diff --git a/.github/workflows/greentea_cmake.yml b/.github/workflows/greentea_cmake.yml index 2455dbb582..0d72453693 100644 --- a/.github/workflows/greentea_cmake.yml +++ b/.github/workflows/greentea_cmake.yml @@ -101,6 +101,12 @@ jobs: profile: full - target: RZ_A1H profile: full + - target: FPB_RA4E1 + profile: full + - target: FPB_RA6E2 + profile: full + - target: FPB_RA8E1 + profile: full # Ambiq MCUs - target: SFE_ARTEMIS_DK diff --git a/CHANGELOG.md b/CHANGELOG.md index 05ad858006..793661c300 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,8 +18,12 @@ A message that notes the main changes in the update. - Added support for Real-Time Transfer (RTT), a method of transferring text from a target device using a debugger connection. RTT allows getting UART console-like behavior at a higher speed and with no additional wires to the target. - RTT can be used automatically by Mbed via the `target.console-rtt` JSON option, or manually in code by linking the `mbed-rtt` CMake library and using the `RTTHandle` class. - RTT is supported in the JLINK, OPENOCD, and PYOCD upload methods. RTT can be used with command-line development and VS Code, but not with CLion at this time. +- Added a new `MBED_NONCACHED` define which can be used to store global variables in non-cached memory on devices with a data cache. This is supported on STM32F7, STM32H7, and MIMXRT (which I believe are the only currently supported MCUs with a D-cache) +- Added a new global, `mbed_used_mpu_regions`, which gives the number of MPU regions used by Mbed. This is intended to allow applications to also use the MPU without creating breakages in the future if Mbed uses additional MPU regions. +- Added new header, `mbed_math_helpers.h`, containing some useful math functions. Currently this contains `mbed_integer_log_2()` and `mbed_is_power_of_two()` +- MIMRT117x: Memory bank configuration is now supported in the linker script. - RP2xxx - - `RASPBERRY_PI_PICO_W` board target added (though note that the wi-fi module on this board is not currently supported, and would take a huge amount of effort to support, so the utility of this board compared to the non-W version is limited). + - `RASPBERRY_PI_PICO_W` board target added (though note that the wi-fi module on this board is not currently supported, and would take a huge amount of effort to support, so the utility of this board with Mbed compared to the non-W version is limited). - `SFE_THING_PLUS_RP2040` board target added for the [SparkFun Thing Plus RP2040 board](https://www.sparkfun.com/sparkfun-thing-plus-rp2040.html) - MPU configuration support added - Support for single-byte i2c operations implemented (allowing features like the I2C EEPROM block device to work). @@ -33,7 +37,8 @@ A message that notes the main changes in the update. - Reworked targets CMake code to only recurse into the subdir for the current target family, which should speed up the CMake configure a bit - The `I2C` class now keeps track of the I2C bus state and prevents you from doing operations that are obviously wrong, such as calling `start()` before `stop()` or calling `write_byte()` before `start()`. Previously these operations would get passed down to the HAL API which may or may not have appropriate error handling for them. - The `I2C` class now detects and rejects attempts to perform a zero-length transaction on hardware which does not support it. -- Use `-Werror=return-type` in the default GCC flags so that a missing return statement in a function becomes a fatal error +- Use `-Werror=return-type` in the default GCC flags so that a missing return statement in a function becomes a fatal error +- On targets with a data cache (`__DCACHE_PRESENT` is defined), one additional MPU region is used to implement the new non-cacheable memory support. - STM32F4 - HAL driver update to `stm32f4xx-hal-driver` v1.8.5 (2025), now integrated as a submodule. - CMSIS device update to `cmsis-device-f4` v2.6.11 (2025), now integrated as a submodule. @@ -50,7 +55,7 @@ A message that notes the main changes in the update. - Standardized ROM names in `cmsis_mcu_descriptions` across STM32F7 targets. - Replaced per-target linker scripts with one common STM32F7 linker script. - Replaced most STM32F7 `system_clock.c` files with one common clock configuration. - - Added target metadata cleanup (`adc-vref`, `hse-value for all F7 targets). + - Added target metadata cleanup (`adc-vref`, `hse-value` for all F7 targets). - Updated STM32F7 config/init files by consolidating Mbed changes with latest upstream templates. Removed unused Ethernet HAL sections from config (Mbed does not use ST Ethernet stack here) - Applied interim local HAL fixes until upstream release includes them: https://github.com/STMicroelectronics/stm32f7xx-hal-driver/issues/23 - F7 Vector table size and vector start is now covered by linker script and all cmsis_nvic.h files were removed @@ -63,6 +68,11 @@ A message that notes the main changes in the update. - The `POWER_ON` reset reason is no longer supported on RP2040 because it could also be [erroneously triggered for non-actual-power-on reasons](https://forums.raspberrypi.com/viewtopic.php?p=2378084), like flashing code through OpenOCD. Mbed now returns the unknown reset reason if this flag is set in HW. - STM32H5/H7 - `mem-size` of lwIP stack increased to 32768 from default 4000 +- ESP32 Wi-Fi driver + - Added tested working modules and their firmware version + - Added note to increase RX buffer size to ensure data integrity and system stability + - Updated code to get RSSI from ESP32 module + ### Deprecated ### Fixed diff --git a/TESTS/configs/greentea_full.json5 b/TESTS/configs/greentea_full.json5 index 039bffeacc..2592c8636d 100644 --- a/TESTS/configs/greentea_full.json5 +++ b/TESTS/configs/greentea_full.json5 @@ -36,6 +36,7 @@ // This assumes that such boards (e.g. RASPBERRY_PI_PICO) have an external USB-serial // adapter connected. "target.console-usb": false, - "target.console-uart": true + "target.console-uart": true, + "target.console-rtt": false } } diff --git a/cmsis/device/rtos/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c b/cmsis/device/rtos/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c index edf5a2d0f5..6b01cd55ba 100644 --- a/cmsis/device/rtos/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c +++ b/cmsis/device/rtos/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c @@ -88,7 +88,18 @@ void mbed_toolchain_init() env_mutex_id = osMutexNew(&env_mutex_attr); /* Run the C++ global object constructors */ +#ifndef TARGET_MCU_RA __libc_init_array(); +#else + // workaround: __libc_init_array() crashes on Renesas RA MCUs + extern void (* __init_array_start[])(void); + extern void (* __init_array_end[])(void); + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } +#endif } extern int __real_main(void); diff --git a/connectivity/drivers/wifi/COMPONENT_ESPRESSIF_ESP32/ESP32/ESP32.cpp b/connectivity/drivers/wifi/COMPONENT_ESPRESSIF_ESP32/ESP32/ESP32.cpp index 9b2400bcb3..a4e8e85dff 100644 --- a/connectivity/drivers/wifi/COMPONENT_ESPRESSIF_ESP32/ESP32/ESP32.cpp +++ b/connectivity/drivers/wifi/COMPONENT_ESPRESSIF_ESP32/ESP32/ESP32.cpp @@ -624,31 +624,34 @@ const char *ESP32::getNetmask_ap() int8_t ESP32::getRSSI() { - bool ret; - int8_t rssi[2]; /* It needs 1 byte extra. */ + // Practically we only care about RSSI when a station is actually connected to AP + // The way AT+CWLAP operates has also changed since ESP8266 era therefore deprecated + // If we ever want to see the RSSI of AP with certain SSID + // Please parse a SSID str here then issue command: AT+CWLAP="SSID" + // Typical response will be: + // +CWLAP:(,<"ssid">,,<"mac">,,,,,,,) + int rssi = -128/* the least possible RSSI value */; + if (!isConnected()) { + return rssi; + } + + // The following 3 variables are not actually needed + // Declared to faciliate parsing + // Typical response to AT+CWJAP? + // +CWJAP:<"ssid">,<"bssid">,,,,,,, char ssid[33]; char bssid[18]; + int elements[6]; + bool ret; _smutex.lock(); _startup_wifi(); ret = _parser.send("AT+CWJAP?") - && _parser.recv("+CWJAP:\"%32[^\"]\",\"%17[^\"]\"", ssid, bssid) - && _parser.recv("OK"); - if (!ret) { - _smutex.unlock(); - return 0; - } - - ret = _parser.send("AT+CWLAP=\"%s\",\"%s\"", ssid, bssid) - && _parser.recv("+CWLAP:(%*d,\"%*[^\"]\",%hhd,", &rssi[0]) + && _parser.recv("+CWJAP:\"%32[^\"]\",\"%17[^\"]\",%d,%d,%d,%d,%d,%d,%d", ssid, bssid, &elements[0], &rssi, &elements[1], &elements[2], &elements[3], &elements[4], &elements[5]) && _parser.recv("OK"); _smutex.unlock(); - if (!ret) { - return 0; - } - - return rssi[0]; + return ret ? rssi : -128; } int ESP32::scan(WiFiAccessPoint *res, unsigned limit) diff --git a/connectivity/drivers/wifi/COMPONENT_ESPRESSIF_ESP32/README.md b/connectivity/drivers/wifi/COMPONENT_ESPRESSIF_ESP32/README.md index b27739ae61..c0840b0090 100644 --- a/connectivity/drivers/wifi/COMPONENT_ESPRESSIF_ESP32/README.md +++ b/connectivity/drivers/wifi/COMPONENT_ESPRESSIF_ESP32/README.md @@ -2,11 +2,21 @@ The Mbed OS driver for the ESP32 WiFi module. ## Firmware version -How to write mbed-os compatible firmware for GR-LCYHEE and GR-PEACH. -https://github.com/d-kato/GR-Boards_ESP32_Serial_Bridge +The following ESP32 modules and firmware versions have been tested working: ESP32-WROOM-32-AT-V3.4.0.0, ESP32-S2-MINI_AT_Bin_V2.1.0.0, ESP32-S2-MINI-AT-V3.4.0.0, ESP32-S2-MINI-AT-V4.1.1.0, ESP32-S2-MINI-AT-V4.2.0.0, ESP32-C5-AT-v5.0.0.0, ESP32-C5-AT-v5.0.1.0 ## Mbed OS BLE stack using ESP32 You can use the Mbed OS BLE stack with ESP32 by using [esp32-at-ble-stack.lib](https://github.com/d-kato/esp32-at-ble-stack). ## Restrictions - Setting up an UDP server is not possible + +## Note: +Please consider increasing the size of RX buffer of BufferedSerial class that underpins this driver if one of the following use cases are involved: +- ESP32 is used to download large files +- HTTPS is used +- Concurrent HTTP/HTTPS and other network requests such as WS/WSS +- Other thread(s) with higher priority may hog CPU for longer time than it takes to fillup RX buffer +The default RX buffer is limited at 256. Data might be lost while your system is busy handling other tasks. This may even make system unstable. To increase the RX buffer size of BufferedSerial class, please add the following entry into the `target_overrides` section of `mbed_app.json5`, either globally or a particular target. +``` +"drivers.uart-serial-rxbuf-size": 2048, +``` diff --git a/doxyfile_options b/doxyfile_options index c914aa1c39..1f126b8f9c 100644 --- a/doxyfile_options +++ b/doxyfile_options @@ -2356,7 +2356,8 @@ PREDEFINED = DOXYGEN_ONLY \ BLE_FEATURE_WHITELIST=1 \ BLE_FEATURE_PRIVACY=1 \ BLE_FEATURE_PERIODIC_ADVERTISING=1 \ - BLE_FEATURE_EXTENDED_ADVERTISING=1 + BLE_FEATURE_EXTENDED_ADVERTISING=1 \ + __DCACHE_PRESENT=1 # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this # tag can be used to specify a list of macro names that should be expanded. The diff --git a/features/frameworks/rtt/RTTHandle.h b/features/frameworks/rtt/RTTHandle.h index adf3fbe31c..aee1a5b532 100644 --- a/features/frameworks/rtt/RTTHandle.h +++ b/features/frameworks/rtt/RTTHandle.h @@ -75,8 +75,8 @@ class RTTHandle : public FileHandle { * @param down_buffer_size Size of the down buffer in bytes. * @param name Optional name to give this channel. * - * @warning On targets with a data cache, the up and down buffer memory needs to be declared in the section - * defined by \c SEGGER_RTT_SECTION, or otherwise placed into non-cachable memory. The same is true for + * @warning On targets with a data cache, the up and down buffer memory needs to be declared as \c MBED_NONCACHED , + * or otherwise placed into non-cachable memory. The same is true for * \c name if it is not a string constant in flash. */ RTTHandle(unsigned int buffer_index, char * up_buffer, size_t up_buffer_size, char * down_buffer, size_t down_buffer_size, char const * name = nullptr); diff --git a/features/frameworks/rtt/SEGGER_RTT_Conf.h b/features/frameworks/rtt/SEGGER_RTT_Conf.h index 3196f6e50a..ef6390a9f8 100644 --- a/features/frameworks/rtt/SEGGER_RTT_Conf.h +++ b/features/frameworks/rtt/SEGGER_RTT_Conf.h @@ -21,6 +21,7 @@ #ifndef __ASSEMBLER__ #include "device.h" // for __DCACHE_PRESENT #include "mbed_critical.h" +#include "mbed_toolchain.h" #endif // Buffer counts and sizes @@ -38,6 +39,7 @@ // Cache setup #if __DCACHE_PRESENT // NOTE: On targets with a data cache, the RTT control block and buffers must be put in an uncached section of memory. -// This requires that the linker script contain logic to place the ".rtt" section. -#define SEGGER_RTT_SECTION ".rtt" +// This requires that the linker script contain logic to place the ".noncached" section. +#define SEGGER_RTT_SECTION MBED_NONCACHED_SECTION_NAME +#define SEGGER_RTT_BUFFER_SECTION MBED_NONCACHED_SECTION_NAME #endif diff --git a/features/frameworks/rtt/mbed_lib.json5 b/features/frameworks/rtt/mbed_lib.json5 index 97dcb1878a..db1299d139 100644 --- a/features/frameworks/rtt/mbed_lib.json5 +++ b/features/frameworks/rtt/mbed_lib.json5 @@ -12,6 +12,32 @@ "max-channels": { help: "Maximum number of channels supported by RTT. This controls the size of some static arrays within the RTT code. Note that this does NOT, by itself, allocate space for the buffers.", value: 3 + }, + "cb-search-range-start": { + help: "Override the start (first address) of the search range that will be used when a debugger searches for the RTT control block.", + value: null + }, + "cb-search-range-end": { + help: "Override the end (last address) of the search range that will be used when a debugger searches for the RTT control block.", + value: null + } + }, + target_overrides: { + "MCU_STM32H7": { + // STM32H7 has an ITCM bank at address 0, which then causes OpenOCD to fault out when searching for the RTT control + // block between the end of that bank and the start of the next one. So, manually target SRAM_D1 + "cb-search-range-start": 0x24000000, + "cb-search-range-end": 0x2407FFFF + }, + "MIMXRT105X": { + // RTT lives in DTCM + "cb-search-range-start": 0x20000000, + "cb-search-range-end": 0x2023FFFF + }, + "MIMXRT1170": { + // RTT lives in OCRAM combined + "cb-search-range-start": 0x20240000, + "cb-search-range-end": 0x2035FFFF } } } \ No newline at end of file diff --git a/hal/include/hal/mpu_api.h b/hal/include/hal/mpu_api.h index 3905b1aaf2..2178399343 100644 --- a/hal/include/hal/mpu_api.h +++ b/hal/include/hal/mpu_api.h @@ -22,6 +22,9 @@ #include "device.h" #include +#include "cmsis.h" + +#include #ifdef __cplusplus extern "C" { @@ -60,6 +63,55 @@ extern "C" { * mbed test -t -m -n tests-mbed_hal-mpu* */ +#if !defined(MBED_MPU_CUSTOM) + +#ifdef MBED_CONF_TARGET_MPU_ROM_END +#define MBED_MPU_ROM_END MBED_CONF_TARGET_MPU_ROM_END +#else +#define MBED_MPU_ROM_END (0x10000000 - 1) +#endif + +#ifdef MBED_CONF_TARGET_MPU_RAM_START +#define MBED_MPU_RAM_START MBED_CONF_TARGET_MPU_RAM_START +#else +// Default to the end of ROM +#define MBED_MPU_RAM_START (MBED_MPU_ROM_END + 1) +#endif + +#if ((__ARM_ARCH_8M_BASE__ == 1U) || (__ARM_ARCH_8M_MAIN__ == 1U) || (__ARM_ARCH_8_1M_MAIN__ == 1U)) +/// On ARMv8 cores, MPU regions must use one of 8 global "attribute registers", which give the attributes +/// for one or more memory regions. This enum gives the attribute registers (i.e. the first arg to +/// \c ARM_MPU_SetMemAttr() ) that are defined by Mbed. +/// The application is free to use attribute registers above this number. +enum mbed_mpu_attr_index { + /// Normal memory, write-through (i.e. writes are always sent immediately to main memory) + MBED_MPU_ATTR_INDEX_NORMAL_WRITE_THROUGH = 0, + + /// Normal memory, write-back (i.e. writes may only write to the cache immediately, and get synced to main memory later) + MBED_MPU_ATTR_INDEX_NORMAL_WRITE_BACK = 1, + + /// Non-cacheable: Reads and writes hit main memory directly. + /// Note that this is still normal memory, not device, so the CPU can still reorder accesses. + MBED_MPU_ATTR_INDEX_NON_CACHEABLE = 2, +}; +#endif + +/// Number of MPU regions that will be used by Mbed OS's MPU configuration. +/// The application is generally free to use regions above this number. +static MSTD_CONSTEXPR_OBJ_11 size_t mbed_used_mpu_regions = +#if ((__ARM_ARCH_8M_BASE__ == 1U) || (__ARM_ARCH_8M_MAIN__ == 1U) || (__ARM_ARCH_8_1M_MAIN__ == 1U)) + 4 +#else + 3 +#endif +#if MBED_MPU_RAM_START < 0x20000000 + + 1 +#endif +#if __DCACHE_PRESENT + + 1 +#endif + ; +#endif /** * Initialize the MPU @@ -78,9 +130,9 @@ void mbed_mpu_init(void); * * By default writes to ROM are disabled. * - * @param enable true to disable writes to ROM, false otherwise + * @param disable true to disable writes to ROM, false otherwise */ -void mbed_mpu_enable_rom_wn(bool enable); +void mbed_mpu_enable_rom_wn(bool disable); /** * Enable or disable ram MPU protection @@ -90,9 +142,9 @@ void mbed_mpu_enable_rom_wn(bool enable); * * By default execution from RAM is disabled. * - * @param enable true to disable execution from RAM, false otherwise + * @param disable true to disable execution from RAM, false otherwise */ -void mbed_mpu_enable_ram_xn(bool enable); +void mbed_mpu_enable_ram_xn(bool disable); /** Deinitialize the MPU * diff --git a/hal/source/mpu/mbed_mpu_v7m.c b/hal/source/mpu/mbed_mpu_v7m.c index 39a8bd4b0c..983c528ca9 100644 --- a/hal/source/mpu/mbed_mpu_v7m.c +++ b/hal/source/mpu/mbed_mpu_v7m.c @@ -18,6 +18,8 @@ #include "platform/mbed_assert.h" #include "cmsis.h" +#include + #if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_6M__ == 1U)) && \ defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) && \ !defined(MBED_MPU_CUSTOM) @@ -26,19 +28,21 @@ #error "Device has v7m MPU but it is not enabled. Add 'MPU' to device_has in targets.json" #endif -#ifdef MBED_CONF_TARGET_MPU_ROM_END -#define MBED_MPU_ROM_END MBED_CONF_TARGET_MPU_ROM_END -#else -#define MBED_MPU_ROM_END (0x10000000 - 1) +#ifdef __DCACHE_PRESENT +// Symbols defined in linker script for noncache region +extern uint8_t __noncached_start[]; +extern uint8_t __noncached_end[]; #endif -#ifdef MBED_CONF_TARGET_MPU_RAM_START -#define MBED_MPU_RAM_START MBED_CONF_TARGET_MPU_RAM_START -#else -// Default to the end of ROM -#define MBED_MPU_RAM_START (MBED_MPU_ROM_END + 1) +#ifdef MBED_MPU_HAS_RAM_FUNCTION_REGION +// Symbols defined in linker script for ram function region. +// This region may be contained inside any other RAM region. Its start address and size must +// be 32-byte aligned. +extern uint8_t __ram_code_start[]; +extern uint8_t __ram_code_end[]; #endif + static_assert( MBED_MPU_ROM_END == 0x04000000 - 1 || MBED_MPU_ROM_END == 0x08000000 - 1 || @@ -59,11 +63,7 @@ void mbed_mpu_init() // Our MPU setup requires 3 or 4 regions - if this assert is hit, remove // a region by setting MPU_ROM_END to 0x1fffffff, or remove MPU from device_has -#if MBED_MPU_RAM_START == 0x20000000 - MBED_ASSERT(regions >= 3); -#else - MBED_ASSERT(regions >= 4); -#endif + MBED_ASSERT(regions >= mbed_used_mpu_regions); // Disable the MPU MPU->CTRL = 0; @@ -185,6 +185,63 @@ void mbed_mpu_init() ARM_MPU_REGION_SIZE_512MB) // Size ); + uint8_t next_ram_region = LAST_RAM_REGION + 1; + (void)next_ram_region; // silence unused warning + +#if __DCACHE_PRESENT + ptrdiff_t noncached_region_size = __noncached_end - __noncached_start; + if (noncached_region_size > 0) { + // Check configuration from linker script + MBED_ASSERT(mbed_is_power_of_two(noncached_region_size)); + MBED_ASSERT(((uintptr_t)__noncached_start) % noncached_region_size == 0); + + // Region size constant is the log2 of the region size, offset by 1 + const uint32_t region_size = mbed_integer_log_2(noncached_region_size) - 1; + + // Select region 3/4 and use it for the non-cached region + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + next_ram_region, // Region + ((uintptr_t)__noncached_start)), // Base + ARM_MPU_RASR_EX( + 1, // DisableExec + ARM_MPU_AP_FULL, // AccessPermission + ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_NOCACHE, ARM_MPU_CACHEP_NOCACHE, true), // Access and cache policy + 0U, // SubRegionDisable + region_size) // Size + ); + ++next_ram_region; + } +#endif + +#if MBED_MPU_HAS_RAM_FUNCTION_REGION + ptrdiff_t ram_code_region_size = __ram_code_end - __ram_code_start; + if (ram_code_region_size > 0) { + // Check configuration from linker script + MBED_ASSERT(mbed_is_power_of_two(ram_code_region_size)); + MBED_ASSERT(((uintptr_t)__ram_code_start) % ram_code_region_size == 0); + + // Region size constant is the log2 of the region size, offset by 1 + const uint32_t region_size = mbed_integer_log_2(ram_code_region_size) - 1; + + // Select region 3/4/5 and use it for the ram code region. + // Note that some target layers, like the RPi Pico SDK, actually modify the code in this section + // at runtime (e.g. for interrupt handler redirection). So, we cannot mark it read-only. + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + next_ram_region, // Region + ((uintptr_t)__ram_code_start)), // Base + ARM_MPU_RASR_EX( + 0, // DisableExec + ARM_MPU_AP_FULL, // AccessPermission + ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_WB_WRA, ARM_MPU_CACHEP_WB_WRA, false), // Access and cache policy + 0U, // SubRegionDisable + region_size) // Size + ); + ++next_ram_region; + } +#endif + // Enable the MPU MPU->CTRL = (1 << MPU_CTRL_PRIVDEFENA_Pos) | // Use the default memory map for unmapped addresses @@ -215,25 +272,25 @@ static void enable_region(bool enable, uint32_t region) MPU->RASR = (MPU->RASR & ~MPU_RASR_ENABLE_Msk) | (enable << MPU_RASR_ENABLE_Pos); } -void mbed_mpu_enable_rom_wn(bool enable) +void mbed_mpu_enable_rom_wn(bool disable) { // Flush memory writes before configuring the MPU. __DMB(); - enable_region(enable, 0); + enable_region(disable, 0); // Ensure changes take effect __DSB(); __ISB(); } -void mbed_mpu_enable_ram_xn(bool enable) +void mbed_mpu_enable_ram_xn(bool disable) { // Flush memory writes before configuring the MPU. __DMB(); for (uint32_t region = 1; region <= LAST_RAM_REGION; region++) { - enable_region(enable, region); + enable_region(disable, region); } // Ensure changes take effect diff --git a/hal/source/mpu/mbed_mpu_v8m.c b/hal/source/mpu/mbed_mpu_v8m.c index ec09dbe41d..507c111f77 100644 --- a/hal/source/mpu/mbed_mpu_v8m.c +++ b/hal/source/mpu/mbed_mpu_v8m.c @@ -39,6 +39,22 @@ #define MBED_MPU_RAM_START (MBED_MPU_ROM_END + 1) #endif +#ifdef __DCACHE_PRESENT +// Symbols defined in linker script for noncache region. +// The region's size does not need to be a power of 2, but its size and address need to be +// 32-byte aligned. It must either be after the end of normal RAM, or before the start. +extern uint8_t __noncached_start[]; +extern uint8_t __noncached_end[]; +#endif + +#ifdef MBED_MPU_HAS_RAM_FUNCTION_REGION +// Symbols defined in linker script for ram function region. +// The region's size does not need to be a power of 2, but its size and address need to be +// 32-byte aligned. It must either be after the end of normal RAM, or before the start. +extern uint8_t __ram_code_start[]; +extern uint8_t __ram_code_end[]; +#endif + static_assert(MBED_MPU_ROM_END <= 0x20000000 - 1, "Unsupported value for MBED_MPU_ROM_END"); @@ -49,13 +65,9 @@ void mbed_mpu_init() const uint32_t regions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; - // Our MPU setup requires 4 or 5 regions - if this assert is hit, remove + // Our MPU setup requires 4-6 regions - if this assert is hit, remove // a region by setting MPU_ROM_END to 0x1fffffff, or remove MPU from device_has -#if MBED_MPU_RAM_START == 0x20000000 - MBED_ASSERT(regions >= 4); -#else - MBED_ASSERT(regions >= 5); -#endif + MBED_ASSERT(regions >= mbed_used_mpu_regions); // Disable the MCU MPU->CTRL = 0; @@ -81,13 +93,10 @@ void mbed_mpu_init() const uint8_t WTRA = ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0); // Non-transient, Write-Through, Read-allocate, Not Write-allocate const uint8_t WBWARA = ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1); // Non-transient, Write-Back, Read-allocate, Write-allocate - enum { - AttrIndex_WTRA, - AttrIndex_WBWARA, - }; - ARM_MPU_SetMemAttr(AttrIndex_WTRA, ARM_MPU_ATTR(WTRA, WTRA)); - ARM_MPU_SetMemAttr(AttrIndex_WBWARA, ARM_MPU_ATTR(WBWARA, WBWARA)); + ARM_MPU_SetMemAttr(MBED_MPU_ATTR_INDEX_NORMAL_WRITE_THROUGH, ARM_MPU_ATTR(WTRA, WTRA)); + ARM_MPU_SetMemAttr(MBED_MPU_ATTR_INDEX_NORMAL_WRITE_BACK, ARM_MPU_ATTR(WBWARA, WBWARA)); + ARM_MPU_SetMemAttr(MBED_MPU_ATTR_INDEX_NON_CACHEABLE, ARM_MPU_ATTR(MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE, MPU_ATTR_NORMAL_INNER_NON_CACHEABLE)); ARM_MPU_SetRegion( 0, // Region @@ -99,38 +108,50 @@ void mbed_mpu_init() 0), // Execute Never disabled ARM_MPU_RLAR( MBED_MPU_ROM_END, // Limit - AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate + MBED_MPU_ATTR_INDEX_NORMAL_WRITE_THROUGH) // Attribute index - Write-Through, Read-allocate ); -#if MBED_MPU_RAM_START != 0x20000000 - ARM_MPU_SetRegion( - 4, // Region - ARM_MPU_RBAR( - MBED_MPU_RAM_START, // Base - ARM_MPU_SH_NON, // Non-shareable - 0, // Read-Write - 1, // Non-Privileged - 1), // Execute Never enabled - ARM_MPU_RLAR( - 0x1FFFFFFF, // Limit - AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate - ); -#define LAST_RAM_REGION 4 -#else -#define LAST_RAM_REGION 3 + // MBED_MPU_RAM_START contains the start of the physical RAM address range on the chip. + // However, because MPU regions cannot overlap, we may need to adjust the RAM region addresses + // to account for the noncached and ram_code regions. + uintptr_t sram_region_start = MBED_MPU_RAM_START; + uintptr_t sram_region_limit = 0x3FFFFFFF; +#if __DCACHE_PRESENT + if (((uintptr_t)__noncached_end <= sram_region_start) || ((uintptr_t)__noncached_start > sram_region_limit)) { + // OK - noncached region outside normal SRAM + } else if ((uintptr_t)__noncached_start == sram_region_start) { + // OK - noncached region at start of SRAM. Move sram start back. + sram_region_start = (uintptr_t)__noncached_end; + } else { + // Assume noncached region at end of SRAM. + sram_region_limit = (uintptr_t)__noncached_start - 1; + } +#endif +#if MBED_MPU_HAS_RAM_FUNCTION_REGION + if (((uintptr_t)__ram_code_end <= sram_region_start) || ((uintptr_t)__ram_code_start > sram_region_limit)) { + // OK - ram_code region outside normal SRAM + } else if ((uintptr_t)__ram_code_start == sram_region_start) { + // OK - ram_code region at start of SRAM. Move sram start back. + sram_region_start = (uintptr_t)__ram_code_end; + } else { + // Assume ram_code region at end of SRAM. + sram_region_limit = (uintptr_t)__ram_code_start - 1; + } #endif +#define LAST_RAM_REGION 3 + ARM_MPU_SetRegion( 1, // Region ARM_MPU_RBAR( - 0x20000000, // Base + sram_region_start, // Base ARM_MPU_SH_NON, // Non-shareable 0, // Read-Write 1, // Non-Privileged 1), // Execute Never enabled ARM_MPU_RLAR( - 0x3FFFFFFF, // Limit - AttrIndex_WBWARA) // Attribute index - Write-Back, Write-allocate + sram_region_limit, // Limit + MBED_MPU_ATTR_INDEX_NORMAL_WRITE_BACK) // Attribute index - Write-Back, Write-allocate ); ARM_MPU_SetRegion( @@ -143,7 +164,7 @@ void mbed_mpu_init() 1), // Execute Never enabled ARM_MPU_RLAR( 0x7FFFFFFF, // Limit - AttrIndex_WBWARA) // Attribute index - Write-Back, Write-allocate + MBED_MPU_ATTR_INDEX_NORMAL_WRITE_BACK) // Attribute index - Write-Back, Write-allocate ); ARM_MPU_SetRegion( @@ -156,8 +177,52 @@ void mbed_mpu_init() 1), // Execute Never enabled ARM_MPU_RLAR( 0x9FFFFFFF, // Limit - AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate + MBED_MPU_ATTR_INDEX_NORMAL_WRITE_THROUGH) // Attribute index - Write-Through, Read-allocate + ); + + uint8_t next_ram_region = LAST_RAM_REGION + 1; + (void)next_ram_region; // silence unused warning + +#if __DCACHE_PRESENT + // Region addresses must be 32-byte aligned. + MBED_ASSERT(((uintptr_t)__noncached_start) % 32 == 0); + MBED_ASSERT(((uintptr_t)__noncached_end) % 32 == 0); + + // Select region 4 and use it for the non-cached region + ARM_MPU_SetRegion( + next_ram_region, + ARM_MPU_RBAR( + (uintptr_t)__noncached_start,// Base + ARM_MPU_SH_OUTER, // Sharability + 0, // Read-Write + 1, // Non-privileged + 1), // Execute Never + ARM_MPU_RLAR( + (uintptr_t)__noncached_end - 1, // Limit + MBED_MPU_ATTR_INDEX_NON_CACHEABLE) ); + ++next_ram_region; +#endif + +#if MBED_MPU_HAS_RAM_FUNCTION_REGION + // Region addresses must be 32-byte aligned. + MBED_ASSERT(((uintptr_t)__ram_code_start) % 32 == 0); + MBED_ASSERT(((uintptr_t)__ram_code_end) % 32 == 0); + + // Select region 4/5 and use it for the non-cached region + ARM_MPU_SetRegion( + next_ram_region, + ARM_MPU_RBAR( + (uintptr_t)__ram_code_start, // Base + ARM_MPU_SH_NON, // Sharability + 0, // Read-Write + 1, // Non-privileged + 0), // Execute Never disabled + ARM_MPU_RLAR( + (uintptr_t)__ram_code_end - 1, // Limit + MBED_MPU_ATTR_INDEX_NORMAL_WRITE_THROUGH) + ); +#endif // Enable the MPU MPU->CTRL = @@ -189,25 +254,25 @@ static void enable_region(bool enable, uint32_t region) MPU->RLAR = (MPU->RLAR & ~MPU_RLAR_EN_Msk) | (enable << MPU_RLAR_EN_Pos); } -void mbed_mpu_enable_rom_wn(bool enable) +void mbed_mpu_enable_rom_wn(bool disable) { // Flush memory writes before configuring the MPU. __DMB(); - enable_region(enable, 0); + enable_region(disable, 0); // Ensure changes take effect __DSB(); __ISB(); } -void mbed_mpu_enable_ram_xn(bool enable) +void mbed_mpu_enable_ram_xn(bool disable) { // Flush memory writes before configuring the MPU. __DMB(); for (uint32_t region = 1; region <= LAST_RAM_REGION; region++) { - enable_region(enable, region); + enable_region(disable, region); } // Ensure changes take effect diff --git a/hal/tests/TESTS/mbed_hal/stack_size_unification/main.cpp b/hal/tests/TESTS/mbed_hal/stack_size_unification/main.cpp index 8d125a76a3..a976734aab 100644 --- a/hal/tests/TESTS/mbed_hal/stack_size_unification/main.cpp +++ b/hal/tests/TESTS/mbed_hal/stack_size_unification/main.cpp @@ -20,7 +20,7 @@ #include "unity.h" #include "utest.h" -#ifdef TARGET_RENESAS +#if defined(TARGET_RENESAS) && !defined(TARGET_RA) #error [NOT_SUPPORTED] Cortex-A target not supported for this test #else diff --git a/platform/cxxsupport/mstd_cstddef b/platform/cxxsupport/mstd_cstddef index cbba89eb50..2816c94273 100644 --- a/platform/cxxsupport/mstd_cstddef +++ b/platform/cxxsupport/mstd_cstddef @@ -59,6 +59,8 @@ using std::max_align_t; #else // __cplusplus +#include + #define MSTD_CONSTEXPR_FN_14 inline #define MSTD_CONSTEXPR_OBJ_14 const #define MSTD_CONSTEXPR_FN_11 inline diff --git a/platform/include/platform/mbed_math_helpers.h b/platform/include/platform/mbed_math_helpers.h new file mode 100644 index 0000000000..c09396c04c --- /dev/null +++ b/platform/include/platform/mbed_math_helpers.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * Copyright (c) 2026 Jamie Smith + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include + +/** + * @brief Check whether an integer is an exact power of two. + */ +// from https://stackoverflow.com/a/600306/7083698 +static inline bool mbed_is_power_of_two(const uint32_t x) +{ + return x > 0 && (x & (x - 1)) == 0; +} + +/** + * @brief Get the log2 of an integer. + * + * Rounds down to the nearest power of 2, i.e. \c mbed_integer_log_2(3) is 1. + */ +static inline uint32_t mbed_integer_log_2(uint32_t x) +{ + return sizeof(uint32_t) * 8 - 1 - __builtin_clz(x); +} diff --git a/platform/include/platform/mbed_toolchain.h b/platform/include/platform/mbed_toolchain.h index f9c016ab8e..0cc06c0b10 100644 --- a/platform/include/platform/mbed_toolchain.h +++ b/platform/include/platform/mbed_toolchain.h @@ -45,6 +45,8 @@ #warning "This compiler is not yet supported." #endif +#include "cmsis.h" + /** \addtogroup platform-public-api */ /** @{*/ @@ -474,6 +476,19 @@ #define MBED_PRETTY_FUNCTION __PRETTY_FUNCTION__ #endif +#if __DCACHE_PRESENT +/// Name of the section where non-cached data is stored. +#define MBED_NONCACHED_SECTION_NAME ".noncached" + +/// Attach to a global variable to put it in the noncached section. +/// Note that this section is always zero-initialized at boot, and any initial value assigned to +/// noncached values is ignored. +#define MBED_NONCACHED MBED_SECTION(MBED_NONCACHED_SECTION_NAME) +#else +// empty define for compatibility +#define MBED_NONCACHED +#endif + #ifndef MBED_PRINTF #if defined(__GNUC__) #define MBED_PRINTF(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx, first_param_idx))) diff --git a/platform/source/mbed_wait_api_no_rtos.c b/platform/source/mbed_wait_api_no_rtos.c index b3228dcf68..92592fa5fd 100644 --- a/platform/source/mbed_wait_api_no_rtos.c +++ b/platform/source/mbed_wait_api_no_rtos.c @@ -89,6 +89,10 @@ void wait_us(int us) // (The NOPs were added to stabilise this - with just the SUB and BCS, it seems that the // M7 sometimes takes 1 cycle, sometimes 2, possibly depending on alignment) #define LOOP_SCALER 2000 +#elif __CORTEX_M == 85 +// Cortex-M85 features advanced dual-issue superscalar pipeline and branch prediction, +// taking approx 1.33 cycles per iteration with this loop sequence. +#define LOOP_SCALER 1333 #endif #elif defined __CORTEX_A #if __CORTEX_A == 9 || __CORTEX_A == 5 diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld index a3191c4699..094dc76f6a 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld @@ -76,6 +76,25 @@ M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE; SECTIONS { + /* Non-cached data section. + * This section is configured in the MPU as uncached, so reads and writes go directly through to memory. + * We put this first in SRAM so it's very, very aligned. */ + .noncached (NOLOAD): + { + __noncached_start = .; + *(.noncached) + + /* For the MPU configuration, we need to align the size of this section up to + * the next power of two. Also note that the MPU does not support regions + * smaller than 32 bytes so round up if smaller than that. */ + __noncached_data_size = (. - __noncached_start); + __noncached_aligned_size = MAX(32, 1 << LOG2CEIL(__noncached_data_size)); + + . += (__noncached_aligned_size - __noncached_data_size); + + __noncached_end = .; + } > RAM + .isr_vector : { __vector_table = .; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld index a38d33ea08..01922b7745 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld @@ -282,6 +282,7 @@ SECTIONS .ncache : { *(NonCacheable) + *(.noncached) . = ALIGN(8); __noncachedata_end__ = .; /* define a global symbol at ncache data end */ } > m_dtcm :ram_ncache_noinit diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mbed_overrides.c index d47a72e943..246a6c93b2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mbed_overrides.c @@ -28,6 +28,9 @@ #include "us_ticker_api.h" #include "flash_api.h" +#include +#include + #if DEVICE_FLASH #include "mimxrt_flash_api.h" #endif @@ -43,6 +46,10 @@ uint8_t mbed_otp_mac_address(char *mac); void mbed_default_mac_address(char *mac); +// Symbols defined in linker script for noncache region +extern uint8_t __noncached_start[]; +extern uint8_t __noncached_end[]; + /* MPU configuration. */ void BOARD_ConfigMPU(void) { @@ -127,8 +134,6 @@ void BOARD_ConfigMPU(void) #endif - - /* The define sets the cacheable memory to shareable, * this suggestion is referred from chapter 2.2.1 Memory regions, * types and attributes in Cortex-M7 Devices, Generic User Guide */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/mbed_overrides.c index 7b0c81459e..f5c916bc35 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/mbed_overrides.c @@ -21,7 +21,12 @@ #include "fsl_gpio.h" #include "fsl_xbara.h" +#include +#include +// Symbols defined in linker script for noncache region +extern uint8_t __noncachedata_start__[]; +extern uint8_t __noncachedata_end__[]; void BOARD_ConfigMPU(void) { @@ -37,66 +42,85 @@ void BOARD_ConfigMPU(void) SCB_DisableDCache(); } -ARM_MPU_Disable(); + ARM_MPU_Disable(); + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + */ /* Region 0 setting: No data access permission. */ MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); - /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable (SEMC0-SEMC1) */ MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - - /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. (CAAM Secure RAM, FlexSPI1 control registers) */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x00000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); - /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back (ITCM) */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); - /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back (DTCM) */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x20000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); - /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back (CM4 TCM, OCRAM1, OCRAM2) */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20200000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB); - /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back (ORCAM1 ECC, OCRAM2 ECC, OCRAM M7) */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20300000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); - /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ + /* Region 7: Noncached memory. */ + ptrdiff_t noncached_region_size = __noncachedata_end__ - __noncachedata_start__; + if(noncached_region_size > 0) { + // Check configuration from linker script + MBED_ASSERT(mbed_is_power_of_two(noncached_region_size)); + MBED_ASSERT(((uintptr_t)__noncachedata_start__) % noncached_region_size == 0); + + // Region size constant is the log2 of the region size, offset by 1 + const uint32_t region_size = mbed_integer_log_2(noncached_region_size) - 1; + + MPU->RBAR = ARM_MPU_RBAR(7, ((uintptr_t)__noncachedata_start__)); + MPU->RASR = + ARM_MPU_RASR_EX( + 1, // DisableExec + ARM_MPU_AP_FULL, // AccessPermission + ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_NOCACHE, ARM_MPU_CACHEP_NOCACHE, true), // Access and cache policy + 0U, // SubRegionDisable + region_size); // Size + } + + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. (FlexSPI1) */ MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); - - /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */ + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back (SEMC0) */ MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); - /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */ + /* Region 11 setting: Memory with Device type, not shareable, non-cacheable (AIPS peripherals) */ MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB); - /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */ + /* Region 12 setting: Memory with Device type, not shareable, non-cacheable (SIM_M/SIM_DISP) */ MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); - /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */ + /* Region 13 setting: Memory with Device type, not shareable, non-cacheable (SIM_M7) */ MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); - /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */ + /* Region 14 setting: Memory with Device type, not shareable, non-cacheable (GPU2D) */ MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); - /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */ + /* Region 15 setting: Memory with Device type, not shareable, non-cacheable (AIPS M7) */ MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h index 36b24fe989..a4a791476a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h @@ -439,7 +439,10 @@ typedef enum IRQn { #define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ + +#ifndef __FPU_PRESENT #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#endif #include "core_cm7.h" /* Core Peripheral Access Layer */ #include "system_MIMXRT1176_cm7.h" /* Device specific configuration file */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld index 001599a2ce..28f84d1744 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld @@ -29,12 +29,12 @@ ENTRY(Reset_Handler) __ram_vector_table__ = 1; -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x30000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x1000000 +/* If we are not configured to execute out of the start of ROM, then a bootloader is + * present. This tells us whether we need to add the Flash Configuration Field at the start of flash. */ +#if MBED_CONFIGURED_ROM_BANK_EXT_FLASH_START == MBED_ROM_BANK_EXT_FLASH_START +#define IS_BOOTLOADER_PRESENT 0 +#else +#define IS_BOOTLOADER_PRESENT 1 #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -49,56 +49,70 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; /* Specify the memory areas */ MEMORY { -#if !defined(MBED_APP_COMPILE) - m_flash_config (RX) : ORIGIN = MBED_APP_START + 0x0400, LENGTH = 0x00000C00 - m_ivt (RX) : ORIGIN = MBED_APP_START + 0x1000, LENGTH = 0x00001000 - m_interrupts (RX) : ORIGIN = MBED_APP_START + 0x2000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = MBED_APP_START + 0x2400, LENGTH = MBED_APP_SIZE - 0x2400 -#else - m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400 + m_text (RX) : ORIGIN = MBED_CONFIGURED_ROM_BANK_EXT_FLASH_START, LENGTH = MBED_CONFIGURED_ROM_BANK_EXT_FLASH_SIZE + m_dtcm (RW) : ORIGIN = MBED_RAM_BANK_SRAM_DTC_START, LENGTH = MBED_RAM_BANK_SRAM_DTC_SIZE + m_itcm (RX) : ORIGIN = MBED_RAM_BANK_SRAM_ITC_START, LENGTH = MBED_RAM_BANK_SRAM_ITC_SIZE + + m_ocram_combined (RW) : ORIGIN = MBED_RAM_BANK_SRAM_OC_1_2_COMBINED_START, LENGTH = MBED_RAM_BANK_SRAM_OC_1_2_COMBINED_SIZE + + /* External SDRAM, if available */ +#ifdef MBED_RAM_BANK_SDRAM_SIZE + m_sdram (RW) : ORIGIN = MBED_RAM_BANK_SDRAM_START, LENGTH = MBED_RAM_BANK_SDRAM_SIZE #endif - m_text2 (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000 - m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x03000000 - m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x01000000 - m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00040000 - m_data3 (RW) : ORIGIN = 0x202C0000, LENGTH = 0x00080000 } /* Define output sections */ SECTIONS { -#if !defined(MBED_APP_COMPILE) +#if !defined(IS_BOOTLOADER_PRESENT) + /* Flash config goes first, at the start of flash */ .flash_config : { . = ALIGN(8); __FLASH_BASE = .; KEEP(* (.boot_hdr.conf)) /* flash config section */ . = ALIGN(8); - } > m_flash_config - - ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); + } > m_text - .ivt : AT(ivt_begin) + /* Then IVT at offset 0x1000 */ + .ivt MBED_ROM_BANK_EXT_FLASH_START + 0x1000 : { . = ALIGN(8); KEEP(* (.boot_hdr.ivt)) /* ivt section */ KEEP(* (.boot_hdr.boot_data)) /* boot section */ KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ . = ALIGN(8); - } > m_ivt + } > m_text + /* Note that we do not want to use AT> above, because that would result in this section being + * placed in flash immediately after .flash_config. Instead we don't use AT> to set the LMA equal + * to the VMA. */ + + /* Interrupts go after that */ + #define INTERRUPT_TABLE_ADDR MBED_ROM_BANK_EXT_FLASH_START + 0x2000 +#else + /* We have a bootloader so we don't need the flash config or IVT */ + /DISCARD/ : { + *(.boot_hdr.conf) + *(.boot_hdr.ivt) + *(.boot_hdr.boot_data) + *(.boot_hdr.dcd_data) + } + + /* Interrupts go at the start of configured flash area */ + #define INTERRUPT_TABLE_ADDR MBED_CONFIGURED_ROM_BANK_EXT_FLASH_START #endif + /* The startup code goes first into internal RAM */ - .interrupts : + .interrupts INTERRUPT_TABLE_ADDR : { __VECTOR_TABLE = .; . = ALIGN(8); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(8); - } > m_interrupts + } > m_text - /* The program code and other data goes into internal RAM */ + /* The program code and other data goes into FlexSPI */ .text : { . = ALIGN(8); @@ -196,12 +210,42 @@ SECTIONS . += M_VECTOR_RAM_SIZE; . = ALIGN(8); __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data2 + } > m_dtcm __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; - .data : AT(__DATA_ROM) + /* Note: MIMXRT1170 has a major errata (ERR050396) which causes many DMA-enabled peripherals to be unable to write to + * DTCM. So, we currently do not use DTCM, even though this does hurt performance a fair bit. */ + + /* Non-cached data section. + * This section is configured in the MPU as uncached, so reads and writes go directly through to memory. + * We put this first in OCRAM so it's very, very aligned. */ + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(8); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ocram_combined + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + *(.noncached) + + /* For the MPU configuration, we need to align the size of this section up to + * the next power of two. Also note that the MPU does not support regions + * smaller than 32 bytes so round up if smaller than that. */ + __noncached_data_size = (. - __noncachedata_start__); + __noncached_aligned_size = MAX(32, 1 << LOG2CEIL(__noncached_data_size)); + + . += (__noncached_aligned_size - __noncached_data_size); + + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ocram_combined + + .data : { . = ALIGN(8); __DATA_RAM = .; @@ -212,37 +256,22 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(8); __data_end__ = .; /* define a global symbol at data end */ - } > m_data + } > m_ocram_combined AT> m_text __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */ - .ram_function : AT(__ram_function_flash_start) + .ram_function : { . = ALIGN(32); __ram_function_start__ = .; *(CodeQuickAccess) . = ALIGN(128); __ram_function_end__ = .; - } > m_text2 + } > m_itcm AT> m_text __ram_function_size = SIZEOF(.ram_function); __NDATA_ROM = __ram_function_flash_start + SIZEOF(.ram_function); - .ncache.init : AT(__NDATA_ROM) - { - __noncachedata_start__ = .; /* create a global symbol at ncache data start */ - *(NonCacheable.init) - . = ALIGN(8); - __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_ncache - . = __noncachedata_init_end__; - .ncache : - { - *(NonCacheable) - . = ALIGN(8); - __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_ncache - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); text_end = ORIGIN(m_text) + LENGTH(m_text); ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") @@ -261,7 +290,7 @@ SECTIONS . = ALIGN(8); __bss_end__ = .; __END_BSS = .; - } > m_data + } > m_ocram_combined .heap : { @@ -269,24 +298,24 @@ SECTIONS __end__ = .; PROVIDE(end = .); __HeapBase = .; - . = ORIGIN(m_data) + LENGTH(m_data) - STACK_SIZE; + . = ORIGIN(m_ocram_combined) + LENGTH(m_ocram_combined) - STACK_SIZE; __HeapLimit = .; __heap_limit = .; /* Add for _sbrk */ - } > m_data + } > m_ocram_combined .stack : { . = ALIGN(8); . += STACK_SIZE; - } > m_data + } > m_ocram_combined /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackTop = ORIGIN(m_ocram_combined) + LENGTH(m_ocram_combined); __StackLimit = __StackTop - STACK_SIZE; PROVIDE(__stack = __StackTop); .ARM.attributes 0 : { *(.ARM.attributes) } - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") + ASSERT(__StackLimit >= __HeapLimit, "region m_ocram_combined overflowed with stack and heap") } diff --git a/targets/TARGET_RENESAS/CMakeLists.txt b/targets/TARGET_RENESAS/CMakeLists.txt index 9ee79c9268..ae33b29f1a 100644 --- a/targets/TARGET_RENESAS/CMakeLists.txt +++ b/targets/TARGET_RENESAS/CMakeLists.txt @@ -1,6 +1,7 @@ # Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(TARGET_RA EXCLUDE_FROM_ALL) add_subdirectory(TARGET_RZ_A1XX EXCLUDE_FROM_ALL) add_subdirectory(TARGET_RZ_A2XX EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_RENESAS/TARGET_RA/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RA/CMakeLists.txt new file mode 100644 index 0000000000..67d0d339c5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/CMakeLists.txt @@ -0,0 +1,58 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(TARGET_RA4E1 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_RA6E2 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_RA8E1 EXCLUDE_FROM_ALL) + +add_library(mbed-renesas-ra INTERFACE) + +target_include_directories(mbed-renesas-ra + INTERFACE + . + ./ra/fsp/inc + ./ra/fsp/inc/api + ./ra/fsp/inc/instances + ./ra/fsp/src/bsp/cmsis/Device/RENESAS/Include + ./ra/fsp/src/bsp/mcu/all +) + +target_sources(mbed-renesas-ra + INTERFACE + ./ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c + ./ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c + ./ra/fsp/src/bsp/mcu/all/bsp_clocks.c + ./ra/fsp/src/bsp/mcu/all/bsp_common.c + ./ra/fsp/src/bsp/mcu/all/bsp_delay.c + ./ra/fsp/src/bsp/mcu/all/bsp_group_irq.c + ./ra/fsp/src/bsp/mcu/all/bsp_guard.c + ./ra/fsp/src/bsp/mcu/all/bsp_io.c + ./ra/fsp/src/bsp/mcu/all/bsp_ipc.c + ./ra/fsp/src/bsp/mcu/all/bsp_irq.c + ./ra/fsp/src/bsp/mcu/all/bsp_macl.c + ./ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c + ./ra/fsp/src/bsp/mcu/all/bsp_register_protection.c + ./ra/fsp/src/bsp/mcu/all/bsp_sdram.c + ./ra/fsp/src/bsp/mcu/all/bsp_security.c + gpio_api.c + gpio_irq_api.c + port_api.c + us_ticker.c + analog_api.c + analogout_api.c + trng_api.c + watchdog_api.c + pwmout_api.c + crc_api.c + flash_api.c + rtc_api.c + serial_api.c + spi_api.c + i2c_api.c + can_api.c + reset_reason.c + pinmap.c + mbed_overrides.cpp +) + +target_link_libraries(mbed-renesas-ra INTERFACE mbed-cmsis-cortex-m) diff --git a/targets/TARGET_RENESAS/TARGET_RA/PeripheralPins.h b/targets/TARGET_RENESAS/TARGET_RA/PeripheralPins.h new file mode 100644 index 0000000000..6d771314b1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/PeripheralPins.h @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +//*** GPIO *** +#if GPIO_PINMAP_READY +/* If this macro is defined, then PinMap_GPIO is present in PeripheralPins.c */ +extern const PinMap PinMap_GPIO[]; +#endif + +//*** GPIO IRQ *** +#if DEVICE_INTERRUPTIN +extern const PinMap PinMap_IRQ[]; +#endif + +//*** ADC *** +#if DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +//*** DAC *** +#if DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +//*** I2C *** +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +//*** PWM *** +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM[]; +#endif + +//*** SERIAL *** +#if DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +#if DEVICE_SERIAL_FC +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif +#endif + +//*** SPI *** +#if DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +//*** CAN *** +#if DEVICE_CAN +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; +#endif + +//*** QSPI *** +#if DEVICE_QSPI +extern const PinMap PinMap_QSPI_DATA0[]; +extern const PinMap PinMap_QSPI_DATA1[]; +extern const PinMap PinMap_QSPI_DATA2[]; +extern const PinMap PinMap_QSPI_DATA3[]; +extern const PinMap PinMap_QSPI_SCLK[]; +extern const PinMap PinMap_QSPI_SSEL[]; +#endif + +//*** OSPI *** +#if DEVICE_OSPI +extern const PinMap PinMap_OSPI_DATA0[]; +extern const PinMap PinMap_OSPI_DATA1[]; +extern const PinMap PinMap_OSPI_DATA2[]; +extern const PinMap PinMap_OSPI_DATA3[]; +extern const PinMap PinMap_OSPI_DATA4[]; +extern const PinMap PinMap_OSPI_DATA5[]; +extern const PinMap PinMap_OSPI_DATA6[]; +extern const PinMap PinMap_OSPI_DATA7[]; +extern const PinMap PinMap_OSPI_DQS[]; +extern const PinMap PinMap_OSPI_SCLK[]; +extern const PinMap PinMap_OSPI_SSEL[]; +#endif + +//*** USB *** +#define USE_USB_NO_OTG 0 +#define USE_USB_OTG_FS 1 +#define USE_USB_OTG_HS 2 +#define USE_USB_HS_IN_FS 3 + +#if DEVICE_USBDEVICE +extern const PinMap PinMap_USB_HS[]; +extern const PinMap PinMap_USB_FS[]; +#endif /* DEVICE_USBDEVICE */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/PinNamesTypes.h b/targets/TARGET_RENESAS/TARGET_RA/PinNamesTypes.h new file mode 100644 index 0000000000..2ef71e2ce4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/PinNamesTypes.h @@ -0,0 +1,50 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#define RA_PIN_MODE_ANALOG (0x0U) +#define RA_PIN_MODE_PERIPHERAL_PP (0x1U) +#define RA_PIN_MODE_PERIPHERAL_OD (0x2U) +#define RA_PIN_MODE_IRQ (0x3U) + +#define RA_PIN_PULL_NONE (0x0U) +#define RA_PIN_PULL_UP (0x1U) +#define RA_PIN_PULL_DOWN (0x2U) + +#define RA_PIN_SPEED_LOW (0x0U) +#define RA_PIN_SPEED_MID (0x1U) +#define RA_PIN_SPEED_MID_I2C (0x2U) +#define RA_PIN_SPEED_HS_HIGH (0x2U) +#define RA_PIN_SPEED_HIGH (0x3U) + +#define RA_PIN_DATA(MODE, PULL, ALT) \ + (((MODE) << 28) | \ + ((PULL) << 24) | \ + ((ALT >> 24) << 16)) + +#define RA_PIN_DATA_SPEED(MODE, PULL, ALT, SPEED) \ + (((MODE) << 28) | \ + ((PULL) << 24) | \ + ((SPEED) << 22) | \ + ((ALT >> 24) << 16)) + +#define RA_PIN_DATA_EXT(MODE, PULL, ALT, CHANNEL) \ + (((MODE) << 28) | \ + ((PULL) << 24) | \ + ((ALT >> 24) << 16) | \ + ((CHANNEL) << 8)) + +#define RA_PIN_DATA_EXT_SPEED(MODE, PULL, ALT, CHANNEL, SPEED) \ + (((MODE) << 28) | \ + ((PULL) << 24) | \ + ((SPEED) << 22) | \ + ((ALT >> 24) << 16) | \ + ((CHANNEL) << 8)) + +#define RA_PIN_MODE(FUNC) (((FUNC) >> 28) & 0xF) +#define RA_PIN_PULL(FUNC) (((FUNC) >> 24) & 0xF) +#define RA_PIN_SPEED(FUNC) (((FUNC) >> 22) & 0x3) +#define RA_PIN_ALT(FUNC) (((FUNC) >> 16) & 0x3F) +#define RA_PIN_CHANNEL(FUNC) (((FUNC) >> 8 ) & 0xFF) diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/CMakeLists.txt new file mode 100644 index 0000000000..e2689cfa81 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/CMakeLists.txt @@ -0,0 +1,243 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# RA4E1 +add_library(mbed-ra4e1 INTERFACE) + +target_include_directories(mbed-ra4e1 + INTERFACE + ../ra/fsp/src/bsp/mcu/ra4e1 + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc + . +) + +target_sources(mbed-ra4e1 + INTERFACE + gpio_irq_device.c + uart_device.c + can_device.c + ../ra/fsp/src/bsp/mcu/ra4e1/bsp_linker.c + ../ra/fsp/src/r_adc/r_adc.c + ../ra/fsp/src/r_agt/r_agt.c + ../ra/fsp/src/r_cac/r_cac.c + ../ra/fsp/src/r_can/r_can.c + ../ra/fsp/src/r_cgc/r_cgc.c + ../ra/fsp/src/r_crc/r_crc.c + ../ra/fsp/src/r_dac/r_dac.c + ../ra/fsp/src/r_dmac/r_dmac.c + ../ra/fsp/src/r_doc/r_doc.c + ../ra/fsp/src/r_dtc/r_dtc.c + ../ra/fsp/src/r_elc/r_elc.c + ../ra/fsp/src/r_flash_hp/r_flash_hp.c + ../ra/fsp/src/r_gpt/r_gpt.c + ../ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c + ../ra/fsp/src/r_icu/r_icu.c + ../ra/fsp/src/r_iic_master/r_iic_master.c + ../ra/fsp/src/r_iic_slave/r_iic_slave.c + ../ra/fsp/src/r_ioport/r_ioport.c + ../ra/fsp/src/r_iwdt/r_iwdt.c + ../ra/fsp/src/r_lpm/r_lpm.c + ../ra/fsp/src/r_lvd/r_lvd.c + ../ra/fsp/src/r_poeg/r_poeg.c + ../ra/fsp/src/r_qspi/r_qspi.c + ../ra/fsp/src/r_rtc/r_rtc.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func000.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func001.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func002.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func003.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func004.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func005.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func006.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func007.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func008.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func009.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func010.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func011.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func022.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func023.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func025.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func027.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func028.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func030.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func040.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func043.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func044.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func048.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func049.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func050.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func051.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func052.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func053.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func054.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func057.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func059.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func060.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func061.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func062.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func063.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func064.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func068.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func069.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func070.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func071.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func073.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func074.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func075.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func076.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func077.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func080.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func081.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func100.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func101.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func102.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func103.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func200.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func202.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func205.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func206.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func207.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func300.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func301.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func302.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func303.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func304.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func305.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func307.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func308.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func309.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func310.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func311.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func312.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func313.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func314.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func315.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func316.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func317.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func318.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func319.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func320.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func321.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func322.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func323.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func324.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func325.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p00.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p07.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p08.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p20.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p21.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p26.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29a.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29t.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2a.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2b.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32a.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32t.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34a.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34t.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36a.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36t.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p40.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p53.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p54.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p56.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p57.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5a.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5aIA.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5b.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5c.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5d.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p6f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p72.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p79.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p7b.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p81.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p82.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p8f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p90.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p92.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p9e.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4f.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4i.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4u.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pdf.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe0.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe1.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe2.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe3.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe4.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe5.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe6.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe7.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe8.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe9.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf0.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf1.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf4.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf5.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf6.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf9.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc01.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc03.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc04.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/s_flash2.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c + ../ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c + ../ra/fsp/src/r_sci_i2c/r_sci_i2c.c + ../ra/fsp/src/r_sci_lin/r_sci_lin.c + ../ra/fsp/src/r_sci_smci/r_sci_smci.c + ../ra/fsp/src/r_sci_spi/r_sci_spi.c + ../ra/fsp/src/r_sci_uart/r_sci_uart.c + ../ra/fsp/src/r_spi/r_spi.c + ../ra/fsp/src/r_wdt/r_wdt.c +) + +target_link_libraries(mbed-ra4e1 INTERFACE mbed-renesas-ra) +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-ra4e1 ../ra/fsp/src/bsp/mcu/ra4e1/RA4E1.ld) +endif() + +add_subdirectory(TARGET_FPB_RA4E1 EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/CMakeLists.txt new file mode 100644 index 0000000000..f9ee39b926 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-fpb-ra4e1 INTERFACE) +target_include_directories(mbed-fpb-ra4e1 + INTERFACE + . +) +target_sources(mbed-fpb-ra4e1 + INTERFACE + board_init.c + common_data.c + hal_warmstart.c + hal_data.c + pin_data.c + vector_data.c + PeripheralPins.c +) +target_link_libraries(mbed-fpb-ra4e1 INTERFACE mbed-ra4e1) diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PeripheralNames.h new file mode 100644 index 0000000000..347acc1b91 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PeripheralNames.h @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = 0, + UART_3 = 3, + UART_4 = 4, + UART_9 = 9 +} UARTName; + +typedef enum { + PWM_GPT1 = 0x00, + PWM_GPT2, + PWM_GPT4, + PWM_GPT5, + PWM_AGT0, + PWM_AGT1, + PWM_AGT2, + PWM_AGT3, + PWM_AGT5, +} PWMName; + +typedef enum { + PORT_0= BSP_IO_PORT_00, + PORT_1= BSP_IO_PORT_01, + PORT_2= BSP_IO_PORT_02, + PORT_3= BSP_IO_PORT_03, + PORT_4= BSP_IO_PORT_04, + PORT_5= BSP_IO_PORT_05, +} PortName; + +typedef enum { + ADC_0= 0, +} ADCName; + +typedef enum { + DAC_0= 0, +} DACName; + +typedef enum { + IRQ_0= 0, + IRQ_1, + IRQ_2, + IRQ_3, + IRQ_4, + IRQ_5, + IRQ_6, + IRQ_7, + IRQ_8, + IRQ_9, + IRQ_13 = 13, +} IRQName; + +typedef enum { + SPI_0 = 0, +} SPIName; + +typedef enum { + I2C_0 = 0, +} I2CName; + +typedef enum { + CAN_0 = 0, +} CANName; + + +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) +#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX +#else +#define STDIO_UART_TX CONSOLE_TX +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) +#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX +#else +#define STDIO_UART_RX CONSOLE_RX +#endif +#define STDIO_UART UART_9 + +#define IRQ_CHANNELS_COUNT (14) +#define UART_COUNT (4) +#define CAN_COUNT (1) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PeripheralPins.c new file mode 100644 index 0000000000..cf65a48793 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PeripheralPins.c @@ -0,0 +1,166 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" +#include "r_adc_api.h" +#include "r_dac_api.h" +#include "r_ioport.h" + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {P0_0, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_0)}, // ARDUINO UNO A0 + {P0_1, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_1)}, // ARDUINO UNO A1 + {P0_2, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_2)}, // ARDUINO UNO A2 + {P0_3, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_3)}, // ARDUINO UNO A3 + {P0_4, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_4)}, // ARDUINO UNO A4 + {P0_13, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_11)}, // ARDUINO UNO A5 + {P0_14, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_12)}, + {P0_15, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_13)}, + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {P0_14, DAC_0, RA_PIN_DATA(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0)}, + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {P1_0, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_1, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + // {P1_2, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_2, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_3, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + // {P1_4, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_5, PWM_AGT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + // {P1_5, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P1_6, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P1_7, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_8, PWM_AGT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_9, PWM_AGT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + // {P1_9, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + // {P1_10, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_11, PWM_AGT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_12, PWM_AGT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P1_13, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P2_5, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P2_5, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P3_1, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P3_2, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P4_8, PWM_AGT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P4_9, PWM_AGT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P4_10, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P4_11, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P5_0, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {NC, NC, 0} +}; + +//*** IRQ *** + +const PinMap PinMap_IRQ[] = { + {P1_5, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_0, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_1, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_4, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_0, IRQ_2, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_13, IRQ_2, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_10, IRQ_3, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_12, IRQ_3, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_11, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_11, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_2, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_10, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_1, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_9, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_8, IRQ_7, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_4, IRQ_9, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_15, IRQ_13, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_6, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_5, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_2, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_1, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_0, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_1, IRQ_7, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_2, IRQ_8, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_4, IRQ_9, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_RX[] = { + {P1_0, UART_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P1_10, UART_9, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P2_6, UART_4, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P4_8, UART_3, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P4_10, UART_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_TX[] = { + {P1_1, UART_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P1_9, UART_9, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P2_5, UART_4, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P2_7, UART_4, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P4_9, UART_3, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P4_11, UART_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {NC, NC, 0} +}; + +//*** SPI *** +const PinMap PinMap_SPI_MOSI[] = { + {P1_9, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P1_10, SPI_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {P1_11, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P1_8, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_12, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P3_0, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P3_1, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P3_2, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {NC, NC, 0} +}; + +//*** I2C *** +const PinMap PinMap_I2C_SCL[] = { + {P4_0, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_8, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SDA[] = { + {P4_1, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_7, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {NC, NC, 0} +}; + +//*** CAN *** +const PinMap PinMap_CAN_RD[] = { + {P1_2, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P4_2, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {P1_3, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P4_1, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PinNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PinNames.h new file mode 100644 index 0000000000..29b2d4950e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PinNames.h @@ -0,0 +1,99 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* MBED TARGET LIST: RZ_A1H */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 4 + +typedef enum { + P0_0 = 0x0000, P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, + P1_0 = 0x0100, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, + P2_0 = 0x0200, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, + P3_0 = 0x0300, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, + P4_0 = 0x0400, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, + P5_0 = 0x0500, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, + + // mbed Pin Names +#define LED1 P4_8 +#define LED2 P4_7 +#define BUTTON0 P2_5 + + CONSOLE_TX = P1_9, + CONSOLE_RX = P1_10, + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Pin Names + ARDUINO_UNO_D0 = P1_10, + ARDUINO_UNO_D1 = P1_9, + ARDUINO_UNO_D2 = P4_9, + ARDUINO_UNO_D3 = P1_4, + ARDUINO_UNO_D4 = P1_7, + ARDUINO_UNO_D5 = P1_5, + ARDUINO_UNO_D6 = P3_3, + ARDUINO_UNO_D7 = P1_13, + ARDUINO_UNO_D8 = P4_2, + ARDUINO_UNO_D9 = P3_2, + ARDUINO_UNO_D10 = P1_3, + ARDUINO_UNO_D11 = P1_1, + ARDUINO_UNO_D12 = P1_0, + ARDUINO_UNO_D13 = P1_2, + ARDUINO_UNO_D14 = P4_1, + ARDUINO_UNO_D15 = P4_0, + + ARDUINO_UNO_A0 = P0_0, + ARDUINO_UNO_A1 = P0_1, + ARDUINO_UNO_A2 = P0_2, + ARDUINO_UNO_A3 = P0_3, + ARDUINO_UNO_A4 = P0_4, + ARDUINO_UNO_A5 = P0_13, +#endif + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown = 3, + PullNone = 2, + OpenDrain = 4, + PullDefault = PullNone +} PinMode; + +#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f) +#define PINNO(pin) ((pin)&0x0f) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PortNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PortNames.h new file mode 100644 index 0000000000..b5664d7425 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/PortNames.h @@ -0,0 +1,36 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3, + Port4 = 4, + Port5 = 5 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board.h new file mode 100644 index 0000000000..879018063b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board.h @@ -0,0 +1,46 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA4E1_FPB for the RA4E1_FPB board + * @brief BSP for the RA4E1_FPB Board + * + * The RA4E1_FPB is a development kit for the Renesas R7FA4E10D2CFM microcontroller in a LQFP64 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA4E1_FPB + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA4E1_FPB) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board_init.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board_init.c new file mode 100644 index 0000000000..5d0ec00667 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board_init.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA4E1_FPB + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA4E1_FPB) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA4E1_FPB) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board_init.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board_init.h new file mode 100644 index 0000000000..4d79d6519b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/board_init.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA4E1_FPB + * @brief Board specific code for the RA4E1_FPB Board + * + * This include file is specific to the RA4E1_FPB board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA4E1_FPB_EK) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/bsp_clock_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/bsp_clock_cfg.h new file mode 100644 index 0000000000..21079b2f82 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/bsp_clock_cfg.h @@ -0,0 +1,29 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* PLL Src: HOCO */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* USBCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCLK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* USBCLK Div /5 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/common_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/common_data.c new file mode 100644 index 0000000000..f934ad5cf6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/common_data.c @@ -0,0 +1,416 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated common source file - do not edit */ +#include "common_data.h" +sce_instance_ctrl_t sce_ctrl; +const sce_cfg_t sce_cfg; +#if SCE_USER_SHA_384_ENABLED +uint32_t SCE_USER_SHA_384_FUNCTION(uint8_t * message, uint8_t * digest, uint32_t message_length); +#endif + icu_instance_ctrl_t g_external_irq13_ctrl; + + /** External IRQ extended configuration for ICU HAL driver */ + const icu_extended_cfg_t g_external_irq13_ext_cfg = + { + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, + }; + + const external_irq_cfg_t g_external_irq13_cfg = + { + .channel = 13, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = (void *) &NULL, + #endif + .p_extend = (void *)&g_external_irq13_ext_cfg, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ13) + .irq = VECTOR_NUMBER_ICU_IRQ13, + #else + .irq = FSP_INVALID_VECTOR, + #endif + }; + /* Instance structure to use this module. */ + const external_irq_instance_t g_external_irq13 = + { + .p_ctrl = &g_external_irq13_ctrl, + .p_cfg = &g_external_irq13_cfg, + .p_api = &g_external_irq_on_icu + }; +icu_instance_ctrl_t g_external_irq9_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq9_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq9_cfg = +{ + .channel = 9, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq9_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ9) + .irq = VECTOR_NUMBER_ICU_IRQ9, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq9 = +{ + .p_ctrl = &g_external_irq9_ctrl, + .p_cfg = &g_external_irq9_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq8_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq8_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq8_cfg = +{ + .channel = 8, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq8_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ8) + .irq = VECTOR_NUMBER_ICU_IRQ8, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq8 = +{ + .p_ctrl = &g_external_irq8_ctrl, + .p_cfg = &g_external_irq8_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq7_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq7_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq7_cfg = +{ + .channel = 7, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq7_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ7) + .irq = VECTOR_NUMBER_ICU_IRQ7, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq7 = +{ + .p_ctrl = &g_external_irq7_ctrl, + .p_cfg = &g_external_irq7_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq6_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq6_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq6_cfg = +{ + .channel = 6, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq6_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ6) + .irq = VECTOR_NUMBER_ICU_IRQ6, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq6 = +{ + .p_ctrl = &g_external_irq6_ctrl, + .p_cfg = &g_external_irq6_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq5_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq5_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq5_cfg = +{ + .channel = 5, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq5_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ5) + .irq = VECTOR_NUMBER_ICU_IRQ5, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq5 = +{ + .p_ctrl = &g_external_irq5_ctrl, + .p_cfg = &g_external_irq5_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq4_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq4_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq4_cfg = +{ + .channel = 4, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq4_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ4) + .irq = VECTOR_NUMBER_ICU_IRQ4, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq4 = +{ + .p_ctrl = &g_external_irq4_ctrl, + .p_cfg = &g_external_irq4_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq3_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq3_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq3_cfg = +{ + .channel = 3, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq3_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ3) + .irq = VECTOR_NUMBER_ICU_IRQ3, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq3 = +{ + .p_ctrl = &g_external_irq3_ctrl, + .p_cfg = &g_external_irq3_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq2_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq2_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq2_cfg = +{ + .channel = 2, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq2_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ2) + .irq = VECTOR_NUMBER_ICU_IRQ2, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq2 = +{ + .p_ctrl = &g_external_irq2_ctrl, + .p_cfg = &g_external_irq2_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq1_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq1_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq1_cfg = +{ + .channel = 1, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq1_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ1) + .irq = VECTOR_NUMBER_ICU_IRQ1, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq1 = +{ + .p_ctrl = &g_external_irq1_ctrl, + .p_cfg = &g_external_irq1_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq0_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq0_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq0_cfg = +{ + .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq0_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ + .p_ctrl = &g_external_irq0_ctrl, + .p_cfg = &g_external_irq0_cfg, + .p_api = &g_external_irq_on_icu +}; +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/common_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/common_data.h new file mode 100644 index 0000000000..f44096d5c2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/common_data.h @@ -0,0 +1,139 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_sce.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +extern sce_instance_ctrl_t sce_ctrl; +extern const sce_cfg_t sce_cfg; +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq13; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq13_ctrl; +extern const external_irq_cfg_t g_external_irq13_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq9; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq9_ctrl; +extern const external_irq_cfg_t g_external_irq9_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq8; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq8_ctrl; +extern const external_irq_cfg_t g_external_irq8_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq7; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq7_ctrl; +extern const external_irq_cfg_t g_external_irq7_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq6; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq6_ctrl; +extern const external_irq_cfg_t g_external_irq6_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq5; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq5_ctrl; +extern const external_irq_cfg_t g_external_irq5_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq4; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq4_ctrl; +extern const external_irq_cfg_t g_external_irq4_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq3; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq3_ctrl; +extern const external_irq_cfg_t g_external_irq3_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq2; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq2_ctrl; +extern const external_irq_cfg_t g_external_irq2_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq1; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq1_ctrl; +extern const external_irq_cfg_t g_external_irq1_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_data.c new file mode 100644 index 0000000000..d2353824ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_data.c @@ -0,0 +1,1960 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated HAL source file - do not edit */ +#include "hal_data.h" + +flash_hp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ + .data_flash_bgo = false, + .p_callback = flash_callback, + .p_context = NULL, +#if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, +#else + .irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_FCU_FIFERR) + .err_irq = VECTOR_NUMBER_FCU_FIFERR, +#else + .err_irq = FSP_INVALID_VECTOR, +#endif + .err_ipl = (7), + .ipl = (7), +}; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ + .p_ctrl = &g_flash0_ctrl, + .p_cfg = &g_flash0_cfg, + .p_api = &g_flash_on_flash_hp +}; +#ifndef CAN0_BAUD_SETTINGS_OVERRIDE +#define CAN0_BAUD_SETTINGS_OVERRIDE (0) +#endif +#if CAN0_BAUD_SETTINGS_OVERRIDE +can_bit_timing_cfg_t g_can0_bit_timing_cfg = +{ + .baud_rate_prescaler = 1, + .time_segment_1 = 4, + .time_segment_2 = 2, + .synchronization_jump_width = 1 +}; +#else +can_bit_timing_cfg_t g_can0_bit_timing_cfg = +{ + /* Actual bitrate: 500000 Hz. Actual Bit Time Ratio: 75 %. */ .baud_rate_prescaler = 1 +4 /* Division value of baud rate prescaler */, .time_segment_1 = 14, .time_segment_2 = 5, .synchronization_jump_width = 4, +}; +#endif + +uint32_t g_can0_mailbox_mask[CAN_NO_OF_MAILBOXES_g_can0/4] = +{ +0x00000000, +#if CAN_NO_OF_MAILBOXES_g_can0 > 4 +0x00000000, +#endif +#if CAN_NO_OF_MAILBOXES_g_can0 > 8 +0x00000000, +0x00000000, +#endif +#if CAN_NO_OF_MAILBOXES_g_can0 > 16 +0x00000000, +0x00000000, +#endif +#if CAN_NO_OF_MAILBOXES_g_can0 > 24 +0x00000000, +0x00000000, +#endif +}; + +can_mailbox_t g_can0_mailbox[CAN_NO_OF_MAILBOXES_g_can0] = +{ + { + .mailbox_id = 0, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_TRANSMIT, + .frame_type = CAN_FRAME_TYPE_DATA +}, + { + .mailbox_id = 1, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 2, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA, + }, + { + .mailbox_id = 3, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, +#if CAN_NO_OF_MAILBOXES_g_can0 > 4 + { + .mailbox_id = 4, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 5, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 6, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 7, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, +#endif +#if CAN_NO_OF_MAILBOXES_g_can0 > 8 + { + .mailbox_id = 8, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 9, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 10, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 11, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 12, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA, + }, + { + .mailbox_id = 13, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 14, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 15, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, +#endif +#if CAN_NO_OF_MAILBOXES_g_can0 > 16 + { + .mailbox_id = 16, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + + { + .mailbox_id = 17, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 18, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 19, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 20, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 21, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 22, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA, + }, + { + .mailbox_id = 23, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, +#endif +#if CAN_NO_OF_MAILBOXES_g_can0 > 24 + { + .mailbox_id = 24, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 25, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 26, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 27, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 28, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 29, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 30, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + { + .mailbox_id = 31, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + } +#endif +}; + +#if CAN_CFG_FIFO_SUPPORT +const can_fifo_interrupt_cfg_t g_can0_fifo_int_cfg = +{ + .fifo_int_mode = (can_fifo_interrupt_mode_t) (CAN_FIFO_INTERRUPT_MODE_RX_EVERY_FRAME | CAN_FIFO_INTERRUPT_MODE_TX_EVERY_FRAME), + .rx_fifo_irq = VECTOR_NUMBER_CAN0_FIFO_RX, + .tx_fifo_irq = VECTOR_NUMBER_CAN0_FIFO_TX, +}; + +can_rx_fifo_cfg_t g_can0_rx_fifo_cfg = +{ + .rx_fifo_mask1 = 0x1FFFFFFF, + .rx_fifo_mask2 = 0x1FFFFFFF, + + .rx_fifo_id1 = + { + .mailbox_id = 0, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, + + .rx_fifo_id2 = + { + .mailbox_id = 0, + .id_mode = CAN_ID_MODE_STANDARD, + .mailbox_type = CAN_MAILBOX_RECEIVE, + .frame_type = CAN_FRAME_TYPE_DATA + }, +}; +#endif + +const can_extended_cfg_t g_can0_extended_cfg = +{ + .clock_source = CAN_CLOCK_SOURCE_PCLKB, + .p_mailbox_mask = g_can0_mailbox_mask, + .p_mailbox = g_can0_mailbox, + .global_id_mode = CAN_GLOBAL_ID_MODE_STANDARD, + .mailbox_count = CAN_NO_OF_MAILBOXES_g_can0, + .message_mode = CAN_MESSAGE_MODE_OVERWRITE, +#if CAN_CFG_FIFO_SUPPORT + .p_fifo_int_cfg = &g_can0_fifo_int_cfg, + .p_rx_fifo_cfg = &g_can0_rx_fifo_cfg, +#else + .p_fifo_int_cfg = NULL, + .p_rx_fifo_cfg = NULL, +#endif +}; + +can_instance_ctrl_t g_can0_ctrl; +const can_cfg_t g_can0_cfg = +{ + .channel = 0, + .p_bit_timing = &g_can0_bit_timing_cfg, + .p_callback = can_callback, + .p_extend = &g_can0_extended_cfg, + .p_context = NULL, + .ipl = (12), +#if defined(VECTOR_NUMBER_CAN0_MAILBOX_TX) + .tx_irq = VECTOR_NUMBER_CAN0_MAILBOX_TX, +#else + .tx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN0_MAILBOX_RX) + .rx_irq = VECTOR_NUMBER_CAN0_MAILBOX_RX, +#else + .rx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN0_ERROR) + .error_irq = VECTOR_NUMBER_CAN0_ERROR, +#else + .error_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const can_instance_t g_can0 = +{ + .p_ctrl = &g_can0_ctrl, + .p_cfg = &g_can0_cfg, + .p_api = &g_can_on_can +}; + +sci_uart_instance_ctrl_t g_uart9_ctrl; + + baud_setting_t g_uart9_baud_setting = + { + /* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .semr_baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart9_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart9_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + }, + .irda_setting = { + .ircr_bits_b.ire = 0, + .ircr_bits_b.irrxinv = 0, + .ircr_bits_b.irtxinv = 0, + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart9_cfg = + { + .channel = 9, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart9_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI9_RXI) + .rxi_irq = VECTOR_NUMBER_SCI9_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_TXI) + .txi_irq = VECTOR_NUMBER_SCI9_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_TEI) + .tei_irq = VECTOR_NUMBER_SCI9_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_ERI) + .eri_irq = VECTOR_NUMBER_SCI9_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart9 = +{ + .p_ctrl = &g_uart9_ctrl, + .p_cfg = &g_uart9_cfg, + .p_api = &g_uart_on_sci +}; +sci_uart_instance_ctrl_t g_uart4_ctrl; + + baud_setting_t g_uart4_baud_setting = + { + /* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .semr_baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart4_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart4_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + }, + .irda_setting = { + .ircr_bits_b.ire = 0, + .ircr_bits_b.irrxinv = 0, + .ircr_bits_b.irtxinv = 0, + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart4_cfg = + { + .channel = 4, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart4_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI4_RXI) + .rxi_irq = VECTOR_NUMBER_SCI4_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI4_TXI) + .txi_irq = VECTOR_NUMBER_SCI4_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI4_TEI) + .tei_irq = VECTOR_NUMBER_SCI4_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI4_ERI) + .eri_irq = VECTOR_NUMBER_SCI4_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart4 = +{ + .p_ctrl = &g_uart4_ctrl, + .p_cfg = &g_uart4_cfg, + .p_api = &g_uart_on_sci +}; +sci_uart_instance_ctrl_t g_uart3_ctrl; + + baud_setting_t g_uart3_baud_setting = + { + /* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .semr_baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart3_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart3_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + }, + .irda_setting = { + .ircr_bits_b.ire = 0, + .ircr_bits_b.irrxinv = 0, + .ircr_bits_b.irtxinv = 0, + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart3_cfg = + { + .channel = 3, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart3_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI3_RXI) + .rxi_irq = VECTOR_NUMBER_SCI3_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI3_TXI) + .txi_irq = VECTOR_NUMBER_SCI3_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI3_TEI) + .tei_irq = VECTOR_NUMBER_SCI3_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI3_ERI) + .eri_irq = VECTOR_NUMBER_SCI3_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart3 = +{ + .p_ctrl = &g_uart3_ctrl, + .p_cfg = &g_uart3_cfg, + .p_api = &g_uart_on_sci +}; + +agt_instance_ctrl_t g_timer_agt5_ctrl; +const agt_extended_cfg_t g_timer_agt5_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_16, +}; +const timer_cfg_t g_timer_agt5_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 5, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt5_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT5_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT5_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt5 = +{ + .p_ctrl = &g_timer_agt5_ctrl, + .p_cfg = &g_timer_agt5_cfg, + .p_api = &g_timer_on_agt +}; +agt_instance_ctrl_t g_timer_agt3_ctrl; +const agt_extended_cfg_t g_timer_agt3_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_16, +}; +const timer_cfg_t g_timer_agt3_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 3, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt3_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT3_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT3_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt3 = +{ + .p_ctrl = &g_timer_agt3_ctrl, + .p_cfg = &g_timer_agt3_cfg, + .p_api = &g_timer_on_agt +}; +agt_instance_ctrl_t g_timer_agt2_ctrl; +const agt_extended_cfg_t g_timer_agt2_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_16, +}; +const timer_cfg_t g_timer_agt2_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 2, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt2_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT2_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT2_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt2 = +{ + .p_ctrl = &g_timer_agt2_ctrl, + .p_cfg = &g_timer_agt2_cfg, + .p_api = &g_timer_on_agt +}; +agt_instance_ctrl_t g_timer_agt1_ctrl; +const agt_extended_cfg_t g_timer_agt1_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_16, +}; +const timer_cfg_t g_timer_agt1_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 1, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt1_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT1_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT1_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt1 = +{ + .p_ctrl = &g_timer_agt1_ctrl, + .p_cfg = &g_timer_agt1_cfg, + .p_api = &g_timer_on_agt +}; +agt_instance_ctrl_t g_timer_agt0_ctrl; +const agt_extended_cfg_t g_timer_agt0_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_16, +}; +const timer_cfg_t g_timer_agt0_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 0, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt0_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt0 = +{ + .p_ctrl = &g_timer_agt0_ctrl, + .p_cfg = &g_timer_agt0_cfg, + .p_api = &g_timer_on_agt +}; +gpt_instance_ctrl_t g_timer_gpt5_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt5_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT5_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt5_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT5_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT5_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT5_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT5_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt5_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt5_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.00065536 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 5, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt5_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT5_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt5 = +{ + .p_ctrl = &g_timer_gpt5_ctrl, + .p_cfg = &g_timer_gpt5_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt4_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt4_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT4_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt4_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT4_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT4_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT4_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT4_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt4_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt4_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.00065536 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 4, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt4_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT4_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt4 = +{ + .p_ctrl = &g_timer_gpt4_ctrl, + .p_cfg = &g_timer_gpt4_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt2_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt2_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt2_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT2_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT2_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT2_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT2_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt2_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt2_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.00065536 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_4, + .channel = 2, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt2_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt2 = +{ + .p_ctrl = &g_timer_gpt2_ctrl, + .p_cfg = &g_timer_gpt2_cfg, + .p_api = &g_timer_on_gpt +}; +sci_uart_instance_ctrl_t g_uart0_ctrl; + + baud_setting_t g_uart0_baud_setting = + { + /* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .semr_baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart0_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + }, + .irda_setting = { + .ircr_bits_b.ire = 0, + .ircr_bits_b.irrxinv = 0, + .ircr_bits_b.irtxinv = 0, + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart0_cfg = + { + .channel = 0, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart0_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ + .p_ctrl = &g_uart0_ctrl, + .p_cfg = &g_uart0_cfg, + .p_api = &g_uart_on_sci +}; + +dmac_instance_ctrl_t g_transfer0_ctrl; +transfer_info_t g_transfer0_info = +{ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .transfer_settings_word_b.irq = TRANSFER_IRQ_END, + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; +const dmac_extended_cfg_t g_transfer0_extend = +{ + .offset = 1, + .src_buffer_size = 1, +#if defined(VECTOR_NUMBER_DMAC0_INT) + .irq = VECTOR_NUMBER_DMAC0_INT, +#else + .irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .channel = 0, + .p_callback = g_spi0_tx_transfer_callback, + .p_context = NULL, + .activation_source = ELC_EVENT_SPI0_TXI, +}; +const transfer_cfg_t g_transfer0_cfg = +{ + .p_info = &g_transfer0_info, + .p_extend = &g_transfer0_extend, +}; +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ + .p_ctrl = &g_transfer0_ctrl, + .p_cfg = &g_transfer0_cfg, + .p_api = &g_transfer_on_dmac +}; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (1) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_tx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +void g_spi0_tx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_tx_dmac_callback(&g_spi0_ctrl); +} +#endif + +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_rx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +void g_spi0_rx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_rx_dmac_callback(&g_spi0_ctrl); +} +#endif +#undef RA_NOT_DEFINED + +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ + .spi_clksyn = SPI_SSL_MODE_SPI, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = { + /* Actual calculated bitrate: 12500000. */ .spbr = 3, .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1, + .burst_interframe_delay = SPI_BURST_TRANSFER_WITH_DELAY + }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ + .channel = 0, + +#if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + + .rxi_ipl = (10), + .txi_ipl = (BSP_IRQ_DISABLED), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, +}; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ + .p_ctrl = &g_spi0_ctrl, + .p_cfg = &g_spi0_cfg, + .p_api = &g_spi_on_spi +}; +iic_slave_instance_ctrl_t g_i2c_slave0_ctrl; +const iic_slave_extended_cfg_t g_i2c_slave0_extend = +{ + /* Actual delay: 260 ns. */ .clock_settings.brl_value = 13, .clock_settings.digital_filter_stages = 3, .clock_settings.cks_value = 0, +}; +const i2c_slave_cfg_t g_i2c_slave0_cfg = +{ + .channel = 0, + .rate = I2C_SLAVE_RATE_STANDARD, + .slave = 0x08, + .general_call_enable = false, + .addr_mode = I2C_SLAVE_ADDR_MODE_7BIT, +#if (IIC_SLAVE_CFG_DTC_ENABLE) +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED +#endif + .p_callback = NULL, + .p_context = NULL, +#if defined(VECTOR_NUMBER_IIC0_RXI) + .rxi_irq = VECTOR_NUMBER_IIC0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_TXI) + .txi_irq = VECTOR_NUMBER_IIC0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_TEI) + .tei_irq = VECTOR_NUMBER_IIC0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_ERI) + .eri_irq = VECTOR_NUMBER_IIC0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .eri_ipl = (12), + .clock_stretching_enable = false, + .p_extend = &g_i2c_slave0_extend, +}; +/* Instance structure to use this module. */ +const i2c_slave_instance_t g_i2c_slave0 = +{ + .p_ctrl = &g_i2c_slave0_ctrl, + .p_cfg = &g_i2c_slave0_cfg, + .p_api = &g_i2c_slave_on_iic +}; +iic_master_instance_ctrl_t g_i2c_master0_ctrl; +const iic_master_extended_cfg_t g_i2c_master0_extend = +{ + .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, + .timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED, + .smbus_operation = 0, + /* Actual calculated bitrate: 98425. Actual calculated duty cycle: 50%. */ .clock_settings.brl_value = 28, .clock_settings.brh_value = 28, .clock_settings.cks_value = 3, .clock_settings.sddl_value = 0, .clock_settings.dlcs_value = 0, +}; +const i2c_master_cfg_t g_i2c_master0_cfg = +{ + .channel = 0, + .rate = I2C_MASTER_RATE_STANDARD, + .slave = 0x00, + .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .p_callback = NULL, + .p_context = NULL, +#if defined(VECTOR_NUMBER_IIC0_RXI) + .rxi_irq = VECTOR_NUMBER_IIC0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_TXI) + .txi_irq = VECTOR_NUMBER_IIC0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_TEI) + .tei_irq = VECTOR_NUMBER_IIC0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_ERI) + .eri_irq = VECTOR_NUMBER_IIC0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .p_extend = &g_i2c_master0_extend, +}; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master0 = +{ + .p_ctrl = &g_i2c_master0_ctrl, + .p_cfg = &g_i2c_master0_cfg, + .p_api = &g_i2c_master_on_iic +}; +wdt_instance_ctrl_t g_wdt0_ctrl; + +const wdt_cfg_t g_wdt0_cfg = +{ + .timeout = WDT_TIMEOUT_16384, + .clock_division = WDT_CLOCK_DIVISION_8192, + .window_start = WDT_WINDOW_START_100, + .window_end = WDT_WINDOW_END_0, + .reset_control = WDT_RESET_CONTROL_RESET, + .stop_control = WDT_STOP_CONTROL_ENABLE, + .p_callback = NULL, +}; + +/* Instance structure to use this module. */ +const wdt_instance_t g_wdt0 = +{ + .p_ctrl = &g_wdt0_ctrl, + .p_cfg = &g_wdt0_cfg, + .p_api = &g_wdt_on_wdt +}; +#if BSP_TZ_NONSECURE_BUILD + #if defined(BSP_CFG_CLOCKS_SECURE) && BSP_CFG_CLOCKS_SECURE + #error "The LPM module requires CGC registers to be non-secure when it is used in a TrustZone Non-secure project." + #endif +#endif + +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ + .low_power_mode = LPM_MODE_SLEEP, + .standby_wake_sources = (lpm_standby_wake_source_t) 0, +#if BSP_FEATURE_ICU_HAS_WUPEN2 + .standby_wake_sources_2 = (lpm_standby_wake_source_2_t) 0, +#endif +#if BSP_FEATURE_LPM_HAS_SNOOZE + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .snooze_request_source = (lpm_snooze_request_t) LPM_SNOOZE_REQUEST_RXD0_FALLING, +#if BSP_FEATURE_LPM_SNZEDCR_MASK > 0 + .snooze_end_sources = (lpm_snooze_end_t) 0, +#endif + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, +#endif +#if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = 0, +#endif +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t) 0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t) 0, +#if BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE + .deep_standby_soft_start_mode = 0, +#endif +#endif +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint16_t) ( 0), + .ram_retention_cfg.tcm_retention = false, +#endif +#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, +#endif +#if BSP_FEATURE_LPM_HAS_LDO_SKEEP + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, +#endif +#if BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT + .lpm_flash_mode_select = false, +#endif +#if BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE + .lpm_hoco_startup_speed = false, +#endif +#if BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT + .lpm_standby_sosc = false, +#endif + .p_extend = NULL, +}; + +const lpm_instance_t g_lpm0 = +{ + .p_api = &g_lpm_on_lpm, + .p_ctrl = &g_lpm0_ctrl, + .p_cfg = &g_lpm0_cfg +}; +gpt_instance_ctrl_t g_timer_gpt1_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt1_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt1_extend = +{ + .gtioca = { .output_enabled = false, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = false, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (10), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT1_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT1_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT1_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT1_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt1_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) false, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) false, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt1_cfg = +{ + .mode = TIMER_MODE_PERIODIC, + /* Actual period: 42.94967296 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = TIMER_SOURCE_DIV_4, + .channel = 1, + .p_callback = usticker_compare_match_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt1_extend, + .cycle_end_ipl = (15), +#if defined(VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt1 = +{ + .p_ctrl = &g_timer_gpt1_ctrl, + .p_cfg = &g_timer_gpt1_cfg, + .p_api = &g_timer_on_gpt +}; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ + .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, +}; +const rtc_cfg_t g_rtc0_cfg = +{ + .clock_source = MBED_CONF_TARGET_RTC_CLOCK_SOURCE, + .freq_compare_value = 255, + .p_err_cfg = &g_rtc0_err_cfg, + .p_callback = NULL, + .p_context = NULL, + .p_extend = NULL, + .alarm_ipl = (BSP_IRQ_DISABLED), + .periodic_ipl = (BSP_IRQ_DISABLED), + .carry_ipl = (12), +#if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, +#else + .alarm_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, +#else + .periodic_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, +#else + .carry_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ + .p_ctrl = &g_rtc0_ctrl, + .p_cfg = &g_rtc0_cfg, + .p_api = &g_rtc_on_rtc +}; +dac_instance_ctrl_t g_dac0_ctrl; +const dac_extended_cfg_t g_dac0_ext_cfg = +{ + .enable_charge_pump = 0, + .data_format = DAC_DATA_FORMAT_FLUSH_RIGHT, + .output_amplifier_enabled = 0, + .internal_output_enabled = false, + .ref_volt_sel = (dac_ref_volt_sel_t) (0) +}; +const dac_cfg_t g_dac0_cfg = +{ + .channel = 0, + .ad_da_synchronized = false, + .p_extend = &g_dac0_ext_cfg +}; +/* Instance structure to use this module. */ +const dac_instance_t g_dac0 = +{ + .p_ctrl = &g_dac0_ctrl, + .p_cfg = &g_dac0_cfg, + .p_api = &g_dac_on_dac +}; +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ + .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger = ADC_START_SOURCE_DISABLED, + .trigger_group_b = ADC_START_SOURCE_DISABLED, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, + .enable_adbuf = 0, +#if defined(VECTOR_NUMBER_ADC0_WINDOW_A) + .window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A, +#else + .window_a_irq = FSP_INVALID_VECTOR, +#endif + .window_a_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC0_WINDOW_B) + .window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B, +#else + .window_b_irq = FSP_INVALID_VECTOR, +#endif + .window_b_ipl = (BSP_IRQ_DISABLED), +}; +const adc_cfg_t g_adc0_cfg = +{ + .unit = 0, + .mode = ADC_MODE_SINGLE_SCAN, + .resolution = ADC_RESOLUTION_12_BIT, + .alignment = (adc_alignment_t) ADC_ALIGNMENT_RIGHT, + .trigger = (adc_trigger_t)0xF, // Not used + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_adc0_cfg_extend, +#if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, +#else + .scan_end_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, +#else + .scan_end_b_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), +}; +#if ((0) | (0)) +const adc_window_cfg_t g_adc0_window_cfg = +{ + .compare_mask = 0, + .compare_mode_mask = 0, + .compare_cfg = (adc_compare_cfg_t) ((0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR)), + .compare_ref_low = 0, + .compare_ref_high = 0, + .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0), + .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE), + .compare_b_ref_low = 0, + .compare_b_ref_high = 0, +}; +#endif +const adc_channel_cfg_t g_adc0_channel_cfg = +{ + .scan_mask = ADC_MASK_CHANNEL_0 | ADC_MASK_CHANNEL_1 | ADC_MASK_CHANNEL_2 | ADC_MASK_CHANNEL_3 | ADC_MASK_CHANNEL_4 | ADC_MASK_CHANNEL_11 | ADC_MASK_CHANNEL_12 | ADC_MASK_CHANNEL_13 | 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, +#if ((0) | (0)) + .p_window_cfg = (adc_window_cfg_t *) &g_adc0_window_cfg, +#else + .p_window_cfg = NULL, +#endif +}; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ + .p_ctrl = &g_adc0_ctrl, + .p_cfg = &g_adc0_cfg, + .p_channel_cfg = &g_adc0_channel_cfg, + .p_api = &g_adc_on_adc +}; +void g_hal_init(void) { +g_common_init(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_data.h new file mode 100644 index 0000000000..25799fa974 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_data.h @@ -0,0 +1,304 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_flash_hp.h" +#include "r_flash_api.h" +#include "r_can.h" +#include "r_can_api.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_gpt.h" +#include "r_timer_api.h" +#include "r_dmac.h" +#include "r_transfer_api.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +#include "r_spi.h" +#include "r_iic_slave.h" +#include "r_i2c_slave_api.h" +#include "r_iic_master.h" +#include "r_i2c_master_api.h" +#include "r_wdt.h" +#include "r_wdt_api.h" +#include "r_crc.h" +#include "r_crc_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_dac.h" +#include "r_dac_api.h" +#include "r_adc.h" +#include "r_adc_api.h" +FSP_HEADER +/* Flash on Flash HP Instance */ +extern const flash_instance_t g_flash0; + +/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_hp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef flash_callback +void flash_callback(flash_callback_args_t * p_args); +#endif +/** CAN on CAN Instance. */ +extern const can_instance_t g_can0; +/** Access the CAN instance using these structures when calling API functions directly (::p_api is not used). */ +extern can_instance_ctrl_t g_can0_ctrl; +extern const can_cfg_t g_can0_cfg; +extern const can_extended_cfg_t g_can0_extended_cfg; + + + + +#ifndef can_callback +void can_callback(can_callback_args_t * p_args); +#endif +#define CAN_NO_OF_MAILBOXES_g_can0 (16) +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt5; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt5_ctrl; +extern const timer_cfg_t g_timer_agt5_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt3; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt3_ctrl; +extern const timer_cfg_t g_timer_agt3_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt2; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt2_ctrl; +extern const timer_cfg_t g_timer_agt2_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt1; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt1_ctrl; +extern const timer_cfg_t g_timer_agt1_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt0_ctrl; +extern const timer_cfg_t g_timer_agt0_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt5; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt5_ctrl; +extern const timer_cfg_t g_timer_gpt5_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt4; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt4_ctrl; +extern const timer_cfg_t g_timer_gpt4_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt2; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt2_ctrl; +extern const timer_cfg_t g_timer_gpt2_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart9; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart9_ctrl; + extern const uart_cfg_t g_uart9_cfg; + extern const sci_uart_extended_cfg_t g_uart9_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart4; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart4_ctrl; + extern const uart_cfg_t g_uart4_cfg; + extern const sci_uart_extended_cfg_t g_uart4_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart0; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart0_ctrl; + extern const uart_cfg_t g_uart0_cfg; + extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart3; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart3_ctrl; + extern const uart_cfg_t g_uart3_cfg; + extern const sci_uart_extended_cfg_t g_uart3_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/* Transfer on DMAC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DMAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dmac_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; + +#ifndef g_spi0_tx_transfer_callback +void g_spi0_tx_transfer_callback(transfer_callback_args_t * p_args); +#endif +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t * p_args); +#endif + + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else + #define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + #define g_spi0_P_TRANSFER_RX (NULL) +#else + #define g_spi0_P_TRANSFER_RX (&RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +/** I2C Slave on IIC Instance. */ +extern const i2c_slave_instance_t g_i2c_slave0; + +/** Access the I2C Slave instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_slave_instance_ctrl_t g_i2c_slave0_ctrl; +extern const i2c_slave_cfg_t g_i2c_slave0_cfg; + +#ifndef NULL +void NULL(i2c_slave_callback_args_t * p_args); +#endif +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master0; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_master_instance_ctrl_t g_i2c_master0_ctrl; +extern const i2c_master_cfg_t g_i2c_master0_cfg; + +#ifndef i2c_callback +void i2c_callback(i2c_master_callback_args_t * p_args); +#endif +/** WDT on WDT Instance. */ +extern const wdt_instance_t g_wdt0; + +/** Access the WDT instance using these structures when calling API functions directly (::p_api is not used). */ +extern wdt_instance_ctrl_t g_wdt0_ctrl; +extern const wdt_cfg_t g_wdt0_cfg; + +#ifndef NULL +void NULL(wdt_callback_args_t * p_args); +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt1; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt1_ctrl; +extern const timer_cfg_t g_timer_gpt1_cfg; + +#ifndef usticker_compare_match_callback +void usticker_compare_match_callback(timer_callback_args_t * p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t * p_args); +#endif +/** DAC on DAC Instance. */ +extern const dac_instance_t g_dac0; + +/** Access the DAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dac_instance_ctrl_t g_dac0_ctrl; +extern const dac_cfg_t g_dac0_cfg; +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t * p_args); +#endif + +#ifndef NULL +#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 8 +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_warmstart.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_warmstart.c new file mode 100644 index 0000000000..2e799ebefe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/hal_warmstart.c @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); + +FSP_CPP_FOOTER + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { +#if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ +#endif + } + +#if BSP_CFG_OSPI_B_STARTUP_ENABLED && defined(BSP_CFG_OSPI_B_STARTUP_FN) + if (BSP_WARM_START_POST_CLOCK == event) + { + /* Setup OSPI_B SiP flash and initialize it. */ + R_BSP_OspiBInit(BSP_CFG_OSPI_B_STARTUP_FN, true); + } +#endif + + if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME); + +#if BSP_CFG_SDRAM_ENABLED + + /* Setup SDRAM and initialize it. Must configure pins first. */ + R_BSP_SdramInit(true); +#endif + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/pin_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/pin_data.c new file mode 100644 index 0000000000..18dc77dfc3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/pin_data.c @@ -0,0 +1,12 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = 0, + .p_pin_cfg_data = NULL, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/vector_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/vector_data.c new file mode 100644 index 0000000000..d9bcaa6b87 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/vector_data.c @@ -0,0 +1,107 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated vector source file - do not edit */ + #include "bsp_api.h" + /* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ + #if VECTOR_DATA_IRQ_COUNT > 0 + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_NUM_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = + { + [0] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [1] = gpt_counter_overflow_isr, /* GPT1 COUNTER OVERFLOW (Overflow) */ + [2] = gpt_capture_compare_a_isr, /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + [3] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [4] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */ + [5] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */ + [6] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */ + [7] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */ + [8] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [9] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [10] = spi_eri_isr, /* SPI0 ERI (Error) */ + [11] = dmac_int_isr, /* DMAC0 INT (DMAC0 transfer end) */ + [12] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [13] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ + [14] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */ + [15] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */ + [16] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [17] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [18] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [19] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [20] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [21] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [22] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ + [23] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ + [24] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ + [25] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ + [26] = sci_uart_rxi_isr, /* SCI3 RXI (Receive data full) */ + [27] = sci_uart_txi_isr, /* SCI3 TXI (Transmit data empty) */ + [28] = sci_uart_tei_isr, /* SCI3 TEI (Transmit end) */ + [29] = sci_uart_eri_isr, /* SCI3 ERI (Receive error) */ + [30] = sci_uart_rxi_isr, /* SCI4 RXI (Receive data full) */ + [31] = sci_uart_txi_isr, /* SCI4 TXI (Transmit data empty) */ + [32] = sci_uart_tei_isr, /* SCI4 TEI (Transmit end) */ + [33] = sci_uart_eri_isr, /* SCI4 ERI (Receive error) */ + [34] = sci_uart_rxi_isr, /* SCI9 RXI (Receive data full) */ + [35] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ + [36] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [37] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [38] = can_error_isr, /* CAN0 ERROR (Error interrupt) */ + [39] = can_rx_isr, /* CAN0 MAILBOX RX (Reception complete interrupt) */ + [40] = can_tx_isr, /* CAN0 MAILBOX TX (Transmission complete interrupt) */ + [41] = can_rx_isr, /* CAN0 FIFO RX (Receive FIFO interrupt) */ + [42] = can_tx_isr, /* CAN0 FIFO TX (Transmit FIFO interrupt) */ + [43] = fcu_frdyi_isr, /* FCU FRDYI (Flash ready interrupt) */ + [44] = fcu_fiferr_isr, /* FCU FIFERR (Flash access error interrupt) */ + }; + #if BSP_FEATURE_ICU_HAS_IELSR + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_NUM_ENTRIES] = + { + [0] = BSP_PRV_VECT_ENUM(EVENT_RTC_CARRY,GROUP0), /* RTC CARRY (Carry interrupt) */ + [1] = BSP_PRV_VECT_ENUM(EVENT_GPT1_COUNTER_OVERFLOW,GROUP1), /* GPT1 COUNTER OVERFLOW (Overflow) */ + [2] = BSP_PRV_VECT_ENUM(EVENT_GPT1_CAPTURE_COMPARE_A,GROUP2), /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + [3] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ0,GROUP3), /* ICU IRQ0 (External pin interrupt 0) */ + [4] = BSP_PRV_VECT_ENUM(EVENT_IIC0_RXI,GROUP4), /* IIC0 RXI (Receive data full) */ + [5] = BSP_PRV_VECT_ENUM(EVENT_IIC0_TXI,GROUP5), /* IIC0 TXI (Transmit data empty) */ + [6] = BSP_PRV_VECT_ENUM(EVENT_IIC0_TEI,GROUP6), /* IIC0 TEI (Transmit end) */ + [7] = BSP_PRV_VECT_ENUM(EVENT_IIC0_ERI,GROUP7), /* IIC0 ERI (Transfer error) */ + [8] = BSP_PRV_VECT_ENUM(EVENT_SPI0_RXI,GROUP0), /* SPI0 RXI (Receive buffer full) */ + [9] = BSP_PRV_VECT_ENUM(EVENT_SPI0_TEI,GROUP1), /* SPI0 TEI (Transmission complete event) */ + [10] = BSP_PRV_VECT_ENUM(EVENT_SPI0_ERI,GROUP2), /* SPI0 ERI (Error) */ + [11] = BSP_PRV_VECT_ENUM(EVENT_DMAC0_INT,GROUP3), /* DMAC0 INT (DMAC0 transfer end) */ + [12] = BSP_PRV_VECT_ENUM(EVENT_SCI0_RXI,GROUP4), /* SCI0 RXI (Receive data full) */ + [13] = BSP_PRV_VECT_ENUM(EVENT_SCI0_TXI,GROUP5), /* SCI0 TXI (Transmit data empty) */ + [14] = BSP_PRV_VECT_ENUM(EVENT_SCI0_TEI,GROUP6), /* SCI0 TEI (Transmit end) */ + [15] = BSP_PRV_VECT_ENUM(EVENT_SCI0_ERI,GROUP7), /* SCI0 ERI (Receive error) */ + [16] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ1,GROUP0), /* ICU IRQ1 (External pin interrupt 1) */ + [17] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ2,GROUP1), /* ICU IRQ2 (External pin interrupt 2) */ + [18] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ3,GROUP2), /* ICU IRQ3 (External pin interrupt 3) */ + [19] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ4,GROUP3), /* ICU IRQ4 (External pin interrupt 4) */ + [20] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ5,GROUP4), /* ICU IRQ5 (External pin interrupt 5) */ + [21] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ6,GROUP5), /* ICU IRQ6 (External pin interrupt 6) */ + [22] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ7,GROUP6), /* ICU IRQ7 (External pin interrupt 7) */ + [23] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ8,GROUP7), /* ICU IRQ8 (External pin interrupt 8) */ + [24] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ9,GROUP0), /* ICU IRQ9 (External pin interrupt 9) */ + [25] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ13,GROUP1), /* ICU IRQ13 (External pin interrupt 13) */ + [26] = BSP_PRV_VECT_ENUM(EVENT_SCI3_RXI,GROUP2), /* SCI3 RXI (Receive data full) */ + [27] = BSP_PRV_VECT_ENUM(EVENT_SCI3_TXI,GROUP3), /* SCI3 TXI (Transmit data empty) */ + [28] = BSP_PRV_VECT_ENUM(EVENT_SCI3_TEI,GROUP4), /* SCI3 TEI (Transmit end) */ + [29] = BSP_PRV_VECT_ENUM(EVENT_SCI3_ERI,GROUP5), /* SCI3 ERI (Receive error) */ + [30] = BSP_PRV_VECT_ENUM(EVENT_SCI4_RXI,GROUP6), /* SCI4 RXI (Receive data full) */ + [31] = BSP_PRV_VECT_ENUM(EVENT_SCI4_TXI,GROUP7), /* SCI4 TXI (Transmit data empty) */ + [32] = BSP_PRV_VECT_ENUM(EVENT_SCI4_TEI,FIXED), /* SCI4 TEI (Transmit end) */ + [33] = BSP_PRV_VECT_ENUM(EVENT_SCI4_ERI,FIXED), /* SCI4 ERI (Receive error) */ + [34] = BSP_PRV_VECT_ENUM(EVENT_SCI9_RXI,FIXED), /* SCI9 RXI (Receive data full) */ + [35] = BSP_PRV_VECT_ENUM(EVENT_SCI9_TXI,FIXED), /* SCI9 TXI (Transmit data empty) */ + [36] = BSP_PRV_VECT_ENUM(EVENT_SCI9_TEI,FIXED), /* SCI9 TEI (Transmit end) */ + [37] = BSP_PRV_VECT_ENUM(EVENT_SCI9_ERI,FIXED), /* SCI9 ERI (Receive error) */ + [38] = BSP_PRV_VECT_ENUM(EVENT_CAN0_ERROR,FIXED), /* CAN0 ERROR (Error interrupt) */ + [39] = BSP_PRV_VECT_ENUM(EVENT_CAN0_MAILBOX_RX,FIXED), /* CAN0 MAILBOX RX (Reception complete interrupt) */ + [40] = BSP_PRV_VECT_ENUM(EVENT_CAN0_MAILBOX_TX,FIXED), /* CAN0 MAILBOX TX (Transmission complete interrupt) */ + [41] = BSP_PRV_VECT_ENUM(EVENT_CAN0_FIFO_RX,FIXED), /* CAN0 FIFO RX (Receive FIFO interrupt) */ + [42] = BSP_PRV_VECT_ENUM(EVENT_CAN0_FIFO_TX,FIXED), /* CAN0 FIFO TX (Transmit FIFO interrupt) */ + [43] = BSP_PRV_VECT_ENUM(EVENT_FCU_FRDYI,FIXED), /* FCU FRDYI (Flash ready interrupt) */ + [44] = BSP_PRV_VECT_ENUM(EVENT_FCU_FIFERR,FIXED), /* FCU FIFERR (Flash access error interrupt) */ + }; + #endif + #endif \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/vector_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/vector_data.h new file mode 100644 index 0000000000..3099bb582d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/TARGET_FPB_RA4E1/vector_data.h @@ -0,0 +1,135 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated vector header file - do not edit */ + #ifndef VECTOR_DATA_H + #define VECTOR_DATA_H + #ifdef __cplusplus + extern "C" { + #endif + /* Number of interrupts allocated */ + #ifndef VECTOR_DATA_IRQ_COUNT + #define VECTOR_DATA_IRQ_COUNT (45) + #endif + /* ISR prototypes */ + void rtc_carry_isr(void); + void gpt_counter_overflow_isr(void); + void gpt_capture_compare_a_isr(void); + void r_icu_isr(void); + void iic_master_rxi_isr(void); + void iic_master_txi_isr(void); + void iic_master_tei_isr(void); + void iic_master_eri_isr(void); + void spi_rxi_isr(void); + void spi_tei_isr(void); + void spi_eri_isr(void); + void dmac_int_isr(void); + void sci_uart_rxi_isr(void); + void sci_uart_txi_isr(void); + void sci_uart_tei_isr(void); + void sci_uart_eri_isr(void); + void can_error_isr(void); + void can_rx_isr(void); + void can_tx_isr(void); + void fcu_frdyi_isr(void); + void fcu_fiferr_isr(void); + + /* Vector table allocations */ + #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type) 0) /* RTC CARRY (Carry interrupt) */ + #define RTC_CARRY_IRQn ((IRQn_Type) 0) /* RTC CARRY (Carry interrupt) */ + #define VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW ((IRQn_Type) 1) /* GPT1 COUNTER OVERFLOW (Overflow) */ + #define GPT1_COUNTER_OVERFLOW_IRQn ((IRQn_Type) 1) /* GPT1 COUNTER OVERFLOW (Overflow) */ + #define VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A ((IRQn_Type) 2) /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + #define GPT1_CAPTURE_COMPARE_A_IRQn ((IRQn_Type) 2) /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 3) /* ICU IRQ0 (External pin interrupt 0) */ + #define ICU_IRQ0_IRQn ((IRQn_Type) 3) /* ICU IRQ0 (External pin interrupt 0) */ + #define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type) 4) /* IIC0 RXI (Receive data full) */ + #define IIC0_RXI_IRQn ((IRQn_Type) 4) /* IIC0 RXI (Receive data full) */ + #define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type) 5) /* IIC0 TXI (Transmit data empty) */ + #define IIC0_TXI_IRQn ((IRQn_Type) 5) /* IIC0 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type) 6) /* IIC0 TEI (Transmit end) */ + #define IIC0_TEI_IRQn ((IRQn_Type) 6) /* IIC0 TEI (Transmit end) */ + #define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type) 7) /* IIC0 ERI (Transfer error) */ + #define IIC0_ERI_IRQn ((IRQn_Type) 7) /* IIC0 ERI (Transfer error) */ + #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type) 8) /* SPI0 RXI (Receive buffer full) */ + #define SPI0_RXI_IRQn ((IRQn_Type) 8) /* SPI0 RXI (Receive buffer full) */ + #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type) 9) /* SPI0 TEI (Transmission complete event) */ + #define SPI0_TEI_IRQn ((IRQn_Type) 9) /* SPI0 TEI (Transmission complete event) */ + #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type) 10) /* SPI0 ERI (Error) */ + #define SPI0_ERI_IRQn ((IRQn_Type) 10) /* SPI0 ERI (Error) */ + #define VECTOR_NUMBER_DMAC0_INT ((IRQn_Type) 11) /* DMAC0 INT (DMAC0 transfer end) */ + #define DMAC0_INT_IRQn ((IRQn_Type) 11) /* DMAC0 INT (DMAC0 transfer end) */ + #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 12) /* SCI0 RXI (Receive data full) */ + #define SCI0_RXI_IRQn ((IRQn_Type) 12) /* SCI0 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type) 13) /* SCI0 TXI (Transmit data empty) */ + #define SCI0_TXI_IRQn ((IRQn_Type) 13) /* SCI0 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type) 14) /* SCI0 TEI (Transmit end) */ + #define SCI0_TEI_IRQn ((IRQn_Type) 14) /* SCI0 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type) 15) /* SCI0 ERI (Receive error) */ + #define SCI0_ERI_IRQn ((IRQn_Type) 15) /* SCI0 ERI (Receive error) */ + #define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type) 16) /* ICU IRQ1 (External pin interrupt 1) */ + #define ICU_IRQ1_IRQn ((IRQn_Type) 16) /* ICU IRQ1 (External pin interrupt 1) */ + #define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type) 17) /* ICU IRQ2 (External pin interrupt 2) */ + #define ICU_IRQ2_IRQn ((IRQn_Type) 17) /* ICU IRQ2 (External pin interrupt 2) */ + #define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type) 18) /* ICU IRQ3 (External pin interrupt 3) */ + #define ICU_IRQ3_IRQn ((IRQn_Type) 18) /* ICU IRQ3 (External pin interrupt 3) */ + #define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type) 19) /* ICU IRQ4 (External pin interrupt 4) */ + #define ICU_IRQ4_IRQn ((IRQn_Type) 19) /* ICU IRQ4 (External pin interrupt 4) */ + #define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type) 20) /* ICU IRQ5 (External pin interrupt 5) */ + #define ICU_IRQ5_IRQn ((IRQn_Type) 20) /* ICU IRQ5 (External pin interrupt 5) */ + #define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type) 21) /* ICU IRQ6 (External pin interrupt 6) */ + #define ICU_IRQ6_IRQn ((IRQn_Type) 21) /* ICU IRQ6 (External pin interrupt 6) */ + #define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type) 22) /* ICU IRQ7 (External pin interrupt 7) */ + #define ICU_IRQ7_IRQn ((IRQn_Type) 22) /* ICU IRQ7 (External pin interrupt 7) */ + #define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type) 23) /* ICU IRQ8 (External pin interrupt 8) */ + #define ICU_IRQ8_IRQn ((IRQn_Type) 23) /* ICU IRQ8 (External pin interrupt 8) */ + #define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type) 24) /* ICU IRQ9 (External pin interrupt 9) */ + #define ICU_IRQ9_IRQn ((IRQn_Type) 24) /* ICU IRQ9 (External pin interrupt 9) */ + #define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type) 25) /* ICU IRQ13 (External pin interrupt 13) */ + #define ICU_IRQ13_IRQn ((IRQn_Type) 25) /* ICU IRQ13 (External pin interrupt 13) */ + #define VECTOR_NUMBER_SCI3_RXI ((IRQn_Type) 26) /* SCI3 RXI (Receive data full) */ + #define SCI3_RXI_IRQn ((IRQn_Type) 26) /* SCI3 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI3_TXI ((IRQn_Type) 27) /* SCI3 TXI (Transmit data empty) */ + #define SCI3_TXI_IRQn ((IRQn_Type) 27) /* SCI3 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI3_TEI ((IRQn_Type) 28) /* SCI3 TEI (Transmit end) */ + #define SCI3_TEI_IRQn ((IRQn_Type) 28) /* SCI3 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI3_ERI ((IRQn_Type) 29) /* SCI3 ERI (Receive error) */ + #define SCI3_ERI_IRQn ((IRQn_Type) 29) /* SCI3 ERI (Receive error) */ + #define VECTOR_NUMBER_SCI4_RXI ((IRQn_Type) 30) /* SCI4 RXI (Receive data full) */ + #define SCI4_RXI_IRQn ((IRQn_Type) 30) /* SCI4 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI4_TXI ((IRQn_Type) 31) /* SCI4 TXI (Transmit data empty) */ + #define SCI4_TXI_IRQn ((IRQn_Type) 31) /* SCI4 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI4_TEI ((IRQn_Type) 32) /* SCI4 TEI (Transmit end) */ + #define SCI4_TEI_IRQn ((IRQn_Type) 32) /* SCI4 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type) 33) /* SCI4 ERI (Receive error) */ + #define SCI4_ERI_IRQn ((IRQn_Type) 33) /* SCI4 ERI (Receive error) */ + #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 34) /* SCI9 RXI (Receive data full) */ + #define SCI9_RXI_IRQn ((IRQn_Type) 34) /* SCI9 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 35) /* SCI9 TXI (Transmit data empty) */ + #define SCI9_TXI_IRQn ((IRQn_Type) 35) /* SCI9 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type) 36) /* SCI9 TEI (Transmit end) */ + #define SCI9_TEI_IRQn ((IRQn_Type) 36) /* SCI9 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 37) /* SCI9 ERI (Receive error) */ + #define SCI9_ERI_IRQn ((IRQn_Type) 37) /* SCI9 ERI (Receive error) */ + #define VECTOR_NUMBER_CAN0_ERROR ((IRQn_Type) 38) /* CAN0 ERROR (Error interrupt) */ + #define CAN0_ERROR_IRQn ((IRQn_Type) 38) /* CAN0 ERROR (Error interrupt) */ + #define VECTOR_NUMBER_CAN0_MAILBOX_RX ((IRQn_Type) 39) /* CAN0 MAILBOX RX (Reception complete interrupt) */ + #define CAN0_MAILBOX_RX_IRQn ((IRQn_Type) 39) /* CAN0 MAILBOX RX (Reception complete interrupt) */ + #define VECTOR_NUMBER_CAN0_MAILBOX_TX ((IRQn_Type) 40) /* CAN0 MAILBOX TX (Transmission complete interrupt) */ + #define CAN0_MAILBOX_TX_IRQn ((IRQn_Type) 40) /* CAN0 MAILBOX TX (Transmission complete interrupt) */ + #define VECTOR_NUMBER_CAN0_FIFO_RX ((IRQn_Type) 41) /* CAN0 FIFO RX (Receive FIFO interrupt) */ + #define CAN0_FIFO_RX_IRQn ((IRQn_Type) 41) /* CAN0 FIFO RX (Receive FIFO interrupt) */ + #define VECTOR_NUMBER_CAN0_FIFO_TX ((IRQn_Type) 42) /* CAN0 FIFO TX (Transmit FIFO interrupt) */ + #define CAN0_FIFO_TX_IRQn ((IRQn_Type) 42) /* CAN0 FIFO TX (Transmit FIFO interrupt) */ + #define VECTOR_NUMBER_FCU_FRDYI ((IRQn_Type) 43) /* FCU FRDYI (Flash ready interrupt) */ + #define FCU_FRDYI_IRQn ((IRQn_Type) 43) /* FCU FRDYI (Flash ready interrupt) */ + #define VECTOR_NUMBER_FCU_FIFERR ((IRQn_Type) 44) /* FCU FIFERR (Flash access error interrupt) */ + #define FCU_FIFERR_IRQn ((IRQn_Type) 44) /* FCU FIFERR (Flash access error interrupt) */ + /* The number of entries required for the ICU vector table. */ + #define BSP_ICU_VECTOR_NUM_ENTRIES (45) + + #ifdef __cplusplus + } + #endif + #endif /* VECTOR_DATA_H */ \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/board_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/board_cfg.h new file mode 100644 index 0000000000..2137658002 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/board_cfg.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "./TARGET_FPB_RA4E1/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_cfg.h new file mode 100644 index 0000000000..0e942c95d2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_cfg.h @@ -0,0 +1,75 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "bsp_mcu_ofs_cfg.h" + #include "board_cfg.h" + #include "vector_data.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #if MBED_CONF_RTOS_PRESENT + #define BSP_CFG_STACK_MAIN_BYTES (MBED_CONF_TARGET_BOOT_STACK_SIZE) + #else + #define BSP_CFG_STACK_MAIN_BYTES (MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE) + #endif + #define BSP_CFG_HEAP_BYTES (0) + #ifdef MBED_DEBUG + #define BSP_CFG_PARAM_CHECKING_ENABLE (1) + #else + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #endif + #define BSP_CFG_ASSERT (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_device_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_device_cfg.h new file mode 100644 index 0000000000..509cd4a2de --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_device_cfg.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_device_pn_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000000..94ee5c56fc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,16 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4E10D2CFM + #define BSP_MCU_FEATURE_SET ('0') + #define BSP_NUMBER_OF_CORES (1) + #define BSP_PACKAGE_QFP + #define BSP_ROM_SIZE_BYTES (524288) + #define BSP_RAM_SIZE_BYTES (131072) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_PINS (64) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_family_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_family_cfg.h new file mode 100644 index 0000000000..675128df7c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_family_cfg.h @@ -0,0 +1,311 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra4e1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA4E1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + + #define BSP_CFG_FLL_ENABLE (0) + + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + + #if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif + + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL + #define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL + #define FPU_FPCCR_TS_VAL (1U) +#endif + #define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL + #define FPU_FPCCR_CLRONRET_VAL (1) +#endif + + /* Type 1 Peripheral Security Attribution */ + + /* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((1 > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((2 > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((1 > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((1 > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((1 > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((1 > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((1 > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((1 > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((1 > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((1 > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((1 > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((1 > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((1 > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((1 > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((1 > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((1 > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((1 > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((1 > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + + /* Type 2 Peripheral Security Attribution */ + + /* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + + /* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR + /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ +#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) +#define BSP_TZ_CFG_LVDSAR (0U) +#else +#define BSP_TZ_CFG_LVDSAR (3U) +#endif +#endif + + /* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((1 > 0) ? 0xFFFFDCEAU : 0xFFFFFFFFU) +#endif + /* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((1 > 0) ? 0xF2E0FC0CU : 0xFFFFFFFFU) +#endif + + /* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFEF402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + + /* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif + + /* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((1 > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((1 > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((1 > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((1 > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((1 > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((1 > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((1 > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((1 > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((1 > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((1 > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((1 > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + + /* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + + /* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((1 > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + + /* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((1 > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + + /* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((1 > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif + + /* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((1 > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif + + /* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED + #define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + + /* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + + /* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ + #define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 0xFFFFFFFCU) +#endif + + /* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + + /* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + + /* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif + /* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + + /* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_ofs_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_ofs_cfg.h new file mode 100644 index 0000000000..23dbc2506a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_mcu_ofs_cfg.h @@ -0,0 +1,25 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_OFS_CFG_H_ +#define BSP_MCU_OFS_CFG_H_ +#ifndef BSP_CFG_OPTION_SETTING_OFS0 +#define OFS_IWDT (0xA001A001 | 1 << 1 | 3 << 2 | 15 << 4 | 3 << 8 | 3 << 10 | 1 << 12 | 1 << 14) +#define OFS_WDT (1 << 17 | 3 << 18 | 15 << 20 | 3 << 24 | 3 << 26 | 1 << 28 | 1 << 30) +#define BSP_CFG_OPTION_SETTING_OFS0 (OFS_IWDT | OFS_WDT) +#endif +#ifndef BSP_CFG_OPTION_SETTING_OFS1_SEC +#define BSP_CFG_OPTION_SETTING_OFS1_SEC_NO_HOCOFRQ (0xFFFFF8F8 | (1 <<2) | (3) | (1 << 8)) + +#define BSP_CFG_OPTION_SETTING_OFS1_SEC ((uint32_t) BSP_CFG_OPTION_SETTING_OFS1_SEC_NO_HOCOFRQ | ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) +#endif +#ifndef BSP_CFG_OPTION_SETTING_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_OPTION_SETTING_OFS1_SEL (4294965496 | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00 : 0U)) +#else + #define BSP_CFG_OPTION_SETTING_OFS1_SEL (4294965496) +#endif +#endif +#endif /* BSP_MCU_OFS_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_pin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_pin_cfg.h new file mode 100644 index 0000000000..14cede38da --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/bsp_pin_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +extern const ioport_cfg_t g_bsp_pin_cfg; /* FPB_RA4E1.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/can_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/can_device.c new file mode 100644 index 0000000000..9d3f080337 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/can_device.c @@ -0,0 +1,11 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "PeripheralNames.h" +#include "hal_data.h" +#include "device.h" + +const can_instance_t * const g_can_instances[CAN_COUNT] = { + &g_can0, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/flash_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/flash_device.h new file mode 100644 index 0000000000..83d68333b2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/flash_device.h @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef FLASH_DEVICE_H +#define FLASH_DEVICE_H + +/* RA4E1: 256KB Code Flash, 8KB Data Flash */ +#ifndef RA_CF_START +#define RA_CF_START (0x00000000u) +#endif +#ifndef RA_CF_SIZE +#define RA_CF_SIZE (256u * 1024u) +#endif +#ifndef RA_CF_WRITE_SIZE +#define RA_CF_WRITE_SIZE (128u) +#endif + +#ifndef RA_DF_START +#define RA_DF_START (0x08000000u) +#endif +#ifndef RA_DF_SIZE +#define RA_DF_SIZE (8u * 1024u) +#endif +#ifndef RA_DF_SECTOR_SIZE +#define RA_DF_SECTOR_SIZE (64u) +#endif +#ifndef RA_DF_WRITE_SIZE +#define RA_DF_WRITE_SIZE (4u) +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/gpio_irq_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/gpio_irq_device.c new file mode 100644 index 0000000000..541533bf8b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/gpio_irq_device.c @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "PeripheralNames.h" +#include "common_data.h" +#include "device.h" + +icu_instance_ctrl_t * const g_icu_ctrl[IRQ_CHANNELS_COUNT] = { + &g_external_irq0_ctrl, + &g_external_irq1_ctrl, + &g_external_irq2_ctrl, + &g_external_irq3_ctrl, + &g_external_irq4_ctrl, + &g_external_irq5_ctrl, + &g_external_irq6_ctrl, + &g_external_irq7_ctrl, + &g_external_irq8_ctrl, + &g_external_irq9_ctrl, + NULL, + NULL, + NULL, + &g_external_irq13_ctrl, +}; + +const external_irq_cfg_t * const g_icu_cfg[IRQ_CHANNELS_COUNT] = { + &g_external_irq0_cfg, + &g_external_irq1_cfg, + &g_external_irq2_cfg, + &g_external_irq3_cfg, + &g_external_irq4_cfg, + &g_external_irq5_cfg, + &g_external_irq6_cfg, + &g_external_irq7_cfg, + &g_external_irq8_cfg, + &g_external_irq9_cfg, + NULL, + NULL, + NULL, + &g_external_irq13_cfg, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/i2c_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/i2c_device.h new file mode 100644 index 0000000000..54b6fd4272 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/i2c_device.h @@ -0,0 +1,21 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef I2C_DEVICE_H +#define I2C_DEVICE_H + +#include "r_iic_master.h" + +typedef struct { + int hz; + iic_master_clock_settings_t clk; +} iic_clock_entry_t; + +static const iic_clock_entry_t g_iic_clock_table[] = { + { 100000, { .cks_value = 3, .brh_value = 28, .brl_value = 28, .sddl_value = 0, .dlcs_value = 0 }}, + { 400000, { .cks_value = 1, .brh_value = 26, .brl_value = 25, .sddl_value = 0, .dlcs_value = 0 }}, + {1000000, { .cks_value = 0, .brh_value = 15, .brl_value = 15, .sddl_value = 0, .dlcs_value = 0 }}, +}; + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/pwmout_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/pwmout_device.h new file mode 100644 index 0000000000..7c771ba0f4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/pwmout_device.h @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "PeripheralNames.h" +#include "hal_data.h" + +const timer_instance_t *pwm_timer_lookup(PWMName name) +{ + switch (name) { + case PWM_GPT1: return &g_timer_gpt1; + case PWM_GPT2: return &g_timer_gpt2; + case PWM_GPT4: return &g_timer_gpt4; + case PWM_GPT5: return &g_timer_gpt5; + case PWM_AGT0: return &g_timer_agt0; + case PWM_AGT1: return &g_timer_agt1; + case PWM_AGT2: return &g_timer_agt2; + case PWM_AGT3: return &g_timer_agt3; + case PWM_AGT5: return &g_timer_agt5; + default: return NULL; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_acmphs_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_acmphs_cfg.h new file mode 100644 index 0000000000..fc8046a7f5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_acmphs_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ACMPHS_CFG_H_ +#define R_ACMPHS_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ACMPHS_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ACMPHS_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_acmplp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_acmplp_cfg.h new file mode 100644 index 0000000000..a66ead8b31 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_acmplp_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ACMPLP_CFG_H_ +#define R_ACMPLP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ACMPLP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ACMPLP_CFG_CH1_IVREF0_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_ACMPLP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_adc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_adc_cfg.h new file mode 100644 index 0000000000..d16c3e39e7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_adc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ADC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_agt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_agt_cfg.h new file mode 100644 index 0000000000..0e70aee2cd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_agt_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define AGT_CFG_OUTPUT_SUPPORT_ENABLE (1) + #define AGT_CFG_INPUT_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_AGT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cac_cfg.h new file mode 100644 index 0000000000..a399409760 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CAC_CFG_H_ +#define R_CAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_can_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_can_cfg.h new file mode 100644 index 0000000000..ad74a28367 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_can_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CAN_CFG_H_ +#define R_CAN_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CAN_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define CAN_CFG_FIFO_SUPPORT (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_CAN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_canfd_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_canfd_cfg.h new file mode 100644 index 0000000000..827af7d985 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_canfd_cfg.h @@ -0,0 +1,158 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CANFD_CFG_H_ +#define R_CANFD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CANFD_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #define CANFD_CFG_AFL_CH0_RULE_NUM (32) + #define CANFD_CFG_AFL_CH1_RULE_NUM (0) + + #define CANFD_CFG_GLOBAL_ERROR_CH (config.driver.canfd.global_err.cb_channel.0) + + #define CANFD_CFG_FD_PROTOCOL_EXCEPTION ((0)) + #define CANFD_CFG_GLOBAL_ERR_IPL ((12)) + #define CANFD_CFG_RX_FIFO_IPL ((12)) + #define CANFD_CFG_GLOBAL_ERR_SOURCES ( 0x3) + #define CANFD_CFG_TX_PRIORITY ((R_CANFD_CFDGCFG_TPRI_Msk)) + #define CANFD_CFG_DLC_CHECK ((0)) + #define CANFD_CFG_FD_OVERFLOW ((0)) + #define CANFD_CFG_RXMB_NUMBER (0) + #define CANFD_CFG_RXMB_SIZE ((0)) + #define CANFD_CFG_RXFIFO0_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO0_DEPTH () + #define CANFD_CFG_RXFIFO0_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO0_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO0_ENABLE ((1)) + + #define CANFD_CFG_RXFIFO1_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO1_DEPTH () + #define CANFD_CFG_RXFIFO1_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO1_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO1_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO2_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO2_DEPTH () + #define CANFD_CFG_RXFIFO2_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO2_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO2_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO3_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO3_DEPTH () + #define CANFD_CFG_RXFIFO3_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO3_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO3_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO4_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO4_DEPTH () + #define CANFD_CFG_RXFIFO4_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO4_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO4_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO5_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO5_DEPTH () + #define CANFD_CFG_RXFIFO5_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO5_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO5_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO6_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO6_DEPTH () + #define CANFD_CFG_RXFIFO6_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO6_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO6_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO7_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO7_DEPTH () + #define CANFD_CFG_RXFIFO7_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO7_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO7_ENABLE ((0)) + + #define CANFD_CFG_COMMONFIFO0 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ( << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ( << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO1 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ( << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ( << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO2 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ( << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ( << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO3 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ( << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ( << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO4 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ( << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ( << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO5 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ( << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ( << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + + #ifdef __cplusplus + } + #endif +#endif /* R_CANFD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cec_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cec_cfg.h new file mode 100644 index 0000000000..8a583197f2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cec_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CEC_CFG_H_ +#define R_CEC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CEC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define CEC_DATA_BUFFER_LENGTH (14) + + #ifdef __cplusplus + } + #endif +#endif /* R_CEC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ceu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ceu_cfg.h new file mode 100644 index 0000000000..12c0fd54f8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ceu_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CEU_CFG_H_ +#define R_CEU_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CEU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CEU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cgc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cgc_cfg.h new file mode 100644 index 0000000000..ffbf789754 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_cgc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CGC_CFG_H_ +#define R_CGC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CGC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define CGC_CFG_USE_LOW_VOLTAGE_MODE RA_NOT_DEFINED + +#ifdef __cplusplus +} +#endif +#endif /* R_CGC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_crc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_crc_cfg.h new file mode 100644 index 0000000000..5de5d44d04 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_crc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CRC_CFG_H_ +#define R_CRC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CRC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CRC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ctsu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ctsu_cfg.h new file mode 100644 index 0000000000..846940d95b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ctsu_cfg.h @@ -0,0 +1,237 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CTSU_CFG_H_ +#define R_CTSU_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CTSU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define CTSU_CFG_DTC_SUPPORT_ENABLE (0) + #define CTSU_CFG_INT_PRIORITY_LEVEL (12) + #define CTSU_CFG_AUTO_JUDGE_ENABLE (0) + #ifndef QE_TOUCH_CONFIGURATION + #define CTSU_CFG_NUM_SELF_ELEMENTS (1) + #define CTSU_CFG_NUM_MUTUAL_ELEMENTS (0) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + #define CTSU_CFG_MAJORITY_MODE (2) + #define CTSU_CFG_NUM_AUTOJUDGE_SELF_ELEMENTS (1) + #define CTSU_CFG_NUM_AUTOJUDGE_MUTUAL_ELEMENTS (0) + #define CTSU_CFG_AUTO_CORRECTION_ENABLE (1) + #else + #define CTSU_CFG_MAJORITY_MODE (1) + #define CTSU_CFG_NUM_AUTOJUDGE_SELF_ELEMENTS (0) + #define CTSU_CFG_NUM_AUTOJUDGE_MUTUAL_ELEMENTS (0) + #define CTSU_CFG_AUTO_CORRECTION_ENABLE (0) + #endif + #define CTSU_CFG_LOW_VOLTAGE_MODE (0) + #define CTSU_CFG_PCLK_DIVISION (0) + #define CTSU_CFG_TSCAP_PORT (0xFFFF) + #define CTSU_CFG_VCC_MV (5000) + #define CTSU_CFG_DIAG_SUPPORT_ENABLE (0) + #if (BSP_FEATURE_CTSU_VERSION == 2) + #define CTSU_CFG_NUM_CFC (0) + #define CTSU_CFG_NUM_CFC_TX (0) + #define CTSU_CFG_NUM_SUMULTI (3) + #define CTSU_CFG_SUMULTI0 (0x3F) + #define CTSU_CFG_SUMULTI1 (0x36) + #define CTSU_CFG_SUMULTI2 (0x48) + #define CTSU_CFG_TEMP_CORRECTION_SUPPORT (0) + #define CTSU_CFG_TEMP_CORRECTION_TS (0) + #define CTSU_CFG_TEMP_CORRECTION_TIME (0) + #define CTSU_CFG_CALIB_RTRIM_SUPPORT (0) + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + #define CTSU_CFG_NUM_SUMULTI (1) + #endif + #endif + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + #if (BSP_FEATURE_CTSU_VERSION == 1) + #if (BSP_CFG_MCU_PART_SERIES == 2) || (BSP_CFG_MCU_PART_SERIES == 4) + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (54888) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (29062) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (3269) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (705) + #define CTSU_CFG_DIAG_SSCG_MAX (21813) + #define CTSU_CFG_DIAG_SSCG_MIN (11782) + #define CTSU_CFG_DIAG_DAC1_MAX (20422) + #define CTSU_CFG_DIAG_DAC2_MAX (21532) + #define CTSU_CFG_DIAG_DAC3_MAX (23015) + #define CTSU_CFG_DIAG_DAC4_MAX (25923) + #define CTSU_CFG_DIAG_DAC5_MAX (32016) + #define CTSU_CFG_DIAG_DAC6_MAX (45795) + #define CTSU_CFG_DIAG_DAC1_MIN (12492) + #define CTSU_CFG_DIAG_DAC2_MIN (14053) + #define CTSU_CFG_DIAG_DAC3_MIN (15322) + #define CTSU_CFG_DIAG_DAC4_MIN (18070) + #define CTSU_CFG_DIAG_DAC5_MIN (23262) + #define CTSU_CFG_DIAG_DAC6_MIN (33446) + + #else + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (43910) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (23249) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (2615) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (564) + #define CTSU_CFG_DIAG_SSCG_MAX (21813) + #define CTSU_CFG_DIAG_SSCG_MIN (11782) + #define CTSU_CFG_DIAG_DAC1_MAX (16599) + #define CTSU_CFG_DIAG_DAC2_MAX (17226) + #define CTSU_CFG_DIAG_DAC3_MAX (18412) + #define CTSU_CFG_DIAG_DAC4_MAX (20738) + #define CTSU_CFG_DIAG_DAC5_MAX (25613) + #define CTSU_CFG_DIAG_DAC6_MAX (36636) + #define CTSU_CFG_DIAG_DAC1_MIN (9994) + #define CTSU_CFG_DIAG_DAC2_MIN (11242) + #define CTSU_CFG_DIAG_DAC3_MIN (12258) + #define CTSU_CFG_DIAG_DAC4_MIN (14456) + #define CTSU_CFG_DIAG_DAC5_MIN (18610) + #define CTSU_CFG_DIAG_DAC6_MIN (26757) + #endif + #endif + #if (BSP_CFG_MCU_PART_SERIES == 6) + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (36873) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (24433) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (1781) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (105) + #define CTSU_CFG_DIAG_SSCG_MAX (17795) + #define CTSU_CFG_DIAG_SSCG_MIN (9610) + #define CTSU_CFG_DIAG_DAC1_MAX (20422) + #define CTSU_CFG_DIAG_DAC2_MAX (21532) + #define CTSU_CFG_DIAG_DAC3_MAX (23015) + #define CTSU_CFG_DIAG_DAC4_MAX (25923) + #define CTSU_CFG_DIAG_DAC5_MAX (32016) + #define CTSU_CFG_DIAG_DAC6_MAX (45795) + #define CTSU_CFG_DIAG_DAC1_MIN (12492) + #define CTSU_CFG_DIAG_DAC2_MIN (14053) + #define CTSU_CFG_DIAG_DAC3_MIN (15322) + #define CTSU_CFG_DIAG_DAC4_MIN (18070) + #define CTSU_CFG_DIAG_DAC5_MIN (23262) + #define CTSU_CFG_DIAG_DAC6_MIN (33446) + #endif + #endif + + #if (BSP_FEATURE_CTSU_VERSION == 2) + #define CTSU_DIAG_TSCAP_RANGE_LOW (1050) + #define CTSU_DIAG_TSCAP_RANGE_HIGH (1419) + + #define CTSU_CFG_DIAG_LOAD_REISTER_MIN (11951) + #define CTSU_CFG_DIAG_LOAD_REISTER_MAX (23957) + + #define CTSU_CFG_DIAG_CURRENT_SOURCE_DIFF_MIN (2890) + #define CTSU_CFG_DIAG_CURRENT_SOURCE_DIFF_MAX (5703) + + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CFG_DIAG_DAC1_MIN (1486) + #define CTSU_CFG_DIAG_DAC2_MIN (2890) + #define CTSU_CFG_DIAG_DAC3_MIN (4202) + #define CTSU_CFG_DIAG_DAC4_MIN (5448) + #define CTSU_CFG_DIAG_DAC5_MIN (6641) + #define CTSU_CFG_DIAG_DAC6_MIN (7787) + #define CTSU_CFG_DIAG_DAC7_MIN (8891) + #define CTSU_CFG_DIAG_DAC8_MIN (9954) + #define CTSU_CFG_DIAG_DAC9_MIN (10974) + #define CTSU_CFG_DIAG_DAC10_MIN (11951) + #define CTSU_CFG_DIAG_DAC11_MIN (12880) + #define CTSU_CFG_DIAG_DAC12_MIN (13761) + + #define CTSU_CFG_DIAG_DAC1_MAX (3057) + #define CTSU_CFG_DIAG_DAC2_MAX (5703) + #define CTSU_CFG_DIAG_DAC3_MAX (8292) + #define CTSU_CFG_DIAG_DAC4_MAX (10838) + #define CTSU_CFG_DIAG_DAC5_MAX (13269) + #define CTSU_CFG_DIAG_DAC6_MAX (15593) + #define CTSU_CFG_DIAG_DAC7_MAX (17816) + #define CTSU_CFG_DIAG_DAC8_MAX (19948) + #define CTSU_CFG_DIAG_DAC9_MAX (21992) + #define CTSU_CFG_DIAG_DAC10_MAX (23957) + #define CTSU_CFG_DIAG_DAC11_MAX (25843) + #define CTSU_CFG_DIAG_DAC12_MAX (27651) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MIN (1384) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MIN (1293) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MIN (1228) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MIN (1176) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MIN (1129) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MIN (1083) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MIN (1037) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MIN (987) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MIN (929) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MIN (867) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MIN (807) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MAX (2781) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MAX (2678) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MAX (2567) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MAX (2458) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MAX (2355) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MAX (2255) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MAX (2166) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MAX (2077) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MAX (1998) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MAX (1921) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MAX (1841) + #else + + #define CTSU_CFG_DIAG_DAC1_MIN (1039) + #define CTSU_CFG_DIAG_DAC2_MIN (2113) + #define CTSU_CFG_DIAG_DAC3_MIN (3130) + #define CTSU_CFG_DIAG_DAC4_MIN (4108) + #define CTSU_CFG_DIAG_DAC5_MIN (5049) + #define CTSU_CFG_DIAG_DAC6_MIN (5961) + #define CTSU_CFG_DIAG_DAC7_MIN (6848) + #define CTSU_CFG_DIAG_DAC8_MIN (7713) + #define CTSU_CFG_DIAG_DAC9_MIN (8554) + #define CTSU_CFG_DIAG_DAC10_MIN (9374) + #define CTSU_CFG_DIAG_DAC11_MIN (10176) + #define CTSU_CFG_DIAG_DAC12_MIN (10945) + + #define CTSU_CFG_DIAG_DAC1_MAX (2627) + #define CTSU_CFG_DIAG_DAC2_MAX (4899) + #define CTSU_CFG_DIAG_DAC3_MAX (6974) + #define CTSU_CFG_DIAG_DAC4_MAX (8907) + #define CTSU_CFG_DIAG_DAC5_MAX (10729) + #define CTSU_CFG_DIAG_DAC6_MAX (12476) + #define CTSU_CFG_DIAG_DAC7_MAX (14314) + #define CTSU_CFG_DIAG_DAC8_MAX (16089) + #define CTSU_CFG_DIAG_DAC9_MAX (17802) + #define CTSU_CFG_DIAG_DAC10_MAX (19462) + #define CTSU_CFG_DIAG_DAC11_MAX (21067) + #define CTSU_CFG_DIAG_DAC12_MAX (22624) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MIN (1081) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MIN (1013) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MIN (967) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MIN (929) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MIN (899) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MIN (867) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MIN (844) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MIN (821) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MIN (794) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MIN (762) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MIN (733) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MAX (2273) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MAX (2118) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MAX (2044) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MAX (1975) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MAX (1909) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MAX (1846) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MAX (1786) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MAX (1731) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MAX (1679) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MAX (1632) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MAX (1581) + #endif + #define CTSU_CFG_DIAG_CLOCK_RECOV_RANGE (20) + #endif + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_CTSU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dac_cfg.h new file mode 100644 index 0000000000..3db92ccc0a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DAC_CFG_H_ +#define R_DAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dmac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dmac_cfg.h new file mode 100644 index 0000000000..c772854a59 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dmac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DMAC_CFG_H_ +#define R_DMAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DMAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DMAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_doc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_doc_cfg.h new file mode 100644 index 0000000000..0124272c17 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_doc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DOC_CFG_H_ +#define R_DOC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DOC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DOC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_drw_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_drw_cfg.h new file mode 100644 index 0000000000..7ca818be9a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_drw_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DRW_CFG_H_ +#define R_DRW_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define DRW_CFG_USE_DLIST_INDIRECT ((1)) + #ifdef VECTOR_NUMBER_DRW_INT + #define DRW_CFG_INT_IRQ (VECTOR_NUMBER_DRW_INT) + #endif + #define DRW_CFG_CUSTOM_MALLOC ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_DRW_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dsmif_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dsmif_cfg.h new file mode 100644 index 0000000000..2c656fa920 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dsmif_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DSMIF_CFG_H_ +#define R_DSMIF_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DSMIF_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) +#define DSMIF_CFG_ERROR_DETECTION_SUPPORT ((1)) + +#ifdef __cplusplus +} +#endif +#endif /* R_DSMIF_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dtc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dtc_cfg.h new file mode 100644 index 0000000000..cd2f683dcf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_dtc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME BSP_UNINIT_SECTION_PREFIX ".fsp_dtc_vector_table" + +#ifdef __cplusplus +} +#endif +#endif /* R_DTC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_edmac.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_edmac.h new file mode 100644 index 0000000000..ff59ea997f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_edmac.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_EDMAC_H_ +#define R_EDMAC_H_ + +#endif /* R_EDMAC_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_elc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_elc_cfg.h new file mode 100644 index 0000000000..00864564b1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_elc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ELC_CFG_H_ +#define R_ELC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ELC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ELC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ether_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ether_cfg.h new file mode 100644 index 0000000000..34341ea337 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ether_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHER_CFG_H_ +#define R_ETHER_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ETHER_CFG_LINK_PRESENT (0) + #define ETHER_CFG_USE_LINKSTA (0) + #define ETHER_CFG_READ_BUFFER_SIZE_CHECK ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHER_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ether_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ether_phy_cfg.h new file mode 100644 index 0000000000..f84bae1260 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ether_phy_cfg.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHER_PHY_CFG_H_ +#define R_ETHER_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHER_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_DP83620_ENABLE + #define ETHER_PHY_CFG_TARGET_DP83620_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + #define ETHER_PHY_CFG_USE_REF_CLK (BOARD_PHY_REF_CLK) + #define ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHER_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ethercat_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ethercat_phy_cfg.h new file mode 100644 index 0000000000..d9c71487c8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ethercat_phy_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHERCAT_PHY_CFG_H_ +#define R_ETHERCAT_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHERCAT_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_flash_hp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_flash_hp_cfg.h new file mode 100644 index 0000000000..1aa7941ae2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_flash_hp_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_HP_CFG_H_ +#define R_FLASH_HP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) + #define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_FLASH_HP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_flash_lp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_flash_lp_cfg.h new file mode 100644 index 0000000000..f67c25a7b5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_flash_lp_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_LP_CFG_H_ +#define R_FLASH_LP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (0) + #define FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE 0 + #define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1) + #define FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE (1) + #define FLASH_LP_CFG_DUAL_BANK_INSTANT_SWAP 0 + + #ifdef __cplusplus + } + #endif +#endif /* R_FLASH_LP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_glcdc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_glcdc_cfg.h new file mode 100644 index 0000000000..eea5f0ca27 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_glcdc_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GLCDC_CFG_H_ +#define R_GLCDC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define GLCDC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define GLCDC_CFG_COLOR_CORRECTION_ENABLE (false) + + /* Enable DSI function handling */ + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define GLCDC_CFG_USING_DSI + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_GLCDC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gpt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gpt_cfg.h new file mode 100644 index 0000000000..d7caf17ca7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gpt_cfg.h @@ -0,0 +1,25 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPT_CFG_H_ +#define R_GPT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (1) +#define GPT_CFG_WRITE_PROTECT_ENABLE (0) + +#ifndef BSP_CFG_GPT_COUNT_CLOCK_SOURCE +#define GPT_CFG_GPTCLK_BYPASS (0) +#else +#define GPT_CFG_GPTCLK_BYPASS (BSP_CFG_GPT_COUNT_CLOCK_SOURCE) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* R_GPT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gpt_three_phase_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gpt_three_phase_cfg.h new file mode 100644 index 0000000000..d97d29d768 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gpt_three_phase_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPT_THREE_PHASE_CFG_H_ +#define R_GPT_THREE_PHASE_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_GPT_THREE_PHASE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gptp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gptp_cfg.h new file mode 100644 index 0000000000..f23e684f73 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_gptp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPTP_CFG_H_ +#define R_GPTP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define GPTP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_GPTP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_i3c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_i3c_cfg.h new file mode 100644 index 0000000000..1206dbd04a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_i3c_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_I3C_CFG_H_ +#define R_I3C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define I3C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define I3C_CFG_UNALIGNED_BUFFER_SUPPORT (1) +#define I3C_CFG_MASTER_SUPPORT (1) +#define I3C_CFG_SLAVE_SUPPORT (1) +#define I3C_CFG_ERROR_RECOVERY_SUPPORT + +#ifdef __cplusplus +} +#endif +#endif /* R_I3C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_icu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_icu_cfg.h new file mode 100644 index 0000000000..8422be1b4b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_icu_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ICU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iic_master_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iic_master_cfg.h new file mode 100644 index 0000000000..9485301407 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iic_master_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IIC_MASTER_CFG_H_ +#define R_IIC_MASTER_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_MASTER_CFG_DTC_ENABLE (0) +#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iic_slave_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iic_slave_cfg.h new file mode 100644 index 0000000000..dce97700e0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iic_slave_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IIC_SLAVE_CFG_H_ +#define R_IIC_SLAVE_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_SLAVE_CFG_DTC_ENABLE (0) +#ifdef __cplusplus +} +#endif +#endif /* R_IIC_SLAVE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iirfa_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iirfa_cfg.h new file mode 100644 index 0000000000..8078ee15be --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iirfa_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IIRFA_CFG_H_ +#define R_IIRFA_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIRFA_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIRFA_CFG_LOOP_UNROLL_DEPTH (1) +#define IIRFA_CFG_LOOP_USE_POLLING (1) +#define IIRFA_CFG_ECC_SUPPORT (1) +#define IIRFA_CFG_ROUNDING_MODE (0) + + +#ifdef __cplusplus +} +#endif +#endif /* R_IIRFA_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ioport_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ioport_cfg.h new file mode 100644 index 0000000000..519ac3734a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ioport_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IOPORT_CFG_CCD_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ipc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ipc_cfg.h new file mode 100644 index 0000000000..7968dbcc75 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ipc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IPC_CFG_H_ +#define R_IPC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define IPC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_IPC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iwdt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iwdt_cfg.h new file mode 100644 index 0000000000..e097d20442 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_iwdt_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IWDT_CFG_H_ +#define R_IWDT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IWDT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IWDT_CFG_REGISTER_START_NMI_SUPPORTED ((0)) + +#ifdef __cplusplus +} +#endif +#endif /* R_IWDT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_jpeg_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_jpeg_cfg.h new file mode 100644 index 0000000000..9149d6c8fa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_jpeg_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_JPEG_CFG_H_ +#define R_JPEG_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define JPEG_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define JPEG_CFG_DECODE_ENABLE (1) + #define JPEG_CFG_ENCODE_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_JPEG_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_kint_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_kint_cfg.h new file mode 100644 index 0000000000..765da0d361 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_kint_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_KINT_CFG_H_ +#define R_KINT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define KINT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_KINT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_layer3_switch_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_layer3_switch_cfg.h new file mode 100644 index 0000000000..a74af95b70 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_layer3_switch_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LAYER3_SWITCH_CFG_H_ +#define R_LAYER3_SWITCH_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #define LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM (4) + + #define LAYER3_SWITCH_CFG_GPTP_ENABLE (1) + + #define LAYER3_SWITCH_CFG_TAS_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_LAYER3_SWITCH_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_lpm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_lpm_cfg.h new file mode 100644 index 0000000000..be928d2cb6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_lpm_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define LPM_CFG_STANDBY_LIMIT (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_LPM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_lvd_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_lvd_cfg.h new file mode 100644 index 0000000000..c8160e206d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_lvd_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LVD_CFG_H_ +#define R_LVD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LVD_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_LVD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mipi_csi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mipi_csi_cfg.h new file mode 100644 index 0000000000..06ccb51e46 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mipi_csi_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MIPI_CSI_CFG_H_ +#define R_MIPI_CSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MIPI_CSI_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_MIPI_CSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mipi_dsi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mipi_dsi_cfg.h new file mode 100644 index 0000000000..7acc8a1dda --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mipi_dsi_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MIPI_DSI_CFG_H_ +#define R_MIPI_DSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MIPI_DSI_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_MIPI_DSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mram_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mram_cfg.h new file mode 100644 index 0000000000..35aca39883 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_mram_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MRAM_CFG_H_ +#define R_MRAM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MRAM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_MRAM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_opamp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_opamp_cfg.h new file mode 100644 index 0000000000..2a4387e532 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_opamp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_OPAMP_CFG_H_ +#define R_OPAMP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define OPAMP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_OPAMP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ospi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ospi_cfg.h new file mode 100644 index 0000000000..fa170f5458 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ospi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_OSPI_CFG_H_ +#define R_OSPI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define OSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define OSPI_CFG_DMAC_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_OSPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_pdc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_pdc_cfg.h new file mode 100644 index 0000000000..509a1e4eb0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_pdc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PDC_CFG_H_ +#define R_PDC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define PDC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_PDC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_pdm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_pdm_cfg.h new file mode 100644 index 0000000000..8a3cd6c1bd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_pdm_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PDM_CFG_H_ +#define R_PDM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define PDM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define PDM_CFG_DMAC_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_PDM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_poeg_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_poeg_cfg.h new file mode 100644 index 0000000000..4bd1a5b99b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_poeg_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_POEG_CFG_H_ +#define R_POEG_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define POEG_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_POEG_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ptp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ptp_cfg.h new file mode 100644 index 0000000000..81182a841a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ptp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PTP_CFG_H_ +#define R_PTP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define PTP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_PTP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_qspi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_qspi_cfg.h new file mode 100644 index 0000000000..663afaefbc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_qspi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_QSPI_CFG_H_ +#define R_QSPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define QSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_QSPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rmac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rmac_cfg.h new file mode 100644 index 0000000000..b596fd0243 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rmac_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RMAC_CFG_H_ +#define R_RMAC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define RMAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define RMAC_CFG_READ_BUFFER_SIZE_CHECK ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_RMAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rmac_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rmac_phy_cfg.h new file mode 100644 index 0000000000..3268e93ff5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rmac_phy_cfg.h @@ -0,0 +1,36 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RMAC_PHY_CFG_H_ +#define R_RMAC_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define RMAC_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_DP83620_ENABLE + #define ETHER_PHY_CFG_TARGET_DP83620_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_GPY111_ENABLE + #define ETHER_PHY_CFG_TARGET_GPY111_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + #define ETHER_PHY_CFG_USE_REF_CLK (BOARD_PHY_REF_CLK) + + #ifdef __cplusplus + } + #endif +#endif /* R_RMAC_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rtc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rtc_cfg.h new file mode 100644 index 0000000000..12bff296fb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_rtc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define RTC_CFG_OPEN_SET_CLOCK_SOURCE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_RTC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_i2c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_i2c_cfg.h new file mode 100644 index 0000000000..cbd57f790b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_i2c_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_I2C_CFG_H_ +#define R_SAU_I2C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_I2C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_I2C_CFG_CRITICAL_SECTION_ENABLE (0) +#define SAU_I2C_CFG_MANUAL_START_STOP_ENABLE (0) +#define SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE config.driver.sau_i2c.single_channel_enable.disabled +#define SAU_I2C_CFG_RESTART_ENABLE (1) +#define SAU_I2C_CFG_DTC_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_I2C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_lin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_lin_cfg.h new file mode 100644 index 0000000000..cccc438932 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_lin_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_LIN_CFG_H_ +#define R_SAU_LIN_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_LIN_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE (1) +#define SAU_LIN_CFG_MASTER_SUPPORT_ENABLE (0) +#define SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE (1) +#define SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE (0) +#define SAU_LIN_AUTO_SYNC_SUPPORT_ENABLE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_LIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_spi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_spi_cfg.h new file mode 100644 index 0000000000..e381c0b8b3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_spi_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_SPI_CFG_H_ +#define R_SAU_SPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_SPI_CFG_CRITICAL_SECTION_ENABLE (0) +#define SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE config.driver.sau_spi.single_channel_enable.disabled +#define SAU_SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_SPI_TRANSFER_OPERATION_MODE (SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION) +#define SAU_SPI_CFG_DTC_SUPPORT_ENABLE (0) +#define SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE (0) +#define SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_SPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_uart_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_uart_cfg.h new file mode 100644 index 0000000000..81f1635ccc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sau_uart_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_UART_CFG_H_ +#define R_SAU_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SAU_UART_CFG_CRITICAL_SECTION_ENABLE (0) + #define SAU_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SAU_UART_CFG_DTC_SUPPORT_ENABLE (0) + #define SAU_UART_CFG_SINGLE_CHANNEL config.driver.sau_uart.single_channel.disabled + #define SAU_UART_CFG_FIXED_BAUDRATE_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_SAU_UART_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sce_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sce_cfg.h new file mode 100644 index 0000000000..58568881a0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sce_cfg.h @@ -0,0 +1,15 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCE_CFG_H_ +#define R_SCE_CFG_H_ +#define SCE_RSA_RETRY_COUNT_FOR_RSA_KEY_GENERATION 10240 + #define SCE_USER_SHA_384_ENABLED (0) + #define SCE_USER_SHA_384_FUNCTION crypto_sha384_user_function + #ifndef SCE_USER_FAST_BOOT + #define SCE_USER_FAST_BOOT (0) + #define SCE_CFG_PARAM_CHECKING_ENABLE BSP_CFG_PARAM_CHECKING_ENABLE + #endif +#endif /* R_SCE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_i2c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_i2c_cfg.h new file mode 100644 index 0000000000..1f4bf5af8e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_i2c_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_I2C_CFG_H_ +#define R_SCI_I2C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_I2C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_I2C_CFG_DTC_ENABLE (0) +#define SCI_I2C_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_I2C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_lin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_lin_cfg.h new file mode 100644 index 0000000000..88134f91d3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_lin_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_LIN_CFG_H_ +#define R_SCI_LIN_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SCI_LIN_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SCI_LIN_CHECKSUM_SUPPORT_ENABLE (1) + #define SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE (0) + #define SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_SCI_LIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_smci_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_smci_cfg.h new file mode 100644 index 0000000000..39c3ec3d52 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_smci_cfg.h @@ -0,0 +1,15 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_SMCI_CFG_H_ +#define R_SCI_SMCI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define SCI_SMCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_SMCI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_spi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_spi_cfg.h new file mode 100644 index 0000000000..441e96d140 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_spi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_SPI_CFG_H_ +#define R_SCI_SPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_SPI_DTC_SUPPORT_ENABLE (1) +#define SCI_SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_SPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_uart_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_uart_cfg.h new file mode 100644 index 0000000000..e9664c9170 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sci_uart_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SCI_UART_CFG_FIFO_SUPPORT (1) + #define SCI_UART_CFG_DTC_SUPPORTED (0) + #define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) + #define SCI_UART_CFG_RS485_SUPPORT (0) + #define SCI_UART_CFG_IRDA_SUPPORT (0) + #ifdef __cplusplus + } + #endif +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sdadc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sdadc_cfg.h new file mode 100644 index 0000000000..b54b68020f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sdadc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SDADC_CFG_H_ +#define R_SDADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SDADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_SDADC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sdhi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sdhi_cfg.h new file mode 100644 index 0000000000..d825b389ef --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_sdhi_cfg.h @@ -0,0 +1,24 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SDHI_CFG_H_ +#define R_SDHI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SDHI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SDMMC_CFG_UNALIGNED_ACCESS_ENABLE (1) + #ifndef SDHI_CFG_SD_SUPPORT_ENABLE + #define SDHI_CFG_SD_SUPPORT_ENABLE ((1)) + #endif + #ifndef SDHI_CFG_EMMC_SUPPORT_ENABLE + #define SDHI_CFG_EMMC_SUPPORT_ENABLE ((0)) + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_SDHI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_spi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_spi_cfg.h new file mode 100644 index 0000000000..eedbdfc959 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_spi_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SPI_DMA_SUPPORT_ENABLE (1) + #define SPI_TRANSMIT_FROM_RXI_ISR (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_SPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ssi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ssi_cfg.h new file mode 100644 index 0000000000..a6ec1f79e0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ssi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SSI_CFG_H_ +#define R_SSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SSI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SSI_CFG_DTC_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_SSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tau_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tau_cfg.h new file mode 100644 index 0000000000..c92f1d8daa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tau_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TAU_CFG_H_ +#define R_TAU_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define TAU_CFG_INTERRUPT_SUPPORT_ENABLE (1) + #define TAU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define TAU_CFG_OUTPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_INPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_EXTRA_INPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_8BIT_MODE_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_TAU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tau_pwm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tau_pwm_cfg.h new file mode 100644 index 0000000000..bd9b7f09af --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tau_pwm_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TAU_PWM_CFG_H_ +#define R_TAU_PWM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define TAU_PWM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE (0) + #define TAU_PWM_CFG_PWM_MODE_ENABLE (1) + #define TAU_PWM_CFG_MULTI_SLAVE_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_TAU_PWM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tml_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tml_cfg.h new file mode 100644 index 0000000000..d05ca45c63 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_tml_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TML_CFG_H_ +#define R_TML_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define TML_CFG_CRITICAL_SECTION_ENABLE (0) +#define TML_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define TML_CFG_16_BIT_CAPTURE_MODE_ENABLE (0) +#define TML_CFG_SINGLE_CHANNEL_ENABLE (0) +#define TML_CFG_INTERRUPT_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_TML_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_uarta_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_uarta_cfg.h new file mode 100644 index 0000000000..b57d6dfeb3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_uarta_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_UARTA_CFG_H_ +#define R_UARTA_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define UARTA_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define UARTA_CFG_DTC_SUPPORT_ENABLE + #define UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE 1 + #ifdef __cplusplus + } + #endif +#endif /* R_UARTA_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ulpt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ulpt_cfg.h new file mode 100644 index 0000000000..b931fda89d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_ulpt_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ULPT_CFG_H_ +#define R_ULPT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ULPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ULPT_CFG_OUTPUT_SUPPORT_ENABLE (0) + #define ULPT_CFG_INPUT_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_ULPT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_usb_basic_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_usb_basic_cfg.h new file mode 100644 index 0000000000..c62ab39d43 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_usb_basic_cfg.h @@ -0,0 +1,138 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_USB_BASIC_CFG_H_ +#define R_USB_BASIC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #ifndef NULL + extern const uint16_t NULL[]; + #endif + + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #include "r_usb_hcdc_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #define USB_CFG_HCDC_ECM_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HHID_USE + #include "r_usb_hhid_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HMSC_USE + #include "r_usb_hmsc_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HVND_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HAUD_USE + #endif + #if ((RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED)) + #define USB_CFG_PCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PCDC2_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID2_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PVND_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HUVC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_DFU_USE + #endif + #if ((RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED)) + #define USB_CFG_OTG_USE + #endif + #if (defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HPRN_USE) || defined(USB_CFG_HMSC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HVND_USE) || defined(USB_CFG_HUVC_USE) || defined(USB_CFG_HAUD_USE)) + #define USB_CFG_HOST_MODE 1 + #else + #define USB_CFG_HOST_MODE 0 + #endif + + #if (defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE) || defined(USB_CFG_PMSC_USE) || defined(USB_CFG_PHID_USE) || defined(USB_CFG_PVND_USE) || defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE) || defined(USB_CFG_PAUD_USE)) + #define USB_CFG_PERI_MODE 2 + #else + #define USB_CFG_PERI_MODE 0 + #endif + + #define USB_CFG_MODE (USB_CFG_PERI_MODE | USB_CFG_HOST_MODE) + #define USB_CFG_MULTIPORT (USB_CFG_DISABLE) + #define USB_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define USB_CFG_CLKSEL (USB_CFG_24MHZ) + #define USB_CFG_BUSWAIT (USB_CFG_BUSWAIT_0) + #define USB_CFG_BC (USB_CFG_DISABLE) + #define USB_CFG_VBUS (USB_CFG_HIGH) + #define USB_CFG_DCP (USB_CFG_DISABLE) + #define USB_CFG_CLASS_REQUEST (USB_CFG_ENABLE) + #define USB_CFG_DBLB (USB_CFG_DBLBON) + #define USB_CFG_CNTMD (USB_CFG_CNTMDOFF) + #define USB_CFG_LDO_REGULATOR (USB_CFG_DISABLE) + #define USB_CFG_TYPEC_FEATURE (RA_NOT_DEFINED) + #define USB_CFG_DMA_DTC_DISABLED (USB_CFG_ENABLE) + #define USB_CFG_TPLCNT (1) + #define USB_CFG_TPL USB_NOVENDOR, USB_NOPRODUCT + #define USB_CFG_TPL_TABLE NULL + #define USB_CFG_COMPLIANCE (USB_CFG_DISABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_USB_BASIC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_vin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_vin_cfg.h new file mode 100644 index 0000000000..816207c8d4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_vin_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_VIN_CFG_H_ +#define R_VIN_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define VIN_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_VIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_wdt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_wdt_cfg.h new file mode 100644 index 0000000000..0d10d3f68a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/r_wdt_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_WDT_CFG_H_ +#define R_WDT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define WDT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define WDT_CFG_REGISTER_START_NMI_SUPPORTED ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_WDT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/uart_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/uart_device.c new file mode 100644 index 0000000000..28d41a2801 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/uart_device.c @@ -0,0 +1,15 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "PeripheralNames.h" +#include "hal_data.h" +#include "device.h" + +const uart_instance_t * const g_uart_instances[UART_COUNT] = { + &g_uart0, + &g_uart3, + &g_uart4, + &g_uart9, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/us_ticker_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/us_ticker_data.h new file mode 100644 index 0000000000..f084d5c258 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA4E1/us_ticker_data.h @@ -0,0 +1,28 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __US_TICKER_DATA_H +#define __US_TICKER_DATA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define US_TICKER_CLOCK_HZ (25000000UL) +#define US_TICKER_CLOCK_BITS (32) +#define US_TICKER_VAR g_timer_gpt1 +#define US_TICKER_INSTANCE R_GPT1 +#define US_TICKER_IRQ GPT1_CAPTURE_COMPARE_A_IRQn + +/* RA4E1 devices have 25MHz us_ticker */ +#define US_TICKER_PERIOD_NUM 1 +#define US_TICKER_PERIOD_DEN 25 + +#ifdef __cplusplus +} +#endif + +#endif // __US_TICKER_DATA_H + diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/CMakeLists.txt new file mode 100644 index 0000000000..94d06395d3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/CMakeLists.txt @@ -0,0 +1,56 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# RA6E2 +add_library(mbed-ra6e2 INTERFACE) + +target_include_directories(mbed-ra6e2 + INTERFACE + ../ra/fsp/src/bsp/mcu/ra6e2 + . +) + +target_sources(mbed-ra6e2 + INTERFACE + gpio_irq_device.c + uart_device.c + can_device.c + ../ra/fsp/src/bsp/mcu/ra6e2/bsp_linker.c + ../ra/fsp/src/r_adc/r_adc.c + ../ra/fsp/src/r_agt/r_agt.c + ../ra/fsp/src/r_cac/r_cac.c + ../ra/fsp/src/r_canfd/r_canfd.c + ../ra/fsp/src/r_cgc/r_cgc.c + ../ra/fsp/src/r_crc/r_crc.c + ../ra/fsp/src/r_dac/r_dac.c + ../ra/fsp/src/r_dmac/r_dmac.c + ../ra/fsp/src/r_doc/r_doc.c + ../ra/fsp/src/r_dtc/r_dtc.c + ../ra/fsp/src/r_elc/r_elc.c + ../ra/fsp/src/r_flash_hp/r_flash_hp.c + ../ra/fsp/src/r_gpt/r_gpt.c + ../ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c + ../ra/fsp/src/r_icu/r_icu.c + ../ra/fsp/src/r_iic_b_master/r_iic_b_master.c + ../ra/fsp/src/r_ioport/r_ioport.c + ../ra/fsp/src/r_iwdt/r_iwdt.c + ../ra/fsp/src/r_lpm/r_lpm.c + ../ra/fsp/src/r_lvd/r_lvd.c + ../ra/fsp/src/r_poeg/r_poeg.c + ../ra/fsp/src/r_qspi/r_qspi.c + ../ra/fsp/src/r_rtc/r_rtc.c + ../ra/fsp/src/r_sci_i2c/r_sci_i2c.c + ../ra/fsp/src/r_sci_lin/r_sci_lin.c + ../ra/fsp/src/r_sci_smci/r_sci_smci.c + ../ra/fsp/src/r_sci_spi/r_sci_spi.c + ../ra/fsp/src/r_sci_uart/r_sci_uart.c + ../ra/fsp/src/r_spi/r_spi.c + ../ra/fsp/src/r_wdt/r_wdt.c +) + +target_link_libraries(mbed-ra6e2 INTERFACE mbed-renesas-ra) +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-ra6e2 ../ra/fsp/src/bsp/mcu/ra6e2/RA6E2.ld) +endif() + +add_subdirectory(TARGET_FPB_RA6E2 EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/CMakeLists.txt new file mode 100644 index 0000000000..fa174530ac --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-fpb-ra6e2 INTERFACE) +target_include_directories(mbed-fpb-ra6e2 + INTERFACE + . +) +target_sources(mbed-fpb-ra6e2 + INTERFACE + board_init.c + common_data.c + hal_warmstart.c + hal_data.c + pin_data.c + vector_data.c + PeripheralPins.c +) +target_link_libraries(mbed-fpb-ra6e2 INTERFACE mbed-ra6e2) diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PeripheralNames.h new file mode 100644 index 0000000000..bfc498d5f7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PeripheralNames.h @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = 0, + UART_9 = 9 +} UARTName; + +typedef enum { + PWM_GPT0 = 0x00, + PWM_GPT1, + PWM_GPT2, + PWM_GPT3, + PWM_GPT4, + PWM_GPT5, + PWM_AGT0, + PWM_AGT1, +} PWMName; + +typedef enum { + PORT_0= BSP_IO_PORT_00, + PORT_1= BSP_IO_PORT_01, + PORT_2= BSP_IO_PORT_02, + PORT_3= BSP_IO_PORT_03, + PORT_4= BSP_IO_PORT_04, + PORT_5= BSP_IO_PORT_05, + PORT_8= BSP_IO_PORT_08, +} PortName; + +typedef enum { + ADC_0= 0, +} ADCName; + +typedef enum { + DAC_0= 0, + DAC_1, +} DACName; + +typedef enum { + IRQ_0= 0, + IRQ_1, + IRQ_2, + IRQ_3, + IRQ_4, + IRQ_5, + IRQ_6, + IRQ_7, + IRQ_8, + IRQ_9, + IRQ_10, + IRQ_11, + IRQ_12, + IRQ_13, + IRQ_14, +} IRQName; + +typedef enum { + SPI_0 = 0, + SPI_1, +} SPIName; + +typedef enum { + I2C_0 = 0, +} I2CName; + +typedef enum { + CAN_0 = 0, +} CANName; + + +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) +#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX +#else +#define STDIO_UART_TX CONSOLE_TX +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) +#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX +#else +#define STDIO_UART_RX CONSOLE_RX +#endif +#define STDIO_UART UART_9 + +#define IRQ_CHANNELS_COUNT (15) +#define UART_COUNT (2) +#define CAN_COUNT (1) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PeripheralPins.c new file mode 100644 index 0000000000..f549c726a5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PeripheralPins.c @@ -0,0 +1,201 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" +#include "r_adc_api.h" +#include "r_dac_api.h" +#include "r_ioport.h" + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {P0_0, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_0)}, + {P0_1, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_1)}, + {P0_2, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_2)}, + {P0_3, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_7)}, + {P0_4, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_4)}, + {P0_5, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_5)}, + {P0_6, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_6)}, + {P0_8, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_8)}, + {P0_13, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_11)}, + {P0_14, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_12)}, + {P0_15, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_13)}, + {P5_0, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_16)}, + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {P0_14, DAC_0, RA_PIN_DATA(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0)}, + {P0_15, DAC_1, RA_PIN_DATA(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0)}, + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {P1_0, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_1, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P1_2, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_2, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_3, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + // {P1_4, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + // {P1_5, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P1_6, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P1_7, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_8, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_9, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + // {P1_9, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P1_10, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + // {P1_10, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_11, PWM_GPT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P1_12, PWM_GPT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_12, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_13, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P2_5, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P2_5, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P2_6, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P2_7, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P2_12, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P2_13, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P3_0, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P3_1, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P3_2, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P4_3, PWM_GPT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P4_8, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + // {P4_8, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P4_9, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + // {P4_9, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P5_0, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P8_14, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P8_15, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {NC, NC, 0} +}; + +//*** IRQ *** + +const PinMap PinMap_IRQ[] = { + {P1_5, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_0, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_1, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_4, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_0, IRQ_2, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_13, IRQ_2, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_10, IRQ_3, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_12, IRQ_3, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_11, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_11, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_2, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_10, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_1, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_9, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_8, IRQ_7, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_4, IRQ_9, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_15, IRQ_13, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_6, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_5, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_2, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_1, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_0, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_1, IRQ_7, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_2, IRQ_8, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_4, IRQ_9, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_5, IRQ_10, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_6, IRQ_11, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_8, IRQ_12, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_3, IRQ_14, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {NC, NC, 0} +}; + +// SERIAL + +const PinMap PinMap_UART_RX[] = { + {P1_0, UART_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P1_10, UART_9, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P2_12, UART_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P4_10, UART_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_TX[] = { + {P1_1, UART_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P1_9, UART_9, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P2_13, UART_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P4_11, UART_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {NC, NC, 0} +}; + +// SPI + +const PinMap PinMap_SPI_MOSI[] = { + {P1_9, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P2_7, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P1_1, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P1_10, SPI_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {P2_6, SPI_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {P1_0, SPI_1, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {P1_11, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P3_2, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P1_2, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P1_7, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_8, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_12, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P2_5, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P3_0, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P3_1, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_3, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_4, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_5, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_6, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {NC, NC, 0} +}; + +// I2C + +const PinMap PinMap_I2C_SCL[] = { + {P1_0, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P2_5, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_0, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_8, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SDA[] = { + {P1_1, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P2_6, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_1, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_7, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {NC, NC, 0} +}; + +// CAN + +const PinMap PinMap_CAN_RD[] = { + {P1_2, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P1_10, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P4_2, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {P1_3, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P1_9, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P4_1, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PinNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PinNames.h new file mode 100644 index 0000000000..a9a067e3a8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PinNames.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 4 + +typedef enum { + P0_0 = 0x0000, P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, + P1_0 = 0x0100, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, + P2_0 = 0x0200, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, + P3_0 = 0x0300, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, + P4_0 = 0x0400, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, + P5_0 = 0x0500, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, + P8_0 = 0x0800, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15, + + // mbed Pin Names +#define LED1 P2_7 +#define LED2 P2_6 +#define BUTTON0 P3_4 + + CONSOLE_TX = P1_9, + CONSOLE_RX = P1_10, + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Pin Names + ARDUINO_UNO_D0 = P4_10, + ARDUINO_UNO_D1 = P4_11, + ARDUINO_UNO_D2 = P1_5, + ARDUINO_UNO_D3 = P4_8, + ARDUINO_UNO_D4 = P5_0, + ARDUINO_UNO_D5 = P4_9, + ARDUINO_UNO_D6 = P1_13, + ARDUINO_UNO_D7 = P0_8, + ARDUINO_UNO_D8 = P0_6, + ARDUINO_UNO_D9 = P4_3, + ARDUINO_UNO_D10 = P3_1, + ARDUINO_UNO_D11 = P1_9, + ARDUINO_UNO_D12 = P1_10, + ARDUINO_UNO_D13 = P1_11, + ARDUINO_UNO_D14 = P1_1, + ARDUINO_UNO_D15 = P1_0, + + ARDUINO_UNO_A0 = P0_0, + ARDUINO_UNO_A1 = P0_1, + ARDUINO_UNO_A2 = P0_2, + ARDUINO_UNO_A3 = P0_4, + ARDUINO_UNO_A4 = P0_3, + ARDUINO_UNO_A5 = P0_13, +#endif + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown = 3, + PullNone = 2, + OpenDrain = 4, + PullDefault = PullNone +} PinMode; + +#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f) +#define PINNO(pin) ((pin)&0x0f) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PortNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PortNames.h new file mode 100644 index 0000000000..661692b2ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/PortNames.h @@ -0,0 +1,37 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3, + Port4 = 4, + Port5 = 5, + Port8 = 8 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board.h new file mode 100644 index 0000000000..77fcb7a00a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board.h @@ -0,0 +1,46 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA6E2_FPB for the RA6E2-FPB board + * @brief BSP for the RA6E2-FPB Board + * + * The RA6E2_FPB is a development kit for the Renesas R7FA6E2BB3CFM microcontroller in a LQFP64 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA6E2_FPB + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA6E2_FPB) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board_init.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board_init.c new file mode 100644 index 0000000000..e3d337a1a1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board_init.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6E2_FPB + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA6E2_FPB) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA6E2_FPB) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board_init.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board_init.h new file mode 100644 index 0000000000..ebb6a0dc96 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/board_init.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6E2_FPB + * @brief Board specific code for the RA6E2-FPB Board + * + * This include file is specific to the RA6E2-FPB board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA6E2_FPB) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/bsp_clock_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/bsp_clock_cfg.h new file mode 100644 index 0000000000..f803b26646 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/bsp_clock_cfg.h @@ -0,0 +1,32 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* PLL Src: HOCO */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(10,0) /* PLL Mul x10.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* USBCLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* CANFDCLK Src: PLL */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* I3CCLK Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCLK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* USBCLK Div /5 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_8) /* CANFDCLK Div /8 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ +#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_2) /* I3CCLK Div /2 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/common_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/common_data.c new file mode 100644 index 0000000000..2fc95f138a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/common_data.c @@ -0,0 +1,555 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated common source file - do not edit */ +#include "common_data.h" +icu_instance_ctrl_t g_external_irq14_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq14_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq14_cfg = +{ + .channel = 14, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq14_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ14) + .irq = VECTOR_NUMBER_ICU_IRQ14, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq14 = +{ + .p_ctrl = &g_external_irq14_ctrl, + .p_cfg = &g_external_irq14_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq13_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq13_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq13_cfg = +{ + .channel = 13, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq13_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ13) + .irq = VECTOR_NUMBER_ICU_IRQ13, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq13 = +{ + .p_ctrl = &g_external_irq13_ctrl, + .p_cfg = &g_external_irq13_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq12_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq12_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq12_cfg = +{ + .channel = 12, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq12_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ12) + .irq = VECTOR_NUMBER_ICU_IRQ12, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq12 = +{ + .p_ctrl = &g_external_irq12_ctrl, + .p_cfg = &g_external_irq12_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq11_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq11_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq11_cfg = +{ + .channel = 11, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq11_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ11) + .irq = VECTOR_NUMBER_ICU_IRQ11, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq11 = +{ + .p_ctrl = &g_external_irq11_ctrl, + .p_cfg = &g_external_irq11_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq10_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq10_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq10_cfg = +{ + .channel = 10, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq10_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ10) + .irq = VECTOR_NUMBER_ICU_IRQ10, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq10 = +{ + .p_ctrl = &g_external_irq10_ctrl, + .p_cfg = &g_external_irq10_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq9_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq9_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq9_cfg = +{ + .channel = 9, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq9_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ9) + .irq = VECTOR_NUMBER_ICU_IRQ9, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq9 = +{ + .p_ctrl = &g_external_irq9_ctrl, + .p_cfg = &g_external_irq9_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq8_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq8_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq8_cfg = +{ + .channel = 8, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq8_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ8) + .irq = VECTOR_NUMBER_ICU_IRQ8, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq8 = +{ + .p_ctrl = &g_external_irq8_ctrl, + .p_cfg = &g_external_irq8_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq7_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq7_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq7_cfg = +{ + .channel = 7, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq7_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ7) + .irq = VECTOR_NUMBER_ICU_IRQ7, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq7 = +{ + .p_ctrl = &g_external_irq7_ctrl, + .p_cfg = &g_external_irq7_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq6_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq6_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq6_cfg = +{ + .channel = 6, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq6_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ6) + .irq = VECTOR_NUMBER_ICU_IRQ6, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq6 = +{ + .p_ctrl = &g_external_irq6_ctrl, + .p_cfg = &g_external_irq6_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq5_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq5_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq5_cfg = +{ + .channel = 5, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq5_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ5) + .irq = VECTOR_NUMBER_ICU_IRQ5, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq5 = +{ + .p_ctrl = &g_external_irq5_ctrl, + .p_cfg = &g_external_irq5_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq4_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq4_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq4_cfg = +{ + .channel = 4, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq4_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ4) + .irq = VECTOR_NUMBER_ICU_IRQ4, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq4 = +{ + .p_ctrl = &g_external_irq4_ctrl, + .p_cfg = &g_external_irq4_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq3_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq3_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq3_cfg = +{ + .channel = 3, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq3_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ3) + .irq = VECTOR_NUMBER_ICU_IRQ3, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq3 = +{ + .p_ctrl = &g_external_irq3_ctrl, + .p_cfg = &g_external_irq3_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq2_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq2_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq2_cfg = +{ + .channel = 2, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq2_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ2) + .irq = VECTOR_NUMBER_ICU_IRQ2, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq2 = +{ + .p_ctrl = &g_external_irq2_ctrl, + .p_cfg = &g_external_irq2_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq1_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq1_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq1_cfg = +{ + .channel = 1, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq1_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ1) + .irq = VECTOR_NUMBER_ICU_IRQ1, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq1 = +{ + .p_ctrl = &g_external_irq1_ctrl, + .p_cfg = &g_external_irq1_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq0_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq0_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq0_cfg = +{ + .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq0_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ + .p_ctrl = &g_external_irq0_ctrl, + .p_cfg = &g_external_irq0_cfg, + .p_api = &g_external_irq_on_icu +}; +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/common_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/common_data.h new file mode 100644 index 0000000000..374344d20b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/common_data.h @@ -0,0 +1,176 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq14; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq14_ctrl; +extern const external_irq_cfg_t g_external_irq14_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq13; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq13_ctrl; +extern const external_irq_cfg_t g_external_irq13_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq12; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq12_ctrl; +extern const external_irq_cfg_t g_external_irq12_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq11; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq11_ctrl; +extern const external_irq_cfg_t g_external_irq11_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq10; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq10_ctrl; +extern const external_irq_cfg_t g_external_irq10_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq9; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq9_ctrl; +extern const external_irq_cfg_t g_external_irq9_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq8; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq8_ctrl; +extern const external_irq_cfg_t g_external_irq8_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq7; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq7_ctrl; +extern const external_irq_cfg_t g_external_irq7_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq6; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq6_ctrl; +extern const external_irq_cfg_t g_external_irq6_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq5; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq5_ctrl; +extern const external_irq_cfg_t g_external_irq5_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq4; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq4_ctrl; +extern const external_irq_cfg_t g_external_irq4_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq3; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq3_ctrl; +extern const external_irq_cfg_t g_external_irq3_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq2; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq2_ctrl; +extern const external_irq_cfg_t g_external_irq2_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq1; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq1_ctrl; +extern const external_irq_cfg_t g_external_irq1_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_data.c new file mode 100644 index 0000000000..320fce69da --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_data.c @@ -0,0 +1,1795 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated HAL source file - do not edit */ +#include "hal_data.h" + +flash_hp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ + .data_flash_bgo = false, + .p_callback = flash_callback, + .p_context = NULL, +#if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, +#else + .irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_FCU_FIFERR) + .err_irq = VECTOR_NUMBER_FCU_FIFERR, +#else + .err_irq = FSP_INVALID_VECTOR, +#endif + .err_ipl = (7), + .ipl = (7), +}; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ + .p_ctrl = &g_flash0_ctrl, + .p_cfg = &g_flash0_cfg, + .p_api = &g_flash_on_flash_hp +}; +/* Nominal and Data bit timing configuration */ + +can_bit_timing_cfg_t g_canfd0_bit_timing_cfg = +{ + /* Actual bitrate: 500000 Hz. Actual sample point: 76 %. */ + .baud_rate_prescaler = 1, + .time_segment_1 = 37, + .time_segment_2 = 12, + .synchronization_jump_width = 4 +}; + +#if BSP_FEATURE_CANFD_FD_SUPPORT +can_bit_timing_cfg_t g_canfd0_data_timing_cfg = +{ + /* Actual bitrate: 1923077 Hz. Actual sample point: 77 %. */ + .baud_rate_prescaler = 1, + .time_segment_1 = 9, + .time_segment_2 = 3, + .synchronization_jump_width = 1 +}; +#endif + + +extern const canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH0_RULE_NUM]; + + +/* Buffer RAM used: 608 bytes */ +canfd_global_cfg_t g_canfd0_global_cfg = +{ + .global_interrupts = ( 0x3), + .global_config = ((R_CANFD_CFDGCFG_TPRI_Msk) | (0) | (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC ? R_CANFD_CFDGCFG_DCS_Msk : 0U) | (0) | + ((0) << R_CANFD_CFDGCFG_ITRCP_Pos)), + .rx_mb_config = (0 | ((7) << R_CANFD_CFDRMNB_RMPLS_Pos)), + .global_err_ipl = CANFD_CFG_GLOBAL_ERR_IPL, + .rx_fifo_ipl = CANFD_CFG_RX_FIFO_IPL, + .rx_fifo_config = + { + ((3U) << R_CANFD_CFDRFCC_RFIGCV_Pos) | ((2) << R_CANFD_CFDRFCC_RFDC_Pos) | ((7) << R_CANFD_CFDRFCC_RFPLS_Pos) | ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) | ((1)), + ((3U) << R_CANFD_CFDRFCC_RFIGCV_Pos) | ((2) << R_CANFD_CFDRFCC_RFDC_Pos) | ((7) << R_CANFD_CFDRFCC_RFPLS_Pos) | ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) | ((0)) + }, + .common_fifo_config = + { + CANFD_CFG_COMMONFIFO0 + } +}; + +canfd_extended_cfg_t g_canfd0_extended_cfg = +{ + .p_afl = p_canfd0_afl, + .txmb_txi_enable = ((1ULL << 0) | 0ULL), + .error_interrupts = (R_CANFD_CFDC_CTR_EWIE_Msk | R_CANFD_CFDC_CTR_EPIE_Msk | R_CANFD_CFDC_CTR_BOEIE_Msk | R_CANFD_CFDC_CTR_BORIE_Msk | R_CANFD_CFDC_CTR_OLIE_Msk | 0U), +#if BSP_FEATURE_CANFD_FD_SUPPORT + .p_data_timing = &g_canfd0_data_timing_cfg, +#else + .p_data_timing = NULL, +#endif + .delay_compensation = (1), + .p_global_cfg = &g_canfd0_global_cfg, +}; + +canfd_instance_ctrl_t g_canfd0_ctrl; +const can_cfg_t g_canfd0_cfg = +{ + .channel = 0, + .p_bit_timing = &g_canfd0_bit_timing_cfg, + .p_callback = can_callback, + .p_extend = &g_canfd0_extended_cfg, + .p_context = NULL, + .ipl = (12), +#if defined(VECTOR_NUMBER_CAN0_COMFRX) + .rx_irq = VECTOR_NUMBER_CAN0_COMFRX, +#else + .rx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN0_TX) + .tx_irq = VECTOR_NUMBER_CAN0_TX, +#else + .tx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN0_CHERR) + .error_irq = VECTOR_NUMBER_CAN0_CHERR, +#else + .error_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const can_instance_t g_canfd0 = +{ + .p_ctrl = &g_canfd0_ctrl, + .p_cfg = &g_canfd0_cfg, + .p_api = &g_canfd_on_canfd +}; + +dmac_instance_ctrl_t g_transfer1_ctrl; +transfer_info_t g_transfer1_info = +{ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .transfer_settings_word_b.irq = TRANSFER_IRQ_END, + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; +const dmac_extended_cfg_t g_transfer1_extend = +{ + .offset = 1, + .src_buffer_size = 1, +#if defined(VECTOR_NUMBER_DMAC1_INT) + .irq = VECTOR_NUMBER_DMAC1_INT, +#else + .irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .channel = 1, + .p_callback = g_spi1_tx_transfer_callback, + .p_context = NULL, + .activation_source = ELC_EVENT_SPI1_TXI, +}; +const transfer_cfg_t g_transfer1_cfg = +{ + .p_info = &g_transfer1_info, + .p_extend = &g_transfer1_extend, +}; +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ + .p_ctrl = &g_transfer1_ctrl, + .p_cfg = &g_transfer1_cfg, + .p_api = &g_transfer_on_dmac +}; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (1) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_tx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +void g_spi1_tx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_tx_dmac_callback(&g_spi1_ctrl); +} +#endif + +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_rx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +void g_spi1_rx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_rx_dmac_callback(&g_spi1_ctrl); +} +#endif +#undef RA_NOT_DEFINED + +spi_instance_ctrl_t g_spi1_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi1_ext_cfg = +{ + .spi_clksyn = SPI_SSL_MODE_SPI, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = { + /* Actual calculated bitrate: 12500000. */ .spbr = 3, .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1, + .burst_interframe_delay = SPI_BURST_TRANSFER_WITH_DELAY + }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi1_cfg = +{ + .channel = 1, + +#if defined(VECTOR_NUMBER_SPI1_RXI) + .rxi_irq = VECTOR_NUMBER_SPI1_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI1_TXI) + .txi_irq = VECTOR_NUMBER_SPI1_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI1_TEI) + .tei_irq = VECTOR_NUMBER_SPI1_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI1_ERI) + .eri_irq = VECTOR_NUMBER_SPI1_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + + .rxi_ipl = (10), + .txi_ipl = (BSP_IRQ_DISABLED), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi1_P_TRANSFER_TX, + .p_transfer_rx = g_spi1_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi1_ext_cfg, +}; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi1 = +{ + .p_ctrl = &g_spi1_ctrl, + .p_cfg = &g_spi1_cfg, + .p_api = &g_spi_on_spi +}; + +sci_uart_instance_ctrl_t g_uart9_ctrl; + + baud_setting_t g_uart9_baud_setting = + { + /* Baud rate calculated with 0.014% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 38, .mddr = (uint8_t) 184, .semr_baudrate_bits_b.brme = true + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart9_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart9_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + }, + .irda_setting = { + .ircr_bits_b.ire = 0, + .ircr_bits_b.irrxinv = 0, + .ircr_bits_b.irtxinv = 0, + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart9_cfg = + { + .channel = 9, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart9_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (5), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI9_RXI) + .rxi_irq = VECTOR_NUMBER_SCI9_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_TXI) + .txi_irq = VECTOR_NUMBER_SCI9_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_TEI) + .tei_irq = VECTOR_NUMBER_SCI9_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_ERI) + .eri_irq = VECTOR_NUMBER_SCI9_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart9 = +{ + .p_ctrl = &g_uart9_ctrl, + .p_cfg = &g_uart9_cfg, + .p_api = &g_uart_on_sci +}; +gpt_instance_ctrl_t g_timer_gpt3_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt3_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT3_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT3_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt3_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT3_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT3_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT3_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT3_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT3_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT3_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT3_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt3_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt3_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0006826666666666667 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 3, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt3_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT3_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT3_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt3 = +{ + .p_ctrl = &g_timer_gpt3_ctrl, + .p_cfg = &g_timer_gpt3_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt0_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt0_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt0_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT0_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT0_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT0_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT0_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt0_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt0_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0006826666666666667 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 0, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt0_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt0 = +{ + .p_ctrl = &g_timer_gpt0_ctrl, + .p_cfg = &g_timer_gpt0_cfg, + .p_api = &g_timer_on_gpt +}; +iic_b_master_instance_ctrl_t g_i2c_master0_ctrl; +const iic_b_master_extended_cfg_t g_i2c_master0_extend = +{ + .timeout_mode = IIC_B_MASTER_TIMEOUT_MODE_SHORT, + .timeout_scl_low = IIC_B_MASTER_TIMEOUT_SCL_LOW_ENABLED, + .smbus_operation = 0, + /* Actual calculated bitrate: 99892. Actual calculated duty cycle: 50%. */ .clock_settings.brl_value = 234, .clock_settings.brh_value = 233, .clock_settings.cks_value = 1, .clock_settings.sdod_value = 0, .clock_settings.sdodcs_value = 0, .iic_clock_freq = 48000000, +}; +const i2c_master_cfg_t g_i2c_master0_cfg = +{ + .channel = 0, + .rate = I2C_MASTER_RATE_STANDARD, + .slave = 0x00, + .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .p_callback = i2c_callback, + .p_context = NULL, +#if defined(VECTOR_NUMBER_IICB0_RXI) + .rxi_irq = VECTOR_NUMBER_IICB0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IICB0_TXI) + .txi_irq = VECTOR_NUMBER_IICB0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IICB0_TEND) + .tei_irq = VECTOR_NUMBER_IICB0_TEND, +#elif defined(VECTOR_NUMBER_IICB0_TEI) + .tei_irq = VECTOR_NUMBER_IICB0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IICB0_EEI) + .eri_irq = VECTOR_NUMBER_IICB0_EEI, +#elif defined(VECTOR_NUMBER_IICB0_ERI) + .eri_irq = VECTOR_NUMBER_IICB0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .p_extend = &g_i2c_master0_extend, +}; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master0 = +{ + .p_ctrl = &g_i2c_master0_ctrl, + .p_cfg = &g_i2c_master0_cfg, + .p_api = &g_i2c_master_on_iic_b +}; +crc_instance_ctrl_t g_crc0_ctrl; +const crc_cfg_t g_crc0_cfg = +{ + .polynomial = CRC_POLYNOMIAL_CRC_32, + .bit_order = CRC_BIT_ORDER_LMS_LSB, + .snoop_address = 0, + .p_extend = NULL, +}; + +/* Instance structure to use this module. */ +const crc_instance_t g_crc0 = +{ + .p_ctrl = &g_crc0_ctrl, + .p_cfg = &g_crc0_cfg, + .p_api = &g_crc_on_crc +}; +agt_instance_ctrl_t g_timer_agt1_ctrl; +const agt_extended_cfg_t g_timer_agt1_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_32, +}; +const timer_cfg_t g_timer_agt1_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0013653333333333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 1, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt1_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT1_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT1_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt1 = +{ + .p_ctrl = &g_timer_agt1_ctrl, + .p_cfg = &g_timer_agt1_cfg, + .p_api = &g_timer_on_agt +}; +agt_instance_ctrl_t g_timer_agt0_ctrl; +const agt_extended_cfg_t g_timer_agt0_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_32, +}; +const timer_cfg_t g_timer_agt0_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0013653333333333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 0, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt0_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt0 = +{ + .p_ctrl = &g_timer_agt0_ctrl, + .p_cfg = &g_timer_agt0_cfg, + .p_api = &g_timer_on_agt +}; +gpt_instance_ctrl_t g_timer_gpt5_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt5_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT5_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt5_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT5_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT5_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT5_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT5_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt5_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt5_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0006826666666666667 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 5, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt5_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT5_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt5 = +{ + .p_ctrl = &g_timer_gpt5_ctrl, + .p_cfg = &g_timer_gpt5_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt4_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt4_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT4_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt4_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT4_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT4_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT4_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT4_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt4_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt4_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0006826666666666667 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 4, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt4_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT4_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt4 = +{ + .p_ctrl = &g_timer_gpt4_ctrl, + .p_cfg = &g_timer_gpt4_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt2_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt2_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt2_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT2_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT2_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT2_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT2_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt2_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt2_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0006826666666666667 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 2, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt2_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt2 = +{ + .p_ctrl = &g_timer_gpt2_ctrl, + .p_cfg = &g_timer_gpt2_cfg, + .p_api = &g_timer_on_gpt +}; +sci_uart_instance_ctrl_t g_uart0_ctrl; + + baud_setting_t g_uart0_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 51, .mddr = (uint8_t) 256, .semr_baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart0_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + #if 0xFF != 0xFF + .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + }, + .irda_setting = { + .ircr_bits_b.ire = 0, + .ircr_bits_b.irrxinv = 0, + .ircr_bits_b.irtxinv = 0, + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart0_cfg = + { + .channel = 0, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart0_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (5), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ + .p_ctrl = &g_uart0_ctrl, + .p_cfg = &g_uart0_cfg, + .p_api = &g_uart_on_sci +}; + +dmac_instance_ctrl_t g_transfer0_ctrl; +transfer_info_t g_transfer0_info = +{ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .transfer_settings_word_b.irq = TRANSFER_IRQ_END, + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; +const dmac_extended_cfg_t g_transfer0_extend = +{ + .offset = 1, + .src_buffer_size = 1, +#if defined(VECTOR_NUMBER_DMAC0_INT) + .irq = VECTOR_NUMBER_DMAC0_INT, +#else + .irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .channel = 0, + .p_callback = g_spi0_tx_transfer_callback, + .p_context = NULL, + .activation_source = ELC_EVENT_SPI0_TXI, +}; +const transfer_cfg_t g_transfer0_cfg = +{ + .p_info = &g_transfer0_info, + .p_extend = &g_transfer0_extend, +}; +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ + .p_ctrl = &g_transfer0_ctrl, + .p_cfg = &g_transfer0_cfg, + .p_api = &g_transfer_on_dmac +}; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (1) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_tx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +void g_spi0_tx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_tx_dmac_callback(&g_spi0_ctrl); +} +#endif + +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_rx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +void g_spi0_rx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_rx_dmac_callback(&g_spi0_ctrl); +} +#endif +#undef RA_NOT_DEFINED + +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ + .spi_clksyn = SPI_SSL_MODE_SPI, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = { + /* Actual calculated bitrate: 12500000. */ .spbr = 3, .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1, + .burst_interframe_delay = SPI_BURST_TRANSFER_WITH_DELAY + }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ + .channel = 0, + +#if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + + .rxi_ipl = (10), + .txi_ipl = (BSP_IRQ_DISABLED), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, +}; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ + .p_ctrl = &g_spi0_ctrl, + .p_cfg = &g_spi0_cfg, + .p_api = &g_spi_on_spi +}; +wdt_instance_ctrl_t g_wdt0_ctrl; + +const wdt_cfg_t g_wdt0_cfg = +{ + .timeout = WDT_TIMEOUT_16384, + .clock_division = WDT_CLOCK_DIVISION_8192, + .window_start = WDT_WINDOW_START_100, + .window_end = WDT_WINDOW_END_0, + .reset_control = WDT_RESET_CONTROL_RESET, + .stop_control = WDT_STOP_CONTROL_ENABLE, + .p_callback = NULL, +}; + +/* Instance structure to use this module. */ +const wdt_instance_t g_wdt0 = +{ + .p_ctrl = &g_wdt0_ctrl, + .p_cfg = &g_wdt0_cfg, + .p_api = &g_wdt_on_wdt +}; +#if BSP_TZ_NONSECURE_BUILD + #if defined(BSP_CFG_CLOCKS_SECURE) && BSP_CFG_CLOCKS_SECURE + #error "The LPM module requires CGC registers to be non-secure when it is used in a TrustZone Non-secure project." + #endif +#endif + +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ + .low_power_mode = LPM_MODE_SLEEP, + .standby_wake_sources = (lpm_standby_wake_source_t) 0, +#if BSP_FEATURE_ICU_HAS_WUPEN2 + .standby_wake_sources_2 = (lpm_standby_wake_source_2_t) 0, +#endif +#if BSP_FEATURE_LPM_HAS_SNOOZE + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .snooze_request_source = (lpm_snooze_request_t) LPM_SNOOZE_REQUEST_RXD0_FALLING, +#if BSP_FEATURE_LPM_SNZEDCR_MASK > 0 + .snooze_end_sources = (lpm_snooze_end_t) 0, +#endif + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, +#endif +#if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, +#endif +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t) 0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t) 0, +#if BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE + .deep_standby_soft_start_mode = 0, +#endif +#endif +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint16_t) ( 0), + .ram_retention_cfg.tcm_retention = false, +#endif +#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, +#endif +#if BSP_FEATURE_LPM_HAS_LDO_SKEEP + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, +#endif +#if BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT + .lpm_flash_mode_select = false, +#endif +#if BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE + .lpm_hoco_startup_speed = false, +#endif +#if BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT + .lpm_standby_sosc = false, +#endif + .p_extend = NULL, +}; + +const lpm_instance_t g_lpm0 = +{ + .p_api = &g_lpm_on_lpm, + .p_ctrl = &g_lpm0_ctrl, + .p_cfg = &g_lpm0_cfg +}; +gpt_instance_ctrl_t g_timer_gpt1_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt1_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt1_extend = +{ + .gtioca = { .output_enabled = false, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = false, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (10), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT1_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT1_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT1_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT1_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt1_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) false, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) false, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt1_cfg = +{ + .mode = TIMER_MODE_PERIODIC, + /* Actual period: 0.0006826666666666667 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_32, + .channel = 1, + .p_callback = usticker_compare_match_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt1_extend, + .cycle_end_ipl = (15), +#if defined(VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt1 = +{ + .p_ctrl = &g_timer_gpt1_ctrl, + .p_cfg = &g_timer_gpt1_cfg, + .p_api = &g_timer_on_gpt +}; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ + .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, +}; +const rtc_cfg_t g_rtc0_cfg = +{ + .clock_source = MBED_CONF_TARGET_RTC_CLOCK_SOURCE, + .freq_compare_value = 255, + .p_err_cfg = &g_rtc0_err_cfg, + .p_callback = NULL, + .p_context = NULL, + .p_extend = NULL, + .alarm_ipl = (BSP_IRQ_DISABLED), + .periodic_ipl = (BSP_IRQ_DISABLED), + .carry_ipl = (12), +#if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, +#else + .alarm_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, +#else + .periodic_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, +#else + .carry_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ + .p_ctrl = &g_rtc0_ctrl, + .p_cfg = &g_rtc0_cfg, + .p_api = &g_rtc_on_rtc +}; +dac_instance_ctrl_t g_dac0_ctrl; +const dac_extended_cfg_t g_dac0_ext_cfg = +{ + .enable_charge_pump = 0, + .data_format = DAC_DATA_FORMAT_FLUSH_RIGHT, + .output_amplifier_enabled = 0, + .internal_output_enabled = false, + .ref_volt_sel = (dac_ref_volt_sel_t) (0) +}; +const dac_cfg_t g_dac0_cfg = +{ + .channel = 0, + .ad_da_synchronized = false, + .p_extend = &g_dac0_ext_cfg +}; +/* Instance structure to use this module. */ +const dac_instance_t g_dac0 = +{ + .p_ctrl = &g_dac0_ctrl, + .p_cfg = &g_dac0_cfg, + .p_api = &g_dac_on_dac +}; +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ + .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger = ADC_START_SOURCE_DISABLED, + .trigger_group_b = ADC_START_SOURCE_DISABLED, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, + .enable_adbuf = 0, +#if defined(VECTOR_NUMBER_ADC0_WINDOW_A) + .window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A, +#else + .window_a_irq = FSP_INVALID_VECTOR, +#endif + .window_a_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC0_WINDOW_B) + .window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B, +#else + .window_b_irq = FSP_INVALID_VECTOR, +#endif + .window_b_ipl = (BSP_IRQ_DISABLED), +}; +const adc_cfg_t g_adc0_cfg = +{ + .unit = 0, + .mode = ADC_MODE_SINGLE_SCAN, + .resolution = ADC_RESOLUTION_12_BIT, + .alignment = (adc_alignment_t) ADC_ALIGNMENT_RIGHT, + .trigger = (adc_trigger_t)0xF, // Not used + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_adc0_cfg_extend, +#if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, +#else + .scan_end_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, +#else + .scan_end_b_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), +}; +#if ((0) | (0)) +const adc_window_cfg_t g_adc0_window_cfg = +{ + .compare_mask = 0, + .compare_mode_mask = 0, + .compare_cfg = (adc_compare_cfg_t) ((0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR)), + .compare_ref_low = 0, + .compare_ref_high = 0, + .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0), + .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE), + .compare_b_ref_low = 0, + .compare_b_ref_high = 0, +}; +#endif +const adc_channel_cfg_t g_adc0_channel_cfg = +{ + .scan_mask = ADC_MASK_CHANNEL_0 | ADC_MASK_CHANNEL_1 | ADC_MASK_CHANNEL_2 | ADC_MASK_CHANNEL_3 | ADC_MASK_CHANNEL_4 | ADC_MASK_CHANNEL_11 | ADC_MASK_CHANNEL_12 | ADC_MASK_CHANNEL_13 | 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, +#if ((0) | (0)) + .p_window_cfg = (adc_window_cfg_t *) &g_adc0_window_cfg, +#else + .p_window_cfg = NULL, +#endif +}; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ + .p_ctrl = &g_adc0_ctrl, + .p_cfg = &g_adc0_cfg, + .p_channel_cfg = &g_adc0_channel_cfg, + .p_api = &g_adc_on_adc +}; +void g_hal_init(void) { +g_common_init(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_data.h new file mode 100644 index 0000000000..27e736a3a0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_data.h @@ -0,0 +1,295 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_flash_hp.h" +#include "r_flash_api.h" +#include "r_canfd.h" +#include "r_can_api.h" +#include "r_dmac.h" +#include "r_transfer_api.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +#include "r_gpt.h" +#include "r_timer_api.h" +#include "r_iic_b_master.h" +#include "r_i2c_master_api.h" +#include "r_crc.h" +#include "r_crc_api.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_spi.h" +#include "r_wdt.h" +#include "r_wdt_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_dac.h" +#include "r_dac_api.h" +#include "r_adc.h" +#include "r_adc_api.h" +FSP_HEADER +/* Flash on Flash HP Instance */ +extern const flash_instance_t g_flash0; + +/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_hp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef flash_callback +void flash_callback(flash_callback_args_t * p_args); +#endif +/** CANFD on CANFD Instance. */ +extern const can_instance_t g_canfd0; +/** Access the CANFD instance using these structures when calling API functions directly (::p_api is not used). */ +extern canfd_instance_ctrl_t g_canfd0_ctrl; +extern const can_cfg_t g_canfd0_cfg; +extern const canfd_extended_cfg_t g_canfd0_cfg_extend; + +#ifndef can_callback +void can_callback(can_callback_args_t * p_args); +#endif + +/* Transfer on DMAC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DMAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dmac_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; + +#ifndef g_spi1_tx_transfer_callback +void g_spi1_tx_transfer_callback(transfer_callback_args_t * p_args); +#endif +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi1; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi1_ctrl; +extern const spi_cfg_t g_spi1_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t * p_args); +#endif + + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi1_P_TRANSFER_TX (NULL) +#else + #define g_spi1_P_TRANSFER_TX (&g_transfer1) +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + #define g_spi1_P_TRANSFER_RX (NULL) +#else + #define g_spi1_P_TRANSFER_RX (&RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart9; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart9_ctrl; + extern const uart_cfg_t g_uart9_cfg; + extern const sci_uart_extended_cfg_t g_uart9_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt3; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt3_ctrl; +extern const timer_cfg_t g_timer_gpt3_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt0; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt0_ctrl; +extern const timer_cfg_t g_timer_gpt0_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master0; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_b_master_instance_ctrl_t g_i2c_master0_ctrl; +extern const i2c_master_cfg_t g_i2c_master0_cfg; + +#ifndef i2c_callback +void i2c_callback(i2c_master_callback_args_t * p_args); +#endif +extern const crc_instance_t g_crc0; +extern crc_instance_ctrl_t g_crc0_ctrl; +extern const crc_cfg_t g_crc0_cfg; +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt1; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt1_ctrl; +extern const timer_cfg_t g_timer_agt1_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt0_ctrl; +extern const timer_cfg_t g_timer_agt0_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt5; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt5_ctrl; +extern const timer_cfg_t g_timer_gpt5_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt4; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt4_ctrl; +extern const timer_cfg_t g_timer_gpt4_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt2; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt2_ctrl; +extern const timer_cfg_t g_timer_gpt2_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart0; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart0_ctrl; + extern const uart_cfg_t g_uart0_cfg; + extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/* Transfer on DMAC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DMAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dmac_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; + +#ifndef g_spi0_tx_transfer_callback +void g_spi0_tx_transfer_callback(transfer_callback_args_t * p_args); +#endif +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t * p_args); +#endif + + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else + #define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + #define g_spi0_P_TRANSFER_RX (NULL) +#else + #define g_spi0_P_TRANSFER_RX (&RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +/** WDT on WDT Instance. */ +extern const wdt_instance_t g_wdt0; + +/** Access the WDT instance using these structures when calling API functions directly (::p_api is not used). */ +extern wdt_instance_ctrl_t g_wdt0_ctrl; +extern const wdt_cfg_t g_wdt0_cfg; + +#ifndef NULL +void NULL(wdt_callback_args_t * p_args); +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt1; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt1_ctrl; +extern const timer_cfg_t g_timer_gpt1_cfg; + +#ifndef usticker_compare_match_callback +void usticker_compare_match_callback(timer_callback_args_t * p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t * p_args); +#endif +/** DAC on DAC Instance. */ +extern const dac_instance_t g_dac0; + +/** Access the DAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dac_instance_ctrl_t g_dac0_ctrl; +extern const dac_cfg_t g_dac0_cfg; +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t * p_args); +#endif + +#ifndef NULL +#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 8 +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_warmstart.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_warmstart.c new file mode 100644 index 0000000000..2e799ebefe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/hal_warmstart.c @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); + +FSP_CPP_FOOTER + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { +#if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ +#endif + } + +#if BSP_CFG_OSPI_B_STARTUP_ENABLED && defined(BSP_CFG_OSPI_B_STARTUP_FN) + if (BSP_WARM_START_POST_CLOCK == event) + { + /* Setup OSPI_B SiP flash and initialize it. */ + R_BSP_OspiBInit(BSP_CFG_OSPI_B_STARTUP_FN, true); + } +#endif + + if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME); + +#if BSP_CFG_SDRAM_ENABLED + + /* Setup SDRAM and initialize it. Must configure pins first. */ + R_BSP_SdramInit(true); +#endif + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/pin_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/pin_data.c new file mode 100644 index 0000000000..18dc77dfc3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/pin_data.c @@ -0,0 +1,12 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = 0, + .p_pin_cfg_data = NULL, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/vector_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/vector_data.c new file mode 100644 index 0000000000..a54626fd39 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/vector_data.c @@ -0,0 +1,107 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated vector source file - do not edit */ + #include "bsp_api.h" + /* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ + #if VECTOR_DATA_IRQ_COUNT > 0 + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_NUM_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = + { + [0] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [1] = gpt_counter_overflow_isr, /* GPT1 COUNTER OVERFLOW (Overflow) */ + [2] = gpt_capture_compare_a_isr, /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + [3] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [4] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [5] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [6] = spi_eri_isr, /* SPI0 ERI (Error) */ + [7] = dmac_int_isr, /* DMAC0 INT (DMAC0 transfer end) */ + [8] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [9] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ + [10] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */ + [12] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [13] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [14] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [15] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [16] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [17] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [18] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ + [19] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ + [20] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ + [21] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */ + [22] = iic_b_master_rxi_isr, /* IICB0 RXI (Receive) */ + [23] = iic_b_master_txi_isr, /* IICB0 TXI (Transmit) */ + [24] = iic_b_master_tei_isr, /* IICB0 TEI (Transmit end) */ + [25] = iic_b_master_eri_isr, /* IICB0 ERI (Error) */ + [26] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ + [27] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ + [28] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ + [29] = r_icu_isr, /* ICU IRQ14 (External pin interrupt 14) */ + [30] = sci_uart_rxi_isr, /* SCI9 RXI (Receive data full) */ + [31] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ + [32] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [33] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [34] = spi_rxi_isr, /* SPI1 RXI (Receive buffer full) */ + [35] = spi_tei_isr, /* SPI1 TEI (Transmission complete event) */ + [36] = spi_eri_isr, /* SPI1 ERI (Error) */ + [37] = dmac_int_isr, /* DMAC1 INT (DMAC1 transfer end) */ + [38] = canfd_error_isr, /* CAN0 CHERR (Channel error) */ + [39] = canfd_channel_tx_isr, /* CAN0 TX (Transmit interrupt) */ + [40] = canfd_common_fifo_rx_isr, /* CAN0 COMFRX (Common FIFO receive interrupt) */ + [41] = canfd_error_isr, /* CAN GLERR (Global error) */ + [42] = canfd_rx_fifo_isr, /* CAN RXF (Global receive FIFO interrupt) */ + [43] = fcu_frdyi_isr, /* FCU FRDYI (Flash ready interrupt) */ + [44] = fcu_fiferr_isr, /* FCU FIFERR (Flash access error interrupt) */ + }; + #if BSP_FEATURE_ICU_HAS_IELSR + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_NUM_ENTRIES] = + { + [0] = BSP_PRV_VECT_ENUM(EVENT_RTC_CARRY,GROUP0), /* RTC CARRY (Carry interrupt) */ + [1] = BSP_PRV_VECT_ENUM(EVENT_GPT1_COUNTER_OVERFLOW,GROUP1), /* GPT1 COUNTER OVERFLOW (Overflow) */ + [2] = BSP_PRV_VECT_ENUM(EVENT_GPT1_CAPTURE_COMPARE_A,GROUP2), /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + [3] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ0,GROUP3), /* ICU IRQ0 (External pin interrupt 0) */ + [4] = BSP_PRV_VECT_ENUM(EVENT_SPI0_RXI,GROUP4), /* SPI0 RXI (Receive buffer full) */ + [5] = BSP_PRV_VECT_ENUM(EVENT_SPI0_TEI,GROUP5), /* SPI0 TEI (Transmission complete event) */ + [6] = BSP_PRV_VECT_ENUM(EVENT_SPI0_ERI,GROUP6), /* SPI0 ERI (Error) */ + [7] = BSP_PRV_VECT_ENUM(EVENT_DMAC0_INT,GROUP7), /* DMAC0 INT (DMAC0 transfer end) */ + [8] = BSP_PRV_VECT_ENUM(EVENT_SCI0_RXI,GROUP0), /* SCI0 RXI (Receive data full) */ + [9] = BSP_PRV_VECT_ENUM(EVENT_SCI0_TXI,GROUP1), /* SCI0 TXI (Transmit data empty) */ + [10] = BSP_PRV_VECT_ENUM(EVENT_SCI0_TEI,GROUP2), /* SCI0 TEI (Transmit end) */ + [11] = BSP_PRV_VECT_ENUM(EVENT_SCI0_ERI,GROUP3), /* SCI0 ERI (Receive error) */ + [12] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ1,GROUP4), /* ICU IRQ1 (External pin interrupt 1) */ + [13] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ2,GROUP5), /* ICU IRQ2 (External pin interrupt 2) */ + [14] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ3,GROUP6), /* ICU IRQ3 (External pin interrupt 3) */ + [15] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ4,GROUP7), /* ICU IRQ4 (External pin interrupt 4) */ + [16] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ5,GROUP0), /* ICU IRQ5 (External pin interrupt 5) */ + [17] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ6,GROUP1), /* ICU IRQ6 (External pin interrupt 6) */ + [18] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ7,GROUP2), /* ICU IRQ7 (External pin interrupt 7) */ + [19] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ8,GROUP3), /* ICU IRQ8 (External pin interrupt 8) */ + [20] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ9,GROUP4), /* ICU IRQ9 (External pin interrupt 9) */ + [21] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ10,GROUP5), /* ICU IRQ10 (External pin interrupt 10) */ + [22] = BSP_PRV_VECT_ENUM(EVENT_IICB0_RXI,GROUP6), /* IICB0 RXI (Receive) */ + [23] = BSP_PRV_VECT_ENUM(EVENT_IICB0_TXI,GROUP7), /* IICB0 TXI (Transmit) */ + [24] = BSP_PRV_VECT_ENUM(EVENT_IICB0_TEI,GROUP0), /* IICB0 TEI (Transmit end) */ + [25] = BSP_PRV_VECT_ENUM(EVENT_IICB0_ERI,GROUP1), /* IICB0 ERI (Error) */ + [26] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ11,GROUP2), /* ICU IRQ11 (External pin interrupt 11) */ + [27] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ12,GROUP3), /* ICU IRQ12 (External pin interrupt 12) */ + [28] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ13,GROUP4), /* ICU IRQ13 (External pin interrupt 13) */ + [29] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ14,GROUP5), /* ICU IRQ14 (External pin interrupt 14) */ + [30] = BSP_PRV_VECT_ENUM(EVENT_SCI9_RXI,GROUP6), /* SCI9 RXI (Receive data full) */ + [31] = BSP_PRV_VECT_ENUM(EVENT_SCI9_TXI,GROUP7), /* SCI9 TXI (Transmit data empty) */ + [32] = BSP_PRV_VECT_ENUM(EVENT_SCI9_TEI,FIXED), /* SCI9 TEI (Transmit end) */ + [33] = BSP_PRV_VECT_ENUM(EVENT_SCI9_ERI,FIXED), /* SCI9 ERI (Receive error) */ + [34] = BSP_PRV_VECT_ENUM(EVENT_SPI1_RXI,FIXED), /* SPI1 RXI (Receive buffer full) */ + [35] = BSP_PRV_VECT_ENUM(EVENT_SPI1_TEI,FIXED), /* SPI1 TEI (Transmission complete event) */ + [36] = BSP_PRV_VECT_ENUM(EVENT_SPI1_ERI,FIXED), /* SPI1 ERI (Error) */ + [37] = BSP_PRV_VECT_ENUM(EVENT_DMAC1_INT,FIXED), /* DMAC1 INT (DMAC1 transfer end) */ + [38] = BSP_PRV_VECT_ENUM(EVENT_CAN0_CHERR,FIXED), /* CAN0 CHERR (Channel error) */ + [39] = BSP_PRV_VECT_ENUM(EVENT_CAN0_TX,FIXED), /* CAN0 TX (Transmit interrupt) */ + [40] = BSP_PRV_VECT_ENUM(EVENT_CAN0_COMFRX,FIXED), /* CAN0 COMFRX (Common FIFO receive interrupt) */ + [41] = BSP_PRV_VECT_ENUM(EVENT_CAN_GLERR,FIXED), /* CAN GLERR (Global error) */ + [42] = BSP_PRV_VECT_ENUM(EVENT_CAN_RXF,FIXED), /* CAN RXF (Global receive FIFO interrupt) */ + [43] = BSP_PRV_VECT_ENUM(EVENT_FCU_FRDYI,FIXED), /* FCU FRDYI (Flash ready interrupt) */ + [44] = BSP_PRV_VECT_ENUM(EVENT_FCU_FIFERR,FIXED), /* FCU FIFERR (Flash access error interrupt) */ + }; + #endif + #endif \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/vector_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/vector_data.h new file mode 100644 index 0000000000..b93ee4762f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/TARGET_FPB_RA6E2/vector_data.h @@ -0,0 +1,136 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated vector header file - do not edit */ + #ifndef VECTOR_DATA_H + #define VECTOR_DATA_H + #ifdef __cplusplus + extern "C" { + #endif + /* Number of interrupts allocated */ + #ifndef VECTOR_DATA_IRQ_COUNT + #define VECTOR_DATA_IRQ_COUNT (45) + #endif + /* ISR prototypes */ + void rtc_carry_isr(void); + void gpt_counter_overflow_isr(void); + void gpt_capture_compare_a_isr(void); + void r_icu_isr(void); + void spi_rxi_isr(void); + void spi_tei_isr(void); + void spi_eri_isr(void); + void dmac_int_isr(void); + void sci_uart_rxi_isr(void); + void sci_uart_txi_isr(void); + void sci_uart_tei_isr(void); + void sci_uart_eri_isr(void); + void iic_b_master_rxi_isr(void); + void iic_b_master_txi_isr(void); + void iic_b_master_tei_isr(void); + void iic_b_master_eri_isr(void); + void canfd_error_isr(void); + void canfd_channel_tx_isr(void); + void canfd_common_fifo_rx_isr(void); + void canfd_rx_fifo_isr(void); + void fcu_frdyi_isr(void); + void fcu_fiferr_isr(void); + + /* Vector table allocations */ + #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type) 0) /* RTC CARRY (Carry interrupt) */ + #define RTC_CARRY_IRQn ((IRQn_Type) 0) /* RTC CARRY (Carry interrupt) */ + #define VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW ((IRQn_Type) 1) /* GPT1 COUNTER OVERFLOW (Overflow) */ + #define GPT1_COUNTER_OVERFLOW_IRQn ((IRQn_Type) 1) /* GPT1 COUNTER OVERFLOW (Overflow) */ + #define VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A ((IRQn_Type) 2) /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + #define GPT1_CAPTURE_COMPARE_A_IRQn ((IRQn_Type) 2) /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 3) /* ICU IRQ0 (External pin interrupt 0) */ + #define ICU_IRQ0_IRQn ((IRQn_Type) 3) /* ICU IRQ0 (External pin interrupt 0) */ + #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type) 4) /* SPI0 RXI (Receive buffer full) */ + #define SPI0_RXI_IRQn ((IRQn_Type) 4) /* SPI0 RXI (Receive buffer full) */ + #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type) 5) /* SPI0 TEI (Transmission complete event) */ + #define SPI0_TEI_IRQn ((IRQn_Type) 5) /* SPI0 TEI (Transmission complete event) */ + #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type) 6) /* SPI0 ERI (Error) */ + #define SPI0_ERI_IRQn ((IRQn_Type) 6) /* SPI0 ERI (Error) */ + #define VECTOR_NUMBER_DMAC0_INT ((IRQn_Type) 7) /* DMAC0 INT (DMAC0 transfer end) */ + #define DMAC0_INT_IRQn ((IRQn_Type) 7) /* DMAC0 INT (DMAC0 transfer end) */ + #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 8) /* SCI0 RXI (Receive data full) */ + #define SCI0_RXI_IRQn ((IRQn_Type) 8) /* SCI0 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type) 9) /* SCI0 TXI (Transmit data empty) */ + #define SCI0_TXI_IRQn ((IRQn_Type) 9) /* SCI0 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type) 10) /* SCI0 TEI (Transmit end) */ + #define SCI0_TEI_IRQn ((IRQn_Type) 10) /* SCI0 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type) 11) /* SCI0 ERI (Receive error) */ + #define SCI0_ERI_IRQn ((IRQn_Type) 11) /* SCI0 ERI (Receive error) */ + #define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type) 12) /* ICU IRQ1 (External pin interrupt 1) */ + #define ICU_IRQ1_IRQn ((IRQn_Type) 12) /* ICU IRQ1 (External pin interrupt 1) */ + #define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type) 13) /* ICU IRQ2 (External pin interrupt 2) */ + #define ICU_IRQ2_IRQn ((IRQn_Type) 13) /* ICU IRQ2 (External pin interrupt 2) */ + #define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type) 14) /* ICU IRQ3 (External pin interrupt 3) */ + #define ICU_IRQ3_IRQn ((IRQn_Type) 14) /* ICU IRQ3 (External pin interrupt 3) */ + #define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type) 15) /* ICU IRQ4 (External pin interrupt 4) */ + #define ICU_IRQ4_IRQn ((IRQn_Type) 15) /* ICU IRQ4 (External pin interrupt 4) */ + #define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type) 16) /* ICU IRQ5 (External pin interrupt 5) */ + #define ICU_IRQ5_IRQn ((IRQn_Type) 16) /* ICU IRQ5 (External pin interrupt 5) */ + #define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type) 17) /* ICU IRQ6 (External pin interrupt 6) */ + #define ICU_IRQ6_IRQn ((IRQn_Type) 17) /* ICU IRQ6 (External pin interrupt 6) */ + #define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type) 18) /* ICU IRQ7 (External pin interrupt 7) */ + #define ICU_IRQ7_IRQn ((IRQn_Type) 18) /* ICU IRQ7 (External pin interrupt 7) */ + #define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type) 19) /* ICU IRQ8 (External pin interrupt 8) */ + #define ICU_IRQ8_IRQn ((IRQn_Type) 19) /* ICU IRQ8 (External pin interrupt 8) */ + #define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type) 20) /* ICU IRQ9 (External pin interrupt 9) */ + #define ICU_IRQ9_IRQn ((IRQn_Type) 20) /* ICU IRQ9 (External pin interrupt 9) */ + #define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type) 21) /* ICU IRQ10 (External pin interrupt 10) */ + #define ICU_IRQ10_IRQn ((IRQn_Type) 21) /* ICU IRQ10 (External pin interrupt 10) */ + #define VECTOR_NUMBER_IICB0_RXI ((IRQn_Type) 22) /* IICB0 RXI (Receive) */ + #define IICB0_RXI_IRQn ((IRQn_Type) 22) /* IICB0 RXI (Receive) */ + #define VECTOR_NUMBER_IICB0_TXI ((IRQn_Type) 23) /* IICB0 TXI (Transmit) */ + #define IICB0_TXI_IRQn ((IRQn_Type) 23) /* IICB0 TXI (Transmit) */ + #define VECTOR_NUMBER_IICB0_TEI ((IRQn_Type) 24) /* IICB0 TEI (Transmit end) */ + #define IICB0_TEI_IRQn ((IRQn_Type) 24) /* IICB0 TEI (Transmit end) */ + #define VECTOR_NUMBER_IICB0_ERI ((IRQn_Type) 25) /* IICB0 ERI (Error) */ + #define IICB0_ERI_IRQn ((IRQn_Type) 25) /* IICB0 ERI (Error) */ + #define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type) 26) /* ICU IRQ11 (External pin interrupt 11) */ + #define ICU_IRQ11_IRQn ((IRQn_Type) 26) /* ICU IRQ11 (External pin interrupt 11) */ + #define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type) 27) /* ICU IRQ12 (External pin interrupt 12) */ + #define ICU_IRQ12_IRQn ((IRQn_Type) 27) /* ICU IRQ12 (External pin interrupt 12) */ + #define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type) 28) /* ICU IRQ13 (External pin interrupt 13) */ + #define ICU_IRQ13_IRQn ((IRQn_Type) 28) /* ICU IRQ13 (External pin interrupt 13) */ + #define VECTOR_NUMBER_ICU_IRQ14 ((IRQn_Type) 29) /* ICU IRQ14 (External pin interrupt 14) */ + #define ICU_IRQ14_IRQn ((IRQn_Type) 29) /* ICU IRQ14 (External pin interrupt 14) */ + #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 30) /* SCI9 RXI (Receive data full) */ + #define SCI9_RXI_IRQn ((IRQn_Type) 30) /* SCI9 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 31) /* SCI9 TXI (Transmit data empty) */ + #define SCI9_TXI_IRQn ((IRQn_Type) 31) /* SCI9 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type) 32) /* SCI9 TEI (Transmit end) */ + #define SCI9_TEI_IRQn ((IRQn_Type) 32) /* SCI9 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 33) /* SCI9 ERI (Receive error) */ + #define SCI9_ERI_IRQn ((IRQn_Type) 33) /* SCI9 ERI (Receive error) */ + #define VECTOR_NUMBER_SPI1_RXI ((IRQn_Type) 34) /* SPI1 RXI (Receive buffer full) */ + #define SPI1_RXI_IRQn ((IRQn_Type) 34) /* SPI1 RXI (Receive buffer full) */ + #define VECTOR_NUMBER_SPI1_TEI ((IRQn_Type) 35) /* SPI1 TEI (Transmission complete event) */ + #define SPI1_TEI_IRQn ((IRQn_Type) 35) /* SPI1 TEI (Transmission complete event) */ + #define VECTOR_NUMBER_SPI1_ERI ((IRQn_Type) 36) /* SPI1 ERI (Error) */ + #define SPI1_ERI_IRQn ((IRQn_Type) 36) /* SPI1 ERI (Error) */ + #define VECTOR_NUMBER_DMAC1_INT ((IRQn_Type) 37) /* DMAC1 INT (DMAC1 transfer end) */ + #define DMAC1_INT_IRQn ((IRQn_Type) 37) /* DMAC1 INT (DMAC1 transfer end) */ + #define VECTOR_NUMBER_CAN0_CHERR ((IRQn_Type) 38) /* CAN0 CHERR (Channel error) */ + #define CAN0_CHERR_IRQn ((IRQn_Type) 38) /* CAN0 CHERR (Channel error) */ + #define VECTOR_NUMBER_CAN0_TX ((IRQn_Type) 39) /* CAN0 TX (Transmit interrupt) */ + #define CAN0_TX_IRQn ((IRQn_Type) 39) /* CAN0 TX (Transmit interrupt) */ + #define VECTOR_NUMBER_CAN0_COMFRX ((IRQn_Type) 40) /* CAN0 COMFRX (Common FIFO receive interrupt) */ + #define CAN0_COMFRX_IRQn ((IRQn_Type) 40) /* CAN0 COMFRX (Common FIFO receive interrupt) */ + #define VECTOR_NUMBER_CAN_GLERR ((IRQn_Type) 41) /* CAN GLERR (Global error) */ + #define CAN_GLERR_IRQn ((IRQn_Type) 41) /* CAN GLERR (Global error) */ + #define VECTOR_NUMBER_CAN_RXF ((IRQn_Type) 42) /* CAN RXF (Global receive FIFO interrupt) */ + #define CAN_RXF_IRQn ((IRQn_Type) 42) /* CAN RXF (Global receive FIFO interrupt) */ + #define VECTOR_NUMBER_FCU_FRDYI ((IRQn_Type) 43) /* FCU FRDYI (Flash ready interrupt) */ + #define FCU_FRDYI_IRQn ((IRQn_Type) 43) /* FCU FRDYI (Flash ready interrupt) */ + #define VECTOR_NUMBER_FCU_FIFERR ((IRQn_Type) 44) /* FCU FIFERR (Flash access error interrupt) */ + #define FCU_FIFERR_IRQn ((IRQn_Type) 44) /* FCU FIFERR (Flash access error interrupt) */ + /* The number of entries required for the ICU vector table. */ + #define BSP_ICU_VECTOR_NUM_ENTRIES (45) + + #ifdef __cplusplus + } + #endif + #endif /* VECTOR_DATA_H */ \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/board_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/board_cfg.h new file mode 100644 index 0000000000..68092dfbe6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/board_cfg.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "./TARGET_FPB_RA6E2/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_cfg.h new file mode 100644 index 0000000000..5f58c88216 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_cfg.h @@ -0,0 +1,71 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "bsp_mcu_ofs_cfg.h" + #include "board_cfg.h" + #include "vector_data.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (1) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #if MBED_CONF_RTOS_PRESENT + #define BSP_CFG_STACK_MAIN_BYTES (MBED_CONF_TARGET_BOOT_STACK_SIZE) + #else + #define BSP_CFG_STACK_MAIN_BYTES (MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE) + #endif + #define BSP_CFG_HEAP_BYTES (0) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_device_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_device_cfg.h new file mode 100644 index 0000000000..9901acf55e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_device_cfg.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_device_pn_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000000..2eea91a55a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,16 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6E2BB3CFM + #define BSP_MCU_FEATURE_SET ('B') + #define BSP_NUMBER_OF_CORES (1) + #define BSP_PACKAGE_LQFP + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (40960) + #define BSP_DATA_FLASH_SIZE_BYTES (4096) + #define BSP_PACKAGE_PINS (64) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_family_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_family_cfg.h new file mode 100644 index 0000000000..1c930e2788 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_family_cfg.h @@ -0,0 +1,294 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra6e2/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA6E2 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + + #define BSP_CFG_FLL_ENABLE (0) + + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + + #if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif + + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL + #define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL + #define FPU_FPCCR_TS_VAL (1U) +#endif + #define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL + #define FPU_FPCCR_CLRONRET_VAL (1) +#endif + + /* The C-Cache line size that is configured during startup. */ +#ifndef BSP_CFG_C_CACHE_LINE_SIZE + #define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif + + /* Type 1 Peripheral Security Attribution */ + + /* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CEC */ | \ + (((1 > 0) ? 0U : 1U) << 4) /* I3C0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((1 > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((1 > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x7FB3F7E7U) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((1 > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((1 > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ + (((1 > 0) ? 0U : 1U) << 28) /* TRNG */ | \ + 0xE7FFDEFC) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((1 > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((1 > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((1 > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((1 > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xFFAE87F3) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((1 > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((1 > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((1 > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((1 > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((1 > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x03FFFFF8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((2 > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + + /* Type 2 Peripheral Security Attribution */ + + /* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + + /* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + + /* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR + /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ +#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) +#define BSP_TZ_CFG_LVDSAR (0U) +#else +#define BSP_TZ_CFG_LVDSAR (3U) +#endif +#endif + + /* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((1 > 0) ? 0xFFFFDCEAU : 0xFFFFFFFFU) +#endif + /* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((1 > 0) ? 0xFAE0A00CU : 0xFFFFFFFFU) +#endif + + /* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFEAF602U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + + /* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((1 > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((1 > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((1 > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((1 > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((1 > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((1 > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((1 > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((1 > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((1 > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((1 > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((1 > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((1 > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((1 > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + 0xFFFF8000U) +#endif + + /* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + + /* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((1 > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((1 > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + + /* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((1 > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + + /* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((1 > 0) ? 0x84F2FFFFU : 0xFFFFFFFFU) +#endif + + /* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((1 > 0) ? 0xFFFFF7FFU : 0xFFFFFFFFU) +#endif + + /* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED + #define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + + /* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + + /* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ + #define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + + /* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + + /* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + + /* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif + /* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + /* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_ofs_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_ofs_cfg.h new file mode 100644 index 0000000000..f735b236b4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_mcu_ofs_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_OFS_CFG_H_ +#define BSP_MCU_OFS_CFG_H_ +#ifndef BSP_CFG_OPTION_SETTING_OFS0 +#define OFS_IWDT (0xA001A001 | 1 << 1 | 3 << 2 | 15 << 4 | 3 << 8 | 3 << 10 | 1 << 12 | 1 << 14) +#define OFS_WDT (1 << 17 | 3 << 18 | 15 << 20 | 3 << 24 | 3 << 26 | 1 << 28 | 1 << 30) +#define BSP_CFG_OPTION_SETTING_OFS0 (OFS_IWDT | OFS_WDT) +#endif +#ifndef BSP_CFG_OPTION_SETTING_OFS1_SEC +#define BSP_CFG_OPTION_SETTING_OFS1_SEC_NO_HOCOFRQ (0xFFFFF8F8 | (1 <<2) | (3) | (1 << 8)) + +#define BSP_CFG_OPTION_SETTING_OFS1_SEC ((uint32_t) BSP_CFG_OPTION_SETTING_OFS1_SEC_NO_HOCOFRQ | ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) +#endif +#endif /* BSP_MCU_OFS_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_pin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_pin_cfg.h new file mode 100644 index 0000000000..60da6244ac --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/bsp_pin_cfg.h @@ -0,0 +1,59 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define ARDUINO_A0 (BSP_IO_PORT_00_PIN_00) +#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01) +#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_02) +#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_03) +#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_04) +#define PMOD1_RESET (BSP_IO_PORT_00_PIN_05) +#define ARDUINO_D8 (BSP_IO_PORT_00_PIN_06) +#define ARDUINO_D7 (BSP_IO_PORT_00_PIN_08) +#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_13) +#define PMOD2_GPIO1 (BSP_IO_PORT_00_PIN_14) +#define PMOD2_GPIO2 (BSP_IO_PORT_00_PIN_15) +#define I3C_SCL_ARDUINO_SCL (BSP_IO_PORT_01_PIN_00) +#define I3C_SDA_ARDUINO_SDA (BSP_IO_PORT_01_PIN_01) +#define PMOD2_SCK (BSP_IO_PORT_01_PIN_02) +#define ARDUINO_D2 (BSP_IO_PORT_01_PIN_05) +#define PMOD1_GPIO1 (BSP_IO_PORT_01_PIN_06) +#define PMOD1_GPIO2 (BSP_IO_PORT_01_PIN_07) +#define DEBUG_SWDIO (BSP_IO_PORT_01_PIN_08) +#define PMOD1_TX_ARDUINO_D11 (BSP_IO_PORT_01_PIN_09) +#define PMOD1_RX_ARDUINO_D12 (BSP_IO_PORT_01_PIN_10) +#define PMOD1_RSPCK_ARDUINO_D13 (BSP_IO_PORT_01_PIN_11) +#define ARDUINO_D6 (BSP_IO_PORT_01_PIN_13) +#define NMI (BSP_IO_PORT_02_PIN_00) +#define BOOT_MODE (BSP_IO_PORT_02_PIN_01) +#define PMOD2_IRQ (BSP_IO_PORT_02_PIN_05) +#define ARDUINO_RESET (BSP_IO_PORT_02_PIN_08) +#define DEBUG_SWDCLK (BSP_IO_PORT_03_PIN_00) +#define ARDUINO_D10 (BSP_IO_PORT_03_PIN_01) +#define SW1 (BSP_IO_PORT_03_PIN_04) +#define I2C_I3C_SEL_SCL (BSP_IO_PORT_04_PIN_00) +#define I2C_I3C_SEL_SDA (BSP_IO_PORT_04_PIN_01) +#define PMOD1_IRQ (BSP_IO_PORT_04_PIN_02) +#define ARDUINO_D9 (BSP_IO_PORT_04_PIN_03) +#define PMOD2_RESET (BSP_IO_PORT_04_PIN_07) +#define ARDUINO_D3 (BSP_IO_PORT_04_PIN_08) +#define ARDUINO_D5 (BSP_IO_PORT_04_PIN_09) +#define PMOD2_MISO_ARDUINO_D0 (BSP_IO_PORT_04_PIN_10) +#define PMOD2_MOSI_ARDUINO_D1 (BSP_IO_PORT_04_PIN_11) +#define ARDUINO_D4 (BSP_IO_PORT_05_PIN_00) + +extern const ioport_cfg_t g_bsp_pin_cfg; /* FPB_RA4E1.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/can_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/can_device.c new file mode 100644 index 0000000000..e61e142863 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/can_device.c @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "PeripheralNames.h" +#include "hal_data.h" +#include "device.h" + +const can_instance_t * const g_can_instances[CAN_COUNT] = { + &g_canfd0, +}; + +canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH0_RULE_NUM]; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/flash_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/flash_device.h new file mode 100644 index 0000000000..4283436631 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/flash_device.h @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef FLASH_DEVICE_H +#define FLASH_DEVICE_H + +/* RA6E2: 512KB Code Flash, 8KB Data Flash */ +#ifndef RA_CF_START +#define RA_CF_START (0x00000000u) +#endif +#ifndef RA_CF_SIZE +#define RA_CF_SIZE (512u * 1024u) +#endif +#ifndef RA_CF_WRITE_SIZE +#define RA_CF_WRITE_SIZE (128u) +#endif + +#ifndef RA_DF_START +#define RA_DF_START (0x08000000u) +#endif +#ifndef RA_DF_SIZE +#define RA_DF_SIZE (8u * 1024u) +#endif +#ifndef RA_DF_SECTOR_SIZE +#define RA_DF_SECTOR_SIZE (64u) +#endif +#ifndef RA_DF_WRITE_SIZE +#define RA_DF_WRITE_SIZE (4u) +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/gpio_irq_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/gpio_irq_device.c new file mode 100644 index 0000000000..b207b58ed3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/gpio_irq_device.c @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "PeripheralNames.h" +#include "common_data.h" +#include "device.h" + +icu_instance_ctrl_t * const g_icu_ctrl[IRQ_CHANNELS_COUNT] = { + &g_external_irq0_ctrl, + &g_external_irq1_ctrl, + &g_external_irq2_ctrl, + &g_external_irq3_ctrl, + &g_external_irq4_ctrl, + &g_external_irq5_ctrl, + &g_external_irq6_ctrl, + &g_external_irq7_ctrl, + &g_external_irq8_ctrl, + &g_external_irq9_ctrl, + &g_external_irq10_ctrl, + &g_external_irq11_ctrl, + &g_external_irq12_ctrl, + &g_external_irq13_ctrl, + &g_external_irq14_ctrl, +}; + +const external_irq_cfg_t * const g_icu_cfg[IRQ_CHANNELS_COUNT] = { + &g_external_irq0_cfg, + &g_external_irq1_cfg, + &g_external_irq2_cfg, + &g_external_irq3_cfg, + &g_external_irq4_cfg, + &g_external_irq5_cfg, + &g_external_irq6_cfg, + &g_external_irq7_cfg, + &g_external_irq8_cfg, + &g_external_irq9_cfg, + &g_external_irq10_cfg, + &g_external_irq11_cfg, + &g_external_irq12_cfg, + &g_external_irq13_cfg, + &g_external_irq14_cfg, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/i2c_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/i2c_device.h new file mode 100644 index 0000000000..bfc2aa3ebe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/i2c_device.h @@ -0,0 +1,21 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef I2C_DEVICE_H +#define I2C_DEVICE_H + +#include "r_iic_b_master.h" + +typedef struct { + int hz; + iic_b_master_clock_settings_t clk; +} iic_clock_entry_t; + +static const iic_clock_entry_t g_iic_clock_table[] = { + { 100000, { .cks_value = 1, .brh_value = 243, .brl_value = 244, .sdod_value = 0, .sdodcs_value = 0 }}, + { 400000, { .cks_value = 0, .brh_value = 112, .brl_value = 113, .sdod_value = 0, .sdodcs_value = 0 }}, + {1000000, { .cks_value = 0, .brh_value = 37, .brl_value = 37, .sdod_value = 0, .sdodcs_value = 0 }}, +}; + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/pwmout_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/pwmout_device.h new file mode 100644 index 0000000000..af5c4afc1e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/pwmout_device.h @@ -0,0 +1,23 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "PeripheralNames.h" +#include "hal_data.h" + +const timer_instance_t *pwm_timer_lookup(PWMName name) +{ + switch (name) { + case PWM_GPT0: return &g_timer_gpt0; + case PWM_GPT1: return &g_timer_gpt1; + case PWM_GPT2: return &g_timer_gpt2; + case PWM_GPT3: return &g_timer_gpt3; + case PWM_GPT4: return &g_timer_gpt4; + case PWM_GPT5: return &g_timer_gpt5; + case PWM_AGT0: return &g_timer_agt0; + case PWM_AGT1: return &g_timer_agt1; + default: return NULL; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_acmphs_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_acmphs_cfg.h new file mode 100644 index 0000000000..fc8046a7f5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_acmphs_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ACMPHS_CFG_H_ +#define R_ACMPHS_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ACMPHS_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ACMPHS_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_acmplp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_acmplp_cfg.h new file mode 100644 index 0000000000..a66ead8b31 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_acmplp_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ACMPLP_CFG_H_ +#define R_ACMPLP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ACMPLP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ACMPLP_CFG_CH1_IVREF0_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_ACMPLP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_adc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_adc_cfg.h new file mode 100644 index 0000000000..d16c3e39e7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_adc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ADC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_agt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_agt_cfg.h new file mode 100644 index 0000000000..0e70aee2cd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_agt_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define AGT_CFG_OUTPUT_SUPPORT_ENABLE (1) + #define AGT_CFG_INPUT_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_AGT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cac_cfg.h new file mode 100644 index 0000000000..a399409760 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CAC_CFG_H_ +#define R_CAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_canfd_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_canfd_cfg.h new file mode 100644 index 0000000000..d5b4b4a3ca --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_canfd_cfg.h @@ -0,0 +1,158 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CANFD_CFG_H_ +#define R_CANFD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CANFD_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #define CANFD_CFG_AFL_CH0_RULE_NUM (16) + #define CANFD_CFG_AFL_CH1_RULE_NUM (0) + + #define CANFD_CFG_GLOBAL_ERROR_CH ((0U)) + + #define CANFD_CFG_FD_PROTOCOL_EXCEPTION ((0)) + #define CANFD_CFG_GLOBAL_ERR_IPL ((12)) + #define CANFD_CFG_RX_FIFO_IPL ((12)) + #define CANFD_CFG_GLOBAL_ERR_SOURCES ( 0x3) + #define CANFD_CFG_TX_PRIORITY ((R_CANFD_CFDGCFG_TPRI_Msk)) + #define CANFD_CFG_DLC_CHECK ((0)) + #define CANFD_CFG_FD_OVERFLOW ((0)) + #define CANFD_CFG_RXMB_NUMBER (0) + #define CANFD_CFG_RXMB_SIZE ((0)) + #define CANFD_CFG_RXFIFO0_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO0_DEPTH ((3)) + #define CANFD_CFG_RXFIFO0_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO0_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO0_ENABLE ((1)) + + #define CANFD_CFG_RXFIFO1_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO1_DEPTH ((3)) + #define CANFD_CFG_RXFIFO1_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO1_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO1_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO2_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO2_DEPTH ((3)) + #define CANFD_CFG_RXFIFO2_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO2_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO2_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO3_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO3_DEPTH ((3)) + #define CANFD_CFG_RXFIFO3_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO3_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO3_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO4_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO4_DEPTH ((3)) + #define CANFD_CFG_RXFIFO4_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO4_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO4_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO5_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO5_DEPTH ((3)) + #define CANFD_CFG_RXFIFO5_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO5_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO5_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO6_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO6_DEPTH ((3)) + #define CANFD_CFG_RXFIFO6_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO6_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO6_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO7_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO7_DEPTH ((3)) + #define CANFD_CFG_RXFIFO7_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO7_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO7_ENABLE ((0)) + + #define CANFD_CFG_COMMONFIFO0 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO1 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO2 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO3 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO4 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO5 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + + #ifdef __cplusplus + } + #endif +#endif /* R_CANFD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cec_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cec_cfg.h new file mode 100644 index 0000000000..8a583197f2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cec_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CEC_CFG_H_ +#define R_CEC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CEC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define CEC_DATA_BUFFER_LENGTH (14) + + #ifdef __cplusplus + } + #endif +#endif /* R_CEC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ceu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ceu_cfg.h new file mode 100644 index 0000000000..12c0fd54f8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ceu_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CEU_CFG_H_ +#define R_CEU_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CEU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CEU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cgc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cgc_cfg.h new file mode 100644 index 0000000000..ffbf789754 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_cgc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CGC_CFG_H_ +#define R_CGC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CGC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define CGC_CFG_USE_LOW_VOLTAGE_MODE RA_NOT_DEFINED + +#ifdef __cplusplus +} +#endif +#endif /* R_CGC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_crc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_crc_cfg.h new file mode 100644 index 0000000000..5de5d44d04 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_crc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CRC_CFG_H_ +#define R_CRC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CRC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CRC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ctsu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ctsu_cfg.h new file mode 100644 index 0000000000..846940d95b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ctsu_cfg.h @@ -0,0 +1,237 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CTSU_CFG_H_ +#define R_CTSU_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CTSU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define CTSU_CFG_DTC_SUPPORT_ENABLE (0) + #define CTSU_CFG_INT_PRIORITY_LEVEL (12) + #define CTSU_CFG_AUTO_JUDGE_ENABLE (0) + #ifndef QE_TOUCH_CONFIGURATION + #define CTSU_CFG_NUM_SELF_ELEMENTS (1) + #define CTSU_CFG_NUM_MUTUAL_ELEMENTS (0) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + #define CTSU_CFG_MAJORITY_MODE (2) + #define CTSU_CFG_NUM_AUTOJUDGE_SELF_ELEMENTS (1) + #define CTSU_CFG_NUM_AUTOJUDGE_MUTUAL_ELEMENTS (0) + #define CTSU_CFG_AUTO_CORRECTION_ENABLE (1) + #else + #define CTSU_CFG_MAJORITY_MODE (1) + #define CTSU_CFG_NUM_AUTOJUDGE_SELF_ELEMENTS (0) + #define CTSU_CFG_NUM_AUTOJUDGE_MUTUAL_ELEMENTS (0) + #define CTSU_CFG_AUTO_CORRECTION_ENABLE (0) + #endif + #define CTSU_CFG_LOW_VOLTAGE_MODE (0) + #define CTSU_CFG_PCLK_DIVISION (0) + #define CTSU_CFG_TSCAP_PORT (0xFFFF) + #define CTSU_CFG_VCC_MV (5000) + #define CTSU_CFG_DIAG_SUPPORT_ENABLE (0) + #if (BSP_FEATURE_CTSU_VERSION == 2) + #define CTSU_CFG_NUM_CFC (0) + #define CTSU_CFG_NUM_CFC_TX (0) + #define CTSU_CFG_NUM_SUMULTI (3) + #define CTSU_CFG_SUMULTI0 (0x3F) + #define CTSU_CFG_SUMULTI1 (0x36) + #define CTSU_CFG_SUMULTI2 (0x48) + #define CTSU_CFG_TEMP_CORRECTION_SUPPORT (0) + #define CTSU_CFG_TEMP_CORRECTION_TS (0) + #define CTSU_CFG_TEMP_CORRECTION_TIME (0) + #define CTSU_CFG_CALIB_RTRIM_SUPPORT (0) + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + #define CTSU_CFG_NUM_SUMULTI (1) + #endif + #endif + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + #if (BSP_FEATURE_CTSU_VERSION == 1) + #if (BSP_CFG_MCU_PART_SERIES == 2) || (BSP_CFG_MCU_PART_SERIES == 4) + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (54888) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (29062) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (3269) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (705) + #define CTSU_CFG_DIAG_SSCG_MAX (21813) + #define CTSU_CFG_DIAG_SSCG_MIN (11782) + #define CTSU_CFG_DIAG_DAC1_MAX (20422) + #define CTSU_CFG_DIAG_DAC2_MAX (21532) + #define CTSU_CFG_DIAG_DAC3_MAX (23015) + #define CTSU_CFG_DIAG_DAC4_MAX (25923) + #define CTSU_CFG_DIAG_DAC5_MAX (32016) + #define CTSU_CFG_DIAG_DAC6_MAX (45795) + #define CTSU_CFG_DIAG_DAC1_MIN (12492) + #define CTSU_CFG_DIAG_DAC2_MIN (14053) + #define CTSU_CFG_DIAG_DAC3_MIN (15322) + #define CTSU_CFG_DIAG_DAC4_MIN (18070) + #define CTSU_CFG_DIAG_DAC5_MIN (23262) + #define CTSU_CFG_DIAG_DAC6_MIN (33446) + + #else + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (43910) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (23249) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (2615) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (564) + #define CTSU_CFG_DIAG_SSCG_MAX (21813) + #define CTSU_CFG_DIAG_SSCG_MIN (11782) + #define CTSU_CFG_DIAG_DAC1_MAX (16599) + #define CTSU_CFG_DIAG_DAC2_MAX (17226) + #define CTSU_CFG_DIAG_DAC3_MAX (18412) + #define CTSU_CFG_DIAG_DAC4_MAX (20738) + #define CTSU_CFG_DIAG_DAC5_MAX (25613) + #define CTSU_CFG_DIAG_DAC6_MAX (36636) + #define CTSU_CFG_DIAG_DAC1_MIN (9994) + #define CTSU_CFG_DIAG_DAC2_MIN (11242) + #define CTSU_CFG_DIAG_DAC3_MIN (12258) + #define CTSU_CFG_DIAG_DAC4_MIN (14456) + #define CTSU_CFG_DIAG_DAC5_MIN (18610) + #define CTSU_CFG_DIAG_DAC6_MIN (26757) + #endif + #endif + #if (BSP_CFG_MCU_PART_SERIES == 6) + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (36873) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (24433) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (1781) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (105) + #define CTSU_CFG_DIAG_SSCG_MAX (17795) + #define CTSU_CFG_DIAG_SSCG_MIN (9610) + #define CTSU_CFG_DIAG_DAC1_MAX (20422) + #define CTSU_CFG_DIAG_DAC2_MAX (21532) + #define CTSU_CFG_DIAG_DAC3_MAX (23015) + #define CTSU_CFG_DIAG_DAC4_MAX (25923) + #define CTSU_CFG_DIAG_DAC5_MAX (32016) + #define CTSU_CFG_DIAG_DAC6_MAX (45795) + #define CTSU_CFG_DIAG_DAC1_MIN (12492) + #define CTSU_CFG_DIAG_DAC2_MIN (14053) + #define CTSU_CFG_DIAG_DAC3_MIN (15322) + #define CTSU_CFG_DIAG_DAC4_MIN (18070) + #define CTSU_CFG_DIAG_DAC5_MIN (23262) + #define CTSU_CFG_DIAG_DAC6_MIN (33446) + #endif + #endif + + #if (BSP_FEATURE_CTSU_VERSION == 2) + #define CTSU_DIAG_TSCAP_RANGE_LOW (1050) + #define CTSU_DIAG_TSCAP_RANGE_HIGH (1419) + + #define CTSU_CFG_DIAG_LOAD_REISTER_MIN (11951) + #define CTSU_CFG_DIAG_LOAD_REISTER_MAX (23957) + + #define CTSU_CFG_DIAG_CURRENT_SOURCE_DIFF_MIN (2890) + #define CTSU_CFG_DIAG_CURRENT_SOURCE_DIFF_MAX (5703) + + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CFG_DIAG_DAC1_MIN (1486) + #define CTSU_CFG_DIAG_DAC2_MIN (2890) + #define CTSU_CFG_DIAG_DAC3_MIN (4202) + #define CTSU_CFG_DIAG_DAC4_MIN (5448) + #define CTSU_CFG_DIAG_DAC5_MIN (6641) + #define CTSU_CFG_DIAG_DAC6_MIN (7787) + #define CTSU_CFG_DIAG_DAC7_MIN (8891) + #define CTSU_CFG_DIAG_DAC8_MIN (9954) + #define CTSU_CFG_DIAG_DAC9_MIN (10974) + #define CTSU_CFG_DIAG_DAC10_MIN (11951) + #define CTSU_CFG_DIAG_DAC11_MIN (12880) + #define CTSU_CFG_DIAG_DAC12_MIN (13761) + + #define CTSU_CFG_DIAG_DAC1_MAX (3057) + #define CTSU_CFG_DIAG_DAC2_MAX (5703) + #define CTSU_CFG_DIAG_DAC3_MAX (8292) + #define CTSU_CFG_DIAG_DAC4_MAX (10838) + #define CTSU_CFG_DIAG_DAC5_MAX (13269) + #define CTSU_CFG_DIAG_DAC6_MAX (15593) + #define CTSU_CFG_DIAG_DAC7_MAX (17816) + #define CTSU_CFG_DIAG_DAC8_MAX (19948) + #define CTSU_CFG_DIAG_DAC9_MAX (21992) + #define CTSU_CFG_DIAG_DAC10_MAX (23957) + #define CTSU_CFG_DIAG_DAC11_MAX (25843) + #define CTSU_CFG_DIAG_DAC12_MAX (27651) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MIN (1384) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MIN (1293) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MIN (1228) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MIN (1176) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MIN (1129) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MIN (1083) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MIN (1037) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MIN (987) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MIN (929) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MIN (867) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MIN (807) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MAX (2781) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MAX (2678) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MAX (2567) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MAX (2458) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MAX (2355) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MAX (2255) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MAX (2166) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MAX (2077) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MAX (1998) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MAX (1921) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MAX (1841) + #else + + #define CTSU_CFG_DIAG_DAC1_MIN (1039) + #define CTSU_CFG_DIAG_DAC2_MIN (2113) + #define CTSU_CFG_DIAG_DAC3_MIN (3130) + #define CTSU_CFG_DIAG_DAC4_MIN (4108) + #define CTSU_CFG_DIAG_DAC5_MIN (5049) + #define CTSU_CFG_DIAG_DAC6_MIN (5961) + #define CTSU_CFG_DIAG_DAC7_MIN (6848) + #define CTSU_CFG_DIAG_DAC8_MIN (7713) + #define CTSU_CFG_DIAG_DAC9_MIN (8554) + #define CTSU_CFG_DIAG_DAC10_MIN (9374) + #define CTSU_CFG_DIAG_DAC11_MIN (10176) + #define CTSU_CFG_DIAG_DAC12_MIN (10945) + + #define CTSU_CFG_DIAG_DAC1_MAX (2627) + #define CTSU_CFG_DIAG_DAC2_MAX (4899) + #define CTSU_CFG_DIAG_DAC3_MAX (6974) + #define CTSU_CFG_DIAG_DAC4_MAX (8907) + #define CTSU_CFG_DIAG_DAC5_MAX (10729) + #define CTSU_CFG_DIAG_DAC6_MAX (12476) + #define CTSU_CFG_DIAG_DAC7_MAX (14314) + #define CTSU_CFG_DIAG_DAC8_MAX (16089) + #define CTSU_CFG_DIAG_DAC9_MAX (17802) + #define CTSU_CFG_DIAG_DAC10_MAX (19462) + #define CTSU_CFG_DIAG_DAC11_MAX (21067) + #define CTSU_CFG_DIAG_DAC12_MAX (22624) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MIN (1081) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MIN (1013) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MIN (967) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MIN (929) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MIN (899) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MIN (867) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MIN (844) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MIN (821) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MIN (794) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MIN (762) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MIN (733) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MAX (2273) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MAX (2118) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MAX (2044) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MAX (1975) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MAX (1909) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MAX (1846) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MAX (1786) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MAX (1731) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MAX (1679) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MAX (1632) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MAX (1581) + #endif + #define CTSU_CFG_DIAG_CLOCK_RECOV_RANGE (20) + #endif + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_CTSU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dac_cfg.h new file mode 100644 index 0000000000..3db92ccc0a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DAC_CFG_H_ +#define R_DAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dmac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dmac_cfg.h new file mode 100644 index 0000000000..c772854a59 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dmac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DMAC_CFG_H_ +#define R_DMAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DMAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DMAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_doc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_doc_cfg.h new file mode 100644 index 0000000000..0124272c17 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_doc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DOC_CFG_H_ +#define R_DOC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DOC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DOC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_drw_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_drw_cfg.h new file mode 100644 index 0000000000..7ca818be9a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_drw_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DRW_CFG_H_ +#define R_DRW_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define DRW_CFG_USE_DLIST_INDIRECT ((1)) + #ifdef VECTOR_NUMBER_DRW_INT + #define DRW_CFG_INT_IRQ (VECTOR_NUMBER_DRW_INT) + #endif + #define DRW_CFG_CUSTOM_MALLOC ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_DRW_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dsmif_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dsmif_cfg.h new file mode 100644 index 0000000000..2c656fa920 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dsmif_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DSMIF_CFG_H_ +#define R_DSMIF_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DSMIF_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) +#define DSMIF_CFG_ERROR_DETECTION_SUPPORT ((1)) + +#ifdef __cplusplus +} +#endif +#endif /* R_DSMIF_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dtc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dtc_cfg.h new file mode 100644 index 0000000000..cd2f683dcf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_dtc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME BSP_UNINIT_SECTION_PREFIX ".fsp_dtc_vector_table" + +#ifdef __cplusplus +} +#endif +#endif /* R_DTC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_edmac.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_edmac.h new file mode 100644 index 0000000000..ff59ea997f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_edmac.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_EDMAC_H_ +#define R_EDMAC_H_ + +#endif /* R_EDMAC_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_elc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_elc_cfg.h new file mode 100644 index 0000000000..00864564b1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_elc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ELC_CFG_H_ +#define R_ELC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ELC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ELC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ether_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ether_cfg.h new file mode 100644 index 0000000000..34341ea337 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ether_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHER_CFG_H_ +#define R_ETHER_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ETHER_CFG_LINK_PRESENT (0) + #define ETHER_CFG_USE_LINKSTA (0) + #define ETHER_CFG_READ_BUFFER_SIZE_CHECK ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHER_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ether_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ether_phy_cfg.h new file mode 100644 index 0000000000..f84bae1260 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ether_phy_cfg.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHER_PHY_CFG_H_ +#define R_ETHER_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHER_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_DP83620_ENABLE + #define ETHER_PHY_CFG_TARGET_DP83620_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + #define ETHER_PHY_CFG_USE_REF_CLK (BOARD_PHY_REF_CLK) + #define ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHER_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ethercat_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ethercat_phy_cfg.h new file mode 100644 index 0000000000..d9c71487c8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ethercat_phy_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHERCAT_PHY_CFG_H_ +#define R_ETHERCAT_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHERCAT_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_flash_hp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_flash_hp_cfg.h new file mode 100644 index 0000000000..1aa7941ae2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_flash_hp_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_HP_CFG_H_ +#define R_FLASH_HP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) + #define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_FLASH_HP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_flash_lp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_flash_lp_cfg.h new file mode 100644 index 0000000000..f67c25a7b5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_flash_lp_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_LP_CFG_H_ +#define R_FLASH_LP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (0) + #define FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE 0 + #define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1) + #define FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE (1) + #define FLASH_LP_CFG_DUAL_BANK_INSTANT_SWAP 0 + + #ifdef __cplusplus + } + #endif +#endif /* R_FLASH_LP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_glcdc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_glcdc_cfg.h new file mode 100644 index 0000000000..eea5f0ca27 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_glcdc_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GLCDC_CFG_H_ +#define R_GLCDC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define GLCDC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define GLCDC_CFG_COLOR_CORRECTION_ENABLE (false) + + /* Enable DSI function handling */ + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define GLCDC_CFG_USING_DSI + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_GLCDC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gpt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gpt_cfg.h new file mode 100644 index 0000000000..d7caf17ca7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gpt_cfg.h @@ -0,0 +1,25 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPT_CFG_H_ +#define R_GPT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (1) +#define GPT_CFG_WRITE_PROTECT_ENABLE (0) + +#ifndef BSP_CFG_GPT_COUNT_CLOCK_SOURCE +#define GPT_CFG_GPTCLK_BYPASS (0) +#else +#define GPT_CFG_GPTCLK_BYPASS (BSP_CFG_GPT_COUNT_CLOCK_SOURCE) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* R_GPT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gpt_three_phase_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gpt_three_phase_cfg.h new file mode 100644 index 0000000000..d97d29d768 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gpt_three_phase_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPT_THREE_PHASE_CFG_H_ +#define R_GPT_THREE_PHASE_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_GPT_THREE_PHASE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gptp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gptp_cfg.h new file mode 100644 index 0000000000..f23e684f73 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_gptp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPTP_CFG_H_ +#define R_GPTP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define GPTP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_GPTP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_i3c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_i3c_cfg.h new file mode 100644 index 0000000000..b9a2bdcc2d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_i3c_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_I3C_CFG_H_ +#define R_I3C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define I3C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define I3C_CFG_UNALIGNED_BUFFER_SUPPORT (1) +#define I3C_CFG_MASTER_SUPPORT (1) +#define I3C_CFG_SLAVE_SUPPORT (1) +#define I3C_CFG_ERROR_RECOVERY_SUPPORT I3C_ERROR_RECOVERY_VERSION_2 + +#ifdef __cplusplus +} +#endif +#endif /* R_I3C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_icu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_icu_cfg.h new file mode 100644 index 0000000000..8422be1b4b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_icu_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ICU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iic_b_master_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iic_b_master_cfg.h new file mode 100644 index 0000000000..cce0f3c2dc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iic_b_master_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IIC_B_MASTER_CFG_H_ +#define R_IIC_B_MASTER_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_B_MASTER_CFG_DTC_ENABLE (0) +#define IIC_B_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_IIC_B_MASTER_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iirfa_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iirfa_cfg.h new file mode 100644 index 0000000000..8078ee15be --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iirfa_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IIRFA_CFG_H_ +#define R_IIRFA_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIRFA_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIRFA_CFG_LOOP_UNROLL_DEPTH (1) +#define IIRFA_CFG_LOOP_USE_POLLING (1) +#define IIRFA_CFG_ECC_SUPPORT (1) +#define IIRFA_CFG_ROUNDING_MODE (0) + + +#ifdef __cplusplus +} +#endif +#endif /* R_IIRFA_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ioport_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ioport_cfg.h new file mode 100644 index 0000000000..519ac3734a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ioport_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IOPORT_CFG_CCD_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ipc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ipc_cfg.h new file mode 100644 index 0000000000..7968dbcc75 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ipc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IPC_CFG_H_ +#define R_IPC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define IPC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_IPC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iwdt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iwdt_cfg.h new file mode 100644 index 0000000000..e097d20442 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_iwdt_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IWDT_CFG_H_ +#define R_IWDT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IWDT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IWDT_CFG_REGISTER_START_NMI_SUPPORTED ((0)) + +#ifdef __cplusplus +} +#endif +#endif /* R_IWDT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_jpeg_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_jpeg_cfg.h new file mode 100644 index 0000000000..9149d6c8fa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_jpeg_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_JPEG_CFG_H_ +#define R_JPEG_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define JPEG_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define JPEG_CFG_DECODE_ENABLE (1) + #define JPEG_CFG_ENCODE_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_JPEG_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_kint_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_kint_cfg.h new file mode 100644 index 0000000000..765da0d361 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_kint_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_KINT_CFG_H_ +#define R_KINT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define KINT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_KINT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_layer3_switch_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_layer3_switch_cfg.h new file mode 100644 index 0000000000..a74af95b70 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_layer3_switch_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LAYER3_SWITCH_CFG_H_ +#define R_LAYER3_SWITCH_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #define LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM (4) + + #define LAYER3_SWITCH_CFG_GPTP_ENABLE (1) + + #define LAYER3_SWITCH_CFG_TAS_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_LAYER3_SWITCH_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_lpm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_lpm_cfg.h new file mode 100644 index 0000000000..be928d2cb6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_lpm_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define LPM_CFG_STANDBY_LIMIT (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_LPM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_lvd_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_lvd_cfg.h new file mode 100644 index 0000000000..c8160e206d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_lvd_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LVD_CFG_H_ +#define R_LVD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LVD_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_LVD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mipi_csi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mipi_csi_cfg.h new file mode 100644 index 0000000000..06ccb51e46 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mipi_csi_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MIPI_CSI_CFG_H_ +#define R_MIPI_CSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MIPI_CSI_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_MIPI_CSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mipi_dsi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mipi_dsi_cfg.h new file mode 100644 index 0000000000..7acc8a1dda --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mipi_dsi_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MIPI_DSI_CFG_H_ +#define R_MIPI_DSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MIPI_DSI_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_MIPI_DSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mram_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mram_cfg.h new file mode 100644 index 0000000000..35aca39883 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_mram_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MRAM_CFG_H_ +#define R_MRAM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MRAM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_MRAM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_opamp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_opamp_cfg.h new file mode 100644 index 0000000000..2a4387e532 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_opamp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_OPAMP_CFG_H_ +#define R_OPAMP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define OPAMP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_OPAMP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ospi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ospi_cfg.h new file mode 100644 index 0000000000..fa170f5458 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ospi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_OSPI_CFG_H_ +#define R_OSPI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define OSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define OSPI_CFG_DMAC_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_OSPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_pdc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_pdc_cfg.h new file mode 100644 index 0000000000..509a1e4eb0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_pdc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PDC_CFG_H_ +#define R_PDC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define PDC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_PDC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_pdm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_pdm_cfg.h new file mode 100644 index 0000000000..8a3cd6c1bd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_pdm_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PDM_CFG_H_ +#define R_PDM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define PDM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define PDM_CFG_DMAC_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_PDM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_poeg_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_poeg_cfg.h new file mode 100644 index 0000000000..4bd1a5b99b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_poeg_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_POEG_CFG_H_ +#define R_POEG_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define POEG_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_POEG_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ptp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ptp_cfg.h new file mode 100644 index 0000000000..81182a841a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ptp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PTP_CFG_H_ +#define R_PTP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define PTP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_PTP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_qspi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_qspi_cfg.h new file mode 100644 index 0000000000..663afaefbc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_qspi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_QSPI_CFG_H_ +#define R_QSPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define QSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_QSPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rmac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rmac_cfg.h new file mode 100644 index 0000000000..b596fd0243 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rmac_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RMAC_CFG_H_ +#define R_RMAC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define RMAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define RMAC_CFG_READ_BUFFER_SIZE_CHECK ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_RMAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rmac_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rmac_phy_cfg.h new file mode 100644 index 0000000000..3268e93ff5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rmac_phy_cfg.h @@ -0,0 +1,36 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RMAC_PHY_CFG_H_ +#define R_RMAC_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define RMAC_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_DP83620_ENABLE + #define ETHER_PHY_CFG_TARGET_DP83620_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_GPY111_ENABLE + #define ETHER_PHY_CFG_TARGET_GPY111_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + #define ETHER_PHY_CFG_USE_REF_CLK (BOARD_PHY_REF_CLK) + + #ifdef __cplusplus + } + #endif +#endif /* R_RMAC_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rtc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rtc_cfg.h new file mode 100644 index 0000000000..12bff296fb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_rtc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define RTC_CFG_OPEN_SET_CLOCK_SOURCE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_RTC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_i2c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_i2c_cfg.h new file mode 100644 index 0000000000..cbd57f790b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_i2c_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_I2C_CFG_H_ +#define R_SAU_I2C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_I2C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_I2C_CFG_CRITICAL_SECTION_ENABLE (0) +#define SAU_I2C_CFG_MANUAL_START_STOP_ENABLE (0) +#define SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE config.driver.sau_i2c.single_channel_enable.disabled +#define SAU_I2C_CFG_RESTART_ENABLE (1) +#define SAU_I2C_CFG_DTC_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_I2C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_lin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_lin_cfg.h new file mode 100644 index 0000000000..cccc438932 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_lin_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_LIN_CFG_H_ +#define R_SAU_LIN_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_LIN_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE (1) +#define SAU_LIN_CFG_MASTER_SUPPORT_ENABLE (0) +#define SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE (1) +#define SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE (0) +#define SAU_LIN_AUTO_SYNC_SUPPORT_ENABLE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_LIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_spi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_spi_cfg.h new file mode 100644 index 0000000000..e381c0b8b3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_spi_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_SPI_CFG_H_ +#define R_SAU_SPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_SPI_CFG_CRITICAL_SECTION_ENABLE (0) +#define SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE config.driver.sau_spi.single_channel_enable.disabled +#define SAU_SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_SPI_TRANSFER_OPERATION_MODE (SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION) +#define SAU_SPI_CFG_DTC_SUPPORT_ENABLE (0) +#define SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE (0) +#define SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_SPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_uart_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_uart_cfg.h new file mode 100644 index 0000000000..81f1635ccc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sau_uart_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_UART_CFG_H_ +#define R_SAU_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SAU_UART_CFG_CRITICAL_SECTION_ENABLE (0) + #define SAU_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SAU_UART_CFG_DTC_SUPPORT_ENABLE (0) + #define SAU_UART_CFG_SINGLE_CHANNEL config.driver.sau_uart.single_channel.disabled + #define SAU_UART_CFG_FIXED_BAUDRATE_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_SAU_UART_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_i2c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_i2c_cfg.h new file mode 100644 index 0000000000..1f4bf5af8e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_i2c_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_I2C_CFG_H_ +#define R_SCI_I2C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_I2C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_I2C_CFG_DTC_ENABLE (0) +#define SCI_I2C_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_I2C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_lin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_lin_cfg.h new file mode 100644 index 0000000000..88134f91d3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_lin_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_LIN_CFG_H_ +#define R_SCI_LIN_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SCI_LIN_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SCI_LIN_CHECKSUM_SUPPORT_ENABLE (1) + #define SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE (0) + #define SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_SCI_LIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_smci_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_smci_cfg.h new file mode 100644 index 0000000000..39c3ec3d52 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_smci_cfg.h @@ -0,0 +1,15 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_SMCI_CFG_H_ +#define R_SCI_SMCI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define SCI_SMCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_SMCI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_spi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_spi_cfg.h new file mode 100644 index 0000000000..441e96d140 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_spi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_SPI_CFG_H_ +#define R_SCI_SPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_SPI_DTC_SUPPORT_ENABLE (1) +#define SCI_SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_SPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_uart_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_uart_cfg.h new file mode 100644 index 0000000000..e9664c9170 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sci_uart_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SCI_UART_CFG_FIFO_SUPPORT (1) + #define SCI_UART_CFG_DTC_SUPPORTED (0) + #define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) + #define SCI_UART_CFG_RS485_SUPPORT (0) + #define SCI_UART_CFG_IRDA_SUPPORT (0) + #ifdef __cplusplus + } + #endif +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sdadc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sdadc_cfg.h new file mode 100644 index 0000000000..b54b68020f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sdadc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SDADC_CFG_H_ +#define R_SDADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SDADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_SDADC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sdhi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sdhi_cfg.h new file mode 100644 index 0000000000..d825b389ef --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_sdhi_cfg.h @@ -0,0 +1,24 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SDHI_CFG_H_ +#define R_SDHI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SDHI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SDMMC_CFG_UNALIGNED_ACCESS_ENABLE (1) + #ifndef SDHI_CFG_SD_SUPPORT_ENABLE + #define SDHI_CFG_SD_SUPPORT_ENABLE ((1)) + #endif + #ifndef SDHI_CFG_EMMC_SUPPORT_ENABLE + #define SDHI_CFG_EMMC_SUPPORT_ENABLE ((0)) + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_SDHI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_spi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_spi_cfg.h new file mode 100644 index 0000000000..eedbdfc959 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_spi_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SPI_DMA_SUPPORT_ENABLE (1) + #define SPI_TRANSMIT_FROM_RXI_ISR (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_SPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ssi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ssi_cfg.h new file mode 100644 index 0000000000..a6ec1f79e0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ssi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SSI_CFG_H_ +#define R_SSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SSI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SSI_CFG_DTC_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_SSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tau_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tau_cfg.h new file mode 100644 index 0000000000..c92f1d8daa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tau_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TAU_CFG_H_ +#define R_TAU_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define TAU_CFG_INTERRUPT_SUPPORT_ENABLE (1) + #define TAU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define TAU_CFG_OUTPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_INPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_EXTRA_INPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_8BIT_MODE_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_TAU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tau_pwm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tau_pwm_cfg.h new file mode 100644 index 0000000000..bd9b7f09af --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tau_pwm_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TAU_PWM_CFG_H_ +#define R_TAU_PWM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define TAU_PWM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE (0) + #define TAU_PWM_CFG_PWM_MODE_ENABLE (1) + #define TAU_PWM_CFG_MULTI_SLAVE_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_TAU_PWM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tml_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tml_cfg.h new file mode 100644 index 0000000000..d05ca45c63 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_tml_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TML_CFG_H_ +#define R_TML_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define TML_CFG_CRITICAL_SECTION_ENABLE (0) +#define TML_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define TML_CFG_16_BIT_CAPTURE_MODE_ENABLE (0) +#define TML_CFG_SINGLE_CHANNEL_ENABLE (0) +#define TML_CFG_INTERRUPT_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_TML_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_uarta_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_uarta_cfg.h new file mode 100644 index 0000000000..b57d6dfeb3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_uarta_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_UARTA_CFG_H_ +#define R_UARTA_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define UARTA_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define UARTA_CFG_DTC_SUPPORT_ENABLE + #define UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE 1 + #ifdef __cplusplus + } + #endif +#endif /* R_UARTA_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ulpt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ulpt_cfg.h new file mode 100644 index 0000000000..b931fda89d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_ulpt_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ULPT_CFG_H_ +#define R_ULPT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ULPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ULPT_CFG_OUTPUT_SUPPORT_ENABLE (0) + #define ULPT_CFG_INPUT_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_ULPT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_usb_basic_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_usb_basic_cfg.h new file mode 100644 index 0000000000..c62ab39d43 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_usb_basic_cfg.h @@ -0,0 +1,138 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_USB_BASIC_CFG_H_ +#define R_USB_BASIC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #ifndef NULL + extern const uint16_t NULL[]; + #endif + + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #include "r_usb_hcdc_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #define USB_CFG_HCDC_ECM_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HHID_USE + #include "r_usb_hhid_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HMSC_USE + #include "r_usb_hmsc_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HVND_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HAUD_USE + #endif + #if ((RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED)) + #define USB_CFG_PCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PCDC2_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID2_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PVND_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HUVC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_DFU_USE + #endif + #if ((RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED)) + #define USB_CFG_OTG_USE + #endif + #if (defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HPRN_USE) || defined(USB_CFG_HMSC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HVND_USE) || defined(USB_CFG_HUVC_USE) || defined(USB_CFG_HAUD_USE)) + #define USB_CFG_HOST_MODE 1 + #else + #define USB_CFG_HOST_MODE 0 + #endif + + #if (defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE) || defined(USB_CFG_PMSC_USE) || defined(USB_CFG_PHID_USE) || defined(USB_CFG_PVND_USE) || defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE) || defined(USB_CFG_PAUD_USE)) + #define USB_CFG_PERI_MODE 2 + #else + #define USB_CFG_PERI_MODE 0 + #endif + + #define USB_CFG_MODE (USB_CFG_PERI_MODE | USB_CFG_HOST_MODE) + #define USB_CFG_MULTIPORT (USB_CFG_DISABLE) + #define USB_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define USB_CFG_CLKSEL (USB_CFG_24MHZ) + #define USB_CFG_BUSWAIT (USB_CFG_BUSWAIT_0) + #define USB_CFG_BC (USB_CFG_DISABLE) + #define USB_CFG_VBUS (USB_CFG_HIGH) + #define USB_CFG_DCP (USB_CFG_DISABLE) + #define USB_CFG_CLASS_REQUEST (USB_CFG_ENABLE) + #define USB_CFG_DBLB (USB_CFG_DBLBON) + #define USB_CFG_CNTMD (USB_CFG_CNTMDOFF) + #define USB_CFG_LDO_REGULATOR (USB_CFG_DISABLE) + #define USB_CFG_TYPEC_FEATURE (RA_NOT_DEFINED) + #define USB_CFG_DMA_DTC_DISABLED (USB_CFG_ENABLE) + #define USB_CFG_TPLCNT (1) + #define USB_CFG_TPL USB_NOVENDOR, USB_NOPRODUCT + #define USB_CFG_TPL_TABLE NULL + #define USB_CFG_COMPLIANCE (USB_CFG_DISABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_USB_BASIC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_vin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_vin_cfg.h new file mode 100644 index 0000000000..816207c8d4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_vin_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_VIN_CFG_H_ +#define R_VIN_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define VIN_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_VIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_wdt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_wdt_cfg.h new file mode 100644 index 0000000000..0d10d3f68a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/r_wdt_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_WDT_CFG_H_ +#define R_WDT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define WDT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define WDT_CFG_REGISTER_START_NMI_SUPPORTED ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_WDT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/uart_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/uart_device.c new file mode 100644 index 0000000000..2d766adfa9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/uart_device.c @@ -0,0 +1,12 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "PeripheralNames.h" +#include "hal_data.h" +#include "device.h" + +const uart_instance_t * const g_uart_instances[UART_COUNT] = { + &g_uart0, + &g_uart9, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/us_ticker_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/us_ticker_data.h new file mode 100644 index 0000000000..cc49b915df --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA6E2/us_ticker_data.h @@ -0,0 +1,27 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __US_TICKER_DATA_H +#define __US_TICKER_DATA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define US_TICKER_CLOCK_HZ (3125000UL) +#define US_TICKER_CLOCK_BITS (16) +#define US_TICKER_VAR g_timer_gpt1 +#define US_TICKER_INSTANCE R_GPT1 +#define US_TICKER_IRQ GPT1_CAPTURE_COMPARE_A_IRQn + +/* RA6E2 devices have 3.125MHz us_ticker */ +#define US_TICKER_PERIOD_NUM 8 +#define US_TICKER_PERIOD_DEN 25 + +#ifdef __cplusplus +} +#endif + +#endif // __US_TICKER_DATA_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/CMakeLists.txt new file mode 100644 index 0000000000..3d977709b8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/CMakeLists.txt @@ -0,0 +1,344 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# RA8E1 +add_library(mbed-ra8e1 INTERFACE) + +target_include_directories(mbed-ra8e1 + INTERFACE + ../ra/fsp/src/bsp/mcu/ra8e1 + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/inc/api + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/inc/instances + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/inc + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/inc + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src + ../ra/fsp/src/r_usb_basic/src/driver/inc + ../ra/fsp/src/r_usb_basic/src/hw/inc + . +) + +target_sources(mbed-ra8e1 + INTERFACE + gpio_irq_device.c + uart_device.c + can_device.c + ../ra/fsp/src/bsp/mcu/ra8e1/bsp_linker.c + ../ra/fsp/src/r_adc/r_adc.c + ../ra/fsp/src/r_agt/r_agt.c + ../ra/fsp/src/r_cac/r_cac.c + ../ra/fsp/src/r_canfd/r_canfd.c + ../ra/fsp/src/r_cgc/r_cgc.c + ../ra/fsp/src/r_crc/r_crc.c + ../ra/fsp/src/r_dac/r_dac.c + ../ra/fsp/src/r_dmac/r_dmac.c + ../ra/fsp/src/r_doc/r_doc.c + ../ra/fsp/src/r_dtc/r_dtc.c + ../ra/fsp/src/r_elc/r_elc.c + ../ra/fsp/src/r_flash_hp/r_flash_hp.c + ../ra/fsp/src/r_gpt/r_gpt.c + ../ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c + ../ra/fsp/src/r_icu/r_icu.c + ../ra/fsp/src/r_iic_master/r_iic_master.c + ../ra/fsp/src/r_iic_slave/r_iic_slave.c + ../ra/fsp/src/r_ioport/r_ioport.c + ../ra/fsp/src/r_iwdt/r_iwdt.c + ../ra/fsp/src/r_lpm/r_lpm.c + ../ra/fsp/src/r_lvd/r_lvd.c + ../ra/fsp/src/r_poeg/r_poeg.c + ../ra/fsp/src/r_rtc/r_rtc.c + ../ra/fsp/src/r_sci_i2c/r_sci_i2c.c + ../ra/fsp/src/r_sci_lin/r_sci_lin.c + ../ra/fsp/src/r_sci_smci/r_sci_smci.c + ../ra/fsp/src/r_sci_spi/r_sci_spi.c + ../ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c + ../ra/fsp/src/r_spi_b/r_spi_b.c + ../ra/fsp/src/r_wdt/r_wdt.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private_sub1.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private_sub2.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_aes.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_chacha.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_ecc.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_kdf.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_otf.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_pki.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_rsa.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_sha.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func008.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func016.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func017.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func027.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func028.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func030.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func031.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func040.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func043.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func044.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func048.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func049.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func052.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func053.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func054.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func055.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func057.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func059.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func061.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func062.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func063.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func065.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func068.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func070.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func071.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func073.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func074.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func075.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func076.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func077.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func078.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func079.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func081.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func082.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func083.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func086.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func087.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func088.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func089.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func090.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func091.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func092.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func100.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func101.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func102.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func103.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func113.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func202.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func214.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func215.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func216.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func220.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func302.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func303.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func304.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func305.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func310.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func311.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func312.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func313.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func314.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func315.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func316.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func317.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func318.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func319.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func320.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func321.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func322.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func323.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func324.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func401.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func402.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func403.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func404.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func405.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func406.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func407.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func408.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func420.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func421.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func422.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func423.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func424.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func501.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p00.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p07.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p08.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0b.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0c.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0d.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0e.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p11.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p12.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p13.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p15.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p16.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p17.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p18.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p19.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p1a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p20.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p21.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29t.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2b.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2d.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2e.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p31.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32t.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34t.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36t.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3b.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3c.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3d.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p40.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p4e.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p4f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p51f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p51i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p52f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p52i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p56.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p57.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5e.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5ff.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5fi.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p6f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73r.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73s.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75r.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75s.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p79.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7b.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7c.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7d.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7e.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p81.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p82.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83t.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85a.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85t.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p8f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p90.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe1.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe2.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe3.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe4.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5e.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5f.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5i.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5r.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5s.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5u.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe6.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe7.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peef.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peei.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peff.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefi.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefr.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefs.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefu.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf0.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf1.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf4.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf5.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf6.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf9.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_sub_func.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_drv_api.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_api.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn_drv.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_manifest.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_sb.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_hal.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.c + ../ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/public/r_rsip_ra.c +) + +target_link_libraries(mbed-ra8e1 INTERFACE mbed-renesas-ra) +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-ra8e1 ../ra/fsp/src/bsp/mcu/ra8e1/RA8E1.ld) +endif() + +add_subdirectory(TARGET_FPB_RA8E1 EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/CMakeLists.txt b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/CMakeLists.txt new file mode 100644 index 0000000000..296d2252a5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-fpb-ra8e1 INTERFACE) +target_include_directories(mbed-fpb-ra8e1 + INTERFACE + . +) +target_sources(mbed-fpb-ra8e1 + INTERFACE + board_init.c + common_data.c + hal_data.c + pin_data.c + hal_warmstart.c + vector_data.c + PeripheralPins.c +) +target_link_libraries(mbed-fpb-ra8e1 INTERFACE mbed-ra8e1) diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PeripheralNames.h new file mode 100644 index 0000000000..d9e8acf74f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PeripheralNames.h @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = 0, + UART_1, + UART_2, + UART_3, + UART_4, + UART_9 = 9 +} UARTName; + +typedef enum { + PWM_GPT0 = 0x00, + PWM_GPT1, + PWM_GPT2, + PWM_GPT3, + PWM_GPT4, + PWM_GPT5, + PWM_GPT10, + PWM_GPT11, + PWM_GPT12, + PWM_GPT13, + PWM_AGT0, + PWM_AGT1, +} PWMName; + +typedef enum { + PORT_0= BSP_IO_PORT_00, + PORT_1= BSP_IO_PORT_01, + PORT_2= BSP_IO_PORT_02, + PORT_3= BSP_IO_PORT_03, + PORT_4= BSP_IO_PORT_04, + PORT_5= BSP_IO_PORT_05, + PORT_6= BSP_IO_PORT_06, + PORT_7= BSP_IO_PORT_07, + PORT_8= BSP_IO_PORT_08, + PORT_9= BSP_IO_PORT_09, +} PortName; + +typedef enum { + ADC_0= 0, + ADC_1, +} ADCName; + +typedef enum { + DAC_0= 0, +} DACName; + +typedef enum { + IRQ_0= 0, + IRQ_1, + IRQ_2, + IRQ_3, + IRQ_4, + IRQ_5, + IRQ_6, + IRQ_7, + IRQ_8, + IRQ_9, + IRQ_10, + IRQ_11, + IRQ_12, + IRQ_13, + IRQ_14, + IRQ_15, +} IRQName; + +typedef enum { + SPI_0 = 0, + SPI_1, +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1, +} I2CName; + +typedef enum { + CAN_0 = 0, + CAN_1, +} CANName; + + +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) +#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX +#else +#define STDIO_UART_TX CONSOLE_TX +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) +#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX +#else +#define STDIO_UART_RX CONSOLE_RX +#endif +#define STDIO_UART UART_9 + +#define IRQ_CHANNELS_COUNT (16) +#define UART_COUNT (6) +#define CAN_COUNT (2) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PeripheralPins.c new file mode 100644 index 0000000000..8a735b87a6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PeripheralPins.c @@ -0,0 +1,294 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" +#include "r_adc_api.h" +#include "r_dac_api.h" +#include "r_ioport.h" + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {P0_0, ADC_1, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_0)}, + {P0_1, ADC_1, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_1)}, + {P0_2, ADC_1, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_2)}, + {P0_3, ADC_1, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_4)}, + {P0_4, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_0)}, + {P0_5, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_1)}, + {P0_6, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_2)}, + {P0_7, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_4)}, + {P0_8, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_8)}, + {P0_9, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_6)}, + {P0_10, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_5)}, + {P0_14, ADC_0, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_7)}, + {P0_15, ADC_1, RA_PIN_DATA_EXT(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0, ADC_CHANNEL_5)}, + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {P0_14, DAC_0, RA_PIN_DATA(RA_PIN_MODE_ANALOG, RA_PIN_PULL_NONE, 0)}, + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {P1_2, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_2, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_3, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P1_4, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_5, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P1_6, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P1_7, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P1_12, PWM_GPT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_13, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P1_14, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P1_15, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P2_2, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P2_3, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P2_4, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P2_5, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P2_5, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P2_8, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P2_9, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P2_10, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P2_11, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P2_12, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P2_13, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P3_0, PWM_GPT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P3_1, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P3_2, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P3_11, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P3_12, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P4_3, PWM_GPT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P4_4, PWM_GPT3, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P4_5, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P4_6, PWM_GPT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P4_7, PWM_GPT10, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P4_8, PWM_GPT10, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P4_10, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P4_11, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P4_14, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P4_15, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P5_11, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P5_12, PWM_GPT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P6_9, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P6_10, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P6_11, PWM_GPT4, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P6_13, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P6_14, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P7_0, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P7_1, PWM_GPT5, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P7_3, PWM_AGT1, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P7_4, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P7_12, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P7_12, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P7_13, PWM_GPT2, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P7_13, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P8_0, PWM_GPT11, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P8_0, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 0)}, + {P8_1, PWM_GPT11, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P8_1, PWM_AGT0, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_AGT, 1)}, + {P8_2, PWM_GPT12, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P8_3, PWM_GPT12, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {P8_4, PWM_GPT13, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 0)}, + {P8_8, PWM_GPT13, RA_PIN_DATA_EXT(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_GPT1, 1)}, + {NC, NC, 0} +}; + +//*** IRQ *** + +const PinMap PinMap_IRQ[] = { + {P1_5, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_0, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P8_6, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_1, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_4, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P1_0, IRQ_2, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_13, IRQ_2, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_8, IRQ_3, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_12, IRQ_3, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_0, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_11, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_2, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_10, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_1, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_9, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_8, IRQ_7, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_5, IRQ_8, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_15, IRQ_8, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P9_5, IRQ_8, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P3_4, IRQ_9, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_14, IRQ_9, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P7_9, IRQ_10, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P7_8, IRQ_11, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P8_0, IRQ_11, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P8_1, IRQ_12, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_15, IRQ_13, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_10, IRQ_14, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P5_12, IRQ_14, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P8_4, IRQ_14, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P5_11, IRQ_15, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P8_8, IRQ_15, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_6, IRQ_0, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_5, IRQ_1, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_3, IRQ_2, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P2_2, IRQ_3, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_2, IRQ_4, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_1, IRQ_5, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_0, IRQ_6, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_1, IRQ_7, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_2, IRQ_8, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_4, IRQ_9, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_5, IRQ_10, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_6, IRQ_11, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_8, IRQ_12, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P0_9, IRQ_13, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_3, IRQ_14, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {P4_4, IRQ_15, RA_PIN_DATA(RA_PIN_MODE_IRQ, RA_PIN_PULL_NONE, 0)}, + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_RX[] = { + {P1_1, UART_9, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P1_13, UART_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P2_6, UART_4, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P2_8, UART_9, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P2_12, UART_1, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P3_9, UART_3, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P4_1, UART_1, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P4_8, UART_3, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9)}, + {P4_14, UART_4, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P6_2, UART_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P6_10, UART_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P7_0, UART_2, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {P8_2, UART_2, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_TX[] = { + {P1_2, UART_9, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P1_12, UART_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P2_5, UART_4, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P2_9, UART_9, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P2_13, UART_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P3_10, UART_3, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P4_0, UART_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P4_6, UART_2, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P4_9, UART_3, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI1_3_5_7_9, RA_PIN_SPEED_MID)}, + {P4_15, UART_4, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P6_3, UART_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P6_9, UART_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {P8_1, UART_2, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_UP, IOPORT_PERIPHERAL_SCI0_2_4_6_8, RA_PIN_SPEED_MID)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {P1_15, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P2_2, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P6_11, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P7_1, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P1_1, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P4_11, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P3_13, SPI_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {P6_9, SPI_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {P7_0, SPI_0, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {P1_0, SPI_1, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {P4_10, SPI_1, RA_PIN_DATA(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {P2_3, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P6_10, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P7_2, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P1_2, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {P4_12, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P1_12, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_13, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_14, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P2_4, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P2_5, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P2_6, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P3_0, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P4_6, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P4_7, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P6_12, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P7_3, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P7_4, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P7_5, SPI_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_3, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_4, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_5, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P1_6, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P4_13, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P4_14, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P4_15, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {P7_8, SPI_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_SPI, RA_PIN_SPEED_MID)}, + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SCL[] = { + {P2_5, I2C_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_8, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_10, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P5_12, I2C_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SDA[] = { + {P2_6, I2C_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_7, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P4_9, I2C_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {P5_11, I2C_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_OD, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_IIC, RA_PIN_SPEED_MID_I2C)}, + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_RD[] = { + {P1_2, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P2_2, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P2_8, CAN_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P3_11, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P4_2, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P4_14, CAN_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P5_11, CAN_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P6_10, CAN_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P7_5, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P8_14, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {P1_3, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P2_3, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P2_9, CAN_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P3_12, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P4_1, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P4_15, CAN_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P5_12, CAN_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P6_9, CAN_1, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P7_4, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {P8_15, CAN_0, RA_PIN_DATA_SPEED(RA_PIN_MODE_PERIPHERAL_PP, RA_PIN_PULL_NONE, IOPORT_PERIPHERAL_CAN, RA_PIN_SPEED_HS_HIGH)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PinNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PinNames.h new file mode 100644 index 0000000000..e6040d804d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PinNames.h @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* MBED TARGET LIST: FPB_RA4E1 */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 4 + +typedef enum { + P0_0 = 0x0000, P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, + P1_0 = 0x0100, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, + P2_0 = 0x0200, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, + P3_0 = 0x0300, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, + P4_0 = 0x0400, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, + P5_0 = 0x0500, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, + P6_0 = 0x0600, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15, + P7_0 = 0x0700, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15, + P8_0 = 0x0800, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15, + P9_0 = 0x0900, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7, P9_8, P9_9, P9_10, P9_11, P9_12, P9_13, P9_14, P9_15, + + // mbed Pin Names +#define LED1 P4_4 +#define LED2 P4_8 +#define BUTTON0 P0_9 + + CONSOLE_TX = P1_2, + CONSOLE_RX = P1_1, + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Pin Names + ARDUINO_UNO_D0 = P3_9, + ARDUINO_UNO_D1 = P3_10, + ARDUINO_UNO_D2 = P3_0, + ARDUINO_UNO_D3 = P4_15, + ARDUINO_UNO_D4 = P9_5, + ARDUINO_UNO_D5 = P1_14, + ARDUINO_UNO_D6 = P1_13, + ARDUINO_UNO_D7 = P3_2, + ARDUINO_UNO_D8 = P3_3, + ARDUINO_UNO_D9 = P1_12, + ARDUINO_UNO_D10 = P2_4, + ARDUINO_UNO_D11 = P2_2, + ARDUINO_UNO_D12 = P3_13, + ARDUINO_UNO_D13 = P2_3, + ARDUINO_UNO_D14 = P5_11, + ARDUINO_UNO_D15 = P5_12, + + ARDUINO_UNO_A0 = P0_4, + ARDUINO_UNO_A1 = P0_3, + ARDUINO_UNO_A2 = P0_7, + ARDUINO_UNO_A3 = P0_1, + ARDUINO_UNO_A4 = P0_14, + ARDUINO_UNO_A5 = P0_15, +#endif + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown = 3, + PullNone = 2, + OpenDrain = 4, + PullDefault = PullNone +} PinMode; + +#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f) +#define PINNO(pin) ((pin)&0x0f) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PortNames.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PortNames.h new file mode 100644 index 0000000000..5fd463d578 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/PortNames.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3, + Port4 = 4, + Port5 = 5, + Port6 = 6, + Port7 = 7, + Port8 = 8, + Port9 = 9, +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board.h new file mode 100644 index 0000000000..c39df1855e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA8E1_FPB for the RA8E1-FPB board + * @brief BSP for the RA8E1-FPB Board + * + * The RA8E1_FPB is a development kit for the Renesas R7FA8E1AFDCFB microcontroller in a LQFP144 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_ethernet_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA8E1_FPB + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA8E1_FPB) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_ethernet_phy.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_ethernet_phy.h new file mode 100644 index 0000000000..5da11c6cc3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_ethernet_phy.h @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA8E1_FPB + * @defgroup BOARD_RA8E1_FPB_ETHERNET_PHY Board Ethernet Phy + * @brief Ethernet Phy information for this board. + * + * This is code specific to the RA8E1_FPB board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_ETHERNET_PHY_H +#define BSP_ETHERNET_PHY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (1) +#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_ICS1894 +#define BOARD_PHY_REF_CLK (1) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA8E1_FPB_ETHERNET_PHY) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_init.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_init.c new file mode 100644 index 0000000000..d0c8208b17 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_init.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA8E1_FPB + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA8E1_FPB) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA8E1_FPB) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_init.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_init.h new file mode 100644 index 0000000000..e57abc49d3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/board_init.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA8E1_FPB + * @brief Board specific code for the RA8E1-FPB Board + * + * This include file is specific to the RA8E1-FPB board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA8E1_FPB) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/bsp_clock_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/bsp_clock_cfg.h new file mode 100644 index 0000000000..3a8bfde083 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/bsp_clock_cfg.h @@ -0,0 +1,54 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* PLL Src: HOCO */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(72,0) /* PLL Mul x60-79|Mul x72|PLL Mul x72.00 */ +#define BSP_CFG_PLL_FREQUENCY_HZ (720000000) /* PLL 720000000Hz */ +#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */ +#define BSP_CFG_PLL1P_FREQUENCY_HZ (360000000) /* PLL1P 360000000Hz */ +#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL1Q Div /2 */ +#define BSP_CFG_PLL1Q_FREQUENCY_HZ (360000000) /* PLL1Q 360000000Hz */ +#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */ +#define BSP_CFG_PLL1R_FREQUENCY_HZ (360000000) /* PLL1R 360000000Hz */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL2 Mul x80-99|Mul x96|PLL2 Mul x96.00 */ +#define BSP_CFG_PLL2_FREQUENCY_HZ (0) /* PLL2 0Hz */ +#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL2P Div /2 */ +#define BSP_CFG_PLL2P_FREQUENCY_HZ (0) /* PLL2P 0Hz */ +#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL2Q Div /2 */ +#define BSP_CFG_PLL2Q_FREQUENCY_HZ (0) /* PLL2Q 0Hz */ +#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL2R Div /2 */ +#define BSP_CFG_PLL2R_FREQUENCY_HZ (0) /* PLL2R 0Hz */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* SCICLK Src: PLL1P */ +#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* SPICLK Src: PLL1P */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* CANFDCLK Src: PLL1Q */ +#define BSP_CFG_UCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* USBCLK Disabled */ +#define BSP_CFG_OCTACLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTACLK Disabled */ +#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_3) /* ICLK Div /3 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_6) /* PCLKA Div /6 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_6) /* PCLKB Div /6 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_6) /* PCLKC Div /6 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_3) /* PCLKD Div /3 */ +#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_3) /* PCLKE Div /3 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_3) /* BCLK Div /3 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_6) /* FCLK Div /6 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_3) /* SCICLK Div /3 */ +#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_3) /* SPICLK Div /3 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_6) /* CANFDCLK Div /6 */ +#define BSP_CFG_UCLK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* USBCLK Div /5 */ +#define BSP_CFG_OCTACLK_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTACLK Div /4 */ +#endif /* BSP_CLOCK_CFG_H_ */ \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/common_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/common_data.c new file mode 100644 index 0000000000..c5029d0401 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/common_data.c @@ -0,0 +1,600 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated common source file - do not edit */ +#include "common_data.h" +rsip_instance_ctrl_t g_rsip_ctrl; +const rsip_cfg_t g_rsip_cfg; +/* Instance structure to use this module. */ +const rsip_instance_t g_rsip = +{ + .p_ctrl = &g_rsip_ctrl, + .p_cfg = &g_rsip_cfg, + .p_api = &g_rsip_on_rsip +}; +icu_instance_ctrl_t g_external_irq15_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq15_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq15_cfg = +{ + .channel = 15, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq15_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ15) + .irq = VECTOR_NUMBER_ICU_IRQ15, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq15 = +{ + .p_ctrl = &g_external_irq15_ctrl, + .p_cfg = &g_external_irq15_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq14_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq14_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq14_cfg = +{ + .channel = 14, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq14_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ14) + .irq = VECTOR_NUMBER_ICU_IRQ14, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq14 = +{ + .p_ctrl = &g_external_irq14_ctrl, + .p_cfg = &g_external_irq14_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq12_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq12_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq12_cfg = +{ + .channel = 12, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq12_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ12) + .irq = VECTOR_NUMBER_ICU_IRQ12, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq12 = +{ + .p_ctrl = &g_external_irq12_ctrl, + .p_cfg = &g_external_irq12_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq11_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq11_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq11_cfg = +{ + .channel = 11, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq11_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ11) + .irq = VECTOR_NUMBER_ICU_IRQ11, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq11 = +{ + .p_ctrl = &g_external_irq11_ctrl, + .p_cfg = &g_external_irq11_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq10_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq10_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq10_cfg = +{ + .channel = 10, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq10_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ10) + .irq = VECTOR_NUMBER_ICU_IRQ10, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq10 = +{ + .p_ctrl = &g_external_irq10_ctrl, + .p_cfg = &g_external_irq10_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq13_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq13_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq13_cfg = +{ + .channel = 13, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq13_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ13) + .irq = VECTOR_NUMBER_ICU_IRQ13, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq13 = +{ + .p_ctrl = &g_external_irq13_ctrl, + .p_cfg = &g_external_irq13_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq9_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq9_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq9_cfg = +{ + .channel = 9, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq9_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ9) + .irq = VECTOR_NUMBER_ICU_IRQ9, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq9 = +{ + .p_ctrl = &g_external_irq9_ctrl, + .p_cfg = &g_external_irq9_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq8_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq8_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq8_cfg = +{ + .channel = 8, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq8_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ8) + .irq = VECTOR_NUMBER_ICU_IRQ8, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq8 = +{ + .p_ctrl = &g_external_irq8_ctrl, + .p_cfg = &g_external_irq8_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq7_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq7_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq7_cfg = +{ + .channel = 7, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq7_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ7) + .irq = VECTOR_NUMBER_ICU_IRQ7, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq7 = +{ + .p_ctrl = &g_external_irq7_ctrl, + .p_cfg = &g_external_irq7_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq6_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq6_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq6_cfg = +{ + .channel = 6, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq6_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ6) + .irq = VECTOR_NUMBER_ICU_IRQ6, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq6 = +{ + .p_ctrl = &g_external_irq6_ctrl, + .p_cfg = &g_external_irq6_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq5_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq5_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq5_cfg = +{ + .channel = 5, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq5_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ5) + .irq = VECTOR_NUMBER_ICU_IRQ5, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq5 = +{ + .p_ctrl = &g_external_irq5_ctrl, + .p_cfg = &g_external_irq5_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq4_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq4_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq4_cfg = +{ + .channel = 4, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq4_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ4) + .irq = VECTOR_NUMBER_ICU_IRQ4, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq4 = +{ + .p_ctrl = &g_external_irq4_ctrl, + .p_cfg = &g_external_irq4_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq3_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq3_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq3_cfg = +{ + .channel = 3, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq3_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ3) + .irq = VECTOR_NUMBER_ICU_IRQ3, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq3 = +{ + .p_ctrl = &g_external_irq3_ctrl, + .p_cfg = &g_external_irq3_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq2_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq2_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq2_cfg = +{ + .channel = 2, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq2_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ2) + .irq = VECTOR_NUMBER_ICU_IRQ2, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq2 = +{ + .p_ctrl = &g_external_irq2_ctrl, + .p_cfg = &g_external_irq2_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq1_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq1_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq1_cfg = +{ + .channel = 1, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq1_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ1) + .irq = VECTOR_NUMBER_ICU_IRQ1, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq1 = +{ + .p_ctrl = &g_external_irq1_ctrl, + .p_cfg = &g_external_irq1_cfg, + .p_api = &g_external_irq_on_icu +}; +icu_instance_ctrl_t g_external_irq0_ctrl; + +/** External IRQ extended configuration for ICU HAL driver */ +const icu_extended_cfg_t g_external_irq0_ext_cfg = +{ + .filter_src = EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV, +}; + +const external_irq_cfg_t g_external_irq0_cfg = +{ + .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_BOTH_EDGE, + .filter_enable = true, + .clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64, + .p_callback = external_irq_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = (void *)&g_external_irq0_ext_cfg, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, +#else + .irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ + .p_ctrl = &g_external_irq0_ctrl, + .p_cfg = &g_external_irq0_cfg, + .p_api = &g_external_irq_on_icu +}; +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/common_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/common_data.h new file mode 100644 index 0000000000..0d72b82d17 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/common_data.h @@ -0,0 +1,191 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_rsip.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* RSIP on RSIP Protected Instance. */ +extern const rsip_instance_t g_rsip; +extern rsip_instance_ctrl_t g_rsip_ctrl; +extern const rsip_cfg_t g_rsip_cfg; +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq15; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq15_ctrl; +extern const external_irq_cfg_t g_external_irq15_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq14; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq14_ctrl; +extern const external_irq_cfg_t g_external_irq14_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq12; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq12_ctrl; +extern const external_irq_cfg_t g_external_irq12_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq11; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq11_ctrl; +extern const external_irq_cfg_t g_external_irq11_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq10; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq10_ctrl; +extern const external_irq_cfg_t g_external_irq10_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq13; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq13_ctrl; +extern const external_irq_cfg_t g_external_irq13_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq9; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq9_ctrl; +extern const external_irq_cfg_t g_external_irq9_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq8; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq8_ctrl; +extern const external_irq_cfg_t g_external_irq8_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq7; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq7_ctrl; +extern const external_irq_cfg_t g_external_irq7_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq6; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq6_ctrl; +extern const external_irq_cfg_t g_external_irq6_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq5; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq5_ctrl; +extern const external_irq_cfg_t g_external_irq5_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq4; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq4_ctrl; +extern const external_irq_cfg_t g_external_irq4_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq3; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq3_ctrl; +extern const external_irq_cfg_t g_external_irq3_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq2; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq2_ctrl; +extern const external_irq_cfg_t g_external_irq2_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq1; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq1_ctrl; +extern const external_irq_cfg_t g_external_irq1_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef external_irq_callback +void external_irq_callback(external_irq_callback_args_t * p_args); +#endif +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_data.c new file mode 100644 index 0000000000..ab5883ddaa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_data.c @@ -0,0 +1,2867 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated HAL source file - do not edit */ +#include "hal_data.h" + +flash_hp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ + .data_flash_bgo = false, + .p_callback = flash_callback, + .p_context = NULL, +#if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, +#else + .irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_FCU_FIFERR) + .err_irq = VECTOR_NUMBER_FCU_FIFERR, +#else + .err_irq = FSP_INVALID_VECTOR, +#endif + .err_ipl = (7), + .ipl = (7), +}; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ + .p_ctrl = &g_flash0_ctrl, + .p_cfg = &g_flash0_cfg, + .p_api = &g_flash_on_flash_hp +}; + +/* Nominal and Data bit timing configuration */ + +can_bit_timing_cfg_t g_canfd1_bit_timing_cfg = +{ + /* Actual bitrate: 500000 Hz. Actual sample point: 75 %. */ + .baud_rate_prescaler = 1, + .time_segment_1 = 89, + .time_segment_2 = 30, + .synchronization_jump_width = 4 +}; + +#if BSP_FEATURE_CANFD_FD_SUPPORT +can_bit_timing_cfg_t g_canfd1_data_timing_cfg = +{ + /* Actual bitrate: 2000000 Hz. Actual sample point: 77 %. */ + .baud_rate_prescaler = 1, + .time_segment_1 = 22, + .time_segment_2 = 7, + .synchronization_jump_width = 1 +}; +#endif + + +extern const canfd_afl_entry_t p_canfd1_afl[CANFD_CFG_AFL_CH1_RULE_NUM]; + + +/* Buffer RAM used: 608 bytes */ +canfd_global_cfg_t g_canfd1_global_cfg = +{ + .global_interrupts = ( 0x3), + .global_config = ((R_CANFD_CFDGCFG_TPRI_Msk) | (0) | (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC ? R_CANFD_CFDGCFG_DCS_Msk : 0U) | (0) | + ((0) << R_CANFD_CFDGCFG_ITRCP_Pos)), + .rx_mb_config = (0 | ((7) << R_CANFD_CFDRMNB_RMPLS_Pos)), + .global_err_ipl = CANFD_CFG_GLOBAL_ERR_IPL, + .rx_fifo_ipl = CANFD_CFG_RX_FIFO_IPL, + .rx_fifo_config = + { + ((3U) << R_CANFD_CFDRFCC_RFIGCV_Pos) | ((2) << R_CANFD_CFDRFCC_RFDC_Pos) | ((7) << R_CANFD_CFDRFCC_RFPLS_Pos) | ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) | ((1)), + ((3U) << R_CANFD_CFDRFCC_RFIGCV_Pos) | ((3) << R_CANFD_CFDRFCC_RFDC_Pos) | ((0) << R_CANFD_CFDRFCC_RFPLS_Pos) | ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) | ((0)) + }, + .common_fifo_config = + { + CANFD_CFG_COMMONFIFO0 + } +}; + +canfd_extended_cfg_t g_canfd1_extended_cfg = +{ + .p_afl = p_canfd1_afl, + .txmb_txi_enable = ((1ULL << 0) | 0ULL), + .error_interrupts = (R_CANFD_CFDC_CTR_EWIE_Msk | R_CANFD_CFDC_CTR_EPIE_Msk | R_CANFD_CFDC_CTR_BOEIE_Msk | R_CANFD_CFDC_CTR_BORIE_Msk | R_CANFD_CFDC_CTR_OLIE_Msk | 0U), +#if BSP_FEATURE_CANFD_FD_SUPPORT + .p_data_timing = &g_canfd1_data_timing_cfg, +#else + .p_data_timing = NULL, +#endif + .delay_compensation = (1), + .p_global_cfg = &g_canfd1_global_cfg, +}; + +canfd_instance_ctrl_t g_canfd1_ctrl; +const can_cfg_t g_canfd1_cfg = +{ + .channel = 1, + .p_bit_timing = &g_canfd1_bit_timing_cfg, + .p_callback = can_callback, + .p_extend = &g_canfd1_extended_cfg, + .p_context = NULL, + .ipl = (12), +#if defined(VECTOR_NUMBER_CAN1_COMFRX) + .rx_irq = VECTOR_NUMBER_CAN1_COMFRX, +#else + .rx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN1_TX) + .tx_irq = VECTOR_NUMBER_CAN1_TX, +#else + .tx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN1_CHERR) + .error_irq = VECTOR_NUMBER_CAN1_CHERR, +#else + .error_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const can_instance_t g_canfd1 = +{ + .p_ctrl = &g_canfd1_ctrl, + .p_cfg = &g_canfd1_cfg, + .p_api = &g_canfd_on_canfd +}; +/* Nominal and Data bit timing configuration */ + +can_bit_timing_cfg_t g_canfd0_bit_timing_cfg = +{ + /* Actual bitrate: 500000 Hz. Actual sample point: 75 %. */ + .baud_rate_prescaler = 1, + .time_segment_1 = 89, + .time_segment_2 = 30, + .synchronization_jump_width = 4 +}; + +#if BSP_FEATURE_CANFD_FD_SUPPORT +can_bit_timing_cfg_t g_canfd0_data_timing_cfg = +{ + /* Actual bitrate: 2000000 Hz. Actual sample point: 77 %. */ + .baud_rate_prescaler = 1, + .time_segment_1 = 22, + .time_segment_2 = 7, + .synchronization_jump_width = 1 +}; +#endif + + +extern const canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH0_RULE_NUM]; + +/* Buffer RAM used: 608 bytes */ +canfd_global_cfg_t g_canfd0_global_cfg = +{ + .global_interrupts = ( 0x3), + .global_config = ((R_CANFD_CFDGCFG_TPRI_Msk) | (0) | (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC ? R_CANFD_CFDGCFG_DCS_Msk : 0U) | (0) | + ((0) << R_CANFD_CFDGCFG_ITRCP_Pos)), + .rx_mb_config = (0 | ((7) << R_CANFD_CFDRMNB_RMPLS_Pos)), + .global_err_ipl = CANFD_CFG_GLOBAL_ERR_IPL, + .rx_fifo_ipl = CANFD_CFG_RX_FIFO_IPL, + .rx_fifo_config = + { + ((3U) << R_CANFD_CFDRFCC_RFIGCV_Pos) | ((2) << R_CANFD_CFDRFCC_RFDC_Pos) | ((7) << R_CANFD_CFDRFCC_RFPLS_Pos) | ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) | ((1)), + ((3U) << R_CANFD_CFDRFCC_RFIGCV_Pos) | ((3) << R_CANFD_CFDRFCC_RFDC_Pos) | ((0) << R_CANFD_CFDRFCC_RFPLS_Pos) | ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) | ((0)) + }, + .common_fifo_config = + { + CANFD_CFG_COMMONFIFO0 + } +}; + +canfd_extended_cfg_t g_canfd0_extended_cfg = +{ + .p_afl = p_canfd0_afl, + .txmb_txi_enable = ((1ULL << 0) | 0ULL), + .error_interrupts = (R_CANFD_CFDC_CTR_EWIE_Msk | R_CANFD_CFDC_CTR_EPIE_Msk | R_CANFD_CFDC_CTR_BOEIE_Msk | R_CANFD_CFDC_CTR_BORIE_Msk | R_CANFD_CFDC_CTR_OLIE_Msk | 0U), +#if BSP_FEATURE_CANFD_FD_SUPPORT + .p_data_timing = &g_canfd0_data_timing_cfg, +#else + .p_data_timing = NULL, +#endif + .delay_compensation = (1), + .p_global_cfg = &g_canfd0_global_cfg, +}; + +canfd_instance_ctrl_t g_canfd0_ctrl; +const can_cfg_t g_canfd0_cfg = +{ + .channel = 0, + .p_bit_timing = &g_canfd0_bit_timing_cfg, + .p_callback = can_callback, + .p_extend = &g_canfd0_extended_cfg, + .p_context = NULL, + .ipl = (12), +#if defined(VECTOR_NUMBER_CAN0_COMFRX) + .rx_irq = VECTOR_NUMBER_CAN0_COMFRX, +#else + .rx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN0_TX) + .tx_irq = VECTOR_NUMBER_CAN0_TX, +#else + .tx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN0_CHERR) + .error_irq = VECTOR_NUMBER_CAN0_CHERR, +#else + .error_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const can_instance_t g_canfd0 = +{ + .p_ctrl = &g_canfd0_ctrl, + .p_cfg = &g_canfd0_cfg, + .p_api = &g_canfd_on_canfd +}; +iic_master_instance_ctrl_t g_i2c_master1_ctrl; +const iic_master_extended_cfg_t g_i2c_master1_extend = +{ + .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, + .timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED, + .smbus_operation = 0, + /* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15, .clock_settings.brh_value = 16, .clock_settings.cks_value = 4, .clock_settings.sddl_value = 0, .clock_settings.dlcs_value = 0, +}; +const i2c_master_cfg_t g_i2c_master1_cfg = +{ + .channel = 1, + .rate = I2C_MASTER_RATE_STANDARD, + .slave = 0x00, + .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .p_callback = i2c_callback, + .p_context = NULL, +#if defined(VECTOR_NUMBER_IIC1_RXI) + .rxi_irq = VECTOR_NUMBER_IIC1_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC1_TXI) + .txi_irq = VECTOR_NUMBER_IIC1_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC1_TEI) + .tei_irq = VECTOR_NUMBER_IIC1_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC1_ERI) + .eri_irq = VECTOR_NUMBER_IIC1_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .p_extend = &g_i2c_master1_extend, +}; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master1 = +{ + .p_ctrl = &g_i2c_master1_ctrl, + .p_cfg = &g_i2c_master1_cfg, + .p_api = &g_i2c_master_on_iic +}; + +dmac_instance_ctrl_t g_transfer1_ctrl; +transfer_info_t g_transfer1_info = +{ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .transfer_settings_word_b.irq = TRANSFER_IRQ_END, + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; +const dmac_extended_cfg_t g_transfer1_extend = +{ + .offset = 1, + .src_buffer_size = 1, +#if defined(VECTOR_NUMBER_DMAC1_INT) + .irq = VECTOR_NUMBER_DMAC1_INT, +#else + .irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .channel = 1, + .p_callback = g_spi1_tx_transfer_callback, + .p_context = NULL, + .activation_source = ELC_EVENT_SPI1_TXI, +}; +const transfer_cfg_t g_transfer1_cfg = +{ + .p_info = &g_transfer1_info, + .p_extend = &g_transfer1_extend, +}; +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ + .p_ctrl = &g_transfer1_ctrl, + .p_cfg = &g_transfer1_cfg, + .p_api = &g_transfer_on_dmac +}; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (1) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_b_tx_dmac_callback(spi_b_instance_ctrl_t const * const p_ctrl); + +void g_spi1_tx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_b_tx_dmac_callback(&g_spi1_ctrl); +} +#endif + +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_b_rx_dmac_callback(spi_b_instance_ctrl_t const * const p_ctrl); + +void g_spi1_rx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_b_rx_dmac_callback(&g_spi1_ctrl); +} +#endif +#undef RA_NOT_DEFINED + +spi_b_instance_ctrl_t g_spi1_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_b_extended_cfg_t g_spi1_ext_cfg = +{ + .spi_clksyn = SPI_B_SSL_MODE_SPI, + .spi_comm = SPI_B_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_B_SSLP_LOW, + .ssl_select = SPI_B_SSL_SELECT_SSL0, + .mosi_idle = SPI_B_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_B_PARITY_MODE_DISABLE, + .byte_swap = SPI_B_BYTE_SWAP_DISABLE, + .clock_source = SPI_B_CLOCK_SOURCE_SCISPICLK, + .spck_div = { + /* Actual calculated bitrate: 60000000. */ .spbr = 0, .brdv = 0 + }, + .spck_delay = SPI_B_DELAY_COUNT_1, + .ssl_negation_delay = SPI_B_DELAY_COUNT_1, + .next_access_delay = SPI_B_DELAY_COUNT_1, + .burst_interframe_delay = SPI_B_BURST_TRANSFER_WITHOUT_DELAY + + }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi1_cfg = +{ + .channel = 1, + +#if defined(VECTOR_NUMBER_SPI1_RXI) + .rxi_irq = VECTOR_NUMBER_SPI1_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI1_TXI) + .txi_irq = VECTOR_NUMBER_SPI1_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI1_TEI) + .tei_irq = VECTOR_NUMBER_SPI1_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI1_ERI) + .eri_irq = VECTOR_NUMBER_SPI1_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + + .rxi_ipl = (10), + .txi_ipl = (BSP_IRQ_DISABLED), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi1_P_TRANSFER_TX, + .p_transfer_rx = g_spi1_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi1_ext_cfg, +}; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi1 = +{ + .p_ctrl = &g_spi1_ctrl, + .p_cfg = &g_spi1_cfg, + .p_api = &g_spi_on_spi_b +}; +sci_b_uart_instance_ctrl_t g_uart9_ctrl; + + sci_b_baud_setting_t g_uart9_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 64, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_b_uart_extended_cfg_t g_uart9_cfg_extend = + { + .clock = SCI_B_UART_CLOCK_INT, + .rx_edge_start = SCI_B_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_B_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_B_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart9_baud_setting, + .flow_control = SCI_B_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_B_UART_RS485_DISABLE, + .polarity = SCI_B_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, + } + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart9_cfg = + { + .channel = 9, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart9_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI9_RXI) + .rxi_irq = VECTOR_NUMBER_SCI9_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_TXI) + .txi_irq = VECTOR_NUMBER_SCI9_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_TEI) + .tei_irq = VECTOR_NUMBER_SCI9_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI9_ERI) + .eri_irq = VECTOR_NUMBER_SCI9_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart9 = +{ + .p_ctrl = &g_uart9_ctrl, + .p_cfg = &g_uart9_cfg, + .p_api = &g_uart_on_sci_b +}; +sci_b_uart_instance_ctrl_t g_uart4_ctrl; + + sci_b_baud_setting_t g_uart4_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 64, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_b_uart_extended_cfg_t g_uart4_cfg_extend = + { + .clock = SCI_B_UART_CLOCK_INT, + .rx_edge_start = SCI_B_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_B_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_B_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart4_baud_setting, + .flow_control = SCI_B_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_B_UART_RS485_DISABLE, + .polarity = SCI_B_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, + } + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart4_cfg = + { + .channel = 4, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart4_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI4_RXI) + .rxi_irq = VECTOR_NUMBER_SCI4_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI4_TXI) + .txi_irq = VECTOR_NUMBER_SCI4_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI4_TEI) + .tei_irq = VECTOR_NUMBER_SCI4_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI4_ERI) + .eri_irq = VECTOR_NUMBER_SCI4_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart4 = +{ + .p_ctrl = &g_uart4_ctrl, + .p_cfg = &g_uart4_cfg, + .p_api = &g_uart_on_sci_b +}; +sci_b_uart_instance_ctrl_t g_uart3_ctrl; + + sci_b_baud_setting_t g_uart3_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 64, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_b_uart_extended_cfg_t g_uart3_cfg_extend = + { + .clock = SCI_B_UART_CLOCK_INT, + .rx_edge_start = SCI_B_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_B_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_B_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart3_baud_setting, + .flow_control = SCI_B_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_B_UART_RS485_DISABLE, + .polarity = SCI_B_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, + } + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart3_cfg = + { + .channel = 3, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart3_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI3_RXI) + .rxi_irq = VECTOR_NUMBER_SCI3_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI3_TXI) + .txi_irq = VECTOR_NUMBER_SCI3_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI3_TEI) + .tei_irq = VECTOR_NUMBER_SCI3_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI3_ERI) + .eri_irq = VECTOR_NUMBER_SCI3_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart3 = +{ + .p_ctrl = &g_uart3_ctrl, + .p_cfg = &g_uart3_cfg, + .p_api = &g_uart_on_sci_b +}; +sci_b_uart_instance_ctrl_t g_uart2_ctrl; + + sci_b_baud_setting_t g_uart2_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 64, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_b_uart_extended_cfg_t g_uart2_cfg_extend = + { + .clock = SCI_B_UART_CLOCK_INT, + .rx_edge_start = SCI_B_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_B_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_B_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart2_baud_setting, + .flow_control = SCI_B_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_B_UART_RS485_DISABLE, + .polarity = SCI_B_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, + } + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart2_cfg = + { + .channel = 2, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart2_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI2_RXI) + .rxi_irq = VECTOR_NUMBER_SCI2_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI2_TXI) + .txi_irq = VECTOR_NUMBER_SCI2_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI2_TEI) + .tei_irq = VECTOR_NUMBER_SCI2_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI2_ERI) + .eri_irq = VECTOR_NUMBER_SCI2_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart2 = +{ + .p_ctrl = &g_uart2_ctrl, + .p_cfg = &g_uart2_cfg, + .p_api = &g_uart_on_sci_b +}; +sci_b_uart_instance_ctrl_t g_uart1_ctrl; + + sci_b_baud_setting_t g_uart1_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 64, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_b_uart_extended_cfg_t g_uart1_cfg_extend = + { + .clock = SCI_B_UART_CLOCK_INT, + .rx_edge_start = SCI_B_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_B_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_B_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart1_baud_setting, + .flow_control = SCI_B_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_B_UART_RS485_DISABLE, + .polarity = SCI_B_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, + } + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart1_cfg = + { + .channel = 1, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart1_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI1_RXI) + .rxi_irq = VECTOR_NUMBER_SCI1_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI1_TXI) + .txi_irq = VECTOR_NUMBER_SCI1_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI1_TEI) + .tei_irq = VECTOR_NUMBER_SCI1_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI1_ERI) + .eri_irq = VECTOR_NUMBER_SCI1_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart1 = +{ + .p_ctrl = &g_uart1_ctrl, + .p_cfg = &g_uart1_cfg, + .p_api = &g_uart_on_sci_b +}; +adc_instance_ctrl_t g_adc1_ctrl; +const adc_extended_cfg_t g_adc1_cfg_extend = +{ + .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger = ADC_START_SOURCE_DISABLED, + .trigger_group_b = ADC_START_SOURCE_DISABLED, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, + .enable_adbuf = 0, +#if defined(VECTOR_NUMBER_ADC1_WINDOW_A) + .window_a_irq = VECTOR_NUMBER_ADC1_WINDOW_A, +#else + .window_a_irq = FSP_INVALID_VECTOR, +#endif + .window_a_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC1_WINDOW_B) + .window_b_irq = VECTOR_NUMBER_ADC1_WINDOW_B, +#else + .window_b_irq = FSP_INVALID_VECTOR, +#endif + .window_b_ipl = (BSP_IRQ_DISABLED), +}; +const adc_cfg_t g_adc1_cfg = +{ + .unit = 1, + .mode = ADC_MODE_SINGLE_SCAN, + .resolution = ADC_RESOLUTION_12_BIT, + .alignment = (adc_alignment_t) ADC_ALIGNMENT_RIGHT, + .trigger = (adc_trigger_t)0xF, // Not used + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_adc1_cfg_extend, +#if defined(VECTOR_NUMBER_ADC1_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END, +#else + .scan_end_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC1_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B, +#else + .scan_end_b_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), +}; +#if ((0) | (0)) +const adc_window_cfg_t g_adc1_window_cfg = +{ + .compare_mask = 0, + .compare_mode_mask = 0, + .compare_cfg = (adc_compare_cfg_t) ((0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR)), + .compare_ref_low = 0, + .compare_ref_high = 0, + .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0), + .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE), + .compare_b_ref_low = 0, + .compare_b_ref_high = 0, +}; +#endif +const adc_channel_cfg_t g_adc1_channel_cfg = +{ + .scan_mask = ADC_MASK_CHANNEL_0 | ADC_MASK_CHANNEL_1 | ADC_MASK_CHANNEL_2 | ADC_MASK_CHANNEL_4 | ADC_MASK_CHANNEL_5 | 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, +#if ((0) | (0)) + .p_window_cfg = (adc_window_cfg_t *) &g_adc1_window_cfg, +#else + .p_window_cfg = NULL, +#endif +}; +/* Instance structure to use this module. */ +const adc_instance_t g_adc1 = +{ + .p_ctrl = &g_adc1_ctrl, + .p_cfg = &g_adc1_cfg, + .p_channel_cfg = &g_adc1_channel_cfg, + .p_api = &g_adc_on_adc +}; +gpt_instance_ctrl_t g_timer_gpt0_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt0_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt0_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT0_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT0_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT0_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT0_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT0_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt0_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt0_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_4, + .channel = 0, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt0_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt0 = +{ + .p_ctrl = &g_timer_gpt0_ctrl, + .p_cfg = &g_timer_gpt0_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt13_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt13_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT13_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT13_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt13_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT13_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT13_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT13_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT13_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT13_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT13_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT13_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT13_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT13_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT13_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT13_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT13_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt13_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt13_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 13, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt13_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT13_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT13_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt13 = +{ + .p_ctrl = &g_timer_gpt13_ctrl, + .p_cfg = &g_timer_gpt13_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt12_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt12_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT12_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT12_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt12_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT12_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT12_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT12_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT12_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT12_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT12_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT12_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT12_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT12_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT12_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT12_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT12_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt12_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt12_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 12, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt12_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT12_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT12_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt12 = +{ + .p_ctrl = &g_timer_gpt12_ctrl, + .p_cfg = &g_timer_gpt12_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt11_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt11_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT11_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT11_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt11_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT11_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT11_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT11_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT11_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT11_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT11_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT11_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT11_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT11_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT11_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT11_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT11_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt11_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt11_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 11, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt11_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT11_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT11_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt11 = +{ + .p_ctrl = &g_timer_gpt11_ctrl, + .p_cfg = &g_timer_gpt11_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt10_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt10_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT10_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT10_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt10_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT10_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT10_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT10_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT10_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT10_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT10_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT10_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT10_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT10_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT10_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT10_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT10_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt10_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt10_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_64, + .channel = 10, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt10_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT10_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT10_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt10 = +{ + .p_ctrl = &g_timer_gpt10_ctrl, + .p_cfg = &g_timer_gpt10_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt3_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt3_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT3_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT3_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt3_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT3_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT3_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT3_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT3_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT3_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT3_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT3_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT3_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt3_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt3_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_4, + .channel = 3, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt3_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT3_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT3_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt3 = +{ + .p_ctrl = &g_timer_gpt3_ctrl, + .p_cfg = &g_timer_gpt3_cfg, + .p_api = &g_timer_on_gpt +}; +sci_b_uart_instance_ctrl_t g_uart0_ctrl; + + sci_b_baud_setting_t g_uart0_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 64, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_b_uart_extended_cfg_t g_uart0_cfg_extend = + { + .clock = SCI_B_UART_CLOCK_INT, + .rx_edge_start = SCI_B_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_B_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_B_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, + .flow_control = SCI_B_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_B_UART_RS485_DISABLE, + .polarity = SCI_B_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, + } + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart0_cfg = + { + .channel = 0, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = uart_callback, + .p_context = NULL, + .p_extend = &g_uart0_cfg_extend, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ + .p_ctrl = &g_uart0_ctrl, + .p_cfg = &g_uart0_cfg, + .p_api = &g_uart_on_sci_b +}; + +dmac_instance_ctrl_t g_transfer0_ctrl; +transfer_info_t g_transfer0_info = +{ + .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .transfer_settings_word_b.irq = TRANSFER_IRQ_END, + .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, + .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; +const dmac_extended_cfg_t g_transfer0_extend = +{ + .offset = 1, + .src_buffer_size = 1, +#if defined(VECTOR_NUMBER_DMAC0_INT) + .irq = VECTOR_NUMBER_DMAC0_INT, +#else + .irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .channel = 0, + .p_callback = g_spi0_tx_transfer_callback, + .p_context = NULL, + .activation_source = ELC_EVENT_SPI0_TXI, +}; +const transfer_cfg_t g_transfer0_cfg = +{ + .p_info = &g_transfer0_info, + .p_extend = &g_transfer0_extend, +}; +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ + .p_ctrl = &g_transfer0_ctrl, + .p_cfg = &g_transfer0_cfg, + .p_api = &g_transfer_on_dmac +}; +#define RA_NOT_DEFINED (UINT32_MAX) +#if (RA_NOT_DEFINED) != (1) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_b_tx_dmac_callback(spi_b_instance_ctrl_t const * const p_ctrl); + +void g_spi0_tx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_b_tx_dmac_callback(&g_spi0_ctrl); +} +#endif + +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + +/* If the transfer module is DMAC, define a DMAC transfer callback. */ +#include "r_dmac.h" +extern void spi_b_rx_dmac_callback(spi_b_instance_ctrl_t const * const p_ctrl); + +void g_spi0_rx_transfer_callback (dmac_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + spi_b_rx_dmac_callback(&g_spi0_ctrl); +} +#endif +#undef RA_NOT_DEFINED + +spi_b_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_b_extended_cfg_t g_spi0_ext_cfg = +{ + .spi_clksyn = SPI_B_SSL_MODE_SPI, + .spi_comm = SPI_B_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_B_SSLP_LOW, + .ssl_select = SPI_B_SSL_SELECT_SSL0, + .mosi_idle = SPI_B_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_B_PARITY_MODE_DISABLE, + .byte_swap = SPI_B_BYTE_SWAP_DISABLE, + .clock_source = SPI_B_CLOCK_SOURCE_SCISPICLK, + .spck_div = { + /* Actual calculated bitrate: 60000000. */ .spbr = 0, .brdv = 0 + }, + .spck_delay = SPI_B_DELAY_COUNT_1, + .ssl_negation_delay = SPI_B_DELAY_COUNT_1, + .next_access_delay = SPI_B_DELAY_COUNT_1, + .burst_interframe_delay = SPI_B_BURST_TRANSFER_WITHOUT_DELAY + + }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ + .channel = 0, + +#if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + + .rxi_ipl = (10), + .txi_ipl = (BSP_IRQ_DISABLED), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, +}; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ + .p_ctrl = &g_spi0_ctrl, + .p_cfg = &g_spi0_cfg, + .p_api = &g_spi_on_spi_b +}; +agt_instance_ctrl_t g_timer_agt1_ctrl; +const agt_extended_cfg_t g_timer_agt1_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_16, +}; +const timer_cfg_t g_timer_agt1_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 1, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt1_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT1_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT1_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt1 = +{ + .p_ctrl = &g_timer_agt1_ctrl, + .p_cfg = &g_timer_agt1_cfg, + .p_api = &g_timer_on_agt +}; +agt_instance_ctrl_t g_timer_agt0_ctrl; +const agt_extended_cfg_t g_timer_agt0_extend = +{ + .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoab_settings_b.agtoa = AGT_PIN_CFG_START_LEVEL_LOW, + .agtoab_settings_b.agtob = AGT_PIN_CFG_START_LEVEL_LOW, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, + .counter_bit_width = AGT_COUNTER_BIT_WIDTH_16, +}; +const timer_cfg_t g_timer_agt0_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 0, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_agt0_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_agt0 = +{ + .p_ctrl = &g_timer_agt0_ctrl, + .p_cfg = &g_timer_agt0_cfg, + .p_api = &g_timer_on_agt +}; +gpt_instance_ctrl_t g_timer_gpt5_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt5_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT5_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt5_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT5_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT5_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT5_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT5_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT5_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT5_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt5_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt5_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_4, + .channel = 5, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt5_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT5_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT5_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt5 = +{ + .p_ctrl = &g_timer_gpt5_ctrl, + .p_cfg = &g_timer_gpt5_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt4_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt4_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT4_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt4_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT4_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT4_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT4_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT4_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT4_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT4_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt4_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt4_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_4, + .channel = 4, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt4_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT4_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT4_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt4 = +{ + .p_ctrl = &g_timer_gpt4_ctrl, + .p_cfg = &g_timer_gpt4_cfg, + .p_api = &g_timer_on_gpt +}; +gpt_instance_ctrl_t g_timer_gpt2_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt2_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt2_extend = +{ + .gtioca = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = true, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (BSP_IRQ_DISABLED), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT2_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT2_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT2_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT2_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT2_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt2_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) true, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) true, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt2_cfg = +{ + .mode = TIMER_MODE_PWM, + /* Actual period: 0.0005461333333333333 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x10000, .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_4, + .channel = 2, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt2_extend, + .cycle_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt2 = +{ + .p_ctrl = &g_timer_gpt2_ctrl, + .p_cfg = &g_timer_gpt2_cfg, + .p_api = &g_timer_on_gpt +}; +iic_master_instance_ctrl_t g_i2c_master0_ctrl; +const iic_master_extended_cfg_t g_i2c_master0_extend = +{ + .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, + .timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED, + .smbus_operation = 0, + /* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15, .clock_settings.brh_value = 16, .clock_settings.cks_value = 4, .clock_settings.sddl_value = 0, .clock_settings.dlcs_value = 0, +}; +const i2c_master_cfg_t g_i2c_master0_cfg = +{ + .channel = 0, + .rate = I2C_MASTER_RATE_STANDARD, + .slave = 0x00, + .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, +#else + .p_transfer_tx = &RA_NOT_DEFINED, +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, +#else + .p_transfer_rx = &RA_NOT_DEFINED, +#endif +#undef RA_NOT_DEFINED + .p_callback = NULL, + .p_context = NULL, +#if defined(VECTOR_NUMBER_IIC0_RXI) + .rxi_irq = VECTOR_NUMBER_IIC0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_TXI) + .txi_irq = VECTOR_NUMBER_IIC0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_TEI) + .tei_irq = VECTOR_NUMBER_IIC0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_IIC0_ERI) + .eri_irq = VECTOR_NUMBER_IIC0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + .ipl = (12), + .p_extend = &g_i2c_master0_extend, +}; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master0 = +{ + .p_ctrl = &g_i2c_master0_ctrl, + .p_cfg = &g_i2c_master0_cfg, + .p_api = &g_i2c_master_on_iic +}; +wdt_instance_ctrl_t g_wdt0_ctrl; + +const wdt_cfg_t g_wdt0_cfg = +{ + .timeout = WDT_TIMEOUT_16384, + .clock_division = WDT_CLOCK_DIVISION_8192, + .window_start = WDT_WINDOW_START_100, + .window_end = WDT_WINDOW_END_0, + .reset_control = WDT_RESET_CONTROL_RESET, + .stop_control = WDT_STOP_CONTROL_ENABLE, + .p_callback = NULL, +}; + +/* Instance structure to use this module. */ +const wdt_instance_t g_wdt0 = +{ + .p_ctrl = &g_wdt0_ctrl, + .p_cfg = &g_wdt0_cfg, + .p_api = &g_wdt_on_wdt +}; +#if BSP_TZ_NONSECURE_BUILD + #if defined(BSP_CFG_CLOCKS_SECURE) && BSP_CFG_CLOCKS_SECURE + #error "The LPM module requires CGC registers to be non-secure when it is used in a TrustZone Non-secure project." + #endif +#endif + +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ + .low_power_mode = LPM_MODE_SLEEP, + .standby_wake_sources = (lpm_standby_wake_source_t) 0, +#if BSP_FEATURE_ICU_HAS_WUPEN2 + .standby_wake_sources_2 = (lpm_standby_wake_source_2_t) 0, +#endif +#if BSP_FEATURE_LPM_HAS_SNOOZE + .snooze_cancel_sources = RA_NOT_DEFINED, + .snooze_request_source = (lpm_snooze_request_t) RA_NOT_DEFINED, +#if BSP_FEATURE_LPM_SNZEDCR_MASK > 0 + .snooze_end_sources = (lpm_snooze_end_t) 0, +#endif + .dtc_state_in_snooze = RA_NOT_DEFINED, +#endif +#if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = 0, +#endif +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t) 0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t) 0, +#if BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE + .deep_standby_soft_start_mode = LPM_DEEP_STANDBY_SOFT_START_MODE_0, +#endif +#endif +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint16_t) ( 0), + .ram_retention_cfg.tcm_retention = false, +#endif +#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, +#endif +#if BSP_FEATURE_LPM_HAS_LDO_SKEEP + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, +#endif +#if BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT + .lpm_flash_mode_select = false, +#endif +#if BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE + .lpm_hoco_startup_speed = false, +#endif +#if BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT + .lpm_standby_sosc = false, +#endif + .p_extend = NULL, +}; + +const lpm_instance_t g_lpm0 = +{ + .p_api = &g_lpm_on_lpm, + .p_ctrl = &g_lpm0_ctrl, + .p_cfg = &g_lpm0_cfg +}; +gpt_instance_ctrl_t g_timer_gpt1_ctrl; +#if 0 +const gpt_extended_pwm_cfg_t g_timer_gpt1_pwm_extend = +{ + .trough_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW) + .trough_irq = VECTOR_NUMBER_GPT1_COUNTER_UNDERFLOW, +#else + .trough_irq = FSP_INVALID_VECTOR, +#endif + .poeg_link = GPT_POEG_LINK_POEG0, + .output_disable = (gpt_output_disable_t) ( GPT_OUTPUT_DISABLE_NONE), + .adc_trigger = (gpt_adc_trigger_t) ( GPT_ADC_TRIGGER_NONE), + .dead_time_count_up = 0, + .dead_time_count_down = 0, + .adc_a_compare_match = 0, + .adc_b_compare_match = 0, + .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, + .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, + .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, + .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, + .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, +}; +#endif +const gpt_extended_cfg_t g_timer_gpt1_extend = +{ + .gtioca = { .output_enabled = false, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .gtiocb = { .output_enabled = false, + .stop_level = GPT_PIN_LEVEL_LOW + }, + .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), + .capture_a_ipl = (12), + .capture_b_ipl = (BSP_IRQ_DISABLED), + .compare_match_c_ipl = (BSP_IRQ_DISABLED), + .compare_match_d_ipl = (BSP_IRQ_DISABLED), + .compare_match_e_ipl = (BSP_IRQ_DISABLED), + .compare_match_f_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A) + .capture_a_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A, +#else + .capture_a_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B) + .capture_b_irq = VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_B, +#else + .capture_b_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_C) + .compare_match_c_irq = VECTOR_NUMBER_GPT1_COMPARE_C, +#else + .compare_match_c_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_D) + .compare_match_d_irq = VECTOR_NUMBER_GPT1_COMPARE_D, +#else + .compare_match_d_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_E) + .compare_match_e_irq = VECTOR_NUMBER_GPT1_COMPARE_E, +#else + .compare_match_e_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_GPT1_COMPARE_F) + .compare_match_f_irq = VECTOR_NUMBER_GPT1_COMPARE_F, +#else + .compare_match_f_irq = FSP_INVALID_VECTOR, +#endif + .compare_match_value = { (uint32_t)0x0, /* CMP_A */(uint32_t)0x0, /* CMP_B */(uint32_t)0x0, /* CMP_C */(uint32_t)0x0, /* CMP_D */(uint32_t)0x0, /* CMP_E */(uint32_t)0x0, /* CMP_F */ }, .compare_match_status = ((0U << 5U) | (0U << 4U) | (0U << 3U) | (0U << 2U) | (0U << 1U) | 0U), + .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, + .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, +#if 0 + .p_pwm_cfg = &g_timer_gpt1_pwm_extend, +#else + .p_pwm_cfg = NULL, +#endif +#if 0 + .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.oahld = 0U, + .gtior_setting.gtior_b.oae = (uint32_t) false, + .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), + .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), + .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, + .gtior_setting.gtior_b.obhld = 0U, + .gtior_setting.gtior_b.obe = (uint32_t) false, + .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, + .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), + .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), +#else + .gtior_setting.gtior = 0U, +#endif + + .gtioca_polarity = GPT_GTIOC_POLARITY_NORMAL, + .gtiocb_polarity = GPT_GTIOC_POLARITY_NORMAL, +}; + +const timer_cfg_t g_timer_gpt1_cfg = +{ + .mode = TIMER_MODE_PERIODIC, + /* Actual period: 35.791394133333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)TIMER_SOURCE_DIV_8, + .channel = 1, + .p_callback = usticker_compare_match_callback, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_timer_gpt1_extend, + .cycle_end_ipl = (10), +#if defined(VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW) + .cycle_end_irq = VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW, +#else + .cycle_end_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer_gpt1 = +{ + .p_ctrl = &g_timer_gpt1_ctrl, + .p_cfg = &g_timer_gpt1_cfg, + .p_api = &g_timer_on_gpt +}; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ + .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, +}; +const rtc_cfg_t g_rtc0_cfg = +{ + .clock_source = MBED_CONF_TARGET_RTC_CLOCK_SOURCE, + .freq_compare_value = 255, + .p_err_cfg = &g_rtc0_err_cfg, + .p_callback = NULL, + .p_context = NULL, + .p_extend = NULL, + .alarm_ipl = (BSP_IRQ_DISABLED), + .periodic_ipl = (BSP_IRQ_DISABLED), + .carry_ipl = (12), +#if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, +#else + .alarm_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, +#else + .periodic_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, +#else + .carry_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ + .p_ctrl = &g_rtc0_ctrl, + .p_cfg = &g_rtc0_cfg, + .p_api = &g_rtc_on_rtc +}; +dac_instance_ctrl_t g_dac0_ctrl; +const dac_extended_cfg_t g_dac0_ext_cfg = +{ + .enable_charge_pump = 0, + .data_format = DAC_DATA_FORMAT_FLUSH_RIGHT, + .output_amplifier_enabled = 0, + .internal_output_enabled = false, + .ref_volt_sel = (dac_ref_volt_sel_t) (0) +}; +const dac_cfg_t g_dac0_cfg = +{ + .channel = 0, + .ad_da_synchronized = false, + .p_extend = &g_dac0_ext_cfg +}; +/* Instance structure to use this module. */ +const dac_instance_t g_dac0 = +{ + .p_ctrl = &g_dac0_ctrl, + .p_cfg = &g_dac0_cfg, + .p_api = &g_dac_on_dac +}; +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ + .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger = ADC_START_SOURCE_DISABLED, + .trigger_group_b = ADC_START_SOURCE_DISABLED, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, + .enable_adbuf = 0, +#if defined(VECTOR_NUMBER_ADC0_WINDOW_A) + .window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A, +#else + .window_a_irq = FSP_INVALID_VECTOR, +#endif + .window_a_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC0_WINDOW_B) + .window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B, +#else + .window_b_irq = FSP_INVALID_VECTOR, +#endif + .window_b_ipl = (BSP_IRQ_DISABLED), +}; +const adc_cfg_t g_adc0_cfg = +{ + .unit = 0, + .mode = ADC_MODE_SINGLE_SCAN, + .resolution = ADC_RESOLUTION_12_BIT, + .alignment = (adc_alignment_t) ADC_ALIGNMENT_RIGHT, + .trigger = (adc_trigger_t)0xF, // Not used + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = (void *) &NULL, +#endif + .p_extend = &g_adc0_cfg_extend, +#if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, +#else + .scan_end_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_ipl = (BSP_IRQ_DISABLED), +#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, +#else + .scan_end_b_irq = FSP_INVALID_VECTOR, +#endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), +}; +#if ((0) | (0)) +const adc_window_cfg_t g_adc0_window_cfg = +{ + .compare_mask = 0, + .compare_mode_mask = 0, + .compare_cfg = (adc_compare_cfg_t) ((0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR)), + .compare_ref_low = 0, + .compare_ref_high = 0, + .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0), + .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE), + .compare_b_ref_low = 0, + .compare_b_ref_high = 0, +}; +#endif +const adc_channel_cfg_t g_adc0_channel_cfg = +{ + .scan_mask = ADC_MASK_CHANNEL_0 | ADC_MASK_CHANNEL_1 | ADC_MASK_CHANNEL_2 | ADC_MASK_CHANNEL_4 | ADC_MASK_CHANNEL_5 | ADC_MASK_CHANNEL_6 | ADC_MASK_CHANNEL_7 | ADC_MASK_CHANNEL_8 | 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, +#if ((0) | (0)) + .p_window_cfg = (adc_window_cfg_t *) &g_adc0_window_cfg, +#else + .p_window_cfg = NULL, +#endif +}; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ + .p_ctrl = &g_adc0_ctrl, + .p_cfg = &g_adc0_cfg, + .p_channel_cfg = &g_adc0_channel_cfg, + .p_api = &g_adc_on_adc +}; +void g_hal_init(void) { +g_common_init(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_data.h new file mode 100644 index 0000000000..134289afc5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_data.h @@ -0,0 +1,406 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_flash_hp.h" +#include "r_flash_api.h" +#include "r_canfd.h" +#include "r_can_api.h" +#include "r_dmac.h" +#include "r_transfer_api.h" +#include "r_sci_b_uart.h" + #include "r_uart_api.h" +#include "r_adc.h" +#include "r_adc_api.h" +#include "r_gpt.h" +#include "r_timer_api.h" +#include "r_spi_b.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_iic_slave.h" +#include "r_i2c_slave_api.h" +#include "r_iic_master.h" +#include "r_i2c_master_api.h" +#include "r_wdt.h" +#include "r_wdt_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_dac.h" +#include "r_dac_api.h" +FSP_HEADER +/* Flash on Flash HP Instance */ +extern const flash_instance_t g_flash0; + +/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_hp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef flash_callback +void flash_callback(flash_callback_args_t * p_args); +#endif +/** CANFD on CANFD Instance. */ +extern const can_instance_t g_canfd1; +/** Access the CANFD instance using these structures when calling API functions directly (::p_api is not used). */ +extern canfd_instance_ctrl_t g_canfd1_ctrl; +extern const can_cfg_t g_canfd1_cfg; +extern const canfd_extended_cfg_t g_canfd1_cfg_extend; + +#ifndef can_callback +void can_callback(can_callback_args_t * p_args); +#endif + +/* Global configuration (referenced by all instances) */ +extern canfd_global_cfg_t g_canfd_global_cfg; +/** CANFD on CANFD Instance. */ +extern const can_instance_t g_canfd0; +/** Access the CANFD instance using these structures when calling API functions directly (::p_api is not used). */ +extern canfd_instance_ctrl_t g_canfd0_ctrl; +extern const can_cfg_t g_canfd0_cfg; +extern const canfd_extended_cfg_t g_canfd0_cfg_extend; + +#ifndef can_callback +void can_callback(can_callback_args_t * p_args); +#endif + +/* Global configuration (referenced by all instances) */ +extern canfd_global_cfg_t g_canfd_global_cfg; +/* Transfer on DMAC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DMAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dmac_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; + +#ifndef g_spi1_tx_transfer_callback +void g_spi1_tx_transfer_callback(transfer_callback_args_t * p_args); +#endif +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi1; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_b_instance_ctrl_t g_spi1_ctrl; +extern const spi_cfg_t g_spi1_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t * p_args); +#endif + + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi1_P_TRANSFER_TX (NULL) +#else + #define g_spi1_P_TRANSFER_TX (&g_transfer1) +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + #define g_spi1_P_TRANSFER_RX (NULL) +#else + #define g_spi1_P_TRANSFER_RX (&RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart9; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_b_uart_instance_ctrl_t g_uart9_ctrl; + extern const uart_cfg_t g_uart9_cfg; + extern const sci_b_uart_extended_cfg_t g_uart9_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart4; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_b_uart_instance_ctrl_t g_uart4_ctrl; + extern const uart_cfg_t g_uart4_cfg; + extern const sci_b_uart_extended_cfg_t g_uart4_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart3; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_b_uart_instance_ctrl_t g_uart3_ctrl; + extern const uart_cfg_t g_uart3_cfg; + extern const sci_b_uart_extended_cfg_t g_uart3_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart2; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_b_uart_instance_ctrl_t g_uart2_ctrl; + extern const uart_cfg_t g_uart2_cfg; + extern const sci_b_uart_extended_cfg_t g_uart2_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart1; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_b_uart_instance_ctrl_t g_uart1_ctrl; + extern const uart_cfg_t g_uart1_cfg; + extern const sci_b_uart_extended_cfg_t g_uart1_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc1; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc1_ctrl; +extern const adc_cfg_t g_adc1_cfg; +extern const adc_channel_cfg_t g_adc1_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t * p_args); +#endif + +#ifndef NULL +#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 5 +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt0; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt0_ctrl; +extern const timer_cfg_t g_timer_gpt0_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt13; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt13_ctrl; +extern const timer_cfg_t g_timer_gpt13_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt12; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt12_ctrl; +extern const timer_cfg_t g_timer_gpt12_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt11; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt11_ctrl; +extern const timer_cfg_t g_timer_gpt11_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt10; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt10_ctrl; +extern const timer_cfg_t g_timer_gpt10_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt3; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt3_ctrl; +extern const timer_cfg_t g_timer_gpt3_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart0; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_b_uart_instance_ctrl_t g_uart0_ctrl; + extern const uart_cfg_t g_uart0_cfg; + extern const sci_b_uart_extended_cfg_t g_uart0_cfg_extend; + + #ifndef uart_callback + void uart_callback(uart_callback_args_t * p_args); + #endif +/* Transfer on DMAC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DMAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dmac_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; + +#ifndef g_spi0_tx_transfer_callback +void g_spi0_tx_transfer_callback(transfer_callback_args_t * p_args); +#endif +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_b_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t * p_args); +#endif + + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else + #define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == RA_NOT_DEFINED) + #define g_spi0_P_TRANSFER_RX (NULL) +#else + #define g_spi0_P_TRANSFER_RX (&RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt1; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt1_ctrl; +extern const timer_cfg_t g_timer_agt1_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer_agt0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer_agt0_ctrl; +extern const timer_cfg_t g_timer_agt0_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt5; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt5_ctrl; +extern const timer_cfg_t g_timer_gpt5_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt4; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt4_ctrl; +extern const timer_cfg_t g_timer_gpt4_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt2; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt2_ctrl; +extern const timer_cfg_t g_timer_gpt2_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t * p_args); +#endif +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master0; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_master_instance_ctrl_t g_i2c_master0_ctrl; +extern const i2c_master_cfg_t g_i2c_master0_cfg; + +#ifndef i2c_callback +void i2c_callback(i2c_master_callback_args_t * p_args); +#endif +/** WDT on WDT Instance. */ +extern const wdt_instance_t g_wdt0; + +/** Access the WDT instance using these structures when calling API functions directly (::p_api is not used). */ +extern wdt_instance_ctrl_t g_wdt0_ctrl; +extern const wdt_cfg_t g_wdt0_cfg; + +#ifndef NULL +void NULL(wdt_callback_args_t * p_args); +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer_gpt1; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer_gpt1_ctrl; +extern const timer_cfg_t g_timer_gpt1_cfg; + +#ifndef usticker_compare_match_callback +void usticker_compare_match_callback(timer_callback_args_t * p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t * p_args); +#endif +/** DAC on DAC Instance. */ +extern const dac_instance_t g_dac0; + +/** Access the DAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dac_instance_ctrl_t g_dac0_ctrl; +extern const dac_cfg_t g_dac0_cfg; +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t * p_args); +#endif + +#ifndef NULL +#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 8 +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_warmstart.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_warmstart.c new file mode 100644 index 0000000000..2e799ebefe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/hal_warmstart.c @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); + +FSP_CPP_FOOTER + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { +#if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ +#endif + } + +#if BSP_CFG_OSPI_B_STARTUP_ENABLED && defined(BSP_CFG_OSPI_B_STARTUP_FN) + if (BSP_WARM_START_POST_CLOCK == event) + { + /* Setup OSPI_B SiP flash and initialize it. */ + R_BSP_OspiBInit(BSP_CFG_OSPI_B_STARTUP_FN, true); + } +#endif + + if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME); + +#if BSP_CFG_SDRAM_ENABLED + + /* Setup SDRAM and initialize it. Must configure pins first. */ + R_BSP_SdramInit(true); +#endif + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/pin_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/pin_data.c new file mode 100644 index 0000000000..18dc77dfc3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/pin_data.c @@ -0,0 +1,12 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = 0, + .p_pin_cfg_data = NULL, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/vector_data.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/vector_data.c new file mode 100644 index 0000000000..4fa568897f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/vector_data.c @@ -0,0 +1,155 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated vector source file - do not edit */ + #include "bsp_api.h" + /* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ + #if VECTOR_DATA_IRQ_COUNT > 0 + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_NUM_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = + { + [0] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [1] = gpt_counter_overflow_isr, /* GPT1 COUNTER OVERFLOW (Overflow) */ + [2] = gpt_capture_compare_a_isr, /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + [3] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [4] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */ + [5] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */ + [6] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */ + [7] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */ + [8] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [9] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [10] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [11] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [12] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [13] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [14] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ + [15] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ + [16] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ + [17] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ + [18] = spi_b_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [19] = spi_b_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [20] = spi_b_eri_isr, /* SPI0 ERI (Error) */ + [21] = dmac_int_isr, /* DMAC0 INT (DMAC0 transfer end) */ + [22] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */ + [23] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ + [24] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ + [25] = r_icu_isr, /* ICU IRQ14 (External pin interrupt 14) */ + [26] = r_icu_isr, /* ICU IRQ15 (External pin interrupt 15) */ + [27] = sci_b_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [28] = sci_b_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ + [29] = sci_b_uart_tei_isr, /* SCI0 TEI (Transmit end) */ + [30] = sci_b_uart_eri_isr, /* SCI0 ERI (Receive error) */ + [31] = sci_b_uart_rxi_isr, /* SCI1 RXI (Receive data full) */ + [32] = sci_b_uart_txi_isr, /* SCI1 TXI (Transmit data empty) */ + [33] = sci_b_uart_tei_isr, /* SCI1 TEI (Transmit end) */ + [34] = sci_b_uart_eri_isr, /* SCI1 ERI (Receive error) */ + [35] = sci_b_uart_rxi_isr, /* SCI2 RXI (Receive data full) */ + [36] = sci_b_uart_txi_isr, /* SCI2 TXI (Transmit data empty) */ + [37] = sci_b_uart_tei_isr, /* SCI2 TEI (Transmit end) */ + [38] = sci_b_uart_eri_isr, /* SCI2 ERI (Receive error) */ + [39] = sci_b_uart_rxi_isr, /* SCI3 RXI (Receive data full) */ + [40] = sci_b_uart_txi_isr, /* SCI3 TXI (Transmit data empty) */ + [41] = sci_b_uart_tei_isr, /* SCI3 TEI (Transmit end) */ + [42] = sci_b_uart_eri_isr, /* SCI3 ERI (Receive error) */ + [43] = sci_b_uart_rxi_isr, /* SCI4 RXI (Receive data full) */ + [44] = sci_b_uart_txi_isr, /* SCI4 TXI (Transmit data empty) */ + [45] = sci_b_uart_tei_isr, /* SCI4 TEI (Transmit end) */ + [46] = sci_b_uart_eri_isr, /* SCI4 ERI (Receive error) */ + [47] = sci_b_uart_rxi_isr, /* SCI9 RXI (Receive data full) */ + [48] = sci_b_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ + [49] = sci_b_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [50] = sci_b_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [51] = spi_b_rxi_isr, /* SPI1 RXI (Receive buffer full) */ + [52] = spi_b_tei_isr, /* SPI1 TEI (Transmission complete event) */ + [53] = spi_b_eri_isr, /* SPI1 ERI (Error) */ + [54] = dmac_int_isr, /* DMAC1 INT (DMAC1 transfer end) */ + [55] = iic_master_rxi_isr, /* IIC1 RXI (Receive data full) */ + [56] = iic_master_txi_isr, /* IIC1 TXI (Transmit data empty) */ + [57] = iic_master_tei_isr, /* IIC1 TEI (Transmit end) */ + [58] = iic_master_eri_isr, /* IIC1 ERI (Transfer error) */ + [59] = canfd_error_isr, /* CAN0 CHERR (Channel error) */ + [60] = canfd_channel_tx_isr, /* CAN0 TX (Transmit interrupt) */ + [61] = canfd_common_fifo_rx_isr, /* CAN0 COMFRX (Common FIFO receive interrupt) */ + [62] = canfd_error_isr, /* CAN GLERR (Global error) */ + [63] = canfd_rx_fifo_isr, /* CAN RXF (Global receive FIFO interrupt) */ + [64] = canfd_error_isr, /* CAN1 CHERR (Channel error) */ + [65] = canfd_channel_tx_isr, /* CAN1 TX (Transmit interrupt) */ + [66] = canfd_common_fifo_rx_isr, /* CAN1 COMFRX (Common FIFO receive interrupt) */ + [67] = fcu_frdyi_isr, /* FCU FRDYI (Flash ready interrupt) */ + [68] = fcu_fiferr_isr, /* FCU FIFERR (Flash access error interrupt) */ + }; + #if BSP_FEATURE_ICU_HAS_IELSR + const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_NUM_ENTRIES] = + { + [0] = BSP_PRV_VECT_ENUM(EVENT_RTC_CARRY,GROUP0), /* RTC CARRY (Carry interrupt) */ + [1] = BSP_PRV_VECT_ENUM(EVENT_GPT1_COUNTER_OVERFLOW,GROUP1), /* GPT1 COUNTER OVERFLOW (Overflow) */ + [2] = BSP_PRV_VECT_ENUM(EVENT_GPT1_CAPTURE_COMPARE_A,GROUP2), /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + [3] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ0,GROUP3), /* ICU IRQ0 (External pin interrupt 0) */ + [4] = BSP_PRV_VECT_ENUM(EVENT_IIC0_RXI,GROUP4), /* IIC0 RXI (Receive data full) */ + [5] = BSP_PRV_VECT_ENUM(EVENT_IIC0_TXI,GROUP5), /* IIC0 TXI (Transmit data empty) */ + [6] = BSP_PRV_VECT_ENUM(EVENT_IIC0_TEI,GROUP6), /* IIC0 TEI (Transmit end) */ + [7] = BSP_PRV_VECT_ENUM(EVENT_IIC0_ERI,GROUP7), /* IIC0 ERI (Transfer error) */ + [8] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ1,GROUP0), /* ICU IRQ1 (External pin interrupt 1) */ + [9] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ2,GROUP1), /* ICU IRQ2 (External pin interrupt 2) */ + [10] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ3,GROUP2), /* ICU IRQ3 (External pin interrupt 3) */ + [11] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ4,GROUP3), /* ICU IRQ4 (External pin interrupt 4) */ + [12] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ5,GROUP4), /* ICU IRQ5 (External pin interrupt 5) */ + [13] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ6,GROUP5), /* ICU IRQ6 (External pin interrupt 6) */ + [14] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ7,GROUP6), /* ICU IRQ7 (External pin interrupt 7) */ + [15] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ8,GROUP7), /* ICU IRQ8 (External pin interrupt 8) */ + [16] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ9,GROUP0), /* ICU IRQ9 (External pin interrupt 9) */ + [17] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ13,GROUP1), /* ICU IRQ13 (External pin interrupt 13) */ + [18] = BSP_PRV_VECT_ENUM(EVENT_SPI0_RXI,GROUP2), /* SPI0 RXI (Receive buffer full) */ + [19] = BSP_PRV_VECT_ENUM(EVENT_SPI0_TEI,GROUP3), /* SPI0 TEI (Transmission complete event) */ + [20] = BSP_PRV_VECT_ENUM(EVENT_SPI0_ERI,GROUP4), /* SPI0 ERI (Error) */ + [21] = BSP_PRV_VECT_ENUM(EVENT_DMAC0_INT,GROUP5), /* DMAC0 INT (DMAC0 transfer end) */ + [22] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ10,GROUP6), /* ICU IRQ10 (External pin interrupt 10) */ + [23] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ11,GROUP7), /* ICU IRQ11 (External pin interrupt 11) */ + [24] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ12,GROUP0), /* ICU IRQ12 (External pin interrupt 12) */ + [25] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ14,GROUP1), /* ICU IRQ14 (External pin interrupt 14) */ + [26] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ15,GROUP2), /* ICU IRQ15 (External pin interrupt 15) */ + [27] = BSP_PRV_VECT_ENUM(EVENT_SCI0_RXI,GROUP3), /* SCI0 RXI (Receive data full) */ + [28] = BSP_PRV_VECT_ENUM(EVENT_SCI0_TXI,GROUP4), /* SCI0 TXI (Transmit data empty) */ + [29] = BSP_PRV_VECT_ENUM(EVENT_SCI0_TEI,GROUP5), /* SCI0 TEI (Transmit end) */ + [30] = BSP_PRV_VECT_ENUM(EVENT_SCI0_ERI,GROUP6), /* SCI0 ERI (Receive error) */ + [31] = BSP_PRV_VECT_ENUM(EVENT_SCI1_RXI,GROUP7), /* SCI1 RXI (Receive data full) */ + [32] = BSP_PRV_VECT_ENUM(EVENT_SCI1_TXI,FIXED), /* SCI1 TXI (Transmit data empty) */ + [33] = BSP_PRV_VECT_ENUM(EVENT_SCI1_TEI,FIXED), /* SCI1 TEI (Transmit end) */ + [34] = BSP_PRV_VECT_ENUM(EVENT_SCI1_ERI,FIXED), /* SCI1 ERI (Receive error) */ + [35] = BSP_PRV_VECT_ENUM(EVENT_SCI2_RXI,FIXED), /* SCI2 RXI (Receive data full) */ + [36] = BSP_PRV_VECT_ENUM(EVENT_SCI2_TXI,FIXED), /* SCI2 TXI (Transmit data empty) */ + [37] = BSP_PRV_VECT_ENUM(EVENT_SCI2_TEI,FIXED), /* SCI2 TEI (Transmit end) */ + [38] = BSP_PRV_VECT_ENUM(EVENT_SCI2_ERI,FIXED), /* SCI2 ERI (Receive error) */ + [39] = BSP_PRV_VECT_ENUM(EVENT_SCI3_RXI,FIXED), /* SCI3 RXI (Receive data full) */ + [40] = BSP_PRV_VECT_ENUM(EVENT_SCI3_TXI,FIXED), /* SCI3 TXI (Transmit data empty) */ + [41] = BSP_PRV_VECT_ENUM(EVENT_SCI3_TEI,FIXED), /* SCI3 TEI (Transmit end) */ + [42] = BSP_PRV_VECT_ENUM(EVENT_SCI3_ERI,FIXED), /* SCI3 ERI (Receive error) */ + [43] = BSP_PRV_VECT_ENUM(EVENT_SCI4_RXI,FIXED), /* SCI4 RXI (Receive data full) */ + [44] = BSP_PRV_VECT_ENUM(EVENT_SCI4_TXI,FIXED), /* SCI4 TXI (Transmit data empty) */ + [45] = BSP_PRV_VECT_ENUM(EVENT_SCI4_TEI,FIXED), /* SCI4 TEI (Transmit end) */ + [46] = BSP_PRV_VECT_ENUM(EVENT_SCI4_ERI,FIXED), /* SCI4 ERI (Receive error) */ + [47] = BSP_PRV_VECT_ENUM(EVENT_SCI9_RXI,FIXED), /* SCI9 RXI (Receive data full) */ + [48] = BSP_PRV_VECT_ENUM(EVENT_SCI9_TXI,FIXED), /* SCI9 TXI (Transmit data empty) */ + [49] = BSP_PRV_VECT_ENUM(EVENT_SCI9_TEI,FIXED), /* SCI9 TEI (Transmit end) */ + [50] = BSP_PRV_VECT_ENUM(EVENT_SCI9_ERI,FIXED), /* SCI9 ERI (Receive error) */ + [51] = BSP_PRV_VECT_ENUM(EVENT_SPI1_RXI,FIXED), /* SPI1 RXI (Receive buffer full) */ + [52] = BSP_PRV_VECT_ENUM(EVENT_SPI1_TEI,FIXED), /* SPI1 TEI (Transmission complete event) */ + [53] = BSP_PRV_VECT_ENUM(EVENT_SPI1_ERI,FIXED), /* SPI1 ERI (Error) */ + [54] = BSP_PRV_VECT_ENUM(EVENT_DMAC1_INT,FIXED), /* DMAC1 INT (DMAC1 transfer end) */ + [55] = BSP_PRV_VECT_ENUM(EVENT_IIC1_RXI,FIXED), /* IIC1 RXI (Receive data full) */ + [56] = BSP_PRV_VECT_ENUM(EVENT_IIC1_TXI,FIXED), /* IIC1 TXI (Transmit data empty) */ + [57] = BSP_PRV_VECT_ENUM(EVENT_IIC1_TEI,FIXED), /* IIC1 TEI (Transmit end) */ + [58] = BSP_PRV_VECT_ENUM(EVENT_IIC1_ERI,FIXED), /* IIC1 ERI (Transfer error) */ + [59] = BSP_PRV_VECT_ENUM(EVENT_CAN0_CHERR,FIXED), /* CAN0 CHERR (Channel error) */ + [60] = BSP_PRV_VECT_ENUM(EVENT_CAN0_TX,FIXED), /* CAN0 TX (Transmit interrupt) */ + [61] = BSP_PRV_VECT_ENUM(EVENT_CAN0_COMFRX,FIXED), /* CAN0 COMFRX (Common FIFO receive interrupt) */ + [62] = BSP_PRV_VECT_ENUM(EVENT_CAN_GLERR,FIXED), /* CAN GLERR (Global error) */ + [63] = BSP_PRV_VECT_ENUM(EVENT_CAN_RXF,FIXED), /* CAN RXF (Global receive FIFO interrupt) */ + [64] = BSP_PRV_VECT_ENUM(EVENT_CAN1_CHERR,FIXED), /* CAN1 CHERR (Channel error) */ + [65] = BSP_PRV_VECT_ENUM(EVENT_CAN1_TX,FIXED), /* CAN1 TX (Transmit interrupt) */ + [66] = BSP_PRV_VECT_ENUM(EVENT_CAN1_COMFRX,FIXED), /* CAN1 COMFRX (Common FIFO receive interrupt) */ + [67] = BSP_PRV_VECT_ENUM(EVENT_FCU_FRDYI,FIXED), /* FCU FRDYI (Flash ready interrupt) */ + [68] = BSP_PRV_VECT_ENUM(EVENT_FCU_FIFERR,FIXED), /* FCU FIFERR (Flash access error interrupt) */ + }; + #endif + #endif \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/vector_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/vector_data.h new file mode 100644 index 0000000000..d3bb43acfc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/TARGET_FPB_RA8E1/vector_data.h @@ -0,0 +1,184 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated vector header file - do not edit */ + #ifndef VECTOR_DATA_H + #define VECTOR_DATA_H + #ifdef __cplusplus + extern "C" { + #endif + /* Number of interrupts allocated */ + #ifndef VECTOR_DATA_IRQ_COUNT + #define VECTOR_DATA_IRQ_COUNT (69) + #endif + /* ISR prototypes */ + void rtc_carry_isr(void); + void gpt_counter_overflow_isr(void); + void gpt_capture_compare_a_isr(void); + void r_icu_isr(void); + void iic_master_rxi_isr(void); + void iic_master_txi_isr(void); + void iic_master_tei_isr(void); + void iic_master_eri_isr(void); + void spi_b_rxi_isr(void); + void spi_b_tei_isr(void); + void spi_b_eri_isr(void); + void dmac_int_isr(void); + void sci_b_uart_rxi_isr(void); + void sci_b_uart_txi_isr(void); + void sci_b_uart_tei_isr(void); + void sci_b_uart_eri_isr(void); + void canfd_error_isr(void); + void canfd_channel_tx_isr(void); + void canfd_common_fifo_rx_isr(void); + void canfd_rx_fifo_isr(void); + void fcu_frdyi_isr(void); + void fcu_fiferr_isr(void); + + /* Vector table allocations */ + #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type) 0) /* RTC CARRY (Carry interrupt) */ + #define RTC_CARRY_IRQn ((IRQn_Type) 0) /* RTC CARRY (Carry interrupt) */ + #define VECTOR_NUMBER_GPT1_COUNTER_OVERFLOW ((IRQn_Type) 1) /* GPT1 COUNTER OVERFLOW (Overflow) */ + #define GPT1_COUNTER_OVERFLOW_IRQn ((IRQn_Type) 1) /* GPT1 COUNTER OVERFLOW (Overflow) */ + #define VECTOR_NUMBER_GPT1_CAPTURE_COMPARE_A ((IRQn_Type) 2) /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + #define GPT1_CAPTURE_COMPARE_A_IRQn ((IRQn_Type) 2) /* GPT1 CAPTURE COMPARE A (Capture/Compare match A) */ + #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 3) /* ICU IRQ0 (External pin interrupt 0) */ + #define ICU_IRQ0_IRQn ((IRQn_Type) 3) /* ICU IRQ0 (External pin interrupt 0) */ + #define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type) 4) /* IIC0 RXI (Receive data full) */ + #define IIC0_RXI_IRQn ((IRQn_Type) 4) /* IIC0 RXI (Receive data full) */ + #define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type) 5) /* IIC0 TXI (Transmit data empty) */ + #define IIC0_TXI_IRQn ((IRQn_Type) 5) /* IIC0 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type) 6) /* IIC0 TEI (Transmit end) */ + #define IIC0_TEI_IRQn ((IRQn_Type) 6) /* IIC0 TEI (Transmit end) */ + #define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type) 7) /* IIC0 ERI (Transfer error) */ + #define IIC0_ERI_IRQn ((IRQn_Type) 7) /* IIC0 ERI (Transfer error) */ + #define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type) 8) /* ICU IRQ1 (External pin interrupt 1) */ + #define ICU_IRQ1_IRQn ((IRQn_Type) 8) /* ICU IRQ1 (External pin interrupt 1) */ + #define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type) 9) /* ICU IRQ2 (External pin interrupt 2) */ + #define ICU_IRQ2_IRQn ((IRQn_Type) 9) /* ICU IRQ2 (External pin interrupt 2) */ + #define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type) 10) /* ICU IRQ3 (External pin interrupt 3) */ + #define ICU_IRQ3_IRQn ((IRQn_Type) 10) /* ICU IRQ3 (External pin interrupt 3) */ + #define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type) 11) /* ICU IRQ4 (External pin interrupt 4) */ + #define ICU_IRQ4_IRQn ((IRQn_Type) 11) /* ICU IRQ4 (External pin interrupt 4) */ + #define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type) 12) /* ICU IRQ5 (External pin interrupt 5) */ + #define ICU_IRQ5_IRQn ((IRQn_Type) 12) /* ICU IRQ5 (External pin interrupt 5) */ + #define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type) 13) /* ICU IRQ6 (External pin interrupt 6) */ + #define ICU_IRQ6_IRQn ((IRQn_Type) 13) /* ICU IRQ6 (External pin interrupt 6) */ + #define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type) 14) /* ICU IRQ7 (External pin interrupt 7) */ + #define ICU_IRQ7_IRQn ((IRQn_Type) 14) /* ICU IRQ7 (External pin interrupt 7) */ + #define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type) 15) /* ICU IRQ8 (External pin interrupt 8) */ + #define ICU_IRQ8_IRQn ((IRQn_Type) 15) /* ICU IRQ8 (External pin interrupt 8) */ + #define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type) 16) /* ICU IRQ9 (External pin interrupt 9) */ + #define ICU_IRQ9_IRQn ((IRQn_Type) 16) /* ICU IRQ9 (External pin interrupt 9) */ + #define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type) 17) /* ICU IRQ13 (External pin interrupt 13) */ + #define ICU_IRQ13_IRQn ((IRQn_Type) 17) /* ICU IRQ13 (External pin interrupt 13) */ + #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type) 18) /* SPI0 RXI (Receive buffer full) */ + #define SPI0_RXI_IRQn ((IRQn_Type) 18) /* SPI0 RXI (Receive buffer full) */ + #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type) 19) /* SPI0 TEI (Transmission complete event) */ + #define SPI0_TEI_IRQn ((IRQn_Type) 19) /* SPI0 TEI (Transmission complete event) */ + #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type) 20) /* SPI0 ERI (Error) */ + #define SPI0_ERI_IRQn ((IRQn_Type) 20) /* SPI0 ERI (Error) */ + #define VECTOR_NUMBER_DMAC0_INT ((IRQn_Type) 21) /* DMAC0 INT (DMAC0 transfer end) */ + #define DMAC0_INT_IRQn ((IRQn_Type) 21) /* DMAC0 INT (DMAC0 transfer end) */ + #define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type) 22) /* ICU IRQ10 (External pin interrupt 10) */ + #define ICU_IRQ10_IRQn ((IRQn_Type) 22) /* ICU IRQ10 (External pin interrupt 10) */ + #define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type) 23) /* ICU IRQ11 (External pin interrupt 11) */ + #define ICU_IRQ11_IRQn ((IRQn_Type) 23) /* ICU IRQ11 (External pin interrupt 11) */ + #define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type) 24) /* ICU IRQ12 (External pin interrupt 12) */ + #define ICU_IRQ12_IRQn ((IRQn_Type) 24) /* ICU IRQ12 (External pin interrupt 12) */ + #define VECTOR_NUMBER_ICU_IRQ14 ((IRQn_Type) 25) /* ICU IRQ14 (External pin interrupt 14) */ + #define ICU_IRQ14_IRQn ((IRQn_Type) 25) /* ICU IRQ14 (External pin interrupt 14) */ + #define VECTOR_NUMBER_ICU_IRQ15 ((IRQn_Type) 26) /* ICU IRQ15 (External pin interrupt 15) */ + #define ICU_IRQ15_IRQn ((IRQn_Type) 26) /* ICU IRQ15 (External pin interrupt 15) */ + #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 27) /* SCI0 RXI (Receive data full) */ + #define SCI0_RXI_IRQn ((IRQn_Type) 27) /* SCI0 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type) 28) /* SCI0 TXI (Transmit data empty) */ + #define SCI0_TXI_IRQn ((IRQn_Type) 28) /* SCI0 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type) 29) /* SCI0 TEI (Transmit end) */ + #define SCI0_TEI_IRQn ((IRQn_Type) 29) /* SCI0 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type) 30) /* SCI0 ERI (Receive error) */ + #define SCI0_ERI_IRQn ((IRQn_Type) 30) /* SCI0 ERI (Receive error) */ + #define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type) 31) /* SCI1 RXI (Receive data full) */ + #define SCI1_RXI_IRQn ((IRQn_Type) 31) /* SCI1 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type) 32) /* SCI1 TXI (Transmit data empty) */ + #define SCI1_TXI_IRQn ((IRQn_Type) 32) /* SCI1 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type) 33) /* SCI1 TEI (Transmit end) */ + #define SCI1_TEI_IRQn ((IRQn_Type) 33) /* SCI1 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type) 34) /* SCI1 ERI (Receive error) */ + #define SCI1_ERI_IRQn ((IRQn_Type) 34) /* SCI1 ERI (Receive error) */ + #define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type) 35) /* SCI2 RXI (Receive data full) */ + #define SCI2_RXI_IRQn ((IRQn_Type) 35) /* SCI2 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type) 36) /* SCI2 TXI (Transmit data empty) */ + #define SCI2_TXI_IRQn ((IRQn_Type) 36) /* SCI2 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type) 37) /* SCI2 TEI (Transmit end) */ + #define SCI2_TEI_IRQn ((IRQn_Type) 37) /* SCI2 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type) 38) /* SCI2 ERI (Receive error) */ + #define SCI2_ERI_IRQn ((IRQn_Type) 38) /* SCI2 ERI (Receive error) */ + #define VECTOR_NUMBER_SCI3_RXI ((IRQn_Type) 39) /* SCI3 RXI (Receive data full) */ + #define SCI3_RXI_IRQn ((IRQn_Type) 39) /* SCI3 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI3_TXI ((IRQn_Type) 40) /* SCI3 TXI (Transmit data empty) */ + #define SCI3_TXI_IRQn ((IRQn_Type) 40) /* SCI3 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI3_TEI ((IRQn_Type) 41) /* SCI3 TEI (Transmit end) */ + #define SCI3_TEI_IRQn ((IRQn_Type) 41) /* SCI3 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI3_ERI ((IRQn_Type) 42) /* SCI3 ERI (Receive error) */ + #define SCI3_ERI_IRQn ((IRQn_Type) 42) /* SCI3 ERI (Receive error) */ + #define VECTOR_NUMBER_SCI4_RXI ((IRQn_Type) 43) /* SCI4 RXI (Receive data full) */ + #define SCI4_RXI_IRQn ((IRQn_Type) 43) /* SCI4 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI4_TXI ((IRQn_Type) 44) /* SCI4 TXI (Transmit data empty) */ + #define SCI4_TXI_IRQn ((IRQn_Type) 44) /* SCI4 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI4_TEI ((IRQn_Type) 45) /* SCI4 TEI (Transmit end) */ + #define SCI4_TEI_IRQn ((IRQn_Type) 45) /* SCI4 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type) 46) /* SCI4 ERI (Receive error) */ + #define SCI4_ERI_IRQn ((IRQn_Type) 46) /* SCI4 ERI (Receive error) */ + #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 47) /* SCI9 RXI (Receive data full) */ + #define SCI9_RXI_IRQn ((IRQn_Type) 47) /* SCI9 RXI (Receive data full) */ + #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 48) /* SCI9 TXI (Transmit data empty) */ + #define SCI9_TXI_IRQn ((IRQn_Type) 48) /* SCI9 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type) 49) /* SCI9 TEI (Transmit end) */ + #define SCI9_TEI_IRQn ((IRQn_Type) 49) /* SCI9 TEI (Transmit end) */ + #define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 50) /* SCI9 ERI (Receive error) */ + #define SCI9_ERI_IRQn ((IRQn_Type) 50) /* SCI9 ERI (Receive error) */ + #define VECTOR_NUMBER_SPI1_RXI ((IRQn_Type) 51) /* SPI1 RXI (Receive buffer full) */ + #define SPI1_RXI_IRQn ((IRQn_Type) 51) /* SPI1 RXI (Receive buffer full) */ + #define VECTOR_NUMBER_SPI1_TEI ((IRQn_Type) 52) /* SPI1 TEI (Transmission complete event) */ + #define SPI1_TEI_IRQn ((IRQn_Type) 52) /* SPI1 TEI (Transmission complete event) */ + #define VECTOR_NUMBER_SPI1_ERI ((IRQn_Type) 53) /* SPI1 ERI (Error) */ + #define SPI1_ERI_IRQn ((IRQn_Type) 53) /* SPI1 ERI (Error) */ + #define VECTOR_NUMBER_DMAC1_INT ((IRQn_Type) 54) /* DMAC1 INT (DMAC1 transfer end) */ + #define DMAC1_INT_IRQn ((IRQn_Type) 54) /* DMAC1 INT (DMAC1 transfer end) */ + #define VECTOR_NUMBER_IIC1_RXI ((IRQn_Type) 55) /* IIC1 RXI (Receive data full) */ + #define IIC1_RXI_IRQn ((IRQn_Type) 55) /* IIC1 RXI (Receive data full) */ + #define VECTOR_NUMBER_IIC1_TXI ((IRQn_Type) 56) /* IIC1 TXI (Transmit data empty) */ + #define IIC1_TXI_IRQn ((IRQn_Type) 56) /* IIC1 TXI (Transmit data empty) */ + #define VECTOR_NUMBER_IIC1_TEI ((IRQn_Type) 57) /* IIC1 TEI (Transmit end) */ + #define IIC1_TEI_IRQn ((IRQn_Type) 57) /* IIC1 TEI (Transmit end) */ + #define VECTOR_NUMBER_IIC1_ERI ((IRQn_Type) 58) /* IIC1 ERI (Transfer error) */ + #define IIC1_ERI_IRQn ((IRQn_Type) 58) /* IIC1 ERI (Transfer error) */ + #define VECTOR_NUMBER_CAN0_CHERR ((IRQn_Type) 59) /* CAN0 CHERR (Channel error) */ + #define CAN0_CHERR_IRQn ((IRQn_Type) 59) /* CAN0 CHERR (Channel error) */ + #define VECTOR_NUMBER_CAN0_TX ((IRQn_Type) 60) /* CAN0 TX (Transmit interrupt) */ + #define CAN0_TX_IRQn ((IRQn_Type) 60) /* CAN0 TX (Transmit interrupt) */ + #define VECTOR_NUMBER_CAN0_COMFRX ((IRQn_Type) 61) /* CAN0 COMFRX (Common FIFO receive interrupt) */ + #define CAN0_COMFRX_IRQn ((IRQn_Type) 61) /* CAN0 COMFRX (Common FIFO receive interrupt) */ + #define VECTOR_NUMBER_CAN_GLERR ((IRQn_Type) 62) /* CAN GLERR (Global error) */ + #define CAN_GLERR_IRQn ((IRQn_Type) 62) /* CAN GLERR (Global error) */ + #define VECTOR_NUMBER_CAN_RXF ((IRQn_Type) 63) /* CAN RXF (Global receive FIFO interrupt) */ + #define CAN_RXF_IRQn ((IRQn_Type) 63) /* CAN RXF (Global receive FIFO interrupt) */ + #define VECTOR_NUMBER_CAN1_CHERR ((IRQn_Type) 64) /* CAN1 CHERR (Channel error) */ + #define CAN1_CHERR_IRQn ((IRQn_Type) 64) /* CAN1 CHERR (Channel error) */ + #define VECTOR_NUMBER_CAN1_TX ((IRQn_Type) 65) /* CAN1 TX (Transmit interrupt) */ + #define CAN1_TX_IRQn ((IRQn_Type) 65) /* CAN1 TX (Transmit interrupt) */ + #define VECTOR_NUMBER_CAN1_COMFRX ((IRQn_Type) 66) /* CAN1 COMFRX (Common FIFO receive interrupt) */ + #define CAN1_COMFRX_IRQn ((IRQn_Type) 66) /* CAN1 COMFRX (Common FIFO receive interrupt) */ + #define VECTOR_NUMBER_FCU_FRDYI ((IRQn_Type) 67) /* FCU FRDYI (Flash ready interrupt) */ + #define FCU_FRDYI_IRQn ((IRQn_Type) 67) /* FCU FRDYI (Flash ready interrupt) */ + #define VECTOR_NUMBER_FCU_FIFERR ((IRQn_Type) 68) /* FCU FIFERR (Flash access error interrupt) */ + #define FCU_FIFERR_IRQn ((IRQn_Type) 68) /* FCU FIFERR (Flash access error interrupt) */ + /* The number of entries required for the ICU vector table. */ + #define BSP_ICU_VECTOR_NUM_ENTRIES (69) + + #ifdef __cplusplus + } + #endif + #endif /* VECTOR_DATA_H */ \ No newline at end of file diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/board_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/board_cfg.h new file mode 100644 index 0000000000..62732fdc0d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/board_cfg.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "./TARGET_FPB_RA8E1/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_cfg.h new file mode 100644 index 0000000000..7c2cb477e3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_cfg.h @@ -0,0 +1,75 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "bsp_mcu_ofs_cfg.h" + #include "board_cfg.h" + #include "vector_data.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (1) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #if MBED_CONF_RTOS_PRESENT + #define BSP_CFG_STACK_MAIN_BYTES (MBED_CONF_TARGET_BOOT_STACK_SIZE) + #else + #define BSP_CFG_STACK_MAIN_BYTES (MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE) + #endif + #define BSP_CFG_HEAP_BYTES (0) + #ifdef MBED_DEBUG + #define BSP_CFG_PARAM_CHECKING_ENABLE (1) + #else + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #endif + #define BSP_CFG_ASSERT (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_device_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_device_cfg.h new file mode 100644 index 0000000000..ddb8945142 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_device_cfg.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (8) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_device_pn_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_device_pn_cfg.h new file mode 100644 index 0000000000..c3a6d9a287 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA8E1AFDCFB + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_NUMBER_OF_CORES (1) + #define BSP_PACKAGE_LQFP + #define BSP_ROM_SIZE_BYTES (1048576) + #define BSP_RAM_SIZE_BYTES (524288) + #define BSP_DATA_FLASH_SIZE_BYTES (12288) + #define BSP_PACKAGE_PINS (144) + #define BSP_OSPI0_CS0_START_ADDRESS (2147483648) + #define BSP_OSPI0_CS0_SIZE_BYTES (268435456) + #define BSP_OSPI0_CS1_START_ADDRESS (2415919104) + #define BSP_OSPI0_CS1_SIZE_BYTES (268435456) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_family_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_family_cfg.h new file mode 100644 index 0000000000..eb63c68c8d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_family_cfg.h @@ -0,0 +1,348 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra8e1/bsp_override.h" + #include "../../../ra/fsp/src/bsp/mcu/ra8e1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA8E1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (0) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 7 + #define BSP_HOCO_HZ (48000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + + #define BSP_CFG_FLL_ENABLE (0) + + #define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1) + #define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1) + #define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1) + #define BSP_CFG_RTOS_IDLE_SLEEP (0) + #define BSP_CFG_CLOCK_SETTLING_DELAY_US (150) + #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U) + + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + + #if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif + + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL + #define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL + #define FPU_FPCCR_TS_VAL (1U) +#endif + #define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL + #define FPU_FPCCR_CLRONRET_VAL (1) +#endif + + /* Type 1 Peripheral Security Attribution */ + + /* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((1 > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((1 > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ETHERC */ | \ + (((1 > 0) ? 0U : 1U) << 16) /* OSPI */ | \ + (((1 > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((1 > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((1 > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((1 > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((1 > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((1 > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* SCI0 */) +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \ + (((1 > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \ + (((1 > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* RSIP-E51A */) +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((1 > 0) ? 0U : 1U) << 4) /* AGT1 */ | \ + (((1 > 0) ? 0U : 1U) << 5) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \ + (((1 > 0) ? 0U : 1U) << 16) /* ADC120 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \ + (((1 > 0) ? 0U : 1U) << 22) /* TSN */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */) +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((1 > 0) ? 0U : 1U) << 1) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \ + (((1 > 0) ? 0U : 1U) << 3) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \ + (((1 > 0) ? 0U : 1U) << 18) /* GPT13 */ | \ + (((1 > 0) ? 0U : 1U) << 19) /* GPT12 */ | \ + (((1 > 0) ? 0U : 1U) << 20) /* GPT11 */ | \ + (((1 > 0) ? 0U : 1U) << 21) /* GPT10 */ | \ + (((1 > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((1 > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((1 > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */) +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((2 > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */) +#endif + + /* Type 2 Peripheral Security Attribution */ + + /* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0x00000007U) +#endif + + /* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR + /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ +#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) +#define BSP_TZ_CFG_LVDSAR (0U) +#else +#define BSP_TZ_CFG_LVDSAR (3U) +#endif +#endif + + /* Security attribution for LPM registers. + * - OPCCR based on clock security. + * - Set remaining registers based on LPM security. + */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((1 > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\ + 0x002E0106U | \ + (BSP_CFG_CLOCKS_SECURE == 0))) +#endif + /* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((1 > 0) ? 0U : 0xAD1FFFFFU) +#endif + /* RAM Standby Control Security Attribution Register. */ +#ifndef BSP_TZ_CFG_RSCSAR +#define BSP_TZ_CFG_RSCSAR ((1 > 0) ? 0U : 0x0001007FU) +#endif + + /* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0x00670BFDU) +#endif +#endif + + /* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#if 0 +#define BSP_TZ_CFG_BBFSAR (0U) +#else +#define BSP_TZ_CFG_BBFSAR (0x1FU) +#endif +#endif + + /* Security attribution for Battery Backup registers (VBTBKRn). */ +#ifndef BSP_TZ_CFG_VBRSABAR +#if 0 +#define BSP_TZ_CFG_VBRSABAR (0xFFE0) +#else +#define BSP_TZ_CFG_VBRSABAR (0xED00) +#endif +#endif + + /* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((1 > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((1 > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((1 > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((1 > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((1 > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((1 > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((1 > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((1 > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((1 > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((1 > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((1 > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((1 > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((1 > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((1 > 0) ? 0U : 1U) << 15U) /* External IRQ15 */) +#endif + + /* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0U) /* Should match AIRCR.BFHFNMINS. */ +#endif + + /* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_DMACCHSAR +#define BSP_TZ_CFG_DMACCHSAR (\ + (((1 > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((1 > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */) +#endif + + /* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((1 > 0) ? 0U : 0xFB1D0000U) +#endif + + /* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((1 > 0) ? 0U : 0x00007708U) +#endif + + /* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */ +#ifndef BSP_TZ_CFG_TEVTRCR +#define BSP_TZ_CFG_TEVTRCR (0) +#endif + + /* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ +#ifndef BSP_TZ_CFG_ELCSARA + #define BSP_TZ_CFG_ELCSARA (0x00000007U) +#endif + + /* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED + #define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + + /* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#define BSP_TZ_CFG_FSAR (\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\ + ((1) > 0 ? 0U: (1U << 1)) | /* FCACHESA */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \ + ((1) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */\ + ((1) > 0 ? 0U: (1U << 10U)) /* FACICMRSA */) +#endif + + /* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ + #define BSP_TZ_CFG_SRAMSAR (\ + ((1U) << 1U) | /* SRAMSA1 */\ + ((1U) << 7U) | /* STBRAMSA */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */) +#endif + + /* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR) +#endif + + /* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA + #define BSP_TZ_CFG_BUSSARA (1U) +#endif + /* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB + #define BSP_TZ_CFG_BUSSARB (1U) +#endif + + /* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifndef BSP_CFG_DCACHE_ENABLED +#define BSP_CFG_DCACHE_ENABLED (1) +#endif + +#ifndef BSP_CFG_DCACHE_FORCE_WRITETHROUGH +#define BSP_CFG_DCACHE_FORCE_WRITETHROUGH (1) +#endif + +#ifndef BSP_CFG_IOPORT_VOLTAGE_MODE_VCC +#define BSP_CFG_IOPORT_VOLTAGE_MODE_VCC (0) +#endif + +#ifndef BSP_CFG_IOPORT_VOLTAGE_MODE_VCC2 +#define BSP_CFG_IOPORT_VOLTAGE_MODE_VCC2 (0) +#endif + + +#ifndef BSP_CFG_OSPI_B_STARTUP_ENABLED + #define BSP_CFG_OSPI_B_STARTUP_ENABLED (0) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_ofs_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_ofs_cfg.h new file mode 100644 index 0000000000..365cb317d9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_mcu_ofs_cfg.h @@ -0,0 +1,28 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_OFS_CFG_H_ +#define BSP_MCU_OFS_CFG_H_ +#ifndef BSP_CFG_OPTION_SETTING_OFS0 +#define OFS_IWDT (0xA001A001 | 1 << 1 | 3 << 2 | 15 << 4 | 3 << 8 | 3 << 10 | 1 << 12 | 1 << 14) +#define OFS_WDT (1 << 17 | 3 << 18 | 15 << 20 | 3 << 24 | 3 << 26 | 1 << 28 | 1 << 30) +#define BSP_CFG_OPTION_SETTING_OFS0 (OFS_IWDT | OFS_WDT) +#endif +#ifndef BSP_CFG_OPTION_SETTING_OFS2 +#define BSP_CFG_OPTION_SETTING_OFS2 ((1 << 0) | (0xFFFFFFFE)) +#endif +#ifndef BSP_CFG_OPTION_SETTING_OFS1_SEC +#define BSP_CFG_OPTION_SETTING_OFS1_SEC_NO_HOCOFRQ (0xFCFFF0D0 | 1 <<3 | 7 | 1 << 5 | 1 << 8 | 1 << 24 | 0 << 25) + +#define BSP_CFG_OPTION_SETTING_OFS1_SEC ((uint32_t) BSP_CFG_OPTION_SETTING_OFS1_SEC_NO_HOCOFRQ | ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET)) +#endif +#ifndef BSP_CFG_OPTION_SETTING_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_OPTION_SETTING_OFS1_SEL (0 | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00 : 0U) | ((0U << 24U)) | ((0U << 25U))) +#else + #define BSP_CFG_OPTION_SETTING_OFS1_SEL (0) +#endif +#endif +#endif /* BSP_MCU_OFS_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_pin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_pin_cfg.h new file mode 100644 index 0000000000..6e01f28001 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/bsp_pin_cfg.h @@ -0,0 +1,89 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define Arduino_A3 (BSP_IO_PORT_00_PIN_01) +#define Arduino_A1 (BSP_IO_PORT_00_PIN_03) +#define Arduino_A0 (BSP_IO_PORT_00_PIN_04) +#define PMOD1_IRQ (BSP_IO_PORT_00_PIN_06) +#define Arduino_A2 (BSP_IO_PORT_00_PIN_07) +#define USER_SW (BSP_IO_PORT_00_PIN_09) +#define PMOD2_IRQ (BSP_IO_PORT_00_PIN_10) +#define Arduino_A4 (BSP_IO_PORT_00_PIN_14) +#define Arduino_A5 (BSP_IO_PORT_00_PIN_15) +#define JLINK_VCOM_RXD (BSP_IO_PORT_01_PIN_01) +#define JLINK_VCOM_TXD (BSP_IO_PORT_01_PIN_02) +#define JLINK_VCOM_CTS_RTS (BSP_IO_PORT_01_PIN_03) +#define JLINK_VCOM_CTS (BSP_IO_PORT_01_PIN_04) +#define Ardiuno_RST (BSP_IO_PORT_01_PIN_05) +#define PMOD2_RST (BSP_IO_PORT_01_PIN_06) +#define PMOD2_P9 (BSP_IO_PORT_01_PIN_07) +#define Ardiuno_D9 (BSP_IO_PORT_01_PIN_12) +#define Ardiuno_D6 (BSP_IO_PORT_01_PIN_13) +#define Ardiuno_D5 (BSP_IO_PORT_01_PIN_14) +#define NMI (BSP_IO_PORT_02_PIN_00) +#define MD (BSP_IO_PORT_02_PIN_01) +#define Arduino_D11 (BSP_IO_PORT_02_PIN_02) +#define Arduino_D13 (BSP_IO_PORT_02_PIN_03) +#define Arduino_D10 (BSP_IO_PORT_02_PIN_04) +#define DEBUG_TDI (BSP_IO_PORT_02_PIN_08) +#define DEBUG_TDO (BSP_IO_PORT_02_PIN_09) +#define DEBUG_TMS (BSP_IO_PORT_02_PIN_10) +#define DEBUG_TCK (BSP_IO_PORT_02_PIN_11) +#define EXTAL (BSP_IO_PORT_02_PIN_12) +#define XTAL (BSP_IO_PORT_02_PIN_13) +#define Arduino_D2 (BSP_IO_PORT_03_PIN_00) +#define Arduino_D7 (BSP_IO_PORT_03_PIN_02) +#define Arduino_D8 (BSP_IO_PORT_03_PIN_03) +#define Arduino_D0 (BSP_IO_PORT_03_PIN_09) +#define Arduino_D1 (BSP_IO_PORT_03_PIN_10) +#define Arduino_D12 (BSP_IO_PORT_03_PIN_13) +#define CAM_D0 (BSP_IO_PORT_04_PIN_00) +#define CAM_D1 (BSP_IO_PORT_04_PIN_01) +#define CAM_XCLK (BSP_IO_PORT_04_PIN_03) +#define CAM_D2 (BSP_IO_PORT_04_PIN_05) +#define CAM_D3 (BSP_IO_PORT_04_PIN_06) +#define CAM_E19 (BSP_IO_PORT_04_PIN_14) +#define CAM_User_Arduino_D3 (BSP_IO_PORT_04_PIN_15) +#define IIC_SYSTEM_SDA1 (BSP_IO_PORT_05_PIN_11) +#define IIC_SYSTEM_SCL1 (BSP_IO_PORT_05_PIN_12) +#define PMOD1_RST (BSP_IO_PORT_06_PIN_04) +#define PMOD1_P9 (BSP_IO_PORT_06_PIN_05) +#define PMOD1_MOSI0_TXD0 (BSP_IO_PORT_06_PIN_09) +#define PMOD1_MISOO_RXD0 (BSP_IO_PORT_06_PIN_10) +#define PMOD1_SCK0 (BSP_IO_PORT_06_PIN_11) +#define PMOD1_SS0_CTD_RTS0 (BSP_IO_PORT_06_PIN_12) +#define PMOD1_CTS0 (BSP_IO_PORT_06_PIN_13) +#define PMOD1_P10 (BSP_IO_PORT_06_PIN_14) +#define CAM_D4 (BSP_IO_PORT_07_PIN_00) +#define CAM_D5 (BSP_IO_PORT_07_PIN_01) +#define CAM_D6 (BSP_IO_PORT_07_PIN_02) +#define CAM_D7 (BSP_IO_PORT_07_PIN_03) +#define CAM_CLK (BSP_IO_PORT_07_PIN_08) +#define CAM_HD (BSP_IO_PORT_07_PIN_09) +#define CAM_VD (BSP_IO_PORT_07_PIN_10) +#define PMOD2_CTS2 (BSP_IO_PORT_08_PIN_00) +#define PMOD2_MOSI2_TXD2 (BSP_IO_PORT_08_PIN_01) +#define PMOD2_MISO2_RXD2 (BSP_IO_PORT_08_PIN_02) +#define PMOD2_SCK2 (BSP_IO_PORT_08_PIN_03) +#define PMOD2_SS2_CTS_RTS2 (BSP_IO_PORT_08_PIN_04) +#define CAM_E23 (BSP_IO_PORT_08_PIN_05) +#define CAM_E34 (BSP_IO_PORT_08_PIN_06) +#define PMOD2_P10 (BSP_IO_PORT_08_PIN_09) +#define Arduino_D4 (BSP_IO_PORT_09_PIN_05) + +extern const ioport_cfg_t g_bsp_pin_cfg; /* FPB_RA4E1.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/can_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/can_device.c new file mode 100644 index 0000000000..25a56d1412 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/can_device.c @@ -0,0 +1,15 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "PeripheralNames.h" +#include "hal_data.h" +#include "device.h" + +const can_instance_t * const g_can_instances[CAN_COUNT] = { + &g_canfd0, + &g_canfd1, +}; + +canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH0_RULE_NUM]; +canfd_afl_entry_t p_canfd1_afl[CANFD_CFG_AFL_CH1_RULE_NUM]; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/flash_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/flash_device.h new file mode 100644 index 0000000000..645df0db6b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/flash_device.h @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef FLASH_DEVICE_H +#define FLASH_DEVICE_H + +/* RA8E1: 1MB Code Flash, 12KB Data Flash */ +#ifndef RA_CF_START +#define RA_CF_START (0x02000000u) +#endif +#ifndef RA_CF_SIZE +#define RA_CF_SIZE (1024u * 1024u) +#endif +#ifndef RA_CF_WRITE_SIZE +#define RA_CF_WRITE_SIZE (128u) +#endif + +#ifndef RA_DF_START +#define RA_DF_START (0x27000000u) +#endif +#ifndef RA_DF_SIZE +#define RA_DF_SIZE (12u * 1024u) +#endif +#ifndef RA_DF_SECTOR_SIZE +#define RA_DF_SECTOR_SIZE (64u) +#endif +#ifndef RA_DF_WRITE_SIZE +#define RA_DF_WRITE_SIZE (4u) +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/gpio_irq_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/gpio_irq_device.c new file mode 100644 index 0000000000..e86e621c98 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/gpio_irq_device.c @@ -0,0 +1,45 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "PeripheralNames.h" +#include "common_data.h" +#include "device.h" + +icu_instance_ctrl_t * const g_icu_ctrl[IRQ_CHANNELS_COUNT] = { + &g_external_irq0_ctrl, + &g_external_irq1_ctrl, + &g_external_irq2_ctrl, + &g_external_irq3_ctrl, + &g_external_irq4_ctrl, + &g_external_irq5_ctrl, + &g_external_irq6_ctrl, + &g_external_irq7_ctrl, + &g_external_irq8_ctrl, + &g_external_irq9_ctrl, + &g_external_irq10_ctrl, + &g_external_irq11_ctrl, + &g_external_irq12_ctrl, + &g_external_irq13_ctrl, + &g_external_irq14_ctrl, + &g_external_irq15_ctrl, +}; + +const external_irq_cfg_t * const g_icu_cfg[IRQ_CHANNELS_COUNT] = { + &g_external_irq0_cfg, + &g_external_irq1_cfg, + &g_external_irq2_cfg, + &g_external_irq3_cfg, + &g_external_irq4_cfg, + &g_external_irq5_cfg, + &g_external_irq6_cfg, + &g_external_irq7_cfg, + &g_external_irq8_cfg, + &g_external_irq9_cfg, + &g_external_irq10_cfg, + &g_external_irq11_cfg, + &g_external_irq12_cfg, + &g_external_irq13_cfg, + &g_external_irq14_cfg, + &g_external_irq15_cfg, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/i2c_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/i2c_device.h new file mode 100644 index 0000000000..78549fb31c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/i2c_device.h @@ -0,0 +1,21 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef I2C_DEVICE_H +#define I2C_DEVICE_H + +#include "r_iic_master.h" + +typedef struct { + int hz; + iic_master_clock_settings_t clk; +} iic_clock_entry_t; + +static const iic_clock_entry_t g_iic_clock_table[] = { + { 100000, { .cks_value = 4, .brh_value = 16, .brl_value = 15, .sddl_value = 0, .dlcs_value = 0 }}, + { 400000, { .cks_value = 1, .brh_value = 31, .brl_value = 31, .sddl_value = 0, .dlcs_value = 0 }}, + {1000000, { .cks_value = 0, .brh_value = 19, .brl_value = 19, .sddl_value = 0, .dlcs_value = 0 }}, +}; + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/pwmout_device.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/pwmout_device.h new file mode 100644 index 0000000000..fa65cb436f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/pwmout_device.h @@ -0,0 +1,27 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "PeripheralNames.h" +#include "hal_data.h" + +const timer_instance_t *pwm_timer_lookup(PWMName name) +{ + switch (name) { + case PWM_GPT0: return &g_timer_gpt0; + case PWM_GPT1: return &g_timer_gpt1; + case PWM_GPT2: return &g_timer_gpt2; + case PWM_GPT3: return &g_timer_gpt3; + case PWM_GPT4: return &g_timer_gpt4; + case PWM_GPT5: return &g_timer_gpt5; + case PWM_GPT10: return &g_timer_gpt10; + case PWM_GPT11: return &g_timer_gpt11; + case PWM_GPT12: return &g_timer_gpt12; + case PWM_GPT13: return &g_timer_gpt13; + case PWM_AGT0: return &g_timer_agt0; + case PWM_AGT1: return &g_timer_agt1; + default: return NULL; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_acmphs_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_acmphs_cfg.h new file mode 100644 index 0000000000..fc8046a7f5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_acmphs_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ACMPHS_CFG_H_ +#define R_ACMPHS_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ACMPHS_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ACMPHS_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_acmplp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_acmplp_cfg.h new file mode 100644 index 0000000000..a66ead8b31 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_acmplp_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ACMPLP_CFG_H_ +#define R_ACMPLP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ACMPLP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ACMPLP_CFG_CH1_IVREF0_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_ACMPLP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_adc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_adc_cfg.h new file mode 100644 index 0000000000..d16c3e39e7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_adc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ADC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_agt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_agt_cfg.h new file mode 100644 index 0000000000..0e70aee2cd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_agt_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define AGT_CFG_OUTPUT_SUPPORT_ENABLE (1) + #define AGT_CFG_INPUT_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_AGT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cac_cfg.h new file mode 100644 index 0000000000..a399409760 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CAC_CFG_H_ +#define R_CAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_canfd_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_canfd_cfg.h new file mode 100644 index 0000000000..8517169fad --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_canfd_cfg.h @@ -0,0 +1,158 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CANFD_CFG_H_ +#define R_CANFD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CANFD_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #define CANFD_CFG_AFL_CH0_RULE_NUM (16) + #define CANFD_CFG_AFL_CH1_RULE_NUM (16) + + #define CANFD_CFG_GLOBAL_ERROR_CH ((0U)) + + #define CANFD_CFG_FD_PROTOCOL_EXCEPTION ((0)) + #define CANFD_CFG_GLOBAL_ERR_IPL ((12)) + #define CANFD_CFG_RX_FIFO_IPL ((12)) + #define CANFD_CFG_GLOBAL_ERR_SOURCES ( 0x3) + #define CANFD_CFG_TX_PRIORITY ((R_CANFD_CFDGCFG_TPRI_Msk)) + #define CANFD_CFG_DLC_CHECK ((0)) + #define CANFD_CFG_FD_OVERFLOW ((0)) + #define CANFD_CFG_RXMB_NUMBER (0) + #define CANFD_CFG_RXMB_SIZE ((0)) + #define CANFD_CFG_RXFIFO0_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO0_DEPTH ((3)) + #define CANFD_CFG_RXFIFO0_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO0_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO0_ENABLE ((1)) + + #define CANFD_CFG_RXFIFO1_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO1_DEPTH ((3)) + #define CANFD_CFG_RXFIFO1_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO1_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO1_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO2_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO2_DEPTH ((3)) + #define CANFD_CFG_RXFIFO2_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO2_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO2_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO3_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO3_DEPTH ((3)) + #define CANFD_CFG_RXFIFO3_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO3_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO3_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO4_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO4_DEPTH ((3)) + #define CANFD_CFG_RXFIFO4_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO4_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO4_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO5_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO5_DEPTH ((3)) + #define CANFD_CFG_RXFIFO5_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO5_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO5_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO6_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO6_DEPTH ((3)) + #define CANFD_CFG_RXFIFO6_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO6_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO6_ENABLE ((0)) + + #define CANFD_CFG_RXFIFO7_INT_THRESHOLD ((3U)) + #define CANFD_CFG_RXFIFO7_DEPTH ((3)) + #define CANFD_CFG_RXFIFO7_PAYLOAD ((0)) + #define CANFD_CFG_RXFIFO7_INT_MODE ((R_CANFD_CFDRFCC_RFIE_Msk | R_CANFD_CFDRFCC_RFIM_Msk)) + #define CANFD_CFG_RXFIFO7_ENABLE ((0)) + + #define CANFD_CFG_COMMONFIFO0 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO1 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO2 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO3 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO4 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + #define CANFD_CFG_COMMONFIFO5 (((0) << R_CANFD_CFDCFCC_CFE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFRXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTXIE_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFPLS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFM_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITSS_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFITR_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFIM_Pos) | \ + ((3U) << R_CANFD_CFDCFCC_CFIGCV_Pos) | \ + ((0) << R_CANFD_CFDCFCC_CFTML_Pos) | \ + ((3) << R_CANFD_CFDCFCC_CFDC_Pos) | \ + (0 << R_CANFD_CFDCFCC_CFITT_Pos)) + + + #ifdef __cplusplus + } + #endif +#endif /* R_CANFD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cec_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cec_cfg.h new file mode 100644 index 0000000000..8a583197f2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cec_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CEC_CFG_H_ +#define R_CEC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CEC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define CEC_DATA_BUFFER_LENGTH (14) + + #ifdef __cplusplus + } + #endif +#endif /* R_CEC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ceu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ceu_cfg.h new file mode 100644 index 0000000000..12c0fd54f8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ceu_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CEU_CFG_H_ +#define R_CEU_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CEU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CEU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cgc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cgc_cfg.h new file mode 100644 index 0000000000..ffbf789754 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_cgc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CGC_CFG_H_ +#define R_CGC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CGC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define CGC_CFG_USE_LOW_VOLTAGE_MODE RA_NOT_DEFINED + +#ifdef __cplusplus +} +#endif +#endif /* R_CGC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_crc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_crc_cfg.h new file mode 100644 index 0000000000..5de5d44d04 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_crc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CRC_CFG_H_ +#define R_CRC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CRC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CRC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ctsu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ctsu_cfg.h new file mode 100644 index 0000000000..846940d95b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ctsu_cfg.h @@ -0,0 +1,237 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_CTSU_CFG_H_ +#define R_CTSU_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define CTSU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define CTSU_CFG_DTC_SUPPORT_ENABLE (0) + #define CTSU_CFG_INT_PRIORITY_LEVEL (12) + #define CTSU_CFG_AUTO_JUDGE_ENABLE (0) + #ifndef QE_TOUCH_CONFIGURATION + #define CTSU_CFG_NUM_SELF_ELEMENTS (1) + #define CTSU_CFG_NUM_MUTUAL_ELEMENTS (0) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + #define CTSU_CFG_MAJORITY_MODE (2) + #define CTSU_CFG_NUM_AUTOJUDGE_SELF_ELEMENTS (1) + #define CTSU_CFG_NUM_AUTOJUDGE_MUTUAL_ELEMENTS (0) + #define CTSU_CFG_AUTO_CORRECTION_ENABLE (1) + #else + #define CTSU_CFG_MAJORITY_MODE (1) + #define CTSU_CFG_NUM_AUTOJUDGE_SELF_ELEMENTS (0) + #define CTSU_CFG_NUM_AUTOJUDGE_MUTUAL_ELEMENTS (0) + #define CTSU_CFG_AUTO_CORRECTION_ENABLE (0) + #endif + #define CTSU_CFG_LOW_VOLTAGE_MODE (0) + #define CTSU_CFG_PCLK_DIVISION (0) + #define CTSU_CFG_TSCAP_PORT (0xFFFF) + #define CTSU_CFG_VCC_MV (5000) + #define CTSU_CFG_DIAG_SUPPORT_ENABLE (0) + #if (BSP_FEATURE_CTSU_VERSION == 2) + #define CTSU_CFG_NUM_CFC (0) + #define CTSU_CFG_NUM_CFC_TX (0) + #define CTSU_CFG_NUM_SUMULTI (3) + #define CTSU_CFG_SUMULTI0 (0x3F) + #define CTSU_CFG_SUMULTI1 (0x36) + #define CTSU_CFG_SUMULTI2 (0x48) + #define CTSU_CFG_TEMP_CORRECTION_SUPPORT (0) + #define CTSU_CFG_TEMP_CORRECTION_TS (0) + #define CTSU_CFG_TEMP_CORRECTION_TIME (0) + #define CTSU_CFG_CALIB_RTRIM_SUPPORT (0) + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + #define CTSU_CFG_NUM_SUMULTI (1) + #endif + #endif + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + #if (BSP_FEATURE_CTSU_VERSION == 1) + #if (BSP_CFG_MCU_PART_SERIES == 2) || (BSP_CFG_MCU_PART_SERIES == 4) + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (54888) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (29062) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (3269) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (705) + #define CTSU_CFG_DIAG_SSCG_MAX (21813) + #define CTSU_CFG_DIAG_SSCG_MIN (11782) + #define CTSU_CFG_DIAG_DAC1_MAX (20422) + #define CTSU_CFG_DIAG_DAC2_MAX (21532) + #define CTSU_CFG_DIAG_DAC3_MAX (23015) + #define CTSU_CFG_DIAG_DAC4_MAX (25923) + #define CTSU_CFG_DIAG_DAC5_MAX (32016) + #define CTSU_CFG_DIAG_DAC6_MAX (45795) + #define CTSU_CFG_DIAG_DAC1_MIN (12492) + #define CTSU_CFG_DIAG_DAC2_MIN (14053) + #define CTSU_CFG_DIAG_DAC3_MIN (15322) + #define CTSU_CFG_DIAG_DAC4_MIN (18070) + #define CTSU_CFG_DIAG_DAC5_MIN (23262) + #define CTSU_CFG_DIAG_DAC6_MIN (33446) + + #else + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (43910) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (23249) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (2615) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (564) + #define CTSU_CFG_DIAG_SSCG_MAX (21813) + #define CTSU_CFG_DIAG_SSCG_MIN (11782) + #define CTSU_CFG_DIAG_DAC1_MAX (16599) + #define CTSU_CFG_DIAG_DAC2_MAX (17226) + #define CTSU_CFG_DIAG_DAC3_MAX (18412) + #define CTSU_CFG_DIAG_DAC4_MAX (20738) + #define CTSU_CFG_DIAG_DAC5_MAX (25613) + #define CTSU_CFG_DIAG_DAC6_MAX (36636) + #define CTSU_CFG_DIAG_DAC1_MIN (9994) + #define CTSU_CFG_DIAG_DAC2_MIN (11242) + #define CTSU_CFG_DIAG_DAC3_MIN (12258) + #define CTSU_CFG_DIAG_DAC4_MIN (14456) + #define CTSU_CFG_DIAG_DAC5_MIN (18610) + #define CTSU_CFG_DIAG_DAC6_MIN (26757) + #endif + #endif + #if (BSP_CFG_MCU_PART_SERIES == 6) + #define CTSU_CFG_DIAG_CCO_HIGH_MAX (36873) + #define CTSU_CFG_DIAG_CCO_HIGH_MIN (24433) + #define CTSU_CFG_DIAG_CCO_LOW_MAX (1781) + #define CTSU_CFG_DIAG_CCO_LOW_MIN (105) + #define CTSU_CFG_DIAG_SSCG_MAX (17795) + #define CTSU_CFG_DIAG_SSCG_MIN (9610) + #define CTSU_CFG_DIAG_DAC1_MAX (20422) + #define CTSU_CFG_DIAG_DAC2_MAX (21532) + #define CTSU_CFG_DIAG_DAC3_MAX (23015) + #define CTSU_CFG_DIAG_DAC4_MAX (25923) + #define CTSU_CFG_DIAG_DAC5_MAX (32016) + #define CTSU_CFG_DIAG_DAC6_MAX (45795) + #define CTSU_CFG_DIAG_DAC1_MIN (12492) + #define CTSU_CFG_DIAG_DAC2_MIN (14053) + #define CTSU_CFG_DIAG_DAC3_MIN (15322) + #define CTSU_CFG_DIAG_DAC4_MIN (18070) + #define CTSU_CFG_DIAG_DAC5_MIN (23262) + #define CTSU_CFG_DIAG_DAC6_MIN (33446) + #endif + #endif + + #if (BSP_FEATURE_CTSU_VERSION == 2) + #define CTSU_DIAG_TSCAP_RANGE_LOW (1050) + #define CTSU_DIAG_TSCAP_RANGE_HIGH (1419) + + #define CTSU_CFG_DIAG_LOAD_REISTER_MIN (11951) + #define CTSU_CFG_DIAG_LOAD_REISTER_MAX (23957) + + #define CTSU_CFG_DIAG_CURRENT_SOURCE_DIFF_MIN (2890) + #define CTSU_CFG_DIAG_CURRENT_SOURCE_DIFF_MAX (5703) + + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CFG_DIAG_DAC1_MIN (1486) + #define CTSU_CFG_DIAG_DAC2_MIN (2890) + #define CTSU_CFG_DIAG_DAC3_MIN (4202) + #define CTSU_CFG_DIAG_DAC4_MIN (5448) + #define CTSU_CFG_DIAG_DAC5_MIN (6641) + #define CTSU_CFG_DIAG_DAC6_MIN (7787) + #define CTSU_CFG_DIAG_DAC7_MIN (8891) + #define CTSU_CFG_DIAG_DAC8_MIN (9954) + #define CTSU_CFG_DIAG_DAC9_MIN (10974) + #define CTSU_CFG_DIAG_DAC10_MIN (11951) + #define CTSU_CFG_DIAG_DAC11_MIN (12880) + #define CTSU_CFG_DIAG_DAC12_MIN (13761) + + #define CTSU_CFG_DIAG_DAC1_MAX (3057) + #define CTSU_CFG_DIAG_DAC2_MAX (5703) + #define CTSU_CFG_DIAG_DAC3_MAX (8292) + #define CTSU_CFG_DIAG_DAC4_MAX (10838) + #define CTSU_CFG_DIAG_DAC5_MAX (13269) + #define CTSU_CFG_DIAG_DAC6_MAX (15593) + #define CTSU_CFG_DIAG_DAC7_MAX (17816) + #define CTSU_CFG_DIAG_DAC8_MAX (19948) + #define CTSU_CFG_DIAG_DAC9_MAX (21992) + #define CTSU_CFG_DIAG_DAC10_MAX (23957) + #define CTSU_CFG_DIAG_DAC11_MAX (25843) + #define CTSU_CFG_DIAG_DAC12_MAX (27651) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MIN (1384) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MIN (1293) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MIN (1228) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MIN (1176) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MIN (1129) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MIN (1083) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MIN (1037) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MIN (987) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MIN (929) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MIN (867) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MIN (807) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MAX (2781) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MAX (2678) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MAX (2567) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MAX (2458) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MAX (2355) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MAX (2255) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MAX (2166) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MAX (2077) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MAX (1998) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MAX (1921) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MAX (1841) + #else + + #define CTSU_CFG_DIAG_DAC1_MIN (1039) + #define CTSU_CFG_DIAG_DAC2_MIN (2113) + #define CTSU_CFG_DIAG_DAC3_MIN (3130) + #define CTSU_CFG_DIAG_DAC4_MIN (4108) + #define CTSU_CFG_DIAG_DAC5_MIN (5049) + #define CTSU_CFG_DIAG_DAC6_MIN (5961) + #define CTSU_CFG_DIAG_DAC7_MIN (6848) + #define CTSU_CFG_DIAG_DAC8_MIN (7713) + #define CTSU_CFG_DIAG_DAC9_MIN (8554) + #define CTSU_CFG_DIAG_DAC10_MIN (9374) + #define CTSU_CFG_DIAG_DAC11_MIN (10176) + #define CTSU_CFG_DIAG_DAC12_MIN (10945) + + #define CTSU_CFG_DIAG_DAC1_MAX (2627) + #define CTSU_CFG_DIAG_DAC2_MAX (4899) + #define CTSU_CFG_DIAG_DAC3_MAX (6974) + #define CTSU_CFG_DIAG_DAC4_MAX (8907) + #define CTSU_CFG_DIAG_DAC5_MAX (10729) + #define CTSU_CFG_DIAG_DAC6_MAX (12476) + #define CTSU_CFG_DIAG_DAC7_MAX (14314) + #define CTSU_CFG_DIAG_DAC8_MAX (16089) + #define CTSU_CFG_DIAG_DAC9_MAX (17802) + #define CTSU_CFG_DIAG_DAC10_MAX (19462) + #define CTSU_CFG_DIAG_DAC11_MAX (21067) + #define CTSU_CFG_DIAG_DAC12_MAX (22624) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MIN (1081) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MIN (1013) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MIN (967) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MIN (929) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MIN (899) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MIN (867) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MIN (844) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MIN (821) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MIN (794) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MIN (762) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MIN (733) + + #define CTSU_CFG_DIAG_DAC1_2_DIFF_MAX (2273) + #define CTSU_CFG_DIAG_DAC2_3_DIFF_MAX (2118) + #define CTSU_CFG_DIAG_DAC3_4_DIFF_MAX (2044) + #define CTSU_CFG_DIAG_DAC4_5_DIFF_MAX (1975) + #define CTSU_CFG_DIAG_DAC5_6_DIFF_MAX (1909) + #define CTSU_CFG_DIAG_DAC6_7_DIFF_MAX (1846) + #define CTSU_CFG_DIAG_DAC7_8_DIFF_MAX (1786) + #define CTSU_CFG_DIAG_DAC8_9_DIFF_MAX (1731) + #define CTSU_CFG_DIAG_DAC9_10_DIFF_MAX (1679) + #define CTSU_CFG_DIAG_DAC10_11_DIFF_MAX (1632) + #define CTSU_CFG_DIAG_DAC11_12_DIFF_MAX (1581) + #endif + #define CTSU_CFG_DIAG_CLOCK_RECOV_RANGE (20) + #endif + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_CTSU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dac_cfg.h new file mode 100644 index 0000000000..3db92ccc0a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DAC_CFG_H_ +#define R_DAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dmac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dmac_cfg.h new file mode 100644 index 0000000000..c772854a59 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dmac_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DMAC_CFG_H_ +#define R_DMAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DMAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DMAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_doc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_doc_cfg.h new file mode 100644 index 0000000000..0124272c17 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_doc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DOC_CFG_H_ +#define R_DOC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DOC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DOC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_drw_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_drw_cfg.h new file mode 100644 index 0000000000..7ca818be9a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_drw_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DRW_CFG_H_ +#define R_DRW_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define DRW_CFG_USE_DLIST_INDIRECT ((1)) + #ifdef VECTOR_NUMBER_DRW_INT + #define DRW_CFG_INT_IRQ (VECTOR_NUMBER_DRW_INT) + #endif + #define DRW_CFG_CUSTOM_MALLOC ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_DRW_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dsmif_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dsmif_cfg.h new file mode 100644 index 0000000000..2c656fa920 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dsmif_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DSMIF_CFG_H_ +#define R_DSMIF_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DSMIF_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) +#define DSMIF_CFG_ERROR_DETECTION_SUPPORT ((1)) + +#ifdef __cplusplus +} +#endif +#endif /* R_DSMIF_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dtc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dtc_cfg.h new file mode 100644 index 0000000000..cd2f683dcf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_dtc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME BSP_UNINIT_SECTION_PREFIX ".fsp_dtc_vector_table" + +#ifdef __cplusplus +} +#endif +#endif /* R_DTC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_edmac.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_edmac.h new file mode 100644 index 0000000000..ff59ea997f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_edmac.h @@ -0,0 +1,9 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_EDMAC_H_ +#define R_EDMAC_H_ + +#endif /* R_EDMAC_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_elc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_elc_cfg.h new file mode 100644 index 0000000000..00864564b1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_elc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ELC_CFG_H_ +#define R_ELC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ELC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ELC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ether_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ether_cfg.h new file mode 100644 index 0000000000..34341ea337 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ether_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHER_CFG_H_ +#define R_ETHER_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ETHER_CFG_LINK_PRESENT (0) + #define ETHER_CFG_USE_LINKSTA (0) + #define ETHER_CFG_READ_BUFFER_SIZE_CHECK ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHER_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ether_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ether_phy_cfg.h new file mode 100644 index 0000000000..f84bae1260 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ether_phy_cfg.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHER_PHY_CFG_H_ +#define R_ETHER_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHER_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_DP83620_ENABLE + #define ETHER_PHY_CFG_TARGET_DP83620_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + #define ETHER_PHY_CFG_USE_REF_CLK (BOARD_PHY_REF_CLK) + #define ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHER_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ethercat_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ethercat_phy_cfg.h new file mode 100644 index 0000000000..d9c71487c8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ethercat_phy_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ETHERCAT_PHY_CFG_H_ +#define R_ETHERCAT_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + + #ifdef __cplusplus + } + #endif +#endif /* R_ETHERCAT_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_flash_hp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_flash_hp_cfg.h new file mode 100644 index 0000000000..1aa7941ae2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_flash_hp_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_HP_CFG_H_ +#define R_FLASH_HP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) + #define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_FLASH_HP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_flash_lp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_flash_lp_cfg.h new file mode 100644 index 0000000000..f67c25a7b5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_flash_lp_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_LP_CFG_H_ +#define R_FLASH_LP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (0) + #define FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE 0 + #define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1) + #define FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE (1) + #define FLASH_LP_CFG_DUAL_BANK_INSTANT_SWAP 0 + + #ifdef __cplusplus + } + #endif +#endif /* R_FLASH_LP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_glcdc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_glcdc_cfg.h new file mode 100644 index 0000000000..eea5f0ca27 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_glcdc_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GLCDC_CFG_H_ +#define R_GLCDC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define GLCDC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define GLCDC_CFG_COLOR_CORRECTION_ENABLE (false) + + /* Enable DSI function handling */ + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define GLCDC_CFG_USING_DSI + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_GLCDC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gpt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gpt_cfg.h new file mode 100644 index 0000000000..d7caf17ca7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gpt_cfg.h @@ -0,0 +1,25 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPT_CFG_H_ +#define R_GPT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (1) +#define GPT_CFG_WRITE_PROTECT_ENABLE (0) + +#ifndef BSP_CFG_GPT_COUNT_CLOCK_SOURCE +#define GPT_CFG_GPTCLK_BYPASS (0) +#else +#define GPT_CFG_GPTCLK_BYPASS (BSP_CFG_GPT_COUNT_CLOCK_SOURCE) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* R_GPT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gpt_three_phase_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gpt_three_phase_cfg.h new file mode 100644 index 0000000000..d97d29d768 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gpt_three_phase_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPT_THREE_PHASE_CFG_H_ +#define R_GPT_THREE_PHASE_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_GPT_THREE_PHASE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gptp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gptp_cfg.h new file mode 100644 index 0000000000..f23e684f73 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_gptp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_GPTP_CFG_H_ +#define R_GPTP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define GPTP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_GPTP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_i3c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_i3c_cfg.h new file mode 100644 index 0000000000..1206dbd04a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_i3c_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_I3C_CFG_H_ +#define R_I3C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define I3C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define I3C_CFG_UNALIGNED_BUFFER_SUPPORT (1) +#define I3C_CFG_MASTER_SUPPORT (1) +#define I3C_CFG_SLAVE_SUPPORT (1) +#define I3C_CFG_ERROR_RECOVERY_SUPPORT + +#ifdef __cplusplus +} +#endif +#endif /* R_I3C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_icu_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_icu_cfg.h new file mode 100644 index 0000000000..8422be1b4b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_icu_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ICU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iic_master_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iic_master_cfg.h new file mode 100644 index 0000000000..9485301407 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iic_master_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IIC_MASTER_CFG_H_ +#define R_IIC_MASTER_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_MASTER_CFG_DTC_ENABLE (0) +#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iic_slave_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iic_slave_cfg.h new file mode 100644 index 0000000000..dce97700e0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iic_slave_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IIC_SLAVE_CFG_H_ +#define R_IIC_SLAVE_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_SLAVE_CFG_DTC_ENABLE (0) +#ifdef __cplusplus +} +#endif +#endif /* R_IIC_SLAVE_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iirfa_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iirfa_cfg.h new file mode 100644 index 0000000000..8078ee15be --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iirfa_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IIRFA_CFG_H_ +#define R_IIRFA_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIRFA_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIRFA_CFG_LOOP_UNROLL_DEPTH (1) +#define IIRFA_CFG_LOOP_USE_POLLING (1) +#define IIRFA_CFG_ECC_SUPPORT (1) +#define IIRFA_CFG_ROUNDING_MODE (0) + + +#ifdef __cplusplus +} +#endif +#endif /* R_IIRFA_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ioport_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ioport_cfg.h new file mode 100644 index 0000000000..519ac3734a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ioport_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IOPORT_CFG_CCD_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ipc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ipc_cfg.h new file mode 100644 index 0000000000..7968dbcc75 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ipc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IPC_CFG_H_ +#define R_IPC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define IPC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_IPC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iwdt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iwdt_cfg.h new file mode 100644 index 0000000000..e097d20442 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_iwdt_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_IWDT_CFG_H_ +#define R_IWDT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IWDT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IWDT_CFG_REGISTER_START_NMI_SUPPORTED ((0)) + +#ifdef __cplusplus +} +#endif +#endif /* R_IWDT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_jpeg_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_jpeg_cfg.h new file mode 100644 index 0000000000..9149d6c8fa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_jpeg_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_JPEG_CFG_H_ +#define R_JPEG_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define JPEG_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define JPEG_CFG_DECODE_ENABLE (1) + #define JPEG_CFG_ENCODE_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_JPEG_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_kint_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_kint_cfg.h new file mode 100644 index 0000000000..765da0d361 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_kint_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_KINT_CFG_H_ +#define R_KINT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define KINT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_KINT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_layer3_switch_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_layer3_switch_cfg.h new file mode 100644 index 0000000000..a74af95b70 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_layer3_switch_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LAYER3_SWITCH_CFG_H_ +#define R_LAYER3_SWITCH_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #define LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM (4) + + #define LAYER3_SWITCH_CFG_GPTP_ENABLE (1) + + #define LAYER3_SWITCH_CFG_TAS_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_LAYER3_SWITCH_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_lpm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_lpm_cfg.h new file mode 100644 index 0000000000..be928d2cb6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_lpm_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define LPM_CFG_STANDBY_LIMIT (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_LPM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_lvd_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_lvd_cfg.h new file mode 100644 index 0000000000..c8160e206d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_lvd_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_LVD_CFG_H_ +#define R_LVD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define LVD_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_LVD_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mipi_csi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mipi_csi_cfg.h new file mode 100644 index 0000000000..06ccb51e46 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mipi_csi_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MIPI_CSI_CFG_H_ +#define R_MIPI_CSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MIPI_CSI_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_MIPI_CSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mipi_dsi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mipi_dsi_cfg.h new file mode 100644 index 0000000000..7acc8a1dda --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mipi_dsi_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MIPI_DSI_CFG_H_ +#define R_MIPI_DSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MIPI_DSI_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_MIPI_DSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mram_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mram_cfg.h new file mode 100644 index 0000000000..35aca39883 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_mram_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_MRAM_CFG_H_ +#define R_MRAM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define MRAM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_MRAM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_opamp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_opamp_cfg.h new file mode 100644 index 0000000000..2a4387e532 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_opamp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_OPAMP_CFG_H_ +#define R_OPAMP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define OPAMP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_OPAMP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ospi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ospi_cfg.h new file mode 100644 index 0000000000..fa170f5458 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ospi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_OSPI_CFG_H_ +#define R_OSPI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define OSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define OSPI_CFG_DMAC_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_OSPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_pdc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_pdc_cfg.h new file mode 100644 index 0000000000..509a1e4eb0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_pdc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PDC_CFG_H_ +#define R_PDC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define PDC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_PDC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_pdm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_pdm_cfg.h new file mode 100644 index 0000000000..8a3cd6c1bd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_pdm_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PDM_CFG_H_ +#define R_PDM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define PDM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define PDM_CFG_DMAC_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_PDM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_poeg_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_poeg_cfg.h new file mode 100644 index 0000000000..4bd1a5b99b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_poeg_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_POEG_CFG_H_ +#define R_POEG_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define POEG_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_POEG_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ptp_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ptp_cfg.h new file mode 100644 index 0000000000..81182a841a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ptp_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_PTP_CFG_H_ +#define R_PTP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define PTP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_PTP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_qspi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_qspi_cfg.h new file mode 100644 index 0000000000..663afaefbc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_qspi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_QSPI_CFG_H_ +#define R_QSPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define QSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_QSPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rmac_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rmac_cfg.h new file mode 100644 index 0000000000..b596fd0243 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rmac_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RMAC_CFG_H_ +#define R_RMAC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define RMAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define RMAC_CFG_READ_BUFFER_SIZE_CHECK ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_RMAC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rmac_phy_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rmac_phy_cfg.h new file mode 100644 index 0000000000..3268e93ff5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rmac_phy_cfg.h @@ -0,0 +1,36 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RMAC_PHY_CFG_H_ +#define R_RMAC_PHY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define RMAC_PHY_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifndef ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE + #define ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_DP83620_ENABLE + #define ETHER_PHY_CFG_TARGET_DP83620_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_ICS1894_ENABLE + #define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_TARGET_GPY111_ENABLE + #define ETHER_PHY_CFG_TARGET_GPY111_ENABLE (0) +#endif +#ifndef ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE + #define ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE (0) +#endif + #define ETHER_PHY_CFG_USE_REF_CLK (BOARD_PHY_REF_CLK) + + #ifdef __cplusplus + } + #endif +#endif /* R_RMAC_PHY_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rsip_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rsip_cfg.h new file mode 100644 index 0000000000..ee1670b453 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rsip_cfg.h @@ -0,0 +1,74 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RSIP_CFG_H_ +#define R_RSIP_CFG_H_ +#define RSIP_CFG_ENC_KEY_SIZE(wrappped_key_value_size) (wrappped_key_value_size - 4) + + #define RSIP_CFG_PARAM_CHECKING_ENABLE BSP_CFG_PARAM_CHECKING_ENABLE + #define RSIP_CFG_AES_128_ENABLE (1) + #define RSIP_CFG_AES_192_ENABLE (1) + #define RSIP_CFG_AES_256_ENABLE (1) + #define RSIP_CFG_XTS_AES_128_ENABLE (1) + #define RSIP_CFG_XTS_AES_256_ENABLE (1) + #define RSIP_CFG_AES_ECB_CBC_CTR_ENABLE (1) + #define RSIP_CFG_AES_XTS_ENABLE (1) + #define RSIP_CFG_AES_GCM_ENABLE (1) + #define RSIP_CFG_AES_CCM_ENABLE (1) + #define RSIP_CFG_AES_CMAC_ENABLE (1) + + #define RSIP_CFG_CHACHA20_ENABLE (0) + #define RSIP_CFG_CHACHA20_POLY1305_ENABLE (0) + + #define RSIP_CFG_ECC_SECP256R1_ENABLE (1) + #define RSIP_CFG_ECC_SECP384R1_ENABLE (1) + #define RSIP_CFG_ECC_SECP521R1_ENABLE (1) + #define RSIP_CFG_ECC_SECP256K1_ENABLE (1) + #define RSIP_CFG_ECC_BRAINPOOLP256R1_ENABLE (1) + #define RSIP_CFG_ECC_BRAINPOOLP384R1_ENABLE (1) + #define RSIP_CFG_ECC_BRAINPOOLP512R1_ENABLE (1) + #define RSIP_CFG_ECC_EDWARDS25519_ENABLE (1) + + #define RSIP_CFG_RSA_1024_ENABLE (0) + #define RSIP_CFG_RSA_2048_ENABLE (1) + #define RSIP_CFG_RSA_3072_ENABLE (1) + #define RSIP_CFG_RSA_4096_ENABLE (1) + + #define RSIP_CFG_SHA1_ENABLE (0) + #define RSIP_CFG_SHA224_ENABLE (1) + #define RSIP_CFG_SHA256_ENABLE (1) + #define RSIP_CFG_SHA384_ENABLE (1) + #define RSIP_CFG_SHA512_ENABLE (1) + #define RSIP_CFG_SHA512_224_ENABLE (1) + #define RSIP_CFG_SHA512_256_ENABLE (1) + #define RSIP_CFG_SHA3_224_ENABLE (0) + #define RSIP_CFG_SHA3_256_ENABLE (0) + #define RSIP_CFG_SHA3_384_ENABLE (0) + #define RSIP_CFG_SHA3_512_ENABLE (0) + #define RSIP_CFG_HMAC_SHA1_ENABLE (0) + #define RSIP_CFG_HMAC_SHA224_ENABLE (1) + #define RSIP_CFG_HMAC_SHA256_ENABLE (1) + #define RSIP_CFG_HMAC_SHA384_ENABLE (1) + #define RSIP_CFG_HMAC_SHA512_ENABLE (1) + #define RSIP_CFG_HMAC_SHA512_224_ENABLE (0) + #define RSIP_CFG_HMAC_SHA512_256_ENABLE (0) + + #define RSIP_CFG_KDF_SHA256_ENABLE (1) + #define RSIP_CFG_KDF_SHA384_ENABLE (1) + #define RSIP_CFG_KDF_SHA_ENABLE (RSIP_CFG_KDF_SHA256_ENABLE || RSIP_CFG_KDF_SHA384_ENABLE) + #define RSIP_CFG_KDF_HMAC_SHA256_ENABLE (1) + #define RSIP_CFG_KDF_HMAC_SHA384_ENABLE (1) + #define RSIP_CFG_KDF_HMAC_SHA512_ENABLE (1) + #define RSIP_CFG_KDF_HMAC_ENABLE (RSIP_CFG_KDF_HMAC_SHA256_ENABLE || RSIP_CFG_KDF_HMAC_SHA384_ENABLE || RSIP_CFG_KDF_HMAC_SHA512_ENABLE) + + #define RSIP_CFG_FW_UPDATE_ENABLE (1) + + #define RSIP_CFG_SHA_BUF_BLOCKS (1U) + #define RSIP_CFG_HMAC_BUF_BLOCKS (1U) + + #define RSIP_CFG_WORD_SIZE_ENCRYPTED_KEY_OVERHEAD (4U) + #define RSIP_CFG_WORD_SIZE_WRAPPED_KEY_OVERHEAD (5U) + #define RSIP_CFG_WORD_SIZE_WRAPPED_PUBLIC_KEY_PREFIX (1U) +#endif /* R_RSIP_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rtc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rtc_cfg.h new file mode 100644 index 0000000000..12bff296fb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_rtc_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define RTC_CFG_OPEN_SET_CLOCK_SOURCE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_RTC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_i2c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_i2c_cfg.h new file mode 100644 index 0000000000..cbd57f790b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_i2c_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_I2C_CFG_H_ +#define R_SAU_I2C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_I2C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_I2C_CFG_CRITICAL_SECTION_ENABLE (0) +#define SAU_I2C_CFG_MANUAL_START_STOP_ENABLE (0) +#define SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE config.driver.sau_i2c.single_channel_enable.disabled +#define SAU_I2C_CFG_RESTART_ENABLE (1) +#define SAU_I2C_CFG_DTC_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_I2C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_lin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_lin_cfg.h new file mode 100644 index 0000000000..cccc438932 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_lin_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_LIN_CFG_H_ +#define R_SAU_LIN_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_LIN_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE (1) +#define SAU_LIN_CFG_MASTER_SUPPORT_ENABLE (0) +#define SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE (1) +#define SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE (0) +#define SAU_LIN_AUTO_SYNC_SUPPORT_ENABLE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_LIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_spi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_spi_cfg.h new file mode 100644 index 0000000000..e381c0b8b3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_spi_cfg.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_SPI_CFG_H_ +#define R_SAU_SPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SAU_SPI_CFG_CRITICAL_SECTION_ENABLE (0) +#define SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE config.driver.sau_spi.single_channel_enable.disabled +#define SAU_SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SAU_SPI_TRANSFER_OPERATION_MODE (SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION) +#define SAU_SPI_CFG_DTC_SUPPORT_ENABLE (0) +#define SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE (0) +#define SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_SAU_SPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_uart_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_uart_cfg.h new file mode 100644 index 0000000000..81f1635ccc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sau_uart_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SAU_UART_CFG_H_ +#define R_SAU_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SAU_UART_CFG_CRITICAL_SECTION_ENABLE (0) + #define SAU_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SAU_UART_CFG_DTC_SUPPORT_ENABLE (0) + #define SAU_UART_CFG_SINGLE_CHANNEL config.driver.sau_uart.single_channel.disabled + #define SAU_UART_CFG_FIXED_BAUDRATE_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_SAU_UART_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_b_uart_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_b_uart_cfg.h new file mode 100644 index 0000000000..3550cb0e82 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_b_uart_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_B_UART_CFG_H_ +#define R_SCI_B_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SCI_B_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SCI_B_UART_CFG_FIFO_SUPPORT (1) + #define SCI_B_UART_CFG_DTC_SUPPORTED (0) + #define SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_SCI_B_UART_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_i2c_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_i2c_cfg.h new file mode 100644 index 0000000000..1f4bf5af8e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_i2c_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_I2C_CFG_H_ +#define R_SCI_I2C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_I2C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_I2C_CFG_DTC_ENABLE (0) +#define SCI_I2C_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_I2C_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_lin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_lin_cfg.h new file mode 100644 index 0000000000..88134f91d3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_lin_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_LIN_CFG_H_ +#define R_SCI_LIN_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SCI_LIN_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SCI_LIN_CHECKSUM_SUPPORT_ENABLE (1) + #define SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE (0) + #define SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_SCI_LIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_smci_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_smci_cfg.h new file mode 100644 index 0000000000..39c3ec3d52 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_smci_cfg.h @@ -0,0 +1,15 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_SMCI_CFG_H_ +#define R_SCI_SMCI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define SCI_SMCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_SMCI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_spi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_spi_cfg.h new file mode 100644 index 0000000000..441e96d140 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sci_spi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SCI_SPI_CFG_H_ +#define R_SCI_SPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_SPI_DTC_SUPPORT_ENABLE (1) +#define SCI_SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_SPI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sdadc_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sdadc_cfg.h new file mode 100644 index 0000000000..b54b68020f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sdadc_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SDADC_CFG_H_ +#define R_SDADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SDADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_SDADC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sdhi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sdhi_cfg.h new file mode 100644 index 0000000000..d825b389ef --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_sdhi_cfg.h @@ -0,0 +1,24 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SDHI_CFG_H_ +#define R_SDHI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SDHI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SDMMC_CFG_UNALIGNED_ACCESS_ENABLE (1) + #ifndef SDHI_CFG_SD_SUPPORT_ENABLE + #define SDHI_CFG_SD_SUPPORT_ENABLE ((1)) + #endif + #ifndef SDHI_CFG_EMMC_SUPPORT_ENABLE + #define SDHI_CFG_EMMC_SUPPORT_ENABLE ((0)) + #endif + + #ifdef __cplusplus + } + #endif +#endif /* R_SDHI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_spi_b_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_spi_b_cfg.h new file mode 100644 index 0000000000..3ea8a592ec --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_spi_b_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SPI_B_CFG_H_ +#define R_SPI_B_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SPI_B_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SPI_B_CFG_DMA_SUPPORT_ENABLE (1) + #define SPI_B_TRANSMIT_FROM_RXI_ISR (0) + + /* DEPRECATED: Use SPI_B_CFG_DMA_SUPPORT_ENABLE instead. */ + #define SPI_B_DTC_SUPPORT_ENABLE (SPI_B_CFG_DMA_SUPPORT_ENABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_SPI_B_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ssi_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ssi_cfg.h new file mode 100644 index 0000000000..a6ec1f79e0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ssi_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_SSI_CFG_H_ +#define R_SSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define SSI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SSI_CFG_DTC_ENABLE (1) + + #ifdef __cplusplus + } + #endif +#endif /* R_SSI_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tau_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tau_cfg.h new file mode 100644 index 0000000000..c92f1d8daa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tau_cfg.h @@ -0,0 +1,22 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TAU_CFG_H_ +#define R_TAU_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define TAU_CFG_INTERRUPT_SUPPORT_ENABLE (1) + #define TAU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define TAU_CFG_OUTPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_INPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_EXTRA_INPUT_SUPPORT_ENABLE (0) + #define TAU_CFG_8BIT_MODE_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_TAU_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tau_pwm_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tau_pwm_cfg.h new file mode 100644 index 0000000000..bd9b7f09af --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tau_pwm_cfg.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TAU_PWM_CFG_H_ +#define R_TAU_PWM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define TAU_PWM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE (0) + #define TAU_PWM_CFG_PWM_MODE_ENABLE (1) + #define TAU_PWM_CFG_MULTI_SLAVE_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_TAU_PWM_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tml_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tml_cfg.h new file mode 100644 index 0000000000..d05ca45c63 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_tml_cfg.h @@ -0,0 +1,21 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_TML_CFG_H_ +#define R_TML_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define TML_CFG_CRITICAL_SECTION_ENABLE (0) +#define TML_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define TML_CFG_16_BIT_CAPTURE_MODE_ENABLE (0) +#define TML_CFG_SINGLE_CHANNEL_ENABLE (0) +#define TML_CFG_INTERRUPT_SUPPORT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_TML_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_uarta_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_uarta_cfg.h new file mode 100644 index 0000000000..b57d6dfeb3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_uarta_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_UARTA_CFG_H_ +#define R_UARTA_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define UARTA_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define UARTA_CFG_DTC_SUPPORT_ENABLE + #define UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE 1 + #ifdef __cplusplus + } + #endif +#endif /* R_UARTA_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ulpt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ulpt_cfg.h new file mode 100644 index 0000000000..b931fda89d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_ulpt_cfg.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_ULPT_CFG_H_ +#define R_ULPT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define ULPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define ULPT_CFG_OUTPUT_SUPPORT_ENABLE (0) + #define ULPT_CFG_INPUT_SUPPORT_ENABLE (0) + + #ifdef __cplusplus + } + #endif +#endif /* R_ULPT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_usb_basic_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_usb_basic_cfg.h new file mode 100644 index 0000000000..c62ab39d43 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_usb_basic_cfg.h @@ -0,0 +1,138 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_USB_BASIC_CFG_H_ +#define R_USB_BASIC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #ifndef NULL + extern const uint16_t NULL[]; + #endif + + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #include "r_usb_hcdc_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #define USB_CFG_HCDC_ECM_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HHID_USE + #include "r_usb_hhid_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HMSC_USE + #include "r_usb_hmsc_cfg.h" + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HVND_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HAUD_USE + #endif + #if ((RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED)) + #define USB_CFG_PCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PCDC2_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID2_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PVND_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HUVC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PCDC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PPRN_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PMSC_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PAUD_USE + #endif + #if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_DFU_USE + #endif + #if ((RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED)) + #define USB_CFG_OTG_USE + #endif + #if (defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HPRN_USE) || defined(USB_CFG_HMSC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HVND_USE) || defined(USB_CFG_HUVC_USE) || defined(USB_CFG_HAUD_USE)) + #define USB_CFG_HOST_MODE 1 + #else + #define USB_CFG_HOST_MODE 0 + #endif + + #if (defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE) || defined(USB_CFG_PMSC_USE) || defined(USB_CFG_PHID_USE) || defined(USB_CFG_PVND_USE) || defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE) || defined(USB_CFG_PAUD_USE)) + #define USB_CFG_PERI_MODE 2 + #else + #define USB_CFG_PERI_MODE 0 + #endif + + #define USB_CFG_MODE (USB_CFG_PERI_MODE | USB_CFG_HOST_MODE) + #define USB_CFG_MULTIPORT (USB_CFG_DISABLE) + #define USB_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define USB_CFG_CLKSEL (USB_CFG_24MHZ) + #define USB_CFG_BUSWAIT (USB_CFG_BUSWAIT_0) + #define USB_CFG_BC (USB_CFG_DISABLE) + #define USB_CFG_VBUS (USB_CFG_HIGH) + #define USB_CFG_DCP (USB_CFG_DISABLE) + #define USB_CFG_CLASS_REQUEST (USB_CFG_ENABLE) + #define USB_CFG_DBLB (USB_CFG_DBLBON) + #define USB_CFG_CNTMD (USB_CFG_CNTMDOFF) + #define USB_CFG_LDO_REGULATOR (USB_CFG_DISABLE) + #define USB_CFG_TYPEC_FEATURE (RA_NOT_DEFINED) + #define USB_CFG_DMA_DTC_DISABLED (USB_CFG_ENABLE) + #define USB_CFG_TPLCNT (1) + #define USB_CFG_TPL USB_NOVENDOR, USB_NOPRODUCT + #define USB_CFG_TPL_TABLE NULL + #define USB_CFG_COMPLIANCE (USB_CFG_DISABLE) + + #ifdef __cplusplus + } + #endif +#endif /* R_USB_BASIC_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_vin_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_vin_cfg.h new file mode 100644 index 0000000000..816207c8d4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_vin_cfg.h @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_VIN_CFG_H_ +#define R_VIN_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define VIN_CFG_PARAM_CHECKING_ENABLE ((BSP_CFG_PARAM_CHECKING_ENABLE)) + + #ifdef __cplusplus + } + #endif +#endif /* R_VIN_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_wdt_cfg.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_wdt_cfg.h new file mode 100644 index 0000000000..0d10d3f68a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/r_wdt_cfg.h @@ -0,0 +1,18 @@ +/* Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* generated configuration header file - do not edit */ +#ifndef R_WDT_CFG_H_ +#define R_WDT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #define WDT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define WDT_CFG_REGISTER_START_NMI_SUPPORTED ((0)) + + #ifdef __cplusplus + } + #endif +#endif /* R_WDT_CFG_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/uart_device.c b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/uart_device.c new file mode 100644 index 0000000000..b31cc7158a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/uart_device.c @@ -0,0 +1,16 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "PeripheralNames.h" +#include "hal_data.h" +#include "device.h" + +const uart_instance_t * const g_uart_instances[UART_COUNT] = { + &g_uart0, + &g_uart1, + &g_uart2, + &g_uart3, + &g_uart4, + &g_uart9, +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/us_ticker_data.h b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/us_ticker_data.h new file mode 100644 index 0000000000..0b4199e242 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/TARGET_RA8E1/us_ticker_data.h @@ -0,0 +1,28 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __US_TICKER_DATA_H +#define __US_TICKER_DATA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define US_TICKER_CLOCK_HZ (15000000UL) +#define US_TICKER_CLOCK_BITS (32) +#define US_TICKER_VAR g_timer_gpt1 +#define US_TICKER_INSTANCE R_GPT1 +#define US_TICKER_IRQ GPT1_CAPTURE_COMPARE_A_IRQn + +/* RA8E1 devices have 15MHz us_ticker */ +#define US_TICKER_PERIOD_NUM 1 +#define US_TICKER_PERIOD_DEN 15 + +#ifdef __cplusplus +} +#endif + +#endif // __US_TICKER_DATA_H + diff --git a/targets/TARGET_RENESAS/TARGET_RA/analog_api.c b/targets/TARGET_RENESAS/TARGET_RA/analog_api.c new file mode 100644 index 0000000000..5d3fb0d90b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/analog_api.c @@ -0,0 +1,118 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "analogin_api.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "hal_data.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#if (BSP_PERIPHERAL_ADC_PRESENT && BSP_PERIPHERAL_ADC_CHANNEL_MASK == 0x3U) || \ + (BSP_PERIPHERAL_ADC_B_PRESENT && BSP_PERIPHERAL_ADC_B_CHANNEL_MASK == 0x3U) || \ + (BSP_PERIPHERAL_ADC_D_PRESENT && BSP_PERIPHERAL_ADC_D_CHANNEL_MASK == 0x3U) +#define HAS_ADC1 1 +#endif + +static bool g_adc_initialized = false; + +static void mbed_adc_init_once(void) +{ + if (g_adc_initialized) { + return; + } + + fsp_err_t err; + + err = R_ADC_Open(&g_adc0_ctrl, &g_adc0_cfg); + MBED_ASSERT(err == FSP_SUCCESS); + + err = R_ADC_ScanCfg(&g_adc0_ctrl, &g_adc0_channel_cfg); + MBED_ASSERT(err == FSP_SUCCESS); + +#ifdef HAS_ADC1 + err = R_ADC_Open(&g_adc1_ctrl, &g_adc1_cfg); + MBED_ASSERT(err == FSP_SUCCESS); + + err = R_ADC_ScanCfg(&g_adc1_ctrl, &g_adc1_channel_cfg); + MBED_ASSERT(err == FSP_SUCCESS); +#endif + + g_adc_initialized = true; +} + +void analogin_init(analogin_t *obj, PinName pin) +{ + MBED_ASSERT(obj); + + mbed_adc_init_once(); + + uint32_t peripheral = pinmap_peripheral(pin, PinMap_ADC); + + obj->pin = pin; + obj->peripheral = peripheral; + uint32_t function = pinmap_function(pin, PinMap_ADC); + pin_function(pin, function); + obj->channel = RA_PIN_CHANNEL(function); +} + +void analogin_free(analogin_t *obj) +{ + pin_mode(obj->pin, PullNone); + + obj->pin = NC; + obj->peripheral = 0; + obj->channel = 0; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = analogin_read_u16(obj); + return (float)value / 65535.0f; +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + adc_status_t status; + uint16_t adc_value = 0; + + if(obj->peripheral == ADC_0) + { + fsp_err_t err = R_ADC_ScanStart(&g_adc0_ctrl); + MBED_ASSERT(err == FSP_SUCCESS); + + do { + R_ADC_StatusGet(&g_adc0_ctrl, &status); + } while (status.state != ADC_STATE_IDLE); + + err = R_ADC_Read(&g_adc0_ctrl, (adc_channel_t) obj->channel, &adc_value); + MBED_ASSERT(err == FSP_SUCCESS); + } +#ifdef HAS_ADC1 + else if(obj->peripheral == ADC_1) + { + fsp_err_t err = R_ADC_ScanStart(&g_adc1_ctrl); + MBED_ASSERT(err == FSP_SUCCESS); + + do { + R_ADC_StatusGet(&g_adc1_ctrl, &status); + } while (status.state != ADC_STATE_IDLE); + + err = R_ADC_Read(&g_adc1_ctrl, (adc_channel_t) obj->channel, &adc_value); + MBED_ASSERT(err == FSP_SUCCESS); + } +#endif + // Extend from 12bits to 16bits + return (adc_value << 4); +} + +PinName analogin_pin(analogin_t *obj) +{ + return obj->pin; +} + +const PinMap *analogin_pinmap(void) +{ + return PinMap_ADC; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/analogout_api.c b/targets/TARGET_RENESAS/TARGET_RA/analogout_api.c new file mode 100644 index 0000000000..e335114845 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/analogout_api.c @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "analogout_api.h" +#include "pinmap.h" +#include "mbed_assert.h" +#include "r_dac.h" +#include "r_dac_api.h" +#include "PeripheralPins.h" + +static dac_instance_ctrl_t dac_ctrls[2]; + +void dac_init(dac_t *obj, PinName pin) +{ + MBED_ASSERT(obj); + + int ch = pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(ch != NC); + + obj->channel = ch; + obj->ctrl = &dac_ctrls[ch]; + + pinmap_pinout(pin, PinMap_DAC); + + obj->ext_cfg.enable_charge_pump = true; + obj->ext_cfg.output_amplifier_enabled = true; + obj->ext_cfg.internal_output_enabled = false; + obj->ext_cfg.data_format = DAC_DATA_FORMAT_FLUSH_RIGHT; + obj->ext_cfg.ref_volt_sel = DAC_VREF_VREFH_VREFL; + + obj->cfg.channel = ch; + obj->cfg.ad_da_synchronized = false; + obj->cfg.p_extend = &obj->ext_cfg; + + R_DAC_Open(obj->ctrl, &obj->cfg); + + obj->last_value = 0; + R_DAC_Write(obj->ctrl, 0); + + R_DAC_Start(obj->ctrl); +} + +void dac_free(dac_t *obj) +{ +} + +void dac_write_u16(dac_t *obj, uint16_t value) +{ + obj->last_value = value; + + uint16_t dac_val = value >> 4; + + R_DAC_Write(obj->ctrl, dac_val); +} + +uint16_t dac_read_u16(dac_t *obj) +{ + return obj->last_value; +} + +void dac_write(dac_t *obj, float value) +{ + if (value < 0.0f) value = 0.0f; + if (value > 1.0f) value = 1.0f; + + uint16_t v = (uint16_t)(value * 65535.0f); + dac_write_u16(obj, v); +} + +float dac_read(dac_t *obj) +{ + return dac_read_u16(obj) / 65535.0f; +} + +const PinMap *analogout_pinmap() +{ + return PinMap_DAC; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/can_api.c b/targets/TARGET_RENESAS/TARGET_RA/can_api.c new file mode 100644 index 0000000000..95ad4698ba --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/can_api.c @@ -0,0 +1,681 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "can_api.h" +#include "pinmap.h" + +#ifdef DEVICE_CAN + +#ifdef DEVICE_CAN_FD +#include "r_canfd.h" +#else +#include "r_can.h" +#endif + +static can_irq_handler irq_handler; + +extern const can_instance_t *const g_can_instances[]; + +#define MBED_CAN_MAILBOX_TX 0 + +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; + +const PinMap *can_rd_pinmap(void) +{ + return PinMap_CAN_RD; +} + +const PinMap *can_td_pinmap(void) +{ + return PinMap_CAN_TD; +} + +static const can_instance_t *can_instance_from_pins(PinName rd, PinName td, int *peripheral_index) +{ + int per_rd = (int) pinmap_peripheral(rd, PinMap_CAN_RD); + int per_td = (int) pinmap_peripheral(td, PinMap_CAN_TD); + int per = (int) pinmap_merge(per_rd, per_td); + + if (per == (int) NC) { + return NULL; + } + + if (peripheral_index) { + *peripheral_index = per; + } + + return g_can_instances[per]; +} + +static void can_configure_pins_from_pins(PinName rd, PinName td) +{ + int func_rd = (int) pinmap_function(rd, PinMap_CAN_RD); + int func_td = (int) pinmap_function(td, PinMap_CAN_TD); + + pin_function(rd, func_rd); + pin_function(td, func_td); +} + +#ifdef DEVICE_CAN_FD +static void canfd_default_accept_all(const canfd_extended_cfg_t *ext) +{ + canfd_afl_entry_t *afl = (canfd_afl_entry_t *) ext->p_afl; + + afl[0].id.id = 0; + afl[0].id.id_mode = CAN_ID_MODE_STANDARD; + afl[0].id.frame_type = CAN_FRAME_TYPE_DATA; + + afl[0].mask.mask_id = 0; + afl[0].mask.mask_id_mode = 0; + afl[0].mask.mask_frame_type = 0; + + afl[0].destination.minimum_dlc = 0; + afl[0].destination.fifo_select_flags = CANFD_RX_FIFO_0; +} + +static uint32_t canfd_get_clock_div(uint32_t div_macro_value) +{ + switch(div_macro_value) + { + case BSP_CLOCKS_CANFD_CLOCK_DIV_1: + return 1; + case BSP_CLOCKS_CANFD_CLOCK_DIV_2: + return 2; + case BSP_CLOCKS_CANFD_CLOCK_DIV_3: + return 3; + case BSP_CLOCKS_CANFD_CLOCK_DIV_4: + return 4; + case BSP_CLOCKS_CANFD_CLOCK_DIV_5: + return 5; + case BSP_CLOCKS_CANFD_CLOCK_DIV_6: + return 6; + case BSP_CLOCKS_CANFD_CLOCK_DIV_8: + return 8; + case BSP_CLOCKS_CANFD_CLOCK_DIV_10: + return 10; + case BSP_CLOCKS_CANFD_CLOCK_DIV_16: + return 16; + case BSP_CLOCKS_CANFD_CLOCK_DIV_32: + return 32; + } + return 1; +} +#endif + +/* ---------------- Mbed API ---------------- */ + +void can_init(can_t *obj, PinName rd, PinName td) +{ + can_init_freq(obj, rd, td, 100000 +#ifdef DEVICE_CAN_FD + , 0 +#endif + ); +} + +void can_init_direct(can_t *obj, const can_pinmap_t *pinmap) +{ + can_init_freq_direct(obj, pinmap, 100000 +#ifdef DEVICE_CAN_FD + , 0 +#endif + ); +} + +void can_init_freq(can_t *obj, PinName rd, PinName td, int hz +#ifdef DEVICE_CAN_FD + , int data_hz +#endif + ) +{ + MBED_ASSERT(obj); + + int per_index = -1; + const can_instance_t *inst = can_instance_from_pins(rd, td, &per_index); + MBED_ASSERT(inst != NULL); + + can_configure_pins_from_pins(rd, td); + + obj->instance = inst; + obj->irq_context = 0; + obj->hz = hz; +#ifdef DEVICE_CAN_FD + obj->data_hz = data_hz; + canfd_default_accept_all((const canfd_extended_cfg_t*)inst->p_cfg->p_extend); +#endif + + const can_cfg_t *cfg_rom = (const can_cfg_t *) inst->p_cfg; + obj->cfg_copy = *cfg_rom; + obj->cfg_copy.p_context = obj; + + fsp_err_t err = obj->instance->p_api->open(obj->instance->p_ctrl, &obj->cfg_copy); + MBED_ASSERT(FSP_SUCCESS == err); + + (void) can_frequency(obj, hz +#ifdef DEVICE_CAN_FD + , data_hz +#endif + ); +} + +void can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz +#ifdef DEVICE_CAN_FD + , int data_hz +#endif + ) +{ + MBED_ASSERT(obj); + MBED_ASSERT(pinmap); + + int per = pinmap->peripheral; + + pin_function(pinmap->rd_pin, pinmap->rd_function); + pin_function(pinmap->td_pin, pinmap->td_function); + + const can_instance_t *inst = g_can_instances[per]; + + obj->instance = inst; + obj->irq_context = 0; + obj->hz = hz; +#ifdef DEVICE_CAN_FD + obj->data_hz = data_hz; + canfd_default_accept_all((const canfd_extended_cfg_t*)inst->p_cfg->p_extend); +#endif + + const can_cfg_t *cfg_rom = (const can_cfg_t *) inst->p_cfg; + obj->cfg_copy = *cfg_rom; + + fsp_err_t err = obj->instance->p_api->open(obj->instance->p_ctrl, &obj->cfg_copy); + MBED_ASSERT(FSP_SUCCESS == err); + + (void) can_frequency(obj, hz +#ifdef DEVICE_CAN_FD + , data_hz +#endif + ); +} + +void can_free(can_t *obj) +{ + if (!obj || !obj->instance) { + return; + } + + (void) obj->instance->p_api->close(obj->instance->p_ctrl); + obj->instance = NULL; + obj->irq_context = 0; +} + +static int calc_bit_timing(uint32_t canclk, uint32_t bitrate, + can_bit_timing_cfg_t *out, + float sample_point) +{ + if (bitrate == 0 || canclk == 0) return 0; + +/* ==================== 1. Define Hardware Limits ==================== */ +#ifdef DEVICE_CAN_FD + /* CAN FD (Nominal Bit Timing Hardware Specifications) */ + const uint32_t min_total_tq = 8; + const uint32_t max_total_tq = 256; + const uint32_t min_tseg1 = 2; + const uint32_t max_tseg1 = 255; + const uint32_t min_tseg2 = 1; + const uint32_t max_tseg2 = 127; + const uint32_t max_sjw = 128; + const uint32_t max_brp = 1024; +#else + /* Classic CAN (e.g., RA4E1 R_CAN Hardware Specifications) */ + const uint32_t min_total_tq = 8; + const uint32_t max_total_tq = 25; + const uint32_t min_tseg1 = 4; + const uint32_t max_tseg1 = 16; + const uint32_t min_tseg2 = 2; + const uint32_t max_tseg2 = 8; + const uint32_t max_sjw = 4; + const uint32_t max_brp = 1024; +#endif + +/* ==================== 2. Bit Timing Calculation Logic ==================== */ + uint32_t best_prescaler = 0; + uint32_t best_tseg1 = 0; + uint32_t best_tseg2 = 0; + float min_error = 1.0f; + + for (uint32_t total_tq = min_total_tq; total_tq <= max_total_tq; total_tq++) { + // Must be evenly divisible to ensure zero baud rate error + if ((canclk % (bitrate * total_tq)) != 0) { + continue; + } + + uint32_t prescaler = canclk / (bitrate * total_tq); + if (prescaler < 1 || prescaler > max_brp) { + continue; + } + + // Calculate TSEG1 based on formula: Sample Point = (1 + TSEG1) / total_tq + uint32_t tseg1 = (uint32_t)((total_tq * sample_point) - 1.0f + 0.5f); + + // Clamp TSEG1 within current hardware limits + if (tseg1 < min_tseg1) tseg1 = min_tseg1; + if (tseg1 > max_tseg1) tseg1 = max_tseg1; + + if (total_tq <= (1 + tseg1)) continue; // Prevent underflow in unsigned subtraction + uint32_t tseg2 = total_tq - 1 - tseg1; + + // Validate whether TSEG2 is within hardware limits + if (tseg2 < min_tseg2 || tseg2 > max_tseg2) { + continue; + } + + // Calculate deviation between actual and target sample point + float actual_sp = (float)(1 + tseg1) / (float)total_tq; + float error = (actual_sp > sample_point) ? (actual_sp - sample_point) : (sample_point - actual_sp); + + if (error < min_error) { + min_error = error; + best_prescaler = prescaler; + best_tseg1 = tseg1; + best_tseg2 = tseg2; + } + } + + // Return failure if no valid configuration matching hardware limits was found + if (best_prescaler == 0) { + return 0; + } + + out->baud_rate_prescaler = (uint16_t)best_prescaler; + out->time_segment_1 = (uint8_t)best_tseg1; + out->time_segment_2 = (uint8_t)best_tseg2; + + // SJW must not exceed TSEG2 nor the maximum hardware limit max_sjw + uint32_t sjw = (best_tseg2 > max_sjw) ? max_sjw : best_tseg2; + out->synchronization_jump_width = (uint8_t)sjw; + + return 1; +} + +int can_frequency(can_t *obj, int hz +#ifdef DEVICE_CAN_FD + , int data_hz +#endif + ) +{ + MBED_ASSERT(obj); + MBED_ASSERT(obj->instance); + + obj->instance->p_api->close(obj->instance->p_ctrl); + +#ifdef DEVICE_CAN_FD + // Use CANFDCLK for CAN FD clock source + uint32_t canclk = R_BSP_SourceClockHzGet(BSP_CFG_CANFDCLK_SOURCE) / canfd_get_clock_div(BSP_CFG_CANFDCLK_DIV) ; +#else + // Use PCLKB for CAN clock source + uint32_t canclk = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); +#endif + + if (!calc_bit_timing(canclk, hz, obj->cfg_copy.p_bit_timing, 0.875f)) { + return 0; + } + + obj->hz = hz; +#ifdef DEVICE_CAN_FD + canfd_extended_cfg_t *ext_rom = (canfd_extended_cfg_t *) obj->cfg_copy.p_extend; + + obj->data_hz = data_hz; + if (data_hz > 0) { + if (!calc_bit_timing(canclk, data_hz, ext_rom->p_data_timing, 0.625f)) { + return 0; + } + } +#endif + + fsp_err_t err = obj->instance->p_api->open(obj->instance->p_ctrl, &obj->cfg_copy); + return (err == FSP_SUCCESS); +} + +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) +{ + MBED_ASSERT(obj); + irq_handler = handler; + obj->irq_context = context; +} + +void can_irq_free(can_t *obj) +{ + if (!obj) { + return; + } + obj->irq_context = 0; +} + +void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) +{ + MBED_ASSERT(obj); + FSP_PARAMETER_NOT_USED(irq); + FSP_PARAMETER_NOT_USED(enable); +} + +static void mbed_to_can_frame(const CAN_Message *msg, can_frame_t *frame) +{ + frame->id = msg->id; + frame->id_mode = (msg->format == CANExtended) ? CAN_ID_MODE_EXTENDED : CAN_ID_MODE_STANDARD; + frame->type = (msg->type == CANRemote) ? CAN_FRAME_TYPE_REMOTE : CAN_FRAME_TYPE_DATA; + frame->data_length_code = msg->len; + frame->options = 0; + for (int i = 0; i < msg->len && i < 8; i++) { + frame->data[i] = msg->data[i]; + } +} + +static void can_frame_to_mbed(const can_frame_t *frame, CAN_Message *msg) +{ + msg->id = frame->id; + msg->format = (frame->id_mode == CAN_ID_MODE_EXTENDED) ? CANExtended : CANStandard; + msg->type = (frame->type == CAN_FRAME_TYPE_REMOTE) ? CANRemote : CANData; + msg->len = frame->data_length_code; + for (int i = 0; i < msg->len && i < 8; i++) { + msg->data[i] = frame->data[i]; + } +} + +int can_write(can_t *obj, CAN_Message msg) +{ + MBED_ASSERT(obj); + MBED_ASSERT(obj->instance); + + can_frame_t frame; + mbed_to_can_frame(&msg, &frame); + + fsp_err_t err = obj->instance->p_api->write(obj->instance->p_ctrl, MBED_CAN_MAILBOX_TX, &frame); + + return (err == FSP_SUCCESS) ? 1 : 0; +} + +int can_read(can_t *obj, CAN_Message *msg, int handle) +{ + FSP_PARAMETER_NOT_USED(handle); + + if (obj->rx_head == obj->rx_tail) { + return 0; // no data + } + + can_frame_t *f = &obj->rx_queue[obj->rx_tail]; + obj->rx_tail = (obj->rx_tail + 1) % MBED_CAN_RX_QUEUE_SIZE; + + can_frame_to_mbed(f, msg); + return 1; +} + + +int can_mode(can_t *obj, CanMode mode) +{ + MBED_ASSERT(obj); + MBED_ASSERT(obj->instance); + + can_operation_mode_t op_mode = CAN_OPERATION_MODE_NORMAL; + can_test_mode_t test_mode = CAN_TEST_MODE_DISABLED; + + switch (mode) { + + case MODE_RESET: + op_mode = CAN_OPERATION_MODE_RESET; + test_mode = CAN_TEST_MODE_DISABLED; + break; + + case MODE_NORMAL: + op_mode = CAN_OPERATION_MODE_NORMAL; + test_mode = CAN_TEST_MODE_DISABLED; + break; + + case MODE_SILENT: + op_mode = CAN_OPERATION_MODE_NORMAL; + test_mode = CAN_TEST_MODE_LISTEN; + break; + + case MODE_TEST_LOCAL: + op_mode = CAN_OPERATION_MODE_NORMAL; + test_mode = CAN_TEST_MODE_LOOPBACK_INTERNAL; + break; + + case MODE_TEST_GLOBAL: + op_mode = CAN_OPERATION_MODE_NORMAL; + test_mode = CAN_TEST_MODE_LOOPBACK_EXTERNAL; + break; + + case MODE_TEST_SILENT: + op_mode = CAN_OPERATION_MODE_NORMAL; + test_mode = CAN_TEST_MODE_LISTEN; + break; + + default: + return 0; + } + + fsp_err_t err = obj->instance->p_api->modeTransition( + obj->instance->p_ctrl, + op_mode, + test_mode + ); + + return (err == FSP_SUCCESS) ? 1 : 0; +} + +#ifdef DEVICE_CAN_FD + +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) +{ + MBED_ASSERT(obj); + + obj->instance->p_api->close(obj->instance->p_ctrl); + + const can_instance_t *inst = obj->instance; + const can_cfg_t *cfg = inst->p_cfg; + canfd_extended_cfg_t *ext = (canfd_extended_cfg_t *) cfg->p_extend; + + canfd_afl_entry_t *afl = (canfd_afl_entry_t *) ext->p_afl; + int32_t rule_num = CANFD_CFG_AFL_CH0_RULE_NUM; + int32_t idx = (handle >= 0 && handle < rule_num) ? handle : 0; + + afl[idx].id.id = id; + afl[idx].id.frame_type = CAN_FRAME_TYPE_DATA; + afl[idx].id.id_mode = (format == CANStandard ? CAN_ID_MODE_STANDARD: CAN_ID_MODE_EXTENDED); + afl[idx].mask.mask_id = mask; + afl[idx].mask.mask_id_mode = (format == CANExtended) ? CAN_ID_MODE_EXTENDED : CAN_ID_MODE_STANDARD; + afl[idx].mask.mask_frame_type = CAN_FRAME_TYPE_DATA; + afl[idx].destination.minimum_dlc = 0; + afl[idx].destination.fifo_select_flags = CANFD_RX_FIFO_0; + + fsp_err_t err = obj->instance->p_api->open(obj->instance->p_ctrl, &obj->cfg_copy); + return (err == FSP_SUCCESS) ? idx : 0; +} + +#else + +int classic_can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) +{ + MBED_ASSERT(obj); + + const can_instance_t *inst = obj->instance; + const can_cfg_t *cfg = inst->p_cfg; + can_extended_cfg_t *ext = (can_extended_cfg_t *) cfg->p_extend; + + /* 1. close CAN */ + inst->p_api->close(inst->p_ctrl); + + /* 2. mailbox index（mailbox 0 is usually used by TX，so starting from 1） */ + uint32_t mb_count = ext->mailbox_count; + uint32_t mb = (handle >= 1 && handle < (int32_t) mb_count) ? handle : 1; + + /* 3. configure mailbox */ + can_mailbox_t *mbox = &ext->p_mailbox[mb]; + + mbox->mailbox_id = id; + mbox->id_mode = (format == CANStandard) ? CAN_ID_MODE_STANDARD : CAN_ID_MODE_EXTENDED; + mbox->frame_type = CAN_FRAME_TYPE_DATA; + mbox->mailbox_type = CAN_MAILBOX_RECEIVE; + + /* 4. set mask（each mask shared by 4 mailboxes） */ + uint32_t group = mb / 4; + ext->p_mailbox_mask[group] = mask; + + /* 5. reopen CAN */ + fsp_err_t err = inst->p_api->open(inst->p_ctrl, &obj->cfg_copy); + return (err == FSP_SUCCESS) ? mb : 0; +} + +#endif + +void can_reset(can_t *obj) +{ + (void) can_mode(obj, MODE_RESET); + (void) can_mode(obj, MODE_NORMAL); +} + +unsigned char can_rderror(can_t *obj) +{ + MBED_ASSERT(obj); + can_info_t info; + if (obj->instance->p_api->infoGet(obj->instance->p_ctrl, &info) != FSP_SUCCESS) { + return 0; + } + return (unsigned char) info.error_count_receive; +} + +unsigned char can_tderror(can_t *obj) +{ + MBED_ASSERT(obj); + can_info_t info; + if (obj->instance->p_api->infoGet(obj->instance->p_ctrl, &info) != FSP_SUCCESS) { + return 0; + } + return (unsigned char) info.error_count_transmit; +} + +void can_monitor(can_t *obj, int silent) +{ + if (silent) { + (void) can_mode(obj, MODE_SILENT); + } else { + (void) can_mode(obj, MODE_NORMAL); + } +} + +#ifdef DEVICE_CAN_FD + +static void mbed_to_canfd_frame(const CANFD_Message *msg, can_frame_t *frame, bool need_brs) +{ + frame->id = msg->id; + frame->id_mode = (msg->format == CANExtended) ? CAN_ID_MODE_EXTENDED : CAN_ID_MODE_STANDARD; + frame->type = (msg->type == CANRemote) ? CAN_FRAME_TYPE_REMOTE : CAN_FRAME_TYPE_DATA; + frame->data_length_code = msg->len; + frame->options = CANFD_FRAME_OPTION_FD | (need_brs ? CANFD_FRAME_OPTION_BRS: 0); + for (int i = 0; i < msg->len && i < 64; i++) { + frame->data[i] = msg->data[i]; + } +} + +static void canfd_frame_to_mbed(const can_frame_t *frame, CANFD_Message *msg) +{ + msg->id = frame->id; + msg->format = (frame->id_mode == CAN_ID_MODE_EXTENDED) ? CANExtended : CANStandard; + msg->type = (frame->type == CAN_FRAME_TYPE_REMOTE) ? CANRemote : CANData; + msg->len = frame->data_length_code; + for (int i = 0; i < msg->len && i < 64; i++) { + msg->data[i] = frame->data[i]; + } +} + +int canfd_write(can_t *obj, CANFD_Message msg) +{ + MBED_ASSERT(obj); + MBED_ASSERT(obj->instance); + + can_frame_t frame; + mbed_to_canfd_frame(&msg, &frame, obj->hz != obj->data_hz); + + const can_api_t *fd_api = (const can_api_t *) obj->instance->p_api; + fsp_err_t err = fd_api->write(obj->instance->p_ctrl, MBED_CAN_MAILBOX_TX, &frame); + return (err == FSP_SUCCESS) ? 1 : 0; +} + +int canfd_read(can_t *obj, CANFD_Message *msg, int handle) +{ + FSP_PARAMETER_NOT_USED(handle); + + if (obj->rx_head == obj->rx_tail) { + return 0; + } + + can_frame_t *f = &obj->rx_queue[obj->rx_tail]; + obj->rx_tail = (obj->rx_tail + 1) % MBED_CAN_RX_QUEUE_SIZE; + + canfd_frame_to_mbed(f, msg); + return 1; +} + +#endif /* DEVICE_CAN_FD */ + +void can_callback(can_callback_args_t *p_args) +{ + can_t *obj = (can_t *) p_args->p_context; + + if (!obj) return; + + switch (p_args->event) { + + case CAN_EVENT_RX_COMPLETE: + { + uint8_t next = (obj->rx_head + 1) % MBED_CAN_RX_QUEUE_SIZE; + + if (next == obj->rx_tail) { + obj->rx_tail = (obj->rx_tail + 1) % MBED_CAN_RX_QUEUE_SIZE; + } + + obj->rx_queue[obj->rx_head] = p_args->frame; + obj->rx_head = next; + + if (irq_handler) { + irq_handler(obj->irq_context, IRQ_RX); + } + break; + } + + case CAN_EVENT_TX_COMPLETE: + if (irq_handler) { + irq_handler(obj->irq_context, IRQ_TX); + } + break; + + case CAN_EVENT_ERR_CHANNEL: + /* Reset channel */ + obj->instance->p_api->modeTransition(obj->instance->p_ctrl, + CAN_OPERATION_MODE_GLOBAL_RESET, + CAN_TEST_MODE_DISABLED); + /* Back to operation */ + obj->instance->p_api->modeTransition(obj->instance->p_ctrl, + CAN_OPERATION_MODE_GLOBAL_OPERATION, + CAN_TEST_MODE_DISABLED); + if (irq_handler) { + irq_handler(obj->irq_context, IRQ_ERROR); + } + break; + case CAN_EVENT_BUS_RECOVERY: + case CAN_EVENT_ERR_PASSIVE: + case CAN_EVENT_ERR_WARNING: + case CAN_EVENT_ERR_BUS_OFF: + if (irq_handler) { + irq_handler(obj->irq_context, IRQ_ERROR); + } + break; + + default: + break; + } +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/cmsis.h b/targets/TARGET_RENESAS/TARGET_RA/cmsis.h new file mode 100644 index 0000000000..43b12e04b7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/cmsis.h @@ -0,0 +1,12 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "bsp_api.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/cmsis_nvic.h b/targets/TARGET_RENESAS/TARGET_RA/cmsis_nvic.h new file mode 100644 index 0000000000..5679039544 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/cmsis_nvic.h @@ -0,0 +1,23 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef CMSIS_NVIC_H +#define CMSIS_NVIC_H + +#include + +#include "vector_data.h" // FSP generated + +/* Cortex-M has 16 system exceptions */ +#define NVIC_NUM_SYSTEM_EXCEPTIONS (16) + +/* Total number of vectors = system exceptions + IRQs */ +#define NVIC_NUM_VECTORS (NVIC_NUM_SYSTEM_EXCEPTIONS + VECTOR_DATA_IRQ_COUNT) + +extern uint32_t __vector_ram_start__; + +#define NVIC_RAM_VECTOR_ADDRESS (uint32_t *)&__vector_ram_start__ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/crc_api.c b/targets/TARGET_RENESAS/TARGET_RA/crc_api.c new file mode 100644 index 0000000000..bab6b1e3b5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/crc_api.c @@ -0,0 +1,155 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "crc_api.h" +#include "r_crc.h" +#include "hal_data.h" + +static crc_instance_ctrl_t g_crc_ctrl; +static crc_cfg_t g_crc_cfg = +{ + .polynomial = CRC_POLYNOMIAL_CRC_32, + .bit_order = CRC_BIT_ORDER_LMS_LSB, + .snoop_address = 0, + .p_extend = NULL, +}; + +static uint32_t g_crc_state = 0; +static uint32_t g_crc_initial = 0; +static uint32_t g_crc_final_xor = 0; +static bool g_crc_reflect_out = false; +static bool g_crc_reflect_in = false; +static uint8_t g_crc_width = 32; + +static uint32_t reflect_bits(uint32_t data, uint8_t width) +{ + uint32_t out = 0; + for (uint8_t i = 0; i < width; i++) + { + out <<= 1; + out |= (data & 1); + data >>= 1; + } + return out; +} + +void hal_crc_compute_partial_start(const crc_mbed_config_t *config) +{ + g_crc_initial = config->initial_xor; + g_crc_final_xor = config->final_xor; + g_crc_reflect_out = config->reflect_out; + g_crc_reflect_in = config->reflect_in; + g_crc_width = config->width; + + uint32_t mask = (g_crc_width == 32) ? 0xFFFFFFFFUL : ((1UL << g_crc_width) - 1); + g_crc_initial &= mask; + + switch (config->polynomial) + { + case POLY_8BIT_CCITT: + g_crc_cfg.polynomial = CRC_POLYNOMIAL_CRC_8; + break; + case POLY_16BIT_IBM: + g_crc_cfg.polynomial = CRC_POLYNOMIAL_CRC_16; + break; + case POLY_16BIT_CCITT: + g_crc_cfg.polynomial = CRC_POLYNOMIAL_CRC_CCITT; + break; + case POLY_32BIT_ANSI: + default: + g_crc_cfg.polynomial = CRC_POLYNOMIAL_CRC_32; + break; + } + + g_crc_cfg.bit_order = config->reflect_in ? + CRC_BIT_ORDER_LMS_LSB : + CRC_BIT_ORDER_LMS_MSB; + + R_CRC_Open(&g_crc_ctrl, &g_crc_cfg); + + if (g_crc_reflect_in) { + g_crc_state = reflect_bits(g_crc_initial, g_crc_width); + } else { + g_crc_state = g_crc_initial; + } +} + +void hal_crc_compute_partial(const uint8_t *data, size_t size) +{ + if (data == NULL || size == 0) return; + + size_t hw_size = size; + if (g_crc_width == 32) { + hw_size = size & ~0x03U; + } + + if (hw_size > 0) { + if (g_crc_width == 32 && g_crc_cfg.bit_order == CRC_BIT_ORDER_LMS_MSB) { + uint32_t swapped; + for (size_t offset = 0; offset < hw_size; offset += 4) { + swapped = ((uint32_t)data[offset] << 24) | + ((uint32_t)data[offset + 1] << 16) | + ((uint32_t)data[offset + 2] << 8) | + ((uint32_t)data[offset + 3]); + + crc_input_t input; + input.num_bytes = 4; + input.p_input_buffer = &swapped; + input.crc_seed = g_crc_state; + uint32_t result = 0; + R_CRC_Calculate(&g_crc_ctrl, &input, &result); + g_crc_state = result; + } + } else { + crc_input_t input; + input.num_bytes = hw_size; + input.p_input_buffer = (void *)data; + input.crc_seed = g_crc_state; + uint32_t result = 0; + R_CRC_Calculate(&g_crc_ctrl, &input, &result); + g_crc_state = result; + } + data += hw_size; + } + + size_t rem_size = size - hw_size; + if (rem_size > 0 && g_crc_width == 32) { + uint32_t crc = g_crc_state; + if (g_crc_cfg.bit_order == CRC_BIT_ORDER_LMS_LSB) { + uint32_t poly = (g_crc_cfg.polynomial == CRC_POLYNOMIAL_CRC_32) + ? 0xEDB88320U : 0x82F63B78U; + for (size_t i = 0; i < rem_size; i++) { + crc ^= data[i]; + for (int j = 0; j < 8; j++) { + if (crc & 1) crc = (crc >> 1) ^ poly; + else crc >>= 1; + } + } + } else { + uint32_t poly = (g_crc_cfg.polynomial == CRC_POLYNOMIAL_CRC_32) + ? 0x04C11DB7U : 0x1EDC6F41U; + for (size_t i = 0; i < rem_size; i++) { + crc ^= ((uint32_t)data[i] << 24); + for (int j = 0; j < 8; j++) { + if (crc & 0x80000000U) crc = (crc << 1) ^ poly; + else crc <<= 1; + } + } + } + g_crc_state = crc; + } +} + +uint32_t hal_crc_get_result(void) +{ + uint32_t mask = (g_crc_width == 32) ? 0xFFFFFFFFUL : ((1UL << g_crc_width) - 1); + uint32_t result = g_crc_state & mask; + + if (g_crc_reflect_out != g_crc_reflect_in) { + result = reflect_bits(result, g_crc_width); + } + + result ^= g_crc_final_xor; + return result & mask; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/device.h b/targets/TARGET_RENESAS/TARGET_RA/device.h new file mode 100644 index 0000000000..d1b962710c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/device.h @@ -0,0 +1,18 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#if DEVICE_USTICKER +#include "us_ticker_defines.h" +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/flash_api.c b/targets/TARGET_RENESAS/TARGET_RA/flash_api.c new file mode 100644 index 0000000000..c7398ba8df --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/flash_api.c @@ -0,0 +1,202 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "mbed_critical.h" +#include "flash_api.h" +#include + +#include "r_flash_hp.h" +#include "bsp_api.h" +#include "flash_device.h" + +#define CODEFLASH_LOW_PART_BLOCK_SIZE 8192u +#define CODEFLASH_LOW_PART_BLOCK_COUNT 8u +#define CODEFLASH_HIGH_PART_BLOCK_SIZE 32768u + +/* Flash instance generated by FSP */ +extern const flash_instance_t g_flash0; + +/* Shortcuts */ +#define FLASH_CTRL ((flash_ctrl_t *)g_flash0.p_ctrl) +#define FLASH_CFG ((flash_cfg_t *)g_flash0.p_cfg) + +/* --------------------------------------------------------- + * Helper Functions + * --------------------------------------------------------- + * Determine whether an address belongs to Code Flash or Data Flash. + */ + +static int is_in_code_flash(uint32_t addr) +{ + return (addr >= RA_CF_START) && (addr < (RA_CF_START + RA_CF_SIZE)); +} + +static int is_in_code_flash_low_part(uint32_t addr) +{ + return (addr >= RA_CF_START) && (addr < (RA_CF_START + CODEFLASH_LOW_PART_BLOCK_SIZE * CODEFLASH_LOW_PART_BLOCK_COUNT)); +} + +static int is_in_code_flash_high_part(uint32_t addr) +{ + return (addr >= RA_CF_START + CODEFLASH_LOW_PART_BLOCK_SIZE * CODEFLASH_LOW_PART_BLOCK_COUNT) && (addr < (RA_CF_START + RA_CF_SIZE)); +} + +static int is_in_data_flash(uint32_t addr) +{ + return (addr >= RA_DF_START) && (addr < (RA_DF_START + RA_DF_SIZE)); +} + +/* --------------------------------------------------------- + * Mbed Flash API Implementation + * --------------------------------------------------------- + */ + +int32_t flash_init(flash_t *obj) +{ + (void)obj; + fsp_err_t err = R_FLASH_HP_Open(FLASH_CTRL, FLASH_CFG); + return (err == FSP_SUCCESS) ? 0 : -1; +} + +int32_t flash_free(flash_t *obj) +{ + (void)obj; + fsp_err_t err = R_FLASH_HP_Close(FLASH_CTRL); + return (err == FSP_SUCCESS) ? 0 : -1; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + (void)obj; + + /* Mbed guarantees the address is aligned to sector boundary */ + if (!is_in_code_flash(address) && !is_in_data_flash(address)) { + return -1; + } + + /* Erase one block (one sector) */ + core_util_critical_section_enter(); + fsp_err_t err = R_FLASH_HP_Erase(FLASH_CTRL, address, 1u); + core_util_critical_section_exit(); + +#if BSP_CFG_DCACHE_ENABLED + SCB_InvalidateDCache_by_Addr((volatile void *)address, flash_get_sector_size(obj, address)); +#endif + + return (err == FSP_SUCCESS) ? 0 : -1; +} + +int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) +{ + (void)obj; + + /* Flash is memory-mapped, so memcpy is sufficient */ + memcpy(data, (const void *)address, size); + return 0; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + (void)obj; + + /* Mbed guarantees: + * - data is 32-bit aligned + * - size is a multiple of page size + * - address is inside a flash sector + * - address is aligned to page size + */ + if (!is_in_code_flash(address) && !is_in_data_flash(address)) { + return -1; + } + + core_util_critical_section_enter(); + fsp_err_t err = R_FLASH_HP_Write(FLASH_CTRL, (uint32_t)data, address, size); + core_util_critical_section_exit(); + +#if BSP_CFG_DCACHE_ENABLED + SCB_InvalidateDCache_by_Addr((volatile void *)address, size); +#endif + + return (err == FSP_SUCCESS) ? 0 : -1; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + (void)obj; + + if (is_in_code_flash_low_part(address)) { + // 8KB in block 0-7 + return CODEFLASH_LOW_PART_BLOCK_SIZE; + } else if (is_in_code_flash_high_part(address)) { + // 32KB starting from block 8 + return CODEFLASH_HIGH_PART_BLOCK_SIZE; + } else if (is_in_data_flash(address)) { + return RA_DF_SECTOR_SIZE; + } else { + return (uint32_t)-1; /* Invalid address */ + } +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + (void)obj; + + /* Return the minimum writable unit for Code Flash. + * Data Flash write size can be queried separately if needed. + */ + return RA_CF_WRITE_SIZE; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + (void)obj; + return RA_CF_START; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + (void)obj; + return RA_CF_SIZE; +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + return 0xFF; /* All RA Flash erases to 0xFF */ +} + +/* --------------------------------------------------------- + * Export Data Flash information for upper layers + * --------------------------------------------------------- + */ + +uint32_t ra_flash_get_data_flash_start(void) +{ + return RA_DF_START; +} + +uint32_t ra_flash_get_data_flash_size(void) +{ + return RA_DF_SIZE; +} + +uint32_t ra_flash_get_data_flash_sector_size(void) +{ + return RA_DF_SECTOR_SIZE; +} + +uint32_t ra_flash_get_data_flash_write_size(void) +{ + return RA_DF_WRITE_SIZE; +} + +/* --------------------------------------------------------- + * Callback function + * --------------------------------------------------------- + */ + +void flash_callback(flash_callback_args_t * p_args) +{ + (void)p_args; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/gpio_api.c b/targets/TARGET_RENESAS/TARGET_RA/gpio_api.c new file mode 100644 index 0000000000..5f581e4dce --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/gpio_api.c @@ -0,0 +1,102 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "gpio_api.h" +#include "r_ioport.h" +#include "common_data.h" + +static inline bsp_io_port_pin_t pin_to_bsp(PinName pin) +{ + return (bsp_io_port_pin_t)pin; +} + +static inline bsp_io_port_t pin_to_port(PinName pin) +{ + return (bsp_io_port_t)(pin >> 8); +} + +static inline uint32_t pin_to_mask(PinName pin) +{ + return (1U << (pin & 0xFF)); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + obj->port = pin_to_port(pin); + obj->pin_mask = pin_to_mask(pin); + + // Keep IRQ flag +#if (3U == BSP_FEATURE_IOPORT_VERSION) + uint32_t cfg = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; +#else + uint32_t cfg = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; +#endif + R_BSP_PinCfg(pin_to_bsp(pin), (cfg & IOPORT_CFG_IRQ_ENABLE) ? IOPORT_CFG_IRQ_ENABLE: IOPORT_CFG_PORT_DIRECTION_INPUT); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + PinName pin = obj->pin; +#if (3U == BSP_FEATURE_IOPORT_VERSION) + uint32_t cfg = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; +#else + uint32_t cfg = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; +#endif + + switch (mode) { + case PullUp: + cfg |= IOPORT_CFG_PULLUP_ENABLE; + cfg &= ~IOPORT_CFG_NMOS_ENABLE; + break; + case OpenDrain: + cfg &= ~IOPORT_CFG_PULLUP_ENABLE; + cfg |= IOPORT_CFG_NMOS_ENABLE; + break; + case PullDown: + case PullNone: + default: + cfg &= ~(IOPORT_CFG_PULLUP_ENABLE|IOPORT_CFG_NMOS_ENABLE); + break; + } + + R_BSP_PinCfg(pin_to_bsp(pin), cfg); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + PinName pin = obj->pin; +#if (3U == BSP_FEATURE_IOPORT_VERSION) + uint32_t cfg = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; +#else + uint32_t cfg = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; +#endif + + if (direction == PIN_OUTPUT) { + cfg |= IOPORT_CFG_PORT_DIRECTION_OUTPUT; + } else { + cfg &= ~IOPORT_CFG_PORT_DIRECTION_OUTPUT; + } + + R_BSP_PinCfg(pin_to_bsp(obj->pin), cfg); +} + +void gpio_write(gpio_t *obj, int value) +{ + R_BSP_PinWrite(pin_to_bsp(obj->pin), value ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW); +} + +int gpio_read(gpio_t *obj) +{ + return (R_BSP_PinRead(pin_to_bsp(obj->pin)) != 0) ? 1 : 0; +} + +int gpio_is_connected(const gpio_t *obj) +{ + if (obj->pin == NC) { + return 0; + } else { + return 1; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RA/gpio_irq_api.c new file mode 100644 index 0000000000..ce516d731b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/gpio_irq_api.c @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "gpio_irq_api.h" +#include "pinmap.h" +#include "mbed_critical.h" +#include "mbed_assert.h" +#include "common_data.h" +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static gpio_irq_handler s_handler = NULL; +static uint8_t s_irq_used[IRQ_CHANNELS_COUNT] = {0}; +static gpio_irq_t * s_irq_obj[IRQ_CHANNELS_COUNT] = {0}; + +extern icu_instance_ctrl_t * const g_icu_ctrl[IRQ_CHANNELS_COUNT]; +extern const external_irq_cfg_t * const g_icu_cfg[IRQ_CHANNELS_COUNT]; + +void external_irq_callback(external_irq_callback_args_t *p_args) +{ + uint32_t ch = p_args->channel; + + if (ch < IRQ_CHANNELS_COUNT && s_irq_used[ch] && s_handler) + { + gpio_irq_t *obj = s_irq_obj[ch]; + int level = R_BSP_PinRead((bsp_io_port_pin_t) obj->pin); + + gpio_irq_event evt = level ? IRQ_RISE : IRQ_FALL; + + s_handler(obj->context, evt); + } +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) +{ + MBED_ASSERT(obj); + MBED_ASSERT(pin != NC); + + core_util_critical_section_enter(); + s_handler = handler; + core_util_critical_section_exit(); + + int irq_channel = pinmap_peripheral(pin, PinMap_IRQ); + MBED_ASSERT(irq_channel != (int)NC); + + int irq_function = pinmap_function(pin, PinMap_IRQ); + pin_function(pin, irq_function); + + obj->pin = pin; + obj->channel = irq_channel; + obj->context = context; + + s_irq_obj[irq_channel] = obj; + s_irq_used[irq_channel] = 1; + + fsp_err_t err = R_ICU_ExternalIrqOpen(g_icu_ctrl[irq_channel], g_icu_cfg[irq_channel]); + MBED_ASSERT(err == FSP_SUCCESS); + + R_ICU_ExternalIrqEnable(g_icu_ctrl[irq_channel]); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + MBED_ASSERT(obj); + + uint32_t ch = obj->channel; + if (ch >= IRQ_CHANNELS_COUNT) + return; + + s_irq_used[ch] = 0; + + R_ICU_ExternalIrqDisable(g_icu_ctrl[ch]); + R_ICU_ExternalIrqClose(g_icu_ctrl[ch]); + + obj->pin = NC; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + /* RA4E1 �� FSP ��֧������ʱ�޸Ĵ�����ʽ����Ҫ���� Open�� + �������Ҫ֧�� RISE/FALL ��̬�л����������������� Open ͨ�� */ + + (void)obj; + (void)event; + (void)enable; + + /* ���գ�Mbed �� InterruptIn Ĭ��ֻ��Ҫ˫�ش��� */ +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + R_ICU_ExternalIrqEnable(g_icu_ctrl[obj->channel]); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + R_ICU_ExternalIrqDisable(g_icu_ctrl[obj->channel]); +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/gpio_object.h b/targets/TARGET_RENESAS/TARGET_RA/gpio_object.h new file mode 100644 index 0000000000..0ea8ed19dd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/gpio_object.h @@ -0,0 +1,30 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t port; + uint32_t pin_mask; +} gpio_t; + +void gpio_init(gpio_t *obj, PinName pin); +void gpio_mode(gpio_t *obj, PinMode mode); +void gpio_dir(gpio_t *obj, PinDirection direction); +void gpio_write(gpio_t *obj, int value); +int gpio_read(gpio_t *obj); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RA/i2c_api.c new file mode 100644 index 0000000000..90acd7bcae --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/i2c_api.c @@ -0,0 +1,488 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#if DEVICE_I2C + +#include "mbed_assert.h" +#include "mbed_error.h" +#include "i2c_api.h" +#include "pinmap.h" + +#include "hal_data.h" +#include "r_ioport.h" + +#include "i2c_device.h" + +#define I2C_ERROR -1 + +extern const PinMap PinMap_I2C_SCL[]; +extern const PinMap PinMap_I2C_SDA[]; + +extern const i2c_master_instance_t g_i2c_master0; +#if (BSP_FEATURE_IIC_VALID_CHANNEL_MASK & 2) != 0 +extern const i2c_master_instance_t g_i2c_master1; +#endif +extern const ioport_instance_t g_ioport; + +/* -------------------------------------------------------------------------- + * Helpers + * -------------------------------------------------------------------------- */ + +static const i2c_master_instance_t *ra_i2c_instance_from_channel(I2CName ch) +{ + switch (ch) { + case I2C_0: return &g_i2c_master0; +#if (BSP_FEATURE_IIC_VALID_CHANNEL_MASK & 2) != 0 + case I2C_1: return &g_i2c_master1; +#endif + default: return NULL; + } +} + +static void ra_i2c_configure_pins(PinName sda, int sda_func, PinName scl, int scl_func) +{ + if (sda != NC && sda_func) { + pin_function(sda, sda_func); + } + if (scl != NC && scl_func) { + pin_function(scl, scl_func); + } +} + +static void ra_i2c_configure_pins_from_pinmap(PinName sda, PinName scl) +{ + uint32_t func; + + if (sda != NC) { + func = pinmap_function(sda, PinMap_I2C_SDA); + if (func) { + pin_function(sda, func); + } + } + + if (scl != NC) { + func = pinmap_function(scl, PinMap_I2C_SCL); + if (func) { + pin_function(scl, func); + } + } +} + +static int ra_i2c_rate_to_hz(i2c_master_rate_t rate) +{ + switch (rate) { + case I2C_MASTER_RATE_STANDARD: return 100000; + case I2C_MASTER_RATE_FAST: return 400000; + case I2C_MASTER_RATE_FASTPLUS: return 1000000; + default: return 100000; + } +} + +static void ra_i2c_set_address(i2c_t *obj, int address, bool ten_bit) +{ + if(!obj->i2c.p_ctrl->restart) + { + uint16_t addr = (uint16_t)(address >> 1); + + fsp_err_t err = R_IIC_MASTER_SlaveAddressSet( + obj->i2c.p_ctrl, + addr, + ten_bit ? I2C_MASTER_ADDR_MODE_10BIT : I2C_MASTER_ADDR_MODE_7BIT + ); + + if (FSP_SUCCESS != err) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_INVALID_ARGUMENT), "i2c_set_address"); + } + } +} + +/* -------------------------------------------------------------------------- + * Init / Free + * -------------------------------------------------------------------------- */ + +void i2c_init_direct(i2c_t *obj, const i2c_pinmap_t *pinmap) +{ + MBED_ASSERT(obj != NULL); + MBED_ASSERT(pinmap != NULL); + + obj->i2c.pending_restart = false; + obj->i2c.tx_active = false; + obj->i2c.tx_len = 0; + + obj->i2c.i2c = (I2CName) pinmap->peripheral; + + ra_i2c_configure_pins(pinmap->sda_pin, pinmap->sda_function, + pinmap->scl_pin, pinmap->scl_function); + + const i2c_master_instance_t *inst = ra_i2c_instance_from_channel(obj->i2c.i2c); + MBED_ASSERT(inst != NULL); + + obj->i2c.p_ctrl = (i2c_instance_ctrl_t *) inst->p_ctrl; + + const i2c_master_cfg_t *cfg_src = inst->p_cfg; + const i2c_extended_cfg_t *ext_src = (const i2c_extended_cfg_t *) cfg_src->p_extend; + + obj->i2c.cfg = *cfg_src; + obj->i2c.cfg.p_context = (void *) obj; + if (ext_src) { + obj->i2c.ext = *ext_src; + obj->i2c.cfg.p_extend = &obj->i2c.ext; + } else { + obj->i2c.cfg.p_extend = NULL; + } + + obj->i2c.hz = ra_i2c_rate_to_hz(obj->i2c.cfg.rate); + + fsp_err_t err = R_IIC_MASTER_Open(obj->i2c.p_ctrl, &obj->i2c.cfg); + if (FSP_SUCCESS != err) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_INITIALIZATION_FAILED), "i2c_init_direct"); + } +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + MBED_ASSERT(obj != NULL); + + obj->i2c.pending_restart = false; + obj->i2c.tx_active = false; + obj->i2c.tx_len = 0; + + int sda_periph = pinmap_peripheral(sda, PinMap_I2C_SDA); + int scl_periph = pinmap_peripheral(scl, PinMap_I2C_SCL); + int i2c_periph = pinmap_merge(sda_periph, scl_periph); + + if (i2c_periph == (int)NC) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_INVALID_ARGUMENT), "i2c_init"); + } + + obj->i2c.i2c = (I2CName)i2c_periph; + + ra_i2c_configure_pins_from_pinmap(sda, scl); + + const i2c_master_instance_t *inst = ra_i2c_instance_from_channel(obj->i2c.i2c); + MBED_ASSERT(inst != NULL); + + obj->i2c.p_ctrl = (i2c_instance_ctrl_t *) inst->p_ctrl; + + const i2c_master_cfg_t *cfg_src = inst->p_cfg; + const i2c_extended_cfg_t *ext_src = (const i2c_extended_cfg_t *) cfg_src->p_extend; + + obj->i2c.cfg = *cfg_src; + obj->i2c.cfg.p_context = (void *) obj; + if (ext_src) { + obj->i2c.ext = *ext_src; + obj->i2c.cfg.p_extend = &obj->i2c.ext; + } else { + obj->i2c.cfg.p_extend = NULL; + } + + obj->i2c.hz = ra_i2c_rate_to_hz(obj->i2c.cfg.rate); + + fsp_err_t err = R_IIC_MASTER_Open(obj->i2c.p_ctrl, &obj->i2c.cfg); + if (FSP_SUCCESS != err) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_INITIALIZATION_FAILED), "i2c_init"); + } +} + +void i2c_free(i2c_t *obj) +{ + if (!obj) { + return; + } + + if (obj->i2c.p_ctrl) { + (void) R_IIC_MASTER_Close(obj->i2c.p_ctrl); + } +} + +/* -------------------------------------------------------------------------- + * Frequency + * -------------------------------------------------------------------------- */ + +bool set_iic_master_clock_settings(int hz, iic_master_clock_settings_t *clock_settings) +{ + for (size_t i = 0; i < sizeof(g_iic_clock_table)/sizeof(g_iic_clock_table[0]); i++) { + if (g_iic_clock_table[i].hz == hz) { + *clock_settings = g_iic_clock_table[i].clk; + return true; + } + } + return false; +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + MBED_ASSERT(obj != NULL); + + if (!set_iic_master_clock_settings(hz, &obj->i2c.ext.clock_settings)) { + return; + } + + if (hz <= 100000) { + obj->i2c.cfg.rate = I2C_MASTER_RATE_STANDARD; + } else if (hz <= 400000) { + obj->i2c.cfg.rate = I2C_MASTER_RATE_FAST; + } else { +#ifdef I2C_MASTER_RATE_FASTPLUS + obj->cfg.rate = I2C_MASTER_RATE_FASTPLUS; +#endif + } + + obj->i2c.hz = hz; + + R_IIC_MASTER_Close(obj->i2c.p_ctrl); + fsp_err_t err = R_IIC_MASTER_Open(obj->i2c.p_ctrl, &obj->i2c.cfg); + if (FSP_SUCCESS != err) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_I2C, MBED_ERROR_CODE_INITIALIZATION_FAILED), "i2c_frequency"); + } +} + +/* -------------------------------------------------------------------------- + * Blocking read / write + * -------------------------------------------------------------------------- */ + +static int i2c_flush_tx_buf(i2c_t *obj, bool restart) +{ + if (!obj->i2c.tx_active || obj->i2c.tx_len == 0) { + return 0; + } + + int addr8 = obj->i2c.tx_buf[0] & 0xFE; + ra_i2c_set_address(obj, addr8, false); + + obj->i2c.xfer_done = false; + obj->i2c.xfer_aborted = false; + + fsp_err_t err = R_IIC_MASTER_Write( + obj->i2c.p_ctrl, + &obj->i2c.tx_buf[1], + obj->i2c.tx_len - 1, + restart + ); + + if (err != FSP_SUCCESS) { + return I2C_ERROR; + } + + while (!obj->i2c.xfer_done) {} + if (obj->i2c.xfer_aborted) { + return I2C_ERROR; + } + + obj->i2c.tx_active = false; + obj->i2c.tx_len = 0; + + return 0; +} + + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + MBED_ASSERT(obj != NULL); + + /* flush pending address bytes */ + if (i2c_flush_tx_buf(obj, true) != 0) { + return I2C_ERROR; + } + + if (!data || length <= 0) { + return 0; + } + + obj->i2c.xfer_done = false; + obj->i2c.xfer_aborted = false; + + ra_i2c_set_address(obj, address, false); + + bool restart = obj->i2c.pending_restart; + + fsp_err_t err = R_IIC_MASTER_Read( + obj->i2c.p_ctrl, + (uint8_t *) data, + (uint32_t) length, + restart + ); + if (FSP_SUCCESS != err) { + obj->i2c.pending_restart = false; + return I2C_ERROR; + } + + while (!obj->i2c.xfer_done) {} + + if (obj->i2c.xfer_aborted) { + obj->i2c.pending_restart = false; + return I2C_ERROR; + } + + obj->i2c.pending_restart = (stop == 0); + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + MBED_ASSERT(obj != NULL); + + /* flush pending address bytes */ + if (i2c_flush_tx_buf(obj, true) != 0) { + return I2C_ERROR; + } + + if (!data || length <= 0) { + /* Zero-length write = send only address */ + obj->i2c.xfer_done = false; + obj->i2c.xfer_aborted = false; + + ra_i2c_set_address(obj, address, false); + + uint8_t dummy = 0; + + fsp_err_t err = R_IIC_MASTER_Write( + obj->i2c.p_ctrl, + &dummy, + 1, + false + ); + + if (err != FSP_SUCCESS) return I2C_ERROR; + while (!obj->i2c.xfer_done) {} + return obj->i2c.xfer_aborted ? I2C_ERROR : 0; + } + + obj->i2c.xfer_done = false; + obj->i2c.xfer_aborted = false; + + ra_i2c_set_address(obj, address, false); + + bool restart = obj->i2c.pending_restart; + + fsp_err_t err = R_IIC_MASTER_Write( + obj->i2c.p_ctrl, + (uint8_t *) data, + (uint32_t) length, + restart + ); + if (FSP_SUCCESS != err) { + obj->i2c.pending_restart = false; + return I2C_ERROR; + } + + while (!obj->i2c.xfer_done) {} + + if (obj->i2c.xfer_aborted) { + obj->i2c.pending_restart = false; + return I2C_ERROR; + } + + obj->i2c.pending_restart = (stop == 0); + + return length; +} + +/* -------------------------------------------------------------------------- + * Byte read / write + * -------------------------------------------------------------------------- */ + +int i2c_byte_read(i2c_t *obj, int last) +{ + uint8_t b = 0; + + int ret = i2c_read(obj, obj->i2c.last_address | 1, (char *)&b, 1, last); + if (ret != 1) { + return I2C_ERROR; + } + return b; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + if (!obj->i2c.tx_active) { + return 3; + } + + if (obj->i2c.tx_len >= sizeof(obj->i2c.tx_buf)) { + return 3; + } + + obj->i2c.tx_buf[obj->i2c.tx_len++] = (uint8_t)data; + return 1; +} + +/* -------------------------------------------------------------------------- + * Start / Stop / Reset + * -------------------------------------------------------------------------- */ + +int i2c_start(i2c_t *obj) +{ + obj->i2c.pending_restart = true; + obj->i2c.tx_active = true; + obj->i2c.tx_len = 0; + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + /* flush pending bytes with restart = false */ + i2c_flush_tx_buf(obj, false); + + obj->i2c.tx_active = false; + obj->i2c.tx_len = 0; + obj->i2c.pending_restart = false; + + return 0; +} + +void i2c_reset(i2c_t *obj) +{ + (void) i2c_stop(obj); +} + +/* -------------------------------------------------------------------------- + * PinMap getters + * -------------------------------------------------------------------------- */ + +const PinMap *i2c_master_sda_pinmap(void) +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap(void) +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap(void) +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap(void) +{ + return PinMap_I2C_SCL; +} + +/* ---------------- I2C callback ---------------- */ + +void i2c_callback(i2c_master_callback_args_t *p_args) +{ + i2c_t *obj = (i2c_t *) p_args->p_context; + + switch (p_args->event) { + case I2C_MASTER_EVENT_TX_COMPLETE: + case I2C_MASTER_EVENT_RX_COMPLETE: + obj->i2c.xfer_done = true; + obj->i2c.xfer_aborted = false; + break; + + case I2C_MASTER_EVENT_ABORTED: + obj->i2c.xfer_done = true; + obj->i2c.xfer_aborted = true; + break; + + default: + break; + } +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/mbed_overrides.cpp b/targets/TARGET_RENESAS/TARGET_RA/mbed_overrides.cpp new file mode 100644 index 0000000000..94d840b220 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/mbed_overrides.cpp @@ -0,0 +1,19 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "cmsis.h" +#include "objects.h" +#include "platform/mbed_error.h" + +int mbed_sdk_inited = 0; + +// This function is called after RAM initialization and before main. +extern "C" void mbed_sdk_init() +{ + /* Enable Pin access globally */ + R_BSP_PinAccessEnable(); + + mbed_sdk_inited = 1; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/mbed_rtx.h b/targets/TARGET_RENESAS/TARGET_RA/mbed_rtx.h new file mode 100644 index 0000000000..8d12159c76 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/mbed_rtx.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Symbols exported by the RA FSP linker script */ +extern uint32_t __StackTop; +extern uint32_t __StackLimit; +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +/* ISR stack region (Mbed/RTX use this for isr stack boundaries) */ +#define ISR_STACK_START ((uint32_t)&__StackLimit) +#define ISR_STACK_SIZE ((uint32_t)&__StackTop - (uint32_t)&__StackLimit) + +/* Main heap region used by Mbed allocator / RTX */ +#define HEAP_START ((uint32_t)&__HeapBase) +#define HEAP_SIZE ((uint32_t)&__HeapLimit - (uint32_t)&__HeapBase) + +#ifdef __cplusplus +} +#endif + +#endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/objects.h b/targets/TARGET_RENESAS/TARGET_RA/objects.h new file mode 100644 index 0000000000..535e887b58 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/objects.h @@ -0,0 +1,225 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "gpio_object.h" +#include "PeripheralNames.h" + +#if MBED_CONF_RTOS_PRESENT +#include "cmsis_os.h" +#include "cmsis_os2.h" +#endif + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; +}; + +#if DEVICE_ANALOGIN +struct analogin_s { + uint32_t peripheral; + uint32_t channel; + PinName pin; +}; +#endif + +#if DEVICE_TRNG +struct trng_s { + void *handle; +}; +#endif + +#if DEVICE_ANALOGOUT +#include "r_dac.h" +struct dac_s { + uint8_t channel; + dac_instance_ctrl_t *ctrl; + dac_cfg_t cfg; + dac_extended_cfg_t ext_cfg; + uint16_t last_value; +}; +#endif + +#if DEVICE_PWMOUT +#include "r_timer_api.h" +#include "r_gpt.h" +#include "r_agt.h" + +typedef enum { + PWM_OUTPUT_A = 0, + PWM_OUTPUT_B = 1, +} pwm_output_t; + +typedef enum { + PWM_TIMER_TYPE_GPT = 0, + PWM_TIMER_TYPE_AGT +} pwm_timer_type_t; + +struct pwmout_s { + PinName pin; + const timer_instance_t *p_timer; + pwm_output_t pwm_unit; + uint32_t period_counts; + uint32_t duty_counts; + uint8_t initialized; + + pwm_timer_type_t timer_type; + bool is_16bit; + timer_cfg_t cfg; + union { + gpt_extended_cfg_t gpt_ext; + agt_extended_cfg_t agt_ext; + } ext_cfg; +}; +#endif + +#if DEVICE_INTERRUPTIN +struct gpio_irq_s { + uint32_t channel; + PinName pin; + uintptr_t context; +}; +#endif + +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + +#if DEVICE_SERIAL +#if BSP_PERIPHERAL_SCI_B_PRESENT + #include "r_sci_b_uart.h" + typedef sci_b_uart_instance_ctrl_t sci_uart_instance_ctrl_t; + typedef sci_b_uart_extended_cfg_t sci_uart_extended_cfg_t; +#else + #include "r_sci_uart.h" +#endif +struct serial_s { + uart_cfg_t cfg; /* Local copy of configuration */ + uart_api_t const *p_api; /* Pointer to R_SCI_UART API */ + sci_uart_instance_ctrl_t *p_ctrl; /* Pointer to R_SCI_UART control block (instance-specific) */ + sci_uart_extended_cfg_t ext; /* Local copy of extended configuration */ + + int instance_index; + PinName tx; + PinName rx; +}; +#endif + +#if DEVICE_SPI +#if BSP_PERIPHERAL_SPI_B_PRESENT + #include + typedef spi_b_extended_cfg_t spi_extended_cfg_t; + typedef spi_b_instance_ctrl_t spi_instance_ctrl_t; + #define R_SPI_Open R_SPI_B_Open + #define R_SPI_Close R_SPI_B_Close + #define R_SPI_WriteRead R_SPI_B_WriteRead + #define R_SPI_Write R_SPI_B_Write + #define R_SPI_Read R_SPI_B_Read + #define SPI_COMMUNICATION_FULL_DUPLEX SPI_B_COMMUNICATION_FULL_DUPLEX + #define SPI_COMMUNICATION_TRANSMIT_ONLY SPI_B_COMMUNICATION_TRANSMIT_ONLY +#else + #include +#endif + +struct spi_s { + spi_cfg_t cfg; /* Local copy of configuration */ + spi_extended_cfg_t ext; /* Local copy of extended configuration */ + spi_instance_ctrl_t *p_ctrl; /* R_SPI control block (instance-specific) */ + SPIName channel; /* SPI_0 / SPI_1 */ + uint32_t hz; /* Current frequency */ + uint8_t bits; /* Bits per frame (usually 8) */ + uint8_t mode; /* SPI mode 0..3 */ + bool has_mosi; /* Has MOSI pin */ + bool has_miso; /* Has MISO pin */ +#if MBED_CONF_RTOS_PRESENT + osSemaphoreId_t semaphoreId; + osRtxSemaphore_t semaphoreMem; +#else + volatile bool xfer_done; /* Set by callback when the current transfer completes or aborted */ +#endif +}; +#endif + +#if DEVICE_I2C +#if BSP_PERIPHERAL_IIC_B_PRESENT + #include "r_iic_b_master.h" + typedef iic_b_master_extended_cfg_t i2c_extended_cfg_t; + typedef iic_b_master_instance_ctrl_t i2c_instance_ctrl_t; + typedef iic_b_master_clock_settings_t iic_master_clock_settings_t; + #define R_IIC_MASTER_Open R_IIC_B_MASTER_Open + #define R_IIC_MASTER_Close R_IIC_B_MASTER_Close + #define R_IIC_MASTER_Read R_IIC_B_MASTER_Read + #define R_IIC_MASTER_Write R_IIC_B_MASTER_Write + #define R_IIC_MASTER_Abort R_IIC_B_MASTER_Abort + #define R_IIC_MASTER_SlaveAddressSet R_IIC_B_MASTER_SlaveAddressSet +#else + #include "r_iic_master.h" + typedef iic_master_extended_cfg_t i2c_extended_cfg_t; + typedef iic_master_instance_ctrl_t i2c_instance_ctrl_t; +#endif + +struct i2c_s { + i2c_master_cfg_t cfg; /* Local copy of the FSP configuration */ + i2c_extended_cfg_t ext; /* Local copy of the extended configuration */ + i2c_instance_ctrl_t *p_ctrl; /* Pointer to the FSP control block */ + I2CName i2c; /* I2C peripheral identifier (I2C_0 / I2C_1 / ...) */ + int hz; /* Current bus frequency in Hz */ + + /* ---- Mbed HAL transaction state ---- */ + bool pending_restart; /* Indicates whether the next transfer should use a repeated START */ + volatile bool xfer_done; /* Set by callback when the current transfer completes */ + volatile bool xfer_aborted; /* Set by callback when the current transfer is aborted (NACK, timeout, etc.) */ + + /* ---- Raw?byte write mode (required for Mbed I2CEEBlockDevice) ---- */ + bool tx_active; /* True after i2c_start(), enabling raw byte accumulation */ + uint8_t tx_buf[256]; /* Accumulated raw bytes to be sent in a single FSP transfer */ + size_t tx_len; /* Number of bytes currently stored in tx_buf */ + + /* ---- Last device address used (required for i2c_byte_read/write) ---- */ + int last_address; /* Cached 8?bit I2C address used for the last read/write operation */ +}; + +#endif /* DEVICE_I2C */ + +#ifdef DEVICE_CAN + +#ifdef DEVICE_CAN_FD +#include "r_canfd.h" +#else +#include "r_can.h" +#endif + +#define MBED_CAN_RX_QUEUE_SIZE 16 + +struct can_s { + const can_instance_t *instance; + can_cfg_t cfg_copy; + + uintptr_t irq_context; + + /* RX ring buffer */ + can_frame_t rx_queue[MBED_CAN_RX_QUEUE_SIZE]; + volatile uint8_t rx_head; + volatile uint8_t rx_tail; + + int hz; +#ifdef DEVICE_CAN_FD + int data_hz; +#endif +}; + + +#endif /* DEVICE_CAN */ + + +#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((polynomial) == POLY_8BIT_CCITT || (polynomial) == POLY_16BIT_CCITT || (polynomial) == POLY_16BIT_IBM || (polynomial) == POLY_32BIT_ANSI) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/pinmap.c b/targets/TARGET_RENESAS/TARGET_RA/pinmap.c new file mode 100644 index 0000000000..e9562de042 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/pinmap.c @@ -0,0 +1,93 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "pinmap.h" +#include "common_data.h" + +void pin_mode(PinName pin, PinMode mode) +{ + if (pin == NC) { + return; + } + + uint32_t cfg = 0; + + switch (mode) { + case PullNone: + cfg |= IOPORT_CFG_PORT_DIRECTION_INPUT; + break; + + case PullUp: + cfg |= IOPORT_CFG_PORT_DIRECTION_INPUT | + IOPORT_CFG_PULLUP_ENABLE; + break; + + case PullDown: + // PullDown not supported on RA + cfg |= IOPORT_CFG_PORT_DIRECTION_INPUT; + break; + + case OpenDrain: + cfg |= IOPORT_CFG_PORT_DIRECTION_OUTPUT | + IOPORT_CFG_NMOS_ENABLE; + break; + + default: + cfg |= IOPORT_CFG_PORT_DIRECTION_INPUT; + break; + } + + R_IOPORT_PinCfg(g_ioport.p_ctrl, (bsp_io_port_pin_t) pin, cfg); +} + +void pin_function(PinName pin, int function) +{ + uint32_t mode = RA_PIN_MODE(function); + uint32_t pull = RA_PIN_PULL(function); + uint32_t alt = RA_PIN_ALT(function); + uint32_t speed = RA_PIN_SPEED(function); + + uint32_t cfg = 0; + + switch (mode) { + case RA_PIN_MODE_ANALOG: + cfg |= IOPORT_CFG_ANALOG_ENABLE; + break; + + case RA_PIN_MODE_PERIPHERAL_PP: + cfg |= IOPORT_CFG_PERIPHERAL_PIN; + cfg |= ((alt & 0x1F) << IOPORT_PRV_PFS_PSEL_OFFSET); + break; + + case RA_PIN_MODE_PERIPHERAL_OD: + cfg |= IOPORT_CFG_PERIPHERAL_PIN; + cfg |= IOPORT_CFG_NMOS_ENABLE; + cfg |= ((alt & 0x1F) << IOPORT_PRV_PFS_PSEL_OFFSET); + break; + + case RA_PIN_MODE_IRQ: + cfg |= IOPORT_CFG_IRQ_ENABLE; + break; + } + + switch (speed) { + case RA_PIN_SPEED_MID: + cfg |= IOPORT_CFG_DRIVE_MID; + break; + case RA_PIN_SPEED_HS_HIGH: + cfg |= IOPORT_CFG_DRIVE_HS_HIGH; + break; + case RA_PIN_SPEED_HIGH: + cfg |= IOPORT_CFG_DRIVE_HIGH; + break; + } + + if (pull == RA_PIN_PULL_UP) { + cfg |= IOPORT_CFG_PULLUP_ENABLE; + } else if (pull == RA_PIN_PULL_DOWN) { + // not supported by RA + } + + R_IOPORT_PinCfg(g_ioport.p_ctrl, (bsp_io_port_pin_t) pin, cfg); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/port_api.c b/targets/TARGET_RENESAS/TARGET_RA/port_api.c new file mode 100644 index 0000000000..ce9ebd41b9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/port_api.c @@ -0,0 +1,36 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "mbed_assert.h" +#include "port_api.h" +#include "r_ioport.h" +#include "hal_data.h" + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + obj->port = port; + obj->mask = mask; + obj->direction = dir; + + R_IOPORT_PortDirectionSet(&g_ioport_ctrl, (bsp_io_port_t) obj->port, obj->mask, + (dir == PIN_OUTPUT) ? 0xFFFFFFFFF : 0x00000000); +} + +void port_write(port_t *obj, int value) +{ + R_IOPORT_PortWrite(&g_ioport_ctrl, (bsp_io_port_t) obj->port, value, obj->mask); +} + +int port_read(port_t *obj) +{ + uint16_t value; + R_IOPORT_PortRead(&g_ioport_ctrl, (bsp_io_port_t) obj->port, &value); + return value & obj->mask; +} + +void port_dir(port_t *obj, PinDirection dir) +{ + R_IOPORT_PortDirectionSet(&g_ioport_ctrl, (bsp_io_port_t) obj->port, obj->mask, + (dir == PIN_OUTPUT) ? 0xFFFFFFFFF : 0x00000000); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RA/pwmout_api.c new file mode 100644 index 0000000000..4e3e31e455 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/pwmout_api.c @@ -0,0 +1,335 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "pwmout_api.h" +#include "mbed_assert.h" +#include "pinmap.h" +#include "bsp_api.h" +#include "PeripheralPins.h" +#include "pwmout_device.h" +#include + +#if MBED_CONF_TARGET_LSE_AVAILABLE +#define AGT_LOW_FREQ_CLOCK AGT_CLOCK_SUBCLOCK +#else +#define AGT_LOW_FREQ_CLOCK AGT_CLOCK_LOCO +#endif + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + MBED_ASSERT(obj); + + // peripheral = PWMName + uint32_t periph = pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(periph != (uint32_t)NC); + + // function = pwm_output_t + uint32_t func = pinmap_find_function(pin, PinMap_PWM); + MBED_ASSERT(func != (uint32_t)NC); + + pin_function(pin, func); + + PWMName timer_id = (PWMName) periph; + pwm_output_t unit = (pwm_output_t) RA_PIN_CHANNEL(func); + + obj->pin = pin; + obj->pwm_unit = unit; + obj->p_timer = pwm_timer_lookup(timer_id); + obj->period_counts = 0; + obj->duty_counts = 0; + obj->initialized = 0; + + MBED_ASSERT(obj->p_timer != NULL); + + /* 1. Identify timer type and bit-width dynamically via FSP API pointer and p_ctrl */ + if (obj->p_timer->p_api == &g_timer_on_gpt) { + obj->timer_type = PWM_TIMER_TYPE_GPT; + } else if (obj->p_timer->p_api == &g_timer_on_agt) { + obj->timer_type = PWM_TIMER_TYPE_AGT; + } else { + // Unsupported timer driver API + MBED_ASSERT(0); + } + + /* 2. Deep-copy FSP default configurations into the local object RAM */ + memcpy(&obj->cfg, obj->p_timer->p_cfg, sizeof(timer_cfg_t)); + if (obj->timer_type == PWM_TIMER_TYPE_GPT) { + if (obj->p_timer->p_cfg->p_extend) { + memcpy(&obj->ext_cfg.gpt_ext, obj->p_timer->p_cfg->p_extend, sizeof(gpt_extended_cfg_t)); + } + obj->cfg.p_extend = &obj->ext_cfg.gpt_ext; + } else { + if (obj->p_timer->p_cfg->p_extend) { + memcpy(&obj->ext_cfg.agt_ext, obj->p_timer->p_cfg->p_extend, sizeof(agt_extended_cfg_t)); + } + obj->cfg.p_extend = &obj->ext_cfg.agt_ext; + } + + /* 3. Open and Start the timer using local configuration */ + fsp_err_t err = obj->p_timer->p_api->open(obj->p_timer->p_ctrl, &obj->cfg); + if (FSP_SUCCESS != err && FSP_ERR_ALREADY_OPEN != err) { + MBED_ASSERT(0); + } + + if(obj->timer_type == PWM_TIMER_TYPE_GPT) { + // Cast p_ctrl to gpt_instance_ctrl_t to check bit-width variant + gpt_instance_ctrl_t *p_gpt_ctrl = (gpt_instance_ctrl_t *) obj->p_timer->p_ctrl; + if (p_gpt_ctrl->variant == TIMER_VARIANT_16_BIT) { + obj->is_16bit = true; + } else { + obj->is_16bit = false; + } + } + else { + // Cast p_ctrl to agt_instance_ctrl_t to check if it's AGTW (32-bit) + agt_instance_ctrl_t *p_agt_ctrl = (agt_instance_ctrl_t *) obj->p_timer->p_ctrl; + if (p_agt_ctrl->is_agtw) { + obj->is_16bit = false; // AGTW is 32-bit + } else { + obj->is_16bit = true; // Regular AGT is 16-bit + } + } + + pwmout_period_us(obj, 1000); + pwmout_write(obj, 0.0f); + + err = obj->p_timer->p_api->start(obj->p_timer->p_ctrl); + if (FSP_SUCCESS != err) { + MBED_ASSERT(0); + } + obj->initialized = 1; +} + +void pwmout_free(pwmout_t *obj) +{ + if (!obj || !obj->initialized) { + return; + } + + obj->p_timer->p_api->stop(obj->p_timer->p_ctrl); + obj->p_timer->p_api->close(obj->p_timer->p_ctrl); + + obj->initialized = 0; +} + +void pwmout_period_us(pwmout_t *obj, int us) +{ + MBED_ASSERT(obj && obj->p_timer); + + if (us <= 0) { + us = 1; + } + + uint64_t max_count = obj->is_16bit ? 0xFFFFULL : 0xFFFFFFFFULL; + + timer_source_div_t best_div = TIMER_SOURCE_DIV_1; + uint32_t period_counts = 0; + bool needs_reopen = false; + + if (obj->timer_type == PWM_TIMER_TYPE_GPT) { + // PCLKD Frequency (GPT Clock Source) + uint32_t pclkd_freq = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD); + + // GPT Prescaler List: Div 1, 2, 4, 8, 16, 32, 64, 256, 1024 + static const timer_source_div_t gpt_divs[] = { + TIMER_SOURCE_DIV_1, TIMER_SOURCE_DIV_2, TIMER_SOURCE_DIV_4, + TIMER_SOURCE_DIV_8, TIMER_SOURCE_DIV_16, TIMER_SOURCE_DIV_32, + TIMER_SOURCE_DIV_64, TIMER_SOURCE_DIV_128, TIMER_SOURCE_DIV_256, + TIMER_SOURCE_DIV_512, TIMER_SOURCE_DIV_1024 + }; + + for (size_t i = 0; i < sizeof(gpt_divs)/sizeof(gpt_divs[0]); i++) { + if(gpt_divs[i] == TIMER_SOURCE_DIV_128 || gpt_divs[i] == TIMER_SOURCE_DIV_512) { + // Skip unsupported divisors + continue; + } + uint32_t div_val = 1U << i; + uint64_t clk_hz = (uint64_t)pclkd_freq / div_val; + uint64_t counts = (clk_hz * (uint64_t)us) / 1000000ULL; + + if (counts <= max_count) { + best_div = gpt_divs[i]; + period_counts = (counts == 0) ? 1 : (uint32_t)counts; + break; + } + } + + if (obj->cfg.source_div != best_div) { + obj->cfg.source_div = best_div; + needs_reopen = true; + } + } + else { // AGT Timer + // Frequency mapping logic: Low frequency (< 500Hz, i.e., us >= 2000) uses LOCO/SUBCLOCK (32768Hz); High frequency uses PCLKB + if (us >= 2000) { + // Switch to LOCO/SUBCLOCK 32768Hz clock source + if (obj->ext_cfg.agt_ext.count_source != AGT_LOW_FREQ_CLOCK) { + obj->ext_cfg.agt_ext.count_source = AGT_LOW_FREQ_CLOCK; + needs_reopen = true; + } + + // AGT with LOCO/SUBCLOCK supports Div 1 to Div 128 + static const timer_source_div_t agt_loco_divs[] = { + TIMER_SOURCE_DIV_1, TIMER_SOURCE_DIV_2, TIMER_SOURCE_DIV_4, + TIMER_SOURCE_DIV_8, TIMER_SOURCE_DIV_16, TIMER_SOURCE_DIV_32, + TIMER_SOURCE_DIV_64, TIMER_SOURCE_DIV_128 + }; + + for (size_t i = 0; i < sizeof(agt_loco_divs)/sizeof(agt_loco_divs[0]); i++) { + uint32_t div_val = 1U << i; + uint64_t clk_hz = 32768ULL / div_val; + uint64_t counts = (clk_hz * (uint64_t)us) / 1000000ULL; + + if (counts <= max_count) { + best_div = agt_loco_divs[i]; + period_counts = (counts == 0) ? 1 : (uint32_t)counts; + break; + } + } + } else { + // Use PCLKB high-frequency clock source + if (obj->ext_cfg.agt_ext.count_source != AGT_CLOCK_PCLKB) { + obj->ext_cfg.agt_ext.count_source = AGT_CLOCK_PCLKB; + needs_reopen = true; + } + + uint32_t pclkb_freq = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + // AGT with PCLKB supports Div 1, 2, 4, 8 + static const timer_source_div_t agt_pclkb_divs[] = { + TIMER_SOURCE_DIV_1, TIMER_SOURCE_DIV_2, TIMER_SOURCE_DIV_4, TIMER_SOURCE_DIV_8 + }; + + for (size_t i = 0; i < sizeof(agt_pclkb_divs)/sizeof(agt_pclkb_divs[0]); i++) { + uint32_t div_val = 1U << i; + uint64_t clk_hz = (uint64_t)pclkb_freq / div_val; + uint64_t counts = (clk_hz * (uint64_t)us) / 1000000ULL; + + if (counts <= max_count) { + best_div = agt_pclkb_divs[i]; + period_counts = (counts == 0) ? 1 : (uint32_t)counts; + break; + } + } + } + + if (obj->cfg.source_div != best_div) { + obj->cfg.source_div = best_div; + needs_reopen = true; + } + } + + // Defensive fallback: Clamp to max counter value if limits are exceeded and run at current prescaler + if (period_counts == 0) { + period_counts = (uint32_t)max_count; + } + + obj->cfg.period_counts = period_counts; + + /* Re-apply settings via Close -> Open if prescaler (source_div) or clock source (count_source) has changed */ + if (needs_reopen && obj->initialized) { + obj->p_timer->p_api->stop(obj->p_timer->p_ctrl); + obj->p_timer->p_api->close(obj->p_timer->p_ctrl); + + fsp_err_t err = obj->p_timer->p_api->open(obj->p_timer->p_ctrl, &obj->cfg); + MBED_ASSERT(FSP_SUCCESS == err); + + obj->p_timer->p_api->start(obj->p_timer->p_ctrl); + } else { + // Update period directly if neither prescaler nor clock source has changed + fsp_err_t err = obj->p_timer->p_api->periodSet(obj->p_timer->p_ctrl, period_counts); + MBED_ASSERT(FSP_SUCCESS == err); + } + + obj->period_counts = period_counts; + + if (obj->duty_counts > 0) { + float duty = (float) obj->duty_counts / (float) obj->period_counts; + pwmout_write(obj, duty); + } +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +void pwmout_write(pwmout_t *obj, float value) +{ + MBED_ASSERT(obj && obj->p_timer); + + if (value < 0.0f) value = 0.0f; + if (value > 1.0f) value = 1.0f; + + if (obj->period_counts == 0) { + pwmout_period_us(obj, 1000); + } + + uint32_t duty = (uint32_t)((float) obj->period_counts * value); + if(duty >= obj->period_counts) + { + duty = obj->period_counts - 1; + } + fsp_err_t err = obj->p_timer->p_api->dutyCycleSet( + obj->p_timer->p_ctrl, + duty, + obj->pwm_unit + ); + MBED_ASSERT(FSP_SUCCESS == err); + + obj->duty_counts = duty; +} + +float pwmout_read(pwmout_t *obj) +{ + MBED_ASSERT(obj); + + if (obj->period_counts == 0) { + return 0.0f; + } + + return (float) obj->duty_counts / (float) obj->period_counts; +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + MBED_ASSERT(obj && obj->p_timer); + + if (us <= 0) { + pwmout_write(obj, 0.0f); + return; + } + + timer_info_t info; + fsp_err_t err = obj->p_timer->p_api->infoGet(obj->p_timer->p_ctrl, &info); + MBED_ASSERT(FSP_SUCCESS == err); + + uint64_t counts = ((uint64_t) info.clock_frequency * (uint64_t) us) / 1000000ULL; + + if (obj->period_counts == 0) { + pwmout_period_us(obj, 1000); + } + + if (counts >= obj->period_counts) { + pwmout_write(obj, 1.0f); + } else { + float duty = (float) counts / (float) obj->period_counts; + pwmout_write(obj, duty); + } +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} + diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/bsp_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/bsp_api.h new file mode 100644 index 0000000000..d912bc0ed4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/bsp_api.h @@ -0,0 +1,101 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_API_H +#define BSP_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* FSP Common Includes. */ +#include "fsp_common_api.h" + +/* Gets MCU configuration information. */ +#include "bsp_cfg.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic push + +/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. + * We are not modifying these files so we will ignore these warnings temporarily. */ + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" +#endif + +/* Vector information for this project. This is generated by the tooling. */ +#include "../../src/bsp/mcu/all/bsp_exceptions.h" +#include "vector_data.h" + +/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ +#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" +#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic pop +#endif + +#if defined(BSP_API_OVERRIDE) + #include BSP_API_OVERRIDE +#else + +/* BSP Common Includes. */ + #include "../../src/bsp/mcu/all/bsp_common.h" + +/* BSP MCU Specific Includes. */ + #include "../../src/bsp/mcu/all/bsp_register_protection.h" + #include "../../src/bsp/mcu/all/bsp_irq.h" + #include "../../src/bsp/mcu/all/bsp_io.h" + #include "../../src/bsp/mcu/all/bsp_group_irq.h" + #include "../../src/bsp/mcu/all/bsp_clocks.h" + #include "../../src/bsp/mcu/all/bsp_module_stop.h" + #include "../../src/bsp/mcu/all/bsp_security.h" + +/* Factory MCU information. */ + #include "../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ + #include "../../src/bsp/mcu/all/bsp_delay.h" + #include "../../src/bsp/mcu/all/bsp_mcu_api.h" + + #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h") + #include "../../src/bsp/mcu/all/internal/bsp_internal.h" + #endif + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/fsp_common_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/fsp_common_api.h new file mode 100644 index 0000000000..2f55005c56 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/fsp_common_api.h @@ -0,0 +1,387 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_COMMON_API_H +#define FSP_COMMON_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/* Includes FSP version macros. */ +#include "fsp_version.h" + +/*******************************************************************************************************************//** + * @ingroup RENESAS_COMMON + * @defgroup RENESAS_ERROR_CODES Common Error Codes + * All FSP modules share these common error codes. + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing + * about using this implementation is that it does not take any extra RAM or ROM. */ + +#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) + +/** Determine if a C++ compiler is being used. + * If so, ensure that standard C is used to process the API information. */ +#if defined(__cplusplus) + #define FSP_CPP_HEADER extern "C" { + #define FSP_CPP_FOOTER } +#else + #define FSP_CPP_HEADER + #define FSP_CPP_FOOTER +#endif + +/** FSP Header and Footer definitions */ +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically + * defined on the Secure side. */ +#define FSP_SECURE_ARGUMENT (NULL) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common error codes */ +typedef enum e_fsp_err +{ + FSP_SUCCESS = 0, + + FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed + FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location + FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter + FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist + FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode + FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API + FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open + FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy + FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h + FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked + FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP + FSP_ERR_OVERFLOW = 12, ///< Hardware overflow + FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow + FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration + FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result + FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason + FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met + FSP_ERR_ABORTED = 18, ///< An operation was aborted + FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled + FSP_ERR_TIMEOUT = 20, ///< Timeout error + FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied + FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied + FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation + FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed + FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed + FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made + FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition + FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU + FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state + FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed + FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed + FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete + FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found + FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback + FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer + FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed + + /* Start of RTOS only error codes */ + FSP_ERR_INTERNAL = 100, ///< Internal error + FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted + + /* Start of UART specific */ + FSP_ERR_FRAMING = 200, ///< Framing error occurs + FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects + FSP_ERR_PARITY = 202, ///< Parity error occurs + FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow + FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue + FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer + FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer + + /* Start of SPI specific */ + FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. + FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. + FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. + FSP_ERR_SPI_PARITY = 303, ///< Parity error. + FSP_ERR_OVERRUN = 304, ///< Overrun error. + + /* Start of CGC Specific */ + FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. + FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. + FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off + FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off + FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled + FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set + FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active + FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit + FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled + FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out + FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode + + /* Start of FLASH Specific */ + FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. + FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state + FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz + FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory + FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed + FSP_ERR_HUK_ZEROIZATION = 505, ///< W-HUK zeroization is in progress + + /* Start of CAC Specific */ + FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate + + /* Start of IIRFA Specific */ + FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. + + /* Start of GLCD Specific */ + FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock + FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter + FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter + FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found + FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter + FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer + FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update + FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry + FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting + FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter + + /* Start of JPEG Specific */ + FSP_ERR_JPEG_ERR = 1100, ///< JPEG error + FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. + FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. + FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. + FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. + FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. + FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. + FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. + FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. + FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. + FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) + FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. + FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. + FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. + FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough + FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU + + /* Start of touch panel framework specific */ + FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed + + /* Start of IIRFA specific */ + FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected + FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected + + /* Start of IP specific */ + FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device + FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device + FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device + + /* Start of USB specific */ + FSP_ERR_USB_FAILED = 1500, + FSP_ERR_USB_BUSY = 1501, + FSP_ERR_USB_SIZE_SHORT = 1502, + FSP_ERR_USB_SIZE_OVER = 1503, + FSP_ERR_USB_NOT_OPEN = 1504, + FSP_ERR_USB_NOT_SUSPEND = 1505, + FSP_ERR_USB_PARAMETER = 1506, + + /* Start of Message framework specific */ + FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool + FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool + FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid + FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid + FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many + FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found + FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue + FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue + FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal + FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released + + /* Start of 2DG Driver specific */ + FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering + FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering + + /* Start of ETHER Driver specific */ + FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. + FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled + FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty + FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable + FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication + FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. + + /* Start of ETHER_PHY Driver specific */ + FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. + FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation + + /* Start of BYTEQ library specific */ + FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data + FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue + + /* Start of CTSU Driver specific */ + FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. + FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. + FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. + FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. + FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. + FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. + FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. + FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. + FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. + FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. + FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. + FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. + FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. + FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. + FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. + FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. + + /* Start of SDMMC specific */ + FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. + FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. + FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. + FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. + FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. + FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. + FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. + + /* Start of FX_IO specific */ + FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. + FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. + + /* Start of CAN specific */ + FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. + FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. + FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. + FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. + FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. + FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. + FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. + FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. + + /* Start of SF_WIFI Specific */ + FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. + FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. + FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed + FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode + FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. + FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. + FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point + FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16XXX Unknown AT command Error + FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16XXX Insufficient parameter + FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16XXX Too many parameters + FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16XXX Wrong parameter value + FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16XXX No result + FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16XXX Response buffer overflow + FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16XXX Function is not configured + FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16XXX NVRAM write failure + FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16XXX Retention memory write failure + FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16XXX unknown error + + /* Start of SF_CELLULAR Specific */ + FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. + FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. + FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed + FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate + FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed + FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. + FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. + FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed + + /* Start of SF_BLE specific */ + FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed + FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed + FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed + FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled + FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled + + /* Start of SF_BLE_ABS specific */ + FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. + FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. + + /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ + FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function + FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy + FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty + FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index + FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry + FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed + FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened + FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized + FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred + FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter + FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented + FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified + FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred + FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid + FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state + FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened + FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. + FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher + FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal. + FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. + FSP_ERR_CRYPTO_SCE_PASS_1 = 0x10016, // Private SCE return code + FSP_ERR_CRYPTO_SCE_PASS_2 = 0x10017, // Private SCE return code + + FSP_ERR_CRYPTO_SCE_LBIST_CHECK_BUSY = 0x100ff, ///< LBIST Check BUSY + + /* Start of Crypto RSIP specific (0x10100) */ + FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy + FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return + FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error + FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal + FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed + + FSP_ERR_CRYPTO_RSIP_LBIST_CHECK_BUSY = 0x101ff, ///< LBIST Check BUSY + + /* Start of SF_CRYPTO specific */ + FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened + FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error + FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key + FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold + FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. + FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. + FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. + + /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. + * Refer to sf_cryoto_err.h for Crypto error codes. + */ + + /* Start of Sensor specific */ + FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. + FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. + FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. + + /* Start of COMMS specific */ + FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. +} fsp_err_t; + +/** @} */ + +/*********************************************************************************************************************** + * Function prototypes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_adc_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_adc_api.h new file mode 100644 index 0000000000..54b75d2c23 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_adc_api.h @@ -0,0 +1,381 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_ADC_API_H +#define R_ADC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_ANALOG_INTERFACES + * @defgroup ADC_API ADC Interface + * @brief Interface for A/D Converters. + * + * @section ADC_API_SUMMARY Summary + * The ADC interface provides standard ADC functionality including one-shot mode (single scan), continuous scan and + * group scan. It also allows configuration of hardware and software triggers for starting scans. After each conversion + * an interrupt can be triggered, and if a callback function is provided, the call back is invoked with the + * appropriate event information. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#ifndef BSP_OVERRIDE_ADC_INCLUDE + #include "r_elc_api.h" +#endif +#include "r_transfer_api.h" + +#if __has_include("r_adc_device_types.h") + #include "r_adc_device_types.h" +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/***************************************************************************** + * Typedef definitions + ******************************************************************************/ +#ifndef BSP_OVERRIDE_ADC_MODE_T + +/** ADC operation mode definitions */ +typedef enum e_adc_mode +{ + ADC_MODE_SINGLE_SCAN = 0, ///< Single scan - one or more channels + ADC_MODE_GROUP_SCAN = 1, ///< Two trigger sources to trigger scan for two groups which contain one or more channels + ADC_MODE_CONTINUOUS_SCAN = 2, ///< Continuous scan - one or more channels +} adc_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_ADC_RESOLUTION_T + +/** ADC data resolution definitions */ +typedef enum e_adc_resolution +{ + ADC_RESOLUTION_12_BIT = 0, ///< 12 bit resolution + ADC_RESOLUTION_10_BIT = 1, ///< 10 bit resolution + ADC_RESOLUTION_8_BIT = 2, ///< 8 bit resolution + ADC_RESOLUTION_14_BIT = 3, ///< 14 bit resolution + ADC_RESOLUTION_16_BIT = 4, ///< 16 bit resolution + ADC_RESOLUTION_24_BIT = 5, ///< 24 bit resolution +} adc_resolution_t; +#endif + +/** ADC data alignment definitions */ +typedef enum e_adc_alignment +{ + ADC_ALIGNMENT_RIGHT = 0, ///< Data alignment right + ADC_ALIGNMENT_LEFT = 1 ///< Data alignment left +} adc_alignment_t; + +#ifndef BSP_OVERRIDE_ADC_TRIGGER_T + +/** ADC trigger mode definitions */ +typedef enum e_adc_trigger +{ + ADC_TRIGGER_SOFTWARE = 0, ///< Software trigger; not for group modes + ADC_TRIGGER_SYNC_ELC = 2, ///< Synchronous trigger via ELC + ADC_TRIGGER_ASYNC_EXTERNAL = 3, ///< External asynchronous trigger; not for group modes +} adc_trigger_t; + +#endif + +#ifndef BSP_OVERRIDE_ADC_EVENT_T + +/** ADC callback event definitions */ +typedef enum e_adc_event +{ + ADC_EVENT_SCAN_COMPLETE, ///< Normal/Group A scan complete + ADC_EVENT_SCAN_COMPLETE_GROUP_B, ///< Group B scan complete + ADC_EVENT_SCAN_COMPLETE_GROUP_C, ///< Group C scan complete + ADC_EVENT_CALIBRATION_COMPLETE, ///< Calibration complete + ADC_EVENT_CONVERSION_COMPLETE, ///< Conversion complete + ADC_EVENT_CALIBRATION_REQUEST, ///< Calibration requested + ADC_EVENT_CONVERSION_ERROR, ///< Scan error + ADC_EVENT_OVERFLOW, ///< Overflow occurred + ADC_EVENT_LIMIT_CLIP, ///< Limiter clipping occurred + ADC_EVENT_FIFO_READ_REQUEST, ///< FIFO read requested + ADC_EVENT_FIFO_OVERFLOW, ///< FIFO overflow occurred + ADC_EVENT_WINDOW_COMPARE_A, ///< Window A comparison condition met + ADC_EVENT_WINDOW_COMPARE_B, ///< Window B comparison condition met + ADC_EVENT_ZERO_CROSS_DETECTION, ///< Zero-cross detection interrupt + ADC_EVENT_CAPTURE_A, ///< Capture A conversion complete + ADC_EVENT_CAPTURE_B, ///< Capture B conversion complete +} adc_event_t; + +#endif + +#ifndef BSP_OVERRIDE_ADC_CHANNEL_T + +/** ADC channels */ +typedef enum e_adc_channel +{ + ADC_CHANNEL_0 = 0, ///< ADC channel 0 + ADC_CHANNEL_1 = 1, ///< ADC channel 1 + ADC_CHANNEL_2 = 2, ///< ADC channel 2 + ADC_CHANNEL_3 = 3, ///< ADC channel 3 + ADC_CHANNEL_4 = 4, ///< ADC channel 4 + ADC_CHANNEL_5 = 5, ///< ADC channel 5 + ADC_CHANNEL_6 = 6, ///< ADC channel 6 + ADC_CHANNEL_7 = 7, ///< ADC channel 7 + ADC_CHANNEL_8 = 8, ///< ADC channel 8 + ADC_CHANNEL_9 = 9, ///< ADC channel 9 + ADC_CHANNEL_10 = 10, ///< ADC channel 10 + ADC_CHANNEL_11 = 11, ///< ADC channel 11 + ADC_CHANNEL_12 = 12, ///< ADC channel 12 + ADC_CHANNEL_13 = 13, ///< ADC channel 13 + ADC_CHANNEL_14 = 14, ///< ADC channel 14 + ADC_CHANNEL_15 = 15, ///< ADC channel 15 + ADC_CHANNEL_16 = 16, ///< ADC channel 16 + ADC_CHANNEL_17 = 17, ///< ADC channel 17 + ADC_CHANNEL_18 = 18, ///< ADC channel 18 + ADC_CHANNEL_19 = 19, ///< ADC channel 19 + ADC_CHANNEL_20 = 20, ///< ADC channel 20 + ADC_CHANNEL_21 = 21, ///< ADC channel 21 + ADC_CHANNEL_22 = 22, ///< ADC channel 22 + ADC_CHANNEL_23 = 23, ///< ADC channel 23 + ADC_CHANNEL_24 = 24, ///< ADC channel 24 + ADC_CHANNEL_25 = 25, ///< ADC channel 25 + ADC_CHANNEL_26 = 26, ///< ADC channel 26 + ADC_CHANNEL_27 = 27, ///< ADC channel 27 + ADC_CHANNEL_28 = 28, ///< ADC channel 28 + ADC_CHANNEL_DUPLEX_A = 50, ///< Data duplexing register A + ADC_CHANNEL_DUPLEX_B = 51, ///< Data duplexing register B + ADC_CHANNEL_DUPLEX = -4, ///< Data duplexing register + ADC_CHANNEL_TEMPERATURE = -3, ///< Temperature sensor output + ADC_CHANNEL_VOLT = -2, ///< Internal reference voltage +} adc_channel_t; + +#endif + +typedef enum e_adc_group_id +{ + ADC_GROUP_ID_0 = 0, ///< Group ID 0 + ADC_GROUP_ID_1 = 1, ///< Group ID 1 + ADC_GROUP_ID_2 = 2, ///< Group ID 2 + ADC_GROUP_ID_3 = 3, ///< Group ID 3 + ADC_GROUP_ID_4 = 4, ///< Group ID 4 + ADC_GROUP_ID_5 = 5, ///< Group ID 5 + ADC_GROUP_ID_6 = 6, ///< Group ID 6 + ADC_GROUP_ID_7 = 7, ///< Group ID 7 + ADC_GROUP_ID_8 = 8, ///< Group ID 8 +} adc_group_id_t; + +typedef enum e_adc_group_mask +{ + ADC_GROUP_MASK_NONE = 0x000, ///< Group Mask Unknown or None + ADC_GROUP_MASK_0 = 0x001, ///< Group Mask 0 + ADC_GROUP_MASK_1 = 0x002, ///< Group Mask 1 + ADC_GROUP_MASK_2 = 0x004, ///< Group Mask 2 + ADC_GROUP_MASK_3 = 0x008, ///< Group Mask 3 + ADC_GROUP_MASK_4 = 0x010, ///< Group Mask 4 + ADC_GROUP_MASK_5 = 0x020, ///< Group Mask 5 + ADC_GROUP_MASK_6 = 0x040, ///< Group Mask 6 + ADC_GROUP_MASK_7 = 0x080, ///< Group Mask 7 + ADC_GROUP_MASK_8 = 0x100, ///< Group Mask 8 + ADC_GROUP_MASK_ALL = 0x1FF, ///< All Groups +} adc_group_mask_t; + +/** ADC states. */ +typedef enum e_adc_state +{ + ADC_STATE_IDLE = 0, ///< ADC is idle + ADC_STATE_SCAN_IN_PROGRESS = 1, ///< ADC scan in progress + ADC_STATE_CALIBRATION_IN_PROGRESS = 2, ///< ADC calibration in progress - Not used by all ADC instances +} adc_state_t; + +/** ADC status. */ +typedef struct st_adc_status +{ + adc_state_t state; ///< Current state +} adc_status_t; + +/** ADC callback arguments definitions */ +typedef struct st_adc_callback_args +{ + uint16_t unit; ///< ADC device in use + adc_event_t event; ///< ADC callback event + void * p_context; ///< Placeholder for user data + adc_channel_t channel; ///< Channel of conversion result + uint64_t channel_mask; ///< Channel mask for conversion result. Only valid for r_adc_b and r_sdadc_b + adc_group_mask_t group_mask; ///< Group Mask +} adc_callback_args_t; + +#ifndef BSP_OVERRIDE_ADC_INFO_T + +/** ADC Information Structure for Transfer Interface */ +typedef struct st_adc_info +{ + __I void * p_address; ///< The address to start reading the data from + uint32_t length; ///< The total number of transfers to read + + transfer_size_t transfer_size; ///< The size of each transfer + elc_peripheral_t elc_peripheral; ///< Name of the peripheral in the ELC list + elc_event_t elc_event; ///< Name of the ELC event for the peripheral + uint32_t calibration_data; ///< Temperature sensor calibration data (0xFFFFFFFF if unsupported) for reference voltage + uint16_t room_calibration_data; ///< Room temperature sensor calibration data (0xFFFFFFFF if unsupported) for reference voltage + uint16_t low_calibration_data; ///< Low temperature sensor calibration data (0xFFFFFFFF if unsupported) for reference voltage + int16_t slope_microvolts; ///< Temperature sensor slope in microvolts/degrees C +} adc_info_t; + +#endif + +/** ADC general configuration */ +typedef struct st_adc_cfg +{ + uint16_t unit; ///< ADC unit to be used + adc_mode_t mode; ///< ADC operation mode + adc_resolution_t resolution; ///< ADC resolution + adc_alignment_t alignment; ///< Specify left or right alignment; ignored if addition used + adc_trigger_t trigger; ///< Default and Group A trigger source + IRQn_Type scan_end_irq; ///< Scan end IRQ number + IRQn_Type scan_end_b_irq; ///< Scan end group B IRQ number + IRQn_Type scan_end_c_irq; ///< Scan end group C IRQ number + uint8_t scan_end_ipl; ///< Scan end interrupt priority + uint8_t scan_end_b_ipl; ///< Scan end group B interrupt priority + uint8_t scan_end_c_ipl; ///< Scan end group C interrupt priority + void (* p_callback)(adc_callback_args_t * p_args); ///< Callback function; set to NULL for none + void * p_context; ///< Placeholder for user data. Passed to the user callback in @ref adc_callback_args_t. + void const * p_extend; ///< Extension parameter for hardware specific settings +} adc_cfg_t; + +/** ADC control block. Allocate using driver instance control structure from driver instance header file. */ +typedef void adc_ctrl_t; + +/** ADC functions implemented at the HAL layer will follow this API. */ +typedef struct st_adc_api +{ + /** Initialize ADC Unit; apply power, set the operational mode, trigger sources, interrupt priority, + * and configurations common to all channels and sensors. + * + * @pre Configure peripheral clocks, ADC pins and IRQs prior to calling this function. + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] p_cfg Pointer to configuration structure + */ + fsp_err_t (* open)(adc_ctrl_t * const p_ctrl, adc_cfg_t const * const p_cfg); + + /** Configure the scan including the channels, groups, and scan triggers to be used for the unit that + * was initialized in the open call. Some configurations are not supported for all implementations. + * See implementation for details. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] p_extend See implementation for details + */ + fsp_err_t (* scanCfg)(adc_ctrl_t * const p_ctrl, void const * const p_extend); + + /** Start the scan (in case of a software trigger), or enable the hardware trigger. + * + * @param[in] p_ctrl Pointer to control handle structure + */ + fsp_err_t (* scanStart)(adc_ctrl_t * const p_ctrl); + + /** Start the scan group (in case of a software trigger), or enable the hardware trigger. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] group_mask Mask of groups to start + */ + fsp_err_t (* scanGroupStart)(adc_ctrl_t * p_ctrl, adc_group_mask_t group_mask); + + /** Stop the ADC scan (in case of a software trigger), or disable the hardware trigger. + * + * @param[in] p_ctrl Pointer to control handle structure + */ + fsp_err_t (* scanStop)(adc_ctrl_t * const p_ctrl); + + /** Check scan status. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_status Pointer to store current status in + */ + fsp_err_t (* scanStatusGet)(adc_ctrl_t * const p_ctrl, adc_status_t * p_status); + + /** Read ADC conversion result. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) + * @param[in] p_data Pointer to variable to load value into. + */ + fsp_err_t (* read)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data); + + /** Read ADC conversion result into a 32-bit word. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) + * @param[in] p_data Pointer to variable to load value into. + */ + fsp_err_t (* read32)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data); + + /** Calibrate ADC or associated PGA (programmable gain amplifier). The driver may require implementation specific + * arguments to the p_extend input. Not supported for all implementations. See implementation for details. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] p_extend Pointer to implementation specific arguments + */ + fsp_err_t (* calibrate)(adc_ctrl_t * const p_ctrl, void const * p_extend); + + /** Set offset for input PGA configured for differential input. Not supported for all implementations. + * See implementation for details. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t) + * @param[in] offset See implementation for details. + */ + fsp_err_t (* offsetSet)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t const offset); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the ADC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(adc_ctrl_t * const p_ctrl, void (* p_callback)(adc_callback_args_t *), + void * const p_context, adc_callback_args_t * const p_callback_memory); + + /** Close the specified ADC unit by ending any scan in progress, disabling interrupts, and removing power to the + * specified A/D unit. + * + * @param[in] p_ctrl Pointer to control handle structure + */ + fsp_err_t (* close)(adc_ctrl_t * const p_ctrl); + + /** Return the ADC data register address of the first (lowest number) channel and the total number of bytes + * to be read in order for the DTC/DMAC to read the conversion results of all configured channels. + * Return the temperature sensor calibration and slope data. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_adc_info Pointer to ADC information structure + */ + fsp_err_t (* infoGet)(adc_ctrl_t * const p_ctrl, adc_info_t * const p_adc_info); +} adc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_adc_instance +{ + adc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + adc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + void const * p_channel_cfg; ///< Pointer to the channel configuration structure for this instance + adc_api_t const * p_api; ///< Pointer to the API structure for this instance +} adc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup ADC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cac_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cac_api.h new file mode 100644 index 0000000000..a952332308 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cac_api.h @@ -0,0 +1,219 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CAC_API_H +#define R_CAC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_MONITORING_INTERFACES + * @defgroup CAC_API CAC Interface + * @brief Interface for clock frequency accuracy measurements. + * + * @section CAC_API_SUMMARY Summary + * The interface for the clock frequency accuracy measurement circuit (CAC) peripheral is used to check a system + * clock frequency with a reference clock signal by counting the number of pulses of the clock to be measured. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Event types returned by the ISR callback when used in CAC interrupt mode */ +typedef enum e_cac_event +{ + CAC_EVENT_FREQUENCY_ERROR, ///< Frequency error + CAC_EVENT_MEASUREMENT_COMPLETE, ///< Measurement complete + CAC_EVENT_COUNTER_OVERFLOW ///< Counter overflow +} cac_event_t; + +/** CAC control block. Allocate an instance specific control block to pass into the CAC API calls. + */ +typedef void cac_ctrl_t; + +/** Enumeration of the two possible clocks. */ +typedef enum e_cac_clock_type +{ + CAC_CLOCK_MEASURED, ///< Measurement clock + CAC_CLOCK_REFERENCE ///< Reference clock +} cac_clock_type_t; + +#ifndef BSP_OVERRIDE_CAC_CLOCK_SOURCE_T + +/** Enumeration of the possible clock sources for both the reference and measurement clocks. */ +typedef enum e_cac_clock_source +{ + CAC_CLOCK_SOURCE_MAIN_OSC = 0x00, ///< Main clock oscillator + CAC_CLOCK_SOURCE_SUBCLOCK = 0x01, ///< Sub-clock + CAC_CLOCK_SOURCE_HOCO = 0x02, ///< HOCO (High speed on chip oscillator) + CAC_CLOCK_SOURCE_MOCO = 0x03, ///< MOCO (Middle speed on chip oscillator) + CAC_CLOCK_SOURCE_LOCO = 0x04, ///< LOCO (Low speed on chip oscillator) + CAC_CLOCK_SOURCE_PCLKB = 0x05, ///< PCLKB (Peripheral Clock B) + CAC_CLOCK_SOURCE_IWDT = 0x06, ///< IWDT-dedicated on-chip oscillator + CAC_CLOCK_SOURCE_EXTERNAL = 0x07, ///< Externally supplied measurement clock on CACREF pin +} cac_clock_source_t; +#endif + +#ifndef BSP_OVERRIDE_CAC_REF_DIVIDER_T + +/** Enumeration of available dividers for the reference clock. */ +typedef enum e_cac_ref_divider +{ + CAC_REF_DIV_32 = 0x00, ///< Reference clock divided by 32 + CAC_REF_DIV_128 = 0x01, ///< Reference clock divided by 128 + CAC_REF_DIV_1024 = 0x02, ///< Reference clock divided by 1024 + CAC_REF_DIV_8192 = 0x03, ///< Reference clock divided by 8192 +} cac_ref_divider_t; +#endif + +/** Enumeration of available digital filter settings for an external reference clock. */ +typedef enum e_cac_ref_digfilter +{ + CAC_REF_DIGITAL_FILTER_OFF = 0x00, ///< No digital filter on the CACREF pin for reference clock + CAC_REF_DIGITAL_FILTER_1 = 0x01, ///< Sampling clock for digital filter = measuring frequency + CAC_REF_DIGITAL_FILTER_4 = 0x02, ///< Sampling clock for digital filter = measuring frequency/4 + CAC_REF_DIGITAL_FILTER_16 = 0x03, ///< Sampling clock for digital filter = measuring frequency/16 +} cac_ref_digfilter_t; + +/** Enumeration of available edge detect settings for the reference clock. */ +typedef enum e_cac_ref_edge +{ + CAC_REF_EDGE_RISE = 0x00, ///< Rising edge detect for the Reference clock + CAC_REF_EDGE_FALL = 0x01, ///< Falling edge detect for the Reference clock + CAC_REF_EDGE_BOTH = 0x02 ///< Both Rising and Falling edges detect for the Reference clock +} cac_ref_edge_t; + +#ifndef BSP_OVERRIDE_CAC_MEAS_DIVIDER_T + +/** Enumeration of available dividers for the measurement clock */ +typedef enum e_cac_meas_divider +{ + CAC_MEAS_DIV_1 = 0x00, ///< Measurement clock divided by 1 + CAC_MEAS_DIV_4 = 0x01, ///< Measurement clock divided by 4 + CAC_MEAS_DIV_8 = 0x02, ///< Measurement clock divided by 8 + CAC_MEAS_DIV_32 = 0x03 ///< Measurement clock divided by 32 +} cac_meas_divider_t; +#endif + +/** Structure defining the settings that apply to reference clock configuration. */ +typedef struct st_cac_ref_clock_config +{ + cac_ref_divider_t divider; ///< Divider specification for the Reference clock + cac_clock_source_t clock; ///< Clock source for the Reference clock + cac_ref_digfilter_t digfilter; ///< Digital filter selection for the CACREF ext clock + cac_ref_edge_t edge; ///< Edge detection for the Reference clock +} cac_ref_clock_config_t; + +/** Structure defining the settings that apply to measurement clock configuration. */ +typedef struct st_cac_meas_clock_config +{ + cac_meas_divider_t divider; ///< Divider specification for the Measurement clock + cac_clock_source_t clock; ///< Clock source for the Measurement clock +} cac_meas_clock_config_t; + +/** Callback function parameter data */ +typedef struct st_cac_user_cb_data +{ + cac_event_t event; ///< The event can be used to identify what caused the callback. + void * p_context; ///< Value provided in configuration structure. +} cac_callback_args_t; + +/** CAC Configuration */ +typedef struct st_cac_cfg +{ + cac_ref_clock_config_t cac_ref_clock; ///< Reference clock specific settings + cac_meas_clock_config_t cac_meas_clock; ///< Measurement clock specific settings + uint16_t cac_upper_limit; ///< The upper limit counter threshold + uint16_t cac_lower_limit; ///< The lower limit counter threshold + + IRQn_Type mendi_irq; ///< Measurement End IRQ number + IRQn_Type ovfi_irq; ///< Measurement Overflow IRQ number + IRQn_Type ferri_irq; ///< Frequency Error IRQ number + + uint8_t mendi_ipl; ///< Measurement end interrupt priority + uint8_t ovfi_ipl; ///< Overflow interrupt priority + uint8_t ferri_ipl; ///< Frequency error interrupt priority + + void (* p_callback)(cac_callback_args_t * p_args); ///< Callback provided when a CAC interrupt ISR occurs. + void * p_context; ///< Passed to user callback in @ref cac_callback_args_t. + + void const * p_extend; ///< CAC hardware dependent configuration */ +} cac_cfg_t; + +/** CAC functions implemented at the HAL layer API */ +typedef struct st_cac_api +{ + /** Open function for CAC device. + * @param[out] p_ctrl Pointer to CAC device control. Must be declared by user. + * @param[in] cac_cfg_t Pointer to CAC configuration structure. + */ + fsp_err_t (* open)(cac_ctrl_t * const p_ctrl, cac_cfg_t const * const p_cfg); + + /** Begin a measurement for the CAC peripheral. + * @param[in] p_ctrl Pointer to CAC device control. + */ + fsp_err_t (* startMeasurement)(cac_ctrl_t * const p_ctrl); + + /** End a measurement for the CAC peripheral. + * @param[in] p_ctrl Pointer to CAC device control. + */ + fsp_err_t (* stopMeasurement)(cac_ctrl_t * const p_ctrl); + + /** Read function for CAC peripheral. + * @param[in] p_ctrl Control for the CAC device context. + * @param[in] p_counter Pointer to variable in which to store the current CACNTBR register contents. + */ + fsp_err_t (* read)(cac_ctrl_t * const p_ctrl, uint32_t * const p_counter); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref cac_api_t::open call + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(cac_ctrl_t * const p_ctrl, void (* p_callback)(cac_callback_args_t *), + void * const p_context, cac_callback_args_t * const p_callback_memory); + + /** Close function for CAC device. + * @param[in] p_ctrl Pointer to CAC device control. + */ + fsp_err_t (* close)(cac_ctrl_t * const p_ctrl); +} cac_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_cac_instance +{ + cac_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + cac_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + cac_api_t const * p_api; ///< Pointer to the API structure for this instance +} cac_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup CAC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_can_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_can_api.h new file mode 100644 index 0000000000..ff6a1b4cd8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_can_api.h @@ -0,0 +1,270 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CAN_API_H +#define R_CAN_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup CAN_API CAN Interface + * @brief Interface for CAN peripheral + * + * @section CAN_INTERFACE_SUMMARY Summary + * The CAN interface provides common APIs for CAN HAL drivers. CAN interface supports following features. + * - Full-duplex CAN communication + * - Generic CAN parameter setting + * - Interrupt driven transmit/receive processing + * - Callback function support with returning event code + * - Hardware resource locking during a transaction + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#if BSP_FEATURE_CANFD_NUM_CHANNELS + #define CAN_DATA_BUFFER_LENGTH (64) +#else + #define CAN_DATA_BUFFER_LENGTH (8) +#endif + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_CAN_EVENT_T + +/** CAN event codes */ +typedef enum e_can_event +{ + CAN_EVENT_ERR_WARNING = 0x0002, ///< Error Warning event. + CAN_EVENT_ERR_PASSIVE = 0x0004, ///< Error Passive event. + CAN_EVENT_ERR_BUS_OFF = 0x0008, ///< Bus Off event. + CAN_EVENT_BUS_RECOVERY = 0x0010, ///< Bus Off Recovery event. + CAN_EVENT_MAILBOX_MESSAGE_LOST = 0x0020, ///< Mailbox has been overrun. + CAN_EVENT_ERR_BUS_LOCK = 0x0080, ///< Bus lock detected (32 consecutive dominant bits). + CAN_EVENT_ERR_CHANNEL = 0x0100, ///< Channel error has occurred. + CAN_EVENT_TX_ABORTED = 0x0200, ///< Transmit abort event. + CAN_EVENT_RX_COMPLETE = 0x0400, ///< Receive complete event. + CAN_EVENT_TX_COMPLETE = 0x0800, ///< Transmit complete event. + CAN_EVENT_ERR_GLOBAL = 0x1000, ///< Global error has occurred. + CAN_EVENT_TX_FIFO_EMPTY = 0x2000, ///< Transmit FIFO is empty. + CAN_EVENT_FIFO_MESSAGE_LOST = 0x4000, ///< Receive FIFO overrun. +} can_event_t; + +#endif + +/** CAN Operation modes */ +typedef enum e_can_operation_mode +{ + CAN_OPERATION_MODE_NORMAL = 0, ///< CAN Normal Operation Mode + CAN_OPERATION_MODE_RESET, ///< CAN Reset Operation Mode + CAN_OPERATION_MODE_HALT, ///< CAN Halt Operation Mode + CAN_OPERATION_MODE_SLEEP = 5, ///< CAN Sleep Operation Mode + CAN_OPERATION_MODE_GLOBAL_OPERATION = 0x80, // CANFD Global Operation Mode + CAN_OPERATION_MODE_GLOBAL_RESET, // CANFD Global Reset Mode + CAN_OPERATION_MODE_GLOBAL_HALT, // CANFD Global Halt Mode + CAN_OPERATION_MODE_GLOBAL_SLEEP = 0x85 // CANFD Global Sleep Mode +} can_operation_mode_t; + +/** CAN Test modes */ +typedef enum e_can_test_mode +{ + CAN_TEST_MODE_DISABLED = 0, ///< CAN Test Mode Disabled. + CAN_TEST_MODE_LISTEN = 3, ///< CAN Test Listen Mode. + CAN_TEST_MODE_LOOPBACK_EXTERNAL = 5, ///< CAN Test External Loopback Mode. + CAN_TEST_MODE_LOOPBACK_INTERNAL = 7, ///< CAN Test Internal Loopback Mode. + CAN_TEST_MODE_INTERNAL_BUS = 0x80 ///< CANFD Internal CAN Bus Communication Test Mode. +} can_test_mode_t; + +#ifndef BSP_OVERRIDE_CAN_INFO_T + +/** CAN status info */ +typedef struct st_can_info +{ + uint32_t status; ///< Useful information from the CAN status register. + uint32_t rx_mb_status; ///< RX Message Buffer New Data flags. + uint32_t rx_fifo_status; ///< RX FIFO Empty flags. + uint8_t error_count_transmit; ///< Transmit error count. + uint8_t error_count_receive; ///< Receive error count. + uint32_t error_code; ///< Error code, cleared after reading. +} can_info_t; + +#endif + +#ifndef BSP_OVERRIDE_CAN_ID_MODE_T + +/** CAN ID modes */ +typedef enum e_can_id_mode +{ + CAN_ID_MODE_STANDARD, ///< Standard IDs of 11 bits used. + CAN_ID_MODE_EXTENDED, ///< Extended IDs of 29 bits used. +} can_id_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_CAN_FRAME_TYPE_T + +/** CAN frame types */ +typedef enum e_can_frame_type +{ + CAN_FRAME_TYPE_DATA, ///< Data frame. + CAN_FRAME_TYPE_REMOTE, ///< Remote frame. +} can_frame_type_t; + +#endif + +/** CAN bit rate configuration. */ +typedef struct st_can_bit_timing_cfg +{ + uint32_t baud_rate_prescaler; ///< Baud rate prescaler. Valid values: 1 - 1024. + uint32_t time_segment_1; ///< Time segment 1 control. + uint32_t time_segment_2; ///< Time segment 2 control. + uint32_t synchronization_jump_width; ///< Synchronization jump width. +} can_bit_timing_cfg_t; + +#ifndef BSP_OVERRIDE_CAN_FRAME_T + +/** CAN data Frame */ +typedef struct st_can_frame +{ + uint32_t id; ///< CAN ID. + can_id_mode_t id_mode; ///< Standard or Extended ID (IDE). + can_frame_type_t type; ///< Frame type (RTR). + uint8_t data_length_code; ///< CAN Data Length Code (DLC). + uint32_t options; ///< Implementation-specific options. + uint8_t data[CAN_DATA_BUFFER_LENGTH]; ///< CAN data. +} can_frame_t; + +#endif + +#ifndef BSP_OVERRIDE_CAN_CALLBACK_ARGS_T + +/** CAN callback parameter definition */ +typedef struct st_can_callback_args +{ + uint32_t channel; ///< Device channel number. + can_event_t event; ///< Event code. + uint32_t error; ///< Error code. + union + { + uint32_t mailbox; ///< Mailbox number of interrupt source. + uint32_t buffer; ///< Buffer number of interrupt source. + }; + void * p_context; ///< Context provided to user during callback. + can_frame_t frame; ///< Received frame data. +} can_callback_args_t; + +#endif + +/** CAN Configuration */ +typedef struct st_can_cfg +{ + /* CAN generic configuration */ + uint32_t channel; ///< CAN channel. + can_bit_timing_cfg_t * p_bit_timing; ///< CAN bit timing. + + /* Configuration for CAN Event processing */ + void (* p_callback)(can_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined callback context. + + /* Pointer to CAN peripheral specific configuration */ + void const * p_extend; ///< CAN hardware dependent configuration + uint8_t ipl; ///< Error/Transmit/Receive interrupt priority + IRQn_Type error_irq; ///< Error IRQ number + IRQn_Type rx_irq; ///< Receive IRQ number + IRQn_Type tx_irq; ///< Transmit IRQ number +} can_cfg_t; + +/** CAN control block. Allocate an instance specific control block to pass into the CAN API calls. + */ +typedef void can_ctrl_t; + +/** Shared Interface definition for CAN */ +typedef struct st_can_api +{ + /** Open function for CAN device + * + * @param[in,out] p_ctrl Pointer to the CAN control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to CAN configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(can_ctrl_t * const p_ctrl, can_cfg_t const * const p_cfg); + + /** Write function for CAN device + * @param[in] p_ctrl Pointer to the CAN control block. + * @param[in] buffer Buffer number (mailbox or message buffer) to write to. + * @param[in] p_frame Pointer for frame of CAN ID, DLC, data and frame type to write. + */ + fsp_err_t (* write)(can_ctrl_t * const p_ctrl, uint32_t buffer_number, can_frame_t * const p_frame); + + /** Read function for CAN device + * @param[in] p_ctrl Pointer to the CAN control block. + * @param[in] buffer Message buffer (number) to read from. + * @param[in] p_frame Pointer to store the CAN ID, DLC, data and frame type. + */ + fsp_err_t (* read)(can_ctrl_t * const p_ctrl, uint32_t buffer_number, can_frame_t * const p_frame); + + /** Close function for CAN device + * @param[in] p_ctrl Pointer to the CAN control block. + */ + fsp_err_t (* close)(can_ctrl_t * const p_ctrl); + + /** Mode Transition function for CAN device + * @param[in] p_ctrl Pointer to the CAN control block. + * @param[in] operation_mode Destination CAN operation state. + * @param[in] test_mode Destination CAN test state. + */ + fsp_err_t (* modeTransition)(can_ctrl_t * const p_ctrl, can_operation_mode_t operation_mode, + can_test_mode_t test_mode); + + /** Get CAN channel info. + * + * @param[in] p_ctrl Handle for channel (pointer to channel control block) + * @param[out] p_info Memory address to return channel specific data to. + */ + fsp_err_t (* infoGet)(can_ctrl_t * const p_ctrl, can_info_t * const p_info); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref can_api_t::open call. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(can_ctrl_t * const p_ctrl, void (* p_callback)(can_callback_args_t *), + void * const p_context, can_callback_args_t * const p_callback_memory); +} can_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_can_instance +{ + can_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + can_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + can_api_t const * p_api; ///< Pointer to the API structure for this instance +} can_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup CAN_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_capture_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_capture_api.h new file mode 100644 index 0000000000..35f8d762fd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_capture_api.h @@ -0,0 +1,146 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_GRAPHICS_INTERFACES + * @defgroup CAPTURE_API CAPTURE Interface + * @brief Interface for CAPTURE functions. + * + * @section CAPTURE_API_SUMMARY Summary + * The CAPTURE interface provides the functionality for capturing an image from an image sensor/camera. + * When a capture is complete a capture complete interrupt is triggered. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_CAPTURE_API_H +#define R_CAPTURE_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CAPTURE states. */ +typedef enum e_capture_state +{ + CAPTURE_STATE_IDLE = 0, ///< CAPTURE is idle + CAPTURE_STATE_IN_PROGRESS = 1, ///< CAPTURE capture in progress + CAPTURE_STATE_BUSY = 2, ///< CAPTURE reset in progress +} capture_state_t; + +/** CAPTURE status */ +typedef struct e_capture_status +{ + capture_state_t state; ///< Current capture state + uint32_t * p_buffer; ///< Pointer to active buffer + uint32_t data_size; ///< Size of data written to provided buffer +} capture_status_t; + +/** CAPTURE callback event ID - see implementation for details */ +typedef uint32_t capture_event_t; + +/** CAPTURE callback function parameter data */ +typedef struct st_capture_callback_args +{ + capture_event_t event; ///< Event causing the callback - See instance header for details. + uint32_t event_status; ///< Capture status data corresponding to given event type - See instance header for details. + uint32_t interrupt_status; ///< Module interrupt status data corresponding to given event type - See instance header for details. + uint8_t * p_buffer; ///< Pointer to buffer that contains the most recently captured data + void * p_context; ///< Placeholder for user data. Set in @ref capture_api_t::open function in @ref capture_cfg_t. +} capture_callback_args_t; + +/** CAPTURE configuration parameters. */ +typedef struct st_capture_cfg +{ + uint16_t x_capture_start_pixel; ///< Horizontal position to start capture + uint16_t x_capture_pixels; ///< Number of horizontal pixels to capture + uint16_t y_capture_start_pixel; ///< Vertical position to start capture + uint16_t y_capture_pixels; ///< Number of vertical lines/pixels to capture + uint8_t bytes_per_pixel; ///< Number of bytes per pixel + void (* p_callback)(capture_callback_args_t * p_args); ///< Callback provided when a CAPTURE transfer ISR occurs + void * p_context; ///< User defined context passed to callback function + void const * p_extend; ///< Extension parameter for hardware specific settings +} capture_cfg_t; + +/** CAPTURE control block. Allocate an instance specific control block to pass into the CAPTURE API calls. + */ +typedef void capture_ctrl_t; + +/** CAPTURE functions implemented at the HAL layer will follow this API. */ +typedef struct st_capture_api +{ + /** Initial configuration. + * + * @note To reconfigure after calling this function, call @ref capture_api_t::close first. + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(capture_ctrl_t * const p_ctrl, capture_cfg_t const * const p_cfg); + + /** Closes the driver and allows reconfiguration. May reduce power consumption. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(capture_ctrl_t * const p_ctrl); + + /** Start a capture. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buffer New pointer to store captured image data. + */ + fsp_err_t (* captureStart)(capture_ctrl_t * const p_ctrl, uint8_t * const p_buffer); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the CAPTURE control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(capture_ctrl_t * const p_ctrl, void (* p_callback)(capture_callback_args_t *), + void * const p_context, capture_callback_args_t * const p_callback_memory); + + /** Check scan status. + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_status Pointer to store current status in + */ + fsp_err_t (* statusGet)(capture_ctrl_t * const p_ctrl, capture_status_t * p_status); +} capture_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_capture_instance +{ + capture_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + capture_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + capture_api_t const * p_api; ///< Pointer to the API structure for this instance +} capture_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_CAPTURE_H + +/*******************************************************************************************************************//** + * @} (end addtogroup CAPTURE_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cec_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cec_api.h new file mode 100644 index 0000000000..7b6a4dfde6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cec_api.h @@ -0,0 +1,247 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CEC_API_H +#define R_CEC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup CEC_API CEC Interface + * @brief Interface for CEC peripheral + * + * @section CEC_INTERFACE_SUMMARY Summary + * The CEC interface provides common APIs for CEC HAL drivers and supports the following features: + * - Opening and closing the CEC module. + * - Allocation for full range of local address settings (TV, Recording Device, Playback Device, etc.) + * - Supports a user-callback function (required), invoked when transmit, receive, or error interrupts are received. + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_cec_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CEC Addresses */ +typedef enum e_cec_addr +{ + CEC_ADDR_TV = 0U, ///< CEC Address for TV + CEC_ADDR_RECORDING_DEVICE_1 = 1U, ///< CEC Address for Recording Device 1 + CEC_ADDR_RECORDING_DEVICE_2 = 2U, ///< CEC Address for Recording Device 2 + CEC_ADDR_TUNER_1 = 3U, ///< CEC Address for Tuner 1 + CEC_ADDR_PLAYBACK_DEVICE_1 = 4U, ///< CEC Address for Playback Device 1 + CEC_ADDR_AUDIO_SYSTEM = 5U, ///< CEC Address for Audio System + CEC_ADDR_TUNER_2 = 6U, ///< CEC Address for Tuner 2 + CEC_ADDR_TUNER_3 = 7U, ///< CEC Address for Tuner 3 + CEC_ADDR_PLAYBACK_DEVICE_2 = 8U, ///< CEC Address for Playback Device 2 + CEC_ADDR_RECORDING_DEVICE_3 = 9U, ///< CEC Address for Recording Device 3 + CEC_ADDR_TUNER_4 = 10U, ///< CEC Address for Tuner 4 + CEC_ADDR_PLAYBACK_DEVICE_3 = 11U, ///< CEC Address for Playback Device 3 + CEC_ADDR_SPECIFIC_USE = 14U, ///< CEC Address for Specific Use + CEC_ADDR_UNREGISTERED = 15U, ///< CEC Address for Unregistered Devices + CEC_ADDR_BROADCAST = 15U ///< CEC Broadcast message +} cec_addr_t; + +/** CEC Source Clock */ +typedef enum e_cec_clock_source +{ + CEC_CLOCK_SOURCE_PCLKB_DIV_32 = 0, ///< PCLKB / 32 is the source of the CEC Clock + CEC_CLOCK_SOURCE_PCLKB_DIV_64 = 1, ///< PCLKB / 64 is the source of the CEC Clock + CEC_CLOCK_SOURCE_PCLKB_DIV_128 = 2, ///< PCLKB / 128 is the source of the CEC Clock + CEC_CLOCK_SOURCE_PCLKB_DIV_256 = 3, ///< PCLKB / 256 is the source of the CEC Clock + CEC_CLOCK_SOURCE_PCLKB_DIV_512 = 4, ///< PCLKB / 512 is the source of the CEC Clock + CEC_CLOCK_SOURCE_PCLKB_DIV_1024 = 5, ///< PCLKB / 1024 is the source of the CEC Clock + CEC_CLOCK_SOURCE_CECCLK = 6, ///< CECCLK is the source of the CEC Clock + CEC_CLOCK_SOURCE_CECCLK_DIV_256 = 7, ///< CECCLK / 256 is the source of the CEC Clock +} cec_clock_source_t; + +/** CEC State */ +typedef enum e_cec_state +{ + CEC_STATE_UNINIT = 0x00, ///< Module requires initialization + CEC_STATE_READY = 0x01, ///< Module ready for operation + CEC_STATE_TX_ACTIVE = 0x02, ///< Transmit in progress, either direct or broadcast + CEC_STATE_RX_ACTIVE = 0x04, ///< Receive in progress, either direct or broadcast + CEC_STATE_BUSY = 0x08, ///< CEC Signal Free Time has not yet elapsed +} cec_state_t; + +/** CEC Error Code */ +typedef enum e_cec_error +{ + CEC_ERROR_NONE = 0x000, ///< No errors currently active + CEC_ERROR_OERR = 0x001, ///< Overrun error + CEC_ERROR_UERR = 0x002, ///< Unterrun Error + CEC_ERROR_ACKERR = 0x004, ///< ACK Error + CEC_ERROR_TERR = 0x008, ///< Timing Error + CEC_ERROR_TXERR = 0x010, ///< Transmission Error + CEC_ERROR_AERR = 0x020, ///< Bus arbitration Loss + CEC_ERROR_BLERR = 0x040, ///< Bus lock error + CEC_ERROR_ADDR = 0x100, ///< Address allocation error +} cec_error_t; + +/** CEC event codes */ +typedef enum e_cec_event +{ + CEC_EVENT_RX_DATA, ///< Receive Data byte event + CEC_EVENT_RX_COMPLETE, ///< Receive complete event + CEC_EVENT_TX_COMPLETE, ///< Transmit complete event + CEC_EVENT_READY, ///< CEC Address allocated and module is now ready + CEC_EVENT_ERR, ///< Error has occurred +} cec_event_t; + +typedef struct st_cec_status +{ + cec_addr_t local_address; ///< Local address + cec_state_t state; ///< CEC module state +} cec_status_t; + +/** CEC message */ +typedef union +{ + struct + { + cec_addr_t destination : 8; ///< Destination Address + uint8_t opcode; ///< CEC Opcode + uint8_t data[CEC_DATA_BUFFER_LENGTH]; ///< CEC Message Data + }; + uint8_t raw_data[CEC_DATA_BUFFER_LENGTH + 2 * sizeof(uint8_t)]; ///< Contiguous raw data +} cec_message_t; + +/** CEC callback parameter definition */ +typedef struct st_cec_callback_args +{ + cec_event_t event; ///< Event code + void * p_context; ///< Context provided to user during callback + bool addr_match; ///< Local addresss matches message destination + uint8_t data_byte; ///< Received data byte (INTDA) + cec_status_t status; ///< CEC Module status data + cec_error_t errors; ///< Error code bitfield +} cec_callback_args_t; + +typedef struct st_cec_timing_t +{ + uint16_t bit_width_tx_start_low; ///< Bit Width Transmit Timing Register for Start Bit Low State + uint16_t bit_width_tx_start_high; ///< Bit Width Transmit Timing Register for Start Bit High State + uint16_t bit_width_tx_zero_low; ///< Bit Width Transmit Timing Register for Logical Zero Low State + uint16_t bit_width_tx_one_low; ///< Bit Width Transmit Timing Register for Logical One Low State + uint16_t bit_width_tx_bit_overall; ///< Bit Width Transmit Timing Register for Overall Bit Width + uint16_t bit_width_rx_start_low_min; ///< Bit Width Receive Timing Register for Start Bit Minimum Low State Time + uint16_t bit_width_rx_start_low_max; ///< Bit Width Receive Timing Register for Start Bit Maximum Low State Time + uint16_t bit_width_rx_start_overall_min; ///< Bit Width Receive Timing Register for Start Bit Minimum High State Time + uint16_t bit_width_rx_start_overall_max; ///< Bit Width Receive Timing Register for Start Bit Maximum High State Time + uint16_t bit_width_rx_zero_low_min; ///< Bit Width Receive Timing Register for Logical Zero Minimum Low State Time + uint16_t bit_width_rx_zero_low_max; ///< Bit Width Receive Timing Register for Logical Zero Maximum Low State Time + uint16_t bit_width_rx_one_low_min; ///< Bit Width Receive Timing Register for Logical One Minimum Low State Time + uint16_t bit_width_rx_one_low_max; ///< Bit Width Receive Timing Register for Logical One Maximum Low State Time + uint16_t bit_width_rx_bit_overall_min; ///< Bit Width Receive Timing Register for Overall Minimum Bit Width + uint16_t bit_width_rx_bit_overall_max; ///< Bit Width Receive Timing Register for Overall Maximum Bit Width +} cec_timing_t; + +/** CEC Configuration */ +typedef struct st_cec_cfg +{ + cec_timing_t const * bit_timing_cfg; ///< CEC Bit Timing Configuration + uint16_t rx_data_sample_time; ///< Receive Data Sample Time Setting + uint16_t rx_data_bit_reference_width; ///< Receive Data Bit Reference Width + + void (* p_callback)(cec_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined callback context + + uint8_t ipl; ///< Error/Data/Message interrupt priority level + IRQn_Type error_irq; ///< Error IRQ number + IRQn_Type data_irq; ///< Data IRQ number + IRQn_Type msg_irq; ///< Communication Complete IRQ number + + void * p_extend; ///< Pointer to extended configuration structure +} cec_cfg_t; + +/** CEC control block. Allocate an instance specific control block to pass into the CEC API calls. + */ +typedef void cec_ctrl_t; + +/** Shared Interface definition for CEC */ +typedef struct st_cec_api +{ + /** Open function for CEC device + * + * @param[in,out] p_ctrl Pointer to the CEC control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to CEC configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(cec_ctrl_t * const p_ctrl, cec_cfg_t const * const p_cfg); + + /** Initializes the CEC device. May be called any time after the CEC module has been opened. + * This API blocks until the device initialization procedure is complete. + * + * @param[in] p_ctrl Pointer to CEC instance control block. + * @param[out] local_address Desired Logical address for local device. + */ + fsp_err_t (* mediaInit)(cec_ctrl_t * const p_ctrl, cec_addr_t local_address); + + /** Write function for CEC device + * + * @param[in] p_ctrl Pointer to CEC instance control block + * @param[in] p_message Message data + * @param[in] message_size Total size of entire message + */ + fsp_err_t (* write)(cec_ctrl_t * const p_ctrl, cec_message_t const * const p_message, uint32_t message_size); + + /** Close function for CEC device + * + * @param[in] p_ctrl Pointer to CEC instance control block + * @param[out] p_message Message data + */ + fsp_err_t (* close)(cec_ctrl_t * const p_ctrl); + + /** Get CEC channel info. + * + * @param[in] p_ctrl Pointer to CEC instance control block + * @param[out] p_status Memory address to return channel specific data to. + */ + fsp_err_t (* statusGet)(cec_ctrl_t * const p_ctrl, cec_status_t * const p_status); + + /** Specify callback function, optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref cec_api_t::open call. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure cec be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(cec_ctrl_t * const p_ctrl, void (* p_callback)(cec_callback_args_t *), + void * const p_context, cec_callback_args_t * const p_callback_memory); +} cec_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_cec_instance +{ + cec_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + cec_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + cec_api_t const * p_api; ///< Pointer to the API structure for this instance +} cec_instance_t; + +/*******************************************************************************************************************//** + * @} (end addtogroup CEC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cgc_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cgc_api.h new file mode 100644 index 0000000000..195a7221ab --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_cgc_api.h @@ -0,0 +1,337 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CGC_API_H +#define R_CGC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SYSTEM_INTERFACES + * @defgroup CGC_API CGC Interface + * @brief Interface for clock generation. + * + * @section CGC_API_SUMMARY Summary + * + * The CGC interface provides the ability to configure and use all of the CGC module's capabilities. Among the + * capabilities is the selection of several clock sources to use as the system clock source. Additionally, the + * system clocks can be divided down to provide a wide range of frequencies for various system and peripheral needs. + * + * Clock stability can be checked and clocks may also be stopped to save power when not needed. The API has a function + * to return the frequency of the system and system peripheral clocks at run time. There is also a feature to detect + * when the main oscillator has stopped, with the option of calling a user provided callback function. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_CGC_EVENT_T + +/** Events that can trigger a callback function */ +typedef enum e_cgc_event +{ + CGC_EVENT_OSC_STOP_DETECT_NMI = 0, ///< Main oscillator stop detection has caused the NMI event + CGC_EVENT_OSC_STOP_DETECT_MAIN_OSC = 1, ///< Main oscillator stop detection has caused the interrupt event + CGC_EVENT_OSC_STOP_DETECT_SUBCLOCK = 2, ///< Subclock oscillator stop detection has caused the interrupt event +} cgc_event_t; +#endif + +/** Callback function parameter data */ +typedef struct st_cgc_callback_args +{ + cgc_event_t event; ///< The event can be used to identify what caused the callback + void * p_context; ///< Placeholder for user data +} cgc_callback_args_t; + +#ifndef BSP_OVERRIDE_CGC_CLOCK_T + +/** System clock source identifiers - The source of ICLK, BCLK, FCLK, PCLKS A-D and UCLK prior to the system clock + * divider */ +typedef enum e_cgc_clock +{ + CGC_CLOCK_HOCO = 0, ///< The high speed on chip oscillator + CGC_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator + CGC_CLOCK_LOCO = 2, ///< The low speed on chip oscillator + CGC_CLOCK_MAIN_OSC = 3, ///< The main oscillator + CGC_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator + CGC_CLOCK_PLL = 5, ///< The PLL oscillator + CGC_CLOCK_PLL2 = 6, ///< The PLL2 oscillator +} cgc_clock_t; +#endif + +/** PLL divider values */ +typedef enum e_cgc_pll_div +{ + CGC_PLL_DIV_1 = 0, ///< PLL divider of 1 + CGC_PLL_DIV_2 = 1, ///< PLL divider of 2 + CGC_PLL_DIV_3 = 2, ///< PLL divider of 3 + CGC_PLL_DIV_4 = 3, ///< PLL divider of 4 + CGC_PLL_DIV_6 = 5, ///< PLL divider of 6 +} cgc_pll_div_t; + +/** PLL clock output divisor. */ +typedef enum e_cgc_pll_out_div +{ + CGC_PLL_OUT_DIV_2 = 2, ///< PLL output clock divided by 2 + CGC_PLL_OUT_DIV_3 = 3, ///< PLL output clock divided by 3 + CGC_PLL_OUT_DIV_4 = 4, ///< PLL output clock divided by 4 + CGC_PLL_OUT_DIV_5 = 5, ///< PLL output clock divided by 5 + CGC_PLL_OUT_DIV_6 = 6, ///< PLL output clock divided by 6 + CGC_PLL_OUT_DIV_8 = 8, ///< PLL output clock divided by 8 + CGC_PLL_OUT_DIV_9 = 9, ///< PLL output clock divided by 9 + CGC_PLL_OUT_DIV_1_5 = 10, ///< PLL output clock divided by 1.5 + CGC_PLL_OUT_DIV_16 = 16, ///< PLL output clock divided by 16 +} cgc_pll_out_div_t; + +#ifndef BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T + +/** System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, + * PCLKS A-D. */ +typedef enum e_cgc_sys_clock_div +{ + CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1 + CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2 + CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4 + CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8 + CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 + CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 + CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 + CGC_SYS_CLOCK_DIV_3 = 7, ///< System clock divided by 3 (BCLK only) +} cgc_sys_clock_div_t; +#endif + +#ifndef BSP_OVERRIDE_CGC_PLL_CFG_T + +/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */ +typedef struct st_cgc_pll_cfg +{ + cgc_clock_t source_clock; ///< PLL source clock (main oscillator or HOCO) + cgc_pll_div_t divider; ///< PLL divider + cgc_pll_mul_t multiplier; ///< PLL multiplier + cgc_pll_out_div_t out_div_p; ///< PLL divisor for output clock P + cgc_pll_out_div_t out_div_q; ///< PLL divisor for output clock Q + cgc_pll_out_div_t out_div_r; ///< PLL divisor for output clock R +} cgc_pll_cfg_t; +#endif + +#ifndef BSP_OVERRIDE_CGC_PIN_OUTPUT_CONTROL_T + +/** Pin output control enable/disable (SDCLK, BCLK). */ +typedef enum e_cgc_pin_output_control +{ + CGC_PIN_OUTPUT_CONTROL_ENABLE = 0, ///< Enable pin output + CGC_PIN_OUTPUT_CONTROL_DISABLE = 1 ///< Disable pin output +} cgc_pin_output_control_t; + +#endif + +#ifndef BSP_OVERRIDE_CGC_DIVIDER_CFG_T + +/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::systemClockSet and @ref cgc_api_t::systemClockGet + * functions. */ +typedef struct st_cgc_divider_cfg +{ + union + { + uint32_t sckdivcr_w; ///< System clock Division control register + + struct + { + cgc_sys_clock_div_t pclkd_div : 4; ///< Divider value for PCLKD + cgc_sys_clock_div_t pclkc_div : 4; ///< Divider value for PCLKC + cgc_sys_clock_div_t pclkb_div : 4; ///< Divider value for PCLKB + cgc_sys_clock_div_t pclka_div : 4; ///< Divider value for PCLKA + cgc_sys_clock_div_t bclk_div : 4; ///< Divider value for BCLK + cgc_sys_clock_div_t pclke_div : 4; ///< Divider value for PCLKE + cgc_sys_clock_div_t iclk_div : 4; ///< Divider value for ICLK + cgc_sys_clock_div_t fclk_div : 4; ///< Divider value for FCLK + } sckdivcr_b; + }; + + union + { + uint8_t sckdivcr2; ///< System clock Division control register 2 + + struct + { + cgc_sys_clock_div_t cpuclk_div : 4; ///< Divider value for CPUCLK + uint8_t reserved : 4; + } sckdivcr2_b; + }; +} cgc_divider_cfg_t; +#endif + +#ifndef BSP_OVERRIDE_CGC_USB_CLOCK_DIV_T + +/** USB clock divider values */ +typedef enum e_cgc_usb_clock_div +{ + CGC_USB_CLOCK_DIV_2 = 1, ///< Divide USB source clock by 2 + CGC_USB_CLOCK_DIV_3 = 2, ///< Divide USB source clock by 3 + CGC_USB_CLOCK_DIV_4 = 3, ///< Divide USB source clock by 4 + CGC_USB_CLOCK_DIV_5 = 4, ///< Divide USB source clock by 5 +} cgc_usb_clock_div_t; +#endif + +#ifndef BSP_OVERRIDE_CGC_CLOCK_CHANGE_T + +/** Clock options */ +typedef enum e_cgc_clock_change +{ + CGC_CLOCK_CHANGE_START = 0, ///< Start the clock + CGC_CLOCK_CHANGE_STOP = 1, ///< Stop the clock + CGC_CLOCK_CHANGE_NONE = 2, ///< No change to the clock +} cgc_clock_change_t; +#endif + +/** CGC control block. Allocate an instance specific control block to pass into the CGC API calls. + */ +typedef void cgc_ctrl_t; + +/** Configuration options. */ +typedef struct st_cgc_cfg +{ + void (* p_callback)(cgc_callback_args_t * p_args); + void * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. +} cgc_cfg_t; + +#ifndef BSP_OVERRIDE_CGC_CLOCKS_CFG_T + +/** Clock configuration */ +typedef struct st_cgc_clocks_cfg +{ + cgc_clock_t system_clock; ///< System clock source enumeration + cgc_pll_cfg_t pll_cfg; ///< PLL configuration structure + cgc_pll_cfg_t pll2_cfg; ///< PLL2 configuration structure + cgc_divider_cfg_t divider_cfg; ///< Clock dividers structure + cgc_clock_change_t loco_state; ///< State of LOCO + cgc_clock_change_t moco_state; ///< State of MOCO + cgc_clock_change_t hoco_state; ///< State of HOCO + cgc_clock_change_t mainosc_state; ///< State of Main oscillator + cgc_clock_change_t pll_state; ///< State of PLL + cgc_clock_change_t pll2_state; ///< State of PLL2 + cgc_clock_change_t subosc_state; ///< State of Sub oscillator +} cgc_clocks_cfg_t; +#endif + +/** CGC functions implemented at the HAL layer follow this API. */ +typedef struct +{ + /** Initial configuration + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration + */ + fsp_err_t (* open)(cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg); + + /** Configure all system clocks. + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_clock_cfg Pointer to desired configuration of system clocks + */ + fsp_err_t (* clocksCfg)(cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * const p_clock_cfg); + + /** Start a clock. + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Clock source to start + * @param[in] p_pll_cfg Pointer to PLL configuration, can be NULL if clock_source is not CGC_CLOCK_PLL or + * CGC_CLOCK_PLL2 + */ + fsp_err_t (* clockStart)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, + cgc_pll_cfg_t const * const p_pll_cfg); + + /** Stop a clock. + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source The clock source to stop + */ + fsp_err_t (* clockStop)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); + + /** Check the stability of the selected clock. + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Which clock source to check for stability + */ + fsp_err_t (* clockCheck)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); + + /** Set the system clock. + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Clock source to set as system clock + * @param[in] p_divider_cfg Pointer to the clock divider configuration + */ + fsp_err_t (* systemClockSet)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, + cgc_divider_cfg_t const * const p_divider_cfg); + + /** Get the system clock information. + * @param[in] p_ctrl Pointer to instance control block + * @param[out] p_clock_source Returns the current system clock + * @param[out] p_divider_cfg Returns the current system clock dividers + */ + fsp_err_t (* systemClockGet)(cgc_ctrl_t * const p_ctrl, cgc_clock_t * const p_clock_source, + cgc_divider_cfg_t * const p_divider_cfg); + + /** Enable and optionally register a callback for Main Oscillator stop detection. + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* oscStopDetectEnable)(cgc_ctrl_t * const p_ctrl); + + /** Disable Main Oscillator stop detection. + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* oscStopDetectDisable)(cgc_ctrl_t * const p_ctrl); + + /** Clear the oscillator stop detection flag. + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* oscStopStatusClear)(cgc_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the CGC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(cgc_ctrl_t * const p_ctrl, void (* p_callback)(cgc_callback_args_t *), + void * const p_context, cgc_callback_args_t * const p_callback_memory); + + /** Close the CGC driver. + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* close)(cgc_ctrl_t * const p_ctrl); +} cgc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_cgc_instance +{ + cgc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + cgc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + cgc_api_t const * p_api; ///< Pointer to the API structure for this instance +} cgc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup CGC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_CGC_API_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_comparator_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_comparator_api.h new file mode 100644 index 0000000000..5e0bf333b7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_comparator_api.h @@ -0,0 +1,186 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_COMPARATOR_API_H +#define R_COMPARATOR_API_H + +/*******************************************************************************************************************//** + * @defgroup COMPARATOR_API Comparator Interface + * @ingroup RENESAS_ANALOG_INTERFACES + * @brief Interface for comparators. + * + * @section COMPARATOR_API_SUMMARY Summary + * The comparator interface provides standard comparator functionality, including generating an event when the + * comparator result changes. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/** Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/***************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/** Comparator control block. Allocate an instance specific control block to pass into the comparator API calls. + */ +typedef void comparator_ctrl_t; + +/** Select whether to invert the polarity of the comparator output. */ +typedef enum e_comparator_mode +{ + COMPARATOR_MODE_NORMAL = 0, ///< Normal mode + COMPARATOR_MODE_WINDOW = 1, ///< Window mode, not supported by all implementations +} comparator_mode_t; + +#ifndef BSP_OVERRIDE_COMARATOR_TRIGGER_T +/** Trigger type: rising edge, falling edge, both edges, low level. */ +typedef enum e_comparator_trigger +{ + COMPARATOR_TRIGGER_RISING = 1, ///< Rising edge trigger + COMPARATOR_TRIGGER_FALLING = 2, ///< Falling edge trigger + COMPARATOR_TRIGGER_BOTH_EDGE = 3, ///< Both edges trigger +} comparator_trigger_t; +#endif + +/** Select whether to invert the polarity of the comparator output. */ +typedef enum e_comparator_polarity_invert +{ + COMPARATOR_POLARITY_INVERT_OFF = 0, ///< Do not invert polarity + COMPARATOR_POLARITY_INVERT_ON = 1, ///< Invert polarity +} comparator_polarity_invert_t; + +/** Select whether to include the comparator output on the output pin. */ +typedef enum e_comparator_pin_output +{ + COMPARATOR_PIN_OUTPUT_OFF = 0, ///< Do not include comparator output on output pin + COMPARATOR_PIN_OUTPUT_ON = 1, ///< Include comparator output on output pin +} comparator_pin_output_t; + +/** Comparator digital filtering sample clock divisor settings. */ +typedef enum e_comparator_filter +{ + COMPARATOR_FILTER_OFF = 0, ///< Disable debounce filter + COMPARATOR_FILTER_1 = 4, ///< Filter using PCLK divided by 1, not supported by all implementations + COMPARATOR_FILTER_8 = 1, ///< Filter using PCLK divided by 8 + COMPARATOR_FILTER_16 = 2, ///< Filter using PCLK divided by 16, not supported by all implementations + COMPARATOR_FILTER_32 = 3, ///< Filter using PCLK divided by 32 +} comparator_filter_t; + +/** Current comparator state. */ +typedef enum e_comparator_state +{ + COMPARATOR_STATE_OUTPUT_LOW = 0, ///< VCMP < VREF if polarity is not inverted, VCMP > VREF if inverted + COMPARATOR_STATE_OUTPUT_HIGH = 1, ///< VCMP > VREF if polarity is not inverted, VCMP < VREF if inverted + COMPARATOR_STATE_OUTPUT_DISABLED = 2, ///< @ref comparator_api_t::outputEnable() has not been called +} comparator_state_t; + +/** Comparator information. */ +typedef struct st_comparator_info +{ + uint32_t min_stabilization_wait_us; ///< Minimum stabilization wait time in microseconds +} comparator_info_t; + +/** Comparator status. */ +typedef struct st_comparator_status +{ + comparator_state_t state; ///< Current comparator state +} comparator_status_t; + +/** Callback function parameter data */ +typedef struct st_comparator_callback_args +{ + /** Placeholder for user data. Set in @ref comparator_api_t::open function in @ref comparator_cfg_t. */ + void * p_context; + uint32_t channel; ///< The physical hardware channel that caused the interrupt. +} comparator_callback_args_t; + +/** User configuration structure, used in open function */ +typedef struct st_comparator_cfg +{ + uint8_t channel; ///< Hardware channel used. + comparator_mode_t mode; ///< Normal or window mode + comparator_trigger_t trigger; ///< Trigger setting. + comparator_filter_t filter; ///< Digital filter clock divisor setting. + comparator_polarity_invert_t invert; ///< Whether to invert output + comparator_pin_output_t pin_output; ///< Whether to include output on output pin + uint8_t vref_select; ///< Internal Vref Select + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< NVIC interrupt number + + /** Callback called when comparator event occurs. */ + void (* p_callback)(comparator_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref comparator_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Comparator hardware dependent configuration. +} comparator_cfg_t; + +/** Comparator functions implemented at the HAL layer will follow this API. */ +typedef struct st_comparator_api +{ + /** Initialize the comparator. + * + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration + */ + fsp_err_t (* open)(comparator_ctrl_t * const p_ctrl, comparator_cfg_t const * const p_cfg); + + /** Start the comparator. + * + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* outputEnable)(comparator_ctrl_t * const p_ctrl); + + /** Provide information such as the recommended minimum stabilization wait time. + * + * @param[in] p_ctrl Pointer to instance control block + * @param[out] p_info Comparator information stored here + */ + fsp_err_t (* infoGet)(comparator_ctrl_t * const p_ctrl, comparator_info_t * const p_info); + + /** Provide current comparator status. + * + * @param[in] p_ctrl Pointer to instance control block + * @param[out] p_status Status stored here + */ + fsp_err_t (* statusGet)(comparator_ctrl_t * const p_ctrl, comparator_status_t * const p_status); + + /** Stop the comparator. + * + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* close)(comparator_ctrl_t * const p_ctrl); +} comparator_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_comparator_instance +{ + comparator_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + comparator_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + comparator_api_t const * p_api; ///< Pointer to the API structure for this instance +} comparator_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*******************************************************************************************************************//** + * @} (end defgroup COMPARATOR_API) + **********************************************************************************************************************/ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_crc_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_crc_api.h new file mode 100644 index 0000000000..c35229cf6c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_crc_api.h @@ -0,0 +1,155 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CRC_API_H +#define R_CRC_API_H + +/*******************************************************************************************************************//** + * @defgroup CRC_API CRC Interface + * @ingroup RENESAS_MONITORING_INTERFACES + * + * @brief Interface for cyclic redundancy checking. + * + * @section CRC_API_SUMMARY Summary + * The CRC (Cyclic Redundancy Check) calculator generates CRC codes using five different polynomials including 8 bit, + * 16 bit, and 32 bit variations. Calculation can be performed by sending data to the block using the CPU or by snooping + * on read or write activity on one of SCI channels. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CRC Generating Polynomial Switching (GPS). */ +typedef enum e_crc_polynomial +{ + CRC_POLYNOMIAL_CRC_8 = 1, ///< 8-bit CRC-8 (X^8 + X^2 + X + 1) + CRC_POLYNOMIAL_CRC_16, ///< 16-bit CRC-16 (X^16 + X^15 + X^2 + 1) + CRC_POLYNOMIAL_CRC_CCITT, ///< 16-bit CRC-CCITT (X^16 + X^12 + X^5 + 1) + + /** 32-bit CRC-32 (X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 + X^8 + X^7 + X^5 + X^4 + X^2 + X + 1) */ + CRC_POLYNOMIAL_CRC_32, + + /** 32-bit CRC-32C (X^32 + X^28 + X^27 + X^26 + X^25 + X^23 + X^22 + X^20 + X^19 + X^18 + X^14 + X^13 + X^11 + X^10 + X^9 + X^8 + + * X^6 + 1) */ + CRC_POLYNOMIAL_CRC_32C, +} _crc_polynomial_t; + +/** CRC Calculation Switching (LMS) */ +typedef enum e_crc_bit_order +{ + CRC_BIT_ORDER_LMS_LSB = 0, ///< Generates CRC for LSB first communication + CRC_BIT_ORDER_LMS_MSB, ///< Generates CRC for MSB first communication +} crc_bit_order_t; + +/** Snoop-On-Write/Read Switch (CRCSWR) */ +typedef enum e_crc_snoop_direction +{ + CRC_SNOOP_DIRECTION_RECEIVE = 0, ///< Snoop-on-read + CRC_SNOOP_DIRECTION_TRANSMIT, ///< Snoop-on-write +} crc_snoop_direction_t; + +/** Structure for CRC inputs */ +typedef struct st_crc_input_t +{ + uint32_t num_bytes; ///< Length of input buffer. It must be 4-byte aligned when a 32-bit CRC polynomial function is used. + uint32_t crc_seed; ///< CRC seed value + const void * p_input_buffer; ///< Pointer to input buffer +} crc_input_t; + +/** CRC control block. Allocate an instance specific control block to pass into the CRC API calls. + */ +typedef void crc_ctrl_t; + +/** User configuration structure, used in open function */ +typedef struct st_crc_cfg +{ + uint8_t channel; ///< Channel number + _crc_polynomial_t polynomial; ///< CRC Generating Polynomial Switching (GPS) + crc_bit_order_t bit_order; ///< CRC Calculation Switching (LMS) + uint32_t snoop_address; ///< Register Snoop Address (CRCSA) + void const * p_extend; ///< CRC Hardware Dependent Configuration +} crc_cfg_t; + +/** CRC driver structure. General CRC functions implemented at the HAL layer will follow this API. */ +typedef struct st_crc_api +{ + /** Open the CRC driver module. + * + * @param[in] p_ctrl Pointer to CRC device handle. + * @param[in] p_cfg Pointer to a configuration structure. + **/ + fsp_err_t (* open)(crc_ctrl_t * const p_ctrl, crc_cfg_t const * const p_cfg); + + /** Close the CRC module driver + * + * @param[in] p_ctrl Pointer to CRC device handle + * @retval FSP_SUCCESS Configuration was successful. + **/ + fsp_err_t (* close)(crc_ctrl_t * const p_ctrl); + + /** Return the current calculated value. + * + * @param[in] p_ctrl Pointer to CRC device handle. + * @param[out] crc_result The calculated value from the last CRC calculation. + **/ + fsp_err_t (* crcResultGet)(crc_ctrl_t * const p_ctrl, uint32_t * crc_result); + + /** Configure and Enable snooping. + * + * @param[in] p_ctrl Pointer to CRC device handle. + * @param[in] crc_seed CRC seed. + **/ + fsp_err_t (* snoopEnable)(crc_ctrl_t * const p_ctrl, uint32_t crc_seed); + + /** Disable snooping. + * + * @param[in] p_ctrl Pointer to CRC device handle. + **/ + fsp_err_t (* snoopDisable)(crc_ctrl_t * const p_ctrl); + + /** Perform a CRC calculation on a block of data. + * + * @param[in] p_ctrl Pointer to CRC device handle. + * @param[in] p_crc_input A pointer to structure for CRC inputs + * @param[out] crc_result The calculated value of the CRC calculation. + **/ + fsp_err_t (* calculate)(crc_ctrl_t * const p_ctrl, crc_input_t * const p_crc_input, uint32_t * p_crc_result); +} crc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_crc_instance +{ + crc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + crc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + crc_api_t const * p_api; ///< Pointer to the API structure for this instance +} crc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup CRC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ctsu_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ctsu_api.h new file mode 100644 index 0000000000..b9251c3dfa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ctsu_api.h @@ -0,0 +1,319 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CAPTOUCH_INTERFACES + * @defgroup CTSU_API CTSU Interface + * @brief Interface for Capacitive Touch Sensing Unit (CTSU) functions. + * + * @section CTSU_API_Summary Summary + * The CTSU interface provides CTSU functionality. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_CTSU_API_H +#define R_CTSU_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" +#include "r_adc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define CTSU_COUNT_MAX (0xFFFF) + +#define CTSU_TARGET_VALUE_CONFIG_SUPPORT (1) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CTSU Events for callback function */ +typedef enum e_ctsu_event +{ + CTSU_EVENT_SCAN_COMPLETE = 0x00, ///< Normal end + CTSU_EVENT_OVERFLOW = 0x01, ///< Sensor counter overflow (CTSUST.CTSUSOVF set) + CTSU_EVENT_ICOMP = 0x02, ///< Abnormal TSCAP voltage (CTSUERRS.CTSUICOMP set) + CTSU_EVENT_ICOMP1 = 0x04 ///< Abnormal sensor current (CTSUSR.ICOMP1 set) +} ctsu_event_t; + +/** CTSU Scan Start Trigger Select */ +typedef enum e_ctsu_cap +{ + CTSU_CAP_SOFTWARE, ///< Scan start by software trigger + CTSU_CAP_EXTERNAL ///< Scan start by external trigger +} ctsu_cap_t; + +/** CTSU Transmission Power Supply Select */ +typedef enum e_ctsu_txvsel +{ + CTSU_TXVSEL_VCC, ///< VCC selected + CTSU_TXVSEL_INTERNAL_POWER ///< Internal logic power supply selected +} ctsu_txvsel_t; + +/** CTSU Transmission Power Supply Select 2 (CTSU2 Only) */ +typedef enum e_ctsu_txvsel2 +{ + CTSU_TXVSEL_MODE, ///< Follow TXVSEL setting + CTSU_TXVSEL_VCC_PRIVATE, ///< VCC private selected +} ctsu_txvsel2_t; + +/** CTSU Power Supply Capacity Adjustment (CTSU Only) */ +typedef enum e_ctsu_atune1 +{ + CTSU_ATUNE1_NORMAL, ///< Normal output (40uA) + CTSU_ATUNE1_HIGH ///< High-current output (80uA) +} ctsu_atune1_t; + +/** CTSU Power Supply Capacity Adjustment (CTSU2 Only) */ +typedef enum e_ctsu_atune12 +{ + CTSU_ATUNE12_80UA, ///< High-current output (80uA) + CTSU_ATUNE12_40UA, ///< Normal output (40uA) + CTSU_ATUNE12_20UA, ///< Low-current output (20uA) + CTSU_ATUNE12_160UA ///< Very high-current output (160uA) +} ctsu_atune12_t; + +/** CTSU Measurement Mode Select */ +typedef enum e_ctsu_mode +{ + CTSU_MODE_SELF_MULTI_SCAN = 1, ///< Self-capacitance multi scan mode + CTSU_MODE_MUTUAL_FULL_SCAN = 3, ///< Mutual capacitance full scan mode + CTSU_MODE_MUTUAL_CFC_SCAN = 7, ///< Mutual capacitance cfc scan mode (CTSU2 Only) + CTSU_MODE_CURRENT_SCAN = 9, ///< Current scan mode (CTSU2 Only) + CTSU_MODE_CORRECTION_SCAN = 17, ///< Correction scan mode (CTSU2 Only) + CTSU_MODE_DIAGNOSIS_SCAN = 33 ///< Diagnosis scan mode +} ctsu_md_t; + +/** CTSU Non-Measured Channel Output Select (CTSU2 Only) */ +typedef enum e_ctsu_posel +{ + CTSU_POSEL_LOW_GPIO, ///< Output low through GPIO + CTSU_POSEL_HI_Z, ///< Hi-Z + CTSU_POSEL_LOW, ///< Setting prohibited + CTSU_POSEL_SAME_PULSE ///< Same phase pulse output as transmission channel through the power setting by the TXVSEL[1:0] bits +} ctsu_posel_t; + +/** CTSU Spectrum Diffusion Frequency Division Setting (CTSU Only) */ +typedef enum e_ctsu_ssdiv +{ + CTSU_SSDIV_4000, ///< 4.00 <= Base clock frequency (MHz) + CTSU_SSDIV_2000, ///< 2.00 <= Base clock frequency (MHz) < 4.00 + CTSU_SSDIV_1330, ///< 1.33 <= Base clock frequency (MHz) < 2.00 + CTSU_SSDIV_1000, ///< 1.00 <= Base clock frequency (MHz) < 1.33 + CTSU_SSDIV_0800, ///< 0.80 <= Base clock frequency (MHz) < 1.00 + CTSU_SSDIV_0670, ///< 0.67 <= Base clock frequency (MHz) < 0.80 + CTSU_SSDIV_0570, ///< 0.57 <= Base clock frequency (MHz) < 0.67 + CTSU_SSDIV_0500, ///< 0.50 <= Base clock frequency (MHz) < 0.57 + CTSU_SSDIV_0440, ///< 0.44 <= Base clock frequency (MHz) < 0.50 + CTSU_SSDIV_0400, ///< 0.40 <= Base clock frequency (MHz) < 0.44 + CTSU_SSDIV_0360, ///< 0.36 <= Base clock frequency (MHz) < 0.40 + CTSU_SSDIV_0330, ///< 0.33 <= Base clock frequency (MHz) < 0.36 + CTSU_SSDIV_0310, ///< 0.31 <= Base clock frequency (MHz) < 0.33 + CTSU_SSDIV_0290, ///< 0.29 <= Base clock frequency (MHz) < 0.31 + CTSU_SSDIV_0270, ///< 0.27 <= Base clock frequency (MHz) < 0.29 + CTSU_SSDIV_0000 ///< 0.00 <= Base clock frequency (MHz) < 0.27 +} ctsu_ssdiv_t; + +/** CTSU select data type for slect data get */ +typedef enum e_ctsu_specific_data_type +{ + CTSU_SPECIFIC_RAW_DATA, + CTSU_SPECIFIC_CCO_CORRECTION_DATA, + CTSU_SPECIFIC_CORRECTION_DATA, + CTSU_SPECIFIC_SELECTED_FREQ, +} ctsu_specific_data_type_t; + +/** Callback function parameter data */ +typedef struct st_ctsu_callback_args +{ + ctsu_event_t event; ///< The event can be used to identify what caused the callback. + void * p_context; ///< Placeholder for user data. Set in ctsu_api_t::open function in ::ctsu_cfg_t. +} ctsu_callback_args_t; + +/** CTSU Control block. Allocate an instance specific control block to pass into the API calls. + */ +typedef void ctsu_ctrl_t; + +/** CTSU Configuration parameters. */ +/** Element Configuration */ +typedef struct st_ctsu_element +{ + ctsu_ssdiv_t ssdiv; ///< CTSU Spectrum Diffusion Frequency Division Setting (CTSU Only) + uint16_t so; ///< CTSU Sensor Offset Adjustment + uint8_t snum; ///< CTSU Measurement Count Setting + uint8_t sdpa; ///< CTSU Base Clock Setting +} ctsu_element_cfg_t; + +/** Configuration of each automatic judgement button */ +typedef struct st_ctsu_auto_button_cfg +{ + uint8_t elem_index; ///< Element number used by this button for automatic judgement. + uint16_t threshold; ///< Touch/non-touch judgement threshold for automatic judgement. + uint16_t hysteresis; ///< Threshold hysteresis for chattering prevention for automatic judgement. +} ctsu_auto_button_cfg_t; + +/** User configuration structure, used in open function */ +typedef struct st_ctsu_cfg +{ + ctsu_cap_t cap; ///< CTSU Scan Start Trigger Select + ctsu_txvsel_t txvsel; ///< CTSU Transmission Power Supply Select + ctsu_txvsel2_t txvsel2; ///< CTSU Transmission Power Supply Select 2 (CTSU2 Only) + ctsu_atune1_t atune1; ///< CTSU Power Supply Capacity Adjustment (CTSU Only) + ctsu_atune12_t atune12; ///< CTSU Power Supply Capacity Adjustment (CTSU2 Only) + ctsu_md_t md; ///< CTSU Measurement Mode Select + ctsu_posel_t posel; ///< CTSU Non-Measured Channel Output Select (CTSU2 Only) + uint8_t tsod; ///< TS all terminal output control for multi electrode scan + uint8_t mec_ts; ///< TS number used when using the MEC function + uint8_t mec_shield_ts; ///< TS number of active shield used when using MEC function + uint8_t tlot; ///< Number of consecutive judgements exceeding the threshold L for automatic judgement + uint8_t thot; ///< Number of consecutive judgements exceeding the threshold H for automatic judgement + uint8_t jc; ///< Judgement condition for automatic judgement + uint8_t ajmmat; ///< Measured value moving average number of times for automatic judgement + uint8_t ajbmat; ///< Average number of baselines for automatic judgement + uint8_t mtucfen; ///< Mutual capacity operation for automatic judgement + uint8_t ajfen; ///< Automatic judgement function enabled for automatic judgement + uint8_t autojudge_monitor_num; ///< Method number for QE monitor for automatic judgement + uint8_t majirimd; ///< JMM or VMM for automatic judgement + uint8_t ctsuchac0; ///< TS00-TS07 enable mask + uint8_t ctsuchac1; ///< TS08-TS15 enable mask + uint8_t ctsuchac2; ///< TS16-TS23 enable mask + uint8_t ctsuchac3; ///< TS24-TS31 enable mask + uint8_t ctsuchac4; ///< TS32-TS39 enable mask + uint8_t ctsuchtrc0; ///< TS00-TS07 mutual-tx mask + uint8_t ctsuchtrc1; ///< TS08-TS15 mutual-tx mask + uint8_t ctsuchtrc2; ///< TS16-TS23 mutual-tx mask + uint8_t ctsuchtrc3; ///< TS24-TS31 mutual-tx mask + uint8_t ctsuchtrc4; ///< TS32-TS39 mutual-tx mask + ctsu_element_cfg_t const * p_elements; ///< Pointer to elements configuration array + uint8_t num_rx; ///< Number of receive terminals + uint8_t num_tx; ///< Number of transmit terminals + uint16_t num_moving_average; ///< Number of moving average for measurement data + bool tunning_enable; ///< Initial offset tuning flag + void (* p_callback)(ctsu_callback_args_t * p_args); ///< Callback provided when CTSUFN ISR occurs. + transfer_instance_t const * p_transfer_tx; ///< DTC instance for transmit at CTSUWR. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< DTC instance for receive at CTSURD. Set to NULL if unused. + adc_instance_t const * p_adc_instance; ///< ADC instance for temperature correction. + IRQn_Type write_irq; ///< CTSU_CTSUWR interrupt vector + IRQn_Type read_irq; ///< CTSU_CTSURD interrupt vector + IRQn_Type end_irq; ///< CTSU_CTSUFN interrupt vector + void * p_context; ///< User defined context passed into callback function. + void const * p_extend; ///< Pointer to extended configuration by instance of interface. + uint16_t tuning_self_target_value; ///< Target self value for initial offset tuning + uint16_t tuning_mutual_target_value; ///< Target mutual value for initial offset tuning + ctsu_auto_button_cfg_t const * p_ctsu_auto_buttons; ///< Pointer to array of automatic judgement button configuration. + uint8_t majority_mode; ///< Software majority mode selection +} ctsu_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_ctsu_api +{ + /** Open driver. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cfg); + + /** Scan start. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* scanStart)(ctsu_ctrl_t * const p_ctrl); + + /** Data get. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_data Pointer to get data array. + */ + fsp_err_t (* dataGet)(ctsu_ctrl_t * const p_ctrl, uint16_t * p_data); + + /** ScanStop. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* scanStop)(ctsu_ctrl_t * const p_ctrl); + + /** Diagnosis. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* diagnosis)(ctsu_ctrl_t * const p_ctrl); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the CTSU control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(ctsu_ctrl_t * const p_ctrl, void (* p_callback)(ctsu_callback_args_t *), + void * const p_context, ctsu_callback_args_t * const p_callback_memory); + + /** Close driver. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(ctsu_ctrl_t * const p_ctrl); + + /** Specific Data get. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_specific_data Pointer to get specific data array. + * @param[in] specific_data_type Specific data type + */ + fsp_err_t (* specificDataGet)(ctsu_ctrl_t * const p_ctrl, uint16_t * p_specific_data, + ctsu_specific_data_type_t specific_data_type); + + /** Data Insert. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_insert_data Pointer to insert data. + */ + fsp_err_t (* dataInsert)(ctsu_ctrl_t * const p_ctrl, uint16_t * p_insert_data); + + /** Initialize automatic judgement and get button status. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_button_status Pointer to get button status array. + */ + fsp_err_t (* autoJudgementDataGet)(ctsu_ctrl_t * const p_ctrl, uint64_t * p_button_status); + + /** Adjust the offset value to tune the sensor. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* offsetTuning)(ctsu_ctrl_t * const p_ctrl); +} ctsu_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ctsu_instance +{ + ctsu_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ctsu_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ctsu_api_t const * p_api; ///< Pointer to the API structure for this instance +} ctsu_instance_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_CTSU_API_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup CTSU_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_dac_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_dac_api.h new file mode 100644 index 0000000000..fdd398f549 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_dac_api.h @@ -0,0 +1,117 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_ANALOG_INTERFACES + * @defgroup DAC_API DAC Interface + * @brief Interface for D/A converters. + * + * @section DAC_API_SUMMARY Summary + * The DAC interface provides standard Digital/Analog Converter functionality. A DAC application writes digital + * sample data to the device and generates analog output on the DAC output pin. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_DAC_API_H +#define R_DAC_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** DAC Open API data format settings. */ +typedef enum e_dac_data_format +{ + DAC_DATA_FORMAT_FLUSH_RIGHT = 0, ///< LSB of data is flush to the right leaving the top 4 bits unused. + DAC_DATA_FORMAT_FLUSH_LEFT = 1 ///< MSB of data is flush to the left leaving the bottom 4 bits unused. +} dac_data_format_t; + +/** DAC information structure to store various information for a DAC */ +typedef struct dac_info +{ + uint8_t bit_width; ///< Resolution of the DAC. +} dac_info_t; + +/** DAC Open API configuration parameter */ +typedef struct st_dac_cfg +{ + uint8_t channel; ///< ID associated with this DAC channel + bool ad_da_synchronized; ///< AD/DA synchronization + void const * p_extend; +} dac_cfg_t; + +/** DAC control block. Allocate an instance specific control block to pass into the DAC API calls. + */ +typedef void dac_ctrl_t; + +/** DAC driver structure. General DAC functions implemented at the HAL layer follow this API. */ +typedef struct st_dac_api +{ + /** Initial configuration. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(dac_ctrl_t * const p_ctrl, dac_cfg_t const * const p_cfg); + + /** Close the D/A Converter. + * + * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. + */ + fsp_err_t (* close)(dac_ctrl_t * const p_ctrl); + + /** Write sample value to the D/A Converter. + * + * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. + * @param[in] value Sample value to be written to the D/A Converter. + */ + fsp_err_t (* write)(dac_ctrl_t * const p_ctrl, uint16_t value); + + /** Start the D/A Converter if it has not been started yet. + * + * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. + */ + fsp_err_t (* start)(dac_ctrl_t * const p_ctrl); + + /** Stop the D/A Converter if the converter is running. + * + * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. + */ + fsp_err_t (* stop)(dac_ctrl_t * const p_ctrl); +} dac_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_dac_instance +{ + dac_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + dac_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + dac_api_t const * p_api; ///< Pointer to the API structure for this instance +} dac_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup DAC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_display_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_display_api.h new file mode 100644 index 0000000000..07e873b789 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_display_api.h @@ -0,0 +1,453 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_GRAPHICS_INTERFACES + * @defgroup DISPLAY_API Display Interface + * @brief Interface for LCD panel displays. + * + * @section DISPLAY_API_SUMMARY Summary + * The display interface provides standard display functionality: + * - Signal timing configuration for LCD panels with RGB interface. + * - Dot clock source selection (internal or external) and frequency divider. + * - Blending of multiple graphics layers on the background screen. + * - Color correction (brightness/configuration/gamma correction). + * - Interrupts and callback function. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_DISPLAY_API_H +#define R_DISPLAY_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define DISPLAY_GAMMA_CURVE_ELEMENT_NUM (16) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Display frame number */ +typedef enum e_display_frame_layer +{ + DISPLAY_FRAME_LAYER_1 = 0, ///< Frame layer 1 + DISPLAY_FRAME_LAYER_2 = 1 ///< Frame layer 2 +} display_frame_layer_t; + +/** Display interface operation state */ +typedef enum e_display_state +{ + DISPLAY_STATE_CLOSED = 0, ///< Display closed + DISPLAY_STATE_OPENED = 1, ///< Display opened + DISPLAY_STATE_DISPLAYING = 2 ///< Displaying +} display_state_t; + +/** Display event codes */ +typedef enum e_display_event +{ + DISPLAY_EVENT_GR1_UNDERFLOW = 1, ///< Graphics frame1 underflow occurs + DISPLAY_EVENT_GR2_UNDERFLOW = 2, ///< Graphics frame2 underflow occurs + DISPLAY_EVENT_LINE_DETECTION = 3, ///< Designated line is processed + DISPLAY_EVENT_FRAME_END = 4, ///< Frame end is processed +} display_event_t; + +#ifndef BSP_OVERRIDE_DISPLAY_IN_FORMAT_T + +/** Input format setting */ +typedef enum e_display_in_format +{ + DISPLAY_IN_FORMAT_32BITS_ARGB8888 = 0, ///< ARGB8888, 32 bits + DISPLAY_IN_FORMAT_32BITS_RGB888 = 1, ///< RGB888, 32 bits + DISPLAY_IN_FORMAT_16BITS_RGB565 = 2, ///< RGB565, 16 bits + DISPLAY_IN_FORMAT_16BITS_ARGB1555 = 3, ///< ARGB1555, 16 bits + DISPLAY_IN_FORMAT_16BITS_ARGB4444 = 4, ///< ARGB4444, 16 bits + DISPLAY_IN_FORMAT_CLUT8 = 5, ///< CLUT8 + DISPLAY_IN_FORMAT_CLUT4 = 6, ///< CLUT4 + DISPLAY_IN_FORMAT_CLUT1 = 7, ///< CLUT1 +} display_in_format_t; + +#endif + +/** Output format setting */ +typedef enum e_display_out_format +{ + DISPLAY_OUT_FORMAT_24BITS_RGB888 = 0, ///< RGB888, 24 bits + DISPLAY_OUT_FORMAT_18BITS_RGB666 = 1, ///< RGB666, 18 bits + DISPLAY_OUT_FORMAT_16BITS_RGB565 = 2, ///< RGB565, 16 bits + DISPLAY_OUT_FORMAT_8BITS_SERIAL = 3, ///< SERIAL, 8 bits +} display_out_format_t; + +/** Data endian select */ +typedef enum e_display_endian +{ + DISPLAY_ENDIAN_LITTLE, ///< Little-endian + DISPLAY_ENDIAN_BIG, ///< Big-endian +} display_endian_t; + +/** RGB color order select */ +typedef enum e_display_color_order +{ + DISPLAY_COLOR_ORDER_RGB, ///< Color order RGB + DISPLAY_COLOR_ORDER_BGR ///< Color order BGR +} display_color_order_t; + +/** Polarity of a signal select */ +typedef enum e_display_signal_polarity +{ + DISPLAY_SIGNAL_POLARITY_LOACTIVE, ///< Low active signal + DISPLAY_SIGNAL_POLARITY_HIACTIVE, ///< High active signal +} display_signal_polarity_t; + +/** Signal synchronization edge select */ +typedef enum e_display_sync_edge +{ + DISPLAY_SIGNAL_SYNC_EDGE_RISING, ///< Signal is synchronized to rising edge + DISPLAY_SIGNAL_SYNC_EDGE_FALLING, ///< Signal is synchronized to falling edge +} display_sync_edge_t; + +/** Fading control */ +typedef enum e_display_fade_control +{ + DISPLAY_FADE_CONTROL_NONE, ///< Applying no fading control + DISPLAY_FADE_CONTROL_FADEIN, ///< Applying fade-in control + DISPLAY_FADE_CONTROL_FADEOUT, ///< Applying fade-out control +} display_fade_control_t; + +/** Fading status */ +typedef enum e_display_fade_status +{ + DISPLAY_FADE_STATUS_NOT_UNDERWAY, ///< Fade-in/fade-out is not in progress + DISPLAY_FADE_STATUS_FADING_UNDERWAY, ///< Fade-in or fade-out is in progress + DISPLAY_FADE_STATUS_PENDING ///< Fade-in/fade-out is configured but not yet started +} display_fade_status_t; + +/** Color Keying enable or disable */ +typedef enum e_display_color_keying +{ + DISPLAY_COLOR_KEYING_DISABLE = 0, ///< Color keying disable + DISPLAY_COLOR_KEYING_ENABLE = 1 ///< Color keying enable +} display_color_keying_t; + +#ifndef BSP_OVERRIDE_DISPLAY_DATA_SWAP_T + +/** Data swap settings */ +typedef enum e_display_data_swap +{ + DISPLAY_DATA_SWAP_8BIT = 1, + DISPLAY_DATA_SWAP_16BIT = 2, + DISPLAY_DATA_SWAP_32BIT = 4, + DISPLAY_DATA_SWAP_64BIT = 8, +} display_data_swap_t; + +#endif + +/** Display signal timing setting */ +typedef struct st_display_timing +{ + uint16_t total_cyc; ///< Total cycles in one line or total lines in one frame + uint16_t display_cyc; ///< Active video cycles or lines + uint16_t back_porch; ///< Back porch cycles or lines + uint16_t sync_width; ///< Sync signal asserting width + display_signal_polarity_t sync_polarity; ///< Sync signal polarity +} display_timing_t; + +/** RGB Color setting */ +typedef struct st_display_color +{ + union + { + uint32_t argb; ///< Entire color + struct + { + uint8_t b; ///< blue + uint8_t g; ///< green + uint8_t r; ///< red + uint8_t a; ///< alpha + } byte; + }; +} display_color_t; + +/** Contrast (gain) correction setting */ +typedef struct st_display_coordinate +{ + int16_t x; ///< Coordinate X, this allows to set signed value. + int16_t y; ///< Coordinate Y, this allows to set signed value. +} display_coordinate_t; + +/** Brightness (DC) correction setting */ +typedef struct st_display_brightness +{ + bool enable; ///< Brightness Correction On/Off + uint16_t r; ///< Brightness (DC) adjustment for R channel + uint16_t g; ///< Brightness (DC) adjustment for G channel + uint16_t b; ///< Brightness (DC) adjustment for B channel +} display_brightness_t; + +/** Contrast (gain) correction setting */ +typedef struct st_display_contrast +{ + bool enable; ///< Contrast Correction On/Off + uint8_t r; ///< Contrast (gain) adjustment for R channel + uint8_t g; ///< Contrast (gain) adjustment for G channel + uint8_t b; ///< Contrast (gain) adjustment for B channel +} display_contrast_t; + +/** Color correction setting */ +typedef struct st_display_correction +{ + display_brightness_t brightness; ///< Brightness + display_contrast_t contrast; ///< Contrast +} display_correction_t; + +/** Gamma correction setting for each color */ +typedef struct st_gamma_correction +{ + bool enable; ///< Gamma Correction On/Off + uint16_t * gain; ///< Gain adjustment + uint16_t * threshold; ///< Start threshold +} gamma_correction_t; + +/** Gamma correction setting */ +typedef struct st_display_gamma_correction +{ + gamma_correction_t r; ///< Gamma correction for R channel + gamma_correction_t g; ///< Gamma correction for G channel + gamma_correction_t b; ///< Gamma correction for B channel +} display_gamma_correction_t; + +/** CLUT setting */ +typedef struct st_display_clut +{ + uint32_t color_num; ///< The number of colors in CLUT + const uint32_t * p_clut; ///< Address of the area storing the CLUT data (in ARGB8888 format) +} display_clut_t; + +/** Color Keying setting */ +typedef struct st_display_colorkeying_cfg +{ + display_color_t src_color; ///< Source color + display_color_t dst_color; ///< Destination color + display_color_keying_t enable_ckey; ///< Select enable or disable +} display_colorkeying_cfg_t; + +/** Color Keying layer setting */ +typedef struct st_display_colorkeying_layer +{ + display_colorkeying_cfg_t layer[2]; +} display_colorkeying_layer_t; + +#ifndef BSP_OVERRIDE_DISPLAY_INPUT_CFG_T + +/** Graphics plane input configuration structure */ +typedef struct st_display_input_cfg +{ + uint32_t * p_base; ///< Base address to the frame buffer + uint16_t hsize; ///< Horizontal pixel size in a line + uint16_t vsize; ///< Vertical pixel size in a frame + uint32_t hstride; ///< Memory stride (bytes) in a line + display_in_format_t format; ///< Input format setting + bool line_descending_enable; ///< Line descending enable + bool lines_repeat_enable; ///< Line repeat enable + uint16_t lines_repeat_times; ///< Expected number of line repeating +} display_input_cfg_t; + +#endif + +/** Display output configuration structure */ +typedef struct st_display_output_cfg +{ + display_timing_t htiming; ///< Horizontal display cycle setting + display_timing_t vtiming; ///< Vertical display cycle setting + display_out_format_t format; ///< Output format setting + display_endian_t endian; ///< Bit order of output data + display_color_order_t color_order; ///< Color order in pixel + display_signal_polarity_t data_enable_polarity; ///< Data Enable signal polarity + display_sync_edge_t sync_edge; ///< Signal sync edge selection + display_color_t bg_color; ///< Background color + display_brightness_t brightness; ///< Brightness setting + display_contrast_t contrast; ///< Contrast setting + display_gamma_correction_t * p_gamma_correction; ///< Pointer to gamma correction setting + bool dithering_on; ///< Dithering on/off +} display_output_cfg_t; + +/** Graphics layer blend setup parameter structure */ +typedef struct st_display_layer +{ + display_coordinate_t coordinate; ///< Blending location (starting point of image) + display_color_t bg_color; ///< Color outside region + display_fade_control_t fade_control; ///< Layer fade-in/out control on/off + uint8_t fade_speed; ///< Layer fade-in/out frame rate +} display_layer_t; + +/** Display callback parameter definition */ +typedef struct st_display_callback_args +{ + display_event_t event; ///< Event code + void * p_context; ///< Context provided to user during callback +} display_callback_args_t; + +/** Display main configuration structure */ +typedef struct st_display_cfg +{ + /** Generic configuration for display devices */ + display_input_cfg_t input[2]; ///< Graphics input frame setting + display_output_cfg_t output; ///< Graphics output frame setting + display_layer_t layer[2]; ///< Graphics layer blend setting + uint8_t line_detect_ipl; ///< Line detect interrupt priority + uint8_t underflow_1_ipl; ///< Underflow 1 interrupt priority + uint8_t underflow_2_ipl; ///< Underflow 2 interrupt priority + IRQn_Type line_detect_irq; ///< Line detect interrupt vector + IRQn_Type underflow_1_irq; ///< Underflow 1 interrupt vector + IRQn_Type underflow_2_irq; ///< Underflow 2 interrupt vector + + /** Configuration for display event processing */ + void (* p_callback)(display_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /** Pointer to display peripheral specific configuration */ + void const * p_extend; ///< Display hardware dependent configuration +} display_cfg_t; + +/** Display main configuration structure */ +typedef struct st_display_runtime_cfg +{ + /** Generic configuration for display devices */ + display_input_cfg_t input; ///< Graphics input frame setting + display_layer_t layer; ///< Graphics layer alpha blending setting +} display_runtime_cfg_t; + +/** Display CLUT configuration structure */ +typedef struct st_display_clut_cfg +{ + uint32_t * p_base; ///< Pointer to CLUT source data + uint16_t start; ///< Beginning of CLUT entry to be updated + uint16_t size; ///< Size of CLUT entry to be updated +} display_clut_cfg_t; + +/** Display control block. Allocate an instance specific control block to pass into the display API calls. + */ + +/** Display control block */ +typedef void display_ctrl_t; + +/** Display Status */ +typedef struct st_display_status +{ + display_state_t state; ///< Status of display module + display_fade_status_t fade_status[DISPLAY_FRAME_LAYER_2 + 1]; ///< Status of fade-in/fade-out status +} display_status_t; + +/** Shared Interface definition for display peripheral */ +typedef struct st_display_api +{ + /** Open display device. + * @param[in,out] p_ctrl Pointer to display interface control block. Must be declared by user. Value set + * here. + * @param[in] p_cfg Pointer to display configuration structure. All elements of this structure must be + * set by user. + */ + fsp_err_t (* open)(display_ctrl_t * const p_ctrl, display_cfg_t const * const p_cfg); + + /** Close display device. + * @param[in] p_ctrl Pointer to display interface control block. + */ + fsp_err_t (* close)(display_ctrl_t * const p_ctrl); + + /** Display start. + * @param[in] p_ctrl Pointer to display interface control block. + */ + fsp_err_t (* start)(display_ctrl_t * const p_ctrl); + + /** Display stop. + * @param[in] p_ctrl Pointer to display interface control block. + */ + fsp_err_t (* stop)(display_ctrl_t * const p_ctrl); + + /** Change layer parameters at runtime. + * @param[in] p_ctrl Pointer to display interface control block. + * @param[in] p_cfg Pointer to run-time layer configuration structure. + * @param[in] frame Number of graphic frames. + */ + fsp_err_t (* layerChange)(display_ctrl_t const * const p_ctrl, display_runtime_cfg_t const * const p_cfg, + display_frame_layer_t frame); + + /** Change layer framebuffer pointer. + * @param[in] p_ctrl Pointer to display interface control block. + * @param[in] framebuffer Pointer to desired framebuffer. + * @param[in] frame Number of graphic frames. + */ + fsp_err_t (* bufferChange)(display_ctrl_t const * const p_ctrl, uint8_t * const framebuffer, + display_frame_layer_t frame); + + /** Color correction. + * @param[in] p_ctrl Pointer to display interface control block. + * @param[in] param Pointer to color correction configuration structure. + */ + fsp_err_t (* correction)(display_ctrl_t const * const p_ctrl, display_correction_t const * const p_param); + + /** Set CLUT for display device. + * @param[in] p_ctrl Pointer to display interface control block. + * @param[in] p_clut_cfg Pointer to CLUT configuration structure. + * @param[in] layer Layer number corresponding to the CLUT. + */ + fsp_err_t (* clut)(display_ctrl_t const * const p_ctrl, display_clut_cfg_t const * const p_clut_cfg, + display_frame_layer_t layer); + + /** Set CLUT element for display device. + * @param[in] p_ctrl Pointer to display interface control block. + * @param[in] layer Layer number corresponding to the CLUT. + * @param[in] index CLUT element index. + * @param[in] color Desired CLUT index color. + */ + fsp_err_t (* clutEdit)(display_ctrl_t const * const p_ctrl, display_frame_layer_t layer, uint8_t index, + uint32_t color); + + /** Configure color keying. + * @param[in] p_ctrl Pointer to display interface control block. + * @param[in] key_cfg Pointer to color keying configuration. + * @param[in] layer Layer to apply color keying. + */ + fsp_err_t (* colorKeySet)(display_ctrl_t const * const p_ctrl, display_colorkeying_layer_t key_cfg, + display_frame_layer_t layer); + + /** Get status for display device. + * @param[in] p_ctrl Pointer to display interface control block. + * @param[in] status Pointer to display interface status structure. + */ + fsp_err_t (* statusGet)(display_ctrl_t const * const p_ctrl, display_status_t * const p_status); +} display_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_display_instance +{ + display_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + display_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + display_api_t const * p_api; ///< Pointer to the API structure for this instance +} display_instance_t; + +/********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/* @} (end defgroup DISPLAY_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_doc_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_doc_api.h new file mode 100644 index 0000000000..565a75f64b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_doc_api.h @@ -0,0 +1,161 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_MONITORING_INTERFACES + * @defgroup DOC_API DOC Interface + * + * @brief Interface for the Data Operation Circuit. + * + * Defines the API and data structures for the DOC implementation of the Data Operation Circuit (DOC) interface. + * + * @section DOC_API_SUMMARY Summary + * @brief This module implements the DOC_API using the Data Operation Circuit (DOC). + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_DOC_API_H +#define R_DOC_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Event that can trigger a callback function. */ +typedef enum e_doc_event +{ + DOC_EVENT_COMPARISON_MISMATCH = 0x00, ///< The data is not equal to the reference data setting. + DOC_EVENT_ADDITION = 0x01, ///< Addition resulted in a value greater than the max for the configured bit width. + DOC_EVENT_SUBTRACTION = 0x02, ///< Subtraction resulted in a value less than 0. + DOC_EVENT_COMPARISON_MATCH = 0x04, ///< The data is equal to the reference data setting. + DOC_EVENT_COMPARISON_LOWER = 0x08, ///< The data is less than the reference data setting. + DOC_EVENT_COMPARISON_UPPER = 0x0C, ///< The data is greater than the reference data setting. + DOC_EVENT_COMPARISON_INSIDE_WINDOW = 0x10, ///< The data is between the two reference data settings. + DOC_EVENT_COMPARISON_OUTSIDE_WINDOW = 0x14, ///< The data is outside the two reference data setttings. +} doc_event_t; + +/** The bit width used during operations. */ +typedef enum e_doc_bit_width +{ + DOC_BIT_WIDTH_16, ///< Operations are 16-bit. + DOC_BIT_WIDTH_32 ///< Operations are 32-bit. +} doc_bit_width_t; + +/** Callback function parameter data. */ +typedef struct st_doc_callback_args +{ + void * p_context; ///< Placeholder for user data. + ///< Set in @ref doc_api_t::open function in @ref doc_cfg_t. +} doc_callback_args_t; + +/** DOC control block. Allocate an instance specific control block to pass into the DOC API calls. + */ +typedef void doc_ctrl_t; + +/** User configuration structure, used in the open function. */ +typedef struct st_doc_cfg +{ + doc_event_t event; ///< Select enumerated value from @ref doc_event_t. + doc_bit_width_t bit_width; ///< The bit width of operations. + + /** + * Initial/Reference data for addition, subtraction, and comparison operations. + * - In Addition and Subtraction mode, this value sets the initial value of the operations. + * - In Comparison match, mismatch, lower, and upper modes, this value is compared with data that is written. + * - In Comparison inside window and outside window modes, this value is used as the lower bound for comparisons. + */ + uint32_t doc_data; + + /** + * Additional reference data for use in Window Comparison operations. + * - In Comparison inside window and outside window modes, this value is used as the upper bound for comparisons. + */ + uint32_t doc_data_extra; + + uint8_t ipl; ///< DOC interrupt priority + IRQn_Type irq; ///< Interrupt number assigned to this instance + + /** Callback provided when a DOC ISR occurs. */ + void (* p_callback)(doc_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref doc_callback_args_t. */ + void * p_context; +} doc_cfg_t; + +/** Data Operation Circuit (DOC) API structure. DOC functions implemented at the HAL layer will follow this API. */ +typedef struct st_doc_api +{ + /** Initial configuration. + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(doc_ctrl_t * const p_ctrl, doc_cfg_t const * const p_cfg); + + /**Allow the driver to be reconfigured. Will reduce power consumption. + * @param[in] p_ctrl Control block set in @ref doc_api_t::open call. + */ + fsp_err_t (* close)(doc_ctrl_t * const p_ctrl); + + /** Gets the result of addition/subtraction operations and stores it in the provided pointer p_result. + * + * @param[in] p_ctrl Control block set in @ref doc_api_t::open call. + * @param[in] p_result The result of the DOC operation. + */ + fsp_err_t (* read)(doc_ctrl_t * const p_ctrl, uint32_t * p_result); + + /** Write to the DODIR register. + * + * @param[in] p_ctrl Control block set in @ref doc_api_t::open call. + * @param[in] data data to be written to DOC DODIR register. + */ + fsp_err_t (* write)(doc_ctrl_t * const p_ctrl, uint32_t data); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the DOC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(doc_ctrl_t * const p_ctrl, void (* p_callback)(doc_callback_args_t *), + void * const p_context, doc_callback_args_t * const p_callback_memory); +} doc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_doc_instance +{ + doc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + doc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + doc_api_t const * p_api; ///< Pointer to the API structure for this instance +} doc_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup DOC_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_elc_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_elc_api.h new file mode 100644 index 0000000000..ccd038e9ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_elc_api.h @@ -0,0 +1,160 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SYSTEM_INTERFACES + * @defgroup ELC_API ELC Interface + * @brief Interface for the Event Link Controller. + * + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_ELC_API_H +#define R_ELC_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef ELC_PERIPHERAL_NUM + #define ELC_PERIPHERAL_NUM (23U) +#endif + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_ELC_PERIPHERAL_T + +/** Possible peripherals to be linked to event signals (not all available on all MCUs) */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_ADC1 = (10), + ELC_PERIPHERAL_ADC1_B = (11), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_CTSU = (18), + ELC_PERIPHERAL_DA8_0 = (19), + ELC_PERIPHERAL_DA8_1 = (20), + ELC_PERIPHERAL_SDADC0 = (22), +} elc_peripheral_t; + +#endif + +/** ELC control block. Allocate an instance specific control block to pass into the ELC API calls. + */ +typedef void elc_ctrl_t; + +/** Main configuration structure for the Event Link Controller */ +typedef struct st_elc_cfg +{ + elc_event_t const link[ELC_PERIPHERAL_NUM]; ///< Event link register settings + void const * p_extend; ///< Extension parameter for hardware specific settings +} elc_cfg_t; + +#ifndef BSP_OVERRIDE_ELC_SOFTWARE_EVENT_T + +/** Software event number */ +typedef enum e_elc_software_event +{ + ELC_SOFTWARE_EVENT_0, ///< Software event 0 + ELC_SOFTWARE_EVENT_1, ///< Software event 1 +} elc_software_event_t; + +#endif + +/** ELC driver structure. General ELC functions implemented at the HAL layer follow this API. */ +typedef struct st_elc_api +{ + /** Initialize all links in the Event Link Controller. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to configuration structure. + **/ + fsp_err_t (* open)(elc_ctrl_t * const p_ctrl, elc_cfg_t const * const p_cfg); + + /** Disable all links in the Event Link Controller and close the API. + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(elc_ctrl_t * const p_ctrl); + + /** Generate a software event in the Event Link Controller. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] eventNum Software event number to be generated. + **/ + fsp_err_t (* softwareEventGenerate)(elc_ctrl_t * const p_ctrl, elc_software_event_t event_num); + + /** Create a single event link. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] peripheral The peripheral block that will receive the event signal. + * @param[in] signal The event signal. + **/ + fsp_err_t (* linkSet)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal); + + /** Break an event link. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] peripheral The peripheral that should no longer be linked. + **/ + fsp_err_t (* linkBreak)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral); + + /** Enable the operation of the Event Link Controller. + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* enable)(elc_ctrl_t * const p_ctrl); + + /** Disable the operation of the Event Link Controller. + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* disable)(elc_ctrl_t * const p_ctrl); +} elc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_elc_instance +{ + elc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + elc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + elc_api_t const * p_api; ///< Pointer to the API structure for this instance +} elc_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup ELC_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_api.h new file mode 100644 index 0000000000..73903d01af --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_api.h @@ -0,0 +1,250 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_NETWORKING_INTERFACES + * @defgroup ETHER_API Ethernet Interface + * @brief Interface for Ethernet functions. + * + * @section ETHER_API_Summary Summary + * The Ethernet interface provides Ethernet functionality. + * The Ethernet interface supports the following features: + * - Transmit/receive processing (Blocking and Non-Blocking) + * - Callback function with returned event code + * - Magic packet detection mode support + * - Auto negotiation support + * - Flow control support + * - Multicast filtering support + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_ETHER_API_H +#define R_ETHER_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_ether_phy_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Wake on LAN */ +typedef enum e_ether_wake_on_lan +{ + ETHER_WAKE_ON_LAN_DISABLE = 0, ///< Disable Wake on LAN + ETHER_WAKE_ON_LAN_ENABLE = 1, ///< Enable Wake on LAN +} ether_wake_on_lan_t; + +/** Flow control functionality */ +typedef enum e_ether_flow_control +{ + ETHER_FLOW_CONTROL_DISABLE = 0, ///< Disable flow control functionality + ETHER_FLOW_CONTROL_ENABLE = 1, ///< Enable flow control functionality with pause frames +} ether_flow_control_t; + +/** Multicast Filter */ +typedef enum e_ether_multicast +{ + ETHER_MULTICAST_DISABLE = 0, ///< Disable reception of multicast frames + ETHER_MULTICAST_ENABLE = 1, ///< Enable reception of multicast frames +} ether_multicast_t; + +/** Promiscuous Mode */ +typedef enum e_ether_promiscuous +{ + ETHER_PROMISCUOUS_DISABLE = 0, ///< Only receive packets with current MAC address, multicast, and broadcast + ETHER_PROMISCUOUS_ENABLE = 1, ///< Receive all packets +} ether_promiscuous_t; + +/** Zero copy */ +typedef enum e_ether_zerocopy +{ + ETHER_ZEROCOPY_DISABLE = 0, ///< Disable zero copy in Read/Write function + ETHER_ZEROCOPY_ENABLE = 1, ///< Enable zero copy in Read/Write function +} ether_zerocopy_t; + +typedef enum e_ether_padding +{ + ETHER_PADDING_DISABLE = 0, + ETHER_PADDING_1BYTE = 1, + ETHER_PADDING_2BYTE = 2, + ETHER_PADDING_3BYTE = 3, +} ether_padding_t; + +#ifndef BSP_OVERRIDE_ETHER_EVENT_T + +/** Event code of callback function */ +typedef enum e_ether_event +{ + ETHER_EVENT_WAKEON_LAN, ///< Magic packet detection event + ETHER_EVENT_LINK_ON, ///< Link up detection event + ETHER_EVENT_LINK_OFF, ///< Link down detection event + ETHER_EVENT_RX_COMPLETE, ///< Receive complete event. + ETHER_EVENT_RX_MESSAGE_LOST, ///< Receive FIFO overflow or Receive descriptor is full. + ETHER_EVENT_TX_COMPLETE, ///< Transmit complete event. + ETHER_EVENT_TX_BUFFER_EMPTY, ///< Transmit descriptor or FIFO is empty. + ETHER_EVENT_TX_ABORTED, ///< Transmit abort event. + ETHER_EVENT_ERR_GLOBAL, ///< Global error has occurred. + ETHER_EVENT_GET_NIC_INFO, ///< Get NIC Info. +} ether_event_t; +#endif + +/** Network interface device information */ +typedef struct st_ether_nic_info +{ + uint8_t * p_mac_address; ///< MAC address +} ether_nic_info_t; + +#ifndef BSP_OVERRIDE_ETHER_CALLBACK_ARGS_T + +/** Callback Function Parameter Data */ +typedef struct st_ether_callback_args +{ + uint32_t channel; ///< Device channel number + ether_event_t event; ///< Event code + uint32_t status_ecsr; ///< ETHERC status register for interrupt handler + uint32_t status_eesr; ///< ETHERC/EDMAC status register for interrupt handler + ether_nic_info_t * p_nic_info; ///< Pointer of NIC info + void * p_context; ///< Placeholder for user data. Set in @ref ether_api_t::open function in @ref ether_cfg_t. +} ether_callback_args_t; +#endif + +/** Control block. Allocate an instance specific control block to pass into the API calls. */ +typedef void ether_ctrl_t; + +/** Configuration parameters. */ +typedef struct st_ether_cfg +{ + uint8_t channel; ///< Channel + ether_zerocopy_t zerocopy; ///< Zero copy enable or disable in Read/Write function + ether_multicast_t multicast; ///< Multicast enable or disable + ether_promiscuous_t promiscuous; ///< Promiscuous mode enable or disable + ether_flow_control_t flow_control; ///< Flow control functionally enable or disable + ether_padding_t padding; ///< Padding length inserted into the received Ethernet frame. + uint32_t padding_offset; ///< Offset of the padding inserted into the received Ethernet frame. + uint32_t broadcast_filter; ///< Limit of the number of broadcast frames received continuously + uint8_t * p_mac_address; ///< Pointer of MAC address + uint8_t num_tx_descriptors; ///< Number of transmission descriptor + uint8_t num_rx_descriptors; ///< Number of receive descriptor + uint8_t ** pp_ether_buffers; ///< Transmit and receive buffer + uint32_t ether_buffer_size; ///< Size of transmit and receive buffer + IRQn_Type irq; ///< Interrupt number + uint32_t interrupt_priority; ///< Interrupt priority + void (* p_callback)(ether_callback_args_t * p_args); ///< Callback provided when an ISR occurs. + ether_phy_instance_t const * p_ether_phy_instance; ///< Pointer to ETHER_PHY instance + + /** Placeholder for user data. Passed to the user callback in ether_callback_args_t. */ + void * p_context; ///< Placeholder for user data. + void const * p_extend; ///< Placeholder for user extension. +} ether_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_ether_api +{ + /** Open driver. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p_cfg); + + /** Close driver. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(ether_ctrl_t * const p_ctrl); + + /** Read packet if data is available. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buffer Pointer to where to store read data. + * @param[in,out] length_bytes Number of bytes in buffer + */ + fsp_err_t (* read)(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t * const length_bytes); + + /** Release rx buffer from buffer pool process in zero-copy read operation. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* bufferRelease)(ether_ctrl_t * const p_ctrl); + + /** Update the buffer pointer in the current receive descriptor. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buffer New address to write into the rx buffer descriptor. + */ + fsp_err_t (* rxBufferUpdate)(ether_ctrl_t * const p_ctrl, void * const p_buffer); + + /** Write packet. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buffer Pointer to data to write. + * @param[in] frame_length Send ethernet frame size (without 4 bytes of CRC data size). + */ + fsp_err_t (* write)(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length); + + /** Process link. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* linkProcess)(ether_ctrl_t * const p_ctrl); + + /** Enable magic packet detection. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* wakeOnLANEnable)(ether_ctrl_t * const p_ctrl); + + /** Get the address of the most recently sent buffer. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_buffer_address Pointer to the address of the most recently sent buffer. + */ + fsp_err_t (* txStatusGet)(ether_ctrl_t * const p_ctrl, void * const p_buffer_address); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the ETHER control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(ether_ctrl_t * const p_ctrl, void (* p_callback)(ether_callback_args_t *), + void * const p_context, ether_callback_args_t * const p_callback_memory); +} ether_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ether_instance +{ + ether_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ether_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ether_api_t const * p_api; ///< Pointer to the API structure for this instance +} ether_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup ETHER_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_ETHER_API_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_phy_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_phy_api.h new file mode 100644 index 0000000000..3ca277179b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_phy_api.h @@ -0,0 +1,214 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_NETWORKING_INTERFACES + * @defgroup ETHER_PHY_API Ethernet PHY Interface + * @brief Interface for Ethernet PHY functions. + * + * @section ETHER_PHY_API_Summary Summary + * The Ethernet PHY module (r_ether_phy) provides an API for standard Ethernet PHY communications applications that use + * the Ethernet peripheral. + * + * The Ethernet PHY interface supports the following features: + * - Auto negotiation support + * - Flow control support + * - Link status check support + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_ETHER_PHY_API_H +#define R_ETHER_PHY_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_ETHER_PHY_LSI_TYPE_T + +/** Phy LSI */ +typedef enum e_ether_phy_lsi_type +{ + ETHER_PHY_LSI_TYPE_DEFAULT = 0, ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option. + ETHER_PHY_LSI_TYPE_KSZ8091RNB = 1, ///< Select configuration for KSZ8091RNB. + ETHER_PHY_LSI_TYPE_KSZ8041 = 2, ///< Select configuration for KSZ8041. + ETHER_PHY_LSI_TYPE_DP83620 = 3, ///< Select configuration for DP83620. + ETHER_PHY_LSI_TYPE_ICS1894 = 4, ///< Select configuration for ICS1894. + ETHER_PHY_LSI_TYPE_GPY111 = 5, ///< Select configuration for GPY111. + ETHER_PHY_LSI_TYPE_CUSTOM = 0xFFU, ///< Select configuration for User custom. +} ether_phy_lsi_type_t; +#endif + +/** Flow control functionality */ +typedef enum e_ether_phy_flow_control +{ + ETHER_PHY_FLOW_CONTROL_DISABLE = 0, ///< Disable flow control functionality + ETHER_PHY_FLOW_CONTROL_ENABLE = 1, ///< Enable flow control functionality with pause frames +} ether_phy_flow_control_t; + +/** Link speed */ +typedef enum e_ether_phy_link_speed +{ + ETHER_PHY_LINK_SPEED_NO_LINK = 0, ///< Link is not established + ETHER_PHY_LINK_SPEED_10H = 1, ///< Link status is 10Mbit/s and half duplex + ETHER_PHY_LINK_SPEED_10F = 2, ///< Link status is 10Mbit/s and full duplex + ETHER_PHY_LINK_SPEED_100H = 3, ///< Link status is 100Mbit/s and half duplex + ETHER_PHY_LINK_SPEED_100F = 4, ///< Link status is 100Mbit/s and full duplex + ETHER_PHY_LINK_SPEED_1000H = 5, ///< Link status is 1000Mbit/s and half duplex + ETHER_PHY_LINK_SPEED_1000F = 6 ///< Link status is 1000Mbit/s and full duplex +} ether_phy_link_speed_t; + +/** Media-independent interface */ +typedef enum e_ether_phy_mii_type +{ + ETHER_PHY_MII_TYPE_MII = 0, ///< MII + ETHER_PHY_MII_TYPE_RMII = 1, ///< RMII + ETHER_PHY_MII_TYPE_GMII = 2, ///< GMII + ETHER_PHY_MII_TYPE_RGMII = 3 ///< RGMII +} ether_phy_mii_type_t; + +/** Event code of callback function */ +typedef enum e_ether_phy_event +{ + /* Frame preemption events. */ + ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_FAIL, ///< Preemption link verification failed. + ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_SUCCESS, ///< Preemption link verification succeeded. + ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_RECEIVE, ///< Preemption link verification frame received. +} ether_phy_event_t; + +/** Callback function parameter data */ +typedef struct st_ether_phy_callback_args +{ + uint32_t channel; ///< Device channel number + uint32_t port; ///< Device port number + ether_phy_event_t event; ///< Event code + + void * p_context; ///< Placeholder for user data. Set in @ref ether_api_t::open function in @ref ether_cfg_t. +} ether_phy_callback_args_t; + +/** Control block. Allocate an instance specific control block to pass into the API calls. + */ +typedef void ether_phy_ctrl_t; + +/** Configuration parameters. */ +typedef struct st_ether_phy_cfg +{ + uint8_t channel; ///< Channel + uint8_t phy_lsi_address; ///< DEPRECATED Address of PHY-LSI + + uint32_t phy_reset_wait_time; ///< Wait time for PHY-LSI reboot + int32_t mii_bit_access_wait_time; ///< Wait time for MII/RMII access + ether_phy_lsi_type_t phy_lsi_type; ///< DEPRECATED Phy LSI type + + ether_phy_flow_control_t flow_control; ///< Flow control functionally enable or disable + ether_phy_mii_type_t mii_type; ///< Interface type is MII or RMII + + /** Placeholder for user data. Passed to the user callback in ether_phy_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Placeholder for user extension. +} ether_phy_cfg_t; + +/** PHY LSI configuration. */ +typedef struct st_ether_phy_lsi_cfg +{ + uint8_t address; ///< Address of PHY-LSI + ether_phy_lsi_type_t type; ///< Phy LSI type +} ether_phy_lsi_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_ether_phy_api +{ + /** Open driver. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg); + + /** Close driver. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(ether_phy_ctrl_t * const p_ctrl); + + /** Initialize PHY-LSI. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* chipInit)(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg); + + /** Read register value of PHY-LSI. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] reg_addr Register address. + * @param[out] p_data Pointer to the location to store read data. + */ + fsp_err_t (* read)(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data); + + /** Write data to register of PHY-LSI. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] reg_addr Register address. + * @param[in] data Data written to register. + */ + fsp_err_t (* write)(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data); + + /** Start auto negotiation. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* startAutoNegotiate)(ether_phy_ctrl_t * const p_ctrl); + + /** Get the partner ability. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_line_speed_duplex Pointer to the location of both the line speed and the duplex. + * @param[out] p_local_pause Pointer to the location to store the local pause bits. + * @param[out] p_partner_pause Pointer to the location to store the partner pause bits. + */ + fsp_err_t (* linkPartnerAbilityGet)(ether_phy_ctrl_t * const p_ctrl, uint32_t * const p_line_speed_duplex, + uint32_t * const p_local_pause, uint32_t * const p_partner_pause); + + /** Get Link status from PHY-LSI interface. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* linkStatusGet)(ether_phy_ctrl_t * const p_ctrl); +} ether_phy_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ether_phy_instance +{ + ether_phy_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ether_phy_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ether_phy_api_t const * p_api; ///< Pointer to the API structure for this instance +} ether_phy_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup ETHER_PHY_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_ETHER_PHY_API_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_switch_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_switch_api.h new file mode 100644 index 0000000000..2a09dc3886 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ether_switch_api.h @@ -0,0 +1,118 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_NETWORKING_INTERFACES + * @defgroup ETHER_SWITCH_API Ethernet Switch Interface + * @brief Interface for Ethernet Switch functions. + * + * @section ETHER_SWITCH_API_Summary Summary + * The Ether Switch module provides an API for ethernet switch peripheral. + * And the general ethernet switch peripheral have forwarding functionality. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_ETHER_SWITCH_API_H +#define R_ETHER_SWITCH_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_ETHER_SWITCH_EVENT_T + +/** Events that can trigger a callback function */ +typedef enum e_ether_switch_event +{ + ETHER_SWITCH_EVENT_RX_COMPLETE, ///< A descriptor complete to receive a flame. + ETHER_SWITCH_EVENT_TX_COMPLETE, ///< A descriptor complete to transmit a flame. + ETHER_SWITCH_EVENT_RX_QUEUE_FULL, ///< A RX descriptor queue is full. + ETHER_SWITCH_EVENT_RX_MESSAGE_LOST, ///< Receive a frame when a RX descriptor queue is full. + ETHER_SWITCH_EVENT_TAS_ERROR, ///< TAS gate error. +} ether_switch_event_t; +#endif + +#ifndef BSP_OVERRIDE_ETHER_SWITCH_CALLBACK_ARGS_T + +/** Callback function parameter data */ +typedef struct st_ether_switch_callback_args +{ + uint32_t channel; ///< Device channel number + uint32_t ports; ///< Bitmap of ports on which the interrupt occurred. + uint32_t queue_index; ///< Queue index where a interrupt occurs. + ether_switch_event_t event; ///< The event can be used to identify what caused the callback. + + void * p_context; ///< Placeholder for user data. Set in @ref ether_switch_api_t::open function in @ref ether_switch_cfg_t. +} ether_switch_callback_args_t; +#endif + +/** Control block. Allocate an instance specific control block to pass into the API calls. + */ +typedef void ether_switch_ctrl_t; + +/** Configuration parameters. */ +typedef struct st_ether_switch_cfg +{ + uint8_t channel; ///< Channel + + IRQn_Type irq; ///< MCU interrupt number + uint8_t ipl; ///< MCU interrupt priority + + void (* p_callback)(ether_switch_callback_args_t * p_args); ///< Callback provided when an ISR occurs. + + /** Placeholder for user data. Passed to the user callback in ether_switch_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Placeholder for user extension. +} ether_switch_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_ether_switch_api +{ + /** Open driver. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(ether_switch_ctrl_t * const p_ctrl, ether_switch_cfg_t const * const p_cfg); + + /** Close driver. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(ether_switch_ctrl_t * const p_ctrl); +} ether_switch_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ether_switch_instance +{ + ether_switch_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ether_switch_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ether_switch_api_t const * p_api; ///< Pointer to the API structure for this instance +} ether_switch_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup ETHER_SWITCH_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_ETHER_SWITCH_API_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_external_irq_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_external_irq_api.h new file mode 100644 index 0000000000..da8dcf8bd6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_external_irq_api.h @@ -0,0 +1,159 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INPUT_INTERFACES + * @defgroup EXTERNAL_IRQ_API External IRQ Interface + * @brief Interface for detecting external interrupts. + * + * @section EXTERNAL_IRQ_API_Summary Summary + * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an + * external IRQ pin. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_EXTERNAL_IRQ_API_H +#define R_EXTERNAL_IRQ_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** Callback function parameter data */ +typedef struct st_external_irq_callback_args +{ + /** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */ + void * p_context; + uint32_t channel; ///< The physical hardware channel that caused the interrupt. +} external_irq_callback_args_t; + +#ifndef BSP_OVERRIDE_EXTERNAL_IRQ_TRIGGER_T + +/** Condition that will trigger an interrupt when detected. */ +typedef enum e_external_irq_trigger +{ + EXTERNAL_IRQ_TRIGGER_FALLING = 0, ///< Falling edge trigger + EXTERNAL_IRQ_TRIGGER_RISING = 1, ///< Rising edge trigger + EXTERNAL_IRQ_TRIGGER_BOTH_EDGE = 2, ///< Both edges trigger + EXTERNAL_IRQ_TRIGGER_LEVEL_LOW = 3, ///< Low level trigger + EXTERNAL_IRQ_TRIGGER_LEVEL_HIGH = 4, ///< High level trigger + EXTERNAL_IRQ_TRIG_FALLING = EXTERNAL_IRQ_TRIGGER_FALLING, ///< DEPRECATED, do not use + EXTERNAL_IRQ_TRIG_RISING = EXTERNAL_IRQ_TRIGGER_RISING, ///< DEPRECATED, do not use + EXTERNAL_IRQ_TRIG_BOTH_EDGE = EXTERNAL_IRQ_TRIGGER_BOTH_EDGE, ///< DEPRECATED, do not use + EXTERNAL_IRQ_TRIG_LEVEL_LOW = EXTERNAL_IRQ_TRIGGER_LEVEL_LOW, ///< DEPRECATED, do not use + EXTERNAL_IRQ_TRIG_LEVEL_HIGH = EXTERNAL_IRQ_TRIGGER_LEVEL_HIGH ///< DEPRECATED, do not use +} external_irq_trigger_t; +#endif + +#ifndef BSP_OVERRIDE_EXTERNAL_IRQ_PCLK_DIV_T + +/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger + * conditions that are shorter than 3 periods of the filter clock. + */ +typedef enum e_external_irq_clock_source_div +{ + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1 = 0, ///< Filter using clock source divided by 1 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_8 = 1, ///< Filter using clock source divided by 8 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_32 = 2, ///< Filter using clock source divided by 32 + EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64 = 3, ///< Filter using clock source divided by 64 +} external_irq_clock_source_div_t; +#endif + +/** User configuration structure, used in open function */ +typedef struct st_external_irq_cfg +{ + uint8_t channel; ///< Hardware channel used. + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< Interrupt number assigned to this instance + external_irq_trigger_t trigger; ///< Trigger setting. + external_irq_clock_source_div_t clock_source_div; ///< Digital filter clock divisor setting. + bool filter_enable; ///< Digital filter enable/disable selection. + + /** Callback provided external input trigger occurs. */ + void (* p_callback)(external_irq_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref external_irq_callback_args_t. */ + void * p_context; + void const * p_extend; ///< External IRQ hardware dependent configuration. +} external_irq_cfg_t; + +/** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls. + */ +typedef void external_irq_ctrl_t; + +/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */ +typedef struct st_external_irq_api +{ + /** Initial configuration. + * + * @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user. + */ + fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg); + + /** Enable callback when an external trigger condition occurs. + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl); + + /** Disable callback when external trigger condition occurs. + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the External IRQ control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_ctrl, void (* p_callback)(external_irq_callback_args_t *), + void * const p_context, external_irq_callback_args_t * const p_callback_memory); + + /** Allow driver to be reconfigured. May reduce power consumption. + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl); +} external_irq_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_external_irq_instance +{ + external_irq_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + external_irq_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + external_irq_api_t const * p_api; ///< Pointer to the API structure for this instance +} external_irq_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*******************************************************************************************************************//** + * @} (end defgroup EXTERNAL_IRQ_API) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_flash_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_flash_api.h new file mode 100644 index 0000000000..172cbbdfd4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_flash_api.h @@ -0,0 +1,356 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_STORAGE_INTERFACES + * @defgroup FLASH_API Flash Interface + * @brief Interface for the Flash Memory. + * + * @section FLASH_API_SUMMARY Summary + * + * The Flash interface provides the ability to read, write, erase, and blank check the code flash and data flash + * regions. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_FLASH_API_H +#define R_FLASH_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** Result type for certain operations */ +typedef enum e_flash_result +{ + FLASH_RESULT_BLANK, ///< Return status for Blank Check Function + FLASH_RESULT_NOT_BLANK, ///< Return status for Blank Check Function + FLASH_RESULT_BGO_ACTIVE ///< Flash is configured for BGO mode. Result is returned in callback. +} flash_result_t; + +/** Parameter for specifying the startup area swap being requested by startupAreaSelect() */ +typedef enum e_flash_startup_area_swap +{ + FLASH_STARTUP_AREA_BTFLG = 0, ///< Startup area will be set based on the value of the BTFLG + FLASH_STARTUP_AREA_BLOCK0 = 0x2, ///< Startup area will be set to Block 0 + FLASH_STARTUP_AREA_BLOCK1 = 0x3, ///< Startup area will be set to Block 1 +} flash_startup_area_swap_t; + +/** Event types returned by the ISR callback when used in Data Flash BGO mode */ +typedef enum e_flash_event +{ + FLASH_EVENT_ERASE_COMPLETE, ///< Erase operation successfully completed + FLASH_EVENT_WRITE_COMPLETE, ///< Write operation successfully completed + FLASH_EVENT_BLANK, ///< Blank check operation successfully completed. Specified area is blank + FLASH_EVENT_NOT_BLANK, ///< Blank check operation successfully completed. Specified area is NOT blank + FLASH_EVENT_ERR_DF_ACCESS, ///< Data Flash operation failed. Can occur when writing an unerased section. + FLASH_EVENT_ERR_CF_ACCESS, ///< Code Flash operation failed. Can occur when writing an unerased section. + FLASH_EVENT_ERR_CMD_LOCKED, ///< Operation failed, FCU is in Locked state (often result of an illegal command) + FLASH_EVENT_ERR_FAILURE, ///< Erase or Program Operation failed + FLASH_EVENT_ERR_ONE_BIT, ///< A 1-bit error has been corrected when reading the flash memory area by the sequencer. See callback 'data' field for address. + FLASH_EVENT_ERR_TWO_BIT, ///< A 2-bit error has been corrected when reading the flash memory area by the sequencer. See callback 'data' field for address. + FLASH_EVENT_ERR_ECC, ///< An uncorrectable error has been detected while reading memory. See callback 'data' field for address. +} flash_event_t; + +/** ID Code Modes for writing to ID code registers */ +typedef enum e_flash_id_code_mode +{ + FLASH_ID_CODE_MODE_UNLOCKED = 0, ///< ID code is ignored + FLASH_ID_CODE_MODE_LOCKED_WITH_ALL_ERASE_SUPPORT = 0xC000U, ///< ID code is checked. All erase is available. + FLASH_ID_CODE_MODE_LOCKED = 0x8000U ///< ID code is checked. +} flash_id_code_mode_t; + +/** Flash status */ +typedef enum e_flash_status +{ + FLASH_STATUS_IDLE, ///< The flash is idle. + FLASH_STATUS_BUSY ///< The flash is currently processing a command. +} flash_status_t; + +/** Anti-rollback counter selection. */ +typedef enum e_flash_arc +{ + FLASH_ARC_SEC = 0, ///< Anti-Rollback Counter for the secure application + FLASH_ARC_OEMBL = 1, ///< Anti-Rollback Counter for the OEM bootloader + FLASH_ARC_NSEC_0 = 2, ///< Anti-Rollback Counter for non-secure application 0 (use when a single non-secure counter is available or when multiple non-secure counters are available) + FLASH_ARC_NSEC_1 = 3, ///< Anti-Rollback Counter for non-secure application 1 (use when multiple non-secure counters are available) + FLASH_ARC_NSEC_2 = 4, ///< Anti-Rollback Counter for non-secure application 2 (use when multiple non-secure counters are available) + FLASH_ARC_NSEC_3 = 5, ///< Anti-Rollback Counter for non-secure application 3 (use when multiple non-secure counters are available) +} flash_arc_t; + +/** Flash block details stored in factory flash. */ +typedef struct st_flash_block_info +{ + uint32_t block_section_st_addr; ///< Starting address for this block section (blocks of this size) + uint32_t block_section_end_addr; ///< Ending address for this block section (blocks of this size) + uint32_t block_size; ///< Flash erase block size + uint32_t block_size_write; ///< Flash write block size +} flash_block_info_t; + +/** Flash block details */ +typedef struct st_flash_regions +{ + uint32_t num_regions; ///< Length of block info array + flash_block_info_t const * p_block_array; ///< Block info array base address +} flash_regions_t; + +/** Information about the flash blocks */ +typedef struct st_flash_info +{ + flash_regions_t code_flash; ///< Information about the code flash regions + flash_regions_t data_flash; ///< Information about the code flash regions +} flash_info_t; + +/** Flash control block. Allocate an instance specific control block to pass into the flash API calls. + */ +typedef void flash_ctrl_t; + +/** Callback function parameter data */ +typedef struct st_flash_user_cb_data +{ + flash_event_t event; ///< Event can be used to identify what caused the callback (flash ready or error). + uint32_t data; ///< Event specific data. Invalid unless specified by the event. + void * p_context; ///< Placeholder for user data. Set in @ref flash_api_t::open function in::flash_cfg_t. +} flash_callback_args_t; + +/** FLASH Configuration */ +typedef struct st_flash_cfg +{ + bool data_flash_bgo; ///< True if BGO (Background Operation) is enabled for Data Flash. + + /* Configuration for FLASH Event processing */ + void (* p_callback)(flash_callback_args_t * p_args); ///< Callback provided when a Flash interrupt ISR occurs. + + /* Pointer to FLASH peripheral specific configuration */ + void const * p_extend; ///< FLASH hardware dependent configuration + void * p_context; ///< Placeholder for user data. Passed to user callback in @ref flash_callback_args_t. + uint8_t ipl; ///< Flash ready interrupt priority + IRQn_Type irq; ///< Flash ready interrupt number + uint8_t err_ipl; ///< Flash error interrupt priority (unused in r_flash_lp) + IRQn_Type err_irq; ///< Flash error interrupt number (unused in r_flash_lp) +} flash_cfg_t; + +/** Shared Interface definition for FLASH */ +typedef struct st_flash_api +{ + /** Open FLASH device. + * + * @param[out] p_ctrl Pointer to FLASH device control. Must be declared by user. Value set here. + * @param[in] flash_cfg_t Pointer to FLASH configuration structure. All elements of this structure + * must be set by the user. + */ + fsp_err_t (* open)(flash_ctrl_t * const p_ctrl, flash_cfg_t const * const p_cfg); + + /** Write FLASH device. + * + * @param[in] p_ctrl Control for the FLASH device context. + * @param[in] src_address Address of the buffer containing the data to write to Flash. + * @param[in] flash_address Code Flash or Data Flash address to write. The address must be on a + * programming line boundary. + * @param[in] num_bytes The number of bytes to write. This number must be a multiple + * of the programming size. For Code Flash this is FLASH_MIN_PGM_SIZE_CF. + * For Data Flash this is FLASH_MIN_PGM_SIZE_DF. + * @warning Specifying a number that is not a multiple of the programming size + * will result in SF_FLASH_ERR_BYTES being returned and no data written. + */ + fsp_err_t (* write)(flash_ctrl_t * const p_ctrl, uint32_t const src_address, uint32_t const flash_address, + uint32_t const num_bytes); + + /** Erase FLASH device. + * + * @param[in] p_ctrl Control for the FLASH device. + * @param[in] address The block containing this address is the first block erased. + * @param[in] num_blocks Specifies the number of blocks to be erased, the starting block determined + * by the block_erase_address. + */ + fsp_err_t (* erase)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_blocks); + + /** Blank check FLASH device. + * + * @param[in] p_ctrl Control for the FLASH device context. + * @param[in] address The starting address of the Flash area to blank check. + * @param[in] num_bytes Specifies the number of bytes that need to be checked. + * See the specific handler for details. + * @param[out] p_blank_check_result Pointer that will be populated by the API with the results of the blank check + * operation in non-BGO (blocking) mode. In this case the blank check operation + * completes here and the result is returned. In Data Flash BGO mode the blank + * check operation is only started here and the result obtained later when the + * supplied callback routine is called. In this case FLASH_RESULT_BGO_ACTIVE will + * be returned in p_blank_check_result. + */ + fsp_err_t (* blankCheck)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_bytes, + flash_result_t * const p_blank_check_result); + + /** Close FLASH device. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[out] p_info Pointer to FLASH info structure. + */ + fsp_err_t (* infoGet)(flash_ctrl_t * const p_ctrl, flash_info_t * const p_info); + + /** Close FLASH device. + * + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* close)(flash_ctrl_t * const p_ctrl); + + /** Get Status for FLASH device. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[out] p_ctrl Pointer to the current flash status. + */ + fsp_err_t (* statusGet)(flash_ctrl_t * const p_ctrl, flash_status_t * const p_status); + + /** Set Access Window for FLASH device. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. This address will not be + * within the access window. + */ + fsp_err_t (* accessWindowSet)(flash_ctrl_t * const p_ctrl, uint32_t const start_addr, uint32_t const end_addr); + + /** Clear any existing Code Flash access window for FLASH device. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. + */ + fsp_err_t (* accessWindowClear)(flash_ctrl_t * const p_ctrl); + + /** Set ID Code for FLASH device. Setting the ID code can restrict access to the device. The ID code will be + * required to connect to the device. Bits 126 and 127 are set based on the mode. + * + * For example, uint8_t id_bytes[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + * 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x00}; + * with mode FLASH_ID_CODE_MODE_LOCKED_WITH_ALL_ERASE_SUPPORT + * will result in an ID code of 00112233445566778899aabbccddeec0 + * + * With mode FLASH_ID_CODE_MODE_LOCKED, it + * will result in an ID code of 00112233445566778899aabbccddee80 + * + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] p_id_bytes Ponter to the ID Code to be written. + * @param[in] mode Mode used for checking the ID code. + */ + fsp_err_t (* idCodeSet)(flash_ctrl_t * const p_ctrl, uint8_t const * const p_id_bytes, flash_id_code_mode_t mode); + + /** Reset function for FLASH device. + * + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* reset)(flash_ctrl_t * const p_ctrl); + + /** Update Flash clock frequency (FCLK) and recalculate timeout values + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* updateFlashClockFreq)(flash_ctrl_t * const p_ctrl); + + /** Select which block - Default (Block 0) or Alternate (Block 1) is used as the start-up area block. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] swap_type FLASH_STARTUP_AREA_BLOCK0, FLASH_STARTUP_AREA_BLOCK1 or FLASH_STARTUP_AREA_BTFLG. + * @param[in] is_temporary True or false. See table below. + * + * | swap_type | is_temporary | Operation | + * |-----------------------|-----------------|-------------| + * | FLASH_STARTUP_AREA_BLOCK0 | false | On next reset Startup area will be Block 0. | + * | FLASH_STARTUP_AREA_BLOCK1 | true | Startup area is immediately, but temporarily switched to Block 1. | + * | FLASH_STARTUP_AREA_BTFLG | true | Startup area is immediately, but temporarily switched to the Block determined by the Configuration BTFLG. | + * + */ + fsp_err_t (* startupAreaSelect)(flash_ctrl_t * const p_ctrl, flash_startup_area_swap_t swap_type, + bool is_temporary); + + /** Swap the bank used as the startup area. On Flash HP, need to change into dual bank mode to use this feature. + * + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* bankSwap)(flash_ctrl_t * const p_ctrl); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(flash_ctrl_t * const p_ctrl, void (* p_callback)(flash_callback_args_t *), + void * const p_context, flash_callback_args_t * const p_callback_memory); + + /** Increment the selected anti-rollback counter. + * + * @warning Once incremented, the counter can never be decremented or reset, even with a debug probe. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] counter The anti-rollback counter to increment + */ + fsp_err_t (* antiRollbackCounterIncrement)(flash_ctrl_t * const p_ctrl, flash_arc_t counter); + + /** Refresh the selected anti-rollback counter flash area. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] counter The anti-rollback counter to refresh + */ + fsp_err_t (* antiRollbackCounterRefresh)(flash_ctrl_t * const p_ctrl, flash_arc_t counter); + + /** Read current count value of the selected anti-rollback counter. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] counter The anti-rollback counter to read + * @param[out] p_count The current count value + */ + fsp_err_t (* antiRollbackCounterRead)(flash_ctrl_t * const p_ctrl, flash_arc_t counter, uint32_t * const p_count); + + /** Write to the user lockable area for the flash device + * + * @warning Data will not be written if any segment of the specified area is locked. + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] src_address Address of the buffer containing the data to write to flash. + * @param[in] flash_address User lockable area flash address to write. The address must be on a + * programming line boundary. + * @param[in] num_bytes The number of bytes to write. This number must be a multiple + * of the programming size. + */ + fsp_err_t (* userLockableAreaWrite)(flash_ctrl_t * const p_ctrl, uint32_t const src_address, + uint32_t const flash_address, uint32_t const num_bytes); +} flash_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_flash_instance +{ + flash_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + flash_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + flash_api_t const * p_api; ///< Pointer to the API structure for this instance +} flash_instance_t; + +/******************************************************************************************************************//** + * @} (end defgroup FLASH_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_gptp_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_gptp_api.h new file mode 100644 index 0000000000..5a45b2ac13 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_gptp_api.h @@ -0,0 +1,161 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_NETWORKING_INTERFACES + * @defgroup GPTP_API GPTP Interface + * @brief Interface for gPTP timing. + * + * @section GPTP_API_Summary Summary + * The gPTP API provides a generic interface for gPTP timer operation. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_GPTP_API_H +#define R_GPTP_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Timer value. */ +typedef struct st_gptp_timer_value +{ + uint16_t time_sec_upper; ///< Second(Upper 16 bit). + uint32_t time_sec_lower; ///< Second(Lower 32 bit). + uint32_t time_nsec; ///< Nanosecond. +} gptp_timer_value_t; + +/** Configuration of gPTP timer. */ +typedef struct st_gptp_timer_cfg +{ + uint8_t clock_period; ///< Timer increment value. +} gptp_timer_cfg_t; + +/** Control block. Allocate an instance specific control block to pass into the API calls. + */ +typedef void gptp_ctrl_t; + +/** GPTP callback arguments definitions. */ +typedef struct st_gptp_callback_args +{ + void * p_context; ///< Placeholder for user data. Set in @ref gptp_api_t::open function in @ref gptp_cfg_t. +} gptp_callback_args_t; + +/** Configuration parameters. */ +typedef struct st_gptp_cfg +{ + void (* p_callback)(gptp_callback_args_t * p_args); ///< Pointer to callback function. + void * p_context; ///< Placeholder for user data. Passed to the user callback in @ref gptp_callback_args_t. + void const * p_extend; ///< Placeholder for user extension. +} gptp_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_gptp_api +{ + /** Open driver. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(gptp_ctrl_t * const p_ctrl, gptp_cfg_t const * const p_cfg); + + /** Close driver. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(gptp_ctrl_t * const p_ctrl); + + /** Configure gptp timer parameters. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] timer Timer index. + * @param[in] p_timer_cfg Configuration of the timer. + */ + fsp_err_t (* timerCfg)(gptp_ctrl_t * const p_ctrl, uint8_t timer, gptp_timer_cfg_t const * const p_timer_cfg); + + /** Start gptp timer. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] timer Timer index. + */ + fsp_err_t (* start)(gptp_ctrl_t * const p_ctrl, uint8_t timer); + + /** Stop gptp timer. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] timer Timer index. + */ + fsp_err_t (* stop)(gptp_ctrl_t * const p_ctrl, uint8_t timer); + + /** Get the current time value to gptp timer. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] timer Timer index. + * @param[out] p_timer_value Pointer to timer value structure. + */ + fsp_err_t (* timerValueGet)(gptp_ctrl_t * const p_ctrl, uint8_t timer, gptp_timer_value_t * const p_timer_value); + + /** Set time offset correction to gptp timer. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] timer Timer index. + * @param[in] offset Time offset value. + */ + fsp_err_t (* timerOffsetSet)(gptp_ctrl_t * const p_ctrl, uint8_t timer, int64_t offset); + + /** Set clock rate correction to gptp timer. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] timer Timer index. + * @param[in] rate Clock rate value. + */ + fsp_err_t (* timerRateSet)(gptp_ctrl_t * const p_ctrl, uint8_t timer, uint32_t rate); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_callback Callback function. + * @param[in] p_context Pointer to send to callback function. + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(gptp_ctrl_t * const p_ctrl, void (* p_callback)(gptp_callback_args_t *), + void * const p_context, gptp_callback_args_t * const p_callback_memory); +} gptp_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_gptp_instance +{ + gptp_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + gptp_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + gptp_api_t const * p_api; ///< Pointer to the API structure for this instance +} gptp_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup GPTP_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_GPTP_API_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2c_master_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2c_master_api.h new file mode 100644 index 0000000000..ebb709596c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2c_master_api.h @@ -0,0 +1,198 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_I2C_MASTER_API_H +#define R_I2C_MASTER_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup I2C_MASTER_API I2C Master Interface + * @brief Interface for I2C master communication. + * + * @section I2C_MASTER_API_SUMMARY Summary + * The I2C master interface provides a common API for I2C HAL drivers. The I2C master interface supports: + * - Interrupt driven transmit/receive processing + * - Callback function support which can return an event code + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Communication speed options */ +typedef enum e_i2c_master_rate +{ + I2C_MASTER_RATE_STANDARD = 100000, ///< 100 kHz + I2C_MASTER_RATE_FAST = 400000, ///< 400 kHz + I2C_MASTER_RATE_FASTPLUS = 1000000, ///< 1 MHz + I2C_MASTER_RATE_HIGHSPEED = 3400000 ///< 3.4 MHz +} i2c_master_rate_t; + +/** Addressing mode options */ +typedef enum e_i2c_master_addr_mode +{ + I2C_MASTER_ADDR_MODE_7BIT = 1, ///< Use 7-bit addressing mode + I2C_MASTER_ADDR_MODE_10BIT = 2, ///< Use 10-bit addressing mode +} i2c_master_addr_mode_t; + +/** Callback events */ +typedef enum e_i2c_master_event +{ + I2C_MASTER_EVENT_ABORTED = 1, ///< A transfer was aborted + I2C_MASTER_EVENT_RX_COMPLETE = 2, ///< A receive operation was completed successfully + I2C_MASTER_EVENT_TX_COMPLETE = 3, ///< A transmit operation was completed successfully + I2C_MASTER_EVENT_START = 4, ///< I2C sent a start condition + I2C_MASTER_EVENT_BYTE_ACK = 5, ///< I2C finished sending/receiving 1 data byte +} i2c_master_event_t; + +/** I2C callback parameter definition */ +typedef struct st_i2c_master_callback_args +{ + void * p_context; ///< Pointer to user-provided context + i2c_master_event_t event; ///< Event code +} i2c_master_callback_args_t; + +/** I2C status indicators */ +typedef struct st_i2c_master_status +{ + bool open; ///< True if driver is open +} i2c_master_status_t; + +/** I2C configuration block */ +typedef struct st_i2c_master_cfg +{ + /** Generic configuration */ + uint8_t channel; ///< Identifier recognizable by implementation + i2c_master_rate_t rate; ///< Device's maximum clock rate from enum i2c_rate_t + uint32_t slave; ///< The address of the slave device + i2c_master_addr_mode_t addr_mode; ///< Indicates how slave fields should be interpreted + uint8_t ipl; ///< Interrupt priority level. Same for RXI, TXI, TEI and ERI. + IRQn_Type rxi_irq; ///< Receive IRQ number + IRQn_Type txi_irq; ///< Transmit IRQ number + IRQn_Type tei_irq; ///< Transmit end IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + + /** Transfer API support */ + transfer_instance_t const * p_transfer_tx; ///< Transfer instance for I2C transmit. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< Transfer instance for I2C receive. Set to NULL if unused. + + /** Parameters to control software behavior */ + void (* p_callback)(i2c_master_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< Pointer to the user-provided context + + /** Implementation-specific configuration */ + void const * p_extend; ///< Any configuration data needed by the hardware +} i2c_master_cfg_t; + +/** I2C control block. Allocate an instance specific control block to pass into the I2C API calls. + */ +typedef void i2c_master_ctrl_t; + +/** Interface definition for I2C access as master */ +typedef struct st_i2c_master_api +{ + /** Opens the I2C Master driver and initializes the hardware. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements are set here. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(i2c_master_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg); + + /** Performs a read operation on an I2C Master device. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + * @param[in] p_dest Pointer to the location to store read data. + * @param[in] bytes Number of bytes to read. + * @param[in] restart Specify if the restart condition should be issued after reading. + */ + fsp_err_t (* read)(i2c_master_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes, + bool const restart); + + /** Performs a write operation on an I2C Master device. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + * @param[in] p_src Pointer to the location to get write data from. + * @param[in] bytes Number of bytes to write. + * @param[in] restart Specify if the restart condition should be issued after writing. + */ + fsp_err_t (* write)(i2c_master_ctrl_t * const p_ctrl, uint8_t * const p_src, uint32_t const bytes, + bool const restart); + + /** Performs a reset of the peripheral. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + */ + fsp_err_t (* abort)(i2c_master_ctrl_t * const p_ctrl); + + /** Sets address of the slave device without reconfiguring the bus. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + * @param[in] slave_address Address of the slave device. + * @param[in] address_mode Addressing mode. + */ + fsp_err_t (* slaveAddressSet)(i2c_master_ctrl_t * const p_ctrl, uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the IIC Master control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2c_master_ctrl_t * const p_ctrl, void (* p_callback)(i2c_master_callback_args_t *), + void * const p_context, i2c_master_callback_args_t * const p_callback_memory); + + /** Gets the status of the configured I2C device. + * + * @param[in] p_ctrl Pointer to the IIC Master control block. + * @param[out] p_status Pointer to store current status. + */ + fsp_err_t (* statusGet)(i2c_master_ctrl_t * const p_ctrl, i2c_master_status_t * p_status); + + /** Closes the driver and releases the I2C Master device. + * + * @param[in] p_ctrl Pointer to control block set in i2c_master_api_t::open call. + */ + fsp_err_t (* close)(i2c_master_ctrl_t * const p_ctrl); +} i2c_master_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_i2c_master_instance +{ + i2c_master_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + i2c_master_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + i2c_master_api_t const * p_api; ///< Pointer to the API structure for this instance +} i2c_master_instance_t; + +/******************************************************************************************************************//** + * @} (end defgroup I2C_MASTER_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2c_slave_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2c_slave_api.h new file mode 100644 index 0000000000..86d52600bb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2c_slave_api.h @@ -0,0 +1,174 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_I2C_SLAVE_API_H +#define R_I2C_SLAVE_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup I2C_SLAVE_API I2C Slave Interface + * @brief Interface for I2C slave communication. + * + * @section I2C_SLAVE_API_SUMMARY Summary + * The I2C slave interface provides a common API for I2C HAL drivers. The I2C slave interface supports: + * - Interrupt driven transmit/receive processing + * - Callback function support which returns a event codes + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Communication speed options */ +typedef enum e_i2c_slave_rate +{ + I2C_SLAVE_RATE_STANDARD = 100000, ///< 100 kHz + I2C_SLAVE_RATE_FAST = 400000, ///< 400 kHz + I2C_SLAVE_RATE_FASTPLUS = 1000000, ///< 1 MHz + I2C_SLAVE_RATE_HIGHSPEED = 3400000 ///< 3.4 MHz +} i2c_slave_rate_t; + +/** Addressing mode options */ +typedef enum e_i2c_slave_addr_mode +{ + I2C_SLAVE_ADDR_MODE_7BIT = 1, ///< Use 7-bit addressing mode + I2C_SLAVE_ADDR_MODE_10BIT ///< Use 10-bit addressing mode +} i2c_slave_addr_mode_t; + +/** Callback events */ +typedef enum e_i2c_slave_event +{ + I2C_SLAVE_EVENT_ABORTED = 1, ///< A transfer was aborted + I2C_SLAVE_EVENT_RX_COMPLETE = 2, ///< A receive operation was completed successfully + I2C_SLAVE_EVENT_TX_COMPLETE = 3, ///< A transmit operation was completed successfully + I2C_SLAVE_EVENT_RX_REQUEST = 4, ///< A read operation expected from slave. Detected a write from master + I2C_SLAVE_EVENT_TX_REQUEST = 5, ///< A write operation expected from slave. Detected a read from master + I2C_SLAVE_EVENT_RX_MORE_REQUEST = 6, ///< A read operation expected from slave. Master sends out more data than configured to be read in slave. + I2C_SLAVE_EVENT_TX_MORE_REQUEST = 7, ///< A write operation expected from slave. Master requests more data than configured to be written by slave. + I2C_SLAVE_EVENT_GENERAL_CALL = 8, ///< General Call address received from Master. Detected a write from master +} i2c_slave_event_t; + +/** I2C callback parameter definition */ +typedef struct st_i2c_slave_callback_args +{ + void * p_context; ///< Pointer to user-provided context + uint32_t bytes; ///< Number of received/transmitted bytes in buffer + i2c_slave_event_t event; ///< Event code +} i2c_slave_callback_args_t; + +/** I2C configuration block */ +typedef struct st_i2c_slave_cfg +{ + /** Generic configuration */ + uint8_t channel; ///< Identifier recognizable by implementation + i2c_slave_rate_t rate; ///< Device's maximum clock rate from enum i2c_rate_t + uint16_t slave; ///< The address of the slave device + i2c_slave_addr_mode_t addr_mode; ///< Indicates how slave fields should be interpreted + bool general_call_enable; ///< Allow a General call from master + + IRQn_Type rxi_irq; ///< Receive IRQ number + IRQn_Type txi_irq; ///< Transmit IRQ number + IRQn_Type tei_irq; ///< Transmit end IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + uint8_t ipl; ///< Interrupt priority level for receive, transmit, and transmit end interrupts + uint8_t eri_ipl; ///< Interrupt priority level for error interrupt + bool clock_stretching_enable; ///< Low Hold SCL during reception for the period between the 9th and the 1st clock cycle + + /** Transfer API support */ + transfer_instance_t const * p_transfer_tx; ///< Transfer instance for I2C transmit. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< Transfer instance for I2C receive. Set to NULL if unused. + + /** Parameters to control software behavior */ + void (* p_callback)(i2c_slave_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< Pointer to the user-provided context + + /** Implementation-specific configuration */ + void const * p_extend; ///< Any configuration data needed by the hardware +} i2c_slave_cfg_t; + +/** I2C control block. Allocate an instance specific control block to pass into the I2C API calls. + */ +typedef void i2c_slave_ctrl_t; + +/** Interface definition for I2C access as slave */ +typedef struct st_i2c_slave_api +{ + /** Opens the I2C Slave driver and initializes the hardware. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements are set here. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(i2c_slave_ctrl_t * const p_ctrl, i2c_slave_cfg_t const * const p_cfg); + + /** Performs a read operation on an I2C Slave device. + * + * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. + * @param[in] p_dest Pointer to the location to store read data. + * @param[in] bytes Number of bytes to read. + */ + fsp_err_t (* read)(i2c_slave_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Performs a write operation on an I2C Slave device. + * + * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. + * @param[in] p_src Pointer to the location to get write data from. + * @param[in] bytes Number of bytes to write. + */ + fsp_err_t (* write)(i2c_slave_ctrl_t * const p_ctrl, uint8_t * const p_src, uint32_t const bytes); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the IIC Slave control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2c_slave_ctrl_t * const p_ctrl, void (* p_callback)(i2c_slave_callback_args_t *), + void * const p_context, i2c_slave_callback_args_t * const p_callback_memory); + + /** Closes the driver and releases the I2C Slave device. + * + * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. + */ + fsp_err_t (* close)(i2c_slave_ctrl_t * const p_ctrl); +} i2c_slave_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_i2c_slave_instance +{ + i2c_slave_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + i2c_slave_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + i2c_slave_api_t const * p_api; ///< Pointer to the API structure for this instance +} i2c_slave_instance_t; + +/******************************************************************************************************************//** + * @} (end defgroup I2C_SLAVE_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2s_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2s_api.h new file mode 100644 index 0000000000..a0b48cb1e4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i2s_api.h @@ -0,0 +1,259 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup I2S_API I2S Interface + * @brief Interface for I2S audio communication. + * + * @section I2S_API_SUMMARY Summary + * @brief The I2S (Inter-IC Sound) interface provides APIs and definitions for I2S audio communication. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_I2S_API_H +#define R_I2S_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#ifndef BSP_OVERRIDE_I2S_INCLUDE + #include "r_timer_api.h" +#endif +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_I2S_PCM_WIDTH_T + +/** Audio PCM width */ +typedef enum e_i2s_pcm_width +{ + I2S_PCM_WIDTH_8_BITS = 0, ///< Using 8-bit PCM + I2S_PCM_WIDTH_16_BITS = 1, ///< Using 16-bit PCM + I2S_PCM_WIDTH_18_BITS = 2, ///< Using 18-bit PCM + I2S_PCM_WIDTH_20_BITS = 3, ///< Using 20-bit PCM + I2S_PCM_WIDTH_22_BITS = 4, ///< Using 22-bit PCM + I2S_PCM_WIDTH_24_BITS = 5, ///< Using 24-bit PCM + I2S_PCM_WIDTH_32_BITS = 6, ///< Using 32-bit PCM +} i2s_pcm_width_t; +#endif + +#ifndef BSP_OVERRIDE_I2S_WORD_LENGTH_T + +/** Audio system word length. */ +typedef enum e_i2s_word_length +{ + I2S_WORD_LENGTH_8_BITS = 0, ///< Using 8-bit system word length + I2S_WORD_LENGTH_16_BITS = 1, ///< Using 16-bit system word length + I2S_WORD_LENGTH_24_BITS = 2, ///< Using 24-bit system word length + I2S_WORD_LENGTH_32_BITS = 3, ///< Using 32-bit system word length + I2S_WORD_LENGTH_48_BITS = 4, ///< Using 48-bit system word length + I2S_WORD_LENGTH_64_BITS = 5, ///< Using 64-bit system word length + I2S_WORD_LENGTH_128_BITS = 6, ///< Using 128-bit system word length + I2S_WORD_LENGTH_256_BITS = 7, ///< Using 256-bit system word length +} i2s_word_length_t; +#endif + +/** Events that can trigger a callback function */ +typedef enum e_i2s_event +{ + I2S_EVENT_IDLE, ///< Communication is idle + I2S_EVENT_TX_EMPTY, ///< Transmit buffer is below FIFO trigger level + I2S_EVENT_RX_FULL, ///< Receive buffer is above FIFO trigger level +} i2s_event_t; + +#ifndef BSP_OVERRIDE_I2S_MODE_T + +/** I2S communication mode */ +typedef enum e_i2s_mode +{ + I2S_MODE_SLAVE = 0, ///< Slave mode + I2S_MODE_MASTER = 1, ///< Master mode +} i2s_mode_t; +#endif + +/** Mute audio samples. */ +typedef enum e_i2s_mute +{ + I2S_MUTE_OFF = 0, ///< Disable mute + I2S_MUTE_ON = 1, ///< Enable mute +} i2s_mute_t; + +/** Whether to continue WS (word select line) transmission during idle state. */ +typedef enum e_i2s_ws_continue +{ + I2S_WS_CONTINUE_ON = 0, ///< Enable WS continue mode + I2S_WS_CONTINUE_OFF = 1, ///< Disable WS continue mode +} i2s_ws_continue_t; + +/** Possible status values returned by @ref i2s_api_t::statusGet. */ +typedef enum e_i2s_state +{ + I2S_STATE_IN_USE, ///< I2S is in use + I2S_STATE_STOPPED ///< I2S is stopped +} i2s_state_t; + +/** Callback function parameter data */ +typedef struct st_i2s_callback_args +{ + /** Placeholder for user data. Set in @ref i2s_api_t::open function in @ref i2s_cfg_t. */ + void * p_context; + i2s_event_t event; ///< The event can be used to identify what caused the callback (overflow or error). +} i2s_callback_args_t; + +/** I2S control block. Allocate an instance specific control block to pass into the I2S API calls. + */ +typedef void i2s_ctrl_t; + +/** I2S status. */ +typedef struct st_i2s_status +{ + i2s_state_t state; ///< Current I2S state +} i2s_status_t; + +/** User configuration structure, used in open function */ +typedef struct st_i2s_cfg +{ + /** Select a channel corresponding to the channel number of the hardware. */ + uint32_t channel; + i2s_pcm_width_t pcm_width; ///< Audio PCM data width + i2s_word_length_t word_length; ///< Audio word length, bits must be >= i2s_cfg_t::pcm_width bits + i2s_ws_continue_t ws_continue; ///< Whether to continue WS transmission during idle state. + i2s_mode_t operating_mode; ///< Master or slave mode + + /** To use DMA for transmitting link a Transfer instance here. Set to NULL if unused. */ + transfer_instance_t const * p_transfer_tx; + + /** To use DMA for receiving link a Transfer instance here. Set to NULL if unused. */ + transfer_instance_t const * p_transfer_rx; + + /** Callback provided when an I2S ISR occurs. Set to NULL for no CPU interrupt. */ + void (* p_callback)(i2s_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref i2s_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. + uint8_t rxi_ipl; ///< Receive interrupt priority + uint8_t txi_ipl; ///< Transmit interrupt priority + uint8_t idle_err_ipl; ///< Idle/Error interrupt priority + IRQn_Type txi_irq; ///< Transmit IRQ number + IRQn_Type rxi_irq; ///< Receive IRQ number + IRQn_Type int_irq; ///< Idle/Error IRQ number +} i2s_cfg_t; + +/** I2S functions implemented at the HAL layer will follow this API. */ +typedef struct st_i2s_api +{ + /** Initial configuration. + * + * @pre Peripheral clocks and any required output pins should be configured prior to calling this function. + * @note To reconfigure after calling this function, call @ref i2s_api_t::close first. + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(i2s_ctrl_t * const p_ctrl, i2s_cfg_t const * const p_cfg); + + /** Stop communication. Communication is stopped when callback is called with I2S_EVENT_IDLE. + * + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + */ + fsp_err_t (* stop)(i2s_ctrl_t * const p_ctrl); + + /** Enable or disable mute. + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[in] mute_enable Whether to enable or disable mute. + */ + fsp_err_t (* mute)(i2s_ctrl_t * const p_ctrl, i2s_mute_t const mute_enable); + + /** Write I2S data. All transmit data is queued when callback is called with I2S_EVENT_TX_EMPTY. + * Transmission is complete when callback is called with I2S_EVENT_IDLE. + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[in] p_src Buffer of PCM samples. Must be 4 byte aligned. + * @param[in] bytes Number of bytes in the buffer. Recommended requesting a multiple of 8 bytes. If not + * a multiple of 8, padding 0s will be added to transmission to make it a multiple of 8. + */ + fsp_err_t (* write)(i2s_ctrl_t * const p_ctrl, void const * const p_src, uint32_t const bytes); + + /** Read I2S data. Reception is complete when callback is called with I2S_EVENT_RX_EMPTY. + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[in] p_dest Buffer to store PCM samples. Must be 4 byte aligned. + * @param[in] bytes Number of bytes in the buffer. Recommended requesting a multiple of 8 bytes. If not + * a multiple of 8, receive will stop at the multiple of 8 below requested bytes. + */ + fsp_err_t (* read)(i2s_ctrl_t * const p_ctrl, void * const p_dest, uint32_t const bytes); + + /** Simultaneously write and read I2S data. Transmission and reception are complete when + * callback is called with I2S_EVENT_IDLE. + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[in] p_src Buffer of PCM samples. Must be 4 byte aligned. + * @param[in] p_dest Buffer to store PCM samples. Must be 4 byte aligned. + * @param[in] bytes Number of bytes in the buffers. Recommended requesting a multiple of 8 bytes. If not + * a multiple of 8, padding 0s will be added to transmission to make it a multiple of 8, + * and receive will stop at the multiple of 8 below requested bytes. + */ + fsp_err_t (* writeRead)(i2s_ctrl_t * const p_ctrl, void const * const p_src, void * const p_dest, + uint32_t const bytes); + + /** Get current status and store it in provided pointer p_status. + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[out] p_status Current status of the driver. + */ + fsp_err_t (* statusGet)(i2s_ctrl_t * const p_ctrl, i2s_status_t * const p_status); + + /** Allows driver to be reconfigured and may reduce power consumption. + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + */ + fsp_err_t (* close)(i2s_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the I2S control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2s_ctrl_t * const p_ctrl, void (* p_callback)(i2s_callback_args_t *), + void * const p_context, i2s_callback_args_t * const p_callback_memory); +} i2s_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_i2s_instance +{ + i2s_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + i2s_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + i2s_api_t const * p_api; ///< Pointer to the API structure for this instance +} i2s_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup I2S_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i3c_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i3c_api.h new file mode 100644 index 0000000000..d762f3de2f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_i3c_api.h @@ -0,0 +1,508 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup I3C_API I3C Interface + * @brief Interface for I3C. + * + * @section I3C_API_SUMMARY Summary + * @brief The I3C interface provides APIs and definitions for I3C communication. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_I3C_API_H +#define R_I3C_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common Command Codes defined by MIPI I3C Specification v1.1. */ +typedef enum e_i3c_common_command_code +{ + /* Broadcast Common Command Codes */ + I3C_CCC_BROADCAST_ENEC = (0x00), ///< Enable Slave initiated events. + I3C_CCC_BROADCAST_DISEC = (0x01), ///< Disable Slave initiated events. + I3C_CCC_BROADCAST_ENTAS0 = (0x02), ///< Enter Activity State 0. + I3C_CCC_BROADCAST_ENTAS1 = (0x03), ///< Enter Activity State 1. + I3C_CCC_BROADCAST_ENTAS2 = (0x04), ///< Enter Activity State 2. + I3C_CCC_BROADCAST_ENTAS3 = (0x05), ///< Enter Activity State 3. + I3C_CCC_BROADCAST_RSTDAA = (0x06), ///< Reset Dynamic Address Assignment. + I3C_CCC_BROADCAST_ENTDAA = (0x07), ///< Enter Dynamic Address Assignment. + I3C_CCC_BROADCAST_DEFSVLS = (0x08), ///< Define List of Slaves. + I3C_CCC_BROADCAST_SETMWL = (0x09), ///< Set Max Write Length. + I3C_CCC_BROADCAST_SETMRL = (0x0A), ///< Set Max Read Length. + I3C_CCC_BROADCAST_ENTTM = (0x0B), ///< Enter Test Mode. + I3C_CCC_BROADCAST_SETBUSCON = (0x0C), ///< Set BUS Context. + I3C_CCC_BROADCAST_ENDXFER = (0x12), ///< Data Transfer Ending Procedure Control. + I3C_CCC_BROADCAST_ENTHDR0 = (0x20), ///< Enter HDR Mode 0. + I3C_CCC_BROADCAST_ENTHDR1 = (0x21), ///< Enter HDR Mode 1. + I3C_CCC_BROADCAST_ENTHDR2 = (0x22), ///< Enter HDR Mode 2. + I3C_CCC_BROADCAST_ENTHDR3 = (0x23), ///< Enter HDR Mode 3. + I3C_CCC_BROADCAST_ENTHDR4 = (0x24), ///< Enter HDR Mode 4 (Reserved for future definition). + I3C_CCC_BROADCAST_ENTHDR5 = (0x25), ///< Enter HDR Mode 5 (Reserved for future definition). + I3C_CCC_BROADCAST_ENTHDR6 = (0x26), ///< Enter HDR Mode 6 (Reserved for future definition). + I3C_CCC_BROADCAST_ENTHDR7 = (0x27), ///< Enter HDR Mode 7 (Reserved for future definition). + I3C_CCC_BROADCAST_SETXTIME = (0x28), ///< Set Exchange Timing Info. + I3C_CCC_BROADCAST_SETAASA = (0x29), ///< Set All Addresses to Static Address. + I3C_CCC_BROADCAST_RSTACT = (0x2A), ///< Slave Reset Action. + I3C_CCC_BROADCAST_DEFGRPA = (0x2B), ///< Define List of Group Address. + I3C_CCC_BROADCAST_RSTGRPA = (0x2C), ///< Reset Group Address. + I3C_CCC_BROADCAST_MLANE = (0x2D), ///< Multi-Lane Data Transfer Control. + + /* Direct Common Command Codes */ + I3C_CCC_DIRECT_ENEC = (0x80), ///< Enable Slave initiated events. + I3C_CCC_DIRECT_DISEC = (0x81), ///< Disable Slave initiated events. + I3C_CCC_DIRECT_ENTAS0 = (0x82), ///< Enter Activity State 0. + I3C_CCC_DIRECT_ENTAS1 = (0x83), ///< Enter Activity State 1. + I3C_CCC_DIRECT_ENTAS2 = (0x84), ///< Enter Activity State 2. + I3C_CCC_DIRECT_ENTAS3 = (0x85), ///< Enter Activity State 3. + I3C_CCC_DIRECT_RSTDAA = (0x86), ///< Reset Dynamic Address Assignment (DEPRECATED v1.0). + I3C_CCC_DIRECT_SETDASA = (0x87), ///< Set Dynamic Address from Static Address. + I3C_CCC_DIRECT_SETNEWDA = (0x88), ///< Set New Dynamic Address. + I3C_CCC_DIRECT_SETMWL = (0x89), ///< Set Max Write Length. + I3C_CCC_DIRECT_SETMRL = (0x8A), ///< Set Max Read Length. + I3C_CCC_DIRECT_GETMWL = (0x8B), ///< Get Max Write Length. + I3C_CCC_DIRECT_GETMRL = (0x8C), ///< Get Max Read Length. + I3C_CCC_DIRECT_GETPID = (0x8D), ///< Get Provisional ID. + I3C_CCC_DIRECT_GETBCR = (0x8E), ///< Get Bus Characteristic Register. + I3C_CCC_DIRECT_GETDCR = (0x8F), ///< Get Device Characteristic Register. + I3C_CCC_DIRECT_GETSTATUS = (0x90), ///< Get Device Status. + I3C_CCC_DIRECT_GETACCMST = (0x91), ///< Get Accept Mastership. + I3C_CCC_DIRECT_ENDXFER = (0x92), ///< Data Transfer Ending Procedure Control. + I3C_CCC_DIRECT_SETBRGTGT = (0x93), ///< Set Bridge Targets. + I3C_CCC_DIRECT_GETMXDS = (0x94), ///< Get Max Data Speed. + I3C_CCC_DIRECT_GETHDRCAP = (0x95), ///< Get HDR Capability. + I3C_CCC_DIRECT_SETROUTE = (0x96), ///< Set Route. + I3C_CCC_DIRECT_D2DXFER = (0x97), ///< Device to Device(s) Tunneling Control. + I3C_CCC_DIRECT_SETXTIME = (0x98), ///< Set Exchange Timing Information. + I3C_CCC_DIRECT_GETXTIME = (0x99), ///< Get Exchange Timing Information. + I3C_CCC_DIRECT_RSTACT = (0x9A), ///< Reset Slave Action. + I3C_CCC_DIRECT_SETGRPA = (0x9B), ///< Set Group Address. + I3C_CCC_DIRECT_RSTGRPA = (0x9C), ///< Reset Group Address. + I3C_CCC_DIRECT_MLANE = (0x9D), ///< Multi-Lane Data Transfer Control. +} i3c_common_command_code_t; + +/** I3C Events that result in a callback. */ +typedef enum e_i3c_event +{ + /** Events that only occur in Master mode. */ + + /** + * A Slave device has finished writing its PID, BCR, and DCR. This information is provided in + * @ref i3c_callback_args_t::p_slave_info. + */ + I3C_EVENT_ENTDAA_ADDRESS_PHASE, + I3C_EVENT_IBI_READ_COMPLETE, ///< An IBI has successfully been read. + + /** + * There is no more space in the IBI read buffer. The application may provide another buffer by calling + * @ref i3c_api_t::ibiRead. + */ + I3C_EVENT_IBI_READ_BUFFER_FULL, + + /** Events that only occur in Slave mode. */ + + /** + * There is no more space in the read buffer. The application may provide another buffer by calling + * @ref i3c_api_t::read. + */ + I3C_EVENT_READ_BUFFER_FULL, + I3C_EVENT_IBI_WRITE_COMPLETE, ///< A IBI was written successfully. + I3C_EVENT_HDR_EXIT_PATTERN_DETECTED, ///< The HDR exit pattern was detected on the bus. + + /** Events that are common to Master and Slave mode. */ + + I3C_EVENT_ADDRESS_ASSIGNMENT_COMPLETE, ///< Dynamic Address Assignment has completed. + I3C_EVENT_COMMAND_COMPLETE, ///< A command was completed. + I3C_EVENT_WRITE_COMPLETE, ///< A write transfer has completed. + I3C_EVENT_READ_COMPLETE, ///< A read transfer has completed. + I3C_EVENT_TIMEOUT_DETECTED, ///< SCL is stuck at the logic high or logic low level during a transfer. + I3C_EVENT_INTERNAL_ERROR, ///< An internal error occurred. + I3C_EVENT_SDA_WRITE_COMPLETE, ///< An SDA (Short Data Argument) write transfer has completed. +} i3c_event_t; + +/** The type of device. */ +typedef enum e_i3c_type +{ + /** The main master starts in master mode and is responsible for configuring the bus. */ + I3C_DEVICE_TYPE_MAIN_MASTER, + + /** A slave device listens to the bus for relevant I3C Commands (CCCs) sent by the current master, and responds accordingly. + * Slave devices may also initiate In-band interrupts and Hot-Join requests. */ + I3C_DEVICE_TYPE_SLAVE, +} i3c_device_type_t; + +/** Identifies the protocol for transferring data with the device on the bus. */ +typedef enum e_i3c_device_protocol +{ + I3C_DEVICE_PROTOCOL_I2C, ///< Transfers will use legacy I2C protocol with open-drain output at a reduced baudrate. + I3C_DEVICE_PROTOCOL_I3C, ///< Transfers will use I3C SDR mode. +} i3c_device_protocol_t; + +/** Address Assignment Mode. */ +typedef enum e_i3c_address_assignment_mode +{ + /** + * Send the ENTDAA command to enter Dynamic Address Assignment mode and assign dynamic addresses in order, starting with the + * starting device index. The procedure is completed after the specified number of devices have been configured. The callback will + * be called after the PID, DCR, and BCR registers have been read for each device. + */ + I3C_ADDRESS_ASSIGNMENT_MODE_ENTDAA = I3C_CCC_BROADCAST_ENTDAA, + + /* Send the SETDASA command to the device selected by the starting device index (Set the device count to 0). */ + I3C_ADDRESS_ASSIGNMENT_MODE_SETDASA = I3C_CCC_DIRECT_SETDASA, +} i3c_address_assignment_mode_t; + +/** The type of In-Band Interrupt. */ +typedef enum e_i3c_ibi_type +{ + I3C_IBI_TYPE_INTERRUPT, ///< Application specific In-Band Interrupt for notifying the master when an event occurs. + I3C_IBI_TYPE_HOT_JOIN, ///< Request the master to perform the Dynamic Address Assignment process. + I3C_IBI_TYPE_MASTERSHIP_REQUEST ///< Request the master to give up control of the bus. +} i3c_ibi_type_t; + +/** The current status of the slave device (See GETSTATUS in the MIPI I3C Specification v1.0). */ +typedef struct s_i3c_device_status +{ + uint8_t pending_interrupt; ///< Contains the interrupt number of any pending interrupt, or 0 if no interrupts are pending. + uint8_t vendor_status; ///< Reserved for vendor-specific meaning. +} i3c_device_status_t; + +/** Device characteristics that define the I3C capabilities of a slave. */ +typedef struct s_i3c_slave_info +{ + uint8_t pid[6]; ///< Provisional ID. + + union + { + uint8_t bcr; ///< Bus Characteristics Register. + + struct + { + /** + * Max Data Speed Limitation: + * - No limitation. + * - Limitation (If this is set, the master shall get the Max Data Speed using the GETMXDS command). + */ + uint8_t max_data_speed_limitation : 1; + + /** + * IBI Request Capable + * - 0: Not Capable. + * - 1: Capable. + */ + uint8_t ibi_request_capable : 1; + + /** + * IBI Payload: + * - 0: No data byte follows the accepted IBI + * - 1: Mandatory one or more data bytes follow the accepted IBI. + */ + uint8_t ibi_payload : 1; + + /** + * Offline Capable: + * - 0: Not Capable. + * - 1: Capable. + */ + uint8_t offline_capable : 1; + + /** + * Bridge Identifier: + * - 0: Not a Bridge Device. + * - 1: Is a Bridge Device. + */ + uint8_t bridge_identifier : 1; + + /** + * HDR Capable: + * - 0: Not Capable. + * - 1: Capable. + */ + uint8_t hdr_capable : 1; + + /** + * Device Role: + * - 0: I3C Slave. + * - 1: I3C Master (Device acting as the main master will set this to 1). + * - 2: Reserved. + * - 3: Reserved. + */ + uint8_t device_role : 2; + } bcr_b; + }; + + uint8_t dcr; ///< Device Characteristics Register. +} i3c_slave_info_t; + +/** + * Structure for configuring an entry in the device table when the driver is in master mode + * (See @ref i3c_api_t::masterDeviceTableSet). + */ +typedef struct s_i3c_device_table_cfg +{ + uint8_t static_address; ///< I3C Static address / I2C address for this device. + + /** Dynamic address for the device. This address will be assigned during Dynamic Address Assignment. */ + uint8_t dynamic_address; + + i3c_device_protocol_t device_protocol; ///< The protocol used to communicate with this device (I3C / I2C Legacy). + bool ibi_accept; ///< Accept or reject IBI requests from this device. + bool master_request_accept; ///< Accept mastership requests from this device. + + /** + * IBI requests from this device have a data payload. + * + * Note: When the device is configured using ENTDAA, the ibi_payload will automatically be updated + * based on the value of BCR. + */ + bool ibi_payload; +} i3c_device_table_cfg_t; + +/** Structure for configuring a slave address when the driver is in slave mode (See @ref i3c_api_t::deviceCfgSet). */ +typedef struct s_i3c_slave_device_cfg +{ + uint8_t static_address; ///< I3C Static address / I2C address for this device. + + /** Dynamic address for this device. Note that the dynamic address will automatically be updated when ENTDAA is + * completed.*/ + uint8_t dynamic_address; + + i3c_slave_info_t slave_info; ///< PID, BCR, and DCR registers for the device (Slave mode only). +} i3c_device_cfg_t; + +/** Descriptor for completing CCC/HDR transfers. */ +typedef struct s_i3c_command_descriptor +{ + uint8_t command_code; ///< Common Command Code / HDR Command Code for the transfer. + uint8_t * p_buffer; ///< Buffer for reading or writing data. + uint32_t length; ///< Length of the data portion of the command. + bool restart; ///< If true, issue a repeated-start after the transfer is completed. + bool rnw; ///< Set to true if the command type is Direct Get. +} i3c_command_descriptor_t; + +/** Arguments that are passed to the user callback when an event occurs. */ +typedef struct s_i3c_callback_args +{ + i3c_event_t event; ///< The type of event that has occurred. + uint32_t event_status; ///< Status flags associated with the event. + uint32_t transfer_size; ///< Number of bytes transferred. + i3c_slave_info_t const * p_slave_info; ///< A pointer to the Characteristics Registers read during ENTDAA. + uint8_t dynamic_address; ///< The dynamic address that was assigned to the slave during ENTDAA. + i3c_ibi_type_t ibi_type; ///< The type of IBI that has been received. + uint8_t ibi_address; ///< The address of the device that sent the IBI. + uint8_t command_code; ///< The command code of the received command. + void * p_context; ///< User defined context. +} i3c_callback_args_t; + +/** User configuration structure, used in open function */ +typedef struct st_i3c_cfg +{ + /** Select a channel corresponding to the channel number of the hardware. */ + uint32_t channel; + + /** The type of device. */ + i3c_device_type_t device_type; + + /** Transfer API support. */ + transfer_instance_t const * p_transfer_tx; ///< Transfer instance for I3C transmit. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< Transfer instance for I3C receive. Set to NULL if unused. + + /** Pointer to the user callback. */ + void (* p_callback)(i3c_callback_args_t const * const p_args); + + void * p_context; ///< Pointer to the user-provided context + + /** Pointer to extended configuration. */ + void const * p_extend; +} i3c_cfg_t; + +/** I3C control block. Allocate an instance specific control block to pass into the I3C API calls. + */ +typedef void i3c_ctrl_t; + +/** I3C functions implemented at the HAL layer will follow this API. */ +typedef struct st_i3c_api +{ + /** Initial configuration. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(i3c_ctrl_t * const p_ctrl, i3c_cfg_t const * const p_cfg); + + /** + * Enable the I3C device. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + */ + fsp_err_t (* enable)(i3c_ctrl_t * const p_ctrl); + + /** + * Set the configuration of this device. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] p_device_cfg Pointer to device configuration. + */ + fsp_err_t (* deviceCfgSet)(i3c_ctrl_t * const p_ctrl, i3c_device_cfg_t const * const p_device_cfg); + + /** + * Set the configuration for the device at the given index in the device table. The configuration will be used by transfers + * when it is selected by @ref deviceSelect. + * + * Note: This function is not used in slave mode. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] device_index Index into the device table. + * @param[in] p_device_table_cfg Pointer to the table settings for the entry in the master device table. + */ + fsp_err_t (* masterDeviceTableSet)(i3c_ctrl_t * const p_ctrl, uint32_t device_index, + i3c_device_table_cfg_t const * const p_device_table_cfg); + + /** + * In master mode, select the device for the next transfer. + * + * Note: This function is not used in slave mode. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] device_index Index into the device table. + * @param[in] bitrate_setting The bitrate settings for the selected device. + */ + fsp_err_t (* deviceSelect)(i3c_ctrl_t * const p_ctrl, uint32_t device_index, uint32_t bitrate_mode); + + /** Start Dynamic Address Assignment by sending either the ENTDAA or SETDASA command See @ref i3c_address_assignment_mode_t + * for more information. + * + * Note: This function is not used in slave mode. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] address_assignment_mode The command to use for Dynamic Address Assignment. + * @param[in] starting_device_index The device index that will be used to assign the first device during Dynamic Address Assignment. + * @param[in] device_count The number of devices to assign (Only used with @ref I3C_ADDRESS_ASSIGNMENT_MODE_ENTDAA). + */ + fsp_err_t (* dynamicAddressAssignmentStart)(i3c_ctrl_t * const p_ctrl, + i3c_address_assignment_mode_t address_assignment_mode, + uint32_t starting_device_index, uint32_t device_count); + + /** + * Set the status returned to the master in response to a GETSTATUS command. + * + * Note: This function is not used in master mode. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] device_status New status settings for responding to the GETSTATUS command code. + */ + fsp_err_t (* slaveStatusSet)(i3c_ctrl_t * const p_ctrl, i3c_device_status_t device_status); + + /** + * Send a read/write/broadcast CCC or HDR command. + * + * Note: This function is not used in slave mode. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] p_command_descriptor A descriptor for executing the command. + */ + fsp_err_t (* commandSend)(i3c_ctrl_t * const p_ctrl, i3c_command_descriptor_t const * const p_command_descriptor); + + /** + * In master mode: Start a write transfer. When the transfer is completed send a stop condition or a repeated-start. + * In slave mode: Set the write buffer and configure the number of bytes that will be transferred before the the transfer + * is ended by the slave via the 'T' bit or by the master issuing a stop condition. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] p_data Pointer to a buffer to write. + * @param[in] length Number of bytes to transfer. + * @param[in] restart If true, issue a repeated-start after the transfer is completed (Master only). + */ + fsp_err_t (* write)(i3c_ctrl_t * const p_ctrl, uint8_t const * const p_data, uint32_t length, bool restart); + + /** + * In master mode: Start a read transfer. When the transfer is completed, send a stop condition or a repeated-start. + * In slave mode: Set the read buffer for storing data read during the transfer. When the buffer is full, the application + * will receive a callback requesting a new read buffer. If no buffer is provided by the application, the driver will + * discard any remaining bytes read during the transfer. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] p_data Pointer to a buffer to store the bytes read during the transfer. + * @param[in] length Number of bytes to transfer. + * @param[in] restart If true, issue a repeated-start after the transfer is completed (Master only). + */ + fsp_err_t (* read)(i3c_ctrl_t * const p_ctrl, uint8_t * const p_data, uint32_t length, bool restart); + + /** + * Initiate an IBI write operation. + * + * Note: This function is not used in master mode. + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] ibi_type The type of In-Band Interrupt. + * @param[in] p_data Pointer to a buffer to start the bytes read during the transfer. + * @param[in] length Number of bytes to transfer. + */ + fsp_err_t (* ibiWrite)(i3c_ctrl_t * const p_ctrl, i3c_ibi_type_t ibi_type, uint8_t const * const p_data, + uint32_t length); + + /** + * Set the read buffer for storing received IBI data (This function is not used in slave mode). + * + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + * @param[in] p_data Pointer to a buffer to store the bytes read during the transfer. + * @param[in] length Number of bytes to transfer. + */ + fsp_err_t (* ibiRead)(i3c_ctrl_t * const p_ctrl, uint8_t * const p_data, uint32_t length); + + /** Allows driver to be reconfigured and may reduce power consumption. + * + * @param[in] p_ctrl Control block set in @ref i3c_api_t::open call for this instance. + */ + fsp_err_t (* close)(i3c_ctrl_t * const p_ctrl); +} i3c_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_i3c_instance +{ + i3c_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + i3c_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + i3c_api_t const * p_api; ///< Pointer to the API structure for this instance +} i3c_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup I3C_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_iir_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_iir_api.h new file mode 100644 index 0000000000..2a4ccc8fb6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_iir_api.h @@ -0,0 +1,140 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_DSP_INTERFACES + * @defgroup IIR_API IIR Interface + * @brief Interface for IIR filter functionality. + * + * @section IIR_API_SUMMARY Summary + * The IIR interface allows access to the IIRFA peripheral for hardware acceleration of direct form 2 + * transposed biquad IIR filters. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IIR_API_H +#define R_IIR_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Filter stage coefficient data */ +typedef struct st_iir_filter_coeffs +{ + float b0; ///< Coefficient B0 + float b1; ///< Coefficient B1 + float b2; ///< Coefficient B2 + float a1; ///< Coefficient A0 + float a2; ///< Coefficient A1 +} iir_filter_coeffs_t; + +/** Filter stage state data */ +typedef struct st_iir_filter_state +{ + float d0; ///< State variable D0 + float d1; ///< State variable D1 +} iir_filter_state_t; + +/** Filter configuration */ +typedef struct st_iir_filter_cfg +{ + iir_filter_coeffs_t * p_filter_coeffs; ///< Filter coefficients + iir_filter_state_t * p_filter_state; ///< Filter state data + uint8_t stage_base; ///< Hardware stage to start from + uint8_t stage_num; ///< Number of filter stages to use +} iir_filter_cfg_t; + +/** Filter state register status */ +typedef struct st_iir_status +{ + iir_filter_state_t * p_filter_state; +} iir_status_t; + +/** IIRFA API configuration parameter */ +typedef struct st_iir_cfg +{ + void const * p_extend; + uint8_t channel; ///< IIRFA channel to use +} iir_cfg_t; + +/** IIR control block. Allocate an instance specific control block to pass into the DAC API calls. + */ +typedef void iir_ctrl_t; + +/** IIR driver structure. IIR functions implemented at the HAL layer follow this API. */ +typedef struct st_iir_api +{ + /** Initial configuration. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(iir_ctrl_t * const p_ctrl, iir_cfg_t const * const p_cfg); + + /** Close the IIRFA channel. + * + * @param[in] p_ctrl Control block set in @ref iir_api_t::open. + */ + fsp_err_t (* close)(iir_ctrl_t * const p_ctrl); + + /** Configure filter coefficients and state variables. + * + * @param[in] p_ctrl Control block set in @ref iir_api_t::open. + * @param[in] p_filter_cfg Pointer to filter configuration to write. + */ + fsp_err_t (* configure)(iir_ctrl_t * const p_ctrl, iir_filter_cfg_t const * const p_filter_cfg); + + /** Filter the specified data. + * + * @param[in] p_ctrl Control block set in @ref iir_api_t::open. + * @param[in] p_data_in Pointer to float input data. + * @param[in] p_data_out Pointer to float output buffer. + * @param[in] num_samples Number of samples to process. + */ + fsp_err_t (* filter)(iir_ctrl_t * const p_ctrl, float const * p_data_in, float * p_data_out, + uint16_t const num_samples); + + /** Retrieve current status (including state registers). + * + * @param[in] p_ctrl Control block set in @ref iir_api_t::open. + * @param[in] p_status Pointer to status struct. + */ + fsp_err_t (* statusGet)(iir_ctrl_t * const p_ctrl, iir_status_t * const p_status); +} iir_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_iirfa_instance +{ + iir_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + iir_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + iir_api_t const * p_api; ///< Pointer to the API structure for this instance +} iirfa_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup DAC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ioport_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ioport_api.h new file mode 100644 index 0000000000..dcb104b06d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ioport_api.h @@ -0,0 +1,192 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SYSTEM_INTERFACES + * @defgroup IOPORT_API I/O Port Interface + * @brief Interface for accessing I/O ports and configuring I/O functionality. + * + * @section IOPORT_API_SUMMARY Summary + * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. + * Port and pin direction can be changed. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_API_H +#define R_IOPORT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_IOPORT_SIZE_T + +/** IO port type used with ports */ +typedef uint16_t ioport_size_t; ///< IO port size +#endif + +/** Pin identifier and pin configuration value */ +typedef struct st_ioport_pin_cfg +{ + uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure + bsp_io_port_pin_t pin; ///< Pin identifier +} ioport_pin_cfg_t; + +/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ +typedef struct st_ioport_cfg +{ + uint16_t number_of_pins; ///< Number of pins for which there is configuration data + ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data + const void * p_extend; ///< Pointer to hardware extend configuration +} ioport_cfg_t; + +/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. + */ +typedef void ioport_ctrl_t; + +/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ +typedef struct st_ioport_api +{ + /** Initialize internal driver data and initial pin configurations. Called during startup. Do + * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of + * multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Close the API. + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); + + /** Configure multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Configure settings for an individual pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] cfg Configuration options for the pin. + */ + fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + + /** Read the event input data of the specified pin and return the level. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_event Pointer to return the event data. + */ + fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); + + /** Write pin event data. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin event data is to be written to. + * @param[in] pin_value Level to be written to pin output event. + */ + fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); + + /** Read level of a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_value Pointer to return the pin level. + */ + fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); + + /** Write specified level to a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be written to. + * @param[in] level State to be written to the pin. + */ + fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); + + /** Set the direction of one or more pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port being configured. + * @param[in] direction_values Value controlling direction of pins on port. + * @param[in] mask Mask controlling which pins on the port are to be configured. + */ + fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, + ioport_size_t mask); + + /** Read captured event data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_event_data Pointer to return the event data. + */ + fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); + + /** Write event output data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port event data will be written to. + * @param[in] event_data Data to be written as event data to specified port. + * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. + * being written to port. + */ + fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, + ioport_size_t mask_value); + + /** Read states of pins on the specified port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_port_value Pointer to return the port value. + */ + fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); + + /** Write to multiple pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be written to. + * @param[in] value Value to be written to the port. + * @param[in] mask Mask controlling which pins on the port are written to. + */ + fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); +} ioport_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ioport_instance +{ + ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ioport_api_t const * p_api; ///< Pointer to the API structure for this instance +} ioport_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ipc_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ipc_api.h new file mode 100644 index 0000000000..8ad24538a3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ipc_api.h @@ -0,0 +1,164 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_IPC_API_H +#define R_IPC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SYSTEM_INTERFACES + * @defgroup IPC_API IPC Interface + * @brief Interface for inter-processor communications (IPC). + * + * @section IPC_INTERFACE_SUMMARY Summary + * The IPC interface provides common APIs for IPC HAL drivers. The IPC interface supports the following features: + * - Sending and receiving messages between cores via IPC one-way FIFOs + * - Triggering maskable interrupts between cores + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IPC Events */ +typedef enum e_ipc_event +{ + IPC_EVENT_IRQ0 = (1UL << 0), ///< IRQ Event 0 set + IPC_EVENT_IRQ1 = (1UL << 1), ///< IRQ Event 1 set + IPC_EVENT_IRQ2 = (1UL << 2), ///< IRQ Event 2 set + IPC_EVENT_IRQ3 = (1UL << 3), ///< IRQ Event 3 set + IPC_EVENT_IRQ4 = (1UL << 4), ///< IRQ Event 4 set + IPC_EVENT_IRQ5 = (1UL << 5), ///< IRQ Event 5 set + IPC_EVENT_IRQ6 = (1UL << 6), ///< IRQ Event 6 set + IPC_EVENT_IRQ7 = (1UL << 7), ///< IRQ Event 7 set + IPC_EVENT_MESSAGE_RECEIVED = (1UL << 16), ///< Message received over FIFO + IPC_EVENT_FIFO_ERROR_EMPTY = (1UL << 24), ///< A read was attempted on an empty FIFO + IPC_EVENT_FIFO_ERROR_FULL = (1UL << 25), ///< Data couldn't be written to a full FIFO +} ipc_event_t; + +/** IPC Generate Events */ +typedef enum e_ipc_generate_event +{ + IPC_GENERATE_EVENT_IRQ0 = (1UL << 0), ///< Generate IRQ Event 0 + IPC_GENERATE_EVENT_IRQ1 = (1UL << 1), ///< Generate IRQ Event 1 + IPC_GENERATE_EVENT_IRQ2 = (1UL << 2), ///< Generate IRQ Event 2 + IPC_GENERATE_EVENT_IRQ3 = (1UL << 3), ///< Generate IRQ Event 3 + IPC_GENERATE_EVENT_IRQ4 = (1UL << 4), ///< Generate IRQ Event 4 + IPC_GENERATE_EVENT_IRQ5 = (1UL << 5), ///< Generate IRQ Event 5 + IPC_GENERATE_EVENT_IRQ6 = (1UL << 6), ///< Generate IRQ Event 6 + IPC_GENERATE_EVENT_IRQ7 = (1UL << 7), ///< Generate IRQ Event 7 +} ipc_generate_event_t; + +/** IPC Callback parameter definition */ +typedef struct st_ipc_callback_args +{ + uint32_t channel; ///< IPC channel + uint32_t message; ///< Received message data + ipc_event_t event; ///< Event code + void * p_context; ///< Context provided to user during callback +} ipc_callback_args_t; + +/** IPC Configuration */ +typedef struct st_ipc_cfg +{ + uint32_t channel; ///< IPC channel + + /** IPC IRQ number + * @note Only required if the user wants to receive messages or interrupts over IPC. + * IRQ should be set to FSP_INVALID_VECTOR when not used. + */ + IRQn_Type irq; + + /** IPC Interrupt priority + * @note Only required if the user wants to receive messages or interrupts over IPC. + */ + uint8_t ipl; + + /** Pointer to callback function + * @note Only required if the user wants to receive messages or interrupts over IPC. + * p_callback should be set to NULL when not used. + */ + void (* p_callback)(ipc_callback_args_t * p_args); + void * p_context; ///< User defined context passed into callback function +} ipc_cfg_t; + +/** IPC control block. Allocate an instance specific control block to pass into the IPC API calls. + */ +typedef void ipc_ctrl_t; + +/** Interface definition for IPC */ +typedef struct st_ipc_api +{ + /** Open IPC instance. + * + * @param[in,out] p_ctrl Pointer to the IPC control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to IPC configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(ipc_ctrl_t * const p_ctrl, ipc_cfg_t const * const p_cfg); + + /** Send message through the FIFO of the configured IPC channel. + * @note Should only be called from the core on the transmit side of the IPC channel. + * + * @param[in] p_ctrl Pointer to the IPC control block. + * @param[in] message Message to send. + */ + fsp_err_t (* messageSend)(ipc_ctrl_t * const p_ctrl, uint32_t message); + + /** Generate event through configured IPC channel interrupt. + * @note Should only be called from the core on the transmit side of the IPC channel. + * + * @param[in] p_ctrl Pointer to the IPC control block. + * @param[in] event Event to generate interrupt for. + */ + fsp_err_t (* eventGenerate)(ipc_ctrl_t * const p_ctrl, ipc_generate_event_t event); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the IPC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(ipc_ctrl_t * const p_ctrl, void (* p_callback)(ipc_callback_args_t *), + void * const p_context, ipc_callback_args_t * const p_callback_memory); + + /** Close IPC instance. + * + * @param[in] p_ctrl Pointer to the IPC control block. + */ + fsp_err_t (* close)(ipc_ctrl_t * const p_ctrl); +} ipc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ipc_instance +{ + ipc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ipc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ipc_api_t const * p_api; ///< Pointer to the API structure for this instance +} ipc_instance_t; + +/******************************************************************************************************************//** + * @} (end defgroup IPC_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_jpeg_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_jpeg_api.h new file mode 100644 index 0000000000..098183f233 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_jpeg_api.h @@ -0,0 +1,317 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_jpeg_api.h + * Description : JPEG_interface layer API + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_GRAPHICS_INTERFACES + * @defgroup JPEG_API JPEG Codec Interface + * @brief Interface for JPEG functions. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_JPEG_API_H +#define R_JPEG_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/** Configuration for this module */ +#include "r_jpeg_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Image color space definitions */ +typedef enum e_jpeg_color_space +{ + JPEG_COLOR_SPACE_YCBCR444 = 0, ///< Color Space YCbCr 444 + JPEG_COLOR_SPACE_YCBCR422 = 1, ///< Color Space YCbCr 422 + JPEG_COLOR_SPACE_YCBCR420 = 2, ///< Color Space YCbCr 420 + JPEG_COLOR_SPACE_YCBCR411 = 6, ///< Color Space YCbCr 411 +} jpeg_color_space_t; + +/** Multi-byte Data Format */ +typedef enum e_jpeg_data_order +{ + JPEG_DATA_ORDER_NORMAL = 0, ///< (1)(2)(3)(4)(5)(6)(7)(8) Normal byte order + JPEG_DATA_ORDER_BYTE_SWAP = 1, ///< (2)(1)(4)(3)(6)(5)(8)(7) Byte Swap + JPEG_DATA_ORDER_WORD_SWAP = 2, ///< (3)(4)(1)(2)(7)(8)(5)(6) Word Swap + JPEG_DATA_ORDER_WORD_BYTE_SWAP = 3, ///< (4)(3)(2)(1)(8)(7)(6)(5) Word-Byte Swap + JPEG_DATA_ORDER_LONGWORD_SWAP = 4, ///< (5)(6)(7)(8)(1)(2)(3)(4) Longword Swap + JPEG_DATA_ORDER_LONGWORD_BYTE_SWAP = 5, ///< (6)(5)(8)(7)(2)(1)(4)(3) Longword Byte Swap + JPEG_DATA_ORDER_LONGWORD_WORD_SWAP = 6, ///< (7)(8)(5)(6)(3)(4)(1)(2) Longword Word Swap + JPEG_DATA_ORDER_LONGWORD_WORD_BYTE_SWAP = 7, ///< (8)(7)(6)(5)(4)(3)(2)(1) Longword Word Byte Swap +} jpeg_data_order_t; + +/** JPEG HLD driver internal status information. + * The driver can simultaneously be in more than any one status at the same time. + * Parse the status bit-fields using the definitions in this enum to determine driver status */ +typedef enum e_jpeg_status +{ + JPEG_STATUS_NONE = 0x0, ///< JPEG codec module is not initialized. + JPEG_STATUS_IDLE = 0x1, ///< JPEG Codec module is open but not running. + JPEG_STATUS_RUNNING = 0x2, ///< JPEG Codec is running. + JPEG_STATUS_HEADER_PROCESSING = 0x4, ///< JPEG Codec module is reading the JPEG header information. + JPEG_STATUS_INPUT_PAUSE = 0x8, ///< JPEG Codec paused waiting for more input data. + JPEG_STATUS_OUTPUT_PAUSE = 0x10, ///< JPEG Codec paused after it decoded the number of lines specified by user. + JPEG_STATUS_IMAGE_SIZE_READY = 0x20, ///< JPEG decoding operation obtained image size, and paused. + JPEG_STATUS_ERROR = 0x40, ///< JPEG Codec module encountered an error. + JPEG_STATUS_OPERATION_COMPLETE = 0x80, ///< JPEG Codec has completed the operation. +} jpeg_status_t; + +typedef enum e_jpeg_mode +{ + JPEG_MODE_DECODE, + JPEG_MODE_ENCODE +} jpeg_mode_t; + +/** Pixel Data Format */ +typedef enum e_jpeg_decode_pixel_format +{ + JPEG_DECODE_PIXEL_FORMAT_ARGB8888 = 1, ///< Pixel Data ARGB8888 format + JPEG_DECODE_PIXEL_FORMAT_RGB565 ///< Pixel Data RGB565 format +} jpeg_decode_pixel_format_t; + +/** Data type for horizontal and vertical subsample settings. This setting applies only to the decoding operation. */ +typedef enum e_jpeg_decode_subsample +{ + JPEG_DECODE_OUTPUT_NO_SUBSAMPLE = 0, ///< No subsample. The image is decoded with no reduction in size. + JPEG_DECODE_OUTPUT_SUBSAMPLE_HALF = 1, ///< The output image size is reduced by half. + JPEG_DECODE_OUTPUT_SUBSAMPLE_ONE_QUARTER = 2, ///< The output image size is reduced to one-quarter. + JPEG_DECODE_OUTPUT_SUBSAMPLE_ONE_EIGHTH = 3 ///< The output image size is reduced to one-eighth. +} jpeg_decode_subsample_t; + +/** Image parameter structure */ +typedef struct st_jpeg_encode_image_size +{ + uint16_t horizontal_stride_pixels; ///< Horizontal stride + uint16_t horizontal_resolution; ///< Horizontal Resolution in pixels + uint16_t vertical_resolution; ///< Vertical Resolution in pixels +} jpeg_encode_image_size_t; + +/** Callback status structure */ +typedef struct st_jpeg_callback_args +{ + jpeg_status_t status; ///< JPEG status + uint32_t image_size; ///< JPEG image size + void * p_context; ///< Pointer to user-provided context +} jpeg_callback_args_t; + +/** User configuration structure, used in open function. */ +typedef struct st_jpeg_cfg +{ + /* General configuration */ + IRQn_Type jedi_irq; ///< Data transfer interrupt IRQ number + IRQn_Type jdti_irq; ///< Decompression interrupt IRQ number + uint8_t jdti_ipl; ///< Data transfer interrupt priority + uint8_t jedi_ipl; ///< Decompression interrupt priority + +#if JPEG_CFG_DECODE_ENABLE && JPEG_CFG_ENCODE_ENABLE + jpeg_mode_t default_mode; ///< Mode to use at startup +#endif + +#if JPEG_CFG_DECODE_ENABLE + + /* Decode configuration */ + jpeg_data_order_t decode_input_data_order; ///< Input data stream byte order + jpeg_data_order_t decode_output_data_order; ///< Output data stream byte order + jpeg_decode_pixel_format_t pixel_format; ///< Pixel format + uint8_t alpha_value; ///< Alpha value to be applied to decoded pixel data. Only valid for ARGB8888 format. + void (* p_decode_callback)(jpeg_callback_args_t * p_args); ///< User-supplied callback functions. + void * p_decode_context; ///< Placeholder for user data. Passed to user callback in ::jpeg_callback_args_t. +#endif + +#if JPEG_CFG_ENCODE_ENABLE + + /* Encode configuration */ + jpeg_data_order_t encode_input_data_order; ///< Input data stream byte order + jpeg_data_order_t encode_output_data_order; ///< Output data stream byte order + uint16_t dri_marker; ///< DRI Marker setting (0 = No DRI or RST marker) + uint16_t horizontal_resolution; ///< Horizontal resolution of input image + uint16_t vertical_resolution; ///< Vertical resolution of input image + uint16_t horizontal_stride_pixels; ///< Horizontal stride of input image + uint8_t const * p_quant_luma_table; ///< Luma quantization table + uint8_t const * p_quant_chroma_table; ///< Chroma quantization table + uint8_t const * p_huffman_luma_ac_table; ///< Huffman AC table for luma + uint8_t const * p_huffman_luma_dc_table; ///< Huffman DC table for luma + uint8_t const * p_huffman_chroma_ac_table; ///< Huffman AC table for chroma + uint8_t const * p_huffman_chroma_dc_table; ///< Huffman DC table for chroma + void (* p_encode_callback)(jpeg_callback_args_t * p_args); ///< User-supplied callback functions. + void * p_encode_context; ///< Placeholder for user data. Passed to user callback in ::jpeg_callback_args_t. +#endif +} jpeg_cfg_t; + +/** JPEG decode control block. Allocate an instance specific control block to pass into the JPEG decode API calls. + */ +typedef void jpeg_ctrl_t; + +/** JPEG functions implemented at the HAL layer will follow this API. */ +typedef struct st_jpeg_api +{ + /** Initial configuration + * + * @pre none + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(jpeg_ctrl_t * const p_ctrl, jpeg_cfg_t const * const p_cfg); + + /** Assign input data buffer to JPEG codec. + * + * @pre the JPEG codec module must have been opened properly. + * @note The buffer starting address must be 8-byte aligned. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[in] p_buffer Pointer to the input buffer space + * @param[in] buffer_size Size of the input buffer + */ + fsp_err_t (* inputBufferSet)(jpeg_ctrl_t * const p_ctrl, void * p_buffer, uint32_t buffer_size); + + /** Assign output buffer to JPEG codec for storing output data. + * + * @pre The JPEG codec module must have been opened properly. + * @note The buffer starting address must be 8-byte aligned. + * For the decoding process, the HLD driver automatically computes the number of lines of the image to decoded so the + * output data fits into the given space. If the supplied output buffer is not able to hold the entire frame, + * the application should call the Output Full Callback function so it can be notified when additional buffer space is + * needed. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[in] p_buffer Pointer to the output buffer space + * @param[in] buffer_size Size of the output buffer + */ + fsp_err_t (* outputBufferSet)(jpeg_ctrl_t * const p_ctrl, void * p_buffer, uint32_t buffer_size); + + /** Retrieve current status of the JPEG codec module. + * + * @pre the JPEG codec module must have been opened properly. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[out] p_status JPEG module status + */ + fsp_err_t (* statusGet)(jpeg_ctrl_t * const p_ctrl, jpeg_status_t * const p_status); + + /** Cancel an outstanding operation. + * + * @pre the JPEG codec module must have been opened properly. + * @note If the encoding or the decoding operation is finished without errors, the HLD driver + * automatically closes the device. In this case, application does not need to explicitly close the + * JPEG device. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + */ + fsp_err_t (* close)(jpeg_ctrl_t * const p_ctrl); + +#if JPEG_CFG_DECODE_ENABLE + + /** Configure the horizontal stride value. + * + * @pre The JPEG codec module must have been opened properly. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[in] horizontal_stride Horizontal stride value to be used for the decoded image data. + * @param[in] buffer_size Size of the output buffer + */ + fsp_err_t (* horizontalStrideSet)(jpeg_ctrl_t * const p_ctrl, uint32_t horizontal_stride); + + /** Get the input pixel format. + * + * @pre the JPEG codec module must have been opened properly. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[out] p_color_space JPEG input format. + */ + fsp_err_t (* pixelFormatGet)(jpeg_ctrl_t * const p_ctrl, jpeg_color_space_t * const p_color_space); + + /** Configure the horizontal and vertical subsample settings. + * + * @pre The JPEG codec module must have been opened properly. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[in] horizontal_subsample Horizontal subsample value + * @param[in] vertical_subsample Vertical subsample value + */ + fsp_err_t (* imageSubsampleSet)(jpeg_ctrl_t * const p_ctrl, jpeg_decode_subsample_t horizontal_subsample, + jpeg_decode_subsample_t vertical_subsample); + + /** Return the number of lines decoded into the output buffer. + * + * @pre the JPEG codec module must have been opened properly. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[out] p_lines Number of lines decoded + */ + fsp_err_t (* linesDecodedGet)(jpeg_ctrl_t * const p_ctrl, uint32_t * const p_lines); + + /** Retrieve image size during decoding operation. + * + * @pre the JPEG codec module must have been opened properly. + * @note If the encoding or the decoding operation is finished without errors, the HLD driver + * automatically closes the device. In this case, application does not need to explicitly close the + * JPEG device. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[out] p_horizontal_size Image horizontal size, in number of pixels. + * @param[out] p_vertical_size Image vertical size, in number of pixels. + */ + fsp_err_t (* imageSizeGet)(jpeg_ctrl_t * const p_ctrl, uint16_t * p_horizontal_size, uint16_t * p_vertical_size); +#endif + +#if JPEG_CFG_ENCODE_ENABLE + + /** Set image parameters to JPEG Codec + * + * @pre The JPEG codec module must have been opened properly. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_image_size Pointer to the RAW image parameters + */ + fsp_err_t (* imageSizeSet)(jpeg_ctrl_t * const p_ctrl, jpeg_encode_image_size_t * p_image_size); + + #if JPEG_CFG_DECODE_ENABLE + + /** Switch between encode and decode mode or vice-versa. + * + * @pre The JPEG codec module must have been opened properly. + * The JPEG Codec can only perform one operation at a time and requires different configuration for encode and + * decode. This function facilitates easy switching between the two modes in case both are needed in an application. + * @param[in] p_ctrl Control block set in jpeg_api_t::open call. + * @param[in] mode Mode to switch to + */ + fsp_err_t (* modeSet)(jpeg_ctrl_t * const p_ctrl, jpeg_mode_t mode); + #endif +#endif +} jpeg_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_jpeg_instance +{ + jpeg_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + jpeg_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + jpeg_api_t const * p_api; ///< Pointer to the API structure for this instance +} jpeg_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup JPEG_DECODE_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_keymatrix_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_keymatrix_api.h new file mode 100644 index 0000000000..f995350572 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_keymatrix_api.h @@ -0,0 +1,119 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup KEYMATRIX_API Key Matrix Interface + * @ingroup RENESAS_INPUT_INTERFACES + * @brief Interface for key matrix functions. + * + * @section KEYMATRIX_API_SUMMARY Summary + * The KEYMATRIX interface provides standard Key Matrix functionality including event generation on a rising or falling + * edge for one or more channels at the same time. The generated event indicates all channels that are active in + * that instant via a bit mask. This allows the interface to be used with a matrix configuration or a one-to-one + * hardware implementation that is triggered on either a rising or a falling edge. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_KEYMATRIX_API_H +#define R_KEYMATRIX_API_H + +/********************************************************************************************************************** + * Includes + *********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ + +/** Key matrix control block. Allocate an instance specific control block to pass into the key matrix API calls. + */ +typedef void keymatrix_ctrl_t; + +/** Trigger type: rising edge, falling edge */ +typedef enum e_keymatrix_trigger +{ + KEYMATRIX_TRIG_FALLING = 0, ///< Falling edge trigger + KEYMATRIX_TRIG_RISING = 1, ///< Rising edge trigger +} keymatrix_trigger_t; + +/** Callback function parameter data */ +typedef struct st_keymatrix_callback_args +{ + void * p_context; ///< Holder for user data. Set in @ref keymatrix_api_t::open function in @ref keymatrix_cfg_t. + + /** Bit vector representing the physical hardware channel(s) that caused the interrupt. */ + uint32_t channel_mask; +} keymatrix_callback_args_t; + +/** User configuration structure, used in open function */ +typedef struct st_keymatrix_cfg +{ + uint32_t channel_mask; ///< Key Input channel(s). Bit mask of channels to open. + keymatrix_trigger_t trigger; ///< Key Input trigger setting. + uint8_t ipl; ///< Interrupt priority level + IRQn_Type irq; ///< NVIC IRQ number + + void (* p_callback)(keymatrix_callback_args_t * p_args); ///< Callback for key interrupt ISR. + void * p_context; ///< Holder for user data. Passed to callback in keymatrix_user_cb_data_t. + void const * p_extend; ///< Extension parameter for hardware specific settings. +} keymatrix_cfg_t; + +/** Key Matrix driver structure. Key Matrix functions implemented at the HAL layer will use this API. */ +typedef struct st_keymatrix_api +{ + /** Initial configuration. + * + * @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set in this function. + * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user. + */ + fsp_err_t (* open)(keymatrix_ctrl_t * const p_ctrl, keymatrix_cfg_t const * const p_cfg); + + /** Enable Key interrupt + * + * @param[in] p_ctrl Control block pointer set in Open call for this Key interrupt. + */ + fsp_err_t (* enable)(keymatrix_ctrl_t * const p_ctrl); + + /** Disable Key interrupt. + * + * @param[in] p_ctrl Control block pointer set in Open call for this Key interrupt. + */ + fsp_err_t (* disable)(keymatrix_ctrl_t * const p_ctrl); + + /** Allow driver to be reconfigured. May reduce power consumption. + * + * @param[in] p_ctrl Control block pointer set in Open call for this Key interrupt. + */ + fsp_err_t (* close)(keymatrix_ctrl_t * const p_ctrl); +} keymatrix_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_keymatrix_instance +{ + keymatrix_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + keymatrix_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + keymatrix_api_t const * p_api; ///< Pointer to the API structure for this instance +} keymatrix_instance_t; + +/******************************************************************************************************************//** + * @} (end addtogroup KEYMATRIX_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lin_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lin_api.h new file mode 100644 index 0000000000..e9f7c64010 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lin_api.h @@ -0,0 +1,256 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_LIN_API_H +#define R_LIN_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup LIN_API LIN Interface + * @brief Interface for LIN communications. + * + * @section LIN_INTERFACE_SUMMARY Summary + * The LIN interface provides common APIs for LIN HAL drivers. The LIN interface supports the following features: + * - Half-duplex master or slave LIN communication + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code and data + * - Checksum generation and validation (standard or enhanced) + * - Bus Sleep and Wakeup + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** LIN driver mode */ +typedef enum e_lin_mode +{ + LIN_MODE_SLAVE = 0U, ///< Slave mode + LIN_MODE_MASTER = 1U, ///< Master mode +} lin_mode_t; + +/** LIN checksum type */ +typedef enum e_lin_checksum_type +{ + LIN_CHECKSUM_TYPE_CLASSIC = 0U, ///< 8 bit LIN classic checksum over data bytes only + LIN_CHECKSUM_TYPE_ENHANCED = 1U, ///< 8 bit LIN enhanced checksum over data bytes and PID + LIN_CHECKSUM_TYPE_NONE = 2U, ///< Skip driver checksum generation/validation +} lin_checksum_type_t; + +/** LIN Event codes */ +typedef enum e_lin_event +{ + LIN_EVENT_NONE = (0), ///< No event present + LIN_EVENT_RX_START_FRAME_COMPLETE = (1UL << 1), ///< DEPRECATED, do not use + LIN_EVENT_RX_INFORMATION_FRAME_COMPLETE = (1UL << 2), ///< DEPRECATED, do not use + LIN_EVENT_TX_START_FRAME_COMPLETE = (1UL << 3), ///< DEPRECATED, do not use + LIN_EVENT_TX_INFORMATION_FRAME_COMPLETE = (1UL << 4), ///< DEPRECATED, do not use + LIN_EVENT_RX_HEADER_COMPLETE = (1UL << 1), ///< Header received event. + LIN_EVENT_RX_DATA_COMPLETE = (1UL << 2), ///< Data received event. + LIN_EVENT_TX_HEADER_COMPLETE = (1UL << 3), ///< Header transmission complete event + LIN_EVENT_TX_DATA_COMPLETE = (1UL << 4), ///< Data transmission complete event + LIN_EVENT_ERR_INVALID_CHECKSUM = (1UL << 5), ///< Data received successfully, but checksum was invalid + LIN_EVENT_TX_WAKEUP_COMPLETE = (1UL << 6), ///< Transmit wake up complete event + LIN_EVENT_RX_WAKEUP_COMPLETE = (1UL << 7), ///< Receive wake up complete event + LIN_EVENT_ERR_TIMEOUT = (1UL << 8), ///< Timeout error event + LIN_EVENT_ERR_BUS_COLLISION_DETECTED = (1UL << 9), ///< Bus collision detection event + LIN_EVENT_ERR_SYNC = (1UL << 10), ///< Sync field error event + LIN_EVENT_ERR_RESPONSE_PREPARE = (1UL << 11), ///< Response preparation error event + LIN_EVENT_ERR_PHYSICAL_BUS = (1UL << 12), ///< Physical bus error detection event + LIN_EVENT_ERR_COUNTER_OVERFLOW = (1UL << 14), ///< Counter overflow event + LIN_EVENT_ERR_OVERRUN = (1UL << 24), ///< Overrun error event + LIN_EVENT_ERR_PARITY = (1UL << 27), ///< Parity error event (header only, LIN data is sent without parity) + LIN_EVENT_ERR_FRAMING = (1UL << 28), ///< Framing error event +} lin_event_t; + +/** LIN data length type */ +#ifndef BSP_OVERRIDE_LIN_DATA_LENGTH_T +typedef uint8_t lin_data_length_t; ///< Data length type uint8_t +#else +typedef uint16_t lin_data_length_t; ///< Data length type uint16_t +#endif + +/** LIN Transfer Parameters */ +typedef struct st_lin_transfer_params +{ + uint8_t id; ///< The unprotected frame ID associated with the data transfer + union + { + uint8_t * p_information; ///< DEPRECATED, do not use + uint8_t * p_data; ///< Pointer to rx or tx buffer associated with the data transfer. + }; + + lin_data_length_t num_bytes; ///< Length of buffer pointed to by p_data, in bytes + lin_checksum_type_t checksum_type; ///< Checksum type to use for checksum generation (when writing data) or validation (when reading data). See @ref lin_checksum_type_t +} lin_transfer_params_t; + +/** LIN Callback Arguments */ +typedef struct st_lin_callback_arg +{ + uint32_t channel; ///< Channel number + lin_event_t event; ///< Event code + + /** Valid for the following events: + * - LIN_EVENT_RX_DATA_COMPLETE + * - LIN_EVENT_ERR_FRAMING + * - LIN_EVENT_ERR_INVALID_CHECKSUM + * + * Contains the number of data bytes received for a + * data reception. + */ + lin_data_length_t bytes_received; + + /** For LIN slave: Contains the most recently received protected identifier + * For LIN master: Contains the most recently transmitted protected identifier. + */ + uint8_t pid; + + /** Received checksum. Valid for the following events: + * - LIN_EVENT_RX_DATA_COMPLETE + * - LIN_EVENT_ERR_INVALID_CHECKSUM. + */ + uint8_t checksum; + + void * p_context; ///< Context provided to user during callback +} lin_callback_args_t; + +/** LIN configuration block */ +typedef struct st_lin_cfg +{ + /* LIN generic configuration */ + uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware. + lin_mode_t mode; ///< Driver mode (master or slave) + + /* Configuration for LIN Event processing */ + void (* p_callback)(lin_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /* Pointer to LIN peripheral specific configuration */ + void const * p_extend; ///< LIN hardware dependent configuration +} lin_cfg_t; + +/** LIN control block. Allocate an instance specific control block to pass into the LIN API calls. + */ +typedef void lin_ctrl_t; + +/** Interface definition for LIN */ +typedef struct st_lin_api +{ + /** Open LIN device. Transmission and reception of LIN frames is enabled upon successful return from this function. + * + * @param[in,out] p_ctrl Pointer to the LIN control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to LIN configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(lin_ctrl_t * const p_ctrl, lin_cfg_t const * const p_cfg); + + /** Begin non-blocking transmission of a LIN frame. + * + * If the node is a LIN master, the LIN header is transmitted before data, if present. + * + * For header-only transmissions (master mode), when the header transmission completes successfully, the + * callback is called with the event LIN_EVENT_TX_HEADER_COMPLETE. + * + * For header+data (master mode) or data-only transmission (slave mode), when the data transmission completes + * successfully, the callback is called with event LIN_EVENT_TX_DATA_COMPLETE. + * + * @param[in,out] p_ctrl Pointer to the LIN control block. + * @param[in] p_transfer_params Pointer to parameters required for the write transaction. + */ + fsp_err_t (* write)(lin_ctrl_t * const p_ctrl, const lin_transfer_params_t * const p_transfer_params); + + /** Begin non-blocking read of data bytes. + * + * When a read completes successfully, the callback is called with event LIN_EVENT_RX_DATA_COMPLETE. + * + * @param[in] p_ctrl Pointer to the LIN control block for the channel. + * @param[in] p_transfer_params Pointer to parameters required for the read transaction. + */ + fsp_err_t (* read)(lin_ctrl_t * const p_ctrl, lin_transfer_params_t * const p_transfer_params); + + /** Abort ongoing transfer. + * + * @param[in] p_ctrl Pointer to the LIN control block. + */ + fsp_err_t (* communicationAbort)(lin_ctrl_t * const p_ctrl); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the LIN control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(lin_ctrl_t * const p_ctrl, void (* p_callback)(lin_callback_args_t *), + void * const p_context, lin_callback_args_t * const p_callback_memory); + + /** Send wakeup signal for LIN device. + * + * @param[in] p_ctrl Pointer to the LIN control block. + */ + fsp_err_t (* wakeupSend)(lin_ctrl_t * const p_ctrl); + + /** Place the LIN node in bus sleep mode. + * + * @param[in] p_ctrl Pointer to the LIN control block. + */ + fsp_err_t (* sleepEnter)(lin_ctrl_t * const p_ctrl); + + /** Exit the bus sleep mode for LIN device. + * + * @param[in] p_ctrl Pointer to the LIN control block. + */ + fsp_err_t (* sleepExit)(lin_ctrl_t * const p_ctrl); + + /** Close LIN device. + * + * @param[in] p_ctrl Pointer to the LIN control block. + */ + fsp_err_t (* close)(lin_ctrl_t * const p_ctrl); + + /** [DEPRECATED] Use @ref lin_api_t::read + */ + fsp_err_t (* informationFrameRead)(lin_ctrl_t * const p_ctrl, lin_transfer_params_t * const p_transfer_params); + + /** [DEPRECATED] Use @ref lin_api_t::write + */ + fsp_err_t (* startFrameWrite)(lin_ctrl_t * const p_ctrl, uint8_t const id); + + /** [DEPRECATED] Use @ref lin_api_t::write + */ + fsp_err_t (* informationFrameWrite)(lin_ctrl_t * const p_ctrl, + const lin_transfer_params_t * const p_transfer_params); +} lin_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_lin_instance +{ + lin_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + lin_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + lin_api_t const * p_api; ///< Pointer to the API structure for this instance +} lin_instance_t; + +/******************************************************************************************************************//** + * @} (end addtogroup LIN_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lpm_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lpm_api.h new file mode 100644 index 0000000000..ff33e6298a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lpm_api.h @@ -0,0 +1,663 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_POWER_INTERFACES + * @defgroup LPM_API Low Power Modes Interface + * @brief Interface for accessing low power modes. + * + * @section LPM_API_SUMMARY Summary + * This section defines the API for the LPM (Low Power Mode) Driver. + * The LPM Driver provides functions for controlling power consumption by configuring + * and transitioning to a low power mode. + * The LPM driver supports configuration of MCU low power modes using the LPM hardware + * peripheral. The LPM driver supports low power modes deep standby, standby, sleep, and snooze. + * + * @note Not all low power modes are available on all MCUs. + * + * + * @{ + **********************************************************************************************************************/ +#ifndef R_LPM_API_H +#define R_LPM_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +#if __has_include("r_lpm_device_types.h") + #include "r_lpm_device_types.h" +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Low power modes */ +typedef enum e_lpm_mode +{ + LPM_MODE_SLEEP, ///< Sleep mode + LPM_MODE_DEEP_SLEEP, ///< Deep Sleep mode + LPM_MODE_STANDBY, ///< Software Standby mode + LPM_MODE_STANDBY_SNOOZE, ///< Software Standby mode with Snooze mode enabled + LPM_MODE_DEEP, ///< Deep Software Standby mode +} lpm_mode_t; + +#ifndef BSP_OVERRIDE_LPM_SNOOZE_REQUEST_T + +/** Snooze request sources */ +typedef enum e_lpm_snooze_request +{ + LPM_SNOOZE_REQUEST_RXD0_FALLING = 0x00000000ULL, ///< Enable RXD0 falling edge snooze request + LPM_SNOOZE_REQUEST_IRQ0 = 0x00000001ULL, ///< Enable IRQ0 pin snooze request + LPM_SNOOZE_REQUEST_IRQ1 = 0x00000002ULL, ///< Enable IRQ1 pin snooze request + LPM_SNOOZE_REQUEST_IRQ2 = 0x00000004ULL, ///< Enable IRQ2 pin snooze request + LPM_SNOOZE_REQUEST_IRQ3 = 0x00000008ULL, ///< Enable IRQ3 pin snooze request + LPM_SNOOZE_REQUEST_IRQ4 = 0x00000010ULL, ///< Enable IRQ4 pin snooze request + LPM_SNOOZE_REQUEST_IRQ5 = 0x00000020ULL, ///< Enable IRQ5 pin snooze request + LPM_SNOOZE_REQUEST_IRQ6 = 0x00000040ULL, ///< Enable IRQ6 pin snooze request + LPM_SNOOZE_REQUEST_IRQ7 = 0x00000080ULL, ///< Enable IRQ7 pin snooze request + LPM_SNOOZE_REQUEST_IRQ8 = 0x00000100ULL, ///< Enable IRQ8 pin snooze request + LPM_SNOOZE_REQUEST_IRQ9 = 0x00000200ULL, ///< Enable IRQ9 pin snooze request + LPM_SNOOZE_REQUEST_IRQ10 = 0x00000400ULL, ///< Enable IRQ10 pin snooze request + LPM_SNOOZE_REQUEST_IRQ11 = 0x00000800ULL, ///< Enable IRQ11 pin snooze request + LPM_SNOOZE_REQUEST_IRQ12 = 0x00001000ULL, ///< Enable IRQ12 pin snooze request + LPM_SNOOZE_REQUEST_IRQ13 = 0x00002000ULL, ///< Enable IRQ13 pin snooze request + LPM_SNOOZE_REQUEST_IRQ14 = 0x00004000ULL, ///< Enable IRQ14 pin snooze request + LPM_SNOOZE_REQUEST_IRQ15 = 0x00008000ULL, ///< Enable IRQ15 pin snooze request + LPM_SNOOZE_REQUEST_KEY = 0x00020000ULL, ///< Enable KR snooze request + LPM_SNOOZE_REQUEST_ACMPHS0 = 0x00400000ULL, ///< Enable High-speed analog comparator 0 snooze request + LPM_SNOOZE_REQUEST_RTC_ALARM1 = 0x00800000ULL, ///< Enable RTC alarm 1 snooze request + LPM_SNOOZE_REQUEST_RTC_ALARM = 0x01000000ULL, ///< Enable RTC alarm snooze request + LPM_SNOOZE_REQUEST_RTC_PERIOD = 0x02000000ULL, ///< Enable RTC period snooze request + LPM_SNOOZE_REQUEST_AGT1_UNDERFLOW = 0x10000000ULL, ///< Enable AGT1 underflow snooze request + LPM_SNOOZE_REQUEST_AGTW1_UNDERFLOW = 0x10000000ULL, ///< Enable AGTW1 underflow snooze request + LPM_SNOOZE_REQUEST_AGT1_COMPARE_A = 0x20000000ULL, ///< Enable AGT1 compare match A snooze request + LPM_SNOOZE_REQUEST_AGTW1_COMPARE_A = 0x20000000ULL, ///< Enable AGTW1 compare match A snooze request + LPM_SNOOZE_REQUEST_AGT1_COMPARE_B = 0x40000000ULL, ///< Enable AGT1 compare match B snooze request + LPM_SNOOZE_REQUEST_AGTW1_COMPARE_B = 0x40000000ULL, ///< Enable AGTW1 compare match B snooze request + LPM_SNOOZE_REQUEST_AGT3_UNDERFLOW = 0x100000000ULL, ///< Enable AGT3 underflow snooze request + LPM_SNOOZE_REQUEST_AGT3_COMPARE_A = 0x200000000ULL, ///< Enable AGT3 compare match A snooze request + LPM_SNOOZE_REQUEST_AGT3_COMPARE_B = 0x400000000ULL, ///< Enable AGT3 compare match B snooze request +} lpm_snooze_request_t; +#endif + +#ifndef BSP_OVERRIDE_LPM_SNOOZE_END_T + +/** Snooze end control */ +typedef enum e_lpm_snooze_end +{ + LPM_SNOOZE_END_STANDBY_WAKE_SOURCES = 0x00U, ///< Transition from Snooze to Normal mode directly + LPM_SNOOZE_END_AGT1_UNDERFLOW = 0x01U, ///< AGT1 underflow + LPM_SNOOZE_END_AGTW1_UNDERFLOW = 0x01U, ///< AGTW1 underflow + LPM_SNOOZE_END_DTC_TRANS_COMPLETE = 0x02U, ///< Last DTC transmission completion + LPM_SNOOZE_END_DTC_TRANS_COMPLETE_NEGATED = 0x04U, ///< Not Last DTC transmission completion + LPM_SNOOZE_END_ADC0_COMPARE_MATCH = 0x08U, ///< ADC Channel 0 compare match + LPM_SNOOZE_END_ADC0_COMPARE_MISMATCH = 0x10U, ///< ADC Channel 0 compare mismatch + LPM_SNOOZE_END_ADC1_COMPARE_MATCH = 0x20U, ///< ADC 1 compare match + LPM_SNOOZE_END_ADC1_COMPARE_MISMATCH = 0x40U, ///< ADC 1 compare mismatch + LPM_SNOOZE_END_SCI0_ADDRESS_MISMATCH = 0x80U, ///< SCI0 address mismatch + LPM_SNOOZE_END_AGT3_UNDERFLOW = 0x100U, ///< AGT3 underflow +} lpm_snooze_end_t; + +typedef uint16_t lpm_snooze_end_bits_t; +#endif + +#ifndef BSP_OVERRIDE_LPM_SNOOZE_CANCEL_T + +/** Snooze cancel control */ +typedef enum e_lpm_snooze_cancel +{ + LPM_SNOOZE_CANCEL_SOURCE_NONE = ELC_EVENT_NONE, ///< No snooze cancel source + LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPM = ELC_EVENT_ADC0_COMPARE_MATCH, ///< ADC Channel 0 window compare match + #if (2U != BSP_FEATURE_ELC_VERSION) + LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPUM = ELC_EVENT_ADC0_COMPARE_MISMATCH, ///< ADC Channel 0 window compare mismatch + #endif + #if BSP_FEATURE_ADC_VALID_UNIT_MASK & (1U << 1) // If ADC has unit 1 + LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPM = ELC_EVENT_ADC1_COMPARE_MATCH, ///< ADC Channel 1 window compare match + #if (2U != BSP_FEATURE_ELC_VERSION) + LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPUM = ELC_EVENT_ADC1_COMPARE_MISMATCH, ///< ADC Channel 1 window compare mismatch + #endif + #endif + #if (BSP_FEATURE_SCI_CHANNELS_MASK & (1U << 0)) && (2U != BSP_FEATURE_ELC_VERSION) // If SCI has channel 0 + LPM_SNOOZE_CANCEL_SOURCE_SCI0_AM = ELC_EVENT_SCI0_AM, ///< SCI0 address match event + LPM_SNOOZE_CANCEL_SOURCE_SCI0_RXI_OR_ERI = ELC_EVENT_SCI0_RXI_OR_ERI, ///< SCI0 receive error + #endif + LPM_SNOOZE_CANCEL_SOURCE_DTC_COMPLETE = ELC_EVENT_DTC_COMPLETE, ///< DTC transfer completion + LPM_SNOOZE_CANCEL_SOURCE_DOC_DOPCI = ELC_EVENT_DOC_INT, ///< Data operation circuit interrupt + #if BSP_FEATURE_CTSU_VERSION + LPM_SNOOZE_CANCEL_SOURCE_CTSU_CTSUFN = ELC_EVENT_CTSU_END, ///< CTSU measurement end interrupt + #endif +} lpm_snooze_cancel_t; +#endif + +/** DTC Enable in Snooze Mode */ +typedef enum e_lpm_snooze_dtc +{ + LPM_SNOOZE_DTC_DISABLE = 0U, ///< Disable DTC operation + LPM_SNOOZE_DTC_ENABLE = 1U, ///< Enable DTC operation +} lpm_snooze_dtc_t; + +#ifndef BSP_OVERRIDE_LPM_STANDBY_WAKE_SOURCE_T + +/** Wake from deep sleep or standby mode sources, does not apply to sleep or deep standby modes */ +typedef enum e_lpm_standby_wake_source +{ + LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 + LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 + LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 + LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 + LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 + LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 + LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 + LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 + LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 + LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 + LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 + LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 + LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 + LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 + LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 + LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 + LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt + LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000ULL, ///< Key interrupt + LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt + LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt + LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt + LPM_STANDBY_WAKE_SOURCE_VRTC = 0x00200000ULL, ///< LVDVRTC interrupt + LPM_STANDBY_WAKE_SOURCE_EXLVD = 0x00400000ULL, ///< LVDEXLVD interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000ULL, ///< Analog Comparator High-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_RTCALM1 = 0x00800000ULL, ///< RTC Alarm interrupt 1 + LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt + LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt + LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt + LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt + LPM_STANDBY_WAKE_SOURCE_AGTW0UD = 0x08000000ULL, ///< AGTW0 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGTW1UD = 0x10000000ULL, ///< AGTW1 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGTW1CA = 0x20000000ULL, ///< AGTW1 Compare Match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGTW1CB = 0x40000000ULL, ///< AGTW1 Compare Match B interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 Compare Match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 Compare Match B interrupt + LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt + LPM_STANDBY_WAKE_SOURCE_AGT0UD = 0x100000000ULL, ///< AGT0 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3UD = 0x100000000ULL, ///< AGT3 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD_S = 0x200000000ULL, ///< AGT1 Underflow interrupt for specific board + LPM_STANDBY_WAKE_SOURCE_AGT3CA = 0x200000000ULL, ///< AGT3 Compare Match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT2UD = 0x400000000ULL, ///< AGT2 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3CB = 0x400000000ULL, ///< AGT3 Compare Match B interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3UD_S = 0x800000000ULL, ///< AGT3 Underflow interrupt for specific board + LPM_STANDBY_WAKE_SOURCE_COMPHS0 = 0x800000000ULL, ///< Comparator-HS0 Interrupt + LPM_STANDBY_WAKE_SOURCE_AGT4UD = 0x1000000000ULL, ///< AGT4 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT5UD = 0x2000000000ULL, ///< AGT5 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT6UD = 0x4000000000ULL, ///< AGT6 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT7UD = 0x8000000000ULL, ///< AGT7 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_SOSTD = 0x10000000000ULL, ///< SOSTD interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0U = 0x10000000000ULL, ///< ULPT0 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0A = 0x20000000000ULL, ///< ULPT0 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0B = 0x40000000000ULL, ///< ULPT0 Compare Match B Interrupt + LPM_STANDBY_WAKE_SOURCE_I3C0 = 0x80000000000ULL, ///< I3C0 address match interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1U = 0x100000000000ULL, ///< ULPT1 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1A = 0x200000000000ULL, ///< ULPT1 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1B = 0x400000000000ULL, ///< ULPT1 Compare Match B Interrupt +} lpm_standby_wake_source_t; + + #if BSP_FEATURE_ICU_HAS_WUPEN2 +typedef enum e_lpm_standby_wake_source_2 +{ + LPM_STANDBY_WAKE_SOURCE_INTUR0 = 0x00000001ULL, ///< UARTA0 INTUR Interrupt + LPM_STANDBY_WAKE_SOURCE_INTURE0 = 0x00000002ULL, ///< UARTA0 INTURE Interrupt + LPM_STANDBY_WAKE_SOURCE_INTUR1 = 0x00000004ULL, ///< UARTA1 INTUR Interrupt + LPM_STANDBY_WAKE_SOURCE_INTURE1 = 0x00000008ULL, ///< UARTA1 INTURE Interrupt + LPM_STANDBY_WAKE_SOURCE_USBCCS = 0x00000010ULL, ///< USBCC Status Change Interrupt +} lpm_standby_wake_source_2_t; + #endif + +typedef uint64_t lpm_standby_wake_source_bits_t; +#endif + +/** I/O port state after Deep Software Standby mode */ +typedef enum e_lpm_io_port +{ + /** + * When the Deep Software Standby mode is canceled, the I/O ports are in the reset state + */ + LPM_IO_PORT_RESET = 0U, + + /** + * When the Deep Software Standby mode is canceled, the I/O ports are in the same state as + * in the Deep Software Standby mode + */ + LPM_IO_PORT_NO_CHANGE = 1U, +} lpm_io_port_t; + +/** Power supply control */ +typedef enum e_lpm_power_supply +{ + /** + * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume + * detecting unit is supplied in deep software standby mode + */ + LPM_POWER_SUPPLY_DEEPCUT0 = 0U, + + /** + * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume + * detecting unit is not supplied in deep software standby mode + */ + LPM_POWER_SUPPLY_DEEPCUT1 = 1U, + + /** + * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume + * detecting unit is not supplied in deep software standby mode. In addition, LVD is + * disabled and the low power function in a poweron reset circuit is enabled + */ + LPM_POWER_SUPPLY_DEEPCUT3 = 3UL, + + /** + * Power to the standby RAM, Low-speed on-chip oscillator, Programmable Voltage Detection Unit 0, + * and USBFS/HS resume detecting unit is supplied in deep software standby mode. + */ + LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1 = 0U, + + /** + * Power to standby RAM, USBFS/HS resume detecting unit, Low-speed on-chip oscillator, and IWDT is + * disabled in deep software standby mode. Power to the Programmable Voltage Detection Unit 0 is + * supplied in deep software standby mode. + */ + LPM_POWER_SUPPLY_DEEP_STANDBY_MODE2 = 1U, + + /** + * Power to standby RAM, Programmable Voltage Detection Unit 0, USBFS/HS resume detecting unit, + * Low-speed on-chip oscillator, and IWDT is disabled in deep software standby mode. + */ + LPM_POWER_SUPPLY_DEEP_STANDBY_MODE3 = 2U, +} lpm_power_supply_t; + +/** Deep Standby Interrupt Edge */ +typedef enum e_lpm_deep_standby_cancel_edge +{ + LPM_DEEP_STANDBY_CANCEL_SOURCE_EDGE_NONE = 0ULL, ///< No options for a deep standby cancel source + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0_RISING = 0x00000001ULL, ///< IRQ0-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0_FALLING = 0ULL, ///< IRQ0-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1_RISING = 0x00000002ULL, ///< IRQ1-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1_FALLING = 0ULL, ///< IRQ1-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2_RISING = 0x00000004ULL, ///< IRQ2-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2_FALLING = 0ULL, ///< IRQ2-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3_RISING = 0x00000008ULL, ///< IRQ3-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3_FALLING = 0ULL, ///< IRQ3-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4_RISING = 0x00000010ULL, ///< IRQ4-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4_FALLING = 0ULL, ///< IRQ4-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5_RISING = 0x00000020ULL, ///< IRQ5-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5_FALLING = 0ULL, ///< IRQ5-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6_RISING = 0x00000040ULL, ///< IRQ6-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6_FALLING = 0ULL, ///< IRQ6-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7_RISING = 0x00000080ULL, ///< IRQ7-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7_FALLING = 0ULL, ///< IRQ7-DS Pin Falling Edge + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8_RISING = 0x00000100ULL, ///< IRQ8-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8_FALLING = 0ULL, ///< IRQ8-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9_RISING = 0x00000200ULL, ///< IRQ9-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9_FALLING = 0ULL, ///< IRQ9-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10_RISING = 0x00000400ULL, ///< IRQ10-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10_FALLING = 0ULL, ///< IRQ10-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11_RISING = 0x00000800ULL, ///< IRQ11-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11_FALLING = 0ULL, ///< IRQ11-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12_RISING = 0x00001000ULL, ///< IRQ12-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12_FALLING = 0ULL, ///< IRQ12-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13_RISING = 0x00002000ULL, ///< IRQ13-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13_FALLING = 0ULL, ///< IRQ13-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14_RISING = 0x00004000ULL, ///< IRQ14-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14_FALLING = 0ULL, ///< IRQ14-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15_RISING = 0x00008000ULL, ///< IRQ14-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15_FALLING = 0ULL, ///< IRQ14-DS Pin Falling Edge + + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1_RISING = 0x00010000ULL, ///< LVD1 Rising Slope + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1_FALLING = 0ULL, ///< LVD1 Falling Slope + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2_RISING = 0x00020000ULL, ///< LVD2 Rising Slope + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2_FALLING = 0ULL, ///< LVD2 Falling Slope + LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI_RISING = 0x00100000ULL, ///< NMI Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI_FALLING = 0ULL, ///< NMI Pin Falling Edge + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ16_RISING = 0x01000000ULL, ///< IRQ16-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ16_FALLING = 0ULL, ///< IRQ16-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ17_RISING = 0x02000000ULL, ///< IRQ17-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ17_FALLING = 0ULL, ///< IRQ17-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ18_RISING = 0x04000000ULL, ///< IRQ18-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ18_FALLING = 0ULL, ///< IRQ18-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ19_RISING = 0x08000000ULL, ///< IRQ19-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ19_FALLING = 0ULL, ///< IRQ19-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ20_RISING = 0x10000000ULL, ///< IRQ20-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ20_FALLING = 0ULL, ///< IRQ20-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ21_RISING = 0x20000000ULL, ///< IRQ21-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ21_FALLING = 0ULL, ///< IRQ21-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ22_RISING = 0x40000000ULL, ///< IRQ22-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ22_FALLING = 0ULL, ///< IRQ22-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ23_RISING = 0x80000000ULL, ///< IRQ23-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ23_FALLING = 0ULL, ///< IRQ23-DS Pin Falling Edge + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ24_RISING = 0x0000000100000000ULL, ///< IRQ24-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ24_FALLING = 0ULL, ///< IRQ24-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ25_RISING = 0x0000000200000000ULL, ///< IRQ25-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ25_FALLING = 0ULL, ///< IRQ25-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ26_RISING = 0x0000000400000000ULL, ///< IRQ26-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ26_FALLING = 0ULL, ///< IRQ26-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ27_RISING = 0x0000000800000000ULL, ///< IRQ27-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ27_FALLING = 0ULL, ///< IRQ27-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ28_RISING = 0x0000001000000000ULL, ///< IRQ28-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ28_FALLING = 0ULL, ///< IRQ28-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ29_RISING = 0x0000002000000000ULL, ///< IRQ29-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ29_FALLING = 0ULL, ///< IRQ29-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ30_RISING = 0x0000004000000000ULL, ///< IRQ30-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ30_FALLING = 0ULL, ///< IRQ30-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ31_RISING = 0x0000008000000000ULL, ///< IRQ31-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ31_FALLING = 0ULL, ///< IRQ31-DS Pin Falling Edge +} lpm_deep_standby_cancel_edge_t; + +typedef uint64_t lpm_deep_standby_cancel_edge_bits_t; + +/** Select soft start mode in deep software standby mode. This setting configures the wake time and + * inrush current when waking from deep software standby mode (See the device user manual for more details). + */ +typedef enum e_lpm_deep_standby_soft_start_mode +{ + LPM_DEEP_STANDBY_SOFT_START_MODE_0 = 0, ///< Soft Start Mode 0 (DCSSMODE=0) + LPM_DEEP_STANDBY_SOFT_START_MODE_1 = 1, ///< Soft Start Mode 1 (DCSSMODE=1) + LPM_DEEP_STANDBY_SOFT_START_MODE_2 = 2, ///< Soft Start Mode 2 (DCSSMODE=2) + LPM_DEEP_STANDBY_SOFT_START_MODE_3 = 3, ///< Soft Start Mode 3 (DCSSMODE=3) +} lpm_deep_standby_soft_start_mode_t; + +#ifndef BSP_OVERRIDE_LPM_DEEP_STANDBY_WAKE_SOURCE_T + +/** Deep Standby cancel sources */ +typedef enum e_lpm_deep_standby_cancel_source +{ + LPM_DEEP_STANDBY_CANCEL_SOURCE_RESET_ONLY = 0U, ///< Cancel deep standby only by reset + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 + + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1 = 0x00010000ULL, ///< LVD1 + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2 = 0x00020000ULL, ///< LVD2 + LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_INTERVAL = 0x00040000ULL, ///< RTC Interval Interrupt + LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_ALARM = 0x00080000ULL, ///< RTC Alarm Interrupt + LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI = 0x00100000ULL, ///< NMI + + LPM_DEEP_STANDBY_CANCEL_SOURCE_USBFS = 0x01000000ULL, ///< USBFS Suspend/Resume + LPM_DEEP_STANDBY_CANCEL_SOURCE_USBHS = 0x02000000ULL, ///< USBHS Suspend/Resume + LPM_DEEP_STANDBY_CANCEL_SOURCE_AGT1 = 0x04000000ULL, ///< AGT1 Underflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_AGT3 = 0x08000000ULL, ///< AGT3 Underflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_ULPT0 = 0x04000000ULL, ///< ULPT0 Overflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_ULPT1 = 0x08000000ULL, ///< ULPT1 Overflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_IWDT = 0x20000000ULL, ///< IWDT Underflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_VBATT = 0x80000000ULL, ///< VBATT Tamper Detection + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ16 = 0x0000000100000000ULL, ///< IRQ16 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ17 = 0x0000000200000000ULL, ///< IRQ17 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ18 = 0x0000000400000000ULL, ///< IRQ18 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ19 = 0x0000000800000000ULL, ///< IRQ19 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ20 = 0x0000001000000000ULL, ///< IRQ20 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ21 = 0x0000002000000000ULL, ///< IRQ21 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ22 = 0x0000004000000000ULL, ///< IRQ22 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ23 = 0x0000008000000000ULL, ///< IRQ23 + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ24 = 0x0000010000000000ULL, ///< IRQ24 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ25 = 0x0000020000000000ULL, ///< IRQ25 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ26 = 0x0000040000000000ULL, ///< IRQ26 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ27 = 0x0000080000000000ULL, ///< IRQ27 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ28 = 0x0000100000000000ULL, ///< IRQ28 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ29 = 0x0000200000000000ULL, ///< IRQ29 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ30 = 0x0000400000000000ULL, ///< IRQ30 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ31 = 0x0000800000000000ULL, ///< IRQ31 +} lpm_deep_standby_cancel_source_t; +#endif + +typedef uint64_t lpm_deep_standby_cancel_source_bits_t; + +/** Output port enable */ +typedef enum e_lpm_output_port_enable +{ + /** + * 0: In Software Standby Mode or Deep Software Standby Mode, the + * address output pins, data output pins, and other bus control signal + * output pins are set to the high-impedance state. In Snooze, the + * status of the address bus and bus control signals are same as + * before entering Software Standby Mode. + */ + LPM_OUTPUT_PORT_ENABLE_HIGH_IMPEDANCE = 0U, + + /** + * 1: In Software Standby Mode, the address output pins, data output + * pins, and other bus control signal output pins retain the + * output state. + */ + LPM_OUTPUT_PORT_ENABLE_RETAIN = 1U, +} lpm_output_port_enable_t; + +/** Configure the behavior of an oscillator's LDO in standby mode. */ +typedef enum e_lpm_ldo_standby_operation +{ + /** The LDO is disabled in standby mode. */ + LPM_LDO_STANDBY_OPERATION_DISABLED, + + /** The LDO state is retained during standby mode. */ + LPM_LDO_STANDBY_OPERATION_RETAINED, +} lpm_ldo_standby_operation_t; + +#if BSP_FEATURE_LPM_HAS_PDRAMSCR || BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + +/** RAM Retention Configuration for deep sleep and standby modes. */ +typedef struct s_lpm_ram_retention +{ + #if BSP_FEATURE_LPM_HAS_PDRAMSCR + + /** Configure RAM retention in software standby mode. */ + uint16_t ram_retention; + + /** Enable or disable TCM retention in deep sleep and software standby modes. */ + bool tcm_retention; + #endif + #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + + /** Enable Standby RAM retention in software standby and deep software standby modes. */ + bool standby_ram_retention; + #endif +} lpm_ram_retention_t; +#endif + +/** Flash operating mode select. */ +typedef enum e_lpm_flash_mode_select +{ + LPM_FLASH_MODE_SELECT_ACTIVE = 0U, ///< Flash active + LPM_FLASH_MODE_SELECT_STOP = 1U, ///< Flash stop +} lpm_flash_mode_select_t; + +/** Starting the high-speed on-chip oscillator at the times of release from SSTBY mode and of transitions to SNOOZE mode. */ +typedef enum e_lpm_hoco_startup_speed +{ + LPM_HOCO_STARTUP_SPEED_NORMAL_SPEED = 0U, ///< Starting of the high-speed on-chip oscillator is at normal speed + LPM_HOCO_STARTUP_SPEED_HIGH_SPEED = 1U, ///< Starting of the high-speed on-chip oscillator is at high speed +} lpm_hoco_startup_speed_t; + +/** SOSC setting in SSTBY mode or in SNOOZE mode. */ +typedef enum e_lpm_standby_sosc +{ + LPM_STANDBY_SOSC_ENABLE = 0U, ///< Enables supply of SOSC clock to peripheral functions + LPM_STANDBY_SOSC_DISABLE = 1U, ///< Stops supply SOSC clock to peripheral functions other than the Realtime clock. +} lpm_standby_sosc_t; + +/** Configure LDO operation in standby mode. */ +typedef struct lpm_ldo_standby_cfg_s +{ + lpm_ldo_standby_operation_t pll1_ldo; ///< Configure the state of PLL1 LDO in standby mode. + lpm_ldo_standby_operation_t pll2_ldo; ///< Configure the state of PLL2 LDO in standby mode. + lpm_ldo_standby_operation_t hoco_ldo; ///< Configure the state of HOCO LDO in standby mode. +} lpm_ldo_standby_cfg_t; + +/** User configuration structure, used in open function */ +typedef struct st_lpm_cfg +{ + /** Low Power Mode */ + lpm_mode_t low_power_mode; + + /** Bitwise list of sources to wake from deep sleep and standby mode */ + lpm_standby_wake_source_bits_t standby_wake_sources; + +#if BSP_FEATURE_ICU_HAS_WUPEN2 + lpm_standby_wake_source_bits_t standby_wake_sources_2; +#endif + +#if BSP_FEATURE_LPM_HAS_SNOOZE + + /** Snooze request source */ + lpm_snooze_request_t snooze_request_source; + + /** Bitwise list of snooze end sources */ + lpm_snooze_end_bits_t snooze_end_sources; + + #ifndef BSP_OVERRIDE_LPM_SNOOZE_CANCEL_SOURCES_T + + /** List of snooze cancel sources */ + lpm_snooze_cancel_t snooze_cancel_sources; + #else + lpm_snooze_cancel_source_bits_t snooze_cancel_sources; + #endif +#endif + + /** State of DTC in snooze mode, enabled or disabled */ + lpm_snooze_dtc_t dtc_state_in_snooze; +#if BSP_FEATURE_LPM_HAS_SBYCR_OPE + + /** Output port enabled/disabled in standby and deep standby */ + lpm_output_port_enable_t output_port_enable; +#endif +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + + /** IO port state in deep standby (maintained or reset) */ + lpm_io_port_t io_port_state; + + /** Internal power supply state in standby and deep standby (deepcut) */ + lpm_power_supply_t power_supply_state; + + /** Sources that can trigger exit from deep standby */ + lpm_deep_standby_cancel_source_bits_t deep_standby_cancel_source; + + /** Signal edges for the sources that can trigger exit from deep standby */ + lpm_deep_standby_cancel_edge_bits_t deep_standby_cancel_edge; +#endif + +#if BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE + /** Configure the soft start mode when waking from deep standby. */ + lpm_deep_standby_soft_start_mode_t deep_standby_soft_start_mode; +#endif + +#if BSP_FEATURE_LPM_HAS_PDRAMSCR || BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + + /** RAM retention configuration for deep sleep and standby modes. */ + lpm_ram_retention_t ram_retention_cfg; +#endif + +#if BSP_FEATURE_LPM_HAS_LDO_SKEEP + + /** Configure LDOs that are disabled in standby mode. */ + lpm_ldo_standby_cfg_t ldo_standby_cfg; +#endif + +#if BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT + + /** Flash mode in sleep mode or in snooze mode. */ + lpm_flash_mode_select_t lpm_flash_mode_select; +#endif + +#if BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE + + /** Startup speed of high-speed on-chip oscillator when exiting software standby mode or entering snooze mode. */ + lpm_hoco_startup_speed_t lpm_hoco_startup_speed; +#endif + +#if BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT + + /** SOSC setting in SSTBY mode or in SNOOZE mode. */ + lpm_standby_sosc_t lpm_standby_sosc; +#endif + + /** Placeholder for extension. */ + void const * p_extend; +} lpm_cfg_t; + +/** LPM control block. Allocate an instance specific control block to pass into the LPM API calls. + */ +typedef void lpm_ctrl_t; + +/** LPM driver structure. General LPM functions implemented at the HAL layer will follow this API. */ +typedef struct st_lpm_api +{ + /** Initialization function + **/ + + fsp_err_t (* open)(lpm_ctrl_t * const p_ctrl, lpm_cfg_t const * const p_cfg); + + /** Initialization function + **/ + fsp_err_t (* close)(lpm_ctrl_t * const p_ctrl); + + /** Configure a low power mode. + * + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + **/ + fsp_err_t (* lowPowerReconfigure)(lpm_ctrl_t * const p_ctrl, lpm_cfg_t const * const p_cfg); + + /** Enter low power mode (sleep/standby/deep standby) using WFI macro. + * Function will return after waking from low power mode. + **/ + fsp_err_t (* lowPowerModeEnter)(lpm_ctrl_t * const p_ctrl); + + /** Clear the IOKEEP bit after deep software standby. + **/ + fsp_err_t (* ioKeepClear)(lpm_ctrl_t * const p_ctrl); +} lpm_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_lpm_instance +{ + lpm_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + lpm_cfg_t const * const p_cfg; ///< Pointer to the configuration structure for this instance + lpm_api_t const * const p_api; ///< Pointer to the API structure for this instance +} lpm_instance_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup LPM_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lvd_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lvd_api.h new file mode 100644 index 0000000000..538ac51d47 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_lvd_api.h @@ -0,0 +1,279 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_MONITORING_INTERFACES + * @defgroup LVD_API Low Voltage Detection Interface + * @brief Interface for Low Voltage Detection + * + * @section LVD_API_SUMMARY Summary + * The LVD driver provides functions for configuring the LVD voltage monitors and detectors. + * + * + * @{ + **********************************************************************************************************************/ +#ifndef R_LVD_API_H +#define R_LVD_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/** Register definitions, common services, and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_LVD_PERIPHERAL_T + +/** Voltage detection level */ + +/** The thresholds supported by each MCU are in the MCU User's Manual as well as + * in the r_lvd module description on the stack tab of the RA project. */ +typedef enum +{ + LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V = 0x00UL, ///< 4.29V + LVD_THRESHOLD_MONITOR_1_LEVEL_4_16V = 0x01UL, ///< 4.16V + LVD_THRESHOLD_MONITOR_1_LEVEL_4_14V = 0x01UL, ///< 4.14V + LVD_THRESHOLD_MONITOR_1_LEVEL_4_03V = 0x02UL, ///< 4.03V + LVD_THRESHOLD_MONITOR_1_LEVEL_4_02V = 0x02UL, ///< 4.02V + LVD_THRESHOLD_MONITOR_1_LEVEL_3_86V = 0x03UL, ///< 3.86V + LVD_THRESHOLD_MONITOR_1_LEVEL_3_84V = 0x03UL, ///< 3.84V + LVD_THRESHOLD_MONITOR_1_LEVEL_3_10V = 0x04UL, ///< 3.10V + LVD_THRESHOLD_MONITOR_1_LEVEL_3_00V = 0x05UL, ///< 3.00V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_90V = 0x06UL, ///< 2.90V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_79V = 0x07UL, ///< 2.79V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_68V = 0x08UL, ///< 2.68V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_58V = 0x09UL, ///< 2.58V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_48V = 0x0AUL, ///< 2.48V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_20V = 0x0BUL, ///< 2.20V + LVD_THRESHOLD_MONITOR_1_LEVEL_1_96V = 0x0CUL, ///< 1.96V + LVD_THRESHOLD_MONITOR_1_LEVEL_1_86V = 0x0DUL, ///< 1.86V + LVD_THRESHOLD_MONITOR_1_LEVEL_1_75V = 0x0EUL, ///< 1.75V + LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V = 0x0FUL, ///< 1.65V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V = 0x11UL, ///< 2.99V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_92V = 0x12UL, ///< 2.92V + LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V = 0x13UL, ///< 2.85V + LVD_THRESHOLD_MONITOR_2_LEVEL_4_31V = 0x00UL, ///< 4.31V + LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V = 0x00UL, ///< 4.29V + LVD_THRESHOLD_MONITOR_2_LEVEL_4_17V = 0x01UL, ///< 4.17V + LVD_THRESHOLD_MONITOR_2_LEVEL_4_14V = 0x01UL, ///< 4.14V + LVD_THRESHOLD_MONITOR_2_LEVEL_4_03V = 0x02UL, ///< 4.03V + LVD_THRESHOLD_MONITOR_2_LEVEL_4_02V = 0x02UL, ///< 4.02V + LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V = 0x03UL, ///< 3.84V + LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V = 0x05UL, ///< 2.99V + LVD_THRESHOLD_MONITOR_2_LEVEL_2_92V = 0x06UL, ///< 2.92V + LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V = 0x07UL, ///< 2.85V + + LVD_THRESHOLD_EXLVDVBAT_LEVEL_3_1V = 0x06UL, ///< 3.1V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_9V = 0x05UL, ///< 2.9V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_8V = 0x04UL, ///< 2.8V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_7V = 0x03UL, ///< 2.7V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_6V = 0x02UL, ///< 2.6V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_4V = 0x01UL, ///< 2.4V + LVD_THRESHOLD_EXLVDVBAT_LEVEL_2_2V = 0x00UL, ///< 2.2V + + LVD_THRESHOLD_LVDVRTC_LEVEL_2_8V = 0x03UL, ///< 2.8V + LVD_THRESHOLD_LVDVRTC_LEVEL_2_6V = 0x02UL, ///< 2.6V + LVD_THRESHOLD_LVDVRTC_LEVEL_2_4V = 0x01UL, ///< 2.4V + LVD_THRESHOLD_LVDVRTC_LEVEL_2_2V = 0x00UL, ///< 2.2V + LVD_THRESHOLD_NOT_AVAILABLE = 0xFFUL, ///< Not Used +} lvd_threshold_t; +#endif + +/** Response types for handling threshold crossing event. */ +typedef enum e_lvd_response +{ + LVD_RESPONSE_NMI, ///< Non-maskable interrupt + LVD_RESPONSE_INTERRUPT, ///< Maskable interrupt + LVD_RESPONSE_RESET, ///< Reset on VCC-fall + LVD_RESPONSE_RESET_ON_RISING, ///< Reset on VCC-rise + LVD_RESPONSE_NONE, ///< No response, status must be requested via statusGet function +} lvd_response_t; + +/** The direction from which VCC must cross the threshold to trigger a detection (rising, falling, or both). */ +typedef enum e_lvd_voltage_slope +{ + LVD_VOLTAGE_SLOPE_RISING = 0, ///< When VCC >= Vdet2 (rise) is detected + LVD_VOLTAGE_SLOPE_FALLING = 1, ///< When VCC < Vdet2 (drop) is detected + LVD_VOLTAGE_SLOPE_BOTH = 2, ///< When drop and rise are detected +} lvd_voltage_slope_t; + +/** Sample clock divider, use LVD_SAMPLE_CLOCK_DISABLED to disable digital filtering */ +typedef enum e_lvd_sample_clock +{ + LVD_SAMPLE_CLOCK_LOCO_DIV_2 = 0, ///< Digital filter sample clock is LOCO divided by 2 + LVD_SAMPLE_CLOCK_LOCO_DIV_4 = 1, ///< Digital filter sample clock is LOCO divided by 4 + LVD_SAMPLE_CLOCK_LOCO_DIV_8 = 2, ///< Digital filter sample clock is LOCO divided by 8 + LVD_SAMPLE_CLOCK_LOCO_DIV_16 = 3, ///< Digital filter sample clock is LOCO divided by 16 + LVD_SAMPLE_CLOCK_DISABLED = -1, ///< Digital filter is disabled +} lvd_sample_clock_t; + +/** Negation delay of LVD reset signal follows reset or voltage in range */ +typedef enum e_lvd_negation_delay +{ + /** + * Negation follows a stabilization time (tLVDn) + * after VCC > Vdet1 is detected. + * If a transition to software standby or deep software + * standby is to be made, the only possible value for + * the RN bit is LVD_NEGATION_DELAY_FROM_VOLTAGE + */ + LVD_NEGATION_DELAY_FROM_VOLTAGE = 0, + + /** + * Negation follows a stabilization time (tLVDn) after + * assertion of the LVDn reset. + * If a transition to software standby or deep software + * standby is to be made, the only possible value for + * the RN bit is LVD_NEGATION_DELAY_FROM_VOLTAGE + */ + LVD_NEGATION_DELAY_FROM_RESET = 1, +} lvd_negation_delay_t; + +/** Threshold crossing detection (latched) */ +typedef enum e_lvd_threshold_crossing +{ + LVD_THRESHOLD_CROSSING_NOT_DETECTED = 0, ///< Threshold crossing has not been detected. + LVD_THRESHOLD_CROSSING_DETECTED = 1, ///< Threshold crossing has been detected. +} lvd_threshold_crossing_t; + +/** Instantaneous status of VCC (above or below threshold) */ +typedef enum e_lvd_current_state +{ + LVD_CURRENT_STATE_BELOW_THRESHOLD = 0, ///< VCC < threshold + LVD_CURRENT_STATE_ABOVE_THRESHOLD = 1, ///< VCC >= threshold or monitor is disabled +} lvd_current_state_t; + +/** + * Current state of a voltage monitor. + */ +typedef struct st_lvd_status +{ + /** Threshold crossing detection (latched) */ + lvd_threshold_crossing_t crossing_detected; + + /** Instantaneous status of monitored voltage (above or below threshold) */ + lvd_current_state_t current_state; +} lvd_status_t; + +/** LVD callback parameter definition */ +typedef struct st_lvd_callback_args +{ + uint32_t monitor_number; ///< Monitor number + lvd_current_state_t current_state; ///< Current state of the voltage monitor + void * p_context; ///< Placeholder for user data +} lvd_callback_args_t; + +/** LVD configuration structure */ +typedef struct st_lvd_cfg +{ + /** Monitor number, 1, 2, ... */ + uint32_t monitor_number; + + /** Threshold for out of range voltage detection */ + lvd_threshold_t voltage_threshold; + + /** Response on detecting a threshold crossing */ + lvd_response_t detection_response; + + /** Direction of voltage crossing that will trigger a detection (Rising Edge, Falling Edge, Both). */ + lvd_voltage_slope_t voltage_slope; + + /** Negation of LVD signal follows reset or voltage in range */ + lvd_negation_delay_t negation_delay; + + /** Sample clock divider, use LVD_SAMPLE_CLOCK_DISABLED to disable digital filtering */ + lvd_sample_clock_t sample_clock_divisor; + + /** Interrupt number. */ + IRQn_Type irq; + + /** Interrupt priority level. */ + uint8_t monitor_ipl; + + /** User function to be called from interrupt */ + void (* p_callback)(lvd_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in */ + void * p_context; + + /** Extension parameter for hardware specific settings */ + void const * p_extend; +} lvd_cfg_t; + +/** LVD control block. Allocate an instance specific control block to pass into the LVD API calls. + */ +typedef void lvd_ctrl_t; + +/** LVD driver API structure. + * LVD driver functions implemented at the HAL layer will adhere to this API. + */ +typedef struct st_lvd_api +{ + /** Initializes a low voltage detection driver according to the passed-in configuration structure. + * @param[in] p_ctrl Pointer to control structure for the driver instance + * @param[in] p_cfg Pointer to the configuration structure for the driver instance + **/ + fsp_err_t (* open)(lvd_ctrl_t * const p_ctrl, lvd_cfg_t const * const p_cfg); + + /** Get the current state of the monitor, (threshold crossing detected, voltage currently above or below threshold). + * Must be used if the peripheral was initialized with lvd_response_t set to LVD_RESPONSE_NONE. + * @param[in] p_ctrl Pointer to the control structure for the driver instance + * @param[in,out] p_lvd_status Pointer to a lvd_status_t structure + **/ + fsp_err_t (* statusGet)(lvd_ctrl_t * const p_ctrl, lvd_status_t * p_lvd_status); + + /** Clears the latched status of the monitor. + * Must be used if the peripheral was initialized with lvd_response_t set to LVD_RESPONSE_NONE. + * @param[in] p_ctrl Pointer to the control structure for the driver instance + **/ + fsp_err_t (* statusClear)(lvd_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the LVD control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(lvd_ctrl_t * const p_ctrl, void (* p_callback)(lvd_callback_args_t *), + void * const p_context, lvd_callback_args_t * const p_callback_memory); + + /** Disables the LVD peripheral. + * Closes the driver instance. + * @param[in] p_ctrl Pointer to the control structure for the driver instance + **/ + fsp_err_t (* close)(lvd_ctrl_t * const p_ctrl); +} lvd_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_lvd_instance +{ + lvd_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + lvd_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this interface instance + lvd_api_t const * p_api; ///< Pointer to the API structure for this interface instance +} lvd_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup LVD_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_cmd_types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_cmd_types.h new file mode 100644 index 0000000000..eb2f3dfe36 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_cmd_types.h @@ -0,0 +1,94 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_GRAPHICS_INTERFACES + * @defgroup MIPI_CMD_TYPES MIPI CMD Data Types + * @brief Common data types for MIPI CSI and DSI communication interfaces. + * + * @section MIPI_CMD_TYPES_SUMMARY Summary + * The MIPI CMD interface provides functionality involved with driving display panels over MIPI. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_MIPI_CMD_TYPES_H +#define R_MIPI_CMD_TYPES_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** MIPI CMD packet Data Type (commands) - See MIPI specification for additional information */ +typedef enum e_mipi_cmd_id +{ + MIPI_CMD_ID_V_SYNC_START = 0x01, ///< (Short) Sync Event, V Sync Start + MIPI_CMD_ID_V_SYNC_END = 0x11, ///< (Short) Sync Event, V Sync End + MIPI_CMD_ID_H_SYNC_START = 0x21, ///< (Short) Sync Event, H Sync Start + MIPI_CMD_ID_H_SYNC_END = 0x31, ///< (Short) Sync Event, H Sync End + + MIPI_CMD_ID_COMPRESSION_MODE = 0x07, ///< (Short) Compression Mode Command + MIPI_CMD_ID_END_OF_TRANSMISSION = 0x08, ///< (Short) End of Transmission packet (EoTp) + + MIPI_CMD_ID_COLOR_MODE_OFF = 0x02, ///< (Short) Color Mode (CM) Off Command + MIPI_CMD_ID_COLOR_MODE_ON = 0x12, ///< (Short) Color Mode (CM) On Command + MIPI_CMD_ID_SHUTDOWN_PERIPHERAL = 0x22, ///< (Short) Shut Down Peripheral Command + MIPI_CMD_ID_TURN_ON_PERIPHERAL = 0x32, ///< (Short) Turn On Peripheral Command + + MIPI_CMD_ID_GENERIC_SHORT_WRITE_0_PARAM = 0x03, ///< (Short) Generic Short WRITE, no parameters + MIPI_CMD_ID_GENERIC_SHORT_WRITE_1_PARAM = 0x13, ///< (Short) Generic Short WRITE, 1 parameter + MIPI_CMD_ID_GENERIC_SHORT_WRITE_2_PARAM = 0x23, ///< (Short) Generic Short WRITE, 2 parameters + + MIPI_CMD_ID_GENERIC_READ_REQUEST_0_PARAM = 0x04, ///< (Short) Generic READ, no parameters + MIPI_CMD_ID_GENERIC_READ_REQUEST_1_PARAM = 0x14, ///< (Short) Generic READ, 1 parameter + MIPI_CMD_ID_GENERIC_READ_REQUEST_2_PARAM = 0x24, ///< (Short) Generic READ, 2 parameters + + MIPI_CMD_ID_DCS_SHORT_WRITE_0_PARAM = 0x05, ///< (Short) DCS Short WRITE, no parameters + MIPI_CMD_ID_DCS_SHORT_WRITE_1_PARAM = 0x15, ///< (Short) DCS Short WRITE, 1 parameter + + MIPI_CMD_ID_DCS_READ = 0x06, ///< (Short) DCS READ, no parameters + MIPI_CMD_ID_EXECUTE_QUEUE = 0x16, ///< (Short) Execute Queue + + MIPI_CMD_ID_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, ///< (Short) Set Maximum Return Packet Size + + MIPI_CMD_ID_NULL_PACKET = 0x09, ///< (Long) Null Packet, no data + MIPI_CMD_ID_BLANKING_PACKET = 0x19, ///< (Long) Blanking Packet, no data + MIPI_CMD_ID_GENERIC_LONG_WRITE = 0x29, ///< (Long) Generic Long Write + MIPI_CMD_ID_DCS_LONG_WRITE = 0x39, ///< (Long) DCS Long Write/write_LUT Command Packet + + MIPI_CMD_ID_PICTURE_PARAMETER_SET = 0x0A, ///< (Long) Picture Parameter Set + MIPI_CMD_ID_COMPRESSED_PIXEL_STREAM = 0x0B, ///< (Long) Compressed Pixel Stream + + MIPI_CMD_ID_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0C, ///< (Long) Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2 Format + MIPI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR24 = 0x1C, ///< (Long) Packed Pixel Stream, 24-bit YCbCr, 4:2:2 Format + MIPI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR16 = 0x2C, ///< (Long) Packed Pixel Stream, 16-bit YCbCr, 4:2:2 Format + + MIPI_CMD_ID_PACKED_PIXEL_STREAM_30 = 0x0D, ///< (Long) Packed Pixel Stream, 30-bit RGB, 10-10-10 Format + MIPI_CMD_ID_PACKED_PIXEL_STREAM_36 = 0x1D, ///< (Long) Packed Pixel Stream, 36-bit RGB, 12-12-12 Format + MIPI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR12 = 0x3D, ///< (Long) Packed Pixel Stream, 12-bit YCbCr, 4:2:0 Format + + MIPI_CMD_ID_PACKED_PIXEL_STREAM_16 = 0x0E, ///< (Long) Packed Pixel Stream, 16-bit RGB, 5-6-5 Format + MIPI_CMD_ID_PACKED_PIXEL_STREAM_18 = 0x1E, ///< (Long) Packed Pixel Stream, 18-bit RGB, 6-6-6 Format + MIPI_CMD_ID_LOOSELY_PACKED_PIXEL_STREAM_18 = 0x2E, ///< (Long) Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format + MIPI_CMD_ID_PACKED_PIXEL_STREAM_24 = 0x3E, ///< (Long) Packed Pixel Stream, 24-bit RGB, 8-8-8 Format +} mipi_cmd_id_t; + +/* @} (end defgroup MIPI_CMD_TYPES) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_csi_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_csi_api.h new file mode 100644 index 0000000000..3cc3d61dda --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_csi_api.h @@ -0,0 +1,178 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_GRAPHICS_INTERFACES + * @defgroup MIPI_CSI_API MIPI CSI Interface + * @brief Interface for MIPI CSI communications. + * + * @section MIPI_CSI_API_SUMMARY Summary + * The MIPI CSI interface provides functionality involved with driving display panels over MIPI. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_MIPI_CSI_API_H +#define R_MIPI_CSI_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_mipi_cmd_types.h" +#include "r_mipi_csi_cfg.h" + +#include "r_mipi_phy.h" + +#if __has_include("r_mipi_csi_device_types.h") + #include "r_mipi_csi_device_types.h" +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Type definitions + **********************************************************************************************************************/ + +/** MIPI CSI State type */ +typedef enum e_mipi_csi_state +{ + MIPI_CSI_STATE_NONE = 0, ///< MIPI CSI State Uninitialized + MIPI_CSI_STATE_IDLE = 1, ///< MIPI CSI State Idle + MIPI_CSI_STATE_RECEIVING = 2, ///< MIPI CSI State Reception in progress +} mipi_csi_state_t; + +/** MIPI CSI Data Lane Error IDs */ +typedef enum e_mipi_csi_data_lane_error +{ + MIPI_CSI_DATA_LANE_ERROR_ERR_SOTHS = 0X01, ///< High-speed SOT leader sequence is corrupted + MIPI_CSI_DATA_LANE_ERROR_ERR_SOTSYNCHS = 0X02, ///< High-speed SOT synchronization error + MIPI_CSI_DATA_LANE_ERROR_ERR_CONTROL = 0X04, ///< Incorrect line sequence detected + MIPI_CSI_DATA_LANE_ERROR_ERR_ESC = 0X80, ///< Escape entry error +} mipi_csi_data_lane_error_t; + +/** MIPI CSI Short Packet Type */ +typedef union st_mipi_csi_short_packet +{ + struct + { + uint32_t data : 16; ///< Short Packet Data + uint32_t data_type : 6; ///< Short Packet Data Type + uint32_t : 2; + uint32_t virtual_channel : 4; ///< Short Packet Virtual Channel + uint32_t : 4; + } bits; + uint32_t mask; +} mipi_csi_short_packet_t; + +/** MIPI CSI status type */ +typedef struct st_mipi_csi_status +{ + mipi_csi_state_t state; ///< CSI State +} mipi_csi_status_t; + +/** MIPI CSI Event ID */ +typedef enum e_mipi_csi_event +{ + MIPI_CSI_EVENT_FRAME_DATA, ///< Virtual Channel Frame Receive Event + MIPI_CSI_EVENT_DATA_LANE, ///< Data Lane Event + MIPI_CSI_EVENT_VIRTUAL_CHANNEL, ///< Virtual Channel Event + MIPI_CSI_EVENT_POWER, ///< Power Management Event + MIPI_CSI_EVENT_SHORT_PACKET_FIFO, ///< Generic Short Packet Event +} mipi_csi_event_t; + +/** MIPI CSI Callback Arguments */ +typedef struct st_mipi_csi_callback_args +{ + mipi_csi_event_t event; ///< Event code + uint8_t event_idx; ///< Index for event type, if applicable + mipi_csi_event_data_t event_data; ///< Data correspondiong to event code + void * p_context; ///< Context provided to user during callback +} mipi_csi_callback_args_t; + +/** MIPI CSI main configuration structure */ +typedef struct st_mipi_csi_cfg +{ + mipi_phy_instance_t const * p_mipi_phy_instance; ///< Pointer to mipi physical layer instance + + mipi_csi_ctrl_data_t ctrl_data; ///< Control register data + mipi_csi_option_data_t option_data; ///< Option register data + mipi_csi_interrupt_cfg_t interrupt_cfg; ///< Interrupt configuration + + /** Callback configuration */ + void (* p_callback)(mipi_csi_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /** Pointer to display peripheral specific configuration */ + void const * p_extend; ///< MIPI hardware dependent configuration +} mipi_csi_cfg_t; + +/** MIPI CSI control block. Allocate an instance specific control block to pass into the MIPI CSI API calls. */ +typedef void mipi_csi_ctrl_t; + +/** Shared Interface definition for MIPI CSI peripheral */ +typedef struct st_mipi_csi_api +{ + /** Open MIPI CSI device. + * + * @param[in,out] p_ctrl Pointer to MIPI CSI interface control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to MIPI CSI configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(mipi_csi_ctrl_t * const p_ctrl, mipi_csi_cfg_t const * const p_cfg); + + /** Close MIPI CSI device. + * + * @param[in] p_ctrl Pointer to MIPI CSI interface control block. + */ + fsp_err_t (* close)(mipi_csi_ctrl_t * const p_ctrl); + + /** Start pixel data output. + * + * @param[in] p_ctrl Pointer to MIPI CSI interface control block. + */ + fsp_err_t (* start)(mipi_csi_ctrl_t * const p_ctrl); + + /** Stop pixel data output. + * + * @param[in] p_ctrl Pointer to MIPI CSI interface control block. + */ + fsp_err_t (* stop)(mipi_csi_ctrl_t * const p_ctrl); + + /** Read Short Packet + * + * @param[in] p_ctrl Pointer to MIPI CSI interface control block. + * @param[out] p_data Pointer to MIPI CSI data structure to read to + */ + fsp_err_t (* read)(mipi_csi_ctrl_t * const p_ctrl, mipi_csi_short_packet_t * p_data); + + /** Get status of MIPI link. + * + * @param[in] p_ctrl Pointer to MIPI CSI interface control block. + * @param[out] p_status Pointer to MIPI CSI interface status structure. + */ + fsp_err_t (* statusGet)(mipi_csi_ctrl_t * const p_ctrl, mipi_csi_status_t * p_status); +} mipi_csi_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_mipi_csi_instance +{ + mipi_csi_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + mipi_csi_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + mipi_csi_api_t const * p_api; ///< Pointer to the API structure for this instance +} mipi_csi_instance_t; + +/* @} (end defgroup MIPI_CSI_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_dsi_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_dsi_api.h new file mode 100644 index 0000000000..85b226baaf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_mipi_dsi_api.h @@ -0,0 +1,550 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_GRAPHICS_INTERFACES + * @defgroup MIPI_DSI_API MIPI DSI Interface + * @brief Interface for MIPI DSI communications. + * + * @section MIPI_DSI_API_SUMMARY Summary + * The MIPI DSI interface provides functionality involved with driving display panels over MIPI. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_MIPI_DSI_API_H +#define R_MIPI_DSI_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_mipi_cmd_types.h" +#include "r_mipi_dsi_cfg.h" + +#include "r_mipi_phy.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** DEPRECATED - MIPI DSI packet Data Type (commands) - See MIPI specification for additional information + * - The use of mipi_dsi_cmd_id_t has been deprecated and will be fully relpaced with the use of + * mipi_cmd_t in a future release. + */ +typedef enum e_mipi_dsi_cmd_id +{ + MIPI_DSI_CMD_ID_V_SYNC_START = 0x01, ///< (Short) Sync Event, V Sync Start + MIPI_DSI_CMD_ID_V_SYNC_END = 0x11, ///< (Short) Sync Event, V Sync End + MIPI_DSI_CMD_ID_H_SYNC_START = 0x21, ///< (Short) Sync Event, H Sync Start + MIPI_DSI_CMD_ID_H_SYNC_END = 0x31, ///< (Short) Sync Event, H Sync End + + MIPI_DSI_CMD_ID_COMPRESSION_MODE = 0x07, ///< (Short) Compression Mode Command + MIPI_DSI_CMD_ID_END_OF_TRANSMISSION = 0x08, ///< (Short) End of Transmission packet (EoTp) + + MIPI_DSI_CMD_ID_COLOR_MODE_OFF = 0x02, ///< (Short) Color Mode (CM) Off Command + MIPI_DSI_CMD_ID_COLOR_MODE_ON = 0x12, ///< (Short) Color Mode (CM) On Command + MIPI_DSI_CMD_ID_SHUTDOWN_PERIPHERAL = 0x22, ///< (Short) Shut Down Peripheral Command + MIPI_DSI_CMD_ID_TURN_ON_PERIPHERAL = 0x32, ///< (Short) Turn On Peripheral Command + + MIPI_DSI_CMD_ID_GENERIC_SHORT_WRITE_0_PARAM = 0x03, ///< (Short) Generic Short WRITE, no parameters + MIPI_DSI_CMD_ID_GENERIC_SHORT_WRITE_1_PARAM = 0x13, ///< (Short) Generic Short WRITE, 1 parameter + MIPI_DSI_CMD_ID_GENERIC_SHORT_WRITE_2_PARAM = 0x23, ///< (Short) Generic Short WRITE, 2 parameters + + MIPI_DSI_CMD_ID_GENERIC_READ_REQUEST_0_PARAM = 0x04, ///< (Short) Generic READ, no parameters + MIPI_DSI_CMD_ID_GENERIC_READ_REQUEST_1_PARAM = 0x14, ///< (Short) Generic READ, 1 parameter + MIPI_DSI_CMD_ID_GENERIC_READ_REQUEST_2_PARAM = 0x24, ///< (Short) Generic READ, 2 parameters + + MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM = 0x05, ///< (Short) DCS Short WRITE, no parameters + MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM = 0x15, ///< (Short) DCS Short WRITE, 1 parameter + + MIPI_DSI_CMD_ID_DCS_READ = 0x06, ///< (Short) DCS READ, no parameters + MIPI_DSI_CMD_ID_EXECUTE_QUEUE = 0x16, ///< (Short) Execute Queue + + MIPI_DSI_CMD_ID_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, ///< (Short) Set Maximum Return Packet Size + + MIPI_DSI_CMD_ID_NULL_PACKET = 0x09, ///< (Long) Null Packet, no data + MIPI_DSI_CMD_ID_BLANKING_PACKET = 0x19, ///< (Long) Blanking Packet, no data + MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE = 0x29, ///< (Long) Generic Long Write + MIPI_DSI_CMD_ID_DCS_LONG_WRITE = 0x39, ///< (Long) DCS Long Write/write_LUT Command Packet + + MIPI_DSI_CMD_ID_PICTURE_PARAMETER_SET = 0x0A, ///< (Long) Picture Parameter Set + MIPI_DSI_CMD_ID_COMPRESSED_PIXEL_STREAM = 0x0B, ///< (Long) Compressed Pixel Stream + + MIPI_DSI_CMD_ID_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0C, ///< (Long) Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2 Format + MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR24 = 0x1C, ///< (Long) Packed Pixel Stream, 24-bit YCbCr, 4:2:2 Format + MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR16 = 0x2C, ///< (Long) Packed Pixel Stream, 16-bit YCbCr, 4:2:2 Format + + MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_30 = 0x0D, ///< (Long) Packed Pixel Stream, 30-bit RGB, 10-10-10 Format + MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_36 = 0x1D, ///< (Long) Packed Pixel Stream, 36-bit RGB, 12-12-12 Format + MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR12 = 0x3D, ///< (Long) Packed Pixel Stream, 12-bit YCbCr, 4:2:0 Format + + MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_16 = 0x0E, ///< (Long) Packed Pixel Stream, 16-bit RGB, 5-6-5 Format + MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_18 = 0x1E, ///< (Long) Packed Pixel Stream, 18-bit RGB, 6-6-6 Format + MIPI_DSI_CMD_ID_LOOSELY_PACKED_PIXEL_STREAM_18 = 0x2E, ///< (Long) Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format + MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_24 = 0x3E, ///< (Long) Packed Pixel Stream, 24-bit RGB, 8-8-8 Format +} mipi_dsi_cmd_id_t; + +/** MIPI DCS ID types - See MIPI DCS specification for additional information */ +typedef enum e_mipi_dsi_dcs_id +{ + MIPI_DSI_DCS_ID_ENTER_IDLE_MODE = 0x39, ///< Enter idle mode + MIPI_DSI_DCS_ID_ENTER_INVERT_MODE = 0x21, ///< Displayed image colors inverted + MIPI_DSI_DCS_ID_ENTER_NORMAL_MODE = 0x13, ///< Whole display area used for image + MIPI_DSI_DCS_ID_ENTER_PARTIAL_MODE = 0x12, ///< Part of display area used for image + MIPI_DSI_DCS_ID_ENTER_SLEEP_MODE = 0x10, ///< Power off the display panel + MIPI_DSI_DCS_ID_EXIT_IDLE_MODE = 0x38, ///< Full color depth used + MIPI_DSI_DCS_ID_EXIT_INVERT_MODE = 0x20, ///< Displayed image colors not inverted + MIPI_DSI_DCS_ID_EXIT_SLEEP_MODE = 0x11, ///< Power on the display panel + MIPI_DSI_DCS_ID_GET_3D_CONTROL = 0x3F, ///< Get display module 3D mode + MIPI_DSI_DCS_ID_GET_ADDRESS_MODE = 0x0B, ///< Get data order for transfers from host to the display device + MIPI_DSI_DCS_ID_GET_BLUE_CHANNEL = 0x08, ///< Get blue component of pixel at 0,0 + MIPI_DSI_DCS_ID_GET_CABC_MIN_BRIGHTNESS = 0x5F, ///< Get current minimum brightness level of the active CABC mode + MIPI_DSI_DCS_ID_GET_COMPRESSION_MODE = 0x03, ///< Get current compression mode + MIPI_DSI_DCS_ID_GET_CONTROL_DISPLAY = 0x54, ///< Get control display mode + MIPI_DSI_DCS_ID_GET_DIAGNOSTIC_RESULT = 0x0F, ///< Get peripheral self-diagnostic result + MIPI_DSI_DCS_ID_GET_DISPLAY_BRIGHTNESS = 0x52, ///< Get current display brightness level + MIPI_DSI_DCS_ID_GET_DISPLAY_MODE = 0x0D, ///< Get current display mode from the peripheral + MIPI_DSI_DCS_ID_GET_DSI_MODE = 0x70, ///< Get DSI operation mode + MIPI_DSI_DCS_ID_GET_ERROR_COUNT_ON_DSI = 0x05, ///< Get number of corrupted packets on DSI + MIPI_DSI_DCS_ID_GET_GREEN_CHANNEL = 0x07, ///< Get green component of pixel at 0,0 + MIPI_DSI_DCS_ID_GET_IMAGE_CHECKSUM_CT = 0x15, ///< Returns checksum of frame of color-transformed pixel data + MIPI_DSI_DCS_ID_GET_IMAGE_CHECKSUM_RGB = 0x14, ///< Returns checksum of frame of RGB pixel data + MIPI_DSI_DCS_ID_GET_PIXEL_FORMAT = 0x0C, ///< Get current pixel format + MIPI_DSI_DCS_ID_GET_POWER_MODE = 0x0A, ///< Get current power mode + MIPI_DSI_DCS_ID_GET_POWER_SAVE = 0x56, ///< Get current power-save mode + MIPI_DSI_DCS_ID_GET_RED_CHANNEL = 0x06, ///< Get red component of pixel at 0,0 + MIPI_DSI_DCS_ID_GET_SCANLINE = 0x45, ///< Get current scanline + MIPI_DSI_DCS_ID_GET_SIGNAL_MODE = 0x0E, ///< Get display module signaling mode + MIPI_DSI_DCS_ID_NOP = 0x00, ///< No operation + MIPI_DSI_DCS_ID_READ_ACMD = 0x62, ///< Perform read access to the ACMD registers + MIPI_DSI_DCS_ID_READ_DDB_CONTINUE = 0xA8, ///< Continue reading the DDB from the last read location + MIPI_DSI_DCS_ID_READ_DDB_START = 0xA1, ///< Read the DDB from the provided location + MIPI_DSI_DCS_ID_READ_DSE_MAILBOX = 0x57, ///< Read access to the registers of the DSE read or write control mailbox + MIPI_DSI_DCS_ID_READ_MEMORY_CONTINUE = 0x3E, ///< Read image data from peripheral, continuing after last read + MIPI_DSI_DCS_ID_READ_MEMORY_START = 0x2E, ///< Read image data from the peripheral to the host + MIPI_DSI_DCS_ID_READ_PPS_CONTINUE = 0xA9, ///< Continue reading the specified length of PPS data + MIPI_DSI_DCS_ID_READ_PPS_START = 0xA2, ///< Read PPS data + MIPI_DSI_DCS_ID_SET_3D_CONTROL = 0x3D, ///< 3D is used on the display panel + MIPI_DSI_DCS_ID_SET_ADDRESS_MODE = 0x36, ///< Set data order for transfers from host to peripheral + MIPI_DSI_DCS_ID_SET_ARP_OFF = 0x60, ///< Disable ARP + MIPI_DSI_DCS_ID_SET_ARP_ON = 0x61, ///< Enable ARP and set T2 timer + MIPI_DSI_DCS_ID_SET_CABC_MIN_BRIGHTNESS = 0x5E, ///< Set minimum brightness level for CABC mode + MIPI_DSI_DCS_ID_SET_COLUMN_ADDRESS = 0x2A, ///< Set column extent + MIPI_DSI_DCS_ID_SET_DISPLAY_BRIGHTNESS = 0x51, ///< Set display brightness level + MIPI_DSI_DCS_ID_SET_DISPLAY_OFF = 0x28, ///< Blank the display device + MIPI_DSI_DCS_ID_SET_DISPLAY_ON = 0x29, ///< Show image on display device + MIPI_DSI_DCS_ID_SET_DSI_MODE = 0x71, ///< Set DSI operation mode + MIPI_DSI_DCS_ID_SET_GAMMA_CURVE = 0x26, ///< Select gamma curve used by display + MIPI_DSI_DCS_ID_SET_PAGE_ADDRESS = 0x2B, ///< Set page extent + MIPI_DSI_DCS_ID_SET_PARTIAL_COLUMNS = 0x31, ///< Define the number of columns in the partial display area + MIPI_DSI_DCS_ID_SET_PARTIAL_ROWS = 0x30, ///< Define the number of rows in the partial display area + MIPI_DSI_DCS_ID_SET_PIXEL_FORMAT = 0x3A, ///< Define how many bits per pixel are used + MIPI_DSI_DCS_ID_SET_SCROLL_AREA = 0x33, ///< Define vertical scrolling and fixed area + MIPI_DSI_DCS_ID_SET_SCROLL_START = 0x37, ///< Define vertical scrolling starting point + MIPI_DSI_DCS_ID_SET_TEAR_OFF = 0x34, ///< Sync information not sent from the display module to the host + MIPI_DSI_DCS_ID_SET_TEAR_ON = 0x35, ///< Sync information is sent from the display module to the host + MIPI_DSI_DCS_ID_SET_TEAR_SCANLINE = 0x44, ///< Sync information is sent from display to the host when display refresh reaches profivided scan line + MIPI_DSI_DCS_ID_SET_VSYNC_TIMING = 0x40, ///< Set VSYNC timing to the specified length of PPS data + MIPI_DSI_DCS_ID_SOFT_RESET = 0x01, ///< Software reset + MIPI_DSI_DCS_ID_WRITE_ACMD = 0x63, ///< Write access to ACMD registers + MIPI_DSI_DCS_ID_WRITE_CONTROL_DISPLAY = 0x53, ///< Write control mode of display brightness + MIPI_DSI_DCS_ID_WRITE_DSE_MAILBOX = 0x58, ///< Write registers of DSE read or write control mailbox + MIPI_DSI_DCS_ID_WRITE_LUT = 0x2D, ///< Fill peripheral look-up table with provided data + MIPI_DSI_DCS_ID_WRITE_MEMORY_CONTINUE = 0x3C, ///< Continue image information transfer from last address + MIPI_DSI_DCS_ID_WRITE_MEMORY_START = 0x2C, ///< Transfer image information from host to peripheral + MIPI_DSI_DCS_ID_WRITE_POWER_SAVE = 0x55, ///< Writes power save mode +} mipi_dsi_dcs_id_t; + +/** MIPI DSI Video Data type */ +typedef enum e_mipi_dsi_video_data +{ + MIPI_DSI_VIDEO_DATA_16RGB_PIXEL_STREAM = 0x0E, ///< 16-bit RGB Packed Pixel Stream + MIPI_DSI_VIDEO_DATA_18RGB_PIXEL_STREAM = 0x1E, ///< 18-bit RGB Packed Pixel Stream + MIPI_DSI_VIDEO_DATA_18RGB_LOOSELY_PIXEL_STREAM = 0x2E, ///< 18-bit RGB Loosely Packed Pixel Stream + MIPI_DSI_VIDEO_DATA_24RGB_PIXEL_STREAM = 0x3E, ///< 24-bit RGB Packed Pixel Stream +} mipi_dsi_video_data_t; + +/** MIPI DSI Acknowledge and Error type */ +typedef enum e_mipi_dsi_ack_err +{ + MIPI_DSI_ACK_ERR_NONE = 0x0000, ///< No Errors + MIPI_DSI_ACK_ERR_SOT_ERROR = 0x0001, ///< SoT Error + MIPI_DSI_ACK_ERR_SOT_SYNC_ERROR = 0x0002, ///< SoT Sync Error + MIPI_DSI_ACK_ERR_EOT_SYNC_ERROR = 0x0004, ///< EoT Sync Error + MIPI_DSI_ACK_ERR_ESCAPE_ENTRY_ERROR = 0x0008, ///< Escape Mode Entry Error + MIPI_DSI_ACK_ERR_LOW_POWER_SYNC_ERROR = 0x0010, ///< Low-Power Transmit Sync Error + MIPI_DSI_ACK_ERR_PERIPHERAL_TIMEOUT_ERROR = 0x0020, ///< Peripheral Timeout Error + MIPI_DSI_ACK_ERR_FALSE_CONTROL_ERROR = 0x0040, ///< False Control Error + MIPI_DSI_ACK_ERR_CONTENTION_DETECTED = 0x0080, ///< Contention Detected Error + MIPI_DSI_ACK_ERR_ECC_SINGLE = 0x0100, ///< ECC Error, single-bit + MIPI_DSI_ACK_ERR_ECC_MULTI = 0x0200, ///< ECC Error, multi-bit + MIPI_DSI_ACK_ERR_CKSM_ERROR = 0x0400, ///< Checksum Error (Long packet only) + MIPI_DSI_ACK_ERR_DSI_DATA_ERROR = 0x0800, ///< DSI Data Type Not Recognized + MIPI_DSI_ACK_ERR_DSI_VC_ID_ERROR = 0x1000, ///< DSI VC ID Invalid + MIPI_DSI_ACK_ERR_INVALID_TX_LEN = 0x2000, ///< Invalid Transmission Length + MIPI_DSI_ACK_ERR_DSI_PROTOCOL_VIOLATION = 0x8000, ///< DSI Protocol Violation +} mipi_dsi_ack_err_t; + +/* MIPI DSI Virtual Channel ID Type*/ +typedef enum e_mipi_dsi_vc +{ + MIPI_DSI_VC_NONE = 0x0, ///< No channels selected + MIPI_DSI_VC_0 = 0x1, ///< Virtual channel 0 + MIPI_DSI_VC_1 = 0x2, ///< Virtual channel 1 + MIPI_DSI_VC_2 = 0x4, ///< Virtual channel 2 + MIPI_DSI_VC_3 = 0x8, ///< Virtual channel 3 +} mipi_dsi_vc_t; + +/** MIPI DSI Message Flags */ +typedef enum e_mipi_dsi_cmd_flag +{ + MIPI_DSI_CMD_FLAG_NONE = 0x00, ///< No flags + MIPI_DSI_CMD_FLAG_BTA = 0x01, ///< Assert bus turnaround at end of transfer + MIPI_DSI_CMD_FLAG_BTA_READ = 0x02, ///< Assert bus turnaround followed by read request (No WRITE request before BTA) + MIPI_DSI_CMD_FLAG_BTA_NO_WRITE = 0x03, ///< Immediately assert bus turnaround (No WRITE request before BTA) + MIPI_DSI_CMD_FLAG_AUX_OPERATION = 0x20, ///< Execute auxiliary operation command + MIPI_DSI_CMD_FLAG_ACT_CODE_RESET_TRIGGER = 0x20, ///< Send action code reset trigger message. + MIPI_DSI_CMD_FLAG_ACT_CODE_INITIAL_SKEW_CAL = 0x24, ///< Send action code initial skew calibration message. + MIPI_DSI_CMD_FLAG_ACT_CODE_PERIODIC_SKEW_CAL = 0x25, ///< Send action code periodic skew message. + MIPI_DSI_CMD_FLAG_ACT_CODE_NO_OPERATION = 0x28, ///< Send action code NOOP message. + MIPI_DSI_CMD_FLAG_LOW_POWER = 0x40, ///< Transmit in low-power mode +} mipi_dsi_cmd_flag_t; + +/** MIPI DSI event codes */ +typedef enum e_mipi_dsi_event +{ + MIPI_DSI_EVENT_SEQUENCE_0, ///< Sequence 0 event (Low-Power) + MIPI_DSI_EVENT_SEQUENCE_1, ///< Sequence 1 event (High-Speed) + MIPI_DSI_EVENT_VIDEO, ///< Video event + MIPI_DSI_EVENT_RECEIVE, ///< Receive event + MIPI_DSI_EVENT_FATAL, ///< Fatal event + MIPI_DSI_EVENT_PHY, ///< Physical layer event + + /* Software triggered events - To allow application specific processing */ + MIPI_DSI_EVENT_POST_OPEN, ///< Interface has been opened. Perform post-open application processing + MIPI_DSI_EVENT_PRE_START, ///< Video is about to start. Perform pre-video application processing +} mipi_dsi_event_t; + +/** MIPI DSI Sequence status */ +typedef enum e_mipi_dsi_sequence_status +{ + MIPI_DSI_SEQUENCE_STATUS_NONE = 0X00000000, ///< Sequence status not set + MIPI_DSI_SEQUENCE_STATUS_RUNNING = 0x00000004, ///< Sequence operation in progress + MIPI_DSI_SEQUENCE_STATUS_ACTIONS_FINISHED = 0x00000010, ///< All descriptor actions finished + MIPI_DSI_SEQUENCE_STATUS_DESCRIPTORS_FINISHED = 0x00000100, ///< All descriptors finished + MIPI_DSI_SEQUENCE_STATUS_DESCRIPTOR_ABORT = 0x00010000, ///< Descriptor abort interrupt + MIPI_DSI_SEQUENCE_STATUS_SIZE_ERROR = 0x00080000, ///< Packet size error + MIPI_DSI_SEQUENCE_STATUS_TX_INTERNAL_BUS_ERROR = 0x01000000, ///< Tx internal bus error + MIPI_DSI_SEQUENCE_STATUS_RX_FATAL_ERROR = 0x04800000, ///< Receive fatal error + MIPI_DSI_SEQUENCE_STATUS_RX_FAIL = 0x08000000, ///< Receive fail + MIPI_DSI_SEQUENCE_STATUS_RX_PACKET_DATA_FAIL = 0x10000000, ///< Receive packet data fail + MIPI_DSI_SEQUENCE_STATUS_RX_CORRECTABLE_ERROR = 0x20000000, ///< Receive correctable error + MIPI_DSI_SEQUENCE_STATUS_RX_ACK_AND_ERROR = 0x40000000, ///< Receive acknowledge and error report +} mipi_dsi_sequence_status_t; + +/** MIPI DSI video status errors */ +typedef enum e_mipi_dsi_video_status +{ + MIPI_DSI_VIDEO_STATUS_NONE = 0x00000000, ///< Video status not set + MIPI_DSI_VIDEO_STATUS_START = 0x00000001, ///< Video started event + MIPI_DSI_VIDEO_STATUS_STOP = 0x00000002, ///< Video stopped event + MIPI_DSI_VIDEO_STATUS_RUNNING = 0x00000004, ///< Video running status + MIPI_DSI_VIDEO_STATUS_READY = 0x00000008, ///< Video ready event + MIPI_DSI_VIDEO_STATUS_TIMING_ERROR = 0x00100000, ///< Video timing error event + MIPI_DSI_VIDEO_STATUS_UNDERFLOW = 0x00400000, ///< Video buffer underflow event + MIPI_DSI_VIDEO_STATUS_OVERFLOW = 0x00800000, ///< Video buffer overflow event +} mipi_dsi_video_status_t; + +/** MIPI DSI receive status errors */ +typedef enum e_mipi_dsi_receive_status +{ + MIPI_DSI_RECEIVE_STATUS_NONE = 0x00000000, ///< Receive status not set + MIPI_DSI_RECEIVE_STATUS_BTA_REQUEST_END = 0x00000001, ///< Receive BTA request end + MIPI_DSI_RECEIVE_STATUS_LP_RX_HOST_TIMEOUT = 0x00000002, ///< Receive low power receive timeout + MIPI_DSI_RECEIVE_STATUS_BTA_ACK_TIMEOUT = 0x00000004, ///< Receive BTA ack timeout + MIPI_DSI_RECEIVE_STATUS_RESPONSE_PACKET = 0x00000100, ///< Receive response + MIPI_DSI_RECEIVE_STATUS_EOTP = 0x00000400, ///< Receive end of transmission packet + MIPI_DSI_RECEIVE_STATUS_TEARING_TRIGGER = 0x00002000, ///< Receive tearing trigger + MIPI_DSI_RECEIVE_STATUS_ACK_TRIGGER = 0x00004000, ///< Receive ack trigger + MIPI_DSI_RECEIVE_STATUS_TEARING_DETECT = 0x00008000, ///< Receive tearing detect + MIPI_DSI_RECEIVE_STATUS_MALFORM_ERROR = 0x00010000, ///< Receive malform error + MIPI_DSI_RECEIVE_STATUS_ECC_MULTI = 0x00020000, ///< Receive ecc multi-bit error + MIPI_DSI_RECEIVE_STATUS_UNEXPECTED_PACKET = 0x00040000, ///< Receive unexpected packet + MIPI_DSI_RECEIVE_STATUS_WORD_COUNT = 0x00100000, ///< Receive word count + MIPI_DSI_RECEIVE_STATUS_CRC = 0x00200000, ///< Receive crc error + MIPI_DSI_RECEIVE_STATUS_INTERNAL_BUS = 0x00400000, ///< Receive internal bus error + MIPI_DSI_RECEIVE_STATUS_BUFFER_OVERFLOW = 0x00800000, ///< Receive buffer overflow + MIPI_DSI_RECEIVE_STATUS_TIMEOUT = 0x01000000, ///< Receive timeout + MIPI_DSI_RECEIVE_STATUS_NO_RESPONSE = 0x02000000, ///< Receive no response + MIPI_DSI_RECEIVE_STATUS_PACKET_SIZE = 0x04000000, ///< Receive packet size error + MIPI_DSI_RECEIVE_STATUS_ECC_SINGLE = 0x10000000, ///< Receive ecc single bit error + MIPI_DSI_RECEIVE_STATUS_ACK_AND_ERROR = 0x40000000, ///< Receive ack and error +} mipi_dsi_receive_status_t; + +/** MIPI DSI fatal status errors */ +typedef enum e_mipi_dsi_fatal_status +{ + MIPI_DSI_FATAL_STATUS_NONE = 0x00000000, ///< Fatal status not set + MIPI_DSI_FATAL_STATUS_HS_TX_TIMEOUT = 0x00000001, ///< Fatal high speed transmit timeout + MIPI_DSI_FATAL_STATUS_LP_RX_TIMEOUT = 0x00000002, ///< Fatal low power receive timeout + MIPI_DSI_FATAL_STATUS_BTA_ACK_TIMEOUT = 0x00000004, ///< Fatal BTA ack timeout + MIPI_DSI_FATAL_STATUS_ESCAPE_ENTRY_ERROR = 0x00010000, ///< Fatal escape mode entry error + MIPI_DSI_FATAL_STATUS_LPDT_SYNC_ERROR = 0x00020000, ///< Fatal low power data transmission synchronization error + MIPI_DSI_FATAL_STATUS_CTRL_ERROR = 0x00040000, ///< Fatal control error + MIPI_DSI_FATAL_STATUS_LP0_CONTENTION_DETECT = 0x00080000, ///< Fatal lane 0 low power contention detect + MIPI_DSI_FATAL_STATUS_LP1_CONTENTION_DETECT = 0x00100000, ///< Fatal lane 1 low power contention detect + MIPI_DSI_FATAL_STATUS_LP0_CONTENTION = 0x80000000, ///< Fatal lane 0 low power contention status + MIPI_DSI_FATAL_STATUS_LP1_CONTENTION = 0x10000000, ///< Fatal lane 1 low power contention status +} mipi_dsi_fatal_status_t; + +/** MIPI DSI physical lane status */ +typedef enum e_mipi_dsi_phy_status +{ + MIPI_DSI_PHY_STATUS_NONE = 0x00000000, ///< Physical lane status not set + MIPI_DSI_PHY_STATUS_ULP_NOT_ACTIVE = 0x00000001, ///< Physical lane ULP not active + MIPI_DSI_PHY_STATUS_CLOCK_LANE_STOP = 0x00000002, ///< Clock lane in stopped state + MIPI_DSI_PHY_STATUS_DATA_LANE0_LP_RX = 0x00000004, ///< Data lane low power receive mode + MIPI_DSI_PHY_STATUS_DATA_LANE0_ULP_RX = 0x00000008, ///< Data lane ultra low power receive mode + MIPI_DSI_PHY_STATUS_DATA_LANE0_NOT_ULP = 0x00000010, ///< Data lane 0 not in ULP mode + MIPI_DSI_PHY_STATUS_DATA_LANE1_NOT_ULP = 0x00000020, ///< Data lane 1 not in ULP mode + MIPI_DSI_PHY_STATUS_DATA_LANE2_NOT_ULP = 0x00000040, ///< Data lane 2 not in ULP mode + MIPI_DSI_PHY_STATUS_DATA_LANE3_NOT_ULP = 0x00000080, ///< Data lane 3 not in ULP mode + MIPI_DSI_PHY_STATUS_DATA_LANE0_STOP = 0x00000100, ///< Data lane 0 stop state + MIPI_DSI_PHY_STATUS_DATA_LANE1_STOP = 0x00000200, ///< Data lane 1 stop state + MIPI_DSI_PHY_STATUS_DATA_LANE2_STOP = 0x00000400, ///< Data lane 2 stop state + MIPI_DSI_PHY_STATUS_DATA_LANE3_STOP = 0x00000800, ///< Data lane 3 stop state + MIPI_DSI_PHY_STATUS_DATA_LANE0_RX_TO_TX = 0x00001000, ///< Data lane Rx to Tx transition event + MIPI_DSI_PHY_STATUS_DATA_LANE0_TX_TO_RX = 0x00002000, ///< Data lane Tx to Rx transition event + MIPI_DSI_PHY_STATUS_DATA_LANE0_RX_STATE = 0x00008000, ///< Data lane Rx active state + MIPI_DSI_PHY_STATUS_CLOCK_ULPS_ENTER = 0x01000000, ///< Clock lane ULPS enter event + MIPI_DSI_PHY_STATUS_CLOCK_ULPS_EXIT = 0x02000000, ///< Clock lane ULPS exit event + MIPI_DSI_PHY_STATUS_CLOCK_LP_TO_HS = 0x04000000, ///< Clock lane LP to HS transition event + MIPI_DSI_PHY_STATUS_CLOCK_HS_TO_LP = 0x08000000, ///< Clock lane HS to LP transition event + MIPI_DSI_PHY_STATUS_DATA_LANE_ULPS_ENTER = 0x10000000, ///< Data lane ULPS enter event + MIPI_DSI_PHY_STATUS_DATA_LANE_ULPS_EXIT = 0x20000000, ///< Data lane ULPS exit event +} mipi_dsi_phy_status_t; + +/** MIPI DSI link status bits */ +typedef enum e_mipi_dsi_link_status +{ + MIPI_DSI_LINK_STATUS_IDLE = 0x0000, ///< Link idle or uninitialized + MIPI_DSI_LINK_STATUS_CH0_RUNNING = 0x0001, ///< Channel 0 running + MIPI_DSI_LINK_STATUS_CH1_RUNNING = 0x0010, ///< Channel 1 running + MIPI_DSI_LINK_STATUS_VIDEO_RUNNING = 0x0100, ///< Video output running + MIPI_DSI_LINK_STATUS_HP_MODE_BUSY = 0x1000, ///< HP operation busy + MIPI_DSI_LINK_STATUS_LP_MODE_BUSY = 0x2000, ///< LP operation busy +} mipi_dsi_link_status_t; + +/** MIPI DSI Lane Type */ +typedef enum e_mipi_dsi_lane +{ + MIPI_DSI_LANE_CLOCK = 0x01, ///< Clock Lanes + MIPI_DSI_LANE_DATA_ALL = 0x02, ///< All Data Lanes +} mipi_dsi_lane_t; + +/** MIPI DSI Command */ +typedef struct st_mipi_dsi_cmd +{ + uint8_t channel; ///< Virtual Channel ID + mipi_cmd_id_t cmd_id; ///< Message ID + mipi_dsi_cmd_flag_t flags; ///< Flags controlling this message transition + uint16_t tx_len; ///< Transmit buffer size + const uint8_t * p_tx_buffer; ///< Transmit buffer pointer + const uint8_t * p_rx_buffer; ///< Receive buffer pointer +} mipi_dsi_cmd_t; + +/** MIPI DSI Acknowledge and Error status type */ +typedef union st_mipi_dsi_ack_err_status_t +{ + __PACKED_STRUCT + { + mipi_dsi_ack_err_t error_report : 16; ///< Error report bits + mipi_dsi_vc_t virtual_channel : 4; ///< Virtual Channel ID + uint32_t : 12; // Padding + }; + uint32_t bits; +} mipi_dsi_ack_err_status_t; + +/** MIPI DSI status type */ +typedef struct st_mipi_dsi_status_t +{ + mipi_dsi_link_status_t link_status; ///< Link status + mipi_dsi_ack_err_status_t ack_err_latest; ///< Latest Acknowledge and Error Report Packet Latest Info + mipi_dsi_ack_err_status_t ack_err_accumulated; ///< Accumulated Acknowledge and Error Report Packet Latest Info +} mipi_dsi_status_t; + +/** MIPI DSI Result */ +typedef __PACKED_STRUCT st_mipi_dsi_result +{ + uint8_t data[2]; ///< Data of received packet header + mipi_cmd_id_t cmd_id : 6; ///< Data type + uint8_t virtual_channel_id : 2; ///< Virtual channel ID + uint8_t long_packet : 1; ///< Sort packet (0) or Long packet (1) + uint8_t rx_success : 1; ///< Response packet or ack trigger received + uint8_t timeout : 1; ///< Fatal timeout error + uint8_t rx_fail : 1; ///< Expected receive not done + uint8_t rx_data_fail : 1; ///< Receive packet data fail + uint8_t rx_correctable_error : 1; ///< Correctable error detected + uint8_t rx_ack_err : 1; ///< Rx acknowledge and error report packet received + uint8_t info_overwrite : 1; ///< This information was overwritten +} mipi_dsi_receive_result_t; + +/** MIPI DSI callback parameter definition */ +typedef struct st_mipi_dsi_callback_args +{ + mipi_dsi_event_t event; ///< Event code + union + { + mipi_dsi_sequence_status_t tx_status; ///< Sequence status + mipi_dsi_receive_status_t rx_status; ///< Receive status + mipi_dsi_fatal_status_t fatal_status; ///< Fatal status + mipi_dsi_video_status_t video_status; ///< Video status + mipi_dsi_phy_status_t phy_status; ///< Phy Status + }; + mipi_dsi_receive_result_t * p_result; ///< Receive result pointer + void * p_context; ///< Context provided to user during callback +} mipi_dsi_callback_args_t; + +/** MIPI DSI transition timing */ +typedef struct st_mipi_dsi_timing +{ + uint32_t clock_stop_time; ///< Clock stop time + uint32_t clock_beforehand_time; ///< Clock beforehand time + uint32_t clock_keep_time; ///< Clock Keep time + uint32_t go_lp_and_back; ///< Go LP and Back time +} mipi_dsi_timing_t; + +/** MIPI DSI main configuration structure */ +typedef struct st_mipi_dsi_cfg +{ + mipi_phy_instance_t const * p_mipi_phy_instance; ///< Pointer to mipi physical layer instance + + mipi_dsi_timing_t const * p_timing; ///< Pointer to MIPI DSI timing configuration + + bool hsa_no_lp; ///< Suppress the transition to LP during HSA period and keep HS + bool hbp_no_lp; ///< Suppress the transition to LP during HBP period and keep HS + bool hfp_no_lp; ///< Suppress the transition to LP during HFP period and keep HS + uint8_t num_lanes; ///< Number of MIPI lanes to use. + uint8_t ulps_wakeup_period; ///< ULPS wakeup period + uint8_t continuous_clock; ///< Always run HS clock on/off + uint32_t hs_tx_timeout; ///< HS-Tx Timeout value + uint32_t lp_rx_timeout; ///< LP-Rx host processor timeout + uint32_t turnaround_timeout; ///< Turnaround Acknowledge Timeout + uint32_t bta_timeout; ///< Peripheral Response Timeout + uint32_t lprw_timeout; ///< LP Read and Write Timeouts + uint32_t hsrw_timeout; ///< HS Read and Write Timeouts + uint32_t max_return_packet_size; ///< Maximum return packet size + bool ecc_enable; ///< ECC Check enable + mipi_dsi_vc_t crc_check_mask; ///< Virtual channel CRC check enable + bool scramble_enable; ///< Scramble on/off + bool tearing_detect; ///< External tearing effect detection mode (0:rising, 1:falling edge) + bool eotp_enable; ///< End of Transmit Packet (EoTP) on/off + bool sync_pulse; ///< Enable for Non-Burst Mode with Sync Pulse sequence + mipi_dsi_video_data_t data_type; ///< Video mode data type: 16-bit RGB, 18-bit RGB, 24-bit RGB + uint8_t virtual_channel_id; ///< Video mode virtual channel to use (from 0x0 to 0x3) + uint32_t vertical_sync_lines; ///< Number of vertical sync active lines + bool vertical_sync_polarity; ///< V-Sync Polarity + uint32_t vertical_active_lines; ///< Number of vertical active lines + uint32_t vertical_back_porch; ///< Vertical back porch + uint32_t vertical_front_porch; ///< Vertical front porch + uint32_t horizontal_sync_lines; ///< Number of horizontal sync active lines + bool horizontal_sync_polarity; ///< H-Sync Polarity + uint32_t horizontal_active_lines; ///< Number of horizontal active lines + uint32_t horizontal_back_porch; ///< Horizontal back porch + uint32_t horizontal_front_porch; ///< Horizontal front porch + uint32_t video_mode_delay; + + /** Callback configuration */ + void (* p_callback)(mipi_dsi_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /** Pointer to display peripheral specific configuration */ + void const * p_extend; ///< MIPI hardware dependent configuration +} mipi_dsi_cfg_t; + +/** MIPI DSI control block. Allocate an instance specific control block to pass into the MIPI DSI API calls. */ +typedef void mipi_dsi_ctrl_t; + +/** Shared Interface definition for MIPI DSI peripheral */ +typedef struct st_mipi_dsi_api +{ + /** Open MIPI DSI device. + * + * @param[in,out] p_ctrl Pointer to MIPI DSI interface control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to MIPI DSI configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(mipi_dsi_ctrl_t * const p_ctrl, mipi_dsi_cfg_t const * const p_cfg); + + /** Close MIPI DSI device. + * + * @param[in] p_ctrl Pointer to MIPI DSI interface control block. + */ + fsp_err_t (* close)(mipi_dsi_ctrl_t * const p_ctrl); + + /** Start pixel data output. + * + * @param[in] p_ctrl Pointer to MIPI DSI interface control block. + */ + fsp_err_t (* start)(mipi_dsi_ctrl_t * const p_ctrl); + + /** Stop pixel data output. + * + * @param[in] p_ctrl Pointer to MIPI DSI interface control block. + */ + fsp_err_t (* stop)(mipi_dsi_ctrl_t * const p_ctrl); + + /** Enter Ultra-low Power State (ULPS). + * + * @param[in] p_ctrl Pointer to MIPI DSI interface control block. + * @param[in] lane Physical lane(s) to transition into ULPS + */ + fsp_err_t (* ulpsEnter)(mipi_dsi_ctrl_t * const p_ctrl, mipi_dsi_lane_t lane); + + /** Exit Ultra-low Power State (ULPS). + * + * @param[in] p_ctrl Pointer to MIPI DSI interface control block. + * @param[in] lane Physical lane(s) to transition from ULPS + */ + fsp_err_t (* ulpsExit)(mipi_dsi_ctrl_t * const p_ctrl, mipi_dsi_lane_t lane); + + /** Send a command to the display. + * + * @param[in] p_ctrl Pointer to MIPI DSI interface control block. + * @param[in] p_cmd Pointer to a command structure + */ + fsp_err_t (* command)(mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cmd_t * p_cmd); + + /** Get status of MIPI link. + * + * @param[in] p_ctrl Pointer to MIPI DSI interface control block. + * @param[in] p_status Pointer to MIPI DSI interface status structure. + */ + fsp_err_t (* statusGet)(mipi_dsi_ctrl_t * const p_ctrl, mipi_dsi_status_t * p_status); +} mipi_dsi_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_mipi_dsi_instance +{ + mipi_dsi_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + mipi_dsi_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + mipi_dsi_api_t const * p_api; ///< Pointer to the API structure for this instance +} mipi_dsi_instance_t; + +/* @} (end defgroup MIPI_DSI_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_opamp_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_opamp_api.h new file mode 100644 index 0000000000..2045eb4686 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_opamp_api.h @@ -0,0 +1,153 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_OPAMP_API_H +#define R_OPAMP_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_ANALOG_INTERFACES + * @defgroup OPAMP_API OPAMP Interface + * @brief Interface for Operational Amplifiers. + * + * @section OPAMP_API_SUMMARY Summary + * The OPAMP interface provides standard operational amplifier functionality, including starting and stopping the + * amplifier. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/** Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/***************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/** Trim command. */ +typedef enum e_opamp_trim_cmd +{ + OPAMP_TRIM_CMD_START, ///< Initialize trim state machine + OPAMP_TRIM_CMD_NEXT_STEP, ///< Move to next step in state machine + OPAMP_TRIM_CMD_CLEAR_BIT, ///< Clear trim bit +} opamp_trim_cmd_t; + +/** Trim input. */ +typedef enum e_opamp_trim_input +{ + OPAMP_TRIM_INPUT_PCH = 0U, ///< Trim non-inverting (+) input + OPAMP_TRIM_INPUT_NCH = 1U, ///< Trim inverting (-) input +} opamp_trim_input_t; + +/** OPAMP trim arguments. */ +typedef struct st_opamp_trim_args +{ + uint8_t channel; ///< Channel + opamp_trim_input_t input; ///< Which input of the channel above +} opamp_trim_args_t; + +/** OPAMP information. */ +typedef struct st_opamp_info +{ + uint32_t min_stabilization_wait_us; ///< Minimum stabilization wait time in microseconds +} opamp_info_t; + +/** OPAMP status. */ +typedef struct st_opamp_status +{ + uint32_t operating_channel_mask; ///< Bitmask of channels currently operating +} opamp_status_t; + +/** OPAMP general configuration. */ +typedef struct st_opamp_cfg +{ + void const * p_extend; ///< Extension parameter for hardware specific settings +} opamp_cfg_t; + +/** OPAMP control block. Allocate using driver instance control structure from driver instance header file. */ +typedef void opamp_ctrl_t; + +/** OPAMP functions implemented at the HAL layer will follow this API. */ +typedef struct st_opamp_api +{ + /** Initialize the operational amplifier. + * + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration + */ + fsp_err_t (* open)(opamp_ctrl_t * const p_ctrl, opamp_cfg_t const * const p_cfg); + + /** Start the op-amp(s). + * + * @param[in] p_ctrl Pointer to instance control block + * @param[in] channel_mask Bitmask of channels to start + */ + fsp_err_t (* start)(opamp_ctrl_t * const p_ctrl, uint32_t const channel_mask); + + /** Stop the op-amp(s). + * + * @param[in] p_ctrl Pointer to instance control block + * @param[in] channel_mask Bitmask of channels to stop + */ + fsp_err_t (* stop)(opamp_ctrl_t * const p_ctrl, uint32_t const channel_mask); + + /** Trim the op-amp(s). Not supported on all MCUs. See implementation for procedure details. + * + * @param[in] p_ctrl Pointer to instance control block + * @param[in] cmd Trim command + * @param[in] p_args Pointer to arguments for the command + */ + fsp_err_t (* trim)(opamp_ctrl_t * const p_ctrl, opamp_trim_cmd_t const cmd, opamp_trim_args_t const * const p_args); + + /** Provide information such as the recommended minimum stabilization wait time. + * + * @param[in] p_ctrl Pointer to instance control block + * @param[out] p_info OPAMP information stored here + */ + fsp_err_t (* infoGet)(opamp_ctrl_t * const p_ctrl, opamp_info_t * const p_info); + + /** Provide status of each op-amp channel. + * + * @param[in] p_ctrl Pointer to instance control block + * @param[out] p_status Status stored here + */ + fsp_err_t (* statusGet)(opamp_ctrl_t * const p_ctrl, opamp_status_t * const p_status); + + /** Close the specified OPAMP unit by ending any scan in progress, disabling interrupts, and removing power to the + * specified A/D unit. + * + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* close)(opamp_ctrl_t * const p_ctrl); +} opamp_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_opamp_instance +{ + opamp_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + opamp_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + opamp_api_t const * p_api; ///< Pointer to the API structure for this instance +} opamp_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup OPAMP_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_pdm_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_pdm_api.h new file mode 100644 index 0000000000..7a035ee7f8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_pdm_api.h @@ -0,0 +1,233 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_AUDIO_INTERFACES + * @defgroup PDM_API PDM Interface + * @brief Interface for PDM audio communication. + * + * @section PDM_API_SUMMARY Summary + * @brief The pulse-density modulation(PDM) interface provides APIs and definitions for PDM audio communication. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_PDM_API_H +#define R_PDM_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Audio PCM width */ +typedef enum e_pdm_pcm_width +{ + PDM_PCM_WIDTH_20_BITS_0_18 = 0x00, ///< Using 20-bit PCM Clips [18:0] bit of the buffer and 1-bit of sign + PDM_PCM_WIDTH_20_BITS_1_18 = 0x01, ///< Using 20-bit PCM Clips [18:1] bit of the buffer and 2-bits of sign + PDM_PCM_WIDTH_20_BITS_2_18 = 0x02, ///< Using 20-bit PCM Clips [18:2] bit of the buffer and 3-bits of sign + PDM_PCM_WIDTH_20_BITS_3_18 = 0x03, ///< Using 20-bit PCM Clips [18:3] bit of the buffer and 4-bits of sign + PDM_PCM_WIDTH_16_BITS_4_18 = 0x08, ///< Using 16-bit PCM Clips [18:4] bit of the buffer and 1-bit of sign + PDM_PCM_WIDTH_16_BITS_3_17 = 0x09, ///< Using 16-bit PCM Clips [17:3] bit of the buffer and 1-bit of sign + PDM_PCM_WIDTH_16_BITS_2_16 = 0x0A, ///< Using 16-bit PCM Clips [16:2] bit of the buffer and 1-bit of sign + PDM_PCM_WIDTH_16_BITS_1_15 = 0x0B, ///< Using 16-bit PCM Clips [15:1] bit of the buffer and 1-bit of sign + PDM_PCM_WIDTH_16_BITS_0_14 = 0x0C, ///< Using 16-bit PCM Clips [14:0] bit of the buffer and 1-bit of sign +} pdm_pcm_width_t; + +/** Input data select. */ +typedef enum e_pdm_input_data_edge +{ + PDM_INPUT_DATA_EDGE_RISE = 0, ///< Rise-edge data of channel n + PDM_INPUT_DATA_EDGE_FALL = 1, ///< Fall-edge data of channel n-1 (In case of n = 0, fall-edge data of channel 2 is selected.) +} pdm_input_data_edge_t; + +/** Events that can trigger a callback function */ +typedef enum e_pdm_event +{ + PDM_EVENT_IDLE, ///< IDLE + PDM_EVENT_DATA, ///< Data reception + PDM_EVENT_SOUND_DETECTION, ///< Sound detection + PDM_EVENT_ERROR, ///< Error +} pdm_event_t; + +/** Error information included in a callback function */ +typedef enum e_pdm_error +{ + PDM_ERROR_NONE = 0, ///< No error + PDM_ERROR_SHORT_CIRCUIT = (1UL << 0), ///< Short circuit detection + PDM_ERROR_OVERVOLTAGE_LOWER = (1UL << 1), ///< Overvoltage lower limit exceeded detection + PDM_ERROR_OVERVOLTAGE_UPPER = (1UL << 2), ///< Overvoltage upper limit exceeded detection + PDM_ERROR_BUFFER_OVERWRITE = (1UL << 11) ///< Buffer overwriting detection +} pdm_error_t; + +/** Possible status values returned by @ref pdm_api_t::statusGet. */ +typedef enum e_pdm_state +{ + PDM_STATE_IN_USE, ///< PDM is actively reading data + PDM_STATE_STOPPED ///< PDM is stopped and not actively reading data +} pdm_state_t; + +/** Callback function parameter data */ +typedef struct st_pdm_callback_args +{ + /** Placeholder for user data. Set in @ref pdm_api_t::open function in @ref pdm_cfg_t. */ + void * p_context; + pdm_event_t event; ///< The event can be used to identify what caused the callback (overflow or error). + pdm_error_t error; ///< The kind of error. +} pdm_callback_args_t; + +/** Sound detection window setting */ +typedef struct st_pdm_sound_detection_setting +{ + uint32_t sound_detection_lower_limit; ///< Sound detection lower limit (20-bit signed fixed point data) + uint32_t sound_detection_upper_limit; ///< Sound detection upper limit (20-bit signed fixed point data) +} pdm_sound_detection_setting_t; + +/** PDM control block. Allocate an instance specific control block to pass into the PDM API calls. + */ +typedef void pdm_ctrl_t; + +/** PDM status. */ +typedef struct st_pdm_status +{ + pdm_state_t state; ///< Current PDM data state + bool sound_detection_enabled; ///< Current PDM sound detection status + pdm_error_t error; ///< Bitfield of current PDM errors +} pdm_status_t; + +/** User configuration structure, used in open function */ +typedef struct st_pdm_cfg +{ + /** Select a unit/channel corresponding to the unit/channel number of the hardware. */ + uint32_t unit; + uint32_t channel; + pdm_pcm_width_t pcm_width; ///< Audio PCM data width + pdm_input_data_edge_t pcm_edge; ///< Input data select + + /** To use DMA for receiving link a Transfer instance here. Set to NULL if unused. */ + transfer_instance_t const * p_transfer_rx; + + /** Callback provided when an PDM ISR occurs. Set to NULL for no CPU interrupt. */ + void (* p_callback)(pdm_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref pdm_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. + uint8_t dat_ipl; ///< Data reception interrupt priority + uint8_t sdet_ipl; ///< Sound detection interrupt priority + uint8_t err_ipl; ///< Idle/Error interrupt priority + IRQn_Type dat_irq; ///< IRQ number of data reception interrupt + IRQn_Type sdet_irq; ///< IRQ number of sound detection interrupt + IRQn_Type err_irq; ///< IRQ number of error detection interrupt +} pdm_cfg_t; + +/** PDM functions implemented at the HAL layer will follow this API. */ +typedef struct st_pdm_api +{ + /** Initial configuration. + * + * @pre Peripheral clocks and any required output pins should be configured prior to calling this function. + * @note To reconfigure after calling this function, call @ref pdm_api_t::close first. + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(pdm_ctrl_t * const p_ctrl, pdm_cfg_t const * const p_cfg); + + /** Start communication. + * + * @param[in] p_ctrl Control block set in @ref pdm_api_t::open call for this instance. + * @param[in] p_buffer Pointer to the reception buffer + * @param[in] buffer_size Size of the buffer + * @param[in] number_of_data_to_callback Number of the data to call the callback function from dat_isr + */ + fsp_err_t (* start)(pdm_ctrl_t * const p_ctrl, void * const p_buffer, size_t const buffer_size, + uint32_t const number_of_data_to_callback); + + /** Stop communication. Communication is stopped when callback is called with PDM_EVENT_IDLE. + * + * @param[in] p_ctrl Control block set in @ref pdm_api_t::open call for this instance. + */ + fsp_err_t (* stop)(pdm_ctrl_t * const p_ctrl); + + /** Enable sound detection with the specified settings. + * + * @param[in] p_ctrl Control block set in @ref pdm_api_t::open call for this instance. + * @param[in] pdm_sound_detection_setting Settings to configure sound detection. + */ + fsp_err_t (* soundDetectionEnable)(pdm_ctrl_t * const p_ctrl, + pdm_sound_detection_setting_t pdm_sound_detection_setting); + + /** Disable sound detection. + * + * @param[in] p_ctrl Control block set in @ref pdm_api_t::open call for this instance. + */ + fsp_err_t (* soundDetectionDisable)(pdm_ctrl_t * const p_ctrl); + + /** Read remaining PDM data. This function can be called during PDM_STATE_STOPPED. + * + * @param[in] p_ctrl Control block set in @ref pdm_api_t::open call for this instance. + * @param[in] p_dest Buffer to store PCM samples. Must be 4 byte aligned. + * @param[in] bytes Number of bytes in the buffer. Recommended requesting a multiple of 8 bytes. If not + * a multiple of 8, receive will stop at the multiple of 8 below requested bytes. + */ + fsp_err_t (* read)(pdm_ctrl_t * const p_ctrl, void * const p_dest, uint32_t const bytes); + + /** Get current status and store it in provided pointer p_status. + * + * @param[in] p_ctrl Control block set in @ref pdm_api_t::open call for this instance. + * @param[out] p_status Current status of the driver. + */ + fsp_err_t (* statusGet)(pdm_ctrl_t * const p_ctrl, pdm_status_t * const p_status); + + /** Allows driver to be reconfigured and may reduce power consumption. + * + * @param[in] p_ctrl Control block set in @ref pdm_api_t::open call for this instance. + */ + fsp_err_t (* close)(pdm_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the PDM control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(pdm_ctrl_t * const p_ctrl, void (* p_callback)(pdm_callback_args_t *), + void * const p_context, pdm_callback_args_t * const p_callback_memory); +} pdm_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_pdm_instance +{ + pdm_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + pdm_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + pdm_api_t const * p_api; ///< Pointer to the API structure for this instance +} pdm_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup PDM_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_poeg_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_poeg_api.h new file mode 100644 index 0000000000..4722cba610 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_poeg_api.h @@ -0,0 +1,197 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_TIMERS_INTERFACES + * @defgroup POEG_API POEG Interface + * + * @brief Interface for the Port Output Enable for GPT. + * + * Defines the API and data structures for the Port Output Enable for GPT (POEG) interface. + * + * @section POEG_API_SUMMARY Summary + * @brief The POEG disables GPT output pins based on configurable events. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_POEG_API_H +#define R_POEG_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_POEG_STATE_T + +/** POEG states. */ +typedef enum e_poeg_state +{ + POEG_STATE_NO_DISABLE_REQUEST = 0, ///< GPT output is not disabled by POEG + POEG_STATE_PIN_DISABLE_REQUEST = 1U << 0, ///< GPT output disabled due to GTETRG pin level + POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST = 1U << 1, ///< GPT output disabled due to high speed analog comparator or GPT + POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST = 1U << 2, ///< GPT output disabled due to main oscillator stop + POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST = 1U << 3, ///< GPT output disabled due to poeg_api_t::outputDisable() + + /** GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of + * the filtered input. */ + POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE = 1U << 16, +} poeg_state_t; + +#endif + +#ifndef BSP_OVERRIDE_POEG_TRIGGER_T + +/** Triggers that will disable GPT output pins. */ +typedef enum e_poeg_trigger +{ + /** Software disable is always supported with POEG. Select this option if no other triggers are used. */ + POEG_TRIGGER_SOFTWARE = 0U, + POEG_TRIGGER_PIN = 1U << 0, ///< Disable GPT output based on GTETRG input level + POEG_TRIGGER_GPT_OUTPUT_LEVEL = 1U << 1, ///< Disable GPT output based on GPT output pin levels + POEG_TRIGGER_OSCILLATION_STOP = 1U << 2, ///< Disable GPT output based on main oscillator stop + POEG_TRIGGER_ACMPHS0 = 1U << 4, ///< Disable GPT output based on ACMPHS0 comparator result + POEG_TRIGGER_ACMPHS1 = 1U << 5, ///< Disable GPT output based on ACMPHS1 comparator result + POEG_TRIGGER_ACMPHS2 = 1U << 6, ///< Disable GPT output based on ACMPHS2 comparator result + POEG_TRIGGER_ACMPHS3 = 1U << 7, ///< Disable GPT output based on ACMPHS3 comparator result + POEG_TRIGGER_ACMPHS4 = 1U << 8, ///< Disable GPT output based on ACMPHS4 comparator result + POEG_TRIGGER_ACMPHS5 = 1U << 9, ///< Disable GPT output based on ACMPHS5 comparator result +} poeg_trigger_t; + +#endif + +/** GTETRG polarity. */ +typedef enum e_poeg_gtetrg_polarity +{ + POEG_GTETRG_POLARITY_ACTIVE_HIGH = 0U, ///< Disable GPT output based when GTETRG input level is high + POEG_GTETRG_POLARITY_ACTIVE_LOW = 1U, ///< Disable GPT output based when GTETRG input level is low +} poeg_gtetrg_polarity_t; + +/** GTETRG noise filter. For the input signal to pass through the noise filter, the active level set in + * @ref poeg_gtetrg_polarity_t must be read 3 consecutive times at the sampling clock selected. + */ +typedef enum e_poeg_gtetrg_noise_filter +{ + POEG_GTETRG_NOISE_FILTER_DISABLED = 0U, ///< No noise filter applied to GTETRG input + POEG_GTETRG_NOISE_FILTER_CLK_SOURCE_DIV_1 = 1U, ///< Apply noise filter with sample clock equal to Clock source/1 + POEG_GTETRG_NOISE_FILTER_CLK_SOURCE_DIV_8 = 3U, ///< Apply noise filter with sample clock equal to Clock source/8 + POEG_GTETRG_NOISE_FILTER_CLK_SOURCE_DIV_32 = 5U, ///< Apply noise filter with sample clock equal to Clock source/32 + POEG_GTETRG_NOISE_FILTER_CLK_SOURCE_DIV_128 = 7U, ///< Apply noise filter with sample clock equal to Clock source/128 +} poeg_gtetrg_noise_filter_t; + +/** POEG status */ +typedef struct st_poeg_status +{ + poeg_state_t state; ///< Current state of POEG +} poeg_status_t; + +/** Callback function parameter data. */ +typedef struct st_poeg_callback_args +{ + void * p_context; ///< Placeholder for user data, set in @ref poeg_cfg_t. +} poeg_callback_args_t; + +/** POEG control block. Allocate an instance specific control block to pass into the POEG API calls. + */ +typedef void poeg_ctrl_t; + +/** User configuration structure, used in the open function. */ +typedef struct st_poeg_cfg +{ + poeg_trigger_t trigger; ///< Select one or more triggers for the POEG + poeg_gtetrg_polarity_t polarity; ///< Select the polarity for the GTETRG pin + poeg_gtetrg_noise_filter_t noise_filter; ///< Configure the GTETRG noise filter + + /** Callback called when a POEG interrupt occurs. */ + void (* p_callback)(poeg_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref poeg_callback_args_t. */ + void * p_context; + uint32_t unit; ///< POEG unit to be used + uint32_t channel; ///< Channel 0 corresponds to GTETRGA, 1 to GTETRGB, etc. + IRQn_Type irq; ///< Interrupt number assigned to this instance + uint8_t ipl; ///< POEG interrupt priority + void const * p_extend; ///< Extension parameter for hardware specific settings +} poeg_cfg_t; + +/** Port Output Enable for GPT (POEG) API structure. POEG functions implemented at the HAL layer will follow this API. */ +typedef struct st_poeg_api +{ + /** Initial configuration. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(poeg_ctrl_t * const p_ctrl, poeg_cfg_t const * const p_cfg); + + /** Gets the current driver state. + * + * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call. + * @param[out] p_status Provides the current state of the POEG. + */ + fsp_err_t (* statusGet)(poeg_ctrl_t * const p_ctrl, poeg_status_t * p_status); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call for this timer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(poeg_ctrl_t * const p_ctrl, void (* p_callback)(poeg_callback_args_t *), + void * const p_context, poeg_callback_args_t * const p_callback_memory); + + /** Disables GPT output pins by software request. + * + * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call. + */ + fsp_err_t (* outputDisable)(poeg_ctrl_t * const p_ctrl); + + /** Attempts to clear status flags to reenable GPT output pins. Confirm all status flags are cleared after calling + * this function by calling poeg_api_t::statusGet(). + * + * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call. + */ + fsp_err_t (* reset)(poeg_ctrl_t * const p_ctrl); + + /** Disables POEG interrupt. + * + * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call. + */ + fsp_err_t (* close)(poeg_ctrl_t * const p_ctrl); +} poeg_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_poeg_instance +{ + poeg_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + poeg_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + poeg_api_t const * p_api; ///< Pointer to the API structure for this instance +} poeg_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup POEG_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ptp_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ptp_api.h new file mode 100644 index 0000000000..8c9f9a5a29 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_ptp_api.h @@ -0,0 +1,689 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_NETWORKING_INTERFACES + * @defgroup PTP_API PTP Interface + * @brief Interface for PTP functions. + * + * @section PTP_API_SUMMARY Summary + * The PTP interface provides the functionality for using PTP. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_PTP_API_H +#define R_PTP_API_H + +#include "bsp_api.h" +#include "../../src/r_ptp/r_edmac/r_edmac.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************* + * Macro definitions + ********************************************************************************************************************/ + +/* Internal Oscillator. */ +#define PTP_TIMESOURCE_INT_OSC (0xA0) + +#if defined(__GNUC__) + #define PTP_PACKED __attribute__((packed)) +#else + #define PTP_PACKED __PACKED +#endif + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum e_ptp_enable +{ + PTP_DISABLE, + PTP_ENABLE +} ptp_enable_t; + +/** Standard PTP message types. */ +typedef enum e_ptp_message_type +{ + PTP_MESSAGE_TYPE_SYNC = 0x00U, ///< Sync Message Type + PTP_MESSAGE_TYPE_DELAY_REQ = 0x01U, ///< Delay_req Message Type + PTP_MESSAGE_TYPE_PDELAY_REQ = 0x02U, ///< PDelay_req Message Type + PTP_MESSAGE_TYPE_PDELAY_RESP = 0x03U, ///< PDelay_resp Message Type + PTP_MESSAGE_TYPE_FOLLOW_UP = 0x08U, ///< Follow_up Message Type + PTP_MESSAGE_TYPE_DELAY_RESP = 0x09U, ///< Delay_resp Message Type + PTP_MESSAGE_TYPE_PDELAY_RESP_FOLLOW_UP = 0x0AU, ///< PDelay_resp_follow_up Message Type + PTP_MESSAGE_TYPE_ANNOUNCE = 0x0BU, ///< Announce Message Type + PTP_MESSAGE_TYPE_SIGNALING = 0x0CU, ///< Signaling Message Type + PTP_MESSAGE_TYPE_MANAGEMENT = 0x0DU, ///< Management Message Type +} ptp_message_type_t; + +/** Possible states that the PTP instance can be in. */ +typedef enum e_ptp_port_state +{ + PTP_PORT_STATE_GENERATE_ANNOUNCE = (1U << 3U), ///< Generate Announce Messages + PTP_PORT_STATE_GENERATE_SYNC = (1U << 7U), ///< Generate Sync Messages + PTP_PORT_STATE_GENERATE_DELAY_REQ = (1U << 11U), ///< Generate Delay_req Messages + PTP_PORT_STATE_GENERATE_PDELAY_REQ = (1U << 15U), ///< Generate PDelay_req Messages + + PTP_PORT_STATE_RECEIVE_ANNOUNCE = (1U << 0U), ///< Receive Announce Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_SYNC = (1U << 4U), ///< Receive Sync Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_FOLLOW_UP = (1U << 8U), ///< Receive Follow_up Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_DELAY_REQ = (1U << 12U), ///< Receive Delay_req Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_DELAY_RESP = (1U << 16U), ///< Receive Delay_resp Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_PDELAY_REQ = (1U << 20U), ///< Receive PDelay_req Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_PDELAY_RESP = (1U << 24U), ///< Receive PDelay_resp Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_PDELAY_RESP_FOLLOW_UP = (1U << 28U), ///< Receive PDelay_resp_follow_up Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_MANAGEMENT = (1U << 1U), ///< Receive Management Messages from @ref ptp_cfg_t::p_callback + PTP_PORT_STATE_RECEIVE_SIGNALING = (1U << 5U), ///< Receive Signaling Messages from @ref ptp_cfg_t::p_callback + + PTP_PORT_STATE_PROCESS_SYNC = (1U << 6U), ///< Enable Sync Message processing. + PTP_PORT_STATE_PROCESS_FOLLOW_UP = (1U << 10U), ///< Enable Follow_up Message processing. + PTP_PORT_STATE_PROCESS_DELAY_REQ = (1U << 14U), ///< Enable Delay_req Message processing. + PTP_PORT_STATE_PROCESS_DELAY_RESP = (1U << 18U), ///< Enable Delay_resp Message processing. + PTP_PORT_STATE_PROCESS_PDELAY_REQ = (1U << 22U), ///< Enable PDelay_req Message processing. + PTP_PORT_STATE_PROCESS_PDELAY_RESP = (1U << 26U), ///< Enable PDelay_resp Message processing. + PTP_PORT_STATE_PROCESS_PDELAY_RESP_FOLLOW_UP = (1U << 30U), ///< Enable PDelay_resp_follow_up Message processing. + + /** Configure the PTP instance to only receive Announce, Management, and Signaling Messages. */ + PTP_PORT_STATE_PASSIVE = (PTP_PORT_STATE_RECEIVE_ANNOUNCE | + PTP_PORT_STATE_RECEIVE_MANAGEMENT | + PTP_PORT_STATE_RECEIVE_SIGNALING), + + /** Configure the PTP instance to operate as a E2E Master. */ + PTP_PORT_STATE_E2E_MASTER = (PTP_PORT_STATE_GENERATE_ANNOUNCE | + PTP_PORT_STATE_GENERATE_SYNC | + PTP_PORT_STATE_PROCESS_DELAY_REQ | + PTP_PORT_STATE_PASSIVE), + + /** Configure the PTP instance to operate as a E2E Slave. */ + PTP_PORT_STATE_E2E_SLAVE = (PTP_PORT_STATE_GENERATE_DELAY_REQ | + PTP_PORT_STATE_PROCESS_SYNC | + PTP_PORT_STATE_PROCESS_FOLLOW_UP | + PTP_PORT_STATE_PROCESS_DELAY_RESP | + PTP_PORT_STATE_PASSIVE), + + /** Configure the PTP instance to operate as a P2P Master. */ + PTP_PORT_STATE_P2P_MASTER = (PTP_PORT_STATE_GENERATE_ANNOUNCE | + PTP_PORT_STATE_GENERATE_SYNC | + PTP_PORT_STATE_GENERATE_PDELAY_REQ | + PTP_PORT_STATE_PROCESS_PDELAY_REQ | + PTP_PORT_STATE_PROCESS_PDELAY_RESP | + PTP_PORT_STATE_PROCESS_PDELAY_RESP_FOLLOW_UP | + PTP_PORT_STATE_PASSIVE), + + /** Configure the PTP instance to operate as a P2P Slave. */ + PTP_PORT_STATE_P2P_SLAVE = (PTP_PORT_STATE_GENERATE_PDELAY_REQ | + PTP_PORT_STATE_PROCESS_SYNC | + PTP_PORT_STATE_PROCESS_FOLLOW_UP | + PTP_PORT_STATE_PROCESS_PDELAY_REQ | + PTP_PORT_STATE_PROCESS_PDELAY_RESP | + PTP_PORT_STATE_PROCESS_PDELAY_RESP_FOLLOW_UP | + PTP_PORT_STATE_PASSIVE), + + /** Configure the PTP instance to receive all messages. */ + PTP_PORT_STATE_RECEIVE_ALL = (PTP_PORT_STATE_RECEIVE_ANNOUNCE | + PTP_PORT_STATE_RECEIVE_SYNC | + PTP_PORT_STATE_RECEIVE_FOLLOW_UP | + PTP_PORT_STATE_RECEIVE_DELAY_REQ | + PTP_PORT_STATE_RECEIVE_DELAY_RESP | + PTP_PORT_STATE_RECEIVE_PDELAY_REQ | + PTP_PORT_STATE_RECEIVE_PDELAY_RESP | + PTP_PORT_STATE_RECEIVE_PDELAY_RESP_FOLLOW_UP | + PTP_PORT_STATE_RECEIVE_MANAGEMENT | + PTP_PORT_STATE_RECEIVE_SIGNALING), + + /** Disable all PTP message generation, processing, and reception. */ + PTP_PORT_STATE_DISABLE = 0, +} ptp_port_state_t; + +/** The mechanism used for delay messages. */ +typedef enum e_ptp_clock_delay_mechanism +{ + PTP_CLOCK_DELAY_MECHANISM_E2E, ///< End to end delay mechanism + PTP_CLOCK_DELAY_MECHANISM_P2P ///< Peer to peer delay mechanism +} ptp_clock_delay_mechanism_t; + +/** Frame formats that PTP messages can be encapsulated in. */ +typedef enum e_ptp_frame_format +{ + /** Send PTP messages using Ethernet II frames. */ + PTP_FRAME_FORMAT_ETHERII, + + /** Send PTP messages using IEEE802_3 frames. */ + PTP_FRAME_FORMAT_IEEE802_3, + + /** Send PTP messages using Ethernet II frames with an IP and UDP header. */ + PTP_FRAME_FORMAT_ETHERII_IPV4_UDP, + + /** Send PTP messages using IEEE802.3 frames with an IP and UDP header. */ + PTP_FRAME_FORMAT_IEEE802_3_IPV4_UDP, +} ptp_frame_format_t; + +/** Filter PTP messages based on destination MAC address. Messages that pass the filter will be transferred to the ETHERC EDMAC. */ +typedef enum e_ptp_frame_filter_mode +{ + PTP_FRAME_FILTER_MODE_EXT_PROMISCUOUS_MODE = 65536U, ///< Receive all packets. + PTP_FRAME_FILTER_MODE_UNICAST_MULTICAST = 0U, ///< Receive all unicast packets destined for the PTP and all multicast packets. + PTP_FRAME_FILTER_MODE_UNICAST_MULTICAST_FILTERED = 6U, ///< Receive Unicast packets destined for the PTP and filter configured multicast packets. + PTP_FRAME_FILTER_MODE_UNICAST = 5U, ///< Receive unicast packets destined for the PTP. +} ptp_frame_filter_mode_t; + +/** The control field for PTP message header. */ +typedef enum PTP_PACKED e_ptp_ctrl_field +{ + PTP_CTRL_FIELD_SYNC = 0, + PTP_CTRL_FIELD_DELAY_REQ = 1, + PTP_CTRL_FIELD_FOLLOW_UP = 2, + PTP_CTRL_FIELD_DELAY_RESP = 3, + PTP_CTRL_FIELD_MANAGEMENT = 4, + PTP_CTRL_FIELD_OTHER = 5 +} ptp_ctrl_field_t; + +/** STCA input clock frequency. */ +typedef enum e_ptp_stca_clock_freq +{ + PTP_STCA_CLOCK_FREQ_20MHZ, ///< 20 Mhz Input Clock + PTP_STCA_CLOCK_FREQ_25MHZ, ///< 25 Mhz Input Clock + PTP_STCA_CLOCK_FREQ_50MHZ, ///< 50 Mhz Input Clock + PTP_STCA_CLOCK_FREQ_100MHZ, ///< 100 Mhz Input Clock +} ptp_stca_clock_freq_t; + +/** STCA input clock selection. */ +typedef enum e_ptp_stca_clock_sel +{ + PTP_STCA_CLOCK_SEL_PCLKA_DIV_1 = 1, ///< PCLKA + PTP_STCA_CLOCK_SEL_PCLKA_DIV_2, ///< PCLKA Divided by 2 + PTP_STCA_CLOCK_SEL_PCLKA_DIV_3, ///< PCLKA Divided by 3 + PTP_STCA_CLOCK_SEL_PCLKA_DIV_4, ///< PCLKA Divided by 4 + PTP_STCA_CLOCK_SEL_PCLKA_DIV_5, ///< PCLKA Divided by 5 + PTP_STCA_CLOCK_SEL_PCLKA_DIV_6, ///< PCLKA Divided by 6 + PTP_STCA_CLOCK_SEL_REF50CK0 = 512, ///< 50-MHz Reference Signal for timing in RMII mode (STCA clock frequency is 25 Mhz when REF50CK0 is used). +} ptp_stca_clock_sel_t; + +/** Message interval for transmitting PTP messages. */ +typedef enum e_ptp_message_interval +{ + PTP_MESSAGE_INTERVAL_1_128 = -7, ///< 1 / 128 seconds + PTP_MESSAGE_INTERVAL_1_64 = -6, ///< 1 / 64 seconds + PTP_MESSAGE_INTERVAL_1_32 = -5, ///< 1 / 32 seconds + PTP_MESSAGE_INTERVAL_1_16 = -4, ///< 1 / 16 seconds + PTP_MESSAGE_INTERVAL_1_8 = -3, ///< 1 / 8 seconds + PTP_MESSAGE_INTERVAL_1_4 = -2, ///< 1 / 4 seconds + PTP_MESSAGE_INTERVAL_1_2 = -1, ///< 1 / 2 seconds + PTP_MESSAGE_INTERVAL_1 = 0, ///< 1 seconds + PTP_MESSAGE_INTERVAL_2 = 1, ///< 2 seconds + PTP_MESSAGE_INTERVAL_4 = 2, ///< 4 seconds + PTP_MESSAGE_INTERVAL_8 = 3, ///< 8 seconds + PTP_MESSAGE_INTERVAL_16 = 4, ///< 16 seconds + PTP_MESSAGE_INTERVAL_32 = 5, ///< 32 seconds + PTP_MESSAGE_INTERVAL_64 = 6, ///< 64 seconds +} ptp_message_interval_t; + +/** Clock correction mode. */ +typedef enum e_ptp_clock_correction_mode +{ + PTP_CLOCK_CORRECTION_MODE1, ///< Correct the local clock using the current offsetFromMaster value. + PTP_CLOCK_CORRECTION_MODE2, ///< Correct the local clock using the calculated clock gradient. +} ptp_clock_correction_mode_t; + +/** PTP events provided by @ref ptp_cfg_t::p_callback. */ +typedef enum e_ptp_event +{ + PTP_EVENT_SYNC_ACQUIRED = 0x80, ///< The local clock is synchronized to the master clock. + PTP_EVENT_SYNC_LOST = 0x81, ///< The local clock is not synchronized to the master clcok. + PTP_EVENT_SYNC_MESSAGE_TIMEOUT = 0x83, ///< A sync message has not been received for the configured time. + PTP_EVENT_WORST10_ACQUIRED = 0x84, ///< Gradient worst10 values has been calculated. + PTP_EVENT_OFFSET_FROM_MASTER_UPDATED = 0x00, ///< The offset from the master clock has been updated. + PTP_EVENT_LOG_MESSAGE_INT_CHANGED = 0x01, ///< The message interval was changed. + PTP_EVENT_MEAN_PATH_DELAY_UPDATED = 0x02, ///< The mean path delay has been updated. + PTP_EVENT_DELAY_RESP_TIMEOUT = 0x04, ///< A delay_resp has not been received for the configured time. + PTP_EVENT_LOG_MESSAGE_INT_OUT_OF_RANGE = 0x05, ///< The updated message interval is out of range. + PTP_EVENT_DELAY_REQ_FIFO_OVERFLOW = 0x06, ///< The FIFO buffer for storing information from received Delay_Req messages holds 32 or more entries. + PTP_EVENT_LOOP_RECEPTION_DETECTED = 0x0C, ///< A packet with the same sourcePortIdendity as the local clock was received. + PTP_EVENT_CTRL_INFO_ABNORMALITY = 0x0D, ///< A malformed frame was received (EDMAC, ETHERC, and EPTPC must be reset). + PTP_EVENT_DELAY_RESP_PROCESSING_HALTED = 0x10, ///< Processing of delay_resp messages has been halted. + PTP_EVENT_MESSAGE_GENERATION_HALTED = 0x11, ///< Generation of messages has been halted. + PTP_EVENT_MESSAGE_RECEIVED = 0x12, ///< A PTP message was received from the EDMAC. + PTP_EVENT_MESSAGE_TRANSMIT_COMPLETE = 0x13, ///< A PTP message has been transmitted. + PTP_EVENT_PULSE_TIMER_MINT_RISING_EDGE = 0x14, ///< A rising edge occurred on a pulse timer channel. + PTP_EVENT_PULSE_TIMER_IPLS_COMMON = 0x15, ///< A rising or falling edge occurred on any pulse timer channel. +} ptp_event_t; + +/** The Ethernet PHY interface type. */ +typedef enum e_ptp_ethernet_phy_interface +{ + PTP_ETHERNET_PHY_INTERFACE_MII, ///< Media-independent interface. + PTP_ETHERNET_PHY_INTERFACE_RMII, ///< Reduced media-independent interface. +} ptp_ethernet_phy_interface_t; + +/** + * Clock properties used in the best master clock algorithm (BMCA) in order to + * determine the grandmaster clock. + * + * In master mode, these properties will be advertised in announce messages. + * + * Note: The final property used in BMCA is the clock ID. This is usually + * configured at runtime because it is often based on the + * hardware address. + */ +typedef struct PTP_PACKED st_ptp_clock_properties +{ + uint8_t priority1; ///< Priority1 value used in best master calculation. + uint8_t cclass; ///< Class value. + uint8_t accuracy; ///< Accuracy of the clock. + uint16_t variance; ///< Variance of the clock. + uint8_t priority2; ///< Priority2 value used as secondary priority in best master calculation. +} ptp_clock_properties_t; + +/** Structure for storing time with nanosecond precision . */ +typedef struct PTP_PACKED st_ptp_time +{ + uint16_t seconds_upper; ///< Upper 16 bits of the seconds. + uint32_t seconds_lower; ///< Lower 32 bits of the seconds. + uint32_t nanoseconds; ///< Nanoseconds +} ptp_time_t; + +/** + * Flags field in PTP message header. + */ +typedef struct PTP_PACKED st_ptp_message_flags +{ + union + { + uint16_t value; + struct + { + /** + * Set the flag to indicate that the last minute of the current day has 61 seconds + * (Add one leap second to currentUtcOffset at the end of the day). + */ + uint16_t leap61 : 1U; + + /** + * Set the flag to indicate that the last minute of the current day has 59 seconds + * (Subtract one leap second from currentUtcOffset at the end of the day). + */ + uint16_t leap59 : 1U; + uint16_t currentUtcOffsetValid : 1U; ///< The currentOffsetFromMaster is valid. + uint16_t ptpTimescale : 1U; ///< The PTP timescale is used. + uint16_t timeTraceable : 1U; ///< The timescale is traceable to a reference clock. + uint16_t frequencyTraceable : 1U; ///< The frequency is traceable to a reference clock. + uint16_t : 2U; /* Reserved */ + uint16_t alternateMasterFlag : 1U; ///< Indicates that the PTP message is transmitted from a PTP Port not in the MASTER state. + uint16_t twoStep : 1U; ///< Indicates that a Sync or a Pdelay_Resp message will be followed by a Follow_Up message. + uint16_t unicast : 1U; ///< Indicates that the PTP message is transmitted as a unicast PTP message. + uint16_t : 2U; /* Reserved */ + uint16_t profileSpecific1 : 1U; ///< As defined by the applicable PTP Profile. + uint16_t profileSpecific2 : 1U; ///< As defined by the applicable PTP Profile. + uint16_t : 1U; /* Reserved */ + } value_b; + }; +} ptp_message_flags_t; + +/** Commom PTP Message Header. */ +typedef struct PTP_PACKED st_ptp_message_header +{ + uint8_t message_type : 4; ///< The message type. + uint8_t sdoid_major : 4; ///< Standard Organization ID Major. + uint8_t version : 4; ///< PTP Version. + uint8_t minor_version : 4; ///< PTP Minor Version. + uint16_t message_length; ///< The total message length (Including the header). + uint8_t domain; ///< The clock domain. + uint8_t sdoid_minor : 8; ///< Standard Organization ID minor. + ptp_message_flags_t flags; ///< Flags set in the message. + uint64_t correction_field; ///< Correction Field that is updated when a message passes through a transparent clock. + uint32_t reserved; /* Reserved */ + uint8_t clock_id[8]; ///< Clock ID that the message was sent from. + uint16_t source_port_id; ///< Port ID that the message was sent from. + uint16_t sequence_id; ///< Sequence ID of the message. + ptp_ctrl_field_t control_field; ///< Control field (Message specifc). + uint8_t log_message_interval; ///< Logbase2 of the message period. +} ptp_message_header_t; + +/** Sync Message Type (0x00). */ +typedef struct PTP_PACKED st_ptp_message_sync +{ + ptp_time_t origin_timestamp; ///< Timestamp when the message was transmitted. +} ptp_message_sync_t; + +/** Delay_req Message Type (0x01). */ +typedef ptp_message_sync_t ptp_message_delay_req_t; + +/** PDelay_req Message Type (0x02). */ +typedef struct PTP_PACKED st_ptp_message_pdelay_req +{ + ptp_time_t origin_timestamp; ///< Timestamp when the message was transmitted. + uint8_t reserved[10]; /* Reserved */ +} ptp_message_pdelay_req_t; + +/** PDelay_resp Message Type (0x03). */ +typedef struct PTP_PACKED st_ptp_message_pdelay_resp +{ + ptp_time_t origin_timestamp; ///< Timestamp when the message was transmitted. + uint8_t source_port_identity[10]; ///< Clock ID + sourcePortId. +} ptp_message_pdelay_resp_t; + +/** Follow_up Message Type (0x08). */ +typedef ptp_message_sync_t ptp_message_follow_up_t; + +/** Delay_resp Message Type (0x09). */ +typedef ptp_message_pdelay_resp_t ptp_message_delay_resp_t; + +/** PDelay_resp_follow_up Message Type (0x0A). */ +typedef ptp_message_delay_resp_t ptp_message_pdelay_resp_follow_up_t; + +/** Announce Message Type (0x0B). */ +typedef struct PTP_PACKED st_ptp_message_announce +{ + ptp_time_t origin_timestamp; ///< Timestamp when the message was transmitted. + uint16_t current_utc_offset; ///< Offset from UTC in seconds. + uint8_t reserved; /* Reserved */ + ptp_clock_properties_t clock_properties; ///< Clock properties used in Best Master Clock Algorithm. + uint8_t clock_id[8]; ///< Clock ID that the message was sent from. + uint16_t steps_removed; ///< The number of boundary clocks between the clock and the grand master clock. + uint8_t time_source; ///< The source of time (Eg. INTERNAL_OSC). +} ptp_message_announce_t; + +/** Signaling Message Type (0x0C). */ +typedef struct PTP_PACKED st_ptp_message_signaling +{ + uint8_t target_clock_id[8]; ///< ID of the target PTP instance. + uint16_t target_port_id; ///< Port of the target PTP instance. +} ptp_message_signaling_t; + +/** Management Message Type (0x0D). */ +typedef struct PTP_PACKED st_ptp_message_management +{ + uint8_t target_clock_id[8]; ///< ID of the target PTP instance. + uint16_t target_port_id; ///< Port of the target PTP instance. + uint8_t starting_boundary_hops; ///< The starting number of times the message is retransmitted by boundary clocks. + uint8_t boundary_hops; ///< The remaining number of retransmissions. + uint8_t action; ///< The action that will be taken on reception of the message. + uint8_t reserved; /* Reserved */ +} ptp_message_management_t; + +/** Complete PTP Message. */ +typedef struct PTP_PACKED st_ptp_message +{ + ptp_message_header_t header; ///< Header of the message. + union + { + ptp_message_announce_t announce; ///< Valid if this is an announce message. + ptp_message_sync_t sync; ///< Valid if this is a sync message. + ptp_message_follow_up_t follow_up; ///< Valid if this is an follow_up message. + ptp_message_delay_req_t delay_req; ///< Valid if this is a delay_req message. + ptp_message_delay_resp_t delay_resp; ///< Valid if this is a delay_resp message. + ptp_message_pdelay_req_t pdelay_req; ///< Valid if this is a p_delay_req message. + ptp_message_pdelay_resp_t pdelay_resp; ///< Valid if this is a p_delay_resp message. + ptp_message_pdelay_resp_follow_up_t pdelay_resp_followup; ///< Valid if this is a p_delay_resp_follow_up message. + ptp_message_signaling_t signaling; ///< Valid if this is a signaling message. + ptp_message_management_t management; ///< Valid if this is a management message. + }; +} ptp_message_t; + +/** Arguments passed to p_ptp_callback. */ +typedef struct st_ptp_callback_args +{ + ptp_event_t event; ///< Event that caused the callback. + ptp_message_t const * p_message; ///< The message received (PTP message fields will be little endian). + uint8_t const * p_tlv_data; ///< Start of TLV data (TLV data will be big endian). + uint16_t tlv_data_size; ///< Total bytes of TLV data. + uint32_t pulse_timer_channel; ///< Channel of the pulse timer that caused @ref ptp_event_t::PTP_EVENT_PULSE_TIMER_MINT_RISING_EDGE + void * p_context; ///< Context value set in the configuration. +} ptp_callback_args_t; + +/** Structure for configuring the IPLS IRQ settings that are common to all pulse timer channels. */ +typedef struct s_ptp_pulse_timer_common_cfg +{ + ptp_enable_t ipls_rising_irq; ///< Enable the IPLS IRQ when a rising edge is detected. + ptp_enable_t ipls_falling_irq; ///< Enable the IPLS IRQ when a falling edge is detected. + ptp_enable_t ipls_rising_irq_auto_clear; ///< Auto disable the rising edge IRQ after the first rising edge is detected. + ptp_enable_t ipls_falling_irq_auto_clear; ///< Auto disable the falling edge IRQ after the first falling edge is detected. +} ptp_pulse_timer_common_cfg_t; + +/** Structure for configuring a pulse timer channel. */ +typedef struct st_ptp_pulse_timer_cfg +{ + ptp_time_t start_time; ///< The exact time when the timer will start. + uint32_t period; ///< The period of the timer in nanoseconds. + uint32_t pulse; ///< The pulse width of the timer in nanoseconds. + ptp_enable_t mint_rising_irq; ///< Enable MINT rising edge IRQ. + ptp_enable_t ipls_rising_event; ///< Enable IPLS rising edge ELC event. + ptp_enable_t ipls_falling_event; ///< Enable IPLS falling edge ELC event. + ptp_enable_t ipls_rising_event_auto_clear; ///< Enable IPLS rising edge ELC event. + ptp_enable_t ipls_falling_event_auto_clear; ///< Enable IPLS falling edge ELC event. + ptp_enable_t ipls_irq_source; ///< Enable using this channel as a source for the IPLS IRQ. +} ptp_pulse_timer_cfg_t; + +/** Configuration settings for determining when the PTP clock is synchronized. */ +typedef struct st_ptp_sync_state_cfg +{ + /** The maximum clock offset required to transition between synchronization states. */ + uint64_t threshold; + + /** + * The number of times the clock must be above the threshold in order to transition + * between synchronization states. + */ + uint8_t count; +} ptp_sync_state_cfg_t; + +/** Configuration settings for the SYNFP. */ +typedef struct st_ptp_synfp_cfg +{ + ptp_ethernet_phy_interface_t ethernet_phy_interface; ///< The type of interface used to communicate with the PHY. + ptp_frame_format_t frame_format; ///< Frame format used to transport PTP messages. + ptp_frame_filter_mode_t frame_filter; ///< Frame filter mode. + uint8_t clock_domain; ///< Clock domain that the clock operates in. + ptp_enable_t clock_domain_filter; ///< Filter out messages from other clock domains. + ptp_message_interval_t announce_interval; ///< Interval for transmitting announce messages. + ptp_message_interval_t sync_interval; ///< Interval for transmitting sync messages. + ptp_message_interval_t delay_req_interval; ///< Interval for transmitting delay_req messages. + uint32_t message_timeout; ///< Timeout in milliseconds for receiving PTP messages. + ptp_clock_properties_t clock_properties; ///< Clock properties used in annonce messages. + uint8_t timesource; ///< TimeSource field used in announce messages. + uint8_t * p_multicast_addr_filter; ///< Filter for multicast packets. + + /** Valid if frame_format is set to Ethernet II or IEEE 802.3. */ + struct + { + uint8_t * p_primary_mac_addr; ///< The MAC address to send primary messages. + uint8_t * p_pdelay_mac_addr; ///< The MAC address to send p2p messages. + } ether; + + /** Valid if frame_format is set to IPV4_UDP. */ + struct + { + uint32_t primary_ip_addr; ///< The IP address to send primary messages. + uint32_t pdelay_ip_addr; ///< The IP address to send pdelay messages. + uint8_t event_tos; ///< Type of service for event messages. + uint8_t general_tos; ///< Type of service for general messages. + uint8_t primary_ttl; ///< Time to live for primary messages. + uint8_t pdelay_ttl; ///< Time to live for pdelay messages. + uint16_t event_udp_port; ///< The port to send event messages. + uint16_t general_udp_port; ///< The port to send general messages. + } ipv4; +} ptp_synfp_cfg_t; + +/** Configuration settings for the STCA. */ +typedef struct st_ptp_stca_cfg +{ + ptp_stca_clock_freq_t clock_freq; ///< Select the clock frequency of the STCA. + ptp_stca_clock_sel_t clock_sel; ///< Select the input clock to the STCA. + ptp_clock_correction_mode_t clock_correction_mode; ///< Select the clock correction mode. + uint8_t gradient_worst10_interval; ///< Select the interval for the gradient worst10 acquisition. + ptp_sync_state_cfg_t sync_threshold; ///< Configure the synchronization threshold. + ptp_sync_state_cfg_t sync_loss_threshold; ///< Configure the SYnchronization lost threshold. +} ptp_stca_cfg_t; + +/** User configuration structure, used in open function */ +typedef struct st_ptp_cfg +{ + ptp_synfp_cfg_t synfp; ///< Configuration settings for the SYNFP. + ptp_stca_cfg_t stca; ///< Configuration settings for the STCA. + edmac_instance_t * p_edmac_instance; ///< Pointer to PTP edmac instance. + uint16_t buffer_size; ///< The maximum Ethernet packet size that can be transmitted or received. + uint8_t ** p_rx_buffers; ///< Pointer to list of buffers used to receive PTP packets. + uint8_t ** p_tx_buffers; ///< Pointer to list of buffers used to transmit PTP packets. + IRQn_Type mint_irq; ///< Interrupt number for PTP event IRQ. + IRQn_Type ipls_irq; ///< Interrupt number for PTP timer IRQ. + uint8_t mint_ipl; ///< Interrupt priority of the PTP event IRQ. + uint8_t ipls_ipl; ///< Interrupt priority of the PTP timer IRQ. + + /** Callback for handling received PTP events. */ + void (* p_callback)(ptp_callback_args_t * p_args); + + void * p_context; + void const * p_extend; +} ptp_cfg_t; + +typedef void ptp_ctrl_t; + +/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */ +typedef struct st_ptp_api +{ + /** Initial configuration. + * + * @note To reconfigure after calling this function, call @ref ptp_api_t::close first. + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(ptp_ctrl_t * const p_ctrl, ptp_cfg_t const * const p_cfg); + + /** Set the MAC address for the PTP. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_hw_addr Pointer to the 6 byte MAC address. + */ + fsp_err_t (* macAddrSet)(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_mac_addr); + + /** Set the IP address for the PTP. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] ip_addr 32 bit IPv4 address of the PTP. + */ + fsp_err_t (* ipAddrSet)(ptp_ctrl_t * const p_ctrl, uint32_t ip_addr); + + /** Set the local clock ID (Usually based off of the PTP MAC address). + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_clock_id Pointer to 8 byte clock ID. + */ + fsp_err_t (* localClockIdSet)(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_clock_id); + + /** Set the master clock ID (Usually obtained from previously received announce message). + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_clock_id Pointer to 8 byte clock ID. + * @param[in] port_id The port on the master clock. + */ + fsp_err_t (* masterClockIdSet)(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_clock_id, uint16_t port_id); + + /** Set the flags field for the given message type. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] message_type The message type. + * @param[in] flags Flags to set. + */ + fsp_err_t (* messageFlagsSet)(ptp_ctrl_t * const p_ctrl, ptp_message_type_t message_type, + ptp_message_flags_t flags); + + /** Sets the offsetFromMaster field in announce messages. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] offset New currentUtcOffset value. + */ + fsp_err_t (* currentUtcOffsetSet)(ptp_ctrl_t * const p_ctrl, uint16_t offset); + + /** Transition to a new clock state. + * + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] state The state to transition into. + */ + fsp_err_t (* portStateSet)(ptp_ctrl_t * const p_ctrl, uint32_t state); + + /** Send a PTP message. Appropriate fields in the PTP message will be endian swapped. + * The application must ensure that the TLV data is in big endian format. + * + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_message Pointer to a PTP message. + * @param[in] p_tlv_data Pointer to TLV data that is appended to the end of the PTP message. + * @param[in] tlv_data_size Size of the TLV data in bytes. + */ + fsp_err_t (* messageSend)(ptp_ctrl_t * const p_ctrl, ptp_message_t const * const p_message, + uint8_t const * const p_tlv_data, uint16_t tlv_data_size); + + /** Set the local clock value. + * + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_time Pointer to the new time setting. + */ + fsp_err_t (* localClockValueSet)(ptp_ctrl_t * const p_ctrl, ptp_time_t const * const p_time); + + /** Get the local clock value. + * + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_time Pointer to store the current time setting. + */ + fsp_err_t (* localClockValueGet)(ptp_ctrl_t * const p_ctrl, ptp_time_t * const p_time); + + /** Configuration that is common to all of the pulse timers. + * + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_timer_cfg Pointer to the pulse timer common configuration. + */ + fsp_err_t (* pulseTimerCommonConfig)(ptp_ctrl_t * const p_ctrl, ptp_pulse_timer_common_cfg_t * p_timer_cfg); + + /** Setup a pulse timer. + * + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] channel The pulse timer channel to setup. + * @param[in] p_timer_cfg Pointer to the pulse timer configuration. + */ + fsp_err_t (* pulseTimerEnable)(ptp_ctrl_t * const p_ctrl, uint32_t channel, + ptp_pulse_timer_cfg_t * const p_timer_cfg); + + /** Stop a pulse timer. + * + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] channel The pulse timer channel to stop. + */ + fsp_err_t (* pulseTimerDisable)(ptp_ctrl_t * const p_ctrl, uint32_t channel); + + /** Stop PTP operation. + * + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(ptp_ctrl_t * const p_ctrl); +} ptp_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ptp_instance +{ + ptp_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ptp_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ptp_api_t const * p_api; ///< Pointer to the API structure for this instance +} ptp_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup PTP_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_rtc_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_rtc_api.h new file mode 100644 index 0000000000..60ddd3af8c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_rtc_api.h @@ -0,0 +1,349 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RTC_API_H +#define R_RTC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_TIMERS_INTERFACES + * @defgroup RTC_API RTC Interface + * @brief Interface for accessing the Realtime Clock. + * + * + * @section RTC_API_Summary Summary + * The RTC Interface is for configuring Real Time Clock (RTC) functionality including alarm, periodic notification and + * error adjustment. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Use of time structure, tm */ +#include + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_RTC_EVENT_T + +/** Events that can trigger a callback function */ +typedef enum e_rtc_event +{ + RTC_EVENT_ALARM_IRQ, ///< Real Time Clock ALARM 0 IRQ + RTC_EVENT_ALARM1_IRQ, ///< Real Time Clock ALARM 1 IRQ + RTC_EVENT_PERIODIC_IRQ, ///< Real Time Clock PERIODIC IRQ +} rtc_event_t; +#endif + +/** RTC alarm channel */ +typedef enum e_rtc_alarm_channel +{ + RTC_ALARM_CHANNEL_0, + RTC_ALARM_CHANNEL_1, +} rtc_alarm_channel_t; + +/** Callback function parameter data */ +typedef struct st_rtc_callback_args +{ + rtc_event_t event; ///< The event can be used to identify what caused the callback (compare match or error). + void * p_context; ///< Placeholder for user data. +} rtc_callback_args_t; + +/** Clock source for the RTC block */ +typedef enum e_rtc_count_source +{ + RTC_CLOCK_SOURCE_SUBCLK = 0, ///< Sub-clock oscillator + RTC_CLOCK_SOURCE_LOCO = 1, ///< Low power On Chip Oscillator + RTC_CLOCK_SOURCE_MAINCLK = 2 ///< Main clock oscillator +} rtc_clock_source_t; + +/** RTC run state */ +typedef enum e_rtc_status +{ + RTC_STATUS_STOPPED = 0, ///< RTC counter is stopped + RTC_STATUS_RUNNING = 1 ///< RTC counter is running +} rtc_status_t; + +/** Time error adjustment settings */ +typedef enum e_rtc_error_adjustment +{ + RTC_ERROR_ADJUSTMENT_NONE = 0, ///< Adjustment is not performed + RTC_ERROR_ADJUSTMENT_ADD_PRESCALER = 1, ///< Adjustment is performed by the addition to the prescaler + RTC_ERROR_ADJUSTMENT_SUBTRACT_PRESCALER = 2, ///< Adjustment is performed by the subtraction from the prescaler +} rtc_error_adjustment_t; + +/** Time error adjustment mode settings */ +typedef enum e_rtc_error_adjustment_mode +{ + RTC_ERROR_ADJUSTMENT_MODE_MANUAL = 0, ///< Adjustment mode is set to manual + RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC = 1, ///< Adjustment mode is set to automatic +} rtc_error_adjustment_mode_t; + +/** Time error adjustment period settings */ +typedef enum e_rtc_error_adjustment_period +{ + RTC_ERROR_ADJUSTMENT_PERIOD_1_MINUTE = 0, ///< Adjustment period is set to every one minute + RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND = 1, ///< Adjustment period is set to every ten second + RTC_ERROR_ADJUSTMENT_PERIOD_NONE = 2, ///< Adjustment period not supported in manual mode + RTC_ERROR_ADJUSTMENT_PERIOD_20_SECOND = 3, ///< Adjustment period is set to every twenty seconds +} rtc_error_adjustment_period_t; + +/** Time error adjustment value configuration */ +typedef struct st_rtc_error_adjustment_cfg +{ + rtc_error_adjustment_mode_t adjustment_mode; ///< Automatic Adjustment Enable/Disable + rtc_error_adjustment_period_t adjustment_period; ///< Error Adjustment period + rtc_error_adjustment_t adjustment_type; ///< Time error adjustment setting + uint32_t adjustment_value; ///< Value of the prescaler for error adjustment +} rtc_error_adjustment_cfg_t; + +#ifndef BSP_OVERRIDE_RTC_PERIODIC_IRQ_SELECT_T + +/** Periodic Interrupt select */ +typedef enum e_rtc_periodic_irq_select +{ + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_256_SECOND = 6, ///< A periodic irq is generated every 1/256 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_128_SECOND = 7, ///< A periodic irq is generated every 1/128 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_64_SECOND = 8, ///< A periodic irq is generated every 1/64 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_32_SECOND = 9, ///< A periodic irq is generated every 1/32 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_16_SECOND = 10, ///< A periodic irq is generated every 1/16 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_8_SECOND = 11, ///< A periodic irq is generated every 1/8 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_4_SECOND = 12, ///< A periodic irq is generated every 1/4 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_2_SECOND = 13, ///< A periodic irq is generated every 1/2 second + RTC_PERIODIC_IRQ_SELECT_1_SECOND = 14, ///< A periodic irq is generated every 1 second + RTC_PERIODIC_IRQ_SELECT_2_SECOND = 15, ///< A periodic irq is generated every 2 seconds + RTC_PERIODIC_IRQ_SELECT_1_MINUTE = 16, ///< A periodic irq is generated every 1 minute + RTC_PERIODIC_IRQ_SELECT_1_HOUR = 17, ///< A periodic irq is generated every 1 hour + RTC_PERIODIC_IRQ_SELECT_1_DAY = 18, ///< A periodic irq is generated every 1 day + RTC_PERIODIC_IRQ_SELECT_1_MONTH = 19, ///< A periodic irq is generated every 1 month +} rtc_periodic_irq_select_t; +#endif + +#ifndef BSP_OVERRIDE_RTC_TIME_CAPTURE_SOURCE_T + +/** Time capture trigger source */ +typedef enum e_rtc_time_capture_source +{ + RTC_TIME_CAPTURE_SOURCE_DISABLED = 0, ///< Disable trigger + RTC_TIME_CAPTURE_SOURCE_PIN_RISING = 1, ///< Rising edge pin trigger + RTC_TIME_CAPTURE_SOURCE_PIN_FALLING = 2, ///< Falling edge pin trigger + RTC_TIME_CAPTURE_SOURCE_PIN_BOTH = 3, ///< Both edges pin trigger + RTC_TIME_CAPTURE_SOURCE_SOFTWARE = 4, ///< Software trigger + RTC_TIME_CAPTURE_SOURCE_ELC_EVENT = 5, ///< ELC event trigger +} rtc_time_capture_source_t; +#endif + +/** Time capture trigger mode */ +typedef enum e_rtc_time_capture_mode +{ + RTC_TIME_CAPTURE_MODE_CONTINUOUS = 0, ///< Continuous capturing to all capturing channels + RTC_TIME_CAPTURE_MODE_ONE_SHOT = 1, ///< Single capture to a particular channel +} rtc_time_capture_mode_t; + +/** Time capture noise filter control */ +typedef enum e_rtc_time_capture_noise_filter +{ + RTC_TIME_CAPTURE_NOISE_FILTER_OFF = 0, ///< Turn noise filter off + RTC_TIME_CAPTURE_NOISE_FILTER_ON = 2, ///< Turn noise filter on (count source) + RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_32 = 3, ///< Turn noise filter on (count source by divided by 32) + RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_4096 = 4, ///< Turn noise filter on (count source by divided by 4096) + RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_8192 = 5, ///< Turn noise filter on (count source by divided by 8192) +} rtc_time_capture_noise_filter_t; + +/** Date and time structure defined in C standard library */ +typedef struct tm rtc_time_t; + +#ifndef BSP_OVERRIDE_RTC_ALARM_TIME_T + +/** Alarm time setting structure */ +typedef struct st_rtc_alarm_time +{ + rtc_time_t time; ///< Time structure + bool sec_match; ///< Enable the alarm based on a match of the seconds field + bool min_match; ///< Enable the alarm based on a match of the minutes field + bool hour_match; ///< Enable the alarm based on a match of the hours field + bool mday_match; ///< Enable the alarm based on a match of the days field + bool mon_match; ///< Enable the alarm based on a match of the months field + bool year_match; ///< Enable the alarm based on a match of the years field + bool dayofweek_match; ///< Enable the alarm based on a match of the dayofweek field + bool sunday_match; ///< Enable the alarm on Sunday + bool monday_match; ///< Enable the alarm on Monday + bool tuesday_match; ///< Enable the alarm on Tuesday + bool wednesday_match; ///< Enable the alarm on Wednesday + bool thursday_match; ///< Enable the alarm on Thursday + bool friday_match; ///< Enable the alarm on Friday + bool saturday_match; ///< Enable the alarm on Saturday + rtc_alarm_channel_t channel; ///< Select alarm 0 or alarm 1 +} rtc_alarm_time_t; +#endif + +/** Time capture configuration structure */ +typedef struct st_rtc_time_capture +{ + rtc_time_t time; ///< Time structure + uint8_t channel; ///< Capture channel + rtc_time_capture_source_t source; ///< Trigger source + rtc_time_capture_noise_filter_t noise_filter; ///< Noise filter + rtc_time_capture_mode_t mode; ///< Capture mode +} rtc_time_capture_t; + +/** RTC Information Structure for information returned by infoGet() */ +typedef struct st_rtc_info +{ + rtc_clock_source_t clock_source; ///< Clock source for the RTC block + rtc_status_t status; ///< RTC run status +} rtc_info_t; + +/** User configuration structure, used in open function */ +typedef struct st_rtc_cfg +{ + rtc_clock_source_t clock_source; ///< Clock source for the RTC block + uint32_t freq_compare_value; ///< The frequency comparison value + rtc_error_adjustment_cfg_t const * const p_err_cfg; ///< Pointer to Error Adjustment configuration + uint8_t alarm_ipl; ///< Alarm interrupt priority + IRQn_Type alarm_irq; ///< Alarm interrupt vector + uint8_t periodic_ipl; ///< Periodic interrupt priority + IRQn_Type periodic_irq; ///< Periodic interrupt vector + uint8_t carry_ipl; ///< Carry interrupt priority + IRQn_Type carry_irq; ///< Carry interrupt vector + void (* p_callback)(rtc_callback_args_t * p_args); ///< Called from the ISR. + void * p_context; ///< User defined context passed into callback function. + void const * p_extend; ///< RTC hardware dependant configuration. +} rtc_cfg_t; + +/** RTC control block. Allocate an instance specific control block to pass into the RTC API calls. + */ +typedef void rtc_ctrl_t; + +/** RTC driver structure. General RTC functions implemented at the HAL layer follow this API. */ +typedef struct st_rtc_api +{ + /** Open the RTC driver. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_cfg Pointer to the configuration structure + */ + fsp_err_t (* open)(rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); + + /** Close the RTC driver. + * + * @param[in] p_ctrl Pointer to RTC device handle. + */ + fsp_err_t (* close)(rtc_ctrl_t * const p_ctrl); + + /** Sets the RTC clock source. + * + * @param[in] p_ctrl Pointer to RTC device handle + */ + fsp_err_t (* clockSourceSet)(rtc_ctrl_t * const p_ctrl); + + /** Set the calendar time and start the calendar counter + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_time Pointer to a time structure that contains the time to set + */ + fsp_err_t (* calendarTimeSet)(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); + + /** Get the calendar time. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_time Pointer to a time structure that contains the time to get + */ + fsp_err_t (* calendarTimeGet)(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); + + /** Set the calendar alarm time and enable the alarm interrupt. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_alarm Pointer to an alarm structure that contains the alarm time to set + */ + fsp_err_t (* calendarAlarmSet)(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); + + /** Get the calendar alarm time. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_alarm Pointer to an alarm structure to fill up with the alarm time + */ + fsp_err_t (* calendarAlarmGet)(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); + + /** Set the periodic irq rate + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] rate Rate of periodic interrupts + */ + fsp_err_t (* periodicIrqRateSet)(rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_select_t const rate); + + /** Set time error adjustment. + * + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] err_adj_cfg Pointer to the Error Adjustment Config + */ + fsp_err_t (* errorAdjustmentSet)(rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the RTC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated + */ + fsp_err_t (* callbackSet)(rtc_ctrl_t * const p_ctrl, void (* p_callback)(rtc_callback_args_t *), + void * const p_context, rtc_callback_args_t * const p_callback_memory); + + /** Return the currently configure clock source for the RTC + * + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_rtc_info Pointer to RTC information structure + */ + fsp_err_t (* infoGet)(rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info); + + /** Config Time capture + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_time_capture Pointer to a time capture structure that contains the configuration + */ + fsp_err_t (* timeCaptureSet)(rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture); + + /** Get the capture time and clear bit status. + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_time_capture Pointer to a time capture structure to fill up with the time capture + */ + fsp_err_t (* timeCaptureGet)(rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture); +} rtc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_rtc_instance +{ + rtc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + rtc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + rtc_api_t const * p_api; ///< Pointer to the API structure for this instance +} rtc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup RTC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_sdmmc_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_sdmmc_api.h new file mode 100644 index 0000000000..078920f368 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_sdmmc_api.h @@ -0,0 +1,496 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SDMMC_API_H +#define R_SDMMC_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @ingroup RENESAS_STORAGE_INTERFACES + * @defgroup SDMMC_API SD/MMC Interface + * @brief Interface for accessing SD, eMMC, and SDIO devices. + * + * @section SDMMC_API_SUMMARY Summary + * The r_sdhi interface provides standard SD and eMMC media functionality. This interface also supports SDIO. + * + * + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** SD/MMC media uses SD protocol or MMC protocol. */ +typedef enum e_sdmmc_card_type +{ + SDMMC_CARD_TYPE_MMC = 0, ///< The media is an eMMC device. + SDMMC_CARD_TYPE_SD = 1, ///< The media is an SD card. + SDMMC_CARD_TYPE_SDIO = 2, ///< The media is an SDIO card. +} sdmmc_card_type_t; + +/** SD/MMC data bus is 1, 4 or 8 bits wide. */ +typedef enum e_sdmmc_bus_width +{ + SDMMC_BUS_WIDTH_1_BIT = 1, ///< Data bus is 1 bit wide. + SDMMC_BUS_WIDTH_4_BITS = 4, ///< Data bus is 4 bits wide. + SDMMC_BUS_WIDTH_8_BITS = 8, ///< Data bus is 8 bits wide. +} sdmmc_bus_width_t; + +/** SDIO transfer mode, configurable in SDIO read/write extended commands. */ +typedef enum e_sdmmc_io_transfer_mode +{ + SDMMC_IO_MODE_TRANSFER_BYTE = 0, ///< SDIO byte transfer mode + SDMMC_IO_MODE_TRANSFER_BLOCK ///< SDIO block transfer mode +} sdmmc_io_transfer_mode_t; + +/** SDIO address mode, configurable in SDIO read/write extended commands. */ +typedef enum e_sdmmc_io_address_mode +{ + SDMMC_IO_ADDRESS_MODE_FIXED = 0, ///< Write all data to the same address + SDMMC_IO_ADDRESS_MODE_INCREMENT ///< Increment destination address after each write +} sdmmc_io_address_mode_t; + +/** Controls the RAW (read after write) flag of CMD52. Used to read back the status after writing a control register. */ +typedef enum e_sdmmc_io_write_mode +{ + SDMMC_IO_WRITE_MODE_NO_READ = 0, ///< Write only (do not read back) + SDMMC_IO_WRITE_READ_AFTER_WRITE ///< Read back the register after write +} sdmmc_io_write_mode_t; + +/** Events that can trigger a callback function */ +typedef enum e_sdmmc_event +{ + SDMMC_EVENT_CARD_REMOVED = 1U << 0, ///< Card removed event. + SDMMC_EVENT_CARD_INSERTED = 1U << 1, ///< Card inserted event. + SDMMC_EVENT_RESPONSE = 1U << 3, ///< Response event. + SDMMC_EVENT_SDIO = 1U << 4, ///< IO event. + SDMMC_EVENT_TRANSFER_COMPLETE = 1U << 5, ///< Read or write complete. + SDMMC_EVENT_TRANSFER_ERROR = 1U << 6, ///< Read or write failed. + SDMMC_EVENT_ERASE_COMPLETE = 1U << 7, ///< Erase completed. + SDMMC_EVENT_ERASE_BUSY = 1U << 8, ///< Erase timeout, poll @ref sdmmc_api_t::statusGet. +} sdmmc_event_t; + +/** Card detection configuration options. */ +/* Card detection using DAT3 is not supported. */ +typedef enum e_sdmmc_card_detect +{ + SDMMC_CARD_DETECT_NONE, ///< Card detection unused. + SDMMC_CARD_DETECT_CD, ///< Card detection using the CD pin +} sdmmc_card_detect_t; + +/** Write protection configuration options. */ +typedef enum e_sdmmc_write_protect +{ + SDMMC_WRITE_PROTECT_NONE, ///< Write protection unused. + SDMMC_WRITE_PROTECT_WP, ///< Write protection using WP pin +} sdmmc_write_protect_t; + +/** Card state when receiving the prior command. */ +typedef enum e_sdmmc_r1_state +{ + SDMMC_R1_STATE_IDLE = 0, ///< Idle State + SDMMC_R1_STATE_READY = 0, ///< Ready State + SDMMC_R1_STATE_IDENT = 0, ///< Identification State + SDMMC_R1_STATE_STBY = 0, ///< Stand-by State + SDMMC_R1_STATE_TRAN = 0, ///< Transfer State + SDMMC_R1_STATE_DATA = 0, ///< Sending-data State + SDMMC_R1_STATE_RCV = 0, ///< Receive-data State + SDMMC_R1_STATE_PRG = 0, ///< Programming State + SDMMC_R1_STATE_DIS = 0, ///< Disconnect State (between programming and stand-by) + SDMMC_R1_STATE_IO = 15, ///< This is an I/O card and memory states do not apply +} sdmmc_r1_state_t; + +/* Structure for decoding the response of a command. For advanced use only. */ +typedef union u_sdmmc_response +{ + uint32_t status; + + /** SDIO Card Status Register. */ + struct + { + uint32_t : 3; + uint32_t ake_seq_error : 1; // Error in the sequence of the authentication process + uint32_t : 1; + uint32_t app_cmd : 1; // The card will expect ACMD, or an indication that the command has been interpreted as ACMD + uint32_t fx_event : 1; // Extension Functions may set this bit to get host to deal with events + uint32_t switch_error : 1; // + uint32_t ready_for_data : 1; // Corresponds to the buffer empty signaling on the bus + + /* The state of the card when receiving the command. If the command execution causes a state change, it will be + * visible to the host in the response to the next command. */ + sdmmc_r1_state_t current_state : 4; + uint32_t erase_reset : 1; // An erase sequence was cleared before executing because an out of erase sequence command was received. + uint32_t card_ecc_disabled : 1; // The command has been executed without using the internal ECC. + uint32_t wp_erase_skip : 1; // Set when only partial address space was erased due to existing write protected blocks or the temporary or permanent write protected card was erased. + uint32_t csd_overwrite : 1; // The read only section of the CSD does not match the card content or an attempt to reverse the copy or permanent WP bits was made. + uint32_t : 2; + uint32_t error : 1; // A general or unknown error occurred during the operation. + uint32_t cc_error : 1; // Internal card controller error. + uint32_t card_ecc_failed : 1; // Card internal ECC was applied but failed to correct the data. + uint32_t illegal_command : 1; // Command not legal for the card state. + uint32_t com_crc_error : 1; // The CRC check of the previous command failed. + uint32_t lock_unlock_failed : 1; // Set when a sequence or password error has been detected in the lock/unlock command. + uint32_t device_is_locked : 1; // When set, signals that the card is locked by the host. + uint32_t wp_violation : 1; // Set when the host attempts to write to a protected block or to the temporary or permanent write protected card. + uint32_t erase_param : 1; // An invalid selection of write-blocks for erase occurred. + uint32_t erase_seq_error : 1; // An error in the sequence of erase commands occurred. + uint32_t block_len_error : 1; // The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length. + uint32_t address_error : 1; // A misaligned address which did not match the block length was used in the command. + uint32_t out_of_range : 1; // The command's argument was out of the allowed range for this card. + } status_b; + + struct + { + uint32_t reserved_0 : 7; + + uint32_t reserved_lvr : 1; + uint32_t reserved_8 : 7; + uint32_t v_27_28 : 1; + uint32_t v_28_29 : 1; + uint32_t v_29_30 : 1; + uint32_t v_30_31 : 1; + uint32_t v_31_32 : 1; + uint32_t v_32_33 : 1; + uint32_t v_33_34 : 1; + uint32_t v_34_35 : 1; + uint32_t v_35_36 : 1; + uint32_t s18A : 1; + uint32_t reserved_25 : 5; + uint32_t card_capacity_status : 1; + uint32_t power_up_status : 1; + } r3; + + struct + { + uint32_t ocr : 24; + + uint32_t reserved_24 : 3; + uint32_t memory : 1; + uint32_t io_functions : 3; + uint32_t ready : 1; + } r4; + + struct + { + uint32_t read_write_data : 8; + + uint32_t out_of_range : 1; + uint32_t invalid_function : 1; + uint32_t rfu : 1; + uint32_t error : 1; + uint32_t current_state : 2; + uint32_t illegal_command : 1; + uint32_t crc_error : 1; + uint32_t reserved_16 : 16; + } r5; + + struct + { + uint32_t reserved_0 : 3; + + uint32_t ake_seq_error : 1; + uint32_t reserved_4 : 1; + uint32_t app_cmd : 1; + uint32_t reserved_6 : 2; + uint32_t ready_for_data : 1; + sdmmc_r1_state_t current_state : 4; + uint32_t error : 1; + uint32_t illegal_command : 1; + uint32_t com_crc_error : 1; + uint32_t rca : 16; + } r6; + + struct + { + uint32_t check_pattern : 8; + + uint32_t voltage_accepted : 4; + uint32_t reserved_11 : 20; + } r7; +} sdmmc_response_t; + +/** Current status. */ +typedef struct s_sdmmc_status +{ + /** False if card was removed (only applies if MCU supports card detection and SDnCD pin is connected), true otherwise. + * + * If ready is false, call @ref sdmmc_api_t::mediaInit to reinitialize it + */ + bool initialized; + bool transfer_in_progress; ///< true = Card is busy + bool card_inserted; ///< Card detect status, true if card detect is not used +} sdmmc_status_t; + +/** Information obtained from the media device. */ +typedef struct s_sdmmc_device +{ + sdmmc_card_type_t card_type; ///< SD, eMMC, or SDIO + bool write_protected; ///< true = Card is write protected + uint32_t clock_rate; ///< Current clock rate + uint32_t sector_count; ///< Sector count + uint32_t sector_size_bytes; ///< Sector size + uint32_t erase_sector_count; ///< Minimum erasable unit (in 512 byte sectors) +} sdmmc_device_t; + +/** Callback function parameter data */ +typedef struct st_sdmmc_callback_args +{ + sdmmc_event_t event; ///< The event can be used to identify what caused the callback. + sdmmc_response_t response; ///< Response from card, only valid if SDMMC_EVENT_RESPONSE is set in event. + void * p_context; ///< Placeholder for user data. +} sdmmc_callback_args_t; + +/** Non-secure arguments for writeIo guard function */ +typedef struct st_sdmmc_write_io_args_t +{ + uint8_t * const p_data; + uint32_t function; + uint32_t address; + sdmmc_io_write_mode_t read_after_write; +} sdmmc_write_io_args_t; + +/** Non-secure arguments for readIoExt guard function */ +typedef struct st_sdmmc_read_io_ext_args_t +{ + uint8_t * const p_dest; + uint32_t function; + uint32_t address; + uint32_t * const count; + sdmmc_io_transfer_mode_t transfer_mode; + sdmmc_io_address_mode_t address_mode; +} sdmmc_read_io_ext_args_t; + +/** Non-secure arguments for writeIoExt guard function */ +typedef struct st_sdmmc_write_io_ext_args_t +{ + uint8_t const * const p_source; + uint32_t function; + uint32_t address; + uint32_t count; + sdmmc_io_transfer_mode_t transfer_mode; + sdmmc_io_address_mode_t address_mode; +} sdmmc_write_io_ext_args_t; + +/** SD/MMC Configuration */ +typedef struct st_sdmmc_cfg +{ + /* SD/MMC generic configuration */ + uint8_t channel; ///< Channel of SD/MMC host interface. + sdmmc_bus_width_t bus_width; ///< Device bus width is 1, 4 or 8 bits wide. + transfer_instance_t const * p_lower_lvl_transfer; ///< Transfer instance used to move data with DMA or DTC + + /* Configuration for SD/MMC Event processing */ + void (* p_callback)(sdmmc_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /* Pointer to SD/MMC peripheral specific configuration */ + void const * p_extend; ///< SD/MMC hardware dependent configuration + + /** Block size in bytes. Block size must be 512 bytes for SD cards and eMMC devices. Block size can be 1-512 + * bytes for SDIO. */ + uint32_t block_size; + + /** Whether or not card detection is used. */ + sdmmc_card_detect_t card_detect; + + /** Select whether or not to use the write protect pin. Select Not Used if the MCU or device does not have a write protect pin. */ + sdmmc_write_protect_t write_protect; + IRQn_Type access_irq; ///< Access IRQ number + IRQn_Type sdio_irq; ///< SDIO IRQ number + IRQn_Type card_irq; ///< Card IRQ number + IRQn_Type dma_req_irq; ///< DMA request IRQ number + uint8_t access_ipl; ///< Access interrupt priority + uint8_t sdio_ipl; ///< SDIO interrupt priority + uint8_t card_ipl; ///< Card interrupt priority + uint8_t dma_req_ipl; ///< DMA request interrupt priority +} sdmmc_cfg_t; + +/** SD/MMC control block. Allocate an instance specific control block to pass into the SD/MMC API calls. + */ +typedef void sdmmc_ctrl_t; + +/** SD/MMC functions implemented at the HAL layer API. */ +typedef struct st_sdmmc_api +{ + /** Open the SD/MMC driver. + * + * + * @param[in] p_ctrl Pointer to SD/MMC instance control block. + * @param[in] p_cfg Pointer to SD/MMC instance configuration structure. + */ + fsp_err_t (* open)(sdmmc_ctrl_t * const p_ctrl, sdmmc_cfg_t const * const p_cfg); + + /** Initializes an SD/MMC device. If the device is a card, the card must be plugged in prior to calling this API. + * This API blocks until the device initialization procedure is complete. + * + * + * @param[in] p_ctrl Pointer to SD/MMC instance control block. + * @param[out] p_device Pointer to store device information. + */ + fsp_err_t (* mediaInit)(sdmmc_ctrl_t * const p_ctrl, sdmmc_device_t * const p_device); + + /** Read data from an SD/MMC channel. + * This API is not supported for SDIO devices. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[out] p_dest Pointer to data buffer to read data to. + * @param[in] start_sector First sector address to read. + * @param[in] sector_count Number of sectors to read. All sectors must be in the range of + * sdmmc_device_t::sector_count. + */ + fsp_err_t (* read)(sdmmc_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const start_sector, + uint32_t const sector_count); + + /** Write data to SD/MMC channel. + * This API is not supported for SDIO devices. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in] p_source Pointer to data buffer to write data from. + * @param[in] start_sector First sector address to write to. + * @param[in] sector_count Number of sectors to write. All sectors must be in the range of + * sdmmc_device_t::sector_count. + */ + fsp_err_t (* write)(sdmmc_ctrl_t * const p_ctrl, uint8_t const * const p_source, uint32_t const start_sector, + uint32_t const sector_count); + + /** Read one byte of I/O data from an SDIO device. + * This API is not supported for SD or eMMC memory devices. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[out] p_data Pointer to location to store data byte. + * @param[in] function SDIO Function Number. + * @param[in] address SDIO register address. + */ + fsp_err_t (* readIo)(sdmmc_ctrl_t * const p_ctrl, uint8_t * const p_data, uint32_t const function, + uint32_t const address); + + /** Write one byte of I/O data to an SDIO device. + * This API is not supported for SD or eMMC memory devices. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in,out] p_data Pointer to data byte to write. Read data is also provided here if + * read_after_write is true. + * @param[in] function SDIO Function Number. + * @param[in] address SDIO register address. + * @param[in] read_after_write Whether or not to read back the same register after writing + */ + fsp_err_t (* writeIo)(sdmmc_ctrl_t * const p_ctrl, uint8_t * const p_data, uint32_t const function, + uint32_t const address, sdmmc_io_write_mode_t const read_after_write); + + /** Read multiple bytes or blocks of I/O data from an SDIO device. + * This API is not supported for SD or eMMC memory devices. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[out] p_dest Pointer to data buffer to read data to. + * @param[in] function SDIO Function Number. + * @param[in] address SDIO register address. + * @param[in] count Number of bytes or blocks to read, maximum 512 bytes or 511 blocks. + * @param[in] transfer_mode Byte or block mode + * @param[in] address_mode Fixed or incrementing address mode + */ + fsp_err_t (* readIoExt)(sdmmc_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const function, + uint32_t const address, uint32_t * const count, sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode); + + /** Write multiple bytes or blocks of I/O data to an SDIO device. + * This API is not supported for SD or eMMC memory devices. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in] p_source Pointer to data buffer to write data from. + * @param[in] function_number SDIO Function Number. + * @param[in] address SDIO register address. + * @param[in] count Number of bytes or blocks to write, maximum 512 bytes or 511 blocks. + * @param[in] transfer_mode Byte or block mode + * @param[in] address_mode Fixed or incrementing address mode + */ + fsp_err_t (* writeIoExt)(sdmmc_ctrl_t * const p_ctrl, uint8_t const * const p_source, uint32_t const function, + uint32_t const address, uint32_t const count, sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode); + + /** Enables SDIO interrupt for SD/MMC instance. + * This API is not supported for SD or eMMC memory devices. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in] enable Interrupt enable = true, interrupt disable = false. + */ + fsp_err_t (* ioIntEnable)(sdmmc_ctrl_t * const p_ctrl, bool enable); + + /** Get SD/MMC device status. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[out] p_status Pointer to current driver status. + */ + fsp_err_t (* statusGet)(sdmmc_ctrl_t * const p_ctrl, sdmmc_status_t * const p_status); + + /** Erase SD/MMC sectors. The sector size for erase is fixed at 512 bytes. + * This API is not supported for SDIO devices. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in] start_sector First sector to erase. Must be a multiple of sdmmc_device_t::erase_sector_count. + * @param[in] sector_count Number of sectors to erase. Must be a multiple of sdmmc_device_t::erase_sector_count. + * All sectors must be in the range of sdmmc_device_t::sector_count. + */ + fsp_err_t (* erase)(sdmmc_ctrl_t * const p_ctrl, uint32_t const start_sector, uint32_t const sector_count); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref sdmmc_api_t::open call. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(sdmmc_ctrl_t * const p_ctrl, void (* p_callback)(sdmmc_callback_args_t *), + void * const p_context, sdmmc_callback_args_t * const p_callback_memory); + + /** Close open SD/MMC device. + * + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + */ + fsp_err_t (* close)(sdmmc_ctrl_t * const p_ctrl); +} sdmmc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_sdmmc_instance +{ + sdmmc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + sdmmc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + sdmmc_api_t const * p_api; ///< Pointer to the API structure for this instance +} sdmmc_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup SDMMC_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_smci_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_smci_api.h new file mode 100644 index 0000000000..31bd96c5ed --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_smci_api.h @@ -0,0 +1,275 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup SMCI_API SMCI Interface + * @brief Interface for SMCI communications. + * + * @section SMCI_INTERFACE_SUMMARY Summary + * The SMCI interface provides common APIs for SMCI HAL drivers. The SMCI interface supports the following features: + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code + * - Runtime baud-rate change (baud = 1/ETU) + * - Hardware resource locking during a transaction + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_SMCI_API_H +#define R_SMCI_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum e_smci_state +{ + SMCI_STATE_IDLE_CLOCK_OFF = 0U, ///< SMCI idle state with no clock output + SMCI_STATE_TX_RX_IDLE = 1U, ///< SMCI is in idle state, clock is active + SMCI_STATE_TX_PROGRESSING = 2U, ///< Transmission is in progress + SMCI_STATE_RX_PROGRESSING = 3U, ///< Reception is in progress +} smci_state_t; + +/** SMCI Event codes */ +typedef enum e_smci_event +{ + SMCI_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event + SMCI_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event + SMCI_EVENT_RX_CHAR = (1UL << 2), ///< Character transfer is completed + SMCI_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event + SMCI_EVENT_ERR_LOW_SIGNAL = (1UL << 4), ///< Low error signal response occurred event + SMCI_EVENT_ERR_OVERRUN = (1UL << 5) ///< Overrun error event +} smci_event_t; + +typedef enum e_smci_convention_type +{ + SMCI_CONVENTION_TYPE_DIRECT = 0U, ///< Direct convention type (LSB First, High=1) + SMCI_CONVENTION_TYPE_INVERSE = 1U, ///< Inverse convention type (MSB First, Low=1) +} smci_convention_type_t; + +/* This table matches Table 7 from ISO/IEC7816-3 Third edition 2006-11-01 */ +typedef enum e_smci_clock_conversion_integer +{ + SMCI_CLOCK_CONVERSION_INTEGER_372_4 = 0U, ///< Fi = 372, max freq = 4MHz + SMCI_CLOCK_CONVERSION_INTEGER_372_5 = 1U, ///< Fi = 372, max freq = 5MHz + SMCI_CLOCK_CONVERSION_INTEGER_558_6 = 2U, ///< Fi = 558, max freq = 6MHz + SMCI_CLOCK_CONVERSION_INTEGER_744_8 = 3U, ///< Fi = 744, max freq = 8MHz + SMCI_CLOCK_CONVERSION_INTEGER_1116_12 = 4U, ///< Fi = 1116, max freq = 12MHz + SMCI_CLOCK_CONVERSION_INTEGER_1488_16 = 5U, ///< Fi = 1488, max freq = 16MHz + SMCI_CLOCK_CONVERSION_INTEGER_1860_20 = 6U, ///< Fi = 1860, max freq = 20MHz + SMCI_CLOCK_CONVERSION_INTEGER_UNSUPPORTED7 = 7U, ///< Unsupported + SMCI_CLOCK_CONVERSION_INTEGER_UNSUPPORTED8 = 8U, ///< Unsupported + SMCI_CLOCK_CONVERSION_INTEGER_512_5 = 9U, ///< Fi = 512, max freq = 5MHz + SMCI_CLOCK_CONVERSION_INTEGER_768_75 = 10U, ///< Fi = 768, max freq = 7.5MHz + SMCI_CLOCK_CONVERSION_INTEGER_1024_10 = 11U, ///< Fi = 1024, max freq = 10MHz + SMCI_CLOCK_CONVERSION_INTEGER_1536_15 = 12U, ///< Fi = 1536, max freq = 15MHz + SMCI_CLOCK_CONVERSION_INTEGER_2048_20 = 13U, ///< Fi = 2048, max freq = 20MHz + SMCI_CLOCK_CONVERSION_INTEGER_UNSUPPORTED14 = 14U, ///< Unsupported + SMCI_CLOCK_CONVERSION_INTEGER_UNSUPPORTED15 = 15U, ///< Unsupported + SMCI_CLOCK_CONVERSION_INTEGER_MAX = 16U +} smci_clock_conversion_integer_t; + +/* This table matches Table 8 from ISO/IEC7816-3 Third edition 2006-11-01 */ +typedef enum e_smci_baudrate_adjustment_integer +{ + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_RFU0 = 0U, ///< RESERVED + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_1 = 1U, ///< Di=1 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_2 = 2U, ///< Di=2 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_4 = 3U, ///< Di=4 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_8 = 4U, ///< Di=8 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_16 = 5U, ///< Di=16 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_32 = 6U, ///< Di=32 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_64 = 7U, ///< Di=64 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_12 = 8U, ///< Di=12 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_20 = 9U, ///< Di=20 + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_RFU10 = 10U, ///< RESERVED + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_RFU11 = 11U, ///< RESERVED + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_RFU12 = 12U, ///< RESERVED + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_RFU13 = 13U, ///< RESERVED + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_RFU14 = 14U, ///< RESERVED + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_RFU15 = 15U, ///< RESERVED + SMCI_BAUDRATE_ADJUSTMENT_INTEGER_MAX = 16U +} smci_baudrate_adjustment_integer_t; + +/** SMCI Protocol Type according to ISO7816-3 */ +typedef enum e_smci_protocol_type +{ + SMCI_PROTOCOL_TYPE_T0 = 0U, ///< Normal mode operation (Protocol T = 0) + SMCI_PROTOCOL_TYPE_T1 = 1U, ///< Block transfer mode operation (Protocol T = 1) +} smci_protocol_type_t; + +/** SMCI driver specific information */ +typedef struct st_smci_status +{ + smci_state_t smci_state; ///< State of the SMCI state machine + uint32_t bytes_recvd; ///< Bytes read into receive buffer since read was called +} smci_status_t; + +/** SMCI Transfer Mode settings */ +typedef struct st_smci_transfer_mode +{ + smci_protocol_type_t protocol; ///< Protocol (Normal t=0, or Block t=1) + smci_convention_type_t convention; ///< Convention Direct or Inverse + bool gsm_mode; ///< True=GMS Mode, false=Normal +} smci_transfer_mode_t; + +/** SMCI settings that are used as inputs to register setting calculations */ +typedef struct st_smci_speed_params +{ + uint32_t baudrate; ///< Bits per second requested, 1/ETU + smci_baudrate_adjustment_integer_t di; ///< Referred to as D in ISO spec (from Table 8 in ISO7816-3 3rd Edition) + smci_clock_conversion_integer_t fi; ///< Index of F in ISO spec (from Table 7 in ISO7816-3 3rd Edition) +} smci_speed_params_t; + +/** SMCI Callback parameter definition */ +typedef struct st_smci_callback_args +{ + uint32_t channel; ///< Device channel number + smci_event_t event; ///< Event code + + /** Contains the next character received for the events SMCI_EVENT_RX_CHAR, SMCI_EVENT_ERR_PARITY, + * SMCI_EVENT_ERR_LOW_SIGNAL, or SMCI_EVENT_ERR_OVERRUN. Otherwise unused. */ + uint8_t data; ///< Data Byte to process + void * p_context; ///< Context provided to user during callback +} smci_callback_args_t; + +/** Configuration Structure for SMCI */ +typedef struct st_smci_cfg +{ + /* SMCI configuration */ + uint8_t channel; ///< Channel number of the hardware. + uint8_t rxi_ipl; ///< Receive interrupt priority + uint8_t txi_ipl; ///< Transmit interrupt priority + uint8_t eri_ipl; ///< Error interrupt priority + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + IRQn_Type eri_irq; ///< Error interrupt IRQ number + + /* Configuration for SMCI Event processing */ + void (* p_callback)(smci_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /* Pointer to SMCI peripheral specific configuration */ + void const * p_extend; ///< SMCI hardware dependent configuration +} smci_cfg_t; + +/** Smart Card Interface control block. Allocate an instance specific control block to pass into the SMCI API calls. + */ +typedef void smci_ctrl_t; + +/** Shared Interface definition for SMCI */ +typedef struct st_smci_api +{ + /** Open Smart Card Interface Mode (SMCI) + * + * @param[in,out] p_ctrl Pointer to the SMCI control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to SMCI configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(smci_ctrl_t * const p_ctrl, smci_cfg_t const * const p_cfg); + + /** Read from Smart Card device. The read buffer is used until the read is complete. When a transfer is complete, + * the callback is called with event SMCI_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received + * in the callback function with event SMCI_EVENT_RX_CHAR. + * + * @param[in] p_ctrl Pointer to the SMCI control block for the channel. + * @param[in] p_dest Destination address to read data from. + * @param[in] bytes Read data length. + */ + fsp_err_t (* read)(smci_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Write to Smart Card device. The write buffer is used until write is complete. Do not overwrite write buffer + * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), + * the callback called with event SMCI_EVENT_TX_COMPLETE. + * + * @param[in] p_ctrl Pointer to the SMCI control block. + * @param[in] p_src Source address to write data to. + * @param[in] bytes Write data length. + */ + fsp_err_t (* write)(smci_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); + + /** Change the peripheral settings based on provided transfer mode and data convention type + * + * @param[in] p_ctrl Pointer to the SMCI control block. + * @param[in] p_transfer_mode_params Pointer to SMCI setting like protocol, convention, and gsm_mode + */ + fsp_err_t (* transferModeSet)(smci_ctrl_t * const p_ctrl, + smci_transfer_mode_t const * const p_transfer_mode_params); + + /** Change baud rate. + * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud + * settings have been applied. + * + * + * @param[in] p_ctrl Pointer to the SMCI control block. + * @param[in] p_baud_setting Pointer to module specific setting for configuring baud rate. + */ + fsp_err_t (* baudSet)(smci_ctrl_t * const p_ctrl, void const * const p_baud_setting); + + /** Get the driver specific information. + * + * @param[in] p_ctrl Pointer to the SMCI control block. + * @param[out] p_status State info for the driver. + */ + fsp_err_t (* statusGet)(smci_ctrl_t * const p_ctrl, smci_status_t * const p_status); + + /** + * Enable or disable the SMCI clock to control the start of the activation or de-activation + * + * @param[in] p_ctrl Pointer to the SMCI control block. + * @param[in] clock_enable True: enables clock output, False disables it + */ + fsp_err_t (* clockControl)(smci_ctrl_t * const p_ctrl, bool clock_enable); + + /** + * Specify callback function and optional context pointer and callback memory pointer. + * + * @param[in] p_ctrl Pointer to the SMCI control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(smci_ctrl_t * const p_ctrl, void (* p_callback)(smci_callback_args_t *), + void * const p_context, smci_callback_args_t * const p_callback_memory); + + /** Close SMCI device. + * + * @param[in] p_ctrl Pointer to the SMCI control block. + */ + fsp_err_t (* close)(smci_ctrl_t * const p_ctrl); +} smci_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_smci_instance +{ + smci_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + smci_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + smci_api_t const * p_api; ///< Pointer to the API structure for this instance +} smci_instance_t; + +/** @} (end defgroup SMCI_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_SMCI_API_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_spi_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_spi_api.h new file mode 100644 index 0000000000..41ded18f90 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_spi_api.h @@ -0,0 +1,269 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SPI_API_H +#define R_SPI_API_H + +/*****************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup SPI_API SPI Interface + * @brief Interface for SPI communications. + * + * @section SPI_API_SUMMARY Summary + * Provides a common interface for communication using the SPI Protocol. + * + * + * @{ + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * Includes + ********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************* + * Macro definitions + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + ********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_SPI_BIT_WIDTH_T + +/** Data bit width */ +typedef enum e_spi_bit_width +{ + SPI_BIT_WIDTH_4_BITS = (3), ///< Data bit width is 4 bits + SPI_BIT_WIDTH_5_BITS = (4), ///< Data bit width is 5 bits + SPI_BIT_WIDTH_6_BITS = (5), ///< Data bit width is 6 bits + SPI_BIT_WIDTH_7_BITS = (6), ///< Data bit width is 7 bits + SPI_BIT_WIDTH_8_BITS = (7), ///< Data bit width is 8 bits + SPI_BIT_WIDTH_9_BITS = (8), ///< Data bit width is 9 bits + SPI_BIT_WIDTH_10_BITS = (9), ///< Data bit width is 10 bits + SPI_BIT_WIDTH_11_BITS = (10), ///< Data bit width is 11 bits + SPI_BIT_WIDTH_12_BITS = (11), ///< Data bit width is 12 bits + SPI_BIT_WIDTH_13_BITS = (12), ///< Data bit width is 13 bits + SPI_BIT_WIDTH_14_BITS = (13), ///< Data bit width is 14 bits + SPI_BIT_WIDTH_15_BITS = (14), ///< Data bit width is 15 bits + SPI_BIT_WIDTH_16_BITS = (15), ///< Data bit width is 16 bits + SPI_BIT_WIDTH_17_BITS = (16), ///< Data bit width is 17 bits + SPI_BIT_WIDTH_18_BITS = (17), ///< Data bit width is 18 bits + SPI_BIT_WIDTH_19_BITS = (18), ///< Data bit width is 19 bits + SPI_BIT_WIDTH_20_BITS = (19), ///< Data bit width is 20 bits + SPI_BIT_WIDTH_21_BITS = (20), ///< Data bit width is 21 bits + SPI_BIT_WIDTH_22_BITS = (21), ///< Data bit width is 22 bits + SPI_BIT_WIDTH_23_BITS = (22), ///< Data bit width is 23 bits + SPI_BIT_WIDTH_24_BITS = (23), ///< Data bit width is 24 bits + SPI_BIT_WIDTH_25_BITS = (24), ///< Data bit width is 25 bits + SPI_BIT_WIDTH_26_BITS = (25), ///< Data bit width is 26 bits + SPI_BIT_WIDTH_27_BITS = (26), ///< Data bit width is 27 bits + SPI_BIT_WIDTH_28_BITS = (27), ///< Data bit width is 28 bits + SPI_BIT_WIDTH_29_BITS = (28), ///< Data bit width is 29 bits + SPI_BIT_WIDTH_30_BITS = (29), ///< Data bit width is 30 bits + SPI_BIT_WIDTH_31_BITS = (30), ///< Data bit width is 31 bits + SPI_BIT_WIDTH_32_BITS = (31) ///< Data bit width is 32 bits +} spi_bit_width_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_MODE_T + +/** Master or slave operating mode */ +typedef enum e_spi_mode +{ + SPI_MODE_MASTER, ///< Channel operates as SPI master + SPI_MODE_SLAVE ///< Channel operates as SPI slave +} spi_mode_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_CLK_PHASE_T + +/** Clock phase */ +typedef enum e_spi_clk_phase +{ + SPI_CLK_PHASE_EDGE_ODD, ///< 0: Data sampling on odd edge, data variation on even edge + SPI_CLK_PHASE_EDGE_EVEN ///< 1: Data variation on odd edge, data sampling on even edge +} spi_clk_phase_t; +#endif + +#ifndef BSP_OVERRIDE_SPI_CLK_POLARITY_T + +/** Clock polarity */ +typedef enum e_spi_clk_polarity +{ + SPI_CLK_POLARITY_LOW, ///< 0: Clock polarity is low when idle + SPI_CLK_POLARITY_HIGH ///< 1: Clock polarity is high when idle +} spi_clk_polarity_t; +#endif + +/** Mode fault error flag. This error occurs when the device is setup as a master, but the SSLA line does not seem to be + * controlled by the master. This usually happens when the connecting device is also acting as master. + * A similar situation can also happen when configured as a slave. */ +typedef enum e_spi_mode_fault +{ + SPI_MODE_FAULT_ERROR_ENABLE, ///< Mode fault error flag on + SPI_MODE_FAULT_ERROR_DISABLE ///< Mode fault error flag off +} spi_mode_fault_t; + +#ifndef BSP_OVERRIDE_SPI_BIT_ORDER_T + +/** Bit order */ +typedef enum e_spi_bit_order +{ + SPI_BIT_ORDER_MSB_FIRST, ///< Send MSB first in transmission + SPI_BIT_ORDER_LSB_FIRST ///< Send LSB first in transmission +} spi_bit_order_t; +#endif + +/** SPI events */ +typedef enum e_spi_event +{ + SPI_EVENT_TRANSFER_COMPLETE = 1, ///< The data transfer was completed + SPI_EVENT_TRANSFER_ABORTED, ///< The data transfer was aborted + SPI_EVENT_ERR_MODE_FAULT, ///< Mode fault error + SPI_EVENT_ERR_READ_OVERFLOW, ///< Read overflow error + SPI_EVENT_ERR_PARITY, ///< Parity error + SPI_EVENT_ERR_OVERRUN, ///< Overrun error + SPI_EVENT_ERR_FRAMING, ///< Framing error + SPI_EVENT_ERR_MODE_UNDERRUN ///< Underrun error +} spi_event_t; + +/** Common callback parameter definition */ +typedef struct st_spi_callback_args +{ + uint32_t channel; ///< Device channel number + spi_event_t event; ///< Event code + void * p_context; ///< Context provided to user during callback +} spi_callback_args_t; + +/** Non-secure arguments for write-read guard function */ +typedef struct st_spi_write_read_guard_args +{ + void const * p_src; + void * p_dest; + uint32_t const length; + spi_bit_width_t const bit_width; +} spi_write_read_guard_args_t; + +/** SPI interface configuration */ +typedef struct st_spi_cfg +{ + uint8_t channel; ///< Channel number to be used + + IRQn_Type rxi_irq; ///< Receive Buffer Full IRQ number + IRQn_Type txi_irq; ///< Transmit Buffer Empty IRQ number + IRQn_Type tei_irq; ///< Transfer Complete IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + uint8_t rxi_ipl; ///< Receive Interrupt priority + uint8_t txi_ipl; ///< Transmit Interrupt priority + uint8_t tei_ipl; ///< Transfer Complete Interrupt priority + uint8_t eri_ipl; ///< Error Interrupt priority + spi_mode_t operating_mode; ///< Select master or slave operating mode + spi_clk_phase_t clk_phase; ///< Data sampling on odd or even clock edge + spi_clk_polarity_t clk_polarity; ///< Clock level when idle + spi_mode_fault_t mode_fault; ///< Mode fault error (master/slave conflict) flag + spi_bit_order_t bit_order; ///< Select to transmit MSB/LSB first + transfer_instance_t const * p_transfer_tx; ///< To use SPI DTC/DMAC write transfer, link a transfer instance here. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< To use SPI DTC/DMAC read transfer, link a transfer instance here. Set to NULL if unused. + void (* p_callback)(spi_callback_args_t * p_args); ///< Pointer to user callback function + void * p_context; ///< User defined context passed to callback function + void const * p_extend; ///< Extended SPI hardware dependent configuration +} spi_cfg_t; + +/** SPI control block. Allocate an instance specific control block to pass into the SPI API calls. + */ +typedef void spi_ctrl_t; + +/** Shared Interface definition for SPI */ +typedef struct st_spi_api +{ + /** Initialize a channel for SPI communication mode. + * + * @param[in, out] p_ctrl Pointer to user-provided storage for the control block. + * @param[in] p_cfg Pointer to SPI configuration structure. + */ + fsp_err_t (* open)(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg); + + /** Receive data from a SPI device. + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI + * device. It is the responsibility of the caller to ensure that adequate space is available + * to hold the requested data count. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* read)(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length, + spi_bit_width_t const bit_width); + + /** Transmit data to a SPI device. + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. + * The argument must not be NULL. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* write)(spi_ctrl_t * const p_ctrl, void const * p_src, uint32_t const length, + spi_bit_width_t const bit_width); + + /** Simultaneously transmit data to a SPI device while receiving data from a SPI device (full duplex). + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. + * The argument must not be NULL. + * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI + * device. It is the responsibility of the caller to ensure that adequate space is available + * to hold the requested data count. The argument must not be NULL. + * @param[in] length Number of units of data to be transferred (unit size specified by the bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* writeRead)(spi_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, uint32_t const length, + spi_bit_width_t const bit_width); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the SPI control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(spi_ctrl_t * const p_ctrl, void (* p_callback)(spi_callback_args_t *), + void * const p_context, spi_callback_args_t * const p_callback_memory); + + /** Remove power to the SPI channel designated by the handle and disable the associated interrupts. + * + * @param[in] p_ctrl Pointer to the control block for the channel. + */ + fsp_err_t (* close)(spi_ctrl_t * const p_ctrl); +} spi_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_spi_instance +{ + spi_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + spi_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + spi_api_t const * p_api; ///< Pointer to the API structure for this instance +} spi_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*****************************************************************************************************************//** + * @} (end defgroup SPI_API) + ********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_spi_flash_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_spi_flash_api.h new file mode 100644 index 0000000000..31ffa3b887 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_spi_flash_api.h @@ -0,0 +1,342 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_STORAGE_INTERFACES + * @defgroup SPI_FLASH_API SPI Flash Interface + * @brief Interface for accessing external SPI flash devices. + * + * @section SPI_FLASH_API_SUMMARY Summary + * The SPI flash API provides an interface that configures, writes, and erases sectors in SPI flash devices. + * @{ + **********************************************************************************************************************/ + +#ifndef R_SPI_FLASH_API_H +#define R_SPI_FLASH_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SPI_FLASH_ERASE_SIZE_CHIP_ERASE (UINT32_MAX) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Read mode. */ +typedef enum e_spi_flash_read_mode +{ + SPI_FLASH_READ_MODE_STANDARD = 0, ///< Standard Read Mode (no dummy cycles) + SPI_FLASH_READ_MODE_FAST_READ = 1, ///< Fast Read Mode (dummy cycles between address and data) + SPI_FLASH_READ_MODE_FAST_READ_DUAL_OUTPUT = 2, ///< Fast Read Dual Output Mode (data on 2 lines) + SPI_FLASH_READ_MODE_FAST_READ_DUAL_IO = 3, ///< Fast Read Dual I/O Mode (address and data on 2 lines) + SPI_FLASH_READ_MODE_FAST_READ_QUAD_OUTPUT = 4, ///< Fast Read Quad Output Mode (data on 4 lines) + SPI_FLASH_READ_MODE_FAST_READ_QUAD_IO = 5, ///< Fast Read Quad I/O Mode (address and data on 4 lines) +} spi_flash_read_mode_t; + +/** SPI protocol. */ +typedef enum e_spi_flash_protocol +{ + /** Extended SPI mode (commands on 1 line) */ + SPI_FLASH_PROTOCOL_EXTENDED_SPI = 0x000, + + /** QPI mode (commands on 4 lines). Note that the application must ensure the device is in QPI mode. */ + SPI_FLASH_PROTOCOL_QPI = 0x002, + + /** SOPI mode (command and data on 8 lines). Note that the application must ensure the device is in SOPI mode. */ + SPI_FLASH_PROTOCOL_SOPI = 0x003, + + /** DOPI mode (command and data on 8 lines, dual data rate). Note that the application must ensure the device is in DOPI mode. */ + SPI_FLASH_PROTOCOL_DOPI = 0x004, + + /** 1S-1S-1S protocol mode */ + SPI_FLASH_PROTOCOL_1S_1S_1S = 0x000, + + /** 4S-4D-4D protocol mode */ + SPI_FLASH_PROTOCOL_4S_4D_4D = 0x3B2, + + /** 8D-8D-8D protocol mode */ + SPI_FLASH_PROTOCOL_8D_8D_8D = 0x3FF, + + /** 8D-8D-8S protocol mode */ + SPI_FLASH_PROTOCOL_8D_8D_8S = 0x2FF, + + /** 1S-2S-2S protocol mode */ + SPI_FLASH_PROTOCOL_1S_2S_2S = 0x048, + + /** 2S-2S-2S protocol mode */ + SPI_FLASH_PROTOCOL_2S_2S_2S = 0x049, + + /** 1S-1S-4S protocol mode */ + SPI_FLASH_PROTOCOL_1S_1S_4S = 0x080, + + /** 1S-4S-4S protocol mode */ + SPI_FLASH_PROTOCOL_1S_4S_4S = 0x090, + + /** 4S-4S-4S protocol mode */ + SPI_FLASH_PROTOCOL_4S_4S_4S = 0x092 +} spi_flash_protocol_t; + +#ifndef BSP_OVERRIDE_SPI_FLASH_ADDRESS_BYTES_T + +/** Number of bytes in the address. */ +typedef enum e_spi_flash_address_bytes +{ + SPI_FLASH_ADDRESS_BYTES_1 = 0, ///< 1-byte address phase + SPI_FLASH_ADDRESS_BYTES_2 = 1, ///< 2-byte address phase + SPI_FLASH_ADDRESS_BYTES_3 = 2, ///< 3-byte address phase + SPI_FLASH_ADDRESS_BYTES_4 = 3, ///< 4-byte address phase + + /** 4 address bytes using standard 4-byte command set. */ + SPI_FLASH_ADDRESS_BYTES_4_4BYTE_READ_CODE = 0x13, +} spi_flash_address_bytes_t; +#endif + +/** Number of data lines used. */ +typedef enum e_spi_flash_data_lines +{ + SPI_FLASH_DATA_LINES_1 = 0, ///< 1 data line + SPI_FLASH_DATA_LINES_2 = 1, ///< 2 data lines + SPI_FLASH_DATA_LINES_4 = 2, ///< 4 data lines +} spi_flash_data_lines_t; + +/** Number of dummy cycles for fast read operations. */ +typedef enum e_spi_flash_dummy_clocks +{ + SPI_FLASH_DUMMY_CLOCKS_0 = 0, ///< 0 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_1, ///< 1 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_2, ///< 2 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_3, ///< 3 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_4, ///< 4 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_5, ///< 5 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_6, ///< 6 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_7, ///< 7 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_8, ///< 8 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_9, ///< 9 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_10, ///< 10 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_11, ///< 11 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_12, ///< 12 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_13, ///< 13 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_14, ///< 14 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_15, ///< 15 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_16, ///< 16 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_17, ///< 17 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_18, ///< 18 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_19, ///< 19 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_20, ///< 20 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_21, ///< 21 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_22, ///< 22 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_23, ///< 23 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_24, ///< 24 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_25, ///< 25 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_26, ///< 26 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_27, ///< 27 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_28, ///< 28 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_29, ///< 29 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_30, ///< 30 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_31, ///< 31 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_DEFAULT = 0xFF, +} spi_flash_dummy_clocks_t; + +/** Direct Read and Write direction */ +typedef enum e_spi_flash_direct_transfer_dir_option +{ + SPI_FLASH_DIRECT_TRANSFER_DIR_READ = 0x0, + SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE = 0x1 +} spi_flash_direct_transfer_dir_t; + +/** Structure to define an erase command and associated erase size. */ +typedef struct st_spi_flash_erase_command +{ + uint16_t command; ///< Erase command + uint32_t size; ///< Size of erase for associated command, set to SPI_FLASH_ERASE_SIZE_CHIP_ERASE for chip erase +} spi_flash_erase_command_t; + +/** Structure to define a direct transfer. */ +typedef struct st_spi_flash_direct_transfer +{ + union + { + uint64_t data_u64; ///< Data (64-bit) + uint32_t data; ///< Data + }; + uint32_t address; ///< Starting address + uint16_t command; ///< Transfer command + uint8_t dummy_cycles; ///< Number of dummy cycles + uint8_t command_length; ///< Command length + uint8_t address_length; ///< Address length + uint8_t data_length; ///< Data length +} spi_flash_direct_transfer_t; + +/** User configuration structure used by the open function */ +typedef struct st_spi_flash_cfg +{ + spi_flash_protocol_t spi_protocol; ///< Initial SPI protocol. SPI protocol can be changed in @ref spi_flash_api_t::spiProtocolSet. + spi_flash_read_mode_t read_mode; ///< Read mode + spi_flash_address_bytes_t address_bytes; ///< Number of bytes used to represent the address + spi_flash_dummy_clocks_t dummy_clocks; ///< Number of dummy clocks to use for fast read operations + + /** Number of lines used to send address for page program command. This should either be 1 or match the number of lines used in + * the selected read mode. */ + spi_flash_data_lines_t page_program_address_lines; + uint8_t write_status_bit; ///< Which bit determines write status + uint8_t write_enable_bit; ///< Which bit determines write status + uint32_t page_size_bytes; ///< Page size in bytes (maximum number of bytes for page program). Used to specify single continuous write size (bytes) in case of OSPI RAM. + uint8_t page_program_command; ///< Page program command + uint8_t write_enable_command; ///< Command to enable write or erase, typically 0x06 + uint8_t status_command; ///< Command to read the write status + uint8_t read_command; ///< Read command - OSPI SPI mode only + uint8_t xip_enter_command; ///< Command to enter XIP mode + uint8_t xip_exit_command; ///< Command to exit XIP mode + uint8_t erase_command_list_length; ///< Length of erase command list + spi_flash_erase_command_t const * p_erase_command_list; ///< List of all erase commands and associated sizes + void const * p_extend; ///< Pointer to implementation specific extended configurations +} spi_flash_cfg_t; + +/** SPI flash control block. Allocate an instance specific control block to pass into the SPI flash API calls. + */ +typedef void spi_flash_ctrl_t; + +/** Status. */ +typedef struct st_spi_flash_status +{ + /** Whether or not a write is in progress. This is determined by reading the @ref spi_flash_cfg_t::write_status_bit + * from the @ref spi_flash_cfg_t::status_command. */ + bool write_in_progress; +} spi_flash_status_t; + +/** SPI flash implementations follow this API. */ +typedef struct st_spi_flash_api +{ + /** Open the SPI flash driver module. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_cfg Pointer to a configuration structure + **/ + fsp_err_t (* open)(spi_flash_ctrl_t * const p_ctrl, spi_flash_cfg_t const * const p_cfg); + + /** Write raw data to the SPI flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_src Pointer to raw data to write, must include any required command/address + * @param[in] bytes Number of bytes to write + * @param[in] read_after_write If true, the slave select remains asserted and the peripheral does not return + * to direct communications mode. If false, the slave select is deasserted and + * memory mapped access is possible after this function returns if the device + * is not busy. + **/ + fsp_err_t (* directWrite)(spi_flash_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes, + bool const read_after_write); + + /** Read raw data from the SPI flash. Must follow a call to @ref spi_flash_api_t::directWrite. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[out] p_dest Pointer to read raw data into + * @param[in] bytes Number of bytes to read + **/ + fsp_err_t (* directRead)(spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Direct Read/Write raw data to the SPI flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_data Pointer to command, address and data values and lengths + * @param[in] direction Direct Read/Write + **/ + fsp_err_t (* directTransfer)(spi_flash_ctrl_t * const p_ctrl, spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); + + /** Change the SPI protocol in the driver. The application must change the SPI protocol on the device. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] spi_protocol Desired SPI protocol + **/ + fsp_err_t (* spiProtocolSet)(spi_flash_ctrl_t * const p_ctrl, spi_flash_protocol_t spi_protocol); + + /** Program a page of data to the flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_src The memory address of the data to write to the flash device + * @param[in] p_dest The location in the flash device address space to write the data to + * @param[in] byte_count The number of bytes to write + **/ + fsp_err_t (* write)(spi_flash_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint8_t * const p_dest, + uint32_t byte_count); + + /** Erase a certain number of bytes of the flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_device_address The location in the flash device address space to start the erase from + * @param[in] byte_count The number of bytes to erase. Set to SPI_FLASH_ERASE_SIZE_CHIP_ERASE to erase entire + * chip. + **/ + fsp_err_t (* erase)(spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); + + /** Get the write or erase status of the flash. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[out] p_status Current status of the SPI flash device stored here. + **/ + fsp_err_t (* statusGet)(spi_flash_ctrl_t * const p_ctrl, spi_flash_status_t * const p_status); + + /** Enter XIP mode. + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* xipEnter)(spi_flash_ctrl_t * const p_ctrl); + + /** Exit XIP mode. + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* xipExit)(spi_flash_ctrl_t * const p_ctrl); + + /** Select the bank to access. See implementation for details. + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] bank The bank number + **/ + fsp_err_t (* bankSet)(spi_flash_ctrl_t * const p_ctrl, uint32_t bank); + + /** AutoCalibrate the SPI flash driver module. Expected to be used when auto-calibrating OSPI RAM device. + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* autoCalibrate)(spi_flash_ctrl_t * const p_ctrl); + + /** Close the SPI flash driver module. + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* close)(spi_flash_ctrl_t * const p_ctrl); +} spi_flash_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_spi_flash_instance +{ + spi_flash_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + spi_flash_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + spi_flash_api_t const * p_api; ///< Pointer to the API structure for this instance +} spi_flash_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup SPI_FLASH_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_three_phase_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_three_phase_api.h new file mode 100644 index 0000000000..e7807ff009 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_three_phase_api.h @@ -0,0 +1,156 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_THREE_PHASE_API_H +#define R_THREE_PHASE_API_H + +/*******************************************************************************************************************//** + * @defgroup THREE_PHASE_API Three-Phase Interface + * @ingroup RENESAS_TIMERS_INTERFACES + * @brief Interface for three-phase timer functions. + * + * @section THREE_PHASE_API_SUMMARY Summary + * The Three-Phase interface provides functionality for synchronous start/stop/reset control of three timer channels for + * use in 3-phase motor control applications. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Leading zeroes removed to avoid coding standard violation. */ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Timer channel indices */ +typedef enum e_three_phase_channel +{ + THREE_PHASE_CHANNEL_U, ///< U-channel index + THREE_PHASE_CHANNEL_V, ///< V-channel index + THREE_PHASE_CHANNEL_W, ///< W-channel index +} three_phase_channel_t; + +/** Buffering mode */ +typedef enum e_three_phase_buffer_mode +{ + THREE_PHASE_BUFFER_MODE_SINGLE = 1, ///< Single-buffer mode + THREE_PHASE_BUFFER_MODE_DOUBLE = 2 ///< Double-buffer mode +} three_phase_buffer_mode_t; + +/** Struct for passing duty cycle values to @ref three_phase_api_t::dutyCycleSet */ +typedef struct st_three_phase_duty_cycle +{ + uint32_t duty[3]; ///< Duty cycle + uint32_t duty_buffer[3]; ///< Double-buffer for duty cycle values +} three_phase_duty_cycle_t; + +/** Three-Phase control block. Allocate an instance specific control block to pass into the timer API calls. + */ +typedef void three_phase_ctrl_t; + +/** User configuration structure, used in open function */ +typedef struct st_three_phase_cfg +{ + three_phase_buffer_mode_t buffer_mode; ///< Single or double-buffer mode + + /* Pointers to instance structs */ + timer_instance_t const * p_timer_instance[3]; ///< Pointer to the timer instance structs + three_phase_channel_t callback_ch; ///< Channel to enable callback when using three_phase_api_t::callbackSet + + uint32_t channel_mask; ///< Bitmask of timer channels used by this module + + /** Placeholder for user data. Passed to the user callback in @ref timer_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. +} three_phase_cfg_t; + +/** Three-Phase API structure. */ +typedef struct st_three_phase_api +{ + /** Initial configuration. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(three_phase_ctrl_t * const p_ctrl, three_phase_cfg_t const * const p_cfg); + + /** Start all three timers synchronously. + * + * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. + */ + fsp_err_t (* start)(three_phase_ctrl_t * const p_ctrl); + + /** Stop all three timers synchronously. + * + * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. + */ + fsp_err_t (* stop)(three_phase_ctrl_t * const p_ctrl); + + /** Reset all three timers synchronously. + * + * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. + */ + fsp_err_t (* reset)(three_phase_ctrl_t * const p_ctrl); + + /** Sets the duty cycle match values. If the timer is counting, the updated duty cycle is + * reflected after the next timer expiration. + * + * + * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. + * @param[in] p_duty_cycle Duty cycle values for all three timer channels. + */ + fsp_err_t (* dutyCycleSet)(three_phase_ctrl_t * const p_ctrl, three_phase_duty_cycle_t * const p_duty_cycle); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call. + * @param[in] p_callback Callback function to register with timer channel + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(three_phase_ctrl_t * const p_ctrl, void (* p_callback)(timer_callback_args_t *), + void * const p_context, timer_callback_args_t * const p_callback_memory); + + /** Allows driver to be reconfigured and may reduce power consumption. + * + * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call for this timer. + */ + fsp_err_t (* close)(three_phase_ctrl_t * const p_ctrl); +} three_phase_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_three_phase_instance +{ + three_phase_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + three_phase_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + three_phase_api_t const * p_api; ///< Pointer to the API structure for this instance +} three_phase_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup THREE_PHASE_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_timer_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_timer_api.h new file mode 100644 index 0000000000..3eaafd52b8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_timer_api.h @@ -0,0 +1,329 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_TIMER_API_H +#define R_TIMER_API_H + +/*******************************************************************************************************************//** + * @defgroup TIMER_API Timer Interface + * @ingroup RENESAS_TIMERS_INTERFACES + * @brief Interface for timer functions. + * + * @section TIMER_API_SUMMARY Summary + * The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output, + * and free-running timer mode. After each timer cycle (overflow or underflow), an interrupt can be triggered. + * + * If an instance supports output compare mode, it is provided in the extension configuration + * timer_on__cfg_t defined in r_.h. + * + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_TIMER_EVENT_T + +/** Events that can trigger a callback function */ +typedef enum e_timer_event +{ + TIMER_EVENT_CYCLE_END, ///< Requested timer delay has expired or timer has wrapped around + TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only) + TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A + TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B + TIMER_EVENT_TROUGH, ///< Timer trough event (counter is 0, triangle-wave PWM only + TIMER_EVENT_COMPARE_A, ///< A compare has occurred on signal A + TIMER_EVENT_COMPARE_B, ///< A compare has occurred on signal B + TIMER_EVENT_COMPARE_C, ///< A compare has occurred on signal C + TIMER_EVENT_COMPARE_D, ///< A compare has occurred on signal D + TIMER_EVENT_COMPARE_E, ///< A compare has occurred on signal E + TIMER_EVENT_COMPARE_F, ///< A compare has occurred on signal F + TIMER_EVENT_DEAD_TIME ///< Dead time event +} timer_event_t; +#endif + +/** Timer variant types. */ +typedef enum e_timer_variant +{ + TIMER_VARIANT_32_BIT, ///< 32-bit timer + TIMER_VARIANT_16_BIT ///< 16-bit timer +} timer_variant_t; + +/** Options for storing compare match value */ +typedef enum e_timer_compare_match +{ + TIMER_COMPARE_MATCH_A = 0U, ///< Compare match A value + TIMER_COMPARE_MATCH_B = 1U, ///< Compare match B value + TIMER_COMPARE_MATCH_C = 2U, ///< Compare match C value + TIMER_COMPARE_MATCH_D = 3U, ///< Compare match D value + TIMER_COMPARE_MATCH_E = 4U, ///< Compare match E value + TIMER_COMPARE_MATCH_F = 5U, ///< Compare match F value + TIMER_COMPARE_MATCH_G = 6U, ///< Compare match G value + TIMER_COMPARE_MATCH_H = 7U, ///< Compare match H value +} timer_compare_match_t; + +#ifndef BSP_OVERRIDE_TIMER_CALLBACK_ARGS_T + +/** Callback function parameter data */ +typedef struct st_timer_callback_args +{ + /** Placeholder for user data. Set in @ref timer_api_t::open function in @ref timer_cfg_t. */ + void * p_context; + timer_event_t event; ///< The event can be used to identify what caused the callback. + + /** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */ + uint32_t capture; +} timer_callback_args_t; + +#endif + +/** Timer control block. Allocate an instance specific control block to pass into the timer API calls. + */ +typedef void timer_ctrl_t; + +#ifndef BSP_OVERRIDE_TIMER_STATE_T + +/** Possible status values returned by @ref timer_api_t::statusGet. */ +typedef enum e_timer_state +{ + TIMER_STATE_STOPPED = 0, ///< Timer is stopped + TIMER_STATE_COUNTING = 1, ///< Timer is running + TIMER_STATE_UNKNOWN = 2 ///< Timer state could not be defined +} timer_state_t; + +#endif + +#ifndef BSP_OVERRIDE_TIMER_MODE_T + +/** Timer operational modes */ +typedef enum e_timer_mode +{ + TIMER_MODE_PERIODIC, ///< Timer restarts after period elapses. + TIMER_MODE_ONE_SHOT, ///< Timer stops after period elapses. + TIMER_MODE_PWM, ///< Timer generates saw-wave PWM output. + TIMER_MODE_ONE_SHOT_PULSE, ///< Saw-wave one-shot pulse mode (fixed buffer operation). + TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM = 4U, ///< Timer generates symmetric triangle-wave PWM output. + TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output. + + /** + * Timer generates Asymmetric Triangle-wave PWM output. In PWM mode 3, the duty cycle does + * not need to be updated at each tough/crest interrupt. Instead, the trough and crest duty cycle values can be + * set once and only need to be updated when the application needs to change the duty cycle. + */ + TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 = 6U +} timer_mode_t; + +#endif + +/** Direction of timer count */ +typedef enum e_timer_direction +{ + TIMER_DIRECTION_DOWN = 0, ///< Timer count goes up + TIMER_DIRECTION_UP = 1 ///< Timer count goes down +} timer_direction_t; + +#ifndef BSP_OVERRIDE_TIMER_SOURCE_DIV_T + +/** Clock source divisors */ +typedef enum e_timer_source_div +{ + TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1 + TIMER_SOURCE_DIV_2 = 1, ///< Timer clock source divided by 2 + TIMER_SOURCE_DIV_4 = 2, ///< Timer clock source divided by 4 + TIMER_SOURCE_DIV_8 = 3, ///< Timer clock source divided by 8 + TIMER_SOURCE_DIV_16 = 4, ///< Timer clock source divided by 16 + TIMER_SOURCE_DIV_32 = 5, ///< Timer clock source divided by 32 + TIMER_SOURCE_DIV_64 = 6, ///< Timer clock source divided by 64 + TIMER_SOURCE_DIV_128 = 7, ///< Timer clock source divided by 128 + TIMER_SOURCE_DIV_256 = 8, ///< Timer clock source divided by 256 + TIMER_SOURCE_DIV_512 = 9, ///< Timer clock source divided by 512 + TIMER_SOURCE_DIV_1024 = 10, ///< Timer clock source divided by 1024 + TIMER_SOURCE_DIV_8192 = 13, ///< Timer clock source divided by 8192 +} timer_source_div_t; +#endif + +/** Timer information structure to store various information for a timer resource */ +typedef struct st_timer_info +{ + timer_direction_t count_direction; ///< Clock counting direction of the timer. + uint32_t clock_frequency; ///< Clock frequency of the timer counter. + + /** Period in raw timer counts. + * @note For triangle wave PWM modes, the full period is double this value. + */ + uint32_t period_counts; +} timer_info_t; + +#ifndef BSP_OVERRIDE_TIMER_STATUS_T + +/** Current timer status. */ +typedef struct st_timer_status +{ + uint32_t counter; ///< Current counter value + timer_state_t state; ///< Current timer state (running or stopped) +} timer_status_t; + +#endif + +/** User configuration structure, used in open function */ +typedef struct st_timer_cfg +{ + timer_mode_t mode; ///< Select enumerated value from @ref timer_mode_t + + /* Period in raw timer counts. + * @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period. + */ + uint32_t period_counts; ///< Period in raw timer counts + timer_source_div_t source_div; ///< Source clock divider + uint32_t duty_cycle_counts; ///< Duty cycle in counts + + /** Select a channel corresponding to the channel number of the hardware. */ + uint8_t channel; + uint8_t cycle_end_ipl; ///< Cycle end interrupt priority + IRQn_Type cycle_end_irq; ///< Cycle end interrupt + + /** Callback provided when a timer ISR occurs. Set to NULL for no CPU interrupt. */ + void (* p_callback)(timer_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref timer_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. +} timer_cfg_t; + +/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */ +typedef struct st_timer_api +{ + /** Initial configuration. + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); + + /** Start the counter. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* start)(timer_ctrl_t * const p_ctrl); + + /** Stop the counter. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl); + + /** Reset the counter to the initial value. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl); + + /** Enables input capture. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl); + + /** Disables input capture. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl); + + /** Set the time until the timer expires. See implementation for details of period update timing. + * + * + * @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in + * @ref timer_api_t::open. + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] period Time until timer should expire. + */ + fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period); + + /** Sets the number of counts for the pin level to be high. If the timer is counting, the updated duty cycle is + * reflected after the next timer expiration. + * + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] duty_cycle_counts Time until duty cycle should expire. + * @param[in] pin Which output pin to update. See implementation for details. + */ + fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); + + /** Set a compare match value in raw counts. + * + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] compare_match_value Timer value to trigger a compare match event. + * @param[in] match_channel Which channel to update. + */ + fsp_err_t (* compareMatchSet)(timer_ctrl_t * const p_ctrl, uint32_t const compare_match_value, + timer_compare_match_t const match_channel); + + /** Stores timer information in p_info. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[out] p_info Collection of information for this timer. + */ + fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); + + /** Get the current counter value and timer state and store it in p_status. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[out] p_status Current status of this timer. + */ + fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(timer_ctrl_t * const p_ctrl, void (* p_callback)(timer_callback_args_t *), + void * const p_context, timer_callback_args_t * const p_callback_memory); + + /** Allows driver to be reconfigured and may reduce power consumption. + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* close)(timer_ctrl_t * const p_ctrl); +} timer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_timer_instance +{ + timer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + timer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + timer_api_t const * p_api; ///< Pointer to the API structure for this instance +} timer_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup TIMER_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_transfer_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_transfer_api.h new file mode 100644 index 0000000000..92aeeabc2a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_transfer_api.h @@ -0,0 +1,389 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_TRANSFER_INTERFACES + * @defgroup TRANSFER_API Transfer Interface + * + * @brief Interface for data transfer functions. + * + * @section TRANSFER_API_SUMMARY Summary + * The transfer interface supports background data transfer (no CPU intervention). + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_TRANSFER_API_H +#define R_TRANSFER_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define TRANSFER_SETTINGS_MODE_BITS (30U) +#define TRANSFER_SETTINGS_SIZE_BITS (28U) +#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) +#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) +#define TRANSFER_SETTINGS_IRQ_BITS (21U) +#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) +#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. + */ +typedef void transfer_ctrl_t; + +#ifndef BSP_OVERRIDE_TRANSFER_MODE_T + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to + * the destination pointer. The transfer length is decremented and the source and address pointers are + * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests + * will not cause any further transfers. */ + TRANSFER_MODE_NORMAL = 0, + + /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the + * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the + * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats + * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is + * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ + TRANSFER_MODE_REPEAT = 1, + + /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. + * After each individual transfer, the source and destination pointers are updated according to + * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is + * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any + * further transfers. */ + TRANSFER_MODE_BLOCK = 2, + + /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets + * within a block (to split blocks into arrays of their first data, second data, etc.) */ + TRANSFER_MODE_REPEAT_BLOCK = 3 +} transfer_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T + +/** Transfer size specifies the size of each individual transfer. + * Total transfer length = transfer_size_t * transfer_length_t + */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value + TRANSFER_SIZE_8_BYTE = 3 ///< Each transfer transfers a 64-bit value +} transfer_size_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 0, + + /** Offset is added to the address pointer after each transfer. */ + TRANSFER_ADDR_MODE_OFFSET = 1, + + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 2, + + /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_DECREMENTED = 3 +} transfer_addr_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T + +/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its + * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, + * the selected pointer returns to its original value after each transfer. */ +typedef enum e_transfer_repeat_area +{ + /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_DESTINATION = 0, + + /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_SOURCE = 1 +} transfer_repeat_area_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T + +/** Chain transfer mode options. + * @note Only applies for DTC. */ +typedef enum e_transfer_chain_mode +{ + /** Chain mode not used. */ + TRANSFER_CHAIN_MODE_DISABLED = 0, + + /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ + TRANSFER_CHAIN_MODE_EACH = 2, + + /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ + TRANSFER_CHAIN_MODE_END = 3 +} transfer_chain_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T + +/** Interrupt options. */ +typedef enum e_transfer_irq +{ + /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, + * the interrupt will occur only after subsequent chained transfer(s) are complete. + * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will + * prevent activation source interrupts until the transfer is complete. */ + TRANSFER_IRQ_END = 0, + + /** Interrupt occurs after each transfer. + * @note Not available in all HAL drivers. See HAL driver for details. */ + TRANSFER_IRQ_EACH = 1 +} transfer_irq_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T + +/** Callback function parameter data. */ +typedef struct st_transfer_callback_args_t +{ + void * p_context; ///< Placeholder for user data. Set in @ref transfer_api_t::open function in ::transfer_cfg_t. +} transfer_callback_args_t; + +#endif + +/** Driver specific information. */ +typedef struct st_transfer_properties +{ + uint32_t block_count_max; ///< Maximum number of blocks + uint32_t block_count_remaining; ///< Number of blocks remaining + uint32_t transfer_length_max; ///< Maximum number of transfers + uint32_t transfer_length_remaining; ///< Number of transfers remaining +} transfer_properties_t; + +#ifndef BSP_OVERRIDE_TRANSFER_INFO_T + +/** This structure specifies the properties of the transfer. + * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. + * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. + * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must + * have a unique transfer_info_t. + * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this + * structure must remain in scope until the transfer it is used for is closed. + * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ +typedef struct st_transfer_info +{ + union + { + struct + { + uint32_t : 16; + uint32_t : 2; + + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode : 2; + + /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ + transfer_repeat_area_t repeat_area : 1; + + /** Select if interrupts should occur after each individual transfer or after the completion of all planned + * transfers. */ + transfer_irq_t irq : 1; + + /** Select when the chain transfer ends. */ + transfer_chain_mode_t chain_mode : 2; + + uint32_t : 2; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode : 2; + + /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ + transfer_size_t size : 2; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode : 2; + } transfer_settings_word_b; + + uint32_t transfer_settings_word; + }; + + void const * volatile p_src; ///< Source pointer + void * volatile p_dest; ///< Destination pointer + + /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or + * @ref TRANSFER_MODE_REPEAT (DMAC only) or + * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ + volatile uint16_t num_blocks; + + /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, + * and @ref TRANSFER_MODE_REPEAT_BLOCK + * see HAL driver for details. */ + volatile uint16_t length; +} transfer_info_t; + +#endif + +/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be + * initialized. */ +typedef struct st_transfer_cfg +{ + /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to + * an array of chained transfers that will be completed in order. */ + transfer_info_t * p_info; + + void const * p_extend; ///< Extension parameter for hardware specific settings. +} transfer_cfg_t; + +/** Select whether to start single or repeated transfer with software start. */ +typedef enum e_transfer_start_mode +{ + TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. + TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. +} transfer_start_mode_t; + +/** Transfer functions implemented at the HAL layer will follow this API. */ +typedef struct st_transfer_api +{ + /** Initial configuration. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure + * must be set by user. + */ + fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); + + /** Reconfigure the transfer. + * Enable the transfer if p_info is valid. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_info Pointer to a new transfer info structure. + */ + fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); + + /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. + * Enable the transfer if p_src, p_dest, and length are valid. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, + * resets number of repeats (initially stored in transfer_info_t::num_blocks) in + * repeat mode. Not used in repeat mode for DTC. + */ + fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint16_t const num_transfers); + + /** Enable transfer. Transfers occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source). + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); + + /** Disable transfer. Transfers do not occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source). + * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a + * transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); + + /** Start transfer in software. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * @note Not supported for DTC. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] mode Select mode from @ref transfer_start_mode_t. + */ + fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); + + /** Stop transfer in software. The transfer will stop after completion of the current transfer. + * @note Not supported for DTC. + * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); + + /** Provides information about this transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[out] p_properties Driver specific information. + */ + fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); + + /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); + + /** To update next transfer information without interruption during transfer. + * Allow further transfer continuation. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or block mode. + */ + fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint32_t const num_transfers); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *), + void * const p_context, transfer_callback_args_t * const p_callback_memory); +} transfer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_transfer_instance +{ + transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + transfer_api_t const * p_api; ///< Pointer to the API structure for this instance +} transfer_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup TRANSFER_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_uart_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_uart_api.h new file mode 100644 index 0000000000..6ca9298dec --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_uart_api.h @@ -0,0 +1,266 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup UART_API UART Interface + * @brief Interface for UART communications. + * + * @section UART_INTERFACE_SUMMARY Summary + * The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features: + * - Full-duplex UART communication + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code + * - Runtime baud-rate change + * - Hardware resource locking during a transaction + * - CTS/RTS hardware flow control support (with an associated IOPORT pin) + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_UART_API_H +#define R_UART_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART Event codes */ +#ifndef BSP_OVERRIDE_UART_EVENT_T +typedef enum e_sf_event +{ + UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event + UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event + UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received + UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event + UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event + UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event + UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event + UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data +} uart_event_t; +#endif +#ifndef BSP_OVERRIDE_UART_DATA_BITS_T + +/** UART Data bit length definition */ +typedef enum e_uart_data_bits +{ + UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit + UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit + UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit +} uart_data_bits_t; +#endif +#ifndef BSP_OVERRIDE_UART_PARITY_T + +/** UART Parity definition */ +typedef enum e_uart_parity +{ + UART_PARITY_OFF = 0U, ///< No parity + UART_PARITY_ZERO = 1U, ///< Zero parity + UART_PARITY_EVEN = 2U, ///< Even parity + UART_PARITY_ODD = 3U, ///< Odd parity +} uart_parity_t; +#endif + +/** UART Stop bits definition */ +typedef enum e_uart_stop_bits +{ + UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit + UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit +} uart_stop_bits_t; + +/** UART transaction definition */ +typedef enum e_uart_dir +{ + UART_DIR_RX_TX = 3U, ///< Both RX and TX + UART_DIR_RX = 1U, ///< Only RX + UART_DIR_TX = 2U, ///< Only TX +} uart_dir_t; + +/** UART driver specific information */ +typedef struct st_uart_info +{ + /** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */ + uint32_t write_bytes_max; + + /** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */ + uint32_t read_bytes_max; +} uart_info_t; + +/** UART Callback parameter definition */ +typedef struct st_uart_callback_arg +{ + uint32_t channel; ///< Device channel number + uart_event_t event; ///< Event code + + /** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY, + * UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */ + uint32_t data; + void * p_context; ///< Context provided to user during callback +} uart_callback_args_t; + +/** UART Configuration */ +typedef struct st_uart_cfg +{ + /* UART generic configuration */ + uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware. + uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9) + uart_parity_t parity; ///< Parity type (none or odd or even) + uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2) + uint8_t rxi_ipl; ///< Receive interrupt priority + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + uint8_t txi_ipl; ///< Transmit interrupt priority + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + uint8_t tei_ipl; ///< Transmit end interrupt priority + IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number + uint8_t eri_ipl; ///< Error interrupt priority + IRQn_Type eri_irq; ///< Error interrupt IRQ number + + /** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_rx; + + /** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_tx; + + /* Configuration for UART Event processing */ + void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function + void * p_context; ///< User defined context passed into callback function + + /* Pointer to UART peripheral specific configuration */ + void const * p_extend; ///< UART hardware dependent configuration +} uart_cfg_t; + +/** UART control block. Allocate an instance specific control block to pass into the UART API calls. + */ +typedef void uart_ctrl_t; + +/** Shared Interface definition for UART */ +typedef struct st_uart_api +{ + /** Open UART device. + * + * @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here. + * @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + + /** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the + * callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in + * the callback function with event UART_EVENT_RX_CHAR. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block for the channel. + * @param[in] p_dest Destination address to read data from. + * @param[in] bytes Read data length. + */ + fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer + * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), + * the callback called with event UART_EVENT_TX_COMPLETE. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_src Source address to write data to. + * @param[in] bytes Write data length. + */ + fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); + + /** Change baud rate. + * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud + * settings have been applied. + * + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate. + */ + fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info); + + /** Get the driver specific information. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[out] p_info Pointer to UART information structure. + */ + fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); + + /** + * Abort ongoing transfer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] communication_to_abort Type of abort request. + */ + fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *), + void * const p_context, uart_callback_args_t * const p_callback_memory); + + /** Close UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* close)(uart_ctrl_t * const p_ctrl); + + /** Stop ongoing read and return the number of bytes remaining in the read. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. + */ + fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); + + /** Suspend RX operations for UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* receiveSuspend)(uart_ctrl_t * const p_ctrl); + + /** Resume RX operations for UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* receiveResume)(uart_ctrl_t * const p_ctrl); +} uart_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_uart_instance +{ + uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + uart_api_t const * p_api; ///< Pointer to the API structure for this instance +} uart_instance_t; + +/** @} (end defgroup UART_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_usb_basic_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_usb_basic_api.h new file mode 100644 index 0000000000..6b18266e25 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_usb_basic_api.h @@ -0,0 +1,666 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup USB_API USB Interface + * @brief Interface for USB functions. + * + * @section USB_API_Summary Summary + * The USB interface provides USB functionality. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_USB_API_H +#define R_USB_API_H + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include "bsp_api.h" +#include "r_transfer_api.h" +#include "../../src/r_usb_basic/src/driver/inc/r_usb_basic_define.h" + +#if (BSP_CFG_RTOS == 2) + #include "FreeRTOS.h" + #include "task.h" + #include "queue.h" + #include "timers.h" + #include "semphr.h" +#elif (BSP_CFG_RTOS == 1) + #include "tx_api.h" +#endif /* #if (BSP_CFG_RTOS == 2) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/* USB Request Type Register */ +#define USB_BREQUEST (0xFF00U) ///< b15-8 + +/* USB Standard request */ +#define USB_GET_STATUS (0x0000U) ///< USB Standard request Get Status +#define USB_CLEAR_FEATURE (0x0100U) ///< USB Standard request Clear Feature +#define USB_REQRESERVED (0x0200U) ///< USB Standard request Reqreserved +#define USB_SET_FEATURE (0x0300U) ///< USB Standard request Set Feature +#define USB_REQRESERVED1 (0x0400U) ///< USB Standard request Reqreserved1 +#define USB_SET_ADDRESS (0x0500U) ///< USB Standard request Set Address +#define USB_GET_DESCRIPTOR (0x0600U) ///< USB Standard request Get Descriptor +#define USB_SET_DESCRIPTOR (0x0700U) ///< USB Standard request Set Descriptor +#define USB_GET_CONFIGURATION (0x0800U) ///< USB Standard request Get Configuration +#define USB_SET_CONFIGURATION (0x0900U) ///< USB Standard request Set Configuration +#define USB_GET_INTERFACE (0x0A00U) ///< USB Standard request Get Interface +#define USB_SET_INTERFACE (0x0B00U) ///< USB Standard request Set Interface +#define USB_SYNCH_FRAME (0x0C00U) ///< USB Standard request Synch Frame + +/* USB_BMREQUESTTYPEDIR 0x0080u(b7) */ +#define USB_HOST_TO_DEV (0x0000U) ///< From host to device. +#define USB_DEV_TO_HOST (0x0080U) ///< From device to host. + +/* USB_BMREQUESTTYPETYPE 0x0060u(b6-5) */ +#define USB_STANDARD (0x0000U) ///< Standard Request +#define USB_CLASS (0x0020U) ///< Class Request +#define USB_VENDOR (0x0040U) ///< Vendor Request + +/* USB_BMREQUESTTYPERECIP 0x001Fu(b4-0) */ +#define USB_DEVICE (0x0000U) ///< Device +#define USB_INTERFACE (0x0001U) ///< Interface +#define USB_ENDPOINT (0x0002U) ///< End Point +#define USB_OTHER (0x0003U) ///< Other + +#define USB_NULL (0x0U) ///< NULL pointer + +#define USB_IP0 (0) ///< USB0 module +#define USB_IP1 (1) ///< USB1 module + +/* USB pipe number */ +#define USB_PIPE0 (0x0U) ///< Pipe Number0 +#define USB_PIPE1 (0x1U) ///< Pipe Number1 +#define USB_PIPE2 (0x2U) ///< Pipe Number2 +#define USB_PIPE3 (0x3U) ///< Pipe Number3 +#define USB_PIPE4 (0x4U) ///< Pipe Number4 +#define USB_PIPE5 (0x5U) ///< Pipe Number5 +#define USB_PIPE6 (0x6U) ///< Pipe Number6 +#define USB_PIPE7 (0x7U) ///< Pipe Number7 +#define USB_PIPE8 (0x8U) ///< Pipe Number8 +#define USB_PIPE9 (0x9U) ///< Pipe Number9 + +#define USB_EP0 (0x0U) ///< End Point Number0 +#define USB_EP1 (0x1U) ///< End Point Number1 +#define USB_EP2 (0x2U) ///< End Point Number2 +#define USB_EP3 (0x3U) ///< End Point Number3 +#define USB_EP4 (0x4U) ///< End Point Number4 +#define USB_EP5 (0x5U) ///< End Point Number5 +#define USB_EP6 (0x6U) ///< End Point Number6 +#define USB_EP7 (0x7U) ///< End Point Number7 +#define USB_EP8 (0x8U) ///< End Point Number8 +#define USB_EP9 (0x9U) ///< End Point Number9 +#define USB_EP10 (0xAU) ///< End Point Number10 +#define USB_EP11 (0xBU) ///< End Point Number11 +#define USB_EP12 (0xCU) ///< End Point Number12 +#define USB_EP13 (0xDU) ///< End Point Number13 +#define USB_EP14 (0xEU) ///< End Point Number14 +#define USB_EP15 (0xFU) ///< End Point Number15 + +/* Endpoint Direction */ +#define USB_EP_DIR (0x0080U) ///< b7: Endpoint Direction +#define USB_EP_DIR_IN (0x0080U) ///< b7: Endpoint Direction In +#define USB_EP_DIR_OUT (0x0000U) ///< b7: Endpoint Direction Out + +/* Descriptor type Define */ +#define USB_DT_DEVICE (0x01U) ///< Device Descriptor +#define USB_DT_CONFIGURATION (0x02U) ///< Configuration Descriptor +#define USB_DT_STRING (0x03U) ///< String Descriptor +#define USB_DT_INTERFACE (0x04U) ///< Interface Descriptor +#define USB_DT_ENDPOINT (0x05U) ///< Endpoint Descriptor +#define USB_DT_DEVICE_QUALIFIER (0x06U) ///< Device Qualifier Descriptor +#define USB_DT_OTHER_SPEED_CONF (0x07U) ///< Other Speed Configuration Descriptor +#define USB_DT_INTERFACE_POWER (0x08U) ///< Interface Power Descriptor +#define USB_DT_OTGDESCRIPTOR (0x09U) ///< OTG Descriptor +#define USB_DT_HUBDESCRIPTOR (0x29U) ///< HUB descriptor + +/* Interface class Define */ +#define USB_IFCLS_NOT (0x00U) ///< Un corresponding Class +#define USB_IFCLS_AUD (0x01U) ///< Audio Class +#define USB_IFCLS_CDC (0x02U) ///< CDC Class +#define USB_IFCLS_CDCC (0x02U) ///< CDC-Control Class +#define USB_IFCLS_HID (0x03U) ///< HID Class +#define USB_IFCLS_PHY (0x05U) ///< Physical Class +#define USB_IFCLS_IMG (0x06U) ///< Image Class +#define USB_IFCLS_PRN (0x07U) ///< Printer Class +#define USB_IFCLS_MAS (0x08U) ///< Mass Storage Class +#define USB_IFCLS_HUB (0x09U) ///< HUB Class +#define USB_IFCLS_CDCD (0x0AU) ///< CDC-Data Class +#define USB_IFCLS_CHIP (0x0BU) ///< Chip/Smart Card Class +#define USB_IFCLS_CNT (0x0CU) ///< Content-Security Class +#define USB_IFCLS_VID (0x0EU) ///< Video Class +#define USB_IFCLS_DIAG (0xDCU) ///< Diagnostic Device +#define USB_IFCLS_WIRE (0xE0U) ///< Wireless Controller +#define USB_IFCLS_APL (0xFEU) ///< Application-Specific +#define USB_IFCLS_VEN (0xFFU) ///< Vendor-Specific Class + +/* Endpoint Descriptor Define */ +#define USB_EP_IN (0x80U) ///< In Endpoint +#define USB_EP_OUT (0x00U) ///< Out Endpoint +#define USB_EP_ISO (0x01U) ///< Isochronous Transfer +#define USB_EP_BULK (0x02U) ///< Bulk Transfer +#define USB_EP_INT (0x03U) ///< Interrupt Transfer + +/* Configuration descriptor bit define */ +#define USB_CF_RESERVED (0x80U) ///< Reserved(set to 1) +#define USB_CF_SELFP (0x40U) ///< Self Powered +#define USB_CF_BUSP (0x00U) ///< Bus Powered +#define USB_CF_RWUPON (0x20U) ///< Remote Wake up ON +#define USB_CF_RWUPOFF (0x00U) ///< Remote Wake up OFF + +/* Descriptor length Define */ +#define USB_DD_BLENGTH (18U) ///< Device Descriptor Length +#define USB_CD_BLENGTH (9U) ///< Configuration Descriptor Length +#define USB_ID_BLENGTH (9U) ///< Interface Descriptor Length +#define USB_ED_BLENGTH (7U) ///< Endpoint Descriptor Length + +/***************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/** USB speed type */ +typedef enum e_usb_speed +{ + USB_SPEED_LS = 0, ///< Low speed operation + USB_SPEED_FS, ///< Full speed operation + USB_SPEED_HS, ///< Hi speed operation +} usb_speed_t; + +/** USB request result */ +typedef enum e_usb_setup_status +{ + USB_SETUP_STATUS_ACK = 0, ///< ACK response + USB_SETUP_STATUS_STALL, ///< STALL response +} usb_setup_status_t; + +/** USB driver status */ +typedef enum e_usb_status +{ + USB_STATUS_POWERED = 0, ///< Powered State + USB_STATUS_DEFAULT, ///< Default State + USB_STATUS_ADDRESS, ///< Address State + USB_STATUS_CONFIGURED, ///< Configured State + USB_STATUS_SUSPEND, ///< Suspend State + USB_STATUS_RESUME, ///< Resume State + USB_STATUS_DETACH, ///< Detach State + USB_STATUS_REQUEST, ///< Request State + USB_STATUS_REQUEST_COMPLETE, ///< Request Complete State + USB_STATUS_READ_COMPLETE, ///< Read Complete State + USB_STATUS_WRITE_COMPLETE, ///< Write Complete State + USB_STATUS_BC, ///< battery Charge State + USB_STATUS_OVERCURRENT, ///< Over Current state + USB_STATUS_NOT_SUPPORT, ///< Device Not Support + USB_STATUS_NONE, ///< None Status + USB_STATUS_MSC_CMD_COMPLETE, ///< MSC_CMD Complete +} usb_status_t; + +/** USB class type */ +typedef enum e_usb_class +{ + USB_CLASS_PCDC = 0x80, ///< PCDC Class + USB_CLASS_PCDCC, ///< PCDCC Class + USB_CLASS_PCDC2, ///< PCDC2 Class + USB_CLASS_PCDCC2, ///< PCDCC2 Class + USB_CLASS_PHID, ///< PHID Class + USB_CLASS_PHID2, ///< PHID2 Class + USB_CLASS_PAUD, ///< PAUD Class + USB_CLASS_PPRN, ///< PPRN Class + USB_CLASS_DFU, ///< DFU Class + USB_CLASS_PVND, ///< PVND Class + USB_CLASS_HCDC, ///< HCDC Class + USB_CLASS_HCDCC, ///< HCDCC Class + USB_CLASS_HHID, ///< HHID Class + USB_CLASS_HVND, ///< HVND Class + USB_CLASS_HMSC, ///< HMSC Class + USB_CLASS_PMSC, ///< PMSC Class + USB_CLASS_HPRN, ///< HPRN Class + USB_CLASS_HUVC, ///< HUVC Class + USB_CLASS_HAUD, ///< HAUD Class + USB_CLASS_REQUEST, ///< USB Class Request + USB_CLASS_HUB, ///< HUB Class + USB_CLASS_END, ///< USB Class End Code +} usb_class_t; + +/** USB battery charging type */ +typedef enum e_usb_bcport +{ + USB_BCPORT_SDP = 0, ///< SDP port settings + USB_BCPORT_CDP, ///< CDP port settings + USB_BCPORT_DCP, ///< DCP port settings +} usb_bcport_t; + +/** USB status */ +typedef enum e_usb_onoff +{ + USB_OFF = 0, ///< USB Off State + USB_ON, ///< USB On State +} usb_onoff_t; + +/** USB read/write type */ +typedef enum e_usb_transfer +{ + USB_TRANSFER_READ = 0, ///< Data Receive communication + USB_TRANSFER_WRITE, ///< Data transmission communication +} usb_transfer_t; + +/** USB transfer type */ +typedef enum e_usb_transfer_type +{ + USB_TRANSFER_TYPE_BULK = 0, ///< Bulk communication + USB_TRANSFER_TYPE_INT, ///< Interrupt communication + USB_TRANSFER_TYPE_ISO, ///< Isochronous communication +} usb_transfer_type_t; + +/* H/W function type */ +typedef enum e_usb_mode +{ + USB_MODE_HOST = 1, ///< Host mode + USB_MODE_PERI, ///< Peripheral mode +} usb_mode_t; + +typedef enum e_usb_compliancetest_status +{ + USB_COMPLIANCETEST_ATTACH, ///< Device Attach Detection + USB_COMPLIANCETEST_DETACH, ///< Device Detach Detection + USB_COMPLIANCETEST_TPL, ///< TPL device connect + USB_COMPLIANCETEST_NOTTPL, ///< Not TPL device connect + USB_COMPLIANCETEST_HUB, ///< USB Hub connect + USB_COMPLIANCETEST_OVRC, ///< Over current + USB_COMPLIANCETEST_NORES, ///< Response Time out for Control Read Transfer + USB_COMPLIANCETEST_SETUP_ERR, ///< Setup Transaction Error +} usb_compliancetest_status_t; + +typedef enum e_usb_address +{ + USB_ADDRESS1 = 1, + USB_ADDRESS2, + USB_ADDRESS3, + USB_ADDRESS4, + USB_ADDRESS5, +} usb_address_t; + +/** USB control block. Allocate an instance specific control block to pass into the USB API calls. + */ +typedef void usb_ctrl_t; +typedef void (usb_compliance_cb_t)(void *); + +typedef struct st_usb_descriptor +{ + uint8_t * p_device; ///< Pointer to the device descriptor + uint8_t * p_config_f; ///< Pointer to the configuration descriptor for Full-speed + uint8_t * p_config_h; ///< Pointer to the configuration descriptor for Hi-speed + uint8_t * p_qualifier; ///< Pointer to the qualifier descriptor + uint8_t ** p_string; ///< Pointer to the string descriptor table + uint8_t num_string; ///< Num entry String Descriptor +} usb_descriptor_t; + +typedef struct st_usb_setup +{ + uint16_t request_type; ///< USB standard/class request type + uint16_t request_value; ///< Request value + uint16_t request_index; ///< Request index + uint16_t request_length; ///< Request length +} usb_setup_t; + +typedef struct st_usb_pipe +{ + uint8_t endpoint; ///< Endpoint number + uint8_t transfer_type; ///< Transfer type (USB_BULK/USB_INT etc) + uint16_t maxpacketsize; ///< Max packet size +} usb_pipe_t; + +typedef struct st_usb_info +{ + uint8_t class_type; ///< USB device class type + uint8_t speed; ///< USB speed + uint8_t device_status; ///< USB device status + uint8_t bcport; ///< Battery charging information +} usb_info_t; + +typedef struct st_usb_compliance +{ + usb_compliancetest_status_t status; ///< USB Status + uint16_t vid; ///< Vendor ID + uint16_t pid; ///< Product ID +} usb_compliance_t; + +typedef struct st_usb_event_info +{ + uint8_t module_number; ///< USB module number (USB_IP0/USB_IP1) + uint8_t device_address; ///< USB device address + uint8_t pipe; ///< USB pipe number + usb_class_t type; ///< USB device class etc + uint16_t status; ///< USB device state etc + usb_status_t event; ///< USB event + uint32_t data_size; ///< Read data size + usb_setup_t setup; ///< usb_setup_t structure area + void * p_data; ///< Other information + void * p_context; ///< Other Context + const transfer_instance_t * p_transfer_tx; ///< Send context + const transfer_instance_t * p_transfer_rx; ///< Receive context +} usb_event_info_t; + +typedef usb_event_info_t usb_callback_args_t; + +#if (BSP_CFG_RTOS == 0) +typedef void (usb_callback_t)(usb_callback_args_t *); +#endif +#if (BSP_CFG_RTOS == 1) +typedef TX_THREAD * usb_hdl_t; +typedef void (usb_callback_t)(usb_event_info_t *, usb_hdl_t, usb_onoff_t); +#endif +#if (BSP_CFG_RTOS == 2) +typedef TaskHandle_t usb_hdl_t; +typedef void (usb_callback_t)(usb_event_info_t *, usb_hdl_t, usb_onoff_t); +#endif /* #if (BSP_CFG_RTOS == 2) */ + +#if (BSP_CFG_RTOS != 1) +typedef uint32_t ULONG; +#endif + +typedef void (usb_otg_callback_t)(ULONG); + +/** USB configuration. */ +typedef struct st_usb_cfg +{ + usb_mode_t usb_mode; ///< USB_MODE_HOST/USB_MODE_PERI + usb_speed_t usb_speed; ///< USB speed (USB_HS/USB_FS/USB_LS) + uint8_t module_number; ///< USB module number (USB_IP0/USB_IP1) + usb_class_t type; ///< USB device class etc + usb_descriptor_t * p_usb_reg; ///< Pointer to the usb_decriptor_t structure area + usb_compliance_cb_t * usb_complience_cb; + IRQn_Type irq; ///< USBI dedicated interrupt number storage variable. + IRQn_Type irq_r; ///< USBR dedicated interrupt number storage variable. + IRQn_Type irq_d0; ///< FS D0FIFO dedicated interrupt number storage variable. + IRQn_Type irq_d1; ///< FS D1FIFO dedicated interrupt number storage variable. + IRQn_Type hsirq; ///< USBIR dedicated interrupt number storage variable. + IRQn_Type hsirq_d0; ///< HS D0FIFO dedicated interrupt number storage variable. + IRQn_Type hsirq_d1; ///< HS D1FIFO dedicated interrupt number storage variable. + uint8_t ipl; ///< Variable to store the interrupt priority of USBI + uint8_t ipl_r; ///< Variable to store the interrupt priority of USBR. + uint8_t ipl_d0; ///< Variable to store the interrupt priority of FS D0FIFO. + uint8_t ipl_d1; ///< Variable to store the interrupt priority of FS D1FIFO. + uint8_t hsipl; ///< Variable to store the interrupt priority of USBIR. + uint8_t hsipl_d0; ///< Variable to store the interrupt priority of HS D0FIFO. + uint8_t hsipl_d1; ///< Variable to store the interrupt priority of HS D1FIFO. + usb_callback_t * p_usb_apl_callback; ///< Application Callback + void * p_context; ///< Other Context + const transfer_instance_t * p_transfer_tx; ///< Send context + const transfer_instance_t * p_transfer_rx; ///< Receive context + void const * p_extend; ///< Pointer to extended configuration by instance of interface. +} usb_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_usb_api +{ + /** Start the USB module + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(usb_ctrl_t * const p_ctrl, usb_cfg_t const * const p_cfg); + + /** Stop the USB module + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(usb_ctrl_t * const p_ctrl); + + /** Request USB data read + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores read data. + * @param[in] size Read request size. + * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. + */ + fsp_err_t (* read)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size, uint8_t destination); + + /** Request USB data write + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores write data. + * @param[in] size Read request size. + * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. + */ + fsp_err_t (* write)(usb_ctrl_t * const p_ctrl, uint8_t const * const p_buf, uint32_t size, uint8_t destination); + + /** Stop USB data read/write processing + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] direction Receive (USB_TRANSFER_READ) or send (USB_TRANSFER_WRITE). + * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. + */ + fsp_err_t (* stop)(usb_ctrl_t * const p_ctrl, usb_transfer_t direction, uint8_t destination); + + /** Request suspend + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* suspend)(usb_ctrl_t * const p_ctrl); + + /** Request resume + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* resume)(usb_ctrl_t * const p_ctrl); + + /** Sets VBUS supply start/stop. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] state VBUS supply start/stop specification + */ + fsp_err_t (* vbusSet)(usb_ctrl_t * const p_ctrl, uint16_t state); + + /** Get information on USB device. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_info Pointer to usb_info_t structure area. + * @param[in] destination Device address for Host. + */ + fsp_err_t (* infoGet)(usb_ctrl_t * const p_ctrl, usb_info_t * p_info, uint8_t destination); + + /** Request data read from specified pipe + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores read data. + * @param[in] size Read request size. + * @param[in] pipe_number Pipe Number. + */ + fsp_err_t (* pipeRead)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + + /** Request data write to specified pipe + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores write data. + * @param[in] size Read request size. + * @param[in] pipe_number Pipe Number. + */ + fsp_err_t (* pipeWrite)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + + /** Stop USB data read/write processing to specified pipe + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pipe_number Pipe Number. + */ + fsp_err_t (* pipeStop)(usb_ctrl_t * const p_ctrl, uint8_t pipe_number); + + /** Get pipe number + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_pipe Pointer to area that stores the selected pipe number (bit map information). + * @param[in] destination Device address for Host. + */ + fsp_err_t (* usedPipesGet)(usb_ctrl_t * const p_ctrl, uint16_t * p_pipe, uint8_t destination); + + /** Get pipe information + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_info Pointer to usb_pipe_t structure area. + * @param[in] pipe_number Pipe Number. + */ + fsp_err_t (* pipeInfoGet)(usb_ctrl_t * const p_ctrl, usb_pipe_t * p_info, uint8_t pipe_number); + + /** Return USB-related completed events (OS less only) + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] event Pointer to event. + */ + fsp_err_t (* eventGet)(usb_ctrl_t * const p_ctrl, usb_status_t * event); + + /** Register a callback function to be called upon completion of a USB related event. (RTOS only) + * + * @param[in] p_callback Pointer to Callback function. + */ + fsp_err_t (* callback)(usb_callback_t * p_callback); + + /** Pull-up enable/disable setting of D+/D- line. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] state Pull-up enable/disable setting. + */ + fsp_err_t (* pullUp)(usb_ctrl_t * const p_ctrl, uint8_t state); + + /** Performs settings and transmission processing when transmitting a setup packet. + * + * @param[in] p_ctrl USB control structure. + * @param[in] p_setup Setup packet information. + * @param[in] p_buf Transfer area information. + * @param[in] device_address Device address information. + */ + fsp_err_t (* hostControlTransfer)(usb_ctrl_t * const p_ctrl, usb_setup_t * p_setup, uint8_t * p_buf, + uint8_t device_address); + + /** Receives data sent by control transfer. + * + * @param[in] p_ctrl USB control structure. + * @param[in] p_buf Data reception area information. + * @param[in] size Data reception size information. + */ + fsp_err_t (* periControlDataGet)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size); + + /** Performs transfer processing for control transfer. + * + * @param[in] p_ctrl USB control structure. + * @param[in] p_buf Area information for data transfer. + * @param[in] size Transfer size information. + */ + fsp_err_t (* periControlDataSet)(usb_ctrl_t * const p_ctrl, uint8_t * p_buf, uint32_t size); + + /** Set the response to the setup packet. + * + * @param[in] p_ctrl USB control structure. + * @param[in] status USB port startup information. + */ + fsp_err_t (* periControlStatusSet)(usb_ctrl_t * const p_ctrl, usb_setup_status_t status); + + /** Sends a remote wake-up signal to the connected Host. + * + * @param[in] p_ctrl USB control structure. + */ + fsp_err_t (* remoteWakeup)(usb_ctrl_t * const p_ctrl); + + /** Activate USB Driver + * + * @param[in] p_api_ctrl USB control structure. + */ + fsp_err_t (* driverActivate)(usb_ctrl_t * const p_api_ctrl); + + /** Set callback memory to USB driver. + * + * @param[in] p_api_ctrl USB control structure. + * @param[in] p_callback_memory Pointer to store USB event information. + */ + fsp_err_t (* callbackMemorySet)(usb_ctrl_t * const p_api_ctrl, usb_callback_args_t * p_callback_memory); + + /** This API gets the module number. + * + * @param[in] p_ctrl USB control structure. + * @param[out] module_number Module number to get. + */ + fsp_err_t (* moduleNumberGet)(usb_ctrl_t * const p_ctrl, uint8_t * module_number); + + /** This API gets the module number. + * + * @param[in] p_ctrl USB control structure. + * @param[out] class_type Class type to get. + */ + fsp_err_t (* classTypeGet)(usb_ctrl_t * const p_ctrl, usb_class_t * class_type); + + /** This API gets the device address. + * + * @param[in] p_ctrl USB control structure. + * @param[out] device_address Device address to get. + */ + fsp_err_t (* deviceAddressGet)(usb_ctrl_t * const p_ctrl, uint8_t * device_address); + + /** This API gets the pipe number. + * + * @param[in] p_ctrl USB control structure. + * @param[out] pipe_number Pipe number to get. + */ + fsp_err_t (* pipeNumberGet)(usb_ctrl_t * const p_ctrl, uint8_t * pipe_number); + + /** This API gets the state of the device. + * + * @param[in] p_ctrl USB control structure. + * @param[out] state Device state to get. + */ + fsp_err_t (* deviceStateGet)(usb_ctrl_t * const p_ctrl, uint16_t * state); + + /** This API gets the data size. + * + * @param[in] p_ctrl USB control structure. + * @param[out] data_size Data size to get. + */ + fsp_err_t (* dataSizeGet)(usb_ctrl_t * const p_ctrl, uint32_t * data_size); + + /** This API gets the setup type. + * + * @param[in] p_ctrl USB control structure. + * @param[out] setup Setup type to get. + */ + fsp_err_t (* setupGet)(usb_ctrl_t * const p_ctrl, usb_setup_t * setup); + + /** This API sets the callback function for OTG. + * + * @param[in] p_ctrl USB control structure. + * @param[in] p_callback Pointer to the callback function for OTG. + */ + fsp_err_t (* otgCallbackSet)(usb_ctrl_t * const p_ctrl, usb_otg_callback_t * p_callback); + + /** This API starts SRP processing for OTG. + * + * @param[in] p_ctrl USB control structure. + */ + fsp_err_t (* otgSRP)(usb_ctrl_t * const p_ctrl); +} usb_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_usb_instance +{ + usb_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + usb_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + usb_api_t const * p_api; ///< Pointer to the API structure for this instance +} usb_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_API_H */ + +/*******************************************************************************************************************//** + * @} (end defgroup USB_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_wdt_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_wdt_api.h new file mode 100644 index 0000000000..368a8b8ccc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/api/r_wdt_api.h @@ -0,0 +1,223 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_MONITORING_INTERFACES + * @defgroup WDT_API WDT Interface + * @brief Interface for watch dog timer functions. + * + * @section WDT_API_Summary Summary + * The WDT interface for the Watchdog Timer (WDT) peripheral provides watchdog functionality including resetting the + * device or generating an interrupt. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_WDT_API_H +#define R_WDT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_WDT_TIMEOUT_T + +/** WDT time-out periods. */ +typedef enum e_wdt_timeout +{ + WDT_TIMEOUT_128 = 0, ///< 128 clock cycles + WDT_TIMEOUT_512, ///< 512 clock cycles + WDT_TIMEOUT_1024, ///< 1024 clock cycles + WDT_TIMEOUT_2048, ///< 2048 clock cycles + WDT_TIMEOUT_4096, ///< 4096 clock cycles + WDT_TIMEOUT_8192, ///< 8192 clock cycles + WDT_TIMEOUT_16384, ///< 16384 clock cycles +} wdt_timeout_t; +#endif + +#ifndef BSP_OVERRIDE_WDT_CLOCK_DIVISION_T + +/** WDT clock division ratio. */ +typedef enum e_wdt_clock_division +{ + WDT_CLOCK_DIVISION_1 = 0, ///< CLK/1 + WDT_CLOCK_DIVISION_4 = 1, ///< CLK/4 + WDT_CLOCK_DIVISION_16 = 2, ///< CLK/16 + WDT_CLOCK_DIVISION_32 = 3, ///< CLK/32 + WDT_CLOCK_DIVISION_64 = 4, ///< CLK/64 + WDT_CLOCK_DIVISION_128 = 15, ///< CLK/128 + WDT_CLOCK_DIVISION_256 = 5, ///< CLK/256 + WDT_CLOCK_DIVISION_512 = 6, ///< CLK/512 + WDT_CLOCK_DIVISION_2048 = 7, ///< CLK/2048 + WDT_CLOCK_DIVISION_8192 = 8, ///< CLK/8192 +} wdt_clock_division_t; +#endif + +#ifndef BSP_OVERRIDE_WDT_WINDOW_START_END_T + +/** WDT refresh permitted period window start position. */ +typedef enum e_wdt_window_start +{ + WDT_WINDOW_START_25 = 0, ///< Start position = 25% + WDT_WINDOW_START_50 = 1, ///< Start position = 50% + WDT_WINDOW_START_75 = 2, ///< Start position = 75% + WDT_WINDOW_START_100 = 3, ///< Start position = 100% +} wdt_window_start_t; + +/** WDT refresh permitted period window end position. */ +typedef enum e_wdt_window_end +{ + WDT_WINDOW_END_75 = 0, ///< End position = 75% + WDT_WINDOW_END_50 = 1, ///< End position = 50% + WDT_WINDOW_END_25 = 2, ///< End position = 25% + WDT_WINDOW_END_0 = 3, ///< End position = 0% +} wdt_window_end_t; +#endif + +/** WDT Counter underflow and refresh error control. */ +typedef enum e_wdt_reset_control +{ + WDT_RESET_CONTROL_NMI = 0, ///< NMI/IRQ request when counter underflows. + WDT_RESET_CONTROL_RESET = 1, ///< Reset request when counter underflows. +} wdt_reset_control_t; + +/** WDT Counter operation in sleep mode. */ +typedef enum e_wdt_stop_control +{ + WDT_STOP_CONTROL_DISABLE = 0, ///< Count will not stop when device enters sleep mode. + WDT_STOP_CONTROL_ENABLE = 1, ///< Count will automatically stop when device enters sleep mode. +} wdt_stop_control_t; + +/** WDT status */ +typedef enum e_wdt_status +{ + WDT_STATUS_NO_ERROR = 0, ///< No status flags set. + WDT_STATUS_UNDERFLOW = 1, ///< Underflow flag set. + WDT_STATUS_REFRESH_ERROR = 2, ///< Refresh error flag set. Refresh outside of permitted window. + WDT_STATUS_UNDERFLOW_AND_REFRESH_ERROR = 3, ///< Underflow and refresh error flags set. + WDT_STATUS_OVERFLOW = 4, ///< Overflow flag set. +} wdt_status_t; + +/** Callback function parameter data */ +typedef struct st_wdt_callback_args +{ + void * p_context; ///< Placeholder for user data. Set in @ref wdt_api_t::open function in @ref wdt_cfg_t. +} wdt_callback_args_t; + +/** WDT timeout data. Used to return frequency of WDT clock and timeout period */ +typedef struct st_wdt_timeout_values +{ + uint32_t clock_frequency_hz; ///< Frequency of watchdog clock after divider. + uint32_t timeout_clocks; ///< Timeout period in units of watchdog clock ticks. +} wdt_timeout_values_t; + +/** WDT control block. Allocate an instance specific control block to pass into the WDT API calls. + */ +typedef void wdt_ctrl_t; + +/** WDT configuration parameters. */ +typedef struct st_wdt_cfg +{ + wdt_timeout_t timeout; ///< Timeout period. + wdt_clock_division_t clock_division; ///< Clock divider. + wdt_window_start_t window_start; ///< Refresh permitted window start position. + wdt_window_end_t window_end; ///< Refresh permitted window end position. + wdt_reset_control_t reset_control; ///< Select NMI/IRQ or reset generated on underflow. + wdt_stop_control_t stop_control; ///< Select whether counter operates in sleep mode. + void (* p_callback)(wdt_callback_args_t * p_args); ///< Callback provided when a WDT ISR occurs. + + /** Placeholder for user data. Passed to the user callback in wdt_callback_args_t. */ + void * p_context; + void const * p_extend; ///< Placeholder for user extension. +} wdt_cfg_t; + +/** WDT functions implemented at the HAL layer will follow this API. */ +typedef struct st_wdt_api +{ + /** Initialize the WDT in register start mode. In auto-start mode (Supported devices only) with NMI output it + * registers the NMI callback. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg); + + /** Refresh the watchdog timer. + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* refresh)(wdt_ctrl_t * const p_ctrl); + + /** Read the status of the WDT. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_status Pointer to variable to return status information through. + */ + fsp_err_t (* statusGet)(wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status); + + /** Clear the status flags of the WDT. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] status Status condition(s) to clear. + */ + fsp_err_t (* statusClear)(wdt_ctrl_t * const p_ctrl, const wdt_status_t status); + + /** Read the current WDT counter value. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_count Pointer to variable to return current WDT counter value. + */ + fsp_err_t (* counterGet)(wdt_ctrl_t * const p_ctrl, uint32_t * const p_count); + + /** Read the watchdog timeout values. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_timeout Pointer to structure to return timeout values. + */ + fsp_err_t (* timeoutGet)(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the WDT control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(wdt_ctrl_t * const p_ctrl, void (* p_callback)(wdt_callback_args_t *), + void * const p_context, wdt_callback_args_t * const p_callback_memory); +} wdt_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_wdt_instance +{ + wdt_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + wdt_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + wdt_api_t const * p_api; ///< Pointer to the API structure for this instance +} wdt_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup WDT_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/fsp_features.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/fsp_features.h new file mode 100644 index 0000000000..dd54197d7d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/fsp_features.h @@ -0,0 +1,297 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_FEATURES_H +#define FSP_FEATURES_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_CFLASH = 0, ///< Code Flash + FSP_IP_DFLASH = 1, ///< Data Flash + FSP_IP_RAM = 2, ///< RAM + FSP_IP_LVD = 3, ///< Low Voltage Detection + FSP_IP_CGC = 3, ///< Clock Generation Circuit + FSP_IP_LPM = 3, ///< Low Power Modes + FSP_IP_FCU = 4, ///< Flash Control Unit + FSP_IP_ICU = 6, ///< Interrupt Control Unit + FSP_IP_DMAC = 7, ///< DMA Controller + FSP_IP_DTC = 8, ///< Data Transfer Controller + FSP_IP_IOPORT = 9, ///< I/O Ports + FSP_IP_PFS = 10, ///< Pin Function Select + FSP_IP_ELC = 11, ///< Event Link Controller + FSP_IP_MPU = 13, ///< Memory Protection Unit + FSP_IP_MSTP = 14, ///< Module Stop + FSP_IP_MMF = 15, ///< Memory Mirror Function + FSP_IP_KEY = 16, ///< Key Interrupt Function + FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit + FSP_IP_DOC = 18, ///< Data Operation Circuit + FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator + FSP_IP_SCI = 20, ///< Serial Communications Interface + FSP_IP_IIC = 21, ///< I2C Bus Interface + FSP_IP_SPI = 22, ///< Serial Peripheral Interface + FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit + FSP_IP_SCE = 24, ///< Secure Cryptographic Engine + FSP_IP_SLCDC = 25, ///< Segment LCD Controller + FSP_IP_AES = 26, ///< Advanced Encryption Standard + FSP_IP_TRNG = 27, ///< True Random Number Generator + FSP_IP_FCACHE = 30, ///< Flash Cache + FSP_IP_SRAM = 31, ///< SRAM + FSP_IP_ADC = 32, ///< A/D Converter + FSP_IP_DAC = 33, ///< 12-Bit D/A Converter + FSP_IP_TSN = 34, ///< Temperature Sensor + FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit + FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator + FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator + FSP_IP_OPAMP = 38, ///< Operational Amplifier + FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter + FSP_IP_RTC = 40, ///< Real Time Clock + FSP_IP_WDT = 41, ///< Watch Dog Timer + FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer + FSP_IP_GPT = 43, ///< General PWM Timer + FSP_IP_POEG = 44, ///< Port Output Enable for GPT + FSP_IP_OPS = 45, ///< Output Phase Switch + FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer + FSP_IP_CAN = 48, ///< Controller Area Network + FSP_IP_IRDA = 49, ///< Infrared Data Association + FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface + FSP_IP_USBFS = 51, ///< USB Full Speed + FSP_IP_SDHI = 52, ///< SD/MMC Host Interface + FSP_IP_SRC = 53, ///< Sampling Rate Converter + FSP_IP_SSI = 54, ///< Serial Sound Interface + FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface + FSP_IP_ETHER = 64, ///< Ethernet MAC Controller + FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller + FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller + FSP_IP_PDC = 66, ///< Parallel Data Capture Unit + FSP_IP_GLCDC = 67, ///< Graphics LCD Controller + FSP_IP_DRW = 68, ///< 2D Drawing Engine + FSP_IP_JPEG = 69, ///< JPEG + FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter + FSP_IP_USBHS = 71, ///< USB High Speed + FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface + FSP_IP_CEC = 73, ///< HDMI CEC + FSP_IP_TFU = 74, ///< Trigonometric Function Unit + FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator + FSP_IP_CANFD = 76, ///< CAN-FD + FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT + FSP_IP_SAU = 78, ///< Serial Array Unit + FSP_IP_IICA = 79, ///< Serial Interface IICA + FSP_IP_UARTA = 80, ///< Serial Interface UARTA + FSP_IP_TAU = 81, ///< Timer Array Unit + FSP_IP_TML = 82, ///< 32-bit Interval Timer + FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator + FSP_IP_USBCC = 84, ///< USB Type-C Controller +} fsp_ip_t; + +/** Signals that can be mapped to an interrupt. */ +typedef enum e_fsp_signal +{ + FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH + FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH + FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END + FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B + FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A + FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B + FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ + FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ + FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A + FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B + FSP_SIGNAL_AGT_INT, ///< AGT INT + FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR + FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END + FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW + FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR + FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX + FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX + FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX + FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX + FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP + FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST + FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 + FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 + FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD + FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT + FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT + FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT + FSP_SIGNAL_CTSU_END = 0, ///< CTSU END + FSP_SIGNAL_CTSU_READ, ///< CTSU READ + FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE + FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI + FSP_SIGNAL_DALI_CLI, ///< DALI CLI + FSP_SIGNAL_DALI_SDI, ///< DALI SDI + FSP_SIGNAL_DALI_BPI, ///< DALI BPI + FSP_SIGNAL_DALI_FEI, ///< DALI FEI + FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI + FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT + FSP_SIGNAL_DOC_INT = 0, ///< DOC INT + FSP_SIGNAL_DRW_INT = 0, ///< DRW INT + FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE + FSP_SIGNAL_DTC_END, ///< DTC END + FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT + FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 + FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 + FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS + FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT + FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT + FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL + FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE + FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL + FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE + FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL + FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE + FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL + FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE + FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL + FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE + FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL + FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE + FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR + FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI + FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT + FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 + FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 + FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A + FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B + FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C + FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D + FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E + FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F + FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW + FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW + FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A + FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B + FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE + FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 + FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 + FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 + FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 + FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 + FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 + FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 + FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 + FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 + FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 + FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 + FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 + FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 + FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 + FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 + FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 + FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL + FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI + FSP_SIGNAL_IIC_RXI, ///< IIC RXI + FSP_SIGNAL_IIC_TEI, ///< IIC TEI + FSP_SIGNAL_IIC_TXI, ///< IIC TXI + FSP_SIGNAL_IIC_WUI, ///< IIC WUI + FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 + FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 + FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 + FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 + FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B + FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C + FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D + FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E + FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW + FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI + FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI + FSP_SIGNAL_KEY_INT = 0, ///< KEY INT + FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END + FSP_SIGNAL_PDC_INT, ///< PDC INT + FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY + FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT + FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT + FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM + FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD + FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY + FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY + FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY + FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG + FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY + FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 + FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 + FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK + FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY + FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 + FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 + FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 + FSP_SIGNAL_SCI_AM = 0, ///< SCI AM + FSP_SIGNAL_SCI_ERI, ///< SCI ERI + FSP_SIGNAL_SCI_RXI, ///< SCI RXI + FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI + FSP_SIGNAL_SCI_TEI, ///< SCI TEI + FSP_SIGNAL_SCI_TXI, ///< SCI TXI + FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI + FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND + FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND + FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS + FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD + FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ + FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO + FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI + FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE + FSP_SIGNAL_SPI_RXI, ///< SPI RXI + FSP_SIGNAL_SPI_TEI, ///< SPI TEI + FSP_SIGNAL_SPI_TXI, ///< SPI TXI + FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END + FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY + FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL + FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW + FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW + FSP_SIGNAL_SSI_INT = 0, ///< SSI INT + FSP_SIGNAL_SSI_RXI, ///< SSI RXI + FSP_SIGNAL_SSI_TXI, ///< SSI TXI + FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI + FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ + FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 + FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 + FSP_SIGNAL_USB_INT, ///< USB INT + FSP_SIGNAL_USB_RESUME, ///< USB RESUME + FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME + FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW + FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A + FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B + FSP_SIGNAL_ULPT_INT, ///< ULPT INT +} fsp_signal_t; + +typedef void (* fsp_vector_t)(void); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/fsp_version.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/fsp_version.h new file mode 100644 index 0000000000..eaaaab2cd1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/fsp_version.h @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef FSP_VERSION_H + #define FSP_VERSION_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ + #include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup RENESAS_COMMON + * @{ + **********************************************************************************************************************/ + + #ifdef __cplusplus +extern "C" { + #endif + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** FSP pack major version. */ + #define FSP_VERSION_MAJOR (6U) + +/** FSP pack minor version. */ + #define FSP_VERSION_MINOR (3U) + +/** FSP pack patch version. */ + #define FSP_VERSION_PATCH (0U) + +/** FSP pack version build number (currently unused). */ + #define FSP_VERSION_BUILD (0U) + +/** Public FSP version name. */ + #define FSP_VERSION_STRING ("6.3.0") + +/** Unique FSP version ID. */ + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 6.3.0") + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** FSP Pack version structure */ +typedef union st_fsp_pack_version +{ + /** Version id */ + uint32_t version_id; + + /** + * Code version parameters, little endian order. + */ + struct version_id_b_s + { + uint8_t build; ///< Build version of FSP Pack + uint8_t patch; ///< Patch version of FSP Pack + uint8_t minor; ///< Minor version of FSP Pack + uint8_t major; ///< Major version of FSP Pack + } version_id_b; +} fsp_pack_version_t; + +/** @} */ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_acmphs.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_acmphs.h new file mode 100644 index 0000000000..28d8a23143 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_acmphs.h @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_ACMPHS_H +#define R_ACMPHS_H + +/*******************************************************************************************************************//** + * @addtogroup ACMPHS + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_comparator_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum +{ + ACMPHS_INPUT_NONE = 0, + ACMPHS_INPUT_IVCMP0 = 1, + ACMPHS_INPUT_IVCMP1 = 2, + ACMPHS_INPUT_IVCMP2 = 4, + ACMPHS_INPUT_IVCMP3 = 8, + ACMPHS_INPUT_IVCMP4 = 16, + ACMPHS_INPUT_IVCMP5 = 32, +} acmphs_input_t; + +typedef enum +{ + ACMPHS_REFERENCE_NONE = 0, + ACMPHS_REFERENCE_IVREF0 = 1, + ACMPHS_REFERENCE_IVREF1 = 2, + ACMPHS_REFERENCE_IVREF2 = 4, + ACMPHS_REFERENCE_IVREF3 = 8, + ACMPHS_REFERENCE_IVREF4 = 16, + ACMPHS_REFERENCE_IVREF5 = 32, +} acmphs_reference_t; + +/* ACMPHS extended configuration */ +typedef struct +{ + acmphs_input_t input_voltage; + acmphs_reference_t reference_voltage; + uint32_t maximum_status_retries; // Maximum number of status retries allowed +} r_acmphs_extended_cfg_t; + +/* Channel instance control block. DO NOT INITIALIZE. Initialization occurs in @ref comparator_api_t::open. */ +typedef struct st_acmphs_instance_ctrl +{ + uint32_t open; // Used to determine if channel control block is in use + const comparator_cfg_t * p_cfg; // Pointer to initial configurations + R_ACMPHS0_Type * p_reg; // Pointer to register base address + uint32_t maximum_status_retries; // Maximum number of status retries allowed +} acmphs_instance_ctrl_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/* @cond INC_HEADER_DEFS_SEC */ +/* Filled in Interface API structure for this Instance. */ +extern const comparator_api_t g_comparator_on_acmphs; + +/* @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_ACMPHS_Open(comparator_ctrl_t * p_ctrl, comparator_cfg_t const * const p_cfg); +fsp_err_t R_ACMPHS_OutputEnable(comparator_ctrl_t * const p_ctrl); +fsp_err_t R_ACMPHS_InfoGet(comparator_ctrl_t * const p_ctrl, comparator_info_t * const p_info); +fsp_err_t R_ACMPHS_StatusGet(comparator_ctrl_t * const p_ctrl, comparator_status_t * const p_status); +fsp_err_t R_ACMPHS_Close(comparator_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup ACMPHS) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_ACMPHS_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_acmplp.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_acmplp.h new file mode 100644 index 0000000000..88c159d8e9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_acmplp.h @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_ACMPLP_H +#define R_ACMPLP_H + +/*******************************************************************************************************************//** + * @addtogroup ACMPLP + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_comparator_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + **********************************************************************************************************************/ +typedef enum +{ + ACMPLP_INPUT_NONE = 0, + ACMPLP_INPUT_CMPIN = 1, + ACMPLP_INPUT_AMPO = 2, ///< Not available on all MCUs + ACMPLP_INPUT_CMPIN_1 = 4, ///< Not available on all MCUs +} acmplp_input_t; + +typedef enum +{ + ACMPLP_REFERENCE_NONE = 0, + ACMPLP_REFERENCE_CMPREF = 1, + ACMPLP_REFERENCE_DAC8 = 2, + ACMPLP_REFERENCE_CMPREF_1 = 4, ///< Not available on all MCUs +} acmplp_reference_t; + +/* ACMPLP extended configuration */ +typedef struct +{ + acmplp_input_t input_voltage; + acmplp_reference_t reference_voltage; +} r_acmplp_extended_cfg_t; + +/* Channel instance control block. DO NOT INITIALIZE. Initialization occurs in @ref comparator_api_t::open. */ +typedef struct st_acmplp_instance_ctrl +{ + uint32_t open; // Used to determine if channel control block is in use + const comparator_cfg_t * p_cfg; // Pointer to initial configurations + uint8_t output_enabled; // 0: output disabled, 1: output enabled +} acmplp_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const comparator_api_t g_comparator_on_acmplp; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_ACMPLP_Open(comparator_ctrl_t * const p_ctrl, comparator_cfg_t const * const p_cfg); +fsp_err_t R_ACMPLP_OutputEnable(comparator_ctrl_t * const p_ctrl); +fsp_err_t R_ACMPLP_InfoGet(comparator_ctrl_t * const p_ctrl, comparator_info_t * const p_info); +fsp_err_t R_ACMPLP_StatusGet(comparator_ctrl_t * const p_ctrl, comparator_status_t * const p_status); +fsp_err_t R_ACMPLP_Close(comparator_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup ACMPLP) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_ACMPLP_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_adc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_adc.h new file mode 100644 index 0000000000..826ade0489 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_adc.h @@ -0,0 +1,372 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_ADC_H +#define R_ADC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include + +/* Fixed width integer support. */ +#include + +/* bool support */ +#include +#include "bsp_api.h" +#include "r_adc_cfg.h" +#include "r_adc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup ADC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Typical values that can be used to modify the sample states. + * The minimum sample state count value is either 6 or 7 depending on the clock ratios. + * It is fixed to 7 based on the fact that at the lowest ADC conversion clock supported (1 MHz) + * this extra state will lead to at worst a "1 microsecond" increase in conversion time. + * At 60 MHz the extra sample state will add 16.7 ns to the conversion time. + */ +#define ADC_SAMPLE_STATE_COUNT_MIN (7U) +#define ADC_SAMPLE_STATE_COUNT_MAX (255U) + +/* Typical values that can be used for the sample and hold counts for the channels 0-2*/ +/* Minimum sample and hold states */ +#define ADC_SAMPLE_STATE_HOLD_COUNT_MIN (4U) + +/* Default sample and hold states */ +#define ADC_SAMPLE_STATE_HOLD_COUNT_DEFAULT (24U) + +/** For ADC Scan configuration adc_channel_cfg_t::scan_mask, adc_channel_cfg_t::scan_mask_group_b, + * adc_channel_cfg_t::add_mask and adc_channel_cfg_t::sample_hold_mask. + * Use bitwise OR to combine these masks for desired channels and sensors. */ +typedef enum e_adc_mask +{ + ADC_MASK_OFF = (0U), ///< No channels selected + ADC_MASK_CHANNEL_0 = (1U << 0U), ///< Channel 0 mask + ADC_MASK_CHANNEL_1 = (1U << 1U), ///< Channel 1 mask + ADC_MASK_CHANNEL_2 = (1U << 2U), ///< Channel 2 mask + ADC_MASK_CHANNEL_3 = (1U << 3U), ///< Channel 3 mask + ADC_MASK_CHANNEL_4 = (1U << 4U), ///< Channel 4 mask + ADC_MASK_CHANNEL_5 = (1U << 5U), ///< Channel 5 mask + ADC_MASK_CHANNEL_6 = (1U << 6U), ///< Channel 6 mask + ADC_MASK_CHANNEL_7 = (1U << 7U), ///< Channel 7 mask + ADC_MASK_CHANNEL_8 = (1U << 8U), ///< Channel 8 mask + ADC_MASK_CHANNEL_9 = (1U << 9U), ///< Channel 9 mask + ADC_MASK_CHANNEL_10 = (1U << 10U), ///< Channel 10 mask + ADC_MASK_CHANNEL_11 = (1U << 11U), ///< Channel 11 mask + ADC_MASK_CHANNEL_12 = (1U << 12U), ///< Channel 12 mask + ADC_MASK_CHANNEL_13 = (1U << 13U), ///< Channel 13 mask + ADC_MASK_CHANNEL_14 = (1U << 14U), ///< Channel 14 mask + ADC_MASK_CHANNEL_15 = (1U << 15U), ///< Channel 15 mask + ADC_MASK_CHANNEL_16 = (1U << 16U), ///< Channel 16 mask + ADC_MASK_CHANNEL_17 = (1U << 17U), ///< Channel 17 mask + ADC_MASK_CHANNEL_18 = (1U << 18U), ///< Channel 18 mask + ADC_MASK_CHANNEL_19 = (1U << 19U), ///< Channel 19 mask + ADC_MASK_CHANNEL_20 = (1U << 20U), ///< Channel 20 mask + ADC_MASK_CHANNEL_21 = (1U << 21U), ///< Channel 21 mask + ADC_MASK_CHANNEL_22 = (1U << 22U), ///< Channel 22 mask + ADC_MASK_CHANNEL_23 = (1U << 23U), ///< Channel 23 mask + ADC_MASK_CHANNEL_24 = (1U << 24U), ///< Channel 24 mask + ADC_MASK_CHANNEL_25 = (1U << 25U), ///< Channel 25 mask + ADC_MASK_CHANNEL_26 = (1U << 26U), ///< Channel 26 mask + ADC_MASK_CHANNEL_27 = (1U << 27U), ///< Channel 27 mask + ADC_MASK_CHANNEL_28 = (1U << 28U), ///< Channel 28 mask + ADC_MASK_TEMPERATURE = (1U << 29UL), ///< Temperature sensor channel mask + ADC_MASK_VOLT = (1U << 30UL), ///< Voltage reference channel mask + ADC_MASK_SENSORS = (ADC_MASK_TEMPERATURE | ADC_MASK_VOLT), ///< All sensor channel mask +} adc_mask_t; + +/** ADC data sample addition and averaging options */ +typedef enum e_adc_add +{ + ADC_ADD_OFF = 0, ///< Addition turned off for channels/sensors + ADC_ADD_TWO = 1, ///< Add two samples + ADC_ADD_THREE = 2, ///< Add three samples + ADC_ADD_FOUR = 3, ///< Add four samples + ADC_ADD_SIXTEEN = 5, ///< Add sixteen samples + ADC_ADD_AVERAGE_TWO = 0x81, ///< Average two samples + ADC_ADD_AVERAGE_FOUR = 0x83, ///< Average four samples + ADC_ADD_AVERAGE_EIGHT = 0x84, ///< Average eight samples + ADC_ADD_AVERAGE_SIXTEEN = 0x85, ///< Add sixteen samples +} adc_add_t; + +/** ADC clear after read definitions */ +typedef enum e_adc_clear +{ + ADC_CLEAR_AFTER_READ_OFF = 0, ///< Clear after read off + ADC_CLEAR_AFTER_READ_ON = 1 ///< Clear after read on +} adc_clear_t; + +/* VREF configuration options, not all options are available on all MCUs. If the MCU does not have VREFAMPCNT or + * ADHVREFCNT. */ +typedef enum e_adc_vref_control +{ + /* Available selections on MCUs with VREFAMPCNT. + * Refer Table "VREFADC output voltage control list" in the ADC section of the relevant hardware manual.*/ + + ADC_VREF_CONTROL_VREFH = 0, ///< VREFAMPCNT reset value. VREFADC Output voltage is Hi-Z + ADC_VREF_CONTROL_1_5V_OUTPUT = 25, ///< BGR turn ON. VREFADC Output voltage is 1.5 V + ADC_VREF_CONTROL_2_0V_OUTPUT = 29, ///< BGR turn ON. VREFADC Output voltage is 2.0 V + ADC_VREF_CONTROL_2_5V_OUTPUT = 31, ///< BGR turn ON. VREFADC Output voltage is 2.5 V + + /* Available selections on MCUs with ADHVREFCNT. + * Reference Section "A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT)" description + * in the ADC section of the relevant hardware manual.*/ + + ADC_VREF_CONTROL_AVCC0_AVSS0 = 0x0, ///< High potential is AVCC0, low potential is AVSS0 + ADC_VREF_CONTROL_VREFH0_AVSS0 = 0x1, ///< High potential is VREFH0, low potential is AVSS0 + + /** High potential is internal reference voltage, low potential is AVSS0. When the high potential is set to the + * internal reference voltage, wait 5 us after R_ADC_Open() to start an ADC measurement. */ + ADC_VREF_CONTROL_IVREF_AVSS0 = 0x2, + ADC_VREF_CONTROL_AVCC0_VREFL0 = 0x10, ///< High potential is AVCC0, low potential is VREFL0 + ADC_VREF_CONTROL_VREFH0_VREFL0 = 0x11, ///< High potential is VREFH0, low potential is VREFL0 + + /** High potential is internal reference voltage, low potential is VREFL0. When the high potential is set to the + * internal reference voltage, wait 5 us after R_ADC_Open() to start an ADC measurement. */ + ADC_VREF_CONTROL_IVREF_VREFL0 = 0x12, +} adc_vref_control_t; + +/** ADC sample state registers */ +typedef enum e_adc_sample_state_reg +{ + ADC_SAMPLE_STATE_CHANNEL_0 = 0, ///< Sample state register channel 0 + ADC_SAMPLE_STATE_CHANNEL_1, ///< Sample state register channel 1 + ADC_SAMPLE_STATE_CHANNEL_2, ///< Sample state register channel 2 + ADC_SAMPLE_STATE_CHANNEL_3, ///< Sample state register channel 3 + ADC_SAMPLE_STATE_CHANNEL_4, ///< Sample state register channel 4 + ADC_SAMPLE_STATE_CHANNEL_5, ///< Sample state register channel 5 + ADC_SAMPLE_STATE_CHANNEL_6, ///< Sample state register channel 6 + ADC_SAMPLE_STATE_CHANNEL_7, ///< Sample state register channel 7 + ADC_SAMPLE_STATE_CHANNEL_8, ///< Sample state register channel 8 + ADC_SAMPLE_STATE_CHANNEL_9, ///< Sample state register channel 9 + ADC_SAMPLE_STATE_CHANNEL_10, ///< Sample state register channel 10 + ADC_SAMPLE_STATE_CHANNEL_11, ///< Sample state register channel 11 + ADC_SAMPLE_STATE_CHANNEL_12, ///< Sample state register channel 12 + ADC_SAMPLE_STATE_CHANNEL_13, ///< Sample state register channel 13 + ADC_SAMPLE_STATE_CHANNEL_14, ///< Sample state register channel 14 + ADC_SAMPLE_STATE_CHANNEL_15, ///< Sample state register channel 15 + ADC_SAMPLE_STATE_CHANNEL_16_TO_31 = -3, ///< Sample state register channel 16 to 31 +} adc_sample_state_reg_t; + +/** ADC comparison settings */ +typedef enum e_adc_compare_cfg +{ + ADC_COMPARE_CFG_EVENT_OUTPUT_OR = 0, + ADC_COMPARE_CFG_EVENT_OUTPUT_XOR = 1, + ADC_COMPARE_CFG_EVENT_OUTPUT_AND = 2, + ADC_COMPARE_CFG_A_ENABLE = R_ADC0_ADCMPCR_CMPAE_Msk | R_ADC0_ADCMPCR_CMPAIE_Msk, + ADC_COMPARE_CFG_B_ENABLE = R_ADC0_ADCMPCR_CMPBE_Msk | R_ADC0_ADCMPCR_CMPBIE_Msk, + ADC_COMPARE_CFG_WINDOW_ENABLE = R_ADC0_ADCMPCR_WCMPE_Msk, +} adc_compare_cfg_t; + +/** ADC Window B channel */ +typedef enum e_adc_window_b_channel +{ + ADC_WINDOW_B_CHANNEL_0 = 0, + ADC_WINDOW_B_CHANNEL_1, + ADC_WINDOW_B_CHANNEL_2, + ADC_WINDOW_B_CHANNEL_3, + ADC_WINDOW_B_CHANNEL_4, + ADC_WINDOW_B_CHANNEL_5, + ADC_WINDOW_B_CHANNEL_6, + ADC_WINDOW_B_CHANNEL_7, + ADC_WINDOW_B_CHANNEL_8, + ADC_WINDOW_B_CHANNEL_9, + ADC_WINDOW_B_CHANNEL_10, + ADC_WINDOW_B_CHANNEL_11, + ADC_WINDOW_B_CHANNEL_12, + ADC_WINDOW_B_CHANNEL_13, + ADC_WINDOW_B_CHANNEL_14, + ADC_WINDOW_B_CHANNEL_15, + ADC_WINDOW_B_CHANNEL_16, + ADC_WINDOW_B_CHANNEL_17, + ADC_WINDOW_B_CHANNEL_18, + ADC_WINDOW_B_CHANNEL_19, + ADC_WINDOW_B_CHANNEL_20, + ADC_WINDOW_B_CHANNEL_21, + ADC_WINDOW_B_CHANNEL_22, + ADC_WINDOW_B_CHANNEL_23, + ADC_WINDOW_B_CHANNEL_24, + ADC_WINDOW_B_CHANNEL_25, + ADC_WINDOW_B_CHANNEL_26, + ADC_WINDOW_B_CHANNEL_27, + ADC_WINDOW_B_CHANNEL_28, + ADC_WINDOW_B_CHANNEL_TEMPERATURE = 32, + ADC_WINDOW_B_CHANNEL_VOLT = 33, + ADC_WINDOW_B_CHANNEL_NONE = 63, +} adc_window_b_channel_t; + +/** ADC Window B comparison mode */ +typedef enum e_adc_window_b_mode +{ + ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE = 0, + ADC_WINDOW_B_MODE_GREATER_THAN_OR_INSIDE = R_ADC0_ADCMPBNSR_CMPLB_Msk, +} adc_window_b_mode_t; + +/** ADC action for group A interrupts group B scan. + * This enumeration is used to specify the priority between Group A and B in group mode. */ +typedef enum e_adc_group_a +{ + ADC_GROUP_A_PRIORITY_OFF = 0, ///< Group A ignored and does not interrupt ongoing group B scan + ADC_GROUP_A_GROUP_B_WAIT_FOR_TRIGGER = 1, ///< Group A interrupts Group B(single scan) which restarts at next Group B trigger + ADC_GROUP_A_GROUP_B_RESTART_SCAN = 3, ///< Group A interrupts Group B(single scan) which restarts immediately after Group A scan is complete + ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN = 0x8001, ///< Group A interrupts Group B(continuous scan) which continues scanning without a new Group B trigger +} adc_group_a_t; + +/** ADC double-trigger mode definitions */ +typedef enum e_adc_double_trigger +{ + ADC_DOUBLE_TRIGGER_DISABLED = 0, ///< Double-triggering disabled + ADC_DOUBLE_TRIGGER_ENABLED = 1, ///< Double-triggering enabled + ADC_DOUBLE_TRIGGER_ENABLED_EXTENDED = 2, ///< Double-triggering enabled on both ADC ELC events +} adc_double_trigger_t; + +/** ADC Trigger synchronous start source + * Note: not all sources are available for all MCUs or channels. See User Manual for more information. */ +typedef enum +{ + ADC_START_SOURCE_DISABLED = 0x3F, ///< ELC/GPT Start source disabled (For use with software start) + ADC_START_SOURCE_ASYNC_EXTERNAL = 0x00, ///< External Trigger Input + ADC_START_SOURCE_ELC_AD0 = 0x09, ///< ELC_AD0 (Converter 0 and Converter 1) + ADC_START_SOURCE_ELC_AD1 = 0x0A, ///< ELC_AD1 (Converter 0 and Converter 1) + ADC_START_SOURCE_ELC_AD01 = 0x0B, ///< ELC_AD0 and ELC_AD1 (Converter 0) also ELC_AD0 and ELC_AD1 (Converter 1) + ADC_START_SOURCE_GPT_A0_A4 = 0x11, ///< GTADTRA0 (Converter 0) and GTADTRA4 (Converter 1) + ADC_START_SOURCE_GPT_B0_B4 = 0x12, ///< GTADTRB0 (Converter 0) and GTADTRB4 (Converter 1) + ADC_START_SOURCE_GPT_A1_A5 = 0x13, ///< GTADTRA1 (Converter 0) and GTADTRB5 (Converter 1) + ADC_START_SOURCE_GPT_B1_B5 = 0x14, ///< GTADTRB1 (Converter 0) and GTADTRB5 (Converter 1) + ADC_START_SOURCE_GPT_A2_A6 = 0x15, ///< GTADTRA2 (Converter 0) and GTADTRA6 (Converter 1) + ADC_START_SOURCE_GPT_B2_B6 = 0x16, ///< GTADTRB2 (Converter 0) and GTADTRB6 (Converter 1) + ADC_START_SOURCE_GPT_A3_A7 = 0x17, ///< GTADTRA3 (Converter 0) and GTADTRA7 (Converter 1) + ADC_START_SOURCE_GPT_B3_B7 = 0x18, ///< GTADTRB3 (Converter 0) and GTADTRB7 (Converter 1) + ADC_START_SOURCE_GPT_AB0_AB4 = 0x19, ///< GTADTRA/B0 (Converter 0) and GTADTRA/B4 (Converter 1) + ADC_START_SOURCE_GPT_AB1_AB5 = 0x1A, ///< GTADTRA/B1 (Converter 0) and GTADTRA/B5 (Converter 1) + ADC_START_SOURCE_GPT_AB2_AB6 = 0x1B, ///< GTADTRA/B2 (Converter 0) and GTADTRA/B6 (Converter 1) + ADC_START_SOURCE_GPT_AB3_AB7 = 0x1C, ///< GTADTRA/B3 (Converter 0) and GTADTRA/B7 (Converter 1) +} adc_start_source_t; + +/** ADC sample state configuration */ +typedef struct st_adc_sample_state +{ + adc_sample_state_reg_t reg_id; ///< Sample state register ID + uint8_t num_states; ///< Number of sampling states for conversion. Ch16-20/21 use the same value. +} adc_sample_state_t; + +/** ADC Window Compare configuration */ +typedef struct st_adc_window_cfg +{ + uint32_t compare_mask; ///< Channel mask to compare with Window A + uint32_t compare_mode_mask; ///< Per-channel condition mask for Window A + adc_compare_cfg_t compare_cfg; ///< Window Compare configuration + uint16_t compare_ref_low; ///< Window A lower reference value + uint16_t compare_ref_high; ///< Window A upper reference value + uint16_t compare_b_ref_low; ///< Window B lower reference value + uint16_t compare_b_ref_high; ///< Window A upper reference value + adc_window_b_channel_t compare_b_channel; ///< Window B channel + adc_window_b_mode_t compare_b_mode; ///< Window B condition setting +} adc_window_cfg_t; + +/** Extended configuration structure for ADC. */ +typedef struct st_adc_extended_cfg +{ + adc_add_t add_average_count; ///< Add or average samples + adc_clear_t clearing; ///< Clear after read + adc_start_source_t trigger; ///< Trigger source for ADC + adc_start_source_t trigger_group_b; ///< Trigger source for ADC group B; valid only for group mode + adc_double_trigger_t double_trigger_mode; ///< Double-trigger mode setting + adc_vref_control_t adc_vref_control; ///< VREFADC output voltage control + uint8_t enable_adbuf; ///< Enable ADC Ring Buffer, Valid only to use along with DMAC transfer + IRQn_Type window_a_irq; ///< IRQ number for Window Compare A interrupts + IRQn_Type window_b_irq; ///< IRQ number for Window Compare B interrupts + uint8_t window_a_ipl; ///< Priority for Window Compare A interrupts + uint8_t window_b_ipl; ///< Priority for Window Compare B interrupts +} adc_extended_cfg_t; + +/** ADC channel(s) configuration */ +typedef struct st_adc_channel_cfg +{ + uint32_t scan_mask; ///< Channels/bits: bit 0 is ch0; bit 15 is ch15. + uint32_t scan_mask_group_b; ///< Valid for group modes. + uint32_t add_mask; ///< Valid if add enabled in Open(). + adc_window_cfg_t * p_window_cfg; ///< Pointer to Window Compare configuration + adc_group_a_t priority_group_a; ///< Valid for group modes. + uint8_t sample_hold_mask; ///< Channels/bits 0-2. + uint8_t sample_hold_states; ///< Number of states to be used for sample and hold. Affects channels 0-2. +} adc_channel_cfg_t; + +/* Sample and hold Channel mask. Sample and hold is only available for channel 0,1,2*/ +#define ADC_SAMPLE_HOLD_CHANNELS (0x07U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** ADC instance control block. DO NOT INITIALIZE. Initialized in @ref adc_api_t::open(). */ +typedef struct +{ + R_ADC0_Type * p_reg; // Base register for this unit + adc_cfg_t const * p_cfg; + uint32_t opened; // Boolean to verify that the Unit has been initialized + uint32_t initialized; // Initialized status of ADC + uint32_t scan_mask; // Scan mask used for Normal scan + uint16_t scan_start_adcsr; + + void (* p_callback)(adc_callback_args_t *); // Pointer to callback that is called when an adc_event_t occurs. + adc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void * p_context; +} adc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Interface Structure for user access */ +extern const adc_api_t g_adc_on_adc; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_ADC_Open(adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg); +fsp_err_t R_ADC_ScanCfg(adc_ctrl_t * p_ctrl, void const * const p_channel_cfg); +fsp_err_t R_ADC_InfoGet(adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info); +fsp_err_t R_ADC_ScanStart(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_ScanGroupStart(adc_ctrl_t * p_ctrl, adc_group_mask_t group_id); +fsp_err_t R_ADC_ScanStop(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_StatusGet(adc_ctrl_t * p_ctrl, adc_status_t * p_status); +fsp_err_t R_ADC_Read(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data); +fsp_err_t R_ADC_Read32(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data); +fsp_err_t R_ADC_SampleStateCountSet(adc_ctrl_t * p_ctrl, adc_sample_state_t * p_sample); +fsp_err_t R_ADC_Close(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_OffsetSet(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset); +fsp_err_t R_ADC_Calibrate(adc_ctrl_t * const p_ctrl, void const * p_extend); +fsp_err_t R_ADC_CallbackSet(adc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(adc_callback_args_t *), + void * const p_context, + adc_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end defgroup ADC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_agt.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_agt.h new file mode 100644 index 0000000000..a05ac54bfe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_agt.h @@ -0,0 +1,196 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_AGT_H +#define R_AGT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_agt_cfg.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Leading zeroes removed to avoid coding standards violation. */ + +/** Maximum number of clock counts for standard AGT peripheral. */ +#define AGT_MAX_CLOCK_COUNTS_16BIT (UINT16_MAX) + +/** Maximum number of clock counts for AGTW peripheral. */ +#define AGT_MAX_CLOCK_COUNTS_32BIT (UINT32_MAX) + +/** Maximum period value allowed for standard AGT peripheral. */ +#define AGT_MAX_PERIOD_16BIT (UINT16_MAX + 1U) + +/** Maximum period valud allowed for AGTW peripheral. */ +#define AGT_MAX_PERIOD_32BIT (UINT32_MAX) + +/*******************************************************************************************************************//** + * @addtogroup AGT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Count source */ +typedef enum e_agt_clock +{ + AGT_CLOCK_PCLKB = 0x00, ///< PCLKB count source, division by 1, 2, or 8 allowed + AGT_CLOCK_LOCO = 0x40, ///< LOCO count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed + AGT_CLOCK_AGT_UNDERFLOW = 0x50, ///< Underflow event signal from next lowest AGT channel, division must be 1 + AGT_CLOCK_SUBCLOCK = 0x60, ///< Subclock count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed + AGT_CLOCK_P402 = 0x92, ///< Counts events on P402, events are counted in deep software standby mode + AGT_CLOCK_P403 = 0x93, ///< Counts events on P403, events are counted in deep software standby mode + AGT_CLOCK_P404 = 0x91, ///< Counts events on P404, events are counted in deep software standby mode + AGT_CLOCK_AGTIO = 0x80, ///< Counts events on AGTIOn, events are not counted in software standby modes +} agt_clock_t; + +/** Enable pin for event counting mode. */ +typedef enum e_agt_measure +{ + AGT_MEASURE_DISABLED = 1U, ///< AGT used as a counter + AGT_MEASURE_PULSE_WIDTH_LOW_LEVEL = 3U, ///< AGT used to measure low level pulse width + AGT_MEASURE_PULSE_WIDTH_HIGH_LEVEL = 0x13U, ///< AGT used to measure high level pulse width + AGT_MEASURE_PULSE_PERIOD = 4U, ///< AGT used to measure pulse period +} agt_measure_t; + +/** Input filter, applies AGTIO in pulse period measurement, pulse width measurement, or event counter mode. The filter + * requires the signal to be at the same level for 3 successive reads at the specified filter frequency. */ +typedef enum e_agt_agtio_filter +{ + AGT_AGTIO_FILTER_NONE = 0x00U, ///< No filter + AGT_AGTIO_FILTER_PCLKB = 0x10U, ///< Filter at PCLKB + AGT_AGTIO_FILTER_PCLKB_DIV_8 = 0x20U, ///< Filter at PCLKB / 8 + AGT_AGTIO_FILTER_PCLKB_DIV_32 = 0x30U, ///< Filter at PCLKB / 32 +} agt_agtio_filter_t; + +/** Enable pin for event counting mode. */ +typedef enum e_agt_enable_pin +{ + AGT_ENABLE_PIN_NOT_USED = 0U, ///< AGTEE/AGTWEE is not used + AGT_ENABLE_PIN_ACTIVE_LOW = 0x40U, ///< Events are only counted when AGTEE/AGTWEE is low + AGT_ENABLE_PIN_ACTIVE_HIGH = 0x44U, ///< Events are only counted when AGTEE/AGTWEE is high +} agt_enable_pin_t; + +/** Trigger edge for pulse period measurement mode and event counting mode. */ +typedef enum e_agt_trigger_edge +{ + AGT_TRIGGER_EDGE_RISING = 0U, ///< Measurement starts or events are counted on rising edge + AGT_TRIGGER_EDGE_FALLING = 1U, ///< Measurement starts or events are counted on falling edge + AGT_TRIGGER_EDGE_BOTH = 8U, ///< Events are counted on both edges (n/a for pulse period mode) +} agt_trigger_edge_t; + +/** Output pins, used to select which duty cycle to update in R_AGT_DutyCycleSet(). */ +typedef enum e_agt_output_pin +{ + AGT_OUTPUT_PIN_AGTOA = 0, ///< AGTOA + AGT_OUTPUT_PIN_AGTOB = 1, ///< AGTOB +} agt_output_pin_t; + +/** Level of AGT pin */ +typedef enum e_agt_pin_cfg +{ + AGT_PIN_CFG_DISABLED = 0, ///< Not used as output pin + AGT_PIN_CFG_START_LEVEL_LOW = 3, ///< Pin level low + AGT_PIN_CFG_START_LEVEL_HIGH = 7, ///< Pin level high +} agt_pin_cfg_t; + +/** Counter type to determine regsiter size */ +typedef enum e_agt_counter_bit_width +{ + AGT_COUNTER_BIT_WIDTH_DEFAULT = 0, ///< Legacy + AGT_COUNTER_BIT_WIDTH_16 = 1, ///< AGT + AGT_COUNTER_BIT_WIDTH_32 = 2, ///< AGTW +} agt_counter_bit_width_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_agt_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations + R_AGTX0_Type * p_reg; // Base register for this channel + bool is_agtw; // Whether or not this channel is agtw, otherwise it is agt + uint32_t period; // Current timer period (counts) + + void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs. + timer_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void * p_context; // Pointer to context to be passed into callback function +} agt_instance_ctrl_t; + +/** Optional AGT extension data structure.*/ +typedef struct st_agt_extended_cfg +{ + agt_clock_t count_source; ///< AGT channel clock source. Valid values are: AGT_CLOCK_PCLKB, AGT_CLOCK_LOCO, AGT_CLOCK_FSUB + + /* Output pin settings. */ + union + { + uint8_t agtoab_settings; + + struct + { + agt_pin_cfg_t agtoa : 3; ///< Configure AGTOA/AGTWOA pin + uint8_t : 1; + agt_pin_cfg_t agtob : 3; ///< Configure AGTOB/AGTWOB pin + } agtoab_settings_b; + }; + agt_pin_cfg_t agto : 3; ///< Configure AGTO pin @note AGTIO polarity is opposite AGTO + + /* Input pin settings. */ + agt_measure_t measurement_mode; ///< Measurement mode + agt_agtio_filter_t agtio_filter; ///< Input filter for AGTIO + agt_enable_pin_t enable_pin; ///< Enable pin (event counting only) + agt_trigger_edge_t trigger_edge; ///< Trigger edge to start pulse period measurement or count external event + agt_counter_bit_width_t counter_bit_width; ///< Counter bit width +} agt_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_agt; + +/** @endcond */ + +fsp_err_t R_AGT_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_AGT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_AGT_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_AGT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_AGT_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_AGT_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_AGT_CompareMatchSet(timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel); + +/*******************************************************************************************************************//** + * @} (end defgroup AGT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ + +FSP_FOOTER + +#endif // R_AGT_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cac.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cac.h new file mode 100644 index 0000000000..24f4536cac --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cac.h @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CAC_H +#define R_CAC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "r_cac_cfg.h" +#include "r_cac_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup CAC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CAC instance control block. DO NOT INITIALIZE. */ +typedef struct st_cac_instance_ctrl +{ + uint32_t open; // Set to "CAC" once API has been successfully opened. + cac_cfg_t const * p_cfg; + + /* Pointer to callback and optional working memory */ + void (* p_callback)(cac_callback_args_t *); + cac_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} cac_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const cac_api_t g_cac_on_cac; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CAC_Open(cac_ctrl_t * const p_ctrl, cac_cfg_t const * const p_cfg); +fsp_err_t R_CAC_StartMeasurement(cac_ctrl_t * const p_ctrl); +fsp_err_t R_CAC_StopMeasurement(cac_ctrl_t * const p_ctrl); +fsp_err_t R_CAC_Read(cac_ctrl_t * const p_ctrl, uint32_t * const p_counter); +fsp_err_t R_CAC_Close(cac_ctrl_t * const p_ctrl); +fsp_err_t R_CAC_CallbackSet(cac_ctrl_t * const p_ctrl, + void ( * p_callback)(cac_callback_args_t *), + void * const p_context, + cac_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end addtogroup CAC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_can.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_can.h new file mode 100644 index 0000000000..bafa7b497b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_can.h @@ -0,0 +1,233 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CAN_H +#define R_CAN_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_can_cfg.h" +#include "r_can_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup CAN + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CAN Status */ +typedef enum e_can_status +{ + CAN_STATUS_NEW_DATA = 1, ///< New Data status flag + CAN_STATUS_SENT_DATA = 2, ///< Sent Data status flag + CAN_STATUS_RECEIVE_FIFO = 4, ///< Receive FIFO status flag + CAN_STATUS_TRANSMIT_FIFO = 8, ///< Transmit FIFO status flag + CAN_STATUS_NORMAL_MBOX_MESSAGE_LOST = 16, ///< Normal mailbox message lost status flag + CAN_STATUS_FIFO_MBOX_MESSAGE_LOST = 32, ///< FIFO mailbox message lost status flag + CAN_STATUS_TRANSMISSION_ABORT = 64, ///< Transmission abort status flag + CAN_STATUS_ERROR = 128, ///< Error status flag + CAN_STATUS_RESET_MODE = 256, ///< Reset mode status flag + CAN_STATUS_HALT_MODE = 512, ///< Halt mode status flag + CAN_STATUS_SLEEP_MODE = 1024, ///< Sleep mode status flag + CAN_STATUS_ERROR_PASSIVE = 2048, ///< Error-passive status flag + CAN_STATUS_BUS_OFF = 4096, ///< Bus-off status flag +} can_status_t; + +/** CAN Error Code */ +typedef enum e_can_error +{ + CAN_ERROR_STUFF = 1, ///< Stuff Error + CAN_ERROR_FORM = 2, ///< Form Error + CAN_ERROR_ACK = 4, ///< ACK Error + CAN_ERROR_CRC = 8, ///< CRC Error + CAN_ERROR_BIT_RECESSIVE = 16, ///< Bit Error (recessive) Error + CAN_ERROR_BIT_DOMINANT = 32, ///< Bit Error (dominant) Error + CAN_ERROR_ACK_DELIMITER = 64, ///< ACK Delimiter Error +} can_error_t; + +/** CAN Mailbox IDs (MB + FIFO) */ +typedef enum e_can_mailbox_id +{ + CAN_MAILBOX_ID_0 = 0, + CAN_MAILBOX_ID_1 = 1, + CAN_MAILBOX_ID_2 = 2, + CAN_MAILBOX_ID_3 = 3, + CAN_MAILBOX_ID_4 = 4, + CAN_MAILBOX_ID_5 = 5, + CAN_MAILBOX_ID_6 = 6, + CAN_MAILBOX_ID_7 = 7, + CAN_MAILBOX_ID_8 = 8, + CAN_MAILBOX_ID_9 = 9, + CAN_MAILBOX_ID_10 = 10, + CAN_MAILBOX_ID_11 = 11, + CAN_MAILBOX_ID_12 = 12, + CAN_MAILBOX_ID_13 = 13, + CAN_MAILBOX_ID_14 = 14, + CAN_MAILBOX_ID_15 = 15, + CAN_MAILBOX_ID_16 = 16, + CAN_MAILBOX_ID_17 = 17, + CAN_MAILBOX_ID_18 = 18, + CAN_MAILBOX_ID_19 = 19, + CAN_MAILBOX_ID_20 = 20, + CAN_MAILBOX_ID_21 = 21, + CAN_MAILBOX_ID_22 = 22, + CAN_MAILBOX_ID_23 = 23, + CAN_MAILBOX_ID_24 = 24, + CAN_MAILBOX_ID_25 = 25, + CAN_MAILBOX_ID_26 = 26, + CAN_MAILBOX_ID_27 = 27, + CAN_MAILBOX_ID_28 = 28, + CAN_MAILBOX_ID_29 = 29, + CAN_MAILBOX_ID_30 = 30, + CAN_MAILBOX_ID_31 = 31, + + CAN_MAILBOX_ID_TX_FIFO = 24, + CAN_MAILBOX_ID_RX_FIFO = 28, +} can_mailbox_number_t; + +/** CAN Mailbox type */ +typedef enum e_can_mailbox_send_receive +{ + CAN_MAILBOX_RECEIVE, ///< Mailbox is for receiving. + CAN_MAILBOX_TRANSMIT, ///< Mailbox is for sending. +} can_mailbox_send_receive_t; + +/** Global CAN ID mode settings */ +typedef enum e_can_global_id_mode +{ + CAN_GLOBAL_ID_MODE_STANDARD, ///< Standard IDs of 11 bits used. + CAN_GLOBAL_ID_MODE_EXTENDED, ///< Extended IDs of 29 bits used. + CAN_GLOBAL_ID_MODE_MIXED, ///< Both Standard and Extended IDs used. +} can_global_id_mode_t; + +/** CAN Message Modes */ +typedef enum e_can_message_mode +{ + CAN_MESSAGE_MODE_OVERWRITE = 0, ///< Receive data will be overwritten if not read before the next frame. + CAN_MESSAGE_MODE_OVERRUN, ///< Receive data will be retained until it is read. +} can_message_mode_t; + +/** CAN Source Clock */ +typedef enum e_can_clock_source +{ + CAN_CLOCK_SOURCE_PCLKB = 0, ///< PCLKB is the source of the CAN Clock + CAN_CLOCK_SOURCE_CANMCLK, ///< CANMCLK is the source of the CAN Clock +} can_clock_source_t; + +/** CAN FIFO Interrupt Modes */ +typedef enum e_can_fifo_interrupt_mode +{ + CAN_FIFO_INTERRUPT_MODE_TX_EVERY_FRAME = R_CAN0_MIER_FIFO_MB24_Msk, + CAN_FIFO_INTERRUPT_MODE_RX_EVERY_FRAME = R_CAN0_MIER_FIFO_MB28_Msk, + CAN_FIFO_INTERRUPT_MODE_TX_EMPTY = R_CAN0_MIER_FIFO_MB25_Msk | R_CAN0_MIER_FIFO_MB24_Msk, +} can_fifo_interrupt_mode_t; + +/** CAN Mailbox */ +typedef struct st_can_mailbox +{ + /* The first three elements are the same as can_frame_t for optimization purposes. */ + uint32_t mailbox_id; ///< Mailbox ID. + can_id_mode_t id_mode; ///< Standard or Extended ID. Only used in Mixed ID mode. + can_frame_type_t frame_type; ///< Frame type for receive mailbox. + can_mailbox_send_receive_t mailbox_type; ///< Receive or Transmit mailbox type. +} can_mailbox_t; + +/** CAN FIFO interrupt configuration */ +typedef struct st_can_fifo_interrupt_cfg +{ + can_fifo_interrupt_mode_t fifo_int_mode; ///< FIFO interrupts mode (RX and TX combined). + + IRQn_Type tx_fifo_irq; ///< TX FIFO IRQ. + IRQn_Type rx_fifo_irq; ///< RX FIFO IRQ. +} can_fifo_interrupt_cfg_t; + +/** CAN RX FIFO configuration */ +typedef struct st_can_rx_fifo_cfg +{ + uint32_t rx_fifo_mask1; ///< RX FIFO acceptance filter mask 1. + uint32_t rx_fifo_mask2; ///< RX FIFO acceptance filter mask 1. + can_mailbox_t rx_fifo_id1; ///< RX FIFO acceptance filter ID 1. + can_mailbox_t rx_fifo_id2; ///< RX FIFO acceptance filter ID 2. +} can_rx_fifo_cfg_t; + +/** CAN extended configuration */ +typedef struct st_can_extended_cfg +{ + can_clock_source_t clock_source; ///< Source of the CAN clock. + uint32_t * p_mailbox_mask; ///< Mailbox mask, one for every 4 mailboxes. + can_mailbox_t * p_mailbox; ///< Pointer to mailboxes. + can_global_id_mode_t global_id_mode; ///< Standard or Extended ID mode. + uint32_t mailbox_count; ///< Number of mailboxes. + can_message_mode_t message_mode; ///< Overwrite message or overrun. + can_fifo_interrupt_cfg_t const * p_fifo_int_cfg; ///< Pointer to FIFO interrupt configuration. + can_rx_fifo_cfg_t * p_rx_fifo_cfg; ///< Pointer to RX FIFO configuration. +} can_extended_cfg_t; + +/* CAN Instance Control Block */ +typedef struct st_can_instance_ctrl +{ + /* Parameters to control CAN peripheral device */ + can_cfg_t const * p_cfg; // Pointer to the configuration structure + R_CAN0_Type * p_reg; // Pointer to register base address + uint32_t open; // Open status of channel. + can_operation_mode_t operation_mode; // Can operation mode. + can_test_mode_t test_mode; // Can operation mode. + can_id_mode_t id_mode; // Standard or Extended ID mode. + uint32_t mailbox_count; // Number of mailboxes. + can_mailbox_t * p_mailbox; // Pointer to mailboxes. + can_clock_source_t clock_source; // Clock source. CANMCLK or PCLKB. + + void (* p_callback)(can_callback_args_t *); // Pointer to callback + can_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void * p_context; // Pointer to context to be passed into callback function +} can_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const can_api_t g_can_on_can; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CAN_Open(can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_cfg); +fsp_err_t R_CAN_Close(can_ctrl_t * const p_api_ctrl); +fsp_err_t R_CAN_Write(can_ctrl_t * const p_api_ctrl, uint32_t const mailbox, can_frame_t * const p_frame); +fsp_err_t R_CAN_Read(can_ctrl_t * const p_api_ctrl, uint32_t mailbox, can_frame_t * const p_frame); +fsp_err_t R_CAN_ModeTransition(can_ctrl_t * const p_api_ctrl, + can_operation_mode_t operation_mode, + can_test_mode_t test_mode); +fsp_err_t R_CAN_InfoGet(can_ctrl_t * const p_api_ctrl, can_info_t * const p_info); +fsp_err_t R_CAN_CallbackSet(can_ctrl_t * const p_api_ctrl, + void ( * p_callback)(can_callback_args_t *), + void * const p_context, + can_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end defgroup CAN) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_canfd.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_canfd.h new file mode 100644 index 0000000000..46b19d1edc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_canfd.h @@ -0,0 +1,398 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CANFD_H +#define R_CANFD_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_canfd_cfg.h" +#include "r_can_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup CANFD + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#if BSP_FEATURE_CANFD_LITE + #define R_CANFD_NUM_COMMON_FIFOS (1U) +#else + #define R_CANFD_NUM_COMMON_FIFOS (6U) +#endif + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CANFD Status */ +typedef enum e_canfd_status +{ + CANFD_STATUS_RESET_MODE = 0x001, ///< Channel in Reset mode + CANFD_STATUS_HALT_MODE = 0x002, ///< Channel in Halt mode + CANFD_STATUS_SLEEP_MODE = 0x004, ///< Channel in Sleep mode + CANFD_STATUS_ERROR_PASSIVE = 0x008, ///< Channel in error-passive state + CANFD_STATUS_BUS_OFF = 0x010, ///< Channel in bus-off state + CANFD_STATUS_TRANSMITTING = 0x020, ///< Channel is transmitting + CANFD_STATUS_RECEIVING = 0x040, ///< Channel is receiving + CANFD_STATUS_READY = 0x080, ///< Channel is ready for communication + CANFD_STATUS_ESI = 0x100, ///< At least one CAN-FD message was received with the ESI flag set +} canfd_status_t; + +/** CANFD Error Code */ +typedef enum e_canfd_error +{ + CANFD_ERROR_CHANNEL_BUS = 0x00000001, ///< Bus Error + CANFD_ERROR_CHANNEL_WARNING = 0x00000002, ///< Error Warning (TX/RX error count over 0x5F) + CANFD_ERROR_CHANNEL_PASSIVE = 0x00000004, ///< Error Passive (TX/RX error count over 0x7F) + CANFD_ERROR_CHANNEL_BUS_OFF_ENTRY = 0x00000008, ///< Bus-Off State Entry + CANFD_ERROR_CHANNEL_BUS_OFF_RECOVERY = 0x00000010, ///< Recovery from Bus-Off State + CANFD_ERROR_CHANNEL_OVERLOAD = 0x00000020, ///< Overload + CANFD_ERROR_CHANNEL_BUS_LOCK = 0x00000040, ///< Bus Locked + CANFD_ERROR_CHANNEL_ARBITRATION_LOSS = 0x00000080, ///< Arbitration Lost + CANFD_ERROR_CHANNEL_STUFF = 0x00000100, ///< Stuff Error + CANFD_ERROR_CHANNEL_FORM = 0x00000200, ///< Form Error + CANFD_ERROR_CHANNEL_ACK = 0x00000400, ///< ACK Error + CANFD_ERROR_CHANNEL_CRC = 0x00000800, ///< CRC Error + CANFD_ERROR_CHANNEL_BIT_RECESSIVE = 0x00001000, ///< Bit Error (recessive) Error + CANFD_ERROR_CHANNEL_BIT_DOMINANT = 0x00002000, ///< Bit Error (dominant) Error + CANFD_ERROR_CHANNEL_ACK_DELIMITER = 0x00004000, ///< ACK Delimiter Error + CANFD_ERROR_GLOBAL_DLC = 0x00010000, ///< DLC Error + CANFD_ERROR_GLOBAL_MESSAGE_LOST = 0x00020000, ///< Message Lost + CANFD_ERROR_GLOBAL_PAYLOAD_OVERFLOW = 0x00080000, ///< FD Payload Overflow + CANFD_ERROR_GLOBAL_TXQ_OVERWRITE = 0x00100000, ///< TX Queue Message Overwrite + CANFD_ERROR_GLOBAL_TXQ_MESSAGE_LOST = 0x00400000, ///< TX Queue Message Lost + CANFD_ERROR_GLOBAL_CH0_SCAN_FAIL = 0x01000000, ///< Channel 0 RX Scan Failure + CANFD_ERROR_GLOBAL_CH1_SCAN_FAIL = 0x02000000, ///< Channel 1 RX Scan Failure + CANFD_ERROR_GLOBAL_CH0_ECC = 0x10000000, ///< Channel 0 ECC Error + CANFD_ERROR_GLOBAL_CH1_ECC = 0x20000000, ///< Channel 1 ECC Error +} canfd_error_t; + +/** CANFD Transmit Buffer (MB + CFIFO) */ +typedef enum e_canfd_tx_buffer +{ + CANFD_TX_BUFFER_0 = 0, + CANFD_TX_BUFFER_1 = 1, + CANFD_TX_BUFFER_2 = 2, + CANFD_TX_BUFFER_3 = 3, +#if !BSP_FEATURE_CANFD_LITE + CANFD_TX_BUFFER_4 = 4, + CANFD_TX_BUFFER_5 = 5, + CANFD_TX_BUFFER_6 = 6, + CANFD_TX_BUFFER_7 = 7, + CANFD_TX_BUFFER_32 = 32, + CANFD_TX_BUFFER_33 = 33, + CANFD_TX_BUFFER_34 = 34, + CANFD_TX_BUFFER_35 = 35, + CANFD_TX_BUFFER_36 = 36, + CANFD_TX_BUFFER_37 = 37, + CANFD_TX_BUFFER_38 = 38, + CANFD_TX_BUFFER_39 = 39, +#endif + CANFD_TX_BUFFER_FIFO_COMMON_0 = 40, +#if !BSP_FEATURE_CANFD_LITE + CANFD_TX_BUFFER_FIFO_COMMON_1 = 41, + CANFD_TX_BUFFER_FIFO_COMMON_2 = 42, +#endif +} canfd_tx_buffer_t; + +/** CANFD Transmit Message Buffer (TX MB) */ +typedef enum e_canfd_tx_mb +{ + CANFD_TX_MB_0 = 0, + CANFD_TX_MB_1 = 1, + CANFD_TX_MB_2 = 2, + CANFD_TX_MB_3 = 3, +#if !BSP_FEATURE_CANFD_LITE + CANFD_TX_MB_4 = 4, + CANFD_TX_MB_5 = 5, + CANFD_TX_MB_6 = 6, + CANFD_TX_MB_7 = 7, + CANFD_TX_MB_32 = 32, + CANFD_TX_MB_33 = 33, + CANFD_TX_MB_34 = 34, + CANFD_TX_MB_35 = 35, + CANFD_TX_MB_36 = 36, + CANFD_TX_MB_37 = 37, + CANFD_TX_MB_38 = 38, + CANFD_TX_MB_39 = 39, +#endif +} canfd_tx_mb_t; + +/** CANFD Receive Buffer (MB + FIFO + CFIFO) */ +typedef enum e_canfd_rx_buffer +{ + CANFD_RX_BUFFER_MB_0 = 0, + CANFD_RX_BUFFER_MB_1 = 1, + CANFD_RX_BUFFER_MB_2 = 2, + CANFD_RX_BUFFER_MB_3 = 3, + CANFD_RX_BUFFER_MB_4 = 4, + CANFD_RX_BUFFER_MB_5 = 5, + CANFD_RX_BUFFER_MB_6 = 6, + CANFD_RX_BUFFER_MB_7 = 7, + CANFD_RX_BUFFER_MB_8 = 8, + CANFD_RX_BUFFER_MB_9 = 9, + CANFD_RX_BUFFER_MB_10 = 10, + CANFD_RX_BUFFER_MB_11 = 11, + CANFD_RX_BUFFER_MB_12 = 12, + CANFD_RX_BUFFER_MB_13 = 13, + CANFD_RX_BUFFER_MB_14 = 14, + CANFD_RX_BUFFER_MB_15 = 15, + CANFD_RX_BUFFER_MB_16 = 16, + CANFD_RX_BUFFER_MB_17 = 17, + CANFD_RX_BUFFER_MB_18 = 18, + CANFD_RX_BUFFER_MB_19 = 19, + CANFD_RX_BUFFER_MB_20 = 20, + CANFD_RX_BUFFER_MB_21 = 21, + CANFD_RX_BUFFER_MB_22 = 22, + CANFD_RX_BUFFER_MB_23 = 23, + CANFD_RX_BUFFER_MB_24 = 24, + CANFD_RX_BUFFER_MB_25 = 25, + CANFD_RX_BUFFER_MB_26 = 26, + CANFD_RX_BUFFER_MB_27 = 27, + CANFD_RX_BUFFER_MB_28 = 28, + CANFD_RX_BUFFER_MB_29 = 29, + CANFD_RX_BUFFER_MB_30 = 30, + CANFD_RX_BUFFER_MB_31 = 31, + CANFD_RX_BUFFER_FIFO_0 = 32, + CANFD_RX_BUFFER_FIFO_1 = 33, +#if !BSP_FEATURE_CANFD_LITE + CANFD_RX_BUFFER_FIFO_2 = 34, + CANFD_RX_BUFFER_FIFO_3 = 35, + CANFD_RX_BUFFER_FIFO_4 = 36, + CANFD_RX_BUFFER_FIFO_5 = 37, + CANFD_RX_BUFFER_FIFO_6 = 38, + CANFD_RX_BUFFER_FIFO_7 = 39, +#endif + CANFD_RX_BUFFER_FIFO_COMMON_0 = 40, +#if !BSP_FEATURE_CANFD_LITE + CANFD_RX_BUFFER_FIFO_COMMON_1 = 41, + CANFD_RX_BUFFER_FIFO_COMMON_2 = 42, +#endif +} canfd_rx_buffer_t; + +/** CANFD Receive Message Buffer (RX MB) */ +typedef enum e_canfd_rx_mb +{ + CANFD_RX_MB_NONE = 0, + CANFD_RX_MB_0 = 0x80, + CANFD_RX_MB_1 = 0x80 + 1, + CANFD_RX_MB_2 = 0x80 + 2, + CANFD_RX_MB_3 = 0x80 + 3, + CANFD_RX_MB_4 = 0x80 + 4, + CANFD_RX_MB_5 = 0x80 + 5, + CANFD_RX_MB_6 = 0x80 + 6, + CANFD_RX_MB_7 = 0x80 + 7, + CANFD_RX_MB_8 = 0x80 + 8, + CANFD_RX_MB_9 = 0x80 + 9, + CANFD_RX_MB_10 = 0x80 + 10, + CANFD_RX_MB_11 = 0x80 + 11, + CANFD_RX_MB_12 = 0x80 + 12, + CANFD_RX_MB_13 = 0x80 + 13, + CANFD_RX_MB_14 = 0x80 + 14, + CANFD_RX_MB_15 = 0x80 + 15, + CANFD_RX_MB_16 = 0x80 + 16, + CANFD_RX_MB_17 = 0x80 + 17, + CANFD_RX_MB_18 = 0x80 + 18, + CANFD_RX_MB_19 = 0x80 + 19, + CANFD_RX_MB_20 = 0x80 + 20, + CANFD_RX_MB_21 = 0x80 + 21, + CANFD_RX_MB_22 = 0x80 + 22, + CANFD_RX_MB_23 = 0x80 + 23, + CANFD_RX_MB_24 = 0x80 + 24, + CANFD_RX_MB_25 = 0x80 + 25, + CANFD_RX_MB_26 = 0x80 + 26, + CANFD_RX_MB_27 = 0x80 + 27, + CANFD_RX_MB_28 = 0x80 + 28, + CANFD_RX_MB_29 = 0x80 + 29, + CANFD_RX_MB_30 = 0x80 + 30, + CANFD_RX_MB_31 = 0x80 + 31, +} canfd_rx_mb_t; + +/** CANFD Receive FIFO (RX FIFO) */ +typedef enum e_canfd_rx_fifo +{ + CANFD_RX_FIFO_0 = (1U), + CANFD_RX_FIFO_1 = (1U << 1), +#if !BSP_FEATURE_CANFD_LITE + CANFD_RX_FIFO_2 = (1U << 2), + CANFD_RX_FIFO_3 = (1U << 3), + CANFD_RX_FIFO_4 = (1U << 4), + CANFD_RX_FIFO_5 = (1U << 5), + CANFD_RX_FIFO_6 = (1U << 6), + CANFD_RX_FIFO_7 = (1U << 7), +#endif + CANFD_RX_FIFO_COMMON_0 = (1U << 8), +#if !BSP_FEATURE_CANFD_LITE + CANFD_RX_FIFO_COMMON_1 = (1U << 9), + CANFD_RX_FIFO_COMMON_2 = (1U << 10), + CANFD_RX_FIFO_COMMON_3 = (1U << 11), + CANFD_RX_FIFO_COMMON_4 = (1U << 12), + CANFD_RX_FIFO_COMMON_5 = (1U << 13), +#endif +} canfd_rx_fifo_t; + +/** CANFD AFL Minimum DLC settings */ +typedef enum e_canfd_minimum_dlc +{ + CANFD_MINIMUM_DLC_0 = 0, + CANFD_MINIMUM_DLC_1, + CANFD_MINIMUM_DLC_2, + CANFD_MINIMUM_DLC_3, + CANFD_MINIMUM_DLC_4, + CANFD_MINIMUM_DLC_5, + CANFD_MINIMUM_DLC_6, + CANFD_MINIMUM_DLC_7, + CANFD_MINIMUM_DLC_8, + CANFD_MINIMUM_DLC_12, + CANFD_MINIMUM_DLC_16, + CANFD_MINIMUM_DLC_20, + CANFD_MINIMUM_DLC_24, + CANFD_MINIMUM_DLC_32, + CANFD_MINIMUM_DLC_48, + CANFD_MINIMUM_DLC_64, +} canfd_minimum_dlc_t; + +/** CANFD Frame Options */ +typedef enum e_canfd_frame_option +{ + CANFD_FRAME_OPTION_ERROR = 0x01, ///< Error state set (ESI). + CANFD_FRAME_OPTION_BRS = 0x02, ///< Bit Rate Switching (BRS) enabled. + CANFD_FRAME_OPTION_FD = 0x04, ///< Flexible Data frame (FDF). + // CANFD_FRAME_OPTION_ONESHOT = 0x80, ///< One-shot mode (no retries). +} canfd_frame_options_t; + +/* CAN Instance Control Block */ +typedef struct st_canfd_instance_ctrl +{ + R_CANFD_Type * p_reg; // Pointer to register base address + + /* Parameters to control CAN peripheral device */ + can_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t open; // Open status of channel. + can_operation_mode_t operation_mode; // Can operation mode. + can_test_mode_t test_mode; // Can operation mode. +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transition is required to call p_callback (BLXNS) +#endif + void (* p_callback)(can_callback_args_t *); // Pointer to callback + can_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void * p_context; // Pointer to context to be passed into callback function +} canfd_instance_ctrl_t; + +/** AFL Entry (based on R_CANFD_CFDGAFL_Type in renesas.h) */ +typedef struct st_canfd_afl_entry_t +{ + union + { + uint32_t id_u32; + + struct + { + uint32_t id : 29; ///< ID to match against + uint32_t : 1; + can_frame_type_t frame_type : 1; ///< Frame type (Data or Remote) + can_id_mode_t id_mode : 1; ///< ID mode (Standard or Extended) + } id; + }; + + union + { + uint32_t mask_u32; + + struct + { + uint32_t mask_id : 29; ///< ID Mask + uint32_t : 1; + uint32_t mask_frame_type : 1; ///< Only accept frames with the configured frame type + uint32_t mask_id_mode : 1; ///< Only accept frames with the configured ID mode + } mask; + }; + + union + { + uint32_t destination_u32[2]; + + struct + { + canfd_minimum_dlc_t minimum_dlc : 4; ///< Minimum DLC value to accept (valid when DLC Check is enabled) + uint32_t : 4; + canfd_rx_mb_t rx_buffer : 8; ///< RX Message Buffer to receive messages accepted by this rule + uint32_t : 16; + canfd_rx_fifo_t fifo_select_flags; ///< RX FIFO(s) to receive messages accepted by this rule + } destination; + }; +} canfd_afl_entry_t; + +/** CANFD Global Configuration */ +typedef struct st_canfd_global_cfg +{ + uint32_t global_interrupts; ///< Global control options (CFDGCTR register setting) + uint32_t global_config; ///< Global configuration options (CFDGCFG register setting) +#if !BSP_FEATURE_CANFD_LITE + uint32_t rx_fifo_config[8]; ///< RX FIFO configuration (CFDRFCCn register settings) +#else + uint32_t rx_fifo_config[2]; ///< RX FIFO configuration (CFDRFCCn register settings) +#endif + uint32_t rx_mb_config; ///< Number and size of RX Message Buffers (CFDRMNB register setting) + uint8_t global_err_ipl; ///< Global Error interrupt priority + uint8_t rx_fifo_ipl; ///< RX FIFO interrupt priority + uint32_t common_fifo_config[R_CANFD_NUM_COMMON_FIFOS]; ///< Common FIFO configurations +} canfd_global_cfg_t; + +/** CANFD Extended Configuration */ +typedef struct st_canfd_extended_cfg +{ + canfd_afl_entry_t const * p_afl; ///< AFL rules list + uint64_t txmb_txi_enable; ///< Array of TX Message Buffer enable bits + uint32_t error_interrupts; ///< Error interrupt enable bits + can_bit_timing_cfg_t * p_data_timing; ///< FD Data Rate (when bitrate switching is used) + uint8_t delay_compensation; ///< FD Transceiver Delay Compensation (enable or disable) + canfd_global_cfg_t * p_global_cfg; ///< Global configuration (global error callback channel only) +} canfd_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const can_api_t g_canfd_on_canfd; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CANFD_Open(can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_cfg); +fsp_err_t R_CANFD_Close(can_ctrl_t * const p_api_ctrl); +fsp_err_t R_CANFD_Write(can_ctrl_t * const p_api_ctrl, uint32_t const buffer, can_frame_t * const p_frame); +fsp_err_t R_CANFD_Read(can_ctrl_t * const p_api_ctrl, uint32_t const buffer, can_frame_t * const p_frame); +fsp_err_t R_CANFD_ModeTransition(can_ctrl_t * const p_api_ctrl, + can_operation_mode_t operation_mode, + can_test_mode_t test_mode); +fsp_err_t R_CANFD_InfoGet(can_ctrl_t * const p_api_ctrl, can_info_t * const p_info); +fsp_err_t R_CANFD_CallbackSet(can_ctrl_t * const p_api_ctrl, + void ( * p_callback)(can_callback_args_t *), + void * const p_context, + can_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end defgroup CAN) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cec.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cec.h new file mode 100644 index 0000000000..f960e32afd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cec.h @@ -0,0 +1,96 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CEC_H +#define R_CEC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_cec_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup CEC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define CEC_CECFC_MASK_ALL (uint8_t) (R_CEC_CECFC_OCTRG_Msk | \ + R_CEC_CECFC_UCTRG_Msk | \ + R_CEC_CECFC_ACKCTRG_Msk | \ + R_CEC_CECFC_TCTRG_Msk | \ + R_CEC_CECFC_TXCTRG_Msk | \ + R_CEC_CECFC_ACTRG_Msk | \ + R_CEC_CECFC_BLCTRG_Msk) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* CEC Instance Control Block */ +typedef struct st_cec_instance_ctrl +{ + /* Parameters to control CEC peripheral device */ + cec_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t open; // Open status of CEC Module + cec_addr_t local_address; // Local address of this CEC device + uint8_t const * p_tx_buf; // Pointer to transmit buffer + uint32_t tx_bytes; // Number of bytes to transmit + cec_state_t state; // CEC Module state + uint8_t cecctl0; // Cached CEC Registry data + void (* p_callback)(cec_callback_args_t *); // Pointer to callback function + cec_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void * p_context; // Pointer to context to be passed into callback function +} cec_instance_ctrl_t; + +/* ACMPLP extended configuration */ +typedef struct +{ + uint8_t ctl0_clock_select; ///< CEC Clock Select Setting + uint8_t ctl0_ackten; ///< CEC ACK Bit Timing Error (Bit Width) Check Enable + uint8_t ctl1; ///< CEC Control 1 register configuration data + uint8_t err_detect_lerplen; ///< Error Pulse Output Enable for Long Bit Width Error + uint8_t err_detect_rercven; ///< Error Start Detection Reception Restart Enable + uint8_t intda_timing_select; ///< Data Interrupt Timing Selection +} cec_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const cec_api_t g_cec_on_cec; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CEC_Open(cec_ctrl_t * const p_ctrl, cec_cfg_t const * const p_cfg); +fsp_err_t R_CEC_MediaInit(cec_ctrl_t * const p_ctrl, cec_addr_t local_address); +fsp_err_t R_CEC_Close(cec_ctrl_t * const p_ctrl); +fsp_err_t R_CEC_Write(cec_ctrl_t * const p_ctrl, cec_message_t const * const p_message, uint32_t message_size); +fsp_err_t R_CEC_StatusGet(cec_ctrl_t * const p_ctrl, cec_status_t * const p_status); +fsp_err_t R_CEC_CallbackSet(cec_ctrl_t * const p_ctrl, + void ( * p_callback)(cec_callback_args_t *), + void * const p_context, + cec_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end defgroup CEC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ceu.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ceu.h new file mode 100644 index 0000000000..8d42407c85 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ceu.h @@ -0,0 +1,188 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup CEU + * @{ + **********************************************************************************************************************/ + +#ifndef R_CEU_H +#define R_CEU_H + +#include "bsp_api.h" +#include "r_capture_api.h" +#include "r_ceu.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Capture mode */ +typedef enum e_ceu_capture_mode +{ + CEU_CAPTURE_MODE_SINGLE = 0U, ///< Single image capture + CEU_CAPTURE_MODE_CONTINUOUS = 1U, ///< Continuous image capture +} ceu_capture_mode_t; + +/** Data bus width */ +typedef enum e_ceu_data_bus_size +{ + CEU_DATA_BUS_SIZE_8_BIT = 0U, ///< Data bus is 8-bit + CEU_DATA_BUS_SIZE_16_BIT = 1U, ///< Data bus is 16-bit +} ceu_data_bus_size_t; + +/** Polarity of input HSYNC signal */ +typedef enum e_ceu_hsync_polarity +{ + CEU_HSYNC_POLARITY_HIGH = 0U, ///< HSYNC signal is active high + CEU_HSYNC_POLARITY_LOW = 1U, ///< HSYNC signal is active low +} ceu_hsync_polarity_t; + +/** Polarity of input VSYNC signal */ +typedef enum e_ceu_vsync_polarity +{ + CEU_VSYNC_POLARITY_HIGH = 0U, ///< VSYNC signal is active high + CEU_VSYNC_POLARITY_LOW = 1U, ///< VSYNC signal is active low +} ceu_vsync_polarity_t; + +typedef enum e_ceu_burst_transfer_mode +{ + CEU_BURST_TRANSFER_MODE_X1 = (0u), ///< Transferred to the bus in 32-byte units */ + CEU_BURST_TRANSFER_MODE_X2 = (1u), ///< Transferred to the bus in 64-byte units */ + CEU_BURST_TRANSFER_MODE_X4 = (2u), ///< Transferred to the bus in 128-byte units */ + CEU_BURST_TRANSFER_MODE_X8 = (3u) ///< Transferred to the bus in 256-byte units */ +} ceu_burst_transfer_mode_t; + +typedef enum e_ceu_event +{ + CEU_EVENT_NONE = 0x00000000, // No event, default state + CEU_EVENT_FRAME_END = 0x00000001, ///< Frame end event (CPE) + CEU_EVENT_HD = 0x00000100, ///< (Not Used) HD received (HD) + CEU_EVENT_VD = 0x00000200, ///< VD received (VD) + CEU_EVENT_CRAM_OVERFLOW = 0x00010000, ///< Data overflowed in the CRAM buffer (CDTOF) + CEU_EVENT_HD_MISMATCH = 0x00020000, ///< HD mismatch (IGHS) + CEU_EVENT_VD_MISMATCH = 0x00040000, ///< VD mismatch (IGVS) + CEU_EVENT_VD_ERROR = 0x00100000, ///< Invalid VD condition (VBP) + CEU_EVENT_FIREWALL = 0x00800000, ///< Data write address exceeds firewall (FWF) + CEU_EVENT_HD_MISSING = 0x01000000, ///< HD was expected but not input (NHD) + CEU_EVENT_VD_MISSING = 0x02000000, ///< VD was expected but not input (NVD) +} ceu_event_t; + +/** Capture mode for CEU. */ +typedef enum e_ceu_capture_format +{ + CEU_CAPTURE_FORMAT_IMAGE_CAPTURE = 0x0, ///< YCbCr data. + CEU_CAPTURE_FORMAT_DATA_SYNCHRONOUS = 0x1, ///< Raw formatted data. + CEU_CAPTURE_FORMAT_DATA_ENABLE = 0x2 ///< JPG formatted data +} ceu_capture_format_t; + +/** Set the input order of the luminance component and chrominance component (Y and CbCr). Used for image capture mode only. */ +typedef enum e_ceu_input_order +{ + CEU_INPUT_ORDER_CB0Y0CR0Y1 = 0, ///< Image input data is fetched in the order of Cb0, Y0, Cr0, Y1 + CEU_INPUT_ORDER_CR0Y0CB0Y1 = 1, ///< Image input data is fetched in the order of Cr0, Y0, Cb0, Y1 + CEU_INPUT_ORDER_Y0CB0Y1CR0 = 2, ///< Image input data is fetched in the order of Y0, Cb0, Y1, Cr0 + CEU_INPUT_ORDER_Y0CR0Y1CB0 = 3, ///< Image input data is fetched in the order of Y0, Cr0, Y1, Cb0 +} ceu_input_order_t; + +/** Format for outputting captured CEU data to memory. */ +typedef enum e_ceu_output_format +{ + CEU_OUTPUT_FORMAT_YCBCR420 = 0, ///< Output the data in YCbCr 4:2:0 format (hardware conversion from YCbCr 4:2:2) + CEU_OUTPUT_FORMAT_YCBCR422 = 1, ///< Output the data in YCbCr 4:2:2 format (no conversion) +} ceu_output_format_t; + +/** Swap bits configuration */ +typedef struct st_ceu_byte_swapping_t +{ + uint8_t swap_8bit_units : 1; ///< Byte swapping in 8-bit units + uint8_t swap_16bit_units : 1; ///< Byte swapping in 16-bit units + uint8_t swap_32bit_units : 1; ///< Byte swapping in 32-bit units +} ceu_byte_swapping_t; + +/** Edge information for latching signals */ +typedef struct st_ceu_edge_info_t +{ + uint8_t dsel : 1; ///< Sets the edge for fetching the image data (D15 to D0) from an external module. + uint8_t hdsel : 1; ///< Sets the edge for capturing hd from external module. + uint8_t vdsel : 1; ///< Sets the edge for capturing vd from external module. +} ceu_edge_info_t; + +/** Extended configuration structure for CEU. */ +typedef struct st_ceu_extended_cfg +{ + ceu_capture_format_t capture_format; ///< Capture format for incoming data + ceu_input_order_t input_order; ///< Input Y and CbCr order (Used for image capture mode) + ceu_output_format_t output_format; ///< Output format for storing to memory (Used for image capture mode) + ceu_data_bus_size_t data_bus_width; ///< Size of camera data bus + ceu_edge_info_t edge_info; + ceu_hsync_polarity_t hsync_polarity; ///< Polarity of HSYNC input + ceu_vsync_polarity_t vsync_polarity; ///< Polarity of VSYNC input + uint32_t image_area_size; ///< Image capture size. Used when setting firewall address for Data Enable Fetch mode. + ceu_byte_swapping_t byte_swapping; ///< Controls byte swapping in 8-bit, 16-bit and 32-bit units + ceu_burst_transfer_mode_t burst_mode; ///< Bus transfer data size + uint32_t scale_down_factor; ///< Scale down capture filter register setting (Used for image capture mode) + uint16_t h_output_size; ///< Output image horizontal size, in pixels (Used for image capture mode) + uint16_t v_output_size; ///< Output image vertical size, in lines (Used for image capture mode) + uint32_t interrupts_enabled; ///< Enabled interrupt events bit mask + uint8_t ceu_ipl; ///< PDC interrupt priority + IRQn_Type ceu_irq; ///< PDC IRQ number +} ceu_extended_cfg_t; + +/** CEU instance control block. DO NOT INITIALIZE. */ +typedef struct st_ceu_instance_ctrl +{ + capture_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t open; // Indicates whether or not the driver is open called. + uint8_t * p_buffer; // Pointer to buffer currently in use + uint32_t image_area_size; // Size of capture area for image (Used for Data Enable Fetch) + uint32_t interrupts_enabled; // Interrupts enabled bitmask + void (* p_callback)(capture_callback_args_t *); // Pointer to callback that is called when an ceu_event_t occurs. + capture_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void * p_context; // Pointer to context to be passed into callback function +} ceu_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const capture_api_t g_ceu_on_capture; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CEU_Open(capture_ctrl_t * const p_ctrl, capture_cfg_t const * const p_cfg); + +fsp_err_t R_CEU_Close(capture_ctrl_t * const p_ctrl); + +fsp_err_t R_CEU_CaptureStart(capture_ctrl_t * const p_ctrl, uint8_t * const p_buffer); + +fsp_err_t R_CEU_CallbackSet(capture_ctrl_t * const p_ctrl, + void ( * p_callback)(capture_callback_args_t *), + void * const p_context, + capture_callback_args_t * const p_callback_memory); + +fsp_err_t R_CEU_StatusGet(capture_ctrl_t * const p_ctrl, capture_status_t * p_status); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_CEU_H + +/*******************************************************************************************************************//** + * @} (end defgroup CEU) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cgc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cgc.h new file mode 100644 index 0000000000..bd1e8db120 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_cgc.h @@ -0,0 +1,107 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_CGC_H +#define R_CGC_H + +/*******************************************************************************************************************//** + * @addtogroup CGC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_cgc_cfg.h" +#include "r_cgc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CGC private control block. DO NOT MODIFY. Initialization occurs when R_CGC_Open() is called. */ +typedef struct st_cgc_instance_ctrl +{ + uint32_t open; + + cgc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void (* p_callback)(cgc_callback_args_t * p_args); // Pointer to callback that is called when a cgc_event_t occurs. + + /** Placeholder for user data. Passed to the user callback in ::cgc_callback_args_t. */ + void * p_context; +#if BSP_FEATURE_CGC_HAS_OSTDCSE + void const * p_extend; +#endif +} cgc_instance_ctrl_t; + +#if BSP_FEATURE_CGC_HAS_OSTDCSE + +/** CGC extend configuration */ +typedef struct s_cgc_extended_cfg_t +{ + bool ostd_enable; /// contrast -> gamma correction + GLCDC_CORRECTION_PROC_ORDER_GAMMA2BRIGHTNESS_CONTRAST ///< Gamma correction -> brightness -> contrast +} glcdc_correction_proc_order_t; + +/** Timing signals for driving the LCD panel */ +typedef enum e_glcdc_tcon_signal_select +{ + GLCDC_TCON_SIGNAL_SELECT_STVA_VS = 0, ///< STVA/VS + GLCDC_TCON_SIGNAL_SELECT_STVB_VE = 1, ///< STVB/VE + GLCDC_TCON_SIGNAL_SELECT_STHA_HS = 2, ///< STH/SP/HS + GLCDC_TCON_SIGNAL_SELECT_STHB_HE = 3, ///< STB/LP/HE + GLCDC_TCON_SIGNAL_SELECT_DE = 7 ///< DE +} glcdc_tcon_signal_select_t; + +/** Clock phase adjustment for serial RGB output */ +typedef enum e_glcdc_clut_plane +{ + GLCDC_CLUT_PLANE_0 = 0, ///< GLCDC CLUT plane 0 + GLCDC_CLUT_PLANE_1 = 1, ///< GLCDC CLUT plane 1 +} glcdc_clut_plane_t; + +/** Dithering mode */ +typedef enum e_glcdc_dithering_mode +{ + GLCDC_DITHERING_MODE_TRUNCATE = 0, ///< No dithering (truncate) + GLCDC_DITHERING_MODE_ROUND_OFF = 1, ///< Dithering with round off + GLCDC_DITHERING_MODE_2X2PATTERN = 2, ///< Dithering with 2x2 pattern + GLCDC_DITHERING_MODE_SETTING_MAX +} glcdc_dithering_mode_t; + +/** Dithering mode */ +typedef enum e_glcdc_dithering_pattern +{ + GLCDC_DITHERING_PATTERN_00 = 0, ///< 2x2 pattern '00' + GLCDC_DITHERING_PATTERN_01 = 1, ///< 2x2 pattern '01' + GLCDC_DITHERING_PATTERN_10 = 2, ///< 2x2 pattern '10' + GLCDC_DITHERING_PATTERN_11 = 3, ///< 2x2 pattern '11' +} glcdc_dithering_pattern_t; + +/** Output interface format */ +typedef enum e_glcdc_input_interface_format +{ + GLCDC_INPUT_INTERFACE_FORMAT_RGB565 = 0, ///< Input interface format RGB565 + GLCDC_INPUT_INTERFACE_FORMAT_RGB888 = 1, ///< Input interface format RGB888 + GLCDC_INPUT_INTERFACE_FORMAT_ARGB1555 = 2, ///< Input interface format ARGB1555 + GLCDC_INPUT_INTERFACE_FORMAT_ARGB4444 = 3, ///< Input interface format ARGB4444 + GLCDC_INPUT_INTERFACE_FORMAT_ARGB8888 = 4, ///< Input interface format ARGB8888 + GLCDC_INPUT_INTERFACE_FORMAT_CLUT8 = 5, ///< Input interface format CLUT8 + GLCDC_INPUT_INTERFACE_FORMAT_CLUT4 = 6, ///< Input interface format CLUT4 + GLCDC_INPUT_INTERFACE_FORMAT_CLUT1 = 7, ///< Input interface format CLUT1 +} glcdc_input_interface_format_t; + +/** Output interface format */ +typedef enum e_glcdc_output_interface_format +{ + GLCDC_OUTPUT_INTERFACE_FORMAT_RGB888 = 0, ///< Output interface format RGB888 + GLCDC_OUTPUT_INTERFACE_FORMAT_RGB666 = 1, ///< Output interface format RGB666 + GLCDC_OUTPUT_INTERFACE_FORMAT_RGB565 = 2, ///< Output interface format RGB565 + GLCDC_OUTPUT_INTERFACE_FORMAT_SERIAL_RGB = 3, ///< Output interface format Serial RGB +} glcdc_output_interface_format_t; + +/** Dithering output format */ +typedef enum e_glcdc_dithering_output_format +{ + GLCDC_DITHERING_OUTPUT_FORMAT_RGB888 = 0, ///< Dithering output format RGB888 + GLCDC_DITHERING_OUTPUT_FORMAT_RGB666 = 1, ///< Dithering output format RGB666 + GLCDC_DITHERING_OUTPUT_FORMAT_RGB565 = 2, ///< Dithering output format RGB565 +} glcdc_dithering_output_format_t; + +/** GLCDC hardware specific configuration */ +typedef struct st_glcdc_extended_cfg +{ + glcdc_tcon_pin_t tcon_hsync; ///< GLCDC TCON output pin select + glcdc_tcon_pin_t tcon_vsync; ///< GLCDC TCON output pin select + glcdc_tcon_pin_t tcon_de; ///< GLCDC TCON output pin select + glcdc_correction_proc_order_t correction_proc_order; ///< Correction control route select + glcdc_clk_src_t clksrc; ///< Clock Source selection + glcdc_panel_clk_div_t clock_div_ratio; ///< Clock divide ratio for dot clock + glcdc_dithering_mode_t dithering_mode; ///< Dithering mode + glcdc_dithering_pattern_t dithering_pattern_A; ///< Dithering pattern A + glcdc_dithering_pattern_t dithering_pattern_B; ///< Dithering pattern B + glcdc_dithering_pattern_t dithering_pattern_C; ///< Dithering pattern C + glcdc_dithering_pattern_t dithering_pattern_D; ///< Dithering pattern D + void * phy_layer; ///< Alternate PHY layer, such as MIPI DSI. +} glcdc_extended_cfg_t; + +/* GLCDC hardware specific control block */ +typedef struct st_glcdc_ctrl +{ + display_coordinate_t back_porch; ///< Zero coordinate for graphics plane(Back porch end) + uint16_t hsize; ///< Horizontal pixel size in a line + uint16_t vsize; ///< Vertical pixel size in a frame + void * p_context; ///< Pointer to the function level device context + // (e.g. display_ctrl_t type data) +} glcdc_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/* @cond INC_HEADER_DEFS_SEC */ +/* Filled in Interface API structure for this Instance. */ +extern const display_api_t g_display_on_glcdc; + +/* @endcond */ + +/********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_GLCDC_Open(display_ctrl_t * const p_api_ctrl, display_cfg_t const * const p_cfg); +fsp_err_t R_GLCDC_Close(display_ctrl_t * const p_api_ctrl); +fsp_err_t R_GLCDC_Start(display_ctrl_t * const p_api_ctrl); +fsp_err_t R_GLCDC_Stop(display_ctrl_t * const p_api_ctrl); +fsp_err_t R_GLCDC_LayerChange(display_ctrl_t const * const p_api_ctrl, + display_runtime_cfg_t const * const p_cfg, + display_frame_layer_t layer); +fsp_err_t R_GLCDC_BufferChange(display_ctrl_t const * const p_api_ctrl, + uint8_t * const framebuffer, + display_frame_layer_t layer); +fsp_err_t R_GLCDC_ColorCorrection(display_ctrl_t const * const p_api_ctrl, + display_correction_t const * const p_correction); +fsp_err_t R_GLCDC_ClutUpdate(display_ctrl_t const * const p_api_ctrl, + display_clut_cfg_t const * const p_clut_cfg, + display_frame_layer_t layer); +fsp_err_t R_GLCDC_ClutEdit(display_ctrl_t const * const p_api_ctrl, + display_frame_layer_t layer, + uint8_t index, + uint32_t color); +fsp_err_t R_GLCDC_ColorKeySet(display_ctrl_t const * const p_api_ctrl, + display_colorkeying_layer_t key_cfg, + display_frame_layer_t layer); +fsp_err_t R_GLCDC_StatusGet(display_ctrl_t const * const p_api_ctrl, display_status_t * const status); + +/*******************************************************************************************************************//** + * @} (end defgroup GLCDC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gpt.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gpt.h new file mode 100644 index 0000000000..38f0c91ed0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gpt.h @@ -0,0 +1,457 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_GPT_H +#define R_GPT_H + +/*******************************************************************************************************************//** + * @addtogroup GPT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */ +typedef enum e_gpt_io_pin +{ + GPT_IO_PIN_GTIOCA = 0, ///< GTIOCA + GPT_IO_PIN_GTIOCB = 1, ///< GTIOCB + GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2, ///< GTIOCA and GTIOCB + GPT_IO_PIN_TROUGH = 4, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. + GPT_IO_PIN_CREST = 8, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. + GPT_IO_PIN_ONE_SHOT_LEADING_EDGE = 4, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRC and GTCCRE registers when One-Shot Pulse mode is selected. + GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE = 8, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRD and GTCCRF registers when One-Shot Pulse mode is selected. +} gpt_io_pin_t; + +/** Forced buffer push operation used in One-Sot Pulse mode with R_GPT_DutyCycleSet(). */ +typedef enum e_gpt_buffer_force_push +{ + GPT_BUFFER_FORCE_PUSH = 64, ///< Used in @ref R_GPT_DutyCycleSet to force push the data from GTCCRn registers to temporary buffer A or B when One-Shot Pulse mode is selected. +} gpt_buffer_force_push; + +/** Level of GPT pin */ +typedef enum e_gpt_pin_level +{ + GPT_PIN_LEVEL_LOW = 0, ///< Pin level low + GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high +} gpt_pin_level_t; + +/** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent + * a bitmask. Multiple sources can be ORed together. */ +typedef enum e_gpt_source +{ + /** No active event sources. */ + GPT_SOURCE_NONE = 0U, + + /** Action performed on GTETRGA rising edge. **/ + GPT_SOURCE_GTETRGA_RISING = (1U << 0), + + /** Action performed on GTETRGA falling edge. **/ + GPT_SOURCE_GTETRGA_FALLING = (1U << 1), + + /** Action performed on GTETRGB rising edge. **/ + GPT_SOURCE_GTETRGB_RISING = (1U << 2), + + /** Action performed on GTETRGB falling edge. **/ + GPT_SOURCE_GTETRGB_FALLING = (1U << 3), + + /** Action performed on GTETRGC rising edge. **/ + GPT_SOURCE_GTETRGC_RISING = (1U << 4), + + /** Action performed on GTETRGC falling edge. **/ + GPT_SOURCE_GTETRGC_FALLING = (1U << 5), + + /** Action performed on GTETRGB rising edge. **/ + GPT_SOURCE_GTETRGD_RISING = (1U << 6), + + /** Action performed on GTETRGB falling edge. **/ + GPT_SOURCE_GTETRGD_FALLING = (1U << 7), + + /** Action performed when GTIOCA input rises while GTIOCB is low. **/ + GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8), + + /** Action performed when GTIOCA input rises while GTIOCB is high. **/ + GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9), + + /** Action performed when GTIOCA input falls while GTIOCB is low. **/ + GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10), + + /** Action performed when GTIOCA input falls while GTIOCB is high. **/ + GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11), + + /** Action performed when GTIOCB input rises while GTIOCA is low. **/ + GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12), + + /** Action performed when GTIOCB input rises while GTIOCA is high. **/ + GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13), + + /** Action performed when GTIOCB input falls while GTIOCA is low. **/ + GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14), + + /** Action performed when GTIOCB input falls while GTIOCA is high. **/ + GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15), + + /** Action performed on ELC GPTA event. **/ + GPT_SOURCE_GPT_A = (1U << 16), + + /** Action performed on ELC GPTB event. **/ + GPT_SOURCE_GPT_B = (1U << 17), + + /** Action performed on ELC GPTC event. **/ + GPT_SOURCE_GPT_C = (1U << 18), + + /** Action performed on ELC GPTD event. **/ + GPT_SOURCE_GPT_D = (1U << 19), + + /** Action performed on ELC GPTE event. **/ + GPT_SOURCE_GPT_E = (1U << 20), + + /** Action performed on ELC GPTF event. **/ + GPT_SOURCE_GPT_F = (1U << 21), + + /** Action performed on ELC GPTG event. **/ + GPT_SOURCE_GPT_G = (1U << 22), + + /** Action performed on ELC GPTH event. **/ + GPT_SOURCE_GPT_H = (1U << 23), +} gpt_source_t; + +/** Configurations for output pins. */ +typedef struct s_gpt_output_pin +{ + bool output_enabled; ///< Set to true to enable output, false to disable output + gpt_pin_level_t stop_level; ///< Select a stop level from ::gpt_pin_level_t +} gpt_output_pin_t; + +/** Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. */ +typedef struct s_gpt_gtior_setting +{ + union + { + uint32_t gtior; + struct + { + /* Settings for GTIOCxA pin. */ + uint32_t gtioa : 5; ///< GTIOCA Pin Function Select. + uint32_t : 1; // Reserved + uint32_t oadflt : 1; ///< GTIOCA Pin Output Value Setting at the Count Stop. + uint32_t oahld : 1; ///< GTIOCA Pin Output Setting at the Start/Stop Count. + uint32_t oae : 1; ///< GTIOCA Pin Output Enable + uint32_t oadf : 2; ///< GTIOCA Pin Disable Value Setting. + uint32_t : 2; /// Reserved + uint32_t nfaen : 1; /// Noise Filter A Enable. + uint32_t nfcsa : 2; /// Noise Filter A Sampling Clock Select. + + /* Settings for GTIOCxB pin. */ + uint32_t gtiob : 5; ///< GTIOCB Pin Function Select. + uint32_t : 1; // Reserved + uint32_t obdflt : 1; ///< GTIOCB Pin Output Value Setting at the Count Stop. + uint32_t obhld : 1; ///< GTIOCB Pin Output Setting at the Start/Stop Count. + uint32_t obe : 1; ///< GTIOCB Pin Output Enable + uint32_t obdf : 2; ///< GTIOCB Pin Disable Value Setting. + uint32_t : 2; /// Reserved + uint32_t nfben : 1; /// Noise Filter B Enable. + uint32_t nfcsb : 2; /// Noise Filter B Sampling Clock Select. + } gtior_b; + }; +} gpt_gtior_setting_t; + +/** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB. + * The noise filter samples the external signal at intervals of the PCLK divided by one of the values. + * When 3 consecutive samples are at the same level (high or low), then that level is passed on as + * the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section. + */ +typedef enum e_gpt_capture_filter +{ + GPT_CAPTURE_FILTER_NONE = 0U, ///< None - no filtering + GPT_CAPTURE_FILTER_PCLKD_DIV_1 = 1U, ///< PCLK/1 - fast sampling + GPT_CAPTURE_FILTER_PCLKD_DIV_4 = 3U, ///< PCLK/4 + GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16 + GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling +} gpt_capture_filter_t; + +/** Trigger options to start A/D conversion. */ +typedef enum e_gpt_adc_trigger +{ + GPT_ADC_TRIGGER_NONE = 0U, ///< None - no output disable request + GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match + GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match + GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match + GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match +} gpt_adc_trigger_t; + +/** POEG channel to link to this channel. */ +typedef enum e_gpt_poeg_link +{ + GPT_POEG_LINK_POEG0 = 0U, ///< Link this GPT channel to POEG channel 0 (GTETRGA) + GPT_POEG_LINK_POEG1 = 1U, ///< Link this GPT channel to POEG channel 1 (GTETRGB) + GPT_POEG_LINK_POEG2 = 2U, ///< Link this GPT channel to POEG channel 2 (GTETRGC) + GPT_POEG_LINK_POEG3 = 3U, ///< Link this GPT channel to POEG channel 3 (GTETRGD) +} gpt_poeg_link_t; + +/** Select trigger to send output disable request to POEG. */ +typedef enum e_gpt_output_disable +{ + GPT_OUTPUT_DISABLE_NONE = 0U, ///< None - no output disable request + GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR = 1U << 0, ///< Request output disable if a dead time error occurs + GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time + GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time +} gpt_output_disable_t; + +/** Disable level options for GTIOC pins. */ +typedef enum e_gpt_gtioc_disable +{ + GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable + GPT_GTIOC_DISABLE_SET_HI_Z = 1U, ///< Set GTIOC to high impedance when output is disabled + GPT_GTIOC_DISABLE_LEVEL_LOW = 2U, ///< Set GTIOC level low when output is disabled + GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled +} gpt_gtioc_disable_t; + +/** Trigger options to start A/D conversion. */ +typedef enum e_gpt_adc_compare_match +{ + GPT_ADC_COMPARE_MATCH_ADC_A = 0U, ///< Set A/D conversion start request value for GPT A/D converter start request A + GPT_ADC_COMPARE_MATCH_ADC_B = 3U, ///< Set A/D conversion start request value for GPT A/D converter start request B +} gpt_adc_compare_match_t; + +/** Interrupt skipping modes */ +typedef enum e_gpt_interrupt_skip_source +{ + GPT_INTERRUPT_SKIP_SOURCE_NONE = 0U, ///< Do not skip interrupts + GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts + + /** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in + * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest + * interrupt. */ + GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U, + + /** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in + * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough + * interrupt. */ + GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U, +} gpt_interrupt_skip_source_t; + +/** Number of interrupts to skip between events */ +typedef enum e_gpt_interrupt_skip_count +{ + GPT_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts + GPT_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt + GPT_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts + GPT_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts + GPT_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts + GPT_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts + GPT_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts + GPT_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts +} gpt_interrupt_skip_count_t; + +/** ADC events to skip during interrupt skipping */ +typedef enum e_gpt_interrupt_skip_adc +{ + GPT_INTERRUPT_SKIP_ADC_NONE = 0U, ///< Do not skip ADC events + GPT_INTERRUPT_SKIP_ADC_A = 1U, ///< Skip ADC A events + GPT_INTERRUPT_SKIP_ADC_B = 4U, ///< Skip ADC B events + GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events +} gpt_interrupt_skip_adc_t; + +/** Delay setting for the PWM Delay Generation Circuit (PDG). */ +typedef enum e_gpt_pwm_output_delay_setting +{ + GPT_PWM_OUTPUT_DELAY_SETTING_0_32, ///< Delay is not applied. + GPT_PWM_OUTPUT_DELAY_SETTING_1_32, ///< Delay of 1 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_2_32, ///< Delay of 2 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_3_32, ///< Delay of 3 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_4_32, ///< Delay of 4 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_5_32, ///< Delay of 5 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_6_32, ///< Delay of 6 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_7_32, ///< Delay of 7 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_8_32, ///< Delay of 8 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_9_32, ///< Delay of 9 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_10_32, ///< Delay of 10 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_11_32, ///< Delay of 11 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_12_32, ///< Delay of 12 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_13_32, ///< Delay of 13 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_14_32, ///< Delay of 14 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_15_32, ///< Delay of 15 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_16_32, ///< Delay of 16 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_17_32, ///< Delay of 17 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_18_32, ///< Delay of 18 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_19_32, ///< Delay of 19 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_20_32, ///< Delay of 20 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_21_32, ///< Delay of 21 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_22_32, ///< Delay of 22 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_23_32, ///< Delay of 23 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_24_32, ///< Delay of 24 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_25_32, ///< Delay of 25 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_26_32, ///< Delay of 26 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_27_32, ///< Delay of 27 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_28_32, ///< Delay of 28 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_29_32, ///< Delay of 29 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_30_32, ///< Delay of 30 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_31_32, ///< Delay of 31 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS, ///< Bypass the PWM Output Delay Circuit. +} gpt_pwm_output_delay_setting_t; + +/** Select which PWM Output Delay setting to apply. */ +typedef enum e_gpt_pwm_output_delay_edge +{ + GPT_PWM_OUTPUT_DELAY_EDGE_RISING, ///< Configure the PWM Output Delay setting for rising edge. + GPT_PWM_OUTPUT_DELAY_EDGE_FALLING, ///< Configure the PWM Output Delay setting for falling edge. +} gpt_pwm_output_delay_edge_t; + +/** Polarity inversion control for GTIOCnA/B pins. */ +typedef enum e_gpt_gtioc_polarity +{ + GPT_GTIOC_POLARITY_NORMAL = 0U, ///< GPTIOCnA/B pin polarity is not changed. + GPT_GTIOC_POLARITY_INVERTED = 1U, ///< GPTIOCnA/B pin polarity is inverted. +} gpt_gtioc_polarity_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_gpt_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations + R_GPT0_Type * p_reg; // Base register for this channel + uint32_t channel_mask; // Channel bitmask + timer_variant_t variant; // Timer variant + + void (* p_callback)(timer_callback_args_t *); // Pointer to callback + timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void * p_context; // Pointer to context to be passed into callback function +} gpt_instance_ctrl_t; + +/** GPT extension for advanced PWM features. */ +typedef struct st_gpt_extended_pwm_cfg +{ + uint8_t trough_ipl; ///< Trough interrupt priority + IRQn_Type trough_irq; ///< Trough interrupt + gpt_poeg_link_t poeg_link; ///< Select which POEG channel controls output disable for this GPT channel + gpt_output_disable_t output_disable; ///< Select which trigger sources request output disable from POEG + gpt_adc_trigger_t adc_trigger; ///< Select trigger sources to start A/D conversion + uint32_t dead_time_count_up; ///< Set a dead time value for counting up + uint32_t dead_time_count_down; ///< Set a dead time value for counting down (available on GPT32E and GPT32EH only) + uint32_t adc_a_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT_AD_TRIG_A + uint32_t adc_b_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT_AD_TRIG_B + gpt_interrupt_skip_source_t interrupt_skip_source; ///< Interrupt source to count for interrupt skipping + gpt_interrupt_skip_count_t interrupt_skip_count; ///< Number of interrupts to skip between events + gpt_interrupt_skip_adc_t interrupt_skip_adc; ///< ADC events to skip when interrupt skipping is enabled + gpt_gtioc_disable_t gtioca_disable_setting; ///< Select how to configure GTIOCA when output is disabled + gpt_gtioc_disable_t gtiocb_disable_setting; ///< Select how to configure GTIOCB when output is disabled +} gpt_extended_pwm_cfg_t; + +/** GPT extension configures the output pins for GPT. */ +typedef struct st_gpt_extended_cfg +{ + gpt_output_pin_t gtioca; ///< Configuration for GPT I/O pin A + gpt_output_pin_t gtiocb; ///< Configuration for GPT I/O pin B + gpt_source_t start_source; ///< Event sources that trigger the timer to start + gpt_source_t stop_source; ///< Event sources that trigger the timer to stop + gpt_source_t clear_source; ///< Event sources that trigger the timer to clear + gpt_source_t capture_a_source; ///< Event sources that trigger capture of GTIOCA + gpt_source_t capture_b_source; ///< Event sources that trigger capture of GTIOCB + + /** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source + * and count_down_source, then the timer count source is PCLK. */ + gpt_source_t count_up_source; + + /** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source + * and count_down_source, then the timer count source is PCLK. */ + gpt_source_t count_down_source; + + /* Debounce filter for GTIOCxA input signal pin. */ + gpt_capture_filter_t capture_filter_gtioca; + + /* Debounce filter for GTIOCxB input signal pin. */ + gpt_capture_filter_t capture_filter_gtiocb; + + uint8_t capture_a_ipl; ///< Capture/Compare match A interrupt priority + uint8_t capture_b_ipl; ///< Capture/Compare match B interrupt priority + uint8_t compare_match_c_ipl; ///< Compare match C interrupt priority + uint8_t compare_match_d_ipl; ///< Compare match D interrupt priority + uint8_t compare_match_e_ipl; ///< Compare match E interrupt priority + uint8_t compare_match_f_ipl; ///< Compare match F interrupt priority + IRQn_Type capture_a_irq; ///< Capture/Compare match A interrupt + IRQn_Type capture_b_irq; ///< Capture/Compare match B interrupt + IRQn_Type compare_match_c_irq; ///< Compare match C interrupt + IRQn_Type compare_match_d_irq; ///< Compare match D interrupt + IRQn_Type compare_match_e_irq; ///< Compare match E interrupt + IRQn_Type compare_match_f_irq; ///< Compare match F interrupt + + uint32_t compare_match_value[6]; ///< Storing compare match value for channels. + uint8_t compare_match_status; ///< Storing the compare match registers status. + + gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional + gpt_gtior_setting_t gtior_setting; ///< Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. + + gpt_gtioc_polarity_t gtioca_polarity; ///< Polarity control for GTIOCxA input/output pin. + gpt_gtioc_polarity_t gtiocb_polarity; ///< Polarity control for GTIOCxB input/output pin. +} gpt_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_gpt; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_GPT_CompareMatchSet(timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel); +fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter); +fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); +fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); +fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl, + gpt_adc_compare_match_t which_compare_match, + uint32_t compare_match_value); +fsp_err_t R_GPT_PwmOutputDelaySet(timer_ctrl_t * const p_ctrl, + gpt_pwm_output_delay_edge_t edge, + gpt_pwm_output_delay_setting_t delay_setting, + uint32_t const pin); +fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_PwmOutputDelayInitialize(void); + +/*******************************************************************************************************************//** + * @} (end defgroup GPT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gpt_three_phase.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gpt_three_phase.h new file mode 100644 index 0000000000..158552f395 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gpt_three_phase.h @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_GPT_THREE_PHASE_H +#define R_GPT_THREE_PHASE_H + +/*******************************************************************************************************************//** + * @addtogroup GPT_THREE_PHASE + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_three_phase_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref three_phase_api_t::open is called. */ +typedef struct st_gpt_three_phase_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + R_GPT0_Type * p_reg[3]; // Pointer to GPT channel registers + uint32_t channel_mask; // Bitmask of GPT channels used + three_phase_buffer_mode_t buffer_mode; // Single- or double-buffer mode + three_phase_cfg_t const * p_cfg; // Pointer to configuration struct +} gpt_three_phase_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const three_phase_api_t g_gpt_three_phase_on_gpt_three_phase; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_Open(three_phase_ctrl_t * const p_ctrl, three_phase_cfg_t const * const p_cfg); +fsp_err_t R_GPT_THREE_PHASE_Stop(three_phase_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_THREE_PHASE_Start(three_phase_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_THREE_PHASE_Reset(three_phase_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_THREE_PHASE_DutyCycleSet(three_phase_ctrl_t * const p_ctrl, + three_phase_duty_cycle_t * const p_duty_cycle); +fsp_err_t R_GPT_THREE_PHASE_CallbackSet(three_phase_ctrl_t * const p_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_GPT_THREE_PHASE_Close(three_phase_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup GPT_THREE_PHASE) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gptp.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gptp.h new file mode 100644 index 0000000000..ca13e530cf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_gptp.h @@ -0,0 +1,111 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup GPTP + * @{ + **********************************************************************************************************************/ + +#ifndef R_GPTP_H +#define R_GPTP_H + +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "r_gptp_cfg.h" +#include "r_gptp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Pulsed output configuration. */ +typedef struct st_gptp_pulsed_output_cfg +{ + uint8_t pulse_num; ///< Pulse generator number. + uint16_t start_sec_upper; ///< Pulse start second(upper 16 bit). + uint32_t start_sec_lower; ///< Pulse start second(lower 32 bit). + uint32_t start_ns; ///< Pulse start nanosecond. + uint16_t wide; ///< Pulse width. + uint16_t period_sec_upper; ///< Pulse period second(upper 16 bit). + uint32_t period_sec_lower; ///< Pulse period second(lower 32 bit). + uint32_t period_ns; ///< Pulse period nanosecond. +} gptp_pulsed_output_cfg_t; + +/** Pulse generator. */ +typedef struct st_gptp_pulse_generator +{ + gptp_pulsed_output_cfg_t * p_pulsed_output_cfg_list[BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM]; ///< List of pointer to pulsed output configuration. +} gptp_pulse_generator_t; + +/** GPTP control block. DO NOT INITIALIZE. Initialization occurs when @ref gptp_api_t::open is called. */ +typedef struct st_gptp_instance_ctrl +{ + uint32_t open; ///< Indicates whether the open() API has been successfully called. + gptp_cfg_t const * p_cfg; ///< Pointer to initial configurations. + + R_GPTP_Type * p_reg_gptp; ///< Pointer to GPTP timer register. + + void (* p_callback)(gptp_callback_args_t *); ///< Pointer to callback that is called. + gptp_callback_args_t * p_callback_memory; ///< Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + void const * p_context; ///< Pointer to context to be passed into callback function. +} gptp_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const gptp_api_t g_gptp_on_gptp; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_GPTP_Open(gptp_ctrl_t * const p_ctrl, gptp_cfg_t const * const p_cfg); + +fsp_err_t R_GPTP_Close(gptp_ctrl_t * const p_ctrl); + +fsp_err_t R_GPTP_TimerCfg(gptp_ctrl_t * const p_ctrl, uint8_t timer, gptp_timer_cfg_t const * const p_timer_cfg); + +fsp_err_t R_GPTP_Start(gptp_ctrl_t * const p_ctrl, uint8_t timer); + +fsp_err_t R_GPTP_Stop(gptp_ctrl_t * const p_ctrl, uint8_t timer); + +fsp_err_t R_GPTP_TimerValueGet(gptp_ctrl_t * const p_ctrl, uint8_t timer, gptp_timer_value_t * const p_timer_value); + +fsp_err_t R_GPTP_TimerOffsetSet(gptp_ctrl_t * const p_ctrl, uint8_t timer, int64_t offset); + +fsp_err_t R_GPTP_TimerRateSet(gptp_ctrl_t * const p_ctrl, uint8_t timer, uint32_t rate); + +fsp_err_t R_GPTP_PulseGeneratorSet(gptp_ctrl_t * const p_ctrl, uint8_t timer, gptp_pulse_generator_t * p_pulse); + +fsp_err_t R_GPTP_CallbackSet(gptp_ctrl_t * const p_ctrl, + void ( * p_callback)(gptp_callback_args_t *), + void * const p_context, + gptp_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end addtogroup GPTP) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_GPTP_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_i3c.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_i3c.h new file mode 100644 index 0000000000..8120987ef1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_i3c.h @@ -0,0 +1,283 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup I3C + * @{ + **********************************************************************************************************************/ + +#ifndef R_I3C_H +#define R_I3C_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_i3c_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** There are two different versions of the RA2E2 MCU and the error recovery procedure is different for each version. */ +#define I3C_ERROR_RECOVERY_VERSION_1 (0U) ///< Support error recovery procedure for chip version 1. +#define I3C_ERROR_RECOVERY_VERSION_2 (1U) ///< Support error recovery procedure for chip version 2. +#define I3C_ERROR_RECOVERY_VERSION_BOTH (2U) ///< Support error recovery procedure for chip version 1 and version 2. + +/** Index for selecting the device defined in the extended address table. */ +#define I3C_DEVICE_INDEX_EXTENDED_DEVICE (1U << 5U) + +/** Event Status Provided by the callback. */ +#define I3C_EVENT_STATUS_SUCCESS (0x0) ///< The transfer was completed as expected. +#define I3C_EVENT_STATUS_PARITY (0x2) ///< A parity error was detected. +#define I3C_EVENT_STATUS_FRAME (0x3) ///< A frame error was detected. +#define I3C_EVENT_STATUS_ADDRESS_HEADER (0x4) ///< An Address Header error wasdetected. +#define I3C_EVENT_STATUS_NACK (0x5) ///< The transfer was NACK'd. +#define I3C_EVENT_STATUS_OVERFLOW (0x6) ///< A Receive FIFO overflow or Transmit FIFO underflow occurred. +#define I3C_EVENT_STATUS_ABORTED_TO_MASTER (0x7) ///< In slave mode, the write transfer was ended via the 'T' bit. +#define I3C_EVENT_STATUS_ABORTED (0x8) ///< In master mode, the transfer was aborted. +#define I3C_EVENT_STATUS_NOT_SUPPORTED (0xA) ///< Operation is not supported. +#define I3C_EVENT_STATUS_IBI_NACK_DISABLED (0x20) ///< An IBI was NACK'd and the a DISEC command was sent. + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Bitrate settings that can be selected at run-time using @ref i3c_api_t::deviceSelect. */ +typedef enum e_i3c_bitrate_setting +{ + I3C_BITRATE_MODE_I2C_STDBR = 0U, ///< Use standard period setting for subsequent I2C transfers. + I3C_BITRATE_MODE_I2C_EXTBR = 1U, ///< Use extended period setting for subsequent I2C transfers. + I3C_BITRATE_MODE_I3C_SDR0_STDBR = 0U, ///< Use standard period setting for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_SDR1_EXTBR = 1U, ///< Use extended period setting for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_SDR2_STDBR_X2 = 2U, ///< Use standard period setting x 2 for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_SDR3_EXTBR_X2 = 3U, ///< Use extended period setting x 2 for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_SDR4_EXTBR_X4 = 4U, ///< Use extended period setting x 4 for subsequent I3C SDR transfers. + I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR = 6U, ///< Use standard period setting for subsequent I3C HDR-DDR transfers. +} i3c_bitrate_mode_t; + +/** Supported activity states for ENTASn Command (See ENTASn in the MIPI I3C Specification v1.0). */ +typedef enum e_i3c_activity_state +{ + I3C_ACTIVITY_STATE_ENTAS0 = 0U, ///< Activity Interval (1 microsecond). + I3C_ACTIVITY_STATE_ENTAS1 = 1U, ///< Activity Interval (100 microseconds). + I3C_ACTIVITY_STATE_ENTAS2 = 2U, ///< Activity Interval (2 milliseconds). + I3C_ACTIVITY_STATE_ENTAS3 = 3U, ///< Activity Interval (50 milliseconds). +} i3c_activity_state_t; + +/** Maximum Sustained Data Rate for non-CCC messages sent by Master Device to Slave Device (See GETMXDS in the MIPI I3C Specification v1.0). */ +typedef enum e_i3c_data_rate_setting +{ + I3C_DATA_RATE_SETTING_FSCL_MAX = 0, ///< There is no data rate limit. + I3C_DATA_RATE_SETTING_8MHZ = 1, ///< The max sustained data rate is 8 Mhz. + I3C_DATA_RATE_SETTING_6MHZ = 2, ///< The max sustained data rate is 6 Mhz. + I3C_DATA_RATE_SETTING_4MHZ = 3, ///< The max sustained data rate is 4 Mhz. + I3C_DATA_RATE_SETTING_2MHZ = 4, ///< The max sustained data rate is 2 Mhz. +} i3c_data_rate_setting_t; + +/** Clock to Data Turnaround Time (See GETMXDS in the MIPI I3C Specification v1.0). */ +typedef enum e_i3c_clock_data_turnaround +{ + I3C_CLOCK_DATA_TURNAROUND_8NS = 0, ///< Clock to turnaround time is 8 nanoseconds or less. + I3C_CLOCK_DATA_TURNAROUND_9NS = 1, ///< Clock to turnaround time is 9 nanoseconds or less. + I3C_CLOCK_DATA_TURNAROUND_10NS = 2, ///< Clock to turnaround time is 10 nanoseconds or less. + I3C_CLOCK_DATA_TURNAROUND_11NS = 3, ///< Clock to turnaround time is 11 nanoseconds or less. + I3C_CLOCK_DATA_TURNAROUND_12NS = 4, ///< Clock to turnaround time is 12 nanoseconds or less. + I3C_CLOCK_DATA_TURNAROUND_EXTENDED = 7, ///< Clock to turnaround time is greater than 12 nanoseconds. +} i3c_clock_data_turnaround_t; + +/** Clock stalling settings. */ +typedef struct s_i3c_clock_stalling +{ + uint32_t assigned_address_phase_enable : 1; ///< Enable Clock Stalling during the address phase of the ENTDAA command. + uint32_t transition_phase_enable : 1; ///< Enable Clock Stalling during the transition bit in read transfers. + uint32_t parity_phase_enable : 1; ///< Enable Clock Stalling during the parity bit period in write transfers. + uint32_t ack_phase_enable : 1; ///< Enable Clock Stalling during the ACK/NACK phase. + uint16_t clock_stalling_time; ///< The amount of time to stall the clock in I3C source clock ticks. +} i3c_clock_stalling_t; + +/** Bitrate settings for configuring the SCL clock frequency. */ +typedef struct s_i3c_bitrate_settings +{ + uint32_t stdbr; ///< The standard bitrate settings. + uint32_t extbr; ///< The extended bitrate settings. + + /** Clock Stalling settings (See Master Clock Stalling in the MIPI I3C Specification v1.0). */ + i3c_clock_stalling_t clock_stalling; +} i3c_bitrate_settings_t; + +/** Settings for controlling the drivers behavior in response to IBIs. */ +typedef struct s_i3c_ibi_control +{ + uint32_t hot_join_acknowledge : 1; ///< If false, NACK all Hot Join requests. + uint32_t notify_rejected_hot_join_requests : 1; ///< Notify the application when an IBI Hot-Join request has been NACK'd. + uint32_t notify_rejected_mastership_requests : 1; ///< Notify the application when an IBI Mastership request has been NACK'd. + uint32_t notify_rejected_interrupt_requests : 1; ///< Notify the application when an IBI Interrupt request has been NACK'd. +} i3c_ibi_control_t; + +/** Default configuration settings for the slave response to Direct Get Common Command Codes. */ +typedef struct s_slave_command_response_info +{ + /** Slave Event Settings (See ENEC and DISEC in the MIPI I3C Specification v1.0). */ + bool inband_interrupt_enable; ///< Enable IBI interrupts. + bool mastership_request_enable; ///< Enable Mastership requests. + bool hotjoin_request_enable; ///< Enable Hot-Join requests. + + /** Starting Activity State (See ENTASn in the MIPI I3C Specification v1.0). */ + i3c_activity_state_t activity_state; + + /** Max Write Length (See SETMWL and GETMWL in the MIPI I3C Specification v1.0). */ + uint16_t write_length; + + /** Max Read Length (See SETMRL and GETMRL in the MIPI I3C Specification v1.0). */ + uint16_t read_length; + + /** Number of bytes that will be written by an IBI (See SETMRL and GETMRL in the MIPI I3C Specification v1.0). */ + uint8_t ibi_payload_length; + + /** Max Data Rate Settings (See GETMXDS in the MIPI I3C Specification v1.0). */ + i3c_data_rate_setting_t write_data_rate; ///< Max Write Data Rate. + i3c_data_rate_setting_t read_data_rate; ///< Max Read Data Rate. + i3c_clock_data_turnaround_t clock_data_turnaround; ///< Max Data Speed Turnaround. + bool read_turnaround_time_enable; ///< Enable transmission of the of the Max Read Max Read Turnaround Time. + uint32_t read_turnaround_time; ///< Max Read Turnaround Time. + + /** This byte represents the Slave’s internal oscillator frequency in increments of 0.5 MHz (500kHz), up to 127.5 MHz. + * (See GETXTIME in the MIPI I3C Specification v1.1). */ + uint8_t oscillator_frequency; + + /** Oscillator inaccuracy in 0.5% increments of 0% up to 25.5% (See GETXTIME in the MIPI I3C Specification v1.1). */ + uint8_t oscillator_inaccuracy; + + bool hdr_ddr_support; ///< HDR-DDR mode is supported. + bool hdr_tsp_support; ///< HDR-TSP mode is supported. + bool hdr_tsl_support; ///< HDR-TSL mode is supported. +} i3c_slave_command_response_info_t; + +/* Buffer descriptor for keeping track of a read transfer. */ +typedef struct s_i3c_read_buffer_descriptor +{ + uint8_t * p_buffer; ///< Pointer to a buffer for storing data that has been read. + uint32_t count; ///< Number of bytes that have been read. + uint32_t buffer_size; ///< Total size of the buffer. + + /** Flag for keeping track of whether the @ref I3C_EVENT_READ_BUFFER_FULL callback has been issued. */ + bool read_request_issued; +} i3c_read_buffer_descriptor_t; + +/* Buffer descriptor for keeping track of a write transfer. */ +typedef struct s_i3c_write_buffer_descriptor +{ + uint8_t * p_buffer; ///< Pointer to a buffer that will be read during a write transfer. + uint32_t count; ///< Number of bytes that have been written. + uint32_t buffer_size; ///< Total size of the buffer. +} i3c_write_buffer_descriptor_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref i3c_api_t::open is called. */ +typedef struct st_i3c_instance_ctrl +{ + uint32_t open; ///< Indicates whether the open() API has been successfully called. + R_I3C0_Type * p_reg; ///< Base register for this channel + volatile uint32_t internal_state; ///< Used to track the current state of the driver. + uint8_t current_command_code; ///< The current Common Command Code that is being transferred. + uint32_t device_index; ///< The device index selected using @ref i3c_api_t::deviceSelect. + i3c_bitrate_mode_t device_bitrate_mode; ///< Runtime bitrate settings to use for the next transfer. + i3c_slave_info_t current_slave_info BSP_ALIGN_VARIABLE(4); ///< The last @ref i3c_slave_info_t read during ENTDAA. + + uint32_t next_word; ///< The next word that will be written to the FIFO. + uint32_t ibi_next_word; ///< The next word that will be written to the IBI FIFO. + i3c_write_buffer_descriptor_t write_buffer_descriptor; ///< Buffer descriptor for keeping track of a write transfer. + i3c_read_buffer_descriptor_t read_buffer_descriptor; ///< Buffer descriptor for keeping track of a read transfer. + i3c_read_buffer_descriptor_t ibi_buffer_descriptor; ///< Buffer descriptor for keeping track of an IBI read/write transfer. + volatile uint32_t read_transfer_count_final; ///< The total number of bytes read during a read transfer. + volatile uint32_t ibi_transfer_count_final; ///< The total number of bytes read during an IBI transfer. + i3c_cfg_t const * p_cfg; ///< A pointer to the configuration structure provided during open. +} i3c_instance_ctrl_t; + +/** Extended configuration for r_i3c. */ +typedef struct s_i3c_extended_cfg +{ + i3c_bitrate_settings_t bitrate_settings; ///< Bitrate settings configuring the frequency and duty cycle for SCL. + i3c_ibi_control_t ibi_control; ///< Configure the driver's behavior in response to IBIs. + + /** + * The time in I3C reference clock ticks needed in order to detect the bus free condition + * (See "Bus Free Condition" in the MIPI I3C Specification v1.0). + */ + uint32_t bus_free_detection_time; + + /** + * The time in I3C reference clock ticks needed in order to detect the bus available condition + * (See "Bus Available Condition" in the MIPI I3C Specification v1.0). + */ + uint32_t bus_available_detection_time; + + /** + * The time in I3C reference clock ticks needed in order to detect the bus idle condition + * (See "Bus Idle Condition" in the MIPI I3C Specification v1.0). + */ + uint32_t bus_idle_detection_time; + + bool timeout_detection_enable; ///< Notify the application if SCL is stuck high or low. + + /** Initial settings for configuring the slave's responses to received commands. */ + i3c_slave_command_response_info_t slave_command_response_info; + + IRQn_Type resp_irq; ///< Response Queue Full IRQ number. + IRQn_Type rx_irq; ///< Receive FIFO Full IRQ number. + IRQn_Type tx_irq; ///< Transmit FIFO Empty IRQ number. + IRQn_Type rcv_irq; ///< Receive Status Queue Full IRQ number. + IRQn_Type ibi_irq; ///< IBI IRQ number. + IRQn_Type eei_irq; ///< EEI IRQ number. + uint8_t ipl; ///< Interrupt Priority for Resp, Rx, Tx, and RCV IRQs. + uint8_t eei_ipl; ///< Error and Event Interrupt Priority. +} i3c_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const i3c_api_t g_i3c_on_i3c; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_I3C_Open(i3c_ctrl_t * const p_api_ctrl, i3c_cfg_t const * const p_cfg); +fsp_err_t R_I3C_Enable(i3c_ctrl_t * const p_api_ctrl); +fsp_err_t R_I3C_DeviceCfgSet(i3c_ctrl_t * const p_api_ctrl, i3c_device_cfg_t const * const p_device_cfg); +fsp_err_t R_I3C_MasterDeviceTableSet(i3c_ctrl_t * const p_api_ctrl, + uint32_t device_index, + i3c_device_table_cfg_t const * const p_device_table_cfg); +fsp_err_t R_I3C_SlaveStatusSet(i3c_ctrl_t * const p_api_ctrl, i3c_device_status_t status); +fsp_err_t R_I3C_DeviceSelect(i3c_ctrl_t * const p_api_ctrl, uint32_t device_index, uint32_t bitrate_mode); +fsp_err_t R_I3C_DynamicAddressAssignmentStart(i3c_ctrl_t * const p_api_ctrl, + i3c_address_assignment_mode_t address_assignment_mode, + uint32_t starting_device_index, + uint32_t device_count); +fsp_err_t R_I3C_CommandSend(i3c_ctrl_t * const p_api_ctrl, i3c_command_descriptor_t const * const p_command_descriptor); +fsp_err_t R_I3C_Write(i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_data, uint32_t length, bool restart); +fsp_err_t R_I3C_Read(i3c_ctrl_t * const p_api_ctrl, uint8_t * const p_data, uint32_t length, bool restart); +fsp_err_t R_I3C_IbiWrite(i3c_ctrl_t * const p_api_ctrl, + i3c_ibi_type_t ibi_type, + uint8_t const * const p_data, + uint32_t length); +fsp_err_t R_I3C_IbiRead(i3c_ctrl_t * const p_api_ctrl, uint8_t * const p_data, uint32_t length); +fsp_err_t R_I3C_Close(i3c_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup I3C) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_icu.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_icu.h new file mode 100644 index 0000000000..1b265bed32 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_icu.h @@ -0,0 +1,94 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup ICU + * @{ + **********************************************************************************************************************/ + +#ifndef R_ICU_H +#define R_ICU_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_external_irq_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** External IRQ input pin digital filtering clock selection. */ +typedef enum e_external_irq_digital_filter +{ + EXTERNAL_IRQ_DIGITAL_FILTER_PCLK_DIV = 0, ///< Digital filter using clock PCLK dividers. + EXTERNAL_IRQ_DIGITAL_FILTER_LOCO = 1, ///< Digital filter using clock LOCO. +} e_external_irq_digital_filter_t; + +/** Extended ICU interface configuration */ +typedef struct st_icu_extended_cfg +{ + e_external_irq_digital_filter_t filter_src; ///< Select digital filter clock source when digital filter is enabled. +} icu_extended_cfg_t; + +/** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */ +typedef struct st_icu_instance_ctrl +{ + uint32_t open; ///< Used to determine if channel control block is in use + IRQn_Type irq; ///< NVIC interrupt number + uint8_t channel; ///< Channel + +#if BSP_TZ_SECURE_BUILD + external_irq_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +#endif + void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin. + + /** Placeholder for user data. Passed to the user callback in ::external_irq_callback_args_t. */ + void * p_context; +} icu_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const external_irq_api_t g_external_irq_on_icu; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg); + +fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl); + +fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl); + +fsp_err_t R_ICU_ExternalIrqCallbackSet(external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)(external_irq_callback_args_t *), + void * const p_context, + external_irq_callback_args_t * const p_callback_memory); + +fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup ICU) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_ICU_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_b_master.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_b_master.h new file mode 100644 index 0000000000..b2904beb98 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_b_master.h @@ -0,0 +1,146 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup IIC_B_MASTER + * @{ + **********************************************************************************************************************/ + +#ifndef R_IIC_B_MASTER_H +#define R_IIC_B_MASTER_H + +#include "bsp_api.h" +#include "r_iic_b_master_cfg.h" +#include "r_i2c_master_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** I2C Timeout mode parameter definition */ +typedef enum e_iic_b_master_timeout_mode +{ + IIC_B_MASTER_TIMEOUT_MODE_LONG = 0, ///< Timeout Detection Time Select: Long Mode -> TMOS = 0 + IIC_B_MASTER_TIMEOUT_MODE_SHORT = 1 ///< Timeout Detection Time Select: Short Mode -> TMOS = 1 +} iic_b_master_timeout_mode_t; + +typedef enum e_iic_b_master_timeout_scl_low +{ + IIC_B_MASTER_TIMEOUT_SCL_LOW_DISABLED = 0, ///< Timeout detection during SCL low disabled + IIC_B_MASTER_TIMEOUT_SCL_LOW_ENABLED = 1 ///< Timeout detection during SCL low enabled +} iic_b_master_timeout_scl_low_t; + +/** I2C clock settings */ +typedef struct iic_b_master_clock_settings +{ + uint8_t cks_value; ///< Internal Reference Clock Select + uint8_t brh_value; ///< High-level period of SCL clock + uint8_t brl_value; ///< Low-level period of SCL clock + uint8_t sdod_value; // < SDA Output Delay Counter + bool sdodcs_value; // < SDA Output Delay Clock Source +} iic_b_master_clock_settings_t; + +/** I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_iic_b_master_instance_ctrl +{ + i2c_master_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t slave; // The address of the slave device + i2c_master_addr_mode_t addr_mode; // Indicates how slave fields should be interpreted + + uint32_t open; // Flag to determine if the device is open + R_I3C0_Type * p_reg; // Base register for this channel + + /* Current transfer information. */ + uint8_t * p_buff; // Holds the data associated with the transfer + uint32_t total; // Holds the total number of data bytes to transfer + uint32_t remain; // Tracks the remaining data bytes to transfer + uint32_t loaded; // Tracks the number of data bytes written to the register + + uint8_t addr_low; // Holds the last address byte to issue + uint8_t addr_high; // Holds the first address byte to issue in 10-bit mode + uint8_t addr_total; // Holds the total number of address bytes to transfer + uint8_t addr_remain; // Tracks the remaining address bytes to transfer + uint8_t addr_loaded; // Tracks the number of address bytes written to the register + + volatile bool read; // Holds the direction of the data byte transfer + volatile bool restart; // Holds whether or not the restart should be issued when done + volatile bool err; // Tracks whether or not an error occurred during processing + volatile bool restarted; // Tracks whether or not a restart was issued during the previous transfer + volatile bool dummy_read_completed; // Tracks whether the dummy read is performed + volatile bool activation_on_rxi; // Tracks whether the transfer is activated on RXI interrupt + volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt + volatile bool address_restarted; // Tracks whether the restart condition is send on 10 bit read + + uint8_t sdod_value; // SDOD value when using SMBus + bool sdodcs_value; // SDODCS value when using SMBus + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + i2c_master_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} iic_b_master_instance_ctrl_t; + +/** R_IIC_B extended configuration */ +typedef struct st_iic_b_master_extended_cfg +{ + iic_b_master_timeout_mode_t timeout_mode; ///< Timeout Detection Time Select: Long Mode = 0 and Short Mode = 1. + iic_b_master_timeout_scl_low_t timeout_scl_low; ///< Allows timeouts to occur when SCL is held low. + iic_b_master_clock_settings_t clock_settings; ///< I2C Clock settings + uint32_t iic_clock_freq; ///< I2C Clock frequency in Hz + bool smbus_operation; ///< SMBus operation on I2C bus +} iic_b_master_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_master_api_t const g_i2c_master_on_iic_b; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_Open(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg); + +fsp_err_t R_IIC_B_MASTER_Read(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart); +fsp_err_t R_IIC_B_MASTER_Write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart); +fsp_err_t R_IIC_B_MASTER_Abort(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_IIC_B_MASTER_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); +fsp_err_t R_IIC_B_MASTER_Close(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_IIC_B_MASTER_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory); +fsp_err_t R_IIC_B_MASTER_StatusGet(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IIC_B_MASTER_H + +/*******************************************************************************************************************//** + * @} (end defgroup IIC_B_MASTER) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_master.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_master.h new file mode 100644 index 0000000000..065f5f1823 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_master.h @@ -0,0 +1,142 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup IIC_MASTER + * @{ + **********************************************************************************************************************/ + +#ifndef R_IIC_MASTER_H +#define R_IIC_MASTER_H + +#include "bsp_api.h" +#include "r_iic_master_cfg.h" +#include "r_i2c_master_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** I2C Timeout mode parameter definition */ +typedef enum e_iic_master_timeout_mode +{ + IIC_MASTER_TIMEOUT_MODE_LONG = 0, ///< Timeout Detection Time Select: Long Mode -> TMOS = 0 + IIC_MASTER_TIMEOUT_MODE_SHORT = 1 ///< Timeout Detection Time Select: Short Mode -> TMOS = 1 +} iic_master_timeout_mode_t; + +typedef enum e_iic_master_timeout_scl_low +{ + IIC_MASTER_TIMEOUT_SCL_LOW_DISABLED = 0, ///< Timeout detection during SCL low disabled + IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED = 1 ///< Timeout detection during SCL low enabled +} iic_master_timeout_scl_low_t; + +/** I2C clock settings */ +typedef struct iic_master_clock_settings +{ + uint8_t cks_value; ///< Internal Reference Clock Select + uint8_t brh_value; ///< High-level period of SCL clock + uint8_t brl_value; ///< Low-level period of SCL clock + uint8_t sddl_value; // < SDA Output Delay Counter + bool dlcs_value; // < SDA Output Delay Clock Source +} iic_master_clock_settings_t; + +/** I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_iic_master_instance_ctrl +{ + i2c_master_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t slave; // The address of the slave device + i2c_master_addr_mode_t addr_mode; // Indicates how slave fields should be interpreted + + uint32_t open; // Flag to determine if the device is open + R_IIC0_Type * p_reg; // Base register for this channel + + /* Current transfer information. */ + uint8_t * p_buff; // Holds the data associated with the transfer + uint32_t total; // Holds the total number of data bytes to transfer + uint32_t remain; // Tracks the remaining data bytes to transfer + uint32_t loaded; // Tracks the number of data bytes written to the register + + uint8_t addr_low; // Holds the last address byte to issue + uint8_t addr_high; // Holds the first address byte to issue in 10-bit mode + uint8_t addr_total; // Holds the total number of address bytes to transfer + uint8_t addr_remain; // Tracks the remaining address bytes to transfer + uint8_t addr_loaded; // Tracks the number of address bytes written to the register + + volatile bool read; // Holds the direction of the data byte transfer + volatile bool restart; // Holds whether or not the restart should be issued when done + volatile bool err; // Tracks whether or not an error occurred during processing + volatile bool restarted; // Tracks whether or not a restart was issued during the previous transfer + volatile bool dummy_read_completed; // Tracks whether the dummy read is performed + volatile bool activation_on_rxi; // Tracks whether the transfer is activated on RXI interrupt + volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt + volatile bool address_restarted; // Tracks whether the restart condition is send on 10 bit read + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + i2c_master_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} iic_master_instance_ctrl_t; + +/** R_IIC extended configuration */ +typedef struct st_iic_master_extended_cfg +{ + iic_master_timeout_mode_t timeout_mode; ///< Timeout Detection Time Select: Long Mode = 0 and Short Mode = 1. + iic_master_timeout_scl_low_t timeout_scl_low; ///< Allows timeouts to occur when SCL is held low. + iic_master_clock_settings_t clock_settings; ///< I2C Clock settings + bool smbus_operation; ///< SMBus operation on I2C bus +} iic_master_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_master_api_t const g_i2c_master_on_iic; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_Open(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg); + +fsp_err_t R_IIC_MASTER_Read(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart); +fsp_err_t R_IIC_MASTER_Write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart); +fsp_err_t R_IIC_MASTER_Abort(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_IIC_MASTER_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); +fsp_err_t R_IIC_MASTER_Close(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_IIC_MASTER_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory); +fsp_err_t R_IIC_MASTER_StatusGet(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IIC_MASTER_H + +/*******************************************************************************************************************//** + * @} (end defgroup IIC_MASTER) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_slave.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_slave.h new file mode 100644 index 0000000000..ed0a13fd2d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iic_slave.h @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup IIC_SLAVE + * @{ + **********************************************************************************************************************/ + +#ifndef R_IIC_SLAVE_H +#define R_IIC_SLAVE_H + +#include "bsp_api.h" +#include "r_iic_slave_cfg.h" +#include "r_i2c_slave_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* IIC Slave transaction enumeration */ +typedef enum e_iic_slave_transfer_dir_option +{ + IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE = 0x0, + IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ = 0x1, + IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED = 0x2 +} iic_slave_transfer_dir_t; + +/** I2C clock settings */ +typedef struct iic_slave_clock_settings +{ + uint8_t cks_value; ///< Internal Reference Clock Select + uint8_t brl_value; ///< Low-level period of SCL clock + uint8_t digital_filter_stages; ///< Number of digital filter stages based on brl_value +} iic_slave_clock_settings_t; + +/* I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_iic_slave_instance_ctrl +{ + i2c_slave_cfg_t const * p_cfg; // Information describing I2C device + uint32_t open; // Flag to determine if the device is open + R_IIC0_Type * p_reg; // Base register for this channel + + /* Current transfer information. */ + uint8_t * p_buff; // Holds the data associated with the transfer + uint32_t total; // Holds the total number of data bytes to transfer + uint32_t remain; // Tracks the remaining data bytes to transfer + uint32_t loaded; // Tracks the number of data bytes written to the register + uint32_t transaction_count; // Tracks the actual number of transactions + volatile bool notify_request; // Track whether the master request is notified to the application + volatile iic_slave_transfer_dir_t direction; // Holds the direction of the data byte transfer + volatile bool do_dummy_read; // Tracks whether a dummy read is issued on the first RX +#if (IIC_SLAVE_CFG_DTC_ENABLE) + volatile bool activation_on_rxi; // Tracks whether the transfer is activated on RXI interrupt + volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt +#endif + volatile bool start_interrupt_enabled; // Tracks whether the start interrupt is enabled + volatile bool transaction_completed; // Tracks whether previous transaction restarted + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_slave_callback_args_t *); + i2c_slave_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} iic_slave_instance_ctrl_t; + +/** R_IIC_SLAVE extended configuration */ +typedef struct st_iic_slave_extended_cfg +{ + iic_slave_clock_settings_t clock_settings; ///< I2C Clock settings +} iic_slave_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + ***********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_slave_api_t const g_i2c_slave_on_iic; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_IIC_SLAVE_Open(i2c_slave_ctrl_t * const p_api_ctrl, i2c_slave_cfg_t const * const p_cfg); +fsp_err_t R_IIC_SLAVE_Read(i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_IIC_SLAVE_Write(i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const p_src, uint32_t const bytes); +fsp_err_t R_IIC_SLAVE_Close(i2c_slave_ctrl_t * const p_api_ctrl); +fsp_err_t R_IIC_SLAVE_CallbackSet(i2c_slave_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_slave_callback_args_t *), + void * const p_context, + i2c_slave_callback_args_t * const p_callback_memory); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IIC_SLAVE_H + +/*******************************************************************************************************************//** + * @} (end defgroup IIC_SLAVE) + ***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iirfa.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iirfa.h new file mode 100644 index 0000000000..84276275e4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iirfa.h @@ -0,0 +1,102 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_IIRFA_H +#define R_IIRFA_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_iirfa_cfg.h" +#include "r_iir_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup IIRFA + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IIRFA instance control block. */ +typedef struct st_iirfa_instance_ctrl +{ + uint32_t open; + uint32_t filter_stages; + uint8_t channel; + uint8_t stage_base; + uint8_t stage_num; +} iirfa_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const iir_api_t g_iir_on_iirfa; + +/** @endcond */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Perform a single inline filter operation. + * + * @note This function is intended to be used in performance-critical applications. As such, no parameter checking or + * error validation is provided. + **********************************************************************************************************************/ +__STATIC_INLINE float R_IIRFA_SingleFilter (iir_ctrl_t * const p_api_ctrl, float data_in) +{ + iirfa_instance_ctrl_t * p_ctrl = (iirfa_instance_ctrl_t *) p_api_ctrl; + + /* Write input data */ + *(volatile float *) &R_IIRFA->IIRCH[p_ctrl->channel].INP = data_in; + +#if IIRFA_CFG_LOOP_USE_POLLING + volatile uint8_t * const p_reg_status = (volatile uint8_t *) &R_IIRFA->IIRCH[p_ctrl->channel].STS; + while (!(*p_reg_status & R_IIRFA_IIRCH_STS_ORDYF_Msk)) + { + /* Wait for IIRFA output data preparation */ + } +#endif + + /* Return output data */ + return *(volatile float *) &R_IIRFA->IIRCH[p_ctrl->channel].OUT; +} + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_IIRFA_Open(iir_ctrl_t * const p_api_ctrl, iir_cfg_t const * const p_cfg); +fsp_err_t R_IIRFA_Configure(iir_ctrl_t * const p_api_ctrl, iir_filter_cfg_t const * const p_filter_cfg); +fsp_err_t R_IIRFA_Filter(iir_ctrl_t * const p_api_ctrl, + float const * p_data_in, + float * p_data_out, + uint16_t const num_samples); +fsp_err_t R_IIRFA_StatusGet(iir_ctrl_t * const p_api_ctrl, iir_status_t * const p_status); +fsp_err_t R_IIRFA_Close(iir_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup IIRFA) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IIRFA_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ioport.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ioport.h new file mode 100644 index 0000000000..05a35c81cf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ioport.h @@ -0,0 +1,543 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_H +#define R_IOPORT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_ioport_api.h" +#if __has_include("r_ioport_cfg.h") + #include "r_ioport_cfg.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define IOPORT_PRV_PFS_PSEL_OFFSET (24) +#define IOPORT_PRV_CCD_PIN_COUNT (8) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ +typedef struct st_ioport_instance_ctrl +{ + uint32_t open; + void * p_context; +} ioport_instance_ctrl_t; + +/* This typedef is here temporarily. See SWFLEX-144 for details. */ +/** Superset list of all possible IO port pins. */ +typedef enum e_ioport_port_pin_t +{ + IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 + IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 + IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 + IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 + IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 + IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 + IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 + IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 + IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 + IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 + IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 + IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 + IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 + IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 + + IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 + IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 + IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 + IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 + IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 + IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 + IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 + IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 + IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 + IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 + IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 + IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 + IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 + IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 + + IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 + IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 + IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 + IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 + IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 + IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 + IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 + IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 + IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 + IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 + IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 + IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 + IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 + IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 + + IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 + IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 + IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 + IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 + IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 + IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 + IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 + IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 + IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 + IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 + IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 + IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 + IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 + IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 + + IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 + IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 + IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 + IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 + IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 + IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 + IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 + IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 + IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 + IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 + IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 + IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 + IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 + IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 + + IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 + IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 + IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 + IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 + IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 + IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 + IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 + IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 + IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 + IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 + IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 + IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 + IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 + + IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 + IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 + IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 + IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 + IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 + IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 + IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 + IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 + IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 + IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 + IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 + IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 + IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 + IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 + + IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 + IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 + IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 + IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 + IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 + IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 + IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 + IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 + IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 + IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 + IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 + IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 + IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 + + IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 + IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 + IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 + IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 + IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 + IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 + IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 + IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 + IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 + IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 + IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 + IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 + IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 + + IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 + IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 + IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 + IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 + IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 + IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 + IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 + IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 + IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 + IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 + IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 + IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 + IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 + IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 + + IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 + IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 + IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 + IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 + IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 + IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 + IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 + IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 + IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 + IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 + IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 + IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 + IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 + IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 + + IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 + IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 + IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 + IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 + IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 + IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 + IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 + IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 + IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 + IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 + IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 + IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 + IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 + IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 + + IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 + IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 + IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 + IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 + IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 + IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 + IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 + IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 + IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 + IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 + IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 + IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 + IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 + IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 + IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 + IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 + + IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 + IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 + IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 + IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 + IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 + IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 + IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 + IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 + IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 + IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 + IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 + IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 + IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 + IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 + IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 + IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 + + IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 + IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 + IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 + IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 + IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 + IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 + IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 + IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 + IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 + IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 + IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 + IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 + IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 + IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 + IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 + IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 +} ioport_port_pin_t; + +#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_peripheral +{ + /** Pin will functions as an IO pin */ + IOPORT_PERIPHERAL_IO = 0x00, + + /** Pin will function as a DEBUG pin */ + IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a SPI peripheral pin */ + IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a IIC peripheral pin */ + IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a KEY peripheral pin */ + IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a clock/comparator/RTC peripheral pin */ + IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC/ADC peripheral pin */ + IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a BUS peripheral pin */ + IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CTSU peripheral pin */ + IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CMPHS peripheral pin */ + IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a segment LCD peripheral pin */ + IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + #else + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + #endif + + /** Pin will function as a DALI peripheral pin */ + IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEU peripheral pin */ + IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAN peripheral pin */ + IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a QSPI peripheral pin */ + IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SSI peripheral pin */ + IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB full speed peripheral pin */ + IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB high speed peripheral pin */ + IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SD/MMC peripheral pin */ + IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet MMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT5 = (0x1BUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet RMMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PDC peripheral pin */ + IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a graphics LCD peripheral pin */ + IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC peripheral pin */ + IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a debug trace peripheral pin */ + IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a OSPI peripheral pin */ + IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEC peripheral pin */ + IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a ULPT peripheral pin */ + IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a MIPI DSI peripheral pin */ + IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an UARTA peripheral pin */ + IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), +} ioport_peripheral_t; +#endif + +#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T + +/** Options to configure pin functions */ +typedef enum e_ioport_cfg_options +{ + IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) + IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output + IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low + IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high + IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up + IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode + IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output + IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain output + IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium + IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed + IOPORT_CFG_DRIVE_MID_IIC = 0x00000800, ///< Sets pin to drive output needed for IIC on a 20mA port + IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high + IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge + IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge + IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges + IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin + IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin + IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin +} ioport_cfg_options_t; +#endif + +/** Output current settings for CCD pins */ +typedef enum e_ioport_output_current_t +{ + IOPORT_OUTPUT_CURRENT_HI_Z = 0, ///< High-impedance state + IOPORT_OUTPUT_CURRENT_2_MA = 1, ///< 2 mA output current + IOPORT_OUTPUT_CURRENT_5_MA = 2, ///< 5 mA output current + IOPORT_OUTPUT_CURRENT_10_MA = 3, ///< 10 mA output current + IOPORT_OUTPUT_CURRENT_15_MA = 4, ///< 15 mA output current + IOPORT_OUTPUT_CURRENT_DISABLE = -1, ///< Disables output current control +} ioport_output_current_t; + +/** R_IOPORT extended configuration */ +typedef struct st_ioport_extended_cfg +{ + ioport_output_current_t const ccd_pin_cfg_data[IOPORT_PRV_CCD_PIN_COUNT]; ///< Low-level output current for the CCD pins +} ioport_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ioport_api_t g_ioport_on_ioport; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); +fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); +fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); +fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); +fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); +fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); +fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask); +fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); +fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value); +fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); +fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IOPORT_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ipc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ipc.h new file mode 100644 index 0000000000..64cdc7cb3a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ipc.h @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_IPC_H +#define R_IPC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ipc_cfg.h" +#include "r_ipc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup IPC + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* IPC Instance Control Block. DO NOT INITIALIZE. */ +typedef struct st_ipc_instance_ctrl +{ + uint32_t open; // Used to determine if the channel is configured + ipc_cfg_t const * p_cfg; // Pointer to the configuration block + R_IPC_IPC_CH_Type * p_send_reg; // Base register for sending + R_IPC_IPC_CH_Type * p_recv_reg; // Base register for receiving + void (* p_callback)(ipc_callback_args_t *); // Pointer to callback + ipc_callback_args_t * p_callback_memory; // Pointer to optional working memory + void * p_context; // Pointer to context to be passed into callback function +} ipc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Interface Structure for user access */ +extern const ipc_api_t g_ipc_on_ipc; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_IPC_Open(ipc_ctrl_t * const p_api_ctrl, ipc_cfg_t const * const p_cfg); +fsp_err_t R_IPC_MessageSend(ipc_ctrl_t * const p_api_ctrl, uint32_t message); +fsp_err_t R_IPC_EventGenerate(ipc_ctrl_t * const p_api_ctrl, ipc_generate_event_t event); +fsp_err_t R_IPC_CallbackSet(ipc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(ipc_callback_args_t *), + void * const p_context, + ipc_callback_args_t * const p_callback_memory); +fsp_err_t R_IPC_Close(ipc_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end addtogroup IPC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iwdt.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iwdt.h new file mode 100644 index 0000000000..ea0cc17f29 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_iwdt.h @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup IWDT + * @{ + **********************************************************************************************************************/ + +#ifndef R_IWDT_H +#define R_IWDT_H + +#include "bsp_api.h" + +#include "r_iwdt_cfg.h" +#include "r_wdt_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IWDT control block. DO NOT INITIALIZE. Initialization occurs when @ref wdt_api_t::open is called. */ +typedef struct st_iwdt_instance_ctrl +{ + uint32_t wdt_open; ///< Indicates whether the open() API has been successfully called. + void * p_context; ///< Placeholder for user data. Passed to the user callback in wdt_callback_args_t. + + void (* p_callback)(wdt_callback_args_t * p_args); ///< Callback provided when a WDT NMI ISR occurs. + wdt_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +} iwdt_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const wdt_api_t g_wdt_on_iwdt; + +/** @endcond */ +fsp_err_t R_IWDT_Refresh(wdt_ctrl_t * const p_api_ctrl); + +fsp_err_t R_IWDT_Open(wdt_ctrl_t * const p_api_ctrl, wdt_cfg_t const * const p_cfg); + +fsp_err_t R_IWDT_StatusClear(wdt_ctrl_t * const p_api_ctrl, const wdt_status_t status); + +fsp_err_t R_IWDT_StatusGet(wdt_ctrl_t * const p_api_ctrl, wdt_status_t * const p_status); + +fsp_err_t R_IWDT_CounterGet(wdt_ctrl_t * const p_api_ctrl, uint32_t * const p_count); + +fsp_err_t R_IWDT_TimeoutGet(wdt_ctrl_t * const p_api_ctrl, wdt_timeout_values_t * const p_timeout); + +fsp_err_t R_IWDT_CallbackSet(wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void * const p_context, + wdt_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IWDT_H + +/*******************************************************************************************************************//** + * @} (end addtogroup IWDT) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_jpeg.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_jpeg.h new file mode 100644 index 0000000000..41d0d2dcd0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_jpeg.h @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_jpeg.h + * Description : JPEG Module instance header file. + **********************************************************************************************************************/ + +/*****************************************************************************************************************//** + * @addtogroup JPEG + * @{ + **********************************************************************************************************************/ + +#ifndef R_JPEG_H +#define R_JPEG_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_jpeg_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** JPEG Codec module control block. DO NOT INITIALIZE. Initialization occurs when jpep_api_t::open is called. */ +typedef struct st_jpeg_instance_ctrl +{ + uint32_t open; ///< JPEG Codec driver status + jpeg_status_t status; ///< JPEG Codec operational status + fsp_err_t error_code; ///< JPEG Codec error code (if any). + jpeg_mode_t mode; ///< Current mode (decode or encode). + + uint32_t horizontal_stride_bytes; ///< Horizontal Stride settings. + uint32_t output_buffer_size; ///< Output buffer size + + /* Pointer to JPEG codec peripheral specific configuration */ + jpeg_cfg_t const * p_cfg; ///< JPEG Decode configuration struct + void const * p_extend; ///< JPEG Codec hardware dependent configuration */ + +#if JPEG_CFG_DECODE_ENABLE + jpeg_decode_pixel_format_t pixel_format; ///< Pixel format + uint16_t total_lines_decoded; ///< Track the number of lines decoded so far. + jpeg_decode_subsample_t horizontal_subsample; ///< Horizontal sub-sample setting. +#endif + +#if JPEG_CFG_ENCODE_ENABLE + uint16_t lines_to_encode; ///< Number of lines to encode + uint16_t vertical_resolution; ///< vertical size + uint16_t total_lines_encoded; ///< Number of lines encoded +#endif +} jpeg_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_JPEG_Open(jpeg_ctrl_t * const p_api_ctrl, jpeg_cfg_t const * const p_cfg); +fsp_err_t R_JPEG_OutputBufferSet(jpeg_ctrl_t * p_api_ctrl, void * output_buffer, uint32_t output_buffer_size); +fsp_err_t R_JPEG_InputBufferSet(jpeg_ctrl_t * constp_api_ctrl, void * p_data_buffer, uint32_t data_buffer_size); +fsp_err_t R_JPEG_StatusGet(jpeg_ctrl_t * p_api_ctrl, jpeg_status_t * p_status); +fsp_err_t R_JPEG_Close(jpeg_ctrl_t * p_api_ctrl); + +#if JPEG_CFG_ENCODE_ENABLE +fsp_err_t R_JPEG_EncodeImageSizeSet(jpeg_ctrl_t * const p_api_ctrl, jpeg_encode_image_size_t * p_image_size); + +#endif + +#if JPEG_CFG_DECODE_ENABLE +fsp_err_t R_JPEG_DecodeLinesDecodedGet(jpeg_ctrl_t * const p_api_ctrl, uint32_t * const p_lines); +fsp_err_t R_JPEG_DecodeHorizontalStrideSet(jpeg_ctrl_t * p_api_ctrl, uint32_t horizontal_stride); +fsp_err_t R_JPEG_DecodeImageSizeGet(jpeg_ctrl_t * p_api_ctrl, uint16_t * p_horizontal_size, uint16_t * p_vertical_size); +fsp_err_t R_JPEG_DecodeImageSubsampleSet(jpeg_ctrl_t * const p_api_ctrl, + jpeg_decode_subsample_t horizontal_subsample, + jpeg_decode_subsample_t vertical_subsample); +fsp_err_t R_JPEG_DecodePixelFormatGet(jpeg_ctrl_t * p_api_ctrl, jpeg_color_space_t * p_color_space); + +#endif + +#if JPEG_CFG_DECODE_ENABLE && JPEG_CFG_ENCODE_ENABLE +fsp_err_t R_JPEG_ModeSet(jpeg_ctrl_t * const p_api_ctrl, jpeg_mode_t mode); + +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +extern const jpeg_api_t g_jpeg_on_jpeg; + +/** @endcond */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup JPEG) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_kint.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_kint.h new file mode 100644 index 0000000000..ce90266bc3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_kint.h @@ -0,0 +1,64 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_KINT_H +#define R_KINT_H + +/*******************************************************************************************************************//** + * @addtogroup KINT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_keymatrix_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Channel instance control block. DO NOT INITIALIZE. Initialization occurs when @ref keymatrix_api_t::open is called. */ +typedef struct st_kint_instance_ctrl +{ + uint32_t open; + keymatrix_cfg_t const * p_cfg; +} kint_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const keymatrix_api_t g_keymatrix_on_kint; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_KINT_Open(keymatrix_ctrl_t * const p_api_ctrl, keymatrix_cfg_t const * const p_cfg); +fsp_err_t R_KINT_Enable(keymatrix_ctrl_t * const p_api_ctrl); +fsp_err_t R_KINT_Disable(keymatrix_ctrl_t * const p_api_ctrl); +fsp_err_t R_KINT_Close(keymatrix_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end addtogroup KINT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_layer3_switch.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_layer3_switch.h new file mode 100644 index 0000000000..9f17e01ebb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_layer3_switch.h @@ -0,0 +1,887 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup LAYER3_SWITCH + * @{ + **********************************************************************************************************************/ + +#ifndef R_LAYER3_SWITCH_H +#define R_LAYER3_SWITCH_H + +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "r_layer3_switch_cfg.h" +#include "r_ether_switch_api.h" +#include "r_ether_phy_api.h" +#include "r_gptp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** GWCA descriptor. */ +typedef struct st_layer3_switch_basic_descriptor +{ +#if ((defined(__GNUC__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) || (defined(__ARMCC_VERSION) && \ + !defined(__ARM_BIG_ENDIAN)) || (defined(__ICCARM__) && (__LITTLE_ENDIAN__))) + + /* Little endian. */ + volatile uint8_t ds_l; ///< 0.. 8 (8 bits), Descriptor size (low). + volatile uint8_t ds_h : 4; ///< 9..12 (4 bits), Descriptor size (High). + volatile uint8_t info0 : 4; ///< 12..15 (4 bits), Information 0. + volatile uint8_t err : 3; ///< 16..18 (3 bits), Error, data size error, AXI bus error. + volatile uint8_t die : 1; ///< 19 (1 bit), Descriptor interrupt enable. + volatile uint8_t dt : 4; ///< 20..23 (4 bits), Descriptor type. + volatile uint8_t ptr_h; ///< 24..31 (8 bits), Pointer (High). + volatile uint32_t ptr_l; ///< 32..63 (32 bits), Pointer (Low). +#endif +} layer3_switch_basic_descriptor_t; + +/** GWCA extended descriptor. */ +typedef struct st_layer3_switch_descriptor +{ + /* Little endian. */ +#if ((defined(__GNUC__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) || (defined(__ARMCC_VERSION) && \ + !defined(__ARM_BIG_ENDIAN)) || (defined(__ICCARM__) && (__LITTLE_ENDIAN__))) + + volatile layer3_switch_basic_descriptor_t basic; ///< Basic descriptor fields. + + /* Extended descriptor fields. */ + union + { + /* INFO1 of RX descriptor. */ + struct st_info1_rx + { + volatile uint8_t fi : 1; ///< 0 (1 bit), FCS in. + volatile uint8_t sec : 1; ///< 1 (1 bit), Secure descriptor. + volatile uint8_t fmt : 1; ///< 2 (1 bit), Descriptor format. + volatile uint8_t txc : 1; ///< 3 (1 bit), TX Time stamp capture. + volatile uint8_t iet : 1; ///< 4 (1 bit), Time stamp insertion request. + volatile uint8_t crt : 1; ///< 5 (1 bit), Residence time calculation request. + volatile uint8_t tn : 1; ///< 6 (1 bit), Timer utilized for capture/insertion. + volatile uint8_t : 1; ///< 7 (1 bit), Reserved. + volatile uint8_t tsun; ///< 8..15 (8 bits), Time stamp unique number. + volatile uint8_t saef; ///< 16..23 (8 bits), Source agent error flags. + volatile uint8_t rn; ///< 24..31 (8 bits), Routing number. + volatile uint32_t : 3; ///< 32..34 (3 bits), Reserved. + volatile uint32_t rv : 1; ///< 35 (1 bit), Routing valid. + volatile uint32_t spn : 3; ///< 36..38 (3 bits), Source port number. + volatile uint32_t : 1; ///< 39 (1 bit), Reserved. + volatile uint32_t fesf : 24; ///< 40..63 (24 bits), Forwarding engine status flags. + } info1_rx; + + /* INFO1 of TX descriptor. */ + struct st_info1_tx + { + volatile uint8_t fi : 1; ///< 0 (1 bit), FCS in. + volatile uint8_t sec : 1; ///< 1 (1 bit), Secure descriptor. + volatile uint8_t fmt : 1; ///< 2 (1 bit), Descriptor format. + volatile uint8_t txc : 1; ///< 3 (1 bit), TX Time stamp capture. + volatile uint8_t iet : 1; ///< 4 (1 bit), Time stamp insertion request. + volatile uint8_t crt : 1; ///< 5 (1 bit), Residence time calculation request. + volatile uint8_t tn : 1; ///< 6 (1 bit), Timer utilized for capture/insertion. + volatile uint8_t : 1; ///< 7 (1 bit), Reserved. + volatile uint8_t tsun; ///< 8..15 (8 bits), Time stamp unique number. + volatile uint8_t rn; ///< 16..23 (8 bits), Routing number. + volatile uint8_t : 3; ///< 24..26 (3 bits), Reserved. + volatile uint8_t rv : 1; ///< 27 (1 bit), Routing valid. + volatile uint8_t ipv : 3; ///< 28..30 (3 bits), Internal priority value. + volatile uint8_t fw : 1; ///< 31 (1 bit), FCS contained in frame is wrong. + volatile uint8_t csd0 : 7; ///< 32..38 (7 bits), CPU sub destination for GWCA0. + volatile uint8_t : 1; ///< 39 (1 bit), Reserved. + volatile uint8_t reserved1; ///< 40..47 (8 bits), Reserved. + volatile uint8_t dv : 7; ///< 48..54 (7 bits), Destination vector. + volatile uint8_t : 1; ///< 55 (1 bit), Reserved. + volatile uint8_t reserved2; ///< 56..63 (8 bits), Reserved. + } info1_tx; + }; + + #if LAYER3_SWITCH_CFG_GPTP_ENABLE + + /* Reception descriptor TS fields. */ + union + { + /* Reception direct descriptor TS. */ + struct st_reception_direct_descriptor + { + volatile uint8_t csd0 : 7; ///< 0..6 (7 bit), CPU sub destination for GWCA0 + volatile uint8_t : 1; ///< 7 (1 bit), Reserved + volatile uint8_t csd1 : 7; ///< 8..14 (7 bit), CPU sub destination for GWCA1 + volatile uint8_t : 1; ///< 15 (1 bit), Reserved + volatile uint8_t dv : 7; ///< 16..22 (7 bit), Destination vector + volatile uint8_t : 1; ///< 23 (1 bit), Reserved + volatile uint8_t reserved1; ///< 24..31 (8 bit), Reserved + volatile uint32_t reserved2; ///< 32..63 (32 bit), Reserved + } reception_direct_descriptor; + + /* Reception ethernet descriptor TS. */ + struct st_reception_ethernet_descriptor + { + volatile uint32_t tsns : 30; ///< 0..29 (30 bit), Timestamp nanosecond [gPTP] PCH header timestamp + volatile uint32_t tsv : 1; ///< 30 (1 bit), Timestamp valid + volatile uint32_t tsd : 1; ///< 31 (1 bit), Timestamp default + volatile uint32_t tss; ///< 32..63 (32 bit), Timestamp second [gPTP] PCH header timestamp + } reception_ethernet_descriptor; + }; + #endif +#endif +} layer3_switch_descriptor_t; + +/** + * GWCA TS reception process descriptor. + */ +typedef struct st_layer3_switch_ts_reception_process_descriptor +{ + /* Little endian. */ +#if ((defined(__GNUC__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) || (defined(__ARMCC_VERSION) && \ + !defined(__ARM_BIG_ENDIAN)) || (defined(__ICCARM__) && (__LITTLE_ENDIAN__))) + union + { + struct st_ts_reception_descriptor_basic + { + volatile uint8_t ds_l; ///< 0..7 (8 bit), Descriptor size + volatile uint8_t ds_h : 4; ///< 8..11 (4 bit), Descriptor size + volatile uint8_t info0 : 4; ///< 12..15 (4 bit), Information 0 + volatile uint8_t err : 1; ///< 16 (1 bit), Error + volatile uint8_t dse : 1; ///< 17 (1 bit), Data Size Error + volatile uint8_t axie : 1; ///< 18 (1 bit), AXI Bus Error + volatile uint8_t die : 1; ///< 19 (1 bit), Descriptor Interrupt Enable + volatile uint8_t dt : 4; ///< 20..23 (4 bit), Descriptor Type + volatile uint8_t ptr_h; ///< 24..31 (8 bit), Pointer + volatile uint32_t ptr_l; ///< 32..63 (32 bit), Pointer + volatile uint32_t reserved1; ///< 64..95 (32 bit), Reserved + volatile uint32_t reserved2; ///< 96..127 (32 bit), Reserved + } ts_reception_descriptor_basic; + + struct st_ts_reception_descriptor_result + { + volatile uint8_t ds_l; ///< 0..7 (8 bit), Descriptor size + volatile uint8_t ds_h : 4; ///< 8..11 (4 bit), Descriptor size + volatile uint8_t info0 : 4; ///< 12..15 (4 bit), Information 0 + volatile uint8_t err : 1; ///< 16 (1 bit), Error + volatile uint8_t dse : 1; ///< 17 (1 bit), Data Size Error + volatile uint8_t axie : 1; ///< 18 (1 bit), AXI Bus Error + volatile uint8_t die : 1; ///< 19 (1 bit), Descriptor Interrupt Enable + volatile uint8_t dt : 4; ///< 20..23 (4 bit), Descriptor Type + volatile uint8_t ptr; ///< 24..31 (8 bit), Pointer + volatile uint8_t tsun; ///< 32..39 (8 bit), Timestamp unique number + volatile uint8_t spn : 2; ///< 40..41 (2 bit), Port number from which the timestamp corresponding frame entered the switch + volatile uint8_t : 6; ///< 42..47 (6 bit), Reserved + volatile uint8_t dpn : 1; ///< 48 (1 bit), Port number by which the timestamp has been taken + volatile uint8_t : 7; ///< 49..55 (7 bit), Reserved + volatile uint8_t tn : 1; ///< 56 (1 bit), Timer Number + volatile uint8_t : 7; ///< 57..63 (7 bit), Reserved + volatile uint32_t tsns : 30; ///< 64..93 (30 bit), Timestamp nanosecond + volatile uint32_t : 2; ///< 94..95 (2 bit), Reserved + volatile uint32_t tss; ///< 96..127 (32 bit), Timestamp second + } ts_reception_descriptor_result; + }; +#endif +} layer3_switch_ts_reception_process_descriptor_t; + +/** GWCA descriptor type. */ +typedef enum e_layer3_switch_descriptor_type +{ + LAYER3_SWITCH_DESCRIPTOR_TYPE_LINKFIX = 0U, ///< Linkfix. Control element pointing to next descriptor in chain. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_IS = 1U, ///< Frame Empty Incremental Start. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_IC = 2U, ///< Frame Empty Incremental Continue. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_ND = 3U, ///< Frame Empty No Data Storage. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY = 4U, ///< Frame Empty. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_START = 5U, ///< Frame Empty Start. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_MID = 6U, ///< Frame Empty Mid. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_END = 7U, ///< Frame Empty End. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FSINGLE = 8U, ///< Frame Single. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FSTART = 9U, ///< Frame Start. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FMID = 10U, ///< Frame Mid. + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEND = 11U, ///< Frame End. + LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY = 12U, ///< Link Empty. + LAYER3_SWITCH_DESCRIPTOR_TYPE_EEMPTY = 13U, ///< EOS Empty. + LAYER3_SWITCH_DESCRIPTOR_TYPE_LINK = 14U, ///< Link. + LAYER3_SWITCH_DESCRIPTOR_TYPE_EOS = 15U, ///< End of Set. +} layer3_switch_descriptor_type_t; + +/** Bitmasks for each port. */ +typedef enum e_layer3_switch_port_bitmask +{ + LAYER3_SWITCH_PORT_BITMASK_PORT0 = (1U << 0U), ///< Port 0 + LAYER3_SWITCH_PORT_BITMASK_PORT1 = (1U << 1U), ///< Port 1 + LAYER3_SWITCH_PORT_BITMASK_PORT2 = (1U << 2U), ///< Port 2 +} layer3_switch_port_bitmask_t; + +/** Descriptor queue type. */ +typedef enum e_layer3_switch_queue_type +{ + LAYER3_SWITCH_QUEUE_TYPE_RX = 0U, ///< Reception queue. + LAYER3_SWITCH_QUEUE_TYPE_TX = 1U, ///< Transmission queue. +} layer3_switch_queue_type_t; + +/** Descriptor format type. */ +typedef enum e_layer3_switch_descriptor_format +{ + LAYER3_SWITCH_DISCRIPTOR_FORMTAT_BASIC = 0U, ///< Using basic descriptor. + LAYER3_SWITCH_DISCRIPTOR_FORMTAT_EXTENDED = 1U, ///< Using extended descriptor with additional fields. + LAYER3_SWITCH_DISCRIPTOR_FORMTAT_TX_TIMESTAMP = 2U, ///< Using TX timestamp descriptor. +} layer3_switch_descriptor_format_t; + +/** Write back mode. */ +typedef enum e_layer3_switch_write_back_mode +{ + LAYER3_SWITCH_WRITE_BACK_MODE_FULL = 0U, ///< All fields are updated by hardware. + LAYER3_SWITCH_WRITE_BACK_MODE_DISABLE = 1U, ///< No fields are updated by hardware. + LAYER3_SWITCH_WRITE_BACK_MODE_KEEP_DT = 2U, ///< Fields exclude DT are updated by hardware. +} layer3_switch_write_back_mode_t; + +/** IP version options. */ +typedef enum e_layer3_switch_ip_version +{ + LAYER3_SWITCH_IP_VERSION_NONE = 0U, ///< Not IP packet. + LAYER3_SWITCH_IP_VERSION_IPV4 = 1U, ///< IPv4 packet. + LAYER3_SWITCH_IP_VERSION_IPV6 = 2U, ///< IPv6 packet. +} layer3_switch_ip_version_t; + +/** Direction of IP address. */ +typedef enum e_layer3_switch_ip_address_direction +{ + LAYER3_SWITCH_IP_ADDRESS_DIRECTION_SOURCE = 0U, ///< Use IP source address in stream ID. + LAYER3_SWITCH_IP_ADDRESS_DIRECTION_DESTINATION = 1U, ///< Use IP destination address in stream ID. +} layer3_switch_ip_address_direction_t; + +/** Magic packet detection options. */ +typedef enum e_layer3_switch_magic_packet_detection +{ + LAYER3_SWITCH_MAGIC_PACKET_DETECTION_ENABLE = 1U, ///< Enable magic packet detection. + LAYER3_SWITCH_MAGIC_PACKET_DETECTION_DISABLE = 0U, ///< Disable magic packet detection. +} layer3_switch_magic_packet_detection_t; + +/** VLAN detection mode. */ +typedef enum e_layer3_switch_vlan_mode +{ + LAYER3_SWITCH_VLAN_MODE_NO_VLAN = 0U, ///< Not use VLAN feature. + LAYER3_SWITCH_VLAN_MODE_C_TAG = 1U, ///< Detect and use VLAN C-TAG. + LAYER3_SWITCH_VLAN_MODE_SC_TAG = 2U, ///< Detect and use VLAN SC-TAG. +} layer3_switch_vlan_mode_t; + +/** VLAN ingress mode determines whether the switch operates with tagged VLAN or port-based VLAN. */ +typedef enum e_layer3_switch_vlan_ingress_mode +{ + LAYER3_SWITCH_VLAN_INGRESS_MODE_TAG_BASED = 0U, ///< Use VLAN ID of the incoming frame. + LAYER3_SWITCH_VLAN_INGRESS_MODE_PORT_BASED = 1U, ///< Use VLAN ID of the incoming port. +} layer3_switch_vlan_ingress_mode_t; + +/** VLAN egress mode determines the VLAN tag that is added to output frames. */ +typedef enum e_layer3_switch_vlan_egress_mode +{ + LAYER3_SWITCH_VLAN_EGRESS_MODE_NO_VLAN = 0U, ///< Frame always outgoing without VLAN TAG. + LAYER3_SWITCH_VLAN_EGRESS_MODE_C_TAG = 1U, ///< Frame outgoing with C-TAG of incoming frame. + LAYER3_SWITCH_VLAN_EGRESS_MODE_HW_C_TAG = 2U, ///< Frame always outgoing with C-TAG of output port. + LAYER3_SWITCH_VLAN_EGRESS_MODE_SC_TAG = 3U, ///< Frame always outgoing with SC-TAG of incoming frame. + LAYER3_SWITCH_VLAN_EGRESS_MODE_HW_SC_TAG = 4U, ///< Frame always outgoing with SC-TAG of output port. +} layer3_switch_vlan_egress_mode_t; + +/** IP protocols type. */ +typedef enum e_layer3_switch_ip_protocol +{ + LAYER3_SWITCH_IP_PROTOCOL_TCP = 0x06U, ///< IP protocol is TCP. + LAYER3_SWITCH_IP_PROTOCOL_UDP = 0x11U, ///< IP protocol is UDP. +} layer3_switch_ip_protocol_t; + +/** R-TAG filed update options. */ +typedef enum e_layer3_switch_forwarding_r_tag +{ + LAYER3_SWITCH_FORWARDING_R_TAG_UPDATE = 0U, ///< Incoming frame with R-TAG will be updated with new R-TAG. + LAYER3_SWITCH_FORWARDING_R_TAG_ALWAYS_ADD = 1U, ///< ALl incoming frame will be added new R-TAG. + LAYER3_SWITCH_FORWARDING_R_TAG_ALWAYS_ELIMINATE = 2U, ///< ALl incoming frame will be removed R-TAG. +} layer3_switch_forwarding_r_tag_t; + +/** Frame filters options for layer3 forwarding. */ +typedef enum e_layer3_switch_l3_filter_bitmask +{ + LAYER3_SWITCH_L3_FILTER_BITMASK_MAC_DESTINATION = 0x1U, ///< Enable MAC destination address. + LAYER3_SWITCH_L3_FILTER_BITMASK_MAC_SOURCE = 0x2U, ///< Enable MAC source address. + LAYER3_SWITCH_L3_FILTER_BITMASK_STAG_ID = 0x4U, ///< Enable VLAN ID of S-TAG. + LAYER3_SWITCH_L3_FILTER_BITMASK_STAG_PCP = 0x8U, ///< Enable PCP of S-TAG. + LAYER3_SWITCH_L3_FILTER_BITMASK_STAG_DEI = 0x10U, ///< Enable DEI of S-TAG. + LAYER3_SWITCH_L3_FILTER_BITMASK_CTAG_ID = 0x20U, ///< Enable VLAN ID of C-TAG. + LAYER3_SWITCH_L3_FILTER_BITMASK_CTAG_PCP = 0x40U, ///< Enable PCP of C-TAG. + LAYER3_SWITCH_L3_FILTER_BITMASK_CTAG_DEI = 0x80U, ///< Enable DEI of C-TAG. + LAYER3_SWITCH_L3_FILTER_BITMASK_IP_SOURCE_ADDRESS = 0x100U, ///< Enable IP source address. + LAYER3_SWITCH_L3_FILTER_BITMASK_IP_DESTINATION_ADDRESS = 0x200U, ///< Enable IP destination address. + LAYER3_SWITCH_L3_FILTER_BITMASK_PROTOCOL = 0x400U, ///< Enable IP protocol. + LAYER3_SWITCH_L3_FILTER_BITMASK_IP_SOURCE_PORT = 0x800U, ///< Enable layer4 source port. + LAYER3_SWITCH_L3_FILTER_BITMASK_IP_DESTINATION_PORT = 0x1000U, ///< Enable layer4 destination port. +} layer3_switch_l3_filter_bitmask_t; + +/** Enable L2/L3 update feature. */ +typedef enum e_layer3_switch_l3_update_bitmask +{ + LAYER3_SWITCH_L3_UPDATE_BITMASK_TTL = 0x1U, ///< Update TTL + LAYER3_SWITCH_L3_UPDATE_BITMASK_MAC_DESTINATION = 0x2U, ///< Update MAC destination address. + LAYER3_SWITCH_L3_UPDATE_BITMASK_MAC_SOURCE = 0x4U, ///< Update MAC source address. + LAYER3_SWITCH_L3_UPDATE_BITMASK_CTAG_ID = 0x8U, ///< Update VLAN ID of C-TAG + LAYER3_SWITCH_L3_UPDATE_BITMASK_CTAG_PCP = 0x10U, ///< Update PCP of C-TAG + LAYER3_SWITCH_L3_UPDATE_BITMASK_CTAG_DEI = 0x20U, ///< Update DEI of C-TAG + LAYER3_SWITCH_L3_UPDATE_BITMASK_STAG_ID = 0x40U, ///< Update VLAN ID of C-TAG + LAYER3_SWITCH_L3_UPDATE_BITMASK_STAG_PCP = 0x80U, ///< Update PCP of C-TAG + LAYER3_SWITCH_L3_UPDATE_BITMASK_STAG_DEI = 0x100U, ///< Update DEI of C-TAG +} layer3_switch_l3_update_bitmask_t; + +/** Table entry type for forwarding feature. */ +typedef enum e_layer3_switch_table_entry_type +{ + LAYER3_SWITCH_TABLE_ENTRY_TYPE_EMPTY = 0U, ///< Entry is not initialized yet. + LAYER3_SWITCH_TABLE_ENTRY_TYPE_MAC = 1U, ///< Entry of MAC table. + LAYER3_SWITCH_TABLE_ENTRY_TYPE_VLAN = 2U, ///< Entry of VLAN table. + LAYER3_SWITCH_TABLE_ENTRY_TYPE_LAYER3 = 3U, ///< Entry of Layer3 table. +} layer3_switch_table_entry_type_t; + +/** Table status for forwarding feature. */ +typedef enum e_layer3_switch_table_status +{ + LAYER3_SWITCH_TABLE_STATUS_UNINITIALIZED = 0, ///< Forwarding table is uninitialized + LAYER3_SWITCH_TABLE_STATUS_INITIALIZED = 1 ///< Forwarding table is initialized +} layer3_switch_table_status_t; + +/** TAS gate state. */ +typedef enum e_layer3_switch_tas_gate_state +{ + LAYER3_SWITCH_TAS_GATE_STATE_CLOSE = 0, ///< Gate is closed. + LAYER3_SWITCH_TAS_GATE_STATE_OPEN = 1 ///< Gate is opened. +} layer3_switch_tas_gate_state_t; + +/** Enable or disable rx timestamp storage. */ +typedef enum e_layer3_switch_rx_timestamp_storage +{ + LAYER3_SWITCH_RX_TIMESTAMP_STORAGE_DISABLE = 0U, ///< Timestamp is not added in the descriptor. + LAYER3_SWITCH_RX_TIMESTAMP_STORAGE_ENABLE = 1U, ///< Timestamp is added in the descriptor. +} layer3_switch_rx_timestamp_storage_t; + +/** Used or not timestamp descriptor queue. */ +typedef enum e_layer3_switch_ts_descriptor_queue_status +{ + LAYER3_SWITCH_TS_DESCRIPTOR_QUEUE_STATUS_UNUSED = 0U, ///< TS descriptor queue is unused. + LAYER3_SWITCH_TS_DESCRIPTOR_QUEUE_STATUS_USED = 1U, ///< TS descriptor queue is used. +} layer3_switch_ts_descriptor_queue_status_t; + +/** Fragment size of preemptable frame. */ +typedef enum e_layer3_switch_preemptable_frame_fragment_size +{ + LAYER3_SWITCH_PREEMPTABLE_FRAME_FRAGMENT_SIZE_64BYTE = 0U, ///< Minimum fragment size is 64 byte. + LAYER3_SWITCH_PREEMPTABLE_FRAME_FRAGMENT_SIZE_128BYTE = 1U, ///< Minimum fragment size is 64 byte. + LAYER3_SWITCH_PREEMPTABLE_FRAME_FRAGMENT_SIZE_192BYTE = 2U, ///< Minimum fragment size is 64 byte. + LAYER3_SWITCH_PREEMPTABLE_FRAME_FRAGMENT_SIZE_256BYTE = 3U, ///< Minimum fragment size is 64 byte. +} layer3_switch_preemptable_frame_fragment_size_t; + +/** Used or not PSFP MSDU filter. */ +typedef enum e_layer3_switch_psfp_filter_status +{ + LAYER3_SWITCH_PSFP_FILTER_STATUS_UNUSED = 0U, ///< PSFP filter is unused. + LAYER3_SWITCH_PSFP_FILTER_STATUS_USED = 1U, ///< PSFP filter is used. +} layer3_switch_psfp_filter_status_t; + +/** PSFP MSDU filter mode. */ +typedef enum e_layer3_switch_msdu_filter_mode +{ + LAYER3_SWITCH_MSDU_FILTER_NORMAL_MODE = 0, ///< Filtering occurs if LDESCR.TPL[GWCA] is greater than FWPMPCi.MSDUV. + LAYER3_SWITCH_MSDU_FILTER_THROTTLE_MODE = 1, ///< Filtering occurs if LDESCR.TPL[GWCA] is greater than FWPMPCi.MSDUV. Frames with FWEIS2.PMFS[i] set are also filtered. +} layer3_switch_msdu_filter_mode_t; + +/** PSFP Meter filter mode. */ +typedef enum e_layer3_switch_meter_filter_mode +{ + LAYER3_SWITCH_METER_FILTER_NORMAL_MODE = 0U, ///< Any frame linked to Meter filter i thanks to L3 table received when not enough token is available will be red. + LAYER3_SWITCH_METER_FILTER_THROTTLE_MODE = 1U, ///< Any frame linked to Meter filter i thanks to L3 table received when not enough token is available or when FWEIS5.PMRFSi is set will be red. +} layer3_switch_meter_filter_mode_t; + +/** Enable or disable copling flag. */ +typedef enum e_layer3_switch_meter_filter_coupling_status +{ + LAYER3_SWITCH_METER_FILTER_COUPLING_STATUS_DISABLE = 0U, ///< When green bucket is full, CIR tokens are lost. + LAYER3_SWITCH_METER_FILTER_COUPLING_STATUS_ENABLE = 1U, ///< When green bucket is full, CIR tokens are added to the yellow bucket. +} layer3_switch_meter_filter_coupling_status_t; + +/** Drop or not red frames. */ +typedef enum e_layer3_switch_meter_filter_drop_red_frame +{ + LAYER3_SWITCH_METER_FILTER_NOT_DROP_RED_FRAME = 0U, ///< Red frames are not dropped by Meter filter. + LAYER3_SWITCH_METER_FILTER_DROP_RED_FRAME = 1U, ///< Red frames are dropped by Meter filter. +} layer3_switch_meter_filter_drop_red_frame_t; + +/** DEI handling policy for determining a frame color. */ +typedef enum e_layer3_switch_meter_filter_dei_handling_policy +{ + LAYER3_SWITCH_METER_FILTER_DEI_HANDLING_POLICY_IGNORE = 0U, ///< Ignore the DEI of the VLAN TAG, and the frame color is determined only by the PCP value. + LAYER3_SWITCH_METER_FILTER_DEI_HANDLING_POLICY_YELLOW = 1U, ///< When the DEI of the VLAN TAG is 1, treat it as a yellow frame. +} layer3_switch_meter_filter_dei_handling_policy_t; + +/** PCP handling policy for determining a frame color. */ +typedef enum e_layer3_switch_meter_filter_pcp_handling_policy +{ + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_GREEN_ALL = 0U, ///< Treat all frames as green, regardless of the PCP. + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_YELLOW_BELOW_1 = 1U, ///< Treat a frame as yellow when the PCP is less than 1. + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_YELLOW_BELOW_2 = 2U, ///< Treat a frame as yellow when the PCP is less than 2. + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_YELLOW_BELOW_3 = 3U, ///< Treat a frame as yellow when the PCP is less than 3. + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_YELLOW_BELOW_4 = 4U, ///< Treat a frame as yellow when the PCP is less than 4. + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_YELLOW_BELOW_5 = 5U, ///< Treat a frame as yellow when the PCP is less than 5. + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_YELLOW_BELOW_6 = 6U, ///< Treat a frame as yellow when the PCP is less than 6. + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_YELLOW_BELOW_7 = 7U, ///< Treat a frame as yellow when the PCP is less than 7. + LAYER3_SWITCH_METER_FILTER_PCP_HANDLING_POLICY_YELLOW_ALL = 8U, ///< Treat all frames as yellow, regardless of the PCP. +} layer3_switch_meter_filter_pcp_handling_policy_t; + +/** Configuration of PSFP MSDU filter. */ +typedef struct st_layer3_switch_psfp_msdu_filter_cfg +{ + uint32_t msdu_filter_id; ///< PSFP MSDU filter ID. + uint32_t maximum_frame_size; ///< Maximum frame size is rejected by PSFP MSDU filter. + layer3_switch_msdu_filter_mode_t mode; ///< PSFP MSDU filter mode. +} layer3_switch_psfp_msdu_filter_cfg_t; + +/** Information of PSFP MSDU filter. */ +typedef struct st_layer3_switch_psfp_msdu_filter_info +{ + uint32_t msdu_filter_hw_id; /// PSFP MSDU filter ID for hardware. + layer3_switch_psfp_filter_status_t status; /// Status of PSFP MSDU filter. + layer3_switch_psfp_msdu_filter_cfg_t * p_psfp_msdu_filter_cfg; ///< Pointer to configuration of PSFP MSDU filter. +} layer3_switch_psfp_msdu_filter_info_t; + +/** Configuration of PSFP Meter filter for user. */ +typedef struct st_layer3_switch_psfp_meter_filter_cfg +{ + uint32_t meter_filter_id; ///< PSFP Meter filter ID. + uint32_t cbs; ///< Maximum number of tokens (in bytes) contained in green bucket. + uint32_t cir; ///< Used to increment green tokens when green bucket is not full. + uint32_t ebs; ///< Maximum number of tokens (in bytes) contained in yellow bucket. + uint32_t eir; ///< Used to increment yellow tokens when yellow bucket is not full. + layer3_switch_meter_filter_mode_t mode; ///< Meter filter mode. + layer3_switch_meter_filter_drop_red_frame_t drop_red_frame; ///< Drop or not red frame by Meter filter. + layer3_switch_meter_filter_coupling_status_t coupling_enable; ///< When green bucket is full, CIR tokens are 0:lost, 1:added the yellow bucket. + layer3_switch_meter_filter_dei_handling_policy_t dei_handling_policy; ///< DEI handling policy for determining a frame color. + layer3_switch_meter_filter_pcp_handling_policy_t pcp_handling_policy; ///< PCP handling policy for determining a frame color. +} layer3_switch_psfp_meter_filter_cfg_t; + +/** Information of PSFP Meter filter. */ +typedef struct st_layer3_switch_psfp_meter_filter_info +{ + uint32_t meter_filter_hw_id; /// PSFP Meter filter ID for hardware. + layer3_switch_psfp_filter_status_t status; /// Status of PSFP Meter filter. + layer3_switch_psfp_meter_filter_cfg_t * p_psfp_meter_filter_cfg; ///< Pointer to configuration of PSFP Meter filter. +} layer3_switch_psfp_meter_filter_info_t; + +/** Bitmasks for clearing error status of throttle mode. */ +typedef struct st_layer3_switch_psfp_error_status_bitmask +{ + uint32_t msdu_filter_bitmask; ///< Bitmask for clearing error status bit of PSFP MSDU filter. + uint32_t meter_filter_bitmask; ///< Bitmask for clearing error status bit of PSFP Meter filter. +} layer3_switch_psfp_error_status_bitmask_t; + +/** Configuration of FRER feature. */ +typedef struct st_layer3_switch_frer_cfg +{ + uint32_t sys_clock; ///< Timeout check time. + uint32_t timeout_enable; ///< Timeout check valid. + uint32_t check_period; ///< Microsecond prescaler used to creates an internal clock for aging at 1 MHz to derive the timeout 1 kHz clock. +} layer3_switch_frer_cfg_t; + +/** FRER table entry. */ +typedef struct st_layer3_switch_frer_entry +{ + uint32_t take_no_sequence; ///< Reject frames without R-TAG. + uint32_t sequence_history_len; ///< Sequence history length. + uint32_t set_recovery_remaining_tick; ///< Time in tick before timeout. +} layer3_switch_frer_entry_t; + +/** Configuration of FRER entry (individual and sequence recovery). */ +typedef struct st_layer3_switch_frer_entry_cfg +{ + layer3_switch_frer_entry_t individual_recovery; ///< FRER table entry for individual recovery. + layer3_switch_frer_entry_t * p_sequence_recovery; ///< Pointer to FRER entry(sequence recovery) information referenced by `FRERN` in this FRER entry(individual recovery). + uint32_t sequence_recovery_id; +} layer3_switch_frer_entry_cfg_t; + +/** Status of FRER sequence recovery table. */ +typedef struct st_layer3_switch_frer_sequence_recovery_status +{ + bool learned; ///< Flags whether the FRER entry(sequence recovery) related to this entry has been learned. + uint32_t frer_entry_index; ///< Real FRER table index of the FRER entry(sequence recovery) related to this entry. +} layer3_switch_frer_sequence_recovery_status_t; + +/** Configuration of a descriptor queue. */ +typedef struct st_layer3_switch_descriptor_queue_cfg +{ + layer3_switch_descriptor_format_t descriptor_format; ///< Enable or disable extended descriptors. + layer3_switch_queue_type_t type; ///< Reception queue or transmission queue. + layer3_switch_write_back_mode_t write_back_mode; ///< Configure write-back to descriptor fields. + layer3_switch_descriptor_t * p_descriptor_array; ///< Descriptor array that use to create queue. + layer3_switch_ts_reception_process_descriptor_t * p_ts_descriptor_array; ///< TS descriptor array that use to create queue. + layer3_switch_rx_timestamp_storage_t rx_timestamp_storage; ///< Configure RX timestamp storage. + uint32_t array_length; ///< Length of descriptor array. This length includes terminate descriptor at the end. + uint32_t ports; ///< Bitmap of ports that use this queue. +} layer3_switch_descriptor_queue_cfg_t; + +/** Configuration of Credit Based Shaper. */ +typedef struct st_layer3_switch_cbs_cfg +{ + uint8_t band_width_list[8]; ///< CBS band width [%] of each queue. + uint8_t max_burst_num_list[8]; ///< Maximum burst frame number of each queue. +} layer3_switch_cbs_cfg_t; + +/** Configuration of each Ethernet port. */ +typedef struct st_layer3_switch_port_cfg +{ + uint8_t * p_mac_address; ///< Pointer to MAC address. + bool forwarding_to_cpu_enable; ///< Enable or disable reception on CPU. + layer3_switch_cbs_cfg_t * p_cbs_cfg; ///< Pointer to CBS configuration. + void (* p_callback)(ether_switch_callback_args_t * p_args); ///< Callback provided when an ISR occurs. + ether_switch_callback_args_t * p_callback_memory; ///< Pointer to optional callback argument memory + void * p_context; ///< Pointer to context to be passed into callback function +} layer3_switch_port_cfg_t; + +/** Status of a descriptor queue. */ +typedef struct st_layer3_switch_descriptor_queue_status +{ + uint32_t head; ///< Index at the head of the queue. This used for GetDescriptor API. + uint32_t tail; ///< Index at the tail of the queue. This used for SetDescriptor API. + bool created; ///< This queue is already created. + layer3_switch_descriptor_queue_cfg_t const * p_queue_cfg; ///< Configuration of this queue. + bool rx_available; ///< Indicates whether the queue is available for reception. +} layer3_switch_descriptor_queue_status_t; + +/** IP address offset for creating IPv6 filter of Layer3 forwarding. */ +typedef struct st_layer3_switch_ipv6_filter_address_offset +{ + uint8_t offset; ///< Offset of IPv6 address. + layer3_switch_ip_address_direction_t direction; ///< Select source or destination. +} layer3_switch_ipv6_filter_address_offset_t; + +/** Configuration of stream filter in Layer3 forwarding. */ +typedef struct st_layer3_switch_l3_stream_filter_cfg +{ + uint16_t filter_field_bitmask; ///< Bitmask of which feilds is enabled in stream filter. Use @ref layer3_switch_l3_filter_bitmask_t. + layer3_switch_ipv6_filter_address_offset_t ipv6_address0; ///< Offset of IPv6 address 0. + layer3_switch_ipv6_filter_address_offset_t ipv6_address1; ///< Offset of IPv6 address 1. +} layer3_switch_l3_stream_filter_cfg_t; + +/* Stream ID of Layer3 forwarding entry. This structure is used internally only. */ +typedef struct st_layer3_switch_stream_id +{ + uint8_t frame_format_code; ///< Format code that implies which filter created this stream ID. + union + { + uint32_t words[4]; ///< Stream ID as words. + uint8_t bytes[16]; ///< Stream ID as bytes. + }; +} layer3_switch_stream_id_t; + +/** VLAN tag structure. */ +typedef struct st_layer3_switch_frame_vlan_tag +{ + uint16_t pcp : 3; ///< Priority Code Point (3 bit). + uint16_t dei : 1; ///< Drop Eligible Indicator (1 bit). + uint16_t id : 12; ///< VLAN ID (12 bit). +} layer3_switch_frame_vlan_tag_t; + +/** Frame filter of a MAC/VLAN/Layer3 forwarding entry. Set values for members required for filtering. */ +typedef struct st_layer3_switch_frame_filter +{ + /* Entry type. */ + layer3_switch_table_entry_type_t entry_type; ///< Type of this entry. Select MAC, VLAN or Layer3. + + /* Used for MAC and Layer3 entry. */ + uint8_t * p_destination_mac_address; ///< Destination MAC address. + uint8_t * p_source_mac_address; ///< Source MAC address. + + /* Used for VLAN and Layer3 entry. */ + layer3_switch_frame_vlan_tag_t vlan_c_tag; ///< VLAN C-TAG. + layer3_switch_frame_vlan_tag_t vlan_s_tag; ///< VLAN S-TAG. + + /* Used for Layer3 table. */ + layer3_switch_ip_version_t ip_version; ///< IP version. Select IPv4, IPv6, or not IP packet. + uint8_t protocol; ///< IP protocol + uint8_t * p_source_ip_address; ///< Source IP address. + uint8_t * p_destination_ip_address; ///< Destination IP address. + uint16_t layer4_source_port; ///< TCP/UDP source port. + uint16_t layer4_destination_port; ///< TCP/UDP destination port. +} layer3_switch_frame_filter_t; + +/** Store filter information of Layer3 forwarding entry. */ +typedef struct st_layer3_switch_l3_filter +{ + layer3_switch_frame_filter_t frame; ///< Target frame format that used to Layer3 forwarding. +} layer3_switch_l3_filter_t; + +/** Configuration of a L2/L3 update feature for output frames. */ +typedef struct st_layer3_switch_l3_update_config +{ + uint32_t enable_destination_ports; ///< Destination ports that this update config is enabled. + uint32_t update_field_bitmask; ///< Bit mask of which fields will be updated. Use @ref layer3_switch_l3_update_bitmask_t. + uint8_t * p_mac_destination_address; ///< MAC Destination Address. + layer3_switch_frame_vlan_tag_t vlan_c_tag; ///< VLAN C-tag. + layer3_switch_frame_vlan_tag_t vlan_s_tag; ///< VLAN S-tag. + layer3_switch_forwarding_r_tag_t r_tag_update_mode; ///< R-TAG update setting. + bool sequence_number_generation_enable; ///< Flags whether sequence number generation (FRER) is enabled for this entry. +} layer3_switch_l3_update_config_t; + +/** Table entry configuration of MAC/VLAN/Layer3 forwarding. */ +typedef struct st_layer3_switch_table_entry_cfg +{ + /* Entry settings. */ + bool entry_enable; ///< Enable or disable entry. If this field is false, entry will be removed. + bool security_enable; ///< Entry is secure or not. + + /* PSFP setting. */ + layer3_switch_psfp_msdu_filter_cfg_t * p_psfp_msdu_filter_cfg; /// Pointer to configuration of PSFP MDSU filter. + layer3_switch_psfp_meter_filter_cfg_t * p_psfp_meter_filter_cfg; ///< Pointer to configuration of PSFP Meter filter. + + /* FRER setting. */ + layer3_switch_frer_entry_cfg_t * p_frer_entry_cfg; ///< Configuration of the FRER entry(individual recovery) for this L3 entry (set to `NULL` : FRER is not valid in this L3 entry). + + /* Forwarding settings. */ + uint32_t destination_ports; ///< Destination ports of forwarding. + uint32_t source_ports; ///< Source ports that enable forwarding of incoming frame. + uint32_t destination_queue_index; ///< Destination queue. This fields is only used when a destination port is CPU. + uint32_t internal_priority_update_enable; ///< Enable to update internal priority + uint32_t internal_priority_update_value; ///< Internal priority when updating is enabled. + + /* Forwarding protocol specific features. */ + union + { + /* MAC forwarding entry fields. */ + struct st_mac + { + bool dinamic_entry; ///< This entry is dynamic entry or not. Dynamic entry enable aging feature. + } mac; + + /* Layer3 forwarding specific feature. */ + struct st_layer3 + { + layer3_switch_l3_update_config_t * p_update_configs; ///< Pointer to an array of a L2/L3 update configurations. + uint32_t number_of_configs; ///< Number of the update configs. + } layer3; + }; +} layer3_switch_table_entry_cfg_t; + +/** Table entry of MAC/VLAN/Layer3 forwarding. */ +typedef struct st_layer3_switch_table_entry +{ + layer3_switch_frame_filter_t target_frame; ///< Target frame of forwarding by this entry. + layer3_switch_table_entry_cfg_t entry_cfg; ///< Configuration of this entry. +} layer3_switch_table_entry_t; + +/** Configuration of forwarding feature for each port. */ +typedef struct st_layer3_switch_forwarding_port_cfg +{ + /* MAC table configuration. */ + bool mac_table_enable; ///< Enable MAC table and forwarding feature. + bool mac_reject_unknown; ///< Reject frame with unknown MAC address. + bool mac_hardware_learning_enable; ///< Enable hardware learning and migration. + + /* VLAN table configuration. */ + bool vlan_table_enable; ///< Enable VLAN table and forwarding feature. + bool vlan_reject_unknown; ///< Reject frame with unknown VLAN ID. + layer3_switch_vlan_ingress_mode_t vlan_ingress_mode; ///< Select Tag-based VLAN or Port-based VLAN for incoming frame. + layer3_switch_vlan_egress_mode_t vlan_egress_mode; ///< Tagging/untagging mode for outgoing frame. + layer3_switch_frame_vlan_tag_t vlan_s_tag; ///< S-TAG of this port. When egress mode is hardware SC-TAG, add this to outgoing frame. + layer3_switch_frame_vlan_tag_t vlan_c_tag; ///< C-TAG of this port. When egress mode is hardware C-TAG, add this to outgoing frame. + + /* Layer3 table configuration. */ + bool layer3_table_enable; ///< Enable Layer3 table and forwarding feature. + bool layer3_reject_unknown; ///< Reject frame that not found in Layer3 table. + bool layer3_ipv4_filter_enable; ///< Enable IPv4 stream filter. + bool layer3_ipv6_filter_enable; ///< Enable IPv6 stream filter. + bool layer3_l2_filter_enable; ///< Enable L2 stream filter. +} layer3_switch_forwarding_port_cfg_t; + +/** Forwarding table containing MAC/VLAN/Layer3 forwarding entries. */ +typedef struct st_layer3_switch_table +{ + layer3_switch_table_entry_t * p_mac_entry_list; ///< List of MAC entries. + uint32_t mac_list_length; ///< Length of the MAC entry list. + layer3_switch_table_entry_t * p_vlan_entry_list; ///< List of VLAN entries. + uint32_t vlan_list_length; ///< Length of the VLAN entry list. + layer3_switch_table_entry_t * p_l3_entry_list; ///< List of Layer3 entries. + uint32_t l3_list_length; ///< Length of the Layer3 entry list. +} layer3_switch_table_t; + +/** Configuration of the forwarding table. */ +typedef struct st_layer3_switch_table_cfg +{ + layer3_switch_table_t * p_table; ///< Pointer to forwarding table. + layer3_switch_forwarding_port_cfg_t port_cfg_list[BSP_FEATURE_ETHER_NUM_CHANNELS + 1]; ///< Forwarding configuration of each port. + uint32_t unsecure_entry_maximum_num; ///< Maximum number of unsecure entries. + + /* MAC table configuration. */ + bool mac_entry_aging_enable; ///< Enable aging feature of MAC table. + uint32_t mac_entry_aging_time_sec; ///< Time[s] to delete an entry by aging. + + /* VLAN table configuration. */ + layer3_switch_vlan_mode_t vlan_mode; ///< VLAN mode options: NO VLAN, C-TAG, or SC-TAG. + + /* Layer3 table configuration. */ + layer3_switch_l3_stream_filter_cfg_t l3_stream_filter_cfg; ///< Configuration of stream filter in Layer3 forwarding. + layer3_switch_frer_cfg_t frer_cfg; ///< Configuration of FRER feature. +} layer3_switch_table_cfg_t; + +/** ESWM extension configures each Ethernet port and forwarding feature. */ +typedef struct st_layer3_switch_extended_cfg +{ + ether_phy_instance_t const * p_ether_phy_instances[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< List of pointers to ETHER_PHY instance. + gptp_instance_t const * p_gptp_instance; ///< Pointer to a gPTP instance. + uint32_t fowarding_target_port_masks[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< List of ports to which incoming frames are forwarded. + uint8_t * p_mac_addresses[BSP_FEATURE_ETHER_NUM_CHANNELS]; // [DEPRECATED] MAC address of each port. + uint32_t ipv_queue_depth_list[BSP_FEATURE_ETHER_NUM_CHANNELS][BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM]; ///< List of IPV queue depth for each port. + uint32_t ipv_queue_preemptable_bitmask[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< Bitmask of IPV queues that contain preemptable frames. + layer3_switch_preemptable_frame_fragment_size_t frame_preemption_fragment_size[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< Minimum fragment size of preemptable frame. + layer3_switch_l3_filter_t * l3_filter_list; ///< Filter list of layer3 routing. + uint32_t l3_filter_list_length; ///< Length of Layer3 filter list. + layer3_switch_port_cfg_t * p_port_cfg_list[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< Configuration for each port. + IRQn_Type etha_error_irq_port_0; ///< ETHA error interrupt number for port 0. + IRQn_Type etha_error_irq_port_1; ///< ETHA error interrupt number for port 1. + uint8_t etha_error_ipl_port_0; ///< ETHA error interrupt priority for port 0. + uint8_t etha_error_ipl_port_1; ///< ETHA error interrupt priority for port 1. + uint8_t gptp_timer_numbers[BSP_FEATURE_ESWM_GPTP_TIMER_NUM]; ///< List of timer numbers for transmission/reception timestamp. +} layer3_switch_extended_cfg_t; + +/** LAYER3_SWITCH control block. DO NOT INITIALIZE. Initialization occurs when @ref ether_switch_api_t::open is called. */ +typedef struct st_layer3_switch_instance_ctrl +{ + uint32_t open; ///< Used to determine if the channel is configured + ether_switch_cfg_t const * p_cfg; ///< Pointer to initial configurations. + R_GWCA0_Type * p_gwca_reg; ///< Pointer to GWCA register. + + uint32_t allocated_descriptor_queue_index; ///< Index of the descriptor pool. + layer3_switch_basic_descriptor_t p_descriptor_queue_list[LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM]; ///< Descriptor queue lists used by hardware. + layer3_switch_descriptor_queue_status_t p_queues_status[LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM]; ///< Status of each descriptor queues. + layer3_switch_port_cfg_t p_port_cfg_list[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< Configuration for each port. + + /* Forwarding features. */ + layer3_switch_table_status_t table_status; ///< Forwarding table is initialized or not. + uint32_t l3_entry_count; ///< Counts of valid LAYER3 entry. + uint8_t l3_routing_number; ///< Routing number for L2/L3 update feature. + uint8_t l3_remapping_number; ///< Remapping number for L2/L3 update feature. + + /* Timestamp features. */ + layer3_switch_ts_descriptor_queue_status_t ts_descriptor_queue_status_list[ + BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM]; ///< Status of TS reception descriptor queues. + + /* PSFP features. */ + layer3_switch_psfp_msdu_filter_info_t psfp_msdu_filter_info_list[BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM]; ///< List of information of PSFP MSDU filter. + layer3_switch_psfp_meter_filter_info_t psfp_meter_filter_info_list[ + BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM]; ///< List of information of PSFP Meter filter. + + /* FRER features. */ + uint32_t valid_frer_entry_num; ///< Number of valid FRER entry. + layer3_switch_frer_sequence_recovery_status_t frer_sequence_recovery_status[BSP_FEATURE_ESWM_FRER_TABLE_SIZE]; ///< Status of table for each FRER sequence recovery entry. + uint32_t used_frer_sequence_generator_num; ///< Number of the sequence number generator. + + /* Frame preemption features. */ + bool frame_preemption_available[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< Status of the frame preemption verification. + + void (* p_callback)(ether_switch_callback_args_t * p_args); ///< Callback provided when an ISR occurs. + ether_switch_callback_args_t * p_callback_memory; ///< Pointer to optional callback argument memory + void * p_context; ///< Pointer to context to be passed into callback function +} layer3_switch_instance_ctrl_t; + +/** Configuration of the gate operation. */ +typedef struct st_layer3_switch_etha_tas_entry +{ + layer3_switch_tas_gate_state_t state; ///< Gate state. + uint32_t time; ///< Time associated with the entry gate state [nsec]. +} layer3_switch_tas_entry_t; + +/** Configuration of the gate. */ +typedef struct st_layer3_switch_tas_gate_cfg +{ + layer3_switch_tas_gate_state_t initial_gate_state; ///< Initial gate state when the cycle starts. + uint8_t tas_entry_num; ///< Number of TAS entries included in this gate. + layer3_switch_tas_entry_t * p_tas_entry_list; ///< List of TAS entries included in this gate. +} layer3_switch_tas_gate_cfg_t; + +/** Configuration of the TAS. */ +typedef struct st_layer3_switch_tas_cfg +{ + uint8_t gptp_timer_number; ///< gPTP timer number. + uint32_t cycle_time_start_high; ///< Upper 32 bits of TAS cycle start time [nsec]. + uint32_t cycle_time_start_low; ///< Lower 32 bits of TAS cycle start time [nsec]. + uint32_t cycle_time; ///< TAS cycle time [nsec]. + layer3_switch_tas_gate_cfg_t gate_cfg_list[8]; ///< List of TAS gate configurations. +} layer3_switch_tas_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ether_switch_api_t g_ether_switch_on_layer3_switch; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_Open(ether_switch_ctrl_t * const p_ctrl, ether_switch_cfg_t const * const p_cfg); + +fsp_err_t R_LAYER3_SWITCH_Close(ether_switch_ctrl_t * const p_ctrl); + +fsp_err_t R_LAYER3_SWITCH_CreateDescriptorQueue(ether_switch_ctrl_t * const p_ctrl, + uint32_t * const p_queue_index, + layer3_switch_descriptor_queue_cfg_t const * const p_queue_cfg); + +fsp_err_t R_LAYER3_SWITCH_SetDescriptor(ether_switch_ctrl_t * const p_ctrl, + uint32_t queue_index, + layer3_switch_descriptor_t const * const p_descriptor); + +fsp_err_t R_LAYER3_SWITCH_GetDescriptor(ether_switch_ctrl_t * const p_ctrl, + uint32_t queue_index, + layer3_switch_descriptor_t * const p_descriptor); + +fsp_err_t R_LAYER3_SWITCH_StartDescriptorQueue(ether_switch_ctrl_t * const p_ctrl, uint32_t queue_index); + +fsp_err_t R_LAYER3_SWITCH_CallbackSet(ether_switch_ctrl_t * const p_ctrl, + void ( * p_callback)(ether_switch_callback_args_t *), + void * const p_context, + ether_switch_callback_args_t * const p_callback_memory); + +fsp_err_t R_LAYER3_SWITCH_ConfigurePort(ether_switch_ctrl_t * const p_ctrl, + uint8_t port, + layer3_switch_port_cfg_t * p_port_cfg); + +fsp_err_t R_LAYER3_SWITCH_AddTableEntry(ether_switch_ctrl_t * const p_ctrl, + layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t const * const p_entry_cfg); +fsp_err_t R_LAYER3_SWITCH_SearchTableEntry(ether_switch_ctrl_t * const p_ctrl, + layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t * const p_entry_cfg); +fsp_err_t R_LAYER3_SWITCH_ConfigureTable(ether_switch_ctrl_t * const p_ctrl, + layer3_switch_table_cfg_t const * const p_table_cfg); +fsp_err_t R_LAYER3_SWITCH_GetTable(ether_switch_ctrl_t * const p_ctrl, layer3_switch_table_t * const p_table); +fsp_err_t R_LAYER3_SWITCH_ConfigureTAS(ether_switch_ctrl_t * const p_ctrl, + uint8_t port, + layer3_switch_tas_cfg_t * p_tas_cfg); +fsp_err_t R_LAYER3_SWITCH_EnableTAS(ether_switch_ctrl_t * const p_ctrl, uint8_t port); + +fsp_err_t R_LAYER3_SWITCH_PsfpClearErrorStatus(ether_switch_ctrl_t * const p_ctrl, + layer3_switch_psfp_error_status_bitmask_t bitmasks); + +/*******************************************************************************************************************//** + * @} (end addtogroup LAYER3_SWITCH) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_LAYER3_SWITCH_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_lpm.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_lpm.h new file mode 100644 index 0000000000..20b6c18d10 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_lpm.h @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup LPM + * @{ + **********************************************************************************************************************/ + +#ifndef R_LPM_H +#define R_LPM_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_lpm_cfg.h" +#include "r_lpm_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** LPM private control block. DO NOT MODIFY. Initialization occurs when R_LPM_Open() is called. */ +typedef struct st_lpm_instance_ctrl +{ + uint32_t lpm_open; // Indicates whether the open() API has been successfully called. + lpm_cfg_t const * p_cfg; // Pointer to initial configurations +} lpm_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const lpm_api_t g_lpm_on_lpm; + +/** @endcond */ + +fsp_err_t R_LPM_Open(lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg); +fsp_err_t R_LPM_Close(lpm_ctrl_t * const p_api_ctrl); +fsp_err_t R_LPM_LowPowerReconfigure(lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg); +fsp_err_t R_LPM_LowPowerModeEnter(lpm_ctrl_t * const p_api_ctrl); +fsp_err_t R_LPM_IoKeepClear(lpm_ctrl_t * const p_api_ctrl); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup LPM) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_lvd.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_lvd.h new file mode 100644 index 0000000000..5bbc9fd331 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_lvd.h @@ -0,0 +1,75 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup LVD-PVD + * @{ + **********************************************************************************************************************/ + +#ifndef R_LVD_H +#define R_LVD_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_lvd_cfg.h" +#include "r_lvd_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** LVD instance control structure */ +typedef struct st_lvd_instance_ctrl +{ + uint32_t open; + lvd_cfg_t const * p_cfg; + + void (* p_callback)(lvd_callback_args_t *); // Pointer to callback that is called when lvd_current_state_t changes. + lvd_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void * p_context; +} lvd_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const lvd_api_t g_lvd_on_lvd; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_LVD_Open(lvd_ctrl_t * const p_api_ctrl, lvd_cfg_t const * const p_cfg); +fsp_err_t R_LVD_Close(lvd_ctrl_t * const p_api_ctrl); +fsp_err_t R_LVD_StatusGet(lvd_ctrl_t * const p_api_ctrl, lvd_status_t * p_lvd_status); +fsp_err_t R_LVD_StatusClear(lvd_ctrl_t * const p_api_ctrl); +fsp_err_t R_LVD_CallbackSet(lvd_ctrl_t * const p_api_ctrl, + void ( * p_callback)(lvd_callback_args_t *), + void * const p_context, + lvd_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup LVD-PVD) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_csi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_csi.h new file mode 100644 index 0000000000..c56d537ff0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_csi.h @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_MIPI_CSI_H +#define R_MIPI_CSI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_mipi_csi_cfg.h" +#include "r_mipi_csi_contract_types.h" +#include "r_mipi_csi_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup MIPI_CSI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** MIPI CSI instance control block. */ +typedef struct st_mipi_csi_instance_ctrl +{ + uint32_t open; ///< Interface is open + mipi_csi_cfg_t const * p_cfg; ///< Pointer to configuration structure used to open the interface + void (* p_callback)(mipi_csi_callback_args_t *); ///< Pointer to callback that is called when an adc_event_t occurs. + void * p_context; ///< Pointer to context to be passed into callback function + mipi_csi_callback_args_t * p_callback_memory; ///< Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +} mipi_csi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const mipi_csi_api_t g_mipi_csi; + +/** @endcond */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_MIPI_CSI_Open(mipi_csi_ctrl_t * const p_api_ctrl, mipi_csi_cfg_t const * const p_cfg); +fsp_err_t R_MIPI_CSI_Close(mipi_csi_ctrl_t * const p_api_ctrl); +fsp_err_t R_MIPI_CSI_Start(mipi_csi_ctrl_t * const p_api_ctrl); +fsp_err_t R_MIPI_CSI_Stop(mipi_csi_ctrl_t * const p_api_ctrl); +fsp_err_t R_MIPI_CSI_StatusGet(mipi_csi_ctrl_t * const p_api_ctrl, mipi_csi_status_t * p_status); +fsp_err_t R_MIPI_CSI_Read(mipi_csi_ctrl_t * const p_api_ctrl, mipi_csi_short_packet_t * p_data); + +/*******************************************************************************************************************//** + * @} (end defgroup MIPI_CSI) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_MIPI_CSI_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_dsi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_dsi.h new file mode 100644 index 0000000000..715f622839 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_dsi.h @@ -0,0 +1,106 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_MIPI_DSI_H +#define R_MIPI_DSI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_mipi_dsi_cfg.h" +#include "r_mipi_dsi_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup MIPI_DSI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** MIPI DSI interrupt configuration */ +typedef struct st_mipi_dsi_irq_cfg +{ + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< Interrupt vector number +} mipi_dsi_irq_cfg_t; + +/** Extended configuration structure for MIPI DSI. */ +typedef struct st_mipi_dsi_extended_cfg +{ + /* Interrupt configuration */ + mipi_dsi_irq_cfg_t dsi_seq0; ///< Sequence 0 interrupt + mipi_dsi_irq_cfg_t dsi_seq1; ///< Sequence 1 interrupt + mipi_dsi_irq_cfg_t dsi_ferr; ///< DSI Fatal Error interrupt + mipi_dsi_irq_cfg_t dsi_ppi; ///< D-PHY PPI interrupt + mipi_dsi_irq_cfg_t dsi_rcv; ///< Receive interrupt + mipi_dsi_irq_cfg_t dsi_vin1; ///< Video Input Operation interrupt + + uint32_t dsi_rxie; ///< Receive interrupt enable configuration + uint32_t dsi_ferrie; ///< Fatal error interrupt enable configuration + uint32_t dsi_plie; ///< Physical lane interrupt enable configuration + uint32_t dsi_vmie; ///< Video mode interrupt enable configuration + uint32_t dsi_sqch0ie; ///< Sequence Channel 0 interrupt enable configuration + uint32_t dsi_sqch1ie; ///< Sequence Channel 1 interrupt enable configuration +} mipi_dsi_extended_cfg_t; + +/** MIPI DSI instance control block. */ +typedef struct st_mipi_dsi_instance_ctrl +{ + uint32_t open; ///< Interface is open + bool data_ulps_active; ///< Data lane ULPS status + bool clock_ulps_active; ///< Data lane ULPS status + mipi_dsi_lane_t ulps_status; ///< Ultra-low Power State active status + mipi_dsi_cfg_t const * p_cfg; ///< Pointer to configuration structure used to open the interface + void (* p_callback)(mipi_dsi_callback_args_t *); ///< Pointer to callback that is called when an adc_event_t occurs. + void * p_context; ///< Pointer to context to be passed into callback function + mipi_dsi_callback_args_t * p_callback_memory; ///< Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +} mipi_dsi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const mipi_dsi_api_t g_mipi_dsi; + +/** @endcond */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_Open(mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cfg_t const * const p_cfg); +fsp_err_t R_MIPI_DSI_Close(mipi_dsi_ctrl_t * const p_api_ctrl); +fsp_err_t R_MIPI_DSI_Start(mipi_dsi_ctrl_t * const p_api_ctrl); +fsp_err_t R_MIPI_DSI_UlpsEnter(mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_lane_t lane); +fsp_err_t R_MIPI_DSI_UlpsExit(mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_lane_t lane); +fsp_err_t R_MIPI_DSI_Stop(mipi_dsi_ctrl_t * const p_api_ctrl); +fsp_err_t R_MIPI_DSI_Command(mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cmd_t * p_cmd); +fsp_err_t R_MIPI_DSI_StatusGet(mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_status_t * p_status); + +/*******************************************************************************************************************//** + * @} (end addtogroup MIPI_DSI) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_MIPI_DSI_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_phy.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_phy.h new file mode 100644 index 0000000000..5308a4bf02 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mipi_phy.h @@ -0,0 +1,166 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_MIPI_PHY_H +#define R_MIPI_PHY_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup MIPI_PHY + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* MIPI_PHY PLL speed configuration */ +typedef union +{ + __PACKED_STRUCT + { + uint8_t div; ///< PHY PLL input divisor + uint8_t mul_frac : 2; ///< PHY PLL fractional multiplier (0, 1/3, 2/3, or 1/2) + uint8_t : 2; + uint8_t pll_div : 2; ///< PHY PLL output divisor (1/1, 1/2, 1/4, 1/8) + uint8_t : 2; + uint16_t mul_int; ///< PHY PLL integer multiplier (1-based) + }; + uint32_t raw; +} mipi_phy_pll_cfg_t; + +/** MIPI PHY D-PHY power mode transition timing */ +typedef struct st_mipi_phy_timing +{ + uint32_t t_init : 19; ///< Minimum duration of the TINIT state (Units: PCLKA cycles) + uint32_t : 13; // Padding + union + { + __PACKED_STRUCT + { + uint32_t t_clk_prep : 8; ///< Duration of the clock lane LP-00 state (immediately before entry to the HS-0 state) + uint32_t t_clk_settle : 8; ///< The period over which a transition to the HS state is to be ignored after the TCLK_PREPARE period has begun in the clock lane. + uint32_t t_clk_miss : 8; ///< The period from detection of the absence of a clock until disabling of the HS-RX in the clock lane + uint32_t : 8; + } dphytim2_b; + uint32_t dphytim2; + }; + + union + { + __PACKED_STRUCT + { + uint32_t t_hs_prep : 8; ///< Duration of the data lane LP-00 state (immediately before entry to the HS-0 state) + uint32_t t_hs_sett : 8; ///< The period over which a transition to the HS state is to be ignored after the TCLK_PREPARE period has begun in the clock lane. + uint32_t : 16; + } dphytim3_b; + uint32_t dphytim3; + }; + + union + { + __PACKED_STRUCT + { + uint8_t t_clk_zero; ///< TCLKZERO setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information + uint8_t t_clk_pre; ///< TCLKPRE setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information + uint8_t t_clk_post; ///< TCLKPOST setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information + uint8_t t_clk_trail; ///< TCLKTRAIL setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information + } dphytim4_b; + uint32_t dphytim4; ///< Clock lane pre and post data timing settings + }; + union + { + __PACKED_STRUCT + { + uint8_t t_hs_zero; ///< THSZERO setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information + uint8_t t_hs_trail; ///< THSTRAIL setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information + uint8_t t_hs_exit; ///< THSEXIT setting. See Figure "High-Speed data transmission in normal mode" in the MIPI PHY section of the relevant hardware manual for more information + uint8_t : 8; + } dphytim5_b; + uint32_t dphytim5; ///< High-Speed data lane timing settings + }; + uint8_t t_lp_exit; ///< Low-power transition time to High-Speed mode +} mipi_phy_timing_t; + +/** MIPI_PHY configuration structure. */ +typedef struct st_mipi_phy_cfg +{ + mipi_phy_pll_cfg_t pll_settings; ///< PHY PLL configuration (DPHYPLFCR) + uint8_t lp_divisor : 5; ///< PHY PLL LP speed divisor setting (DPHYESCCR) + mipi_phy_timing_t const * p_timing; ///< Pointer to D-PHY HS/LP transition timing values + bool dsi_mode; ///< DSI Mode Enabled (CSI Mode Disabled) +} mipi_phy_cfg_t; + +/** MIPI_PHY instance control block. */ +typedef struct st_mipi_phy_ctrl +{ + uint32_t open; + mipi_phy_cfg_t const * p_cfg; +} mipi_phy_ctrl_t; + +/** Private Interface definition for MIPI PHY peripheral */ +typedef struct st_mipi_phy_api +{ + /** Open MIPI PHY device. + * @param[in,out] p_ctrl Pointer to MIPI PHY interface control block. + * @param[in] p_cfg Pointer to MIPI PHY configuration structure. + */ + fsp_err_t (* open)(mipi_phy_ctrl_t * const p_ctrl, mipi_phy_cfg_t const * const p_cfg); + + /** Close MIPI PHY device. + * @param[in] p_ctrl Pointer to MIPI PHY interface control block. + */ + fsp_err_t (* close)(mipi_phy_ctrl_t * const p_ctrl); +} mipi_phy_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_mipi_phy_instance +{ + mipi_phy_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + mipi_phy_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + mipi_phy_api_t const * p_api; ///< Pointer to the API structure for this instance +} mipi_phy_instance_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const mipi_phy_api_t g_mipi_phy; + +/** @endcond */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Instance Functions (Note: This is not a public API and should not be called directly) + **********************************************************************************************************************/ +fsp_err_t r_mipi_phy_open(mipi_phy_ctrl_t * const p_api_ctrl, mipi_phy_cfg_t const * const p_cfg); +fsp_err_t r_mipi_phy_close(mipi_phy_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup MIPI_PHY) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_MIPI_PHY_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mram.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mram.h new file mode 100644 index 0000000000..ed6e87287f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_mram.h @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_MRAM_H +#define R_MRAM_H + +/*******************************************************************************************************************//** + * @addtogroup MRAM + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_flash_api.h" +#include "r_mram_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* If Code Flash programming is enabled, then all API functions must execute out of RAM. */ +#if defined(__ICCARM__) + #pragma section=".ram_from_flash" +#endif +#if defined(__ARMCC_VERSION) || defined(__GNUC__) + #define PLACE_IN_RAM_SECTION __attribute__((noinline)) BSP_PLACE_IN_SECTION(".ram_from_flash") +#else + #define PLACE_IN_RAM_SECTION BSP_PLACE_IN_SECTION(".ram_from_flash") +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** MRAM instance control block. DO NOT INITIALIZE. */ +typedef struct st_mram_instance_ctrl +{ + uint32_t opened; // To check whether api has been opened or not. + flash_cfg_t const * p_cfg; + + uint32_t timeout_mram_write; + uint32_t timeout_arc_increment; + uint32_t timeout_arc_read; + uint32_t timeout_configuration_set; + uint32_t timeout_maci_command; + + void (* p_callback)(flash_callback_args_t *); // Pointer to callback + flash_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void * p_context; // Pointer to context to be passed into callback function +} mram_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const flash_api_t g_flash_on_mram; + +/** @endcond */ + +fsp_err_t R_MRAM_Open(flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg); + +fsp_err_t R_MRAM_Write(flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t mram_address, + uint32_t const num_bytes) PLACE_IN_RAM_SECTION; + +fsp_err_t R_MRAM_Erase(flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks); + +fsp_err_t R_MRAM_BlankCheck(flash_ctrl_t * const p_api_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * blank_check_result); + +fsp_err_t R_MRAM_Close(flash_ctrl_t * const p_api_ctrl); + +fsp_err_t R_MRAM_StatusGet(flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status); + +fsp_err_t R_MRAM_AccessWindowSet(flash_ctrl_t * const p_api_ctrl, uint32_t const start_addr, uint32_t const end_addr); + +fsp_err_t R_MRAM_AccessWindowClear(flash_ctrl_t * const p_api_ctrl); + +fsp_err_t R_MRAM_IdCodeSet(flash_ctrl_t * const p_api_ctrl, uint8_t const * const p_id_code, flash_id_code_mode_t mode); + +fsp_err_t R_MRAM_Reset(flash_ctrl_t * const p_api_ctrl); + +fsp_err_t R_MRAM_UpdateFlashClockFreq(flash_ctrl_t * const p_api_ctrl); + +fsp_err_t R_MRAM_StartUpAreaSelect(flash_ctrl_t * const p_api_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary); +fsp_err_t R_MRAM_CallbackSet(flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void * const p_context, + flash_callback_args_t * const p_callback_memory); +fsp_err_t R_MRAM_BankSwap(flash_ctrl_t * const p_api_ctrl); +fsp_err_t R_MRAM_InfoGet(flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info); +fsp_err_t R_MRAM_AntiRollbackCounterIncrement(flash_ctrl_t * const p_api_ctrl, flash_arc_t counter); +fsp_err_t R_MRAM_AntiRollbackCounterRefresh(flash_ctrl_t * const p_api_ctrl, flash_arc_t counter); +fsp_err_t R_MRAM_AntiRollbackCounterRead(flash_ctrl_t * const p_api_ctrl, flash_arc_t counter, + uint32_t * const p_count); +fsp_err_t R_MRAM_UserLockableAreaWrite(flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t mram_address, + uint32_t const num_bytes); + +/*******************************************************************************************************************//** + * @} (end defgroup MRAM) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_opamp.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_opamp.h new file mode 100644 index 0000000000..6caff8c0a6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_opamp.h @@ -0,0 +1,179 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_OPAMP_H +#define R_OPAMP_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_opamp_cfg.h" +#include "r_opamp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup OPAMP + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Version of code that implements the API defined in this file */ + +#define OPAMP_MASK_CHANNEL_0 (1U << 0) +#define OPAMP_MASK_CHANNEL_1 (1U << 1) +#define OPAMP_MASK_CHANNEL_2 (1U << 2) +#define OPAMP_MASK_CHANNEL_3 (1U << 3) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Start and stop trigger for the op-amp. */ +typedef enum e_opamp_trigger +{ + OPAMP_TRIGGER_SOFTWARE_START_SOFTWARE_STOP = 0, ///< Start and stop with APIs + OPAMP_TRIGGER_AGT_START_SOFTWARE_STOP = 1, ///< Start by AGT compare match and stop with API + OPAMP_TRIGGER_AGT_START_ADC_STOP = 3, ///< Start by AGT compare match and stop after ADC conversion +} opamp_trigger_t; + +/** Which AGT timer starts the op-amp. Only applies to channels if OPAMP_TRIGGER_AGT_START_SOFTWARE_STOP or + * OPAMP_TRIGGER_AGT_START_ADC_STOP is selected for the channel. If OPAMP_TRIGGER_SOFTWARE_START_SOFTWARE_STOP is + * selected for a channel, then no AGT compare match event will start that op-amp channel. */ +typedef enum e_opamp_agt_link +{ + /** OPAMP channel 0 and 2 are started by AGT1 compare match. OPAMP channel 1 and 3 are started by AGT0 compare + * match. */ + OPAMP_AGT_LINK_AGT1_OPAMP_0_2_AGT0_OPAMP_1_3 = 0, + + /** OPAMP channel 0 and 1 are started by AGT1 compare match. OPAMP channel 2 and 3 are started by AGT0 compare + * match. */ + OPAMP_AGT_LINK_AGT1_OPAMP_0_1_AGT0_OPAMP_2_3 = 1, + + /** All OPAMP channels are started by AGT1 compare match. */ + OPAMP_AGT_LINK_AGT1_OPAMP_0_1_2_3 = 3, +} opamp_agt_link_t; + +/** Op-amp mode. */ +typedef enum e_opamp_mode +{ + OPAMP_MODE_LOW_POWER = 0, ///< Low power mode + OPAMP_MODE_MIDDLE_SPEED = 1, ///< Middle speed mode (not supported on all MCUs) + OPAMP_MODE_HIGH_SPEED = 3 ///< High speed mode +} opamp_mode_t; + +/* Op-amp trim state. */ +typedef enum e_opamp_priv_trim_state +{ + OPAMP_PRIV_TRIM_STATE_INVALID = -1, + OPAMP_PRIV_TRIM_STATE_END = 0, + OPAMP_PRIV_TRIM_STATE_BIT_0 = 0, + OPAMP_PRIV_TRIM_STATE_BIT_1 = 1, + OPAMP_PRIV_TRIM_STATE_BIT_2 = 2, + OPAMP_PRIV_TRIM_STATE_BIT_3 = 3, + OPAMP_PRIV_TRIM_STATE_BIT_4 = 4, + OPAMP_PRIV_TRIM_STATE_BEGIN = 5, +} opamp_priv_trim_state_t; + +/** Options to connect AMPnPS pins. */ +typedef enum e_opamp_plus_input +{ + OPAMP_PLUS_INPUT_NONE = 0, ///< No Connection + OPAMP_PLUS_INPUT_AMPPS0 = 1, ///< Set AMPPS0. See hardware manual for channel specific options + OPAMP_PLUS_INPUT_AMPPS1 = 2, ///< Set AMPPS1. See hardware manual for channel specific options + OPAMP_PLUS_INPUT_AMPPS2 = 4, ///< Set AMPPS2. See hardware manual for channel specific options + OPAMP_PLUS_INPUT_AMPPS3 = 8, ///< Set AMPPS3. See hardware manual for channel specific options + OPAMP_PLUS_INPUT_AMPPS7 = 128, ///< Set AMPPS7. See hardware manual for channel specific options +} opamp_plus_input_t; + +/** Options to connect AMPnMS pins. */ +typedef enum e_opamp_minus_input +{ + OPAMP_MINUS_INPUT_NONE = 0, ///< No Connection + OPAMP_MINUS_INPUT_AMPMS0 = 1, ///< Set AMPMS0. See hardware manual for channel specific options + OPAMP_MINUS_INPUT_AMPMS1 = 2, ///< Set AMPMS1. See hardware manual for channel specific options + OPAMP_MINUS_INPUT_AMPMS2 = 4, ///< Set AMPMS2. See hardware manual for channel specific options + OPAMP_MINUS_INPUT_AMPMS3 = 8, ///< Set AMPMS3. See hardware manual for channel specific options + OPAMP_MINUS_INPUT_AMPMS4 = 16, ///< Set AMPMS4. See hardware manual for channel specific options + OPAMP_MINUS_INPUT_AMPMS7 = 128, ///< Set AMPMS7. See hardware manual for channel specific options +} opamp_minus_input_t; + +/** Options to connect AMP0OS pin. */ +typedef enum e_opamp_output +{ + OPAMP_OUTPUT_NONE = 0, ///< No Connection + OPAMP_OUTPUT_AMPOS0 = 1, ///< Set AMPOS0. See hardware manual for channel specific options + OPAMP_OUTPUT_AMPOS1 = 2, ///< Set AMPOS1. See hardware manual for channel specific options + OPAMP_OUTPUT_AMPOS2 = 4, ///< Set AMPOS2. See hardware manual for channel specific options + OPAMP_OUTPUT_AMPOS3 = 8, ///< Set AMPOS3. See hardware manual for channel specific options +} opamp_output_t; + +/** OPAMP configuration extension. This extension is required and must be provided in opamp_cfg_t::p_extend. */ +typedef struct st_opamp_extended_cfg +{ + /** Configure which AGT links are paired to which channel. Only applies to channels if + * OPAMP_TRIGGER_AGT_START_SOFTWARE_STOP or OPAMP_TRIGGER_AGT_START_ADC_STOP is selected for the channel. */ + opamp_agt_link_t agt_link; + opamp_mode_t mode; ///< Low power, middle speed, or high speed mode + opamp_trigger_t trigger_channel_0; ///< Start and stop triggers for channel 0 + opamp_trigger_t trigger_channel_1; ///< Start and stop triggers for channel 1 + opamp_trigger_t trigger_channel_2; ///< Start and stop triggers for channel 2 + opamp_trigger_t trigger_channel_3; ///< Start and stop triggers for channel 3 + opamp_plus_input_t plus_input_select_opamp0; ///< OPAMP0+ connection + opamp_minus_input_t minus_input_select_opamp0; ///< OPAMP0- connection + opamp_output_t output_select_opamp0; ///< OPAMP0O connection + opamp_plus_input_t plus_input_select_opamp1; ///< OPAMP1+ connection + opamp_minus_input_t minus_input_select_opamp1; ///< OPAMP1- connection + opamp_plus_input_t plus_input_select_opamp2; ///< OPAMP2+ connection + opamp_minus_input_t minus_input_select_opamp2; ///< OPAMP2- connection +} opamp_extended_cfg_t; + +/** OPAMP instance control block. DO NOT INITIALIZE. Initialized in @ref opamp_api_t::open(). */ +typedef struct +{ + opamp_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t opened; // Boolean to verify that the Unit has been initialized + opamp_priv_trim_state_t trim_state; // Trim state for each op-amp + uint8_t trim_channel; // Channel + opamp_trim_input_t trim_input; // Which input of the channel above +} opamp_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_OPAMP_Open(opamp_ctrl_t * const p_api_ctrl, opamp_cfg_t const * const p_cfg); +fsp_err_t R_OPAMP_InfoGet(opamp_ctrl_t * const p_api_ctrl, opamp_info_t * const p_info); +fsp_err_t R_OPAMP_Start(opamp_ctrl_t * const p_api_ctrl, uint32_t const channel_mask); +fsp_err_t R_OPAMP_Stop(opamp_ctrl_t * const p_api_ctrl, uint32_t const channel_mask); +fsp_err_t R_OPAMP_StatusGet(opamp_ctrl_t * const p_api_ctrl, opamp_status_t * const p_status); +fsp_err_t R_OPAMP_Trim(opamp_ctrl_t * const p_api_ctrl, + opamp_trim_cmd_t const cmd, + opamp_trim_args_t const * const p_args); +fsp_err_t R_OPAMP_Close(opamp_ctrl_t * const p_api_ctrl); + +/** @cond INC_HEADER_DEFS_SEC */ +/** Interface Structure for user access */ +extern const opamp_api_t g_opamp_on_opamp; + +/** @endcond */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup OPAMP) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ospi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ospi.h new file mode 100644 index 0000000000..8cc64a53e5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ospi.h @@ -0,0 +1,191 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup OSPI + * @{ + **********************************************************************************************************************/ + +#ifndef R_OSPI_H +#define R_OSPI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_ospi_cfg.h" +#include "r_spi_flash_api.h" + +#if OSPI_CFG_DMAC_SUPPORT_ENABLE + #include "r_transfer_api.h" +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* OSPI Memory device chip select */ +typedef enum e_ospi_device_number +{ + OSPI_DEVICE_NUMBER_0, ///< Device connected to Chip-Select 0 + OSPI_DEVICE_NUMBER_1, ///< Device connected to Chip-Select 1 +} ospi_device_number_t; + +/* OSPI Memory device type select */ +typedef enum e_ospi_device_type +{ + OSPI_DEVICE_FLASH = 0, ///< Device Memory type OctaFlash + OSPI_DEVICE_RAM, ///< Device Memory type OctaRAM +} ospi_device_type_t; + +/* OSPI command to command interval in single continuous read/write mode + * Unit: OCTACLK + */ +typedef enum e_ospi_command_interval_clocks +{ + OSPI_COMMAND_INTERVAL_CLOCKS_2, + OSPI_COMMAND_INTERVAL_CLOCKS_5, + OSPI_COMMAND_INTERVAL_CLOCKS_7, + OSPI_COMMAND_INTERVAL_CLOCKS_9, + OSPI_COMMAND_INTERVAL_CLOCKS_11, + OSPI_COMMAND_INTERVAL_CLOCKS_13, + OSPI_COMMAND_INTERVAL_CLOCKS_15, + OSPI_COMMAND_INTERVAL_CLOCKS_17 +} ospi_command_interval_clocks_t; + +/* OSPI chip select de-assertion duration after last command in single continuous read/write mode + * Unit: OCTACLK + */ +typedef enum e_ospi_cs_pullup_clocks +{ + OSPI_COMMAND_CS_PULLUP_CLOCKS_2, ///< 1.5 clocks DOPI mode; 2 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_3, ///< 2.5 clocks DOPI mode; 3 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_4, ///< 3.5 clocks DOPI mode; 4 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_5, ///< 4.5 clocks DOPI mode; 5 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_6, ///< 5.5 clocks DOPI mode; 6 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_7, ///< 6.5 clocks DOPI mode; 7 Clocks all other modes + OSPI_COMMAND_CS_PULLUP_CLOCKS_8, ///< 7.5 clocks DOPI mode; 8 Clocks all other modes + OSPI_COMMAND_CS_PULLUP_CLOCKS_9 ///< 8.5 clocks DOPI mode; 9 Clocks all other modes +} ospi_command_cs_pullup_clocks_t; + +/* OSPI chip select assertion duration before first command in single continuous read/write mode + * Unit: OCTACLK + */ +typedef enum e_ospi_cs_pulldown_clocks +{ + OSPI_COMMAND_CS_PULLDOWN_CLOCKS_3 = 1, ///< 2.5 clocks DOPI mode; 3 Clocks all other modes + OSPI_COMMAND_CS_PULLDOWN_CLOCKS_4, ///< 3.5 clocks DOPI mode; 4 Clocks all other modes + OSPI_COMMAND_CS_PULLDOWN_CLOCKS_5 ///< 4.5 clocks DOPI mode; 5 Clocks all other modes +} ospi_command_cs_pulldown_clocks_t; + +/* OSPI DOPI byte order options */ +typedef enum e_ospi_dopi_byte_order +{ + OSPI_DOPI_BYTE_ORDER_0123, ///< DOPI byte order byte 0, byte 1, byte 2, byte 3 + OSPI_DOPI_BYTE_ORDER_1032 ///< DOPI byte order byte 1, byte 0, byte 3, byte 2 +} ospi_dopi_byte_order_t; + +/* Memory mapped timing */ +typedef struct st_ospi_timing_setting +{ + ospi_command_interval_clocks_t command_to_command_interval; ///< Interval between 2 consecutive commands + ospi_command_cs_pullup_clocks_t cs_pullup_lag; ///< Duration to de-assert CS line after the last command + ospi_command_cs_pulldown_clocks_t cs_pulldown_lead; ///< Duration to assert CS line before the first command +} ospi_timing_setting_t; + +/* This command set is used only with OPI mode set under ospi_extended_cfg_t. spi_flash_cfg_t holds commands for SPI mode. */ +typedef struct st_ospi_opi_command_set +{ + uint16_t dual_read_command; ///< Dual data Read command, valid only in DOPI mode + uint16_t page_program_command; ///< Page program command + uint16_t write_enable_command; ///< Command to enable write or erase, typically 0x06 + uint16_t status_command; ///< Command to read the write status + uint16_t read_command; ///< Read command + uint8_t command_bytes; ///< Command Bytes +} ospi_opi_command_set_t; + +/* Extended configuration. */ +typedef struct st_ospi_extended_cfg +{ + ospi_device_number_t channel; ///< Device number to be used for memory device + uint32_t memory_size; ///< Size of memory device + ospi_device_type_t memory_type; ///< Type of memory device + uint8_t data_latch_delay_clocks; ///< Specify delay between OM_DQS and OM_DQS Strobe. Set to 0 to auto-callibrate. Typical value is 0x80. + uint8_t om_dqs_enable_counter_dopi; ///< OM_DQS enable counter; Setting for DOPI mode (OctaRAM or OctaFlash based on memory_type). + uint8_t om_dqs_enable_counter_sopi; ///< OM_DQS enable counter; Setting for SOPI mode (OctaFlash Only). + uint8_t single_continuous_mode_read_idle_time; ///< Mode idle time duration in PCLKA + uint8_t single_continuous_mode_write_idle_time; ///< Mode idle time duration in PCLKA + ospi_timing_setting_t const * p_mem_mapped_read_timing_settings; ///< Memory mapped read mode settings + ospi_timing_setting_t const * p_mem_mapped_write_timing_settings; ///< Memory mapped write mode settings + ospi_timing_setting_t const * p_timing_settings; ///< Memory mapped write mode settings + ospi_opi_command_set_t const * p_opi_commands; ///< If OPI commands are not used set this to NULL + uint8_t opi_mem_read_dummy_cycles; ///< Dummy cycles to be inserted for memory mapped reads + uint8_t opi_mem_write_dummy_cycles; ///< Dummy cycles to be inserted for memory mapped writes + uint8_t opi_status_read_dummy_cycles; ///< Dummy cycles to be inserted for status reads in OPI mode. + uint8_t * p_autocalibration_preamble_pattern_addr; ///< OctaFlash memory address holding the preamble pattern + ospi_dopi_byte_order_t dopi_byte_order; ///< Byte order on external bus. Only applicable in DOPI mode. + uint16_t ram_chip_select_max_period_setting; ///< Indicates the maximum period that OM_CS0/OM_CS1 are Low in single continuous write/read of OctaRAM. +#if OSPI_CFG_DMAC_SUPPORT_ENABLE + transfer_instance_t const * p_lower_lvl_transfer; ///< DMA Transfer instance used for data transmission +#endif +} ospi_extended_cfg_t; + +/** Instance control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_flash_api_t::open is called */ +typedef struct st_ospi_instance_ctrl +{ + spi_flash_cfg_t const * p_cfg; // Pointer to initial configuration + ospi_device_number_t channel; // Device number to be used for memory device + spi_flash_protocol_t spi_protocol; // Current SPI protocol selected + uint32_t open; // Whether or not driver is open +} ospi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_flash_api_t g_ospi_on_spi_flash; + +/** @endcond */ + +fsp_err_t R_OSPI_Open(spi_flash_ctrl_t * const p_ctrl, spi_flash_cfg_t const * const p_cfg); +fsp_err_t R_OSPI_Close(spi_flash_ctrl_t * const p_ctrl); +fsp_err_t R_OSPI_DirectWrite(spi_flash_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write); +fsp_err_t R_OSPI_DirectRead(spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_OSPI_DirectTransfer(spi_flash_ctrl_t * const p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); +fsp_err_t R_OSPI_SpiProtocolSet(spi_flash_ctrl_t * const p_ctrl, spi_flash_protocol_t spi_protocol); +fsp_err_t R_OSPI_XipEnter(spi_flash_ctrl_t * const p_ctrl); +fsp_err_t R_OSPI_XipExit(spi_flash_ctrl_t * const p_ctrl); +fsp_err_t R_OSPI_Write(spi_flash_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count); +fsp_err_t R_OSPI_Erase(spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); +fsp_err_t R_OSPI_StatusGet(spi_flash_ctrl_t * const p_ctrl, spi_flash_status_t * const p_status); +fsp_err_t R_OSPI_BankSet(spi_flash_ctrl_t * const p_ctrl, uint32_t bank); +fsp_err_t R_OSPI_AutoCalibrate(spi_flash_ctrl_t * const p_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup OSPI) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_pdc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_pdc.h new file mode 100644 index 0000000000..4be3ff8306 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_pdc.h @@ -0,0 +1,135 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup PDC + * @{ + **********************************************************************************************************************/ + +#ifndef R_PDC_H +#define R_PDC_H + +#include "bsp_api.h" +#include "r_capture_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** PDC events */ +typedef enum e_pdc_event +{ + PDC_EVENT_TRANSFER_COMPLETE = 0U, ///< Complete frame transferred by DMAC/DTC + PDC_EVENT_RX_DATA_READY = 0x01U, ///< Receive data ready interrupt + PDC_EVENT_FRAME_END = 0x04U, ///< Frame end interrupt + PDC_EVENT_ERR_OVERRUN = 0x08U, ///< Overrun interrupt + PDC_EVENT_ERR_UNDERRUN = 0x10U, ///< Underrun interrupt + PDC_EVENT_ERR_V_SET = 0x20U, ///< Vertical line setting error interrupt + PDC_EVENT_ERR_H_SET = 0x40U, ///< Horizontal byte number setting error interrupt +} pdc_event_t; + +/** Clock divider applied to PDC clock to provide PCKO output frequency */ +typedef enum e_pdc_clock_division +{ + PDC_CLOCK_DIVISION_2 = 0U, ///< CLK / 2 + PDC_CLOCK_DIVISION_4 = 1U, ///< CLK / 4 + PDC_CLOCK_DIVISION_6 = 2U, ///< CLK / 6 + PDC_CLOCK_DIVISION_8 = 3U, ///< CLK / 8 + PDC_CLOCK_DIVISION_10 = 4U, ///< CLK / 10 + PDC_CLOCK_DIVISION_12 = 5U, ///< CLK / 12 + PDC_CLOCK_DIVISION_14 = 6U, ///< CLK / 14 + PDC_CLOCK_DIVISION_16 = 7U, ///< CLK / 16 +} pdc_clock_division_t; + +/** Endian of captured data */ +typedef enum e_pdc_endian +{ + PDC_ENDIAN_LITTLE = 0U, ///< Data is in little endian format + PDC_ENDIAN_BIG = 1U, ///< Data is in big endian format +} pdc_endian_t; + +/** Polarity of input HSYNC signal */ +typedef enum e_pdc_hsync_polarity +{ + PDC_HSYNC_POLARITY_HIGH = 0U, ///< HSYNC signal is active high + PDC_HSYNC_POLARITY_LOW = 1U, ///< HSYNC signal is active low +} pdc_hsync_polarity_t; + +/** Polarity of input VSYNC signal */ +typedef enum e_pdc_vsync_polarity +{ + PDC_VSYNC_POLARITY_HIGH = 0U, ///< VSYNC signal is active high + PDC_VSYNC_POLARITY_LOW = 1U, ///< VSYNC signal is active low +} pdc_vsync_polarity_t; + +/** Extended configuration structure for PDC. */ +typedef struct st_pdc_extended_cfg +{ + pdc_clock_division_t clock_division; ///< Clock divider + pdc_endian_t endian; ///< Endian of capture data + pdc_hsync_polarity_t hsync_polarity; ///< Polarity of HSYNC input + pdc_vsync_polarity_t vsync_polarity; ///< Polarity of VSYNC input + uint8_t pdc_ipl; ///< PDC interrupt priority + uint8_t transfer_req_ipl; ///< Transfer interrupt priority + IRQn_Type pdc_irq; ///< PDC IRQ number + IRQn_Type transfer_req_irq; ///< Transfer request IRQ number + transfer_instance_t const * p_lower_lvl_transfer; ///< Pointer to the transfer instance the PDC should use +} pdc_extended_cfg_t; + +/** PDC instance control block. DO NOT INITIALIZE. */ +typedef struct st_pdc_instance_ctrl +{ + capture_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t open; // Indicates whether or not the driver is open called. + uint16_t num_blocks; // Number of blocks to be transferred using DMA + uint8_t * p_current_buffer; // Pointer to buffer currently in use + bool transfer_in_progress; // Indicates if a PDC transfer is already in progress + void * p_context; // Placeholder for user data. Passed to the user callback. + void (* p_callback)(capture_callback_args_t * p_args); // Callback provided when a PDC transfer ISR occurs. +} pdc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const capture_api_t g_pdc_on_capture; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_PDC_Open(capture_ctrl_t * const p_ctrl, capture_cfg_t const * const p_cfg); + +fsp_err_t R_PDC_Close(capture_ctrl_t * const p_ctrl); + +fsp_err_t R_PDC_CaptureStart(capture_ctrl_t * const p_ctrl, uint8_t * const p_buffer); + +fsp_err_t R_PDC_StatusGet(capture_ctrl_t * const p_ctrl, capture_status_t * p_status); + +fsp_err_t R_PDC_CallbackSet(capture_ctrl_t * const p_ctrl, + void ( * p_callback)(capture_callback_args_t *), + void * const p_context, + capture_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_PDC_H + +/*******************************************************************************************************************//** + * @} (end defgroup PDC) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_pdm.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_pdm.h new file mode 100644 index 0000000000..4648489878 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_pdm.h @@ -0,0 +1,232 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup PDM + * @{ + **********************************************************************************************************************/ + +#ifndef R_PDM_H +#define R_PDM_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_pdm_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define PDM_NUM_HPF_COEFFICIENT_H 2 ///< Number of high pass filter h coefficients +#define PDM_NUM_COMPENSATION_FILTER_COEFFICIENT_H 11 ///< Number of compensation filter h coefficients +#define PDM_NUM_LPF_FILTER_COEFFICIENT_H1 20 ///< Number of low pass filter h1 coefficients + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** PDM_CLKn's division ratio to core clock. */ +typedef enum e_pdm_clk_div +{ + PDM_CLOCK_DIV_2 = 0x0, ///< 0000b: 1/2 + PDM_CLOCK_DIV_4 = 0x1, ///< 0001b: 1/4 + PDM_CLOCK_DIV_6 = 0x2, ///< 0010b: 1/6 + PDM_CLOCK_DIV_8 = 0x3, ///< 0011b: 1/8 + PDM_CLOCK_DIV_10 = 0x4, ///< 0100b: 1/10 + PDM_CLOCK_DIV_12 = 0x5, ///< 0101b: 1/12 + PDM_CLOCK_DIV_14 = 0x6, ///< 0110b: 1/14 + PDM_CLOCK_DIV_16 = 0x7, ///< 0111b: 1/16 + PDM_CLOCK_DIV_18 = 0x8, ///< 1000b: 1/18 + PDM_CLOCK_DIV_20 = 0x9, ///< 1001b: 1/20 + PDM_CLOCK_DIV_22 = 0xA, ///< 1010b: 1/22 + PDM_CLOCK_DIV_24 = 0xB, ///< 1011b: 1/24 + PDM_CLOCK_DIV_26 = 0xC, ///< 1100b: 1/26 + PDM_CLOCK_DIV_28 = 0xD, ///< 1101b: 1/28 + PDM_CLOCK_DIV_30 = 0xE, ///< 1110b: 1/30 + PDM_CLOCK_DIV_32 = 0xF, ///< 1111b: 1/32 +} pdm_clk_div_t; + +/** Moving average mode for sound detection data. */ +typedef enum e_pdm_moving_average_mode +{ + PDM_MOVING_AVERAGE_MODE_1_ORDER = 0, ///< 1-order + PDM_MOVING_AVERAGE_MODE_2_ORDER = 1, ///< 2-order + PDM_MOVING_AVERAGE_MODE_4_ORDER = 2, ///< 4-order +} pdm_moving_average_mode_t; + +/** Low-pass (half-band decimation) filter input shift setting. */ +typedef enum e_pdm_low_pass_filter_shift +{ + PDM_LPF_RIGHT_SHIFT_0 = 0, ///< No shift + PDM_LPF_RIGHT_SHIFT_1 = 1, ///< 1-bit right shift + PDM_LPF_RIGHT_SHIFT_2 = 2, ///< 2-bit right shift + PDM_LPF_RIGHT_SHIFT_3 = 3, ///< 3-bit right shift +} pdm_low_pass_filter_shift_t; + +/** Compensation filter input shift setting. */ +typedef enum e_pdm_compensation_filter_shift +{ + PDM_COMPENSATION_FILTER_RIGHT_SHIFT_0 = 0, ///< No shift + PDM_COMPENSATION_FILTER_RIGHT_SHIFT_1 = 1, ///< 1-bit right shift + PDM_COMPENSATION_FILTER_RIGHT_SHIFT_2 = 2, ///< 2-bit right shift + PDM_COMPENSATION_FILTER_RIGHT_SHIFT_3 = 3, ///< 3-bit right shift +} pdm_compensation_filter_shift_t; + +/** High-pass filter input shift setting. */ +typedef enum e_pdm_high_pass_filter_shift +{ + PDM_HPF_RIGHT_SHIFT_0 = 0, ///< No shift + PDM_HPF_RIGHT_SHIFT_1 = 1, ///< 1-bit right shift + PDM_HPF_RIGHT_SHIFT_2 = 2, ///< 2-bit right shift + PDM_HPF_RIGHT_SHIFT_3 = 3, ///< 3-bit right shift +} pdm_high_pass_filter_shift_t; + +/** Sinc filter mode setting. */ +typedef enum e_pdm_sinc_filter_mode +{ + PDM_SINC_FILTER_MODE_1 = 1, ///< 1-order + PDM_SINC_FILTER_MODE_2 = 2, ///< 2-order + PDM_SINC_FILTER_MODE_3 = 3, ///< 3-order + PDM_SINC_FILTER_MODE_4 = 4, ///< 4-order +} pdm_sinc_filter_mode_t; + +/** Data reception interrupt threshold. */ +typedef enum e_pdm_interrupt_threshold +{ + PDM_INTERRUPT_THRESHOLD_1 = 0, ///< 000b: Output interrupt when receiving 1 or more data + PDM_INTERRUPT_THRESHOLD_2 = 1, ///< 001b: Output interrupt when receiving 2 or more data + PDM_INTERRUPT_THRESHOLD_4 = 2, ///< 010b: Output interrupt when receiving 4 or more data + PDM_INTERRUPT_THRESHOLD_8 = 3, ///< 011b: Output interrupt when receiving 8 or more data + PDM_INTERRUPT_THRESHOLD_16 = 4, ///< 100b: Output interrupt when receiving 16 or more data +} pdm_interrupt_threshold_t; + +/** Short circuit detection enable setting. */ +typedef enum e_pdm_short_circuit_enable +{ + PDM_SHORT_CIRCUIT_DISABLED = 0, ///< Short circuit disabled + PDM_SHORT_CIRCUIT_ENABLED = (1 << R_PDM_CH_PDSDCR_SCDE_Pos), ///< Short circuit enabled +} pdm_short_circuit_enable_t; + +/** Overvoltage lower limit enable setting. */ +typedef enum e_pdm_overvoltage_lower_limit_enable +{ + PDM_OVERVOLTAGE_LOWER_LIMIT_DISABLED = 0, ///< Overvoltage lower limit disabled + PDM_OVERVOLTAGE_LOWER_LIMIT_ENABLED = (1 << R_PDM_CH_PDSDCR_OVLDE_Pos), ///< Overvoltage lower limit enabled +} pdm_overvoltage_lower_limit_enable_t; + +/** Overvoltage upper limit enable setting. */ +typedef enum e_pdm_overvoltage_upper_limit_enable +{ + PDM_OVERVOLTAGE_UPPER_LIMIT_DISABLED = 0, ///< Overvoltage upper limit disabled + PDM_OVERVOLTAGE_UPPER_LIMIT_ENABLED = (1 << R_PDM_CH_PDSDCR_OVUDE_Pos), ///< Overvoltage upper limit enabled +} pdm_overvoltage_upper_limit_enable_t; + +/** Buffer overwrite detection enable setting. */ +typedef enum e_pdm_buffer_overwrite_detection_enable +{ + PDM_BUFFER_OVERWRITE_DETECTION_DISABLED = 0, ///< Buffer overwrite detection disabled + PDM_BUFFER_OVERWRITE_DETECTION_ENABLED = (1 << R_PDM_CH_PDSDCR_BFOWDE_Pos), ///< Buffer overwrite detection enabled +} pdm_buffer_overwrite_detection_enable_t; + +/** Channel instance control block. DO NOT INITIALIZE. Initialization occurs when @ref pdm_api_t::open is called. */ +typedef struct st_pdm_instance_ctrl +{ + uint32_t open; // Whether or not this control block is initialized + pdm_cfg_t const * p_cfg; // Initial configurations + R_PDM_CH_Type * p_reg; // Pointer to channel-specific PDM registers + + /* Data reception */ + void * p_rx_dest; // Destination buffer pointer used read data from PDM FIFO + uint32_t rx_dest_samples; // Size of destination buffer + void * p_read; // Read pointer for p_rx_dest, determines where to store the next sample (block of samples for DMA) + uint32_t rx_int_count; // Byte count for processing data in the data interrupt + uint32_t rx_int_count_max; // Max byte count to receive at a time + + /* Pointer to callback and optional working memory */ + void (* p_callback)(pdm_callback_args_t *); + pdm_callback_args_t * p_callback_memory; + void * p_context; // User defined context passed into callback function +} pdm_instance_ctrl_t; + +/** PDM configuration extension. This extension is optional. */ +typedef struct st_pdm_extended_cfg +{ + pdm_clk_div_t clock_div; ///< PDM_CLKn's division ratio to core clock + + /** Function Settings. */ + pdm_short_circuit_enable_t short_circuit_detection_enable; ///< Short circuit detection enable + pdm_overvoltage_lower_limit_enable_t over_voltage_lower_limit_detection_enable; ///< Overvoltage detection lower limit enable + pdm_overvoltage_upper_limit_enable_t over_voltage_upper_limit_detection_enable; ///< Overvoltage detection upper limit enable + pdm_buffer_overwrite_detection_enable_t buffer_overwrite_detection_enable; ///< Buffer overwrite detection enable + + /** Filter Settings. */ + pdm_moving_average_mode_t moving_average_mode; ///< Moving average mode f or sound detection data + pdm_low_pass_filter_shift_t low_pass_filter_shift; ///< Low-pass (half -band decimation) filter input shift setting + pdm_compensation_filter_shift_t compensation_filter_shift; ///< Compensation filter input shift setting + pdm_high_pass_filter_shift_t high_pass_filter_shift; ///< High-pass filter input shift setting + pdm_sinc_filter_mode_t sinc_filter_mode; ///< Sinc filter mode setting + uint8_t sincrng; ///< Sinc filter output valid range + uint8_t sincdec; ///< Sinc filter decimation ratio + uint16_t hpf_coefficient_s0; ///< High-pass filter coefficient s0 (16-bit signed fixed point data) + uint16_t hpf_coefficient_k1; ///< High-pass filter coefficient k1 (16-bit signed fixed point data) + uint16_t hpf_coefficient_h[PDM_NUM_HPF_COEFFICIENT_H]; ///< High-pass filter coefficient h(p) (16-bit signed fixed point data) + uint16_t compensation_filter_coefficient_h[PDM_NUM_COMPENSATION_FILTER_COEFFICIENT_H]; ///< High-pass filter coefficient h(p) (13-bit signed fixed point data) + uint16_t lpf_coefficient_h0; ///< Low-pass (half-band decimation) filter coefficient h0 (13-bit signed fixed point data) + uint16_t lpf_coefficient_h1[PDM_NUM_LPF_FILTER_COEFFICIENT_H1]; ///< Low-pass (half-band decimation) filter coefficient h1 (13-bit signed fixed point data) + + /** Data Reception. */ + pdm_interrupt_threshold_t interrupt_threshold; ///< Data reception interrupt threshold + + /** Short-Circuit Detection. */ + uint16_t short_circuit_count_h; ///< Short circuit detection High Continuous detection count + uint16_t short_circuit_count_l; ///< Continuous detection count + + /** Overvoltage Detection. */ + uint32_t overvoltage_detection_lower_limit; ///< Overvoltage detection lower limit (20-bit signed fixed point data) + uint32_t overvoltage_detection_upper_limit; ///< Overvoltage detection upper limit (20-bit signed fixed point data) +} pdm_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +extern const pdm_api_t g_pdm_on_pdm; + +/** @endcond */ + +/********************************************************************************************************************** + * Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_PDM_Open(pdm_ctrl_t * const p_ctrl, pdm_cfg_t const * const p_cfg); +fsp_err_t R_PDM_Start(pdm_ctrl_t * const p_ctrl, + void * const p_buffer, + size_t const buffer_size, + uint32_t const number_of_data_to_callback); +fsp_err_t R_PDM_Stop(pdm_ctrl_t * const p_ctrl); +fsp_err_t R_PDM_SoundDetectionEnable(pdm_ctrl_t * const p_ctrl, pdm_sound_detection_setting_t sound_detection_setting); +fsp_err_t R_PDM_SoundDetectionDisable(pdm_ctrl_t * const p_ctrl); +fsp_err_t R_PDM_Read(pdm_ctrl_t * const p_ctrl, void * const p_dest, uint32_t const bytes); +fsp_err_t R_PDM_StatusGet(pdm_ctrl_t * const p_ctrl, pdm_status_t * const p_status); +fsp_err_t R_PDM_Close(pdm_ctrl_t * const p_ctrl); +fsp_err_t R_PDM_CallbackSet(pdm_ctrl_t * const p_ctrl, + void ( * p_callback)(pdm_callback_args_t *), + void * const p_context, + pdm_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_PDM_H + +/*******************************************************************************************************************//** + * @} (end defgroup PDM) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_poeg.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_poeg.h new file mode 100644 index 0000000000..9275b9299c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_poeg.h @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_POEG_H +#define R_POEG_H + +/*******************************************************************************************************************//** + * @addtogroup POEG + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_poeg_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref poeg_api_t::open is called. */ +typedef struct st_poeg_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + const poeg_cfg_t * p_cfg; // Pointer to initial configurations + R_GPT_POEG0_Type * p_reg; // Base register for this channel + + void (* p_callback)(poeg_callback_args_t *); // Pointer to callback + poeg_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void * p_context; // Pointer to context to be passed into callback function +} poeg_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const poeg_api_t g_poeg_on_poeg; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_POEG_Open(poeg_ctrl_t * const p_ctrl, poeg_cfg_t const * const p_cfg); +fsp_err_t R_POEG_StatusGet(poeg_ctrl_t * const p_ctrl, poeg_status_t * const p_status); +fsp_err_t R_POEG_CallbackSet(poeg_ctrl_t * const p_ctrl, + void ( * p_callback)(poeg_callback_args_t *), + void * const p_context, + poeg_callback_args_t * const p_callback_memory); +fsp_err_t R_POEG_OutputDisable(poeg_ctrl_t * const p_ctrl); +fsp_err_t R_POEG_Reset(poeg_ctrl_t * const p_ctrl); +fsp_err_t R_POEG_Close(poeg_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup POEG) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ptp.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ptp.h new file mode 100644 index 0000000000..59bbd82ce5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ptp.h @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_PTP_H +#define R_PTP_H + +/*******************************************************************************************************************//** + * @addtogroup PTP + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ptp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/************************************************************************************************* + * Type defines for the SPI interface API + *************************************************************************************************/ + +/** PTP instance control block. */ +typedef struct +{ + uint32_t open; ///< Marks if the instance has been opened. + uint32_t tx_buffer_write_index; ///< Index into the descriptor list to write the next packet. + uint32_t tx_buffer_complete_index; ///< Index into the descriptor list of the last transmitted packet. + uint32_t rx_buffer_index; ///< Index into the descriptor of the last received packet. + uint32_t tslatr; ///< Keep track of whether tslatr was set. + ptp_cfg_t const * p_cfg; ///< Pointer to the configuration structure. +} ptp_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ptp_api_t g_ptp_api; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_PTP_Open(ptp_ctrl_t * const p_ctrl, ptp_cfg_t const * const p_cfg); +fsp_err_t R_PTP_MacAddrSet(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_mac_addr); +fsp_err_t R_PTP_IpAddrSet(ptp_ctrl_t * const p_ctrl, uint32_t ip_addr); +fsp_err_t R_PTP_LocalClockIdSet(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_clock_id); +fsp_err_t R_PTP_MasterClockIdSet(ptp_ctrl_t * const p_ctrl, uint8_t const * const p_clock_id, uint16_t port_id); +fsp_err_t R_PTP_MessageFlagsSet(ptp_ctrl_t * const p_ctrl, ptp_message_type_t message_type, ptp_message_flags_t flags); +fsp_err_t R_PTP_CurrentUtcOffsetSet(ptp_ctrl_t * const p_ctrl, uint16_t offset); +fsp_err_t R_PTP_PortStateSet(ptp_ctrl_t * const p_ctrl, uint32_t state); +fsp_err_t R_PTP_MessageSend(ptp_ctrl_t * const p_ctrl, + ptp_message_t const * const p_message, + uint8_t const * const p_tlv_data, + uint16_t tlv_data_size); +fsp_err_t R_PTP_LocalClockValueSet(ptp_ctrl_t * const p_ctrl, ptp_time_t const * const p_time); +fsp_err_t R_PTP_LocalClockValueGet(ptp_ctrl_t * const p_ctrl, ptp_time_t * const p_time); +fsp_err_t R_PTP_PulseTimerCommonConfig(ptp_ctrl_t * const p_ctrl, ptp_pulse_timer_common_cfg_t * const p_timer_cfg); +fsp_err_t R_PTP_PulseTimerEnable(ptp_ctrl_t * const p_ctrl, uint32_t channel, + ptp_pulse_timer_cfg_t * const p_timer_cfg); +fsp_err_t R_PTP_PulseTimerDisable(ptp_ctrl_t * const p_ctrl, uint32_t channel); +fsp_err_t R_PTP_Close(ptp_ctrl_t * const p_ctrl); + +fsp_err_t R_PTP_BestMasterClock(ptp_message_t const * const p_announce1, + ptp_message_t const * const p_announce2, + int8_t * const p_comparison); + +/*******************************************************************************************************************//** + * @} (end ingroup PTP) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_qspi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_qspi.h new file mode 100644 index 0000000000..79c3971424 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_qspi.h @@ -0,0 +1,149 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup QSPI + * @{ + **********************************************************************************************************************/ + +#ifndef R_QSPI_H +#define R_QSPI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include +#include "r_qspi_cfg.h" +#include "r_spi_flash_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define QSPI_DEVICE_START_ADDRESS (0x60000000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Minimum QSPCLK cycles for QSSL to remain high between operations. */ +typedef enum e_qspi_qssl_min_high_level +{ + QSPI_QSSL_MIN_HIGH_LEVEL_1_QSPCLK, ///< QSSL deselected for at least 1 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_2_QSPCLK, ///< QSSL deselected for at least 2 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_3_QSPCLK, ///< QSSL deselected for at least 3 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_4_QSPCLK, ///< QSSL deselected for at least 4 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_5_QSPCLK, ///< QSSL deselected for at least 5 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_6_QSPCLK, ///< QSSL deselected for at least 6 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_7_QSPCLK, ///< QSSL deselected for at least 7 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_8_QSPCLK, ///< QSSL deselected for at least 8 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_9_QSPCLK, ///< QSSL deselected for at least 9 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_10_QSPCLK, ///< QSSL deselected for at least 10 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_11_QSPCLK, ///< QSSL deselected for at least 11 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_12_QSPCLK, ///< QSSL deselected for at least 12 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_13_QSPCLK, ///< QSSL deselected for at least 13 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_14_QSPCLK, ///< QSSL deselected for at least 14 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_15_QSPCLK, ///< QSSL deselected for at least 15 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_16_QSPCLK, ///< QSSL deselected for at least 16 QSPCLK +} qspi_qssl_min_high_level_t; + +/* QSPCLK divider. */ +typedef enum e_qspi_qspclk_div +{ + QSPI_QSPCLK_DIV_2 = 0x0, ///< QSPCLK = PCLK / 2 + QSPI_QSPCLK_DIV_3 = 0x1, ///< QSPCLK = PCLK / 3 + QSPI_QSPCLK_DIV_4 = 0x2, ///< QSPCLK = PCLK / 4 + QSPI_QSPCLK_DIV_5 = 0x3, ///< QSPCLK = PCLK / 5 + QSPI_QSPCLK_DIV_6 = 0x4, ///< QSPCLK = PCLK / 6 + QSPI_QSPCLK_DIV_7 = 0x5, ///< QSPCLK = PCLK / 7 + QSPI_QSPCLK_DIV_8 = 0x6, ///< QSPCLK = PCLK / 8 + QSPI_QSPCLK_DIV_9 = 0x7, ///< QSPCLK = PCLK / 9 + QSPI_QSPCLK_DIV_10 = 0x8, ///< QSPCLK = PCLK / 10 + QSPI_QSPCLK_DIV_11 = 0x9, ///< QSPCLK = PCLK / 11 + QSPI_QSPCLK_DIV_12 = 0xA, ///< QSPCLK = PCLK / 12 + QSPI_QSPCLK_DIV_13 = 0xB, ///< QSPCLK = PCLK / 13 + QSPI_QSPCLK_DIV_14 = 0xC, ///< QSPCLK = PCLK / 14 + QSPI_QSPCLK_DIV_15 = 0xD, ///< QSPCLK = PCLK / 15 + QSPI_QSPCLK_DIV_16 = 0xE, ///< QSPCLK = PCLK / 16 + QSPI_QSPCLK_DIV_17 = 0xF, ///< QSPCLK = PCLK / 17 + QSPI_QSPCLK_DIV_18 = 0x10, ///< QSPCLK = PCLK / 18 + QSPI_QSPCLK_DIV_20 = 0x11, ///< QSPCLK = PCLK / 20 + QSPI_QSPCLK_DIV_22 = 0x12, ///< QSPCLK = PCLK / 22 + QSPI_QSPCLK_DIV_24 = 0x13, ///< QSPCLK = PCLK / 24 + QSPI_QSPCLK_DIV_26 = 0x14, ///< QSPCLK = PCLK / 26 + QSPI_QSPCLK_DIV_28 = 0x15, ///< QSPCLK = PCLK / 28 + QSPI_QSPCLK_DIV_30 = 0x16, ///< QSPCLK = PCLK / 30 + QSPI_QSPCLK_DIV_32 = 0x17, ///< QSPCLK = PCLK / 32 + QSPI_QSPCLK_DIV_34 = 0x18, ///< QSPCLK = PCLK / 34 + QSPI_QSPCLK_DIV_36 = 0x19, ///< QSPCLK = PCLK / 36 + QSPI_QSPCLK_DIV_38 = 0x1A, ///< QSPCLK = PCLK / 38 + QSPI_QSPCLK_DIV_40 = 0x1B, ///< QSPCLK = PCLK / 40 + QSPI_QSPCLK_DIV_42 = 0x1C, ///< QSPCLK = PCLK / 42 + QSPI_QSPCLK_DIV_44 = 0x1D, ///< QSPCLK = PCLK / 44 + QSPI_QSPCLK_DIV_46 = 0x1E, ///< QSPCLK = PCLK / 46 + QSPI_QSPCLK_DIV_48 = 0x1F, ///< QSPCLK = PCLK / 48 +} qspi_qspclk_div_t; + +/* Extended configuration. */ +typedef struct st_qspi_extended_cfg +{ + qspi_qssl_min_high_level_t min_qssl_deselect_cycles; ///< Minimum QSSL deselect time + qspi_qspclk_div_t qspclk_div; ///< QSPCLK divider +} qspi_extended_cfg_t; + +/** Instance control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_flash_api_t::open is called */ +typedef struct st_qspi_instance_ctrl +{ + spi_flash_cfg_t const * p_cfg; // Pointer to initial configuration + spi_flash_data_lines_t data_lines; // Data lines + uint32_t total_size_bytes; // Total size of the flash in bytes + uint32_t open; // Whether or not driver is open +} qspi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_flash_api_t g_qspi_on_spi_flash; + +/** @endcond */ + +fsp_err_t R_QSPI_Open(spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg); +fsp_err_t R_QSPI_Close(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_QSPI_DirectWrite(spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write); +fsp_err_t R_QSPI_DirectRead(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_QSPI_SpiProtocolSet(spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol); +fsp_err_t R_QSPI_XipEnter(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_QSPI_XipExit(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_QSPI_Write(spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count); +fsp_err_t R_QSPI_Erase(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); +fsp_err_t R_QSPI_StatusGet(spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status); +fsp_err_t R_QSPI_BankSet(spi_flash_ctrl_t * p_ctrl, uint32_t bank); +fsp_err_t R_QSPI_DirectTransfer(spi_flash_ctrl_t * p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); +fsp_err_t R_QSPI_AutoCalibrate(spi_flash_ctrl_t * p_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup QSPI) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rmac.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rmac.h new file mode 100644 index 0000000000..e18b60a2b3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rmac.h @@ -0,0 +1,185 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RMAC_H +#define R_RMAC_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ether_api.h" +#include "r_layer3_switch.h" + +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum e_ether_previous_link_status +{ + ETHER_PREVIOUS_LINK_STATUS_DOWN = 0, ///< Previous link status is down + ETHER_PREVIOUS_LINK_STATUS_UP = 1, ///< Previous link status is up +} ether_previous_link_status_t; + +typedef enum e_ether_link_change +{ + ETHER_LINK_CHANGE_NO_CHANGE = 0, ///< Link status is no change + ETHER_LINK_CHANGE_LINK_DOWN = 1, ///< Link status changes to down + ETHER_LINK_CHANGE_LINK_UP = 2, ///< Link status changes to up +} ether_link_change_t; + +typedef enum e_ether_link_establish_status +{ + ETHER_LINK_ESTABLISH_STATUS_DOWN = 0, ///< Link establish status is down + ETHER_LINK_ESTABLISH_STATUS_UP = 1, ///< Link establish status is up +} ether_link_establish_status_t; + +/** Information of a descriptor queue. */ +typedef struct st_rmac_queue_info +{ + layer3_switch_descriptor_queue_cfg_t queue_cfg; ///< Queue configuration. + uint32_t index; ///< Queue index. +} rmac_queue_info_t; + +/** Write configuration. */ +typedef struct st_rmac_write_cfg +{ + uint32_t tx_timestamp_enable : 1; ///< Enable to get TX timestamp. + uint32_t reserved : 31; +} rmac_write_cfg_t; + +/** Timestamp. */ +typedef struct st_rmac_timestamp +{ + uint16_t sec_upper; ///< Timestamp second (Upper 16 bit). + uint32_t sec_lower; ///< Timestamp second (Lower 32 bit). + uint32_t ns; ///< Timestamp nanosecond. +} rmac_timestamp_t; + +/** Node to manage buffer. */ +typedef struct st_rmac_buffer_node +{ + void * p_buffer; ///< Pointer to the buffer. + uint32_t size; ///< Buffer size. +#if LAYER3_SWITCH_CFG_GPTP_ENABLE + rmac_timestamp_t timestamp; ///< RX timestamp value. +#endif + struct st_rmac_buffer_node * p_next; ///< Pointer to the next node. +} rmac_buffer_node_t; + +/** Queue of internal buffers. */ +typedef struct st_rmac_buffer_queue +{ + rmac_buffer_node_t * p_head; ///< Pointer to the head of the queue. + rmac_buffer_node_t * p_tail; ///< Pointer to the tail of the queue. +} rmac_buffer_queue_t; + +/* Extended configuration. */ +typedef struct st_rmac_extended_cfg +{ + ether_switch_instance_t const * p_ether_switch; ///< Pointer to ETHER_SWITCH instance. + + uint32_t tx_queue_num; ///< Number of TX descriptor queues. + uint32_t rx_queue_num; ///< Number of RX descriptor queues. + + rmac_queue_info_t * p_ts_queue; ///< Configuration of TS queue. + rmac_queue_info_t * p_tx_queue_list; ///< TX queue list. + rmac_queue_info_t * p_rx_queue_list; ///< RX queue list. + + IRQn_Type rmpi_irq; ///< Magic packet detection interrupt number. + uint32_t rmpi_ipl; ///< Magic packet detection interrupt priority. + rmac_buffer_node_t * p_buffer_node_list; ///< List of buffer nodes for managing TX/RX buffers. + uint32_t buffer_node_num; ///< Length of buffer nodes list. +} rmac_extended_cfg_t; + +/** Instance control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_flash_api_t::open is called */ +typedef struct st_rmac_instance_ctrl +{ + uint32_t open; // Whether or not driver is open + ether_cfg_t const * p_cfg; // Pointer to initial configuration + + bool is_lost_rx_packet; + + /* IP dependent members. */ + R_ETHA0_Type * p_reg_etha; + R_RMAC0_Type * p_reg_rmac; + + /* RX statuses. */ + uint32_t read_queue_index; ///< RX queue that used for next BufferRelease API. + uint32_t rx_running_queue_index; ///< Whether a RX queue is running or not. + rmac_buffer_queue_t rx_completed_buffer_queue; ///< RX buffers that have completed reception. + rmac_buffer_queue_t rx_unreleased_buffer_queue; ///< RX buffers that have been read but not yet released. + rmac_buffer_queue_t rx_empty_buffer_queue; ///< RX Buffers that have no data. + uint32_t rx_initialized_buffer_num; ///< RX buffer num of initialized. This is used in RxBufferUpdate API. + + /* TX statuses. */ + uint32_t write_queue_index; ///< TX queue that used for next Write API. + uint32_t tx_running_queue_index; ///< Index of the queue that is running now. + void * p_last_sent_buffer; ///< Pointer to the last sent TX buffer. + rmac_buffer_queue_t tx_pending_buffer_queue; ///< Delayed TX buffers. + rmac_buffer_queue_t tx_empty_buffer_queue; ///< TX Buffers that have no data. + uint32_t write_descriptor_count; ///< Count of descriptor that already write in active queue. + + rmac_buffer_queue_t buffer_node_pool; ///< Buffer nodes pool. + + /* Timestamp features. */ + rmac_timestamp_t * p_rx_timestamp; ///< RX timestamp pointer. + rmac_timestamp_t tx_timestamp; ///< TX timestamp. + uint32_t tx_timestamp_seq_num; ///< Sequence number of TX timestamp. + rmac_write_cfg_t write_cfg; ///< Configuration of transmission. + + /* Status of ethernet driver. */ + ether_previous_link_status_t previous_link_status; ///< Previous link status + ether_link_change_t link_change; ///< Status of link change + ether_link_establish_status_t link_establish_status; ///< Current Link status + ether_wake_on_lan_t wake_on_lan; ///< Wake on LAN mode. + + /* Pointer to callback and optional working memory */ + void (* p_callback)(ether_callback_args_t *); + ether_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} rmac_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ether_api_t g_ether_on_rmac; + +/** @endcond */ + +fsp_err_t R_RMAC_Open(ether_ctrl_t * p_ctrl, ether_cfg_t const * const p_cfg); +fsp_err_t R_RMAC_Close(ether_ctrl_t * p_ctrl); +fsp_err_t R_RMAC_BufferRelease(ether_ctrl_t * const p_ctrl); +fsp_err_t R_RMAC_RxBufferUpdate(ether_ctrl_t * const p_ctrl, void * const p_buffer); +fsp_err_t R_RMAC_LinkProcess(ether_ctrl_t * const p_ctrl); +fsp_err_t R_RMAC_WakeOnLANEnable(ether_ctrl_t * const p_ctrl); +fsp_err_t R_RMAC_Read(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t * const length_bytes); +fsp_err_t R_RMAC_Write(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length); +fsp_err_t R_RMAC_TxStatusGet(ether_ctrl_t * const p_ctrl, void * const p_buffer_address); +fsp_err_t R_RMAC_CallbackSet(ether_ctrl_t * const p_api_ctrl, + void ( * p_callback)(ether_callback_args_t *), + void * const p_context, + ether_callback_args_t * const p_callback_memory); +fsp_err_t R_RMAC_SetWriteConfig(ether_ctrl_t * const p_ctrl, rmac_write_cfg_t * const p_write_cfg); +fsp_err_t R_RMAC_GetTxTimestamp(ether_ctrl_t * const p_ctrl, rmac_timestamp_t * const p_timestamp); +fsp_err_t R_RMAC_GetRxTimestamp(ether_ctrl_t * const p_ctrl, rmac_timestamp_t * const p_timestamp); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_RMAC_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rmac_phy.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rmac_phy.h new file mode 100644 index 0000000000..9c417ef64e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rmac_phy.h @@ -0,0 +1,130 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup RMAC_PHY + * @{ + **********************************************************************************************************************/ + +#ifndef R_RMAC_PHY_H +#define R_RMAC_PHY_H + +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rmac_phy_cfg.h" +#include "r_ether_phy_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Initialization state for read/write */ +typedef enum e_rmac_phy_interface_status +{ + RMAC_PHY_INTERFACE_STATUS_UNINITIALIZED = 0, ///< ETHER PHY interface is uninitialized + RMAC_PHY_INTERFACE_STATUS_INITIALIZED = 1 ///< ETHER PHY interface is initialized +} rmac_phy_interface_status_t; + +typedef enum e_rmac_phy_frame_format +{ + RMAC_PHY_FRAME_FORMAT_MDIO = 0, ///< Normal management frame format defined in clause 22. + RMAC_PHY_FRAME_FORMAT_EMDIO = 1 ///< Extension management frame format defined in clause 45. +} rmac_phy_frame_format_t; + +/** RMAC PHY control block. DO NOT INITIALIZE. Initialization occurs when @ref ether_phy_api_t::open is called. */ +typedef struct st_rmac_phy_instance_ctrl +{ + uint32_t open; ///< Used to determine if the channel is configured + ether_phy_cfg_t const * p_ether_phy_cfg; ///< Pointer to initial configurations. + R_RMAC0_Type * p_reg_rmac; ///< Pointer to RMAC peripheral registers. + uint32_t local_advertise; ///< Capabilities bitmap for local advertising. + rmac_phy_interface_status_t interface_status; ///< Initialized status of ETHER PHY interface. + uint8_t phy_lsi_cfg_index; ///< Index of the PHY LSI that is currently the target of operation + void (* p_callback)(ether_phy_callback_args_t * p_args); ///< Callback provided when an ISR occurs. + void * p_context; + ether_phy_callback_args_t * p_callback_memory; +} rmac_phy_instance_ctrl_t; + +/** RMAC PHY extended configuration. */ +typedef struct st_rmac_phy_extended_cfg +{ + void (* p_target_init)(rmac_phy_instance_ctrl_t * p_instance_ctrl); ///< Pointer to callback that is called to initialize the target. + bool (* p_target_link_partner_ability_get)(rmac_phy_instance_ctrl_t * p_instance_ctrl, uint32_t line_speed_duplex); ///< Pointer to callback that is called to get the link partner ability. + rmac_phy_frame_format_t frame_format; ///< Whether the management frame format is MDIO or eMDIO + uint32_t mdc_clock_rate; ///< MDC frequency division + uint8_t mdio_hold_time; ///< MDIO hold time adjustment + uint8_t mdio_capture_time; ///< MDIO capture time adjustment + ether_phy_lsi_cfg_t const * p_phy_lsi_cfg_list[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< Pointer list of PHY LSI configurations. + uint8_t default_phy_lsi_cfg_index; ///< Index of the default PHY LSI condiguration. + bool frame_preemption_enable; + uint32_t frame_preemption_verification_interval; ///< Interval for sending verify frame [ms]. + IRQn_Type easi_irq[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< EASI interrupt number + uint32_t easi_ipl[BSP_FEATURE_ETHER_NUM_CHANNELS]; ///< EASI interrupt priority + void (* p_callback)(ether_phy_callback_args_t * p_args); ///< Callback provided when an ISR occurs. + void * p_context; ///< Placeholder for user data. +} rmac_phy_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ether_phy_api_t g_ether_phy_on_rmac_phy; + +/** @endcond */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + ***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_Open(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg); + +fsp_err_t R_RMAC_PHY_Close(ether_phy_ctrl_t * const p_ctrl); + +fsp_err_t R_RMAC_PHY_ChipInit(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg); + +fsp_err_t R_RMAC_PHY_Read(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data); + +fsp_err_t R_RMAC_PHY_Write(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data); + +fsp_err_t R_RMAC_PHY_StartAutoNegotiate(ether_phy_ctrl_t * const p_ctrl); + +fsp_err_t R_RMAC_PHY_LinkPartnerAbilityGet(ether_phy_ctrl_t * const p_ctrl, + uint32_t * const p_line_speed_duplex, + uint32_t * const p_local_pause, + uint32_t * const p_partner_pause); + +fsp_err_t R_RMAC_PHY_LinkStatusGet(ether_phy_ctrl_t * const p_ctrl); + +fsp_err_t R_RMAC_PHY_ChipSelect(ether_phy_ctrl_t * const p_ctrl, uint8_t port); + +fsp_err_t R_RMAC_PHY_CallbackSet(ether_phy_ctrl_t * const p_ctrl, + void ( * p_callback)(ether_phy_callback_args_t *), + void * const p_context, + ether_phy_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end addtogroup RMAC_PHY) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_RMAC_PHY_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rtc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rtc.h new file mode 100644 index 0000000000..cba69ddb49 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_rtc.h @@ -0,0 +1,93 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RTC_H +#define R_RTC_H + +/*******************************************************************************************************************//** + * @addtogroup RTC RTC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_rtc_cfg.h" +#include "r_rtc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Counting mode */ +#define RTC_CALENDAR_MODE (0) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** RTC extend configuration */ +typedef struct st_rtc_extended_cfg +{ + uint8_t alarm1_ipl; ///< Alarm 1 interrupt priority + IRQn_Type alarm1_irq; ///< Alarm 1 interrupt vector +} rtc_extended_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref rtc_api_t::open is called */ +typedef struct st_rtc_ctrl +{ + uint32_t open; ///< Whether or not driver is open + const rtc_cfg_t * p_cfg; ///< Pointer to initial configurations + volatile bool carry_isr_triggered; ///< Was the carry isr triggered + + void (* p_callback)(rtc_callback_args_t *); // Pointer to callback that is called when a rtc_event_t occurs. + rtc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + void * p_context; // Pointer to context to be passed into callback function +} rtc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const rtc_api_t g_rtc_on_rtc; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_RTC_Open(rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); +fsp_err_t R_RTC_Close(rtc_ctrl_t * const p_ctrl); +fsp_err_t R_RTC_ClockSourceSet(rtc_ctrl_t * const p_ctrl); +fsp_err_t R_RTC_CalendarTimeSet(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); +fsp_err_t R_RTC_CalendarTimeGet(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); +fsp_err_t R_RTC_CalendarAlarmSet(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); +fsp_err_t R_RTC_CalendarAlarmGet(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); +fsp_err_t R_RTC_PeriodicIrqRateSet(rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_select_t const rate); +fsp_err_t R_RTC_ErrorAdjustmentSet(rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg); +fsp_err_t R_RTC_InfoGet(rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info); +fsp_err_t R_RTC_CallbackSet(rtc_ctrl_t * const p_ctrl, + void ( * p_callback)(rtc_callback_args_t *), + void * const p_context, + rtc_callback_args_t * const p_callback_memory); +fsp_err_t R_RTC_TimeCaptureSet(rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture); +fsp_err_t R_RTC_TimeCaptureGet(rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_RTC_H + +/*******************************************************************************************************************//** + * @} (end addtogroup RTC) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_i2c.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_i2c.h new file mode 100644 index 0000000000..84eb1e9249 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_i2c.h @@ -0,0 +1,120 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup SAU_I2C + * @{ + **********************************************************************************************************************/ + +#ifndef R_SAU_I2C_H +#define R_SAU_I2C_H + +#include "bsp_api.h" +#include "r_sau_i2c_cfg.h" +#include "r_i2c_master_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Operation clock */ +typedef enum e_sau_i2c_operation_clock +{ + SAU_I2C_MASTER_OPERATION_CLOCK_CK0 = 0, ///< Operating clock select CK0 + SAU_I2C_MASTER_OPERATION_CLOCK_CK1 = 1, ///< Operating clock select CK1 +} sau_i2c_operation_clock_t; + +/** I2C clock settings */ +typedef struct st_sau_i2c_clock_settings +{ + uint8_t stclk; ///< Bit rate register settings + sau_i2c_operation_clock_t operation_clock; ///< I2C operating clock select +} sau_i2c_clock_settings_t; + +/** I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_sau_i2c_instance_ctrl +{ + i2c_master_cfg_t const * p_cfg; ///< Pointer to the configuration structure + uint32_t open; ///< Flag to determine if the device is open + R_SAU0_Type * p_reg; ///< Base register for this channel + + /* Current transfer information. */ + uint8_t * p_buff; ///< Holds the data associated with the transfer + uint32_t total; ///< Holds the total number of data bytes to transfer + uint32_t loaded; ///< Tracks the number of data bytes written to the register + volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt + + volatile bool read; ///< Holds the direction of the data byte transfer + volatile bool restart; ///< Holds whether or not the restart should be issued when done + volatile bool restarted; ///< Tracks whether or not a restart was issued during the previous transfer + volatile bool do_dummy_read; ///< Tracks whether a dummy read is issued on the first RX + uint8_t slave; ///< The address of the slave device + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + + /* Pointer to context to be passed into callback function */ + void * p_context; +} sau_i2c_instance_ctrl_t; + +/** SAU I2C extended configuration */ +typedef struct st_sau_i2c_extended_cfg +{ + sau_i2c_clock_settings_t clock_settings; ///< I2C clock settings + uint8_t delay_time; ///< The delay time of the slave device + uint8_t i2c_unit; ///< The SAU unit corresponding to the selected channel +} sau_i2c_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_master_api_t const g_i2c_master_on_sau; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_Open(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg); +fsp_err_t R_SAU_I2C_Close(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_I2C_Read(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart); +fsp_err_t R_SAU_I2C_Write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart); +fsp_err_t R_SAU_I2C_Abort(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_I2C_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); +fsp_err_t R_SAU_I2C_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory); +fsp_err_t R_SAU_I2C_StatusGet(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); +fsp_err_t R_SAU_I2C_Start(sau_i2c_instance_ctrl_t * const p_ctrl); +fsp_err_t R_SAU_I2C_Stop(sau_i2c_instance_ctrl_t * const p_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup SAU_I2C) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_lin.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_lin.h new file mode 100644 index 0000000000..03dfba636e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_lin.h @@ -0,0 +1,125 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup SAU_LIN + * @{ + **********************************************************************************************************************/ + +#ifndef R_SAU_LIN_H +#define R_SAU_LIN_H + +#include "r_sau_lin_cfg.h" +#include "r_lin_api.h" +#include "r_sau_uart.h" +#include "r_timer_api.h" +#include "r_external_irq_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** SAU LIN Event codes */ +typedef enum e_sau_lin_state +{ + SAU_LIN_STATE_NONE, ///< Master mode: No event present Slave mode: Waiting for break field signal + SAU_LIN_STATE_SENDING_WAKEUP, ///< Transmitting wakeup signal + SAU_LIN_STATE_SENDING_BREAK_FIELD, ///< Transmitting break field signal + SAU_LIN_STATE_SENDING_SYNC, ///< Transmitting sync word + SAU_LIN_STATE_AWAITING_SYNC_SIGNAL, ///< Waiting to receive sync word + SAU_LIN_STATE_SENDING_PID, ///< Transmitting protected identifier + SAU_LIN_STATE_AWAITING_PID_SIGNAL, ///< Waiting to receive protected identifier + SAU_LIN_STATE_HEADER_RECEIVED, ///< LIN header received + SAU_LIN_STATE_SENDING_DATA, ///< Transmitting LIN data + SAU_LIN_STATE_AWAITING_DATA, ///< Receiving LIN data + SAU_LIN_STATE_AWAITING_CHECKSUM, ///< Receiving LIN checksum + SAU_LIN_STATE_BUS_SLEEP, ///< Bus sleep state +} sau_lin_state_t; + +/** Auto synchronization setting. */ +typedef enum e_sau_lin_synchronization +{ + SAU_LIN_AUTO_SYNCHRONIZATION_DISABLE = 0, ///< Disable auto synchronization during sync byte reception. + SAU_LIN_AUTO_SYNCHRONIZATION_ENABLE = 1, ///< Enable auto synchronization during sync byte reception. +} sau_lin_synchronization_t; + +/** SAU UART LIN extended configuration */ +typedef struct st_sau_lin_extended_cfg +{ + const uart_instance_t * p_uart; ///< The UART instance used in SAU LIN + const external_irq_instance_t * p_icu; ///< The IRQ instance used in SAU LIN +#if SAU_LIN_CFG_MASTER_SUPPORT_ENABLE + sau_uart_baudrate_setting_t * p_break_field_baudrate; ///< Alternate baud rate setting for sending break field +#endif +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + const timer_instance_t * p_timer; ///< The TAU instance used in SAU LIN + uint32_t timer_clock_frequency; ///< Timer clock frequency + sau_lin_synchronization_t auto_synchronization; ///< Auto synchronization setting +#endif +} sau_lin_extended_cfg_t; + +/** LIN Instance Control Block. DO NOT INITIALIZE. */ +typedef struct st_sau_lin_instance_ctrl +{ + lin_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t open; // Used to determine if the channel is configured + void (* p_callback)(lin_callback_args_t *); // Pointer to callback + void * p_context; // Pointer to context to be passed into callback function + uint8_t * p_data; // Data frame buffer pointer (used for both transmission and reception) + uint8_t count; // Tracks number of data bytes expected in the transfer (used for both transmission and reception). + lin_checksum_type_t checksum_type; // Checksum type to use for checksum generation + uint8_t checksum; // Transmission: stores the computed checksum for transmitted data. Reception: upon receiving the checksum byte, stores the received checksum. + uint8_t validate_checksum; // Indicates whether checksum should be validated by driver + uint8_t last_pid; // Last PID transmitted or received + sau_lin_state_t state; // Tracks LIN transmission/reception state +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + uint32_t sync_bits_sum; // Stores the calculated sum of pulse widths + uint8_t sync_bits_received; // Stores the calculated sum of pulse times +#endif +} sau_lin_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern lin_api_t const g_lin_on_sau_lin; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_Open(lin_ctrl_t * const p_api_ctrl, lin_cfg_t const * const p_cfg); +fsp_err_t R_SAU_LIN_Write(lin_ctrl_t * const p_api_ctrl, const lin_transfer_params_t * const p_transfer_params); +fsp_err_t R_SAU_LIN_StartFrameWrite(lin_ctrl_t * const p_api_ctrl, uint8_t const id); // [DEPRECATED] +fsp_err_t R_SAU_LIN_InformationFrameWrite(lin_ctrl_t * const p_api_ctrl, + const lin_transfer_params_t * const p_transfer_params); // [DEPRECATED] +fsp_err_t R_SAU_LIN_InformationFrameRead(lin_ctrl_t * const p_api_ctrl, + lin_transfer_params_t * const p_transfer_params); // [DEPRECATED] +fsp_err_t R_SAU_LIN_Read(lin_ctrl_t * const p_api_ctrl, lin_transfer_params_t * const p_transfer_params); +fsp_err_t R_SAU_LIN_CommunicationAbort(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_LIN_CallbackSet(lin_ctrl_t * const p_api_ctrl, + void ( * p_callback)(lin_callback_args_t *), + void * const p_context, + lin_callback_args_t * const p_callback_memory); +fsp_err_t R_SAU_LIN_WakeupSend(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_LIN_SleepEnter(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_LIN_SleepExit(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_LIN_Close(lin_ctrl_t * const p_api_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup SAU_LIN) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_spi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_spi.h new file mode 100644 index 0000000000..885f0f6c3a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_spi.h @@ -0,0 +1,155 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SAU_SPI_H +#define R_SAU_SPI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_api.h" +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*****************************************************************************************************************//** + * @ingroup SAU_SPI + * @{ + ********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SAU_SPI_TRANSFER_MODE_RECEPTION (1U) ///< Reception only +#define SAU_SPI_TRANSFER_MODE_TRANSMISSION (2U) ///< Transmission only +#define SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION (3U) ///< Transmission/reception + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Selection of operating clock (fMCK) of channel */ +typedef enum e_sau_spi_operation_clock +{ + SAU_SPI_OPERATION_CLOCK_CK0 = 0, ///< Operation clock CK0 set by SPS register + SAU_SPI_OPERATION_CLOCK_CK1 = 1, ///< Operation clock CK1 set by SPS register +} sau_spi_operation_clock_t; + +/** Selection of transfer mode of channel */ +typedef enum e_sau_spi_transfer_mode +{ + SAU_SPI_TRANSFER_MODE_SINGLE = 0, ///< Single transfer mode + SAU_SPI_TRANSFER_MODE_CONTINUOUS = 1, ///< Continuous transfer mode +} sau_spi_transfer_mode_t; + +/** Data phase */ +typedef enum e_sau_spi_data_phase +{ + SAU_SPI_DATA_PHASE_START = 0, ///< Data output starts from the start of the operation of the serial clock + SAU_SPI_DATA_PHASE_HALF_CYCLE_START = 1, ///< Data output starts half a clock cycle before the start of the serial clock operation +} sau_spi_data_phase_t; + +/** Clock phase */ +typedef enum e_sau_spi_clock_phase +{ + SAU_SPI_CLOCK_PHASE_NON_REVERSE = 0, ///< Non-reverse + SAU_SPI_CLOCK_PHASE_REVERSE = 1, ///< Reverse +} sau_spi_clock_phase_t; + +/** Settings for adjusting the SPI CLK */ +typedef struct st_sau_spi_div_setting +{ + sau_spi_operation_clock_t operation_clock; + uint8_t stclk; +} sau_spi_div_setting_t; + +/** Configuration settings for SAU_SPI pins */ +typedef struct sau_spi_pin_settings +{ + bsp_io_port_pin_t pin; ///< The pin + uint32_t cfg; ///< Configuration for the pin +} sau_spi_pin_settings_t; + +/** SAU SPI extended configuration */ +typedef struct st_sau_spi_extended_cfg +{ + sau_spi_div_setting_t clk_div; + sau_spi_transfer_mode_t transfer_mode; + sau_spi_data_phase_t data_phase; + sau_spi_clock_phase_t clock_phase; + uint8_t sau_unit; + sau_spi_pin_settings_t sck_pin_settings; + sau_spi_pin_settings_t so_pin_settings; +} sau_spi_extended_cfg_t; + +/** SPI instance control block. DO NOT INITIALIZE. */ +typedef struct st_sau_spi_instance_ctrl +{ + uint32_t open; + spi_cfg_t const * p_cfg; + R_SAU0_Type * p_reg; + uint8_t * p_src; + uint8_t * p_dest; + uint32_t tx_count; + uint32_t rx_count; + uint32_t count; + bool transfer_in_progress; + bool activation_on_tei; + + /* Pointer to callback and optional working memory. */ + void (* p_callback)(spi_callback_args_t *); + + /* Pointer to context to be passed into callback function. */ + void * p_context; +} sau_spi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_api_t g_spi_on_sau; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_SAU_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); +fsp_err_t R_SAU_SPI_Read(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SAU_SPI_Write(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SAU_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SAU_SPI_Close(spi_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_SPI_CalculateBitrate(uint32_t bitrate, + sau_spi_div_setting_t * sclk_div, + uint8_t sau_unit, + uint8_t channel); +fsp_err_t R_SAU_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end ingroup SAU_SPI) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_uart.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_uart.h new file mode 100644 index 0000000000..1b0516ed4f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sau_uart.h @@ -0,0 +1,125 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef R_SAU_UART_H +#define R_SAU_UART_H + +/*******************************************************************************************************************//** + * @addtogroup SAU_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_sau_uart_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART Data transfer sequence definition */ +typedef enum e_sau_uart_data_sequence +{ + SAU_UART_DATA_SEQUENCE_MSB = 0U, ///< Data sequence MSB first + SAU_UART_DATA_SEQUENCE_LSB = 1U, ///< Data sequence LSB first +} sau_uart_data_sequence_t; + +/** UART operation clock selection definition */ +typedef enum e_sau_operation_clock +{ + SAU_UART_OPERATION_CLOCK_CK0 = 0U, ///< Operating clock use CK0 + SAU_UART_OPERATION_CLOCK_CK1 = 1U, ///< Operating clock use CK1 +} sau_operation_clock_t; + +/** UART data signal level definition */ +typedef enum e_sau_uart_signal_level +{ + SAU_UART_SIGNAL_LEVEL_STANDARD = 0U, ///< Uart data signal level standard + SAU_UART_SIGNAL_LEVEL_INVERTED = 1U, ///< Uart data signal level inverted +} sau_uart_signal_level_t; + +typedef struct +{ + sau_operation_clock_t operation_clock; ///< Select operation clock + uint8_t stclk; ///< Transfer clock setting by dividing the operation clock + uint8_t prs; ///< Operation clock divider register setting +} sau_uart_baudrate_setting_t; + +/** UART Configuration */ +typedef struct st_sau_uart_extended_cfg +{ + /* UART generic configuration */ + sau_uart_data_sequence_t sequence; ///< Transfer sequence (LSB or MSB) + sau_uart_signal_level_t signal_level; ///< Transfer data signal level (standard or inverted) + sau_uart_baudrate_setting_t * p_baudrate; ///< Baud rate setting (SPS and SDR value) +} sau_uart_extended_cfg_t; + +/** UART instance control block. DO NOT INITIALIZE. */ +typedef struct st_sau_uart_instance_ctrl +{ + uint8_t extra_data_byte; ///< 0 for 7 or 8 bit data length(1-byte), 1 for 9 bit data length(2-byte) + uint32_t open; ///< Used to determine if the channel is configured + uart_cfg_t const * p_cfg; ///< Pointer to the configuration block. + R_SAU0_Type * p_reg; ///< Base register for the transmit channel + uint8_t sau_unit; ///< SAU unit information + uint8_t sau_tx_channel; ///< SAU channel information + uint8_t * p_src; ///< Source buffer pointer + uint32_t tx_count; ///< Size of destination buffer pointer from transmit ISR + uint8_t * p_dest; ///< Destination buffer pointer + uint32_t rx_count; ///< Size of destination buffer pointer used for receiving data + + /* Pointer to callback and optional working memory. */ + void (* p_callback)(uart_callback_args_t *); + + /* Pointer to context to be passed into callback function. */ + void * p_context; +} sau_uart_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_sau; + +/** @endcond */ + +fsp_err_t R_SAU_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_SAU_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SAU_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SAU_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_SAU_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); +fsp_err_t R_SAU_UART_Close(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_SAU_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_SAU_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); +fsp_err_t R_SAU_UART_BaudCalculate(sau_uart_instance_ctrl_t * const p_ctrl, + uint32_t baudrate, + sau_uart_baudrate_setting_t * const p_baud_setting); +fsp_err_t R_SAU_UART_ReceiveSuspend(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SAU_UART_ReceiveResume(uart_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end addtogroup SAU_UART) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_b_uart.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_b_uart.h new file mode 100644 index 0000000000..913a92d872 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_b_uart.h @@ -0,0 +1,219 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCI_B_UART_H +#define R_SCI_B_UART_H + +/*******************************************************************************************************************//** + * @addtogroup SCI_B_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_sci_b_uart_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for SCI clock source */ +typedef enum e_sci_b_clk_src +{ + SCI_B_UART_CLOCK_INT, ///< Use internal clock for baud generation + SCI_B_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK + SCI_B_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate + SCI_B_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate +} sci_b_clk_src_t; + +/** UART flow control mode definition */ +typedef enum e_sci_b_uart_flow_control +{ + SCI_B_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS + SCI_B_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS + SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS + SCI_B_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS +} sci_b_uart_flow_control_t; + +/** UART instance control block. */ +typedef struct st_sci_b_uart_instance_ctrl +{ + /* Parameters to control UART peripheral device */ + uint8_t fifo_depth; // FIFO depth of the UART channel + uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise + uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data + uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise + uint32_t open; // Used to determine if the channel is configured + + bsp_io_port_pin_t flow_pin; + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t const * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Base register for this channel */ + R_SCI_B0_Type * p_reg; + + void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. + uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void * p_context; +} sci_b_uart_instance_ctrl_t; + +/** Receive FIFO trigger configuration. */ +typedef enum e_sci_b_uart_rx_fifo_trigger +{ + SCI_B_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering + SCI_B_UART_RX_FIFO_TRIGGER_2 = 0x2, ///< Callback when FIFO having 2 bytes + SCI_B_UART_RX_FIFO_TRIGGER_3 = 0x3, ///< Callback when FIFO having 3 bytes + SCI_B_UART_RX_FIFO_TRIGGER_4 = 0x4, ///< Callback when FIFO having 4 bytes + SCI_B_UART_RX_FIFO_TRIGGER_5 = 0x5, ///< Callback when FIFO having 5 bytes + SCI_B_UART_RX_FIFO_TRIGGER_6 = 0x6, ///< Callback when FIFO having 6 bytes + SCI_B_UART_RX_FIFO_TRIGGER_7 = 0x7, ///< Callback when FIFO having 7 bytes + SCI_B_UART_RX_FIFO_TRIGGER_8 = 0x8, ///< Callback when FIFO having 8 bytes + SCI_B_UART_RX_FIFO_TRIGGER_9 = 0x9, ///< Callback when FIFO having 9 bytes + SCI_B_UART_RX_FIFO_TRIGGER_10 = 0xA, ///< Callback when FIFO having 10 bytes + SCI_B_UART_RX_FIFO_TRIGGER_11 = 0xB, ///< Callback when FIFO having 11 bytes + SCI_B_UART_RX_FIFO_TRIGGER_12 = 0xC, ///< Callback when FIFO having 12 bytes + SCI_B_UART_RX_FIFO_TRIGGER_13 = 0xD, ///< Callback when FIFO having 13 bytes + SCI_B_UART_RX_FIFO_TRIGGER_14 = 0xE, ///< Callback when FIFO having 14 bytes + SCI_B_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) +} sci_b_uart_rx_fifo_trigger_t; + +/** Asynchronous Start Bit Edge Detection configuration. */ +typedef enum e_sci_b_uart_start_bit_detect +{ + SCI_B_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit + SCI_B_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit +} sci_b_uart_start_bit_detect_t; + +/** Noise cancellation configuration. */ +typedef enum e_sci_b_uart_noise_cancellation +{ + SCI_B_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation + SCI_B_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation +} sci_b_uart_noise_cancellation_t; + +/** RS-485 Enable/Disable. */ +typedef enum e_sci_b_uart_rs485_enable +{ + SCI_B_UART_RS485_DISABLE = 0, ///< RS-485 disabled. + SCI_B_UART_RS485_ENABLE = 1, ///< RS-485 enabled. +} sci_b_uart_rs485_enable_t; + +/** The polarity of the RS-485 DE signal. */ +typedef enum e_sci_b_uart_rs485_de_polarity +{ + SCI_B_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. + SCI_B_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. +} sci_b_uart_rs485_de_polarity_t; + +/** Register settings to achieve a desired baud rate and modulation duty. */ +typedef struct st_sci_b_baud_setting_t +{ + union + { + uint32_t baudrate_bits; + + struct + { + uint32_t : 3; + uint32_t : 1; + uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select + uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select + uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 + uint32_t : 1; + uint32_t brr : 8; ///< Bit Rate Register setting + uint32_t brme : 1; ///< Bit Rate Modulation Enable + uint32_t : 3; + uint32_t cks : 2; ///< CKS value to get divisor (CKS = N) + uint32_t : 2; + uint32_t mddr : 8; ///< Modulation Duty Register setting + } baudrate_bits_b; + }; +} sci_b_baud_setting_t; + +/** Configuration settings for controlling the DE signal for RS-485. */ +typedef struct st_sci_b_uart_rs485_setting +{ + sci_b_uart_rs485_enable_t enable; ///< Enable the DE signal. + sci_b_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. + uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer. + uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated. +} sci_b_uart_rs485_setting_t; + +/** UART on SCI device Configuration */ +typedef struct st_sci_b_uart_extended_cfg +{ + sci_b_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK + sci_b_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge + sci_b_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting + sci_b_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + sci_b_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used. + bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin + sci_b_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin + sci_b_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. +} sci_b_uart_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_sci_b; + +/** @endcond */ + +fsp_err_t R_SCI_B_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_SCI_B_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SCI_B_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SCI_B_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_SCI_B_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); +fsp_err_t R_SCI_B_UART_Close(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_B_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_SCI_B_UART_BaudCalculate(uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + sci_b_baud_setting_t * const p_baud_setting); +fsp_err_t R_SCI_B_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_B_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); +fsp_err_t R_SCI_B_UART_ReceiveSuspend(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_B_UART_ReceiveResume(uart_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_B_UART) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_i2c.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_i2c.h new file mode 100644 index 0000000000..34394bf5a8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_i2c.h @@ -0,0 +1,128 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup SCI_I2C + * @{ + **********************************************************************************************************************/ + +#ifndef R_SCI_I2C_H +#define R_SCI_I2C_H + +#include "bsp_api.h" +#include "r_sci_i2c_cfg.h" +#include "r_i2c_master_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** I2C clock settings */ +typedef struct sci_i2c_clock_settings +{ + bool bitrate_modulation; ///< Bit-rate Modulation Function enable or disable + uint8_t brr_value; ///< Bit rate register settings + uint8_t clk_divisor_value; ///< Clock Select settings + uint8_t mddr_value; ///< Modulation Duty Register settings + uint8_t cycles_value; ///< SDA Delay Output Cycles Select + uint8_t snfr_value; ///< Noise Filter Setting Register value +} sci_i2c_clock_settings_t; + +/** I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_sci_i2c_instance_ctrl +{ + i2c_master_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t slave; // The address of the slave device + i2c_master_addr_mode_t addr_mode; // Indicates how slave fields should be interpreted + uint32_t open; // Flag to determine if the device is open + R_SCI0_Type * p_reg; // Base register for this channel + + IRQn_Type rxi_irq; // Receive IRQ number + IRQn_Type txi_irq; // Transmit IRQ number + IRQn_Type tei_irq; // Transmit end IRQ number + + /* Current transfer information. */ + uint8_t * p_buff; // Holds the data associated with the transfer */ + uint32_t total; // Holds the total number of data bytes to transfer */ + uint32_t remain; // Tracks the remaining data bytes to transfer */ + uint32_t loaded; // Tracks the number of data bytes written to the register */ + + uint8_t addr_low; // Holds the last address byte to issue */ + uint8_t addr_high; // Holds the first address byte to issue in 10-bit mode */ + uint8_t addr_total; // Holds the total number of address bytes to transfer */ + uint8_t addr_remain; // Tracks the remaining address bytes to transfer */ + uint8_t addr_loaded; // Tracks the number of address bytes written to the register */ + + volatile bool read; // Holds the direction of the data byte transfer */ + volatile bool restart; // Holds whether or not the restart should be issued when done */ + volatile bool err; // Tracks whether or not an error occurred during processing */ + volatile bool restarted; // Tracks whether or not a restart was issued during the previous transfer */ + volatile bool do_dummy_read; // Tracks whether a dummy read is issued on the first RX */ + volatile bool activation_on_rxi; // Tracks whether the transfer is activated on RXI interrupt */ + volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt */ + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + i2c_master_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} sci_i2c_instance_ctrl_t; + +/** SCI I2C extended configuration */ +typedef struct st_sci_i2c_extended_cfg +{ + sci_i2c_clock_settings_t clock_settings; ///< I2C Clock settings +} sci_i2c_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_master_api_t const g_i2c_master_on_sci; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_Open(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg); +fsp_err_t R_SCI_I2C_Close(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_I2C_Read(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart); +fsp_err_t R_SCI_I2C_Write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart); +fsp_err_t R_SCI_I2C_Abort(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_I2C_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); +fsp_err_t R_SCI_I2C_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_I2C_StatusGet(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup SCI_I2C) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_lin.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_lin.h new file mode 100644 index 0000000000..d2ebe0b03c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_lin.h @@ -0,0 +1,254 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCI_LIN_H +#define R_SCI_LIN_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_sci_lin_cfg.h" +#include "r_lin_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup SCI_LIN + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Priority interrupt bit options for ID filtering. */ +typedef enum e_sci_lin_priority_interrupt_bit +{ + SCI_LIN_PRIORITY_INTERRUPT_BIT_DISABLE = 0, ///< Disable the priority interrupt bit + SCI_LIN_PRIORITY_INTERRUPT_BIT_ENABLE = 1, ///< Enable the priority interrupt bit +} sci_lin_priority_interrupt_bit_t; + +/** Compare Data Select options for ID filtering. */ +typedef enum e_sci_lin_compare_data_select +{ + SCI_LIN_COMPARE_DATA_SELECT_PRIORITY = 0, ///< Deprecated + SCI_LIN_COMPARE_DATA_SELECT_PRIMARY = 0, ///< Select the primary compare data filter as the compare data + SCI_LIN_COMPARE_DATA_SELECT_SECONDARY = 1, ///< Select the secondary compare data filter as the compare data + SCI_LIN_COMPARE_DATA_SELECT_BOTH = 2, ///< Select both the priority/primary compare data filter and the secondary compare data filter as the compare data. The priority filter will be checked first. +} sci_lin_compare_data_select_t; + +/** LIN timer divider selection. */ +typedef enum e_sci_lin_timer_divider +{ + SCI_LIN_TIMER_DIV_1 = 0U, ///< LIN timer frequency is PCLK/1 + SCI_LIN_TIMER_DIV_2 = 1U, ///< LIN timer frequency is PCLK/2 + SCI_LIN_TIMER_DIV_4 = 2U, ///< LIN timer frequency is PCLK/4 + SCI_LIN_TIMER_DIV_8 = 3U, ///< LIN timer frequency is PCLK/8 + SCI_LIN_TIMER_DIV_16 = 4U, ///< LIN timer frequency is PCLK/16 + SCI_LIN_TIMER_DIV_32 = 5U, ///< LIN timer frequency is PCLK/32 + SCI_LIN_TIMER_DIV_64 = 6U, ///< LIN timer frequency is PCLK/64 + SCI_LIN_TIMER_DIV_128 = 7U, ///< LIN timer frequency is PCLK/128 +} sci_lin_timer_divider_t; + +/** Digital filter configuration. */ +typedef enum e_sci_lin_digital_filter_clock +{ + SCI_LIN_DIGITAL_FILTER_CLOCK_DISABLED = 0U, ///< Filter is disabled + SCI_LIN_DIGITAL_FILTER_CLOCK_SCI_BASE_CLK = 1U, ///< Filter clock is SCI base clock. + SCI_LIN_DIGITAL_FILTER_CLOCK_PCLK_DIV_8 = 2U, ///< Filter clock is PCLK/8 + SCI_LIN_DIGITAL_FILTER_CLOCK_PCLK_DIV_16 = 3U, ///< Filter clock is PCLK/16 + SCI_LIN_DIGITAL_FILTER_CLOCK_PCLK_DIV_32 = 4U, ///< Filter clock is PCLK/32 + SCI_LIN_DIGITAL_FILTER_CLOCK_PCLK_DIV_64 = 5U, ///< Filter clock is PCLK/64 + SCI_LIN_DIGITAL_FILTER_CLOCK_PCLK_DIV_128 = 6U, ///< Filter clock is PCLK/128 +} sci_lin_digital_filter_clock_t; + +/** Bus conflict detection clock selection. + * The period of the SCI base clock is 1/16 of a single bit period when the SCIn.SEMR.ABCS is 0, + * and 1/8 of a single bit period when the SCIn.SEMR.ABCS is 1. + **/ +typedef enum e_sci_lin_bus_conflict_clock +{ + SCI_LIN_BUS_CONFLICT_CLOCK_DIV_1 = 0U, ///< Bus conflict detection clock is base clock + SCI_LIN_BUS_CONFLICT_CLOCK_DIV_2 = 1U, ///< Bus conflict detection clock is base clock/2 + SCI_LIN_BUS_CONFLICT_CLOCK_DIV_4 = 2U, ///< Bus conflict detection clock is base clock/4. +} sci_lin_bus_conflict_clock_t; + +/** Asynchronous Mode Base Clock Select. + * The period of the SCI base clock is 1/16 of a single bit period when the SCIn.SEMR.ABCS is 0, + * and 1/8 of a single bit period when the SCIn.SEMR.ABCS is 1. + **/ +typedef enum e_sci_lin_base_clock +{ + SCI_LIN_BASE_CLOCK_16 = 0U, ///< Select 16 base clock cycles for 1-bit period + SCI_LIN_BASE_CLOCK_8 = 1U, ///< Select 8 base clock cycles for 1-bit period +} sci_lin_base_clock_t; + +/** Register settings for configuring the LIN timer */ +typedef struct st_sci_lin_timer_setting +{ + uint8_t tcss; ///< LIN timer count clock source selection + uint8_t break_field_tpre; ///< Break field prescaler + uint8_t break_field_tcnt; ///< Break field count value + uint8_t delimiter_tpre; ///< Break delimiter prescaler + uint8_t delimiter_tcnt; ///< Break delimiter count value +} sci_lin_timer_setting_t; + +/** Register settings for achieving a desired baud rate. */ +typedef struct st_sci_lin_baud_setting +{ + sci_lin_timer_setting_t timer_setting; ///< Break field timer settings associated with this baud rate + union + { + uint8_t semr_baudrate_bits; + + struct + { + uint8_t : 3; + uint8_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select + uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select + uint8_t : 1; + uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select + uint8_t : 1; + } semr_baudrate_bits_b; + }; + uint8_t brr; ///< Bit Rate Register setting + uint8_t cks : 2; ///< CKS value to get divisor +} sci_lin_baud_setting_t; + +/** Parameters for configuring the ID filter settings */ +typedef struct st_sci_lin_id_filter_setting +{ + /** Bit mask applied before comparing the received PID to the compare data. + * Selects which bits of the selected compare data must match.*/ + uint8_t compare_data_mask; + + /** Primary compare data */ + uint8_t primary_compare_data; + + /** Secondary compare data */ + uint8_t secondary_compare_data; + + /** Specify ONE of bits 0 to 7 of Control Field 1 as the priority interrupt bit. + * 0 is bit 0 of the PID, 1 is bit 1 of the PID, and so on.*/ + uint8_t priority_interrupt_bit_select : 3; + + /** Set to 1 to enable the priority interrupt bit filter specified by priority_interrupt_bit_select, + * 0 to disable. When this bit is 1, regardless of the compare_data_select setting value, the bit + * specified by priority_interrupt_bit_select is compared with the Primary comparison data + * for Control Field 1 (primary_compare_data).*/ + uint8_t priority_interrupt_enable : 1; + + /** Select the compare data for Control Field 1 (priority, secondary, or both). + * See @ref sci_lin_compare_data_select_t*/ + uint8_t compare_data_select : 2; + uint8_t : 2; +} sci_lin_id_filter_setting_t; + +/** Parameters for baud and timer setting calculation */ +typedef struct st_sci_lin_baud_params +{ + uint32_t baudrate; ///< Desired baudrate + uint16_t break_bits; ///< Master mode: Number of break field bits to transmit. Slave mode: Number of break field threshold bits. + uint8_t delimiter_bits; ///< Break delimeter length setting (at least 1 nominal bit time long). + sci_lin_base_clock_t base_clock_cycles_per_bit; ///< Number of base clock cycles for 1-bit period. +} sci_lin_baud_params_t; + +/** SCI LIN extended configuration */ +typedef struct st_sci_lin_extended_cfg +{ + sci_lin_digital_filter_clock_t digital_filter_clock; ///< Digital filter setting. See @ref sci_lin_digital_filter_clock_t + sci_lin_bus_conflict_clock_t bus_conflict_clock; ///< Bus conflict detection clock setting. See @ref sci_lin_bus_conflict_clock_t + uint16_t break_bits; ///< Master mode: Number of break field bits to transmit. Slave mode: Number of break field threshold bits. + uint8_t delimiter_bits; ///< Break delimeter length setting (at least 1 nominal bit time long). + sci_lin_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + sci_lin_id_filter_setting_t filter_setting; ///< ID filter setting + + /* Interrupt settings */ + IRQn_Type scix0_irq; ///< Break field low width IRQ number + IRQn_Type scix1_irq; ///< Control field 0-1 match / Priority interrupt bit detect IRQ number + IRQn_Type scix2_irq; ///< Bus collision detect IRQ number + IRQn_Type scix3_irq; ///< Valid edge detect IRQ number + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number + IRQn_Type eri_irq; ///< Error interrupt IRQ number + uint8_t scix0_ipl; ///< Break field low width interrupt priority + uint8_t scix1_ipl; ///< Control field 0-1 match / Priority interrupt bit detect interrupt priority + uint8_t scix2_ipl; ///< Bus collision detect interrupt priority + uint8_t scix3_ipl; ///< Valid edge detect interrupt priority + uint8_t rxi_ipl; ///< Receive interrupt priority + uint8_t txi_ipl; ///< Transmit interrupt priority + uint8_t tei_ipl; ///< Transmit end interrupt priority + uint8_t eri_ipl; ///< Error interrupt priority +} sci_lin_extended_cfg_t; + +/** LIN Instance Control Block. DO NOT INITIALIZE. */ +typedef struct st_sci_lin_instance_ctrl +{ + uint32_t open; // Used to determine if the channel is configured + lin_cfg_t const * p_cfg; // Pointer to the configuration block + R_SCI0_Type * p_reg; // Base register for this channel + void (* p_callback)(lin_callback_args_t *); // Pointer to callback + lin_callback_args_t * p_callback_memory; // Pointer to optional working memory + void * p_context; // Pointer to context to be passed into callback function + lin_event_t event; // Used to distinguish between header and data transmission completion events + uint8_t * p_data; // Information frame buffer pointer (used for both transmission and reception) + uint32_t sync_bits_sum; // Sum of sync bit durations when auto synchronization is used + uint32_t timer_freq_hz; // LIN timer frequency (Hz) used for break field generation/reception, break delimiter transmission, and auto synchronization + uint8_t tx_src_bytes; // Transmit buffer length, in bytes + uint8_t tx_header_bytes; // Tracks number of header bytes transmitted + uint8_t rx_bytes_expected; // Tracks number of frame bytes expected in the transfer (including checksum) + uint8_t rx_bytes_received; // Tracks number of information frame bytes received in the transfer (excluding checksum) + uint8_t checksum; // Stores computed checksum as bytes come in during reception. Once checksum byte is received, stores received checksum + uint8_t validate_checksum; // Indicates whether checksum should be validated by driver + uint8_t last_pid; // Last PID transmitted or received + uint8_t sync_bits_received; // Number of sync bits successfully measured so far during auto synchronization +} sci_lin_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Interface Structure for user access */ +extern const lin_api_t g_lin_on_sci; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_Open(lin_ctrl_t * const p_api_ctrl, lin_cfg_t const * const p_cfg); +fsp_err_t R_SCI_LIN_Write(lin_ctrl_t * const p_api_ctrl, const lin_transfer_params_t * const p_transfer_params); +fsp_err_t R_SCI_LIN_Read(lin_ctrl_t * const p_api_ctrl, lin_transfer_params_t * const p_transfer_params); +fsp_err_t R_SCI_LIN_CommunicationAbort(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_LIN_CallbackSet(lin_ctrl_t * const p_api_ctrl, + void ( * p_callback)(lin_callback_args_t *), + void * const p_context, + lin_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_LIN_IdFilterSet(lin_ctrl_t * const p_api_ctrl, sci_lin_id_filter_setting_t const * const p_config); +fsp_err_t R_SCI_LIN_IdFilterGet(lin_ctrl_t * const p_api_ctrl, sci_lin_id_filter_setting_t * const p_config); +fsp_err_t R_SCI_LIN_Close(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_LIN_BaudCalculate(sci_lin_baud_params_t const * const p_baud_params, + sci_lin_baud_setting_t * const p_baud_setting); +fsp_err_t R_SCI_LIN_WakeupSend(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_LIN_SleepEnter(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_LIN_SleepExit(lin_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_LIN_StartFrameWrite(lin_ctrl_t * const p_api_ctrl, uint8_t const id); // [DEPRECATED] +fsp_err_t R_SCI_LIN_InformationFrameWrite(lin_ctrl_t * const p_api_ctrl, + const lin_transfer_params_t * const p_transfer_params); // [DEPRECATED] +fsp_err_t R_SCI_LIN_InformationFrameRead(lin_ctrl_t * const p_api_ctrl, + lin_transfer_params_t * const p_transfer_params); // [DEPRECATED] + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_LIN) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_smci.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_smci.h new file mode 100644 index 0000000000..bc9148d184 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_smci.h @@ -0,0 +1,139 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCI_SMCI_H +#define R_SCI_SMCI_H + +/*******************************************************************************************************************//** + * @addtogroup SCI_SMCI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_smci_api.h" +#include "r_sci_smci_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** SMCI instance control block. */ +typedef struct st_sci_smci_instance_ctrl +{ + /* Used to determine if the channel is configured. */ + uint32_t open; + + /* Source buffer pointer used to fill hardware TDR from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Number of bytes received */ + uint32_t rx_bytes_received; + + /* Pointer to the configuration block. */ + smci_cfg_t const * p_cfg; + + /* State of this instance of the SMCI */ + smci_state_t smci_state; + + /* Base register for this channel */ + R_SCI0_Type * p_reg; + + void (* p_callback)(smci_callback_args_t *); // Pointer to callback that is called when a smci_event_t occurs. + smci_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void * p_context; +} sci_smci_instance_ctrl_t; + +/** Register settings to achieve a desired baud rate in Smart Card mode */ +typedef struct st_smci_baud_setting_t +{ + uint32_t computed_baud_rate; + union + { + uint8_t smr_smci_clock_bits; + + struct st_smr_smci_clock_bits_b + { + uint8_t cks : 2; ///< Clock divisor Select + uint8_t bcp01 : 2; ///< Base Clock Pulse + uint8_t : 1; + uint8_t : 1; + uint8_t : 1; + uint8_t : 1; + } smr_smci_clock_bits_b; + }; + + uint8_t scmr_bcp2 : 1; ///< BCP2 setting in Smart Card Mode Register + uint8_t brr; ///< Bit Rate Register setting +} smci_baud_setting_t; + +/** SMCI on SCI device Configuration */ +typedef struct st_sci_smci_extended_cfg +{ + smci_baud_setting_t * p_smci_baud_setting; ///< Register settings for a desired baud rate. +} sci_smci_extended_cfg_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * sci_smci_prv_ns_callback)(smci_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_smci_prv_ns_callback)(smci_callback_args_t * p_args); +#endif + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const smci_api_t g_smci_on_sci; + +/** @endcond */ +fsp_err_t R_SCI_SMCI_Open(smci_ctrl_t * const p_api_ctrl, smci_cfg_t const * const p_cfg); +fsp_err_t R_SCI_SMCI_Write(smci_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SCI_SMCI_Read(smci_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SCI_SMCI_TransferModeSet(smci_ctrl_t * const p_api_ctrl, + smci_transfer_mode_t const * const p_transfer_mode_params); +fsp_err_t R_SCI_SMCI_BaudCalculate(smci_speed_params_t const * const p_speed_params, + uint32_t baud_rate_error_x_1000, + void * const p_baud_setting); + +fsp_err_t R_SCI_SMCI_BaudSet(smci_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_SCI_SMCI_StatusGet(smci_ctrl_t * const p_api_ctrl, smci_status_t * const p_status); +fsp_err_t R_SCI_SMCI_ClockControl(smci_ctrl_t * const p_api_ctrl, bool clock_enable); +fsp_err_t R_SCI_SMCI_CallbackSet(smci_ctrl_t * const p_api_ctrl, + void ( * p_callback)(smci_callback_args_t *), + void * const p_context, + smci_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_SMCI_Close(smci_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_SMCI) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_SCI_SMCI_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_spi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_spi.h new file mode 100644 index 0000000000..1c0ca73d5d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_spi.h @@ -0,0 +1,106 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCI_SPI_H +#define R_SCI_SPI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*****************************************************************************************************************//** + * @ingroup SCI_SPI + * @{ + ********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Settings for adjusting the SPI CLK. */ +typedef struct +{ + uint8_t brr; + uint8_t cks : 2; + uint8_t mddr; ///< Set to 0 to disable MDDR. +} sci_spi_div_setting_t; + +/** SCI SPI extended configuration */ +typedef struct st_sci_spi_extended_cfg +{ + sci_spi_div_setting_t clk_div; +} sci_spi_extended_cfg_t; + +/** SPI instance control block. DO NOT INITIALIZE. */ +typedef struct st_sci_spi_instance_ctrl +{ + uint32_t open; + spi_cfg_t const * p_cfg; + R_SCI0_Type * p_reg; + uint8_t * p_src; + uint8_t * p_dest; + uint32_t tx_count; + uint32_t rx_count; + uint32_t count; + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} sci_spi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_api_t g_spi_on_sci; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); +fsp_err_t R_SCI_SPI_Read(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SCI_SPI_Write(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SCI_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SCI_SPI_Close(spi_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_SPI_CalculateBitrate(uint32_t bitrate, sci_spi_div_setting_t * sclk_div, bool use_mddr); +fsp_err_t R_SCI_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end ingroup SCI_SPI) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_uart.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_uart.h new file mode 100644 index 0000000000..e37bae4dec --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sci_uart.h @@ -0,0 +1,249 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCI_UART_H +#define R_SCI_UART_H + +/*******************************************************************************************************************//** + * @addtogroup SCI_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_sci_uart_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for SCI clock source */ +typedef enum e_sci_clk_src +{ + SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation + SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK + SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate + SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate +} sci_clk_src_t; + +/** UART flow control mode definition */ +typedef enum e_sci_uart_flow_control +{ + SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use SCI pin for RTS + SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use SCI pin for CTS + SCI_UART_FLOW_CONTROL_CTSRTS = 3U, ///< Use SCI pin for CTS, external pin for RTS + SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 8U, ///< Use CTSn_RTSn pin for RTS and CTSn pin for CTS. Available only for some channels on selected MCUs. See hardware manual for channel specific options +} sci_uart_flow_control_t; + +/** UART instance control block. */ +typedef struct st_sci_uart_instance_ctrl +{ + /* Parameters to control UART peripheral device */ + uint8_t fifo_depth; // FIFO depth of the UART channel + uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise + uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data + uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise + uint32_t open; // Used to determine if the channel is configured + + bsp_io_port_pin_t flow_pin; + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t const * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Base register for this channel */ + R_SCI0_Type * p_reg; + + void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. + uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void * p_context; +} sci_uart_instance_ctrl_t; + +/** Receive FIFO trigger configuration. */ +typedef enum e_sci_uart_rx_fifo_trigger +{ + SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering + SCI_UART_RX_FIFO_TRIGGER_2 = 0x2, ///< Callback when FIFO having 2 bytes + SCI_UART_RX_FIFO_TRIGGER_3 = 0x3, ///< Callback when FIFO having 3 bytes + SCI_UART_RX_FIFO_TRIGGER_4 = 0x4, ///< Callback when FIFO having 4 bytes + SCI_UART_RX_FIFO_TRIGGER_5 = 0x5, ///< Callback when FIFO having 5 bytes + SCI_UART_RX_FIFO_TRIGGER_6 = 0x6, ///< Callback when FIFO having 6 bytes + SCI_UART_RX_FIFO_TRIGGER_7 = 0x7, ///< Callback when FIFO having 7 bytes + SCI_UART_RX_FIFO_TRIGGER_8 = 0x8, ///< Callback when FIFO having 8 bytes + SCI_UART_RX_FIFO_TRIGGER_9 = 0x9, ///< Callback when FIFO having 9 bytes + SCI_UART_RX_FIFO_TRIGGER_10 = 0xA, ///< Callback when FIFO having 10 bytes + SCI_UART_RX_FIFO_TRIGGER_11 = 0xB, ///< Callback when FIFO having 11 bytes + SCI_UART_RX_FIFO_TRIGGER_12 = 0xC, ///< Callback when FIFO having 12 bytes + SCI_UART_RX_FIFO_TRIGGER_13 = 0xD, ///< Callback when FIFO having 13 bytes + SCI_UART_RX_FIFO_TRIGGER_14 = 0xE, ///< Callback when FIFO having 14 bytes + SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) +} sci_uart_rx_fifo_trigger_t; + +/** Asynchronous Start Bit Edge Detection configuration. */ +typedef enum e_sci_uart_start_bit_t +{ + SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit + SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit +} sci_uart_start_bit_t; + +/** Noise cancellation configuration. */ +typedef enum e_sci_uart_noise_cancellation +{ + SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation + SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation +} sci_uart_noise_cancellation_t; + +/** RS-485 Enable/Disable. */ +typedef enum e_sci_uart_rs485_enable +{ + SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled. + SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled. +} sci_uart_rs485_enable_t; + +/** The polarity of the RS-485 DE signal. */ +typedef enum e_sci_uart_rs485_de_polarity +{ + SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. + SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. +} sci_uart_rs485_de_polarity_t; + +/** Register settings to achieve a desired baud rate and modulation duty. */ +typedef struct st_baud_setting_t +{ + union + { + uint8_t semr_baudrate_bits; + + struct + { + uint8_t : 2; + uint8_t brme : 1; ///< Bit Rate Modulation Enable + uint8_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 + uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select + uint8_t : 1; + uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select + uint8_t : 1; + } semr_baudrate_bits_b; + }; + uint8_t cks : 2; ///< CKS value to get divisor (CKS = N) + uint8_t brr; ///< Bit Rate Register setting + uint8_t mddr; ///< Modulation Duty Register setting +} baud_setting_t; + +/** Configuration settings for controlling the DE signal for RS-485. */ +typedef struct st_sci_uart_rs485_setting +{ + sci_uart_rs485_enable_t enable; ///< Enable the DE signal. + sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. + bsp_io_port_pin_t de_control_pin; ///< UART Driver Enable pin. +} sci_uart_rs485_setting_t; + +/** IrDA Enable/Disable. */ +typedef enum e_sci_uart_irda_enable +{ + SCI_UART_IRDA_DISABLED = 0, ///< IrDA disabled. + SCI_UART_IRDA_ENABLED = 1, ///< IrDA enabled. +} sci_uart_irda_enable_t; + +/** IrDA Polarity Switching. */ +typedef enum e_sci_uart_irda_polarity +{ + SCI_UART_IRDA_POLARITY_NORMAL = 0, ///< IrDA Tx/Rx polarity not inverted. + SCI_UART_IRDA_POLARITY_INVERTED = 1, ///< IrDA Tx/Rx polarity inverted. +} sci_uart_irda_polarity_t; + +/** Configuration settings for IrDA interface. */ +typedef struct st_sci_uart_irda_setting +{ + union + { + uint8_t ircr_bits; + + struct + { + uint8_t : 2; + uint8_t irrxinv : 1; ///< IRRXD Polarity Switching + uint8_t irtxinv : 1; ///< IRTXD Polarity Switching + uint8_t : 3; + uint8_t ire : 1; ///< Enable IrDA pulse encoding and decoding. + } ircr_bits_b; + }; +} sci_uart_irda_setting_t; + +/** UART on SCI device Configuration */ +typedef struct st_sci_uart_extended_cfg +{ + sci_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK + sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge + sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting + baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used. + bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin + sci_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin + sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. + sci_uart_irda_setting_t irda_setting; ///< IrDA settings +} sci_uart_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_sci; + +/** @endcond */ + +fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); +fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_SCI_UART_BaudCalculate(uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + baud_setting_t * const p_baud_setting); +fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); +fsp_err_t R_SCI_UART_ReceiveSuspend(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_UART_ReceiveResume(uart_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_UART) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sdadc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sdadc.h new file mode 100644 index 0000000000..63d9311738 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sdadc.h @@ -0,0 +1,237 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SDADC_H +#define R_SDADC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sdadc_cfg.h" +#include "r_adc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup SDADC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SDADC_MAX_NUM_CHANNELS (5U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Source of Vref. */ +typedef enum e_sdadc_vref_src +{ + SDADC_VREF_SRC_INTERNAL = 0, ///< Vref is internally sourced, can be output as SBIAS + SDADC_VREF_SRC_EXTERNAL = 1, ///< Vref is externally sourced from the VREFI pin +} sdadc_vref_src_t; + +/** Voltage of Vref. */ +typedef enum e_sdadc_vref_voltage +{ + SDADC_VREF_VOLTAGE_800_MV = 0, ///< Vref is 0.8 V + SDADC_VREF_VOLTAGE_1000_MV = 1, ///< Vref is 1.0 V + SDADC_VREF_VOLTAGE_1200_MV = 2, ///< Vref is 1.2 V + SDADC_VREF_VOLTAGE_1400_MV = 3, ///< Vref is 1.4 V + SDADC_VREF_VOLTAGE_1600_MV = 4, ///< Vref is 1.6 V + SDADC_VREF_VOLTAGE_1800_MV = 5, ///< Vref is 1.8 V + SDADC_VREF_VOLTAGE_2000_MV = 6, ///< Vref is 2.0 V + SDADC_VREF_VOLTAGE_2200_MV = 7, ///< Vref is 2.2 V + SDADC_VREF_VOLTAGE_2400_MV = 15, ///< Vref is 2.4 V (only valid for external Vref) +} sdadc_vref_voltage_t; + +/** Per channel input mode. */ +typedef enum e_sdadc_channel_input +{ + SDADC_CHANNEL_INPUT_DIFFERENTIAL = 0, ///< Differential input + SDADC_CHANNEL_INPUT_SINGLE_ENDED = 1, ///< Single-ended input +} sdadc_channel_input_t; + +/** Per channel stage 1 gain options. */ +typedef enum e_sdadc_channel_stage_1_gain +{ + SDADC_CHANNEL_STAGE_1_GAIN_1 = 0, ///< Gain of 1 + SDADC_CHANNEL_STAGE_1_GAIN_2 = 1, ///< Gain of 2 + SDADC_CHANNEL_STAGE_1_GAIN_3 = 2, ///< Gain of 3 (only valid for stage 1) + SDADC_CHANNEL_STAGE_1_GAIN_4 = 3, ///< Gain of 4 + SDADC_CHANNEL_STAGE_1_GAIN_8 = 4, ///< Gain of 8 +} sdadc_channel_stage_1_gain_t; + +/** Per channel stage 2 gain options. */ +typedef enum e_sdadc_channel_stage_2_gain +{ + SDADC_CHANNEL_STAGE_2_GAIN_1 = 0, ///< Gain of 1 + SDADC_CHANNEL_STAGE_2_GAIN_2 = 1, ///< Gain of 2 + SDADC_CHANNEL_STAGE_2_GAIN_4 = 2, ///< Gain of 4 + SDADC_CHANNEL_STAGE_2_GAIN_8 = 3, ///< Gain of 8 +} sdadc_channel_stage_2_gain_t; + +/** Per channel oversampling ratio. */ +typedef enum e_sdadc_channel_oversampling +{ + SDADC_CHANNEL_OVERSAMPLING_64 = 0, ///< Oversampling ratio of 64 + SDADC_CHANNEL_OVERSAMPLING_128 = 1, ///< Oversampling ratio of 128 + SDADC_CHANNEL_OVERSAMPLING_256 = 2, ///< Oversampling ratio of 256 + SDADC_CHANNEL_OVERSAMPLING_512 = 3, ///< Oversampling ratio of 512 + SDADC_CHANNEL_OVERSAMPLING_1024 = 4, ///< Oversampling ratio of 1024 + SDADC_CHANNEL_OVERSAMPLING_2048 = 5, ///< Oversampling ratio of 2048 +} sdadc_channel_oversampling_t; + +/** Per channel polarity, valid for single-ended input only. */ +typedef enum e_sdadc_channel_polarity +{ + SDADC_CHANNEL_POLARITY_POSITIVE = 0, ///< Positive-side single-ended input + SDADC_CHANNEL_POLARITY_NEGATIVE = 1, ///< Negative-side single-ended input +} sdadc_channel_polarity_t; + +/** Per channel number of conversions to average before conversion end callback. */ +typedef enum e_sdadc_channel_average_t +{ + SDADC_CHANNEL_AVERAGE_NONE = 0, ///< Do not average (callback for each conversion) + SDADC_CHANNEL_AVERAGE_8 = 12, ///< Average 8 samples for each conversion end callback + SDADC_CHANNEL_AVERAGE_16 = 13, ///< Average 16 samples for each conversion end callback + SDADC_CHANNEL_AVERAGE_32 = 14, ///< Average 32 samples for each conversion end callback + SDADC_CHANNEL_AVERAGE_64 = 15, ///< Average 64 samples for each conversion end callback +} sdadc_channel_average_t; + +/** Per channel polarity, valid for negative-side single-ended input only. */ +typedef enum e_sdadc_channel_inversion +{ + SDADC_CHANNEL_INVERSION_OFF = 0, ///< Do not invert conversion result + SDADC_CHANNEL_INVERSION_ON = 1, ///< Invert conversion result +} sdadc_channel_inversion_t; + +/** Select a formula to specify the number of conversions. The following symbols are used in the formulas: + * * N: Number of conversions + * * n: sdadc_channel_cfg_t::coefficient_n, do not set to 0 if m is 0 + * * m: sdadc_channel_cfg_t::coefficient_m, do not set to 0 if n is 0 + * + * Either m or n must be non-zero. + */ +typedef enum e_sdadc_channel_count_formula +{ + SDADC_CHANNEL_COUNT_FORMULA_EXPONENTIAL = 0, ///< N = 32 * (2 ^ n - 1) + m * 2 ^ n + SDADC_CHANNEL_COUNT_FORMULA_LINEAR = 1, ///< N = (32 * n) + m +} sdadc_channel_count_formula_t; + +/** Calibration mode. */ +typedef enum e_sdadc_calibration +{ + SDADC_CALIBRATION_INTERNAL_GAIN_OFFSET = 0, ///< Use internal reference to calibrate offset and gain + SDADC_CALIBRATION_EXTERNAL_OFFSET = 1, ///< Use external reference to calibrate offset + SDADC_CALIBRATION_EXTERNAL_GAIN = 2, ///< Use external reference to calibrate gain +} sdadc_calibration_t; + +/** Structure to pass to the @ref adc_api_t::calibrate p_extend argument. */ +typedef struct st_sdadc_calibrate_args +{ + adc_channel_t channel; ///< Which channel to calibrate + sdadc_calibration_t mode; ///< Calibration mode +} sdadc_calibrate_args_t; + +/** SDADC per channel configuration. */ +typedef struct st_sdadc_channel_cfg +{ + union + { + struct + { + sdadc_channel_stage_2_gain_t stage_2_gain : 2; ///< Gain of PGA stage 2, must be 1 for single-ended input + sdadc_channel_stage_1_gain_t stage_1_gain : 3; ///< Gain of PGA stage 1, must be 1 for single-ended input + sdadc_channel_oversampling_t oversampling : 3; ///< Oversampling ratio, must be 256 in single-ended input + uint32_t : 6; + sdadc_channel_polarity_t polarity : 1; ///< Polarity, valid for single-ended mode only + sdadc_channel_input_t input : 1; ///< Single-ended or differential input + uint32_t coefficient_m : 5; ///< See ::sdadc_channel_count_formula_t + uint32_t coefficient_n : 3; ///< See ::sdadc_channel_count_formula_t + sdadc_channel_average_t average : 4; ///< Number of samples to average for each conversion result + sdadc_channel_inversion_t invert : 1; ///< Whether to invert negative single-ended input + uint32_t : 2; + sdadc_channel_count_formula_t count_formula : 1; ///< Linear or exponential formula used for number of conversions + } pgac_setting_b; + + uint32_t pgac_setting; + }; +} sdadc_channel_cfg_t; + +/** SDADC active channel configuration */ +typedef struct st_sdadc_scan_cfg +{ + uint32_t scan_mask; ///< Channels/bits: bit 0 is ch0; bit 15 is ch15. +} sdadc_scan_cfg_t; + +/** SDADC configuration extension. This extension is required and must be provided in adc_cfg_t::p_extend. */ +typedef struct st_sdadc_on_adc_cfg +{ + uint8_t conv_end_ipl; ///< Conversion end interrupt priority + IRQn_Type conv_end_irq; // Conversion end IRQ number + sdadc_vref_src_t vref_src; ///< Source of Vref (internal or external) + + /** Voltage of Vref, required for both internal and external Vref. If Vref is from an external source, the + * voltage must match the specified voltage within 3%. */ + sdadc_vref_voltage_t vref_voltage; + sdadc_channel_cfg_t const * p_channel_cfgs[SDADC_MAX_NUM_CHANNELS]; ///< Configuration for each channel, set to NULL if unused +} sdadc_extended_cfg_t; + +/** ADC instance control block. DO NOT INITIALIZE. Initialized in @ref adc_api_t::open(). */ +typedef struct +{ + adc_cfg_t const * p_cfg; + uint32_t opened; // Boolean to verify that the Unit has been initialized + uint32_t scan_mask; // Scan mask of enabled channels. + uint32_t scan_cfg_mask; // Scan mask of configured channels. + volatile uint8_t calib_status; // Calibration in progress if set + union + { + uint16_t results_16[SDADC_MAX_NUM_CHANNELS]; + uint32_t results_32[SDADC_MAX_NUM_CHANNELS]; + } results; +} sdadc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Interface Structure for user access */ +extern const adc_api_t g_adc_on_sdadc; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SDADC_Open(adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg); +fsp_err_t R_SDADC_ScanCfg(adc_ctrl_t * p_ctrl, void const * const p_extend); +fsp_err_t R_SDADC_InfoGet(adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info); +fsp_err_t R_SDADC_ScanStart(adc_ctrl_t * p_ctrl); +fsp_err_t R_SDADC_ScanGroupStart(adc_ctrl_t * p_ctrl, adc_group_mask_t group_id); +fsp_err_t R_SDADC_ScanStop(adc_ctrl_t * p_ctrl); +fsp_err_t R_SDADC_StatusGet(adc_ctrl_t * p_ctrl, adc_status_t * p_status); +fsp_err_t R_SDADC_Read(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data); +fsp_err_t R_SDADC_Read32(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data); +fsp_err_t R_SDADC_OffsetSet(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t const offset); +fsp_err_t R_SDADC_Calibrate(adc_ctrl_t * const p_ctrl, void const * p_extend); +fsp_err_t R_SDADC_Close(adc_ctrl_t * p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup ADC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sdhi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sdhi.h new file mode 100644 index 0000000000..d80b4daf3e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_sdhi.h @@ -0,0 +1,159 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SDHI_H +#define R_SDHI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sdhi_cfg.h" +#include "r_sdmmc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup SDHI + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SDHI_MAX_BLOCK_SIZE (512U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Private enumeration used in sdhi_instance_ctrl_t. */ +typedef enum e_sdhi_transfer_dir +{ + SDHI_TRANSFER_DIR_NONE, + SDHI_TRANSFER_DIR_READ, + SDHI_TRANSFER_DIR_WRITE +} sdhi_transfer_dir_t; + +/* Private structure used in sdhi_instance_ctrl_t. */ +typedef union +{ + uint32_t word; + + struct s_sdhi_event_type + { + uint32_t response_end : 1; // < response end detected + uint32_t reserved_1 : 1; + uint32_t access_end : 1; // < access end detected + uint32_t card_removed : 1; // < card removal detected by cd pin + uint32_t card_inserted : 1; // < card insertion detected by cd pin + uint32_t reserved_5 : 3; + uint32_t card_dat3_removed : 1; // < card removal detected by dat3 pin + uint32_t card_dat3_inserted : 1; // < card inserion detected by dat3 pin + uint32_t reserved_10 : 6; + uint32_t cmd_err : 1; // < command error + uint32_t crc_err : 1; // < crc error + uint32_t end_err : 1; // < end bit error + uint32_t dto : 1; // < data timeout + uint32_t ilw : 1; // < illegal write address + uint32_t ilr : 1; // < illegal read address + uint32_t rspt : 1; // < response timeout + uint32_t event_error : 1; // < all error flags combined + uint32_t bre : 1; // < buffer read enable + uint32_t bwe : 1; // < buffer write enable + uint32_t reserved_26 : 5; + uint32_t ila_err : 1; // < illegal access + } bit; +} sdhi_event_t; + +/** SDMMC instance control block. This is private to the FSP and should not be used or modified by the application. */ +typedef struct st_sdmmc_instance_ctrl +{ + uint32_t open; + sdmmc_cfg_t const * p_cfg; + sdmmc_device_t device; + bool sector_addressing; + bool transfer_in_progress; + bool initialized; + R_SDHI0_Type * p_reg; + volatile sdhi_event_t sdhi_event; + sdhi_transfer_dir_t transfer_dir; + uint8_t * p_transfer_data; + uint32_t transfer_blocks_total; + uint32_t transfer_block_current; + uint32_t transfer_block_size; + uint32_t aligned_buff[SDHI_MAX_BLOCK_SIZE / sizeof(uint32_t)]; + + void (* p_callback)(sdmmc_callback_args_t *); // Pointer to callback + sdmmc_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void * p_context; // Pointer to context to be passed into callback function +} sdhi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const sdmmc_api_t g_sdmmc_on_sdhi; + +/** @endcond */ + +/********************************************************************************************************************** + * Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_SDHI_Open(sdmmc_ctrl_t * const p_api_ctrl, sdmmc_cfg_t const * const p_cfg); +fsp_err_t R_SDHI_MediaInit(sdmmc_ctrl_t * const p_api_ctrl, sdmmc_device_t * const p_device); +fsp_err_t R_SDHI_Read(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const start_sector, + uint32_t const sector_count); +fsp_err_t R_SDHI_Write(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t const * const p_source, + uint32_t const start_sector, + uint32_t const sector_count); +fsp_err_t R_SDHI_ReadIo(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_data, + uint32_t const function, + uint32_t const address); +fsp_err_t R_SDHI_WriteIo(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_data, + uint32_t const function, + uint32_t const address, + sdmmc_io_write_mode_t const read_after_write); +fsp_err_t R_SDHI_ReadIoExt(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const function, + uint32_t const address, + uint32_t * const count, + sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode); +fsp_err_t R_SDHI_WriteIoExt(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t const * const p_source, + uint32_t const function, + uint32_t const address, + uint32_t const count, + sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode); +fsp_err_t R_SDHI_IoIntEnable(sdmmc_ctrl_t * const p_api_ctrl, bool enable); +fsp_err_t R_SDHI_StatusGet(sdmmc_ctrl_t * const p_api_ctrl, sdmmc_status_t * const p_status); +fsp_err_t R_SDHI_Erase(sdmmc_ctrl_t * const p_api_ctrl, uint32_t const start_sector, uint32_t const sector_count); +fsp_err_t R_SDHI_CallbackSet(sdmmc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(sdmmc_callback_args_t *), + void * const p_context, + sdmmc_callback_args_t * const p_callback_memory); +fsp_err_t R_SDHI_Close(sdmmc_ctrl_t * const p_api_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_SDHI_H + +/*******************************************************************************************************************//** + * @} (end addtogroup SDHI) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_spi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_spi.h new file mode 100644 index 0000000000..964f58d65a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_spi.h @@ -0,0 +1,195 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SPI_H +#define R_SPI_H + +/*******************************************************************************************************************//** + * @addtogroup SPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/************************************************************************************************* + * Type defines for the SPI interface API + *************************************************************************************************/ + +/** 3-Wire or 4-Wire mode. */ +typedef enum e_spi_ssl_mode +{ + SPI_SSL_MODE_SPI, ///< SPI operation (4-wire method) + SPI_SSL_MODE_CLK_SYN ///< Clock Synchronous operation (3-wire method) +} spi_ssl_mode_t; + +/** Burst Transfer Without Delay. */ +typedef enum e_spi_burst_transfer_without_delay +{ + SPI_BURST_TRANSFER_WITH_DELAY, ///< Interframe delay + SPI_BURST_TRANSFER_WITHOUT_DELAY ///< No interframe delay +} spi_burst_transfer_without_delay_t; + +/** Transmit Only (Half Duplex), or Full Duplex. */ +typedef enum e_spi_communication +{ + SPI_COMMUNICATION_FULL_DUPLEX, ///< Full-Duplex synchronous serial communication + SPI_COMMUNICATION_TRANSMIT_ONLY ///< Transit only serial communication +} spi_communication_t; + +/** Slave Select Polarity. */ +typedef enum e_spi_sslp +{ + SPI_SSLP_LOW, ///< SSLP signal polarity active low + SPI_SSLP_HIGH ///< SSLP signal polarity active high +} spi_ssl_polarity_t; + +/** The Slave Select Line */ +typedef enum e_spi_ssl_select +{ + SPI_SSL_SELECT_SSL0, ///< Select SSL0 + SPI_SSL_SELECT_SSL1, ///< Select SSL1 + SPI_SSL_SELECT_SSL2, ///< Select SSL2 + SPI_SSL_SELECT_SSL3 ///< Select SSL3 +} spi_ssl_select_t; + +/** MOSI Idle Behavior. */ +typedef enum e_spi_mosi_idle_value_fixing +{ + SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, ///< MOSI output value=value set in MOIFV bit + SPI_MOSI_IDLE_VALUE_FIXING_LOW, ///< MOSIn level low during MOSI idling + SPI_MOSI_IDLE_VALUE_FIXING_HIGH ///< MOSIn level high during MOSI idling +} spi_mosi_idle_value_fixing_t; + +/** Parity Mode */ +typedef enum e_spi_parity_mode +{ + SPI_PARITY_MODE_DISABLE, ///< Disable parity + SPI_PARITY_MODE_ODD, ///< Select even parity + SPI_PARITY_MODE_EVEN ///< Select odd parity +} spi_parity_t; + +/** Byte Swapping Enable/Disable. */ +typedef enum +{ + SPI_BYTE_SWAP_DISABLE = 0, ///< Disable Byte swapping for 16/32-Bit transfers + SPI_BYTE_SWAP_ENABLE ///< Enable Byte swapping for 16/32-Bit transfers +} spi_byte_swap_t; + +/** Delay count for SPI delay settings. */ +typedef enum e_spi_clock_delay_count +{ + SPI_DELAY_COUNT_1, ///< Set RSPCK delay count to 1 RSPCK + SPI_DELAY_COUNT_2, ///< Set RSPCK delay count to 2 RSPCK + SPI_DELAY_COUNT_3, ///< Set RSPCK delay count to 3 RSPCK + SPI_DELAY_COUNT_4, ///< Set RSPCK delay count to 4 RSPCK + SPI_DELAY_COUNT_5, ///< Set RSPCK delay count to 5 RSPCK + SPI_DELAY_COUNT_6, ///< Set RSPCK delay count to 6 RSPCK + SPI_DELAY_COUNT_7, ///< Set RSPCK delay count to 7 RSPCK + SPI_DELAY_COUNT_8 ///< Set RSPCK delay count to 8 RSPCK +} spi_delay_count_t; + +/** SPI Clock Divider settings. */ +typedef struct +{ + uint8_t spbr; ///< SPBR register setting + uint8_t brdv : 2; ///< BRDV setting in SPCMD0 +} rspck_div_setting_t; + +/** Extended SPI interface configuration */ +typedef struct st_spi_extended_cfg +{ + spi_ssl_mode_t spi_clksyn; ///< Select spi or clock syn mode operation + spi_communication_t spi_comm; ///< Select full-duplex or transmit-only communication + spi_ssl_polarity_t ssl_polarity; ///< Select SSLn signal polarity + spi_ssl_select_t ssl_select; ///< Select which slave to use: 0-SSL0, 1-SSL1, 2-SSL2, 3-SSL3 + spi_mosi_idle_value_fixing_t mosi_idle; ///< Select MOSI idle fixed value and selection + spi_parity_t parity; ///< Select parity and enable/disable parity + spi_byte_swap_t byte_swap; ///< Select byte swap mode + rspck_div_setting_t spck_div; ///< Register values for configuring the SPI Clock Divider. + spi_delay_count_t spck_delay; ///< SPI Clock Delay Register Setting + spi_delay_count_t ssl_negation_delay; ///< SPI Slave Select Negation Delay Register Setting + spi_delay_count_t next_access_delay; ///< SPI Next-Access Delay Register Setting + spi_burst_transfer_without_delay_t burst_interframe_delay; ///< SPI Between Burst Transfer Frames Delay Select +} spi_extended_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_api_t::open is called. */ +typedef struct st_spi_instance_ctrl +{ + uint32_t open; ///< Indicates whether the open() API has been successfully called. + spi_cfg_t const * p_cfg; ///< Pointer to instance configuration + R_SPI0_Type * p_regs; ///< Base register for this channel + void const * p_tx_data; ///< Buffer to transmit + void * p_rx_data; ///< Buffer to receive + uint32_t tx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + uint32_t rx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + uint32_t count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + spi_bit_width_t bit_width; ///< Bits per Data frame (8-bit, 16-bit, 32-bit) + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} spi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_api_t g_spi_on_spi; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); + +fsp_err_t R_SPI_Read(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_Write(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_Close(spi_ctrl_t * const p_api_ctrl); + +fsp_err_t R_SPI_CalculateBitrate(uint32_t bitrate, rspck_div_setting_t * spck_div); +fsp_err_t R_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end ingroup SPI) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_spi_b.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_spi_b.h new file mode 100644 index 0000000000..5d870a9109 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_spi_b.h @@ -0,0 +1,203 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SPI_B_H +#define R_SPI_B_H + +/*******************************************************************************************************************//** + * @addtogroup SPI_B + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/************************************************************************************************* + * Type defines for the SPI interface API + *************************************************************************************************/ + +/** 3-Wire or 4-Wire mode. */ +typedef enum e_spi_b_ssl_mode +{ + SPI_B_SSL_MODE_SPI, ///< SPI operation (4-wire method) + SPI_B_SSL_MODE_CLK_SYN ///< Clock Synchronous operation (3-wire method) +} spi_b_ssl_mode_t; + +/** Burst Transfer Without Delay. */ +typedef enum e_spi_b_burst_transfer_without_delay +{ + SPI_B_BURST_TRANSFER_WITH_DELAY, ///< Interframe delay + SPI_B_BURST_TRANSFER_WITHOUT_DELAY ///< No interframe delay +} spi_b_burst_transfer_without_delay_t; + +/** Transmit Only (Half Duplex), or Full Duplex. */ +typedef enum e_spi_b_communication +{ + SPI_B_COMMUNICATION_FULL_DUPLEX, ///< Full-Duplex synchronous serial communication + SPI_B_COMMUNICATION_TRANSMIT_ONLY, ///< Transit only serial communication +} spi_b_communication_t; + +/** Slave Select Polarity. */ +typedef enum e_spi_b_sslp +{ + SPI_B_SSLP_LOW, ///< SSLP signal polarity active low + SPI_B_SSLP_HIGH ///< SSLP signal polarity active high +} spi_b_ssl_polarity_t; + +/** The Slave Select Line */ +typedef enum e_spi_b_ssl_select +{ + SPI_B_SSL_SELECT_SSL0, ///< Select SSL0 + SPI_B_SSL_SELECT_SSL1, ///< Select SSL1 + SPI_B_SSL_SELECT_SSL2, ///< Select SSL2 + SPI_B_SSL_SELECT_SSL3 ///< Select SSL3 +} spi_b_ssl_select_t; + +/** MOSI Idle Behavior. */ +typedef enum e_spi_b_mosi_idle_value_fixing +{ + SPI_B_MOSI_IDLE_VALUE_FIXING_DISABLE, ///< MOSI output value=value set in MOIFV bit + SPI_B_MOSI_IDLE_VALUE_FIXING_LOW, ///< MOSIn level low during MOSI idling + SPI_B_MOSI_IDLE_VALUE_FIXING_HIGH ///< MOSIn level high during MOSI idling +} spi_b_mosi_idle_value_fixing_t; + +/** Parity Mode */ +typedef enum e_spi_b_parity_mode +{ + SPI_B_PARITY_MODE_DISABLE, ///< Disable parity + SPI_B_PARITY_MODE_ODD, ///< Select even parity + SPI_B_PARITY_MODE_EVEN ///< Select odd parity +} spi_b_parity_t; + +/** Byte Swapping Enable/Disable. */ +typedef enum +{ + SPI_B_BYTE_SWAP_DISABLE = 0, ///< Disable Byte swapping for 16/32-Bit transfers + SPI_B_BYTE_SWAP_ENABLE ///< Enable Byte swapping for 16/32-Bit transfers +} spi_b_byte_swap_t; + +/** Delay count for SPI delay settings. */ +typedef enum e_spi_b_clock_delay_count +{ + SPI_B_DELAY_COUNT_1, ///< Set RSPCK delay count to 1 RSPCK + SPI_B_DELAY_COUNT_2, ///< Set RSPCK delay count to 2 RSPCK + SPI_B_DELAY_COUNT_3, ///< Set RSPCK delay count to 3 RSPCK + SPI_B_DELAY_COUNT_4, ///< Set RSPCK delay count to 4 RSPCK + SPI_B_DELAY_COUNT_5, ///< Set RSPCK delay count to 5 RSPCK + SPI_B_DELAY_COUNT_6, ///< Set RSPCK delay count to 6 RSPCK + SPI_B_DELAY_COUNT_7, ///< Set RSPCK delay count to 7 RSPCK + SPI_B_DELAY_COUNT_8 ///< Set RSPCK delay count to 8 RSPCK +} spi_b_delay_count_t; + +/** SPI communication clock source. */ +typedef enum e_spi_b_clock_source +{ + SPI_B_CLOCK_SOURCE_SCISPICLK, + SPI_B_CLOCK_SOURCE_PCLK +} spi_b_clock_source_t; + +/** SPI Clock Divider settings. */ +typedef struct +{ + uint8_t spbr; ///< SPBR register setting + uint8_t brdv : 2; ///< BRDV setting in SPCMD0 +} rspck_div_setting_t; + +/** Extended SPI interface configuration */ +typedef struct st_spi_b_extended_cfg +{ + spi_b_ssl_mode_t spi_clksyn; ///< Select SPI or Clock Synchronous mode operation + spi_b_communication_t spi_comm; ///< Select full-duplex or transmit-only communication + spi_b_ssl_polarity_t ssl_polarity; ///< Select SSLn signal polarity + spi_b_ssl_select_t ssl_select; ///< Select which slave to use: 0-SSL0, 1-SSL1, 2-SSL2, 3-SSL3 + spi_b_mosi_idle_value_fixing_t mosi_idle; ///< Select MOSI idle fixed value and selection + spi_b_parity_t parity; ///< Select parity and enable/disable parity + spi_b_byte_swap_t byte_swap; ///< Select byte swap mode + spi_b_clock_source_t clock_source; ///< Communication clock source (TCLK). + rspck_div_setting_t spck_div; ///< Register values for configuring the SPI Clock Divider. + spi_b_delay_count_t spck_delay; ///< SPI Clock Delay Register Setting + spi_b_delay_count_t ssl_negation_delay; ///< SPI Slave Select Negation Delay Register Setting + spi_b_delay_count_t next_access_delay; ///< SPI Next-Access Delay Register Setting + spi_b_burst_transfer_without_delay_t burst_interframe_delay; ///< SPI Between Burst Transfer Frames Delay Select +} spi_b_extended_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_api_t::open is called. */ +typedef struct st_spi_b_instance_ctrl +{ + uint32_t open; ///< Indicates whether the open() API has been successfully called. + spi_cfg_t const * p_cfg; ///< Pointer to instance configuration + R_SPI_B0_Type * p_regs; ///< Base register for this channel + void const * p_tx_data; ///< Buffer to transmit + void * p_rx_data; ///< Buffer to receive + uint32_t tx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + uint32_t rx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + uint32_t count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + spi_bit_width_t bit_width; ///< Bits per Data frame (8-bit, 16-bit, 32-bit) + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} spi_b_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_api_t g_spi_on_spi_b; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SPI_B_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); + +fsp_err_t R_SPI_B_Read(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_B_Write(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_B_WriteRead(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_B_Close(spi_ctrl_t * const p_api_ctrl); + +fsp_err_t R_SPI_B_CalculateBitrate(uint32_t bitrate, spi_b_clock_source_t clock_source, rspck_div_setting_t * spck_div); +fsp_err_t R_SPI_B_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end ingroup SPI_B) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ssi.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ssi.h new file mode 100644 index 0000000000..279f01a4df --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ssi.h @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup SSI + * @{ + **********************************************************************************************************************/ + +#ifndef R_SSI_H +#define R_SSI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_i2s_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Audio clock source. */ +typedef enum e_ssi_audio_clock +{ + SSI_AUDIO_CLOCK_EXTERNAL = 0, ///< Audio clock source is the AUDIO_CLK input pin + SSI_AUDIO_CLOCK_INTERNAL = 1, ///< Audio clock source is internal connection to a MCU specific GPT channel output +} ssi_audio_clock_t; + +/** Bit clock division ratio. Bit clock frequency = audio clock frequency / bit clock division ratio. */ +typedef enum e_ssi_clock_div +{ + SSI_CLOCK_DIV_1 = 0, ///< Clock divisor 1 + SSI_CLOCK_DIV_2 = 1, ///< Clock divisor 2 + SSI_CLOCK_DIV_4 = 2, ///< Clock divisor 4 + SSI_CLOCK_DIV_6 = 8, ///< Clock divisor 6 + SSI_CLOCK_DIV_8 = 3, ///< Clock divisor 8 + SSI_CLOCK_DIV_12 = 9, ///< Clock divisor 12 + SSI_CLOCK_DIV_16 = 4, ///< Clock divisor 16 + SSI_CLOCK_DIV_24 = 10, ///< Clock divisor 24 + SSI_CLOCK_DIV_32 = 5, ///< Clock divisor 32 + SSI_CLOCK_DIV_48 = 11, ///< Clock divisor 48 + SSI_CLOCK_DIV_64 = 6, ///< Clock divisor 64 + SSI_CLOCK_DIV_96 = 12, ///< Clock divisor 96 + SSI_CLOCK_DIV_128 = 7, ///< Clock divisor 128 +} ssi_clock_div_t; + +/** Channel instance control block. DO NOT INITIALIZE. Initialization occurs when @ref i2s_api_t::open is called. */ +typedef struct st_ssi_instance_ctrl +{ + uint32_t open; // Whether or not this control block is initialized + i2s_cfg_t const * p_cfg; // Initial configurations. + R_SSI0_Type * p_reg; // Pointer to SSI register base address + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + void const * p_tx_src; + + /* Size of source buffer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_samples; + + /* Destination buffer pointer used to fill from hardware FIFO in receive ISR. */ + void * p_rx_dest; + + /* Size of destination buffer used to fill from hardware FIFO in receive ISR. */ + uint32_t rx_dest_samples; + transfer_size_t fifo_access_size; // Access the FIFO as 1 byte, 2 bytes, or 4 bytes + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2s_callback_args_t *); + i2s_callback_args_t * p_callback_memory; + void * p_context; // < User defined context passed into callback function +} ssi_instance_ctrl_t; + +/** SSI configuration extension. This extension is optional. */ +typedef struct st_ssi_extended_cfg +{ + ssi_audio_clock_t audio_clock; ///< Audio clock source, default is SSI_AUDIO_CLOCK_EXTERNAL + ssi_clock_div_t bit_clock_div; ///< Select bit clock division ratio +} ssi_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +extern const i2s_api_t g_i2s_on_ssi; + +/** @endcond */ + +/********************************************************************************************************************** + * Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_SSI_Open(i2s_ctrl_t * const p_ctrl, i2s_cfg_t const * const p_cfg); +fsp_err_t R_SSI_Stop(i2s_ctrl_t * const p_ctrl); +fsp_err_t R_SSI_StatusGet(i2s_ctrl_t * const p_ctrl, i2s_status_t * const p_status); +fsp_err_t R_SSI_Write(i2s_ctrl_t * const p_ctrl, void const * const p_src, uint32_t const bytes); +fsp_err_t R_SSI_Read(i2s_ctrl_t * const p_ctrl, void * const p_dest, uint32_t const bytes); +fsp_err_t R_SSI_WriteRead(i2s_ctrl_t * const p_ctrl, void const * const p_src, void * const p_dest, + uint32_t const bytes); +fsp_err_t R_SSI_Mute(i2s_ctrl_t * const p_ctrl, i2s_mute_t const mute_enable); +fsp_err_t R_SSI_Close(i2s_ctrl_t * const p_ctrl); +fsp_err_t R_SSI_CallbackSet(i2s_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2s_callback_args_t *), + void * const p_context, + i2s_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_SSI_H + +/*******************************************************************************************************************//** + * @} (end defgroup SSI) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tau.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tau.h new file mode 100644 index 0000000000..83a1b3ce8a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tau.h @@ -0,0 +1,196 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_TAU_H +#define R_TAU_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_tau_cfg.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup TAU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Timer function */ +typedef enum e_tau_function +{ + TAU_FUNCTION_INTERVAL = 0U, ///< Interval Timer Function + TAU_FUNCTION_SQUARE_WAVE = 1U, ///< Square Wave Function + TAU_FUNCTION_EXTERNAL_EVENT_COUNT = 2U, ///< External Event Count Function + TAU_FUNCTION_DIVIDER = 3U, ///< Divider Function + TAU_FUNCTION_INPUT_PULSE_INTERVAL_MEASUREMENT = 4U, ///< Input Pulse Interval Function + TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT = 5U, ///< Low Level Width Measure Function + TAU_FUNCTION_HIGH_LEVEL_WIDTH_MEASUREMENT = 6U, ///< High Level Width Measure Function + TAU_FUNCTION_DELAY_COUNT = 7U ///< Delay Count Function +} tau_function_t; + +/** Timer bit mode */ +typedef enum e_tau_bit_mode +{ + TAU_BIT_MODE_16BIT = 0U, ///< 16-Bit Timer Mode + TAU_BIT_MODE_HIGHER_8BIT = 1U, ///< Higher 8-bit Timer Mode + TAU_BIT_MODE_LOWER_8BIT = 2U, ///< Lower 8-bit Timer Mode + TAU_BIT_MODE_HIGHER_LOWER_8BIT = 3U, ///< Lower and Higher 8-bit Timer Mode +} tau_bit_mode_t; + +/** Timer operation clock. */ +typedef enum e_tau_operation_ck +{ + TAU_OPERATION_CK00 = 0U, + TAU_OPERATION_CK01 = 2U, + TAU_OPERATION_CK02 = 1U, + TAU_OPERATION_CK03 = 3U +} tau_operation_ck_t; + +/** Trigger edge for pulse period measurement mode, high-low measurement, divider, delay counter + * and event counting mode. */ +typedef enum e_tau_trigger_edge +{ + TAU_TRIGGER_EDGE_FALLING = 0U, ///< Measurement starts or events are counted on falling edge + TAU_TRIGGER_EDGE_RISING = 1U, ///< Measurement starts or events are counted on rising edge + TAU_TRIGGER_EDGE_BOTH = 2U, ///< Events are counted on both edges (pulse period mode and high-low measurement) +} tau_trigger_edge_t; + +/** Interrupt and starting Count Mode */ +typedef enum e_tau_interrupt_opirq_bit +{ + /* When OPIRQ bit is 0. + * + Interval Timer, Square Wave, Divider, External Event Count and Input Pulse Measurement function : Timer + * interrupt is not generated when counting is started (timer output does not change, either). + * + High-Low Measurement function Timer: interrupt is not generated when counting is started (timer output + * does not change, either). Start trigger is invalid during counting operation. At that time interrupt is not generated. + * + Delay Counter function: Start trigger is invalid during counting operation. At that time, interrupt is not generated. + */ + TAU_INTERRUPT_OPIRQ_BIT_RESET = 0U, + + /* When OPIRQ bit is 1. + * + Interval Timer, Square Wave, Divider and Input Pulse Measurement function: Timer interrupt is generated when counting is + * started (timer output also changes). + * + Delay Counter function: Start trigger is valid during counting operation. At that time, interrupt is not generated. + */ + TAU_INTERRUPT_OPIRQ_BIT_SET = 1U, +} tau_interrupt_opirq_bit_t; + +/** Input source */ +typedef enum e_tau_input_source +{ + TAU_INPUT_SOURCE_TI_PIN = 0U, ///< Timer Input Source is input pin + TAU_INPUT_SOURCE_ELC = 1U, ///< ELC Timer Input Source + TAU_INPUT_SOURCE_RXD_PIN = 2U, ///< Timer Input Source is RXD pin + TAU_INPUT_SOURCE_RXD2_PIN = 2U, ///< DEPRECATED, do not use + TAU_INPUT_SOURCE_MOCO = 3U, ///< Timer Input Source is MOCO + TAU_INPUT_SOURCE_LOCO = 4U, ///< Timer Input Source is LOCO + TAU_INPUT_SOURCE_FSUB = 5U, ///< Timer Input Source is FSUB + TAU_INPUT_SOURCE_NONE = 6U, ///< No Timer Input Source +} tau_input_source_t; + +/** Level of TAU pin */ +typedef enum e_tau_pin_output_cfg +{ + TAU_PIN_OUTPUT_CFG_START_LEVEL_LOW = 0U, ///< Pin level low + TAU_PIN_OUTPUT_CFG_START_LEVEL_HIGH = 1U, ///< Pin level high + TAU_PIN_OUTPUT_CFG_DISABLED = 2U, ///< Not used as output pin +} tau_pin_output_cfg_t; + +/** Input filter, applies TAU in high-low measurement, pulse width measurement, delay counter, divider, + * or event counter mode. */ +typedef enum e_tau_input_noise_filter +{ + TAU_INPUT_NOISE_FILTER_DISABLE = 0U, ///< Disable noise filter + TAU_INPUT_NOISE_FILTER_ENABLE = 1U ///< Enable noise filter +} tau_input_noise_filter_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_tau_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations + + uint16_t channel_mask; // Channel bitmask + uint16_t channel_bitmode_mask; // Channel bitmode mask + + void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs. + + void * p_context; // Pointer to context to be passed into callback function +} tau_instance_ctrl_t; + +/** Optional TAU extension data structure.*/ +typedef struct st_tau_extended_cfg +{ + tau_interrupt_opirq_bit_t opirq : 1; ///< Setting of starting count and interrupt + tau_function_t tau_func; ///< Setting of Function for TAU + tau_bit_mode_t bit_mode; ///< Setting of 16-bit timer or 8-bit timer + + /* Output pin settings. */ + tau_pin_output_cfg_t initial_output; ///< Setting of Function for TAU + + /* Input settings. */ + tau_input_source_t input_source; + tau_input_noise_filter_t tau_filter; ///< Input filter for TAU + tau_trigger_edge_t trigger_edge; ///< Trigger edge to start pulse period measurement or count external event + + tau_operation_ck_t operation_clock; + + uint16_t period_higher_8bit_counts; ///< Period in raw higher 8 bit timer counts + uint8_t higher_8bit_cycle_end_ipl; ///< Cycle higher 8-bit end interrupt priority + IRQn_Type higher_8bit_cycle_end_irq; ///< Cycle higher 8-bit end interrupt +} tau_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_tau; + +/** @endcond */ + +fsp_err_t R_TAU_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_TAU_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TAU_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TAU_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TAU_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TAU_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TAU_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_TAU_CompareMatchSet(timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel); +fsp_err_t R_TAU_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_TAU_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_TAU_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_TAU_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_TAU_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TAU_LinMeasurementFuncSwitch(timer_ctrl_t * const p_ctrl, tau_function_t func); + +/*******************************************************************************************************************//** + * @} (end defgroup TAU) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ + +FSP_FOOTER + +#endif // R_TAU_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tau_pwm.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tau_pwm.h new file mode 100644 index 0000000000..b8ee04dbe4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tau_pwm.h @@ -0,0 +1,172 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_TAU_PWM_H +#define R_TAU_PWM_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_tau_pwm_cfg.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup TAU_PWM + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Even though there are 8 channels, there always has to be one slave.. (slave > master) + * so valid master channels numbers are 0-6, and valid slave numbers are 1-7 */ +#define TAU_PWM_MAX_CHANNEL_NUM (7U) + +#if TAU_PWM_CFG_MULTI_SLAVE_ENABLE + #define TAU_PWM_MAX_NUM_SLAVE_CHANNELS (TAU_PWM_MAX_CHANNEL_NUM) +#else + #define TAU_PWM_MAX_NUM_SLAVE_CHANNELS (1) +#endif +#define TAU_PWM_SLAVE_CHANNEL_UNUSED (0) /* 0 is an invalid slave channel since master channel < slave channel*/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Operation clock. */ +typedef enum e_tau_pwm_operation_clock +{ + TAU_PWM_OPERATION_CLOCK_CK00 = 0U, ///< Operation Clock CK00 + TAU_PWM_OPERATION_CLOCK_CK01 = 2U, ///< Operation CLock CK01 +} tau_pwm_operation_clock_t; + +/** Trigger Source */ +typedef enum e_tau_pwm_source +{ + TAU_PWM_SOURCE_PIN_INPUT = 0U, ///< Use TI0n pin input as trigger source + TAU_PWM_SOURCE_ELC_EVENT = 1U, ///< Use ELC events as trigger source +} tau_pwm_source_t; + +/**TI0n pin input edge */ +typedef enum e_tau_pwm_detect_edge +{ + TAU_PWM_DETECT_EDGE_FALLING = 0U, ///< Detects falling edge + TAU_PWM_DETECT_EDGE_RISING = 1U, ///< Detects rising edge + TAU_PWM_DETECT_EDGES_BOTH = 2U, ///< Detects both edges +} tau_pwm_detect_edge_t; + +/** Level of TAU pin */ +typedef enum e_tau_pwm_output_level +{ + TAU_PWM_OUTPUT_LEVEL_LOW = 0U, ///< Pin level low + TAU_PWM_OUTPUT_LEVEL_HIGH = 1U, ///< Pin level high +} tau_pwm_output_level_t; + +/** Timer output polarity */ +typedef enum e_tau_pwm_output_polarity +{ + TAU_PWM_OUTPUT_POLARITY_ACTIVE_HIGH = 0U, ///< Positive logic output (active-high) + TAU_PWM_OUTPUT_POLARITY_ACTIVE_LOW = 1U, ///< Negative logic output (active-low) +} tau_pwm_output_polarity_t; + +/** Input/Output pins, used to select which duty cycle to update in R_TAU_PWM_DutyCycleSet(). */ +typedef enum e_tau_pwm_io_pin +{ + TAU_PWM_IO_PIN_CHANNEL_0 = 0, ///< I/O pin of channel 0 + TAU_PWM_IO_PIN_CHANNEL_1 = 1, ///< I/O pin of channel 1 + TAU_PWM_IO_PIN_CHANNEL_2 = 2, ///< I/O pin of channel 2 + TAU_PWM_IO_PIN_CHANNEL_3 = 3, ///< I/O pin of channel 3 + TAU_PWM_IO_PIN_CHANNEL_4 = 4, ///< I/O pin of channel 4 + TAU_PWM_IO_PIN_CHANNEL_5 = 5, ///< I/O pin of channel 5 + TAU_PWM_IO_PIN_CHANNEL_6 = 6, ///< I/O pin of channel 6 + TAU_PWM_IO_PIN_CHANNEL_7 = 7, ///< I/O pin of channel 7 +} tau_pwm_io_pin_t; + +/** TAU_PWM per channel configuration. */ +typedef struct st_tau_pwm_channel_cfg +{ + uint8_t channel; ///< Slave Channel Number (1..7) + uint16_t duty_cycle_counts; ///< One-shot: Pulse_width_counts; PWM: Duty_cycle_counts + + /* Output pin settings. */ + tau_pwm_output_level_t output_level; ///< Setting of output level for TAU + tau_pwm_output_polarity_t output_polarity; ///< Setting of output polarity for TAU + + uint8_t cycle_end_ipl; ///< TAU slave channel IPL + IRQn_Type cycle_end_irq; ///< TAU slave channel IRQ +} tau_pwm_channel_cfg_t; + +/** Extended configuration structure for TAU_PWM */ +typedef struct st_tau_pwm_extended_cfg +{ + tau_pwm_operation_clock_t operation_clock; ///< Setting of operation clock for master and slave channels + + /* Input settings. */ + tau_pwm_source_t trigger_source; ///< Trigger source for master channel + tau_pwm_detect_edge_t detect_edge; ///< Trigger edge to start pulse period measurement + + tau_pwm_channel_cfg_t const * p_slave_channel_cfgs[TAU_PWM_MAX_NUM_SLAVE_CHANNELS]; ///< Configuration for each slave channel, at least 1 slave channel is required +} tau_pwm_extended_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_tau_pwm_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations + uint8_t channels_mask; // Masked value of all channels used + uint8_t master_channel_mask; // Masked value of master channel used + uint8_t slave_channels_mask; // Masked value of slave channels used + + void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs. + void * p_context; // Pointer to context to be passed into callback function +} tau_pwm_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Interface Structure for user access */ +extern const timer_api_t g_timer_on_tau_pwm; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_TAU_PWM_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TAU_PWM_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TAU_PWM_Reset(timer_ctrl_t * const p_ctrl); + +fsp_err_t R_TAU_PWM_Enable(timer_ctrl_t * const p_ctrl); + +fsp_err_t R_TAU_PWM_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_TAU_PWM_CompareMatchSet(timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel); +fsp_err_t R_TAU_PWM_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_TAU_PWM_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_TAU_PWM_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_TAU_PWM_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_TAU_PWM_Close(timer_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup TAU_PWM) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tml.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tml.h new file mode 100644 index 0000000000..632d891c25 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_tml.h @@ -0,0 +1,114 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_TML_H +#define R_TML_H + +/*******************************************************************************************************************//** + * @addtogroup TML + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for TML FITL0, FITL1 clock source */ +typedef enum e_tml_clock +{ + TML_CLOCK_HOCO = 1U, ///< HOCO + TML_CLOCK_MOCO = 2U, ///< MOCO + TML_CLOCK_MOSC = 3U, ///< MOSC + TML_CLOCK_LOCO_SOSC = 4U, ///< SOSC + TML_CLOCK_ELC_EVENT = 5U, ///< Event input from the ELC +} tml_clock_t; + +/** Enumeration for TML FITL2 capture trigger source */ +typedef enum e_tml_capture_trigger +{ + TML_CAPTURE_TRIGGER_SOFTWARE = 0U, ///< Software trigger + TML_CAPTURE_TRIGGER_ITLCMP01 = 1U, ///< Interrupt on compare match with ITLCMP01 + TML_CAPTURE_TRIGGER_LOCO_SOSC = 2U, ///< LOCO/SOSC (rising edge) + TML_CAPTURE_TRIGGER_EVENT_ELC = 3U, ///< Event input from ELC (rising edge) +} tml_capture_trigger_t; + +/** Enumeration for status of 16-bit counter (ITL000 + ITL001) after completion of capturing */ +typedef enum e_tml_counter_status +{ + TML_COUNTER_STATUS_RETAINED_AFTER_CAPTURING = 0U, ///< 16-bit counter (ITL000 + ITL001) is retained after the completion of capturing + TML_COUNTER_STATUS_CLEARED_AFTER_CAPTURING = 1U, ///< 16-bit counter (ITL000 + ITL001) is cleared after the completion of capturing +} tml_counter_status_t; + +/** User configuration structure, used in open function */ +typedef struct st_tml_extended_cfg +{ + tml_capture_trigger_t capture_trigger; ///< Select the capture source for capture channel + tml_counter_status_t counter_status; ///< Status of 16-bit counter (ITL000 + ITL001) after completion of capturing +} tml_extended_cfg_t; + +/** TML instance control block. */ +typedef struct st_tml_instance_ctrl +{ + uint32_t open; ///< Used to determine if the channel is configured + const timer_cfg_t * p_cfg; ///< Pointer to the configuration block. + uint8_t channel_mask; ///< Mask value of channel used. + + void (* p_callback)(timer_callback_args_t *); ///< Pointer to callback that is called when a timer event occurs. + void * p_context; ///< Pointer to context to be passed into callback function +} tml_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_tml; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_TML_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_TML_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TML_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TML_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TML_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TML_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_TML_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_TML_CompareMatchSet(timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel); +fsp_err_t R_TML_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_TML_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_TML_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_TML_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_TML_Close(timer_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup TML) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_uarta.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_uarta.h new file mode 100644 index 0000000000..c273088544 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_uarta.h @@ -0,0 +1,178 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_UARTA_H +#define R_UARTA_H + +/*******************************************************************************************************************//** + * @addtogroup UARTA + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_uarta_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define UARTA_UTAnCK_LOCO_SETTING (0x08U) // for LOCO or FSXP +#define UARTA_UTAnCK_SOSC_SETTING (0x09U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for UARTA clock source */ +typedef enum e_uarta_clock_source +{ + UARTA_CLOCK_SOURCE_SOSC_LOCO = 0U, ///< SOSC/LOCO + UARTA_CLOCK_SOURCE_LOCO = UARTA_CLOCK_SOURCE_SOSC_LOCO, ///< LOCO + UARTA_CLOCK_SOURCE_MOSC = 1U, ///< MOSC + UARTA_CLOCK_SOURCE_HOCO = 2U, ///< HOCO + UARTA_CLOCK_SOURCE_MOCO = 3U, ///< MOCO + UARTA_CLOCK_SOURCE_SOSC = 4U, ///< SOSC +} uarta_clock_source_t; + +/** Enumeration for UARTA clock divider */ +typedef enum e_uarta_clock_div +{ + UARTA_CLOCK_DIV_1 = 0U, ///< fSEL/1 + UARTA_CLOCK_DIV_2, ///< fSEL/2 + UARTA_CLOCK_DIV_4, ///< fSEL/4 + UARTA_CLOCK_DIV_8, ///< fSEL/8 + UARTA_CLOCK_DIV_16, ///< fSEL/16 + UARTA_CLOCK_DIV_32, ///< fSEL/32 + UARTA_CLOCK_DIV_64, ///< fSEL/64 + UARTA_CLOCK_DIV_COUNT, ///< Total number of clock divider options. +} uarta_clock_div_t; + +/** Enabled/Disabled Clock output */ +typedef enum e_uarta_clock_out +{ + UARTA_CLOCK_OUTPUT_DISABLED = 0U, ///< Disables CLKAn output + UARTA_CLOCK_OUTPUT_ENABLED = 1U, ///< Enables CLKAn output +} uarta_clock_out_t; + +/** Transmission/reception order configuration. */ +typedef enum e_uarta_dir_bit +{ + UARTA_DIR_BIT_MSB_FIRST = 0U, ///< MSB first + UARTA_DIR_BIT_LSB_FIRST = 1U, ///< LSB first +} uarta_dir_bit_t; + +/** Transmission/reception level configuration. */ +typedef enum e_uarta_alv_bit +{ + UARTA_ALV_BIT_POSITIVE_LOGIC = 0U, ///< Positive logic (wait state = high level, start bit = low level, stop bit = high level) + UARTA_ALV_BIT_NEGATIVE_LOGIC = 1U, ///< Negative logic (wait state = low level, start bit = high level, stop bit = low level) +} uarta_alv_bit_t; + +/** Register settings to achieve a desired baud rate and modulation duty. */ +typedef struct st_uarta_baud_setting +{ + union + { + uint8_t utanck_clock; + + struct + { + uint8_t utanck : 4; ///< UARTA operation clock select (f_UTA0n) + uint8_t utasel : 2; ///< fSEL clock select + uint8_t : 2; + } utanck_clock_b; + }; + uint8_t brgca; ///< Baud rate generator control setting + uint16_t delay_time; ///< Delay time (us) required to enable TX at open +} uarta_baud_setting_t; + +/** UART on UARTA device Configuration */ +typedef struct st_uarta_extended_cfg +{ + uarta_dir_bit_t transfer_dir; ///< Transmission/reception order configuration + uarta_alv_bit_t transfer_level; ///< Transmission/reception level configuration + uarta_clock_out_t clock_output; ///< Disable/Enable clock output + uarta_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. +} uarta_extended_cfg_t; + +/** UARTA instance control block. */ +typedef struct st_uarta_instance_ctrl +{ + /* Parameters to control UARTA peripheral device */ + uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise + uint32_t open; // Used to determine if the channel is configured + + /* Source buffer pointer used for transmitting data. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used for transmitting data. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Base register for this channel. */ + R_UARTA0_Type * p_reg; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Pointer to callback that is called when a uart_event_t occurs. */ + void (* p_callback)(uart_callback_args_t *); + + /* Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. */ + uart_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void * p_context; +} uarta_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_uarta; + +/** @endcond */ + +fsp_err_t R_UARTA_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_UARTA_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_UARTA_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_UARTA_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_UARTA_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); +fsp_err_t R_UARTA_Close(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_UARTA_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_UARTA_BaudCalculate(uint32_t baudrate, + uint32_t baud_rate_percent_error_x1000, + uarta_clock_source_t clock_source, + uarta_baud_setting_t * const p_baud_setting); +fsp_err_t R_UARTA_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_UARTA_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * p_remaining_bytes); +fsp_err_t R_UARTA_ReceiveSuspend(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_UARTA_ReceiveResume(uart_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end addtogroup UARTA) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ulpt.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ulpt.h new file mode 100644 index 0000000000..d04acc8943 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_ulpt.h @@ -0,0 +1,181 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_ULPT_H +#define R_ULPT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_ulpt_cfg.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup ULPT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Count source. */ +typedef enum e_ulpt_clock +{ + ULPT_CLOCK_LOCO = 0x00U, ///< LOCO count source, division by 1, 2, 4, 8, 16, 32, 64, 128. + ULPT_CLOCK_SUBCLOCK = 0x20U, ///< Subclock count source, division by 1, 2, 4, 8, 16, 32, 64, 128. + ULPT_CLOCK_ULPTEVI = 0x02U, ///< Counts external events on ULPTEVI. +} ulpt_clock_t; + +/** Counter mode for event enable. */ +typedef enum e_ulpt_enable_function +{ + // R_ULPT0_ULPTIOC_TIOGT0_Msk 0X00 0000 0=Always count, 1 count external events (Not to be mized with nonzero TEECTL) + // R_ULPT0_ULPTISR_RCCPSEL2_Msk 0000 0X00 0=count low level, 1 count high level, only valid when TIOGT0=1 (Not to be mized with nonzero TEECTL) + // R_ULPT0_ULPTMR3_TEECTL_Msk 00XX 0000 + // 0100 0000 Count external high, + // 0100 0100 Count external low + ULPT_ENABLE_FUNCTION_IGNORED = 0x00U, ///< Always count external events, ignore ULPTEE. + ULPT_ENABLE_FUNCTION_ENABLE_LOW = 0x40U, ///< Event counting is enabled while ULPTEE is low (event counting only). + ULPT_ENABLE_FUNCTION_ENABLE_HIGH = 0x44U, ///< Event counting is enabled while ULPTEE is high (event counting only). + ULPT_ENABLE_FUNCTION_START = 0x20U, ///< Counting is started after ULPTEE. + ULPT_ENABLE_FUNCTION_RESTART = 0x30U, ///< Counting is restarted after ULPTEE. +} ulpt_enable_function_t; + +/** Enable signal trigger edge for start and restart functions. */ +typedef enum e_ulpt_trigger_edge +{ + ULPT_TRIGGER_EDGE_RISING = 0x00U, ///< Timer enable function occurs on the rising edge of ULPTEE. + ULPT_TRIGGER_EDGE_FALLING = 0x40U, ///< Timer enable function occurs on the falling edge of ULPTEE. + ULPT_TRIGGER_EDGE_BOTH = 0x80U, ///< Timer enable function occurs on any edge of ULPTEE. +} ulpt_trigger_edge_t; + +/** Event signal pin. */ +typedef enum e_ulpt_event_pin +{ + ULPT_EVENT_PIN_RISING = 0x00U, ///< Event count occurs on the rising edge. + ULPT_EVENT_PIN_FALLING = 0x02U, ///< Event count occurs on the falling edge. + ULPT_EVENT_PIN_BOTH = 0x08U, ///< Event count occurs on both edges. +} ulpt_event_pin_t; + +/** Output pins, used to select which duty cycle to update in R_ULPT_DutyCycleSet(). */ +typedef enum e_ulpt_output_pin +{ + ULPT_OUTPUT_PIN_ULPTOA = 0U, ///< Compare match A output. + ULPT_OUTPUT_PIN_ULPTOB = 1U, ///< Compare match B output. +} ulpt_output_pin_t; + +/** ULPTO pulse output pin. */ +typedef enum e_ulpt_pulse_pin_cfg +{ + ULPT_PULSE_PIN_CFG_DISABLED = 0x00U, ///< Output pin disabled. + ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_LOW = 0x01U, ///< Output pin Enabled Start Low + ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_HIGH = 0x02U, ///< Output pin enabled Start Hig +} ulpt_pulse_pin_cfg_t; + +/** ULPT match output pin. */ +typedef enum e_ulpt_match_pin_cfg +{ + ULPT_MATCH_PIN_CFG_DISABLED = 0x00U, ///< Match output disabled. + ULPT_MATCH_PIN_CFG_START_LEVEL_LOW = 0x03U, ///< Match output enabled, starts low. + ULPT_MATCH_PIN_CFG_START_LEVEL_HIGH = 0x07U, ///< Match output enabled, starts high. +} ulpt_match_pin_cfg_t; + +/** Input filter, applied to ULPTEVI in event counter mode. The filter requires the signal to be at the same level for + * 3 successive reads at the specified filter frequency. */ +typedef enum e_ulpt_ulptevi_filter +{ + ULPT_ULPTEVI_FILTER_NONE = 0x00U, ///< No filter + ULPT_ULPTEVI_FILTER_PCLKB = 0x10U, ///< Filter at PCLKB + ULPT_ULPTEVI_FILTER_PCLKB_DIV_8 = 0x20U, ///< Filter at PCLKB / 8 + ULPT_ULPTEVI_FILTER_PCLKB_DIV_32 = 0x30U, ///< Filter at PCLKB / 32 +} ulpt_ulptevi_filter_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_ulpt_instance_ctrl +{ + uint32_t open; // Whether or not the channel is open. + const timer_cfg_t * p_cfg; // Pointer to initial configuration. + R_ULPT0_Type * p_reg; // Base register for this channel. + uint32_t period; // Current timer period (counts). + + void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs. + timer_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void * p_context; // Pointer to context to be passed into callback function +} ulpt_instance_ctrl_t; + +/** Optional ULPT extension data structure. */ +typedef struct st_ulpt_extended_cfg +{ + ulpt_clock_t count_source; ///< ULPT channel clock source. + + /* Input pin settings */ + ulpt_ulptevi_filter_t ulptevi_filter; ///< Input filter for ULTPEVI. + ulpt_enable_function_t enable_function; ///< Counter function when ULPTEE is valid. + ulpt_trigger_edge_t trigger_edge; ///< Enable trigger edge (start and restart functions only). + ulpt_event_pin_t event_pin; ///< Event pin (event counting only). + + /* Output settings */ + ulpt_pulse_pin_cfg_t ulpto; ///< Pulse output pin. + union + { + uint8_t ulptoab_settings; ///< Compare match output register. + struct + { + ulpt_match_pin_cfg_t ulptoa : 3; ///< Compare match A output pin. + uint8_t : 1; + ulpt_match_pin_cfg_t ulptob : 3; ///< Compare match B output pin. + uint8_t : 1; + } ulptoab_settings_b; + }; +} ulpt_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_ulpt; + +/** @endcond */ + +fsp_err_t R_ULPT_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_ULPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_ULPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_ULPT_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_ULPT_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_ULPT_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_ULPT_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_ULPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_ULPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_ULPT_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_ULPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_ULPT_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_ULPT_CompareMatchSet(timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel); + +/*******************************************************************************************************************//** + * @} (end defgroup ULPT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ + +FSP_FOOTER + +#endif // R_ULPT_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_usb_basic.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_usb_basic.h new file mode 100644 index 0000000000..f831ea3e05 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_usb_basic.h @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup USB USB + * @{ + **********************************************************************************************************************/ + +#ifndef R_USB_H +#define R_USB_H + +#include "bsp_api.h" +#include "r_usb_basic_cfg.h" +#include "r_usb_basic_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** USB private control block. DO NOT MODIFY. Initialization occurs when R_USB_Open is called. */ + +typedef usb_event_info_t usb_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +extern const usb_api_t g_usb_on_usb; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_USB_Open(usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const cfg); + +fsp_err_t R_USB_Close(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_Read(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t destination); + +fsp_err_t R_USB_Write(usb_ctrl_t * const p_api_ctrl, uint8_t const * const p_buf, uint32_t size, uint8_t destination); + +fsp_err_t R_USB_Stop(usb_ctrl_t * const p_api_ctrl, usb_transfer_t direction, uint8_t destination); + +fsp_err_t R_USB_Suspend(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_Resume(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_VbusSet(usb_ctrl_t * const p_api_ctrl, uint16_t state); + +fsp_err_t R_USB_InfoGet(usb_ctrl_t * const p_api_ctrl, usb_info_t * p_info, uint8_t destination); + +fsp_err_t R_USB_PipeRead(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + +fsp_err_t R_USB_PipeWrite(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + +fsp_err_t R_USB_PipeStop(usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number); + +fsp_err_t R_USB_UsedPipesGet(usb_ctrl_t * const p_api_ctrl, uint16_t * p_pipe, uint8_t destination); + +fsp_err_t R_USB_PipeInfoGet(usb_ctrl_t * const p_api_ctrl, usb_pipe_t * p_info, uint8_t pipe_number); + +fsp_err_t R_USB_PullUp(usb_ctrl_t * const p_api_ctrl, uint8_t state); + +fsp_err_t R_USB_EventGet(usb_ctrl_t * const p_api_ctrl, usb_status_t * event); + +fsp_err_t R_USB_Callback(usb_callback_t * p_callback); + +fsp_err_t R_USB_HostControlTransfer(usb_ctrl_t * const p_api_ctrl, + usb_setup_t * p_setup, + uint8_t * p_buf, + uint8_t device_address); + +fsp_err_t R_USB_PeriControlDataGet(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size); + +fsp_err_t R_USB_PeriControlDataSet(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size); + +fsp_err_t R_USB_PeriControlStatusSet(usb_ctrl_t * const p_api_ctrl, usb_setup_status_t status); + +fsp_err_t R_USB_RemoteWakeup(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_ModuleNumberGet(usb_ctrl_t * const p_api_ctrl, uint8_t * module_number); + +fsp_err_t R_USB_ClassTypeGet(usb_ctrl_t * const p_api_ctrl, usb_class_t * class_type); + +fsp_err_t R_USB_DeviceAddressGet(usb_ctrl_t * const p_api_ctrl, uint8_t * device_address); + +fsp_err_t R_USB_PipeNumberGet(usb_ctrl_t * const p_api_ctrl, uint8_t * pipe_number); + +fsp_err_t R_USB_DeviceStateGet(usb_ctrl_t * const p_api_ctrl, uint16_t * state); + +fsp_err_t R_USB_DataSizeGet(usb_ctrl_t * const p_api_ctrl, uint32_t * data_size); + +fsp_err_t R_USB_SetupGet(usb_ctrl_t * const p_api_ctrl, usb_setup_t * setup); + +fsp_err_t R_USB_OtgCallbackSet(usb_ctrl_t * const p_api_ctrl, usb_otg_callback_t * p_callback); + +fsp_err_t R_USB_OtgSRP(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_DriverActivate(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_CallbackMemorySet(usb_ctrl_t * const p_api_ctrl, usb_callback_args_t * p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_USB_H + +/*******************************************************************************************************************//** + * @} (end addtogroup USB) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_vin.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_vin.h new file mode 100644 index 0000000000..1648e4f007 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_vin.h @@ -0,0 +1,96 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_VIN_H +#define R_VIN_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_vin_cfg.h" +#include "r_vin_device_types.h" +#include "r_capture_api.h" +#include "r_mipi_csi.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup VIN + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** VIN instance control block. Implements */ +typedef enum e_vin_event +{ + VIN_EVENT_NONE, ///< No Event + VIN_EVENT_NOTIFY, ///< Notification Event + VIN_EVENT_ERROR ///< Error Event +} vin_event_t; + +/** VIN instance control block. */ +typedef struct st_vin_instance_ctrl +{ + uint32_t open; ///< Interface is open + capture_cfg_t const * p_cfg; // Pointer to the configuration structure + void (* p_callback)(capture_callback_args_t *); ///< Pointer to callback that is called when an adc_event_t occurs. + + void * p_context; ///< Pointer to context to be passed into callback function + capture_callback_args_t * p_callback_memory; ///< Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +} vin_instance_ctrl_t; + +/** Extended configuration structure for VIN. */ +typedef struct st_vin_extended_cfg +{ + mipi_csi_instance_t const * p_mipi_csi_instance; ///< Pointer to mipi physical layer instance + + vin_input_ctrl_t input_ctrl; + vin_output_ctrl_t output_ctrl; + vin_conversion_ctrl_t conversion_ctrl; + vin_conversion_data_t conversion_data; + vin_interrupt_cfg_t interrupt_cfg; +} vin_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const capture_api_t g_capture_on_vin; + +/** @endcond */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_VIN_Open(capture_ctrl_t * const p_api_ctrl, capture_cfg_t const * const p_cfg); +fsp_err_t R_VIN_Close(capture_ctrl_t * const p_api_ctrl); +fsp_err_t R_VIN_CaptureStart(capture_ctrl_t * const p_api_ctrl, uint8_t * const p_buffer); +fsp_err_t R_VIN_StatusGet(capture_ctrl_t * const p_api_ctrl, capture_status_t * p_status); + +/*******************************************************************************************************************//** + * @} (end defgroup VIN) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_VIN_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_wdt.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_wdt.h new file mode 100644 index 0000000000..1f3c2c1dd7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/inc/instances/r_wdt.h @@ -0,0 +1,79 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup WDT WDT + * @{ + **********************************************************************************************************************/ + +#ifndef R_WDT_H +#define R_WDT_H + +#include "bsp_api.h" + +#include "r_wdt_cfg.h" +#include "r_wdt_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** WDT private control block. DO NOT MODIFY. Initialization occurs when R_WDT_Open() is called. */ +typedef struct st_wdt_instance_ctrl +{ + uint32_t wdt_open; // Indicates whether the open() API has been successfully + // called. + void * p_context; // Placeholder for user data. Passed to the user callback in + // wdt_callback_args_t. + void (* p_callback)(wdt_callback_args_t * p_args); // Callback provided when a WDT NMI ISR occurs. + wdt_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +} wdt_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const wdt_api_t g_wdt_on_wdt; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_WDT_Refresh(wdt_ctrl_t * const p_ctrl); + +fsp_err_t R_WDT_Open(wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg); + +fsp_err_t R_WDT_StatusClear(wdt_ctrl_t * const p_ctrl, const wdt_status_t status); + +fsp_err_t R_WDT_StatusGet(wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status); + +fsp_err_t R_WDT_CounterGet(wdt_ctrl_t * const p_ctrl, uint32_t * const p_count); + +fsp_err_t R_WDT_TimeoutGet(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); + +fsp_err_t R_WDT_CallbackSet(wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void * const p_context, + wdt_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_WDT_H + +/*******************************************************************************************************************//** + * @} (end addtogroup WDT) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h new file mode 100644 index 0000000000..6eae16a4ac --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h @@ -0,0 +1,20281 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7FA4E10D.h + * @brief CMSIS HeaderFile + * @version 1.10.00 + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA4E10D + * @{ + */ + +#ifndef R7FA4E10D_H + #define R7FA4E10D_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA4E10D System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + }; + __IM uint32_t RESERVED3; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; + } MSSAR_b; + }; + + union + { + __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED13[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 12; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } FCNTSELR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR0_b; + }; + + union + { + __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[11]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ + + struct + { + __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address + * or the last blank checked address which is found in 'Blank + * Check' command execution. */ + uint32_t : 8; + } FBCADDR_b; + }; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ + + struct + { + __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ + uint8_t : 6; + } PRWCNTR_b; + }; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + + union + { + __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register + * 2 */ + + struct + { + __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ + uint8_t : 1; + __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ + uint8_t : 2; + } HOCOCR2_b; + }; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED15[3]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED17; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ + + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 5; + } I3CCKDIVCR_b; + }; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ + uint8_t : 3; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED22; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED28[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED29[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED30; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED36[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } CGFSAR_b; + }; + __IM uint32_t RESERVED37; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED39[6]; + __IM uint16_t RESERVED40; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED41; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED42; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED43; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED46[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED47; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED48; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED51; + __IM uint32_t RESERVED52[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED53; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED54; + __IM uint32_t RESERVED55[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED57; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED58; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED59; + __IM uint16_t RESERVED60; + __IM uint32_t RESERVED61[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint16_t RESERVED[276]; + + union + { + __IM uint16_t TSCDR; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register */ + + struct + { + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; + }; + }; + __IM uint16_t TSCDRR; /*!< (@ 0x0000022A) Temperature Sensor Calibration Data Register + * (Room Temperature) */ +} R_TSN_Type; /*!< Size = 556 (0x22c) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; +} R_TZF_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ + uint32_t : 17; + } ICUSARF_b; + }; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ + __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ + __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ + uint32_t : 25; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ + + struct + { + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ + uint32_t : 24; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED10[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED11[126]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn + * and ELCSRn */ + uint32_t : 31; + } TEVTRCR_b; + }; +} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash (R_FLAD) + */ + +typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */ +{ + __IM uint8_t RESERVED[64]; + + union + { + __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ + + struct + { + __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ + } FCKMHZ_b; + }; +} R_FLAD_Type; /*!< Size = 65 (0x41) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CRC_BASE 0x40108000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_MPU_MMPU_BASE 0x40000000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SPI2_BASE 0x40072200UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CPSCU_BASE 0x40008000UL + #define R_AGTX0_BASE 0x400E8000UL + #define R_AGTX1_BASE 0x400E8100UL + #define R_AGTX2_BASE 0x400E8200UL + #define R_AGTX3_BASE 0x400E8300UL + #define R_AGTX4_BASE 0x400E8400UL + #define R_AGTX5_BASE 0x400E8500UL + #define R_AGTX6_BASE 0x400E8600UL + #define R_AGTX7_BASE 0x400E8700UL + #define R_AGTX8_BASE 0x400E8800UL + #define R_AGTX9_BASE 0x400E8900UL + #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB17_Pos (17UL) /*!< PSARB17 (Bit 17) */ + #define R_PSCU_PSARB_PSARB17_Msk (0x20000UL) /*!< PSARB17 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FBCADDR ======================================================== */ + #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ + #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ +/* ======================================================= FCNTSELR ======================================================== */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ====================================================== FCNTDATAR0 ======================================================= */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FCNTDATAR1 ======================================================= */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================== PRWCNTR ======================================================== */ + #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ + #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR2 ======================================================== */ + #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ + #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ + #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCKMHZ ========================================================= */ + #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ + #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA4E10D_H */ + +/** @} */ /* End of group R7FA4E10D */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h new file mode 100644 index 0000000000..8e56cc23bd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h @@ -0,0 +1,21923 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7FA4M3AF.h + * @brief CMSIS HeaderFile + * @version 1.30.00 + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA4M3AF + * @{ + */ + +#ifndef R7FA4M3AF_H + #define R7FA4M3AF_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA4M3AF System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + }; + __IM uint32_t RESERVED3; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; + } MSSAR_b; + }; + + union + { + __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED13[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 12; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } FCNTSELR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR0_b; + }; + + union + { + __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[11]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ + + struct + { + __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address + * or the last blank checked address which is found in 'Blank + * Check' command execution. */ + uint32_t : 8; + } FBCADDR_b; + }; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ + + struct + { + __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ + uint8_t : 6; + } PRWCNTR_b; + }; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + + union + { + __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register + * 2 */ + + struct + { + __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ + uint8_t : 1; + __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ + uint8_t : 2; + } HOCOCR2_b; + }; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED15[3]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED17; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ + + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 5; + } I3CCKDIVCR_b; + }; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ + uint8_t : 3; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED22; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED28[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED29[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED30; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED36[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } CGFSAR_b; + }; + __IM uint32_t RESERVED37; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED39[6]; + __IM uint16_t RESERVED40; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED41; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED42; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED43; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED46[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED47; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED48; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED51; + __IM uint32_t RESERVED52[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED53; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED54; + __IM uint32_t RESERVED55[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED57; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED58; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED59; + __IM uint16_t RESERVED60; + __IM uint32_t RESERVED61[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; +} R_TZF_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 31; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + uint32_t : 31; + } CCAFCT_b; + }; + + union + { + __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ + uint32_t : 30; + } CCALCF_b; + }; + __IM uint32_t RESERVED[13]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 31; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + uint32_t : 31; + } SCAFCT_b; + }; + + union + { + __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ + uint32_t : 30; + } SCALCF_b; + }; + __IM uint32_t RESERVED1[109]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 31; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ + uint32_t : 17; + } ICUSARF_b; + }; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ + __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ + __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ + uint32_t : 25; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ + + struct + { + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ + uint32_t : 24; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED10[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED11[126]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn + * and ELCSRn */ + uint32_t : 31; + } TEVTRCR_b; + }; +} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash (R_FLAD) + */ + +typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */ +{ + __IM uint8_t RESERVED[64]; + + union + { + __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ + + struct + { + __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ + } FCKMHZ_b; + }; +} R_FLAD_Type; /*!< Size = 65 (0x41) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CRC_BASE 0x40108000UL + #define R_CTSU_BASE 0x400D0000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_OPS_BASE 0x40169A00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_MPU_MMPU_BASE 0x40000000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SDHI0_BASE 0x40092000UL + #define R_SDHI1_BASE 0x40092400UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SPI2_BASE 0x40072200UL + #define R_SRAM_BASE 0x40002000UL + #define R_SSI0_BASE 0x4009D000UL + #define R_SSI1_BASE 0x4009D100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x400F3000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CACHE_BASE 0x40007000UL + #define R_CPSCU_BASE 0x40008000UL + #define R_AGTX0_BASE 0x400E8000UL + #define R_AGTX1_BASE 0x400E8100UL + #define R_AGTX2_BASE 0x400E8200UL + #define R_AGTX3_BASE 0x400E8300UL + #define R_AGTX4_BASE 0x400E8400UL + #define R_AGTX5_BASE 0x400E8500UL + #define R_AGTX6_BASE 0x400E8600UL + #define R_AGTX7_BASE 0x400E8700UL + #define R_AGTX8_BASE 0x400E8800UL + #define R_AGTX9_BASE 0x400E8900UL + #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB17_Pos (17UL) /*!< PSARB17 (Bit 17) */ + #define R_PSCU_PSARB_PSARB17_Msk (0x20000UL) /*!< PSARB17 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FBCADDR ======================================================== */ + #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ + #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ +/* ======================================================= FCNTSELR ======================================================== */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ====================================================== FCNTDATAR0 ======================================================= */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FCNTDATAR1 ======================================================= */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================== PRWCNTR ======================================================== */ + #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ + #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR2 ======================================================== */ + #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ + #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ + #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCALCF ========================================================= */ + #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCALCF ========================================================= */ + #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCKMHZ ========================================================= */ + #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ + #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA4M3AF_H */ + +/** @} */ /* End of group R7FA4M3AF */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h new file mode 100644 index 0000000000..f77d175910 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E2BB.h @@ -0,0 +1,24961 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7FA6E2BB.h + * @brief CMSIS HeaderFile + * @version 1.00.00 + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA6E2BB + * @{ + */ + +#ifndef R7FA6E2BB_H + #define R7FA6E2BB_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA6E2BB System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + }; + __IM uint32_t RESERVED3; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution */ + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution */ + uint32_t : 3; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution */ + uint32_t : 2; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution */ + uint32_t : 27; + } MSSAR_b; + }; + + union + { + __IOM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IOM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IOM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IOM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IOM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IOM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IOM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IOM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IOM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED13[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 12; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } FCNTSELR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR0_b; + }; + + union + { + __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[11]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ + + struct + { + __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address + * or the last blank checked address which is found in 'Blank + * Check' command execution. */ + uint32_t : 8; + } FBCADDR_b; + }; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED13[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED14[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; + } SVST_b; + }; + + union + { + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ + + struct + { + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED27[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED28[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED30; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED32[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED33[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ + + struct + { + __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ + uint8_t : 6; + } PRWCNTR_b; + }; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + + union + { + __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register + * 2 */ + + struct + { + __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ + uint8_t : 1; + __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ + uint8_t : 2; + } HOCOCR2_b; + }; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED15[3]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED17; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ + + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 5; + } I3CCKDIVCR_b; + }; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ + uint8_t : 3; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED22; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED28[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED29[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED30; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED36[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } CGFSAR_b; + }; + __IM uint32_t RESERVED37; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED39[6]; + __IM uint16_t RESERVED40; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED41; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED42; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED43; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED46[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED47; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED48; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED51; + __IM uint32_t RESERVED52[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED53; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED54; + __IM uint32_t RESERVED55[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED57; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED58; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED59; + __IM uint16_t RESERVED60; + __IM uint32_t RESERVED61[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TRNG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief True Random Number Generator (R_TRNG) + */ + +typedef struct /*!< (@ 0x40162000) R_TRNG Structure */ +{ + union + { + __IM uint8_t TRNGSDR; /*!< (@ 0x00000000) TRNG SEED Data Register */ + + struct + { + __IM uint8_t SDATA : 8; /*!< [7..0] When RDRDY bit is 1, these bits hold the generated SEED. + * When RDRDY bit is 0, these bits are read as 00h.The SEED + * is generated as 32-bit data. When TRNGSDR is read 4 times + * while RDRDY = 1, SEED reading is completed and RDRDY bit + * changes to 0 */ + } TRNGSDR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TRNGSCR0; /*!< (@ 0x00000002) TRNG SEED Command Register 0 */ + + struct + { + uint8_t : 2; + __OM uint8_t SGSTART : 1; /*!< [2..2] SEED Generation Start */ + __IOM uint8_t SGCEN : 1; /*!< [3..3] SEED Generation Circuit Enable */ + uint8_t : 3; + __IM uint8_t RDRDY : 1; /*!< [7..7] When SEED geenration is completed, this bit changes to + * 0 */ + } TRNGSCR0_b; + }; + + union + { + __IOM uint8_t TRNGSCR1; /*!< (@ 0x00000003) TRNG SEED Command Register 1 */ + + struct + { + __IOM uint8_t INTEN : 1; /*!< [0..0] TRNG Interrupt Enable */ + uint8_t : 7; + } TRNGSCR1_b; + }; +} R_TRNG_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; +} R_TZF_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 31; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + uint32_t : 31; + } CCAFCT_b; + }; + + union + { + __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ + uint32_t : 30; + } CCALCF_b; + }; + __IM uint32_t RESERVED[13]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 31; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + uint32_t : 31; + } SCAFCT_b; + }; + + union + { + __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ + uint32_t : 30; + } SCALCF_b; + }; + __IM uint32_t RESERVED1[109]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 31; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ + uint32_t : 17; + } ICUSARF_b; + }; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ + __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ + __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ + uint32_t : 25; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ + + struct + { + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ + uint32_t : 24; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED10[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED11[126]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn + * and ELCSRn */ + uint32_t : 31; + } TEVTRCR_b; + }; +} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ + +/* =========================================================================================================================== */ +/* ================ R_CEC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Consumer Electronics Control (R_CEC) + */ + +typedef struct /*!< (@ 0x400AC000) R_CEC Structure */ +{ + union + { + __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */ + + struct + { + __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */ + __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device + * 1) */ + __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device + * 2) */ + __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */ + __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */ + __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */ + __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */ + __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */ + __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */ + __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device + * 3) */ + __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */ + __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device + * 3) */ + __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */ + __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */ + __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */ + uint16_t : 1; + } CADR_b; + }; + + union + { + __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */ + + struct + { + __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */ + __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing + * Select */ + __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */ + __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */ + __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */ + __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */ + } CECCTL1_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */ + + struct + { + __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */ + uint16_t : 7; + } STATB_b; + }; + + union + { + __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting + * Register */ + + struct + { + __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */ + uint16_t : 7; + } STATL_b; + }; + + union + { + __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */ + uint16_t : 7; + } LGC0L_b; + }; + + union + { + __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */ + uint16_t : 7; + } LGC1L_b; + }; + + union + { + __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */ + + struct + { + __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */ + uint16_t : 7; + } DATB_b; + }; + + union + { + __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */ + + struct + { + __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */ + uint16_t : 7; + } NOMT_b; + }; + + union + { + __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */ + uint16_t : 7; + } STATLL_b; + }; + + union + { + __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ + uint16_t : 7; + } STATLH_b; + }; + + union + { + __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting + * Register */ + + struct + { + __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */ + uint16_t : 7; + } STATBL_b; + }; + + union + { + __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting + * Register */ + + struct + { + __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ + uint16_t : 7; + } STATBH_b; + }; + + union + { + __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ + uint16_t : 7; + } LGC0LL_b; + }; + + union + { + __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ + uint16_t : 7; + } LGC0LH_b; + }; + + union + { + __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */ + uint16_t : 7; + } LGC1LL_b; + }; + + union + { + __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */ + uint16_t : 7; + } LGC1LH_b; + }; + + union + { + __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting + * Register */ + + struct + { + __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */ + uint16_t : 7; + } DATBL_b; + }; + + union + { + __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting + * Register */ + + struct + { + __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */ + uint16_t : 7; + } DATBH_b; + }; + + union + { + __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */ + + struct + { + __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */ + uint16_t : 7; + } NOMP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */ + __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */ + uint8_t : 1; + __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */ + } CECEXMD_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */ + + struct + { + __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */ + __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */ + uint8_t : 6; + } CECEXMON_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[10]; + __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */ + __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */ + + union + { + __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */ + + struct + { + __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */ + __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */ + __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */ + __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */ + __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */ + __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */ + __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */ + uint8_t : 1; + } CECES_b; + }; + + union + { + __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */ + + struct + { + __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */ + __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */ + __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */ + __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */ + __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */ + uint8_t : 2; + __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */ + } CECS_b; + }; + + union + { + __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */ + + struct + { + __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */ + __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */ + __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */ + __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */ + __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */ + __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */ + __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */ + uint8_t : 1; + } CECFC_b; + }; + + union + { + __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */ + + struct + { + __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */ + __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */ + __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */ + __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */ + __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */ + __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */ + } CECCTL0_b; + }; +} R_CEC_Type; /*!< Size = 70 (0x46) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash (R_FLAD) + */ + +typedef struct /*!< (@ 0x407FC000) R_FLAD Structure */ +{ + __IM uint8_t RESERVED[64]; + + union + { + __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ + + struct + { + __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ + } FCKMHZ_b; + }; +} R_FLAD_Type; /*!< Size = 65 (0x41) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CANFD_BASE 0x400B0000UL + #define R_CANFD1_BASE 0x400B2000UL + #define R_CRC_BASE 0x40108000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_OPS_BASE 0x40169A00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_I3C0_BASE 0x4011F000UL + #define R_I3C1_BASE 0x4011F400UL + #define R_MPU_MMPU_BASE 0x40000000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SPI2_BASE 0x40072200UL + #define R_SRAM_BASE 0x40002000UL + #define R_SSI0_BASE 0x4009D000UL + #define R_SSI1_BASE 0x4009D100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TRNG_BASE 0x40162000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x400F3000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CACHE_BASE 0x40007000UL + #define R_CPSCU_BASE 0x40008000UL + #define R_CEC_BASE 0x400AC000UL + #define R_AGTX0_BASE 0x400E8000UL + #define R_AGTX1_BASE 0x400E8100UL + #define R_AGTX2_BASE 0x400E8200UL + #define R_AGTX3_BASE 0x400E8300UL + #define R_AGTX4_BASE 0x400E8400UL + #define R_AGTX5_BASE 0x400E8500UL + #define R_AGTX6_BASE 0x400E8600UL + #define R_AGTX7_BASE 0x400E8700UL + #define R_AGTX8_BASE 0x400E8800UL + #define R_AGTX9_BASE 0x400E8900UL + #define R_ECCMB0_BASE 0x4036F200UL + #define R_ECCMB1_BASE 0x4036F300UL + #define R_FLAD_BASE 0x407FC000UL + #define R_WDT1_BASE 0x40044300UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TRNG ((R_TRNG_Type *) R_TRNG_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_CEC ((R_CEC_Type *) R_CEC_BASE) + #define R_AGTW0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGTW1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGTW2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGTW3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGTW4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGTW5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGTW6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGTW7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGTW8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGTW9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) + #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB0_Pos (0UL) /*!< PSARB0 (Bit 0) */ + #define R_PSCU_PSARB_PSARB0_Msk (0x1UL) /*!< PSARB0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */ + #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB5_Pos (5UL) /*!< PSARB5 (Bit 5) */ + #define R_PSCU_PSARB_PSARB5_Msk (0x20UL) /*!< PSARB5 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB17_Pos (17UL) /*!< PSARB17 (Bit 17) */ + #define R_PSCU_PSARB_PSARB17_Msk (0x20000UL) /*!< PSARB17 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC4_Pos (4UL) /*!< PSARC4 (Bit 4) */ + #define R_PSCU_PSARC_PSARC4_Msk (0x10UL) /*!< PSARC4 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD29_Pos (29UL) /*!< PSARD29 (Bit 29) */ + #define R_PSCU_PSARD_PSARD29_Msk (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR4_Pos (4UL) /*!< MSSAR4 (Bit 4) */ + #define R_PSCU_MSSAR_MSSAR4_Msk (0x10UL) /*!< MSSAR4 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FBCADDR ======================================================== */ + #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ + #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ +/* ======================================================= FCNTSELR ======================================================== */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ====================================================== FCNTDATAR0 ======================================================= */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FCNTDATAR1 ======================================================= */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================== PRWCNTR ======================================================== */ + #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ + #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR2 ======================================================== */ + #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ + #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ + #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TRNG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TRNGSDR ======================================================== */ + #define R_TRNG_TRNGSDR_SDATA_Pos (0UL) /*!< SDATA (Bit 0) */ + #define R_TRNG_TRNGSDR_SDATA_Msk (0xffUL) /*!< SDATA (Bitfield-Mask: 0xff) */ +/* ======================================================= TRNGSCR0 ======================================================== */ + #define R_TRNG_TRNGSCR0_RDRDY_Pos (7UL) /*!< RDRDY (Bit 7) */ + #define R_TRNG_TRNGSCR0_RDRDY_Msk (0x80UL) /*!< RDRDY (Bitfield-Mask: 0x01) */ + #define R_TRNG_TRNGSCR0_SGCEN_Pos (3UL) /*!< SGCEN (Bit 3) */ + #define R_TRNG_TRNGSCR0_SGCEN_Msk (0x8UL) /*!< SGCEN (Bitfield-Mask: 0x01) */ + #define R_TRNG_TRNGSCR0_SGSTART_Pos (2UL) /*!< SGSTART (Bit 2) */ + #define R_TRNG_TRNGSCR0_SGSTART_Msk (0x4UL) /*!< SGSTART (Bitfield-Mask: 0x01) */ +/* ======================================================= TRNGSCR1 ======================================================== */ + #define R_TRNG_TRNGSCR1_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_TRNG_TRNGSCR1_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCALCF ========================================================= */ + #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCALCF ========================================================= */ + #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CADR ========================================================== */ + #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */ + #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */ + #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */ + #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */ + #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */ + #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */ + #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */ + #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */ + #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */ + #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */ + #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */ + #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */ + #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */ + #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */ + #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */ + #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCTL1 ======================================================== */ + #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */ + #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */ + #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */ + #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */ + #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */ + #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */ + #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */ + #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */ + #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */ +/* ========================================================= STATB ========================================================= */ + #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */ + #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */ +/* ========================================================= STATL ========================================================= */ + #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */ + #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */ +/* ========================================================= LGC0L ========================================================= */ + #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */ + #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */ +/* ========================================================= LGC1L ========================================================= */ + #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */ + #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DATB ========================================================== */ + #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */ + #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */ +/* ========================================================= NOMT ========================================================== */ + #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */ + #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */ +/* ======================================================== STATLL ========================================================= */ + #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */ + #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== STATLH ========================================================= */ + #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */ + #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */ +/* ======================================================== STATBL ========================================================= */ + #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */ + #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== STATBH ========================================================= */ + #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */ + #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LGC0LL ========================================================= */ + #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */ + #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LGC0LH ========================================================= */ + #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */ + #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LGC1LL ========================================================= */ + #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */ + #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LGC1LH ========================================================= */ + #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */ + #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DATBL ========================================================= */ + #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */ + #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DATBH ========================================================= */ + #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */ + #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */ +/* ========================================================= NOMP ========================================================== */ + #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */ + #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CECEXMD ======================================================== */ + #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */ + #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */ + #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */ + #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */ + #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */ + #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= CECEXMON ======================================================== */ + #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */ + #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */ + #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */ + #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */ +/* ========================================================= CTXD ========================================================== */ +/* ========================================================= CRXD ========================================================== */ +/* ========================================================= CECES ========================================================= */ + #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */ + #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */ + #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */ + #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */ + #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */ + #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */ + #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */ + #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */ +/* ========================================================= CECS ========================================================== */ + #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */ + #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */ + #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */ + #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */ + #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */ + #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */ + #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */ +/* ========================================================= CECFC ========================================================= */ + #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */ + #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */ + #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */ + #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */ + #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */ + #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */ + #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */ + #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCTL0 ======================================================== */ + #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */ + #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */ + #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */ + #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */ + #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */ + #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */ + #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */ + #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCKMHZ ========================================================= */ + #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ + #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6E2BB_H */ + +/** @} */ /* End of group R7FA6E2BB */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h new file mode 100644 index 0000000000..626fd5e5f6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h @@ -0,0 +1,29603 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7FA6M3AH.h + * @brief CMSIS HeaderFile + * @version 1.2 + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA6M3AH + * @{ + */ + +#ifndef R7FA6M3AH_H + #define R7FA6M3AH_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ + #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + #include "system.h" /*!< R7FA6M3AH System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + }; + __IM uint32_t RESERVED3; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t STTRU; /*!< (@ 0x00000000) Timer Start Time Setting Register */ + + struct + { + __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the start time of the pulse output timer in nanoseconds. */ + } STTRU_b; + }; + + union + { + __IOM uint32_t STTRL; /*!< (@ 0x00000004) Timer Start Time Setting Register */ + + struct + { + __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the start time of the pulse output timer in nanoseconds. */ + } STTRL_b; + }; + + union + { + __IOM uint32_t CYCR; /*!< (@ 0x00000008) Timer Cycle Setting Registers */ + + struct + { + __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in + * nanoseconds. Set a value that is equivalent to at least + * four cycles of the STCA clock. */ + uint32_t : 2; + } CYCR_b; + }; + + union + { + __IOM uint32_t PLSR; /*!< (@ 0x0000000C) Timer Pulse Width Setting Register */ + + struct + { + __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse + * signal from the timer in nanoseconds. Set a value that + * is equivalent to at least two cycles of the STCA clock. */ + uint32_t : 3; + } PLSR_b; + }; +} R_ETHERC_EPTPC_COMMON_TM_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t MACRU; /*!< (@ 0x00000000) Channel Local MAC Address Register */ + + struct + { + __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address for Ethernet port 0. */ + uint32_t : 8; + } MACRU_b; + }; + + union + { + __IOM uint32_t MACRL; /*!< (@ 0x00000004) Channel Local MAC Address Register */ + + struct + { + __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address for Ethernet port 0. */ + uint32_t : 8; + } MACRL_b; + }; +} R_ETHERC_EPTPC_COMMON_PR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; + }; + + union + { + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ + + struct + { + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; + }; + + union + { + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position + * Register */ + + struct + { + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; + }; + + union + { + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; + }; + + union + { + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + } HSIZE_b; + }; + + union + { + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; + }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ + +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + + struct + { + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; + }; + + union + { + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + + struct + { + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; + }; + + union + { + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + + struct + { + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; + }; + + union + { + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + + struct + { + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; + }; + + union + { + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + + struct + { + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; + }; + + union + { + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + + struct + { + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; + }; + + union + { + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + + struct + { + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; + }; + + union + { + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + + struct + { + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; + }; + + union + { + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + + struct + { + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; + }; + + union + { + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + + struct + { + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; + }; + + union + { + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + + struct + { + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; + }; + + union + { + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + + struct + { + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; + }; + + union + { + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + + struct + { + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; + }; + + union + { + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + + struct + { + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; + }; + + union + { + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + + struct + { + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + + struct + { + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; + }; + + union + { + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + + struct + { + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + + struct + { + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; + }; + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + */ +typedef struct +{ + union + { + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; + }; + + union + { + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + + struct + { + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; + }; + + union + { + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; + }; + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control + * Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; + }; + + union + { + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + + struct + { + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; + }; + + union + { + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ + + struct + { + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; + }; + + union + { + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ + + struct + { + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; + }; + + union + { + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + + struct + { + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; + }; + + union + { + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ + + struct + { + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; + }; +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + + struct + { + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; + + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; + }; + + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; + + union + { + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; + }; + + union + { + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; + }; + + union + { + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; + }; + + union + { + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; + }; + + union + { + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; + + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; + }; + + union + { + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + + struct + { + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; + }; +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ + +/** + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ + + struct + { + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; + }; + + union + { + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ + + struct + { + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; + }; + + union + { + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + + struct + { + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; + }; + + union + { + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + + struct + { + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; + }; + + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ + + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + uint16_t : 13; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_MMPU_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000000) Bus Master MPU Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t OAD : 1; /*!< [1..1] Operation after detection */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } CTL_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[63]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000102) Protection of Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of region register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + __IM uint32_t RESERVED3[63]; + __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers */ +} R_MPU_MMPU_MMPU_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU) + */ +typedef struct +{ + union + { + __IOM uint16_t R; /*!< (@ 0x00000000) Access Control Register for MBIU */ + + struct + { + uint16_t : 2; + __IOM uint16_t RPGRPA : 1; /*!< [2..2] Master Group A Read protection */ + __IOM uint16_t WPGRPA : 1; /*!< [3..3] Master Group A Write protection */ + __IOM uint16_t RPGRPB : 1; /*!< [4..4] Master Group B Read protection */ + __IOM uint16_t WPGRPB : 1; /*!< [5..5] Master Group B Write protection */ + __IOM uint16_t RPGRPC : 1; /*!< [6..6] Master Group C Read protection */ + __IOM uint16_t WPGRPC : 1; /*!< [7..7] Master Group C Write protection */ + uint16_t : 4; + __IOM uint16_t RPFLI : 1; /*!< [12..12] Code Flash Memory Read Protection */ + __IOM uint16_t WPFLI : 1; /*!< [13..13] Code Flash Memory Write Protection (Note: This bit + * is read as 1. The write value should be 1.) */ + __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection */ + __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection */ + } R_b; + }; + __IM uint16_t RESERVED; +} R_MPU_SMPU_SMPU_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED13[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 12; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x400E4000) R_DRW Structure */ +{ + union + { + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ + + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; + }; + + union + { + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union + { + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; + }; + __IM uint32_t RESERVED[2]; + + union + { + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; + }; + + union + { + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; + }; + + union + { + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; + }; + + union + { + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; + }; + + union + { + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; + }; + + union + { + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; + }; + + union + { + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; + }; + + union + { + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; + }; + + union + { + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; + }; + + union + { + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; + }; + + union + { + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; + }; + + union + { + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; + }; + + union + { + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; + }; + + union + { + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; + }; + + union + { + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; + }; + + union + { + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; + }; + + union + { + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; + }; + + union + { + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; + }; + + union + { + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; + }; + + union + { + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; + }; + __IM uint32_t RESERVED1; + + union + { + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + + struct + { + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; + }; + + union + { + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + + struct + { + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + + struct + { + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; + }; + + union + { + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + + struct + { + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; + }; + + union + { + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + + struct + { + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; + + union + { + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + + struct + { + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + + struct + { + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; + }; + + union + { + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + + struct + { + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; + }; + + union + { + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + + struct + { + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; + }; + + union + { + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + + struct + { + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; + }; + + union + { + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + + struct + { + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; + }; + + union + { + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; + }; + + union + { + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; + }; + + union + { + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + + struct + { + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + + struct + { + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; + }; + + union + { + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + + struct + { + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; + }; + + union + { + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + + struct + { + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; + }; + + union + { + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + + struct + { + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; + }; + + union + { + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + + struct + { + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; + }; + + union + { + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + + struct + { + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; + }; + + union + { + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; + }; + + union + { + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; + }; + + union + { + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + + struct + { + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + + struct + { + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; + }; + + union + { + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + + struct + { + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; + }; + + union + { + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + + struct + { + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; + }; + + union + { + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + + struct + { + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t DBWER; /*!< (@ 0x00000100) DRW Bufferable Write Enable Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t BWE : 1; /*!< [2..2] Bufferable Write Enable */ + uint32_t : 29; + } DBWER_b; + }; +} R_DRW_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller (R_ETHERC_EPTPC) + */ + +typedef struct /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure */ +{ + union + { + __IOM uint32_t SYSR; /*!< (@ 0x00000000) SYNFP Status Register */ + + struct + { + __IOM uint32_t OFMUD : 1; /*!< [0..0] offsetFromMaster Value Update Flag */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] meanPathDelay Value Update Flag */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] Loop Reception Detection Flag */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] Response Stop Completion Detection Flag */ + __IOM uint32_t GENDN : 1; /*!< [17..17] Generation Stop Completion Detection Flag */ + uint32_t : 14; + } SYSR_b; + }; + + union + { + __IOM uint32_t SYIPR; /*!< (@ 0x00000004) SYNFP Status Notification Permission Register */ + + struct + { + __IOM uint32_t OFMUD : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission */ + __IOM uint32_t GENDN : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission */ + uint32_t : 14; + } SYIPR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SYMACRU; /*!< (@ 0x00000010) SYNFP MAC Address Registers */ + + struct + { + __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address. */ + uint32_t : 8; + } SYMACRU_b; + }; + + union + { + __IOM uint32_t SYMACRL; /*!< (@ 0x00000014) SYNFP MAC Address Registers */ + + struct + { + __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the local MAC address. */ + uint32_t : 8; + } SYMACRL_b; + }; + + union + { + __IOM uint32_t SYLLCCTLR; /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register */ + + struct + { + __IOM uint32_t CTL : 8; /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the + * control field in the LLC sublayer when generating IEEE802.3 + * frames. */ + uint32_t : 24; + } SYLLCCTLR_b; + }; + + union + { + __IOM uint32_t SYIPADDRR; /*!< (@ 0x0000001C) SYNFP Local IP Address Register */ + + struct + { + __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address. */ + } SYIPADDRR_b; + }; + __IM uint32_t RESERVED1[8]; + + union + { + __IOM uint32_t SYSPVRR; /*!< (@ 0x00000040) SYNFP Specification Version Setting Register */ + + struct + { + __IOM uint32_t VER : 4; /*!< [3..0] versionPTP Field ValueThese bits are used to set the + * versionPTP field value of the PTP v2 header.When a message + * is received, this value is compared with the versionPTP + * field of the received frame.In generating messages, the + * value is used for the versionPTP field of the frame for + * transmission.Set these bits to 0010b (PTP v2). */ + __IOM uint32_t TRSP : 4; /*!< [7..4] transportSpecific Field ValueThese bits are used to set + * the transportSpecific field value of the PTP v2 header.When + * a message is received, this value is compared with the + * transportSpecific field of the received frame.In generating + * messages, the value is used for the transportSpecific field + * of the frame for transmission.Set these bits to 0000b (IEEE + * 1588). */ + uint32_t : 24; + } SYSPVRR_b; + }; + + union + { + __IOM uint32_t SYDOMR; /*!< (@ 0x00000044) SYNFP Domain Number Setting Register */ + + struct + { + __IOM uint32_t DNUM : 8; /*!< [7..0] domainNumber Field Value SettingThese bits are used to + * set the domainNumber field value of the PTP v2 header.When + * a message is received, this value is compared with the + * domainNumber field of the received frame as a condition + * for PTP reception processing.In generating messages, the + * value is used for the domainNumber field of the frame for + * transmission. */ + uint32_t : 24; + } SYDOMR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ANFR; /*!< (@ 0x00000050) Announce Message Flag Field Setting Register */ + + struct + { + __IOM uint32_t FLAG0 : 1; /*!< [0..0] leap61This bit is used to set the logical value of the + * leap61 member of timePropertiesDS. */ + __IOM uint32_t FLAG1 : 1; /*!< [1..1] leap59This bit is used to set the logical value of the + * leap59 member of timePropertiesDS. */ + __IOM uint32_t FLAG2 : 1; /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical + * value of the currentUtcOffsetValid member of timePropertiesDS. */ + __IOM uint32_t FLAG3 : 1; /*!< [3..3] ptpTimescaleThis bit is used to set the logical value + * of the ptpTimescale member of timePropertiesDS. */ + __IOM uint32_t FLAG4 : 1; /*!< [4..4] timeTraceableThis bit is used to set the logical value + * of the timeTraceable member of timePropertiesDS. */ + __IOM uint32_t FLAG5 : 1; /*!< [5..5] frequencyTraceableThis bit is used to set the logical + * value of the frequencyTraceable member of timePropertiesDS. */ + uint32_t : 2; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + uint32_t : 1; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } ANFR_b; + }; + + union + { + __IOM uint32_t SYNFR; /*!< (@ 0x00000054) Sync Message Flag Field Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] twoStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } SYNFR_b; + }; + + union + { + __IOM uint32_t DYRQFR; /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRQFR_b; + }; + + union + { + __IOM uint32_t DYRPFR; /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] woStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRPFR_b; + }; + + union + { + __IOM uint32_t SYCIDRU; /*!< (@ 0x00000060) SYNFP Local Clock ID Registers */ + + struct + { + __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of your port. */ + } SYCIDRU_b; + }; + + union + { + __IOM uint32_t SYCIDRL; /*!< (@ 0x00000064) SYNFP Local Clock ID Registers */ + + struct + { + __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of your port. */ + } SYCIDRL_b; + }; + + union + { + __IOM uint32_t SYPNUMR; /*!< (@ 0x00000068) SYNFP Local Port Number Register */ + + struct + { + __IOM uint32_t PNUM : 16; /*!< [15..0] Local Port Number SettingThese bits hold the setting + * for the port number of the local port. */ + uint32_t : 16; + } SYPNUMR_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __OM uint32_t SYRVLDR; /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register */ + + struct + { + __OM uint32_t BMUP : 1; /*!< [0..0] BMC Update */ + __OM uint32_t STUP : 1; /*!< [1..1] State Update */ + __OM uint32_t ANUP : 1; /*!< [2..2] Announce Message Generation Information Update */ + uint32_t : 29; + } SYRVLDR_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SYRFL1R; /*!< (@ 0x00000090) SYNFP Reception Filter Register 1 */ + + struct + { + __IOM uint32_t ANCE0 : 1; /*!< [0..0] Announce Message Processing */ + __IOM uint32_t ANCE1 : 1; /*!< [1..1] Announce Message Processing */ + uint32_t : 2; + __IOM uint32_t SYNC0 : 1; /*!< [4..4] Sync Message Processing */ + __IOM uint32_t SYNC1 : 1; /*!< [5..5] Sync Message Processing */ + __IOM uint32_t SYNC2 : 1; /*!< [6..6] Sync Message Processing */ + uint32_t : 1; + __IOM uint32_t FUP0 : 1; /*!< [8..8] Follow_Up Message Processing */ + __IOM uint32_t FUP1 : 1; /*!< [9..9] Follow_Up Message Processing */ + __IOM uint32_t FUP2 : 1; /*!< [10..10] Follow_Up Message Processing */ + uint32_t : 1; + __IOM uint32_t DRQ0 : 1; /*!< [12..12] Delay_Req Message Processing */ + __IOM uint32_t DRQ1 : 1; /*!< [13..13] Delay_Req Message Processing */ + __IOM uint32_t DRQ2 : 1; /*!< [14..14] Delay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t DRP0 : 1; /*!< [16..16] Delay_Resp Message Processing */ + __IOM uint32_t DRP1 : 1; /*!< [17..17] Delay_Resp Message Processing */ + __IOM uint32_t DRP2 : 1; /*!< [18..18] Delay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRQ0 : 1; /*!< [20..20] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ1 : 1; /*!< [21..21] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ2 : 1; /*!< [22..22] Pdelay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRP0 : 1; /*!< [24..24] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP1 : 1; /*!< [25..25] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP2 : 1; /*!< [26..26] Pdelay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing */ + uint32_t : 1; + } SYRFL1R_b; + }; + + union + { + __IOM uint32_t SYRFL2R; /*!< (@ 0x00000094) SYNFP Reception Filter Register 2 */ + + struct + { + __IOM uint32_t MAN0 : 1; /*!< [0..0] Management Message Processing Setting */ + __IOM uint32_t MAN1 : 1; /*!< [1..1] Management Message Processing Setting */ + uint32_t : 2; + __IOM uint32_t SIG0 : 1; /*!< [4..4] Signaling Message Processing Setting */ + __IOM uint32_t SIG1 : 1; /*!< [5..5] Signaling Message Processing Setting */ + uint32_t : 22; + __IOM uint32_t ILL0 : 1; /*!< [28..28] Illegal Message Processing Setting */ + __IOM uint32_t ILL1 : 1; /*!< [29..29] Illegal Message Processing Setting */ + uint32_t : 2; + } SYRFL2R_b; + }; + + union + { + __IOM uint32_t SYTRENR; /*!< (@ 0x00000098) SYNFP Transmission Enable Register */ + + struct + { + __IOM uint32_t ANCE : 1; /*!< [0..0] Announce Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t SYNC : 1; /*!< [4..4] Sync Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t DRQ : 1; /*!< [8..8] Delay_Req Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t PDRQ : 1; /*!< [12..12] Pdelay_Req Message Transmission Enable */ + uint32_t : 19; + } SYTRENR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t MTCIDU; /*!< (@ 0x000000A0) Master Clock ID Registers */ + + struct + { + __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of the master clock. */ + } MTCIDU_b; + }; + + union + { + __IOM uint32_t MTCIDL; /*!< (@ 0x000000A4) Master Clock ID Registers */ + + struct + { + __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of the master clock. */ + } MTCIDL_b; + }; + + union + { + __IOM uint32_t MTPID; /*!< (@ 0x000000A8) Master clock port number register */ + + struct + { + __IOM uint32_t PNUM : 16; /*!< [15..0] Master Clock Port Number SettingThese bits hold the + * setting for the port number of the master clock. */ + uint32_t : 16; + } MTPID_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t SYTLIR; /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register */ + + struct + { + __IOM uint32_t ANCE : 8; /*!< [7..0] Announce Message Transmission Interval SettingThese bits + * set the interval for the transmission of Announce messages. */ + __IOM uint32_t SYNC : 8; /*!< [15..8] Sync Message Transmission Interval SettingThese bits + * set the interval for the transmission of Sync messages. + * The setting is also placed in the logMessageInterval field + * of transmitted Sync messages. */ + __IOM uint32_t DREQ : 8; /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req + * Transmission Interval SettingThe bits set the average interval + * for the transmission of Delay_Req messages and the interval + * for the transmission of Pdelay_Req messages.The setting + * is also placed in the logMessageInterval field of Delay_Resp + * messages. */ + uint32_t : 8; + } SYTLIR_b; + }; + + union + { + __IM uint32_t SYRLIR; /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication + * Register */ + + struct + { + __IM uint32_t ANCE : 8; /*!< [7..0] Announce Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Announce message. */ + __IM uint32_t SYNC : 8; /*!< [15..8] Sync Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Sync message. */ + __IM uint32_t DRESP : 8; /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Delay_Resp message. */ + uint32_t : 8; + } SYRLIR_b; + }; + + union + { + __IM uint32_t OFMRU; /*!< (@ 0x000000C8) offsetFromMaster Value Registers */ + + struct + { + __IM uint32_t OFMRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated offsetFromMaster value. */ + } OFMRU_b; + }; + + union + { + __IM uint32_t OFMRL; /*!< (@ 0x000000CC) offsetFromMaster Value Registers */ + + struct + { + __IM uint32_t OFMRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * offsetFromMaster value. */ + } OFMRL_b; + }; + + union + { + __IM uint32_t MPDRU; /*!< (@ 0x000000D0) meanPathDelay Value Registers */ + + struct + { + __IM uint32_t MPDRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated meanPathDelay value. */ + } MPDRU_b; + }; + + union + { + __IM uint32_t MPDRL; /*!< (@ 0x000000D4) meanPathDelay Value Registers */ + + struct + { + __IM uint32_t MPDRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * meanPathDelay value. */ + } MPDRL_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint32_t GMPR; /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register */ + + struct + { + __IOM uint32_t GMPR2 : 8; /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are + * used to set the value of the grandmasterPriority2 fields + * of Announce messages. */ + uint32_t : 8; + __IOM uint32_t GMPR1 : 8; /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits + * are used to set the value of the grandmasterPriority1 fields + * of Announce messages. */ + uint32_t : 8; + } GMPR_b; + }; + + union + { + __IOM uint32_t GMCQR; /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register */ + + struct + { + __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality + * fields of Announce messages. The correspondence between + * bits and the grandmasterClockQuality fields is as listed + * below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 + * to b0: offsetScaledLogVariance */ + } GMCQR_b; + }; + + union + { + __IOM uint32_t GMIDRU; /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers */ + + struct + { + __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the value of the grandmasterIdentity fields of + * Announce messages. */ + } GMIDRU_b; + }; + + union + { + __IOM uint32_t GMIDRL; /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers */ + + struct + { + __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the value of the grandmasterIdentity fields of Announce + * messages. */ + } GMIDRL_b; + }; + + union + { + __IOM uint32_t CUOTSR; /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register */ + + struct + { + __IOM uint32_t TSRC : 8; /*!< [7..0] timeSource Field SettingThese bits set the value of the + * timeSource fields of Announce messages. */ + uint32_t : 8; + __IOM uint32_t CUTO : 16; /*!< [31..16] currentUtcOffset Field SettingThese bits set the value + * of the currentUtcOffset fields of Announce messages. */ + } CUOTSR_b; + }; + + union + { + __IOM uint32_t SRR; /*!< (@ 0x000000F4) stepsRemoved Field Setting Register */ + + struct + { + __IOM uint32_t SRMV : 16; /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value + * of the stepsRemoved fields of Announce messages. */ + uint32_t : 16; + } SRR_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t PPMACRU; /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting + * Registers */ + + struct + { + __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRU_b; + }; + + union + { + __IOM uint32_t PPMACRL; /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting + * Registers */ + + struct + { + __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRL_b; + }; + + union + { + __IOM uint32_t PDMACRU; /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers */ + + struct + { + __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRU_b; + }; + + union + { + __IOM uint32_t PDMACRL; /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers */ + + struct + { + __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRL_b; + }; + + union + { + __IOM uint32_t PETYPER; /*!< (@ 0x00000110) PTP Message EtherType Setting Register */ + + struct + { + __IOM uint32_t TYPE : 16; /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the + * setting for the EtherType field value for frames in the + * Ethernet II format. */ + uint32_t : 16; + } PETYPER_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t PPIPR; /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting + * Register */ + + struct + { + __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPprimary messages. */ + } PPIPR_b; + }; + + union + { + __IOM uint32_t PDIPR; /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting + * Register */ + + struct + { + __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPpdelay messages. */ + } PDIPR_b; + }; + + union + { + __IOM uint32_t PETOSR; /*!< (@ 0x00000128) PTP Event Message TOS Setting Register */ + + struct + { + __IOM uint32_t EVTO : 8; /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold + * the setting for the value of the TOS field within the IPv4 + * headers of PTP event messages. */ + uint32_t : 24; + } PETOSR_b; + }; + + union + { + __IOM uint32_t PGTOSR; /*!< (@ 0x0000012C) PTP general Message TOS Setting Register */ + + struct + { + __IOM uint32_t GETO : 8; /*!< [7..0] PTP general Message TOS Field Value SettingThese bits + * hold the setting for the value of the TOS field within + * the IPv4 headers of PTP general messages. */ + uint32_t : 24; + } PGTOSR_b; + }; + + union + { + __IOM uint32_t PPTTLR; /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register */ + + struct + { + __IOM uint32_t PRTL : 8; /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits + * hold the setting for the value of the TTL field within + * the IPv4 headers of PTP-primary messages. */ + uint32_t : 24; + } PPTTLR_b; + }; + + union + { + __IOM uint32_t PDTTLR; /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register */ + + struct + { + __IOM uint32_t PDTL : 8; /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the + * setting for the value of the TTL field within the IPv4 + * headers of PTP-pdelay messages. */ + uint32_t : 24; + } PDTTLR_b; + }; + + union + { + __IOM uint32_t PEUDPR; /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number + * Setting Register */ + + struct + { + __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese + * bits hold the setting for the value of the destination + * port number field within the UDP headers of PTP event messages. */ + uint32_t : 16; + } PEUDPR_b; + }; + + union + { + __IOM uint32_t PGUDPR; /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number + * Setting Register */ + + struct + { + __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits + * hold the setting for the value of the destination port + * number field within the UDP headers of PTP general messages. */ + uint32_t : 16; + } PGUDPR_b; + }; + + union + { + __IOM uint32_t FFLTR; /*!< (@ 0x00000140) Frame Reception Filter Setting Register */ + + struct + { + __IOM uint32_t SEL : 1; /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these + * bits is only effective when EXTPRM=0, ENB=1and RPT=1. */ + __IOM uint32_t PRT : 1; /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0 and ENB=1. */ + __IOM uint32_t ENB : 1; /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0. */ + uint32_t : 13; + __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting */ + uint32_t : 15; + } FFLTR_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t FMAC0RU; /*!< (@ 0x00000160) Frame Reception Filter MAC Address 0 Setting + * Register Upper */ + + struct + { + __IOM uint32_t FMAC0RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination + * MAC address for received multicast frames. */ + uint32_t : 8; + } FMAC0RU_b; + }; + + union + { + __IOM uint32_t FMAC0RL; /*!< (@ 0x00000164) Frame Reception Filter MAC Address 0 Setting + * Register Lower */ + + struct + { + __IOM uint32_t FMAC0RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination + * MAC address for received multicast frames. */ + uint32_t : 8; + } FMAC0RL_b; + }; + + union + { + __IOM uint32_t FMAC1RU; /*!< (@ 0x00000168) Frame Reception Filter MAC Address 1 Setting + * Register Upper */ + + struct + { + __IOM uint32_t FMAC1RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination + * MAC address for received multicast frames. */ + uint32_t : 8; + } FMAC1RU_b; + }; + + union + { + __IOM uint32_t FMAC1RL; /*!< (@ 0x0000016C) Frame Reception Filter MAC Address 1 Setting + * Register Lower */ + + struct + { + __IOM uint32_t FMAC1RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination + * MAC address for received multicast frames. */ + uint32_t : 8; + } FMAC1RL_b; + }; + __IM uint32_t RESERVED11[20]; + + union + { + __IOM uint32_t DASYMRU; /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers */ + + struct + { + __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the asymmetric delay value. */ + uint32_t : 16; + } DASYMRU_b; + }; + + union + { + __IOM uint32_t DASYMRL; /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers */ + + struct + { + __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the asymmetric delay value. */ + } DASYMRL_b; + }; + + union + { + __IOM uint32_t TSLATR; /*!< (@ 0x000001C8) Timestamp Latency Setting Register */ + + struct + { + __IOM uint32_t EGP : 16; /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the input + * ports. */ + __IOM uint32_t INGP : 16; /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the output + * ports. */ + } TSLATR_b; + }; + + union + { + __IOM uint32_t SYCONFR; /*!< (@ 0x000001CC) SYNFP Operation Setting Register */ + + struct + { + __IOM uint32_t TCYC : 8; /*!< [7..0] PTP Message Transmission Interval SettingThese bits are + * used to set the time from the completion of one transmission + * to the start of the next in cycles of the transmission + * clock. A value n in these bits means that a transmission + * interval of n cycles will be secured.No interval is secured + * if the setting is 00h.We recommend the setting 28h (40 + * cycles). */ + uint32_t : 4; + __IOM uint32_t SBDIS : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable */ + uint32_t : 3; + __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable */ + uint32_t : 3; + __IOM uint32_t TCMOD : 1; /*!< [20..20] TC Mode Setting */ + uint32_t : 11; + } SYCONFR_b; + }; + + union + { + __IOM uint32_t SYFORMR; /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register */ + + struct + { + __IOM uint32_t FORM0 : 1; /*!< [0..0] Ethernet/UDP Encapsulation */ + __IOM uint32_t FORM1 : 1; /*!< [1..1] Ethernet Frame Format Setting */ + uint32_t : 30; + } SYFORMR_b; + }; + + union + { + __IOM uint32_t RSTOUTR; /*!< (@ 0x000001D4) Response Message Reception Timeout Register */ + + struct + { + __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response + * message not being received within n x 1024 (ns), where + * n is the setting, is judged to represent a timeout. */ + } RSTOUTR_b; + }; +} R_ETHERC_EPTPC_Type; /*!< Size = 472 (0x1d8) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_CFG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG) + */ + +typedef struct /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure */ +{ + union + { + __IOM uint32_t PTRSTR; /*!< (@ 0x00000000) EPTPC Reset Register */ + + struct + { + __IOM uint32_t RESET : 1; /*!< [0..0] EPTPC Software Reset */ + uint32_t : 31; + } PTRSTR_b; + }; + + union + { + __IOM uint32_t STCSELR; /*!< (@ 0x00000004) STCA Clock Select Register */ + + struct + { + __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division */ + uint32_t : 5; + __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select */ + uint32_t : 21; + } STCSELR_b; + }; + + union + { + __IOM uint32_t BYPASS; /*!< (@ 0x00000008) Bypass 1588 module Register */ + + struct + { + __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch */ + uint32_t : 15; + __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch */ + uint32_t : 15; + } BYPASS_b; + }; +} R_ETHERC_EPTPC_CFG_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON) + */ + +typedef struct /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure */ +{ + union + { + __IOM uint32_t MIESR; /*!< (@ 0x00000000) MINT Interrupt Source Status Register */ + + struct + { + __IM uint32_t ST : 1; /*!< [0..0] STCA Status Flag */ + __IM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Flag */ + __IM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Flag */ + __IM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Flag */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag */ + uint32_t : 10; + } MIESR_b; + }; + + union + { + __IOM uint32_t MIEIPR; /*!< (@ 0x00000004) MINT Interrupt Request Permission Register */ + + struct + { + __IOM uint32_t ST : 1; /*!< [0..0] STCA Status Interrupt Request Permission */ + __IOM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Interrupt Request Permission */ + __IOM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Interrupt Request Permission */ + __IOM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Interrupt Request Permission */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt + * Request Permission */ + uint32_t : 10; + } MIEIPR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t ELIPPR; /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission + * Register */ + + struct + { + __IOM uint32_t CYCP0 : 1; /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + } ELIPPR_b; + }; + + union + { + __IOM uint32_t ELIPACR; /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic + * Clearing Register */ + + struct + { + __IOM uint32_t CYCP0 : 1; /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing */ + uint32_t : 7; + } ELIPACR_b; + }; + __IM uint32_t RESERVED1[10]; + + union + { + __IOM uint32_t STSR; /*!< (@ 0x00000040) STCA Status Register */ + + struct + { + __IOM uint32_t SYNC : 1; /*!< [0..0] Synchronized State Detection Flag */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag */ + __IOM uint32_t W10D : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag */ + uint32_t : 27; + } STSR_b; + }; + + union + { + __IOM uint32_t STIPR; /*!< (@ 0x00000044) STCA Status Notification Permission Register */ + + struct + { + __IOM uint32_t SYNC : 1; /*!< [0..0] SYNC Status Notification Enable */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable */ + __IOM uint32_t W10D : 1; /*!< [4..4] W10D Status Notification Enable */ + uint32_t : 27; + } STIPR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t STCFR; /*!< (@ 0x00000050) STCA Clock Frequency Setting Register */ + + struct + { + __IOM uint32_t STCF : 2; /*!< [1..0] STCA Clock Frequency */ + uint32_t : 30; + } STCFR_b; + }; + + union + { + __IOM uint32_t STMR; /*!< (@ 0x00000054) STCA Operating Mode Register */ + + struct + { + __IOM uint32_t WINT : 8; /*!< [7..0] Worst 10 Acquisition Time */ + uint32_t : 5; + __IOM uint32_t CMOD : 1; /*!< [13..13] Time Synchronization Correction Mode */ + uint32_t : 1; + __IOM uint32_t W10S : 1; /*!< [15..15] Worst 10 Acquisition Control Select */ + __IOM uint32_t SYTH : 4; /*!< [19..16] Synchronized State Detection Threshold Setting */ + __IOM uint32_t DVTH : 4; /*!< [23..20] Synchronization Loss Detection Threshold Setting */ + uint32_t : 4; + __IOM uint32_t ALEN0 : 1; /*!< [28..28] Alarm Detection Enable 0 */ + __IOM uint32_t ALEN1 : 1; /*!< [29..29] Alarm Detection Enable 1 */ + uint32_t : 2; + } STMR_b; + }; + + union + { + __IOM uint32_t SYNTOR; /*!< (@ 0x00000058) Sync Message Reception Timeout Register */ + + struct + { + __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns), + * where n is the setting, leads to a timeout for reception + * of Sync messages, leading to the STSR.SYNTOUT flag being + * set to 1. */ + } SYNTOR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t IPTSELR; /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register */ + + struct + { + __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select */ + __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select */ + __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select */ + __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select */ + __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select */ + __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select */ + uint32_t : 26; + } IPTSELR_b; + }; + + union + { + __IOM uint32_t MITSELR; /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register */ + + struct + { + __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable */ + uint32_t : 26; + } MITSELR_b; + }; + + union + { + __IOM uint32_t ELTSELR; /*!< (@ 0x00000068) ELC Output Timer Select Register */ + + struct + { + __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable */ + __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable */ + __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable */ + __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable */ + __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable */ + __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable */ + uint32_t : 26; + } ELTSELR_b; + }; + + union + { + __IOM uint32_t STCHSELR; /*!< (@ 0x0000006C) Time Synchronization Channel Select Register */ + + struct + { + __IOM uint32_t SYSEL : 1; /*!< [0..0] Timer Information Input SelectNOTE: Do not change the + * value of this bit while the SYNSTARTR.STR bit is 1. */ + uint32_t : 31; + } STCHSELR_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t SYNSTARTR; /*!< (@ 0x00000080) Slave Time Synchronization Start Register */ + + struct + { + __IOM uint32_t STR : 1; /*!< [0..0] Slave Time Synchronization Control */ + uint32_t : 31; + } SYNSTARTR_b; + }; + + union + { + __OM uint32_t LCIVLDR; /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive + * Register */ + + struct + { + __OM uint32_t LOAD : 1; /*!< [0..0] Local Time Counter Initial Value Load Directive */ + uint32_t : 31; + } LCIVLDR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SYNTDARU; /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of loss of synchronization. */ + } SYNTDARU_b; + }; + + union + { + __IOM uint32_t SYNTDARL; /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of loss of synchronization. */ + } SYNTDARL_b; + }; + + union + { + __IOM uint32_t SYNTDBRU; /*!< (@ 0x00000098) Synchronization Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of synchronization. */ + } SYNTDBRU_b; + }; + + union + { + __IOM uint32_t SYNTDBRL; /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of synchronization. */ + } SYNTDBRL_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t LCIVRU; /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the integer portion of the initial value for the + * local timer counter. */ + uint32_t : 16; + } LCIVRU_b; + }; + + union + { + __IOM uint32_t LCIVRM; /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the integer portion of the initial value for the local + * timer counter. */ + } LCIVRM_b; + }; + + union + { + __IOM uint32_t LCIVRL; /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion + * of the initial value of the local timer counter in nanoseconds. */ + } LCIVRL_b; + }; + __IM uint32_t RESERVED7[26]; + + union + { + __IOM uint32_t GETW10R; /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register */ + + struct + { + __IOM uint32_t GW10 : 1; /*!< [0..0] Worst 10 Acquisition Directive */ + uint32_t : 31; + } GETW10R_b; + }; + + union + { + __IOM uint32_t PLIMITRU; /*!< (@ 0x00000128) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the positive gradient. */ + uint32_t : 1; + } PLIMITRU_b; + }; + + union + { + __IOM uint32_t PLIMITRM; /*!< (@ 0x0000012C) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the positive gradient. */ + } PLIMITRM_b; + }; + + union + { + __IOM uint32_t PLIMITRL; /*!< (@ 0x00000130) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the positive gradient. */ + } PLIMITRL_b; + }; + + union + { + __IOM uint32_t MLIMITRU; /*!< (@ 0x00000134) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the negative gradient. */ + uint32_t : 1; + } MLIMITRU_b; + }; + + union + { + __IOM uint32_t MLIMITRM; /*!< (@ 0x00000138) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the negative gradient. */ + } MLIMITRM_b; + }; + + union + { + __IOM uint32_t MLIMITRL; /*!< (@ 0x0000013C) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the negative gradient. */ + } MLIMITRL_b; + }; + + union + { + __IOM uint32_t GETINFOR; /*!< (@ 0x00000140) Statistical Information Retention Control Register */ + + struct + { + __IOM uint32_t INFO : 1; /*!< [0..0] Information Retention ControlNOTE: Once information fetching + * is directed, values of various statistical information + * read before completion of information fetching are not + * guaranteed. */ + uint32_t : 31; + } GETINFOR_b; + }; + __IM uint32_t RESERVED8[11]; + + union + { + __IM uint32_t LCCVRU; /*!< (@ 0x00000170) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits + * of the integer portion of the local timer counter's value. */ + uint32_t : 16; + } LCCVRU_b; + }; + + union + { + __IM uint32_t LCCVRM; /*!< (@ 0x00000174) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the integer portion of the local timer counter's value. */ + } LCCVRM_b; + }; + + union + { + __IM uint32_t LCCVRL; /*!< (@ 0x00000178) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of + * the local timer counter's value (in nanoseconds). */ + } LCCVRL_b; + }; + __IM uint32_t RESERVED9[37]; + + union + { + __IM uint32_t PW10VRU; /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the positive gradient value. */ + } PW10VRU_b; + }; + + union + { + __IM uint32_t PW10VRM; /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the positive gradient value. */ + } PW10VRM_b; + }; + + union + { + __IM uint32_t PW10VRL; /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the positive gradient value. */ + } PW10VRL_b; + }; + __IM uint32_t RESERVED10[45]; + + union + { + __IM uint32_t MW10RU; /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the negative gradient value. */ + } MW10RU_b; + }; + + union + { + __IM uint32_t MW10RM; /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the negative gradient value. */ + } MW10RM_b; + }; + + union + { + __IM uint32_t MW10RL; /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the negative gradient value. */ + } MW10RL_b; + }; + __IM uint32_t RESERVED11[9]; + __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers */ + __IM uint32_t RESERVED12[7]; + + union + { + __IOM uint32_t TMSTARTR; /*!< (@ 0x0000037C) Timer Start Register */ + + struct + { + __IOM uint32_t EN0 : 1; /*!< [0..0] Pulse Output Timer 0 Start */ + __IOM uint32_t EN1 : 1; /*!< [1..1] Pulse Output Timer 1 Start */ + __IOM uint32_t EN2 : 1; /*!< [2..2] Pulse Output Timer 2 Start */ + __IOM uint32_t EN3 : 1; /*!< [3..3] Pulse Output Timer 3 Start */ + __IOM uint32_t EN4 : 1; /*!< [4..4] Pulse Output Timer 4 Start */ + __IOM uint32_t EN5 : 1; /*!< [5..5] Pulse Output Timer 5 Start */ + uint32_t : 26; + } TMSTARTR_b; + }; + __IM uint32_t RESERVED13[32]; + + union + { + __IOM uint32_t PRSR; /*!< (@ 0x00000400) PRC-TC Status Register */ + + struct + { + __IOM uint32_t OVRE0 : 1; /*!< [0..0] Relay Packet Overflow Detection Flag 0 */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] Relay Packet Overflow Detection Flag 1 */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] Relay Packet Overflow Detection Flag 2 */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] Relay Packet Overflow Detection Flag 3 */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] Originating MAC Address Mismatch Detection Flag */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] Relay Packet Underflow Detection Flag 0 */ + __IOM uint32_t URE1 : 1; /*!< [29..29] Relay Packet Underflow Detection Flag 1 */ + uint32_t : 2; + } PRSR_b; + }; + + union + { + __IOM uint32_t PRIPR; /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register */ + + struct + { + __IOM uint32_t OVRE0 : 1; /*!< [0..0] PRSR.OVRE0 Status Notification Permission */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] PRSR.OVRE1 Status Notification Permission */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] PRSR.OVRE2 Status Notification Permission */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] PRSR.OVRE3 Status Notification Permission */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] PRSR.MACE Status Notification Permission */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] PRSR.URE0 Status Notification Permission */ + __IOM uint32_t URE1 : 1; /*!< [29..29] PRSR.URE1 Status Notification Permission */ + uint32_t : 2; + } PRIPR_b; + }; + __IM uint32_t RESERVED14[2]; + __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers */ + + union + { + __IOM uint32_t TRNDISR; /*!< (@ 0x00000420) Packet Transmission Control Register */ + + struct + { + __IOM uint32_t TDIS : 2; /*!< [1..0] Packet Transmission Control */ + uint32_t : 30; + } TRNDISR_b; + }; + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint32_t TRNMR; /*!< (@ 0x00000430) Relay Mode Register */ + + struct + { + __IOM uint32_t MOD : 1; /*!< [0..0] Cut-Through Mode */ + uint32_t : 7; + __IOM uint32_t FWD0 : 1; /*!< [8..8] Channel 0 Relay Enable */ + __IOM uint32_t FWD1 : 1; /*!< [9..9] Channel 1 Relay Enable */ + uint32_t : 22; + } TRNMR_b; + }; + + union + { + __IOM uint32_t TRNCTTDR; /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register */ + + struct + { + __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read + * data from the relay FIFO in cut-through mode (specified + * as the number of bytes)NOTE1: A value cannot be set in + * the lower-order 2 bits. These bits are fixed to 0.NOTE2: + * A value of less than 96 bytes cannot be set. */ + uint32_t : 21; + } TRNCTTDR_b; + }; +} R_ETHERC_EPTPC_COMMON_Type; /*!< Size = 1080 (0x438) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } FCNTSELR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR0_b; + }; + + union + { + __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[11]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ + + struct + { + __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address + * or the last blank checked address which is found in 'Blank + * Check' command execution. */ + uint32_t : 8; + } FBCADDR_b; + }; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t PFBERSA : 1; /*!< [1..1] PFBERSA Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution */ + uint16_t : 4; + __IOM uint16_t DFLCTLSA : 1; /*!< [15..15] DFLCTL Security Attribution */ + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x400E0000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 3; /*!< [26..24] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 1; + __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select */ + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + + union + { + __IOM uint32_t WUPEN2; /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t INTUR0WUPEN : 1; /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE0WUPEN : 1; /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t INTUR1WUPEN : 1; /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return + * Enable */ + __IOM uint32_t INTURE1WUPEN : 1; /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode + * Return Enable */ + __IOM uint32_t USBCCSWUPEN : 1; /*!< [4..4] USBCC Status Change Interrupt Software Standby/Snooze + * Mode */ + uint32_t : 27; + } WUPEN2_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IrDA Interface (R_IRDA) + */ + +typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ +{ + union + { + __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ + __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ + uint8_t : 3; + __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ + } IRCR_b; + }; +} R_IRDA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_JPEG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief JPEG Codec (R_JPEG) + */ + +typedef struct /*!< (@ 0x400E6000) R_JPEG Structure */ +{ + union + { + __IOM uint8_t JCMOD; /*!< (@ 0x00000000) JPEG Code Mode Register */ + + struct + { + __IOM uint8_t REDU : 3; /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression. */ + __IOM uint8_t DSP : 1; /*!< [3..3] Compression/Decompression Set Note: When changing between + * processing for compression and for decompression, be sure + * to reset this module in advance by setting the JCUSRST + * bit in the software reset control register 2 (SWRSTCR2) + * of the power-downmodes. */ + uint8_t : 4; + } JCMOD_b; + }; + + union + { + __OM uint8_t JCCMD; /*!< (@ 0x00000001) JPEG Code Command Register */ + + struct + { + __OM uint8_t JSRT : 1; /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing, + * set this bit to 1. Do not write this bit to 1 again while + * this module is in operation. */ + __OM uint8_t JRST : 1; /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped + * state caused by requests to read the image size and pixel + * format (enabled by the INT3 bit in JINTE0), set this bit + * to 1. */ + __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only + * for the interrupt sources corresponding to bits INS6, INS5, + * and INS3 in JINTS0. To clear an interrupt request, set + * this bit to 1 */ + uint8_t : 4; + __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the + * bus reset command should not be issued. */ + } JCCMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t JCQTN; /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register */ + + struct + { + __IOM uint8_t QT1 : 2; /*!< [1..0] Quantization table number for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t QT2 : 2; /*!< [3..2] Quantization table number for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t QT3 : 2; /*!< [5..4] Quantization table number for the third color component + * NOTE: Read-only in Decompression. */ + uint8_t : 2; + } JCQTN_b; + }; + + union + { + __IOM uint8_t JCHTN; /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register */ + + struct + { + __IOM uint8_t HTD1 : 1; /*!< [0..0] Huffman table number (DC) for the first color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA1 : 1; /*!< [1..1] Huffman table number (AC) for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD2 : 1; /*!< [2..2] Huffman table number (DC) for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA2 : 1; /*!< [3..3] Huffman table number (AC) for the second color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD3 : 1; /*!< [4..4] Huffman table number (DC) for the third color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA3 : 1; /*!< [5..5] Huffman table number (AC) for the third color componentNOTE: + * Read-only in Decompression. */ + uint8_t : 2; + } JCHTN_b; + }; + + union + { + __IOM uint8_t JCDRIU; /*!< (@ 0x00000005) JPEG Code DRI Upper Register */ + + struct + { + __IOM uint8_t DRIU : 8; /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRIU_b; + }; + + union + { + __IOM uint8_t JCDRID; /*!< (@ 0x00000006) JPEG Code DRI Lower Register */ + + struct + { + __IOM uint8_t DRID : 8; /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRID_b; + }; + + union + { + __IOM uint8_t JCVSZU; /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register */ + + struct + { + __IOM uint8_t VSZU : 8; /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZU_b; + }; + + union + { + __IOM uint8_t JCVSZD; /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register */ + + struct + { + __IOM uint8_t VSZD : 8; /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZD_b; + }; + + union + { + __IOM uint8_t JCHSZU; /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register */ + + struct + { + __IOM uint8_t HSZU : 8; /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZU_b; + }; + + union + { + __IOM uint8_t JCHSZD; /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register */ + + struct + { + __IOM uint8_t HSZD : 8; /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZD_b; + }; + + union + { + __IM uint8_t JCDTCU; /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register */ + + struct + { + __IM uint8_t DCU : 8; /*!< [7..0] Upper bytes of the counted amount of data to be compressed + * The values of this register are reset before compression + * starts.NOTE: Read-only in Decompression. */ + } JCDTCU_b; + }; + + union + { + __IM uint8_t JCDTCM; /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register */ + + struct + { + __IM uint8_t DCM : 8; /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts. + * NOTE: Read-only in Decompression. */ + } JCDTCM_b; + }; + + union + { + __IM uint8_t JCDTCD; /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register */ + + struct + { + __IM uint8_t DCD : 8; /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts.NOTE: + * Read-only in Decompression. */ + } JCDTCD_b; + }; + + union + { + __IOM uint8_t JINTE0; /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0 */ + + struct + { + uint8_t : 3; + __IOM uint8_t INT3 : 1; /*!< [3..3] This bit enables an interrupt to be generated when it + * has been determined that the image size and the subsampling + * setting of the compressed data can be read through analyzing + * the data. */ + uint8_t : 1; + __IOM uint8_t INT5 : 1; /*!< [5..5] This bit enables an interrupt to be generated when the + * final number of MCU data in the Huffman-coding segment + * is not correct in decompression. When this bit is not set + * to enable interrupt generation, an error code is not returned. */ + __IOM uint8_t INT6 : 1; /*!< [6..6] This bit enables an interrupt to be generated when the + * total number of data in the Huffman-coding segment is not + * correct in decompression. When this bit is not set to enable + * interrupt generation, an error code is not returned. */ + __IOM uint8_t INT7 : 1; /*!< [7..7] This bit enables an interrupt to be generated when the + * number of data in the restart interval of the Huffman-coding + * segment is not correct in decompression.When this bit is + * not set to enable interrupt generation, an error code is + * not returned. */ + } JINTE0_b; + }; + + union + { + __IOM uint8_t JINTS0; /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0 */ + + struct + { + uint8_t : 3; + __IOM uint8_t INS3 : 1; /*!< [3..3] This bit is set to 1 when the image size and pixel format + * can be read. When an interrupt occurs, this module stops + * processing and the state is indicated by the JCRST register. + * To make this module resume processing, set the JPEG core + * process stop clear command bit (JRST) in JCCMD. */ + uint8_t : 1; + __IOM uint8_t INS5 : 1; /*!< [5..5] This bit is set to 1 when a compressed data error occurs. */ + __IOM uint8_t INS6 : 1; /*!< [6..6] This bit is set to 1 when this module completes compression + * process normally. */ + uint8_t : 1; + } JINTS0_b; + }; + + union + { + __IOM uint8_t JCDERR; /*!< (@ 0x00000010) JPEG Code Decode Error Register */ + + struct + { + __IOM uint8_t ERR : 4; /*!< [3..0] Error Code (See tables )Identify the type of the error + * which has occurred in the compressed data analysis for + * decompression. */ + uint8_t : 4; + } JCDERR_b; + }; + + union + { + __IM uint8_t JCRST; /*!< (@ 0x00000011) JPEG Code Reset Register */ + + struct + { + __IM uint8_t RST : 1; /*!< [0..0] Operating State */ + uint8_t : 7; + } JCRST_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[11]; + + union + { + __IOM uint32_t JIFECNT; /*!< (@ 0x00000040) JPEG Interface Compression Control Register */ + + struct + { + __IOM uint32_t DINSWAP : 3; /*!< [2..0] Byte/Halfword Swap */ + uint32_t : 1; + __IOM uint32_t DINLC : 1; /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines */ + __OM uint32_t DINRCMD : 1; /*!< [5..5] Input Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the input of image + * data lines is on. Setting this bit to 1 resumes reading + * input image data. This bit is always read as 0. */ + __IOM uint32_t DINRINI : 1; /*!< [6..6] Address Initialization when Resuming Input of Image Data + * Lines This bit is only valid when the count mode for stopping + * the input of image data lines is on. Set this bit before + * writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression + * is swapped. */ + uint32_t : 21; + } JIFECNT_b; + }; + + union + { + __IOM uint32_t JIFESA; /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register */ + + struct + { + __IOM uint32_t ESA : 32; /*!< [31..0] Input Image Data Source Address (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFESA_b; + }; + + union + { + __IOM uint32_t JIFESOFST; /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register */ + + struct + { + __IOM uint32_t ESMW : 15; /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower + * three bits should be set to 0. */ + uint32_t : 17; + } JIFESOFST_b; + }; + + union + { + __IOM uint32_t JIFEDA; /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address + * Register */ + + struct + { + __IOM uint32_t EDA : 32; /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFEDA_b; + }; + + union + { + __IOM uint32_t JIFESLC; /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count + * Register */ + + struct + { + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line + * units) The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFESLC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t JIFDCNT; /*!< (@ 0x00000058) JPEG Interface Decompression Control Register */ + + struct + { + __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is + * swapped. */ + uint32_t : 1; + __IOM uint32_t DOUTLC : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines */ + __OM uint32_t DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the output of image + * data lines is on. Setting this bit to 1 resumes writing + * image data. This bit is always read as 0. */ + __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image + * Data Lines This bit is only valid when the count mode for + * stopping the output of image data lines is on. Set this + * bit before writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JINSWAP : 3; /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression + * is swapped. */ + uint32_t : 1; + __IOM uint32_t JINC : 1; /*!< [12..12] Count Mode Setting for Stopping Input Coded Data */ + __OM uint32_t JINRCMD : 1; /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only + * when the count mode for stopping the input of coded data + * is on. Setting this bit to 1 resumes reading input coded + * data. This bit is always read as 0. */ + __IOM uint32_t JINRINI : 1; /*!< [14..14] Address Initialization when Input Coded Data is Resumed + * This bit is only valid when the count mode for stopping + * the input of coded data is on. Set this bit before writing + * 1 to the data resume command bit. */ + uint32_t : 9; + __IOM uint32_t OPF : 2; /*!< [25..24] Specifies output image data pixel format. */ + __IOM uint32_t HINTER : 2; /*!< [27..26] Horizontal Subsampling Subsamples horizontal output + * image data. */ + __IOM uint32_t VINTER : 2; /*!< [29..28] Vertical SubsamplingSubsamples vertical output image + * data. */ + uint32_t : 2; + } JIFDCNT_b; + }; + + union + { + __IOM uint32_t JIFDSA; /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register */ + + struct + { + __IOM uint32_t DSA : 32; /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source + * Address (in 8-byte units) The lower three bits should be + * set to 0. */ + } JIFDSA_b; + }; + + union + { + __IOM uint32_t JIFDDOFST; /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register */ + + struct + { + __IOM uint32_t DDMW : 15; /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + uint32_t : 17; + } JIFDDOFST_b; + }; + + union + { + __IOM uint32_t JIFDDA; /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address + * Register */ + + struct + { + __IOM uint32_t DDA : 32; /*!< [31..0] Output Image Data Destination Address (in 8-byte units) + * The lower three bits should be set to 0. */ + } JIFDDA_b; + }; + + union + { + __IOM uint32_t JIFDSDC; /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count + * Register */ + + struct + { + __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units) + * The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFDSDC_b; + }; + + union + { + __IOM uint32_t JIFDDLC; /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line + * Count Register */ + + struct + { + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three + * bits should be set to 0. These bits are read as0.Number + * of input image data lines to be read, in 8-line units. */ + uint32_t : 16; + } JIFDDLC_b; + }; + + union + { + __IOM uint32_t JIFDADT; /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register */ + + struct + { + __IOM uint32_t ALPHA : 8; /*!< [7..0] Setting of the alpha value for output in ARGB8888 format. */ + uint32_t : 24; + } JIFDADT_b; + }; + __IM uint32_t RESERVED4[6]; + + union + { + __IOM uint32_t JINTE1; /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DOUTLF bit in JINTS1 is set to + * 1 */ + __IOM uint32_t JINEN : 1; /*!< [1..1] Enables or disables a data transfer processing interrupt + * request (JDTI) when the JINF bit in JINTS1 is set to 1. */ + __IOM uint32_t DBTEN : 1; /*!< [2..2] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DBTF bit in JINTS1 is set to 1. */ + uint32_t : 2; + __IOM uint32_t DINLEN : 1; /*!< [5..5] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DINLF bit in JINTS1 is set to 1. */ + __IOM uint32_t CBTEN : 1; /*!< [6..6] Enables or disables a data transfer processing interrupt + * request (JDTI) when the CBTF bit in JINTS1 is set to 1. */ + uint32_t : 25; + } JINTE1_b; + }; + + union + { + __IOM uint32_t JINTS1; /*!< (@ 0x00000090) JPEG Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number + * of lines of output image data indicated by JIFDDLC have + * been written. This bit is only valid when the DOUTLC bit + * in JIFDCNT is set to 1. */ + __IOM uint32_t JINF : 1; /*!< [1..1] This bit is set to 1 when the amount of input coded data + * indicated by JIFDSDC is read in decompression. This bit + * is valid only when the JINC bit in JIFDCNT is set to 1. */ + __IOM uint32_t DBTF : 1; /*!< [2..2] This bit is set to 1 when the last output image data + * is written in decompression. */ + uint32_t : 2; + __IOM uint32_t DINLF : 1; /*!< [5..5] This bit is set to 1 when the number of input image data + * lines indicated by JIFESLC is read in compression. This + * bit is valid only when the DINLC bit in JIFECNT is set + * to 1. */ + __IOM uint32_t CBTF : 1; /*!< [6..6] This bit is set to 1 when the last output coded data + * is written in compression. */ + uint32_t : 25; + } JINTS1_b; + }; + __IM uint32_t RESERVED5[27]; + __OM uint8_t JCQTBL0[64]; /*!< (@ 0x00000100) Quantization Table 0 */ + __OM uint8_t JCQTBL1[64]; /*!< (@ 0x00000140) Quantization Table 1 */ + __OM uint8_t JCQTBL2[64]; /*!< (@ 0x00000180) Quantization Table 2 */ + __OM uint8_t JCQTBL3[64]; /*!< (@ 0x000001C0) Quantization Table 3 */ + __IOM uint8_t JCHTBD0[28]; /*!< (@ 0x00000200) DC Huffman Table 0 */ + __IM uint32_t RESERVED6; + __IOM uint8_t JCHTBA0[178]; /*!< (@ 0x00000220) AC Huffman Table 0 */ + __IM uint16_t RESERVED7; + __IM uint32_t RESERVED8[11]; + __IOM uint8_t JCHTBD1[28]; /*!< (@ 0x00000300) DC Huffman Table 1 */ + __IM uint32_t RESERVED9; + __IOM uint8_t JCHTBA1[178]; /*!< (@ 0x00000320) DC Huffman Table 1 */ + __IM uint16_t RESERVED10; +} R_JPEG_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Slave MPU (R_MPU_SMPU) + */ + +typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ +{ + union + { + __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting + * of the PROTECT and OAD bit. */ + } SMPUCTL_b; + }; + __IM uint16_t RESERVED[7]; + __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ +} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Parallel Data Capture Unit (R_PDC) + */ + +typedef struct /*!< (@ 0x40094000) R_PDC Structure */ +{ + union + { + __IOM uint32_t PCCR0; /*!< (@ 0x00000000) PDC Control Register 0 */ + + struct + { + __IOM uint32_t PCKE : 1; /*!< [0..0] Channel 0 GTCNT Count Clear */ + __IOM uint32_t VPS : 1; /*!< [1..1] VSYNC Signal Polarity Select */ + __IOM uint32_t HPS : 1; /*!< [2..2] HSYNC Signal Polarity Select */ + __OM uint32_t PRST : 1; /*!< [3..3] PDC Reset */ + __IOM uint32_t DFIE : 1; /*!< [4..4] Receive Data Ready Interrupt Enable */ + __IOM uint32_t FEIE : 1; /*!< [5..5] Frame End Interrupt Enable */ + __IOM uint32_t OVIE : 1; /*!< [6..6] Overrun Interrupt Enable */ + __IOM uint32_t UDRIE : 1; /*!< [7..7] Underrun Interrupt Enable */ + __IOM uint32_t VERIE : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable */ + __IOM uint32_t HERIE : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable */ + __IOM uint32_t PCKOE : 1; /*!< [10..10] PCKO Output Enable */ + __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select */ + __IOM uint32_t EDS : 1; /*!< [14..14] Endian Select */ + uint32_t : 17; + } PCCR0_b; + }; + + union + { + __IOM uint32_t PCCR1; /*!< (@ 0x00000004) PDC Control Register 1 */ + + struct + { + __IOM uint32_t PCE : 1; /*!< [0..0] PDC Operation Enable */ + uint32_t : 31; + } PCCR1_b; + }; + + union + { + __IOM uint32_t PCSR; /*!< (@ 0x00000008) PDC Status Register */ + + struct + { + __IM uint32_t FBSY : 1; /*!< [0..0] Frame Busy Flag */ + __IM uint32_t FEMPF : 1; /*!< [1..1] FIFO Empty Flag */ + __IOM uint32_t FEF : 1; /*!< [2..2] Frame End Flag */ + __IOM uint32_t OVRF : 1; /*!< [3..3] Overrun Flag */ + __IOM uint32_t UDRF : 1; /*!< [4..4] Underrun Flag */ + __IOM uint32_t VERF : 1; /*!< [5..5] Vertical Line Number Setting Error Flag */ + __IOM uint32_t HERF : 1; /*!< [6..6] Horizontal Byte Number Setting Error Flag */ + uint32_t : 25; + } PCSR_b; + }; + + union + { + __IM uint32_t PCMONR; /*!< (@ 0x0000000C) PDC Pin Monitor Register */ + + struct + { + __IM uint32_t VSYNC : 1; /*!< [0..0] VSYNC Signal Status Flag */ + __IM uint32_t HSYNC : 1; /*!< [1..1] HSYNC Signal Status Flag */ + uint32_t : 30; + } PCMONR_b; + }; + + union + { + __IM uint32_t PCDR; /*!< (@ 0x00000010) PDC Receive Data Register */ + + struct + { + __IM uint32_t PCDR : 32; /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the + * storage of captured data. The PCDR register is a 4-byte + * space to which the FIFO is mapped, and four bytes of data + * are read from the PCDR register at a time. */ + } PCDR_b; + }; + + union + { + __IOM uint32_t VCR; /*!< (@ 0x00000014) Vertical Capture Register */ + + struct + { + __IOM uint32_t VST : 12; /*!< [11..0] Vertical Capture Start Line PositionNumber of the line + * where capture is to start. */ + uint32_t : 4; + __IOM uint32_t VSZ : 12; /*!< [27..16] Vertical Capture Size Number of lines to be captured. */ + uint32_t : 4; + } VCR_b; + }; + + union + { + __IOM uint32_t HCR; /*!< (@ 0x00000018) Horizontal Capture Register */ + + struct + { + __IOM uint32_t HST : 12; /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position + * in bytes where capture is to start. */ + uint32_t : 4; + __IOM uint32_t HSZ : 12; /*!< [27..16] Horizontal Capture Size Number of bytes to capture + * horizontally. */ + uint32_t : 4; + } HCR_b; + }; +} R_PDC_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[4]; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t PRWCNTR; /*!< (@ 0x0000000F) Port Read Wait Control Register */ + + struct + { + __IOM uint8_t WAIT : 2; /*!< [1..0] Wait Cycle Control */ + uint8_t : 6; + } PRWCNTR_b; + }; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Address bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40062000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Sampling Rate Converter (R_SRC) + */ + +typedef struct /*!< (@ 0x40048000) R_SRC Structure */ +{ + union + { + __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */ + + struct + { + __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */ + uint32_t : 10; + } SRCFCTR_b[5552]; + }; + __IM uint32_t RESERVED[588]; + + union + { + __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */ + + struct + { + __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to + * input the data before sampling rate conversion. All the + * bits are read as 0. */ + } SRCID_b; + }; + + union + { + __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */ + + struct + { + __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output + * the data after sampling rate conversion. The data in the + * 16-stage output data FIFO is read through SRCOD. When the + * number of data in the output data FIFO is zero after the + * start of conversion, the value previously read is read + * again. */ + } SRCOD_b; + }; + + union + { + __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */ + + struct + { + __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */ + uint16_t : 6; + __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */ + __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */ + uint16_t : 6; + } SRCIDCTRL_b; + }; + + union + { + __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */ + + struct + { + __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */ + uint16_t : 6; + __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */ + __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */ + __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */ + uint16_t : 5; + } SRCODCTRL_b; + }; + + union + { + __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */ + + struct + { + __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */ + uint16_t : 1; + __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */ + __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */ + __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */ + __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */ + __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */ + __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */ + __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */ + } SRCCTRL_b; + }; + + union + { + __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */ + + struct + { + __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */ + __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */ + __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */ + __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */ + __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */ + __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */ + uint16_t : 1; + __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units + * in the input FIFO. */ + __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data + * units in the output FIFO. */ + } SRCSTAT_b; + }; +} R_SRC_Type; /*!< Size = 24576 (0x6000) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + + union + { + __IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register + * 2 */ + + struct + { + __IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */ + uint8_t : 1; + __IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */ + uint8_t : 2; + } HOCOCR2_b; + }; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED15[3]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED17; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ + + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000071) I3C clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 5; + } I3CCKDIVCR_b; + }; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ + uint8_t : 3; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED22; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED28[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED29[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED30; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED36[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } CGFSAR_b; + }; + __IM uint32_t RESERVED37; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED39[6]; + __IM uint16_t RESERVED40; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED41; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED42; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED43; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED46[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED47; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED48; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED51; + __IM uint32_t RESERVED52[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED53; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED54; + __IM uint32_t RESERVED55[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED57; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED58; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED59; + __IM uint16_t RESERVED60; + __IM uint32_t RESERVED61[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x40085000UL + #define R_ACMPHS1_BASE 0x40085100UL + #define R_ACMPHS2_BASE 0x40085200UL + #define R_ACMPHS3_BASE 0x40085300UL + #define R_ACMPHS4_BASE 0x40085400UL + #define R_ACMPHS5_BASE 0x40085500UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU_BASE 0x40081000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40054100UL + #define R_DRW_BASE 0x400E4000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_ETHERC0_BASE 0x40064100UL + #define R_ETHERC_EDMAC_BASE 0x40064000UL + #define R_PTP_EDMAC_BASE 0x40064400UL + #define R_ETHERC_EPTPC_BASE 0x40065800UL + #define R_ETHERC_EPTPC1_BASE 0x40065C00UL + #define R_ETHERC_EPTPC_CFG_BASE 0x40064500UL + #define R_ETHERC_EPTPC_COMMON_BASE 0x40065000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GLCDC_BASE 0x400E0000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_ODC_BASE 0x4007B000UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IRDA_BASE 0x40070F00UL + #define R_IWDT_BASE 0x40044400UL + #define R_JPEG_BASE 0x400E6000UL + #define R_KINT_BASE 0x40080000UL + #define R_MMF_BASE 0x40001000UL + #define R_MPU_MMPU_BASE 0x40000000UL + #define R_MPU_SMPU_BASE 0x40000C00UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PDC_BASE 0x40094000UL + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SDHI0_BASE 0x40062000UL + #define R_SDHI1_BASE 0x40062400UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SPI2_BASE 0x40072200UL + #define R_SRAM_BASE 0x40002000UL + #define R_SRC_BASE 0x40048000UL + #define R_SSI0_BASE 0x4004E000UL + #define R_SSI1_BASE 0x4004E100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x4005D000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40044200UL + #define R_USB_HS0_BASE 0x40060000UL + #define R_AGTX0_BASE 0x40084000UL + #define R_AGTX1_BASE 0x40084100UL + #define R_AGTX2_BASE 0x40084200UL + #define R_AGTX3_BASE 0x40084300UL + #define R_AGTX4_BASE 0x40084400UL + #define R_AGTX5_BASE 0x40084500UL + #define R_AGTX6_BASE 0x40084600UL + #define R_AGTX7_BASE 0x40084700UL + #define R_AGTX8_BASE 0x40084800UL + #define R_AGTX9_BASE 0x40084900UL + #define R_WDT1_BASE 0x40044300UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_PTP_EDMAC ((R_ETHERC_EDMAC_Type *) R_PTP_EDMAC_BASE) + #define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE) + #define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC1_BASE) + #define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE) + #define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PDC ((R_PDC_Type *) R_PDC_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SRC ((R_SRC_Type *) R_SRC_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ TM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STTRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Pos (0UL) /*!< TMSTTRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Msk (0xffffffffUL) /*!< TMSTTRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STTRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Pos (0UL) /*!< TMSTTRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Msk (0xffffffffUL) /*!< TMSTTRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CYCR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Pos (0UL) /*!< TMCYCR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Msk (0x3fffffffUL) /*!< TMCYCR (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= PLSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Pos (0UL) /*!< TMPLSR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Msk (0x1fffffffUL) /*!< TMPLSR (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ PR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MACRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Pos (0UL) /*!< PRMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Msk (0xffffffUL) /*!< PRMACRU (Bitfield-Mask: 0xffffff) */ +/* ========================================================= MACRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Pos (0UL) /*!< PRMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Msk (0xffffffUL) /*!< PRMACRL (Bitfield-Mask: 0xffffff) */ + +/* =========================================================================================================================== */ +/* ================ BG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= PERI ========================================================== */ + #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */ + #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */ + #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SYNC ========================================================== */ + #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */ + #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */ + #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */ +/* ========================================================= VSIZE ========================================================= */ + #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= HSIZE ========================================================= */ + #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== BGC ========================================================== */ + #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== VEN ========================================================== */ + #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */ + #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FLMRD ========================================================= */ + #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */ + #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */ +/* ========================================================= FLM1 ========================================================== */ + #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */ + #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */ +/* ========================================================= FLM2 ========================================================== */ + #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ + #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLM3 ========================================================== */ + #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */ + #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM5 ========================================================== */ + #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */ + #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */ + #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM6 ========================================================== */ + #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */ + #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */ +/* ========================================================== AB1 ========================================================== */ + #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */ + #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */ + #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== AB2 ========================================================== */ + #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */ + #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */ + #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB3 ========================================================== */ + #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */ + #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */ + #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB4 ========================================================== */ + #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */ + #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */ + #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB5 ========================================================== */ + #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */ + #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */ + #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB6 ========================================================== */ + #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */ + #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */ + #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */ + #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */ +/* ========================================================== AB7 ========================================================== */ + #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */ + #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */ + #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */ +/* ========================================================== AB8 ========================================================== */ + #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */ + #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */ + #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */ + #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */ +/* ========================================================== AB9 ========================================================== */ + #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */ + #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */ + #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */ + #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */ + #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */ +/* ========================================================= BASE ========================================================== */ + #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */ + #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */ + #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */ +/* ======================================================== CLUTINT ======================================================== */ + #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */ + #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */ + #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */ + #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */ + #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LATCH ========================================================= */ + #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ======================================================== GAM_SW ========================================================= */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */ +/* ========================================================== LUT ========================================================== */ + #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */ +/* ========================================================= AREA ========================================================== */ + #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ OUT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VLATCH ========================================================= */ + #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */ + #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */ + #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */ + #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */ + #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */ + #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */ + #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +/* ======================================================== BRIGHT1 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BRIGHT2 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CONTRAST ======================================================== */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */ +/* ========================================================= PDTHA ========================================================= */ + #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */ + #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */ + #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */ + #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */ + #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */ + #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */ + #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */ +/* ======================================================= CLKPHASE ======================================================== */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TCON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TIM ========================================================== */ + #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */ + #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA1 ========================================================= */ + #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVB1 ========================================================= */ + #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA2 ========================================================= */ + #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STVB2 ========================================================= */ + #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHA1 ========================================================= */ + #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHB1 ========================================================= */ + #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHA2 ========================================================= */ + #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHB2 ========================================================= */ + #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================== DE =========================================================== */ + #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */ + #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSCNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DTCTEN ========================================================= */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCLR ========================================================= */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= STMON ========================================================= */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */ +/* ======================================================= PANEL_CLK ======================================================= */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ + #define R_MPU_MMPU_MMPU_CTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_MMPU_CTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_MMPU_CTL_OAD_Pos (1UL) /*!< OAD (Bit 1) */ + #define R_MPU_MMPU_MMPU_CTL_OAD_Msk (0x2UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_MMPU_MMPU_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_MMPU_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SMPU ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== R =========================================================== */ + #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos (15UL) /*!< WPSRAMHS (Bit 15) */ + #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos (14UL) /*!< RPSRAMHS (Bit 14) */ + #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPFLI_Pos (13UL) /*!< WPFLI (Bit 13) */ + #define R_MPU_SMPU_SMPU_R_WPFLI_Msk (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPFLI_Pos (12UL) /*!< RPFLI (Bit 12) */ + #define R_MPU_SMPU_SMPU_R_RPFLI_Msk (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos (7UL) /*!< WPGRPC (Bit 7) */ + #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk (0x80UL) /*!< WPGRPC (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos (6UL) /*!< RPGRPC (Bit 6) */ + #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk (0x40UL) /*!< RPGRPC (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos (5UL) /*!< WPGRPB (Bit 5) */ + #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk (0x20UL) /*!< WPGRPB (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos (4UL) /*!< RPGRPB (Bit 4) */ + #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk (0x10UL) /*!< RPGRPB (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos (3UL) /*!< WPGRPA (Bit 3) */ + #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk (0x8UL) /*!< WPGRPA (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos (2UL) /*!< RPGRPA (Bit 2) */ + #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk (0x4UL) /*!< RPGRPA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONTROL ======================================================== */ + #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */ + #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */ + #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */ + #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */ + #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */ + #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */ + #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */ + #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */ + #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */ + #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */ + #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */ + #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */ + #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */ + #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */ + #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */ + #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */ + #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */ + #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */ + #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */ + #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */ + #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */ + #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */ + #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */ + #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */ + #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */ + #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */ + #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */ + #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */ + #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */ + #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */ + #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCTL ========================================================= */ + #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */ + #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */ + #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CACHECTL ======================================================== */ + #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */ + #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */ + #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */ + #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */ + #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */ + #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */ + #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */ + #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */ + #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */ + #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */ + #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */ + #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */ + #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */ + #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */ +/* ====================================================== HWREVISION ======================================================= */ + #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */ + #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */ + #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */ + #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */ + #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */ + #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */ + #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */ + #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */ + #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */ + #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */ +/* ======================================================== COLOR1 ========================================================= */ + #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */ + #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */ + #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */ + #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */ + #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */ +/* ======================================================== COLOR2 ========================================================= */ + #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */ + #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */ + #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */ + #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */ + #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */ +/* ======================================================== PATTERN ======================================================== */ + #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */ + #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */ +/* ======================================================== L1START ======================================================== */ + #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2START ======================================================== */ + #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3START ======================================================== */ + #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4START ======================================================== */ + #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5START ======================================================== */ + #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6START ======================================================== */ + #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1XADD ========================================================= */ + #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2XADD ========================================================= */ + #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3XADD ========================================================= */ + #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4XADD ========================================================= */ + #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5XADD ========================================================= */ + #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6XADD ========================================================= */ + #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1YADD ========================================================= */ + #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2YADD ========================================================= */ + #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3YADD ========================================================= */ + #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4YADD ========================================================= */ + #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5YADD ========================================================= */ + #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6YADD ========================================================= */ + #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1BAND ========================================================= */ + #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2BAND ========================================================= */ + #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXORIGIN ======================================================= */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXPITCH ======================================================== */ + #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */ + #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TEXMASK ======================================================== */ + #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */ + #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */ + #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */ + #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */ +/* ======================================================== LUSTART ======================================================== */ + #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */ + #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUXADD ========================================================= */ + #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */ + #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUYADD ========================================================= */ + #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */ + #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTI ======================================================== */ + #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */ + #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTF ======================================================== */ + #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */ + #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */ +/* ======================================================== LVXADDI ======================================================== */ + #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */ + #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LVYADDI ======================================================== */ + #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */ + #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVYXADDF ======================================================== */ + #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */ + #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */ + #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */ + #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */ +/* ======================================================= TEXCLADDR ======================================================= */ + #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */ + #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */ +/* ======================================================= TEXCLDATA ======================================================= */ + #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */ + #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TEXCLOFFSET ====================================================== */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== COLKEY ========================================================= */ + #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */ + #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */ + #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */ + #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */ +/* ========================================================= SIZE ========================================================== */ + #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */ + #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */ + #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */ + #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */ +/* ========================================================= PITCH ========================================================= */ + #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */ + #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */ + #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */ + #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */ +/* ======================================================== ORIGIN ========================================================= */ + #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */ + #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLISTSTART ======================================================= */ + #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */ + #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFTRIGGER ====================================================== */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== PERFCOUNT1 ======================================================= */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFCOUNT2 ======================================================= */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBWER ========================================================= */ + #define R_DRW_DBWER_BWE_Pos (2UL) /*!< BWE (Bit 2) */ + #define R_DRW_DBWER_BWE_Msk (0x4UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SYSR ========================================================== */ + #define R_ETHERC_EPTPC_SYSR_GENDN_Pos (17UL) /*!< GENDN (Bit 17) */ + #define R_ETHERC_EPTPC_SYSR_GENDN_Msk (0x20000UL) /*!< GENDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_RESDN_Pos (16UL) /*!< RESDN (Bit 16) */ + #define R_ETHERC_EPTPC_SYSR_RESDN_Msk (0x10000UL) /*!< RESDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INFABT_Pos (14UL) /*!< INFABT (Bit 14) */ + #define R_ETHERC_EPTPC_SYSR_INFABT_Msk (0x4000UL) /*!< INFABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_RECLP_Pos (12UL) /*!< RECLP (Bit 12) */ + #define R_ETHERC_EPTPC_SYSR_RECLP_Msk (0x1000UL) /*!< RECLP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_DRQOVR_Pos (6UL) /*!< DRQOVR (Bit 6) */ + #define R_ETHERC_EPTPC_SYSR_DRQOVR_Msk (0x40UL) /*!< DRQOVR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INTDEV_Pos (5UL) /*!< INTDEV (Bit 5) */ + #define R_ETHERC_EPTPC_SYSR_INTDEV_Msk (0x20UL) /*!< INTDEV (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_DRPTO_Pos (4UL) /*!< DRPTO (Bit 4) */ + #define R_ETHERC_EPTPC_SYSR_DRPTO_Msk (0x10UL) /*!< DRPTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_MPDUD_Pos (2UL) /*!< MPDUD (Bit 2) */ + #define R_ETHERC_EPTPC_SYSR_MPDUD_Msk (0x4UL) /*!< MPDUD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INTCHG_Pos (1UL) /*!< INTCHG (Bit 1) */ + #define R_ETHERC_EPTPC_SYSR_INTCHG_Msk (0x2UL) /*!< INTCHG (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_OFMUD_Pos (0UL) /*!< OFMUD (Bit 0) */ + #define R_ETHERC_EPTPC_SYSR_OFMUD_Msk (0x1UL) /*!< OFMUD (Bitfield-Mask: 0x01) */ +/* ========================================================= SYIPR ========================================================= */ + #define R_ETHERC_EPTPC_SYIPR_GENDN_Pos (17UL) /*!< GENDN (Bit 17) */ + #define R_ETHERC_EPTPC_SYIPR_GENDN_Msk (0x20000UL) /*!< GENDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_RESDN_Pos (16UL) /*!< RESDN (Bit 16) */ + #define R_ETHERC_EPTPC_SYIPR_RESDN_Msk (0x10000UL) /*!< RESDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INFABT_Pos (14UL) /*!< INFABT (Bit 14) */ + #define R_ETHERC_EPTPC_SYIPR_INFABT_Msk (0x4000UL) /*!< INFABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_RECLP_Pos (12UL) /*!< RECLP (Bit 12) */ + #define R_ETHERC_EPTPC_SYIPR_RECLP_Msk (0x1000UL) /*!< RECLP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Pos (6UL) /*!< DRQOVR (Bit 6) */ + #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Msk (0x40UL) /*!< DRQOVR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INTDEV_Pos (5UL) /*!< INTDEV (Bit 5) */ + #define R_ETHERC_EPTPC_SYIPR_INTDEV_Msk (0x20UL) /*!< INTDEV (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_DRPTO_Pos (4UL) /*!< DRPTO (Bit 4) */ + #define R_ETHERC_EPTPC_SYIPR_DRPTO_Msk (0x10UL) /*!< DRPTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_MPDUD_Pos (2UL) /*!< MPDUD (Bit 2) */ + #define R_ETHERC_EPTPC_SYIPR_MPDUD_Msk (0x4UL) /*!< MPDUD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INTCHG_Pos (1UL) /*!< INTCHG (Bit 1) */ + #define R_ETHERC_EPTPC_SYIPR_INTCHG_Msk (0x2UL) /*!< INTCHG (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_OFMUD_Pos (0UL) /*!< OFMUD (Bit 0) */ + #define R_ETHERC_EPTPC_SYIPR_OFMUD_Msk (0x1UL) /*!< OFMUD (Bitfield-Mask: 0x01) */ +/* ======================================================== SYMACRU ======================================================== */ + #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Pos (0UL) /*!< SYMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Msk (0xffffffUL) /*!< SYMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SYMACRL ======================================================== */ + #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Pos (0UL) /*!< SYMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Msk (0xffffffUL) /*!< SYMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================= SYLLCCTLR ======================================================= */ + #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Pos (0UL) /*!< CTL (Bit 0) */ + #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Msk (0xffUL) /*!< CTL (Bitfield-Mask: 0xff) */ +/* ======================================================= SYIPADDRR ======================================================= */ + #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Pos (0UL) /*!< SYIPADDRR (Bit 0) */ + #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Msk (0xffffffffUL) /*!< SYIPADDRR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYSPVRR ======================================================== */ + #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Pos (4UL) /*!< TRSP (Bit 4) */ + #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Msk (0xf0UL) /*!< TRSP (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_SYSPVRR_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_ETHERC_EPTPC_SYSPVRR_VER_Msk (0xfUL) /*!< VER (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYDOMR ========================================================= */ + #define R_ETHERC_EPTPC_SYDOMR_DNUM_Pos (0UL) /*!< DNUM (Bit 0) */ + #define R_ETHERC_EPTPC_SYDOMR_DNUM_Msk (0xffUL) /*!< DNUM (Bitfield-Mask: 0xff) */ +/* ========================================================= ANFR ========================================================== */ + #define R_ETHERC_EPTPC_ANFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_ANFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_ANFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_ANFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_ANFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG5_Pos (5UL) /*!< FLAG5 (Bit 5) */ + #define R_ETHERC_EPTPC_ANFR_FLAG5_Msk (0x20UL) /*!< FLAG5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG4_Pos (4UL) /*!< FLAG4 (Bit 4) */ + #define R_ETHERC_EPTPC_ANFR_FLAG4_Msk (0x10UL) /*!< FLAG4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG3_Pos (3UL) /*!< FLAG3 (Bit 3) */ + #define R_ETHERC_EPTPC_ANFR_FLAG3_Msk (0x8UL) /*!< FLAG3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG2_Pos (2UL) /*!< FLAG2 (Bit 2) */ + #define R_ETHERC_EPTPC_ANFR_FLAG2_Msk (0x4UL) /*!< FLAG2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG1_Pos (1UL) /*!< FLAG1 (Bit 1) */ + #define R_ETHERC_EPTPC_ANFR_FLAG1_Msk (0x2UL) /*!< FLAG1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG0_Pos (0UL) /*!< FLAG0 (Bit 0) */ + #define R_ETHERC_EPTPC_ANFR_FLAG0_Msk (0x1UL) /*!< FLAG0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SYNFR ========================================================= */ + #define R_ETHERC_EPTPC_SYNFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG9_Pos (9UL) /*!< FLAG9 (Bit 9) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG9_Msk (0x200UL) /*!< FLAG9 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ +/* ======================================================== DYRQFR ========================================================= */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ +/* ======================================================== DYRPFR ========================================================= */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Pos (9UL) /*!< FLAG9 (Bit 9) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Msk (0x200UL) /*!< FLAG9 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYCIDRU ======================================================== */ + #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Pos (0UL) /*!< SYCIDRU (Bit 0) */ + #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Msk (0xffffffffUL) /*!< SYCIDRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYCIDRL ======================================================== */ + #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Pos (0UL) /*!< SYCIDRL (Bit 0) */ + #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Msk (0xffffffffUL) /*!< SYCIDRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYPNUMR ======================================================== */ + #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Pos (0UL) /*!< PNUM (Bit 0) */ + #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Msk (0xffffUL) /*!< PNUM (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYRVLDR ======================================================== */ + #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Pos (2UL) /*!< ANUP (Bit 2) */ + #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk (0x4UL) /*!< ANUP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRVLDR_STUP_Pos (1UL) /*!< STUP (Bit 1) */ + #define R_ETHERC_EPTPC_SYRVLDR_STUP_Msk (0x2UL) /*!< STUP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Pos (0UL) /*!< BMUP (Bit 0) */ + #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk (0x1UL) /*!< BMUP (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRFL1R ======================================================== */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Pos (30UL) /*!< PDFUP2 (Bit 30) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Msk (0x40000000UL) /*!< PDFUP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Pos (29UL) /*!< PDFUP1 (Bit 29) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Msk (0x20000000UL) /*!< PDFUP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Pos (28UL) /*!< PDFUP0 (Bit 28) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Msk (0x10000000UL) /*!< PDFUP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Pos (26UL) /*!< PDRP2 (Bit 26) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Msk (0x4000000UL) /*!< PDRP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Pos (25UL) /*!< PDRP1 (Bit 25) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Msk (0x2000000UL) /*!< PDRP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Pos (24UL) /*!< PDRP0 (Bit 24) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Msk (0x1000000UL) /*!< PDRP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Pos (22UL) /*!< PDRQ2 (Bit 22) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Msk (0x400000UL) /*!< PDRQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Pos (21UL) /*!< PDRQ1 (Bit 21) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Msk (0x200000UL) /*!< PDRQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Pos (20UL) /*!< PDRQ0 (Bit 20) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Msk (0x100000UL) /*!< PDRQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Pos (18UL) /*!< DRP2 (Bit 18) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Msk (0x40000UL) /*!< DRP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Pos (17UL) /*!< DRP1 (Bit 17) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Msk (0x20000UL) /*!< DRP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Pos (16UL) /*!< DRP0 (Bit 16) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Msk (0x10000UL) /*!< DRP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Pos (14UL) /*!< DRQ2 (Bit 14) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Msk (0x4000UL) /*!< DRQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Pos (13UL) /*!< DRQ1 (Bit 13) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Msk (0x2000UL) /*!< DRQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Pos (12UL) /*!< DRQ0 (Bit 12) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Msk (0x1000UL) /*!< DRQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Pos (10UL) /*!< FUP2 (Bit 10) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Msk (0x400UL) /*!< FUP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Pos (9UL) /*!< FUP1 (Bit 9) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Msk (0x200UL) /*!< FUP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Pos (8UL) /*!< FUP0 (Bit 8) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Msk (0x100UL) /*!< FUP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Pos (6UL) /*!< SYNC2 (Bit 6) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Msk (0x40UL) /*!< SYNC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Pos (5UL) /*!< SYNC1 (Bit 5) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Msk (0x20UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Pos (4UL) /*!< SYNC0 (Bit 4) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Msk (0x10UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Pos (1UL) /*!< ANCE1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Msk (0x2UL) /*!< ANCE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Pos (0UL) /*!< ANCE0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Msk (0x1UL) /*!< ANCE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRFL2R ======================================================== */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Pos (29UL) /*!< ILL1 (Bit 29) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Msk (0x20000000UL) /*!< ILL1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Pos (28UL) /*!< ILL0 (Bit 28) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Msk (0x10000000UL) /*!< ILL0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Pos (5UL) /*!< SIG1 (Bit 5) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Msk (0x20UL) /*!< SIG1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Pos (4UL) /*!< SIG0 (Bit 4) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Msk (0x10UL) /*!< SIG0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Pos (1UL) /*!< MAN1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Msk (0x2UL) /*!< MAN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Pos (0UL) /*!< MAN0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Msk (0x1UL) /*!< MAN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYTRENR ======================================================== */ + #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Pos (12UL) /*!< PDRQ (Bit 12) */ + #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Msk (0x1000UL) /*!< PDRQ (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_DRQ_Pos (8UL) /*!< DRQ (Bit 8) */ + #define R_ETHERC_EPTPC_SYTRENR_DRQ_Msk (0x100UL) /*!< DRQ (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_SYNC_Pos (4UL) /*!< SYNC (Bit 4) */ + #define R_ETHERC_EPTPC_SYTRENR_SYNC_Msk (0x10UL) /*!< SYNC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYTRENR_ANCE_Msk (0x1UL) /*!< ANCE (Bitfield-Mask: 0x01) */ +/* ======================================================== MTCIDU ========================================================= */ + #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Pos (0UL) /*!< MTCIDU (Bit 0) */ + #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Msk (0xffffffffUL) /*!< MTCIDU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTCIDL ========================================================= */ + #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Pos (0UL) /*!< MTCIDL (Bit 0) */ + #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Msk (0xffffffffUL) /*!< MTCIDL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTPID ========================================================= */ + #define R_ETHERC_EPTPC_MTPID_PNUM_Pos (0UL) /*!< PNUM (Bit 0) */ + #define R_ETHERC_EPTPC_MTPID_PNUM_Msk (0xffffUL) /*!< PNUM (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYTLIR ========================================================= */ + #define R_ETHERC_EPTPC_SYTLIR_DREQ_Pos (16UL) /*!< DREQ (Bit 16) */ + #define R_ETHERC_EPTPC_SYTLIR_DREQ_Msk (0xff0000UL) /*!< DREQ (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYTLIR_SYNC_Pos (8UL) /*!< SYNC (Bit 8) */ + #define R_ETHERC_EPTPC_SYTLIR_SYNC_Msk (0xff00UL) /*!< SYNC (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYTLIR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYTLIR_ANCE_Msk (0xffUL) /*!< ANCE (Bitfield-Mask: 0xff) */ +/* ======================================================== SYRLIR ========================================================= */ + #define R_ETHERC_EPTPC_SYRLIR_DRESP_Pos (16UL) /*!< DRESP (Bit 16) */ + #define R_ETHERC_EPTPC_SYRLIR_DRESP_Msk (0xff0000UL) /*!< DRESP (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYRLIR_SYNC_Pos (8UL) /*!< SYNC (Bit 8) */ + #define R_ETHERC_EPTPC_SYRLIR_SYNC_Msk (0xff00UL) /*!< SYNC (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYRLIR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYRLIR_ANCE_Msk (0xffUL) /*!< ANCE (Bitfield-Mask: 0xff) */ +/* ========================================================= OFMRU ========================================================= */ + #define R_ETHERC_EPTPC_OFMRU_OFMRU_Pos (0UL) /*!< OFMRU (Bit 0) */ + #define R_ETHERC_EPTPC_OFMRU_OFMRU_Msk (0xffffffffUL) /*!< OFMRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= OFMRL ========================================================= */ + #define R_ETHERC_EPTPC_OFMRL_OFMRL_Pos (0UL) /*!< OFMRL (Bit 0) */ + #define R_ETHERC_EPTPC_OFMRL_OFMRL_Msk (0xffffffffUL) /*!< OFMRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MPDRU ========================================================= */ + #define R_ETHERC_EPTPC_MPDRU_MPDRU_Pos (0UL) /*!< MPDRU (Bit 0) */ + #define R_ETHERC_EPTPC_MPDRU_MPDRU_Msk (0xffffffffUL) /*!< MPDRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MPDRL ========================================================= */ + #define R_ETHERC_EPTPC_MPDRL_MPDRL_Pos (0UL) /*!< MPDRL (Bit 0) */ + #define R_ETHERC_EPTPC_MPDRL_MPDRL_Msk (0xffffffffUL) /*!< MPDRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GMPR ========================================================== */ + #define R_ETHERC_EPTPC_GMPR_GMPR1_Pos (16UL) /*!< GMPR1 (Bit 16) */ + #define R_ETHERC_EPTPC_GMPR_GMPR1_Msk (0xff0000UL) /*!< GMPR1 (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_GMPR_GMPR2_Pos (0UL) /*!< GMPR2 (Bit 0) */ + #define R_ETHERC_EPTPC_GMPR_GMPR2_Msk (0xffUL) /*!< GMPR2 (Bitfield-Mask: 0xff) */ +/* ========================================================= GMCQR ========================================================= */ + #define R_ETHERC_EPTPC_GMCQR_GMCQR_Pos (0UL) /*!< GMCQR (Bit 0) */ + #define R_ETHERC_EPTPC_GMCQR_GMCQR_Msk (0xffffffffUL) /*!< GMCQR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GMIDRU ========================================================= */ + #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Pos (0UL) /*!< GMIDRU (Bit 0) */ + #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Msk (0xffffffffUL) /*!< GMIDRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GMIDRL ========================================================= */ + #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Pos (0UL) /*!< GMIDRL (Bit 0) */ + #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Msk (0xffffffffUL) /*!< GMIDRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CUOTSR ========================================================= */ + #define R_ETHERC_EPTPC_CUOTSR_CUTO_Pos (16UL) /*!< CUTO (Bit 16) */ + #define R_ETHERC_EPTPC_CUOTSR_CUTO_Msk (0xffff0000UL) /*!< CUTO (Bitfield-Mask: 0xffff) */ + #define R_ETHERC_EPTPC_CUOTSR_TSRC_Pos (0UL) /*!< TSRC (Bit 0) */ + #define R_ETHERC_EPTPC_CUOTSR_TSRC_Msk (0xffUL) /*!< TSRC (Bitfield-Mask: 0xff) */ +/* ========================================================== SRR ========================================================== */ + #define R_ETHERC_EPTPC_SRR_SRMV_Pos (0UL) /*!< SRMV (Bit 0) */ + #define R_ETHERC_EPTPC_SRR_SRMV_Msk (0xffffUL) /*!< SRMV (Bitfield-Mask: 0xffff) */ +/* ======================================================== PPMACRU ======================================================== */ + #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Pos (0UL) /*!< PPMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Msk (0xffffffUL) /*!< PPMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PPMACRL ======================================================== */ + #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Pos (0UL) /*!< PPMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Msk (0xffffffUL) /*!< PPMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PDMACRU ======================================================== */ + #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Pos (0UL) /*!< PDMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Msk (0xffffffUL) /*!< PDMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PDMACRL ======================================================== */ + #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Pos (0UL) /*!< PDMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Msk (0xffffffUL) /*!< PDMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PETYPER ======================================================== */ + #define R_ETHERC_EPTPC_PETYPER_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ + #define R_ETHERC_EPTPC_PETYPER_TYPE_Msk (0xffffUL) /*!< TYPE (Bitfield-Mask: 0xffff) */ +/* ========================================================= PPIPR ========================================================= */ + #define R_ETHERC_EPTPC_PPIPR_PPIPR_Pos (0UL) /*!< PPIPR (Bit 0) */ + #define R_ETHERC_EPTPC_PPIPR_PPIPR_Msk (0xffffffffUL) /*!< PPIPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PDIPR ========================================================= */ + #define R_ETHERC_EPTPC_PDIPR_PDIPR_Pos (0UL) /*!< PDIPR (Bit 0) */ + #define R_ETHERC_EPTPC_PDIPR_PDIPR_Msk (0xffffffffUL) /*!< PDIPR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PETOSR ========================================================= */ + #define R_ETHERC_EPTPC_PETOSR_EVTO_Pos (0UL) /*!< EVTO (Bit 0) */ + #define R_ETHERC_EPTPC_PETOSR_EVTO_Msk (0xffUL) /*!< EVTO (Bitfield-Mask: 0xff) */ +/* ======================================================== PGTOSR ========================================================= */ + #define R_ETHERC_EPTPC_PGTOSR_GETO_Pos (0UL) /*!< GETO (Bit 0) */ + #define R_ETHERC_EPTPC_PGTOSR_GETO_Msk (0xffUL) /*!< GETO (Bitfield-Mask: 0xff) */ +/* ======================================================== PPTTLR ========================================================= */ + #define R_ETHERC_EPTPC_PPTTLR_PRTL_Pos (0UL) /*!< PRTL (Bit 0) */ + #define R_ETHERC_EPTPC_PPTTLR_PRTL_Msk (0xffUL) /*!< PRTL (Bitfield-Mask: 0xff) */ +/* ======================================================== PDTTLR ========================================================= */ + #define R_ETHERC_EPTPC_PDTTLR_PDTL_Pos (0UL) /*!< PDTL (Bit 0) */ + #define R_ETHERC_EPTPC_PDTTLR_PDTL_Msk (0xffUL) /*!< PDTL (Bitfield-Mask: 0xff) */ +/* ======================================================== PEUDPR ========================================================= */ + #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Pos (0UL) /*!< EVUPT (Bit 0) */ + #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Msk (0xffffUL) /*!< EVUPT (Bitfield-Mask: 0xffff) */ +/* ======================================================== PGUDPR ========================================================= */ + #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Pos (0UL) /*!< GEUPT (Bit 0) */ + #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Msk (0xffffUL) /*!< GEUPT (Bitfield-Mask: 0xffff) */ +/* ========================================================= FFLTR ========================================================= */ + #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Pos (16UL) /*!< EXTPRM (Bit 16) */ + #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Msk (0x10000UL) /*!< EXTPRM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_ENB_Pos (2UL) /*!< ENB (Bit 2) */ + #define R_ETHERC_EPTPC_FFLTR_ENB_Msk (0x4UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_PRT_Pos (1UL) /*!< PRT (Bit 1) */ + #define R_ETHERC_EPTPC_FFLTR_PRT_Msk (0x2UL) /*!< PRT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_ETHERC_EPTPC_FFLTR_SEL_Msk (0x1UL) /*!< SEL (Bitfield-Mask: 0x01) */ +/* ======================================================== FMAC0RU ======================================================== */ + #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Pos (0UL) /*!< FMAC0RU (Bit 0) */ + #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Msk (0xffffffUL) /*!< FMAC0RU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FMAC0RL ======================================================== */ + #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Pos (0UL) /*!< FMAC0RL (Bit 0) */ + #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Msk (0xffffffUL) /*!< FMAC0RL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FMAC1RU ======================================================== */ + #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Pos (0UL) /*!< FMAC1RU (Bit 0) */ + #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Msk (0xffffffUL) /*!< FMAC1RU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FMAC1RL ======================================================== */ + #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Pos (0UL) /*!< FMAC1RL (Bit 0) */ + #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Msk (0xffffffUL) /*!< FMAC1RL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== DASYMRU ======================================================== */ + #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Pos (0UL) /*!< DASYMRU (Bit 0) */ + #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Msk (0xffffUL) /*!< DASYMRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== DASYMRL ======================================================== */ + #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Pos (0UL) /*!< DASYMRL (Bit 0) */ + #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Msk (0xffffffffUL) /*!< DASYMRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSLATR ========================================================= */ + #define R_ETHERC_EPTPC_TSLATR_INGP_Pos (16UL) /*!< INGP (Bit 16) */ + #define R_ETHERC_EPTPC_TSLATR_INGP_Msk (0xffff0000UL) /*!< INGP (Bitfield-Mask: 0xffff) */ + #define R_ETHERC_EPTPC_TSLATR_EGP_Pos (0UL) /*!< EGP (Bit 0) */ + #define R_ETHERC_EPTPC_TSLATR_EGP_Msk (0xffffUL) /*!< EGP (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYCONFR ======================================================== */ + #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Pos (20UL) /*!< TCMOD (Bit 20) */ + #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Msk (0x100000UL) /*!< TCMOD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Pos (16UL) /*!< FILDIS (Bit 16) */ + #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Msk (0x10000UL) /*!< FILDIS (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Pos (12UL) /*!< SBDIS (Bit 12) */ + #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Msk (0x1000UL) /*!< SBDIS (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_TCYC_Pos (0UL) /*!< TCYC (Bit 0) */ + #define R_ETHERC_EPTPC_SYCONFR_TCYC_Msk (0xffUL) /*!< TCYC (Bitfield-Mask: 0xff) */ +/* ======================================================== SYFORMR ======================================================== */ + #define R_ETHERC_EPTPC_SYFORMR_FORM1_Pos (1UL) /*!< FORM1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM1_Msk (0x2UL) /*!< FORM1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM0_Pos (0UL) /*!< FORM0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM0_Msk (0x1UL) /*!< FORM0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTOUTR ======================================================== */ + #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Pos (0UL) /*!< RSTOUTR (Bit 0) */ + #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Msk (0xffffffffUL) /*!< RSTOUTR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_CFG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PTRSTR ========================================================= */ + #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Pos (0UL) /*!< RESET (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Msk (0x1UL) /*!< RESET (Bitfield-Mask: 0x01) */ +/* ======================================================== STCSELR ======================================================== */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Pos (8UL) /*!< SCLKSEL (Bit 8) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Msk (0x700UL) /*!< SCLKSEL (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Pos (0UL) /*!< SCLKDIV (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Msk (0x7UL) /*!< SCLKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== BYPASS ========================================================= */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Pos (16UL) /*!< BYPASS1 (Bit 16) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Msk (0x10000UL) /*!< BYPASS1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Pos (0UL) /*!< BYPASS0 (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Msk (0x1UL) /*!< BYPASS0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MIESR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Pos (21UL) /*!< CYC5 (Bit 21) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Msk (0x200000UL) /*!< CYC5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Pos (20UL) /*!< CYC4 (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Msk (0x100000UL) /*!< CYC4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Pos (19UL) /*!< CYC3 (Bit 19) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Msk (0x80000UL) /*!< CYC3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Pos (18UL) /*!< CYC2 (Bit 18) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Msk (0x40000UL) /*!< CYC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Pos (17UL) /*!< CYC1 (Bit 17) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Msk (0x20000UL) /*!< CYC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Pos (16UL) /*!< CYC0 (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Msk (0x10000UL) /*!< CYC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Pos (3UL) /*!< PRC (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Msk (0x8UL) /*!< PRC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Pos (2UL) /*!< SY1 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Msk (0x4UL) /*!< SY1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Pos (1UL) /*!< SY0 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Msk (0x2UL) /*!< SY0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Pos (0UL) /*!< ST (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Msk (0x1UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ======================================================== MIEIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Pos (21UL) /*!< CYC5 (Bit 21) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Msk (0x200000UL) /*!< CYC5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Pos (20UL) /*!< CYC4 (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Msk (0x100000UL) /*!< CYC4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Pos (19UL) /*!< CYC3 (Bit 19) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Msk (0x80000UL) /*!< CYC3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Pos (18UL) /*!< CYC2 (Bit 18) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Msk (0x40000UL) /*!< CYC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Pos (17UL) /*!< CYC1 (Bit 17) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Msk (0x20000UL) /*!< CYC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos (16UL) /*!< CYC0 (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Msk (0x10000UL) /*!< CYC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Pos (3UL) /*!< PRC (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Msk (0x8UL) /*!< PRC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Pos (2UL) /*!< SY1 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Msk (0x4UL) /*!< SY1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Pos (1UL) /*!< SY0 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Msk (0x2UL) /*!< SY0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Pos (0UL) /*!< ST (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Msk (0x1UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ======================================================== ELIPPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Pos (24UL) /*!< PLSN (Bit 24) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Msk (0x1000000UL) /*!< PLSN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Pos (16UL) /*!< PLSP (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Msk (0x10000UL) /*!< PLSP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Pos (13UL) /*!< CYCN5 (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Msk (0x2000UL) /*!< CYCN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Pos (12UL) /*!< CYCN4 (Bit 12) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Msk (0x1000UL) /*!< CYCN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Pos (11UL) /*!< CYCN3 (Bit 11) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Msk (0x800UL) /*!< CYCN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Pos (10UL) /*!< CYCN2 (Bit 10) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Msk (0x400UL) /*!< CYCN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Pos (9UL) /*!< CYCN1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Msk (0x200UL) /*!< CYCN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos (8UL) /*!< CYCN0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Msk (0x100UL) /*!< CYCN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Pos (5UL) /*!< CYCP5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Msk (0x20UL) /*!< CYCP5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Pos (4UL) /*!< CYCP4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Msk (0x10UL) /*!< CYCP4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Pos (3UL) /*!< CYCP3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Msk (0x8UL) /*!< CYCP3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Pos (2UL) /*!< CYCP2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Msk (0x4UL) /*!< CYCP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Pos (1UL) /*!< CYCP1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Msk (0x2UL) /*!< CYCP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Pos (0UL) /*!< CYCP0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Msk (0x1UL) /*!< CYCP0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELIPACR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Pos (24UL) /*!< PLSN (Bit 24) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Msk (0x1000000UL) /*!< PLSN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Pos (16UL) /*!< PLSP (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Msk (0x10000UL) /*!< PLSP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Pos (13UL) /*!< CYCN5 (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Msk (0x2000UL) /*!< CYCN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Pos (12UL) /*!< CYCN4 (Bit 12) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Msk (0x1000UL) /*!< CYCN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Pos (11UL) /*!< CYCN3 (Bit 11) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Msk (0x800UL) /*!< CYCN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Pos (10UL) /*!< CYCN2 (Bit 10) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Msk (0x400UL) /*!< CYCN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Pos (9UL) /*!< CYCN1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Msk (0x200UL) /*!< CYCN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos (8UL) /*!< CYCN0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Msk (0x100UL) /*!< CYCN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Pos (5UL) /*!< CYCP5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Msk (0x20UL) /*!< CYCP5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Pos (4UL) /*!< CYCP4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Msk (0x10UL) /*!< CYCP4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Pos (3UL) /*!< CYCP3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Msk (0x8UL) /*!< CYCP3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Pos (2UL) /*!< CYCP2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Msk (0x4UL) /*!< CYCP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Pos (1UL) /*!< CYCP1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Msk (0x2UL) /*!< CYCP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Pos (0UL) /*!< CYCP0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Msk (0x1UL) /*!< CYCP0 (Bitfield-Mask: 0x01) */ +/* ========================================================= STSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Pos (4UL) /*!< W10D (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Msk (0x10UL) /*!< W10D (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Pos (3UL) /*!< SYNTOUT (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Msk (0x8UL) /*!< SYNTOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Pos (1UL) /*!< SYNCOUT (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Msk (0x2UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Pos (0UL) /*!< SYNC (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Msk (0x1UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= STIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Pos (4UL) /*!< W10D (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Msk (0x10UL) /*!< W10D (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Pos (3UL) /*!< SYNTOUT (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Msk (0x8UL) /*!< SYNTOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Pos (1UL) /*!< SYNCOUT (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Msk (0x2UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Pos (0UL) /*!< SYNC (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Msk (0x1UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= STCFR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Pos (0UL) /*!< STCF (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Msk (0x3UL) /*!< STCF (Bitfield-Mask: 0x03) */ +/* ========================================================= STMR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Pos (29UL) /*!< ALEN1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Msk (0x20000000UL) /*!< ALEN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Pos (28UL) /*!< ALEN0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Msk (0x10000000UL) /*!< ALEN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Pos (20UL) /*!< DVTH (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Msk (0xf00000UL) /*!< DVTH (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Pos (16UL) /*!< SYTH (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Msk (0xf0000UL) /*!< SYTH (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Pos (15UL) /*!< W10S (Bit 15) */ + #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Msk (0x8000UL) /*!< W10S (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Pos (13UL) /*!< CMOD (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Msk (0x2000UL) /*!< CMOD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Pos (0UL) /*!< WINT (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Msk (0xffUL) /*!< WINT (Bitfield-Mask: 0xff) */ +/* ======================================================== SYNTOR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Pos (0UL) /*!< SYNTOR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Msk (0xffffffffUL) /*!< SYNTOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== IPTSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Pos (5UL) /*!< IPTSEL5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Msk (0x20UL) /*!< IPTSEL5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Pos (4UL) /*!< IPTSEL4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Msk (0x10UL) /*!< IPTSEL4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Pos (3UL) /*!< IPTSEL3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Msk (0x8UL) /*!< IPTSEL3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Pos (2UL) /*!< IPTSEL2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Msk (0x4UL) /*!< IPTSEL2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Pos (1UL) /*!< IPTSEL1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Msk (0x2UL) /*!< IPTSEL1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Pos (0UL) /*!< IPTSEL0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Msk (0x1UL) /*!< IPTSEL0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MITSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Pos (5UL) /*!< MINTEN5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Msk (0x20UL) /*!< MINTEN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Pos (4UL) /*!< MINTEN4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Msk (0x10UL) /*!< MINTEN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Pos (3UL) /*!< MINTEN3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Msk (0x8UL) /*!< MINTEN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Pos (2UL) /*!< MINTEN2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Msk (0x4UL) /*!< MINTEN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Pos (1UL) /*!< MINTEN1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Msk (0x2UL) /*!< MINTEN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Pos (0UL) /*!< MINTEN0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Msk (0x1UL) /*!< MINTEN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELTSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Pos (5UL) /*!< ELTDIS5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Msk (0x20UL) /*!< ELTDIS5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Pos (4UL) /*!< ELTDIS4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Msk (0x10UL) /*!< ELTDIS4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Pos (3UL) /*!< ELTDIS3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Msk (0x8UL) /*!< ELTDIS3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Pos (2UL) /*!< ELTDIS2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Msk (0x4UL) /*!< ELTDIS2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Pos (1UL) /*!< ELTDIS1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Msk (0x2UL) /*!< ELTDIS1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Pos (0UL) /*!< ELTDIS0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Msk (0x1UL) /*!< ELTDIS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= STCHSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Pos (0UL) /*!< SYSEL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Msk (0x1UL) /*!< SYSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SYNSTARTR ======================================================= */ + #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Pos (0UL) /*!< STR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Msk (0x1UL) /*!< STR (Bitfield-Mask: 0x01) */ +/* ======================================================== LCIVLDR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Pos (0UL) /*!< LOAD (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Msk (0x1UL) /*!< LOAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SYNTDARU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Pos (0UL) /*!< SYNTDARU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Msk (0xffffffffUL) /*!< SYNTDARU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDARL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Pos (0UL) /*!< SYNTDARL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Msk (0xffffffffUL) /*!< SYNTDARL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDBRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Pos (0UL) /*!< SYNTDBRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Msk (0xffffffffUL) /*!< SYNTDBRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDBRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Pos (0UL) /*!< SYNTDBRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Msk (0xffffffffUL) /*!< SYNTDBRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCIVRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Pos (0UL) /*!< LCIVRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Msk (0xffffUL) /*!< LCIVRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== LCIVRM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Pos (0UL) /*!< LCIVRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Msk (0xffffffffUL) /*!< LCIVRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCIVRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Pos (0UL) /*!< LCIVRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Msk (0xffffffffUL) /*!< LCIVRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GETW10R ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Pos (0UL) /*!< GW10 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Msk (0x1UL) /*!< GW10 (Bitfield-Mask: 0x01) */ +/* ======================================================= PLIMITRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Pos (0UL) /*!< PLIMITRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Msk (0x7fffffffUL) /*!< PLIMITRU (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= PLIMITRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Pos (0UL) /*!< PLIMITRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Msk (0xffffffffUL) /*!< PLIMITRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PLIMITRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Pos (0UL) /*!< PLIMITRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Msk (0xffffffffUL) /*!< PLIMITRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MLIMITRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Pos (0UL) /*!< MLIMITRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Msk (0x7fffffffUL) /*!< MLIMITRU (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= MLIMITRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Pos (0UL) /*!< MLIMITRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Msk (0xffffffffUL) /*!< MLIMITRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MLIMITRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Pos (0UL) /*!< MLIMITRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Msk (0xffffffffUL) /*!< MLIMITRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GETINFOR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Pos (0UL) /*!< INFO (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Msk (0x1UL) /*!< INFO (Bitfield-Mask: 0x01) */ +/* ======================================================== LCCVRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Pos (0UL) /*!< LCCVRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Msk (0xffffUL) /*!< LCCVRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== LCCVRM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Pos (0UL) /*!< LCCVRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Msk (0xffffffffUL) /*!< LCCVRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCCVRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Pos (0UL) /*!< LCCVRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Msk (0xffffffffUL) /*!< LCCVRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Pos (0UL) /*!< PW10VRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Msk (0xffffffffUL) /*!< PW10VRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Pos (0UL) /*!< PW10VRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Msk (0xffffffffUL) /*!< PW10VRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Pos (0UL) /*!< PW10VRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Msk (0xffffffffUL) /*!< PW10VRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Pos (0UL) /*!< MW10RU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Msk (0xffffffffUL) /*!< MW10RU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Pos (0UL) /*!< MW10RM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Msk (0xffffffffUL) /*!< MW10RM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Pos (0UL) /*!< MW10RL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Msk (0xffffffffUL) /*!< MW10RL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TMSTARTR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Pos (5UL) /*!< EN5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Msk (0x20UL) /*!< EN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Pos (4UL) /*!< EN4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Msk (0x10UL) /*!< EN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Pos (3UL) /*!< EN3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Msk (0x8UL) /*!< EN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Pos (2UL) /*!< EN2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Msk (0x4UL) /*!< EN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Pos (1UL) /*!< EN1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Pos (0UL) /*!< EN0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Pos (29UL) /*!< URE1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Msk (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Pos (28UL) /*!< URE0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Msk (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Pos (8UL) /*!< MACE (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Msk (0x100UL) /*!< MACE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Pos (3UL) /*!< OVRE3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Msk (0x8UL) /*!< OVRE3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Pos (2UL) /*!< OVRE2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Msk (0x4UL) /*!< OVRE2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Pos (1UL) /*!< OVRE1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Msk (0x2UL) /*!< OVRE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Pos (0UL) /*!< OVRE0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Msk (0x1UL) /*!< OVRE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Pos (29UL) /*!< URE1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Msk (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Pos (28UL) /*!< URE0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Msk (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Pos (8UL) /*!< MACE (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Msk (0x100UL) /*!< MACE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Pos (3UL) /*!< OVRE3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Msk (0x8UL) /*!< OVRE3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Pos (2UL) /*!< OVRE2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Msk (0x4UL) /*!< OVRE2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Pos (1UL) /*!< OVRE1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Msk (0x2UL) /*!< OVRE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Pos (0UL) /*!< OVRE0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Msk (0x1UL) /*!< OVRE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRNDISR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Pos (0UL) /*!< TDIS (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Msk (0x3UL) /*!< TDIS (Bitfield-Mask: 0x03) */ +/* ========================================================= TRNMR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Pos (9UL) /*!< FWD1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Msk (0x200UL) /*!< FWD1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Pos (8UL) /*!< FWD0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Msk (0x100UL) /*!< FWD0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Pos (0UL) /*!< MOD (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Msk (0x1UL) /*!< MOD (Bitfield-Mask: 0x01) */ +/* ======================================================= TRNCTTDR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Pos (0UL) /*!< THVAL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Msk (0x7ffUL) /*!< THVAL (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FBCADDR ======================================================== */ + #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ + #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ +/* ======================================================= FCNTSELR ======================================================== */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ====================================================== FCNTDATAR0 ======================================================= */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FCNTDATAR1 ======================================================= */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_PFBERSA_Pos (1UL) /*!< PFBERSA (Bit 1) */ + #define R_FCACHE_FSAR_PFBERSA_Msk (0x2UL) /*!< PFBERSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_DFLCTLSA_Pos (15UL) /*!< DFLCTLSA (Bit 15) */ + #define R_FCACHE_FSAR_DFLCTLSA_Msk (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GR1_CLUT0 ======================================================= */ + #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR1_CLUT1 ======================================================= */ + #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT0 ======================================================= */ + #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT1 ======================================================= */ + #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (24UL) /*!< TPCS (Bit 24) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7000000UL) /*!< TPCS (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_LOCOSEL_Pos (3UL) /*!< LOCOSEL (Bit 3) */ + #define R_ICU_IRQCR_LOCOSEL_Msk (0x8UL) /*!< LOCOSEL (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN2 ========================================================= */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Pos (0UL) /*!< INTUR0WUPEN (Bit 0) */ + #define R_ICU_WUPEN2_INTUR0WUPEN_Msk (0x1UL) /*!< INTUR0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Pos (1UL) /*!< INTURE0WUPEN (Bit 1) */ + #define R_ICU_WUPEN2_INTURE0WUPEN_Msk (0x2UL) /*!< INTURE0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Pos (2UL) /*!< INTUR1WUPEN (Bit 2) */ + #define R_ICU_WUPEN2_INTUR1WUPEN_Msk (0x4UL) /*!< INTUR1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Pos (3UL) /*!< INTURE1WUPEN (Bit 3) */ + #define R_ICU_WUPEN2_INTURE1WUPEN_Msk (0x8UL) /*!< INTURE1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Pos (4UL) /*!< USBCCSWUPEN (Bit 4) */ + #define R_ICU_WUPEN2_USBCCSWUPEN_Msk (0x10UL) /*!< USBCCSWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRCR ========================================================== */ + #define R_IRDA_IRCR_IRE_Pos (7UL) /*!< IRE (Bit 7) */ + #define R_IRDA_IRCR_IRE_Msk (0x80UL) /*!< IRE (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRTXINV_Pos (3UL) /*!< IRTXINV (Bit 3) */ + #define R_IRDA_IRCR_IRTXINV_Msk (0x8UL) /*!< IRTXINV (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRRXINV_Pos (2UL) /*!< IRRXINV (Bit 2) */ + #define R_IRDA_IRCR_IRRXINV_Msk (0x4UL) /*!< IRRXINV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_JPEG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= JCMOD ========================================================= */ + #define R_JPEG_JCMOD_DSP_Pos (3UL) /*!< DSP (Bit 3) */ + #define R_JPEG_JCMOD_DSP_Msk (0x8UL) /*!< DSP (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCMOD_REDU_Pos (0UL) /*!< REDU (Bit 0) */ + #define R_JPEG_JCMOD_REDU_Msk (0x7UL) /*!< REDU (Bitfield-Mask: 0x07) */ +/* ========================================================= JCCMD ========================================================= */ + #define R_JPEG_JCCMD_BRST_Pos (7UL) /*!< BRST (Bit 7) */ + #define R_JPEG_JCCMD_BRST_Msk (0x80UL) /*!< BRST (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JEND_Pos (2UL) /*!< JEND (Bit 2) */ + #define R_JPEG_JCCMD_JEND_Msk (0x4UL) /*!< JEND (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JRST_Pos (1UL) /*!< JRST (Bit 1) */ + #define R_JPEG_JCCMD_JRST_Msk (0x2UL) /*!< JRST (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JSRT_Pos (0UL) /*!< JSRT (Bit 0) */ + #define R_JPEG_JCCMD_JSRT_Msk (0x1UL) /*!< JSRT (Bitfield-Mask: 0x01) */ +/* ========================================================= JCQTN ========================================================= */ + #define R_JPEG_JCQTN_QT3_Pos (4UL) /*!< QT3 (Bit 4) */ + #define R_JPEG_JCQTN_QT3_Msk (0x30UL) /*!< QT3 (Bitfield-Mask: 0x03) */ + #define R_JPEG_JCQTN_QT2_Pos (2UL) /*!< QT2 (Bit 2) */ + #define R_JPEG_JCQTN_QT2_Msk (0xcUL) /*!< QT2 (Bitfield-Mask: 0x03) */ + #define R_JPEG_JCQTN_QT1_Pos (0UL) /*!< QT1 (Bit 0) */ + #define R_JPEG_JCQTN_QT1_Msk (0x3UL) /*!< QT1 (Bitfield-Mask: 0x03) */ +/* ========================================================= JCHTN ========================================================= */ + #define R_JPEG_JCHTN_HTA3_Pos (5UL) /*!< HTA3 (Bit 5) */ + #define R_JPEG_JCHTN_HTA3_Msk (0x20UL) /*!< HTA3 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD3_Pos (4UL) /*!< HTD3 (Bit 4) */ + #define R_JPEG_JCHTN_HTD3_Msk (0x10UL) /*!< HTD3 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTA2_Pos (3UL) /*!< HTA2 (Bit 3) */ + #define R_JPEG_JCHTN_HTA2_Msk (0x8UL) /*!< HTA2 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD2_Pos (2UL) /*!< HTD2 (Bit 2) */ + #define R_JPEG_JCHTN_HTD2_Msk (0x4UL) /*!< HTD2 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTA1_Pos (1UL) /*!< HTA1 (Bit 1) */ + #define R_JPEG_JCHTN_HTA1_Msk (0x2UL) /*!< HTA1 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD1_Pos (0UL) /*!< HTD1 (Bit 0) */ + #define R_JPEG_JCHTN_HTD1_Msk (0x1UL) /*!< HTD1 (Bitfield-Mask: 0x01) */ +/* ======================================================== JCDRIU ========================================================= */ + #define R_JPEG_JCDRIU_DRIU_Pos (0UL) /*!< DRIU (Bit 0) */ + #define R_JPEG_JCDRIU_DRIU_Msk (0xffUL) /*!< DRIU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDRID ========================================================= */ + #define R_JPEG_JCDRID_DRID_Pos (0UL) /*!< DRID (Bit 0) */ + #define R_JPEG_JCDRID_DRID_Msk (0xffUL) /*!< DRID (Bitfield-Mask: 0xff) */ +/* ======================================================== JCVSZU ========================================================= */ + #define R_JPEG_JCVSZU_VSZU_Pos (0UL) /*!< VSZU (Bit 0) */ + #define R_JPEG_JCVSZU_VSZU_Msk (0xffUL) /*!< VSZU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCVSZD ========================================================= */ + #define R_JPEG_JCVSZD_VSZD_Pos (0UL) /*!< VSZD (Bit 0) */ + #define R_JPEG_JCVSZD_VSZD_Msk (0xffUL) /*!< VSZD (Bitfield-Mask: 0xff) */ +/* ======================================================== JCHSZU ========================================================= */ + #define R_JPEG_JCHSZU_HSZU_Pos (0UL) /*!< HSZU (Bit 0) */ + #define R_JPEG_JCHSZU_HSZU_Msk (0xffUL) /*!< HSZU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCHSZD ========================================================= */ + #define R_JPEG_JCHSZD_HSZD_Pos (0UL) /*!< HSZD (Bit 0) */ + #define R_JPEG_JCHSZD_HSZD_Msk (0xffUL) /*!< HSZD (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCU ========================================================= */ + #define R_JPEG_JCDTCU_DCU_Pos (0UL) /*!< DCU (Bit 0) */ + #define R_JPEG_JCDTCU_DCU_Msk (0xffUL) /*!< DCU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCM ========================================================= */ + #define R_JPEG_JCDTCM_DCM_Pos (0UL) /*!< DCM (Bit 0) */ + #define R_JPEG_JCDTCM_DCM_Msk (0xffUL) /*!< DCM (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCD ========================================================= */ + #define R_JPEG_JCDTCD_DCD_Pos (0UL) /*!< DCD (Bit 0) */ + #define R_JPEG_JCDTCD_DCD_Msk (0xffUL) /*!< DCD (Bitfield-Mask: 0xff) */ +/* ======================================================== JINTE0 ========================================================= */ + #define R_JPEG_JINTE0_INT7_Pos (7UL) /*!< INT7 (Bit 7) */ + #define R_JPEG_JINTE0_INT7_Msk (0x80UL) /*!< INT7 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT6_Pos (6UL) /*!< INT6 (Bit 6) */ + #define R_JPEG_JINTE0_INT6_Msk (0x40UL) /*!< INT6 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT5_Pos (5UL) /*!< INT5 (Bit 5) */ + #define R_JPEG_JINTE0_INT5_Msk (0x20UL) /*!< INT5 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT3_Pos (3UL) /*!< INT3 (Bit 3) */ + #define R_JPEG_JINTE0_INT3_Msk (0x8UL) /*!< INT3 (Bitfield-Mask: 0x01) */ +/* ======================================================== JINTS0 ========================================================= */ + #define R_JPEG_JINTS0_INS6_Pos (6UL) /*!< INS6 (Bit 6) */ + #define R_JPEG_JINTS0_INS6_Msk (0x40UL) /*!< INS6 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS0_INS5_Pos (5UL) /*!< INS5 (Bit 5) */ + #define R_JPEG_JINTS0_INS5_Msk (0x20UL) /*!< INS5 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS0_INS3_Pos (3UL) /*!< INS3 (Bit 3) */ + #define R_JPEG_JINTS0_INS3_Msk (0x8UL) /*!< INS3 (Bitfield-Mask: 0x01) */ +/* ======================================================== JCDERR ========================================================= */ + #define R_JPEG_JCDERR_ERR_Pos (0UL) /*!< ERR (Bit 0) */ + #define R_JPEG_JCDERR_ERR_Msk (0xfUL) /*!< ERR (Bitfield-Mask: 0x0f) */ +/* ========================================================= JCRST ========================================================= */ + #define R_JPEG_JCRST_RST_Pos (0UL) /*!< RST (Bit 0) */ + #define R_JPEG_JCRST_RST_Msk (0x1UL) /*!< RST (Bitfield-Mask: 0x01) */ +/* ======================================================== JIFECNT ======================================================== */ + #define R_JPEG_JIFECNT_JOUTSWAP_Pos (8UL) /*!< JOUTSWAP (Bit 8) */ + #define R_JPEG_JIFECNT_JOUTSWAP_Msk (0x700UL) /*!< JOUTSWAP (Bitfield-Mask: 0x07) */ + #define R_JPEG_JIFECNT_DINRINI_Pos (6UL) /*!< DINRINI (Bit 6) */ + #define R_JPEG_JIFECNT_DINRINI_Msk (0x40UL) /*!< DINRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINRCMD_Pos (5UL) /*!< DINRCMD (Bit 5) */ + #define R_JPEG_JIFECNT_DINRCMD_Msk (0x20UL) /*!< DINRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINLC_Pos (4UL) /*!< DINLC (Bit 4) */ + #define R_JPEG_JIFECNT_DINLC_Msk (0x10UL) /*!< DINLC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINSWAP_Pos (0UL) /*!< DINSWAP (Bit 0) */ + #define R_JPEG_JIFECNT_DINSWAP_Msk (0x7UL) /*!< DINSWAP (Bitfield-Mask: 0x07) */ +/* ======================================================== JIFESA ========================================================= */ + #define R_JPEG_JIFESA_ESA_Pos (0UL) /*!< ESA (Bit 0) */ + #define R_JPEG_JIFESA_ESA_Msk (0xffffffffUL) /*!< ESA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= JIFESOFST ======================================================= */ + #define R_JPEG_JIFESOFST_ESMW_Pos (0UL) /*!< ESMW (Bit 0) */ + #define R_JPEG_JIFESOFST_ESMW_Msk (0x7fffUL) /*!< ESMW (Bitfield-Mask: 0x7fff) */ +/* ======================================================== JIFEDA ========================================================= */ + #define R_JPEG_JIFEDA_EDA_Pos (0UL) /*!< EDA (Bit 0) */ + #define R_JPEG_JIFEDA_EDA_Msk (0xffffffffUL) /*!< EDA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== JIFESLC ======================================================== */ + #define R_JPEG_JIFESLC_LINES_Pos (0UL) /*!< LINES (Bit 0) */ + #define R_JPEG_JIFESLC_LINES_Msk (0xffffUL) /*!< LINES (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDCNT ======================================================== */ + #define R_JPEG_JIFDCNT_VINTER_Pos (28UL) /*!< VINTER (Bit 28) */ + #define R_JPEG_JIFDCNT_VINTER_Msk (0x30000000UL) /*!< VINTER (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_HINTER_Pos (26UL) /*!< HINTER (Bit 26) */ + #define R_JPEG_JIFDCNT_HINTER_Msk (0xc000000UL) /*!< HINTER (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_OPF_Pos (24UL) /*!< OPF (Bit 24) */ + #define R_JPEG_JIFDCNT_OPF_Msk (0x3000000UL) /*!< OPF (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_JINRINI_Pos (14UL) /*!< JINRINI (Bit 14) */ + #define R_JPEG_JIFDCNT_JINRINI_Msk (0x4000UL) /*!< JINRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINRCMD_Pos (13UL) /*!< JINRCMD (Bit 13) */ + #define R_JPEG_JIFDCNT_JINRCMD_Msk (0x2000UL) /*!< JINRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINC_Pos (12UL) /*!< JINC (Bit 12) */ + #define R_JPEG_JIFDCNT_JINC_Msk (0x1000UL) /*!< JINC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINSWAP_Pos (8UL) /*!< JINSWAP (Bit 8) */ + #define R_JPEG_JIFDCNT_JINSWAP_Msk (0x700UL) /*!< JINSWAP (Bitfield-Mask: 0x07) */ + #define R_JPEG_JIFDCNT_DOUTRINI_Pos (6UL) /*!< DOUTRINI (Bit 6) */ + #define R_JPEG_JIFDCNT_DOUTRINI_Msk (0x40UL) /*!< DOUTRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTRCMD_Pos (5UL) /*!< DOUTRCMD (Bit 5) */ + #define R_JPEG_JIFDCNT_DOUTRCMD_Msk (0x20UL) /*!< DOUTRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTLC_Pos (4UL) /*!< DOUTLC (Bit 4) */ + #define R_JPEG_JIFDCNT_DOUTLC_Msk (0x10UL) /*!< DOUTLC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTSWAP_Pos (0UL) /*!< DOUTSWAP (Bit 0) */ + #define R_JPEG_JIFDCNT_DOUTSWAP_Msk (0x7UL) /*!< DOUTSWAP (Bitfield-Mask: 0x07) */ +/* ======================================================== JIFDSA ========================================================= */ + #define R_JPEG_JIFDSA_DSA_Pos (0UL) /*!< DSA (Bit 0) */ + #define R_JPEG_JIFDSA_DSA_Msk (0xffffffffUL) /*!< DSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= JIFDDOFST ======================================================= */ + #define R_JPEG_JIFDDOFST_DDMW_Pos (0UL) /*!< DDMW (Bit 0) */ + #define R_JPEG_JIFDDOFST_DDMW_Msk (0x7fffUL) /*!< DDMW (Bitfield-Mask: 0x7fff) */ +/* ======================================================== JIFDDA ========================================================= */ + #define R_JPEG_JIFDDA_DDA_Pos (0UL) /*!< DDA (Bit 0) */ + #define R_JPEG_JIFDDA_DDA_Msk (0xffffffffUL) /*!< DDA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== JIFDSDC ======================================================== */ + #define R_JPEG_JIFDSDC_JDATAS_Pos (0UL) /*!< JDATAS (Bit 0) */ + #define R_JPEG_JIFDSDC_JDATAS_Msk (0xffffUL) /*!< JDATAS (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDDLC ======================================================== */ + #define R_JPEG_JIFDDLC_LINES_Pos (0UL) /*!< LINES (Bit 0) */ + #define R_JPEG_JIFDDLC_LINES_Msk (0xffffUL) /*!< LINES (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDADT ======================================================== */ + #define R_JPEG_JIFDADT_ALPHA_Pos (0UL) /*!< ALPHA (Bit 0) */ + #define R_JPEG_JIFDADT_ALPHA_Msk (0xffUL) /*!< ALPHA (Bitfield-Mask: 0xff) */ +/* ======================================================== JINTE1 ========================================================= */ + #define R_JPEG_JINTE1_CBTEN_Pos (6UL) /*!< CBTEN (Bit 6) */ + #define R_JPEG_JINTE1_CBTEN_Msk (0x40UL) /*!< CBTEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DINLEN_Pos (5UL) /*!< DINLEN (Bit 5) */ + #define R_JPEG_JINTE1_DINLEN_Msk (0x20UL) /*!< DINLEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DBTEN_Pos (2UL) /*!< DBTEN (Bit 2) */ + #define R_JPEG_JINTE1_DBTEN_Msk (0x4UL) /*!< DBTEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_JINEN_Pos (1UL) /*!< JINEN (Bit 1) */ + #define R_JPEG_JINTE1_JINEN_Msk (0x2UL) /*!< JINEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DOUTLEN_Pos (0UL) /*!< DOUTLEN (Bit 0) */ + #define R_JPEG_JINTE1_DOUTLEN_Msk (0x1UL) /*!< DOUTLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== JINTS1 ========================================================= */ + #define R_JPEG_JINTS1_CBTF_Pos (6UL) /*!< CBTF (Bit 6) */ + #define R_JPEG_JINTS1_CBTF_Msk (0x40UL) /*!< CBTF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DINLF_Pos (5UL) /*!< DINLF (Bit 5) */ + #define R_JPEG_JINTS1_DINLF_Msk (0x20UL) /*!< DINLF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DBTF_Pos (2UL) /*!< DBTF (Bit 2) */ + #define R_JPEG_JINTS1_DBTF_Msk (0x4UL) /*!< DBTF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_JINF_Pos (1UL) /*!< JINF (Bit 1) */ + #define R_JPEG_JINTS1_JINF_Msk (0x2UL) /*!< JINF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DOUTLF_Pos (0UL) /*!< DOUTLF (Bit 0) */ + #define R_JPEG_JINTS1_DOUTLF_Msk (0x1UL) /*!< DOUTLF (Bitfield-Mask: 0x01) */ +/* ======================================================== JCQTBL0 ======================================================== */ +/* ======================================================== JCQTBL1 ======================================================== */ +/* ======================================================== JCQTBL2 ======================================================== */ +/* ======================================================== JCQTBL3 ======================================================== */ +/* ======================================================== JCHTBD0 ======================================================== */ +/* ======================================================== JCHTBD1 ======================================================== */ +/* ======================================================== JCHTBA0 ======================================================== */ +/* ======================================================== JCHTBA1 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MMSFR ========================================================= */ + #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */ + #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= MMEN ========================================================== */ + #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SMPUCTL ======================================================== */ + #define R_MPU_SMPU_SMPUCTL_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SMPU_SMPUCTL_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos (1UL) /*!< PROTECT (Bit 1) */ + #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk (0x2UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_MPU_SMPU_SMPUCTL_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SMPU_SMPUCTL_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCCR0 ========================================================= */ + #define R_PDC_PCCR0_EDS_Pos (14UL) /*!< EDS (Bit 14) */ + #define R_PDC_PCCR0_EDS_Msk (0x4000UL) /*!< EDS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PCKDIV_Pos (11UL) /*!< PCKDIV (Bit 11) */ + #define R_PDC_PCCR0_PCKDIV_Msk (0x3800UL) /*!< PCKDIV (Bitfield-Mask: 0x07) */ + #define R_PDC_PCCR0_PCKOE_Pos (10UL) /*!< PCKOE (Bit 10) */ + #define R_PDC_PCCR0_PCKOE_Msk (0x400UL) /*!< PCKOE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_HERIE_Pos (9UL) /*!< HERIE (Bit 9) */ + #define R_PDC_PCCR0_HERIE_Msk (0x200UL) /*!< HERIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_VERIE_Pos (8UL) /*!< VERIE (Bit 8) */ + #define R_PDC_PCCR0_VERIE_Msk (0x100UL) /*!< VERIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_UDRIE_Pos (7UL) /*!< UDRIE (Bit 7) */ + #define R_PDC_PCCR0_UDRIE_Msk (0x80UL) /*!< UDRIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_OVIE_Pos (6UL) /*!< OVIE (Bit 6) */ + #define R_PDC_PCCR0_OVIE_Msk (0x40UL) /*!< OVIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_FEIE_Pos (5UL) /*!< FEIE (Bit 5) */ + #define R_PDC_PCCR0_FEIE_Msk (0x20UL) /*!< FEIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_DFIE_Pos (4UL) /*!< DFIE (Bit 4) */ + #define R_PDC_PCCR0_DFIE_Msk (0x10UL) /*!< DFIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PRST_Pos (3UL) /*!< PRST (Bit 3) */ + #define R_PDC_PCCR0_PRST_Msk (0x8UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_HPS_Pos (2UL) /*!< HPS (Bit 2) */ + #define R_PDC_PCCR0_HPS_Msk (0x4UL) /*!< HPS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_VPS_Pos (1UL) /*!< VPS (Bit 1) */ + #define R_PDC_PCCR0_VPS_Msk (0x2UL) /*!< VPS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PCKE_Pos (0UL) /*!< PCKE (Bit 0) */ + #define R_PDC_PCCR0_PCKE_Msk (0x1UL) /*!< PCKE (Bitfield-Mask: 0x01) */ +/* ========================================================= PCCR1 ========================================================= */ + #define R_PDC_PCCR1_PCE_Pos (0UL) /*!< PCE (Bit 0) */ + #define R_PDC_PCCR1_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */ +/* ========================================================= PCSR ========================================================== */ + #define R_PDC_PCSR_HERF_Pos (6UL) /*!< HERF (Bit 6) */ + #define R_PDC_PCSR_HERF_Msk (0x40UL) /*!< HERF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_VERF_Pos (5UL) /*!< VERF (Bit 5) */ + #define R_PDC_PCSR_VERF_Msk (0x20UL) /*!< VERF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_PDC_PCSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_OVRF_Pos (3UL) /*!< OVRF (Bit 3) */ + #define R_PDC_PCSR_OVRF_Msk (0x8UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FEF_Pos (2UL) /*!< FEF (Bit 2) */ + #define R_PDC_PCSR_FEF_Msk (0x4UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FEMPF_Pos (1UL) /*!< FEMPF (Bit 1) */ + #define R_PDC_PCSR_FEMPF_Msk (0x2UL) /*!< FEMPF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FBSY_Pos (0UL) /*!< FBSY (Bit 0) */ + #define R_PDC_PCSR_FBSY_Msk (0x1UL) /*!< FBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== PCMONR ========================================================= */ + #define R_PDC_PCMONR_HSYNC_Pos (1UL) /*!< HSYNC (Bit 1) */ + #define R_PDC_PCMONR_HSYNC_Msk (0x2UL) /*!< HSYNC (Bitfield-Mask: 0x01) */ + #define R_PDC_PCMONR_VSYNC_Pos (0UL) /*!< VSYNC (Bit 0) */ + #define R_PDC_PCMONR_VSYNC_Msk (0x1UL) /*!< VSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= PCDR ========================================================== */ + #define R_PDC_PCDR_PCDR_Pos (0UL) /*!< PCDR (Bit 0) */ + #define R_PDC_PCDR_PCDR_Msk (0xffffffffUL) /*!< PCDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== VCR ========================================================== */ + #define R_PDC_VCR_VSZ_Pos (16UL) /*!< VSZ (Bit 16) */ + #define R_PDC_VCR_VSZ_Msk (0xfff0000UL) /*!< VSZ (Bitfield-Mask: 0xfff) */ + #define R_PDC_VCR_VST_Pos (0UL) /*!< VST (Bit 0) */ + #define R_PDC_VCR_VST_Msk (0xfffUL) /*!< VST (Bitfield-Mask: 0xfff) */ +/* ========================================================== HCR ========================================================== */ + #define R_PDC_HCR_HSZ_Pos (16UL) /*!< HSZ (Bit 16) */ + #define R_PDC_HCR_HSZ_Msk (0xfff0000UL) /*!< HSZ (Bitfield-Mask: 0xfff) */ + #define R_PDC_HCR_HST_Pos (0UL) /*!< HST (Bit 0) */ + #define R_PDC_HCR_HST_Msk (0xfffUL) /*!< HST (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================== PRWCNTR ======================================================== */ + #define R_PMISC_PRWCNTR_WAIT_Pos (0UL) /*!< WAIT (Bit 0) */ + #define R_PMISC_PRWCNTR_WAIT_Msk (0x3UL) /*!< WAIT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SRCFCTR ======================================================== */ + #define R_SRC_SRCFCTR_SRCFCOE_Pos (0UL) /*!< SRCFCOE (Bit 0) */ + #define R_SRC_SRCFCTR_SRCFCOE_Msk (0x3fffffUL) /*!< SRCFCOE (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= SRCID ========================================================= */ + #define R_SRC_SRCID_SRCID_Pos (0UL) /*!< SRCID (Bit 0) */ + #define R_SRC_SRCID_SRCID_Msk (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SRCOD ========================================================= */ + #define R_SRC_SRCOD_SRCOD_Pos (0UL) /*!< SRCOD (Bit 0) */ + #define R_SRC_SRCOD_SRCOD_Msk (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCIDCTRL ======================================================= */ + #define R_SRC_SRCIDCTRL_IED_Pos (9UL) /*!< IED (Bit 9) */ + #define R_SRC_SRCIDCTRL_IED_Msk (0x200UL) /*!< IED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IEN_Pos (8UL) /*!< IEN (Bit 8) */ + #define R_SRC_SRCIDCTRL_IEN_Msk (0x100UL) /*!< IEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IFTRG_Pos (0UL) /*!< IFTRG (Bit 0) */ + #define R_SRC_SRCIDCTRL_IFTRG_Msk (0x3UL) /*!< IFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCCTRL ======================================================== */ + #define R_SRC_SRCCTRL_FICRAE_Pos (15UL) /*!< FICRAE (Bit 15) */ + #define R_SRC_SRCCTRL_FICRAE_Msk (0x8000UL) /*!< FICRAE (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CEEN_Pos (13UL) /*!< CEEN (Bit 13) */ + #define R_SRC_SRCCTRL_CEEN_Msk (0x2000UL) /*!< CEEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_SRCEN_Pos (12UL) /*!< SRCEN (Bit 12) */ + #define R_SRC_SRCCTRL_SRCEN_Msk (0x1000UL) /*!< SRCEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_UDEN_Pos (11UL) /*!< UDEN (Bit 11) */ + #define R_SRC_SRCCTRL_UDEN_Msk (0x800UL) /*!< UDEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_OVEN_Pos (10UL) /*!< OVEN (Bit 10) */ + #define R_SRC_SRCCTRL_OVEN_Msk (0x400UL) /*!< OVEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_FL_Pos (9UL) /*!< FL (Bit 9) */ + #define R_SRC_SRCCTRL_FL_Msk (0x200UL) /*!< FL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CL_Pos (8UL) /*!< CL (Bit 8) */ + #define R_SRC_SRCCTRL_CL_Msk (0x100UL) /*!< CL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_IFS_Pos (4UL) /*!< IFS (Bit 4) */ + #define R_SRC_SRCCTRL_IFS_Msk (0xf0UL) /*!< IFS (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCCTRL_OFS_Pos (0UL) /*!< OFS (Bit 0) */ + #define R_SRC_SRCCTRL_OFS_Msk (0x7UL) /*!< OFS (Bitfield-Mask: 0x07) */ +/* ======================================================= SRCODCTRL ======================================================= */ + #define R_SRC_SRCODCTRL_OCH_Pos (10UL) /*!< OCH (Bit 10) */ + #define R_SRC_SRCODCTRL_OCH_Msk (0x400UL) /*!< OCH (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OED_Pos (9UL) /*!< OED (Bit 9) */ + #define R_SRC_SRCODCTRL_OED_Msk (0x200UL) /*!< OED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OEN_Pos (8UL) /*!< OEN (Bit 8) */ + #define R_SRC_SRCODCTRL_OEN_Msk (0x100UL) /*!< OEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OFTRG_Pos (0UL) /*!< OFTRG (Bit 0) */ + #define R_SRC_SRCODCTRL_OFTRG_Msk (0x3UL) /*!< OFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCSTAT ======================================================== */ + #define R_SRC_SRCSTAT_OFDN_Pos (11UL) /*!< OFDN (Bit 11) */ + #define R_SRC_SRCSTAT_OFDN_Msk (0xf800UL) /*!< OFDN (Bitfield-Mask: 0x1f) */ + #define R_SRC_SRCSTAT_IFDN_Pos (7UL) /*!< IFDN (Bit 7) */ + #define R_SRC_SRCSTAT_IFDN_Msk (0x780UL) /*!< IFDN (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCSTAT_CEF_Pos (5UL) /*!< CEF (Bit 5) */ + #define R_SRC_SRCSTAT_CEF_Msk (0x20UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_FLF_Pos (4UL) /*!< FLF (Bit 4) */ + #define R_SRC_SRCSTAT_FLF_Msk (0x10UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_UDF_Pos (3UL) /*!< UDF (Bit 3) */ + #define R_SRC_SRCSTAT_UDF_Msk (0x8UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OVF_Pos (2UL) /*!< OVF (Bit 2) */ + #define R_SRC_SRCSTAT_OVF_Msk (0x4UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_IINT_Pos (1UL) /*!< IINT (Bit 1) */ + #define R_SRC_SRCSTAT_IINT_Msk (0x2UL) /*!< IINT (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OINT_Pos (0UL) /*!< OINT (Bit 0) */ + #define R_SRC_SRCSTAT_OINT_Msk (0x1UL) /*!< OINT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR2 ======================================================== */ + #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */ + #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */ + #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x7UL) /*!< LVDLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6M3AH_H */ + +/** @} */ /* End of group R7FA6M3AH */ + +/** @} */ /* End of group Renesas */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h new file mode 100644 index 0000000000..7f535ca581 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h @@ -0,0 +1,45231 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7FA8D1BH.h + * @brief CMSIS HeaderFile + * @version 1.2 + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA8D1BH + * @{ + */ + +#ifndef R7FA8D1BH_H + #define R7FA8D1BH_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M85 Processor and Core Peripherals =========================== */ + #define __CM85_REV 0x0000U /*!< CM85 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */ + #define __DCACHE_PRESENT 1 /*!< Data Cache present */ + #define __SAUREGION_PRESENT 1 /*!< SAU region present */ + #define __PMU_PRESENT 1 /*!< PMU present */ + #define __PMU_NUM_EVENTCNT 8 /*!< PMU Event Counters */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm85.h" /*!< ARM Cortex-M85 processor and core peripherals */ + #include "system.h" /*!< R7FA8D1BH System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + }; + __IM uint32_t RESERVED3; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..30]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; + }; + + union + { + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ + + struct + { + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; + }; + + union + { + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position + * Register */ + + struct + { + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; + }; + + union + { + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; + }; + + union + { + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + } HSIZE_b; + }; + + union + { + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; + }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ + +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + + struct + { + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; + }; + + union + { + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + + struct + { + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; + }; + + union + { + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + + struct + { + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; + }; + + union + { + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + + struct + { + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; + }; + + union + { + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + + struct + { + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; + }; + + union + { + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + + struct + { + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; + }; + + union + { + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + + struct + { + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; + }; + + union + { + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + + struct + { + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; + }; + + union + { + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + + struct + { + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; + }; + + union + { + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + + struct + { + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; + }; + + union + { + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + + struct + { + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; + }; + + union + { + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + + struct + { + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; + }; + + union + { + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + + struct + { + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; + }; + + union + { + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + + struct + { + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; + }; + + union + { + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + + struct + { + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + + struct + { + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; + }; + + union + { + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + + struct + { + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + + struct + { + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; + }; + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + */ +typedef struct +{ + union + { + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; + }; + + union + { + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + + struct + { + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; + }; + + union + { + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; + }; + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control + * Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; + }; + + union + { + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + + struct + { + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; + }; + + union + { + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ + + struct + { + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; + }; + + union + { + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ + + struct + { + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; + }; + + union + { + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + + struct + { + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; + }; + + union + { + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ + + struct + { + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; + }; +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + + struct + { + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; + + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; + }; + + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; + + union + { + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; + }; + + union + { + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; + }; + + union + { + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; + }; + + union + { + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; + }; + + union + { + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; + + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; + }; + + union + { + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + + struct + { + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; + }; +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ + +/** + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ + + struct + { + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; + }; + + union + { + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ + + struct + { + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; + }; + + union + { + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + + struct + { + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; + }; + + union + { + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + + struct + { + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; + }; + + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ + + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint32_t : 1; + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint16_t : 1; + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint8_t : 1; + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_XSPI0_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration register 0 */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode */ + __IOM uint32_t ARYAMD : 1; /*!< [5..5] Array address mode */ + uint32_t : 10; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration register 1 */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration register 2 */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CMCFGCS_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CDBUF [CDBUF] (xSPI BUF register) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2byte) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_CDBUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CCCTLCS [CCCTLCS] (xSPI CS register) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control register 0 */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control register 1 */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control register 2 */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3 */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control register 4 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control register 5 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control register 6 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CCCTLCS_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_OFS_DATAFLASH_CFGDLOCK_CFGD [CFGD] (Configuration Data [0..1] Lock Bits) + */ +typedef struct +{ + union + { + __IM uint32_t CFGD_L; /*!< (@ 0x00000000) Configuration Data Lock Bits Lower Word */ + + struct + { + __IM uint32_t CDLK0 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint32_t CDLK1 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint32_t CDLK2 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint32_t CDLK3 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint32_t CDLK4 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint32_t CDLK5 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint32_t CDLK6 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint32_t CDLK7 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint32_t CDLK8 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint32_t CDLK9 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint32_t CDLK10 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint32_t CDLK11 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint32_t CDLK12 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint32_t CDLK13 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint32_t CDLK14 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint32_t CDLK15 : 1; /*!< [15..15] Configuration Data Lock Bit */ + __IM uint32_t CDLK16 : 1; /*!< [16..16] Configuration Data Lock Bit */ + __IM uint32_t CDLK17 : 1; /*!< [17..17] Configuration Data Lock Bit */ + __IM uint32_t CDLK18 : 1; /*!< [18..18] Configuration Data Lock Bit */ + __IM uint32_t CDLK19 : 1; /*!< [19..19] Configuration Data Lock Bit */ + __IM uint32_t CDLK20 : 1; /*!< [20..20] Configuration Data Lock Bit */ + __IM uint32_t CDLK21 : 1; /*!< [21..21] Configuration Data Lock Bit */ + __IM uint32_t CDLK22 : 1; /*!< [22..22] Configuration Data Lock Bit */ + __IM uint32_t CDLK23 : 1; /*!< [23..23] Configuration Data Lock Bit */ + __IM uint32_t CDLK24 : 1; /*!< [24..24] Configuration Data Lock Bit */ + __IM uint32_t CDLK25 : 1; /*!< [25..25] Configuration Data Lock Bit */ + __IM uint32_t CDLK26 : 1; /*!< [26..26] Configuration Data Lock Bit */ + __IM uint32_t CDLK27 : 1; /*!< [27..27] Configuration Data Lock Bit */ + __IM uint32_t CDLK28 : 1; /*!< [28..28] Configuration Data Lock Bit */ + __IM uint32_t CDLK29 : 1; /*!< [29..29] Configuration Data Lock Bit */ + __IM uint32_t CDLK30 : 1; /*!< [30..30] Configuration Data Lock Bit */ + __IM uint32_t CDLK31 : 1; /*!< [31..31] Configuration Data Lock Bit */ + } CFGD_L_b; + }; + + union + { + __IM uint32_t CFGD_H; /*!< (@ 0x00000004) Configuration Data Lock Bits Higher Word */ + + struct + { + __IM uint32_t CDLK32 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint32_t CDLK33 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint32_t CDLK34 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint32_t CDLK35 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint32_t CDLK36 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint32_t CDLK37 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint32_t CDLK38 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint32_t CDLK39 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint32_t CDLK40 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint32_t CDLK41 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint32_t CDLK42 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint32_t CDLK43 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint32_t CDLK44 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint32_t CDLK45 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint32_t CDLK46 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint32_t CDLK47 : 1; /*!< [15..15] Configuration Data Lock Bit */ + __IM uint32_t CDLK48 : 1; /*!< [16..16] Configuration Data Lock Bit */ + __IM uint32_t CDLK49 : 1; /*!< [17..17] Configuration Data Lock Bit */ + __IM uint32_t CDLK50 : 1; /*!< [18..18] Configuration Data Lock Bit */ + __IM uint32_t CDLK51 : 1; /*!< [19..19] Configuration Data Lock Bit */ + __IM uint32_t CDLK52 : 1; /*!< [20..20] Configuration Data Lock Bit */ + __IM uint32_t CDLK53 : 1; /*!< [21..21] Configuration Data Lock Bit */ + __IM uint32_t CDLK54 : 1; /*!< [22..22] Configuration Data Lock Bit */ + __IM uint32_t CDLK55 : 1; /*!< [23..23] Configuration Data Lock Bit */ + __IM uint32_t CDLK56 : 1; /*!< [24..24] Configuration Data Lock Bit */ + __IM uint32_t CDLK57 : 1; /*!< [25..25] Configuration Data Lock Bit */ + __IM uint32_t CDLK58 : 1; /*!< [26..26] Configuration Data Lock Bit */ + __IM uint32_t CDLK59 : 1; /*!< [27..27] Configuration Data Lock Bit */ + __IM uint32_t CDLK60 : 1; /*!< [28..28] Configuration Data Lock Bit */ + __IM uint32_t CDLK61 : 1; /*!< [29..29] Configuration Data Lock Bit */ + __IM uint32_t CDLK62 : 1; /*!< [30..30] Configuration Data Lock Bit */ + __IM uint32_t CDLK63 : 1; /*!< [31..31] Configuration Data Lock Bit */ + } CFGD_H_b; + }; +} R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_OFS_DATAFLASH_CFGDLOCK [CFGDLOCK] (Configuration Data Lock Bits) + */ +typedef struct +{ + __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD0; /*!< (@ 0x00000000) Configuration Data 0 Lock Bits */ + __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD1; /*!< (@ 0x00000008) Configuration Data 1 Lock Bits */ + + union + { + __IM uint16_t CFGD2; /*!< (@ 0x00000010) Configuration Data 2 Lock Bit */ + + struct + { + __IM uint16_t CDLK0 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint16_t CDLK1 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint16_t CDLK2 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint16_t CDLK3 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint16_t CDLK4 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint16_t CDLK5 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint16_t CDLK6 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint16_t CDLK7 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint16_t CDLK8 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint16_t CDLK9 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint16_t CDLK10 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint16_t CDLK11 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint16_t CDLK12 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint16_t CDLK13 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint16_t CDLK14 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint16_t CDLK15 : 1; /*!< [15..15] Configuration Data Lock Bit */ + } CFGD2_b; + }; + __IM uint16_t RESERVED; +} R_OFS_DATAFLASH_CFGDLOCK_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40332000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x40204000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ + } MSSAR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARB_b; + }; + + union + { + __IOM uint32_t PPARC; /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C */ + + struct + { + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARC_b; + }; + + union + { + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARD_b; + }; + + union + { + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARE_b; + }; + + union + { + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } MSPAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000034) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 60 (0x3c) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED13[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40202400) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40310000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40333000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 12; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x4000A800) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x4000A000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x40344000) R_DRW Structure */ +{ + union + { + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ + + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; + }; + + union + { + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union + { + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; + }; + __IM uint32_t RESERVED[2]; + + union + { + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; + }; + + union + { + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; + }; + + union + { + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; + }; + + union + { + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; + }; + + union + { + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; + }; + + union + { + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; + }; + + union + { + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; + }; + + union + { + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; + }; + + union + { + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; + }; + + union + { + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; + }; + + union + { + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; + }; + + union + { + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; + }; + + union + { + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; + }; + + union + { + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; + }; + + union + { + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; + }; + + union + { + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; + }; + + union + { + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; + }; + + union + { + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; + }; + + union + { + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; + }; + + union + { + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; + }; + __IM uint32_t RESERVED1; + + union + { + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + + struct + { + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; + }; + + union + { + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + + struct + { + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + + struct + { + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; + }; + + union + { + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + + struct + { + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; + }; + + union + { + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + + struct + { + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; + + union + { + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + + struct + { + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + + struct + { + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; + }; + + union + { + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + + struct + { + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; + }; + + union + { + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + + struct + { + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; + }; + + union + { + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + + struct + { + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; + }; + + union + { + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + + struct + { + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; + }; + + union + { + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; + }; + + union + { + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; + }; + + union + { + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + + struct + { + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + + struct + { + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; + }; + + union + { + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + + struct + { + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; + }; + + union + { + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + + struct + { + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; + }; + + union + { + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + + struct + { + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; + }; + + union + { + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + + struct + { + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; + }; + + union + { + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + + struct + { + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; + }; + + union + { + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; + }; + + union + { + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; + }; + + union + { + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + + struct + { + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + + struct + { + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; + }; + + union + { + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + + struct + { + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; + }; + + union + { + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + + struct + { + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; + }; + + union + { + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + + struct + { + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t DBWER; /*!< (@ 0x00000100) DRW Bufferable Write Enable Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t BWE : 1; /*!< [2..2] Bufferable Write Enable */ + uint32_t : 29; + } DBWER_b; + }; +} R_DRW_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x4000AC00) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40201000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */ + __IM uint32_t RESERVED2[6]; + __IOM R_ELC_ELSR_Type ELSR[31]; /*!< (@ 0x00000020) Event Link Setting Register [0..30] */ + __IM uint32_t RESERVED3[17]; + + union + { + __IOM uint32_t ELCSARA; /*!< (@ 0x000000E0) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint32_t : 29; + } ELCSARA_b; + }; + + union + { + __IOM uint32_t ELCSARB; /*!< (@ 0x000000E4) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + uint32_t : 12; + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + uint32_t : 1; + } ELCSARB_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t ELCPARA; /*!< (@ 0x000000F0) Event Link Controller Privilege Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller Register Privilege Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Privilege + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Privilege + * Attribution */ + uint32_t : 29; + } ELCPARA_b; + }; + + union + { + __IOM uint32_t ELCPARB; /*!< (@ 0x000000F4) Event Link Controller Privilege Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + uint32_t : 12; + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + uint32_t : 1; + } ELCPARB_b; + }; +} R_ELC_Type; /*!< Size = 248 (0xf8) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40354100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x40100000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x4011E000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } FCNTSELR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR0_b; + }; + + union + { + __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[11]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ + + struct + { + __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address + * or the last blank checked address which is found in 'Blank + * Check' command execution. */ + uint32_t : 8; + } FBCADDR_b; + }; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C100) R_FCACHE Structure */ +{ + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000000) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] Flash Cache Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000004) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED1[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000001C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000040) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t FCACHEENSA : 1; /*!< [1..1] FCHACHEEN Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI command Registers Security Attribution */ + __IOM uint16_t FACITRSA : 1; /*!< [11..11] FACI transfer Security Attribution */ + uint16_t : 4; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 66 (0x42) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x40342000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40322000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + + union + { + __IM uint8_t NMICR; /*!< (@ 0x00000010) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[6143]; + + union + { + __IOM uint8_t SWIRQ_S; /*!< (@ 0x00006010) Software Interrupt Request Register for Secure + * Interrupt */ + + struct + { + __IOM uint8_t SWIRQS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem. */ + uint8_t : 7; + } SWIRQ_S_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint8_t SWIRQ_NS; /*!< (@ 0x00006020) Software Interrupt Request Register for Non-secure + * Interrupt */ + + struct + { + __IOM uint8_t SWIRQNS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem. */ + uint8_t : 7; + } SWIRQ_NS_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + __IM uint32_t RESERVED8[15]; + + union + { + __IOM uint16_t IENMIER; /*!< (@ 0x00006060) Integrated Error NMI Interrupt Enable Registe + * for CPU */ + + struct + { + __IOM uint16_t CMEN : 1; /*!< [0..0] Integrated Common Memory error nmi Enable */ + __IOM uint16_t LMEN : 1; /*!< [1..1] Integrated Local Memory error nmi Enable */ + __IOM uint16_t BUSEN : 1; /*!< [2..2] Integrated BUS error nmi Enable */ + uint16_t : 13; + } IENMIER_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[39]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + uint16_t : 2; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t BUSEN : 1; /*!< [12..12] BUS error Interrupt Enable */ + __IOM uint16_t CMEN : 1; /*!< [13..13] Common Memory error Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LUEN : 1; /*!< [15..15] LockUp Interrupt Enable */ + } NMIER_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __IOM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __IOM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __IOM uint16_t LVD1CLR : 1; /*!< [2..2] PVD1 Clear */ + __IOM uint16_t LVD2CLR : 1; /*!< [3..3] PVD2 Clear */ + uint16_t : 2; + __IOM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __IOM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + uint16_t : 4; + __IOM uint16_t BUSCLR : 1; /*!< [12..12] Bus Clear */ + __IOM uint16_t CMCLR : 1; /*!< [13..13] CM Clear */ + uint16_t : 1; + __IOM uint16_t LUCLR : 1; /*!< [15..15] LU Clear */ + } NMICLR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + uint16_t : 2; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + uint16_t : 4; + __IM uint16_t BUSST : 1; /*!< [12..12] BUS error Interrupt Status Flag */ + __IM uint16_t CMST : 1; /*!< [13..13] Common Memory error Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t LUST : 1; /*!< [15..15] LockUp Interrupt Status Flag */ + } NMISR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[31]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + uint32_t : 1; + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] PVD1 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] PVD2 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT Monitor Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + uint32_t : 3; + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC Alarm Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT Period Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS0 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 Compare Match A Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t RIIC0WUPEN : 1; /*!< [31..31] RIIC0 Address Match Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1 */ + + struct + { + uint32_t : 3; + __IOM uint32_t COMPHS0WUPEN : 1; /*!< [3..3] Comparator-HS0 Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + uint32_t : 4; + __IOM uint32_t ULP0UWUPEN : 1; /*!< [8..8] ULPT0 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP0AWUPEN : 1; /*!< [9..9] ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP0BWUPEN : 1; /*!< [10..10] ULPT0 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t I3CWUPEN : 1; /*!< [11..11] I3C Wakeup Condition Detection Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t ULP1UWUPEN : 1; /*!< [12..12] ULPT1 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP1AWUPEN : 1; /*!< [13..13] ULPT1 Compare Match A Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t ULP1BWUPEN : 1; /*!< [14..14] ULPT1 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + uint32_t : 17; + } WUPEN1_b; + }; + __IM uint32_t RESERVED17[86]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 25728 (0x6480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4025E000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40202200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED13[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED14[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; + } SVST_b; + }; + + union + { + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ + + struct + { + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED27[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED28[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED30; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED32[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED33[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40203000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40400000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000002) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + + union + { + __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40400800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40400D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[3]; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[13]; + __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40202000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40252000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint16_t SRAMPRCR; /*!< (@ 0x00000000) SRAM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t SRAMPRCR_NS; /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) SRAM Wait State Control Register */ + + struct + { + __IOM uint8_t WTEN : 1; /*!< [0..0] Wait enable */ + uint8_t : 7; + } SRAMWTSC_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4; + + union + { + __IOM uint8_t SRAMCR0; /*!< (@ 0x00000010) SRAM Control Register 0 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection for 1-bit ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR0_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRAMCR1; /*!< (@ 0x00000014) SRAM Control Register 1 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection for parity error detection */ + uint8_t : 7; + } SRAMCR1_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SRAMECCRGN0; /*!< (@ 0x00000030) SRAM0 ECC Region Control Register */ + + struct + { + __IOM uint8_t ECCRGN : 2; /*!< [1..0] ECC Region */ + uint8_t : 6; + } SRAMECCRGN0_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[3]; + + union + { + __IM uint16_t SRAMESR; /*!< (@ 0x00000040) SRAM Error Status Register */ + + struct + { + __IM uint16_t ERR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status */ + __IM uint16_t ERR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status */ + __IM uint16_t ERR1 : 1; /*!< [2..2] SRAM1 Parity Error Status */ + uint16_t : 11; + __IM uint16_t ERRS : 1; /*!< [14..14] Standby SRAM Parity Error status */ + uint16_t : 1; + } SRAMESR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t SRAMESCLR; /*!< (@ 0x00000048) SRAM Error Status Clear Register */ + + struct + { + __IOM uint16_t CLR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status Clear */ + __IOM uint16_t CLR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status Clear */ + __IOM uint16_t CLR1 : 1; /*!< [2..2] SRAM1 Parity Error Status Clear */ + uint16_t : 11; + __IOM uint16_t CLRS : 1; /*!< [14..14] Standby SRAM Parity Error Status Clear */ + uint16_t : 1; + } SRAMESCLR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IM uint32_t SRAMEAR0; /*!< (@ 0x00000050) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR0_b; + }; + + union + { + __IM uint32_t SRAMEAR1; /*!< (@ 0x00000054) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR1_b; + }; + + union + { + __IM uint32_t SRAMEAR2; /*!< (@ 0x00000058) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR2_b; + }; + __IM uint32_t RESERVED17[45]; + + union + { + __IOM uint8_t STBRAMCR; /*!< (@ 0x00000110) Standby SRAM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection */ + uint8_t : 7; + } STBRAMCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[15]; + + union + { + __IM uint32_t STBRAMEAR; /*!< (@ 0x00000150) Standby SRAM Error Address Register */ + + struct + { + uint32_t : 2; + __IM uint32_t EA : 8; /*!< [9..2] SRAM Error Address */ + uint32_t : 22; + } STBRAMEAR_b; + }; +} R_SRAM_Type; /*!< Size = 340 (0x154) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4025D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint8_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t OPE : 1; /*!< [6..6] Output Port Enable */ + uint8_t : 1; + } SBYCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t SSCR2; /*!< (@ 0x0000000E) Software Standby Control Register 2 */ + + struct + { + __IM uint8_t SS1RSF : 1; /*!< [0..0] Software Standby 1 regulator status flag */ + uint8_t : 7; + } SSCR2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t FLSCR; /*!< (@ 0x00000010) Flash Standby Control Register */ + + struct + { + __IOM uint8_t FLSWCF : 1; /*!< [0..0] Flash Stabilization wait completion flag */ + uint8_t : 7; + } FLSCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 4; /*!< [3..0] Peripheral Module Clock D (PCLKD) Select */ + __IOM uint32_t PCKC : 4; /*!< [7..4] Peripheral Module Clock C (PCLKC) Select */ + __IOM uint32_t PCKB : 4; /*!< [11..8] Peripheral Module Clock B (PCLKB) Select */ + __IOM uint32_t PCKA : 4; /*!< [15..12] Peripheral Module Clock A (PCLKA) Select */ + __IOM uint32_t BCK : 4; /*!< [19..16] External Bus Clock (BCLK) Select */ + __IOM uint32_t PCKE : 4; /*!< [23..20] Peripheral Module Clock E (PCLKE) Select */ + __IOM uint32_t ICK : 4; /*!< [27..24] System Clock (ICLK) Select */ + __IOM uint32_t FCK : 4; /*!< [31..28] Flash IF Clock (FCLK) Select */ + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + __IOM uint8_t CPUCK : 4; /*!< [3..0] CPU Clock (CPUCLK) Select */ + uint8_t : 4; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select */ + uint16_t : 1; + __IOM uint16_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select */ + __IOM uint16_t PLLMUL : 8; /*!< [15..8] PLL1 Frequency Multiplication Factor Select */ + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + __IM uint8_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock source select */ + uint8_t : 2; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IM uint8_t OSCMONR; /*!< (@ 0x00000043) Oscillator Monitor Register */ + + struct + { + uint8_t : 1; + __IM uint8_t MOCOMON : 1; /*!< [1..1] MOCO operation monitor */ + __IM uint8_t LOCOMON : 1; /*!< [2..2] LOCO operation monitor */ + uint8_t : 5; + } OSCMONR_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 1; + __IOM uint16_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select */ + __IOM uint16_t PLL2MUL : 8; /*!< [15..8] PLL2 Frequency Multiplication Factor Select */ + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint16_t PLLCCR2; /*!< (@ 0x0000004C) PLL Clock Control Register 2 */ + + struct + { + __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLLCCR2_b; + }; + + union + { + __IOM uint16_t PLL2CCR2; /*!< (@ 0x0000004E) PLL2 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLL2CCR2_b; + }; + __IM uint16_t RESERVED18; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + + union + { + __IOM uint8_t SCICKDIVCR; /*!< (@ 0x00000054) SCI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } SCICKDIVCR_b; + }; + + union + { + __IOM uint8_t SCICKCR; /*!< (@ 0x00000055) SCI clock control register */ + + struct + { + __IOM uint8_t SCICKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } SCICKCR_b; + }; + + union + { + __IOM uint8_t SPICKDIVCR; /*!< (@ 0x00000056) SPI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } SPICKDIVCR_b; + }; + + union + { + __IOM uint8_t SPICKCR; /*!< (@ 0x00000057) SPI clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } SPICKCR_b; + }; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t ADCCKDIVCR; /*!< (@ 0x0000005A) ADC clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } ADCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ADCCKCR; /*!< (@ 0x0000005B) ADC clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ADCCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000005C) GPT clock Division control register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x0000005D) GPT clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t LCDCKDIVCR; /*!< (@ 0x0000005E) LCD clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } LCDCKDIVCR_b; + }; + + union + { + __IOM uint8_t LCDCKCR; /*!< (@ 0x0000005F) LCD clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } LCDCKCR_b; + }; + __IM uint8_t RESERVED20; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB clock Division control register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI clock Division control register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Core clock Division control register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Core clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 clock Division control register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000070) I3C clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 5; + } I3CCKDIVCR_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB clock control register */ + + struct + { + __IOM uint8_t USBCKSEL : 4; /*!< [3..0] USB clock (USBCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB clock (USBCLK) Switching Request */ + __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI clock control register */ + + struct + { + __IOM uint8_t OCTACKSEL : 4; /*!< [3..0] Octal-SPI clock (OCTACLK) Source Select */ + uint8_t : 2; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI clock (OCTACLK) Switching Request */ + __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Core clock control register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 4; /*!< [3..0] CANFD Core clock (CANFDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Core clock (CANFDCLK) Switching Request */ + __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Core clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000078) I3C clock control register */ + + struct + { + __IOM uint8_t I3CCKSEL : 4; /*!< [3..0] I3C clock (I3CCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t I3CCKREQ : 1; /*!< [6..6] I3C clock (I3CCLK) Switching Request */ + __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) Switching Ready state flag */ + } I3CCKCR_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t MOSCSCR; /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register */ + + struct + { + __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select */ + uint8_t : 7; + } MOSCSCR_b; + }; + + union + { + __IOM uint8_t HOCOSCR; /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t HOCOSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select */ + uint8_t : 7; + } HOCOSCR_b; + }; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28[8]; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED29; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED30[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED31[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; + + union + { + __IOM uint32_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint32_t WDTRF : 1; /*!< [1..1] Watchdog Timer0 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint32_t SWRF : 1; /*!< [2..2] Software Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 1; + __IOM uint32_t CLU0RF : 1; /*!< [4..4] CPU0 Lockup Reset Detect Flag. NOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint32_t LM0RF : 1; /*!< [5..5] Local memory 0 error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + uint32_t : 4; + __IOM uint32_t BUSRF : 1; /*!< [10..10] Bus error Reset Detect Flag. NOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 3; + __IOM uint32_t CMRF : 1; /*!< [14..14] Common memory error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + uint32_t : 2; + __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint32_t : 3; + __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint32_t NWRF : 1; /*!< [22..22] Network Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 9; + } RSTSR1_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IOM uint8_t SYRACCR; /*!< (@ 0x000000CC) System Register Access Control Register */ + + struct + { + __IOM uint8_t BUSY : 1; /*!< [0..0] Access Ready monitor */ + uint8_t : 7; + } SYRACCR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[4]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t CRVSYSCR; /*!< (@ 0x000000F0) Clock Recovery System Control Register */ + + struct + { + __IOM uint8_t CRVEN : 1; /*!< [0..0] Clock Recovery Enable */ + uint8_t : 7; + } CRVSYSCR_b; + }; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41[7]; + + union + { + __IOM uint8_t PDCTRGD; /*!< (@ 0x00000110) Graphics Power Domain Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRGD_b; + }; + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; + __IM uint32_t RESERVED44[11]; + __IOM uint16_t PDRAMSCR0; /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0 */ + __IOM uint8_t PDRAMSCR1; /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1 */ + __IM uint8_t RESERVED45; + __IM uint32_t RESERVED46[155]; + + union + { + __IOM uint16_t VBRSABAR; /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary + * Address Register */ + + struct + { + __IOM uint16_t SABA : 16; /*!< [15..0] Security Attribute Boundary Address */ + } VBRSABAR_b; + }; + __IM uint16_t RESERVED47; + + union + { + __IOM uint16_t VBRPABARS; /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Secure Region */ + + struct + { + __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region */ + } VBRPABARS_b; + }; + __IM uint16_t RESERVED48; + + union + { + __IOM uint16_t VBRPABARNS; /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Non-secure Region */ + + struct + { + __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure + * Region */ + } VBRPABARNS_b; + }; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non-secure Attribute bit 9 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13 */ + uint32_t : 2; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22 */ + uint32_t : 1; + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26 */ + uint32_t : 5; + } CGFSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003C4) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + uint32_t : 28; + } RSTSAR_b; + }; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 00 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 03 */ + uint32_t : 4; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 08 */ + uint32_t : 7; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + uint32_t : 1; + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + uint32_t : 10; + } LPMSAR_b; + }; + + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Programmable Voltage Detection Security Attribution + * Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + uint32_t : 27; + } BBFSAR_b; + }; + __IM uint32_t RESERVED51; + + union + { + __IOM uint32_t PGCSAR; /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02 */ + uint32_t : 29; + } PGCSAR_b; + }; + __IM uint32_t RESERVED52; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 1; + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + uint32_t : 1; + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR_b; + }; + + union + { + __IOM uint32_t RSCSAR; /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register */ + + struct + { + __IOM uint32_t RSCSA0 : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 00 */ + __IOM uint32_t RSCSA1 : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 01 */ + __IOM uint32_t RSCSA2 : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 02 */ + __IOM uint32_t RSCSA3 : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 03 */ + __IOM uint32_t RSCSA4 : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 04 */ + __IOM uint32_t RSCSA5 : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 05 */ + __IOM uint32_t RSCSA6 : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 06 */ + __IOM uint32_t RSCSA7 : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 07 */ + __IOM uint32_t RSCSA8 : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 08 */ + __IOM uint32_t RSCSA9 : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 09 */ + __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10 */ + __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11 */ + __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12 */ + __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13 */ + __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14 */ + uint32_t : 1; + __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16 */ + __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17 */ + uint32_t : 14; + } RSCSAR_b; + }; + __IM uint32_t RESERVED53[4]; + __IM uint16_t RESERVED54; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FA) Protect Register for Secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the security + * and privilege setting registers. */ + __IOM uint16_t PRC5 : 1; /*!< [5..5] Enables writing to the registers related the reset control. */ + uint16_t : 2; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_b; + }; + __IM uint16_t RESERVED55; + + union + { + __IOM uint16_t PRCR_NS; /*!< (@ 0x000003FE) Protect Register for Non-secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the privilege + * setting registers. */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_NS_b; + }; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000402) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[2]; + __IM uint16_t RESERVED59; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + __IM uint32_t RESERVED61[380]; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000A00) Deep Standby Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t DCSSMODE : 1; /*!< [2..2] DCDC SSMODE */ + uint8_t : 1; + __IOM uint8_t SRKEEP : 1; /*!< [4..4] Standby RAM Retention */ + uint8_t : 1; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000A04) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 8; /*!< [7..0] Deep Software Wait Standby Time Setting Bit */ + } DPSWCR_b; + }; + __IM uint8_t RESERVED64; + __IM uint16_t RESERVED65; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ0-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ1-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ2-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ3-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ4-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ5-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ6-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ7-DS Pin Enable */ + } DPSIER0_b; + }; + __IM uint8_t RESERVED66; + __IM uint16_t RESERVED67; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ8-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ9-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ10-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ11-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ12-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ13-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ14-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ15-DS Pin Enable */ + } DPSIER1_b; + }; + __IM uint8_t RESERVED68; + __IM uint16_t RESERVED69; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DPVD1IE : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DPVD2IE : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + __IM uint8_t RESERVED70; + __IM uint16_t RESERVED71; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT0IE : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT1IE : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DIWDTIE : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable */ + } DPSIER3_b; + }; + __IM uint8_t RESERVED72; + __IM uint16_t RESERVED73; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ0-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ1-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ2-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ3-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ4-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ5-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ6-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ7-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + __IM uint8_t RESERVED74; + __IM uint16_t RESERVED75; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ8-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ9-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ10-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ11-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ12-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ13-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ14-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ15-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + __IM uint8_t RESERVED76; + __IM uint16_t RESERVED77; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DPVD1IF : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DPVD2IF : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + __IM uint8_t RESERVED78; + __IM uint16_t RESERVED79; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DULPT0IF : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DULPT1IF : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DIWDTIF : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag */ + } DPSIFR3_b; + }; + __IM uint8_t RESERVED80; + __IM uint16_t RESERVED81; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ0-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ1-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ2-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ3-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ4-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ5-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ6-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ7-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + __IM uint8_t RESERVED82; + __IM uint16_t RESERVED83; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ8EG : 1; /*!< [0..0] IRQ8-DS Pin Edge Select */ + __IOM uint8_t DIRQ9EG : 1; /*!< [1..1] IRQ9-DS Pin Edge Select */ + __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ10-DS Pin Edge Select */ + __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ11-DS Pin Edge Select */ + __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ12-DS Pin Edge Select */ + __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ13-DS Pin Edge Select */ + __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ14-DS Pin Edge Select */ + __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ15-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + __IM uint8_t RESERVED84; + __IM uint16_t RESERVED85; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DPVD1EG : 1; /*!< [0..0] PVD1 Edge Select */ + __IOM uint8_t DPVD2EG : 1; /*!< [1..1] PVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED86; + __IM uint16_t RESERVED87; + __IM uint32_t RESERVED88; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x00000A38) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + __IM uint8_t RESERVED89; + __IM uint16_t RESERVED90; + __IM uint32_t RESERVED91; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000A40) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD3RF : 1; /*!< [4..4] Voltage Monitor 3 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD4RF : 1; /*!< [5..5] Voltage Monitor 4 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD5RF : 1; /*!< [6..6] Voltage Monitor 5 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + } RSTSR0_b; + }; + __IM uint8_t RESERVED92; + __IM uint16_t RESERVED93; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000A44) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED94; + __IM uint16_t RESERVED95; + + union + { + __IOM uint8_t RSTSR3; /*!< (@ 0x00000A48) Reset Status Register 3 */ + + struct + { + uint8_t : 4; + __IOM uint8_t OCPRF : 1; /*!< [4..4] Overcurrent protection reset Detect Flag */ + uint8_t : 3; + } RSTSR3_b; + }; + __IM uint8_t RESERVED96; + __IM uint16_t RESERVED97; + __IM uint32_t RESERVED98; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t MODRV0 : 3; /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching */ + uint8_t : 2; + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + uint8_t : 1; + } MOMCR_b; + }; + __IM uint8_t RESERVED99; + __IM uint16_t RESERVED100; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000A54) Flash Write Erase Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programing and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + __IM uint8_t RESERVED101; + __IM uint16_t RESERVED102; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000A58) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000A58) Voltage Monitor 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage 1 Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + __IM uint8_t RESERVED103; + __IM uint16_t RESERVED104; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000A5C) Voltage Monitor 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage 2 Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + __IM uint8_t RESERVED105; + __IM uint16_t RESERVED106; + __IM uint32_t RESERVED107[4]; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + __IM uint8_t RESERVED108; + __IM uint16_t RESERVED109; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED110; + __IM uint16_t RESERVED111; + __IM uint32_t RESERVED112[3]; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Voltage Monitor Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + __IM uint8_t RESERVED113; + __IM uint16_t RESERVED114; + + union + { + __IOM uint8_t VBTBPCR1; /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop */ + uint8_t : 7; + } VBTBPCR1_b; + }; + __IM uint8_t RESERVED115; + __IM uint16_t RESERVED116; + __IM uint32_t RESERVED117; + + union + { + __IOM uint8_t LPSCR; /*!< (@ 0x00000A90) Low Power State Control Register */ + + struct + { + __IOM uint8_t LPMD : 4; /*!< [3..0] Low power mode setting bit */ + uint8_t : 4; + } LPSCR_b; + }; + __IM uint8_t RESERVED118; + __IM uint16_t RESERVED119; + __IM uint32_t RESERVED120; + + union + { + __IOM uint8_t SSCR1; /*!< (@ 0x00000A98) Software Standby Control Register 1 */ + + struct + { + __IOM uint8_t SS1FR : 1; /*!< [0..0] Software Standby 1 Fast Return */ + uint8_t : 7; + } SSCR1_b; + }; + __IM uint8_t RESERVED121; + __IM uint16_t RESERVED122; + __IM uint32_t RESERVED123[5]; + + union + { + __IOM uint8_t LVOCR; /*!< (@ 0x00000AB0) Low Power State Control Register */ + + struct + { + __IOM uint8_t LVO0E : 1; /*!< [0..0] Low Voltage Operation 0 Enable */ + __IOM uint8_t LVO1E : 1; /*!< [1..1] Low Voltage Operation 1 Enable */ + uint8_t : 6; + } LVOCR_b; + }; + __IM uint8_t RESERVED124; + __IM uint16_t RESERVED125; + __IM uint32_t RESERVED126[7]; + + union + { + __IOM uint8_t SYRSTMSK0; /*!< (@ 0x00000AD0) System Reset Mask Control Register0 */ + + struct + { + __IOM uint8_t IWDTMASK : 1; /*!< [0..0] Independent watchdog timer Reset Mask */ + __IOM uint8_t WDT0MASK : 1; /*!< [1..1] CPU0 Watchdog timer Reset Mask */ + __IOM uint8_t SWMASK : 1; /*!< [2..2] Software Reset Mask */ + uint8_t : 1; + __IOM uint8_t CLUP0MASK : 1; /*!< [4..4] CPU0 Lockup Reset Mask */ + __IOM uint8_t LM0MASK : 1; /*!< [5..5] Local memory 0 error Reset Mask */ + __IOM uint8_t CMMASK : 1; /*!< [6..6] Common memory error Reset Mask */ + __IOM uint8_t BUSMASK : 1; /*!< [7..7] BUS error Reset Mask */ + } SYRSTMSK0_b; + }; + __IM uint8_t RESERVED127; + __IM uint16_t RESERVED128; + + union + { + __IOM uint8_t SYRSTMSK1; /*!< (@ 0x00000AD4) System Reset Mask Control Register1 */ + + struct + { + uint8_t : 5; + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ + uint8_t : 1; + __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ + } SYRSTMSK1_b; + }; + __IM uint8_t RESERVED129; + __IM uint16_t RESERVED130; + + union + { + __IOM uint8_t SYRSTMSK2; /*!< (@ 0x00000AD8) System Reset Mask Control Register2 */ + + struct + { + __IOM uint8_t LVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask */ + __IOM uint8_t LVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask */ + __IOM uint8_t LVD3MASK : 1; /*!< [2..2] Voltage Monitor 3 Reset Mask */ + __IOM uint8_t LVD4MASK : 1; /*!< [3..3] Voltage Monitor 4 Reset Mask */ + __IOM uint8_t LVD5MASK : 1; /*!< [4..4] Voltage Monitor 5 Reset Mask */ + uint8_t : 3; + } SYRSTMSK2_b; + }; + __IM uint8_t RESERVED131; + __IM uint16_t RESERVED132; + __IM uint32_t RESERVED133[10]; + + union + { + __IOM uint8_t PLL1LDOCR; /*!< (@ 0x00000B04) PLL1-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL1LDOCR_b; + }; + __IM uint8_t RESERVED134; + __IM uint16_t RESERVED135; + + union + { + __IOM uint8_t PLL2LDOCR; /*!< (@ 0x00000B08) PLL2-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL2LDOCR_b; + }; + __IM uint8_t RESERVED136; + __IM uint16_t RESERVED137; + + union + { + __IOM uint8_t HOCOLDOCR; /*!< (@ 0x00000B0C) HOCO-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } HOCOLDOCR_b; + }; + __IM uint8_t RESERVED138; + __IM uint16_t RESERVED139; + __IM uint32_t RESERVED140[4]; + + union + { + __IOM uint8_t LVD1FCR; /*!< (@ 0x00000B20) Voltage Monitor % Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD1FCR_b; + }; + __IM uint8_t RESERVED141; + __IM uint16_t RESERVED142; + + union + { + __IOM uint8_t LVD2FCR; /*!< (@ 0x00000B24) Voltage Monitor % Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD2FCR_b; + }; + __IM uint8_t RESERVED143; + __IM uint16_t RESERVED144; + __IM uint32_t RESERVED145[54]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000C00) Sub-clock oscillator control register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub Clock Oscillator Drive Capability Switching */ + uint8_t : 4; + __IOM uint8_t SOSEL : 1; /*!< [6..6] Sub Clock Oscillator Switching */ + uint8_t : 1; + } SOMCR_b; + }; + __IM uint16_t RESERVED146; + __IM uint32_t RESERVED147[15]; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x00000C40) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED148; + __IM uint16_t RESERVED149; + __IM uint8_t RESERVED150; + + union + { + __IOM uint8_t VBTBPCR2; /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2 */ + + struct + { + __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select */ + uint8_t : 1; + __IOM uint8_t VDETE : 1; /*!< [4..4] Voltage drop detection enable */ + uint8_t : 3; + } VBTBPCR2_b; + }; + + union + { + __IOM uint8_t VBTBPSR; /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register */ + + struct + { + __IOM uint8_t VBPORF : 1; /*!< [0..0] VBATT_POR Flag */ + uint8_t : 3; + __IOM uint8_t VBPORM : 1; /*!< [4..4] VBATT_POR Monitor */ + __IOM uint8_t BPWSWM : 1; /*!< [5..5] Battery Power Supply Switch Status Monitor */ + uint8_t : 2; + } VBTBPSR_b; + }; + __IM uint8_t RESERVED151; + + union + { + __IOM uint8_t VBTADSR; /*!< (@ 0x00000C48) VBATT Tamper detection Status Register */ + + struct + { + __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0 */ + __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1 */ + __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2 */ + uint8_t : 5; + } VBTADSR_b; + }; + + union + { + __IOM uint8_t VBTADCR1; /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1 */ + + struct + { + __IOM uint8_t VBTADIE0 : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0 */ + __IOM uint8_t VBTADIE1 : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1 */ + __IOM uint8_t VBTADIE2 : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2 */ + uint8_t : 1; + __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0 */ + __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1 */ + __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2 */ + uint8_t : 1; + } VBTADCR1_b; + }; + + union + { + __IOM uint8_t VBTADCR2; /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2 */ + + struct + { + __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0 */ + __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1 */ + __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2 */ + uint8_t : 5; + } VBTADCR2_b; + }; + __IM uint8_t RESERVED152; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x00000C4C) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTICTLR2; /*!< (@ 0x00000C4D) VBATT Input Control Register 2 */ + + struct + { + __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable */ + __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable */ + __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable */ + uint8_t : 1; + __IOM uint8_t VCH0EG : 1; /*!< [4..4] VBATT CH0 Input Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [5..5] VBATT CH1 Input Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [6..6] VBATT CH2 Input Edge Select */ + uint8_t : 1; + } VBTICTLR2_b; + }; + + union + { + __IOM uint8_t VBTIMONR; /*!< (@ 0x00000C4E) VBATT Input Monitor Register */ + + struct + { + __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor */ + __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor */ + __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor */ + uint8_t : 5; + } VBTIMONR_b; + }; + __IM uint8_t RESERVED153; + __IM uint32_t RESERVED154[44]; + + union + { + __IOM uint8_t VBTBKR0; /*!< (@ 0x00000D00) VBATT Backup Register 0 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR0_b; + }; + + union + { + __IOM uint8_t VBTBKR1; /*!< (@ 0x00000D01) VBATT Backup Register 1 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR1_b; + }; + + union + { + __IOM uint8_t VBTBKR2; /*!< (@ 0x00000D02) VBATT Backup Register 2 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR2_b; + }; + + union + { + __IOM uint8_t VBTBKR3; /*!< (@ 0x00000D03) VBATT Backup Register 3 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR3_b; + }; + + union + { + __IOM uint8_t VBTBKR4; /*!< (@ 0x00000D04) VBATT Backup Register 4 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR4_b; + }; + + union + { + __IOM uint8_t VBTBKR5; /*!< (@ 0x00000D05) VBATT Backup Register 5 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR5_b; + }; + + union + { + __IOM uint8_t VBTBKR6; /*!< (@ 0x00000D06) VBATT Backup Register 6 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR6_b; + }; + + union + { + __IOM uint8_t VBTBKR7; /*!< (@ 0x00000D07) VBATT Backup Register 7 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR7_b; + }; + + union + { + __IOM uint8_t VBTBKR8; /*!< (@ 0x00000D08) VBATT Backup Register 8 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR8_b; + }; + + union + { + __IOM uint8_t VBTBKR9; /*!< (@ 0x00000D09) VBATT Backup Register 9 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR9_b; + }; + + union + { + __IOM uint8_t VBTBKR10; /*!< (@ 0x00000D0A) VBATT Backup Register 10 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR10_b; + }; + + union + { + __IOM uint8_t VBTBKR11; /*!< (@ 0x00000D0B) VBATT Backup Register 11 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR11_b; + }; + + union + { + __IOM uint8_t VBTBKR12; /*!< (@ 0x00000D0C) VBATT Backup Register 12 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR12_b; + }; + + union + { + __IOM uint8_t VBTBKR13; /*!< (@ 0x00000D0D) VBATT Backup Register 13 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR13_b; + }; + + union + { + __IOM uint8_t VBTBKR14; /*!< (@ 0x00000D0E) VBATT Backup Register 14 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR14_b; + }; + + union + { + __IOM uint8_t VBTBKR15; /*!< (@ 0x00000D0F) VBATT Backup Register 15 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR15_b; + }; + + union + { + __IOM uint8_t VBTBKR16; /*!< (@ 0x00000D10) VBATT Backup Register 16 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR16_b; + }; + + union + { + __IOM uint8_t VBTBKR17; /*!< (@ 0x00000D11) VBATT Backup Register 17 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR17_b; + }; + + union + { + __IOM uint8_t VBTBKR18; /*!< (@ 0x00000D12) VBATT Backup Register 18 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR18_b; + }; + + union + { + __IOM uint8_t VBTBKR19; /*!< (@ 0x00000D13) VBATT Backup Register 19 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR19_b; + }; + + union + { + __IOM uint8_t VBTBKR20; /*!< (@ 0x00000D14) VBATT Backup Register 20 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR20_b; + }; + + union + { + __IOM uint8_t VBTBKR21; /*!< (@ 0x00000D15) VBATT Backup Register 21 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR21_b; + }; + + union + { + __IOM uint8_t VBTBKR22; /*!< (@ 0x00000D16) VBATT Backup Register 22 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR22_b; + }; + + union + { + __IOM uint8_t VBTBKR23; /*!< (@ 0x00000D17) VBATT Backup Register 23 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR23_b; + }; + + union + { + __IOM uint8_t VBTBKR24; /*!< (@ 0x00000D18) VBATT Backup Register 24 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR24_b; + }; + + union + { + __IOM uint8_t VBTBKR25; /*!< (@ 0x00000D19) VBATT Backup Register 25 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR25_b; + }; + + union + { + __IOM uint8_t VBTBKR26; /*!< (@ 0x00000D1A) VBATT Backup Register 26 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR26_b; + }; + + union + { + __IOM uint8_t VBTBKR27; /*!< (@ 0x00000D1B) VBATT Backup Register 27 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR27_b; + }; + + union + { + __IOM uint8_t VBTBKR28; /*!< (@ 0x00000D1C) VBATT Backup Register 28 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR28_b; + }; + + union + { + __IOM uint8_t VBTBKR29; /*!< (@ 0x00000D1D) VBATT Backup Register 29 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR29_b; + }; + + union + { + __IOM uint8_t VBTBKR30; /*!< (@ 0x00000D1E) VBATT Backup Register 30 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR30_b; + }; + + union + { + __IOM uint8_t VBTBKR31; /*!< (@ 0x00000D1F) VBATT Backup Register 31 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR31_b; + }; + + union + { + __IOM uint8_t VBTBKR32; /*!< (@ 0x00000D20) VBATT Backup Register 32 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR32_b; + }; + + union + { + __IOM uint8_t VBTBKR33; /*!< (@ 0x00000D21) VBATT Backup Register 33 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR33_b; + }; + + union + { + __IOM uint8_t VBTBKR34; /*!< (@ 0x00000D22) VBATT Backup Register 34 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR34_b; + }; + + union + { + __IOM uint8_t VBTBKR35; /*!< (@ 0x00000D23) VBATT Backup Register 35 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR35_b; + }; + + union + { + __IOM uint8_t VBTBKR36; /*!< (@ 0x00000D24) VBATT Backup Register 36 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR36_b; + }; + + union + { + __IOM uint8_t VBTBKR37; /*!< (@ 0x00000D25) VBATT Backup Register 37 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR37_b; + }; + + union + { + __IOM uint8_t VBTBKR38; /*!< (@ 0x00000D26) VBATT Backup Register 38 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR38_b; + }; + + union + { + __IOM uint8_t VBTBKR39; /*!< (@ 0x00000D27) VBATT Backup Register 39 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR39_b; + }; + + union + { + __IOM uint8_t VBTBKR40; /*!< (@ 0x00000D28) VBATT Backup Register 40 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR40_b; + }; + + union + { + __IOM uint8_t VBTBKR41; /*!< (@ 0x00000D29) VBATT Backup Register 41 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR41_b; + }; + + union + { + __IOM uint8_t VBTBKR42; /*!< (@ 0x00000D2A) VBATT Backup Register 42 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR42_b; + }; + + union + { + __IOM uint8_t VBTBKR43; /*!< (@ 0x00000D2B) VBATT Backup Register 43 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR43_b; + }; + + union + { + __IOM uint8_t VBTBKR44; /*!< (@ 0x00000D2C) VBATT Backup Register 44 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR44_b; + }; + + union + { + __IOM uint8_t VBTBKR45; /*!< (@ 0x00000D2D) VBATT Backup Register 45 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR45_b; + }; + + union + { + __IOM uint8_t VBTBKR46; /*!< (@ 0x00000D2E) VBATT Backup Register 46 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR46_b; + }; + + union + { + __IOM uint8_t VBTBKR47; /*!< (@ 0x00000D2F) VBATT Backup Register 47 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR47_b; + }; + + union + { + __IOM uint8_t VBTBKR48; /*!< (@ 0x00000D30) VBATT Backup Register 48 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR48_b; + }; + + union + { + __IOM uint8_t VBTBKR49; /*!< (@ 0x00000D31) VBATT Backup Register 49 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR49_b; + }; + + union + { + __IOM uint8_t VBTBKR50; /*!< (@ 0x00000D32) VBATT Backup Register 50 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR50_b; + }; + + union + { + __IOM uint8_t VBTBKR51; /*!< (@ 0x00000D33) VBATT Backup Register 51 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR51_b; + }; + + union + { + __IOM uint8_t VBTBKR52; /*!< (@ 0x00000D34) VBATT Backup Register 52 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR52_b; + }; + + union + { + __IOM uint8_t VBTBKR53; /*!< (@ 0x00000D35) VBATT Backup Register 53 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR53_b; + }; + + union + { + __IOM uint8_t VBTBKR54; /*!< (@ 0x00000D36) VBATT Backup Register 54 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR54_b; + }; + + union + { + __IOM uint8_t VBTBKR55; /*!< (@ 0x00000D37) VBATT Backup Register 55 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR55_b; + }; + + union + { + __IOM uint8_t VBTBKR56; /*!< (@ 0x00000D38) VBATT Backup Register 56 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR56_b; + }; + + union + { + __IOM uint8_t VBTBKR57; /*!< (@ 0x00000D39) VBATT Backup Register 57 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR57_b; + }; + + union + { + __IOM uint8_t VBTBKR58; /*!< (@ 0x00000D3A) VBATT Backup Register 58 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR58_b; + }; + + union + { + __IOM uint8_t VBTBKR59; /*!< (@ 0x00000D3B) VBATT Backup Register 59 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR59_b; + }; + + union + { + __IOM uint8_t VBTBKR60; /*!< (@ 0x00000D3C) VBATT Backup Register 60 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR60_b; + }; + + union + { + __IOM uint8_t VBTBKR61; /*!< (@ 0x00000D3D) VBATT Backup Register 61 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR61_b; + }; + + union + { + __IOM uint8_t VBTBKR62; /*!< (@ 0x00000D3E) VBATT Backup Register 62 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR62_b; + }; + + union + { + __IOM uint8_t VBTBKR63; /*!< (@ 0x00000D3F) VBATT Backup Register 63 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR63_b; + }; + + union + { + __IOM uint8_t VBTBKR64; /*!< (@ 0x00000D40) VBATT Backup Register 64 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR64_b; + }; + + union + { + __IOM uint8_t VBTBKR65; /*!< (@ 0x00000D41) VBATT Backup Register 65 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR65_b; + }; + + union + { + __IOM uint8_t VBTBKR66; /*!< (@ 0x00000D42) VBATT Backup Register 66 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR66_b; + }; + + union + { + __IOM uint8_t VBTBKR67; /*!< (@ 0x00000D43) VBATT Backup Register 67 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR67_b; + }; + + union + { + __IOM uint8_t VBTBKR68; /*!< (@ 0x00000D44) VBATT Backup Register 68 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR68_b; + }; + + union + { + __IOM uint8_t VBTBKR69; /*!< (@ 0x00000D45) VBATT Backup Register 69 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR69_b; + }; + + union + { + __IOM uint8_t VBTBKR70; /*!< (@ 0x00000D46) VBATT Backup Register 70 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR70_b; + }; + + union + { + __IOM uint8_t VBTBKR71; /*!< (@ 0x00000D47) VBATT Backup Register 71 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR71_b; + }; + + union + { + __IOM uint8_t VBTBKR72; /*!< (@ 0x00000D48) VBATT Backup Register 72 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR72_b; + }; + + union + { + __IOM uint8_t VBTBKR73; /*!< (@ 0x00000D49) VBATT Backup Register 73 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR73_b; + }; + + union + { + __IOM uint8_t VBTBKR74; /*!< (@ 0x00000D4A) VBATT Backup Register 74 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR74_b; + }; + + union + { + __IOM uint8_t VBTBKR75; /*!< (@ 0x00000D4B) VBATT Backup Register 75 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR75_b; + }; + + union + { + __IOM uint8_t VBTBKR76; /*!< (@ 0x00000D4C) VBATT Backup Register 76 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR76_b; + }; + + union + { + __IOM uint8_t VBTBKR77; /*!< (@ 0x00000D4D) VBATT Backup Register 77 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR77_b; + }; + + union + { + __IOM uint8_t VBTBKR78; /*!< (@ 0x00000D4E) VBATT Backup Register 78 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR78_b; + }; + + union + { + __IOM uint8_t VBTBKR79; /*!< (@ 0x00000D4F) VBATT Backup Register 79 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR79_b; + }; + + union + { + __IOM uint8_t VBTBKR80; /*!< (@ 0x00000D50) VBATT Backup Register 80 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR80_b; + }; + + union + { + __IOM uint8_t VBTBKR81; /*!< (@ 0x00000D51) VBATT Backup Register 81 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR81_b; + }; + + union + { + __IOM uint8_t VBTBKR82; /*!< (@ 0x00000D52) VBATT Backup Register 82 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR82_b; + }; + + union + { + __IOM uint8_t VBTBKR83; /*!< (@ 0x00000D53) VBATT Backup Register 83 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR83_b; + }; + + union + { + __IOM uint8_t VBTBKR84; /*!< (@ 0x00000D54) VBATT Backup Register 84 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR84_b; + }; + + union + { + __IOM uint8_t VBTBKR85; /*!< (@ 0x00000D55) VBATT Backup Register 85 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR85_b; + }; + + union + { + __IOM uint8_t VBTBKR86; /*!< (@ 0x00000D56) VBATT Backup Register 86 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR86_b; + }; + + union + { + __IOM uint8_t VBTBKR87; /*!< (@ 0x00000D57) VBATT Backup Register 87 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR87_b; + }; + + union + { + __IOM uint8_t VBTBKR88; /*!< (@ 0x00000D58) VBATT Backup Register 88 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR88_b; + }; + + union + { + __IOM uint8_t VBTBKR89; /*!< (@ 0x00000D59) VBATT Backup Register 89 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR89_b; + }; + + union + { + __IOM uint8_t VBTBKR90; /*!< (@ 0x00000D5A) VBATT Backup Register 90 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR90_b; + }; + + union + { + __IOM uint8_t VBTBKR91; /*!< (@ 0x00000D5B) VBATT Backup Register 91 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR91_b; + }; + + union + { + __IOM uint8_t VBTBKR92; /*!< (@ 0x00000D5C) VBATT Backup Register 92 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR92_b; + }; + + union + { + __IOM uint8_t VBTBKR93; /*!< (@ 0x00000D5D) VBATT Backup Register 93 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR93_b; + }; + + union + { + __IOM uint8_t VBTBKR94; /*!< (@ 0x00000D5E) VBATT Backup Register 94 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR94_b; + }; + + union + { + __IOM uint8_t VBTBKR95; /*!< (@ 0x00000D5F) VBATT Backup Register 95 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR95_b; + }; + + union + { + __IOM uint8_t VBTBKR96; /*!< (@ 0x00000D60) VBATT Backup Register 96 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR96_b; + }; + + union + { + __IOM uint8_t VBTBKR97; /*!< (@ 0x00000D61) VBATT Backup Register 97 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR97_b; + }; + + union + { + __IOM uint8_t VBTBKR98; /*!< (@ 0x00000D62) VBATT Backup Register 98 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR98_b; + }; + + union + { + __IOM uint8_t VBTBKR99; /*!< (@ 0x00000D63) VBATT Backup Register 99 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR99_b; + }; + + union + { + __IOM uint8_t VBTBKR100; /*!< (@ 0x00000D64) VBATT Backup Register 100 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR100_b; + }; + + union + { + __IOM uint8_t VBTBKR101; /*!< (@ 0x00000D65) VBATT Backup Register 101 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR101_b; + }; + + union + { + __IOM uint8_t VBTBKR102; /*!< (@ 0x00000D66) VBATT Backup Register 102 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR102_b; + }; + + union + { + __IOM uint8_t VBTBKR103; /*!< (@ 0x00000D67) VBATT Backup Register 103 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR103_b; + }; + + union + { + __IOM uint8_t VBTBKR104; /*!< (@ 0x00000D68) VBATT Backup Register 104 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR104_b; + }; + + union + { + __IOM uint8_t VBTBKR105; /*!< (@ 0x00000D69) VBATT Backup Register 105 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR105_b; + }; + + union + { + __IOM uint8_t VBTBKR106; /*!< (@ 0x00000D6A) VBATT Backup Register 106 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR106_b; + }; + + union + { + __IOM uint8_t VBTBKR107; /*!< (@ 0x00000D6B) VBATT Backup Register 107 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR107_b; + }; + + union + { + __IOM uint8_t VBTBKR108; /*!< (@ 0x00000D6C) VBATT Backup Register 108 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR108_b; + }; + + union + { + __IOM uint8_t VBTBKR109; /*!< (@ 0x00000D6D) VBATT Backup Register 109 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR109_b; + }; + + union + { + __IOM uint8_t VBTBKR110; /*!< (@ 0x00000D6E) VBATT Backup Register 110 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR110_b; + }; + + union + { + __IOM uint8_t VBTBKR111; /*!< (@ 0x00000D6F) VBATT Backup Register 111 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR111_b; + }; + + union + { + __IOM uint8_t VBTBKR112; /*!< (@ 0x00000D70) VBATT Backup Register 112 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR112_b; + }; + + union + { + __IOM uint8_t VBTBKR113; /*!< (@ 0x00000D71) VBATT Backup Register 113 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR113_b; + }; + + union + { + __IOM uint8_t VBTBKR114; /*!< (@ 0x00000D72) VBATT Backup Register 114 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR114_b; + }; + + union + { + __IOM uint8_t VBTBKR115; /*!< (@ 0x00000D73) VBATT Backup Register 115 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR115_b; + }; + + union + { + __IOM uint8_t VBTBKR116; /*!< (@ 0x00000D74) VBATT Backup Register 116 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR116_b; + }; + + union + { + __IOM uint8_t VBTBKR117; /*!< (@ 0x00000D75) VBATT Backup Register 117 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR117_b; + }; + + union + { + __IOM uint8_t VBTBKR118; /*!< (@ 0x00000D76) VBATT Backup Register 118 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR118_b; + }; + + union + { + __IOM uint8_t VBTBKR119; /*!< (@ 0x00000D77) VBATT Backup Register 119 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR119_b; + }; + + union + { + __IOM uint8_t VBTBKR120; /*!< (@ 0x00000D78) VBATT Backup Register 120 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR120_b; + }; + + union + { + __IOM uint8_t VBTBKR121; /*!< (@ 0x00000D79) VBATT Backup Register 121 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR121_b; + }; + + union + { + __IOM uint8_t VBTBKR122; /*!< (@ 0x00000D7A) VBATT Backup Register 122 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR122_b; + }; + + union + { + __IOM uint8_t VBTBKR123; /*!< (@ 0x00000D7B) VBATT Backup Register 123 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR123_b; + }; + + union + { + __IOM uint8_t VBTBKR124; /*!< (@ 0x00000D7C) VBATT Backup Register 124 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR124_b; + }; + + union + { + __IOM uint8_t VBTBKR125; /*!< (@ 0x00000D7D) VBATT Backup Register 125 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR125_b; + }; + + union + { + __IOM uint8_t VBTBKR126; /*!< (@ 0x00000D7E) VBATT Backup Register 126 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR126_b; + }; + + union + { + __IOM uint8_t VBTBKR127; /*!< (@ 0x00000D7F) VBATT Backup Register 127 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR127_b; + }; +} R_SYSTEM_Type; /*!< Size = 3456 (0xd80) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x4011B17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x40235000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40202600) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ + uint32_t : 17; + } ICUSARF_b; + }; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ + __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ + __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ + uint32_t : 25; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ + + struct + { + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ + uint32_t : 24; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED10[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED11[126]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn + * and ELCSRn */ + uint32_t : 31; + } TEVTRCR_b; + }; +} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC_B) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC_B Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */ + __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */ + + struct + { + __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */ + uint8_t : 7; + } DOSR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */ + + struct + { + __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */ + uint8_t : 7; + } DOSCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */ + __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */ + __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */ +} R_DOC_B_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI_B0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI_B0 Structure */ +{ + union + { + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint8_t RDR_BY; /*!< (@ 0x00000000) Receive Data Register (byte access) */ + + struct + { + __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data */ + } RDR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 2; + __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */ + uint32_t : 19; + } TDR_b; + }; + + union + { + __IOM uint8_t TDR_BY; /*!< (@ 0x00000004) Transmit Data Register (byte access) */ + + struct + { + __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data */ + } TDR_BY_b; + }; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 1; + __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit. */ + uint32_t : 4; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + + union + { + __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */ + + struct + { + __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */ + uint8_t : 3; + __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */ + uint8_t : 3; + } CESR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */ + + struct + { + __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint32_t : 1; + __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */ + __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + uint32_t : 1; + __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */ + __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */ + uint32_t : 2; + __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */ + __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */ + uint32_t : 2; + __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */ + __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */ + __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */ + uint32_t : 5; + } MCR_b; + }; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + + union + { + __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */ + + struct + { + __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */ + uint32_t : 6; + __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */ + __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */ + __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */ + __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */ + __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */ + __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */ + __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */ + uint32_t : 2; + __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */ + __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */ + __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */ + uint32_t : 1; + __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */ + uint32_t : 6; + } XCR0_b; + }; + + union + { + __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */ + + struct + { + __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */ + uint32_t : 3; + __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */ + __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */ + uint32_t : 2; + __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */ + __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */ + __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */ + } XCR1_b; + }; + + union + { + __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */ + + struct + { + __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */ + __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */ + __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */ + } XCR2_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */ + __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */ + __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + + union + { + __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */ + + struct + { + __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */ + __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */ + __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */ + uint32_t : 1; + __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */ + uint32_t : 1; + __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */ + uint32_t : 25; + } MSR_b; + }; + + union + { + __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */ + + struct + { + __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */ + __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */ + uint32_t : 6; + __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */ + __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */ + __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */ + __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */ + __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */ + __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */ + __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */ + __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */ + __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */ + __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */ + } XSR0_b; + }; + + union + { + __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */ + + struct + { + __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */ + uint32_t : 16; + } XSR1_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */ + __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */ + __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */ + uint32_t : 31; + } FFCLR_b; + }; + + union + { + __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */ + + struct + { + __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */ + __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */ + __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */ + uint32_t : 1; + __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */ + uint32_t : 27; + } MFCLR_b; + }; + + union + { + __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */ + __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */ + __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */ + __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */ + __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */ + __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */ + __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */ + __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */ + uint32_t : 16; + } XFCLR_b; + }; +} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI_B0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI_B0 Structure */ +{ + __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */ + + union + { + __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */ + + struct + { + __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */ + uint32_t : 5; + __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */ + uint32_t : 5; + __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */ + uint32_t : 5; + __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */ + uint32_t : 5; + } SPDECR_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */ + + struct + { + __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint32_t : 1; + __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */ + __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */ + __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */ + __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */ + __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */ + uint32_t : 2; + __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */ + __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */ + uint32_t : 10; + } SPCR2_b; + }; + + union + { + __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */ + + struct + { + __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */ + __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */ + __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */ + __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */ + uint32_t : 4; + __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */ + uint32_t : 8; + __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */ + uint32_t : 5; + } SPCR3_b; + }; + + union + { + __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD0_b; + }; + + union + { + __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD1_b; + }; + + union + { + __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD2_b; + }; + + union + { + __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD3_b; + }; + + union + { + __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD4_b; + }; + + union + { + __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD5_b; + }; + + union + { + __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD6_b; + }; + + union + { + __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD7_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */ + + struct + { + __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint32_t : 2; + __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */ + __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */ + uint32_t : 3; + __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */ + uint32_t : 22; + } SPDCR_b; + }; + + union + { + __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */ + + struct + { + __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint32_t : 6; + __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint32_t : 22; + } SPDCR2_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */ + uint32_t : 1; + __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */ + uint32_t : 8; + __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */ + __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */ + __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */ + __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */ + __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */ + __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */ + __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */ + + struct + { + __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint32_t : 29; + } SPTFSR_b; + }; + + union + { + __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */ + + struct + { + __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint32_t : 29; + } SPRFSR_b; + }; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */ + + struct + { + uint32_t : 23; + __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */ + __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */ + uint32_t : 1; + __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */ + __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */ + __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */ + __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */ + __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */ + __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */ + + struct + { + __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */ + uint32_t : 31; + } SPFCR_b; + }; +} R_SPI_B0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40351000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief eXpanded SPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x40268000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration register */ + + struct + { + __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 3; + __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration register */ + + struct + { + __IOM uint32_t ARBMD : 2; /*!< [1..0] Channel arbitration mode */ + uint32_t : 2; + __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable */ + uint32_t : 10; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFGCH[2]; /*!< (@ 0x00000008) xSPI Bridge Map Configuration register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 7; + __IOM uint32_t CMBTIM : 8; /*!< [31..24] Combination timer */ + } BMCFGCH_b[2]; + }; + __IOM R_XSPI0_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers */ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1] */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + + union + { + __IOM uint32_t ABMCFG; /*!< (@ 0x00000058) xSPI AXI Bridge Map Config */ + + struct + { + __IOM uint32_t ODRMD : 2; /*!< [1..0] AXI Transfer Ordering Mode */ + uint32_t : 14; + __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select */ + } ABMCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control register 0 */ + + struct + { + __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable */ + __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable */ + __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable */ + __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable */ + uint32_t : 24; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0 */ + __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1 */ + __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0 */ + __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1 */ + uint32_t : 20; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTLCH[2]; /*!< (@ 0x00000068) xSPI Command Map Control register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTLCH_b[2]; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED2; + __IOM R_XSPI0_CDBUF_Type CDBUF[4]; /*!< (@ 0x00000080) xSPI BUF register */ + __IM uint32_t RESERVED3[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave 0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave 1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_XSPI0_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register */ + __IM uint32_t RESERVED5[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status register */ + + struct + { + __IM uint32_t MEMACCCH0 : 1; /*!< [0..0] Memory access ongoing from ch0 */ + __IM uint32_t MEMACCCH1 : 1; /*!< [1..1] Memory access ongoing from ch1 */ + uint32_t : 2; + __IM uint32_t PBUFNECH0 : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0 */ + __IM uint32_t PBUFNECH1 : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1 */ + __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0 */ + __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1 */ + uint32_t : 8; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status register */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOFCH0 : 1; /*!< [16..16] Bridge Buffer overflow for CH0 */ + __IM uint32_t BRGOFCH1 : 1; /*!< [17..17] Bridge Buffer overflow for CH1 */ + __IM uint32_t BRGUFCH0 : 1; /*!< [18..18] Bridge Buffer underflow for CH0 */ + __IM uint32_t BRGUFCH1 : 1; /*!< [19..19] Bridge Buffer underflow for CH1 */ + __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0 */ + __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1 */ + uint32_t : 6; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFCH0C : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear */ + __OM uint32_t BRGOFCH1C : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear */ + __OM uint32_t BRGUFCH0C : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear */ + __OM uint32_t BRGUFCH1C : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear */ + __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear */ + __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear */ + uint32_t : 6; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFCH0E : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable */ + __IOM uint32_t BRGOFCH1E : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable */ + __IOM uint32_t BRGUFCH0E : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable */ + __IOM uint32_t BRGUFCH1E : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable */ + __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable */ + __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable */ + uint32_t : 6; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D-PHY Controller Top (R_MIPI_PHY) + */ + +typedef struct /*!< (@ 0x40346C00) R_MIPI_PHY Structure */ +{ + union + { + __IOM uint32_t DPHYREFCR; /*!< (@ 0x00000000) D-PHY Reference Clock Setting Register */ + + struct + { + __IOM uint32_t RFREQ : 8; /*!< [7..0] Reference Clock Frequency Setting */ + uint32_t : 24; + } DPHYREFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLFCR; /*!< (@ 0x00000004) D-PHY PLL Frequency Control Register */ + + struct + { + __IOM uint32_t IDIV : 2; /*!< [1..0] D-PHY PLL Input Frequency Division Ratio Select */ + uint32_t : 6; + __IOM uint32_t NFMUL : 2; /*!< [9..8] D-PHY PLL Frequency Multiplication Factor Select (Fractional + * Part) */ + uint32_t : 2; + __IOM uint32_t PMUL : 2; /*!< [13..12] D-PHY PLL Output Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t NMUL : 9; /*!< [24..16] D-PHY PLL Frequency Multiplication Factor Select (Integer + * Part) */ + uint32_t : 7; + } DPHYPLFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLOCR; /*!< (@ 0x00000008) D-PHY PLL Operation Control Register */ + + struct + { + __IOM uint32_t PLLSTP : 1; /*!< [0..0] D-PHY PLL Operation Control */ + uint32_t : 31; + } DPHYPLOCR_b; + }; + + union + { + __IOM uint32_t DPHYESCCR; /*!< (@ 0x0000000C) D-PHY Escape Mode Clock Control Register */ + + struct + { + __IOM uint32_t ESCDIV : 5; /*!< [4..0] Escape Mode Transfer Clock Division Ratio */ + uint32_t : 27; + } DPHYESCCR_b; + }; + + union + { + __IOM uint32_t DPHYPWRCR; /*!< (@ 0x00000010) D-PHY Power Supplying Control Register */ + + struct + { + __IOM uint32_t PWRSEN : 1; /*!< [0..0] D-PHY Power Supplying Control */ + uint32_t : 31; + } DPHYPWRCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IM uint32_t DPHYSFR; /*!< (@ 0x0000001C) D-PHY Status Flag Register */ + + struct + { + __IM uint32_t PWRSF : 1; /*!< [0..0] D-PHY LDO Power-on Status Flag */ + uint32_t : 7; + __IM uint32_t PLLSF : 1; /*!< [8..8] D-PHY PLL Oscillation Stabilization Flag */ + uint32_t : 23; + } DPHYSFR_b; + }; + + union + { + __IOM uint32_t DPHYOCR; /*!< (@ 0x00000020) D-PHY Operation Control Register */ + + struct + { + __IOM uint32_t DPHYEN : 1; /*!< [0..0] D-PHY Operation Control */ + uint32_t : 31; + } DPHYOCR_b; + }; + + union + { + __IOM uint32_t DPHYTIM1; /*!< (@ 0x00000024) D-PHY Timing Control Register 1 */ + + struct + { + __IOM uint32_t TINIT : 19; /*!< [18..0] D-PHY T_INIT Parameter Setting */ + uint32_t : 13; + } DPHYTIM1_b; + }; + + union + { + __IOM uint32_t DPHYTIM2; /*!< (@ 0x00000028) D-PHY Timing Control Register 2 */ + + struct + { + __IOM uint32_t TCLKPREP : 8; /*!< [7..0] D-PHY T_CLK_PREPARE Parameter Setting */ + __IOM uint32_t TCLKSETT : 8; /*!< [15..8] D-PHY T_CLK_SETTLE Parameter Setting */ + __IOM uint32_t TCLKMISS : 8; /*!< [23..16] D-PHY T_CLK_MISS Parameter Setting */ + uint32_t : 8; + } DPHYTIM2_b; + }; + + union + { + __IOM uint32_t DPHYTIM3; /*!< (@ 0x0000002C) D-PHY Timing Control Register 3 */ + + struct + { + __IOM uint32_t THSPREP : 8; /*!< [7..0] D-PHY T_THS_PREPARE Parameter Setting */ + __IOM uint32_t THSSETT : 8; /*!< [15..8] D-PHY T_THS_SETTLE Parameter Setting */ + uint32_t : 16; + } DPHYTIM3_b; + }; + + union + { + __IOM uint32_t DPHYTIM4; /*!< (@ 0x00000030) D-PHY Timing Control Register 4 */ + + struct + { + __IOM uint32_t TCLKZERO : 8; /*!< [7..0] D-PHY T_CLK_ZERO Parameter Setting */ + __IOM uint32_t TCLKPRE : 8; /*!< [15..8] D-PHY T_TCLK_PRE Parameter Setting */ + __IOM uint32_t TCLKPOST : 8; /*!< [23..16] D-PHY T_TCLK_POST Parameter Setting */ + __IOM uint32_t TCLKTRL : 8; /*!< [31..24] D-PHY T_TCLK_TRAIL Parameter Setting */ + } DPHYTIM4_b; + }; + + union + { + __IOM uint32_t DPHYTIM5; /*!< (@ 0x00000034) D-PHY Timing Control Register 5 */ + + struct + { + __IOM uint32_t THSZERO : 8; /*!< [7..0] D-PHY T_THS_ZERO Parameter Setting */ + __IOM uint32_t THSTRL : 8; /*!< [15..8] D-PHY T_THS_TRAIL Parameter Setting */ + __IOM uint32_t THSEXIT : 8; /*!< [23..16] D-PHY T_THS_EXIT Parameter Setting */ + uint32_t : 8; + } DPHYTIM5_b; + }; + + union + { + __IOM uint32_t DPHYTIM6; /*!< (@ 0x00000038) D-PHY Timing Control Register 6 */ + + struct + { + __IOM uint32_t TLPX : 8; /*!< [7..0] D-PHY T_TLPX Parameter Setting */ + uint32_t : 24; + } DPHYTIM6_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DPHYMDC; /*!< (@ 0x00000048) D-PHY Mode Control Register */ + + struct + { + __IOM uint32_t MASTEREN : 1; /*!< [0..0] D-PHY Master/Slave Select */ + uint32_t : 31; + } DPHYMDC_b; + }; +} R_MIPI_PHY_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capture Engine Unit (R_CEU) + */ + +typedef struct /*!< (@ 0x40348000) R_CEU Structure */ +{ + union + { + __IOM uint32_t CAPSR; /*!< (@ 0x00000000) Capture Start Register */ + + struct + { + __IOM uint32_t CE : 1; /*!< [0..0] Capture enable */ + uint32_t : 15; + __IOM uint32_t CPKIL : 1; /*!< [16..16] Write 1 to this bit to perform a software reset of + * capturing. */ + uint32_t : 15; + } CAPSR_b; + }; + + union + { + __IOM uint32_t CAPCR; /*!< (@ 0x00000004) Capture Control Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CTNCP : 1; /*!< [16..16] When capturing is started with this bit set to 1, capturing + * continues until the CE bit in CAPSR is cleared to 0 or + * a software reset is initiated by the CPKIL bit in CAPSR + * (see ). Continuous capture must be set before capturing + * is started. */ + uint32_t : 3; + __IOM uint32_t MTCM : 2; /*!< [21..20] Specify the unit for transferring data to a bus bridge + * module. */ + uint32_t : 2; + __IOM uint32_t FDRP : 8; /*!< [31..24] Set the frame drop interval in continuous-frame capture. */ + } CAPCR_b; + }; + + union + { + __IOM uint32_t CAMCR; /*!< (@ 0x00000008) Capture interface control register */ + + struct + { + __IOM uint32_t HDPOL : 1; /*!< [0..0] Sets the polarity for detection of the horizontal sync + * signal input from an external module. */ + __IOM uint32_t VDPOL : 1; /*!< [1..1] Sets the polarity for detection of the vertical sync + * signal input from an external module. */ + uint32_t : 2; + __IOM uint32_t JPG : 2; /*!< [5..4] These bits select the fetched data type. */ + uint32_t : 2; + __IOM uint32_t DTARY : 2; /*!< [9..8] Set the input order of the luminance component and chrominance + * component. */ + uint32_t : 2; + __IOM uint32_t DTIF : 1; /*!< [12..12] Sets the digital image input pins from which data is + * to be captured. */ + uint32_t : 3; + __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal + * (FLD) from an external module. */ + uint32_t : 7; + __IOM uint32_t DSEL : 1; /*!< [24..24] Sets the edge for fetching the image data (D7 to D0) + * from an external module. */ + __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification + * signal (FLD) from an external module. */ + __IOM uint32_t HDSEL : 1; /*!< [26..26] Sets the edge for capturing the horizontal sync signal + * (HD) from an external module. */ + __IOM uint32_t VDSEL : 1; /*!< [27..27] Sets the edge for capturing the vertical sync signal + * (VD) from an external module. */ + uint32_t : 4; + } CAMCR_b; + }; + + union + { + __IOM uint32_t CMCYR; /*!< (@ 0x0000000C) Capture Interface Cycle Register */ + + struct + { + __IOM uint32_t HCYL : 14; /*!< [13..0] Horizontal Cycle Count of External Module */ + uint32_t : 2; + __IOM uint32_t VCYL : 14; /*!< [29..16] Vertical HD Count of External Module */ + uint32_t : 2; + } CMCYR_b; + }; + + union + { + __IOM uint32_t CAMOR; /*!< (@ 0x00000010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_b; + }; + + union + { + __IOM uint32_t CAPWR; /*!< (@ 0x00000014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_b; + }; + + union + { + __IOM uint32_t CAIFR; /*!< (@ 0x00000018) Capture Interface Input Format Register */ + + struct + { + __IOM uint32_t FCI : 2; /*!< [1..0] Set the timing to start capturing. */ + uint32_t : 2; + __IOM uint32_t CIM : 1; /*!< [4..4] Sets the images to be captured. */ + uint32_t : 3; + __IOM uint32_t IFS : 1; /*!< [8..8] Sets the input mode for capturing images. */ + uint32_t : 23; + } CAIFR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CRCNTR; /*!< (@ 0x00000028) CEU Register Control Register */ + + struct + { + __IOM uint32_t RC : 1; /*!< [0..0] Specifies switching of the register plane used by the + * CEU in synchronization with VD. */ + __IOM uint32_t RS : 1; /*!< [1..1] Specifies which register plane is used by the CEU in + * synchronization with VD. */ + uint32_t : 2; + __IOM uint32_t RVS : 1; /*!< [4..4] Sets the timing to switch the register plane in both-field + * capture. */ + uint32_t : 27; + } CRCNTR_b; + }; + + union + { + __IOM uint32_t CRCMPR; /*!< (@ 0x0000002C) CEU Register Forcible Control Register */ + + struct + { + __IOM uint32_t RA : 1; /*!< [0..0] Indicates the register plane currently specified. */ + uint32_t : 31; + } CRCMPR_b; + }; + + union + { + __IOM uint32_t CFLCR; /*!< (@ 0x00000030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_b; + }; + + union + { + __IOM uint32_t CFSZR; /*!< (@ 0x00000034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_b; + }; + + union + { + __IOM uint32_t CDWDR; /*!< (@ 0x00000038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_b; + }; + + union + { + __IOM uint32_t CDAYR; /*!< (@ 0x0000003C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_b; + }; + + union + { + __IOM uint32_t CDACR; /*!< (@ 0x00000040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_b; + }; + + union + { + __IOM uint32_t CDBYR; /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_b; + }; + + union + { + __IOM uint32_t CDBCR; /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_b; + }; + + union + { + __IOM uint32_t CBDSR; /*!< (@ 0x0000004C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFWCR; /*!< (@ 0x0000005C) Firewall Operation Control Register */ + + struct + { + __IOM uint32_t FWE : 1; /*!< [0..0] With the setting of FWE = 1, when an address exceeds + * the value set with FWV, the address is retained and an + * interrupt source FWF is set. After this, the address is + * not incremented and data is overwritten on the upper limit + * address. */ + uint32_t : 4; + __IOM uint32_t FWV : 27; /*!< [31..5] Specify the upper limit of a write address. */ + } CFWCR_b; + }; + + union + { + __IOM uint32_t CLFCR; /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_b; + }; + + union + { + __IOM uint32_t CDOCR; /*!< (@ 0x00000064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CEIER; /*!< (@ 0x00000070) Capture Event Interrupt Enable Register */ + + struct + { + __IOM uint32_t CPEIE : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable */ + __IOM uint32_t CFEIE : 1; /*!< [1..1] CFE Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t IGRWIE : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t HDIE : 1; /*!< [8..8] HD Interrupt Enable */ + __IOM uint32_t VDIE : 1; /*!< [9..9] VD Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable */ + __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable */ + __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable */ + __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable */ + __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable */ + __IOM uint32_t IGHSIE : 1; /*!< [17..17] IGHS Interrupt Enable */ + __IOM uint32_t IGVSIE : 1; /*!< [18..18] IGVS Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBPIE : 1; /*!< [20..20] VBP Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FWFIE : 1; /*!< [23..23] FWF Interrupt Enable */ + __IOM uint32_t NHDIE : 1; /*!< [24..24] Non-HD Interrupt Enable */ + __IOM uint32_t NVDIE : 1; /*!< [25..25] Non-VD Interrupt Enable */ + uint32_t : 6; + } CEIER_b; + }; + + union + { + __IOM uint32_t CETCR; /*!< (@ 0x00000074) Capture Event Flag Clear Register */ + + struct + { + __IOM uint32_t CPE : 1; /*!< [0..0] An interrupt indicating that capturing of one frame from + * an external module has finished. */ + __IOM uint32_t CFE : 1; /*!< [1..1] An interrupt indicating that capturing of one field from + * an external module has finished. */ + uint32_t : 2; + __IOM uint32_t IGRW : 1; /*!< [4..4] An interrupt indicating that during capturing, access + * was attempted to a register to which writing during operation + * is prohibited. */ + uint32_t : 3; + __IOM uint32_t HD : 1; /*!< [8..8] An interrupt indicating that HD (horizontal sync signal) + * was input from an external module. */ + __IOM uint32_t VD : 1; /*!< [9..9] An interrupt indicating that VD (vertical sync signal) + * was input from an external module. */ + uint32_t : 2; + __IOM uint32_t CPBE1 : 1; /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR + * in a bundle write has finished. */ + __IOM uint32_t CPBE2 : 1; /*!< [13..13] An interrupt indicating that writing to CDAYR2 and + * CDACR2 in a bundle write has finished. */ + __IOM uint32_t CPBE3 : 1; /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR + * in a bundle write has finished. */ + __IOM uint32_t CPBE4 : 1; /*!< [15..15] An interrupt indicating that writing to CDBYR2 and + * CDBCR2 in a bundle write has finished. */ + __IOM uint32_t CDTOF : 1; /*!< [16..16] An interrupt indicating that data overflowed in the + * CRAM of the write buffer */ + __IOM uint32_t IGHS : 1; /*!< [17..17] An interrupt generated when the number of HD cycles + * set in CMCYR differ from the number of HD cycles input + * from an external module. */ + __IOM uint32_t IGVS : 1; /*!< [18..18] An interrupt generated when the number of VD cycles + * set in CMCYR differ from the number of VD cycles input + * from an external module. */ + uint32_t : 1; + __IOM uint32_t VBP : 1; /*!< [20..20] An interrupt indicating that VD has been input while + * the CEU holds data (insufficient vertical-sync front porch). */ + uint32_t : 2; + __IOM uint32_t FWF : 1; /*!< [23..23] The interrupt is generated when data is written to + * the address that exceeds the value specified with CFWCR.FMV. */ + __IOM uint32_t NHD : 1; /*!< [24..24] An interrupt indicating that no HD was input. */ + __IOM uint32_t NVD : 1; /*!< [25..25] An interrupt indicating that no VD was input. */ + uint32_t : 6; + } CETCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t CSTSR; /*!< (@ 0x0000007C) Capture Status Register */ + + struct + { + __IM uint32_t CPTON : 1; /*!< [0..0] Indicates that the CEU is operating. */ + uint32_t : 15; + __IM uint32_t CPFLD : 1; /*!< [16..16] Indicates which field is being captured. */ + uint32_t : 7; + __IM uint32_t CRST : 1; /*!< [24..24] Indicates which register plane is currently used. */ + uint32_t : 7; + } CSTSR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t CDSSR; /*!< (@ 0x00000084) Capture Data Size Register */ + + struct + { + __IM uint32_t CDSS : 32; /*!< [31..0] Indicate the size of data written to the memory in data + * enable fetch. */ + } CDSSR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CDAYR2; /*!< (@ 0x00000090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_b; + }; + + union + { + __IOM uint32_t CDACR2; /*!< (@ 0x00000094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_b; + }; + + union + { + __IOM uint32_t CDBYR2; /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_b; + }; + + union + { + __IOM uint32_t CDBCR2; /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_b; + }; + + union + { + __IOM uint32_t AXIBUSCTL2; /*!< (@ 0x000000A0) AXI Bus Control Register 2 */ + + struct + { + __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit */ + uint32_t : 28; + } AXIBUSCTL2_b; + }; + __IM uint32_t RESERVED6[987]; + + union + { + __IOM uint32_t CAMOR_B; /*!< (@ 0x00001010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_B_b; + }; + + union + { + __IOM uint32_t CAPWR_B; /*!< (@ 0x00001014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_B_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t CFLCR_B; /*!< (@ 0x00001030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_B_b; + }; + + union + { + __IOM uint32_t CFSZR_B; /*!< (@ 0x00001034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_B_b; + }; + + union + { + __IOM uint32_t CDWDR_B; /*!< (@ 0x00001038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_B_b; + }; + + union + { + __IOM uint32_t CDAYR_B; /*!< (@ 0x0000103C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_B_b; + }; + + union + { + __IOM uint32_t CDACR_B; /*!< (@ 0x00001040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_B_b; + }; + + union + { + __IOM uint32_t CDBYR_B; /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_B_b; + }; + + union + { + __IOM uint32_t CDBCR_B; /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_B_b; + }; + + union + { + __IOM uint32_t CBDSR_B; /*!< (@ 0x0000104C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_B_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint32_t CLFCR_B; /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_B_b; + }; + + union + { + __IOM uint32_t CDOCR_B; /*!< (@ 0x00001064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_B_b; + }; + __IM uint32_t RESERVED9[10]; + + union + { + __IOM uint32_t CDAYR2_B; /*!< (@ 0x00001090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_B_b; + }; + + union + { + __IOM uint32_t CDACR2_B; /*!< (@ 0x00001094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_B_b; + }; + + union + { + __IOM uint32_t CDBYR2_B; /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_B_b; + }; + + union + { + __IOM uint32_t CDBCR2_B; /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_B_b; + }; + __IM uint32_t RESERVED10[988]; + + union + { + __IOM uint32_t CAMOR_M; /*!< (@ 0x00002010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_M_b; + }; + + union + { + __IOM uint32_t CAPWR_M; /*!< (@ 0x00002014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_M_b; + }; + __IM uint32_t RESERVED11[6]; + + union + { + __IOM uint32_t CFLCR_M; /*!< (@ 0x00002030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_M_b; + }; + + union + { + __IOM uint32_t CFSZR_M; /*!< (@ 0x00002034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_M_b; + }; + + union + { + __IOM uint32_t CDWDR_M; /*!< (@ 0x00002038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_M_b; + }; + + union + { + __IOM uint32_t CDAYR_M; /*!< (@ 0x0000203C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_M_b; + }; + + union + { + __IOM uint32_t CDACR_M; /*!< (@ 0x00002040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_M_b; + }; + + union + { + __IOM uint32_t CDBYR_M; /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_M_b; + }; + + union + { + __IOM uint32_t CDBCR_M; /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_M_b; + }; + + union + { + __IOM uint32_t CBDSR_M; /*!< (@ 0x0000204C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_M_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CLFCR_M; /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_M_b; + }; + + union + { + __IOM uint32_t CDOCR_M; /*!< (@ 0x00002064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_M_b; + }; + __IM uint32_t RESERVED13[10]; + + union + { + __IOM uint32_t CDAYR2_M; /*!< (@ 0x00002090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_M_b; + }; + + union + { + __IOM uint32_t CDACR2_M; /*!< (@ 0x00002094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_M_b; + }; + + union + { + __IOM uint32_t CDBYR2_M; /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_M_b; + }; + + union + { + __IOM uint32_t CDBCR2_M; /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_M_b; + }; +} R_CEU_Type; /*!< Size = 8352 (0x20a0) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ultra-Low Power Timer 0 (R_ULPT0) + */ + +typedef struct /*!< (@ 0x40220000) R_ULPT0 Structure */ +{ + union + { + __IOM uint32_t ULPTCNT; /*!< (@ 0x00000000) ULPT Counter Register */ + + struct + { + __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, the 32-bit counter + * is forcibly stopped and set to FFFFFFFFH. */ + } ULPTCNT_b; + }; + + union + { + __IOM uint32_t ULPTCMA; /*!< (@ 0x00000004) ULPT Compare Match A Register */ + + struct + { + __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMA_b; + }; + + union + { + __IOM uint32_t ULPTCMB; /*!< (@ 0x00000008) ULPT Compare Match B Register */ + + struct + { + __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMB_b; + }; + + union + { + __IOM uint8_t ULPTCR; /*!< (@ 0x0000000C) ULPT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] ULPT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] ULPT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] ULPT count forced stop */ + uint8_t : 2; + __IOM uint8_t TUNDF : 1; /*!< [5..5] ULPT underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] ULPT compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] ULPT compare match B flag */ + } ULPTCR_b; + }; + + union + { + __IOM uint8_t ULPTMR1; /*!< (@ 0x0000000D) ULPT Mode Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t TMOD1 : 1; /*!< [1..1] ULPT operating mode select */ + uint8_t : 1; + __IOM uint8_t TEDGPL : 1; /*!< [3..3] ULPTEVI edge polarity select */ + uint8_t : 1; + __IOM uint8_t TCK1 : 1; /*!< [5..5] ULPT count source select */ + uint8_t : 2; + } ULPTMR1_b; + }; + + union + { + __IOM uint8_t ULPTMR2; /*!< (@ 0x0000000E) ULPT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] fsub/LOCO count source clock frequency division ratio + * select */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] ULPT Low Power Mode */ + } ULPTMR2_b; + }; + + union + { + __IOM uint8_t ULPTMR3; /*!< (@ 0x0000000F) ULPT Mode Register 3 */ + + struct + { + __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select */ + __IOM uint8_t TEVPOL : 1; /*!< [1..1] ULPTEVI polarity switch */ + __IOM uint8_t TOPOL : 1; /*!< [2..2] ULPTO polarity select */ + uint8_t : 1; + __IOM uint8_t TEECTL : 2; /*!< [5..4] ULPTEE function select */ + __IOM uint8_t TEEPOL : 2; /*!< [7..6] ULPTEE edge polarity select */ + } ULPTMR3_b; + }; + + union + { + __IOM uint8_t ULPTIOC; /*!< (@ 0x00000010) ULPT I/O Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t TOE : 1; /*!< [2..2] ULPTO output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] ULPTEVI input filter select */ + __IOM uint8_t TIOGT0 : 1; /*!< [6..6] ULPTEVI count control */ + uint8_t : 1; + } ULPTIOC_b; + }; + + union + { + __IOM uint8_t ULPTISR; /*!< (@ 0x00000011) ULPT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection */ + uint8_t : 5; + } ULPTISR_b; + }; + + union + { + __IOM uint8_t ULPTCMSR; /*!< (@ 0x00000012) ULPT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] ULPTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] ULPTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] ULPTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] ULPTOB polarity select */ + uint8_t : 1; + } ULPTCMSR_b; + }; + __IM uint8_t RESERVED; +} R_ULPT0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief On-Chip Debug Function (R_DEBUG_OCD) + */ + +typedef struct /*!< (@ 0x40011000) R_DEBUG_OCD Structure */ +{ + __IM uint32_t RESERVED[192]; + + union + { + __IM uint32_t FSBLSTATM; /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register */ + + struct + { + __IM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 30; + } FSBLSTATM_b; + }; +} R_DEBUG_OCD_Type; /*!< Size = 772 (0x304) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Decryption On The Fly (R_DOTF) + */ + +typedef struct /*!< (@ 0x40268800) R_DOTF Structure */ +{ + union + { + __IOM uint32_t CONVAREAST; /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area */ + } CONVAREAST_b; + }; + + union + { + __IOM uint32_t CONVAREAD; /*!< (@ 0x00000004) DOTF Conversion Area End Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area */ + } CONVAREAD_b; + }; + __IM uint32_t RESERVED[30]; + + union + { + __IOM uint32_t REG00; /*!< (@ 0x00000080) Register 0 */ + + struct + { + uint32_t : 9; + __IOM uint32_t B09 : 1; /*!< [9..9] Bit 09 */ + uint32_t : 6; + __IOM uint32_t B16 : 1; /*!< [16..16] Bit 09 */ + __IOM uint32_t B17 : 1; /*!< [17..17] Bit 17 */ + uint32_t : 2; + __IOM uint32_t B20 : 1; /*!< [20..20] Bit 20 */ + uint32_t : 3; + __IOM uint32_t B24 : 2; /*!< [25..24] Bit24-25 */ + uint32_t : 2; + __IOM uint32_t B28 : 2; /*!< [29..28] Bit28-29 */ + uint32_t : 2; + } REG00_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t REG03; /*!< (@ 0x0000008C) Register 03 */ + + struct + { + __IOM uint32_t B00 : 32; /*!< [31..0] Bit 0 */ + } REG03_b; + }; +} R_DOTF_Type; /*!< Size = 144 (0x90) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash (R_FLAD) + */ + +typedef struct /*!< (@ 0x4011C000) R_FLAD Structure */ +{ + __IM uint8_t RESERVED[64]; + + union + { + __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ + + struct + { + __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ + } FCKMHZ_b; + }; +} R_FLAD_Type; /*!< Size = 65 (0x41) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DSI Link (R_MIPI_DSI) + */ + +typedef struct /*!< (@ 0x40346000) R_MIPI_DSI Structure */ +{ + union + { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt Status Register */ + + struct + { + __IM uint32_t SQ0 : 1; /*!< [0..0] Sequence Channel-0 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t SQ1 : 1; /*!< [4..4] Sequence Channel-1 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t VM : 1; /*!< [8..8] Video Mode Interrupt Flag */ + uint32_t : 3; + __IM uint32_t RCV : 1; /*!< [12..12] Receive Interrupt Flag */ + uint32_t : 3; + __IM uint32_t FERR : 1; /*!< [16..16] Fatal Error Interrupt Flag */ + uint32_t : 3; + __IM uint32_t PPI : 1; /*!< [20..20] PPI Interrupt Flag */ + uint32_t : 11; + } ISR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IM uint32_t LINKSR; /*!< (@ 0x00000010) Link Status Register */ + + struct + { + __IM uint32_t SQ0RUN : 1; /*!< [0..0] Sequence Channel-0 Running Flag */ + uint32_t : 3; + __IM uint32_t SQ1RUN : 1; /*!< [4..4] Sequence Channel-1 Running Flag */ + uint32_t : 3; + __IM uint32_t VRUN : 1; /*!< [8..8] Video Mode Operation Running Flag */ + uint32_t : 3; + __IM uint32_t HSBUSY : 1; /*!< [12..12] HS Operation Busy Flag */ + __IM uint32_t LPBUSY : 1; /*!< [13..13] LP Operation Busy Flag */ + uint32_t : 18; + } LINKSR_b; + }; + __IM uint32_t RESERVED1[59]; + + union + { + __IOM uint32_t TXSETR; /*!< (@ 0x00000100) Transmit Set Register */ + + struct + { + __IOM uint32_t NUMLANE : 2; /*!< [1..0] Number of Lane */ + uint32_t : 6; + __IOM uint32_t CLEN : 1; /*!< [8..8] Clock Lane Enable */ + __IOM uint32_t DLEN : 1; /*!< [9..9] Data Lane Enable */ + uint32_t : 22; + } TXSETR_b; + }; + + union + { + __IOM uint32_t HSCLKSETR; /*!< (@ 0x00000104) HS Clock Set Register */ + + struct + { + __IOM uint32_t HSCLST : 1; /*!< [0..0] HS Clock Start */ + __IOM uint32_t HSCLMD : 1; /*!< [1..1] HS Clock Running Mode */ + uint32_t : 30; + } HSCLKSETR_b; + }; + + union + { + __IOM uint32_t ULPSSETR; /*!< (@ 0x00000108) ULPS Set Register */ + + struct + { + __IOM uint32_t WKUP : 8; /*!< [7..0] ULPS Wakeup Period */ + uint32_t : 24; + } ULPSSETR_b; + }; + + union + { + __OM uint32_t ULPSCR; /*!< (@ 0x0000010C) ULPS Control Register */ + + struct + { + uint32_t : 24; + __OM uint32_t CLENT : 1; /*!< [24..24] CL ULPS Enter */ + __OM uint32_t CLEXIT : 1; /*!< [25..25] CL ULPS Exit */ + uint32_t : 2; + __OM uint32_t DLENT : 1; /*!< [28..28] DL ULPS Enter */ + __OM uint32_t DLEXIT : 1; /*!< [29..29] DL ULPS Exit */ + uint32_t : 2; + } ULPSCR_b; + }; + + union + { + __IOM uint32_t RSTCR; /*!< (@ 0x00000110) Reset Control Register */ + + struct + { + __IOM uint32_t SWRST : 1; /*!< [0..0] Software Reset */ + uint32_t : 15; + __IOM uint32_t FTXSTP : 1; /*!< [16..16] Force Tx Stop Mode */ + uint32_t : 15; + } RSTCR_b; + }; + + union + { + __IM uint32_t RSTSR; /*!< (@ 0x00000114) Reset Status Register */ + + struct + { + __IM uint32_t RSTHS : 1; /*!< [0..0] HS Software Reset Status */ + __IM uint32_t RSTLP : 1; /*!< [1..1] LP Software Reset Status */ + __IM uint32_t RSTAPB : 1; /*!< [2..2] APB Software Reset Status */ + __IM uint32_t RSTAXI : 1; /*!< [3..3] AXI Software Reset Status */ + __IM uint32_t RSTV : 1; /*!< [4..4] Video Software Reset Status */ + uint32_t : 3; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 5; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 16; + } RSTSR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t DSISETR; /*!< (@ 0x00000120) DSI Set Register */ + + struct + { + __IOM uint32_t MRPSZ : 16; /*!< [15..0] Maximum Return Packet Size */ + __IOM uint32_t ECCEN : 1; /*!< [16..16] ECC Check Enable */ + uint32_t : 3; + __IOM uint32_t VC0CRCEN : 1; /*!< [20..20] VC-0 CRC Check Enable */ + __IOM uint32_t VC1CRCEN : 1; /*!< [21..21] VC-1 CRC Check Enable */ + __IOM uint32_t VC2CRCEN : 1; /*!< [22..22] VC-2 CRC Check Enable */ + __IOM uint32_t VC3CRCEN : 1; /*!< [23..23] VC-3 CRC Check Enable */ + uint32_t : 5; + __IOM uint32_t SCREN : 1; /*!< [29..29] Data Scramble Enable */ + __IOM uint32_t EXTEMD : 1; /*!< [30..30] External Tearing Effect Detection Sense Select */ + __IOM uint32_t EOTPEN : 1; /*!< [31..31] HS Transfer EoTp Enable */ + } DSISETR_b; + }; + __IM uint32_t RESERVED3[15]; + + union + { + __IOM uint32_t TXPPD0R; /*!< (@ 0x00000160) Transmit Packet Payload Data 0 Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IOM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IOM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } TXPPD0R_b; + }; + + union + { + __IOM uint32_t TXPPD1R; /*!< (@ 0x00000164) Transmit Packet Payload Data 1 Register */ + + struct + { + __IOM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 4 */ + __IOM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 5 */ + __IOM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 6 */ + __IOM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 7 */ + } TXPPD1R_b; + }; + + union + { + __IOM uint32_t TXPPD2R; /*!< (@ 0x00000168) Transmit Packet Payload Data 2 Register */ + + struct + { + __IOM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IOM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IOM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IOM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } TXPPD2R_b; + }; + + union + { + __IOM uint32_t TXPPD3R; /*!< (@ 0x0000016C) Transmit Packet Payload Data 3 Register */ + + struct + { + __IOM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IOM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IOM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IOM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } TXPPD3R_b; + }; + __IM uint32_t RESERVED4[36]; + + union + { + __IM uint32_t RXSR; /*!< (@ 0x00000200) Receive Status Register */ + + struct + { + __IM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 5; + __IM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag */ + uint32_t : 2; + __IM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag */ + __IM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag */ + __IM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag */ + __IM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag */ + __IM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag */ + __IM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag */ + __IM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag */ + __IM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag */ + __IM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag */ + __IM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag */ + __IM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag */ + __IM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag */ + uint32_t : 1; + } RXSR_b; + }; + + union + { + __IOM uint32_t RXSCR; /*!< (@ 0x00000204) Receive Status Clear Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag Clear */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag Clear */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag Clear */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag Clear */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag Clear */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag Clear */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag Clear */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag Clear */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag Clear */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag + * Clear */ + uint32_t : 1; + } RXSCR_b; + }; + + union + { + __IOM uint32_t RXIER; /*!< (@ 0x00000208) Receive Interrupt Enable Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Enable */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Enable */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Enable */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Enable */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Enable */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Enable */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Enable */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Enable */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Enable */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Enable */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Enable */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Enable */ + uint32_t : 1; + } RXIER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PRESPTOBTASETR; /*!< (@ 0x00000210) Peripheral Response Timeout BTA Set Register */ + + struct + { + __IOM uint32_t PRTBTA : 32; /*!< [31..0] Peripheral Response Timeout Count */ + } PRESPTOBTASETR_b; + }; + + union + { + __IOM uint32_t PRESPTOLPSETR; /*!< (@ 0x00000214) Peripheral Response Timeout LP Set Register */ + + struct + { + __IOM uint32_t LPWTO : 16; /*!< [15..0] LPDT WRITE Request Timeout */ + __IOM uint32_t LPRTO : 16; /*!< [31..16] LPDT READ Request Timeout */ + } PRESPTOLPSETR_b; + }; + + union + { + __IOM uint32_t PRESPTOHSSETR; /*!< (@ 0x00000218) Peripheral Response Timeout HS Set Register */ + + struct + { + __IOM uint32_t HSWTO : 16; /*!< [15..0] HS WRITE Request Timeout */ + __IOM uint32_t HSRTO : 16; /*!< [31..16] HS READ Request Timeout */ + } PRESPTOHSSETR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IM uint32_t AKEPLATIR; /*!< (@ 0x00000220) Acknowledge and Error Report Packet Parameter + * Latest Info Register */ + + struct + { + __IM uint32_t EREP : 16; /*!< [15..0] Error Report */ + __IM uint32_t VC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPLATIR_b; + }; + + union + { + __IM uint32_t AKEPACMSR; /*!< (@ 0x00000224) Acknowledge and Error Report Packet Parameter + * Accumulate Status Register */ + + struct + { + __IM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPACMSR_b; + }; + + union + { + __IOM uint32_t AKEPSCR; /*!< (@ 0x00000228) Acknowledge and Error Report Packet Parameter + * Status Clear Register */ + + struct + { + __IOM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report Clear */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPSCR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RXRSSR; /*!< (@ 0x00000230) Receive Result Saved Status Register */ + + struct + { + __IM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag */ + __IM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag */ + __IM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag */ + __IM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag */ + uint32_t : 28; + } RXRSSR_b; + }; + + union + { + __IOM uint32_t RXRSSCR; /*!< (@ 0x00000234) Receive Result Saved Status Clear Register */ + + struct + { + __IOM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag Clear */ + __IOM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag Clear */ + __IOM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag Clear */ + __IOM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag Clear */ + uint32_t : 28; + } RXRSSCR_b; + }; + + union + { + __IM uint32_t RXRINFOOWSR; /*!< (@ 0x00000238) Receive Result Info Overwrite Status Register */ + + struct + { + __IM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag */ + __IM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag */ + __IM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag */ + __IM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag */ + uint32_t : 28; + } RXRINFOOWSR_b; + }; + + union + { + __IOM uint32_t RXRINFOOWSCR; /*!< (@ 0x0000023C) Receive Result Info Overwrite Status Clear Register */ + + struct + { + __IOM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag Clear */ + __IOM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag Clear */ + __IOM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag Clear */ + __IOM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag Clear */ + uint32_t : 28; + } RXRINFOOWSCR_b; + }; + + union + { + union + { + __IM uint32_t RXRSS0R; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS0R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS0R_L; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS0R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_LL; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS0R_LL_b; + }; + + union + { + __IM uint8_t RXRSS0R_LH; /*!< (@ 0x00000241) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS0R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS0R_H; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS0R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_HL; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS0R_HL_b; + }; + + union + { + __IM uint8_t RXRSS0R_HH; /*!< (@ 0x00000243) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS0R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS1R; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS1R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS1R_L; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS1R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_LL; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS1R_LL_b; + }; + + union + { + __IM uint8_t RXRSS1R_LH; /*!< (@ 0x00000245) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS1R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS1R_H; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS1R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_HL; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS1R_HL_b; + }; + + union + { + __IM uint8_t RXRSS1R_HH; /*!< (@ 0x00000247) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS1R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS2R; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS2R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS2R_L; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS2R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_LL; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS2R_LL_b; + }; + + union + { + __IM uint8_t RXRSS2R_LH; /*!< (@ 0x00000249) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS2R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS2R_H; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS2R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_HL; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS2R_HL_b; + }; + + union + { + __IM uint8_t RXRSS2R_HH; /*!< (@ 0x0000024B) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS2R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS3R; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS3R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS3R_L; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS3R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_LL; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS3R_LL_b; + }; + + union + { + __IM uint8_t RXRSS3R_LH; /*!< (@ 0x0000024D) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS3R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS3R_H; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS3R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_HL; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS3R_HL_b; + }; + + union + { + __IM uint8_t RXRSS3R_HH; /*!< (@ 0x0000024F) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS3R_HH_b; + }; + }; + }; + }; + }; + __IM uint32_t RESERVED8[28]; + + union + { + __IM uint32_t RXPPD0R; /*!< (@ 0x000002C0) Receive Packet Payload Data 0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD0R_b; + }; + + union + { + __IM uint32_t RXPPD1R; /*!< (@ 0x000002C4) Receive Packet Payload Data 1 Register */ + + struct + { + __IM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD1R_b; + }; + + union + { + __IM uint32_t RXPPD2R; /*!< (@ 0x000002C8) Receive Packet Payload Data 2 Register */ + + struct + { + __IM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } RXPPD2R_b; + }; + + union + { + __IM uint32_t RXPPD3R; /*!< (@ 0x000002CC) Receive Packet Payload Data 3 Register */ + + struct + { + __IM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } RXPPD3R_b; + }; + __IM uint32_t RESERVED9[4]; + + union + { + __IOM uint32_t HSTXTOSETR; /*!< (@ 0x000002E0) HS TX Timeout Set Register */ + + struct + { + __IOM uint32_t HTXTO : 32; /*!< [31..0] HS TX Timeout Count */ + } HSTXTOSETR_b; + }; + + union + { + __IOM uint32_t LRXHTOSETR; /*!< (@ 0x000002E4) LRX-H Timeout Set Register */ + + struct + { + __IOM uint32_t LRXHTO : 32; /*!< [31..0] LP-RX Host Processor Timeout */ + } LRXHTOSETR_b; + }; + + union + { + __IOM uint32_t TATOSETR; /*!< (@ 0x000002E8) TA Timeout Set Register */ + + struct + { + __IOM uint32_t TATO : 32; /*!< [31..0] Turnaround Acknowledge Timeout */ + } TATOSETR_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IM uint32_t FERRSR; /*!< (@ 0x00000300) Fatal Error Status Register */ + + struct + { + __IM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 13; + __IM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag */ + __IM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag */ + __IM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag */ + __IM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag */ + __IM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag */ + uint32_t : 6; + __IM uint32_t CLP0S : 1; /*!< [27..27] LP0 Contention Error Status */ + __IM uint32_t CLP1S : 1; /*!< [28..28] LP1 Contention Error Status */ + uint32_t : 3; + } FERRSR_b; + }; + + union + { + __IOM uint32_t FERRSCR; /*!< (@ 0x00000304) Fatal Error Status Clear Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag Clear */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag Clear */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag Clear */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag Clear */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag Clear */ + uint32_t : 11; + } FERRSCR_b; + }; + + union + { + __IOM uint32_t FERRIER; /*!< (@ 0x00000308) Fatal Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Enable */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Enable */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Enable */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Enable */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Enable */ + uint32_t : 11; + } FERRIER_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t CLSTPTSETR; /*!< (@ 0x00000314) Clock Lane Stop Time Set Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CLKSTPT : 10; /*!< [11..2] Clock Stop Time */ + uint32_t : 4; + __IOM uint32_t CLKBFHT : 8; /*!< [23..16] Clock Beforehand Time */ + __IOM uint32_t CLKKPT : 8; /*!< [31..24] Clock Keep Time */ + } CLSTPTSETR_b; + }; + + union + { + __IOM uint32_t LPTRNSTSETR; /*!< (@ 0x00000318) LP Transition Time Set Register */ + + struct + { + __IOM uint32_t GOLPBKT : 10; /*!< [9..0] Go LP and Back Time */ + uint32_t : 22; + } LPTRNSTSETR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t PLSR; /*!< (@ 0x00000320) Physical Lane Status Register */ + + struct + { + __IM uint32_t CLUAN : 1; /*!< [0..0] Clock Lane UlpsActiveNot Status */ + __IM uint32_t CLSTP : 1; /*!< [1..1] Clock Lane Stop Status */ + __IM uint32_t DL0RLE : 1; /*!< [2..2] Data Lane-0 RxLpdtEsc Status */ + __IM uint32_t DL0RUE : 1; /*!< [3..3] Data Lane-0 RxUlpsEsc Status */ + __IM uint32_t DL0UAN : 1; /*!< [4..4] Data Lane-0 UlpsActiveNot Status */ + __IM uint32_t DL1UAN : 1; /*!< [5..5] Data Lane-1 UlpsActiveNot Status */ + uint32_t : 2; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 2; + __IM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag */ + __IM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag */ + uint32_t : 1; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 8; + __IM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag */ + __IM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag */ + __IM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag */ + __IM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag */ + __IM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag */ + __IM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag */ + uint32_t : 2; + } PLSR_b; + }; + + union + { + __IOM uint32_t PLSCR; /*!< (@ 0x00000324) Physical Lane Status Clear Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag Clear */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag Clear */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag Clear */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag Clear */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag Clear */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag Clear */ + uint32_t : 2; + } PLSCR_b; + }; + + union + { + __IOM uint32_t PLIER; /*!< (@ 0x00000328) Physical Lane Interrupt Enable Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Enable */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Enable */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Enable */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Enable */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Enable */ + uint32_t : 2; + } PLIER_b; + }; + __IM uint32_t RESERVED13[53]; + + union + { + __IOM uint32_t VMSET0R; /*!< (@ 0x00000400) Video Mode Set 0 Register */ + + struct + { + __OM uint32_t VSTART : 1; /*!< [0..0] Video Mode Operation Start */ + __OM uint32_t VSTOP : 1; /*!< [1..1] Video Mode Operation Stop */ + uint32_t : 6; + __IOM uint32_t HSANOLP : 1; /*!< [8..8] HSA period No LP */ + __IOM uint32_t HBPNOLP : 1; /*!< [9..9] HBP period No LP */ + __IOM uint32_t HFPNOLP : 1; /*!< [10..10] HFP period No LP */ + uint32_t : 21; + } VMSET0R_b; + }; + + union + { + __IOM uint32_t VMSET1R; /*!< (@ 0x00000404) Video Mode Set 1 Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t DLY : 12; /*!< [13..2] Delay Value */ + uint32_t : 18; + } VMSET1R_b; + }; + __IM uint32_t RESERVED14[2]; + + union + { + __IM uint32_t VMSR; /*!< (@ 0x00000410) Video Mode Status Register */ + + struct + { + __IM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag */ + __IM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag */ + __IM uint32_t RUNNING : 1; /*!< [2..2] Video Mode Operation Running Status */ + __IM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag */ + uint32_t : 16; + __IM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag */ + __IM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag */ + uint32_t : 8; + } VMSR_b; + }; + + union + { + __IOM uint32_t VMSCR; /*!< (@ 0x00000414) Video Mode Status Clear Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag Clear */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag Clear */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag Clear */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag Clear */ + uint32_t : 8; + } VMSCR_b; + }; + + union + { + __IOM uint32_t VMIER; /*!< (@ 0x00000418) Video Mode Interrupt Enable Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Enable */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Enable */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Enable */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Enable */ + uint32_t : 8; + } VMIER_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t VMPPSETR; /*!< (@ 0x00000420) Video Mode Pixel Packet Set Register */ + + struct + { + uint32_t : 15; + __IOM uint32_t TXESYNC : 1; /*!< [15..15] Transmit End of Sync Pulse */ + __IOM uint32_t DT : 6; /*!< [21..16] Video Mode Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Video Mode Virtual Channel */ + uint32_t : 8; + } VMPPSETR_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t VMVSSETR; /*!< (@ 0x00000428) Video Mode Vertical Size Set Register */ + + struct + { + __IOM uint32_t VSA : 12; /*!< [11..0] VSA Lines */ + uint32_t : 3; + __IOM uint32_t VSPOL : 1; /*!< [15..15] VSYNC Polarity */ + __IOM uint32_t VACT : 15; /*!< [30..16] Vertical Active Lines */ + uint32_t : 1; + } VMVSSETR_b; + }; + + union + { + __IOM uint32_t VMVPSETR; /*!< (@ 0x0000042C) Video Mode Vertical Porch Set Register */ + + struct + { + __IOM uint32_t VBP : 13; /*!< [12..0] VBP Lines */ + uint32_t : 3; + __IOM uint32_t VFP : 13; /*!< [28..16] VFP Lines */ + uint32_t : 3; + } VMVPSETR_b; + }; + + union + { + __IOM uint32_t VMHSSETR; /*!< (@ 0x00000430) Video Mode Horizontal Size Set Register */ + + struct + { + __IOM uint32_t HSA : 12; /*!< [11..0] HSA Pixels */ + uint32_t : 3; + __IOM uint32_t HSPOL : 1; /*!< [15..15] HSYNC Polarity */ + __IOM uint32_t HACT : 15; /*!< [30..16] HACT Pixels */ + uint32_t : 1; + } VMHSSETR_b; + }; + + union + { + __IOM uint32_t VMHPSETR; /*!< (@ 0x00000434) Video Mode Horizontal Porch Set Register */ + + struct + { + __IOM uint32_t HBP : 13; /*!< [12..0] HBP Pixels */ + uint32_t : 3; + __IOM uint32_t HFP : 13; /*!< [28..16] HFP Pixels */ + uint32_t : 3; + } VMHPSETR_b; + }; + __IM uint32_t RESERVED17[98]; + + union + { + __IOM uint32_t SQCH0SET0R; /*!< (@ 0x000005C0) Sequence Channel 0 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH0SET0R_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IM uint32_t SQCH0SR; /*!< (@ 0x000005D0) Sequence Channel 0 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH0SR_b; + }; + + union + { + __IOM uint32_t SQCH0SCR; /*!< (@ 0x000005D4) Sequence Channel 0 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH0SCR_b; + }; + + union + { + __IOM uint32_t SQCH0IER; /*!< (@ 0x000005D8) Sequence Channel 0 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH0IER_b; + }; + __IM uint32_t RESERVED19[9]; + + union + { + __IOM uint32_t SQCH1SET0R; /*!< (@ 0x00000600) Sequence Channel 1 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH1SET0R_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IM uint32_t SQCH1SR; /*!< (@ 0x00000610) Sequence Channel 1 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH1SR_b; + }; + + union + { + __IOM uint32_t SQCH1SCR; /*!< (@ 0x00000614) Sequence Channel 1 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH1SCR_b; + }; + + union + { + __IOM uint32_t SQCH1IER; /*!< (@ 0x00000618) Sequence Channel 1 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH1IER_b; + }; + __IM uint32_t RESERVED21[89]; + + union + { + union + { + __IOM uint32_t SQCH0DSC0AR; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_L; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_LL; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_LH; /*!< (@ 0x00000781) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_H; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_HL; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_HH; /*!< (@ 0x00000783) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC0BR; /*!< (@ 0x00000784) Sequence Channel 0 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0CR; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_L; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_LL; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_H; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0CR_HL; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_HH; /*!< (@ 0x0000078B) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0DR; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_L; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_LL; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_LH; /*!< (@ 0x0000078D) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_H; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_HL; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_HH; /*!< (@ 0x0000078F) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1AR; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_L; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_LL; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_LH; /*!< (@ 0x00000791) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_H; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_HL; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_HH; /*!< (@ 0x00000793) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC1BR; /*!< (@ 0x00000794) Sequence Channel 0 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1CR; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_L; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_LL; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_H; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1CR_HL; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_HH; /*!< (@ 0x0000079B) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1DR; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_L; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_LL; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_LH; /*!< (@ 0x0000079D) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_H; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_HL; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_HH; /*!< (@ 0x0000079F) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2AR; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_L; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_LL; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_LH; /*!< (@ 0x000007A1) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_H; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_HL; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_HH; /*!< (@ 0x000007A3) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC2BR; /*!< (@ 0x000007A4) Sequence Channel 0 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2CR; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_L; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_LL; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_H; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2CR_HL; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_HH; /*!< (@ 0x000007AB) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2DR; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_L; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_LL; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_LH; /*!< (@ 0x000007AD) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_H; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_HL; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_HH; /*!< (@ 0x000007AF) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3AR; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_L; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_LL; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_LH; /*!< (@ 0x000007B1) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_H; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_HL; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_HH; /*!< (@ 0x000007B3) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC3BR; /*!< (@ 0x000007B4) Sequence Channel 0 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3CR; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_L; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_LL; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_H; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3CR_HL; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_HH; /*!< (@ 0x000007BB) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3DR; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_L; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_LL; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_LH; /*!< (@ 0x000007BD) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_H; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_HL; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_HH; /*!< (@ 0x000007BF) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4AR; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_L; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_LL; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_LH; /*!< (@ 0x000007C1) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_H; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_HL; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_HH; /*!< (@ 0x000007C3) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC4BR; /*!< (@ 0x000007C4) Sequence Channel 0 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4CR; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_L; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_LL; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_H; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4CR_HL; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_HH; /*!< (@ 0x000007CB) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4DR; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_L; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_LL; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_LH; /*!< (@ 0x000007CD) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_H; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_HL; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_HH; /*!< (@ 0x000007CF) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5AR; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_L; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_LL; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_LH; /*!< (@ 0x000007D1) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_H; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_HL; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_HH; /*!< (@ 0x000007D3) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC5BR; /*!< (@ 0x000007D4) Sequence Channel 0 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5CR; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_L; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_LL; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_H; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5CR_HL; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_HH; /*!< (@ 0x000007DB) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5DR; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_L; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_LL; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_LH; /*!< (@ 0x000007DD) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_H; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_HL; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_HH; /*!< (@ 0x000007DF) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6AR; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_L; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_LL; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_LH; /*!< (@ 0x000007E1) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_H; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_HL; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_HH; /*!< (@ 0x000007E3) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC6BR; /*!< (@ 0x000007E4) Sequence Channel 0 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6CR; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_L; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_LL; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_H; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6CR_HL; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_HH; /*!< (@ 0x000007EB) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6DR; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_L; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_LL; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_LH; /*!< (@ 0x000007ED) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_H; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_HL; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_HH; /*!< (@ 0x000007EF) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7AR; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_L; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_LL; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_LH; /*!< (@ 0x000007F1) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_H; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_HL; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_HH; /*!< (@ 0x000007F3) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC7BR; /*!< (@ 0x000007F4) Sequence Channel 0 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7CR; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_L; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_LL; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_H; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7CR_HL; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_HH; /*!< (@ 0x000007FB) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7DR; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_L; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_LL; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_LH; /*!< (@ 0x000007FD) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_H; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_HL; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_HH; /*!< (@ 0x000007FF) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0AR; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_L; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_LL; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_LH; /*!< (@ 0x00000801) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_H; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_HL; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_HH; /*!< (@ 0x00000803) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC0BR; /*!< (@ 0x00000804) Sequence Channel 1 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0CR; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_L; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_LL; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_H; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0CR_HL; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_HH; /*!< (@ 0x0000080B) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0DR; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0DR_L; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0DR_LL; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_LH; /*!< (@ 0x0000080D) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HL; /*!< (@ 0x0000080E) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HH; /*!< (@ 0x0000080F) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1AR; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_L; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_LL; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_LH; /*!< (@ 0x00000811) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_H; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_HL; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_HH; /*!< (@ 0x00000813) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC1BR; /*!< (@ 0x00000814) Sequence Channel 1 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1CR; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_L; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_LL; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_H; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1CR_HL; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_HH; /*!< (@ 0x0000081B) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1DR; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1DR_L; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1DR_LL; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_LH; /*!< (@ 0x0000081D) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HL; /*!< (@ 0x0000081E) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HH; /*!< (@ 0x0000081F) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2AR; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_L; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_LL; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_LH; /*!< (@ 0x00000821) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_H; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_HL; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_HH; /*!< (@ 0x00000823) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC2BR; /*!< (@ 0x00000824) Sequence Channel 1 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2CR; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_L; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_LL; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_H; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2CR_HL; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_HH; /*!< (@ 0x0000082B) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2DR; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2DR_L; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2DR_LL; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_LH; /*!< (@ 0x0000082D) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HL; /*!< (@ 0x0000082E) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HH; /*!< (@ 0x0000082F) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3AR; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_L; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_LL; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_LH; /*!< (@ 0x00000831) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_H; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_HL; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_HH; /*!< (@ 0x00000833) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC3BR; /*!< (@ 0x00000834) Sequence Channel 1 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3CR; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_L; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_LL; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_H; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3CR_HL; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_HH; /*!< (@ 0x0000083B) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3DR; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3DR_L; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3DR_LL; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_LH; /*!< (@ 0x0000083D) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HL; /*!< (@ 0x0000083E) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HH; /*!< (@ 0x0000083F) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4AR; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_L; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_LL; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_LH; /*!< (@ 0x00000841) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_H; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_HL; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_HH; /*!< (@ 0x00000843) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC4BR; /*!< (@ 0x00000844) Sequence Channel 1 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4CR; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_L; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_LL; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_H; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4CR_HL; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_HH; /*!< (@ 0x0000084B) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4DR; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4DR_L; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4DR_LL; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_LH; /*!< (@ 0x0000084D) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HL; /*!< (@ 0x0000084E) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HH; /*!< (@ 0x0000084F) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5AR; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_L; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_LL; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_LH; /*!< (@ 0x00000851) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_H; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_HL; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_HH; /*!< (@ 0x00000853) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC5BR; /*!< (@ 0x00000854) Sequence Channel 1 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5CR; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_L; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_LL; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_H; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5CR_HL; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_HH; /*!< (@ 0x0000085B) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5DR; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5DR_L; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5DR_LL; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_LH; /*!< (@ 0x0000085D) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HL; /*!< (@ 0x0000085E) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HH; /*!< (@ 0x0000085F) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6AR; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_L; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_LL; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_LH; /*!< (@ 0x00000861) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_H; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_HL; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_HH; /*!< (@ 0x00000863) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC6BR; /*!< (@ 0x00000864) Sequence Channel 1 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6CR; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_L; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_LL; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_H; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6CR_HL; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_HH; /*!< (@ 0x0000086B) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6DR; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6DR_L; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6DR_LL; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_LH; /*!< (@ 0x0000086D) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HL; /*!< (@ 0x0000086E) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HH; /*!< (@ 0x0000086F) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7AR; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_L; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_LL; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_LH; /*!< (@ 0x00000871) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_H; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_HL; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_HH; /*!< (@ 0x00000873) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC7BR; /*!< (@ 0x00000874) Sequence Channel 1 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7CR; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_L; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_LL; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_H; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7CR_HL; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_HH; /*!< (@ 0x0000087B) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7DR; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7DR_L; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7DR_LL; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_LH; /*!< (@ 0x0000087D) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HL; /*!< (@ 0x0000087E) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HH; /*!< (@ 0x0000087F) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HH_b; + }; + }; + }; +} R_MIPI_DSI_Type; /*!< Size = 2176 (0x880) */ + +/* =========================================================================================================================== */ +/* ================ R_OFS_DATAFLASH ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash Option-Setting Memory (R_OFS_DATAFLASH) + */ + +typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Structure */ +{ + __IM uint32_t RESERVED[32]; + + union + { + __IM uint32_t FSBLCTRL0; /*!< (@ 0x00000080) FSBL Control Register 0 */ + + struct + { + __IM uint32_t FSBLEN : 3; /*!< [2..0] FSBL Enable */ + __IM uint32_t FSBLSKIPSW : 3; /*!< [5..3] FSBL Skip Enable for Software Reset */ + __IM uint32_t FSBLSKIPDS : 3; /*!< [8..6] FSBL Skip Enable for Deep Software Standby Reset */ + __IM uint32_t FSBLCLK : 3; /*!< [11..9] Clock Frequency Selection during FSBL Execution */ + uint32_t : 20; + } FSBLCTRL0_b; + }; + + union + { + __IM uint32_t FSBLCTRL1; /*!< (@ 0x00000084) FSBL Control Register 1 */ + + struct + { + __IM uint32_t FSBLEXMD : 2; /*!< [1..0] FSBL Execution Mode */ + uint32_t : 30; + } FSBLCTRL1_b; + }; + + union + { + __IM uint32_t FSBLCTRL2; /*!< (@ 0x00000088) FSBL Control Register 2 */ + + struct + { + __IM uint32_t PORTPN : 4; /*!< [3..0] FSBL Error Notification Port Pin Number */ + __IM uint32_t PORTGN : 5; /*!< [8..4] FSBL Error Notification Port Group Name */ + uint32_t : 23; + } FSBLCTRL2_b; + }; + __IOM uint32_t SACC0; /*!< (@ 0x0000008C) Start Address of Code Certification 0 */ + __IOM uint32_t SACC1; /*!< (@ 0x00000090) Start Address of Code Certification 1 */ + __IOM uint32_t SAMR; /*!< (@ 0x00000094) Start Address of Measurement Report */ + __IM uint32_t RESERVED1[178]; + __IM uint32_t HOEMRTPK; /*!< (@ 0x00000360) Hask of OEM_ROOT_PK */ + __IM uint32_t RESERVED2[7]; + __IOM R_OFS_DATAFLASH_CFGDLOCK_Type CFGDLOCK; /*!< (@ 0x00000380) Configuration Data Lock Bits */ + __IM uint32_t RESERVED3[11]; + + union + { + __IOM uint16_t ARCLS; /*!< (@ 0x000003C0) Anti-Rollback Counter Lock Setting */ + + struct + { + __IOM uint16_t ARCS_LK : 1; /*!< [0..0] ARC_SEC Lock */ + __IOM uint16_t ARCNS_LK : 4; /*!< [4..1] ARC_NSEC Lock */ + __IOM uint16_t ARCBL_LK : 1; /*!< [5..5] ARC_OEMBL Lock */ + uint16_t : 10; + } ARCLS_b; + }; + + union + { + __IOM uint16_t ARCCS; /*!< (@ 0x000003C2) ARCCS */ + + struct + { + __IOM uint16_t CNF_ARCNS : 2; /*!< [1..0] Configuation setting for ARC_NSEC */ + uint16_t : 14; + } ARCCS_b; + }; + __IM uint32_t RESERVED4[291]; + + union + { + __IOM uint32_t ARC_SEC[2]; /*!< (@ 0x00000850) Anti-Rollback Counter for Secure Application + * n */ + + struct + { + __IOM uint32_t ARC_SEC : 32; /*!< [31..0] ARC_SEC */ + } ARC_SEC_b[2]; + }; + + union + { + __IOM uint32_t ARC_NSEC[8]; /*!< (@ 0x00000858) Anti-Rollback Counter for Non-Secure Application */ + + struct + { + __IOM uint32_t ARC_NSEC : 32; /*!< [31..0] Anti-Rollback Counter for Non-secure Application */ + } ARC_NSEC_b[8]; + }; + + union + { + __IOM uint32_t ARC_OEMBL[2]; /*!< (@ 0x00000878) Anti-Rollback Counter for OEMBL */ + + struct + { + __IOM uint32_t ARC_OEMBL : 32; /*!< [31..0] Anti-Rollback Counter for OEM_BL Application */ + } ARC_OEMBL_b[2]; + }; +} R_OFS_DATAFLASH_Type; /*!< Size = 2176 (0x880) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #if defined(_RA_TZ_NONSECURE) + #define BASE_NS_OFFSET (BSP_FEATURE_TZ_NS_OFFSET) + #else + #define BASE_NS_OFFSET 0U + #endif + + #define R_ACMPHS0_BASE (0x40236000UL + BASE_NS_OFFSET) + #define R_ACMPHS1_BASE (0x40236100UL + BASE_NS_OFFSET) + #define R_ACMPHS2_BASE (0x40236200UL + BASE_NS_OFFSET) + #define R_ACMPHS3_BASE (0x40236300UL + BASE_NS_OFFSET) + #define R_ACMPHS4_BASE (0x40236400UL + BASE_NS_OFFSET) + #define R_ACMPHS5_BASE (0x40236500UL + BASE_NS_OFFSET) + #define R_ADC0_BASE (0x40332000UL + BASE_NS_OFFSET) + #define R_ADC1_BASE (0x40332200UL + BASE_NS_OFFSET) + #define R_PSCU_BASE (0x40204000UL + BASE_NS_OFFSET) + #define R_BUS_BASE (0x40003000UL + BASE_NS_OFFSET) + #define R_CAC_BASE (0x40202400UL + BASE_NS_OFFSET) + #define R_CANFD_BASE (0x40380000UL + BASE_NS_OFFSET) + #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) + #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) + #define R_DAC_BASE (0x40333000UL + BASE_NS_OFFSET) + #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) + #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) + #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) + #define R_DMAC1_BASE (0x4000A040UL + BASE_NS_OFFSET) + #define R_DMAC2_BASE (0x4000A080UL + BASE_NS_OFFSET) + #define R_DMAC3_BASE (0x4000A0C0UL + BASE_NS_OFFSET) + #define R_DMAC4_BASE (0x4000A100UL + BASE_NS_OFFSET) + #define R_DMAC5_BASE (0x4000A140UL + BASE_NS_OFFSET) + #define R_DMAC6_BASE (0x4000A180UL + BASE_NS_OFFSET) + #define R_DMAC7_BASE (0x4000A1C0UL + BASE_NS_OFFSET) + #define R_DOC_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_DRW_BASE (0x40344000UL + BASE_NS_OFFSET) + #define R_DTC_BASE (0x4000AC00UL + BASE_NS_OFFSET) + #define R_ELC_BASE (0x40201000UL + BASE_NS_OFFSET) + #define R_ETHERC0_BASE (0x40354100UL + BASE_NS_OFFSET) + #define R_ETHERC_EDMAC_BASE (0x40354000UL + BASE_NS_OFFSET) + #define R_FACI_HP_CMD_BASE (0x40100000UL + BASE_NS_OFFSET) + #define R_FACI_HP_BASE (0x4011E000UL + BASE_NS_OFFSET) + #define R_FCACHE_BASE (0x4001C100UL + BASE_NS_OFFSET) + #define R_GLCDC_BASE (0x40342000UL + BASE_NS_OFFSET) + #define R_GPT0_BASE (0x40322000UL + BASE_NS_OFFSET) + #define R_GPT1_BASE (0x40322100UL + BASE_NS_OFFSET) + #define R_GPT2_BASE (0x40322200UL + BASE_NS_OFFSET) + #define R_GPT3_BASE (0x40322300UL + BASE_NS_OFFSET) + #define R_GPT4_BASE (0x40322400UL + BASE_NS_OFFSET) + #define R_GPT5_BASE (0x40322500UL + BASE_NS_OFFSET) + #define R_GPT6_BASE (0x40322600UL + BASE_NS_OFFSET) + #define R_GPT7_BASE (0x40322700UL + BASE_NS_OFFSET) + #define R_GPT8_BASE (0x40322800UL + BASE_NS_OFFSET) + #define R_GPT9_BASE (0x40322900UL + BASE_NS_OFFSET) + #define R_GPT10_BASE (0x40322A00UL + BASE_NS_OFFSET) + #define R_GPT11_BASE (0x40322B00UL + BASE_NS_OFFSET) + #define R_GPT12_BASE (0x40322C00UL + BASE_NS_OFFSET) + #define R_GPT13_BASE (0x40322D00UL + BASE_NS_OFFSET) + #define R_GPT_OPS_BASE (0x40323F00UL + BASE_NS_OFFSET) + #define R_GPT_POEG0_BASE (0x40212000UL + BASE_NS_OFFSET) + #define R_GPT_POEG1_BASE (0x40212100UL + BASE_NS_OFFSET) + #define R_GPT_POEG2_BASE (0x40212200UL + BASE_NS_OFFSET) + #define R_GPT_POEG3_BASE (0x40212300UL + BASE_NS_OFFSET) + #define R_ICU_BASE (0x40006000UL + BASE_NS_OFFSET) + #define R_IIC0_BASE (0x4025E000UL + BASE_NS_OFFSET) + #define R_IIC1_BASE (0x4025E100UL + BASE_NS_OFFSET) + #define R_IIC2_BASE (0x4025E200UL + BASE_NS_OFFSET) + #define R_IWDT_BASE (0x40202200UL + BASE_NS_OFFSET) + #define R_I3C0_BASE (0x4035F000UL + BASE_NS_OFFSET) + #define R_I3C1_BASE (0x4035F100UL + BASE_NS_OFFSET) + #define R_MPU_MMPU_BASE (0x40000000UL + BASE_NS_OFFSET) + #define R_MPU_SPMON_BASE (0x40000D00UL + BASE_NS_OFFSET) + #define R_MSTP_BASE (0x40203000UL + BASE_NS_OFFSET) + #define R_PORT0_BASE (0x40400000UL + BASE_NS_OFFSET) + #define R_PORT1_BASE (0x40400020UL + BASE_NS_OFFSET) + #define R_PORT2_BASE (0x40400040UL + BASE_NS_OFFSET) + #define R_PORT3_BASE (0x40400060UL + BASE_NS_OFFSET) + #define R_PORT4_BASE (0x40400080UL + BASE_NS_OFFSET) + #define R_PORT5_BASE (0x404000A0UL + BASE_NS_OFFSET) + #define R_PORT6_BASE (0x404000C0UL + BASE_NS_OFFSET) + #define R_PORT7_BASE (0x404000E0UL + BASE_NS_OFFSET) + #define R_PORT8_BASE (0x40400100UL + BASE_NS_OFFSET) + #define R_PORT9_BASE (0x40400120UL + BASE_NS_OFFSET) + #define R_PORT10_BASE (0x40400140UL + BASE_NS_OFFSET) + #define R_PORT11_BASE (0x40400160UL + BASE_NS_OFFSET) + #define R_PORT12_BASE (0x40400180UL + BASE_NS_OFFSET) + #define R_PORT13_BASE (0x404001A0UL + BASE_NS_OFFSET) + #define R_PORT14_BASE (0x404001C0UL + BASE_NS_OFFSET) + #define R_PFS_BASE (0x40400800UL + BASE_NS_OFFSET) + #define R_PMISC_BASE (0x40400D00UL + BASE_NS_OFFSET) + #define R_RTC_BASE (0x40202000UL + BASE_NS_OFFSET) + #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_SCI9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SDHI0_BASE (0x40252000UL + BASE_NS_OFFSET) + #define R_SDHI1_BASE (0x40252400UL + BASE_NS_OFFSET) + #define R_SPI0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_SPI2_BASE (0x40072200UL + BASE_NS_OFFSET) + #define R_SRAM_BASE (0x40002000UL + BASE_NS_OFFSET) + #define R_SSI0_BASE (0x4025D000UL + BASE_NS_OFFSET) + #define R_SSI1_BASE (0x4025D100UL + BASE_NS_OFFSET) + #define R_SYSTEM_BASE (0x4001E000UL + BASE_NS_OFFSET) + #define R_TSN_CAL_BASE (0x4011B17CUL + BASE_NS_OFFSET) + #define R_TSN_CTRL_BASE (0x40235000UL + BASE_NS_OFFSET) + #define R_USB_FS0_BASE (0x40250000UL + BASE_NS_OFFSET) + #define R_WDT_BASE (0x40202600UL + BASE_NS_OFFSET) + #define R_CPSCU_BASE (0x40008000UL + BASE_NS_OFFSET) + #define R_DOC_B_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_SCI_B0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI_B1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI_B2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI_B3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI_B4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI_B9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SPI_B0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI_B1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_USB_HS0_BASE (0x40351000UL + BASE_NS_OFFSET) + #define R_XSPI0_BASE (0x40268000UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) + #define R_MIPI_PHY_BASE (0x40346C00UL + BASE_NS_OFFSET) + #define R_CEU_BASE (0x40348000UL + BASE_NS_OFFSET) + #define R_ULPT0_BASE (0x40220000UL + BASE_NS_OFFSET) + #define R_ULPT1_BASE (0x40220100UL + BASE_NS_OFFSET) + #define R_DEBUG_OCD_BASE (0x40011000UL + BASE_NS_OFFSET) + #define R_DOTF_BASE (0x40268800UL + BASE_NS_OFFSET) + #define R_AGTX0_BASE (0x40221000UL + BASE_NS_OFFSET) + #define R_AGTX1_BASE (0x40221100UL + BASE_NS_OFFSET) + #define R_AGTX2_BASE (0x40221200UL + BASE_NS_OFFSET) + #define R_AGTX3_BASE (0x40221300UL + BASE_NS_OFFSET) + #define R_AGTX4_BASE (0x40221400UL + BASE_NS_OFFSET) + #define R_AGTX5_BASE (0x40221500UL + BASE_NS_OFFSET) + #define R_AGTX6_BASE (0x40221600UL + BASE_NS_OFFSET) + #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) + #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) + #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_DOTF1_BASE (0x40268900UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) + #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) + #define R_MIPI_DSI_BASE (0x40346000UL + BASE_NS_OFFSET) + #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40044300UL + BASE_NS_OFFSET) + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE) + #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE) + #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE) + #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE) + #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE) + #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE) + #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE) + #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) + #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_MIPI_PHY ((R_MIPI_PHY_Type *) R_MIPI_PHY_BASE) + #define R_CEU ((R_CEU_Type *) R_CEU_BASE) + #define R_ULPT0 ((R_ULPT0_Type *) R_ULPT0_BASE) + #define R_ULPT1 ((R_ULPT0_Type *) R_ULPT1_BASE) + #define R_DEBUG_OCD ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE) + #define R_DOTF ((R_DOTF_Type *) R_DOTF_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_DOTF1 ((R_DOTF_Type *) R_DOTF1_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) + #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_MIPI_DSI ((R_MIPI_DSI_Type *) R_MIPI_DSI_BASE) + #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ BG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= PERI ========================================================== */ + #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */ + #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */ + #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SYNC ========================================================== */ + #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */ + #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */ + #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */ +/* ========================================================= VSIZE ========================================================= */ + #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= HSIZE ========================================================= */ + #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== BGC ========================================================== */ + #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== VEN ========================================================== */ + #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */ + #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FLMRD ========================================================= */ + #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */ + #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */ +/* ========================================================= FLM1 ========================================================== */ + #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */ + #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */ +/* ========================================================= FLM2 ========================================================== */ + #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ + #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLM3 ========================================================== */ + #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */ + #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM5 ========================================================== */ + #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */ + #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */ + #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM6 ========================================================== */ + #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */ + #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */ +/* ========================================================== AB1 ========================================================== */ + #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */ + #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */ + #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== AB2 ========================================================== */ + #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */ + #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */ + #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB3 ========================================================== */ + #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */ + #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */ + #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB4 ========================================================== */ + #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */ + #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */ + #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB5 ========================================================== */ + #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */ + #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */ + #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB6 ========================================================== */ + #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */ + #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */ + #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */ + #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */ +/* ========================================================== AB7 ========================================================== */ + #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */ + #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */ + #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */ +/* ========================================================== AB8 ========================================================== */ + #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */ + #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */ + #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */ + #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */ +/* ========================================================== AB9 ========================================================== */ + #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */ + #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */ + #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */ + #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */ + #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */ +/* ========================================================= BASE ========================================================== */ + #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */ + #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */ + #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */ +/* ======================================================== CLUTINT ======================================================== */ + #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */ + #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */ + #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */ + #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */ + #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LATCH ========================================================= */ + #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ======================================================== GAM_SW ========================================================= */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */ +/* ========================================================== LUT ========================================================== */ + #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */ +/* ========================================================= AREA ========================================================== */ + #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ OUT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VLATCH ========================================================= */ + #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */ + #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */ + #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */ + #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */ + #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */ + #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */ + #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +/* ======================================================== BRIGHT1 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BRIGHT2 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CONTRAST ======================================================== */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */ +/* ========================================================= PDTHA ========================================================= */ + #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */ + #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */ + #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */ + #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */ + #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */ + #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */ + #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */ +/* ======================================================= CLKPHASE ======================================================== */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TCON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TIM ========================================================== */ + #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */ + #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA1 ========================================================= */ + #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVB1 ========================================================= */ + #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA2 ========================================================= */ + #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STVB2 ========================================================= */ + #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHA1 ========================================================= */ + #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHB1 ========================================================= */ + #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHA2 ========================================================= */ + #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHB2 ========================================================= */ + #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================== DE =========================================================== */ + #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */ + #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSCNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DTCTEN ========================================================= */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCLR ========================================================= */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= STMON ========================================================= */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */ +/* ======================================================= PANEL_CLK ======================================================= */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CMCFGCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Pos (4UL) /*!< WPBSTMD (Bit 4) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Msk (0x10UL) /*!< WPBSTMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Pos (5UL) /*!< ARYAMD (Bit 5) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Msk (0x20UL) /*!< ARYAMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ CDBUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CDBUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_CDBUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDBUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_CDBUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_CDBUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_CDBUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_CDBUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_CDBUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CCCTLCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFGD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFGD_L ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ +/* ======================================================== CFGD_H ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CFGDLOCK ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CFGD2 ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARB ========================================================= */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARC ========================================================= */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARD ========================================================= */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARE ========================================================= */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSPAR ========================================================= */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONTROL ======================================================== */ + #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */ + #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */ + #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */ + #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */ + #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */ + #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */ + #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */ + #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */ + #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */ + #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */ + #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */ + #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */ + #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */ + #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */ + #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */ + #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */ + #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */ + #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */ + #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */ + #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */ + #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */ + #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */ + #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */ + #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */ + #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */ + #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */ + #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */ + #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */ + #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */ + #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */ + #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCTL ========================================================= */ + #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */ + #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */ + #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CACHECTL ======================================================== */ + #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */ + #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */ + #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */ + #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */ + #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */ + #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */ + #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */ + #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */ + #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */ + #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */ + #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */ + #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */ + #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */ + #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */ +/* ====================================================== HWREVISION ======================================================= */ + #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */ + #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */ + #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */ + #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */ + #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */ + #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */ + #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */ + #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */ + #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */ + #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */ +/* ======================================================== COLOR1 ========================================================= */ + #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */ + #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */ + #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */ + #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */ + #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */ +/* ======================================================== COLOR2 ========================================================= */ + #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */ + #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */ + #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */ + #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */ + #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */ +/* ======================================================== PATTERN ======================================================== */ + #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */ + #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */ +/* ======================================================== L1START ======================================================== */ + #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2START ======================================================== */ + #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3START ======================================================== */ + #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4START ======================================================== */ + #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5START ======================================================== */ + #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6START ======================================================== */ + #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1XADD ========================================================= */ + #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2XADD ========================================================= */ + #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3XADD ========================================================= */ + #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4XADD ========================================================= */ + #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5XADD ========================================================= */ + #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6XADD ========================================================= */ + #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1YADD ========================================================= */ + #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2YADD ========================================================= */ + #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3YADD ========================================================= */ + #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4YADD ========================================================= */ + #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5YADD ========================================================= */ + #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6YADD ========================================================= */ + #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1BAND ========================================================= */ + #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2BAND ========================================================= */ + #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXORIGIN ======================================================= */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXPITCH ======================================================== */ + #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */ + #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TEXMASK ======================================================== */ + #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */ + #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */ + #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */ + #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */ +/* ======================================================== LUSTART ======================================================== */ + #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */ + #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUXADD ========================================================= */ + #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */ + #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUYADD ========================================================= */ + #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */ + #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTI ======================================================== */ + #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */ + #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTF ======================================================== */ + #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */ + #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */ +/* ======================================================== LVXADDI ======================================================== */ + #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */ + #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LVYADDI ======================================================== */ + #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */ + #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVYXADDF ======================================================== */ + #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */ + #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */ + #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */ + #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */ +/* ======================================================= TEXCLADDR ======================================================= */ + #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */ + #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */ +/* ======================================================= TEXCLDATA ======================================================= */ + #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */ + #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TEXCLOFFSET ====================================================== */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== COLKEY ========================================================= */ + #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */ + #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */ + #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */ + #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */ +/* ========================================================= SIZE ========================================================== */ + #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */ + #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */ + #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */ + #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */ +/* ========================================================= PITCH ========================================================= */ + #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */ + #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */ + #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */ + #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */ +/* ======================================================== ORIGIN ========================================================= */ + #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */ + #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLISTSTART ======================================================= */ + #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */ + #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFTRIGGER ====================================================== */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== PERFCOUNT1 ======================================================= */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFCOUNT2 ======================================================= */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBWER ========================================================= */ + #define R_DRW_DBWER_BWE_Pos (2UL) /*!< BWE (Bit 2) */ + #define R_DRW_DBWER_BWE_Msk (0x4UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR30_Pos (30UL) /*!< ELSR30 (Bit 30) */ + #define R_ELC_ELCSARB_ELSR30_Msk (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARA ======================================================== */ + #define R_ELC_ELCPARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCPARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCPARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCPARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARB ======================================================== */ + #define R_ELC_ELCPARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARB_ELSR30_Pos (30UL) /*!< ELSR30 (Bit 30) */ + #define R_ELC_ELCPARB_ELSR30_Msk (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FBCADDR ======================================================== */ + #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ + #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ +/* ======================================================= FCNTSELR ======================================================== */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ====================================================== FCNTDATAR0 ======================================================= */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FCNTDATAR1 ======================================================= */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCACHEENSA_Pos (1UL) /*!< FCACHEENSA (Bit 1) */ + #define R_FCACHE_FSAR_FCACHEENSA_Msk (0x2UL) /*!< FCACHEENSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACITRSA_Pos (11UL) /*!< FACITRSA (Bit 11) */ + #define R_FCACHE_FSAR_FACITRSA_Msk (0x800UL) /*!< FACITRSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GR1_CLUT0 ======================================================= */ + #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR1_CLUT1 ======================================================= */ + #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT0 ======================================================= */ + #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT1 ======================================================= */ + #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SWIRQ_S ======================================================== */ + #define R_ICU_SWIRQ_S_SWIRQS_Pos (0UL) /*!< SWIRQS (Bit 0) */ + #define R_ICU_SWIRQ_S_SWIRQS_Msk (0x1UL) /*!< SWIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= SWIRQ_NS ======================================================== */ + #define R_ICU_SWIRQ_NS_SWIRQNS_Pos (0UL) /*!< SWIRQNS (Bit 0) */ + #define R_ICU_SWIRQ_NS_SWIRQNS_Msk (0x1UL) /*!< SWIRQNS (Bitfield-Mask: 0x01) */ +/* ======================================================== IENMIER ======================================================== */ + #define R_ICU_IENMIER_CMEN_Pos (0UL) /*!< CMEN (Bit 0) */ + #define R_ICU_IENMIER_CMEN_Msk (0x1UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IENMIER_LMEN_Pos (1UL) /*!< LMEN (Bit 1) */ + #define R_ICU_IENMIER_LMEN_Msk (0x2UL) /*!< LMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IENMIER_BUSEN_Pos (2UL) /*!< BUSEN (Bit 2) */ + #define R_ICU_IENMIER_BUSEN_Msk (0x4UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSEN_Pos (12UL) /*!< BUSEN (Bit 12) */ + #define R_ICU_NMIER_BUSEN_Msk (0x1000UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CMEN_Pos (13UL) /*!< CMEN (Bit 13) */ + #define R_ICU_NMIER_CMEN_Msk (0x2000UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LUEN_Pos (15UL) /*!< LUEN (Bit 15) */ + #define R_ICU_NMIER_LUEN_Msk (0x8000UL) /*!< LUEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSCLR_Pos (12UL) /*!< BUSCLR (Bit 12) */ + #define R_ICU_NMICLR_BUSCLR_Msk (0x1000UL) /*!< BUSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CMCLR_Pos (13UL) /*!< CMCLR (Bit 13) */ + #define R_ICU_NMICLR_CMCLR_Msk (0x2000UL) /*!< CMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LUCLR_Pos (15UL) /*!< LUCLR (Bit 15) */ + #define R_ICU_NMICLR_LUCLR_Msk (0x8000UL) /*!< LUCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_ICU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_ICU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_ICU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IRQWUPEN0_Pos (0UL) /*!< IRQWUPEN0 (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN0_Msk (0x1UL) /*!< IRQWUPEN0 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN1_Pos (1UL) /*!< IRQWUPEN1 (Bit 1) */ + #define R_ICU_WUPEN_IRQWUPEN1_Msk (0x2UL) /*!< IRQWUPEN1 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN2_Pos (2UL) /*!< IRQWUPEN2 (Bit 2) */ + #define R_ICU_WUPEN_IRQWUPEN2_Msk (0x4UL) /*!< IRQWUPEN2 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN3_Pos (3UL) /*!< IRQWUPEN3 (Bit 3) */ + #define R_ICU_WUPEN_IRQWUPEN3_Msk (0x8UL) /*!< IRQWUPEN3 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN4_Pos (4UL) /*!< IRQWUPEN4 (Bit 4) */ + #define R_ICU_WUPEN_IRQWUPEN4_Msk (0x10UL) /*!< IRQWUPEN4 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN5_Pos (5UL) /*!< IRQWUPEN5 (Bit 5) */ + #define R_ICU_WUPEN_IRQWUPEN5_Msk (0x20UL) /*!< IRQWUPEN5 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN6_Pos (6UL) /*!< IRQWUPEN6 (Bit 6) */ + #define R_ICU_WUPEN_IRQWUPEN6_Msk (0x40UL) /*!< IRQWUPEN6 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN7_Pos (7UL) /*!< IRQWUPEN7 (Bit 7) */ + #define R_ICU_WUPEN_IRQWUPEN7_Msk (0x80UL) /*!< IRQWUPEN7 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN8_Pos (8UL) /*!< IRQWUPEN8 (Bit 8) */ + #define R_ICU_WUPEN_IRQWUPEN8_Msk (0x100UL) /*!< IRQWUPEN8 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN9_Pos (9UL) /*!< IRQWUPEN9 (Bit 9) */ + #define R_ICU_WUPEN_IRQWUPEN9_Msk (0x200UL) /*!< IRQWUPEN9 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN10_Pos (10UL) /*!< IRQWUPEN10 (Bit 10) */ + #define R_ICU_WUPEN_IRQWUPEN10_Msk (0x400UL) /*!< IRQWUPEN10 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN11_Pos (11UL) /*!< IRQWUPEN11 (Bit 11) */ + #define R_ICU_WUPEN_IRQWUPEN11_Msk (0x800UL) /*!< IRQWUPEN11 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN12_Pos (12UL) /*!< IRQWUPEN12 (Bit 12) */ + #define R_ICU_WUPEN_IRQWUPEN12_Msk (0x1000UL) /*!< IRQWUPEN12 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN13_Pos (13UL) /*!< IRQWUPEN13 (Bit 13) */ + #define R_ICU_WUPEN_IRQWUPEN13_Msk (0x2000UL) /*!< IRQWUPEN13 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN14_Pos (14UL) /*!< IRQWUPEN14 (Bit 14) */ + #define R_ICU_WUPEN_IRQWUPEN14_Msk (0x4000UL) /*!< IRQWUPEN14 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN15_Pos (15UL) /*!< IRQWUPEN15 (Bit 15) */ + #define R_ICU_WUPEN_IRQWUPEN15_Msk (0x8000UL) /*!< IRQWUPEN15 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RIIC0WUPEN_Pos (31UL) /*!< RIIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_RIIC0WUPEN_Msk (0x80000000UL) /*!< RIIC0WUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_COMPHS0WUPEN_Pos (3UL) /*!< COMPHS0WUPEN (Bit 3) */ + #define R_ICU_WUPEN1_COMPHS0WUPEN_Msk (0x8UL) /*!< COMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0UWUPEN_Pos (8UL) /*!< ULP0UWUPEN (Bit 8) */ + #define R_ICU_WUPEN1_ULP0UWUPEN_Msk (0x100UL) /*!< ULP0UWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0AWUPEN_Pos (9UL) /*!< ULP0AWUPEN (Bit 9) */ + #define R_ICU_WUPEN1_ULP0AWUPEN_Msk (0x200UL) /*!< ULP0AWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0BWUPEN_Pos (10UL) /*!< ULP0BWUPEN (Bit 10) */ + #define R_ICU_WUPEN1_ULP0BWUPEN_Msk (0x400UL) /*!< ULP0BWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_I3CWUPEN_Pos (11UL) /*!< I3CWUPEN (Bit 11) */ + #define R_ICU_WUPEN1_I3CWUPEN_Msk (0x800UL) /*!< I3CWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1UWUPEN_Pos (12UL) /*!< ULP1UWUPEN (Bit 12) */ + #define R_ICU_WUPEN1_ULP1UWUPEN_Msk (0x1000UL) /*!< ULP1UWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1AWUPEN_Pos (13UL) /*!< ULP1AWUPEN (Bit 13) */ + #define R_ICU_WUPEN1_ULP1AWUPEN_Msk (0x2000UL) /*!< ULP1AWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1BWUPEN_Pos (14UL) /*!< ULP1BWUPEN (Bit 14) */ + #define R_ICU_WUPEN1_ULP1BWUPEN_Msk (0x4000UL) /*!< ULP1BWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMPRCR_NS ====================================================== */ + #define R_SRAM_SRAMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================= SRAMWTSC ======================================================== */ + #define R_SRAM_SRAMWTSC_WTEN_Pos (0UL) /*!< WTEN (Bit 0) */ + #define R_SRAM_SRAMWTSC_WTEN_Msk (0x1UL) /*!< WTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR0 ======================================================== */ + #define R_SRAM_SRAMCR0_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR0_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR0_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR0_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR0_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR0_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR1 ======================================================== */ + #define R_SRAM_SRAMCR1_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR1_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMECCRGN0 ====================================================== */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk (0x3UL) /*!< ECCRGN (Bitfield-Mask: 0x03) */ +/* ======================================================== SRAMESR ======================================================== */ + #define R_SRAM_SRAMESR_ERR00_Pos (0UL) /*!< ERR00 (Bit 0) */ + #define R_SRAM_SRAMESR_ERR00_Msk (0x1UL) /*!< ERR00 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR01_Pos (1UL) /*!< ERR01 (Bit 1) */ + #define R_SRAM_SRAMESR_ERR01_Msk (0x2UL) /*!< ERR01 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR1_Pos (2UL) /*!< ERR1 (Bit 2) */ + #define R_SRAM_SRAMESR_ERR1_Msk (0x4UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERRS_Pos (14UL) /*!< ERRS (Bit 14) */ + #define R_SRAM_SRAMESR_ERRS_Msk (0x4000UL) /*!< ERRS (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMESCLR ======================================================= */ + #define R_SRAM_SRAMESCLR_CLR00_Pos (0UL) /*!< CLR00 (Bit 0) */ + #define R_SRAM_SRAMESCLR_CLR00_Msk (0x1UL) /*!< CLR00 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR01_Pos (1UL) /*!< CLR01 (Bit 1) */ + #define R_SRAM_SRAMESCLR_CLR01_Msk (0x2UL) /*!< CLR01 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR1_Pos (2UL) /*!< CLR1 (Bit 2) */ + #define R_SRAM_SRAMESCLR_CLR1_Msk (0x4UL) /*!< CLR1 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLRS_Pos (14UL) /*!< CLRS (Bit 14) */ + #define R_SRAM_SRAMESCLR_CLRS_Msk (0x4000UL) /*!< CLRS (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMEAR0 ======================================================== */ + #define R_SRAM_SRAMEAR0_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR0_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= SRAMEAR1 ======================================================== */ + #define R_SRAM_SRAMEAR1_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR1_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= SRAMEAR2 ======================================================== */ + #define R_SRAM_SRAMEAR2_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR2_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= STBRAMCR ======================================================== */ + #define R_SRAM_STBRAMCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_STBRAMCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMEAR ======================================================= */ + #define R_SRAM_STBRAMEAR_EA_Pos (2UL) /*!< EA (Bit 2) */ + #define R_SRAM_STBRAMEAR_EA_Msk (0x3fcUL) /*!< EA (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_OPE_Pos (6UL) /*!< OPE (Bit 6) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x40UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ========================================================= SSCR2 ========================================================= */ + #define R_SYSTEM_SSCR2_SS1RSF_Pos (0UL) /*!< SS1RSF (Bit 0) */ + #define R_SYSTEM_SSCR2_SS1RSF_Msk (0x1UL) /*!< SS1RSF (Bitfield-Mask: 0x01) */ +/* ========================================================= FLSCR ========================================================= */ + #define R_SYSTEM_FLSCR_FLSWCF_Pos (0UL) /*!< FLSWCF (Bit 0) */ + #define R_SYSTEM_FLSCR_FLSWCF_Msk (0x1UL) /*!< FLSWCF (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0xf000000UL) /*!< ICK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Pos (20UL) /*!< PCKE (Bit 20) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Msk (0xf00000UL) /*!< PCKE (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0xf0000UL) /*!< BCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0xf000UL) /*!< PCKA (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0xf00UL) /*!< PCKB (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0xf0UL) /*!< PCKC (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0xfUL) /*!< PCKD (Bitfield-Mask: 0x0f) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Pos (6UL) /*!< PLLMULNF (Bit 6) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Msk (0xc0UL) /*!< PLLMULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0xff00UL) /*!< PLLMUL (Bitfield-Mask: 0xff) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Pos (4UL) /*!< TRCKSEL (Bit 4) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Msk (0x10UL) /*!< TRCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== OSCMONR ======================================================== */ + #define R_SYSTEM_OSCMONR_MOCOMON_Pos (1UL) /*!< MOCOMON (Bit 1) */ + #define R_SYSTEM_OSCMONR_MOCOMON_Msk (0x2UL) /*!< MOCOMON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Pos (2UL) /*!< LOCOMON (Bit 2) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Msk (0x4UL) /*!< LOCOMON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos (6UL) /*!< PLL2MULNF (Bit 6) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk (0xc0UL) /*!< PLL2MULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0xff00UL) /*!< PLL2MUL (Bitfield-Mask: 0xff) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Pos (0UL) /*!< PLODIVP (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Msk (0xfUL) /*!< PLODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos (4UL) /*!< PLODIVQ (Bit 4) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk (0xf0UL) /*!< PLODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Pos (8UL) /*!< PLODIVR (Bit 8) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Msk (0xf00UL) /*!< PLODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PLL2CCR2 ======================================================== */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos (0UL) /*!< PL2ODIVP (Bit 0) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk (0xfUL) /*!< PL2ODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos (4UL) /*!< PL2ODIVQ (Bit 4) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk (0xf0UL) /*!< PL2ODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos (8UL) /*!< PL2ODIVR (Bit 8) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk (0xf00UL) /*!< PL2ODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCICKDIVCR ======================================================= */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== SCICKCR ======================================================== */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Pos (0UL) /*!< SCICKSEL (Bit 0) */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Msk (0xfUL) /*!< SCICKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SPICKDIVCR ======================================================= */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== SPICKCR ======================================================== */ + #define R_SYSTEM_SPICKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SPICKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCCKDIVCR ======================================================= */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== ADCCKCR ======================================================== */ + #define R_SYSTEM_ADCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ADCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_GPTCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== LCDCKDIVCR ======================================================= */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== LCDCKCR ======================================================== */ + #define R_SYSTEM_LCDCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_LCDCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0xfUL) /*!< USBCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0xfUL) /*!< OCTACKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0xfUL) /*!< CANFDCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0xfUL) /*!< I3CCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_I3CCKCR_I3CCKREQ_Pos (6UL) /*!< I3CCKREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKREQ_Msk (0x40UL) /*!< I3CCKREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCSCR ======================================================== */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos (0UL) /*!< MOSCSOKP (Bit 0) */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk (0x1UL) /*!< MOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOSCR ======================================================== */ + #define R_SYSTEM_HOCOSCR_HOCOSOKP_Pos (0UL) /*!< HOCOSOKP (Bit 0) */ + #define R_SYSTEM_HOCOSCR_HOCOSOKP_Msk (0x1UL) /*!< HOCOSOKP (Bitfield-Mask: 0x01) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLU0RF_Pos (4UL) /*!< CLU0RF (Bit 4) */ + #define R_SYSTEM_RSTSR1_CLU0RF_Msk (0x10UL) /*!< CLU0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM0RF_Pos (5UL) /*!< LM0RF (Bit 5) */ + #define R_SYSTEM_RSTSR1_LM0RF_Msk (0x20UL) /*!< LM0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSRF_Pos (10UL) /*!< BUSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSRF_Msk (0x400UL) /*!< BUSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CMRF_Pos (14UL) /*!< CMRF (Bit 14) */ + #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ + #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ + #define R_SYSTEM_RSTSR1_NWRF_Msk (0x400000UL) /*!< NWRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRACCR ======================================================== */ + #define R_SYSTEM_SYRACCR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SYSTEM_SYRACCR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================= CRVSYSCR ======================================================== */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Pos (0UL) /*!< CRVEN (Bit 0) */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Msk (0x1UL) /*!< CRVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCTRGD ======================================================== */ + #define R_SYSTEM_PDCTRGD_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRGD_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR0 ======================================================= */ +/* ======================================================= PDRAMSCR1 ======================================================= */ +/* ======================================================= VBRSABAR ======================================================== */ + #define R_SYSTEM_VBRSABAR_SABA_Pos (0UL) /*!< SABA (Bit 0) */ + #define R_SYSTEM_VBRSABAR_SABA_Msk (0xffffUL) /*!< SABA (Bitfield-Mask: 0xffff) */ +/* ======================================================= VBRPABARS ======================================================= */ + #define R_SYSTEM_VBRPABARS_PABAS_Pos (0UL) /*!< PABAS (Bit 0) */ + #define R_SYSTEM_VBRPABARS_PABAS_Msk (0xffffUL) /*!< PABAS (Bitfield-Mask: 0xffff) */ +/* ====================================================== VBRPABARNS ======================================================= */ + #define R_SYSTEM_VBRPABARNS_PABANS_Pos (0UL) /*!< PABANS (Bit 0) */ + #define R_SYSTEM_VBRPABARNS_PABANS_Msk (0xffffUL) /*!< PABANS (Bitfield-Mask: 0xffff) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC13_Pos (13UL) /*!< NONSEC13 (Bit 13) */ + #define R_SYSTEM_CGFSAR_NONSEC13_Msk (0x2000UL) /*!< NONSEC13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_CGFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_CGFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_CGFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_CGFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_CGFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC24_Pos (24UL) /*!< NONSEC24 (Bit 24) */ + #define R_SYSTEM_CGFSAR_NONSEC24_Msk (0x1000000UL) /*!< NONSEC24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC25_Pos (25UL) /*!< NONSEC25 (Bit 25) */ + #define R_SYSTEM_CGFSAR_NONSEC25_Msk (0x2000000UL) /*!< NONSEC25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC26_Pos (26UL) /*!< NONSEC26 (Bit 26) */ + #define R_SYSTEM_CGFSAR_NONSEC26_Msk (0x4000000UL) /*!< NONSEC26 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_RSTSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LPMSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_LPMSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_LPMSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_LPMSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_LPMSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_LPMSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_LPMSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== PGCSAR ========================================================= */ + #define R_SYSTEM_PGCSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_PGCSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PGCSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_PGCSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA25_Pos (25UL) /*!< DPFSA25 (Bit 25) */ + #define R_SYSTEM_DPFSAR_DPFSA25_Msk (0x2000000UL) /*!< DPFSA25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA29_Pos (29UL) /*!< DPFSA29 (Bit 29) */ + #define R_SYSTEM_DPFSAR_DPFSA29_Msk (0x20000000UL) /*!< DPFSA29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA31_Pos (31UL) /*!< DPFSA31 (Bit 31) */ + #define R_SYSTEM_DPFSAR_DPFSA31_Msk (0x80000000UL) /*!< DPFSA31 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSCSAR ========================================================= */ + #define R_SYSTEM_RSCSAR_RSCSA0_Pos (0UL) /*!< RSCSA0 (Bit 0) */ + #define R_SYSTEM_RSCSAR_RSCSA0_Msk (0x1UL) /*!< RSCSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA1_Pos (1UL) /*!< RSCSA1 (Bit 1) */ + #define R_SYSTEM_RSCSAR_RSCSA1_Msk (0x2UL) /*!< RSCSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA2_Pos (2UL) /*!< RSCSA2 (Bit 2) */ + #define R_SYSTEM_RSCSAR_RSCSA2_Msk (0x4UL) /*!< RSCSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA3_Pos (3UL) /*!< RSCSA3 (Bit 3) */ + #define R_SYSTEM_RSCSAR_RSCSA3_Msk (0x8UL) /*!< RSCSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA4_Pos (4UL) /*!< RSCSA4 (Bit 4) */ + #define R_SYSTEM_RSCSAR_RSCSA4_Msk (0x10UL) /*!< RSCSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA5_Pos (5UL) /*!< RSCSA5 (Bit 5) */ + #define R_SYSTEM_RSCSAR_RSCSA5_Msk (0x20UL) /*!< RSCSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA6_Pos (6UL) /*!< RSCSA6 (Bit 6) */ + #define R_SYSTEM_RSCSAR_RSCSA6_Msk (0x40UL) /*!< RSCSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA7_Pos (7UL) /*!< RSCSA7 (Bit 7) */ + #define R_SYSTEM_RSCSAR_RSCSA7_Msk (0x80UL) /*!< RSCSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA8_Pos (8UL) /*!< RSCSA8 (Bit 8) */ + #define R_SYSTEM_RSCSAR_RSCSA8_Msk (0x100UL) /*!< RSCSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA9_Pos (9UL) /*!< RSCSA9 (Bit 9) */ + #define R_SYSTEM_RSCSAR_RSCSA9_Msk (0x200UL) /*!< RSCSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA10_Pos (10UL) /*!< RSCSA10 (Bit 10) */ + #define R_SYSTEM_RSCSAR_RSCSA10_Msk (0x400UL) /*!< RSCSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA11_Pos (11UL) /*!< RSCSA11 (Bit 11) */ + #define R_SYSTEM_RSCSAR_RSCSA11_Msk (0x800UL) /*!< RSCSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA12_Pos (12UL) /*!< RSCSA12 (Bit 12) */ + #define R_SYSTEM_RSCSAR_RSCSA12_Msk (0x1000UL) /*!< RSCSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA13_Pos (13UL) /*!< RSCSA13 (Bit 13) */ + #define R_SYSTEM_RSCSAR_RSCSA13_Msk (0x2000UL) /*!< RSCSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA14_Pos (14UL) /*!< RSCSA14 (Bit 14) */ + #define R_SYSTEM_RSCSAR_RSCSA14_Msk (0x4000UL) /*!< RSCSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA16_Pos (16UL) /*!< RSCSA16 (Bit 16) */ + #define R_SYSTEM_RSCSAR_RSCSA16_Msk (0x10000UL) /*!< RSCSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA17_Pos (17UL) /*!< RSCSA17 (Bit 17) */ + #define R_SYSTEM_RSCSAR_RSCSA17_Msk (0x20000UL) /*!< RSCSA17 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC5_Pos (5UL) /*!< PRC5 (Bit 5) */ + #define R_SYSTEM_PRCR_PRC5_Msk (0x20UL) /*!< PRC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== PRCR_NS ======================================================== */ + #define R_SYSTEM_PRCR_NS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_NS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_NS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_NS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_NS_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos (2UL) /*!< DCSSMODE (Bit 2) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk (0x4UL) /*!< DCSSMODE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_SRKEEP_Pos (4UL) /*!< SRKEEP (Bit 4) */ + #define R_SYSTEM_DPSBYCR_SRKEEP_Msk (0x10UL) /*!< SRKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0xffUL) /*!< WTSTS (Bitfield-Mask: 0xff) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQ0E_Pos (0UL) /*!< DIRQ0E (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQ0E_Msk (0x1UL) /*!< DIRQ0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ1E_Pos (1UL) /*!< DIRQ1E (Bit 1) */ + #define R_SYSTEM_DPSIER0_DIRQ1E_Msk (0x2UL) /*!< DIRQ1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ2E_Pos (2UL) /*!< DIRQ2E (Bit 2) */ + #define R_SYSTEM_DPSIER0_DIRQ2E_Msk (0x4UL) /*!< DIRQ2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ3E_Pos (3UL) /*!< DIRQ3E (Bit 3) */ + #define R_SYSTEM_DPSIER0_DIRQ3E_Msk (0x8UL) /*!< DIRQ3E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ4E_Pos (4UL) /*!< DIRQ4E (Bit 4) */ + #define R_SYSTEM_DPSIER0_DIRQ4E_Msk (0x10UL) /*!< DIRQ4E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ5E_Pos (5UL) /*!< DIRQ5E (Bit 5) */ + #define R_SYSTEM_DPSIER0_DIRQ5E_Msk (0x20UL) /*!< DIRQ5E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ6E_Pos (6UL) /*!< DIRQ6E (Bit 6) */ + #define R_SYSTEM_DPSIER0_DIRQ6E_Msk (0x40UL) /*!< DIRQ6E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ7E_Pos (7UL) /*!< DIRQ7E (Bit 7) */ + #define R_SYSTEM_DPSIER0_DIRQ7E_Msk (0x80UL) /*!< DIRQ7E (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQ8E_Pos (0UL) /*!< DIRQ8E (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQ8E_Msk (0x1UL) /*!< DIRQ8E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ9E_Pos (1UL) /*!< DIRQ9E (Bit 1) */ + #define R_SYSTEM_DPSIER1_DIRQ9E_Msk (0x2UL) /*!< DIRQ9E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ10E_Pos (2UL) /*!< DIRQ10E (Bit 2) */ + #define R_SYSTEM_DPSIER1_DIRQ10E_Msk (0x4UL) /*!< DIRQ10E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ11E_Pos (3UL) /*!< DIRQ11E (Bit 3) */ + #define R_SYSTEM_DPSIER1_DIRQ11E_Msk (0x8UL) /*!< DIRQ11E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ12E_Pos (4UL) /*!< DIRQ12E (Bit 4) */ + #define R_SYSTEM_DPSIER1_DIRQ12E_Msk (0x10UL) /*!< DIRQ12E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ13E_Pos (5UL) /*!< DIRQ13E (Bit 5) */ + #define R_SYSTEM_DPSIER1_DIRQ13E_Msk (0x20UL) /*!< DIRQ13E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ14E_Pos (6UL) /*!< DIRQ14E (Bit 6) */ + #define R_SYSTEM_DPSIER1_DIRQ14E_Msk (0x40UL) /*!< DIRQ14E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ15E_Pos (7UL) /*!< DIRQ15E (Bit 7) */ + #define R_SYSTEM_DPSIER1_DIRQ15E_Msk (0x80UL) /*!< DIRQ15E (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Pos (0UL) /*!< DPVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Msk (0x1UL) /*!< DPVD1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Pos (1UL) /*!< DPVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Msk (0x2UL) /*!< DPVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Pos (2UL) /*!< DULPT0IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Msk (0x4UL) /*!< DULPT0IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Pos (3UL) /*!< DULPT1IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Msk (0x8UL) /*!< DULPT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Pos (5UL) /*!< DIWDTIE (Bit 5) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Msk (0x20UL) /*!< DIWDTIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos (7UL) /*!< DVBATTADIE (Bit 7) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk (0x80UL) /*!< DVBATTADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQ0F_Pos (0UL) /*!< DIRQ0F (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQ0F_Msk (0x1UL) /*!< DIRQ0F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ1F_Pos (1UL) /*!< DIRQ1F (Bit 1) */ + #define R_SYSTEM_DPSIFR0_DIRQ1F_Msk (0x2UL) /*!< DIRQ1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ2F_Pos (2UL) /*!< DIRQ2F (Bit 2) */ + #define R_SYSTEM_DPSIFR0_DIRQ2F_Msk (0x4UL) /*!< DIRQ2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ3F_Pos (3UL) /*!< DIRQ3F (Bit 3) */ + #define R_SYSTEM_DPSIFR0_DIRQ3F_Msk (0x8UL) /*!< DIRQ3F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ4F_Pos (4UL) /*!< DIRQ4F (Bit 4) */ + #define R_SYSTEM_DPSIFR0_DIRQ4F_Msk (0x10UL) /*!< DIRQ4F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ5F_Pos (5UL) /*!< DIRQ5F (Bit 5) */ + #define R_SYSTEM_DPSIFR0_DIRQ5F_Msk (0x20UL) /*!< DIRQ5F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ6F_Pos (6UL) /*!< DIRQ6F (Bit 6) */ + #define R_SYSTEM_DPSIFR0_DIRQ6F_Msk (0x40UL) /*!< DIRQ6F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ7F_Pos (7UL) /*!< DIRQ7F (Bit 7) */ + #define R_SYSTEM_DPSIFR0_DIRQ7F_Msk (0x80UL) /*!< DIRQ7F (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQ8F_Pos (0UL) /*!< DIRQ8F (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQ8F_Msk (0x1UL) /*!< DIRQ8F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ9F_Pos (1UL) /*!< DIRQ9F (Bit 1) */ + #define R_SYSTEM_DPSIFR1_DIRQ9F_Msk (0x2UL) /*!< DIRQ9F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ10F_Pos (2UL) /*!< DIRQ10F (Bit 2) */ + #define R_SYSTEM_DPSIFR1_DIRQ10F_Msk (0x4UL) /*!< DIRQ10F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ11F_Pos (3UL) /*!< DIRQ11F (Bit 3) */ + #define R_SYSTEM_DPSIFR1_DIRQ11F_Msk (0x8UL) /*!< DIRQ11F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ12F_Pos (4UL) /*!< DIRQ12F (Bit 4) */ + #define R_SYSTEM_DPSIFR1_DIRQ12F_Msk (0x10UL) /*!< DIRQ12F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ13F_Pos (5UL) /*!< DIRQ13F (Bit 5) */ + #define R_SYSTEM_DPSIFR1_DIRQ13F_Msk (0x20UL) /*!< DIRQ13F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ14F_Pos (6UL) /*!< DIRQ14F (Bit 6) */ + #define R_SYSTEM_DPSIFR1_DIRQ14F_Msk (0x40UL) /*!< DIRQ14F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ15F_Pos (7UL) /*!< DIRQ15F (Bit 7) */ + #define R_SYSTEM_DPSIFR1_DIRQ15F_Msk (0x80UL) /*!< DIRQ15F (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos (0UL) /*!< DPVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk (0x1UL) /*!< DPVD1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos (1UL) /*!< DPVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk (0x2UL) /*!< DPVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos (2UL) /*!< DULPT0IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk (0x4UL) /*!< DULPT0IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos (3UL) /*!< DULPT1IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk (0x8UL) /*!< DULPT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos (5UL) /*!< DIWDTIF (Bit 5) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk (0x20UL) /*!< DIWDTIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos (7UL) /*!< DVBATTADIF (Bit 7) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk (0x80UL) /*!< DVBATTADIF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Pos (0UL) /*!< DIRQ0EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Msk (0x1UL) /*!< DIRQ0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Pos (1UL) /*!< DIRQ1EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Msk (0x2UL) /*!< DIRQ1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Pos (2UL) /*!< DIRQ2EG (Bit 2) */ + #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Msk (0x4UL) /*!< DIRQ2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Pos (3UL) /*!< DIRQ3EG (Bit 3) */ + #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Msk (0x8UL) /*!< DIRQ3EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Pos (4UL) /*!< DIRQ4EG (Bit 4) */ + #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Msk (0x10UL) /*!< DIRQ4EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Pos (5UL) /*!< DIRQ5EG (Bit 5) */ + #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Msk (0x20UL) /*!< DIRQ5EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Pos (6UL) /*!< DIRQ6EG (Bit 6) */ + #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Msk (0x40UL) /*!< DIRQ6EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Pos (7UL) /*!< DIRQ7EG (Bit 7) */ + #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Msk (0x80UL) /*!< DIRQ7EG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Pos (0UL) /*!< DIRQ8EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Msk (0x1UL) /*!< DIRQ8EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Pos (1UL) /*!< DIRQ9EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Msk (0x2UL) /*!< DIRQ9EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Pos (2UL) /*!< DIRQ10EG (Bit 2) */ + #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Msk (0x4UL) /*!< DIRQ10EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Pos (3UL) /*!< DIRQ11EG (Bit 3) */ + #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Msk (0x8UL) /*!< DIRQ11EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Pos (4UL) /*!< DIRQ12EG (Bit 4) */ + #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Msk (0x10UL) /*!< DIRQ12EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Pos (5UL) /*!< DIRQ13EG (Bit 5) */ + #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Msk (0x20UL) /*!< DIRQ13EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Pos (6UL) /*!< DIRQ14EG (Bit 6) */ + #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Msk (0x40UL) /*!< DIRQ14EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Pos (7UL) /*!< DIRQ15EG (Bit 7) */ + #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Msk (0x80UL) /*!< DIRQ15EG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DPVD1EG_Pos (0UL) /*!< DPVD1EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DPVD1EG_Msk (0x1UL) /*!< DPVD1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DPVD2EG_Pos (1UL) /*!< DPVD2EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DPVD2EG_Msk (0x2UL) /*!< DPVD2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD3RF_Pos (4UL) /*!< LVD3RF (Bit 4) */ + #define R_SYSTEM_RSTSR0_LVD3RF_Msk (0x10UL) /*!< LVD3RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Pos (5UL) /*!< LVD4RF (Bit 5) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Msk (0x20UL) /*!< LVD4RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Pos (6UL) /*!< LVD5RF (Bit 6) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Msk (0x40UL) /*!< LVD5RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR3 ========================================================= */ + #define R_SYSTEM_RSTSR3_OCPRF_Pos (4UL) /*!< OCPRF (Bit 4) */ + #define R_SYSTEM_RSTSR3_OCPRF_Msk (0x10UL) /*!< OCPRF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (1UL) /*!< MODRV0 (Bit 1) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0xeUL) /*!< MODRV0 (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR1 ======================================================== */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSCR ========================================================= */ + #define R_SYSTEM_LPSCR_LPMD_Pos (0UL) /*!< LPMD (Bit 0) */ + #define R_SYSTEM_LPSCR_LPMD_Msk (0xfUL) /*!< LPMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SSCR1 ========================================================= */ + #define R_SYSTEM_SSCR1_SS1FR_Pos (0UL) /*!< SS1FR (Bit 0) */ + #define R_SYSTEM_SSCR1_SS1FR_Msk (0x1UL) /*!< SS1FR (Bitfield-Mask: 0x01) */ +/* ========================================================= LVOCR ========================================================= */ + #define R_SYSTEM_LVOCR_LVO0E_Pos (0UL) /*!< LVO0E (Bit 0) */ + #define R_SYSTEM_LVOCR_LVO0E_Msk (0x1UL) /*!< LVO0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVOCR_LVO1E_Pos (1UL) /*!< LVO1E (Bit 1) */ + #define R_SYSTEM_LVOCR_LVO1E_Msk (0x2UL) /*!< LVO1E (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK0 ======================================================= */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos (0UL) /*!< IWDTMASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk (0x1UL) /*!< IWDTMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos (1UL) /*!< WDT0MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk (0x2UL) /*!< WDT0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos (2UL) /*!< SWMASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk (0x4UL) /*!< SWMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Pos (4UL) /*!< CLUP0MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Msk (0x10UL) /*!< CLUP0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos (5UL) /*!< LM0MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk (0x20UL) /*!< LM0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos (6UL) /*!< CMMASK (Bit 6) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk (0x40UL) /*!< CMMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK1 ======================================================= */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos (7UL) /*!< NWMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK1_NWMASK_Msk (0x80UL) /*!< NWMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK2 ======================================================= */ + #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Pos (0UL) /*!< LVD1MASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Msk (0x1UL) /*!< LVD1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Pos (1UL) /*!< LVD2MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Msk (0x2UL) /*!< LVD2MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Pos (2UL) /*!< LVD3MASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Msk (0x4UL) /*!< LVD3MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Pos (3UL) /*!< LVD4MASK (Bit 3) */ + #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Msk (0x8UL) /*!< LVD4MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Pos (4UL) /*!< LVD5MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Msk (0x10UL) /*!< LVD5MASK (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL1LDOCR ======================================================= */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2LDOCR ======================================================= */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= HOCOLDOCR ======================================================= */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1FCR ======================================================== */ + #define R_SYSTEM_LVD1FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD1FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2FCR ======================================================== */ + #define R_SYSTEM_LVD2FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD2FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_SOMCR_SOSEL_Pos (6UL) /*!< SOSEL (Bit 6) */ + #define R_SYSTEM_SOMCR_SOSEL_Msk (0x40UL) /*!< SOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR2 ======================================================== */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos (0UL) /*!< VDETLVL (Bit 0) */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk (0x7UL) /*!< VDETLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Pos (4UL) /*!< VDETE (Bit 4) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Msk (0x10UL) /*!< VDETE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBPSR ======================================================== */ + #define R_SYSTEM_VBTBPSR_VBPORF_Pos (0UL) /*!< VBPORF (Bit 0) */ + #define R_SYSTEM_VBTBPSR_VBPORF_Msk (0x1UL) /*!< VBPORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Pos (4UL) /*!< VBPORM (Bit 4) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Msk (0x10UL) /*!< VBPORM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Pos (5UL) /*!< BPWSWM (Bit 5) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Msk (0x20UL) /*!< BPWSWM (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTADSR ======================================================== */ + #define R_SYSTEM_VBTADSR_VBTADF0_Pos (0UL) /*!< VBTADF0 (Bit 0) */ + #define R_SYSTEM_VBTADSR_VBTADF0_Msk (0x1UL) /*!< VBTADF0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Pos (1UL) /*!< VBTADF1 (Bit 1) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Msk (0x2UL) /*!< VBTADF1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Pos (2UL) /*!< VBTADF2 (Bit 2) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Msk (0x4UL) /*!< VBTADF2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR1 ======================================================== */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos (0UL) /*!< VBTADIE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk (0x1UL) /*!< VBTADIE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos (1UL) /*!< VBTADIE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk (0x2UL) /*!< VBTADIE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos (2UL) /*!< VBTADIE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk (0x4UL) /*!< VBTADIE2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos (4UL) /*!< VBTADCLE0 (Bit 4) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk (0x10UL) /*!< VBTADCLE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos (5UL) /*!< VBTADCLE1 (Bit 5) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk (0x20UL) /*!< VBTADCLE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos (6UL) /*!< VBTADCLE2 (Bit 6) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk (0x40UL) /*!< VBTADCLE2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR2 ======================================================== */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos (0UL) /*!< VBRTCES0 (Bit 0) */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk (0x1UL) /*!< VBRTCES0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos (1UL) /*!< VBRTCES1 (Bit 1) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk (0x2UL) /*!< VBRTCES1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos (2UL) /*!< VBRTCES2 (Bit 2) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk (0x4UL) /*!< VBRTCES2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR2 ======================================================= */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos (0UL) /*!< VCH0NCE (Bit 0) */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk (0x1UL) /*!< VCH0NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos (1UL) /*!< VCH1NCE (Bit 1) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk (0x2UL) /*!< VCH1NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos (2UL) /*!< VCH2NCE (Bit 2) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk (0x4UL) /*!< VCH2NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos (4UL) /*!< VCH0EG (Bit 4) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk (0x10UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos (5UL) /*!< VCH1EG (Bit 5) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk (0x20UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos (6UL) /*!< VCH2EG (Bit 6) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk (0x40UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTIMONR ======================================================== */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Pos (0UL) /*!< VCH0MON (Bit 0) */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Msk (0x1UL) /*!< VCH0MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Pos (1UL) /*!< VCH1MON (Bit 1) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Msk (0x2UL) /*!< VCH1MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Pos (2UL) /*!< VCH2MON (Bit 2) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Msk (0x4UL) /*!< VCH2MON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR0 ======================================================== */ + #define R_SYSTEM_VBTBKR0_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR0_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR1 ======================================================== */ + #define R_SYSTEM_VBTBKR1_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR1_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR2 ======================================================== */ + #define R_SYSTEM_VBTBKR2_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR2_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR3 ======================================================== */ + #define R_SYSTEM_VBTBKR3_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR3_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR4 ======================================================== */ + #define R_SYSTEM_VBTBKR4_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR4_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR5 ======================================================== */ + #define R_SYSTEM_VBTBKR5_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR5_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR6 ======================================================== */ + #define R_SYSTEM_VBTBKR6_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR6_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR7 ======================================================== */ + #define R_SYSTEM_VBTBKR7_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR7_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR8 ======================================================== */ + #define R_SYSTEM_VBTBKR8_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR8_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR9 ======================================================== */ + #define R_SYSTEM_VBTBKR9_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR9_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR10 ======================================================== */ + #define R_SYSTEM_VBTBKR10_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR10_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR11 ======================================================== */ + #define R_SYSTEM_VBTBKR11_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR11_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR12 ======================================================== */ + #define R_SYSTEM_VBTBKR12_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR12_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR13 ======================================================== */ + #define R_SYSTEM_VBTBKR13_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR13_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR14 ======================================================== */ + #define R_SYSTEM_VBTBKR14_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR14_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR15 ======================================================== */ + #define R_SYSTEM_VBTBKR15_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR15_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR16 ======================================================== */ + #define R_SYSTEM_VBTBKR16_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR16_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR17 ======================================================== */ + #define R_SYSTEM_VBTBKR17_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR17_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR18 ======================================================== */ + #define R_SYSTEM_VBTBKR18_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR18_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR19 ======================================================== */ + #define R_SYSTEM_VBTBKR19_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR19_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR20 ======================================================== */ + #define R_SYSTEM_VBTBKR20_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR20_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR21 ======================================================== */ + #define R_SYSTEM_VBTBKR21_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR21_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR22 ======================================================== */ + #define R_SYSTEM_VBTBKR22_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR22_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR23 ======================================================== */ + #define R_SYSTEM_VBTBKR23_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR23_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR24 ======================================================== */ + #define R_SYSTEM_VBTBKR24_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR24_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR25 ======================================================== */ + #define R_SYSTEM_VBTBKR25_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR25_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR26 ======================================================== */ + #define R_SYSTEM_VBTBKR26_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR26_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR27 ======================================================== */ + #define R_SYSTEM_VBTBKR27_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR27_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR28 ======================================================== */ + #define R_SYSTEM_VBTBKR28_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR28_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR29 ======================================================== */ + #define R_SYSTEM_VBTBKR29_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR29_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR30 ======================================================== */ + #define R_SYSTEM_VBTBKR30_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR30_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR31 ======================================================== */ + #define R_SYSTEM_VBTBKR31_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR31_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR32 ======================================================== */ + #define R_SYSTEM_VBTBKR32_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR32_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR33 ======================================================== */ + #define R_SYSTEM_VBTBKR33_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR33_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR34 ======================================================== */ + #define R_SYSTEM_VBTBKR34_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR34_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR35 ======================================================== */ + #define R_SYSTEM_VBTBKR35_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR35_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR36 ======================================================== */ + #define R_SYSTEM_VBTBKR36_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR36_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR37 ======================================================== */ + #define R_SYSTEM_VBTBKR37_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR37_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR38 ======================================================== */ + #define R_SYSTEM_VBTBKR38_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR38_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR39 ======================================================== */ + #define R_SYSTEM_VBTBKR39_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR39_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR40 ======================================================== */ + #define R_SYSTEM_VBTBKR40_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR40_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR41 ======================================================== */ + #define R_SYSTEM_VBTBKR41_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR41_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR42 ======================================================== */ + #define R_SYSTEM_VBTBKR42_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR42_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR43 ======================================================== */ + #define R_SYSTEM_VBTBKR43_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR43_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR44 ======================================================== */ + #define R_SYSTEM_VBTBKR44_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR44_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR45 ======================================================== */ + #define R_SYSTEM_VBTBKR45_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR45_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR46 ======================================================== */ + #define R_SYSTEM_VBTBKR46_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR46_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR47 ======================================================== */ + #define R_SYSTEM_VBTBKR47_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR47_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR48 ======================================================== */ + #define R_SYSTEM_VBTBKR48_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR48_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR49 ======================================================== */ + #define R_SYSTEM_VBTBKR49_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR49_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR50 ======================================================== */ + #define R_SYSTEM_VBTBKR50_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR50_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR51 ======================================================== */ + #define R_SYSTEM_VBTBKR51_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR51_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR52 ======================================================== */ + #define R_SYSTEM_VBTBKR52_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR52_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR53 ======================================================== */ + #define R_SYSTEM_VBTBKR53_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR53_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR54 ======================================================== */ + #define R_SYSTEM_VBTBKR54_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR54_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR55 ======================================================== */ + #define R_SYSTEM_VBTBKR55_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR55_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR56 ======================================================== */ + #define R_SYSTEM_VBTBKR56_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR56_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR57 ======================================================== */ + #define R_SYSTEM_VBTBKR57_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR57_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR58 ======================================================== */ + #define R_SYSTEM_VBTBKR58_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR58_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR59 ======================================================== */ + #define R_SYSTEM_VBTBKR59_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR59_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR60 ======================================================== */ + #define R_SYSTEM_VBTBKR60_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR60_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR61 ======================================================== */ + #define R_SYSTEM_VBTBKR61_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR61_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR62 ======================================================== */ + #define R_SYSTEM_VBTBKR62_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR62_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR63 ======================================================== */ + #define R_SYSTEM_VBTBKR63_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR63_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR64 ======================================================== */ + #define R_SYSTEM_VBTBKR64_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR64_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR65 ======================================================== */ + #define R_SYSTEM_VBTBKR65_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR65_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR66 ======================================================== */ + #define R_SYSTEM_VBTBKR66_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR66_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR67 ======================================================== */ + #define R_SYSTEM_VBTBKR67_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR67_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR68 ======================================================== */ + #define R_SYSTEM_VBTBKR68_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR68_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR69 ======================================================== */ + #define R_SYSTEM_VBTBKR69_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR69_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR70 ======================================================== */ + #define R_SYSTEM_VBTBKR70_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR70_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR71 ======================================================== */ + #define R_SYSTEM_VBTBKR71_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR71_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR72 ======================================================== */ + #define R_SYSTEM_VBTBKR72_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR72_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR73 ======================================================== */ + #define R_SYSTEM_VBTBKR73_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR73_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR74 ======================================================== */ + #define R_SYSTEM_VBTBKR74_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR74_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR75 ======================================================== */ + #define R_SYSTEM_VBTBKR75_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR75_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR76 ======================================================== */ + #define R_SYSTEM_VBTBKR76_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR76_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR77 ======================================================== */ + #define R_SYSTEM_VBTBKR77_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR77_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR78 ======================================================== */ + #define R_SYSTEM_VBTBKR78_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR78_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR79 ======================================================== */ + #define R_SYSTEM_VBTBKR79_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR79_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR80 ======================================================== */ + #define R_SYSTEM_VBTBKR80_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR80_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR81 ======================================================== */ + #define R_SYSTEM_VBTBKR81_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR81_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR82 ======================================================== */ + #define R_SYSTEM_VBTBKR82_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR82_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR83 ======================================================== */ + #define R_SYSTEM_VBTBKR83_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR83_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR84 ======================================================== */ + #define R_SYSTEM_VBTBKR84_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR84_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR85 ======================================================== */ + #define R_SYSTEM_VBTBKR85_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR85_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR86 ======================================================== */ + #define R_SYSTEM_VBTBKR86_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR86_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR87 ======================================================== */ + #define R_SYSTEM_VBTBKR87_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR87_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR88 ======================================================== */ + #define R_SYSTEM_VBTBKR88_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR88_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR89 ======================================================== */ + #define R_SYSTEM_VBTBKR89_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR89_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR90 ======================================================== */ + #define R_SYSTEM_VBTBKR90_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR90_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR91 ======================================================== */ + #define R_SYSTEM_VBTBKR91_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR91_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR92 ======================================================== */ + #define R_SYSTEM_VBTBKR92_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR92_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR93 ======================================================== */ + #define R_SYSTEM_VBTBKR93_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR93_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR94 ======================================================== */ + #define R_SYSTEM_VBTBKR94_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR94_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR95 ======================================================== */ + #define R_SYSTEM_VBTBKR95_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR95_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR96 ======================================================== */ + #define R_SYSTEM_VBTBKR96_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR96_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR97 ======================================================== */ + #define R_SYSTEM_VBTBKR97_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR97_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR98 ======================================================== */ + #define R_SYSTEM_VBTBKR98_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR98_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR99 ======================================================== */ + #define R_SYSTEM_VBTBKR99_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR99_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR100 ======================================================= */ + #define R_SYSTEM_VBTBKR100_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR100_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR101 ======================================================= */ + #define R_SYSTEM_VBTBKR101_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR101_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR102 ======================================================= */ + #define R_SYSTEM_VBTBKR102_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR102_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR103 ======================================================= */ + #define R_SYSTEM_VBTBKR103_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR103_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR104 ======================================================= */ + #define R_SYSTEM_VBTBKR104_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR104_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR105 ======================================================= */ + #define R_SYSTEM_VBTBKR105_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR105_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR106 ======================================================= */ + #define R_SYSTEM_VBTBKR106_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR106_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR107 ======================================================= */ + #define R_SYSTEM_VBTBKR107_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR107_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR108 ======================================================= */ + #define R_SYSTEM_VBTBKR108_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR108_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR109 ======================================================= */ + #define R_SYSTEM_VBTBKR109_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR109_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR110 ======================================================= */ + #define R_SYSTEM_VBTBKR110_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR110_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR111 ======================================================= */ + #define R_SYSTEM_VBTBKR111_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR111_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR112 ======================================================= */ + #define R_SYSTEM_VBTBKR112_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR112_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR113 ======================================================= */ + #define R_SYSTEM_VBTBKR113_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR113_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR114 ======================================================= */ + #define R_SYSTEM_VBTBKR114_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR114_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR115 ======================================================= */ + #define R_SYSTEM_VBTBKR115_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR115_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR116 ======================================================= */ + #define R_SYSTEM_VBTBKR116_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR116_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR117 ======================================================= */ + #define R_SYSTEM_VBTBKR117_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR117_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR118 ======================================================= */ + #define R_SYSTEM_VBTBKR118_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR118_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR119 ======================================================= */ + #define R_SYSTEM_VBTBKR119_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR119_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR120 ======================================================= */ + #define R_SYSTEM_VBTBKR120_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR120_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR121 ======================================================= */ + #define R_SYSTEM_VBTBKR121_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR121_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR122 ======================================================= */ + #define R_SYSTEM_VBTBKR122_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR122_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR123 ======================================================= */ + #define R_SYSTEM_VBTBKR123_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR123_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR124 ======================================================= */ + #define R_SYSTEM_VBTBKR124_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR124_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR125 ======================================================= */ + #define R_SYSTEM_VBTBKR125_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR125_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR126 ======================================================= */ + #define R_SYSTEM_VBTBKR126_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR126_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR127 ======================================================= */ + #define R_SYSTEM_VBTBKR127_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR127_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */ + #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */ + #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */ + #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= DOSR ========================================================== */ + #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */ + #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSCR ========================================================= */ + #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */ + #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ======================================================== DODSR0 ========================================================= */ +/* ======================================================== DODSR1 ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ======================================================== RDR_BY ========================================================= */ + #define R_SCI_B0_RDR_BY_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_BY_RDAT_Msk (0xffUL) /*!< RDAT (Bitfield-Mask: 0xff) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== TDR_BY ========================================================= */ + #define R_SCI_B0_TDR_BY_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_BY_TDAT_Msk (0xffUL) /*!< TDAT (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_SCKSEL_Pos (19UL) /*!< SCKSEL (Bit 19) */ + #define R_SCI_B0_CCR4_SCKSEL_Msk (0x80000UL) /*!< SCKSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= CESR ========================================================== */ + #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */ + #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */ + #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCR ========================================================== */ + #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */ + #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */ + #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */ + #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */ + #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */ + #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */ + #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */ + #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================= XCR0 ========================================================== */ + #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */ + #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */ + #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */ + #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */ + #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */ + #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */ + #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */ + #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */ + #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */ + #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */ + #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */ + #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */ + #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */ +/* ========================================================= XCR1 ========================================================== */ + #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */ + #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */ + #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */ + #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */ + #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */ + #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */ +/* ========================================================= XCR2 ========================================================== */ + #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */ + #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */ + #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */ + #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================== MSR ========================================================== */ + #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */ + #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */ + #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= XSR0 ========================================================== */ + #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */ + #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */ + #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */ + #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */ + #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */ + #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */ + #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */ + #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */ + #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */ + #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */ + #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */ + #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */ + #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */ +/* ========================================================= XSR1 ========================================================== */ + #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */ + #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ +/* ========================================================= MFCLR ========================================================= */ + #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */ + #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */ + #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */ + #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */ + #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */ +/* ========================================================= XFCLR ========================================================= */ + #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */ + #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */ + #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */ + #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */ + #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */ + #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */ + #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */ + #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */ + #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDECR ========================================================= */ + #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */ + #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */ + #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */ + #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */ + #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */ + #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */ + #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */ + #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */ + #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */ + #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD0 ========================================================= */ + #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD1 ========================================================= */ + #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD2 ========================================================= */ + #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD3 ========================================================= */ + #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD4 ========================================================= */ + #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD5 ========================================================= */ + #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD6 ========================================================= */ + #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD7 ========================================================= */ + #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */ + #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */ + #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */ + #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */ + #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */ + #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */ + #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */ + #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */ + #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */ + #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */ + #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */ + #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */ + #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */ + #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */ + #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */ + #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */ + #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */ + #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */ + #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */ + #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Pos (0UL) /*!< CKSFTCS0 (Bit 0) */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Msk (0x1fUL) /*!< CKSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Pos (16UL) /*!< CKSFTCS1 (Bit 16) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Msk (0x1f0000UL) /*!< CKSFTCS1 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_ARBMD_Pos (0UL) /*!< ARBMD (Bit 0) */ + #define R_XSPI0_COMCFG_ARBMD_Msk (0x3UL) /*!< ARBMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Pos (4UL) /*!< ECSINTOUTEN (Bit 4) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Msk (0x30UL) /*!< ECSINTOUTEN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ======================================================== BMCFGCH ======================================================== */ + #define R_XSPI0_BMCFGCH_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFGCH_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFGCH_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFGCH_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Pos (24UL) /*!< CMBTIM (Bit 24) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Msk (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== ABMCFG ========================================================= */ + #define R_XSPI0_ABMCFG_ODRMD_Pos (0UL) /*!< ODRMD (Bit 0) */ + #define R_XSPI0_ABMCFG_ODRMD_Msk (0x3UL) /*!< ODRMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_ABMCFG_CHSEL_Pos (16UL) /*!< CHSEL (Bit 16) */ + #define R_XSPI0_ABMCFG_CHSEL_Msk (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Pos (0UL) /*!< CH0CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Msk (0x3UL) /*!< CH0CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Pos (2UL) /*!< CH0CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Msk (0xcUL) /*!< CH0CS1ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Pos (4UL) /*!< CH1CS0ACC (Bit 4) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Msk (0x30UL) /*!< CH1CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Pos (6UL) /*!< CH1CS1ACC (Bit 6) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Msk (0xc0UL) /*!< CH1CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Pos (8UL) /*!< MWRPUSHCH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Msk (0x100UL) /*!< MWRPUSHCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Pos (10UL) /*!< PBUFCLRCH (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Msk (0x400UL) /*!< PBUFCLRCH (Bitfield-Mask: 0x01) */ +/* ======================================================== CMCTLCH ======================================================== */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTLCH_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS_Pos (0UL) /*!< WPCS (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS_Msk (0x1UL) /*!< WPCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS_Pos (16UL) /*!< RSTCS (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS_Msk (0x10000UL) /*!< RSTCS (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACCCH_Pos (0UL) /*!< MEMACCCH (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACCCH_Msk (0x1UL) /*!< MEMACCCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNECH_Pos (4UL) /*!< PBUFNECH (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNECH_Msk (0x10UL) /*!< PBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Pos (6UL) /*!< WRBUFNECH (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Msk (0x40UL) /*!< WRBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS_Pos (16UL) /*!< ECSCS (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS_Msk (0x10000UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS_Pos (17UL) /*!< INTCS (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS_Msk (0x20000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS_Pos (18UL) /*!< RSTOCS (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS_Msk (0x40000UL) /*!< RSTOCS (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS_Pos (4UL) /*!< DSTOCS (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS_Msk (0x10UL) /*!< DSTOCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS_Pos (8UL) /*!< ECSCS (Bit 8) */ + #define R_XSPI0_INTS_ECSCS_Msk (0x100UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS_Pos (12UL) /*!< INTCS (Bit 12) */ + #define R_XSPI0_INTS_INTCS_Msk (0x1000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOFCH_Pos (16UL) /*!< BRGOFCH (Bit 16) */ + #define R_XSPI0_INTS_BRGOFCH_Msk (0x10000UL) /*!< BRGOFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUFCH_Pos (18UL) /*!< BRGUFCH (Bit 18) */ + #define R_XSPI0_INTS_BRGUFCH_Msk (0x40000UL) /*!< BRGUFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERRCH_Pos (20UL) /*!< BUSERRCH (Bit 20) */ + #define R_XSPI0_INTS_BUSERRCH_Msk (0x100000UL) /*!< BUSERRCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS_Pos (28UL) /*!< CAFAILCS (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS_Msk (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS_Pos (30UL) /*!< CASUCCS (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS_Msk (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCSC_Pos (4UL) /*!< DSTOCSC (Bit 4) */ + #define R_XSPI0_INTC_DSTOCSC_Msk (0x10UL) /*!< DSTOCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCSC_Pos (8UL) /*!< ECSCSC (Bit 8) */ + #define R_XSPI0_INTC_ECSCSC_Msk (0x100UL) /*!< ECSCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCSC_Pos (12UL) /*!< INTCSC (Bit 12) */ + #define R_XSPI0_INTC_INTCSC_Msk (0x1000UL) /*!< INTCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFCHC_Pos (16UL) /*!< BRGOFCHC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFCHC_Msk (0x10000UL) /*!< BRGOFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFCHC_Pos (18UL) /*!< BRGUFCHC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFCHC_Msk (0x40000UL) /*!< BRGUFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRCHC_Pos (20UL) /*!< BUSERRCHC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRCHC_Msk (0x100000UL) /*!< BUSERRCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCSC_Pos (28UL) /*!< CAFAILCSC (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCSC_Msk (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCSC_Pos (30UL) /*!< CASUCCSC (Bit 30) */ + #define R_XSPI0_INTC_CASUCCSC_Msk (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCSE_Pos (4UL) /*!< DSTOCSE (Bit 4) */ + #define R_XSPI0_INTE_DSTOCSE_Msk (0x10UL) /*!< DSTOCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCSE_Pos (8UL) /*!< ECSCSE (Bit 8) */ + #define R_XSPI0_INTE_ECSCSE_Msk (0x100UL) /*!< ECSCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCSE_Pos (12UL) /*!< INTCSE (Bit 12) */ + #define R_XSPI0_INTE_INTCSE_Msk (0x1000UL) /*!< INTCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFCHE_Pos (16UL) /*!< BRGOFCHE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFCHE_Msk (0x10000UL) /*!< BRGOFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFCHE_Pos (18UL) /*!< BRGUFCHE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFCHE_Msk (0x40000UL) /*!< BRGUFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRCHE_Pos (20UL) /*!< BUSERRCHE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRCHE_Msk (0x100000UL) /*!< BUSERRCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCSE_Pos (28UL) /*!< CAFAILCSE (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCSE_Msk (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCSE_Pos (30UL) /*!< CASUCCSE (Bit 30) */ + #define R_XSPI0_INTE_CASUCCSE_Msk (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DPHYREFCR ======================================================= */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Pos (0UL) /*!< RFREQ (Bit 0) */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Msk (0xffUL) /*!< RFREQ (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYPLFCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Pos (0UL) /*!< IDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Msk (0x3UL) /*!< IDIV (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Pos (8UL) /*!< NFMUL (Bit 8) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Msk (0x300UL) /*!< NFMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Pos (12UL) /*!< PMUL (Bit 12) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Msk (0x3000UL) /*!< PMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Pos (16UL) /*!< NMUL (Bit 16) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Msk (0x1ff0000UL) /*!< NMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================= DPHYPLOCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYESCCR ======================================================= */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Pos (0UL) /*!< ESCDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Msk (0x1fUL) /*!< ESCDIV (Bitfield-Mask: 0x1f) */ +/* ======================================================= DPHYPWRCR ======================================================= */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Pos (0UL) /*!< PWRSEN (Bit 0) */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Msk (0x1UL) /*!< PWRSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYSFR ======================================================== */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Pos (0UL) /*!< PWRSF (Bit 0) */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Msk (0x1UL) /*!< PWRSF (Bitfield-Mask: 0x01) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Pos (8UL) /*!< PLLSF (Bit 8) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Msk (0x100UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYOCR ======================================================== */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Pos (0UL) /*!< DPHYEN (Bit 0) */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Msk (0x1UL) /*!< DPHYEN (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYTIM1 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Pos (0UL) /*!< TINIT (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Msk (0x7ffffUL) /*!< TINIT (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DPHYTIM2 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Pos (0UL) /*!< TCLKPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Msk (0xffUL) /*!< TCLKPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Pos (8UL) /*!< TCLKSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Msk (0xff00UL) /*!< TCLKSETT (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Pos (16UL) /*!< TCLKMISS (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Msk (0xff0000UL) /*!< TCLKMISS (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM3 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Pos (0UL) /*!< THSPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Msk (0xffUL) /*!< THSPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Pos (8UL) /*!< THSSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Msk (0xff00UL) /*!< THSSETT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM4 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Pos (0UL) /*!< TCLKZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Msk (0xffUL) /*!< TCLKZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Pos (8UL) /*!< TCLKPRE (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Msk (0xff00UL) /*!< TCLKPRE (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Pos (16UL) /*!< TCLKPOST (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Msk (0xff0000UL) /*!< TCLKPOST (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Pos (24UL) /*!< TCLKTRL (Bit 24) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Msk (0xff000000UL) /*!< TCLKTRL (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM5 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Pos (0UL) /*!< THSZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Msk (0xffUL) /*!< THSZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Pos (8UL) /*!< THSTRL (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Msk (0xff00UL) /*!< THSTRL (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Pos (16UL) /*!< THSEXIT (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Msk (0xff0000UL) /*!< THSEXIT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM6 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Pos (0UL) /*!< TLPX (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Msk (0xffUL) /*!< TLPX (Bitfield-Mask: 0xff) */ +/* ======================================================== DPHYMDC ======================================================== */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Pos (0UL) /*!< MASTEREN (Bit 0) */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Msk (0x1UL) /*!< MASTEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CAPSR ========================================================= */ + #define R_CEU_CAPSR_CE_Pos (0UL) /*!< CE (Bit 0) */ + #define R_CEU_CAPSR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPSR_CPKIL_Pos (16UL) /*!< CPKIL (Bit 16) */ + #define R_CEU_CAPSR_CPKIL_Msk (0x10000UL) /*!< CPKIL (Bitfield-Mask: 0x01) */ +/* ========================================================= CAPCR ========================================================= */ + #define R_CEU_CAPCR_CTNCP_Pos (16UL) /*!< CTNCP (Bit 16) */ + #define R_CEU_CAPCR_CTNCP_Msk (0x10000UL) /*!< CTNCP (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPCR_MTCM_Pos (20UL) /*!< MTCM (Bit 20) */ + #define R_CEU_CAPCR_MTCM_Msk (0x300000UL) /*!< MTCM (Bitfield-Mask: 0x03) */ + #define R_CEU_CAPCR_FDRP_Pos (24UL) /*!< FDRP (Bit 24) */ + #define R_CEU_CAPCR_FDRP_Msk (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff) */ +/* ========================================================= CAMCR ========================================================= */ + #define R_CEU_CAMCR_HDPOL_Pos (0UL) /*!< HDPOL (Bit 0) */ + #define R_CEU_CAMCR_HDPOL_Msk (0x1UL) /*!< HDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDPOL_Pos (1UL) /*!< VDPOL (Bit 1) */ + #define R_CEU_CAMCR_VDPOL_Msk (0x2UL) /*!< VDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_JPG_Pos (4UL) /*!< JPG (Bit 4) */ + #define R_CEU_CAMCR_JPG_Msk (0x30UL) /*!< JPG (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTARY_Pos (8UL) /*!< DTARY (Bit 8) */ + #define R_CEU_CAMCR_DTARY_Msk (0x300UL) /*!< DTARY (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTIF_Pos (12UL) /*!< DTIF (Bit 12) */ + #define R_CEU_CAMCR_DTIF_Msk (0x1000UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDPOL_Pos (16UL) /*!< FLDPOL (Bit 16) */ + #define R_CEU_CAMCR_FLDPOL_Msk (0x10000UL) /*!< FLDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_DSEL_Pos (24UL) /*!< DSEL (Bit 24) */ + #define R_CEU_CAMCR_DSEL_Msk (0x1000000UL) /*!< DSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDSEL_Pos (25UL) /*!< FLDSEL (Bit 25) */ + #define R_CEU_CAMCR_FLDSEL_Msk (0x2000000UL) /*!< FLDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_HDSEL_Pos (26UL) /*!< HDSEL (Bit 26) */ + #define R_CEU_CAMCR_HDSEL_Msk (0x4000000UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDSEL_Pos (27UL) /*!< VDSEL (Bit 27) */ + #define R_CEU_CAMCR_VDSEL_Msk (0x8000000UL) /*!< VDSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCYR ========================================================= */ + #define R_CEU_CMCYR_HCYL_Pos (0UL) /*!< HCYL (Bit 0) */ + #define R_CEU_CMCYR_HCYL_Msk (0x3fffUL) /*!< HCYL (Bitfield-Mask: 0x3fff) */ + #define R_CEU_CMCYR_VCYL_Pos (16UL) /*!< VCYL (Bit 16) */ + #define R_CEU_CMCYR_VCYL_Msk (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CAMOR ========================================================= */ + #define R_CEU_CAMOR_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAPWR ========================================================= */ + #define R_CEU_CAPWR_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAIFR ========================================================= */ + #define R_CEU_CAIFR_FCI_Pos (0UL) /*!< FCI (Bit 0) */ + #define R_CEU_CAIFR_FCI_Msk (0x3UL) /*!< FCI (Bitfield-Mask: 0x03) */ + #define R_CEU_CAIFR_CIM_Pos (4UL) /*!< CIM (Bit 4) */ + #define R_CEU_CAIFR_CIM_Msk (0x10UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_CEU_CAIFR_IFS_Pos (8UL) /*!< IFS (Bit 8) */ + #define R_CEU_CAIFR_IFS_Msk (0x100UL) /*!< IFS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCNTR ========================================================= */ + #define R_CEU_CRCNTR_RC_Pos (0UL) /*!< RC (Bit 0) */ + #define R_CEU_CRCNTR_RC_Msk (0x1UL) /*!< RC (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_CEU_CRCNTR_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RVS_Pos (4UL) /*!< RVS (Bit 4) */ + #define R_CEU_CRCNTR_RVS_Msk (0x10UL) /*!< RVS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCMPR ========================================================= */ + #define R_CEU_CRCMPR_RA_Pos (0UL) /*!< RA (Bit 0) */ + #define R_CEU_CRCMPR_RA_Msk (0x1UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ========================================================= CFLCR ========================================================= */ + #define R_CEU_CFLCR_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFSZR ========================================================= */ + #define R_CEU_CFSZR_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ========================================================= CDWDR ========================================================= */ + #define R_CEU_CDWDR_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ========================================================= CDAYR ========================================================= */ + #define R_CEU_CDAYR_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDACR ========================================================= */ + #define R_CEU_CDACR_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBYR ========================================================= */ + #define R_CEU_CDBYR_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBCR ========================================================= */ + #define R_CEU_CDBCR_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CBDSR ========================================================= */ + #define R_CEU_CBDSR_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= CFWCR ========================================================= */ + #define R_CEU_CFWCR_FWE_Pos (0UL) /*!< FWE (Bit 0) */ + #define R_CEU_CFWCR_FWE_Msk (0x1UL) /*!< FWE (Bitfield-Mask: 0x01) */ + #define R_CEU_CFWCR_FWV_Pos (5UL) /*!< FWV (Bit 5) */ + #define R_CEU_CFWCR_FWV_Msk (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff) */ +/* ========================================================= CLFCR ========================================================= */ + #define R_CEU_CLFCR_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ========================================================= CDOCR ========================================================= */ + #define R_CEU_CDOCR_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ========================================================= CEIER ========================================================= */ + #define R_CEU_CEIER_CPEIE_Pos (0UL) /*!< CPEIE (Bit 0) */ + #define R_CEU_CEIER_CPEIE_Msk (0x1UL) /*!< CPEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CFEIE_Pos (1UL) /*!< CFEIE (Bit 1) */ + #define R_CEU_CEIER_CFEIE_Msk (0x2UL) /*!< CFEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGRWIE_Pos (4UL) /*!< IGRWIE (Bit 4) */ + #define R_CEU_CEIER_IGRWIE_Msk (0x10UL) /*!< IGRWIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_HDIE_Pos (8UL) /*!< HDIE (Bit 8) */ + #define R_CEU_CEIER_HDIE_Msk (0x100UL) /*!< HDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VDIE_Pos (9UL) /*!< VDIE (Bit 9) */ + #define R_CEU_CEIER_VDIE_Msk (0x200UL) /*!< VDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE1IE_Pos (12UL) /*!< CPBE1IE (Bit 12) */ + #define R_CEU_CEIER_CPBE1IE_Msk (0x1000UL) /*!< CPBE1IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE2IE_Pos (13UL) /*!< CPBE2IE (Bit 13) */ + #define R_CEU_CEIER_CPBE2IE_Msk (0x2000UL) /*!< CPBE2IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE3IE_Pos (14UL) /*!< CPBE3IE (Bit 14) */ + #define R_CEU_CEIER_CPBE3IE_Msk (0x4000UL) /*!< CPBE3IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE4IE_Pos (15UL) /*!< CPBE4IE (Bit 15) */ + #define R_CEU_CEIER_CPBE4IE_Msk (0x8000UL) /*!< CPBE4IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CDTOFIE_Pos (16UL) /*!< CDTOFIE (Bit 16) */ + #define R_CEU_CEIER_CDTOFIE_Msk (0x10000UL) /*!< CDTOFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGHSIE_Pos (17UL) /*!< IGHSIE (Bit 17) */ + #define R_CEU_CEIER_IGHSIE_Msk (0x20000UL) /*!< IGHSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGVSIE_Pos (18UL) /*!< IGVSIE (Bit 18) */ + #define R_CEU_CEIER_IGVSIE_Msk (0x40000UL) /*!< IGVSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VBPIE_Pos (20UL) /*!< VBPIE (Bit 20) */ + #define R_CEU_CEIER_VBPIE_Msk (0x100000UL) /*!< VBPIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_FWFIE_Pos (23UL) /*!< FWFIE (Bit 23) */ + #define R_CEU_CEIER_FWFIE_Msk (0x800000UL) /*!< FWFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NHDIE_Pos (24UL) /*!< NHDIE (Bit 24) */ + #define R_CEU_CEIER_NHDIE_Msk (0x1000000UL) /*!< NHDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NVDIE_Pos (25UL) /*!< NVDIE (Bit 25) */ + #define R_CEU_CEIER_NVDIE_Msk (0x2000000UL) /*!< NVDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETCR ========================================================= */ + #define R_CEU_CETCR_CPE_Pos (0UL) /*!< CPE (Bit 0) */ + #define R_CEU_CETCR_CPE_Msk (0x1UL) /*!< CPE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CFE_Pos (1UL) /*!< CFE (Bit 1) */ + #define R_CEU_CETCR_CFE_Msk (0x2UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGRW_Pos (4UL) /*!< IGRW (Bit 4) */ + #define R_CEU_CETCR_IGRW_Msk (0x10UL) /*!< IGRW (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_HD_Pos (8UL) /*!< HD (Bit 8) */ + #define R_CEU_CETCR_HD_Msk (0x100UL) /*!< HD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VD_Pos (9UL) /*!< VD (Bit 9) */ + #define R_CEU_CETCR_VD_Msk (0x200UL) /*!< VD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE1_Pos (12UL) /*!< CPBE1 (Bit 12) */ + #define R_CEU_CETCR_CPBE1_Msk (0x1000UL) /*!< CPBE1 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE2_Pos (13UL) /*!< CPBE2 (Bit 13) */ + #define R_CEU_CETCR_CPBE2_Msk (0x2000UL) /*!< CPBE2 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE3_Pos (14UL) /*!< CPBE3 (Bit 14) */ + #define R_CEU_CETCR_CPBE3_Msk (0x4000UL) /*!< CPBE3 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE4_Pos (15UL) /*!< CPBE4 (Bit 15) */ + #define R_CEU_CETCR_CPBE4_Msk (0x8000UL) /*!< CPBE4 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CDTOF_Pos (16UL) /*!< CDTOF (Bit 16) */ + #define R_CEU_CETCR_CDTOF_Msk (0x10000UL) /*!< CDTOF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGHS_Pos (17UL) /*!< IGHS (Bit 17) */ + #define R_CEU_CETCR_IGHS_Msk (0x20000UL) /*!< IGHS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGVS_Pos (18UL) /*!< IGVS (Bit 18) */ + #define R_CEU_CETCR_IGVS_Msk (0x40000UL) /*!< IGVS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VBP_Pos (20UL) /*!< VBP (Bit 20) */ + #define R_CEU_CETCR_VBP_Msk (0x100000UL) /*!< VBP (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_FWF_Pos (23UL) /*!< FWF (Bit 23) */ + #define R_CEU_CETCR_FWF_Msk (0x800000UL) /*!< FWF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NHD_Pos (24UL) /*!< NHD (Bit 24) */ + #define R_CEU_CETCR_NHD_Msk (0x1000000UL) /*!< NHD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NVD_Pos (25UL) /*!< NVD (Bit 25) */ + #define R_CEU_CETCR_NVD_Msk (0x2000000UL) /*!< NVD (Bitfield-Mask: 0x01) */ +/* ========================================================= CSTSR ========================================================= */ + #define R_CEU_CSTSR_CPTON_Pos (0UL) /*!< CPTON (Bit 0) */ + #define R_CEU_CSTSR_CPTON_Msk (0x1UL) /*!< CPTON (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CPFLD_Pos (16UL) /*!< CPFLD (Bit 16) */ + #define R_CEU_CSTSR_CPFLD_Msk (0x10000UL) /*!< CPFLD (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CRST_Pos (24UL) /*!< CRST (Bit 24) */ + #define R_CEU_CSTSR_CRST_Msk (0x1000000UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CDSSR ========================================================= */ + #define R_CEU_CDSSR_CDSS_Pos (0UL) /*!< CDSS (Bit 0) */ + #define R_CEU_CDSSR_CDSS_Msk (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDAYR2 ========================================================= */ + #define R_CEU_CDAYR2_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR2 ========================================================= */ + #define R_CEU_CDACR2_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR2 ========================================================= */ + #define R_CEU_CDBYR2_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR2 ========================================================= */ + #define R_CEU_CDBCR2_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== AXIBUSCTL2 ======================================================= */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Pos (0UL) /*!< AWCACHE (Bit 0) */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Msk (0xfUL) /*!< AWCACHE (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAMOR_B ======================================================== */ + #define R_CEU_CAMOR_B_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_B_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_B_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_B_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_B ======================================================== */ + #define R_CEU_CAPWR_B_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_B_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_B_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_B_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_B ======================================================== */ + #define R_CEU_CFLCR_B_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_B_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_B_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_B_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_B_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_B_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_B ======================================================== */ + #define R_CEU_CFSZR_B_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_B_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_B_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_B_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_B ======================================================== */ + #define R_CEU_CDWDR_B_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_B_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_B ======================================================== */ + #define R_CEU_CDAYR_B_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_B_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_B ======================================================== */ + #define R_CEU_CDACR_B_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_B_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_B ======================================================== */ + #define R_CEU_CDBYR_B_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_B_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_B ======================================================== */ + #define R_CEU_CDBCR_B_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_B_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_B ======================================================== */ + #define R_CEU_CBDSR_B_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_B_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_B ======================================================== */ + #define R_CEU_CLFCR_B_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_B_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_B ======================================================== */ + #define R_CEU_CDOCR_B_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_B_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_B_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_B_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_B_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_B_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_B ======================================================== */ + #define R_CEU_CDAYR2_B_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_B_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_B ======================================================== */ + #define R_CEU_CDACR2_B_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_B_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_B ======================================================== */ + #define R_CEU_CDBYR2_B_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_B_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_B ======================================================== */ + #define R_CEU_CDBCR2_B_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_B_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAMOR_M ======================================================== */ + #define R_CEU_CAMOR_M_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_M_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_M_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_M_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_M ======================================================== */ + #define R_CEU_CAPWR_M_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_M_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_M_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_M_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_M ======================================================== */ + #define R_CEU_CFLCR_M_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_M_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_M_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_M_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_M_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_M_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_M ======================================================== */ + #define R_CEU_CFSZR_M_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_M_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_M_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_M_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_M ======================================================== */ + #define R_CEU_CDWDR_M_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_M_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_M ======================================================== */ + #define R_CEU_CDAYR_M_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_M_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_M ======================================================== */ + #define R_CEU_CDACR_M_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_M_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_M ======================================================== */ + #define R_CEU_CDBYR_M_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_M_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_M ======================================================== */ + #define R_CEU_CDBCR_M_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_M_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_M ======================================================== */ + #define R_CEU_CBDSR_M_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_M_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_M ======================================================== */ + #define R_CEU_CLFCR_M_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_M_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_M ======================================================== */ + #define R_CEU_CDOCR_M_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_M_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_M_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_M_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_M_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_M_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_M ======================================================== */ + #define R_CEU_CDAYR2_M_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_M_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_M ======================================================== */ + #define R_CEU_CDACR2_M_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_M_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_M ======================================================== */ + #define R_CEU_CDBYR2_M_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_M_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_M ======================================================== */ + #define R_CEU_CDBCR2_M_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_M_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ULPTCNT ======================================================== */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Pos (0UL) /*!< ULPTCNT (Bit 0) */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Msk (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMA ======================================================== */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Pos (0UL) /*!< ULPTCMA (Bit 0) */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Msk (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMB ======================================================== */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Pos (0UL) /*!< ULPTCMB (Bit 0) */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Msk (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCR ========================================================= */ + #define R_ULPT0_ULPTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_ULPT0_ULPTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_ULPT0_ULPTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_ULPT0_ULPTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_ULPT0_ULPTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_ULPT0_ULPTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_ULPT0_ULPTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR1 ======================================================== */ + #define R_ULPT0_ULPTMR1_TMOD1_Pos (1UL) /*!< TMOD1 (Bit 1) */ + #define R_ULPT0_ULPTMR1_TMOD1_Msk (0x2UL) /*!< TMOD1 (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TCK1_Pos (5UL) /*!< TCK1 (Bit 5) */ + #define R_ULPT0_ULPTMR1_TCK1_Msk (0x20UL) /*!< TCK1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR2 ======================================================== */ + #define R_ULPT0_ULPTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_ULPT0_ULPTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_ULPT0_ULPTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_ULPT0_ULPTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR3 ======================================================== */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Pos (0UL) /*!< TCNTCTL (Bit 0) */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Msk (0x1UL) /*!< TCNTCTL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Pos (1UL) /*!< TEVPOL (Bit 1) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Msk (0x2UL) /*!< TEVPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TOPOL_Pos (2UL) /*!< TOPOL (Bit 2) */ + #define R_ULPT0_ULPTMR3_TOPOL_Msk (0x4UL) /*!< TOPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEECTL_Pos (4UL) /*!< TEECTL (Bit 4) */ + #define R_ULPT0_ULPTMR3_TEECTL_Msk (0x30UL) /*!< TEECTL (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Pos (6UL) /*!< TEEPOL (Bit 6) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Msk (0xc0UL) /*!< TEEPOL (Bitfield-Mask: 0x03) */ +/* ======================================================== ULPTIOC ======================================================== */ + #define R_ULPT0_ULPTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_ULPT0_ULPTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_ULPT0_ULPTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Pos (6UL) /*!< TIOGT0 (Bit 6) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Msk (0x40UL) /*!< TIOGT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTISR ======================================================== */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Pos (2UL) /*!< RCCPSEL2 (Bit 2) */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Msk (0x4UL) /*!< RCCPSEL2 (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPTCMSR ======================================================== */ + #define R_ULPT0_ULPTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_ULPT0_ULPTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_ULPT0_ULPTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_ULPT0_ULPTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= FSBLSTATM ======================================================= */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CONVAREAST ======================================================= */ + #define R_DOTF_CONVAREAST_CONVAREAST_Pos (12UL) /*!< CONVAREAST (Bit 12) */ + #define R_DOTF_CONVAREAST_CONVAREAST_Msk (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff) */ +/* ======================================================= CONVAREAD ======================================================= */ + #define R_DOTF_CONVAREAD_CONVAREAD_Pos (12UL) /*!< CONVAREAD (Bit 12) */ + #define R_DOTF_CONVAREAD_CONVAREAD_Msk (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= REG00 ========================================================= */ + #define R_DOTF_REG00_B09_Pos (9UL) /*!< B09 (Bit 9) */ + #define R_DOTF_REG00_B09_Msk (0x200UL) /*!< B09 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B16_Pos (16UL) /*!< B16 (Bit 16) */ + #define R_DOTF_REG00_B16_Msk (0x10000UL) /*!< B16 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B17_Pos (17UL) /*!< B17 (Bit 17) */ + #define R_DOTF_REG00_B17_Msk (0x20000UL) /*!< B17 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B20_Pos (20UL) /*!< B20 (Bit 20) */ + #define R_DOTF_REG00_B20_Msk (0x100000UL) /*!< B20 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B24_Pos (24UL) /*!< B24 (Bit 24) */ + #define R_DOTF_REG00_B24_Msk (0x3000000UL) /*!< B24 (Bitfield-Mask: 0x03) */ + #define R_DOTF_REG00_B28_Pos (28UL) /*!< B28 (Bit 28) */ + #define R_DOTF_REG00_B28_Msk (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03) */ +/* ========================================================= REG03 ========================================================= */ + #define R_DOTF_REG03_B00_Pos (0UL) /*!< B00 (Bit 0) */ + #define R_DOTF_REG03_B00_Msk (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCKMHZ ========================================================= */ + #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ + #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ + #define R_MIPI_DSI_ISR_SQ0_Pos (0UL) /*!< SQ0 (Bit 0) */ + #define R_MIPI_DSI_ISR_SQ0_Msk (0x1UL) /*!< SQ0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_SQ1_Pos (4UL) /*!< SQ1 (Bit 4) */ + #define R_MIPI_DSI_ISR_SQ1_Msk (0x10UL) /*!< SQ1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_VM_Pos (8UL) /*!< VM (Bit 8) */ + #define R_MIPI_DSI_ISR_VM_Msk (0x100UL) /*!< VM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_RCV_Pos (12UL) /*!< RCV (Bit 12) */ + #define R_MIPI_DSI_ISR_RCV_Msk (0x1000UL) /*!< RCV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_FERR_Pos (16UL) /*!< FERR (Bit 16) */ + #define R_MIPI_DSI_ISR_FERR_Msk (0x10000UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_PPI_Pos (20UL) /*!< PPI (Bit 20) */ + #define R_MIPI_DSI_ISR_PPI_Msk (0x100000UL) /*!< PPI (Bitfield-Mask: 0x01) */ +/* ======================================================== LINKSR ========================================================= */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Pos (0UL) /*!< SQ0RUN (Bit 0) */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Msk (0x1UL) /*!< SQ0RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Pos (4UL) /*!< SQ1RUN (Bit 4) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Msk (0x10UL) /*!< SQ1RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_VRUN_Pos (8UL) /*!< VRUN (Bit 8) */ + #define R_MIPI_DSI_LINKSR_VRUN_Msk (0x100UL) /*!< VRUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Pos (12UL) /*!< HSBUSY (Bit 12) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Msk (0x1000UL) /*!< HSBUSY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Pos (13UL) /*!< LPBUSY (Bit 13) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Msk (0x2000UL) /*!< LPBUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== TXSETR ========================================================= */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Pos (0UL) /*!< NUMLANE (Bit 0) */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Msk (0x3UL) /*!< NUMLANE (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_TXSETR_CLEN_Pos (8UL) /*!< CLEN (Bit 8) */ + #define R_MIPI_DSI_TXSETR_CLEN_Msk (0x100UL) /*!< CLEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_TXSETR_DLEN_Pos (9UL) /*!< DLEN (Bit 9) */ + #define R_MIPI_DSI_TXSETR_DLEN_Msk (0x200UL) /*!< DLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= HSCLKSETR ======================================================= */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Pos (0UL) /*!< HSCLST (Bit 0) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Msk (0x1UL) /*!< HSCLST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Pos (1UL) /*!< HSCLMD (Bit 1) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Msk (0x2UL) /*!< HSCLMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPSSETR ======================================================== */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Pos (0UL) /*!< WKUP (Bit 0) */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Msk (0xffUL) /*!< WKUP (Bitfield-Mask: 0xff) */ +/* ======================================================== ULPSCR ========================================================= */ + #define R_MIPI_DSI_ULPSCR_CLENT_Pos (24UL) /*!< CLENT (Bit 24) */ + #define R_MIPI_DSI_ULPSCR_CLENT_Msk (0x1000000UL) /*!< CLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Pos (25UL) /*!< CLEXIT (Bit 25) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Msk (0x2000000UL) /*!< CLEXIT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Pos (28UL) /*!< DLENT (Bit 28) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Msk (0x10000000UL) /*!< DLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Pos (29UL) /*!< DLEXIT (Bit 29) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Msk (0x20000000UL) /*!< DLEXIT (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTCR ========================================================= */ + #define R_MIPI_DSI_RSTCR_SWRST_Pos (0UL) /*!< SWRST (Bit 0) */ + #define R_MIPI_DSI_RSTCR_SWRST_Msk (0x1UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Pos (16UL) /*!< FTXSTP (Bit 16) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Msk (0x10000UL) /*!< FTXSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTSR ========================================================= */ + #define R_MIPI_DSI_RSTSR_RSTHS_Pos (0UL) /*!< RSTHS (Bit 0) */ + #define R_MIPI_DSI_RSTSR_RSTHS_Msk (0x1UL) /*!< RSTHS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Pos (1UL) /*!< RSTLP (Bit 1) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Msk (0x2UL) /*!< RSTLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Pos (2UL) /*!< RSTAPB (Bit 2) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Msk (0x4UL) /*!< RSTAPB (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Pos (3UL) /*!< RSTAXI (Bit 3) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Msk (0x8UL) /*!< RSTAXI (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTV_Pos (4UL) /*!< RSTV (Bit 4) */ + #define R_MIPI_DSI_RSTSR_RSTV_Msk (0x10UL) /*!< RSTV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DSISETR ======================================================== */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Pos (0UL) /*!< MRPSZ (Bit 0) */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Msk (0xffffUL) /*!< MRPSZ (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Pos (16UL) /*!< ECCEN (Bit 16) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Msk (0x10000UL) /*!< ECCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Pos (20UL) /*!< VC0CRCEN (Bit 20) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Msk (0x100000UL) /*!< VC0CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Pos (21UL) /*!< VC1CRCEN (Bit 21) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Msk (0x200000UL) /*!< VC1CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Pos (22UL) /*!< VC2CRCEN (Bit 22) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Msk (0x400000UL) /*!< VC2CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Pos (23UL) /*!< VC3CRCEN (Bit 23) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Msk (0x800000UL) /*!< VC3CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_SCREN_Pos (29UL) /*!< SCREN (Bit 29) */ + #define R_MIPI_DSI_DSISETR_SCREN_Msk (0x20000000UL) /*!< SCREN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Pos (30UL) /*!< EXTEMD (Bit 30) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Msk (0x40000000UL) /*!< EXTEMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Pos (31UL) /*!< EOTPEN (Bit 31) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Msk (0x80000000UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TXPPD0R ======================================================== */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD1R ======================================================== */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD2R ======================================================== */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD3R ======================================================== */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ========================================================= RXSR ========================================================== */ + #define R_MIPI_DSI_RXSR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSCR ========================================================= */ + #define R_MIPI_DSI_RXSCR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSCR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSCR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSCR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSCR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSCR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIER ========================================================= */ + #define R_MIPI_DSI_RXIER_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXIER_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXIER_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXIER_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXIER_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXIER_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXIER_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXIER_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXIER_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXIER_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXIER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ==================================================== PRESPTOBTASETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Pos (0UL) /*!< PRTBTA (Bit 0) */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Msk (0xffffffffUL) /*!< PRTBTA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PRESPTOLPSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Pos (0UL) /*!< LPWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Msk (0xffffUL) /*!< LPWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Pos (16UL) /*!< LPRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Msk (0xffff0000UL) /*!< LPRTO (Bitfield-Mask: 0xffff) */ +/* ===================================================== PRESPTOHSSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Pos (0UL) /*!< HSWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Msk (0xffffUL) /*!< HSWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Pos (16UL) /*!< HSRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Msk (0xffff0000UL) /*!< HSRTO (Bitfield-Mask: 0xffff) */ +/* ======================================================= AKEPLATIR ======================================================= */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Pos (0UL) /*!< EREP (Bit 0) */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Msk (0xffffUL) /*!< EREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Pos (16UL) /*!< VC (Bit 16) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Msk (0xf0000UL) /*!< VC (Bitfield-Mask: 0x0f) */ +/* ======================================================= AKEPACMSR ======================================================= */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== AKEPSCR ======================================================== */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== RXRSSR ========================================================= */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSSCR ======================================================== */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRINFOOWSR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ===================================================== RXRINFOOWSCR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS0R ======================================================== */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS0R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS0R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS1R ======================================================== */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS1R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS1R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS2R ======================================================== */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS2R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS2R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS3R ======================================================== */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS3R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS3R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS0R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS1R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS2R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS3R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS0R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS1R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS2R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS3R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS0R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS1R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS2R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS3R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS0R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS1R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS2R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS3R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXPPD0R ======================================================== */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD1R ======================================================== */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD2R ======================================================== */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD3R ======================================================== */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ====================================================== HSTXTOSETR ======================================================= */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Msk (0xffffffffUL) /*!< HTXTO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== LRXHTOSETR ======================================================= */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Pos (0UL) /*!< LRXHTO (Bit 0) */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Msk (0xffffffffUL) /*!< LRXHTO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TATOSETR ======================================================== */ + #define R_MIPI_DSI_TATOSETR_TATO_Pos (0UL) /*!< TATO (Bit 0) */ + #define R_MIPI_DSI_TATOSETR_TATO_Msk (0xffffffffUL) /*!< TATO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FERRSR ========================================================= */ + #define R_MIPI_DSI_FERRSR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Pos (27UL) /*!< CLP0S (Bit 27) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Msk (0x8000000UL) /*!< CLP0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Pos (28UL) /*!< CLP1S (Bit 28) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Msk (0x10000000UL) /*!< CLP1S (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRSCR ======================================================== */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRIER ======================================================== */ + #define R_MIPI_DSI_FERRIER_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRIER_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRIER_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRIER_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRIER_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CLSTPTSETR ======================================================= */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Pos (2UL) /*!< CLKSTPT (Bit 2) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Msk (0xffcUL) /*!< CLKSTPT (Bitfield-Mask: 0x3ff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Pos (16UL) /*!< CLKBFHT (Bit 16) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Msk (0xff0000UL) /*!< CLKBFHT (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Pos (24UL) /*!< CLKKPT (Bit 24) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Msk (0xff000000UL) /*!< CLKKPT (Bitfield-Mask: 0xff) */ +/* ====================================================== LPTRNSTSETR ====================================================== */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Pos (0UL) /*!< GOLPBKT (Bit 0) */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Msk (0x3ffUL) /*!< GOLPBKT (Bitfield-Mask: 0x3ff) */ +/* ========================================================= PLSR ========================================================== */ + #define R_MIPI_DSI_PLSR_CLUAN_Pos (0UL) /*!< CLUAN (Bit 0) */ + #define R_MIPI_DSI_PLSR_CLUAN_Msk (0x1UL) /*!< CLUAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLSTP_Pos (1UL) /*!< CLSTP (Bit 1) */ + #define R_MIPI_DSI_PLSR_CLSTP_Msk (0x2UL) /*!< CLSTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Pos (2UL) /*!< DL0RLE (Bit 2) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Msk (0x4UL) /*!< DL0RLE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Pos (3UL) /*!< DL0RUE (Bit 3) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Msk (0x8UL) /*!< DL0RUE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Pos (4UL) /*!< DL0UAN (Bit 4) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Msk (0x10UL) /*!< DL0UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Pos (5UL) /*!< DL1UAN (Bit 5) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Msk (0x20UL) /*!< DL1UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_PLSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_PLSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLSCR ========================================================= */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLIER ========================================================= */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET0R ======================================================== */ + #define R_MIPI_DSI_VMSET0R_VSTART_Pos (0UL) /*!< VSTART (Bit 0) */ + #define R_MIPI_DSI_VMSET0R_VSTART_Msk (0x1UL) /*!< VSTART (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Pos (1UL) /*!< VSTOP (Bit 1) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Msk (0x2UL) /*!< VSTOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Pos (8UL) /*!< HSANOLP (Bit 8) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Msk (0x100UL) /*!< HSANOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Pos (9UL) /*!< HBPNOLP (Bit 9) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Msk (0x200UL) /*!< HBPNOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Pos (10UL) /*!< HFPNOLP (Bit 10) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Msk (0x400UL) /*!< HFPNOLP (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET1R ======================================================== */ + #define R_MIPI_DSI_VMSET1R_DLY_Pos (2UL) /*!< DLY (Bit 2) */ + #define R_MIPI_DSI_VMSET1R_DLY_Msk (0x3ffcUL) /*!< DLY (Bitfield-Mask: 0xfff) */ +/* ========================================================= VMSR ========================================================== */ + #define R_MIPI_DSI_VMSR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_VMSR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMSCR ========================================================= */ + #define R_MIPI_DSI_VMSCR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSCR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSCR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMIER ========================================================= */ + #define R_MIPI_DSI_VMIER_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMIER_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMIER_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMIER_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMIER_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= VMPPSETR ======================================================== */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Pos (15UL) /*!< TXESYNC (Bit 15) */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Msk (0x8000UL) /*!< TXESYNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMPPSETR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_VMPPSETR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_VMPPSETR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_VMPPSETR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ======================================================= VMVSSETR ======================================================== */ + #define R_MIPI_DSI_VMVSSETR_VSA_Pos (0UL) /*!< VSA (Bit 0) */ + #define R_MIPI_DSI_VMVSSETR_VSA_Msk (0xfffUL) /*!< VSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Pos (15UL) /*!< VSPOL (Bit 15) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Msk (0x8000UL) /*!< VSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Pos (16UL) /*!< VACT (Bit 16) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Msk (0x7fff0000UL) /*!< VACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMVPSETR ======================================================== */ + #define R_MIPI_DSI_VMVPSETR_VBP_Pos (0UL) /*!< VBP (Bit 0) */ + #define R_MIPI_DSI_VMVPSETR_VBP_Msk (0x1fffUL) /*!< VBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Pos (16UL) /*!< VFP (Bit 16) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Msk (0x1fff0000UL) /*!< VFP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= VMHSSETR ======================================================== */ + #define R_MIPI_DSI_VMHSSETR_HSA_Pos (0UL) /*!< HSA (Bit 0) */ + #define R_MIPI_DSI_VMHSSETR_HSA_Msk (0xfffUL) /*!< HSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Pos (15UL) /*!< HSPOL (Bit 15) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Msk (0x8000UL) /*!< HSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Pos (16UL) /*!< HACT (Bit 16) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Msk (0x7fff0000UL) /*!< HACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMHPSETR ======================================================== */ + #define R_MIPI_DSI_VMHPSETR_HBP_Pos (0UL) /*!< HBP (Bit 0) */ + #define R_MIPI_DSI_VMHPSETR_HBP_Msk (0x1fffUL) /*!< HBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Pos (16UL) /*!< HFP (Bit 16) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Msk (0x1fff0000UL) /*!< HFP (Bitfield-Mask: 0x1fff) */ +/* ====================================================== SQCH0SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH0SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH0SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH0SR ======================================================== */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0SCR ======================================================== */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0IER ======================================================== */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH1SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH1SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH1SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH1SR ======================================================== */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1SCR ======================================================== */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1IER ======================================================== */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH0DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH0DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH1DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH1DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_OFS_DATAFLASH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= FSBLCTRL0 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos (0UL) /*!< FSBLEN (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Msk (0x7UL) /*!< FSBLEN (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos (3UL) /*!< FSBLSKIPSW (Bit 3) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Msk (0x38UL) /*!< FSBLSKIPSW (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos (6UL) /*!< FSBLSKIPDS (Bit 6) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Msk (0x1c0UL) /*!< FSBLSKIPDS (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos (9UL) /*!< FSBLCLK (Bit 9) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Msk (0xe00UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ +/* ======================================================= FSBLCTRL1 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos (0UL) /*!< FSBLEXMD (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Msk (0x3UL) /*!< FSBLEXMD (Bitfield-Mask: 0x03) */ +/* ======================================================= FSBLCTRL2 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos (0UL) /*!< PORTPN (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Msk (0xfUL) /*!< PORTPN (Bitfield-Mask: 0x0f) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos (4UL) /*!< PORTGN (Bit 4) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Msk (0x1f0UL) /*!< PORTGN (Bitfield-Mask: 0x1f) */ +/* ========================================================= SACC0 ========================================================= */ +/* ========================================================= SACC1 ========================================================= */ +/* ========================================================= SAMR ========================================================== */ +/* ======================================================= HOEMRTPK ======================================================== */ +/* ========================================================= ARCLS ========================================================= */ + #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Pos (0UL) /*!< ARCS_LK (Bit 0) */ + #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Msk (0x1UL) /*!< ARCS_LK (Bitfield-Mask: 0x01) */ + #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Pos (1UL) /*!< ARCNS_LK (Bit 1) */ + #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Msk (0x1eUL) /*!< ARCNS_LK (Bitfield-Mask: 0x0f) */ + #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Pos (5UL) /*!< ARCBL_LK (Bit 5) */ + #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Msk (0x20UL) /*!< ARCBL_LK (Bitfield-Mask: 0x01) */ +/* ========================================================= ARCCS ========================================================= */ + #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Pos (0UL) /*!< CNF_ARCNS (Bit 0) */ + #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Msk (0x3UL) /*!< CNF_ARCNS (Bitfield-Mask: 0x03) */ +/* ======================================================== ARC_SEC ======================================================== */ + #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Pos (0UL) /*!< ARC_SEC (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Msk (0xffffffffUL) /*!< ARC_SEC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ARC_NSEC ======================================================== */ + #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Pos (0UL) /*!< ARC_NSEC (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Msk (0xffffffffUL) /*!< ARC_NSEC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ARC_OEMBL ======================================================= */ + #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Pos (0UL) /*!< ARC_OEMBL (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Msk (0xffffffffUL) /*!< ARC_OEMBL (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA8D1BH_H */ + +/** @} */ /* End of group R7FA8D1BH */ + +/** @} */ /* End of group Renesas */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8E1AF.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8E1AF.h new file mode 100644 index 0000000000..e40b15304e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8E1AF.h @@ -0,0 +1,28982 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7FA8E1AF.h + * @brief CMSIS HeaderFile + * @version 1.2 + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA8E1AF + * @{ + */ + +#ifndef R7FA8E1AF_H + #define R7FA8E1AF_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M85 Processor and Core Peripherals =========================== */ + #define __CM85_REV 0x0000U /*!< CM85 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */ + #define __DCACHE_PRESENT 1 /*!< Data Cache present */ + #define __SAUREGION_PRESENT 1 /*!< SAU region present */ + #define __PMU_PRESENT 1 /*!< PMU present */ + #define __PMU_NUM_EVENTCNT 8 /*!< PMU Event Counters */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm85.h" /*!< ARM Cortex-M85 processor and core peripherals */ + #include "system.h" /*!< R7FA8E1AF System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint32_t : 31; + } IRQEN_b; + }; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + }; + __IM uint32_t RESERVED3; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + }; + __IM uint32_t RESERVED8; + + union + { + union + { + __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } EOBI_b; + }; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED10; + + union + { + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..30]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint32_t : 1; + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint16_t : 1; + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint8_t : 1; + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_XSPI0_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration register 0 */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode */ + __IOM uint32_t ARYAMD : 1; /*!< [5..5] Array address mode */ + uint32_t : 10; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration register 1 */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration register 2 */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CMCFGCS_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CDBUF [CDBUF] (xSPI BUF register) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2byte) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_CDBUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CCCTLCS [CCCTLCS] (xSPI CS register) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control register 0 */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control register 1 */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control register 2 */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3 */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control register 4 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control register 5 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control register 6 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CCCTLCS_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_OFS_DATAFLASH_CFGDLOCK_CFGD [CFGD] (Configuration Data [0..1] Lock Bits) + */ +typedef struct +{ + union + { + __IM uint32_t CFGD_L; /*!< (@ 0x00000000) Configuration Data Lock Bits Lower Word */ + + struct + { + __IM uint32_t CDLK0 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint32_t CDLK1 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint32_t CDLK2 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint32_t CDLK3 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint32_t CDLK4 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint32_t CDLK5 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint32_t CDLK6 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint32_t CDLK7 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint32_t CDLK8 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint32_t CDLK9 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint32_t CDLK10 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint32_t CDLK11 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint32_t CDLK12 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint32_t CDLK13 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint32_t CDLK14 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint32_t CDLK15 : 1; /*!< [15..15] Configuration Data Lock Bit */ + __IM uint32_t CDLK16 : 1; /*!< [16..16] Configuration Data Lock Bit */ + __IM uint32_t CDLK17 : 1; /*!< [17..17] Configuration Data Lock Bit */ + __IM uint32_t CDLK18 : 1; /*!< [18..18] Configuration Data Lock Bit */ + __IM uint32_t CDLK19 : 1; /*!< [19..19] Configuration Data Lock Bit */ + __IM uint32_t CDLK20 : 1; /*!< [20..20] Configuration Data Lock Bit */ + __IM uint32_t CDLK21 : 1; /*!< [21..21] Configuration Data Lock Bit */ + __IM uint32_t CDLK22 : 1; /*!< [22..22] Configuration Data Lock Bit */ + __IM uint32_t CDLK23 : 1; /*!< [23..23] Configuration Data Lock Bit */ + __IM uint32_t CDLK24 : 1; /*!< [24..24] Configuration Data Lock Bit */ + __IM uint32_t CDLK25 : 1; /*!< [25..25] Configuration Data Lock Bit */ + __IM uint32_t CDLK26 : 1; /*!< [26..26] Configuration Data Lock Bit */ + __IM uint32_t CDLK27 : 1; /*!< [27..27] Configuration Data Lock Bit */ + __IM uint32_t CDLK28 : 1; /*!< [28..28] Configuration Data Lock Bit */ + __IM uint32_t CDLK29 : 1; /*!< [29..29] Configuration Data Lock Bit */ + __IM uint32_t CDLK30 : 1; /*!< [30..30] Configuration Data Lock Bit */ + __IM uint32_t CDLK31 : 1; /*!< [31..31] Configuration Data Lock Bit */ + } CFGD_L_b; + }; + + union + { + __IM uint32_t CFGD_H; /*!< (@ 0x00000004) Configuration Data Lock Bits Higher Word */ + + struct + { + __IM uint32_t CDLK32 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint32_t CDLK33 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint32_t CDLK34 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint32_t CDLK35 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint32_t CDLK36 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint32_t CDLK37 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint32_t CDLK38 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint32_t CDLK39 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint32_t CDLK40 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint32_t CDLK41 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint32_t CDLK42 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint32_t CDLK43 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint32_t CDLK44 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint32_t CDLK45 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint32_t CDLK46 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint32_t CDLK47 : 1; /*!< [15..15] Configuration Data Lock Bit */ + __IM uint32_t CDLK48 : 1; /*!< [16..16] Configuration Data Lock Bit */ + __IM uint32_t CDLK49 : 1; /*!< [17..17] Configuration Data Lock Bit */ + __IM uint32_t CDLK50 : 1; /*!< [18..18] Configuration Data Lock Bit */ + __IM uint32_t CDLK51 : 1; /*!< [19..19] Configuration Data Lock Bit */ + __IM uint32_t CDLK52 : 1; /*!< [20..20] Configuration Data Lock Bit */ + __IM uint32_t CDLK53 : 1; /*!< [21..21] Configuration Data Lock Bit */ + __IM uint32_t CDLK54 : 1; /*!< [22..22] Configuration Data Lock Bit */ + __IM uint32_t CDLK55 : 1; /*!< [23..23] Configuration Data Lock Bit */ + __IM uint32_t CDLK56 : 1; /*!< [24..24] Configuration Data Lock Bit */ + __IM uint32_t CDLK57 : 1; /*!< [25..25] Configuration Data Lock Bit */ + __IM uint32_t CDLK58 : 1; /*!< [26..26] Configuration Data Lock Bit */ + __IM uint32_t CDLK59 : 1; /*!< [27..27] Configuration Data Lock Bit */ + __IM uint32_t CDLK60 : 1; /*!< [28..28] Configuration Data Lock Bit */ + __IM uint32_t CDLK61 : 1; /*!< [29..29] Configuration Data Lock Bit */ + __IM uint32_t CDLK62 : 1; /*!< [30..30] Configuration Data Lock Bit */ + __IM uint32_t CDLK63 : 1; /*!< [31..31] Configuration Data Lock Bit */ + } CFGD_H_b; + }; +} R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_OFS_DATAFLASH_CFGDLOCK [CFGDLOCK] (Configuration Data Lock Bits) + */ +typedef struct +{ + __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD0; /*!< (@ 0x00000000) Configuration Data 0 Lock Bits */ + __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD1; /*!< (@ 0x00000008) Configuration Data 1 Lock Bits */ + + union + { + __IM uint16_t CFGD2; /*!< (@ 0x00000010) Configuration Data 2 Lock Bit */ + + struct + { + __IM uint16_t CDLK0 : 1; /*!< [0..0] Configuration Data Lock Bit */ + __IM uint16_t CDLK1 : 1; /*!< [1..1] Configuration Data Lock Bit */ + __IM uint16_t CDLK2 : 1; /*!< [2..2] Configuration Data Lock Bit */ + __IM uint16_t CDLK3 : 1; /*!< [3..3] Configuration Data Lock Bit */ + __IM uint16_t CDLK4 : 1; /*!< [4..4] Configuration Data Lock Bit */ + __IM uint16_t CDLK5 : 1; /*!< [5..5] Configuration Data Lock Bit */ + __IM uint16_t CDLK6 : 1; /*!< [6..6] Configuration Data Lock Bit */ + __IM uint16_t CDLK7 : 1; /*!< [7..7] Configuration Data Lock Bit */ + __IM uint16_t CDLK8 : 1; /*!< [8..8] Configuration Data Lock Bit */ + __IM uint16_t CDLK9 : 1; /*!< [9..9] Configuration Data Lock Bit */ + __IM uint16_t CDLK10 : 1; /*!< [10..10] Configuration Data Lock Bit */ + __IM uint16_t CDLK11 : 1; /*!< [11..11] Configuration Data Lock Bit */ + __IM uint16_t CDLK12 : 1; /*!< [12..12] Configuration Data Lock Bit */ + __IM uint16_t CDLK13 : 1; /*!< [13..13] Configuration Data Lock Bit */ + __IM uint16_t CDLK14 : 1; /*!< [14..14] Configuration Data Lock Bit */ + __IM uint16_t CDLK15 : 1; /*!< [15..15] Configuration Data Lock Bit */ + } CFGD2_b; + }; + __IM uint16_t RESERVED; +} R_OFS_DATAFLASH_CFGDLOCK_Type; /*!< Size = 20 (0x14) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40332000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (left-justified). The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[29]; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED11; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED12; + __IM uint16_t RESERVED13; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED15; + __IM uint32_t RESERVED16[2]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x40204000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ + } MSSAR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARB_b; + }; + + union + { + __IOM uint32_t PPARC; /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C */ + + struct + { + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARC_b; + }; + + union + { + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARD_b; + }; + + union + { + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARE_b; + }; + + union + { + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } MSPAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000034) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 60 (0x3c) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[33]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ + __IM uint32_t RESERVED13[5]; + __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40202400) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40310000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40333000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 6; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 12; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[123]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x4000A800) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x4000A000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x4000AC00) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40201000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */ + __IM uint32_t RESERVED2[6]; + __IOM R_ELC_ELSR_Type ELSR[31]; /*!< (@ 0x00000020) Event Link Setting Register [0..30] */ + __IM uint32_t RESERVED3[17]; + + union + { + __IOM uint32_t ELCSARA; /*!< (@ 0x000000E0) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint32_t : 29; + } ELCSARA_b; + }; + + union + { + __IOM uint32_t ELCSARB; /*!< (@ 0x000000E4) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + uint32_t : 12; + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + uint32_t : 1; + } ELCSARB_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t ELCPARA; /*!< (@ 0x000000F0) Event Link Controller Privilege Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller Register Privilege Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Privilege + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Privilege + * Attribution */ + uint32_t : 29; + } ELCPARA_b; + }; + + union + { + __IOM uint32_t ELCPARB; /*!< (@ 0x000000F4) Event Link Controller Privilege Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + uint32_t : 12; + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + uint32_t : 1; + } ELCPARB_b; + }; +} R_ELC_Type; /*!< Size = 248 (0xf8) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40354100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x40100000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x4011E000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + uint8_t : 3; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint8_t FCNTSELR; /*!< (@ 0x00000048) Flash Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } FCNTSELR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IM uint32_t FCNTDATAR0; /*!< (@ 0x0000004C) Flash Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR0_b; + }; + + union + { + __IM uint32_t FCNTDATAR1; /*!< (@ 0x00000050) Flash Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } FCNTDATAR1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[11]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IOM uint32_t FBCADDR; /*!< (@ 0x000000D8) Flash Blank Check Address Register */ + + struct + { + __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address + * or the last blank checked address which is found in 'Blank + * Check' command execution. */ + uint32_t : 8; + } FBCADDR_b; + }; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C100) R_FCACHE Structure */ +{ + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000000) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] Flash Cache Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000004) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED1[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000001C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000040) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + __IOM uint16_t FCACHEENSA : 1; /*!< [1..1] FCHACHEEN Security Attribution */ + uint16_t : 6; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI command Issuing Security Attribution */ + __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI command Registers Security Attribution */ + __IOM uint16_t FACITRSA : 1; /*!< [11..11] FACI transfer Security Attribution */ + uint16_t : 4; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 66 (0x42) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40322000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + + union + { + __IM uint8_t NMICR; /*!< (@ 0x00000010) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[6143]; + + union + { + __IOM uint8_t SWIRQ_S; /*!< (@ 0x00006010) Software Interrupt Request Register for Secure + * Interrupt */ + + struct + { + __IOM uint8_t SWIRQS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem. */ + uint8_t : 7; + } SWIRQ_S_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint8_t SWIRQ_NS; /*!< (@ 0x00006020) Software Interrupt Request Register for Non-secure + * Interrupt */ + + struct + { + __IOM uint8_t SWIRQNS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem. */ + uint8_t : 7; + } SWIRQ_NS_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + __IM uint32_t RESERVED8[15]; + + union + { + __IOM uint16_t IENMIER; /*!< (@ 0x00006060) Integrated Error NMI Interrupt Enable Registe + * for CPU */ + + struct + { + __IOM uint16_t CMEN : 1; /*!< [0..0] Integrated Common Memory error nmi Enable */ + __IOM uint16_t LMEN : 1; /*!< [1..1] Integrated Local Memory error nmi Enable */ + __IOM uint16_t BUSEN : 1; /*!< [2..2] Integrated BUS error nmi Enable */ + uint16_t : 13; + } IENMIER_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[39]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + uint16_t : 2; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t BUSEN : 1; /*!< [12..12] BUS error Interrupt Enable */ + __IOM uint16_t CMEN : 1; /*!< [13..13] Common Memory error Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LUEN : 1; /*!< [15..15] LockUp Interrupt Enable */ + } NMIER_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __IOM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __IOM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __IOM uint16_t LVD1CLR : 1; /*!< [2..2] PVD1 Clear */ + __IOM uint16_t LVD2CLR : 1; /*!< [3..3] PVD2 Clear */ + uint16_t : 2; + __IOM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __IOM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + uint16_t : 4; + __IOM uint16_t BUSCLR : 1; /*!< [12..12] Bus Clear */ + __IOM uint16_t CMCLR : 1; /*!< [13..13] CM Clear */ + uint16_t : 1; + __IOM uint16_t LUCLR : 1; /*!< [15..15] LU Clear */ + } NMICLR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + uint16_t : 2; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + uint16_t : 4; + __IM uint16_t BUSST : 1; /*!< [12..12] BUS error Interrupt Status Flag */ + __IM uint16_t CMST : 1; /*!< [13..13] Common Memory error Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t LUST : 1; /*!< [15..15] LockUp Interrupt Status Flag */ + } NMISR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[31]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + uint32_t : 1; + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] PVD1 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] PVD2 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT Monitor Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + uint32_t : 3; + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC Alarm Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT Period Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS0 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 Compare Match A Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t RIIC0WUPEN : 1; /*!< [31..31] RIIC0 Address Match Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1 */ + + struct + { + uint32_t : 3; + __IOM uint32_t COMPHS0WUPEN : 1; /*!< [3..3] Comparator-HS0 Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + uint32_t : 4; + __IOM uint32_t ULP0UWUPEN : 1; /*!< [8..8] ULPT0 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP0AWUPEN : 1; /*!< [9..9] ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP0BWUPEN : 1; /*!< [10..10] ULPT0 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t I3CWUPEN : 1; /*!< [11..11] I3C Wakeup Condition Detection Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t ULP1UWUPEN : 1; /*!< [12..12] ULPT1 Underflow Interrupt Deep Sleep/Software Standby + * Returns Enable bit */ + __IOM uint32_t ULP1AWUPEN : 1; /*!< [13..13] ULPT1 Compare Match A Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + __IOM uint32_t ULP1BWUPEN : 1; /*!< [14..14] ULPT1 Compare Match B Interrupt Deep Sleep/Software + * Standby Returns Enable bit */ + uint32_t : 17; + } WUPEN1_b; + }; + __IM uint32_t RESERVED17[86]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 25728 (0x6480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4025E000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40202200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3840 (0xf00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40203000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40400000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000002) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + + union + { + __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40400800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40400D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[3]; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[13]; + __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40202000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint16_t SRAMPRCR; /*!< (@ 0x00000000) SRAM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t SRAMPRCR_NS; /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) SRAM Wait State Control Register */ + + struct + { + __IOM uint8_t WTEN : 1; /*!< [0..0] Wait enable */ + uint8_t : 7; + } SRAMWTSC_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4; + + union + { + __IOM uint8_t SRAMCR0; /*!< (@ 0x00000010) SRAM Control Register 0 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection for 1-bit ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR0_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRAMCR1; /*!< (@ 0x00000014) SRAM Control Register 1 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection for parity error detection */ + uint8_t : 7; + } SRAMCR1_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SRAMECCRGN0; /*!< (@ 0x00000030) SRAM0 ECC Region Control Register */ + + struct + { + __IOM uint8_t ECCRGN : 2; /*!< [1..0] ECC Region */ + uint8_t : 6; + } SRAMECCRGN0_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[3]; + + union + { + __IM uint16_t SRAMESR; /*!< (@ 0x00000040) SRAM Error Status Register */ + + struct + { + __IM uint16_t ERR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status */ + __IM uint16_t ERR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status */ + __IM uint16_t ERR1 : 1; /*!< [2..2] SRAM1 Parity Error Status */ + uint16_t : 11; + __IM uint16_t ERRS : 1; /*!< [14..14] Standby SRAM Parity Error status */ + uint16_t : 1; + } SRAMESR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t SRAMESCLR; /*!< (@ 0x00000048) SRAM Error Status Clear Register */ + + struct + { + __IOM uint16_t CLR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status Clear */ + __IOM uint16_t CLR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status Clear */ + __IOM uint16_t CLR1 : 1; /*!< [2..2] SRAM1 Parity Error Status Clear */ + uint16_t : 11; + __IOM uint16_t CLRS : 1; /*!< [14..14] Standby SRAM Parity Error Status Clear */ + uint16_t : 1; + } SRAMESCLR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16; + + union + { + __IM uint32_t SRAMEAR0; /*!< (@ 0x00000050) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR0_b; + }; + + union + { + __IM uint32_t SRAMEAR1; /*!< (@ 0x00000054) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR1_b; + }; + + union + { + __IM uint32_t SRAMEAR2; /*!< (@ 0x00000058) SRAM Error Address Register */ + + struct + { + uint32_t : 3; + __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */ + uint32_t : 12; + } SRAMEAR2_b; + }; + __IM uint32_t RESERVED17[45]; + + union + { + __IOM uint8_t STBRAMCR; /*!< (@ 0x00000110) Standby SRAM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection */ + uint8_t : 7; + } STBRAMCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[15]; + + union + { + __IM uint32_t STBRAMEAR; /*!< (@ 0x00000150) Standby SRAM Error Address Register */ + + struct + { + uint32_t : 2; + __IM uint32_t EA : 8; /*!< [9..2] SRAM Error Address */ + uint32_t : 22; + } STBRAMEAR_b; + }; +} R_SRAM_Type; /*!< Size = 340 (0x154) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4025D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint8_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t OPE : 1; /*!< [6..6] Output Port Enable */ + uint8_t : 1; + } SBYCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t SSCR2; /*!< (@ 0x0000000E) Software Standby Control Register 2 */ + + struct + { + __IM uint8_t SS1RSF : 1; /*!< [0..0] Software Standby 1 regulator status flag */ + uint8_t : 7; + } SSCR2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t FLSCR; /*!< (@ 0x00000010) Flash Standby Control Register */ + + struct + { + __IOM uint8_t FLSWCF : 1; /*!< [0..0] Flash Stabilization wait completion flag */ + uint8_t : 7; + } FLSCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 4; /*!< [3..0] Peripheral Module Clock D (PCLKD) Select */ + __IOM uint32_t PCKC : 4; /*!< [7..4] Peripheral Module Clock C (PCLKC) Select */ + __IOM uint32_t PCKB : 4; /*!< [11..8] Peripheral Module Clock B (PCLKB) Select */ + __IOM uint32_t PCKA : 4; /*!< [15..12] Peripheral Module Clock A (PCLKA) Select */ + __IOM uint32_t BCK : 4; /*!< [19..16] External Bus Clock (BCLK) Select */ + __IOM uint32_t PCKE : 4; /*!< [23..20] Peripheral Module Clock E (PCLKE) Select */ + __IOM uint32_t ICK : 4; /*!< [27..24] System Clock (ICLK) Select */ + __IOM uint32_t FCK : 4; /*!< [31..28] Flash IF Clock (FCLK) Select */ + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + __IOM uint8_t CPUCK : 4; /*!< [3..0] CPU Clock (CPUCLK) Select */ + uint8_t : 4; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select */ + uint16_t : 1; + __IOM uint16_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select */ + __IOM uint16_t PLLMUL : 8; /*!< [15..8] PLL1 Frequency Multiplication Factor Select */ + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + __IM uint8_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED14; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock source select */ + uint8_t : 2; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IM uint8_t OSCMONR; /*!< (@ 0x00000043) Oscillator Monitor Register */ + + struct + { + uint8_t : 1; + __IM uint8_t MOCOMON : 1; /*!< [1..1] MOCO operation monitor */ + __IM uint8_t LOCOMON : 1; /*!< [2..2] LOCO operation monitor */ + uint8_t : 5; + } OSCMONR_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 1; + __IOM uint16_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select */ + __IOM uint16_t PLL2MUL : 8; /*!< [15..8] PLL2 Frequency Multiplication Factor Select */ + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint16_t PLLCCR2; /*!< (@ 0x0000004C) PLL Clock Control Register 2 */ + + struct + { + __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLLCCR2_b; + }; + + union + { + __IOM uint16_t PLL2CCR2; /*!< (@ 0x0000004E) PLL2 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLL2CCR2_b; + }; + __IM uint16_t RESERVED18; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + + union + { + __IOM uint8_t SCICKDIVCR; /*!< (@ 0x00000054) SCI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } SCICKDIVCR_b; + }; + + union + { + __IOM uint8_t SCICKCR; /*!< (@ 0x00000055) SCI clock control register */ + + struct + { + __IOM uint8_t SCICKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } SCICKCR_b; + }; + + union + { + __IOM uint8_t SPICKDIVCR; /*!< (@ 0x00000056) SPI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } SPICKDIVCR_b; + }; + + union + { + __IOM uint8_t SPICKCR; /*!< (@ 0x00000057) SPI clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } SPICKCR_b; + }; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t ADCCKDIVCR; /*!< (@ 0x0000005A) ADC clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } ADCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ADCCKCR; /*!< (@ 0x0000005B) ADC clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ADCCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000005C) GPT clock Division control register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x0000005D) GPT clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t LCDCKDIVCR; /*!< (@ 0x0000005E) LCD clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */ + uint8_t : 5; + } LCDCKDIVCR_b; + }; + + union + { + __IOM uint8_t LCDCKCR; /*!< (@ 0x0000005F) LCD clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } LCDCKCR_b; + }; + __IM uint8_t RESERVED20; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED21; + __IM uint32_t RESERVED22[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB clock Division control register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI clock Division control register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Core clock Division control register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Core clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 clock Division control register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000070) I3C clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 5; + } I3CCKDIVCR_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB clock control register */ + + struct + { + __IOM uint8_t USBCKSEL : 4; /*!< [3..0] USB clock (USBCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB clock (USBCLK) Switching Request */ + __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI clock control register */ + + struct + { + __IOM uint8_t OCTACKSEL : 4; /*!< [3..0] Octal-SPI clock (OCTACLK) Source Select */ + uint8_t : 2; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI clock (OCTACLK) Switching Request */ + __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Core clock control register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 4; /*!< [3..0] CANFD Core clock (CANFDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Core clock (CANFDCLK) Switching Request */ + __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Core clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000078) I3C clock control register */ + + struct + { + __IOM uint8_t I3CCKSEL : 4; /*!< [3..0] I3C clock (I3CCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t I3CCKREQ : 1; /*!< [6..6] I3C clock (I3CCLK) Switching Request */ + __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) Switching Ready state flag */ + } I3CCKCR_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t MOSCSCR; /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register */ + + struct + { + __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select */ + uint8_t : 7; + } MOSCSCR_b; + }; + + union + { + __IOM uint8_t HOCOSCR; /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t HOCOSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select */ + uint8_t : 7; + } HOCOSCR_b; + }; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28[8]; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED29; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED30[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED31[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; + + union + { + __IOM uint32_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint32_t WDTRF : 1; /*!< [1..1] Watchdog Timer0 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint32_t SWRF : 1; /*!< [2..2] Software Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 1; + __IOM uint32_t CLU0RF : 1; /*!< [4..4] CPU0 Lockup Reset Detect Flag. NOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint32_t LM0RF : 1; /*!< [5..5] Local memory 0 error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + uint32_t : 4; + __IOM uint32_t BUSRF : 1; /*!< [10..10] Bus error Reset Detect Flag. NOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 3; + __IOM uint32_t CMRF : 1; /*!< [14..14] Common memory error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + uint32_t : 2; + __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint32_t : 3; + __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint32_t NWRF : 1; /*!< [22..22] Network Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint32_t : 9; + } RSTSR1_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IOM uint8_t SYRACCR; /*!< (@ 0x000000CC) System Register Access Control Register */ + + struct + { + __IOM uint8_t BUSY : 1; /*!< [0..0] Access Ready monitor */ + uint8_t : 7; + } SYRACCR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[4]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t CRVSYSCR; /*!< (@ 0x000000F0) Clock Recovery System Control Register */ + + struct + { + __IOM uint8_t CRVEN : 1; /*!< [0..0] Clock Recovery Enable */ + uint8_t : 7; + } CRVSYSCR_b; + }; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41[7]; + + union + { + __IOM uint8_t PDCTRGD; /*!< (@ 0x00000110) Graphics Power Domain Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRGD_b; + }; + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; + __IM uint32_t RESERVED44[11]; + __IOM uint16_t PDRAMSCR0; /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0 */ + __IOM uint8_t PDRAMSCR1; /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1 */ + __IM uint8_t RESERVED45; + __IM uint32_t RESERVED46[155]; + + union + { + __IOM uint16_t VBRSABAR; /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary + * Address Register */ + + struct + { + __IOM uint16_t SABA : 16; /*!< [15..0] Security Attribute Boundary Address */ + } VBRSABAR_b; + }; + __IM uint16_t RESERVED47; + + union + { + __IOM uint16_t VBRPABARS; /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Secure Region */ + + struct + { + __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region */ + } VBRPABARS_b; + }; + __IM uint16_t RESERVED48; + + union + { + __IOM uint16_t VBRPABARNS; /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Non-secure Region */ + + struct + { + __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure + * Region */ + } VBRPABARNS_b; + }; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non-secure Attribute bit 9 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13 */ + uint32_t : 2; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22 */ + uint32_t : 1; + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26 */ + uint32_t : 5; + } CGFSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003C4) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + uint32_t : 28; + } RSTSAR_b; + }; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 00 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 03 */ + uint32_t : 4; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 08 */ + uint32_t : 7; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + uint32_t : 1; + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + uint32_t : 10; + } LPMSAR_b; + }; + + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Programmable Voltage Detection Security Attribution + * Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + uint32_t : 27; + } BBFSAR_b; + }; + __IM uint32_t RESERVED51; + + union + { + __IOM uint32_t PGCSAR; /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02 */ + uint32_t : 29; + } PGCSAR_b; + }; + __IM uint32_t RESERVED52; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 1; + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + uint32_t : 1; + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR_b; + }; + + union + { + __IOM uint32_t RSCSAR; /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register */ + + struct + { + __IOM uint32_t RSCSA0 : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 00 */ + __IOM uint32_t RSCSA1 : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 01 */ + __IOM uint32_t RSCSA2 : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 02 */ + __IOM uint32_t RSCSA3 : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 03 */ + __IOM uint32_t RSCSA4 : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 04 */ + __IOM uint32_t RSCSA5 : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 05 */ + __IOM uint32_t RSCSA6 : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 06 */ + __IOM uint32_t RSCSA7 : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 07 */ + __IOM uint32_t RSCSA8 : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 08 */ + __IOM uint32_t RSCSA9 : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 09 */ + __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10 */ + __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11 */ + __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12 */ + __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13 */ + __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14 */ + uint32_t : 1; + __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16 */ + __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17 */ + uint32_t : 14; + } RSCSAR_b; + }; + __IM uint32_t RESERVED53[4]; + __IM uint16_t RESERVED54; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FA) Protect Register for Secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the security + * and privilege setting registers. */ + __IOM uint16_t PRC5 : 1; /*!< [5..5] Enables writing to the registers related the reset control. */ + uint16_t : 2; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_b; + }; + __IM uint16_t RESERVED55; + + union + { + __IOM uint16_t PRCR_NS; /*!< (@ 0x000003FE) Protect Register for Non-secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the privilege + * setting registers. */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_NS_b; + }; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000402) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[2]; + __IM uint16_t RESERVED59; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + __IM uint32_t RESERVED61[380]; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000A00) Deep Standby Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t DCSSMODE : 1; /*!< [2..2] DCDC SSMODE */ + uint8_t : 1; + __IOM uint8_t SRKEEP : 1; /*!< [4..4] Standby RAM Retention */ + uint8_t : 1; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000A04) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 8; /*!< [7..0] Deep Software Wait Standby Time Setting Bit */ + } DPSWCR_b; + }; + __IM uint8_t RESERVED64; + __IM uint16_t RESERVED65; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ0-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ1-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ2-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ3-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ4-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ5-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ6-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ7-DS Pin Enable */ + } DPSIER0_b; + }; + __IM uint8_t RESERVED66; + __IM uint16_t RESERVED67; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ8-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ9-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ10-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ11-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ12-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ13-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ14-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ15-DS Pin Enable */ + } DPSIER1_b; + }; + __IM uint8_t RESERVED68; + __IM uint16_t RESERVED69; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DPVD1IE : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DPVD2IE : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + __IM uint8_t RESERVED70; + __IM uint16_t RESERVED71; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT0IE : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT1IE : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DIWDTIE : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable */ + } DPSIER3_b; + }; + __IM uint8_t RESERVED72; + __IM uint16_t RESERVED73; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ0-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ1-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ2-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ3-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ4-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ5-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ6-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ7-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + __IM uint8_t RESERVED74; + __IM uint16_t RESERVED75; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ8-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ9-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ10-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ11-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ12-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ13-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ14-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ15-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + __IM uint8_t RESERVED76; + __IM uint16_t RESERVED77; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DPVD1IF : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DPVD2IF : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + __IM uint8_t RESERVED78; + __IM uint16_t RESERVED79; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DULPT0IF : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DULPT1IF : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DIWDTIF : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag */ + } DPSIFR3_b; + }; + __IM uint8_t RESERVED80; + __IM uint16_t RESERVED81; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ0-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ1-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ2-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ3-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ4-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ5-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ6-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ7-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + __IM uint8_t RESERVED82; + __IM uint16_t RESERVED83; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ8EG : 1; /*!< [0..0] IRQ8-DS Pin Edge Select */ + __IOM uint8_t DIRQ9EG : 1; /*!< [1..1] IRQ9-DS Pin Edge Select */ + __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ10-DS Pin Edge Select */ + __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ11-DS Pin Edge Select */ + __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ12-DS Pin Edge Select */ + __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ13-DS Pin Edge Select */ + __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ14-DS Pin Edge Select */ + __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ15-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + __IM uint8_t RESERVED84; + __IM uint16_t RESERVED85; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DPVD1EG : 1; /*!< [0..0] PVD1 Edge Select */ + __IOM uint8_t DPVD2EG : 1; /*!< [1..1] PVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED86; + __IM uint16_t RESERVED87; + __IM uint32_t RESERVED88; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x00000A38) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + __IM uint8_t RESERVED89; + __IM uint16_t RESERVED90; + __IM uint32_t RESERVED91; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000A40) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect Flag. NOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD3RF : 1; /*!< [4..4] Voltage Monitor 3 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD4RF : 1; /*!< [5..5] Voltage Monitor 4 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD5RF : 1; /*!< [6..6] Voltage Monitor 5 Reset Detect Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag. NOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + } RSTSR0_b; + }; + __IM uint8_t RESERVED92; + __IM uint16_t RESERVED93; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000A44) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED94; + __IM uint16_t RESERVED95; + + union + { + __IOM uint8_t RSTSR3; /*!< (@ 0x00000A48) Reset Status Register 3 */ + + struct + { + uint8_t : 4; + __IOM uint8_t OCPRF : 1; /*!< [4..4] Overcurrent protection reset Detect Flag */ + uint8_t : 3; + } RSTSR3_b; + }; + __IM uint8_t RESERVED96; + __IM uint16_t RESERVED97; + __IM uint32_t RESERVED98; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t MODRV0 : 3; /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching */ + uint8_t : 2; + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + uint8_t : 1; + } MOMCR_b; + }; + __IM uint8_t RESERVED99; + __IM uint16_t RESERVED100; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000A54) Flash Write Erase Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programing and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + __IM uint8_t RESERVED101; + __IM uint16_t RESERVED102; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000A58) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000A58) Voltage Monitor 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage 1 Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + __IM uint8_t RESERVED103; + __IM uint16_t RESERVED104; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000A5C) Voltage Monitor 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage 2 Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + __IM uint8_t RESERVED105; + __IM uint16_t RESERVED106; + __IM uint32_t RESERVED107[4]; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + __IM uint8_t RESERVED108; + __IM uint16_t RESERVED109; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED110; + __IM uint16_t RESERVED111; + __IM uint32_t RESERVED112[3]; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Voltage Monitor Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + __IM uint8_t RESERVED113; + __IM uint16_t RESERVED114; + + union + { + __IOM uint8_t VBTBPCR1; /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop */ + uint8_t : 7; + } VBTBPCR1_b; + }; + __IM uint8_t RESERVED115; + __IM uint16_t RESERVED116; + __IM uint32_t RESERVED117; + + union + { + __IOM uint8_t LPSCR; /*!< (@ 0x00000A90) Low Power State Control Register */ + + struct + { + __IOM uint8_t LPMD : 4; /*!< [3..0] Low power mode setting bit */ + uint8_t : 4; + } LPSCR_b; + }; + __IM uint8_t RESERVED118; + __IM uint16_t RESERVED119; + __IM uint32_t RESERVED120; + + union + { + __IOM uint8_t SSCR1; /*!< (@ 0x00000A98) Software Standby Control Register 1 */ + + struct + { + __IOM uint8_t SS1FR : 1; /*!< [0..0] Software Standby 1 Fast Return */ + uint8_t : 7; + } SSCR1_b; + }; + __IM uint8_t RESERVED121; + __IM uint16_t RESERVED122; + __IM uint32_t RESERVED123[5]; + + union + { + __IOM uint8_t LVOCR; /*!< (@ 0x00000AB0) Low Power State Control Register */ + + struct + { + __IOM uint8_t LVO0E : 1; /*!< [0..0] Low Voltage Operation 0 Enable */ + __IOM uint8_t LVO1E : 1; /*!< [1..1] Low Voltage Operation 1 Enable */ + uint8_t : 6; + } LVOCR_b; + }; + __IM uint8_t RESERVED124; + __IM uint16_t RESERVED125; + __IM uint32_t RESERVED126[7]; + + union + { + __IOM uint8_t SYRSTMSK0; /*!< (@ 0x00000AD0) System Reset Mask Control Register0 */ + + struct + { + __IOM uint8_t IWDTMASK : 1; /*!< [0..0] Independent watchdog timer Reset Mask */ + __IOM uint8_t WDT0MASK : 1; /*!< [1..1] CPU0 Watchdog timer Reset Mask */ + __IOM uint8_t SWMASK : 1; /*!< [2..2] Software Reset Mask */ + uint8_t : 1; + __IOM uint8_t CLUP0MASK : 1; /*!< [4..4] CPU0 Lockup Reset Mask */ + __IOM uint8_t LM0MASK : 1; /*!< [5..5] Local memory 0 error Reset Mask */ + __IOM uint8_t CMMASK : 1; /*!< [6..6] Common memory error Reset Mask */ + __IOM uint8_t BUSMASK : 1; /*!< [7..7] BUS error Reset Mask */ + } SYRSTMSK0_b; + }; + __IM uint8_t RESERVED127; + __IM uint16_t RESERVED128; + + union + { + __IOM uint8_t SYRSTMSK1; /*!< (@ 0x00000AD4) System Reset Mask Control Register1 */ + + struct + { + uint8_t : 5; + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */ + uint8_t : 1; + __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */ + } SYRSTMSK1_b; + }; + __IM uint8_t RESERVED129; + __IM uint16_t RESERVED130; + + union + { + __IOM uint8_t SYRSTMSK2; /*!< (@ 0x00000AD8) System Reset Mask Control Register2 */ + + struct + { + __IOM uint8_t LVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask */ + __IOM uint8_t LVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask */ + __IOM uint8_t LVD3MASK : 1; /*!< [2..2] Voltage Monitor 3 Reset Mask */ + __IOM uint8_t LVD4MASK : 1; /*!< [3..3] Voltage Monitor 4 Reset Mask */ + __IOM uint8_t LVD5MASK : 1; /*!< [4..4] Voltage Monitor 5 Reset Mask */ + uint8_t : 3; + } SYRSTMSK2_b; + }; + __IM uint8_t RESERVED131; + __IM uint16_t RESERVED132; + __IM uint32_t RESERVED133[10]; + + union + { + __IOM uint8_t PLL1LDOCR; /*!< (@ 0x00000B04) PLL1-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL1LDOCR_b; + }; + __IM uint8_t RESERVED134; + __IM uint16_t RESERVED135; + + union + { + __IOM uint8_t PLL2LDOCR; /*!< (@ 0x00000B08) PLL2-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL2LDOCR_b; + }; + __IM uint8_t RESERVED136; + __IM uint16_t RESERVED137; + + union + { + __IOM uint8_t HOCOLDOCR; /*!< (@ 0x00000B0C) HOCO-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } HOCOLDOCR_b; + }; + __IM uint8_t RESERVED138; + __IM uint16_t RESERVED139; + __IM uint32_t RESERVED140[4]; + + union + { + __IOM uint8_t LVD1FCR; /*!< (@ 0x00000B20) Voltage Monitor % Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD1FCR_b; + }; + __IM uint8_t RESERVED141; + __IM uint16_t RESERVED142; + + union + { + __IOM uint8_t LVD2FCR; /*!< (@ 0x00000B24) Voltage Monitor % Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD2FCR_b; + }; + __IM uint8_t RESERVED143; + __IM uint16_t RESERVED144; + __IM uint32_t RESERVED145[54]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000C00) Sub-clock oscillator control register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub Clock Oscillator Drive Capability Switching */ + uint8_t : 4; + __IOM uint8_t SOSEL : 1; /*!< [6..6] Sub Clock Oscillator Switching */ + uint8_t : 1; + } SOMCR_b; + }; + __IM uint16_t RESERVED146; + __IM uint32_t RESERVED147[15]; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x00000C40) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED148; + __IM uint16_t RESERVED149; + __IM uint8_t RESERVED150; + + union + { + __IOM uint8_t VBTBPCR2; /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2 */ + + struct + { + __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select */ + uint8_t : 1; + __IOM uint8_t VDETE : 1; /*!< [4..4] Voltage drop detection enable */ + uint8_t : 3; + } VBTBPCR2_b; + }; + + union + { + __IOM uint8_t VBTBPSR; /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register */ + + struct + { + __IOM uint8_t VBPORF : 1; /*!< [0..0] VBATT_POR Flag */ + uint8_t : 3; + __IOM uint8_t VBPORM : 1; /*!< [4..4] VBATT_POR Monitor */ + __IOM uint8_t BPWSWM : 1; /*!< [5..5] Battery Power Supply Switch Status Monitor */ + uint8_t : 2; + } VBTBPSR_b; + }; + __IM uint8_t RESERVED151; + + union + { + __IOM uint8_t VBTADSR; /*!< (@ 0x00000C48) VBATT Tamper detection Status Register */ + + struct + { + __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0 */ + __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1 */ + __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2 */ + uint8_t : 5; + } VBTADSR_b; + }; + + union + { + __IOM uint8_t VBTADCR1; /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1 */ + + struct + { + __IOM uint8_t VBTADIE0 : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0 */ + __IOM uint8_t VBTADIE1 : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1 */ + __IOM uint8_t VBTADIE2 : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2 */ + uint8_t : 1; + __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0 */ + __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1 */ + __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2 */ + uint8_t : 1; + } VBTADCR1_b; + }; + + union + { + __IOM uint8_t VBTADCR2; /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2 */ + + struct + { + __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0 */ + __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1 */ + __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2 */ + uint8_t : 5; + } VBTADCR2_b; + }; + __IM uint8_t RESERVED152; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x00000C4C) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTICTLR2; /*!< (@ 0x00000C4D) VBATT Input Control Register 2 */ + + struct + { + __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable */ + __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable */ + __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable */ + uint8_t : 1; + __IOM uint8_t VCH0EG : 1; /*!< [4..4] VBATT CH0 Input Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [5..5] VBATT CH1 Input Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [6..6] VBATT CH2 Input Edge Select */ + uint8_t : 1; + } VBTICTLR2_b; + }; + + union + { + __IOM uint8_t VBTIMONR; /*!< (@ 0x00000C4E) VBATT Input Monitor Register */ + + struct + { + __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor */ + __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor */ + __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor */ + uint8_t : 5; + } VBTIMONR_b; + }; + __IM uint8_t RESERVED153; + __IM uint32_t RESERVED154[44]; + + union + { + __IOM uint8_t VBTBKR0; /*!< (@ 0x00000D00) VBATT Backup Register 0 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR0_b; + }; + + union + { + __IOM uint8_t VBTBKR1; /*!< (@ 0x00000D01) VBATT Backup Register 1 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR1_b; + }; + + union + { + __IOM uint8_t VBTBKR2; /*!< (@ 0x00000D02) VBATT Backup Register 2 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR2_b; + }; + + union + { + __IOM uint8_t VBTBKR3; /*!< (@ 0x00000D03) VBATT Backup Register 3 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR3_b; + }; + + union + { + __IOM uint8_t VBTBKR4; /*!< (@ 0x00000D04) VBATT Backup Register 4 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR4_b; + }; + + union + { + __IOM uint8_t VBTBKR5; /*!< (@ 0x00000D05) VBATT Backup Register 5 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR5_b; + }; + + union + { + __IOM uint8_t VBTBKR6; /*!< (@ 0x00000D06) VBATT Backup Register 6 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR6_b; + }; + + union + { + __IOM uint8_t VBTBKR7; /*!< (@ 0x00000D07) VBATT Backup Register 7 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR7_b; + }; + + union + { + __IOM uint8_t VBTBKR8; /*!< (@ 0x00000D08) VBATT Backup Register 8 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR8_b; + }; + + union + { + __IOM uint8_t VBTBKR9; /*!< (@ 0x00000D09) VBATT Backup Register 9 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR9_b; + }; + + union + { + __IOM uint8_t VBTBKR10; /*!< (@ 0x00000D0A) VBATT Backup Register 10 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR10_b; + }; + + union + { + __IOM uint8_t VBTBKR11; /*!< (@ 0x00000D0B) VBATT Backup Register 11 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR11_b; + }; + + union + { + __IOM uint8_t VBTBKR12; /*!< (@ 0x00000D0C) VBATT Backup Register 12 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR12_b; + }; + + union + { + __IOM uint8_t VBTBKR13; /*!< (@ 0x00000D0D) VBATT Backup Register 13 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR13_b; + }; + + union + { + __IOM uint8_t VBTBKR14; /*!< (@ 0x00000D0E) VBATT Backup Register 14 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR14_b; + }; + + union + { + __IOM uint8_t VBTBKR15; /*!< (@ 0x00000D0F) VBATT Backup Register 15 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR15_b; + }; + + union + { + __IOM uint8_t VBTBKR16; /*!< (@ 0x00000D10) VBATT Backup Register 16 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR16_b; + }; + + union + { + __IOM uint8_t VBTBKR17; /*!< (@ 0x00000D11) VBATT Backup Register 17 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR17_b; + }; + + union + { + __IOM uint8_t VBTBKR18; /*!< (@ 0x00000D12) VBATT Backup Register 18 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR18_b; + }; + + union + { + __IOM uint8_t VBTBKR19; /*!< (@ 0x00000D13) VBATT Backup Register 19 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR19_b; + }; + + union + { + __IOM uint8_t VBTBKR20; /*!< (@ 0x00000D14) VBATT Backup Register 20 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR20_b; + }; + + union + { + __IOM uint8_t VBTBKR21; /*!< (@ 0x00000D15) VBATT Backup Register 21 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR21_b; + }; + + union + { + __IOM uint8_t VBTBKR22; /*!< (@ 0x00000D16) VBATT Backup Register 22 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR22_b; + }; + + union + { + __IOM uint8_t VBTBKR23; /*!< (@ 0x00000D17) VBATT Backup Register 23 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR23_b; + }; + + union + { + __IOM uint8_t VBTBKR24; /*!< (@ 0x00000D18) VBATT Backup Register 24 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR24_b; + }; + + union + { + __IOM uint8_t VBTBKR25; /*!< (@ 0x00000D19) VBATT Backup Register 25 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR25_b; + }; + + union + { + __IOM uint8_t VBTBKR26; /*!< (@ 0x00000D1A) VBATT Backup Register 26 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR26_b; + }; + + union + { + __IOM uint8_t VBTBKR27; /*!< (@ 0x00000D1B) VBATT Backup Register 27 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR27_b; + }; + + union + { + __IOM uint8_t VBTBKR28; /*!< (@ 0x00000D1C) VBATT Backup Register 28 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR28_b; + }; + + union + { + __IOM uint8_t VBTBKR29; /*!< (@ 0x00000D1D) VBATT Backup Register 29 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR29_b; + }; + + union + { + __IOM uint8_t VBTBKR30; /*!< (@ 0x00000D1E) VBATT Backup Register 30 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR30_b; + }; + + union + { + __IOM uint8_t VBTBKR31; /*!< (@ 0x00000D1F) VBATT Backup Register 31 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR31_b; + }; + + union + { + __IOM uint8_t VBTBKR32; /*!< (@ 0x00000D20) VBATT Backup Register 32 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR32_b; + }; + + union + { + __IOM uint8_t VBTBKR33; /*!< (@ 0x00000D21) VBATT Backup Register 33 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR33_b; + }; + + union + { + __IOM uint8_t VBTBKR34; /*!< (@ 0x00000D22) VBATT Backup Register 34 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR34_b; + }; + + union + { + __IOM uint8_t VBTBKR35; /*!< (@ 0x00000D23) VBATT Backup Register 35 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR35_b; + }; + + union + { + __IOM uint8_t VBTBKR36; /*!< (@ 0x00000D24) VBATT Backup Register 36 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR36_b; + }; + + union + { + __IOM uint8_t VBTBKR37; /*!< (@ 0x00000D25) VBATT Backup Register 37 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR37_b; + }; + + union + { + __IOM uint8_t VBTBKR38; /*!< (@ 0x00000D26) VBATT Backup Register 38 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR38_b; + }; + + union + { + __IOM uint8_t VBTBKR39; /*!< (@ 0x00000D27) VBATT Backup Register 39 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR39_b; + }; + + union + { + __IOM uint8_t VBTBKR40; /*!< (@ 0x00000D28) VBATT Backup Register 40 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR40_b; + }; + + union + { + __IOM uint8_t VBTBKR41; /*!< (@ 0x00000D29) VBATT Backup Register 41 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR41_b; + }; + + union + { + __IOM uint8_t VBTBKR42; /*!< (@ 0x00000D2A) VBATT Backup Register 42 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR42_b; + }; + + union + { + __IOM uint8_t VBTBKR43; /*!< (@ 0x00000D2B) VBATT Backup Register 43 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR43_b; + }; + + union + { + __IOM uint8_t VBTBKR44; /*!< (@ 0x00000D2C) VBATT Backup Register 44 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR44_b; + }; + + union + { + __IOM uint8_t VBTBKR45; /*!< (@ 0x00000D2D) VBATT Backup Register 45 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR45_b; + }; + + union + { + __IOM uint8_t VBTBKR46; /*!< (@ 0x00000D2E) VBATT Backup Register 46 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR46_b; + }; + + union + { + __IOM uint8_t VBTBKR47; /*!< (@ 0x00000D2F) VBATT Backup Register 47 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR47_b; + }; + + union + { + __IOM uint8_t VBTBKR48; /*!< (@ 0x00000D30) VBATT Backup Register 48 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR48_b; + }; + + union + { + __IOM uint8_t VBTBKR49; /*!< (@ 0x00000D31) VBATT Backup Register 49 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR49_b; + }; + + union + { + __IOM uint8_t VBTBKR50; /*!< (@ 0x00000D32) VBATT Backup Register 50 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR50_b; + }; + + union + { + __IOM uint8_t VBTBKR51; /*!< (@ 0x00000D33) VBATT Backup Register 51 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR51_b; + }; + + union + { + __IOM uint8_t VBTBKR52; /*!< (@ 0x00000D34) VBATT Backup Register 52 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR52_b; + }; + + union + { + __IOM uint8_t VBTBKR53; /*!< (@ 0x00000D35) VBATT Backup Register 53 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR53_b; + }; + + union + { + __IOM uint8_t VBTBKR54; /*!< (@ 0x00000D36) VBATT Backup Register 54 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR54_b; + }; + + union + { + __IOM uint8_t VBTBKR55; /*!< (@ 0x00000D37) VBATT Backup Register 55 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR55_b; + }; + + union + { + __IOM uint8_t VBTBKR56; /*!< (@ 0x00000D38) VBATT Backup Register 56 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR56_b; + }; + + union + { + __IOM uint8_t VBTBKR57; /*!< (@ 0x00000D39) VBATT Backup Register 57 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR57_b; + }; + + union + { + __IOM uint8_t VBTBKR58; /*!< (@ 0x00000D3A) VBATT Backup Register 58 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR58_b; + }; + + union + { + __IOM uint8_t VBTBKR59; /*!< (@ 0x00000D3B) VBATT Backup Register 59 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR59_b; + }; + + union + { + __IOM uint8_t VBTBKR60; /*!< (@ 0x00000D3C) VBATT Backup Register 60 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR60_b; + }; + + union + { + __IOM uint8_t VBTBKR61; /*!< (@ 0x00000D3D) VBATT Backup Register 61 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR61_b; + }; + + union + { + __IOM uint8_t VBTBKR62; /*!< (@ 0x00000D3E) VBATT Backup Register 62 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR62_b; + }; + + union + { + __IOM uint8_t VBTBKR63; /*!< (@ 0x00000D3F) VBATT Backup Register 63 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR63_b; + }; + + union + { + __IOM uint8_t VBTBKR64; /*!< (@ 0x00000D40) VBATT Backup Register 64 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR64_b; + }; + + union + { + __IOM uint8_t VBTBKR65; /*!< (@ 0x00000D41) VBATT Backup Register 65 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR65_b; + }; + + union + { + __IOM uint8_t VBTBKR66; /*!< (@ 0x00000D42) VBATT Backup Register 66 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR66_b; + }; + + union + { + __IOM uint8_t VBTBKR67; /*!< (@ 0x00000D43) VBATT Backup Register 67 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR67_b; + }; + + union + { + __IOM uint8_t VBTBKR68; /*!< (@ 0x00000D44) VBATT Backup Register 68 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR68_b; + }; + + union + { + __IOM uint8_t VBTBKR69; /*!< (@ 0x00000D45) VBATT Backup Register 69 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR69_b; + }; + + union + { + __IOM uint8_t VBTBKR70; /*!< (@ 0x00000D46) VBATT Backup Register 70 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR70_b; + }; + + union + { + __IOM uint8_t VBTBKR71; /*!< (@ 0x00000D47) VBATT Backup Register 71 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR71_b; + }; + + union + { + __IOM uint8_t VBTBKR72; /*!< (@ 0x00000D48) VBATT Backup Register 72 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR72_b; + }; + + union + { + __IOM uint8_t VBTBKR73; /*!< (@ 0x00000D49) VBATT Backup Register 73 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR73_b; + }; + + union + { + __IOM uint8_t VBTBKR74; /*!< (@ 0x00000D4A) VBATT Backup Register 74 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR74_b; + }; + + union + { + __IOM uint8_t VBTBKR75; /*!< (@ 0x00000D4B) VBATT Backup Register 75 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR75_b; + }; + + union + { + __IOM uint8_t VBTBKR76; /*!< (@ 0x00000D4C) VBATT Backup Register 76 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR76_b; + }; + + union + { + __IOM uint8_t VBTBKR77; /*!< (@ 0x00000D4D) VBATT Backup Register 77 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR77_b; + }; + + union + { + __IOM uint8_t VBTBKR78; /*!< (@ 0x00000D4E) VBATT Backup Register 78 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR78_b; + }; + + union + { + __IOM uint8_t VBTBKR79; /*!< (@ 0x00000D4F) VBATT Backup Register 79 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR79_b; + }; + + union + { + __IOM uint8_t VBTBKR80; /*!< (@ 0x00000D50) VBATT Backup Register 80 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR80_b; + }; + + union + { + __IOM uint8_t VBTBKR81; /*!< (@ 0x00000D51) VBATT Backup Register 81 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR81_b; + }; + + union + { + __IOM uint8_t VBTBKR82; /*!< (@ 0x00000D52) VBATT Backup Register 82 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR82_b; + }; + + union + { + __IOM uint8_t VBTBKR83; /*!< (@ 0x00000D53) VBATT Backup Register 83 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR83_b; + }; + + union + { + __IOM uint8_t VBTBKR84; /*!< (@ 0x00000D54) VBATT Backup Register 84 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR84_b; + }; + + union + { + __IOM uint8_t VBTBKR85; /*!< (@ 0x00000D55) VBATT Backup Register 85 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR85_b; + }; + + union + { + __IOM uint8_t VBTBKR86; /*!< (@ 0x00000D56) VBATT Backup Register 86 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR86_b; + }; + + union + { + __IOM uint8_t VBTBKR87; /*!< (@ 0x00000D57) VBATT Backup Register 87 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR87_b; + }; + + union + { + __IOM uint8_t VBTBKR88; /*!< (@ 0x00000D58) VBATT Backup Register 88 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR88_b; + }; + + union + { + __IOM uint8_t VBTBKR89; /*!< (@ 0x00000D59) VBATT Backup Register 89 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR89_b; + }; + + union + { + __IOM uint8_t VBTBKR90; /*!< (@ 0x00000D5A) VBATT Backup Register 90 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR90_b; + }; + + union + { + __IOM uint8_t VBTBKR91; /*!< (@ 0x00000D5B) VBATT Backup Register 91 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR91_b; + }; + + union + { + __IOM uint8_t VBTBKR92; /*!< (@ 0x00000D5C) VBATT Backup Register 92 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR92_b; + }; + + union + { + __IOM uint8_t VBTBKR93; /*!< (@ 0x00000D5D) VBATT Backup Register 93 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR93_b; + }; + + union + { + __IOM uint8_t VBTBKR94; /*!< (@ 0x00000D5E) VBATT Backup Register 94 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR94_b; + }; + + union + { + __IOM uint8_t VBTBKR95; /*!< (@ 0x00000D5F) VBATT Backup Register 95 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR95_b; + }; + + union + { + __IOM uint8_t VBTBKR96; /*!< (@ 0x00000D60) VBATT Backup Register 96 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR96_b; + }; + + union + { + __IOM uint8_t VBTBKR97; /*!< (@ 0x00000D61) VBATT Backup Register 97 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR97_b; + }; + + union + { + __IOM uint8_t VBTBKR98; /*!< (@ 0x00000D62) VBATT Backup Register 98 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR98_b; + }; + + union + { + __IOM uint8_t VBTBKR99; /*!< (@ 0x00000D63) VBATT Backup Register 99 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR99_b; + }; + + union + { + __IOM uint8_t VBTBKR100; /*!< (@ 0x00000D64) VBATT Backup Register 100 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR100_b; + }; + + union + { + __IOM uint8_t VBTBKR101; /*!< (@ 0x00000D65) VBATT Backup Register 101 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR101_b; + }; + + union + { + __IOM uint8_t VBTBKR102; /*!< (@ 0x00000D66) VBATT Backup Register 102 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR102_b; + }; + + union + { + __IOM uint8_t VBTBKR103; /*!< (@ 0x00000D67) VBATT Backup Register 103 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR103_b; + }; + + union + { + __IOM uint8_t VBTBKR104; /*!< (@ 0x00000D68) VBATT Backup Register 104 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR104_b; + }; + + union + { + __IOM uint8_t VBTBKR105; /*!< (@ 0x00000D69) VBATT Backup Register 105 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR105_b; + }; + + union + { + __IOM uint8_t VBTBKR106; /*!< (@ 0x00000D6A) VBATT Backup Register 106 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR106_b; + }; + + union + { + __IOM uint8_t VBTBKR107; /*!< (@ 0x00000D6B) VBATT Backup Register 107 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR107_b; + }; + + union + { + __IOM uint8_t VBTBKR108; /*!< (@ 0x00000D6C) VBATT Backup Register 108 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR108_b; + }; + + union + { + __IOM uint8_t VBTBKR109; /*!< (@ 0x00000D6D) VBATT Backup Register 109 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR109_b; + }; + + union + { + __IOM uint8_t VBTBKR110; /*!< (@ 0x00000D6E) VBATT Backup Register 110 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR110_b; + }; + + union + { + __IOM uint8_t VBTBKR111; /*!< (@ 0x00000D6F) VBATT Backup Register 111 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR111_b; + }; + + union + { + __IOM uint8_t VBTBKR112; /*!< (@ 0x00000D70) VBATT Backup Register 112 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR112_b; + }; + + union + { + __IOM uint8_t VBTBKR113; /*!< (@ 0x00000D71) VBATT Backup Register 113 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR113_b; + }; + + union + { + __IOM uint8_t VBTBKR114; /*!< (@ 0x00000D72) VBATT Backup Register 114 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR114_b; + }; + + union + { + __IOM uint8_t VBTBKR115; /*!< (@ 0x00000D73) VBATT Backup Register 115 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR115_b; + }; + + union + { + __IOM uint8_t VBTBKR116; /*!< (@ 0x00000D74) VBATT Backup Register 116 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR116_b; + }; + + union + { + __IOM uint8_t VBTBKR117; /*!< (@ 0x00000D75) VBATT Backup Register 117 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR117_b; + }; + + union + { + __IOM uint8_t VBTBKR118; /*!< (@ 0x00000D76) VBATT Backup Register 118 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR118_b; + }; + + union + { + __IOM uint8_t VBTBKR119; /*!< (@ 0x00000D77) VBATT Backup Register 119 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR119_b; + }; + + union + { + __IOM uint8_t VBTBKR120; /*!< (@ 0x00000D78) VBATT Backup Register 120 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR120_b; + }; + + union + { + __IOM uint8_t VBTBKR121; /*!< (@ 0x00000D79) VBATT Backup Register 121 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR121_b; + }; + + union + { + __IOM uint8_t VBTBKR122; /*!< (@ 0x00000D7A) VBATT Backup Register 122 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR122_b; + }; + + union + { + __IOM uint8_t VBTBKR123; /*!< (@ 0x00000D7B) VBATT Backup Register 123 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR123_b; + }; + + union + { + __IOM uint8_t VBTBKR124; /*!< (@ 0x00000D7C) VBATT Backup Register 124 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR124_b; + }; + + union + { + __IOM uint8_t VBTBKR125; /*!< (@ 0x00000D7D) VBATT Backup Register 125 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR125_b; + }; + + union + { + __IOM uint8_t VBTBKR126; /*!< (@ 0x00000D7E) VBATT Backup Register 126 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR126_b; + }; + + union + { + __IOM uint8_t VBTBKR127; /*!< (@ 0x00000D7F) VBATT Backup Register 127 */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */ + } VBTBKR127_b; + }; +} R_SYSTEM_Type; /*!< Size = 3456 (0xd80) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x4011B17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x40235000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40202600) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */ + uint32_t : 2; + __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23 */ + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */ + uint32_t : 17; + } ICUSARF_b; + }; + + union + { + __IOM uint32_t ICUSARM; /*!< (@ 0x00000058) ICU Security Attribution Register M */ + + struct + { + __IOM uint32_t SAINTUR0WUP : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0 */ + __IOM uint32_t SAINTURE0WUP : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1 */ + __IOM uint32_t SAINTUR1WUP : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2 */ + __IOM uint32_t SAINTURE1WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3 */ + __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4 */ + __IOM uint32_t SALVDVRTCWUP : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5 */ + __IOM uint32_t SAEXLVDWUP : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6 */ + uint32_t : 25; + } ICUSARM_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[6]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED7[18]; + + union + { + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + }; + __IM uint32_t RESERVED8[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */ + + struct + { + __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC + * channel */ + uint32_t : 24; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED10[147]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register + * 0 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register + * 1 */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start + * address of non-secure region). */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + __IM uint32_t RESERVED11[126]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn + * and ELCSRn */ + uint32_t : 31; + } TEVTRCR_b; + }; +} R_CPSCU_Type; /*!< Size = 1540 (0x604) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC_B) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC_B Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */ + __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */ + + struct + { + __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */ + uint8_t : 7; + } DOSR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */ + + struct + { + __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */ + uint8_t : 7; + } DOSCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */ + __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */ + __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */ +} R_DOC_B_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI_B0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI_B0 Structure */ +{ + union + { + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint8_t RDR_BY; /*!< (@ 0x00000000) Receive Data Register (byte access) */ + + struct + { + __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data */ + } RDR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 2; + __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */ + uint32_t : 19; + } TDR_b; + }; + + union + { + __IOM uint8_t TDR_BY; /*!< (@ 0x00000004) Transmit Data Register (byte access) */ + + struct + { + __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data */ + } TDR_BY_b; + }; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 1; + __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit. */ + uint32_t : 4; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + + union + { + __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */ + + struct + { + __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */ + uint8_t : 3; + __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */ + uint8_t : 3; + } CESR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */ + + struct + { + __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint32_t : 1; + __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */ + __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + uint32_t : 1; + __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */ + __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */ + uint32_t : 2; + __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */ + __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */ + uint32_t : 2; + __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */ + __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */ + __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */ + uint32_t : 5; + } MCR_b; + }; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + + union + { + __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */ + + struct + { + __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */ + uint32_t : 6; + __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */ + __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */ + __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */ + __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */ + __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */ + __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */ + __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */ + uint32_t : 2; + __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */ + __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */ + __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */ + uint32_t : 1; + __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */ + uint32_t : 6; + } XCR0_b; + }; + + union + { + __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */ + + struct + { + __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */ + uint32_t : 3; + __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */ + __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */ + uint32_t : 2; + __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */ + __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */ + __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */ + } XCR1_b; + }; + + union + { + __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */ + + struct + { + __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */ + __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */ + __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */ + } XCR2_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */ + __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */ + __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + + union + { + __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */ + + struct + { + __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */ + __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */ + __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */ + uint32_t : 1; + __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */ + uint32_t : 1; + __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */ + uint32_t : 25; + } MSR_b; + }; + + union + { + __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */ + + struct + { + __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */ + __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */ + uint32_t : 6; + __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */ + __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */ + __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */ + __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */ + __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */ + __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */ + __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */ + __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */ + __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */ + __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */ + } XSR0_b; + }; + + union + { + __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */ + + struct + { + __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */ + uint32_t : 16; + } XSR1_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */ + __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */ + __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */ + uint32_t : 31; + } FFCLR_b; + }; + + union + { + __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */ + + struct + { + __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */ + __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */ + __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */ + uint32_t : 1; + __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */ + uint32_t : 27; + } MFCLR_b; + }; + + union + { + __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */ + __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */ + __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */ + __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */ + __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */ + __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */ + __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */ + __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */ + uint32_t : 16; + } XFCLR_b; + }; +} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI_B0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI_B0 Structure */ +{ + __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */ + + union + { + __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */ + + struct + { + __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */ + uint32_t : 5; + __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */ + uint32_t : 5; + __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */ + uint32_t : 5; + __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */ + uint32_t : 5; + } SPDECR_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */ + + struct + { + __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint32_t : 1; + __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */ + __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */ + __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */ + __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */ + __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */ + uint32_t : 2; + __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */ + __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */ + uint32_t : 10; + } SPCR2_b; + }; + + union + { + __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */ + + struct + { + __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */ + __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */ + __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */ + __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */ + uint32_t : 4; + __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */ + uint32_t : 8; + __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */ + uint32_t : 5; + } SPCR3_b; + }; + + union + { + __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD0_b; + }; + + union + { + __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD1_b; + }; + + union + { + __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD2_b; + }; + + union + { + __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD3_b; + }; + + union + { + __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD4_b; + }; + + union + { + __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD5_b; + }; + + union + { + __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD6_b; + }; + + union + { + __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD7_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */ + + struct + { + __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint32_t : 2; + __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */ + __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */ + uint32_t : 3; + __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */ + uint32_t : 22; + } SPDCR_b; + }; + + union + { + __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */ + + struct + { + __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint32_t : 6; + __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint32_t : 22; + } SPDCR2_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */ + uint32_t : 1; + __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */ + uint32_t : 8; + __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */ + __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */ + __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */ + __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */ + __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */ + __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */ + __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */ + + struct + { + __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint32_t : 29; + } SPTFSR_b; + }; + + union + { + __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */ + + struct + { + __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint32_t : 29; + } SPRFSR_b; + }; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */ + + struct + { + uint32_t : 23; + __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */ + __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */ + uint32_t : 1; + __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */ + __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */ + __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */ + __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */ + __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */ + __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */ + + struct + { + __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */ + uint32_t : 31; + } SPFCR_b; + }; +} R_SPI_B0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief eXpanded SPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x40268000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration register */ + + struct + { + __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 3; + __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration register */ + + struct + { + __IOM uint32_t ARBMD : 2; /*!< [1..0] Channel arbitration mode */ + uint32_t : 2; + __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable */ + uint32_t : 10; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFGCH[2]; /*!< (@ 0x00000008) xSPI Bridge Map Configuration register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 7; + __IOM uint32_t CMBTIM : 8; /*!< [31..24] Combination timer */ + } BMCFGCH_b[2]; + }; + __IOM R_XSPI0_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers */ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1] */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + + union + { + __IOM uint32_t ABMCFG; /*!< (@ 0x00000058) xSPI AXI Bridge Map Config */ + + struct + { + __IOM uint32_t ODRMD : 2; /*!< [1..0] AXI Transfer Ordering Mode */ + uint32_t : 14; + __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select */ + } ABMCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control register 0 */ + + struct + { + __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable */ + __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable */ + __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable */ + __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable */ + uint32_t : 24; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0 */ + __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1 */ + __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0 */ + __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1 */ + uint32_t : 20; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTLCH[2]; /*!< (@ 0x00000068) xSPI Command Map Control register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTLCH_b[2]; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED2; + __IOM R_XSPI0_CDBUF_Type CDBUF[4]; /*!< (@ 0x00000080) xSPI BUF register */ + __IM uint32_t RESERVED3[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave 0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave 1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_XSPI0_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register */ + __IM uint32_t RESERVED5[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status register */ + + struct + { + __IM uint32_t MEMACCCH0 : 1; /*!< [0..0] Memory access ongoing from ch0 */ + __IM uint32_t MEMACCCH1 : 1; /*!< [1..1] Memory access ongoing from ch1 */ + uint32_t : 2; + __IM uint32_t PBUFNECH0 : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0 */ + __IM uint32_t PBUFNECH1 : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1 */ + __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0 */ + __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1 */ + uint32_t : 8; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status register */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOFCH0 : 1; /*!< [16..16] Bridge Buffer overflow for CH0 */ + __IM uint32_t BRGOFCH1 : 1; /*!< [17..17] Bridge Buffer overflow for CH1 */ + __IM uint32_t BRGUFCH0 : 1; /*!< [18..18] Bridge Buffer underflow for CH0 */ + __IM uint32_t BRGUFCH1 : 1; /*!< [19..19] Bridge Buffer underflow for CH1 */ + __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0 */ + __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1 */ + uint32_t : 6; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFCH0C : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear */ + __OM uint32_t BRGOFCH1C : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear */ + __OM uint32_t BRGUFCH0C : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear */ + __OM uint32_t BRGUFCH1C : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear */ + __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear */ + __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear */ + uint32_t : 6; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFCH0E : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable */ + __IOM uint32_t BRGOFCH1E : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable */ + __IOM uint32_t BRGUFCH0E : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable */ + __IOM uint32_t BRGUFCH1E : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable */ + __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable */ + __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable */ + uint32_t : 6; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capture Engine Unit (R_CEU) + */ + +typedef struct /*!< (@ 0x40348000) R_CEU Structure */ +{ + union + { + __IOM uint32_t CAPSR; /*!< (@ 0x00000000) Capture Start Register */ + + struct + { + __IOM uint32_t CE : 1; /*!< [0..0] Capture enable */ + uint32_t : 15; + __IOM uint32_t CPKIL : 1; /*!< [16..16] Write 1 to this bit to perform a software reset of + * capturing. */ + uint32_t : 15; + } CAPSR_b; + }; + + union + { + __IOM uint32_t CAPCR; /*!< (@ 0x00000004) Capture Control Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CTNCP : 1; /*!< [16..16] When capturing is started with this bit set to 1, capturing + * continues until the CE bit in CAPSR is cleared to 0 or + * a software reset is initiated by the CPKIL bit in CAPSR + * (see ). Continuous capture must be set before capturing + * is started. */ + uint32_t : 3; + __IOM uint32_t MTCM : 2; /*!< [21..20] Specify the unit for transferring data to a bus bridge + * module. */ + uint32_t : 2; + __IOM uint32_t FDRP : 8; /*!< [31..24] Set the frame drop interval in continuous-frame capture. */ + } CAPCR_b; + }; + + union + { + __IOM uint32_t CAMCR; /*!< (@ 0x00000008) Capture interface control register */ + + struct + { + __IOM uint32_t HDPOL : 1; /*!< [0..0] Sets the polarity for detection of the horizontal sync + * signal input from an external module. */ + __IOM uint32_t VDPOL : 1; /*!< [1..1] Sets the polarity for detection of the vertical sync + * signal input from an external module. */ + uint32_t : 2; + __IOM uint32_t JPG : 2; /*!< [5..4] These bits select the fetched data type. */ + uint32_t : 2; + __IOM uint32_t DTARY : 2; /*!< [9..8] Set the input order of the luminance component and chrominance + * component. */ + uint32_t : 2; + __IOM uint32_t DTIF : 1; /*!< [12..12] Sets the digital image input pins from which data is + * to be captured. */ + uint32_t : 3; + __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal + * (FLD) from an external module. */ + uint32_t : 7; + __IOM uint32_t DSEL : 1; /*!< [24..24] Sets the edge for fetching the image data (D7 to D0) + * from an external module. */ + __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification + * signal (FLD) from an external module. */ + __IOM uint32_t HDSEL : 1; /*!< [26..26] Sets the edge for capturing the horizontal sync signal + * (HD) from an external module. */ + __IOM uint32_t VDSEL : 1; /*!< [27..27] Sets the edge for capturing the vertical sync signal + * (VD) from an external module. */ + uint32_t : 4; + } CAMCR_b; + }; + + union + { + __IOM uint32_t CMCYR; /*!< (@ 0x0000000C) Capture Interface Cycle Register */ + + struct + { + __IOM uint32_t HCYL : 14; /*!< [13..0] Horizontal Cycle Count of External Module */ + uint32_t : 2; + __IOM uint32_t VCYL : 14; /*!< [29..16] Vertical HD Count of External Module */ + uint32_t : 2; + } CMCYR_b; + }; + + union + { + __IOM uint32_t CAMOR; /*!< (@ 0x00000010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_b; + }; + + union + { + __IOM uint32_t CAPWR; /*!< (@ 0x00000014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_b; + }; + + union + { + __IOM uint32_t CAIFR; /*!< (@ 0x00000018) Capture Interface Input Format Register */ + + struct + { + __IOM uint32_t FCI : 2; /*!< [1..0] Set the timing to start capturing. */ + uint32_t : 2; + __IOM uint32_t CIM : 1; /*!< [4..4] Sets the images to be captured. */ + uint32_t : 3; + __IOM uint32_t IFS : 1; /*!< [8..8] Sets the input mode for capturing images. */ + uint32_t : 23; + } CAIFR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CRCNTR; /*!< (@ 0x00000028) CEU Register Control Register */ + + struct + { + __IOM uint32_t RC : 1; /*!< [0..0] Specifies switching of the register plane used by the + * CEU in synchronization with VD. */ + __IOM uint32_t RS : 1; /*!< [1..1] Specifies which register plane is used by the CEU in + * synchronization with VD. */ + uint32_t : 2; + __IOM uint32_t RVS : 1; /*!< [4..4] Sets the timing to switch the register plane in both-field + * capture. */ + uint32_t : 27; + } CRCNTR_b; + }; + + union + { + __IOM uint32_t CRCMPR; /*!< (@ 0x0000002C) CEU Register Forcible Control Register */ + + struct + { + __IOM uint32_t RA : 1; /*!< [0..0] Indicates the register plane currently specified. */ + uint32_t : 31; + } CRCMPR_b; + }; + + union + { + __IOM uint32_t CFLCR; /*!< (@ 0x00000030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_b; + }; + + union + { + __IOM uint32_t CFSZR; /*!< (@ 0x00000034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_b; + }; + + union + { + __IOM uint32_t CDWDR; /*!< (@ 0x00000038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_b; + }; + + union + { + __IOM uint32_t CDAYR; /*!< (@ 0x0000003C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_b; + }; + + union + { + __IOM uint32_t CDACR; /*!< (@ 0x00000040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_b; + }; + + union + { + __IOM uint32_t CDBYR; /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_b; + }; + + union + { + __IOM uint32_t CDBCR; /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_b; + }; + + union + { + __IOM uint32_t CBDSR; /*!< (@ 0x0000004C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFWCR; /*!< (@ 0x0000005C) Firewall Operation Control Register */ + + struct + { + __IOM uint32_t FWE : 1; /*!< [0..0] With the setting of FWE = 1, when an address exceeds + * the value set with FWV, the address is retained and an + * interrupt source FWF is set. After this, the address is + * not incremented and data is overwritten on the upper limit + * address. */ + uint32_t : 4; + __IOM uint32_t FWV : 27; /*!< [31..5] Specify the upper limit of a write address. */ + } CFWCR_b; + }; + + union + { + __IOM uint32_t CLFCR; /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_b; + }; + + union + { + __IOM uint32_t CDOCR; /*!< (@ 0x00000064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CEIER; /*!< (@ 0x00000070) Capture Event Interrupt Enable Register */ + + struct + { + __IOM uint32_t CPEIE : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable */ + __IOM uint32_t CFEIE : 1; /*!< [1..1] CFE Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t IGRWIE : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t HDIE : 1; /*!< [8..8] HD Interrupt Enable */ + __IOM uint32_t VDIE : 1; /*!< [9..9] VD Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable */ + __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable */ + __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable */ + __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable */ + __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable */ + __IOM uint32_t IGHSIE : 1; /*!< [17..17] IGHS Interrupt Enable */ + __IOM uint32_t IGVSIE : 1; /*!< [18..18] IGVS Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBPIE : 1; /*!< [20..20] VBP Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FWFIE : 1; /*!< [23..23] FWF Interrupt Enable */ + __IOM uint32_t NHDIE : 1; /*!< [24..24] Non-HD Interrupt Enable */ + __IOM uint32_t NVDIE : 1; /*!< [25..25] Non-VD Interrupt Enable */ + uint32_t : 6; + } CEIER_b; + }; + + union + { + __IOM uint32_t CETCR; /*!< (@ 0x00000074) Capture Event Flag Clear Register */ + + struct + { + __IOM uint32_t CPE : 1; /*!< [0..0] An interrupt indicating that capturing of one frame from + * an external module has finished. */ + __IOM uint32_t CFE : 1; /*!< [1..1] An interrupt indicating that capturing of one field from + * an external module has finished. */ + uint32_t : 2; + __IOM uint32_t IGRW : 1; /*!< [4..4] An interrupt indicating that during capturing, access + * was attempted to a register to which writing during operation + * is prohibited. */ + uint32_t : 3; + __IOM uint32_t HD : 1; /*!< [8..8] An interrupt indicating that HD (horizontal sync signal) + * was input from an external module. */ + __IOM uint32_t VD : 1; /*!< [9..9] An interrupt indicating that VD (vertical sync signal) + * was input from an external module. */ + uint32_t : 2; + __IOM uint32_t CPBE1 : 1; /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR + * in a bundle write has finished. */ + __IOM uint32_t CPBE2 : 1; /*!< [13..13] An interrupt indicating that writing to CDAYR2 and + * CDACR2 in a bundle write has finished. */ + __IOM uint32_t CPBE3 : 1; /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR + * in a bundle write has finished. */ + __IOM uint32_t CPBE4 : 1; /*!< [15..15] An interrupt indicating that writing to CDBYR2 and + * CDBCR2 in a bundle write has finished. */ + __IOM uint32_t CDTOF : 1; /*!< [16..16] An interrupt indicating that data overflowed in the + * CRAM of the write buffer */ + __IOM uint32_t IGHS : 1; /*!< [17..17] An interrupt generated when the number of HD cycles + * set in CMCYR differ from the number of HD cycles input + * from an external module. */ + __IOM uint32_t IGVS : 1; /*!< [18..18] An interrupt generated when the number of VD cycles + * set in CMCYR differ from the number of VD cycles input + * from an external module. */ + uint32_t : 1; + __IOM uint32_t VBP : 1; /*!< [20..20] An interrupt indicating that VD has been input while + * the CEU holds data (insufficient vertical-sync front porch). */ + uint32_t : 2; + __IOM uint32_t FWF : 1; /*!< [23..23] The interrupt is generated when data is written to + * the address that exceeds the value specified with CFWCR.FMV. */ + __IOM uint32_t NHD : 1; /*!< [24..24] An interrupt indicating that no HD was input. */ + __IOM uint32_t NVD : 1; /*!< [25..25] An interrupt indicating that no VD was input. */ + uint32_t : 6; + } CETCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t CSTSR; /*!< (@ 0x0000007C) Capture Status Register */ + + struct + { + __IM uint32_t CPTON : 1; /*!< [0..0] Indicates that the CEU is operating. */ + uint32_t : 15; + __IM uint32_t CPFLD : 1; /*!< [16..16] Indicates which field is being captured. */ + uint32_t : 7; + __IM uint32_t CRST : 1; /*!< [24..24] Indicates which register plane is currently used. */ + uint32_t : 7; + } CSTSR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t CDSSR; /*!< (@ 0x00000084) Capture Data Size Register */ + + struct + { + __IM uint32_t CDSS : 32; /*!< [31..0] Indicate the size of data written to the memory in data + * enable fetch. */ + } CDSSR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CDAYR2; /*!< (@ 0x00000090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_b; + }; + + union + { + __IOM uint32_t CDACR2; /*!< (@ 0x00000094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_b; + }; + + union + { + __IOM uint32_t CDBYR2; /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_b; + }; + + union + { + __IOM uint32_t CDBCR2; /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_b; + }; + + union + { + __IOM uint32_t AXIBUSCTL2; /*!< (@ 0x000000A0) AXI Bus Control Register 2 */ + + struct + { + __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit */ + uint32_t : 28; + } AXIBUSCTL2_b; + }; + __IM uint32_t RESERVED6[987]; + + union + { + __IOM uint32_t CAMOR_B; /*!< (@ 0x00001010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_B_b; + }; + + union + { + __IOM uint32_t CAPWR_B; /*!< (@ 0x00001014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_B_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t CFLCR_B; /*!< (@ 0x00001030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_B_b; + }; + + union + { + __IOM uint32_t CFSZR_B; /*!< (@ 0x00001034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_B_b; + }; + + union + { + __IOM uint32_t CDWDR_B; /*!< (@ 0x00001038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_B_b; + }; + + union + { + __IOM uint32_t CDAYR_B; /*!< (@ 0x0000103C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_B_b; + }; + + union + { + __IOM uint32_t CDACR_B; /*!< (@ 0x00001040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_B_b; + }; + + union + { + __IOM uint32_t CDBYR_B; /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_B_b; + }; + + union + { + __IOM uint32_t CDBCR_B; /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_B_b; + }; + + union + { + __IOM uint32_t CBDSR_B; /*!< (@ 0x0000104C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_B_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint32_t CLFCR_B; /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_B_b; + }; + + union + { + __IOM uint32_t CDOCR_B; /*!< (@ 0x00001064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_B_b; + }; + __IM uint32_t RESERVED9[10]; + + union + { + __IOM uint32_t CDAYR2_B; /*!< (@ 0x00001090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_B_b; + }; + + union + { + __IOM uint32_t CDACR2_B; /*!< (@ 0x00001094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_B_b; + }; + + union + { + __IOM uint32_t CDBYR2_B; /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_B_b; + }; + + union + { + __IOM uint32_t CDBCR2_B; /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_B_b; + }; + __IM uint32_t RESERVED10[988]; + + union + { + __IOM uint32_t CAMOR_M; /*!< (@ 0x00002010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_M_b; + }; + + union + { + __IOM uint32_t CAPWR_M; /*!< (@ 0x00002014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_M_b; + }; + __IM uint32_t RESERVED11[6]; + + union + { + __IOM uint32_t CFLCR_M; /*!< (@ 0x00002030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_M_b; + }; + + union + { + __IOM uint32_t CFSZR_M; /*!< (@ 0x00002034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_M_b; + }; + + union + { + __IOM uint32_t CDWDR_M; /*!< (@ 0x00002038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_M_b; + }; + + union + { + __IOM uint32_t CDAYR_M; /*!< (@ 0x0000203C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_M_b; + }; + + union + { + __IOM uint32_t CDACR_M; /*!< (@ 0x00002040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_M_b; + }; + + union + { + __IOM uint32_t CDBYR_M; /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_M_b; + }; + + union + { + __IOM uint32_t CDBCR_M; /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_M_b; + }; + + union + { + __IOM uint32_t CBDSR_M; /*!< (@ 0x0000204C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_M_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CLFCR_M; /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_M_b; + }; + + union + { + __IOM uint32_t CDOCR_M; /*!< (@ 0x00002064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_M_b; + }; + __IM uint32_t RESERVED13[10]; + + union + { + __IOM uint32_t CDAYR2_M; /*!< (@ 0x00002090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_M_b; + }; + + union + { + __IOM uint32_t CDACR2_M; /*!< (@ 0x00002094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_M_b; + }; + + union + { + __IOM uint32_t CDBYR2_M; /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_M_b; + }; + + union + { + __IOM uint32_t CDBCR2_M; /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_M_b; + }; +} R_CEU_Type; /*!< Size = 8352 (0x20a0) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ultra-Low Power Timer 0 (R_ULPT0) + */ + +typedef struct /*!< (@ 0x40220000) R_ULPT0 Structure */ +{ + union + { + __IOM uint32_t ULPTCNT; /*!< (@ 0x00000000) ULPT Counter Register */ + + struct + { + __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, the 32-bit counter + * is forcibly stopped and set to FFFFFFFFH. */ + } ULPTCNT_b; + }; + + union + { + __IOM uint32_t ULPTCMA; /*!< (@ 0x00000004) ULPT Compare Match A Register */ + + struct + { + __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMA_b; + }; + + union + { + __IOM uint32_t ULPTCMB; /*!< (@ 0x00000008) ULPT Compare Match B Register */ + + struct + { + __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMB_b; + }; + + union + { + __IOM uint8_t ULPTCR; /*!< (@ 0x0000000C) ULPT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] ULPT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] ULPT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] ULPT count forced stop */ + uint8_t : 2; + __IOM uint8_t TUNDF : 1; /*!< [5..5] ULPT underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] ULPT compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] ULPT compare match B flag */ + } ULPTCR_b; + }; + + union + { + __IOM uint8_t ULPTMR1; /*!< (@ 0x0000000D) ULPT Mode Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t TMOD1 : 1; /*!< [1..1] ULPT operating mode select */ + uint8_t : 1; + __IOM uint8_t TEDGPL : 1; /*!< [3..3] ULPTEVI edge polarity select */ + uint8_t : 1; + __IOM uint8_t TCK1 : 1; /*!< [5..5] ULPT count source select */ + uint8_t : 2; + } ULPTMR1_b; + }; + + union + { + __IOM uint8_t ULPTMR2; /*!< (@ 0x0000000E) ULPT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] fsub/LOCO count source clock frequency division ratio + * select */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] ULPT Low Power Mode */ + } ULPTMR2_b; + }; + + union + { + __IOM uint8_t ULPTMR3; /*!< (@ 0x0000000F) ULPT Mode Register 3 */ + + struct + { + __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select */ + __IOM uint8_t TEVPOL : 1; /*!< [1..1] ULPTEVI polarity switch */ + __IOM uint8_t TOPOL : 1; /*!< [2..2] ULPTO polarity select */ + uint8_t : 1; + __IOM uint8_t TEECTL : 2; /*!< [5..4] ULPTEE function select */ + __IOM uint8_t TEEPOL : 2; /*!< [7..6] ULPTEE edge polarity select */ + } ULPTMR3_b; + }; + + union + { + __IOM uint8_t ULPTIOC; /*!< (@ 0x00000010) ULPT I/O Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t TOE : 1; /*!< [2..2] ULPTO output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] ULPTEVI input filter select */ + __IOM uint8_t TIOGT0 : 1; /*!< [6..6] ULPTEVI count control */ + uint8_t : 1; + } ULPTIOC_b; + }; + + union + { + __IOM uint8_t ULPTISR; /*!< (@ 0x00000011) ULPT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection */ + uint8_t : 5; + } ULPTISR_b; + }; + + union + { + __IOM uint8_t ULPTCMSR; /*!< (@ 0x00000012) ULPT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] ULPTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] ULPTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] ULPTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] ULPTOB polarity select */ + uint8_t : 1; + } ULPTCMSR_b; + }; + __IM uint8_t RESERVED; +} R_ULPT0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief On-Chip Debug Function (R_DEBUG_OCD) + */ + +typedef struct /*!< (@ 0x40011000) R_DEBUG_OCD Structure */ +{ + __IM uint32_t RESERVED[192]; + + union + { + __IM uint32_t FSBLSTATM; /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register */ + + struct + { + __IM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 30; + } FSBLSTATM_b; + }; +} R_DEBUG_OCD_Type; /*!< Size = 772 (0x304) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Decryption On The Fly (R_DOTF) + */ + +typedef struct /*!< (@ 0x40268800) R_DOTF Structure */ +{ + union + { + __IOM uint32_t CONVAREAST; /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area */ + } CONVAREAST_b; + }; + + union + { + __IOM uint32_t CONVAREAD; /*!< (@ 0x00000004) DOTF Conversion Area End Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area */ + } CONVAREAD_b; + }; + __IM uint32_t RESERVED[30]; + + union + { + __IOM uint32_t REG00; /*!< (@ 0x00000080) Register 0 */ + + struct + { + uint32_t : 9; + __IOM uint32_t B09 : 1; /*!< [9..9] Bit 09 */ + uint32_t : 6; + __IOM uint32_t B16 : 1; /*!< [16..16] Bit 09 */ + __IOM uint32_t B17 : 1; /*!< [17..17] Bit 17 */ + uint32_t : 2; + __IOM uint32_t B20 : 1; /*!< [20..20] Bit 20 */ + uint32_t : 3; + __IOM uint32_t B24 : 2; /*!< [25..24] Bit24-25 */ + uint32_t : 2; + __IOM uint32_t B28 : 2; /*!< [29..28] Bit28-29 */ + uint32_t : 2; + } REG00_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t REG03; /*!< (@ 0x0000008C) Register 03 */ + + struct + { + __IOM uint32_t B00 : 32; /*!< [31..0] Bit 0 */ + } REG03_b; + }; +} R_DOTF_Type; /*!< Size = 144 (0x90) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash (R_FLAD) + */ + +typedef struct /*!< (@ 0x4011C000) R_FLAD Structure */ +{ + __IM uint8_t RESERVED[64]; + + union + { + __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */ + + struct + { + __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */ + } FCKMHZ_b; + }; +} R_FLAD_Type; /*!< Size = 65 (0x41) */ + +/* =========================================================================================================================== */ +/* ================ R_OFS_DATAFLASH ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Flash Option-Setting Memory (R_OFS_DATAFLASH) + */ + +typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Structure */ +{ + __IM uint32_t RESERVED[32]; + + union + { + __IM uint32_t FSBLCTRL0; /*!< (@ 0x00000080) FSBL Control Register 0 */ + + struct + { + __IM uint32_t FSBLEN : 3; /*!< [2..0] FSBL Enable */ + __IM uint32_t FSBLSKIPSW : 3; /*!< [5..3] FSBL Skip Enable for Software Reset */ + __IM uint32_t FSBLSKIPDS : 3; /*!< [8..6] FSBL Skip Enable for Deep Software Standby Reset */ + __IM uint32_t FSBLCLK : 3; /*!< [11..9] Clock Frequency Selection during FSBL Execution */ + uint32_t : 20; + } FSBLCTRL0_b; + }; + + union + { + __IM uint32_t FSBLCTRL1; /*!< (@ 0x00000084) FSBL Control Register 1 */ + + struct + { + __IM uint32_t FSBLEXMD : 2; /*!< [1..0] FSBL Execution Mode */ + uint32_t : 30; + } FSBLCTRL1_b; + }; + + union + { + __IM uint32_t FSBLCTRL2; /*!< (@ 0x00000088) FSBL Control Register 2 */ + + struct + { + __IM uint32_t PORTPN : 4; /*!< [3..0] FSBL Error Notification Port Pin Number */ + __IM uint32_t PORTGN : 5; /*!< [8..4] FSBL Error Notification Port Group Name */ + uint32_t : 23; + } FSBLCTRL2_b; + }; + __IOM uint32_t SACC0; /*!< (@ 0x0000008C) Start Address of Code Certification 0 */ + __IOM uint32_t SACC1; /*!< (@ 0x00000090) Start Address of Code Certification 1 */ + __IOM uint32_t SAMR; /*!< (@ 0x00000094) Start Address of Measurement Report */ + __IM uint32_t RESERVED1[178]; + __IM uint32_t HOEMRTPK; /*!< (@ 0x00000360) Hask of OEM_ROOT_PK */ + __IM uint32_t RESERVED2[7]; + __IOM R_OFS_DATAFLASH_CFGDLOCK_Type CFGDLOCK; /*!< (@ 0x00000380) Configuration Data Lock Bits */ + __IM uint32_t RESERVED3[11]; + + union + { + __IOM uint16_t ARCLS; /*!< (@ 0x000003C0) Anti-Rollback Counter Lock Setting */ + + struct + { + __IOM uint16_t ARCS_LK : 1; /*!< [0..0] ARC_SEC Lock */ + __IOM uint16_t ARCNS_LK : 4; /*!< [4..1] ARC_NSEC Lock */ + __IOM uint16_t ARCBL_LK : 1; /*!< [5..5] ARC_OEMBL Lock */ + uint16_t : 10; + } ARCLS_b; + }; + + union + { + __IOM uint16_t ARCCS; /*!< (@ 0x000003C2) ARCCS */ + + struct + { + __IOM uint16_t CNF_ARCNS : 2; /*!< [1..0] Configuation setting for ARC_NSEC */ + uint16_t : 14; + } ARCCS_b; + }; + __IM uint32_t RESERVED4[291]; + + union + { + __IOM uint32_t ARC_SEC[2]; /*!< (@ 0x00000850) Anti-Rollback Counter for Secure Application + * n */ + + struct + { + __IOM uint32_t ARC_SEC : 32; /*!< [31..0] ARC_SEC */ + } ARC_SEC_b[2]; + }; + + union + { + __IOM uint32_t ARC_NSEC[8]; /*!< (@ 0x00000858) Anti-Rollback Counter for Non-Secure Application */ + + struct + { + __IOM uint32_t ARC_NSEC : 32; /*!< [31..0] Anti-Rollback Counter for Non-secure Application */ + } ARC_NSEC_b[8]; + }; + + union + { + __IOM uint32_t ARC_OEMBL[2]; /*!< (@ 0x00000878) Anti-Rollback Counter for OEMBL */ + + struct + { + __IOM uint32_t ARC_OEMBL : 32; /*!< [31..0] Anti-Rollback Counter for OEM_BL Application */ + } ARC_OEMBL_b[2]; + }; +} R_OFS_DATAFLASH_Type; /*!< Size = 2176 (0x880) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #if defined(_RA_TZ_NONSECURE) + #define BASE_NS_OFFSET (BSP_FEATURE_TZ_NS_OFFSET) + #else + #define BASE_NS_OFFSET 0U + #endif + + #define R_ACMPHS0_BASE (0x40236000UL + BASE_NS_OFFSET) + #define R_ACMPHS1_BASE (0x40236100UL + BASE_NS_OFFSET) + #define R_ACMPHS2_BASE (0x40236200UL + BASE_NS_OFFSET) + #define R_ACMPHS3_BASE (0x40236300UL + BASE_NS_OFFSET) + #define R_ACMPHS4_BASE (0x40236400UL + BASE_NS_OFFSET) + #define R_ACMPHS5_BASE (0x40236500UL + BASE_NS_OFFSET) + #define R_ADC0_BASE (0x40332000UL + BASE_NS_OFFSET) + #define R_ADC1_BASE (0x40332200UL + BASE_NS_OFFSET) + #define R_PSCU_BASE (0x40204000UL + BASE_NS_OFFSET) + #define R_BUS_BASE (0x40003000UL + BASE_NS_OFFSET) + #define R_CAC_BASE (0x40202400UL + BASE_NS_OFFSET) + #define R_CANFD_BASE (0x40380000UL + BASE_NS_OFFSET) + #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) + #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) + #define R_DAC_BASE (0x40333000UL + BASE_NS_OFFSET) + #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) + #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) + #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) + #define R_DMAC1_BASE (0x4000A040UL + BASE_NS_OFFSET) + #define R_DMAC2_BASE (0x4000A080UL + BASE_NS_OFFSET) + #define R_DMAC3_BASE (0x4000A0C0UL + BASE_NS_OFFSET) + #define R_DMAC4_BASE (0x4000A100UL + BASE_NS_OFFSET) + #define R_DMAC5_BASE (0x4000A140UL + BASE_NS_OFFSET) + #define R_DMAC6_BASE (0x4000A180UL + BASE_NS_OFFSET) + #define R_DMAC7_BASE (0x4000A1C0UL + BASE_NS_OFFSET) + #define R_DOC_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_DTC_BASE (0x4000AC00UL + BASE_NS_OFFSET) + #define R_ELC_BASE (0x40201000UL + BASE_NS_OFFSET) + #define R_ETHERC0_BASE (0x40354100UL + BASE_NS_OFFSET) + #define R_ETHERC_EDMAC_BASE (0x40354000UL + BASE_NS_OFFSET) + #define R_FACI_HP_CMD_BASE (0x40100000UL + BASE_NS_OFFSET) + #define R_FACI_HP_BASE (0x4011E000UL + BASE_NS_OFFSET) + #define R_FCACHE_BASE (0x4001C100UL + BASE_NS_OFFSET) + #define R_GPT0_BASE (0x40322000UL + BASE_NS_OFFSET) + #define R_GPT1_BASE (0x40322100UL + BASE_NS_OFFSET) + #define R_GPT2_BASE (0x40322200UL + BASE_NS_OFFSET) + #define R_GPT3_BASE (0x40322300UL + BASE_NS_OFFSET) + #define R_GPT4_BASE (0x40322400UL + BASE_NS_OFFSET) + #define R_GPT5_BASE (0x40322500UL + BASE_NS_OFFSET) + #define R_GPT6_BASE (0x40322600UL + BASE_NS_OFFSET) + #define R_GPT7_BASE (0x40322700UL + BASE_NS_OFFSET) + #define R_GPT8_BASE (0x40322800UL + BASE_NS_OFFSET) + #define R_GPT9_BASE (0x40322900UL + BASE_NS_OFFSET) + #define R_GPT10_BASE (0x40322A00UL + BASE_NS_OFFSET) + #define R_GPT11_BASE (0x40322B00UL + BASE_NS_OFFSET) + #define R_GPT12_BASE (0x40322C00UL + BASE_NS_OFFSET) + #define R_GPT13_BASE (0x40322D00UL + BASE_NS_OFFSET) + #define R_GPT_POEG0_BASE (0x40212000UL + BASE_NS_OFFSET) + #define R_GPT_POEG1_BASE (0x40212100UL + BASE_NS_OFFSET) + #define R_GPT_POEG2_BASE (0x40212200UL + BASE_NS_OFFSET) + #define R_GPT_POEG3_BASE (0x40212300UL + BASE_NS_OFFSET) + #define R_ICU_BASE (0x40006000UL + BASE_NS_OFFSET) + #define R_IIC0_BASE (0x4025E000UL + BASE_NS_OFFSET) + #define R_IIC1_BASE (0x4025E100UL + BASE_NS_OFFSET) + #define R_IIC2_BASE (0x4025E200UL + BASE_NS_OFFSET) + #define R_IWDT_BASE (0x40202200UL + BASE_NS_OFFSET) + #define R_MPU_MMPU_BASE (0x40000000UL + BASE_NS_OFFSET) + #define R_MPU_SPMON_BASE (0x40000D00UL + BASE_NS_OFFSET) + #define R_MSTP_BASE (0x40203000UL + BASE_NS_OFFSET) + #define R_PORT0_BASE (0x40400000UL + BASE_NS_OFFSET) + #define R_PORT1_BASE (0x40400020UL + BASE_NS_OFFSET) + #define R_PORT2_BASE (0x40400040UL + BASE_NS_OFFSET) + #define R_PORT3_BASE (0x40400060UL + BASE_NS_OFFSET) + #define R_PORT4_BASE (0x40400080UL + BASE_NS_OFFSET) + #define R_PORT5_BASE (0x404000A0UL + BASE_NS_OFFSET) + #define R_PORT6_BASE (0x404000C0UL + BASE_NS_OFFSET) + #define R_PORT7_BASE (0x404000E0UL + BASE_NS_OFFSET) + #define R_PORT8_BASE (0x40400100UL + BASE_NS_OFFSET) + #define R_PORT9_BASE (0x40400120UL + BASE_NS_OFFSET) + #define R_PORT10_BASE (0x40400140UL + BASE_NS_OFFSET) + #define R_PORT11_BASE (0x40400160UL + BASE_NS_OFFSET) + #define R_PORT12_BASE (0x40400180UL + BASE_NS_OFFSET) + #define R_PORT13_BASE (0x404001A0UL + BASE_NS_OFFSET) + #define R_PORT14_BASE (0x404001C0UL + BASE_NS_OFFSET) + #define R_PFS_BASE (0x40400800UL + BASE_NS_OFFSET) + #define R_PMISC_BASE (0x40400D00UL + BASE_NS_OFFSET) + #define R_RTC_BASE (0x40202000UL + BASE_NS_OFFSET) + #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_SCI9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SPI0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_SPI2_BASE (0x40072200UL + BASE_NS_OFFSET) + #define R_SRAM_BASE (0x40002000UL + BASE_NS_OFFSET) + #define R_SSI0_BASE (0x4025D000UL + BASE_NS_OFFSET) + #define R_SSI1_BASE (0x4025D100UL + BASE_NS_OFFSET) + #define R_SYSTEM_BASE (0x4001E000UL + BASE_NS_OFFSET) + #define R_TSN_CAL_BASE (0x4011B17CUL + BASE_NS_OFFSET) + #define R_TSN_CTRL_BASE (0x40235000UL + BASE_NS_OFFSET) + #define R_USB_FS0_BASE (0x40250000UL + BASE_NS_OFFSET) + #define R_WDT_BASE (0x40202600UL + BASE_NS_OFFSET) + #define R_CPSCU_BASE (0x40008000UL + BASE_NS_OFFSET) + #define R_DOC_B_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_SCI_B0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI_B1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI_B2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI_B3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI_B4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI_B9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SPI_B0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI_B1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_XSPI0_BASE (0x40268000UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) + #define R_CEU_BASE (0x40348000UL + BASE_NS_OFFSET) + #define R_ULPT0_BASE (0x40220000UL + BASE_NS_OFFSET) + #define R_ULPT1_BASE (0x40220100UL + BASE_NS_OFFSET) + #define R_DEBUG_OCD_BASE (0x40011000UL + BASE_NS_OFFSET) + #define R_DOTF_BASE (0x40268800UL + BASE_NS_OFFSET) + #define R_AGTX0_BASE (0x40221000UL + BASE_NS_OFFSET) + #define R_AGTX1_BASE (0x40221100UL + BASE_NS_OFFSET) + #define R_AGTX2_BASE (0x40221200UL + BASE_NS_OFFSET) + #define R_AGTX3_BASE (0x40221300UL + BASE_NS_OFFSET) + #define R_AGTX4_BASE (0x40221400UL + BASE_NS_OFFSET) + #define R_AGTX5_BASE (0x40221500UL + BASE_NS_OFFSET) + #define R_AGTX6_BASE (0x40221600UL + BASE_NS_OFFSET) + #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) + #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) + #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_DOTF1_BASE (0x40268900UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) + #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET) + #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40044300UL + BASE_NS_OFFSET) + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE) + #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE) + #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE) + #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE) + #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE) + #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE) + #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE) + #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) + #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_CEU ((R_CEU_Type *) R_CEU_BASE) + #define R_ULPT0 ((R_ULPT0_Type *) R_ULPT0_BASE) + #define R_ULPT1 ((R_ULPT0_Type *) R_ULPT1_BASE) + #define R_DEBUG_OCD ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE) + #define R_DOTF ((R_DOTF_Type *) R_DOTF_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_DOTF1 ((R_DOTF_Type *) R_DOTF1_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) + #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= EOBI ========================================================== */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CMCFGCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Pos (4UL) /*!< WPBSTMD (Bit 4) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Msk (0x10UL) /*!< WPBSTMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Pos (5UL) /*!< ARYAMD (Bit 5) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Msk (0x20UL) /*!< ARYAMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ CDBUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CDBUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_CDBUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDBUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_CDBUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_CDBUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_CDBUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_CDBUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_CDBUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CCCTLCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFGD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFGD_L ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ +/* ======================================================== CFGD_H ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CFGDLOCK ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CFGD2 ========================================================= */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */ + #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARB ========================================================= */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARC ========================================================= */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARD ========================================================= */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARE ========================================================= */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSPAR ========================================================= */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR30_Pos (30UL) /*!< ELSR30 (Bit 30) */ + #define R_ELC_ELCSARB_ELSR30_Msk (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARA ======================================================== */ + #define R_ELC_ELCPARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCPARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCPARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCPARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARB ======================================================== */ + #define R_ELC_ELCPARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARB_ELSR30_Pos (30UL) /*!< ELSR30 (Bit 30) */ + #define R_ELC_ELCPARB_ELSR30_Msk (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FBCADDR ======================================================== */ + #define R_FACI_HP_FBCADDR_BCADR_Pos (0UL) /*!< BCADR (Bit 0) */ + #define R_FACI_HP_FBCADDR_BCADR_Msk (0xffffffUL) /*!< BCADR (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ +/* ======================================================= FCNTSELR ======================================================== */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_FACI_HP_FCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ====================================================== FCNTDATAR0 ======================================================= */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FCNTDATAR1 ======================================================= */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCACHEENSA_Pos (1UL) /*!< FCACHEENSA (Bit 1) */ + #define R_FCACHE_FSAR_FCACHEENSA_Msk (0x2UL) /*!< FCACHEENSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */ + #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */ + #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FACITRSA_Pos (11UL) /*!< FACITRSA (Bit 11) */ + #define R_FCACHE_FSAR_FACITRSA_Msk (0x800UL) /*!< FACITRSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SWIRQ_S ======================================================== */ + #define R_ICU_SWIRQ_S_SWIRQS_Pos (0UL) /*!< SWIRQS (Bit 0) */ + #define R_ICU_SWIRQ_S_SWIRQS_Msk (0x1UL) /*!< SWIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= SWIRQ_NS ======================================================== */ + #define R_ICU_SWIRQ_NS_SWIRQNS_Pos (0UL) /*!< SWIRQNS (Bit 0) */ + #define R_ICU_SWIRQ_NS_SWIRQNS_Msk (0x1UL) /*!< SWIRQNS (Bitfield-Mask: 0x01) */ +/* ======================================================== IENMIER ======================================================== */ + #define R_ICU_IENMIER_CMEN_Pos (0UL) /*!< CMEN (Bit 0) */ + #define R_ICU_IENMIER_CMEN_Msk (0x1UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IENMIER_LMEN_Pos (1UL) /*!< LMEN (Bit 1) */ + #define R_ICU_IENMIER_LMEN_Msk (0x2UL) /*!< LMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IENMIER_BUSEN_Pos (2UL) /*!< BUSEN (Bit 2) */ + #define R_ICU_IENMIER_BUSEN_Msk (0x4UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSEN_Pos (12UL) /*!< BUSEN (Bit 12) */ + #define R_ICU_NMIER_BUSEN_Msk (0x1000UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CMEN_Pos (13UL) /*!< CMEN (Bit 13) */ + #define R_ICU_NMIER_CMEN_Msk (0x2000UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LUEN_Pos (15UL) /*!< LUEN (Bit 15) */ + #define R_ICU_NMIER_LUEN_Msk (0x8000UL) /*!< LUEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSCLR_Pos (12UL) /*!< BUSCLR (Bit 12) */ + #define R_ICU_NMICLR_BUSCLR_Msk (0x1000UL) /*!< BUSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CMCLR_Pos (13UL) /*!< CMCLR (Bit 13) */ + #define R_ICU_NMICLR_CMCLR_Msk (0x2000UL) /*!< CMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LUCLR_Pos (15UL) /*!< LUCLR (Bit 15) */ + #define R_ICU_NMICLR_LUCLR_Msk (0x8000UL) /*!< LUCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_ICU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_ICU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_ICU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IRQWUPEN0_Pos (0UL) /*!< IRQWUPEN0 (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN0_Msk (0x1UL) /*!< IRQWUPEN0 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN1_Pos (1UL) /*!< IRQWUPEN1 (Bit 1) */ + #define R_ICU_WUPEN_IRQWUPEN1_Msk (0x2UL) /*!< IRQWUPEN1 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN2_Pos (2UL) /*!< IRQWUPEN2 (Bit 2) */ + #define R_ICU_WUPEN_IRQWUPEN2_Msk (0x4UL) /*!< IRQWUPEN2 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN3_Pos (3UL) /*!< IRQWUPEN3 (Bit 3) */ + #define R_ICU_WUPEN_IRQWUPEN3_Msk (0x8UL) /*!< IRQWUPEN3 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN4_Pos (4UL) /*!< IRQWUPEN4 (Bit 4) */ + #define R_ICU_WUPEN_IRQWUPEN4_Msk (0x10UL) /*!< IRQWUPEN4 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN5_Pos (5UL) /*!< IRQWUPEN5 (Bit 5) */ + #define R_ICU_WUPEN_IRQWUPEN5_Msk (0x20UL) /*!< IRQWUPEN5 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN6_Pos (6UL) /*!< IRQWUPEN6 (Bit 6) */ + #define R_ICU_WUPEN_IRQWUPEN6_Msk (0x40UL) /*!< IRQWUPEN6 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN7_Pos (7UL) /*!< IRQWUPEN7 (Bit 7) */ + #define R_ICU_WUPEN_IRQWUPEN7_Msk (0x80UL) /*!< IRQWUPEN7 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN8_Pos (8UL) /*!< IRQWUPEN8 (Bit 8) */ + #define R_ICU_WUPEN_IRQWUPEN8_Msk (0x100UL) /*!< IRQWUPEN8 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN9_Pos (9UL) /*!< IRQWUPEN9 (Bit 9) */ + #define R_ICU_WUPEN_IRQWUPEN9_Msk (0x200UL) /*!< IRQWUPEN9 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN10_Pos (10UL) /*!< IRQWUPEN10 (Bit 10) */ + #define R_ICU_WUPEN_IRQWUPEN10_Msk (0x400UL) /*!< IRQWUPEN10 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN11_Pos (11UL) /*!< IRQWUPEN11 (Bit 11) */ + #define R_ICU_WUPEN_IRQWUPEN11_Msk (0x800UL) /*!< IRQWUPEN11 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN12_Pos (12UL) /*!< IRQWUPEN12 (Bit 12) */ + #define R_ICU_WUPEN_IRQWUPEN12_Msk (0x1000UL) /*!< IRQWUPEN12 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN13_Pos (13UL) /*!< IRQWUPEN13 (Bit 13) */ + #define R_ICU_WUPEN_IRQWUPEN13_Msk (0x2000UL) /*!< IRQWUPEN13 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN14_Pos (14UL) /*!< IRQWUPEN14 (Bit 14) */ + #define R_ICU_WUPEN_IRQWUPEN14_Msk (0x4000UL) /*!< IRQWUPEN14 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN15_Pos (15UL) /*!< IRQWUPEN15 (Bit 15) */ + #define R_ICU_WUPEN_IRQWUPEN15_Msk (0x8000UL) /*!< IRQWUPEN15 (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RIIC0WUPEN_Pos (31UL) /*!< RIIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_RIIC0WUPEN_Msk (0x80000000UL) /*!< RIIC0WUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_COMPHS0WUPEN_Pos (3UL) /*!< COMPHS0WUPEN (Bit 3) */ + #define R_ICU_WUPEN1_COMPHS0WUPEN_Msk (0x8UL) /*!< COMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0UWUPEN_Pos (8UL) /*!< ULP0UWUPEN (Bit 8) */ + #define R_ICU_WUPEN1_ULP0UWUPEN_Msk (0x100UL) /*!< ULP0UWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0AWUPEN_Pos (9UL) /*!< ULP0AWUPEN (Bit 9) */ + #define R_ICU_WUPEN1_ULP0AWUPEN_Msk (0x200UL) /*!< ULP0AWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP0BWUPEN_Pos (10UL) /*!< ULP0BWUPEN (Bit 10) */ + #define R_ICU_WUPEN1_ULP0BWUPEN_Msk (0x400UL) /*!< ULP0BWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_I3CWUPEN_Pos (11UL) /*!< I3CWUPEN (Bit 11) */ + #define R_ICU_WUPEN1_I3CWUPEN_Msk (0x800UL) /*!< I3CWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1UWUPEN_Pos (12UL) /*!< ULP1UWUPEN (Bit 12) */ + #define R_ICU_WUPEN1_ULP1UWUPEN_Msk (0x1000UL) /*!< ULP1UWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1AWUPEN_Pos (13UL) /*!< ULP1AWUPEN (Bit 13) */ + #define R_ICU_WUPEN1_ULP1AWUPEN_Msk (0x2000UL) /*!< ULP1AWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_ULP1BWUPEN_Pos (14UL) /*!< ULP1BWUPEN (Bit 14) */ + #define R_ICU_WUPEN1_ULP1BWUPEN_Msk (0x4000UL) /*!< ULP1BWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMPRCR_NS ====================================================== */ + #define R_SRAM_SRAMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================= SRAMWTSC ======================================================== */ + #define R_SRAM_SRAMWTSC_WTEN_Pos (0UL) /*!< WTEN (Bit 0) */ + #define R_SRAM_SRAMWTSC_WTEN_Msk (0x1UL) /*!< WTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR0 ======================================================== */ + #define R_SRAM_SRAMCR0_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR0_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR0_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR0_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR0_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR0_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR1 ======================================================== */ + #define R_SRAM_SRAMCR1_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR1_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMECCRGN0 ====================================================== */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk (0x3UL) /*!< ECCRGN (Bitfield-Mask: 0x03) */ +/* ======================================================== SRAMESR ======================================================== */ + #define R_SRAM_SRAMESR_ERR00_Pos (0UL) /*!< ERR00 (Bit 0) */ + #define R_SRAM_SRAMESR_ERR00_Msk (0x1UL) /*!< ERR00 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR01_Pos (1UL) /*!< ERR01 (Bit 1) */ + #define R_SRAM_SRAMESR_ERR01_Msk (0x2UL) /*!< ERR01 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR1_Pos (2UL) /*!< ERR1 (Bit 2) */ + #define R_SRAM_SRAMESR_ERR1_Msk (0x4UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERRS_Pos (14UL) /*!< ERRS (Bit 14) */ + #define R_SRAM_SRAMESR_ERRS_Msk (0x4000UL) /*!< ERRS (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMESCLR ======================================================= */ + #define R_SRAM_SRAMESCLR_CLR00_Pos (0UL) /*!< CLR00 (Bit 0) */ + #define R_SRAM_SRAMESCLR_CLR00_Msk (0x1UL) /*!< CLR00 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR01_Pos (1UL) /*!< CLR01 (Bit 1) */ + #define R_SRAM_SRAMESCLR_CLR01_Msk (0x2UL) /*!< CLR01 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR1_Pos (2UL) /*!< CLR1 (Bit 2) */ + #define R_SRAM_SRAMESCLR_CLR1_Msk (0x4UL) /*!< CLR1 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLRS_Pos (14UL) /*!< CLRS (Bit 14) */ + #define R_SRAM_SRAMESCLR_CLRS_Msk (0x4000UL) /*!< CLRS (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMEAR0 ======================================================== */ + #define R_SRAM_SRAMEAR0_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR0_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= SRAMEAR1 ======================================================== */ + #define R_SRAM_SRAMEAR1_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR1_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= SRAMEAR2 ======================================================== */ + #define R_SRAM_SRAMEAR2_EA_Pos (3UL) /*!< EA (Bit 3) */ + #define R_SRAM_SRAMEAR2_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= STBRAMCR ======================================================== */ + #define R_SRAM_STBRAMCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_STBRAMCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMEAR ======================================================= */ + #define R_SRAM_STBRAMEAR_EA_Pos (2UL) /*!< EA (Bit 2) */ + #define R_SRAM_STBRAMEAR_EA_Msk (0x3fcUL) /*!< EA (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_OPE_Pos (6UL) /*!< OPE (Bit 6) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x40UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ========================================================= SSCR2 ========================================================= */ + #define R_SYSTEM_SSCR2_SS1RSF_Pos (0UL) /*!< SS1RSF (Bit 0) */ + #define R_SYSTEM_SSCR2_SS1RSF_Msk (0x1UL) /*!< SS1RSF (Bitfield-Mask: 0x01) */ +/* ========================================================= FLSCR ========================================================= */ + #define R_SYSTEM_FLSCR_FLSWCF_Pos (0UL) /*!< FLSWCF (Bit 0) */ + #define R_SYSTEM_FLSCR_FLSWCF_Msk (0x1UL) /*!< FLSWCF (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0xf000000UL) /*!< ICK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Pos (20UL) /*!< PCKE (Bit 20) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Msk (0xf00000UL) /*!< PCKE (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0xf0000UL) /*!< BCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0xf000UL) /*!< PCKA (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0xf00UL) /*!< PCKB (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0xf0UL) /*!< PCKC (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0xfUL) /*!< PCKD (Bitfield-Mask: 0x0f) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Pos (6UL) /*!< PLLMULNF (Bit 6) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Msk (0xc0UL) /*!< PLLMULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0xff00UL) /*!< PLLMUL (Bitfield-Mask: 0xff) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Pos (4UL) /*!< TRCKSEL (Bit 4) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Msk (0x10UL) /*!< TRCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== OSCMONR ======================================================== */ + #define R_SYSTEM_OSCMONR_MOCOMON_Pos (1UL) /*!< MOCOMON (Bit 1) */ + #define R_SYSTEM_OSCMONR_MOCOMON_Msk (0x2UL) /*!< MOCOMON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Pos (2UL) /*!< LOCOMON (Bit 2) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Msk (0x4UL) /*!< LOCOMON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos (6UL) /*!< PLL2MULNF (Bit 6) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk (0xc0UL) /*!< PLL2MULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0xff00UL) /*!< PLL2MUL (Bitfield-Mask: 0xff) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Pos (0UL) /*!< PLODIVP (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Msk (0xfUL) /*!< PLODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos (4UL) /*!< PLODIVQ (Bit 4) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk (0xf0UL) /*!< PLODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Pos (8UL) /*!< PLODIVR (Bit 8) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Msk (0xf00UL) /*!< PLODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PLL2CCR2 ======================================================== */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos (0UL) /*!< PL2ODIVP (Bit 0) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk (0xfUL) /*!< PL2ODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos (4UL) /*!< PL2ODIVQ (Bit 4) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk (0xf0UL) /*!< PL2ODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos (8UL) /*!< PL2ODIVR (Bit 8) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk (0xf00UL) /*!< PL2ODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCICKDIVCR ======================================================= */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== SCICKCR ======================================================== */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Pos (0UL) /*!< SCICKSEL (Bit 0) */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Msk (0xfUL) /*!< SCICKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SPICKDIVCR ======================================================= */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== SPICKCR ======================================================== */ + #define R_SYSTEM_SPICKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SPICKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCCKDIVCR ======================================================= */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== ADCCKCR ======================================================== */ + #define R_SYSTEM_ADCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ADCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_GPTCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== LCDCKDIVCR ======================================================= */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== LCDCKCR ======================================================== */ + #define R_SYSTEM_LCDCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_LCDCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0xfUL) /*!< USBCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0xfUL) /*!< OCTACKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0xfUL) /*!< CANFDCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0xfUL) /*!< I3CCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_I3CCKCR_I3CCKREQ_Pos (6UL) /*!< I3CCKREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKREQ_Msk (0x40UL) /*!< I3CCKREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCSCR ======================================================== */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos (0UL) /*!< MOSCSOKP (Bit 0) */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk (0x1UL) /*!< MOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOSCR ======================================================== */ + #define R_SYSTEM_HOCOSCR_HOCOSOKP_Pos (0UL) /*!< HOCOSOKP (Bit 0) */ + #define R_SYSTEM_HOCOSCR_HOCOSOKP_Msk (0x1UL) /*!< HOCOSOKP (Bitfield-Mask: 0x01) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLU0RF_Pos (4UL) /*!< CLU0RF (Bit 4) */ + #define R_SYSTEM_RSTSR1_CLU0RF_Msk (0x10UL) /*!< CLU0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM0RF_Pos (5UL) /*!< LM0RF (Bit 5) */ + #define R_SYSTEM_RSTSR1_LM0RF_Msk (0x20UL) /*!< LM0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSRF_Pos (10UL) /*!< BUSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSRF_Msk (0x400UL) /*!< BUSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CMRF_Pos (14UL) /*!< CMRF (Bit 14) */ + #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ + #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ + #define R_SYSTEM_RSTSR1_NWRF_Msk (0x400000UL) /*!< NWRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRACCR ======================================================== */ + #define R_SYSTEM_SYRACCR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SYSTEM_SYRACCR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================= CRVSYSCR ======================================================== */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Pos (0UL) /*!< CRVEN (Bit 0) */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Msk (0x1UL) /*!< CRVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCTRGD ======================================================== */ + #define R_SYSTEM_PDCTRGD_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRGD_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR0 ======================================================= */ +/* ======================================================= PDRAMSCR1 ======================================================= */ +/* ======================================================= VBRSABAR ======================================================== */ + #define R_SYSTEM_VBRSABAR_SABA_Pos (0UL) /*!< SABA (Bit 0) */ + #define R_SYSTEM_VBRSABAR_SABA_Msk (0xffffUL) /*!< SABA (Bitfield-Mask: 0xffff) */ +/* ======================================================= VBRPABARS ======================================================= */ + #define R_SYSTEM_VBRPABARS_PABAS_Pos (0UL) /*!< PABAS (Bit 0) */ + #define R_SYSTEM_VBRPABARS_PABAS_Msk (0xffffUL) /*!< PABAS (Bitfield-Mask: 0xffff) */ +/* ====================================================== VBRPABARNS ======================================================= */ + #define R_SYSTEM_VBRPABARNS_PABANS_Pos (0UL) /*!< PABANS (Bit 0) */ + #define R_SYSTEM_VBRPABARNS_PABANS_Msk (0xffffUL) /*!< PABANS (Bitfield-Mask: 0xffff) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC13_Pos (13UL) /*!< NONSEC13 (Bit 13) */ + #define R_SYSTEM_CGFSAR_NONSEC13_Msk (0x2000UL) /*!< NONSEC13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_CGFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_CGFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_CGFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_CGFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_CGFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC24_Pos (24UL) /*!< NONSEC24 (Bit 24) */ + #define R_SYSTEM_CGFSAR_NONSEC24_Msk (0x1000000UL) /*!< NONSEC24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC25_Pos (25UL) /*!< NONSEC25 (Bit 25) */ + #define R_SYSTEM_CGFSAR_NONSEC25_Msk (0x2000000UL) /*!< NONSEC25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC26_Pos (26UL) /*!< NONSEC26 (Bit 26) */ + #define R_SYSTEM_CGFSAR_NONSEC26_Msk (0x4000000UL) /*!< NONSEC26 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_RSTSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LPMSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_LPMSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_LPMSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_LPMSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_LPMSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_LPMSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_LPMSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== PGCSAR ========================================================= */ + #define R_SYSTEM_PGCSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_PGCSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PGCSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_PGCSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA25_Pos (25UL) /*!< DPFSA25 (Bit 25) */ + #define R_SYSTEM_DPFSAR_DPFSA25_Msk (0x2000000UL) /*!< DPFSA25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA29_Pos (29UL) /*!< DPFSA29 (Bit 29) */ + #define R_SYSTEM_DPFSAR_DPFSA29_Msk (0x20000000UL) /*!< DPFSA29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA31_Pos (31UL) /*!< DPFSA31 (Bit 31) */ + #define R_SYSTEM_DPFSAR_DPFSA31_Msk (0x80000000UL) /*!< DPFSA31 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSCSAR ========================================================= */ + #define R_SYSTEM_RSCSAR_RSCSA0_Pos (0UL) /*!< RSCSA0 (Bit 0) */ + #define R_SYSTEM_RSCSAR_RSCSA0_Msk (0x1UL) /*!< RSCSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA1_Pos (1UL) /*!< RSCSA1 (Bit 1) */ + #define R_SYSTEM_RSCSAR_RSCSA1_Msk (0x2UL) /*!< RSCSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA2_Pos (2UL) /*!< RSCSA2 (Bit 2) */ + #define R_SYSTEM_RSCSAR_RSCSA2_Msk (0x4UL) /*!< RSCSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA3_Pos (3UL) /*!< RSCSA3 (Bit 3) */ + #define R_SYSTEM_RSCSAR_RSCSA3_Msk (0x8UL) /*!< RSCSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA4_Pos (4UL) /*!< RSCSA4 (Bit 4) */ + #define R_SYSTEM_RSCSAR_RSCSA4_Msk (0x10UL) /*!< RSCSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA5_Pos (5UL) /*!< RSCSA5 (Bit 5) */ + #define R_SYSTEM_RSCSAR_RSCSA5_Msk (0x20UL) /*!< RSCSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA6_Pos (6UL) /*!< RSCSA6 (Bit 6) */ + #define R_SYSTEM_RSCSAR_RSCSA6_Msk (0x40UL) /*!< RSCSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA7_Pos (7UL) /*!< RSCSA7 (Bit 7) */ + #define R_SYSTEM_RSCSAR_RSCSA7_Msk (0x80UL) /*!< RSCSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA8_Pos (8UL) /*!< RSCSA8 (Bit 8) */ + #define R_SYSTEM_RSCSAR_RSCSA8_Msk (0x100UL) /*!< RSCSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA9_Pos (9UL) /*!< RSCSA9 (Bit 9) */ + #define R_SYSTEM_RSCSAR_RSCSA9_Msk (0x200UL) /*!< RSCSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA10_Pos (10UL) /*!< RSCSA10 (Bit 10) */ + #define R_SYSTEM_RSCSAR_RSCSA10_Msk (0x400UL) /*!< RSCSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA11_Pos (11UL) /*!< RSCSA11 (Bit 11) */ + #define R_SYSTEM_RSCSAR_RSCSA11_Msk (0x800UL) /*!< RSCSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA12_Pos (12UL) /*!< RSCSA12 (Bit 12) */ + #define R_SYSTEM_RSCSAR_RSCSA12_Msk (0x1000UL) /*!< RSCSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA13_Pos (13UL) /*!< RSCSA13 (Bit 13) */ + #define R_SYSTEM_RSCSAR_RSCSA13_Msk (0x2000UL) /*!< RSCSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA14_Pos (14UL) /*!< RSCSA14 (Bit 14) */ + #define R_SYSTEM_RSCSAR_RSCSA14_Msk (0x4000UL) /*!< RSCSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA16_Pos (16UL) /*!< RSCSA16 (Bit 16) */ + #define R_SYSTEM_RSCSAR_RSCSA16_Msk (0x10000UL) /*!< RSCSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSCSAR_RSCSA17_Pos (17UL) /*!< RSCSA17 (Bit 17) */ + #define R_SYSTEM_RSCSAR_RSCSA17_Msk (0x20000UL) /*!< RSCSA17 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC5_Pos (5UL) /*!< PRC5 (Bit 5) */ + #define R_SYSTEM_PRCR_PRC5_Msk (0x20UL) /*!< PRC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== PRCR_NS ======================================================== */ + #define R_SYSTEM_PRCR_NS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_NS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_NS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_NS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_NS_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos (2UL) /*!< DCSSMODE (Bit 2) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk (0x4UL) /*!< DCSSMODE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_SRKEEP_Pos (4UL) /*!< SRKEEP (Bit 4) */ + #define R_SYSTEM_DPSBYCR_SRKEEP_Msk (0x10UL) /*!< SRKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0xffUL) /*!< WTSTS (Bitfield-Mask: 0xff) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQ0E_Pos (0UL) /*!< DIRQ0E (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQ0E_Msk (0x1UL) /*!< DIRQ0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ1E_Pos (1UL) /*!< DIRQ1E (Bit 1) */ + #define R_SYSTEM_DPSIER0_DIRQ1E_Msk (0x2UL) /*!< DIRQ1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ2E_Pos (2UL) /*!< DIRQ2E (Bit 2) */ + #define R_SYSTEM_DPSIER0_DIRQ2E_Msk (0x4UL) /*!< DIRQ2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ3E_Pos (3UL) /*!< DIRQ3E (Bit 3) */ + #define R_SYSTEM_DPSIER0_DIRQ3E_Msk (0x8UL) /*!< DIRQ3E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ4E_Pos (4UL) /*!< DIRQ4E (Bit 4) */ + #define R_SYSTEM_DPSIER0_DIRQ4E_Msk (0x10UL) /*!< DIRQ4E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ5E_Pos (5UL) /*!< DIRQ5E (Bit 5) */ + #define R_SYSTEM_DPSIER0_DIRQ5E_Msk (0x20UL) /*!< DIRQ5E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ6E_Pos (6UL) /*!< DIRQ6E (Bit 6) */ + #define R_SYSTEM_DPSIER0_DIRQ6E_Msk (0x40UL) /*!< DIRQ6E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER0_DIRQ7E_Pos (7UL) /*!< DIRQ7E (Bit 7) */ + #define R_SYSTEM_DPSIER0_DIRQ7E_Msk (0x80UL) /*!< DIRQ7E (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQ8E_Pos (0UL) /*!< DIRQ8E (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQ8E_Msk (0x1UL) /*!< DIRQ8E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ9E_Pos (1UL) /*!< DIRQ9E (Bit 1) */ + #define R_SYSTEM_DPSIER1_DIRQ9E_Msk (0x2UL) /*!< DIRQ9E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ10E_Pos (2UL) /*!< DIRQ10E (Bit 2) */ + #define R_SYSTEM_DPSIER1_DIRQ10E_Msk (0x4UL) /*!< DIRQ10E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ11E_Pos (3UL) /*!< DIRQ11E (Bit 3) */ + #define R_SYSTEM_DPSIER1_DIRQ11E_Msk (0x8UL) /*!< DIRQ11E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ12E_Pos (4UL) /*!< DIRQ12E (Bit 4) */ + #define R_SYSTEM_DPSIER1_DIRQ12E_Msk (0x10UL) /*!< DIRQ12E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ13E_Pos (5UL) /*!< DIRQ13E (Bit 5) */ + #define R_SYSTEM_DPSIER1_DIRQ13E_Msk (0x20UL) /*!< DIRQ13E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ14E_Pos (6UL) /*!< DIRQ14E (Bit 6) */ + #define R_SYSTEM_DPSIER1_DIRQ14E_Msk (0x40UL) /*!< DIRQ14E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER1_DIRQ15E_Pos (7UL) /*!< DIRQ15E (Bit 7) */ + #define R_SYSTEM_DPSIER1_DIRQ15E_Msk (0x80UL) /*!< DIRQ15E (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Pos (0UL) /*!< DPVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Msk (0x1UL) /*!< DPVD1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Pos (1UL) /*!< DPVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Msk (0x2UL) /*!< DPVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Pos (2UL) /*!< DULPT0IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Msk (0x4UL) /*!< DULPT0IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Pos (3UL) /*!< DULPT1IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Msk (0x8UL) /*!< DULPT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Pos (5UL) /*!< DIWDTIE (Bit 5) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Msk (0x20UL) /*!< DIWDTIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos (7UL) /*!< DVBATTADIE (Bit 7) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk (0x80UL) /*!< DVBATTADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQ0F_Pos (0UL) /*!< DIRQ0F (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQ0F_Msk (0x1UL) /*!< DIRQ0F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ1F_Pos (1UL) /*!< DIRQ1F (Bit 1) */ + #define R_SYSTEM_DPSIFR0_DIRQ1F_Msk (0x2UL) /*!< DIRQ1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ2F_Pos (2UL) /*!< DIRQ2F (Bit 2) */ + #define R_SYSTEM_DPSIFR0_DIRQ2F_Msk (0x4UL) /*!< DIRQ2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ3F_Pos (3UL) /*!< DIRQ3F (Bit 3) */ + #define R_SYSTEM_DPSIFR0_DIRQ3F_Msk (0x8UL) /*!< DIRQ3F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ4F_Pos (4UL) /*!< DIRQ4F (Bit 4) */ + #define R_SYSTEM_DPSIFR0_DIRQ4F_Msk (0x10UL) /*!< DIRQ4F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ5F_Pos (5UL) /*!< DIRQ5F (Bit 5) */ + #define R_SYSTEM_DPSIFR0_DIRQ5F_Msk (0x20UL) /*!< DIRQ5F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ6F_Pos (6UL) /*!< DIRQ6F (Bit 6) */ + #define R_SYSTEM_DPSIFR0_DIRQ6F_Msk (0x40UL) /*!< DIRQ6F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR0_DIRQ7F_Pos (7UL) /*!< DIRQ7F (Bit 7) */ + #define R_SYSTEM_DPSIFR0_DIRQ7F_Msk (0x80UL) /*!< DIRQ7F (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQ8F_Pos (0UL) /*!< DIRQ8F (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQ8F_Msk (0x1UL) /*!< DIRQ8F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ9F_Pos (1UL) /*!< DIRQ9F (Bit 1) */ + #define R_SYSTEM_DPSIFR1_DIRQ9F_Msk (0x2UL) /*!< DIRQ9F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ10F_Pos (2UL) /*!< DIRQ10F (Bit 2) */ + #define R_SYSTEM_DPSIFR1_DIRQ10F_Msk (0x4UL) /*!< DIRQ10F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ11F_Pos (3UL) /*!< DIRQ11F (Bit 3) */ + #define R_SYSTEM_DPSIFR1_DIRQ11F_Msk (0x8UL) /*!< DIRQ11F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ12F_Pos (4UL) /*!< DIRQ12F (Bit 4) */ + #define R_SYSTEM_DPSIFR1_DIRQ12F_Msk (0x10UL) /*!< DIRQ12F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ13F_Pos (5UL) /*!< DIRQ13F (Bit 5) */ + #define R_SYSTEM_DPSIFR1_DIRQ13F_Msk (0x20UL) /*!< DIRQ13F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ14F_Pos (6UL) /*!< DIRQ14F (Bit 6) */ + #define R_SYSTEM_DPSIFR1_DIRQ14F_Msk (0x40UL) /*!< DIRQ14F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR1_DIRQ15F_Pos (7UL) /*!< DIRQ15F (Bit 7) */ + #define R_SYSTEM_DPSIFR1_DIRQ15F_Msk (0x80UL) /*!< DIRQ15F (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos (0UL) /*!< DPVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk (0x1UL) /*!< DPVD1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos (1UL) /*!< DPVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk (0x2UL) /*!< DPVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos (2UL) /*!< DULPT0IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk (0x4UL) /*!< DULPT0IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos (3UL) /*!< DULPT1IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk (0x8UL) /*!< DULPT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos (5UL) /*!< DIWDTIF (Bit 5) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk (0x20UL) /*!< DIWDTIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos (7UL) /*!< DVBATTADIF (Bit 7) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk (0x80UL) /*!< DVBATTADIF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Pos (0UL) /*!< DIRQ0EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Msk (0x1UL) /*!< DIRQ0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Pos (1UL) /*!< DIRQ1EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Msk (0x2UL) /*!< DIRQ1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Pos (2UL) /*!< DIRQ2EG (Bit 2) */ + #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Msk (0x4UL) /*!< DIRQ2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Pos (3UL) /*!< DIRQ3EG (Bit 3) */ + #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Msk (0x8UL) /*!< DIRQ3EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Pos (4UL) /*!< DIRQ4EG (Bit 4) */ + #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Msk (0x10UL) /*!< DIRQ4EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Pos (5UL) /*!< DIRQ5EG (Bit 5) */ + #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Msk (0x20UL) /*!< DIRQ5EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Pos (6UL) /*!< DIRQ6EG (Bit 6) */ + #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Msk (0x40UL) /*!< DIRQ6EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Pos (7UL) /*!< DIRQ7EG (Bit 7) */ + #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Msk (0x80UL) /*!< DIRQ7EG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Pos (0UL) /*!< DIRQ8EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Msk (0x1UL) /*!< DIRQ8EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Pos (1UL) /*!< DIRQ9EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Msk (0x2UL) /*!< DIRQ9EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Pos (2UL) /*!< DIRQ10EG (Bit 2) */ + #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Msk (0x4UL) /*!< DIRQ10EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Pos (3UL) /*!< DIRQ11EG (Bit 3) */ + #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Msk (0x8UL) /*!< DIRQ11EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Pos (4UL) /*!< DIRQ12EG (Bit 4) */ + #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Msk (0x10UL) /*!< DIRQ12EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Pos (5UL) /*!< DIRQ13EG (Bit 5) */ + #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Msk (0x20UL) /*!< DIRQ13EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Pos (6UL) /*!< DIRQ14EG (Bit 6) */ + #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Msk (0x40UL) /*!< DIRQ14EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Pos (7UL) /*!< DIRQ15EG (Bit 7) */ + #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Msk (0x80UL) /*!< DIRQ15EG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DPVD1EG_Pos (0UL) /*!< DPVD1EG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DPVD1EG_Msk (0x1UL) /*!< DPVD1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DPVD2EG_Pos (1UL) /*!< DPVD2EG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DPVD2EG_Msk (0x2UL) /*!< DPVD2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD3RF_Pos (4UL) /*!< LVD3RF (Bit 4) */ + #define R_SYSTEM_RSTSR0_LVD3RF_Msk (0x10UL) /*!< LVD3RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Pos (5UL) /*!< LVD4RF (Bit 5) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Msk (0x20UL) /*!< LVD4RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Pos (6UL) /*!< LVD5RF (Bit 6) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Msk (0x40UL) /*!< LVD5RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR3 ========================================================= */ + #define R_SYSTEM_RSTSR3_OCPRF_Pos (4UL) /*!< OCPRF (Bit 4) */ + #define R_SYSTEM_RSTSR3_OCPRF_Msk (0x10UL) /*!< OCPRF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (1UL) /*!< MODRV0 (Bit 1) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0xeUL) /*!< MODRV0 (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR1 ======================================================== */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSCR ========================================================= */ + #define R_SYSTEM_LPSCR_LPMD_Pos (0UL) /*!< LPMD (Bit 0) */ + #define R_SYSTEM_LPSCR_LPMD_Msk (0xfUL) /*!< LPMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SSCR1 ========================================================= */ + #define R_SYSTEM_SSCR1_SS1FR_Pos (0UL) /*!< SS1FR (Bit 0) */ + #define R_SYSTEM_SSCR1_SS1FR_Msk (0x1UL) /*!< SS1FR (Bitfield-Mask: 0x01) */ +/* ========================================================= LVOCR ========================================================= */ + #define R_SYSTEM_LVOCR_LVO0E_Pos (0UL) /*!< LVO0E (Bit 0) */ + #define R_SYSTEM_LVOCR_LVO0E_Msk (0x1UL) /*!< LVO0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVOCR_LVO1E_Pos (1UL) /*!< LVO1E (Bit 1) */ + #define R_SYSTEM_LVOCR_LVO1E_Msk (0x2UL) /*!< LVO1E (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK0 ======================================================= */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos (0UL) /*!< IWDTMASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk (0x1UL) /*!< IWDTMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos (1UL) /*!< WDT0MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk (0x2UL) /*!< WDT0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos (2UL) /*!< SWMASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk (0x4UL) /*!< SWMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Pos (4UL) /*!< CLUP0MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Msk (0x10UL) /*!< CLUP0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos (5UL) /*!< LM0MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk (0x20UL) /*!< LM0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos (6UL) /*!< CMMASK (Bit 6) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk (0x40UL) /*!< CMMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK1 ======================================================= */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos (7UL) /*!< NWMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK1_NWMASK_Msk (0x80UL) /*!< NWMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK2 ======================================================= */ + #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Pos (0UL) /*!< LVD1MASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Msk (0x1UL) /*!< LVD1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Pos (1UL) /*!< LVD2MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Msk (0x2UL) /*!< LVD2MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Pos (2UL) /*!< LVD3MASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Msk (0x4UL) /*!< LVD3MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Pos (3UL) /*!< LVD4MASK (Bit 3) */ + #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Msk (0x8UL) /*!< LVD4MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Pos (4UL) /*!< LVD5MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Msk (0x10UL) /*!< LVD5MASK (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL1LDOCR ======================================================= */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2LDOCR ======================================================= */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= HOCOLDOCR ======================================================= */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1FCR ======================================================== */ + #define R_SYSTEM_LVD1FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD1FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2FCR ======================================================== */ + #define R_SYSTEM_LVD2FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD2FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_SOMCR_SOSEL_Pos (6UL) /*!< SOSEL (Bit 6) */ + #define R_SYSTEM_SOMCR_SOSEL_Msk (0x40UL) /*!< SOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR2 ======================================================== */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos (0UL) /*!< VDETLVL (Bit 0) */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk (0x7UL) /*!< VDETLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Pos (4UL) /*!< VDETE (Bit 4) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Msk (0x10UL) /*!< VDETE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBPSR ======================================================== */ + #define R_SYSTEM_VBTBPSR_VBPORF_Pos (0UL) /*!< VBPORF (Bit 0) */ + #define R_SYSTEM_VBTBPSR_VBPORF_Msk (0x1UL) /*!< VBPORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Pos (4UL) /*!< VBPORM (Bit 4) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Msk (0x10UL) /*!< VBPORM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Pos (5UL) /*!< BPWSWM (Bit 5) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Msk (0x20UL) /*!< BPWSWM (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTADSR ======================================================== */ + #define R_SYSTEM_VBTADSR_VBTADF0_Pos (0UL) /*!< VBTADF0 (Bit 0) */ + #define R_SYSTEM_VBTADSR_VBTADF0_Msk (0x1UL) /*!< VBTADF0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Pos (1UL) /*!< VBTADF1 (Bit 1) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Msk (0x2UL) /*!< VBTADF1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Pos (2UL) /*!< VBTADF2 (Bit 2) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Msk (0x4UL) /*!< VBTADF2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR1 ======================================================== */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos (0UL) /*!< VBTADIE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk (0x1UL) /*!< VBTADIE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos (1UL) /*!< VBTADIE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk (0x2UL) /*!< VBTADIE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos (2UL) /*!< VBTADIE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk (0x4UL) /*!< VBTADIE2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos (4UL) /*!< VBTADCLE0 (Bit 4) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk (0x10UL) /*!< VBTADCLE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos (5UL) /*!< VBTADCLE1 (Bit 5) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk (0x20UL) /*!< VBTADCLE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos (6UL) /*!< VBTADCLE2 (Bit 6) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk (0x40UL) /*!< VBTADCLE2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR2 ======================================================== */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos (0UL) /*!< VBRTCES0 (Bit 0) */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk (0x1UL) /*!< VBRTCES0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos (1UL) /*!< VBRTCES1 (Bit 1) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk (0x2UL) /*!< VBRTCES1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos (2UL) /*!< VBRTCES2 (Bit 2) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk (0x4UL) /*!< VBRTCES2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR2 ======================================================= */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos (0UL) /*!< VCH0NCE (Bit 0) */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk (0x1UL) /*!< VCH0NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos (1UL) /*!< VCH1NCE (Bit 1) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk (0x2UL) /*!< VCH1NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos (2UL) /*!< VCH2NCE (Bit 2) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk (0x4UL) /*!< VCH2NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos (4UL) /*!< VCH0EG (Bit 4) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk (0x10UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos (5UL) /*!< VCH1EG (Bit 5) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk (0x20UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos (6UL) /*!< VCH2EG (Bit 6) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk (0x40UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTIMONR ======================================================== */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Pos (0UL) /*!< VCH0MON (Bit 0) */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Msk (0x1UL) /*!< VCH0MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Pos (1UL) /*!< VCH1MON (Bit 1) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Msk (0x2UL) /*!< VCH1MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Pos (2UL) /*!< VCH2MON (Bit 2) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Msk (0x4UL) /*!< VCH2MON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR0 ======================================================== */ + #define R_SYSTEM_VBTBKR0_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR0_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR1 ======================================================== */ + #define R_SYSTEM_VBTBKR1_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR1_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR2 ======================================================== */ + #define R_SYSTEM_VBTBKR2_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR2_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR3 ======================================================== */ + #define R_SYSTEM_VBTBKR3_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR3_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR4 ======================================================== */ + #define R_SYSTEM_VBTBKR4_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR4_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR5 ======================================================== */ + #define R_SYSTEM_VBTBKR5_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR5_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR6 ======================================================== */ + #define R_SYSTEM_VBTBKR6_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR6_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR7 ======================================================== */ + #define R_SYSTEM_VBTBKR7_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR7_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR8 ======================================================== */ + #define R_SYSTEM_VBTBKR8_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR8_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTBKR9 ======================================================== */ + #define R_SYSTEM_VBTBKR9_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR9_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR10 ======================================================== */ + #define R_SYSTEM_VBTBKR10_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR10_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR11 ======================================================== */ + #define R_SYSTEM_VBTBKR11_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR11_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR12 ======================================================== */ + #define R_SYSTEM_VBTBKR12_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR12_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR13 ======================================================== */ + #define R_SYSTEM_VBTBKR13_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR13_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR14 ======================================================== */ + #define R_SYSTEM_VBTBKR14_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR14_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR15 ======================================================== */ + #define R_SYSTEM_VBTBKR15_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR15_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR16 ======================================================== */ + #define R_SYSTEM_VBTBKR16_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR16_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR17 ======================================================== */ + #define R_SYSTEM_VBTBKR17_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR17_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR18 ======================================================== */ + #define R_SYSTEM_VBTBKR18_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR18_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR19 ======================================================== */ + #define R_SYSTEM_VBTBKR19_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR19_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR20 ======================================================== */ + #define R_SYSTEM_VBTBKR20_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR20_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR21 ======================================================== */ + #define R_SYSTEM_VBTBKR21_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR21_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR22 ======================================================== */ + #define R_SYSTEM_VBTBKR22_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR22_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR23 ======================================================== */ + #define R_SYSTEM_VBTBKR23_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR23_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR24 ======================================================== */ + #define R_SYSTEM_VBTBKR24_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR24_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR25 ======================================================== */ + #define R_SYSTEM_VBTBKR25_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR25_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR26 ======================================================== */ + #define R_SYSTEM_VBTBKR26_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR26_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR27 ======================================================== */ + #define R_SYSTEM_VBTBKR27_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR27_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR28 ======================================================== */ + #define R_SYSTEM_VBTBKR28_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR28_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR29 ======================================================== */ + #define R_SYSTEM_VBTBKR29_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR29_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR30 ======================================================== */ + #define R_SYSTEM_VBTBKR30_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR30_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR31 ======================================================== */ + #define R_SYSTEM_VBTBKR31_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR31_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR32 ======================================================== */ + #define R_SYSTEM_VBTBKR32_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR32_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR33 ======================================================== */ + #define R_SYSTEM_VBTBKR33_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR33_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR34 ======================================================== */ + #define R_SYSTEM_VBTBKR34_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR34_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR35 ======================================================== */ + #define R_SYSTEM_VBTBKR35_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR35_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR36 ======================================================== */ + #define R_SYSTEM_VBTBKR36_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR36_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR37 ======================================================== */ + #define R_SYSTEM_VBTBKR37_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR37_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR38 ======================================================== */ + #define R_SYSTEM_VBTBKR38_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR38_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR39 ======================================================== */ + #define R_SYSTEM_VBTBKR39_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR39_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR40 ======================================================== */ + #define R_SYSTEM_VBTBKR40_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR40_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR41 ======================================================== */ + #define R_SYSTEM_VBTBKR41_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR41_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR42 ======================================================== */ + #define R_SYSTEM_VBTBKR42_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR42_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR43 ======================================================== */ + #define R_SYSTEM_VBTBKR43_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR43_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR44 ======================================================== */ + #define R_SYSTEM_VBTBKR44_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR44_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR45 ======================================================== */ + #define R_SYSTEM_VBTBKR45_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR45_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR46 ======================================================== */ + #define R_SYSTEM_VBTBKR46_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR46_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR47 ======================================================== */ + #define R_SYSTEM_VBTBKR47_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR47_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR48 ======================================================== */ + #define R_SYSTEM_VBTBKR48_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR48_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR49 ======================================================== */ + #define R_SYSTEM_VBTBKR49_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR49_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR50 ======================================================== */ + #define R_SYSTEM_VBTBKR50_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR50_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR51 ======================================================== */ + #define R_SYSTEM_VBTBKR51_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR51_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR52 ======================================================== */ + #define R_SYSTEM_VBTBKR52_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR52_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR53 ======================================================== */ + #define R_SYSTEM_VBTBKR53_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR53_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR54 ======================================================== */ + #define R_SYSTEM_VBTBKR54_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR54_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR55 ======================================================== */ + #define R_SYSTEM_VBTBKR55_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR55_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR56 ======================================================== */ + #define R_SYSTEM_VBTBKR56_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR56_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR57 ======================================================== */ + #define R_SYSTEM_VBTBKR57_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR57_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR58 ======================================================== */ + #define R_SYSTEM_VBTBKR58_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR58_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR59 ======================================================== */ + #define R_SYSTEM_VBTBKR59_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR59_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR60 ======================================================== */ + #define R_SYSTEM_VBTBKR60_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR60_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR61 ======================================================== */ + #define R_SYSTEM_VBTBKR61_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR61_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR62 ======================================================== */ + #define R_SYSTEM_VBTBKR62_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR62_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR63 ======================================================== */ + #define R_SYSTEM_VBTBKR63_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR63_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR64 ======================================================== */ + #define R_SYSTEM_VBTBKR64_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR64_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR65 ======================================================== */ + #define R_SYSTEM_VBTBKR65_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR65_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR66 ======================================================== */ + #define R_SYSTEM_VBTBKR66_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR66_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR67 ======================================================== */ + #define R_SYSTEM_VBTBKR67_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR67_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR68 ======================================================== */ + #define R_SYSTEM_VBTBKR68_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR68_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR69 ======================================================== */ + #define R_SYSTEM_VBTBKR69_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR69_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR70 ======================================================== */ + #define R_SYSTEM_VBTBKR70_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR70_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR71 ======================================================== */ + #define R_SYSTEM_VBTBKR71_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR71_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR72 ======================================================== */ + #define R_SYSTEM_VBTBKR72_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR72_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR73 ======================================================== */ + #define R_SYSTEM_VBTBKR73_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR73_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR74 ======================================================== */ + #define R_SYSTEM_VBTBKR74_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR74_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR75 ======================================================== */ + #define R_SYSTEM_VBTBKR75_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR75_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR76 ======================================================== */ + #define R_SYSTEM_VBTBKR76_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR76_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR77 ======================================================== */ + #define R_SYSTEM_VBTBKR77_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR77_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR78 ======================================================== */ + #define R_SYSTEM_VBTBKR78_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR78_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR79 ======================================================== */ + #define R_SYSTEM_VBTBKR79_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR79_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR80 ======================================================== */ + #define R_SYSTEM_VBTBKR80_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR80_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR81 ======================================================== */ + #define R_SYSTEM_VBTBKR81_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR81_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR82 ======================================================== */ + #define R_SYSTEM_VBTBKR82_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR82_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR83 ======================================================== */ + #define R_SYSTEM_VBTBKR83_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR83_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR84 ======================================================== */ + #define R_SYSTEM_VBTBKR84_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR84_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR85 ======================================================== */ + #define R_SYSTEM_VBTBKR85_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR85_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR86 ======================================================== */ + #define R_SYSTEM_VBTBKR86_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR86_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR87 ======================================================== */ + #define R_SYSTEM_VBTBKR87_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR87_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR88 ======================================================== */ + #define R_SYSTEM_VBTBKR88_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR88_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR89 ======================================================== */ + #define R_SYSTEM_VBTBKR89_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR89_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR90 ======================================================== */ + #define R_SYSTEM_VBTBKR90_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR90_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR91 ======================================================== */ + #define R_SYSTEM_VBTBKR91_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR91_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR92 ======================================================== */ + #define R_SYSTEM_VBTBKR92_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR92_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR93 ======================================================== */ + #define R_SYSTEM_VBTBKR93_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR93_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR94 ======================================================== */ + #define R_SYSTEM_VBTBKR94_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR94_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR95 ======================================================== */ + #define R_SYSTEM_VBTBKR95_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR95_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR96 ======================================================== */ + #define R_SYSTEM_VBTBKR96_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR96_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR97 ======================================================== */ + #define R_SYSTEM_VBTBKR97_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR97_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR98 ======================================================== */ + #define R_SYSTEM_VBTBKR98_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR98_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR99 ======================================================== */ + #define R_SYSTEM_VBTBKR99_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR99_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR100 ======================================================= */ + #define R_SYSTEM_VBTBKR100_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR100_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR101 ======================================================= */ + #define R_SYSTEM_VBTBKR101_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR101_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR102 ======================================================= */ + #define R_SYSTEM_VBTBKR102_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR102_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR103 ======================================================= */ + #define R_SYSTEM_VBTBKR103_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR103_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR104 ======================================================= */ + #define R_SYSTEM_VBTBKR104_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR104_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR105 ======================================================= */ + #define R_SYSTEM_VBTBKR105_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR105_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR106 ======================================================= */ + #define R_SYSTEM_VBTBKR106_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR106_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR107 ======================================================= */ + #define R_SYSTEM_VBTBKR107_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR107_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR108 ======================================================= */ + #define R_SYSTEM_VBTBKR108_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR108_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR109 ======================================================= */ + #define R_SYSTEM_VBTBKR109_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR109_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR110 ======================================================= */ + #define R_SYSTEM_VBTBKR110_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR110_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR111 ======================================================= */ + #define R_SYSTEM_VBTBKR111_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR111_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR112 ======================================================= */ + #define R_SYSTEM_VBTBKR112_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR112_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR113 ======================================================= */ + #define R_SYSTEM_VBTBKR113_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR113_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR114 ======================================================= */ + #define R_SYSTEM_VBTBKR114_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR114_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR115 ======================================================= */ + #define R_SYSTEM_VBTBKR115_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR115_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR116 ======================================================= */ + #define R_SYSTEM_VBTBKR116_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR116_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR117 ======================================================= */ + #define R_SYSTEM_VBTBKR117_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR117_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR118 ======================================================= */ + #define R_SYSTEM_VBTBKR118_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR118_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR119 ======================================================= */ + #define R_SYSTEM_VBTBKR119_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR119_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR120 ======================================================= */ + #define R_SYSTEM_VBTBKR120_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR120_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR121 ======================================================= */ + #define R_SYSTEM_VBTBKR121_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR121_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR122 ======================================================= */ + #define R_SYSTEM_VBTBKR122_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR122_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR123 ======================================================= */ + #define R_SYSTEM_VBTBKR123_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR123_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR124 ======================================================= */ + #define R_SYSTEM_VBTBKR124_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR124_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR125 ======================================================= */ + #define R_SYSTEM_VBTBKR125_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR125_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR126 ======================================================= */ + #define R_SYSTEM_VBTBKR126_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR126_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================= VBTBKR127 ======================================================= */ + #define R_SYSTEM_VBTBKR127_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR127_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos (23UL) /*!< SAACMPLP0WUP (Bit 23) */ + #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk (0x800000UL) /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARM ======================================================== */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos (0UL) /*!< SAINTUR0WUP (Bit 0) */ + #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk (0x1UL) /*!< SAINTUR0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos (1UL) /*!< SAINTURE0WUP (Bit 1) */ + #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk (0x2UL) /*!< SAINTURE0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos (2UL) /*!< SAINTUR1WUP (Bit 2) */ + #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk (0x4UL) /*!< SAINTUR1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos (3UL) /*!< SAINTURE1WUP (Bit 3) */ + #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk (0x8UL) /*!< SAINTURE1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos (4UL) /*!< SAEXLVDVBATWUP (Bit 4) */ + #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk (0x10UL) /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos (5UL) /*!< SALVDVRTCWUP (Bit 5) */ + #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk (0x20UL) /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos (6UL) /*!< SAEXLVDWUP (Bit 6) */ + #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk (0x40UL) /*!< SAEXLVDWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_CPSCU_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_CPSCU_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */ + #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */ + #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */ + #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */ + #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= DOSR ========================================================== */ + #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */ + #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSCR ========================================================= */ + #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */ + #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ======================================================== DODSR0 ========================================================= */ +/* ======================================================== DODSR1 ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ======================================================== RDR_BY ========================================================= */ + #define R_SCI_B0_RDR_BY_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_BY_RDAT_Msk (0xffUL) /*!< RDAT (Bitfield-Mask: 0xff) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== TDR_BY ========================================================= */ + #define R_SCI_B0_TDR_BY_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_BY_TDAT_Msk (0xffUL) /*!< TDAT (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_SCKSEL_Pos (19UL) /*!< SCKSEL (Bit 19) */ + #define R_SCI_B0_CCR4_SCKSEL_Msk (0x80000UL) /*!< SCKSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= CESR ========================================================== */ + #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */ + #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */ + #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCR ========================================================== */ + #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */ + #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */ + #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */ + #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */ + #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */ + #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */ + #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */ + #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================= XCR0 ========================================================== */ + #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */ + #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */ + #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */ + #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */ + #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */ + #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */ + #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */ + #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */ + #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */ + #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */ + #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */ + #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */ + #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */ +/* ========================================================= XCR1 ========================================================== */ + #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */ + #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */ + #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */ + #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */ + #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */ + #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */ +/* ========================================================= XCR2 ========================================================== */ + #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */ + #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */ + #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */ + #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================== MSR ========================================================== */ + #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */ + #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */ + #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= XSR0 ========================================================== */ + #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */ + #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */ + #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */ + #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */ + #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */ + #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */ + #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */ + #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */ + #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */ + #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */ + #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */ + #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */ + #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */ +/* ========================================================= XSR1 ========================================================== */ + #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */ + #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ +/* ========================================================= MFCLR ========================================================= */ + #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */ + #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */ + #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */ + #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */ + #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */ +/* ========================================================= XFCLR ========================================================= */ + #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */ + #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */ + #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */ + #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */ + #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */ + #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */ + #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */ + #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */ + #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDECR ========================================================= */ + #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */ + #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */ + #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */ + #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */ + #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */ + #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */ + #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */ + #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */ + #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */ + #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD0 ========================================================= */ + #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD1 ========================================================= */ + #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD2 ========================================================= */ + #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD3 ========================================================= */ + #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD4 ========================================================= */ + #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD5 ========================================================= */ + #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD6 ========================================================= */ + #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD7 ========================================================= */ + #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */ + #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */ + #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */ + #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */ + #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */ + #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */ + #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */ + #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */ + #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */ + #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */ + #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */ + #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */ + #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */ + #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */ + #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */ + #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */ + #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */ + #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */ + #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */ + #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Pos (0UL) /*!< CKSFTCS0 (Bit 0) */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Msk (0x1fUL) /*!< CKSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Pos (16UL) /*!< CKSFTCS1 (Bit 16) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Msk (0x1f0000UL) /*!< CKSFTCS1 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_ARBMD_Pos (0UL) /*!< ARBMD (Bit 0) */ + #define R_XSPI0_COMCFG_ARBMD_Msk (0x3UL) /*!< ARBMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Pos (4UL) /*!< ECSINTOUTEN (Bit 4) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Msk (0x30UL) /*!< ECSINTOUTEN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ======================================================== BMCFGCH ======================================================== */ + #define R_XSPI0_BMCFGCH_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFGCH_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFGCH_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFGCH_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Pos (24UL) /*!< CMBTIM (Bit 24) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Msk (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== ABMCFG ========================================================= */ + #define R_XSPI0_ABMCFG_ODRMD_Pos (0UL) /*!< ODRMD (Bit 0) */ + #define R_XSPI0_ABMCFG_ODRMD_Msk (0x3UL) /*!< ODRMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_ABMCFG_CHSEL_Pos (16UL) /*!< CHSEL (Bit 16) */ + #define R_XSPI0_ABMCFG_CHSEL_Msk (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Pos (0UL) /*!< CH0CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Msk (0x3UL) /*!< CH0CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Pos (2UL) /*!< CH0CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Msk (0xcUL) /*!< CH0CS1ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Pos (4UL) /*!< CH1CS0ACC (Bit 4) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Msk (0x30UL) /*!< CH1CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Pos (6UL) /*!< CH1CS1ACC (Bit 6) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Msk (0xc0UL) /*!< CH1CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Pos (8UL) /*!< MWRPUSHCH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Msk (0x100UL) /*!< MWRPUSHCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Pos (10UL) /*!< PBUFCLRCH (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Msk (0x400UL) /*!< PBUFCLRCH (Bitfield-Mask: 0x01) */ +/* ======================================================== CMCTLCH ======================================================== */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTLCH_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS_Pos (0UL) /*!< WPCS (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS_Msk (0x1UL) /*!< WPCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS_Pos (16UL) /*!< RSTCS (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS_Msk (0x10000UL) /*!< RSTCS (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACCCH_Pos (0UL) /*!< MEMACCCH (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACCCH_Msk (0x1UL) /*!< MEMACCCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNECH_Pos (4UL) /*!< PBUFNECH (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNECH_Msk (0x10UL) /*!< PBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Pos (6UL) /*!< WRBUFNECH (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Msk (0x40UL) /*!< WRBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS_Pos (16UL) /*!< ECSCS (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS_Msk (0x10000UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS_Pos (17UL) /*!< INTCS (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS_Msk (0x20000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS_Pos (18UL) /*!< RSTOCS (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS_Msk (0x40000UL) /*!< RSTOCS (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS_Pos (4UL) /*!< DSTOCS (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS_Msk (0x10UL) /*!< DSTOCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS_Pos (8UL) /*!< ECSCS (Bit 8) */ + #define R_XSPI0_INTS_ECSCS_Msk (0x100UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS_Pos (12UL) /*!< INTCS (Bit 12) */ + #define R_XSPI0_INTS_INTCS_Msk (0x1000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOFCH_Pos (16UL) /*!< BRGOFCH (Bit 16) */ + #define R_XSPI0_INTS_BRGOFCH_Msk (0x10000UL) /*!< BRGOFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUFCH_Pos (18UL) /*!< BRGUFCH (Bit 18) */ + #define R_XSPI0_INTS_BRGUFCH_Msk (0x40000UL) /*!< BRGUFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERRCH_Pos (20UL) /*!< BUSERRCH (Bit 20) */ + #define R_XSPI0_INTS_BUSERRCH_Msk (0x100000UL) /*!< BUSERRCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS_Pos (28UL) /*!< CAFAILCS (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS_Msk (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS_Pos (30UL) /*!< CASUCCS (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS_Msk (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCSC_Pos (4UL) /*!< DSTOCSC (Bit 4) */ + #define R_XSPI0_INTC_DSTOCSC_Msk (0x10UL) /*!< DSTOCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCSC_Pos (8UL) /*!< ECSCSC (Bit 8) */ + #define R_XSPI0_INTC_ECSCSC_Msk (0x100UL) /*!< ECSCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCSC_Pos (12UL) /*!< INTCSC (Bit 12) */ + #define R_XSPI0_INTC_INTCSC_Msk (0x1000UL) /*!< INTCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFCHC_Pos (16UL) /*!< BRGOFCHC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFCHC_Msk (0x10000UL) /*!< BRGOFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFCHC_Pos (18UL) /*!< BRGUFCHC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFCHC_Msk (0x40000UL) /*!< BRGUFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRCHC_Pos (20UL) /*!< BUSERRCHC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRCHC_Msk (0x100000UL) /*!< BUSERRCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCSC_Pos (28UL) /*!< CAFAILCSC (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCSC_Msk (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCSC_Pos (30UL) /*!< CASUCCSC (Bit 30) */ + #define R_XSPI0_INTC_CASUCCSC_Msk (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCSE_Pos (4UL) /*!< DSTOCSE (Bit 4) */ + #define R_XSPI0_INTE_DSTOCSE_Msk (0x10UL) /*!< DSTOCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCSE_Pos (8UL) /*!< ECSCSE (Bit 8) */ + #define R_XSPI0_INTE_ECSCSE_Msk (0x100UL) /*!< ECSCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCSE_Pos (12UL) /*!< INTCSE (Bit 12) */ + #define R_XSPI0_INTE_INTCSE_Msk (0x1000UL) /*!< INTCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFCHE_Pos (16UL) /*!< BRGOFCHE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFCHE_Msk (0x10000UL) /*!< BRGOFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFCHE_Pos (18UL) /*!< BRGUFCHE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFCHE_Msk (0x40000UL) /*!< BRGUFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRCHE_Pos (20UL) /*!< BUSERRCHE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRCHE_Msk (0x100000UL) /*!< BUSERRCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCSE_Pos (28UL) /*!< CAFAILCSE (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCSE_Msk (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCSE_Pos (30UL) /*!< CASUCCSE (Bit 30) */ + #define R_XSPI0_INTE_CASUCCSE_Msk (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CAPSR ========================================================= */ + #define R_CEU_CAPSR_CE_Pos (0UL) /*!< CE (Bit 0) */ + #define R_CEU_CAPSR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPSR_CPKIL_Pos (16UL) /*!< CPKIL (Bit 16) */ + #define R_CEU_CAPSR_CPKIL_Msk (0x10000UL) /*!< CPKIL (Bitfield-Mask: 0x01) */ +/* ========================================================= CAPCR ========================================================= */ + #define R_CEU_CAPCR_CTNCP_Pos (16UL) /*!< CTNCP (Bit 16) */ + #define R_CEU_CAPCR_CTNCP_Msk (0x10000UL) /*!< CTNCP (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPCR_MTCM_Pos (20UL) /*!< MTCM (Bit 20) */ + #define R_CEU_CAPCR_MTCM_Msk (0x300000UL) /*!< MTCM (Bitfield-Mask: 0x03) */ + #define R_CEU_CAPCR_FDRP_Pos (24UL) /*!< FDRP (Bit 24) */ + #define R_CEU_CAPCR_FDRP_Msk (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff) */ +/* ========================================================= CAMCR ========================================================= */ + #define R_CEU_CAMCR_HDPOL_Pos (0UL) /*!< HDPOL (Bit 0) */ + #define R_CEU_CAMCR_HDPOL_Msk (0x1UL) /*!< HDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDPOL_Pos (1UL) /*!< VDPOL (Bit 1) */ + #define R_CEU_CAMCR_VDPOL_Msk (0x2UL) /*!< VDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_JPG_Pos (4UL) /*!< JPG (Bit 4) */ + #define R_CEU_CAMCR_JPG_Msk (0x30UL) /*!< JPG (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTARY_Pos (8UL) /*!< DTARY (Bit 8) */ + #define R_CEU_CAMCR_DTARY_Msk (0x300UL) /*!< DTARY (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTIF_Pos (12UL) /*!< DTIF (Bit 12) */ + #define R_CEU_CAMCR_DTIF_Msk (0x1000UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDPOL_Pos (16UL) /*!< FLDPOL (Bit 16) */ + #define R_CEU_CAMCR_FLDPOL_Msk (0x10000UL) /*!< FLDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_DSEL_Pos (24UL) /*!< DSEL (Bit 24) */ + #define R_CEU_CAMCR_DSEL_Msk (0x1000000UL) /*!< DSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDSEL_Pos (25UL) /*!< FLDSEL (Bit 25) */ + #define R_CEU_CAMCR_FLDSEL_Msk (0x2000000UL) /*!< FLDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_HDSEL_Pos (26UL) /*!< HDSEL (Bit 26) */ + #define R_CEU_CAMCR_HDSEL_Msk (0x4000000UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDSEL_Pos (27UL) /*!< VDSEL (Bit 27) */ + #define R_CEU_CAMCR_VDSEL_Msk (0x8000000UL) /*!< VDSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCYR ========================================================= */ + #define R_CEU_CMCYR_HCYL_Pos (0UL) /*!< HCYL (Bit 0) */ + #define R_CEU_CMCYR_HCYL_Msk (0x3fffUL) /*!< HCYL (Bitfield-Mask: 0x3fff) */ + #define R_CEU_CMCYR_VCYL_Pos (16UL) /*!< VCYL (Bit 16) */ + #define R_CEU_CMCYR_VCYL_Msk (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CAMOR ========================================================= */ + #define R_CEU_CAMOR_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAPWR ========================================================= */ + #define R_CEU_CAPWR_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAIFR ========================================================= */ + #define R_CEU_CAIFR_FCI_Pos (0UL) /*!< FCI (Bit 0) */ + #define R_CEU_CAIFR_FCI_Msk (0x3UL) /*!< FCI (Bitfield-Mask: 0x03) */ + #define R_CEU_CAIFR_CIM_Pos (4UL) /*!< CIM (Bit 4) */ + #define R_CEU_CAIFR_CIM_Msk (0x10UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_CEU_CAIFR_IFS_Pos (8UL) /*!< IFS (Bit 8) */ + #define R_CEU_CAIFR_IFS_Msk (0x100UL) /*!< IFS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCNTR ========================================================= */ + #define R_CEU_CRCNTR_RC_Pos (0UL) /*!< RC (Bit 0) */ + #define R_CEU_CRCNTR_RC_Msk (0x1UL) /*!< RC (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_CEU_CRCNTR_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RVS_Pos (4UL) /*!< RVS (Bit 4) */ + #define R_CEU_CRCNTR_RVS_Msk (0x10UL) /*!< RVS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCMPR ========================================================= */ + #define R_CEU_CRCMPR_RA_Pos (0UL) /*!< RA (Bit 0) */ + #define R_CEU_CRCMPR_RA_Msk (0x1UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ========================================================= CFLCR ========================================================= */ + #define R_CEU_CFLCR_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFSZR ========================================================= */ + #define R_CEU_CFSZR_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ========================================================= CDWDR ========================================================= */ + #define R_CEU_CDWDR_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ========================================================= CDAYR ========================================================= */ + #define R_CEU_CDAYR_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDACR ========================================================= */ + #define R_CEU_CDACR_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBYR ========================================================= */ + #define R_CEU_CDBYR_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBCR ========================================================= */ + #define R_CEU_CDBCR_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CBDSR ========================================================= */ + #define R_CEU_CBDSR_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= CFWCR ========================================================= */ + #define R_CEU_CFWCR_FWE_Pos (0UL) /*!< FWE (Bit 0) */ + #define R_CEU_CFWCR_FWE_Msk (0x1UL) /*!< FWE (Bitfield-Mask: 0x01) */ + #define R_CEU_CFWCR_FWV_Pos (5UL) /*!< FWV (Bit 5) */ + #define R_CEU_CFWCR_FWV_Msk (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff) */ +/* ========================================================= CLFCR ========================================================= */ + #define R_CEU_CLFCR_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ========================================================= CDOCR ========================================================= */ + #define R_CEU_CDOCR_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ========================================================= CEIER ========================================================= */ + #define R_CEU_CEIER_CPEIE_Pos (0UL) /*!< CPEIE (Bit 0) */ + #define R_CEU_CEIER_CPEIE_Msk (0x1UL) /*!< CPEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CFEIE_Pos (1UL) /*!< CFEIE (Bit 1) */ + #define R_CEU_CEIER_CFEIE_Msk (0x2UL) /*!< CFEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGRWIE_Pos (4UL) /*!< IGRWIE (Bit 4) */ + #define R_CEU_CEIER_IGRWIE_Msk (0x10UL) /*!< IGRWIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_HDIE_Pos (8UL) /*!< HDIE (Bit 8) */ + #define R_CEU_CEIER_HDIE_Msk (0x100UL) /*!< HDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VDIE_Pos (9UL) /*!< VDIE (Bit 9) */ + #define R_CEU_CEIER_VDIE_Msk (0x200UL) /*!< VDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE1IE_Pos (12UL) /*!< CPBE1IE (Bit 12) */ + #define R_CEU_CEIER_CPBE1IE_Msk (0x1000UL) /*!< CPBE1IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE2IE_Pos (13UL) /*!< CPBE2IE (Bit 13) */ + #define R_CEU_CEIER_CPBE2IE_Msk (0x2000UL) /*!< CPBE2IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE3IE_Pos (14UL) /*!< CPBE3IE (Bit 14) */ + #define R_CEU_CEIER_CPBE3IE_Msk (0x4000UL) /*!< CPBE3IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE4IE_Pos (15UL) /*!< CPBE4IE (Bit 15) */ + #define R_CEU_CEIER_CPBE4IE_Msk (0x8000UL) /*!< CPBE4IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CDTOFIE_Pos (16UL) /*!< CDTOFIE (Bit 16) */ + #define R_CEU_CEIER_CDTOFIE_Msk (0x10000UL) /*!< CDTOFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGHSIE_Pos (17UL) /*!< IGHSIE (Bit 17) */ + #define R_CEU_CEIER_IGHSIE_Msk (0x20000UL) /*!< IGHSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGVSIE_Pos (18UL) /*!< IGVSIE (Bit 18) */ + #define R_CEU_CEIER_IGVSIE_Msk (0x40000UL) /*!< IGVSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VBPIE_Pos (20UL) /*!< VBPIE (Bit 20) */ + #define R_CEU_CEIER_VBPIE_Msk (0x100000UL) /*!< VBPIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_FWFIE_Pos (23UL) /*!< FWFIE (Bit 23) */ + #define R_CEU_CEIER_FWFIE_Msk (0x800000UL) /*!< FWFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NHDIE_Pos (24UL) /*!< NHDIE (Bit 24) */ + #define R_CEU_CEIER_NHDIE_Msk (0x1000000UL) /*!< NHDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NVDIE_Pos (25UL) /*!< NVDIE (Bit 25) */ + #define R_CEU_CEIER_NVDIE_Msk (0x2000000UL) /*!< NVDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETCR ========================================================= */ + #define R_CEU_CETCR_CPE_Pos (0UL) /*!< CPE (Bit 0) */ + #define R_CEU_CETCR_CPE_Msk (0x1UL) /*!< CPE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CFE_Pos (1UL) /*!< CFE (Bit 1) */ + #define R_CEU_CETCR_CFE_Msk (0x2UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGRW_Pos (4UL) /*!< IGRW (Bit 4) */ + #define R_CEU_CETCR_IGRW_Msk (0x10UL) /*!< IGRW (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_HD_Pos (8UL) /*!< HD (Bit 8) */ + #define R_CEU_CETCR_HD_Msk (0x100UL) /*!< HD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VD_Pos (9UL) /*!< VD (Bit 9) */ + #define R_CEU_CETCR_VD_Msk (0x200UL) /*!< VD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE1_Pos (12UL) /*!< CPBE1 (Bit 12) */ + #define R_CEU_CETCR_CPBE1_Msk (0x1000UL) /*!< CPBE1 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE2_Pos (13UL) /*!< CPBE2 (Bit 13) */ + #define R_CEU_CETCR_CPBE2_Msk (0x2000UL) /*!< CPBE2 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE3_Pos (14UL) /*!< CPBE3 (Bit 14) */ + #define R_CEU_CETCR_CPBE3_Msk (0x4000UL) /*!< CPBE3 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE4_Pos (15UL) /*!< CPBE4 (Bit 15) */ + #define R_CEU_CETCR_CPBE4_Msk (0x8000UL) /*!< CPBE4 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CDTOF_Pos (16UL) /*!< CDTOF (Bit 16) */ + #define R_CEU_CETCR_CDTOF_Msk (0x10000UL) /*!< CDTOF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGHS_Pos (17UL) /*!< IGHS (Bit 17) */ + #define R_CEU_CETCR_IGHS_Msk (0x20000UL) /*!< IGHS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGVS_Pos (18UL) /*!< IGVS (Bit 18) */ + #define R_CEU_CETCR_IGVS_Msk (0x40000UL) /*!< IGVS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VBP_Pos (20UL) /*!< VBP (Bit 20) */ + #define R_CEU_CETCR_VBP_Msk (0x100000UL) /*!< VBP (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_FWF_Pos (23UL) /*!< FWF (Bit 23) */ + #define R_CEU_CETCR_FWF_Msk (0x800000UL) /*!< FWF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NHD_Pos (24UL) /*!< NHD (Bit 24) */ + #define R_CEU_CETCR_NHD_Msk (0x1000000UL) /*!< NHD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NVD_Pos (25UL) /*!< NVD (Bit 25) */ + #define R_CEU_CETCR_NVD_Msk (0x2000000UL) /*!< NVD (Bitfield-Mask: 0x01) */ +/* ========================================================= CSTSR ========================================================= */ + #define R_CEU_CSTSR_CPTON_Pos (0UL) /*!< CPTON (Bit 0) */ + #define R_CEU_CSTSR_CPTON_Msk (0x1UL) /*!< CPTON (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CPFLD_Pos (16UL) /*!< CPFLD (Bit 16) */ + #define R_CEU_CSTSR_CPFLD_Msk (0x10000UL) /*!< CPFLD (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CRST_Pos (24UL) /*!< CRST (Bit 24) */ + #define R_CEU_CSTSR_CRST_Msk (0x1000000UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CDSSR ========================================================= */ + #define R_CEU_CDSSR_CDSS_Pos (0UL) /*!< CDSS (Bit 0) */ + #define R_CEU_CDSSR_CDSS_Msk (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDAYR2 ========================================================= */ + #define R_CEU_CDAYR2_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR2 ========================================================= */ + #define R_CEU_CDACR2_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR2 ========================================================= */ + #define R_CEU_CDBYR2_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR2 ========================================================= */ + #define R_CEU_CDBCR2_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== AXIBUSCTL2 ======================================================= */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Pos (0UL) /*!< AWCACHE (Bit 0) */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Msk (0xfUL) /*!< AWCACHE (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAMOR_B ======================================================== */ + #define R_CEU_CAMOR_B_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_B_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_B_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_B_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_B ======================================================== */ + #define R_CEU_CAPWR_B_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_B_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_B_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_B_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_B ======================================================== */ + #define R_CEU_CFLCR_B_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_B_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_B_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_B_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_B_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_B_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_B ======================================================== */ + #define R_CEU_CFSZR_B_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_B_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_B_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_B_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_B ======================================================== */ + #define R_CEU_CDWDR_B_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_B_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_B ======================================================== */ + #define R_CEU_CDAYR_B_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_B_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_B ======================================================== */ + #define R_CEU_CDACR_B_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_B_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_B ======================================================== */ + #define R_CEU_CDBYR_B_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_B_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_B ======================================================== */ + #define R_CEU_CDBCR_B_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_B_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_B ======================================================== */ + #define R_CEU_CBDSR_B_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_B_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_B ======================================================== */ + #define R_CEU_CLFCR_B_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_B_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_B ======================================================== */ + #define R_CEU_CDOCR_B_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_B_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_B_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_B_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_B_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_B_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_B ======================================================== */ + #define R_CEU_CDAYR2_B_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_B_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_B ======================================================== */ + #define R_CEU_CDACR2_B_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_B_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_B ======================================================== */ + #define R_CEU_CDBYR2_B_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_B_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_B ======================================================== */ + #define R_CEU_CDBCR2_B_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_B_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAMOR_M ======================================================== */ + #define R_CEU_CAMOR_M_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_M_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_M_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_M_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_M ======================================================== */ + #define R_CEU_CAPWR_M_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_M_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_M_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_M_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_M ======================================================== */ + #define R_CEU_CFLCR_M_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_M_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_M_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_M_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_M_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_M_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_M ======================================================== */ + #define R_CEU_CFSZR_M_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_M_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_M_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_M_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_M ======================================================== */ + #define R_CEU_CDWDR_M_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_M_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_M ======================================================== */ + #define R_CEU_CDAYR_M_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_M_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_M ======================================================== */ + #define R_CEU_CDACR_M_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_M_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_M ======================================================== */ + #define R_CEU_CDBYR_M_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_M_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_M ======================================================== */ + #define R_CEU_CDBCR_M_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_M_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_M ======================================================== */ + #define R_CEU_CBDSR_M_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_M_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_M ======================================================== */ + #define R_CEU_CLFCR_M_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_M_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_M ======================================================== */ + #define R_CEU_CDOCR_M_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_M_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_M_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_M_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_M_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_M_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_M ======================================================== */ + #define R_CEU_CDAYR2_M_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_M_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_M ======================================================== */ + #define R_CEU_CDACR2_M_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_M_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_M ======================================================== */ + #define R_CEU_CDBYR2_M_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_M_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_M ======================================================== */ + #define R_CEU_CDBCR2_M_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_M_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ULPTCNT ======================================================== */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Pos (0UL) /*!< ULPTCNT (Bit 0) */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Msk (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMA ======================================================== */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Pos (0UL) /*!< ULPTCMA (Bit 0) */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Msk (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMB ======================================================== */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Pos (0UL) /*!< ULPTCMB (Bit 0) */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Msk (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCR ========================================================= */ + #define R_ULPT0_ULPTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_ULPT0_ULPTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_ULPT0_ULPTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_ULPT0_ULPTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_ULPT0_ULPTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_ULPT0_ULPTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_ULPT0_ULPTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR1 ======================================================== */ + #define R_ULPT0_ULPTMR1_TMOD1_Pos (1UL) /*!< TMOD1 (Bit 1) */ + #define R_ULPT0_ULPTMR1_TMOD1_Msk (0x2UL) /*!< TMOD1 (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TCK1_Pos (5UL) /*!< TCK1 (Bit 5) */ + #define R_ULPT0_ULPTMR1_TCK1_Msk (0x20UL) /*!< TCK1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR2 ======================================================== */ + #define R_ULPT0_ULPTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_ULPT0_ULPTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_ULPT0_ULPTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_ULPT0_ULPTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR3 ======================================================== */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Pos (0UL) /*!< TCNTCTL (Bit 0) */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Msk (0x1UL) /*!< TCNTCTL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Pos (1UL) /*!< TEVPOL (Bit 1) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Msk (0x2UL) /*!< TEVPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TOPOL_Pos (2UL) /*!< TOPOL (Bit 2) */ + #define R_ULPT0_ULPTMR3_TOPOL_Msk (0x4UL) /*!< TOPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEECTL_Pos (4UL) /*!< TEECTL (Bit 4) */ + #define R_ULPT0_ULPTMR3_TEECTL_Msk (0x30UL) /*!< TEECTL (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Pos (6UL) /*!< TEEPOL (Bit 6) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Msk (0xc0UL) /*!< TEEPOL (Bitfield-Mask: 0x03) */ +/* ======================================================== ULPTIOC ======================================================== */ + #define R_ULPT0_ULPTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_ULPT0_ULPTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_ULPT0_ULPTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Pos (6UL) /*!< TIOGT0 (Bit 6) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Msk (0x40UL) /*!< TIOGT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTISR ======================================================== */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Pos (2UL) /*!< RCCPSEL2 (Bit 2) */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Msk (0x4UL) /*!< RCCPSEL2 (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPTCMSR ======================================================== */ + #define R_ULPT0_ULPTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_ULPT0_ULPTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_ULPT0_ULPTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_ULPT0_ULPTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= FSBLSTATM ======================================================= */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CONVAREAST ======================================================= */ + #define R_DOTF_CONVAREAST_CONVAREAST_Pos (12UL) /*!< CONVAREAST (Bit 12) */ + #define R_DOTF_CONVAREAST_CONVAREAST_Msk (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff) */ +/* ======================================================= CONVAREAD ======================================================= */ + #define R_DOTF_CONVAREAD_CONVAREAD_Pos (12UL) /*!< CONVAREAD (Bit 12) */ + #define R_DOTF_CONVAREAD_CONVAREAD_Msk (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= REG00 ========================================================= */ + #define R_DOTF_REG00_B09_Pos (9UL) /*!< B09 (Bit 9) */ + #define R_DOTF_REG00_B09_Msk (0x200UL) /*!< B09 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B16_Pos (16UL) /*!< B16 (Bit 16) */ + #define R_DOTF_REG00_B16_Msk (0x10000UL) /*!< B16 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B17_Pos (17UL) /*!< B17 (Bit 17) */ + #define R_DOTF_REG00_B17_Msk (0x20000UL) /*!< B17 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B20_Pos (20UL) /*!< B20 (Bit 20) */ + #define R_DOTF_REG00_B20_Msk (0x100000UL) /*!< B20 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B24_Pos (24UL) /*!< B24 (Bit 24) */ + #define R_DOTF_REG00_B24_Msk (0x3000000UL) /*!< B24 (Bitfield-Mask: 0x03) */ + #define R_DOTF_REG00_B28_Pos (28UL) /*!< B28 (Bit 28) */ + #define R_DOTF_REG00_B28_Msk (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03) */ +/* ========================================================= REG03 ========================================================= */ + #define R_DOTF_REG03_B00_Pos (0UL) /*!< B00 (Bit 0) */ + #define R_DOTF_REG03_B00_Msk (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_FLAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCKMHZ ========================================================= */ + #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */ + #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_OFS_DATAFLASH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= FSBLCTRL0 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos (0UL) /*!< FSBLEN (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Msk (0x7UL) /*!< FSBLEN (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos (3UL) /*!< FSBLSKIPSW (Bit 3) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Msk (0x38UL) /*!< FSBLSKIPSW (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos (6UL) /*!< FSBLSKIPDS (Bit 6) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Msk (0x1c0UL) /*!< FSBLSKIPDS (Bitfield-Mask: 0x07) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos (9UL) /*!< FSBLCLK (Bit 9) */ + #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Msk (0xe00UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ +/* ======================================================= FSBLCTRL1 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos (0UL) /*!< FSBLEXMD (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Msk (0x3UL) /*!< FSBLEXMD (Bitfield-Mask: 0x03) */ +/* ======================================================= FSBLCTRL2 ======================================================= */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos (0UL) /*!< PORTPN (Bit 0) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Msk (0xfUL) /*!< PORTPN (Bitfield-Mask: 0x0f) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos (4UL) /*!< PORTGN (Bit 4) */ + #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Msk (0x1f0UL) /*!< PORTGN (Bitfield-Mask: 0x1f) */ +/* ========================================================= SACC0 ========================================================= */ +/* ========================================================= SACC1 ========================================================= */ +/* ========================================================= SAMR ========================================================== */ +/* ======================================================= HOEMRTPK ======================================================== */ +/* ========================================================= ARCLS ========================================================= */ + #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Pos (0UL) /*!< ARCS_LK (Bit 0) */ + #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Msk (0x1UL) /*!< ARCS_LK (Bitfield-Mask: 0x01) */ + #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Pos (1UL) /*!< ARCNS_LK (Bit 1) */ + #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Msk (0x1eUL) /*!< ARCNS_LK (Bitfield-Mask: 0x0f) */ + #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Pos (5UL) /*!< ARCBL_LK (Bit 5) */ + #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Msk (0x20UL) /*!< ARCBL_LK (Bitfield-Mask: 0x01) */ +/* ========================================================= ARCCS ========================================================= */ + #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Pos (0UL) /*!< CNF_ARCNS (Bit 0) */ + #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Msk (0x3UL) /*!< CNF_ARCNS (Bitfield-Mask: 0x03) */ +/* ======================================================== ARC_SEC ======================================================== */ + #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Pos (0UL) /*!< ARC_SEC (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Msk (0xffffffffUL) /*!< ARC_SEC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ARC_NSEC ======================================================== */ + #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Pos (0UL) /*!< ARC_NSEC (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Msk (0xffffffffUL) /*!< ARC_NSEC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= ARC_OEMBL ======================================================= */ + #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Pos (0UL) /*!< ARC_OEMBL (Bit 0) */ + #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Msk (0xffffffffUL) /*!< ARC_OEMBL (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA8E1AF_H */ + +/** @} */ /* End of group R7FA8E1AF */ + +/** @} */ /* End of group Renesas */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core0.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core0.h new file mode 100644 index 0000000000..ea862def79 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core0.h @@ -0,0 +1,94177 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7KA8P1KF_core0.h + * @brief CMSIS HeaderFile + * @version 0.1 + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7KA8P1KF_core0 + * @{ + */ + +#ifndef R7KA8P1KF_CORE0_H + #define R7KA8P1KF_CORE0_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M85 Processor and Core Peripherals =========================== */ + #define __CM85_REV 0x0002U /*!< CM85 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */ + #define __DCACHE_PRESENT 1 /*!< Data Cache present */ + #define __SAUREGION_PRESENT 1 /*!< SAU region present */ + #define __PMU_PRESENT 1 /*!< PMU present */ + #define __PMU_NUM_EVENTCNT 8 /*!< PMU Event Counters */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm85.h" /*!< ARM Cortex-M85 processor and core peripherals */ + #include "system.h" /*!< R7KA8P1KF_core0 System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000004) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint8_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint8_t : 7; + } IRQEN_b; + }; + __IM uint8_t RESERVED2[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000080) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000088) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000090) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 148 (0x94) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED[3]; +} R_ELC_ELSEGR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..52]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 10; /*!< [9..0] Event Link Select */ + uint16_t : 6; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; + }; + + union + { + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ + + struct + { + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; + }; + + union + { + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position + * Register */ + + struct + { + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; + }; + + union + { + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; + }; + + union + { + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + } HSIZE_b; + }; + + union + { + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; + }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ + +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + + struct + { + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; + }; + + union + { + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + + struct + { + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; + }; + + union + { + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + + struct + { + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; + }; + + union + { + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + + struct + { + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; + }; + + union + { + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + + struct + { + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; + }; + + union + { + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + + struct + { + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; + }; + + union + { + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + + struct + { + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; + }; + + union + { + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + + struct + { + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; + }; + + union + { + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + + struct + { + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; + }; + + union + { + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + + struct + { + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; + }; + + union + { + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + + struct + { + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; + }; + + union + { + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + + struct + { + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; + }; + + union + { + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + + struct + { + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; + }; + + union + { + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + + struct + { + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; + }; + + union + { + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + + struct + { + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + + struct + { + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; + }; + + union + { + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + + struct + { + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + + struct + { + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; + }; + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + */ +typedef struct +{ + union + { + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; + }; + + union + { + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + + struct + { + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; + }; + + union + { + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; + }; + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control + * Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; + }; + + union + { + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + + struct + { + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; + }; + + union + { + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ + + struct + { + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; + }; + + union + { + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ + + struct + { + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; + }; + + union + { + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + + struct + { + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; + }; + + union + { + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ + + struct + { + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; + }; +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + + struct + { + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; + + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; + }; + + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; + + union + { + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; + }; + + union + { + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; + }; + + union + { + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; + }; + + union + { + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; + }; + + union + { + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; + + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; + }; + + union + { + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + + struct + { + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; + }; +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ + +/** + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ + + struct + { + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; + }; + + union + { + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ + + struct + { + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; + }; + + union + { + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + + struct + { + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; + }; + + union + { + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + + struct + { + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; + }; + + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ + + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint32_t : 1; + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint16_t : 1; + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint8_t : 1; + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_XSPI0_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration register 0 */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode */ + __IOM uint32_t ARYAMD : 1; /*!< [5..5] Array address mode */ + uint32_t : 10; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration register 1 */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration register 2 */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CMCFGCS_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CDBUF [CDBUF] (xSPI BUF register) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2byte) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_CDBUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CCCTLCS [CCCTLCS] (xSPI CS register) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control register 0 */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control register 1 */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control register 2 */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3 */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control register 4 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control register 5 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control register 6 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CCCTLCS_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_COMA_CABPPPFLC [CABPPPFLC] ([0..2]) + */ +typedef struct +{ + union + { + __IOM uint32_t LEVEL0; /*!< (@ 0x00000000) Port 0 Buffer Pointer Pause Frame Level 0 Configuration + * Register */ + + struct + { + __IOM uint32_t PPDL : 10; /*!< [9..0] Pause De-Assertion Level */ + uint32_t : 6; + __IOM uint32_t PPAL : 10; /*!< [25..16] Pause Assertion Level */ + uint32_t : 6; + } LEVEL0_b; + }; + + union + { + __IOM uint32_t LEVEL1; /*!< (@ 0x00000004) Port 0 Buffer Pointer Pause Frame Level 1 Configuration + * Register */ + + struct + { + __IOM uint32_t PPDL : 10; /*!< [9..0] Pause De-Assertion Level */ + uint32_t : 6; + __IOM uint32_t PPAL : 10; /*!< [25..16] Pause Assertion Level */ + uint32_t : 6; + } LEVEL1_b; + }; +} R_COMA_CABPPPFLC_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_IPC_IPCNMI [IPCNMI] (Inter-Processor NMI Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STA; /*!< (@ 0x00000000) NMI Request Status Register */ + + struct + { + __IM uint32_t NMI : 1; /*!< [0..0] Status of the interrupt request */ + uint32_t : 31; + } STA_b; + }; + + union + { + __OM uint32_t SET; /*!< (@ 0x00000004) NMI Request Set Register */ + + struct + { + __OM uint32_t SET : 1; /*!< [0..0] Sets the NMI request */ + uint32_t : 31; + } SET_b; + }; + + union + { + __OM uint32_t CLR; /*!< (@ 0x00000008) NMI Request Clear Register */ + + struct + { + __OM uint32_t CLR : 1; /*!< [0..0] Clears the NMI request */ + uint32_t : 31; + } CLR_b; + }; + __IM uint32_t RESERVED; +} R_IPC_IPCNMI_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_IPC_IPC_CH [CH] (Inter-Processor Communications Channel Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STA; /*!< (@ 0x00000000) Inter-Processor Status Register */ + + struct + { + __IM uint32_t IRQ0 : 1; /*!< [0..0] Indicates the status of the interrupt request */ + __IM uint32_t IRQ1 : 1; /*!< [1..1] Indicates the status of the interrupt request */ + __IM uint32_t IRQ2 : 1; /*!< [2..2] Indicates the status of the interrupt request */ + __IM uint32_t IRQ3 : 1; /*!< [3..3] Indicates the status of the interrupt request */ + __IM uint32_t IRQ4 : 1; /*!< [4..4] Indicates the status of the interrupt request */ + __IM uint32_t IRQ5 : 1; /*!< [5..5] Indicates the status of the interrupt request */ + __IM uint32_t IRQ6 : 1; /*!< [6..6] Indicates the status of the interrupt request */ + __IM uint32_t IRQ7 : 1; /*!< [7..7] Indicates the status of the interrupt request */ + uint32_t : 8; + __IM uint32_t RDY : 1; /*!< [16..16] This bit is set when FIFO is not empty */ + __IM uint32_t FULL : 1; /*!< [17..17] FIFO is full */ + uint32_t : 6; + __IM uint32_t RERR : 1; /*!< [24..24] Indicates that the message FIFO 00 tried to read Data + * despite Empty */ + __IM uint32_t FERR : 1; /*!< [25..25] Indicates that the message FIFO 00 tried to send more + * data even though it was full */ + uint32_t : 6; + } STA_b; + }; + + union + { + __OM uint32_t SET; /*!< (@ 0x00000004) Inter-Processor IRQ Request Set Register */ + + struct + { + __OM uint32_t SET0 : 1; /*!< [0..0] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET1 : 1; /*!< [1..1] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET2 : 1; /*!< [2..2] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET3 : 1; /*!< [3..3] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET4 : 1; /*!< [4..4] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET5 : 1; /*!< [5..5] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET6 : 1; /*!< [6..6] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET7 : 1; /*!< [7..7] Sets IPCmSTA0.IRQn */ + uint32_t : 24; + } SET_b; + }; + + union + { + __OM uint32_t TXD; /*!< (@ 0x00000008) Inter-Processor FIFO Transfer Data Register */ + + struct + { + __OM uint32_t TXD : 32; /*!< [31..0] Transfer data */ + } TXD_b; + }; + + union + { + __IM uint32_t RXD; /*!< (@ 0x0000000C) Inter-Processor FIFO Receive Data Register */ + + struct + { + __IM uint32_t RXD : 32; /*!< [31..0] Receive data */ + } RXD_b; + }; + + union + { + __OM uint32_t CLR; /*!< (@ 0x00000010) Inter-Processor Clear Register */ + + struct + { + __OM uint32_t CLR0 : 1; /*!< [0..0] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR1 : 1; /*!< [1..1] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR2 : 1; /*!< [2..2] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR3 : 1; /*!< [3..3] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR4 : 1; /*!< [4..4] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR5 : 1; /*!< [5..5] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR6 : 1; /*!< [6..6] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR7 : 1; /*!< [7..7] Clears the interrupt request for IPCmSTA0.IRQn */ + uint32_t : 8; + __OM uint32_t RST : 1; /*!< [16..16] Resets message FIFO */ + uint32_t : 7; + __OM uint32_t RCLR : 1; /*!< [24..24] Resets IPCmSTA0.RERR */ + __OM uint32_t FCLR : 1; /*!< [25..25] Resets IPCmSTA0.FERR */ + uint32_t : 6; + } CLR_b; + }; + __IM uint32_t RESERVED[3]; +} R_IPC_IPC_CH_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_IPC_IPC [IPC] (Inter-Processor Registers) + */ +typedef struct +{ + __IOM R_IPC_IPC_CH_Type CH[2]; /*!< (@ 0x00000000) Inter-Processor Communications Channel Registers */ +} R_IPC_IPC_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PDM_CH [CH] (PDM Channel-Specific Registers) + */ +typedef struct +{ + union + { + __OM uint32_t PDSTRTR; /*!< (@ 0x00000000) Software Start Trigger Register */ + + struct + { + __OM uint32_t STRTRG : 1; /*!< [0..0] Start trigger */ + uint32_t : 31; + } PDSTRTR_b; + }; + + union + { + __OM uint32_t PDSTPTR; /*!< (@ 0x00000004) Software Stop Trigger Register */ + + struct + { + __OM uint32_t STPTRG : 1; /*!< [0..0] Stop trigger */ + uint32_t : 31; + } PDSTPTR_b; + }; + + union + { + __OM uint32_t PDCHGTR; /*!< (@ 0x00000008) Software Change Trigger Register */ + + struct + { + __OM uint32_t CHGTRG : 1; /*!< [0..0] Change trigger */ + uint32_t : 31; + } PDCHGTR_b; + }; + + union + { + __IOM uint32_t PDICR; /*!< (@ 0x0000000C) Interrupt Control Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t ISDE : 1; /*!< [1..1] Sound detection interrupt enable bit */ + __IOM uint32_t IDRE : 1; /*!< [2..2] Data reception interrupt enable bit */ + uint32_t : 13; + __IOM uint32_t IEDE : 1; /*!< [16..16] Error detection interrupt enable bit */ + uint32_t : 15; + } PDICR_b; + }; + + union + { + __IOM uint32_t PDSDCR; /*!< (@ 0x00000010) Status Detection Control Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t SDE : 1; /*!< [1..1] Sound detection enable bit */ + uint32_t : 14; + __IOM uint32_t SCDE : 1; /*!< [16..16] Short circuit detection enable bit */ + __IOM uint32_t OVLDE : 1; /*!< [17..17] Overvoltage lower limit exceeded detection enable bit */ + __IOM uint32_t OVUDE : 1; /*!< [18..18] Overvoltage upper limit exceeded detection enable bit */ + uint32_t : 8; + __IOM uint32_t BFOWDE : 1; /*!< [27..27] Buffer overwriting detection enable bit */ + uint32_t : 4; + } PDSDCR_b; + }; + + union + { + __IM uint32_t PDSR; /*!< (@ 0x00000014) Status Register */ + + struct + { + __IM uint32_t STATE : 1; /*!< [0..0] State */ + __IM uint32_t SDF : 1; /*!< [1..1] Sound detection flag */ + __IM uint32_t DRF : 1; /*!< [2..2] Data reception flag */ + uint32_t : 13; + __IM uint32_t SCDF : 1; /*!< [16..16] Short circuit detection flag */ + __IM uint32_t OVLDF : 1; /*!< [17..17] Overvoltage lower limit exceeded detection flag */ + __IM uint32_t OVUDF : 1; /*!< [18..18] Overvoltage upper limit exceeded detection flag */ + uint32_t : 8; + __IM uint32_t BFOWDF : 1; /*!< [27..27] Buffer overwriting detection flag */ + uint32_t : 4; + } PDSR_b; + }; + + union + { + __OM uint32_t PDSCR; /*!< (@ 0x00000018) Status Clear Register */ + + struct + { + uint32_t : 1; + __OM uint32_t SDFC : 1; /*!< [1..1] Sound detection flag clear */ + uint32_t : 14; + __OM uint32_t SCDFC : 1; /*!< [16..16] Short circuit detection flag clear */ + __OM uint32_t OVLDFC : 1; /*!< [17..17] Overvoltage lower limit exceeded detection flag clear */ + __OM uint32_t OVUDFC : 1; /*!< [18..18] Overvoltage upper limit exceeded detection flag clear */ + uint32_t : 8; + __OM uint32_t BFOWDFC : 1; /*!< [27..27] Buffer overwriting detection flag clear */ + uint32_t : 4; + } PDSCR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PDMDSR; /*!< (@ 0x00000020) Mode Setting Register */ + + struct + { + __IOM uint32_t INPSEL : 1; /*!< [0..0] Input data select */ + uint32_t : 3; + __IOM uint32_t SFMD : 3; /*!< [6..4] Sinc filter mode setting */ + uint32_t : 1; + __IOM uint32_t HFIS : 2; /*!< [9..8] High-pass filter input shift setting */ + uint32_t : 2; + __IOM uint32_t CFIS : 2; /*!< [13..12] Compensation filter input shift setting */ + uint32_t : 2; + __IOM uint32_t LFIS : 2; /*!< [17..16] Low-pass (half-band decimation) filter input shift + * setting */ + uint32_t : 6; + __IOM uint32_t SDMAMD : 2; /*!< [25..24] Moving average mode for sound detection data */ + uint32_t : 2; + __IOM uint32_t DBIS : 4; /*!< [31..28] Data buffer input shift setting */ + } PDMDSR_b; + }; + + union + { + __IOM uint32_t PDSFCR; /*!< (@ 0x00000024) Sinc filter Control Register */ + + struct + { + __IOM uint32_t CKDIV : 4; /*!< [3..0] PDM_CLKn's dividend ratio to core clock */ + uint32_t : 12; + __IOM uint32_t SINCDEC : 8; /*!< [23..16] Sinc filter decimation ratio */ + __IOM uint32_t SINCRNG : 5; /*!< [28..24] Sinc filter output valid range */ + uint32_t : 3; + } PDSFCR_b; + }; + + union + { + __IOM uint32_t PDHFCS0R; /*!< (@ 0x00000028) High-pass filter Coefficient s(0) Register */ + + struct + { + __IOM uint32_t HFS0 : 16; /*!< [15..0] High-pass filter coefficient s(0) */ + uint32_t : 16; + } PDHFCS0R_b; + }; + + union + { + __IOM uint32_t PDHFCK1R; /*!< (@ 0x0000002C) High-pass filter Coefficient k(1) Register */ + + struct + { + __IOM uint32_t HFK1 : 16; /*!< [15..0] High-pass filter coefficient k(1) */ + uint32_t : 16; + } PDHFCK1R_b; + }; + + union + { + __IOM uint32_t PDHFCHR[2]; /*!< (@ 0x00000030) High-pass filter Coefficient h([0..1]) Registers */ + + struct + { + __IOM uint32_t HFHn : 16; /*!< [15..0] High-pass filter coefficient h(n) */ + uint32_t : 16; + } PDHFCHR_b[2]; + }; + + union + { + __IOM uint32_t PDCFCHR[11]; /*!< (@ 0x00000038) Compensation filter Coefficient h([0..10]) Registers */ + + struct + { + __IOM uint32_t CFHn : 13; /*!< [12..0] Compensation filter coefficient h(n) */ + uint32_t : 19; + } PDCFCHR_b[11]; + }; + + union + { + __IOM uint32_t PDLFCH010R; /*!< (@ 0x00000064) Low-pass filter Coefficient h0(10) Register */ + + struct + { + __IOM uint32_t LFH010 : 13; /*!< [12..0] Low-pass (half-band decimation) filter coefficient h0(10) */ + uint32_t : 19; + } PDLFCH010R_b; + }; + + union + { + __IOM uint32_t PDLFCH1R[20]; /*!< (@ 0x00000068) Low-pass filter Coefficient h1([0..19]) Registers */ + + struct + { + __IOM uint32_t LFH1n : 13; /*!< [12..0] Low-pass (half-band decimation) filter coefficient h1(n) */ + uint32_t : 19; + } PDLFCH1R_b[20]; + }; + + union + { + __IOM uint32_t PDSDLTR; /*!< (@ 0x000000B8) Sound Detection Lower Threshold Register */ + + struct + { + __IOM uint32_t SDETL : 20; /*!< [19..0] Sound detection lower limit */ + uint32_t : 12; + } PDSDLTR_b; + }; + + union + { + __IOM uint32_t PDSDUTR; /*!< (@ 0x000000BC) Sound Detection Upper Threshold Register */ + + struct + { + __IOM uint32_t SDETU : 20; /*!< [19..0] Sound detection upper limit */ + uint32_t : 12; + } PDSDUTR_b; + }; + + union + { + __IOM uint32_t PDDBCR; /*!< (@ 0x000000C0) Data Buffer Control Register */ + + struct + { + __IOM uint32_t DATRITHR : 3; /*!< [2..0] Data reception interrupt threshold */ + uint32_t : 29; + } PDDBCR_b; + }; + + union + { + __IOM uint32_t PDSCTSR; /*!< (@ 0x000000C4) Short Circuit Threshold Setting Register */ + + struct + { + __IOM uint32_t SCDL : 13; /*!< [12..0] Short circuit detection Low Continuous detection count */ + uint32_t : 3; + __IOM uint32_t SCDH : 13; /*!< [28..16] Short circuit detection High Continuous detection count */ + uint32_t : 3; + } PDSCTSR_b; + }; + + union + { + __IOM uint32_t PDOVLTR; /*!< (@ 0x000000C8) Overvoltage Lower Threshold Register */ + + struct + { + __IOM uint32_t OVDL : 20; /*!< [19..0] Overvoltage detection lower limit */ + uint32_t : 12; + } PDOVLTR_b; + }; + + union + { + __IOM uint32_t PDOVUTR; /*!< (@ 0x000000CC) Overvoltage Upper Threshold Register */ + + struct + { + __IOM uint32_t OVDU : 20; /*!< [19..0] Overvoltage detection upper limit */ + uint32_t : 12; + } PDOVUTR_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t PDDRCR; /*!< (@ 0x000000E0) Data Read Control Register */ + + struct + { + __IOM uint32_t DATRE : 1; /*!< [0..0] Data read enable bit */ + uint32_t : 31; + } PDDRCR_b; + }; + + union + { + __OM uint32_t PDDCR; /*!< (@ 0x000000E4) Data Clear Register */ + + struct + { + __OM uint32_t DATC : 1; /*!< [0..0] Data clear */ + uint32_t : 31; + } PDDCR_b; + }; + + union + { + __IM uint32_t PDDRR; /*!< (@ 0x000000E8) Data Read Register */ + + struct + { + __IM uint32_t DAT : 20; /*!< [19..0] Data */ + uint32_t : 12; + } PDDRR_b; + }; + + union + { + __IM uint32_t PDDSR; /*!< (@ 0x000000EC) Data Status Register */ + + struct + { + __IM uint32_t DATNUM : 8; /*!< [7..0] Number of data stored in buffer */ + uint32_t : 24; + } PDDSR_b; + }; + __IM uint32_t RESERVED2[4]; +} R_PDM_CH_Type; /*!< Size = 256 (0x100) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x40204000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ + } MSSAR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARB_b; + }; + + union + { + __IOM uint32_t PPARC; /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C */ + + struct + { + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARC_b; + }; + + union + { + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARD_b; + }; + + union + { + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARE_b; + }; + + union + { + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } MSPAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code MRAM Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Secure area */ + uint32_t : 8; + } CFSAMONA_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; + + union + { + __IM uint32_t SFSAMON; /*!< (@ 0x0000003C) SiP Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t SFS : 9; /*!< [23..15] SiP Flash Secure Area */ + uint32_t : 8; + } SFSAMON_b; + }; +} R_PSCU_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[27]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6924 (0x1b0c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40202400) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40310000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit D/A converter (R_DAC_B0) + */ + +typedef struct /*!< (@ 0x40233000) R_DAC_B0 Structure */ +{ + union + { + __IOM uint16_t DADR; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A converted data */ + } DADR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t DACR0; /*!< (@ 0x00000004) D/A Control Register 0 */ + + struct + { + __IOM uint32_t DACEN : 1; /*!< [0..0] DA enable bit */ + uint32_t : 14; + __IOM uint32_t DAE : 1; /*!< [15..15] DA batch conversion control bit */ + uint32_t : 15; + __IOM uint32_t DAOUTDIS : 1; /*!< [31..31] Analog output disable bit */ + } DACR0_b; + }; + + union + { + __IOM uint32_t DACR1; /*!< (@ 0x00000008) D/A Control Register 1 */ + + struct + { + uint32_t : 16; + __IOM uint32_t DPSEL : 1; /*!< [16..16] Data placement selection bit */ + uint32_t : 15; + } DACR1_b; + }; + + union + { + __IOM uint32_t DACR2; /*!< (@ 0x0000000C) D/A Control Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t OFSSEL : 1; /*!< [8..8] DAC-HM operating voltage mode select bit */ + uint32_t : 23; + } DACR2_b; + }; +} R_DAC_B0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT1 : 1; /*!< [2..2] Mask bit for WDT1 reset/interrupt in the OCD run mode */ + uint32_t : 11; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + __IOM uint32_t DBGSTOP_NVMERR : 1; /*!< [26..26] Mask bit for MRAM ECC error reset/interrupt */ + uint32_t : 1; + __IOM uint32_t DBGSTOP_CTERR0 : 1; /*!< [28..28] Mask bit for CPU0's Cache/TCM ECC error reset */ + __IOM uint32_t DBGSTOP_CTERR1 : 1; /*!< [29..29] This bit is reserved. It can be R/W but no effect */ + uint32_t : 1; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DBGAUTH0; /*!< (@ 0x00000020) Debug Authentication Control Register0 */ + + struct + { + __IOM uint32_t DBGEN0 : 1; /*!< [0..0] CPU0 invasive debug enable */ + __IOM uint32_t DBGEN1 : 1; /*!< [1..1] CPU1 invasive debug enable */ + uint32_t : 2; + __IOM uint32_t NIDEN0 : 1; /*!< [4..4] CPU0 non-invasive debug enable */ + __IOM uint32_t NIDEN1 : 1; /*!< [5..5] CPU1 non-invasive debug enable */ + uint32_t : 10; + __IOM uint32_t DEVICEEN : 1; /*!< [16..16] APB-AP (AP1) authentication */ + uint32_t : 14; + __IM uint32_t SWDBG : 1; /*!< [31..31] Software control of debug function */ + } DBGAUTH0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t TRPORTCR; /*!< (@ 0x00000030) Trace Port Control Register */ + + struct + { + __IOM uint32_t OE : 1; /*!< [0..0] Data Out Enable bit indicates whether Trace Clock, Trace + * Data and SWO outputs are enabled or not. */ + uint32_t : 1; + __IOM uint32_t DRV : 2; /*!< [3..2] Port Drive Capability Control indicate trace port buffer + * speed */ + uint32_t : 4; + __IOM uint32_t PORTSEL : 2; /*!< [9..8] None */ + uint32_t : 6; + __IOM uint32_t SWOSEL : 1; /*!< [16..16] Select SWO between CPU0 and CPU1 */ + uint32_t : 15; + } TRPORTCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t TRPORTSZ; /*!< (@ 0x00000038) Trace Port Size Control Register */ + + struct + { + __IOM uint32_t PORTSIZE : 32; /*!< [31..0] Indicates how many pins of TRACEDATA are available. */ + } TRPORTSZ_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t CACHEDBGCR; /*!< (@ 0x00000040) Cache Debug Control Register */ + + struct + { + __IOM uint32_t L1RSTDIS : 1; /*!< [0..0] Disable L1 cache automatic invalidation of CPU0 */ + uint32_t : 31; + } CACHEDBGCR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t DBGNVMCR; /*!< (@ 0x00000050) Debug Non-volatile Memory Control Register */ + + struct + { + __IOM uint32_t NVMWE : 1; /*!< [0..0] Non-volatile memory write enable */ + uint32_t : 31; + } DBGNVMCR_b; + }; + __IM uint32_t RESERVED6[43]; + + union + { + __IOM uint32_t ALCTRL; /*!< (@ 0x00000100) Authentication Level Control Register */ + + struct + { + __IOM uint32_t AL : 8; /*!< [7..0] AL monitor */ + uint32_t : 22; + __IOM uint32_t FAILCNT : 2; /*!< [31..30] Number of times responding incorrect response data */ + } ALCTRL_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x4000A800) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x4000A000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x40444000) R_DRW Structure */ +{ + union + { + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ + + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; + }; + + union + { + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union + { + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; + }; + __IM uint32_t RESERVED[2]; + + union + { + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; + }; + + union + { + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; + }; + + union + { + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; + }; + + union + { + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; + }; + + union + { + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; + }; + + union + { + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; + }; + + union + { + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; + }; + + union + { + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; + }; + + union + { + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; + }; + + union + { + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; + }; + + union + { + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; + }; + + union + { + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; + }; + + union + { + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; + }; + + union + { + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; + }; + + union + { + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; + }; + + union + { + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; + }; + + union + { + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; + }; + + union + { + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; + }; + + union + { + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; + }; + + union + { + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; + }; + __IM uint32_t RESERVED1; + + union + { + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + + struct + { + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; + }; + + union + { + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + + struct + { + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + + struct + { + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; + }; + + union + { + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + + struct + { + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; + }; + + union + { + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + + struct + { + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; + + union + { + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + + struct + { + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + + struct + { + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; + }; + + union + { + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + + struct + { + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; + }; + + union + { + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + + struct + { + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; + }; + + union + { + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + + struct + { + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; + }; + + union + { + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + + struct + { + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; + }; + + union + { + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; + }; + + union + { + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; + }; + + union + { + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + + struct + { + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + + struct + { + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; + }; + + union + { + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + + struct + { + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; + }; + + union + { + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + + struct + { + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; + }; + + union + { + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + + struct + { + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; + }; + + union + { + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + + struct + { + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; + }; + + union + { + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + + struct + { + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; + }; + + union + { + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; + }; + + union + { + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; + }; + + union + { + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + + struct + { + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + + struct + { + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; + }; + + union + { + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + + struct + { + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; + }; + + union + { + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + + struct + { + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; + }; + + union + { + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + + struct + { + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t DBWER; /*!< (@ 0x00000100) DRW Bufferable Write Enable Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t BWE : 1; /*!< [2..2] Bufferable Write Enable */ + uint32_t : 29; + } DBWER_b; + }; +} R_DRW_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x4000AC00) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40201000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IOM R_ELC_ELSEGR_Type ELSEGR[4]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */ + __IM uint32_t RESERVED2[3]; + __IOM R_ELC_ELSR_Type ELSR[53]; /*!< (@ 0x00000020) Event Link Setting Register [0..52] */ + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t ELCSARA; /*!< (@ 0x00000100) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Security + * Attribution */ + __IOM uint32_t ELSEGR2 : 1; /*!< [3..3] Event Link Software Event Generation Register 2 Security + * Attribution */ + __IOM uint32_t ELSEGR3 : 1; /*!< [4..4] Event Link Software Event Generation Register 3 Security + * Attribution */ + uint32_t : 27; + } ELCSARA_b; + }; + + union + { + __IOM uint32_t ELCSARB; /*!< (@ 0x00000104) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Security Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Security Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Security Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Security Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Security Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Security Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Security Attribution */ + } ELCSARB_b; + }; + + union + { + __IOM uint32_t ELCSARC; /*!< (@ 0x00000108) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Security Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Security Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Security Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Security Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Security Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Security Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Security Attribution */ + } ELCSARC_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ELCPARA; /*!< (@ 0x00000110) Event Link Controller Privilege Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller Register Privilege Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Privilege + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Privilege + * Attribution */ + __IOM uint32_t ELSEGR2 : 1; /*!< [3..3] Event Link Software Event Generation Register 2 Privilege + * Attribution */ + __IOM uint32_t ELSEGR3 : 1; /*!< [4..4] Event Link Software Event Generation Register 3 Privilege + * Attribution */ + uint32_t : 27; + } ELCPARA_b; + }; + + union + { + __IOM uint32_t ELCPARB; /*!< (@ 0x00000114) Event Link Controller Privilege Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Privilege Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Privilege Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Privilege Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Privilege Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Privilege Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Privilege Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Privilege Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Privilege Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Privilege Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Privilege Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Privilege Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Privilege Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Privilege Attribution */ + } ELCPARB_b; + }; + + union + { + __IOM uint32_t ELCPARC; /*!< (@ 0x00000118) Event Link Controller Privilege Attribution Register + * C */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Privilege Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Privilege Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Privilege Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Privilege Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Privilege Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Privilege Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Privilege Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Privilege Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Privilege Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Privilege Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Privilege Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Privilege Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Privilege Attribution */ + } ELCPARC_b; + }; +} R_ELC_Type; /*!< Size = 284 (0x11c) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x40342000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40322000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GTCLK (R_GPT_GTCLK) + */ + +typedef struct /*!< (@ 0x40323F10) R_GPT_GTCLK Structure */ +{ + union + { + __IOM uint32_t GTCLKCR; /*!< (@ 0x00000000) General PWM Timer Clock Control Register */ + + struct + { + __IOM uint32_t BPEN : 1; /*!< [0..0] Synchronization Circuit Bypass Enable */ + uint32_t : 31; + } GTCLKCR_b; + }; +} R_GPT_GTCLK_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x40324000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCRa[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCRa_b[16]; + }; + + union + { + __IM uint8_t NMICR; /*!< (@ 0x00000010) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t IRQCRb[16]; /*!< (@ 0x00000014) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCRb_b[16]; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IOM uint32_t INTSELR[32]; /*!< (@ 0x00000040) Interrupt request select Register */ + + struct + { + __IOM uint32_t IS0 : 1; /*!< [0..0] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS16 : 1; /*!< [16..16] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS17 : 1; /*!< [17..17] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS18 : 1; /*!< [18..18] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS19 : 1; /*!< [19..19] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS20 : 1; /*!< [20..20] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS21 : 1; /*!< [21..21] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS22 : 1; /*!< [22..22] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS23 : 1; /*!< [23..23] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS24 : 1; /*!< [24..24] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS25 : 1; /*!< [25..25] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS26 : 1; /*!< [26..26] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS27 : 1; /*!< [27..27] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS28 : 1; /*!< [28..28] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS29 : 1; /*!< [29..29] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS30 : 1; /*!< [30..30] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS31 : 1; /*!< [31..31] Selects which CPU receives interrupt requests */ + } INTSELR_b[32]; + }; + __IM uint32_t RESERVED3[6160]; + + union + { + __IOM uint32_t NMIER; /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint32_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint32_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint32_t PVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint32_t PVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t SOSTEN : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Enable */ + __IOM uint32_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint32_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t BUSEN : 1; /*!< [12..12] BUS error Interrupt Enable */ + __IOM uint32_t CMEN : 1; /*!< [13..13] Common Memory error Interrupt Enable */ + __IOM uint32_t LMEN : 1; /*!< [14..14] Local Memory Error Interrupt Enable */ + __IOM uint32_t LUEN : 1; /*!< [15..15] LockUp Interrupt Enable */ + __IOM uint32_t FPUFLTEN : 1; /*!< [16..16] FPU FAULT Interrupt Enable */ + __IOM uint32_t MRCRDEN : 1; /*!< [17..17] MRAM MRC read Error Interrupt Enable */ + __IOM uint32_t MRERDEN : 1; /*!< [18..18] MRAM MRE read Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t IPCEN : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Enable */ + uint32_t : 11; + } NMIER_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t NMICLR; /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __IOM uint32_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __IOM uint32_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __IOM uint32_t PVD1CLR : 1; /*!< [2..2] PVD1 Clear */ + __IOM uint32_t PVD2CLR : 1; /*!< [3..3] PVD2 Clear */ + uint32_t : 1; + __IOM uint32_t SOSTCLR : 1; /*!< [5..5] Sub OST Clear */ + __IOM uint32_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __IOM uint32_t NMICLR : 1; /*!< [7..7] NMI Clear */ + uint32_t : 4; + __IOM uint32_t BUSCLR : 1; /*!< [12..12] Bus Clear */ + __IOM uint32_t CMCLR : 1; /*!< [13..13] CM Clear */ + __IOM uint32_t LMCLR : 1; /*!< [14..14] LM Clear */ + __IOM uint32_t LUCLR : 1; /*!< [15..15] LU Clear */ + __IOM uint32_t FPUFLTCLR : 1; /*!< [16..16] FPU FAULT Clear */ + __IOM uint32_t MRCRDCLR : 1; /*!< [17..17] MRAM MRC read Error Interrupt Clear */ + __IOM uint32_t MRERDCLR : 1; /*!< [18..18] MRAM MRE read Error Interrupt Clear */ + uint32_t : 1; + __IOM uint32_t IPCCLR : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Clear */ + uint32_t : 11; + } NMICLR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IM uint32_t NMISR; /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint32_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint32_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint32_t PVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint32_t PVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t SOSTST : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + uint32_t : 4; + __IM uint32_t BUSST : 1; /*!< [12..12] BUS error Interrupt Status Flag */ + __IM uint32_t CMST : 1; /*!< [13..13] Common Memory error Interrupt Status Flag */ + __IM uint32_t LMST : 1; /*!< [14..14] Local Memory Error Interrupt Status Flag */ + __IM uint32_t LUST : 1; /*!< [15..15] LockUp Interrupt Status Flag */ + __IM uint32_t FPUFLTST : 1; /*!< [16..16] FPU FAULT Interrupt Status Flag */ + __IM uint32_t MRCRDST : 1; /*!< [17..17] MRAM MRC read Error Interrupt Status Flag */ + __IM uint32_t MRERDST : 1; /*!< [18..18] MRAM MRE read Error Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t IPCST : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Status Flag */ + uint32_t : 11; + } NMISR_b; + }; + __IM uint32_t RESERVED6[31]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t WUPEN0 : 1; /*!< [16..16] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 0 */ + __IOM uint32_t WUPEN1 : 1; /*!< [17..17] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 1 */ + __IOM uint32_t WUPEN2 : 1; /*!< [18..18] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 2 */ + __IOM uint32_t WUPEN3 : 1; /*!< [19..19] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 3 */ + __IOM uint32_t WUPEN4 : 1; /*!< [20..20] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 4 */ + __IOM uint32_t WUPEN5 : 1; /*!< [21..21] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 5 */ + __IOM uint32_t WUPEN6 : 1; /*!< [22..22] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 6 */ + __IOM uint32_t WUPEN7 : 1; /*!< [23..23] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 7 */ + __IOM uint32_t WUPEN8 : 1; /*!< [24..24] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 8 */ + __IOM uint32_t WUPEN9 : 1; /*!< [25..25] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 9 */ + __IOM uint32_t WUPEN10 : 1; /*!< [26..26] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 10 */ + __IOM uint32_t WUPEN11 : 1; /*!< [27..27] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 11 */ + __IOM uint32_t WUPEN12 : 1; /*!< [28..28] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 12 */ + __IOM uint32_t WUPEN13 : 1; /*!< [29..29] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 13 */ + __IOM uint32_t WUPEN14 : 1; /*!< [30..30] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 14 */ + __IOM uint32_t WUPEN15 : 1; /*!< [31..31] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 15 */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t WUPEN16 : 1; /*!< [0..0] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 16 */ + __IOM uint32_t WUPEN17 : 1; /*!< [1..1] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 17 */ + __IOM uint32_t WUPEN18 : 1; /*!< [2..2] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 18 */ + __IOM uint32_t WUPEN19 : 1; /*!< [3..3] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 19 */ + __IOM uint32_t WUPEN20 : 1; /*!< [4..4] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 20 */ + __IOM uint32_t WUPEN21 : 1; /*!< [5..5] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 21 */ + __IOM uint32_t WUPEN22 : 1; /*!< [6..6] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 22 */ + __IOM uint32_t WUPEN23 : 1; /*!< [7..7] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 23 */ + __IOM uint32_t WUPEN24 : 1; /*!< [8..8] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 24 */ + __IOM uint32_t WUPEN25 : 1; /*!< [9..9] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 25 */ + __IOM uint32_t WUPEN26 : 1; /*!< [10..10] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 26 */ + __IOM uint32_t WUPEN27 : 1; /*!< [11..11] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 27 */ + __IOM uint32_t WUPEN28 : 1; /*!< [12..12] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 28 */ + __IOM uint32_t WUPEN29 : 1; /*!< [13..13] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 29 */ + __IOM uint32_t WUPEN30 : 1; /*!< [14..14] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 30 */ + __IOM uint32_t WUPEN31 : 1; /*!< [15..15] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 31 */ + __IOM uint32_t IRQWUPEN16 : 1; /*!< [16..16] IRQ16 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN17 : 1; /*!< [17..17] IRQ17 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN18 : 1; /*!< [18..18] IRQ18 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN19 : 1; /*!< [19..19] IRQ19 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN20 : 1; /*!< [20..20] IRQ20 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN21 : 1; /*!< [21..21] IRQ21 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN22 : 1; /*!< [22..22] IRQ22 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN23 : 1; /*!< [23..23] IRQ23 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN24 : 1; /*!< [24..24] IRQ24 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN25 : 1; /*!< [25..25] IRQ25 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN26 : 1; /*!< [26..26] IRQ26 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN27 : 1; /*!< [27..27] IRQ27 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN28 : 1; /*!< [28..28] IRQ28 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN29 : 1; /*!< [29..29] IRQ29 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN30 : 1; /*!< [30..30] IRQ30 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN31 : 1; /*!< [31..31] IRQ31 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + } WUPEN1_b; + }; + __IM uint32_t RESERVED7[26]; + + union + { + __IOM uint32_t DSLPWUPIRQEN[3]; /*!< (@ 0x00006210) Deep Sleep Wake Up IRQ Enable Register */ + + struct + { + __IOM uint32_t IRQ0 : 1; /*!< [0..0] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ1 : 1; /*!< [1..1] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ2 : 1; /*!< [2..2] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ3 : 1; /*!< [3..3] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ4 : 1; /*!< [4..4] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ5 : 1; /*!< [5..5] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ6 : 1; /*!< [6..6] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ7 : 1; /*!< [7..7] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ8 : 1; /*!< [8..8] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ9 : 1; /*!< [9..9] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ10 : 1; /*!< [10..10] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ11 : 1; /*!< [11..11] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ12 : 1; /*!< [12..12] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ13 : 1; /*!< [13..13] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ14 : 1; /*!< [14..14] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ15 : 1; /*!< [15..15] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ16 : 1; /*!< [16..16] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ17 : 1; /*!< [17..17] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ18 : 1; /*!< [18..18] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ19 : 1; /*!< [19..19] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ20 : 1; /*!< [20..20] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ21 : 1; /*!< [21..21] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ22 : 1; /*!< [22..22] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ23 : 1; /*!< [23..23] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ24 : 1; /*!< [24..24] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ25 : 1; /*!< [25..25] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ26 : 1; /*!< [26..26] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ27 : 1; /*!< [27..27] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ28 : 1; /*!< [28..28] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ29 : 1; /*!< [29..29] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ30 : 1; /*!< [30..30] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ31 : 1; /*!< [31..31] IRQ Deep Sleep Returns Enable bit */ + } DSLPWUPIRQEN_b[3]; + }; + __IM uint32_t RESERVED8[25]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00006280) DMAC Event Link Setting Registers */ + + struct + { + __IOM uint32_t DELS : 10; /*!< [9..0] DMAC Event Link Select */ + uint32_t : 6; + __IOM uint32_t IR : 1; /*!< [16..16] DMAC Activation Request Status Flag */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED9[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 10; /*!< [9..0] ICU Event Link Select */ + uint32_t : 6; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 25728 (0x6480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4025E000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40202200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED13[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED14[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; + } SVST_b; + }; + + union + { + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ + + struct + { + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED27[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED28[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED30; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED32[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED33[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40203000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40400000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000002) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + + union + { + __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40400800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40400D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[3]; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[13]; + __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40202000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40252000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint16_t SRAMPRCR; /*!< (@ 0x00000000) SRAM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t SRAMPRCR_NS; /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) SRAM Wait State Control Register */ + + struct + { + __IOM uint8_t WTEN : 1; /*!< [0..0] SRAM wait enable */ + uint8_t : 7; + } SRAMWTSC_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4; + + union + { + __IOM uint8_t SRAMCR0; /*!< (@ 0x00000010) SRAM Control Register 0 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR0_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRAMCR1; /*!< (@ 0x00000014) SRAM Control Register 1 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR1_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t SRAMCR2; /*!< (@ 0x00000018) SRAM Control Register 2 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR2_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t SRAMCR3; /*!< (@ 0x0000001C) SRAM Control Register 3 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR3_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[4]; + + union + { + __IOM uint8_t SRAMECCRGN0; /*!< (@ 0x00000030) SRAM ECC Region Control Register 0 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN0_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; + + union + { + __IOM uint8_t SRAMECCRGN1; /*!< (@ 0x00000034) SRAM ECC Region Control Register 1 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN1_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t SRAMECCRGN2; /*!< (@ 0x00000038) SRAM ECC Region Control Register 2 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN2_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t SRAMECCRGN3; /*!< (@ 0x0000003C) SRAM ECC Region Control Register 3 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN3_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IM uint16_t SRAMESR; /*!< (@ 0x00000040) SRAM Error Status Register For ECC RAM */ + + struct + { + __IM uint16_t ERR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status */ + __IM uint16_t ERR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status */ + __IM uint16_t ERR10 : 1; /*!< [2..2] SRAM1 1-bit ECC Error Status */ + __IM uint16_t ERR11 : 1; /*!< [3..3] SRAM1 2-bit ECC Error Status */ + __IM uint16_t ERR20 : 1; /*!< [4..4] SRAM2 1-bit ECC Error Status */ + __IM uint16_t ERR21 : 1; /*!< [5..5] SRAM2 2-bit ECC Error Status */ + __IM uint16_t ERR30 : 1; /*!< [6..6] SRAM3 1-bit ECC Error Status */ + __IM uint16_t ERR31 : 1; /*!< [7..7] SRAM3 2-bit ECC Error Status */ + uint16_t : 8; + } SRAMESR_b; + }; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23; + + union + { + __OM uint16_t SRAMESCLR; /*!< (@ 0x00000048) SRAM Error Status Clear Register For ECC RAM */ + + struct + { + __OM uint16_t CLR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status Clear */ + __OM uint16_t CLR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status Clear */ + __OM uint16_t CLR10 : 1; /*!< [2..2] SRAM1 1-bit ECC Error Status Clear */ + __OM uint16_t CLR11 : 1; /*!< [3..3] SRAM1 2-bit ECC Error Status Clear */ + __OM uint16_t CLR20 : 1; /*!< [4..4] SRAM2 1-bit ECC Error Status Clear */ + __OM uint16_t CLR21 : 1; /*!< [5..5] SRAM2 2-bit ECC Error Status Clear */ + __OM uint16_t CLR30 : 1; /*!< [6..6] SRAM3 1-bit ECC Error Status Clear */ + __OM uint16_t CLR31 : 1; /*!< [7..7] SRAM3 2-bit ECC Error Status Clear */ + uint16_t : 8; + } SRAMESCLR_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25; + + union + { + __IM uint32_t SRAMEAR00; /*!< (@ 0x00000050) SRAM Error Address Register 00 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR00_b; + }; + + union + { + __IM uint32_t SRAMEAR01; /*!< (@ 0x00000054) SRAM Error Address Register 01 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR01_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IM uint32_t SRAMEAR10; /*!< (@ 0x00000060) SRAM Error Address Register 10 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR10_b; + }; + + union + { + __IM uint32_t SRAMEAR11; /*!< (@ 0x00000064) SRAM Error Address Register 11 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR11_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IM uint32_t SRAMEAR20; /*!< (@ 0x00000070) SRAM Error Address Register 20 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR20_b; + }; + + union + { + __IM uint32_t SRAMEAR21; /*!< (@ 0x00000074) SRAM Error Address Register 21 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR21_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IM uint32_t SRAMEAR30; /*!< (@ 0x00000080) SRAM Error Address Register 30 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR30_b; + }; + + union + { + __IM uint32_t SRAMEAR31; /*!< (@ 0x00000084) SRAM Error Address Register 31 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR31_b; + }; +} R_SRAM_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4025D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint8_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t OPE : 1; /*!< [6..6] Output Port Enable */ + uint8_t : 1; + } SBYCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t SSCR2; /*!< (@ 0x0000000E) Software Standby Control Register 2 */ + + struct + { + __IOM uint8_t SS2FSR : 1; /*!< [0..0] Software Standby 2 Fast Return */ + uint8_t : 7; + } SSCR2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IM uint8_t MRSCR; /*!< (@ 0x00000010) MRAM Standby Control Register */ + + struct + { + __IM uint8_t MRSWCF : 1; /*!< [0..0] MRAM Stabilization wait completion flag */ + uint8_t : 7; + } MRSCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t VSCR; /*!< (@ 0x00000014) Voltage Scaling Control Register */ + + struct + { + __IOM uint8_t VSCM : 3; /*!< [2..0] Voltage Scaling Control Mode */ + uint8_t : 1; + __IOM uint8_t VSCMTSF : 1; /*!< [4..4] Voltage Scaling Control Mode Transition Status Flag */ + uint8_t : 3; + } VSCR_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRMONR; /*!< (@ 0x00000018) SRAM Monitor Register */ + + struct + { + __IOM uint8_t MON : 2; /*!< [1..0] SRAM Voltage Monitor */ + uint8_t : 6; + } SRMONR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 4; /*!< [3..0] Peripheral Module Clock D (PCLKD) Select */ + __IOM uint32_t PCKC : 4; /*!< [7..4] Peripheral Module Clock C (PCLKC) Select */ + __IOM uint32_t PCKB : 4; /*!< [11..8] Peripheral Module Clock B (PCLKB) Select */ + __IOM uint32_t PCKA : 4; /*!< [15..12] Peripheral Module Clock A (PCLKA) Select */ + __IOM uint32_t BCK : 4; /*!< [19..16] External Bus Clock (BCLK) Select */ + __IOM uint32_t PCKE : 4; /*!< [23..20] Peripheral Module Clock E (PCLKE) Select */ + __IOM uint32_t ICK : 4; /*!< [27..24] System Clock (ICLK) Select */ + __IOM uint32_t FCK : 4; /*!< [31..28] MRAM Clock (MRPCLK) Select */ + } SCKDIVCR_b; + }; + + union + { + __IOM uint16_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + __IOM uint16_t CPUCK : 4; /*!< [3..0] CPU0 Clock (CPUCLK0) Select */ + __IOM uint16_t CPUCK1 : 4; /*!< [7..4] CPU1 Clock (CPUCLK1) Select */ + __IOM uint16_t NPUCK : 4; /*!< [11..8] NPU Clock (NPUCLK) Select */ + __IOM uint16_t MRICK : 4; /*!< [15..12] MRAM bus Clock (MRICLK) Select */ + } SCKDIVCR2_b; + }; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL1 Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL1 Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + __IM uint8_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 6; + __IOM uint8_t EBCKASEL : 1; /*!< [7..7] External Bus Asynchronous Select */ + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock Out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock Control Register */ + uint8_t : 2; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IM uint8_t OSCMONR; /*!< (@ 0x00000043) Oscillator Monitor Register */ + + struct + { + uint8_t : 1; + __IM uint8_t MOCOMON : 1; /*!< [1..1] MOCO operation monitor */ + __IM uint8_t LOCOMON : 1; /*!< [2..2] LOCO operation monitor */ + uint8_t : 5; + } OSCMONR_b; + }; + __IM uint32_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED21; + + union + { + union + { + __IOM uint16_t PLLCCR2; /*!< (@ 0x0000004C) PLL1 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLLCCR2_b; + }; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + }; + + union + { + __IOM uint16_t PLL2CCR2; /*!< (@ 0x0000004E) PLL2 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLL2CCR2_b; + }; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED22; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] EBCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + + union + { + __IOM uint8_t SCICKDIVCR; /*!< (@ 0x00000054) SCI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] SCI clock (SCICLK) Division Select */ + uint8_t : 4; + } SCICKDIVCR_b; + }; + + union + { + __IOM uint8_t SCICKCR; /*!< (@ 0x00000055) SCI clock control register */ + + struct + { + __IOM uint8_t SCICKSEL : 4; /*!< [3..0] SCI clock (SCICLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] SCI clock (SCICLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] SCI clock (SCICLK) Switching Ready state flag */ + } SCICKCR_b; + }; + + union + { + __IOM uint8_t SPICKDIVCR; /*!< (@ 0x00000056) SPI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] SPI clock (SPICLK) Division Select */ + uint8_t : 4; + } SPICKDIVCR_b; + }; + + union + { + __IOM uint8_t SPICKCR; /*!< (@ 0x00000057) SPI clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] SPI clock (SPICLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] SPI clock (SPICLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] SPI clock (SPICLK) Switching Ready state flag */ + } SPICKCR_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADCCKDIVCR; /*!< (@ 0x0000005A) ADC clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ADCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ADCCKCR; /*!< (@ 0x0000005B) ADC clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ADCCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000005C) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 4; /*!< [3..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 4; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x0000005D) GPT clock control register */ + + struct + { + __IOM uint8_t GPTCKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t LCDCKDIVCR; /*!< (@ 0x0000005E) LCD clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] LCD clock (LCDCLK) Division Select */ + uint8_t : 4; + } LCDCKDIVCR_b; + }; + + union + { + __IOM uint8_t LCDCKCR; /*!< (@ 0x0000005F) LCD clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] LCD clock (LCDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] LCD clock (LCDCLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] LCD clock (LCDCLK) Switching Ready state flag */ + } LCDCKCR_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED25; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 4; /*!< [3..0] USB Clock (USBCLK) Division Select */ + uint8_t : 4; + } USBCKDIVCR_b; + }; + + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 4; /*!< [3..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 4; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 4; /*!< [3..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 4; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 4; /*!< [3..0] USB clock (USB60CLK) Division Select */ + uint8_t : 4; + } USB60CKDIVCR_b; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000070) I3C Clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 4; /*!< [3..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 4; + } I3CCKDIVCR_b; + }; + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 4; /*!< [3..0] USB Clock (USBCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 4; /*!< [3..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 2; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 4; /*!< [3..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000078) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 4; /*!< [3..0] I3C clock (I3CCLK) source select */ + uint8_t : 2; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t MOSCSCR; /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register */ + + struct + { + __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select */ + uint8_t : 7; + } MOSCSCR_b; + }; + + union + { + __IOM uint8_t HOCOSCR; /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t HOSCSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select */ + uint8_t : 7; + } HOCOSCR_b; + }; + __IM uint16_t RESERVED31; + __IM uint32_t RESERVED32; + + union + { + __IOM uint8_t MOCOSCR; /*!< (@ 0x00000084) Middle-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t MOCOSOKP : 1; /*!< [0..0] MOCO Standby Oscillation Keep select */ + uint8_t : 7; + } MOCOSCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[5]; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED37; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED38[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED39[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED40; + + union + { + __IOM uint32_t PLLCCR; /*!< (@ 0x000000AC) PLL1 Clock Control Register */ + + struct + { + __IOM uint32_t PLIDIV : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select */ + uint32_t : 1; + __IOM uint32_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select */ + __IOM uint32_t PLLMUL : 9; /*!< [16..8] PLL1 Frequency Multiplication Factor Select */ + uint32_t : 15; + } PLLCCR_b; + }; + __IM uint32_t RESERVED41[4]; + + union + { + __IOM uint32_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag */ + __IOM uint32_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect Flag */ + __IOM uint32_t SWRF : 1; /*!< [2..2] Software Reset Detect Flag */ + uint32_t : 1; + __IOM uint32_t CLURF : 1; /*!< [4..4] CPU0 Lockup Reset Detect flags */ + __IOM uint32_t LM0RF : 1; /*!< [5..5] Local memory 0 error Reset Detect Flag */ + uint32_t : 4; + __IOM uint32_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect Flag */ + uint32_t : 3; + __IOM uint32_t CMRF : 1; /*!< [14..14] Common memory error Reset Detect Flag */ + uint32_t : 2; + __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag */ + uint32_t : 2; + __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag */ + __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag */ + __IOM uint32_t NWRF : 1; /*!< [22..22] Network Reset Detect Flag */ + uint32_t : 9; + } RSTSR1_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t PLL2CCR; /*!< (@ 0x000000C8) PLL2 Clock Control Register */ + + struct + { + __IOM uint32_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint32_t : 1; + __IOM uint32_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select */ + __IOM uint32_t PLL2MUL : 9; /*!< [16..8] PLL2 Frequency Multiplication Factor Select */ + uint32_t : 15; + } PLL2CCR_b; + }; + + union + { + __IM uint8_t SYRACCR; /*!< (@ 0x000000CC) System Register Access Control Register */ + + struct + { + __IM uint8_t BUSY : 1; /*!< [0..0] Access Ready Monitor */ + uint8_t : 7; + } SYRACCR_b; + }; + __IM uint8_t RESERVED43; + __IM uint16_t RESERVED44; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED45; + + union + { + __IOM uint8_t BCKADIVCR; /*!< (@ 0x000000D4) Asynchronous external Bus clock Division control + * register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } BCKADIVCR_b; + }; + + union + { + __IOM uint8_t ESWCKDIVCR; /*!< (@ 0x000000D5) EtherSW clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESWCKDIVCR_b; + }; + + union + { + __IOM uint8_t ESWPCKDIVCR; /*!< (@ 0x000000D6) EtherSW-PHY clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESWPCKDIVCR_b; + }; + + union + { + __IOM uint8_t ESCCKDIVCR; /*!< (@ 0x000000D7) EtherCAT clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ETHPCKDIVCR; /*!< (@ 0x000000D8) Ether-PHY clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ETHPCKDIVCR_b; + }; + __IM uint8_t RESERVED46; + + union + { + __IOM uint8_t BCKACR; /*!< (@ 0x000000DA) Asynchronous external bus clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } BCKACR_b; + }; + + union + { + __IOM uint8_t ESWCKCR; /*!< (@ 0x000000DB) EtherSW clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESWCKCR_b; + }; + + union + { + __IOM uint8_t ESWPCKCR; /*!< (@ 0x000000DC) EtherSW-PHY clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESWPCKCR_b; + }; + + union + { + __IOM uint8_t ESCCKCR; /*!< (@ 0x000000DD) EtherCAT clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESCCKCR_b; + }; + + union + { + __IOM uint8_t ETHPCKCR; /*!< (@ 0x000000DE) Ether-PHY clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ETHPCKCR_b; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + + union + { + __IOM uint8_t LVD3CR1; /*!< (@ 0x000000E4) Voltage Monitor 3 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD3CR1_b; + }; + + union + { + __IOM uint8_t LVD3SR; /*!< (@ 0x000000E5) Voltage Monitor 3 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD3SR_b; + }; + + union + { + __IOM uint8_t LVD4CR1; /*!< (@ 0x000000E6) Voltage Monitor 4 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD4CR1_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t LVD5CR1; /*!< (@ 0x000000E8) Voltage Monitor 5 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD5CR1_b; + }; + __IM uint8_t RESERVED49; + __IM uint16_t RESERVED50; + __IM uint32_t RESERVED51; + + union + { + __IOM uint8_t CRVSYSCR; /*!< (@ 0x000000F0) Clock Recovery System Control Register */ + + struct + { + __IOM uint8_t CRVEN : 1; /*!< [0..0] Clock Recovery Enable */ + uint8_t : 7; + } CRVSYSCR_b; + }; + __IM uint8_t RESERVED52; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; + + union + { + __IOM uint8_t CPUDSCR; /*!< (@ 0x00000100) CPU Deep Sleep Control Register */ + + struct + { + __IOM uint8_t PGD0 : 1; /*!< [0..0] Power Gating Disable for CPU0 */ + __IOM uint8_t PGD1 : 1; /*!< [1..1] Power Gating Disable for CPU1 */ + uint8_t : 6; + } CPUDSCR_b; + }; + __IM uint8_t RESERVED55; + __IM uint16_t RESERVED56; + __IM uint32_t RESERVED57[3]; + + union + { + __IOM uint8_t PDCTRGD; /*!< (@ 0x00000110) General Power Domain GD Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRGD_b; + }; + __IM uint8_t RESERVED58; + __IM uint16_t RESERVED59; + + union + { + __IOM uint8_t PDCTRNPU; /*!< (@ 0x00000114) General Power Domain NPU Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRNPU_b; + }; + __IM uint8_t RESERVED60; + __IM uint16_t RESERVED61; + + union + { + __IOM uint8_t PDCTRESWM; /*!< (@ 0x00000118) General Power Domain ESWM Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRESWM_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[9]; + + union + { + __IOM uint16_t PDRAMSCR0; /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0 */ + + struct + { + __IOM uint16_t RKEEP0 : 1; /*!< [0..0] RAM Retention bit 0 */ + __IOM uint16_t RKEEP1 : 1; /*!< [1..1] RAM Retention bit 1 */ + __IOM uint16_t RKEEP2 : 1; /*!< [2..2] RAM Retention bit 2 */ + __IOM uint16_t RKEEP3 : 1; /*!< [3..3] RAM Retention bit 3 */ + __IOM uint16_t RKEEP4 : 1; /*!< [4..4] RAM Retention bit 4 */ + __IOM uint16_t RKEEP5 : 1; /*!< [5..5] RAM Retention bit 5 */ + __IOM uint16_t RKEEP6 : 1; /*!< [6..6] RAM Retention bit 6 */ + __IOM uint16_t RKEEP7 : 1; /*!< [7..7] RAM Retention bit 7 */ + __IOM uint16_t RKEEP8 : 1; /*!< [8..8] RAM Retention bit 8 */ + __IOM uint16_t RKEEP9 : 1; /*!< [9..9] RAM Retention bit 9 */ + __IOM uint16_t RKEEP10 : 1; /*!< [10..10] RAM Retention bit 10 */ + __IOM uint16_t RKEEP11 : 1; /*!< [11..11] RAM Retention bit 11 */ + __IOM uint16_t RKEEP12 : 1; /*!< [12..12] RAM Retention bit 12 */ + __IOM uint16_t RKEEP13 : 1; /*!< [13..13] RAM Retention bit 13 */ + __IOM uint16_t RKEEP14 : 1; /*!< [14..14] RAM Retention bit 14 */ + __IOM uint16_t RKEEP15 : 1; /*!< [15..15] RAM Retention bit 15 */ + } PDRAMSCR0_b; + }; + + union + { + __IOM uint8_t PDRAMSCR1; /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1 */ + + struct + { + __IOM uint8_t RKEEP0 : 1; /*!< [0..0] RAM Retention bit 0 */ + __IOM uint8_t RKEEP1 : 1; /*!< [1..1] RAM Retention bit 1 */ + __IOM uint8_t RKEEP2 : 1; /*!< [2..2] RAM Retention bit 2 */ + __IOM uint8_t RKEEP3 : 1; /*!< [3..3] RAM Retention bit 3 */ + __IOM uint8_t RKEEP4 : 1; /*!< [4..4] RAM Retention bit 4 */ + __IOM uint8_t RKEEP5 : 1; /*!< [5..5] RAM Retention bit 5 */ + __IOM uint8_t RKEEP6 : 1; /*!< [6..6] RAM Retention bit 6 */ + __IOM uint8_t RKEEP7 : 1; /*!< [7..7] RAM Retention bit 7 */ + } PDRAMSCR1_b; + }; + __IM uint8_t RESERVED65; + __IM uint32_t RESERVED66[155]; + + union + { + __IOM uint16_t VBRSABAR; /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary + * Address Register */ + + struct + { + __IOM uint16_t SABA : 16; /*!< [15..0] Security Attribute Boundary Address */ + } VBRSABAR_b; + }; + __IM uint16_t RESERVED67; + + union + { + __IOM uint16_t VBRPABARS; /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Secure Region */ + + struct + { + __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region */ + } VBRPABARS_b; + }; + __IM uint16_t RESERVED68; + + union + { + __IOM uint16_t VBRPABARNS; /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Non-secure Region */ + + struct + { + __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure + * Region */ + } VBRPABARNS_b; + }; + __IM uint16_t RESERVED69; + __IM uint32_t RESERVED70; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } CGFSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003C4) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 27; + } RSTSAR_b; + }; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } LPMSAR_b; + }; + + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + uint32_t : 23; + } BBFSAR_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t PGCSAR; /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non-secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non-secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non-secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non-secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non-secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non-secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non-secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non-secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non-secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non-secure Attribute bit 31 */ + } PGCSAR_b; + }; + __IM uint32_t RESERVED72; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + __IOM uint32_t DPFSA21 : 1; /*!< [21..21] Deep Standby Interrupt Factor Security Attribute bit + * 21 */ + __IOM uint32_t DPFSA22 : 1; /*!< [22..22] Deep Standby Interrupt Factor Security Attribute bit + * 22 */ + __IOM uint32_t DPFSA23 : 1; /*!< [23..23] Deep Standby Interrupt Factor Security Attribute bit + * 23 */ + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + __IOM uint32_t DPFSA28 : 1; /*!< [28..28] Deep Standby Interrupt Factor Security Attribute bit + * 28 */ + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + __IOM uint32_t DPFSA30 : 1; /*!< [30..30] Deep Standby Interrupt Factor Security Attribute bit + * 30 */ + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR_b; + }; + + union + { + __IOM uint32_t RSCSAR; /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register */ + + struct + { + __IOM uint32_t RSCSA0 : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 0 */ + __IOM uint32_t RSCSA1 : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 1 */ + __IOM uint32_t RSCSA2 : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 2 */ + __IOM uint32_t RSCSA3 : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 3 */ + __IOM uint32_t RSCSA4 : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 4 */ + __IOM uint32_t RSCSA5 : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 5 */ + __IOM uint32_t RSCSA6 : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 6 */ + __IOM uint32_t RSCSA7 : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 7 */ + __IOM uint32_t RSCSA8 : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 8 */ + __IOM uint32_t RSCSA9 : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 9 */ + __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10 */ + __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11 */ + __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12 */ + __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13 */ + __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14 */ + __IOM uint32_t RSCSA15 : 1; /*!< [15..15] RAM Standby Control Security Attribute bit 15 */ + __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16 */ + __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17 */ + __IOM uint32_t RSCSA18 : 1; /*!< [18..18] RAM Standby Control Security Attribute bit 18 */ + __IOM uint32_t RSCSA19 : 1; /*!< [19..19] RAM Standby Control Security Attribute bit 19 */ + __IOM uint32_t RSCSA20 : 1; /*!< [20..20] RAM Standby Control Security Attribute bit 20 */ + __IOM uint32_t RSCSA21 : 1; /*!< [21..21] RAM Standby Control Security Attribute bit 21 */ + __IOM uint32_t RSCSA22 : 1; /*!< [22..22] RAM Standby Control Security Attribute bit 22 */ + __IOM uint32_t RSCSA23 : 1; /*!< [23..23] RAM Standby Control Security Attribute bit 23 */ + __IOM uint32_t RSCSA24 : 1; /*!< [24..24] RAM Standby Control Security Attribute bit 24 */ + __IOM uint32_t RSCSA25 : 1; /*!< [25..25] RAM Standby Control Security Attribute bit 25 */ + __IOM uint32_t RSCSA26 : 1; /*!< [26..26] RAM Standby Control Security Attribute bit 26 */ + __IOM uint32_t RSCSA27 : 1; /*!< [27..27] RAM Standby Control Security Attribute bit 27 */ + __IOM uint32_t RSCSA28 : 1; /*!< [28..28] RAM Standby Control Security Attribute bit 28 */ + __IOM uint32_t RSCSA29 : 1; /*!< [29..29] RAM Standby Control Security Attribute bit 29 */ + __IOM uint32_t RSCSA30 : 1; /*!< [30..30] RAM Standby Control Security Attribute bit 30 */ + __IOM uint32_t RSCSA31 : 1; /*!< [31..31] RAM Standby Control Security Attribute bit 31 */ + } RSCSAR_b; + }; + + union + { + __IOM uint32_t DPFSAR1; /*!< (@ 0x000003E8) Deep Standby Interrupt Factor Security Attribution + * Register 1 */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + __IOM uint32_t DPFSA21 : 1; /*!< [21..21] Deep Standby Interrupt Factor Security Attribute bit + * 21 */ + __IOM uint32_t DPFSA22 : 1; /*!< [22..22] Deep Standby Interrupt Factor Security Attribute bit + * 22 */ + __IOM uint32_t DPFSA23 : 1; /*!< [23..23] Deep Standby Interrupt Factor Security Attribute bit + * 23 */ + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + __IOM uint32_t DPFSA28 : 1; /*!< [28..28] Deep Standby Interrupt Factor Security Attribute bit + * 28 */ + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + __IOM uint32_t DPFSA30 : 1; /*!< [30..30] Deep Standby Interrupt Factor Security Attribute bit + * 30 */ + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR1_b; + }; + __IM uint32_t RESERVED73[3]; + __IM uint16_t RESERVED74; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FA) Protect Register for Secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the security + * and privilege setting registers. */ + __IOM uint16_t PRC5 : 1; /*!< [5..5] Enables writing to the registers related the reset control. */ + uint16_t : 2; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_b; + }; + __IM uint16_t RESERVED75; + + union + { + __IOM uint16_t PRCR_NS; /*!< (@ 0x000003FE) Protect Register for Non-secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the privilege + * setting registers. */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_NS_b; + }; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED76; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000402) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED77; + __IM uint32_t RESERVED78[2]; + __IM uint16_t RESERVED79; + __IM uint8_t RESERVED80; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + __IM uint32_t RESERVED81; + __IM uint16_t RESERVED82; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + __IM uint8_t RESERVED83; + __IM uint32_t RESERVED84; + __IM uint16_t RESERVED85; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED86[8]; + + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED87; + __IM uint32_t RESERVED88[15]; + __IM uint16_t RESERVED89; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED90; + __IM uint32_t RESERVED91[11]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED92; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED93; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED94; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + __IM uint8_t RESERVED95; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + __IM uint32_t RESERVED96[336]; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000A00) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + __IOM uint8_t DCSSMODE : 2; /*!< [3..2] DCDC SSMODE */ + uint8_t : 2; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + __IM uint8_t RESERVED97; + __IM uint16_t RESERVED98; + __IM uint32_t RESERVED99; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + __IM uint8_t RESERVED100; + __IM uint16_t RESERVED101; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + __IM uint8_t RESERVED102; + __IM uint16_t RESERVED103; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DPVD1IE : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DPVD2IE : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + __IOM uint8_t DPVD3IE : 1; /*!< [5..5] PVD3 Deep Standby Cancel Signal Enable */ + uint8_t : 2; + } DPSIER2_b; + }; + __IM uint8_t RESERVED104; + __IM uint16_t RESERVED105; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT0IE : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT1IE : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DIWDTIE : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DSOSTDIE : 1; /*!< [6..6] Sub-clock Oscillation stop detection Deep Standby Cancel + * Signal Enable */ + __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable */ + } DPSIER3_b; + }; + __IM uint8_t RESERVED106; + __IM uint16_t RESERVED107; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + __IM uint8_t RESERVED108; + __IM uint16_t RESERVED109; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + __IM uint8_t RESERVED110; + __IM uint16_t RESERVED111; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DPVD1IF : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DPVD2IF : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + __IOM uint8_t DPVD3IF : 1; /*!< [5..5] PVD5 Deep Standby Cancel Flag */ + uint8_t : 2; + } DPSIFR2_b; + }; + __IM uint8_t RESERVED112; + __IM uint16_t RESERVED113; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DULPT0IF : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DULPT1IF : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DIWDTIF : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DSOSTDIF : 1; /*!< [6..6] Sub-clock Oscillation stop detection Deep Standby Cancel + * Flag */ + __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag */ + } DPSIFR3_b; + }; + __IM uint8_t RESERVED114; + __IM uint16_t RESERVED115; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + __IM uint8_t RESERVED116; + __IM uint16_t RESERVED117; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ8EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ9EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + __IM uint8_t RESERVED118; + __IM uint16_t RESERVED119; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + __IOM uint8_t DLVD3IEG : 1; /*!< [5..5] LVD3 Edge Select */ + uint8_t : 2; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED120; + __IM uint16_t RESERVED121; + + union + { + __IOM uint8_t DPSIEGR3; /*!< (@ 0x00000A34) Deep Standby Interrupt Edge Register 3 */ + + struct + { + __IOM uint8_t DIRQ16EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ17EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ18EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ19EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ20EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ21EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ22EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ23EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR3_b; + }; + __IM uint8_t RESERVED122; + __IM uint16_t RESERVED123; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x00000A38) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + __IM uint8_t RESERVED124; + __IM uint16_t RESERVED125; + __IM uint32_t RESERVED126; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000A40) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect Flag */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect Flag */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect Flag */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect Flag */ + uint8_t : 1; + __IOM uint8_t LVD4RF : 1; /*!< [5..5] Voltage Monitor 4 Reset Detect Flag */ + __IOM uint8_t LVD5RF : 1; /*!< [6..6] Voltage Monitor 5 Reset Detect Flag */ + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag */ + } RSTSR0_b; + }; + __IM uint8_t RESERVED127; + __IM uint16_t RESERVED128; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000A44) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED129; + __IM uint16_t RESERVED130; + + union + { + __IOM uint8_t RSTSR3; /*!< (@ 0x00000A48) Reset Status Register 3 */ + + struct + { + __IOM uint8_t CVMRF : 1; /*!< [0..0] Core Voltage Monitor Reset Detect Flag */ + uint8_t : 3; + __IOM uint8_t OCPRF : 1; /*!< [4..4] Overcurrent Protection Reset Detect Flag */ + uint8_t : 2; + __IOM uint8_t TEMPRF : 1; /*!< [7..7] Temperature Monitor Reset Detect Flag */ + } RSTSR3_b; + }; + __IM uint8_t RESERVED131; + __IM uint16_t RESERVED132; + __IM uint32_t RESERVED133; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t MODRV0 : 3; /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching */ + uint8_t : 2; + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + uint8_t : 1; + } MOMCR_b; + }; + __IM uint8_t RESERVED134; + __IM uint16_t RESERVED135; + __IM uint32_t RESERVED136; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000A58) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD1CMPCR_b; + }; + __IM uint8_t RESERVED137; + __IM uint16_t RESERVED138; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000A5C) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD2CMPCR_b; + }; + __IM uint8_t RESERVED139; + __IM uint16_t RESERVED140; + + union + { + __IOM uint8_t LVD3CMPCR; /*!< (@ 0x00000A60) Voltage Monitoring 3 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD3CMPCR_b; + }; + __IM uint8_t RESERVED141; + __IM uint16_t RESERVED142; + + union + { + __IOM uint8_t LVD4CMPCR; /*!< (@ 0x00000A64) Voltage Monitoring 4 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD4CMPCR_b; + }; + __IM uint8_t RESERVED143; + __IM uint16_t RESERVED144; + + union + { + __IOM uint8_t LVD5CMPCR; /*!< (@ 0x00000A68) Voltage Monitoring 5 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD5CMPCR_b; + }; + __IM uint8_t RESERVED145; + __IM uint16_t RESERVED146; + __IM uint32_t RESERVED147; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + __IM uint8_t RESERVED148; + __IM uint16_t RESERVED149; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED150; + __IM uint16_t RESERVED151; + + union + { + __IOM uint8_t LVD3CR0; /*!< (@ 0x00000A78) Voltage Monitor 3 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD3CR0_b; + }; + __IM uint8_t RESERVED152; + __IM uint16_t RESERVED153; + + union + { + __IOM uint8_t LVD4CR0; /*!< (@ 0x00000A7C) Voltage Monitor 4 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD4CR0_b; + }; + __IM uint8_t RESERVED154; + __IM uint16_t RESERVED155; + + union + { + __IOM uint8_t LVD5CR0; /*!< (@ 0x00000A80) Voltage Monitor 5 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD5CR0_b; + }; + __IM uint8_t RESERVED156; + __IM uint16_t RESERVED157; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + __IM uint8_t RESERVED158; + __IM uint16_t RESERVED159; + + union + { + __IOM uint8_t VBTBPCR1; /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop */ + uint8_t : 7; + } VBTBPCR1_b; + }; + __IM uint8_t RESERVED160; + __IM uint16_t RESERVED161; + __IM uint32_t RESERVED162; + + union + { + __IOM uint8_t LPSCR; /*!< (@ 0x00000A90) Low Power State Control Register */ + + struct + { + __IOM uint8_t LPMD : 4; /*!< [3..0] Low power mode setting bit */ + uint8_t : 4; + } LPSCR_b; + }; + __IM uint8_t RESERVED163; + __IM uint16_t RESERVED164; + __IM uint32_t RESERVED165; + + union + { + __IOM uint8_t SSCR1; /*!< (@ 0x00000A98) Software Standby Control Register 1 */ + + struct + { + __IOM uint8_t SS2FR : 1; /*!< [0..0] Software Standby 2 Fast Return */ + uint8_t : 1; + __IOM uint8_t SS2LP : 2; /*!< [3..2] Software Standby 2 Low Power Select */ + uint8_t : 4; + } SSCR1_b; + }; + __IM uint8_t RESERVED166; + __IM uint16_t RESERVED167; + + union + { + __IOM uint8_t SVSCR; /*!< (@ 0x00000A9C) SSTBY Voltage Scaling Control Register */ + + struct + { + __IOM uint8_t SVSCM : 3; /*!< [2..0] SSTBY Voltage Scaling Control Mode */ + uint8_t : 5; + } SVSCR_b; + }; + __IM uint8_t RESERVED168; + __IM uint16_t RESERVED169; + __IM uint32_t RESERVED170[4]; + + union + { + __IOM uint8_t LVOCR; /*!< (@ 0x00000AB0) Low Voltage Operation Control Register */ + + struct + { + __IOM uint8_t LVO0E : 1; /*!< [0..0] Low Voltage Operation 0 Enable */ + __IOM uint8_t LVO1E : 1; /*!< [1..1] Low Voltage Operation 1 Enable */ + uint8_t : 6; + } LVOCR_b; + }; + __IM uint8_t RESERVED171; + __IM uint16_t RESERVED172; + + union + { + __IOM uint8_t MWMCR; /*!< (@ 0x00000AB4) MRAM-OTP Write Mode Control Register */ + + struct + { + __IOM uint8_t MWM : 2; /*!< [1..0] MRAM-OTP Write Mode */ + uint8_t : 6; + } MWMCR_b; + }; + __IM uint8_t RESERVED173; + __IM uint16_t RESERVED174; + __IM uint32_t RESERVED175[6]; + + union + { + __IOM uint8_t SYRSTMSK0; /*!< (@ 0x00000AD0) System Reset Mask Control Register 0 */ + + struct + { + __IOM uint8_t IWDTMASK : 1; /*!< [0..0] Independent Watchdog Timer Reset Mask */ + __IOM uint8_t WDT0MASK : 1; /*!< [1..1] Watchdog Timer Reset Mask */ + __IOM uint8_t SWMASK : 1; /*!< [2..2] Software Reset Mask */ + uint8_t : 1; + __IOM uint8_t CLU0MASK : 1; /*!< [4..4] CPU Lockup Reset Mask */ + __IOM uint8_t LM0MASK : 1; /*!< [5..5] Local Memory 0 Error Reset Mask */ + __IOM uint8_t CMMASK : 1; /*!< [6..6] Common Memory Error Reset Mask */ + __IOM uint8_t BUSMASK : 1; /*!< [7..7] Bus Error Reset Mask */ + } SYRSTMSK0_b; + }; + __IM uint8_t RESERVED176; + __IM uint16_t RESERVED177; + + union + { + __IOM uint8_t SYRSTMSK1; /*!< (@ 0x00000AD4) System Reset Mask Control Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog Timer Reset Mask */ + uint8_t : 2; + __IOM uint8_t CLU1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */ + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local Memory 1 Error Reset Mask */ + uint8_t : 2; + } SYRSTMSK1_b; + }; + __IM uint8_t RESERVED178; + __IM uint16_t RESERVED179; + + union + { + __IOM uint8_t SYRSTMSK2; /*!< (@ 0x00000AD8) System Reset Mask Control Register 2 */ + + struct + { + __IOM uint8_t PVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask */ + __IOM uint8_t PVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask */ + uint8_t : 6; + } SYRSTMSK2_b; + }; + __IM uint8_t RESERVED180; + __IM uint16_t RESERVED181; + + union + { + __IOM uint8_t TEMPRCR; /*!< (@ 0x00000ADC) Temperature Monitor Reset Control Register */ + + struct + { + __IOM uint8_t TEMPREN : 1; /*!< [0..0] Temperature Monitor Reset Enable */ + __IOM uint8_t TSNEN : 1; /*!< [1..1] Temperature Monitor Sensor Enable */ + __IOM uint8_t CMPEN : 1; /*!< [2..2] Comparator Enable */ + __IOM uint8_t TSNKEEP : 1; /*!< [3..3] Temperature Monitor Sensor Latch Control */ + uint8_t : 4; + } TEMPRCR_b; + }; + __IM uint8_t RESERVED182; + __IM uint16_t RESERVED183; + + union + { + __IOM uint8_t TEMPRLR; /*!< (@ 0x00000AE0) Temperature Monitor Reset Lock Register */ + + struct + { + __IOM uint8_t LOCK : 1; /*!< [0..0] Temperature Monitor Reset Control Register Lock */ + uint8_t : 7; + } TEMPRLR_b; + }; + __IM uint8_t RESERVED184; + __IM uint16_t RESERVED185; + __IM uint32_t RESERVED186[7]; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000B00) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + __IOM uint8_t LDOSTP2 : 1; /*!< [2..2] LDO2 Stop */ + __IOM uint8_t LDOSTP3 : 1; /*!< [3..3] LDO3 Stop */ + __IOM uint8_t LDOSTP4 : 1; /*!< [4..4] LDO4 Stop */ + __IOM uint8_t LDOSTP5 : 1; /*!< [5..5] LDO5 Stop */ + __IOM uint8_t LDOSTP6 : 1; /*!< [6..6] LDO6 Stop */ + __IOM uint8_t LDOSTP7 : 1; /*!< [7..7] LDO7 Stop */ + } LDOSCR_b; + }; + __IM uint8_t RESERVED187; + __IM uint16_t RESERVED188; + + union + { + __IOM uint8_t PLL1LDOCR; /*!< (@ 0x00000B04) PLL1-LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL1LDOCR_b; + }; + __IM uint8_t RESERVED189; + __IM uint16_t RESERVED190; + + union + { + __IOM uint8_t PLL2LDOCR; /*!< (@ 0x00000B08) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL2LDOCR_b; + }; + __IM uint8_t RESERVED191; + __IM uint16_t RESERVED192; + + union + { + __IOM uint8_t HOCOLDOCR; /*!< (@ 0x00000B0C) HOCO-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } HOCOLDOCR_b; + }; + __IM uint8_t RESERVED193; + __IM uint16_t RESERVED194; + + union + { + __IOM uint8_t MOMCR2; /*!< (@ 0x00000B10) Main Clock Oscillator Mode Oscillation Control + * Register 2 */ + + struct + { + __IOM uint8_t MOMODE : 1; /*!< [0..0] Main Clock Oscillator Mode Select */ + uint8_t : 7; + } MOMCR2_b; + }; + __IM uint8_t RESERVED195; + __IM uint16_t RESERVED196; + __IM uint32_t RESERVED197[3]; + + union + { + __IOM uint8_t LVD1FCR; /*!< (@ 0x00000B20) Voltage Monitor 1 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD1FCR_b; + }; + __IM uint8_t RESERVED198; + __IM uint16_t RESERVED199; + + union + { + __IOM uint8_t LVD2FCR; /*!< (@ 0x00000B24) Voltage Monitor 2 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD2FCR_b; + }; + __IM uint8_t RESERVED200; + __IM uint16_t RESERVED201; + + union + { + __IOM uint8_t LVD3FCR; /*!< (@ 0x00000B28) Voltage Monitor 3 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD3FCR_b; + }; + __IM uint8_t RESERVED202; + __IM uint16_t RESERVED203; + + union + { + __IOM uint8_t LVD4FCR; /*!< (@ 0x00000B2C) Voltage Monitor 4 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD4FCR_b; + }; + __IM uint8_t RESERVED204; + __IM uint16_t RESERVED205; + + union + { + __IOM uint8_t LVD5FCR; /*!< (@ 0x00000B30) Voltage Monitor 5 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD5FCR_b; + }; + __IM uint8_t RESERVED206; + __IM uint16_t RESERVED207; + + union + { + __IOM uint8_t PVDLR; /*!< (@ 0x00000B34) Voltage Monitor Lock Register */ + + struct + { + __IOM uint8_t LOCK : 1; /*!< [0..0] LOCK control */ + uint8_t : 7; + } PVDLR_b; + }; + __IM uint8_t RESERVED208; + __IM uint16_t RESERVED209; + __IM uint32_t RESERVED210[2]; + + union + { + __IOM uint8_t DPSIER4; /*!< (@ 0x00000B40) Deep Standby Interrupt Enable Register 4 */ + + struct + { + __IOM uint8_t DIRQ16E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ17E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ18E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ19E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ20E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ21E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ22E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ23E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER4_b; + }; + __IM uint8_t RESERVED211; + __IM uint16_t RESERVED212; + + union + { + __IOM uint8_t DPSIER5; /*!< (@ 0x00000B44) Deep Standby Interrupt Enable Register 5 */ + + struct + { + __IOM uint8_t DIRQ24E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ25E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ26E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ27E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ28E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ29E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ30E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ31E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER5_b; + }; + __IM uint8_t RESERVED213; + __IM uint16_t RESERVED214; + + union + { + __IOM uint8_t DPSIFR4; /*!< (@ 0x00000B48) Deep Standby Interrupt Flag Register 4 */ + + struct + { + __IOM uint8_t DIRQ16F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ17F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ18F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ19F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ20F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ21F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ22F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ23F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR4_b; + }; + __IM uint8_t RESERVED215; + __IM uint16_t RESERVED216; + + union + { + __IOM uint8_t DPSIFR5; /*!< (@ 0x00000B4C) Deep Standby Interrupt Flag Register 5 */ + + struct + { + __IOM uint8_t DIRQ24F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ25F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ26F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ27F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ28F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ29F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ30F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ31F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR5_b; + }; + __IM uint8_t RESERVED217; + __IM uint16_t RESERVED218; + + union + { + __IOM uint8_t DPSIEGR4; /*!< (@ 0x00000B50) Deep Standby Interrupt Edge Register 4 */ + + struct + { + __IOM uint8_t DIRQ24EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ25EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ26EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ27EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ28EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ29EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ30EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ31EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR4_b; + }; + __IM uint8_t RESERVED219; + __IM uint16_t RESERVED220; + __IM uint32_t RESERVED221[3]; + + union + { + __IOM uint8_t VBTSWMON; /*!< (@ 0x00000B60) LVDVBATSW control Monitor Register */ + + struct + { + __IOM uint8_t VLVLMON : 3; /*!< [2..0] VDETBAT Level Monitor */ + uint8_t : 1; + __IOM uint8_t VDETEMON : 1; /*!< [4..4] Voltage drop detection enable Monitor */ + uint8_t : 3; + } VBTSWMON_b; + }; + __IM uint8_t RESERVED222; + __IM uint16_t RESERVED223; + + union + { + __IOM uint8_t VBTSWSCR; /*!< (@ 0x00000B64) LVDVBATSW Start-up stable wait Control Register */ + + struct + { + __IOM uint8_t VBTSWE : 1; /*!< [0..0] LVDVBATSW output enable */ + uint8_t : 7; + } VBTSWSCR_b; + }; + __IM uint8_t RESERVED224; + __IM uint16_t RESERVED225; + __IM uint32_t RESERVED226[38]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000C00) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 4; + __IOM uint8_t SOSEL : 1; /*!< [6..6] Sub-Clock Oscillator Switching */ + uint8_t : 1; + } SOMCR_b; + }; + __IM uint16_t RESERVED227; + + union + { + __IOM uint8_t SOSTDCR; /*!< (@ 0x00000C04) Sub-clock Oscillation Stop Detection Control + * Register */ + + struct + { + __IOM uint8_t SOSTDIE : 1; /*!< [0..0] Sub-clock Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t SOSTDE : 1; /*!< [7..7] Sub-clock Oscillation Stop Detection Function Enable */ + } SOSTDCR_b; + }; + + union + { + __IOM uint8_t SOSTDSR; /*!< (@ 0x00000C05) Sub-clock Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t SOSTDF : 1; /*!< [0..0] Sub-clock Oscillation Stop Detection Flag */ + uint8_t : 7; + } SOSTDSR_b; + }; + __IM uint16_t RESERVED228; + __IM uint32_t RESERVED229[14]; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x00000C40) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED230; + __IM uint16_t RESERVED231; + __IM uint8_t RESERVED232; + + union + { + __IOM uint8_t VBTBPCR2; /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2 */ + + struct + { + __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select */ + uint8_t : 1; + __IOM uint8_t VDETE : 1; /*!< [4..4] Voltage drop detection enable */ + uint8_t : 3; + } VBTBPCR2_b; + }; + + union + { + __IOM uint8_t VBTBPSR; /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register */ + + struct + { + __IOM uint8_t VBPORF : 1; /*!< [0..0] VBATT_POR Flag */ + uint8_t : 3; + __IOM uint8_t VBPORM : 1; /*!< [4..4] VBATT_POR Monitor */ + __IOM uint8_t BPWSWM : 1; /*!< [5..5] Battery Power Supply Switch Status Monitor */ + uint8_t : 2; + } VBTBPSR_b; + }; + __IM uint8_t RESERVED233; + + union + { + __IOM uint8_t VBTADSR; /*!< (@ 0x00000C48) VBATT Tamper detection Status Register */ + + struct + { + __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0 */ + __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1 */ + __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2 */ + uint8_t : 5; + } VBTADSR_b; + }; + + union + { + __IOM uint8_t VBTADCR1; /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1 */ + + struct + { + __IOM uint8_t VBTADIE0 : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0 */ + __IOM uint8_t VBTADIE1 : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1 */ + __IOM uint8_t VBTADIE2 : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2 */ + uint8_t : 1; + __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0 */ + __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1 */ + __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2 */ + uint8_t : 1; + } VBTADCR1_b; + }; + + union + { + __IOM uint8_t VBTADCR2; /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2 */ + + struct + { + __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0 */ + __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1 */ + __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2 */ + uint8_t : 5; + } VBTADCR2_b; + }; + __IM uint8_t RESERVED234; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x00000C4C) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTICTLR2; /*!< (@ 0x00000C4D) VBATT Input Control Register 2 */ + + struct + { + __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable */ + __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable */ + __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable */ + uint8_t : 1; + __IOM uint8_t VCH0EG : 1; /*!< [4..4] VBATT CH0 Input Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [5..5] VBATT CH1 Input Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [6..6] VBATT CH2 Input Edge Select */ + uint8_t : 1; + } VBTICTLR2_b; + }; + + union + { + __IOM uint8_t VBTIMONR; /*!< (@ 0x00000C4E) VBATT Input Monitor Register */ + + struct + { + __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor */ + __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor */ + __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor */ + uint8_t : 5; + } VBTIMONR_b; + }; + __IM uint8_t RESERVED235; + + union + { + __IOM uint8_t VBTNCWCR; /*!< (@ 0x00000C50) VBATT Noise Canceler Width Control Register */ + + struct + { + __IOM uint8_t VINCW : 3; /*!< [2..0] VBATT Input Noise Canceler Width select */ + uint8_t : 5; + } VBTNCWCR_b; + }; + __IM uint8_t RESERVED236; + __IM uint16_t RESERVED237; + + union + { + __IOM uint8_t VBTADCR3; /*!< (@ 0x00000C54) VBATT Tamper detection Control Register 3 */ + + struct + { + __IOM uint8_t VBTADZE0 : 1; /*!< [0..0] VBATT Tamper Detection Zeroization Enable 0 */ + __IOM uint8_t VBTADZE1 : 1; /*!< [1..1] VBATT Tamper Detection Zeroization Enable 1 */ + __IOM uint8_t VBTADZE2 : 1; /*!< [2..2] VBATT Tamper Detection Zeroization Enable 2 */ + uint8_t : 5; + } VBTADCR3_b; + }; + __IM uint8_t RESERVED238; + __IM uint16_t RESERVED239; + __IM uint32_t RESERVED240[42]; + + union + { + __IOM uint8_t VBTBKR[128]; /*!< (@ 0x00000D00) VBATT Backup Register [0..127] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[128]; + }; +} R_SYSTEM_Type; /*!< Size = 3456 (0xd80) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x02C1EDA0) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x40235000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_VIN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Video Input Module (R_VIN) + */ + +typedef struct /*!< (@ 0x40347400) R_VIN Structure */ +{ + union + { + __IOM uint32_t MC; /*!< (@ 0x00000000) Main Control Register */ + + struct + { + __IOM uint32_t ME : 1; /*!< [0..0] Module Enable */ + __IOM uint32_t BPS : 1; /*!< [1..1] Color Space Conversion Bypass Mode */ + uint32_t : 1; + __IOM uint32_t IM : 2; /*!< [4..3] Interlace Mode */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [6..6] Endian Type */ + uint32_t : 7; + __IOM uint32_t DC : 2; /*!< [15..14] Dithering Mode Control */ + __IOM uint32_t INF : 3; /*!< [18..16] Input Interface Format */ + uint32_t : 1; + __IOM uint32_t LUTE : 1; /*!< [20..20] Lookup Table Enable */ + uint32_t : 1; + __OM uint32_t ST : 1; /*!< [22..22] Initialization control at STartup */ + uint32_t : 1; + __IOM uint32_t DC2 : 1; /*!< [24..24] Dithering mode Control 2 */ + __IOM uint32_t YUV444 : 1; /*!< [25..25] YUV444 conversion */ + __IOM uint32_t SCLE : 1; /*!< [26..26] This bit is used to enable or disable scaling by the + * UDS. */ + uint32_t : 1; + __IOM uint32_t CLP : 2; /*!< [29..28] Pixel Data Clipping */ + uint32_t : 2; + } MC_b; + }; + + union + { + __IM uint32_t MS; /*!< (@ 0x00000004) Module Status Register */ + + struct + { + __IM uint32_t CA : 1; /*!< [0..0] Video Capture Active Status */ + __IM uint32_t AV : 1; /*!< [1..1] Active Video Status */ + __IM uint32_t FS : 1; /*!< [2..2] Field Status */ + __IM uint32_t FBS : 2; /*!< [4..3] Frame Buffer Status */ + uint32_t : 11; + __IM uint32_t MA : 1; /*!< [16..16] External frame Memory capture Active status */ + uint32_t : 2; + __IM uint32_t FMS : 2; /*!< [20..19] External Frame Memory buffer Status */ + uint32_t : 11; + } MS_b; + }; + + union + { + __IOM uint32_t FC; /*!< (@ 0x00000008) Frame Capture Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC : 1; /*!< [1..1] Continuous Frame Capture Mode */ + uint32_t : 30; + } FC_b; + }; + + union + { + __IOM uint32_t SLPRC; /*!< (@ 0x0000000C) Start Line Pre-Clip Register */ + + struct + { + __IOM uint32_t SLPRC : 12; /*!< [11..0] Start Line PRe-Clip */ + uint32_t : 20; + } SLPRC_b; + }; + + union + { + __IOM uint32_t ELPRC; /*!< (@ 0x00000010) End Line Pre-Clip Register */ + + struct + { + __IOM uint32_t ELPRC : 12; /*!< [11..0] End Line PRe-Clip */ + uint32_t : 20; + } ELPRC_b; + }; + + union + { + __IOM uint32_t SPPRC; /*!< (@ 0x00000014) Start Pixel Pre-Clip Register */ + + struct + { + __IOM uint32_t SPPRC : 12; /*!< [11..0] Start Pixel Pre-Clip */ + uint32_t : 20; + } SPPRC_b; + }; + + union + { + __IOM uint32_t EPPRC; /*!< (@ 0x00000018) End Pixel Pre-Clip Register */ + + struct + { + __IOM uint32_t EPPRC : 12; /*!< [11..0] End Pixel PRe-Clip */ + uint32_t : 20; + } EPPRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CSI_IFMD; /*!< (@ 0x00000020) CSI2 Interface Mode Register */ + + struct + { + __IOM uint32_t VC_SEL : 4; /*!< [3..0] Virtual Channel SELect */ + uint32_t : 4; + __IOM uint32_t DT : 6; /*!< [13..8] Data Type select */ + uint32_t : 11; + __IOM uint32_t DES0 : 1; /*!< [25..25] Data Extension Select */ + uint32_t : 6; + } CSI_IFMD_b; + }; + + union + { + __IOM uint32_t CSIFLD; /*!< (@ 0x00000024) Field detection control Register */ + + struct + { + __IOM uint32_t FLD_EN : 1; /*!< [0..0] FieLD detect ENable */ + uint32_t : 3; + __IOM uint32_t FLD_SEL : 2; /*!< [5..4] even FieLD DETect SELect */ + uint32_t : 10; + __IOM uint32_t FLD_NUM : 1; /*!< [16..16] even FieLD NUMber setting */ + uint32_t : 15; + } CSIFLD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t IS; /*!< (@ 0x0000002C) Image Stride Register */ + + struct + { + __IOM uint32_t IS : 13; /*!< [12..0] Image Stride (Setting unit: pixel) */ + uint32_t : 19; + } IS_b; + }; + + union + { + __IOM uint32_t MB1; /*!< (@ 0x00000030) Memory Base 1 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB1 : 25; /*!< [31..7] Memory Base Address 1 */ + } MB1_b; + }; + + union + { + __IOM uint32_t MB2; /*!< (@ 0x00000034) Memory Base 2 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB2 : 25; /*!< [31..7] Memory Base Address 2 */ + } MB2_b; + }; + + union + { + __IOM uint32_t MB3; /*!< (@ 0x00000038) Memory Base 3 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB3 : 25; /*!< [31..7] Memory Base Address 3 */ + } MB3_b; + }; + + union + { + __IM uint32_t LC; /*!< (@ 0x0000003C) Line Count Register */ + + struct + { + __IM uint32_t LC : 12; /*!< [11..0] Line Count */ + uint32_t : 20; + } LC_b; + }; + + union + { + __IOM uint32_t IE; /*!< (@ 0x00000040) Interrupt Enable Register */ + + struct + { + __IOM uint32_t FOE : 1; /*!< [0..0] FIFO Overflow Interrupt Enable */ + __IOM uint32_t EFE : 1; /*!< [1..1] End of Frame Interrupt Enable */ + __IOM uint32_t SIE : 1; /*!< [2..2] Scanline Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t FIE : 1; /*!< [4..4] Field Interrupt Enable */ + __IOM uint32_t FME : 1; /*!< [5..5] Frame Memory write completion interrupt Enable */ + uint32_t : 2; + __IOM uint32_t PRCLIPHEE : 1; /*!< [8..8] PRCLIPH Error interrupt Enable */ + __IOM uint32_t PRCLIPVEE : 1; /*!< [9..9] PRCLIPV Error interrupt Enable */ + uint32_t : 4; + __IOM uint32_t ROE : 1; /*!< [14..14] Response Overflow interrupt Enable */ + __IOM uint32_t AREE : 1; /*!< [15..15] Axi Resp Error interrupt Enable */ + __IOM uint32_t VRE : 1; /*!< [16..16] VSYNC Deasserting Detect Interrupt Enable */ + __IOM uint32_t VFE : 1; /*!< [17..17] Vsync asserting detect interrupt Enable */ + uint32_t : 13; + __IOM uint32_t FIE2 : 1; /*!< [31..31] Field Interrupt Enable 2 */ + } IE_b; + }; + + union + { + __IOM uint32_t INTS; /*!< (@ 0x00000044) Interrupt Status Register */ + + struct + { + __IOM uint32_t FOS : 1; /*!< [0..0] FIFO Overflow Interrupt Status */ + __IOM uint32_t EFS : 1; /*!< [1..1] End of Frame Interrupt Status */ + __IOM uint32_t SIS : 1; /*!< [2..2] Scanline Interrupt Status */ + uint32_t : 1; + __IOM uint32_t FIS : 1; /*!< [4..4] Field Interrupt Status */ + __IOM uint32_t FMS : 1; /*!< [5..5] Frame Memory write completion interrupt Status */ + uint32_t : 2; + __IOM uint32_t PRCLIPHES : 1; /*!< [8..8] PRCLIPH Error interrupt Status */ + __IOM uint32_t PRCLIPVES : 1; /*!< [9..9] PRCLIPV Error interrupt Status */ + uint32_t : 4; + __IOM uint32_t ROS : 1; /*!< [14..14] Response Overflow interrupt Status */ + __IOM uint32_t ARES : 1; /*!< [15..15] Axi Resp Error interrupt Status */ + __IOM uint32_t VRS : 1; /*!< [16..16] VSYNC Deasserting Detect Interrupt Status */ + __IOM uint32_t VFS : 1; /*!< [17..17] VSYNC Asserting Detect Interrupt Status */ + uint32_t : 13; + __IOM uint32_t FIS2 : 1; /*!< [31..31] Field Interrupt Status 2 */ + } INTS_b; + }; + + union + { + __IOM uint32_t SI; /*!< (@ 0x00000048) Scanline Interrupt Register */ + + struct + { + __IOM uint32_t SI : 12; /*!< [11..0] Scanline Interrupt Setting */ + uint32_t : 20; + } SI_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t MTCSTOP; /*!< (@ 0x00000054) AXI transfer stop control register */ + + struct + { + __IOM uint32_t STOPREQ : 1; /*!< [0..0] axi forced STOP REQuest */ + __IM uint32_t STOPACK : 1; /*!< [1..1] for axi forced STOP request, ACKnowledgement */ + uint32_t : 14; + __IM uint32_t OUTSTAND : 6; /*!< [21..16] OUTSTANDing current number */ + uint32_t : 10; + } MTCSTOP_b; + }; + + union + { + __IOM uint32_t DMR; /*!< (@ 0x00000058) Data Mode Register */ + + struct + { + __IOM uint32_t DTMD : 2; /*!< [1..0] Data Conversion Mode */ + __IOM uint32_t ABIT : 1; /*!< [2..2] Alpha Bit */ + uint32_t : 1; + __IOM uint32_t BPSM : 1; /*!< [4..4] Output Data Byte Swap Mode */ + uint32_t : 3; + __IOM uint32_t EXRGB : 1; /*!< [8..8] Extension RGB Conversion Mode */ + uint32_t : 2; + __IOM uint32_t YC_THR : 1; /*!< [11..11] YC Data Through Mode */ + __IOM uint32_t YMODE : 3; /*!< [14..12] YC Data Transfer Mode */ + uint32_t : 9; + __IOM uint32_t A8BIT : 8; /*!< [31..24] Alpha 8 */ + } DMR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t UVAOF; /*!< (@ 0x00000060) UV Address Offset Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t UVAOF : 25; /*!< [31..7] UV Data Address Offset */ + } UVAOF_b; + }; + __IM uint32_t RESERVED4[7]; + + union + { + __IOM uint32_t UDS_CTRL; /*!< (@ 0x00000080) Scaling Control Registers */ + + struct + { + uint32_t : 16; + __IOM uint32_t NE_BCB : 1; /*!< [16..16] B/Cb Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + __IOM uint32_t NE_GY : 1; /*!< [17..17] G/Y Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + __IOM uint32_t NE_RCR : 1; /*!< [18..18] R/Cr Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + uint32_t : 1; + __IOM uint32_t BC : 1; /*!< [20..20] Pixel Component Interpolation Method at Scale-Up/Down */ + uint32_t : 7; + __IOM uint32_t BLADV : 1; /*!< [28..28] BiLinear or nearest neighbor interpolation characteristic + * ADVanced mode */ + uint32_t : 1; + __IOM uint32_t AMD : 1; /*!< [30..30] Advanced MoDe: Pixel Count at Scale-Up */ + uint32_t : 1; + } UDS_CTRL_b; + }; + + union + { + __IOM uint32_t UDS_SCALE; /*!< (@ 0x00000084) Scaling Factor Registers */ + + struct + { + __IOM uint32_t VFRAC : 12; /*!< [11..0] Multiplier (Fractional Part) of Vertical Scaling Factor */ + __IOM uint32_t VMANT : 4; /*!< [15..12] Multiplier (Integral Part) of Vertical Scaling Factor */ + __IOM uint32_t HFRAC : 12; /*!< [27..16] Multiplier (Fractional Part) of Horizontal Scaling + * Factor */ + __IOM uint32_t HMANT : 4; /*!< [31..28] Multiplier (Integral Part) of Horizontal Scaling Factor */ + } UDS_SCALE_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t UDS_PASS_BWIDTH; /*!< (@ 0x00000090) Passband Registers */ + + struct + { + __IOM uint32_t BWIDTH_V : 7; /*!< [6..0] Vertical Signal Passband at Image Scale-Up/Down */ + uint32_t : 9; + __IOM uint32_t BWIDTH_H : 7; /*!< [22..16] Horizontal Signal Passband at Image Scale-Up/Down */ + uint32_t : 9; + } UDS_PASS_BWIDTH_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t UDS_CLIP_SIZE; /*!< (@ 0x000000A4) UDS Output Size Clipping Registers */ + + struct + { + __IOM uint32_t CL_VSIZE : 12; /*!< [11..0] Clipping Size of Vertical Pixel Count after Scale-Up/-Down */ + uint32_t : 4; + __IOM uint32_t CL_HSIZE : 12; /*!< [27..16] Clipping Size of Horizontal Pixel Count after Scale-Up/-Down */ + uint32_t : 4; + } UDS_CLIP_SIZE_b; + }; + __IM uint32_t RESERVED7[22]; + + union + { + __IOM uint32_t LUTP; /*!< (@ 0x00000100) Lookup Table Pointer Register */ + + struct + { + __IOM uint32_t LTCRPR : 10; /*!< [9..0] Lookup Table Cr Pointer */ + __IOM uint32_t LTCBPR : 10; /*!< [19..10] Lookup Table Cb Pointer */ + __IOM uint32_t LTYPR : 10; /*!< [29..20] Lookup Table Y Pointer */ + uint32_t : 2; + } LUTP_b; + }; + + union + { + __IOM uint32_t LUTD; /*!< (@ 0x00000104) Lookup Table Data Register */ + + struct + { + __IOM uint32_t LTCRDT : 8; /*!< [7..0] Lookup Table Cr Data */ + __IOM uint32_t LTCBDT : 8; /*!< [15..8] Lookup Table Cb Data */ + __IOM uint32_t LTYDT : 8; /*!< [23..16] Lookup Table Y Data */ + uint32_t : 8; + } LUTD_b; + }; + __IM uint32_t RESERVED8[72]; + + union + { + __IOM uint32_t YCCR1; /*!< (@ 0x00000228) RGB to Y Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t YCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Y Calculation */ + uint32_t : 19; + } YCCR1_b; + }; + + union + { + __IOM uint32_t YCCR2; /*!< (@ 0x0000022C) RGB to Y Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t YCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Y Calculation */ + uint32_t : 3; + __IOM uint32_t YCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Y Calculation */ + uint32_t : 3; + } YCCR2_b; + }; + + union + { + __IOM uint32_t YCCR3; /*!< (@ 0x00000230) RGB to Y Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t YCLAP : 12; /*!< [11..0] Y Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t YCLHEN : 1; /*!< [23..23] Y Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t YCLSFT : 5; /*!< [28..24] Y Calculation Shift Down Volume */ + uint32_t : 3; + } YCCR3_b; + }; + + union + { + __IOM uint32_t CBCCR1; /*!< (@ 0x00000234) RGB to Cb Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t CBCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Cb Calculation */ + uint32_t : 19; + } CBCCR1_b; + }; + + union + { + __IOM uint32_t CBCCR2; /*!< (@ 0x00000238) RGB to Cb Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t CBCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Cb Calculation */ + uint32_t : 3; + __IOM uint32_t CBCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Cb Calculation */ + uint32_t : 3; + } CBCCR2_b; + }; + + union + { + __IOM uint32_t CBCCR3; /*!< (@ 0x0000023C) RGB to Cb Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t CBCLAP : 12; /*!< [11..0] Cb Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t CBCLHEN : 1; /*!< [23..23] Cb Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t CBCLSFT : 5; /*!< [28..24] Cb Calculation Shift Down Volume */ + uint32_t : 3; + } CBCCR3_b; + }; + + union + { + __IOM uint32_t CRCCR1; /*!< (@ 0x00000240) RGB to Cr Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t CRCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Cr Calculation */ + uint32_t : 19; + } CRCCR1_b; + }; + + union + { + __IOM uint32_t CRCCR2; /*!< (@ 0x00000244) RGB to Cr Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t CRCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Cr Calculation */ + uint32_t : 3; + __IOM uint32_t CRCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Cr Calculation */ + uint32_t : 3; + } CRCCR2_b; + }; + + union + { + __IOM uint32_t CRCCR3; /*!< (@ 0x00000248) RGB to Cr Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t CRCLAP : 12; /*!< [11..0] Cr Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t CRCLHEN : 1; /*!< [23..23] Cr Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t CRCLSFT : 5; /*!< [28..24] Cr Calculation Shift Down Volume */ + uint32_t : 3; + } CRCCR3_b; + }; + __IM uint32_t RESERVED9[45]; + + union + { + __IOM uint32_t CSCE1; /*!< (@ 0x00000300) YC to RGB Calculation Setting Extension Register + * 1 */ + + struct + { + __IOM uint32_t YMUL2 : 14; /*!< [13..0] Y Multiplication Coefficient 2 for RGB Calculation */ + uint32_t : 2; + __IOM uint32_t ROUND : 1; /*!< [16..16] ROUND off enable */ + uint32_t : 15; + } CSCE1_b; + }; + + union + { + __IOM uint32_t CSCE2; /*!< (@ 0x00000304) YC to RGB Calculation Setting Extension Register + * 2 */ + + struct + { + __IOM uint32_t CSUB2 : 12; /*!< [11..0] CbCr Subtraction Coefficient 2 for RGB Calculation */ + uint32_t : 4; + __IOM uint32_t YSUB2 : 12; /*!< [27..16] Y Subtraction Coefficient 2 for RGB Calculation */ + uint32_t : 4; + } CSCE2_b; + }; + + union + { + __IOM uint32_t CSCE3; /*!< (@ 0x00000308) YC to RGB Calculation Setting Extension Register + * 3 */ + + struct + { + __IOM uint32_t GCRMUL2 : 14; /*!< [13..0] Cr Multiplication Coefficient 2 for G Calculation */ + uint32_t : 2; + __IOM uint32_t RCRMUL2 : 14; /*!< [29..16] Cr Multiplication Coefficient 2 for R Calculation */ + uint32_t : 2; + } CSCE3_b; + }; + + union + { + __IOM uint32_t CSCE4; /*!< (@ 0x0000030C) YC to RGB Calculation Setting Extension Register + * 4 */ + + struct + { + __IOM uint32_t BCBMUL2 : 14; /*!< [13..0] Cb Multiplication Coefficient 2 for B Calculation */ + uint32_t : 2; + __IOM uint32_t GCBMUL2 : 14; /*!< [29..16] Cb Multiplication Coefficient 2 for G Calculation */ + uint32_t : 2; + } CSCE4_b; + }; +} R_VIN_Type; /*!< Size = 784 (0x310) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40202600) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] SRAM0 Register Security Attribution */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] SRAM1 Register Security Attribution */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] SRAM2 Register Security Attribution */ + __IOM uint32_t SRAMSA3 : 1; /*!< [3..3] SRAM3 Register Security Attribution */ + uint32_t : 4; + __IOM uint32_t SRAMWTSA : 1; /*!< [8..8] Security attribution for SRAMWTSC */ + uint32_t : 23; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA0 : 1; /*!< [0..0] DTC0 Security Attribution */ + uint32_t : 15; + __IOM uint32_t DTCSTSA1 : 1; /*!< [16..16] DTC1 Security Attribution */ + uint32_t : 15; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA0 : 1; /*!< [0..0] DMAC0 DMAST Security Attribution */ + uint32_t : 15; + __IOM uint32_t DMASTSA1 : 1; /*!< [16..16] DMAC1 DMAST Security Attribution */ + uint32_t : 15; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) Interrupt Controller Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t SAIRQCR0 : 1; /*!< [0..0] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR1 : 1; /*!< [1..1] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR2 : 1; /*!< [2..2] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR3 : 1; /*!< [3..3] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR4 : 1; /*!< [4..4] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR5 : 1; /*!< [5..5] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR6 : 1; /*!< [6..6] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR7 : 1; /*!< [7..7] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR8 : 1; /*!< [8..8] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR9 : 1; /*!< [9..9] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR10 : 1; /*!< [10..10] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR11 : 1; /*!< [11..11] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR12 : 1; /*!< [12..12] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR13 : 1; /*!< [13..13] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR14 : 1; /*!< [14..14] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR15 : 1; /*!< [15..15] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR16 : 1; /*!< [16..16] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR17 : 1; /*!< [17..17] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR18 : 1; /*!< [18..18] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR19 : 1; /*!< [19..19] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR20 : 1; /*!< [20..20] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR21 : 1; /*!< [21..21] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR22 : 1; /*!< [22..22] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR23 : 1; /*!< [23..23] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR24 : 1; /*!< [24..24] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR25 : 1; /*!< [25..25] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR26 : 1; /*!< [26..26] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR27 : 1; /*!< [27..27] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR28 : 1; /*!< [28..28] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR29 : 1; /*!< [29..29] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR30 : 1; /*!< [30..30] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR31 : 1; /*!< [31..31] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) Interrupt Controller Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t SANMI0 : 1; /*!< [0..0] Security Attributes of registers */ + __IOM uint32_t SANMI1 : 1; /*!< [1..1] Security Attributes of registers */ + __IOM uint32_t SANMI2 : 1; /*!< [2..2] Security Attributes of registers */ + uint32_t : 29; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) Interrupt Controller Unit Security Attribution + * Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security attributes of registers for WUPEN0.b16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security attributes of registers for WUPEN0.b20 */ + uint32_t : 3; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security attributes of registers for WUPEN0.b24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security attributes of registers for WUPEN0.b25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security attributes of registers for WUPEN0.b27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security attributes of registers for WUPEN0.b28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security attributes of registers for WUPEN0.b29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security attributes of registers for WUPEN0.b30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security attributes of registers for WUPEN0.b31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) Interrupt Controller Unit Security Attribution + * Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security attributes of registers for WUPEN1.b10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security attributes of registers for WUPEN1.b11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security attributes of registers for WUPEN1.b12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security attributes of registers for WUPEN1.b13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security attributes of registers for WUPEN1.b14 */ + __IOM uint32_t SAPDMWUP : 1; /*!< [15..15] Security attributes of registers for WUPEN1.b15 */ + uint32_t : 16; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) Interrupt Controller Unit Security Attribution + * Register G */ + + struct + { + __IOM uint32_t SAIELSR0 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR1 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR2 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR3 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR4 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR5 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR6 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR7 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR8 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR9 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR10 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR11 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR12 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR13 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR14 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR15 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR16 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR17 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR18 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR19 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR20 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR21 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR22 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR23 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR24 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR25 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR26 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR27 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR28 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR29 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR30 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR31 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) Interrupt Controller Unit Security Attribution + * Register H */ + + struct + { + __IOM uint32_t SAIELSR32 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR33 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR34 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR35 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR36 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR37 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR38 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR39 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR40 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR41 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR42 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR43 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR44 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR45 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR46 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR47 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR48 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR49 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR50 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR51 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR52 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR53 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR54 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR55 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR56 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR57 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR58 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR59 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR60 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR61 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR62 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR63 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting1 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) Interrupt Controller Unit Security Attribution + * Register I */ + + struct + { + __IOM uint32_t SAIELSR64 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR65 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR66 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR67 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR68 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR69 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR70 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR71 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR72 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR73 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR74 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR75 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR76 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR77 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR78 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR79 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR80 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR81 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR82 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR83 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR84 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR85 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR86 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR87 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR88 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR89 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR90 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR91 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR92 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR93 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR94 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR95 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting2 */ + } ICUSARI_b; + }; + + union + { + __IOM uint32_t ICUSARJ; /*!< (@ 0x0000007C) Interrupt Controller Unit Security Attribution + * Register J */ + + struct + { + __IOM uint32_t SAIELSR0 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR1 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR2 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR3 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR4 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR5 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR6 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR7 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR8 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR9 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR10 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR11 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR12 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR13 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR14 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR15 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR16 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR17 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR18 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR19 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR20 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR21 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR22 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR23 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR24 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR25 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR26 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR27 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR28 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR29 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR30 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR31 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting0 */ + } ICUSARJ_b; + }; + + union + { + __IOM uint32_t ICUSARK; /*!< (@ 0x00000080) Interrupt Controller Unit Security Attribution + * Register K */ + + struct + { + __IOM uint32_t SAIELSR32 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR33 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR34 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR35 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR36 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR37 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR38 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR39 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR40 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR41 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR42 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR43 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR44 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR45 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR46 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR47 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR48 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR49 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR50 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR51 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR52 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR53 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR54 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR55 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR56 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR57 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR58 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR59 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR60 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR61 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR62 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR63 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting1 */ + } ICUSARK_b; + }; + + union + { + __IOM uint32_t ICUSARL; /*!< (@ 0x00000084) Interrupt Controller Unit Security Attribution + * Register L */ + + struct + { + __IOM uint32_t SAIELSR64 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR65 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR66 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR67 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR68 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR69 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR70 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR71 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR72 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR73 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR74 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR75 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR76 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR77 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR78 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR79 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR80 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR81 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR82 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR83 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR84 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR85 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR86 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR87 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR88 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR89 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR90 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR91 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR92 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR93 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR94 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR95 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting2 */ + } ICUSARL_b; + }; + __IM uint32_t RESERVED4[30]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] Bus Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] Bus Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IM uint32_t NMISR; /*!< (@ 0x00000120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint32_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Status Flag */ + __IM uint32_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Status Flag */ + __IM uint32_t PVD1ST : 1; /*!< [2..2] Voltage Monitor 1 Interrupt Status Flag */ + __IM uint32_t PVD2ST : 1; /*!< [3..3] Voltage Monitor 2 Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t SOSTST : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t OSTST : 1; /*!< [6..6] Main Clock Oscillation Stop Detection Interrupt Status + * Flag */ + __IM uint32_t NMIST : 1; /*!< [7..7] NMI Pin Interrupt Status Flag */ + uint32_t : 4; + __IM uint32_t BUSST : 1; /*!< [12..12] Bus Error Interrupt Status Flag */ + __IM uint32_t CMST : 1; /*!< [13..13] Common Memory Error Interrupt Status Flag */ + __IM uint32_t LMST : 1; /*!< [14..14] Local Memory Error Interrupt Status Flag */ + __IM uint32_t LUST : 1; /*!< [15..15] LockUp Error Interrupt Status Flag */ + __IM uint32_t FPUEXCST : 1; /*!< [16..16] FPU Exception Interrupt Status Flag */ + __IM uint32_t MRCRDST : 1; /*!< [17..17] MRAM MRC read Error Interrupt Status Flag */ + __IM uint32_t MRERDST : 1; /*!< [18..18] MRAM MRE read Error Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t IPCST : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Status Flag */ + uint32_t : 11; + } NMISR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUASA0 : 1; /*!< [0..0] MMPUA0 Security Attribution */ + __IOM uint32_t MMPUASA1 : 1; /*!< [1..1] MMPUA1 Security Attribution */ + __IOM uint32_t MMPUASA2 : 1; /*!< [2..2] MMPUA2 Security Attribution */ + __IOM uint32_t MMPUASA3 : 1; /*!< [3..3] MMPUA3 Security Attribution */ + __IOM uint32_t MMPUASA4 : 1; /*!< [4..4] MMPUA4 Security Attribution */ + __IOM uint32_t MMPUASA5 : 1; /*!< [5..5] MMPUA5 Security Attribution */ + __IOM uint32_t MMPUASA6 : 1; /*!< [6..6] MMPUA6 Security Attribution */ + __IOM uint32_t MMPUASA7 : 1; /*!< [7..7] MMPUA7 Security Attribution */ + __IOM uint32_t MMPUASA8 : 1; /*!< [8..8] MMPUA8 Security Attribution */ + __IOM uint32_t MMPUASA9 : 1; /*!< [9..9] MMPUA9 Security Attribution */ + __IOM uint32_t MMPUASA10 : 1; /*!< [10..10] MMPUA10 Security Attribution */ + __IOM uint32_t MMPUASA11 : 1; /*!< [11..11] MMPUA11 Security Attribution */ + __IOM uint32_t MMPUASA12 : 1; /*!< [12..12] MMPUA12 Security Attribution */ + __IOM uint32_t MMPUASA13 : 1; /*!< [13..13] MMPUA13 Security Attribution */ + __IOM uint32_t MMPUASA14 : 1; /*!< [14..14] MMPUA14 Security Attribution */ + __IOM uint32_t MMPUASA15 : 1; /*!< [15..15] MMPUA15 Security Attribution */ + __IOM uint32_t MMPUASA16 : 1; /*!< [16..16] MMPUA16 Security Attribution */ + __IOM uint32_t MMPUASA17 : 1; /*!< [17..17] MMPUA17 Security Attribution */ + __IOM uint32_t MMPUASA18 : 1; /*!< [18..18] MMPUA18 Security Attribution */ + __IOM uint32_t MMPUASA19 : 1; /*!< [19..19] MMPUA19 Security Attribution */ + __IOM uint32_t MMPUASA20 : 1; /*!< [20..20] MMPUA20 Security Attribution */ + __IOM uint32_t MMPUASA21 : 1; /*!< [21..21] MMPUA21 Security Attribution */ + __IOM uint32_t MMPUASA22 : 1; /*!< [22..22] MMPUA22 Security Attribution */ + __IOM uint32_t MMPUASA23 : 1; /*!< [23..23] MMPUA23 Security Attribution */ + __IOM uint32_t MMPUASA24 : 1; /*!< [24..24] MMPUA24 Security Attribution */ + __IOM uint32_t MMPUASA25 : 1; /*!< [25..25] MMPUA25 Security Attribution */ + __IOM uint32_t MMPUASA26 : 1; /*!< [26..26] MMPUA26 Security Attribution */ + __IOM uint32_t MMPUASA27 : 1; /*!< [27..27] MMPUA27 Security Attribution */ + __IOM uint32_t MMPUASA28 : 1; /*!< [28..28] MMPUA28 Security Attribution */ + __IOM uint32_t MMPUASA29 : 1; /*!< [29..29] MMPUA29 Security Attribution */ + __IOM uint32_t MMPUASA30 : 1; /*!< [30..30] MMPUA30 Security Attribution */ + __IOM uint32_t MMPUASA31 : 1; /*!< [31..31] MMPUA31 Security Attribution */ + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUBSA0 : 1; /*!< [0..0] MMPUB0 Security Attribution */ + __IOM uint32_t MMPUBSA1 : 1; /*!< [1..1] MMPUB1 Security Attribution */ + __IOM uint32_t MMPUBSA2 : 1; /*!< [2..2] MMPUB2 Security Attribution */ + __IOM uint32_t MMPUBSA3 : 1; /*!< [3..3] MMPUB3 Security Attribution */ + __IOM uint32_t MMPUBSA4 : 1; /*!< [4..4] MMPUB4 Security Attribution */ + __IOM uint32_t MMPUBSA5 : 1; /*!< [5..5] MMPUB5 Security Attribution */ + __IOM uint32_t MMPUBSA6 : 1; /*!< [6..6] MMPUB6 Security Attribution */ + __IOM uint32_t MMPUBSA7 : 1; /*!< [7..7] MMPUB7 Security Attribution */ + __IOM uint32_t MMPUBSA8 : 1; /*!< [8..8] MMPUB8 Security Attribution */ + __IOM uint32_t MMPUBSA9 : 1; /*!< [9..9] MMPUB9 Security Attribution */ + __IOM uint32_t MMPUBSA10 : 1; /*!< [10..10] MMPUB10 Security Attribution */ + __IOM uint32_t MMPUBSA11 : 1; /*!< [11..11] MMPUB11 Security Attribution */ + __IOM uint32_t MMPUBSA12 : 1; /*!< [12..12] MMPUB12 Security Attribution */ + __IOM uint32_t MMPUBSA13 : 1; /*!< [13..13] MMPUB13 Security Attribution */ + __IOM uint32_t MMPUBSA14 : 1; /*!< [14..14] MMPUB14 Security Attribution */ + __IOM uint32_t MMPUBSA15 : 1; /*!< [15..15] MMPUB15 Security Attribution */ + __IOM uint32_t MMPUBSA16 : 1; /*!< [16..16] MMPUB16 Security Attribution */ + __IOM uint32_t MMPUBSA17 : 1; /*!< [17..17] MMPUB17 Security Attribution */ + __IOM uint32_t MMPUBSA18 : 1; /*!< [18..18] MMPUB18 Security Attribution */ + __IOM uint32_t MMPUBSA19 : 1; /*!< [19..19] MMPUB19 Security Attribution */ + __IOM uint32_t MMPUBSA20 : 1; /*!< [20..20] MMPUB20 Security Attribution */ + __IOM uint32_t MMPUBSA21 : 1; /*!< [21..21] MMPUB21 Security Attribution */ + __IOM uint32_t MMPUBSA22 : 1; /*!< [22..22] MMPUB22 Security Attribution */ + __IOM uint32_t MMPUBSA23 : 1; /*!< [23..23] MMPUB23 Security Attribution */ + __IOM uint32_t MMPUBSA24 : 1; /*!< [24..24] MMPUB24 Security Attribution */ + __IOM uint32_t MMPUBSA25 : 1; /*!< [25..25] MMPUB25 Security Attribution */ + __IOM uint32_t MMPUBSA26 : 1; /*!< [26..26] MMPUB26 Security Attribution */ + __IOM uint32_t MMPUBSA27 : 1; /*!< [27..27] MMPUB27 Security Attribution */ + __IOM uint32_t MMPUBSA28 : 1; /*!< [28..28] MMPUB28 Security Attribution */ + __IOM uint32_t MMPUBSA29 : 1; /*!< [29..29] MMPUB29 Security Attribution */ + __IOM uint32_t MMPUBSA30 : 1; /*!< [30..30] MMPUB30 Security Attribution */ + __IOM uint32_t MMPUBSA31 : 1; /*!< [31..31] MMPUB31 Security Attribution */ + } MMPUSARB_b; + }; + __IM uint32_t RESERVED8[14]; + + union + { + __IOM uint32_t CPUSAR; /*!< (@ 0x00000170) CPU Security Attribution Register */ + + struct + { + __IOM uint32_t CPUSA0 : 1; /*!< [0..0] CPU Security Attribution 0 */ + __IOM uint32_t CPUSA1 : 1; /*!< [1..1] CPU Security Attribution 1 */ + uint32_t : 30; + } CPUSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMAC channel Security Attribution Register */ + + struct + { + __IOM uint32_t SADMAC00 : 1; /*!< [0..0] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC01 : 1; /*!< [1..1] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC02 : 1; /*!< [2..2] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC03 : 1; /*!< [3..3] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC04 : 1; /*!< [4..4] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC05 : 1; /*!< [5..5] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC06 : 1; /*!< [6..6] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC07 : 1; /*!< [7..7] Security attributes of registers for DMAC0 channel */ + uint32_t : 8; + __IOM uint32_t SADMAC10 : 1; /*!< [16..16] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC11 : 1; /*!< [17..17] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC12 : 1; /*!< [18..18] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC13 : 1; /*!< [19..19] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC14 : 1; /*!< [20..20] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC15 : 1; /*!< [21..21] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC16 : 1; /*!< [22..22] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC17 : 1; /*!< [23..23] Security attributes of registers for DMAC1 channel */ + uint32_t : 8; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED12[15]; + + union + { + __IOM uint32_t DMACCHPAR; /*!< (@ 0x000001F0) DMA Channel Privilege Attribution Register */ + + struct + { + __IOM uint32_t PADMAC00 : 1; /*!< [0..0] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC01 : 1; /*!< [1..1] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC02 : 1; /*!< [2..2] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC03 : 1; /*!< [3..3] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC04 : 1; /*!< [4..4] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC05 : 1; /*!< [5..5] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC06 : 1; /*!< [6..6] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC07 : 1; /*!< [7..7] Privilege attributes of outputs and registers for DMAC0 + * channel */ + uint32_t : 8; + __IOM uint32_t PADMAC10 : 1; /*!< [16..16] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC11 : 1; /*!< [17..17] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC12 : 1; /*!< [18..18] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC13 : 1; /*!< [19..19] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC14 : 1; /*!< [20..20] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC15 : 1; /*!< [21..21] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC16 : 1; /*!< [22..22] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC17 : 1; /*!< [23..23] Privilege attributes of outputs and registers for DMAC1 + * channel */ + uint32_t : 8; + } DMACCHPAR_b; + }; + __IM uint32_t RESERVED13[131]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + + union + { + __IOM uint32_t SRAMSABAR2; /*!< (@ 0x00000408) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR2_b; + }; + + union + { + __IOM uint32_t SRAMSABAR3; /*!< (@ 0x0000040C) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR3_b; + }; + __IM uint32_t RESERVED14[60]; + + union + { + __IOM uint32_t CACHESAR; /*!< (@ 0x00000500) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security attributes of registers for CACHE Control */ + uint32_t : 1; + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security attributes of registers for CACHE Error */ + uint32_t : 29; + } CACHESAR_b; + }; + + union + { + __IOM uint32_t TCMSAR; /*!< (@ 0x00000504) TCM Security Attribution Register */ + + struct + { + __IOM uint32_t TCMSA : 1; /*!< [0..0] Security attributes of registers for TCM Control */ + uint32_t : 31; + } TCMSAR_b; + }; + + union + { + __IOM uint32_t TCMSABARC; /*!< (@ 0x00000508) TCM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t TCMSABA : 6; /*!< [18..13] Boundary address between secure and non-secure. (Start + * address of non-secure region) */ + uint32_t : 13; + } TCMSABARC_b; + }; + + union + { + __IOM uint32_t TCMSABARS; /*!< (@ 0x0000050C) TCM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t TCMSABA : 6; /*!< [18..13] Boundary address between secure and non-secure. (Start + * address of non-secure region) */ + uint32_t : 13; + } TCMSABARS_b; + }; + + union + { + __IOM uint32_t SRAMESAR; /*!< (@ 0x00000510) SRAM ECC region Security Attribute Register */ + + struct + { + __IOM uint32_t SRAMESA : 1; /*!< [0..0] ECC region Security Attribution */ + uint32_t : 31; + } SRAMESAR_b; + }; + __IM uint32_t RESERVED15[59]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for ELC */ + __IOM uint32_t TEVTEICU0 : 1; /*!< [1..1] Trusted Event Route Control Register for ICU0 */ + __IOM uint32_t TEVTEICU1 : 1; /*!< [2..2] Trusted Event Route Control Register for ICU1 */ + uint32_t : 29; + } TEVTRCR_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t IPCSAR; /*!< (@ 0x00000610) IPC Security Attribution Register */ + + struct + { + __IOM uint32_t SAIPCSEM0 : 1; /*!< [0..0] Security attributes of registers for IPCSEMn */ + __IOM uint32_t SAIPCSEM1 : 1; /*!< [1..1] Security attributes of registers for IPCSEMn */ + uint32_t : 6; + __IOM uint32_t SAIPCNMI0 : 1; /*!< [8..8] Security attributes of the registers */ + __IOM uint32_t SAIPCNMI1 : 1; /*!< [9..9] Security attributes of the registers */ + uint32_t : 6; + __IOM uint32_t SAIPCIR0 : 1; /*!< [16..16] Security attributes of registers for IPC0STA0, IPC0ISET0, + * IPC0TXD0, IPC0RXD0 and IPC0CLR0 */ + __IOM uint32_t SAIPCIR1 : 1; /*!< [17..17] Security attributes of registers for IPC0STA1, IPC0ISET1, + * IPC0TXD1, IPC0RXD1 and IPC0CLR1 */ + __IOM uint32_t SAIPCIR2 : 1; /*!< [18..18] Security attributes of registers for IPC1STA0, IPC1ISET0, + * IPC1TXD0, IPC1RXD0 and IPC1CLR0 */ + __IOM uint32_t SAIPCIR3 : 1; /*!< [19..19] Security attributes of registers for IPC1STA1, IPC1ISET1, + * IPC1TXD1, IPC1RXD1 and IPC1CLR1 */ + uint32_t : 12; + } IPCSAR_b; + }; + + union + { + __IOM uint32_t IPCPAR; /*!< (@ 0x00000614) IPC Privileged Attribution Register */ + + struct + { + __IOM uint32_t PAIPCSEM0 : 1; /*!< [0..0] Privileged attributes of registers for IPCSEMn */ + __IOM uint32_t PAIPCSEM1 : 1; /*!< [1..1] Privileged attributes of registers for IPCSEMn */ + uint32_t : 6; + __IOM uint32_t PAIPCNMI0 : 1; /*!< [8..8] Privileged attributes of registers */ + __IOM uint32_t PAIPCNMI1 : 1; /*!< [9..9] Privileged attributes of registers */ + uint32_t : 6; + __IOM uint32_t PAIPCIR0 : 1; /*!< [16..16] Privileged attributes of registers for IPC0STA0, IPC0ISET0, + * IPC0TXD0, IPC0RXD0 and IPC0CLR0 */ + __IOM uint32_t PAIPCIR1 : 1; /*!< [17..17] Privileged attributes of registers for IPC0STA1, IPC0ISET1, + * IPC0TXD1, IPC0RXD1 and IPC0CLR1 */ + __IOM uint32_t PAIPCIR2 : 1; /*!< [18..18] Privileged attributes of registers for IPC1STA0, IPC1ISET0, + * IPC1TXD0, IPC1RXD0 and IPC1CLR0 */ + __IOM uint32_t PAIPCIR3 : 1; /*!< [19..19] Privileged attributes of registers for IPC1STA1, IPC1ISET1, + * IPC1TXD1, IPC1RXD1 and IPC1CLR1 */ + uint32_t : 12; + } IPCPAR_b; + }; +} R_CPSCU_Type; /*!< Size = 1560 (0x618) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit A/D Converter (R_ADC_B0) + */ + +typedef struct /*!< (@ 0x40338000) R_ADC_B0 Structure */ +{ + union + { + __IOM uint32_t ADCLKENR; /*!< (@ 0x00000000) A/D Conversion Clock Enable Register */ + + struct + { + __IOM uint32_t CLKEN : 1; /*!< [0..0] ADCLK Operating Enable bit */ + uint32_t : 31; + } ADCLKENR_b; + }; + + union + { + __IM uint32_t ADCLKSR; /*!< (@ 0x00000004) A/D Conversion Clock Status Register */ + + struct + { + __IM uint32_t CLKSR : 1; /*!< [0..0] ADCLK status bit */ + uint32_t : 31; + } ADCLKSR_b; + }; + + union + { + __IOM uint32_t ADCLKCR; /*!< (@ 0x00000008) A/D Conversion Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select */ + uint32_t : 14; + __IOM uint32_t DIVR : 3; /*!< [18..16] Clock Division Ratio Select */ + uint32_t : 13; + } ADCLKCR_b; + }; + + union + { + __IOM uint32_t ADSYCR; /*!< (@ 0x0000000C) A/D Converter Synchronous Operation Control Register */ + + struct + { + __IOM uint32_t ADSYCYC : 11; /*!< [10..0] A/D Converter Synchronous Operation Period Cycle */ + uint32_t : 5; + __IOM uint32_t ADSYDIS0 : 1; /*!< [16..16] ADC0 Synchronous Operation Select */ + __IOM uint32_t ADSYDIS1 : 1; /*!< [17..17] ADC1 Synchronous Operation Select */ + uint32_t : 14; + } ADSYCR_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t ADERINTCR; /*!< (@ 0x00000020) A/D Conversion Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADEIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Error Interrupt Enable */ + __IOM uint32_t ADEIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Error Interrupt Enable */ + uint32_t : 30; + } ADERINTCR_b; + }; + + union + { + __IOM uint32_t ADOVFINTCR; /*!< (@ 0x00000024) A/D Conversion Overflow Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADOVFIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Overflow Interrupt Enable */ + __IOM uint32_t ADOVFIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Overflow Interrupt Enable */ + uint32_t : 30; + } ADOVFINTCR_b; + }; + + union + { + __IOM uint32_t ADCALINTCR; /*!< (@ 0x00000028) Calibration interrupt Enable Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CALENDIE0 : 1; /*!< [16..16] ADC0 Calibration End Interrupt Enable */ + __IOM uint32_t CALENDIE1 : 1; /*!< [17..17] ADC1 Calibration End Interrupt Enable */ + uint32_t : 14; + } ADCALINTCR_b; + }; + __IM uint32_t RESERVED1[5]; + + union + { + __IOM uint32_t ADMDR; /*!< (@ 0x00000040) A/D Converter Mode Selection Register */ + + struct + { + __IOM uint32_t ADMD0 : 4; /*!< [3..0] ADC0 Mode Selection */ + uint32_t : 4; + __IOM uint32_t ADMD1 : 4; /*!< [11..8] ADC1 Mode Selection */ + uint32_t : 20; + } ADMDR_b; + }; + + union + { + __IOM uint32_t ADGSPCR; /*!< (@ 0x00000044) A/D Group scan Priority Control Register */ + + struct + { + __IOM uint32_t PGS0 : 1; /*!< [0..0] ADC0 Group Priority Control Setting */ + __IOM uint32_t RSCN0 : 1; /*!< [1..1] ADC0 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS0 : 1; /*!< [2..2] ADC0 Group Priority Control Setting 3 */ + __IOM uint32_t GRP0 : 1; /*!< [3..3] ADC0 Group Priority Control Setting 4 */ + uint32_t : 4; + __IOM uint32_t PGS1 : 1; /*!< [8..8] ADC1 Group Priority Control Setting */ + __IOM uint32_t RSCN1 : 1; /*!< [9..9] ADC1 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS1 : 1; /*!< [10..10] ADC1 Group Priority Control Setting 3 */ + __IOM uint32_t GRP1 : 1; /*!< [11..11] ADC1 Group Priority Control Setting 4 */ + uint32_t : 20; + } ADGSPCR_b; + }; + + union + { + __IOM uint32_t ADSGER; /*!< (@ 0x00000048) Scan Group Enable Register */ + + struct + { + __IOM uint32_t SGREn : 9; /*!< [8..0] Scan Group n Enable */ + uint32_t : 23; + } ADSGER_b; + }; + + union + { + __IOM uint32_t ADSGCR0; /*!< (@ 0x0000004C) Scan Group Control Register 0 */ + + struct + { + __IOM uint32_t SGADS0 : 2; /*!< [1..0] Scan Group 0 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS1 : 2; /*!< [9..8] Scan Group 1 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS2 : 2; /*!< [17..16] Scan Group 2 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS3 : 2; /*!< [25..24] Scan Group 3 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR0_b; + }; + + union + { + __IOM uint32_t ADSGCR1; /*!< (@ 0x00000050) Scan Group Control Register 1 */ + + struct + { + __IOM uint32_t SGADS4 : 2; /*!< [1..0] Scan Group 4 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS5 : 2; /*!< [9..8] Scan Group 5 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS6 : 2; /*!< [17..16] Scan Group 6 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS7 : 2; /*!< [25..24] Scan Group 7 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR1_b; + }; + + union + { + __IOM uint32_t ADSGCR2; /*!< (@ 0x00000054) Scan Group Control Register 2 */ + + struct + { + __IOM uint32_t SGADS8 : 2; /*!< [1..0] Scan Group 8 A/D Converter Selection */ + uint32_t : 30; + } ADSGCR2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ADINTCR; /*!< (@ 0x0000005C) Scan End Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADIEn : 9; /*!< [8..0] Scan Group n Scan End Interrupt Enable */ + uint32_t : 23; + } ADINTCR_b; + }; + __IM uint32_t RESERVED3[24]; + + union + { + __IOM uint32_t ADTRGEXT0; /*!< (@ 0x000000C0) External Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT0_b; + }; + + union + { + __IOM uint32_t ADTRGELC0; /*!< (@ 0x000000C4) ELC Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC0_b; + }; + + union + { + __IOM uint32_t ADTRGGPT0; /*!< (@ 0x000000C8) GPT Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT0_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ADTRGEXT1; /*!< (@ 0x000000D0) External Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT1_b; + }; + + union + { + __IOM uint32_t ADTRGELC1; /*!< (@ 0x000000D4) ELC Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC1_b; + }; + + union + { + __IOM uint32_t ADTRGGPT1; /*!< (@ 0x000000D8) GPT Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT1_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t ADTRGEXT2; /*!< (@ 0x000000E0) External Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT2_b; + }; + + union + { + __IOM uint32_t ADTRGELC2; /*!< (@ 0x000000E4) ELC Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC2_b; + }; + + union + { + __IOM uint32_t ADTRGGPT2; /*!< (@ 0x000000E8) GPT Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT2_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t ADTRGEXT3; /*!< (@ 0x000000F0) External Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT3_b; + }; + + union + { + __IOM uint32_t ADTRGELC3; /*!< (@ 0x000000F4) ELC Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC3_b; + }; + + union + { + __IOM uint32_t ADTRGGPT3; /*!< (@ 0x000000F8) GPT Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT3_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ADTRGEXT4; /*!< (@ 0x00000100) External Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT4_b; + }; + + union + { + __IOM uint32_t ADTRGELC4; /*!< (@ 0x00000104) ELC Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC4_b; + }; + + union + { + __IOM uint32_t ADTRGGPT4; /*!< (@ 0x00000108) GPT Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT4_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ADTRGEXT5; /*!< (@ 0x00000110) External Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT5_b; + }; + + union + { + __IOM uint32_t ADTRGELC5; /*!< (@ 0x00000114) ELC Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC5_b; + }; + + union + { + __IOM uint32_t ADTRGGPT5; /*!< (@ 0x00000118) GPT Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT5_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t ADTRGEXT6; /*!< (@ 0x00000120) External Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT6_b; + }; + + union + { + __IOM uint32_t ADTRGELC6; /*!< (@ 0x00000124) ELC Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC6_b; + }; + + union + { + __IOM uint32_t ADTRGGPT6; /*!< (@ 0x00000128) GPT Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT6_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t ADTRGEXT7; /*!< (@ 0x00000130) External Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT7_b; + }; + + union + { + __IOM uint32_t ADTRGELC7; /*!< (@ 0x00000134) ELC Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC7_b; + }; + + union + { + __IOM uint32_t ADTRGGPT7; /*!< (@ 0x00000138) GPT Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT7_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t ADTRGEXT8; /*!< (@ 0x00000140) External Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT8_b; + }; + + union + { + __IOM uint32_t ADTRGELC8; /*!< (@ 0x00000144) ELC Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC8_b; + }; + + union + { + __IOM uint32_t ADTRGGPT8; /*!< (@ 0x00000148) GPT Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT8_b; + }; + __IM uint32_t RESERVED12[29]; + + union + { + __IOM uint32_t ADTRGDLR0; /*!< (@ 0x000001C0) A/D Conversion Start Trigger Delay Register 0 */ + + struct + { + __IOM uint32_t TRGDLY0 : 8; /*!< [7..0] Scan Group 0 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY1 : 8; /*!< [23..16] Scan Group 1 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR0_b; + }; + + union + { + __IOM uint32_t ADTRGDLR1; /*!< (@ 0x000001C4) A/D Conversion Start Trigger Delay Register 1 */ + + struct + { + __IOM uint32_t TRGDLY2 : 8; /*!< [7..0] Scan Group 2 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY3 : 8; /*!< [23..16] Scan Group 3 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR1_b; + }; + + union + { + __IOM uint32_t ADTRGDLR2; /*!< (@ 0x000001C8) A/D Conversion Start Trigger Delay Register 2 */ + + struct + { + __IOM uint32_t TRGDLY4 : 8; /*!< [7..0] Scan Group 4 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY5 : 8; /*!< [23..16] Scan Group 5 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR2_b; + }; + + union + { + __IOM uint32_t ADTRGDLR3; /*!< (@ 0x000001CC) A/D Conversion Start Trigger Delay Register 3 */ + + struct + { + __IOM uint32_t TRGDLY6 : 8; /*!< [7..0] Scan Group 6 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY7 : 8; /*!< [23..16] Scan Group 7 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR3_b; + }; + + union + { + __IOM uint32_t ADTRGDLR4; /*!< (@ 0x000001D0) A/D Conversion Start Trigger Delay Register 4 */ + + struct + { + __IOM uint32_t TRGDLY8 : 8; /*!< [7..0] Scan Group 8 Trigger Input Delay Configuration */ + uint32_t : 24; + } ADTRGDLR4_b; + }; + __IM uint32_t RESERVED13[11]; + + union + { + __IOM uint32_t ADSGDCR0; /*!< (@ 0x00000200) Scan Group Diagnosis Function Control Register + * 0 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR0_b; + }; + + union + { + __IOM uint32_t ADSGDCR1; /*!< (@ 0x00000204) Scan Group Diagnosis Function Control Register + * 1 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR1_b; + }; + + union + { + __IOM uint32_t ADSGDCR2; /*!< (@ 0x00000208) Scan Group Diagnosis Function Control Register + * 2 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR2_b; + }; + + union + { + __IOM uint32_t ADSGDCR3; /*!< (@ 0x0000020C) Scan Group Diagnosis Function Control Register + * 3 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR3_b; + }; + + union + { + __IOM uint32_t ADSGDCR4; /*!< (@ 0x00000210) Scan Group Diagnosis Function Control Register + * 4 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR4_b; + }; + + union + { + __IOM uint32_t ADSGDCR5; /*!< (@ 0x00000214) Scan Group Diagnosis Function Control Register + * 5 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR5_b; + }; + + union + { + __IOM uint32_t ADSGDCR6; /*!< (@ 0x00000218) Scan Group Diagnosis Function Control Register + * 6 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR6_b; + }; + + union + { + __IOM uint32_t ADSGDCR7; /*!< (@ 0x0000021C) Scan Group Diagnosis Function Control Register + * 7 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR7_b; + }; + + union + { + __IOM uint32_t ADSGDCR8; /*!< (@ 0x00000220) Scan Group Diagnosis Function Control Register + * 8 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR8_b; + }; + __IM uint32_t RESERVED14[7]; + + union + { + __IOM uint32_t ADSSTR0; /*!< (@ 0x00000240) Sampling State Table Register 0 */ + + struct + { + __IOM uint32_t SST0 : 10; /*!< [9..0] Sampling State Table 0 */ + uint32_t : 6; + __IOM uint32_t SST1 : 10; /*!< [25..16] Sampling State Table 1 */ + uint32_t : 6; + } ADSSTR0_b; + }; + + union + { + __IOM uint32_t ADSSTR1; /*!< (@ 0x00000244) Sampling State Table Register 1 */ + + struct + { + __IOM uint32_t SST2 : 10; /*!< [9..0] Sampling State Table 2 */ + uint32_t : 6; + __IOM uint32_t SST3 : 10; /*!< [25..16] Sampling State Table 3 */ + uint32_t : 6; + } ADSSTR1_b; + }; + + union + { + __IOM uint32_t ADSSTR2; /*!< (@ 0x00000248) Sampling State Table Register 2 */ + + struct + { + __IOM uint32_t SST4 : 10; /*!< [9..0] Sampling State Table 4 */ + uint32_t : 6; + __IOM uint32_t SST5 : 10; /*!< [25..16] Sampling State Table 5 */ + uint32_t : 6; + } ADSSTR2_b; + }; + + union + { + __IOM uint32_t ADSSTR3; /*!< (@ 0x0000024C) Sampling State Table Register 3 */ + + struct + { + __IOM uint32_t SST6 : 10; /*!< [9..0] Sampling State Table 6 */ + uint32_t : 6; + __IOM uint32_t SST7 : 10; /*!< [25..16] Sampling State Table 7 */ + uint32_t : 6; + } ADSSTR3_b; + }; + + union + { + __IOM uint32_t ADSSTR4; /*!< (@ 0x00000250) Sampling State Table Register 4 */ + + struct + { + __IOM uint32_t SST8 : 10; /*!< [9..0] Sampling State Table 8 */ + uint32_t : 6; + __IOM uint32_t SST9 : 10; /*!< [25..16] Sampling State Table 9 */ + uint32_t : 6; + } ADSSTR4_b; + }; + + union + { + __IOM uint32_t ADSSTR5; /*!< (@ 0x00000254) Sampling State Table Register 5 */ + + struct + { + __IOM uint32_t SST10 : 10; /*!< [9..0] Sampling State Table 10 */ + uint32_t : 6; + __IOM uint32_t SST11 : 10; /*!< [25..16] Sampling State Table 11 */ + uint32_t : 6; + } ADSSTR5_b; + }; + + union + { + __IOM uint32_t ADSSTR6; /*!< (@ 0x00000258) Sampling State Table Register 6 */ + + struct + { + __IOM uint32_t SST12 : 10; /*!< [9..0] Sampling State Table 12 */ + uint32_t : 6; + __IOM uint32_t SST13 : 10; /*!< [25..16] Sampling State Table 13 */ + uint32_t : 6; + } ADSSTR6_b; + }; + + union + { + __IOM uint32_t ADSSTR7; /*!< (@ 0x0000025C) Sampling State Table Register 7 */ + + struct + { + __IOM uint32_t SST14 : 10; /*!< [9..0] Sampling State Table 14 */ + uint32_t : 6; + __IOM uint32_t SST15 : 10; /*!< [25..16] Sampling State Table 15 */ + uint32_t : 6; + } ADSSTR7_b; + }; + + union + { + __IOM uint32_t ADCNVSTR; /*!< (@ 0x00000260) A/D Conversion State Register */ + + struct + { + __IOM uint32_t CST0 : 6; /*!< [5..0] A/D Converter Unit 0 (ADC0) */ + uint32_t : 2; + __IOM uint32_t CST1 : 6; /*!< [13..8] A/D Converter Unit 1 (ADC1) */ + uint32_t : 18; + } ADCNVSTR_b; + }; + + union + { + __IOM uint32_t ADCALSTCR; /*!< (@ 0x00000264) A/D Converter Calibration State Register */ + + struct + { + __IOM uint32_t CALADSST : 10; /*!< [9..0] A/D Converter Calibration Sampling Time Configuration */ + uint32_t : 6; + __IOM uint32_t CALADCST : 6; /*!< [21..16] A/D Converter Calibration Conversion Time Configuration. */ + uint32_t : 10; + } ADCALSTCR_b; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t ADSHCR0; /*!< (@ 0x00000280) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 0 */ + + struct + { + __IOM uint32_t SHEN0 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 Select */ + __IOM uint32_t SHEN1 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 1 Select */ + __IOM uint32_t SHEN2 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 2 Select */ + uint32_t : 13; + __IOM uint32_t SHMD0 : 1; /*!< [16..16] Channel-dedicated Sample-and-hold Circuit Unit 0 Input + * Mode Select */ + __IOM uint32_t SHMD1 : 1; /*!< [17..17] Channel-dedicated Sample-and-hold Circuit Unit 1 Input + * Mode Select */ + __IOM uint32_t SHMD2 : 1; /*!< [18..18] Channel-dedicated Sample-and-hold Circuit Unit 2 Input + * Mode Select */ + uint32_t : 13; + } ADSHCR0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t ADSHSTR0; /*!< (@ 0x00000288) Channel-Dedicated Sample & Hold Circuit State + * Register 0 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to 2 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to + * 2 */ + uint32_t : 13; + } ADSHSTR0_b; + }; + + union + { + __IOM uint32_t ADSHCR1; /*!< (@ 0x0000028C) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 1 */ + + struct + { + __IOM uint32_t SHEN4 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 Select */ + __IOM uint32_t SHEN5 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 5 Select */ + __IOM uint32_t SHEN6 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 6 Select */ + uint32_t : 13; + __IOM uint32_t SHMD4 : 1; /*!< [16..16] Channel-dedicated Sample-and-hold Circuit Unit 4 Input + * Mode Select */ + __IOM uint32_t SHMD5 : 1; /*!< [17..17] Channel-dedicated Sample-and-hold Circuit Unit 5 Input + * Mode Select */ + __IOM uint32_t SHMD6 : 1; /*!< [18..18] Channel-dedicated Sample-and-hold Circuit Unit 6 Input + * Mode Select */ + uint32_t : 13; + } ADSHCR1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t ADSHSTR1; /*!< (@ 0x00000294) Channel-Dedicated Sample & Hold Circuit State + * Register 1 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to 6 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to + * 6 */ + uint32_t : 13; + } ADSHSTR1_b; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t ADCALSHCR; /*!< (@ 0x000002B0) Channel-Dedicated Sample & Hold Circuit Calibration + * State Register */ + + struct + { + __IOM uint32_t CALSHSST : 8; /*!< [7..0] Channel-Dedicated Sample & Hold Circuit Calibration Sampling + * Time Configuration */ + uint32_t : 8; + __IOM uint32_t CALSHHST : 3; /*!< [18..16] Channel-Dedicated Sample & Hold Circuit Calibration + * Holding Time Configuration */ + uint32_t : 13; + } ADCALSHCR_b; + }; + __IM uint32_t RESERVED19[27]; + + union + { + __IOM uint32_t ADREFCR; /*!< (@ 0x00000320) Internal Reference Voltage Monitor Enable Register */ + + struct + { + __IOM uint32_t VDE : 1; /*!< [0..0] Internal Reference Voltage A/D Conversion Select */ + uint32_t : 31; + } ADREFCR_b; + }; + __IM uint32_t RESERVED20[7]; + + union + { + __IOM uint32_t ADDFSR0; /*!< (@ 0x00000340) A/D Converter Digital Filter Selection Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR0_b; + }; + + union + { + __IOM uint32_t ADDFSR1; /*!< (@ 0x00000344) A/D Converter Digital Filter Selection Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR1_b; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t ADUOFTR0; /*!< (@ 0x00000360) User Offset Table Register 0 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR0_b; + }; + + union + { + __IOM uint32_t ADUOFTR1; /*!< (@ 0x00000364) User Offset Table Register 1 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR1_b; + }; + + union + { + __IOM uint32_t ADUOFTR2; /*!< (@ 0x00000368) User Offset Table Register 2 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR2_b; + }; + + union + { + __IOM uint32_t ADUOFTR3; /*!< (@ 0x0000036C) User Offset Table Register 3 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR3_b; + }; + + union + { + __IOM uint32_t ADUOFTR4; /*!< (@ 0x00000370) User Offset Table Register 4 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR4_b; + }; + + union + { + __IOM uint32_t ADUOFTR5; /*!< (@ 0x00000374) User Offset Table Register 5 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR5_b; + }; + + union + { + __IOM uint32_t ADUOFTR6; /*!< (@ 0x00000378) User Offset Table Register 6 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR6_b; + }; + + union + { + __IOM uint32_t ADUOFTR7; /*!< (@ 0x0000037C) User Offset Table Register 7 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR7_b; + }; + + union + { + __IOM uint32_t ADUGTR0; /*!< (@ 0x00000380) User Gain Table Register 0 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR0_b; + }; + + union + { + __IOM uint32_t ADUGTR1; /*!< (@ 0x00000384) User Gain Table Register 1 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR1_b; + }; + + union + { + __IOM uint32_t ADUGTR2; /*!< (@ 0x00000388) User Gain Table Register 2 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR2_b; + }; + + union + { + __IOM uint32_t ADUGTR3; /*!< (@ 0x0000038C) User Gain Table Register 3 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR3_b; + }; + + union + { + __IOM uint32_t ADUGTR4; /*!< (@ 0x00000390) User Gain Table Register 4 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR4_b; + }; + + union + { + __IOM uint32_t ADUGTR5; /*!< (@ 0x00000394) User Gain Table Register 5 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR5_b; + }; + + union + { + __IOM uint32_t ADUGTR6; /*!< (@ 0x00000398) User Gain Table Register 6 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR6_b; + }; + + union + { + __IOM uint32_t ADUGTR7; /*!< (@ 0x0000039C) User Gain Table Register 7 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR7_b; + }; + + union + { + __IOM uint32_t ADLIMINTCR; /*!< (@ 0x000003A0) Limiter Clip Interrupt Enable Register */ + + struct + { + __IOM uint32_t LIMIEn : 9; /*!< [8..0] Limiter Clip Interrupt n Enable bit */ + uint32_t : 23; + } ADLIMINTCR_b; + }; + + union + { + __IOM uint32_t ADLIMTR0; /*!< (@ 0x000003A4) Limiter Clip Table Register 0 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR0_b; + }; + + union + { + __IOM uint32_t ADLIMTR1; /*!< (@ 0x000003A8) Limiter Clip Table Register 1 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR1_b; + }; + + union + { + __IOM uint32_t ADLIMTR2; /*!< (@ 0x000003AC) Limiter Clip Table Register 2 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR2_b; + }; + + union + { + __IOM uint32_t ADLIMTR3; /*!< (@ 0x000003B0) Limiter Clip Table Register 3 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR3_b; + }; + + union + { + __IOM uint32_t ADLIMTR4; /*!< (@ 0x000003B4) Limiter Clip Table Register 4 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR4_b; + }; + + union + { + __IOM uint32_t ADLIMTR5; /*!< (@ 0x000003B8) Limiter Clip Table Register 5 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR5_b; + }; + + union + { + __IOM uint32_t ADLIMTR6; /*!< (@ 0x000003BC) Limiter Clip Table Register 6 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR6_b; + }; + + union + { + __IOM uint32_t ADLIMTR7; /*!< (@ 0x000003C0) Limiter Clip Table Register 7 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR7_b; + }; + __IM uint32_t RESERVED22[15]; + + union + { + __IOM uint32_t ADCMPENR; /*!< (@ 0x00000400) Compare Match Enable Register */ + + struct + { + __IOM uint32_t CMPENn : 8; /*!< [7..0] Compare Match n Enable */ + uint32_t : 24; + } ADCMPENR_b; + }; + + union + { + __IOM uint32_t ADCMPINTCR; /*!< (@ 0x00000404) Compare Match Interrupt Enable Register */ + + struct + { + __IOM uint32_t CMPIEn : 4; /*!< [3..0] Compare Match Interrupt n Enable */ + uint32_t : 28; + } ADCMPINTCR_b; + }; + + union + { + __IOM uint32_t ADCCMPCR0; /*!< (@ 0x00000408) Composite Compare Match Configuration Register + * 0 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR0_b; + }; + + union + { + __IOM uint32_t ADCCMPCR1; /*!< (@ 0x0000040C) Composite Compare Match Configuration Register + * 1 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR1_b; + }; + __IM uint32_t RESERVED23[14]; + + union + { + __IOM uint32_t ADCMPMDR0; /*!< (@ 0x00000448) Compare Match Mode Selection Register 0 */ + + struct + { + __IOM uint32_t CMPMD0 : 2; /*!< [1..0] Compare Match 0 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD1 : 2; /*!< [9..8] Compare Match 1 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD2 : 2; /*!< [17..16] Compare Match 2 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD3 : 2; /*!< [25..24] Compare Match 3 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR0_b; + }; + + union + { + __IOM uint32_t ADCMPMDR1; /*!< (@ 0x0000044C) Compare Match Mode Selection Register 1 */ + + struct + { + __IOM uint32_t CMPMD4 : 2; /*!< [1..0] Compare Match 4 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD5 : 2; /*!< [9..8] Compare Match 5 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD6 : 2; /*!< [17..16] Compare Match 6 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD7 : 2; /*!< [25..24] Compare Match 7 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR1_b; + }; + __IM uint32_t RESERVED24[2]; + + union + { + __IOM uint32_t ADCMPTBR0; /*!< (@ 0x00000458) Compare Match Table Register 0 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR0_b; + }; + + union + { + __IOM uint32_t ADCMPTBR1; /*!< (@ 0x0000045C) Compare Match Table Register 1 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR1_b; + }; + + union + { + __IOM uint32_t ADCMPTBR2; /*!< (@ 0x00000460) Compare Match Table Register 2 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR2_b; + }; + + union + { + __IOM uint32_t ADCMPTBR3; /*!< (@ 0x00000464) Compare Match Table Register 3 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR3_b; + }; + + union + { + __IOM uint32_t ADCMPTBR4; /*!< (@ 0x00000468) Compare Match Table Register 4 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR4_b; + }; + + union + { + __IOM uint32_t ADCMPTBR5; /*!< (@ 0x0000046C) Compare Match Table Register 5 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR5_b; + }; + + union + { + __IOM uint32_t ADCMPTBR6; /*!< (@ 0x00000470) Compare Match Table Register 6 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR6_b; + }; + + union + { + __IOM uint32_t ADCMPTBR7; /*!< (@ 0x00000474) Compare Match Table Register 7 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR7_b; + }; + __IM uint32_t RESERVED25[18]; + + union + { + __IOM uint32_t ADFIFOCR; /*!< (@ 0x000004C0) FIFO Control Register */ + + struct + { + __IOM uint32_t FIFOEN0 : 1; /*!< [0..0] Scan Group 0 FIFO Enable */ + __IOM uint32_t FIFOEN1 : 1; /*!< [1..1] Scan Group 1 FIFO Enable */ + __IOM uint32_t FIFOEN2 : 1; /*!< [2..2] Scan Group 2 FIFO Enable */ + __IOM uint32_t FIFOEN3 : 1; /*!< [3..3] Scan Group 3 FIFO Enable */ + __IOM uint32_t FIFOEN4 : 1; /*!< [4..4] Scan Group 4 FIFO Enable */ + __IOM uint32_t FIFOEN5 : 1; /*!< [5..5] Scan Group 5 FIFO Enable */ + __IOM uint32_t FIFOEN6 : 1; /*!< [6..6] Scan Group 6 FIFO Enable */ + __IOM uint32_t FIFOEN7 : 1; /*!< [7..7] Scan Group 7 FIFO Enable */ + __IOM uint32_t FIFOEN8 : 1; /*!< [8..8] Scan Group 8 FIFO Enable */ + uint32_t : 23; + } ADFIFOCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTCR; /*!< (@ 0x000004C4) FIFO Interrupt Control Register */ + + struct + { + __IOM uint32_t FIFOIE0 : 1; /*!< [0..0] Scan Group 0 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE1 : 1; /*!< [1..1] Scan Group 1 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE2 : 1; /*!< [2..2] Scan Group 2 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE3 : 1; /*!< [3..3] Scan Group 3 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE4 : 1; /*!< [4..4] Scan Group 4 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE5 : 1; /*!< [5..5] Scan Group 5 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE6 : 1; /*!< [6..6] Scan Group 6 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE7 : 1; /*!< [7..7] Scan Group 7 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE8 : 1; /*!< [8..8] Scan Group 8 FIFO Interrupt Enable */ + uint32_t : 23; + } ADFIFOINTCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR0; /*!< (@ 0x000004C8) FIFO Interrupt Generation Level Register 0 */ + + struct + { + __IOM uint32_t FIFOILV0 : 4; /*!< [3..0] Scan Group 0 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV1 : 4; /*!< [19..16] Scan Group 1 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR0_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR1; /*!< (@ 0x000004CC) FIFO Interrupt Generation Level Register 1 */ + + struct + { + __IOM uint32_t FIFOILV2 : 4; /*!< [3..0] Scan Group 2 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV3 : 4; /*!< [19..16] Scan Group 3 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR1_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR2; /*!< (@ 0x000004D0) FIFO Interrupt Generation Level Register 2 */ + + struct + { + __IOM uint32_t FIFOILV4 : 4; /*!< [3..0] Scan Group 4 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV5 : 4; /*!< [19..16] Scan Group 5 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR2_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR3; /*!< (@ 0x000004D4) FIFO Interrupt Generation Level Register 3 */ + + struct + { + __IOM uint32_t FIFOILV6 : 4; /*!< [3..0] Scan Group 6 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV7 : 4; /*!< [19..16] Scan Group 7 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR3_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR4; /*!< (@ 0x000004D8) FIFO Interrupt Generation Level Register 4 */ + + struct + { + __IOM uint32_t FIFOILV8 : 4; /*!< [3..0] Scan Group 8 FIFO Interrupt Output Timing Setting */ + uint32_t : 28; + } ADFIFOINTLR4_b; + }; + __IM uint32_t RESERVED26[73]; + + union + { + __IOM uint32_t ADCHCR0; /*!< (@ 0x00000600) A/D Conversion Channel Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR0_b; + }; + + union + { + __IOM uint32_t ADDOPCRA0; /*!< (@ 0x00000604) A/D Conversion Data Operation Control A Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA0_b; + }; + + union + { + __IOM uint32_t ADDOPCRB0; /*!< (@ 0x00000608) A/D Conversion Data Operation Control B Register + * 0 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB0_b; + }; + + union + { + __IOM uint32_t ADDOPCRC0; /*!< (@ 0x0000060C) A/D Conversion Data Operation Control C Register + * 0 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC0_b; + }; + + union + { + __IOM uint32_t ADCHCR1; /*!< (@ 0x00000610) A/D Conversion Channel Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR1_b; + }; + + union + { + __IOM uint32_t ADDOPCRA1; /*!< (@ 0x00000614) A/D Conversion Data Operation Control A Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA1_b; + }; + + union + { + __IOM uint32_t ADDOPCRB1; /*!< (@ 0x00000618) A/D Conversion Data Operation Control B Register + * 1 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB1_b; + }; + + union + { + __IOM uint32_t ADDOPCRC1; /*!< (@ 0x0000061C) A/D Conversion Data Operation Control C Register + * 1 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC1_b; + }; + + union + { + __IOM uint32_t ADCHCR2; /*!< (@ 0x00000620) A/D Conversion Channel Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR2_b; + }; + + union + { + __IOM uint32_t ADDOPCRA2; /*!< (@ 0x00000624) A/D Conversion Data Operation Control A Register + * 2 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA2_b; + }; + + union + { + __IOM uint32_t ADDOPCRB2; /*!< (@ 0x00000628) A/D Conversion Data Operation Control B Register + * 2 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB2_b; + }; + + union + { + __IOM uint32_t ADDOPCRC2; /*!< (@ 0x0000062C) A/D Conversion Data Operation Control C Register + * 2 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC2_b; + }; + + union + { + __IOM uint32_t ADCHCR3; /*!< (@ 0x00000630) A/D Conversion Channel Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR3_b; + }; + + union + { + __IOM uint32_t ADDOPCRA3; /*!< (@ 0x00000634) A/D Conversion Data Operation Control A Register + * 3 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA3_b; + }; + + union + { + __IOM uint32_t ADDOPCRB3; /*!< (@ 0x00000638) A/D Conversion Data Operation Control B Register + * 3 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB3_b; + }; + + union + { + __IOM uint32_t ADDOPCRC3; /*!< (@ 0x0000063C) A/D Conversion Data Operation Control C Register + * 3 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC3_b; + }; + + union + { + __IOM uint32_t ADCHCR4; /*!< (@ 0x00000640) A/D Conversion Channel Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR4_b; + }; + + union + { + __IOM uint32_t ADDOPCRA4; /*!< (@ 0x00000644) A/D Conversion Data Operation Control A Register + * 4 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA4_b; + }; + + union + { + __IOM uint32_t ADDOPCRB4; /*!< (@ 0x00000648) A/D Conversion Data Operation Control B Register + * 4 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB4_b; + }; + + union + { + __IOM uint32_t ADDOPCRC4; /*!< (@ 0x0000064C) A/D Conversion Data Operation Control C Register + * 4 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC4_b; + }; + + union + { + __IOM uint32_t ADCHCR5; /*!< (@ 0x00000650) A/D Conversion Channel Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR5_b; + }; + + union + { + __IOM uint32_t ADDOPCRA5; /*!< (@ 0x00000654) A/D Conversion Data Operation Control A Register + * 5 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA5_b; + }; + + union + { + __IOM uint32_t ADDOPCRB5; /*!< (@ 0x00000658) A/D Conversion Data Operation Control B Register + * 5 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB5_b; + }; + + union + { + __IOM uint32_t ADDOPCRC5; /*!< (@ 0x0000065C) A/D Conversion Data Operation Control C Register + * 5 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC5_b; + }; + + union + { + __IOM uint32_t ADCHCR6; /*!< (@ 0x00000660) A/D Conversion Channel Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR6_b; + }; + + union + { + __IOM uint32_t ADDOPCRA6; /*!< (@ 0x00000664) A/D Conversion Data Operation Control A Register + * 6 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA6_b; + }; + + union + { + __IOM uint32_t ADDOPCRB6; /*!< (@ 0x00000668) A/D Conversion Data Operation Control B Register + * 6 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB6_b; + }; + + union + { + __IOM uint32_t ADDOPCRC6; /*!< (@ 0x0000066C) A/D Conversion Data Operation Control C Register + * 6 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC6_b; + }; + + union + { + __IOM uint32_t ADCHCR7; /*!< (@ 0x00000670) A/D Conversion Channel Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR7_b; + }; + + union + { + __IOM uint32_t ADDOPCRA7; /*!< (@ 0x00000674) A/D Conversion Data Operation Control A Register + * 7 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA7_b; + }; + + union + { + __IOM uint32_t ADDOPCRB7; /*!< (@ 0x00000678) A/D Conversion Data Operation Control B Register + * 7 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB7_b; + }; + + union + { + __IOM uint32_t ADDOPCRC7; /*!< (@ 0x0000067C) A/D Conversion Data Operation Control C Register + * 7 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC7_b; + }; + + union + { + __IOM uint32_t ADCHCR8; /*!< (@ 0x00000680) A/D Conversion Channel Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR8_b; + }; + + union + { + __IOM uint32_t ADDOPCRA8; /*!< (@ 0x00000684) A/D Conversion Data Operation Control A Register + * 8 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA8_b; + }; + + union + { + __IOM uint32_t ADDOPCRB8; /*!< (@ 0x00000688) A/D Conversion Data Operation Control B Register + * 8 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB8_b; + }; + + union + { + __IOM uint32_t ADDOPCRC8; /*!< (@ 0x0000068C) A/D Conversion Data Operation Control C Register + * 8 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC8_b; + }; + + union + { + __IOM uint32_t ADCHCR9; /*!< (@ 0x00000690) A/D Conversion Channel Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR9_b; + }; + + union + { + __IOM uint32_t ADDOPCRA9; /*!< (@ 0x00000694) A/D Conversion Data Operation Control A Register + * 9 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA9_b; + }; + + union + { + __IOM uint32_t ADDOPCRB9; /*!< (@ 0x00000698) A/D Conversion Data Operation Control B Register + * 9 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB9_b; + }; + + union + { + __IOM uint32_t ADDOPCRC9; /*!< (@ 0x0000069C) A/D Conversion Data Operation Control C Register + * 9 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC9_b; + }; + + union + { + __IOM uint32_t ADCHCR10; /*!< (@ 0x000006A0) A/D Conversion Channel Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR10_b; + }; + + union + { + __IOM uint32_t ADDOPCRA10; /*!< (@ 0x000006A4) A/D Conversion Data Operation Control A Register + * 10 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA10_b; + }; + + union + { + __IOM uint32_t ADDOPCRB10; /*!< (@ 0x000006A8) A/D Conversion Data Operation Control B Register + * 10 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB10_b; + }; + + union + { + __IOM uint32_t ADDOPCRC10; /*!< (@ 0x000006AC) A/D Conversion Data Operation Control C Register + * 10 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC10_b; + }; + + union + { + __IOM uint32_t ADCHCR11; /*!< (@ 0x000006B0) A/D Conversion Channel Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR11_b; + }; + + union + { + __IOM uint32_t ADDOPCRA11; /*!< (@ 0x000006B4) A/D Conversion Data Operation Control A Register + * 11 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA11_b; + }; + + union + { + __IOM uint32_t ADDOPCRB11; /*!< (@ 0x000006B8) A/D Conversion Data Operation Control B Register + * 11 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB11_b; + }; + + union + { + __IOM uint32_t ADDOPCRC11; /*!< (@ 0x000006BC) A/D Conversion Data Operation Control C Register + * 11 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC11_b; + }; + + union + { + __IOM uint32_t ADCHCR12; /*!< (@ 0x000006C0) A/D Conversion Channel Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR12_b; + }; + + union + { + __IOM uint32_t ADDOPCRA12; /*!< (@ 0x000006C4) A/D Conversion Data Operation Control A Register + * 12 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA12_b; + }; + + union + { + __IOM uint32_t ADDOPCRB12; /*!< (@ 0x000006C8) A/D Conversion Data Operation Control B Register + * 12 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB12_b; + }; + + union + { + __IOM uint32_t ADDOPCRC12; /*!< (@ 0x000006CC) A/D Conversion Data Operation Control C Register + * 12 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC12_b; + }; + + union + { + __IOM uint32_t ADCHCR13; /*!< (@ 0x000006D0) A/D Conversion Channel Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR13_b; + }; + + union + { + __IOM uint32_t ADDOPCRA13; /*!< (@ 0x000006D4) A/D Conversion Data Operation Control A Register + * 13 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA13_b; + }; + + union + { + __IOM uint32_t ADDOPCRB13; /*!< (@ 0x000006D8) A/D Conversion Data Operation Control B Register + * 13 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB13_b; + }; + + union + { + __IOM uint32_t ADDOPCRC13; /*!< (@ 0x000006DC) A/D Conversion Data Operation Control C Register + * 13 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC13_b; + }; + + union + { + __IOM uint32_t ADCHCR14; /*!< (@ 0x000006E0) A/D Conversion Channel Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR14_b; + }; + + union + { + __IOM uint32_t ADDOPCRA14; /*!< (@ 0x000006E4) A/D Conversion Data Operation Control A Register + * 14 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA14_b; + }; + + union + { + __IOM uint32_t ADDOPCRB14; /*!< (@ 0x000006E8) A/D Conversion Data Operation Control B Register + * 14 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB14_b; + }; + + union + { + __IOM uint32_t ADDOPCRC14; /*!< (@ 0x000006EC) A/D Conversion Data Operation Control C Register + * 14 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC14_b; + }; + + union + { + __IOM uint32_t ADCHCR15; /*!< (@ 0x000006F0) A/D Conversion Channel Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR15_b; + }; + + union + { + __IOM uint32_t ADDOPCRA15; /*!< (@ 0x000006F4) A/D Conversion Data Operation Control A Register + * 15 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA15_b; + }; + + union + { + __IOM uint32_t ADDOPCRB15; /*!< (@ 0x000006F8) A/D Conversion Data Operation Control B Register + * 15 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB15_b; + }; + + union + { + __IOM uint32_t ADDOPCRC15; /*!< (@ 0x000006FC) A/D Conversion Data Operation Control C Register + * 15 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC15_b; + }; + + union + { + __IOM uint32_t ADCHCR16; /*!< (@ 0x00000700) A/D Conversion Channel Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR16_b; + }; + + union + { + __IOM uint32_t ADDOPCRA16; /*!< (@ 0x00000704) A/D Conversion Data Operation Control A Register + * 16 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA16_b; + }; + + union + { + __IOM uint32_t ADDOPCRB16; /*!< (@ 0x00000708) A/D Conversion Data Operation Control B Register + * 16 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB16_b; + }; + + union + { + __IOM uint32_t ADDOPCRC16; /*!< (@ 0x0000070C) A/D Conversion Data Operation Control C Register + * 16 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC16_b; + }; + + union + { + __IOM uint32_t ADCHCR17; /*!< (@ 0x00000710) A/D Conversion Channel Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR17_b; + }; + + union + { + __IOM uint32_t ADDOPCRA17; /*!< (@ 0x00000714) A/D Conversion Data Operation Control A Register + * 17 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA17_b; + }; + + union + { + __IOM uint32_t ADDOPCRB17; /*!< (@ 0x00000718) A/D Conversion Data Operation Control B Register + * 17 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB17_b; + }; + + union + { + __IOM uint32_t ADDOPCRC17; /*!< (@ 0x0000071C) A/D Conversion Data Operation Control C Register + * 17 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC17_b; + }; + + union + { + __IOM uint32_t ADCHCR18; /*!< (@ 0x00000720) A/D Conversion Channel Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR18_b; + }; + + union + { + __IOM uint32_t ADDOPCRA18; /*!< (@ 0x00000724) A/D Conversion Data Operation Control A Register + * 18 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA18_b; + }; + + union + { + __IOM uint32_t ADDOPCRB18; /*!< (@ 0x00000728) A/D Conversion Data Operation Control B Register + * 18 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB18_b; + }; + + union + { + __IOM uint32_t ADDOPCRC18; /*!< (@ 0x0000072C) A/D Conversion Data Operation Control C Register + * 18 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC18_b; + }; + + union + { + __IOM uint32_t ADCHCR19; /*!< (@ 0x00000730) A/D Conversion Channel Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR19_b; + }; + + union + { + __IOM uint32_t ADDOPCRA19; /*!< (@ 0x00000734) A/D Conversion Data Operation Control A Register + * 19 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA19_b; + }; + + union + { + __IOM uint32_t ADDOPCRB19; /*!< (@ 0x00000738) A/D Conversion Data Operation Control B Register + * 19 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB19_b; + }; + + union + { + __IOM uint32_t ADDOPCRC19; /*!< (@ 0x0000073C) A/D Conversion Data Operation Control C Register + * 19 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC19_b; + }; + + union + { + __IOM uint32_t ADCHCR20; /*!< (@ 0x00000740) A/D Conversion Channel Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR20_b; + }; + + union + { + __IOM uint32_t ADDOPCRA20; /*!< (@ 0x00000744) A/D Conversion Data Operation Control A Register + * 20 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA20_b; + }; + + union + { + __IOM uint32_t ADDOPCRB20; /*!< (@ 0x00000748) A/D Conversion Data Operation Control B Register + * 20 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB20_b; + }; + + union + { + __IOM uint32_t ADDOPCRC20; /*!< (@ 0x0000074C) A/D Conversion Data Operation Control C Register + * 20 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC20_b; + }; + + union + { + __IOM uint32_t ADCHCR21; /*!< (@ 0x00000750) A/D Conversion Channel Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR21_b; + }; + + union + { + __IOM uint32_t ADDOPCRA21; /*!< (@ 0x00000754) A/D Conversion Data Operation Control A Register + * 21 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA21_b; + }; + + union + { + __IOM uint32_t ADDOPCRB21; /*!< (@ 0x00000758) A/D Conversion Data Operation Control B Register + * 21 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB21_b; + }; + + union + { + __IOM uint32_t ADDOPCRC21; /*!< (@ 0x0000075C) A/D Conversion Data Operation Control C Register + * 21 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC21_b; + }; + + union + { + __IOM uint32_t ADCHCR22; /*!< (@ 0x00000760) A/D Conversion Channel Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR22_b; + }; + + union + { + __IOM uint32_t ADDOPCRA22; /*!< (@ 0x00000764) A/D Conversion Data Operation Control A Register + * 22 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA22_b; + }; + + union + { + __IOM uint32_t ADDOPCRB22; /*!< (@ 0x00000768) A/D Conversion Data Operation Control B Register + * 22 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB22_b; + }; + + union + { + __IOM uint32_t ADDOPCRC22; /*!< (@ 0x0000076C) A/D Conversion Data Operation Control C Register + * 22 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC22_b; + }; + + union + { + __IOM uint32_t ADCHCR23; /*!< (@ 0x00000770) A/D Conversion Channel Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR23_b; + }; + + union + { + __IOM uint32_t ADDOPCRA23; /*!< (@ 0x00000774) A/D Conversion Data Operation Control A Register + * 23 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA23_b; + }; + + union + { + __IOM uint32_t ADDOPCRB23; /*!< (@ 0x00000778) A/D Conversion Data Operation Control B Register + * 23 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB23_b; + }; + + union + { + __IOM uint32_t ADDOPCRC23; /*!< (@ 0x0000077C) A/D Conversion Data Operation Control C Register + * 23 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC23_b; + }; + + union + { + __IOM uint32_t ADCHCR24; /*!< (@ 0x00000780) A/D Conversion Channel Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR24_b; + }; + + union + { + __IOM uint32_t ADDOPCRA24; /*!< (@ 0x00000784) A/D Conversion Data Operation Control A Register + * 24 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA24_b; + }; + + union + { + __IOM uint32_t ADDOPCRB24; /*!< (@ 0x00000788) A/D Conversion Data Operation Control B Register + * 24 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB24_b; + }; + + union + { + __IOM uint32_t ADDOPCRC24; /*!< (@ 0x0000078C) A/D Conversion Data Operation Control C Register + * 24 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC24_b; + }; + + union + { + __IOM uint32_t ADCHCR25; /*!< (@ 0x00000790) A/D Conversion Channel Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR25_b; + }; + + union + { + __IOM uint32_t ADDOPCRA25; /*!< (@ 0x00000794) A/D Conversion Data Operation Control A Register + * 25 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA25_b; + }; + + union + { + __IOM uint32_t ADDOPCRB25; /*!< (@ 0x00000798) A/D Conversion Data Operation Control B Register + * 25 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB25_b; + }; + + union + { + __IOM uint32_t ADDOPCRC25; /*!< (@ 0x0000079C) A/D Conversion Data Operation Control C Register + * 25 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC25_b; + }; + + union + { + __IOM uint32_t ADCHCR26; /*!< (@ 0x000007A0) A/D Conversion Channel Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR26_b; + }; + + union + { + __IOM uint32_t ADDOPCRA26; /*!< (@ 0x000007A4) A/D Conversion Data Operation Control A Register + * 26 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA26_b; + }; + + union + { + __IOM uint32_t ADDOPCRB26; /*!< (@ 0x000007A8) A/D Conversion Data Operation Control B Register + * 26 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB26_b; + }; + + union + { + __IOM uint32_t ADDOPCRC26; /*!< (@ 0x000007AC) A/D Conversion Data Operation Control C Register + * 26 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC26_b; + }; + + union + { + __IOM uint32_t ADCHCR27; /*!< (@ 0x000007B0) A/D Conversion Channel Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR27_b; + }; + + union + { + __IOM uint32_t ADDOPCRA27; /*!< (@ 0x000007B4) A/D Conversion Data Operation Control A Register + * 27 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA27_b; + }; + + union + { + __IOM uint32_t ADDOPCRB27; /*!< (@ 0x000007B8) A/D Conversion Data Operation Control B Register + * 27 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB27_b; + }; + + union + { + __IOM uint32_t ADDOPCRC27; /*!< (@ 0x000007BC) A/D Conversion Data Operation Control C Register + * 27 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC27_b; + }; + + union + { + __IOM uint32_t ADCHCR28; /*!< (@ 0x000007C0) A/D Conversion Channel Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR28_b; + }; + + union + { + __IOM uint32_t ADDOPCRA28; /*!< (@ 0x000007C4) A/D Conversion Data Operation Control A Register + * 28 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA28_b; + }; + + union + { + __IOM uint32_t ADDOPCRB28; /*!< (@ 0x000007C8) A/D Conversion Data Operation Control B Register + * 28 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB28_b; + }; + + union + { + __IOM uint32_t ADDOPCRC28; /*!< (@ 0x000007CC) A/D Conversion Data Operation Control C Register + * 28 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC28_b; + }; + + union + { + __IOM uint32_t ADCHCR29; /*!< (@ 0x000007D0) A/D Conversion Channel Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR29_b; + }; + + union + { + __IOM uint32_t ADDOPCRA29; /*!< (@ 0x000007D4) A/D Conversion Data Operation Control A Register + * 29 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA29_b; + }; + + union + { + __IOM uint32_t ADDOPCRB29; /*!< (@ 0x000007D8) A/D Conversion Data Operation Control B Register + * 29 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB29_b; + }; + + union + { + __IOM uint32_t ADDOPCRC29; /*!< (@ 0x000007DC) A/D Conversion Data Operation Control C Register + * 29 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC29_b; + }; + + union + { + __IOM uint32_t ADCHCR30; /*!< (@ 0x000007E0) A/D Conversion Channel Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR30_b; + }; + + union + { + __IOM uint32_t ADDOPCRA30; /*!< (@ 0x000007E4) A/D Conversion Data Operation Control A Register + * 30 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA30_b; + }; + + union + { + __IOM uint32_t ADDOPCRB30; /*!< (@ 0x000007E8) A/D Conversion Data Operation Control B Register + * 30 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB30_b; + }; + + union + { + __IOM uint32_t ADDOPCRC30; /*!< (@ 0x000007EC) A/D Conversion Data Operation Control C Register + * 30 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC30_b; + }; + + union + { + __IOM uint32_t ADCHCR31; /*!< (@ 0x000007F0) A/D Conversion Channel Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR31_b; + }; + + union + { + __IOM uint32_t ADDOPCRA31; /*!< (@ 0x000007F4) A/D Conversion Data Operation Control A Register + * 31 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA31_b; + }; + + union + { + __IOM uint32_t ADDOPCRB31; /*!< (@ 0x000007F8) A/D Conversion Data Operation Control B Register + * 31 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB31_b; + }; + + union + { + __IOM uint32_t ADDOPCRC31; /*!< (@ 0x000007FC) A/D Conversion Data Operation Control C Register + * 31 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC31_b; + }; + + union + { + __IOM uint32_t ADCHCR32; /*!< (@ 0x00000800) A/D Conversion Channel Configuration Register + * 32 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR32_b; + }; + + union + { + __IOM uint32_t ADDOPCRA32; /*!< (@ 0x00000804) A/D Conversion Data Operation Control A Register + * 32 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA32_b; + }; + + union + { + __IOM uint32_t ADDOPCRB32; /*!< (@ 0x00000808) A/D Conversion Data Operation Control B Register + * 32 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB32_b; + }; + + union + { + __IOM uint32_t ADDOPCRC32; /*!< (@ 0x0000080C) A/D Conversion Data Operation Control C Register + * 32 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC32_b; + }; + __IM uint32_t RESERVED27[252]; + + union + { + __OM uint32_t ADCALSTR; /*!< (@ 0x00000C00) A/D Converter Calibration Start Register */ + + struct + { + __OM uint32_t ADCALST0 : 3; /*!< [2..0] A/D Converter Unit 0 (ADC0) Calibration Start Control + * bits */ + uint32_t : 5; + __OM uint32_t ADCALST1 : 3; /*!< [10..8] A/D Converter Unit 1 (ADC1) Calibration Start Control + * bits */ + uint32_t : 21; + } ADCALSTR_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t ADTRGENR; /*!< (@ 0x00000C08) A/D Conversion Start Trigger Enable Register */ + + struct + { + __IOM uint32_t STTRGENn : 9; /*!< [8..0] Scan Group n A/D Conversion Start Trigger Enable */ + uint32_t : 23; + } ADTRGENR_b; + }; + __IM uint32_t RESERVED29; + + union + { + __OM uint32_t ADSYSTR; /*!< (@ 0x00000C10) A/D Conversion Synchronous Software Start Register */ + + struct + { + __OM uint32_t ADSYSTn : 9; /*!< [8..0] Scan Group n : A/D Conversion start */ + uint32_t : 23; + } ADSYSTR_b; + }; + __IM uint32_t RESERVED30[3]; + + union + { + __OM uint32_t ADSTR[9]; /*!< (@ 0x00000C20) A/D Conversion Software Start Register [0..8] */ + + struct + { + __OM uint32_t ADST : 1; /*!< [0..0] Scan Group n A/D Conversion Start */ + uint32_t : 31; + } ADSTR_b[9]; + }; + __IM uint32_t RESERVED31[7]; + + union + { + __OM uint32_t ADSTOPR; /*!< (@ 0x00000C60) A/D Conversion Stop Register */ + + struct + { + __OM uint32_t ADSTOP0 : 1; /*!< [0..0] A/D Converter Unit 0 Force Stop bit */ + uint32_t : 7; + __OM uint32_t ADSTOP1 : 1; /*!< [8..8] A/D Converter Unit 1 Force Stop bit */ + uint32_t : 23; + } ADSTOPR_b; + }; + __IM uint32_t RESERVED32[7]; + + union + { + __IM uint32_t ADSR; /*!< (@ 0x00000C80) A/D Conversion Status Register */ + + struct + { + __IM uint32_t ADACT0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) A/D Conversion Status */ + __IM uint32_t ADACT1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) A/D Conversion Status */ + uint32_t : 14; + __IM uint32_t CALACT0 : 1; /*!< [16..16] A/D Converter Unit 0 (ADC0) : Calibration Status */ + __IM uint32_t CALACT1 : 1; /*!< [17..17] A/D Converter Unit 1 (ADC1) : Calibration Status */ + uint32_t : 14; + } ADSR_b; + }; + + union + { + __IM uint32_t ADGRSR; /*!< (@ 0x00000C84) Scan Group Status Register */ + + struct + { + __IM uint32_t ACTGRn : 9; /*!< [8..0] Scan Group n Status */ + uint32_t : 23; + } ADGRSR_b; + }; + + union + { + __IM uint32_t ADERSR; /*!< (@ 0x00000C88) A/D Conversion Error Status Register */ + + struct + { + __IM uint32_t ADERF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Error Flag */ + __IM uint32_t ADERF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Error Flag */ + uint32_t : 30; + } ADERSR_b; + }; + + union + { + __OM uint32_t ADERSCR; /*!< (@ 0x00000C8C) A/D Conversion Error Status Clear Register */ + + struct + { + __OM uint32_t ADERCLR0 : 1; /*!< [0..0] A/D Converter Unit 0 Error Flag Clear */ + __OM uint32_t ADERCLR1 : 1; /*!< [1..1] A/D Converter Unit 1 Error Flag Clear */ + uint32_t : 30; + } ADERSCR_b; + }; + __IM uint32_t RESERVED33[2]; + + union + { + __IM uint32_t ADCALENDSR; /*!< (@ 0x00000C98) A/D Converter Calibration End Status Register */ + + struct + { + __IM uint32_t CALENDF0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End flag */ + __IM uint32_t CALENDF1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End flag */ + uint32_t : 30; + } ADCALENDSR_b; + }; + + union + { + __OM uint32_t ADCALENDSCR; /*!< (@ 0x00000C9C) A/D Converter Calibration End Status Clear Register */ + + struct + { + __OM uint32_t CALENDC0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End Flag Clear */ + __OM uint32_t CALENDC1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End Flag Clear */ + uint32_t : 30; + } ADCALENDSCR_b; + }; + + union + { + __IM uint32_t ADOVFERSR; /*!< (@ 0x00000CA0) A/D Conversion Overflow Error Status Register */ + + struct + { + __IM uint32_t ADOVFEF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag */ + __IM uint32_t ADOVFEF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag */ + uint32_t : 30; + } ADOVFERSR_b; + }; + + union + { + __IM uint32_t ADOVFCHSR0; /*!< (@ 0x00000CA4) A/D Conversion Overflow Channel Status Register + * 0 */ + + struct + { + __IM uint32_t OVFCHFn : 23; /*!< [22..0] Analog Input Channel No. n : Overflow Flag */ + uint32_t : 9; + } ADOVFCHSR0_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IM uint32_t ADOVFEXSR; /*!< (@ 0x00000CB0) Extended Analog A/D Conversion Overflow Status + * Register */ + + struct + { + __IM uint32_t OVFEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Overflow Flag */ + __IM uint32_t OVFEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Overflow Flag */ + uint32_t : 2; + __IM uint32_t OVFEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Overflow Flag */ + __IM uint32_t OVFEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Overflow Flag */ + __IM uint32_t OVFEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Overflow Flag */ + uint32_t : 1; + __IM uint32_t OVFEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Overflow Flag */ + __IM uint32_t OVFEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Overflow Flag */ + uint32_t : 6; + __IM uint32_t OVFEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Overflow Flag */ + __IM uint32_t OVFEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Overflow Flag */ + __IM uint32_t OVFEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Overflow Flag */ + uint32_t : 1; + __IM uint32_t OVFEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Overflow Flag */ + __IM uint32_t OVFEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Overflow Flag */ + __IM uint32_t OVFEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Overflow Flag */ + uint32_t : 9; + } ADOVFEXSR_b; + }; + + union + { + __OM uint32_t ADOVFERSCR; /*!< (@ 0x00000CB4) A/D Conversion Overflow Error Status Clear Register */ + + struct + { + __OM uint32_t ADOVFEC0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear */ + __OM uint32_t ADOVFEC1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear */ + uint32_t : 30; + } ADOVFERSCR_b; + }; + + union + { + __OM uint32_t ADOVFCHSCR0; /*!< (@ 0x00000CB8) A/D Conversion Overflow Channel Status Clear + * Register 0 */ + + struct + { + __OM uint32_t OVFCHCn : 23; /*!< [22..0] Analog Input Channel No. n : Overflow Flag Clear */ + uint32_t : 9; + } ADOVFCHSCR0_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __OM uint32_t ADOVFEXSCR; /*!< (@ 0x00000CC4) Extended Analog A/D Conversion Overflow Status + * Clear Register */ + + struct + { + __OM uint32_t OVFEXC0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag Clear */ + __OM uint32_t OVFEXC1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag Clear */ + uint32_t : 2; + __OM uint32_t OVFEXC4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag Clear */ + __OM uint32_t OVFEXC5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag + * Clear */ + __OM uint32_t OVFEXC6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag Clear */ + uint32_t : 1; + __OM uint32_t OVFEXC8 : 1; /*!< [8..8] D/A Converter 0 Channel: Compare Match Flag Clear */ + __OM uint32_t OVFEXC9 : 1; /*!< [9..9] D/A Converter 1 Channel: Compare Match Flag Clear */ + uint32_t : 6; + __OM uint32_t OVFEXC16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag Clear */ + __OM uint32_t OVFEXC17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag Clear */ + __OM uint32_t OVFEXC18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag Clear */ + uint32_t : 1; + __OM uint32_t OVFEXC20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag Clear */ + __OM uint32_t OVFEXC21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Compare Match Flag Clear */ + __OM uint32_t OVFEXC22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Compare Match Flag Clear */ + uint32_t : 9; + } ADOVFEXSCR_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IM uint32_t ADFIFOSR0; /*!< (@ 0x00000CD0) FIFO Status Register 0 */ + + struct + { + __IM uint32_t FIFOST0 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 0 */ + uint32_t : 12; + __IM uint32_t FIFOST1 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 1 */ + uint32_t : 12; + } ADFIFOSR0_b; + }; + + union + { + __IM uint32_t ADFIFOSR1; /*!< (@ 0x00000CD4) FIFO Status Register 1 */ + + struct + { + __IM uint32_t FIFOST2 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 2 */ + uint32_t : 12; + __IM uint32_t FIFOST3 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 3 */ + uint32_t : 12; + } ADFIFOSR1_b; + }; + + union + { + __IM uint32_t ADFIFOSR2; /*!< (@ 0x00000CD8) FIFO Status Register 2 */ + + struct + { + __IM uint32_t FIFOST4 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 4 */ + uint32_t : 12; + __IM uint32_t FIFOST5 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 5 */ + uint32_t : 12; + } ADFIFOSR2_b; + }; + + union + { + __IM uint32_t ADFIFOSR3; /*!< (@ 0x00000CDC) FIFO Status Register 3 */ + + struct + { + __IM uint32_t FIFOST6 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 6 */ + uint32_t : 12; + __IM uint32_t FIFOST7 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 7 */ + uint32_t : 12; + } ADFIFOSR3_b; + }; + + union + { + __IM uint32_t ADFIFOSR4; /*!< (@ 0x00000CE0) FIFO Status Register 4 */ + + struct + { + __IM uint32_t FIFOST8 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 8 */ + uint32_t : 28; + } ADFIFOSR4_b; + }; + __IM uint32_t RESERVED37[3]; + + union + { + __OM uint32_t ADFIFODCR; /*!< (@ 0x00000CF0) FIFO Data Clear Register */ + + struct + { + __OM uint32_t FIFODCn : 9; /*!< [8..0] Scan Group n FIFO Data Clear */ + uint32_t : 23; + } ADFIFODCR_b; + }; + + union + { + __IM uint32_t ADFIFOERSR; /*!< (@ 0x00000CF4) FIFO Error Status Register */ + + struct + { + __IM uint32_t FIFOOVFn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag */ + uint32_t : 7; + __IM uint32_t FIFOFLFn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag */ + uint32_t : 7; + } ADFIFOERSR_b; + }; + + union + { + __OM uint32_t ADFIFOERSCR; /*!< (@ 0x00000CF8) FIFO Error Status Clear Register */ + + struct + { + __OM uint32_t FIFOOVFCn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag Clear */ + uint32_t : 7; + __OM uint32_t FIFOFLCn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag Clear */ + uint32_t : 7; + } ADFIFOERSCR_b; + }; + __IM uint32_t RESERVED38; + + union + { + __IM uint32_t ADCMPTBSR; /*!< (@ 0x00000D00) Compare Match Table Status Register */ + + struct + { + __IM uint32_t CMPTBFn : 8; /*!< [7..0] Compare Match Table n Match Flag */ + uint32_t : 24; + } ADCMPTBSR_b; + }; + + union + { + __OM uint32_t ADCMPTBSCR; /*!< (@ 0x00000D04) Compare Match Table Status Clear Register */ + + struct + { + __OM uint32_t CMPTBCn : 8; /*!< [7..0] Compare Match Table n : Match Flag Clear */ + uint32_t : 24; + } ADCMPTBSCR_b; + }; + + union + { + __IM uint32_t ADCMPCHSR0; /*!< (@ 0x00000D08) Compare Match Channel Status Register 0 */ + + struct + { + __IM uint32_t CMPCHFn : 23; /*!< [22..0] Analog Channel No. n : Compare Match Flag */ + uint32_t : 9; + } ADCMPCHSR0_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IM uint32_t ADCMPEXSR; /*!< (@ 0x00000D14) Extended Analog Compare Match Status Register */ + + struct + { + __IM uint32_t CMPEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag */ + __IM uint32_t CMPEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag */ + uint32_t : 2; + __IM uint32_t CMPEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag */ + __IM uint32_t CMPEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag */ + __IM uint32_t CMPEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag */ + uint32_t : 1; + __IM uint32_t CMPEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel : Compare Match Flag */ + __IM uint32_t CMPEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Compare Match Flag */ + uint32_t : 6; + __IM uint32_t CMPEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag */ + __IM uint32_t CMPEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag */ + __IM uint32_t CMPEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag */ + uint32_t : 1; + __IM uint32_t CMPEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + __IM uint32_t CMPEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + __IM uint32_t CMPEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + uint32_t : 9; + } ADCMPEXSR_b; + }; + + union + { + __OM uint32_t ADCMPCHSCR0; /*!< (@ 0x00000D18) Compare Match Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t CMPCHCn : 23; /*!< [22..0] Analog Channel No. n : Compare Match Flag Clear bit */ + uint32_t : 9; + } ADCMPCHSCR0_b; + }; + __IM uint32_t RESERVED40[2]; + + union + { + __OM uint32_t ADCMPEXSCR; /*!< (@ 0x00000D24) Extended Analog Compare Match Status Clear Register */ + + struct + { + __OM uint32_t CMPEXC0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag Clear */ + __OM uint32_t CMPEXC1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag Clear */ + uint32_t : 2; + __OM uint32_t CMPEXC4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag Clear */ + __OM uint32_t CMPEXC5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag + * Clear */ + __OM uint32_t CMPEXC6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag Clear */ + uint32_t : 1; + __OM uint32_t CMPEXC8 : 1; /*!< [8..8] D/A Converter 0 Channel: Compare Match Flag Clear */ + __OM uint32_t CMPEXC9 : 1; /*!< [9..9] D/A Converter 1 Channel : Compare Match Flag Clear */ + uint32_t : 6; + __OM uint32_t CMPEXC16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag Clear */ + __OM uint32_t CMPEXC17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag Clear */ + __OM uint32_t CMPEXC18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag Clear */ + uint32_t : 1; + __OM uint32_t CMPEXC20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag Clear */ + __OM uint32_t CMPEXC21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Compare Match Flag Clear */ + __OM uint32_t CMPEXC22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Compare Match Flag Clear */ + uint32_t : 9; + } ADCMPEXSCR_b; + }; + + union + { + __IM uint32_t ADLIMGRSR; /*!< (@ 0x00000D28) Limiter Clip Scan Group Status Register */ + + struct + { + __IM uint32_t LIMGRFn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag */ + uint32_t : 23; + } ADLIMGRSR_b; + }; + + union + { + __IM uint32_t ADLIMCHSR0; /*!< (@ 0x00000D2C) Limiter Clip Channel Status Register 0 */ + + struct + { + __IM uint32_t LIMCHFn : 23; /*!< [22..0] Analog Channel No. n : Limiter Clip Flag bit */ + uint32_t : 9; + } ADLIMCHSR0_b; + }; + __IM uint32_t RESERVED41[2]; + + union + { + __IM uint32_t ADLIMEXSR; /*!< (@ 0x00000D38) Extended Analog Limiter Clip Status Register */ + + struct + { + __IM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Limiter Clip Flag */ + __IM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel for A/D unit 1: Limiter Clip + * Flag */ + uint32_t : 2; + __IM uint32_t LIMEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Limiter Clip + * Flag */ + uint32_t : 1; + __IM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Limiter Clip Flag */ + uint32_t : 6; + __IM uint32_t LIMEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Limiter Clip Flag */ + __IM uint32_t LIMEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Limiter Clip Flag */ + __IM uint32_t LIMEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Limiter Clip Flag */ + uint32_t : 1; + __IM uint32_t LIMEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Limiter Clip Flag */ + __IM uint32_t LIMEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Limiter Clip Flag */ + __IM uint32_t LIMEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Limiter Clip Flag */ + uint32_t : 9; + } ADLIMEXSR_b; + }; + + union + { + __OM uint32_t ADLIMGRSCR; /*!< (@ 0x00000D3C) Limiter Clip Scan Group Status Clear Register */ + + struct + { + __OM uint32_t LIMGRCn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag Clear */ + uint32_t : 23; + } ADLIMGRSCR_b; + }; + + union + { + __OM uint32_t ADLIMCHSCR0; /*!< (@ 0x00000D40) Limiter Clip Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t LIMCHCn : 23; /*!< [22..0] Analog Channel No. n Limiter Clip Flag Clear bit */ + uint32_t : 9; + } ADLIMCHSCR0_b; + }; + __IM uint32_t RESERVED42[2]; + + union + { + __OM uint32_t ADLIMEXSCR; /*!< (@ 0x00000D4C) Extended Analog Limiter Clip Status Clear Register */ + + struct + { + __OM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Limiter Clip Flag + * Clear */ + __OM uint32_t LIMEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Limiter Clip Flag + * Clear */ + uint32_t : 2; + __OM uint32_t LIMEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Limiter Clip Flag + * Clear */ + __OM uint32_t LIMEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Limiter Clip + * Flag Clear */ + uint32_t : 1; + __OM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Limiter Clip Flag Clear */ + uint32_t : 6; + __OM uint32_t LIMEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Limiter Clip Flag Clear */ + uint32_t : 1; + __OM uint32_t LIMEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Limiter Clip Flag Clear */ + uint32_t : 9; + } ADLIMEXSCR_b; + }; + + union + { + __IM uint32_t ADSCANENDSR; /*!< (@ 0x00000D50) Scan End Status Register */ + + struct + { + __IM uint32_t SCENDFn : 9; /*!< [8..0] Scan Group n Scan End Flag */ + uint32_t : 23; + } ADSCANENDSR_b; + }; + + union + { + __OM uint32_t ADSCANENDSCR; /*!< (@ 0x00000D54) Scan End Status Clear Register */ + + struct + { + __OM uint32_t SCENDCn : 9; /*!< [8..0] Scan Group n Scan End Flag Clear */ + uint32_t : 23; + } ADSCANENDSCR_b; + }; + __IM uint32_t RESERVED43[1194]; + + union + { + __IM uint32_t ADDR[23]; /*!< (@ 0x00002000) A/D Data Register [0..22] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 15; + __IM uint32_t ERR : 1; /*!< [31..31] A/D conversion data error status */ + } ADDR_b[23]; + }; + __IM uint32_t RESERVED44[73]; + + union + { + __IM uint32_t ADEXDR[23]; /*!< (@ 0x00002180) A/D Extended Analog Data Register [0..22] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 8; + __IM uint32_t DIAGSR : 3; /*!< [26..24] Self-Diagnosis Status */ + uint32_t : 4; + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Error Status */ + } ADEXDR_b[23]; + }; + __IM uint32_t RESERVED45[9]; + + union + { + __IM uint32_t ADFIFODR0; /*!< (@ 0x00002200) FIFO Data Register 0 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR0_b; + }; + + union + { + __IM uint32_t ADFIFODR1; /*!< (@ 0x00002204) FIFO Data Register 1 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR1_b; + }; + + union + { + __IM uint32_t ADFIFODR2; /*!< (@ 0x00002208) FIFO Data Register 2 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR2_b; + }; + + union + { + __IM uint32_t ADFIFODR3; /*!< (@ 0x0000220C) FIFO Data Register 3 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR3_b; + }; + + union + { + __IM uint32_t ADFIFODR4; /*!< (@ 0x00002210) FIFO Data Register 4 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR4_b; + }; + + union + { + __IM uint32_t ADFIFODR5; /*!< (@ 0x00002214) FIFO Data Register 5 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR5_b; + }; + + union + { + __IM uint32_t ADFIFODR6; /*!< (@ 0x00002218) FIFO Data Register 6 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR6_b; + }; + + union + { + __IM uint32_t ADFIFODR7; /*!< (@ 0x0000221C) FIFO Data Register 7 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR7_b; + }; + + union + { + __IM uint32_t ADFIFODR8; /*!< (@ 0x00002220) FIFO Data Register 8 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR8_b; + }; +} R_ADC_B0_Type; /*!< Size = 8740 (0x2224) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC_B) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC_B Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */ + __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */ + + struct + { + __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */ + uint8_t : 7; + } DOSR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */ + + struct + { + __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */ + uint8_t : 7; + } DOSCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */ + __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */ + __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */ +} R_DOC_B_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI_B0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI_B0 Structure */ +{ + union + { + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint8_t RDR_BY; /*!< (@ 0x00000000) Receive Data Register (byte access) */ + + struct + { + __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data */ + } RDR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 2; + __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */ + uint32_t : 19; + } TDR_b; + }; + + union + { + __IOM uint8_t TDR_BY; /*!< (@ 0x00000004) Transmit Data Register (byte access) */ + + struct + { + __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data */ + } TDR_BY_b; + }; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 1; + __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit. */ + uint32_t : 4; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + + union + { + __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */ + + struct + { + __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */ + uint8_t : 3; + __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */ + uint8_t : 3; + } CESR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */ + + struct + { + __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint32_t : 1; + __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */ + __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + uint32_t : 1; + __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */ + __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */ + uint32_t : 2; + __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */ + __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */ + uint32_t : 2; + __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */ + __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */ + __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */ + uint32_t : 5; + } MCR_b; + }; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + + union + { + __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */ + + struct + { + __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */ + uint32_t : 6; + __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */ + __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */ + __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */ + __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */ + __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */ + __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */ + __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */ + uint32_t : 2; + __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */ + __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */ + __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */ + uint32_t : 1; + __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */ + uint32_t : 6; + } XCR0_b; + }; + + union + { + __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */ + + struct + { + __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */ + uint32_t : 3; + __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */ + __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */ + uint32_t : 2; + __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */ + __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */ + __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */ + } XCR1_b; + }; + + union + { + __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */ + + struct + { + __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */ + __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */ + __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */ + } XCR2_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */ + __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */ + __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + + union + { + __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */ + + struct + { + __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */ + __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */ + __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */ + uint32_t : 1; + __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */ + uint32_t : 1; + __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */ + uint32_t : 25; + } MSR_b; + }; + + union + { + __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */ + + struct + { + __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */ + __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */ + uint32_t : 6; + __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */ + __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */ + __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */ + __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */ + __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */ + __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */ + __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */ + __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */ + __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */ + __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */ + } XSR0_b; + }; + + union + { + __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */ + + struct + { + __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */ + uint32_t : 16; + } XSR1_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */ + __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */ + __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */ + uint32_t : 31; + } FFCLR_b; + }; + + union + { + __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */ + + struct + { + __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */ + __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */ + __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */ + uint32_t : 1; + __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */ + uint32_t : 27; + } MFCLR_b; + }; + + union + { + __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */ + __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */ + __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */ + __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */ + __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */ + __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */ + __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */ + __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */ + uint32_t : 16; + } XFCLR_b; + }; +} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI_B0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI_B0 Structure */ +{ + __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */ + + union + { + __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */ + + struct + { + __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */ + uint32_t : 5; + __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */ + uint32_t : 5; + __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */ + uint32_t : 5; + __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */ + uint32_t : 5; + } SPDECR_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */ + + struct + { + __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint32_t : 1; + __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */ + __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */ + __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */ + __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */ + __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */ + uint32_t : 2; + __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */ + __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */ + uint32_t : 10; + } SPCR2_b; + }; + + union + { + __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */ + + struct + { + __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */ + __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */ + __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */ + __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */ + uint32_t : 4; + __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */ + uint32_t : 8; + __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */ + uint32_t : 5; + } SPCR3_b; + }; + + union + { + __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD0_b; + }; + + union + { + __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD1_b; + }; + + union + { + __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD2_b; + }; + + union + { + __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD3_b; + }; + + union + { + __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD4_b; + }; + + union + { + __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD5_b; + }; + + union + { + __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD6_b; + }; + + union + { + __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD7_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */ + + struct + { + __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint32_t : 2; + __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */ + __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */ + uint32_t : 3; + __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */ + uint32_t : 22; + } SPDCR_b; + }; + + union + { + __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */ + + struct + { + __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint32_t : 6; + __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint32_t : 22; + } SPDCR2_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */ + uint32_t : 1; + __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */ + uint32_t : 8; + __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */ + __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */ + __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */ + __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */ + __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */ + __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */ + __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */ + + struct + { + __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint32_t : 29; + } SPTFSR_b; + }; + + union + { + __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */ + + struct + { + __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint32_t : 29; + } SPRFSR_b; + }; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */ + + struct + { + uint32_t : 23; + __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */ + __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */ + uint32_t : 1; + __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */ + __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */ + __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */ + __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */ + __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */ + __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */ + + struct + { + __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */ + uint32_t : 31; + } SPFCR_b; + }; +} R_SPI_B0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40351000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief eXpanded SPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x40268000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration register */ + + struct + { + __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 3; + __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration register */ + + struct + { + __IOM uint32_t ARBMD : 2; /*!< [1..0] Channel arbitration mode */ + uint32_t : 2; + __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable */ + uint32_t : 10; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFGCH[2]; /*!< (@ 0x00000008) xSPI Bridge Map Configuration register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 7; + __IOM uint32_t CMBTIM : 8; /*!< [31..24] Combination timer */ + } BMCFGCH_b[2]; + }; + __IOM R_XSPI0_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers */ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1] */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + + union + { + __IOM uint32_t ABMCFG; /*!< (@ 0x00000058) xSPI AXI Bridge Map Config */ + + struct + { + __IOM uint32_t ODRMD : 2; /*!< [1..0] AXI Transfer Ordering Mode */ + uint32_t : 14; + __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select */ + } ABMCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control register 0 */ + + struct + { + __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable */ + __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable */ + __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable */ + __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable */ + uint32_t : 24; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0 */ + __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1 */ + __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0 */ + __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1 */ + uint32_t : 20; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTLCH[2]; /*!< (@ 0x00000068) xSPI Command Map Control register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTLCH_b[2]; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED2; + __IOM R_XSPI0_CDBUF_Type CDBUF[4]; /*!< (@ 0x00000080) xSPI BUF register */ + __IM uint32_t RESERVED3[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave 0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave 1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_XSPI0_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register */ + __IM uint32_t RESERVED5[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status register */ + + struct + { + __IM uint32_t MEMACCCH0 : 1; /*!< [0..0] Memory access ongoing from ch0 */ + __IM uint32_t MEMACCCH1 : 1; /*!< [1..1] Memory access ongoing from ch1 */ + uint32_t : 2; + __IM uint32_t PBUFNECH0 : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0 */ + __IM uint32_t PBUFNECH1 : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1 */ + __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0 */ + __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1 */ + uint32_t : 8; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status register */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOFCH0 : 1; /*!< [16..16] Bridge Buffer overflow for CH0 */ + __IM uint32_t BRGOFCH1 : 1; /*!< [17..17] Bridge Buffer overflow for CH1 */ + __IM uint32_t BRGUFCH0 : 1; /*!< [18..18] Bridge Buffer underflow for CH0 */ + __IM uint32_t BRGUFCH1 : 1; /*!< [19..19] Bridge Buffer underflow for CH1 */ + __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0 */ + __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1 */ + uint32_t : 6; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFCH0C : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear */ + __OM uint32_t BRGOFCH1C : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear */ + __OM uint32_t BRGUFCH0C : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear */ + __OM uint32_t BRGUFCH1C : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear */ + __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear */ + __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear */ + uint32_t : 6; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFCH0E : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable */ + __IOM uint32_t BRGOFCH1E : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable */ + __IOM uint32_t BRGUFCH0E : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable */ + __IOM uint32_t BRGUFCH1E : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable */ + __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable */ + __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable */ + uint32_t : 6; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D-PHY Controller Top (R_MIPI_PHY) + */ + +typedef struct /*!< (@ 0x40346C00) R_MIPI_PHY Structure */ +{ + union + { + __IOM uint32_t DPHYREFCR; /*!< (@ 0x00000000) D-PHY Reference Clock Setting Register */ + + struct + { + __IOM uint32_t RFREQ : 8; /*!< [7..0] Reference Clock Frequency Setting */ + uint32_t : 24; + } DPHYREFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLFCR; /*!< (@ 0x00000004) D-PHY PLL Frequency Control Register */ + + struct + { + __IOM uint32_t IDIV : 2; /*!< [1..0] D-PHY PLL Input Frequency Division Ratio Select */ + uint32_t : 6; + __IOM uint32_t NFMUL : 2; /*!< [9..8] D-PHY PLL Frequency Multiplication Factor Select (Fractional + * Part) */ + uint32_t : 2; + __IOM uint32_t PMUL : 2; /*!< [13..12] D-PHY PLL Output Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t NMUL : 9; /*!< [24..16] D-PHY PLL Frequency Multiplication Factor Select (Integer + * Part) */ + uint32_t : 7; + } DPHYPLFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLOCR; /*!< (@ 0x00000008) D-PHY PLL Operation Control Register */ + + struct + { + __IOM uint32_t PLLSTP : 1; /*!< [0..0] D-PHY PLL Operation Control */ + uint32_t : 31; + } DPHYPLOCR_b; + }; + + union + { + __IOM uint32_t DPHYESCCR; /*!< (@ 0x0000000C) D-PHY Escape Mode Clock Control Register */ + + struct + { + __IOM uint32_t ESCDIV : 5; /*!< [4..0] Escape Mode Transfer Clock Division Ratio */ + uint32_t : 27; + } DPHYESCCR_b; + }; + + union + { + __IOM uint32_t DPHYPWRCR; /*!< (@ 0x00000010) D-PHY Power Supplying Control Register */ + + struct + { + __IOM uint32_t PWRSEN : 1; /*!< [0..0] D-PHY Power Supplying Control */ + uint32_t : 31; + } DPHYPWRCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IM uint32_t DPHYSFR; /*!< (@ 0x0000001C) D-PHY Status Flag Register */ + + struct + { + __IM uint32_t PWRSF : 1; /*!< [0..0] D-PHY LDO Power-on Status Flag */ + uint32_t : 7; + __IM uint32_t PLLSF : 1; /*!< [8..8] D-PHY PLL Oscillation Stabilization Flag */ + uint32_t : 23; + } DPHYSFR_b; + }; + + union + { + __IOM uint32_t DPHYOCR; /*!< (@ 0x00000020) D-PHY Operation Control Register */ + + struct + { + __IOM uint32_t DPHYEN : 1; /*!< [0..0] D-PHY Operation Control */ + uint32_t : 31; + } DPHYOCR_b; + }; + + union + { + __IOM uint32_t DPHYTIM1; /*!< (@ 0x00000024) D-PHY Timing Control Register 1 */ + + struct + { + __IOM uint32_t TINIT : 19; /*!< [18..0] D-PHY T_INIT Parameter Setting */ + uint32_t : 13; + } DPHYTIM1_b; + }; + + union + { + __IOM uint32_t DPHYTIM2; /*!< (@ 0x00000028) D-PHY Timing Control Register 2 */ + + struct + { + __IOM uint32_t TCLKPREP : 8; /*!< [7..0] D-PHY T_CLK_PREPARE Parameter Setting */ + __IOM uint32_t TCLKSETT : 8; /*!< [15..8] D-PHY T_CLK_SETTLE Parameter Setting */ + __IOM uint32_t TCLKMISS : 8; /*!< [23..16] D-PHY T_CLK_MISS Parameter Setting */ + uint32_t : 8; + } DPHYTIM2_b; + }; + + union + { + __IOM uint32_t DPHYTIM3; /*!< (@ 0x0000002C) D-PHY Timing Control Register 3 */ + + struct + { + __IOM uint32_t THSPREP : 8; /*!< [7..0] D-PHY T_THS_PREPARE Parameter Setting */ + __IOM uint32_t THSSETT : 8; /*!< [15..8] D-PHY T_THS_SETTLE Parameter Setting */ + uint32_t : 16; + } DPHYTIM3_b; + }; + + union + { + __IOM uint32_t DPHYTIM4; /*!< (@ 0x00000030) D-PHY Timing Control Register 4 */ + + struct + { + __IOM uint32_t TCLKZERO : 8; /*!< [7..0] D-PHY T_CLK_ZERO Parameter Setting */ + __IOM uint32_t TCLKPRE : 8; /*!< [15..8] D-PHY T_TCLK_PRE Parameter Setting */ + __IOM uint32_t TCLKPOST : 8; /*!< [23..16] D-PHY T_TCLK_POST Parameter Setting */ + __IOM uint32_t TCLKTRL : 8; /*!< [31..24] D-PHY T_TCLK_TRAIL Parameter Setting */ + } DPHYTIM4_b; + }; + + union + { + __IOM uint32_t DPHYTIM5; /*!< (@ 0x00000034) D-PHY Timing Control Register 5 */ + + struct + { + __IOM uint32_t THSZERO : 8; /*!< [7..0] D-PHY T_THS_ZERO Parameter Setting */ + __IOM uint32_t THSTRL : 8; /*!< [15..8] D-PHY T_THS_TRAIL Parameter Setting */ + __IOM uint32_t THSEXIT : 8; /*!< [23..16] D-PHY T_THS_EXIT Parameter Setting */ + uint32_t : 8; + } DPHYTIM5_b; + }; + + union + { + __IOM uint32_t DPHYTIM6; /*!< (@ 0x00000038) D-PHY Timing Control Register 6 */ + + struct + { + __IOM uint32_t TLPX : 8; /*!< [7..0] D-PHY T_TLPX Parameter Setting */ + uint32_t : 24; + } DPHYTIM6_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DPHYMDC; /*!< (@ 0x00000048) D-PHY Mode Control Register */ + + struct + { + __IOM uint32_t MASTEREN : 1; /*!< [0..0] D-PHY Master/Slave Select */ + uint32_t : 31; + } DPHYMDC_b; + }; +} R_MIPI_PHY_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_CSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MIPI_CSI Register area (R_MIPI_CSI) + */ + +typedef struct /*!< (@ 0x40347000) R_MIPI_CSI Structure */ +{ + union + { + __IM uint32_t MCG; /*!< (@ 0x00000000) Module Configuration Register */ + + struct + { + __IM uint32_t VER : 4; /*!< [3..0] VERsion of this ip */ + uint32_t : 4; + __IM uint32_t SDLN : 4; /*!< [11..8] Number of Supported Data Lanes */ + uint32_t : 4; + __IM uint32_t GSNM : 8; /*!< [23..16] NuMber of Generic Short packt FIFO */ + uint32_t : 8; + } MCG_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t MCT0; /*!< (@ 0x00000010) Module Control Register 0 */ + + struct + { + __IOM uint32_t VDLN : 4; /*!< [3..0] Numer of Valid Data Lanes */ + uint32_t : 12; + __IOM uint32_t ZLMD : 1; /*!< [16..16] Zero Length long packet output MoDe */ + __IOM uint32_t EDMD : 1; /*!< [17..17] ErrframeData notification MoDe */ + uint32_t : 1; + __IOM uint32_t RVMD : 1; /*!< [19..19] ReserVed packet reception MoDe */ + __IOM uint32_t GRMD : 1; /*!< [20..20] Generic csi-2 Rule MoDe */ + uint32_t : 3; + __IOM uint32_t ECCV13 : 1; /*!< [24..24] ECC check csi-2 Ver 1.3 mode */ + __IOM uint32_t LFSREN : 1; /*!< [25..25] LFSR Enable mode */ + uint32_t : 6; + } MCT0_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t MCT2; /*!< (@ 0x00000018) Module Control Register 2 */ + + struct + { + __IOM uint32_t FRRCLK : 9; /*!< [8..0] clock FRequency Rate to judge packet reception end */ + uint32_t : 7; + __IOM uint32_t FRRSKW : 9; /*!< [24..16] clock FRequency Rate to adjust data lane SKew */ + uint32_t : 7; + } MCT2_b; + }; + + union + { + __IOM uint32_t MCT3; /*!< (@ 0x0000001C) Module Control Register 3 */ + + struct + { + __IOM uint32_t RXEN : 1; /*!< [0..0] RX (reception) Enable */ + uint32_t : 31; + } MCT3_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t RTCT; /*!< (@ 0x00000028) Reset Control Register */ + + struct + { + __OM uint32_t VSRST : 1; /*!< [0..0] Video pixel interface Software ReSeT */ + uint32_t : 31; + } RTCT_b; + }; + + union + { + __IM uint32_t RTST; /*!< (@ 0x0000002C) Reset Status Register */ + + struct + { + __IM uint32_t VSRSTS : 1; /*!< [0..0] Video pixel interface Software ReSeT Status */ + uint32_t : 31; + } RTST_b; + }; + __IM uint32_t RESERVED3[4]; + + union + { + __IOM uint32_t EPCT; /*!< (@ 0x00000040) EPD Option Control Register */ + + struct + { + __IOM uint32_t SLP : 15; /*!< [14..0] Long Packet Spacers */ + __IOM uint32_t EPDOP : 1; /*!< [15..15] EPD OPtion select */ + __IOM uint32_t SSP : 15; /*!< [30..16] epd Short Packet Spacers */ + __IOM uint32_t EPDEN : 1; /*!< [31..31] ENable EPD operation */ + } EPCT_b; + }; + + union + { + __IOM uint32_t EMCT; /*!< (@ 0x00000044) EPD Misc Option Control Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t VLSIEN : 2; /*!< [5..4] ENable Variable-Length Spacer Insertions */ + __IOM uint32_t EOTPEN : 1; /*!< [6..6] ENable EOTP */ + uint32_t : 25; + } EMCT_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t MIST; /*!< (@ 0x00000050) Module Interrupt Status Register */ + + struct + { + __IM uint32_t DL0S : 1; /*!< [0..0] interrupt Status related to Data Lane 0 */ + __IM uint32_t DL1S : 1; /*!< [1..1] interrupt Status related to Data Lane 1 */ + uint32_t : 6; + __IM uint32_t PMS : 1; /*!< [8..8] interrupt Status related to Power Management */ + __IM uint32_t GSTS : 1; /*!< [9..9] interrupt Status related to Generic ShorT packet */ + __IM uint32_t RXS : 1; /*!< [10..10] interrupt Status related to RX (Reception) */ + uint32_t : 5; + __IM uint32_t VC0S : 1; /*!< [16..16] interrupt Status related to Vitrtual Channel 0 */ + __IM uint32_t VC1S : 1; /*!< [17..17] interrupt Status related to Vitrtual Channel 1 */ + __IM uint32_t VC2S : 1; /*!< [18..18] interrupt Status related to Vitrtual Channel 2 */ + __IM uint32_t VC3S : 1; /*!< [19..19] interrupt Status related to Vitrtual Channel 3 */ + __IM uint32_t VC4S : 1; /*!< [20..20] interrupt Status related to Vitrtual Channel 4 */ + __IM uint32_t VC5S : 1; /*!< [21..21] interrupt Status related to Vitrtual Channel 5 */ + __IM uint32_t VC6S : 1; /*!< [22..22] interrupt Status related to Vitrtual Channel 6 */ + __IM uint32_t VC7S : 1; /*!< [23..23] interrupt Status related to Vitrtual Channel 7 */ + __IM uint32_t VC8S : 1; /*!< [24..24] interrupt Status related to Vitrtual Channel 8 */ + __IM uint32_t VC9S : 1; /*!< [25..25] interrupt Status related to Vitrtual Channel 9 */ + __IM uint32_t VC10S : 1; /*!< [26..26] interrupt Status related to Vitrtual Channel 10 */ + __IM uint32_t VC11S : 1; /*!< [27..27] interrupt Status related to Vitrtual Channel 11 */ + __IM uint32_t VC12S : 1; /*!< [28..28] interrupt Status related to Vitrtual Channel 12 */ + __IM uint32_t VC13S : 1; /*!< [29..29] interrupt Status related to Vitrtual Channel 13 */ + __IM uint32_t VC14S : 1; /*!< [30..30] interrupt Status related to Vitrtual Channel 14 */ + __IM uint32_t VC15S : 1; /*!< [31..31] interrupt Status related to Vitrtual Channel 15 */ + } MIST_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t DTEL; /*!< (@ 0x00000060) Receive Data Type Enable Low Register */ + + struct + { + __IOM uint32_t DTEN : 32; /*!< [31..0] Data Type ENable (DT = 0x00 to 0x1F) */ + } DTEL_b; + }; + + union + { + __IOM uint32_t DTEH; /*!< (@ 0x00000064) Receive Data Type Enable High Register */ + + struct + { + __IOM uint32_t DTEN : 32; /*!< [31..0] Data Type ENable (DT = 0x20 to 0x3F) */ + } DTEH_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IM uint32_t RXST; /*!< (@ 0x00000070) Receive Status Register */ + + struct + { + __IM uint32_t FRM0 : 1; /*!< [0..0] FRaMe of virtual channel 0 active */ + __IM uint32_t FRM1 : 1; /*!< [1..1] FRaMe of virtual channel 1 active */ + __IM uint32_t FRM2 : 1; /*!< [2..2] FRaMe of virtual channel 2 active */ + __IM uint32_t FRM3 : 1; /*!< [3..3] FRaMe of virtual channel 3 active */ + __IM uint32_t FRM4 : 1; /*!< [4..4] FRaMe of virtual channel 4 active */ + __IM uint32_t FRM5 : 1; /*!< [5..5] FRaMe of virtual channel 5 active */ + __IM uint32_t FRM6 : 1; /*!< [6..6] FRaMe of virtual channel 6 active */ + __IM uint32_t FRM7 : 1; /*!< [7..7] FRaMe of virtual channel 7 active */ + __IM uint32_t FRM8 : 1; /*!< [8..8] FRaMe of virtual channel 8 active */ + __IM uint32_t FRM9 : 1; /*!< [9..9] FRaMe of virtual channel 9 active */ + __IM uint32_t FRM10 : 1; /*!< [10..10] FRaMe of virtual channel 10 active */ + __IM uint32_t FRM11 : 1; /*!< [11..11] FRaMe of virtual channel 11 active */ + __IM uint32_t FRM12 : 1; /*!< [12..12] FRaMe of virtual channel 12 active */ + __IM uint32_t FRM13 : 1; /*!< [13..13] FRaMe of virtual channel 13 active */ + __IM uint32_t FRM14 : 1; /*!< [14..14] FRaMe of virtual channel 14 active */ + __IM uint32_t FRM15 : 1; /*!< [15..15] FRaMe of virtual channel 15 active */ + __IM uint32_t RACT : 1; /*!< [16..16] Rx (Reception) ACTive status */ + __IM uint32_t RACTDET : 1; /*!< [17..17] Rx (Reception) ACTive DETect */ + uint32_t : 14; + } RXST_b; + }; + + union + { + __OM uint32_t RXSC; /*!< (@ 0x00000074) Receive Status Clear Register */ + + struct + { + uint32_t : 17; + __OM uint32_t RACTDETC : 1; /*!< [17..17] Rx (Reception) ACTive DETect status Clear */ + uint32_t : 14; + } RXSC_b; + }; + + union + { + __IOM uint32_t RXIE; /*!< (@ 0x00000078) Receive Interrupt Enable Register */ + + struct + { + uint32_t : 17; + __IOM uint32_t RACTDETE : 1; /*!< [17..17] Rx (Reception) ACTive DETect interrupt Enable */ + uint32_t : 14; + } RXIE_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t DLST0; /*!< (@ 0x00000080) Data Lane (N) Status Register */ + + struct + { + __IM uint32_t ESH : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status */ + __IM uint32_t ESS : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status */ + __IM uint32_t ECT : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status */ + __IM uint32_t EES : 1; /*!< [3..3] ErrESc detect on data lane (N) status */ + uint32_t : 12; + __IM uint32_t EUL : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status */ + __IM uint32_t RUL : 1; /*!< [17..17] entry to ULps detect on data lane (N) status */ + uint32_t : 6; + __IM uint32_t ULP : 1; /*!< [24..24] rxULPsesc of data lane (N) status */ + uint32_t : 7; + } DLST0_b; + }; + + union + { + __OM uint32_t DLSC0; /*!< (@ 0x00000084) Data Lane (N) Status Clear Register */ + + struct + { + __OM uint32_t ESHC : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status Clear */ + __OM uint32_t ESSC : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status Clear */ + __OM uint32_t ECTC : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status Clear */ + __OM uint32_t EESC : 1; /*!< [3..3] ErrESc detect on data lane (N) status Clear */ + uint32_t : 12; + __OM uint32_t EULC : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status Clear */ + __OM uint32_t RULC : 1; /*!< [17..17] Entry to ULps detect on data lane (N) status Clear */ + uint32_t : 14; + } DLSC0_b; + }; + + union + { + __IOM uint32_t DLIE0; /*!< (@ 0x00000088) Data Lane (N) Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESHE : 1; /*!< [0..0] ErrSotHs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ESSE : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ECTE : 1; /*!< [2..2] ErrConTrol detect on data lane (N) interrupt Enable */ + __IOM uint32_t EESE : 1; /*!< [3..3] ErrESc detect on data lane (N) interrupt Enable */ + uint32_t : 12; + __IOM uint32_t EULE : 1; /*!< [16..16] Exit to ULps detect on data lane (N) interrupt Enable */ + __IOM uint32_t RULE : 1; /*!< [17..17] Entry to ULps detect on data lane (N) interrupt Enable */ + uint32_t : 14; + } DLIE0_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IM uint32_t DLST1; /*!< (@ 0x00000090) Data Lane (N) Status Register */ + + struct + { + __IM uint32_t ESH : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status */ + __IM uint32_t ESS : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status */ + __IM uint32_t ECT : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status */ + __IM uint32_t EES : 1; /*!< [3..3] ErrESc detect on data lane (N) status */ + uint32_t : 12; + __IM uint32_t EUL : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status */ + __IM uint32_t RUL : 1; /*!< [17..17] entry to ULps detect on data lane (N) status */ + uint32_t : 6; + __IM uint32_t ULP : 1; /*!< [24..24] rxULPsesc of data lane (N) status */ + uint32_t : 7; + } DLST1_b; + }; + + union + { + __OM uint32_t DLSC1; /*!< (@ 0x00000094) Data Lane (N) Status Clear Register */ + + struct + { + __OM uint32_t ESHC : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status Clear */ + __OM uint32_t ESSC : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status Clear */ + __OM uint32_t ECTC : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status Clear */ + __OM uint32_t EESC : 1; /*!< [3..3] ErrESc detect on data lane (N) status Clear */ + uint32_t : 12; + __OM uint32_t EULC : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status Clear */ + __OM uint32_t RULC : 1; /*!< [17..17] Entry to ULps detect on data lane (N) status Clear */ + uint32_t : 14; + } DLSC1_b; + }; + + union + { + __IOM uint32_t DLIE1; /*!< (@ 0x00000098) Data Lane (N) Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESHE : 1; /*!< [0..0] ErrSotHs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ESSE : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ECTE : 1; /*!< [2..2] ErrConTrol detect on data lane (N) interrupt Enable */ + __IOM uint32_t EESE : 1; /*!< [3..3] ErrESc detect on data lane (N) interrupt Enable */ + uint32_t : 12; + __IOM uint32_t EULE : 1; /*!< [16..16] Exit to ULps detect on data lane (N) interrupt Enable */ + __IOM uint32_t RULE : 1; /*!< [17..17] Entry to ULps detect on data lane (N) interrupt Enable */ + uint32_t : 14; + } DLIE1_b; + }; + __IM uint32_t RESERVED9[25]; + + union + { + __IM uint32_t VCST0; /*!< (@ 0x00000100) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST0_b; + }; + + union + { + __OM uint32_t VCSC0; /*!< (@ 0x00000104) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC0_b; + }; + + union + { + __IOM uint32_t VCIE0; /*!< (@ 0x00000108) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE0_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IM uint32_t VCST1; /*!< (@ 0x00000110) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST1_b; + }; + + union + { + __OM uint32_t VCSC1; /*!< (@ 0x00000114) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC1_b; + }; + + union + { + __IOM uint32_t VCIE1; /*!< (@ 0x00000118) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE1_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IM uint32_t VCST2; /*!< (@ 0x00000120) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST2_b; + }; + + union + { + __OM uint32_t VCSC2; /*!< (@ 0x00000124) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC2_b; + }; + + union + { + __IOM uint32_t VCIE2; /*!< (@ 0x00000128) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE2_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t VCST3; /*!< (@ 0x00000130) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST3_b; + }; + + union + { + __OM uint32_t VCSC3; /*!< (@ 0x00000134) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC3_b; + }; + + union + { + __IOM uint32_t VCIE3; /*!< (@ 0x00000138) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE3_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IM uint32_t VCST4; /*!< (@ 0x00000140) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST4_b; + }; + + union + { + __OM uint32_t VCSC4; /*!< (@ 0x00000144) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC4_b; + }; + + union + { + __IOM uint32_t VCIE4; /*!< (@ 0x00000148) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE4_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IM uint32_t VCST5; /*!< (@ 0x00000150) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST5_b; + }; + + union + { + __OM uint32_t VCSC5; /*!< (@ 0x00000154) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC5_b; + }; + + union + { + __IOM uint32_t VCIE5; /*!< (@ 0x00000158) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE5_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IM uint32_t VCST6; /*!< (@ 0x00000160) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST6_b; + }; + + union + { + __OM uint32_t VCSC6; /*!< (@ 0x00000164) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC6_b; + }; + + union + { + __IOM uint32_t VCIE6; /*!< (@ 0x00000168) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE6_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IM uint32_t VCST7; /*!< (@ 0x00000170) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST7_b; + }; + + union + { + __OM uint32_t VCSC7; /*!< (@ 0x00000174) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC7_b; + }; + + union + { + __IOM uint32_t VCIE7; /*!< (@ 0x00000178) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE7_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t VCST8; /*!< (@ 0x00000180) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST8_b; + }; + + union + { + __OM uint32_t VCSC8; /*!< (@ 0x00000184) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC8_b; + }; + + union + { + __IOM uint32_t VCIE8; /*!< (@ 0x00000188) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE8_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IM uint32_t VCST9; /*!< (@ 0x00000190) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST9_b; + }; + + union + { + __OM uint32_t VCSC9; /*!< (@ 0x00000194) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC9_b; + }; + + union + { + __IOM uint32_t VCIE9; /*!< (@ 0x00000198) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE9_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t VCST10; /*!< (@ 0x000001A0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST10_b; + }; + + union + { + __OM uint32_t VCSC10; /*!< (@ 0x000001A4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC10_b; + }; + + union + { + __IOM uint32_t VCIE10; /*!< (@ 0x000001A8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE10_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t VCST11; /*!< (@ 0x000001B0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST11_b; + }; + + union + { + __OM uint32_t VCSC11; /*!< (@ 0x000001B4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC11_b; + }; + + union + { + __IOM uint32_t VCIE11; /*!< (@ 0x000001B8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE11_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IM uint32_t VCST12; /*!< (@ 0x000001C0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST12_b; + }; + + union + { + __OM uint32_t VCSC12; /*!< (@ 0x000001C4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC12_b; + }; + + union + { + __IOM uint32_t VCIE12; /*!< (@ 0x000001C8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE12_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t VCST13; /*!< (@ 0x000001D0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST13_b; + }; + + union + { + __OM uint32_t VCSC13; /*!< (@ 0x000001D4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC13_b; + }; + + union + { + __IOM uint32_t VCIE13; /*!< (@ 0x000001D8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE13_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t VCST14; /*!< (@ 0x000001E0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST14_b; + }; + + union + { + __OM uint32_t VCSC14; /*!< (@ 0x000001E4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC14_b; + }; + + union + { + __IOM uint32_t VCIE14; /*!< (@ 0x000001E8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE14_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IM uint32_t VCST15; /*!< (@ 0x000001F0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST15_b; + }; + + union + { + __OM uint32_t VCSC15; /*!< (@ 0x000001F4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC15_b; + }; + + union + { + __IOM uint32_t VCIE15; /*!< (@ 0x000001F8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE15_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IM uint32_t PMST; /*!< (@ 0x00000200) Power Management Status Register */ + + struct + { + __IM uint32_t DSX : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes status */ + __IM uint32_t DSN : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes status */ + __IM uint32_t CSX : 1; /*!< [2..2] eXit from Stop state detect on Clock lane status */ + __IM uint32_t CSN : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane status */ + __IM uint32_t DUX : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes status */ + __IM uint32_t DUN : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes status */ + __IM uint32_t CUX : 1; /*!< [6..6] eXit frum Ulps detect on Clock lane status */ + __IM uint32_t CUN : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane status */ + uint32_t : 6; + __IM uint32_t CLSS : 1; /*!< [14..14] Stop State of Clock Lane status */ + __IM uint32_t CLUL : 1; /*!< [15..15] rxULpsclknot (inverted) of Clock Lane status */ + __IM uint32_t DLSS : 2; /*!< [17..16] Stop State of Data Lanes status */ + uint32_t : 6; + __IM uint32_t DLUL : 2; /*!< [25..24] rxULpsesc of Data Lanes status */ + uint32_t : 6; + } PMST_b; + }; + + union + { + __OM uint32_t PMSC; /*!< (@ 0x00000204) Power Management Status Clear Register */ + + struct + { + __OM uint32_t DSXC : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes status + * Clear */ + __OM uint32_t DSNC : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes status + * Clear */ + __OM uint32_t CSXC : 1; /*!< [2..2] eXit from Stop state detect on Clock lane status Clear */ + __OM uint32_t CSNC : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane status Clear */ + __OM uint32_t DUXC : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes status + * Clear */ + __OM uint32_t DUNC : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes status Clear */ + __OM uint32_t CUXC : 1; /*!< [6..6] eXit frum Ulps detect on Clock lane status Clear */ + __OM uint32_t CUNC : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane status Clear */ + uint32_t : 24; + } PMSC_b; + }; + + union + { + __IOM uint32_t PMIE; /*!< (@ 0x00000208) Power Management Interrupt Enable Register */ + + struct + { + __IOM uint32_t DSXE : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t DSNE : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t CSXE : 1; /*!< [2..2] eXit from Stop state detect on Clock lane interrupt Enable */ + __IOM uint32_t CSNE : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane interrupt Enable */ + __IOM uint32_t DUXE : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t DUNE : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t CUXE : 1; /*!< [6..6] eXit from Ulps detect on Clock lane interrupt Enable */ + __IOM uint32_t CUNE : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane interrupt Enable */ + uint32_t : 24; + } PMIE_b; + }; + __IM uint32_t RESERVED26[29]; + + union + { + __IOM uint32_t GSCT; /*!< (@ 0x00000280) Generic Short Packet Control Register */ + + struct + { + __IOM uint32_t SHTH : 7; /*!< [6..0] Stored generic short packet THreshold */ + uint32_t : 9; + __IOM uint32_t GFIF : 1; /*!< [16..16] Generic short packet store in FIFo */ + uint32_t : 15; + } GSCT_b; + }; + + union + { + __IM uint32_t GSST; /*!< (@ 0x00000284) Generic Short Packet Status Register */ + + struct + { + __IM uint32_t GNE : 1; /*!< [0..0] Generic short packet fifo Not Empty */ + __IM uint32_t GTH : 1; /*!< [1..1] more than THreshold Generic short packets existed in + * fifo */ + uint32_t : 2; + __IM uint32_t GOV : 1; /*!< [4..4] Generic short packet fifo OVerflow status */ + uint32_t : 3; + __IM uint32_t PNUM : 8; /*!< [15..8] NUMber of stored generic short Packets in fifo */ + __IM uint32_t GCD : 1; /*!< [16..16] Generic short packet fifo Clear status */ + __IM uint32_t STRDS : 1; /*!< [17..17] generic short packet SToRe DiSable */ + uint32_t : 14; + } GSST_b; + }; + + union + { + __OM uint32_t GSSC; /*!< (@ 0x00000288) Generic Short Packet Status Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t GOVC : 1; /*!< [4..4] Generic short packet fifo OVerflow status Clear */ + uint32_t : 27; + } GSSC_b; + }; + + union + { + __IOM uint32_t GSIE; /*!< (@ 0x0000028C) Generic Short Packet Interrupt Enable Register */ + + struct + { + __IOM uint32_t GNEE : 1; /*!< [0..0] Generic short packet fifo Not Empty interrupt Enable */ + __IOM uint32_t GTHE : 1; /*!< [1..1] more than THreshold Generic short packets existed in + * fifo interrupt Enable */ + uint32_t : 2; + __IOM uint32_t GOVE : 1; /*!< [4..4] Generic short packet fifo OVerflow interrupt Enable */ + uint32_t : 27; + } GSIE_b; + }; + + union + { + __IM uint32_t GSHT; /*!< (@ 0x00000290) Generic Short Packet Register */ + + struct + { + __IM uint32_t SPDT : 16; /*!< [15..0] Stored Packet DaTa */ + __IM uint32_t DTYP : 6; /*!< [21..16] Stored packet Data TYPe */ + uint32_t : 2; + __IM uint32_t SPVC : 4; /*!< [27..24] Stored Packet Virtual Channel */ + uint32_t : 4; + } GSHT_b; + }; + + union + { + __IOM uint32_t GSIU; /*!< (@ 0x00000294) Generic Short Packet Information Update Register */ + + struct + { + __OM uint32_t FINC : 1; /*!< [0..0] generic short packet Fifo update (INCrement internal + * pointer) */ + uint32_t : 7; + __IOM uint32_t GFCLR : 1; /*!< [8..8] Generic short packet Fifo CLeaR */ + uint32_t : 7; + __OM uint32_t GFEN : 1; /*!< [16..16] Generic short packet Fifo ENable */ + uint32_t : 15; + } GSIU_b; + }; +} R_MIPI_CSI_Type; /*!< Size = 664 (0x298) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capture Engine Unit (R_CEU) + */ + +typedef struct /*!< (@ 0x40348000) R_CEU Structure */ +{ + union + { + __IOM uint32_t CAPSR; /*!< (@ 0x00000000) Capture Start Register */ + + struct + { + __IOM uint32_t CE : 1; /*!< [0..0] Capture enable */ + uint32_t : 15; + __IOM uint32_t CPKIL : 1; /*!< [16..16] Write 1 to this bit to perform a software reset of + * capturing. */ + uint32_t : 15; + } CAPSR_b; + }; + + union + { + __IOM uint32_t CAPCR; /*!< (@ 0x00000004) Capture Control Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CTNCP : 1; /*!< [16..16] When capturing is started with this bit set to 1, capturing + * continues until the CE bit in CAPSR is cleared to 0 or + * a software reset is initiated by the CPKIL bit in CAPSR + * (see ). Continuous capture must be set before capturing + * is started. */ + uint32_t : 3; + __IOM uint32_t MTCM : 2; /*!< [21..20] Specify the unit for transferring data to a bus bridge + * module. */ + uint32_t : 2; + __IOM uint32_t FDRP : 8; /*!< [31..24] Set the frame drop interval in continuous-frame capture. */ + } CAPCR_b; + }; + + union + { + __IOM uint32_t CAMCR; /*!< (@ 0x00000008) Capture interface control register */ + + struct + { + __IOM uint32_t HDPOL : 1; /*!< [0..0] Sets the polarity for detection of the horizontal sync + * signal input from an external module. */ + __IOM uint32_t VDPOL : 1; /*!< [1..1] Sets the polarity for detection of the vertical sync + * signal input from an external module. */ + uint32_t : 2; + __IOM uint32_t JPG : 2; /*!< [5..4] These bits select the fetched data type. */ + uint32_t : 2; + __IOM uint32_t DTARY : 2; /*!< [9..8] Set the input order of the luminance component and chrominance + * component. */ + uint32_t : 2; + __IOM uint32_t DTIF : 1; /*!< [12..12] Sets the digital image input pins from which data is + * to be captured. */ + uint32_t : 3; + __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal + * (FLD) from an external module. */ + uint32_t : 7; + __IOM uint32_t DSEL : 1; /*!< [24..24] Sets the edge for fetching the image data (D7 to D0) + * from an external module. */ + __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification + * signal (FLD) from an external module. */ + __IOM uint32_t HDSEL : 1; /*!< [26..26] Sets the edge for capturing the horizontal sync signal + * (HD) from an external module. */ + __IOM uint32_t VDSEL : 1; /*!< [27..27] Sets the edge for capturing the vertical sync signal + * (VD) from an external module. */ + uint32_t : 4; + } CAMCR_b; + }; + + union + { + __IOM uint32_t CMCYR; /*!< (@ 0x0000000C) Capture Interface Cycle Register */ + + struct + { + __IOM uint32_t HCYL : 14; /*!< [13..0] Horizontal Cycle Count of External Module */ + uint32_t : 2; + __IOM uint32_t VCYL : 14; /*!< [29..16] Vertical HD Count of External Module */ + uint32_t : 2; + } CMCYR_b; + }; + + union + { + __IOM uint32_t CAMOR; /*!< (@ 0x00000010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_b; + }; + + union + { + __IOM uint32_t CAPWR; /*!< (@ 0x00000014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_b; + }; + + union + { + __IOM uint32_t CAIFR; /*!< (@ 0x00000018) Capture Interface Input Format Register */ + + struct + { + __IOM uint32_t FCI : 2; /*!< [1..0] Set the timing to start capturing. */ + uint32_t : 2; + __IOM uint32_t CIM : 1; /*!< [4..4] Sets the images to be captured. */ + uint32_t : 3; + __IOM uint32_t IFS : 1; /*!< [8..8] Sets the input mode for capturing images. */ + uint32_t : 23; + } CAIFR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CRCNTR; /*!< (@ 0x00000028) CEU Register Control Register */ + + struct + { + __IOM uint32_t RC : 1; /*!< [0..0] Specifies switching of the register plane used by the + * CEU in synchronization with VD. */ + __IOM uint32_t RS : 1; /*!< [1..1] Specifies which register plane is used by the CEU in + * synchronization with VD. */ + uint32_t : 2; + __IOM uint32_t RVS : 1; /*!< [4..4] Sets the timing to switch the register plane in both-field + * capture. */ + uint32_t : 27; + } CRCNTR_b; + }; + + union + { + __IOM uint32_t CRCMPR; /*!< (@ 0x0000002C) CEU Register Forcible Control Register */ + + struct + { + __IOM uint32_t RA : 1; /*!< [0..0] Indicates the register plane currently specified. */ + uint32_t : 31; + } CRCMPR_b; + }; + + union + { + __IOM uint32_t CFLCR; /*!< (@ 0x00000030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_b; + }; + + union + { + __IOM uint32_t CFSZR; /*!< (@ 0x00000034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_b; + }; + + union + { + __IOM uint32_t CDWDR; /*!< (@ 0x00000038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_b; + }; + + union + { + __IOM uint32_t CDAYR; /*!< (@ 0x0000003C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_b; + }; + + union + { + __IOM uint32_t CDACR; /*!< (@ 0x00000040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_b; + }; + + union + { + __IOM uint32_t CDBYR; /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_b; + }; + + union + { + __IOM uint32_t CDBCR; /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_b; + }; + + union + { + __IOM uint32_t CBDSR; /*!< (@ 0x0000004C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFWCR; /*!< (@ 0x0000005C) Firewall Operation Control Register */ + + struct + { + __IOM uint32_t FWE : 1; /*!< [0..0] With the setting of FWE = 1, when an address exceeds + * the value set with FWV, the address is retained and an + * interrupt source FWF is set. After this, the address is + * not incremented and data is overwritten on the upper limit + * address. */ + uint32_t : 4; + __IOM uint32_t FWV : 27; /*!< [31..5] Specify the upper limit of a write address. */ + } CFWCR_b; + }; + + union + { + __IOM uint32_t CLFCR; /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_b; + }; + + union + { + __IOM uint32_t CDOCR; /*!< (@ 0x00000064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CEIER; /*!< (@ 0x00000070) Capture Event Interrupt Enable Register */ + + struct + { + __IOM uint32_t CPEIE : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable */ + __IOM uint32_t CFEIE : 1; /*!< [1..1] CFE Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t IGRWIE : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t HDIE : 1; /*!< [8..8] HD Interrupt Enable */ + __IOM uint32_t VDIE : 1; /*!< [9..9] VD Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable */ + __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable */ + __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable */ + __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable */ + __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable */ + __IOM uint32_t IGHSIE : 1; /*!< [17..17] IGHS Interrupt Enable */ + __IOM uint32_t IGVSIE : 1; /*!< [18..18] IGVS Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBPIE : 1; /*!< [20..20] VBP Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FWFIE : 1; /*!< [23..23] FWF Interrupt Enable */ + __IOM uint32_t NHDIE : 1; /*!< [24..24] Non-HD Interrupt Enable */ + __IOM uint32_t NVDIE : 1; /*!< [25..25] Non-VD Interrupt Enable */ + uint32_t : 6; + } CEIER_b; + }; + + union + { + __IOM uint32_t CETCR; /*!< (@ 0x00000074) Capture Event Flag Clear Register */ + + struct + { + __IOM uint32_t CPE : 1; /*!< [0..0] An interrupt indicating that capturing of one frame from + * an external module has finished. */ + __IOM uint32_t CFE : 1; /*!< [1..1] An interrupt indicating that capturing of one field from + * an external module has finished. */ + uint32_t : 2; + __IOM uint32_t IGRW : 1; /*!< [4..4] An interrupt indicating that during capturing, access + * was attempted to a register to which writing during operation + * is prohibited. */ + uint32_t : 3; + __IOM uint32_t HD : 1; /*!< [8..8] An interrupt indicating that HD (horizontal sync signal) + * was input from an external module. */ + __IOM uint32_t VD : 1; /*!< [9..9] An interrupt indicating that VD (vertical sync signal) + * was input from an external module. */ + uint32_t : 2; + __IOM uint32_t CPBE1 : 1; /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR + * in a bundle write has finished. */ + __IOM uint32_t CPBE2 : 1; /*!< [13..13] An interrupt indicating that writing to CDAYR2 and + * CDACR2 in a bundle write has finished. */ + __IOM uint32_t CPBE3 : 1; /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR + * in a bundle write has finished. */ + __IOM uint32_t CPBE4 : 1; /*!< [15..15] An interrupt indicating that writing to CDBYR2 and + * CDBCR2 in a bundle write has finished. */ + __IOM uint32_t CDTOF : 1; /*!< [16..16] An interrupt indicating that data overflowed in the + * CRAM of the write buffer */ + __IOM uint32_t IGHS : 1; /*!< [17..17] An interrupt generated when the number of HD cycles + * set in CMCYR differ from the number of HD cycles input + * from an external module. */ + __IOM uint32_t IGVS : 1; /*!< [18..18] An interrupt generated when the number of VD cycles + * set in CMCYR differ from the number of VD cycles input + * from an external module. */ + uint32_t : 1; + __IOM uint32_t VBP : 1; /*!< [20..20] An interrupt indicating that VD has been input while + * the CEU holds data (insufficient vertical-sync front porch). */ + uint32_t : 2; + __IOM uint32_t FWF : 1; /*!< [23..23] The interrupt is generated when data is written to + * the address that exceeds the value specified with CFWCR.FMV. */ + __IOM uint32_t NHD : 1; /*!< [24..24] An interrupt indicating that no HD was input. */ + __IOM uint32_t NVD : 1; /*!< [25..25] An interrupt indicating that no VD was input. */ + uint32_t : 6; + } CETCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t CSTSR; /*!< (@ 0x0000007C) Capture Status Register */ + + struct + { + __IM uint32_t CPTON : 1; /*!< [0..0] Indicates that the CEU is operating. */ + uint32_t : 15; + __IM uint32_t CPFLD : 1; /*!< [16..16] Indicates which field is being captured. */ + uint32_t : 7; + __IM uint32_t CRST : 1; /*!< [24..24] Indicates which register plane is currently used. */ + uint32_t : 7; + } CSTSR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t CDSSR; /*!< (@ 0x00000084) Capture Data Size Register */ + + struct + { + __IM uint32_t CDSS : 32; /*!< [31..0] Indicate the size of data written to the memory in data + * enable fetch. */ + } CDSSR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CDAYR2; /*!< (@ 0x00000090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_b; + }; + + union + { + __IOM uint32_t CDACR2; /*!< (@ 0x00000094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_b; + }; + + union + { + __IOM uint32_t CDBYR2; /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_b; + }; + + union + { + __IOM uint32_t CDBCR2; /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_b; + }; + + union + { + __IOM uint32_t AXIBUSCTL2; /*!< (@ 0x000000A0) AXI Bus Control Register 2 */ + + struct + { + __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit */ + uint32_t : 28; + } AXIBUSCTL2_b; + }; + __IM uint32_t RESERVED6[987]; + + union + { + __IOM uint32_t CAMOR_B; /*!< (@ 0x00001010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_B_b; + }; + + union + { + __IOM uint32_t CAPWR_B; /*!< (@ 0x00001014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_B_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t CFLCR_B; /*!< (@ 0x00001030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_B_b; + }; + + union + { + __IOM uint32_t CFSZR_B; /*!< (@ 0x00001034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_B_b; + }; + + union + { + __IOM uint32_t CDWDR_B; /*!< (@ 0x00001038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_B_b; + }; + + union + { + __IOM uint32_t CDAYR_B; /*!< (@ 0x0000103C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_B_b; + }; + + union + { + __IOM uint32_t CDACR_B; /*!< (@ 0x00001040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_B_b; + }; + + union + { + __IOM uint32_t CDBYR_B; /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_B_b; + }; + + union + { + __IOM uint32_t CDBCR_B; /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_B_b; + }; + + union + { + __IOM uint32_t CBDSR_B; /*!< (@ 0x0000104C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_B_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint32_t CLFCR_B; /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_B_b; + }; + + union + { + __IOM uint32_t CDOCR_B; /*!< (@ 0x00001064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_B_b; + }; + __IM uint32_t RESERVED9[10]; + + union + { + __IOM uint32_t CDAYR2_B; /*!< (@ 0x00001090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_B_b; + }; + + union + { + __IOM uint32_t CDACR2_B; /*!< (@ 0x00001094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_B_b; + }; + + union + { + __IOM uint32_t CDBYR2_B; /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_B_b; + }; + + union + { + __IOM uint32_t CDBCR2_B; /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_B_b; + }; + __IM uint32_t RESERVED10[988]; + + union + { + __IOM uint32_t CAMOR_M; /*!< (@ 0x00002010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_M_b; + }; + + union + { + __IOM uint32_t CAPWR_M; /*!< (@ 0x00002014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_M_b; + }; + __IM uint32_t RESERVED11[6]; + + union + { + __IOM uint32_t CFLCR_M; /*!< (@ 0x00002030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_M_b; + }; + + union + { + __IOM uint32_t CFSZR_M; /*!< (@ 0x00002034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_M_b; + }; + + union + { + __IOM uint32_t CDWDR_M; /*!< (@ 0x00002038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_M_b; + }; + + union + { + __IOM uint32_t CDAYR_M; /*!< (@ 0x0000203C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_M_b; + }; + + union + { + __IOM uint32_t CDACR_M; /*!< (@ 0x00002040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_M_b; + }; + + union + { + __IOM uint32_t CDBYR_M; /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_M_b; + }; + + union + { + __IOM uint32_t CDBCR_M; /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_M_b; + }; + + union + { + __IOM uint32_t CBDSR_M; /*!< (@ 0x0000204C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_M_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CLFCR_M; /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_M_b; + }; + + union + { + __IOM uint32_t CDOCR_M; /*!< (@ 0x00002064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_M_b; + }; + __IM uint32_t RESERVED13[10]; + + union + { + __IOM uint32_t CDAYR2_M; /*!< (@ 0x00002090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_M_b; + }; + + union + { + __IOM uint32_t CDACR2_M; /*!< (@ 0x00002094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_M_b; + }; + + union + { + __IOM uint32_t CDBYR2_M; /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_M_b; + }; + + union + { + __IOM uint32_t CDBCR2_M; /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_M_b; + }; +} R_CEU_Type; /*!< Size = 8352 (0x20a0) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ultra-Low Power Timer 0 (R_ULPT0) + */ + +typedef struct /*!< (@ 0x40220000) R_ULPT0 Structure */ +{ + union + { + __IOM uint32_t ULPTCNT; /*!< (@ 0x00000000) ULPT Counter Register */ + + struct + { + __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, the 32-bit counter + * is forcibly stopped and set to FFFFFFFFH. */ + } ULPTCNT_b; + }; + + union + { + __IOM uint32_t ULPTCMA; /*!< (@ 0x00000004) ULPT Compare Match A Register */ + + struct + { + __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMA_b; + }; + + union + { + __IOM uint32_t ULPTCMB; /*!< (@ 0x00000008) ULPT Compare Match B Register */ + + struct + { + __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMB_b; + }; + + union + { + __IOM uint8_t ULPTCR; /*!< (@ 0x0000000C) ULPT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] ULPT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] ULPT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] ULPT count forced stop */ + uint8_t : 2; + __IOM uint8_t TUNDF : 1; /*!< [5..5] ULPT underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] ULPT compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] ULPT compare match B flag */ + } ULPTCR_b; + }; + + union + { + __IOM uint8_t ULPTMR1; /*!< (@ 0x0000000D) ULPT Mode Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t TMOD1 : 1; /*!< [1..1] ULPT operating mode select */ + uint8_t : 1; + __IOM uint8_t TEDGPL : 1; /*!< [3..3] ULPTEVI edge polarity select */ + uint8_t : 1; + __IOM uint8_t TCK1 : 1; /*!< [5..5] ULPT count source select */ + uint8_t : 2; + } ULPTMR1_b; + }; + + union + { + __IOM uint8_t ULPTMR2; /*!< (@ 0x0000000E) ULPT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] fsub/LOCO count source clock frequency division ratio + * select */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] ULPT Low Power Mode */ + } ULPTMR2_b; + }; + + union + { + __IOM uint8_t ULPTMR3; /*!< (@ 0x0000000F) ULPT Mode Register 3 */ + + struct + { + __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select */ + __IOM uint8_t TEVPOL : 1; /*!< [1..1] ULPTEVI polarity switch */ + __IOM uint8_t TOPOL : 1; /*!< [2..2] ULPTO polarity select */ + uint8_t : 1; + __IOM uint8_t TEECTL : 2; /*!< [5..4] ULPTEE function select */ + __IOM uint8_t TEEPOL : 2; /*!< [7..6] ULPTEE edge polarity select */ + } ULPTMR3_b; + }; + + union + { + __IOM uint8_t ULPTIOC; /*!< (@ 0x00000010) ULPT I/O Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t TOE : 1; /*!< [2..2] ULPTO output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] ULPTEVI input filter select */ + __IOM uint8_t TIOGT0 : 1; /*!< [6..6] ULPTEVI count control */ + uint8_t : 1; + } ULPTIOC_b; + }; + + union + { + __IOM uint8_t ULPTISR; /*!< (@ 0x00000011) ULPT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection */ + uint8_t : 5; + } ULPTISR_b; + }; + + union + { + __IOM uint8_t ULPTCMSR; /*!< (@ 0x00000012) ULPT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] ULPTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] ULPTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] ULPTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] ULPTOB polarity select */ + uint8_t : 1; + } ULPTCMSR_b; + }; + __IM uint8_t RESERVED; +} R_ULPT0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief On-Chip Debug Function (R_DEBUG_OCD) + */ + +typedef struct /*!< (@ 0x40011000) R_DEBUG_OCD Structure */ +{ + union + { + __IM uint32_t MCUERRSTAT; /*!< (@ 0x00000000) MCU Error Status Register */ + + struct + { + __IM uint32_t ZERO : 1; /*!< [0..0] Zeroization status flag */ + uint32_t : 31; + } MCUERRSTAT_b; + }; + + union + { + __IOM uint32_t MCUCTRL; /*!< (@ 0x00000004) MCU Control Register */ + + struct + { + __IOM uint32_t EDBGRQ0 : 1; /*!< [0..0] External Debug Request for CPU0 */ + __IOM uint32_t EDBGRQ1 : 1; /*!< [1..1] External Debug Request for CPU1 */ + uint32_t : 6; + __IOM uint32_t DBIRQ0 : 1; /*!< [8..8] Writing 1 to the bit wakes up the CPU0 from Deep Sleep + * mode or the MCU from Software Standby Mode or Deep Software + * Standby mode */ + __IOM uint32_t DBIRQ1 : 1; /*!< [9..9] Writing 1 to the bit wakes up the CPU1 from Deep Sleep + * mode or the MCU from Software Standby Mode or Deep Software + * Standby mode */ + uint32_t : 6; + __IOM uint32_t CPUWAIT0 : 1; /*!< [16..16] CPU0 WAIT SETTING */ + __IOM uint32_t CPUWAIT1 : 1; /*!< [17..17] CPU1 WAIT SETTING */ + uint32_t : 14; + } MCUCTRL_b; + }; + __IM uint32_t RESERVED[62]; + + union + { + __IOM uint32_t JBMDR; /*!< (@ 0x00000100) JTAG Boot Mode Entry Register */ + + struct + { + __IOM uint32_t KEY : 8; /*!< [7..0] Mode entry key */ + uint32_t : 24; + } JBMDR_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t JBRDR; /*!< (@ 0x00000120) JTAG Boot Receive Data Register */ + + struct + { + __IOM uint32_t RDAT : 32; /*!< [31..0] Received data register */ + } JBRDR_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t JBTDR; /*!< (@ 0x00000130) JTAG Boot Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 32; /*!< [31..0] Transmitted data register */ + } JBTDR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t JBSTR; /*!< (@ 0x00000140) JTAG Boot Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive buffer full */ + __IOM uint32_t TDE : 1; /*!< [1..1] Transmit data empty */ + uint32_t : 30; + } JBSTR_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t JBICR; /*!< (@ 0x00000150) JTAG Boot Interrupt Control Register */ + + struct + { + __IOM uint32_t RDFIE : 1; /*!< [0..0] Receive buffer full interrupt enabled */ + uint32_t : 31; + } JBICR_b; + }; + __IM uint32_t RESERVED5[107]; + + union + { + __IM uint32_t FSBLSTATM; /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register */ + + struct + { + __IM uint32_t CS : 1; /*!< [0..0] FSBL completion status */ + __IM uint32_t RS : 1; /*!< [1..1] FSBL result status */ + uint32_t : 30; + } FSBLSTATM_b; + }; +} R_DEBUG_OCD_Type; /*!< Size = 772 (0x304) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Decryption On The Fly (R_DOTF) + */ + +typedef struct /*!< (@ 0x40268800) R_DOTF Structure */ +{ + union + { + __IOM uint32_t CONVAREAST; /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area */ + } CONVAREAST_b; + }; + + union + { + __IOM uint32_t CONVAREAD; /*!< (@ 0x00000004) DOTF Conversion Area End Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area */ + } CONVAREAD_b; + }; + __IM uint32_t RESERVED[30]; + + union + { + __IOM uint32_t REG00; /*!< (@ 0x00000080) Register 0 */ + + struct + { + uint32_t : 9; + __IOM uint32_t B09 : 1; /*!< [9..9] Bit 09 */ + uint32_t : 6; + __IOM uint32_t B16 : 1; /*!< [16..16] Bit 09 */ + __IOM uint32_t B17 : 1; /*!< [17..17] Bit 17 */ + uint32_t : 2; + __IOM uint32_t B20 : 1; /*!< [20..20] Bit 20 */ + uint32_t : 3; + __IOM uint32_t B24 : 2; /*!< [25..24] Bit24-25 */ + uint32_t : 2; + __IOM uint32_t B28 : 2; /*!< [29..28] Bit28-29 */ + uint32_t : 2; + } REG00_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t REG03; /*!< (@ 0x0000008C) Register 03 */ + + struct + { + __IOM uint32_t B00 : 32; /*!< [31..0] Bit 0 */ + } REG03_b; + }; +} R_DOTF_Type; /*!< Size = 144 (0x90) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_COMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Common Agent (R_COMA) + */ + +typedef struct /*!< (@ 0x403C9000) R_COMA Structure */ +{ + union + { + __IM uint32_t RIPV; /*!< (@ 0x00000000) IP Version Register */ + + struct + { + __IM uint32_t TIPV : 4; /*!< [3..0] Top Module IP Version Number */ + __IM uint32_t GWIPV : 4; /*!< [7..4] Gateway CPU Agent IP Version Number */ + __IM uint32_t FWIPV : 4; /*!< [11..8] Forwarding Engine IP Version Number */ + __IM uint32_t EAIPV : 4; /*!< [15..12] Ethernet Agent IP Version Number */ + __IM uint32_t FBIPV : 4; /*!< [19..16] Fabric Bus IP Version Number */ + __IM uint32_t CAIPV : 4; /*!< [23..20] Common Agent IP Version Number */ + uint32_t : 8; + } RIPV_b; + }; + + union + { + __IOM uint32_t RRC; /*!< (@ 0x00000004) Reset Configuration Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Software Reset */ + uint32_t : 31; + } RRC_b; + }; + + union + { + __IOM uint32_t RCEC; /*!< (@ 0x00000008) Clock Enable Configuration Register */ + + struct + { + __IOM uint32_t ACE : 7; /*!< [6..0] Agent Clock Enable */ + uint32_t : 9; + __IOM uint32_t RCE : 1; /*!< [16..16] Clock Enable */ + uint32_t : 15; + } RCEC_b; + }; + + union + { + __IM uint32_t RCDC; /*!< (@ 0x0000000C) Clock Disable Configuration Register */ + + struct + { + __IM uint32_t ACD : 7; /*!< [6..0] Agent Clock Disable */ + uint32_t : 9; + __IM uint32_t RCD : 1; /*!< [16..16] Clock Disable */ + uint32_t : 15; + } RCDC_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t CABPIBWMC[8]; /*!< (@ 0x00000020) Buffer Pool IPV Based Watermark Configuration + * Register [0..7] */ + + struct + { + __IOM uint32_t IBUWMPN : 10; /*!< [9..0] IPV Based Unsecure Watermark Pointer Number */ + uint32_t : 6; + __IOM uint32_t IBSWMPN : 10; /*!< [25..16] IPV Based Secure Watermark Pointer Number */ + uint32_t : 6; + } CABPIBWMC_b[8]; + }; + + union + { + __IOM uint32_t CABPWMLC; /*!< (@ 0x00000040) Buffer Pool Watermark Level Configuration Register */ + + struct + { + __IOM uint32_t WMFL : 13; /*!< [12..0] Watermark Flush Level */ + uint32_t : 3; + __IOM uint32_t WMCL : 13; /*!< [28..16] Watermark Critical Level */ + uint32_t : 3; + } CABPWMLC_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CABPPFLC[2]; /*!< (@ 0x00000050) Buffer Pointer Pause Frame Level [0..1] Configuration + * Register */ + + struct + { + __IOM uint32_t PDL : 13; /*!< [12..0] Pause De-Assertion Level */ + uint32_t : 3; + __IOM uint32_t PAL : 13; /*!< [28..16] Pause Assertion Level */ + uint32_t : 3; + } CABPPFLC_b[2]; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CABPPWMLC[3]; /*!< (@ 0x00000060) Port [0..2] Buffer Pool Watermark Level Configuration + * Register */ + + struct + { + __IOM uint32_t PWMFL : 13; /*!< [12..0] Watermark Flush Level */ + uint32_t : 3; + __IOM uint32_t PWMCL : 13; /*!< [28..16] Watermark Critical Level */ + uint32_t : 3; + } CABPPWMLC_b[3]; + }; + __IM uint32_t RESERVED3[13]; + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC0; /*!< (@ 0x000000A0) 0 */ + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC1; /*!< (@ 0x000000A8) 1 */ + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC2; /*!< (@ 0x000000B0) 2 */ + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CABPULC[3]; /*!< (@ 0x00000100) Buffer Pointer Utilization Level Configuration + * Register [0..2] */ + + struct + { + __IOM uint32_t MXNPN : 13; /*!< [12..0] Maximum Number of Pointer for Port */ + uint32_t : 3; + __IOM uint32_t MNNPN : 13; /*!< [28..16] Minimum Number of Pointer for Port */ + uint32_t : 3; + } CABPULC_b[3]; + }; + __IM uint32_t RESERVED5[13]; + + union + { + __IOM uint32_t CABPIRM; /*!< (@ 0x00000140) Buffer Pool Initialization Register Monitoring + * Register */ + + struct + { + __IOM uint32_t BPIOG : 1; /*!< [0..0] Buffer Pool Initialization Ongoing */ + __IOM uint32_t BPR : 1; /*!< [1..1] Buffer Pool Ready */ + uint32_t : 30; + } CABPIRM_b; + }; + + union + { + __IM uint32_t CABPPCM; /*!< (@ 0x00000144) Buffer Pool Pointer Count Monitoring Register */ + + struct + { + __IM uint32_t RPC : 13; /*!< [12..0] Remaining Pointer Count */ + uint32_t : 3; + __IM uint32_t TPC : 13; /*!< [28..16] Total Pointer Count */ + uint32_t : 3; + } CABPPCM_b; + }; + + union + { + __IM uint32_t CABPLCM; /*!< (@ 0x00000148) Buffer Pool Pointer Least Count Monitoring Register */ + + struct + { + __IM uint32_t LRC : 13; /*!< [12..0] Least Remaining Pointer Count */ + uint32_t : 19; + } CABPLCM_b; + }; + __IM uint32_t RESERVED6[13]; + + union + { + __IM uint32_t CABPCPM[3]; /*!< (@ 0x00000180) Port [0..2] Buffer Pointer Count Monitoring Register */ + + struct + { + __IM uint32_t RPCP : 13; /*!< [12..0] Received Pointer Count */ + uint32_t : 19; + } CABPCPM_b[3]; + }; + __IM uint32_t RESERVED7[29]; + + union + { + __IM uint32_t CABPMCPM[3]; /*!< (@ 0x00000200) Port [0..2] Buffer Pointer Maximum Count Monitoring + * Register */ + + struct + { + __IM uint32_t RPMCP : 13; /*!< [12..0] Received Pointer Maximum Count */ + uint32_t : 19; + } CABPMCPM_b[3]; + }; + __IM uint32_t RESERVED8[61]; + + union + { + __IM uint32_t CARDNM; /*!< (@ 0x00000300) Rejected Descriptor Number Monitoring Register */ + + struct + { + __IM uint32_t RDNRR : 13; /*!< [12..0] Rejected Descriptor Number in Reject RAM */ + uint32_t : 19; + } CARDNM_b; + }; + + union + { + __IM uint32_t CARDMNM; /*!< (@ 0x00000304) Rejected Descriptor Maximum Number Monitoring + * Register */ + + struct + { + __IM uint32_t RDMNRR : 13; /*!< [12..0] Rejected Descriptor Maximum Number in Reject RAM */ + uint32_t : 19; + } CARDMNM_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IM uint32_t CARDCN; /*!< (@ 0x00000310) Rejected Descriptor Counter Register */ + + struct + { + __IM uint32_t RDN : 32; /*!< [31..0] Rejected Descriptor Number */ + } CARDCN_b; + }; + __IM uint32_t RESERVED10[59]; + + union + { + __IOM uint32_t CAEIS0; /*!< (@ 0x00000400) Error Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t PECCES : 1; /*!< [0..0] Pointer ECC Error Interrupt Status */ + __IOM uint32_t DSECCES : 1; /*!< [1..1] Descriptor ECC Error Interrupt Status */ + __IOM uint32_t BPECCES : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Status */ + uint32_t : 5; + __IOM uint32_t BPOPS : 1; /*!< [8..8] Buffer Pool Out of Pointer Status */ + __IOM uint32_t WMCLOS : 1; /*!< [9..9] Watermark Critical Level Overtook Status */ + __IOM uint32_t WMFLOS : 1; /*!< [10..10] Watermark Flush Level Overtook Status */ + uint32_t : 5; + __IM uint32_t EEIPLN : 4; /*!< [19..16] ECC Error Inducing Pointer Loss Number */ + uint32_t : 12; + } CAEIS0_b; + }; + + union + { + __IOM uint32_t CAEIE0; /*!< (@ 0x00000404) Error Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t PECCEE : 1; /*!< [0..0] Pointer ECC Error Interrupt Enable */ + __IOM uint32_t DSECCEE : 1; /*!< [1..1] Descriptor ECC Error Interrupt Enable */ + __IOM uint32_t BPECCEE : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t BPOPE : 1; /*!< [8..8] Buffer Pool Out of Pointer Enable */ + __IOM uint32_t WMCLOE : 1; /*!< [9..9] Watermark Critical Level Overtook Enable */ + __IOM uint32_t WMFLOE : 1; /*!< [10..10] Watermark Flush Level Overtook Enable */ + uint32_t : 21; + } CAEIE0_b; + }; + + union + { + __IM uint32_t CAEID0; /*!< (@ 0x00000408) Error Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t PECCED : 1; /*!< [0..0] Pointer ECC Error Interrupt Disable */ + __IM uint32_t DSECCED : 1; /*!< [1..1] Descriptor ECC Error Interrupt Disable */ + __IM uint32_t BPECCED : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Disable */ + uint32_t : 5; + __IM uint32_t BPOPD : 1; /*!< [8..8] Buffer Pool Out of Pointer Disable */ + __IM uint32_t WMCLOD : 1; /*!< [9..9] Watermark Critical Level Overtook Disable */ + __IM uint32_t WMFLOD : 1; /*!< [10..10] Watermark Flush Level Overtook Disable */ + uint32_t : 21; + } CAEID0_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CAEIS1; /*!< (@ 0x00000410) Error Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t PWMCLOS : 7; /*!< [6..0] Port Watermark Critical Level Overtook Status */ + uint32_t : 9; + __IOM uint32_t PWMFLOS : 7; /*!< [22..16] Port Watermark Flush Level Overtook Status */ + uint32_t : 9; + } CAEIS1_b; + }; + + union + { + __IOM uint32_t CAEIE1; /*!< (@ 0x00000414) Error Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t PWMCLOE : 7; /*!< [6..0] Port Watermark Critical Level Overtook Enable */ + uint32_t : 9; + __IOM uint32_t PWMFLOE : 7; /*!< [22..16] Port Watermark Flush Level Overtook Enable */ + uint32_t : 9; + } CAEIE1_b; + }; + + union + { + __IM uint32_t CAEID1; /*!< (@ 0x00000418) Error Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t PWMCLOD : 7; /*!< [6..0] Port Watermark Critical Level Overtook Disable */ + uint32_t : 9; + __IM uint32_t PWMFLOD : 7; /*!< [22..16] Port Watermark Flush Level Overtook Disable */ + uint32_t : 9; + } CAEID1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint32_t CAMIS0; /*!< (@ 0x00000440) Monitoring Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t PFS : 2; /*!< [1..0] Pause Frame Status */ + uint32_t : 30; + } CAMIS0_b; + }; + + union + { + __IOM uint32_t CAMIE0; /*!< (@ 0x00000444) Monitoring Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t PFE : 2; /*!< [1..0] Pause Frame Enable */ + uint32_t : 30; + } CAMIE0_b; + }; + + union + { + __IM uint32_t CAMID0; /*!< (@ 0x00000448) Monitoring Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t PFD : 2; /*!< [1..0] Pause Frame Disable */ + uint32_t : 30; + } CAMID0_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t CAMIS1; /*!< (@ 0x00000450) Monitoring Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t PPFS : 14; /*!< [13..0] Port Pause Frame Status */ + uint32_t : 18; + } CAMIS1_b; + }; + + union + { + __IOM uint32_t CAMIE1; /*!< (@ 0x00000454) Monitoring Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t PPFE : 14; /*!< [13..0] Port Pause Frame Enable */ + uint32_t : 18; + } CAMIE1_b; + }; + + union + { + __IM uint32_t CAMID1; /*!< (@ 0x00000458) Monitoring Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t PPFD : 14; /*!< [13..0] Port Pause Frame Disable */ + uint32_t : 18; + } CAMID1_b; + }; +} R_COMA_Type; /*!< Size = 1116 (0x45c) */ + +/* =========================================================================================================================== */ +/* ================ R_CPU_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Individual CPU Control (R_CPU_CTRL) + */ + +typedef struct /*!< (@ 0x4000F000) R_CPU_CTRL Structure */ +{ + __IM uint32_t RESERVED[12]; + + union + { + __IOM uint8_t CPU0LCKUPCR; /*!< (@ 0x00000030) CPU0 Lockup Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection of CPUn lockup */ + uint8_t : 7; + } CPU0LCKUPCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t CPU1LCKUPCR; /*!< (@ 0x00000034) CPU1 Lockup Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection of CPUn lockup */ + uint8_t : 7; + } CPU1LCKUPCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CPU0INITVTOR; /*!< (@ 0x00000040) CPU0 Initial Vector Base Address Register */ + + struct + { + __IOM uint32_t CPUnINITVTOR : 32; /*!< [31..0] CPUn Initial Vector Base Address */ + } CPU0INITVTOR_b; + }; + + union + { + __IOM uint32_t CPU1INITVTOR; /*!< (@ 0x00000044) CPU1 Initial Vector Base Address Register */ + + struct + { + __IOM uint32_t CPUnINITVTOR : 32; /*!< [31..0] CPUn Initial Vector Base Address */ + } CPU1INITVTOR_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint8_t CPU0WAITCR; /*!< (@ 0x00000050) CPU0 CPUWAIT Control Register */ + + struct + { + __IOM uint8_t CPUWAIT : 1; /*!< [0..0] Writing 1 to stall the CPUn when it is out of reset */ + uint8_t : 7; + } CPU0WAITCR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t CPU1WAITCR; /*!< (@ 0x00000054) CPU1 CPUWAIT Control Register */ + + struct + { + __IOM uint8_t CPUWAIT : 1; /*!< [0..0] Writing 1 to stall the CPUn when it is out of reset */ + uint8_t : 7; + } CPU1WAITCR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint16_t CPU0ACTCSR; /*!< (@ 0x00000060) CPU0 Activation Control and Status Register */ + + struct + { + __IOM uint16_t ACTREQ : 1; /*!< [0..0] CPUn activation request */ + uint16_t : 6; + __IM uint16_t ACT : 1; /*!< [7..7] CPUn activation state */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key code */ + } CPU0ACTCSR_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t CPU1ACTCSR; /*!< (@ 0x00000064) CPU1 Activation Control and Status Register */ + + struct + { + __IOM uint16_t ACTREQ : 1; /*!< [0..0] CPUn activation request */ + uint16_t : 6; + __IM uint16_t ACT : 1; /*!< [7..7] CPUn activation state */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key code */ + } CPU1ACTCSR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[2]; + + union + { + __IOM uint8_t CPU0LMECR; /*!< (@ 0x00000070) CPU0 Local Memory Error Control Register */ + + struct + { + __IOM uint8_t SYRSTEN : 1; /*!< [0..0] System Reset request enable */ + uint8_t : 7; + } CPU0LMECR_b; + }; + __IM uint8_t RESERVED15; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17; + + union + { + __IOM uint8_t CPUIDR; /*!< (@ 0x00000078) CPU Identification Register */ + + struct + { + __IM uint8_t CPUID : 1; /*!< [0..0] CPU Identification */ + uint8_t : 7; + } CPUIDR_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20; + + union + { + __IOM uint8_t CPU0STATM; /*!< (@ 0x00000080) CPU0 Status Monitor Register */ + + struct + { + __IM uint8_t SLEEPING : 1; /*!< [0..0] Sleeping State */ + __IM uint8_t SLEEPDEEP : 1; /*!< [1..1] Indicates that the processor is at a Deep Sleep mode */ + uint8_t : 2; + __IM uint8_t SAHBSTP : 1; /*!< [4..4] S-AHB Status Flag */ + uint8_t : 3; + } CPU0STATM_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IOM uint8_t CPU1STATM; /*!< (@ 0x00000084) CPU1 Status Monitor Register */ + + struct + { + __IM uint8_t SLEEPING : 1; /*!< [0..0] Sleeping State */ + __IM uint8_t SLEEPDEEP : 1; /*!< [1..1] Indicates that the processor is at a Deep Sleep mode */ + uint8_t : 2; + __IM uint8_t SAHBSTP : 1; /*!< [4..4] S-AHB Status Flag */ + uint8_t : 3; + } CPU1STATM_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[2]; + + union + { + __IOM uint8_t SECEXTMON; /*!< (@ 0x00000090) CPU SECEXT Monitor Register */ + + struct + { + __IM uint8_t SECEXT0 : 1; /*!< [0..0] CPU0 Security Extension */ + __IM uint8_t SECEXT1 : 1; /*!< [1..1] CPU1 Security Extension */ + uint8_t : 6; + } SECEXTMON_b; + }; + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + + union + { + __IOM uint32_t NSCPUCR; /*!< (@ 0x00000094) Non-secure CPU Control Register */ + + struct + { + __IOM uint32_t RSTREQEN : 1; /*!< [0..0] System Reset Request Enable */ + uint32_t : 31; + } NSCPUCR_b; + }; + __IM uint32_t RESERVED28[218]; + + union + { + __IOM uint8_t CPU0LOCKCR; /*!< (@ 0x00000400) CPU0 Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKSVTAIR : 1; /*!< [0..0] Disables writes to secure registers VTOR_S, AIRCR.PRIS, + * AIRCR.BFHFNMINS */ + __IOM uint8_t LCKSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Secure MPU region */ + __IOM uint8_t LCKSAU : 1; /*!< [2..2] Disables writes to registers that are associated with + * the SAU region */ + __IOM uint8_t LCKITGU : 1; /*!< [3..3] Disables writes to registers that are associated with + * the ITCM interface */ + __IOM uint8_t LCKDTGU : 1; /*!< [4..4] Disables writes to registers that are associated with + * the DTCM interface */ + __IOM uint8_t LCKDCAIC : 1; /*!< [5..5] Disable access to the instruction cache direct cache + * access registers DCAICLR and DCAICRR */ + uint8_t : 2; + } CPU0LOCKCR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t CPU1LOCKCR; /*!< (@ 0x00000404) CPU1 Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKSVTAIR : 1; /*!< [0..0] Disables writes to secure registers VTOR_S, AIRCR.PRIS, + * AIRCR.BFHFNMINS */ + __IOM uint8_t LCKSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Secure MPU region */ + __IOM uint8_t LCKSAU : 1; /*!< [2..2] Disables writes to registers that are associated with + * the SAU region */ + __IOM uint8_t LCKITGU : 1; /*!< [3..3] Disables writes to registers that are associated with + * the ITCM interface */ + __IOM uint8_t LCKDTGU : 1; /*!< [4..4] Disables writes to registers that are associated with + * the DTCM interface */ + __IOM uint8_t LCKDCAIC : 1; /*!< [5..5] Disable access to the instruction cache direct cache + * access registers DCAICLR and DCAICRR */ + uint8_t : 2; + } CPU1LOCKCR_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33[62]; + + union + { + __IOM uint8_t CPU0LOCKCRNS; /*!< (@ 0x00000500) CPU0 Non-secure Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKNSVTOR : 1; /*!< [0..0] Disables writes to the VTOR_NS register */ + __IOM uint8_t LCKNSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Non-secure MPU region */ + uint8_t : 6; + } CPU0LOCKCRNS_b; + }; + __IM uint8_t RESERVED34; + __IM uint16_t RESERVED35; + + union + { + __IOM uint8_t CPU1LOCKCRNS; /*!< (@ 0x00000504) CPU1 Non-secure Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKNSVTOR : 1; /*!< [0..0] Disables writes to the VTOR_NS register */ + __IOM uint8_t LCKNSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Non-secure MPU region */ + uint8_t : 6; + } CPU1LOCKCRNS_b; + }; + __IM uint8_t RESERVED36; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[206]; + + union + { + __IOM uint16_t CPU0CRPT; /*!< (@ 0x00000840) CPU0 Control Register Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key to enable/disable writing to PROTECT */ + } CPU0CRPT_b; + }; + __IM uint16_t RESERVED39; + + union + { + __IOM uint16_t CPU1CRPT; /*!< (@ 0x00000844) CPU1 Control Register Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key to enable/disable writing to PROTECT */ + } CPU1CRPT_b; + }; + __IM uint16_t RESERVED40; +} R_CPU_CTRL_Type; /*!< Size = 2120 (0x848) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_ESWM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Layer 3 Ethernet Switch Module (R_ESWM) + */ + +typedef struct /*!< (@ 0x403C8000) R_ESWM Structure */ +{ + union + { + __IOM uint32_t TPEMIMC0; /*!< (@ 0x00000000) Error and Monitoring Interrupt Mapping Configuration + * Register 0 */ + + struct + { + __IOM uint32_t SEIM : 1; /*!< [0..0] Switch Error Interrupt Mapping */ + __IOM uint32_t SEIGM : 1; /*!< [1..1] Switch Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SEICM : 3; /*!< [6..4] Switch Error Interrupt Core Mapping */ + uint32_t : 9; + __IOM uint32_t SSIM0 : 1; /*!< [16..16] Switch Status Interrupt 0 Mapping */ + __IOM uint32_t SSIGM0 : 1; /*!< [17..17] Switch Status Interrupt 0 GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SSICM0 : 3; /*!< [22..20] Switch Status Interrupt 0 Core Mapping */ + uint32_t : 1; + __IOM uint32_t SSIM1 : 1; /*!< [24..24] Switch Status Interrupt 1 Mapping */ + __IOM uint32_t SSIGM1 : 1; /*!< [25..25] Switch Status Interrupt 1 GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SSICM1 : 3; /*!< [30..28] Switch Status Interrupt 1 Core Mapping */ + uint32_t : 1; + } TPEMIMC0_b; + }; + + union + { + __IOM uint32_t TPEMIMC1; /*!< (@ 0x00000004) Error and Monitoring Interrupt Mapping Configuration + * Register 1 */ + + struct + { + __IOM uint32_t FEIM : 1; /*!< [0..0] MFWD Error Interrupt Mapping */ + __IOM uint32_t FEIGM : 1; /*!< [1..1] MFWD Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t FEICM : 3; /*!< [6..4] MFWD Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t FSIM : 1; /*!< [8..8] MFWD Status Interrupt Mapping */ + __IOM uint32_t FSIGM : 1; /*!< [9..9] MFWD Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t FSICM : 3; /*!< [14..12] MFWD Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t CEIM : 1; /*!< [16..16] COMA Error Interrupt Mapping */ + __IOM uint32_t CEIGM : 1; /*!< [17..17] COMA Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t CEICM : 3; /*!< [22..20] COMA Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t CSIM : 1; /*!< [24..24] COMA Status Interrupt Mapping */ + __IOM uint32_t CSIGM : 1; /*!< [25..25] COMA Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t CSICM : 3; /*!< [30..28] COMA Status Interrupt Core Mapping */ + uint32_t : 1; + } TPEMIMC1_b; + }; + + union + { + __IOM uint32_t TPEMIMC2; /*!< (@ 0x00000008) Error and Monitoring Interrupt Mapping Configuration + * Register 2 */ + + struct + { + __IOM uint32_t GEIM0 : 1; /*!< [0..0] GWCA0 Error Interrupt Mapping */ + __IOM uint32_t GEIGM0 : 1; /*!< [1..1] GWCA0 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t GEICM0 : 3; /*!< [6..4] GWCA0 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t GSIM0 : 1; /*!< [8..8] GWCA0 Status Interrupt Mapping */ + __IOM uint32_t GSIGM0 : 1; /*!< [9..9] GWCA0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t GSICM0 : 3; /*!< [14..12] GWCA0 Status Interrupt Core Mapping */ + uint32_t : 17; + } TPEMIMC2_b; + }; + + union + { + __IOM uint32_t TPEMIMC3; /*!< (@ 0x0000000C) Error and Monitoring Interrupt Mapping Configuration + * Register 3 */ + + struct + { + __IOM uint32_t EEIM0 : 1; /*!< [0..0] ETHA0 Error Interrupt Mapping */ + __IOM uint32_t EEIGM0 : 1; /*!< [1..1] ETHA0 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t EEICM0 : 3; /*!< [6..4] ETHA0 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t ESIM0 : 1; /*!< [8..8] ETHA0 Status Interrupt Mapping */ + __IOM uint32_t ESIGM0 : 1; /*!< [9..9] ETHA0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t ESICM0 : 3; /*!< [14..12] ETHA0 Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t RSIM0 : 1; /*!< [16..16] RMAC0 Status Interrupt Mapping */ + __IOM uint32_t RSIGM0 : 1; /*!< [17..17] RMAC0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t RSICM0 : 3; /*!< [22..20] RMAC0 Status Interrupt Core Mapping */ + uint32_t : 9; + } TPEMIMC3_b; + }; + + union + { + __IOM uint32_t TPEMIMC4; /*!< (@ 0x00000010) Error and Monitoring Interrupt Mapping Configuration + * Register 4 */ + + struct + { + __IOM uint32_t EEIM1 : 1; /*!< [0..0] ETHA1 Error Interrupt Mapping */ + __IOM uint32_t EEIGM1 : 1; /*!< [1..1] ETHA1 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t EEICM1 : 3; /*!< [6..4] ETHA1 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t ESIM1 : 1; /*!< [8..8] ETHA1 Status Interrupt Mapping */ + __IOM uint32_t ESIGM1 : 1; /*!< [9..9] ETHA1 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t ESICM1 : 3; /*!< [14..12] ETHA1 Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t RSIM1 : 1; /*!< [16..16] RMAC1 Status Interrupt Mapping */ + __IOM uint32_t RSIGM1 : 1; /*!< [17..17] RMAC1 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t RSICM1 : 3; /*!< [22..20] RMAC1 Status Interrupt Core Mapping */ + uint32_t : 9; + } TPEMIMC4_b; + }; + __IM uint32_t RESERVED[27]; + + union + { + __IOM uint32_t TPEMIMC60; /*!< (@ 0x00000080) Error and Monitoring Interrupt Mapping Configuration + * Register 60 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC60_b; + }; + + union + { + __IOM uint32_t TPEMIMC61; /*!< (@ 0x00000084) Error and Monitoring Interrupt Mapping Configuration + * Register 61 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC61_b; + }; + + union + { + __IOM uint32_t TPEMIMC62; /*!< (@ 0x00000088) Error and Monitoring Interrupt Mapping Configuration + * Register 62 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC62_b; + }; + + union + { + __IOM uint32_t TPEMIMC63; /*!< (@ 0x0000008C) Error and Monitoring Interrupt Mapping Configuration + * Register 63 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC63_b; + }; + + union + { + __IOM uint32_t TPEMIMC64; /*!< (@ 0x00000090) Error and Monitoring Interrupt Mapping Configuration + * Register 64 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC64_b; + }; + __IM uint32_t RESERVED1[27]; + + union + { + __IOM uint32_t TPEMIMC70; /*!< (@ 0x00000100) Error and Monitoring Interrupt Mapping Configuration + * Register 70 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC70_b; + }; + + union + { + __IOM uint32_t TPEMIMC71; /*!< (@ 0x00000104) Error and Monitoring Interrupt Mapping Configuration + * Register 71 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC71_b; + }; + + union + { + __IOM uint32_t TPEMIMC72; /*!< (@ 0x00000108) Error and Monitoring Interrupt Mapping Configuration + * Register 72 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC72_b; + }; + + union + { + __IOM uint32_t TPEMIMC73; /*!< (@ 0x0000010C) Error and Monitoring Interrupt Mapping Configuration + * Register 73 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC73_b; + }; + + union + { + __IOM uint32_t TPEMIMC74; /*!< (@ 0x00000110) Error and Monitoring Interrupt Mapping Configuration + * Register 74 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC74_b; + }; + __IM uint32_t RESERVED2[379]; + + union + { + __IM uint32_t TSIM; /*!< (@ 0x00000700) Summarized Interrupt Mirroring Register */ + + struct + { + __IM uint32_t FIM : 1; /*!< [0..0] MFWD Interrupt Mirroring */ + __IM uint32_t CIM : 1; /*!< [1..1] COMA Interrupt Mirroring */ + __IM uint32_t GIM0 : 1; /*!< [2..2] GWCA0 Interrupt Monitoring */ + __IM uint32_t GIM1 : 1; /*!< [3..3] GWCA1 Interrupt Monitoring */ + __IM uint32_t EIM0 : 1; /*!< [4..4] ETHA0 Interrupt Monitoring */ + __IM uint32_t EIM1 : 1; /*!< [5..5] ETHA1 Interrupt Monitoring */ + __IM uint32_t EIM2 : 1; /*!< [6..6] ETHA2 Interrupt Monitoring */ + uint32_t : 25; + } TSIM_b; + }; + + union + { + __IM uint32_t TFIM; /*!< (@ 0x00000704) MFWD Interrupt Mirroring Register */ + + struct + { + __IM uint32_t FWEISIM0 : 1; /*!< [0..0] FWEIS0 Interrupt Mirroring */ + __IM uint32_t FWEISIM1 : 1; /*!< [1..1] FWEIS1 Interrupt Mirroring */ + __IM uint32_t FWEISIM2 : 1; /*!< [2..2] FWEIS2 Interrupt Mirroring */ + __IM uint32_t FWEISIM3 : 1; /*!< [3..3] FWEIS3 Interrupt Mirroring */ + __IM uint32_t FWEISIM4 : 1; /*!< [4..4] FWEIS4 Interrupt Mirroring */ + __IM uint32_t FWEISIM5 : 1; /*!< [5..5] FWEIS5 Interrupt Mirroring */ + __IM uint32_t FWEISIM6 : 1; /*!< [6..6] FWEIS6 Interrupt Mirroring */ + __IM uint32_t FWEISIM7 : 1; /*!< [7..7] FWEIS7 Interrupt Mirroring */ + __IM uint32_t FWEISIM8 : 1; /*!< [8..8] FWEIS8 Interrupt Mirroring */ + __IM uint32_t FWMISIM0 : 1; /*!< [9..9] FWMIS0 Interrupt Mirroring */ + uint32_t : 22; + } TFIM_b; + }; + + union + { + __IM uint32_t TCIM; /*!< (@ 0x00000708) COMA Interrupt Mirroring Register */ + + struct + { + __IM uint32_t RSSISIM : 1; /*!< [0..0] RSSIS Interrupt Mirroring */ + __IM uint32_t CAEISIM0 : 1; /*!< [1..1] CAEIS0 Interrupt Mirroring */ + __IM uint32_t CAEISIM1 : 1; /*!< [2..2] CAEIS1 Interrupt Mirroring */ + __IM uint32_t CAMISIM0 : 1; /*!< [3..3] CAMIS0 Interrupt Mirroring */ + __IM uint32_t CAMISIM1 : 1; /*!< [4..4] CAMIS1 Interrupt Mirroring */ + uint32_t : 27; + } TCIM_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t TGIM0; /*!< (@ 0x00000710) GWCA0 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t GWDISIM : 1; /*!< [0..0] GWDIS Interrupt Mirroring */ + __IM uint32_t GWTSDISIM : 1; /*!< [1..1] GWTSDIS Interrupt Mirroring */ + __IM uint32_t GWEISIM0 : 1; /*!< [2..2] GWEIS0 Interrupt Mirroring */ + __IM uint32_t GWEISIM1 : 1; /*!< [3..3] GWEIS1 Interrupt Mirroring */ + __IM uint32_t GWEISIM2 : 1; /*!< [4..4] GWEIS2 Interrupt Mirroring */ + __IM uint32_t GWEISIM3 : 1; /*!< [5..5] GWEIS3 Interrupt Mirroring */ + __IM uint32_t GWEISIM4 : 1; /*!< [6..6] GWEIS4 Interrupt Mirroring */ + __IM uint32_t GWEISIM5 : 1; /*!< [7..7] GWEIS5 Interrupt Mirroring */ + uint32_t : 24; + } TGIM0_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IM uint32_t TEIM0; /*!< (@ 0x00000720) ETHA0 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t EAEISIM0 : 1; /*!< [0..0] EAEIS0 Interrupt Mirroring */ + __IM uint32_t EAEISIM1 : 1; /*!< [1..1] EAEIS1 Interrupt Mirroring */ + __IM uint32_t EAEISIM2 : 1; /*!< [2..2] EAEIS2 Interrupt Mirroring */ + __IM uint32_t MEISIM : 1; /*!< [3..3] MEIS Interrupt Mirroring */ + __IM uint32_t MMISIM : 1; /*!< [4..4] MMIS0 Interrupt Mirroring */ + uint32_t : 27; + } TEIM0_b; + }; + + union + { + __IM uint32_t TEIM1; /*!< (@ 0x00000724) ETHA1 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t EAEISIM0 : 1; /*!< [0..0] EAEIS0 Interrupt Mirroring */ + __IM uint32_t EAEISIM1 : 1; /*!< [1..1] EAEIS1 Interrupt Mirroring */ + __IM uint32_t EAEISIM2 : 1; /*!< [2..2] EAEIS2 Interrupt Mirroring */ + __IM uint32_t MEISIM : 1; /*!< [3..3] MEIS Interrupt Mirroring */ + __IM uint32_t MMISIM : 1; /*!< [4..4] MMIS0 Interrupt Mirroring */ + uint32_t : 27; + } TEIM1_b; + }; + __IM uint32_t RESERVED5[25398]; + + union + { + __IOM uint32_t MIIRR; /*!< (@ 0x00019400) Media Interface Reset Register */ + + struct + { + __IOM uint32_t RGRST0 : 1; /*!< [0..0] RGMII0 Interface Reset */ + __IOM uint32_t RGRST1 : 1; /*!< [1..1] RGMII1 Interface Reset */ + uint32_t : 6; + __IOM uint32_t RMRST0 : 1; /*!< [8..8] RMII0 Interface Reset */ + __IOM uint32_t RMRST1 : 1; /*!< [9..9] RMII1 Interface Reset */ + uint32_t : 22; + } MIIRR_b; + }; + + union + { + __IOM uint32_t MIICR0; /*!< (@ 0x00019404) Media Interface Control Register 0 */ + + struct + { + __IOM uint32_t MIISEL : 2; /*!< [1..0] MII Select */ + uint32_t : 6; + __IOM uint32_t DIVSTP : 1; /*!< [8..8] Clock Divider Stop */ + uint32_t : 3; + __IOM uint32_t TXCIDE : 1; /*!< [12..12] TXC Internal Delay Enable in RGMII */ + uint32_t : 19; + } MIICR0_b; + }; + + union + { + __IOM uint32_t MIICR1; /*!< (@ 0x00019408) Media Interface Control Register 1 */ + + struct + { + __IOM uint32_t MIISEL : 2; /*!< [1..0] MII Select */ + uint32_t : 6; + __IOM uint32_t DIVSTP : 1; /*!< [8..8] Clock Divider Stop */ + uint32_t : 3; + __IOM uint32_t TXCIDE : 1; /*!< [12..12] TXC Internal Delay Enable in RGMII */ + uint32_t : 19; + } MIICR1_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t MCCESR; /*!< (@ 0x00019410) Media Clock Capture Event Select Register */ + + struct + { + __IOM uint32_t MCCES0 : 1; /*!< [0..0] Media Clock Capture Event Select 0 */ + __IOM uint32_t MCCES1 : 1; /*!< [1..1] Media Clock Capture Event Select 1 */ + uint32_t : 30; + } MCCESR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t TASSTSR; /*!< (@ 0x00019420) TAS Status Monitor Signal Select Register */ + + struct + { + __IOM uint32_t MSS0 : 5; /*!< [4..0] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state[8 + * 0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS1 : 5; /*!< [12..8] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state[ + * :0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS2 : 5; /*!< [20..16] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state + * 8:0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS3 : 5; /*!< [28..24] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state + * 8:0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + } TASSTSR_b; + }; +} R_ESWM_Type; /*!< Size = 103460 (0x19424) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Agent (R_ETHA0) + */ + +typedef struct /*!< (@ 0x403CA000) R_ETHA0 Structure */ +{ + union + { + __IOM uint32_t EAMC; /*!< (@ 0x00000000) Ethernet Agent Mode Configuration Register (EAMC) */ + + struct + { + __IOM uint32_t OPC : 2; /*!< [1..0] OPC */ + uint32_t : 30; + } EAMC_b; + }; + + union + { + __IOM uint32_t EAMS; /*!< (@ 0x00000004) Ethernet Agent Mode Status Register (EAMS) */ + + struct + { + __IOM uint32_t OPS : 2; /*!< [1..0] OPS */ + uint32_t : 30; + } EAMS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t EAIRC; /*!< (@ 0x00000010) Ethernet Agent IPV Remapping Configuration Register + * [802.1Q] (EAIRC) */ + + struct + { + __IOM uint32_t IPVR0 : 3; /*!< [2..0] IPVR0 */ + uint32_t : 1; + __IOM uint32_t IPVR1 : 3; /*!< [6..4] IPVR1 */ + uint32_t : 1; + __IOM uint32_t IPVR2 : 3; /*!< [10..8] IPVR2 */ + uint32_t : 1; + __IOM uint32_t IPVR3 : 3; /*!< [14..12] IPVR3 */ + uint32_t : 1; + __IOM uint32_t IPVR4 : 3; /*!< [18..16] IPVR4 */ + uint32_t : 1; + __IOM uint32_t IPVR5 : 3; /*!< [22..20] IPVR5 */ + uint32_t : 1; + __IOM uint32_t IPVR6 : 3; /*!< [26..24] IPVR6 */ + uint32_t : 1; + __IOM uint32_t IPVR7 : 3; /*!< [30..28] IPVR7 */ + uint32_t : 1; + } EAIRC_b; + }; + + union + { + __IOM uint32_t EATDQSC; /*!< (@ 0x00000014) Ethernet Agent TX Descriptor Queue Security Configuration + * Register (EATDQSC) */ + + struct + { + __IOM uint32_t TDQSL0 : 1; /*!< [0..0] TDQSL0 */ + __IOM uint32_t TDQSL1 : 1; /*!< [1..1] TDQSL1 */ + __IOM uint32_t TDQSL2 : 1; /*!< [2..2] TDQSL2 */ + __IOM uint32_t TDQSL3 : 1; /*!< [3..3] TDQSL3 */ + __IOM uint32_t TDQSL4 : 1; /*!< [4..4] TDQSL4 */ + __IOM uint32_t TDQSL5 : 1; /*!< [5..5] TDQSL5 */ + __IOM uint32_t TDQSL6 : 1; /*!< [6..6] TDQSL6 */ + __IOM uint32_t TDQSL7 : 1; /*!< [7..7] TDQSL7 */ + uint32_t : 24; + } EATDQSC_b; + }; + + union + { + __IOM uint32_t EATDQC; /*!< (@ 0x00000018) Ethernet Agent TX Descriptor Queue Configuration + * Register (EATDQC) */ + + struct + { + __IOM uint32_t TDQD0 : 1; /*!< [0..0] TDQD0 */ + __IOM uint32_t TDQD1 : 1; /*!< [1..1] TDQD1 */ + __IOM uint32_t TDQD2 : 1; /*!< [2..2] TDQD2 */ + __IOM uint32_t TDQD3 : 1; /*!< [3..3] TDQD3 */ + __IOM uint32_t TDQD4 : 1; /*!< [4..4] TDQD4 */ + __IOM uint32_t TDQD5 : 1; /*!< [5..5] TDQD5 */ + __IOM uint32_t TDQD6 : 1; /*!< [6..6] TDQD6 */ + __IOM uint32_t TDQD7 : 1; /*!< [7..7] TDQD7 */ + __IOM uint32_t TCTDQD : 1; /*!< [8..8] TCTDQD */ + uint32_t : 7; + __IOM uint32_t TDQP0 : 1; /*!< [16..16] TDQP0 */ + __IOM uint32_t TDQP1 : 1; /*!< [17..17] TDQP1 */ + __IOM uint32_t TDQP2 : 1; /*!< [18..18] TDQP2 */ + __IOM uint32_t TDQP3 : 1; /*!< [19..19] TDQP3 */ + __IOM uint32_t TDQP4 : 1; /*!< [20..20] TDQP4 */ + __IOM uint32_t TDQP5 : 1; /*!< [21..21] TDQP5 */ + __IOM uint32_t TDQP6 : 1; /*!< [22..22] TDQP6 */ + __IOM uint32_t TDQP7 : 1; /*!< [23..23] TDQP7 */ + uint32_t : 8; + } EATDQC_b; + }; + + union + { + __IOM uint32_t EATDQAC; /*!< (@ 0x0000001C) Ethernet Agent TX Descriptor Queue Arbitration + * Configuration Register (EATDQAC) */ + + struct + { + __IOM uint32_t TDQA0 : 4; /*!< [3..0] TDQA0 */ + __IOM uint32_t TDQA1 : 4; /*!< [7..4] TDQA1 */ + __IOM uint32_t TDQA2 : 4; /*!< [11..8] TDQA2 */ + __IOM uint32_t TDQA3 : 4; /*!< [15..12] TDQA3 */ + __IOM uint32_t TDQA4 : 4; /*!< [19..16] TDQA4 */ + __IOM uint32_t TDQA5 : 4; /*!< [23..20] TDQA5 */ + __IOM uint32_t TDQA6 : 4; /*!< [27..24] TDQA6 */ + __IOM uint32_t TDQA7 : 4; /*!< [31..28] TDQA7 */ + } EATDQAC_b; + }; + + union + { + __IOM uint32_t EATPEC; /*!< (@ 0x00000020) Ethernet Agent TX Pre-Emption Configuration Register + * (EATPEC) */ + + struct + { + __IOM uint32_t TTQ0 : 1; /*!< [0..0] TTQ0 */ + __IOM uint32_t TTQ1 : 1; /*!< [1..1] TTQ1 */ + __IOM uint32_t TTQ2 : 1; /*!< [2..2] TTQ2 */ + __IOM uint32_t TTQ3 : 1; /*!< [3..3] TTQ3 */ + __IOM uint32_t TTQ4 : 1; /*!< [4..4] TTQ4 */ + __IOM uint32_t TTQ5 : 1; /*!< [5..5] TTQ5 */ + __IOM uint32_t TTQ6 : 1; /*!< [6..6] TTQ6 */ + __IOM uint32_t TTQ7 : 1; /*!< [7..7] TTQ7 */ + __IOM uint32_t TTQ8 : 1; /*!< [8..8] TTQ8 */ + __IOM uint32_t TTQ9 : 1; /*!< [9..9] TTQ9 */ + uint32_t : 6; + __IOM uint32_t AFS : 2; /*!< [17..16] AFS */ + uint32_t : 14; + } EATPEC_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t EATMFSC0; /*!< (@ 0x00000040) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC0_b; + }; + + union + { + __IOM uint32_t EATMFSC1; /*!< (@ 0x00000044) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC1_b; + }; + + union + { + __IOM uint32_t EATMFSC2; /*!< (@ 0x00000048) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC2_b; + }; + + union + { + __IOM uint32_t EATMFSC3; /*!< (@ 0x0000004C) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC3_b; + }; + + union + { + __IOM uint32_t EATMFSC4; /*!< (@ 0x00000050) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC4_b; + }; + + union + { + __IOM uint32_t EATMFSC5; /*!< (@ 0x00000054) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC5_b; + }; + + union + { + __IOM uint32_t EATMFSC6; /*!< (@ 0x00000058) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC6_b; + }; + + union + { + __IOM uint32_t EATMFSC7; /*!< (@ 0x0000005C) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC7_b; + }; + + union + { + __IOM uint32_t EATDQDC0; /*!< (@ 0x00000060) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC0_b; + }; + + union + { + __IOM uint32_t EATDQDC1; /*!< (@ 0x00000064) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC1_b; + }; + + union + { + __IOM uint32_t EATDQDC2; /*!< (@ 0x00000068) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC2_b; + }; + + union + { + __IOM uint32_t EATDQDC3; /*!< (@ 0x0000006C) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC3_b; + }; + + union + { + __IOM uint32_t EATDQDC4; /*!< (@ 0x00000070) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC4_b; + }; + + union + { + __IOM uint32_t EATDQDC5; /*!< (@ 0x00000074) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC5_b; + }; + + union + { + __IOM uint32_t EATDQDC6; /*!< (@ 0x00000078) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC6_b; + }; + + union + { + __IOM uint32_t EATDQDC7; /*!< (@ 0x0000007C) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC7_b; + }; + + union + { + __IOM uint32_t EATDQM0; /*!< (@ 0x00000080) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM0_b; + }; + + union + { + __IOM uint32_t EATDQM1; /*!< (@ 0x00000084) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM1_b; + }; + + union + { + __IOM uint32_t EATDQM2; /*!< (@ 0x00000088) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM2_b; + }; + + union + { + __IOM uint32_t EATDQM3; /*!< (@ 0x0000008C) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM3_b; + }; + + union + { + __IOM uint32_t EATDQM4; /*!< (@ 0x00000090) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM4_b; + }; + + union + { + __IOM uint32_t EATDQM5; /*!< (@ 0x00000094) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM5_b; + }; + + union + { + __IOM uint32_t EATDQM6; /*!< (@ 0x00000098) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM6_b; + }; + + union + { + __IOM uint32_t EATDQM7; /*!< (@ 0x0000009C) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM7_b; + }; + + union + { + __IOM uint32_t EATDQMLM0; /*!< (@ 0x000000A0) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM0_b; + }; + + union + { + __IOM uint32_t EATDQMLM1; /*!< (@ 0x000000A4) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM1_b; + }; + + union + { + __IOM uint32_t EATDQMLM2; /*!< (@ 0x000000A8) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM2_b; + }; + + union + { + __IOM uint32_t EATDQMLM3; /*!< (@ 0x000000AC) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM3_b; + }; + + union + { + __IOM uint32_t EATDQMLM4; /*!< (@ 0x000000B0) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM4_b; + }; + + union + { + __IOM uint32_t EATDQMLM5; /*!< (@ 0x000000B4) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM5_b; + }; + + union + { + __IOM uint32_t EATDQMLM6; /*!< (@ 0x000000B8) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM6_b; + }; + + union + { + __IOM uint32_t EATDQMLM7; /*!< (@ 0x000000BC) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM7_b; + }; + __IM uint32_t RESERVED2[16]; + + union + { + __IOM uint32_t EACTQC; /*!< (@ 0x00000100) Ethernet Agent Cut-Through Queue Configuration + * Register (EACTQC) */ + + struct + { + __IOM uint32_t CTQD : 16; /*!< [15..0] CTQD */ + uint32_t : 16; + } EACTQC_b; + }; + + union + { + __IOM uint32_t EACTDQDC; /*!< (@ 0x00000104) Ethernet Agent Cut-Through Descriptor Queue Depth + * Configuration Register (EACTDQDC) */ + + struct + { + __IOM uint32_t CTDQD : 4; /*!< [3..0] CTDQD */ + uint32_t : 28; + } EACTDQDC_b; + }; + + union + { + __IOM uint32_t EACTDQM; /*!< (@ 0x00000108) Ethernet Agent Cut-Through Descriptor Queue Monitoring + * Register (EACTDQM) */ + + struct + { + __IOM uint32_t CTQDN : 10; /*!< [9..0] CTQDN */ + uint32_t : 22; + } EACTDQM_b; + }; + + union + { + __IOM uint32_t EACTDQMLM; /*!< (@ 0x0000010C) Ethernet Agent Cut-Through Descriptor Queue Max + * Level Monitoring Register (EACTDQMLM) */ + + struct + { + __IOM uint32_t CTDMLQ : 4; /*!< [3..0] CTDMLQ */ + uint32_t : 28; + } EACTDQMLM_b; + }; + __IM uint32_t RESERVED3[8]; + + union + { + __IOM uint32_t EAVCC; /*!< (@ 0x00000130) Ethernet Agent VLAN Control Configuration Register + * (EAVCC) */ + + struct + { + __IOM uint32_t VIM : 1; /*!< [0..0] VIM */ + uint32_t : 15; + __IOM uint32_t VEM : 3; /*!< [18..16] VEM */ + uint32_t : 13; + } EAVCC_b; + }; + + union + { + __IOM uint32_t EAVTC; /*!< (@ 0x00000134) Ethernet Agent VLAN TAG Configuration Register + * (EAVTC) */ + + struct + { + __IOM uint32_t CTV : 12; /*!< [11..0] CTV */ + __IOM uint32_t CTP : 3; /*!< [14..12] CTP */ + __IOM uint32_t CTD : 1; /*!< [15..15] CTD */ + __IOM uint32_t STV : 12; /*!< [27..16] STV */ + __IOM uint32_t STP : 3; /*!< [30..28] STP */ + __IOM uint32_t STD : 1; /*!< [31..31] STD */ + } EAVTC_b; + }; + + union + { + __IOM uint32_t EARTFC; /*!< (@ 0x00000138) Ethernet Agent Reception TAG Filtering Configuration + * Register (EARTFC) */ + + struct + { + __IOM uint32_t NT : 1; /*!< [0..0] NT */ + __IOM uint32_t RT : 1; /*!< [1..1] RT */ + __IOM uint32_t CST : 1; /*!< [2..2] CST */ + __IOM uint32_t CSRT : 1; /*!< [3..3] CSRT */ + __IOM uint32_t CT : 1; /*!< [4..4] CT */ + __IOM uint32_t CRT : 1; /*!< [5..5] CRT */ + __IOM uint32_t SCT : 1; /*!< [6..6] SCT */ + __IOM uint32_t SCRT : 1; /*!< [7..7] SCRT */ + __IOM uint32_t UT : 1; /*!< [8..8] UT */ + uint32_t : 23; + } EARTFC_b; + }; + __IM uint32_t RESERVED4[49]; + + union + { + __IOM uint32_t EACAEC; /*!< (@ 0x00000200) Ethernet Agent CBS Admin Enable Configuration + * Register (EACAEC) */ + + struct + { + __IOM uint32_t CE0 : 1; /*!< [0..0] CE0 */ + __IOM uint32_t CE1 : 1; /*!< [1..1] CE1 */ + __IOM uint32_t CE2 : 1; /*!< [2..2] CE2 */ + __IOM uint32_t CE3 : 1; /*!< [3..3] CE3 */ + __IOM uint32_t CE4 : 1; /*!< [4..4] CE4 */ + __IOM uint32_t CE5 : 1; /*!< [5..5] CE5 */ + __IOM uint32_t CE6 : 1; /*!< [6..6] CE6 */ + __IOM uint32_t CE7 : 1; /*!< [7..7] CE7 */ + uint32_t : 24; + } EACAEC_b; + }; + + union + { + __IOM uint32_t EACC; /*!< (@ 0x00000204) Ethernet Agent CBS Configuration Register (EACC) */ + + struct + { + __IOM uint32_t CC0 : 1; /*!< [0..0] CC0 */ + __IOM uint32_t CC1 : 1; /*!< [1..1] CC1 */ + __IOM uint32_t CC2 : 1; /*!< [2..2] CC2 */ + __IOM uint32_t CC3 : 1; /*!< [3..3] CC3 */ + __IOM uint32_t CC4 : 1; /*!< [4..4] CC4 */ + __IOM uint32_t CC5 : 1; /*!< [5..5] CC5 */ + __IOM uint32_t CC6 : 1; /*!< [6..6] CC6 */ + __IOM uint32_t CC7 : 1; /*!< [7..7] CC7 */ + uint32_t : 24; + } EACC_b; + }; + __IM uint32_t RESERVED5[6]; + + union + { + __IOM uint32_t EACAIVC0; /*!< (@ 0x00000220) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC0_b; + }; + + union + { + __IOM uint32_t EACAIVC1; /*!< (@ 0x00000224) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC1_b; + }; + + union + { + __IOM uint32_t EACAIVC2; /*!< (@ 0x00000228) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC2_b; + }; + + union + { + __IOM uint32_t EACAIVC3; /*!< (@ 0x0000022C) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC3_b; + }; + + union + { + __IOM uint32_t EACAIVC4; /*!< (@ 0x00000230) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC4_b; + }; + + union + { + __IOM uint32_t EACAIVC5; /*!< (@ 0x00000234) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC5_b; + }; + + union + { + __IOM uint32_t EACAIVC6; /*!< (@ 0x00000238) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC6_b; + }; + + union + { + __IOM uint32_t EACAIVC7; /*!< (@ 0x0000023C) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC7_b; + }; + + union + { + __IOM uint32_t EACAULC0; /*!< (@ 0x00000240) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC0_b; + }; + + union + { + __IOM uint32_t EACAULC1; /*!< (@ 0x00000244) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC1_b; + }; + + union + { + __IOM uint32_t EACAULC2; /*!< (@ 0x00000248) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC2_b; + }; + + union + { + __IOM uint32_t EACAULC3; /*!< (@ 0x0000024C) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC3_b; + }; + + union + { + __IOM uint32_t EACAULC4; /*!< (@ 0x00000250) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC4_b; + }; + + union + { + __IOM uint32_t EACAULC5; /*!< (@ 0x00000254) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC5_b; + }; + + union + { + __IOM uint32_t EACAULC6; /*!< (@ 0x00000258) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC6_b; + }; + + union + { + __IOM uint32_t EACAULC7; /*!< (@ 0x0000025C) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC7_b; + }; + + union + { + __IOM uint32_t EACOEM; /*!< (@ 0x00000260) Ethernet Agent CBS Oper Enable Monitoring Register + * (EACOEM) */ + + struct + { + __IOM uint32_t CE0 : 1; /*!< [0..0] CE0 */ + __IOM uint32_t CE1 : 1; /*!< [1..1] CE1 */ + __IOM uint32_t CE2 : 1; /*!< [2..2] CE2 */ + __IOM uint32_t CE3 : 1; /*!< [3..3] CE3 */ + __IOM uint32_t CE4 : 1; /*!< [4..4] CE4 */ + __IOM uint32_t CE5 : 1; /*!< [5..5] CE5 */ + __IOM uint32_t CE6 : 1; /*!< [6..6] CE6 */ + __IOM uint32_t CE7 : 1; /*!< [7..7] CE7 */ + uint32_t : 24; + } EACOEM_b; + }; + __IM uint32_t RESERVED6[7]; + + union + { + __IOM uint32_t EACOIVM0; /*!< (@ 0x00000280) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM0_b; + }; + + union + { + __IOM uint32_t EACOIVM1; /*!< (@ 0x00000284) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM1_b; + }; + + union + { + __IOM uint32_t EACOIVM2; /*!< (@ 0x00000288) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM2_b; + }; + + union + { + __IOM uint32_t EACOIVM3; /*!< (@ 0x0000028C) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM3_b; + }; + + union + { + __IOM uint32_t EACOIVM4; /*!< (@ 0x00000290) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM4_b; + }; + + union + { + __IOM uint32_t EACOIVM5; /*!< (@ 0x00000294) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM5_b; + }; + + union + { + __IOM uint32_t EACOIVM6; /*!< (@ 0x00000298) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM6_b; + }; + + union + { + __IOM uint32_t EACOIVM7; /*!< (@ 0x0000029C) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM7_b; + }; + + union + { + __IOM uint32_t EACOULM0; /*!< (@ 0x000002A0) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM0_b; + }; + + union + { + __IOM uint32_t EACOULM1; /*!< (@ 0x000002A4) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM1_b; + }; + + union + { + __IOM uint32_t EACOULM2; /*!< (@ 0x000002A8) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM2_b; + }; + + union + { + __IOM uint32_t EACOULM3; /*!< (@ 0x000002AC) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM3_b; + }; + + union + { + __IOM uint32_t EACOULM4; /*!< (@ 0x000002B0) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM4_b; + }; + + union + { + __IOM uint32_t EACOULM5; /*!< (@ 0x000002B4) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM5_b; + }; + + union + { + __IOM uint32_t EACOULM6; /*!< (@ 0x000002B8) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM6_b; + }; + + union + { + __IOM uint32_t EACOULM7; /*!< (@ 0x000002BC) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM7_b; + }; + + union + { + __IOM uint32_t EACGSM; /*!< (@ 0x000002C0) Ethernet Agent CBS Gate State Monitoring Register + * (EACGSM) */ + + struct + { + __IOM uint32_t CGS0 : 1; /*!< [0..0] CGS0 */ + __IOM uint32_t CGS1 : 1; /*!< [1..1] CGS1 */ + __IOM uint32_t CGS2 : 1; /*!< [2..2] CGS2 */ + __IOM uint32_t CGS3 : 1; /*!< [3..3] CGS3 */ + __IOM uint32_t CGS4 : 1; /*!< [4..4] CGS4 */ + __IOM uint32_t CGS5 : 1; /*!< [5..5] CGS5 */ + __IOM uint32_t CGS6 : 1; /*!< [6..6] CGS6 */ + __IOM uint32_t CGS7 : 1; /*!< [7..7] CGS7 */ + uint32_t : 24; + } EACGSM_b; + }; + __IM uint32_t RESERVED7[15]; + + union + { + __IOM uint32_t EATASC; /*!< (@ 0x00000300) Ethernet Agent TAS Configuration Register (EATASC) */ + + struct + { + __IOM uint32_t TASE : 1; /*!< [0..0] TASE */ + __IOM uint32_t TASCC : 1; /*!< [1..1] TASCC */ + __IOM uint32_t TASCI : 1; /*!< [2..2] TASCI */ + uint32_t : 5; + __IOM uint32_t TASTS : 1; /*!< [8..8] TASTS */ + uint32_t : 7; + __IOM uint32_t TASCA : 8; /*!< [23..16] TASCA */ + uint32_t : 8; + } EATASC_b; + }; + + union + { + __IOM uint32_t EATASIGSC; /*!< (@ 0x00000304) Ethernet Agent TAS Initial Gate State Configuration + * Register (EATASIGSC) */ + + struct + { + __IOM uint32_t TASIGS0 : 1; /*!< [0..0] TASIGS0 */ + __IOM uint32_t TASIGS1 : 1; /*!< [1..1] TASIGS1 */ + __IOM uint32_t TASIGS2 : 1; /*!< [2..2] TASIGS2 */ + __IOM uint32_t TASIGS3 : 1; /*!< [3..3] TASIGS3 */ + __IOM uint32_t TASIGS4 : 1; /*!< [4..4] TASIGS4 */ + __IOM uint32_t TASIGS5 : 1; /*!< [5..5] TASIGS5 */ + __IOM uint32_t TASIGS6 : 1; /*!< [6..6] TASIGS6 */ + __IOM uint32_t TASIGS7 : 1; /*!< [7..7] TASIGS7 */ + __IOM uint32_t TASCTIGS : 1; /*!< [8..8] TASCTIGS */ + uint32_t : 23; + } EATASIGSC_b; + }; + __IM uint32_t RESERVED8[6]; + + union + { + __IOM uint32_t EATASENC0; /*!< (@ 0x00000320) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC0_b; + }; + + union + { + __IOM uint32_t EATASENC1; /*!< (@ 0x00000324) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC1_b; + }; + + union + { + __IOM uint32_t EATASENC2; /*!< (@ 0x00000328) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC2_b; + }; + + union + { + __IOM uint32_t EATASENC3; /*!< (@ 0x0000032C) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC3_b; + }; + + union + { + __IOM uint32_t EATASENC4; /*!< (@ 0x00000330) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC4_b; + }; + + union + { + __IOM uint32_t EATASENC5; /*!< (@ 0x00000334) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC5_b; + }; + + union + { + __IOM uint32_t EATASENC6; /*!< (@ 0x00000338) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC6_b; + }; + + union + { + __IOM uint32_t EATASENC7; /*!< (@ 0x0000033C) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC7_b; + }; + + union + { + __IOM uint32_t EATASCTENC; /*!< (@ 0x00000340) Ethernet Agent TAS Cut-Through Entry Number Configuration + * Register (EATASCTENC) */ + + struct + { + __IOM uint32_t TASCTAEN : 9; /*!< [8..0] TASCTAEN */ + uint32_t : 23; + } EATASCTENC_b; + }; + __IM uint32_t RESERVED9[7]; + + union + { + __IOM uint32_t EATASENM0; /*!< (@ 0x00000360) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM0_b; + }; + + union + { + __IOM uint32_t EATASENM1; /*!< (@ 0x00000364) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM1_b; + }; + + union + { + __IOM uint32_t EATASENM2; /*!< (@ 0x00000368) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM2_b; + }; + + union + { + __IOM uint32_t EATASENM3; /*!< (@ 0x0000036C) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM3_b; + }; + + union + { + __IOM uint32_t EATASENM4; /*!< (@ 0x00000370) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM4_b; + }; + + union + { + __IOM uint32_t EATASENM5; /*!< (@ 0x00000374) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM5_b; + }; + + union + { + __IOM uint32_t EATASENM6; /*!< (@ 0x00000378) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM6_b; + }; + + union + { + __IOM uint32_t EATASENM7; /*!< (@ 0x0000037C) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM7_b; + }; + + union + { + __IOM uint32_t EATASCTENM; /*!< (@ 0x00000380) Ethernet Agent TAS Cut-Through Entry Number Monitoring + * Register (EATASCTENM) */ + + struct + { + __IOM uint32_t TASCTOEN : 9; /*!< [8..0] TASCTOEN */ + uint32_t : 23; + } EATASCTENM_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t EATASCSTC0; /*!< (@ 0x000003A0) Ethernet Agent TAS Cycle Start Time Configuration + * Register 0 (EATASCSTC0) */ + + struct + { + __IOM uint32_t TASACSTP0 : 32; /*!< [31..0] TASACSTP0 */ + } EATASCSTC0_b; + }; + + union + { + __IOM uint32_t EATASCSTC1; /*!< (@ 0x000003A4) Ethernet Agent TAS Cycle Start Time Configuration + * Register 1 (EATASCSTC1) */ + + struct + { + __IOM uint32_t TASACSTP1 : 32; /*!< [31..0] TASACSTP1 */ + } EATASCSTC1_b; + }; + + union + { + __IOM uint32_t EATASCSTM0; /*!< (@ 0x000003A8) Ethernet Agent TAS Cycle Start Time Monitoring + * Register 0 (EATASCSTM0) */ + + struct + { + __IOM uint32_t TASOCSTP0 : 32; /*!< [31..0] TASOCSTP0 */ + } EATASCSTM0_b; + }; + + union + { + __IOM uint32_t EATASCSTM1; /*!< (@ 0x000003AC) Ethernet Agent TAS Cycle Start Time Monitoring + * Register 1 (EATASCSTM1) */ + + struct + { + __IOM uint32_t TASOCSTP1 : 32; /*!< [31..0] TASOCSTP1 */ + } EATASCSTM1_b; + }; + + union + { + __IOM uint32_t EATASCTC; /*!< (@ 0x000003B0) Ethernet Agent TAS Cycle Time Configuration Register + * (EATASCTC) */ + + struct + { + __IOM uint32_t TASACT : 32; /*!< [31..0] TASACT */ + } EATASCTC_b; + }; + + union + { + __IOM uint32_t EATASCTM; /*!< (@ 0x000003B4) Ethernet Agent TAS Cycle Time Monitoring Register + * (EATASCTM) */ + + struct + { + __IOM uint32_t TASOCT : 32; /*!< [31..0] TASOCT */ + } EATASCTM_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t EATASGL0; /*!< (@ 0x000003C0) Ethernet Agent TAS Gate Learn Register 0 (EATASGL0) */ + + struct + { + __IOM uint32_t TASGAL : 8; /*!< [7..0] TASGAL */ + uint32_t : 24; + } EATASGL0_b; + }; + + union + { + __IOM uint32_t EATASGL1; /*!< (@ 0x000003C4) Ethernet Agent TAS Gate Learn Register 1 (EATASGL1) */ + + struct + { + __IOM uint32_t TASGTL : 28; /*!< [27..0] TASGTL */ + __IOM uint32_t TASGSL : 1; /*!< [28..28] TASGSL */ + uint32_t : 3; + } EATASGL1_b; + }; + + union + { + __IOM uint32_t EATASGLR; /*!< (@ 0x000003C8) Ethernet Agent TAS Gate Learn Result Register + * (EATASGLR) */ + + struct + { + uint32_t : 31; + __IOM uint32_t GL : 1; /*!< [31..31] GL */ + } EATASGLR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t EATASGR; /*!< (@ 0x000003D0) Ethernet Agent TAS Gate Read Register (EATASGR) */ + + struct + { + __IOM uint32_t TASGAR : 8; /*!< [7..0] TASGAR */ + uint32_t : 24; + } EATASGR_b; + }; + + union + { + __IOM uint32_t EATASGRR; /*!< (@ 0x000003D4) Ethernet Agent TAS Gate Read Result Register + * (EATASGRR) */ + + struct + { + __IOM uint32_t TASGTR : 28; /*!< [27..0] TASGTR */ + __IOM uint32_t TASGSR : 1; /*!< [28..28] TASGSR */ + __IOM uint32_t TASREF : 1; /*!< [29..29] TASREF */ + uint32_t : 1; + __IOM uint32_t GR : 1; /*!< [31..31] GR */ + } EATASGRR_b; + }; + __IM uint32_t RESERVED13[2]; + + union + { + __IOM uint32_t EATASHCC; /*!< (@ 0x000003E0) Ethernet Agent TAS Hardware Calibration Configuration + * Register (EATASHCC) */ + + struct + { + __IOM uint32_t TASJ : 16; /*!< [15..0] TASJ */ + uint32_t : 16; + } EATASHCC_b; + }; + + union + { + __IOM uint32_t EATASRIRM; /*!< (@ 0x000003E4) Ethernet Agent TAS RAM Initialization Register + * Monitoring Register (EATASRIRM) */ + + struct + { + __IOM uint32_t TASRIOG : 1; /*!< [0..0] TASRIOG */ + __IOM uint32_t TASRR : 1; /*!< [1..1] TASRR */ + uint32_t : 30; + } EATASRIRM_b; + }; + + union + { + __IOM uint32_t EATASSM; /*!< (@ 0x000003E8) Ethernet Agent TAS Status Monitoring Register + * (EATASSM) */ + + struct + { + __IOM uint32_t TASGS0 : 1; /*!< [0..0] TASGS0 */ + __IOM uint32_t TASGS1 : 1; /*!< [1..1] TASGS1 */ + __IOM uint32_t TASGS2 : 1; /*!< [2..2] TASGS2 */ + __IOM uint32_t TASGS3 : 1; /*!< [3..3] TASGS3 */ + __IOM uint32_t TASGS4 : 1; /*!< [4..4] TASGS4 */ + __IOM uint32_t TASGS5 : 1; /*!< [5..5] TASGS5 */ + __IOM uint32_t TASGS6 : 1; /*!< [6..6] TASGS6 */ + __IOM uint32_t TASGS7 : 1; /*!< [7..7] TASGS7 */ + __IOM uint32_t TASCTGS : 1; /*!< [8..8] TASCTGS */ + uint32_t : 7; + __IOM uint32_t TASSO : 1; /*!< [16..16] TASSO */ + uint32_t : 15; + } EATASSM_b; + }; + __IM uint32_t RESERVED14[5]; + + union + { + __IOM uint32_t EAUSMFSECN; /*!< (@ 0x00000400) Ethernet Agent Switch Minimum Frame Size Error + * Counter Register (EAUSMFSECN) */ + + struct + { + __IOM uint32_t USMFSEN : 16; /*!< [15..0] USMFSEN */ + uint32_t : 16; + } EAUSMFSECN_b; + }; + + union + { + __IOM uint32_t EATFECN; /*!< (@ 0x00000404) Ethernet Agent TAG Filtering Error Counter Register + * (EATFECN) */ + + struct + { + __IOM uint32_t TFEN : 16; /*!< [15..0] TFEN */ + uint32_t : 16; + } EATFECN_b; + }; + + union + { + __IOM uint32_t EAFSECN; /*!< (@ 0x00000408) Ethernet Agent Frame Size Error Counter Register + * (EAFSECN) */ + + struct + { + __IOM uint32_t FSEN : 16; /*!< [15..0] FSEN */ + uint32_t : 16; + } EAFSECN_b; + }; + + union + { + __IOM uint32_t EADQOECN; /*!< (@ 0x0000040C) Ethernet Agent Descriptor Queue Overflow Error + * Counter Register (EADQOECN) */ + + struct + { + __IOM uint32_t DQOEN : 16; /*!< [15..0] DQOEN */ + uint32_t : 16; + } EADQOECN_b; + }; + + union + { + __IOM uint32_t EADQSECN; /*!< (@ 0x00000410) Ethernet Agent Descriptor Queue Security Error + * Counter Register (EADQSECN) */ + + struct + { + __IOM uint32_t DQSEN : 16; /*!< [15..0] DQSEN */ + uint32_t : 16; + } EADQSECN_b; + }; + __IM uint32_t RESERVED15[59]; + + union + { + __IOM uint32_t EAEIS0; /*!< (@ 0x00000500) Ethernet Agent Error Interrupt Status Register + * 0 (EAEIS0) */ + + struct + { + __IOM uint32_t DECCES : 1; /*!< [0..0] DECCES */ + __IOM uint32_t TECCES : 1; /*!< [1..1] TECCES */ + __IOM uint32_t PECCES : 1; /*!< [2..2] PECCES */ + __IOM uint32_t DSECCES : 1; /*!< [3..3] DSECCES */ + __IOM uint32_t L23UECCES : 1; /*!< [4..4] L23UECCES */ + __IOM uint32_t USMFSES : 1; /*!< [5..5] USMFSES */ + __IOM uint32_t TFES : 1; /*!< [6..6] TFES */ + uint32_t : 1; + __IOM uint32_t FSES0 : 1; /*!< [8..8] FSES0 */ + __IOM uint32_t FSES1 : 1; /*!< [9..9] FSES1 */ + __IOM uint32_t FSES2 : 1; /*!< [10..10] FSES2 */ + __IOM uint32_t FSES3 : 1; /*!< [11..11] FSES3 */ + __IOM uint32_t FSES4 : 1; /*!< [12..12] FSES4 */ + __IOM uint32_t FSES5 : 1; /*!< [13..13] FSES5 */ + __IOM uint32_t FSES6 : 1; /*!< [14..14] FSES6 */ + __IOM uint32_t FSES7 : 1; /*!< [15..15] FSES7 */ + __IOM uint32_t TASGEES0 : 1; /*!< [16..16] TASGEES0 */ + __IOM uint32_t TASGEES1 : 1; /*!< [17..17] TASGEES1 */ + __IOM uint32_t TASGEES2 : 1; /*!< [18..18] TASGEES2 */ + __IOM uint32_t TASGEES3 : 1; /*!< [19..19] TASGEES3 */ + __IOM uint32_t TASGEES4 : 1; /*!< [20..20] TASGEES4 */ + __IOM uint32_t TASGEES5 : 1; /*!< [21..21] TASGEES5 */ + __IOM uint32_t TASGEES6 : 1; /*!< [22..22] TASGEES6 */ + __IOM uint32_t TASGEES7 : 1; /*!< [23..23] TASGEES7 */ + __IOM uint32_t TASCTGEES : 1; /*!< [24..24] TASCTGEES */ + uint32_t : 7; + } EAEIS0_b; + }; + + union + { + __IOM uint32_t EAEIE0; /*!< (@ 0x00000504) Ethernet Agent Error Interrupt Enable Register + * 0 (EAEIE0) */ + + struct + { + __IOM uint32_t DECCEE : 1; /*!< [0..0] DECCEE */ + __IOM uint32_t TECCEE : 1; /*!< [1..1] TECCEE */ + __IOM uint32_t PECCEE : 1; /*!< [2..2] PECCEE */ + __IOM uint32_t DSECCEE : 1; /*!< [3..3] DSECCEE */ + __IOM uint32_t L23UECCEE : 1; /*!< [4..4] L23UECCEE */ + __IOM uint32_t USMFSEE : 1; /*!< [5..5] USMFSEE */ + __IOM uint32_t TFEE : 1; /*!< [6..6] TFEE */ + uint32_t : 1; + __IOM uint32_t FSEE0 : 1; /*!< [8..8] FSEE0 */ + __IOM uint32_t FSEE1 : 1; /*!< [9..9] FSEE1 */ + __IOM uint32_t FSEE2 : 1; /*!< [10..10] FSEE2 */ + __IOM uint32_t FSEE3 : 1; /*!< [11..11] FSEE3 */ + __IOM uint32_t FSEE4 : 1; /*!< [12..12] FSEE4 */ + __IOM uint32_t FSEE5 : 1; /*!< [13..13] FSEE5 */ + __IOM uint32_t FSEE6 : 1; /*!< [14..14] FSEE6 */ + __IOM uint32_t FSEE7 : 1; /*!< [15..15] FSEE7 */ + __IOM uint32_t TASGEEE0 : 1; /*!< [16..16] TASGEEE0 */ + __IOM uint32_t TASGEEE1 : 1; /*!< [17..17] TASGEEE1 */ + __IOM uint32_t TASGEEE2 : 1; /*!< [18..18] TASGEEE2 */ + __IOM uint32_t TASGEEE3 : 1; /*!< [19..19] TASGEEE3 */ + __IOM uint32_t TASGEEE4 : 1; /*!< [20..20] TASGEEE4 */ + __IOM uint32_t TASGEEE5 : 1; /*!< [21..21] TASGEEE5 */ + __IOM uint32_t TASGEEE6 : 1; /*!< [22..22] TASGEEE6 */ + __IOM uint32_t TASGEEE7 : 1; /*!< [23..23] TASGEEE7 */ + __IOM uint32_t TASCTGEEE : 1; /*!< [24..24] TASCTGEEE */ + uint32_t : 7; + } EAEIE0_b; + }; + + union + { + __IOM uint32_t EAEID0; /*!< (@ 0x00000508) Ethernet Agent Error Interrupt Disable Register + * 0 (EAEID0) */ + + struct + { + __IOM uint32_t DECCED : 1; /*!< [0..0] DECCED */ + __IOM uint32_t TECCED : 1; /*!< [1..1] TECCED */ + __IOM uint32_t PECCED : 1; /*!< [2..2] PECCED */ + __IOM uint32_t DSECCED : 1; /*!< [3..3] DSECCED */ + __IOM uint32_t L23UECCED : 1; /*!< [4..4] L23UECCED */ + __IOM uint32_t USMFSED : 1; /*!< [5..5] USMFSED */ + __IOM uint32_t TFED : 1; /*!< [6..6] TFED */ + uint32_t : 1; + __IOM uint32_t FSED0 : 1; /*!< [8..8] FSED0 */ + __IOM uint32_t FSED1 : 1; /*!< [9..9] FSED1 */ + __IOM uint32_t FSED2 : 1; /*!< [10..10] FSED2 */ + __IOM uint32_t FSED3 : 1; /*!< [11..11] FSED3 */ + __IOM uint32_t FSED4 : 1; /*!< [12..12] FSED4 */ + __IOM uint32_t FSED5 : 1; /*!< [13..13] FSED5 */ + __IOM uint32_t FSED6 : 1; /*!< [14..14] FSED6 */ + __IOM uint32_t FSED7 : 1; /*!< [15..15] FSED7 */ + __IOM uint32_t TASGEED0 : 1; /*!< [16..16] TASGEED0 */ + __IOM uint32_t TASGEED1 : 1; /*!< [17..17] TASGEED1 */ + __IOM uint32_t TASGEED2 : 1; /*!< [18..18] TASGEED2 */ + __IOM uint32_t TASGEED3 : 1; /*!< [19..19] TASGEED3 */ + __IOM uint32_t TASGEED4 : 1; /*!< [20..20] TASGEED4 */ + __IOM uint32_t TASGEED5 : 1; /*!< [21..21] TASGEED5 */ + __IOM uint32_t TASGEED6 : 1; /*!< [22..22] TASGEED6 */ + __IOM uint32_t TASGEED7 : 1; /*!< [23..23] TASGEED7 */ + __IOM uint32_t TASCTGEED : 1; /*!< [24..24] TASCTGEED */ + uint32_t : 7; + } EAEID0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t EAEIS1; /*!< (@ 0x00000510) Ethernet Agent Error Interrupt Status Register + * 1 (EAEIS1) */ + + struct + { + __IOM uint32_t CULES0 : 1; /*!< [0..0] CULES0 */ + __IOM uint32_t CULES1 : 1; /*!< [1..1] CULES1 */ + __IOM uint32_t CULES2 : 1; /*!< [2..2] CULES2 */ + __IOM uint32_t CULES3 : 1; /*!< [3..3] CULES3 */ + __IOM uint32_t CULES4 : 1; /*!< [4..4] CULES4 */ + __IOM uint32_t CULES5 : 1; /*!< [5..5] CULES5 */ + __IOM uint32_t CULES6 : 1; /*!< [6..6] CULES6 */ + __IOM uint32_t CULES7 : 1; /*!< [7..7] CULES7 */ + uint32_t : 8; + __IOM uint32_t TASGES0 : 1; /*!< [16..16] TASGES0 */ + __IOM uint32_t TASGES1 : 1; /*!< [17..17] TASGES1 */ + __IOM uint32_t TASGES2 : 1; /*!< [18..18] TASGES2 */ + __IOM uint32_t TASGES3 : 1; /*!< [19..19] TASGES3 */ + __IOM uint32_t TASGES4 : 1; /*!< [20..20] TASGES4 */ + __IOM uint32_t TASGES5 : 1; /*!< [21..21] TASGES5 */ + __IOM uint32_t TASGES6 : 1; /*!< [22..22] TASGES6 */ + __IOM uint32_t TASGES7 : 1; /*!< [23..23] TASGES7 */ + __IOM uint32_t TASCTGES : 1; /*!< [24..24] TASCTGES */ + uint32_t : 7; + } EAEIS1_b; + }; + + union + { + __IOM uint32_t EAEIE1; /*!< (@ 0x00000514) Ethernet Agent Error Interrupt Enable Register + * 1 (EAEIE1) */ + + struct + { + __IOM uint32_t CULEE0 : 1; /*!< [0..0] CULEE0 */ + __IOM uint32_t CULEE1 : 1; /*!< [1..1] CULEE1 */ + __IOM uint32_t CULEE2 : 1; /*!< [2..2] CULEE2 */ + __IOM uint32_t CULEE3 : 1; /*!< [3..3] CULEE3 */ + __IOM uint32_t CULEE4 : 1; /*!< [4..4] CULEE4 */ + __IOM uint32_t CULEE5 : 1; /*!< [5..5] CULEE5 */ + __IOM uint32_t CULEE6 : 1; /*!< [6..6] CULEE6 */ + __IOM uint32_t CULEE7 : 1; /*!< [7..7] CULEE7 */ + uint32_t : 8; + __IOM uint32_t TASGEE0 : 1; /*!< [16..16] TASGEE0 */ + __IOM uint32_t TASGEE1 : 1; /*!< [17..17] TASGEE1 */ + __IOM uint32_t TASGEE2 : 1; /*!< [18..18] TASGEE2 */ + __IOM uint32_t TASGEE3 : 1; /*!< [19..19] TASGEE3 */ + __IOM uint32_t TASGEE4 : 1; /*!< [20..20] TASGEE4 */ + __IOM uint32_t TASGEE5 : 1; /*!< [21..21] TASGEE5 */ + __IOM uint32_t TASGEE6 : 1; /*!< [22..22] TASGEE6 */ + __IOM uint32_t TASGEE7 : 1; /*!< [23..23] TASGEE7 */ + __IOM uint32_t TASCTGEE : 1; /*!< [24..24] TASCTGEE */ + uint32_t : 7; + } EAEIE1_b; + }; + + union + { + __IOM uint32_t EAEID1; /*!< (@ 0x00000518) Ethernet Agent Error Interrupt Disable Register + * 1 (EAEID1) */ + + struct + { + __IOM uint32_t CULED0 : 1; /*!< [0..0] CULED0 */ + __IOM uint32_t CULED1 : 1; /*!< [1..1] CULED1 */ + __IOM uint32_t CULED2 : 1; /*!< [2..2] CULED2 */ + __IOM uint32_t CULED3 : 1; /*!< [3..3] CULED3 */ + __IOM uint32_t CULED4 : 1; /*!< [4..4] CULED4 */ + __IOM uint32_t CULED5 : 1; /*!< [5..5] CULED5 */ + __IOM uint32_t CULED6 : 1; /*!< [6..6] CULED6 */ + __IOM uint32_t CULED7 : 1; /*!< [7..7] CULED7 */ + uint32_t : 8; + __IOM uint32_t TASGED0 : 1; /*!< [16..16] TASGED0 */ + __IOM uint32_t TASGED1 : 1; /*!< [17..17] TASGED1 */ + __IOM uint32_t TASGED2 : 1; /*!< [18..18] TASGED2 */ + __IOM uint32_t TASGED3 : 1; /*!< [19..19] TASGED3 */ + __IOM uint32_t TASGED4 : 1; /*!< [20..20] TASGED4 */ + __IOM uint32_t TASGED5 : 1; /*!< [21..21] TASGED5 */ + __IOM uint32_t TASGED6 : 1; /*!< [22..22] TASGED6 */ + __IOM uint32_t TASGED7 : 1; /*!< [23..23] TASGED7 */ + __IOM uint32_t TASCTGED : 1; /*!< [24..24] TASCTGED */ + uint32_t : 7; + } EAEID1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t EAEIS2; /*!< (@ 0x00000520) Ethernet Agent Error Interrupt Status Register + * 2 (EAEIS2) */ + + struct + { + __IOM uint32_t DQOES0 : 1; /*!< [0..0] DQOES0 */ + __IOM uint32_t DQOES1 : 1; /*!< [1..1] DQOES1 */ + __IOM uint32_t DQOES2 : 1; /*!< [2..2] DQOES2 */ + __IOM uint32_t DQOES3 : 1; /*!< [3..3] DQOES3 */ + __IOM uint32_t DQOES4 : 1; /*!< [4..4] DQOES4 */ + __IOM uint32_t DQOES5 : 1; /*!< [5..5] DQOES5 */ + __IOM uint32_t DQOES6 : 1; /*!< [6..6] DQOES6 */ + __IOM uint32_t DQOES7 : 1; /*!< [7..7] DQOES7 */ + __IOM uint32_t CTDQOES : 1; /*!< [8..8] CTDQOES */ + uint32_t : 7; + __IOM uint32_t DQSES0 : 1; /*!< [16..16] DQSES0 */ + __IOM uint32_t DQSES1 : 1; /*!< [17..17] DQSES1 */ + __IOM uint32_t DQSES2 : 1; /*!< [18..18] DQSES2 */ + __IOM uint32_t DQSES3 : 1; /*!< [19..19] DQSES3 */ + __IOM uint32_t DQSES4 : 1; /*!< [20..20] DQSES4 */ + __IOM uint32_t DQSES5 : 1; /*!< [21..21] DQSES5 */ + __IOM uint32_t DQSES6 : 1; /*!< [22..22] DQSES6 */ + __IOM uint32_t DQSES7 : 1; /*!< [23..23] DQSES7 */ + uint32_t : 8; + } EAEIS2_b; + }; + + union + { + __IOM uint32_t EAEIE2; /*!< (@ 0x00000524) Ethernet Agent Error Interrupt Enable Register + * 2 (EAEIE2) */ + + struct + { + __IOM uint32_t DQOEE0 : 1; /*!< [0..0] DQOEE0 */ + __IOM uint32_t DQOEE1 : 1; /*!< [1..1] DQOEE1 */ + __IOM uint32_t DQOEE2 : 1; /*!< [2..2] DQOEE2 */ + __IOM uint32_t DQOEE3 : 1; /*!< [3..3] DQOEE3 */ + __IOM uint32_t DQOEE4 : 1; /*!< [4..4] DQOEE4 */ + __IOM uint32_t DQOEE5 : 1; /*!< [5..5] DQOEE5 */ + __IOM uint32_t DQOEE6 : 1; /*!< [6..6] DQOEE6 */ + __IOM uint32_t DQOEE7 : 1; /*!< [7..7] DQOEE7 */ + __IOM uint32_t CTDQOEE : 1; /*!< [8..8] CTDQOEE */ + uint32_t : 7; + __IOM uint32_t DQSEE0 : 1; /*!< [16..16] DQSEE0 */ + __IOM uint32_t DQSEE1 : 1; /*!< [17..17] DQSEE1 */ + __IOM uint32_t DQSEE2 : 1; /*!< [18..18] DQSEE2 */ + __IOM uint32_t DQSEE3 : 1; /*!< [19..19] DQSEE3 */ + __IOM uint32_t DQSEE4 : 1; /*!< [20..20] DQSEE4 */ + __IOM uint32_t DQSEE5 : 1; /*!< [21..21] DQSEE5 */ + __IOM uint32_t DQSEE6 : 1; /*!< [22..22] DQSEE6 */ + __IOM uint32_t DQSEE7 : 1; /*!< [23..23] DQSEE7 */ + uint32_t : 8; + } EAEIE2_b; + }; + + union + { + __IOM uint32_t EAEID2; /*!< (@ 0x00000528) Ethernet Agent Error Interrupt Disable Register + * 2 (EAEID2) */ + + struct + { + __IOM uint32_t DQOED0 : 1; /*!< [0..0] DQOED0 */ + __IOM uint32_t DQOED1 : 1; /*!< [1..1] DQOED1 */ + __IOM uint32_t DQOED2 : 1; /*!< [2..2] DQOED2 */ + __IOM uint32_t DQOED3 : 1; /*!< [3..3] DQOED3 */ + __IOM uint32_t DQOED4 : 1; /*!< [4..4] DQOED4 */ + __IOM uint32_t DQOED5 : 1; /*!< [5..5] DQOED5 */ + __IOM uint32_t DQOED6 : 1; /*!< [6..6] DQOED6 */ + __IOM uint32_t DQOED7 : 1; /*!< [7..7] DQOED7 */ + __IOM uint32_t CTDQOED : 1; /*!< [8..8] CTDQOED */ + uint32_t : 7; + __IOM uint32_t DQSED0 : 1; /*!< [16..16] DQSED0 */ + __IOM uint32_t DQSED1 : 1; /*!< [17..17] DQSED1 */ + __IOM uint32_t DQSED2 : 1; /*!< [18..18] DQSED2 */ + __IOM uint32_t DQSED3 : 1; /*!< [19..19] DQSED3 */ + __IOM uint32_t DQSED4 : 1; /*!< [20..20] DQSED4 */ + __IOM uint32_t DQSED5 : 1; /*!< [21..21] DQSED5 */ + __IOM uint32_t DQSED6 : 1; /*!< [22..22] DQSED6 */ + __IOM uint32_t DQSED7 : 1; /*!< [23..23] DQSED7 */ + uint32_t : 8; + } EAEID2_b; + }; + __IM uint32_t RESERVED18[21]; + + union + { + __IOM uint32_t EASCR; /*!< (@ 0x00000580) Ethernet Agent Security Configuration Register + * (EASCR) */ + + struct + { + __IOM uint32_t MRSL : 1; /*!< [0..0] MRSL */ + __IOM uint32_t TRSL : 1; /*!< [1..1] TRSL */ + __IOM uint32_t MCRSL : 1; /*!< [2..2] MCRSL */ + __IOM uint32_t TGRSL : 1; /*!< [3..3] TGRSL */ + __IOM uint32_t TASRSL : 1; /*!< [4..4] TASRSL */ + __IOM uint32_t EIRSL : 1; /*!< [5..5] EIRSL */ + __IOM uint32_t CRSL : 1; /*!< [6..6] CRSL */ + uint32_t : 9; + __IOM uint32_t DQRSL0 : 1; /*!< [16..16] DQRSL0 */ + __IOM uint32_t DQRSL1 : 1; /*!< [17..17] DQRSL1 */ + __IOM uint32_t DQRSL2 : 1; /*!< [18..18] DQRSL2 */ + __IOM uint32_t DQRSL3 : 1; /*!< [19..19] DQRSL3 */ + __IOM uint32_t DQRSL4 : 1; /*!< [20..20] DQRSL4 */ + __IOM uint32_t DQRSL5 : 1; /*!< [21..21] DQRSL5 */ + __IOM uint32_t DQRSL6 : 1; /*!< [22..22] DQRSL6 */ + __IOM uint32_t DQRSL7 : 1; /*!< [23..23] DQRSL7 */ + uint32_t : 8; + } EASCR_b; + }; +} R_ETHA0_Type; /*!< Size = 1412 (0x584) */ + +/* =========================================================================================================================== */ +/* ================ R_GPTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Generic PTP Timer (R_GPTP) + */ + +typedef struct /*!< (@ 0x403E0000) R_GPTP Structure */ +{ + union + { + __IM uint32_t PTPIPV; /*!< (@ 0x00000000) IP Version Register */ + + struct + { + __IM uint32_t IPV : 32; /*!< [31..0] IP Version */ + } PTPIPV_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t PTPTMEC; /*!< (@ 0x00000010) Timer Enable Configuration Register */ + + struct + { + __IOM uint32_t TE : 2; /*!< [1..0] Timer Enable */ + uint32_t : 30; + } PTPTMEC_b; + }; + + union + { + __IOM uint32_t PTPTMDC; /*!< (@ 0x00000014) Timer Disable Configuration Register */ + + struct + { + __OM uint32_t TD : 2; /*!< [1..0] Timer Disable */ + uint32_t : 30; + } PTPTMDC_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t PTPTIVC0; /*!< (@ 0x00000020) Timer Increment Value Configuration Register + * 0 */ + + struct + { + __IOM uint32_t TIV : 32; /*!< [31..0] Timer Increment Value */ + } PTPTIVC0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t PTPTOVCL0; /*!< (@ 0x00000030) Timer Offset Value Configuration Register L0 */ + + struct + { + __IOM uint32_t TOVL : 30; /*!< [29..0] Timer Offset Value Lower Part */ + uint32_t : 2; + } PTPTOVCL0_b; + }; + + union + { + __IOM uint32_t PTPTOVCM0; /*!< (@ 0x00000034) Timer Offset Value Configuration Register M0 */ + + struct + { + __IOM uint32_t TOVM : 32; /*!< [31..0] Timer Offset Value Middle Part */ + } PTPTOVCM0_b; + }; + + union + { + __IOM uint32_t PTPTOVCU0; /*!< (@ 0x00000038) Timer Offset Value Configuration Register U0 */ + + struct + { + __IOM uint32_t TOVU : 16; /*!< [15..0] Timer Offset Value Upper Part */ + uint32_t : 16; + } PTPTOVCU0_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t PTPAVTPTML0; /*!< (@ 0x00000040) AVTP Timer Monitoring Register L0 */ + + struct + { + __IM uint32_t AVTPL : 32; /*!< [31..0] AVTP Timer Value Lower Part */ + } PTPAVTPTML0_b; + }; + + union + { + __IM uint32_t PTPAVTPTMU0; /*!< (@ 0x00000044) AVTP Timer Monitoring Register U0 */ + + struct + { + __IM uint32_t AVTPU : 32; /*!< [31..0] AVTP Timer Value Upper Part */ + } PTPAVTPTMU0_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t PTPGPTPTML0; /*!< (@ 0x00000050) GPTP Timer Monitoring Register L0 */ + + struct + { + __IM uint32_t GPTPL : 30; /*!< [29..0] GPTP Timer Value Lower Part */ + uint32_t : 2; + } PTPGPTPTML0_b; + }; + + union + { + __IM uint32_t PTPGPTPTMM0; /*!< (@ 0x00000054) GPTP Timer Monitoring Register M0 */ + + struct + { + __IM uint32_t GPTPM : 32; /*!< [31..0] GPTP Timer Value Middle Part */ + } PTPGPTPTMM0_b; + }; + + union + { + __IM uint32_t PTPGPTPTMU0; /*!< (@ 0x00000058) GPTP Timer Monitoring Register U0 */ + + struct + { + __IM uint32_t GPTPU : 16; /*!< [15..0] GPTP Timer Value Upper Part */ + uint32_t : 16; + } PTPGPTPTMU0_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PTPTIVC1; /*!< (@ 0x00000060) Timer Increment Value Configuration Register + * 1 */ + + struct + { + __IOM uint32_t TIV : 32; /*!< [31..0] Timer Increment Value */ + } PTPTIVC1_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t PTPTOVCL1; /*!< (@ 0x00000070) Timer Offset Value Configuration Register L1 */ + + struct + { + __IOM uint32_t TOVL : 30; /*!< [29..0] Timer Offset Value Lower Part */ + uint32_t : 2; + } PTPTOVCL1_b; + }; + + union + { + __IOM uint32_t PTPTOVCM1; /*!< (@ 0x00000074) Timer Offset Value Configuration Register M1 */ + + struct + { + __IOM uint32_t TOVM : 32; /*!< [31..0] Timer Offset Value Middle Part */ + } PTPTOVCM1_b; + }; + + union + { + __IOM uint32_t PTPTOVCU1; /*!< (@ 0x00000078) Timer Offset Value Configuration Register U1 */ + + struct + { + __IOM uint32_t TOVU : 16; /*!< [15..0] Timer Offset Value Upper Part */ + uint32_t : 16; + } PTPTOVCU1_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t PTPAVTPTML1; /*!< (@ 0x00000080) AVTP Timer Monitoring Register L1 */ + + struct + { + __IM uint32_t AVTPL : 32; /*!< [31..0] AVTP Timer Value Lower Part */ + } PTPAVTPTML1_b; + }; + + union + { + __IM uint32_t PTPAVTPTMU1; /*!< (@ 0x00000084) AVTP Timer Monitoring Register U1 */ + + struct + { + __IM uint32_t AVTPU : 32; /*!< [31..0] AVTP Timer Value Upper Part */ + } PTPAVTPTMU1_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IM uint32_t PTPGPTPTML1; /*!< (@ 0x00000090) GPTP Timer Monitoring Register L1 */ + + struct + { + __IM uint32_t GPTPL : 30; /*!< [29..0] GPTP Timer Value Lower Part */ + uint32_t : 2; + } PTPGPTPTML1_b; + }; + + union + { + __IM uint32_t PTPGPTPTMM1; /*!< (@ 0x00000094) GPTP Timer Monitoring Register M1 */ + + struct + { + __IM uint32_t GPTPM : 32; /*!< [31..0] GPTP Timer Value Middle Part */ + } PTPGPTPTMM1_b; + }; + + union + { + __IM uint32_t PTPGPTPTMU1; /*!< (@ 0x00000098) GPTP Timer Monitoring Register U1 */ + + struct + { + __IM uint32_t GPTPU : 16; /*!< [15..0] GPTP Timer Value Upper Part */ + uint32_t : 16; + } PTPGPTPTMU1_b; + }; + __IM uint32_t RESERVED9[89]; + + union + { + __IOM uint32_t PTPMCCC0; /*!< (@ 0x00000200) Media Clock Capture Configuration Register 0 */ + + struct + { + __IOM uint32_t MCPEE : 1; /*!< [0..0] Media Clock Capture Positive Edge Enable */ + __IOM uint32_t MCNEE : 1; /*!< [1..1] Media Clock Capture Negative Edge Enable */ + __IOM uint32_t MCTTS : 1; /*!< [2..2] Media Clock Capture Timer Type Select */ + __IOM uint32_t MCTNS : 1; /*!< [3..3] Media Clock Capture Timer Number Select */ + uint32_t : 12; + __IOM uint32_t MCCR : 1; /*!< [16..16] Media Clock Capture Request */ + uint32_t : 15; + } PTPMCCC0_b; + }; + + union + { + __IM uint32_t PTPMCCML0; /*!< (@ 0x00000204) Media Clock Capture Monitoring Register L0 */ + + struct + { + __IM uint32_t MCCTVL : 32; /*!< [31..0] Media Clock Captured Timer Value Lower Part */ + } PTPMCCML0_b; + }; + + union + { + __IM uint32_t PTPMCCMM0; /*!< (@ 0x00000208) Media Clock Capture Monitoring Register M0 */ + + struct + { + __IM uint32_t MCCTVM : 32; /*!< [31..0] Media Clock Captured Timer Value Middle Part */ + } PTPMCCMM0_b; + }; + + union + { + __IM uint32_t PTPMCCMU0; /*!< (@ 0x0000020C) Media Clock Capture Monitoring Register U0 */ + + struct + { + __IM uint32_t MCCTVU : 16; /*!< [15..0] Media Clock Captured Timer Value Upper Part */ + __IM uint32_t MCPEC : 1; /*!< [16..16] Media Clock Positive Edge Captured */ + __IM uint32_t MCNEC : 1; /*!< [17..17] Media Clock Negative Edge Captured */ + __IM uint32_t MCSWC : 1; /*!< [18..18] Media Clock SoftWare Captured */ + uint32_t : 5; + __IM uint32_t MCCN : 2; /*!< [25..24] Media Clock Capture Number */ + uint32_t : 6; + } PTPMCCMU0_b; + }; + + union + { + __IOM uint32_t PTPMCCC1; /*!< (@ 0x00000210) Media Clock Capture Configuration Register 1 */ + + struct + { + __IOM uint32_t MCPEE : 1; /*!< [0..0] Media Clock Capture Positive Edge Enable */ + __IOM uint32_t MCNEE : 1; /*!< [1..1] Media Clock Capture Negative Edge Enable */ + __IOM uint32_t MCTTS : 1; /*!< [2..2] Media Clock Capture Timer Type Select */ + __IOM uint32_t MCTNS : 1; /*!< [3..3] Media Clock Capture Timer Number Select */ + uint32_t : 12; + __IOM uint32_t MCCR : 1; /*!< [16..16] Media Clock Capture Request */ + uint32_t : 15; + } PTPMCCC1_b; + }; + + union + { + __IM uint32_t PTPMCCML1; /*!< (@ 0x00000214) Media Clock Capture Monitoring Register L1 */ + + struct + { + __IM uint32_t MCCTVL : 32; /*!< [31..0] Media Clock Captured Timer Value Lower Part */ + } PTPMCCML1_b; + }; + + union + { + __IM uint32_t PTPMCCMM1; /*!< (@ 0x00000218) Media Clock Capture Monitoring Register M1 */ + + struct + { + __IM uint32_t MCCTVM : 32; /*!< [31..0] Media Clock Captured Timer Value Middle Part */ + } PTPMCCMM1_b; + }; + + union + { + __IM uint32_t PTPMCCMU1; /*!< (@ 0x0000021C) Media Clock Capture Monitoring Register U1 */ + + struct + { + __IM uint32_t MCCTVU : 16; /*!< [15..0] Media Clock Captured Timer Value Upper Part */ + __IM uint32_t MCPEC : 1; /*!< [16..16] Media Clock Positive Edge Captured */ + __IM uint32_t MCNEC : 1; /*!< [17..17] Media Clock Negative Edge Captured */ + __IM uint32_t MCSWC : 1; /*!< [18..18] Media Clock SoftWare Captured */ + uint32_t : 5; + __IM uint32_t MCCN : 2; /*!< [25..24] Media Clock Capture Number */ + uint32_t : 6; + } PTPMCCMU1_b; + }; + __IM uint32_t RESERVED10[56]; + + union + { + __IOM uint32_t PTPMCRC0; /*!< (@ 0x00000300) Media Clock Recovery Configuration Register 0 */ + + struct + { + __IOM uint32_t MRTTS : 1; /*!< [0..0] Media Clock Recovery Timer Type Select */ + __IOM uint32_t MRAMS : 1; /*!< [1..1] Media Clock Recovery AVTP Mode Select */ + __IOM uint32_t MRTNS : 1; /*!< [2..2] Media Clock Recovery Timer Number Select */ + uint32_t : 13; + __IOM uint32_t MRPL : 16; /*!< [31..16] Media Clock Recovery Pulse Length */ + } PTPMCRC0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCL0; /*!< (@ 0x00000304) Media Clock Recovery Time Configuration Register + * L0 */ + + struct + { + __IOM uint32_t MRTVL : 32; /*!< [31..0] Media Clock Recovery Timer Value Lower Part */ + } PTPMCRTCL0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCM0; /*!< (@ 0x00000308) Media Clock Recovery Time Configuration Register + * M0 */ + + struct + { + __IOM uint32_t MRTVM : 32; /*!< [31..0] Media Clock Recovery Timer Value Middle Part */ + } PTPMCRTCM0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCU0; /*!< (@ 0x0000030C) Media Clock Recovery Time Configuration Register + * U0 */ + + struct + { + __IOM uint32_t MRTVU : 16; /*!< [15..0] Media Clock Recovery Timer Value Upper Part */ + __IOM uint32_t MRTT : 2; /*!< [17..16] Media Clock Recovery Trigger Type */ + __IM uint32_t MCRN : 3; /*!< [20..18] Media Clock Recovery Number */ + uint32_t : 10; + __IM uint32_t MRBCR : 1; /*!< [31..31] Media Clock Recovery Buffer Clear Request */ + } PTPMCRTCU0_b; + }; + + union + { + __IOM uint32_t PTPMCRC1; /*!< (@ 0x00000310) Media Clock Recovery Configuration Register 1 */ + + struct + { + __IOM uint32_t MRTTS : 1; /*!< [0..0] Media Clock Recovery Timer Type Select */ + __IOM uint32_t MRAMS : 1; /*!< [1..1] Media Clock Recovery AVTP Mode Select */ + __IOM uint32_t MRTNS : 1; /*!< [2..2] Media Clock Recovery Timer Number Select */ + uint32_t : 13; + __IOM uint32_t MRPL : 16; /*!< [31..16] Media Clock Recovery Pulse Length */ + } PTPMCRC1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCL1; /*!< (@ 0x00000314) Media Clock Recovery Time Configuration Register + * L1 */ + + struct + { + __IOM uint32_t MRTVL : 32; /*!< [31..0] Media Clock Recovery Timer Value Lower Part */ + } PTPMCRTCL1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCM1; /*!< (@ 0x00000318) Media Clock Recovery Time Configuration Register + * M1 */ + + struct + { + __IOM uint32_t MRTVM : 32; /*!< [31..0] Media Clock Recovery Timer Value Middle Part */ + } PTPMCRTCM1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCU1; /*!< (@ 0x0000031C) Media Clock Recovery Time Configuration Register + * U1 */ + + struct + { + __IOM uint32_t MRTVU : 16; /*!< [15..0] Media Clock Recovery Timer Value Upper Part */ + __IOM uint32_t MRTT : 2; /*!< [17..16] Media Clock Recovery Trigger Type */ + __IM uint32_t MCRN : 3; /*!< [20..18] Media Clock Recovery Number */ + uint32_t : 10; + __IM uint32_t MRBCR : 1; /*!< [31..31] Media Clock Recovery Buffer Clear Request */ + } PTPMCRTCU1_b; + }; + __IM uint32_t RESERVED11[56]; + + union + { + __IOM uint32_t PTPMCPC0; /*!< (@ 0x00000400) Media Clock Pin Configuration Register 0 */ + + struct + { + __IOM uint32_t PE : 1; /*!< [0..0] Pin Enable */ + __IOM uint32_t MRS : 1; /*!< [1..1] Media Clock Recovery Select */ + uint32_t : 30; + } PTPMCPC0_b; + }; + + union + { + __IOM uint32_t PTPMCPC1; /*!< (@ 0x00000404) Media Clock Pin Configuration Register 1 */ + + struct + { + __IOM uint32_t PE : 1; /*!< [0..0] Pin Enable */ + __IOM uint32_t MRS : 1; /*!< [1..1] Media Clock Recovery Select */ + uint32_t : 30; + } PTPMCPC1_b; + }; + __IM uint32_t RESERVED12[62]; + + union + { + __IOM uint32_t PTPCCC00; /*!< (@ 0x00000500) Cyclic Compare Configuration Register 00 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC00_b; + }; + + union + { + __IOM uint32_t PTPCCC10; /*!< (@ 0x00000504) Cyclic Compare Configuration Register 10 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC10_b; + }; + + union + { + __IOM uint32_t PTPCCC01; /*!< (@ 0x00000508) Cyclic Compare Configuration Register 01 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC01_b; + }; + + union + { + __IOM uint32_t PTPCCC11; /*!< (@ 0x0000050C) Cyclic Compare Configuration Register 11 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC11_b; + }; + + union + { + __IOM uint32_t PTPCCC02; /*!< (@ 0x00000510) Cyclic Compare Configuration Register 02 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC02_b; + }; + + union + { + __IOM uint32_t PTPCCC12; /*!< (@ 0x00000514) Cyclic Compare Configuration Register 12 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC12_b; + }; + + union + { + __IOM uint32_t PTPCCC03; /*!< (@ 0x00000518) Cyclic Compare Configuration Register 03 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC03_b; + }; + + union + { + __IOM uint32_t PTPCCC13; /*!< (@ 0x0000051C) Cyclic Compare Configuration Register 13 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC13_b; + }; + + union + { + __IOM uint32_t PTPCCC04; /*!< (@ 0x00000520) Cyclic Compare Configuration Register 04 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC04_b; + }; + + union + { + __IOM uint32_t PTPCCC14; /*!< (@ 0x00000524) Cyclic Compare Configuration Register 14 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC14_b; + }; + + union + { + __IOM uint32_t PTPCCC05; /*!< (@ 0x00000528) Cyclic Compare Configuration Register 05 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC05_b; + }; + + union + { + __IOM uint32_t PTPCCC15; /*!< (@ 0x0000052C) Cyclic Compare Configuration Register 15 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC15_b; + }; + + union + { + __IOM uint32_t PTPCCC06; /*!< (@ 0x00000530) Cyclic Compare Configuration Register 06 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC06_b; + }; + + union + { + __IOM uint32_t PTPCCC16; /*!< (@ 0x00000534) Cyclic Compare Configuration Register 16 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC16_b; + }; + + union + { + __IOM uint32_t PTPCCC07; /*!< (@ 0x00000538) Cyclic Compare Configuration Register 07 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC07_b; + }; + + union + { + __IOM uint32_t PTPCCC17; /*!< (@ 0x0000053C) Cyclic Compare Configuration Register 17 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC17_b; + }; + __IM uint32_t RESERVED13[112]; + + union + { + __IOM uint32_t PTPIS0; /*!< (@ 0x00000700) Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t MCCS : 2; /*!< [1..0] Media Clock Capture Status */ + uint32_t : 14; + __IOM uint32_t MCCOES : 2; /*!< [17..16] Media Clock Capture Overflow Error Status */ + uint32_t : 14; + } PTPIS0_b; + }; + + union + { + __IOM uint32_t PTPIE0; /*!< (@ 0x00000704) Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t MCCE : 2; /*!< [1..0] Media Clock Capture Enable */ + uint32_t : 14; + __IOM uint32_t MCCOEE : 2; /*!< [17..16] Media Clock Capture Overflow Error Enable */ + uint32_t : 14; + } PTPIE0_b; + }; + + union + { + __IM uint32_t PTPID0; /*!< (@ 0x00000708) Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t MCCD : 2; /*!< [1..0] Media Clock Capture Disable */ + uint32_t : 14; + __IM uint32_t MCCOED : 2; /*!< [17..16] Media Clock Capture Overflow Error Disable */ + uint32_t : 14; + } PTPID0_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t PTPIS1; /*!< (@ 0x00000710) Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t MCRMS : 2; /*!< [1..0] Media Clock Recovery Match Status */ + uint32_t : 30; + } PTPIS1_b; + }; + + union + { + __IOM uint32_t PTPIE1; /*!< (@ 0x00000714) Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t MCRME : 2; /*!< [1..0] Media Clock Recovery Match Enable */ + uint32_t : 30; + } PTPIE1_b; + }; + + union + { + __IM uint32_t PTPID1; /*!< (@ 0x00000718) Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t MCRMD : 2; /*!< [1..0] Media Clock Recovery Match Disable */ + uint32_t : 30; + } PTPID1_b; + }; + __IM uint32_t RESERVED15[25]; + + union + { + __IOM uint32_t PTPSCR0; /*!< (@ 0x00000780) Security Configuration Register 0 */ + + struct + { + __IOM uint32_t TRSL : 2; /*!< [1..0] TRSL */ + uint32_t : 14; + __IOM uint32_t MCRSL : 2; /*!< [17..16] MCRSL */ + uint32_t : 14; + } PTPSCR0_b; + }; + + union + { + __IOM uint32_t PTPSCR1; /*!< (@ 0x00000784) Security Configuration Register 1 */ + + struct + { + __IOM uint32_t MRRSL : 2; /*!< [1..0] MRRSL */ + uint32_t : 14; + __IOM uint32_t MRRRSL : 2; /*!< [17..16] MRRRSL */ + uint32_t : 14; + } PTPSCR1_b; + }; + + union + { + __IOM uint32_t PTPSCR2; /*!< (@ 0x00000788) Security Configuration Register 2 */ + + struct + { + __IOM uint32_t CCRSL : 2; /*!< [1..0] CCRSL */ + uint32_t : 14; + __IOM uint32_t VRSL : 1; /*!< [16..16] VRSL */ + uint32_t : 15; + } PTPSCR2_b; + }; + __IM uint32_t RESERVED16[541]; + + union + { + __IOM uint32_t POTCFGR; /*!< (@ 0x00001000) Pulse Output Timer Configuration Register */ + + struct + { + __IOM uint32_t REFSEL : 1; /*!< [0..0] Reference Timer Select */ + uint32_t : 31; + } POTCFGR_b; + }; + + union + { + __IOM uint32_t POTCR0; /*!< (@ 0x00001004) Pulse Output Timer Control Register 0 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR0_b; + }; + __IOM uint32_t POTSTRU0; /*!< (@ 0x00001008) Pulse Output Start Time Setting Register U0 */ + __IOM uint32_t POTSTRM0; /*!< (@ 0x0000100C) Pulse Output Start Time Setting Register M0 */ + __IOM uint32_t POTSTRL0; /*!< (@ 0x00001010) Pulse Output Start Time Setting Register L0 */ + __IOM uint32_t POTPERU0; /*!< (@ 0x00001014) Period Setting Register U0 */ + __IOM uint32_t POTPERM0; /*!< (@ 0x00001018) Period Setting Register M0 */ + __IOM uint32_t POTPERL0; /*!< (@ 0x0000101C) Period Setting Register L0 */ + __IOM uint32_t POTPWR0; /*!< (@ 0x00001020) Pulse Width Setting Register 0 */ + __IM uint32_t RESERVED17; + __IM uint32_t POTCPRU0; /*!< (@ 0x00001028) Time Capture Register U0 */ + __IM uint32_t POTCPRM0; /*!< (@ 0x0000102C) Time Capture Register M0 */ + __IM uint32_t POTCPRL0; /*!< (@ 0x00001030) Time Capture Register L0 */ + + union + { + __IOM uint32_t POTCR1; /*!< (@ 0x00001034) Pulse Output Timer Control Register 1 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR1_b; + }; + __IOM uint32_t POTSTRU1; /*!< (@ 0x00001038) Pulse Output Start Time Setting Register U1 */ + __IOM uint32_t POTSTRM1; /*!< (@ 0x0000103C) Pulse Output Start Time Setting Register M1 */ + __IOM uint32_t POTSTRL1; /*!< (@ 0x00001040) Pulse Output Start Time Setting Register L1 */ + __IOM uint32_t POTPERU1; /*!< (@ 0x00001044) Period Setting Register U1 */ + __IOM uint32_t POTPERM1; /*!< (@ 0x00001048) Period Setting Register M1 */ + __IOM uint32_t POTPERL1; /*!< (@ 0x0000104C) Period Setting Register L1 */ + __IOM uint32_t POTPWR1; /*!< (@ 0x00001050) Pulse Width Setting Register 1 */ + __IM uint32_t RESERVED18; + __IM uint32_t POTCPRU1; /*!< (@ 0x00001058) Time Capture Register U1 */ + __IM uint32_t POTCPRM1; /*!< (@ 0x0000105C) Time Capture Register M1 */ + __IM uint32_t POTCPRL1; /*!< (@ 0x00001060) Time Capture Register L1 */ + + union + { + __IOM uint32_t POTCR2; /*!< (@ 0x00001064) Pulse Output Timer Control Register 2 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR2_b; + }; + __IOM uint32_t POTSTRU2; /*!< (@ 0x00001068) Pulse Output Start Time Setting Register U2 */ + __IOM uint32_t POTSTRM2; /*!< (@ 0x0000106C) Pulse Output Start Time Setting Register M2 */ + __IOM uint32_t POTSTRL2; /*!< (@ 0x00001070) Pulse Output Start Time Setting Register L2 */ + __IOM uint32_t POTPERU2; /*!< (@ 0x00001074) Period Setting Register U2 */ + __IOM uint32_t POTPERM2; /*!< (@ 0x00001078) Period Setting Register M2 */ + __IOM uint32_t POTPERL2; /*!< (@ 0x0000107C) Period Setting Register L2 */ + __IOM uint32_t POTPWR2; /*!< (@ 0x00001080) Pulse Width Setting Register 2 */ + __IM uint32_t RESERVED19; + __IM uint32_t POTCPRU2; /*!< (@ 0x00001088) Time Capture Register U2 */ + __IM uint32_t POTCPRM2; /*!< (@ 0x0000108C) Time Capture Register M2 */ + __IM uint32_t POTCPRL2; /*!< (@ 0x00001090) Time Capture Register L2 */ + + union + { + __IOM uint32_t POTCR3; /*!< (@ 0x00001094) Pulse Output Timer Control Register 3 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR3_b; + }; + __IOM uint32_t POTSTRU3; /*!< (@ 0x00001098) Pulse Output Start Time Setting Register U3 */ + __IOM uint32_t POTSTRM3; /*!< (@ 0x0000109C) Pulse Output Start Time Setting Register M3 */ + __IOM uint32_t POTSTRL3; /*!< (@ 0x000010A0) Pulse Output Start Time Setting Register L3 */ + __IOM uint32_t POTPERU3; /*!< (@ 0x000010A4) Period Setting Register U3 */ + __IOM uint32_t POTPERM3; /*!< (@ 0x000010A8) Period Setting Register M3 */ + __IOM uint32_t POTPERL3; /*!< (@ 0x000010AC) Period Setting Register L3 */ + __IOM uint32_t POTPWR3; /*!< (@ 0x000010B0) Pulse Width Setting Register 3 */ + __IM uint32_t RESERVED20; + __IM uint32_t POTCPRU3; /*!< (@ 0x000010B8) Time Capture Register U3 */ + __IM uint32_t POTCPRM3; /*!< (@ 0x000010BC) Time Capture Register M3 */ + __IM uint32_t POTCPRL3; /*!< (@ 0x000010C0) Time Capture Register L3 */ +} R_GPTP_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_GWCA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Gateway CPU Agent (R_GWCA0) + */ + +typedef struct /*!< (@ 0x403CE000) R_GWCA0 Structure */ +{ + union + { + __IOM uint32_t GWMC; /*!< (@ 0x00000000) GWCA Mode Configuration Register (GWMC) */ + + struct + { + __IOM uint32_t OPC : 2; /*!< [1..0] OPC */ + uint32_t : 30; + } GWMC_b; + }; + + union + { + __IOM uint32_t GWMS; /*!< (@ 0x00000004) GWCA Mode Status Register (GWMS) */ + + struct + { + __IOM uint32_t OPS : 2; /*!< [1..0] OPS */ + uint32_t : 30; + } GWMS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GWIRC; /*!< (@ 0x00000010) GWCA IPV Remapping Configuration Register [802.1Q] + * (GWIRC) */ + + struct + { + __IOM uint32_t IPVR0 : 3; /*!< [2..0] IPVR0 */ + uint32_t : 1; + __IOM uint32_t IPVR1 : 3; /*!< [6..4] IPVR1 */ + uint32_t : 1; + __IOM uint32_t IPVR2 : 3; /*!< [10..8] IPVR2 */ + uint32_t : 1; + __IOM uint32_t IPVR3 : 3; /*!< [14..12] IPVR3 */ + uint32_t : 1; + __IOM uint32_t IPVR4 : 3; /*!< [18..16] IPVR4 */ + uint32_t : 1; + __IOM uint32_t IPVR5 : 3; /*!< [22..20] IPVR5 */ + uint32_t : 1; + __IOM uint32_t IPVR6 : 3; /*!< [26..24] IPVR6 */ + uint32_t : 1; + __IOM uint32_t IPVR7 : 3; /*!< [30..28] IPVR7 */ + uint32_t : 1; + } GWIRC_b; + }; + + union + { + __IOM uint32_t GWRDQSC; /*!< (@ 0x00000014) GWCA RX Descriptor Queue Security Configuration + * Register (GWRDQSC) */ + + struct + { + __IOM uint32_t RDQSL0 : 1; /*!< [0..0] RDQSL0 */ + __IOM uint32_t RDQSL1 : 1; /*!< [1..1] RDQSL1 */ + __IOM uint32_t RDQSL2 : 1; /*!< [2..2] RDQSL2 */ + __IOM uint32_t RDQSL3 : 1; /*!< [3..3] RDQSL3 */ + __IOM uint32_t RDQSL4 : 1; /*!< [4..4] RDQSL4 */ + __IOM uint32_t RDQSL5 : 1; /*!< [5..5] RDQSL5 */ + __IOM uint32_t RDQSL6 : 1; /*!< [6..6] RDQSL6 */ + __IOM uint32_t RDQSL7 : 1; /*!< [7..7] RDQSL7 */ + uint32_t : 24; + } GWRDQSC_b; + }; + + union + { + __IOM uint32_t GWRDQC; /*!< (@ 0x00000018) GWCA RX Descriptor Queue Control Register (GWRDQC) */ + + struct + { + __IOM uint32_t RDQD0 : 1; /*!< [0..0] RDQD0 */ + __IOM uint32_t RDQD1 : 1; /*!< [1..1] RDQD1 */ + __IOM uint32_t RDQD2 : 1; /*!< [2..2] RDQD2 */ + __IOM uint32_t RDQD3 : 1; /*!< [3..3] RDQD3 */ + __IOM uint32_t RDQD4 : 1; /*!< [4..4] RDQD4 */ + __IOM uint32_t RDQD5 : 1; /*!< [5..5] RDQD5 */ + __IOM uint32_t RDQD6 : 1; /*!< [6..6] RDQD6 */ + __IOM uint32_t RDQD7 : 1; /*!< [7..7] RDQD7 */ + uint32_t : 8; + __IOM uint32_t RDQP0 : 1; /*!< [16..16] RDQP0 */ + __IOM uint32_t RDQP1 : 1; /*!< [17..17] RDQP1 */ + __IOM uint32_t RDQP2 : 1; /*!< [18..18] RDQP2 */ + __IOM uint32_t RDQP3 : 1; /*!< [19..19] RDQP3 */ + __IOM uint32_t RDQP4 : 1; /*!< [20..20] RDQP4 */ + __IOM uint32_t RDQP5 : 1; /*!< [21..21] RDQP5 */ + __IOM uint32_t RDQP6 : 1; /*!< [22..22] RDQP6 */ + __IOM uint32_t RDQP7 : 1; /*!< [23..23] RDQP7 */ + uint32_t : 8; + } GWRDQC_b; + }; + + union + { + __IOM uint32_t GWRDQAC; /*!< (@ 0x0000001C) GWCA RX Descriptor Queue Arbitration Control + * Register (GWRDQAC) */ + + struct + { + __IOM uint32_t RDQA0 : 4; /*!< [3..0] RDQA0 */ + __IOM uint32_t RDQA1 : 4; /*!< [7..4] RDQA1 */ + __IOM uint32_t RDQA2 : 4; /*!< [11..8] RDQA2 */ + __IOM uint32_t RDQA3 : 4; /*!< [15..12] RDQA3 */ + __IOM uint32_t RDQA4 : 4; /*!< [19..16] RDQA4 */ + __IOM uint32_t RDQA5 : 4; /*!< [23..20] RDQA5 */ + __IOM uint32_t RDQA6 : 4; /*!< [27..24] RDQA6 */ + __IOM uint32_t RDQA7 : 4; /*!< [31..28] RDQA7 */ + } GWRDQAC_b; + }; + + union + { + __IOM uint32_t GWRGC; /*!< (@ 0x00000020) GWCA RX General Configuration Register (GWRGC) */ + + struct + { + __IOM uint32_t RCPT : 1; /*!< [0..0] RCPT */ + uint32_t : 31; + } GWRGC_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t GWRMFSC0; /*!< (@ 0x00000040) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC0_b; + }; + + union + { + __IOM uint32_t GWRMFSC1; /*!< (@ 0x00000044) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC1_b; + }; + + union + { + __IOM uint32_t GWRMFSC2; /*!< (@ 0x00000048) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC2_b; + }; + + union + { + __IOM uint32_t GWRMFSC3; /*!< (@ 0x0000004C) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC3_b; + }; + + union + { + __IOM uint32_t GWRMFSC4; /*!< (@ 0x00000050) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC4_b; + }; + + union + { + __IOM uint32_t GWRMFSC5; /*!< (@ 0x00000054) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC5_b; + }; + + union + { + __IOM uint32_t GWRMFSC6; /*!< (@ 0x00000058) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC6_b; + }; + + union + { + __IOM uint32_t GWRMFSC7; /*!< (@ 0x0000005C) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC7_b; + }; + + union + { + __IOM uint32_t GWRDQDC0; /*!< (@ 0x00000060) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC0_b; + }; + + union + { + __IOM uint32_t GWRDQDC1; /*!< (@ 0x00000064) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC1_b; + }; + + union + { + __IOM uint32_t GWRDQDC2; /*!< (@ 0x00000068) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC2_b; + }; + + union + { + __IOM uint32_t GWRDQDC3; /*!< (@ 0x0000006C) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC3_b; + }; + + union + { + __IOM uint32_t GWRDQDC4; /*!< (@ 0x00000070) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC4_b; + }; + + union + { + __IOM uint32_t GWRDQDC5; /*!< (@ 0x00000074) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC5_b; + }; + + union + { + __IOM uint32_t GWRDQDC6; /*!< (@ 0x00000078) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC6_b; + }; + + union + { + __IOM uint32_t GWRDQDC7; /*!< (@ 0x0000007C) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC7_b; + }; + + union + { + __IOM uint32_t GWRDQM0; /*!< (@ 0x00000080) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM0_b; + }; + + union + { + __IOM uint32_t GWRDQM1; /*!< (@ 0x00000084) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM1_b; + }; + + union + { + __IOM uint32_t GWRDQM2; /*!< (@ 0x00000088) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM2_b; + }; + + union + { + __IOM uint32_t GWRDQM3; /*!< (@ 0x0000008C) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM3_b; + }; + + union + { + __IOM uint32_t GWRDQM4; /*!< (@ 0x00000090) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM4_b; + }; + + union + { + __IOM uint32_t GWRDQM5; /*!< (@ 0x00000094) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM5_b; + }; + + union + { + __IOM uint32_t GWRDQM6; /*!< (@ 0x00000098) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM6_b; + }; + + union + { + __IOM uint32_t GWRDQM7; /*!< (@ 0x0000009C) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM7_b; + }; + + union + { + __IOM uint32_t GWRDQMLM0; /*!< (@ 0x000000A0) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM0_b; + }; + + union + { + __IOM uint32_t GWRDQMLM1; /*!< (@ 0x000000A4) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM1_b; + }; + + union + { + __IOM uint32_t GWRDQMLM2; /*!< (@ 0x000000A8) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM2_b; + }; + + union + { + __IOM uint32_t GWRDQMLM3; /*!< (@ 0x000000AC) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM3_b; + }; + + union + { + __IOM uint32_t GWRDQMLM4; /*!< (@ 0x000000B0) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM4_b; + }; + + union + { + __IOM uint32_t GWRDQMLM5; /*!< (@ 0x000000B4) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM5_b; + }; + + union + { + __IOM uint32_t GWRDQMLM6; /*!< (@ 0x000000B8) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM6_b; + }; + + union + { + __IOM uint32_t GWRDQMLM7; /*!< (@ 0x000000BC) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM7_b; + }; + __IM uint32_t RESERVED2[16]; + + union + { + __IOM uint32_t GWMTIRM; /*!< (@ 0x00000100) GWCA Multicast Table Initialization Register + * Monitoring Register (GWMTIRM) */ + + struct + { + __IOM uint32_t MTIOG : 1; /*!< [0..0] MTIOG */ + __IOM uint32_t MTR : 1; /*!< [1..1] MTR */ + uint32_t : 30; + } GWMTIRM_b; + }; + + union + { + __IOM uint32_t GWMSTLS; /*!< (@ 0x00000104) GWCA Multicast Table Learning Setting Register + * (GWMSTLS) */ + + struct + { + __IOM uint32_t MNRCNL : 7; /*!< [6..0] MNRCNL */ + uint32_t : 1; + __IOM uint32_t MNL : 3; /*!< [10..8] MNL */ + uint32_t : 5; + __IOM uint32_t MSENL : 7; /*!< [22..16] MSENL */ + uint32_t : 9; + } GWMSTLS_b; + }; + + union + { + __IOM uint32_t GWMSTLR; /*!< (@ 0x00000108) GWCA Multicast Table Learning Result Register + * (GWMSTLR) */ + + struct + { + __IOM uint32_t MTLF : 1; /*!< [0..0] MTLF */ + uint32_t : 30; + __IOM uint32_t MTL : 1; /*!< [31..31] MTL */ + } GWMSTLR_b; + }; + + union + { + __IOM uint32_t GWMSTSS; /*!< (@ 0x0000010C) GWCA Multicast Table Searching Setting Register + * (GWMSTSS) */ + + struct + { + __IOM uint32_t MSENS : 7; /*!< [6..0] MSENS */ + uint32_t : 25; + } GWMSTSS_b; + }; + + union + { + __IOM uint32_t GWMSTSR; /*!< (@ 0x00000110) GWCA Multicast Table Searching Result Register + * (GWMSTSR) */ + + struct + { + __IOM uint32_t MNRCNR : 7; /*!< [6..0] MNRCNR */ + uint32_t : 1; + __IOM uint32_t MNR : 3; /*!< [10..8] MNR */ + uint32_t : 5; + __IOM uint32_t MTSEF : 1; /*!< [16..16] MTSEF */ + uint32_t : 14; + __IOM uint32_t MTS : 1; /*!< [31..31] MTS */ + } GWMSTSR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t GWMAC0; /*!< (@ 0x00000120) GWCA MAC Address Configuration Register 0 (GWMAC0) */ + + struct + { + __IOM uint32_t MAUP : 16; /*!< [15..0] MAUP */ + uint32_t : 16; + } GWMAC0_b; + }; + + union + { + __IOM uint32_t GWMAC1; /*!< (@ 0x00000124) GWCA MAC Address Configuration Register 1 (GWMAC1) */ + + struct + { + __IOM uint32_t MADP : 32; /*!< [31..0] MADP */ + } GWMAC1_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t GWVCC; /*!< (@ 0x00000130) GWCA VLAN Control Configuration Register (GWVCC) */ + + struct + { + __IOM uint32_t VIM : 1; /*!< [0..0] VIM */ + uint32_t : 7; + __IOM uint32_t CTVUM : 1; /*!< [8..8] CTVUM */ + uint32_t : 7; + __IOM uint32_t VEM : 3; /*!< [18..16] VEM */ + uint32_t : 13; + } GWVCC_b; + }; + + union + { + __IOM uint32_t GWVTC; /*!< (@ 0x00000134) GWCA VLAN TAG Configuration Register (GWVTC) */ + + struct + { + __IOM uint32_t CTV : 12; /*!< [11..0] CTV */ + __IOM uint32_t CTP : 3; /*!< [14..12] CTP */ + __IOM uint32_t CTD : 1; /*!< [15..15] CTD */ + __IOM uint32_t STV : 12; /*!< [27..16] STV */ + __IOM uint32_t STP : 3; /*!< [30..28] STP */ + __IOM uint32_t STD : 1; /*!< [31..31] STD */ + } GWVTC_b; + }; + + union + { + __IOM uint32_t GWTTFC; /*!< (@ 0x00000138) GWCA Transmission TAG Filtering Configuration + * Register (GWTTFC) */ + + struct + { + __IOM uint32_t NT : 1; /*!< [0..0] NT */ + __IOM uint32_t RT : 1; /*!< [1..1] RT */ + __IOM uint32_t CST : 1; /*!< [2..2] CST */ + __IOM uint32_t CSRT : 1; /*!< [3..3] CSRT */ + __IOM uint32_t CT : 1; /*!< [4..4] CT */ + __IOM uint32_t CRT : 1; /*!< [5..5] CRT */ + __IOM uint32_t SCT : 1; /*!< [6..6] SCT */ + __IOM uint32_t SCRT : 1; /*!< [7..7] SCRT */ + __IOM uint32_t UT : 1; /*!< [8..8] UT */ + uint32_t : 23; + } GWTTFC_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t GWTDCAC00; /*!< (@ 0x00000140) GWCA Timestamp Descriptor Chain Address Configuration + * Register 0s (GWTDCAC0s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCAUP : 8; /*!< [7..0] TSCCAUP */ + uint32_t : 24; + } GWTDCAC00_b; + }; + + union + { + __IOM uint32_t GWTDCAC10; /*!< (@ 0x00000144) GWCA Timestamp Descriptor Chain Address Configuration + * Register 1s (GWTDCAC1s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCADP : 32; /*!< [31..0] TSCCADP */ + } GWTDCAC10_b; + }; + + union + { + __IOM uint32_t GWTDCAC01; /*!< (@ 0x00000148) GWCA Timestamp Descriptor Chain Address Configuration + * Register 0s (GWTDCAC0s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCAUP : 8; /*!< [7..0] TSCCAUP */ + uint32_t : 24; + } GWTDCAC01_b; + }; + + union + { + __IOM uint32_t GWTDCAC11; /*!< (@ 0x0000014C) GWCA Timestamp Descriptor Chain Address Configuration + * Register 1s (GWTDCAC1s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCADP : 32; /*!< [31..0] TSCCADP */ + } GWTDCAC11_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t GWTSDCC0; /*!< (@ 0x00000160) GWCA Timestamp Descriptor Chain Configuration + * Register s (GWTSDCCs) (s = 0, 1) */ + + struct + { + __IOM uint32_t TE : 1; /*!< [0..0] TE */ + __IOM uint32_t DCS : 2; /*!< [2..1] DCS */ + uint32_t : 5; + __IOM uint32_t OSID : 3; /*!< [10..8] OSID */ + uint32_t : 21; + } GWTSDCC0_b; + }; + + union + { + __IOM uint32_t GWTSDCC1; /*!< (@ 0x00000164) GWCA Timestamp Descriptor Chain Configuration + * Register s (GWTSDCCs) (s = 0, 1) */ + + struct + { + __IOM uint32_t TE : 1; /*!< [0..0] TE */ + __IOM uint32_t DCS : 2; /*!< [2..1] DCS */ + uint32_t : 5; + __IOM uint32_t OSID : 3; /*!< [10..8] OSID */ + uint32_t : 21; + } GWTSDCC1_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t GWTSNM; /*!< (@ 0x00000180) GWCA Timestamp Number Monitoring Register (GWTSNM) */ + + struct + { + __IOM uint32_t TNTR : 8; /*!< [7..0] TNTR */ + uint32_t : 24; + } GWTSNM_b; + }; + + union + { + __IOM uint32_t GWTSMNM; /*!< (@ 0x00000184) GWCA Timestamp Maximum Number Monitoring Register + * (GWTSMNM) */ + + struct + { + __IOM uint32_t TMNTR : 8; /*!< [7..0] TMNTR */ + uint32_t : 24; + } GWTSMNM_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t GWAC; /*!< (@ 0x00000190) GWCA AXI Control Register (GWAC) */ + + struct + { + __IOM uint32_t AMPR : 1; /*!< [0..0] AMPR */ + __IOM uint32_t AMP : 1; /*!< [1..1] AMP */ + uint32_t : 30; + } GWAC_b; + }; + + union + { + __IOM uint32_t GWDCBAC0; /*!< (@ 0x00000194) GWCA Descriptor Chain Base Address Configuration + * Register 0 (GWDCBAC0) */ + + struct + { + __IOM uint32_t DCBAUP : 8; /*!< [7..0] DCBAUP */ + uint32_t : 24; + } GWDCBAC0_b; + }; + + union + { + __IOM uint32_t GWDCBAC1; /*!< (@ 0x00000198) GWCA Descriptor Chain Base Address Configuration + * Register 1 (GWDCBAC1) */ + + struct + { + __IOM uint32_t DCBADP : 32; /*!< [31..0] DCBADP */ + } GWDCBAC1_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t GWMDNC; /*!< (@ 0x000001A0) GWCA Maximum Descriptor Number Configuration + * Register (GWMDNC) */ + + struct + { + __IOM uint32_t RXDMN : 5; /*!< [4..0] RXDMN */ + uint32_t : 3; + __IOM uint32_t TXDMN : 5; /*!< [12..8] TXDMN */ + uint32_t : 3; + __IOM uint32_t TSDMN : 2; /*!< [17..16] TSDMN */ + uint32_t : 14; + } GWMDNC_b; + }; + __IM uint32_t RESERVED10[23]; + __IOM uint32_t GWTRC0; /*!< (@ 0x00000200) GWCA Transmission Request Configuration Register + * i (GWTRCi) (i = 0, 1) */ + __IOM uint32_t GWTRC1; /*!< (@ 0x00000204) GWCA Transmission Request Configuration Register + * i (GWTRCi) (i = 0, 1) */ + __IM uint32_t RESERVED11[62]; + + union + { + __IOM uint32_t GWTPC0; /*!< (@ 0x00000300) GWCA Transmission Pause Configuration Register + * p (GWTPCp) (p = 0, 1) */ + + struct + { + __IOM uint32_t PPPL0 : 1; /*!< [0..0] PPPL0 */ + __IOM uint32_t PPPL1 : 1; /*!< [1..1] PPPL1 */ + __IOM uint32_t PPPL2 : 1; /*!< [2..2] PPPL2 */ + __IOM uint32_t PPPL3 : 1; /*!< [3..3] PPPL3 */ + __IOM uint32_t PPPL4 : 1; /*!< [4..4] PPPL4 */ + __IOM uint32_t PPPL5 : 1; /*!< [5..5] PPPL5 */ + __IOM uint32_t PPPL6 : 1; /*!< [6..6] PPPL6 */ + __IOM uint32_t PPPL7 : 1; /*!< [7..7] PPPL7 */ + __IOM uint32_t PPPL8 : 1; /*!< [8..8] PPPL8 */ + uint32_t : 23; + } GWTPC0_b; + }; + + union + { + __IOM uint32_t GWTPC1; /*!< (@ 0x00000304) GWCA Transmission Pause Configuration Register + * p (GWTPCp) (p = 0, 1) */ + + struct + { + __IOM uint32_t PPPL0 : 1; /*!< [0..0] PPPL0 */ + __IOM uint32_t PPPL1 : 1; /*!< [1..1] PPPL1 */ + __IOM uint32_t PPPL2 : 1; /*!< [2..2] PPPL2 */ + __IOM uint32_t PPPL3 : 1; /*!< [3..3] PPPL3 */ + __IOM uint32_t PPPL4 : 1; /*!< [4..4] PPPL4 */ + __IOM uint32_t PPPL5 : 1; /*!< [5..5] PPPL5 */ + __IOM uint32_t PPPL6 : 1; /*!< [6..6] PPPL6 */ + __IOM uint32_t PPPL7 : 1; /*!< [7..7] PPPL7 */ + __IOM uint32_t PPPL8 : 1; /*!< [8..8] PPPL8 */ + uint32_t : 23; + } GWTPC1_b; + }; + __IM uint32_t RESERVED12[30]; + + union + { + __IOM uint32_t GWARIRM; /*!< (@ 0x00000380) GWCA AXI RAM Initialization Register Monitoring + * Register (GWARIRM) */ + + struct + { + __IOM uint32_t ARIOG : 1; /*!< [0..0] ARIOG */ + __IOM uint32_t ARR : 1; /*!< [1..1] ARR */ + uint32_t : 30; + } GWARIRM_b; + }; + __IM uint32_t RESERVED13[31]; + + union + { + __IOM uint32_t GWDCC0; /*!< (@ 0x00000400) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC0_b; + }; + + union + { + __IOM uint32_t GWDCC1; /*!< (@ 0x00000404) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC1_b; + }; + + union + { + __IOM uint32_t GWDCC2; /*!< (@ 0x00000408) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC2_b; + }; + + union + { + __IOM uint32_t GWDCC3; /*!< (@ 0x0000040C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC3_b; + }; + + union + { + __IOM uint32_t GWDCC4; /*!< (@ 0x00000410) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC4_b; + }; + + union + { + __IOM uint32_t GWDCC5; /*!< (@ 0x00000414) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC5_b; + }; + + union + { + __IOM uint32_t GWDCC6; /*!< (@ 0x00000418) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC6_b; + }; + + union + { + __IOM uint32_t GWDCC7; /*!< (@ 0x0000041C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC7_b; + }; + + union + { + __IOM uint32_t GWDCC8; /*!< (@ 0x00000420) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC8_b; + }; + + union + { + __IOM uint32_t GWDCC9; /*!< (@ 0x00000424) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC9_b; + }; + + union + { + __IOM uint32_t GWDCC10; /*!< (@ 0x00000428) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC10_b; + }; + + union + { + __IOM uint32_t GWDCC11; /*!< (@ 0x0000042C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC11_b; + }; + + union + { + __IOM uint32_t GWDCC12; /*!< (@ 0x00000430) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC12_b; + }; + + union + { + __IOM uint32_t GWDCC13; /*!< (@ 0x00000434) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC13_b; + }; + + union + { + __IOM uint32_t GWDCC14; /*!< (@ 0x00000438) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC14_b; + }; + + union + { + __IOM uint32_t GWDCC15; /*!< (@ 0x0000043C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC15_b; + }; + + union + { + __IOM uint32_t GWDCC16; /*!< (@ 0x00000440) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC16_b; + }; + + union + { + __IOM uint32_t GWDCC17; /*!< (@ 0x00000444) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC17_b; + }; + + union + { + __IOM uint32_t GWDCC18; /*!< (@ 0x00000448) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC18_b; + }; + + union + { + __IOM uint32_t GWDCC19; /*!< (@ 0x0000044C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC19_b; + }; + + union + { + __IOM uint32_t GWDCC20; /*!< (@ 0x00000450) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC20_b; + }; + + union + { + __IOM uint32_t GWDCC21; /*!< (@ 0x00000454) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC21_b; + }; + + union + { + __IOM uint32_t GWDCC22; /*!< (@ 0x00000458) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC22_b; + }; + + union + { + __IOM uint32_t GWDCC23; /*!< (@ 0x0000045C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC23_b; + }; + + union + { + __IOM uint32_t GWDCC24; /*!< (@ 0x00000460) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC24_b; + }; + + union + { + __IOM uint32_t GWDCC25; /*!< (@ 0x00000464) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC25_b; + }; + + union + { + __IOM uint32_t GWDCC26; /*!< (@ 0x00000468) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC26_b; + }; + + union + { + __IOM uint32_t GWDCC27; /*!< (@ 0x0000046C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC27_b; + }; + + union + { + __IOM uint32_t GWDCC28; /*!< (@ 0x00000470) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC28_b; + }; + + union + { + __IOM uint32_t GWDCC29; /*!< (@ 0x00000474) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC29_b; + }; + + union + { + __IOM uint32_t GWDCC30; /*!< (@ 0x00000478) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC30_b; + }; + + union + { + __IOM uint32_t GWDCC31; /*!< (@ 0x0000047C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC31_b; + }; + + union + { + __IOM uint32_t GWDCC32; /*!< (@ 0x00000480) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC32_b; + }; + + union + { + __IOM uint32_t GWDCC33; /*!< (@ 0x00000484) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC33_b; + }; + + union + { + __IOM uint32_t GWDCC34; /*!< (@ 0x00000488) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC34_b; + }; + + union + { + __IOM uint32_t GWDCC35; /*!< (@ 0x0000048C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC35_b; + }; + + union + { + __IOM uint32_t GWDCC36; /*!< (@ 0x00000490) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC36_b; + }; + + union + { + __IOM uint32_t GWDCC37; /*!< (@ 0x00000494) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC37_b; + }; + + union + { + __IOM uint32_t GWDCC38; /*!< (@ 0x00000498) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC38_b; + }; + + union + { + __IOM uint32_t GWDCC39; /*!< (@ 0x0000049C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC39_b; + }; + + union + { + __IOM uint32_t GWDCC40; /*!< (@ 0x000004A0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC40_b; + }; + + union + { + __IOM uint32_t GWDCC41; /*!< (@ 0x000004A4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC41_b; + }; + + union + { + __IOM uint32_t GWDCC42; /*!< (@ 0x000004A8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC42_b; + }; + + union + { + __IOM uint32_t GWDCC43; /*!< (@ 0x000004AC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC43_b; + }; + + union + { + __IOM uint32_t GWDCC44; /*!< (@ 0x000004B0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC44_b; + }; + + union + { + __IOM uint32_t GWDCC45; /*!< (@ 0x000004B4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC45_b; + }; + + union + { + __IOM uint32_t GWDCC46; /*!< (@ 0x000004B8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC46_b; + }; + + union + { + __IOM uint32_t GWDCC47; /*!< (@ 0x000004BC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC47_b; + }; + + union + { + __IOM uint32_t GWDCC48; /*!< (@ 0x000004C0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC48_b; + }; + + union + { + __IOM uint32_t GWDCC49; /*!< (@ 0x000004C4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC49_b; + }; + + union + { + __IOM uint32_t GWDCC50; /*!< (@ 0x000004C8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC50_b; + }; + + union + { + __IOM uint32_t GWDCC51; /*!< (@ 0x000004CC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC51_b; + }; + + union + { + __IOM uint32_t GWDCC52; /*!< (@ 0x000004D0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC52_b; + }; + + union + { + __IOM uint32_t GWDCC53; /*!< (@ 0x000004D4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC53_b; + }; + + union + { + __IOM uint32_t GWDCC54; /*!< (@ 0x000004D8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC54_b; + }; + + union + { + __IOM uint32_t GWDCC55; /*!< (@ 0x000004DC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC55_b; + }; + + union + { + __IOM uint32_t GWDCC56; /*!< (@ 0x000004E0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC56_b; + }; + + union + { + __IOM uint32_t GWDCC57; /*!< (@ 0x000004E4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC57_b; + }; + + union + { + __IOM uint32_t GWDCC58; /*!< (@ 0x000004E8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC58_b; + }; + + union + { + __IOM uint32_t GWDCC59; /*!< (@ 0x000004EC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC59_b; + }; + + union + { + __IOM uint32_t GWDCC60; /*!< (@ 0x000004F0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC60_b; + }; + + union + { + __IOM uint32_t GWDCC61; /*!< (@ 0x000004F4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC61_b; + }; + + union + { + __IOM uint32_t GWDCC62; /*!< (@ 0x000004F8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC62_b; + }; + + union + { + __IOM uint32_t GWDCC63; /*!< (@ 0x000004FC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC63_b; + }; + __IM uint32_t RESERVED14[192]; + + union + { + __IOM uint32_t GWAARSS; /*!< (@ 0x00000800) GWCA AXI Address RAM Searching Setting Register + * (GWAARSS) */ + + struct + { + __IOM uint32_t AARA : 7; /*!< [6..0] AARA */ + uint32_t : 25; + } GWAARSS_b; + }; + + union + { + __IOM uint32_t GWAARSR0; /*!< (@ 0x00000804) GWCA AXI Address RAM Searching Result Register + * 0 (GWAARSR0) */ + + struct + { + __IOM uint32_t ACARU : 8; /*!< [7..0] ACARU */ + uint32_t : 8; + __IOM uint32_t AARSEF : 1; /*!< [16..16] AARSEF */ + __IOM uint32_t AARSSF : 1; /*!< [17..17] AARSSF */ + uint32_t : 13; + __IOM uint32_t AARS : 1; /*!< [31..31] AARS */ + } GWAARSR0_b; + }; + + union + { + __IOM uint32_t GWAARSR1; /*!< (@ 0x00000808) GWCA AXI Address RAM Searching Result Register + * 1 (GWAARSR1) */ + + struct + { + __IOM uint32_t ACARD : 32; /*!< [31..0] ACARD */ + } GWAARSR1_b; + }; + __IM uint32_t RESERVED15[13]; + + union + { + __IOM uint32_t GWIDAUAS0; /*!< (@ 0x00000840) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS0_b; + }; + + union + { + __IOM uint32_t GWIDAUAS1; /*!< (@ 0x00000844) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS1_b; + }; + + union + { + __IOM uint32_t GWIDAUAS2; /*!< (@ 0x00000848) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS2_b; + }; + + union + { + __IOM uint32_t GWIDAUAS3; /*!< (@ 0x0000084C) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS3_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __IOM uint32_t GWIDASM0; /*!< (@ 0x00000880) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM0_b; + }; + + union + { + __IOM uint32_t GWIDASM1; /*!< (@ 0x00000884) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM1_b; + }; + + union + { + __IOM uint32_t GWIDASM2; /*!< (@ 0x00000888) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM2_b; + }; + + union + { + __IOM uint32_t GWIDASM3; /*!< (@ 0x0000088C) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM3_b; + }; + __IM uint32_t RESERVED17[28]; + + union + { + __IOM uint32_t GWIDASAM00; /*!< (@ 0x00000900) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM00_b; + }; + + union + { + __IOM uint32_t GWIDASAM10; /*!< (@ 0x00000904) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM10_b; + }; + + union + { + __IOM uint32_t GWIDASAM01; /*!< (@ 0x00000908) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM01_b; + }; + + union + { + __IOM uint32_t GWIDASAM11; /*!< (@ 0x0000090C) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM11_b; + }; + + union + { + __IOM uint32_t GWIDASAM02; /*!< (@ 0x00000910) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM02_b; + }; + + union + { + __IOM uint32_t GWIDASAM12; /*!< (@ 0x00000914) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM12_b; + }; + + union + { + __IOM uint32_t GWIDASAM03; /*!< (@ 0x00000918) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM03_b; + }; + + union + { + __IOM uint32_t GWIDASAM13; /*!< (@ 0x0000091C) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM13_b; + }; + __IM uint32_t RESERVED18[24]; + + union + { + __IOM uint32_t GWIDACAM00; /*!< (@ 0x00000980) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM00_b; + }; + + union + { + __IOM uint32_t GWIDACAM10; /*!< (@ 0x00000984) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM10_b; + }; + + union + { + __IOM uint32_t GWIDACAM01; /*!< (@ 0x00000988) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM01_b; + }; + + union + { + __IOM uint32_t GWIDACAM11; /*!< (@ 0x0000098C) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM11_b; + }; + + union + { + __IOM uint32_t GWIDACAM02; /*!< (@ 0x00000990) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM02_b; + }; + + union + { + __IOM uint32_t GWIDACAM12; /*!< (@ 0x00000994) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM12_b; + }; + + union + { + __IOM uint32_t GWIDACAM03; /*!< (@ 0x00000998) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM03_b; + }; + + union + { + __IOM uint32_t GWIDACAM13; /*!< (@ 0x0000099C) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM13_b; + }; + __IM uint32_t RESERVED19[24]; + + union + { + __IOM uint32_t GWGRLC; /*!< (@ 0x00000A00) GWCA Global Rate Limiter Configuration Register + * (GWGRLC) */ + + struct + { + __IOM uint32_t GRLIV : 16; /*!< [15..0] GRLIV */ + __IOM uint32_t GRLE : 1; /*!< [16..16] GRLE */ + __IOM uint32_t GRLULRS : 1; /*!< [17..17] GRLULRS */ + uint32_t : 14; + } GWGRLC_b; + }; + + union + { + __IOM uint32_t GWGRLULC; /*!< (@ 0x00000A04) GWCA Global Rate Limiter Upper Limit Configuration + * Register (GWGRLULC) */ + + struct + { + __IOM uint32_t GRLUL : 24; /*!< [23..0] GRLUL */ + uint32_t : 8; + } GWGRLULC_b; + }; + __IM uint32_t RESERVED20[30]; + + union + { + __IOM uint32_t GWRLC0; /*!< (@ 0x00000A80) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC0_b; + }; + + union + { + __IOM uint32_t GWRLULC0; /*!< (@ 0x00000A84) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC0_b; + }; + + union + { + __IOM uint32_t GWRLC1; /*!< (@ 0x00000A88) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC1_b; + }; + + union + { + __IOM uint32_t GWRLULC1; /*!< (@ 0x00000A8C) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC1_b; + }; + + union + { + __IOM uint32_t GWRLC2; /*!< (@ 0x00000A90) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC2_b; + }; + + union + { + __IOM uint32_t GWRLULC2; /*!< (@ 0x00000A94) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC2_b; + }; + + union + { + __IOM uint32_t GWRLC3; /*!< (@ 0x00000A98) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC3_b; + }; + + union + { + __IOM uint32_t GWRLULC3; /*!< (@ 0x00000A9C) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC3_b; + }; + + union + { + __IOM uint32_t GWRLC4; /*!< (@ 0x00000AA0) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC4_b; + }; + + union + { + __IOM uint32_t GWRLULC4; /*!< (@ 0x00000AA4) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC4_b; + }; + + union + { + __IOM uint32_t GWRLC5; /*!< (@ 0x00000AA8) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC5_b; + }; + + union + { + __IOM uint32_t GWRLULC5; /*!< (@ 0x00000AAC) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC5_b; + }; + + union + { + __IOM uint32_t GWRLC6; /*!< (@ 0x00000AB0) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC6_b; + }; + + union + { + __IOM uint32_t GWRLULC6; /*!< (@ 0x00000AB4) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC6_b; + }; + + union + { + __IOM uint32_t GWRLC7; /*!< (@ 0x00000AB8) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC7_b; + }; + + union + { + __IOM uint32_t GWRLULC7; /*!< (@ 0x00000ABC) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC7_b; + }; + __IM uint32_t RESERVED21[48]; + + union + { + __IOM uint32_t GWIDPC; /*!< (@ 0x00000B80) GWCA Interrupt Delay Prescaler Configuration + * Register (GWIDPC) */ + + struct + { + __IOM uint32_t IDPV : 10; /*!< [9..0] IDPV */ + uint32_t : 22; + } GWIDPC_b; + }; + __IM uint32_t RESERVED22[31]; + + union + { + __IOM uint32_t GWIDC0; /*!< (@ 0x00000C00) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC0_b; + }; + + union + { + __IOM uint32_t GWIDC1; /*!< (@ 0x00000C04) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC1_b; + }; + + union + { + __IOM uint32_t GWIDC2; /*!< (@ 0x00000C08) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC2_b; + }; + + union + { + __IOM uint32_t GWIDC3; /*!< (@ 0x00000C0C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC3_b; + }; + + union + { + __IOM uint32_t GWIDC4; /*!< (@ 0x00000C10) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC4_b; + }; + + union + { + __IOM uint32_t GWIDC5; /*!< (@ 0x00000C14) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC5_b; + }; + + union + { + __IOM uint32_t GWIDC6; /*!< (@ 0x00000C18) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC6_b; + }; + + union + { + __IOM uint32_t GWIDC7; /*!< (@ 0x00000C1C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC7_b; + }; + + union + { + __IOM uint32_t GWIDC8; /*!< (@ 0x00000C20) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC8_b; + }; + + union + { + __IOM uint32_t GWIDC9; /*!< (@ 0x00000C24) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC9_b; + }; + + union + { + __IOM uint32_t GWIDC10; /*!< (@ 0x00000C28) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC10_b; + }; + + union + { + __IOM uint32_t GWIDC11; /*!< (@ 0x00000C2C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC11_b; + }; + + union + { + __IOM uint32_t GWIDC12; /*!< (@ 0x00000C30) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC12_b; + }; + + union + { + __IOM uint32_t GWIDC13; /*!< (@ 0x00000C34) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC13_b; + }; + + union + { + __IOM uint32_t GWIDC14; /*!< (@ 0x00000C38) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC14_b; + }; + + union + { + __IOM uint32_t GWIDC15; /*!< (@ 0x00000C3C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC15_b; + }; + + union + { + __IOM uint32_t GWIDC16; /*!< (@ 0x00000C40) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC16_b; + }; + + union + { + __IOM uint32_t GWIDC17; /*!< (@ 0x00000C44) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC17_b; + }; + + union + { + __IOM uint32_t GWIDC18; /*!< (@ 0x00000C48) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC18_b; + }; + + union + { + __IOM uint32_t GWIDC19; /*!< (@ 0x00000C4C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC19_b; + }; + + union + { + __IOM uint32_t GWIDC20; /*!< (@ 0x00000C50) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC20_b; + }; + + union + { + __IOM uint32_t GWIDC21; /*!< (@ 0x00000C54) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC21_b; + }; + + union + { + __IOM uint32_t GWIDC22; /*!< (@ 0x00000C58) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC22_b; + }; + + union + { + __IOM uint32_t GWIDC23; /*!< (@ 0x00000C5C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC23_b; + }; + + union + { + __IOM uint32_t GWIDC24; /*!< (@ 0x00000C60) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC24_b; + }; + + union + { + __IOM uint32_t GWIDC25; /*!< (@ 0x00000C64) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC25_b; + }; + + union + { + __IOM uint32_t GWIDC26; /*!< (@ 0x00000C68) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC26_b; + }; + + union + { + __IOM uint32_t GWIDC27; /*!< (@ 0x00000C6C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC27_b; + }; + + union + { + __IOM uint32_t GWIDC28; /*!< (@ 0x00000C70) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC28_b; + }; + + union + { + __IOM uint32_t GWIDC29; /*!< (@ 0x00000C74) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC29_b; + }; + + union + { + __IOM uint32_t GWIDC30; /*!< (@ 0x00000C78) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC30_b; + }; + + union + { + __IOM uint32_t GWIDC31; /*!< (@ 0x00000C7C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC31_b; + }; + + union + { + __IOM uint32_t GWIDC32; /*!< (@ 0x00000C80) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC32_b; + }; + + union + { + __IOM uint32_t GWIDC33; /*!< (@ 0x00000C84) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC33_b; + }; + + union + { + __IOM uint32_t GWIDC34; /*!< (@ 0x00000C88) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC34_b; + }; + + union + { + __IOM uint32_t GWIDC35; /*!< (@ 0x00000C8C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC35_b; + }; + + union + { + __IOM uint32_t GWIDC36; /*!< (@ 0x00000C90) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC36_b; + }; + + union + { + __IOM uint32_t GWIDC37; /*!< (@ 0x00000C94) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC37_b; + }; + + union + { + __IOM uint32_t GWIDC38; /*!< (@ 0x00000C98) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC38_b; + }; + + union + { + __IOM uint32_t GWIDC39; /*!< (@ 0x00000C9C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC39_b; + }; + + union + { + __IOM uint32_t GWIDC40; /*!< (@ 0x00000CA0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC40_b; + }; + + union + { + __IOM uint32_t GWIDC41; /*!< (@ 0x00000CA4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC41_b; + }; + + union + { + __IOM uint32_t GWIDC42; /*!< (@ 0x00000CA8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC42_b; + }; + + union + { + __IOM uint32_t GWIDC43; /*!< (@ 0x00000CAC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC43_b; + }; + + union + { + __IOM uint32_t GWIDC44; /*!< (@ 0x00000CB0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC44_b; + }; + + union + { + __IOM uint32_t GWIDC45; /*!< (@ 0x00000CB4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC45_b; + }; + + union + { + __IOM uint32_t GWIDC46; /*!< (@ 0x00000CB8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC46_b; + }; + + union + { + __IOM uint32_t GWIDC47; /*!< (@ 0x00000CBC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC47_b; + }; + + union + { + __IOM uint32_t GWIDC48; /*!< (@ 0x00000CC0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC48_b; + }; + + union + { + __IOM uint32_t GWIDC49; /*!< (@ 0x00000CC4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC49_b; + }; + + union + { + __IOM uint32_t GWIDC50; /*!< (@ 0x00000CC8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC50_b; + }; + + union + { + __IOM uint32_t GWIDC51; /*!< (@ 0x00000CCC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC51_b; + }; + + union + { + __IOM uint32_t GWIDC52; /*!< (@ 0x00000CD0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC52_b; + }; + + union + { + __IOM uint32_t GWIDC53; /*!< (@ 0x00000CD4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC53_b; + }; + + union + { + __IOM uint32_t GWIDC54; /*!< (@ 0x00000CD8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC54_b; + }; + + union + { + __IOM uint32_t GWIDC55; /*!< (@ 0x00000CDC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC55_b; + }; + + union + { + __IOM uint32_t GWIDC56; /*!< (@ 0x00000CE0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC56_b; + }; + + union + { + __IOM uint32_t GWIDC57; /*!< (@ 0x00000CE4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC57_b; + }; + + union + { + __IOM uint32_t GWIDC58; /*!< (@ 0x00000CE8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC58_b; + }; + + union + { + __IOM uint32_t GWIDC59; /*!< (@ 0x00000CEC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC59_b; + }; + + union + { + __IOM uint32_t GWIDC60; /*!< (@ 0x00000CF0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC60_b; + }; + + union + { + __IOM uint32_t GWIDC61; /*!< (@ 0x00000CF4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC61_b; + }; + + union + { + __IOM uint32_t GWIDC62; /*!< (@ 0x00000CF8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC62_b; + }; + + union + { + __IOM uint32_t GWIDC63; /*!< (@ 0x00000CFC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC63_b; + }; + + union + { + __IOM uint32_t GWIDC64; /*!< (@ 0x00000D00) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC64_b; + }; + __IM uint32_t RESERVED23[191]; + + union + { + __IOM uint32_t GWRDCN; /*!< (@ 0x00001000) GWCA Received Data Counter Register (GWRDCN) */ + + struct + { + __IOM uint32_t RDN : 32; /*!< [31..0] RDN */ + } GWRDCN_b; + }; + + union + { + __IOM uint32_t GWTDCN; /*!< (@ 0x00001004) GWCA Transmitted Data Counter Register (GWTDCN) */ + + struct + { + __IOM uint32_t TDN : 32; /*!< [31..0] TDN */ + } GWTDCN_b; + }; + + union + { + __IOM uint32_t GWTSCN; /*!< (@ 0x00001008) GWCA Timestamp Counter Register (GWTSCN) */ + + struct + { + __IOM uint32_t TN : 32; /*!< [31..0] TN */ + } GWTSCN_b; + }; + + union + { + __IOM uint32_t GWTSOVFECN; /*!< (@ 0x0000100C) GWCA Timestamp Overflow Error Counter Register + * (GWTSOVFECN) */ + + struct + { + __IOM uint32_t TSOVFEN : 16; /*!< [15..0] TSOVFEN */ + uint32_t : 16; + } GWTSOVFECN_b; + }; + + union + { + __IOM uint32_t GWUSMFSECN; /*!< (@ 0x00001010) GWCA Under Switch Minimum Frame Size Error Counter + * Register (GWUSMFSECN) */ + + struct + { + __IOM uint32_t USMFSEN : 16; /*!< [15..0] USMFSEN */ + uint32_t : 16; + } GWUSMFSECN_b; + }; + + union + { + __IOM uint32_t GWTFECN; /*!< (@ 0x00001014) GWCA TAG Filtering Error Counter Register (GWTFECN) */ + + struct + { + __IOM uint32_t TFEN : 16; /*!< [15..0] TFEN */ + uint32_t : 16; + } GWTFECN_b; + }; + + union + { + __IOM uint32_t GWSEQECN; /*!< (@ 0x00001018) GWCA Sequence Error Counter Register (GWSEQECN) */ + + struct + { + __IOM uint32_t SEQEN : 16; /*!< [15..0] SEQEN */ + uint32_t : 16; + } GWSEQECN_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t GWTXDNECN; /*!< (@ 0x00001020) GWCA TX Descriptor Number Error Counter Register + * (GWTXDNECN) */ + + struct + { + __IOM uint32_t TXDNEN : 16; /*!< [15..0] TXDNEN */ + uint32_t : 16; + } GWTXDNECN_b; + }; + + union + { + __IOM uint32_t GWFSECN; /*!< (@ 0x00001024) GWCA Frame Size Error Counter Register (GWFSECN) */ + + struct + { + __IOM uint32_t FSEN : 16; /*!< [15..0] FSEN */ + uint32_t : 16; + } GWFSECN_b; + }; + + union + { + __IOM uint32_t GWTDFECN; /*!< (@ 0x00001028) GWCA Timestamp Descriptor Full Error Counter + * Register (GWTDFECN) */ + + struct + { + __IOM uint32_t TDFEN : 16; /*!< [15..0] TDFEN */ + uint32_t : 16; + } GWTDFECN_b; + }; + + union + { + __IOM uint32_t GWTSDNECN; /*!< (@ 0x0000102C) GWCA Timestamp Descriptor Number Error Counter + * Register (GWTSDNECN) */ + + struct + { + __IOM uint32_t TSDNEN : 16; /*!< [15..0] TSDNEN */ + uint32_t : 16; + } GWTSDNECN_b; + }; + + union + { + __IOM uint32_t GWDQOECN; /*!< (@ 0x00001030) GWCA Descriptor Queue Overflow Error Counter + * Register (GWDQOECN) */ + + struct + { + __IOM uint32_t DQOEN : 16; /*!< [15..0] DQOEN */ + uint32_t : 16; + } GWDQOECN_b; + }; + + union + { + __IOM uint32_t GWDQSECN; /*!< (@ 0x00001034) GWCA Descriptor Queue Security Error Counter + * Register (GWDQSECN) */ + + struct + { + __IOM uint32_t DQSEN : 16; /*!< [15..0] DQSEN */ + uint32_t : 16; + } GWDQSECN_b; + }; + + union + { + __IOM uint32_t GWDFECN; /*!< (@ 0x00001038) GWCA Descriptor Full Error Counter Register (GWDFECN) */ + + struct + { + __IOM uint32_t DFEN : 16; /*!< [15..0] DFEN */ + uint32_t : 16; + } GWDFECN_b; + }; + + union + { + __IOM uint32_t GWDSECN; /*!< (@ 0x0000103C) GWCA Descriptor Security Error Counter Register + * (GWDSECN) */ + + struct + { + __IOM uint32_t DSEN : 16; /*!< [15..0] DSEN */ + uint32_t : 16; + } GWDSECN_b; + }; + + union + { + __IOM uint32_t GWDSZECN; /*!< (@ 0x00001040) GWCA Data Size Error Counter Register (GWDSZECN) */ + + struct + { + __IOM uint32_t DSZEN : 16; /*!< [15..0] DSZEN */ + uint32_t : 16; + } GWDSZECN_b; + }; + + union + { + __IOM uint32_t GWDCTECN; /*!< (@ 0x00001044) GWCA Descriptor Chain Type Error Counter Register + * (GWDCTECN) */ + + struct + { + __IOM uint32_t DCTEN : 16; /*!< [15..0] DCTEN */ + uint32_t : 16; + } GWDCTECN_b; + }; + + union + { + __IOM uint32_t GWRXDNECN; /*!< (@ 0x00001048) GWCA RX Descriptor Number Error Counter Register + * (GWRXDNECN) */ + + struct + { + __IOM uint32_t RXDNEN : 16; /*!< [15..0] RXDNEN */ + uint32_t : 16; + } GWRXDNECN_b; + }; + __IM uint32_t RESERVED25[45]; + __IOM uint32_t GWDIS0; /*!< (@ 0x00001100) GWCA Data Interrupt Status Register i (GWDISi) + * (i = 0, 1) */ + __IOM uint32_t GWDIE0; /*!< (@ 0x00001104) GWCA Data Interrupt Enable Register i (GWDIEi) + * (i = 0, 1) */ + __IOM uint32_t GWDID0; /*!< (@ 0x00001108) GWCA Data Interrupt Disable Register i (GWDIDi) + * (i = 0, 1) */ + __IOM uint32_t GWDIDS0; /*!< (@ 0x0000110C) GWCA Data Interrupt Delayed Status Register i + * (GWDIDSi) (i = 0, 1) */ + __IOM uint32_t GWDIS1; /*!< (@ 0x00001110) GWCA Data Interrupt Status Register i (GWDISi) + * (i = 0, 1) */ + __IOM uint32_t GWDIE1; /*!< (@ 0x00001114) GWCA Data Interrupt Enable Register i (GWDIEi) + * (i = 0, 1) */ + __IOM uint32_t GWDID1; /*!< (@ 0x00001118) GWCA Data Interrupt Disable Register i (GWDIDi) + * (i = 0, 1) */ + __IOM uint32_t GWDIDS1; /*!< (@ 0x0000111C) GWCA Data Interrupt Delayed Status Register i + * (GWDIDSi) (i = 0, 1) */ + __IM uint32_t RESERVED26[24]; + + union + { + __IOM uint32_t GWTSDIS; /*!< (@ 0x00001180) GWCA Timestamp Data Interrupt Status Register + * (GWTSDIS) */ + + struct + { + __IOM uint32_t TSDIS0 : 1; /*!< [0..0] TSDIS0 */ + __IOM uint32_t TSDIS1 : 1; /*!< [1..1] TSDIS1 */ + uint32_t : 30; + } GWTSDIS_b; + }; + + union + { + __IOM uint32_t GWTSDIE; /*!< (@ 0x00001184) GWCA Timestamp Data Interrupt Enable Register + * (GWTSDIE) */ + + struct + { + __IOM uint32_t TSDIE0 : 1; /*!< [0..0] TSDIE0 */ + __IOM uint32_t TSDIE1 : 1; /*!< [1..1] TSDIE1 */ + uint32_t : 30; + } GWTSDIE_b; + }; + + union + { + __IOM uint32_t GWTSDID; /*!< (@ 0x00001188) GWCA Timestamp Data Interrupt Disable Register + * (GWTSDID) */ + + struct + { + __IOM uint32_t TSDID0 : 1; /*!< [0..0] TSDID0 */ + __IOM uint32_t TSDID1 : 1; /*!< [1..1] TSDID1 */ + uint32_t : 30; + } GWTSDID_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IOM uint32_t GWEIS0; /*!< (@ 0x00001190) GWCA Error Interrupt Status Register 0 (GWEIS0) */ + + struct + { + __IOM uint32_t AES : 1; /*!< [0..0] AES */ + __IOM uint32_t DECCES : 1; /*!< [1..1] DECCES */ + __IOM uint32_t TECCES : 1; /*!< [2..2] TECCES */ + __IOM uint32_t PECCES : 1; /*!< [3..3] PECCES */ + __IOM uint32_t DSECCES : 1; /*!< [4..4] DSECCES */ + __IOM uint32_t MECCES : 1; /*!< [5..5] MECCES */ + __IOM uint32_t AECCES : 1; /*!< [6..6] AECCES */ + __IOM uint32_t TSECCES : 1; /*!< [7..7] TSECCES */ + __IOM uint32_t L23UECCES : 1; /*!< [8..8] L23UECCES */ + __IOM uint32_t TSOVFES : 1; /*!< [9..9] TSOVFES */ + __IOM uint32_t USMFSES : 1; /*!< [10..10] USMFSES */ + __IOM uint32_t TFES : 1; /*!< [11..11] TFES */ + __IOM uint32_t SEQES : 1; /*!< [12..12] SEQES */ + uint32_t : 1; + __IOM uint32_t TXDNES : 1; /*!< [14..14] TXDNES */ + __IOM uint32_t TSHES : 1; /*!< [15..15] TSHES */ + __IOM uint32_t FSES0 : 1; /*!< [16..16] FSES0 */ + __IOM uint32_t FSES1 : 1; /*!< [17..17] FSES1 */ + __IOM uint32_t FSES2 : 1; /*!< [18..18] FSES2 */ + __IOM uint32_t FSES3 : 1; /*!< [19..19] FSES3 */ + __IOM uint32_t FSES4 : 1; /*!< [20..20] FSES4 */ + __IOM uint32_t FSES5 : 1; /*!< [21..21] FSES5 */ + __IOM uint32_t FSES6 : 1; /*!< [22..22] FSES6 */ + __IOM uint32_t FSES7 : 1; /*!< [23..23] FSES7 */ + __IOM uint32_t TDFES0 : 1; /*!< [24..24] TDFES0 */ + __IOM uint32_t TDFES1 : 1; /*!< [25..25] TDFES1 */ + uint32_t : 2; + __IOM uint32_t TSDNES0 : 1; /*!< [28..28] TSDNES0 */ + __IOM uint32_t TSDNES1 : 1; /*!< [29..29] TSDNES1 */ + uint32_t : 2; + } GWEIS0_b; + }; + + union + { + __IOM uint32_t GWEIE0; /*!< (@ 0x00001194) GWCA Error Interrupt Enable Register 0 (GWEIE0) */ + + struct + { + __IOM uint32_t AEE : 1; /*!< [0..0] AEE */ + __IOM uint32_t DECCEE : 1; /*!< [1..1] DECCEE */ + __IOM uint32_t TECCEE : 1; /*!< [2..2] TECCEE */ + __IOM uint32_t PECCEE : 1; /*!< [3..3] PECCEE */ + __IOM uint32_t DSECCEE : 1; /*!< [4..4] DSECCEE */ + __IOM uint32_t MECCEE : 1; /*!< [5..5] MECCEE */ + __IOM uint32_t AECCEE : 1; /*!< [6..6] AECCEE */ + __IOM uint32_t TSECCEE : 1; /*!< [7..7] TSECCEE */ + __IOM uint32_t L23UECCEE : 1; /*!< [8..8] L23UECCEE */ + __IOM uint32_t TSOVFEE : 1; /*!< [9..9] TSOVFEE */ + __IOM uint32_t USMFSEE : 1; /*!< [10..10] USMFSEE */ + __IOM uint32_t TFEE : 1; /*!< [11..11] TFEE */ + __IOM uint32_t SEQEE : 1; /*!< [12..12] SEQEE */ + uint32_t : 1; + __IOM uint32_t TXDNEE : 1; /*!< [14..14] TXDNEE */ + __IOM uint32_t TSHEE : 1; /*!< [15..15] TSHEE */ + __IOM uint32_t FSEE0 : 1; /*!< [16..16] FSEE0 */ + __IOM uint32_t FSEE1 : 1; /*!< [17..17] FSEE1 */ + __IOM uint32_t FSEE2 : 1; /*!< [18..18] FSEE2 */ + __IOM uint32_t FSEE3 : 1; /*!< [19..19] FSEE3 */ + __IOM uint32_t FSEE4 : 1; /*!< [20..20] FSEE4 */ + __IOM uint32_t FSEE5 : 1; /*!< [21..21] FSEE5 */ + __IOM uint32_t FSEE6 : 1; /*!< [22..22] FSEE6 */ + __IOM uint32_t FSEE7 : 1; /*!< [23..23] FSEE7 */ + __IOM uint32_t TDFEE0 : 1; /*!< [24..24] TDFEE0 */ + __IOM uint32_t TDFEE1 : 1; /*!< [25..25] TDFEE1 */ + uint32_t : 2; + __IOM uint32_t TSDNEE0 : 1; /*!< [28..28] TSDNEE0 */ + __IOM uint32_t TSDNEE1 : 1; /*!< [29..29] TSDNEE1 */ + uint32_t : 2; + } GWEIE0_b; + }; + + union + { + __IOM uint32_t GWEID0; /*!< (@ 0x00001198) GWCA Error Interrupt Disable Register 0 (GWEID0) */ + + struct + { + __IOM uint32_t AED : 1; /*!< [0..0] AED */ + __IOM uint32_t TECCED : 1; /*!< [1..1] TECCED */ + __IOM uint32_t DECCED : 1; /*!< [2..2] DECCED */ + __IOM uint32_t PECCED : 1; /*!< [3..3] PECCED */ + __IOM uint32_t DSECCED : 1; /*!< [4..4] DSECCED */ + __IOM uint32_t MECCED : 1; /*!< [5..5] MECCED */ + __IOM uint32_t AECCED : 1; /*!< [6..6] AECCED */ + __IOM uint32_t TSECCED : 1; /*!< [7..7] TSECCED */ + __IOM uint32_t L23UECCED : 1; /*!< [8..8] L23UECCED */ + __IOM uint32_t TSOVFED : 1; /*!< [9..9] TSOVFED */ + __IOM uint32_t USMFSED : 1; /*!< [10..10] USMFSED */ + __IOM uint32_t TFED : 1; /*!< [11..11] TFED */ + __IOM uint32_t SEQED : 1; /*!< [12..12] SEQED */ + __IOM uint32_t IIPED : 1; /*!< [13..13] IIPED */ + __IOM uint32_t TXDNED : 1; /*!< [14..14] TXDNED */ + __IOM uint32_t TSHED : 1; /*!< [15..15] TSHED */ + __IOM uint32_t FSED0 : 1; /*!< [16..16] FSED0 */ + __IOM uint32_t FSED1 : 1; /*!< [17..17] FSED1 */ + __IOM uint32_t FSED2 : 1; /*!< [18..18] FSED2 */ + __IOM uint32_t FSED3 : 1; /*!< [19..19] FSED3 */ + __IOM uint32_t FSED4 : 1; /*!< [20..20] FSED4 */ + __IOM uint32_t FSED5 : 1; /*!< [21..21] FSED5 */ + __IOM uint32_t FSED6 : 1; /*!< [22..22] FSED6 */ + __IOM uint32_t FSED7 : 1; /*!< [23..23] FSED7 */ + __IOM uint32_t TDFED0 : 1; /*!< [24..24] TDFED0 */ + __IOM uint32_t TDFED1 : 1; /*!< [25..25] TDFED1 */ + uint32_t : 2; + __IOM uint32_t TSDNED0 : 1; /*!< [28..28] TSDNED0 */ + __IOM uint32_t TSDNED1 : 1; /*!< [29..29] TSDNED1 */ + uint32_t : 2; + } GWEID0_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t GWEIS1; /*!< (@ 0x000011A0) GWCA Error Interrupt Status Register 1 (GWEIS1) */ + + struct + { + __IOM uint32_t DQOES0 : 1; /*!< [0..0] DQOES0 */ + __IOM uint32_t DQOES1 : 1; /*!< [1..1] DQOES1 */ + __IOM uint32_t DQOES2 : 1; /*!< [2..2] DQOES2 */ + __IOM uint32_t DQOES3 : 1; /*!< [3..3] DQOES3 */ + __IOM uint32_t DQOES4 : 1; /*!< [4..4] DQOES4 */ + __IOM uint32_t DQOES5 : 1; /*!< [5..5] DQOES5 */ + __IOM uint32_t DQOES6 : 1; /*!< [6..6] DQOES6 */ + __IOM uint32_t DQOES7 : 1; /*!< [7..7] DQOES7 */ + uint32_t : 8; + __IOM uint32_t DQSES0 : 1; /*!< [16..16] DQSES0 */ + __IOM uint32_t DQSES1 : 1; /*!< [17..17] DQSES1 */ + __IOM uint32_t DQSES2 : 1; /*!< [18..18] DQSES2 */ + __IOM uint32_t DQSES3 : 1; /*!< [19..19] DQSES3 */ + __IOM uint32_t DQSES4 : 1; /*!< [20..20] DQSES4 */ + __IOM uint32_t DQSES5 : 1; /*!< [21..21] DQSES5 */ + __IOM uint32_t DQSES6 : 1; /*!< [22..22] DQSES6 */ + __IOM uint32_t DQSES7 : 1; /*!< [23..23] DQSES7 */ + uint32_t : 8; + } GWEIS1_b; + }; + + union + { + __IOM uint32_t GWEIE1; /*!< (@ 0x000011A4) GWCA Error Interrupt Enable Register 1 (GWEIE1) */ + + struct + { + __IOM uint32_t DQOEE0 : 1; /*!< [0..0] DQOEE0 */ + __IOM uint32_t DQOEE1 : 1; /*!< [1..1] DQOEE1 */ + __IOM uint32_t DQOEE2 : 1; /*!< [2..2] DQOEE2 */ + __IOM uint32_t DQOEE3 : 1; /*!< [3..3] DQOEE3 */ + __IOM uint32_t DQOEE4 : 1; /*!< [4..4] DQOEE4 */ + __IOM uint32_t DQOEE5 : 1; /*!< [5..5] DQOEE5 */ + __IOM uint32_t DQOEE6 : 1; /*!< [6..6] DQOEE6 */ + __IOM uint32_t DQOEE7 : 1; /*!< [7..7] DQOEE7 */ + uint32_t : 8; + __IOM uint32_t DQSEE0 : 1; /*!< [16..16] DQSEE0 */ + __IOM uint32_t DQSEE1 : 1; /*!< [17..17] DQSEE1 */ + __IOM uint32_t DQSEE2 : 1; /*!< [18..18] DQSEE2 */ + __IOM uint32_t DQSEE3 : 1; /*!< [19..19] DQSEE3 */ + __IOM uint32_t DQSEE4 : 1; /*!< [20..20] DQSEE4 */ + __IOM uint32_t DQSEE5 : 1; /*!< [21..21] DQSEE5 */ + __IOM uint32_t DQSEE6 : 1; /*!< [22..22] DQSEE6 */ + __IOM uint32_t DQSEE7 : 1; /*!< [23..23] DQSEE7 */ + uint32_t : 8; + } GWEIE1_b; + }; + + union + { + __IOM uint32_t GWEID1; /*!< (@ 0x000011A8) GWCA Error Interrupt Disable Register 1 (GWEID1) */ + + struct + { + __IOM uint32_t DQOED0 : 1; /*!< [0..0] DQOED0 */ + __IOM uint32_t DQOED1 : 1; /*!< [1..1] DQOED1 */ + __IOM uint32_t DQOED2 : 1; /*!< [2..2] DQOED2 */ + __IOM uint32_t DQOED3 : 1; /*!< [3..3] DQOED3 */ + __IOM uint32_t DQOED4 : 1; /*!< [4..4] DQOED4 */ + __IOM uint32_t DQOED5 : 1; /*!< [5..5] DQOED5 */ + __IOM uint32_t DQOED6 : 1; /*!< [6..6] DQOED6 */ + __IOM uint32_t DQOED7 : 1; /*!< [7..7] DQOED7 */ + uint32_t : 8; + __IOM uint32_t DQSED0 : 1; /*!< [16..16] DQSED0 */ + __IOM uint32_t DQSED1 : 1; /*!< [17..17] DQSED1 */ + __IOM uint32_t DQSED2 : 1; /*!< [18..18] DQSED2 */ + __IOM uint32_t DQSED3 : 1; /*!< [19..19] DQSED3 */ + __IOM uint32_t DQSED4 : 1; /*!< [20..20] DQSED4 */ + __IOM uint32_t DQSED5 : 1; /*!< [21..21] DQSED5 */ + __IOM uint32_t DQSED6 : 1; /*!< [22..22] DQSED6 */ + __IOM uint32_t DQSED7 : 1; /*!< [23..23] DQSED7 */ + uint32_t : 8; + } GWEID1_b; + }; + __IM uint32_t RESERVED29[21]; + __IOM uint32_t GWEIS20; /*!< (@ 0x00001200) GWCA Error Interrupt Status Register 2i (GWEIS2i) + * (i = 0, 1) */ + __IOM uint32_t GWEIE20; /*!< (@ 0x00001204) GWCA Error Interrupt Enable Register 2i (GWEIE2i) + * (i = 0, 1) */ + __IOM uint32_t GWEID20; /*!< (@ 0x00001208) GWCA Error Interrupt Disable Register 2i (GWEID2i) + * (i = 0, 1) */ + __IM uint32_t RESERVED30; + __IOM uint32_t GWEIS21; /*!< (@ 0x00001210) GWCA Error Interrupt Status Register 2i (GWEIS2i) + * (i = 0, 1) */ + __IOM uint32_t GWEIE21; /*!< (@ 0x00001214) GWCA Error Interrupt Enable Register 2i (GWEIE2i) + * (i = 0, 1) */ + __IOM uint32_t GWEID21; /*!< (@ 0x00001218) GWCA Error Interrupt Disable Register 2i (GWEID2i) + * (i = 0, 1) */ + __IM uint32_t RESERVED31[25]; + + union + { + __IOM uint32_t GWEIS3; /*!< (@ 0x00001280) GWCA Error Interrupt Status Register 3 (GWEIS3) */ + + struct + { + __IOM uint32_t IAOES0 : 1; /*!< [0..0] IAOES0 */ + __IOM uint32_t IAOES1 : 1; /*!< [1..1] IAOES1 */ + __IOM uint32_t IAOES2 : 1; /*!< [2..2] IAOES2 */ + __IOM uint32_t IAOES3 : 1; /*!< [3..3] IAOES3 */ + __IOM uint32_t IAOES4 : 1; /*!< [4..4] IAOES4 */ + uint32_t : 27; + } GWEIS3_b; + }; + + union + { + __IOM uint32_t GWEIE3; /*!< (@ 0x00001284) GWCA Error Interrupt Enable Register 3 (GWEIE3) */ + + struct + { + __IOM uint32_t IAOEE0 : 1; /*!< [0..0] IAOEE0 */ + __IOM uint32_t IAOEE1 : 1; /*!< [1..1] IAOEE1 */ + __IOM uint32_t IAOEE2 : 1; /*!< [2..2] IAOEE2 */ + __IOM uint32_t IAOEE3 : 1; /*!< [3..3] IAOEE3 */ + __IOM uint32_t IAOEE4 : 1; /*!< [4..4] IAOEE4 */ + uint32_t : 27; + } GWEIE3_b; + }; + + union + { + __IOM uint32_t GWEID3; /*!< (@ 0x00001288) GWCA Error Interrupt Disable Register 3 (GWEID3) */ + + struct + { + __IOM uint32_t IAOED0 : 1; /*!< [0..0] IAOED0 */ + __IOM uint32_t IAOED1 : 1; /*!< [1..1] IAOED1 */ + __IOM uint32_t IAOED2 : 1; /*!< [2..2] IAOED2 */ + __IOM uint32_t IAOED3 : 1; /*!< [3..3] IAOED3 */ + __IOM uint32_t IAOED4 : 1; /*!< [4..4] IAOED4 */ + uint32_t : 27; + } GWEID3_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t GWEIS4; /*!< (@ 0x00001290) GWCA Error Interrupt Status Register 4 (GWEIS4) */ + + struct + { + __IOM uint32_t DSSES : 1; /*!< [0..0] DSSES */ + __IOM uint32_t DSSEIOS : 1; /*!< [1..1] DSSEIOS */ + uint32_t : 6; + __IOM uint32_t DSSECN : 6; /*!< [13..8] DSSECN */ + uint32_t : 2; + __IOM uint32_t DSES : 1; /*!< [16..16] DSES */ + __IOM uint32_t DSEIOS : 1; /*!< [17..17] DSEIOS */ + uint32_t : 6; + __IOM uint32_t DSECN : 6; /*!< [29..24] DSECN */ + uint32_t : 2; + } GWEIS4_b; + }; + + union + { + __IOM uint32_t GWEIE4; /*!< (@ 0x00001294) GWCA Error Interrupt Enable Register 4 (GWEIE4) */ + + struct + { + __IOM uint32_t DSSEE : 1; /*!< [0..0] DSSEE */ + __IOM uint32_t DSSEIOE : 1; /*!< [1..1] DSSEIOE */ + uint32_t : 14; + __IOM uint32_t DSEE : 1; /*!< [16..16] DSEE */ + __IOM uint32_t DSEIOE : 1; /*!< [17..17] DSEIOE */ + uint32_t : 14; + } GWEIE4_b; + }; + + union + { + __IOM uint32_t GWEID4; /*!< (@ 0x00001298) GWCA Error Interrupt Disable Register 4 (GWEID4) */ + + struct + { + __IOM uint32_t DSSED : 1; /*!< [0..0] DSSED */ + __IOM uint32_t DSSEIOD : 1; /*!< [1..1] DSSEIOD */ + uint32_t : 14; + __IOM uint32_t DSED : 1; /*!< [16..16] DSED */ + __IOM uint32_t DSEIOD : 1; /*!< [17..17] DSEIOD */ + uint32_t : 14; + } GWEID4_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t GWEIS5; /*!< (@ 0x000012A0) GWCA Error Interrupt Status Register 5 (GWEIS5) */ + + struct + { + __IOM uint32_t DCTES : 1; /*!< [0..0] DCTES */ + __IOM uint32_t DCTEIOS : 1; /*!< [1..1] DCTEIOS */ + uint32_t : 6; + __IOM uint32_t DCTECN : 6; /*!< [13..8] DCTECN */ + uint32_t : 2; + __IOM uint32_t RXDNES : 1; /*!< [16..16] RXDNES */ + __IOM uint32_t RXDNEIOS : 1; /*!< [17..17] RXDNEIOS */ + uint32_t : 14; + } GWEIS5_b; + }; + + union + { + __IOM uint32_t GWEIE5; /*!< (@ 0x000012A4) GWCA Error Interrupt Enable Register 5 (GWEIE5) */ + + struct + { + __IOM uint32_t DCTEE : 1; /*!< [0..0] DCTEE */ + __IOM uint32_t DCTEIOE : 1; /*!< [1..1] DCTEIOE */ + uint32_t : 14; + __IOM uint32_t RXDNEE : 1; /*!< [16..16] RXDNEE */ + __IOM uint32_t RXDNEIOE : 1; /*!< [17..17] RXDNEIOE */ + uint32_t : 14; + } GWEIE5_b; + }; + + union + { + __IOM uint32_t GWEID5; /*!< (@ 0x000012A8) GWCA Error Interrupt Disable Register 5 (GWEID5) */ + + struct + { + __IOM uint32_t DCTED : 1; /*!< [0..0] DCTED */ + __IOM uint32_t DCTEIOD : 1; /*!< [1..1] DCTEIOD */ + uint32_t : 13; + __IOM uint32_t RXDNED : 1; /*!< [15..15] RXDNED */ + __IOM uint32_t RXDNEIOD : 1; /*!< [16..16] RXDNEIOD */ + uint32_t : 15; + } GWEID5_b; + }; +} R_GWCA0_Type; /*!< Size = 4780 (0x12ac) */ + +/* =========================================================================================================================== */ +/* ================ R_IPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Inter-Processor Communication (R_IPC) + */ + +typedef struct /*!< (@ 0x40020000) R_IPC Structure */ +{ + union + { + __IOM uint32_t IPCSEM[16]; /*!< (@ 0x00000000) Semaphore Registers */ + + struct + { + __IOM uint32_t LOCK : 1; /*!< [0..0] Indicates the shared resource is locked */ + uint32_t : 31; + } IPCSEM_b[16]; + }; + __IM uint32_t RESERVED[16]; + __IOM R_IPC_IPCNMI_Type IPC0NMI; /*!< (@ 0x00000080) Inter-Processor NMI Registers */ + __IOM R_IPC_IPCNMI_Type IPC1NMI; /*!< (@ 0x00000090) Inter-Processor NMI Registers */ + __IM uint32_t RESERVED1[8]; + __IOM R_IPC_IPC_Type IPC0; /*!< (@ 0x000000C0) Inter-Processor Registers */ + __IOM R_IPC_IPC_Type IPC1; /*!< (@ 0x00000100) Inter-Processor Registers */ +} R_IPC_Type; /*!< Size = 320 (0x140) */ + +/* =========================================================================================================================== */ +/* ================ R_MFWD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Message Forwarding Engine (R_MFWD) + */ + +typedef struct /*!< (@ 0x403C0000) R_MFWD Structure */ +{ + union + { + __IOM uint32_t FWGC; /*!< (@ 0x00000000) General Configuration Register */ + + struct + { + __IOM uint32_t SVM : 2; /*!< [1..0] Switch VLAN Mode */ + uint32_t : 30; + } FWGC_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t FWTTC0; /*!< (@ 0x00000010) TAG TPID Configuration Register 0 */ + + struct + { + __IOM uint32_t CTT : 16; /*!< [15..0] C-TAG TPID */ + __IOM uint32_t STT : 16; /*!< [31..16] S-TAG TPID */ + } FWTTC0_b; + }; + + union + { + __IOM uint32_t FWTTC1; /*!< (@ 0x00000014) TAG TPID Configuration Register 1 */ + + struct + { + __IOM uint32_t RTT : 16; /*!< [15..0] R-TAG TPID */ + uint32_t : 16; + } FWTTC1_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t FWCEPTC; /*!< (@ 0x00000020) CPU Exceptional Path Target Configuration Register */ + + struct + { + __IOM uint32_t EPCSD : 7; /*!< [6..0] Exceptional Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t EPIPV : 3; /*!< [14..12] Exceptional Path Internal Priority Value */ + uint32_t : 1; + __IOM uint32_t EPCS : 2; /*!< [17..16] Exceptional Path CPU Select */ + uint32_t : 6; + __IOM uint32_t EPSL : 1; /*!< [24..24] Exceptional Path Security Level */ + uint32_t : 7; + } FWCEPTC_b; + }; + + union + { + __IOM uint32_t FWCEPRC0; /*!< (@ 0x00000024) CPU Exceptional Path Reason Configuration Register + * 0 */ + + struct + { + __IOM uint32_t EPHYEEF : 1; /*!< [0..0] Ethernet PHY Error Exceptional Forwarding */ + __IOM uint32_t EPCRCEEF : 1; /*!< [1..1] Ethernet PCH CRC Error Exceptional Forwarding */ + __IOM uint32_t ENIBEEF : 1; /*!< [2..2] Ethernet Nibble Error Exceptional Forwarding */ + __IOM uint32_t EFCSEEF : 1; /*!< [3..3] Ethernet FCS Error Exceptional Forwarding */ + __IOM uint32_t EFFMEEF : 1; /*!< [4..4] Ethernet Final Fragment Missing Error Exceptional Forwarding */ + __IOM uint32_t ECFSEEF : 1; /*!< [5..5] Ethernet C-Fragment SMD Error Exceptional Forwarding */ + __IOM uint32_t ECFFCEEF : 1; /*!< [6..6] Ethernet C-Fragment FRAG_COUNT Error Exceptional Forwarding */ + __IOM uint32_t ERFFEF : 1; /*!< [7..7] Ethernet RMAC Frame Filtered Exceptional Forwarding */ + __IOM uint32_t ERPOOEF : 1; /*!< [8..8] Ethernet Reception Partially Out of Operation Exceptional + * Forwarding */ + __IOM uint32_t EBOEEF : 1; /*!< [9..9] Ethernet Buffer Overflow Error Exceptional Forwarding */ + __IOM uint32_t EUEEF : 1; /*!< [10..10] Ethernet Undersize Error Exceptional Forwarding */ + __IOM uint32_t EOEEF : 1; /*!< [11..11] Ethernet Oversize Error Exceptional Forwarding */ + __IOM uint32_t ETFEF : 1; /*!< [12..12] Ethernet TAG Filtering Exceptional Forwarding */ + uint32_t : 3; + __IOM uint32_t GAREEEF : 1; /*!< [16..16] GWCA AXI RAM ECC Error Exceptional Forwarding */ + __IOM uint32_t GAXEEF : 1; /*!< [17..17] GWCA AXI Error Exceptional Forwarding */ + __IOM uint32_t GSEQEEF : 1; /*!< [18..18] GWCA Sequence Error Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t GTFEF : 1; /*!< [20..20] GWCA TAG Filtering Exceptional Forwarding */ + __IOM uint32_t GDNEEF : 1; /*!< [21..21] GWCA Descriptor Number Error Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t DDEEF : 1; /*!< [24..24] Direct Descriptor Error Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t DDFSFEF : 1; /*!< [26..26] Direct Descriptor Format Security Filtering Exceptional + * Forwarding */ + uint32_t : 5; + } FWCEPRC0_b; + }; + + union + { + __IOM uint32_t FWCEPRC1; /*!< (@ 0x00000028) CPU Exceptional Path Reason Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FMSDUFEF : 1; /*!< [0..0] MSDU Filtering Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t FMTRFEF : 1; /*!< [2..2] Meter Filtering Exceptional Forwarding */ + uint32_t : 5; + __IOM uint32_t FIFFEF : 1; /*!< [8..8] Individual FRER Filtering Exceptional Forwarding */ + __IOM uint32_t FSFFEF : 1; /*!< [9..9] Sequence FRER Filtering Exceptional Forwarding */ + uint32_t : 22; + } FWCEPRC1_b; + }; + + union + { + __IOM uint32_t FWCEPRC2; /*!< (@ 0x0000002C) CPU Exceptional Path Reason Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FLTHUFEF : 1; /*!< [0..0] Layer 3 Unknown Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDMACUFEF : 1; /*!< [3..3] Destination MAC Unknown Filtering Exceptional Forwarding */ + __IOM uint32_t FSMACUFEF : 1; /*!< [4..4] Source MAC Unknown Filtering Exceptional Forwarding */ + __IOM uint32_t FVLANUFEF : 1; /*!< [5..5] VLAN Unknown Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDDNTFEF : 1; /*!< [8..8] Direct Descriptor No Target Filtering Exceptional Forwarding */ + __IOM uint32_t FLTHNTFEF : 1; /*!< [9..9] Layer 3 No Target Filtering Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t FLTWNTFEF : 1; /*!< [11..11] Layer 2 No Target Filtering Exceptional Forwarding */ + __IOM uint32_t FPBNTFEF : 1; /*!< [12..12] Port Based No Target Filtering Exceptional Forwarding */ + uint32_t : 3; + __IOM uint32_t FLTHSLFEF : 1; /*!< [16..16] Layer 3 Source Lock Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDMACSLFEF : 1; /*!< [19..19] Destination MAC Source Lock Filtering Exceptional Forwarding */ + __IOM uint32_t FSMACSLFEF : 1; /*!< [20..20] Source MAC Source Lock Filtering Exceptional Forwarding */ + __IOM uint32_t FVLANSLFEF : 1; /*!< [21..21] VLAN Source Lock Filtering Exceptional Forwarding */ + uint32_t : 4; + __IOM uint32_t FWMFEF : 1; /*!< [26..26] Watermark Filtering Exceptional Forwarding */ + uint32_t : 5; + } FWCEPRC2_b; + }; + + union + { + __IOM uint32_t FWCLPTC; /*!< (@ 0x00000030) CPU Learning Path Target Configuration Register */ + + struct + { + __IOM uint32_t LPCSD : 7; /*!< [6..0] Learning Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t LPIPV : 3; /*!< [14..12] Learning Path Internal Priority Value */ + uint32_t : 1; + __IOM uint32_t LPCS : 2; /*!< [17..16] Learning Path CPU Select */ + uint32_t : 6; + __IOM uint32_t LPSL : 1; /*!< [24..24] Learning Path Security Level */ + uint32_t : 7; + } FWCLPTC_b; + }; + + union + { + __IOM uint32_t FWCLPRC; /*!< (@ 0x00000034) CPU Learning Path Reason Configuration Register */ + + struct + { + __IOM uint32_t USIDLF : 1; /*!< [0..0] Unknown Stream ID Learning Forwarding */ + uint32_t : 3; + __IOM uint32_t UDMACLF : 1; /*!< [4..4] Unknown Destination MAC Learning Forwarding */ + __IOM uint32_t USMACLF : 1; /*!< [5..5] Unknown Source MAC Learning Forwarding */ + __IOM uint32_t UPSMACLF : 1; /*!< [6..6] Unknown Port for Source MAC Learning Forwarding */ + __IOM uint32_t UVLANLF : 1; /*!< [7..7] Unknown VLAN Learning Forwarding */ + uint32_t : 24; + } FWCLPRC_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t FWCMPTC; /*!< (@ 0x00000040) CPU Mirroring Path Target Configuration Register */ + + struct + { + __IOM uint32_t CMPCSD : 7; /*!< [6..0] CPU Mirroring Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t CMPIPV : 3; /*!< [14..12] CPU Mirroring Path Internal Priority Value */ + __IOM uint32_t CMPIPU : 1; /*!< [15..15] CPU Mirroring Path Internal Priority Update */ + __IOM uint32_t CMPCS : 2; /*!< [17..16] CPU Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t CMPSL : 1; /*!< [24..24] CPU Mirroring Path Security Level */ + uint32_t : 7; + } FWCMPTC_b; + }; + + union + { + __IOM uint32_t FWEMPTC; /*!< (@ 0x00000044) Ethernet Mirroring Path Target Configuration + * Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t EMPIPV : 3; /*!< [14..12] Ethernet Mirroring Path Internal Priority Value */ + __IOM uint32_t EMPIPU : 1; /*!< [15..15] Ethernet Mirroring Path Internal Priority Update */ + __IOM uint32_t EMPPS : 2; /*!< [17..16] Ethernet Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t EMPSL : 1; /*!< [24..24] Ethernet Mirroring Path Security Level */ + uint32_t : 7; + } FWEMPTC_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t FWSDMPTC; /*!< (@ 0x00000050) Source-Destination Mirroring Path Target Configuration + * Register */ + + struct + { + __IOM uint32_t SDMPCSD : 7; /*!< [6..0] Source-Destination Mirroring Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t SDMPIPV : 3; /*!< [14..12] Source-Destination Mirroring Path Internal Priority + * Value */ + __IOM uint32_t SDMPIPU : 1; /*!< [15..15] Source-Destination Mirroring Path Internal Priority + * Update */ + __IOM uint32_t SDMPPS : 2; /*!< [17..16] Source-Destination Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t SDMPSL : 1; /*!< [24..24] Source-Destination Mirroring Path Security Level */ + uint32_t : 7; + } FWSDMPTC_b; + }; + + union + { + __IOM uint32_t FWSDMPVC; /*!< (@ 0x00000054) Source-Destination Mirroring Path Vector Configuration + * Register */ + + struct + { + __IOM uint32_t SDMDV : 7; /*!< [6..0] Source-Destination Mirroring Destination Vector */ + uint32_t : 9; + __IOM uint32_t SDMSV : 7; /*!< [22..16] Source-Destination Mirroring Source Vector */ + uint32_t : 9; + } FWSDMPVC_b; + }; + __IM uint32_t RESERVED4[10]; + + union + { + __IOM uint32_t FWLBWMC0; /*!< (@ 0x00000080) Level Based Watermark Configuration Register + * 0 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC0_b; + }; + + union + { + __IOM uint32_t FWLBWMC1; /*!< (@ 0x00000084) Level Based Watermark Configuration Register + * 1 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC1_b; + }; + + union + { + __IOM uint32_t FWLBWMC2; /*!< (@ 0x00000088) Level Based Watermark Configuration Register + * 2 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC2_b; + }; + __IM uint32_t RESERVED5[29]; + + union + { + __IOM uint32_t FWPC00; /*!< (@ 0x00000100) Port Configuration Register 00 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC00_b; + }; + + union + { + __IOM uint32_t FWPC10; /*!< (@ 0x00000104) Port Configuration Register 10 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC10_b; + }; + + union + { + __IOM uint32_t FWPC20; /*!< (@ 0x00000108) Port Configuration Register 20 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC20_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t FWPC01; /*!< (@ 0x00000110) Port Configuration Register 01 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC01_b; + }; + + union + { + __IOM uint32_t FWPC11; /*!< (@ 0x00000114) Port Configuration Register 11 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC11_b; + }; + + union + { + __IOM uint32_t FWPC21; /*!< (@ 0x00000118) Port Configuration Register 21 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC21_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t FWPC02; /*!< (@ 0x00000120) Port Configuration Register 02 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC02_b; + }; + + union + { + __IOM uint32_t FWPC12; /*!< (@ 0x00000124) Port Configuration Register 12 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC12_b; + }; + + union + { + __IOM uint32_t FWPC22; /*!< (@ 0x00000128) Port Configuration Register 22 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC22_b; + }; + __IM uint32_t RESERVED8[181]; + + union + { + __IOM uint32_t FWCTGC00; /*!< (@ 0x00000400) Cut-Through General Configuration Register 00 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC00_b; + }; + + union + { + __IOM uint32_t FWCTGC10; /*!< (@ 0x00000404) Cut-Through General Configuration Register 10 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC10_b; + }; + + union + { + __IOM uint32_t FWCTTC00; /*!< (@ 0x00000408) Cut-Through Target Configuration Register 00 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC00_b; + }; + + union + { + __IOM uint32_t FWCTTC10; /*!< (@ 0x0000040C) Cut-Through Target Configuration Register 10 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC10_b; + }; + + union + { + __IOM uint32_t FWCTTC200; /*!< (@ 0x00000410) Cut-Through Target Configuration Register 200 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC200_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t FWCTSC00; /*!< (@ 0x00000420) Cut-Through Separation Configuration Register + * 00 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC00_b; + }; + + union + { + __IOM uint32_t FWCTSC10; /*!< (@ 0x00000424) Cut-Through Separation Configuration Register + * 10 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC10_b; + }; + + union + { + __IOM uint32_t FWCTSC20; /*!< (@ 0x00000428) Cut-Through Separation Configuration Register + * 20 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC20_b; + }; + + union + { + __IOM uint32_t FWCTSC30; /*!< (@ 0x0000042C) Cut-Through Separation Configuration Register + * 30 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC30_b; + }; + + union + { + __IOM uint32_t FWCTSC40; /*!< (@ 0x00000430) Cut-Through Separation Configuration Register + * 40 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC40_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t FWCTGC01; /*!< (@ 0x00000440) Cut-Through General Configuration Register 01 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC01_b; + }; + + union + { + __IOM uint32_t FWCTGC11; /*!< (@ 0x00000444) Cut-Through General Configuration Register 11 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC11_b; + }; + + union + { + __IOM uint32_t FWCTTC01; /*!< (@ 0x00000448) Cut-Through Target Configuration Register 01 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC01_b; + }; + + union + { + __IOM uint32_t FWCTTC11; /*!< (@ 0x0000044C) Cut-Through Target Configuration Register 11 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC11_b; + }; + + union + { + __IOM uint32_t FWCTTC201; /*!< (@ 0x00000450) Cut-Through Target Configuration Register 201 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC201_b; + }; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint32_t FWCTSC01; /*!< (@ 0x00000460) Cut-Through Separation Configuration Register + * 01 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC01_b; + }; + + union + { + __IOM uint32_t FWCTSC11; /*!< (@ 0x00000464) Cut-Through Separation Configuration Register + * 11 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC11_b; + }; + + union + { + __IOM uint32_t FWCTSC21; /*!< (@ 0x00000468) Cut-Through Separation Configuration Register + * 21 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC21_b; + }; + + union + { + __IOM uint32_t FWCTSC31; /*!< (@ 0x0000046C) Cut-Through Separation Configuration Register + * 31 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC31_b; + }; + + union + { + __IOM uint32_t FWCTSC41; /*!< (@ 0x00000470) Cut-Through Separation Configuration Register + * 41 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC41_b; + }; + __IM uint32_t RESERVED12[3]; + + union + { + __IOM uint32_t FWCTGC02; /*!< (@ 0x00000480) Cut-Through General Configuration Register 02 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC02_b; + }; + + union + { + __IOM uint32_t FWCTGC12; /*!< (@ 0x00000484) Cut-Through General Configuration Register 12 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC12_b; + }; + + union + { + __IOM uint32_t FWCTTC02; /*!< (@ 0x00000488) Cut-Through Target Configuration Register 02 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC02_b; + }; + + union + { + __IOM uint32_t FWCTTC12; /*!< (@ 0x0000048C) Cut-Through Target Configuration Register 12 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC12_b; + }; + + union + { + __IOM uint32_t FWCTTC202; /*!< (@ 0x00000490) Cut-Through Target Configuration Register 202 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC202_b; + }; + __IM uint32_t RESERVED13[3]; + + union + { + __IOM uint32_t FWCTSC02; /*!< (@ 0x000004A0) Cut-Through Separation Configuration Register + * 02 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC02_b; + }; + + union + { + __IOM uint32_t FWCTSC12; /*!< (@ 0x000004A4) Cut-Through Separation Configuration Register + * 12 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC12_b; + }; + + union + { + __IOM uint32_t FWCTSC22; /*!< (@ 0x000004A8) Cut-Through Separation Configuration Register + * 22 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC22_b; + }; + + union + { + __IOM uint32_t FWCTSC32; /*!< (@ 0x000004AC) Cut-Through Separation Configuration Register + * 32 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC32_b; + }; + + union + { + __IOM uint32_t FWCTSC42; /*!< (@ 0x000004B0) Cut-Through Separation Configuration Register + * 42 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC42_b; + }; + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t FWCTGC03; /*!< (@ 0x000004C0) Cut-Through General Configuration Register 03 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC03_b; + }; + + union + { + __IOM uint32_t FWCTGC13; /*!< (@ 0x000004C4) Cut-Through General Configuration Register 13 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC13_b; + }; + + union + { + __IOM uint32_t FWCTTC03; /*!< (@ 0x000004C8) Cut-Through Target Configuration Register 03 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC03_b; + }; + + union + { + __IOM uint32_t FWCTTC13; /*!< (@ 0x000004CC) Cut-Through Target Configuration Register 13 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC13_b; + }; + + union + { + __IOM uint32_t FWCTTC203; /*!< (@ 0x000004D0) Cut-Through Target Configuration Register 203 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC203_b; + }; + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint32_t FWCTSC03; /*!< (@ 0x000004E0) Cut-Through Separation Configuration Register + * 03 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC03_b; + }; + + union + { + __IOM uint32_t FWCTSC13; /*!< (@ 0x000004E4) Cut-Through Separation Configuration Register + * 13 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC13_b; + }; + + union + { + __IOM uint32_t FWCTSC23; /*!< (@ 0x000004E8) Cut-Through Separation Configuration Register + * 23 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC23_b; + }; + + union + { + __IOM uint32_t FWCTSC33; /*!< (@ 0x000004EC) Cut-Through Separation Configuration Register + * 33 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC33_b; + }; + + union + { + __IOM uint32_t FWCTSC43; /*!< (@ 0x000004F0) Cut-Through Separation Configuration Register + * 43 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC43_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t FWCTGC04; /*!< (@ 0x00000500) Cut-Through General Configuration Register 04 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC04_b; + }; + + union + { + __IOM uint32_t FWCTGC14; /*!< (@ 0x00000504) Cut-Through General Configuration Register 14 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC14_b; + }; + + union + { + __IOM uint32_t FWCTTC04; /*!< (@ 0x00000508) Cut-Through Target Configuration Register 04 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC04_b; + }; + + union + { + __IOM uint32_t FWCTTC14; /*!< (@ 0x0000050C) Cut-Through Target Configuration Register 14 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC14_b; + }; + + union + { + __IOM uint32_t FWCTTC204; /*!< (@ 0x00000510) Cut-Through Target Configuration Register 204 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC204_b; + }; + __IM uint32_t RESERVED17[3]; + + union + { + __IOM uint32_t FWCTSC04; /*!< (@ 0x00000520) Cut-Through Separation Configuration Register + * 04 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC04_b; + }; + + union + { + __IOM uint32_t FWCTSC14; /*!< (@ 0x00000524) Cut-Through Separation Configuration Register + * 14 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC14_b; + }; + + union + { + __IOM uint32_t FWCTSC24; /*!< (@ 0x00000528) Cut-Through Separation Configuration Register + * 24 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC24_b; + }; + + union + { + __IOM uint32_t FWCTSC34; /*!< (@ 0x0000052C) Cut-Through Separation Configuration Register + * 34 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC34_b; + }; + + union + { + __IOM uint32_t FWCTSC44; /*!< (@ 0x00000530) Cut-Through Separation Configuration Register + * 44 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC44_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IOM uint32_t FWCTGC05; /*!< (@ 0x00000540) Cut-Through General Configuration Register 05 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC05_b; + }; + + union + { + __IOM uint32_t FWCTGC15; /*!< (@ 0x00000544) Cut-Through General Configuration Register 15 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC15_b; + }; + + union + { + __IOM uint32_t FWCTTC05; /*!< (@ 0x00000548) Cut-Through Target Configuration Register 05 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC05_b; + }; + + union + { + __IOM uint32_t FWCTTC15; /*!< (@ 0x0000054C) Cut-Through Target Configuration Register 15 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC15_b; + }; + + union + { + __IOM uint32_t FWCTTC205; /*!< (@ 0x00000550) Cut-Through Target Configuration Register 205 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC205_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IOM uint32_t FWCTSC05; /*!< (@ 0x00000560) Cut-Through Separation Configuration Register + * 05 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC05_b; + }; + + union + { + __IOM uint32_t FWCTSC15; /*!< (@ 0x00000564) Cut-Through Separation Configuration Register + * 15 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC15_b; + }; + + union + { + __IOM uint32_t FWCTSC25; /*!< (@ 0x00000568) Cut-Through Separation Configuration Register + * 25 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC25_b; + }; + + union + { + __IOM uint32_t FWCTSC35; /*!< (@ 0x0000056C) Cut-Through Separation Configuration Register + * 35 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC35_b; + }; + + union + { + __IOM uint32_t FWCTSC45; /*!< (@ 0x00000570) Cut-Through Separation Configuration Register + * 45 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC45_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint32_t FWCTGC06; /*!< (@ 0x00000580) Cut-Through General Configuration Register 06 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC06_b; + }; + + union + { + __IOM uint32_t FWCTGC16; /*!< (@ 0x00000584) Cut-Through General Configuration Register 16 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC16_b; + }; + + union + { + __IOM uint32_t FWCTTC06; /*!< (@ 0x00000588) Cut-Through Target Configuration Register 06 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC06_b; + }; + + union + { + __IOM uint32_t FWCTTC16; /*!< (@ 0x0000058C) Cut-Through Target Configuration Register 16 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC16_b; + }; + + union + { + __IOM uint32_t FWCTTC206; /*!< (@ 0x00000590) Cut-Through Target Configuration Register 206 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC206_b; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t FWCTSC06; /*!< (@ 0x000005A0) Cut-Through Separation Configuration Register + * 06 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC06_b; + }; + + union + { + __IOM uint32_t FWCTSC16; /*!< (@ 0x000005A4) Cut-Through Separation Configuration Register + * 16 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC16_b; + }; + + union + { + __IOM uint32_t FWCTSC26; /*!< (@ 0x000005A8) Cut-Through Separation Configuration Register + * 26 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC26_b; + }; + + union + { + __IOM uint32_t FWCTSC36; /*!< (@ 0x000005AC) Cut-Through Separation Configuration Register + * 36 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC36_b; + }; + + union + { + __IOM uint32_t FWCTSC46; /*!< (@ 0x000005B0) Cut-Through Separation Configuration Register + * 46 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC46_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint32_t FWCTGC07; /*!< (@ 0x000005C0) Cut-Through General Configuration Register 07 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC07_b; + }; + + union + { + __IOM uint32_t FWCTGC17; /*!< (@ 0x000005C4) Cut-Through General Configuration Register 17 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC17_b; + }; + + union + { + __IOM uint32_t FWCTTC07; /*!< (@ 0x000005C8) Cut-Through Target Configuration Register 07 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC07_b; + }; + + union + { + __IOM uint32_t FWCTTC17; /*!< (@ 0x000005CC) Cut-Through Target Configuration Register 17 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC17_b; + }; + + union + { + __IOM uint32_t FWCTTC207; /*!< (@ 0x000005D0) Cut-Through Target Configuration Register 207 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC207_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t FWCTSC07; /*!< (@ 0x000005E0) Cut-Through Separation Configuration Register + * 07 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC07_b; + }; + + union + { + __IOM uint32_t FWCTSC17; /*!< (@ 0x000005E4) Cut-Through Separation Configuration Register + * 17 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC17_b; + }; + + union + { + __IOM uint32_t FWCTSC27; /*!< (@ 0x000005E8) Cut-Through Separation Configuration Register + * 27 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC27_b; + }; + + union + { + __IOM uint32_t FWCTSC37; /*!< (@ 0x000005EC) Cut-Through Separation Configuration Register + * 37 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC37_b; + }; + + union + { + __IOM uint32_t FWCTSC47; /*!< (@ 0x000005F0) Cut-Through Separation Configuration Register + * 47 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC47_b; + }; + __IM uint32_t RESERVED24[643]; + + union + { + __IOM uint32_t FWTWBFC0; /*!< (@ 0x00001000) Two-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC0_b; + }; + + union + { + __IOM uint32_t FWTWBFVC0; /*!< (@ 0x00001004) Two-Byte Filter Value Configuration Register + * 0 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC0_b; + }; + __IM uint32_t RESERVED25[2]; + + union + { + __IOM uint32_t FWTWBFC1; /*!< (@ 0x00001010) Two-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC1_b; + }; + + union + { + __IOM uint32_t FWTWBFVC1; /*!< (@ 0x00001014) Two-Byte Filter Value Configuration Register + * 1 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC1_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint32_t FWTWBFC2; /*!< (@ 0x00001020) Two-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC2_b; + }; + + union + { + __IOM uint32_t FWTWBFVC2; /*!< (@ 0x00001024) Two-Byte Filter Value Configuration Register + * 2 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC2_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IOM uint32_t FWTWBFC3; /*!< (@ 0x00001030) Two-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC3_b; + }; + + union + { + __IOM uint32_t FWTWBFVC3; /*!< (@ 0x00001034) Two-Byte Filter Value Configuration Register + * 3 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC3_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t FWTWBFC4; /*!< (@ 0x00001040) Two-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC4_b; + }; + + union + { + __IOM uint32_t FWTWBFVC4; /*!< (@ 0x00001044) Two-Byte Filter Value Configuration Register + * 4 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC4_b; + }; + __IM uint32_t RESERVED29[2]; + + union + { + __IOM uint32_t FWTWBFC5; /*!< (@ 0x00001050) Two-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC5_b; + }; + + union + { + __IOM uint32_t FWTWBFVC5; /*!< (@ 0x00001054) Two-Byte Filter Value Configuration Register + * 5 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC5_b; + }; + __IM uint32_t RESERVED30[2]; + + union + { + __IOM uint32_t FWTWBFC6; /*!< (@ 0x00001060) Two-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC6_b; + }; + + union + { + __IOM uint32_t FWTWBFVC6; /*!< (@ 0x00001064) Two-Byte Filter Value Configuration Register + * 6 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC6_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IOM uint32_t FWTWBFC7; /*!< (@ 0x00001070) Two-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC7_b; + }; + + union + { + __IOM uint32_t FWTWBFVC7; /*!< (@ 0x00001074) Two-Byte Filter Value Configuration Register + * 7 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC7_b; + }; + __IM uint32_t RESERVED32[2]; + + union + { + __IOM uint32_t FWTWBFC8; /*!< (@ 0x00001080) Two-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC8_b; + }; + + union + { + __IOM uint32_t FWTWBFVC8; /*!< (@ 0x00001084) Two-Byte Filter Value Configuration Register + * 8 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC8_b; + }; + __IM uint32_t RESERVED33[2]; + + union + { + __IOM uint32_t FWTWBFC9; /*!< (@ 0x00001090) Two-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC9_b; + }; + + union + { + __IOM uint32_t FWTWBFVC9; /*!< (@ 0x00001094) Two-Byte Filter Value Configuration Register + * 9 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC9_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IOM uint32_t FWTWBFC10; /*!< (@ 0x000010A0) Two-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC10_b; + }; + + union + { + __IOM uint32_t FWTWBFVC10; /*!< (@ 0x000010A4) Two-Byte Filter Value Configuration Register + * 10 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC10_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IOM uint32_t FWTWBFC11; /*!< (@ 0x000010B0) Two-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC11_b; + }; + + union + { + __IOM uint32_t FWTWBFVC11; /*!< (@ 0x000010B4) Two-Byte Filter Value Configuration Register + * 11 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC11_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t FWTWBFC12; /*!< (@ 0x000010C0) Two-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC12_b; + }; + + union + { + __IOM uint32_t FWTWBFVC12; /*!< (@ 0x000010C4) Two-Byte Filter Value Configuration Register + * 12 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC12_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IOM uint32_t FWTWBFC13; /*!< (@ 0x000010D0) Two-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC13_b; + }; + + union + { + __IOM uint32_t FWTWBFVC13; /*!< (@ 0x000010D4) Two-Byte Filter Value Configuration Register + * 13 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC13_b; + }; + __IM uint32_t RESERVED38[2]; + + union + { + __IOM uint32_t FWTWBFC14; /*!< (@ 0x000010E0) Two-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC14_b; + }; + + union + { + __IOM uint32_t FWTWBFVC14; /*!< (@ 0x000010E4) Two-Byte Filter Value Configuration Register + * 14 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC14_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IOM uint32_t FWTWBFC15; /*!< (@ 0x000010F0) Two-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC15_b; + }; + + union + { + __IOM uint32_t FWTWBFVC15; /*!< (@ 0x000010F4) Two-Byte Filter Value Configuration Register + * 15 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC15_b; + }; + __IM uint32_t RESERVED40[194]; + + union + { + __IOM uint32_t FWTHBFC0; /*!< (@ 0x00001400) Three-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC0_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C0; /*!< (@ 0x00001404) Three-Byte Filter Value 0 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C0_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C0; /*!< (@ 0x00001408) Three-Byte Filter Value 1 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C0_b; + }; + __IM uint32_t RESERVED41; + + union + { + __IOM uint32_t FWTHBFC1; /*!< (@ 0x00001410) Three-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC1_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C1; /*!< (@ 0x00001414) Three-Byte Filter Value 0 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C1_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C1; /*!< (@ 0x00001418) Three-Byte Filter Value 1 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C1_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t FWTHBFC2; /*!< (@ 0x00001420) Three-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC2_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C2; /*!< (@ 0x00001424) Three-Byte Filter Value 0 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C2_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C2; /*!< (@ 0x00001428) Three-Byte Filter Value 1 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C2_b; + }; + __IM uint32_t RESERVED43; + + union + { + __IOM uint32_t FWTHBFC3; /*!< (@ 0x00001430) Three-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC3_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C3; /*!< (@ 0x00001434) Three-Byte Filter Value 0 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C3_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C3; /*!< (@ 0x00001438) Three-Byte Filter Value 1 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C3_b; + }; + __IM uint32_t RESERVED44; + + union + { + __IOM uint32_t FWTHBFC4; /*!< (@ 0x00001440) Three-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC4_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C4; /*!< (@ 0x00001444) Three-Byte Filter Value 0 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C4_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C4; /*!< (@ 0x00001448) Three-Byte Filter Value 1 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C4_b; + }; + __IM uint32_t RESERVED45; + + union + { + __IOM uint32_t FWTHBFC5; /*!< (@ 0x00001450) Three-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC5_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C5; /*!< (@ 0x00001454) Three-Byte Filter Value 0 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C5_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C5; /*!< (@ 0x00001458) Three-Byte Filter Value 1 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C5_b; + }; + __IM uint32_t RESERVED46; + + union + { + __IOM uint32_t FWTHBFC6; /*!< (@ 0x00001460) Three-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC6_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C6; /*!< (@ 0x00001464) Three-Byte Filter Value 0 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C6_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C6; /*!< (@ 0x00001468) Three-Byte Filter Value 1 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C6_b; + }; + __IM uint32_t RESERVED47; + + union + { + __IOM uint32_t FWTHBFC7; /*!< (@ 0x00001470) Three-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC7_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C7; /*!< (@ 0x00001474) Three-Byte Filter Value 0 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C7_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C7; /*!< (@ 0x00001478) Three-Byte Filter Value 1 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C7_b; + }; + __IM uint32_t RESERVED48; + + union + { + __IOM uint32_t FWTHBFC8; /*!< (@ 0x00001480) Three-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC8_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C8; /*!< (@ 0x00001484) Three-Byte Filter Value 0 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C8_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C8; /*!< (@ 0x00001488) Three-Byte Filter Value 1 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C8_b; + }; + __IM uint32_t RESERVED49; + + union + { + __IOM uint32_t FWTHBFC9; /*!< (@ 0x00001490) Three-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC9_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C9; /*!< (@ 0x00001494) Three-Byte Filter Value 0 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C9_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C9; /*!< (@ 0x00001498) Three-Byte Filter Value 1 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C9_b; + }; + __IM uint32_t RESERVED50; + + union + { + __IOM uint32_t FWTHBFC10; /*!< (@ 0x000014A0) Three-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC10_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C10; /*!< (@ 0x000014A4) Three-Byte Filter Value 0 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C10_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C10; /*!< (@ 0x000014A8) Three-Byte Filter Value 1 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C10_b; + }; + __IM uint32_t RESERVED51; + + union + { + __IOM uint32_t FWTHBFC11; /*!< (@ 0x000014B0) Three-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC11_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C11; /*!< (@ 0x000014B4) Three-Byte Filter Value 0 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C11_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C11; /*!< (@ 0x000014B8) Three-Byte Filter Value 1 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C11_b; + }; + __IM uint32_t RESERVED52; + + union + { + __IOM uint32_t FWTHBFC12; /*!< (@ 0x000014C0) Three-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC12_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C12; /*!< (@ 0x000014C4) Three-Byte Filter Value 0 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C12_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C12; /*!< (@ 0x000014C8) Three-Byte Filter Value 1 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C12_b; + }; + __IM uint32_t RESERVED53; + + union + { + __IOM uint32_t FWTHBFC13; /*!< (@ 0x000014D0) Three-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC13_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C13; /*!< (@ 0x000014D4) Three-Byte Filter Value 0 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C13_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C13; /*!< (@ 0x000014D8) Three-Byte Filter Value 1 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C13_b; + }; + __IM uint32_t RESERVED54; + + union + { + __IOM uint32_t FWTHBFC14; /*!< (@ 0x000014E0) Three-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC14_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C14; /*!< (@ 0x000014E4) Three-Byte Filter Value 0 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C14_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C14; /*!< (@ 0x000014E8) Three-Byte Filter Value 1 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C14_b; + }; + __IM uint32_t RESERVED55; + + union + { + __IOM uint32_t FWTHBFC15; /*!< (@ 0x000014F0) Three-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC15_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C15; /*!< (@ 0x000014F4) Three-Byte Filter Value 0 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C15_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C15; /*!< (@ 0x000014F8) Three-Byte Filter Value 1 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C15_b; + }; + __IM uint32_t RESERVED56[193]; + + union + { + __IOM uint32_t FWFOBFC0; /*!< (@ 0x00001800) Four-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC0_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C0; /*!< (@ 0x00001804) Four-Byte Filter Value 0 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C0_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C0; /*!< (@ 0x00001808) Four-Byte Filter Value 1 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C0_b; + }; + __IM uint32_t RESERVED57; + + union + { + __IOM uint32_t FWFOBFC1; /*!< (@ 0x00001810) Four-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC1_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C1; /*!< (@ 0x00001814) Four-Byte Filter Value 0 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C1_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C1; /*!< (@ 0x00001818) Four-Byte Filter Value 1 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C1_b; + }; + __IM uint32_t RESERVED58; + + union + { + __IOM uint32_t FWFOBFC2; /*!< (@ 0x00001820) Four-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC2_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C2; /*!< (@ 0x00001824) Four-Byte Filter Value 0 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C2_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C2; /*!< (@ 0x00001828) Four-Byte Filter Value 1 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C2_b; + }; + __IM uint32_t RESERVED59; + + union + { + __IOM uint32_t FWFOBFC3; /*!< (@ 0x00001830) Four-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC3_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C3; /*!< (@ 0x00001834) Four-Byte Filter Value 0 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C3_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C3; /*!< (@ 0x00001838) Four-Byte Filter Value 1 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C3_b; + }; + __IM uint32_t RESERVED60; + + union + { + __IOM uint32_t FWFOBFC4; /*!< (@ 0x00001840) Four-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC4_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C4; /*!< (@ 0x00001844) Four-Byte Filter Value 0 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C4_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C4; /*!< (@ 0x00001848) Four-Byte Filter Value 1 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C4_b; + }; + __IM uint32_t RESERVED61; + + union + { + __IOM uint32_t FWFOBFC5; /*!< (@ 0x00001850) Four-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC5_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C5; /*!< (@ 0x00001854) Four-Byte Filter Value 0 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C5_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C5; /*!< (@ 0x00001858) Four-Byte Filter Value 1 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C5_b; + }; + __IM uint32_t RESERVED62; + + union + { + __IOM uint32_t FWFOBFC6; /*!< (@ 0x00001860) Four-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC6_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C6; /*!< (@ 0x00001864) Four-Byte Filter Value 0 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C6_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C6; /*!< (@ 0x00001868) Four-Byte Filter Value 1 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C6_b; + }; + __IM uint32_t RESERVED63; + + union + { + __IOM uint32_t FWFOBFC7; /*!< (@ 0x00001870) Four-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC7_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C7; /*!< (@ 0x00001874) Four-Byte Filter Value 0 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C7_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C7; /*!< (@ 0x00001878) Four-Byte Filter Value 1 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C7_b; + }; + __IM uint32_t RESERVED64; + + union + { + __IOM uint32_t FWFOBFC8; /*!< (@ 0x00001880) Four-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC8_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C8; /*!< (@ 0x00001884) Four-Byte Filter Value 0 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C8_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C8; /*!< (@ 0x00001888) Four-Byte Filter Value 1 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C8_b; + }; + __IM uint32_t RESERVED65; + + union + { + __IOM uint32_t FWFOBFC9; /*!< (@ 0x00001890) Four-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC9_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C9; /*!< (@ 0x00001894) Four-Byte Filter Value 0 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C9_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C9; /*!< (@ 0x00001898) Four-Byte Filter Value 1 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C9_b; + }; + __IM uint32_t RESERVED66; + + union + { + __IOM uint32_t FWFOBFC10; /*!< (@ 0x000018A0) Four-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC10_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C10; /*!< (@ 0x000018A4) Four-Byte Filter Value 0 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C10_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C10; /*!< (@ 0x000018A8) Four-Byte Filter Value 1 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C10_b; + }; + __IM uint32_t RESERVED67; + + union + { + __IOM uint32_t FWFOBFC11; /*!< (@ 0x000018B0) Four-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC11_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C11; /*!< (@ 0x000018B4) Four-Byte Filter Value 0 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C11_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C11; /*!< (@ 0x000018B8) Four-Byte Filter Value 1 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C11_b; + }; + __IM uint32_t RESERVED68; + + union + { + __IOM uint32_t FWFOBFC12; /*!< (@ 0x000018C0) Four-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC12_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C12; /*!< (@ 0x000018C4) Four-Byte Filter Value 0 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C12_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C12; /*!< (@ 0x000018C8) Four-Byte Filter Value 1 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C12_b; + }; + __IM uint32_t RESERVED69; + + union + { + __IOM uint32_t FWFOBFC13; /*!< (@ 0x000018D0) Four-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC13_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C13; /*!< (@ 0x000018D4) Four-Byte Filter Value 0 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C13_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C13; /*!< (@ 0x000018D8) Four-Byte Filter Value 1 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C13_b; + }; + __IM uint32_t RESERVED70; + + union + { + __IOM uint32_t FWFOBFC14; /*!< (@ 0x000018E0) Four-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC14_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C14; /*!< (@ 0x000018E4) Four-Byte Filter Value 0 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C14_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C14; /*!< (@ 0x000018E8) Four-Byte Filter Value 1 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C14_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t FWFOBFC15; /*!< (@ 0x000018F0) Four-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC15_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C15; /*!< (@ 0x000018F4) Four-Byte Filter Value 0 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C15_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C15; /*!< (@ 0x000018F8) Four-Byte Filter Value 1 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C15_b; + }; + __IM uint32_t RESERVED72[193]; + + union + { + __IOM uint32_t FWRFC0; /*!< (@ 0x00001C00) Range Filter Configuration Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RFM : 1; /*!< [8..8] Range Filtering Mode */ + uint32_t : 7; + __IOM uint32_t RFOV : 8; /*!< [23..16] Range Filter Offset Value */ + uint32_t : 8; + } FWRFC0_b; + }; + + union + { + __IOM uint32_t FWRFVC0; /*!< (@ 0x00001C04) Range Filter Value Configuration Register 0 */ + + struct + { + __IOM uint32_t RFSV0 : 8; /*!< [7..0] Range Filter Start Value 0 */ + __IOM uint32_t RFSV1 : 8; /*!< [15..8] Range Filter Start Value 1 */ + __IOM uint32_t RFRV : 4; /*!< [19..16] Range Filter Range Value */ + uint32_t : 12; + } FWRFVC0_b; + }; + __IM uint32_t RESERVED73[2]; + + union + { + __IOM uint32_t FWRFC1; /*!< (@ 0x00001C10) Range Filter Configuration Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RFM : 1; /*!< [8..8] Range Filtering Mode */ + uint32_t : 7; + __IOM uint32_t RFOV : 8; /*!< [23..16] Range Filter Offset Value */ + uint32_t : 8; + } FWRFC1_b; + }; + + union + { + __IOM uint32_t FWRFVC1; /*!< (@ 0x00001C14) Range Filter Value Configuration Register 1 */ + + struct + { + __IOM uint32_t RFSV0 : 8; /*!< [7..0] Range Filter Start Value 0 */ + __IOM uint32_t RFSV1 : 8; /*!< [15..8] Range Filter Start Value 1 */ + __IOM uint32_t RFRV : 4; /*!< [19..16] Range Filter Range Value */ + uint32_t : 12; + } FWRFVC1_b; + }; + __IM uint32_t RESERVED74[250]; + + union + { + __IOM uint32_t FWCFC0; /*!< (@ 0x00002000) Cascade Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC0_b; + }; + + union + { + __IOM uint32_t FWCFMC00; /*!< (@ 0x00002004) Cascade Filter Mapping Configuration Register + * 00 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC00_b; + }; + + union + { + __IOM uint32_t FWCFMC01; /*!< (@ 0x00002008) Cascade Filter Mapping Configuration Register + * 01 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC01_b; + }; + + union + { + __IOM uint32_t FWCFMC02; /*!< (@ 0x0000200C) Cascade Filter Mapping Configuration Register + * 02 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC02_b; + }; + + union + { + __IOM uint32_t FWCFMC03; /*!< (@ 0x00002010) Cascade Filter Mapping Configuration Register + * 03 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC03_b; + }; + + union + { + __IOM uint32_t FWCFMC04; /*!< (@ 0x00002014) Cascade Filter Mapping Configuration Register + * 04 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC04_b; + }; + + union + { + __IOM uint32_t FWCFMC05; /*!< (@ 0x00002018) Cascade Filter Mapping Configuration Register + * 05 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC05_b; + }; + + union + { + __IOM uint32_t FWCFMC06; /*!< (@ 0x0000201C) Cascade Filter Mapping Configuration Register + * 06 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC06_b; + }; + __IM uint32_t RESERVED75[8]; + + union + { + __IOM uint32_t FWCFC1; /*!< (@ 0x00002040) Cascade Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC1_b; + }; + + union + { + __IOM uint32_t FWCFMC10; /*!< (@ 0x00002044) Cascade Filter Mapping Configuration Register + * 10 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC10_b; + }; + + union + { + __IOM uint32_t FWCFMC11; /*!< (@ 0x00002048) Cascade Filter Mapping Configuration Register + * 11 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC11_b; + }; + + union + { + __IOM uint32_t FWCFMC12; /*!< (@ 0x0000204C) Cascade Filter Mapping Configuration Register + * 12 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC12_b; + }; + + union + { + __IOM uint32_t FWCFMC13; /*!< (@ 0x00002050) Cascade Filter Mapping Configuration Register + * 13 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC13_b; + }; + + union + { + __IOM uint32_t FWCFMC14; /*!< (@ 0x00002054) Cascade Filter Mapping Configuration Register + * 14 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC14_b; + }; + + union + { + __IOM uint32_t FWCFMC15; /*!< (@ 0x00002058) Cascade Filter Mapping Configuration Register + * 15 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC15_b; + }; + + union + { + __IOM uint32_t FWCFMC16; /*!< (@ 0x0000205C) Cascade Filter Mapping Configuration Register + * 16 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC16_b; + }; + __IM uint32_t RESERVED76[8]; + + union + { + __IOM uint32_t FWCFC2; /*!< (@ 0x00002080) Cascade Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC2_b; + }; + + union + { + __IOM uint32_t FWCFMC20; /*!< (@ 0x00002084) Cascade Filter Mapping Configuration Register + * 20 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC20_b; + }; + + union + { + __IOM uint32_t FWCFMC21; /*!< (@ 0x00002088) Cascade Filter Mapping Configuration Register + * 21 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC21_b; + }; + + union + { + __IOM uint32_t FWCFMC22; /*!< (@ 0x0000208C) Cascade Filter Mapping Configuration Register + * 22 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC22_b; + }; + + union + { + __IOM uint32_t FWCFMC23; /*!< (@ 0x00002090) Cascade Filter Mapping Configuration Register + * 23 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC23_b; + }; + + union + { + __IOM uint32_t FWCFMC24; /*!< (@ 0x00002094) Cascade Filter Mapping Configuration Register + * 24 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC24_b; + }; + + union + { + __IOM uint32_t FWCFMC25; /*!< (@ 0x00002098) Cascade Filter Mapping Configuration Register + * 25 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC25_b; + }; + + union + { + __IOM uint32_t FWCFMC26; /*!< (@ 0x0000209C) Cascade Filter Mapping Configuration Register + * 26 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC26_b; + }; + __IM uint32_t RESERVED77[8]; + + union + { + __IOM uint32_t FWCFC3; /*!< (@ 0x000020C0) Cascade Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC3_b; + }; + + union + { + __IOM uint32_t FWCFMC30; /*!< (@ 0x000020C4) Cascade Filter Mapping Configuration Register + * 30 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC30_b; + }; + + union + { + __IOM uint32_t FWCFMC31; /*!< (@ 0x000020C8) Cascade Filter Mapping Configuration Register + * 31 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC31_b; + }; + + union + { + __IOM uint32_t FWCFMC32; /*!< (@ 0x000020CC) Cascade Filter Mapping Configuration Register + * 32 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC32_b; + }; + + union + { + __IOM uint32_t FWCFMC33; /*!< (@ 0x000020D0) Cascade Filter Mapping Configuration Register + * 33 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC33_b; + }; + + union + { + __IOM uint32_t FWCFMC34; /*!< (@ 0x000020D4) Cascade Filter Mapping Configuration Register + * 34 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC34_b; + }; + + union + { + __IOM uint32_t FWCFMC35; /*!< (@ 0x000020D8) Cascade Filter Mapping Configuration Register + * 35 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC35_b; + }; + + union + { + __IOM uint32_t FWCFMC36; /*!< (@ 0x000020DC) Cascade Filter Mapping Configuration Register + * 36 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC36_b; + }; + __IM uint32_t RESERVED78[8]; + + union + { + __IOM uint32_t FWCFC4; /*!< (@ 0x00002100) Cascade Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC4_b; + }; + + union + { + __IOM uint32_t FWCFMC40; /*!< (@ 0x00002104) Cascade Filter Mapping Configuration Register + * 40 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC40_b; + }; + + union + { + __IOM uint32_t FWCFMC41; /*!< (@ 0x00002108) Cascade Filter Mapping Configuration Register + * 41 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC41_b; + }; + + union + { + __IOM uint32_t FWCFMC42; /*!< (@ 0x0000210C) Cascade Filter Mapping Configuration Register + * 42 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC42_b; + }; + + union + { + __IOM uint32_t FWCFMC43; /*!< (@ 0x00002110) Cascade Filter Mapping Configuration Register + * 43 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC43_b; + }; + + union + { + __IOM uint32_t FWCFMC44; /*!< (@ 0x00002114) Cascade Filter Mapping Configuration Register + * 44 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC44_b; + }; + + union + { + __IOM uint32_t FWCFMC45; /*!< (@ 0x00002118) Cascade Filter Mapping Configuration Register + * 45 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC45_b; + }; + + union + { + __IOM uint32_t FWCFMC46; /*!< (@ 0x0000211C) Cascade Filter Mapping Configuration Register + * 46 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC46_b; + }; + __IM uint32_t RESERVED79[8]; + + union + { + __IOM uint32_t FWCFC5; /*!< (@ 0x00002140) Cascade Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC5_b; + }; + + union + { + __IOM uint32_t FWCFMC50; /*!< (@ 0x00002144) Cascade Filter Mapping Configuration Register + * 50 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC50_b; + }; + + union + { + __IOM uint32_t FWCFMC51; /*!< (@ 0x00002148) Cascade Filter Mapping Configuration Register + * 51 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC51_b; + }; + + union + { + __IOM uint32_t FWCFMC52; /*!< (@ 0x0000214C) Cascade Filter Mapping Configuration Register + * 52 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC52_b; + }; + + union + { + __IOM uint32_t FWCFMC53; /*!< (@ 0x00002150) Cascade Filter Mapping Configuration Register + * 53 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC53_b; + }; + + union + { + __IOM uint32_t FWCFMC54; /*!< (@ 0x00002154) Cascade Filter Mapping Configuration Register + * 54 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC54_b; + }; + + union + { + __IOM uint32_t FWCFMC55; /*!< (@ 0x00002158) Cascade Filter Mapping Configuration Register + * 55 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC55_b; + }; + + union + { + __IOM uint32_t FWCFMC56; /*!< (@ 0x0000215C) Cascade Filter Mapping Configuration Register + * 56 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC56_b; + }; + __IM uint32_t RESERVED80[8]; + + union + { + __IOM uint32_t FWCFC6; /*!< (@ 0x00002180) Cascade Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC6_b; + }; + + union + { + __IOM uint32_t FWCFMC60; /*!< (@ 0x00002184) Cascade Filter Mapping Configuration Register + * 60 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC60_b; + }; + + union + { + __IOM uint32_t FWCFMC61; /*!< (@ 0x00002188) Cascade Filter Mapping Configuration Register + * 61 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC61_b; + }; + + union + { + __IOM uint32_t FWCFMC62; /*!< (@ 0x0000218C) Cascade Filter Mapping Configuration Register + * 62 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC62_b; + }; + + union + { + __IOM uint32_t FWCFMC63; /*!< (@ 0x00002190) Cascade Filter Mapping Configuration Register + * 63 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC63_b; + }; + + union + { + __IOM uint32_t FWCFMC64; /*!< (@ 0x00002194) Cascade Filter Mapping Configuration Register + * 64 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC64_b; + }; + + union + { + __IOM uint32_t FWCFMC65; /*!< (@ 0x00002198) Cascade Filter Mapping Configuration Register + * 65 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC65_b; + }; + + union + { + __IOM uint32_t FWCFMC66; /*!< (@ 0x0000219C) Cascade Filter Mapping Configuration Register + * 66 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC66_b; + }; + __IM uint32_t RESERVED81[8]; + + union + { + __IOM uint32_t FWCFC7; /*!< (@ 0x000021C0) Cascade Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC7_b; + }; + + union + { + __IOM uint32_t FWCFMC70; /*!< (@ 0x000021C4) Cascade Filter Mapping Configuration Register + * 70 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC70_b; + }; + + union + { + __IOM uint32_t FWCFMC71; /*!< (@ 0x000021C8) Cascade Filter Mapping Configuration Register + * 71 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC71_b; + }; + + union + { + __IOM uint32_t FWCFMC72; /*!< (@ 0x000021CC) Cascade Filter Mapping Configuration Register + * 72 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC72_b; + }; + + union + { + __IOM uint32_t FWCFMC73; /*!< (@ 0x000021D0) Cascade Filter Mapping Configuration Register + * 73 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC73_b; + }; + + union + { + __IOM uint32_t FWCFMC74; /*!< (@ 0x000021D4) Cascade Filter Mapping Configuration Register + * 74 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC74_b; + }; + + union + { + __IOM uint32_t FWCFMC75; /*!< (@ 0x000021D8) Cascade Filter Mapping Configuration Register + * 75 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC75_b; + }; + + union + { + __IOM uint32_t FWCFMC76; /*!< (@ 0x000021DC) Cascade Filter Mapping Configuration Register + * 76 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC76_b; + }; + __IM uint32_t RESERVED82[8]; + + union + { + __IOM uint32_t FWCFC8; /*!< (@ 0x00002200) Cascade Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC8_b; + }; + + union + { + __IOM uint32_t FWCFMC80; /*!< (@ 0x00002204) Cascade Filter Mapping Configuration Register + * 80 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC80_b; + }; + + union + { + __IOM uint32_t FWCFMC81; /*!< (@ 0x00002208) Cascade Filter Mapping Configuration Register + * 81 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC81_b; + }; + + union + { + __IOM uint32_t FWCFMC82; /*!< (@ 0x0000220C) Cascade Filter Mapping Configuration Register + * 82 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC82_b; + }; + + union + { + __IOM uint32_t FWCFMC83; /*!< (@ 0x00002210) Cascade Filter Mapping Configuration Register + * 83 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC83_b; + }; + + union + { + __IOM uint32_t FWCFMC84; /*!< (@ 0x00002214) Cascade Filter Mapping Configuration Register + * 84 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC84_b; + }; + + union + { + __IOM uint32_t FWCFMC85; /*!< (@ 0x00002218) Cascade Filter Mapping Configuration Register + * 85 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC85_b; + }; + + union + { + __IOM uint32_t FWCFMC86; /*!< (@ 0x0000221C) Cascade Filter Mapping Configuration Register + * 86 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC86_b; + }; + __IM uint32_t RESERVED83[8]; + + union + { + __IOM uint32_t FWCFC9; /*!< (@ 0x00002240) Cascade Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC9_b; + }; + + union + { + __IOM uint32_t FWCFMC90; /*!< (@ 0x00002244) Cascade Filter Mapping Configuration Register + * 90 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC90_b; + }; + + union + { + __IOM uint32_t FWCFMC91; /*!< (@ 0x00002248) Cascade Filter Mapping Configuration Register + * 91 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC91_b; + }; + + union + { + __IOM uint32_t FWCFMC92; /*!< (@ 0x0000224C) Cascade Filter Mapping Configuration Register + * 92 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC92_b; + }; + + union + { + __IOM uint32_t FWCFMC93; /*!< (@ 0x00002250) Cascade Filter Mapping Configuration Register + * 93 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC93_b; + }; + + union + { + __IOM uint32_t FWCFMC94; /*!< (@ 0x00002254) Cascade Filter Mapping Configuration Register + * 94 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC94_b; + }; + + union + { + __IOM uint32_t FWCFMC95; /*!< (@ 0x00002258) Cascade Filter Mapping Configuration Register + * 95 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC95_b; + }; + + union + { + __IOM uint32_t FWCFMC96; /*!< (@ 0x0000225C) Cascade Filter Mapping Configuration Register + * 96 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC96_b; + }; + __IM uint32_t RESERVED84[8]; + + union + { + __IOM uint32_t FWCFC10; /*!< (@ 0x00002280) Cascade Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC10_b; + }; + + union + { + __IOM uint32_t FWCFMC100; /*!< (@ 0x00002284) Cascade Filter Mapping Configuration Register + * 100 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC100_b; + }; + + union + { + __IOM uint32_t FWCFMC101; /*!< (@ 0x00002288) Cascade Filter Mapping Configuration Register + * 101 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC101_b; + }; + + union + { + __IOM uint32_t FWCFMC102; /*!< (@ 0x0000228C) Cascade Filter Mapping Configuration Register + * 102 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC102_b; + }; + + union + { + __IOM uint32_t FWCFMC103; /*!< (@ 0x00002290) Cascade Filter Mapping Configuration Register + * 103 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC103_b; + }; + + union + { + __IOM uint32_t FWCFMC104; /*!< (@ 0x00002294) Cascade Filter Mapping Configuration Register + * 104 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC104_b; + }; + + union + { + __IOM uint32_t FWCFMC105; /*!< (@ 0x00002298) Cascade Filter Mapping Configuration Register + * 105 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC105_b; + }; + + union + { + __IOM uint32_t FWCFMC106; /*!< (@ 0x0000229C) Cascade Filter Mapping Configuration Register + * 106 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC106_b; + }; + __IM uint32_t RESERVED85[8]; + + union + { + __IOM uint32_t FWCFC11; /*!< (@ 0x000022C0) Cascade Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC11_b; + }; + + union + { + __IOM uint32_t FWCFMC110; /*!< (@ 0x000022C4) Cascade Filter Mapping Configuration Register + * 110 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC110_b; + }; + + union + { + __IOM uint32_t FWCFMC111; /*!< (@ 0x000022C8) Cascade Filter Mapping Configuration Register + * 111 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC111_b; + }; + + union + { + __IOM uint32_t FWCFMC112; /*!< (@ 0x000022CC) Cascade Filter Mapping Configuration Register + * 112 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC112_b; + }; + + union + { + __IOM uint32_t FWCFMC113; /*!< (@ 0x000022D0) Cascade Filter Mapping Configuration Register + * 113 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC113_b; + }; + + union + { + __IOM uint32_t FWCFMC114; /*!< (@ 0x000022D4) Cascade Filter Mapping Configuration Register + * 114 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC114_b; + }; + + union + { + __IOM uint32_t FWCFMC115; /*!< (@ 0x000022D8) Cascade Filter Mapping Configuration Register + * 115 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC115_b; + }; + + union + { + __IOM uint32_t FWCFMC116; /*!< (@ 0x000022DC) Cascade Filter Mapping Configuration Register + * 116 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC116_b; + }; + __IM uint32_t RESERVED86[8]; + + union + { + __IOM uint32_t FWCFC12; /*!< (@ 0x00002300) Cascade Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC12_b; + }; + + union + { + __IOM uint32_t FWCFMC120; /*!< (@ 0x00002304) Cascade Filter Mapping Configuration Register + * 120 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC120_b; + }; + + union + { + __IOM uint32_t FWCFMC121; /*!< (@ 0x00002308) Cascade Filter Mapping Configuration Register + * 121 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC121_b; + }; + + union + { + __IOM uint32_t FWCFMC122; /*!< (@ 0x0000230C) Cascade Filter Mapping Configuration Register + * 122 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC122_b; + }; + + union + { + __IOM uint32_t FWCFMC123; /*!< (@ 0x00002310) Cascade Filter Mapping Configuration Register + * 123 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC123_b; + }; + + union + { + __IOM uint32_t FWCFMC124; /*!< (@ 0x00002314) Cascade Filter Mapping Configuration Register + * 124 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC124_b; + }; + + union + { + __IOM uint32_t FWCFMC125; /*!< (@ 0x00002318) Cascade Filter Mapping Configuration Register + * 125 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC125_b; + }; + + union + { + __IOM uint32_t FWCFMC126; /*!< (@ 0x0000231C) Cascade Filter Mapping Configuration Register + * 126 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC126_b; + }; + __IM uint32_t RESERVED87[8]; + + union + { + __IOM uint32_t FWCFC13; /*!< (@ 0x00002340) Cascade Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC13_b; + }; + + union + { + __IOM uint32_t FWCFMC130; /*!< (@ 0x00002344) Cascade Filter Mapping Configuration Register + * 130 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC130_b; + }; + + union + { + __IOM uint32_t FWCFMC131; /*!< (@ 0x00002348) Cascade Filter Mapping Configuration Register + * 131 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC131_b; + }; + + union + { + __IOM uint32_t FWCFMC132; /*!< (@ 0x0000234C) Cascade Filter Mapping Configuration Register + * 132 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC132_b; + }; + + union + { + __IOM uint32_t FWCFMC133; /*!< (@ 0x00002350) Cascade Filter Mapping Configuration Register + * 133 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC133_b; + }; + + union + { + __IOM uint32_t FWCFMC134; /*!< (@ 0x00002354) Cascade Filter Mapping Configuration Register + * 134 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC134_b; + }; + + union + { + __IOM uint32_t FWCFMC135; /*!< (@ 0x00002358) Cascade Filter Mapping Configuration Register + * 135 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC135_b; + }; + + union + { + __IOM uint32_t FWCFMC136; /*!< (@ 0x0000235C) Cascade Filter Mapping Configuration Register + * 136 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC136_b; + }; + __IM uint32_t RESERVED88[8]; + + union + { + __IOM uint32_t FWCFC14; /*!< (@ 0x00002380) Cascade Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC14_b; + }; + + union + { + __IOM uint32_t FWCFMC140; /*!< (@ 0x00002384) Cascade Filter Mapping Configuration Register + * 140 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC140_b; + }; + + union + { + __IOM uint32_t FWCFMC141; /*!< (@ 0x00002388) Cascade Filter Mapping Configuration Register + * 141 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC141_b; + }; + + union + { + __IOM uint32_t FWCFMC142; /*!< (@ 0x0000238C) Cascade Filter Mapping Configuration Register + * 142 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC142_b; + }; + + union + { + __IOM uint32_t FWCFMC143; /*!< (@ 0x00002390) Cascade Filter Mapping Configuration Register + * 143 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC143_b; + }; + + union + { + __IOM uint32_t FWCFMC144; /*!< (@ 0x00002394) Cascade Filter Mapping Configuration Register + * 144 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC144_b; + }; + + union + { + __IOM uint32_t FWCFMC145; /*!< (@ 0x00002398) Cascade Filter Mapping Configuration Register + * 145 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC145_b; + }; + + union + { + __IOM uint32_t FWCFMC146; /*!< (@ 0x0000239C) Cascade Filter Mapping Configuration Register + * 146 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC146_b; + }; + __IM uint32_t RESERVED89[8]; + + union + { + __IOM uint32_t FWCFC15; /*!< (@ 0x000023C0) Cascade Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC15_b; + }; + + union + { + __IOM uint32_t FWCFMC150; /*!< (@ 0x000023C4) Cascade Filter Mapping Configuration Register + * 150 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC150_b; + }; + + union + { + __IOM uint32_t FWCFMC151; /*!< (@ 0x000023C8) Cascade Filter Mapping Configuration Register + * 151 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC151_b; + }; + + union + { + __IOM uint32_t FWCFMC152; /*!< (@ 0x000023CC) Cascade Filter Mapping Configuration Register + * 152 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC152_b; + }; + + union + { + __IOM uint32_t FWCFMC153; /*!< (@ 0x000023D0) Cascade Filter Mapping Configuration Register + * 153 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC153_b; + }; + + union + { + __IOM uint32_t FWCFMC154; /*!< (@ 0x000023D4) Cascade Filter Mapping Configuration Register + * 154 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC154_b; + }; + + union + { + __IOM uint32_t FWCFMC155; /*!< (@ 0x000023D8) Cascade Filter Mapping Configuration Register + * 155 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC155_b; + }; + + union + { + __IOM uint32_t FWCFMC156; /*!< (@ 0x000023DC) Cascade Filter Mapping Configuration Register + * 156 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC156_b; + }; + __IM uint32_t RESERVED90[1802]; + + union + { + __IOM uint32_t FWIP4SC; /*!< (@ 0x00004008) IPv4 Stream Configuration Register */ + + struct + { + __IOM uint32_t IP4IMDH : 1; /*!< [0..0] IPv4 Include MAC Destination in Hash */ + __IOM uint32_t IP4IMSH : 1; /*!< [1..1] IPv4 Include MAC Source in Hash */ + __IOM uint32_t IP4ISVH : 1; /*!< [2..2] IPv4 Include S-TAG VLAN ID in Hash */ + __IOM uint32_t IP4ISPH : 1; /*!< [3..3] IPv4 Include S-TAG PCP in Hash */ + __IOM uint32_t IP4ISDH : 1; /*!< [4..4] IPv4 Include S-TAG DEI in Hash */ + __IOM uint32_t IP4ICVH : 1; /*!< [5..5] IPv4 Include C-TAG VLAN ID in Hash */ + __IOM uint32_t IP4ICPH : 1; /*!< [6..6] IPv4 Include C-TAG PCP in Hash */ + __IOM uint32_t IP4ICDH : 1; /*!< [7..7] IPv4 Include C-TAG DEI in Hash */ + __IOM uint32_t IP4IISH : 1; /*!< [8..8] IPv4 Include IP Source in Hash */ + __IOM uint32_t IP4IIDH : 1; /*!< [9..9] IPv4 Include IP Destination in Hash */ + __IOM uint32_t IP4IPH : 1; /*!< [10..10] IPv4 Include Protocol in Hash */ + __IOM uint32_t IP4ISPTH : 1; /*!< [11..11] IPv4 Include Source Port in Hash */ + __IOM uint32_t IP4IDPTH : 1; /*!< [12..12] IPv4 Include Destination Port in Hash */ + uint32_t : 3; + __IOM uint32_t IP4ISVS : 1; /*!< [16..16] IPv4 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t IP4ISPS : 1; /*!< [17..17] IPv4 Include S-TAG PCP in Stream */ + __IOM uint32_t IP4ISDS : 1; /*!< [18..18] IPv4 Include S-TAG DEI in Stream */ + __IOM uint32_t IP4ICVS : 1; /*!< [19..19] IPv4 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t IP4ICPS : 1; /*!< [20..20] IPv4 Include C-TAG PCP in Stream */ + __IOM uint32_t IP4ICDS : 1; /*!< [21..21] IPv4 Include C-TAG DEI in Stream */ + __IOM uint32_t IP4IISS : 1; /*!< [22..22] IPv4 Include IP Source in Stream */ + __IOM uint32_t IP4IIDS : 1; /*!< [23..23] IPv4 Include IP Destination in Stream */ + __IOM uint32_t IP4IDPTS : 1; /*!< [24..24] IPv4 Include Destination Port in Stream */ + uint32_t : 7; + } FWIP4SC_b; + }; + __IM uint32_t RESERVED91[3]; + + union + { + __IOM uint32_t FWIP6SC; /*!< (@ 0x00004018) IPv6 Stream Configuration Register */ + + struct + { + __IOM uint32_t IP6IMDH : 1; /*!< [0..0] IPv6 Include MAC Destination in Hash */ + __IOM uint32_t IP6IMSH : 1; /*!< [1..1] IPv6 Include MAC Source in Hash */ + __IOM uint32_t IP6ISVH : 1; /*!< [2..2] IPv6 Include S-TAG VLAN ID in Hash */ + __IOM uint32_t IP6ISPH : 1; /*!< [3..3] IPv6 Include S-TAG PCP in Hash */ + __IOM uint32_t IP6ISDH : 1; /*!< [4..4] IPv6 Include S-TAG DEI in Hash */ + __IOM uint32_t IP6ICVH : 1; /*!< [5..5] IPv6 Include C-TAG VLAN ID in Hash */ + __IOM uint32_t IP6ICPH : 1; /*!< [6..6] IPv6 Include C-TAG PCP in Hash */ + __IOM uint32_t IP6ICDH : 1; /*!< [7..7] IPv6 Include C-TAG DEI in Hash */ + __IOM uint32_t IP6IISH : 1; /*!< [8..8] IPv6 Include IP Source in Hash */ + __IOM uint32_t IP6IIDH : 1; /*!< [9..9] IPv6 Include IP Destination in Hash */ + __IOM uint32_t IP6IPH : 1; /*!< [10..10] IPv6 Include Protocol in Hash */ + __IOM uint32_t IP6ISPTH : 1; /*!< [11..11] IPv6 Include Source Port in Hash */ + __IOM uint32_t IP6IDPTH : 1; /*!< [12..12] IPv6 Include Destination Port in Hash */ + uint32_t : 3; + __IOM uint32_t IP6ISVS : 1; /*!< [16..16] IPv6 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t IP6ISPS : 1; /*!< [17..17] IPv6 Include S-TAG PCP in Stream */ + __IOM uint32_t IP6ISDS : 1; /*!< [18..18] IPv6 Include S-TAG DEI in Stream */ + __IOM uint32_t IP6ICVS : 1; /*!< [19..19] IPv6 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t IP6ICPS : 1; /*!< [20..20] IPv6 Include C-TAG PCP in Stream */ + __IOM uint32_t IP6ICDS : 1; /*!< [21..21] IPv6 Include C-TAG DEI in Stream */ + __IOM uint32_t IP6II0S : 1; /*!< [22..22] IPv6 Include IP 0 in Stream */ + __IOM uint32_t IP6II1S : 1; /*!< [23..23] IPv6 Include IP 1 in Stream */ + __IOM uint32_t IP6IDPTS : 1; /*!< [24..24] IPv6 Include Destination Port in Stream */ + uint32_t : 7; + } FWIP6SC_b; + }; + + union + { + __IOM uint32_t FWIP6OC; /*!< (@ 0x0000401C) IPv6 Offset Configuration Register */ + + struct + { + __IOM uint32_t IP6IPOM0 : 1; /*!< [0..0] IPv6 IP Offset mode 0 */ + uint32_t : 3; + __IOM uint32_t IP6IPO0 : 4; /*!< [7..4] IPv6 IP Offset 0 */ + uint32_t : 8; + __IOM uint32_t IP6IPOM1 : 1; /*!< [16..16] IPv6 IP Offset mode 1 */ + uint32_t : 3; + __IOM uint32_t IP6IPO1 : 4; /*!< [23..20] IPv6 IP Offset 1 */ + uint32_t : 8; + } FWIP6OC_b; + }; + + union + { + __IOM uint32_t FWL2SC; /*!< (@ 0x00004020) Layer 2 Stream Configuration Register */ + + struct + { + __IOM uint32_t L2IMDS : 1; /*!< [0..0] Layer 2 Include MAC Destination in Stream */ + __IOM uint32_t L2IMSS : 1; /*!< [1..1] Layer 2 Include MAC Source in Stream */ + __IOM uint32_t L2ISVS : 1; /*!< [2..2] Layer 2 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t L2ISPS : 1; /*!< [3..3] Layer 2 Include S-TAG PCP ID in Stream */ + __IOM uint32_t L2ISDS : 1; /*!< [4..4] Layer 2 Include S-TAG DEI in Stream */ + __IOM uint32_t L2ICVS : 1; /*!< [5..5] Layer 2 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t L2ICPS : 1; /*!< [6..6] Layer 2 Include C-TAG PCP ID in Stream */ + __IOM uint32_t L2ICDS : 1; /*!< [7..7] Layer 2 Include C-TAG DEI in Stream */ + uint32_t : 24; + } FWL2SC_b; + }; + __IM uint32_t RESERVED92[3]; + + union + { + __IOM uint32_t FWSFHEC; /*!< (@ 0x00004030) Stream Filter Hash Equation Configuration Register */ + + struct + { + __IOM uint32_t IP4HE : 16; /*!< [15..0] Stream Filter Hash Equation */ + __IOM uint32_t IP6HE : 16; /*!< [31..16] Stream Filter Hash Equation */ + } FWSFHEC_b; + }; + __IM uint32_t RESERVED93[3]; + + union + { + __IOM uint32_t FWSHCR0; /*!< (@ 0x00004040) Software Hash Calculation Request Register 0 */ + + struct + { + __IOM uint32_t SHCMDP0 : 32; /*!< [31..0] Software Hash Calculation MAC Destination Part 0 */ + } FWSHCR0_b; + }; + + union + { + __IOM uint32_t FWSHCR1; /*!< (@ 0x00004044) Software Hash Calculation Request Register 1 */ + + struct + { + __IOM uint32_t SHCMSP0 : 16; /*!< [15..0] Software Hash Calculation MAC Source Part 0 */ + __IOM uint32_t SHCMDP1 : 16; /*!< [31..16] Software Hash Calculation MAC Destination Part 1 */ + } FWSHCR1_b; + }; + + union + { + __IOM uint32_t FWSHCR2; /*!< (@ 0x00004048) Software Hash Calculation Request Register 2 */ + + struct + { + __IOM uint32_t SHCMSP1 : 32; /*!< [31..0] Software Hash Calculation MAC Source Part 1 */ + } FWSHCR2_b; + }; + + union + { + __IOM uint32_t FWSHCR3; /*!< (@ 0x0000404C) Software Hash Calculation Request Register 3 */ + + struct + { + __IOM uint32_t SHCCV : 12; /*!< [11..0] Software Hash Calculation C-TAG VLAN */ + __IOM uint32_t SHCCD : 1; /*!< [12..12] Software Hash Calculation C-TAG DEI */ + __IOM uint32_t SHCCP : 3; /*!< [15..13] Software Hash Calculation C-TAG PCP */ + __IOM uint32_t SHCSV : 12; /*!< [27..16] Software Hash Calculation S-TAG VLANs */ + __IOM uint32_t SHCSD : 1; /*!< [28..28] Software Hash Calculation S-TAG DEI */ + __IOM uint32_t SHCSP : 3; /*!< [31..29] Software Hash Calculation S-TAG PCP */ + } FWSHCR3_b; + }; + + union + { + __IOM uint32_t FWSHCR4; /*!< (@ 0x00004050) Software Hash Calculation Request Register 4 */ + + struct + { + __IOM uint32_t SHCP : 8; /*!< [7..0] Software Hash Calculation Protocol (NextHeader for IPv6) */ + uint32_t : 8; + __IOM uint32_t SHCFF : 1; /*!< [16..16] Software Hash Calculation Frame Format */ + uint32_t : 15; + } FWSHCR4_b; + }; + + union + { + __IOM uint32_t FWSHCR5; /*!< (@ 0x00004054) Software Hash Calculation Request Register 5 */ + + struct + { + __IOM uint32_t SHCISP0 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 0 */ + } FWSHCR5_b; + }; + + union + { + __IOM uint32_t FWSHCR6; /*!< (@ 0x00004058) Software Hash Calculation Request Register 6 */ + + struct + { + __IOM uint32_t SHCISP1 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 1 */ + } FWSHCR6_b; + }; + + union + { + __IOM uint32_t FWSHCR7; /*!< (@ 0x0000405C) Software Hash Calculation Request Register 7 */ + + struct + { + __IOM uint32_t SHCISP2 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 2 */ + } FWSHCR7_b; + }; + + union + { + __IOM uint32_t FWSHCR8; /*!< (@ 0x00004060) Software Hash Calculation Request Register 8 */ + + struct + { + __IOM uint32_t SHCISP3 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 3 */ + } FWSHCR8_b; + }; + + union + { + __IOM uint32_t FWSHCR9; /*!< (@ 0x00004064) Software Hash Calculation Request Register 9 */ + + struct + { + __IOM uint32_t SHCIDP0 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 0 */ + } FWSHCR9_b; + }; + + union + { + __IOM uint32_t FWSHCR10; /*!< (@ 0x00004068) Software Hash Calculation Request Register 10 */ + + struct + { + __IOM uint32_t SHCIDP1 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 1 */ + } FWSHCR10_b; + }; + + union + { + __IOM uint32_t FWSHCR11; /*!< (@ 0x0000406C) Software Hash Calculation Request Register 11 */ + + struct + { + __IOM uint32_t SHCIDP2 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 2 */ + } FWSHCR11_b; + }; + + union + { + __IOM uint32_t FWSHCR12; /*!< (@ 0x00004070) Software Hash Calculation Request Register 12 */ + + struct + { + __IOM uint32_t SHCIDP3 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 3 */ + } FWSHCR12_b; + }; + + union + { + __IOM uint32_t FWSHCR13; /*!< (@ 0x00004074) Software Hash Calculation Request Register 13 */ + + struct + { + __IOM uint32_t SHCDP : 16; /*!< [15..0] Software Hash Calculation Destination Port */ + __IOM uint32_t SHCSP : 16; /*!< [31..16] Software Hash Calculation Source Port */ + } FWSHCR13_b; + }; + + union + { + __IM uint32_t FWSHCRR; /*!< (@ 0x00004078) Software Hash Calculation Request Result Register */ + + struct + { + __IM uint32_t SHCR : 16; /*!< [15..0] Software Hash Calculation Result */ + uint32_t : 15; + __IM uint32_t SHC : 1; /*!< [31..31] Software Hash Calculation */ + } FWSHCRR_b; + }; + __IM uint32_t RESERVED94[5]; + + union + { + __IOM uint32_t FWLTHHEC; /*!< (@ 0x00004090) L3 Hash Entry Configuration Register */ + + struct + { + __IOM uint32_t LTHHMC : 10; /*!< [9..0] L3 Hash Maximum Collision */ + uint32_t : 6; + __IOM uint32_t LTHHMUE : 11; /*!< [26..16] L3 Hash Maximum Unsecure Entry */ + uint32_t : 5; + } FWLTHHEC_b; + }; + + union + { + __IOM uint32_t FWLTHHC; /*!< (@ 0x00004094) L3 Hash Configuration Register */ + + struct + { + __IOM uint32_t LTHHE : 10; /*!< [9..0] L3 Hash Equation */ + uint32_t : 22; + } FWLTHHC_b; + }; + __IM uint32_t RESERVED95[2]; + + union + { + __IOM uint32_t FWLTHTL0; /*!< (@ 0x000040A0) L3 Table Learn Register 0 */ + + struct + { + __IOM uint32_t LTHSLP0 : 3; /*!< [2..0] L3 Stream Learn Part 0 */ + uint32_t : 5; + __IOM uint32_t LTHSLL : 1; /*!< [8..8] L3 Security Level Learn */ + uint32_t : 7; + __IOM uint32_t LTHED : 1; /*!< [16..16] L3 Entry Delete */ + uint32_t : 15; + } FWLTHTL0_b; + }; + + union + { + __IOM uint32_t FWLTHTL1; /*!< (@ 0x000040A4) L3 Table Learn Register 1 */ + + struct + { + __IOM uint32_t LTHSLP1 : 32; /*!< [31..0] L3 Stream Learn Part 1 */ + } FWLTHTL1_b; + }; + + union + { + __IOM uint32_t FWLTHTL2; /*!< (@ 0x000040A8) L3 Table Learn Register 2 */ + + struct + { + __IOM uint32_t LTHSLP2 : 32; /*!< [31..0] L3 Stream Learn Part 2 */ + } FWLTHTL2_b; + }; + + union + { + __IOM uint32_t FWLTHTL3; /*!< (@ 0x000040AC) L3 Table Learn Register 3 */ + + struct + { + __IOM uint32_t LTHSLP3 : 32; /*!< [31..0] L3 Stream Learn Part 3 */ + } FWLTHTL3_b; + }; + + union + { + __IOM uint32_t FWLTHTL4; /*!< (@ 0x000040B0) L3 Table Learn Register 4 */ + + struct + { + __IOM uint32_t LTHSLP4 : 32; /*!< [31..0] L3 Stream Learn Part 4 */ + } FWLTHTL4_b; + }; + + union + { + __IOM uint32_t FWLTHTL5; /*!< (@ 0x000040B4) L3 Table Learn Register 5 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTHMSDUNL : 4; /*!< [19..16] L3 MSDU Number Learn */ + uint32_t : 11; + __IOM uint32_t LTHMSDUVL : 1; /*!< [31..31] L3 MSDU Valid Learn */ + } FWLTHTL5_b; + }; + + union + { + __IOM uint32_t FWLTHTL6; /*!< (@ 0x000040B8) L3 Table Learn Register 6 */ + + struct + { + __IOM uint32_t LTHFRERNL : 7; /*!< [6..0] L3 FRER Number Learn */ + uint32_t : 8; + __IOM uint32_t LTHFRERVL : 1; /*!< [15..15] L3 FRER Valid Learn */ + __IOM uint32_t LTHMTRNL : 5; /*!< [20..16] L3 MeTeR Number Learn */ + uint32_t : 10; + __IOM uint32_t LTHMTRVL : 1; /*!< [31..31] L3 MeTeR Valid Learn */ + } FWLTHTL6_b; + }; + + union + { + __IOM uint32_t FWLTHTL7; /*!< (@ 0x000040BC) L3 Table Learn Register 7 */ + + struct + { + __IOM uint32_t LTHRNL : 8; /*!< [7..0] L3 Routing Number Learn */ + uint32_t : 7; + __IOM uint32_t LTHRVL : 1; /*!< [15..15] L3 Routing Valid Learn */ + __IOM uint32_t LTHSLVL : 7; /*!< [22..16] L3 Source Lock Vector Learn */ + uint32_t : 9; + } FWLTHTL7_b; + }; + + union + { + __IOM uint32_t FWLTHTL80; /*!< (@ 0x000040C0) L3 Table Learn Register 80 */ + + struct + { + __IOM uint32_t LTHCSDL : 7; /*!< [6..0] L3 CPU Sub-Destination Learn */ + uint32_t : 25; + } FWLTHTL80_b; + }; + __IM uint32_t RESERVED96[3]; + + union + { + __IOM uint32_t FWLTHTL9; /*!< (@ 0x000040D0) L3 Table Learn Register 9 */ + + struct + { + __IOM uint32_t LTHDVL : 7; /*!< [6..0] L3 Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t LTHIPVL : 3; /*!< [18..16] L3 Internal Priority Value Learn */ + __IOM uint32_t LTHIPUL : 1; /*!< [19..19] L3 Internal Priority Update Learn */ + __IOM uint32_t LTHEMEL : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Learn */ + __IOM uint32_t LTHCMEL : 1; /*!< [21..21] L3 CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWLTHTL9_b; + }; + + union + { + __IM uint32_t FWLTHTLR; /*!< (@ 0x000040D4) L3 Table Learn Result Register */ + + struct + { + __IM uint32_t LTHLF : 1; /*!< [0..0] L3 Learn Fail */ + __IM uint32_t LTHLSF : 1; /*!< [1..1] L3 Learn Security Fail */ + __IM uint32_t LTHLEF : 1; /*!< [2..2] L3 Learn ECC Fail */ + __IM uint32_t LTHLO : 1; /*!< [3..3] L3 Learn Overwrite */ + uint32_t : 12; + __IM uint32_t LTHLCN : 10; /*!< [25..16] L3 Learn Collision Number */ + uint32_t : 5; + __IM uint32_t LTHTL : 1; /*!< [31..31] L3 Table Learn */ + } FWLTHTLR_b; + }; + __IM uint32_t RESERVED97[2]; + + union + { + __IOM uint32_t FWLTHTIM; /*!< (@ 0x000040E0) L3 Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t LTHTIOG : 1; /*!< [0..0] L3 Table Initialization Ongoing */ + __IM uint32_t LTHTR : 1; /*!< [1..1] L3 Table Ready */ + uint32_t : 30; + } FWLTHTIM_b; + }; + + union + { + __IM uint32_t FWLTHTEM; /*!< (@ 0x000040E4) L3 Table Entry Monitoring Register */ + + struct + { + __IM uint32_t LTHTEN : 11; /*!< [10..0] L3 Table Entry Number */ + uint32_t : 5; + __IM uint32_t LTHTUEN : 11; /*!< [26..16] L3 Table Unsecure Entry Number */ + uint32_t : 5; + } FWLTHTEM_b; + }; + __IM uint32_t RESERVED98[6]; + + union + { + __IOM uint32_t FWLTHTS0; /*!< (@ 0x00004100) L3 Table Search Register 0 */ + + struct + { + __IOM uint32_t LTHSSP0 : 3; /*!< [2..0] L3 Stream Search Part 0 */ + uint32_t : 21; + __IOM uint32_t LTHSSPFS : 1; /*!< [24..24] L3 Stream Search Perfect Filter Select */ + uint32_t : 7; + } FWLTHTS0_b; + }; + + union + { + __IOM uint32_t FWLTHTS1; /*!< (@ 0x00004104) L3 Table Search Register 1 */ + + struct + { + __IOM uint32_t LTHSSP1 : 32; /*!< [31..0] L3 Stream Search Part 1 */ + } FWLTHTS1_b; + }; + + union + { + __IOM uint32_t FWLTHTS2; /*!< (@ 0x00004108) L3 Table Search Register 2 */ + + struct + { + __IOM uint32_t LTHSSP2 : 32; /*!< [31..0] L3 Stream Search Part 2 */ + } FWLTHTS2_b; + }; + + union + { + __IOM uint32_t FWLTHTS3; /*!< (@ 0x0000410C) L3 Table Search Register 3 */ + + struct + { + __IOM uint32_t LTHSSP3 : 32; /*!< [31..0] L3 Stream Search Part 3 */ + } FWLTHTS3_b; + }; + + union + { + __IOM uint32_t FWLTHTS4; /*!< (@ 0x00004110) L3 Table Search Register 4 */ + + struct + { + __IOM uint32_t LTHSSP4 : 32; /*!< [31..0] L3 Stream Search Part 4 */ + } FWLTHTS4_b; + }; + __IM uint32_t RESERVED99[3]; + + union + { + __IOM uint32_t FWLTHTSR0; /*!< (@ 0x00004120) L3 Table Search Result Register 0 */ + + struct + { + __IOM uint32_t LTHSEF : 1; /*!< [0..0] L3 Search ECC Fail */ + __IM uint32_t LTHSNF : 1; /*!< [1..1] L3 Search Not found */ + uint32_t : 6; + __IM uint32_t LTHSLS : 1; /*!< [8..8] L3 Security Level Search */ + uint32_t : 7; + __IM uint32_t LTHSCN : 10; /*!< [25..16] L3 Search Collision Number */ + uint32_t : 5; + __IM uint32_t LTHTS : 1; /*!< [31..31] L3 Table Search */ + } FWLTHTSR0_b; + }; + + union + { + __IM uint32_t FWLTHTSR1; /*!< (@ 0x00004124) L3 Table Search Result Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t LTHMSDUNS : 4; /*!< [19..16] L3 MSDU Number Search */ + uint32_t : 11; + __IM uint32_t LTHMSDUVS : 1; /*!< [31..31] L3 MSDU Valid Search */ + } FWLTHTSR1_b; + }; + + union + { + __IM uint32_t FWLTHTSR2; /*!< (@ 0x00004128) L3 Table Search Result Register 2 */ + + struct + { + __IM uint32_t LTHFRERNS : 6; /*!< [5..0] L3 FRER Number Search */ + uint32_t : 9; + __IM uint32_t LTHFRERVS : 1; /*!< [15..15] L3 FRER Valid Search */ + __IM uint32_t LTHMTRNS : 5; /*!< [20..16] L3 MeTeR Number Search */ + uint32_t : 10; + __IM uint32_t LTHMTRVS : 1; /*!< [31..31] L3 MeTeR Valid Search */ + } FWLTHTSR2_b; + }; + + union + { + __IM uint32_t FWLTHTSR3; /*!< (@ 0x0000412C) L3 Table Search Result Register 3 */ + + struct + { + __IM uint32_t LTHRNS : 8; /*!< [7..0] L3 Routing Number Search */ + uint32_t : 7; + __IM uint32_t LTHRVS : 1; /*!< [15..15] L3 Routing Valid Search */ + __IM uint32_t LTHSLVS : 7; /*!< [22..16] L3 Source Lock Vector Search */ + uint32_t : 9; + } FWLTHTSR3_b; + }; + + union + { + __IM uint32_t FWLTHTSR40; /*!< (@ 0x00004130) L3 Table Search Result Register 40 */ + + struct + { + __IM uint32_t LTHCSDS : 7; /*!< [6..0] L3 CPU Sub-Destination Search */ + uint32_t : 25; + } FWLTHTSR40_b; + }; + __IM uint32_t RESERVED100[3]; + + union + { + __IM uint32_t FWLTHTSR5; /*!< (@ 0x00004140) L3 Table Search Result Register 5 */ + + struct + { + __IM uint32_t LTHDVS : 7; /*!< [6..0] L3 Destination Vector Search */ + uint32_t : 9; + __IM uint32_t LTHIPVS : 3; /*!< [18..16] L3 Internal Priority Value Search */ + __IM uint32_t LTHIPUS : 1; /*!< [19..19] L3 Internal Priority Update Search */ + __IM uint32_t LTHEMES : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Search */ + __IM uint32_t LTHCMES : 1; /*!< [21..21] L3 CPU Mirroring Enable Search */ + uint32_t : 10; + } FWLTHTSR5_b; + }; + __IM uint32_t RESERVED101[3]; + + union + { + __IOM uint32_t FWLTHTR; /*!< (@ 0x00004150) L3 Table Read Register */ + + struct + { + __IOM uint32_t LTHAR : 10; /*!< [9..0] L3 Address Read */ + uint32_t : 22; + } FWLTHTR_b; + }; + + union + { + __IM uint32_t FWLTHTRR0; /*!< (@ 0x00004154) L3 Table Read Result Register 0 */ + + struct + { + __IM uint32_t LTHREF : 1; /*!< [0..0] L3 Read ECC Fail */ + __IM uint32_t LTHEVR : 1; /*!< [1..1] L3 Entry Valid Read */ + uint32_t : 29; + __IM uint32_t LTHTR : 1; /*!< [31..31] L3 Table Read */ + } FWLTHTRR0_b; + }; + + union + { + __IM uint32_t FWLTHTRR1; /*!< (@ 0x00004158) L3 Table Read Result Register 1 */ + + struct + { + __IM uint32_t LTHSRP0 : 3; /*!< [2..0] L3 Stream Read Part 0 */ + uint32_t : 5; + __IM uint32_t LTHSLR : 1; /*!< [8..8] L3 Security Level Read */ + uint32_t : 23; + } FWLTHTRR1_b; + }; + + union + { + __IM uint32_t FWLTHTRR2; /*!< (@ 0x0000415C) L3 Table Read Result Register 2 */ + + struct + { + __IM uint32_t LTHSRP1 : 32; /*!< [31..0] L3 Stream Read Part 1 */ + } FWLTHTRR2_b; + }; + + union + { + __IM uint32_t FWLTHTRR3; /*!< (@ 0x00004160) L3 Table Read Result Register 3 */ + + struct + { + __IM uint32_t LTHSRP2 : 32; /*!< [31..0] L3 Stream Read Part 2 */ + } FWLTHTRR3_b; + }; + + union + { + __IM uint32_t FWLTHTRR4; /*!< (@ 0x00004164) L3 Table Read Result Register 4 */ + + struct + { + __IM uint32_t LTHSRP3 : 32; /*!< [31..0] L3 Stream Read Part 3 */ + } FWLTHTRR4_b; + }; + + union + { + __IM uint32_t FWLTHTRR5; /*!< (@ 0x00004168) L3 Table Read Result Register 5 */ + + struct + { + __IM uint32_t LTHSRP4 : 32; /*!< [31..0] L3 Stream Read Part 4 */ + } FWLTHTRR5_b; + }; + + union + { + __IM uint32_t FWLTHTRR6; /*!< (@ 0x0000416C) L3 Table Read Result Register 6 */ + + struct + { + uint32_t : 16; + __IM uint32_t LTHMSDUNR : 4; /*!< [19..16] L3 MSDU Number Read */ + uint32_t : 11; + __IM uint32_t LTHMSDUVR : 1; /*!< [31..31] L3 MSDU Valid Read */ + } FWLTHTRR6_b; + }; + + union + { + __IM uint32_t FWLTHTRR7; /*!< (@ 0x00004170) L3 Table Read Result Register 7 */ + + struct + { + __IM uint32_t LTHFRERNR : 6; /*!< [5..0] L3 FRER Number Read */ + uint32_t : 9; + __IM uint32_t LTHFRERVR : 1; /*!< [15..15] L3 FRER Valid Read */ + __IM uint32_t LTHMTRNR : 5; /*!< [20..16] L3 MeTeR Number Read */ + uint32_t : 10; + __IM uint32_t LTHMTRVR : 1; /*!< [31..31] L3 MeTeR Valid Read */ + } FWLTHTRR7_b; + }; + + union + { + __IM uint32_t FWLTHTRR8; /*!< (@ 0x00004174) L3 Table Read Result Register 8 */ + + struct + { + __IM uint32_t LTHRNR : 8; /*!< [7..0] L3 Routing Number Read */ + uint32_t : 7; + __IM uint32_t LTHRVR : 1; /*!< [15..15] L3 Routing Valid Read */ + __IM uint32_t LTHSLVR : 7; /*!< [22..16] L3 Source Lock Vector Read */ + uint32_t : 9; + } FWLTHTRR8_b; + }; + __IM uint32_t RESERVED102[2]; + + union + { + __IM uint32_t FWLTHTRR90; /*!< (@ 0x00004180) L3 Table Read Result Register 90 */ + + struct + { + __IM uint32_t LTHCSDR : 7; /*!< [6..0] L3 CPU Sub-Destination Read */ + uint32_t : 25; + } FWLTHTRR90_b; + }; + __IM uint32_t RESERVED103[3]; + + union + { + __IM uint32_t FWLTHTRR10; /*!< (@ 0x00004190) L3 Table Read Result Register 10 */ + + struct + { + __IM uint32_t LTHDVR : 7; /*!< [6..0] L3 Destination Vector Read */ + uint32_t : 9; + __IM uint32_t LTHIPVR : 3; /*!< [18..16] L3 Internal Priority Value Read */ + __IM uint32_t LTHIPUR : 1; /*!< [19..19] L3 Internal Priority Update Read */ + __IM uint32_t LTHEMER : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Read */ + __IM uint32_t LTHCMER : 1; /*!< [21..21] L3 CPU Mirroring Enable Read */ + uint32_t : 10; + } FWLTHTRR10_b; + }; + __IM uint32_t RESERVED104[291]; + + union + { + __IOM uint32_t FWMACHEC; /*!< (@ 0x00004620) MAC Hash Entry Configuration Register */ + + struct + { + __IOM uint32_t MACHMC : 11; /*!< [10..0] MAC Hash Maximum Collision */ + uint32_t : 5; + __IOM uint32_t MACHMUE : 12; /*!< [27..16] MAC Hash Maximum Unsecure Entry */ + uint32_t : 4; + } FWMACHEC_b; + }; + + union + { + __IOM uint32_t FWMACHC; /*!< (@ 0x00004624) MAC Hash Configuration Register */ + + struct + { + __IOM uint32_t MACHE : 11; /*!< [10..0] MAC Hash Equation */ + uint32_t : 21; + } FWMACHC_b; + }; + __IM uint32_t RESERVED105[2]; + + union + { + __IOM uint32_t FWMACTL0; /*!< (@ 0x00004630) MAC Table Learn Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t MACSLL : 1; /*!< [8..8] MAC Security Level Learn */ + __IOM uint32_t MACDEL : 1; /*!< [9..9] MAC Dynamic Entry Limit */ + __IOM uint32_t MACHLDL : 1; /*!< [10..10] MAC Hardware Learning Disable Learn */ + uint32_t : 5; + __IOM uint32_t MACED : 1; /*!< [16..16] MAC Entry Delete */ + uint32_t : 15; + } FWMACTL0_b; + }; + + union + { + __IOM uint32_t FWMACTL1; /*!< (@ 0x00004634) MAC Table Learn Register 1 */ + + struct + { + __IOM uint32_t MACMALP0 : 16; /*!< [15..0] MAC MAC address Learn Part 0 */ + uint32_t : 16; + } FWMACTL1_b; + }; + + union + { + __IOM uint32_t FWMACTL2; /*!< (@ 0x00004638) MAC Table Learn Register 2 */ + + struct + { + __IOM uint32_t MACMALP1 : 32; /*!< [31..0] MAC MAC address Learn Part 1 */ + } FWMACTL2_b; + }; + + union + { + __IOM uint32_t FWMACTL3; /*!< (@ 0x0000463C) MAC Table Learn Register 3 */ + + struct + { + __IOM uint32_t MACSSLVL : 7; /*!< [6..0] MAC Source Source Lock Vector Learn */ + uint32_t : 9; + __IOM uint32_t MACDSLVL : 7; /*!< [22..16] MAC Destination Source Lock Vector Learn */ + uint32_t : 9; + } FWMACTL3_b; + }; + + union + { + __IOM uint32_t FWMACTL40; /*!< (@ 0x00004640) MAC Table Learn Register 40 */ + + struct + { + __IOM uint32_t MACCSDL : 7; /*!< [6..0] MAC CPU Sub-Destination Learn */ + uint32_t : 25; + } FWMACTL40_b; + }; + __IM uint32_t RESERVED106[3]; + + union + { + __IOM uint32_t FWMACTL5; /*!< (@ 0x00004650) MAC Table Learn Register 5 */ + + struct + { + __IOM uint32_t MACDVL : 7; /*!< [6..0] MAC Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t MACIPVL : 3; /*!< [18..16] MAC Internal Priority Value Learn */ + __IOM uint32_t MACIPUL : 1; /*!< [19..19] MAC Internal Priority Update Learn */ + __IOM uint32_t MACEMEL : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Learn */ + __IOM uint32_t MACCMEL : 1; /*!< [21..21] MAC CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWMACTL5_b; + }; + + union + { + __IM uint32_t FWMACTLR; /*!< (@ 0x00004654) MAC Table Learn Result Register */ + + struct + { + __IM uint32_t MACLF : 1; /*!< [0..0] MAC Learn Fail */ + __IM uint32_t MACLSF : 1; /*!< [1..1] MAC Learn Security Fail */ + __IM uint32_t MACLEF : 1; /*!< [2..2] MAC Learn ECC Fail */ + __IM uint32_t MACLO : 1; /*!< [3..3] MAC Learn Overwrite */ + uint32_t : 12; + __IM uint32_t MACLCN : 10; /*!< [25..16] MAC Learn Collision Number */ + uint32_t : 5; + __IM uint32_t MACTL : 1; /*!< [31..31] MAC Table Learn */ + } FWMACTLR_b; + }; + __IM uint32_t RESERVED107[2]; + + union + { + __IOM uint32_t FWMACTIM; /*!< (@ 0x00004660) MAC Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t MACTIOG : 1; /*!< [0..0] MAC Table Initialization Ongoing */ + __IM uint32_t MACTR : 1; /*!< [1..1] MAC Table Ready */ + uint32_t : 30; + } FWMACTIM_b; + }; + + union + { + __IM uint32_t FWMACTEM; /*!< (@ 0x00004664) MAC Table Entry Monitoring Register */ + + struct + { + __IM uint32_t MACTEN : 11; /*!< [10..0] MAC Table Entry Number */ + uint32_t : 5; + __IM uint32_t MACTUEN : 11; /*!< [26..16] MAC Table Unsecure Entry Number */ + uint32_t : 5; + } FWMACTEM_b; + }; + __IM uint32_t RESERVED108[2]; + + union + { + __IOM uint32_t FWMACTS0; /*!< (@ 0x00004670) MAC Table Search Register 0 */ + + struct + { + __IOM uint32_t MACMASP0 : 16; /*!< [15..0] MAC MAC Address Search Part 0 */ + uint32_t : 16; + } FWMACTS0_b; + }; + + union + { + __IOM uint32_t FWMACTS1; /*!< (@ 0x00004674) MAC Table Search Register 1 */ + + struct + { + __IOM uint32_t MACMASP1 : 32; /*!< [31..0] MAC MAC Address Search Part 1 */ + } FWMACTS1_b; + }; + + union + { + __IOM uint32_t FWMACTSR0; /*!< (@ 0x00004678) MAC Table Search Result Register 0 */ + + struct + { + __IOM uint32_t MACSEF : 1; /*!< [0..0] MAC Search ECC Fail */ + __IM uint32_t MACSNF : 1; /*!< [1..1] MAC Search Not found */ + uint32_t : 6; + __IM uint32_t MACSLS : 1; /*!< [8..8] MAC Security Level Search */ + __IM uint32_t MACDES : 1; /*!< [9..9] MAC Dynamic Entry Search */ + __IM uint32_t MACHLDS : 1; /*!< [10..10] MAC Hardware Learning Disable Search */ + uint32_t : 5; + __IM uint32_t MACSCN : 10; /*!< [25..16] MAC Search Collision Number */ + uint32_t : 5; + __IM uint32_t MACTS : 1; /*!< [31..31] MAC Table Search */ + } FWMACTSR0_b; + }; + + union + { + __IM uint32_t FWMACTSR1; /*!< (@ 0x0000467C) MAC Table Search Result Register 1 */ + + struct + { + __IM uint32_t MACSSLVS : 7; /*!< [6..0] MAC Source Source Lock Vector Search */ + uint32_t : 9; + __IM uint32_t MACDSLVS : 7; /*!< [22..16] MAC Destination Source Lock Vector Search */ + uint32_t : 9; + } FWMACTSR1_b; + }; + + union + { + __IM uint32_t FWMACTSR20; /*!< (@ 0x00004680) MAC Table Search Result Register 20 */ + + struct + { + __IM uint32_t MACCSDS : 7; /*!< [6..0] MAC CPU Sub-Destination Search */ + uint32_t : 25; + } FWMACTSR20_b; + }; + __IM uint32_t RESERVED109[3]; + + union + { + __IM uint32_t FWMACTSR3; /*!< (@ 0x00004690) MAC Table Search Result Register 3 */ + + struct + { + __IM uint32_t MACDVS : 7; /*!< [6..0] MAC Destination Vector Search */ + uint32_t : 9; + __IM uint32_t MACIPVS : 3; /*!< [18..16] MAC Internal Priority Value Search */ + __IM uint32_t MACIPUS : 1; /*!< [19..19] MAC Internal Priority Update Search */ + __IM uint32_t MACEMES : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Search */ + __IM uint32_t MACCMES : 1; /*!< [21..21] MAC CPU Mirroring Enable Search */ + uint32_t : 10; + } FWMACTSR3_b; + }; + __IM uint32_t RESERVED110[3]; + + union + { + __IOM uint32_t FWMACTR; /*!< (@ 0x000046A0) MAC Table Read Register */ + + struct + { + __IOM uint32_t MACAR : 10; /*!< [9..0] MAC Address Read */ + uint32_t : 22; + } FWMACTR_b; + }; + + union + { + __IM uint32_t FWMACTRR0; /*!< (@ 0x000046A4) MAC Table Read Result Register 0 */ + + struct + { + __IM uint32_t MACEVR : 1; /*!< [0..0] MAC Entry Valid Read */ + __IM uint32_t MACREF : 1; /*!< [1..1] MAC Read ECC Fail */ + uint32_t : 29; + __IM uint32_t MACTR : 1; /*!< [31..31] MAC Table Read */ + } FWMACTRR0_b; + }; + + union + { + __IM uint32_t FWMACTRR1; /*!< (@ 0x000046A8) MAC Table Read Result Register 1 */ + + struct + { + uint32_t : 8; + __IM uint32_t MACSLR : 1; /*!< [8..8] MAC Security Level Read */ + __IM uint32_t MACDER : 1; /*!< [9..9] MAC Dynamic Entry Read */ + __IM uint32_t MACHLDR : 1; /*!< [10..10] MAC Hardware Learn Disable Read */ + __IM uint32_t MACABR : 1; /*!< [11..11] MAC Aging Bit Read */ + uint32_t : 20; + } FWMACTRR1_b; + }; + + union + { + __IM uint32_t FWMACTRR2; /*!< (@ 0x000046AC) MAC Table Read Result Register 2 */ + + struct + { + __IM uint32_t MACMARP0 : 16; /*!< [15..0] MAC MAC address Read Part 0 */ + uint32_t : 16; + } FWMACTRR2_b; + }; + + union + { + __IM uint32_t FWMACTRR3; /*!< (@ 0x000046B0) MAC Table Read Result Register 3 */ + + struct + { + __IM uint32_t MACMARP1 : 32; /*!< [31..0] MAC MAC address Read Part 1 */ + } FWMACTRR3_b; + }; + + union + { + __IM uint32_t FWMACTRR4; /*!< (@ 0x000046B4) MAC Table Read Result Register 4 */ + + struct + { + __IM uint32_t MACSSLVR : 7; /*!< [6..0] MAC Source Source Lock Vector Read */ + uint32_t : 9; + __IM uint32_t MACDSLVR : 7; /*!< [22..16] MAC Destination Source Lock Vector Read */ + uint32_t : 9; + } FWMACTRR4_b; + }; + __IM uint32_t RESERVED111[2]; + + union + { + __IM uint32_t FWMACTRR50; /*!< (@ 0x000046C0) MAC Table Read Result Register 50 */ + + struct + { + __IM uint32_t MACCSDR : 7; /*!< [6..0] MAC CPU Sub-Destination Read */ + uint32_t : 25; + } FWMACTRR50_b; + }; + __IM uint32_t RESERVED112[3]; + + union + { + __IM uint32_t FWMACTRR6; /*!< (@ 0x000046D0) MAC Table Read Result Register 6 */ + + struct + { + __IM uint32_t MACDVR : 7; /*!< [6..0] MAC Destination Vector Read */ + uint32_t : 9; + __IM uint32_t MACIPVR : 3; /*!< [18..16] MAC Internal Priority Value Read */ + __IM uint32_t MACIPUR : 1; /*!< [19..19] MAC Internal Priority Update Read */ + __IM uint32_t MACEMER : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Read */ + __IM uint32_t MACCMER : 1; /*!< [21..21] MAC CPU Mirroring Enable Read */ + uint32_t : 10; + } FWMACTRR6_b; + }; + __IM uint32_t RESERVED113[107]; + + union + { + __IOM uint32_t FWMACAGUSPC; /*!< (@ 0x00004880) MAC Aging US Prescaler Configuration Register */ + + struct + { + __IOM uint32_t MACAGUSP : 10; /*!< [9..0] MAC Aging US prescaler */ + uint32_t : 22; + } FWMACAGUSPC_b; + }; + + union + { + __IOM uint32_t FWMACAGC; /*!< (@ 0x00004884) MAC Aging Configuration Register */ + + struct + { + __IOM uint32_t MACAGT : 16; /*!< [15..0] MAC Aging Time */ + __IOM uint32_t MACAGE : 1; /*!< [16..16] MAC Aging Enable */ + __IOM uint32_t MACAGSL : 1; /*!< [17..17] MAC Aging Security Level */ + __IOM uint32_t MACAGPM : 1; /*!< [18..18] MAC Aging Polling Mode */ + uint32_t : 5; + __IM uint32_t MACDES : 1; /*!< [24..24] MAC Dynamic Entry Suppression */ + uint32_t : 3; + __IM uint32_t MACAGOG : 1; /*!< [28..28] MAC Aging OnGoing */ + __IM uint32_t MACDESOG : 1; /*!< [29..29] MAC Dynamic Entry Suppression OnGoing */ + uint32_t : 2; + } FWMACAGC_b; + }; + + union + { + __IM uint32_t FWMACAGM0; /*!< (@ 0x00004888) MAC Aging Monitoring Register 0 */ + + struct + { + __IM uint32_t AGMACAP0 : 16; /*!< [15..0] Aged MAC Address Part 0 */ + uint32_t : 16; + } FWMACAGM0_b; + }; + + union + { + __IM uint32_t FWMACAGM1; /*!< (@ 0x0000488C) MAC Aging Monitoring Register 1 */ + + struct + { + __IM uint32_t AGMACAP1 : 32; /*!< [31..0] Aged MAC Address Part 1 */ + } FWMACAGM1_b; + }; + __IM uint32_t RESERVED114[28]; + + union + { + __IOM uint32_t FWVLANTEC; /*!< (@ 0x00004900) VLAN Table Entry Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t VLANTMUE : 13; /*!< [28..16] VLAN Table Maximum Unsecure Entry */ + uint32_t : 3; + } FWVLANTEC_b; + }; + __IM uint32_t RESERVED115[3]; + + union + { + __IOM uint32_t FWVLANTL0; /*!< (@ 0x00004910) VLAN Table Learn Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t VLANSLL : 1; /*!< [8..8] VLAN Security Level Learn */ + uint32_t : 1; + __IOM uint32_t VLANHLDL : 1; /*!< [10..10] VLAN Hardware Learning Disable Learn */ + uint32_t : 5; + __IOM uint32_t VLANED : 1; /*!< [16..16] VLAN Entry Delete */ + uint32_t : 15; + } FWVLANTL0_b; + }; + + union + { + __IOM uint32_t FWVLANTL1; /*!< (@ 0x00004914) VLAN Table Learn Register 1 */ + + struct + { + __IOM uint32_t VLANVIDL : 12; /*!< [11..0] VLAN VID Learn */ + uint32_t : 20; + } FWVLANTL1_b; + }; + + union + { + __IOM uint32_t FWVLANTL2; /*!< (@ 0x00004918) VLAN Table Learn Register 2 */ + + struct + { + __IOM uint32_t VLANSLVL : 7; /*!< [6..0] VLAN Source Lock Vector Learn */ + uint32_t : 25; + } FWVLANTL2_b; + }; + __IM uint32_t RESERVED116; + + union + { + __IOM uint32_t FWVLANTL30; /*!< (@ 0x00004920) VLAN Table Learn Register 30 */ + + struct + { + __IOM uint32_t VLANCSDL : 7; /*!< [6..0] VLAN CPU Sub-Destination Learn */ + uint32_t : 25; + } FWVLANTL30_b; + }; + __IM uint32_t RESERVED117[3]; + + union + { + __IOM uint32_t FWVLANTL4; /*!< (@ 0x00004930) VLAN Table Learn Register 4 */ + + struct + { + __IOM uint32_t VLANDVL : 7; /*!< [6..0] VLAN Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t VLANIPVL : 3; /*!< [18..16] VLAN Internal Priority Value Learn */ + __IOM uint32_t VLANIPUL : 1; /*!< [19..19] VLAN Internal Priority Update Learn */ + __IOM uint32_t VLANEMEL : 1; /*!< [20..20] VLAN Ethernet Mirroring Enable Learn */ + __IOM uint32_t VLANCMEL : 1; /*!< [21..21] VLAN CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWVLANTL4_b; + }; + + union + { + __IM uint32_t FWVLANTLR; /*!< (@ 0x00004934) VLAN Table Learn Result Register */ + + struct + { + __IM uint32_t VLANLF : 1; /*!< [0..0] VLAN Learn Fail */ + __IM uint32_t VLANLSF : 1; /*!< [1..1] VLAN Learn Security Fail */ + __IM uint32_t VLANLEF : 1; /*!< [2..2] VLAN Learn ECC Fail */ + __IM uint32_t VLANLO : 1; /*!< [3..3] VLAN Learn Overwrite */ + uint32_t : 27; + __IM uint32_t VLANTL : 1; /*!< [31..31] VLAN Table Learn */ + } FWVLANTLR_b; + }; + __IM uint32_t RESERVED118[2]; + + union + { + __IOM uint32_t FWVLANTIM; /*!< (@ 0x00004940) VLAN Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t VLANTIOG : 1; /*!< [0..0] VLAN Table Initialization Ongoing */ + __IM uint32_t VLANTR : 1; /*!< [1..1] VLAN Table Ready */ + uint32_t : 30; + } FWVLANTIM_b; + }; + + union + { + __IM uint32_t FWVLANTEM; /*!< (@ 0x00004944) VLAN Table Entry Monitoring Register */ + + struct + { + __IM uint32_t VLANTEN : 13; /*!< [12..0] VLAN Table Entry Number */ + uint32_t : 3; + __IM uint32_t VLANTUEN : 13; /*!< [28..16] VLAN Table Unsecure Entry Number */ + uint32_t : 3; + } FWVLANTEM_b; + }; + __IM uint32_t RESERVED119[2]; + + union + { + __IOM uint32_t FWVLANTS; /*!< (@ 0x00004950) VLAN Table Search Register */ + + struct + { + __IOM uint32_t VLANVIDS : 12; /*!< [11..0] VLAN VID Search */ + uint32_t : 20; + } FWVLANTS_b; + }; + + union + { + __IM uint32_t FWVLANTSR0; /*!< (@ 0x00004954) VLAN Table Search Result Register 0 */ + + struct + { + __IM uint32_t VLANSEF : 1; /*!< [0..0] VLAN Search ECC Fail */ + __IM uint32_t VLANSNF : 1; /*!< [1..1] VLAN Search Not found */ + uint32_t : 6; + __IM uint32_t VLANSLS : 1; /*!< [8..8] VLAN Security Level Search */ + uint32_t : 1; + __IM uint32_t VLANHLDS : 1; /*!< [10..10] VLAN Hardware Learning Disable Search */ + uint32_t : 20; + __IM uint32_t VLANTS : 1; /*!< [31..31] VLAN Table Search */ + } FWVLANTSR0_b; + }; + + union + { + __IM uint32_t FWVLANTSR1; /*!< (@ 0x00004958) VLAN Table Search Result Register 1 */ + + struct + { + __IM uint32_t VLANSLVS : 7; /*!< [6..0] VLAN Source Lock Vector Search */ + uint32_t : 25; + } FWVLANTSR1_b; + }; + __IM uint32_t RESERVED120; + + union + { + __IM uint32_t FWVLANTSR20; /*!< (@ 0x00004960) VLAN Table Search Result Register 20 */ + + struct + { + __IM uint32_t VLANCSDS : 7; /*!< [6..0] VLAN CPU Sub-Destination Search */ + uint32_t : 25; + } FWVLANTSR20_b; + }; + __IM uint32_t RESERVED121[3]; + + union + { + __IM uint32_t FWVLANTSR3; /*!< (@ 0x00004970) VLAN Table Search Result Register 3 */ + + struct + { + __IM uint32_t VLANDVS : 7; /*!< [6..0] VLAN Destination Vector Search */ + uint32_t : 9; + __IM uint32_t VLANIPVS : 3; /*!< [18..16] VLAN Internal Priority Value Search */ + __IM uint32_t VLANIPUS : 1; /*!< [19..19] VLAN Internal Priority Update Search */ + __IM uint32_t VLANEMES : 1; /*!< [20..20] VLAN Ethernet Mirroring Enable Search */ + __IM uint32_t VLANCMES : 1; /*!< [21..21] VLAN CPU Mirroring Enable Search */ + uint32_t : 10; + } FWVLANTSR3_b; + }; + __IM uint32_t RESERVED122[35]; + + union + { + __IOM uint32_t FWPBFC0; /*!< (@ 0x00004A00) Port Based Forwarding Configuration Register + * 0 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC0_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC00; /*!< (@ 0x00004A04) Port Based Forwarding CSD Configuration Register + * 00 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC00_b; + }; + __IM uint32_t RESERVED123[2]; + + union + { + __IOM uint32_t FWPBFC1; /*!< (@ 0x00004A10) Port Based Forwarding Configuration Register + * 1 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC1_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC01; /*!< (@ 0x00004A14) Port Based Forwarding CSD Configuration Register + * 01 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC01_b; + }; + __IM uint32_t RESERVED124[2]; + + union + { + __IOM uint32_t FWPBFC2; /*!< (@ 0x00004A20) Port Based Forwarding Configuration Register + * 2 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC2_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC02; /*!< (@ 0x00004A24) Port Based Forwarding CSD Configuration Register + * 02 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC02_b; + }; + __IM uint32_t RESERVED125[246]; + + union + { + __IOM uint32_t FWL23URL0; /*!< (@ 0x00004E00) Layer 2/Layer 3 Update Rule Learn Register 0 */ + + struct + { + __IOM uint32_t L23URNL : 8; /*!< [7..0] Layer 2/Layer 3 Update Routing Number Learn */ + uint32_t : 8; + __IOM uint32_t L23URPVL : 7; /*!< [22..16] Layer 2/Layer 3 Update Routing Port Valid Learn */ + uint32_t : 9; + } FWL23URL0_b; + }; + + union + { + __IOM uint32_t FWL23URL1; /*!< (@ 0x00004E04) Layer 2/Layer 3 Update Rule Learn Register 1 */ + + struct + { + __IOM uint32_t L23UMDALP0 : 16; /*!< [15..0] Layer 2/Layer 3 Update MAC Destination Address Learn + * Part 0 */ + __IOM uint32_t L23UTTLUL : 1; /*!< [16..16] Layer 2/Layer 3 Update Time To Live Update Learn */ + __IOM uint32_t L23UMDAUL : 1; /*!< [17..17] Layer 2/Layer 3 Update MAC Destination Address Update + * Learn */ + __IOM uint32_t L23UMSAUL : 1; /*!< [18..18] Layer 2/Layer 3 Update MAC Source Address Update Learn */ + __IOM uint32_t L23UCVIDUL : 1; /*!< [19..19] Layer 2/Layer 3 Update C-TAG VID Update Learn */ + __IOM uint32_t L23UCPCPUL : 1; /*!< [20..20] Layer 2/Layer 3 Update C-TAG PCP Update Learn */ + __IOM uint32_t L23UCDEIUL : 1; /*!< [21..21] Layer 2/Layer 3 Update C-TAG DEI Update Learn */ + __IOM uint32_t L23USVIDUL : 1; /*!< [22..22] Layer 2/Layer 3 Update S-TAG VID Update Learn */ + __IOM uint32_t L23USPCPUL : 1; /*!< [23..23] Layer 2/Layer 3 Update S-TAG PCP Update Learn */ + __IOM uint32_t L23USDEIUL : 1; /*!< [24..24] Layer 2/Layer 3 Update S-TAG DEI Update Learn */ + __IOM uint32_t L23URTUL : 2; /*!< [26..25] Layer 2/Layer 3 Update R-TAG Update Learn */ + uint32_t : 5; + } FWL23URL1_b; + }; + + union + { + __IOM uint32_t FWL23URL2; /*!< (@ 0x00004E08) Layer 2/Layer 3 Update Rule Learn Register 2 */ + + struct + { + __IOM uint32_t L23UMDALP1 : 32; /*!< [31..0] Layer 2/Layer 3 Update MAC Destination Address Learn + * Part 1 */ + } FWL23URL2_b; + }; + + union + { + __IOM uint32_t FWL23URL3; /*!< (@ 0x00004E0C) Layer 2/Layer 3 Update Rule Learn Register 3 */ + + struct + { + __IOM uint32_t L23UCVIDL : 12; /*!< [11..0] Layer 2/Layer 3 Update C-TAG VID Learn */ + __IOM uint32_t L23UCPCPL : 3; /*!< [14..12] Layer 2/Layer 3 Update C-TAG PCP Learn */ + __IOM uint32_t L23UCDEIL : 1; /*!< [15..15] Layer 2/Layer 3 Update C-TAG DEI Learn */ + __IOM uint32_t L23USVIDL : 12; /*!< [27..16] Layer 2/Layer 3 Update S-TAG VID Learn */ + __IOM uint32_t L23USPCPL : 3; /*!< [30..28] Layer 2/Layer 3 Update S-TAG PCP Learn */ + __IOM uint32_t L23USDEIL : 1; /*!< [31..31] Layer 2/Layer 3 Update S-TAG DEI Learn */ + } FWL23URL3_b; + }; + + union + { + __IM uint32_t FWL23URLR; /*!< (@ 0x00004E10) Layer 2/Layer 3 Update Rule Learn Result Register */ + + struct + { + __IM uint32_t L23ULF : 1; /*!< [0..0] Layer 2/Layer 3 Update Learn Fail */ + uint32_t : 30; + __IM uint32_t L23URL : 1; /*!< [31..31] Layer 2/Layer 3 Update Rule Learn */ + } FWL23URLR_b; + }; + __IM uint32_t RESERVED126[3]; + + union + { + __IOM uint32_t FWL23UTIM; /*!< (@ 0x00004E20) Layer 2/Layer 3 Update Table Initialization Monitoring + * Register */ + + struct + { + __IOM uint32_t L23UTIOG : 1; /*!< [0..0] Layer 2/Layer 3 Update Table Initialization Ongoing */ + __IM uint32_t L23UTR : 1; /*!< [1..1] Layer 2/Layer 3 Update Table Ready */ + uint32_t : 30; + } FWL23UTIM_b; + }; + __IM uint32_t RESERVED127[3]; + + union + { + __IOM uint32_t FWL23URR; /*!< (@ 0x00004E30) Layer 2/Layer 3 Update Rule Read Register */ + + struct + { + __IOM uint32_t L23RNR : 8; /*!< [7..0] Layer 2/Layer 3 Routing Number Read */ + uint32_t : 24; + } FWL23URR_b; + }; + + union + { + __IM uint32_t FWL23URRR0; /*!< (@ 0x00004E34) Layer 2/Layer 3 Update Rule Read Result Register + * 0 */ + + struct + { + __IM uint32_t L23URPVR : 7; /*!< [6..0] Layer 2/Layer 3 Update Routing Port Valid Read */ + uint32_t : 9; + __IM uint32_t L23UREF : 1; /*!< [16..16] Layer 2/Layer 3 Update Read ECC Fail */ + uint32_t : 14; + __IM uint32_t L23URR : 1; /*!< [31..31] Layer 2/Layer 3 Update Rule Read */ + } FWL23URRR0_b; + }; + + union + { + __IM uint32_t FWL23URRR1; /*!< (@ 0x00004E38) Layer 2/Layer 3 Update Rule Read Result Register + * 1 */ + + struct + { + __IM uint32_t L23UMDARP0 : 16; /*!< [15..0] Layer 2/Layer 3 MAC Destination Address Read Part 0 */ + __IM uint32_t L23UTTLUR : 1; /*!< [16..16] Layer 2/Layer 3 Time To Live Update Read */ + __IM uint32_t L23UMDAUR : 1; /*!< [17..17] Layer 2/Layer 3 MAC Destination Address Update Read */ + __IM uint32_t L23UMSAUR : 1; /*!< [18..18] Layer 2/Layer 3 MAC Source Address Update Read */ + __IM uint32_t L23UCVIDUR : 1; /*!< [19..19] Layer 2/Layer 3 C-TAG VID Update Read */ + __IM uint32_t L23UCPCPUR : 1; /*!< [20..20] Layer 2/Layer 3 C-TAG PCP Update Read */ + __IM uint32_t L23UCDEIUR : 1; /*!< [21..21] Layer 2/Layer 3 C-TAG DEI Update Read */ + __IM uint32_t L23USVIDUR : 1; /*!< [22..22] Layer 2/Layer 3 S-TAG VID Update Read */ + __IM uint32_t L23USPCPUR : 1; /*!< [23..23] Layer 2/Layer 3 S-TAG PCP Update Read */ + __IM uint32_t L23USDEIUR : 1; /*!< [24..24] Layer 2/Layer 3 S-TAG DEI Update Read */ + __IM uint32_t L23URTUR : 2; /*!< [26..25] Layer 2/Layer 3 R-TAG Update Read */ + uint32_t : 5; + } FWL23URRR1_b; + }; + + union + { + __IM uint32_t FWL23URRR2; /*!< (@ 0x00004E3C) Layer 2/Layer 3 Update Rule Read Result Register + * 2 */ + + struct + { + __IM uint32_t L23UMDARP1 : 32; /*!< [31..0] Layer 2/Layer 3 MAC Destination Address Read Part 1 */ + } FWL23URRR2_b; + }; + + union + { + __IM uint32_t FWL23URRR3; /*!< (@ 0x00004E40) Layer 2/Layer 3 Update Rule Read Result Register + * 3 */ + + struct + { + __IM uint32_t L23UCVIDR : 12; /*!< [11..0] Layer 2/Layer 3 Update MAC C-TAG VID Read */ + __IM uint32_t L23UCPCPR : 3; /*!< [14..12] Layer 2/Layer 3 Update MAC C-TAG PCP Read */ + __IM uint32_t L23UCDEIR : 1; /*!< [15..15] Layer 2/Layer 3 Update MAC C-TAG DEI Read */ + __IM uint32_t L23USVIDR : 12; /*!< [27..16] Layer 2/Layer 3 Update MAC S-TAG VID Read */ + __IM uint32_t L23USPCPR : 3; /*!< [30..28] Layer 2/Layer 3 Update MAC S-TAG PCP Read */ + __IM uint32_t L23USDEIR : 1; /*!< [31..31] Layer 2/Layer 3 Update MAC S-TAG DEI Read */ + } FWL23URRR3_b; + }; + __IM uint32_t RESERVED128[47]; + + union + { + __IOM uint32_t FWL23URMC0; /*!< (@ 0x00004F00) Layer 2/Layer 3 Update ReMapping Configuration + * Register 0 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC0_b; + }; + + union + { + __IOM uint32_t FWL23URMC1; /*!< (@ 0x00004F04) Layer 2/Layer 3 Update ReMapping Configuration + * Register 1 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC1_b; + }; + + union + { + __IOM uint32_t FWL23URMC2; /*!< (@ 0x00004F08) Layer 2/Layer 3 Update ReMapping Configuration + * Register 2 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC2_b; + }; + + union + { + __IOM uint32_t FWL23URMC3; /*!< (@ 0x00004F0C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 3 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC3_b; + }; + + union + { + __IOM uint32_t FWL23URMC4; /*!< (@ 0x00004F10) Layer 2/Layer 3 Update ReMapping Configuration + * Register 4 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC4_b; + }; + + union + { + __IOM uint32_t FWL23URMC5; /*!< (@ 0x00004F14) Layer 2/Layer 3 Update ReMapping Configuration + * Register 5 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC5_b; + }; + + union + { + __IOM uint32_t FWL23URMC6; /*!< (@ 0x00004F18) Layer 2/Layer 3 Update ReMapping Configuration + * Register 6 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC6_b; + }; + + union + { + __IOM uint32_t FWL23URMC7; /*!< (@ 0x00004F1C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 7 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC7_b; + }; + + union + { + __IOM uint32_t FWL23URMC8; /*!< (@ 0x00004F20) Layer 2/Layer 3 Update ReMapping Configuration + * Register 8 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC8_b; + }; + + union + { + __IOM uint32_t FWL23URMC9; /*!< (@ 0x00004F24) Layer 2/Layer 3 Update ReMapping Configuration + * Register 9 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC9_b; + }; + + union + { + __IOM uint32_t FWL23URMC10; /*!< (@ 0x00004F28) Layer 2/Layer 3 Update ReMapping Configuration + * Register 10 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC10_b; + }; + + union + { + __IOM uint32_t FWL23URMC11; /*!< (@ 0x00004F2C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 11 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC11_b; + }; + + union + { + __IOM uint32_t FWL23URMC12; /*!< (@ 0x00004F30) Layer 2/Layer 3 Update ReMapping Configuration + * Register 12 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC12_b; + }; + + union + { + __IOM uint32_t FWL23URMC13; /*!< (@ 0x00004F34) Layer 2/Layer 3 Update ReMapping Configuration + * Register 13 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC13_b; + }; + + union + { + __IOM uint32_t FWL23URMC14; /*!< (@ 0x00004F38) Layer 2/Layer 3 Update ReMapping Configuration + * Register 14 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC14_b; + }; + + union + { + __IOM uint32_t FWL23URMC15; /*!< (@ 0x00004F3C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 15 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC15_b; + }; + + union + { + __IOM uint32_t FWL23URMC16; /*!< (@ 0x00004F40) Layer 2/Layer 3 Update ReMapping Configuration + * Register 16 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC16_b; + }; + + union + { + __IOM uint32_t FWL23URMC17; /*!< (@ 0x00004F44) Layer 2/Layer 3 Update ReMapping Configuration + * Register 17 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC17_b; + }; + + union + { + __IOM uint32_t FWL23URMC18; /*!< (@ 0x00004F48) Layer 2/Layer 3 Update ReMapping Configuration + * Register 18 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC18_b; + }; + + union + { + __IOM uint32_t FWL23URMC19; /*!< (@ 0x00004F4C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 19 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC19_b; + }; + + union + { + __IOM uint32_t FWL23URMC20; /*!< (@ 0x00004F50) Layer 2/Layer 3 Update ReMapping Configuration + * Register 20 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC20_b; + }; + + union + { + __IOM uint32_t FWL23URMC21; /*!< (@ 0x00004F54) Layer 2/Layer 3 Update ReMapping Configuration + * Register 21 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC21_b; + }; + + union + { + __IOM uint32_t FWL23URMC22; /*!< (@ 0x00004F58) Layer 2/Layer 3 Update ReMapping Configuration + * Register 22 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC22_b; + }; + + union + { + __IOM uint32_t FWL23URMC23; /*!< (@ 0x00004F5C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 23 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC23_b; + }; + + union + { + __IOM uint32_t FWL23URMC24; /*!< (@ 0x00004F60) Layer 2/Layer 3 Update ReMapping Configuration + * Register 24 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC24_b; + }; + + union + { + __IOM uint32_t FWL23URMC25; /*!< (@ 0x00004F64) Layer 2/Layer 3 Update ReMapping Configuration + * Register 25 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC25_b; + }; + + union + { + __IOM uint32_t FWL23URMC26; /*!< (@ 0x00004F68) Layer 2/Layer 3 Update ReMapping Configuration + * Register 26 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC26_b; + }; + + union + { + __IOM uint32_t FWL23URMC27; /*!< (@ 0x00004F6C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 27 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC27_b; + }; + + union + { + __IOM uint32_t FWL23URMC28; /*!< (@ 0x00004F70) Layer 2/Layer 3 Update ReMapping Configuration + * Register 28 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC28_b; + }; + + union + { + __IOM uint32_t FWL23URMC29; /*!< (@ 0x00004F74) Layer 2/Layer 3 Update ReMapping Configuration + * Register 29 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC29_b; + }; + + union + { + __IOM uint32_t FWL23URMC30; /*!< (@ 0x00004F78) Layer 2/Layer 3 Update ReMapping Configuration + * Register 30 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC30_b; + }; + + union + { + __IOM uint32_t FWL23URMC31; /*!< (@ 0x00004F7C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 31 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC31_b; + }; + __IM uint32_t RESERVED129[32]; + + union + { + __IOM uint32_t FWPMFGC0; /*!< (@ 0x00005000) PSFP MSDU Filter Global Configuration Register + * 0 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC0_b; + }; + + union + { + __IOM uint32_t FWPMFGC1; /*!< (@ 0x00005004) PSFP MSDU Filter Global Configuration Register + * 1 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC1_b; + }; + + union + { + __IOM uint32_t FWPMFGC2; /*!< (@ 0x00005008) PSFP MSDU Filter Global Configuration Register + * 2 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC2_b; + }; + + union + { + __IOM uint32_t FWPMFGC3; /*!< (@ 0x0000500C) PSFP MSDU Filter Global Configuration Register + * 3 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC3_b; + }; + + union + { + __IOM uint32_t FWPMFGC4; /*!< (@ 0x00005010) PSFP MSDU Filter Global Configuration Register + * 4 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC4_b; + }; + + union + { + __IOM uint32_t FWPMFGC5; /*!< (@ 0x00005014) PSFP MSDU Filter Global Configuration Register + * 5 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC5_b; + }; + + union + { + __IOM uint32_t FWPMFGC6; /*!< (@ 0x00005018) PSFP MSDU Filter Global Configuration Register + * 6 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC6_b; + }; + + union + { + __IOM uint32_t FWPMFGC7; /*!< (@ 0x0000501C) PSFP MSDU Filter Global Configuration Register + * 7 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC7_b; + }; + + union + { + __IOM uint32_t FWPMFGC8; /*!< (@ 0x00005020) PSFP MSDU Filter Global Configuration Register + * 8 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC8_b; + }; + + union + { + __IOM uint32_t FWPMFGC9; /*!< (@ 0x00005024) PSFP MSDU Filter Global Configuration Register + * 9 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC9_b; + }; + + union + { + __IOM uint32_t FWPMFGC10; /*!< (@ 0x00005028) PSFP MSDU Filter Global Configuration Register + * 10 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC10_b; + }; + + union + { + __IOM uint32_t FWPMFGC11; /*!< (@ 0x0000502C) PSFP MSDU Filter Global Configuration Register + * 11 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC11_b; + }; + + union + { + __IOM uint32_t FWPMFGC12; /*!< (@ 0x00005030) PSFP MSDU Filter Global Configuration Register + * 12 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC12_b; + }; + + union + { + __IOM uint32_t FWPMFGC13; /*!< (@ 0x00005034) PSFP MSDU Filter Global Configuration Register + * 13 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC13_b; + }; + + union + { + __IOM uint32_t FWPMFGC14; /*!< (@ 0x00005038) PSFP MSDU Filter Global Configuration Register + * 14 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC14_b; + }; + + union + { + __IOM uint32_t FWPMFGC15; /*!< (@ 0x0000503C) PSFP MSDU Filter Global Configuration Register + * 15 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC15_b; + }; + __IM uint32_t RESERVED130[368]; + + union + { + __IOM uint32_t FWPMTRFC0; /*!< (@ 0x00005600) PSFP Meter Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC0_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC0; /*!< (@ 0x00005604) PSFP Meter CBS Configuration Register 0 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC0_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC0; /*!< (@ 0x00005608) PSFP Meter CIR Configuration Register 0 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC0_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC0; /*!< (@ 0x0000560C) PSFP Meter EBS Configuration Register 0 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC0_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC0; /*!< (@ 0x00005610) PSFP Meter EIR Configuration Register 0 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC0_b; + }; + + union + { + __IM uint32_t FWPMTRFM0; /*!< (@ 0x00005614) PSFP Meter Filter Monitoring Register 0 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM0_b; + }; + __IM uint32_t RESERVED131[2]; + + union + { + __IOM uint32_t FWPMTRFC1; /*!< (@ 0x00005620) PSFP Meter Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC1_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC1; /*!< (@ 0x00005624) PSFP Meter CBS Configuration Register 1 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC1_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC1; /*!< (@ 0x00005628) PSFP Meter CIR Configuration Register 1 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC1_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC1; /*!< (@ 0x0000562C) PSFP Meter EBS Configuration Register 1 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC1_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC1; /*!< (@ 0x00005630) PSFP Meter EIR Configuration Register 1 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC1_b; + }; + + union + { + __IM uint32_t FWPMTRFM1; /*!< (@ 0x00005634) PSFP Meter Filter Monitoring Register 1 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM1_b; + }; + __IM uint32_t RESERVED132[2]; + + union + { + __IOM uint32_t FWPMTRFC2; /*!< (@ 0x00005640) PSFP Meter Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC2_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC2; /*!< (@ 0x00005644) PSFP Meter CBS Configuration Register 2 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC2_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC2; /*!< (@ 0x00005648) PSFP Meter CIR Configuration Register 2 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC2_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC2; /*!< (@ 0x0000564C) PSFP Meter EBS Configuration Register 2 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC2_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC2; /*!< (@ 0x00005650) PSFP Meter EIR Configuration Register 2 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC2_b; + }; + + union + { + __IM uint32_t FWPMTRFM2; /*!< (@ 0x00005654) PSFP Meter Filter Monitoring Register 2 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM2_b; + }; + __IM uint32_t RESERVED133[2]; + + union + { + __IOM uint32_t FWPMTRFC3; /*!< (@ 0x00005660) PSFP Meter Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC3_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC3; /*!< (@ 0x00005664) PSFP Meter CBS Configuration Register 3 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC3_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC3; /*!< (@ 0x00005668) PSFP Meter CIR Configuration Register 3 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC3_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC3; /*!< (@ 0x0000566C) PSFP Meter EBS Configuration Register 3 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC3_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC3; /*!< (@ 0x00005670) PSFP Meter EIR Configuration Register 3 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC3_b; + }; + + union + { + __IM uint32_t FWPMTRFM3; /*!< (@ 0x00005674) PSFP Meter Filter Monitoring Register 3 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM3_b; + }; + __IM uint32_t RESERVED134[2]; + + union + { + __IOM uint32_t FWPMTRFC4; /*!< (@ 0x00005680) PSFP Meter Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC4_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC4; /*!< (@ 0x00005684) PSFP Meter CBS Configuration Register 4 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC4_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC4; /*!< (@ 0x00005688) PSFP Meter CIR Configuration Register 4 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC4_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC4; /*!< (@ 0x0000568C) PSFP Meter EBS Configuration Register 4 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC4_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC4; /*!< (@ 0x00005690) PSFP Meter EIR Configuration Register 4 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC4_b; + }; + + union + { + __IM uint32_t FWPMTRFM4; /*!< (@ 0x00005694) PSFP Meter Filter Monitoring Register 4 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM4_b; + }; + __IM uint32_t RESERVED135[2]; + + union + { + __IOM uint32_t FWPMTRFC5; /*!< (@ 0x000056A0) PSFP Meter Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC5_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC5; /*!< (@ 0x000056A4) PSFP Meter CBS Configuration Register 5 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC5_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC5; /*!< (@ 0x000056A8) PSFP Meter CIR Configuration Register 5 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC5_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC5; /*!< (@ 0x000056AC) PSFP Meter EBS Configuration Register 5 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC5_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC5; /*!< (@ 0x000056B0) PSFP Meter EIR Configuration Register 5 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC5_b; + }; + + union + { + __IM uint32_t FWPMTRFM5; /*!< (@ 0x000056B4) PSFP Meter Filter Monitoring Register 5 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM5_b; + }; + __IM uint32_t RESERVED136[2]; + + union + { + __IOM uint32_t FWPMTRFC6; /*!< (@ 0x000056C0) PSFP Meter Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC6_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC6; /*!< (@ 0x000056C4) PSFP Meter CBS Configuration Register 6 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC6_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC6; /*!< (@ 0x000056C8) PSFP Meter CIR Configuration Register 6 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC6_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC6; /*!< (@ 0x000056CC) PSFP Meter EBS Configuration Register 6 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC6_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC6; /*!< (@ 0x000056D0) PSFP Meter EIR Configuration Register 6 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC6_b; + }; + + union + { + __IM uint32_t FWPMTRFM6; /*!< (@ 0x000056D4) PSFP Meter Filter Monitoring Register 6 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM6_b; + }; + __IM uint32_t RESERVED137[2]; + + union + { + __IOM uint32_t FWPMTRFC7; /*!< (@ 0x000056E0) PSFP Meter Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC7_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC7; /*!< (@ 0x000056E4) PSFP Meter CBS Configuration Register 7 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC7_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC7; /*!< (@ 0x000056E8) PSFP Meter CIR Configuration Register 7 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC7_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC7; /*!< (@ 0x000056EC) PSFP Meter EBS Configuration Register 7 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC7_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC7; /*!< (@ 0x000056F0) PSFP Meter EIR Configuration Register 7 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC7_b; + }; + + union + { + __IM uint32_t FWPMTRFM7; /*!< (@ 0x000056F4) PSFP Meter Filter Monitoring Register 7 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM7_b; + }; + __IM uint32_t RESERVED138[2]; + + union + { + __IOM uint32_t FWPMTRFC8; /*!< (@ 0x00005700) PSFP Meter Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC8_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC8; /*!< (@ 0x00005704) PSFP Meter CBS Configuration Register 8 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC8_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC8; /*!< (@ 0x00005708) PSFP Meter CIR Configuration Register 8 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC8_b; + }; + __IM uint32_t RESERVED139[2]; + + union + { + __IM uint32_t FWPMTRFM8; /*!< (@ 0x00005714) PSFP Meter Filter Monitoring Register 8 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM8_b; + }; + __IM uint32_t RESERVED140[2]; + + union + { + __IOM uint32_t FWPMTRFC9; /*!< (@ 0x00005720) PSFP Meter Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC9_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC9; /*!< (@ 0x00005724) PSFP Meter CBS Configuration Register 9 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC9_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC9; /*!< (@ 0x00005728) PSFP Meter CIR Configuration Register 9 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC9_b; + }; + __IM uint32_t RESERVED141[2]; + + union + { + __IM uint32_t FWPMTRFM9; /*!< (@ 0x00005734) PSFP Meter Filter Monitoring Register 9 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM9_b; + }; + __IM uint32_t RESERVED142[2]; + + union + { + __IOM uint32_t FWPMTRFC10; /*!< (@ 0x00005740) PSFP Meter Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC10_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC10; /*!< (@ 0x00005744) PSFP Meter CBS Configuration Register 10 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC10_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC10; /*!< (@ 0x00005748) PSFP Meter CIR Configuration Register 10 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC10_b; + }; + __IM uint32_t RESERVED143[2]; + + union + { + __IM uint32_t FWPMTRFM10; /*!< (@ 0x00005754) PSFP Meter Filter Monitoring Register 10 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM10_b; + }; + __IM uint32_t RESERVED144[2]; + + union + { + __IOM uint32_t FWPMTRFC11; /*!< (@ 0x00005760) PSFP Meter Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC11_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC11; /*!< (@ 0x00005764) PSFP Meter CBS Configuration Register 11 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC11_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC11; /*!< (@ 0x00005768) PSFP Meter CIR Configuration Register 11 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC11_b; + }; + __IM uint32_t RESERVED145[2]; + + union + { + __IM uint32_t FWPMTRFM11; /*!< (@ 0x00005774) PSFP Meter Filter Monitoring Register 11 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM11_b; + }; + __IM uint32_t RESERVED146[2]; + + union + { + __IOM uint32_t FWPMTRFC12; /*!< (@ 0x00005780) PSFP Meter Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC12_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC12; /*!< (@ 0x00005784) PSFP Meter CBS Configuration Register 12 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC12_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC12; /*!< (@ 0x00005788) PSFP Meter CIR Configuration Register 12 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC12_b; + }; + __IM uint32_t RESERVED147[2]; + + union + { + __IM uint32_t FWPMTRFM12; /*!< (@ 0x00005794) PSFP Meter Filter Monitoring Register 12 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM12_b; + }; + __IM uint32_t RESERVED148[2]; + + union + { + __IOM uint32_t FWPMTRFC13; /*!< (@ 0x000057A0) PSFP Meter Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC13_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC13; /*!< (@ 0x000057A4) PSFP Meter CBS Configuration Register 13 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC13_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC13; /*!< (@ 0x000057A8) PSFP Meter CIR Configuration Register 13 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC13_b; + }; + __IM uint32_t RESERVED149[2]; + + union + { + __IM uint32_t FWPMTRFM13; /*!< (@ 0x000057B4) PSFP Meter Filter Monitoring Register 13 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM13_b; + }; + __IM uint32_t RESERVED150[2]; + + union + { + __IOM uint32_t FWPMTRFC14; /*!< (@ 0x000057C0) PSFP Meter Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC14_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC14; /*!< (@ 0x000057C4) PSFP Meter CBS Configuration Register 14 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC14_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC14; /*!< (@ 0x000057C8) PSFP Meter CIR Configuration Register 14 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC14_b; + }; + __IM uint32_t RESERVED151[2]; + + union + { + __IM uint32_t FWPMTRFM14; /*!< (@ 0x000057D4) PSFP Meter Filter Monitoring Register 14 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM14_b; + }; + __IM uint32_t RESERVED152[2]; + + union + { + __IOM uint32_t FWPMTRFC15; /*!< (@ 0x000057E0) PSFP Meter Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC15_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC15; /*!< (@ 0x000057E4) PSFP Meter CBS Configuration Register 15 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC15_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC15; /*!< (@ 0x000057E8) PSFP Meter CIR Configuration Register 15 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC15_b; + }; + __IM uint32_t RESERVED153[2]; + + union + { + __IM uint32_t FWPMTRFM15; /*!< (@ 0x000057F4) PSFP Meter Filter Monitoring Register 15 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM15_b; + }; + __IM uint32_t RESERVED154[2]; + + union + { + __IOM uint32_t FWPMTRFC16; /*!< (@ 0x00005800) PSFP Meter Filter Configuration Register 16 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC16_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC16; /*!< (@ 0x00005804) PSFP Meter CBS Configuration Register 16 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC16_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC16; /*!< (@ 0x00005808) PSFP Meter CIR Configuration Register 16 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC16_b; + }; + __IM uint32_t RESERVED155[2]; + + union + { + __IM uint32_t FWPMTRFM16; /*!< (@ 0x00005814) PSFP Meter Filter Monitoring Register 16 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM16_b; + }; + __IM uint32_t RESERVED156[2]; + + union + { + __IOM uint32_t FWPMTRFC17; /*!< (@ 0x00005820) PSFP Meter Filter Configuration Register 17 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC17_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC17; /*!< (@ 0x00005824) PSFP Meter CBS Configuration Register 17 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC17_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC17; /*!< (@ 0x00005828) PSFP Meter CIR Configuration Register 17 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC17_b; + }; + __IM uint32_t RESERVED157[2]; + + union + { + __IM uint32_t FWPMTRFM17; /*!< (@ 0x00005834) PSFP Meter Filter Monitoring Register 17 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM17_b; + }; + __IM uint32_t RESERVED158[2]; + + union + { + __IOM uint32_t FWPMTRFC18; /*!< (@ 0x00005840) PSFP Meter Filter Configuration Register 18 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC18_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC18; /*!< (@ 0x00005844) PSFP Meter CBS Configuration Register 18 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC18_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC18; /*!< (@ 0x00005848) PSFP Meter CIR Configuration Register 18 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC18_b; + }; + __IM uint32_t RESERVED159[2]; + + union + { + __IM uint32_t FWPMTRFM18; /*!< (@ 0x00005854) PSFP Meter Filter Monitoring Register 18 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM18_b; + }; + __IM uint32_t RESERVED160[2]; + + union + { + __IOM uint32_t FWPMTRFC19; /*!< (@ 0x00005860) PSFP Meter Filter Configuration Register 19 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC19_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC19; /*!< (@ 0x00005864) PSFP Meter CBS Configuration Register 19 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC19_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC19; /*!< (@ 0x00005868) PSFP Meter CIR Configuration Register 19 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC19_b; + }; + __IM uint32_t RESERVED161[2]; + + union + { + __IM uint32_t FWPMTRFM19; /*!< (@ 0x00005874) PSFP Meter Filter Monitoring Register 19 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM19_b; + }; + __IM uint32_t RESERVED162[2]; + + union + { + __IOM uint32_t FWPMTRFC20; /*!< (@ 0x00005880) PSFP Meter Filter Configuration Register 20 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC20_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC20; /*!< (@ 0x00005884) PSFP Meter CBS Configuration Register 20 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC20_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC20; /*!< (@ 0x00005888) PSFP Meter CIR Configuration Register 20 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC20_b; + }; + __IM uint32_t RESERVED163[2]; + + union + { + __IM uint32_t FWPMTRFM20; /*!< (@ 0x00005894) PSFP Meter Filter Monitoring Register 20 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM20_b; + }; + __IM uint32_t RESERVED164[2]; + + union + { + __IOM uint32_t FWPMTRFC21; /*!< (@ 0x000058A0) PSFP Meter Filter Configuration Register 21 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC21_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC21; /*!< (@ 0x000058A4) PSFP Meter CBS Configuration Register 21 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC21_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC21; /*!< (@ 0x000058A8) PSFP Meter CIR Configuration Register 21 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC21_b; + }; + __IM uint32_t RESERVED165[2]; + + union + { + __IM uint32_t FWPMTRFM21; /*!< (@ 0x000058B4) PSFP Meter Filter Monitoring Register 21 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM21_b; + }; + __IM uint32_t RESERVED166[2]; + + union + { + __IOM uint32_t FWPMTRFC22; /*!< (@ 0x000058C0) PSFP Meter Filter Configuration Register 22 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC22_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC22; /*!< (@ 0x000058C4) PSFP Meter CBS Configuration Register 22 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC22_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC22; /*!< (@ 0x000058C8) PSFP Meter CIR Configuration Register 22 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC22_b; + }; + __IM uint32_t RESERVED167[2]; + + union + { + __IM uint32_t FWPMTRFM22; /*!< (@ 0x000058D4) PSFP Meter Filter Monitoring Register 22 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM22_b; + }; + __IM uint32_t RESERVED168[2]; + + union + { + __IOM uint32_t FWPMTRFC23; /*!< (@ 0x000058E0) PSFP Meter Filter Configuration Register 23 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC23_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC23; /*!< (@ 0x000058E4) PSFP Meter CBS Configuration Register 23 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC23_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC23; /*!< (@ 0x000058E8) PSFP Meter CIR Configuration Register 23 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC23_b; + }; + __IM uint32_t RESERVED169[2]; + + union + { + __IM uint32_t FWPMTRFM23; /*!< (@ 0x000058F4) PSFP Meter Filter Monitoring Register 23 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM23_b; + }; + __IM uint32_t RESERVED170[2]; + + union + { + __IOM uint32_t FWPMTRFC24; /*!< (@ 0x00005900) PSFP Meter Filter Configuration Register 24 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC24_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC24; /*!< (@ 0x00005904) PSFP Meter CBS Configuration Register 24 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC24_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC24; /*!< (@ 0x00005908) PSFP Meter CIR Configuration Register 24 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC24_b; + }; + __IM uint32_t RESERVED171[2]; + + union + { + __IM uint32_t FWPMTRFM24; /*!< (@ 0x00005914) PSFP Meter Filter Monitoring Register 24 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM24_b; + }; + __IM uint32_t RESERVED172[2]; + + union + { + __IOM uint32_t FWPMTRFC25; /*!< (@ 0x00005920) PSFP Meter Filter Configuration Register 25 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC25_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC25; /*!< (@ 0x00005924) PSFP Meter CBS Configuration Register 25 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC25_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC25; /*!< (@ 0x00005928) PSFP Meter CIR Configuration Register 25 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC25_b; + }; + __IM uint32_t RESERVED173[2]; + + union + { + __IM uint32_t FWPMTRFM25; /*!< (@ 0x00005934) PSFP Meter Filter Monitoring Register 25 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM25_b; + }; + __IM uint32_t RESERVED174[2]; + + union + { + __IOM uint32_t FWPMTRFC26; /*!< (@ 0x00005940) PSFP Meter Filter Configuration Register 26 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC26_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC26; /*!< (@ 0x00005944) PSFP Meter CBS Configuration Register 26 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC26_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC26; /*!< (@ 0x00005948) PSFP Meter CIR Configuration Register 26 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC26_b; + }; + __IM uint32_t RESERVED175[2]; + + union + { + __IM uint32_t FWPMTRFM26; /*!< (@ 0x00005954) PSFP Meter Filter Monitoring Register 26 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM26_b; + }; + __IM uint32_t RESERVED176[2]; + + union + { + __IOM uint32_t FWPMTRFC27; /*!< (@ 0x00005960) PSFP Meter Filter Configuration Register 27 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC27_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC27; /*!< (@ 0x00005964) PSFP Meter CBS Configuration Register 27 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC27_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC27; /*!< (@ 0x00005968) PSFP Meter CIR Configuration Register 27 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC27_b; + }; + __IM uint32_t RESERVED177[2]; + + union + { + __IM uint32_t FWPMTRFM27; /*!< (@ 0x00005974) PSFP Meter Filter Monitoring Register 27 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM27_b; + }; + __IM uint32_t RESERVED178[2]; + + union + { + __IOM uint32_t FWPMTRFC28; /*!< (@ 0x00005980) PSFP Meter Filter Configuration Register 28 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC28_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC28; /*!< (@ 0x00005984) PSFP Meter CBS Configuration Register 28 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC28_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC28; /*!< (@ 0x00005988) PSFP Meter CIR Configuration Register 28 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC28_b; + }; + __IM uint32_t RESERVED179[2]; + + union + { + __IM uint32_t FWPMTRFM28; /*!< (@ 0x00005994) PSFP Meter Filter Monitoring Register 28 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM28_b; + }; + __IM uint32_t RESERVED180[2]; + + union + { + __IOM uint32_t FWPMTRFC29; /*!< (@ 0x000059A0) PSFP Meter Filter Configuration Register 29 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC29_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC29; /*!< (@ 0x000059A4) PSFP Meter CBS Configuration Register 29 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC29_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC29; /*!< (@ 0x000059A8) PSFP Meter CIR Configuration Register 29 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC29_b; + }; + __IM uint32_t RESERVED181[2]; + + union + { + __IM uint32_t FWPMTRFM29; /*!< (@ 0x000059B4) PSFP Meter Filter Monitoring Register 29 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM29_b; + }; + __IM uint32_t RESERVED182[2]; + + union + { + __IOM uint32_t FWPMTRFC30; /*!< (@ 0x000059C0) PSFP Meter Filter Configuration Register 30 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC30_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC30; /*!< (@ 0x000059C4) PSFP Meter CBS Configuration Register 30 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC30_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC30; /*!< (@ 0x000059C8) PSFP Meter CIR Configuration Register 30 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC30_b; + }; + __IM uint32_t RESERVED183[2]; + + union + { + __IM uint32_t FWPMTRFM30; /*!< (@ 0x000059D4) PSFP Meter Filter Monitoring Register 30 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM30_b; + }; + __IM uint32_t RESERVED184[2]; + + union + { + __IOM uint32_t FWPMTRFC31; /*!< (@ 0x000059E0) PSFP Meter Filter Configuration Register 31 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC31_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC31; /*!< (@ 0x000059E4) PSFP Meter CBS Configuration Register 31 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC31_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC31; /*!< (@ 0x000059E8) PSFP Meter CIR Configuration Register 31 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC31_b; + }; + __IM uint32_t RESERVED185[2]; + + union + { + __IM uint32_t FWPMTRFM31; /*!< (@ 0x000059F4) PSFP Meter Filter Monitoring Register 31 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM31_b; + }; + __IM uint32_t RESERVED186[386]; + + union + { + __IOM uint32_t FWFTL0; /*!< (@ 0x00006000) FRER Table Learn Register 0 */ + + struct + { + __IOM uint32_t FEAL : 7; /*!< [6..0] FRER Entry Address Learn */ + uint32_t : 9; + __IOM uint32_t FSRPL : 7; /*!< [22..16] FRER Sequence Recovery Pointer Learn */ + uint32_t : 9; + } FWFTL0_b; + }; + + union + { + __IOM uint32_t FWFTL1; /*!< (@ 0x00006004) FRER Table Learn Register 1 */ + + struct + { + __IOM uint32_t FSHLL : 4; /*!< [3..0] FRER Sequence History Length Learn */ + uint32_t : 4; + __IOM uint32_t FTNSL : 1; /*!< [8..8] FRER Take No Sequence Learn */ + __IOM uint32_t FSRPVL : 1; /*!< [9..9] FRER Sequence Recovery Pointer Valid Learn */ + uint32_t : 6; + __IOM uint32_t FSRRTL : 10; /*!< [25..16] FRER Sequence Recovery Remaining Ticks Learn */ + uint32_t : 6; + } FWFTL1_b; + }; + + union + { + __IM uint32_t FWFTLR; /*!< (@ 0x00006008) FRER Table Learn Result Register */ + + struct + { + __IM uint32_t FLF : 1; /*!< [0..0] FRER Learn Fail */ + uint32_t : 30; + __IM uint32_t FTL : 1; /*!< [31..31] FRER Table Learn */ + } FWFTLR_b; + }; + __IM uint32_t RESERVED187; + + union + { + __IOM uint32_t FWFTOC; /*!< (@ 0x00006010) FRER Timeout Configuration Register */ + + struct + { + __IOM uint32_t TOT : 16; /*!< [15..0] Timeout Time (ms) */ + __IOM uint32_t TOCE : 1; /*!< [16..16] Timeout Check Enable */ + __IOM uint32_t TOOG : 1; /*!< [17..17] Timeout Ongoing */ + uint32_t : 14; + } FWFTOC_b; + }; + + union + { + __IOM uint32_t FWFTOPC; /*!< (@ 0x00006014) FRER Timeout Prescaler Configuration Register + * 0 */ + + struct + { + __IOM uint32_t USP : 10; /*!< [9..0] Microsecond Prescaler */ + uint32_t : 22; + } FWFTOPC_b; + }; + __IM uint32_t RESERVED188[2]; + + union + { + __IOM uint32_t FWFTIM; /*!< (@ 0x00006020) FRER Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t FTIOG : 1; /*!< [0..0] FRER Table Initialization Ongoing */ + __IM uint32_t FTR : 1; /*!< [1..1] FRER Table Ready */ + uint32_t : 30; + } FWFTIM_b; + }; + __IM uint32_t RESERVED189[3]; + + union + { + __IOM uint32_t FWFTR; /*!< (@ 0x00006030) FRER Table Read Register */ + + struct + { + __IOM uint32_t FEAR : 7; /*!< [6..0] FRER Entry Address Read */ + uint32_t : 25; + } FWFTR_b; + }; + + union + { + __IM uint32_t FWFTRR0; /*!< (@ 0x00006034) FRER Table Read Result Register 0 */ + + struct + { + __IM uint32_t FSHLR : 4; /*!< [3..0] FRER Sequence History Length Read */ + uint32_t : 4; + __IM uint32_t FTNSR : 1; /*!< [8..8] FRER Take No Sequence Read */ + __IM uint32_t FSRPVR : 1; /*!< [9..9] FRER Sequence Recovery Pointer Valid Read */ + uint32_t : 6; + __IM uint32_t FSRRTR : 10; /*!< [25..16] FRER Set Recovery Remaining Ticks Read */ + uint32_t : 4; + __IM uint32_t FTREF : 1; /*!< [30..30] FRER Table Read ECC Fail */ + __IM uint32_t FTR : 1; /*!< [31..31] FRER Table Read */ + } FWFTRR0_b; + }; + + union + { + __IM uint32_t FWFTRR1; /*!< (@ 0x00006038) FRER Table Read Result Register 1 */ + + struct + { + __IM uint32_t FSHR : 15; /*!< [14..0] FRER Sequence History Read */ + uint32_t : 1; + __IM uint32_t FSRPR : 7; /*!< [22..16] FRER Sequence Recovery Pointer Read */ + uint32_t : 9; + } FWFTRR1_b; + }; + + union + { + __IM uint32_t FWFTRR2; /*!< (@ 0x0000603C) FRER Table Read Result Register 2 */ + + struct + { + __IM uint32_t FRSNR : 16; /*!< [15..0] FRER Recovery Sequence Number Read */ + __IM uint32_t FRRTR : 10; /*!< [25..16] FRER Recovery Remaining Ticks Read */ + uint32_t : 6; + } FWFTRR2_b; + }; + __IM uint32_t RESERVED190[48]; + + union + { + __IOM uint32_t FWSEQNGC0; /*!< (@ 0x00006100) Sequence Number Generation Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC0_b; + }; + + union + { + __IM uint32_t FWSEQNGM0; /*!< (@ 0x00006104) Sequence Number Generation Monitoring Register + * 0 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM0_b; + }; + + union + { + __IOM uint32_t FWSEQNGC1; /*!< (@ 0x00006108) Sequence Number Generation Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC1_b; + }; + + union + { + __IM uint32_t FWSEQNGM1; /*!< (@ 0x0000610C) Sequence Number Generation Monitoring Register + * 1 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM1_b; + }; + + union + { + __IOM uint32_t FWSEQNGC2; /*!< (@ 0x00006110) Sequence Number Generation Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC2_b; + }; + + union + { + __IM uint32_t FWSEQNGM2; /*!< (@ 0x00006114) Sequence Number Generation Monitoring Register + * 2 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM2_b; + }; + + union + { + __IOM uint32_t FWSEQNGC3; /*!< (@ 0x00006118) Sequence Number Generation Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC3_b; + }; + + union + { + __IM uint32_t FWSEQNGM3; /*!< (@ 0x0000611C) Sequence Number Generation Monitoring Register + * 3 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM3_b; + }; + + union + { + __IOM uint32_t FWSEQNGC4; /*!< (@ 0x00006120) Sequence Number Generation Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC4_b; + }; + + union + { + __IM uint32_t FWSEQNGM4; /*!< (@ 0x00006124) Sequence Number Generation Monitoring Register + * 4 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM4_b; + }; + + union + { + __IOM uint32_t FWSEQNGC5; /*!< (@ 0x00006128) Sequence Number Generation Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC5_b; + }; + + union + { + __IM uint32_t FWSEQNGM5; /*!< (@ 0x0000612C) Sequence Number Generation Monitoring Register + * 5 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM5_b; + }; + + union + { + __IOM uint32_t FWSEQNGC6; /*!< (@ 0x00006130) Sequence Number Generation Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC6_b; + }; + + union + { + __IM uint32_t FWSEQNGM6; /*!< (@ 0x00006134) Sequence Number Generation Monitoring Register + * 6 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM6_b; + }; + + union + { + __IOM uint32_t FWSEQNGC7; /*!< (@ 0x00006138) Sequence Number Generation Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC7_b; + }; + + union + { + __IM uint32_t FWSEQNGM7; /*!< (@ 0x0000613C) Sequence Number Generation Monitoring Register + * 7 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM7_b; + }; + + union + { + __IOM uint32_t FWSEQNGC8; /*!< (@ 0x00006140) Sequence Number Generation Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC8_b; + }; + + union + { + __IM uint32_t FWSEQNGM8; /*!< (@ 0x00006144) Sequence Number Generation Monitoring Register + * 8 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM8_b; + }; + + union + { + __IOM uint32_t FWSEQNGC9; /*!< (@ 0x00006148) Sequence Number Generation Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC9_b; + }; + + union + { + __IM uint32_t FWSEQNGM9; /*!< (@ 0x0000614C) Sequence Number Generation Monitoring Register + * 9 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM9_b; + }; + + union + { + __IOM uint32_t FWSEQNGC10; /*!< (@ 0x00006150) Sequence Number Generation Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC10_b; + }; + + union + { + __IM uint32_t FWSEQNGM10; /*!< (@ 0x00006154) Sequence Number Generation Monitoring Register + * 10 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM10_b; + }; + + union + { + __IOM uint32_t FWSEQNGC11; /*!< (@ 0x00006158) Sequence Number Generation Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC11_b; + }; + + union + { + __IM uint32_t FWSEQNGM11; /*!< (@ 0x0000615C) Sequence Number Generation Monitoring Register + * 11 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM11_b; + }; + + union + { + __IOM uint32_t FWSEQNGC12; /*!< (@ 0x00006160) Sequence Number Generation Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC12_b; + }; + + union + { + __IM uint32_t FWSEQNGM12; /*!< (@ 0x00006164) Sequence Number Generation Monitoring Register + * 12 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM12_b; + }; + + union + { + __IOM uint32_t FWSEQNGC13; /*!< (@ 0x00006168) Sequence Number Generation Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC13_b; + }; + + union + { + __IM uint32_t FWSEQNGM13; /*!< (@ 0x0000616C) Sequence Number Generation Monitoring Register + * 13 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM13_b; + }; + + union + { + __IOM uint32_t FWSEQNGC14; /*!< (@ 0x00006170) Sequence Number Generation Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC14_b; + }; + + union + { + __IM uint32_t FWSEQNGM14; /*!< (@ 0x00006174) Sequence Number Generation Monitoring Register + * 14 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM14_b; + }; + + union + { + __IOM uint32_t FWSEQNGC15; /*!< (@ 0x00006178) Sequence Number Generation Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC15_b; + }; + + union + { + __IM uint32_t FWSEQNGM15; /*!< (@ 0x0000617C) Sequence Number Generation Monitoring Register + * 15 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM15_b; + }; + + union + { + __IOM uint32_t FWSEQNGC16; /*!< (@ 0x00006180) Sequence Number Generation Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC16_b; + }; + + union + { + __IM uint32_t FWSEQNGM16; /*!< (@ 0x00006184) Sequence Number Generation Monitoring Register + * 16 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM16_b; + }; + + union + { + __IOM uint32_t FWSEQNGC17; /*!< (@ 0x00006188) Sequence Number Generation Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC17_b; + }; + + union + { + __IM uint32_t FWSEQNGM17; /*!< (@ 0x0000618C) Sequence Number Generation Monitoring Register + * 17 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM17_b; + }; + + union + { + __IOM uint32_t FWSEQNGC18; /*!< (@ 0x00006190) Sequence Number Generation Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC18_b; + }; + + union + { + __IM uint32_t FWSEQNGM18; /*!< (@ 0x00006194) Sequence Number Generation Monitoring Register + * 18 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM18_b; + }; + + union + { + __IOM uint32_t FWSEQNGC19; /*!< (@ 0x00006198) Sequence Number Generation Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC19_b; + }; + + union + { + __IM uint32_t FWSEQNGM19; /*!< (@ 0x0000619C) Sequence Number Generation Monitoring Register + * 19 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM19_b; + }; + + union + { + __IOM uint32_t FWSEQNGC20; /*!< (@ 0x000061A0) Sequence Number Generation Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC20_b; + }; + + union + { + __IM uint32_t FWSEQNGM20; /*!< (@ 0x000061A4) Sequence Number Generation Monitoring Register + * 20 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM20_b; + }; + + union + { + __IOM uint32_t FWSEQNGC21; /*!< (@ 0x000061A8) Sequence Number Generation Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC21_b; + }; + + union + { + __IM uint32_t FWSEQNGM21; /*!< (@ 0x000061AC) Sequence Number Generation Monitoring Register + * 21 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM21_b; + }; + + union + { + __IOM uint32_t FWSEQNGC22; /*!< (@ 0x000061B0) Sequence Number Generation Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC22_b; + }; + + union + { + __IM uint32_t FWSEQNGM22; /*!< (@ 0x000061B4) Sequence Number Generation Monitoring Register + * 22 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM22_b; + }; + + union + { + __IOM uint32_t FWSEQNGC23; /*!< (@ 0x000061B8) Sequence Number Generation Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC23_b; + }; + + union + { + __IM uint32_t FWSEQNGM23; /*!< (@ 0x000061BC) Sequence Number Generation Monitoring Register + * 23 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM23_b; + }; + + union + { + __IOM uint32_t FWSEQNGC24; /*!< (@ 0x000061C0) Sequence Number Generation Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC24_b; + }; + + union + { + __IM uint32_t FWSEQNGM24; /*!< (@ 0x000061C4) Sequence Number Generation Monitoring Register + * 24 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM24_b; + }; + + union + { + __IOM uint32_t FWSEQNGC25; /*!< (@ 0x000061C8) Sequence Number Generation Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC25_b; + }; + + union + { + __IM uint32_t FWSEQNGM25; /*!< (@ 0x000061CC) Sequence Number Generation Monitoring Register + * 25 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM25_b; + }; + + union + { + __IOM uint32_t FWSEQNGC26; /*!< (@ 0x000061D0) Sequence Number Generation Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC26_b; + }; + + union + { + __IM uint32_t FWSEQNGM26; /*!< (@ 0x000061D4) Sequence Number Generation Monitoring Register + * 26 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM26_b; + }; + + union + { + __IOM uint32_t FWSEQNGC27; /*!< (@ 0x000061D8) Sequence Number Generation Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC27_b; + }; + + union + { + __IM uint32_t FWSEQNGM27; /*!< (@ 0x000061DC) Sequence Number Generation Monitoring Register + * 27 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM27_b; + }; + + union + { + __IOM uint32_t FWSEQNGC28; /*!< (@ 0x000061E0) Sequence Number Generation Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC28_b; + }; + + union + { + __IM uint32_t FWSEQNGM28; /*!< (@ 0x000061E4) Sequence Number Generation Monitoring Register + * 28 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM28_b; + }; + + union + { + __IOM uint32_t FWSEQNGC29; /*!< (@ 0x000061E8) Sequence Number Generation Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC29_b; + }; + + union + { + __IM uint32_t FWSEQNGM29; /*!< (@ 0x000061EC) Sequence Number Generation Monitoring Register + * 29 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM29_b; + }; + + union + { + __IOM uint32_t FWSEQNGC30; /*!< (@ 0x000061F0) Sequence Number Generation Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC30_b; + }; + + union + { + __IM uint32_t FWSEQNGM30; /*!< (@ 0x000061F4) Sequence Number Generation Monitoring Register + * 30 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM30_b; + }; + + union + { + __IOM uint32_t FWSEQNGC31; /*!< (@ 0x000061F8) Sequence Number Generation Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC31_b; + }; + + union + { + __IM uint32_t FWSEQNGM31; /*!< (@ 0x000061FC) Sequence Number Generation Monitoring Register + * 31 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM31_b; + }; + + union + { + __OM uint32_t FWSEQNRC; /*!< (@ 0x00006200) Sequence Number Reset Configuration Register */ + + struct + { + __OM uint32_t SEQNR : 32; /*!< [31..0] Sequence Number Generation Reset */ + } FWSEQNRC_b; + }; + __IM uint32_t RESERVED191[63]; + + union + { + __IM uint32_t FWCTFDCN0; /*!< (@ 0x00006300) Cut-Through Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t CTFDN : 32; /*!< [31..0] Cut-Through Forwarded Descriptor Number */ + } FWCTFDCN0_b; + }; + + union + { + __IM uint32_t FWLTHFDCN0; /*!< (@ 0x00006304) Layer 3 Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN0_b; + }; + __IM uint32_t RESERVED192; + + union + { + __IM uint32_t FWLTWFDCN0; /*!< (@ 0x0000630C) Layer 2 Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN0_b; + }; + + union + { + __IM uint32_t FWPBFDCN0; /*!< (@ 0x00006310) Port Based Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN0_b; + }; + + union + { + __IM uint32_t FWMHLCN0; /*!< (@ 0x00006314) MAC Hardware Learn Counter Register 0 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN0_b; + }; + __IM uint32_t RESERVED193[2]; + + union + { + __IM uint32_t FWCTFDCN1; /*!< (@ 0x00006320) Cut-Through Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t CTFDN : 32; /*!< [31..0] Cut-Through Forwarded Descriptor Number */ + } FWCTFDCN1_b; + }; + + union + { + __IM uint32_t FWLTHFDCN1; /*!< (@ 0x00006324) Layer 3 Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN1_b; + }; + __IM uint32_t RESERVED194; + + union + { + __IM uint32_t FWLTWFDCN1; /*!< (@ 0x0000632C) Layer 2 Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN1_b; + }; + + union + { + __IM uint32_t FWPBFDCN1; /*!< (@ 0x00006330) Port Based Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN1_b; + }; + + union + { + __IM uint32_t FWMHLCN1; /*!< (@ 0x00006334) MAC Hardware Learn Counter Register 1 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN1_b; + }; + __IM uint32_t RESERVED195[2]; + + union + { + __IM uint32_t FWDDFDCN0; /*!< (@ 0x00006340) Direct Descriptor Forwarded Descriptor Counter + * Register 0 */ + + struct + { + __IM uint32_t DDFDN : 32; /*!< [31..0] Direct Descriptor Forwarded Descriptor Number */ + } FWDDFDCN0_b; + }; + + union + { + __IM uint32_t FWLTHFDCN2; /*!< (@ 0x00006344) Layer 3 Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN2_b; + }; + __IM uint32_t RESERVED196; + + union + { + __IM uint32_t FWLTWFDCN2; /*!< (@ 0x0000634C) Layer 2 Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN2_b; + }; + + union + { + __IM uint32_t FWPBFDCN2; /*!< (@ 0x00006350) Port Based Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN2_b; + }; + + union + { + __IM uint32_t FWMHLCN2; /*!< (@ 0x00006354) MAC Hardware Learn Counter Register 2 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN2_b; + }; + __IM uint32_t RESERVED197[107]; + + union + { + __IM uint32_t FWWMRDCN0; /*!< (@ 0x00006504) Watermark Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN0_b; + }; + + union + { + __IM uint32_t FWCTRDCN0; /*!< (@ 0x00006508) Cut-Through Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t CTRDN : 16; /*!< [15..0] Cut-through rejected Descriptor Number */ + uint32_t : 16; + } FWCTRDCN0_b; + }; + + union + { + __IM uint32_t FWLTHRDCN0; /*!< (@ 0x0000650C) Layer 3 Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN0_b; + }; + __IM uint32_t RESERVED198; + + union + { + __IM uint32_t FWLTWRDCN0; /*!< (@ 0x00006514) Layer 2 Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN0_b; + }; + + union + { + __IM uint32_t FWPBRDCN0; /*!< (@ 0x00006518) Port Based Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN0_b; + }; + __IM uint32_t RESERVED199[2]; + + union + { + __IM uint32_t FWWMRDCN1; /*!< (@ 0x00006524) Watermark Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN1_b; + }; + + union + { + __IM uint32_t FWCTRDCN1; /*!< (@ 0x00006528) Cut-Through Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t CTRDN : 16; /*!< [15..0] Cut-through rejected Descriptor Number */ + uint32_t : 16; + } FWCTRDCN1_b; + }; + + union + { + __IM uint32_t FWLTHRDCN1; /*!< (@ 0x0000652C) Layer 3 Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN1_b; + }; + __IM uint32_t RESERVED200; + + union + { + __IM uint32_t FWLTWRDCN1; /*!< (@ 0x00006534) Layer 2 Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN1_b; + }; + + union + { + __IM uint32_t FWPBRDCN1; /*!< (@ 0x00006538) Port Based Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN1_b; + }; + __IM uint32_t RESERVED201[2]; + + union + { + __IM uint32_t FWWMRDCN2; /*!< (@ 0x00006544) Watermark Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN2_b; + }; + + union + { + __IM uint32_t FWDDRDCN0; /*!< (@ 0x00006548) Direct Descriptor Rejected Descriptor Counter + * Register 0 */ + + struct + { + __IM uint32_t DDRDN : 16; /*!< [15..0] Direct Descriptor rejected Descriptor Number */ + uint32_t : 16; + } FWDDRDCN0_b; + }; + + union + { + __IM uint32_t FWLTHRDCN2; /*!< (@ 0x0000654C) Layer 3 Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN2_b; + }; + __IM uint32_t RESERVED202; + + union + { + __IM uint32_t FWLTWRDCN2; /*!< (@ 0x00006554) Layer 2 Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN2_b; + }; + + union + { + __IM uint32_t FWPBRDCN2; /*!< (@ 0x00006558) Port Based Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN2_b; + }; + __IM uint32_t RESERVED203[105]; + + union + { + __IM uint32_t FWPMFDCN0; /*!< (@ 0x00006700) PSFP MSDU Filtered Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN0_b; + }; + + union + { + __IM uint32_t FWPMFDCN1; /*!< (@ 0x00006704) PSFP MSDU Filtered Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN1_b; + }; + + union + { + __IM uint32_t FWPMFDCN2; /*!< (@ 0x00006708) PSFP MSDU Filtered Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN2_b; + }; + + union + { + __IM uint32_t FWPMFDCN3; /*!< (@ 0x0000670C) PSFP MSDU Filtered Descriptor Counter Register + * 3 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN3_b; + }; + + union + { + __IM uint32_t FWPMFDCN4; /*!< (@ 0x00006710) PSFP MSDU Filtered Descriptor Counter Register + * 4 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN4_b; + }; + + union + { + __IM uint32_t FWPMFDCN5; /*!< (@ 0x00006714) PSFP MSDU Filtered Descriptor Counter Register + * 5 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN5_b; + }; + + union + { + __IM uint32_t FWPMFDCN6; /*!< (@ 0x00006718) PSFP MSDU Filtered Descriptor Counter Register + * 6 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN6_b; + }; + + union + { + __IM uint32_t FWPMFDCN7; /*!< (@ 0x0000671C) PSFP MSDU Filtered Descriptor Counter Register + * 7 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN7_b; + }; + + union + { + __IM uint32_t FWPMFDCN8; /*!< (@ 0x00006720) PSFP MSDU Filtered Descriptor Counter Register + * 8 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN8_b; + }; + + union + { + __IM uint32_t FWPMFDCN9; /*!< (@ 0x00006724) PSFP MSDU Filtered Descriptor Counter Register + * 9 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN9_b; + }; + + union + { + __IM uint32_t FWPMFDCN10; /*!< (@ 0x00006728) PSFP MSDU Filtered Descriptor Counter Register + * 10 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN10_b; + }; + + union + { + __IM uint32_t FWPMFDCN11; /*!< (@ 0x0000672C) PSFP MSDU Filtered Descriptor Counter Register + * 11 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN11_b; + }; + + union + { + __IM uint32_t FWPMFDCN12; /*!< (@ 0x00006730) PSFP MSDU Filtered Descriptor Counter Register + * 12 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN12_b; + }; + + union + { + __IM uint32_t FWPMFDCN13; /*!< (@ 0x00006734) PSFP MSDU Filtered Descriptor Counter Register + * 13 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN13_b; + }; + + union + { + __IM uint32_t FWPMFDCN14; /*!< (@ 0x00006738) PSFP MSDU Filtered Descriptor Counter Register + * 14 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN14_b; + }; + + union + { + __IM uint32_t FWPMFDCN15; /*!< (@ 0x0000673C) PSFP MSDU Filtered Descriptor Counter Register + * 15 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN15_b; + }; + __IM uint32_t RESERVED204[48]; + + union + { + __IM uint32_t FWPMGDCN0; /*!< (@ 0x00006800) PSFP Meter Green Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN0_b; + }; + + union + { + __IM uint32_t FWPMYDCN0; /*!< (@ 0x00006804) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN0_b; + }; + + union + { + __IM uint32_t FWPMRDCN0; /*!< (@ 0x00006808) PSFP Meter Red Descriptor Counter Register 0 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN0_b; + }; + __IM uint32_t RESERVED205; + + union + { + __IM uint32_t FWPMGDCN1; /*!< (@ 0x00006810) PSFP Meter Green Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN1_b; + }; + + union + { + __IM uint32_t FWPMYDCN1; /*!< (@ 0x00006814) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN1_b; + }; + + union + { + __IM uint32_t FWPMRDCN1; /*!< (@ 0x00006818) PSFP Meter Red Descriptor Counter Register 1 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN1_b; + }; + __IM uint32_t RESERVED206; + + union + { + __IM uint32_t FWPMGDCN2; /*!< (@ 0x00006820) PSFP Meter Green Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN2_b; + }; + + union + { + __IM uint32_t FWPMYDCN2; /*!< (@ 0x00006824) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN2_b; + }; + + union + { + __IM uint32_t FWPMRDCN2; /*!< (@ 0x00006828) PSFP Meter Red Descriptor Counter Register 2 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN2_b; + }; + __IM uint32_t RESERVED207; + + union + { + __IM uint32_t FWPMGDCN3; /*!< (@ 0x00006830) PSFP Meter Green Descriptor Counter Register + * 3 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN3_b; + }; + + union + { + __IM uint32_t FWPMYDCN3; /*!< (@ 0x00006834) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN3_b; + }; + + union + { + __IM uint32_t FWPMRDCN3; /*!< (@ 0x00006838) PSFP Meter Red Descriptor Counter Register 3 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN3_b; + }; + __IM uint32_t RESERVED208; + + union + { + __IM uint32_t FWPMGDCN4; /*!< (@ 0x00006840) PSFP Meter Green Descriptor Counter Register + * 4 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN4_b; + }; + + union + { + __IM uint32_t FWPMYDCN4; /*!< (@ 0x00006844) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN4_b; + }; + + union + { + __IM uint32_t FWPMRDCN4; /*!< (@ 0x00006848) PSFP Meter Red Descriptor Counter Register 4 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN4_b; + }; + __IM uint32_t RESERVED209; + + union + { + __IM uint32_t FWPMGDCN5; /*!< (@ 0x00006850) PSFP Meter Green Descriptor Counter Register + * 5 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN5_b; + }; + + union + { + __IM uint32_t FWPMYDCN5; /*!< (@ 0x00006854) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN5_b; + }; + + union + { + __IM uint32_t FWPMRDCN5; /*!< (@ 0x00006858) PSFP Meter Red Descriptor Counter Register 5 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN5_b; + }; + __IM uint32_t RESERVED210; + + union + { + __IM uint32_t FWPMGDCN6; /*!< (@ 0x00006860) PSFP Meter Green Descriptor Counter Register + * 6 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN6_b; + }; + + union + { + __IM uint32_t FWPMYDCN6; /*!< (@ 0x00006864) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN6_b; + }; + + union + { + __IM uint32_t FWPMRDCN6; /*!< (@ 0x00006868) PSFP Meter Red Descriptor Counter Register 6 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN6_b; + }; + __IM uint32_t RESERVED211; + + union + { + __IM uint32_t FWPMGDCN7; /*!< (@ 0x00006870) PSFP Meter Green Descriptor Counter Register + * 7 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN7_b; + }; + + union + { + __IM uint32_t FWPMYDCN7; /*!< (@ 0x00006874) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN7_b; + }; + + union + { + __IM uint32_t FWPMRDCN7; /*!< (@ 0x00006878) PSFP Meter Red Descriptor Counter Register 7 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN7_b; + }; + __IM uint32_t RESERVED212; + + union + { + __IM uint32_t FWPMGDCN8; /*!< (@ 0x00006880) PSFP Meter Green Descriptor Counter Register + * 8 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN8_b; + }; + __IM uint32_t RESERVED213; + + union + { + __IM uint32_t FWPMRDCN8; /*!< (@ 0x00006888) PSFP Meter Red Descriptor Counter Register 8 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN8_b; + }; + __IM uint32_t RESERVED214; + + union + { + __IM uint32_t FWPMGDCN9; /*!< (@ 0x00006890) PSFP Meter Green Descriptor Counter Register + * 9 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN9_b; + }; + __IM uint32_t RESERVED215; + + union + { + __IM uint32_t FWPMRDCN9; /*!< (@ 0x00006898) PSFP Meter Red Descriptor Counter Register 9 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN9_b; + }; + __IM uint32_t RESERVED216; + + union + { + __IM uint32_t FWPMGDCN10; /*!< (@ 0x000068A0) PSFP Meter Green Descriptor Counter Register + * 10 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN10_b; + }; + __IM uint32_t RESERVED217; + + union + { + __IM uint32_t FWPMRDCN10; /*!< (@ 0x000068A8) PSFP Meter Red Descriptor Counter Register 10 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN10_b; + }; + __IM uint32_t RESERVED218; + + union + { + __IM uint32_t FWPMGDCN11; /*!< (@ 0x000068B0) PSFP Meter Green Descriptor Counter Register + * 11 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN11_b; + }; + __IM uint32_t RESERVED219; + + union + { + __IM uint32_t FWPMRDCN11; /*!< (@ 0x000068B8) PSFP Meter Red Descriptor Counter Register 11 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN11_b; + }; + __IM uint32_t RESERVED220; + + union + { + __IM uint32_t FWPMGDCN12; /*!< (@ 0x000068C0) PSFP Meter Green Descriptor Counter Register + * 12 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN12_b; + }; + __IM uint32_t RESERVED221; + + union + { + __IM uint32_t FWPMRDCN12; /*!< (@ 0x000068C8) PSFP Meter Red Descriptor Counter Register 12 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN12_b; + }; + __IM uint32_t RESERVED222; + + union + { + __IM uint32_t FWPMGDCN13; /*!< (@ 0x000068D0) PSFP Meter Green Descriptor Counter Register + * 13 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN13_b; + }; + __IM uint32_t RESERVED223; + + union + { + __IM uint32_t FWPMRDCN13; /*!< (@ 0x000068D8) PSFP Meter Red Descriptor Counter Register 13 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN13_b; + }; + __IM uint32_t RESERVED224; + + union + { + __IM uint32_t FWPMGDCN14; /*!< (@ 0x000068E0) PSFP Meter Green Descriptor Counter Register + * 14 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN14_b; + }; + __IM uint32_t RESERVED225; + + union + { + __IM uint32_t FWPMRDCN14; /*!< (@ 0x000068E8) PSFP Meter Red Descriptor Counter Register 14 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN14_b; + }; + __IM uint32_t RESERVED226; + + union + { + __IM uint32_t FWPMGDCN15; /*!< (@ 0x000068F0) PSFP Meter Green Descriptor Counter Register + * 15 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN15_b; + }; + __IM uint32_t RESERVED227; + + union + { + __IM uint32_t FWPMRDCN15; /*!< (@ 0x000068F8) PSFP Meter Red Descriptor Counter Register 15 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN15_b; + }; + __IM uint32_t RESERVED228; + + union + { + __IM uint32_t FWPMGDCN16; /*!< (@ 0x00006900) PSFP Meter Green Descriptor Counter Register + * 16 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN16_b; + }; + __IM uint32_t RESERVED229; + + union + { + __IM uint32_t FWPMRDCN16; /*!< (@ 0x00006908) PSFP Meter Red Descriptor Counter Register 16 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN16_b; + }; + __IM uint32_t RESERVED230; + + union + { + __IM uint32_t FWPMGDCN17; /*!< (@ 0x00006910) PSFP Meter Green Descriptor Counter Register + * 17 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN17_b; + }; + __IM uint32_t RESERVED231; + + union + { + __IM uint32_t FWPMRDCN17; /*!< (@ 0x00006918) PSFP Meter Red Descriptor Counter Register 17 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN17_b; + }; + __IM uint32_t RESERVED232; + + union + { + __IM uint32_t FWPMGDCN18; /*!< (@ 0x00006920) PSFP Meter Green Descriptor Counter Register + * 18 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN18_b; + }; + __IM uint32_t RESERVED233; + + union + { + __IM uint32_t FWPMRDCN18; /*!< (@ 0x00006928) PSFP Meter Red Descriptor Counter Register 18 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN18_b; + }; + __IM uint32_t RESERVED234; + + union + { + __IM uint32_t FWPMGDCN19; /*!< (@ 0x00006930) PSFP Meter Green Descriptor Counter Register + * 19 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN19_b; + }; + __IM uint32_t RESERVED235; + + union + { + __IM uint32_t FWPMRDCN19; /*!< (@ 0x00006938) PSFP Meter Red Descriptor Counter Register 19 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN19_b; + }; + __IM uint32_t RESERVED236; + + union + { + __IM uint32_t FWPMGDCN20; /*!< (@ 0x00006940) PSFP Meter Green Descriptor Counter Register + * 20 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN20_b; + }; + __IM uint32_t RESERVED237; + + union + { + __IM uint32_t FWPMRDCN20; /*!< (@ 0x00006948) PSFP Meter Red Descriptor Counter Register 20 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN20_b; + }; + __IM uint32_t RESERVED238; + + union + { + __IM uint32_t FWPMGDCN21; /*!< (@ 0x00006950) PSFP Meter Green Descriptor Counter Register + * 21 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN21_b; + }; + __IM uint32_t RESERVED239; + + union + { + __IM uint32_t FWPMRDCN21; /*!< (@ 0x00006958) PSFP Meter Red Descriptor Counter Register 21 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN21_b; + }; + __IM uint32_t RESERVED240; + + union + { + __IM uint32_t FWPMGDCN22; /*!< (@ 0x00006960) PSFP Meter Green Descriptor Counter Register + * 22 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN22_b; + }; + __IM uint32_t RESERVED241; + + union + { + __IM uint32_t FWPMRDCN22; /*!< (@ 0x00006968) PSFP Meter Red Descriptor Counter Register 22 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN22_b; + }; + __IM uint32_t RESERVED242; + + union + { + __IM uint32_t FWPMGDCN23; /*!< (@ 0x00006970) PSFP Meter Green Descriptor Counter Register + * 23 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN23_b; + }; + __IM uint32_t RESERVED243; + + union + { + __IM uint32_t FWPMRDCN23; /*!< (@ 0x00006978) PSFP Meter Red Descriptor Counter Register 23 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN23_b; + }; + __IM uint32_t RESERVED244; + + union + { + __IM uint32_t FWPMGDCN24; /*!< (@ 0x00006980) PSFP Meter Green Descriptor Counter Register + * 24 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN24_b; + }; + __IM uint32_t RESERVED245; + + union + { + __IM uint32_t FWPMRDCN24; /*!< (@ 0x00006988) PSFP Meter Red Descriptor Counter Register 24 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN24_b; + }; + __IM uint32_t RESERVED246; + + union + { + __IM uint32_t FWPMGDCN25; /*!< (@ 0x00006990) PSFP Meter Green Descriptor Counter Register + * 25 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN25_b; + }; + __IM uint32_t RESERVED247; + + union + { + __IM uint32_t FWPMRDCN25; /*!< (@ 0x00006998) PSFP Meter Red Descriptor Counter Register 25 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN25_b; + }; + __IM uint32_t RESERVED248; + + union + { + __IM uint32_t FWPMGDCN26; /*!< (@ 0x000069A0) PSFP Meter Green Descriptor Counter Register + * 26 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN26_b; + }; + __IM uint32_t RESERVED249; + + union + { + __IM uint32_t FWPMRDCN26; /*!< (@ 0x000069A8) PSFP Meter Red Descriptor Counter Register 26 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN26_b; + }; + __IM uint32_t RESERVED250; + + union + { + __IM uint32_t FWPMGDCN27; /*!< (@ 0x000069B0) PSFP Meter Green Descriptor Counter Register + * 27 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN27_b; + }; + __IM uint32_t RESERVED251; + + union + { + __IM uint32_t FWPMRDCN27; /*!< (@ 0x000069B8) PSFP Meter Red Descriptor Counter Register 27 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN27_b; + }; + __IM uint32_t RESERVED252; + + union + { + __IM uint32_t FWPMGDCN28; /*!< (@ 0x000069C0) PSFP Meter Green Descriptor Counter Register + * 28 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN28_b; + }; + __IM uint32_t RESERVED253; + + union + { + __IM uint32_t FWPMRDCN28; /*!< (@ 0x000069C8) PSFP Meter Red Descriptor Counter Register 28 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN28_b; + }; + __IM uint32_t RESERVED254; + + union + { + __IM uint32_t FWPMGDCN29; /*!< (@ 0x000069D0) PSFP Meter Green Descriptor Counter Register + * 29 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN29_b; + }; + __IM uint32_t RESERVED255; + + union + { + __IM uint32_t FWPMRDCN29; /*!< (@ 0x000069D8) PSFP Meter Red Descriptor Counter Register 29 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN29_b; + }; + __IM uint32_t RESERVED256; + + union + { + __IM uint32_t FWPMGDCN30; /*!< (@ 0x000069E0) PSFP Meter Green Descriptor Counter Register + * 30 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN30_b; + }; + __IM uint32_t RESERVED257; + + union + { + __IM uint32_t FWPMRDCN30; /*!< (@ 0x000069E8) PSFP Meter Red Descriptor Counter Register 30 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN30_b; + }; + __IM uint32_t RESERVED258; + + union + { + __IM uint32_t FWPMGDCN31; /*!< (@ 0x000069F0) PSFP Meter Green Descriptor Counter Register + * 31 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN31_b; + }; + __IM uint32_t RESERVED259; + + union + { + __IM uint32_t FWPMRDCN31; /*!< (@ 0x000069F8) PSFP Meter Red Descriptor Counter Register 31 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN31_b; + }; + __IM uint32_t RESERVED260; + + union + { + __IM uint32_t FWFRPPCN0; /*!< (@ 0x00006A00) FRER Passed Packet Counter Register 0 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN0_b; + }; + + union + { + __IM uint32_t FWFRDPCN0; /*!< (@ 0x00006A04) FRER Discarded Packet Counter Register 0 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN0_b; + }; + + union + { + __IM uint32_t FWFRPPCN1; /*!< (@ 0x00006A08) FRER Passed Packet Counter Register 1 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN1_b; + }; + + union + { + __IM uint32_t FWFRDPCN1; /*!< (@ 0x00006A0C) FRER Discarded Packet Counter Register 1 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN1_b; + }; + + union + { + __IM uint32_t FWFRPPCN2; /*!< (@ 0x00006A10) FRER Passed Packet Counter Register 2 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN2_b; + }; + + union + { + __IM uint32_t FWFRDPCN2; /*!< (@ 0x00006A14) FRER Discarded Packet Counter Register 2 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN2_b; + }; + + union + { + __IM uint32_t FWFRPPCN3; /*!< (@ 0x00006A18) FRER Passed Packet Counter Register 3 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN3_b; + }; + + union + { + __IM uint32_t FWFRDPCN3; /*!< (@ 0x00006A1C) FRER Discarded Packet Counter Register 3 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN3_b; + }; + + union + { + __IM uint32_t FWFRPPCN4; /*!< (@ 0x00006A20) FRER Passed Packet Counter Register 4 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN4_b; + }; + + union + { + __IM uint32_t FWFRDPCN4; /*!< (@ 0x00006A24) FRER Discarded Packet Counter Register 4 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN4_b; + }; + + union + { + __IM uint32_t FWFRPPCN5; /*!< (@ 0x00006A28) FRER Passed Packet Counter Register 5 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN5_b; + }; + + union + { + __IM uint32_t FWFRDPCN5; /*!< (@ 0x00006A2C) FRER Discarded Packet Counter Register 5 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN5_b; + }; + + union + { + __IM uint32_t FWFRPPCN6; /*!< (@ 0x00006A30) FRER Passed Packet Counter Register 6 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN6_b; + }; + + union + { + __IM uint32_t FWFRDPCN6; /*!< (@ 0x00006A34) FRER Discarded Packet Counter Register 6 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN6_b; + }; + + union + { + __IM uint32_t FWFRPPCN7; /*!< (@ 0x00006A38) FRER Passed Packet Counter Register 7 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN7_b; + }; + + union + { + __IM uint32_t FWFRDPCN7; /*!< (@ 0x00006A3C) FRER Discarded Packet Counter Register 7 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN7_b; + }; + + union + { + __IM uint32_t FWFRPPCN8; /*!< (@ 0x00006A40) FRER Passed Packet Counter Register 8 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN8_b; + }; + + union + { + __IM uint32_t FWFRDPCN8; /*!< (@ 0x00006A44) FRER Discarded Packet Counter Register 8 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN8_b; + }; + + union + { + __IM uint32_t FWFRPPCN9; /*!< (@ 0x00006A48) FRER Passed Packet Counter Register 9 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN9_b; + }; + + union + { + __IM uint32_t FWFRDPCN9; /*!< (@ 0x00006A4C) FRER Discarded Packet Counter Register 9 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN9_b; + }; + + union + { + __IM uint32_t FWFRPPCN10; /*!< (@ 0x00006A50) FRER Passed Packet Counter Register 10 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN10_b; + }; + + union + { + __IM uint32_t FWFRDPCN10; /*!< (@ 0x00006A54) FRER Discarded Packet Counter Register 10 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN10_b; + }; + + union + { + __IM uint32_t FWFRPPCN11; /*!< (@ 0x00006A58) FRER Passed Packet Counter Register 11 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN11_b; + }; + + union + { + __IM uint32_t FWFRDPCN11; /*!< (@ 0x00006A5C) FRER Discarded Packet Counter Register 11 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN11_b; + }; + + union + { + __IM uint32_t FWFRPPCN12; /*!< (@ 0x00006A60) FRER Passed Packet Counter Register 12 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN12_b; + }; + + union + { + __IM uint32_t FWFRDPCN12; /*!< (@ 0x00006A64) FRER Discarded Packet Counter Register 12 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN12_b; + }; + + union + { + __IM uint32_t FWFRPPCN13; /*!< (@ 0x00006A68) FRER Passed Packet Counter Register 13 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN13_b; + }; + + union + { + __IM uint32_t FWFRDPCN13; /*!< (@ 0x00006A6C) FRER Discarded Packet Counter Register 13 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN13_b; + }; + + union + { + __IM uint32_t FWFRPPCN14; /*!< (@ 0x00006A70) FRER Passed Packet Counter Register 14 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN14_b; + }; + + union + { + __IM uint32_t FWFRDPCN14; /*!< (@ 0x00006A74) FRER Discarded Packet Counter Register 14 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN14_b; + }; + + union + { + __IM uint32_t FWFRPPCN15; /*!< (@ 0x00006A78) FRER Passed Packet Counter Register 15 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN15_b; + }; + + union + { + __IM uint32_t FWFRDPCN15; /*!< (@ 0x00006A7C) FRER Discarded Packet Counter Register 15 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN15_b; + }; + + union + { + __IM uint32_t FWFRPPCN16; /*!< (@ 0x00006A80) FRER Passed Packet Counter Register 16 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN16_b; + }; + + union + { + __IM uint32_t FWFRDPCN16; /*!< (@ 0x00006A84) FRER Discarded Packet Counter Register 16 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN16_b; + }; + + union + { + __IM uint32_t FWFRPPCN17; /*!< (@ 0x00006A88) FRER Passed Packet Counter Register 17 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN17_b; + }; + + union + { + __IM uint32_t FWFRDPCN17; /*!< (@ 0x00006A8C) FRER Discarded Packet Counter Register 17 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN17_b; + }; + + union + { + __IM uint32_t FWFRPPCN18; /*!< (@ 0x00006A90) FRER Passed Packet Counter Register 18 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN18_b; + }; + + union + { + __IM uint32_t FWFRDPCN18; /*!< (@ 0x00006A94) FRER Discarded Packet Counter Register 18 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN18_b; + }; + + union + { + __IM uint32_t FWFRPPCN19; /*!< (@ 0x00006A98) FRER Passed Packet Counter Register 19 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN19_b; + }; + + union + { + __IM uint32_t FWFRDPCN19; /*!< (@ 0x00006A9C) FRER Discarded Packet Counter Register 19 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN19_b; + }; + + union + { + __IM uint32_t FWFRPPCN20; /*!< (@ 0x00006AA0) FRER Passed Packet Counter Register 20 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN20_b; + }; + + union + { + __IM uint32_t FWFRDPCN20; /*!< (@ 0x00006AA4) FRER Discarded Packet Counter Register 20 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN20_b; + }; + + union + { + __IM uint32_t FWFRPPCN21; /*!< (@ 0x00006AA8) FRER Passed Packet Counter Register 21 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN21_b; + }; + + union + { + __IM uint32_t FWFRDPCN21; /*!< (@ 0x00006AAC) FRER Discarded Packet Counter Register 21 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN21_b; + }; + + union + { + __IM uint32_t FWFRPPCN22; /*!< (@ 0x00006AB0) FRER Passed Packet Counter Register 22 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN22_b; + }; + + union + { + __IM uint32_t FWFRDPCN22; /*!< (@ 0x00006AB4) FRER Discarded Packet Counter Register 22 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN22_b; + }; + + union + { + __IM uint32_t FWFRPPCN23; /*!< (@ 0x00006AB8) FRER Passed Packet Counter Register 23 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN23_b; + }; + + union + { + __IM uint32_t FWFRDPCN23; /*!< (@ 0x00006ABC) FRER Discarded Packet Counter Register 23 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN23_b; + }; + + union + { + __IM uint32_t FWFRPPCN24; /*!< (@ 0x00006AC0) FRER Passed Packet Counter Register 24 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN24_b; + }; + + union + { + __IM uint32_t FWFRDPCN24; /*!< (@ 0x00006AC4) FRER Discarded Packet Counter Register 24 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN24_b; + }; + + union + { + __IM uint32_t FWFRPPCN25; /*!< (@ 0x00006AC8) FRER Passed Packet Counter Register 25 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN25_b; + }; + + union + { + __IM uint32_t FWFRDPCN25; /*!< (@ 0x00006ACC) FRER Discarded Packet Counter Register 25 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN25_b; + }; + + union + { + __IM uint32_t FWFRPPCN26; /*!< (@ 0x00006AD0) FRER Passed Packet Counter Register 26 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN26_b; + }; + + union + { + __IM uint32_t FWFRDPCN26; /*!< (@ 0x00006AD4) FRER Discarded Packet Counter Register 26 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN26_b; + }; + + union + { + __IM uint32_t FWFRPPCN27; /*!< (@ 0x00006AD8) FRER Passed Packet Counter Register 27 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN27_b; + }; + + union + { + __IM uint32_t FWFRDPCN27; /*!< (@ 0x00006ADC) FRER Discarded Packet Counter Register 27 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN27_b; + }; + + union + { + __IM uint32_t FWFRPPCN28; /*!< (@ 0x00006AE0) FRER Passed Packet Counter Register 28 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN28_b; + }; + + union + { + __IM uint32_t FWFRDPCN28; /*!< (@ 0x00006AE4) FRER Discarded Packet Counter Register 28 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN28_b; + }; + + union + { + __IM uint32_t FWFRPPCN29; /*!< (@ 0x00006AE8) FRER Passed Packet Counter Register 29 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN29_b; + }; + + union + { + __IM uint32_t FWFRDPCN29; /*!< (@ 0x00006AEC) FRER Discarded Packet Counter Register 29 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN29_b; + }; + + union + { + __IM uint32_t FWFRPPCN30; /*!< (@ 0x00006AF0) FRER Passed Packet Counter Register 30 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN30_b; + }; + + union + { + __IM uint32_t FWFRDPCN30; /*!< (@ 0x00006AF4) FRER Discarded Packet Counter Register 30 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN30_b; + }; + + union + { + __IM uint32_t FWFRPPCN31; /*!< (@ 0x00006AF8) FRER Passed Packet Counter Register 31 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN31_b; + }; + + union + { + __IM uint32_t FWFRDPCN31; /*!< (@ 0x00006AFC) FRER Discarded Packet Counter Register 31 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN31_b; + }; + + union + { + __IM uint32_t FWFRPPCN32; /*!< (@ 0x00006B00) FRER Passed Packet Counter Register 32 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN32_b; + }; + + union + { + __IM uint32_t FWFRDPCN32; /*!< (@ 0x00006B04) FRER Discarded Packet Counter Register 32 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN32_b; + }; + + union + { + __IM uint32_t FWFRPPCN33; /*!< (@ 0x00006B08) FRER Passed Packet Counter Register 33 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN33_b; + }; + + union + { + __IM uint32_t FWFRDPCN33; /*!< (@ 0x00006B0C) FRER Discarded Packet Counter Register 33 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN33_b; + }; + + union + { + __IM uint32_t FWFRPPCN34; /*!< (@ 0x00006B10) FRER Passed Packet Counter Register 34 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN34_b; + }; + + union + { + __IM uint32_t FWFRDPCN34; /*!< (@ 0x00006B14) FRER Discarded Packet Counter Register 34 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN34_b; + }; + + union + { + __IM uint32_t FWFRPPCN35; /*!< (@ 0x00006B18) FRER Passed Packet Counter Register 35 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN35_b; + }; + + union + { + __IM uint32_t FWFRDPCN35; /*!< (@ 0x00006B1C) FRER Discarded Packet Counter Register 35 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN35_b; + }; + + union + { + __IM uint32_t FWFRPPCN36; /*!< (@ 0x00006B20) FRER Passed Packet Counter Register 36 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN36_b; + }; + + union + { + __IM uint32_t FWFRDPCN36; /*!< (@ 0x00006B24) FRER Discarded Packet Counter Register 36 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN36_b; + }; + + union + { + __IM uint32_t FWFRPPCN37; /*!< (@ 0x00006B28) FRER Passed Packet Counter Register 37 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN37_b; + }; + + union + { + __IM uint32_t FWFRDPCN37; /*!< (@ 0x00006B2C) FRER Discarded Packet Counter Register 37 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN37_b; + }; + + union + { + __IM uint32_t FWFRPPCN38; /*!< (@ 0x00006B30) FRER Passed Packet Counter Register 38 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN38_b; + }; + + union + { + __IM uint32_t FWFRDPCN38; /*!< (@ 0x00006B34) FRER Discarded Packet Counter Register 38 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN38_b; + }; + + union + { + __IM uint32_t FWFRPPCN39; /*!< (@ 0x00006B38) FRER Passed Packet Counter Register 39 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN39_b; + }; + + union + { + __IM uint32_t FWFRDPCN39; /*!< (@ 0x00006B3C) FRER Discarded Packet Counter Register 39 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN39_b; + }; + + union + { + __IM uint32_t FWFRPPCN40; /*!< (@ 0x00006B40) FRER Passed Packet Counter Register 40 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN40_b; + }; + + union + { + __IM uint32_t FWFRDPCN40; /*!< (@ 0x00006B44) FRER Discarded Packet Counter Register 40 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN40_b; + }; + + union + { + __IM uint32_t FWFRPPCN41; /*!< (@ 0x00006B48) FRER Passed Packet Counter Register 41 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN41_b; + }; + + union + { + __IM uint32_t FWFRDPCN41; /*!< (@ 0x00006B4C) FRER Discarded Packet Counter Register 41 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN41_b; + }; + + union + { + __IM uint32_t FWFRPPCN42; /*!< (@ 0x00006B50) FRER Passed Packet Counter Register 42 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN42_b; + }; + + union + { + __IM uint32_t FWFRDPCN42; /*!< (@ 0x00006B54) FRER Discarded Packet Counter Register 42 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN42_b; + }; + + union + { + __IM uint32_t FWFRPPCN43; /*!< (@ 0x00006B58) FRER Passed Packet Counter Register 43 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN43_b; + }; + + union + { + __IM uint32_t FWFRDPCN43; /*!< (@ 0x00006B5C) FRER Discarded Packet Counter Register 43 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN43_b; + }; + + union + { + __IM uint32_t FWFRPPCN44; /*!< (@ 0x00006B60) FRER Passed Packet Counter Register 44 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN44_b; + }; + + union + { + __IM uint32_t FWFRDPCN44; /*!< (@ 0x00006B64) FRER Discarded Packet Counter Register 44 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN44_b; + }; + + union + { + __IM uint32_t FWFRPPCN45; /*!< (@ 0x00006B68) FRER Passed Packet Counter Register 45 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN45_b; + }; + + union + { + __IM uint32_t FWFRDPCN45; /*!< (@ 0x00006B6C) FRER Discarded Packet Counter Register 45 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN45_b; + }; + + union + { + __IM uint32_t FWFRPPCN46; /*!< (@ 0x00006B70) FRER Passed Packet Counter Register 46 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN46_b; + }; + + union + { + __IM uint32_t FWFRDPCN46; /*!< (@ 0x00006B74) FRER Discarded Packet Counter Register 46 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN46_b; + }; + + union + { + __IM uint32_t FWFRPPCN47; /*!< (@ 0x00006B78) FRER Passed Packet Counter Register 47 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN47_b; + }; + + union + { + __IM uint32_t FWFRDPCN47; /*!< (@ 0x00006B7C) FRER Discarded Packet Counter Register 47 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN47_b; + }; + + union + { + __IM uint32_t FWFRPPCN48; /*!< (@ 0x00006B80) FRER Passed Packet Counter Register 48 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN48_b; + }; + + union + { + __IM uint32_t FWFRDPCN48; /*!< (@ 0x00006B84) FRER Discarded Packet Counter Register 48 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN48_b; + }; + + union + { + __IM uint32_t FWFRPPCN49; /*!< (@ 0x00006B88) FRER Passed Packet Counter Register 49 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN49_b; + }; + + union + { + __IM uint32_t FWFRDPCN49; /*!< (@ 0x00006B8C) FRER Discarded Packet Counter Register 49 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN49_b; + }; + + union + { + __IM uint32_t FWFRPPCN50; /*!< (@ 0x00006B90) FRER Passed Packet Counter Register 50 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN50_b; + }; + + union + { + __IM uint32_t FWFRDPCN50; /*!< (@ 0x00006B94) FRER Discarded Packet Counter Register 50 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN50_b; + }; + + union + { + __IM uint32_t FWFRPPCN51; /*!< (@ 0x00006B98) FRER Passed Packet Counter Register 51 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN51_b; + }; + + union + { + __IM uint32_t FWFRDPCN51; /*!< (@ 0x00006B9C) FRER Discarded Packet Counter Register 51 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN51_b; + }; + + union + { + __IM uint32_t FWFRPPCN52; /*!< (@ 0x00006BA0) FRER Passed Packet Counter Register 52 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN52_b; + }; + + union + { + __IM uint32_t FWFRDPCN52; /*!< (@ 0x00006BA4) FRER Discarded Packet Counter Register 52 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN52_b; + }; + + union + { + __IM uint32_t FWFRPPCN53; /*!< (@ 0x00006BA8) FRER Passed Packet Counter Register 53 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN53_b; + }; + + union + { + __IM uint32_t FWFRDPCN53; /*!< (@ 0x00006BAC) FRER Discarded Packet Counter Register 53 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN53_b; + }; + + union + { + __IM uint32_t FWFRPPCN54; /*!< (@ 0x00006BB0) FRER Passed Packet Counter Register 54 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN54_b; + }; + + union + { + __IM uint32_t FWFRDPCN54; /*!< (@ 0x00006BB4) FRER Discarded Packet Counter Register 54 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN54_b; + }; + + union + { + __IM uint32_t FWFRPPCN55; /*!< (@ 0x00006BB8) FRER Passed Packet Counter Register 55 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN55_b; + }; + + union + { + __IM uint32_t FWFRDPCN55; /*!< (@ 0x00006BBC) FRER Discarded Packet Counter Register 55 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN55_b; + }; + + union + { + __IM uint32_t FWFRPPCN56; /*!< (@ 0x00006BC0) FRER Passed Packet Counter Register 56 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN56_b; + }; + + union + { + __IM uint32_t FWFRDPCN56; /*!< (@ 0x00006BC4) FRER Discarded Packet Counter Register 56 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN56_b; + }; + + union + { + __IM uint32_t FWFRPPCN57; /*!< (@ 0x00006BC8) FRER Passed Packet Counter Register 57 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN57_b; + }; + + union + { + __IM uint32_t FWFRDPCN57; /*!< (@ 0x00006BCC) FRER Discarded Packet Counter Register 57 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN57_b; + }; + + union + { + __IM uint32_t FWFRPPCN58; /*!< (@ 0x00006BD0) FRER Passed Packet Counter Register 58 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN58_b; + }; + + union + { + __IM uint32_t FWFRDPCN58; /*!< (@ 0x00006BD4) FRER Discarded Packet Counter Register 58 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN58_b; + }; + + union + { + __IM uint32_t FWFRPPCN59; /*!< (@ 0x00006BD8) FRER Passed Packet Counter Register 59 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN59_b; + }; + + union + { + __IM uint32_t FWFRDPCN59; /*!< (@ 0x00006BDC) FRER Discarded Packet Counter Register 59 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN59_b; + }; + + union + { + __IM uint32_t FWFRPPCN60; /*!< (@ 0x00006BE0) FRER Passed Packet Counter Register 60 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN60_b; + }; + + union + { + __IM uint32_t FWFRDPCN60; /*!< (@ 0x00006BE4) FRER Discarded Packet Counter Register 60 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN60_b; + }; + + union + { + __IM uint32_t FWFRPPCN61; /*!< (@ 0x00006BE8) FRER Passed Packet Counter Register 61 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN61_b; + }; + + union + { + __IM uint32_t FWFRDPCN61; /*!< (@ 0x00006BEC) FRER Discarded Packet Counter Register 61 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN61_b; + }; + + union + { + __IM uint32_t FWFRPPCN62; /*!< (@ 0x00006BF0) FRER Passed Packet Counter Register 62 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN62_b; + }; + + union + { + __IM uint32_t FWFRDPCN62; /*!< (@ 0x00006BF4) FRER Discarded Packet Counter Register 62 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN62_b; + }; + + union + { + __IM uint32_t FWFRPPCN63; /*!< (@ 0x00006BF8) FRER Passed Packet Counter Register 63 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN63_b; + }; + + union + { + __IM uint32_t FWFRDPCN63; /*!< (@ 0x00006BFC) FRER Discarded Packet Counter Register 63 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN63_b; + }; + + union + { + __IM uint32_t FWFRPPCN64; /*!< (@ 0x00006C00) FRER Passed Packet Counter Register 64 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN64_b; + }; + + union + { + __IM uint32_t FWFRDPCN64; /*!< (@ 0x00006C04) FRER Discarded Packet Counter Register 64 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN64_b; + }; + + union + { + __IM uint32_t FWFRPPCN65; /*!< (@ 0x00006C08) FRER Passed Packet Counter Register 65 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN65_b; + }; + + union + { + __IM uint32_t FWFRDPCN65; /*!< (@ 0x00006C0C) FRER Discarded Packet Counter Register 65 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN65_b; + }; + + union + { + __IM uint32_t FWFRPPCN66; /*!< (@ 0x00006C10) FRER Passed Packet Counter Register 66 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN66_b; + }; + + union + { + __IM uint32_t FWFRDPCN66; /*!< (@ 0x00006C14) FRER Discarded Packet Counter Register 66 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN66_b; + }; + + union + { + __IM uint32_t FWFRPPCN67; /*!< (@ 0x00006C18) FRER Passed Packet Counter Register 67 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN67_b; + }; + + union + { + __IM uint32_t FWFRDPCN67; /*!< (@ 0x00006C1C) FRER Discarded Packet Counter Register 67 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN67_b; + }; + + union + { + __IM uint32_t FWFRPPCN68; /*!< (@ 0x00006C20) FRER Passed Packet Counter Register 68 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN68_b; + }; + + union + { + __IM uint32_t FWFRDPCN68; /*!< (@ 0x00006C24) FRER Discarded Packet Counter Register 68 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN68_b; + }; + + union + { + __IM uint32_t FWFRPPCN69; /*!< (@ 0x00006C28) FRER Passed Packet Counter Register 69 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN69_b; + }; + + union + { + __IM uint32_t FWFRDPCN69; /*!< (@ 0x00006C2C) FRER Discarded Packet Counter Register 69 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN69_b; + }; + + union + { + __IM uint32_t FWFRPPCN70; /*!< (@ 0x00006C30) FRER Passed Packet Counter Register 70 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN70_b; + }; + + union + { + __IM uint32_t FWFRDPCN70; /*!< (@ 0x00006C34) FRER Discarded Packet Counter Register 70 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN70_b; + }; + + union + { + __IM uint32_t FWFRPPCN71; /*!< (@ 0x00006C38) FRER Passed Packet Counter Register 71 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN71_b; + }; + + union + { + __IM uint32_t FWFRDPCN71; /*!< (@ 0x00006C3C) FRER Discarded Packet Counter Register 71 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN71_b; + }; + + union + { + __IM uint32_t FWFRPPCN72; /*!< (@ 0x00006C40) FRER Passed Packet Counter Register 72 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN72_b; + }; + + union + { + __IM uint32_t FWFRDPCN72; /*!< (@ 0x00006C44) FRER Discarded Packet Counter Register 72 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN72_b; + }; + + union + { + __IM uint32_t FWFRPPCN73; /*!< (@ 0x00006C48) FRER Passed Packet Counter Register 73 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN73_b; + }; + + union + { + __IM uint32_t FWFRDPCN73; /*!< (@ 0x00006C4C) FRER Discarded Packet Counter Register 73 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN73_b; + }; + + union + { + __IM uint32_t FWFRPPCN74; /*!< (@ 0x00006C50) FRER Passed Packet Counter Register 74 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN74_b; + }; + + union + { + __IM uint32_t FWFRDPCN74; /*!< (@ 0x00006C54) FRER Discarded Packet Counter Register 74 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN74_b; + }; + + union + { + __IM uint32_t FWFRPPCN75; /*!< (@ 0x00006C58) FRER Passed Packet Counter Register 75 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN75_b; + }; + + union + { + __IM uint32_t FWFRDPCN75; /*!< (@ 0x00006C5C) FRER Discarded Packet Counter Register 75 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN75_b; + }; + + union + { + __IM uint32_t FWFRPPCN76; /*!< (@ 0x00006C60) FRER Passed Packet Counter Register 76 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN76_b; + }; + + union + { + __IM uint32_t FWFRDPCN76; /*!< (@ 0x00006C64) FRER Discarded Packet Counter Register 76 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN76_b; + }; + + union + { + __IM uint32_t FWFRPPCN77; /*!< (@ 0x00006C68) FRER Passed Packet Counter Register 77 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN77_b; + }; + + union + { + __IM uint32_t FWFRDPCN77; /*!< (@ 0x00006C6C) FRER Discarded Packet Counter Register 77 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN77_b; + }; + + union + { + __IM uint32_t FWFRPPCN78; /*!< (@ 0x00006C70) FRER Passed Packet Counter Register 78 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN78_b; + }; + + union + { + __IM uint32_t FWFRDPCN78; /*!< (@ 0x00006C74) FRER Discarded Packet Counter Register 78 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN78_b; + }; + + union + { + __IM uint32_t FWFRPPCN79; /*!< (@ 0x00006C78) FRER Passed Packet Counter Register 79 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN79_b; + }; + + union + { + __IM uint32_t FWFRDPCN79; /*!< (@ 0x00006C7C) FRER Discarded Packet Counter Register 79 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN79_b; + }; + + union + { + __IM uint32_t FWFRPPCN80; /*!< (@ 0x00006C80) FRER Passed Packet Counter Register 80 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN80_b; + }; + + union + { + __IM uint32_t FWFRDPCN80; /*!< (@ 0x00006C84) FRER Discarded Packet Counter Register 80 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN80_b; + }; + + union + { + __IM uint32_t FWFRPPCN81; /*!< (@ 0x00006C88) FRER Passed Packet Counter Register 81 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN81_b; + }; + + union + { + __IM uint32_t FWFRDPCN81; /*!< (@ 0x00006C8C) FRER Discarded Packet Counter Register 81 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN81_b; + }; + + union + { + __IM uint32_t FWFRPPCN82; /*!< (@ 0x00006C90) FRER Passed Packet Counter Register 82 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN82_b; + }; + + union + { + __IM uint32_t FWFRDPCN82; /*!< (@ 0x00006C94) FRER Discarded Packet Counter Register 82 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN82_b; + }; + + union + { + __IM uint32_t FWFRPPCN83; /*!< (@ 0x00006C98) FRER Passed Packet Counter Register 83 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN83_b; + }; + + union + { + __IM uint32_t FWFRDPCN83; /*!< (@ 0x00006C9C) FRER Discarded Packet Counter Register 83 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN83_b; + }; + + union + { + __IM uint32_t FWFRPPCN84; /*!< (@ 0x00006CA0) FRER Passed Packet Counter Register 84 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN84_b; + }; + + union + { + __IM uint32_t FWFRDPCN84; /*!< (@ 0x00006CA4) FRER Discarded Packet Counter Register 84 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN84_b; + }; + + union + { + __IM uint32_t FWFRPPCN85; /*!< (@ 0x00006CA8) FRER Passed Packet Counter Register 85 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN85_b; + }; + + union + { + __IM uint32_t FWFRDPCN85; /*!< (@ 0x00006CAC) FRER Discarded Packet Counter Register 85 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN85_b; + }; + + union + { + __IM uint32_t FWFRPPCN86; /*!< (@ 0x00006CB0) FRER Passed Packet Counter Register 86 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN86_b; + }; + + union + { + __IM uint32_t FWFRDPCN86; /*!< (@ 0x00006CB4) FRER Discarded Packet Counter Register 86 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN86_b; + }; + + union + { + __IM uint32_t FWFRPPCN87; /*!< (@ 0x00006CB8) FRER Passed Packet Counter Register 87 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN87_b; + }; + + union + { + __IM uint32_t FWFRDPCN87; /*!< (@ 0x00006CBC) FRER Discarded Packet Counter Register 87 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN87_b; + }; + + union + { + __IM uint32_t FWFRPPCN88; /*!< (@ 0x00006CC0) FRER Passed Packet Counter Register 88 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN88_b; + }; + + union + { + __IM uint32_t FWFRDPCN88; /*!< (@ 0x00006CC4) FRER Discarded Packet Counter Register 88 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN88_b; + }; + + union + { + __IM uint32_t FWFRPPCN89; /*!< (@ 0x00006CC8) FRER Passed Packet Counter Register 89 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN89_b; + }; + + union + { + __IM uint32_t FWFRDPCN89; /*!< (@ 0x00006CCC) FRER Discarded Packet Counter Register 89 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN89_b; + }; + + union + { + __IM uint32_t FWFRPPCN90; /*!< (@ 0x00006CD0) FRER Passed Packet Counter Register 90 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN90_b; + }; + + union + { + __IM uint32_t FWFRDPCN90; /*!< (@ 0x00006CD4) FRER Discarded Packet Counter Register 90 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN90_b; + }; + + union + { + __IM uint32_t FWFRPPCN91; /*!< (@ 0x00006CD8) FRER Passed Packet Counter Register 91 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN91_b; + }; + + union + { + __IM uint32_t FWFRDPCN91; /*!< (@ 0x00006CDC) FRER Discarded Packet Counter Register 91 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN91_b; + }; + + union + { + __IM uint32_t FWFRPPCN92; /*!< (@ 0x00006CE0) FRER Passed Packet Counter Register 92 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN92_b; + }; + + union + { + __IM uint32_t FWFRDPCN92; /*!< (@ 0x00006CE4) FRER Discarded Packet Counter Register 92 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN92_b; + }; + + union + { + __IM uint32_t FWFRPPCN93; /*!< (@ 0x00006CE8) FRER Passed Packet Counter Register 93 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN93_b; + }; + + union + { + __IM uint32_t FWFRDPCN93; /*!< (@ 0x00006CEC) FRER Discarded Packet Counter Register 93 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN93_b; + }; + + union + { + __IM uint32_t FWFRPPCN94; /*!< (@ 0x00006CF0) FRER Passed Packet Counter Register 94 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN94_b; + }; + + union + { + __IM uint32_t FWFRDPCN94; /*!< (@ 0x00006CF4) FRER Discarded Packet Counter Register 94 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN94_b; + }; + + union + { + __IM uint32_t FWFRPPCN95; /*!< (@ 0x00006CF8) FRER Passed Packet Counter Register 95 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN95_b; + }; + + union + { + __IM uint32_t FWFRDPCN95; /*!< (@ 0x00006CFC) FRER Discarded Packet Counter Register 95 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN95_b; + }; + + union + { + __IM uint32_t FWFRPPCN96; /*!< (@ 0x00006D00) FRER Passed Packet Counter Register 96 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN96_b; + }; + + union + { + __IM uint32_t FWFRDPCN96; /*!< (@ 0x00006D04) FRER Discarded Packet Counter Register 96 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN96_b; + }; + + union + { + __IM uint32_t FWFRPPCN97; /*!< (@ 0x00006D08) FRER Passed Packet Counter Register 97 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN97_b; + }; + + union + { + __IM uint32_t FWFRDPCN97; /*!< (@ 0x00006D0C) FRER Discarded Packet Counter Register 97 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN97_b; + }; + + union + { + __IM uint32_t FWFRPPCN98; /*!< (@ 0x00006D10) FRER Passed Packet Counter Register 98 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN98_b; + }; + + union + { + __IM uint32_t FWFRDPCN98; /*!< (@ 0x00006D14) FRER Discarded Packet Counter Register 98 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN98_b; + }; + + union + { + __IM uint32_t FWFRPPCN99; /*!< (@ 0x00006D18) FRER Passed Packet Counter Register 99 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN99_b; + }; + + union + { + __IM uint32_t FWFRDPCN99; /*!< (@ 0x00006D1C) FRER Discarded Packet Counter Register 99 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN99_b; + }; + + union + { + __IM uint32_t FWFRPPCN100; /*!< (@ 0x00006D20) FRER Passed Packet Counter Register 100 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN100_b; + }; + + union + { + __IM uint32_t FWFRDPCN100; /*!< (@ 0x00006D24) FRER Discarded Packet Counter Register 100 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN100_b; + }; + + union + { + __IM uint32_t FWFRPPCN101; /*!< (@ 0x00006D28) FRER Passed Packet Counter Register 101 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN101_b; + }; + + union + { + __IM uint32_t FWFRDPCN101; /*!< (@ 0x00006D2C) FRER Discarded Packet Counter Register 101 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN101_b; + }; + + union + { + __IM uint32_t FWFRPPCN102; /*!< (@ 0x00006D30) FRER Passed Packet Counter Register 102 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN102_b; + }; + + union + { + __IM uint32_t FWFRDPCN102; /*!< (@ 0x00006D34) FRER Discarded Packet Counter Register 102 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN102_b; + }; + + union + { + __IM uint32_t FWFRPPCN103; /*!< (@ 0x00006D38) FRER Passed Packet Counter Register 103 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN103_b; + }; + + union + { + __IM uint32_t FWFRDPCN103; /*!< (@ 0x00006D3C) FRER Discarded Packet Counter Register 103 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN103_b; + }; + + union + { + __IM uint32_t FWFRPPCN104; /*!< (@ 0x00006D40) FRER Passed Packet Counter Register 104 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN104_b; + }; + + union + { + __IM uint32_t FWFRDPCN104; /*!< (@ 0x00006D44) FRER Discarded Packet Counter Register 104 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN104_b; + }; + + union + { + __IM uint32_t FWFRPPCN105; /*!< (@ 0x00006D48) FRER Passed Packet Counter Register 105 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN105_b; + }; + + union + { + __IM uint32_t FWFRDPCN105; /*!< (@ 0x00006D4C) FRER Discarded Packet Counter Register 105 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN105_b; + }; + + union + { + __IM uint32_t FWFRPPCN106; /*!< (@ 0x00006D50) FRER Passed Packet Counter Register 106 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN106_b; + }; + + union + { + __IM uint32_t FWFRDPCN106; /*!< (@ 0x00006D54) FRER Discarded Packet Counter Register 106 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN106_b; + }; + + union + { + __IM uint32_t FWFRPPCN107; /*!< (@ 0x00006D58) FRER Passed Packet Counter Register 107 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN107_b; + }; + + union + { + __IM uint32_t FWFRDPCN107; /*!< (@ 0x00006D5C) FRER Discarded Packet Counter Register 107 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN107_b; + }; + + union + { + __IM uint32_t FWFRPPCN108; /*!< (@ 0x00006D60) FRER Passed Packet Counter Register 108 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN108_b; + }; + + union + { + __IM uint32_t FWFRDPCN108; /*!< (@ 0x00006D64) FRER Discarded Packet Counter Register 108 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN108_b; + }; + + union + { + __IM uint32_t FWFRPPCN109; /*!< (@ 0x00006D68) FRER Passed Packet Counter Register 109 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN109_b; + }; + + union + { + __IM uint32_t FWFRDPCN109; /*!< (@ 0x00006D6C) FRER Discarded Packet Counter Register 109 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN109_b; + }; + + union + { + __IM uint32_t FWFRPPCN110; /*!< (@ 0x00006D70) FRER Passed Packet Counter Register 110 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN110_b; + }; + + union + { + __IM uint32_t FWFRDPCN110; /*!< (@ 0x00006D74) FRER Discarded Packet Counter Register 110 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN110_b; + }; + + union + { + __IM uint32_t FWFRPPCN111; /*!< (@ 0x00006D78) FRER Passed Packet Counter Register 111 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN111_b; + }; + + union + { + __IM uint32_t FWFRDPCN111; /*!< (@ 0x00006D7C) FRER Discarded Packet Counter Register 111 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN111_b; + }; + + union + { + __IM uint32_t FWFRPPCN112; /*!< (@ 0x00006D80) FRER Passed Packet Counter Register 112 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN112_b; + }; + + union + { + __IM uint32_t FWFRDPCN112; /*!< (@ 0x00006D84) FRER Discarded Packet Counter Register 112 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN112_b; + }; + + union + { + __IM uint32_t FWFRPPCN113; /*!< (@ 0x00006D88) FRER Passed Packet Counter Register 113 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN113_b; + }; + + union + { + __IM uint32_t FWFRDPCN113; /*!< (@ 0x00006D8C) FRER Discarded Packet Counter Register 113 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN113_b; + }; + + union + { + __IM uint32_t FWFRPPCN114; /*!< (@ 0x00006D90) FRER Passed Packet Counter Register 114 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN114_b; + }; + + union + { + __IM uint32_t FWFRDPCN114; /*!< (@ 0x00006D94) FRER Discarded Packet Counter Register 114 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN114_b; + }; + + union + { + __IM uint32_t FWFRPPCN115; /*!< (@ 0x00006D98) FRER Passed Packet Counter Register 115 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN115_b; + }; + + union + { + __IM uint32_t FWFRDPCN115; /*!< (@ 0x00006D9C) FRER Discarded Packet Counter Register 115 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN115_b; + }; + + union + { + __IM uint32_t FWFRPPCN116; /*!< (@ 0x00006DA0) FRER Passed Packet Counter Register 116 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN116_b; + }; + + union + { + __IM uint32_t FWFRDPCN116; /*!< (@ 0x00006DA4) FRER Discarded Packet Counter Register 116 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN116_b; + }; + + union + { + __IM uint32_t FWFRPPCN117; /*!< (@ 0x00006DA8) FRER Passed Packet Counter Register 117 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN117_b; + }; + + union + { + __IM uint32_t FWFRDPCN117; /*!< (@ 0x00006DAC) FRER Discarded Packet Counter Register 117 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN117_b; + }; + + union + { + __IM uint32_t FWFRPPCN118; /*!< (@ 0x00006DB0) FRER Passed Packet Counter Register 118 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN118_b; + }; + + union + { + __IM uint32_t FWFRDPCN118; /*!< (@ 0x00006DB4) FRER Discarded Packet Counter Register 118 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN118_b; + }; + + union + { + __IM uint32_t FWFRPPCN119; /*!< (@ 0x00006DB8) FRER Passed Packet Counter Register 119 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN119_b; + }; + + union + { + __IM uint32_t FWFRDPCN119; /*!< (@ 0x00006DBC) FRER Discarded Packet Counter Register 119 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN119_b; + }; + + union + { + __IM uint32_t FWFRPPCN120; /*!< (@ 0x00006DC0) FRER Passed Packet Counter Register 120 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN120_b; + }; + + union + { + __IM uint32_t FWFRDPCN120; /*!< (@ 0x00006DC4) FRER Discarded Packet Counter Register 120 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN120_b; + }; + + union + { + __IM uint32_t FWFRPPCN121; /*!< (@ 0x00006DC8) FRER Passed Packet Counter Register 121 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN121_b; + }; + + union + { + __IM uint32_t FWFRDPCN121; /*!< (@ 0x00006DCC) FRER Discarded Packet Counter Register 121 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN121_b; + }; + + union + { + __IM uint32_t FWFRPPCN122; /*!< (@ 0x00006DD0) FRER Passed Packet Counter Register 122 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN122_b; + }; + + union + { + __IM uint32_t FWFRDPCN122; /*!< (@ 0x00006DD4) FRER Discarded Packet Counter Register 122 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN122_b; + }; + + union + { + __IM uint32_t FWFRPPCN123; /*!< (@ 0x00006DD8) FRER Passed Packet Counter Register 123 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN123_b; + }; + + union + { + __IM uint32_t FWFRDPCN123; /*!< (@ 0x00006DDC) FRER Discarded Packet Counter Register 123 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN123_b; + }; + + union + { + __IM uint32_t FWFRPPCN124; /*!< (@ 0x00006DE0) FRER Passed Packet Counter Register 124 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN124_b; + }; + + union + { + __IM uint32_t FWFRDPCN124; /*!< (@ 0x00006DE4) FRER Discarded Packet Counter Register 124 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN124_b; + }; + + union + { + __IM uint32_t FWFRPPCN125; /*!< (@ 0x00006DE8) FRER Passed Packet Counter Register 125 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN125_b; + }; + + union + { + __IM uint32_t FWFRDPCN125; /*!< (@ 0x00006DEC) FRER Discarded Packet Counter Register 125 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN125_b; + }; + + union + { + __IM uint32_t FWFRPPCN126; /*!< (@ 0x00006DF0) FRER Passed Packet Counter Register 126 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN126_b; + }; + + union + { + __IM uint32_t FWFRDPCN126; /*!< (@ 0x00006DF4) FRER Discarded Packet Counter Register 126 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN126_b; + }; + + union + { + __IM uint32_t FWFRPPCN127; /*!< (@ 0x00006DF8) FRER Passed Packet Counter Register 127 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN127_b; + }; + + union + { + __IM uint32_t FWFRDPCN127; /*!< (@ 0x00006DFC) FRER Discarded Packet Counter Register 127 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN127_b; + }; + __IM uint32_t RESERVED261[704]; + + union + { + __IOM uint32_t FWEIS00; /*!< (@ 0x00007900) Error Interrupt Status Register 00 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS00_b; + }; + + union + { + __IOM uint32_t FWEIE00; /*!< (@ 0x00007904) Error Interrupt Enable Register 00 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE00_b; + }; + + union + { + __IOM uint32_t FWEID00; /*!< (@ 0x00007908) Error Interrupt Disable Register 00 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID00_b; + }; + __IM uint32_t RESERVED262; + + union + { + __IOM uint32_t FWEIS01; /*!< (@ 0x00007910) Error Interrupt Status Register 01 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS01_b; + }; + + union + { + __IOM uint32_t FWEIE01; /*!< (@ 0x00007914) Error Interrupt Enable Register 01 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE01_b; + }; + + union + { + __IOM uint32_t FWEID01; /*!< (@ 0x00007918) Error Interrupt Disable Register 01 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID01_b; + }; + __IM uint32_t RESERVED263; + + union + { + __IOM uint32_t FWEIS02; /*!< (@ 0x00007920) Error Interrupt Status Register 02 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS02_b; + }; + + union + { + __IOM uint32_t FWEIE02; /*!< (@ 0x00007924) Error Interrupt Enable Register 02 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE02_b; + }; + + union + { + __IOM uint32_t FWEID02; /*!< (@ 0x00007928) Error Interrupt Disable Register 02 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID02_b; + }; + __IM uint32_t RESERVED264[53]; + + union + { + __IOM uint32_t FWEIS1; /*!< (@ 0x00007A00) Error Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t LTHTEES : 1; /*!< [0..0] L3 Table ECC Error Status */ + __IOM uint32_t LTHTSES : 1; /*!< [1..1] L3 Table Security Error Status */ + uint32_t : 2; + __IOM uint32_t MACTEES : 1; /*!< [4..4] MAC Table ECC Error Status */ + __IOM uint32_t MACTSES : 1; /*!< [5..5] MAC Table Security Error Status */ + __IOM uint32_t VLANTEES : 1; /*!< [6..6] VLAN Table ECC Error Status */ + __IOM uint32_t VLANTSES : 1; /*!< [7..7] VLAN Table Security Error Status */ + __IOM uint32_t L23UEES : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Status */ + uint32_t : 7; + __IOM uint32_t AREES : 1; /*!< [16..16] ATS RAM ECC Error Status */ + uint32_t : 15; + } FWEIS1_b; + }; + + union + { + __IOM uint32_t FWEIE1; /*!< (@ 0x00007A04) Error Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t LTHTEEE : 1; /*!< [0..0] L3 Table ECC Error Enable */ + __IOM uint32_t LTHTSEE : 1; /*!< [1..1] L3 Table Security Error Enable */ + uint32_t : 2; + __IOM uint32_t MACTEEE : 1; /*!< [4..4] MAC Table ECC Error Enable */ + __IOM uint32_t MACTSEE : 1; /*!< [5..5] MAC Table Security Error Enable */ + __IOM uint32_t VLANTEEE : 1; /*!< [6..6] VLAN Table ECC Error Enable */ + __IOM uint32_t VLANTSEE : 1; /*!< [7..7] VLAN Table Security Error Enable */ + __IOM uint32_t L23UEEE : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Enable */ + uint32_t : 7; + __IOM uint32_t AREEE : 1; /*!< [16..16] ATS RAM ECC Error Enable */ + uint32_t : 15; + } FWEIE1_b; + }; + + union + { + __IOM uint32_t FWEID1; /*!< (@ 0x00007A08) Error Interrupt Disable Register 1 */ + + struct + { + __IOM uint32_t LTHTEED : 1; /*!< [0..0] L3 Table ECC Error Disable */ + __IOM uint32_t LTHTSED : 1; /*!< [1..1] L3 Table Security Error Disable */ + uint32_t : 2; + __IOM uint32_t MACTEED : 1; /*!< [4..4] MAC Table ECC Error Disable */ + __IOM uint32_t MACTSED : 1; /*!< [5..5] MAC Table Security Error Disable */ + __IOM uint32_t VLANTEED : 1; /*!< [6..6] VLAN Table ECC Error Disable */ + __IOM uint32_t VLANTSED : 1; /*!< [7..7] VLAN Table Security Error Disable */ + __IOM uint32_t L23UEED : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Disable */ + uint32_t : 7; + __IOM uint32_t AREED : 1; /*!< [16..16] ATS RAM ECC Error Disable */ + uint32_t : 15; + } FWEID1_b; + }; + __IM uint32_t RESERVED265; + + union + { + __IOM uint32_t FWEIS2; /*!< (@ 0x00007A10) Error Interrupt Status Register 2 */ + + struct + { + __IOM uint32_t PMFS : 16; /*!< [15..0] PSFP MSDU Filtering Status */ + uint32_t : 16; + } FWEIS2_b; + }; + + union + { + __IOM uint32_t FWEIE2; /*!< (@ 0x00007A14) Error Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t PMFE : 16; /*!< [15..0] PSFP MSDU Filtering Enable */ + uint32_t : 16; + } FWEIE2_b; + }; + + union + { + __IOM uint32_t FWEID2; /*!< (@ 0x00007A18) Error Interrupt Disable Register 2 */ + + struct + { + __IOM uint32_t PMFD : 16; /*!< [15..0] PSFP MSDU Filtering Disable */ + uint32_t : 16; + } FWEID2_b; + }; + __IM uint32_t RESERVED266[9]; + + union + { + __IOM uint32_t FWEIS5; /*!< (@ 0x00007A40) Error Interrupt Status Register 5 */ + + struct + { + __IOM uint32_t PMRFS : 32; /*!< [31..0] PSFP Meter Filtering Status */ + } FWEIS5_b; + }; + + union + { + __IOM uint32_t FWEIE5; /*!< (@ 0x00007A44) Error Interrupt Enable Register 5 */ + + struct + { + __IOM uint32_t PMRFE : 32; /*!< [31..0] PSFP Meter Filtering Enable */ + } FWEIE5_b; + }; + + union + { + __IOM uint32_t FWEID5; /*!< (@ 0x00007A48) Error Interrupt Disable Register 5 */ + + struct + { + __IOM uint32_t PMRFD : 32; /*!< [31..0] PSFP Meter Filtering Disable */ + } FWEID5_b; + }; + __IM uint32_t RESERVED267; + + union + { + __IOM uint32_t FWEIS60; /*!< (@ 0x00007A50) Error Interrupt Status Register 60 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS60_b; + }; + + union + { + __IOM uint32_t FWEIE60; /*!< (@ 0x00007A54) Error Interrupt Enable Register 60 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE60_b; + }; + + union + { + __IOM uint32_t FWEID60; /*!< (@ 0x00007A58) Error Interrupt Disable Register 60 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID60_b; + }; + __IM uint32_t RESERVED268; + + union + { + __IOM uint32_t FWEIS61; /*!< (@ 0x00007A60) Error Interrupt Status Register 61 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS61_b; + }; + + union + { + __IOM uint32_t FWEIE61; /*!< (@ 0x00007A64) Error Interrupt Enable Register 61 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE61_b; + }; + + union + { + __IOM uint32_t FWEID61; /*!< (@ 0x00007A68) Error Interrupt Disable Register 61 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID61_b; + }; + __IM uint32_t RESERVED269; + + union + { + __IOM uint32_t FWEIS62; /*!< (@ 0x00007A70) Error Interrupt Status Register 62 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS62_b; + }; + + union + { + __IOM uint32_t FWEIE62; /*!< (@ 0x00007A74) Error Interrupt Enable Register 62 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE62_b; + }; + + union + { + __IOM uint32_t FWEID62; /*!< (@ 0x00007A78) Error Interrupt Disable Register 62 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID62_b; + }; + __IM uint32_t RESERVED270; + + union + { + __IOM uint32_t FWEIS63; /*!< (@ 0x00007A80) Error Interrupt Status Register 63 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS63_b; + }; + + union + { + __IOM uint32_t FWEIE63; /*!< (@ 0x00007A84) Error Interrupt Enable Register 63 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE63_b; + }; + + union + { + __IOM uint32_t FWEID63; /*!< (@ 0x00007A88) Error Interrupt Disable Register 63 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID63_b; + }; + __IM uint32_t RESERVED271; + + union + { + __IOM uint32_t FWEIS70; /*!< (@ 0x00007A90) Error Interrupt Status Register 70 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS70_b; + }; + + union + { + __IOM uint32_t FWEIE70; /*!< (@ 0x00007A94) Error Interrupt Enable Register 70 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE70_b; + }; + + union + { + __IOM uint32_t FWEID70; /*!< (@ 0x00007A98) Error Interrupt Disable Register 70 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID70_b; + }; + __IM uint32_t RESERVED272; + + union + { + __IOM uint32_t FWEIS71; /*!< (@ 0x00007AA0) Error Interrupt Status Register 71 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS71_b; + }; + + union + { + __IOM uint32_t FWEIE71; /*!< (@ 0x00007AA4) Error Interrupt Enable Register 71 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE71_b; + }; + + union + { + __IOM uint32_t FWEID71; /*!< (@ 0x00007AA8) Error Interrupt Disable Register 71 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID71_b; + }; + __IM uint32_t RESERVED273; + + union + { + __IOM uint32_t FWEIS72; /*!< (@ 0x00007AB0) Error Interrupt Status Register 72 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS72_b; + }; + + union + { + __IOM uint32_t FWEIE72; /*!< (@ 0x00007AB4) Error Interrupt Enable Register 72 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE72_b; + }; + + union + { + __IOM uint32_t FWEID72; /*!< (@ 0x00007AB8) Error Interrupt Disable Register 72 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID72_b; + }; + __IM uint32_t RESERVED274; + + union + { + __IOM uint32_t FWEIS73; /*!< (@ 0x00007AC0) Error Interrupt Status Register 73 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS73_b; + }; + + union + { + __IOM uint32_t FWEIE73; /*!< (@ 0x00007AC4) Error Interrupt Enable Register 73 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE73_b; + }; + + union + { + __IOM uint32_t FWEID73; /*!< (@ 0x00007AC8) Error Interrupt Disable Register 73 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID73_b; + }; + __IM uint32_t RESERVED275; + + union + { + __IOM uint32_t FWEIS80; /*!< (@ 0x00007AD0) Error Interrupt Status Register 80 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS80_b; + }; + + union + { + __IOM uint32_t FWEIE80; /*!< (@ 0x00007AD4) Error Interrupt Enable Register 80 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE80_b; + }; + + union + { + __IOM uint32_t FWEID80; /*!< (@ 0x00007AD8) Error Interrupt Disable Register 80 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID80_b; + }; + __IM uint32_t RESERVED276; + + union + { + __IOM uint32_t FWEIS81; /*!< (@ 0x00007AE0) Error Interrupt Status Register 81 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS81_b; + }; + + union + { + __IOM uint32_t FWEIE81; /*!< (@ 0x00007AE4) Error Interrupt Enable Register 81 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE81_b; + }; + + union + { + __IOM uint32_t FWEID81; /*!< (@ 0x00007AE8) Error Interrupt Disable Register 81 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID81_b; + }; + __IM uint32_t RESERVED277; + + union + { + __IOM uint32_t FWEIS82; /*!< (@ 0x00007AF0) Error Interrupt Status Register 82 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS82_b; + }; + + union + { + __IOM uint32_t FWEIE82; /*!< (@ 0x00007AF4) Error Interrupt Enable Register 82 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE82_b; + }; + + union + { + __IOM uint32_t FWEID82; /*!< (@ 0x00007AF8) Error Interrupt Disable Register 82 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID82_b; + }; + __IM uint32_t RESERVED278; + + union + { + __IOM uint32_t FWEIS83; /*!< (@ 0x00007B00) Error Interrupt Status Register 83 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS83_b; + }; + + union + { + __IOM uint32_t FWEIE83; /*!< (@ 0x00007B04) Error Interrupt Enable Register 83 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE83_b; + }; + + union + { + __IOM uint32_t FWEID83; /*!< (@ 0x00007B08) Error Interrupt Disable Register 83 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID83_b; + }; + __IM uint32_t RESERVED279[61]; + + union + { + __IOM uint32_t FWMIS0; /*!< (@ 0x00007C00) Monitoring Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t LTHTFS : 1; /*!< [0..0] L3 Table Full Status */ + uint32_t : 1; + __IOM uint32_t MACTFS : 1; /*!< [2..2] MAC Table Full Status */ + __IOM uint32_t VLANTFS : 1; /*!< [3..3] VLAN Table Full Status */ + uint32_t : 13; + __IOM uint32_t MACADAS : 1; /*!< [17..17] MAC Address Deleted Aging Status */ + uint32_t : 14; + } FWMIS0_b; + }; + + union + { + __IOM uint32_t FWMIE0; /*!< (@ 0x00007C04) Monitoring Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t LTHTFE : 1; /*!< [0..0] L3 Table Full Enable */ + uint32_t : 1; + __IOM uint32_t MACTFE : 1; /*!< [2..2] MAC Table Full Enable */ + __IOM uint32_t VLANTFE : 1; /*!< [3..3] VLAN Table Full Enable */ + uint32_t : 13; + __IOM uint32_t MACADAE : 1; /*!< [17..17] MAC Address Deleted Aging Enable */ + uint32_t : 14; + } FWMIE0_b; + }; + + union + { + __IOM uint32_t FWMID0; /*!< (@ 0x00007C08) Monitoring Interrupt Disable Register 0 */ + + struct + { + __IOM uint32_t LTHTFD : 1; /*!< [0..0] L3 Table Full Disable */ + uint32_t : 1; + __IOM uint32_t MACTFD : 1; /*!< [2..2] MAC Table Full Disable */ + __IOM uint32_t VLANTFD : 1; /*!< [3..3] VLAN Table Full Disable */ + uint32_t : 13; + __IOM uint32_t MACADAD : 1; /*!< [17..17] MAC Address Deleted Aging Disable */ + uint32_t : 14; + } FWMID0_b; + }; +} R_MFWD_Type; /*!< Size = 31756 (0x7c0c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DSI Link (R_MIPI_DSI) + */ + +typedef struct /*!< (@ 0x40346000) R_MIPI_DSI Structure */ +{ + union + { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt Status Register */ + + struct + { + __IM uint32_t SQ0 : 1; /*!< [0..0] Sequence Channel-0 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t SQ1 : 1; /*!< [4..4] Sequence Channel-1 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t VM : 1; /*!< [8..8] Video Mode Interrupt Flag */ + uint32_t : 3; + __IM uint32_t RCV : 1; /*!< [12..12] Receive Interrupt Flag */ + uint32_t : 3; + __IM uint32_t FERR : 1; /*!< [16..16] Fatal Error Interrupt Flag */ + uint32_t : 3; + __IM uint32_t PPI : 1; /*!< [20..20] PPI Interrupt Flag */ + uint32_t : 11; + } ISR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IM uint32_t LINKSR; /*!< (@ 0x00000010) Link Status Register */ + + struct + { + __IM uint32_t SQ0RUN : 1; /*!< [0..0] Sequence Channel-0 Running Flag */ + uint32_t : 3; + __IM uint32_t SQ1RUN : 1; /*!< [4..4] Sequence Channel-1 Running Flag */ + uint32_t : 3; + __IM uint32_t VRUN : 1; /*!< [8..8] Video Mode Operation Running Flag */ + uint32_t : 3; + __IM uint32_t HSBUSY : 1; /*!< [12..12] HS Operation Busy Flag */ + __IM uint32_t LPBUSY : 1; /*!< [13..13] LP Operation Busy Flag */ + uint32_t : 18; + } LINKSR_b; + }; + __IM uint32_t RESERVED1[59]; + + union + { + __IOM uint32_t TXSETR; /*!< (@ 0x00000100) Transmit Set Register */ + + struct + { + __IOM uint32_t NUMLANE : 2; /*!< [1..0] Number of Lane */ + uint32_t : 6; + __IOM uint32_t CLEN : 1; /*!< [8..8] Clock Lane Enable */ + __IOM uint32_t DLEN : 1; /*!< [9..9] Data Lane Enable */ + uint32_t : 22; + } TXSETR_b; + }; + + union + { + __IOM uint32_t HSCLKSETR; /*!< (@ 0x00000104) HS Clock Set Register */ + + struct + { + __IOM uint32_t HSCLST : 1; /*!< [0..0] HS Clock Start */ + __IOM uint32_t HSCLMD : 1; /*!< [1..1] HS Clock Running Mode */ + uint32_t : 30; + } HSCLKSETR_b; + }; + + union + { + __IOM uint32_t ULPSSETR; /*!< (@ 0x00000108) ULPS Set Register */ + + struct + { + __IOM uint32_t WKUP : 8; /*!< [7..0] ULPS Wakeup Period */ + uint32_t : 24; + } ULPSSETR_b; + }; + + union + { + __OM uint32_t ULPSCR; /*!< (@ 0x0000010C) ULPS Control Register */ + + struct + { + uint32_t : 24; + __OM uint32_t CLENT : 1; /*!< [24..24] CL ULPS Enter */ + __OM uint32_t CLEXIT : 1; /*!< [25..25] CL ULPS Exit */ + uint32_t : 2; + __OM uint32_t DLENT : 1; /*!< [28..28] DL ULPS Enter */ + __OM uint32_t DLEXIT : 1; /*!< [29..29] DL ULPS Exit */ + uint32_t : 2; + } ULPSCR_b; + }; + + union + { + __IOM uint32_t RSTCR; /*!< (@ 0x00000110) Reset Control Register */ + + struct + { + __IOM uint32_t SWRST : 1; /*!< [0..0] Software Reset */ + uint32_t : 15; + __IOM uint32_t FTXSTP : 1; /*!< [16..16] Force Tx Stop Mode */ + uint32_t : 15; + } RSTCR_b; + }; + + union + { + __IM uint32_t RSTSR; /*!< (@ 0x00000114) Reset Status Register */ + + struct + { + __IM uint32_t RSTHS : 1; /*!< [0..0] HS Software Reset Status */ + __IM uint32_t RSTLP : 1; /*!< [1..1] LP Software Reset Status */ + __IM uint32_t RSTAPB : 1; /*!< [2..2] APB Software Reset Status */ + __IM uint32_t RSTAXI : 1; /*!< [3..3] AXI Software Reset Status */ + __IM uint32_t RSTV : 1; /*!< [4..4] Video Software Reset Status */ + uint32_t : 3; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 5; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 16; + } RSTSR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t DSISETR; /*!< (@ 0x00000120) DSI Set Register */ + + struct + { + __IOM uint32_t MRPSZ : 16; /*!< [15..0] Maximum Return Packet Size */ + __IOM uint32_t ECCEN : 1; /*!< [16..16] ECC Check Enable */ + uint32_t : 3; + __IOM uint32_t VC0CRCEN : 1; /*!< [20..20] VC-0 CRC Check Enable */ + __IOM uint32_t VC1CRCEN : 1; /*!< [21..21] VC-1 CRC Check Enable */ + __IOM uint32_t VC2CRCEN : 1; /*!< [22..22] VC-2 CRC Check Enable */ + __IOM uint32_t VC3CRCEN : 1; /*!< [23..23] VC-3 CRC Check Enable */ + uint32_t : 5; + __IOM uint32_t SCREN : 1; /*!< [29..29] Data Scramble Enable */ + __IOM uint32_t EXTEMD : 1; /*!< [30..30] External Tearing Effect Detection Sense Select */ + __IOM uint32_t EOTPEN : 1; /*!< [31..31] HS Transfer EoTp Enable */ + } DSISETR_b; + }; + __IM uint32_t RESERVED3[15]; + + union + { + __IOM uint32_t TXPPD0R; /*!< (@ 0x00000160) Transmit Packet Payload Data 0 Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IOM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IOM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } TXPPD0R_b; + }; + + union + { + __IOM uint32_t TXPPD1R; /*!< (@ 0x00000164) Transmit Packet Payload Data 1 Register */ + + struct + { + __IOM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 4 */ + __IOM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 5 */ + __IOM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 6 */ + __IOM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 7 */ + } TXPPD1R_b; + }; + + union + { + __IOM uint32_t TXPPD2R; /*!< (@ 0x00000168) Transmit Packet Payload Data 2 Register */ + + struct + { + __IOM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IOM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IOM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IOM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } TXPPD2R_b; + }; + + union + { + __IOM uint32_t TXPPD3R; /*!< (@ 0x0000016C) Transmit Packet Payload Data 3 Register */ + + struct + { + __IOM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IOM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IOM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IOM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } TXPPD3R_b; + }; + __IM uint32_t RESERVED4[36]; + + union + { + __IM uint32_t RXSR; /*!< (@ 0x00000200) Receive Status Register */ + + struct + { + __IM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 5; + __IM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag */ + uint32_t : 2; + __IM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag */ + __IM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag */ + __IM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag */ + __IM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag */ + __IM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag */ + __IM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag */ + __IM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag */ + __IM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag */ + __IM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag */ + __IM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag */ + __IM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag */ + __IM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag */ + uint32_t : 1; + } RXSR_b; + }; + + union + { + __IOM uint32_t RXSCR; /*!< (@ 0x00000204) Receive Status Clear Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag Clear */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag Clear */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag Clear */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag Clear */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag Clear */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag Clear */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag Clear */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag Clear */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag Clear */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag + * Clear */ + uint32_t : 1; + } RXSCR_b; + }; + + union + { + __IOM uint32_t RXIER; /*!< (@ 0x00000208) Receive Interrupt Enable Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Enable */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Enable */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Enable */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Enable */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Enable */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Enable */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Enable */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Enable */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Enable */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Enable */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Enable */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Enable */ + uint32_t : 1; + } RXIER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PRESPTOBTASETR; /*!< (@ 0x00000210) Peripheral Response Timeout BTA Set Register */ + + struct + { + __IOM uint32_t PRTBTA : 32; /*!< [31..0] Peripheral Response Timeout Count */ + } PRESPTOBTASETR_b; + }; + + union + { + __IOM uint32_t PRESPTOLPSETR; /*!< (@ 0x00000214) Peripheral Response Timeout LP Set Register */ + + struct + { + __IOM uint32_t LPWTO : 16; /*!< [15..0] LPDT WRITE Request Timeout */ + __IOM uint32_t LPRTO : 16; /*!< [31..16] LPDT READ Request Timeout */ + } PRESPTOLPSETR_b; + }; + + union + { + __IOM uint32_t PRESPTOHSSETR; /*!< (@ 0x00000218) Peripheral Response Timeout HS Set Register */ + + struct + { + __IOM uint32_t HSWTO : 16; /*!< [15..0] HS WRITE Request Timeout */ + __IOM uint32_t HSRTO : 16; /*!< [31..16] HS READ Request Timeout */ + } PRESPTOHSSETR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IM uint32_t AKEPLATIR; /*!< (@ 0x00000220) Acknowledge and Error Report Packet Parameter + * Latest Info Register */ + + struct + { + __IM uint32_t EREP : 16; /*!< [15..0] Error Report */ + __IM uint32_t VC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPLATIR_b; + }; + + union + { + __IM uint32_t AKEPACMSR; /*!< (@ 0x00000224) Acknowledge and Error Report Packet Parameter + * Accumulate Status Register */ + + struct + { + __IM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPACMSR_b; + }; + + union + { + __IOM uint32_t AKEPSCR; /*!< (@ 0x00000228) Acknowledge and Error Report Packet Parameter + * Status Clear Register */ + + struct + { + __IOM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report Clear */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPSCR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RXRSSR; /*!< (@ 0x00000230) Receive Result Saved Status Register */ + + struct + { + __IM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag */ + __IM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag */ + __IM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag */ + __IM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag */ + uint32_t : 28; + } RXRSSR_b; + }; + + union + { + __IOM uint32_t RXRSSCR; /*!< (@ 0x00000234) Receive Result Saved Status Clear Register */ + + struct + { + __IOM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag Clear */ + __IOM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag Clear */ + __IOM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag Clear */ + __IOM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag Clear */ + uint32_t : 28; + } RXRSSCR_b; + }; + + union + { + __IM uint32_t RXRINFOOWSR; /*!< (@ 0x00000238) Receive Result Info Overwrite Status Register */ + + struct + { + __IM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag */ + __IM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag */ + __IM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag */ + __IM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag */ + uint32_t : 28; + } RXRINFOOWSR_b; + }; + + union + { + __IOM uint32_t RXRINFOOWSCR; /*!< (@ 0x0000023C) Receive Result Info Overwrite Status Clear Register */ + + struct + { + __IOM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag Clear */ + __IOM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag Clear */ + __IOM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag Clear */ + __IOM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag Clear */ + uint32_t : 28; + } RXRINFOOWSCR_b; + }; + + union + { + union + { + __IM uint32_t RXRSS0R; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS0R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS0R_L; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS0R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_LL; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS0R_LL_b; + }; + + union + { + __IM uint8_t RXRSS0R_LH; /*!< (@ 0x00000241) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS0R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS0R_H; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS0R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_HL; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS0R_HL_b; + }; + + union + { + __IM uint8_t RXRSS0R_HH; /*!< (@ 0x00000243) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS0R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS1R; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS1R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS1R_L; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS1R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_LL; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS1R_LL_b; + }; + + union + { + __IM uint8_t RXRSS1R_LH; /*!< (@ 0x00000245) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS1R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS1R_H; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS1R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_HL; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS1R_HL_b; + }; + + union + { + __IM uint8_t RXRSS1R_HH; /*!< (@ 0x00000247) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS1R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS2R; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS2R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS2R_L; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS2R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_LL; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS2R_LL_b; + }; + + union + { + __IM uint8_t RXRSS2R_LH; /*!< (@ 0x00000249) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS2R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS2R_H; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS2R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_HL; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS2R_HL_b; + }; + + union + { + __IM uint8_t RXRSS2R_HH; /*!< (@ 0x0000024B) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS2R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS3R; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS3R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS3R_L; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS3R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_LL; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS3R_LL_b; + }; + + union + { + __IM uint8_t RXRSS3R_LH; /*!< (@ 0x0000024D) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS3R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS3R_H; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS3R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_HL; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS3R_HL_b; + }; + + union + { + __IM uint8_t RXRSS3R_HH; /*!< (@ 0x0000024F) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS3R_HH_b; + }; + }; + }; + }; + }; + __IM uint32_t RESERVED8[28]; + + union + { + __IM uint32_t RXPPD0R; /*!< (@ 0x000002C0) Receive Packet Payload Data 0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD0R_b; + }; + + union + { + __IM uint32_t RXPPD1R; /*!< (@ 0x000002C4) Receive Packet Payload Data 1 Register */ + + struct + { + __IM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD1R_b; + }; + + union + { + __IM uint32_t RXPPD2R; /*!< (@ 0x000002C8) Receive Packet Payload Data 2 Register */ + + struct + { + __IM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } RXPPD2R_b; + }; + + union + { + __IM uint32_t RXPPD3R; /*!< (@ 0x000002CC) Receive Packet Payload Data 3 Register */ + + struct + { + __IM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } RXPPD3R_b; + }; + __IM uint32_t RESERVED9[4]; + + union + { + __IOM uint32_t HSTXTOSETR; /*!< (@ 0x000002E0) HS TX Timeout Set Register */ + + struct + { + __IOM uint32_t HTXTO : 32; /*!< [31..0] HS TX Timeout Count */ + } HSTXTOSETR_b; + }; + + union + { + __IOM uint32_t LRXHTOSETR; /*!< (@ 0x000002E4) LRX-H Timeout Set Register */ + + struct + { + __IOM uint32_t LRXHTO : 32; /*!< [31..0] LP-RX Host Processor Timeout */ + } LRXHTOSETR_b; + }; + + union + { + __IOM uint32_t TATOSETR; /*!< (@ 0x000002E8) TA Timeout Set Register */ + + struct + { + __IOM uint32_t TATO : 32; /*!< [31..0] Turnaround Acknowledge Timeout */ + } TATOSETR_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IM uint32_t FERRSR; /*!< (@ 0x00000300) Fatal Error Status Register */ + + struct + { + __IM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 13; + __IM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag */ + __IM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag */ + __IM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag */ + __IM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag */ + __IM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag */ + uint32_t : 6; + __IM uint32_t CLP0S : 1; /*!< [27..27] LP0 Contention Error Status */ + __IM uint32_t CLP1S : 1; /*!< [28..28] LP1 Contention Error Status */ + uint32_t : 3; + } FERRSR_b; + }; + + union + { + __IOM uint32_t FERRSCR; /*!< (@ 0x00000304) Fatal Error Status Clear Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag Clear */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag Clear */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag Clear */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag Clear */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag Clear */ + uint32_t : 11; + } FERRSCR_b; + }; + + union + { + __IOM uint32_t FERRIER; /*!< (@ 0x00000308) Fatal Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Enable */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Enable */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Enable */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Enable */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Enable */ + uint32_t : 11; + } FERRIER_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t CLSTPTSETR; /*!< (@ 0x00000314) Clock Lane Stop Time Set Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CLKSTPT : 10; /*!< [11..2] Clock Stop Time */ + uint32_t : 4; + __IOM uint32_t CLKBFHT : 8; /*!< [23..16] Clock Beforehand Time */ + __IOM uint32_t CLKKPT : 8; /*!< [31..24] Clock Keep Time */ + } CLSTPTSETR_b; + }; + + union + { + __IOM uint32_t LPTRNSTSETR; /*!< (@ 0x00000318) LP Transition Time Set Register */ + + struct + { + __IOM uint32_t GOLPBKT : 10; /*!< [9..0] Go LP and Back Time */ + uint32_t : 22; + } LPTRNSTSETR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t PLSR; /*!< (@ 0x00000320) Physical Lane Status Register */ + + struct + { + __IM uint32_t CLUAN : 1; /*!< [0..0] Clock Lane UlpsActiveNot Status */ + __IM uint32_t CLSTP : 1; /*!< [1..1] Clock Lane Stop Status */ + __IM uint32_t DL0RLE : 1; /*!< [2..2] Data Lane-0 RxLpdtEsc Status */ + __IM uint32_t DL0RUE : 1; /*!< [3..3] Data Lane-0 RxUlpsEsc Status */ + __IM uint32_t DL0UAN : 1; /*!< [4..4] Data Lane-0 UlpsActiveNot Status */ + __IM uint32_t DL1UAN : 1; /*!< [5..5] Data Lane-1 UlpsActiveNot Status */ + uint32_t : 2; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 2; + __IM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag */ + __IM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag */ + uint32_t : 1; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 8; + __IM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag */ + __IM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag */ + __IM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag */ + __IM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag */ + __IM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag */ + __IM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag */ + uint32_t : 2; + } PLSR_b; + }; + + union + { + __IOM uint32_t PLSCR; /*!< (@ 0x00000324) Physical Lane Status Clear Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag Clear */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag Clear */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag Clear */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag Clear */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag Clear */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag Clear */ + uint32_t : 2; + } PLSCR_b; + }; + + union + { + __IOM uint32_t PLIER; /*!< (@ 0x00000328) Physical Lane Interrupt Enable Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Enable */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Enable */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Enable */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Enable */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Enable */ + uint32_t : 2; + } PLIER_b; + }; + __IM uint32_t RESERVED13[53]; + + union + { + __IOM uint32_t VMSET0R; /*!< (@ 0x00000400) Video Mode Set 0 Register */ + + struct + { + __OM uint32_t VSTART : 1; /*!< [0..0] Video Mode Operation Start */ + __OM uint32_t VSTOP : 1; /*!< [1..1] Video Mode Operation Stop */ + uint32_t : 6; + __IOM uint32_t HSANOLP : 1; /*!< [8..8] HSA period No LP */ + __IOM uint32_t HBPNOLP : 1; /*!< [9..9] HBP period No LP */ + __IOM uint32_t HFPNOLP : 1; /*!< [10..10] HFP period No LP */ + uint32_t : 21; + } VMSET0R_b; + }; + + union + { + __IOM uint32_t VMSET1R; /*!< (@ 0x00000404) Video Mode Set 1 Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t DLY : 12; /*!< [13..2] Delay Value */ + uint32_t : 18; + } VMSET1R_b; + }; + __IM uint32_t RESERVED14[2]; + + union + { + __IM uint32_t VMSR; /*!< (@ 0x00000410) Video Mode Status Register */ + + struct + { + __IM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag */ + __IM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag */ + __IM uint32_t RUNNING : 1; /*!< [2..2] Video Mode Operation Running Status */ + __IM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag */ + uint32_t : 16; + __IM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag */ + __IM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag */ + uint32_t : 8; + } VMSR_b; + }; + + union + { + __IOM uint32_t VMSCR; /*!< (@ 0x00000414) Video Mode Status Clear Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag Clear */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag Clear */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag Clear */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag Clear */ + uint32_t : 8; + } VMSCR_b; + }; + + union + { + __IOM uint32_t VMIER; /*!< (@ 0x00000418) Video Mode Interrupt Enable Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Enable */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Enable */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Enable */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Enable */ + uint32_t : 8; + } VMIER_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t VMPPSETR; /*!< (@ 0x00000420) Video Mode Pixel Packet Set Register */ + + struct + { + uint32_t : 15; + __IOM uint32_t TXESYNC : 1; /*!< [15..15] Transmit End of Sync Pulse */ + __IOM uint32_t DT : 6; /*!< [21..16] Video Mode Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Video Mode Virtual Channel */ + uint32_t : 8; + } VMPPSETR_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t VMVSSETR; /*!< (@ 0x00000428) Video Mode Vertical Size Set Register */ + + struct + { + __IOM uint32_t VSA : 12; /*!< [11..0] VSA Lines */ + uint32_t : 3; + __IOM uint32_t VSPOL : 1; /*!< [15..15] VSYNC Polarity */ + __IOM uint32_t VACT : 15; /*!< [30..16] Vertical Active Lines */ + uint32_t : 1; + } VMVSSETR_b; + }; + + union + { + __IOM uint32_t VMVPSETR; /*!< (@ 0x0000042C) Video Mode Vertical Porch Set Register */ + + struct + { + __IOM uint32_t VBP : 13; /*!< [12..0] VBP Lines */ + uint32_t : 3; + __IOM uint32_t VFP : 13; /*!< [28..16] VFP Lines */ + uint32_t : 3; + } VMVPSETR_b; + }; + + union + { + __IOM uint32_t VMHSSETR; /*!< (@ 0x00000430) Video Mode Horizontal Size Set Register */ + + struct + { + __IOM uint32_t HSA : 12; /*!< [11..0] HSA Pixels */ + uint32_t : 3; + __IOM uint32_t HSPOL : 1; /*!< [15..15] HSYNC Polarity */ + __IOM uint32_t HACT : 15; /*!< [30..16] HACT Pixels */ + uint32_t : 1; + } VMHSSETR_b; + }; + + union + { + __IOM uint32_t VMHPSETR; /*!< (@ 0x00000434) Video Mode Horizontal Porch Set Register */ + + struct + { + __IOM uint32_t HBP : 13; /*!< [12..0] HBP Pixels */ + uint32_t : 3; + __IOM uint32_t HFP : 13; /*!< [28..16] HFP Pixels */ + uint32_t : 3; + } VMHPSETR_b; + }; + __IM uint32_t RESERVED17[98]; + + union + { + __IOM uint32_t SQCH0SET0R; /*!< (@ 0x000005C0) Sequence Channel 0 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH0SET0R_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IM uint32_t SQCH0SR; /*!< (@ 0x000005D0) Sequence Channel 0 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH0SR_b; + }; + + union + { + __IOM uint32_t SQCH0SCR; /*!< (@ 0x000005D4) Sequence Channel 0 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH0SCR_b; + }; + + union + { + __IOM uint32_t SQCH0IER; /*!< (@ 0x000005D8) Sequence Channel 0 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH0IER_b; + }; + __IM uint32_t RESERVED19[9]; + + union + { + __IOM uint32_t SQCH1SET0R; /*!< (@ 0x00000600) Sequence Channel 1 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH1SET0R_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IM uint32_t SQCH1SR; /*!< (@ 0x00000610) Sequence Channel 1 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH1SR_b; + }; + + union + { + __IOM uint32_t SQCH1SCR; /*!< (@ 0x00000614) Sequence Channel 1 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH1SCR_b; + }; + + union + { + __IOM uint32_t SQCH1IER; /*!< (@ 0x00000618) Sequence Channel 1 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH1IER_b; + }; + __IM uint32_t RESERVED21[89]; + + union + { + union + { + __IOM uint32_t SQCH0DSC0AR; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_L; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_LL; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_LH; /*!< (@ 0x00000781) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_H; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_HL; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_HH; /*!< (@ 0x00000783) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC0BR; /*!< (@ 0x00000784) Sequence Channel 0 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0CR; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_L; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_LL; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_H; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0CR_HL; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_HH; /*!< (@ 0x0000078B) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0DR; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_L; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_LL; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_LH; /*!< (@ 0x0000078D) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_H; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_HL; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_HH; /*!< (@ 0x0000078F) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1AR; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_L; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_LL; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_LH; /*!< (@ 0x00000791) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_H; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_HL; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_HH; /*!< (@ 0x00000793) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC1BR; /*!< (@ 0x00000794) Sequence Channel 0 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1CR; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_L; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_LL; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_H; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1CR_HL; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_HH; /*!< (@ 0x0000079B) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1DR; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_L; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_LL; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_LH; /*!< (@ 0x0000079D) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_H; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_HL; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_HH; /*!< (@ 0x0000079F) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2AR; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_L; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_LL; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_LH; /*!< (@ 0x000007A1) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_H; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_HL; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_HH; /*!< (@ 0x000007A3) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC2BR; /*!< (@ 0x000007A4) Sequence Channel 0 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2CR; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_L; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_LL; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_H; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2CR_HL; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_HH; /*!< (@ 0x000007AB) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2DR; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_L; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_LL; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_LH; /*!< (@ 0x000007AD) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_H; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_HL; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_HH; /*!< (@ 0x000007AF) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3AR; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_L; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_LL; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_LH; /*!< (@ 0x000007B1) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_H; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_HL; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_HH; /*!< (@ 0x000007B3) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC3BR; /*!< (@ 0x000007B4) Sequence Channel 0 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3CR; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_L; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_LL; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_H; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3CR_HL; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_HH; /*!< (@ 0x000007BB) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3DR; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_L; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_LL; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_LH; /*!< (@ 0x000007BD) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_H; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_HL; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_HH; /*!< (@ 0x000007BF) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4AR; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_L; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_LL; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_LH; /*!< (@ 0x000007C1) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_H; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_HL; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_HH; /*!< (@ 0x000007C3) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC4BR; /*!< (@ 0x000007C4) Sequence Channel 0 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4CR; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_L; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_LL; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_H; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4CR_HL; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_HH; /*!< (@ 0x000007CB) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4DR; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_L; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_LL; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_LH; /*!< (@ 0x000007CD) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_H; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_HL; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_HH; /*!< (@ 0x000007CF) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5AR; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_L; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_LL; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_LH; /*!< (@ 0x000007D1) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_H; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_HL; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_HH; /*!< (@ 0x000007D3) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC5BR; /*!< (@ 0x000007D4) Sequence Channel 0 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5CR; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_L; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_LL; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_H; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5CR_HL; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_HH; /*!< (@ 0x000007DB) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5DR; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_L; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_LL; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_LH; /*!< (@ 0x000007DD) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_H; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_HL; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_HH; /*!< (@ 0x000007DF) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6AR; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_L; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_LL; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_LH; /*!< (@ 0x000007E1) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_H; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_HL; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_HH; /*!< (@ 0x000007E3) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC6BR; /*!< (@ 0x000007E4) Sequence Channel 0 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6CR; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_L; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_LL; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_H; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6CR_HL; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_HH; /*!< (@ 0x000007EB) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6DR; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_L; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_LL; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_LH; /*!< (@ 0x000007ED) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_H; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_HL; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_HH; /*!< (@ 0x000007EF) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7AR; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_L; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_LL; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_LH; /*!< (@ 0x000007F1) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_H; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_HL; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_HH; /*!< (@ 0x000007F3) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC7BR; /*!< (@ 0x000007F4) Sequence Channel 0 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7CR; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_L; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_LL; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_H; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7CR_HL; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_HH; /*!< (@ 0x000007FB) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7DR; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_L; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_LL; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_LH; /*!< (@ 0x000007FD) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_H; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_HL; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_HH; /*!< (@ 0x000007FF) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0AR; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_L; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_LL; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_LH; /*!< (@ 0x00000801) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_H; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_HL; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_HH; /*!< (@ 0x00000803) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC0BR; /*!< (@ 0x00000804) Sequence Channel 1 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0CR; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_L; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_LL; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_H; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0CR_HL; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_HH; /*!< (@ 0x0000080B) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0DR; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0DR_L; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0DR_LL; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_LH; /*!< (@ 0x0000080D) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HL; /*!< (@ 0x0000080E) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HH; /*!< (@ 0x0000080F) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1AR; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_L; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_LL; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_LH; /*!< (@ 0x00000811) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_H; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_HL; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_HH; /*!< (@ 0x00000813) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC1BR; /*!< (@ 0x00000814) Sequence Channel 1 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1CR; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_L; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_LL; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_H; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1CR_HL; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_HH; /*!< (@ 0x0000081B) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1DR; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1DR_L; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1DR_LL; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_LH; /*!< (@ 0x0000081D) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HL; /*!< (@ 0x0000081E) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HH; /*!< (@ 0x0000081F) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2AR; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_L; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_LL; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_LH; /*!< (@ 0x00000821) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_H; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_HL; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_HH; /*!< (@ 0x00000823) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC2BR; /*!< (@ 0x00000824) Sequence Channel 1 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2CR; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_L; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_LL; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_H; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2CR_HL; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_HH; /*!< (@ 0x0000082B) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2DR; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2DR_L; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2DR_LL; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_LH; /*!< (@ 0x0000082D) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HL; /*!< (@ 0x0000082E) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HH; /*!< (@ 0x0000082F) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3AR; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_L; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_LL; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_LH; /*!< (@ 0x00000831) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_H; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_HL; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_HH; /*!< (@ 0x00000833) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC3BR; /*!< (@ 0x00000834) Sequence Channel 1 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3CR; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_L; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_LL; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_H; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3CR_HL; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_HH; /*!< (@ 0x0000083B) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3DR; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3DR_L; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3DR_LL; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_LH; /*!< (@ 0x0000083D) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HL; /*!< (@ 0x0000083E) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HH; /*!< (@ 0x0000083F) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4AR; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_L; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_LL; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_LH; /*!< (@ 0x00000841) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_H; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_HL; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_HH; /*!< (@ 0x00000843) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC4BR; /*!< (@ 0x00000844) Sequence Channel 1 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4CR; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_L; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_LL; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_H; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4CR_HL; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_HH; /*!< (@ 0x0000084B) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4DR; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4DR_L; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4DR_LL; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_LH; /*!< (@ 0x0000084D) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HL; /*!< (@ 0x0000084E) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HH; /*!< (@ 0x0000084F) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5AR; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_L; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_LL; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_LH; /*!< (@ 0x00000851) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_H; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_HL; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_HH; /*!< (@ 0x00000853) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC5BR; /*!< (@ 0x00000854) Sequence Channel 1 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5CR; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_L; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_LL; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_H; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5CR_HL; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_HH; /*!< (@ 0x0000085B) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5DR; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5DR_L; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5DR_LL; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_LH; /*!< (@ 0x0000085D) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HL; /*!< (@ 0x0000085E) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HH; /*!< (@ 0x0000085F) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6AR; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_L; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_LL; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_LH; /*!< (@ 0x00000861) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_H; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_HL; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_HH; /*!< (@ 0x00000863) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC6BR; /*!< (@ 0x00000864) Sequence Channel 1 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6CR; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_L; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_LL; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_H; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6CR_HL; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_HH; /*!< (@ 0x0000086B) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6DR; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6DR_L; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6DR_LL; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_LH; /*!< (@ 0x0000086D) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HL; /*!< (@ 0x0000086E) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HH; /*!< (@ 0x0000086F) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7AR; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_L; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_LL; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_LH; /*!< (@ 0x00000871) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_H; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_HL; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_HH; /*!< (@ 0x00000873) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC7BR; /*!< (@ 0x00000874) Sequence Channel 1 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7CR; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_L; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_LL; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_H; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7CR_HL; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_HH; /*!< (@ 0x0000087B) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7DR; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7DR_L; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7DR_LL; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_LH; /*!< (@ 0x0000087D) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HL; /*!< (@ 0x0000087E) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HH; /*!< (@ 0x0000087F) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HH_b; + }; + }; + }; +} R_MIPI_DSI_Type; /*!< Size = 2176 (0x880) */ + +/* =========================================================================================================================== */ +/* ================ R_MRMS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MRAM Control (R_MRMS) + */ + +typedef struct /*!< (@ 0x4013C000) R_MRMS Structure */ +{ + union + { + __IOM uint8_t MRCPFB; /*!< (@ 0x00000000) Code MRAM Pre-Fetch Buffer Enable Register */ + + struct + { + __IOM uint8_t MPFBEN : 1; /*!< [0..0] MRAM Pre-Fetch Buffer enable. */ + uint8_t : 7; + } MRCPFB_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t MRCFREQ; /*!< (@ 0x00000004) Code MRAM Frequency Notifications Register */ + + struct + { + __IOM uint32_t MRCMHZ : 10; /*!< [9..0] Setting the operating frequency in the order of MHz */ + uint32_t : 14; + __IOM uint32_t KEY : 8; /*!< [31..24] Key Code */ + } MRCFREQ_b; + }; + + union + { + __IOM uint32_t MREFREQ; /*!< (@ 0x00000008) Extra MRAM Frequency Notifications Register */ + + struct + { + __IOM uint32_t MREMHZ : 8; /*!< [7..0] Setting the operating frequency in the order of MHz */ + uint32_t : 16; + __IOM uint32_t KEY : 8; /*!< [31..24] Key Code */ + } MREFREQ_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint16_t MRCDECC; /*!< (@ 0x00000010) Code MRAM ECC Decoder Control Register */ + + struct + { + __IOM uint16_t DECDISC : 1; /*!< [0..0] MRC ECC Decoder disable */ + __IOM uint16_t ECCSELC : 1; /*!< [1..1] MRC ECC Data select */ + uint16_t : 6; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCDECC_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t MRCRAEINT; /*!< (@ 0x00000014) Code MRAM Read Access Error Interrupt Enable + * Register */ + + struct + { + __IOM uint8_t INTENBDC : 1; /*!< [0..0] MRC DEC error interrupt enable. */ + __IOM uint8_t INTENBTC : 1; /*!< [1..1] MRC TED error interrupt enable. */ + uint8_t : 6; + } MRCRAEINT_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t MRCRAES; /*!< (@ 0x00000018) Code MRAM Read Access Error Status Register */ + + struct + { + __IOM uint8_t DECERRC : 1; /*!< [0..0] MRC DEC error detected. */ + __IOM uint8_t TEDERRC : 1; /*!< [1..1] MRC TED error detected. */ + uint8_t : 6; + } MRCRAES_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IM uint32_t MRCRTEA; /*!< (@ 0x0000001C) Code MRAM TED Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MRCRTEA : 27; /*!< [31..5] MRC read access TED error Address. */ + } MRCRTEA_b; + }; + + union + { + __IM uint32_t MRCRDEA; /*!< (@ 0x00000020) Code MRAM DEC Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MRCRDEA : 27; /*!< [31..5] MRC read access DEC error Address. */ + } MRCRDEA_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint8_t MRERAINT; /*!< (@ 0x00000034) Extra MRAM Read Access Error Interrupt Enable + * Register */ + + struct + { + __IOM uint8_t INTENBDE : 1; /*!< [0..0] MRE DEC error interrupt enable. */ + __IOM uint8_t INTENBTE : 1; /*!< [1..1] MRE TED error interrupt enable. */ + uint8_t : 6; + } MRERAINT_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t MRERAES; /*!< (@ 0x00000038) Extra MRAM Read Access Error Status Register */ + + struct + { + __IOM uint8_t DECERRE : 1; /*!< [0..0] MRE DEC error detected. */ + __IOM uint8_t TEDERRE : 1; /*!< [1..1] MRE TED error detected. */ + uint8_t : 6; + } MRERAES_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t MRERTEA; /*!< (@ 0x0000003C) Extra MRAM TED Error Address Register */ + + struct + { + uint32_t : 4; + __IM uint32_t MRERTEA : 28; /*!< [31..4] MRE read access TED error Address. */ + } MRERTEA_b; + }; + + union + { + __IM uint32_t MRERDEA; /*!< (@ 0x00000040) Extra MRAM DEC Error Address Register */ + + struct + { + uint32_t : 4; + __IM uint32_t MRERDEA : 28; /*!< [31..4] MRE read access DEC error Address. */ + } MRERDEA_b; + }; + __IM uint32_t RESERVED13[47]; + + union + { + __IOM uint16_t MSAR; /*!< (@ 0x00000100) MRAM Security Attribution Register */ + + struct + { + __IOM uint16_t MREECCSA : 1; /*!< [0..0] Extra MRAM ECC Register Security Attribution */ + __IOM uint16_t MREFREQSA : 1; /*!< [1..1] MREFREQ register Security Attribution */ + __IOM uint16_t MRCECCSA : 1; /*!< [2..2] Code MRAM ECC Register Security Attribution */ + __IOM uint16_t MRCFREQSA : 1; /*!< [3..3] MRCFREQ register Security Attribution */ + __IOM uint16_t MPFBENSA : 1; /*!< [4..4] MRCPFB register Security Attribution */ + uint16_t : 4; + __IOM uint16_t MACICMISA : 1; /*!< [9..9] MACI Command Issuing Security Attribution */ + __IOM uint16_t MACICMRSA : 1; /*!< [10..10] MACI Command Registers Security Attribution */ + __IOM uint16_t MACITRSA : 1; /*!< [11..11] MACI Transfer Security Attribution */ + uint16_t : 1; + __IOM uint16_t MRCPSA : 1; /*!< [13..13] Code MRAM Program Register Security Attribution */ + __IOM uint16_t MREPSEQSA : 1; /*!< [14..14] EPSEQ Area Register Security Attribution */ + __IOM uint16_t MRCPSEQSA : 1; /*!< [15..15] CPSEQ Area Register Security Attribution */ + } MSAR_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[191]; + + union + { + __IM uint8_t MREZS; /*!< (@ 0x00000400) Extra MRAM Zeroization Status Register */ + + struct + { + __IM uint8_t WHUKZF : 1; /*!< [0..0] W-HUK Zero Flag Status. */ + __IM uint8_t WHUKEXE : 1; /*!< [1..1] W-HUK Zeroization Executing Status */ + uint8_t : 6; + } MREZS_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t MREZC; /*!< (@ 0x00000404) Extra MRAM Zeroization Control Register */ + + struct + { + __IOM uint16_t WHUKZE : 3; /*!< [2..0] W-KUK zeroization execute. */ + uint16_t : 5; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MREZC_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19[1794]; + + union + { + __IOM uint8_t MASTAT; /*!< (@ 0x00002010) Extra MRAM Access Status Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MREAE : 1; /*!< [3..3] Extra MRAM Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 3; + } MASTAT_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t MPAEINT; /*!< (@ 0x00002014) Extra MRAM Access Error Interrupt Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MREAEIE : 1; /*!< [3..3] MRE Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 3; + } MPAEINT_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t MRDYIE; /*!< (@ 0x00002018) Extra MRAM Ready Interrupt Enable Register */ + + struct + { + __IOM uint8_t MRDYIE : 1; /*!< [0..0] MRDY Interrupt Enable */ + uint8_t : 7; + } MRDYIE_b; + }; + __IM uint8_t RESERVED24; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[5]; + + union + { + __IOM uint32_t MSADDR; /*!< (@ 0x00002030) MACI Command Start Address Register */ + + struct + { + __IOM uint32_t MSADDR : 32; /*!< [31..0] Start Address for MACI Command Processing */ + } MSADDR_b; + }; + __IM uint32_t RESERVED27[5]; + + union + { + __IOM uint8_t MCNTSELR; /*!< (@ 0x00002048) MRAM Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } MCNTSELR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + + union + { + __IM uint32_t MCNTDTR0; /*!< (@ 0x0000204C) MRAM Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } MCNTDTR0_b; + }; + + union + { + __IM uint32_t MCNTDTR1; /*!< (@ 0x00002050) MRAM Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } MCNTDTR1_b; + }; + __IM uint32_t RESERVED30[3]; + + union + { + __IOM uint16_t MCTRCNTR; /*!< (@ 0x00002060) MRAM Configuration Update Transfer Control Register */ + + struct + { + __IOM uint16_t TRTRG : 1; /*!< [0..0] Transfer Start Trigger */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MCTRCNTR_b; + }; + __IM uint16_t RESERVED31; + + union + { + __IOM uint8_t MCTRLSR; /*!< (@ 0x00002064) MRAM Configuration Update Transfer List Select + * Register */ + + struct + { + __IOM uint8_t TRLIST : 3; /*!< [2..0] Configuration Update Transfer List */ + uint8_t : 5; + } MCTRLSR_b; + }; + __IM uint8_t RESERVED32; + __IM uint16_t RESERVED33; + __IM uint32_t RESERVED34; + + union + { + __IM uint8_t MCTRSTATR; /*!< (@ 0x0000206C) MRAM Configuration Update Transfer Status Register */ + + struct + { + __IM uint8_t TRBUSY : 1; /*!< [0..0] Transfer Busy Status */ + uint8_t : 1; + __IM uint8_t TRMD : 1; /*!< [2..2] Transfer Mode Setting Status */ + uint8_t : 5; + } MCTRSTATR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[4]; + + union + { + __IM uint32_t MSTATR; /*!< (@ 0x00002080) Extra MRAM Status Register */ + + struct + { + uint32_t : 5; + __IM uint32_t CFGSETERR : 1; /*!< [5..5] Configuration Set Error Flag */ + uint32_t : 6; + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + uint32_t : 1; + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Error */ + __IM uint32_t MRDY : 1; /*!< [15..15] MRE Ready */ + uint32_t : 3; + __IM uint32_t TZFERR : 1; /*!< [19..19] TrustZone Filter Error */ + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + uint32_t : 1; + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } MSTATR_b; + }; + + union + { + __IOM uint16_t MENTRYR; /*!< (@ 0x00002084) Extra MRAM Program Mode Entry Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t MENTRY : 1; /*!< [7..7] Extra MRAM Mode Entry */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MENTRYR_b; + }; + __IM uint16_t RESERVED38; + __IM uint32_t RESERVED39; + + union + { + __IOM uint16_t MSUINITR; /*!< (@ 0x0000208C) Extra MRAM Sequencer Set-Up Initialization Register */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MSUINITR_b; + }; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41[4]; + + union + { + __IM uint16_t MCMDR; /*!< (@ 0x000020A0) MACI Command Register */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Pre-command Flag */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Flag */ + } MCMDR_b; + }; + __IM uint16_t RESERVED42; + __IM uint32_t RESERVED43[14]; + + union + { + __IM uint32_t MSUASMON; /*!< (@ 0x000020DC) MRAM Start-Up Area Select Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programing to set the Start-Up Area + * Select setting */ + uint32_t : 13; + __IM uint32_t BTSIZE : 2; /*!< [30..29] Size of Start-Up area select for Boot Swap */ + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } MSUASMON_b; + }; + __IM uint32_t RESERVED44[2]; + + union + { + __IOM uint16_t MSUACR; /*!< (@ 0x000020E8) MRAM Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select */ + uint16_t : 6; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MSUACR_b; + }; + __IM uint16_t RESERVED45; + __IM uint32_t RESERVED46[453]; + + union + { + __IOM uint8_t MRPSC; /*!< (@ 0x00002800) MRAM Program Speed Control Register */ + + struct + { + __IOM uint8_t MHSPEN : 1; /*!< [0..0] MRAM high speed program mode enable. */ + uint8_t : 7; + } MRPSC_b; + }; + __IM uint8_t RESERVED47; + __IM uint16_t RESERVED48; + __IM uint32_t RESERVED49[511]; + + union + { + __IOM uint16_t MRCPC0; /*!< (@ 0x00003000) Code MRAM Program Control Register */ + + struct + { + __IOM uint16_t MRCPNEN : 1; /*!< [0..0] Code MRAM Program Enable for Non-secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCPC0_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint16_t MRCPC1; /*!< (@ 0x00003004) Code MRAM Program Control for Secure Register */ + + struct + { + __IOM uint16_t MRCPSEN : 1; /*!< [0..0] Code MRAM Program Enable for Secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCPC1_b; + }; + __IM uint16_t RESERVED51; + + union + { + __IOM uint16_t MRCBPROT0; /*!< (@ 0x00003008) Code MRAM Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Code MRAM Block Protection Cancel for Non-secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCBPROT0_b; + }; + __IM uint16_t RESERVED52; + + union + { + __IOM uint16_t MRCBPROT1; /*!< (@ 0x0000300C) Code MRAM Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Code MRAM Block Protection Cancel for Secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCBPROT1_b; + }; + __IM uint16_t RESERVED53; + + union + { + __IOM uint8_t MRCPS; /*!< (@ 0x00003010) Code MRAM Program Status Register */ + + struct + { + __IOM uint8_t PRGERRC : 1; /*!< [0..0] Programming Error */ + __IOM uint8_t ECCERRC : 1; /*!< [1..1] ECC Error */ + uint8_t : 3; + __IM uint8_t ABUFEMP : 1; /*!< [5..5] Address Buffer Empty */ + __IM uint8_t ABUFFULL : 1; /*!< [6..6] Address Buffer Full */ + __IM uint8_t PRGBSYC : 1; /*!< [7..7] Code MRAM Program Busy */ + } MRCPS_b; + }; + __IM uint8_t RESERVED54; + __IM uint16_t RESERVED55; + + union + { + __IOM uint8_t MRCPAEINT; /*!< (@ 0x00003014) Code MRAM Program Access Error Interrupt Enable + * Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t MRCAEIE : 1; /*!< [7..7] Code MRAM Program Access Error Interrupt Enable */ + } MRCPAEINT_b; + }; + __IM uint8_t RESERVED56; + __IM uint16_t RESERVED57; + + union + { + __IM uint32_t MRCPEA; /*!< (@ 0x00003018) Code MRAM Program Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MCPEA : 27; /*!< [31..5] Code MRAM Program Error Address */ + } MRCPEA_b; + }; + __IM uint32_t RESERVED58[5]; + + union + { + __IOM uint16_t MRCFLR; /*!< (@ 0x00003030) Code MRAM Flush Register */ + + struct + { + __IOM uint16_t MRCFL : 1; /*!< [0..0] Flush Write Data Buffer for code MRAM */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCFLR_b; + }; + __IM uint16_t RESERVED59; + __IM uint32_t RESERVED60[500]; + + union + { + __IOM uint16_t MRCEECC; /*!< (@ 0x00003804) Code MRAM ECC Encoder Control Register */ + + struct + { + __IOM uint16_t ECCBYPC : 1; /*!< [0..0] Code MRAM ECC encoder outputs bypass enable */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCEECC_b; + }; + __IM uint16_t RESERVED61; +} R_MRMS_Type; /*!< Size = 14344 (0x3808) */ + +/* =========================================================================================================================== */ +/* ================ R_NPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Neural Processing Unit (R_NPU) + */ + +typedef struct /*!< (@ 0x40140000) R_NPU Structure */ +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) ID register */ + + struct + { + __IM uint32_t version_status : 4; /*!< [3..0] This is the version of the product */ + __IM uint32_t version_minor : 4; /*!< [7..4] This is the n for the P-part of an RnPn release number */ + __IM uint32_t version_major : 4; /*!< [11..8] This is the n for the R-part of an RnPn release number */ + __IM uint32_t product_major : 4; /*!< [15..12] This is the X-part of the ML00X product number */ + __IM uint32_t arch_patch_rev : 4; /*!< [19..16] This is the patch number of the architecture version + * a.b */ + __IM uint32_t arch_minor_rev : 8; /*!< [27..20] This is the minor architecture version number, b in + * the architecture version a.b */ + __IM uint32_t arch_major_rev : 4; /*!< [31..28] This is the major architecture version number, a in + * the architecture version a.b */ + } ID_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000004) Register describes the current operating status + * of the NPU */ + + struct + { + __IM uint32_t state : 1; /*!< [0..0] NPU state; 0 = Stopped, 1 = Running */ + __IM uint32_t irq_raised : 1; /*!< [1..1] Raw IRQ status: 0 = IRQ not raised, 1 = IRQ raised. IRQ + * is cleared using command register bit 1. */ + __IM uint32_t bus_status : 1; /*!< [2..2] 0=OK, 1=Bus abort detected and processing halted (the + * NPU has reached IDLE state and does not start to process + * any more commands/AXI transactions). Can only be cleared + * by a reset. */ + __IM uint32_t reset_status : 1; /*!< [3..3] Reset is ongoing and only this register can be read (other + * registers read as 0 and writes are ignored). A value of + * 0 means the NPU is not being reset and can be accessed + * as normal. */ + __IM uint32_t cmd_parse_error : 1; /*!< [4..4] 0=No error, 1=Command-stream parsing error detected. + * Can only be cleared by a reset. */ + __IM uint32_t cmd_end_reached : 1; /*!< [5..5] 0=Not reached, 1=Reached. Cleared by writing QBASE or + * QSIZE when the NPU is in stopped state. */ + __IM uint32_t pmu_irq_raised : 1; /*!< [6..6] 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command + * register bit 1 */ + uint32_t : 1; + __IM uint32_t ecc_fault : 1; /*!< [8..8] ECC state for internal RAMs: 0=no fault, 1=ECC fault + * signalled. Can only be cleared by reset. */ + uint32_t : 2; + __IM uint32_t faulting_interface : 1; /*!< [11..11] Faulting interface on bus abort. 0=AXI-M0, 1=AXI-M1 */ + __IM uint32_t faulting_channel : 4; /*!< [15..12] Faulting channel on a bus abort. Read: 0=Cmd, 1=IFM, + * 2=Weights, 3=Scale+Bias, 4=Mem2Mem; Write: 8=OFM, 9=Mem2Mem */ + __IM uint32_t irq_history_mask : 16; /*!< [31..16] IRQ History mask */ + } STATUS_b; + }; + + union + { + __IOM uint32_t CMD; /*!< (@ 0x00000008) Command register, reads as last written command */ + + struct + { + __IOM uint32_t transition_to_running_state : 1; /*!< [0..0] Write 1 to transition the NPU to running state. Writing + * 0 has no effect */ + __IOM uint32_t clear_irq : 1; /*!< [1..1] Write 1 to clear the IRQ status in the STATUS register. + * Writing 0 has no effect */ + __IOM uint32_t clock_q_enable : 1; /*!< [2..2] Write 1 to this bit to enable clock off using the Clock + * Q-interface and enable the main clock gate */ + __IOM uint32_t power_q_enable : 1; /*!< [3..3] Write 1 to this bit to enable power off using the Power + * Q-interface */ + uint32_t : 12; + __IOM uint32_t clear_irq_history : 16; /*!< [31..16] Clears the IRQ history mask */ + } CMD_b; + }; + + union + { + __IOM uint32_t RESET; /*!< (@ 0x0000000C) Request Reset and new security mode */ + + struct + { + __IOM uint32_t pending_CPL : 1; /*!< [0..0] Current privilege level: 0=User, 1=Privileged */ + __IOM uint32_t pending_CSL : 1; /*!< [1..1] Current security level: 0=Secure, 1=Non secure */ + uint32_t : 30; + } RESET_b; + }; + + union + { + __IOM uint32_t QBASE0; /*!< (@ 0x00000010) Base address of Command-queue bits[31:0]. The + * address is 4-byte-aligned */ + + struct + { + __IOM uint32_t QBASE0 : 32; /*!< [31..0] The 4-byte-aligned lower bytes of the base address value + * for the command stream */ + } QBASE0_b; + }; + + union + { + __IOM uint32_t QBASE1; /*!< (@ 0x00000014) Address extension bits[47:32] for queue base */ + + struct + { + __IOM uint32_t QBASE1 : 32; /*!< [31..0] The 4-byte-aligned upper bytes of the base address value + * for the command stream */ + } QBASE1_b; + }; + + union + { + __IM uint32_t QREAD; /*!< (@ 0x00000018) Read offset in the command stream in bytes. Multiples + * of 4 in the range 0-16 MB */ + + struct + { + __IM uint32_t QREAD : 32; /*!< [31..0] The read offset of the current command under execution */ + } QREAD_b; + }; + + union + { + __IOM uint32_t QCONFIG; /*!< (@ 0x0000001C) AXI configuration for the command stream in the + * range 0-3. Same encoding as for REGIONCFG */ + + struct + { + __IOM uint32_t QCONFIG : 32; /*!< [31..0] AXI configuration for the command stream in the range + * 0-3 */ + } QCONFIG_b; + }; + + union + { + __IOM uint32_t QSIZE; /*!< (@ 0x00000020) Size of the command stream in bytes. Multiples + * of 4 in the range 0-16 MB */ + + struct + { + __IOM uint32_t QSIZE : 32; /*!< [31..0] Size of the next command stream to be executed by the + * NPU */ + } QSIZE_b; + }; + + union + { + __IM uint32_t PROT; /*!< (@ 0x00000024) Protection level configured for the NPU when + * acting as an AXI master */ + + struct + { + __IM uint32_t active_CPL : 1; /*!< [0..0] Current privilege level: 0=User, 1=Privileged */ + __IM uint32_t active_CSL : 1; /*!< [1..1] Current security level: 0=Secure, 1=Non-secure */ + uint32_t : 30; + } PROT_b; + }; + + union + { + __IM uint32_t CONFIG; /*!< (@ 0x00000028) RTL configuration */ + + struct + { + __IM uint32_t macs_per_cc : 4; /*!< [3..0] The log2(macs/clock cycle). Valid encoding range is 5-8 + * for 32-256 MACs/clock cycle. */ + __IM uint32_t cmd_stream_version : 4; /*!< [7..4] Command-stream version accepted by this NPU. */ + __IM uint32_t shram_size : 8; /*!< [15..8] Size in KB of SHRAM in the range 8-48. */ + uint32_t : 11; + __IM uint32_t custom_dma : 1; /*!< [27..27] Custom DMA configuration */ + __IM uint32_t product : 4; /*!< [31..28] Product configuration */ + } CONFIG_b; + }; + + union + { + __IOM uint32_t LOCK; /*!< (@ 0x0000002C) Lock register. This register is designed for + * driver use and does not affect NPU functionality */ + + struct + { + __IOM uint32_t LOCK : 32; /*!< [31..0] 32-bit value for the LOCK configuration */ + } LOCK_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t REGIONCFG; /*!< (@ 0x0000003C) Base pointer configuration. Bits[2*k+1:2*k] give + * the memory type for REGION[k] */ + + struct + { + __IOM uint32_t region0 : 2; /*!< [1..0] Bits for the Region0 configuration */ + __IOM uint32_t region1 : 2; /*!< [3..2] Bits for the Region1 configuration */ + __IOM uint32_t region2 : 2; /*!< [5..4] Bits for the Region2 configuration */ + __IOM uint32_t region3 : 2; /*!< [7..6] Bits for the Region3 configuration */ + __IOM uint32_t region4 : 2; /*!< [9..8] Bits for the Region4 configuration */ + __IOM uint32_t region5 : 2; /*!< [11..10] Bits for the Region5 configuration */ + __IOM uint32_t region6 : 2; /*!< [13..12] Bits for the Region6 configuration */ + __IOM uint32_t region7 : 2; /*!< [15..14] Bits for the Region7 configuration */ + uint32_t : 16; + } REGIONCFG_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT0; /*!< (@ 0x00000040) AXI limits for port 0 counter 0 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT0_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT1; /*!< (@ 0x00000044) AXI limits for port 0 counter 1 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT1_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT2; /*!< (@ 0x00000048) AXI limits for port 1 counter 2 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT2_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT3; /*!< (@ 0x0000004C) AXI limits for port 1 counter 3 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT3_b; + }; + __IM uint32_t RESERVED1[12]; + + union + { + __IOM uint32_t BASEP0; /*!< (@ 0x00000080) Lower 32 bits of the Base pointer for region + * index 0 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP0_b; + }; + + union + { + __IOM uint32_t BASEP1; /*!< (@ 0x00000084) Upper 32 bits of the Base pointer for region + * index 0 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP1_b; + }; + + union + { + __IOM uint32_t BASEP2; /*!< (@ 0x00000088) Lower 32 bits of the Base pointer for region + * index 1 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP2_b; + }; + + union + { + __IOM uint32_t BASEP3; /*!< (@ 0x0000008C) Upper 32 bits of the Base pointer for region + * index 1 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP3_b; + }; + + union + { + __IOM uint32_t BASEP4; /*!< (@ 0x00000090) Lower 32 bits of the Base pointer for region + * index 2 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP4_b; + }; + + union + { + __IOM uint32_t BASEP5; /*!< (@ 0x00000094) Upper 32 bits of the Base pointer for region + * index 2 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP5_b; + }; + + union + { + __IOM uint32_t BASEP6; /*!< (@ 0x00000098) Lower 32 bits of the Base pointer for region + * index 3 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP6_b; + }; + + union + { + __IOM uint32_t BASEP7; /*!< (@ 0x0000009C) Upper 32 bits of the Base pointer for region + * index 3 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP7_b; + }; + + union + { + __IOM uint32_t BASEP8; /*!< (@ 0x000000A0) Lower 32 bits of the Base pointer for region + * index 4 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP8_b; + }; + + union + { + __IOM uint32_t BASEP9; /*!< (@ 0x000000A4) Upper 32 bits of the Base pointer for region + * index 4 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP9_b; + }; + + union + { + __IOM uint32_t BASEP10; /*!< (@ 0x000000A8) Lower 32 bits of the Base pointer for region + * index 5 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP10_b; + }; + + union + { + __IOM uint32_t BASEP11; /*!< (@ 0x000000AC) Upper 32 bits of the Base pointer for region + * index 5 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP11_b; + }; + + union + { + __IOM uint32_t BASEP12; /*!< (@ 0x000000B0) Lower 32 bits of the Base pointer for region + * index 6 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP12_b; + }; + + union + { + __IOM uint32_t BASEP13; /*!< (@ 0x000000B4) Upper 32 bits of the Base pointer for region + * index 6 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP13_b; + }; + + union + { + __IOM uint32_t BASEP14; /*!< (@ 0x000000B8) Lower 32 bits of the Base pointer for region + * index 7 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP14_b; + }; + + union + { + __IOM uint32_t BASEP15; /*!< (@ 0x000000BC) Upper 32 bits of the Base pointer for region + * index 7 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP15_b; + }; + __IM uint32_t RESERVED2[48]; + + union + { + __IOM uint32_t PMCR; /*!< (@ 0x00000180) PMU master control register */ + + struct + { + __IOM uint32_t cnt_en : 1; /*!< [0..0] Enable counter */ + __IOM uint32_t event_cnt_rst : 1; /*!< [1..1] Reset event counter */ + __IOM uint32_t cycle_cnt_rst : 1; /*!< [2..2] Reset cycle counter */ + __IOM uint32_t mask_en : 1; /*!< [3..3] PMU can be enabled/disabled by command stream operationNPU_OP_PMU_MASK */ + uint32_t : 7; + __IOM uint32_t num_event_cnt : 5; /*!< [15..11] Number of event counters available for performance + * measurement */ + uint32_t : 16; + } PMCR_b; + }; + + union + { + __IOM uint32_t PMCNTENSET; /*!< (@ 0x00000184) Count-enable set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0 : 1; /*!< [0..0] Event-counter enable bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1 : 1; /*!< [1..1] Event-counter enable bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2 : 1; /*!< [2..2] Event-counter enable bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3 : 1; /*!< [3..3] Event-counter enable bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT : 1; /*!< [31..31] PMCCNTR enable bit */ + } PMCNTENSET_b; + }; + + union + { + __IOM uint32_t PMCNTENCLR; /*!< (@ 0x00000188) Count-enable clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0 : 1; /*!< [0..0] Event-counter disable bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1 : 1; /*!< [1..1] Event-counter disable bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2 : 1; /*!< [2..2] Event-counter disable bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3 : 1; /*!< [3..3] Event-counter disable bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT : 1; /*!< [31..31] PMCCNTR disable bit */ + } PMCNTENCLR_b; + }; + + union + { + __IOM uint32_t PMOVSSET; /*!< (@ 0x0000018C) Overflow-flag status set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_OVF : 1; /*!< [0..0] Event-counter overflow set bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_OVF : 1; /*!< [1..1] Event-counter overflow set bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_OVF : 1; /*!< [2..2] Event-counter overflow set bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_OVF : 1; /*!< [3..3] Event-counter overflow set bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_OVF : 1; /*!< [31..31] PMCCNTR overflow set bit */ + } PMOVSSET_b; + }; + + union + { + __IOM uint32_t PMOVSCLR; /*!< (@ 0x00000190) Overflow-flag status clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_OVF : 1; /*!< [0..0] Event-counter overflow clear bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_OVF : 1; /*!< [1..1] Event-counter overflow clear bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_OVF : 1; /*!< [2..2] Event-counter overflow clear bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_OVF : 1; /*!< [3..3] Event-counter overflow clear bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_OVF : 1; /*!< [31..31] PMCCNTR overflow clear bit */ + } PMOVSCLR_b; + }; + + union + { + __IOM uint32_t PMINTSET; /*!< (@ 0x00000194) Interrupt-enable set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_INT : 1; /*!< [0..0] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_INT : 1; /*!< [1..1] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_INT : 1; /*!< [2..2] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_INT : 1; /*!< [3..3] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_INT : 1; /*!< [31..31] PMCCNTR overflow interrupt-request enable bit */ + } PMINTSET_b; + }; + + union + { + __IOM uint32_t PMINTCLR; /*!< (@ 0x00000198) Interrupt-enable clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_INT : 1; /*!< [0..0] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_INT : 1; /*!< [1..1] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_INT : 1; /*!< [2..2] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_INT : 1; /*!< [3..3] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_INT : 1; /*!< [31..31] PMCCNTR overflow interrupt-request disable bit */ + } PMINTCLR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PMCCNTR_LO; /*!< (@ 0x000001A0) Performance-monitor cycle count low register */ + + struct + { + __IOM uint32_t CYCLE_CNT_LO : 32; /*!< [31..0] Cycle count low */ + } PMCCNTR_LO_b; + }; + + union + { + __IOM uint32_t PMCCNTR_HI; /*!< (@ 0x000001A4) Performance-monitor cycle count high register */ + + struct + { + __IOM uint32_t CYCLE_CNT_HI : 32; /*!< [31..0] Cycle count high */ + } PMCCNTR_HI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t PMCAXI_CHAN; /*!< (@ 0x000001AC) Set which AXI channel monitor */ + + struct + { + __IOM uint32_t CH_SEL : 4; /*!< [3..0] Specify the type of traffic for bandwidth or latency + * measurements (Read: 0=command traffic, 1=IFM traffic, 2=Weight + * traffic, 3=Scale+Bias, 4=Mem2Mem traffic - read direction; + * Write: 8=OFM traffic, 9=Mem2Mem traffic - write direction) */ + uint32_t : 4; + __IOM uint32_t AXI_CNT_SEL : 2; /*!< [9..8] Select AXI counter to monitor for latency measurements + * (0=AXI0 counter0, 1=AXI0 counter1, 2=AXI1 counter 2, 3=AXI1 + * counter3) */ + __IOM uint32_t BW_CH_SEL_EN : 1; /*!< [10..10] Enable bandwidth channel selector: 0=AXI bw events + * measured for all channels, 1=AXI bw events measured for + * channel specified by CH_SEL */ + uint32_t : 21; + } PMCAXI_CHAN_b; + }; + __IM uint32_t RESERVED5[84]; + + union + { + __IOM uint32_t PMU_EVCNTR0; /*!< (@ 0x00000300) Performance-monitor event counters 0 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR0_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR1; /*!< (@ 0x00000304) Performance-monitor event counters 1 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR1_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR2; /*!< (@ 0x00000308) Performance-monitor event counters 2 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR2_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR3; /*!< (@ 0x0000030C) Performance-monitor event counters 3 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR3_b; + }; + __IM uint32_t RESERVED6[28]; + + union + { + __IOM uint32_t PMU_EVTYPER0; /*!< (@ 0x00000380) Performance-monitor event-type control counters + * 0 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER0_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER1; /*!< (@ 0x00000384) Performance-monitor event-type control counters + * 1 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER1_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER2; /*!< (@ 0x00000388) Performance-monitor event-type control counters + * 2 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER2_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER3; /*!< (@ 0x0000038C) Performance-monitor event-type control counters + * 3 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER3_b; + }; + __IM uint32_t RESERVED7[784]; + + union + { + __IM uint32_t PID4; /*!< (@ 0x00000FD0) Peripheral ID byte 4 (Arm=code 4) */ + + struct + { + __IM uint32_t PID4 : 32; /*!< [31..0] Byte 4 of the Peripheral ID (Lower 8 bits valid) */ + } PID4_b; + }; + + union + { + __IM uint32_t PID5; /*!< (@ 0x00000FD4) Peripheral ID byte 5 (reserved) */ + + struct + { + __IM uint32_t PID5 : 32; /*!< [31..0] Byte 5 of the Peripheral ID (Lower 8 bits valid) */ + } PID5_b; + }; + + union + { + __IM uint32_t PID6; /*!< (@ 0x00000FD8) Peripheral ID byte 6 (reserved) */ + + struct + { + __IM uint32_t PID6 : 32; /*!< [31..0] Byte 6 of the Peripheral ID (Lower 8 bits valid) */ + } PID6_b; + }; + + union + { + __IM uint32_t PID7; /*!< (@ 0x00000FDC) Peripheral ID byte 7 (reserved) */ + + struct + { + __IM uint32_t PID7 : 32; /*!< [31..0] Byte 7 of the Peripheral ID (Lower 8 bits valid) */ + } PID7_b; + }; + + union + { + __IM uint32_t PID0; /*!< (@ 0x00000FE0) Peripheral ID byte 0. This is bits[7:0] of the + * part number. */ + + struct + { + __IM uint32_t PID0 : 32; /*!< [31..0] Byte 0 of the Peripheral ID (Lower 8 bits valid) */ + } PID0_b; + }; + + union + { + __IM uint32_t PID1; /*!< (@ 0x00000FE4) Peripheral ID byte 1. This is bits[11:8] of the + * part number in bits[3:0], and bits[3:0] + * of the Arm ID in bits[7:4]. */ + + struct + { + __IM uint32_t PID1 : 32; /*!< [31..0] Byte 1 of the Peripheral ID (Lower 8 bits valid) */ + } PID1_b; + }; + + union + { + __IM uint32_t PID2; /*!< (@ 0x00000FE8) Peripheral ID byte 2. This is bits[6:4] of the + * Arm ID in bits[2:0], and bit 3 indicates + * format B. */ + + struct + { + __IM uint32_t PID2 : 32; /*!< [31..0] Byte 2 of the Peripheral ID (Lower 8 bits valid) */ + } PID2_b; + }; + + union + { + __IM uint32_t PID3; /*!< (@ 0x00000FEC) Peripheral ID byte 3. */ + + struct + { + __IM uint32_t PID3 : 32; /*!< [31..0] Byte 3 of the Peripheral ID (Lower 8 bits valid) */ + } PID3_b; + }; + + union + { + __IM uint32_t CID0; /*!< (@ 0x00000FF0) Component ID byte 0. */ + + struct + { + __IM uint32_t CID0 : 32; /*!< [31..0] Byte 0 of the Component ID (Lower 8 bits valid) */ + } CID0_b; + }; + + union + { + __IM uint32_t CID1; /*!< (@ 0x00000FF4) Component ID byte 1. */ + + struct + { + __IM uint32_t CID1 : 32; /*!< [31..0] Byte 1 of the Component ID (Lower 8 bits valid) */ + } CID1_b; + }; + + union + { + __IM uint32_t CID2; /*!< (@ 0x00000FF8) Component ID byte 2. */ + + struct + { + __IM uint32_t CID2 : 32; /*!< [31..0] Byte 2 of the Component ID (Lower 8 bits valid) */ + } CID2_b; + }; + + union + { + __IM uint32_t CID3; /*!< (@ 0x00000FFC) Component ID byte 3. */ + + struct + { + __IM uint32_t CID3 : 32; /*!< [31..0] Byte 3 of the Component ID (Lower 8 bits valid) */ + } CID3_b; + }; +} R_NPU_Type; /*!< Size = 4096 (0x1000) */ + +/* =========================================================================================================================== */ +/* ================ R_PDM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Pulse Density Modulator Interface (R_PDM) + */ + +typedef struct /*!< (@ 0x40256000) R_PDM Structure */ +{ + union + { + __OM uint32_t PDCSTRTR; /*!< (@ 0x00000000) Channel Software Start Trigger Register */ + + struct + { + __OM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger */ + __OM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger */ + __OM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger */ + uint32_t : 29; + } PDCSTRTR_b; + }; + + union + { + __OM uint32_t PDCSTPTR; /*!< (@ 0x00000004) Channel Software Stop Trigger Register */ + + struct + { + __OM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger */ + __OM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger */ + __OM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger */ + uint32_t : 29; + } PDCSTPTR_b; + }; + + union + { + __OM uint32_t PDCCHGTR; /*!< (@ 0x00000008) Channel Software Change Trigger Register */ + + struct + { + __OM uint32_t CHGTRG0 : 1; /*!< [0..0] Channel 0 change trigger */ + __OM uint32_t CHGTRG1 : 1; /*!< [1..1] Channel 1 change trigger */ + __OM uint32_t CHGTRG2 : 1; /*!< [2..2] Channel 2 change trigger */ + uint32_t : 29; + } PDCCHGTR_b; + }; + + union + { + __IOM uint32_t PDCICR; /*!< (@ 0x0000000C) Channel Interrupt Control Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t ISDE0 : 1; /*!< [8..8] Channel 0 sound detection interrupt enable bit */ + __IOM uint32_t ISDE1 : 1; /*!< [9..9] Channel 1 sound detection interrupt enable bit */ + __IOM uint32_t ISDE2 : 1; /*!< [10..10] Channel 2 sound detection interrupt enable bit */ + uint32_t : 5; + __IOM uint32_t IDRE0 : 1; /*!< [16..16] Channel 0 data reception interrupt enable bit */ + __IOM uint32_t IDRE1 : 1; /*!< [17..17] Channel 1 data reception interrupt enable bit */ + __IOM uint32_t IDRE2 : 1; /*!< [18..18] Channel 2 data reception interrupt enable bit */ + uint32_t : 5; + __IOM uint32_t IEDE0 : 1; /*!< [24..24] Channel 0 error detection interrupt enable bit */ + __IOM uint32_t IEDE1 : 1; /*!< [25..25] Channel 1 error detection interrupt enable bit */ + __IOM uint32_t IEDE2 : 1; /*!< [26..26] Channel 2 error detection interrupt enable bit */ + uint32_t : 5; + } PDCICR_b; + }; + + union + { + __IM uint32_t PDCSR; /*!< (@ 0x00000010) Channel Status Register */ + + struct + { + __IM uint32_t STATE0 : 1; /*!< [0..0] Channel 0 state */ + __IM uint32_t STATE1 : 1; /*!< [1..1] Channel 1 state */ + __IM uint32_t STATE2 : 1; /*!< [2..2] Channel 2 state */ + uint32_t : 5; + __IM uint32_t SDF0 : 1; /*!< [8..8] Channel 0 sound detection flag */ + __IM uint32_t SDF1 : 1; /*!< [9..9] Channel 1 sound detection flag */ + __IM uint32_t SDF2 : 1; /*!< [10..10] Channel 2 sound detection flag */ + uint32_t : 5; + __IM uint32_t DRF0 : 1; /*!< [16..16] Channel 0 data reception flag */ + __IM uint32_t DRF1 : 1; /*!< [17..17] Channel 1 data reception flag */ + __IM uint32_t DRF2 : 1; /*!< [18..18] Channel 2 data reception flag */ + uint32_t : 5; + __IM uint32_t EDF0 : 1; /*!< [24..24] Channel 0 error detection flag */ + __IM uint32_t EDF1 : 1; /*!< [25..25] Channel 1 error detection flag */ + __IM uint32_t EDF2 : 1; /*!< [26..26] Channel 2 error detection flag */ + uint32_t : 5; + } PDCSR_b; + }; + + union + { + __OM uint32_t PDCSCR; /*!< (@ 0x00000014) Channel Status Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t SDFC0 : 1; /*!< [8..8] Channel 0 sound detection flag clear */ + __OM uint32_t SDFC1 : 1; /*!< [9..9] Channel 1 sound detection flag clear */ + __OM uint32_t SDFC2 : 1; /*!< [10..10] Channel 2 sound detection flag clear */ + uint32_t : 21; + } PDCSCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t PDCSDCR; /*!< (@ 0x00000020) Channel Sound Detection Control Register */ + + struct + { + __IOM uint32_t SDE0 : 1; /*!< [0..0] Channel 0 sound detection enable bit */ + __IOM uint32_t SDE1 : 1; /*!< [1..1] Channel 1 sound detection enable bit */ + __IOM uint32_t SDE2 : 1; /*!< [2..2] Channel 2 sound detection enable bit */ + uint32_t : 29; + } PDCSDCR_b; + }; + + union + { + __IOM uint32_t PDCDRCR; /*!< (@ 0x00000024) Channel Data Read Control Register */ + + struct + { + __IOM uint32_t DATRE0 : 1; /*!< [0..0] Channel 0 data read enable bit */ + __IOM uint32_t DATRE1 : 1; /*!< [1..1] Channel 1 data read enable bit */ + __IOM uint32_t DATRE2 : 1; /*!< [2..2] Channel 2 data read enable bit */ + uint32_t : 29; + } PDCDRCR_b; + }; + + union + { + __OM uint32_t PDCDCR; /*!< (@ 0x00000028) Channel Data Clear Register */ + + struct + { + __OM uint32_t DATC0 : 1; /*!< [0..0] Channel 0 data clear */ + __OM uint32_t DATC1 : 1; /*!< [1..1] Channel 1 data clear */ + __OM uint32_t DATC2 : 1; /*!< [2..2] Channel 2 data clear */ + uint32_t : 29; + } PDCDCR_b; + }; + __IM uint32_t RESERVED1[21]; + + union + { + __IM uint32_t PDVR; /*!< (@ 0x00000080) Version Register */ + + struct + { + __IM uint32_t VER : 12; /*!< [11..0] Version */ + uint32_t : 20; + } PDVR_b; + }; + __IM uint32_t RESERVED2[31]; + __IOM R_PDM_CH_Type CH[3]; /*!< (@ 0x00000100) PDM Channel-Specific Registers */ +} R_PDM_Type; /*!< Size = 1024 (0x400) */ + +/* =========================================================================================================================== */ +/* ================ R_RMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC (R_RMAC0) + */ + +typedef struct /*!< (@ 0x403CB000) R_RMAC0 Structure */ +{ + union + { + __IOM uint32_t MPSM; /*!< (@ 0x00000000) MAC PHY Station Management Register (MPSM) */ + + struct + { + __IOM uint32_t PSME : 1; /*!< [0..0] PSME */ + uint32_t : 1; + __IOM uint32_t MFF : 1; /*!< [2..2] MFF */ + __IOM uint32_t PDA : 5; /*!< [7..3] PDA */ + __IOM uint32_t PRA : 5; /*!< [12..8] PRA */ + __IOM uint32_t POP : 2; /*!< [14..13] POP */ + uint32_t : 1; + __IOM uint32_t PRD : 16; /*!< [31..16] PRD */ + } MPSM_b; + }; + + union + { + __IOM uint32_t MPIC; /*!< (@ 0x00000004) MAC PHY Interfaces Configuration Register (MPIC) */ + + struct + { + __IOM uint32_t PIS : 3; /*!< [2..0] PIS */ + __IOM uint32_t LSC : 3; /*!< [5..3] LSC */ + uint32_t : 2; + __IOM uint32_t PIP : 1; /*!< [8..8] PIP */ + __IOM uint32_t PIPP : 1; /*!< [9..9] PIPP */ + __IOM uint32_t PLSPP : 1; /*!< [10..10] PLSPP */ + uint32_t : 5; + __IOM uint32_t PSMCS : 7; /*!< [22..16] PSMCS */ + __IOM uint32_t PSMDP : 1; /*!< [23..23] PSMDP */ + __IOM uint32_t PSMHT : 3; /*!< [26..24] PSMHT */ + uint32_t : 1; + __IOM uint32_t PSMCT : 3; /*!< [30..28] PSMCT */ + uint32_t : 1; + } MPIC_b; + }; + + union + { + __IOM uint32_t MPIM; /*!< (@ 0x00000008) MAC PHY Interfaces Monitoring Register (MPIM) */ + + struct + { + __IOM uint32_t PLS : 1; /*!< [0..0] PLS */ + __IOM uint32_t LPIA : 1; /*!< [1..1] LPIA */ + uint32_t : 30; + } MPIM_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t MIOC; /*!< (@ 0x00000010) RMAC IO Configuration Registers Register (MIOC) */ + + struct + { + __IOM uint32_t MIOC : 32; /*!< [31..0] MIOC */ + } MIOC_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t MTFFC; /*!< (@ 0x00000020) MAC Transmission Frame Format Configuration Register + * (MTFFC) */ + + struct + { + __IOM uint32_t DPAD : 1; /*!< [0..0] DPAD */ + __IOM uint32_t FCM : 1; /*!< [1..1] FCM */ + uint32_t : 30; + } MTFFC_b; + }; + + union + { + __IOM uint32_t MTPFC; /*!< (@ 0x00000024) MAC Transmission Pause or PFC Frame Configuration + * Register (MTPFC) */ + + struct + { + __IOM uint32_t PT : 16; /*!< [15..0] PT */ + __IOM uint32_t PFRT : 8; /*!< [23..16] PFRT */ + uint32_t : 2; + __IOM uint32_t PFM : 1; /*!< [26..26] PFM */ + __IOM uint32_t PFRLV : 5; /*!< [31..27] PFRLV */ + } MTPFC_b; + }; + + union + { + __IOM uint32_t MTPFC2; /*!< (@ 0x00000028) MAC Transmission Pause or PFC Frame configuration2 + * Register (MTPFC2) */ + + struct + { + __IOM uint32_t PFCTTZ : 2; /*!< [1..0] PFCTTZ */ + uint32_t : 6; + __IOM uint32_t MPFCFR0 : 1; /*!< [8..8] MPFCFR0 */ + __IOM uint32_t MPFCFR1 : 1; /*!< [9..9] MPFCFR1 */ + uint32_t : 6; + __IOM uint32_t PFTTZ : 1; /*!< [16..16] PFTTZ */ + __IOM uint32_t MPFR : 1; /*!< [17..17] MPFR */ + uint32_t : 14; + } MTPFC2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MTPFC30; /*!< (@ 0x00000030) MAC Transmission Pause or PFC Frame Configuration + * Register 3 (MTPFC3t) (t = 0, 1) */ + + struct + { + __IOM uint32_t PFCPG : 8; /*!< [7..0] PFCPG */ + uint32_t : 24; + } MTPFC30_b; + }; + + union + { + __IOM uint32_t MTPFC31; /*!< (@ 0x00000034) MAC Transmission Pause or PFC Frame Configuration + * Register 3 (MTPFC3t) (t = 0, 1) */ + + struct + { + __IOM uint32_t PFCPG : 8; /*!< [7..0] PFCPG */ + uint32_t : 24; + } MTPFC31_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t MTATC0; /*!< (@ 0x00000050) MAC Transmission Automatic Timestamp Configuration + * Register (MTATCt) (t = 0, 1) */ + + struct + { + __IOM uint32_t TRTP : 8; /*!< [7..0] TRTP */ + __IOM uint32_t TRTL : 3; /*!< [10..8] TRTL */ + uint32_t : 21; + } MTATC0_b; + }; + + union + { + __IOM uint32_t MTATC1; /*!< (@ 0x00000054) MAC Transmission Automatic Timestamp Configuration + * Register (MTATCt) (t = 0, 1) */ + + struct + { + __IOM uint32_t TRTP : 8; /*!< [7..0] TRTP */ + __IOM uint32_t TRTL : 3; /*!< [10..8] TRTL */ + uint32_t : 21; + } MTATC1_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t MTIM; /*!< (@ 0x00000060) MAC Transmission Interfaces Monitoring Register + * (MTIM) */ + + struct + { + __IOM uint32_t TS : 1; /*!< [0..0] TS */ + uint32_t : 31; + } MTIM_b; + }; + __IM uint32_t RESERVED5[7]; + + union + { + __IOM uint32_t MRGC; /*!< (@ 0x00000080) MAC Reception General Configuration Register + * (MRGC) */ + + struct + { + __IOM uint32_t RCPT : 1; /*!< [0..0] RCPT */ + __IOM uint32_t PFRC : 1; /*!< [1..1] PFRC */ + __IOM uint32_t PFRTZ : 1; /*!< [2..2] PFRTZ */ + __IOM uint32_t MPDE : 1; /*!< [3..3] MPDE */ + __IOM uint32_t RFCFE : 1; /*!< [4..4] RFCFE */ + uint32_t : 11; + __IOM uint32_t PFCRC : 8; /*!< [23..16] PFCRC */ + uint32_t : 8; + } MRGC_b; + }; + + union + { + __IOM uint32_t MRMAC0; /*!< (@ 0x00000084) MAC Reception MAC Address Configuration Register + * 0 (MRMAC0) */ + + struct + { + __IOM uint32_t MAU : 16; /*!< [15..0] MAU */ + uint32_t : 16; + } MRMAC0_b; + }; + + union + { + __IOM uint32_t MRMAC1; /*!< (@ 0x00000088) MAC Reception MAC Address Configuration Register + * 1 (MRMAC1) */ + + struct + { + __IOM uint32_t MAL : 32; /*!< [31..0] MAL */ + } MRMAC1_b; + }; + + union + { + __IOM uint32_t MRAFC; /*!< (@ 0x0000008C) MAC Reception Address Filter Configuration Register + * (MRAFC) */ + + struct + { + __IOM uint32_t UCENE : 1; /*!< [0..0] UCENE */ + __IOM uint32_t MCENE : 1; /*!< [1..1] MCENE */ + __IOM uint32_t BCENE : 1; /*!< [2..2] BCENE */ + __IOM uint32_t MSTENE : 1; /*!< [3..3] MSTENE */ + __IOM uint32_t BSTENE : 1; /*!< [4..4] BSTENE */ + __IOM uint32_t MCACE : 1; /*!< [5..5] MCACE */ + __IOM uint32_t BCACE : 1; /*!< [6..6] BCACE */ + __IOM uint32_t NDAREE : 1; /*!< [7..7] NDAREE */ + __IOM uint32_t SDSFREE : 1; /*!< [8..8] SDSFREE */ + __IOM uint32_t NSAREE : 1; /*!< [9..9] NSAREE */ + __IOM uint32_t MSAREE : 1; /*!< [10..10] MSAREE */ + uint32_t : 5; + __IOM uint32_t UCENP : 1; /*!< [16..16] UCENP */ + __IOM uint32_t MCENP : 1; /*!< [17..17] MCENP */ + __IOM uint32_t BCENP : 1; /*!< [18..18] BCENP */ + __IOM uint32_t MSTENP : 1; /*!< [19..19] MSTENP */ + __IOM uint32_t BSTENP : 1; /*!< [20..20] BSTENP */ + __IOM uint32_t MCACP : 1; /*!< [21..21] MCACP */ + __IOM uint32_t BCACP : 1; /*!< [22..22] BCACP */ + __IOM uint32_t NDAREP : 1; /*!< [23..23] NDAREP */ + __IOM uint32_t SDSFREP : 1; /*!< [24..24] SDSFREP */ + __IOM uint32_t NSAREP : 1; /*!< [25..25] NSAREP */ + __IOM uint32_t MSAREP : 1; /*!< [26..26] MSAREP */ + uint32_t : 5; + } MRAFC_b; + }; + + union + { + __IOM uint32_t MRSCE; /*!< (@ 0x00000090) MAC Reception Storm Configuration for e-Frames + * Register (MRSCE) */ + + struct + { + __IOM uint32_t CMFE : 16; /*!< [15..0] CMFE */ + __IOM uint32_t CBFE : 16; /*!< [31..16] CBFE */ + } MRSCE_b; + }; + + union + { + __IOM uint32_t MRSCP; /*!< (@ 0x00000094) MAC Reception Storm Configuration for p-Frames + * Register (MRSCP) */ + + struct + { + __IOM uint32_t CMFP : 16; /*!< [15..0] CMFP */ + __IOM uint32_t CBFP : 16; /*!< [31..16] CBFP */ + } MRSCP_b; + }; + + union + { + __IOM uint32_t MRSCC; /*!< (@ 0x00000098) MAC Reception Storm Counter Configuration Register + * (MRSCC) */ + + struct + { + __IOM uint32_t MSCCE : 1; /*!< [0..0] MSCCE */ + __IOM uint32_t BSCCE : 1; /*!< [1..1] BSCCE */ + uint32_t : 14; + __IOM uint32_t MSCCP : 1; /*!< [16..16] MSCCP */ + __IOM uint32_t BSCCP : 1; /*!< [17..17] BSCCP */ + uint32_t : 14; + } MRSCC_b; + }; + + union + { + __IOM uint32_t MRFSCE; /*!< (@ 0x0000009C) MAC Reception Frame Size Configuration for e-Frames + * Register (MRFSCE) */ + + struct + { + __IOM uint32_t EMXS : 16; /*!< [15..0] EMXS */ + __IOM uint32_t EMNS : 16; /*!< [31..16] EMNS */ + } MRFSCE_b; + }; + + union + { + __IOM uint32_t MRFSCP; /*!< (@ 0x000000A0) MAC Reception Frame Size Configuration for p-Frames + * Register (MRFSCP) */ + + struct + { + __IOM uint32_t PMXS : 16; /*!< [15..0] PMXS */ + __IOM uint32_t PMNS : 16; /*!< [31..16] PMNS */ + } MRFSCP_b; + }; + + union + { + __IOM uint32_t MTRC; /*!< (@ 0x000000A4) MAC Timestamp Reception Configuration Register + * (MTRC) */ + + struct + { + __IOM uint32_t TRHFME0 : 1; /*!< [0..0] TRHFME0 */ + __IOM uint32_t TRHFME1 : 1; /*!< [1..1] TRHFME1 */ + uint32_t : 22; + __IOM uint32_t TRDDE : 1; /*!< [24..24] TRDDE */ + __IOM uint32_t TRDDP : 1; /*!< [25..25] TRDDP */ + __IOM uint32_t TCTSE : 1; /*!< [26..26] TCTSE */ + __IOM uint32_t TCTSP : 1; /*!< [27..27] TCTSP */ + __IOM uint32_t DTN : 1; /*!< [28..28] DTN */ + uint32_t : 3; + } MTRC_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t MRPFM; /*!< (@ 0x000000AC) MAC Reception Pause or PFC Frame Monitoring Register + * (MRPFM) */ + + struct + { + __IOM uint32_t PTCA : 1; /*!< [0..0] PTCA */ + uint32_t : 15; + __IOM uint32_t PFCTCA : 8; /*!< [23..16] PFCTCA */ + uint32_t : 8; + } MRPFM_b; + }; + __IM uint32_t RESERVED7[20]; + + union + { + __IOM uint32_t MPFC0; /*!< (@ 0x00000100) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC0_b; + }; + + union + { + __IOM uint32_t MPFC1; /*!< (@ 0x00000104) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC1_b; + }; + + union + { + __IOM uint32_t MPFC2; /*!< (@ 0x00000108) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC2_b; + }; + + union + { + __IOM uint32_t MPFC3; /*!< (@ 0x0000010C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC3_b; + }; + + union + { + __IOM uint32_t MPFC4; /*!< (@ 0x00000110) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC4_b; + }; + + union + { + __IOM uint32_t MPFC5; /*!< (@ 0x00000114) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC5_b; + }; + + union + { + __IOM uint32_t MPFC6; /*!< (@ 0x00000118) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC6_b; + }; + + union + { + __IOM uint32_t MPFC7; /*!< (@ 0x0000011C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC7_b; + }; + + union + { + __IOM uint32_t MPFC8; /*!< (@ 0x00000120) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC8_b; + }; + + union + { + __IOM uint32_t MPFC9; /*!< (@ 0x00000124) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC9_b; + }; + + union + { + __IOM uint32_t MPFC10; /*!< (@ 0x00000128) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC10_b; + }; + + union + { + __IOM uint32_t MPFC11; /*!< (@ 0x0000012C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC11_b; + }; + + union + { + __IOM uint32_t MPFC12; /*!< (@ 0x00000130) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC12_b; + }; + + union + { + __IOM uint32_t MPFC13; /*!< (@ 0x00000134) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC13_b; + }; + + union + { + __IOM uint32_t MPFC14; /*!< (@ 0x00000138) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC14_b; + }; + + union + { + __IOM uint32_t MPFC15; /*!< (@ 0x0000013C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC15_b; + }; + __IM uint32_t RESERVED8[16]; + + union + { + __IOM uint32_t MLVC; /*!< (@ 0x00000180) MAC Link Verification Configuration Register + * (MLVC) */ + + struct + { + __IOM uint32_t LVT : 7; /*!< [6..0] LVT */ + uint32_t : 1; + __IOM uint32_t PASE : 1; /*!< [8..8] PASE */ + uint32_t : 7; + __IOM uint32_t PLV : 1; /*!< [16..16] PLV */ + uint32_t : 15; + } MLVC_b; + }; + + union + { + __IOM uint32_t MEEEC; /*!< (@ 0x00000184) MAC Energy Efficient Ethernet Configuration Register + * (MEEEC) */ + + struct + { + __IOM uint32_t LPITR : 1; /*!< [0..0] LPITR */ + uint32_t : 31; + } MEEEC_b; + }; + + union + { + __IOM uint32_t MLBC; /*!< (@ 0x00000188) MAC Loopback Configuration Register (MLBC) */ + + struct + { + __IOM uint32_t LBME : 1; /*!< [0..0] LBME */ + uint32_t : 31; + } MLBC_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MXGMIIC; /*!< (@ 0x00000190) XGMII Configuration Register (MXGMIIC) */ + + struct + { + __IOM uint32_t LFS_TXRFS : 1; /*!< [0..0] LFS_TXRFS */ + __IOM uint32_t LFS_TXIDLE : 1; /*!< [1..1] LFS_TXIDLE */ + uint32_t : 30; + } MXGMIIC_b; + }; + + union + { + __IOM uint32_t MPCH; /*!< (@ 0x00000194) XGMII PCH Configuration Register (MPCH) */ + + struct + { + __IOM uint32_t TXPCH_M : 1; /*!< [0..0] TXPCH_M */ + uint32_t : 1; + __IOM uint32_t TXPCH_ETYPE : 2; /*!< [3..2] TXPCH_ETYPE */ + __IOM uint32_t TXPCH_PID : 4; /*!< [7..4] TXPCH_PID */ + __IOM uint32_t IETPTE : 1; /*!< [8..8] IETPTE */ + __IOM uint32_t CTPTE : 1; /*!< [9..9] CTPTE */ + __IOM uint32_t IETRIOD : 1; /*!< [10..10] IETRIOD */ + __IOM uint32_t CTRIOD : 1; /*!< [11..11] CTRIOD */ + uint32_t : 4; + __IOM uint32_t RXPCH_TSM : 1; /*!< [16..16] RXPCH_TSM */ + __IOM uint32_t RPHCRCD : 1; /*!< [17..17] RPHCRCD */ + uint32_t : 14; + } MPCH_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t MANM; /*!< (@ 0x0000019C) Auto-Negotiation Message Register (MANM) */ + + struct + { + __IOM uint32_t RX_AN_MES : 16; /*!< [15..0] RX_AN_MES */ + uint32_t : 16; + } MANM_b; + }; + __IM uint32_t RESERVED11[24]; + + union + { + __IOM uint32_t MEIS; /*!< (@ 0x00000200) MAC Error Interrupt Status Register (MEIS) */ + + struct + { + __IOM uint32_t TSLS : 1; /*!< [0..0] TSLS */ + __IOM uint32_t TIES : 1; /*!< [1..1] TIES */ + __IOM uint32_t PRES : 1; /*!< [2..2] PRES */ + __IOM uint32_t PFRROS : 1; /*!< [3..3] PFRROS */ + __IOM uint32_t FCDS : 1; /*!< [4..4] FCDS */ + __IOM uint32_t TCES : 1; /*!< [5..5] TCES */ + __IOM uint32_t TBCIS : 1; /*!< [6..6] TBCIS */ + __IOM uint32_t BFES : 1; /*!< [7..7] BFES */ + __IOM uint32_t FCES : 1; /*!< [8..8] FCES */ + __IOM uint32_t REOES : 1; /*!< [9..9] REOES */ + __IOM uint32_t RPOES : 1; /*!< [10..10] RPOES */ + __IOM uint32_t RPCRES : 1; /*!< [11..11] RPCRES */ + __IOM uint32_t CTLES0 : 1; /*!< [12..12] CTLES0 */ + __IOM uint32_t CTLES1 : 1; /*!< [13..13] CTLES1 */ + uint32_t : 6; + __IOM uint32_t PDES : 1; /*!< [20..20] PDES */ + __IOM uint32_t PNAES : 1; /*!< [21..21] PNAES */ + __IOM uint32_t FCMCES : 1; /*!< [22..22] FCMCES */ + __IOM uint32_t FFMES : 1; /*!< [23..23] FFMES */ + __IOM uint32_t CFCES : 1; /*!< [24..24] CFCES */ + __IOM uint32_t FRCES : 1; /*!< [25..25] FRCES */ + __IOM uint32_t RPOOMS : 1; /*!< [26..26] RPOOMS */ + __IOM uint32_t FFS : 1; /*!< [27..27] FFS */ + __IOM uint32_t FUES : 1; /*!< [28..28] FUES */ + __IOM uint32_t FOES : 1; /*!< [29..29] FOES */ + uint32_t : 2; + } MEIS_b; + }; + + union + { + __IOM uint32_t MEIE; /*!< (@ 0x00000204) MAC Error Interrupt Enable Register (MEIE) */ + + struct + { + __IOM uint32_t TSLE : 1; /*!< [0..0] TSLE */ + __IOM uint32_t TIEE : 1; /*!< [1..1] TIEE */ + __IOM uint32_t PMSEE : 1; /*!< [2..2] PMSEE */ + __IOM uint32_t PFRROE : 1; /*!< [3..3] PFRROE */ + __IOM uint32_t FCDE : 1; /*!< [4..4] FCDE */ + __IOM uint32_t TCEE : 1; /*!< [5..5] TCEE */ + __IOM uint32_t TBCIE : 1; /*!< [6..6] TBCIE */ + __IOM uint32_t BFEE : 1; /*!< [7..7] BFEE */ + __IOM uint32_t FCEE : 1; /*!< [8..8] FCEE */ + __IOM uint32_t REOEE : 1; /*!< [9..9] REOEE */ + __IOM uint32_t RPOEE : 1; /*!< [10..10] RPOEE */ + __IOM uint32_t RPCREE : 1; /*!< [11..11] RPCREE */ + __IOM uint32_t CTLEE0 : 1; /*!< [12..12] CTLEE0 */ + __IOM uint32_t CTLEE1 : 1; /*!< [13..13] CTLEE1 */ + uint32_t : 6; + __IOM uint32_t PDEE : 1; /*!< [20..20] PDEE */ + __IOM uint32_t PNAEE : 1; /*!< [21..21] PNAEE */ + __IOM uint32_t FCMCEE : 1; /*!< [22..22] FCMCEE */ + __IOM uint32_t FFMEE : 1; /*!< [23..23] FFMEE */ + __IOM uint32_t CFCEE : 1; /*!< [24..24] CFCEE */ + __IOM uint32_t FRCEE : 1; /*!< [25..25] FRCEE */ + __IOM uint32_t RPOOME : 1; /*!< [26..26] RPOOME */ + __IOM uint32_t FFE : 1; /*!< [27..27] FFE */ + __IOM uint32_t FUEE : 1; /*!< [28..28] FUEE */ + __IOM uint32_t FOEE : 1; /*!< [29..29] FOEE */ + uint32_t : 2; + } MEIE_b; + }; + + union + { + __IOM uint32_t MEID; /*!< (@ 0x00000208) MAC Error Interrupt Disable Register (MEID) */ + + struct + { + __IOM uint32_t TSLD : 1; /*!< [0..0] TSLD */ + __IOM uint32_t TIED : 1; /*!< [1..1] TIED */ + __IOM uint32_t PRED : 1; /*!< [2..2] PRED */ + __IOM uint32_t PFRROD : 1; /*!< [3..3] PFRROD */ + __IOM uint32_t FCDD : 1; /*!< [4..4] FCDD */ + __IOM uint32_t TCED : 1; /*!< [5..5] TCED */ + __IOM uint32_t TBCID : 1; /*!< [6..6] TBCID */ + __IOM uint32_t BFED : 1; /*!< [7..7] BFED */ + __IOM uint32_t FCED : 1; /*!< [8..8] FCED */ + __IOM uint32_t REOED : 1; /*!< [9..9] REOED */ + __IOM uint32_t RPOED : 1; /*!< [10..10] RPOED */ + __IOM uint32_t RPCRED : 1; /*!< [11..11] RPCRED */ + __IOM uint32_t CTLED0 : 1; /*!< [12..12] CTLED0 */ + __IOM uint32_t CTLED1 : 1; /*!< [13..13] CTLED1 */ + uint32_t : 6; + __IOM uint32_t PDED : 1; /*!< [20..20] PDED */ + __IOM uint32_t PNAED : 1; /*!< [21..21] PNAED */ + __IOM uint32_t FCMCED : 1; /*!< [22..22] FCMCED */ + __IOM uint32_t FFMED : 1; /*!< [23..23] FFMED */ + __IOM uint32_t CFCED : 1; /*!< [24..24] CFCED */ + __IOM uint32_t FRCED : 1; /*!< [25..25] FRCED */ + __IOM uint32_t RPOOMD : 1; /*!< [26..26] RPOOMD */ + __IOM uint32_t FFD : 1; /*!< [27..27] FFD */ + __IOM uint32_t FUED : 1; /*!< [28..28] FUED */ + __IOM uint32_t FOED : 1; /*!< [29..29] FOED */ + uint32_t : 2; + } MEID_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t MMIS0; /*!< (@ 0x00000210) MAC Monitoring Interrupt Status Register 0 (MMIS0) */ + + struct + { + __IOM uint32_t PLSCS : 1; /*!< [0..0] PLSCS */ + __IOM uint32_t PIDS : 1; /*!< [1..1] PIDS */ + __IOM uint32_t LVSS : 1; /*!< [2..2] LVSS */ + __IOM uint32_t LVFS : 1; /*!< [3..3] LVFS */ + __IOM uint32_t VFRS : 1; /*!< [4..4] VFRS */ + uint32_t : 1; + __IOM uint32_t ANDETS : 1; /*!< [6..6] ANDETS */ + uint32_t : 1; + __IOM uint32_t XLFDS : 1; /*!< [8..8] XLFDS */ + __IOM uint32_t XLFES : 1; /*!< [9..9] XLFES */ + __IOM uint32_t XLFSDS : 1; /*!< [10..10] XLFSDS */ + __IOM uint32_t XRFSDS : 1; /*!< [11..11] XRFSDS */ + __IOM uint32_t XLISDS : 1; /*!< [12..12] XLISDS */ + uint32_t : 19; + } MMIS0_b; + }; + + union + { + __IOM uint32_t MMIE0; /*!< (@ 0x00000214) MAC Monitoring Interrupt Enable Register 0 (MMIE0) */ + + struct + { + __IOM uint32_t PLSCE : 1; /*!< [0..0] PLSCE */ + __IOM uint32_t PIDE : 1; /*!< [1..1] PIDE */ + __IOM uint32_t LVSE : 1; /*!< [2..2] LVSE */ + __IOM uint32_t LVFE : 1; /*!< [3..3] LVFE */ + __IOM uint32_t VFRE : 1; /*!< [4..4] VFRE */ + uint32_t : 1; + __IOM uint32_t ANDETE : 1; /*!< [6..6] ANDETE */ + uint32_t : 1; + __IOM uint32_t XLFDE : 1; /*!< [8..8] XLFDE */ + __IOM uint32_t XLFEE : 1; /*!< [9..9] XLFEE */ + __IOM uint32_t XLFSDE : 1; /*!< [10..10] XLFSDE */ + __IOM uint32_t XRFSDE : 1; /*!< [11..11] XRFSDE */ + __IOM uint32_t XLISDE : 1; /*!< [12..12] XLISDE */ + uint32_t : 19; + } MMIE0_b; + }; + + union + { + __IOM uint32_t MMID0; /*!< (@ 0x00000218) MAC Monitoring Interrupt Disable Register 0 (MMID0) */ + + struct + { + __IOM uint32_t PLSCD : 1; /*!< [0..0] PLSCD */ + __IOM uint32_t PIDD : 1; /*!< [1..1] PIDD */ + __IOM uint32_t LVSD : 1; /*!< [2..2] LVSD */ + __IOM uint32_t LVFD : 1; /*!< [3..3] LVFD */ + __IOM uint32_t VFRD : 1; /*!< [4..4] VFRD */ + uint32_t : 1; + __IOM uint32_t ANDETD : 1; /*!< [6..6] ANDETD */ + uint32_t : 1; + __IOM uint32_t XLFDD : 1; /*!< [8..8] XLFDD */ + __IOM uint32_t XLFED : 1; /*!< [9..9] XLFED */ + __IOM uint32_t XLFSDD : 1; /*!< [10..10] XLFSDD */ + __IOM uint32_t XRFSDD : 1; /*!< [11..11] XRFSDD */ + __IOM uint32_t XLISDD : 1; /*!< [12..12] XLISDD */ + uint32_t : 19; + } MMID0_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t MMIS1; /*!< (@ 0x00000220) MAC Monitoring Interrupt Status Register 1 (MMIS1) */ + + struct + { + __IOM uint32_t PRACS : 1; /*!< [0..0] PRACS */ + __IOM uint32_t PWACS : 1; /*!< [1..1] PWACS */ + __IOM uint32_t PAACS : 1; /*!< [2..2] PAACS */ + __IOM uint32_t PPRACS : 1; /*!< [3..3] PPRACS */ + uint32_t : 28; + } MMIS1_b; + }; + + union + { + __IOM uint32_t MMIE1; /*!< (@ 0x00000224) MAC Monitoring Interrupt Enable Register 1 (MMIE1) */ + + struct + { + __IOM uint32_t PRACE : 1; /*!< [0..0] PRACE */ + __IOM uint32_t PWACE : 1; /*!< [1..1] PWACE */ + __IOM uint32_t PAACE : 1; /*!< [2..2] PAACE */ + __IOM uint32_t PPRACE : 1; /*!< [3..3] PPRACE */ + uint32_t : 28; + } MMIE1_b; + }; + + union + { + __IOM uint32_t MMID1; /*!< (@ 0x00000228) MAC Monitoring Interrupt Disable Register 1 (MMID1) */ + + struct + { + __IOM uint32_t PRACD : 1; /*!< [0..0] PRACD */ + __IOM uint32_t PWACD : 1; /*!< [1..1] PWACD */ + __IOM uint32_t PAACD : 1; /*!< [2..2] PAACD */ + __IOM uint32_t PPRACD : 1; /*!< [3..3] PPRACD */ + uint32_t : 28; + } MMID1_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t MMIS2; /*!< (@ 0x00000230) MAC Monitoring Interrupt Status Register 2 (MMIS2) */ + + struct + { + __IOM uint32_t MPDIS : 1; /*!< [0..0] MPDIS */ + __IOM uint32_t LPIAIS : 1; /*!< [1..1] LPIAIS */ + __IOM uint32_t LPIDIS : 1; /*!< [2..2] LPIDIS */ + uint32_t : 29; + } MMIS2_b; + }; + + union + { + __IOM uint32_t MMIE2; /*!< (@ 0x00000234) MAC Monitoring Interrupt Enable Register 2 (MMIE2) */ + + struct + { + __IOM uint32_t MPDIE : 1; /*!< [0..0] MPDIE */ + __IOM uint32_t LPIAIE : 1; /*!< [1..1] LPIAIE */ + __IOM uint32_t LPIDIE : 1; /*!< [2..2] LPIDIE */ + uint32_t : 29; + } MMIE2_b; + }; + + union + { + __IOM uint32_t MMID2; /*!< (@ 0x00000238) MAC Monitoring Interrupt Disable Register 2 (MMID2) */ + + struct + { + __IOM uint32_t MPDID : 1; /*!< [0..0] MPDID */ + __IOM uint32_t LPIAID : 1; /*!< [1..1] LPIAID */ + __IOM uint32_t LPIDID : 1; /*!< [2..2] LPIDID */ + uint32_t : 29; + } MMID2_b; + }; + __IM uint32_t RESERVED15[49]; + + union + { + __IOM uint32_t MMPFTCT; /*!< (@ 0x00000300) MAC Manual Pause Frame Transmit Counter Register + * (MMPFTCT) */ + + struct + { + __IOM uint32_t MPFTC : 16; /*!< [15..0] MPFTC */ + uint32_t : 16; + } MMPFTCT_b; + }; + + union + { + __IOM uint32_t MAPFTCT; /*!< (@ 0x00000304) MAC Automatic Pause Frame Transmit Counter Register + * (MAPFTCT) */ + + struct + { + __IOM uint32_t APFTC : 16; /*!< [15..0] APFTC */ + uint32_t : 16; + } MAPFTCT_b; + }; + + union + { + __IOM uint32_t MPFRCT; /*!< (@ 0x00000308) MAC Pause Frame Receive Counter Register (MPFRCT) */ + + struct + { + __IOM uint32_t PFRC : 16; /*!< [15..0] PFRC */ + uint32_t : 16; + } MPFRCT_b; + }; + + union + { + __IOM uint32_t MFCICT; /*!< (@ 0x0000030C) MAC False Carrier Indication Counter Register + * (MFCICT) */ + + struct + { + __IOM uint32_t FCIC : 16; /*!< [15..0] FCIC */ + uint32_t : 16; + } MFCICT_b; + }; + + union + { + __IOM uint32_t MEEECT; /*!< (@ 0x00000310) MAC Energy Efficient Ethernet Counter Register + * (MEEECT) */ + + struct + { + __IOM uint32_t EEERC : 16; /*!< [15..0] EEERC */ + uint32_t : 16; + } MEEECT_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t MMPCFTCT0; /*!< (@ 0x00000320) MAC Manual PFC Frame Transmit Counter Register + * (MMPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t MPCFCTC : 16; /*!< [15..0] MPCFCTC */ + uint32_t : 16; + } MMPCFTCT0_b; + }; + + union + { + __IOM uint32_t MMPCFTCT1; /*!< (@ 0x00000324) MAC Manual PFC Frame Transmit Counter Register + * (MMPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t MPCFCTC : 16; /*!< [15..0] MPCFCTC */ + uint32_t : 16; + } MMPCFTCT1_b; + }; + __IM uint32_t RESERVED17[2]; + + union + { + __IOM uint32_t MAPCFTCT0; /*!< (@ 0x00000330) MAC Automatic PFC Frame Transmit Counter Register + * (MAPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t APCFCTC : 16; /*!< [15..0] APCFCTC */ + uint32_t : 16; + } MAPCFTCT0_b; + }; + + union + { + __IOM uint32_t MAPCFTCT1; /*!< (@ 0x00000334) MAC Automatic PFC Frame Transmit Counter Register + * (MAPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t APCFCTC : 16; /*!< [15..0] APCFCTC */ + uint32_t : 16; + } MAPCFTCT1_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t MPCFRCT0; /*!< (@ 0x00000340) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT0_b; + }; + + union + { + __IOM uint32_t MPCFRCT1; /*!< (@ 0x00000344) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT1_b; + }; + + union + { + __IOM uint32_t MPCFRCT2; /*!< (@ 0x00000348) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT2_b; + }; + + union + { + __IOM uint32_t MPCFRCT3; /*!< (@ 0x0000034C) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT3_b; + }; + + union + { + __IOM uint32_t MPCFRCT4; /*!< (@ 0x00000350) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT4_b; + }; + + union + { + __IOM uint32_t MPCFRCT5; /*!< (@ 0x00000354) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT5_b; + }; + + union + { + __IOM uint32_t MPCFRCT6; /*!< (@ 0x00000358) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT6_b; + }; + + union + { + __IOM uint32_t MPCFRCT7; /*!< (@ 0x0000035C) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT7_b; + }; + + union + { + __IOM uint32_t MROVFC; /*!< (@ 0x00000360) Receive Overflow Counter Register (MROVFC) */ + + struct + { + __IOM uint32_t ROVFC : 32; /*!< [31..0] ROVFC */ + } MROVFC_b; + }; + + union + { + __IOM uint32_t MRHCRCEC; /*!< (@ 0x00000364) Reception Header-CRC(PCH CRC) Error Counter Register + * (MRHCRCEC) */ + + struct + { + __IOM uint32_t RHCRCEC : 16; /*!< [15..0] RHCRCEC */ + uint32_t : 16; + } MRHCRCEC_b; + }; + __IM uint32_t RESERVED19[40]; + + union + { + __IOM uint32_t MRGFCE; /*!< (@ 0x00000408) RMAC Received Good Frame Counter E-Frames Register + * (MRGFCE) */ + + struct + { + __IOM uint32_t RGFNE : 32; /*!< [31..0] RGFNE */ + } MRGFCE_b; + }; + + union + { + __IOM uint32_t MRGFCP; /*!< (@ 0x0000040C) RMAC Received Good Frame Counter P-Frames Register + * (MRGFCP) */ + + struct + { + __IOM uint32_t RGFNP : 32; /*!< [31..0] RGFNP */ + } MRGFCP_b; + }; + + union + { + __IOM uint32_t MRBFC; /*!< (@ 0x00000410) Register (MRBFC) */ + + struct + { + __IOM uint32_t RBFN : 32; /*!< [31..0] RBFN */ + } MRBFC_b; + }; + + union + { + __IOM uint32_t MRMFC; /*!< (@ 0x00000414) RMAC Received Good Multicast Frame Counter Register + * (MRMFC) */ + + struct + { + __IOM uint32_t RMFN : 32; /*!< [31..0] RMFN */ + } MRMFC_b; + }; + + union + { + __IOM uint32_t MRUFC; /*!< (@ 0x00000418) RMAC Received Good Unicast Frame Counter Register + * (MRUFC) */ + + struct + { + __IOM uint32_t RUFN : 32; /*!< [31..0] RUFN */ + } MRUFC_b; + }; + + union + { + __IOM uint32_t MRPEFC; /*!< (@ 0x0000041C) Register (MRPEFC) */ + + struct + { + __IOM uint32_t RPEFN : 16; /*!< [15..0] RPEFN */ + uint32_t : 16; + } MRPEFC_b; + }; + + union + { + __IOM uint32_t MRNEFC; /*!< (@ 0x00000420) Register (MRNEFC) */ + + struct + { + __IOM uint32_t RNEFN : 16; /*!< [15..0] RNEFN */ + uint32_t : 16; + } MRNEFC_b; + }; + + union + { + __IOM uint32_t MRFMEFC; /*!< (@ 0x00000424) Register (MRFMEFC) */ + + struct + { + __IOM uint32_t RFMEFN : 32; /*!< [31..0] RFMEFN */ + } MRFMEFC_b; + }; + + union + { + __IOM uint32_t MRFFMEFC; /*!< (@ 0x00000428) Register (MRFFMEFC) */ + + struct + { + __IOM uint32_t RFFMEFN : 16; /*!< [15..0] RFFMEFN */ + uint32_t : 16; + } MRFFMEFC_b; + }; + + union + { + __IOM uint32_t MRCFCEFC; /*!< (@ 0x0000042C) Register (MRCFCEFC) */ + + struct + { + __IOM uint32_t RCFCEFN : 16; /*!< [15..0] RCFCEFN */ + uint32_t : 16; + } MRCFCEFC_b; + }; + + union + { + __IOM uint32_t MRFCEFC; /*!< (@ 0x00000430) Register (MRFCEFC) */ + + struct + { + __IOM uint32_t RFCEFN : 16; /*!< [15..0] RFCEFN */ + uint32_t : 16; + } MRFCEFC_b; + }; + + union + { + __IOM uint32_t MRRCFEFC; /*!< (@ 0x00000434) Register (MRRCFEFC) */ + + struct + { + __IOM uint32_t RRCFEFN : 16; /*!< [15..0] RRCFEFN */ + uint32_t : 16; + } MRRCFEFC_b; + }; + + union + { + __IOM uint32_t MRFC; /*!< (@ 0x00000438) Register (MRFC) */ + + struct + { + __IOM uint32_t RFN : 32; /*!< [31..0] RFN */ + } MRFC_b; + }; + + union + { + __IOM uint32_t MRGUEFC; /*!< (@ 0x0000043C) RMAC Received Good Undersize Error Frame Count + * Register (MRGUEFC) */ + + struct + { + __IOM uint32_t RUEFN : 32; /*!< [31..0] RUEFN */ + } MRGUEFC_b; + }; + + union + { + __IOM uint32_t MRBUEFC; /*!< (@ 0x00000440) RMAC Received bad Undersize Error Frame Count + * Register (MRBUEFC) */ + + struct + { + __IOM uint32_t RUEFN : 32; /*!< [31..0] RUEFN */ + } MRBUEFC_b; + }; + + union + { + __IOM uint32_t MRGOEFC; /*!< (@ 0x00000444) Register (MRGOEFC) */ + + struct + { + __IOM uint32_t RGOEFN : 32; /*!< [31..0] RGOEFN */ + } MRGOEFC_b; + }; + + union + { + __IOM uint32_t MRBOEFC; /*!< (@ 0x00000448) Register (MRBOEFC) */ + + struct + { + __IOM uint32_t RBOEFN : 32; /*!< [31..0] RBOEFN */ + } MRBOEFC_b; + }; + + union + { + __IOM uint32_t MRXBCEU; /*!< (@ 0x0000044C) Register (MRXBCEU) */ + + struct + { + __IOM uint32_t RBNEU : 32; /*!< [31..0] RBNEU */ + } MRXBCEU_b; + }; + + union + { + __IOM uint32_t MRXBCEL; /*!< (@ 0x00000450) Register (MRXBCEL) */ + + struct + { + __IOM uint32_t RBNEL : 32; /*!< [31..0] RBNEL */ + } MRXBCEL_b; + }; + + union + { + __IOM uint32_t MRXBCPU; /*!< (@ 0x00000454) Register (MRXBCPU) */ + + struct + { + __IOM uint32_t RBNPU : 32; /*!< [31..0] RBNPU */ + } MRXBCPU_b; + }; + + union + { + __IOM uint32_t MRXBCPL; /*!< (@ 0x00000458) Register (MRXBCPL) */ + + struct + { + __IOM uint32_t RBNPL : 32; /*!< [31..0] RBNPL */ + } MRXBCPL_b; + }; + __IM uint32_t RESERVED20[43]; + + union + { + __IOM uint32_t MTGFCE; /*!< (@ 0x00000508) RMAC Transmitted Good Frame Counter E-Frames + * Register (MTGFCE) */ + + struct + { + __IOM uint32_t TGFNE : 32; /*!< [31..0] TGFNE */ + } MTGFCE_b; + }; + + union + { + __IOM uint32_t MTGFCP; /*!< (@ 0x0000050C) RMAC Transmitted Good Frame Counter P-Frames + * Register (MTGFCP) */ + + struct + { + __IOM uint32_t TGFNP : 32; /*!< [31..0] TGFNP */ + } MTGFCP_b; + }; + + union + { + __IOM uint32_t MTBFC; /*!< (@ 0x00000510) Register (MTBFC) */ + + struct + { + __IOM uint32_t TBFN : 32; /*!< [31..0] TBFN */ + } MTBFC_b; + }; + + union + { + __IOM uint32_t MTMFC; /*!< (@ 0x00000514) RMAC Transmitted Multicast Frame Counter Register + * (MTMFC) */ + + struct + { + __IOM uint32_t TMFN : 32; /*!< [31..0] TMFN */ + } MTMFC_b; + }; + + union + { + __IOM uint32_t MTUFC; /*!< (@ 0x00000518) Register (MTUFC) */ + + struct + { + __IOM uint32_t TUFN : 32; /*!< [31..0] TUFN */ + } MTUFC_b; + }; + + union + { + __IOM uint32_t MTEFC; /*!< (@ 0x0000051C) Register (MTEFC) */ + + struct + { + __IOM uint32_t TEFN : 16; /*!< [15..0] TEFN */ + uint32_t : 16; + } MTEFC_b; + }; + + union + { + __IOM uint32_t MTXBCEU; /*!< (@ 0x00000520) Register (MTXBCEU) */ + + struct + { + __IOM uint32_t TBNEU : 32; /*!< [31..0] TBNEU */ + } MTXBCEU_b; + }; + + union + { + __IOM uint32_t MTXBCEL; /*!< (@ 0x00000524) Register (MTXBCEL) */ + + struct + { + __IOM uint32_t TBNEL : 32; /*!< [31..0] TBNEL */ + } MTXBCEL_b; + }; + + union + { + __IOM uint32_t MTXBCPU; /*!< (@ 0x00000528) RMAC Transmitted Byte Counter P-Frames Upper + * Side Register (MTXBCPU) */ + + struct + { + __IOM uint32_t TBNPU : 32; /*!< [31..0] TBNPU */ + } MTXBCPU_b; + }; + + union + { + __IOM uint32_t MTXBCPL; /*!< (@ 0x0000052C) RMAC Transmitted Byte Counter P-Frames Lower + * Side Register (MTXBCPL) */ + + struct + { + __IOM uint32_t TBNPL : 32; /*!< [31..0] TBNPL */ + } MTXBCPL_b; + }; +} R_RMAC0_Type; /*!< Size = 1328 (0x530) */ + +/* =========================================================================================================================== */ +/* ================ R_TCM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Tightly Coupled Memory (R_TCM) + */ + +typedef struct /*!< (@ 0x4001C800) R_TCM Structure */ +{ + union + { + __IOM uint16_t TCMPRCR_S; /*!< (@ 0x00000000) TCM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __IOM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } TCMPRCR_S_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TCMPRCR_NS; /*!< (@ 0x00000004) TCM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __IOM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } TCMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint8_t TCMCRC; /*!< (@ 0x00000010) TCM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } TCMCRC_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t TCMCRS; /*!< (@ 0x00000014) TCM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } TCMCRS_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[10]; + + union + { + __IOM uint16_t TCMESR; /*!< (@ 0x00000040) TCM Error Status Register */ + + struct + { + __IOM uint16_t ERRC0 : 1; /*!< [0..0] C-TCM 1-bit ECC Error Status */ + __IOM uint16_t ERRC1 : 1; /*!< [1..1] C-TCM 2-bit ECC Error Status */ + __IOM uint16_t ERRS0 : 1; /*!< [2..2] S-TCM 1-bit ECC Error Status */ + __IOM uint16_t ERRS1 : 1; /*!< [3..3] S-TCM 2-bit ECC Error Status */ + uint16_t : 12; + } TCMESR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t TCMESCLR; /*!< (@ 0x00000048) TCM Error Status Clear Register */ + + struct + { + __IOM uint16_t CLRC0 : 1; /*!< [0..0] TCM 1-bit ECC Error Status Clear */ + __IOM uint16_t CLRC1 : 1; /*!< [1..1] TCM 2-bit ECC Error Status Clear */ + __IOM uint16_t CLRS0 : 1; /*!< [2..2] S-TCM 1-bit ECC Error Status Clear */ + __IOM uint16_t CLRS1 : 1; /*!< [3..3] S-TCM 2-bit ECC Error Status Clear */ + uint16_t : 12; + } TCMESCLR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t TCMEARC0; /*!< (@ 0x00000050) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARC0_b; + }; + + union + { + __IOM uint32_t TCMEARC1; /*!< (@ 0x00000054) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARC1_b; + }; + + union + { + __IOM uint32_t TCMEARS0; /*!< (@ 0x00000058) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARS0_b; + }; + + union + { + __IOM uint32_t TCMEARS1; /*!< (@ 0x0000005C) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARS1_b; + }; +} R_TCM_Type; /*!< Size = 96 (0x60) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #if defined(_RA_TZ_NONSECURE) + #define BASE_NS_OFFSET (BSP_FEATURE_TZ_NS_OFFSET) + #else + #define BASE_NS_OFFSET 0U + #endif + + #define R_ACMPHS0_BASE (0x40236000UL + BASE_NS_OFFSET) + #define R_ACMPHS1_BASE (0x40236100UL + BASE_NS_OFFSET) + #define R_ACMPHS2_BASE (0x40236200UL + BASE_NS_OFFSET) + #define R_ACMPHS3_BASE (0x40236300UL + BASE_NS_OFFSET) + #define R_ACMPHS4_BASE (0x40236400UL + BASE_NS_OFFSET) + #define R_ACMPHS5_BASE (0x40236500UL + BASE_NS_OFFSET) + #define R_PSCU_BASE (0x40204000UL + BASE_NS_OFFSET) + #define R_BUS_BASE (0x40003000UL + BASE_NS_OFFSET) + #define R_CAC_BASE (0x40202400UL + BASE_NS_OFFSET) + #define R_CANFD_BASE (0x40380000UL + BASE_NS_OFFSET) + #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) + #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) + #define R_DAC_B0_BASE (0x40233000UL + BASE_NS_OFFSET) + #define R_DAC_B1_BASE (0x40233100UL + BASE_NS_OFFSET) + #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) + #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) + #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) + #define R_DMAC1_BASE (0x4000A040UL + BASE_NS_OFFSET) + #define R_DMAC2_BASE (0x4000A080UL + BASE_NS_OFFSET) + #define R_DMAC3_BASE (0x4000A0C0UL + BASE_NS_OFFSET) + #define R_DMAC4_BASE (0x4000A100UL + BASE_NS_OFFSET) + #define R_DMAC5_BASE (0x4000A140UL + BASE_NS_OFFSET) + #define R_DMAC6_BASE (0x4000A180UL + BASE_NS_OFFSET) + #define R_DMAC7_BASE (0x4000A1C0UL + BASE_NS_OFFSET) + #define R_DOC_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_DRW_BASE (0x40444000UL + BASE_NS_OFFSET) + #define R_DTC_BASE (0x4000AC00UL + BASE_NS_OFFSET) + #define R_ELC_BASE (0x40201000UL + BASE_NS_OFFSET) + #define R_ETHERC_EDMAC_BASE (0x40354000UL + BASE_NS_OFFSET) + #define R_GLCDC_BASE (0x40342000UL + BASE_NS_OFFSET) + #define R_GPT0_BASE (0x40322000UL + BASE_NS_OFFSET) + #define R_GPT1_BASE (0x40322100UL + BASE_NS_OFFSET) + #define R_GPT2_BASE (0x40322200UL + BASE_NS_OFFSET) + #define R_GPT3_BASE (0x40322300UL + BASE_NS_OFFSET) + #define R_GPT4_BASE (0x40322400UL + BASE_NS_OFFSET) + #define R_GPT5_BASE (0x40322500UL + BASE_NS_OFFSET) + #define R_GPT6_BASE (0x40322600UL + BASE_NS_OFFSET) + #define R_GPT7_BASE (0x40322700UL + BASE_NS_OFFSET) + #define R_GPT8_BASE (0x40322800UL + BASE_NS_OFFSET) + #define R_GPT9_BASE (0x40322900UL + BASE_NS_OFFSET) + #define R_GPT10_BASE (0x40322A00UL + BASE_NS_OFFSET) + #define R_GPT11_BASE (0x40322B00UL + BASE_NS_OFFSET) + #define R_GPT12_BASE (0x40322C00UL + BASE_NS_OFFSET) + #define R_GPT13_BASE (0x40322D00UL + BASE_NS_OFFSET) + #define R_GPT_GTCLK_BASE (0x40323F10UL + BASE_NS_OFFSET) + #define R_GPT_ODC_BASE (0x40324000UL + BASE_NS_OFFSET) + #define R_GPT_OPS_BASE (0x40323F00UL + BASE_NS_OFFSET) + #define R_GPT_POEG0_BASE (0x40212000UL + BASE_NS_OFFSET) + #define R_GPT_POEG1_BASE (0x40212100UL + BASE_NS_OFFSET) + #define R_GPT_POEG2_BASE (0x40212200UL + BASE_NS_OFFSET) + #define R_GPT_POEG3_BASE (0x40212300UL + BASE_NS_OFFSET) + #define R_ICU_BASE (0x40006000UL + BASE_NS_OFFSET) + #define R_IIC0_BASE (0x4025E000UL + BASE_NS_OFFSET) + #define R_IIC1_BASE (0x4025E100UL + BASE_NS_OFFSET) + #define R_IIC2_BASE (0x4025E200UL + BASE_NS_OFFSET) + #define R_IWDT_BASE (0x40202200UL + BASE_NS_OFFSET) + #define R_I3C0_BASE (0x4035F000UL + BASE_NS_OFFSET) + #define R_I3C1_BASE (0x4035F100UL + BASE_NS_OFFSET) + #define R_MPU_MMPU_BASE (0x40000000UL + BASE_NS_OFFSET) + #define R_MPU_SPMON_BASE (0x40000D00UL + BASE_NS_OFFSET) + #define R_MSTP_BASE (0x40203000UL + BASE_NS_OFFSET) + #define R_PORT0_BASE (0x40400000UL + BASE_NS_OFFSET) + #define R_PORT1_BASE (0x40400020UL + BASE_NS_OFFSET) + #define R_PORT2_BASE (0x40400040UL + BASE_NS_OFFSET) + #define R_PORT3_BASE (0x40400060UL + BASE_NS_OFFSET) + #define R_PORT4_BASE (0x40400080UL + BASE_NS_OFFSET) + #define R_PORT5_BASE (0x404000A0UL + BASE_NS_OFFSET) + #define R_PORT6_BASE (0x404000C0UL + BASE_NS_OFFSET) + #define R_PORT7_BASE (0x404000E0UL + BASE_NS_OFFSET) + #define R_PORT8_BASE (0x40400100UL + BASE_NS_OFFSET) + #define R_PORT9_BASE (0x40400120UL + BASE_NS_OFFSET) + #define R_PORT10_BASE (0x40400140UL + BASE_NS_OFFSET) + #define R_PORT11_BASE (0x40400160UL + BASE_NS_OFFSET) + #define R_PORT12_BASE (0x40400180UL + BASE_NS_OFFSET) + #define R_PORT13_BASE (0x404001A0UL + BASE_NS_OFFSET) + #define R_PORT14_BASE (0x404001C0UL + BASE_NS_OFFSET) + #define R_PFS_BASE (0x40400800UL + BASE_NS_OFFSET) + #define R_PMISC_BASE (0x40400D00UL + BASE_NS_OFFSET) + #define R_RTC_BASE (0x40202000UL + BASE_NS_OFFSET) + #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_SCI9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SDHI0_BASE (0x40252000UL + BASE_NS_OFFSET) + #define R_SDHI1_BASE (0x40252400UL + BASE_NS_OFFSET) + #define R_SPI0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_SPI2_BASE (0x40072200UL + BASE_NS_OFFSET) + #define R_SRAM_BASE (0x40002000UL + BASE_NS_OFFSET) + #define R_SSI0_BASE (0x4025D000UL + BASE_NS_OFFSET) + #define R_SSI1_BASE (0x4025D100UL + BASE_NS_OFFSET) + #define R_SYSTEM_BASE (0x4001E000UL + BASE_NS_OFFSET) + #define R_TSN_CAL_BASE (0x02C1EDA0UL + BASE_NS_OFFSET) + #define R_TSN_CTRL_BASE (0x40235000UL + BASE_NS_OFFSET) + #define R_USB_FS0_BASE (0x40250000UL + BASE_NS_OFFSET) + #define R_VIN_BASE (0x40347400UL + BASE_NS_OFFSET) + #define R_WDT_BASE (0x40202600UL + BASE_NS_OFFSET) + #define R_CPSCU_BASE (0x40008000UL + BASE_NS_OFFSET) + #define R_ADC_B0_BASE (0x40338000UL + BASE_NS_OFFSET) + #define R_DOC_B_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_SCI_B0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI_B1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI_B2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI_B3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI_B4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI_B9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SPI_B0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI_B1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_USB_HS0_BASE (0x40351000UL + BASE_NS_OFFSET) + #define R_XSPI0_BASE (0x40268000UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) + #define R_MIPI_PHY_BASE (0x40346C00UL + BASE_NS_OFFSET) + #define R_MIPI_CSI_BASE (0x40347000UL + BASE_NS_OFFSET) + #define R_CEU_BASE (0x40348000UL + BASE_NS_OFFSET) + #define R_ULPT0_BASE (0x40220000UL + BASE_NS_OFFSET) + #define R_ULPT1_BASE (0x40220100UL + BASE_NS_OFFSET) + #define R_DEBUG_OCD_BASE (0x40011000UL + BASE_NS_OFFSET) + #define R_DOTF_BASE (0x40268800UL + BASE_NS_OFFSET) + #define R_AGTX0_BASE (0x40221000UL + BASE_NS_OFFSET) + #define R_AGTX1_BASE (0x40221100UL + BASE_NS_OFFSET) + #define R_AGTX2_BASE (0x40221200UL + BASE_NS_OFFSET) + #define R_AGTX3_BASE (0x40221300UL + BASE_NS_OFFSET) + #define R_AGTX4_BASE (0x40221400UL + BASE_NS_OFFSET) + #define R_AGTX5_BASE (0x40221500UL + BASE_NS_OFFSET) + #define R_AGTX6_BASE (0x40221600UL + BASE_NS_OFFSET) + #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) + #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) + #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_COMA_BASE (0x403C9000UL + BASE_NS_OFFSET) + #define R_CPU_CTRL_BASE (0x4000F000UL + BASE_NS_OFFSET) + #define R_DOTF1_BASE (0x40268900UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) + #define R_ESWM_BASE (0x403C8000UL + BASE_NS_OFFSET) + #define R_ETHA0_BASE (0x403CA000UL + BASE_NS_OFFSET) + #define R_ETHA1_BASE (0x403CC000UL + BASE_NS_OFFSET) + #define R_GPTP_BASE (0x403E0000UL + BASE_NS_OFFSET) + #define R_GWCA0_BASE (0x403CE000UL + BASE_NS_OFFSET) + #define R_IPC_BASE (0x40020000UL + BASE_NS_OFFSET) + #define R_MFWD_BASE (0x403C0000UL + BASE_NS_OFFSET) + #define R_MIPI_DSI_BASE (0x40346000UL + BASE_NS_OFFSET) + #define R_MRMS_BASE (0x4013C000UL + BASE_NS_OFFSET) + #define R_NPU_BASE (0x40140000UL + BASE_NS_OFFSET) + #define R_PDM_BASE (0x40256000UL + BASE_NS_OFFSET) + #define R_RMAC0_BASE (0x403CB000UL + BASE_NS_OFFSET) + #define R_RMAC1_BASE (0x403CD000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_TCM_BASE (0x4001C800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40202700UL + BASE_NS_OFFSET) + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC_B0 ((R_DAC_B0_Type *) R_DAC_B0_BASE) + #define R_DAC_B1 ((R_DAC_B0_Type *) R_DAC_B1_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_VIN ((R_VIN_Type *) R_VIN_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_ADC_B ((R_ADC_B0_Type *) R_ADC_B0_BASE) + #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE) + #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE) + #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE) + #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE) + #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE) + #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE) + #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE) + #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) + #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_MIPI_PHY ((R_MIPI_PHY_Type *) R_MIPI_PHY_BASE) + #define R_MIPI_CSI ((R_MIPI_CSI_Type *) R_MIPI_CSI_BASE) + #define R_CEU ((R_CEU_Type *) R_CEU_BASE) + #define R_ULPT0 ((R_ULPT0_Type *) R_ULPT0_BASE) + #define R_ULPT1 ((R_ULPT0_Type *) R_ULPT1_BASE) + #define R_DEBUG_OCD ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE) + #define R_DOTF ((R_DOTF_Type *) R_DOTF_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_COMA ((R_COMA_Type *) R_COMA_BASE) + #define R_CPU_CTRL ((R_CPU_CTRL_Type *) R_CPU_CTRL_BASE) + #define R_DOTF1 ((R_DOTF_Type *) R_DOTF1_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) + #define R_ESWM ((R_ESWM_Type *) R_ESWM_BASE) + #define R_ETHA0 ((R_ETHA0_Type *) R_ETHA0_BASE) + #define R_ETHA1 ((R_ETHA0_Type *) R_ETHA1_BASE) + #define R_GPTP ((R_GPTP_Type *) R_GPTP_BASE) + #define R_GWCA0 ((R_GWCA0_Type *) R_GWCA0_BASE) + #define R_IPC ((R_IPC_Type *) R_IPC_BASE) + #define R_MFWD ((R_MFWD_Type *) R_MFWD_BASE) + #define R_MIPI_DSI ((R_MIPI_DSI_Type *) R_MIPI_DSI_BASE) + #define R_MRMS ((R_MRMS_Type *) R_MRMS_BASE) + #define R_NPU ((R_NPU_Type *) R_NPU_BASE) + #define R_PDM ((R_PDM_Type *) R_PDM_BASE) + #define R_RMAC0 ((R_RMAC0_Type *) R_RMAC0_BASE) + #define R_RMAC1 ((R_RMAC0_Type *) R_RMAC1_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_TCM ((R_TCM_Type *) R_TCM_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x3ffUL) /*!< ELS (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ BG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= PERI ========================================================== */ + #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */ + #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */ + #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SYNC ========================================================== */ + #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */ + #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */ + #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */ +/* ========================================================= VSIZE ========================================================= */ + #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= HSIZE ========================================================= */ + #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== BGC ========================================================== */ + #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== VEN ========================================================== */ + #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */ + #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FLMRD ========================================================= */ + #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */ + #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */ +/* ========================================================= FLM1 ========================================================== */ + #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */ + #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */ +/* ========================================================= FLM2 ========================================================== */ + #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ + #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLM3 ========================================================== */ + #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */ + #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM5 ========================================================== */ + #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */ + #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */ + #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM6 ========================================================== */ + #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */ + #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */ +/* ========================================================== AB1 ========================================================== */ + #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */ + #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */ + #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== AB2 ========================================================== */ + #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */ + #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */ + #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB3 ========================================================== */ + #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */ + #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */ + #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB4 ========================================================== */ + #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */ + #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */ + #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB5 ========================================================== */ + #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */ + #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */ + #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB6 ========================================================== */ + #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */ + #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */ + #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */ + #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */ +/* ========================================================== AB7 ========================================================== */ + #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */ + #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */ + #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */ +/* ========================================================== AB8 ========================================================== */ + #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */ + #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */ + #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */ + #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */ +/* ========================================================== AB9 ========================================================== */ + #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */ + #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */ + #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */ + #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */ + #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */ +/* ========================================================= BASE ========================================================== */ + #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */ + #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */ + #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */ +/* ======================================================== CLUTINT ======================================================== */ + #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */ + #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */ + #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */ + #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */ + #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LATCH ========================================================= */ + #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ======================================================== GAM_SW ========================================================= */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */ +/* ========================================================== LUT ========================================================== */ + #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */ +/* ========================================================= AREA ========================================================== */ + #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ OUT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VLATCH ========================================================= */ + #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */ + #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */ + #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */ + #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */ + #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */ + #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */ + #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +/* ======================================================== BRIGHT1 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BRIGHT2 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CONTRAST ======================================================== */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */ +/* ========================================================= PDTHA ========================================================= */ + #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */ + #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */ + #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */ + #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */ + #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */ + #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */ + #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */ +/* ======================================================= CLKPHASE ======================================================== */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TCON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TIM ========================================================== */ + #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */ + #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA1 ========================================================= */ + #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVB1 ========================================================= */ + #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA2 ========================================================= */ + #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STVB2 ========================================================= */ + #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHA1 ========================================================= */ + #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHB1 ========================================================= */ + #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHA2 ========================================================= */ + #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHB2 ========================================================= */ + #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================== DE =========================================================== */ + #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */ + #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSCNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DTCTEN ========================================================= */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCLR ========================================================= */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= STMON ========================================================= */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */ +/* ======================================================= PANEL_CLK ======================================================= */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CMCFGCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Pos (4UL) /*!< WPBSTMD (Bit 4) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Msk (0x10UL) /*!< WPBSTMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Pos (5UL) /*!< ARYAMD (Bit 5) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Msk (0x20UL) /*!< ARYAMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ CDBUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CDBUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_CDBUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDBUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_CDBUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_CDBUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_CDBUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_CDBUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_CDBUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CCCTLCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CABPPPFLC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== LEVEL0 ========================================================= */ + #define R_COMA_CABPPPFLC_LEVEL0_PPDL_Pos (0UL) /*!< PPDL (Bit 0) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPDL_Msk (0x3ffUL) /*!< PPDL (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPAL_Pos (16UL) /*!< PPAL (Bit 16) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPAL_Msk (0x3ff0000UL) /*!< PPAL (Bitfield-Mask: 0x3ff) */ +/* ======================================================== LEVEL1 ========================================================= */ + #define R_COMA_CABPPPFLC_LEVEL1_PPDL_Pos (0UL) /*!< PPDL (Bit 0) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPDL_Msk (0x3ffUL) /*!< PPDL (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPAL_Pos (16UL) /*!< PPAL (Bit 16) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPAL_Msk (0x3ff0000UL) /*!< PPAL (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ IPCNMI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== STA ========================================================== */ + #define R_IPC_IPCNMI_STA_NMI_Pos (0UL) /*!< NMI (Bit 0) */ + #define R_IPC_IPCNMI_STA_NMI_Msk (0x1UL) /*!< NMI (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_IPC_IPCNMI_SET_SET_Pos (0UL) /*!< SET (Bit 0) */ + #define R_IPC_IPCNMI_SET_SET_Msk (0x1UL) /*!< SET (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_IPC_IPCNMI_CLR_CLR_Pos (0UL) /*!< CLR (Bit 0) */ + #define R_IPC_IPCNMI_CLR_CLR_Msk (0x1UL) /*!< CLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== STA ========================================================== */ + #define R_IPC_IPC_CH_STA_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ + #define R_IPC_IPC_CH_STA_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_RDY_Pos (16UL) /*!< RDY (Bit 16) */ + #define R_IPC_IPC_CH_STA_RDY_Msk (0x10000UL) /*!< RDY (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_FULL_Pos (17UL) /*!< FULL (Bit 17) */ + #define R_IPC_IPC_CH_STA_FULL_Msk (0x20000UL) /*!< FULL (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_RERR_Pos (24UL) /*!< RERR (Bit 24) */ + #define R_IPC_IPC_CH_STA_RERR_Msk (0x1000000UL) /*!< RERR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_FERR_Pos (25UL) /*!< FERR (Bit 25) */ + #define R_IPC_IPC_CH_STA_FERR_Msk (0x2000000UL) /*!< FERR (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_IPC_IPC_CH_SET_SET_Pos (0UL) /*!< SET (Bit 0) */ + #define R_IPC_IPC_CH_SET_SET_Msk (0x1UL) /*!< SET (Bitfield-Mask: 0x01) */ +/* ========================================================== TXD ========================================================== */ + #define R_IPC_IPC_CH_TXD_TXD_Pos (0UL) /*!< TXD (Bit 0) */ + #define R_IPC_IPC_CH_TXD_TXD_Msk (0xffffffffUL) /*!< TXD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RXD ========================================================== */ + #define R_IPC_IPC_CH_RXD_RXD_Pos (0UL) /*!< RXD (Bit 0) */ + #define R_IPC_IPC_CH_RXD_RXD_Msk (0xffffffffUL) /*!< RXD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== CLR ========================================================== */ + #define R_IPC_IPC_CH_CLR_CLR_Pos (0UL) /*!< CLR (Bit 0) */ + #define R_IPC_IPC_CH_CLR_CLR_Msk (0x1UL) /*!< CLR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_RST_Pos (16UL) /*!< RST (Bit 16) */ + #define R_IPC_IPC_CH_CLR_RST_Msk (0x10000UL) /*!< RST (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_RCLR_Pos (24UL) /*!< RCLR (Bit 24) */ + #define R_IPC_IPC_CH_CLR_RCLR_Msk (0x1000000UL) /*!< RCLR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_FCLR_Pos (25UL) /*!< FCLR (Bit 25) */ + #define R_IPC_IPC_CH_CLR_FCLR_Msk (0x2000000UL) /*!< FCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ IPC ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PDSTRTR ======================================================== */ + #define R_PDM_CH_PDSTRTR_STRTRG_Pos (0UL) /*!< STRTRG (Bit 0) */ + #define R_PDM_CH_PDSTRTR_STRTRG_Msk (0x1UL) /*!< STRTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== PDSTPTR ======================================================== */ + #define R_PDM_CH_PDSTPTR_STPTRG_Pos (0UL) /*!< STPTRG (Bit 0) */ + #define R_PDM_CH_PDSTPTR_STPTRG_Msk (0x1UL) /*!< STPTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCHGTR ======================================================== */ + #define R_PDM_CH_PDCHGTR_CHGTRG_Pos (0UL) /*!< CHGTRG (Bit 0) */ + #define R_PDM_CH_PDCHGTR_CHGTRG_Msk (0x1UL) /*!< CHGTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= PDICR ========================================================= */ + #define R_PDM_CH_PDICR_ISDE_Pos (1UL) /*!< ISDE (Bit 1) */ + #define R_PDM_CH_PDICR_ISDE_Msk (0x2UL) /*!< ISDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDICR_IDRE_Pos (2UL) /*!< IDRE (Bit 2) */ + #define R_PDM_CH_PDICR_IDRE_Msk (0x4UL) /*!< IDRE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDICR_IEDE_Pos (16UL) /*!< IEDE (Bit 16) */ + #define R_PDM_CH_PDICR_IEDE_Msk (0x10000UL) /*!< IEDE (Bitfield-Mask: 0x01) */ +/* ======================================================== PDSDCR ========================================================= */ + #define R_PDM_CH_PDSDCR_SDE_Pos (1UL) /*!< SDE (Bit 1) */ + #define R_PDM_CH_PDSDCR_SDE_Msk (0x2UL) /*!< SDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_SCDE_Pos (16UL) /*!< SCDE (Bit 16) */ + #define R_PDM_CH_PDSDCR_SCDE_Msk (0x10000UL) /*!< SCDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_OVLDE_Pos (17UL) /*!< OVLDE (Bit 17) */ + #define R_PDM_CH_PDSDCR_OVLDE_Msk (0x20000UL) /*!< OVLDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_OVUDE_Pos (18UL) /*!< OVUDE (Bit 18) */ + #define R_PDM_CH_PDSDCR_OVUDE_Msk (0x40000UL) /*!< OVUDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_BFOWDE_Pos (27UL) /*!< BFOWDE (Bit 27) */ + #define R_PDM_CH_PDSDCR_BFOWDE_Msk (0x8000000UL) /*!< BFOWDE (Bitfield-Mask: 0x01) */ +/* ========================================================= PDSR ========================================================== */ + #define R_PDM_CH_PDSR_STATE_Pos (0UL) /*!< STATE (Bit 0) */ + #define R_PDM_CH_PDSR_STATE_Msk (0x1UL) /*!< STATE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_SDF_Pos (1UL) /*!< SDF (Bit 1) */ + #define R_PDM_CH_PDSR_SDF_Msk (0x2UL) /*!< SDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_DRF_Pos (2UL) /*!< DRF (Bit 2) */ + #define R_PDM_CH_PDSR_DRF_Msk (0x4UL) /*!< DRF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_SCDF_Pos (16UL) /*!< SCDF (Bit 16) */ + #define R_PDM_CH_PDSR_SCDF_Msk (0x10000UL) /*!< SCDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_OVLDF_Pos (17UL) /*!< OVLDF (Bit 17) */ + #define R_PDM_CH_PDSR_OVLDF_Msk (0x20000UL) /*!< OVLDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_OVUDF_Pos (18UL) /*!< OVUDF (Bit 18) */ + #define R_PDM_CH_PDSR_OVUDF_Msk (0x40000UL) /*!< OVUDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_BFOWDF_Pos (27UL) /*!< BFOWDF (Bit 27) */ + #define R_PDM_CH_PDSR_BFOWDF_Msk (0x8000000UL) /*!< BFOWDF (Bitfield-Mask: 0x01) */ +/* ========================================================= PDSCR ========================================================= */ + #define R_PDM_CH_PDSCR_SDFC_Pos (1UL) /*!< SDFC (Bit 1) */ + #define R_PDM_CH_PDSCR_SDFC_Msk (0x2UL) /*!< SDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_SCDFC_Pos (16UL) /*!< SCDFC (Bit 16) */ + #define R_PDM_CH_PDSCR_SCDFC_Msk (0x10000UL) /*!< SCDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_OVLDFC_Pos (17UL) /*!< OVLDFC (Bit 17) */ + #define R_PDM_CH_PDSCR_OVLDFC_Msk (0x20000UL) /*!< OVLDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_OVUDFC_Pos (18UL) /*!< OVUDFC (Bit 18) */ + #define R_PDM_CH_PDSCR_OVUDFC_Msk (0x40000UL) /*!< OVUDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_BFOWDFC_Pos (27UL) /*!< BFOWDFC (Bit 27) */ + #define R_PDM_CH_PDSCR_BFOWDFC_Msk (0x8000000UL) /*!< BFOWDFC (Bitfield-Mask: 0x01) */ +/* ======================================================== PDMDSR ========================================================= */ + #define R_PDM_CH_PDMDSR_INPSEL_Pos (0UL) /*!< INPSEL (Bit 0) */ + #define R_PDM_CH_PDMDSR_INPSEL_Msk (0x1UL) /*!< INPSEL (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDMDSR_SFMD_Pos (4UL) /*!< SFMD (Bit 4) */ + #define R_PDM_CH_PDMDSR_SFMD_Msk (0x70UL) /*!< SFMD (Bitfield-Mask: 0x07) */ + #define R_PDM_CH_PDMDSR_HFIS_Pos (8UL) /*!< HFIS (Bit 8) */ + #define R_PDM_CH_PDMDSR_HFIS_Msk (0x300UL) /*!< HFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_CFIS_Pos (12UL) /*!< CFIS (Bit 12) */ + #define R_PDM_CH_PDMDSR_CFIS_Msk (0x3000UL) /*!< CFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_LFIS_Pos (16UL) /*!< LFIS (Bit 16) */ + #define R_PDM_CH_PDMDSR_LFIS_Msk (0x30000UL) /*!< LFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_SDMAMD_Pos (24UL) /*!< SDMAMD (Bit 24) */ + #define R_PDM_CH_PDMDSR_SDMAMD_Msk (0x3000000UL) /*!< SDMAMD (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_DBIS_Pos (28UL) /*!< DBIS (Bit 28) */ + #define R_PDM_CH_PDMDSR_DBIS_Msk (0xf0000000UL) /*!< DBIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== PDSFCR ========================================================= */ + #define R_PDM_CH_PDSFCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_PDM_CH_PDSFCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ + #define R_PDM_CH_PDSFCR_SINCDEC_Pos (16UL) /*!< SINCDEC (Bit 16) */ + #define R_PDM_CH_PDSFCR_SINCDEC_Msk (0xff0000UL) /*!< SINCDEC (Bitfield-Mask: 0xff) */ + #define R_PDM_CH_PDSFCR_SINCRNG_Pos (24UL) /*!< SINCRNG (Bit 24) */ + #define R_PDM_CH_PDSFCR_SINCRNG_Msk (0x1f000000UL) /*!< SINCRNG (Bitfield-Mask: 0x1f) */ +/* ======================================================= PDHFCS0R ======================================================== */ + #define R_PDM_CH_PDHFCS0R_HFS0_Pos (0UL) /*!< HFS0 (Bit 0) */ + #define R_PDM_CH_PDHFCS0R_HFS0_Msk (0xffffUL) /*!< HFS0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= PDHFCK1R ======================================================== */ + #define R_PDM_CH_PDHFCK1R_HFK1_Pos (0UL) /*!< HFK1 (Bit 0) */ + #define R_PDM_CH_PDHFCK1R_HFK1_Msk (0xffffUL) /*!< HFK1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== PDHFCHR ======================================================== */ + #define R_PDM_CH_PDHFCHR_HFHn_Pos (0UL) /*!< HFHn (Bit 0) */ + #define R_PDM_CH_PDHFCHR_HFHn_Msk (0xffffUL) /*!< HFHn (Bitfield-Mask: 0xffff) */ +/* ======================================================== PDCFCHR ======================================================== */ + #define R_PDM_CH_PDCFCHR_CFHn_Pos (0UL) /*!< CFHn (Bit 0) */ + #define R_PDM_CH_PDCFCHR_CFHn_Msk (0x1fffUL) /*!< CFHn (Bitfield-Mask: 0x1fff) */ +/* ====================================================== PDLFCH010R ======================================================= */ + #define R_PDM_CH_PDLFCH010R_LFH010_Pos (0UL) /*!< LFH010 (Bit 0) */ + #define R_PDM_CH_PDLFCH010R_LFH010_Msk (0x1fffUL) /*!< LFH010 (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PDLFCH1R ======================================================== */ + #define R_PDM_CH_PDLFCH1R_LFH1n_Pos (0UL) /*!< LFH1n (Bit 0) */ + #define R_PDM_CH_PDLFCH1R_LFH1n_Msk (0x1fffUL) /*!< LFH1n (Bitfield-Mask: 0x1fff) */ +/* ======================================================== PDSDLTR ======================================================== */ + #define R_PDM_CH_PDSDLTR_SDETL_Pos (0UL) /*!< SDETL (Bit 0) */ + #define R_PDM_CH_PDSDLTR_SDETL_Msk (0xfffffUL) /*!< SDETL (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDSDUTR ======================================================== */ + #define R_PDM_CH_PDSDUTR_SDETU_Pos (0UL) /*!< SDETU (Bit 0) */ + #define R_PDM_CH_PDSDUTR_SDETU_Msk (0xfffffUL) /*!< SDETU (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDDBCR ========================================================= */ + #define R_PDM_CH_PDDBCR_DATRITHR_Pos (0UL) /*!< DATRITHR (Bit 0) */ + #define R_PDM_CH_PDDBCR_DATRITHR_Msk (0x7UL) /*!< DATRITHR (Bitfield-Mask: 0x07) */ +/* ======================================================== PDSCTSR ======================================================== */ + #define R_PDM_CH_PDSCTSR_SCDL_Pos (0UL) /*!< SCDL (Bit 0) */ + #define R_PDM_CH_PDSCTSR_SCDL_Msk (0x1fffUL) /*!< SCDL (Bitfield-Mask: 0x1fff) */ + #define R_PDM_CH_PDSCTSR_SCDH_Pos (16UL) /*!< SCDH (Bit 16) */ + #define R_PDM_CH_PDSCTSR_SCDH_Msk (0x1fff0000UL) /*!< SCDH (Bitfield-Mask: 0x1fff) */ +/* ======================================================== PDOVLTR ======================================================== */ + #define R_PDM_CH_PDOVLTR_OVDL_Pos (0UL) /*!< OVDL (Bit 0) */ + #define R_PDM_CH_PDOVLTR_OVDL_Msk (0xfffffUL) /*!< OVDL (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDOVUTR ======================================================== */ + #define R_PDM_CH_PDOVUTR_OVDU_Pos (0UL) /*!< OVDU (Bit 0) */ + #define R_PDM_CH_PDOVUTR_OVDU_Msk (0xfffffUL) /*!< OVDU (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDDRCR ========================================================= */ + #define R_PDM_CH_PDDRCR_DATRE_Pos (0UL) /*!< DATRE (Bit 0) */ + #define R_PDM_CH_PDDRCR_DATRE_Msk (0x1UL) /*!< DATRE (Bitfield-Mask: 0x01) */ +/* ========================================================= PDDCR ========================================================= */ + #define R_PDM_CH_PDDCR_DATC_Pos (0UL) /*!< DATC (Bit 0) */ + #define R_PDM_CH_PDDCR_DATC_Msk (0x1UL) /*!< DATC (Bitfield-Mask: 0x01) */ +/* ========================================================= PDDRR ========================================================= */ + #define R_PDM_CH_PDDRR_DAT_Pos (0UL) /*!< DAT (Bit 0) */ + #define R_PDM_CH_PDDRR_DAT_Msk (0xfffffUL) /*!< DAT (Bitfield-Mask: 0xfffff) */ +/* ========================================================= PDDSR ========================================================= */ + #define R_PDM_CH_PDDSR_DATNUM_Pos (0UL) /*!< DATNUM (Bit 0) */ + #define R_PDM_CH_PDDSR_DATNUM_Msk (0xffUL) /*!< DATNUM (Bitfield-Mask: 0xff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARB ========================================================= */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARC ========================================================= */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARD ========================================================= */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARE ========================================================= */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSPAR ========================================================= */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFSAMON ======================================================== */ + #define R_PSCU_SFSAMON_SFS_Pos (15UL) /*!< SFS (Bit 15) */ + #define R_PSCU_SFSAMON_SFS_Msk (0xff8000UL) /*!< SFS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DADR ========================================================== */ + #define R_DAC_B0_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_B0_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DACR0 ========================================================= */ + #define R_DAC_B0_DACR0_DACEN_Pos (0UL) /*!< DACEN (Bit 0) */ + #define R_DAC_B0_DACR0_DACEN_Msk (0x1UL) /*!< DACEN (Bitfield-Mask: 0x01) */ + #define R_DAC_B0_DACR0_DAE_Pos (15UL) /*!< DAE (Bit 15) */ + #define R_DAC_B0_DACR0_DAE_Msk (0x8000UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_B0_DACR0_DAOUTDIS_Pos (31UL) /*!< DAOUTDIS (Bit 31) */ + #define R_DAC_B0_DACR0_DAOUTDIS_Msk (0x80000000UL) /*!< DAOUTDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= DACR1 ========================================================= */ + #define R_DAC_B0_DACR1_DPSEL_Pos (16UL) /*!< DPSEL (Bit 16) */ + #define R_DAC_B0_DACR1_DPSEL_Msk (0x10000UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= DACR2 ========================================================= */ + #define R_DAC_B0_DACR2_OFSSEL_Pos (8UL) /*!< OFSSEL (Bit 8) */ + #define R_DAC_B0_DACR2_OFSSEL_Msk (0x100UL) /*!< OFSSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT1_Pos (2UL) /*!< DBGSTOP_WDT1 (Bit 2) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT1_Msk (0x4UL) /*!< DBGSTOP_WDT1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_NVMERR_Pos (26UL) /*!< DBGSTOP_NVMERR (Bit 26) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_NVMERR_Msk (0x4000000UL) /*!< DBGSTOP_NVMERR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR0_Pos (28UL) /*!< DBGSTOP_CTERR0 (Bit 28) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR0_Msk (0x10000000UL) /*!< DBGSTOP_CTERR0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR1_Pos (29UL) /*!< DBGSTOP_CTERR1 (Bit 29) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR1_Msk (0x20000000UL) /*!< DBGSTOP_CTERR1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGAUTH0 ======================================================== */ + #define R_DEBUG_DBGAUTH0_DBGEN0_Pos (0UL) /*!< DBGEN0 (Bit 0) */ + #define R_DEBUG_DBGAUTH0_DBGEN0_Msk (0x1UL) /*!< DBGEN0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_DBGEN1_Pos (1UL) /*!< DBGEN1 (Bit 1) */ + #define R_DEBUG_DBGAUTH0_DBGEN1_Msk (0x2UL) /*!< DBGEN1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_NIDEN0_Pos (4UL) /*!< NIDEN0 (Bit 4) */ + #define R_DEBUG_DBGAUTH0_NIDEN0_Msk (0x10UL) /*!< NIDEN0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_NIDEN1_Pos (5UL) /*!< NIDEN1 (Bit 5) */ + #define R_DEBUG_DBGAUTH0_NIDEN1_Msk (0x20UL) /*!< NIDEN1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_DEVICEEN_Pos (16UL) /*!< DEVICEEN (Bit 16) */ + #define R_DEBUG_DBGAUTH0_DEVICEEN_Msk (0x10000UL) /*!< DEVICEEN (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_SWDBG_Pos (31UL) /*!< SWDBG (Bit 31) */ + #define R_DEBUG_DBGAUTH0_SWDBG_Msk (0x80000000UL) /*!< SWDBG (Bitfield-Mask: 0x01) */ +/* ====================================================== CACHEDBGCR ======================================================= */ + #define R_DEBUG_CACHEDBGCR_L1RSTDIS_Pos (0UL) /*!< L1RSTDIS (Bit 0) */ + #define R_DEBUG_CACHEDBGCR_L1RSTDIS_Msk (0x1UL) /*!< L1RSTDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= TRPORTCR ======================================================== */ + #define R_DEBUG_TRPORTCR_OE_Pos (0UL) /*!< OE (Bit 0) */ + #define R_DEBUG_TRPORTCR_OE_Msk (0x1UL) /*!< OE (Bitfield-Mask: 0x01) */ + #define R_DEBUG_TRPORTCR_DRV_Pos (2UL) /*!< DRV (Bit 2) */ + #define R_DEBUG_TRPORTCR_DRV_Msk (0xcUL) /*!< DRV (Bitfield-Mask: 0x03) */ + #define R_DEBUG_TRPORTCR_PORTSEL_Pos (8UL) /*!< PORTSEL (Bit 8) */ + #define R_DEBUG_TRPORTCR_PORTSEL_Msk (0x300UL) /*!< PORTSEL (Bitfield-Mask: 0x03) */ + #define R_DEBUG_TRPORTCR_SWOSEL_Pos (16UL) /*!< SWOSEL (Bit 16) */ + #define R_DEBUG_TRPORTCR_SWOSEL_Msk (0x10000UL) /*!< SWOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== ALCTRL ========================================================= */ + #define R_DEBUG_ALCTRL_AL_Pos (0UL) /*!< AL (Bit 0) */ + #define R_DEBUG_ALCTRL_AL_Msk (0xffUL) /*!< AL (Bitfield-Mask: 0xff) */ + #define R_DEBUG_ALCTRL_FAILCNT_Pos (30UL) /*!< FAILCNT (Bit 30) */ + #define R_DEBUG_ALCTRL_FAILCNT_Msk (0xc0000000UL) /*!< FAILCNT (Bitfield-Mask: 0x03) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ +/* ======================================================= TRPORTSZ ======================================================== */ + #define R_DEBUG_TRPORTSZ_PORTSIZE_Pos (0UL) /*!< PORTSIZE (Bit 0) */ + #define R_DEBUG_TRPORTSZ_PORTSIZE_Msk (0xffffffffUL) /*!< PORTSIZE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DBGNVMCR ======================================================== */ + #define R_DEBUG_DBGNVMCR_NVMWE_Pos (0UL) /*!< NVMWE (Bit 0) */ + #define R_DEBUG_DBGNVMCR_NVMWE_Msk (0x1UL) /*!< NVMWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONTROL ======================================================== */ + #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */ + #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */ + #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */ + #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */ + #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */ + #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */ + #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */ + #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */ + #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */ + #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */ + #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */ + #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */ + #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */ + #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */ + #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */ + #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */ + #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */ + #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */ + #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */ + #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */ + #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */ + #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */ + #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */ + #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */ + #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */ + #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */ + #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */ + #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */ + #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */ + #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */ + #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCTL ========================================================= */ + #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */ + #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */ + #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CACHECTL ======================================================== */ + #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */ + #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */ + #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */ + #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */ + #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */ + #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */ + #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */ + #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */ + #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */ + #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */ + #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */ + #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */ + #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */ + #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */ +/* ====================================================== HWREVISION ======================================================= */ + #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */ + #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */ + #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */ + #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */ + #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */ + #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */ + #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */ + #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */ + #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */ + #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */ +/* ======================================================== COLOR1 ========================================================= */ + #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */ + #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */ + #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */ + #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */ + #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */ +/* ======================================================== COLOR2 ========================================================= */ + #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */ + #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */ + #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */ + #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */ + #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */ +/* ======================================================== PATTERN ======================================================== */ + #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */ + #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */ +/* ======================================================== L1START ======================================================== */ + #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2START ======================================================== */ + #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3START ======================================================== */ + #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4START ======================================================== */ + #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5START ======================================================== */ + #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6START ======================================================== */ + #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1XADD ========================================================= */ + #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2XADD ========================================================= */ + #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3XADD ========================================================= */ + #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4XADD ========================================================= */ + #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5XADD ========================================================= */ + #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6XADD ========================================================= */ + #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1YADD ========================================================= */ + #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2YADD ========================================================= */ + #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3YADD ========================================================= */ + #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4YADD ========================================================= */ + #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5YADD ========================================================= */ + #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6YADD ========================================================= */ + #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1BAND ========================================================= */ + #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2BAND ========================================================= */ + #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXORIGIN ======================================================= */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXPITCH ======================================================== */ + #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */ + #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TEXMASK ======================================================== */ + #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */ + #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */ + #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */ + #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */ +/* ======================================================== LUSTART ======================================================== */ + #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */ + #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUXADD ========================================================= */ + #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */ + #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUYADD ========================================================= */ + #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */ + #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTI ======================================================== */ + #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */ + #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTF ======================================================== */ + #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */ + #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */ +/* ======================================================== LVXADDI ======================================================== */ + #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */ + #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LVYADDI ======================================================== */ + #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */ + #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVYXADDF ======================================================== */ + #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */ + #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */ + #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */ + #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */ +/* ======================================================= TEXCLADDR ======================================================= */ + #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */ + #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */ +/* ======================================================= TEXCLDATA ======================================================= */ + #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */ + #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TEXCLOFFSET ====================================================== */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== COLKEY ========================================================= */ + #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */ + #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */ + #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */ + #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */ +/* ========================================================= SIZE ========================================================== */ + #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */ + #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */ + #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */ + #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */ +/* ========================================================= PITCH ========================================================= */ + #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */ + #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */ + #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */ + #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */ +/* ======================================================== ORIGIN ========================================================= */ + #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */ + #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLISTSTART ======================================================= */ + #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */ + #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFTRIGGER ====================================================== */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== PERFCOUNT1 ======================================================= */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFCOUNT2 ======================================================= */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBWER ========================================================= */ + #define R_DRW_DBWER_BWE_Pos (2UL) /*!< BWE (Bit 2) */ + #define R_DRW_DBWER_BWE_Msk (0x4UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR_Pos (1UL) /*!< ELSEGR (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR_Msk (0x2UL) /*!< ELSEGR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARC_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARA ======================================================== */ + #define R_ELC_ELCPARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCPARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR_Pos (1UL) /*!< ELSEGR (Bit 1) */ + #define R_ELC_ELCPARA_ELSEGR_Msk (0x2UL) /*!< ELSEGR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARB ======================================================== */ + #define R_ELC_ELCPARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARC ======================================================== */ + #define R_ELC_ELCPARC_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARC_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GR1_CLUT0 ======================================================= */ + #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR1_CLUT1 ======================================================= */ + #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT0 ======================================================= */ + #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT1 ======================================================= */ + #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== GTCLKCR ======================================================== */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Pos (0UL) /*!< BPEN (Bit 0) */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Msk (0x1UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IRQCRa ========================================================= */ + #define R_ICU_IRQCRa_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCRa_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRa_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCRa_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRa_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCRa_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCRb ========================================================= */ + #define R_ICU_IRQCRb_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCRb_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRb_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCRb_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRb_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCRb_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSELR ======================================================== */ + #define R_ICU_INTSELR_IS_Pos (0UL) /*!< IS (Bit 0) */ + #define R_ICU_INTSELR_IS_Msk (0x1UL) /*!< IS (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_PVD1EN_Pos (2UL) /*!< PVD1EN (Bit 2) */ + #define R_ICU_NMIER_PVD1EN_Msk (0x4UL) /*!< PVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_PVD2EN_Pos (3UL) /*!< PVD2EN (Bit 3) */ + #define R_ICU_NMIER_PVD2EN_Msk (0x8UL) /*!< PVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SOSTEN_Pos (5UL) /*!< SOSTEN (Bit 5) */ + #define R_ICU_NMIER_SOSTEN_Msk (0x20UL) /*!< SOSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSEN_Pos (12UL) /*!< BUSEN (Bit 12) */ + #define R_ICU_NMIER_BUSEN_Msk (0x1000UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CMEN_Pos (13UL) /*!< CMEN (Bit 13) */ + #define R_ICU_NMIER_CMEN_Msk (0x2000UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LMEN_Pos (14UL) /*!< LMEN (Bit 14) */ + #define R_ICU_NMIER_LMEN_Msk (0x4000UL) /*!< LMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LUEN_Pos (15UL) /*!< LUEN (Bit 15) */ + #define R_ICU_NMIER_LUEN_Msk (0x8000UL) /*!< LUEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_FPUFLTEN_Pos (16UL) /*!< FPUFLTEN (Bit 16) */ + #define R_ICU_NMIER_FPUFLTEN_Msk (0x10000UL) /*!< FPUFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_MRCRDEN_Pos (17UL) /*!< MRCRDEN (Bit 17) */ + #define R_ICU_NMIER_MRCRDEN_Msk (0x20000UL) /*!< MRCRDEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_MRERDEN_Pos (18UL) /*!< MRERDEN (Bit 18) */ + #define R_ICU_NMIER_MRERDEN_Msk (0x40000UL) /*!< MRERDEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IPCEN_Pos (20UL) /*!< IPCEN (Bit 20) */ + #define R_ICU_NMIER_IPCEN_Msk (0x100000UL) /*!< IPCEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_PVD1CLR_Pos (2UL) /*!< PVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_PVD1CLR_Msk (0x4UL) /*!< PVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_PVD2CLR_Pos (3UL) /*!< PVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_PVD2CLR_Msk (0x8UL) /*!< PVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SOSTCLR_Pos (5UL) /*!< SOSTCLR (Bit 5) */ + #define R_ICU_NMICLR_SOSTCLR_Msk (0x20UL) /*!< SOSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSCLR_Pos (12UL) /*!< BUSCLR (Bit 12) */ + #define R_ICU_NMICLR_BUSCLR_Msk (0x1000UL) /*!< BUSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CMCLR_Pos (13UL) /*!< CMCLR (Bit 13) */ + #define R_ICU_NMICLR_CMCLR_Msk (0x2000UL) /*!< CMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LMCLR_Pos (14UL) /*!< LMCLR (Bit 14) */ + #define R_ICU_NMICLR_LMCLR_Msk (0x4000UL) /*!< LMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LUCLR_Pos (15UL) /*!< LUCLR (Bit 15) */ + #define R_ICU_NMICLR_LUCLR_Msk (0x8000UL) /*!< LUCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_FPUFLTCLR_Pos (16UL) /*!< FPUFLTCLR (Bit 16) */ + #define R_ICU_NMICLR_FPUFLTCLR_Msk (0x10000UL) /*!< FPUFLTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_MRCRDCLR_Pos (17UL) /*!< MRCRDCLR (Bit 17) */ + #define R_ICU_NMICLR_MRCRDCLR_Msk (0x20000UL) /*!< MRCRDCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_MRERDCLR_Pos (18UL) /*!< MRERDCLR (Bit 18) */ + #define R_ICU_NMICLR_MRERDCLR_Msk (0x40000UL) /*!< MRERDCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IPCCLR_Pos (20UL) /*!< IPCCLR (Bit 20) */ + #define R_ICU_NMICLR_IPCCLR_Msk (0x100000UL) /*!< IPCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_PVD1ST_Pos (2UL) /*!< PVD1ST (Bit 2) */ + #define R_ICU_NMISR_PVD1ST_Msk (0x4UL) /*!< PVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_PVD2ST_Pos (3UL) /*!< PVD2ST (Bit 3) */ + #define R_ICU_NMISR_PVD2ST_Msk (0x8UL) /*!< PVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SOSTST_Pos (5UL) /*!< SOSTST (Bit 5) */ + #define R_ICU_NMISR_SOSTST_Msk (0x20UL) /*!< SOSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_ICU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_ICU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LMST_Pos (14UL) /*!< LMST (Bit 14) */ + #define R_ICU_NMISR_LMST_Msk (0x4000UL) /*!< LMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_ICU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_FPUFLTST_Pos (16UL) /*!< FPUFLTST (Bit 16) */ + #define R_ICU_NMISR_FPUFLTST_Msk (0x10000UL) /*!< FPUFLTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_MRCRDST_Pos (17UL) /*!< MRCRDST (Bit 17) */ + #define R_ICU_NMISR_MRCRDST_Msk (0x20000UL) /*!< MRCRDST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_MRERDST_Pos (18UL) /*!< MRERDST (Bit 18) */ + #define R_ICU_NMISR_MRERDST_Msk (0x40000UL) /*!< MRERDST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IPCST_Pos (20UL) /*!< IPCST (Bit 20) */ + #define R_ICU_NMISR_IPCST_Msk (0x100000UL) /*!< IPCST (Bitfield-Mask: 0x01) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_WUPEN_Pos (16UL) /*!< WUPEN (Bit 16) */ + #define R_ICU_WUPEN_WUPEN_Msk (0x10000UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_WUPEN_Pos (0UL) /*!< WUPEN (Bit 0) */ + #define R_ICU_WUPEN1_WUPEN_Msk (0x1UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_IRQWUPEN_Pos (16UL) /*!< IRQWUPEN (Bit 16) */ + #define R_ICU_WUPEN1_IRQWUPEN_Msk (0x10000UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ===================================================== DSLPWUPIRQEN ====================================================== */ + #define R_ICU_DSLPWUPIRQEN_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ + #define R_ICU_DSLPWUPIRQEN_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x3ffUL) /*!< DELS (Bitfield-Mask: 0x3ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x3ffUL) /*!< IELS (Bitfield-Mask: 0x3ff) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMPRCR_NS ====================================================== */ + #define R_SRAM_SRAMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================= SRAMWTSC ======================================================== */ + #define R_SRAM_SRAMWTSC_WTEN_Pos (0UL) /*!< WTEN (Bit 0) */ + #define R_SRAM_SRAMWTSC_WTEN_Msk (0x1UL) /*!< WTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR0 ======================================================== */ + #define R_SRAM_SRAMCR0_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR0_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR0_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR0_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR0_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR0_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR1 ======================================================== */ + #define R_SRAM_SRAMCR1_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR1_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR1_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR1_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR1_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR1_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR1_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR1_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR2 ======================================================== */ + #define R_SRAM_SRAMCR2_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR2_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR2_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR2_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR2_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR2_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR2_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR2_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR3 ======================================================== */ + #define R_SRAM_SRAMCR3_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR3_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR3_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR3_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR3_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR3_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR3_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR3_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMECCRGN0 ====================================================== */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN1 ====================================================== */ + #define R_SRAM_SRAMECCRGN1_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN1_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN2 ====================================================== */ + #define R_SRAM_SRAMECCRGN2_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN2_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN3 ====================================================== */ + #define R_SRAM_SRAMECCRGN3_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN3_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ======================================================== SRAMESR ======================================================== */ + #define R_SRAM_SRAMESR_ERR0_Pos (0UL) /*!< ERR0 (Bit 0) */ + #define R_SRAM_SRAMESR_ERR0_Msk (0x1UL) /*!< ERR0 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR1_Pos (1UL) /*!< ERR1 (Bit 1) */ + #define R_SRAM_SRAMESR_ERR1_Msk (0x2UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMESCLR ======================================================= */ + #define R_SRAM_SRAMESCLR_CLR0_Pos (0UL) /*!< CLR0 (Bit 0) */ + #define R_SRAM_SRAMESCLR_CLR0_Msk (0x1UL) /*!< CLR0 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR1_Pos (1UL) /*!< CLR1 (Bit 1) */ + #define R_SRAM_SRAMESCLR_CLR1_Msk (0x2UL) /*!< CLR1 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMEAR00 ======================================================= */ + #define R_SRAM_SRAMEAR00_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR00_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR10 ======================================================= */ + #define R_SRAM_SRAMEAR10_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR10_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR20 ======================================================= */ + #define R_SRAM_SRAMEAR20_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR20_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR30 ======================================================= */ + #define R_SRAM_SRAMEAR30_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR30_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR01 ======================================================= */ + #define R_SRAM_SRAMEAR01_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR01_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR11 ======================================================= */ + #define R_SRAM_SRAMEAR11_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR11_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR21 ======================================================= */ + #define R_SRAM_SRAMEAR21_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR21_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR31 ======================================================= */ + #define R_SRAM_SRAMEAR31_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR31_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_OPE_Pos (6UL) /*!< OPE (Bit 6) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x40UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ========================================================= SSCR2 ========================================================= */ + #define R_SYSTEM_SSCR2_SS2FSR_Pos (0UL) /*!< SS2FSR (Bit 0) */ + #define R_SYSTEM_SSCR2_SS2FSR_Msk (0x1UL) /*!< SS2FSR (Bitfield-Mask: 0x01) */ +/* ========================================================= MRSCR ========================================================= */ + #define R_SYSTEM_MRSCR_MRSWCF_Pos (0UL) /*!< MRSWCF (Bit 0) */ + #define R_SYSTEM_MRSCR_MRSWCF_Msk (0x1UL) /*!< MRSWCF (Bitfield-Mask: 0x01) */ +/* ========================================================= VSCR ========================================================== */ + #define R_SYSTEM_VSCR_VSCM_Pos (0UL) /*!< VSCM (Bit 0) */ + #define R_SYSTEM_VSCR_VSCM_Msk (0x7UL) /*!< VSCM (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VSCR_VSCMTSF_Pos (4UL) /*!< VSCMTSF (Bit 4) */ + #define R_SYSTEM_VSCR_VSCMTSF_Msk (0x10UL) /*!< VSCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================== SRMONR ========================================================= */ + #define R_SYSTEM_SRMONR_MON_Pos (0UL) /*!< MON (Bit 0) */ + #define R_SYSTEM_SRMONR_MON_Msk (0x3UL) /*!< MON (Bitfield-Mask: 0x03) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0xfUL) /*!< PCKD (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0xf0UL) /*!< PCKC (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0xf00UL) /*!< PCKB (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0xf000UL) /*!< PCKA (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0xf0000UL) /*!< BCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Pos (20UL) /*!< PCKE (Bit 20) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Msk (0xf00000UL) /*!< PCKE (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0xf000000UL) /*!< ICK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK1_Pos (4UL) /*!< CPUCK1 (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK1_Msk (0xf0UL) /*!< CPUCK1 (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_NPUCK_Pos (8UL) /*!< NPUCK (Bit 8) */ + #define R_SYSTEM_SCKDIVCR2_NPUCK_Msk (0xf00UL) /*!< NPUCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_MRICK_Pos (12UL) /*!< MRICK (Bit 12) */ + #define R_SYSTEM_SCKDIVCR2_MRICK_Msk (0xf000UL) /*!< MRICK (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKCR_EBCKASEL_Pos (7UL) /*!< EBCKASEL (Bit 7) */ + #define R_SYSTEM_BCKCR_EBCKASEL_Msk (0x80UL) /*!< EBCKASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Pos (4UL) /*!< TRCKSEL (Bit 4) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Msk (0x10UL) /*!< TRCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== OSCMONR ======================================================== */ + #define R_SYSTEM_OSCMONR_MOCOMON_Pos (1UL) /*!< MOCOMON (Bit 1) */ + #define R_SYSTEM_OSCMONR_MOCOMON_Msk (0x2UL) /*!< MOCOMON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Pos (2UL) /*!< LOCOMON (Bit 2) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Msk (0x4UL) /*!< LOCOMON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Pos (0UL) /*!< PLODIVP (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Msk (0xfUL) /*!< PLODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos (4UL) /*!< PLODIVQ (Bit 4) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk (0xf0UL) /*!< PLODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Pos (8UL) /*!< PLODIVR (Bit 8) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Msk (0xf00UL) /*!< PLODIVR (Bitfield-Mask: 0x0f) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2CCR2 ======================================================== */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos (0UL) /*!< PL2ODIVP (Bit 0) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk (0xfUL) /*!< PL2ODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos (4UL) /*!< PL2ODIVQ (Bit 4) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk (0xf0UL) /*!< PL2ODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos (8UL) /*!< PL2ODIVR (Bit 8) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk (0xf00UL) /*!< PL2ODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCICKDIVCR ======================================================= */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCICKCR ======================================================== */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Pos (0UL) /*!< SCICKSEL (Bit 0) */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Msk (0xfUL) /*!< SCICKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SPICKDIVCR ======================================================= */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== SPICKCR ======================================================== */ + #define R_SYSTEM_SPICKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SPICKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCCKDIVCR ======================================================= */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCCKCR ======================================================== */ + #define R_SYSTEM_ADCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ADCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0xfUL) /*!< GPTCKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0xfUL) /*!< GPTCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== LCDCKDIVCR ======================================================= */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== LCDCKCR ======================================================== */ + #define R_SYSTEM_LCDCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_LCDCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0xfUL) /*!< USBCKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0xfUL) /*!< OCTACKDIV (Bitfield-Mask: 0x0f) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0xfUL) /*!< CANFDCKDIV (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0xfUL) /*!< USB60CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0xfUL) /*!< I3CCKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0xfUL) /*!< USBCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0xfUL) /*!< OCTACKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0xfUL) /*!< CANFDCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0xfUL) /*!< I3CCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCSCR ======================================================== */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos (0UL) /*!< MOSCSOKP (Bit 0) */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk (0x1UL) /*!< MOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOSCR ======================================================== */ + #define R_SYSTEM_HOCOSCR_HOSCSOKP_Pos (0UL) /*!< HOSCSOKP (Bit 0) */ + #define R_SYSTEM_HOCOSCR_HOSCSOKP_Msk (0x1UL) /*!< HOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOSCR ======================================================== */ + #define R_SYSTEM_MOCOSCR_MOCOSOKP_Pos (0UL) /*!< MOCOSOKP (Bit 0) */ + #define R_SYSTEM_MOCOSCR_MOCOSOKP_Msk (0x1UL) /*!< MOCOSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Pos (6UL) /*!< PLLMULNF (Bit 6) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Msk (0xc0UL) /*!< PLLMULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x1ff00UL) /*!< PLLMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLURF_Pos (4UL) /*!< CLURF (Bit 4) */ + #define R_SYSTEM_RSTSR1_CLURF_Msk (0x10UL) /*!< CLURF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM0RF_Pos (5UL) /*!< LM0RF (Bit 5) */ + #define R_SYSTEM_RSTSR1_LM0RF_Msk (0x20UL) /*!< LM0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CMRF_Pos (14UL) /*!< CMRF (Bit 14) */ + #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ + #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ + #define R_SYSTEM_RSTSR1_NWRF_Msk (0x400000UL) /*!< NWRF (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos (6UL) /*!< PLL2MULNF (Bit 6) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk (0xc0UL) /*!< PLL2MULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x1ff00UL) /*!< PLL2MUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SYRACCR ======================================================== */ + #define R_SYSTEM_SYRACCR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SYSTEM_SYRACCR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================= BCKADIVCR ======================================================= */ + #define R_SYSTEM_BCKADIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_BCKADIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESWCKDIVCR ======================================================= */ + #define R_SYSTEM_ESWCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESWCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESWPCKDIVCR ====================================================== */ + #define R_SYSTEM_ESWPCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESWPCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESCCKDIVCR ======================================================= */ + #define R_SYSTEM_ESCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESCCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ETHPCKDIVCR ====================================================== */ + #define R_SYSTEM_ETHPCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ETHPCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCKACR ========================================================= */ + #define R_SYSTEM_BCKACR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_BCKACR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_BCKACR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_BCKACR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKACR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_BCKACR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== ESWCKCR ======================================================== */ + #define R_SYSTEM_ESWCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESWCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESWCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESWCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESWCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESWCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= ESWPCKCR ======================================================== */ + #define R_SYSTEM_ESWPCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESWPCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESWPCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESWPCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESWPCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESWPCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== ESCCKCR ======================================================== */ + #define R_SYSTEM_ESCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= ETHPCKCR ======================================================== */ + #define R_SYSTEM_ETHPCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ETHPCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ETHPCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ETHPCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ETHPCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ETHPCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3CR1 ======================================================== */ + #define R_SYSTEM_LVD3CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD3CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD3CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD3CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4CR1 ======================================================== */ + #define R_SYSTEM_LVD4CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD4CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD4CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD4CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5CR1 ======================================================== */ + #define R_SYSTEM_LVD5CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD5CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD5CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD5CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3SR ========================================================= */ + #define R_SYSTEM_LVD3SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD3SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD3SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================= CRVSYSCR ======================================================== */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Pos (0UL) /*!< CRVEN (Bit 0) */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Msk (0x1UL) /*!< CRVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSCR ======================================================== */ + #define R_SYSTEM_CPUDSCR_PGD_Pos (0UL) /*!< PGD (Bit 0) */ + #define R_SYSTEM_CPUDSCR_PGD_Msk (0x1UL) /*!< PGD (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCTRGD ======================================================== */ + #define R_SYSTEM_PDCTRGD_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRGD_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCTRNPU ======================================================== */ + #define R_SYSTEM_PDCTRNPU_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRNPU_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRNPU_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRNPU_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRNPU_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRNPU_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCTRESWM ======================================================= */ + #define R_SYSTEM_PDCTRESWM_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRESWM_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRESWM_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRESWM_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRESWM_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRESWM_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR0 ======================================================= */ + #define R_SYSTEM_PDRAMSCR0_RKEEP_Pos (0UL) /*!< RKEEP (Bit 0) */ + #define R_SYSTEM_PDRAMSCR0_RKEEP_Msk (0x1UL) /*!< RKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR1 ======================================================= */ + #define R_SYSTEM_PDRAMSCR1_RKEEP_Pos (0UL) /*!< RKEEP (Bit 0) */ + #define R_SYSTEM_PDRAMSCR1_RKEEP_Msk (0x1UL) /*!< RKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= VBRSABAR ======================================================== */ + #define R_SYSTEM_VBRSABAR_SABA_Pos (0UL) /*!< SABA (Bit 0) */ + #define R_SYSTEM_VBRSABAR_SABA_Msk (0xffffUL) /*!< SABA (Bitfield-Mask: 0xffff) */ +/* ======================================================= VBRPABARS ======================================================= */ + #define R_SYSTEM_VBRPABARS_PABAS_Pos (0UL) /*!< PABAS (Bit 0) */ + #define R_SYSTEM_VBRPABARS_PABAS_Msk (0xffffUL) /*!< PABAS (Bitfield-Mask: 0xffff) */ +/* ====================================================== VBRPABARNS ======================================================= */ + #define R_SYSTEM_VBRPABARNS_PABANS_Pos (0UL) /*!< PABANS (Bit 0) */ + #define R_SYSTEM_VBRPABARNS_PABANS_Msk (0xffffUL) /*!< PABANS (Bitfield-Mask: 0xffff) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC5_Pos (5UL) /*!< NONSEC5 (Bit 5) */ + #define R_SYSTEM_BBFSAR_NONSEC5_Msk (0x20UL) /*!< NONSEC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC6_Pos (6UL) /*!< NONSEC6 (Bit 6) */ + #define R_SYSTEM_BBFSAR_NONSEC6_Msk (0x40UL) /*!< NONSEC6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC7_Pos (7UL) /*!< NONSEC7 (Bit 7) */ + #define R_SYSTEM_BBFSAR_NONSEC7_Msk (0x80UL) /*!< NONSEC7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_BBFSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ +/* ======================================================== PGCSAR ========================================================= */ + #define R_SYSTEM_PGCSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_PGCSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA_Pos (0UL) /*!< DPFSA (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA_Msk (0x1UL) /*!< DPFSA (Bitfield-Mask: 0x01) */ +/* ======================================================== RSCSAR ========================================================= */ + #define R_SYSTEM_RSCSAR_RSCSA_Pos (0UL) /*!< RSCSA (Bit 0) */ + #define R_SYSTEM_RSCSAR_RSCSA_Msk (0x1UL) /*!< RSCSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR1 ======================================================== */ + #define R_SYSTEM_DPFSAR1_DPFSA_Pos (0UL) /*!< DPFSA (Bit 0) */ + #define R_SYSTEM_DPFSAR1_DPFSA_Msk (0x1UL) /*!< DPFSA (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC5_Pos (5UL) /*!< PRC5 (Bit 5) */ + #define R_SYSTEM_PRCR_PRC5_Msk (0x20UL) /*!< PRC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== PRCR_NS ======================================================== */ + #define R_SYSTEM_PRCR_NS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_NS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_NS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_NS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_NS_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos (2UL) /*!< DCSSMODE (Bit 2) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk (0xcUL) /*!< DCSSMODE (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Pos (0UL) /*!< DPVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Msk (0x1UL) /*!< DPVD1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Pos (1UL) /*!< DPVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Msk (0x2UL) /*!< DPVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCIIE_Pos (2UL) /*!< DRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DRTCIIE_Msk (0x4UL) /*!< DRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD3IE_Pos (5UL) /*!< DPVD3IE (Bit 5) */ + #define R_SYSTEM_DPSIER2_DPVD3IE_Msk (0x20UL) /*!< DPVD3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Pos (2UL) /*!< DULPT0IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Msk (0x4UL) /*!< DULPT0IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Pos (3UL) /*!< DULPT1IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Msk (0x8UL) /*!< DULPT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Pos (5UL) /*!< DIWDTIE (Bit 5) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Msk (0x20UL) /*!< DIWDTIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DSOSTDIE_Pos (6UL) /*!< DSOSTDIE (Bit 6) */ + #define R_SYSTEM_DPSIER3_DSOSTDIE_Msk (0x40UL) /*!< DSOSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos (7UL) /*!< DVBATTADIE (Bit 7) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk (0x80UL) /*!< DVBATTADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos (0UL) /*!< DPVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk (0x1UL) /*!< DPVD1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos (1UL) /*!< DPVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk (0x2UL) /*!< DPVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCIIF_Pos (2UL) /*!< DRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DRTCIIF_Msk (0x4UL) /*!< DRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD3IF_Pos (5UL) /*!< DPVD3IF (Bit 5) */ + #define R_SYSTEM_DPSIFR2_DPVD3IF_Msk (0x20UL) /*!< DPVD3IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos (2UL) /*!< DULPT0IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk (0x4UL) /*!< DULPT0IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos (3UL) /*!< DULPT1IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk (0x8UL) /*!< DULPT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos (5UL) /*!< DIWDTIF (Bit 5) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk (0x20UL) /*!< DIWDTIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DSOSTDIF_Pos (6UL) /*!< DSOSTDIF (Bit 6) */ + #define R_SYSTEM_DPSIFR3_DSOSTDIF_Msk (0x40UL) /*!< DSOSTDIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos (7UL) /*!< DVBATTADIF (Bit 7) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk (0x80UL) /*!< DVBATTADIF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD3IEG_Pos (5UL) /*!< DLVD3IEG (Bit 5) */ + #define R_SYSTEM_DPSIEGR2_DLVD3IEG_Msk (0x20UL) /*!< DLVD3IEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR3 ======================================================== */ + #define R_SYSTEM_DPSIEGR3_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR3_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Pos (5UL) /*!< LVD4RF (Bit 5) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Msk (0x20UL) /*!< LVD4RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Pos (6UL) /*!< LVD5RF (Bit 6) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Msk (0x40UL) /*!< LVD5RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR3 ========================================================= */ + #define R_SYSTEM_RSTSR3_CVMRF_Pos (0UL) /*!< CVMRF (Bit 0) */ + #define R_SYSTEM_RSTSR3_CVMRF_Msk (0x1UL) /*!< CVMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR3_OCPRF_Pos (4UL) /*!< OCPRF (Bit 4) */ + #define R_SYSTEM_RSTSR3_OCPRF_Msk (0x10UL) /*!< OCPRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR3_TEMPRF_Pos (7UL) /*!< TEMPRF (Bit 7) */ + #define R_SYSTEM_RSTSR3_TEMPRF_Msk (0x80UL) /*!< TEMPRF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (1UL) /*!< MODRV0 (Bit 1) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0xeUL) /*!< MODRV0 (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD3CMPCR ======================================================= */ + #define R_SYSTEM_LVD3CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD3CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD3CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD3CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD4CMPCR ======================================================= */ + #define R_SYSTEM_LVD4CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD4CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD4CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD4CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD5CMPCR ======================================================= */ + #define R_SYSTEM_LVD5CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD5CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD5CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD5CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3CR0 ======================================================== */ + #define R_SYSTEM_LVD3CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD3CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD3CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD3CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD3CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD3CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD3CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD3CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4CR0 ======================================================== */ + #define R_SYSTEM_LVD4CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD4CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD4CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD4CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD4CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD4CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD4CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD4CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5CR0 ======================================================== */ + #define R_SYSTEM_LVD5CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD5CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD5CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD5CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD5CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD5CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD5CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD5CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR1 ======================================================== */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSCR ========================================================= */ + #define R_SYSTEM_LPSCR_LPMD_Pos (0UL) /*!< LPMD (Bit 0) */ + #define R_SYSTEM_LPSCR_LPMD_Msk (0xfUL) /*!< LPMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SSCR1 ========================================================= */ + #define R_SYSTEM_SSCR1_SS2FR_Pos (0UL) /*!< SS2FR (Bit 0) */ + #define R_SYSTEM_SSCR1_SS2FR_Msk (0x1UL) /*!< SS2FR (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SSCR1_SS2LP_Pos (2UL) /*!< SS2LP (Bit 2) */ + #define R_SYSTEM_SSCR1_SS2LP_Msk (0xcUL) /*!< SS2LP (Bitfield-Mask: 0x03) */ +/* ========================================================= SVSCR ========================================================= */ + #define R_SYSTEM_SVSCR_SVSCM_Pos (0UL) /*!< SVSCM (Bit 0) */ + #define R_SYSTEM_SVSCR_SVSCM_Msk (0x7UL) /*!< SVSCM (Bitfield-Mask: 0x07) */ +/* ========================================================= LVOCR ========================================================= */ + #define R_SYSTEM_LVOCR_LVO0E_Pos (0UL) /*!< LVO0E (Bit 0) */ + #define R_SYSTEM_LVOCR_LVO0E_Msk (0x1UL) /*!< LVO0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVOCR_LVO1E_Pos (1UL) /*!< LVO1E (Bit 1) */ + #define R_SYSTEM_LVOCR_LVO1E_Msk (0x2UL) /*!< LVO1E (Bitfield-Mask: 0x01) */ +/* ========================================================= MWMCR ========================================================= */ + #define R_SYSTEM_MWMCR_MWM_Pos (0UL) /*!< MWM (Bit 0) */ + #define R_SYSTEM_MWMCR_MWM_Msk (0x3UL) /*!< MWM (Bitfield-Mask: 0x03) */ +/* ======================================================= SYRSTMSK0 ======================================================= */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos (0UL) /*!< IWDTMASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk (0x1UL) /*!< IWDTMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos (1UL) /*!< WDT0MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk (0x2UL) /*!< WDT0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos (2UL) /*!< SWMASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk (0x4UL) /*!< SWMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CLU0MASK_Pos (4UL) /*!< CLU0MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK0_CLU0MASK_Msk (0x10UL) /*!< CLU0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos (5UL) /*!< LM0MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk (0x20UL) /*!< LM0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos (6UL) /*!< CMMASK (Bit 6) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk (0x40UL) /*!< CMMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK1 ======================================================= */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_CLU1MASK_Pos (4UL) /*!< CLU1MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK1_CLU1MASK_Msk (0x10UL) /*!< CLU1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK2 ======================================================= */ + #define R_SYSTEM_SYRSTMSK2_PVD1MASK_Pos (0UL) /*!< PVD1MASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK2_PVD1MASK_Msk (0x1UL) /*!< PVD1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_PVD2MASK_Pos (1UL) /*!< PVD2MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK2_PVD2MASK_Msk (0x2UL) /*!< PVD2MASK (Bitfield-Mask: 0x01) */ +/* ======================================================== TEMPRCR ======================================================== */ + #define R_SYSTEM_TEMPRCR_TEMPREN_Pos (0UL) /*!< TEMPREN (Bit 0) */ + #define R_SYSTEM_TEMPRCR_TEMPREN_Msk (0x1UL) /*!< TEMPREN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_TSNEN_Pos (1UL) /*!< TSNEN (Bit 1) */ + #define R_SYSTEM_TEMPRCR_TSNEN_Msk (0x2UL) /*!< TSNEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_CMPEN_Pos (2UL) /*!< CMPEN (Bit 2) */ + #define R_SYSTEM_TEMPRCR_CMPEN_Msk (0x4UL) /*!< CMPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_TSNKEEP_Pos (3UL) /*!< TSNKEEP (Bit 3) */ + #define R_SYSTEM_TEMPRCR_TSNKEEP_Msk (0x8UL) /*!< TSNKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== TEMPRLR ======================================================== */ + #define R_SYSTEM_TEMPRLR_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_SYSTEM_TEMPRLR_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL1LDOCR ======================================================= */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2LDOCR ======================================================= */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= HOCOLDOCR ======================================================= */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOMCR2 ========================================================= */ + #define R_SYSTEM_MOMCR2_MOMODE_Pos (0UL) /*!< MOMODE (Bit 0) */ + #define R_SYSTEM_MOMCR2_MOMODE_Msk (0x1UL) /*!< MOMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1FCR ======================================================== */ + #define R_SYSTEM_LVD1FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD1FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2FCR ======================================================== */ + #define R_SYSTEM_LVD2FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD2FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3FCR ======================================================== */ + #define R_SYSTEM_LVD3FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD3FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4FCR ======================================================== */ + #define R_SYSTEM_LVD4FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD4FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5FCR ======================================================== */ + #define R_SYSTEM_LVD5FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD5FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= PVDLR ========================================================= */ + #define R_SYSTEM_PVDLR_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_SYSTEM_PVDLR_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER4 ======================================================== */ + #define R_SYSTEM_DPSIER4_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER4_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER5 ======================================================== */ + #define R_SYSTEM_DPSIER5_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER5_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR4 ======================================================== */ + #define R_SYSTEM_DPSIFR4_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR4_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR5 ======================================================== */ + #define R_SYSTEM_DPSIFR5_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR5_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR4 ======================================================== */ + #define R_SYSTEM_DPSIEGR4_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR4_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTSWMON ======================================================== */ + #define R_SYSTEM_VBTSWMON_VLVLMON_Pos (0UL) /*!< VLVLMON (Bit 0) */ + #define R_SYSTEM_VBTSWMON_VLVLMON_Msk (0x7UL) /*!< VLVLMON (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTSWMON_VDETEMON_Pos (4UL) /*!< VDETEMON (Bit 4) */ + #define R_SYSTEM_VBTSWMON_VDETEMON_Msk (0x10UL) /*!< VDETEMON (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTSWSCR ======================================================== */ + #define R_SYSTEM_VBTSWSCR_VBTSWE_Pos (0UL) /*!< VBTSWE (Bit 0) */ + #define R_SYSTEM_VBTSWSCR_VBTSWE_Msk (0x1UL) /*!< VBTSWE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_SOMCR_SOSEL_Pos (6UL) /*!< SOSEL (Bit 6) */ + #define R_SYSTEM_SOMCR_SOSEL_Msk (0x40UL) /*!< SOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSTDCR ======================================================== */ + #define R_SYSTEM_SOSTDCR_SOSTDIE_Pos (0UL) /*!< SOSTDIE (Bit 0) */ + #define R_SYSTEM_SOSTDCR_SOSTDIE_Msk (0x1UL) /*!< SOSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOSTDCR_SOSTDE_Pos (7UL) /*!< SOSTDE (Bit 7) */ + #define R_SYSTEM_SOSTDCR_SOSTDE_Msk (0x80UL) /*!< SOSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSTDSR ======================================================== */ + #define R_SYSTEM_SOSTDSR_SOSTDF_Pos (0UL) /*!< SOSTDF (Bit 0) */ + #define R_SYSTEM_SOSTDSR_SOSTDF_Msk (0x1UL) /*!< SOSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR2 ======================================================== */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos (0UL) /*!< VDETLVL (Bit 0) */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk (0x7UL) /*!< VDETLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Pos (4UL) /*!< VDETE (Bit 4) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Msk (0x10UL) /*!< VDETE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBPSR ======================================================== */ + #define R_SYSTEM_VBTBPSR_VBPORF_Pos (0UL) /*!< VBPORF (Bit 0) */ + #define R_SYSTEM_VBTBPSR_VBPORF_Msk (0x1UL) /*!< VBPORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Pos (4UL) /*!< VBPORM (Bit 4) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Msk (0x10UL) /*!< VBPORM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Pos (5UL) /*!< BPWSWM (Bit 5) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Msk (0x20UL) /*!< BPWSWM (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTADSR ======================================================== */ + #define R_SYSTEM_VBTADSR_VBTADF0_Pos (0UL) /*!< VBTADF0 (Bit 0) */ + #define R_SYSTEM_VBTADSR_VBTADF0_Msk (0x1UL) /*!< VBTADF0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Pos (1UL) /*!< VBTADF1 (Bit 1) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Msk (0x2UL) /*!< VBTADF1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Pos (2UL) /*!< VBTADF2 (Bit 2) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Msk (0x4UL) /*!< VBTADF2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR1 ======================================================== */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos (0UL) /*!< VBTADIE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk (0x1UL) /*!< VBTADIE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos (1UL) /*!< VBTADIE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk (0x2UL) /*!< VBTADIE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos (2UL) /*!< VBTADIE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk (0x4UL) /*!< VBTADIE2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos (4UL) /*!< VBTADCLE0 (Bit 4) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk (0x10UL) /*!< VBTADCLE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos (5UL) /*!< VBTADCLE1 (Bit 5) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk (0x20UL) /*!< VBTADCLE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos (6UL) /*!< VBTADCLE2 (Bit 6) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk (0x40UL) /*!< VBTADCLE2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR2 ======================================================== */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos (0UL) /*!< VBRTCES0 (Bit 0) */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk (0x1UL) /*!< VBRTCES0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos (1UL) /*!< VBRTCES1 (Bit 1) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk (0x2UL) /*!< VBRTCES1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos (2UL) /*!< VBRTCES2 (Bit 2) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk (0x4UL) /*!< VBRTCES2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR2 ======================================================= */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos (0UL) /*!< VCH0NCE (Bit 0) */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk (0x1UL) /*!< VCH0NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos (1UL) /*!< VCH1NCE (Bit 1) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk (0x2UL) /*!< VCH1NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos (2UL) /*!< VCH2NCE (Bit 2) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk (0x4UL) /*!< VCH2NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos (4UL) /*!< VCH0EG (Bit 4) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk (0x10UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos (5UL) /*!< VCH1EG (Bit 5) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk (0x20UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos (6UL) /*!< VCH2EG (Bit 6) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk (0x40UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTIMONR ======================================================== */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Pos (0UL) /*!< VCH0MON (Bit 0) */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Msk (0x1UL) /*!< VCH0MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Pos (1UL) /*!< VCH1MON (Bit 1) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Msk (0x2UL) /*!< VCH1MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Pos (2UL) /*!< VCH2MON (Bit 2) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Msk (0x4UL) /*!< VCH2MON (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTNCWCR ======================================================== */ + #define R_SYSTEM_VBTNCWCR_VINCW_Pos (0UL) /*!< VINCW (Bit 0) */ + #define R_SYSTEM_VBTNCWCR_VINCW_Msk (0x7UL) /*!< VINCW (Bitfield-Mask: 0x07) */ +/* ======================================================= VBTADCR3 ======================================================== */ + #define R_SYSTEM_VBTADCR3_VBTADZE0_Pos (0UL) /*!< VBTADZE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR3_VBTADZE0_Msk (0x1UL) /*!< VBTADZE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR3_VBTADZE1_Pos (1UL) /*!< VBTADZE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR3_VBTADZE1_Msk (0x2UL) /*!< VBTADZE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR3_VBTADZE2_Pos (2UL) /*!< VBTADZE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR3_VBTADZE2_Msk (0x4UL) /*!< VBTADZE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_VIN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MC =========================================================== */ + #define R_VIN_MC_ME_Pos (0UL) /*!< ME (Bit 0) */ + #define R_VIN_MC_ME_Msk (0x1UL) /*!< ME (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_BPS_Pos (1UL) /*!< BPS (Bit 1) */ + #define R_VIN_MC_BPS_Msk (0x2UL) /*!< BPS (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_IM_Pos (3UL) /*!< IM (Bit 3) */ + #define R_VIN_MC_IM_Msk (0x18UL) /*!< IM (Bitfield-Mask: 0x03) */ + #define R_VIN_MC_EN_Pos (6UL) /*!< EN (Bit 6) */ + #define R_VIN_MC_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_DC_Pos (14UL) /*!< DC (Bit 14) */ + #define R_VIN_MC_DC_Msk (0xc000UL) /*!< DC (Bitfield-Mask: 0x03) */ + #define R_VIN_MC_INF_Pos (16UL) /*!< INF (Bit 16) */ + #define R_VIN_MC_INF_Msk (0x70000UL) /*!< INF (Bitfield-Mask: 0x07) */ + #define R_VIN_MC_LUTE_Pos (20UL) /*!< LUTE (Bit 20) */ + #define R_VIN_MC_LUTE_Msk (0x100000UL) /*!< LUTE (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_ST_Pos (22UL) /*!< ST (Bit 22) */ + #define R_VIN_MC_ST_Msk (0x400000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_DC2_Pos (24UL) /*!< DC2 (Bit 24) */ + #define R_VIN_MC_DC2_Msk (0x1000000UL) /*!< DC2 (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_YUV444_Pos (25UL) /*!< YUV444 (Bit 25) */ + #define R_VIN_MC_YUV444_Msk (0x2000000UL) /*!< YUV444 (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_SCLE_Pos (26UL) /*!< SCLE (Bit 26) */ + #define R_VIN_MC_SCLE_Msk (0x4000000UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_CLP_Pos (28UL) /*!< CLP (Bit 28) */ + #define R_VIN_MC_CLP_Msk (0x30000000UL) /*!< CLP (Bitfield-Mask: 0x03) */ +/* ========================================================== MS =========================================================== */ + #define R_VIN_MS_CA_Pos (0UL) /*!< CA (Bit 0) */ + #define R_VIN_MS_CA_Msk (0x1UL) /*!< CA (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_AV_Pos (1UL) /*!< AV (Bit 1) */ + #define R_VIN_MS_AV_Msk (0x2UL) /*!< AV (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FS_Pos (2UL) /*!< FS (Bit 2) */ + #define R_VIN_MS_FS_Msk (0x4UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FBS_Pos (3UL) /*!< FBS (Bit 3) */ + #define R_VIN_MS_FBS_Msk (0x18UL) /*!< FBS (Bitfield-Mask: 0x03) */ + #define R_VIN_MS_MA_Pos (16UL) /*!< MA (Bit 16) */ + #define R_VIN_MS_MA_Msk (0x10000UL) /*!< MA (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FMS_Pos (19UL) /*!< FMS (Bit 19) */ + #define R_VIN_MS_FMS_Msk (0x180000UL) /*!< FMS (Bitfield-Mask: 0x03) */ +/* ========================================================== FC =========================================================== */ + #define R_VIN_FC_CC_Pos (1UL) /*!< CC (Bit 1) */ + #define R_VIN_FC_CC_Msk (0x2UL) /*!< CC (Bitfield-Mask: 0x01) */ +/* ========================================================= SLPRC ========================================================= */ + #define R_VIN_SLPRC_SLPRC_Pos (0UL) /*!< SLPRC (Bit 0) */ + #define R_VIN_SLPRC_SLPRC_Msk (0xfffUL) /*!< SLPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= ELPRC ========================================================= */ + #define R_VIN_ELPRC_ELPRC_Pos (0UL) /*!< ELPRC (Bit 0) */ + #define R_VIN_ELPRC_ELPRC_Msk (0xfffUL) /*!< ELPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= SPPRC ========================================================= */ + #define R_VIN_SPPRC_SPPRC_Pos (0UL) /*!< SPPRC (Bit 0) */ + #define R_VIN_SPPRC_SPPRC_Msk (0xfffUL) /*!< SPPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= EPPRC ========================================================= */ + #define R_VIN_EPPRC_EPPRC_Pos (0UL) /*!< EPPRC (Bit 0) */ + #define R_VIN_EPPRC_EPPRC_Msk (0xfffUL) /*!< EPPRC (Bitfield-Mask: 0xfff) */ +/* ======================================================= CSI_IFMD ======================================================== */ + #define R_VIN_CSI_IFMD_VC_SEL_Pos (0UL) /*!< VC_SEL (Bit 0) */ + #define R_VIN_CSI_IFMD_VC_SEL_Msk (0xfUL) /*!< VC_SEL (Bitfield-Mask: 0x0f) */ + #define R_VIN_CSI_IFMD_DT_Pos (8UL) /*!< DT (Bit 8) */ + #define R_VIN_CSI_IFMD_DT_Msk (0x3f00UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_VIN_CSI_IFMD_DES0_Pos (25UL) /*!< DES0 (Bit 25) */ + #define R_VIN_CSI_IFMD_DES0_Msk (0x2000000UL) /*!< DES0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CSIFLD ========================================================= */ + #define R_VIN_CSIFLD_FLD_EN_Pos (0UL) /*!< FLD_EN (Bit 0) */ + #define R_VIN_CSIFLD_FLD_EN_Msk (0x1UL) /*!< FLD_EN (Bitfield-Mask: 0x01) */ + #define R_VIN_CSIFLD_FLD_SEL_Pos (4UL) /*!< FLD_SEL (Bit 4) */ + #define R_VIN_CSIFLD_FLD_SEL_Msk (0x30UL) /*!< FLD_SEL (Bitfield-Mask: 0x03) */ + #define R_VIN_CSIFLD_FLD_NUM_Pos (16UL) /*!< FLD_NUM (Bit 16) */ + #define R_VIN_CSIFLD_FLD_NUM_Msk (0x10000UL) /*!< FLD_NUM (Bitfield-Mask: 0x01) */ +/* ========================================================== IS =========================================================== */ + #define R_VIN_IS_IS_Pos (0UL) /*!< IS (Bit 0) */ + #define R_VIN_IS_IS_Msk (0x1fffUL) /*!< IS (Bitfield-Mask: 0x1fff) */ +/* ========================================================== MB1 ========================================================== */ + #define R_VIN_MB1_MB1_Pos (7UL) /*!< MB1 (Bit 7) */ + #define R_VIN_MB1_MB1_Msk (0xffffff80UL) /*!< MB1 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== MB2 ========================================================== */ + #define R_VIN_MB2_MB2_Pos (7UL) /*!< MB2 (Bit 7) */ + #define R_VIN_MB2_MB2_Msk (0xffffff80UL) /*!< MB2 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== MB3 ========================================================== */ + #define R_VIN_MB3_MB3_Pos (7UL) /*!< MB3 (Bit 7) */ + #define R_VIN_MB3_MB3_Msk (0xffffff80UL) /*!< MB3 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== LC =========================================================== */ + #define R_VIN_LC_LC_Pos (0UL) /*!< LC (Bit 0) */ + #define R_VIN_LC_LC_Msk (0xfffUL) /*!< LC (Bitfield-Mask: 0xfff) */ +/* ========================================================== IE =========================================================== */ + #define R_VIN_IE_FOE_Pos (0UL) /*!< FOE (Bit 0) */ + #define R_VIN_IE_FOE_Msk (0x1UL) /*!< FOE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_EFE_Pos (1UL) /*!< EFE (Bit 1) */ + #define R_VIN_IE_EFE_Msk (0x2UL) /*!< EFE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_SIE_Pos (2UL) /*!< SIE (Bit 2) */ + #define R_VIN_IE_SIE_Msk (0x4UL) /*!< SIE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FIE_Pos (4UL) /*!< FIE (Bit 4) */ + #define R_VIN_IE_FIE_Msk (0x10UL) /*!< FIE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FME_Pos (5UL) /*!< FME (Bit 5) */ + #define R_VIN_IE_FME_Msk (0x20UL) /*!< FME (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_PRCLIPHEE_Pos (8UL) /*!< PRCLIPHEE (Bit 8) */ + #define R_VIN_IE_PRCLIPHEE_Msk (0x100UL) /*!< PRCLIPHEE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_PRCLIPVEE_Pos (9UL) /*!< PRCLIPVEE (Bit 9) */ + #define R_VIN_IE_PRCLIPVEE_Msk (0x200UL) /*!< PRCLIPVEE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_ROE_Pos (14UL) /*!< ROE (Bit 14) */ + #define R_VIN_IE_ROE_Msk (0x4000UL) /*!< ROE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_AREE_Pos (15UL) /*!< AREE (Bit 15) */ + #define R_VIN_IE_AREE_Msk (0x8000UL) /*!< AREE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_VRE_Pos (16UL) /*!< VRE (Bit 16) */ + #define R_VIN_IE_VRE_Msk (0x10000UL) /*!< VRE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_VFE_Pos (17UL) /*!< VFE (Bit 17) */ + #define R_VIN_IE_VFE_Msk (0x20000UL) /*!< VFE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FIE2_Pos (31UL) /*!< FIE2 (Bit 31) */ + #define R_VIN_IE_FIE2_Msk (0x80000000UL) /*!< FIE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ + #define R_VIN_INTS_FOS_Pos (0UL) /*!< FOS (Bit 0) */ + #define R_VIN_INTS_FOS_Msk (0x1UL) /*!< FOS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_EFS_Pos (1UL) /*!< EFS (Bit 1) */ + #define R_VIN_INTS_EFS_Msk (0x2UL) /*!< EFS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_SIS_Pos (2UL) /*!< SIS (Bit 2) */ + #define R_VIN_INTS_SIS_Msk (0x4UL) /*!< SIS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FIS_Pos (4UL) /*!< FIS (Bit 4) */ + #define R_VIN_INTS_FIS_Msk (0x10UL) /*!< FIS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FMS_Pos (5UL) /*!< FMS (Bit 5) */ + #define R_VIN_INTS_FMS_Msk (0x20UL) /*!< FMS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_PRCLIPHES_Pos (8UL) /*!< PRCLIPHES (Bit 8) */ + #define R_VIN_INTS_PRCLIPHES_Msk (0x100UL) /*!< PRCLIPHES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_PRCLIPVES_Pos (9UL) /*!< PRCLIPVES (Bit 9) */ + #define R_VIN_INTS_PRCLIPVES_Msk (0x200UL) /*!< PRCLIPVES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_ROS_Pos (14UL) /*!< ROS (Bit 14) */ + #define R_VIN_INTS_ROS_Msk (0x4000UL) /*!< ROS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_ARES_Pos (15UL) /*!< ARES (Bit 15) */ + #define R_VIN_INTS_ARES_Msk (0x8000UL) /*!< ARES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_VRS_Pos (16UL) /*!< VRS (Bit 16) */ + #define R_VIN_INTS_VRS_Msk (0x10000UL) /*!< VRS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_VFS_Pos (17UL) /*!< VFS (Bit 17) */ + #define R_VIN_INTS_VFS_Msk (0x20000UL) /*!< VFS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FIS2_Pos (31UL) /*!< FIS2 (Bit 31) */ + #define R_VIN_INTS_FIS2_Msk (0x80000000UL) /*!< FIS2 (Bitfield-Mask: 0x01) */ +/* ========================================================== SI =========================================================== */ + #define R_VIN_SI_SI_Pos (0UL) /*!< SI (Bit 0) */ + #define R_VIN_SI_SI_Msk (0xfffUL) /*!< SI (Bitfield-Mask: 0xfff) */ +/* ======================================================== MTCSTOP ======================================================== */ + #define R_VIN_MTCSTOP_STOPREQ_Pos (0UL) /*!< STOPREQ (Bit 0) */ + #define R_VIN_MTCSTOP_STOPREQ_Msk (0x1UL) /*!< STOPREQ (Bitfield-Mask: 0x01) */ + #define R_VIN_MTCSTOP_STOPACK_Pos (1UL) /*!< STOPACK (Bit 1) */ + #define R_VIN_MTCSTOP_STOPACK_Msk (0x2UL) /*!< STOPACK (Bitfield-Mask: 0x01) */ + #define R_VIN_MTCSTOP_OUTSTAND_Pos (16UL) /*!< OUTSTAND (Bit 16) */ + #define R_VIN_MTCSTOP_OUTSTAND_Msk (0x3f0000UL) /*!< OUTSTAND (Bitfield-Mask: 0x3f) */ +/* ========================================================== DMR ========================================================== */ + #define R_VIN_DMR_DTMD_Pos (0UL) /*!< DTMD (Bit 0) */ + #define R_VIN_DMR_DTMD_Msk (0x3UL) /*!< DTMD (Bitfield-Mask: 0x03) */ + #define R_VIN_DMR_ABIT_Pos (2UL) /*!< ABIT (Bit 2) */ + #define R_VIN_DMR_ABIT_Msk (0x4UL) /*!< ABIT (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_BPSM_Pos (4UL) /*!< BPSM (Bit 4) */ + #define R_VIN_DMR_BPSM_Msk (0x10UL) /*!< BPSM (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_EXRGB_Pos (8UL) /*!< EXRGB (Bit 8) */ + #define R_VIN_DMR_EXRGB_Msk (0x100UL) /*!< EXRGB (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_YC_THR_Pos (11UL) /*!< YC_THR (Bit 11) */ + #define R_VIN_DMR_YC_THR_Msk (0x800UL) /*!< YC_THR (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_YMODE_Pos (12UL) /*!< YMODE (Bit 12) */ + #define R_VIN_DMR_YMODE_Msk (0x7000UL) /*!< YMODE (Bitfield-Mask: 0x07) */ + #define R_VIN_DMR_A8BIT_Pos (24UL) /*!< A8BIT (Bit 24) */ + #define R_VIN_DMR_A8BIT_Msk (0xff000000UL) /*!< A8BIT (Bitfield-Mask: 0xff) */ +/* ========================================================= UVAOF ========================================================= */ + #define R_VIN_UVAOF_UVAOF_Pos (7UL) /*!< UVAOF (Bit 7) */ + #define R_VIN_UVAOF_UVAOF_Msk (0xffffff80UL) /*!< UVAOF (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================= CSCE1 ========================================================= */ + #define R_VIN_CSCE1_YMUL2_Pos (0UL) /*!< YMUL2 (Bit 0) */ + #define R_VIN_CSCE1_YMUL2_Msk (0x3fffUL) /*!< YMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE1_ROUND_Pos (16UL) /*!< ROUND (Bit 16) */ + #define R_VIN_CSCE1_ROUND_Msk (0x10000UL) /*!< ROUND (Bitfield-Mask: 0x01) */ +/* ========================================================= CSCE2 ========================================================= */ + #define R_VIN_CSCE2_CSUB2_Pos (0UL) /*!< CSUB2 (Bit 0) */ + #define R_VIN_CSCE2_CSUB2_Msk (0xfffUL) /*!< CSUB2 (Bitfield-Mask: 0xfff) */ + #define R_VIN_CSCE2_YSUB2_Pos (16UL) /*!< YSUB2 (Bit 16) */ + #define R_VIN_CSCE2_YSUB2_Msk (0xfff0000UL) /*!< YSUB2 (Bitfield-Mask: 0xfff) */ +/* ========================================================= CSCE3 ========================================================= */ + #define R_VIN_CSCE3_GCRMUL2_Pos (0UL) /*!< GCRMUL2 (Bit 0) */ + #define R_VIN_CSCE3_GCRMUL2_Msk (0x3fffUL) /*!< GCRMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE3_RCRMUL2_Pos (16UL) /*!< RCRMUL2 (Bit 16) */ + #define R_VIN_CSCE3_RCRMUL2_Msk (0x3fff0000UL) /*!< RCRMUL2 (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CSCE4 ========================================================= */ + #define R_VIN_CSCE4_BCBMUL2_Pos (0UL) /*!< BCBMUL2 (Bit 0) */ + #define R_VIN_CSCE4_BCBMUL2_Msk (0x3fffUL) /*!< BCBMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE4_GCBMUL2_Pos (16UL) /*!< GCBMUL2 (Bit 16) */ + #define R_VIN_CSCE4_GCBMUL2_Msk (0x3fff0000UL) /*!< GCBMUL2 (Bitfield-Mask: 0x3fff) */ +/* ======================================================= UDS_CTRL ======================================================== */ + #define R_VIN_UDS_CTRL_NE_BCB_Pos (16UL) /*!< NE_BCB (Bit 16) */ + #define R_VIN_UDS_CTRL_NE_BCB_Msk (0x10000UL) /*!< NE_BCB (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_NE_GY_Pos (17UL) /*!< NE_GY (Bit 17) */ + #define R_VIN_UDS_CTRL_NE_GY_Msk (0x20000UL) /*!< NE_GY (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_NE_RCR_Pos (18UL) /*!< NE_RCR (Bit 18) */ + #define R_VIN_UDS_CTRL_NE_RCR_Msk (0x40000UL) /*!< NE_RCR (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_BC_Pos (20UL) /*!< BC (Bit 20) */ + #define R_VIN_UDS_CTRL_BC_Msk (0x100000UL) /*!< BC (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_BLADV_Pos (28UL) /*!< BLADV (Bit 28) */ + #define R_VIN_UDS_CTRL_BLADV_Msk (0x10000000UL) /*!< BLADV (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_AMD_Pos (30UL) /*!< AMD (Bit 30) */ + #define R_VIN_UDS_CTRL_AMD_Msk (0x40000000UL) /*!< AMD (Bitfield-Mask: 0x01) */ +/* ======================================================= UDS_SCALE ======================================================= */ + #define R_VIN_UDS_SCALE_VFRAC_Pos (0UL) /*!< VFRAC (Bit 0) */ + #define R_VIN_UDS_SCALE_VFRAC_Msk (0xfffUL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_SCALE_VMANT_Pos (12UL) /*!< VMANT (Bit 12) */ + #define R_VIN_UDS_SCALE_VMANT_Msk (0xf000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ + #define R_VIN_UDS_SCALE_HFRAC_Pos (16UL) /*!< HFRAC (Bit 16) */ + #define R_VIN_UDS_SCALE_HFRAC_Msk (0xfff0000UL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_SCALE_HMANT_Pos (28UL) /*!< HMANT (Bit 28) */ + #define R_VIN_UDS_SCALE_HMANT_Msk (0xf0000000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ +/* ==================================================== UDS_PASS_BWIDTH ==================================================== */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_V_Pos (0UL) /*!< BWIDTH_V (Bit 0) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_V_Msk (0x7fUL) /*!< BWIDTH_V (Bitfield-Mask: 0x7f) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_H_Pos (16UL) /*!< BWIDTH_H (Bit 16) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_H_Msk (0x7f0000UL) /*!< BWIDTH_H (Bitfield-Mask: 0x7f) */ +/* ===================================================== UDS_CLIP_SIZE ===================================================== */ + #define R_VIN_UDS_CLIP_SIZE_CL_VSIZE_Pos (0UL) /*!< CL_VSIZE (Bit 0) */ + #define R_VIN_UDS_CLIP_SIZE_CL_VSIZE_Msk (0xfffUL) /*!< CL_VSIZE (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_CLIP_SIZE_CL_HSIZE_Pos (16UL) /*!< CL_HSIZE (Bit 16) */ + #define R_VIN_UDS_CLIP_SIZE_CL_HSIZE_Msk (0xfff0000UL) /*!< CL_HSIZE (Bitfield-Mask: 0xfff) */ +/* ========================================================= LUTP ========================================================== */ + #define R_VIN_LUTP_LTCRPR_Pos (0UL) /*!< LTCRPR (Bit 0) */ + #define R_VIN_LUTP_LTCRPR_Msk (0x3ffUL) /*!< LTCRPR (Bitfield-Mask: 0x3ff) */ + #define R_VIN_LUTP_LTCBPR_Pos (10UL) /*!< LTCBPR (Bit 10) */ + #define R_VIN_LUTP_LTCBPR_Msk (0xffc00UL) /*!< LTCBPR (Bitfield-Mask: 0x3ff) */ + #define R_VIN_LUTP_LTYPR_Pos (20UL) /*!< LTYPR (Bit 20) */ + #define R_VIN_LUTP_LTYPR_Msk (0x3ff00000UL) /*!< LTYPR (Bitfield-Mask: 0x3ff) */ +/* ========================================================= LUTD ========================================================== */ + #define R_VIN_LUTD_LTCRDT_Pos (0UL) /*!< LTCRDT (Bit 0) */ + #define R_VIN_LUTD_LTCRDT_Msk (0xffUL) /*!< LTCRDT (Bitfield-Mask: 0xff) */ + #define R_VIN_LUTD_LTCBDT_Pos (8UL) /*!< LTCBDT (Bit 8) */ + #define R_VIN_LUTD_LTCBDT_Msk (0xff00UL) /*!< LTCBDT (Bitfield-Mask: 0xff) */ + #define R_VIN_LUTD_LTYDT_Pos (16UL) /*!< LTYDT (Bit 16) */ + #define R_VIN_LUTD_LTYDT_Msk (0xff0000UL) /*!< LTYDT (Bitfield-Mask: 0xff) */ +/* ========================================================= YCCR1 ========================================================= */ + #define R_VIN_YCCR1_YCLRP_Pos (0UL) /*!< YCLRP (Bit 0) */ + #define R_VIN_YCCR1_YCLRP_Msk (0x1fffUL) /*!< YCLRP (Bitfield-Mask: 0x1fff) */ +/* ========================================================= YCCR2 ========================================================= */ + #define R_VIN_YCCR2_YCLGP_Pos (0UL) /*!< YCLGP (Bit 0) */ + #define R_VIN_YCCR2_YCLGP_Msk (0x1fffUL) /*!< YCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_YCCR2_YCLBP_Pos (16UL) /*!< YCLBP (Bit 16) */ + #define R_VIN_YCCR2_YCLBP_Msk (0x1fff0000UL) /*!< YCLBP (Bitfield-Mask: 0x1fff) */ +/* ========================================================= YCCR3 ========================================================= */ + #define R_VIN_YCCR3_YCLAP_Pos (0UL) /*!< YCLAP (Bit 0) */ + #define R_VIN_YCCR3_YCLAP_Msk (0xfffUL) /*!< YCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_YCCR3_YCLHEN_Pos (23UL) /*!< YCLHEN (Bit 23) */ + #define R_VIN_YCCR3_YCLHEN_Msk (0x800000UL) /*!< YCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_YCCR3_YCLSFT_Pos (24UL) /*!< YCLSFT (Bit 24) */ + #define R_VIN_YCCR3_YCLSFT_Msk (0x1f000000UL) /*!< YCLSFT (Bitfield-Mask: 0x1f) */ +/* ======================================================== CBCCR1 ========================================================= */ + #define R_VIN_CBCCR1_CBCLRP_Pos (0UL) /*!< CBCLRP (Bit 0) */ + #define R_VIN_CBCCR1_CBCLRP_Msk (0x1fffUL) /*!< CBCLRP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CBCCR2 ========================================================= */ + #define R_VIN_CBCCR2_CBCLGP_Pos (0UL) /*!< CBCLGP (Bit 0) */ + #define R_VIN_CBCCR2_CBCLGP_Msk (0x1fffUL) /*!< CBCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_CBCCR2_CBCLBP_Pos (16UL) /*!< CBCLBP (Bit 16) */ + #define R_VIN_CBCCR2_CBCLBP_Msk (0x1fff0000UL) /*!< CBCLBP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CBCCR3 ========================================================= */ + #define R_VIN_CBCCR3_CBCLAP_Pos (0UL) /*!< CBCLAP (Bit 0) */ + #define R_VIN_CBCCR3_CBCLAP_Msk (0xfffUL) /*!< CBCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_CBCCR3_CBCLHEN_Pos (23UL) /*!< CBCLHEN (Bit 23) */ + #define R_VIN_CBCCR3_CBCLHEN_Msk (0x800000UL) /*!< CBCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_CBCCR3_CBCLSFT_Pos (24UL) /*!< CBCLSFT (Bit 24) */ + #define R_VIN_CBCCR3_CBCLSFT_Msk (0x1f000000UL) /*!< CBCLSFT (Bitfield-Mask: 0x1f) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_VIN_CRCCR1_CRCLRP_Pos (0UL) /*!< CRCLRP (Bit 0) */ + #define R_VIN_CRCCR1_CRCLRP_Msk (0x1fffUL) /*!< CRCLRP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CRCCR2 ========================================================= */ + #define R_VIN_CRCCR2_CRCLGP_Pos (0UL) /*!< CRCLGP (Bit 0) */ + #define R_VIN_CRCCR2_CRCLGP_Msk (0x1fffUL) /*!< CRCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_CRCCR2_CRCLBP_Pos (16UL) /*!< CRCLBP (Bit 16) */ + #define R_VIN_CRCCR2_CRCLBP_Msk (0x1fff0000UL) /*!< CRCLBP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CRCCR3 ========================================================= */ + #define R_VIN_CRCCR3_CRCLAP_Pos (0UL) /*!< CRCLAP (Bit 0) */ + #define R_VIN_CRCCR3_CRCLAP_Msk (0xfffUL) /*!< CRCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_CRCCR3_CRCLHEN_Pos (23UL) /*!< CRCLHEN (Bit 23) */ + #define R_VIN_CRCCR3_CRCLHEN_Msk (0x800000UL) /*!< CRCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_CRCCR3_CRCLSFT_Pos (24UL) /*!< CRCLSFT (Bit 24) */ + #define R_VIN_CRCCR3_CRCLSFT_Msk (0x1f000000UL) /*!< CRCLSFT (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA_Pos (0UL) /*!< SRAMSA (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA_Msk (0x1UL) /*!< SRAMSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMWTSA_Pos (8UL) /*!< SRAMWTSA (Bit 8) */ + #define R_CPSCU_SRAMSAR_SRAMWTSA_Msk (0x100UL) /*!< SRAMWTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCR_Pos (0UL) /*!< SAIRQCR (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCR_Msk (0x1UL) /*!< SAIRQCR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAPDMWUP_Pos (15UL) /*!< SAPDMWUP (Bit 15) */ + #define R_CPSCU_ICUSARF_SAPDMWUP_Msk (0x8000UL) /*!< SAPDMWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARJ ======================================================== */ + #define R_CPSCU_ICUSARJ_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARJ_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARK ======================================================== */ + #define R_CPSCU_ICUSARK_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARK_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARL ======================================================== */ + #define R_CPSCU_ICUSARL_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARL_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_CPSCU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_CPSCU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_CPSCU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_PVD1ST_Pos (2UL) /*!< PVD1ST (Bit 2) */ + #define R_CPSCU_NMISR_PVD1ST_Msk (0x4UL) /*!< PVD1ST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_PVD2ST_Pos (3UL) /*!< PVD2ST (Bit 3) */ + #define R_CPSCU_NMISR_PVD2ST_Msk (0x8UL) /*!< PVD2ST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_SOSTST_Pos (5UL) /*!< SOSTST (Bit 5) */ + #define R_CPSCU_NMISR_SOSTST_Msk (0x20UL) /*!< SOSTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_CPSCU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_CPSCU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_CPSCU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_CPSCU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_LMST_Pos (14UL) /*!< LMST (Bit 14) */ + #define R_CPSCU_NMISR_LMST_Msk (0x4000UL) /*!< LMST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_CPSCU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_FPUEXCST_Pos (16UL) /*!< FPUEXCST (Bit 16) */ + #define R_CPSCU_NMISR_FPUEXCST_Msk (0x10000UL) /*!< FPUEXCST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_MRCRDST_Pos (17UL) /*!< MRCRDST (Bit 17) */ + #define R_CPSCU_NMISR_MRCRDST_Msk (0x20000UL) /*!< MRCRDST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_MRERDST_Pos (18UL) /*!< MRERDST (Bit 18) */ + #define R_CPSCU_NMISR_MRERDST_Msk (0x40000UL) /*!< MRERDST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_IPCST_Pos (20UL) /*!< IPCST (Bit 20) */ + #define R_CPSCU_NMISR_IPCST_Msk (0x100000UL) /*!< IPCST (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUASA_Pos (0UL) /*!< MMPUASA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUASA_Msk (0x1UL) /*!< MMPUASA (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUBSA_Pos (0UL) /*!< MMPUBSA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUBSA_Msk (0x1UL) /*!< MMPUBSA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUSAR ========================================================= */ + #define R_CPSCU_CPUSAR_CPUSA_Pos (0UL) /*!< CPUSA (Bit 0) */ + #define R_CPSCU_CPUSAR_CPUSA_Msk (0x1UL) /*!< CPUSA (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_SADMAC0_Pos (0UL) /*!< SADMAC0 (Bit 0) */ + #define R_CPSCU_DMACCHSAR_SADMAC0_Msk (0x1UL) /*!< SADMAC0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_DMACCHSAR_SADMAC1_Pos (16UL) /*!< SADMAC1 (Bit 16) */ + #define R_CPSCU_DMACCHSAR_SADMAC1_Msk (0x10000UL) /*!< SADMAC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHPAR ======================================================= */ + #define R_CPSCU_DMACCHPAR_PADMAC0_Pos (0UL) /*!< PADMAC0 (Bit 0) */ + #define R_CPSCU_DMACCHPAR_PADMAC0_Msk (0x1UL) /*!< PADMAC0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_DMACCHPAR_PADMAC1_Pos (16UL) /*!< PADMAC1 (Bit 16) */ + #define R_CPSCU_DMACCHPAR_PADMAC1_Msk (0x10000UL) /*!< PADMAC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR2 ======================================================= */ + #define R_CPSCU_SRAMSABAR2_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR2_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR3 ======================================================= */ + #define R_CPSCU_SRAMSABAR3_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR3_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================= CACHESAR ======================================================== */ + #define R_CPSCU_CACHESAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CACHESAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CACHESAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CACHESAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMSAR ========================================================= */ + #define R_CPSCU_TCMSAR_TCMSA_Pos (0UL) /*!< TCMSA (Bit 0) */ + #define R_CPSCU_TCMSAR_TCMSA_Msk (0x1UL) /*!< TCMSA (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMSABARC ======================================================= */ + #define R_CPSCU_TCMSABARC_TCMSABA_Pos (13UL) /*!< TCMSABA (Bit 13) */ + #define R_CPSCU_TCMSABARC_TCMSABA_Msk (0x7e000UL) /*!< TCMSABA (Bitfield-Mask: 0x3f) */ +/* ======================================================= TCMSABARS ======================================================= */ + #define R_CPSCU_TCMSABARS_TCMSABA_Pos (13UL) /*!< TCMSABA (Bit 13) */ + #define R_CPSCU_TCMSABARS_TCMSABA_Msk (0x7e000UL) /*!< TCMSABA (Bitfield-Mask: 0x3f) */ +/* ======================================================= SRAMESAR ======================================================== */ + #define R_CPSCU_SRAMESAR_SRAMESA_Pos (0UL) /*!< SRAMESA (Bit 0) */ + #define R_CPSCU_SRAMESAR_SRAMESA_Msk (0x1UL) /*!< SRAMESA (Bitfield-Mask: 0x01) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + #define R_CPSCU_TEVTRCR_TEVTEICU_Pos (1UL) /*!< TEVTEICU (Bit 1) */ + #define R_CPSCU_TEVTRCR_TEVTEICU_Msk (0x2UL) /*!< TEVTEICU (Bitfield-Mask: 0x01) */ +/* ======================================================== IPCSAR ========================================================= */ + #define R_CPSCU_IPCSAR_SAIPCSEM_Pos (0UL) /*!< SAIPCSEM (Bit 0) */ + #define R_CPSCU_IPCSAR_SAIPCSEM_Msk (0x1UL) /*!< SAIPCSEM (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCNMI_Pos (8UL) /*!< SAIPCNMI (Bit 8) */ + #define R_CPSCU_IPCSAR_SAIPCNMI_Msk (0x100UL) /*!< SAIPCNMI (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR0_Pos (16UL) /*!< SAIPCIR0 (Bit 16) */ + #define R_CPSCU_IPCSAR_SAIPCIR0_Msk (0x10000UL) /*!< SAIPCIR0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR1_Pos (17UL) /*!< SAIPCIR1 (Bit 17) */ + #define R_CPSCU_IPCSAR_SAIPCIR1_Msk (0x20000UL) /*!< SAIPCIR1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR2_Pos (18UL) /*!< SAIPCIR2 (Bit 18) */ + #define R_CPSCU_IPCSAR_SAIPCIR2_Msk (0x40000UL) /*!< SAIPCIR2 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR3_Pos (19UL) /*!< SAIPCIR3 (Bit 19) */ + #define R_CPSCU_IPCSAR_SAIPCIR3_Msk (0x80000UL) /*!< SAIPCIR3 (Bitfield-Mask: 0x01) */ +/* ======================================================== IPCPAR ========================================================= */ + #define R_CPSCU_IPCPAR_PAIPCSEM_Pos (0UL) /*!< PAIPCSEM (Bit 0) */ + #define R_CPSCU_IPCPAR_PAIPCSEM_Msk (0x1UL) /*!< PAIPCSEM (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCNMI_Pos (8UL) /*!< PAIPCNMI (Bit 8) */ + #define R_CPSCU_IPCPAR_PAIPCNMI_Msk (0x100UL) /*!< PAIPCNMI (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR0_Pos (16UL) /*!< PAIPCIR0 (Bit 16) */ + #define R_CPSCU_IPCPAR_PAIPCIR0_Msk (0x10000UL) /*!< PAIPCIR0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR1_Pos (17UL) /*!< PAIPCIR1 (Bit 17) */ + #define R_CPSCU_IPCPAR_PAIPCIR1_Msk (0x20000UL) /*!< PAIPCIR1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR2_Pos (18UL) /*!< PAIPCIR2 (Bit 18) */ + #define R_CPSCU_IPCPAR_PAIPCIR2_Msk (0x40000UL) /*!< PAIPCIR2 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR3_Pos (19UL) /*!< PAIPCIR3 (Bit 19) */ + #define R_CPSCU_IPCPAR_PAIPCIR3_Msk (0x80000UL) /*!< PAIPCIR3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ADCLKENR ======================================================== */ + #define R_ADC_B0_ADCLKENR_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */ + #define R_ADC_B0_ADCLKENR_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKSR ======================================================== */ + #define R_ADC_B0_ADCLKSR_CLKSR_Pos (0UL) /*!< CLKSR (Bit 0) */ + #define R_ADC_B0_ADCLKSR_CLKSR_Msk (0x1UL) /*!< CLKSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKCR ======================================================== */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCLKCR_DIVR_Pos (16UL) /*!< DIVR (Bit 16) */ + #define R_ADC_B0_ADCLKCR_DIVR_Msk (0x70000UL) /*!< DIVR (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSYCR ========================================================= */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Pos (0UL) /*!< ADSYCYC (Bit 0) */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Msk (0x7ffUL) /*!< ADSYCYC (Bitfield-Mask: 0x7ff) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Pos (16UL) /*!< ADSYDIS0 (Bit 16) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Msk (0x10000UL) /*!< ADSYDIS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Pos (17UL) /*!< ADSYDIS1 (Bit 17) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Msk (0x20000UL) /*!< ADSYDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADERINTCR ======================================================= */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Pos (0UL) /*!< ADEIE0 (Bit 0) */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Msk (0x1UL) /*!< ADEIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Pos (1UL) /*!< ADEIE1 (Bit 1) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Msk (0x2UL) /*!< ADEIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFINTCR ======================================================= */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Pos (0UL) /*!< ADOVFIE0 (Bit 0) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Msk (0x1UL) /*!< ADOVFIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Pos (1UL) /*!< ADOVFIE1 (Bit 1) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Msk (0x2UL) /*!< ADOVFIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALINTCR ======================================================= */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Pos (16UL) /*!< CALENDIE0 (Bit 16) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Msk (0x10000UL) /*!< CALENDIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Pos (17UL) /*!< CALENDIE1 (Bit 17) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Msk (0x20000UL) /*!< CALENDIE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADMDR ========================================================= */ + #define R_ADC_B0_ADMDR_ADMD0_Pos (0UL) /*!< ADMD0 (Bit 0) */ + #define R_ADC_B0_ADMDR_ADMD0_Msk (0xfUL) /*!< ADMD0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADMDR_ADMD1_Pos (8UL) /*!< ADMD1 (Bit 8) */ + #define R_ADC_B0_ADMDR_ADMD1_Msk (0xf00UL) /*!< ADMD1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC_B0_ADGSPCR_PGS0_Pos (0UL) /*!< PGS0 (Bit 0) */ + #define R_ADC_B0_ADGSPCR_PGS0_Msk (0x1UL) /*!< PGS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Pos (1UL) /*!< RSCN0 (Bit 1) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Msk (0x2UL) /*!< RSCN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Pos (2UL) /*!< LGRRS0 (Bit 2) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Msk (0x4UL) /*!< LGRRS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP0_Pos (3UL) /*!< GRP0 (Bit 3) */ + #define R_ADC_B0_ADGSPCR_GRP0_Msk (0x8UL) /*!< GRP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_PGS1_Pos (8UL) /*!< PGS1 (Bit 8) */ + #define R_ADC_B0_ADGSPCR_PGS1_Msk (0x100UL) /*!< PGS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Pos (9UL) /*!< RSCN1 (Bit 9) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Msk (0x200UL) /*!< RSCN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Pos (10UL) /*!< LGRRS1 (Bit 10) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Msk (0x400UL) /*!< LGRRS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP1_Pos (11UL) /*!< GRP1 (Bit 11) */ + #define R_ADC_B0_ADGSPCR_GRP1_Msk (0x800UL) /*!< GRP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSGER ========================================================= */ + #define R_ADC_B0_ADSGER_SGREn_Pos (0UL) /*!< SGREn (Bit 0) */ + #define R_ADC_B0_ADSGER_SGREn_Msk (0x1ffUL) /*!< SGREn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSGCR0 ======================================================== */ + #define R_ADC_B0_ADSGCR0_SGADS0_Pos (0UL) /*!< SGADS0 (Bit 0) */ + #define R_ADC_B0_ADSGCR0_SGADS0_Msk (0x3UL) /*!< SGADS0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Pos (8UL) /*!< SGADS1 (Bit 8) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Msk (0x300UL) /*!< SGADS1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Pos (16UL) /*!< SGADS2 (Bit 16) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Msk (0x30000UL) /*!< SGADS2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Pos (24UL) /*!< SGADS3 (Bit 24) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Msk (0x3000000UL) /*!< SGADS3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR1 ======================================================== */ + #define R_ADC_B0_ADSGCR1_SGADS4_Pos (0UL) /*!< SGADS4 (Bit 0) */ + #define R_ADC_B0_ADSGCR1_SGADS4_Msk (0x3UL) /*!< SGADS4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Pos (8UL) /*!< SGADS5 (Bit 8) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Msk (0x300UL) /*!< SGADS5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Pos (16UL) /*!< SGADS6 (Bit 16) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Msk (0x30000UL) /*!< SGADS6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Pos (24UL) /*!< SGADS7 (Bit 24) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Msk (0x3000000UL) /*!< SGADS7 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR2 ======================================================== */ + #define R_ADC_B0_ADSGCR2_SGADS8_Pos (0UL) /*!< SGADS8 (Bit 0) */ + #define R_ADC_B0_ADSGCR2_SGADS8_Msk (0x3UL) /*!< SGADS8 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADINTCR ======================================================== */ + #define R_ADC_B0_ADINTCR_ADIEn_Pos (0UL) /*!< ADIEn (Bit 0) */ + #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x1ffUL) /*!< ADIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADTRGEXT0 ======================================================= */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT1 ======================================================= */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT2 ======================================================= */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT3 ======================================================= */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT4 ======================================================= */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT5 ======================================================= */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT6 ======================================================= */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT7 ======================================================= */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT8 ======================================================= */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGELC0 ======================================================= */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC1 ======================================================= */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC2 ======================================================= */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC3 ======================================================= */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC4 ======================================================= */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC5 ======================================================= */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC6 ======================================================= */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC7 ======================================================= */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC8 ======================================================= */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGGPT0 ======================================================= */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT1 ======================================================= */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT2 ======================================================= */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT3 ======================================================= */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT4 ======================================================= */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT5 ======================================================= */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT6 ======================================================= */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT7 ======================================================= */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT8 ======================================================= */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGDLR0 ======================================================= */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Pos (0UL) /*!< TRGDLY0 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Msk (0xffUL) /*!< TRGDLY0 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Pos (16UL) /*!< TRGDLY1 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Msk (0xff0000UL) /*!< TRGDLY1 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR1 ======================================================= */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Pos (0UL) /*!< TRGDLY2 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Msk (0xffUL) /*!< TRGDLY2 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Pos (16UL) /*!< TRGDLY3 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Msk (0xff0000UL) /*!< TRGDLY3 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR2 ======================================================= */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Pos (0UL) /*!< TRGDLY4 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Msk (0xffUL) /*!< TRGDLY4 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Pos (16UL) /*!< TRGDLY5 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Msk (0xff0000UL) /*!< TRGDLY5 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR3 ======================================================= */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Pos (0UL) /*!< TRGDLY6 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Msk (0xffUL) /*!< TRGDLY6 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Pos (16UL) /*!< TRGDLY7 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Msk (0xff0000UL) /*!< TRGDLY7 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR4 ======================================================= */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Pos (0UL) /*!< TRGDLY8 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Msk (0xffUL) /*!< TRGDLY8 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR0 ======================================================== */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR1 ======================================================== */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR2 ======================================================== */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR3 ======================================================== */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR4 ======================================================== */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR5 ======================================================== */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR6 ======================================================== */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR7 ======================================================== */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR8 ======================================================== */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR0 ======================================================== */ + #define R_ADC_B0_ADSSTR0_SST0_Pos (0UL) /*!< SST0 (Bit 0) */ + #define R_ADC_B0_ADSSTR0_SST0_Msk (0x3ffUL) /*!< SST0 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR0_SST1_Pos (16UL) /*!< SST1 (Bit 16) */ + #define R_ADC_B0_ADSSTR0_SST1_Msk (0x3ff0000UL) /*!< SST1 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR1 ======================================================== */ + #define R_ADC_B0_ADSSTR1_SST2_Pos (0UL) /*!< SST2 (Bit 0) */ + #define R_ADC_B0_ADSSTR1_SST2_Msk (0x3ffUL) /*!< SST2 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR1_SST3_Pos (16UL) /*!< SST3 (Bit 16) */ + #define R_ADC_B0_ADSSTR1_SST3_Msk (0x3ff0000UL) /*!< SST3 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR2 ======================================================== */ + #define R_ADC_B0_ADSSTR2_SST4_Pos (0UL) /*!< SST4 (Bit 0) */ + #define R_ADC_B0_ADSSTR2_SST4_Msk (0x3ffUL) /*!< SST4 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR2_SST5_Pos (16UL) /*!< SST5 (Bit 16) */ + #define R_ADC_B0_ADSSTR2_SST5_Msk (0x3ff0000UL) /*!< SST5 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR3 ======================================================== */ + #define R_ADC_B0_ADSSTR3_SST6_Pos (0UL) /*!< SST6 (Bit 0) */ + #define R_ADC_B0_ADSSTR3_SST6_Msk (0x3ffUL) /*!< SST6 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR3_SST7_Pos (16UL) /*!< SST7 (Bit 16) */ + #define R_ADC_B0_ADSSTR3_SST7_Msk (0x3ff0000UL) /*!< SST7 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR4 ======================================================== */ + #define R_ADC_B0_ADSSTR4_SST8_Pos (0UL) /*!< SST8 (Bit 0) */ + #define R_ADC_B0_ADSSTR4_SST8_Msk (0x3ffUL) /*!< SST8 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR4_SST9_Pos (16UL) /*!< SST9 (Bit 16) */ + #define R_ADC_B0_ADSSTR4_SST9_Msk (0x3ff0000UL) /*!< SST9 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR5 ======================================================== */ + #define R_ADC_B0_ADSSTR5_SST10_Pos (0UL) /*!< SST10 (Bit 0) */ + #define R_ADC_B0_ADSSTR5_SST10_Msk (0x3ffUL) /*!< SST10 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR5_SST11_Pos (16UL) /*!< SST11 (Bit 16) */ + #define R_ADC_B0_ADSSTR5_SST11_Msk (0x3ff0000UL) /*!< SST11 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR6 ======================================================== */ + #define R_ADC_B0_ADSSTR6_SST12_Pos (0UL) /*!< SST12 (Bit 0) */ + #define R_ADC_B0_ADSSTR6_SST12_Msk (0x3ffUL) /*!< SST12 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR6_SST13_Pos (16UL) /*!< SST13 (Bit 16) */ + #define R_ADC_B0_ADSSTR6_SST13_Msk (0x3ff0000UL) /*!< SST13 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR7 ======================================================== */ + #define R_ADC_B0_ADSSTR7_SST14_Pos (0UL) /*!< SST14 (Bit 0) */ + #define R_ADC_B0_ADSSTR7_SST14_Msk (0x3ffUL) /*!< SST14 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR7_SST15_Pos (16UL) /*!< SST15 (Bit 16) */ + #define R_ADC_B0_ADSSTR7_SST15_Msk (0x3ff0000UL) /*!< SST15 (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADCNVSTR ======================================================== */ + #define R_ADC_B0_ADCNVSTR_CST0_Pos (0UL) /*!< CST0 (Bit 0) */ + #define R_ADC_B0_ADCNVSTR_CST0_Msk (0x3fUL) /*!< CST0 (Bitfield-Mask: 0x3f) */ + #define R_ADC_B0_ADCNVSTR_CST1_Pos (8UL) /*!< CST1 (Bit 8) */ + #define R_ADC_B0_ADCNVSTR_CST1_Msk (0x3f00UL) /*!< CST1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADCALSTCR ======================================================= */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Pos (0UL) /*!< CALADSST (Bit 0) */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Msk (0x3ffUL) /*!< CALADSST (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Pos (16UL) /*!< CALADCST (Bit 16) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Msk (0x3f0000UL) /*!< CALADCST (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADSHCR0 ======================================================== */ + #define R_ADC_B0_ADSHCR0_SHEN_Pos (0UL) /*!< SHEN (Bit 0) */ + #define R_ADC_B0_ADSHCR0_SHEN_Msk (0x1UL) /*!< SHEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR0_SHMD_Pos (16UL) /*!< SHMD (Bit 16) */ + #define R_ADC_B0_ADSHCR0_SHMD_Msk (0x10000UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR0 ======================================================== */ + #define R_ADC_B0_ADSHSTR0_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR0_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSHCR1 ======================================================== */ + #define R_ADC_B0_ADSHCR1_SHEN_Pos (0UL) /*!< SHEN (Bit 0) */ + #define R_ADC_B0_ADSHCR1_SHEN_Msk (0x1UL) /*!< SHEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR1_SHMD_Pos (16UL) /*!< SHMD (Bit 16) */ + #define R_ADC_B0_ADSHCR1_SHMD_Msk (0x10000UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR1 ======================================================== */ + #define R_ADC_B0_ADSHSTR1_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR1_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================= ADCALSHCR ======================================================= */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Pos (0UL) /*!< CALSHSST (Bit 0) */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Msk (0xffUL) /*!< CALSHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Pos (16UL) /*!< CALSHHST (Bit 16) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Msk (0x70000UL) /*!< CALSHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADREFCR ======================================================== */ + #define R_ADC_B0_ADREFCR_VDE_Pos (0UL) /*!< VDE (Bit 0) */ + #define R_ADC_B0_ADREFCR_VDE_Msk (0x1UL) /*!< VDE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDFSR0 ======================================================== */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADDFSR1 ======================================================== */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADUOFTR0 ======================================================== */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR1 ======================================================== */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR2 ======================================================== */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR3 ======================================================== */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR4 ======================================================== */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR5 ======================================================== */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR6 ======================================================== */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR7 ======================================================== */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADUGTR0 ======================================================== */ + #define R_ADC_B0_ADUGTR0_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR0_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR0_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR0_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR1 ======================================================== */ + #define R_ADC_B0_ADUGTR1_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR1_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR1_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR1_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR2 ======================================================== */ + #define R_ADC_B0_ADUGTR2_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR2_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR2_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR2_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR3 ======================================================== */ + #define R_ADC_B0_ADUGTR3_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR3_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR3_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR3_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR4 ======================================================== */ + #define R_ADC_B0_ADUGTR4_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR4_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR4_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR4_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR5 ======================================================== */ + #define R_ADC_B0_ADUGTR5_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR5_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR5_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR5_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR6 ======================================================== */ + #define R_ADC_B0_ADUGTR6_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR6_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR6_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR6_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR7 ======================================================== */ + #define R_ADC_B0_ADUGTR7_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR7_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR7_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR7_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ====================================================== ADLIMINTCR ======================================================= */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Pos (0UL) /*!< LIMIEn (Bit 0) */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Msk (0x1ffUL) /*!< LIMIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADLIMTR0 ======================================================== */ + #define R_ADC_B0_ADLIMTR0_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR0_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR1 ======================================================== */ + #define R_ADC_B0_ADLIMTR1_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR1_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR2 ======================================================== */ + #define R_ADC_B0_ADLIMTR2_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR2_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR3 ======================================================== */ + #define R_ADC_B0_ADLIMTR3_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR3_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR4 ======================================================== */ + #define R_ADC_B0_ADLIMTR4_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR4_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR5 ======================================================== */ + #define R_ADC_B0_ADLIMTR5_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR5_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR6 ======================================================== */ + #define R_ADC_B0_ADLIMTR6_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR6_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR7 ======================================================== */ + #define R_ADC_B0_ADLIMTR7_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR7_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPENR ======================================================== */ + #define R_ADC_B0_ADCMPENR_CMPENn_Pos (0UL) /*!< CMPENn (Bit 0) */ + #define R_ADC_B0_ADCMPENR_CMPENn_Msk (0xffUL) /*!< CMPENn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPINTCR ======================================================= */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Pos (0UL) /*!< CMPIEn (Bit 0) */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Msk (0xfUL) /*!< CMPIEn (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCCMPCR0 ======================================================= */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCCMPCR1 ======================================================= */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCMPMDR0 ======================================================= */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Pos (0UL) /*!< CMPMD0 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Msk (0x3UL) /*!< CMPMD0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Pos (8UL) /*!< CMPMD1 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Msk (0x300UL) /*!< CMPMD1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Pos (16UL) /*!< CMPMD2 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Msk (0x30000UL) /*!< CMPMD2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Pos (24UL) /*!< CMPMD3 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Msk (0x3000000UL) /*!< CMPMD3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPMDR1 ======================================================= */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Pos (0UL) /*!< CMPMD4 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Msk (0x3UL) /*!< CMPMD4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Pos (8UL) /*!< CMPMD5 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Msk (0x300UL) /*!< CMPMD5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Pos (16UL) /*!< CMPMD6 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Msk (0x30000UL) /*!< CMPMD6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Pos (24UL) /*!< CMPMD7 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Msk (0x3000000UL) /*!< CMPMD7 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPTBR0 ======================================================= */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR1 ======================================================= */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR2 ======================================================= */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR3 ======================================================= */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR4 ======================================================= */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR5 ======================================================= */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR6 ======================================================= */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR7 ======================================================= */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADFIFOCR ======================================================== */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Pos (0UL) /*!< FIFOEN0 (Bit 0) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Msk (0x1UL) /*!< FIFOEN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Pos (1UL) /*!< FIFOEN1 (Bit 1) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Msk (0x2UL) /*!< FIFOEN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Pos (2UL) /*!< FIFOEN2 (Bit 2) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Msk (0x4UL) /*!< FIFOEN2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Pos (3UL) /*!< FIFOEN3 (Bit 3) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Msk (0x8UL) /*!< FIFOEN3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Pos (4UL) /*!< FIFOEN4 (Bit 4) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Msk (0x10UL) /*!< FIFOEN4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Pos (5UL) /*!< FIFOEN5 (Bit 5) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Msk (0x20UL) /*!< FIFOEN5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Pos (6UL) /*!< FIFOEN6 (Bit 6) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Msk (0x40UL) /*!< FIFOEN6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Pos (7UL) /*!< FIFOEN7 (Bit 7) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Msk (0x80UL) /*!< FIFOEN7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Pos (8UL) /*!< FIFOEN8 (Bit 8) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Msk (0x100UL) /*!< FIFOEN8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADFIFOINTCR ====================================================== */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Pos (0UL) /*!< FIFOIE0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Msk (0x1UL) /*!< FIFOIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Pos (1UL) /*!< FIFOIE1 (Bit 1) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Msk (0x2UL) /*!< FIFOIE1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Pos (2UL) /*!< FIFOIE2 (Bit 2) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Msk (0x4UL) /*!< FIFOIE2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Pos (3UL) /*!< FIFOIE3 (Bit 3) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Msk (0x8UL) /*!< FIFOIE3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Pos (4UL) /*!< FIFOIE4 (Bit 4) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Msk (0x10UL) /*!< FIFOIE4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Pos (5UL) /*!< FIFOIE5 (Bit 5) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Msk (0x20UL) /*!< FIFOIE5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Pos (6UL) /*!< FIFOIE6 (Bit 6) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Msk (0x40UL) /*!< FIFOIE6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Pos (7UL) /*!< FIFOIE7 (Bit 7) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Msk (0x80UL) /*!< FIFOIE7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Pos (8UL) /*!< FIFOIE8 (Bit 8) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Msk (0x100UL) /*!< FIFOIE8 (Bitfield-Mask: 0x01) */ +/* ===================================================== ADFIFOINTLR0 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Pos (0UL) /*!< FIFOILV0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Msk (0xfUL) /*!< FIFOILV0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Pos (16UL) /*!< FIFOILV1 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Msk (0xf0000UL) /*!< FIFOILV1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR1 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Pos (0UL) /*!< FIFOILV2 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Msk (0xfUL) /*!< FIFOILV2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Pos (16UL) /*!< FIFOILV3 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Msk (0xf0000UL) /*!< FIFOILV3 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR2 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Pos (0UL) /*!< FIFOILV4 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Msk (0xfUL) /*!< FIFOILV4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Pos (16UL) /*!< FIFOILV5 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Msk (0xf0000UL) /*!< FIFOILV5 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR3 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Pos (0UL) /*!< FIFOILV6 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Msk (0xfUL) /*!< FIFOILV6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Pos (16UL) /*!< FIFOILV7 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Msk (0xf0000UL) /*!< FIFOILV7 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR4 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Pos (0UL) /*!< FIFOILV8 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Msk (0xfUL) /*!< FIFOILV8 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR0 ======================================================== */ + #define R_ADC_B0_ADCHCR0_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR0_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR0_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR0_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR1 ======================================================== */ + #define R_ADC_B0_ADCHCR1_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR1_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR1_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR1_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR2 ======================================================== */ + #define R_ADC_B0_ADCHCR2_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR2_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR2_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR2_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR3 ======================================================== */ + #define R_ADC_B0_ADCHCR3_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR3_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR3_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR3_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR4 ======================================================== */ + #define R_ADC_B0_ADCHCR4_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR4_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR4_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR4_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR5 ======================================================== */ + #define R_ADC_B0_ADCHCR5_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR5_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR5_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR5_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR6 ======================================================== */ + #define R_ADC_B0_ADCHCR6_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR6_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR6_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR6_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR7 ======================================================== */ + #define R_ADC_B0_ADCHCR7_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR7_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR7_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR7_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR8 ======================================================== */ + #define R_ADC_B0_ADCHCR8_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR8_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR8_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR8_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR9 ======================================================== */ + #define R_ADC_B0_ADCHCR9_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR9_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR9_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR9_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR10 ======================================================== */ + #define R_ADC_B0_ADCHCR10_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR10_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR10_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR10_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR11 ======================================================== */ + #define R_ADC_B0_ADCHCR11_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR11_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR11_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR11_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR12 ======================================================== */ + #define R_ADC_B0_ADCHCR12_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR12_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR12_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR12_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR13 ======================================================== */ + #define R_ADC_B0_ADCHCR13_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR13_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR13_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR13_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR14 ======================================================== */ + #define R_ADC_B0_ADCHCR14_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR14_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR14_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR14_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR15 ======================================================== */ + #define R_ADC_B0_ADCHCR15_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR15_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR15_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR15_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR16 ======================================================== */ + #define R_ADC_B0_ADCHCR16_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR16_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR16_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR16_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR17 ======================================================== */ + #define R_ADC_B0_ADCHCR17_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR17_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR17_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR17_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR18 ======================================================== */ + #define R_ADC_B0_ADCHCR18_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR18_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR18_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR18_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR19 ======================================================== */ + #define R_ADC_B0_ADCHCR19_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR19_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR19_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR19_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR20 ======================================================== */ + #define R_ADC_B0_ADCHCR20_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR20_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR20_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR20_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR21 ======================================================== */ + #define R_ADC_B0_ADCHCR21_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR21_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR21_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR21_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR22 ======================================================== */ + #define R_ADC_B0_ADCHCR22_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR22_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR22_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR22_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR23 ======================================================== */ + #define R_ADC_B0_ADCHCR23_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR23_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR23_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR23_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR24 ======================================================== */ + #define R_ADC_B0_ADCHCR24_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR24_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR24_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR24_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR25 ======================================================== */ + #define R_ADC_B0_ADCHCR25_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR25_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR25_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR25_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR26 ======================================================== */ + #define R_ADC_B0_ADCHCR26_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR26_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR26_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR26_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR27 ======================================================== */ + #define R_ADC_B0_ADCHCR27_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR27_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR27_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR27_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR28 ======================================================== */ + #define R_ADC_B0_ADCHCR28_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR28_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR28_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR28_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR29 ======================================================== */ + #define R_ADC_B0_ADCHCR29_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR29_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR29_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR29_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR30 ======================================================== */ + #define R_ADC_B0_ADCHCR30_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR30_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR30_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR30_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR31 ======================================================== */ + #define R_ADC_B0_ADCHCR31_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR31_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR31_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR31_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR32 ======================================================== */ + #define R_ADC_B0_ADCHCR32_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR32_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR32_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR32_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA0 ======================================================= */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA1 ======================================================= */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA2 ======================================================= */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA3 ======================================================= */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA4 ======================================================= */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA5 ======================================================= */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA6 ======================================================= */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA7 ======================================================= */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA8 ======================================================= */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA9 ======================================================= */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA10 ======================================================= */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA11 ======================================================= */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA12 ======================================================= */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA13 ======================================================= */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA14 ======================================================= */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA15 ======================================================= */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA16 ======================================================= */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA17 ======================================================= */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA18 ======================================================= */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA19 ======================================================= */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA20 ======================================================= */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA21 ======================================================= */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA22 ======================================================= */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA23 ======================================================= */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA24 ======================================================= */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA25 ======================================================= */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA26 ======================================================= */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA27 ======================================================= */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA28 ======================================================= */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA29 ======================================================= */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA30 ======================================================= */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA31 ======================================================= */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA32 ======================================================= */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRB0 ======================================================= */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB1 ======================================================= */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB2 ======================================================= */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB3 ======================================================= */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB4 ======================================================= */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB5 ======================================================= */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB6 ======================================================= */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB7 ======================================================= */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB8 ======================================================= */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB9 ======================================================= */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB10 ======================================================= */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB11 ======================================================= */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB12 ======================================================= */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB13 ======================================================= */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB14 ======================================================= */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB15 ======================================================= */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB16 ======================================================= */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB17 ======================================================= */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB18 ======================================================= */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB19 ======================================================= */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB20 ======================================================= */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB21 ======================================================= */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB22 ======================================================= */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB23 ======================================================= */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB24 ======================================================= */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB25 ======================================================= */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB26 ======================================================= */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB27 ======================================================= */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB28 ======================================================= */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB29 ======================================================= */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB30 ======================================================= */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB31 ======================================================= */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB32 ======================================================= */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRC0 ======================================================= */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC1 ======================================================= */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC2 ======================================================= */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC3 ======================================================= */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC4 ======================================================= */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC5 ======================================================= */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC6 ======================================================= */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC7 ======================================================= */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC8 ======================================================= */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC9 ======================================================= */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC10 ======================================================= */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC11 ======================================================= */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC12 ======================================================= */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC13 ======================================================= */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC14 ======================================================= */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC15 ======================================================= */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC16 ======================================================= */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC17 ======================================================= */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC18 ======================================================= */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC19 ======================================================= */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC20 ======================================================= */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC21 ======================================================= */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC22 ======================================================= */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC23 ======================================================= */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC24 ======================================================= */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC25 ======================================================= */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC26 ======================================================= */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC27 ======================================================= */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC28 ======================================================= */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC29 ======================================================= */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC30 ======================================================= */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC31 ======================================================= */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC32 ======================================================= */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALSTR ======================================================== */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Pos (0UL) /*!< ADCALST0 (Bit 0) */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Msk (0x7UL) /*!< ADCALST0 (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Pos (8UL) /*!< ADCALST1 (Bit 8) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Msk (0x700UL) /*!< ADCALST1 (Bitfield-Mask: 0x07) */ +/* ======================================================= ADTRGENR ======================================================== */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Pos (0UL) /*!< STTRGENn (Bit 0) */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Msk (0x1ffUL) /*!< STTRGENn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSYSTR ======================================================== */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Pos (0UL) /*!< ADSYSTn (Bit 0) */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Msk (0x1ffUL) /*!< ADSYSTn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADSTR ========================================================= */ + #define R_ADC_B0_ADSTR_ADST_Pos (0UL) /*!< ADST (Bit 0) */ + #define R_ADC_B0_ADSTR_ADST_Msk (0x1UL) /*!< ADST (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTOPR ======================================================== */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Pos (0UL) /*!< ADSTOP0 (Bit 0) */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Msk (0x1UL) /*!< ADSTOP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Pos (8UL) /*!< ADSTOP1 (Bit 8) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Msk (0x100UL) /*!< ADSTOP1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADSR ========================================================== */ + #define R_ADC_B0_ADSR_ADACT0_Pos (0UL) /*!< ADACT0 (Bit 0) */ + #define R_ADC_B0_ADSR_ADACT0_Msk (0x1UL) /*!< ADACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_ADACT1_Pos (1UL) /*!< ADACT1 (Bit 1) */ + #define R_ADC_B0_ADSR_ADACT1_Msk (0x2UL) /*!< ADACT1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT0_Pos (16UL) /*!< CALACT0 (Bit 16) */ + #define R_ADC_B0_ADSR_CALACT0_Msk (0x10000UL) /*!< CALACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT1_Pos (17UL) /*!< CALACT1 (Bit 17) */ + #define R_ADC_B0_ADSR_CALACT1_Msk (0x20000UL) /*!< CALACT1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGRSR ========================================================= */ + #define R_ADC_B0_ADGRSR_ACTGRn_Pos (0UL) /*!< ACTGRn (Bit 0) */ + #define R_ADC_B0_ADGRSR_ACTGRn_Msk (0x1ffUL) /*!< ACTGRn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADERSR ========================================================= */ + #define R_ADC_B0_ADERSR_ADERF0_Pos (0UL) /*!< ADERF0 (Bit 0) */ + #define R_ADC_B0_ADERSR_ADERF0_Msk (0x1UL) /*!< ADERF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSR_ADERF1_Pos (1UL) /*!< ADERF1 (Bit 1) */ + #define R_ADC_B0_ADERSR_ADERF1_Msk (0x2UL) /*!< ADERF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADERSCR ======================================================== */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Pos (0UL) /*!< ADERCLR0 (Bit 0) */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Msk (0x1UL) /*!< ADERCLR0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Pos (1UL) /*!< ADERCLR1 (Bit 1) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Msk (0x2UL) /*!< ADERCLR1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSR ======================================================= */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Pos (0UL) /*!< CALENDF0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Msk (0x1UL) /*!< CALENDF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Pos (1UL) /*!< CALENDF1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Msk (0x2UL) /*!< CALENDF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSCR ====================================================== */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Pos (0UL) /*!< CALENDC0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Msk (0x1UL) /*!< CALENDC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Pos (1UL) /*!< CALENDC1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Msk (0x2UL) /*!< CALENDC1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADOVFERSR ======================================================= */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Pos (0UL) /*!< ADOVFEF0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Msk (0x1UL) /*!< ADOVFEF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Pos (1UL) /*!< ADOVFEF1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Msk (0x2UL) /*!< ADOVFEF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSR0 ======================================================= */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Pos (0UL) /*!< OVFCHFn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Msk (0x7fffffUL) /*!< OVFCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADOVFEXSR ======================================================= */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Pos (0UL) /*!< OVFEXF0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Msk (0x1UL) /*!< OVFEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Pos (1UL) /*!< OVFEXF1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Msk (0x2UL) /*!< OVFEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF4_Pos (4UL) /*!< OVFEXF4 (Bit 4) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF4_Msk (0x10UL) /*!< OVFEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Pos (5UL) /*!< OVFEXF5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Msk (0x20UL) /*!< OVFEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Pos (6UL) /*!< OVFEXF6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Msk (0x40UL) /*!< OVFEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Pos (8UL) /*!< OVFEXF8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Msk (0x100UL) /*!< OVFEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF9_Pos (9UL) /*!< OVFEXF9 (Bit 9) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF9_Msk (0x200UL) /*!< OVFEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF16_Pos (16UL) /*!< OVFEXF16 (Bit 16) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF16_Msk (0x10000UL) /*!< OVFEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF17_Pos (17UL) /*!< OVFEXF17 (Bit 17) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF17_Msk (0x20000UL) /*!< OVFEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF18_Pos (18UL) /*!< OVFEXF18 (Bit 18) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF18_Msk (0x40000UL) /*!< OVFEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF20_Pos (20UL) /*!< OVFEXF20 (Bit 20) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF20_Msk (0x100000UL) /*!< OVFEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF21_Pos (21UL) /*!< OVFEXF21 (Bit 21) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF21_Msk (0x200000UL) /*!< OVFEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF22_Pos (22UL) /*!< OVFEXF22 (Bit 22) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF22_Msk (0x400000UL) /*!< OVFEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFERSCR ======================================================= */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Pos (0UL) /*!< ADOVFEC0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Msk (0x1UL) /*!< ADOVFEC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Pos (1UL) /*!< ADOVFEC1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Msk (0x2UL) /*!< ADOVFEC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSCR0 ====================================================== */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Pos (0UL) /*!< OVFCHCn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Msk (0x7fffffUL) /*!< OVFCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADOVFEXSCR ======================================================= */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Pos (0UL) /*!< OVFEXC0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Msk (0x1UL) /*!< OVFEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Pos (1UL) /*!< OVFEXC1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Msk (0x2UL) /*!< OVFEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC4_Pos (4UL) /*!< OVFEXC4 (Bit 4) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC4_Msk (0x10UL) /*!< OVFEXC4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Pos (5UL) /*!< OVFEXC5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Msk (0x20UL) /*!< OVFEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Pos (6UL) /*!< OVFEXC6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Msk (0x40UL) /*!< OVFEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Pos (8UL) /*!< OVFEXC8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Msk (0x100UL) /*!< OVFEXC8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC9_Pos (9UL) /*!< OVFEXC9 (Bit 9) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC9_Msk (0x200UL) /*!< OVFEXC9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC16_Pos (16UL) /*!< OVFEXC16 (Bit 16) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC16_Msk (0x10000UL) /*!< OVFEXC16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC17_Pos (17UL) /*!< OVFEXC17 (Bit 17) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC17_Msk (0x20000UL) /*!< OVFEXC17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC18_Pos (18UL) /*!< OVFEXC18 (Bit 18) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC18_Msk (0x40000UL) /*!< OVFEXC18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC20_Pos (20UL) /*!< OVFEXC20 (Bit 20) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC20_Msk (0x100000UL) /*!< OVFEXC20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC21_Pos (21UL) /*!< OVFEXC21 (Bit 21) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC21_Msk (0x200000UL) /*!< OVFEXC21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC22_Pos (22UL) /*!< OVFEXC22 (Bit 22) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC22_Msk (0x400000UL) /*!< OVFEXC22 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFOSR0 ======================================================= */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Pos (0UL) /*!< FIFOST0 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Msk (0xfUL) /*!< FIFOST0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Pos (16UL) /*!< FIFOST1 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Msk (0xf0000UL) /*!< FIFOST1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR1 ======================================================= */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Pos (0UL) /*!< FIFOST2 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Msk (0xfUL) /*!< FIFOST2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Pos (16UL) /*!< FIFOST3 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Msk (0xf0000UL) /*!< FIFOST3 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR2 ======================================================= */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Pos (0UL) /*!< FIFOST4 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Msk (0xfUL) /*!< FIFOST4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Pos (16UL) /*!< FIFOST5 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Msk (0xf0000UL) /*!< FIFOST5 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR3 ======================================================= */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Pos (0UL) /*!< FIFOST6 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Msk (0xfUL) /*!< FIFOST6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Pos (16UL) /*!< FIFOST7 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Msk (0xf0000UL) /*!< FIFOST7 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR4 ======================================================= */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Pos (0UL) /*!< FIFOST8 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Msk (0xfUL) /*!< FIFOST8 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFODCR ======================================================= */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Pos (0UL) /*!< FIFODCn (Bit 0) */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Msk (0x1ffUL) /*!< FIFODCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSR ======================================================= */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Pos (0UL) /*!< FIFOOVFn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Msk (0x1ffUL) /*!< FIFOOVFn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Pos (16UL) /*!< FIFOFLFn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Msk (0x1ff0000UL) /*!< FIFOFLFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSCR ====================================================== */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Pos (0UL) /*!< FIFOOVFCn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Msk (0x1ffUL) /*!< FIFOOVFCn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Pos (16UL) /*!< FIFOFLCn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Msk (0x1ff0000UL) /*!< FIFOFLCn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADCMPTBSR ======================================================= */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Pos (0UL) /*!< CMPTBFn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Msk (0xffUL) /*!< CMPTBFn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPTBSCR ======================================================= */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Pos (0UL) /*!< CMPTBCn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Msk (0xffUL) /*!< CMPTBCn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPCHSR0 ======================================================= */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Pos (0UL) /*!< CMPCHFn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Msk (0x7fffffUL) /*!< CMPCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADCMPEXSR ======================================================= */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Pos (0UL) /*!< CMPEXF0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Msk (0x1UL) /*!< CMPEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Pos (1UL) /*!< CMPEXF1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Msk (0x2UL) /*!< CMPEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF4_Pos (4UL) /*!< CMPEXF4 (Bit 4) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF4_Msk (0x10UL) /*!< CMPEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Pos (5UL) /*!< CMPEXF5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Msk (0x20UL) /*!< CMPEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Pos (6UL) /*!< CMPEXF6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Msk (0x40UL) /*!< CMPEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Pos (8UL) /*!< CMPEXF8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Msk (0x100UL) /*!< CMPEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF9_Pos (9UL) /*!< CMPEXF9 (Bit 9) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF9_Msk (0x200UL) /*!< CMPEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF16_Pos (16UL) /*!< CMPEXF16 (Bit 16) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF16_Msk (0x10000UL) /*!< CMPEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF17_Pos (17UL) /*!< CMPEXF17 (Bit 17) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF17_Msk (0x20000UL) /*!< CMPEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF18_Pos (18UL) /*!< CMPEXF18 (Bit 18) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF18_Msk (0x40000UL) /*!< CMPEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF20_Pos (20UL) /*!< CMPEXF20 (Bit 20) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF20_Msk (0x100000UL) /*!< CMPEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF21_Pos (21UL) /*!< CMPEXF21 (Bit 21) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF21_Msk (0x200000UL) /*!< CMPEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF22_Pos (22UL) /*!< CMPEXF22 (Bit 22) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF22_Msk (0x400000UL) /*!< CMPEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCMPCHSCR0 ====================================================== */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Pos (0UL) /*!< CMPCHCn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Msk (0x7fffffUL) /*!< CMPCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADCMPEXSCR ======================================================= */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Pos (0UL) /*!< CMPEXC0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Msk (0x1UL) /*!< CMPEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Pos (1UL) /*!< CMPEXC1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Msk (0x2UL) /*!< CMPEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC4_Pos (4UL) /*!< CMPEXC4 (Bit 4) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC4_Msk (0x10UL) /*!< CMPEXC4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Pos (5UL) /*!< CMPEXC5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Msk (0x20UL) /*!< CMPEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Pos (6UL) /*!< CMPEXC6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Msk (0x40UL) /*!< CMPEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Pos (8UL) /*!< CMPEXC8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Msk (0x100UL) /*!< CMPEXC8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC9_Pos (9UL) /*!< CMPEXC9 (Bit 9) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC9_Msk (0x200UL) /*!< CMPEXC9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC16_Pos (16UL) /*!< CMPEXC16 (Bit 16) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC16_Msk (0x10000UL) /*!< CMPEXC16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC17_Pos (17UL) /*!< CMPEXC17 (Bit 17) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC17_Msk (0x20000UL) /*!< CMPEXC17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC18_Pos (18UL) /*!< CMPEXC18 (Bit 18) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC18_Msk (0x40000UL) /*!< CMPEXC18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC20_Pos (20UL) /*!< CMPEXC20 (Bit 20) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC20_Msk (0x100000UL) /*!< CMPEXC20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC21_Pos (21UL) /*!< CMPEXC21 (Bit 21) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC21_Msk (0x200000UL) /*!< CMPEXC21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC22_Pos (22UL) /*!< CMPEXC22 (Bit 22) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC22_Msk (0x400000UL) /*!< CMPEXC22 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADLIMGRSR ======================================================= */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Pos (0UL) /*!< LIMGRFn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Msk (0x1ffUL) /*!< LIMGRFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSR0 ======================================================= */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Pos (0UL) /*!< LIMCHFn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Msk (0x7fffffUL) /*!< LIMCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADLIMEXSR ======================================================= */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF4_Pos (4UL) /*!< LIMEXF4 (Bit 4) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF4_Msk (0x10UL) /*!< LIMEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF9_Pos (9UL) /*!< LIMEXF9 (Bit 9) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF9_Msk (0x200UL) /*!< LIMEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF16_Pos (16UL) /*!< LIMEXF16 (Bit 16) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF16_Msk (0x10000UL) /*!< LIMEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF17_Pos (17UL) /*!< LIMEXF17 (Bit 17) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF17_Msk (0x20000UL) /*!< LIMEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF18_Pos (18UL) /*!< LIMEXF18 (Bit 18) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF18_Msk (0x40000UL) /*!< LIMEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF20_Pos (20UL) /*!< LIMEXF20 (Bit 20) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF20_Msk (0x100000UL) /*!< LIMEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF21_Pos (21UL) /*!< LIMEXF21 (Bit 21) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF21_Msk (0x200000UL) /*!< LIMEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF22_Pos (22UL) /*!< LIMEXF22 (Bit 22) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF22_Msk (0x400000UL) /*!< LIMEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADLIMGRSCR ======================================================= */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Pos (0UL) /*!< LIMGRCn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Msk (0x1ffUL) /*!< LIMGRCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSCR0 ====================================================== */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Pos (0UL) /*!< LIMCHCn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Msk (0x7fffffUL) /*!< LIMCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADLIMEXSCR ======================================================= */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF4_Pos (4UL) /*!< LIMEXF4 (Bit 4) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF4_Msk (0x10UL) /*!< LIMEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF9_Pos (9UL) /*!< LIMEXF9 (Bit 9) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF9_Msk (0x200UL) /*!< LIMEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF16_Pos (16UL) /*!< LIMEXF16 (Bit 16) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF16_Msk (0x10000UL) /*!< LIMEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF17_Pos (17UL) /*!< LIMEXF17 (Bit 17) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF17_Msk (0x20000UL) /*!< LIMEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF18_Pos (18UL) /*!< LIMEXF18 (Bit 18) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF18_Msk (0x40000UL) /*!< LIMEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF20_Pos (20UL) /*!< LIMEXF20 (Bit 20) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF20_Msk (0x100000UL) /*!< LIMEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF21_Pos (21UL) /*!< LIMEXF21 (Bit 21) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF21_Msk (0x200000UL) /*!< LIMEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF22_Pos (22UL) /*!< LIMEXF22 (Bit 22) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF22_Msk (0x400000UL) /*!< LIMEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADSCANENDSR ====================================================== */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Pos (0UL) /*!< SCENDFn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Msk (0x1ffUL) /*!< SCENDFn (Bitfield-Mask: 0x1ff) */ +/* ===================================================== ADSCANENDSCR ====================================================== */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Pos (0UL) /*!< SCENDCn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Msk (0x1ffUL) /*!< SCENDCn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC_B0_ADDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXDR ========================================================= */ + #define R_ADC_B0_ADEXDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADEXDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Pos (24UL) /*!< DIAGSR (Bit 24) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Msk (0x7000000UL) /*!< DIAGSR (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADEXDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADEXDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR0 ======================================================= */ + #define R_ADC_B0_ADFIFODR0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR0_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR0_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR0_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR0_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR0_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR1 ======================================================= */ + #define R_ADC_B0_ADFIFODR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR1_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR1_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR1_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR1_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR1_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR2 ======================================================= */ + #define R_ADC_B0_ADFIFODR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR2_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR2_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR2_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR2_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR2_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR3 ======================================================= */ + #define R_ADC_B0_ADFIFODR3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR3_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR3_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR3_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR3_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR3_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR4 ======================================================= */ + #define R_ADC_B0_ADFIFODR4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR4_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR4_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR4_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR4_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR4_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR5 ======================================================= */ + #define R_ADC_B0_ADFIFODR5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR5_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR5_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR5_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR5_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR5_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR6 ======================================================= */ + #define R_ADC_B0_ADFIFODR6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR6_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR6_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR6_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR6_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR6_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR7 ======================================================= */ + #define R_ADC_B0_ADFIFODR7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR7_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR7_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR7_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR7_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR7_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR8 ======================================================= */ + #define R_ADC_B0_ADFIFODR8_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR8_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR8_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR8_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR8_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR8_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */ + #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */ + #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */ + #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= DOSR ========================================================== */ + #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */ + #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSCR ========================================================= */ + #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */ + #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ======================================================== DODSR0 ========================================================= */ +/* ======================================================== DODSR1 ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ======================================================== RDR_BY ========================================================= */ + #define R_SCI_B0_RDR_BY_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_BY_RDAT_Msk (0xffUL) /*!< RDAT (Bitfield-Mask: 0xff) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== TDR_BY ========================================================= */ + #define R_SCI_B0_TDR_BY_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_BY_TDAT_Msk (0xffUL) /*!< TDAT (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_SCKSEL_Pos (19UL) /*!< SCKSEL (Bit 19) */ + #define R_SCI_B0_CCR4_SCKSEL_Msk (0x80000UL) /*!< SCKSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= CESR ========================================================== */ + #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */ + #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */ + #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCR ========================================================== */ + #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */ + #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */ + #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */ + #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */ + #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */ + #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */ + #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */ + #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================= XCR0 ========================================================== */ + #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */ + #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */ + #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */ + #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */ + #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */ + #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */ + #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */ + #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */ + #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */ + #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */ + #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */ + #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */ + #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */ +/* ========================================================= XCR1 ========================================================== */ + #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */ + #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */ + #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */ + #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */ + #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */ + #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */ +/* ========================================================= XCR2 ========================================================== */ + #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */ + #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */ + #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */ + #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================== MSR ========================================================== */ + #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */ + #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */ + #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= XSR0 ========================================================== */ + #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */ + #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */ + #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */ + #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */ + #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */ + #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */ + #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */ + #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */ + #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */ + #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */ + #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */ + #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */ + #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */ +/* ========================================================= XSR1 ========================================================== */ + #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */ + #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ +/* ========================================================= MFCLR ========================================================= */ + #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */ + #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */ + #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */ + #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */ + #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */ +/* ========================================================= XFCLR ========================================================= */ + #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */ + #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */ + #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */ + #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */ + #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */ + #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */ + #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */ + #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */ + #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDECR ========================================================= */ + #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */ + #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */ + #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */ + #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */ + #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */ + #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */ + #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */ + #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */ + #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */ + #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD0 ========================================================= */ + #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD1 ========================================================= */ + #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD2 ========================================================= */ + #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD3 ========================================================= */ + #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD4 ========================================================= */ + #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD5 ========================================================= */ + #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD6 ========================================================= */ + #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD7 ========================================================= */ + #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */ + #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */ + #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */ + #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */ + #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */ + #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */ + #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */ + #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */ + #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */ + #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */ + #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */ + #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */ + #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */ + #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */ + #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */ + #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */ + #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */ + #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */ + #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */ + #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Pos (0UL) /*!< CKSFTCS0 (Bit 0) */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Msk (0x1fUL) /*!< CKSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Pos (16UL) /*!< CKSFTCS1 (Bit 16) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Msk (0x1f0000UL) /*!< CKSFTCS1 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_ARBMD_Pos (0UL) /*!< ARBMD (Bit 0) */ + #define R_XSPI0_COMCFG_ARBMD_Msk (0x3UL) /*!< ARBMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Pos (4UL) /*!< ECSINTOUTEN (Bit 4) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Msk (0x30UL) /*!< ECSINTOUTEN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ======================================================== BMCFGCH ======================================================== */ + #define R_XSPI0_BMCFGCH_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFGCH_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFGCH_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFGCH_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Pos (24UL) /*!< CMBTIM (Bit 24) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Msk (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== ABMCFG ========================================================= */ + #define R_XSPI0_ABMCFG_ODRMD_Pos (0UL) /*!< ODRMD (Bit 0) */ + #define R_XSPI0_ABMCFG_ODRMD_Msk (0x3UL) /*!< ODRMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_ABMCFG_CHSEL_Pos (16UL) /*!< CHSEL (Bit 16) */ + #define R_XSPI0_ABMCFG_CHSEL_Msk (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Pos (0UL) /*!< CH0CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Msk (0x3UL) /*!< CH0CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Pos (2UL) /*!< CH0CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Msk (0xcUL) /*!< CH0CS1ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Pos (4UL) /*!< CH1CS0ACC (Bit 4) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Msk (0x30UL) /*!< CH1CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Pos (6UL) /*!< CH1CS1ACC (Bit 6) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Msk (0xc0UL) /*!< CH1CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Pos (8UL) /*!< MWRPUSHCH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Msk (0x100UL) /*!< MWRPUSHCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Pos (10UL) /*!< PBUFCLRCH (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Msk (0x400UL) /*!< PBUFCLRCH (Bitfield-Mask: 0x01) */ +/* ======================================================== CMCTLCH ======================================================== */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTLCH_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS_Pos (0UL) /*!< WPCS (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS_Msk (0x1UL) /*!< WPCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS_Pos (16UL) /*!< RSTCS (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS_Msk (0x10000UL) /*!< RSTCS (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACCCH_Pos (0UL) /*!< MEMACCCH (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACCCH_Msk (0x1UL) /*!< MEMACCCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNECH_Pos (4UL) /*!< PBUFNECH (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNECH_Msk (0x10UL) /*!< PBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Pos (6UL) /*!< WRBUFNECH (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Msk (0x40UL) /*!< WRBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS_Pos (16UL) /*!< ECSCS (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS_Msk (0x10000UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS_Pos (17UL) /*!< INTCS (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS_Msk (0x20000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS_Pos (18UL) /*!< RSTOCS (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS_Msk (0x40000UL) /*!< RSTOCS (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS_Pos (4UL) /*!< DSTOCS (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS_Msk (0x10UL) /*!< DSTOCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS_Pos (8UL) /*!< ECSCS (Bit 8) */ + #define R_XSPI0_INTS_ECSCS_Msk (0x100UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS_Pos (12UL) /*!< INTCS (Bit 12) */ + #define R_XSPI0_INTS_INTCS_Msk (0x1000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOFCH_Pos (16UL) /*!< BRGOFCH (Bit 16) */ + #define R_XSPI0_INTS_BRGOFCH_Msk (0x10000UL) /*!< BRGOFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUFCH_Pos (18UL) /*!< BRGUFCH (Bit 18) */ + #define R_XSPI0_INTS_BRGUFCH_Msk (0x40000UL) /*!< BRGUFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERRCH_Pos (20UL) /*!< BUSERRCH (Bit 20) */ + #define R_XSPI0_INTS_BUSERRCH_Msk (0x100000UL) /*!< BUSERRCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS_Pos (28UL) /*!< CAFAILCS (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS_Msk (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS_Pos (30UL) /*!< CASUCCS (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS_Msk (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCSC_Pos (4UL) /*!< DSTOCSC (Bit 4) */ + #define R_XSPI0_INTC_DSTOCSC_Msk (0x10UL) /*!< DSTOCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCSC_Pos (8UL) /*!< ECSCSC (Bit 8) */ + #define R_XSPI0_INTC_ECSCSC_Msk (0x100UL) /*!< ECSCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCSC_Pos (12UL) /*!< INTCSC (Bit 12) */ + #define R_XSPI0_INTC_INTCSC_Msk (0x1000UL) /*!< INTCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFCHC_Pos (16UL) /*!< BRGOFCHC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFCHC_Msk (0x10000UL) /*!< BRGOFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFCHC_Pos (18UL) /*!< BRGUFCHC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFCHC_Msk (0x40000UL) /*!< BRGUFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRCHC_Pos (20UL) /*!< BUSERRCHC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRCHC_Msk (0x100000UL) /*!< BUSERRCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCSC_Pos (28UL) /*!< CAFAILCSC (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCSC_Msk (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCSC_Pos (30UL) /*!< CASUCCSC (Bit 30) */ + #define R_XSPI0_INTC_CASUCCSC_Msk (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCSE_Pos (4UL) /*!< DSTOCSE (Bit 4) */ + #define R_XSPI0_INTE_DSTOCSE_Msk (0x10UL) /*!< DSTOCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCSE_Pos (8UL) /*!< ECSCSE (Bit 8) */ + #define R_XSPI0_INTE_ECSCSE_Msk (0x100UL) /*!< ECSCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCSE_Pos (12UL) /*!< INTCSE (Bit 12) */ + #define R_XSPI0_INTE_INTCSE_Msk (0x1000UL) /*!< INTCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFCHE_Pos (16UL) /*!< BRGOFCHE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFCHE_Msk (0x10000UL) /*!< BRGOFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFCHE_Pos (18UL) /*!< BRGUFCHE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFCHE_Msk (0x40000UL) /*!< BRGUFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRCHE_Pos (20UL) /*!< BUSERRCHE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRCHE_Msk (0x100000UL) /*!< BUSERRCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCSE_Pos (28UL) /*!< CAFAILCSE (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCSE_Msk (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCSE_Pos (30UL) /*!< CASUCCSE (Bit 30) */ + #define R_XSPI0_INTE_CASUCCSE_Msk (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DPHYREFCR ======================================================= */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Pos (0UL) /*!< RFREQ (Bit 0) */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Msk (0xffUL) /*!< RFREQ (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYPLFCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Pos (0UL) /*!< IDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Msk (0x3UL) /*!< IDIV (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Pos (8UL) /*!< NFMUL (Bit 8) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Msk (0x300UL) /*!< NFMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Pos (12UL) /*!< PMUL (Bit 12) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Msk (0x3000UL) /*!< PMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Pos (16UL) /*!< NMUL (Bit 16) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Msk (0x1ff0000UL) /*!< NMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================= DPHYPLOCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYESCCR ======================================================= */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Pos (0UL) /*!< ESCDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Msk (0x1fUL) /*!< ESCDIV (Bitfield-Mask: 0x1f) */ +/* ======================================================= DPHYPWRCR ======================================================= */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Pos (0UL) /*!< PWRSEN (Bit 0) */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Msk (0x1UL) /*!< PWRSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYSFR ======================================================== */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Pos (0UL) /*!< PWRSF (Bit 0) */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Msk (0x1UL) /*!< PWRSF (Bitfield-Mask: 0x01) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Pos (8UL) /*!< PLLSF (Bit 8) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Msk (0x100UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYOCR ======================================================== */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Pos (0UL) /*!< DPHYEN (Bit 0) */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Msk (0x1UL) /*!< DPHYEN (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYTIM1 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Pos (0UL) /*!< TINIT (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Msk (0x7ffffUL) /*!< TINIT (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DPHYTIM2 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Pos (0UL) /*!< TCLKPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Msk (0xffUL) /*!< TCLKPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Pos (8UL) /*!< TCLKSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Msk (0xff00UL) /*!< TCLKSETT (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Pos (16UL) /*!< TCLKMISS (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Msk (0xff0000UL) /*!< TCLKMISS (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM3 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Pos (0UL) /*!< THSPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Msk (0xffUL) /*!< THSPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Pos (8UL) /*!< THSSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Msk (0xff00UL) /*!< THSSETT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM4 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Pos (0UL) /*!< TCLKZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Msk (0xffUL) /*!< TCLKZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Pos (8UL) /*!< TCLKPRE (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Msk (0xff00UL) /*!< TCLKPRE (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Pos (16UL) /*!< TCLKPOST (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Msk (0xff0000UL) /*!< TCLKPOST (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Pos (24UL) /*!< TCLKTRL (Bit 24) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Msk (0xff000000UL) /*!< TCLKTRL (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM5 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Pos (0UL) /*!< THSZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Msk (0xffUL) /*!< THSZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Pos (8UL) /*!< THSTRL (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Msk (0xff00UL) /*!< THSTRL (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Pos (16UL) /*!< THSEXIT (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Msk (0xff0000UL) /*!< THSEXIT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM6 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Pos (0UL) /*!< TLPX (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Msk (0xffUL) /*!< TLPX (Bitfield-Mask: 0xff) */ +/* ======================================================== DPHYMDC ======================================================== */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Pos (0UL) /*!< MASTEREN (Bit 0) */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Msk (0x1UL) /*!< MASTEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_CSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MCG ========================================================== */ + #define R_MIPI_CSI_MCG_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_MIPI_CSI_MCG_VER_Msk (0xfUL) /*!< VER (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCG_SDLN_Pos (8UL) /*!< SDLN (Bit 8) */ + #define R_MIPI_CSI_MCG_SDLN_Msk (0xf00UL) /*!< SDLN (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCG_GSNM_Pos (16UL) /*!< GSNM (Bit 16) */ + #define R_MIPI_CSI_MCG_GSNM_Msk (0xff0000UL) /*!< GSNM (Bitfield-Mask: 0xff) */ +/* ========================================================= MCT0 ========================================================== */ + #define R_MIPI_CSI_MCT0_VDLN_Pos (0UL) /*!< VDLN (Bit 0) */ + #define R_MIPI_CSI_MCT0_VDLN_Msk (0xfUL) /*!< VDLN (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCT0_ZLMD_Pos (16UL) /*!< ZLMD (Bit 16) */ + #define R_MIPI_CSI_MCT0_ZLMD_Msk (0x10000UL) /*!< ZLMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_EDMD_Pos (17UL) /*!< EDMD (Bit 17) */ + #define R_MIPI_CSI_MCT0_EDMD_Msk (0x20000UL) /*!< EDMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_RVMD_Pos (19UL) /*!< RVMD (Bit 19) */ + #define R_MIPI_CSI_MCT0_RVMD_Msk (0x80000UL) /*!< RVMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_GRMD_Pos (20UL) /*!< GRMD (Bit 20) */ + #define R_MIPI_CSI_MCT0_GRMD_Msk (0x100000UL) /*!< GRMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_ECCV13_Pos (24UL) /*!< ECCV13 (Bit 24) */ + #define R_MIPI_CSI_MCT0_ECCV13_Msk (0x1000000UL) /*!< ECCV13 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_LFSREN_Pos (25UL) /*!< LFSREN (Bit 25) */ + #define R_MIPI_CSI_MCT0_LFSREN_Msk (0x2000000UL) /*!< LFSREN (Bitfield-Mask: 0x01) */ +/* ========================================================= MCT2 ========================================================== */ + #define R_MIPI_CSI_MCT2_FRRCLK_Pos (0UL) /*!< FRRCLK (Bit 0) */ + #define R_MIPI_CSI_MCT2_FRRCLK_Msk (0x1ffUL) /*!< FRRCLK (Bitfield-Mask: 0x1ff) */ + #define R_MIPI_CSI_MCT2_FRRSKW_Pos (16UL) /*!< FRRSKW (Bit 16) */ + #define R_MIPI_CSI_MCT2_FRRSKW_Msk (0x1ff0000UL) /*!< FRRSKW (Bitfield-Mask: 0x1ff) */ +/* ========================================================= MCT3 ========================================================== */ + #define R_MIPI_CSI_MCT3_RXEN_Pos (0UL) /*!< RXEN (Bit 0) */ + #define R_MIPI_CSI_MCT3_RXEN_Msk (0x1UL) /*!< RXEN (Bitfield-Mask: 0x01) */ +/* ========================================================= RTCT ========================================================== */ + #define R_MIPI_CSI_RTCT_VSRST_Pos (0UL) /*!< VSRST (Bit 0) */ + #define R_MIPI_CSI_RTCT_VSRST_Msk (0x1UL) /*!< VSRST (Bitfield-Mask: 0x01) */ +/* ========================================================= RTST ========================================================== */ + #define R_MIPI_CSI_RTST_VSRSTS_Pos (0UL) /*!< VSRSTS (Bit 0) */ + #define R_MIPI_CSI_RTST_VSRSTS_Msk (0x1UL) /*!< VSRSTS (Bitfield-Mask: 0x01) */ +/* ========================================================= EPCT ========================================================== */ + #define R_MIPI_CSI_EPCT_SLP_Pos (0UL) /*!< SLP (Bit 0) */ + #define R_MIPI_CSI_EPCT_SLP_Msk (0x7fffUL) /*!< SLP (Bitfield-Mask: 0x7fff) */ + #define R_MIPI_CSI_EPCT_EPDOP_Pos (15UL) /*!< EPDOP (Bit 15) */ + #define R_MIPI_CSI_EPCT_EPDOP_Msk (0x8000UL) /*!< EPDOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_EPCT_SSP_Pos (16UL) /*!< SSP (Bit 16) */ + #define R_MIPI_CSI_EPCT_SSP_Msk (0x7fff0000UL) /*!< SSP (Bitfield-Mask: 0x7fff) */ + #define R_MIPI_CSI_EPCT_EPDEN_Pos (31UL) /*!< EPDEN (Bit 31) */ + #define R_MIPI_CSI_EPCT_EPDEN_Msk (0x80000000UL) /*!< EPDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= EMCT ========================================================== */ + #define R_MIPI_CSI_EMCT_VLSIEN_Pos (4UL) /*!< VLSIEN (Bit 4) */ + #define R_MIPI_CSI_EMCT_VLSIEN_Msk (0x30UL) /*!< VLSIEN (Bitfield-Mask: 0x03) */ + #define R_MIPI_CSI_EMCT_EOTPEN_Pos (6UL) /*!< EOTPEN (Bit 6) */ + #define R_MIPI_CSI_EMCT_EOTPEN_Msk (0x40UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= MIST ========================================================== */ + #define R_MIPI_CSI_MIST_DL0S_Pos (0UL) /*!< DL0S (Bit 0) */ + #define R_MIPI_CSI_MIST_DL0S_Msk (0x1UL) /*!< DL0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_DL1S_Pos (1UL) /*!< DL1S (Bit 1) */ + #define R_MIPI_CSI_MIST_DL1S_Msk (0x2UL) /*!< DL1S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_PMS_Pos (8UL) /*!< PMS (Bit 8) */ + #define R_MIPI_CSI_MIST_PMS_Msk (0x100UL) /*!< PMS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_GSTS_Pos (9UL) /*!< GSTS (Bit 9) */ + #define R_MIPI_CSI_MIST_GSTS_Msk (0x200UL) /*!< GSTS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_RXS_Pos (10UL) /*!< RXS (Bit 10) */ + #define R_MIPI_CSI_MIST_RXS_Msk (0x400UL) /*!< RXS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC0S_Pos (16UL) /*!< VC0S (Bit 16) */ + #define R_MIPI_CSI_MIST_VC0S_Msk (0x10000UL) /*!< VC0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC1S_Pos (17UL) /*!< VC1S (Bit 17) */ + #define R_MIPI_CSI_MIST_VC1S_Msk (0x20000UL) /*!< VC1S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC2S_Pos (18UL) /*!< VC2S (Bit 18) */ + #define R_MIPI_CSI_MIST_VC2S_Msk (0x40000UL) /*!< VC2S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC3S_Pos (19UL) /*!< VC3S (Bit 19) */ + #define R_MIPI_CSI_MIST_VC3S_Msk (0x80000UL) /*!< VC3S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC4S_Pos (20UL) /*!< VC4S (Bit 20) */ + #define R_MIPI_CSI_MIST_VC4S_Msk (0x100000UL) /*!< VC4S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC5S_Pos (21UL) /*!< VC5S (Bit 21) */ + #define R_MIPI_CSI_MIST_VC5S_Msk (0x200000UL) /*!< VC5S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC6S_Pos (22UL) /*!< VC6S (Bit 22) */ + #define R_MIPI_CSI_MIST_VC6S_Msk (0x400000UL) /*!< VC6S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC7S_Pos (23UL) /*!< VC7S (Bit 23) */ + #define R_MIPI_CSI_MIST_VC7S_Msk (0x800000UL) /*!< VC7S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC8S_Pos (24UL) /*!< VC8S (Bit 24) */ + #define R_MIPI_CSI_MIST_VC8S_Msk (0x1000000UL) /*!< VC8S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC9S_Pos (25UL) /*!< VC9S (Bit 25) */ + #define R_MIPI_CSI_MIST_VC9S_Msk (0x2000000UL) /*!< VC9S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC10S_Pos (26UL) /*!< VC10S (Bit 26) */ + #define R_MIPI_CSI_MIST_VC10S_Msk (0x4000000UL) /*!< VC10S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC11S_Pos (27UL) /*!< VC11S (Bit 27) */ + #define R_MIPI_CSI_MIST_VC11S_Msk (0x8000000UL) /*!< VC11S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC12S_Pos (28UL) /*!< VC12S (Bit 28) */ + #define R_MIPI_CSI_MIST_VC12S_Msk (0x10000000UL) /*!< VC12S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC13S_Pos (29UL) /*!< VC13S (Bit 29) */ + #define R_MIPI_CSI_MIST_VC13S_Msk (0x20000000UL) /*!< VC13S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC14S_Pos (30UL) /*!< VC14S (Bit 30) */ + #define R_MIPI_CSI_MIST_VC14S_Msk (0x40000000UL) /*!< VC14S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC15S_Pos (31UL) /*!< VC15S (Bit 31) */ + #define R_MIPI_CSI_MIST_VC15S_Msk (0x80000000UL) /*!< VC15S (Bitfield-Mask: 0x01) */ +/* ========================================================= DTEL ========================================================== */ + #define R_MIPI_CSI_DTEL_DTEN_Pos (0UL) /*!< DTEN (Bit 0) */ + #define R_MIPI_CSI_DTEL_DTEN_Msk (0xffffffffUL) /*!< DTEN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEH ========================================================== */ + #define R_MIPI_CSI_DTEH_DTEN_Pos (0UL) /*!< DTEN (Bit 0) */ + #define R_MIPI_CSI_DTEH_DTEN_Msk (0xffffffffUL) /*!< DTEN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RXST ========================================================== */ + #define R_MIPI_CSI_RXST_FRM0_Pos (0UL) /*!< FRM0 (Bit 0) */ + #define R_MIPI_CSI_RXST_FRM0_Msk (0x1UL) /*!< FRM0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM1_Pos (1UL) /*!< FRM1 (Bit 1) */ + #define R_MIPI_CSI_RXST_FRM1_Msk (0x2UL) /*!< FRM1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM2_Pos (2UL) /*!< FRM2 (Bit 2) */ + #define R_MIPI_CSI_RXST_FRM2_Msk (0x4UL) /*!< FRM2 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM3_Pos (3UL) /*!< FRM3 (Bit 3) */ + #define R_MIPI_CSI_RXST_FRM3_Msk (0x8UL) /*!< FRM3 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM4_Pos (4UL) /*!< FRM4 (Bit 4) */ + #define R_MIPI_CSI_RXST_FRM4_Msk (0x10UL) /*!< FRM4 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM5_Pos (5UL) /*!< FRM5 (Bit 5) */ + #define R_MIPI_CSI_RXST_FRM5_Msk (0x20UL) /*!< FRM5 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM6_Pos (6UL) /*!< FRM6 (Bit 6) */ + #define R_MIPI_CSI_RXST_FRM6_Msk (0x40UL) /*!< FRM6 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM7_Pos (7UL) /*!< FRM7 (Bit 7) */ + #define R_MIPI_CSI_RXST_FRM7_Msk (0x80UL) /*!< FRM7 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM8_Pos (8UL) /*!< FRM8 (Bit 8) */ + #define R_MIPI_CSI_RXST_FRM8_Msk (0x100UL) /*!< FRM8 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM9_Pos (9UL) /*!< FRM9 (Bit 9) */ + #define R_MIPI_CSI_RXST_FRM9_Msk (0x200UL) /*!< FRM9 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM10_Pos (10UL) /*!< FRM10 (Bit 10) */ + #define R_MIPI_CSI_RXST_FRM10_Msk (0x400UL) /*!< FRM10 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM11_Pos (11UL) /*!< FRM11 (Bit 11) */ + #define R_MIPI_CSI_RXST_FRM11_Msk (0x800UL) /*!< FRM11 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM12_Pos (12UL) /*!< FRM12 (Bit 12) */ + #define R_MIPI_CSI_RXST_FRM12_Msk (0x1000UL) /*!< FRM12 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM13_Pos (13UL) /*!< FRM13 (Bit 13) */ + #define R_MIPI_CSI_RXST_FRM13_Msk (0x2000UL) /*!< FRM13 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM14_Pos (14UL) /*!< FRM14 (Bit 14) */ + #define R_MIPI_CSI_RXST_FRM14_Msk (0x4000UL) /*!< FRM14 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM15_Pos (15UL) /*!< FRM15 (Bit 15) */ + #define R_MIPI_CSI_RXST_FRM15_Msk (0x8000UL) /*!< FRM15 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_RACT_Pos (16UL) /*!< RACT (Bit 16) */ + #define R_MIPI_CSI_RXST_RACT_Msk (0x10000UL) /*!< RACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_RACTDET_Pos (17UL) /*!< RACTDET (Bit 17) */ + #define R_MIPI_CSI_RXST_RACTDET_Msk (0x20000UL) /*!< RACTDET (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSC ========================================================== */ + #define R_MIPI_CSI_RXSC_RACTDETC_Pos (17UL) /*!< RACTDETC (Bit 17) */ + #define R_MIPI_CSI_RXSC_RACTDETC_Msk (0x20000UL) /*!< RACTDETC (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIE ========================================================== */ + #define R_MIPI_CSI_RXIE_RACTDETE_Pos (17UL) /*!< RACTDETE (Bit 17) */ + #define R_MIPI_CSI_RXIE_RACTDETE_Msk (0x20000UL) /*!< RACTDETE (Bitfield-Mask: 0x01) */ +/* ========================================================= DLST0 ========================================================= */ + #define R_MIPI_CSI_DLST0_ESH_Pos (0UL) /*!< ESH (Bit 0) */ + #define R_MIPI_CSI_DLST0_ESH_Msk (0x1UL) /*!< ESH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ESS_Pos (1UL) /*!< ESS (Bit 1) */ + #define R_MIPI_CSI_DLST0_ESS_Msk (0x2UL) /*!< ESS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ECT_Pos (2UL) /*!< ECT (Bit 2) */ + #define R_MIPI_CSI_DLST0_ECT_Msk (0x4UL) /*!< ECT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_EES_Pos (3UL) /*!< EES (Bit 3) */ + #define R_MIPI_CSI_DLST0_EES_Msk (0x8UL) /*!< EES (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_EUL_Pos (16UL) /*!< EUL (Bit 16) */ + #define R_MIPI_CSI_DLST0_EUL_Msk (0x10000UL) /*!< EUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_RUL_Pos (17UL) /*!< RUL (Bit 17) */ + #define R_MIPI_CSI_DLST0_RUL_Msk (0x20000UL) /*!< RUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ULP_Pos (24UL) /*!< ULP (Bit 24) */ + #define R_MIPI_CSI_DLST0_ULP_Msk (0x1000000UL) /*!< ULP (Bitfield-Mask: 0x01) */ +/* ========================================================= DLST1 ========================================================= */ + #define R_MIPI_CSI_DLST1_ESH_Pos (0UL) /*!< ESH (Bit 0) */ + #define R_MIPI_CSI_DLST1_ESH_Msk (0x1UL) /*!< ESH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ESS_Pos (1UL) /*!< ESS (Bit 1) */ + #define R_MIPI_CSI_DLST1_ESS_Msk (0x2UL) /*!< ESS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ECT_Pos (2UL) /*!< ECT (Bit 2) */ + #define R_MIPI_CSI_DLST1_ECT_Msk (0x4UL) /*!< ECT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_EES_Pos (3UL) /*!< EES (Bit 3) */ + #define R_MIPI_CSI_DLST1_EES_Msk (0x8UL) /*!< EES (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_EUL_Pos (16UL) /*!< EUL (Bit 16) */ + #define R_MIPI_CSI_DLST1_EUL_Msk (0x10000UL) /*!< EUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_RUL_Pos (17UL) /*!< RUL (Bit 17) */ + #define R_MIPI_CSI_DLST1_RUL_Msk (0x20000UL) /*!< RUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ULP_Pos (24UL) /*!< ULP (Bit 24) */ + #define R_MIPI_CSI_DLST1_ULP_Msk (0x1000000UL) /*!< ULP (Bitfield-Mask: 0x01) */ +/* ========================================================= DLSC0 ========================================================= */ + #define R_MIPI_CSI_DLSC0_ESHC_Pos (0UL) /*!< ESHC (Bit 0) */ + #define R_MIPI_CSI_DLSC0_ESHC_Msk (0x1UL) /*!< ESHC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_ESSC_Pos (1UL) /*!< ESSC (Bit 1) */ + #define R_MIPI_CSI_DLSC0_ESSC_Msk (0x2UL) /*!< ESSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_ECTC_Pos (2UL) /*!< ECTC (Bit 2) */ + #define R_MIPI_CSI_DLSC0_ECTC_Msk (0x4UL) /*!< ECTC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_EESC_Pos (3UL) /*!< EESC (Bit 3) */ + #define R_MIPI_CSI_DLSC0_EESC_Msk (0x8UL) /*!< EESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_EULC_Pos (16UL) /*!< EULC (Bit 16) */ + #define R_MIPI_CSI_DLSC0_EULC_Msk (0x10000UL) /*!< EULC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_RULC_Pos (17UL) /*!< RULC (Bit 17) */ + #define R_MIPI_CSI_DLSC0_RULC_Msk (0x20000UL) /*!< RULC (Bitfield-Mask: 0x01) */ +/* ========================================================= DLSC1 ========================================================= */ + #define R_MIPI_CSI_DLSC1_ESHC_Pos (0UL) /*!< ESHC (Bit 0) */ + #define R_MIPI_CSI_DLSC1_ESHC_Msk (0x1UL) /*!< ESHC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_ESSC_Pos (1UL) /*!< ESSC (Bit 1) */ + #define R_MIPI_CSI_DLSC1_ESSC_Msk (0x2UL) /*!< ESSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_ECTC_Pos (2UL) /*!< ECTC (Bit 2) */ + #define R_MIPI_CSI_DLSC1_ECTC_Msk (0x4UL) /*!< ECTC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_EESC_Pos (3UL) /*!< EESC (Bit 3) */ + #define R_MIPI_CSI_DLSC1_EESC_Msk (0x8UL) /*!< EESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_EULC_Pos (16UL) /*!< EULC (Bit 16) */ + #define R_MIPI_CSI_DLSC1_EULC_Msk (0x10000UL) /*!< EULC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_RULC_Pos (17UL) /*!< RULC (Bit 17) */ + #define R_MIPI_CSI_DLSC1_RULC_Msk (0x20000UL) /*!< RULC (Bitfield-Mask: 0x01) */ +/* ========================================================= DLIE0 ========================================================= */ + #define R_MIPI_CSI_DLIE0_ESHE_Pos (0UL) /*!< ESHE (Bit 0) */ + #define R_MIPI_CSI_DLIE0_ESHE_Msk (0x1UL) /*!< ESHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_ESSE_Pos (1UL) /*!< ESSE (Bit 1) */ + #define R_MIPI_CSI_DLIE0_ESSE_Msk (0x2UL) /*!< ESSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_ECTE_Pos (2UL) /*!< ECTE (Bit 2) */ + #define R_MIPI_CSI_DLIE0_ECTE_Msk (0x4UL) /*!< ECTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_EESE_Pos (3UL) /*!< EESE (Bit 3) */ + #define R_MIPI_CSI_DLIE0_EESE_Msk (0x8UL) /*!< EESE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_EULE_Pos (16UL) /*!< EULE (Bit 16) */ + #define R_MIPI_CSI_DLIE0_EULE_Msk (0x10000UL) /*!< EULE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_RULE_Pos (17UL) /*!< RULE (Bit 17) */ + #define R_MIPI_CSI_DLIE0_RULE_Msk (0x20000UL) /*!< RULE (Bitfield-Mask: 0x01) */ +/* ========================================================= DLIE1 ========================================================= */ + #define R_MIPI_CSI_DLIE1_ESHE_Pos (0UL) /*!< ESHE (Bit 0) */ + #define R_MIPI_CSI_DLIE1_ESHE_Msk (0x1UL) /*!< ESHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_ESSE_Pos (1UL) /*!< ESSE (Bit 1) */ + #define R_MIPI_CSI_DLIE1_ESSE_Msk (0x2UL) /*!< ESSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_ECTE_Pos (2UL) /*!< ECTE (Bit 2) */ + #define R_MIPI_CSI_DLIE1_ECTE_Msk (0x4UL) /*!< ECTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_EESE_Pos (3UL) /*!< EESE (Bit 3) */ + #define R_MIPI_CSI_DLIE1_EESE_Msk (0x8UL) /*!< EESE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_EULE_Pos (16UL) /*!< EULE (Bit 16) */ + #define R_MIPI_CSI_DLIE1_EULE_Msk (0x10000UL) /*!< EULE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_RULE_Pos (17UL) /*!< RULE (Bit 17) */ + #define R_MIPI_CSI_DLIE1_RULE_Msk (0x20000UL) /*!< RULE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST0 ========================================================= */ + #define R_MIPI_CSI_VCST0_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST0_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST0_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST0_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST0_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST0_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST0_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST0_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST0_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST0_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST0_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST0_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST0_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST0_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST0_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST0_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST1 ========================================================= */ + #define R_MIPI_CSI_VCST1_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST1_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST1_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST1_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST1_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST1_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST1_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST1_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST1_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST1_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST1_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST1_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST1_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST1_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST1_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST1_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST2 ========================================================= */ + #define R_MIPI_CSI_VCST2_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST2_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST2_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST2_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST2_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST2_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST2_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST2_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST2_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST2_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST2_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST2_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST2_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST2_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST2_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST2_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST3 ========================================================= */ + #define R_MIPI_CSI_VCST3_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST3_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST3_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST3_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST3_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST3_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST3_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST3_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST3_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST3_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST3_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST3_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST3_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST3_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST3_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST3_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST4 ========================================================= */ + #define R_MIPI_CSI_VCST4_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST4_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST4_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST4_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST4_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST4_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST4_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST4_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST4_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST4_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST4_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST4_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST4_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST4_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST4_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST4_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST5 ========================================================= */ + #define R_MIPI_CSI_VCST5_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST5_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST5_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST5_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST5_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST5_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST5_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST5_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST5_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST5_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST5_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST5_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST5_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST5_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST5_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST5_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST6 ========================================================= */ + #define R_MIPI_CSI_VCST6_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST6_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST6_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST6_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST6_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST6_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST6_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST6_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST6_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST6_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST6_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST6_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST6_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST6_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST6_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST6_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST7 ========================================================= */ + #define R_MIPI_CSI_VCST7_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST7_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST7_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST7_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST7_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST7_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST7_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST7_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST7_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST7_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST7_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST7_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST7_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST7_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST7_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST7_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST8 ========================================================= */ + #define R_MIPI_CSI_VCST8_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST8_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST8_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST8_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST8_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST8_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST8_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST8_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST8_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST8_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST8_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST8_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST8_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST8_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST8_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST8_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST9 ========================================================= */ + #define R_MIPI_CSI_VCST9_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST9_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST9_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST9_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST9_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST9_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST9_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST9_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST9_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST9_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST9_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST9_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST9_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST9_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST9_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST9_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST10 ========================================================= */ + #define R_MIPI_CSI_VCST10_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST10_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST10_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST10_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST10_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST10_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST10_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST10_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST10_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST10_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST10_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST10_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST10_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST10_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST10_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST10_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST11 ========================================================= */ + #define R_MIPI_CSI_VCST11_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST11_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST11_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST11_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST11_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST11_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST11_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST11_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST11_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST11_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST11_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST11_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST11_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST11_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST11_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST11_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST12 ========================================================= */ + #define R_MIPI_CSI_VCST12_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST12_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST12_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST12_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST12_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST12_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST12_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST12_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST12_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST12_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST12_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST12_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST12_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST12_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST12_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST12_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST13 ========================================================= */ + #define R_MIPI_CSI_VCST13_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST13_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST13_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST13_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST13_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST13_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST13_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST13_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST13_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST13_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST13_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST13_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST13_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST13_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST13_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST13_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST14 ========================================================= */ + #define R_MIPI_CSI_VCST14_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST14_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST14_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST14_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST14_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST14_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST14_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST14_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST14_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST14_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST14_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST14_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST14_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST14_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST14_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST14_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST15 ========================================================= */ + #define R_MIPI_CSI_VCST15_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST15_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST15_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST15_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST15_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST15_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST15_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST15_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST15_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST15_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST15_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST15_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST15_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST15_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST15_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST15_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC0 ========================================================= */ + #define R_MIPI_CSI_VCSC0_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC0_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC0_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC0_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC0_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC0_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC0_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC0_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC0_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC0_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC0_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC0_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC0_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC0_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC0_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC0_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC0_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC0_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC1 ========================================================= */ + #define R_MIPI_CSI_VCSC1_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC1_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC1_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC1_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC1_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC1_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC1_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC1_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC1_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC1_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC1_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC1_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC1_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC1_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC1_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC1_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC1_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC1_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC2 ========================================================= */ + #define R_MIPI_CSI_VCSC2_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC2_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC2_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC2_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC2_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC2_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC2_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC2_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC2_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC2_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC2_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC2_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC2_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC2_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC2_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC2_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC2_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC2_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC3 ========================================================= */ + #define R_MIPI_CSI_VCSC3_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC3_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC3_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC3_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC3_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC3_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC3_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC3_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC3_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC3_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC3_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC3_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC3_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC3_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC3_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC3_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC3_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC3_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC4 ========================================================= */ + #define R_MIPI_CSI_VCSC4_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC4_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC4_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC4_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC4_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC4_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC4_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC4_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC4_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC4_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC4_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC4_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC4_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC4_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC4_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC4_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC4_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC4_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC5 ========================================================= */ + #define R_MIPI_CSI_VCSC5_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC5_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC5_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC5_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC5_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC5_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC5_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC5_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC5_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC5_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC5_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC5_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC5_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC5_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC5_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC5_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC5_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC5_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC6 ========================================================= */ + #define R_MIPI_CSI_VCSC6_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC6_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC6_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC6_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC6_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC6_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC6_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC6_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC6_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC6_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC6_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC6_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC6_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC6_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC6_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC6_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC6_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC6_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC7 ========================================================= */ + #define R_MIPI_CSI_VCSC7_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC7_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC7_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC7_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC7_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC7_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC7_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC7_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC7_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC7_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC7_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC7_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC7_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC7_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC7_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC7_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC7_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC7_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC8 ========================================================= */ + #define R_MIPI_CSI_VCSC8_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC8_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC8_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC8_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC8_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC8_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC8_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC8_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC8_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC8_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC8_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC8_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC8_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC8_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC8_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC8_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC8_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC8_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC9 ========================================================= */ + #define R_MIPI_CSI_VCSC9_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC9_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC9_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC9_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC9_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC9_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC9_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC9_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC9_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC9_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC9_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC9_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC9_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC9_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC9_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC9_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC9_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC9_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC10 ========================================================= */ + #define R_MIPI_CSI_VCSC10_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC10_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC10_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC10_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC10_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC10_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC10_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC10_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC10_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC10_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC10_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC10_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC10_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC10_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC10_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC10_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC10_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC10_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC11 ========================================================= */ + #define R_MIPI_CSI_VCSC11_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC11_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC11_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC11_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC11_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC11_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC11_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC11_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC11_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC11_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC11_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC11_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC11_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC11_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC11_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC11_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC11_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC11_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC12 ========================================================= */ + #define R_MIPI_CSI_VCSC12_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC12_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC12_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC12_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC12_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC12_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC12_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC12_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC12_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC12_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC12_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC12_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC12_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC12_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC12_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC12_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC12_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC12_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC13 ========================================================= */ + #define R_MIPI_CSI_VCSC13_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC13_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC13_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC13_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC13_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC13_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC13_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC13_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC13_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC13_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC13_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC13_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC13_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC13_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC13_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC13_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC13_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC13_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC14 ========================================================= */ + #define R_MIPI_CSI_VCSC14_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC14_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC14_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC14_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC14_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC14_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC14_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC14_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC14_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC14_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC14_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC14_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC14_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC14_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC14_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC14_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC14_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC14_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC15 ========================================================= */ + #define R_MIPI_CSI_VCSC15_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC15_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC15_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC15_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC15_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC15_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC15_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC15_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC15_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC15_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC15_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC15_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC15_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC15_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC15_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC15_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC15_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC15_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE0 ========================================================= */ + #define R_MIPI_CSI_VCIE0_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE0_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE0_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE0_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE0_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE0_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE0_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE0_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE0_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE0_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE0_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE0_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE0_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE0_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE0_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE0_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE1 ========================================================= */ + #define R_MIPI_CSI_VCIE1_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE1_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE1_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE1_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE1_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE1_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE1_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE1_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE1_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE1_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE1_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE1_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE1_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE1_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE1_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE1_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE2 ========================================================= */ + #define R_MIPI_CSI_VCIE2_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE2_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE2_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE2_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE2_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE2_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE2_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE2_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE2_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE2_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE2_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE2_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE2_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE2_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE2_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE2_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE3 ========================================================= */ + #define R_MIPI_CSI_VCIE3_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE3_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE3_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE3_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE3_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE3_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE3_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE3_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE3_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE3_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE3_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE3_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE3_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE3_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE3_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE3_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE4 ========================================================= */ + #define R_MIPI_CSI_VCIE4_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE4_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE4_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE4_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE4_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE4_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE4_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE4_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE4_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE4_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE4_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE4_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE4_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE4_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE4_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE4_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE5 ========================================================= */ + #define R_MIPI_CSI_VCIE5_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE5_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE5_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE5_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE5_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE5_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE5_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE5_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE5_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE5_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE5_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE5_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE5_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE5_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE5_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE5_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE6 ========================================================= */ + #define R_MIPI_CSI_VCIE6_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE6_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE6_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE6_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE6_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE6_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE6_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE6_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE6_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE6_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE6_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE6_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE6_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE6_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE6_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE6_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE7 ========================================================= */ + #define R_MIPI_CSI_VCIE7_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE7_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE7_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE7_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE7_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE7_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE7_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE7_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE7_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE7_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE7_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE7_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE7_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE7_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE7_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE7_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE8 ========================================================= */ + #define R_MIPI_CSI_VCIE8_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE8_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE8_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE8_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE8_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE8_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE8_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE8_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE8_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE8_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE8_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE8_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE8_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE8_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE8_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE8_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE9 ========================================================= */ + #define R_MIPI_CSI_VCIE9_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE9_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE9_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE9_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE9_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE9_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE9_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE9_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE9_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE9_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE9_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE9_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE9_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE9_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE9_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE9_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE10 ========================================================= */ + #define R_MIPI_CSI_VCIE10_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE10_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE10_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE10_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE10_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE10_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE10_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE10_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE10_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE10_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE10_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE10_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE10_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE10_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE10_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE10_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE11 ========================================================= */ + #define R_MIPI_CSI_VCIE11_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE11_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE11_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE11_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE11_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE11_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE11_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE11_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE11_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE11_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE11_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE11_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE11_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE11_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE11_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE11_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE12 ========================================================= */ + #define R_MIPI_CSI_VCIE12_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE12_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE12_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE12_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE12_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE12_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE12_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE12_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE12_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE12_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE12_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE12_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE12_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE12_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE12_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE12_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE13 ========================================================= */ + #define R_MIPI_CSI_VCIE13_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE13_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE13_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE13_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE13_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE13_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE13_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE13_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE13_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE13_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE13_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE13_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE13_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE13_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE13_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE13_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE14 ========================================================= */ + #define R_MIPI_CSI_VCIE14_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE14_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE14_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE14_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE14_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE14_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE14_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE14_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE14_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE14_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE14_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE14_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE14_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE14_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE14_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE14_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE15 ========================================================= */ + #define R_MIPI_CSI_VCIE15_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE15_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE15_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE15_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE15_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE15_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE15_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE15_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE15_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE15_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE15_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE15_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE15_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE15_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE15_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE15_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= PMST ========================================================== */ + #define R_MIPI_CSI_PMST_DSX_Pos (0UL) /*!< DSX (Bit 0) */ + #define R_MIPI_CSI_PMST_DSX_Msk (0x1UL) /*!< DSX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DSN_Pos (1UL) /*!< DSN (Bit 1) */ + #define R_MIPI_CSI_PMST_DSN_Msk (0x2UL) /*!< DSN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CSX_Pos (2UL) /*!< CSX (Bit 2) */ + #define R_MIPI_CSI_PMST_CSX_Msk (0x4UL) /*!< CSX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CSN_Pos (3UL) /*!< CSN (Bit 3) */ + #define R_MIPI_CSI_PMST_CSN_Msk (0x8UL) /*!< CSN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DUX_Pos (4UL) /*!< DUX (Bit 4) */ + #define R_MIPI_CSI_PMST_DUX_Msk (0x10UL) /*!< DUX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DUN_Pos (5UL) /*!< DUN (Bit 5) */ + #define R_MIPI_CSI_PMST_DUN_Msk (0x20UL) /*!< DUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CUX_Pos (6UL) /*!< CUX (Bit 6) */ + #define R_MIPI_CSI_PMST_CUX_Msk (0x40UL) /*!< CUX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CUN_Pos (7UL) /*!< CUN (Bit 7) */ + #define R_MIPI_CSI_PMST_CUN_Msk (0x80UL) /*!< CUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CLSS_Pos (14UL) /*!< CLSS (Bit 14) */ + #define R_MIPI_CSI_PMST_CLSS_Msk (0x4000UL) /*!< CLSS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CLUL_Pos (15UL) /*!< CLUL (Bit 15) */ + #define R_MIPI_CSI_PMST_CLUL_Msk (0x8000UL) /*!< CLUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DLSS_Pos (16UL) /*!< DLSS (Bit 16) */ + #define R_MIPI_CSI_PMST_DLSS_Msk (0x30000UL) /*!< DLSS (Bitfield-Mask: 0x03) */ + #define R_MIPI_CSI_PMST_DLUL_Pos (24UL) /*!< DLUL (Bit 24) */ + #define R_MIPI_CSI_PMST_DLUL_Msk (0x3000000UL) /*!< DLUL (Bitfield-Mask: 0x03) */ +/* ========================================================= PMSC ========================================================== */ + #define R_MIPI_CSI_PMSC_DSXC_Pos (0UL) /*!< DSXC (Bit 0) */ + #define R_MIPI_CSI_PMSC_DSXC_Msk (0x1UL) /*!< DSXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DSNC_Pos (1UL) /*!< DSNC (Bit 1) */ + #define R_MIPI_CSI_PMSC_DSNC_Msk (0x2UL) /*!< DSNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CSXC_Pos (2UL) /*!< CSXC (Bit 2) */ + #define R_MIPI_CSI_PMSC_CSXC_Msk (0x4UL) /*!< CSXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CSNC_Pos (3UL) /*!< CSNC (Bit 3) */ + #define R_MIPI_CSI_PMSC_CSNC_Msk (0x8UL) /*!< CSNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DUXC_Pos (4UL) /*!< DUXC (Bit 4) */ + #define R_MIPI_CSI_PMSC_DUXC_Msk (0x10UL) /*!< DUXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DUNC_Pos (5UL) /*!< DUNC (Bit 5) */ + #define R_MIPI_CSI_PMSC_DUNC_Msk (0x20UL) /*!< DUNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CUXC_Pos (6UL) /*!< CUXC (Bit 6) */ + #define R_MIPI_CSI_PMSC_CUXC_Msk (0x40UL) /*!< CUXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CUNC_Pos (7UL) /*!< CUNC (Bit 7) */ + #define R_MIPI_CSI_PMSC_CUNC_Msk (0x80UL) /*!< CUNC (Bitfield-Mask: 0x01) */ +/* ========================================================= PMIE ========================================================== */ + #define R_MIPI_CSI_PMIE_DSXE_Pos (0UL) /*!< DSXE (Bit 0) */ + #define R_MIPI_CSI_PMIE_DSXE_Msk (0x1UL) /*!< DSXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DSNE_Pos (1UL) /*!< DSNE (Bit 1) */ + #define R_MIPI_CSI_PMIE_DSNE_Msk (0x2UL) /*!< DSNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CSXE_Pos (2UL) /*!< CSXE (Bit 2) */ + #define R_MIPI_CSI_PMIE_CSXE_Msk (0x4UL) /*!< CSXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CSNE_Pos (3UL) /*!< CSNE (Bit 3) */ + #define R_MIPI_CSI_PMIE_CSNE_Msk (0x8UL) /*!< CSNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DUXE_Pos (4UL) /*!< DUXE (Bit 4) */ + #define R_MIPI_CSI_PMIE_DUXE_Msk (0x10UL) /*!< DUXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DUNE_Pos (5UL) /*!< DUNE (Bit 5) */ + #define R_MIPI_CSI_PMIE_DUNE_Msk (0x20UL) /*!< DUNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CUXE_Pos (6UL) /*!< CUXE (Bit 6) */ + #define R_MIPI_CSI_PMIE_CUXE_Msk (0x40UL) /*!< CUXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CUNE_Pos (7UL) /*!< CUNE (Bit 7) */ + #define R_MIPI_CSI_PMIE_CUNE_Msk (0x80UL) /*!< CUNE (Bitfield-Mask: 0x01) */ +/* ========================================================= GSCT ========================================================== */ + #define R_MIPI_CSI_GSCT_SHTH_Pos (0UL) /*!< SHTH (Bit 0) */ + #define R_MIPI_CSI_GSCT_SHTH_Msk (0x7fUL) /*!< SHTH (Bitfield-Mask: 0x7f) */ + #define R_MIPI_CSI_GSCT_GFIF_Pos (16UL) /*!< GFIF (Bit 16) */ + #define R_MIPI_CSI_GSCT_GFIF_Msk (0x10000UL) /*!< GFIF (Bitfield-Mask: 0x01) */ +/* ========================================================= GSST ========================================================== */ + #define R_MIPI_CSI_GSST_GNE_Pos (0UL) /*!< GNE (Bit 0) */ + #define R_MIPI_CSI_GSST_GNE_Msk (0x1UL) /*!< GNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_GTH_Pos (1UL) /*!< GTH (Bit 1) */ + #define R_MIPI_CSI_GSST_GTH_Msk (0x2UL) /*!< GTH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_GOV_Pos (4UL) /*!< GOV (Bit 4) */ + #define R_MIPI_CSI_GSST_GOV_Msk (0x10UL) /*!< GOV (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_MIPI_CSI_GSST_PNUM_Msk (0xff00UL) /*!< PNUM (Bitfield-Mask: 0xff) */ + #define R_MIPI_CSI_GSST_GCD_Pos (16UL) /*!< GCD (Bit 16) */ + #define R_MIPI_CSI_GSST_GCD_Msk (0x10000UL) /*!< GCD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_STRDS_Pos (17UL) /*!< STRDS (Bit 17) */ + #define R_MIPI_CSI_GSST_STRDS_Msk (0x20000UL) /*!< STRDS (Bitfield-Mask: 0x01) */ +/* ========================================================= GSSC ========================================================== */ + #define R_MIPI_CSI_GSSC_GOVC_Pos (4UL) /*!< GOVC (Bit 4) */ + #define R_MIPI_CSI_GSSC_GOVC_Msk (0x10UL) /*!< GOVC (Bitfield-Mask: 0x01) */ +/* ========================================================= GSIE ========================================================== */ + #define R_MIPI_CSI_GSIE_GNEE_Pos (0UL) /*!< GNEE (Bit 0) */ + #define R_MIPI_CSI_GSIE_GNEE_Msk (0x1UL) /*!< GNEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIE_GTHE_Pos (1UL) /*!< GTHE (Bit 1) */ + #define R_MIPI_CSI_GSIE_GTHE_Msk (0x2UL) /*!< GTHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIE_GOVE_Pos (4UL) /*!< GOVE (Bit 4) */ + #define R_MIPI_CSI_GSIE_GOVE_Msk (0x10UL) /*!< GOVE (Bitfield-Mask: 0x01) */ +/* ========================================================= GSHT ========================================================== */ + #define R_MIPI_CSI_GSHT_SPDT_Pos (0UL) /*!< SPDT (Bit 0) */ + #define R_MIPI_CSI_GSHT_SPDT_Msk (0xffffUL) /*!< SPDT (Bitfield-Mask: 0xffff) */ + #define R_MIPI_CSI_GSHT_DTYP_Pos (16UL) /*!< DTYP (Bit 16) */ + #define R_MIPI_CSI_GSHT_DTYP_Msk (0x3f0000UL) /*!< DTYP (Bitfield-Mask: 0x3f) */ + #define R_MIPI_CSI_GSHT_SPVC_Pos (24UL) /*!< SPVC (Bit 24) */ + #define R_MIPI_CSI_GSHT_SPVC_Msk (0xf000000UL) /*!< SPVC (Bitfield-Mask: 0x0f) */ +/* ========================================================= GSIU ========================================================== */ + #define R_MIPI_CSI_GSIU_FINC_Pos (0UL) /*!< FINC (Bit 0) */ + #define R_MIPI_CSI_GSIU_FINC_Msk (0x1UL) /*!< FINC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIU_GFCLR_Pos (8UL) /*!< GFCLR (Bit 8) */ + #define R_MIPI_CSI_GSIU_GFCLR_Msk (0x100UL) /*!< GFCLR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIU_GFEN_Pos (16UL) /*!< GFEN (Bit 16) */ + #define R_MIPI_CSI_GSIU_GFEN_Msk (0x10000UL) /*!< GFEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CAPSR ========================================================= */ + #define R_CEU_CAPSR_CE_Pos (0UL) /*!< CE (Bit 0) */ + #define R_CEU_CAPSR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPSR_CPKIL_Pos (16UL) /*!< CPKIL (Bit 16) */ + #define R_CEU_CAPSR_CPKIL_Msk (0x10000UL) /*!< CPKIL (Bitfield-Mask: 0x01) */ +/* ========================================================= CAPCR ========================================================= */ + #define R_CEU_CAPCR_CTNCP_Pos (16UL) /*!< CTNCP (Bit 16) */ + #define R_CEU_CAPCR_CTNCP_Msk (0x10000UL) /*!< CTNCP (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPCR_MTCM_Pos (20UL) /*!< MTCM (Bit 20) */ + #define R_CEU_CAPCR_MTCM_Msk (0x300000UL) /*!< MTCM (Bitfield-Mask: 0x03) */ + #define R_CEU_CAPCR_FDRP_Pos (24UL) /*!< FDRP (Bit 24) */ + #define R_CEU_CAPCR_FDRP_Msk (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff) */ +/* ========================================================= CAMCR ========================================================= */ + #define R_CEU_CAMCR_HDPOL_Pos (0UL) /*!< HDPOL (Bit 0) */ + #define R_CEU_CAMCR_HDPOL_Msk (0x1UL) /*!< HDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDPOL_Pos (1UL) /*!< VDPOL (Bit 1) */ + #define R_CEU_CAMCR_VDPOL_Msk (0x2UL) /*!< VDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_JPG_Pos (4UL) /*!< JPG (Bit 4) */ + #define R_CEU_CAMCR_JPG_Msk (0x30UL) /*!< JPG (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTARY_Pos (8UL) /*!< DTARY (Bit 8) */ + #define R_CEU_CAMCR_DTARY_Msk (0x300UL) /*!< DTARY (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTIF_Pos (12UL) /*!< DTIF (Bit 12) */ + #define R_CEU_CAMCR_DTIF_Msk (0x1000UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDPOL_Pos (16UL) /*!< FLDPOL (Bit 16) */ + #define R_CEU_CAMCR_FLDPOL_Msk (0x10000UL) /*!< FLDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_DSEL_Pos (24UL) /*!< DSEL (Bit 24) */ + #define R_CEU_CAMCR_DSEL_Msk (0x1000000UL) /*!< DSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDSEL_Pos (25UL) /*!< FLDSEL (Bit 25) */ + #define R_CEU_CAMCR_FLDSEL_Msk (0x2000000UL) /*!< FLDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_HDSEL_Pos (26UL) /*!< HDSEL (Bit 26) */ + #define R_CEU_CAMCR_HDSEL_Msk (0x4000000UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDSEL_Pos (27UL) /*!< VDSEL (Bit 27) */ + #define R_CEU_CAMCR_VDSEL_Msk (0x8000000UL) /*!< VDSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCYR ========================================================= */ + #define R_CEU_CMCYR_HCYL_Pos (0UL) /*!< HCYL (Bit 0) */ + #define R_CEU_CMCYR_HCYL_Msk (0x3fffUL) /*!< HCYL (Bitfield-Mask: 0x3fff) */ + #define R_CEU_CMCYR_VCYL_Pos (16UL) /*!< VCYL (Bit 16) */ + #define R_CEU_CMCYR_VCYL_Msk (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CAMOR ========================================================= */ + #define R_CEU_CAMOR_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAPWR ========================================================= */ + #define R_CEU_CAPWR_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAIFR ========================================================= */ + #define R_CEU_CAIFR_FCI_Pos (0UL) /*!< FCI (Bit 0) */ + #define R_CEU_CAIFR_FCI_Msk (0x3UL) /*!< FCI (Bitfield-Mask: 0x03) */ + #define R_CEU_CAIFR_CIM_Pos (4UL) /*!< CIM (Bit 4) */ + #define R_CEU_CAIFR_CIM_Msk (0x10UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_CEU_CAIFR_IFS_Pos (8UL) /*!< IFS (Bit 8) */ + #define R_CEU_CAIFR_IFS_Msk (0x100UL) /*!< IFS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCNTR ========================================================= */ + #define R_CEU_CRCNTR_RC_Pos (0UL) /*!< RC (Bit 0) */ + #define R_CEU_CRCNTR_RC_Msk (0x1UL) /*!< RC (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_CEU_CRCNTR_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RVS_Pos (4UL) /*!< RVS (Bit 4) */ + #define R_CEU_CRCNTR_RVS_Msk (0x10UL) /*!< RVS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCMPR ========================================================= */ + #define R_CEU_CRCMPR_RA_Pos (0UL) /*!< RA (Bit 0) */ + #define R_CEU_CRCMPR_RA_Msk (0x1UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ========================================================= CFLCR ========================================================= */ + #define R_CEU_CFLCR_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFSZR ========================================================= */ + #define R_CEU_CFSZR_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ========================================================= CDWDR ========================================================= */ + #define R_CEU_CDWDR_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ========================================================= CDAYR ========================================================= */ + #define R_CEU_CDAYR_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDACR ========================================================= */ + #define R_CEU_CDACR_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBYR ========================================================= */ + #define R_CEU_CDBYR_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBCR ========================================================= */ + #define R_CEU_CDBCR_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CBDSR ========================================================= */ + #define R_CEU_CBDSR_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= CFWCR ========================================================= */ + #define R_CEU_CFWCR_FWE_Pos (0UL) /*!< FWE (Bit 0) */ + #define R_CEU_CFWCR_FWE_Msk (0x1UL) /*!< FWE (Bitfield-Mask: 0x01) */ + #define R_CEU_CFWCR_FWV_Pos (5UL) /*!< FWV (Bit 5) */ + #define R_CEU_CFWCR_FWV_Msk (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff) */ +/* ========================================================= CLFCR ========================================================= */ + #define R_CEU_CLFCR_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ========================================================= CDOCR ========================================================= */ + #define R_CEU_CDOCR_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ========================================================= CEIER ========================================================= */ + #define R_CEU_CEIER_CPEIE_Pos (0UL) /*!< CPEIE (Bit 0) */ + #define R_CEU_CEIER_CPEIE_Msk (0x1UL) /*!< CPEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CFEIE_Pos (1UL) /*!< CFEIE (Bit 1) */ + #define R_CEU_CEIER_CFEIE_Msk (0x2UL) /*!< CFEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGRWIE_Pos (4UL) /*!< IGRWIE (Bit 4) */ + #define R_CEU_CEIER_IGRWIE_Msk (0x10UL) /*!< IGRWIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_HDIE_Pos (8UL) /*!< HDIE (Bit 8) */ + #define R_CEU_CEIER_HDIE_Msk (0x100UL) /*!< HDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VDIE_Pos (9UL) /*!< VDIE (Bit 9) */ + #define R_CEU_CEIER_VDIE_Msk (0x200UL) /*!< VDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE1IE_Pos (12UL) /*!< CPBE1IE (Bit 12) */ + #define R_CEU_CEIER_CPBE1IE_Msk (0x1000UL) /*!< CPBE1IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE2IE_Pos (13UL) /*!< CPBE2IE (Bit 13) */ + #define R_CEU_CEIER_CPBE2IE_Msk (0x2000UL) /*!< CPBE2IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE3IE_Pos (14UL) /*!< CPBE3IE (Bit 14) */ + #define R_CEU_CEIER_CPBE3IE_Msk (0x4000UL) /*!< CPBE3IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE4IE_Pos (15UL) /*!< CPBE4IE (Bit 15) */ + #define R_CEU_CEIER_CPBE4IE_Msk (0x8000UL) /*!< CPBE4IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CDTOFIE_Pos (16UL) /*!< CDTOFIE (Bit 16) */ + #define R_CEU_CEIER_CDTOFIE_Msk (0x10000UL) /*!< CDTOFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGHSIE_Pos (17UL) /*!< IGHSIE (Bit 17) */ + #define R_CEU_CEIER_IGHSIE_Msk (0x20000UL) /*!< IGHSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGVSIE_Pos (18UL) /*!< IGVSIE (Bit 18) */ + #define R_CEU_CEIER_IGVSIE_Msk (0x40000UL) /*!< IGVSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VBPIE_Pos (20UL) /*!< VBPIE (Bit 20) */ + #define R_CEU_CEIER_VBPIE_Msk (0x100000UL) /*!< VBPIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_FWFIE_Pos (23UL) /*!< FWFIE (Bit 23) */ + #define R_CEU_CEIER_FWFIE_Msk (0x800000UL) /*!< FWFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NHDIE_Pos (24UL) /*!< NHDIE (Bit 24) */ + #define R_CEU_CEIER_NHDIE_Msk (0x1000000UL) /*!< NHDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NVDIE_Pos (25UL) /*!< NVDIE (Bit 25) */ + #define R_CEU_CEIER_NVDIE_Msk (0x2000000UL) /*!< NVDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETCR ========================================================= */ + #define R_CEU_CETCR_CPE_Pos (0UL) /*!< CPE (Bit 0) */ + #define R_CEU_CETCR_CPE_Msk (0x1UL) /*!< CPE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CFE_Pos (1UL) /*!< CFE (Bit 1) */ + #define R_CEU_CETCR_CFE_Msk (0x2UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGRW_Pos (4UL) /*!< IGRW (Bit 4) */ + #define R_CEU_CETCR_IGRW_Msk (0x10UL) /*!< IGRW (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_HD_Pos (8UL) /*!< HD (Bit 8) */ + #define R_CEU_CETCR_HD_Msk (0x100UL) /*!< HD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VD_Pos (9UL) /*!< VD (Bit 9) */ + #define R_CEU_CETCR_VD_Msk (0x200UL) /*!< VD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE1_Pos (12UL) /*!< CPBE1 (Bit 12) */ + #define R_CEU_CETCR_CPBE1_Msk (0x1000UL) /*!< CPBE1 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE2_Pos (13UL) /*!< CPBE2 (Bit 13) */ + #define R_CEU_CETCR_CPBE2_Msk (0x2000UL) /*!< CPBE2 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE3_Pos (14UL) /*!< CPBE3 (Bit 14) */ + #define R_CEU_CETCR_CPBE3_Msk (0x4000UL) /*!< CPBE3 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE4_Pos (15UL) /*!< CPBE4 (Bit 15) */ + #define R_CEU_CETCR_CPBE4_Msk (0x8000UL) /*!< CPBE4 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CDTOF_Pos (16UL) /*!< CDTOF (Bit 16) */ + #define R_CEU_CETCR_CDTOF_Msk (0x10000UL) /*!< CDTOF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGHS_Pos (17UL) /*!< IGHS (Bit 17) */ + #define R_CEU_CETCR_IGHS_Msk (0x20000UL) /*!< IGHS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGVS_Pos (18UL) /*!< IGVS (Bit 18) */ + #define R_CEU_CETCR_IGVS_Msk (0x40000UL) /*!< IGVS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VBP_Pos (20UL) /*!< VBP (Bit 20) */ + #define R_CEU_CETCR_VBP_Msk (0x100000UL) /*!< VBP (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_FWF_Pos (23UL) /*!< FWF (Bit 23) */ + #define R_CEU_CETCR_FWF_Msk (0x800000UL) /*!< FWF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NHD_Pos (24UL) /*!< NHD (Bit 24) */ + #define R_CEU_CETCR_NHD_Msk (0x1000000UL) /*!< NHD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NVD_Pos (25UL) /*!< NVD (Bit 25) */ + #define R_CEU_CETCR_NVD_Msk (0x2000000UL) /*!< NVD (Bitfield-Mask: 0x01) */ +/* ========================================================= CSTSR ========================================================= */ + #define R_CEU_CSTSR_CPTON_Pos (0UL) /*!< CPTON (Bit 0) */ + #define R_CEU_CSTSR_CPTON_Msk (0x1UL) /*!< CPTON (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CPFLD_Pos (16UL) /*!< CPFLD (Bit 16) */ + #define R_CEU_CSTSR_CPFLD_Msk (0x10000UL) /*!< CPFLD (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CRST_Pos (24UL) /*!< CRST (Bit 24) */ + #define R_CEU_CSTSR_CRST_Msk (0x1000000UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CDSSR ========================================================= */ + #define R_CEU_CDSSR_CDSS_Pos (0UL) /*!< CDSS (Bit 0) */ + #define R_CEU_CDSSR_CDSS_Msk (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDAYR2 ========================================================= */ + #define R_CEU_CDAYR2_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR2 ========================================================= */ + #define R_CEU_CDACR2_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR2 ========================================================= */ + #define R_CEU_CDBYR2_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR2 ========================================================= */ + #define R_CEU_CDBCR2_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== AXIBUSCTL2 ======================================================= */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Pos (0UL) /*!< AWCACHE (Bit 0) */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Msk (0xfUL) /*!< AWCACHE (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAMOR_B ======================================================== */ + #define R_CEU_CAMOR_B_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_B_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_B_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_B_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_B ======================================================== */ + #define R_CEU_CAPWR_B_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_B_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_B_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_B_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_B ======================================================== */ + #define R_CEU_CFLCR_B_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_B_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_B_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_B_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_B_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_B_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_B ======================================================== */ + #define R_CEU_CFSZR_B_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_B_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_B_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_B_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_B ======================================================== */ + #define R_CEU_CDWDR_B_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_B_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_B ======================================================== */ + #define R_CEU_CDAYR_B_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_B_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_B ======================================================== */ + #define R_CEU_CDACR_B_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_B_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_B ======================================================== */ + #define R_CEU_CDBYR_B_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_B_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_B ======================================================== */ + #define R_CEU_CDBCR_B_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_B_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_B ======================================================== */ + #define R_CEU_CBDSR_B_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_B_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_B ======================================================== */ + #define R_CEU_CLFCR_B_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_B_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_B ======================================================== */ + #define R_CEU_CDOCR_B_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_B_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_B_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_B_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_B_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_B_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_B ======================================================== */ + #define R_CEU_CDAYR2_B_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_B_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_B ======================================================== */ + #define R_CEU_CDACR2_B_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_B_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_B ======================================================== */ + #define R_CEU_CDBYR2_B_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_B_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_B ======================================================== */ + #define R_CEU_CDBCR2_B_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_B_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAMOR_M ======================================================== */ + #define R_CEU_CAMOR_M_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_M_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_M_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_M_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_M ======================================================== */ + #define R_CEU_CAPWR_M_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_M_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_M_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_M_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_M ======================================================== */ + #define R_CEU_CFLCR_M_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_M_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_M_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_M_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_M_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_M_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_M ======================================================== */ + #define R_CEU_CFSZR_M_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_M_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_M_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_M_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_M ======================================================== */ + #define R_CEU_CDWDR_M_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_M_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_M ======================================================== */ + #define R_CEU_CDAYR_M_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_M_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_M ======================================================== */ + #define R_CEU_CDACR_M_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_M_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_M ======================================================== */ + #define R_CEU_CDBYR_M_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_M_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_M ======================================================== */ + #define R_CEU_CDBCR_M_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_M_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_M ======================================================== */ + #define R_CEU_CBDSR_M_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_M_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_M ======================================================== */ + #define R_CEU_CLFCR_M_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_M_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_M ======================================================== */ + #define R_CEU_CDOCR_M_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_M_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_M_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_M_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_M_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_M_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_M ======================================================== */ + #define R_CEU_CDAYR2_M_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_M_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_M ======================================================== */ + #define R_CEU_CDACR2_M_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_M_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_M ======================================================== */ + #define R_CEU_CDBYR2_M_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_M_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_M ======================================================== */ + #define R_CEU_CDBCR2_M_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_M_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ULPTCNT ======================================================== */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Pos (0UL) /*!< ULPTCNT (Bit 0) */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Msk (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMA ======================================================== */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Pos (0UL) /*!< ULPTCMA (Bit 0) */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Msk (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMB ======================================================== */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Pos (0UL) /*!< ULPTCMB (Bit 0) */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Msk (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCR ========================================================= */ + #define R_ULPT0_ULPTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_ULPT0_ULPTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_ULPT0_ULPTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_ULPT0_ULPTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_ULPT0_ULPTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_ULPT0_ULPTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_ULPT0_ULPTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR1 ======================================================== */ + #define R_ULPT0_ULPTMR1_TMOD1_Pos (1UL) /*!< TMOD1 (Bit 1) */ + #define R_ULPT0_ULPTMR1_TMOD1_Msk (0x2UL) /*!< TMOD1 (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TCK1_Pos (5UL) /*!< TCK1 (Bit 5) */ + #define R_ULPT0_ULPTMR1_TCK1_Msk (0x20UL) /*!< TCK1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR2 ======================================================== */ + #define R_ULPT0_ULPTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_ULPT0_ULPTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_ULPT0_ULPTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_ULPT0_ULPTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR3 ======================================================== */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Pos (0UL) /*!< TCNTCTL (Bit 0) */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Msk (0x1UL) /*!< TCNTCTL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Pos (1UL) /*!< TEVPOL (Bit 1) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Msk (0x2UL) /*!< TEVPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TOPOL_Pos (2UL) /*!< TOPOL (Bit 2) */ + #define R_ULPT0_ULPTMR3_TOPOL_Msk (0x4UL) /*!< TOPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEECTL_Pos (4UL) /*!< TEECTL (Bit 4) */ + #define R_ULPT0_ULPTMR3_TEECTL_Msk (0x30UL) /*!< TEECTL (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Pos (6UL) /*!< TEEPOL (Bit 6) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Msk (0xc0UL) /*!< TEEPOL (Bitfield-Mask: 0x03) */ +/* ======================================================== ULPTIOC ======================================================== */ + #define R_ULPT0_ULPTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_ULPT0_ULPTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_ULPT0_ULPTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Pos (6UL) /*!< TIOGT0 (Bit 6) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Msk (0x40UL) /*!< TIOGT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTISR ======================================================== */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Pos (2UL) /*!< RCCPSEL2 (Bit 2) */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Msk (0x4UL) /*!< RCCPSEL2 (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPTCMSR ======================================================== */ + #define R_ULPT0_ULPTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_ULPT0_ULPTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_ULPT0_ULPTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_ULPT0_ULPTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== MCUERRSTAT ======================================================= */ + #define R_DEBUG_OCD_MCUERRSTAT_ZERO_Pos (0UL) /*!< ZERO (Bit 0) */ + #define R_DEBUG_OCD_MCUERRSTAT_ZERO_Msk (0x1UL) /*!< ZERO (Bitfield-Mask: 0x01) */ +/* ======================================================== MCUCTRL ======================================================== */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ0_Pos (0UL) /*!< EDBGRQ0 (Bit 0) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ0_Msk (0x1UL) /*!< EDBGRQ0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ1_Pos (1UL) /*!< EDBGRQ1 (Bit 1) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ1_Msk (0x2UL) /*!< EDBGRQ1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ0_Pos (8UL) /*!< DBIRQ0 (Bit 8) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ0_Msk (0x100UL) /*!< DBIRQ0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ1_Pos (9UL) /*!< DBIRQ1 (Bit 9) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ1_Msk (0x200UL) /*!< DBIRQ1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT0_Pos (16UL) /*!< CPUWAIT0 (Bit 16) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT0_Msk (0x10000UL) /*!< CPUWAIT0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT1_Pos (17UL) /*!< CPUWAIT1 (Bit 17) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT1_Msk (0x20000UL) /*!< CPUWAIT1 (Bitfield-Mask: 0x01) */ +/* ========================================================= JBMDR ========================================================= */ + #define R_DEBUG_OCD_JBMDR_KEY_Pos (0UL) /*!< KEY (Bit 0) */ + #define R_DEBUG_OCD_JBMDR_KEY_Msk (0xffUL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= JBRDR ========================================================= */ + #define R_DEBUG_OCD_JBRDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_DEBUG_OCD_JBRDR_RDAT_Msk (0xffffffffUL) /*!< RDAT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= JBTDR ========================================================= */ + #define R_DEBUG_OCD_JBTDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_DEBUG_OCD_JBTDR_TDAT_Msk (0xffffffffUL) /*!< TDAT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= JBSTR ========================================================= */ + #define R_DEBUG_OCD_JBSTR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_DEBUG_OCD_JBSTR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_JBSTR_TDE_Pos (1UL) /*!< TDE (Bit 1) */ + #define R_DEBUG_OCD_JBSTR_TDE_Msk (0x2UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= JBICR ========================================================= */ + #define R_DEBUG_OCD_JBICR_RDFIE_Pos (0UL) /*!< RDFIE (Bit 0) */ + #define R_DEBUG_OCD_JBICR_RDFIE_Msk (0x1UL) /*!< RDFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTATM ======================================================= */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CONVAREAST ======================================================= */ + #define R_DOTF_CONVAREAST_CONVAREAST_Pos (12UL) /*!< CONVAREAST (Bit 12) */ + #define R_DOTF_CONVAREAST_CONVAREAST_Msk (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff) */ +/* ======================================================= CONVAREAD ======================================================= */ + #define R_DOTF_CONVAREAD_CONVAREAD_Pos (12UL) /*!< CONVAREAD (Bit 12) */ + #define R_DOTF_CONVAREAD_CONVAREAD_Msk (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= REG00 ========================================================= */ + #define R_DOTF_REG00_B09_Pos (9UL) /*!< B09 (Bit 9) */ + #define R_DOTF_REG00_B09_Msk (0x200UL) /*!< B09 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B16_Pos (16UL) /*!< B16 (Bit 16) */ + #define R_DOTF_REG00_B16_Msk (0x10000UL) /*!< B16 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B17_Pos (17UL) /*!< B17 (Bit 17) */ + #define R_DOTF_REG00_B17_Msk (0x20000UL) /*!< B17 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B20_Pos (20UL) /*!< B20 (Bit 20) */ + #define R_DOTF_REG00_B20_Msk (0x100000UL) /*!< B20 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B24_Pos (24UL) /*!< B24 (Bit 24) */ + #define R_DOTF_REG00_B24_Msk (0x3000000UL) /*!< B24 (Bitfield-Mask: 0x03) */ + #define R_DOTF_REG00_B28_Pos (28UL) /*!< B28 (Bit 28) */ + #define R_DOTF_REG00_B28_Msk (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03) */ +/* ========================================================= REG03 ========================================================= */ + #define R_DOTF_REG03_B00_Pos (0UL) /*!< B00 (Bit 0) */ + #define R_DOTF_REG03_B00_Msk (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_COMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RIPV ========================================================== */ + #define R_COMA_RIPV_TIPV_Pos (0UL) /*!< TIPV (Bit 0) */ + #define R_COMA_RIPV_TIPV_Msk (0xfUL) /*!< TIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_GWIPV_Pos (4UL) /*!< GWIPV (Bit 4) */ + #define R_COMA_RIPV_GWIPV_Msk (0xf0UL) /*!< GWIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_FWIPV_Pos (8UL) /*!< FWIPV (Bit 8) */ + #define R_COMA_RIPV_FWIPV_Msk (0xf00UL) /*!< FWIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_EAIPV_Pos (12UL) /*!< EAIPV (Bit 12) */ + #define R_COMA_RIPV_EAIPV_Msk (0xf000UL) /*!< EAIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_FBIPV_Pos (16UL) /*!< FBIPV (Bit 16) */ + #define R_COMA_RIPV_FBIPV_Msk (0xf0000UL) /*!< FBIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_CAIPV_Pos (20UL) /*!< CAIPV (Bit 20) */ + #define R_COMA_RIPV_CAIPV_Msk (0xf00000UL) /*!< CAIPV (Bitfield-Mask: 0x0f) */ +/* ========================================================== RRC ========================================================== */ + #define R_COMA_RRC_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_COMA_RRC_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= RCEC ========================================================== */ + #define R_COMA_RCEC_ACE_Pos (0UL) /*!< ACE (Bit 0) */ + #define R_COMA_RCEC_ACE_Msk (0x7fUL) /*!< ACE (Bitfield-Mask: 0x7f) */ + #define R_COMA_RCEC_RCE_Pos (16UL) /*!< RCE (Bit 16) */ + #define R_COMA_RCEC_RCE_Msk (0x10000UL) /*!< RCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCDC ========================================================== */ + #define R_COMA_RCDC_ACD_Pos (0UL) /*!< ACD (Bit 0) */ + #define R_COMA_RCDC_ACD_Msk (0x7fUL) /*!< ACD (Bitfield-Mask: 0x7f) */ + #define R_COMA_RCDC_RCD_Pos (16UL) /*!< RCD (Bit 16) */ + #define R_COMA_RCDC_RCD_Msk (0x10000UL) /*!< RCD (Bitfield-Mask: 0x01) */ +/* ======================================================= CABPIBWMC ======================================================= */ + #define R_COMA_CABPIBWMC_IBUWMPN_Pos (0UL) /*!< IBUWMPN (Bit 0) */ + #define R_COMA_CABPIBWMC_IBUWMPN_Msk (0x3ffUL) /*!< IBUWMPN (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPIBWMC_IBSWMPN_Pos (16UL) /*!< IBSWMPN (Bit 16) */ + #define R_COMA_CABPIBWMC_IBSWMPN_Msk (0x3ff0000UL) /*!< IBSWMPN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CABPWMLC ======================================================== */ + #define R_COMA_CABPWMLC_WMFL_Pos (0UL) /*!< WMFL (Bit 0) */ + #define R_COMA_CABPWMLC_WMFL_Msk (0x1fffUL) /*!< WMFL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPWMLC_WMCL_Pos (16UL) /*!< WMCL (Bit 16) */ + #define R_COMA_CABPWMLC_WMCL_Msk (0x1fff0000UL) /*!< WMCL (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPPFLC ======================================================== */ + #define R_COMA_CABPPFLC_PDL_Pos (0UL) /*!< PDL (Bit 0) */ + #define R_COMA_CABPPFLC_PDL_Msk (0x1fffUL) /*!< PDL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPFLC_PAL_Pos (16UL) /*!< PAL (Bit 16) */ + #define R_COMA_CABPPFLC_PAL_Msk (0x1fff0000UL) /*!< PAL (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPPWMLC ======================================================= */ + #define R_COMA_CABPPWMLC_PWMFL_Pos (0UL) /*!< PWMFL (Bit 0) */ + #define R_COMA_CABPPWMLC_PWMFL_Msk (0x1fffUL) /*!< PWMFL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPWMLC_PWMCL_Pos (16UL) /*!< PWMCL (Bit 16) */ + #define R_COMA_CABPPWMLC_PWMCL_Msk (0x1fff0000UL) /*!< PWMCL (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPULC ======================================================== */ + #define R_COMA_CABPULC_MXNPN_Pos (0UL) /*!< MXNPN (Bit 0) */ + #define R_COMA_CABPULC_MXNPN_Msk (0x1fffUL) /*!< MXNPN (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPULC_MNNPN_Pos (16UL) /*!< MNNPN (Bit 16) */ + #define R_COMA_CABPULC_MNNPN_Msk (0x1fff0000UL) /*!< MNNPN (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPIRM ======================================================== */ + #define R_COMA_CABPIRM_BPIOG_Pos (0UL) /*!< BPIOG (Bit 0) */ + #define R_COMA_CABPIRM_BPIOG_Msk (0x1UL) /*!< BPIOG (Bitfield-Mask: 0x01) */ + #define R_COMA_CABPIRM_BPR_Pos (1UL) /*!< BPR (Bit 1) */ + #define R_COMA_CABPIRM_BPR_Msk (0x2UL) /*!< BPR (Bitfield-Mask: 0x01) */ +/* ======================================================== CABPPCM ======================================================== */ + #define R_COMA_CABPPCM_RPC_Pos (0UL) /*!< RPC (Bit 0) */ + #define R_COMA_CABPPCM_RPC_Msk (0x1fffUL) /*!< RPC (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPCM_TPC_Pos (16UL) /*!< TPC (Bit 16) */ + #define R_COMA_CABPPCM_TPC_Msk (0x1fff0000UL) /*!< TPC (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPLCM ======================================================== */ + #define R_COMA_CABPLCM_LRC_Pos (0UL) /*!< LRC (Bit 0) */ + #define R_COMA_CABPLCM_LRC_Msk (0x1fffUL) /*!< LRC (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPCPM ======================================================== */ + #define R_COMA_CABPCPM_RPCP_Pos (0UL) /*!< RPCP (Bit 0) */ + #define R_COMA_CABPCPM_RPCP_Msk (0x1fffUL) /*!< RPCP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPMCPM ======================================================== */ + #define R_COMA_CABPMCPM_RPMCP_Pos (0UL) /*!< RPMCP (Bit 0) */ + #define R_COMA_CABPMCPM_RPMCP_Msk (0x1fffUL) /*!< RPMCP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDNM ========================================================= */ + #define R_COMA_CARDNM_RDNRR_Pos (0UL) /*!< RDNRR (Bit 0) */ + #define R_COMA_CARDNM_RDNRR_Msk (0x1fffUL) /*!< RDNRR (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDMNM ======================================================== */ + #define R_COMA_CARDMNM_RDMNRR_Pos (0UL) /*!< RDMNRR (Bit 0) */ + #define R_COMA_CARDMNM_RDMNRR_Msk (0x1fffUL) /*!< RDMNRR (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDCN ========================================================= */ + #define R_COMA_CARDCN_RDN_Pos (0UL) /*!< RDN (Bit 0) */ + #define R_COMA_CARDCN_RDN_Msk (0xffffffffUL) /*!< RDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAEIS0 ========================================================= */ + #define R_COMA_CAEIS0_PECCES_Pos (0UL) /*!< PECCES (Bit 0) */ + #define R_COMA_CAEIS0_PECCES_Msk (0x1UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_DSECCES_Pos (1UL) /*!< DSECCES (Bit 1) */ + #define R_COMA_CAEIS0_DSECCES_Msk (0x2UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_BPECCES_Pos (2UL) /*!< BPECCES (Bit 2) */ + #define R_COMA_CAEIS0_BPECCES_Msk (0x4UL) /*!< BPECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_BPOPS_Pos (8UL) /*!< BPOPS (Bit 8) */ + #define R_COMA_CAEIS0_BPOPS_Msk (0x100UL) /*!< BPOPS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_WMCLOS_Pos (9UL) /*!< WMCLOS (Bit 9) */ + #define R_COMA_CAEIS0_WMCLOS_Msk (0x200UL) /*!< WMCLOS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_WMFLOS_Pos (10UL) /*!< WMFLOS (Bit 10) */ + #define R_COMA_CAEIS0_WMFLOS_Msk (0x400UL) /*!< WMFLOS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_EEIPLN_Pos (16UL) /*!< EEIPLN (Bit 16) */ + #define R_COMA_CAEIS0_EEIPLN_Msk (0xf0000UL) /*!< EEIPLN (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAEIE0 ========================================================= */ + #define R_COMA_CAEIE0_PECCEE_Pos (0UL) /*!< PECCEE (Bit 0) */ + #define R_COMA_CAEIE0_PECCEE_Msk (0x1UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_DSECCEE_Pos (1UL) /*!< DSECCEE (Bit 1) */ + #define R_COMA_CAEIE0_DSECCEE_Msk (0x2UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_BPECCEE_Pos (2UL) /*!< BPECCEE (Bit 2) */ + #define R_COMA_CAEIE0_BPECCEE_Msk (0x4UL) /*!< BPECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_BPOPE_Pos (8UL) /*!< BPOPE (Bit 8) */ + #define R_COMA_CAEIE0_BPOPE_Msk (0x100UL) /*!< BPOPE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_WMCLOE_Pos (9UL) /*!< WMCLOE (Bit 9) */ + #define R_COMA_CAEIE0_WMCLOE_Msk (0x200UL) /*!< WMCLOE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_WMFLOE_Pos (10UL) /*!< WMFLOE (Bit 10) */ + #define R_COMA_CAEIE0_WMFLOE_Msk (0x400UL) /*!< WMFLOE (Bitfield-Mask: 0x01) */ +/* ======================================================== CAEID0 ========================================================= */ + #define R_COMA_CAEID0_PECCED_Pos (0UL) /*!< PECCED (Bit 0) */ + #define R_COMA_CAEID0_PECCED_Msk (0x1UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_DSECCED_Pos (1UL) /*!< DSECCED (Bit 1) */ + #define R_COMA_CAEID0_DSECCED_Msk (0x2UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_BPECCED_Pos (2UL) /*!< BPECCED (Bit 2) */ + #define R_COMA_CAEID0_BPECCED_Msk (0x4UL) /*!< BPECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_BPOPD_Pos (8UL) /*!< BPOPD (Bit 8) */ + #define R_COMA_CAEID0_BPOPD_Msk (0x100UL) /*!< BPOPD (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_WMCLOD_Pos (9UL) /*!< WMCLOD (Bit 9) */ + #define R_COMA_CAEID0_WMCLOD_Msk (0x200UL) /*!< WMCLOD (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_WMFLOD_Pos (10UL) /*!< WMFLOD (Bit 10) */ + #define R_COMA_CAEID0_WMFLOD_Msk (0x400UL) /*!< WMFLOD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAEIS1 ========================================================= */ + #define R_COMA_CAEIS1_PWMCLOS_Pos (0UL) /*!< PWMCLOS (Bit 0) */ + #define R_COMA_CAEIS1_PWMCLOS_Msk (0x7fUL) /*!< PWMCLOS (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEIS1_PWMFLOS_Pos (16UL) /*!< PWMFLOS (Bit 16) */ + #define R_COMA_CAEIS1_PWMFLOS_Msk (0x7f0000UL) /*!< PWMFLOS (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAEIE1 ========================================================= */ + #define R_COMA_CAEIE1_PWMCLOE_Pos (0UL) /*!< PWMCLOE (Bit 0) */ + #define R_COMA_CAEIE1_PWMCLOE_Msk (0x7fUL) /*!< PWMCLOE (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEIE1_PWMFLOE_Pos (16UL) /*!< PWMFLOE (Bit 16) */ + #define R_COMA_CAEIE1_PWMFLOE_Msk (0x7f0000UL) /*!< PWMFLOE (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAEID1 ========================================================= */ + #define R_COMA_CAEID1_PWMCLOD_Pos (0UL) /*!< PWMCLOD (Bit 0) */ + #define R_COMA_CAEID1_PWMCLOD_Msk (0x7fUL) /*!< PWMCLOD (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEID1_PWMFLOD_Pos (16UL) /*!< PWMFLOD (Bit 16) */ + #define R_COMA_CAEID1_PWMFLOD_Msk (0x7f0000UL) /*!< PWMFLOD (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAMIS0 ========================================================= */ + #define R_COMA_CAMIS0_PFS_Pos (0UL) /*!< PFS (Bit 0) */ + #define R_COMA_CAMIS0_PFS_Msk (0x3UL) /*!< PFS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMIE0 ========================================================= */ + #define R_COMA_CAMIE0_PFE_Pos (0UL) /*!< PFE (Bit 0) */ + #define R_COMA_CAMIE0_PFE_Msk (0x3UL) /*!< PFE (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMID0 ========================================================= */ + #define R_COMA_CAMID0_PFD_Pos (0UL) /*!< PFD (Bit 0) */ + #define R_COMA_CAMID0_PFD_Msk (0x3UL) /*!< PFD (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMIS1 ========================================================= */ + #define R_COMA_CAMIS1_PPFS_Pos (0UL) /*!< PPFS (Bit 0) */ + #define R_COMA_CAMIS1_PPFS_Msk (0x3fffUL) /*!< PPFS (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CAMIE1 ========================================================= */ + #define R_COMA_CAMIE1_PPFE_Pos (0UL) /*!< PPFE (Bit 0) */ + #define R_COMA_CAMIE1_PPFE_Msk (0x3fffUL) /*!< PPFE (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CAMID1 ========================================================= */ + #define R_COMA_CAMID1_PPFD_Pos (0UL) /*!< PPFD (Bit 0) */ + #define R_COMA_CAMID1_PPFD_Msk (0x3fffUL) /*!< PPFD (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CPU_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CPU0LCKUPCR ====================================================== */ + #define R_CPU_CTRL_CPU0LCKUPCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CPU_CTRL_CPU0LCKUPCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1LCKUPCR ====================================================== */ + #define R_CPU_CTRL_CPU1LCKUPCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CPU_CTRL_CPU1LCKUPCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0INITVTOR ====================================================== */ + #define R_CPU_CTRL_CPU0INITVTOR_CPUnINITVTOR_Pos (0UL) /*!< CPUnINITVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU0INITVTOR_CPUnINITVTOR_Msk (0xffffffffUL) /*!< CPUnINITVTOR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CPU1INITVTOR ====================================================== */ + #define R_CPU_CTRL_CPU1INITVTOR_CPUnINITVTOR_Pos (0UL) /*!< CPUnINITVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU1INITVTOR_CPUnINITVTOR_Msk (0xffffffffUL) /*!< CPUnINITVTOR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CPU0WAITCR ======================================================= */ + #define R_CPU_CTRL_CPU0WAITCR_CPUWAIT_Pos (0UL) /*!< CPUWAIT (Bit 0) */ + #define R_CPU_CTRL_CPU0WAITCR_CPUWAIT_Msk (0x1UL) /*!< CPUWAIT (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1WAITCR ======================================================= */ + #define R_CPU_CTRL_CPU1WAITCR_CPUWAIT_Pos (0UL) /*!< CPUWAIT (Bit 0) */ + #define R_CPU_CTRL_CPU1WAITCR_CPUWAIT_Msk (0x1UL) /*!< CPUWAIT (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0ACTCSR ======================================================= */ + #define R_CPU_CTRL_CPU0ACTCSR_ACTREQ_Pos (0UL) /*!< ACTREQ (Bit 0) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACTREQ_Msk (0x1UL) /*!< ACTREQ (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0ACTCSR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU0ACTCSR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ====================================================== CPU1ACTCSR ======================================================= */ + #define R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Pos (0UL) /*!< ACTREQ (Bit 0) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Msk (0x1UL) /*!< ACTREQ (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1ACTCSR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU1ACTCSR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CPU0LMECR ======================================================= */ + #define R_CPU_CTRL_CPU0LMECR_SYRSTEN_Pos (0UL) /*!< SYRSTEN (Bit 0) */ + #define R_CPU_CTRL_CPU0LMECR_SYRSTEN_Msk (0x1UL) /*!< SYRSTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUIDR ========================================================= */ + #define R_CPU_CTRL_CPUIDR_CPUID_Pos (0UL) /*!< CPUID (Bit 0) */ + #define R_CPU_CTRL_CPUIDR_CPUID_Msk (0x1UL) /*!< CPUID (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0STATM ======================================================= */ + #define R_CPU_CTRL_CPU0STATM_SLEEPING_Pos (0UL) /*!< SLEEPING (Bit 0) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPING_Msk (0x1UL) /*!< SLEEPING (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPDEEP_Pos (1UL) /*!< SLEEPDEEP (Bit 1) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPDEEP_Msk (0x2UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0STATM_SAHBSTP_Pos (4UL) /*!< SAHBSTP (Bit 4) */ + #define R_CPU_CTRL_CPU0STATM_SAHBSTP_Msk (0x10UL) /*!< SAHBSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1STATM ======================================================= */ + #define R_CPU_CTRL_CPU1STATM_SLEEPING_Pos (0UL) /*!< SLEEPING (Bit 0) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPING_Msk (0x1UL) /*!< SLEEPING (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPDEEP_Pos (1UL) /*!< SLEEPDEEP (Bit 1) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPDEEP_Msk (0x2UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1STATM_SAHBSTP_Pos (4UL) /*!< SAHBSTP (Bit 4) */ + #define R_CPU_CTRL_CPU1STATM_SAHBSTP_Msk (0x10UL) /*!< SAHBSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= SECEXTMON ======================================================= */ + #define R_CPU_CTRL_SECEXTMON_SECEXT_Pos (0UL) /*!< SECEXT (Bit 0) */ + #define R_CPU_CTRL_SECEXTMON_SECEXT_Msk (0x1UL) /*!< SECEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== NSCPUCR ======================================================== */ + #define R_CPU_CTRL_NSCPUCR_RSTREQEN_Pos (0UL) /*!< RSTREQEN (Bit 0) */ + #define R_CPU_CTRL_NSCPUCR_RSTREQEN_Msk (0x1UL) /*!< RSTREQEN (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0LOCKCR ======================================================= */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSVTAIR_Pos (0UL) /*!< LCKSVTAIR (Bit 0) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSVTAIR_Msk (0x1UL) /*!< LCKSVTAIR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSMPU_Pos (1UL) /*!< LCKSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSMPU_Msk (0x2UL) /*!< LCKSMPU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSAU_Pos (2UL) /*!< LCKSAU (Bit 2) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSAU_Msk (0x4UL) /*!< LCKSAU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKITGU_Pos (3UL) /*!< LCKITGU (Bit 3) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKITGU_Msk (0x8UL) /*!< LCKITGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDTGU_Pos (4UL) /*!< LCKDTGU (Bit 4) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDTGU_Msk (0x10UL) /*!< LCKDTGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDCAIC_Pos (5UL) /*!< LCKDCAIC (Bit 5) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDCAIC_Msk (0x20UL) /*!< LCKDCAIC (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1LOCKCR ======================================================= */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSVTAIR_Pos (0UL) /*!< LCKSVTAIR (Bit 0) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSVTAIR_Msk (0x1UL) /*!< LCKSVTAIR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSMPU_Pos (1UL) /*!< LCKSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSMPU_Msk (0x2UL) /*!< LCKSMPU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSAU_Pos (2UL) /*!< LCKSAU (Bit 2) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSAU_Msk (0x4UL) /*!< LCKSAU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKITGU_Pos (3UL) /*!< LCKITGU (Bit 3) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKITGU_Msk (0x8UL) /*!< LCKITGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDTGU_Pos (4UL) /*!< LCKDTGU (Bit 4) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDTGU_Msk (0x10UL) /*!< LCKDTGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDCAIC_Pos (5UL) /*!< LCKDCAIC (Bit 5) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDCAIC_Msk (0x20UL) /*!< LCKDCAIC (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0LOCKCRNS ====================================================== */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSVTOR_Pos (0UL) /*!< LCKNSVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSVTOR_Msk (0x1UL) /*!< LCKNSVTOR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSMPU_Pos (1UL) /*!< LCKNSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSMPU_Msk (0x2UL) /*!< LCKNSMPU (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU1LOCKCRNS ====================================================== */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSVTOR_Pos (0UL) /*!< LCKNSVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSVTOR_Msk (0x1UL) /*!< LCKNSVTOR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSMPU_Pos (1UL) /*!< LCKNSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSMPU_Msk (0x2UL) /*!< LCKNSMPU (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0CRPT ======================================================== */ + #define R_CPU_CTRL_CPU0CRPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_CPU_CTRL_CPU0CRPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0CRPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU0CRPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CPU1CRPT ======================================================== */ + #define R_CPU_CTRL_CPU1CRPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_CPU_CTRL_CPU1CRPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1CRPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU1CRPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_ESWM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= TPEMIMC0 ======================================================== */ + #define R_ESWM_TPEMIMC0_SEIM_Pos (0UL) /*!< SEIM (Bit 0) */ + #define R_ESWM_TPEMIMC0_SEIM_Msk (0x1UL) /*!< SEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SEIGM_Pos (1UL) /*!< SEIGM (Bit 1) */ + #define R_ESWM_TPEMIMC0_SEIGM_Msk (0x2UL) /*!< SEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SEICM_Pos (4UL) /*!< SEICM (Bit 4) */ + #define R_ESWM_TPEMIMC0_SEICM_Msk (0x70UL) /*!< SEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC0_SSIM_Pos (16UL) /*!< SSIM (Bit 16) */ + #define R_ESWM_TPEMIMC0_SSIM_Msk (0x10000UL) /*!< SSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SSIGM_Pos (17UL) /*!< SSIGM (Bit 17) */ + #define R_ESWM_TPEMIMC0_SSIGM_Msk (0x20000UL) /*!< SSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SSICM_Pos (20UL) /*!< SSICM (Bit 20) */ + #define R_ESWM_TPEMIMC0_SSICM_Msk (0x700000UL) /*!< SSICM (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC1 ======================================================== */ + #define R_ESWM_TPEMIMC1_FEIM_Pos (0UL) /*!< FEIM (Bit 0) */ + #define R_ESWM_TPEMIMC1_FEIM_Msk (0x1UL) /*!< FEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FEIGM_Pos (1UL) /*!< FEIGM (Bit 1) */ + #define R_ESWM_TPEMIMC1_FEIGM_Msk (0x2UL) /*!< FEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FEICM_Pos (4UL) /*!< FEICM (Bit 4) */ + #define R_ESWM_TPEMIMC1_FEICM_Msk (0x70UL) /*!< FEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_FSIM_Pos (8UL) /*!< FSIM (Bit 8) */ + #define R_ESWM_TPEMIMC1_FSIM_Msk (0x100UL) /*!< FSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FSIGM_Pos (9UL) /*!< FSIGM (Bit 9) */ + #define R_ESWM_TPEMIMC1_FSIGM_Msk (0x200UL) /*!< FSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FSICM_Pos (12UL) /*!< FSICM (Bit 12) */ + #define R_ESWM_TPEMIMC1_FSICM_Msk (0x7000UL) /*!< FSICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_CEIM_Pos (16UL) /*!< CEIM (Bit 16) */ + #define R_ESWM_TPEMIMC1_CEIM_Msk (0x10000UL) /*!< CEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CEIGM_Pos (17UL) /*!< CEIGM (Bit 17) */ + #define R_ESWM_TPEMIMC1_CEIGM_Msk (0x20000UL) /*!< CEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CEICM_Pos (20UL) /*!< CEICM (Bit 20) */ + #define R_ESWM_TPEMIMC1_CEICM_Msk (0x700000UL) /*!< CEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_CSIM_Pos (24UL) /*!< CSIM (Bit 24) */ + #define R_ESWM_TPEMIMC1_CSIM_Msk (0x1000000UL) /*!< CSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CSIGM_Pos (25UL) /*!< CSIGM (Bit 25) */ + #define R_ESWM_TPEMIMC1_CSIGM_Msk (0x2000000UL) /*!< CSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CSICM_Pos (28UL) /*!< CSICM (Bit 28) */ + #define R_ESWM_TPEMIMC1_CSICM_Msk (0x70000000UL) /*!< CSICM (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC2 ======================================================== */ + #define R_ESWM_TPEMIMC2_GEIM0_Pos (0UL) /*!< GEIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC2_GEIM0_Msk (0x1UL) /*!< GEIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GEIGM0_Pos (1UL) /*!< GEIGM0 (Bit 1) */ + #define R_ESWM_TPEMIMC2_GEIGM0_Msk (0x2UL) /*!< GEIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GEICM0_Pos (4UL) /*!< GEICM0 (Bit 4) */ + #define R_ESWM_TPEMIMC2_GEICM0_Msk (0x70UL) /*!< GEICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC2_GSIM0_Pos (8UL) /*!< GSIM0 (Bit 8) */ + #define R_ESWM_TPEMIMC2_GSIM0_Msk (0x100UL) /*!< GSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GSIGM0_Pos (9UL) /*!< GSIGM0 (Bit 9) */ + #define R_ESWM_TPEMIMC2_GSIGM0_Msk (0x200UL) /*!< GSIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GSICM0_Pos (12UL) /*!< GSICM0 (Bit 12) */ + #define R_ESWM_TPEMIMC2_GSICM0_Msk (0x7000UL) /*!< GSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC3 ======================================================== */ + #define R_ESWM_TPEMIMC3_EEIM0_Pos (0UL) /*!< EEIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC3_EEIM0_Msk (0x1UL) /*!< EEIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_EEIGM0_Pos (1UL) /*!< EEIGM0 (Bit 1) */ + #define R_ESWM_TPEMIMC3_EEIGM0_Msk (0x2UL) /*!< EEIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_EEICM0_Pos (4UL) /*!< EEICM0 (Bit 4) */ + #define R_ESWM_TPEMIMC3_EEICM0_Msk (0x70UL) /*!< EEICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC3_ESIM0_Pos (8UL) /*!< ESIM0 (Bit 8) */ + #define R_ESWM_TPEMIMC3_ESIM0_Msk (0x100UL) /*!< ESIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_ESIGM0_Pos (9UL) /*!< ESIGM0 (Bit 9) */ + #define R_ESWM_TPEMIMC3_ESIGM0_Msk (0x200UL) /*!< ESIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_ESICM0_Pos (12UL) /*!< ESICM0 (Bit 12) */ + #define R_ESWM_TPEMIMC3_ESICM0_Msk (0x7000UL) /*!< ESICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC3_RSIM0_Pos (16UL) /*!< RSIM0 (Bit 16) */ + #define R_ESWM_TPEMIMC3_RSIM0_Msk (0x10000UL) /*!< RSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_RSIGM0_Pos (17UL) /*!< RSIGM0 (Bit 17) */ + #define R_ESWM_TPEMIMC3_RSIGM0_Msk (0x20000UL) /*!< RSIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_RSICM0_Pos (20UL) /*!< RSICM0 (Bit 20) */ + #define R_ESWM_TPEMIMC3_RSICM0_Msk (0x700000UL) /*!< RSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC4 ======================================================== */ + #define R_ESWM_TPEMIMC4_EEIM1_Pos (0UL) /*!< EEIM1 (Bit 0) */ + #define R_ESWM_TPEMIMC4_EEIM1_Msk (0x1UL) /*!< EEIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_EEIGM1_Pos (1UL) /*!< EEIGM1 (Bit 1) */ + #define R_ESWM_TPEMIMC4_EEIGM1_Msk (0x2UL) /*!< EEIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_EEICM1_Pos (4UL) /*!< EEICM1 (Bit 4) */ + #define R_ESWM_TPEMIMC4_EEICM1_Msk (0x70UL) /*!< EEICM1 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC4_ESIM1_Pos (8UL) /*!< ESIM1 (Bit 8) */ + #define R_ESWM_TPEMIMC4_ESIM1_Msk (0x100UL) /*!< ESIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_ESIGM1_Pos (9UL) /*!< ESIGM1 (Bit 9) */ + #define R_ESWM_TPEMIMC4_ESIGM1_Msk (0x200UL) /*!< ESIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_ESICM1_Pos (12UL) /*!< ESICM1 (Bit 12) */ + #define R_ESWM_TPEMIMC4_ESICM1_Msk (0x7000UL) /*!< ESICM1 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC4_RSIM1_Pos (16UL) /*!< RSIM1 (Bit 16) */ + #define R_ESWM_TPEMIMC4_RSIM1_Msk (0x10000UL) /*!< RSIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_RSIGM1_Pos (17UL) /*!< RSIGM1 (Bit 17) */ + #define R_ESWM_TPEMIMC4_RSIGM1_Msk (0x20000UL) /*!< RSIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_RSICM1_Pos (20UL) /*!< RSICM1 (Bit 20) */ + #define R_ESWM_TPEMIMC4_RSICM1_Msk (0x700000UL) /*!< RSICM1 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC60 ======================================================= */ + #define R_ESWM_TPEMIMC60_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC60_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC60_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC60_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC61 ======================================================= */ + #define R_ESWM_TPEMIMC61_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC61_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC61_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC61_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC62 ======================================================= */ + #define R_ESWM_TPEMIMC62_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC62_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC62_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC62_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC63 ======================================================= */ + #define R_ESWM_TPEMIMC63_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC63_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC63_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC63_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC64 ======================================================= */ + #define R_ESWM_TPEMIMC64_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC64_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC64_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC64_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC70 ======================================================= */ + #define R_ESWM_TPEMIMC70_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC70_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC71 ======================================================= */ + #define R_ESWM_TPEMIMC71_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC71_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC72 ======================================================= */ + #define R_ESWM_TPEMIMC72_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC72_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC73 ======================================================= */ + #define R_ESWM_TPEMIMC73_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC73_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC74 ======================================================= */ + #define R_ESWM_TPEMIMC74_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC74_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ========================================================= TSIM ========================================================== */ + #define R_ESWM_TSIM_FIM_Pos (0UL) /*!< FIM (Bit 0) */ + #define R_ESWM_TSIM_FIM_Msk (0x1UL) /*!< FIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_CIM_Pos (1UL) /*!< CIM (Bit 1) */ + #define R_ESWM_TSIM_CIM_Msk (0x2UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_GIM_Pos (2UL) /*!< GIM (Bit 2) */ + #define R_ESWM_TSIM_GIM_Msk (0x4UL) /*!< GIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_EIM_Pos (4UL) /*!< EIM (Bit 4) */ + #define R_ESWM_TSIM_EIM_Msk (0x10UL) /*!< EIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TFIM ========================================================== */ + #define R_ESWM_TFIM_FWEISIM_Pos (0UL) /*!< FWEISIM (Bit 0) */ + #define R_ESWM_TFIM_FWEISIM_Msk (0x1UL) /*!< FWEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TFIM_FWMISIM0_Pos (9UL) /*!< FWMISIM0 (Bit 9) */ + #define R_ESWM_TFIM_FWMISIM0_Msk (0x200UL) /*!< FWMISIM0 (Bitfield-Mask: 0x01) */ +/* ========================================================= TCIM ========================================================== */ + #define R_ESWM_TCIM_RSSISIM_Pos (0UL) /*!< RSSISIM (Bit 0) */ + #define R_ESWM_TCIM_RSSISIM_Msk (0x1UL) /*!< RSSISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TCIM_CAEISIM_Pos (1UL) /*!< CAEISIM (Bit 1) */ + #define R_ESWM_TCIM_CAEISIM_Msk (0x2UL) /*!< CAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TCIM_CAMISIM_Pos (3UL) /*!< CAMISIM (Bit 3) */ + #define R_ESWM_TCIM_CAMISIM_Msk (0x8UL) /*!< CAMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TGIM0 ========================================================= */ + #define R_ESWM_TGIM0_GWDISIM_Pos (0UL) /*!< GWDISIM (Bit 0) */ + #define R_ESWM_TGIM0_GWDISIM_Msk (0x1UL) /*!< GWDISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TGIM0_GWTSDISIM_Pos (1UL) /*!< GWTSDISIM (Bit 1) */ + #define R_ESWM_TGIM0_GWTSDISIM_Msk (0x2UL) /*!< GWTSDISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TGIM0_GWEISIM_Pos (2UL) /*!< GWEISIM (Bit 2) */ + #define R_ESWM_TGIM0_GWEISIM_Msk (0x4UL) /*!< GWEISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TEIM0 ========================================================= */ + #define R_ESWM_TEIM0_EAEISIM_Pos (0UL) /*!< EAEISIM (Bit 0) */ + #define R_ESWM_TEIM0_EAEISIM_Msk (0x1UL) /*!< EAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM0_MEISIM_Pos (3UL) /*!< MEISIM (Bit 3) */ + #define R_ESWM_TEIM0_MEISIM_Msk (0x8UL) /*!< MEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM0_MMISIM_Pos (4UL) /*!< MMISIM (Bit 4) */ + #define R_ESWM_TEIM0_MMISIM_Msk (0x10UL) /*!< MMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TEIM1 ========================================================= */ + #define R_ESWM_TEIM1_EAEISIM_Pos (0UL) /*!< EAEISIM (Bit 0) */ + #define R_ESWM_TEIM1_EAEISIM_Msk (0x1UL) /*!< EAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM1_MEISIM_Pos (3UL) /*!< MEISIM (Bit 3) */ + #define R_ESWM_TEIM1_MEISIM_Msk (0x8UL) /*!< MEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM1_MMISIM_Pos (4UL) /*!< MMISIM (Bit 4) */ + #define R_ESWM_TEIM1_MMISIM_Msk (0x10UL) /*!< MMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= MIIRR ========================================================= */ + #define R_ESWM_MIIRR_RGRST_Pos (0UL) /*!< RGRST (Bit 0) */ + #define R_ESWM_MIIRR_RGRST_Msk (0x1UL) /*!< RGRST (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIIRR_RMRST_Pos (8UL) /*!< RMRST (Bit 8) */ + #define R_ESWM_MIIRR_RMRST_Msk (0x100UL) /*!< RMRST (Bitfield-Mask: 0x01) */ +/* ======================================================== MIICR0 ========================================================= */ + #define R_ESWM_MIICR0_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_ESWM_MIICR0_MIISEL_Msk (0x3UL) /*!< MIISEL (Bitfield-Mask: 0x03) */ + #define R_ESWM_MIICR0_DIVSTP_Pos (8UL) /*!< DIVSTP (Bit 8) */ + #define R_ESWM_MIICR0_DIVSTP_Msk (0x100UL) /*!< DIVSTP (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIICR0_TXCIDE_Pos (12UL) /*!< TXCIDE (Bit 12) */ + #define R_ESWM_MIICR0_TXCIDE_Msk (0x1000UL) /*!< TXCIDE (Bitfield-Mask: 0x01) */ +/* ======================================================== MIICR1 ========================================================= */ + #define R_ESWM_MIICR1_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_ESWM_MIICR1_MIISEL_Msk (0x3UL) /*!< MIISEL (Bitfield-Mask: 0x03) */ + #define R_ESWM_MIICR1_DIVSTP_Pos (8UL) /*!< DIVSTP (Bit 8) */ + #define R_ESWM_MIICR1_DIVSTP_Msk (0x100UL) /*!< DIVSTP (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIICR1_TXCIDE_Pos (12UL) /*!< TXCIDE (Bit 12) */ + #define R_ESWM_MIICR1_TXCIDE_Msk (0x1000UL) /*!< TXCIDE (Bitfield-Mask: 0x01) */ +/* ======================================================== MCCESR ========================================================= */ + #define R_ESWM_MCCESR_MCCES_Pos (0UL) /*!< MCCES (Bit 0) */ + #define R_ESWM_MCCESR_MCCES_Msk (0x1UL) /*!< MCCES (Bitfield-Mask: 0x01) */ +/* ======================================================== TASSTSR ======================================================== */ + #define R_ESWM_TASSTSR_MSS_Pos (0UL) /*!< MSS (Bit 0) */ + #define R_ESWM_TASSTSR_MSS_Msk (0x1fUL) /*!< MSS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EAMC ========================================================== */ + #define R_ETHA0_EAMC_OPC_Pos (0UL) /*!< OPC (Bit 0) */ + #define R_ETHA0_EAMC_OPC_Msk (0x3UL) /*!< OPC (Bitfield-Mask: 0x03) */ +/* ========================================================= EAMS ========================================================== */ + #define R_ETHA0_EAMS_OPS_Pos (0UL) /*!< OPS (Bit 0) */ + #define R_ETHA0_EAMS_OPS_Msk (0x3UL) /*!< OPS (Bitfield-Mask: 0x03) */ +/* ========================================================= EAIRC ========================================================= */ + #define R_ETHA0_EAIRC_IPVR0_Pos (0UL) /*!< IPVR0 (Bit 0) */ + #define R_ETHA0_EAIRC_IPVR0_Msk (0x7UL) /*!< IPVR0 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR1_Pos (4UL) /*!< IPVR1 (Bit 4) */ + #define R_ETHA0_EAIRC_IPVR1_Msk (0x70UL) /*!< IPVR1 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR2_Pos (8UL) /*!< IPVR2 (Bit 8) */ + #define R_ETHA0_EAIRC_IPVR2_Msk (0x700UL) /*!< IPVR2 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR3_Pos (12UL) /*!< IPVR3 (Bit 12) */ + #define R_ETHA0_EAIRC_IPVR3_Msk (0x7000UL) /*!< IPVR3 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR4_Pos (16UL) /*!< IPVR4 (Bit 16) */ + #define R_ETHA0_EAIRC_IPVR4_Msk (0x70000UL) /*!< IPVR4 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR5_Pos (20UL) /*!< IPVR5 (Bit 20) */ + #define R_ETHA0_EAIRC_IPVR5_Msk (0x700000UL) /*!< IPVR5 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR6_Pos (24UL) /*!< IPVR6 (Bit 24) */ + #define R_ETHA0_EAIRC_IPVR6_Msk (0x7000000UL) /*!< IPVR6 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR7_Pos (28UL) /*!< IPVR7 (Bit 28) */ + #define R_ETHA0_EAIRC_IPVR7_Msk (0x70000000UL) /*!< IPVR7 (Bitfield-Mask: 0x07) */ +/* ======================================================== EATDQSC ======================================================== */ + #define R_ETHA0_EATDQSC_TDQSL0_Pos (0UL) /*!< TDQSL0 (Bit 0) */ + #define R_ETHA0_EATDQSC_TDQSL0_Msk (0x1UL) /*!< TDQSL0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL1_Pos (1UL) /*!< TDQSL1 (Bit 1) */ + #define R_ETHA0_EATDQSC_TDQSL1_Msk (0x2UL) /*!< TDQSL1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL2_Pos (2UL) /*!< TDQSL2 (Bit 2) */ + #define R_ETHA0_EATDQSC_TDQSL2_Msk (0x4UL) /*!< TDQSL2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL3_Pos (3UL) /*!< TDQSL3 (Bit 3) */ + #define R_ETHA0_EATDQSC_TDQSL3_Msk (0x8UL) /*!< TDQSL3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL4_Pos (4UL) /*!< TDQSL4 (Bit 4) */ + #define R_ETHA0_EATDQSC_TDQSL4_Msk (0x10UL) /*!< TDQSL4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL5_Pos (5UL) /*!< TDQSL5 (Bit 5) */ + #define R_ETHA0_EATDQSC_TDQSL5_Msk (0x20UL) /*!< TDQSL5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL6_Pos (6UL) /*!< TDQSL6 (Bit 6) */ + #define R_ETHA0_EATDQSC_TDQSL6_Msk (0x40UL) /*!< TDQSL6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL7_Pos (7UL) /*!< TDQSL7 (Bit 7) */ + #define R_ETHA0_EATDQSC_TDQSL7_Msk (0x80UL) /*!< TDQSL7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATDQC ========================================================= */ + #define R_ETHA0_EATDQC_TDQD0_Pos (0UL) /*!< TDQD0 (Bit 0) */ + #define R_ETHA0_EATDQC_TDQD0_Msk (0x1UL) /*!< TDQD0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD1_Pos (1UL) /*!< TDQD1 (Bit 1) */ + #define R_ETHA0_EATDQC_TDQD1_Msk (0x2UL) /*!< TDQD1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD2_Pos (2UL) /*!< TDQD2 (Bit 2) */ + #define R_ETHA0_EATDQC_TDQD2_Msk (0x4UL) /*!< TDQD2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD3_Pos (3UL) /*!< TDQD3 (Bit 3) */ + #define R_ETHA0_EATDQC_TDQD3_Msk (0x8UL) /*!< TDQD3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD4_Pos (4UL) /*!< TDQD4 (Bit 4) */ + #define R_ETHA0_EATDQC_TDQD4_Msk (0x10UL) /*!< TDQD4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD5_Pos (5UL) /*!< TDQD5 (Bit 5) */ + #define R_ETHA0_EATDQC_TDQD5_Msk (0x20UL) /*!< TDQD5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD6_Pos (6UL) /*!< TDQD6 (Bit 6) */ + #define R_ETHA0_EATDQC_TDQD6_Msk (0x40UL) /*!< TDQD6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD7_Pos (7UL) /*!< TDQD7 (Bit 7) */ + #define R_ETHA0_EATDQC_TDQD7_Msk (0x80UL) /*!< TDQD7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TCTDQD_Pos (8UL) /*!< TCTDQD (Bit 8) */ + #define R_ETHA0_EATDQC_TCTDQD_Msk (0x100UL) /*!< TCTDQD (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP0_Pos (16UL) /*!< TDQP0 (Bit 16) */ + #define R_ETHA0_EATDQC_TDQP0_Msk (0x10000UL) /*!< TDQP0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP1_Pos (17UL) /*!< TDQP1 (Bit 17) */ + #define R_ETHA0_EATDQC_TDQP1_Msk (0x20000UL) /*!< TDQP1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP2_Pos (18UL) /*!< TDQP2 (Bit 18) */ + #define R_ETHA0_EATDQC_TDQP2_Msk (0x40000UL) /*!< TDQP2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP3_Pos (19UL) /*!< TDQP3 (Bit 19) */ + #define R_ETHA0_EATDQC_TDQP3_Msk (0x80000UL) /*!< TDQP3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP4_Pos (20UL) /*!< TDQP4 (Bit 20) */ + #define R_ETHA0_EATDQC_TDQP4_Msk (0x100000UL) /*!< TDQP4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP5_Pos (21UL) /*!< TDQP5 (Bit 21) */ + #define R_ETHA0_EATDQC_TDQP5_Msk (0x200000UL) /*!< TDQP5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP6_Pos (22UL) /*!< TDQP6 (Bit 22) */ + #define R_ETHA0_EATDQC_TDQP6_Msk (0x400000UL) /*!< TDQP6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP7_Pos (23UL) /*!< TDQP7 (Bit 23) */ + #define R_ETHA0_EATDQC_TDQP7_Msk (0x800000UL) /*!< TDQP7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATDQAC ======================================================== */ + #define R_ETHA0_EATDQAC_TDQA0_Pos (0UL) /*!< TDQA0 (Bit 0) */ + #define R_ETHA0_EATDQAC_TDQA0_Msk (0xfUL) /*!< TDQA0 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA1_Pos (4UL) /*!< TDQA1 (Bit 4) */ + #define R_ETHA0_EATDQAC_TDQA1_Msk (0xf0UL) /*!< TDQA1 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA2_Pos (8UL) /*!< TDQA2 (Bit 8) */ + #define R_ETHA0_EATDQAC_TDQA2_Msk (0xf00UL) /*!< TDQA2 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA3_Pos (12UL) /*!< TDQA3 (Bit 12) */ + #define R_ETHA0_EATDQAC_TDQA3_Msk (0xf000UL) /*!< TDQA3 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA4_Pos (16UL) /*!< TDQA4 (Bit 16) */ + #define R_ETHA0_EATDQAC_TDQA4_Msk (0xf0000UL) /*!< TDQA4 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA5_Pos (20UL) /*!< TDQA5 (Bit 20) */ + #define R_ETHA0_EATDQAC_TDQA5_Msk (0xf00000UL) /*!< TDQA5 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA6_Pos (24UL) /*!< TDQA6 (Bit 24) */ + #define R_ETHA0_EATDQAC_TDQA6_Msk (0xf000000UL) /*!< TDQA6 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA7_Pos (28UL) /*!< TDQA7 (Bit 28) */ + #define R_ETHA0_EATDQAC_TDQA7_Msk (0xf0000000UL) /*!< TDQA7 (Bitfield-Mask: 0x0f) */ +/* ======================================================== EATPEC ========================================================= */ + #define R_ETHA0_EATPEC_TTQ0_Pos (0UL) /*!< TTQ0 (Bit 0) */ + #define R_ETHA0_EATPEC_TTQ0_Msk (0x1UL) /*!< TTQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ1_Pos (1UL) /*!< TTQ1 (Bit 1) */ + #define R_ETHA0_EATPEC_TTQ1_Msk (0x2UL) /*!< TTQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ2_Pos (2UL) /*!< TTQ2 (Bit 2) */ + #define R_ETHA0_EATPEC_TTQ2_Msk (0x4UL) /*!< TTQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ3_Pos (3UL) /*!< TTQ3 (Bit 3) */ + #define R_ETHA0_EATPEC_TTQ3_Msk (0x8UL) /*!< TTQ3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ4_Pos (4UL) /*!< TTQ4 (Bit 4) */ + #define R_ETHA0_EATPEC_TTQ4_Msk (0x10UL) /*!< TTQ4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ5_Pos (5UL) /*!< TTQ5 (Bit 5) */ + #define R_ETHA0_EATPEC_TTQ5_Msk (0x20UL) /*!< TTQ5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ6_Pos (6UL) /*!< TTQ6 (Bit 6) */ + #define R_ETHA0_EATPEC_TTQ6_Msk (0x40UL) /*!< TTQ6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ7_Pos (7UL) /*!< TTQ7 (Bit 7) */ + #define R_ETHA0_EATPEC_TTQ7_Msk (0x80UL) /*!< TTQ7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ8_Pos (8UL) /*!< TTQ8 (Bit 8) */ + #define R_ETHA0_EATPEC_TTQ8_Msk (0x100UL) /*!< TTQ8 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ9_Pos (9UL) /*!< TTQ9 (Bit 9) */ + #define R_ETHA0_EATPEC_TTQ9_Msk (0x200UL) /*!< TTQ9 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_AFS_Pos (16UL) /*!< AFS (Bit 16) */ + #define R_ETHA0_EATPEC_AFS_Msk (0x30000UL) /*!< AFS (Bitfield-Mask: 0x03) */ +/* ======================================================= EATMFSC0 ======================================================== */ + #define R_ETHA0_EATMFSC0_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC0_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC1 ======================================================== */ + #define R_ETHA0_EATMFSC1_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC1_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC2 ======================================================== */ + #define R_ETHA0_EATMFSC2_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC2_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC3 ======================================================== */ + #define R_ETHA0_EATMFSC3_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC3_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC4 ======================================================== */ + #define R_ETHA0_EATMFSC4_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC4_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC5 ======================================================== */ + #define R_ETHA0_EATMFSC5_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC5_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC6 ======================================================== */ + #define R_ETHA0_EATMFSC6_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC6_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC7 ======================================================== */ + #define R_ETHA0_EATMFSC7_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC7_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATDQDC0 ======================================================== */ + #define R_ETHA0_EATDQDC0_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC0_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC1 ======================================================== */ + #define R_ETHA0_EATDQDC1_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC1_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC2 ======================================================== */ + #define R_ETHA0_EATDQDC2_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC2_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC3 ======================================================== */ + #define R_ETHA0_EATDQDC3_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC3_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC4 ======================================================== */ + #define R_ETHA0_EATDQDC4_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC4_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC5 ======================================================== */ + #define R_ETHA0_EATDQDC5_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC5_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC6 ======================================================== */ + #define R_ETHA0_EATDQDC6_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC6_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC7 ======================================================== */ + #define R_ETHA0_EATDQDC7_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC7_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM0 ======================================================== */ + #define R_ETHA0_EATDQM0_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM0_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM1 ======================================================== */ + #define R_ETHA0_EATDQM1_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM1_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM2 ======================================================== */ + #define R_ETHA0_EATDQM2_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM2_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM3 ======================================================== */ + #define R_ETHA0_EATDQM3_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM3_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM4 ======================================================== */ + #define R_ETHA0_EATDQM4_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM4_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM5 ======================================================== */ + #define R_ETHA0_EATDQM5_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM5_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM6 ======================================================== */ + #define R_ETHA0_EATDQM6_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM6_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM7 ======================================================== */ + #define R_ETHA0_EATDQM7_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM7_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM0 ======================================================= */ + #define R_ETHA0_EATDQMLM0_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM0_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM1 ======================================================= */ + #define R_ETHA0_EATDQMLM1_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM1_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM2 ======================================================= */ + #define R_ETHA0_EATDQMLM2_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM2_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM3 ======================================================= */ + #define R_ETHA0_EATDQMLM3_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM3_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM4 ======================================================= */ + #define R_ETHA0_EATDQMLM4_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM4_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM5 ======================================================= */ + #define R_ETHA0_EATDQMLM5_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM5_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM6 ======================================================= */ + #define R_ETHA0_EATDQMLM6_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM6_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM7 ======================================================= */ + #define R_ETHA0_EATDQMLM7_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM7_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EACTQC ========================================================= */ + #define R_ETHA0_EACTQC_CTQD_Pos (0UL) /*!< CTQD (Bit 0) */ + #define R_ETHA0_EACTQC_CTQD_Msk (0xffffUL) /*!< CTQD (Bitfield-Mask: 0xffff) */ +/* ======================================================= EACTDQDC ======================================================== */ + #define R_ETHA0_EACTDQDC_CTDQD_Pos (0UL) /*!< CTDQD (Bit 0) */ + #define R_ETHA0_EACTDQDC_CTDQD_Msk (0xfUL) /*!< CTDQD (Bitfield-Mask: 0x0f) */ +/* ======================================================== EACTDQM ======================================================== */ + #define R_ETHA0_EACTDQM_CTQDN_Pos (0UL) /*!< CTQDN (Bit 0) */ + #define R_ETHA0_EACTDQM_CTQDN_Msk (0x3ffUL) /*!< CTQDN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= EACTDQMLM ======================================================= */ + #define R_ETHA0_EACTDQMLM_CTDMLQ_Pos (0UL) /*!< CTDMLQ (Bit 0) */ + #define R_ETHA0_EACTDQMLM_CTDMLQ_Msk (0xfUL) /*!< CTDMLQ (Bitfield-Mask: 0x0f) */ +/* ========================================================= EAVCC ========================================================= */ + #define R_ETHA0_EAVCC_VIM_Pos (0UL) /*!< VIM (Bit 0) */ + #define R_ETHA0_EAVCC_VIM_Msk (0x1UL) /*!< VIM (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAVCC_VEM_Pos (16UL) /*!< VEM (Bit 16) */ + #define R_ETHA0_EAVCC_VEM_Msk (0x70000UL) /*!< VEM (Bitfield-Mask: 0x07) */ +/* ========================================================= EAVTC ========================================================= */ + #define R_ETHA0_EAVTC_CTV_Pos (0UL) /*!< CTV (Bit 0) */ + #define R_ETHA0_EAVTC_CTV_Msk (0xfffUL) /*!< CTV (Bitfield-Mask: 0xfff) */ + #define R_ETHA0_EAVTC_CTP_Pos (12UL) /*!< CTP (Bit 12) */ + #define R_ETHA0_EAVTC_CTP_Msk (0x7000UL) /*!< CTP (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAVTC_CTD_Pos (15UL) /*!< CTD (Bit 15) */ + #define R_ETHA0_EAVTC_CTD_Msk (0x8000UL) /*!< CTD (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAVTC_STV_Pos (16UL) /*!< STV (Bit 16) */ + #define R_ETHA0_EAVTC_STV_Msk (0xfff0000UL) /*!< STV (Bitfield-Mask: 0xfff) */ + #define R_ETHA0_EAVTC_STP_Pos (28UL) /*!< STP (Bit 28) */ + #define R_ETHA0_EAVTC_STP_Msk (0x70000000UL) /*!< STP (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAVTC_STD_Pos (31UL) /*!< STD (Bit 31) */ + #define R_ETHA0_EAVTC_STD_Msk (0x80000000UL) /*!< STD (Bitfield-Mask: 0x01) */ +/* ======================================================== EARTFC ========================================================= */ + #define R_ETHA0_EARTFC_NT_Pos (0UL) /*!< NT (Bit 0) */ + #define R_ETHA0_EARTFC_NT_Msk (0x1UL) /*!< NT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_RT_Pos (1UL) /*!< RT (Bit 1) */ + #define R_ETHA0_EARTFC_RT_Msk (0x2UL) /*!< RT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CST_Pos (2UL) /*!< CST (Bit 2) */ + #define R_ETHA0_EARTFC_CST_Msk (0x4UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CSRT_Pos (3UL) /*!< CSRT (Bit 3) */ + #define R_ETHA0_EARTFC_CSRT_Msk (0x8UL) /*!< CSRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CT_Pos (4UL) /*!< CT (Bit 4) */ + #define R_ETHA0_EARTFC_CT_Msk (0x10UL) /*!< CT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CRT_Pos (5UL) /*!< CRT (Bit 5) */ + #define R_ETHA0_EARTFC_CRT_Msk (0x20UL) /*!< CRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_SCT_Pos (6UL) /*!< SCT (Bit 6) */ + #define R_ETHA0_EARTFC_SCT_Msk (0x40UL) /*!< SCT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_SCRT_Pos (7UL) /*!< SCRT (Bit 7) */ + #define R_ETHA0_EARTFC_SCRT_Msk (0x80UL) /*!< SCRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_UT_Pos (8UL) /*!< UT (Bit 8) */ + #define R_ETHA0_EARTFC_UT_Msk (0x100UL) /*!< UT (Bitfield-Mask: 0x01) */ +/* ======================================================== EACAEC ========================================================= */ + #define R_ETHA0_EACAEC_CE0_Pos (0UL) /*!< CE0 (Bit 0) */ + #define R_ETHA0_EACAEC_CE0_Msk (0x1UL) /*!< CE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE1_Pos (1UL) /*!< CE1 (Bit 1) */ + #define R_ETHA0_EACAEC_CE1_Msk (0x2UL) /*!< CE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE2_Pos (2UL) /*!< CE2 (Bit 2) */ + #define R_ETHA0_EACAEC_CE2_Msk (0x4UL) /*!< CE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE3_Pos (3UL) /*!< CE3 (Bit 3) */ + #define R_ETHA0_EACAEC_CE3_Msk (0x8UL) /*!< CE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE4_Pos (4UL) /*!< CE4 (Bit 4) */ + #define R_ETHA0_EACAEC_CE4_Msk (0x10UL) /*!< CE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE5_Pos (5UL) /*!< CE5 (Bit 5) */ + #define R_ETHA0_EACAEC_CE5_Msk (0x20UL) /*!< CE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE6_Pos (6UL) /*!< CE6 (Bit 6) */ + #define R_ETHA0_EACAEC_CE6_Msk (0x40UL) /*!< CE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE7_Pos (7UL) /*!< CE7 (Bit 7) */ + #define R_ETHA0_EACAEC_CE7_Msk (0x80UL) /*!< CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= EACC ========================================================== */ + #define R_ETHA0_EACC_CC0_Pos (0UL) /*!< CC0 (Bit 0) */ + #define R_ETHA0_EACC_CC0_Msk (0x1UL) /*!< CC0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC1_Pos (1UL) /*!< CC1 (Bit 1) */ + #define R_ETHA0_EACC_CC1_Msk (0x2UL) /*!< CC1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC2_Pos (2UL) /*!< CC2 (Bit 2) */ + #define R_ETHA0_EACC_CC2_Msk (0x4UL) /*!< CC2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC3_Pos (3UL) /*!< CC3 (Bit 3) */ + #define R_ETHA0_EACC_CC3_Msk (0x8UL) /*!< CC3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC4_Pos (4UL) /*!< CC4 (Bit 4) */ + #define R_ETHA0_EACC_CC4_Msk (0x10UL) /*!< CC4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC5_Pos (5UL) /*!< CC5 (Bit 5) */ + #define R_ETHA0_EACC_CC5_Msk (0x20UL) /*!< CC5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC6_Pos (6UL) /*!< CC6 (Bit 6) */ + #define R_ETHA0_EACC_CC6_Msk (0x40UL) /*!< CC6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC7_Pos (7UL) /*!< CC7 (Bit 7) */ + #define R_ETHA0_EACC_CC7_Msk (0x80UL) /*!< CC7 (Bitfield-Mask: 0x01) */ +/* ======================================================= EACAIVC0 ======================================================== */ + #define R_ETHA0_EACAIVC0_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC0_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC1 ======================================================== */ + #define R_ETHA0_EACAIVC1_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC1_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC2 ======================================================== */ + #define R_ETHA0_EACAIVC2_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC2_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC3 ======================================================== */ + #define R_ETHA0_EACAIVC3_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC3_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC4 ======================================================== */ + #define R_ETHA0_EACAIVC4_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC4_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC5 ======================================================== */ + #define R_ETHA0_EACAIVC5_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC5_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC6 ======================================================== */ + #define R_ETHA0_EACAIVC6_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC6_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC7 ======================================================== */ + #define R_ETHA0_EACAIVC7_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC7_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAULC0 ======================================================== */ + #define R_ETHA0_EACAULC0_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC0_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC1 ======================================================== */ + #define R_ETHA0_EACAULC1_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC1_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC2 ======================================================== */ + #define R_ETHA0_EACAULC2_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC2_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC3 ======================================================== */ + #define R_ETHA0_EACAULC3_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC3_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC4 ======================================================== */ + #define R_ETHA0_EACAULC4_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC4_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC5 ======================================================== */ + #define R_ETHA0_EACAULC5_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC5_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC6 ======================================================== */ + #define R_ETHA0_EACAULC6_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC6_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC7 ======================================================== */ + #define R_ETHA0_EACAULC7_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC7_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================== EACOEM ========================================================= */ + #define R_ETHA0_EACOEM_CE0_Pos (0UL) /*!< CE0 (Bit 0) */ + #define R_ETHA0_EACOEM_CE0_Msk (0x1UL) /*!< CE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE1_Pos (1UL) /*!< CE1 (Bit 1) */ + #define R_ETHA0_EACOEM_CE1_Msk (0x2UL) /*!< CE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE2_Pos (2UL) /*!< CE2 (Bit 2) */ + #define R_ETHA0_EACOEM_CE2_Msk (0x4UL) /*!< CE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE3_Pos (3UL) /*!< CE3 (Bit 3) */ + #define R_ETHA0_EACOEM_CE3_Msk (0x8UL) /*!< CE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE4_Pos (4UL) /*!< CE4 (Bit 4) */ + #define R_ETHA0_EACOEM_CE4_Msk (0x10UL) /*!< CE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE5_Pos (5UL) /*!< CE5 (Bit 5) */ + #define R_ETHA0_EACOEM_CE5_Msk (0x20UL) /*!< CE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE6_Pos (6UL) /*!< CE6 (Bit 6) */ + #define R_ETHA0_EACOEM_CE6_Msk (0x40UL) /*!< CE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE7_Pos (7UL) /*!< CE7 (Bit 7) */ + #define R_ETHA0_EACOEM_CE7_Msk (0x80UL) /*!< CE7 (Bitfield-Mask: 0x01) */ +/* ======================================================= EACOIVM0 ======================================================== */ + #define R_ETHA0_EACOIVM0_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM0_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM1 ======================================================== */ + #define R_ETHA0_EACOIVM1_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM1_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM2 ======================================================== */ + #define R_ETHA0_EACOIVM2_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM2_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM3 ======================================================== */ + #define R_ETHA0_EACOIVM3_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM3_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM4 ======================================================== */ + #define R_ETHA0_EACOIVM4_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM4_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM5 ======================================================== */ + #define R_ETHA0_EACOIVM5_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM5_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM6 ======================================================== */ + #define R_ETHA0_EACOIVM6_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM6_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM7 ======================================================== */ + #define R_ETHA0_EACOIVM7_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM7_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOULM0 ======================================================== */ + #define R_ETHA0_EACOULM0_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM0_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM1 ======================================================== */ + #define R_ETHA0_EACOULM1_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM1_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM2 ======================================================== */ + #define R_ETHA0_EACOULM2_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM2_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM3 ======================================================== */ + #define R_ETHA0_EACOULM3_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM3_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM4 ======================================================== */ + #define R_ETHA0_EACOULM4_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM4_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM5 ======================================================== */ + #define R_ETHA0_EACOULM5_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM5_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM6 ======================================================== */ + #define R_ETHA0_EACOULM6_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM6_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM7 ======================================================== */ + #define R_ETHA0_EACOULM7_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM7_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================== EACGSM ========================================================= */ + #define R_ETHA0_EACGSM_CGS0_Pos (0UL) /*!< CGS0 (Bit 0) */ + #define R_ETHA0_EACGSM_CGS0_Msk (0x1UL) /*!< CGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS1_Pos (1UL) /*!< CGS1 (Bit 1) */ + #define R_ETHA0_EACGSM_CGS1_Msk (0x2UL) /*!< CGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS2_Pos (2UL) /*!< CGS2 (Bit 2) */ + #define R_ETHA0_EACGSM_CGS2_Msk (0x4UL) /*!< CGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS3_Pos (3UL) /*!< CGS3 (Bit 3) */ + #define R_ETHA0_EACGSM_CGS3_Msk (0x8UL) /*!< CGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS4_Pos (4UL) /*!< CGS4 (Bit 4) */ + #define R_ETHA0_EACGSM_CGS4_Msk (0x10UL) /*!< CGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS5_Pos (5UL) /*!< CGS5 (Bit 5) */ + #define R_ETHA0_EACGSM_CGS5_Msk (0x20UL) /*!< CGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS6_Pos (6UL) /*!< CGS6 (Bit 6) */ + #define R_ETHA0_EACGSM_CGS6_Msk (0x40UL) /*!< CGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS7_Pos (7UL) /*!< CGS7 (Bit 7) */ + #define R_ETHA0_EACGSM_CGS7_Msk (0x80UL) /*!< CGS7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASC ========================================================= */ + #define R_ETHA0_EATASC_TASE_Pos (0UL) /*!< TASE (Bit 0) */ + #define R_ETHA0_EATASC_TASE_Msk (0x1UL) /*!< TASE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCC_Pos (1UL) /*!< TASCC (Bit 1) */ + #define R_ETHA0_EATASC_TASCC_Msk (0x2UL) /*!< TASCC (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCI_Pos (2UL) /*!< TASCI (Bit 2) */ + #define R_ETHA0_EATASC_TASCI_Msk (0x4UL) /*!< TASCI (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASTS_Pos (8UL) /*!< TASTS (Bit 8) */ + #define R_ETHA0_EATASC_TASTS_Msk (0x100UL) /*!< TASTS (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCA_Pos (16UL) /*!< TASCA (Bit 16) */ + #define R_ETHA0_EATASC_TASCA_Msk (0xff0000UL) /*!< TASCA (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASIGSC ======================================================= */ + #define R_ETHA0_EATASIGSC_TASIGS0_Pos (0UL) /*!< TASIGS0 (Bit 0) */ + #define R_ETHA0_EATASIGSC_TASIGS0_Msk (0x1UL) /*!< TASIGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS1_Pos (1UL) /*!< TASIGS1 (Bit 1) */ + #define R_ETHA0_EATASIGSC_TASIGS1_Msk (0x2UL) /*!< TASIGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS2_Pos (2UL) /*!< TASIGS2 (Bit 2) */ + #define R_ETHA0_EATASIGSC_TASIGS2_Msk (0x4UL) /*!< TASIGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS3_Pos (3UL) /*!< TASIGS3 (Bit 3) */ + #define R_ETHA0_EATASIGSC_TASIGS3_Msk (0x8UL) /*!< TASIGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS4_Pos (4UL) /*!< TASIGS4 (Bit 4) */ + #define R_ETHA0_EATASIGSC_TASIGS4_Msk (0x10UL) /*!< TASIGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS5_Pos (5UL) /*!< TASIGS5 (Bit 5) */ + #define R_ETHA0_EATASIGSC_TASIGS5_Msk (0x20UL) /*!< TASIGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS6_Pos (6UL) /*!< TASIGS6 (Bit 6) */ + #define R_ETHA0_EATASIGSC_TASIGS6_Msk (0x40UL) /*!< TASIGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS7_Pos (7UL) /*!< TASIGS7 (Bit 7) */ + #define R_ETHA0_EATASIGSC_TASIGS7_Msk (0x80UL) /*!< TASIGS7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASCTIGS_Pos (8UL) /*!< TASCTIGS (Bit 8) */ + #define R_ETHA0_EATASIGSC_TASCTIGS_Msk (0x100UL) /*!< TASCTIGS (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASENC0 ======================================================= */ + #define R_ETHA0_EATASENC0_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC0_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC1 ======================================================= */ + #define R_ETHA0_EATASENC1_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC1_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC2 ======================================================= */ + #define R_ETHA0_EATASENC2_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC2_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC3 ======================================================= */ + #define R_ETHA0_EATASENC3_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC3_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC4 ======================================================= */ + #define R_ETHA0_EATASENC4_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC4_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC5 ======================================================= */ + #define R_ETHA0_EATASENC5_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC5_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC6 ======================================================= */ + #define R_ETHA0_EATASENC6_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC6_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC7 ======================================================= */ + #define R_ETHA0_EATASENC7_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC7_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCTENC ======================================================= */ + #define R_ETHA0_EATASCTENC_TASCTAEN_Pos (0UL) /*!< TASCTAEN (Bit 0) */ + #define R_ETHA0_EATASCTENC_TASCTAEN_Msk (0x1ffUL) /*!< TASCTAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM0 ======================================================= */ + #define R_ETHA0_EATASENM0_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM0_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM1 ======================================================= */ + #define R_ETHA0_EATASENM1_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM1_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM2 ======================================================= */ + #define R_ETHA0_EATASENM2_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM2_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM3 ======================================================= */ + #define R_ETHA0_EATASENM3_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM3_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM4 ======================================================= */ + #define R_ETHA0_EATASENM4_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM4_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM5 ======================================================= */ + #define R_ETHA0_EATASENM5_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM5_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM6 ======================================================= */ + #define R_ETHA0_EATASENM6_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM6_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM7 ======================================================= */ + #define R_ETHA0_EATASENM7_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM7_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCTENM ======================================================= */ + #define R_ETHA0_EATASCTENM_TASCTOEN_Pos (0UL) /*!< TASCTOEN (Bit 0) */ + #define R_ETHA0_EATASCTENM_TASCTOEN_Msk (0x1ffUL) /*!< TASCTOEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCSTC0 ======================================================= */ + #define R_ETHA0_EATASCSTC0_TASACSTP0_Pos (0UL) /*!< TASACSTP0 (Bit 0) */ + #define R_ETHA0_EATASCSTC0_TASACSTP0_Msk (0xffffffffUL) /*!< TASACSTP0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTC1 ======================================================= */ + #define R_ETHA0_EATASCSTC1_TASACSTP1_Pos (0UL) /*!< TASACSTP1 (Bit 0) */ + #define R_ETHA0_EATASCSTC1_TASACSTP1_Msk (0xffffffffUL) /*!< TASACSTP1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTM0 ======================================================= */ + #define R_ETHA0_EATASCSTM0_TASOCSTP0_Pos (0UL) /*!< TASOCSTP0 (Bit 0) */ + #define R_ETHA0_EATASCSTM0_TASOCSTP0_Msk (0xffffffffUL) /*!< TASOCSTP0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTM1 ======================================================= */ + #define R_ETHA0_EATASCSTM1_TASOCSTP1_Pos (0UL) /*!< TASOCSTP1 (Bit 0) */ + #define R_ETHA0_EATASCSTM1_TASOCSTP1_Msk (0xffffffffUL) /*!< TASOCSTP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASCTC ======================================================== */ + #define R_ETHA0_EATASCTC_TASACT_Pos (0UL) /*!< TASACT (Bit 0) */ + #define R_ETHA0_EATASCTC_TASACT_Msk (0xffffffffUL) /*!< TASACT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASCTM ======================================================== */ + #define R_ETHA0_EATASCTM_TASOCT_Pos (0UL) /*!< TASOCT (Bit 0) */ + #define R_ETHA0_EATASCTM_TASOCT_Msk (0xffffffffUL) /*!< TASOCT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASGL0 ======================================================== */ + #define R_ETHA0_EATASGL0_TASGAL_Pos (0UL) /*!< TASGAL (Bit 0) */ + #define R_ETHA0_EATASGL0_TASGAL_Msk (0xffUL) /*!< TASGAL (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASGL1 ======================================================== */ + #define R_ETHA0_EATASGL1_TASGTL_Pos (0UL) /*!< TASGTL (Bit 0) */ + #define R_ETHA0_EATASGL1_TASGTL_Msk (0xfffffffUL) /*!< TASGTL (Bitfield-Mask: 0xfffffff) */ + #define R_ETHA0_EATASGL1_TASGSL_Pos (28UL) /*!< TASGSL (Bit 28) */ + #define R_ETHA0_EATASGL1_TASGSL_Msk (0x10000000UL) /*!< TASGSL (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASGLR ======================================================== */ + #define R_ETHA0_EATASGLR_GL_Pos (31UL) /*!< GL (Bit 31) */ + #define R_ETHA0_EATASGLR_GL_Msk (0x80000000UL) /*!< GL (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASGR ======================================================== */ + #define R_ETHA0_EATASGR_TASGAR_Pos (0UL) /*!< TASGAR (Bit 0) */ + #define R_ETHA0_EATASGR_TASGAR_Msk (0xffUL) /*!< TASGAR (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASGRR ======================================================== */ + #define R_ETHA0_EATASGRR_TASGTR_Pos (0UL) /*!< TASGTR (Bit 0) */ + #define R_ETHA0_EATASGRR_TASGTR_Msk (0xfffffffUL) /*!< TASGTR (Bitfield-Mask: 0xfffffff) */ + #define R_ETHA0_EATASGRR_TASGSR_Pos (28UL) /*!< TASGSR (Bit 28) */ + #define R_ETHA0_EATASGRR_TASGSR_Msk (0x10000000UL) /*!< TASGSR (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASGRR_TASREF_Pos (29UL) /*!< TASREF (Bit 29) */ + #define R_ETHA0_EATASGRR_TASREF_Msk (0x20000000UL) /*!< TASREF (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASGRR_GR_Pos (31UL) /*!< GR (Bit 31) */ + #define R_ETHA0_EATASGRR_GR_Msk (0x80000000UL) /*!< GR (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASHCC ======================================================== */ + #define R_ETHA0_EATASHCC_TASJ_Pos (0UL) /*!< TASJ (Bit 0) */ + #define R_ETHA0_EATASHCC_TASJ_Msk (0xffffUL) /*!< TASJ (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATASRIRM ======================================================= */ + #define R_ETHA0_EATASRIRM_TASRIOG_Pos (0UL) /*!< TASRIOG (Bit 0) */ + #define R_ETHA0_EATASRIRM_TASRIOG_Msk (0x1UL) /*!< TASRIOG (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASRIRM_TASRR_Pos (1UL) /*!< TASRR (Bit 1) */ + #define R_ETHA0_EATASRIRM_TASRR_Msk (0x2UL) /*!< TASRR (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASSM ======================================================== */ + #define R_ETHA0_EATASSM_TASGS0_Pos (0UL) /*!< TASGS0 (Bit 0) */ + #define R_ETHA0_EATASSM_TASGS0_Msk (0x1UL) /*!< TASGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS1_Pos (1UL) /*!< TASGS1 (Bit 1) */ + #define R_ETHA0_EATASSM_TASGS1_Msk (0x2UL) /*!< TASGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS2_Pos (2UL) /*!< TASGS2 (Bit 2) */ + #define R_ETHA0_EATASSM_TASGS2_Msk (0x4UL) /*!< TASGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS3_Pos (3UL) /*!< TASGS3 (Bit 3) */ + #define R_ETHA0_EATASSM_TASGS3_Msk (0x8UL) /*!< TASGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS4_Pos (4UL) /*!< TASGS4 (Bit 4) */ + #define R_ETHA0_EATASSM_TASGS4_Msk (0x10UL) /*!< TASGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS5_Pos (5UL) /*!< TASGS5 (Bit 5) */ + #define R_ETHA0_EATASSM_TASGS5_Msk (0x20UL) /*!< TASGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS6_Pos (6UL) /*!< TASGS6 (Bit 6) */ + #define R_ETHA0_EATASSM_TASGS6_Msk (0x40UL) /*!< TASGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS7_Pos (7UL) /*!< TASGS7 (Bit 7) */ + #define R_ETHA0_EATASSM_TASGS7_Msk (0x80UL) /*!< TASGS7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASCTGS_Pos (8UL) /*!< TASCTGS (Bit 8) */ + #define R_ETHA0_EATASSM_TASCTGS_Msk (0x100UL) /*!< TASCTGS (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASSO_Pos (16UL) /*!< TASSO (Bit 16) */ + #define R_ETHA0_EATASSM_TASSO_Msk (0x10000UL) /*!< TASSO (Bitfield-Mask: 0x01) */ +/* ====================================================== EAUSMFSECN ======================================================= */ + #define R_ETHA0_EAUSMFSECN_USMFSEN_Pos (0UL) /*!< USMFSEN (Bit 0) */ + #define R_ETHA0_EAUSMFSECN_USMFSEN_Msk (0xffffUL) /*!< USMFSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EATFECN ======================================================== */ + #define R_ETHA0_EATFECN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ + #define R_ETHA0_EATFECN_TFEN_Msk (0xffffUL) /*!< TFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EAFSECN ======================================================== */ + #define R_ETHA0_EAFSECN_FSEN_Pos (0UL) /*!< FSEN (Bit 0) */ + #define R_ETHA0_EAFSECN_FSEN_Msk (0xffffUL) /*!< FSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= EADQOECN ======================================================== */ + #define R_ETHA0_EADQOECN_DQOEN_Pos (0UL) /*!< DQOEN (Bit 0) */ + #define R_ETHA0_EADQOECN_DQOEN_Msk (0xffffUL) /*!< DQOEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= EADQSECN ======================================================== */ + #define R_ETHA0_EADQSECN_DQSEN_Pos (0UL) /*!< DQSEN (Bit 0) */ + #define R_ETHA0_EADQSECN_DQSEN_Msk (0xffffUL) /*!< DQSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EAEIS0 ========================================================= */ + #define R_ETHA0_EAEIS0_DECCES_Pos (0UL) /*!< DECCES (Bit 0) */ + #define R_ETHA0_EAEIS0_DECCES_Msk (0x1UL) /*!< DECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TECCES_Pos (1UL) /*!< TECCES (Bit 1) */ + #define R_ETHA0_EAEIS0_TECCES_Msk (0x2UL) /*!< TECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_PECCES_Pos (2UL) /*!< PECCES (Bit 2) */ + #define R_ETHA0_EAEIS0_PECCES_Msk (0x4UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_DSECCES_Pos (3UL) /*!< DSECCES (Bit 3) */ + #define R_ETHA0_EAEIS0_DSECCES_Msk (0x8UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_L23UECCES_Pos (4UL) /*!< L23UECCES (Bit 4) */ + #define R_ETHA0_EAEIS0_L23UECCES_Msk (0x10UL) /*!< L23UECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_USMFSES_Pos (5UL) /*!< USMFSES (Bit 5) */ + #define R_ETHA0_EAEIS0_USMFSES_Msk (0x20UL) /*!< USMFSES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TFES_Pos (6UL) /*!< TFES (Bit 6) */ + #define R_ETHA0_EAEIS0_TFES_Msk (0x40UL) /*!< TFES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES0_Pos (8UL) /*!< FSES0 (Bit 8) */ + #define R_ETHA0_EAEIS0_FSES0_Msk (0x100UL) /*!< FSES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES1_Pos (9UL) /*!< FSES1 (Bit 9) */ + #define R_ETHA0_EAEIS0_FSES1_Msk (0x200UL) /*!< FSES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES2_Pos (10UL) /*!< FSES2 (Bit 10) */ + #define R_ETHA0_EAEIS0_FSES2_Msk (0x400UL) /*!< FSES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES3_Pos (11UL) /*!< FSES3 (Bit 11) */ + #define R_ETHA0_EAEIS0_FSES3_Msk (0x800UL) /*!< FSES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES4_Pos (12UL) /*!< FSES4 (Bit 12) */ + #define R_ETHA0_EAEIS0_FSES4_Msk (0x1000UL) /*!< FSES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES5_Pos (13UL) /*!< FSES5 (Bit 13) */ + #define R_ETHA0_EAEIS0_FSES5_Msk (0x2000UL) /*!< FSES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES6_Pos (14UL) /*!< FSES6 (Bit 14) */ + #define R_ETHA0_EAEIS0_FSES6_Msk (0x4000UL) /*!< FSES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES7_Pos (15UL) /*!< FSES7 (Bit 15) */ + #define R_ETHA0_EAEIS0_FSES7_Msk (0x8000UL) /*!< FSES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES0_Pos (16UL) /*!< TASGEES0 (Bit 16) */ + #define R_ETHA0_EAEIS0_TASGEES0_Msk (0x10000UL) /*!< TASGEES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES1_Pos (17UL) /*!< TASGEES1 (Bit 17) */ + #define R_ETHA0_EAEIS0_TASGEES1_Msk (0x20000UL) /*!< TASGEES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES2_Pos (18UL) /*!< TASGEES2 (Bit 18) */ + #define R_ETHA0_EAEIS0_TASGEES2_Msk (0x40000UL) /*!< TASGEES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES3_Pos (19UL) /*!< TASGEES3 (Bit 19) */ + #define R_ETHA0_EAEIS0_TASGEES3_Msk (0x80000UL) /*!< TASGEES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES4_Pos (20UL) /*!< TASGEES4 (Bit 20) */ + #define R_ETHA0_EAEIS0_TASGEES4_Msk (0x100000UL) /*!< TASGEES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES5_Pos (21UL) /*!< TASGEES5 (Bit 21) */ + #define R_ETHA0_EAEIS0_TASGEES5_Msk (0x200000UL) /*!< TASGEES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES6_Pos (22UL) /*!< TASGEES6 (Bit 22) */ + #define R_ETHA0_EAEIS0_TASGEES6_Msk (0x400000UL) /*!< TASGEES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES7_Pos (23UL) /*!< TASGEES7 (Bit 23) */ + #define R_ETHA0_EAEIS0_TASGEES7_Msk (0x800000UL) /*!< TASGEES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASCTGEES_Pos (24UL) /*!< TASCTGEES (Bit 24) */ + #define R_ETHA0_EAEIS0_TASCTGEES_Msk (0x1000000UL) /*!< TASCTGEES (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE0 ========================================================= */ + #define R_ETHA0_EAEIE0_DECCEE_Pos (0UL) /*!< DECCEE (Bit 0) */ + #define R_ETHA0_EAEIE0_DECCEE_Msk (0x1UL) /*!< DECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TECCEE_Pos (1UL) /*!< TECCEE (Bit 1) */ + #define R_ETHA0_EAEIE0_TECCEE_Msk (0x2UL) /*!< TECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_PECCEE_Pos (2UL) /*!< PECCEE (Bit 2) */ + #define R_ETHA0_EAEIE0_PECCEE_Msk (0x4UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_DSECCEE_Pos (3UL) /*!< DSECCEE (Bit 3) */ + #define R_ETHA0_EAEIE0_DSECCEE_Msk (0x8UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_L23UECCEE_Pos (4UL) /*!< L23UECCEE (Bit 4) */ + #define R_ETHA0_EAEIE0_L23UECCEE_Msk (0x10UL) /*!< L23UECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_USMFSEE_Pos (5UL) /*!< USMFSEE (Bit 5) */ + #define R_ETHA0_EAEIE0_USMFSEE_Msk (0x20UL) /*!< USMFSEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TFEE_Pos (6UL) /*!< TFEE (Bit 6) */ + #define R_ETHA0_EAEIE0_TFEE_Msk (0x40UL) /*!< TFEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE0_Pos (8UL) /*!< FSEE0 (Bit 8) */ + #define R_ETHA0_EAEIE0_FSEE0_Msk (0x100UL) /*!< FSEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE1_Pos (9UL) /*!< FSEE1 (Bit 9) */ + #define R_ETHA0_EAEIE0_FSEE1_Msk (0x200UL) /*!< FSEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE2_Pos (10UL) /*!< FSEE2 (Bit 10) */ + #define R_ETHA0_EAEIE0_FSEE2_Msk (0x400UL) /*!< FSEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE3_Pos (11UL) /*!< FSEE3 (Bit 11) */ + #define R_ETHA0_EAEIE0_FSEE3_Msk (0x800UL) /*!< FSEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE4_Pos (12UL) /*!< FSEE4 (Bit 12) */ + #define R_ETHA0_EAEIE0_FSEE4_Msk (0x1000UL) /*!< FSEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE5_Pos (13UL) /*!< FSEE5 (Bit 13) */ + #define R_ETHA0_EAEIE0_FSEE5_Msk (0x2000UL) /*!< FSEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE6_Pos (14UL) /*!< FSEE6 (Bit 14) */ + #define R_ETHA0_EAEIE0_FSEE6_Msk (0x4000UL) /*!< FSEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE7_Pos (15UL) /*!< FSEE7 (Bit 15) */ + #define R_ETHA0_EAEIE0_FSEE7_Msk (0x8000UL) /*!< FSEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE0_Pos (16UL) /*!< TASGEEE0 (Bit 16) */ + #define R_ETHA0_EAEIE0_TASGEEE0_Msk (0x10000UL) /*!< TASGEEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE1_Pos (17UL) /*!< TASGEEE1 (Bit 17) */ + #define R_ETHA0_EAEIE0_TASGEEE1_Msk (0x20000UL) /*!< TASGEEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE2_Pos (18UL) /*!< TASGEEE2 (Bit 18) */ + #define R_ETHA0_EAEIE0_TASGEEE2_Msk (0x40000UL) /*!< TASGEEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE3_Pos (19UL) /*!< TASGEEE3 (Bit 19) */ + #define R_ETHA0_EAEIE0_TASGEEE3_Msk (0x80000UL) /*!< TASGEEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE4_Pos (20UL) /*!< TASGEEE4 (Bit 20) */ + #define R_ETHA0_EAEIE0_TASGEEE4_Msk (0x100000UL) /*!< TASGEEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE5_Pos (21UL) /*!< TASGEEE5 (Bit 21) */ + #define R_ETHA0_EAEIE0_TASGEEE5_Msk (0x200000UL) /*!< TASGEEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE6_Pos (22UL) /*!< TASGEEE6 (Bit 22) */ + #define R_ETHA0_EAEIE0_TASGEEE6_Msk (0x400000UL) /*!< TASGEEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE7_Pos (23UL) /*!< TASGEEE7 (Bit 23) */ + #define R_ETHA0_EAEIE0_TASGEEE7_Msk (0x800000UL) /*!< TASGEEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASCTGEEE_Pos (24UL) /*!< TASCTGEEE (Bit 24) */ + #define R_ETHA0_EAEIE0_TASCTGEEE_Msk (0x1000000UL) /*!< TASCTGEEE (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID0 ========================================================= */ + #define R_ETHA0_EAEID0_DECCED_Pos (0UL) /*!< DECCED (Bit 0) */ + #define R_ETHA0_EAEID0_DECCED_Msk (0x1UL) /*!< DECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TECCED_Pos (1UL) /*!< TECCED (Bit 1) */ + #define R_ETHA0_EAEID0_TECCED_Msk (0x2UL) /*!< TECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_PECCED_Pos (2UL) /*!< PECCED (Bit 2) */ + #define R_ETHA0_EAEID0_PECCED_Msk (0x4UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_DSECCED_Pos (3UL) /*!< DSECCED (Bit 3) */ + #define R_ETHA0_EAEID0_DSECCED_Msk (0x8UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_L23UECCED_Pos (4UL) /*!< L23UECCED (Bit 4) */ + #define R_ETHA0_EAEID0_L23UECCED_Msk (0x10UL) /*!< L23UECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_USMFSED_Pos (5UL) /*!< USMFSED (Bit 5) */ + #define R_ETHA0_EAEID0_USMFSED_Msk (0x20UL) /*!< USMFSED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TFED_Pos (6UL) /*!< TFED (Bit 6) */ + #define R_ETHA0_EAEID0_TFED_Msk (0x40UL) /*!< TFED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED0_Pos (8UL) /*!< FSED0 (Bit 8) */ + #define R_ETHA0_EAEID0_FSED0_Msk (0x100UL) /*!< FSED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED1_Pos (9UL) /*!< FSED1 (Bit 9) */ + #define R_ETHA0_EAEID0_FSED1_Msk (0x200UL) /*!< FSED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED2_Pos (10UL) /*!< FSED2 (Bit 10) */ + #define R_ETHA0_EAEID0_FSED2_Msk (0x400UL) /*!< FSED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED3_Pos (11UL) /*!< FSED3 (Bit 11) */ + #define R_ETHA0_EAEID0_FSED3_Msk (0x800UL) /*!< FSED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED4_Pos (12UL) /*!< FSED4 (Bit 12) */ + #define R_ETHA0_EAEID0_FSED4_Msk (0x1000UL) /*!< FSED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED5_Pos (13UL) /*!< FSED5 (Bit 13) */ + #define R_ETHA0_EAEID0_FSED5_Msk (0x2000UL) /*!< FSED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED6_Pos (14UL) /*!< FSED6 (Bit 14) */ + #define R_ETHA0_EAEID0_FSED6_Msk (0x4000UL) /*!< FSED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED7_Pos (15UL) /*!< FSED7 (Bit 15) */ + #define R_ETHA0_EAEID0_FSED7_Msk (0x8000UL) /*!< FSED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED0_Pos (16UL) /*!< TASGEED0 (Bit 16) */ + #define R_ETHA0_EAEID0_TASGEED0_Msk (0x10000UL) /*!< TASGEED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED1_Pos (17UL) /*!< TASGEED1 (Bit 17) */ + #define R_ETHA0_EAEID0_TASGEED1_Msk (0x20000UL) /*!< TASGEED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED2_Pos (18UL) /*!< TASGEED2 (Bit 18) */ + #define R_ETHA0_EAEID0_TASGEED2_Msk (0x40000UL) /*!< TASGEED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED3_Pos (19UL) /*!< TASGEED3 (Bit 19) */ + #define R_ETHA0_EAEID0_TASGEED3_Msk (0x80000UL) /*!< TASGEED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED4_Pos (20UL) /*!< TASGEED4 (Bit 20) */ + #define R_ETHA0_EAEID0_TASGEED4_Msk (0x100000UL) /*!< TASGEED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED5_Pos (21UL) /*!< TASGEED5 (Bit 21) */ + #define R_ETHA0_EAEID0_TASGEED5_Msk (0x200000UL) /*!< TASGEED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED6_Pos (22UL) /*!< TASGEED6 (Bit 22) */ + #define R_ETHA0_EAEID0_TASGEED6_Msk (0x400000UL) /*!< TASGEED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED7_Pos (23UL) /*!< TASGEED7 (Bit 23) */ + #define R_ETHA0_EAEID0_TASGEED7_Msk (0x800000UL) /*!< TASGEED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASCTGEED_Pos (24UL) /*!< TASCTGEED (Bit 24) */ + #define R_ETHA0_EAEID0_TASCTGEED_Msk (0x1000000UL) /*!< TASCTGEED (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIS1 ========================================================= */ + #define R_ETHA0_EAEIS1_CULES0_Pos (0UL) /*!< CULES0 (Bit 0) */ + #define R_ETHA0_EAEIS1_CULES0_Msk (0x1UL) /*!< CULES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES1_Pos (1UL) /*!< CULES1 (Bit 1) */ + #define R_ETHA0_EAEIS1_CULES1_Msk (0x2UL) /*!< CULES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES2_Pos (2UL) /*!< CULES2 (Bit 2) */ + #define R_ETHA0_EAEIS1_CULES2_Msk (0x4UL) /*!< CULES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES3_Pos (3UL) /*!< CULES3 (Bit 3) */ + #define R_ETHA0_EAEIS1_CULES3_Msk (0x8UL) /*!< CULES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES4_Pos (4UL) /*!< CULES4 (Bit 4) */ + #define R_ETHA0_EAEIS1_CULES4_Msk (0x10UL) /*!< CULES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES5_Pos (5UL) /*!< CULES5 (Bit 5) */ + #define R_ETHA0_EAEIS1_CULES5_Msk (0x20UL) /*!< CULES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES6_Pos (6UL) /*!< CULES6 (Bit 6) */ + #define R_ETHA0_EAEIS1_CULES6_Msk (0x40UL) /*!< CULES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES7_Pos (7UL) /*!< CULES7 (Bit 7) */ + #define R_ETHA0_EAEIS1_CULES7_Msk (0x80UL) /*!< CULES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES0_Pos (16UL) /*!< TASGES0 (Bit 16) */ + #define R_ETHA0_EAEIS1_TASGES0_Msk (0x10000UL) /*!< TASGES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES1_Pos (17UL) /*!< TASGES1 (Bit 17) */ + #define R_ETHA0_EAEIS1_TASGES1_Msk (0x20000UL) /*!< TASGES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES2_Pos (18UL) /*!< TASGES2 (Bit 18) */ + #define R_ETHA0_EAEIS1_TASGES2_Msk (0x40000UL) /*!< TASGES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES3_Pos (19UL) /*!< TASGES3 (Bit 19) */ + #define R_ETHA0_EAEIS1_TASGES3_Msk (0x80000UL) /*!< TASGES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES4_Pos (20UL) /*!< TASGES4 (Bit 20) */ + #define R_ETHA0_EAEIS1_TASGES4_Msk (0x100000UL) /*!< TASGES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES5_Pos (21UL) /*!< TASGES5 (Bit 21) */ + #define R_ETHA0_EAEIS1_TASGES5_Msk (0x200000UL) /*!< TASGES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES6_Pos (22UL) /*!< TASGES6 (Bit 22) */ + #define R_ETHA0_EAEIS1_TASGES6_Msk (0x400000UL) /*!< TASGES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES7_Pos (23UL) /*!< TASGES7 (Bit 23) */ + #define R_ETHA0_EAEIS1_TASGES7_Msk (0x800000UL) /*!< TASGES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASCTGES_Pos (24UL) /*!< TASCTGES (Bit 24) */ + #define R_ETHA0_EAEIS1_TASCTGES_Msk (0x1000000UL) /*!< TASCTGES (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE1 ========================================================= */ + #define R_ETHA0_EAEIE1_CULEE0_Pos (0UL) /*!< CULEE0 (Bit 0) */ + #define R_ETHA0_EAEIE1_CULEE0_Msk (0x1UL) /*!< CULEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE1_Pos (1UL) /*!< CULEE1 (Bit 1) */ + #define R_ETHA0_EAEIE1_CULEE1_Msk (0x2UL) /*!< CULEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE2_Pos (2UL) /*!< CULEE2 (Bit 2) */ + #define R_ETHA0_EAEIE1_CULEE2_Msk (0x4UL) /*!< CULEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE3_Pos (3UL) /*!< CULEE3 (Bit 3) */ + #define R_ETHA0_EAEIE1_CULEE3_Msk (0x8UL) /*!< CULEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE4_Pos (4UL) /*!< CULEE4 (Bit 4) */ + #define R_ETHA0_EAEIE1_CULEE4_Msk (0x10UL) /*!< CULEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE5_Pos (5UL) /*!< CULEE5 (Bit 5) */ + #define R_ETHA0_EAEIE1_CULEE5_Msk (0x20UL) /*!< CULEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE6_Pos (6UL) /*!< CULEE6 (Bit 6) */ + #define R_ETHA0_EAEIE1_CULEE6_Msk (0x40UL) /*!< CULEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE7_Pos (7UL) /*!< CULEE7 (Bit 7) */ + #define R_ETHA0_EAEIE1_CULEE7_Msk (0x80UL) /*!< CULEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE0_Pos (16UL) /*!< TASGEE0 (Bit 16) */ + #define R_ETHA0_EAEIE1_TASGEE0_Msk (0x10000UL) /*!< TASGEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE1_Pos (17UL) /*!< TASGEE1 (Bit 17) */ + #define R_ETHA0_EAEIE1_TASGEE1_Msk (0x20000UL) /*!< TASGEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE2_Pos (18UL) /*!< TASGEE2 (Bit 18) */ + #define R_ETHA0_EAEIE1_TASGEE2_Msk (0x40000UL) /*!< TASGEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE3_Pos (19UL) /*!< TASGEE3 (Bit 19) */ + #define R_ETHA0_EAEIE1_TASGEE3_Msk (0x80000UL) /*!< TASGEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE4_Pos (20UL) /*!< TASGEE4 (Bit 20) */ + #define R_ETHA0_EAEIE1_TASGEE4_Msk (0x100000UL) /*!< TASGEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE5_Pos (21UL) /*!< TASGEE5 (Bit 21) */ + #define R_ETHA0_EAEIE1_TASGEE5_Msk (0x200000UL) /*!< TASGEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE6_Pos (22UL) /*!< TASGEE6 (Bit 22) */ + #define R_ETHA0_EAEIE1_TASGEE6_Msk (0x400000UL) /*!< TASGEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE7_Pos (23UL) /*!< TASGEE7 (Bit 23) */ + #define R_ETHA0_EAEIE1_TASGEE7_Msk (0x800000UL) /*!< TASGEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASCTGEE_Pos (24UL) /*!< TASCTGEE (Bit 24) */ + #define R_ETHA0_EAEIE1_TASCTGEE_Msk (0x1000000UL) /*!< TASCTGEE (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID1 ========================================================= */ + #define R_ETHA0_EAEID1_CULED0_Pos (0UL) /*!< CULED0 (Bit 0) */ + #define R_ETHA0_EAEID1_CULED0_Msk (0x1UL) /*!< CULED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED1_Pos (1UL) /*!< CULED1 (Bit 1) */ + #define R_ETHA0_EAEID1_CULED1_Msk (0x2UL) /*!< CULED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED2_Pos (2UL) /*!< CULED2 (Bit 2) */ + #define R_ETHA0_EAEID1_CULED2_Msk (0x4UL) /*!< CULED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED3_Pos (3UL) /*!< CULED3 (Bit 3) */ + #define R_ETHA0_EAEID1_CULED3_Msk (0x8UL) /*!< CULED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED4_Pos (4UL) /*!< CULED4 (Bit 4) */ + #define R_ETHA0_EAEID1_CULED4_Msk (0x10UL) /*!< CULED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED5_Pos (5UL) /*!< CULED5 (Bit 5) */ + #define R_ETHA0_EAEID1_CULED5_Msk (0x20UL) /*!< CULED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED6_Pos (6UL) /*!< CULED6 (Bit 6) */ + #define R_ETHA0_EAEID1_CULED6_Msk (0x40UL) /*!< CULED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED7_Pos (7UL) /*!< CULED7 (Bit 7) */ + #define R_ETHA0_EAEID1_CULED7_Msk (0x80UL) /*!< CULED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED0_Pos (16UL) /*!< TASGED0 (Bit 16) */ + #define R_ETHA0_EAEID1_TASGED0_Msk (0x10000UL) /*!< TASGED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED1_Pos (17UL) /*!< TASGED1 (Bit 17) */ + #define R_ETHA0_EAEID1_TASGED1_Msk (0x20000UL) /*!< TASGED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED2_Pos (18UL) /*!< TASGED2 (Bit 18) */ + #define R_ETHA0_EAEID1_TASGED2_Msk (0x40000UL) /*!< TASGED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED3_Pos (19UL) /*!< TASGED3 (Bit 19) */ + #define R_ETHA0_EAEID1_TASGED3_Msk (0x80000UL) /*!< TASGED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED4_Pos (20UL) /*!< TASGED4 (Bit 20) */ + #define R_ETHA0_EAEID1_TASGED4_Msk (0x100000UL) /*!< TASGED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED5_Pos (21UL) /*!< TASGED5 (Bit 21) */ + #define R_ETHA0_EAEID1_TASGED5_Msk (0x200000UL) /*!< TASGED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED6_Pos (22UL) /*!< TASGED6 (Bit 22) */ + #define R_ETHA0_EAEID1_TASGED6_Msk (0x400000UL) /*!< TASGED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED7_Pos (23UL) /*!< TASGED7 (Bit 23) */ + #define R_ETHA0_EAEID1_TASGED7_Msk (0x800000UL) /*!< TASGED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASCTGED_Pos (24UL) /*!< TASCTGED (Bit 24) */ + #define R_ETHA0_EAEID1_TASCTGED_Msk (0x1000000UL) /*!< TASCTGED (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIS2 ========================================================= */ + #define R_ETHA0_EAEIS2_DQOES0_Pos (0UL) /*!< DQOES0 (Bit 0) */ + #define R_ETHA0_EAEIS2_DQOES0_Msk (0x1UL) /*!< DQOES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES1_Pos (1UL) /*!< DQOES1 (Bit 1) */ + #define R_ETHA0_EAEIS2_DQOES1_Msk (0x2UL) /*!< DQOES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES2_Pos (2UL) /*!< DQOES2 (Bit 2) */ + #define R_ETHA0_EAEIS2_DQOES2_Msk (0x4UL) /*!< DQOES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES3_Pos (3UL) /*!< DQOES3 (Bit 3) */ + #define R_ETHA0_EAEIS2_DQOES3_Msk (0x8UL) /*!< DQOES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES4_Pos (4UL) /*!< DQOES4 (Bit 4) */ + #define R_ETHA0_EAEIS2_DQOES4_Msk (0x10UL) /*!< DQOES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES5_Pos (5UL) /*!< DQOES5 (Bit 5) */ + #define R_ETHA0_EAEIS2_DQOES5_Msk (0x20UL) /*!< DQOES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES6_Pos (6UL) /*!< DQOES6 (Bit 6) */ + #define R_ETHA0_EAEIS2_DQOES6_Msk (0x40UL) /*!< DQOES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES7_Pos (7UL) /*!< DQOES7 (Bit 7) */ + #define R_ETHA0_EAEIS2_DQOES7_Msk (0x80UL) /*!< DQOES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_CTDQOES_Pos (8UL) /*!< CTDQOES (Bit 8) */ + #define R_ETHA0_EAEIS2_CTDQOES_Msk (0x100UL) /*!< CTDQOES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES0_Pos (16UL) /*!< DQSES0 (Bit 16) */ + #define R_ETHA0_EAEIS2_DQSES0_Msk (0x10000UL) /*!< DQSES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES1_Pos (17UL) /*!< DQSES1 (Bit 17) */ + #define R_ETHA0_EAEIS2_DQSES1_Msk (0x20000UL) /*!< DQSES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES2_Pos (18UL) /*!< DQSES2 (Bit 18) */ + #define R_ETHA0_EAEIS2_DQSES2_Msk (0x40000UL) /*!< DQSES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES3_Pos (19UL) /*!< DQSES3 (Bit 19) */ + #define R_ETHA0_EAEIS2_DQSES3_Msk (0x80000UL) /*!< DQSES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES4_Pos (20UL) /*!< DQSES4 (Bit 20) */ + #define R_ETHA0_EAEIS2_DQSES4_Msk (0x100000UL) /*!< DQSES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES5_Pos (21UL) /*!< DQSES5 (Bit 21) */ + #define R_ETHA0_EAEIS2_DQSES5_Msk (0x200000UL) /*!< DQSES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES6_Pos (22UL) /*!< DQSES6 (Bit 22) */ + #define R_ETHA0_EAEIS2_DQSES6_Msk (0x400000UL) /*!< DQSES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES7_Pos (23UL) /*!< DQSES7 (Bit 23) */ + #define R_ETHA0_EAEIS2_DQSES7_Msk (0x800000UL) /*!< DQSES7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE2 ========================================================= */ + #define R_ETHA0_EAEIE2_DQOEE0_Pos (0UL) /*!< DQOEE0 (Bit 0) */ + #define R_ETHA0_EAEIE2_DQOEE0_Msk (0x1UL) /*!< DQOEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE1_Pos (1UL) /*!< DQOEE1 (Bit 1) */ + #define R_ETHA0_EAEIE2_DQOEE1_Msk (0x2UL) /*!< DQOEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE2_Pos (2UL) /*!< DQOEE2 (Bit 2) */ + #define R_ETHA0_EAEIE2_DQOEE2_Msk (0x4UL) /*!< DQOEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE3_Pos (3UL) /*!< DQOEE3 (Bit 3) */ + #define R_ETHA0_EAEIE2_DQOEE3_Msk (0x8UL) /*!< DQOEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE4_Pos (4UL) /*!< DQOEE4 (Bit 4) */ + #define R_ETHA0_EAEIE2_DQOEE4_Msk (0x10UL) /*!< DQOEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE5_Pos (5UL) /*!< DQOEE5 (Bit 5) */ + #define R_ETHA0_EAEIE2_DQOEE5_Msk (0x20UL) /*!< DQOEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE6_Pos (6UL) /*!< DQOEE6 (Bit 6) */ + #define R_ETHA0_EAEIE2_DQOEE6_Msk (0x40UL) /*!< DQOEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE7_Pos (7UL) /*!< DQOEE7 (Bit 7) */ + #define R_ETHA0_EAEIE2_DQOEE7_Msk (0x80UL) /*!< DQOEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_CTDQOEE_Pos (8UL) /*!< CTDQOEE (Bit 8) */ + #define R_ETHA0_EAEIE2_CTDQOEE_Msk (0x100UL) /*!< CTDQOEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE0_Pos (16UL) /*!< DQSEE0 (Bit 16) */ + #define R_ETHA0_EAEIE2_DQSEE0_Msk (0x10000UL) /*!< DQSEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE1_Pos (17UL) /*!< DQSEE1 (Bit 17) */ + #define R_ETHA0_EAEIE2_DQSEE1_Msk (0x20000UL) /*!< DQSEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE2_Pos (18UL) /*!< DQSEE2 (Bit 18) */ + #define R_ETHA0_EAEIE2_DQSEE2_Msk (0x40000UL) /*!< DQSEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE3_Pos (19UL) /*!< DQSEE3 (Bit 19) */ + #define R_ETHA0_EAEIE2_DQSEE3_Msk (0x80000UL) /*!< DQSEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE4_Pos (20UL) /*!< DQSEE4 (Bit 20) */ + #define R_ETHA0_EAEIE2_DQSEE4_Msk (0x100000UL) /*!< DQSEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE5_Pos (21UL) /*!< DQSEE5 (Bit 21) */ + #define R_ETHA0_EAEIE2_DQSEE5_Msk (0x200000UL) /*!< DQSEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE6_Pos (22UL) /*!< DQSEE6 (Bit 22) */ + #define R_ETHA0_EAEIE2_DQSEE6_Msk (0x400000UL) /*!< DQSEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE7_Pos (23UL) /*!< DQSEE7 (Bit 23) */ + #define R_ETHA0_EAEIE2_DQSEE7_Msk (0x800000UL) /*!< DQSEE7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID2 ========================================================= */ + #define R_ETHA0_EAEID2_DQOED0_Pos (0UL) /*!< DQOED0 (Bit 0) */ + #define R_ETHA0_EAEID2_DQOED0_Msk (0x1UL) /*!< DQOED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED1_Pos (1UL) /*!< DQOED1 (Bit 1) */ + #define R_ETHA0_EAEID2_DQOED1_Msk (0x2UL) /*!< DQOED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED2_Pos (2UL) /*!< DQOED2 (Bit 2) */ + #define R_ETHA0_EAEID2_DQOED2_Msk (0x4UL) /*!< DQOED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED3_Pos (3UL) /*!< DQOED3 (Bit 3) */ + #define R_ETHA0_EAEID2_DQOED3_Msk (0x8UL) /*!< DQOED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED4_Pos (4UL) /*!< DQOED4 (Bit 4) */ + #define R_ETHA0_EAEID2_DQOED4_Msk (0x10UL) /*!< DQOED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED5_Pos (5UL) /*!< DQOED5 (Bit 5) */ + #define R_ETHA0_EAEID2_DQOED5_Msk (0x20UL) /*!< DQOED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED6_Pos (6UL) /*!< DQOED6 (Bit 6) */ + #define R_ETHA0_EAEID2_DQOED6_Msk (0x40UL) /*!< DQOED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED7_Pos (7UL) /*!< DQOED7 (Bit 7) */ + #define R_ETHA0_EAEID2_DQOED7_Msk (0x80UL) /*!< DQOED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_CTDQOED_Pos (8UL) /*!< CTDQOED (Bit 8) */ + #define R_ETHA0_EAEID2_CTDQOED_Msk (0x100UL) /*!< CTDQOED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED0_Pos (16UL) /*!< DQSED0 (Bit 16) */ + #define R_ETHA0_EAEID2_DQSED0_Msk (0x10000UL) /*!< DQSED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED1_Pos (17UL) /*!< DQSED1 (Bit 17) */ + #define R_ETHA0_EAEID2_DQSED1_Msk (0x20000UL) /*!< DQSED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED2_Pos (18UL) /*!< DQSED2 (Bit 18) */ + #define R_ETHA0_EAEID2_DQSED2_Msk (0x40000UL) /*!< DQSED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED3_Pos (19UL) /*!< DQSED3 (Bit 19) */ + #define R_ETHA0_EAEID2_DQSED3_Msk (0x80000UL) /*!< DQSED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED4_Pos (20UL) /*!< DQSED4 (Bit 20) */ + #define R_ETHA0_EAEID2_DQSED4_Msk (0x100000UL) /*!< DQSED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED5_Pos (21UL) /*!< DQSED5 (Bit 21) */ + #define R_ETHA0_EAEID2_DQSED5_Msk (0x200000UL) /*!< DQSED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED6_Pos (22UL) /*!< DQSED6 (Bit 22) */ + #define R_ETHA0_EAEID2_DQSED6_Msk (0x400000UL) /*!< DQSED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED7_Pos (23UL) /*!< DQSED7 (Bit 23) */ + #define R_ETHA0_EAEID2_DQSED7_Msk (0x800000UL) /*!< DQSED7 (Bitfield-Mask: 0x01) */ +/* ========================================================= EASCR ========================================================= */ + #define R_ETHA0_EASCR_MRSL_Pos (0UL) /*!< MRSL (Bit 0) */ + #define R_ETHA0_EASCR_MRSL_Msk (0x1UL) /*!< MRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TRSL_Pos (1UL) /*!< TRSL (Bit 1) */ + #define R_ETHA0_EASCR_TRSL_Msk (0x2UL) /*!< TRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_MCRSL_Pos (2UL) /*!< MCRSL (Bit 2) */ + #define R_ETHA0_EASCR_MCRSL_Msk (0x4UL) /*!< MCRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TGRSL_Pos (3UL) /*!< TGRSL (Bit 3) */ + #define R_ETHA0_EASCR_TGRSL_Msk (0x8UL) /*!< TGRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TASRSL_Pos (4UL) /*!< TASRSL (Bit 4) */ + #define R_ETHA0_EASCR_TASRSL_Msk (0x10UL) /*!< TASRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_EIRSL_Pos (5UL) /*!< EIRSL (Bit 5) */ + #define R_ETHA0_EASCR_EIRSL_Msk (0x20UL) /*!< EIRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_CRSL_Pos (6UL) /*!< CRSL (Bit 6) */ + #define R_ETHA0_EASCR_CRSL_Msk (0x40UL) /*!< CRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL0_Pos (16UL) /*!< DQRSL0 (Bit 16) */ + #define R_ETHA0_EASCR_DQRSL0_Msk (0x10000UL) /*!< DQRSL0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL1_Pos (17UL) /*!< DQRSL1 (Bit 17) */ + #define R_ETHA0_EASCR_DQRSL1_Msk (0x20000UL) /*!< DQRSL1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL2_Pos (18UL) /*!< DQRSL2 (Bit 18) */ + #define R_ETHA0_EASCR_DQRSL2_Msk (0x40000UL) /*!< DQRSL2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL3_Pos (19UL) /*!< DQRSL3 (Bit 19) */ + #define R_ETHA0_EASCR_DQRSL3_Msk (0x80000UL) /*!< DQRSL3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL4_Pos (20UL) /*!< DQRSL4 (Bit 20) */ + #define R_ETHA0_EASCR_DQRSL4_Msk (0x100000UL) /*!< DQRSL4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL5_Pos (21UL) /*!< DQRSL5 (Bit 21) */ + #define R_ETHA0_EASCR_DQRSL5_Msk (0x200000UL) /*!< DQRSL5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL6_Pos (22UL) /*!< DQRSL6 (Bit 22) */ + #define R_ETHA0_EASCR_DQRSL6_Msk (0x400000UL) /*!< DQRSL6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL7_Pos (23UL) /*!< DQRSL7 (Bit 23) */ + #define R_ETHA0_EASCR_DQRSL7_Msk (0x800000UL) /*!< DQRSL7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PTPIPV ========================================================= */ + #define R_GPTP_PTPIPV_IPV_Pos (0UL) /*!< IPV (Bit 0) */ + #define R_GPTP_PTPIPV_IPV_Msk (0xffffffffUL) /*!< IPV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PTPTMEC ======================================================== */ + #define R_GPTP_PTPTMEC_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GPTP_PTPTMEC_TE_Msk (0x3UL) /*!< TE (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPTMDC ======================================================== */ + #define R_GPTP_PTPTMDC_TD_Pos (0UL) /*!< TD (Bit 0) */ + #define R_GPTP_PTPTMDC_TD_Msk (0x3UL) /*!< TD (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPTIVC0 ======================================================== */ + #define R_GPTP_PTPTIVC0_TIV_Pos (0UL) /*!< TIV (Bit 0) */ + #define R_GPTP_PTPTIVC0_TIV_Msk (0xffffffffUL) /*!< TIV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTIVC1 ======================================================== */ + #define R_GPTP_PTPTIVC1_TIV_Pos (0UL) /*!< TIV (Bit 0) */ + #define R_GPTP_PTPTIVC1_TIV_Msk (0xffffffffUL) /*!< TIV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCL0 ======================================================= */ + #define R_GPTP_PTPTOVCL0_TOVL_Pos (0UL) /*!< TOVL (Bit 0) */ + #define R_GPTP_PTPTOVCL0_TOVL_Msk (0x3fffffffUL) /*!< TOVL (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= PTPTOVCL1 ======================================================= */ + #define R_GPTP_PTPTOVCL1_TOVL_Pos (0UL) /*!< TOVL (Bit 0) */ + #define R_GPTP_PTPTOVCL1_TOVL_Msk (0x3fffffffUL) /*!< TOVL (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= PTPTOVCM0 ======================================================= */ + #define R_GPTP_PTPTOVCM0_TOVM_Pos (0UL) /*!< TOVM (Bit 0) */ + #define R_GPTP_PTPTOVCM0_TOVM_Msk (0xffffffffUL) /*!< TOVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCM1 ======================================================= */ + #define R_GPTP_PTPTOVCM1_TOVM_Pos (0UL) /*!< TOVM (Bit 0) */ + #define R_GPTP_PTPTOVCM1_TOVM_Msk (0xffffffffUL) /*!< TOVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCU0 ======================================================= */ + #define R_GPTP_PTPTOVCU0_TOVU_Pos (0UL) /*!< TOVU (Bit 0) */ + #define R_GPTP_PTPTOVCU0_TOVU_Msk (0xffffUL) /*!< TOVU (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPTOVCU1 ======================================================= */ + #define R_GPTP_PTPTOVCU1_TOVU_Pos (0UL) /*!< TOVU (Bit 0) */ + #define R_GPTP_PTPTOVCU1_TOVU_Msk (0xffffUL) /*!< TOVU (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPAVTPTML0 ====================================================== */ + #define R_GPTP_PTPAVTPTML0_AVTPL_Pos (0UL) /*!< AVTPL (Bit 0) */ + #define R_GPTP_PTPAVTPTML0_AVTPL_Msk (0xffffffffUL) /*!< AVTPL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTML1 ====================================================== */ + #define R_GPTP_PTPAVTPTML1_AVTPL_Pos (0UL) /*!< AVTPL (Bit 0) */ + #define R_GPTP_PTPAVTPTML1_AVTPL_Msk (0xffffffffUL) /*!< AVTPL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTMU0 ====================================================== */ + #define R_GPTP_PTPAVTPTMU0_AVTPU_Pos (0UL) /*!< AVTPU (Bit 0) */ + #define R_GPTP_PTPAVTPTMU0_AVTPU_Msk (0xffffffffUL) /*!< AVTPU (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTMU1 ====================================================== */ + #define R_GPTP_PTPAVTPTMU1_AVTPU_Pos (0UL) /*!< AVTPU (Bit 0) */ + #define R_GPTP_PTPAVTPTMU1_AVTPU_Msk (0xffffffffUL) /*!< AVTPU (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTML0 ====================================================== */ + #define R_GPTP_PTPGPTPTML0_GPTPL_Pos (0UL) /*!< GPTPL (Bit 0) */ + #define R_GPTP_PTPGPTPTML0_GPTPL_Msk (0x3fffffffUL) /*!< GPTPL (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== PTPGPTPTML1 ====================================================== */ + #define R_GPTP_PTPGPTPTML1_GPTPL_Pos (0UL) /*!< GPTPL (Bit 0) */ + #define R_GPTP_PTPGPTPTML1_GPTPL_Msk (0x3fffffffUL) /*!< GPTPL (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== PTPGPTPTMM0 ====================================================== */ + #define R_GPTP_PTPGPTPTMM0_GPTPM_Pos (0UL) /*!< GPTPM (Bit 0) */ + #define R_GPTP_PTPGPTPTMM0_GPTPM_Msk (0xffffffffUL) /*!< GPTPM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTMM1 ====================================================== */ + #define R_GPTP_PTPGPTPTMM1_GPTPM_Pos (0UL) /*!< GPTPM (Bit 0) */ + #define R_GPTP_PTPGPTPTMM1_GPTPM_Msk (0xffffffffUL) /*!< GPTPM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTMU0 ====================================================== */ + #define R_GPTP_PTPGPTPTMU0_GPTPU_Pos (0UL) /*!< GPTPU (Bit 0) */ + #define R_GPTP_PTPGPTPTMU0_GPTPU_Msk (0xffffUL) /*!< GPTPU (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPGPTPTMU1 ====================================================== */ + #define R_GPTP_PTPGPTPTMU1_GPTPU_Pos (0UL) /*!< GPTPU (Bit 0) */ + #define R_GPTP_PTPGPTPTMU1_GPTPU_Msk (0xffffUL) /*!< GPTPU (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPMCCC0 ======================================================== */ + #define R_GPTP_PTPMCCC0_MCPEE_Pos (0UL) /*!< MCPEE (Bit 0) */ + #define R_GPTP_PTPMCCC0_MCPEE_Msk (0x1UL) /*!< MCPEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCNEE_Pos (1UL) /*!< MCNEE (Bit 1) */ + #define R_GPTP_PTPMCCC0_MCNEE_Msk (0x2UL) /*!< MCNEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCTTS_Pos (2UL) /*!< MCTTS (Bit 2) */ + #define R_GPTP_PTPMCCC0_MCTTS_Msk (0x4UL) /*!< MCTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCTNS_Pos (3UL) /*!< MCTNS (Bit 3) */ + #define R_GPTP_PTPMCCC0_MCTNS_Msk (0x8UL) /*!< MCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCCR_Pos (16UL) /*!< MCCR (Bit 16) */ + #define R_GPTP_PTPMCCC0_MCCR_Msk (0x10000UL) /*!< MCCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCCC1 ======================================================== */ + #define R_GPTP_PTPMCCC1_MCPEE_Pos (0UL) /*!< MCPEE (Bit 0) */ + #define R_GPTP_PTPMCCC1_MCPEE_Msk (0x1UL) /*!< MCPEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCNEE_Pos (1UL) /*!< MCNEE (Bit 1) */ + #define R_GPTP_PTPMCCC1_MCNEE_Msk (0x2UL) /*!< MCNEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCTTS_Pos (2UL) /*!< MCTTS (Bit 2) */ + #define R_GPTP_PTPMCCC1_MCTTS_Msk (0x4UL) /*!< MCTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCTNS_Pos (3UL) /*!< MCTNS (Bit 3) */ + #define R_GPTP_PTPMCCC1_MCTNS_Msk (0x8UL) /*!< MCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCCR_Pos (16UL) /*!< MCCR (Bit 16) */ + #define R_GPTP_PTPMCCC1_MCCR_Msk (0x10000UL) /*!< MCCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCCML0 ======================================================= */ + #define R_GPTP_PTPMCCML0_MCCTVL_Pos (0UL) /*!< MCCTVL (Bit 0) */ + #define R_GPTP_PTPMCCML0_MCCTVL_Msk (0xffffffffUL) /*!< MCCTVL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCML1 ======================================================= */ + #define R_GPTP_PTPMCCML1_MCCTVL_Pos (0UL) /*!< MCCTVL (Bit 0) */ + #define R_GPTP_PTPMCCML1_MCCTVL_Msk (0xffffffffUL) /*!< MCCTVL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMM0 ======================================================= */ + #define R_GPTP_PTPMCCMM0_MCCTVM_Pos (0UL) /*!< MCCTVM (Bit 0) */ + #define R_GPTP_PTPMCCMM0_MCCTVM_Msk (0xffffffffUL) /*!< MCCTVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMM1 ======================================================= */ + #define R_GPTP_PTPMCCMM1_MCCTVM_Pos (0UL) /*!< MCCTVM (Bit 0) */ + #define R_GPTP_PTPMCCMM1_MCCTVM_Msk (0xffffffffUL) /*!< MCCTVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMU0 ======================================================= */ + #define R_GPTP_PTPMCCMU0_MCCTVU_Pos (0UL) /*!< MCCTVU (Bit 0) */ + #define R_GPTP_PTPMCCMU0_MCCTVU_Msk (0xffffUL) /*!< MCCTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCCMU0_MCPEC_Pos (16UL) /*!< MCPEC (Bit 16) */ + #define R_GPTP_PTPMCCMU0_MCPEC_Msk (0x10000UL) /*!< MCPEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCNEC_Pos (17UL) /*!< MCNEC (Bit 17) */ + #define R_GPTP_PTPMCCMU0_MCNEC_Msk (0x20000UL) /*!< MCNEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCSWC_Pos (18UL) /*!< MCSWC (Bit 18) */ + #define R_GPTP_PTPMCCMU0_MCSWC_Msk (0x40000UL) /*!< MCSWC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCCN_Pos (24UL) /*!< MCCN (Bit 24) */ + #define R_GPTP_PTPMCCMU0_MCCN_Msk (0x3000000UL) /*!< MCCN (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPMCCMU1 ======================================================= */ + #define R_GPTP_PTPMCCMU1_MCCTVU_Pos (0UL) /*!< MCCTVU (Bit 0) */ + #define R_GPTP_PTPMCCMU1_MCCTVU_Msk (0xffffUL) /*!< MCCTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCCMU1_MCPEC_Pos (16UL) /*!< MCPEC (Bit 16) */ + #define R_GPTP_PTPMCCMU1_MCPEC_Msk (0x10000UL) /*!< MCPEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCNEC_Pos (17UL) /*!< MCNEC (Bit 17) */ + #define R_GPTP_PTPMCCMU1_MCNEC_Msk (0x20000UL) /*!< MCNEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCSWC_Pos (18UL) /*!< MCSWC (Bit 18) */ + #define R_GPTP_PTPMCCMU1_MCSWC_Msk (0x40000UL) /*!< MCSWC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCCN_Pos (24UL) /*!< MCCN (Bit 24) */ + #define R_GPTP_PTPMCCMU1_MCCN_Msk (0x3000000UL) /*!< MCCN (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPMCRC0 ======================================================== */ + #define R_GPTP_PTPMCRC0_MRTTS_Pos (0UL) /*!< MRTTS (Bit 0) */ + #define R_GPTP_PTPMCRC0_MRTTS_Msk (0x1UL) /*!< MRTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRAMS_Pos (1UL) /*!< MRAMS (Bit 1) */ + #define R_GPTP_PTPMCRC0_MRAMS_Msk (0x2UL) /*!< MRAMS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRTNS_Pos (2UL) /*!< MRTNS (Bit 2) */ + #define R_GPTP_PTPMCRC0_MRTNS_Msk (0x4UL) /*!< MRTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRPL_Pos (16UL) /*!< MRPL (Bit 16) */ + #define R_GPTP_PTPMCRC0_MRPL_Msk (0xffff0000UL) /*!< MRPL (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPMCRC1 ======================================================== */ + #define R_GPTP_PTPMCRC1_MRTTS_Pos (0UL) /*!< MRTTS (Bit 0) */ + #define R_GPTP_PTPMCRC1_MRTTS_Msk (0x1UL) /*!< MRTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRAMS_Pos (1UL) /*!< MRAMS (Bit 1) */ + #define R_GPTP_PTPMCRC1_MRAMS_Msk (0x2UL) /*!< MRAMS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRTNS_Pos (2UL) /*!< MRTNS (Bit 2) */ + #define R_GPTP_PTPMCRC1_MRTNS_Msk (0x4UL) /*!< MRTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRPL_Pos (16UL) /*!< MRPL (Bit 16) */ + #define R_GPTP_PTPMCRC1_MRPL_Msk (0xffff0000UL) /*!< MRPL (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPMCRTCL0 ======================================================= */ + #define R_GPTP_PTPMCRTCL0_MRTVL_Pos (0UL) /*!< MRTVL (Bit 0) */ + #define R_GPTP_PTPMCRTCL0_MRTVL_Msk (0xffffffffUL) /*!< MRTVL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCL1 ======================================================= */ + #define R_GPTP_PTPMCRTCL1_MRTVL_Pos (0UL) /*!< MRTVL (Bit 0) */ + #define R_GPTP_PTPMCRTCL1_MRTVL_Msk (0xffffffffUL) /*!< MRTVL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCM0 ======================================================= */ + #define R_GPTP_PTPMCRTCM0_MRTVM_Pos (0UL) /*!< MRTVM (Bit 0) */ + #define R_GPTP_PTPMCRTCM0_MRTVM_Msk (0xffffffffUL) /*!< MRTVM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCM1 ======================================================= */ + #define R_GPTP_PTPMCRTCM1_MRTVM_Pos (0UL) /*!< MRTVM (Bit 0) */ + #define R_GPTP_PTPMCRTCM1_MRTVM_Msk (0xffffffffUL) /*!< MRTVM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCU0 ======================================================= */ + #define R_GPTP_PTPMCRTCU0_MRTVU_Pos (0UL) /*!< MRTVU (Bit 0) */ + #define R_GPTP_PTPMCRTCU0_MRTVU_Msk (0xffffUL) /*!< MRTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCRTCU0_MRTT_Pos (16UL) /*!< MRTT (Bit 16) */ + #define R_GPTP_PTPMCRTCU0_MRTT_Msk (0x30000UL) /*!< MRTT (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPMCRTCU0_MCRN_Pos (18UL) /*!< MCRN (Bit 18) */ + #define R_GPTP_PTPMCRTCU0_MCRN_Msk (0x1c0000UL) /*!< MCRN (Bitfield-Mask: 0x07) */ + #define R_GPTP_PTPMCRTCU0_MRBCR_Pos (31UL) /*!< MRBCR (Bit 31) */ + #define R_GPTP_PTPMCRTCU0_MRBCR_Msk (0x80000000UL) /*!< MRBCR (Bitfield-Mask: 0x01) */ +/* ====================================================== PTPMCRTCU1 ======================================================= */ + #define R_GPTP_PTPMCRTCU1_MRTVU_Pos (0UL) /*!< MRTVU (Bit 0) */ + #define R_GPTP_PTPMCRTCU1_MRTVU_Msk (0xffffUL) /*!< MRTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCRTCU1_MRTT_Pos (16UL) /*!< MRTT (Bit 16) */ + #define R_GPTP_PTPMCRTCU1_MRTT_Msk (0x30000UL) /*!< MRTT (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPMCRTCU1_MCRN_Pos (18UL) /*!< MCRN (Bit 18) */ + #define R_GPTP_PTPMCRTCU1_MCRN_Msk (0x1c0000UL) /*!< MCRN (Bitfield-Mask: 0x07) */ + #define R_GPTP_PTPMCRTCU1_MRBCR_Pos (31UL) /*!< MRBCR (Bit 31) */ + #define R_GPTP_PTPMCRTCU1_MRBCR_Msk (0x80000000UL) /*!< MRBCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCPC0 ======================================================== */ + #define R_GPTP_PTPMCPC0_PE_Pos (0UL) /*!< PE (Bit 0) */ + #define R_GPTP_PTPMCPC0_PE_Msk (0x1UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCPC0_MRS_Pos (1UL) /*!< MRS (Bit 1) */ + #define R_GPTP_PTPMCPC0_MRS_Msk (0x2UL) /*!< MRS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCPC1 ======================================================== */ + #define R_GPTP_PTPMCPC1_PE_Pos (0UL) /*!< PE (Bit 0) */ + #define R_GPTP_PTPMCPC1_PE_Msk (0x1UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCPC1_MRS_Pos (1UL) /*!< MRS (Bit 1) */ + #define R_GPTP_PTPMCPC1_MRS_Msk (0x2UL) /*!< MRS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC00 ======================================================== */ + #define R_GPTP_PTPCCC00_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC00_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC00_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC00_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC01 ======================================================== */ + #define R_GPTP_PTPCCC01_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC01_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC01_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC01_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC02 ======================================================== */ + #define R_GPTP_PTPCCC02_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC02_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC02_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC02_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC03 ======================================================== */ + #define R_GPTP_PTPCCC03_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC03_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC03_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC03_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC04 ======================================================== */ + #define R_GPTP_PTPCCC04_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC04_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC04_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC04_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC05 ======================================================== */ + #define R_GPTP_PTPCCC05_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC05_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC05_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC05_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC06 ======================================================== */ + #define R_GPTP_PTPCCC06_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC06_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC06_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC06_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC07 ======================================================== */ + #define R_GPTP_PTPCCC07_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC07_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC07_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC07_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC10 ======================================================== */ + #define R_GPTP_PTPCCC10_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC10_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC11 ======================================================== */ + #define R_GPTP_PTPCCC11_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC11_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC12 ======================================================== */ + #define R_GPTP_PTPCCC12_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC12_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC13 ======================================================== */ + #define R_GPTP_PTPCCC13_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC13_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC14 ======================================================== */ + #define R_GPTP_PTPCCC14_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC14_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC15 ======================================================== */ + #define R_GPTP_PTPCCC15_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC15_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC16 ======================================================== */ + #define R_GPTP_PTPCCC16_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC16_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC17 ======================================================== */ + #define R_GPTP_PTPCCC17_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC17_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PTPIS0 ========================================================= */ + #define R_GPTP_PTPIS0_MCCS_Pos (0UL) /*!< MCCS (Bit 0) */ + #define R_GPTP_PTPIS0_MCCS_Msk (0x3UL) /*!< MCCS (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPIS0_MCCOES_Pos (16UL) /*!< MCCOES (Bit 16) */ + #define R_GPTP_PTPIS0_MCCOES_Msk (0x30000UL) /*!< MCCOES (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIE0 ========================================================= */ + #define R_GPTP_PTPIE0_MCCE_Pos (0UL) /*!< MCCE (Bit 0) */ + #define R_GPTP_PTPIE0_MCCE_Msk (0x3UL) /*!< MCCE (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPIE0_MCCOEE_Pos (16UL) /*!< MCCOEE (Bit 16) */ + #define R_GPTP_PTPIE0_MCCOEE_Msk (0x30000UL) /*!< MCCOEE (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPID0 ========================================================= */ + #define R_GPTP_PTPID0_MCCD_Pos (0UL) /*!< MCCD (Bit 0) */ + #define R_GPTP_PTPID0_MCCD_Msk (0x3UL) /*!< MCCD (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPID0_MCCOED_Pos (16UL) /*!< MCCOED (Bit 16) */ + #define R_GPTP_PTPID0_MCCOED_Msk (0x30000UL) /*!< MCCOED (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIS1 ========================================================= */ + #define R_GPTP_PTPIS1_MCRMS_Pos (0UL) /*!< MCRMS (Bit 0) */ + #define R_GPTP_PTPIS1_MCRMS_Msk (0x3UL) /*!< MCRMS (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIE1 ========================================================= */ + #define R_GPTP_PTPIE1_MCRME_Pos (0UL) /*!< MCRME (Bit 0) */ + #define R_GPTP_PTPIE1_MCRME_Msk (0x3UL) /*!< MCRME (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPID1 ========================================================= */ + #define R_GPTP_PTPID1_MCRMD_Pos (0UL) /*!< MCRMD (Bit 0) */ + #define R_GPTP_PTPID1_MCRMD_Msk (0x3UL) /*!< MCRMD (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR0 ======================================================== */ + #define R_GPTP_PTPSCR0_TRSL_Pos (0UL) /*!< TRSL (Bit 0) */ + #define R_GPTP_PTPSCR0_TRSL_Msk (0x3UL) /*!< TRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR0_MCRSL_Pos (16UL) /*!< MCRSL (Bit 16) */ + #define R_GPTP_PTPSCR0_MCRSL_Msk (0x30000UL) /*!< MCRSL (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR1 ======================================================== */ + #define R_GPTP_PTPSCR1_MRRSL_Pos (0UL) /*!< MRRSL (Bit 0) */ + #define R_GPTP_PTPSCR1_MRRSL_Msk (0x3UL) /*!< MRRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR1_MRRRSL_Pos (16UL) /*!< MRRRSL (Bit 16) */ + #define R_GPTP_PTPSCR1_MRRRSL_Msk (0x30000UL) /*!< MRRRSL (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR2 ======================================================== */ + #define R_GPTP_PTPSCR2_CCRSL_Pos (0UL) /*!< CCRSL (Bit 0) */ + #define R_GPTP_PTPSCR2_CCRSL_Msk (0x3UL) /*!< CCRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR2_VRSL_Pos (16UL) /*!< VRSL (Bit 16) */ + #define R_GPTP_PTPSCR2_VRSL_Msk (0x10000UL) /*!< VRSL (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCFGR ======================================================== */ + #define R_GPTP_POTCFGR_REFSEL_Pos (0UL) /*!< REFSEL (Bit 0) */ + #define R_GPTP_POTCFGR_REFSEL_Msk (0x1UL) /*!< REFSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR0 ========================================================= */ + #define R_GPTP_POTCR0_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR1 ========================================================= */ + #define R_GPTP_POTCR1_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR2 ========================================================= */ + #define R_GPTP_POTCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR3 ========================================================= */ + #define R_GPTP_POTCR3_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================= POTSTRU0 ======================================================== */ +/* ======================================================= POTSTRU1 ======================================================== */ +/* ======================================================= POTSTRU2 ======================================================== */ +/* ======================================================= POTSTRU3 ======================================================== */ +/* ======================================================= POTSTRM0 ======================================================== */ +/* ======================================================= POTSTRM1 ======================================================== */ +/* ======================================================= POTSTRM2 ======================================================== */ +/* ======================================================= POTSTRM3 ======================================================== */ +/* ======================================================= POTSTRL0 ======================================================== */ +/* ======================================================= POTSTRL1 ======================================================== */ +/* ======================================================= POTSTRL2 ======================================================== */ +/* ======================================================= POTSTRL3 ======================================================== */ +/* ======================================================= POTPERU0 ======================================================== */ +/* ======================================================= POTPERU1 ======================================================== */ +/* ======================================================= POTPERU2 ======================================================== */ +/* ======================================================= POTPERU3 ======================================================== */ +/* ======================================================= POTPERM0 ======================================================== */ +/* ======================================================= POTPERM1 ======================================================== */ +/* ======================================================= POTPERM2 ======================================================== */ +/* ======================================================= POTPERM3 ======================================================== */ +/* ======================================================= POTPERL0 ======================================================== */ +/* ======================================================= POTPERL1 ======================================================== */ +/* ======================================================= POTPERL2 ======================================================== */ +/* ======================================================= POTPERL3 ======================================================== */ +/* ======================================================== POTPWR0 ======================================================== */ +/* ======================================================== POTPWR1 ======================================================== */ +/* ======================================================== POTPWR2 ======================================================== */ +/* ======================================================== POTPWR3 ======================================================== */ +/* ======================================================= POTCPRU0 ======================================================== */ +/* ======================================================= POTCPRU1 ======================================================== */ +/* ======================================================= POTCPRU2 ======================================================== */ +/* ======================================================= POTCPRU3 ======================================================== */ +/* ======================================================= POTCPRM0 ======================================================== */ +/* ======================================================= POTCPRM1 ======================================================== */ +/* ======================================================= POTCPRM2 ======================================================== */ +/* ======================================================= POTCPRM3 ======================================================== */ +/* ======================================================= POTCPRL0 ======================================================== */ +/* ======================================================= POTCPRL1 ======================================================== */ +/* ======================================================= POTCPRL2 ======================================================== */ +/* ======================================================= POTCPRL3 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_GWCA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GWMC ========================================================== */ + #define R_GWCA0_GWMC_OPC_Pos (0UL) /*!< OPC (Bit 0) */ + #define R_GWCA0_GWMC_OPC_Msk (0x3UL) /*!< OPC (Bitfield-Mask: 0x03) */ +/* ========================================================= GWMS ========================================================== */ + #define R_GWCA0_GWMS_OPS_Pos (0UL) /*!< OPS (Bit 0) */ + #define R_GWCA0_GWMS_OPS_Msk (0x3UL) /*!< OPS (Bitfield-Mask: 0x03) */ +/* ========================================================= GWIRC ========================================================= */ + #define R_GWCA0_GWIRC_IPVR0_Pos (0UL) /*!< IPVR0 (Bit 0) */ + #define R_GWCA0_GWIRC_IPVR0_Msk (0x7UL) /*!< IPVR0 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR1_Pos (4UL) /*!< IPVR1 (Bit 4) */ + #define R_GWCA0_GWIRC_IPVR1_Msk (0x70UL) /*!< IPVR1 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR2_Pos (8UL) /*!< IPVR2 (Bit 8) */ + #define R_GWCA0_GWIRC_IPVR2_Msk (0x700UL) /*!< IPVR2 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR3_Pos (12UL) /*!< IPVR3 (Bit 12) */ + #define R_GWCA0_GWIRC_IPVR3_Msk (0x7000UL) /*!< IPVR3 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR4_Pos (16UL) /*!< IPVR4 (Bit 16) */ + #define R_GWCA0_GWIRC_IPVR4_Msk (0x70000UL) /*!< IPVR4 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR5_Pos (20UL) /*!< IPVR5 (Bit 20) */ + #define R_GWCA0_GWIRC_IPVR5_Msk (0x700000UL) /*!< IPVR5 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR6_Pos (24UL) /*!< IPVR6 (Bit 24) */ + #define R_GWCA0_GWIRC_IPVR6_Msk (0x7000000UL) /*!< IPVR6 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR7_Pos (28UL) /*!< IPVR7 (Bit 28) */ + #define R_GWCA0_GWIRC_IPVR7_Msk (0x70000000UL) /*!< IPVR7 (Bitfield-Mask: 0x07) */ +/* ======================================================== GWRDQSC ======================================================== */ + #define R_GWCA0_GWRDQSC_RDQSL0_Pos (0UL) /*!< RDQSL0 (Bit 0) */ + #define R_GWCA0_GWRDQSC_RDQSL0_Msk (0x1UL) /*!< RDQSL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL1_Pos (1UL) /*!< RDQSL1 (Bit 1) */ + #define R_GWCA0_GWRDQSC_RDQSL1_Msk (0x2UL) /*!< RDQSL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL2_Pos (2UL) /*!< RDQSL2 (Bit 2) */ + #define R_GWCA0_GWRDQSC_RDQSL2_Msk (0x4UL) /*!< RDQSL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL3_Pos (3UL) /*!< RDQSL3 (Bit 3) */ + #define R_GWCA0_GWRDQSC_RDQSL3_Msk (0x8UL) /*!< RDQSL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL4_Pos (4UL) /*!< RDQSL4 (Bit 4) */ + #define R_GWCA0_GWRDQSC_RDQSL4_Msk (0x10UL) /*!< RDQSL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL5_Pos (5UL) /*!< RDQSL5 (Bit 5) */ + #define R_GWCA0_GWRDQSC_RDQSL5_Msk (0x20UL) /*!< RDQSL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL6_Pos (6UL) /*!< RDQSL6 (Bit 6) */ + #define R_GWCA0_GWRDQSC_RDQSL6_Msk (0x40UL) /*!< RDQSL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL7_Pos (7UL) /*!< RDQSL7 (Bit 7) */ + #define R_GWCA0_GWRDQSC_RDQSL7_Msk (0x80UL) /*!< RDQSL7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWRDQC ========================================================= */ + #define R_GWCA0_GWRDQC_RDQD0_Pos (0UL) /*!< RDQD0 (Bit 0) */ + #define R_GWCA0_GWRDQC_RDQD0_Msk (0x1UL) /*!< RDQD0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD1_Pos (1UL) /*!< RDQD1 (Bit 1) */ + #define R_GWCA0_GWRDQC_RDQD1_Msk (0x2UL) /*!< RDQD1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD2_Pos (2UL) /*!< RDQD2 (Bit 2) */ + #define R_GWCA0_GWRDQC_RDQD2_Msk (0x4UL) /*!< RDQD2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD3_Pos (3UL) /*!< RDQD3 (Bit 3) */ + #define R_GWCA0_GWRDQC_RDQD3_Msk (0x8UL) /*!< RDQD3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD4_Pos (4UL) /*!< RDQD4 (Bit 4) */ + #define R_GWCA0_GWRDQC_RDQD4_Msk (0x10UL) /*!< RDQD4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD5_Pos (5UL) /*!< RDQD5 (Bit 5) */ + #define R_GWCA0_GWRDQC_RDQD5_Msk (0x20UL) /*!< RDQD5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD6_Pos (6UL) /*!< RDQD6 (Bit 6) */ + #define R_GWCA0_GWRDQC_RDQD6_Msk (0x40UL) /*!< RDQD6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD7_Pos (7UL) /*!< RDQD7 (Bit 7) */ + #define R_GWCA0_GWRDQC_RDQD7_Msk (0x80UL) /*!< RDQD7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP0_Pos (16UL) /*!< RDQP0 (Bit 16) */ + #define R_GWCA0_GWRDQC_RDQP0_Msk (0x10000UL) /*!< RDQP0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP1_Pos (17UL) /*!< RDQP1 (Bit 17) */ + #define R_GWCA0_GWRDQC_RDQP1_Msk (0x20000UL) /*!< RDQP1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP2_Pos (18UL) /*!< RDQP2 (Bit 18) */ + #define R_GWCA0_GWRDQC_RDQP2_Msk (0x40000UL) /*!< RDQP2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP3_Pos (19UL) /*!< RDQP3 (Bit 19) */ + #define R_GWCA0_GWRDQC_RDQP3_Msk (0x80000UL) /*!< RDQP3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP4_Pos (20UL) /*!< RDQP4 (Bit 20) */ + #define R_GWCA0_GWRDQC_RDQP4_Msk (0x100000UL) /*!< RDQP4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP5_Pos (21UL) /*!< RDQP5 (Bit 21) */ + #define R_GWCA0_GWRDQC_RDQP5_Msk (0x200000UL) /*!< RDQP5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP6_Pos (22UL) /*!< RDQP6 (Bit 22) */ + #define R_GWCA0_GWRDQC_RDQP6_Msk (0x400000UL) /*!< RDQP6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP7_Pos (23UL) /*!< RDQP7 (Bit 23) */ + #define R_GWCA0_GWRDQC_RDQP7_Msk (0x800000UL) /*!< RDQP7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWRDQAC ======================================================== */ + #define R_GWCA0_GWRDQAC_RDQA0_Pos (0UL) /*!< RDQA0 (Bit 0) */ + #define R_GWCA0_GWRDQAC_RDQA0_Msk (0xfUL) /*!< RDQA0 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA1_Pos (4UL) /*!< RDQA1 (Bit 4) */ + #define R_GWCA0_GWRDQAC_RDQA1_Msk (0xf0UL) /*!< RDQA1 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA2_Pos (8UL) /*!< RDQA2 (Bit 8) */ + #define R_GWCA0_GWRDQAC_RDQA2_Msk (0xf00UL) /*!< RDQA2 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA3_Pos (12UL) /*!< RDQA3 (Bit 12) */ + #define R_GWCA0_GWRDQAC_RDQA3_Msk (0xf000UL) /*!< RDQA3 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA4_Pos (16UL) /*!< RDQA4 (Bit 16) */ + #define R_GWCA0_GWRDQAC_RDQA4_Msk (0xf0000UL) /*!< RDQA4 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA5_Pos (20UL) /*!< RDQA5 (Bit 20) */ + #define R_GWCA0_GWRDQAC_RDQA5_Msk (0xf00000UL) /*!< RDQA5 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA6_Pos (24UL) /*!< RDQA6 (Bit 24) */ + #define R_GWCA0_GWRDQAC_RDQA6_Msk (0xf000000UL) /*!< RDQA6 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA7_Pos (28UL) /*!< RDQA7 (Bit 28) */ + #define R_GWCA0_GWRDQAC_RDQA7_Msk (0xf0000000UL) /*!< RDQA7 (Bitfield-Mask: 0x0f) */ +/* ========================================================= GWRGC ========================================================= */ + #define R_GWCA0_GWRGC_RCPT_Pos (0UL) /*!< RCPT (Bit 0) */ + #define R_GWCA0_GWRGC_RCPT_Msk (0x1UL) /*!< RCPT (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRMFSC0 ======================================================== */ + #define R_GWCA0_GWRMFSC0_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC0_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC1 ======================================================== */ + #define R_GWCA0_GWRMFSC1_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC1_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC2 ======================================================== */ + #define R_GWCA0_GWRMFSC2_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC2_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC3 ======================================================== */ + #define R_GWCA0_GWRMFSC3_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC3_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC4 ======================================================== */ + #define R_GWCA0_GWRMFSC4_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC4_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC5 ======================================================== */ + #define R_GWCA0_GWRMFSC5_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC5_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC6 ======================================================== */ + #define R_GWCA0_GWRMFSC6_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC6_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC7 ======================================================== */ + #define R_GWCA0_GWRMFSC7_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC7_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRDQDC0 ======================================================== */ + #define R_GWCA0_GWRDQDC0_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC0_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC1 ======================================================== */ + #define R_GWCA0_GWRDQDC1_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC1_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC2 ======================================================== */ + #define R_GWCA0_GWRDQDC2_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC2_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC3 ======================================================== */ + #define R_GWCA0_GWRDQDC3_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC3_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC4 ======================================================== */ + #define R_GWCA0_GWRDQDC4_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC4_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC5 ======================================================== */ + #define R_GWCA0_GWRDQDC5_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC5_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC6 ======================================================== */ + #define R_GWCA0_GWRDQDC6_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC6_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC7 ======================================================== */ + #define R_GWCA0_GWRDQDC7_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC7_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM0 ======================================================== */ + #define R_GWCA0_GWRDQM0_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM0_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM1 ======================================================== */ + #define R_GWCA0_GWRDQM1_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM1_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM2 ======================================================== */ + #define R_GWCA0_GWRDQM2_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM2_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM3 ======================================================== */ + #define R_GWCA0_GWRDQM3_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM3_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM4 ======================================================== */ + #define R_GWCA0_GWRDQM4_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM4_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM5 ======================================================== */ + #define R_GWCA0_GWRDQM5_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM5_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM6 ======================================================== */ + #define R_GWCA0_GWRDQM6_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM6_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM7 ======================================================== */ + #define R_GWCA0_GWRDQM7_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM7_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM0 ======================================================= */ + #define R_GWCA0_GWRDQMLM0_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM0_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM1 ======================================================= */ + #define R_GWCA0_GWRDQMLM1_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM1_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM2 ======================================================= */ + #define R_GWCA0_GWRDQMLM2_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM2_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM3 ======================================================= */ + #define R_GWCA0_GWRDQMLM3_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM3_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM4 ======================================================= */ + #define R_GWCA0_GWRDQMLM4_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM4_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM5 ======================================================= */ + #define R_GWCA0_GWRDQMLM5_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM5_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM6 ======================================================= */ + #define R_GWCA0_GWRDQMLM6_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM6_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM7 ======================================================= */ + #define R_GWCA0_GWRDQMLM7_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM7_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWMTIRM ======================================================== */ + #define R_GWCA0_GWMTIRM_MTIOG_Pos (0UL) /*!< MTIOG (Bit 0) */ + #define R_GWCA0_GWMTIRM_MTIOG_Msk (0x1UL) /*!< MTIOG (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMTIRM_MTR_Pos (1UL) /*!< MTR (Bit 1) */ + #define R_GWCA0_GWMTIRM_MTR_Msk (0x2UL) /*!< MTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMSTLS ======================================================== */ + #define R_GWCA0_GWMSTLS_MNRCNL_Pos (0UL) /*!< MNRCNL (Bit 0) */ + #define R_GWCA0_GWMSTLS_MNRCNL_Msk (0x7fUL) /*!< MNRCNL (Bitfield-Mask: 0x7f) */ + #define R_GWCA0_GWMSTLS_MNL_Pos (8UL) /*!< MNL (Bit 8) */ + #define R_GWCA0_GWMSTLS_MNL_Msk (0x700UL) /*!< MNL (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWMSTLS_MSENL_Pos (16UL) /*!< MSENL (Bit 16) */ + #define R_GWCA0_GWMSTLS_MSENL_Msk (0x7f0000UL) /*!< MSENL (Bitfield-Mask: 0x7f) */ +/* ======================================================== GWMSTLR ======================================================== */ + #define R_GWCA0_GWMSTLR_MTLF_Pos (0UL) /*!< MTLF (Bit 0) */ + #define R_GWCA0_GWMSTLR_MTLF_Msk (0x1UL) /*!< MTLF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMSTLR_MTL_Pos (31UL) /*!< MTL (Bit 31) */ + #define R_GWCA0_GWMSTLR_MTL_Msk (0x80000000UL) /*!< MTL (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMSTSS ======================================================== */ + #define R_GWCA0_GWMSTSS_MSENS_Pos (0UL) /*!< MSENS (Bit 0) */ + #define R_GWCA0_GWMSTSS_MSENS_Msk (0x7fUL) /*!< MSENS (Bitfield-Mask: 0x7f) */ +/* ======================================================== GWMSTSR ======================================================== */ + #define R_GWCA0_GWMSTSR_MNRCNR_Pos (0UL) /*!< MNRCNR (Bit 0) */ + #define R_GWCA0_GWMSTSR_MNRCNR_Msk (0x7fUL) /*!< MNRCNR (Bitfield-Mask: 0x7f) */ + #define R_GWCA0_GWMSTSR_MNR_Pos (8UL) /*!< MNR (Bit 8) */ + #define R_GWCA0_GWMSTSR_MNR_Msk (0x700UL) /*!< MNR (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWMSTSR_MTSEF_Pos (16UL) /*!< MTSEF (Bit 16) */ + #define R_GWCA0_GWMSTSR_MTSEF_Msk (0x10000UL) /*!< MTSEF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMSTSR_MTS_Pos (31UL) /*!< MTS (Bit 31) */ + #define R_GWCA0_GWMSTSR_MTS_Msk (0x80000000UL) /*!< MTS (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMAC0 ========================================================= */ + #define R_GWCA0_GWMAC0_MAUP_Pos (0UL) /*!< MAUP (Bit 0) */ + #define R_GWCA0_GWMAC0_MAUP_Msk (0xffffUL) /*!< MAUP (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWMAC1 ========================================================= */ + #define R_GWCA0_GWMAC1_MADP_Pos (0UL) /*!< MADP (Bit 0) */ + #define R_GWCA0_GWMAC1_MADP_Msk (0xffffffffUL) /*!< MADP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GWVCC ========================================================= */ + #define R_GWCA0_GWVCC_VIM_Pos (0UL) /*!< VIM (Bit 0) */ + #define R_GWCA0_GWVCC_VIM_Msk (0x1UL) /*!< VIM (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVCC_CTVUM_Pos (8UL) /*!< CTVUM (Bit 8) */ + #define R_GWCA0_GWVCC_CTVUM_Msk (0x100UL) /*!< CTVUM (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVCC_VEM_Pos (16UL) /*!< VEM (Bit 16) */ + #define R_GWCA0_GWVCC_VEM_Msk (0x70000UL) /*!< VEM (Bitfield-Mask: 0x07) */ +/* ========================================================= GWVTC ========================================================= */ + #define R_GWCA0_GWVTC_CTV_Pos (0UL) /*!< CTV (Bit 0) */ + #define R_GWCA0_GWVTC_CTV_Msk (0xfffUL) /*!< CTV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWVTC_CTP_Pos (12UL) /*!< CTP (Bit 12) */ + #define R_GWCA0_GWVTC_CTP_Msk (0x7000UL) /*!< CTP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWVTC_CTD_Pos (15UL) /*!< CTD (Bit 15) */ + #define R_GWCA0_GWVTC_CTD_Msk (0x8000UL) /*!< CTD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVTC_STV_Pos (16UL) /*!< STV (Bit 16) */ + #define R_GWCA0_GWVTC_STV_Msk (0xfff0000UL) /*!< STV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWVTC_STP_Pos (28UL) /*!< STP (Bit 28) */ + #define R_GWCA0_GWVTC_STP_Msk (0x70000000UL) /*!< STP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWVTC_STD_Pos (31UL) /*!< STD (Bit 31) */ + #define R_GWCA0_GWVTC_STD_Msk (0x80000000UL) /*!< STD (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTTFC ========================================================= */ + #define R_GWCA0_GWTTFC_NT_Pos (0UL) /*!< NT (Bit 0) */ + #define R_GWCA0_GWTTFC_NT_Msk (0x1UL) /*!< NT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_RT_Pos (1UL) /*!< RT (Bit 1) */ + #define R_GWCA0_GWTTFC_RT_Msk (0x2UL) /*!< RT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CST_Pos (2UL) /*!< CST (Bit 2) */ + #define R_GWCA0_GWTTFC_CST_Msk (0x4UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CSRT_Pos (3UL) /*!< CSRT (Bit 3) */ + #define R_GWCA0_GWTTFC_CSRT_Msk (0x8UL) /*!< CSRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CT_Pos (4UL) /*!< CT (Bit 4) */ + #define R_GWCA0_GWTTFC_CT_Msk (0x10UL) /*!< CT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CRT_Pos (5UL) /*!< CRT (Bit 5) */ + #define R_GWCA0_GWTTFC_CRT_Msk (0x20UL) /*!< CRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_SCT_Pos (6UL) /*!< SCT (Bit 6) */ + #define R_GWCA0_GWTTFC_SCT_Msk (0x40UL) /*!< SCT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_SCRT_Pos (7UL) /*!< SCRT (Bit 7) */ + #define R_GWCA0_GWTTFC_SCRT_Msk (0x80UL) /*!< SCRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_UT_Pos (8UL) /*!< UT (Bit 8) */ + #define R_GWCA0_GWTTFC_UT_Msk (0x100UL) /*!< UT (Bitfield-Mask: 0x01) */ +/* ======================================================= GWTDCAC00 ======================================================= */ + #define R_GWCA0_GWTDCAC00_TSCCAUP_Pos (0UL) /*!< TSCCAUP (Bit 0) */ + #define R_GWCA0_GWTDCAC00_TSCCAUP_Msk (0xffUL) /*!< TSCCAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWTDCAC10 ======================================================= */ + #define R_GWCA0_GWTDCAC10_TSCCADP_Pos (0UL) /*!< TSCCADP (Bit 0) */ + #define R_GWCA0_GWTDCAC10_TSCCADP_Msk (0xffffffffUL) /*!< TSCCADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWTDCAC01 ======================================================= */ + #define R_GWCA0_GWTDCAC01_TSCCAUP_Pos (0UL) /*!< TSCCAUP (Bit 0) */ + #define R_GWCA0_GWTDCAC01_TSCCAUP_Msk (0xffUL) /*!< TSCCAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWTDCAC11 ======================================================= */ + #define R_GWCA0_GWTDCAC11_TSCCADP_Pos (0UL) /*!< TSCCADP (Bit 0) */ + #define R_GWCA0_GWTDCAC11_TSCCADP_Msk (0xffffffffUL) /*!< TSCCADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWTSDCC0 ======================================================== */ + #define R_GWCA0_GWTSDCC0_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GWCA0_GWTSDCC0_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDCC0_DCS_Pos (1UL) /*!< DCS (Bit 1) */ + #define R_GWCA0_GWTSDCC0_DCS_Msk (0x6UL) /*!< DCS (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWTSDCC0_OSID_Pos (8UL) /*!< OSID (Bit 8) */ + #define R_GWCA0_GWTSDCC0_OSID_Msk (0x700UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================= GWTSDCC1 ======================================================== */ + #define R_GWCA0_GWTSDCC1_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GWCA0_GWTSDCC1_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDCC1_DCS_Pos (1UL) /*!< DCS (Bit 1) */ + #define R_GWCA0_GWTSDCC1_DCS_Msk (0x6UL) /*!< DCS (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWTSDCC1_OSID_Pos (8UL) /*!< OSID (Bit 8) */ + #define R_GWCA0_GWTSDCC1_OSID_Msk (0x700UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWTSNM ========================================================= */ + #define R_GWCA0_GWTSNM_TNTR_Pos (0UL) /*!< TNTR (Bit 0) */ + #define R_GWCA0_GWTSNM_TNTR_Msk (0xffUL) /*!< TNTR (Bitfield-Mask: 0xff) */ +/* ======================================================== GWTSMNM ======================================================== */ + #define R_GWCA0_GWTSMNM_TMNTR_Pos (0UL) /*!< TMNTR (Bit 0) */ + #define R_GWCA0_GWTSMNM_TMNTR_Msk (0xffUL) /*!< TMNTR (Bitfield-Mask: 0xff) */ +/* ========================================================= GWAC ========================================================== */ + #define R_GWCA0_GWAC_AMPR_Pos (0UL) /*!< AMPR (Bit 0) */ + #define R_GWCA0_GWAC_AMPR_Msk (0x1UL) /*!< AMPR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAC_AMP_Pos (1UL) /*!< AMP (Bit 1) */ + #define R_GWCA0_GWAC_AMP_Msk (0x2UL) /*!< AMP (Bitfield-Mask: 0x01) */ +/* ======================================================= GWDCBAC0 ======================================================== */ + #define R_GWCA0_GWDCBAC0_DCBAUP_Pos (0UL) /*!< DCBAUP (Bit 0) */ + #define R_GWCA0_GWDCBAC0_DCBAUP_Msk (0xffUL) /*!< DCBAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWDCBAC1 ======================================================== */ + #define R_GWCA0_GWDCBAC1_DCBADP_Pos (0UL) /*!< DCBADP (Bit 0) */ + #define R_GWCA0_GWDCBAC1_DCBADP_Msk (0xffffffffUL) /*!< DCBADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWMDNC ========================================================= */ + #define R_GWCA0_GWMDNC_RXDMN_Pos (0UL) /*!< RXDMN (Bit 0) */ + #define R_GWCA0_GWMDNC_RXDMN_Msk (0x1fUL) /*!< RXDMN (Bitfield-Mask: 0x1f) */ + #define R_GWCA0_GWMDNC_TXDMN_Pos (8UL) /*!< TXDMN (Bit 8) */ + #define R_GWCA0_GWMDNC_TXDMN_Msk (0x1f00UL) /*!< TXDMN (Bitfield-Mask: 0x1f) */ + #define R_GWCA0_GWMDNC_TSDMN_Pos (16UL) /*!< TSDMN (Bit 16) */ + #define R_GWCA0_GWMDNC_TSDMN_Msk (0x30000UL) /*!< TSDMN (Bitfield-Mask: 0x03) */ +/* ======================================================== GWTRC0 ========================================================= */ +/* ======================================================== GWTRC1 ========================================================= */ +/* ======================================================== GWTPC0 ========================================================= */ + #define R_GWCA0_GWTPC0_PPPL0_Pos (0UL) /*!< PPPL0 (Bit 0) */ + #define R_GWCA0_GWTPC0_PPPL0_Msk (0x1UL) /*!< PPPL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL1_Pos (1UL) /*!< PPPL1 (Bit 1) */ + #define R_GWCA0_GWTPC0_PPPL1_Msk (0x2UL) /*!< PPPL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL2_Pos (2UL) /*!< PPPL2 (Bit 2) */ + #define R_GWCA0_GWTPC0_PPPL2_Msk (0x4UL) /*!< PPPL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL3_Pos (3UL) /*!< PPPL3 (Bit 3) */ + #define R_GWCA0_GWTPC0_PPPL3_Msk (0x8UL) /*!< PPPL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL4_Pos (4UL) /*!< PPPL4 (Bit 4) */ + #define R_GWCA0_GWTPC0_PPPL4_Msk (0x10UL) /*!< PPPL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL5_Pos (5UL) /*!< PPPL5 (Bit 5) */ + #define R_GWCA0_GWTPC0_PPPL5_Msk (0x20UL) /*!< PPPL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL6_Pos (6UL) /*!< PPPL6 (Bit 6) */ + #define R_GWCA0_GWTPC0_PPPL6_Msk (0x40UL) /*!< PPPL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL7_Pos (7UL) /*!< PPPL7 (Bit 7) */ + #define R_GWCA0_GWTPC0_PPPL7_Msk (0x80UL) /*!< PPPL7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL8_Pos (8UL) /*!< PPPL8 (Bit 8) */ + #define R_GWCA0_GWTPC0_PPPL8_Msk (0x100UL) /*!< PPPL8 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTPC1 ========================================================= */ + #define R_GWCA0_GWTPC1_PPPL0_Pos (0UL) /*!< PPPL0 (Bit 0) */ + #define R_GWCA0_GWTPC1_PPPL0_Msk (0x1UL) /*!< PPPL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL1_Pos (1UL) /*!< PPPL1 (Bit 1) */ + #define R_GWCA0_GWTPC1_PPPL1_Msk (0x2UL) /*!< PPPL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL2_Pos (2UL) /*!< PPPL2 (Bit 2) */ + #define R_GWCA0_GWTPC1_PPPL2_Msk (0x4UL) /*!< PPPL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL3_Pos (3UL) /*!< PPPL3 (Bit 3) */ + #define R_GWCA0_GWTPC1_PPPL3_Msk (0x8UL) /*!< PPPL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL4_Pos (4UL) /*!< PPPL4 (Bit 4) */ + #define R_GWCA0_GWTPC1_PPPL4_Msk (0x10UL) /*!< PPPL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL5_Pos (5UL) /*!< PPPL5 (Bit 5) */ + #define R_GWCA0_GWTPC1_PPPL5_Msk (0x20UL) /*!< PPPL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL6_Pos (6UL) /*!< PPPL6 (Bit 6) */ + #define R_GWCA0_GWTPC1_PPPL6_Msk (0x40UL) /*!< PPPL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL7_Pos (7UL) /*!< PPPL7 (Bit 7) */ + #define R_GWCA0_GWTPC1_PPPL7_Msk (0x80UL) /*!< PPPL7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL8_Pos (8UL) /*!< PPPL8 (Bit 8) */ + #define R_GWCA0_GWTPC1_PPPL8_Msk (0x100UL) /*!< PPPL8 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWARIRM ======================================================== */ + #define R_GWCA0_GWARIRM_ARIOG_Pos (0UL) /*!< ARIOG (Bit 0) */ + #define R_GWCA0_GWARIRM_ARIOG_Msk (0x1UL) /*!< ARIOG (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWARIRM_ARR_Pos (1UL) /*!< ARR (Bit 1) */ + #define R_GWCA0_GWARIRM_ARR_Msk (0x2UL) /*!< ARR (Bitfield-Mask: 0x01) */ +/* ======================================================== GWDCC0 ========================================================= */ + #define R_GWCA0_GWDCC0_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC0_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC0_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC0_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC0_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC0_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC0_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC0_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC0_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC0_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC0_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC1 ========================================================= */ + #define R_GWCA0_GWDCC1_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC1_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC1_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC1_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC1_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC1_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC1_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC1_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC1_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC1_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC1_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC2 ========================================================= */ + #define R_GWCA0_GWDCC2_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC2_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC2_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC2_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC2_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC2_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC2_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC2_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC2_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC2_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC2_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC3 ========================================================= */ + #define R_GWCA0_GWDCC3_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC3_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC3_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC3_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC3_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC3_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC3_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC3_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC3_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC3_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC3_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC4 ========================================================= */ + #define R_GWCA0_GWDCC4_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC4_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC4_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC4_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC4_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC4_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC4_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC4_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC4_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC4_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC4_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC5 ========================================================= */ + #define R_GWCA0_GWDCC5_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC5_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC5_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC5_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC5_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC5_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC5_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC5_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC5_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC5_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC5_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC6 ========================================================= */ + #define R_GWCA0_GWDCC6_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC6_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC6_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC6_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC6_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC6_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC6_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC6_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC6_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC6_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC6_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC7 ========================================================= */ + #define R_GWCA0_GWDCC7_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC7_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC7_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC7_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC7_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC7_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC7_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC7_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC7_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC7_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC7_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC8 ========================================================= */ + #define R_GWCA0_GWDCC8_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC8_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC8_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC8_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC8_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC8_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC8_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC8_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC8_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC8_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC8_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC9 ========================================================= */ + #define R_GWCA0_GWDCC9_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC9_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC9_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC9_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC9_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC9_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC9_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC9_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC9_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC9_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC9_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC10 ======================================================== */ + #define R_GWCA0_GWDCC10_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC10_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC10_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC10_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC10_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC10_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC10_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC10_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC10_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC10_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC10_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC11 ======================================================== */ + #define R_GWCA0_GWDCC11_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC11_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC11_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC11_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC11_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC11_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC11_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC11_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC11_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC11_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC11_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC12 ======================================================== */ + #define R_GWCA0_GWDCC12_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC12_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC12_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC12_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC12_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC12_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC12_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC12_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC12_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC12_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC12_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC13 ======================================================== */ + #define R_GWCA0_GWDCC13_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC13_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC13_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC13_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC13_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC13_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC13_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC13_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC13_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC13_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC13_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC14 ======================================================== */ + #define R_GWCA0_GWDCC14_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC14_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC14_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC14_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC14_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC14_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC14_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC14_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC14_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC14_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC14_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC15 ======================================================== */ + #define R_GWCA0_GWDCC15_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC15_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC15_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC15_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC15_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC15_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC15_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC15_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC15_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC15_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC15_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC16 ======================================================== */ + #define R_GWCA0_GWDCC16_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC16_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC16_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC16_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC16_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC16_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC16_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC16_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC16_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC16_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC16_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC17 ======================================================== */ + #define R_GWCA0_GWDCC17_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC17_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC17_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC17_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC17_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC17_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC17_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC17_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC17_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC17_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC17_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC18 ======================================================== */ + #define R_GWCA0_GWDCC18_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC18_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC18_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC18_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC18_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC18_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC18_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC18_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC18_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC18_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC18_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC19 ======================================================== */ + #define R_GWCA0_GWDCC19_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC19_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC19_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC19_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC19_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC19_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC19_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC19_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC19_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC19_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC19_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC20 ======================================================== */ + #define R_GWCA0_GWDCC20_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC20_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC20_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC20_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC20_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC20_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC20_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC20_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC20_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC20_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC20_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC21 ======================================================== */ + #define R_GWCA0_GWDCC21_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC21_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC21_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC21_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC21_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC21_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC21_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC21_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC21_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC21_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC21_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC22 ======================================================== */ + #define R_GWCA0_GWDCC22_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC22_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC22_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC22_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC22_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC22_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC22_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC22_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC22_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC22_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC22_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC23 ======================================================== */ + #define R_GWCA0_GWDCC23_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC23_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC23_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC23_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC23_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC23_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC23_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC23_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC23_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC23_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC23_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC24 ======================================================== */ + #define R_GWCA0_GWDCC24_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC24_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC24_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC24_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC24_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC24_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC24_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC24_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC24_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC24_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC24_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC25 ======================================================== */ + #define R_GWCA0_GWDCC25_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC25_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC25_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC25_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC25_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC25_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC25_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC25_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC25_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC25_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC25_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC26 ======================================================== */ + #define R_GWCA0_GWDCC26_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC26_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC26_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC26_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC26_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC26_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC26_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC26_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC26_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC26_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC26_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC27 ======================================================== */ + #define R_GWCA0_GWDCC27_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC27_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC27_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC27_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC27_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC27_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC27_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC27_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC27_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC27_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC27_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC28 ======================================================== */ + #define R_GWCA0_GWDCC28_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC28_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC28_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC28_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC28_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC28_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC28_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC28_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC28_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC28_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC28_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC29 ======================================================== */ + #define R_GWCA0_GWDCC29_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC29_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC29_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC29_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC29_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC29_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC29_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC29_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC29_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC29_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC29_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC30 ======================================================== */ + #define R_GWCA0_GWDCC30_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC30_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC30_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC30_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC30_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC30_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC30_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC30_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC30_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC30_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC30_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC31 ======================================================== */ + #define R_GWCA0_GWDCC31_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC31_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC31_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC31_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC31_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC31_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC31_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC31_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC31_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC31_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC31_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC32 ======================================================== */ + #define R_GWCA0_GWDCC32_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC32_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC32_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC32_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC32_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC32_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC32_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC32_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC32_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC32_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC32_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC33 ======================================================== */ + #define R_GWCA0_GWDCC33_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC33_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC33_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC33_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC33_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC33_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC33_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC33_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC33_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC33_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC33_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC34 ======================================================== */ + #define R_GWCA0_GWDCC34_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC34_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC34_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC34_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC34_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC34_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC34_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC34_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC34_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC34_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC34_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC35 ======================================================== */ + #define R_GWCA0_GWDCC35_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC35_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC35_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC35_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC35_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC35_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC35_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC35_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC35_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC35_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC35_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC36 ======================================================== */ + #define R_GWCA0_GWDCC36_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC36_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC36_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC36_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC36_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC36_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC36_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC36_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC36_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC36_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC36_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC37 ======================================================== */ + #define R_GWCA0_GWDCC37_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC37_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC37_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC37_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC37_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC37_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC37_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC37_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC37_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC37_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC37_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC38 ======================================================== */ + #define R_GWCA0_GWDCC38_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC38_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC38_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC38_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC38_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC38_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC38_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC38_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC38_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC38_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC38_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC39 ======================================================== */ + #define R_GWCA0_GWDCC39_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC39_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC39_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC39_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC39_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC39_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC39_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC39_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC39_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC39_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC39_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC40 ======================================================== */ + #define R_GWCA0_GWDCC40_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC40_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC40_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC40_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC40_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC40_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC40_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC40_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC40_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC40_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC40_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC41 ======================================================== */ + #define R_GWCA0_GWDCC41_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC41_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC41_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC41_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC41_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC41_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC41_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC41_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC41_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC41_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC41_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC42 ======================================================== */ + #define R_GWCA0_GWDCC42_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC42_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC42_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC42_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC42_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC42_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC42_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC42_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC42_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC42_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC42_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC43 ======================================================== */ + #define R_GWCA0_GWDCC43_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC43_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC43_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC43_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC43_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC43_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC43_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC43_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC43_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC43_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC43_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC44 ======================================================== */ + #define R_GWCA0_GWDCC44_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC44_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC44_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC44_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC44_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC44_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC44_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC44_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC44_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC44_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC44_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC45 ======================================================== */ + #define R_GWCA0_GWDCC45_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC45_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC45_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC45_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC45_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC45_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC45_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC45_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC45_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC45_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC45_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC46 ======================================================== */ + #define R_GWCA0_GWDCC46_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC46_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC46_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC46_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC46_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC46_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC46_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC46_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC46_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC46_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC46_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC47 ======================================================== */ + #define R_GWCA0_GWDCC47_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC47_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC47_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC47_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC47_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC47_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC47_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC47_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC47_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC47_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC47_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC48 ======================================================== */ + #define R_GWCA0_GWDCC48_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC48_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC48_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC48_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC48_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC48_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC48_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC48_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC48_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC48_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC48_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC49 ======================================================== */ + #define R_GWCA0_GWDCC49_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC49_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC49_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC49_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC49_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC49_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC49_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC49_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC49_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC49_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC49_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC50 ======================================================== */ + #define R_GWCA0_GWDCC50_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC50_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC50_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC50_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC50_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC50_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC50_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC50_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC50_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC50_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC50_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC51 ======================================================== */ + #define R_GWCA0_GWDCC51_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC51_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC51_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC51_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC51_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC51_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC51_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC51_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC51_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC51_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC51_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC52 ======================================================== */ + #define R_GWCA0_GWDCC52_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC52_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC52_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC52_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC52_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC52_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC52_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC52_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC52_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC52_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC52_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC53 ======================================================== */ + #define R_GWCA0_GWDCC53_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC53_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC53_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC53_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC53_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC53_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC53_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC53_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC53_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC53_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC53_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC54 ======================================================== */ + #define R_GWCA0_GWDCC54_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC54_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC54_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC54_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC54_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC54_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC54_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC54_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC54_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC54_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC54_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC55 ======================================================== */ + #define R_GWCA0_GWDCC55_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC55_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC55_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC55_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC55_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC55_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC55_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC55_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC55_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC55_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC55_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC56 ======================================================== */ + #define R_GWCA0_GWDCC56_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC56_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC56_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC56_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC56_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC56_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC56_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC56_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC56_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC56_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC56_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC57 ======================================================== */ + #define R_GWCA0_GWDCC57_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC57_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC57_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC57_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC57_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC57_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC57_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC57_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC57_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC57_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC57_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC58 ======================================================== */ + #define R_GWCA0_GWDCC58_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC58_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC58_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC58_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC58_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC58_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC58_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC58_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC58_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC58_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC58_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC59 ======================================================== */ + #define R_GWCA0_GWDCC59_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC59_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC59_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC59_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC59_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC59_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC59_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC59_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC59_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC59_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC59_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC60 ======================================================== */ + #define R_GWCA0_GWDCC60_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC60_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC60_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC60_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC60_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC60_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC60_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC60_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC60_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC60_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC60_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC61 ======================================================== */ + #define R_GWCA0_GWDCC61_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC61_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC61_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC61_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC61_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC61_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC61_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC61_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC61_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC61_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC61_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC62 ======================================================== */ + #define R_GWCA0_GWDCC62_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC62_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC62_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC62_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC62_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC62_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC62_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC62_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC62_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC62_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC62_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC63 ======================================================== */ + #define R_GWCA0_GWDCC63_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC63_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC63_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC63_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC63_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC63_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC63_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC63_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC63_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC63_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC63_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWAARSS ======================================================== */ + #define R_GWCA0_GWAARSS_AARA_Pos (0UL) /*!< AARA (Bit 0) */ + #define R_GWCA0_GWAARSS_AARA_Msk (0x7fUL) /*!< AARA (Bitfield-Mask: 0x7f) */ +/* ======================================================= GWAARSR0 ======================================================== */ + #define R_GWCA0_GWAARSR0_ACARU_Pos (0UL) /*!< ACARU (Bit 0) */ + #define R_GWCA0_GWAARSR0_ACARU_Msk (0xffUL) /*!< ACARU (Bitfield-Mask: 0xff) */ + #define R_GWCA0_GWAARSR0_AARSEF_Pos (16UL) /*!< AARSEF (Bit 16) */ + #define R_GWCA0_GWAARSR0_AARSEF_Msk (0x10000UL) /*!< AARSEF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAARSR0_AARSSF_Pos (17UL) /*!< AARSSF (Bit 17) */ + #define R_GWCA0_GWAARSR0_AARSSF_Msk (0x20000UL) /*!< AARSSF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAARSR0_AARS_Pos (31UL) /*!< AARS (Bit 31) */ + #define R_GWCA0_GWAARSR0_AARS_Msk (0x80000000UL) /*!< AARS (Bitfield-Mask: 0x01) */ +/* ======================================================= GWAARSR1 ======================================================== */ + #define R_GWCA0_GWAARSR1_ACARD_Pos (0UL) /*!< ACARD (Bit 0) */ + #define R_GWCA0_GWAARSR1_ACARD_Msk (0xffffffffUL) /*!< ACARD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWIDAUAS0 ======================================================= */ + #define R_GWCA0_GWIDAUAS0_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS0_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS1 ======================================================= */ + #define R_GWCA0_GWIDAUAS1_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS1_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS2 ======================================================= */ + #define R_GWCA0_GWIDAUAS2_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS2_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS3 ======================================================= */ + #define R_GWCA0_GWIDAUAS3_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS3_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM0 ======================================================== */ + #define R_GWCA0_GWIDASM0_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM0_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM1 ======================================================== */ + #define R_GWCA0_GWIDASM1_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM1_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM2 ======================================================== */ + #define R_GWCA0_GWIDASM2_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM2_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM3 ======================================================== */ + #define R_GWCA0_GWIDASM3_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM3_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ====================================================== GWIDASAM00 ======================================================= */ + #define R_GWCA0_GWIDASAM00_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM00_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM10 ======================================================= */ + #define R_GWCA0_GWIDASAM10_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM10_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM01 ======================================================= */ + #define R_GWCA0_GWIDASAM01_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM01_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM11 ======================================================= */ + #define R_GWCA0_GWIDASAM11_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM11_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM02 ======================================================= */ + #define R_GWCA0_GWIDASAM02_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM02_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM12 ======================================================= */ + #define R_GWCA0_GWIDASAM12_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM12_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM03 ======================================================= */ + #define R_GWCA0_GWIDASAM03_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM03_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM13 ======================================================= */ + #define R_GWCA0_GWIDASAM13_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM13_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM00 ======================================================= */ + #define R_GWCA0_GWIDACAM00_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM00_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM10 ======================================================= */ + #define R_GWCA0_GWIDACAM10_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM10_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM01 ======================================================= */ + #define R_GWCA0_GWIDACAM01_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM01_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM11 ======================================================= */ + #define R_GWCA0_GWIDACAM11_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM11_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM02 ======================================================= */ + #define R_GWCA0_GWIDACAM02_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM02_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM12 ======================================================= */ + #define R_GWCA0_GWIDACAM12_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM12_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM03 ======================================================= */ + #define R_GWCA0_GWIDACAM03_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM03_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM13 ======================================================= */ + #define R_GWCA0_GWIDACAM13_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM13_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWGRLC ========================================================= */ + #define R_GWCA0_GWGRLC_GRLIV_Pos (0UL) /*!< GRLIV (Bit 0) */ + #define R_GWCA0_GWGRLC_GRLIV_Msk (0xffffUL) /*!< GRLIV (Bitfield-Mask: 0xffff) */ + #define R_GWCA0_GWGRLC_GRLE_Pos (16UL) /*!< GRLE (Bit 16) */ + #define R_GWCA0_GWGRLC_GRLE_Msk (0x10000UL) /*!< GRLE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWGRLC_GRLULRS_Pos (17UL) /*!< GRLULRS (Bit 17) */ + #define R_GWCA0_GWGRLC_GRLULRS_Msk (0x20000UL) /*!< GRLULRS (Bitfield-Mask: 0x01) */ +/* ======================================================= GWGRLULC ======================================================== */ + #define R_GWCA0_GWGRLULC_GRLUL_Pos (0UL) /*!< GRLUL (Bit 0) */ + #define R_GWCA0_GWGRLULC_GRLUL_Msk (0xffffffUL) /*!< GRLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC0 ========================================================= */ + #define R_GWCA0_GWRLC0_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC0_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC0_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC0_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC0 ======================================================== */ + #define R_GWCA0_GWRLULC0_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC0_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC1 ========================================================= */ + #define R_GWCA0_GWRLC1_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC1_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC1_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC1_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC1 ======================================================== */ + #define R_GWCA0_GWRLULC1_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC1_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC2 ========================================================= */ + #define R_GWCA0_GWRLC2_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC2_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC2_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC2_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC2 ======================================================== */ + #define R_GWCA0_GWRLULC2_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC2_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC3 ========================================================= */ + #define R_GWCA0_GWRLC3_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC3_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC3_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC3_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC3 ======================================================== */ + #define R_GWCA0_GWRLULC3_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC3_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC4 ========================================================= */ + #define R_GWCA0_GWRLC4_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC4_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC4_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC4_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC4 ======================================================== */ + #define R_GWCA0_GWRLULC4_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC4_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC5 ========================================================= */ + #define R_GWCA0_GWRLC5_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC5_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC5_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC5_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC5 ======================================================== */ + #define R_GWCA0_GWRLULC5_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC5_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC6 ========================================================= */ + #define R_GWCA0_GWRLC6_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC6_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC6_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC6_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC6 ======================================================== */ + #define R_GWCA0_GWRLULC6_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC6_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC7 ========================================================= */ + #define R_GWCA0_GWRLC7_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC7_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC7_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC7_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC7 ======================================================== */ + #define R_GWCA0_GWRLULC7_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC7_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWIDPC ========================================================= */ + #define R_GWCA0_GWIDPC_IDPV_Pos (0UL) /*!< IDPV (Bit 0) */ + #define R_GWCA0_GWIDPC_IDPV_Msk (0x3ffUL) /*!< IDPV (Bitfield-Mask: 0x3ff) */ +/* ======================================================== GWIDC0 ========================================================= */ + #define R_GWCA0_GWIDC0_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC0_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC1 ========================================================= */ + #define R_GWCA0_GWIDC1_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC1_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC2 ========================================================= */ + #define R_GWCA0_GWIDC2_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC2_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC3 ========================================================= */ + #define R_GWCA0_GWIDC3_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC3_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC4 ========================================================= */ + #define R_GWCA0_GWIDC4_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC4_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC5 ========================================================= */ + #define R_GWCA0_GWIDC5_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC5_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC6 ========================================================= */ + #define R_GWCA0_GWIDC6_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC6_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC7 ========================================================= */ + #define R_GWCA0_GWIDC7_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC7_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC8 ========================================================= */ + #define R_GWCA0_GWIDC8_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC8_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC9 ========================================================= */ + #define R_GWCA0_GWIDC9_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC9_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC10 ======================================================== */ + #define R_GWCA0_GWIDC10_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC10_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC11 ======================================================== */ + #define R_GWCA0_GWIDC11_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC11_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC12 ======================================================== */ + #define R_GWCA0_GWIDC12_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC12_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC13 ======================================================== */ + #define R_GWCA0_GWIDC13_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC13_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC14 ======================================================== */ + #define R_GWCA0_GWIDC14_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC14_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC15 ======================================================== */ + #define R_GWCA0_GWIDC15_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC15_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC16 ======================================================== */ + #define R_GWCA0_GWIDC16_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC16_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC17 ======================================================== */ + #define R_GWCA0_GWIDC17_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC17_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC18 ======================================================== */ + #define R_GWCA0_GWIDC18_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC18_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC19 ======================================================== */ + #define R_GWCA0_GWIDC19_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC19_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC20 ======================================================== */ + #define R_GWCA0_GWIDC20_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC20_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC21 ======================================================== */ + #define R_GWCA0_GWIDC21_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC21_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC22 ======================================================== */ + #define R_GWCA0_GWIDC22_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC22_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC23 ======================================================== */ + #define R_GWCA0_GWIDC23_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC23_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC24 ======================================================== */ + #define R_GWCA0_GWIDC24_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC24_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC25 ======================================================== */ + #define R_GWCA0_GWIDC25_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC25_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC26 ======================================================== */ + #define R_GWCA0_GWIDC26_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC26_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC27 ======================================================== */ + #define R_GWCA0_GWIDC27_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC27_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC28 ======================================================== */ + #define R_GWCA0_GWIDC28_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC28_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC29 ======================================================== */ + #define R_GWCA0_GWIDC29_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC29_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC30 ======================================================== */ + #define R_GWCA0_GWIDC30_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC30_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC31 ======================================================== */ + #define R_GWCA0_GWIDC31_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC31_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC32 ======================================================== */ + #define R_GWCA0_GWIDC32_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC32_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC33 ======================================================== */ + #define R_GWCA0_GWIDC33_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC33_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC34 ======================================================== */ + #define R_GWCA0_GWIDC34_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC34_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC35 ======================================================== */ + #define R_GWCA0_GWIDC35_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC35_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC36 ======================================================== */ + #define R_GWCA0_GWIDC36_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC36_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC37 ======================================================== */ + #define R_GWCA0_GWIDC37_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC37_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC38 ======================================================== */ + #define R_GWCA0_GWIDC38_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC38_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC39 ======================================================== */ + #define R_GWCA0_GWIDC39_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC39_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC40 ======================================================== */ + #define R_GWCA0_GWIDC40_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC40_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC41 ======================================================== */ + #define R_GWCA0_GWIDC41_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC41_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC42 ======================================================== */ + #define R_GWCA0_GWIDC42_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC42_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC43 ======================================================== */ + #define R_GWCA0_GWIDC43_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC43_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC44 ======================================================== */ + #define R_GWCA0_GWIDC44_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC44_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC45 ======================================================== */ + #define R_GWCA0_GWIDC45_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC45_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC46 ======================================================== */ + #define R_GWCA0_GWIDC46_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC46_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC47 ======================================================== */ + #define R_GWCA0_GWIDC47_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC47_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC48 ======================================================== */ + #define R_GWCA0_GWIDC48_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC48_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC49 ======================================================== */ + #define R_GWCA0_GWIDC49_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC49_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC50 ======================================================== */ + #define R_GWCA0_GWIDC50_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC50_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC51 ======================================================== */ + #define R_GWCA0_GWIDC51_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC51_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC52 ======================================================== */ + #define R_GWCA0_GWIDC52_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC52_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC53 ======================================================== */ + #define R_GWCA0_GWIDC53_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC53_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC54 ======================================================== */ + #define R_GWCA0_GWIDC54_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC54_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC55 ======================================================== */ + #define R_GWCA0_GWIDC55_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC55_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC56 ======================================================== */ + #define R_GWCA0_GWIDC56_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC56_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC57 ======================================================== */ + #define R_GWCA0_GWIDC57_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC57_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC58 ======================================================== */ + #define R_GWCA0_GWIDC58_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC58_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC59 ======================================================== */ + #define R_GWCA0_GWIDC59_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC59_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC60 ======================================================== */ + #define R_GWCA0_GWIDC60_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC60_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC61 ======================================================== */ + #define R_GWCA0_GWIDC61_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC61_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC62 ======================================================== */ + #define R_GWCA0_GWIDC62_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC62_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC63 ======================================================== */ + #define R_GWCA0_GWIDC63_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC63_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC64 ======================================================== */ + #define R_GWCA0_GWIDC64_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC64_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWRDCN ========================================================= */ + #define R_GWCA0_GWRDCN_RDN_Pos (0UL) /*!< RDN (Bit 0) */ + #define R_GWCA0_GWRDCN_RDN_Msk (0xffffffffUL) /*!< RDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWTDCN ========================================================= */ + #define R_GWCA0_GWTDCN_TDN_Pos (0UL) /*!< TDN (Bit 0) */ + #define R_GWCA0_GWTDCN_TDN_Msk (0xffffffffUL) /*!< TDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWTSCN ========================================================= */ + #define R_GWCA0_GWTSCN_TN_Pos (0UL) /*!< TN (Bit 0) */ + #define R_GWCA0_GWTSCN_TN_Msk (0xffffffffUL) /*!< TN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWTSOVFECN ======================================================= */ + #define R_GWCA0_GWTSOVFECN_TSOVFEN_Pos (0UL) /*!< TSOVFEN (Bit 0) */ + #define R_GWCA0_GWTSOVFECN_TSOVFEN_Msk (0xffffUL) /*!< TSOVFEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== GWUSMFSECN ======================================================= */ + #define R_GWCA0_GWUSMFSECN_USMFSEN_Pos (0UL) /*!< USMFSEN (Bit 0) */ + #define R_GWCA0_GWUSMFSECN_USMFSEN_Msk (0xffffUL) /*!< USMFSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWTFECN ======================================================== */ + #define R_GWCA0_GWTFECN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ + #define R_GWCA0_GWTFECN_TFEN_Msk (0xffffUL) /*!< TFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWSEQECN ======================================================== */ + #define R_GWCA0_GWSEQECN_SEQEN_Pos (0UL) /*!< SEQEN (Bit 0) */ + #define R_GWCA0_GWSEQECN_SEQEN_Msk (0xffffUL) /*!< SEQEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTXDNECN ======================================================= */ + #define R_GWCA0_GWTXDNECN_TXDNEN_Pos (0UL) /*!< TXDNEN (Bit 0) */ + #define R_GWCA0_GWTXDNECN_TXDNEN_Msk (0xffffUL) /*!< TXDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWFSECN ======================================================== */ + #define R_GWCA0_GWFSECN_FSEN_Pos (0UL) /*!< FSEN (Bit 0) */ + #define R_GWCA0_GWFSECN_FSEN_Msk (0xffffUL) /*!< FSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTDFECN ======================================================== */ + #define R_GWCA0_GWTDFECN_TDFEN_Pos (0UL) /*!< TDFEN (Bit 0) */ + #define R_GWCA0_GWTDFECN_TDFEN_Msk (0xffffUL) /*!< TDFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTSDNECN ======================================================= */ + #define R_GWCA0_GWTSDNECN_TSDNEN_Pos (0UL) /*!< TSDNEN (Bit 0) */ + #define R_GWCA0_GWTSDNECN_TSDNEN_Msk (0xffffUL) /*!< TSDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDQOECN ======================================================== */ + #define R_GWCA0_GWDQOECN_DQOEN_Pos (0UL) /*!< DQOEN (Bit 0) */ + #define R_GWCA0_GWDQOECN_DQOEN_Msk (0xffffUL) /*!< DQOEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDQSECN ======================================================== */ + #define R_GWCA0_GWDQSECN_DQSEN_Pos (0UL) /*!< DQSEN (Bit 0) */ + #define R_GWCA0_GWDQSECN_DQSEN_Msk (0xffffUL) /*!< DQSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDFECN ======================================================== */ + #define R_GWCA0_GWDFECN_DFEN_Pos (0UL) /*!< DFEN (Bit 0) */ + #define R_GWCA0_GWDFECN_DFEN_Msk (0xffffUL) /*!< DFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDSECN ======================================================== */ + #define R_GWCA0_GWDSECN_DSEN_Pos (0UL) /*!< DSEN (Bit 0) */ + #define R_GWCA0_GWDSECN_DSEN_Msk (0xffffUL) /*!< DSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDSZECN ======================================================== */ + #define R_GWCA0_GWDSZECN_DSZEN_Pos (0UL) /*!< DSZEN (Bit 0) */ + #define R_GWCA0_GWDSZECN_DSZEN_Msk (0xffffUL) /*!< DSZEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDCTECN ======================================================== */ + #define R_GWCA0_GWDCTECN_DCTEN_Pos (0UL) /*!< DCTEN (Bit 0) */ + #define R_GWCA0_GWDCTECN_DCTEN_Msk (0xffffUL) /*!< DCTEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRXDNECN ======================================================= */ + #define R_GWCA0_GWRXDNECN_RXDNEN_Pos (0UL) /*!< RXDNEN (Bit 0) */ + #define R_GWCA0_GWRXDNECN_RXDNEN_Msk (0xffffUL) /*!< RXDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDIS0 ========================================================= */ +/* ======================================================== GWDIE0 ========================================================= */ +/* ======================================================== GWDID0 ========================================================= */ +/* ======================================================== GWDIDS0 ======================================================== */ +/* ======================================================== GWDIS1 ========================================================= */ +/* ======================================================== GWDIE1 ========================================================= */ +/* ======================================================== GWDID1 ========================================================= */ +/* ======================================================== GWDIDS1 ======================================================== */ +/* ======================================================== GWTSDIS ======================================================== */ + #define R_GWCA0_GWTSDIS_TSDIS0_Pos (0UL) /*!< TSDIS0 (Bit 0) */ + #define R_GWCA0_GWTSDIS_TSDIS0_Msk (0x1UL) /*!< TSDIS0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDIS_TSDIS1_Pos (1UL) /*!< TSDIS1 (Bit 1) */ + #define R_GWCA0_GWTSDIS_TSDIS1_Msk (0x2UL) /*!< TSDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTSDIE ======================================================== */ + #define R_GWCA0_GWTSDIE_TSDIE0_Pos (0UL) /*!< TSDIE0 (Bit 0) */ + #define R_GWCA0_GWTSDIE_TSDIE0_Msk (0x1UL) /*!< TSDIE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDIE_TSDIE1_Pos (1UL) /*!< TSDIE1 (Bit 1) */ + #define R_GWCA0_GWTSDIE_TSDIE1_Msk (0x2UL) /*!< TSDIE1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTSDID ======================================================== */ + #define R_GWCA0_GWTSDID_TSDID0_Pos (0UL) /*!< TSDID0 (Bit 0) */ + #define R_GWCA0_GWTSDID_TSDID0_Msk (0x1UL) /*!< TSDID0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDID_TSDID1_Pos (1UL) /*!< TSDID1 (Bit 1) */ + #define R_GWCA0_GWTSDID_TSDID1_Msk (0x2UL) /*!< TSDID1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS0 ========================================================= */ + #define R_GWCA0_GWEIS0_AES_Pos (0UL) /*!< AES (Bit 0) */ + #define R_GWCA0_GWEIS0_AES_Msk (0x1UL) /*!< AES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_DECCES_Pos (1UL) /*!< DECCES (Bit 1) */ + #define R_GWCA0_GWEIS0_DECCES_Msk (0x2UL) /*!< DECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TECCES_Pos (2UL) /*!< TECCES (Bit 2) */ + #define R_GWCA0_GWEIS0_TECCES_Msk (0x4UL) /*!< TECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_PECCES_Pos (3UL) /*!< PECCES (Bit 3) */ + #define R_GWCA0_GWEIS0_PECCES_Msk (0x8UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_DSECCES_Pos (4UL) /*!< DSECCES (Bit 4) */ + #define R_GWCA0_GWEIS0_DSECCES_Msk (0x10UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_MECCES_Pos (5UL) /*!< MECCES (Bit 5) */ + #define R_GWCA0_GWEIS0_MECCES_Msk (0x20UL) /*!< MECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_AECCES_Pos (6UL) /*!< AECCES (Bit 6) */ + #define R_GWCA0_GWEIS0_AECCES_Msk (0x40UL) /*!< AECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSECCES_Pos (7UL) /*!< TSECCES (Bit 7) */ + #define R_GWCA0_GWEIS0_TSECCES_Msk (0x80UL) /*!< TSECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_L23UECCES_Pos (8UL) /*!< L23UECCES (Bit 8) */ + #define R_GWCA0_GWEIS0_L23UECCES_Msk (0x100UL) /*!< L23UECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSOVFES_Pos (9UL) /*!< TSOVFES (Bit 9) */ + #define R_GWCA0_GWEIS0_TSOVFES_Msk (0x200UL) /*!< TSOVFES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_USMFSES_Pos (10UL) /*!< USMFSES (Bit 10) */ + #define R_GWCA0_GWEIS0_USMFSES_Msk (0x400UL) /*!< USMFSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TFES_Pos (11UL) /*!< TFES (Bit 11) */ + #define R_GWCA0_GWEIS0_TFES_Msk (0x800UL) /*!< TFES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_SEQES_Pos (12UL) /*!< SEQES (Bit 12) */ + #define R_GWCA0_GWEIS0_SEQES_Msk (0x1000UL) /*!< SEQES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TXDNES_Pos (14UL) /*!< TXDNES (Bit 14) */ + #define R_GWCA0_GWEIS0_TXDNES_Msk (0x4000UL) /*!< TXDNES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSHES_Pos (15UL) /*!< TSHES (Bit 15) */ + #define R_GWCA0_GWEIS0_TSHES_Msk (0x8000UL) /*!< TSHES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES0_Pos (16UL) /*!< FSES0 (Bit 16) */ + #define R_GWCA0_GWEIS0_FSES0_Msk (0x10000UL) /*!< FSES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES1_Pos (17UL) /*!< FSES1 (Bit 17) */ + #define R_GWCA0_GWEIS0_FSES1_Msk (0x20000UL) /*!< FSES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES2_Pos (18UL) /*!< FSES2 (Bit 18) */ + #define R_GWCA0_GWEIS0_FSES2_Msk (0x40000UL) /*!< FSES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES3_Pos (19UL) /*!< FSES3 (Bit 19) */ + #define R_GWCA0_GWEIS0_FSES3_Msk (0x80000UL) /*!< FSES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES4_Pos (20UL) /*!< FSES4 (Bit 20) */ + #define R_GWCA0_GWEIS0_FSES4_Msk (0x100000UL) /*!< FSES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES5_Pos (21UL) /*!< FSES5 (Bit 21) */ + #define R_GWCA0_GWEIS0_FSES5_Msk (0x200000UL) /*!< FSES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES6_Pos (22UL) /*!< FSES6 (Bit 22) */ + #define R_GWCA0_GWEIS0_FSES6_Msk (0x400000UL) /*!< FSES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES7_Pos (23UL) /*!< FSES7 (Bit 23) */ + #define R_GWCA0_GWEIS0_FSES7_Msk (0x800000UL) /*!< FSES7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TDFES0_Pos (24UL) /*!< TDFES0 (Bit 24) */ + #define R_GWCA0_GWEIS0_TDFES0_Msk (0x1000000UL) /*!< TDFES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TDFES1_Pos (25UL) /*!< TDFES1 (Bit 25) */ + #define R_GWCA0_GWEIS0_TDFES1_Msk (0x2000000UL) /*!< TDFES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSDNES0_Pos (28UL) /*!< TSDNES0 (Bit 28) */ + #define R_GWCA0_GWEIS0_TSDNES0_Msk (0x10000000UL) /*!< TSDNES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSDNES1_Pos (29UL) /*!< TSDNES1 (Bit 29) */ + #define R_GWCA0_GWEIS0_TSDNES1_Msk (0x20000000UL) /*!< TSDNES1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE0 ========================================================= */ + #define R_GWCA0_GWEIE0_AEE_Pos (0UL) /*!< AEE (Bit 0) */ + #define R_GWCA0_GWEIE0_AEE_Msk (0x1UL) /*!< AEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_DECCEE_Pos (1UL) /*!< DECCEE (Bit 1) */ + #define R_GWCA0_GWEIE0_DECCEE_Msk (0x2UL) /*!< DECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TECCEE_Pos (2UL) /*!< TECCEE (Bit 2) */ + #define R_GWCA0_GWEIE0_TECCEE_Msk (0x4UL) /*!< TECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_PECCEE_Pos (3UL) /*!< PECCEE (Bit 3) */ + #define R_GWCA0_GWEIE0_PECCEE_Msk (0x8UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_DSECCEE_Pos (4UL) /*!< DSECCEE (Bit 4) */ + #define R_GWCA0_GWEIE0_DSECCEE_Msk (0x10UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_MECCEE_Pos (5UL) /*!< MECCEE (Bit 5) */ + #define R_GWCA0_GWEIE0_MECCEE_Msk (0x20UL) /*!< MECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_AECCEE_Pos (6UL) /*!< AECCEE (Bit 6) */ + #define R_GWCA0_GWEIE0_AECCEE_Msk (0x40UL) /*!< AECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSECCEE_Pos (7UL) /*!< TSECCEE (Bit 7) */ + #define R_GWCA0_GWEIE0_TSECCEE_Msk (0x80UL) /*!< TSECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_L23UECCEE_Pos (8UL) /*!< L23UECCEE (Bit 8) */ + #define R_GWCA0_GWEIE0_L23UECCEE_Msk (0x100UL) /*!< L23UECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSOVFEE_Pos (9UL) /*!< TSOVFEE (Bit 9) */ + #define R_GWCA0_GWEIE0_TSOVFEE_Msk (0x200UL) /*!< TSOVFEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_USMFSEE_Pos (10UL) /*!< USMFSEE (Bit 10) */ + #define R_GWCA0_GWEIE0_USMFSEE_Msk (0x400UL) /*!< USMFSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TFEE_Pos (11UL) /*!< TFEE (Bit 11) */ + #define R_GWCA0_GWEIE0_TFEE_Msk (0x800UL) /*!< TFEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_SEQEE_Pos (12UL) /*!< SEQEE (Bit 12) */ + #define R_GWCA0_GWEIE0_SEQEE_Msk (0x1000UL) /*!< SEQEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TXDNEE_Pos (14UL) /*!< TXDNEE (Bit 14) */ + #define R_GWCA0_GWEIE0_TXDNEE_Msk (0x4000UL) /*!< TXDNEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSHEE_Pos (15UL) /*!< TSHEE (Bit 15) */ + #define R_GWCA0_GWEIE0_TSHEE_Msk (0x8000UL) /*!< TSHEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE0_Pos (16UL) /*!< FSEE0 (Bit 16) */ + #define R_GWCA0_GWEIE0_FSEE0_Msk (0x10000UL) /*!< FSEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE1_Pos (17UL) /*!< FSEE1 (Bit 17) */ + #define R_GWCA0_GWEIE0_FSEE1_Msk (0x20000UL) /*!< FSEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE2_Pos (18UL) /*!< FSEE2 (Bit 18) */ + #define R_GWCA0_GWEIE0_FSEE2_Msk (0x40000UL) /*!< FSEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE3_Pos (19UL) /*!< FSEE3 (Bit 19) */ + #define R_GWCA0_GWEIE0_FSEE3_Msk (0x80000UL) /*!< FSEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE4_Pos (20UL) /*!< FSEE4 (Bit 20) */ + #define R_GWCA0_GWEIE0_FSEE4_Msk (0x100000UL) /*!< FSEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE5_Pos (21UL) /*!< FSEE5 (Bit 21) */ + #define R_GWCA0_GWEIE0_FSEE5_Msk (0x200000UL) /*!< FSEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE6_Pos (22UL) /*!< FSEE6 (Bit 22) */ + #define R_GWCA0_GWEIE0_FSEE6_Msk (0x400000UL) /*!< FSEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE7_Pos (23UL) /*!< FSEE7 (Bit 23) */ + #define R_GWCA0_GWEIE0_FSEE7_Msk (0x800000UL) /*!< FSEE7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TDFEE0_Pos (24UL) /*!< TDFEE0 (Bit 24) */ + #define R_GWCA0_GWEIE0_TDFEE0_Msk (0x1000000UL) /*!< TDFEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TDFEE1_Pos (25UL) /*!< TDFEE1 (Bit 25) */ + #define R_GWCA0_GWEIE0_TDFEE1_Msk (0x2000000UL) /*!< TDFEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSDNEE0_Pos (28UL) /*!< TSDNEE0 (Bit 28) */ + #define R_GWCA0_GWEIE0_TSDNEE0_Msk (0x10000000UL) /*!< TSDNEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSDNEE1_Pos (29UL) /*!< TSDNEE1 (Bit 29) */ + #define R_GWCA0_GWEIE0_TSDNEE1_Msk (0x20000000UL) /*!< TSDNEE1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID0 ========================================================= */ + #define R_GWCA0_GWEID0_AED_Pos (0UL) /*!< AED (Bit 0) */ + #define R_GWCA0_GWEID0_AED_Msk (0x1UL) /*!< AED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TECCED_Pos (1UL) /*!< TECCED (Bit 1) */ + #define R_GWCA0_GWEID0_TECCED_Msk (0x2UL) /*!< TECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_DECCED_Pos (2UL) /*!< DECCED (Bit 2) */ + #define R_GWCA0_GWEID0_DECCED_Msk (0x4UL) /*!< DECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_PECCED_Pos (3UL) /*!< PECCED (Bit 3) */ + #define R_GWCA0_GWEID0_PECCED_Msk (0x8UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_DSECCED_Pos (4UL) /*!< DSECCED (Bit 4) */ + #define R_GWCA0_GWEID0_DSECCED_Msk (0x10UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_MECCED_Pos (5UL) /*!< MECCED (Bit 5) */ + #define R_GWCA0_GWEID0_MECCED_Msk (0x20UL) /*!< MECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_AECCED_Pos (6UL) /*!< AECCED (Bit 6) */ + #define R_GWCA0_GWEID0_AECCED_Msk (0x40UL) /*!< AECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSECCED_Pos (7UL) /*!< TSECCED (Bit 7) */ + #define R_GWCA0_GWEID0_TSECCED_Msk (0x80UL) /*!< TSECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_L23UECCED_Pos (8UL) /*!< L23UECCED (Bit 8) */ + #define R_GWCA0_GWEID0_L23UECCED_Msk (0x100UL) /*!< L23UECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSOVFED_Pos (9UL) /*!< TSOVFED (Bit 9) */ + #define R_GWCA0_GWEID0_TSOVFED_Msk (0x200UL) /*!< TSOVFED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_USMFSED_Pos (10UL) /*!< USMFSED (Bit 10) */ + #define R_GWCA0_GWEID0_USMFSED_Msk (0x400UL) /*!< USMFSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TFED_Pos (11UL) /*!< TFED (Bit 11) */ + #define R_GWCA0_GWEID0_TFED_Msk (0x800UL) /*!< TFED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_SEQED_Pos (12UL) /*!< SEQED (Bit 12) */ + #define R_GWCA0_GWEID0_SEQED_Msk (0x1000UL) /*!< SEQED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_IIPED_Pos (13UL) /*!< IIPED (Bit 13) */ + #define R_GWCA0_GWEID0_IIPED_Msk (0x2000UL) /*!< IIPED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TXDNED_Pos (14UL) /*!< TXDNED (Bit 14) */ + #define R_GWCA0_GWEID0_TXDNED_Msk (0x4000UL) /*!< TXDNED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSHED_Pos (15UL) /*!< TSHED (Bit 15) */ + #define R_GWCA0_GWEID0_TSHED_Msk (0x8000UL) /*!< TSHED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED0_Pos (16UL) /*!< FSED0 (Bit 16) */ + #define R_GWCA0_GWEID0_FSED0_Msk (0x10000UL) /*!< FSED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED1_Pos (17UL) /*!< FSED1 (Bit 17) */ + #define R_GWCA0_GWEID0_FSED1_Msk (0x20000UL) /*!< FSED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED2_Pos (18UL) /*!< FSED2 (Bit 18) */ + #define R_GWCA0_GWEID0_FSED2_Msk (0x40000UL) /*!< FSED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED3_Pos (19UL) /*!< FSED3 (Bit 19) */ + #define R_GWCA0_GWEID0_FSED3_Msk (0x80000UL) /*!< FSED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED4_Pos (20UL) /*!< FSED4 (Bit 20) */ + #define R_GWCA0_GWEID0_FSED4_Msk (0x100000UL) /*!< FSED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED5_Pos (21UL) /*!< FSED5 (Bit 21) */ + #define R_GWCA0_GWEID0_FSED5_Msk (0x200000UL) /*!< FSED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED6_Pos (22UL) /*!< FSED6 (Bit 22) */ + #define R_GWCA0_GWEID0_FSED6_Msk (0x400000UL) /*!< FSED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED7_Pos (23UL) /*!< FSED7 (Bit 23) */ + #define R_GWCA0_GWEID0_FSED7_Msk (0x800000UL) /*!< FSED7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TDFED0_Pos (24UL) /*!< TDFED0 (Bit 24) */ + #define R_GWCA0_GWEID0_TDFED0_Msk (0x1000000UL) /*!< TDFED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TDFED1_Pos (25UL) /*!< TDFED1 (Bit 25) */ + #define R_GWCA0_GWEID0_TDFED1_Msk (0x2000000UL) /*!< TDFED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSDNED0_Pos (28UL) /*!< TSDNED0 (Bit 28) */ + #define R_GWCA0_GWEID0_TSDNED0_Msk (0x10000000UL) /*!< TSDNED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSDNED1_Pos (29UL) /*!< TSDNED1 (Bit 29) */ + #define R_GWCA0_GWEID0_TSDNED1_Msk (0x20000000UL) /*!< TSDNED1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS1 ========================================================= */ + #define R_GWCA0_GWEIS1_DQOES0_Pos (0UL) /*!< DQOES0 (Bit 0) */ + #define R_GWCA0_GWEIS1_DQOES0_Msk (0x1UL) /*!< DQOES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES1_Pos (1UL) /*!< DQOES1 (Bit 1) */ + #define R_GWCA0_GWEIS1_DQOES1_Msk (0x2UL) /*!< DQOES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES2_Pos (2UL) /*!< DQOES2 (Bit 2) */ + #define R_GWCA0_GWEIS1_DQOES2_Msk (0x4UL) /*!< DQOES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES3_Pos (3UL) /*!< DQOES3 (Bit 3) */ + #define R_GWCA0_GWEIS1_DQOES3_Msk (0x8UL) /*!< DQOES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES4_Pos (4UL) /*!< DQOES4 (Bit 4) */ + #define R_GWCA0_GWEIS1_DQOES4_Msk (0x10UL) /*!< DQOES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES5_Pos (5UL) /*!< DQOES5 (Bit 5) */ + #define R_GWCA0_GWEIS1_DQOES5_Msk (0x20UL) /*!< DQOES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES6_Pos (6UL) /*!< DQOES6 (Bit 6) */ + #define R_GWCA0_GWEIS1_DQOES6_Msk (0x40UL) /*!< DQOES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES7_Pos (7UL) /*!< DQOES7 (Bit 7) */ + #define R_GWCA0_GWEIS1_DQOES7_Msk (0x80UL) /*!< DQOES7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES0_Pos (16UL) /*!< DQSES0 (Bit 16) */ + #define R_GWCA0_GWEIS1_DQSES0_Msk (0x10000UL) /*!< DQSES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES1_Pos (17UL) /*!< DQSES1 (Bit 17) */ + #define R_GWCA0_GWEIS1_DQSES1_Msk (0x20000UL) /*!< DQSES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES2_Pos (18UL) /*!< DQSES2 (Bit 18) */ + #define R_GWCA0_GWEIS1_DQSES2_Msk (0x40000UL) /*!< DQSES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES3_Pos (19UL) /*!< DQSES3 (Bit 19) */ + #define R_GWCA0_GWEIS1_DQSES3_Msk (0x80000UL) /*!< DQSES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES4_Pos (20UL) /*!< DQSES4 (Bit 20) */ + #define R_GWCA0_GWEIS1_DQSES4_Msk (0x100000UL) /*!< DQSES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES5_Pos (21UL) /*!< DQSES5 (Bit 21) */ + #define R_GWCA0_GWEIS1_DQSES5_Msk (0x200000UL) /*!< DQSES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES6_Pos (22UL) /*!< DQSES6 (Bit 22) */ + #define R_GWCA0_GWEIS1_DQSES6_Msk (0x400000UL) /*!< DQSES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES7_Pos (23UL) /*!< DQSES7 (Bit 23) */ + #define R_GWCA0_GWEIS1_DQSES7_Msk (0x800000UL) /*!< DQSES7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE1 ========================================================= */ + #define R_GWCA0_GWEIE1_DQOEE0_Pos (0UL) /*!< DQOEE0 (Bit 0) */ + #define R_GWCA0_GWEIE1_DQOEE0_Msk (0x1UL) /*!< DQOEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE1_Pos (1UL) /*!< DQOEE1 (Bit 1) */ + #define R_GWCA0_GWEIE1_DQOEE1_Msk (0x2UL) /*!< DQOEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE2_Pos (2UL) /*!< DQOEE2 (Bit 2) */ + #define R_GWCA0_GWEIE1_DQOEE2_Msk (0x4UL) /*!< DQOEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE3_Pos (3UL) /*!< DQOEE3 (Bit 3) */ + #define R_GWCA0_GWEIE1_DQOEE3_Msk (0x8UL) /*!< DQOEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE4_Pos (4UL) /*!< DQOEE4 (Bit 4) */ + #define R_GWCA0_GWEIE1_DQOEE4_Msk (0x10UL) /*!< DQOEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE5_Pos (5UL) /*!< DQOEE5 (Bit 5) */ + #define R_GWCA0_GWEIE1_DQOEE5_Msk (0x20UL) /*!< DQOEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE6_Pos (6UL) /*!< DQOEE6 (Bit 6) */ + #define R_GWCA0_GWEIE1_DQOEE6_Msk (0x40UL) /*!< DQOEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE7_Pos (7UL) /*!< DQOEE7 (Bit 7) */ + #define R_GWCA0_GWEIE1_DQOEE7_Msk (0x80UL) /*!< DQOEE7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE0_Pos (16UL) /*!< DQSEE0 (Bit 16) */ + #define R_GWCA0_GWEIE1_DQSEE0_Msk (0x10000UL) /*!< DQSEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE1_Pos (17UL) /*!< DQSEE1 (Bit 17) */ + #define R_GWCA0_GWEIE1_DQSEE1_Msk (0x20000UL) /*!< DQSEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE2_Pos (18UL) /*!< DQSEE2 (Bit 18) */ + #define R_GWCA0_GWEIE1_DQSEE2_Msk (0x40000UL) /*!< DQSEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE3_Pos (19UL) /*!< DQSEE3 (Bit 19) */ + #define R_GWCA0_GWEIE1_DQSEE3_Msk (0x80000UL) /*!< DQSEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE4_Pos (20UL) /*!< DQSEE4 (Bit 20) */ + #define R_GWCA0_GWEIE1_DQSEE4_Msk (0x100000UL) /*!< DQSEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE5_Pos (21UL) /*!< DQSEE5 (Bit 21) */ + #define R_GWCA0_GWEIE1_DQSEE5_Msk (0x200000UL) /*!< DQSEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE6_Pos (22UL) /*!< DQSEE6 (Bit 22) */ + #define R_GWCA0_GWEIE1_DQSEE6_Msk (0x400000UL) /*!< DQSEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE7_Pos (23UL) /*!< DQSEE7 (Bit 23) */ + #define R_GWCA0_GWEIE1_DQSEE7_Msk (0x800000UL) /*!< DQSEE7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID1 ========================================================= */ + #define R_GWCA0_GWEID1_DQOED0_Pos (0UL) /*!< DQOED0 (Bit 0) */ + #define R_GWCA0_GWEID1_DQOED0_Msk (0x1UL) /*!< DQOED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED1_Pos (1UL) /*!< DQOED1 (Bit 1) */ + #define R_GWCA0_GWEID1_DQOED1_Msk (0x2UL) /*!< DQOED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED2_Pos (2UL) /*!< DQOED2 (Bit 2) */ + #define R_GWCA0_GWEID1_DQOED2_Msk (0x4UL) /*!< DQOED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED3_Pos (3UL) /*!< DQOED3 (Bit 3) */ + #define R_GWCA0_GWEID1_DQOED3_Msk (0x8UL) /*!< DQOED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED4_Pos (4UL) /*!< DQOED4 (Bit 4) */ + #define R_GWCA0_GWEID1_DQOED4_Msk (0x10UL) /*!< DQOED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED5_Pos (5UL) /*!< DQOED5 (Bit 5) */ + #define R_GWCA0_GWEID1_DQOED5_Msk (0x20UL) /*!< DQOED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED6_Pos (6UL) /*!< DQOED6 (Bit 6) */ + #define R_GWCA0_GWEID1_DQOED6_Msk (0x40UL) /*!< DQOED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED7_Pos (7UL) /*!< DQOED7 (Bit 7) */ + #define R_GWCA0_GWEID1_DQOED7_Msk (0x80UL) /*!< DQOED7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED0_Pos (16UL) /*!< DQSED0 (Bit 16) */ + #define R_GWCA0_GWEID1_DQSED0_Msk (0x10000UL) /*!< DQSED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED1_Pos (17UL) /*!< DQSED1 (Bit 17) */ + #define R_GWCA0_GWEID1_DQSED1_Msk (0x20000UL) /*!< DQSED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED2_Pos (18UL) /*!< DQSED2 (Bit 18) */ + #define R_GWCA0_GWEID1_DQSED2_Msk (0x40000UL) /*!< DQSED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED3_Pos (19UL) /*!< DQSED3 (Bit 19) */ + #define R_GWCA0_GWEID1_DQSED3_Msk (0x80000UL) /*!< DQSED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED4_Pos (20UL) /*!< DQSED4 (Bit 20) */ + #define R_GWCA0_GWEID1_DQSED4_Msk (0x100000UL) /*!< DQSED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED5_Pos (21UL) /*!< DQSED5 (Bit 21) */ + #define R_GWCA0_GWEID1_DQSED5_Msk (0x200000UL) /*!< DQSED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED6_Pos (22UL) /*!< DQSED6 (Bit 22) */ + #define R_GWCA0_GWEID1_DQSED6_Msk (0x400000UL) /*!< DQSED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED7_Pos (23UL) /*!< DQSED7 (Bit 23) */ + #define R_GWCA0_GWEID1_DQSED7_Msk (0x800000UL) /*!< DQSED7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS20 ======================================================== */ +/* ======================================================== GWEIE20 ======================================================== */ +/* ======================================================== GWEID20 ======================================================== */ +/* ======================================================== GWEIS21 ======================================================== */ +/* ======================================================== GWEIE21 ======================================================== */ +/* ======================================================== GWEID21 ======================================================== */ +/* ======================================================== GWEIS3 ========================================================= */ + #define R_GWCA0_GWEIS3_IAOES0_Pos (0UL) /*!< IAOES0 (Bit 0) */ + #define R_GWCA0_GWEIS3_IAOES0_Msk (0x1UL) /*!< IAOES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES1_Pos (1UL) /*!< IAOES1 (Bit 1) */ + #define R_GWCA0_GWEIS3_IAOES1_Msk (0x2UL) /*!< IAOES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES2_Pos (2UL) /*!< IAOES2 (Bit 2) */ + #define R_GWCA0_GWEIS3_IAOES2_Msk (0x4UL) /*!< IAOES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES3_Pos (3UL) /*!< IAOES3 (Bit 3) */ + #define R_GWCA0_GWEIS3_IAOES3_Msk (0x8UL) /*!< IAOES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES4_Pos (4UL) /*!< IAOES4 (Bit 4) */ + #define R_GWCA0_GWEIS3_IAOES4_Msk (0x10UL) /*!< IAOES4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE3 ========================================================= */ + #define R_GWCA0_GWEIE3_IAOEE0_Pos (0UL) /*!< IAOEE0 (Bit 0) */ + #define R_GWCA0_GWEIE3_IAOEE0_Msk (0x1UL) /*!< IAOEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE1_Pos (1UL) /*!< IAOEE1 (Bit 1) */ + #define R_GWCA0_GWEIE3_IAOEE1_Msk (0x2UL) /*!< IAOEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE2_Pos (2UL) /*!< IAOEE2 (Bit 2) */ + #define R_GWCA0_GWEIE3_IAOEE2_Msk (0x4UL) /*!< IAOEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE3_Pos (3UL) /*!< IAOEE3 (Bit 3) */ + #define R_GWCA0_GWEIE3_IAOEE3_Msk (0x8UL) /*!< IAOEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE4_Pos (4UL) /*!< IAOEE4 (Bit 4) */ + #define R_GWCA0_GWEIE3_IAOEE4_Msk (0x10UL) /*!< IAOEE4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID3 ========================================================= */ + #define R_GWCA0_GWEID3_IAOED0_Pos (0UL) /*!< IAOED0 (Bit 0) */ + #define R_GWCA0_GWEID3_IAOED0_Msk (0x1UL) /*!< IAOED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED1_Pos (1UL) /*!< IAOED1 (Bit 1) */ + #define R_GWCA0_GWEID3_IAOED1_Msk (0x2UL) /*!< IAOED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED2_Pos (2UL) /*!< IAOED2 (Bit 2) */ + #define R_GWCA0_GWEID3_IAOED2_Msk (0x4UL) /*!< IAOED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED3_Pos (3UL) /*!< IAOED3 (Bit 3) */ + #define R_GWCA0_GWEID3_IAOED3_Msk (0x8UL) /*!< IAOED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED4_Pos (4UL) /*!< IAOED4 (Bit 4) */ + #define R_GWCA0_GWEID3_IAOED4_Msk (0x10UL) /*!< IAOED4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS4 ========================================================= */ + #define R_GWCA0_GWEIS4_DSSES_Pos (0UL) /*!< DSSES (Bit 0) */ + #define R_GWCA0_GWEIS4_DSSES_Msk (0x1UL) /*!< DSSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSSEIOS_Pos (1UL) /*!< DSSEIOS (Bit 1) */ + #define R_GWCA0_GWEIS4_DSSEIOS_Msk (0x2UL) /*!< DSSEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSSECN_Pos (8UL) /*!< DSSECN (Bit 8) */ + #define R_GWCA0_GWEIS4_DSSECN_Msk (0x3f00UL) /*!< DSSECN (Bitfield-Mask: 0x3f) */ + #define R_GWCA0_GWEIS4_DSES_Pos (16UL) /*!< DSES (Bit 16) */ + #define R_GWCA0_GWEIS4_DSES_Msk (0x10000UL) /*!< DSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSEIOS_Pos (17UL) /*!< DSEIOS (Bit 17) */ + #define R_GWCA0_GWEIS4_DSEIOS_Msk (0x20000UL) /*!< DSEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSECN_Pos (24UL) /*!< DSECN (Bit 24) */ + #define R_GWCA0_GWEIS4_DSECN_Msk (0x3f000000UL) /*!< DSECN (Bitfield-Mask: 0x3f) */ +/* ======================================================== GWEIE4 ========================================================= */ + #define R_GWCA0_GWEIE4_DSSEE_Pos (0UL) /*!< DSSEE (Bit 0) */ + #define R_GWCA0_GWEIE4_DSSEE_Msk (0x1UL) /*!< DSSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSSEIOE_Pos (1UL) /*!< DSSEIOE (Bit 1) */ + #define R_GWCA0_GWEIE4_DSSEIOE_Msk (0x2UL) /*!< DSSEIOE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSEE_Pos (16UL) /*!< DSEE (Bit 16) */ + #define R_GWCA0_GWEIE4_DSEE_Msk (0x10000UL) /*!< DSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSEIOE_Pos (17UL) /*!< DSEIOE (Bit 17) */ + #define R_GWCA0_GWEIE4_DSEIOE_Msk (0x20000UL) /*!< DSEIOE (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID4 ========================================================= */ + #define R_GWCA0_GWEID4_DSSED_Pos (0UL) /*!< DSSED (Bit 0) */ + #define R_GWCA0_GWEID4_DSSED_Msk (0x1UL) /*!< DSSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSSEIOD_Pos (1UL) /*!< DSSEIOD (Bit 1) */ + #define R_GWCA0_GWEID4_DSSEIOD_Msk (0x2UL) /*!< DSSEIOD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSED_Pos (16UL) /*!< DSED (Bit 16) */ + #define R_GWCA0_GWEID4_DSED_Msk (0x10000UL) /*!< DSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSEIOD_Pos (17UL) /*!< DSEIOD (Bit 17) */ + #define R_GWCA0_GWEID4_DSEIOD_Msk (0x20000UL) /*!< DSEIOD (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS5 ========================================================= */ + #define R_GWCA0_GWEIS5_DCTES_Pos (0UL) /*!< DCTES (Bit 0) */ + #define R_GWCA0_GWEIS5_DCTES_Msk (0x1UL) /*!< DCTES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_DCTEIOS_Pos (1UL) /*!< DCTEIOS (Bit 1) */ + #define R_GWCA0_GWEIS5_DCTEIOS_Msk (0x2UL) /*!< DCTEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_DCTECN_Pos (8UL) /*!< DCTECN (Bit 8) */ + #define R_GWCA0_GWEIS5_DCTECN_Msk (0x3f00UL) /*!< DCTECN (Bitfield-Mask: 0x3f) */ + #define R_GWCA0_GWEIS5_RXDNES_Pos (16UL) /*!< RXDNES (Bit 16) */ + #define R_GWCA0_GWEIS5_RXDNES_Msk (0x10000UL) /*!< RXDNES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_RXDNEIOS_Pos (17UL) /*!< RXDNEIOS (Bit 17) */ + #define R_GWCA0_GWEIS5_RXDNEIOS_Msk (0x20000UL) /*!< RXDNEIOS (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE5 ========================================================= */ + #define R_GWCA0_GWEIE5_DCTEE_Pos (0UL) /*!< DCTEE (Bit 0) */ + #define R_GWCA0_GWEIE5_DCTEE_Msk (0x1UL) /*!< DCTEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_DCTEIOE_Pos (1UL) /*!< DCTEIOE (Bit 1) */ + #define R_GWCA0_GWEIE5_DCTEIOE_Msk (0x2UL) /*!< DCTEIOE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_RXDNEE_Pos (16UL) /*!< RXDNEE (Bit 16) */ + #define R_GWCA0_GWEIE5_RXDNEE_Msk (0x10000UL) /*!< RXDNEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_RXDNEIOE_Pos (17UL) /*!< RXDNEIOE (Bit 17) */ + #define R_GWCA0_GWEIE5_RXDNEIOE_Msk (0x20000UL) /*!< RXDNEIOE (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID5 ========================================================= */ + #define R_GWCA0_GWEID5_DCTED_Pos (0UL) /*!< DCTED (Bit 0) */ + #define R_GWCA0_GWEID5_DCTED_Msk (0x1UL) /*!< DCTED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_DCTEIOD_Pos (1UL) /*!< DCTEIOD (Bit 1) */ + #define R_GWCA0_GWEID5_DCTEIOD_Msk (0x2UL) /*!< DCTEIOD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_RXDNED_Pos (15UL) /*!< RXDNED (Bit 15) */ + #define R_GWCA0_GWEID5_RXDNED_Msk (0x8000UL) /*!< RXDNED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_RXDNEIOD_Pos (16UL) /*!< RXDNEIOD (Bit 16) */ + #define R_GWCA0_GWEID5_RXDNEIOD_Msk (0x10000UL) /*!< RXDNEIOD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IPC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IPCSEM ========================================================= */ + #define R_IPC_IPCSEM_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_IPC_IPCSEM_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MFWD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FWGC ========================================================== */ + #define R_MFWD_FWGC_SVM_Pos (0UL) /*!< SVM (Bit 0) */ + #define R_MFWD_FWGC_SVM_Msk (0x3UL) /*!< SVM (Bitfield-Mask: 0x03) */ +/* ======================================================== FWTTC0 ========================================================= */ + #define R_MFWD_FWTTC0_CTT_Pos (0UL) /*!< CTT (Bit 0) */ + #define R_MFWD_FWTTC0_CTT_Msk (0xffffUL) /*!< CTT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTTC0_STT_Pos (16UL) /*!< STT (Bit 16) */ + #define R_MFWD_FWTTC0_STT_Msk (0xffff0000UL) /*!< STT (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWTTC1 ========================================================= */ + #define R_MFWD_FWTTC1_RTT_Pos (0UL) /*!< RTT (Bit 0) */ + #define R_MFWD_FWTTC1_RTT_Msk (0xffffUL) /*!< RTT (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWCEPTC ======================================================== */ + #define R_MFWD_FWCEPTC_EPCSD_Pos (0UL) /*!< EPCSD (Bit 0) */ + #define R_MFWD_FWCEPTC_EPCSD_Msk (0x7fUL) /*!< EPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCEPTC_EPIPV_Pos (12UL) /*!< EPIPV (Bit 12) */ + #define R_MFWD_FWCEPTC_EPIPV_Msk (0x7000UL) /*!< EPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCEPTC_EPCS_Pos (16UL) /*!< EPCS (Bit 16) */ + #define R_MFWD_FWCEPTC_EPCS_Msk (0x30000UL) /*!< EPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCEPTC_EPSL_Pos (24UL) /*!< EPSL (Bit 24) */ + #define R_MFWD_FWCEPTC_EPSL_Msk (0x1000000UL) /*!< EPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC0 ======================================================== */ + #define R_MFWD_FWCEPRC0_EPHYEEF_Pos (0UL) /*!< EPHYEEF (Bit 0) */ + #define R_MFWD_FWCEPRC0_EPHYEEF_Msk (0x1UL) /*!< EPHYEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EPCRCEEF_Pos (1UL) /*!< EPCRCEEF (Bit 1) */ + #define R_MFWD_FWCEPRC0_EPCRCEEF_Msk (0x2UL) /*!< EPCRCEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ENIBEEF_Pos (2UL) /*!< ENIBEEF (Bit 2) */ + #define R_MFWD_FWCEPRC0_ENIBEEF_Msk (0x4UL) /*!< ENIBEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EFCSEEF_Pos (3UL) /*!< EFCSEEF (Bit 3) */ + #define R_MFWD_FWCEPRC0_EFCSEEF_Msk (0x8UL) /*!< EFCSEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EFFMEEF_Pos (4UL) /*!< EFFMEEF (Bit 4) */ + #define R_MFWD_FWCEPRC0_EFFMEEF_Msk (0x10UL) /*!< EFFMEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ECFSEEF_Pos (5UL) /*!< ECFSEEF (Bit 5) */ + #define R_MFWD_FWCEPRC0_ECFSEEF_Msk (0x20UL) /*!< ECFSEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ECFFCEEF_Pos (6UL) /*!< ECFFCEEF (Bit 6) */ + #define R_MFWD_FWCEPRC0_ECFFCEEF_Msk (0x40UL) /*!< ECFFCEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ERFFEF_Pos (7UL) /*!< ERFFEF (Bit 7) */ + #define R_MFWD_FWCEPRC0_ERFFEF_Msk (0x80UL) /*!< ERFFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ERPOOEF_Pos (8UL) /*!< ERPOOEF (Bit 8) */ + #define R_MFWD_FWCEPRC0_ERPOOEF_Msk (0x100UL) /*!< ERPOOEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EBOEEF_Pos (9UL) /*!< EBOEEF (Bit 9) */ + #define R_MFWD_FWCEPRC0_EBOEEF_Msk (0x200UL) /*!< EBOEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EUEEF_Pos (10UL) /*!< EUEEF (Bit 10) */ + #define R_MFWD_FWCEPRC0_EUEEF_Msk (0x400UL) /*!< EUEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EOEEF_Pos (11UL) /*!< EOEEF (Bit 11) */ + #define R_MFWD_FWCEPRC0_EOEEF_Msk (0x800UL) /*!< EOEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ETFEF_Pos (12UL) /*!< ETFEF (Bit 12) */ + #define R_MFWD_FWCEPRC0_ETFEF_Msk (0x1000UL) /*!< ETFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GAREEEF_Pos (16UL) /*!< GAREEEF (Bit 16) */ + #define R_MFWD_FWCEPRC0_GAREEEF_Msk (0x10000UL) /*!< GAREEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GAXEEF_Pos (17UL) /*!< GAXEEF (Bit 17) */ + #define R_MFWD_FWCEPRC0_GAXEEF_Msk (0x20000UL) /*!< GAXEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GSEQEEF_Pos (18UL) /*!< GSEQEEF (Bit 18) */ + #define R_MFWD_FWCEPRC0_GSEQEEF_Msk (0x40000UL) /*!< GSEQEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GTFEF_Pos (20UL) /*!< GTFEF (Bit 20) */ + #define R_MFWD_FWCEPRC0_GTFEF_Msk (0x100000UL) /*!< GTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GDNEEF_Pos (21UL) /*!< GDNEEF (Bit 21) */ + #define R_MFWD_FWCEPRC0_GDNEEF_Msk (0x200000UL) /*!< GDNEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_DDEEF_Pos (24UL) /*!< DDEEF (Bit 24) */ + #define R_MFWD_FWCEPRC0_DDEEF_Msk (0x1000000UL) /*!< DDEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_DDFSFEF_Pos (26UL) /*!< DDFSFEF (Bit 26) */ + #define R_MFWD_FWCEPRC0_DDFSFEF_Msk (0x4000000UL) /*!< DDFSFEF (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC1 ======================================================== */ + #define R_MFWD_FWCEPRC1_FMSDUFEF_Pos (0UL) /*!< FMSDUFEF (Bit 0) */ + #define R_MFWD_FWCEPRC1_FMSDUFEF_Msk (0x1UL) /*!< FMSDUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FMTRFEF_Pos (2UL) /*!< FMTRFEF (Bit 2) */ + #define R_MFWD_FWCEPRC1_FMTRFEF_Msk (0x4UL) /*!< FMTRFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FIFFEF_Pos (8UL) /*!< FIFFEF (Bit 8) */ + #define R_MFWD_FWCEPRC1_FIFFEF_Msk (0x100UL) /*!< FIFFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FSFFEF_Pos (9UL) /*!< FSFFEF (Bit 9) */ + #define R_MFWD_FWCEPRC1_FSFFEF_Msk (0x200UL) /*!< FSFFEF (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC2 ======================================================== */ + #define R_MFWD_FWCEPRC2_FLTHUFEF_Pos (0UL) /*!< FLTHUFEF (Bit 0) */ + #define R_MFWD_FWCEPRC2_FLTHUFEF_Msk (0x1UL) /*!< FLTHUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDMACUFEF_Pos (3UL) /*!< FDMACUFEF (Bit 3) */ + #define R_MFWD_FWCEPRC2_FDMACUFEF_Msk (0x8UL) /*!< FDMACUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FSMACUFEF_Pos (4UL) /*!< FSMACUFEF (Bit 4) */ + #define R_MFWD_FWCEPRC2_FSMACUFEF_Msk (0x10UL) /*!< FSMACUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FVLANUFEF_Pos (5UL) /*!< FVLANUFEF (Bit 5) */ + #define R_MFWD_FWCEPRC2_FVLANUFEF_Msk (0x20UL) /*!< FVLANUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDDNTFEF_Pos (8UL) /*!< FDDNTFEF (Bit 8) */ + #define R_MFWD_FWCEPRC2_FDDNTFEF_Msk (0x100UL) /*!< FDDNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTHNTFEF_Pos (9UL) /*!< FLTHNTFEF (Bit 9) */ + #define R_MFWD_FWCEPRC2_FLTHNTFEF_Msk (0x200UL) /*!< FLTHNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTWNTFEF_Pos (11UL) /*!< FLTWNTFEF (Bit 11) */ + #define R_MFWD_FWCEPRC2_FLTWNTFEF_Msk (0x800UL) /*!< FLTWNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FPBNTFEF_Pos (12UL) /*!< FPBNTFEF (Bit 12) */ + #define R_MFWD_FWCEPRC2_FPBNTFEF_Msk (0x1000UL) /*!< FPBNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTHSLFEF_Pos (16UL) /*!< FLTHSLFEF (Bit 16) */ + #define R_MFWD_FWCEPRC2_FLTHSLFEF_Msk (0x10000UL) /*!< FLTHSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDMACSLFEF_Pos (19UL) /*!< FDMACSLFEF (Bit 19) */ + #define R_MFWD_FWCEPRC2_FDMACSLFEF_Msk (0x80000UL) /*!< FDMACSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FSMACSLFEF_Pos (20UL) /*!< FSMACSLFEF (Bit 20) */ + #define R_MFWD_FWCEPRC2_FSMACSLFEF_Msk (0x100000UL) /*!< FSMACSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FVLANSLFEF_Pos (21UL) /*!< FVLANSLFEF (Bit 21) */ + #define R_MFWD_FWCEPRC2_FVLANSLFEF_Msk (0x200000UL) /*!< FVLANSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FWMFEF_Pos (26UL) /*!< FWMFEF (Bit 26) */ + #define R_MFWD_FWCEPRC2_FWMFEF_Msk (0x4000000UL) /*!< FWMFEF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCLPTC ======================================================== */ + #define R_MFWD_FWCLPTC_LPCSD_Pos (0UL) /*!< LPCSD (Bit 0) */ + #define R_MFWD_FWCLPTC_LPCSD_Msk (0x7fUL) /*!< LPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCLPTC_LPIPV_Pos (12UL) /*!< LPIPV (Bit 12) */ + #define R_MFWD_FWCLPTC_LPIPV_Msk (0x7000UL) /*!< LPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCLPTC_LPCS_Pos (16UL) /*!< LPCS (Bit 16) */ + #define R_MFWD_FWCLPTC_LPCS_Msk (0x30000UL) /*!< LPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCLPTC_LPSL_Pos (24UL) /*!< LPSL (Bit 24) */ + #define R_MFWD_FWCLPTC_LPSL_Msk (0x1000000UL) /*!< LPSL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCLPRC ======================================================== */ + #define R_MFWD_FWCLPRC_USIDLF_Pos (0UL) /*!< USIDLF (Bit 0) */ + #define R_MFWD_FWCLPRC_USIDLF_Msk (0x1UL) /*!< USIDLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UDMACLF_Pos (4UL) /*!< UDMACLF (Bit 4) */ + #define R_MFWD_FWCLPRC_UDMACLF_Msk (0x10UL) /*!< UDMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_USMACLF_Pos (5UL) /*!< USMACLF (Bit 5) */ + #define R_MFWD_FWCLPRC_USMACLF_Msk (0x20UL) /*!< USMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UPSMACLF_Pos (6UL) /*!< UPSMACLF (Bit 6) */ + #define R_MFWD_FWCLPRC_UPSMACLF_Msk (0x40UL) /*!< UPSMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UVLANLF_Pos (7UL) /*!< UVLANLF (Bit 7) */ + #define R_MFWD_FWCLPRC_UVLANLF_Msk (0x80UL) /*!< UVLANLF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCMPTC ======================================================== */ + #define R_MFWD_FWCMPTC_CMPCSD_Pos (0UL) /*!< CMPCSD (Bit 0) */ + #define R_MFWD_FWCMPTC_CMPCSD_Msk (0x7fUL) /*!< CMPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCMPTC_CMPIPV_Pos (12UL) /*!< CMPIPV (Bit 12) */ + #define R_MFWD_FWCMPTC_CMPIPV_Msk (0x7000UL) /*!< CMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCMPTC_CMPIPU_Pos (15UL) /*!< CMPIPU (Bit 15) */ + #define R_MFWD_FWCMPTC_CMPIPU_Msk (0x8000UL) /*!< CMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCMPTC_CMPCS_Pos (16UL) /*!< CMPCS (Bit 16) */ + #define R_MFWD_FWCMPTC_CMPCS_Msk (0x30000UL) /*!< CMPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCMPTC_CMPSL_Pos (24UL) /*!< CMPSL (Bit 24) */ + #define R_MFWD_FWCMPTC_CMPSL_Msk (0x1000000UL) /*!< CMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEMPTC ======================================================== */ + #define R_MFWD_FWEMPTC_EMPIPV_Pos (12UL) /*!< EMPIPV (Bit 12) */ + #define R_MFWD_FWEMPTC_EMPIPV_Msk (0x7000UL) /*!< EMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWEMPTC_EMPIPU_Pos (15UL) /*!< EMPIPU (Bit 15) */ + #define R_MFWD_FWEMPTC_EMPIPU_Msk (0x8000UL) /*!< EMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEMPTC_EMPPS_Pos (16UL) /*!< EMPPS (Bit 16) */ + #define R_MFWD_FWEMPTC_EMPPS_Msk (0x30000UL) /*!< EMPPS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWEMPTC_EMPSL_Pos (24UL) /*!< EMPSL (Bit 24) */ + #define R_MFWD_FWEMPTC_EMPSL_Msk (0x1000000UL) /*!< EMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSDMPTC ======================================================== */ + #define R_MFWD_FWSDMPTC_SDMPCSD_Pos (0UL) /*!< SDMPCSD (Bit 0) */ + #define R_MFWD_FWSDMPTC_SDMPCSD_Msk (0x7fUL) /*!< SDMPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWSDMPTC_SDMPIPV_Pos (12UL) /*!< SDMPIPV (Bit 12) */ + #define R_MFWD_FWSDMPTC_SDMPIPV_Msk (0x7000UL) /*!< SDMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWSDMPTC_SDMPIPU_Pos (15UL) /*!< SDMPIPU (Bit 15) */ + #define R_MFWD_FWSDMPTC_SDMPIPU_Msk (0x8000UL) /*!< SDMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSDMPTC_SDMPPS_Pos (16UL) /*!< SDMPPS (Bit 16) */ + #define R_MFWD_FWSDMPTC_SDMPPS_Msk (0x30000UL) /*!< SDMPPS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWSDMPTC_SDMPSL_Pos (24UL) /*!< SDMPSL (Bit 24) */ + #define R_MFWD_FWSDMPTC_SDMPSL_Msk (0x1000000UL) /*!< SDMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSDMPVC ======================================================== */ + #define R_MFWD_FWSDMPVC_SDMDV_Pos (0UL) /*!< SDMDV (Bit 0) */ + #define R_MFWD_FWSDMPVC_SDMDV_Msk (0x7fUL) /*!< SDMDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWSDMPVC_SDMSV_Pos (16UL) /*!< SDMSV (Bit 16) */ + #define R_MFWD_FWSDMPVC_SDMSV_Msk (0x7f0000UL) /*!< SDMSV (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLBWMC0 ======================================================== */ + #define R_MFWD_FWLBWMC0_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC0_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC0_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC0_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWLBWMC1 ======================================================== */ + #define R_MFWD_FWLBWMC1_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC1_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC1_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC1_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWLBWMC2 ======================================================== */ + #define R_MFWD_FWLBWMC2_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC2_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC2_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC2_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWPC00 ========================================================= */ + #define R_MFWD_FWPC00_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC00_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC00_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC00_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC00_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC00_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC00_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC00_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC00_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC00_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC00_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC00_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC00_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC00_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC00_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC00_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC00_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC00_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC00_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC00_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC00_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC00_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC01 ========================================================= */ + #define R_MFWD_FWPC01_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC01_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC01_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC01_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC01_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC01_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC01_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC01_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC01_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC01_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC01_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC01_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC01_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC01_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC01_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC01_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC01_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC01_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC01_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC01_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC01_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC01_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC02 ========================================================= */ + #define R_MFWD_FWPC02_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC02_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC02_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC02_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC02_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC02_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC02_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC02_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC02_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC02_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC02_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC02_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC02_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC02_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC02_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC02_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC02_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC02_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC02_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC02_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC02_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC02_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC10 ========================================================= */ + #define R_MFWD_FWPC10_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC10_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC10_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC10_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC10_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC10_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC11 ========================================================= */ + #define R_MFWD_FWPC11_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC11_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC11_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC11_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC11_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC11_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC12 ========================================================= */ + #define R_MFWD_FWPC12_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC12_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC12_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC12_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC12_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC12_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC20 ========================================================= */ + #define R_MFWD_FWPC20_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC20_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC21 ========================================================= */ + #define R_MFWD_FWPC21_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC21_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC22 ========================================================= */ + #define R_MFWD_FWPC22_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC22_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTGC00 ======================================================== */ + #define R_MFWD_FWCTGC00_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC00_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC00_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC00_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC00_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC00_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC00_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC00_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC00_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC00_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC00_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC00_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC00_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC00_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC01 ======================================================== */ + #define R_MFWD_FWCTGC01_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC01_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC01_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC01_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC01_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC01_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC01_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC01_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC01_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC01_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC01_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC01_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC01_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC01_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC02 ======================================================== */ + #define R_MFWD_FWCTGC02_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC02_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC02_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC02_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC02_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC02_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC02_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC02_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC02_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC02_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC02_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC02_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC02_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC02_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC03 ======================================================== */ + #define R_MFWD_FWCTGC03_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC03_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC03_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC03_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC03_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC03_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC03_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC03_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC03_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC03_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC03_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC03_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC03_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC03_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC04 ======================================================== */ + #define R_MFWD_FWCTGC04_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC04_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC04_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC04_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC04_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC04_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC04_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC04_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC04_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC04_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC04_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC04_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC04_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC04_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC05 ======================================================== */ + #define R_MFWD_FWCTGC05_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC05_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC05_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC05_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC05_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC05_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC05_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC05_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC05_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC05_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC05_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC05_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC05_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC05_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC06 ======================================================== */ + #define R_MFWD_FWCTGC06_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC06_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC06_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC06_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC06_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC06_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC06_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC06_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC06_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC06_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC06_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC06_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC06_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC06_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC07 ======================================================== */ + #define R_MFWD_FWCTGC07_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC07_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC07_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC07_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC07_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC07_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC07_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC07_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC07_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC07_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC07_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC07_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC07_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC07_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC10 ======================================================== */ + #define R_MFWD_FWCTGC10_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC10_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC11 ======================================================== */ + #define R_MFWD_FWCTGC11_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC11_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC12 ======================================================== */ + #define R_MFWD_FWCTGC12_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC12_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC13 ======================================================== */ + #define R_MFWD_FWCTGC13_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC13_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC14 ======================================================== */ + #define R_MFWD_FWCTGC14_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC14_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC15 ======================================================== */ + #define R_MFWD_FWCTGC15_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC15_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC16 ======================================================== */ + #define R_MFWD_FWCTGC16_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC16_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC17 ======================================================== */ + #define R_MFWD_FWCTGC17_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC17_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTTC00 ======================================================== */ + #define R_MFWD_FWCTTC00_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC00_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC00_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC00_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC01 ======================================================== */ + #define R_MFWD_FWCTTC01_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC01_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC01_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC01_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC02 ======================================================== */ + #define R_MFWD_FWCTTC02_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC02_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC02_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC02_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC03 ======================================================== */ + #define R_MFWD_FWCTTC03_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC03_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC03_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC03_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC04 ======================================================== */ + #define R_MFWD_FWCTTC04_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC04_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC04_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC04_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC05 ======================================================== */ + #define R_MFWD_FWCTTC05_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC05_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC05_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC05_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC06 ======================================================== */ + #define R_MFWD_FWCTTC06_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC06_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC06_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC06_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC07 ======================================================== */ + #define R_MFWD_FWCTTC07_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC07_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC07_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC07_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC10 ======================================================== */ + #define R_MFWD_FWCTTC10_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC10_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC10_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC10_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC10_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC10_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC10_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC10_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC11 ======================================================== */ + #define R_MFWD_FWCTTC11_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC11_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC11_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC11_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC11_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC11_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC11_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC11_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC12 ======================================================== */ + #define R_MFWD_FWCTTC12_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC12_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC12_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC12_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC12_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC12_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC12_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC12_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC13 ======================================================== */ + #define R_MFWD_FWCTTC13_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC13_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC13_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC13_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC13_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC13_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC13_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC13_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC14 ======================================================== */ + #define R_MFWD_FWCTTC14_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC14_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC14_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC14_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC14_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC14_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC14_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC14_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC15 ======================================================== */ + #define R_MFWD_FWCTTC15_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC15_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC15_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC15_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC15_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC15_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC15_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC15_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC16 ======================================================== */ + #define R_MFWD_FWCTTC16_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC16_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC16_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC16_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC16_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC16_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC16_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC16_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC17 ======================================================== */ + #define R_MFWD_FWCTTC17_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC17_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC17_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC17_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC17_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC17_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC17_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC17_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC200 ======================================================= */ + #define R_MFWD_FWCTTC200_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC200_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC201 ======================================================= */ + #define R_MFWD_FWCTTC201_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC201_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC202 ======================================================= */ + #define R_MFWD_FWCTTC202_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC202_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC203 ======================================================= */ + #define R_MFWD_FWCTTC203_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC203_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC204 ======================================================= */ + #define R_MFWD_FWCTTC204_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC204_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC205 ======================================================= */ + #define R_MFWD_FWCTTC205_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC205_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC206 ======================================================= */ + #define R_MFWD_FWCTTC206_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC206_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC207 ======================================================= */ + #define R_MFWD_FWCTTC207_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC207_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTSC00 ======================================================== */ + #define R_MFWD_FWCTSC00_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC00_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC01 ======================================================== */ + #define R_MFWD_FWCTSC01_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC01_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC02 ======================================================== */ + #define R_MFWD_FWCTSC02_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC02_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC03 ======================================================== */ + #define R_MFWD_FWCTSC03_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC03_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC04 ======================================================== */ + #define R_MFWD_FWCTSC04_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC04_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC05 ======================================================== */ + #define R_MFWD_FWCTSC05_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC05_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC06 ======================================================== */ + #define R_MFWD_FWCTSC06_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC06_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC07 ======================================================== */ + #define R_MFWD_FWCTSC07_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC07_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC10 ======================================================== */ + #define R_MFWD_FWCTSC10_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC10_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC10_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC10_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC11 ======================================================== */ + #define R_MFWD_FWCTSC11_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC11_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC11_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC11_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC12 ======================================================== */ + #define R_MFWD_FWCTSC12_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC12_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC12_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC12_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC13 ======================================================== */ + #define R_MFWD_FWCTSC13_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC13_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC13_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC13_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC14 ======================================================== */ + #define R_MFWD_FWCTSC14_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC14_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC14_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC14_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC15 ======================================================== */ + #define R_MFWD_FWCTSC15_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC15_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC15_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC15_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC16 ======================================================== */ + #define R_MFWD_FWCTSC16_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC16_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC16_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC16_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC17 ======================================================== */ + #define R_MFWD_FWCTSC17_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC17_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC17_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC17_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC20 ======================================================== */ + #define R_MFWD_FWCTSC20_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC20_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC21 ======================================================== */ + #define R_MFWD_FWCTSC21_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC21_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC22 ======================================================== */ + #define R_MFWD_FWCTSC22_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC22_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC23 ======================================================== */ + #define R_MFWD_FWCTSC23_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC23_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC24 ======================================================== */ + #define R_MFWD_FWCTSC24_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC24_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC25 ======================================================== */ + #define R_MFWD_FWCTSC25_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC25_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC26 ======================================================== */ + #define R_MFWD_FWCTSC26_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC26_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC27 ======================================================== */ + #define R_MFWD_FWCTSC27_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC27_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC30 ======================================================== */ + #define R_MFWD_FWCTSC30_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC30_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC30_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC30_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC30_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC30_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC30_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC30_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC30_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC30_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC30_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC30_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC31 ======================================================== */ + #define R_MFWD_FWCTSC31_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC31_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC31_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC31_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC31_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC31_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC31_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC31_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC31_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC31_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC31_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC31_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC32 ======================================================== */ + #define R_MFWD_FWCTSC32_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC32_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC32_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC32_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC32_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC32_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC32_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC32_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC32_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC32_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC32_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC32_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC33 ======================================================== */ + #define R_MFWD_FWCTSC33_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC33_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC33_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC33_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC33_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC33_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC33_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC33_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC33_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC33_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC33_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC33_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC34 ======================================================== */ + #define R_MFWD_FWCTSC34_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC34_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC34_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC34_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC34_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC34_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC34_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC34_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC34_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC34_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC34_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC34_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC35 ======================================================== */ + #define R_MFWD_FWCTSC35_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC35_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC35_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC35_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC35_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC35_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC35_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC35_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC35_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC35_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC35_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC35_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC36 ======================================================== */ + #define R_MFWD_FWCTSC36_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC36_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC36_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC36_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC36_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC36_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC36_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC36_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC36_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC36_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC36_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC36_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC37 ======================================================== */ + #define R_MFWD_FWCTSC37_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC37_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC37_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC37_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC37_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC37_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC37_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC37_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC37_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC37_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC37_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC37_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC40 ======================================================== */ + #define R_MFWD_FWCTSC40_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC40_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC40_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC40_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC41 ======================================================== */ + #define R_MFWD_FWCTSC41_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC41_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC41_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC41_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC42 ======================================================== */ + #define R_MFWD_FWCTSC42_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC42_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC42_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC42_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC43 ======================================================== */ + #define R_MFWD_FWCTSC43_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC43_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC43_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC43_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC44 ======================================================== */ + #define R_MFWD_FWCTSC44_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC44_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC44_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC44_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC45 ======================================================== */ + #define R_MFWD_FWCTSC45_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC45_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC45_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC45_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC46 ======================================================== */ + #define R_MFWD_FWCTSC46_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC46_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC46_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC46_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC47 ======================================================== */ + #define R_MFWD_FWCTSC47_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC47_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC47_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC47_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWTWBFC0 ======================================================== */ + #define R_MFWD_FWTWBFC0_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC0_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC0_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC0_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC0_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC0_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC1 ======================================================== */ + #define R_MFWD_FWTWBFC1_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC1_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC1_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC1_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC1_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC1_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC2 ======================================================== */ + #define R_MFWD_FWTWBFC2_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC2_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC2_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC2_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC2_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC2_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC3 ======================================================== */ + #define R_MFWD_FWTWBFC3_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC3_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC3_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC3_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC3_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC3_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC4 ======================================================== */ + #define R_MFWD_FWTWBFC4_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC4_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC4_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC4_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC4_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC4_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC5 ======================================================== */ + #define R_MFWD_FWTWBFC5_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC5_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC5_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC5_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC5_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC5_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC6 ======================================================== */ + #define R_MFWD_FWTWBFC6_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC6_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC6_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC6_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC6_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC6_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC7 ======================================================== */ + #define R_MFWD_FWTWBFC7_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC7_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC7_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC7_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC7_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC7_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC8 ======================================================== */ + #define R_MFWD_FWTWBFC8_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC8_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC8_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC8_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC8_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC8_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC9 ======================================================== */ + #define R_MFWD_FWTWBFC9_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC9_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC9_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC9_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC9_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC9_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC10 ======================================================= */ + #define R_MFWD_FWTWBFC10_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC10_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC10_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC10_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC10_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC10_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC11 ======================================================= */ + #define R_MFWD_FWTWBFC11_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC11_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC11_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC11_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC11_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC11_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC12 ======================================================= */ + #define R_MFWD_FWTWBFC12_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC12_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC12_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC12_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC12_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC12_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC13 ======================================================= */ + #define R_MFWD_FWTWBFC13_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC13_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC13_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC13_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC13_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC13_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC14 ======================================================= */ + #define R_MFWD_FWTWBFC14_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC14_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC14_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC14_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC14_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC14_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC15 ======================================================= */ + #define R_MFWD_FWTWBFC15_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC15_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC15_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC15_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC15_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC15_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFVC0 ======================================================= */ + #define R_MFWD_FWTWBFVC0_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC0_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC0_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC0_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC1 ======================================================= */ + #define R_MFWD_FWTWBFVC1_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC1_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC1_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC1_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC2 ======================================================= */ + #define R_MFWD_FWTWBFVC2_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC2_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC2_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC2_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC3 ======================================================= */ + #define R_MFWD_FWTWBFVC3_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC3_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC3_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC3_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC4 ======================================================= */ + #define R_MFWD_FWTWBFVC4_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC4_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC4_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC4_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC5 ======================================================= */ + #define R_MFWD_FWTWBFVC5_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC5_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC5_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC5_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC6 ======================================================= */ + #define R_MFWD_FWTWBFVC6_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC6_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC6_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC6_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC7 ======================================================= */ + #define R_MFWD_FWTWBFVC7_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC7_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC7_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC7_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC8 ======================================================= */ + #define R_MFWD_FWTWBFVC8_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC8_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC8_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC8_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC9 ======================================================= */ + #define R_MFWD_FWTWBFVC9_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC9_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC9_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC9_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC10 ======================================================= */ + #define R_MFWD_FWTWBFVC10_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC10_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC10_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC10_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC11 ======================================================= */ + #define R_MFWD_FWTWBFVC11_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC11_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC11_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC11_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC12 ======================================================= */ + #define R_MFWD_FWTWBFVC12_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC12_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC12_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC12_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC13 ======================================================= */ + #define R_MFWD_FWTWBFVC13_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC13_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC13_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC13_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC14 ======================================================= */ + #define R_MFWD_FWTWBFVC14_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC14_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC14_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC14_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC15 ======================================================= */ + #define R_MFWD_FWTWBFVC15_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC15_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC15_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC15_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTHBFC0 ======================================================== */ + #define R_MFWD_FWTHBFC0_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC0_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC0_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC0_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC1 ======================================================== */ + #define R_MFWD_FWTHBFC1_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC1_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC1_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC1_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC2 ======================================================== */ + #define R_MFWD_FWTHBFC2_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC2_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC2_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC2_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC3 ======================================================== */ + #define R_MFWD_FWTHBFC3_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC3_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC3_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC3_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC4 ======================================================== */ + #define R_MFWD_FWTHBFC4_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC4_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC4_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC4_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC5 ======================================================== */ + #define R_MFWD_FWTHBFC5_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC5_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC5_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC5_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC6 ======================================================== */ + #define R_MFWD_FWTHBFC6_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC6_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC6_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC6_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC7 ======================================================== */ + #define R_MFWD_FWTHBFC7_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC7_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC7_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC7_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC8 ======================================================== */ + #define R_MFWD_FWTHBFC8_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC8_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC8_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC8_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC9 ======================================================== */ + #define R_MFWD_FWTHBFC9_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC9_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC9_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC9_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC10 ======================================================= */ + #define R_MFWD_FWTHBFC10_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC10_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC10_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC10_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC11 ======================================================= */ + #define R_MFWD_FWTHBFC11_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC11_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC11_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC11_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC12 ======================================================= */ + #define R_MFWD_FWTHBFC12_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC12_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC12_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC12_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC13 ======================================================= */ + #define R_MFWD_FWTHBFC13_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC13_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC13_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC13_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC14 ======================================================= */ + #define R_MFWD_FWTHBFC14_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC14_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC14_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC14_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC15 ======================================================= */ + #define R_MFWD_FWTHBFC15_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC15_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC15_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC15_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ====================================================== FWTHBFV0C0 ======================================================= */ + #define R_MFWD_FWTHBFV0C0_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C0_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C1 ======================================================= */ + #define R_MFWD_FWTHBFV0C1_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C1_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C2 ======================================================= */ + #define R_MFWD_FWTHBFV0C2_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C2_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C3 ======================================================= */ + #define R_MFWD_FWTHBFV0C3_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C3_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C4 ======================================================= */ + #define R_MFWD_FWTHBFV0C4_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C4_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C5 ======================================================= */ + #define R_MFWD_FWTHBFV0C5_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C5_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C6 ======================================================= */ + #define R_MFWD_FWTHBFV0C6_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C6_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C7 ======================================================= */ + #define R_MFWD_FWTHBFV0C7_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C7_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C8 ======================================================= */ + #define R_MFWD_FWTHBFV0C8_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C8_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C9 ======================================================= */ + #define R_MFWD_FWTHBFV0C9_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C9_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C10 ====================================================== */ + #define R_MFWD_FWTHBFV0C10_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C10_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C11 ====================================================== */ + #define R_MFWD_FWTHBFV0C11_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C11_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C12 ====================================================== */ + #define R_MFWD_FWTHBFV0C12_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C12_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C13 ====================================================== */ + #define R_MFWD_FWTHBFV0C13_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C13_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C14 ====================================================== */ + #define R_MFWD_FWTHBFV0C14_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C14_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C15 ====================================================== */ + #define R_MFWD_FWTHBFV0C15_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C15_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C0 ======================================================= */ + #define R_MFWD_FWTHBFV1C0_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C0_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C1 ======================================================= */ + #define R_MFWD_FWTHBFV1C1_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C1_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C2 ======================================================= */ + #define R_MFWD_FWTHBFV1C2_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C2_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C3 ======================================================= */ + #define R_MFWD_FWTHBFV1C3_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C3_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C4 ======================================================= */ + #define R_MFWD_FWTHBFV1C4_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C4_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C5 ======================================================= */ + #define R_MFWD_FWTHBFV1C5_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C5_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C6 ======================================================= */ + #define R_MFWD_FWTHBFV1C6_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C6_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C7 ======================================================= */ + #define R_MFWD_FWTHBFV1C7_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C7_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C8 ======================================================= */ + #define R_MFWD_FWTHBFV1C8_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C8_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C9 ======================================================= */ + #define R_MFWD_FWTHBFV1C9_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C9_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C10 ====================================================== */ + #define R_MFWD_FWTHBFV1C10_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C10_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C11 ====================================================== */ + #define R_MFWD_FWTHBFV1C11_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C11_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C12 ====================================================== */ + #define R_MFWD_FWTHBFV1C12_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C12_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C13 ====================================================== */ + #define R_MFWD_FWTHBFV1C13_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C13_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C14 ====================================================== */ + #define R_MFWD_FWTHBFV1C14_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C14_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C15 ====================================================== */ + #define R_MFWD_FWTHBFV1C15_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C15_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= FWFOBFC0 ======================================================== */ + #define R_MFWD_FWFOBFC0_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC0_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC0_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC0_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC1 ======================================================== */ + #define R_MFWD_FWFOBFC1_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC1_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC1_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC1_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC2 ======================================================== */ + #define R_MFWD_FWFOBFC2_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC2_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC2_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC2_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC3 ======================================================== */ + #define R_MFWD_FWFOBFC3_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC3_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC3_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC3_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC4 ======================================================== */ + #define R_MFWD_FWFOBFC4_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC4_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC4_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC4_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC5 ======================================================== */ + #define R_MFWD_FWFOBFC5_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC5_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC5_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC5_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC6 ======================================================== */ + #define R_MFWD_FWFOBFC6_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC6_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC6_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC6_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC7 ======================================================== */ + #define R_MFWD_FWFOBFC7_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC7_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC7_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC7_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC8 ======================================================== */ + #define R_MFWD_FWFOBFC8_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC8_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC8_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC8_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC9 ======================================================== */ + #define R_MFWD_FWFOBFC9_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC9_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC9_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC9_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC10 ======================================================= */ + #define R_MFWD_FWFOBFC10_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC10_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC10_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC10_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC11 ======================================================= */ + #define R_MFWD_FWFOBFC11_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC11_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC11_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC11_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC12 ======================================================= */ + #define R_MFWD_FWFOBFC12_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC12_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC12_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC12_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC13 ======================================================= */ + #define R_MFWD_FWFOBFC13_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC13_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC13_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC13_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC14 ======================================================= */ + #define R_MFWD_FWFOBFC14_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC14_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC14_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC14_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC15 ======================================================= */ + #define R_MFWD_FWFOBFC15_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC15_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC15_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC15_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ====================================================== FWFOBFV0C0 ======================================================= */ + #define R_MFWD_FWFOBFV0C0_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C0_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C1 ======================================================= */ + #define R_MFWD_FWFOBFV0C1_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C1_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C2 ======================================================= */ + #define R_MFWD_FWFOBFV0C2_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C2_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C3 ======================================================= */ + #define R_MFWD_FWFOBFV0C3_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C3_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C4 ======================================================= */ + #define R_MFWD_FWFOBFV0C4_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C4_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C5 ======================================================= */ + #define R_MFWD_FWFOBFV0C5_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C5_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C6 ======================================================= */ + #define R_MFWD_FWFOBFV0C6_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C6_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C7 ======================================================= */ + #define R_MFWD_FWFOBFV0C7_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C7_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C8 ======================================================= */ + #define R_MFWD_FWFOBFV0C8_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C8_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C9 ======================================================= */ + #define R_MFWD_FWFOBFV0C9_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C9_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C10 ====================================================== */ + #define R_MFWD_FWFOBFV0C10_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C10_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C11 ====================================================== */ + #define R_MFWD_FWFOBFV0C11_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C11_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C12 ====================================================== */ + #define R_MFWD_FWFOBFV0C12_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C12_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C13 ====================================================== */ + #define R_MFWD_FWFOBFV0C13_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C13_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C14 ====================================================== */ + #define R_MFWD_FWFOBFV0C14_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C14_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C15 ====================================================== */ + #define R_MFWD_FWFOBFV0C15_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C15_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C0 ======================================================= */ + #define R_MFWD_FWFOBFV1C0_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C0_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C1 ======================================================= */ + #define R_MFWD_FWFOBFV1C1_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C1_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C2 ======================================================= */ + #define R_MFWD_FWFOBFV1C2_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C2_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C3 ======================================================= */ + #define R_MFWD_FWFOBFV1C3_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C3_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C4 ======================================================= */ + #define R_MFWD_FWFOBFV1C4_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C4_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C5 ======================================================= */ + #define R_MFWD_FWFOBFV1C5_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C5_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C6 ======================================================= */ + #define R_MFWD_FWFOBFV1C6_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C6_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C7 ======================================================= */ + #define R_MFWD_FWFOBFV1C7_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C7_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C8 ======================================================= */ + #define R_MFWD_FWFOBFV1C8_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C8_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C9 ======================================================= */ + #define R_MFWD_FWFOBFV1C9_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C9_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C10 ====================================================== */ + #define R_MFWD_FWFOBFV1C10_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C10_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C11 ====================================================== */ + #define R_MFWD_FWFOBFV1C11_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C11_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C12 ====================================================== */ + #define R_MFWD_FWFOBFV1C12_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C12_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C13 ====================================================== */ + #define R_MFWD_FWFOBFV1C13_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C13_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C14 ====================================================== */ + #define R_MFWD_FWFOBFV1C14_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C14_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C15 ====================================================== */ + #define R_MFWD_FWFOBFV1C15_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C15_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWRFC0 ========================================================= */ + #define R_MFWD_FWRFC0_RFM_Pos (8UL) /*!< RFM (Bit 8) */ + #define R_MFWD_FWRFC0_RFM_Msk (0x100UL) /*!< RFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWRFC0_RFOV_Pos (16UL) /*!< RFOV (Bit 16) */ + #define R_MFWD_FWRFC0_RFOV_Msk (0xff0000UL) /*!< RFOV (Bitfield-Mask: 0xff) */ +/* ======================================================== FWRFC1 ========================================================= */ + #define R_MFWD_FWRFC1_RFM_Pos (8UL) /*!< RFM (Bit 8) */ + #define R_MFWD_FWRFC1_RFM_Msk (0x100UL) /*!< RFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWRFC1_RFOV_Pos (16UL) /*!< RFOV (Bit 16) */ + #define R_MFWD_FWRFC1_RFOV_Msk (0xff0000UL) /*!< RFOV (Bitfield-Mask: 0xff) */ +/* ======================================================== FWRFVC0 ======================================================== */ + #define R_MFWD_FWRFVC0_RFSV_Pos (0UL) /*!< RFSV (Bit 0) */ + #define R_MFWD_FWRFVC0_RFSV_Msk (0xffUL) /*!< RFSV (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWRFVC0_RFRV_Pos (16UL) /*!< RFRV (Bit 16) */ + #define R_MFWD_FWRFVC0_RFRV_Msk (0xf0000UL) /*!< RFRV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWRFVC1 ======================================================== */ + #define R_MFWD_FWRFVC1_RFSV_Pos (0UL) /*!< RFSV (Bit 0) */ + #define R_MFWD_FWRFVC1_RFSV_Msk (0xffUL) /*!< RFSV (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWRFVC1_RFRV_Pos (16UL) /*!< RFRV (Bit 16) */ + #define R_MFWD_FWRFVC1_RFRV_Msk (0xf0000UL) /*!< RFRV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC0 ========================================================= */ + #define R_MFWD_FWCFC0_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC0_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC0_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC0_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC1 ========================================================= */ + #define R_MFWD_FWCFC1_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC1_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC1_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC1_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC2 ========================================================= */ + #define R_MFWD_FWCFC2_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC2_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC2_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC2_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC3 ========================================================= */ + #define R_MFWD_FWCFC3_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC3_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC3_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC3_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC4 ========================================================= */ + #define R_MFWD_FWCFC4_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC4_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC4_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC4_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC5 ========================================================= */ + #define R_MFWD_FWCFC5_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC5_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC5_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC5_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC6 ========================================================= */ + #define R_MFWD_FWCFC6_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC6_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC6_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC6_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC7 ========================================================= */ + #define R_MFWD_FWCFC7_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC7_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC7_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC7_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC8 ========================================================= */ + #define R_MFWD_FWCFC8_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC8_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC8_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC8_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC9 ========================================================= */ + #define R_MFWD_FWCFC9_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC9_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC9_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC9_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC10 ======================================================== */ + #define R_MFWD_FWCFC10_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC10_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC10_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC10_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC11 ======================================================== */ + #define R_MFWD_FWCFC11_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC11_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC11_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC11_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC12 ======================================================== */ + #define R_MFWD_FWCFC12_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC12_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC12_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC12_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC13 ======================================================== */ + #define R_MFWD_FWCFC13_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC13_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC13_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC13_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC14 ======================================================== */ + #define R_MFWD_FWCFC14_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC14_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC14_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC14_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC15 ======================================================== */ + #define R_MFWD_FWCFC15_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC15_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC15_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC15_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCFMC00 ======================================================== */ + #define R_MFWD_FWCFMC00_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC00_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC00_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC00_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC10 ======================================================== */ + #define R_MFWD_FWCFMC10_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC10_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC10_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC10_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC20 ======================================================== */ + #define R_MFWD_FWCFMC20_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC20_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC20_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC20_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC30 ======================================================== */ + #define R_MFWD_FWCFMC30_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC30_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC30_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC30_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC40 ======================================================== */ + #define R_MFWD_FWCFMC40_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC40_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC40_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC40_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC50 ======================================================== */ + #define R_MFWD_FWCFMC50_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC50_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC50_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC50_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC60 ======================================================== */ + #define R_MFWD_FWCFMC60_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC60_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC60_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC60_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC70 ======================================================== */ + #define R_MFWD_FWCFMC70_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC70_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC70_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC70_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC80 ======================================================== */ + #define R_MFWD_FWCFMC80_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC80_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC80_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC80_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC90 ======================================================== */ + #define R_MFWD_FWCFMC90_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC90_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC90_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC90_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC100 ======================================================= */ + #define R_MFWD_FWCFMC100_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC100_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC100_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC100_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC110 ======================================================= */ + #define R_MFWD_FWCFMC110_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC110_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC110_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC110_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC120 ======================================================= */ + #define R_MFWD_FWCFMC120_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC120_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC120_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC120_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC130 ======================================================= */ + #define R_MFWD_FWCFMC130_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC130_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC130_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC130_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC140 ======================================================= */ + #define R_MFWD_FWCFMC140_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC140_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC140_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC140_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC150 ======================================================= */ + #define R_MFWD_FWCFMC150_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC150_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC150_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC150_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC01 ======================================================== */ + #define R_MFWD_FWCFMC01_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC01_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC01_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC01_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC11 ======================================================== */ + #define R_MFWD_FWCFMC11_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC11_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC11_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC11_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC21 ======================================================== */ + #define R_MFWD_FWCFMC21_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC21_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC21_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC21_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC31 ======================================================== */ + #define R_MFWD_FWCFMC31_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC31_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC31_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC31_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC41 ======================================================== */ + #define R_MFWD_FWCFMC41_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC41_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC41_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC41_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC51 ======================================================== */ + #define R_MFWD_FWCFMC51_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC51_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC51_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC51_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC61 ======================================================== */ + #define R_MFWD_FWCFMC61_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC61_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC61_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC61_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC71 ======================================================== */ + #define R_MFWD_FWCFMC71_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC71_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC71_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC71_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC81 ======================================================== */ + #define R_MFWD_FWCFMC81_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC81_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC81_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC81_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC91 ======================================================== */ + #define R_MFWD_FWCFMC91_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC91_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC91_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC91_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC101 ======================================================= */ + #define R_MFWD_FWCFMC101_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC101_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC101_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC101_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC111 ======================================================= */ + #define R_MFWD_FWCFMC111_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC111_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC111_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC111_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC121 ======================================================= */ + #define R_MFWD_FWCFMC121_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC121_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC121_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC121_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC131 ======================================================= */ + #define R_MFWD_FWCFMC131_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC131_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC131_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC131_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC141 ======================================================= */ + #define R_MFWD_FWCFMC141_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC141_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC141_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC141_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC151 ======================================================= */ + #define R_MFWD_FWCFMC151_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC151_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC151_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC151_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC02 ======================================================== */ + #define R_MFWD_FWCFMC02_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC02_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC02_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC02_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC12 ======================================================== */ + #define R_MFWD_FWCFMC12_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC12_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC12_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC12_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC22 ======================================================== */ + #define R_MFWD_FWCFMC22_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC22_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC22_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC22_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC32 ======================================================== */ + #define R_MFWD_FWCFMC32_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC32_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC32_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC32_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC42 ======================================================== */ + #define R_MFWD_FWCFMC42_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC42_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC42_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC42_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC52 ======================================================== */ + #define R_MFWD_FWCFMC52_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC52_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC52_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC52_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC62 ======================================================== */ + #define R_MFWD_FWCFMC62_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC62_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC62_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC62_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC72 ======================================================== */ + #define R_MFWD_FWCFMC72_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC72_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC72_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC72_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC82 ======================================================== */ + #define R_MFWD_FWCFMC82_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC82_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC82_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC82_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC92 ======================================================== */ + #define R_MFWD_FWCFMC92_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC92_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC92_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC92_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC102 ======================================================= */ + #define R_MFWD_FWCFMC102_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC102_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC102_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC102_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC112 ======================================================= */ + #define R_MFWD_FWCFMC112_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC112_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC112_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC112_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC122 ======================================================= */ + #define R_MFWD_FWCFMC122_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC122_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC122_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC122_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC132 ======================================================= */ + #define R_MFWD_FWCFMC132_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC132_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC132_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC132_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC142 ======================================================= */ + #define R_MFWD_FWCFMC142_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC142_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC142_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC142_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC152 ======================================================= */ + #define R_MFWD_FWCFMC152_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC152_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC152_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC152_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC03 ======================================================== */ + #define R_MFWD_FWCFMC03_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC03_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC03_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC03_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC13 ======================================================== */ + #define R_MFWD_FWCFMC13_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC13_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC13_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC13_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC23 ======================================================== */ + #define R_MFWD_FWCFMC23_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC23_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC23_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC23_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC33 ======================================================== */ + #define R_MFWD_FWCFMC33_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC33_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC33_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC33_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC43 ======================================================== */ + #define R_MFWD_FWCFMC43_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC43_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC43_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC43_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC53 ======================================================== */ + #define R_MFWD_FWCFMC53_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC53_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC53_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC53_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC63 ======================================================== */ + #define R_MFWD_FWCFMC63_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC63_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC63_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC63_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC73 ======================================================== */ + #define R_MFWD_FWCFMC73_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC73_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC73_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC73_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC83 ======================================================== */ + #define R_MFWD_FWCFMC83_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC83_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC83_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC83_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC93 ======================================================== */ + #define R_MFWD_FWCFMC93_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC93_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC93_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC93_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC103 ======================================================= */ + #define R_MFWD_FWCFMC103_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC103_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC103_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC103_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC113 ======================================================= */ + #define R_MFWD_FWCFMC113_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC113_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC113_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC113_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC123 ======================================================= */ + #define R_MFWD_FWCFMC123_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC123_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC123_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC123_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC133 ======================================================= */ + #define R_MFWD_FWCFMC133_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC133_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC133_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC133_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC143 ======================================================= */ + #define R_MFWD_FWCFMC143_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC143_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC143_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC143_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC153 ======================================================= */ + #define R_MFWD_FWCFMC153_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC153_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC153_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC153_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC04 ======================================================== */ + #define R_MFWD_FWCFMC04_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC04_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC04_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC04_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC14 ======================================================== */ + #define R_MFWD_FWCFMC14_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC14_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC14_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC14_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC24 ======================================================== */ + #define R_MFWD_FWCFMC24_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC24_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC24_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC24_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC34 ======================================================== */ + #define R_MFWD_FWCFMC34_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC34_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC34_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC34_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC44 ======================================================== */ + #define R_MFWD_FWCFMC44_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC44_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC44_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC44_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC54 ======================================================== */ + #define R_MFWD_FWCFMC54_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC54_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC54_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC54_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC64 ======================================================== */ + #define R_MFWD_FWCFMC64_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC64_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC64_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC64_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC74 ======================================================== */ + #define R_MFWD_FWCFMC74_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC74_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC74_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC74_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC84 ======================================================== */ + #define R_MFWD_FWCFMC84_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC84_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC84_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC84_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC94 ======================================================== */ + #define R_MFWD_FWCFMC94_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC94_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC94_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC94_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC104 ======================================================= */ + #define R_MFWD_FWCFMC104_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC104_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC104_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC104_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC114 ======================================================= */ + #define R_MFWD_FWCFMC114_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC114_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC114_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC114_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC124 ======================================================= */ + #define R_MFWD_FWCFMC124_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC124_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC124_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC124_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC134 ======================================================= */ + #define R_MFWD_FWCFMC134_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC134_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC134_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC134_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC144 ======================================================= */ + #define R_MFWD_FWCFMC144_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC144_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC144_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC144_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC154 ======================================================= */ + #define R_MFWD_FWCFMC154_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC154_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC154_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC154_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC05 ======================================================== */ + #define R_MFWD_FWCFMC05_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC05_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC05_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC05_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC15 ======================================================== */ + #define R_MFWD_FWCFMC15_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC15_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC15_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC15_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC25 ======================================================== */ + #define R_MFWD_FWCFMC25_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC25_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC25_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC25_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC35 ======================================================== */ + #define R_MFWD_FWCFMC35_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC35_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC35_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC35_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC45 ======================================================== */ + #define R_MFWD_FWCFMC45_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC45_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC45_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC45_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC55 ======================================================== */ + #define R_MFWD_FWCFMC55_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC55_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC55_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC55_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC65 ======================================================== */ + #define R_MFWD_FWCFMC65_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC65_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC65_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC65_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC75 ======================================================== */ + #define R_MFWD_FWCFMC75_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC75_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC75_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC75_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC85 ======================================================== */ + #define R_MFWD_FWCFMC85_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC85_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC85_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC85_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC95 ======================================================== */ + #define R_MFWD_FWCFMC95_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC95_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC95_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC95_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC105 ======================================================= */ + #define R_MFWD_FWCFMC105_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC105_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC105_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC105_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC115 ======================================================= */ + #define R_MFWD_FWCFMC115_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC115_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC115_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC115_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC125 ======================================================= */ + #define R_MFWD_FWCFMC125_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC125_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC125_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC125_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC135 ======================================================= */ + #define R_MFWD_FWCFMC135_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC135_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC135_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC135_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC145 ======================================================= */ + #define R_MFWD_FWCFMC145_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC145_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC145_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC145_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC155 ======================================================= */ + #define R_MFWD_FWCFMC155_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC155_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC155_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC155_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC06 ======================================================== */ + #define R_MFWD_FWCFMC06_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC06_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC06_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC06_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC16 ======================================================== */ + #define R_MFWD_FWCFMC16_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC16_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC16_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC16_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC26 ======================================================== */ + #define R_MFWD_FWCFMC26_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC26_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC26_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC26_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC36 ======================================================== */ + #define R_MFWD_FWCFMC36_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC36_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC36_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC36_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC46 ======================================================== */ + #define R_MFWD_FWCFMC46_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC46_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC46_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC46_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC56 ======================================================== */ + #define R_MFWD_FWCFMC56_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC56_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC56_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC56_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC66 ======================================================== */ + #define R_MFWD_FWCFMC66_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC66_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC66_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC66_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC76 ======================================================== */ + #define R_MFWD_FWCFMC76_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC76_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC76_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC76_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC86 ======================================================== */ + #define R_MFWD_FWCFMC86_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC86_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC86_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC86_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC96 ======================================================== */ + #define R_MFWD_FWCFMC96_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC96_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC96_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC96_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC106 ======================================================= */ + #define R_MFWD_FWCFMC106_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC106_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC106_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC106_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC116 ======================================================= */ + #define R_MFWD_FWCFMC116_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC116_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC116_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC116_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC126 ======================================================= */ + #define R_MFWD_FWCFMC126_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC126_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC126_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC126_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC136 ======================================================= */ + #define R_MFWD_FWCFMC136_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC136_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC136_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC136_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC146 ======================================================= */ + #define R_MFWD_FWCFMC146_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC146_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC146_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC146_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC156 ======================================================= */ + #define R_MFWD_FWCFMC156_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC156_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC156_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC156_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP4SC ======================================================== */ + #define R_MFWD_FWIP4SC_IP4IMDH_Pos (0UL) /*!< IP4IMDH (Bit 0) */ + #define R_MFWD_FWIP4SC_IP4IMDH_Msk (0x1UL) /*!< IP4IMDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IMSH_Pos (1UL) /*!< IP4IMSH (Bit 1) */ + #define R_MFWD_FWIP4SC_IP4IMSH_Msk (0x2UL) /*!< IP4IMSH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISVH_Pos (2UL) /*!< IP4ISVH (Bit 2) */ + #define R_MFWD_FWIP4SC_IP4ISVH_Msk (0x4UL) /*!< IP4ISVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPH_Pos (3UL) /*!< IP4ISPH (Bit 3) */ + #define R_MFWD_FWIP4SC_IP4ISPH_Msk (0x8UL) /*!< IP4ISPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISDH_Pos (4UL) /*!< IP4ISDH (Bit 4) */ + #define R_MFWD_FWIP4SC_IP4ISDH_Msk (0x10UL) /*!< IP4ISDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICVH_Pos (5UL) /*!< IP4ICVH (Bit 5) */ + #define R_MFWD_FWIP4SC_IP4ICVH_Msk (0x20UL) /*!< IP4ICVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICPH_Pos (6UL) /*!< IP4ICPH (Bit 6) */ + #define R_MFWD_FWIP4SC_IP4ICPH_Msk (0x40UL) /*!< IP4ICPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICDH_Pos (7UL) /*!< IP4ICDH (Bit 7) */ + #define R_MFWD_FWIP4SC_IP4ICDH_Msk (0x80UL) /*!< IP4ICDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IISH_Pos (8UL) /*!< IP4IISH (Bit 8) */ + #define R_MFWD_FWIP4SC_IP4IISH_Msk (0x100UL) /*!< IP4IISH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IIDH_Pos (9UL) /*!< IP4IIDH (Bit 9) */ + #define R_MFWD_FWIP4SC_IP4IIDH_Msk (0x200UL) /*!< IP4IIDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IPH_Pos (10UL) /*!< IP4IPH (Bit 10) */ + #define R_MFWD_FWIP4SC_IP4IPH_Msk (0x400UL) /*!< IP4IPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPTH_Pos (11UL) /*!< IP4ISPTH (Bit 11) */ + #define R_MFWD_FWIP4SC_IP4ISPTH_Msk (0x800UL) /*!< IP4ISPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IDPTH_Pos (12UL) /*!< IP4IDPTH (Bit 12) */ + #define R_MFWD_FWIP4SC_IP4IDPTH_Msk (0x1000UL) /*!< IP4IDPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISVS_Pos (16UL) /*!< IP4ISVS (Bit 16) */ + #define R_MFWD_FWIP4SC_IP4ISVS_Msk (0x10000UL) /*!< IP4ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPS_Pos (17UL) /*!< IP4ISPS (Bit 17) */ + #define R_MFWD_FWIP4SC_IP4ISPS_Msk (0x20000UL) /*!< IP4ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISDS_Pos (18UL) /*!< IP4ISDS (Bit 18) */ + #define R_MFWD_FWIP4SC_IP4ISDS_Msk (0x40000UL) /*!< IP4ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICVS_Pos (19UL) /*!< IP4ICVS (Bit 19) */ + #define R_MFWD_FWIP4SC_IP4ICVS_Msk (0x80000UL) /*!< IP4ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICPS_Pos (20UL) /*!< IP4ICPS (Bit 20) */ + #define R_MFWD_FWIP4SC_IP4ICPS_Msk (0x100000UL) /*!< IP4ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICDS_Pos (21UL) /*!< IP4ICDS (Bit 21) */ + #define R_MFWD_FWIP4SC_IP4ICDS_Msk (0x200000UL) /*!< IP4ICDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IISS_Pos (22UL) /*!< IP4IISS (Bit 22) */ + #define R_MFWD_FWIP4SC_IP4IISS_Msk (0x400000UL) /*!< IP4IISS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IIDS_Pos (23UL) /*!< IP4IIDS (Bit 23) */ + #define R_MFWD_FWIP4SC_IP4IIDS_Msk (0x800000UL) /*!< IP4IIDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IDPTS_Pos (24UL) /*!< IP4IDPTS (Bit 24) */ + #define R_MFWD_FWIP4SC_IP4IDPTS_Msk (0x1000000UL) /*!< IP4IDPTS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP6SC ======================================================== */ + #define R_MFWD_FWIP6SC_IP6IMDH_Pos (0UL) /*!< IP6IMDH (Bit 0) */ + #define R_MFWD_FWIP6SC_IP6IMDH_Msk (0x1UL) /*!< IP6IMDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IMSH_Pos (1UL) /*!< IP6IMSH (Bit 1) */ + #define R_MFWD_FWIP6SC_IP6IMSH_Msk (0x2UL) /*!< IP6IMSH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISVH_Pos (2UL) /*!< IP6ISVH (Bit 2) */ + #define R_MFWD_FWIP6SC_IP6ISVH_Msk (0x4UL) /*!< IP6ISVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPH_Pos (3UL) /*!< IP6ISPH (Bit 3) */ + #define R_MFWD_FWIP6SC_IP6ISPH_Msk (0x8UL) /*!< IP6ISPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISDH_Pos (4UL) /*!< IP6ISDH (Bit 4) */ + #define R_MFWD_FWIP6SC_IP6ISDH_Msk (0x10UL) /*!< IP6ISDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICVH_Pos (5UL) /*!< IP6ICVH (Bit 5) */ + #define R_MFWD_FWIP6SC_IP6ICVH_Msk (0x20UL) /*!< IP6ICVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICPH_Pos (6UL) /*!< IP6ICPH (Bit 6) */ + #define R_MFWD_FWIP6SC_IP6ICPH_Msk (0x40UL) /*!< IP6ICPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICDH_Pos (7UL) /*!< IP6ICDH (Bit 7) */ + #define R_MFWD_FWIP6SC_IP6ICDH_Msk (0x80UL) /*!< IP6ICDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IISH_Pos (8UL) /*!< IP6IISH (Bit 8) */ + #define R_MFWD_FWIP6SC_IP6IISH_Msk (0x100UL) /*!< IP6IISH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IIDH_Pos (9UL) /*!< IP6IIDH (Bit 9) */ + #define R_MFWD_FWIP6SC_IP6IIDH_Msk (0x200UL) /*!< IP6IIDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IPH_Pos (10UL) /*!< IP6IPH (Bit 10) */ + #define R_MFWD_FWIP6SC_IP6IPH_Msk (0x400UL) /*!< IP6IPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPTH_Pos (11UL) /*!< IP6ISPTH (Bit 11) */ + #define R_MFWD_FWIP6SC_IP6ISPTH_Msk (0x800UL) /*!< IP6ISPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IDPTH_Pos (12UL) /*!< IP6IDPTH (Bit 12) */ + #define R_MFWD_FWIP6SC_IP6IDPTH_Msk (0x1000UL) /*!< IP6IDPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISVS_Pos (16UL) /*!< IP6ISVS (Bit 16) */ + #define R_MFWD_FWIP6SC_IP6ISVS_Msk (0x10000UL) /*!< IP6ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPS_Pos (17UL) /*!< IP6ISPS (Bit 17) */ + #define R_MFWD_FWIP6SC_IP6ISPS_Msk (0x20000UL) /*!< IP6ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISDS_Pos (18UL) /*!< IP6ISDS (Bit 18) */ + #define R_MFWD_FWIP6SC_IP6ISDS_Msk (0x40000UL) /*!< IP6ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICVS_Pos (19UL) /*!< IP6ICVS (Bit 19) */ + #define R_MFWD_FWIP6SC_IP6ICVS_Msk (0x80000UL) /*!< IP6ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICPS_Pos (20UL) /*!< IP6ICPS (Bit 20) */ + #define R_MFWD_FWIP6SC_IP6ICPS_Msk (0x100000UL) /*!< IP6ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICDS_Pos (21UL) /*!< IP6ICDS (Bit 21) */ + #define R_MFWD_FWIP6SC_IP6ICDS_Msk (0x200000UL) /*!< IP6ICDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6II0S_Pos (22UL) /*!< IP6II0S (Bit 22) */ + #define R_MFWD_FWIP6SC_IP6II0S_Msk (0x400000UL) /*!< IP6II0S (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6II1S_Pos (23UL) /*!< IP6II1S (Bit 23) */ + #define R_MFWD_FWIP6SC_IP6II1S_Msk (0x800000UL) /*!< IP6II1S (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IDPTS_Pos (24UL) /*!< IP6IDPTS (Bit 24) */ + #define R_MFWD_FWIP6SC_IP6IDPTS_Msk (0x1000000UL) /*!< IP6IDPTS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP6OC ======================================================== */ + #define R_MFWD_FWIP6OC_IP6IPOM_Pos (0UL) /*!< IP6IPOM (Bit 0) */ + #define R_MFWD_FWIP6OC_IP6IPOM_Msk (0x1UL) /*!< IP6IPOM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6OC_IP6IPO_Pos (4UL) /*!< IP6IPO (Bit 4) */ + #define R_MFWD_FWIP6OC_IP6IPO_Msk (0xf0UL) /*!< IP6IPO (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWL2SC ========================================================= */ + #define R_MFWD_FWL2SC_L2IMDS_Pos (0UL) /*!< L2IMDS (Bit 0) */ + #define R_MFWD_FWL2SC_L2IMDS_Msk (0x1UL) /*!< L2IMDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2IMSS_Pos (1UL) /*!< L2IMSS (Bit 1) */ + #define R_MFWD_FWL2SC_L2IMSS_Msk (0x2UL) /*!< L2IMSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISVS_Pos (2UL) /*!< L2ISVS (Bit 2) */ + #define R_MFWD_FWL2SC_L2ISVS_Msk (0x4UL) /*!< L2ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISPS_Pos (3UL) /*!< L2ISPS (Bit 3) */ + #define R_MFWD_FWL2SC_L2ISPS_Msk (0x8UL) /*!< L2ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISDS_Pos (4UL) /*!< L2ISDS (Bit 4) */ + #define R_MFWD_FWL2SC_L2ISDS_Msk (0x10UL) /*!< L2ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICVS_Pos (5UL) /*!< L2ICVS (Bit 5) */ + #define R_MFWD_FWL2SC_L2ICVS_Msk (0x20UL) /*!< L2ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICPS_Pos (6UL) /*!< L2ICPS (Bit 6) */ + #define R_MFWD_FWL2SC_L2ICPS_Msk (0x40UL) /*!< L2ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICDS_Pos (7UL) /*!< L2ICDS (Bit 7) */ + #define R_MFWD_FWL2SC_L2ICDS_Msk (0x80UL) /*!< L2ICDS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWSFHEC ======================================================== */ + #define R_MFWD_FWSFHEC_IP4HE_Pos (0UL) /*!< IP4HE (Bit 0) */ + #define R_MFWD_FWSFHEC_IP4HE_Msk (0xffffUL) /*!< IP4HE (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSFHEC_IP6HE_Pos (16UL) /*!< IP6HE (Bit 16) */ + #define R_MFWD_FWSFHEC_IP6HE_Msk (0xffff0000UL) /*!< IP6HE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCR0 ======================================================== */ + #define R_MFWD_FWSHCR0_SHCMDP0_Pos (0UL) /*!< SHCMDP0 (Bit 0) */ + #define R_MFWD_FWSHCR0_SHCMDP0_Msk (0xffffffffUL) /*!< SHCMDP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR1 ======================================================== */ + #define R_MFWD_FWSHCR1_SHCMSP0_Pos (0UL) /*!< SHCMSP0 (Bit 0) */ + #define R_MFWD_FWSHCR1_SHCMSP0_Msk (0xffffUL) /*!< SHCMSP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCR1_SHCMDP1_Pos (16UL) /*!< SHCMDP1 (Bit 16) */ + #define R_MFWD_FWSHCR1_SHCMDP1_Msk (0xffff0000UL) /*!< SHCMDP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCR2 ======================================================== */ + #define R_MFWD_FWSHCR2_SHCMSP1_Pos (0UL) /*!< SHCMSP1 (Bit 0) */ + #define R_MFWD_FWSHCR2_SHCMSP1_Msk (0xffffffffUL) /*!< SHCMSP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR3 ======================================================== */ + #define R_MFWD_FWSHCR3_SHCCV_Pos (0UL) /*!< SHCCV (Bit 0) */ + #define R_MFWD_FWSHCR3_SHCCV_Msk (0xfffUL) /*!< SHCCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWSHCR3_SHCCD_Pos (12UL) /*!< SHCCD (Bit 12) */ + #define R_MFWD_FWSHCR3_SHCCD_Msk (0x1000UL) /*!< SHCCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSHCR3_SHCCP_Pos (13UL) /*!< SHCCP (Bit 13) */ + #define R_MFWD_FWSHCR3_SHCCP_Msk (0xe000UL) /*!< SHCCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWSHCR3_SHCSV_Pos (16UL) /*!< SHCSV (Bit 16) */ + #define R_MFWD_FWSHCR3_SHCSV_Msk (0xfff0000UL) /*!< SHCSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWSHCR3_SHCSD_Pos (28UL) /*!< SHCSD (Bit 28) */ + #define R_MFWD_FWSHCR3_SHCSD_Msk (0x10000000UL) /*!< SHCSD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSHCR3_SHCSP_Pos (29UL) /*!< SHCSP (Bit 29) */ + #define R_MFWD_FWSHCR3_SHCSP_Msk (0xe0000000UL) /*!< SHCSP (Bitfield-Mask: 0x07) */ +/* ======================================================== FWSHCR4 ======================================================== */ + #define R_MFWD_FWSHCR4_SHCP_Pos (0UL) /*!< SHCP (Bit 0) */ + #define R_MFWD_FWSHCR4_SHCP_Msk (0xffUL) /*!< SHCP (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSHCR4_SHCFF_Pos (16UL) /*!< SHCFF (Bit 16) */ + #define R_MFWD_FWSHCR4_SHCFF_Msk (0x10000UL) /*!< SHCFF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWSHCR5 ======================================================== */ + #define R_MFWD_FWSHCR5_SHCISP0_Pos (0UL) /*!< SHCISP0 (Bit 0) */ + #define R_MFWD_FWSHCR5_SHCISP0_Msk (0xffffffffUL) /*!< SHCISP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR6 ======================================================== */ + #define R_MFWD_FWSHCR6_SHCISP1_Pos (0UL) /*!< SHCISP1 (Bit 0) */ + #define R_MFWD_FWSHCR6_SHCISP1_Msk (0xffffffffUL) /*!< SHCISP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR7 ======================================================== */ + #define R_MFWD_FWSHCR7_SHCISP2_Pos (0UL) /*!< SHCISP2 (Bit 0) */ + #define R_MFWD_FWSHCR7_SHCISP2_Msk (0xffffffffUL) /*!< SHCISP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR8 ======================================================== */ + #define R_MFWD_FWSHCR8_SHCISP3_Pos (0UL) /*!< SHCISP3 (Bit 0) */ + #define R_MFWD_FWSHCR8_SHCISP3_Msk (0xffffffffUL) /*!< SHCISP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR9 ======================================================== */ + #define R_MFWD_FWSHCR9_SHCIDP0_Pos (0UL) /*!< SHCIDP0 (Bit 0) */ + #define R_MFWD_FWSHCR9_SHCIDP0_Msk (0xffffffffUL) /*!< SHCIDP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR10 ======================================================== */ + #define R_MFWD_FWSHCR10_SHCIDP1_Pos (0UL) /*!< SHCIDP1 (Bit 0) */ + #define R_MFWD_FWSHCR10_SHCIDP1_Msk (0xffffffffUL) /*!< SHCIDP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR11 ======================================================== */ + #define R_MFWD_FWSHCR11_SHCIDP2_Pos (0UL) /*!< SHCIDP2 (Bit 0) */ + #define R_MFWD_FWSHCR11_SHCIDP2_Msk (0xffffffffUL) /*!< SHCIDP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR12 ======================================================== */ + #define R_MFWD_FWSHCR12_SHCIDP3_Pos (0UL) /*!< SHCIDP3 (Bit 0) */ + #define R_MFWD_FWSHCR12_SHCIDP3_Msk (0xffffffffUL) /*!< SHCIDP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR13 ======================================================== */ + #define R_MFWD_FWSHCR13_SHCDP_Pos (0UL) /*!< SHCDP (Bit 0) */ + #define R_MFWD_FWSHCR13_SHCDP_Msk (0xffffUL) /*!< SHCDP (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCR13_SHCSP_Pos (16UL) /*!< SHCSP (Bit 16) */ + #define R_MFWD_FWSHCR13_SHCSP_Msk (0xffff0000UL) /*!< SHCSP (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCRR ======================================================== */ + #define R_MFWD_FWSHCRR_SHCR_Pos (0UL) /*!< SHCR (Bit 0) */ + #define R_MFWD_FWSHCRR_SHCR_Msk (0xffffUL) /*!< SHCR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCRR_SHC_Pos (31UL) /*!< SHC (Bit 31) */ + #define R_MFWD_FWSHCRR_SHC_Msk (0x80000000UL) /*!< SHC (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHHEC ======================================================== */ + #define R_MFWD_FWLTHHEC_LTHHMC_Pos (0UL) /*!< LTHHMC (Bit 0) */ + #define R_MFWD_FWLTHHEC_LTHHMC_Msk (0x3ffUL) /*!< LTHHMC (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHHEC_LTHHMUE_Pos (16UL) /*!< LTHHMUE (Bit 16) */ + #define R_MFWD_FWLTHHEC_LTHHMUE_Msk (0x7ff0000UL) /*!< LTHHMUE (Bitfield-Mask: 0x7ff) */ +/* ======================================================== FWLTHHC ======================================================== */ + #define R_MFWD_FWLTHHC_LTHHE_Pos (0UL) /*!< LTHHE (Bit 0) */ + #define R_MFWD_FWLTHHC_LTHHE_Msk (0x3ffUL) /*!< LTHHE (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWLTHTL0 ======================================================== */ + #define R_MFWD_FWLTHTL0_LTHSLP0_Pos (0UL) /*!< LTHSLP0 (Bit 0) */ + #define R_MFWD_FWLTHTL0_LTHSLP0_Msk (0x7UL) /*!< LTHSLP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTL0_LTHSLL_Pos (8UL) /*!< LTHSLL (Bit 8) */ + #define R_MFWD_FWLTHTL0_LTHSLL_Msk (0x100UL) /*!< LTHSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL0_LTHED_Pos (16UL) /*!< LTHED (Bit 16) */ + #define R_MFWD_FWLTHTL0_LTHED_Msk (0x10000UL) /*!< LTHED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL1 ======================================================== */ + #define R_MFWD_FWLTHTL1_LTHSLP1_Pos (0UL) /*!< LTHSLP1 (Bit 0) */ + #define R_MFWD_FWLTHTL1_LTHSLP1_Msk (0xffffffffUL) /*!< LTHSLP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL2 ======================================================== */ + #define R_MFWD_FWLTHTL2_LTHSLP2_Pos (0UL) /*!< LTHSLP2 (Bit 0) */ + #define R_MFWD_FWLTHTL2_LTHSLP2_Msk (0xffffffffUL) /*!< LTHSLP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL3 ======================================================== */ + #define R_MFWD_FWLTHTL3_LTHSLP3_Pos (0UL) /*!< LTHSLP3 (Bit 0) */ + #define R_MFWD_FWLTHTL3_LTHSLP3_Msk (0xffffffffUL) /*!< LTHSLP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL4 ======================================================== */ + #define R_MFWD_FWLTHTL4_LTHSLP4_Pos (0UL) /*!< LTHSLP4 (Bit 0) */ + #define R_MFWD_FWLTHTL4_LTHSLP4_Msk (0xffffffffUL) /*!< LTHSLP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL5 ======================================================== */ + #define R_MFWD_FWLTHTL5_LTHMSDUNL_Pos (16UL) /*!< LTHMSDUNL (Bit 16) */ + #define R_MFWD_FWLTHTL5_LTHMSDUNL_Msk (0xf0000UL) /*!< LTHMSDUNL (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTL5_LTHMSDUVL_Pos (31UL) /*!< LTHMSDUVL (Bit 31) */ + #define R_MFWD_FWLTHTL5_LTHMSDUVL_Msk (0x80000000UL) /*!< LTHMSDUVL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL6 ======================================================== */ + #define R_MFWD_FWLTHTL6_LTHFRERNL_Pos (0UL) /*!< LTHFRERNL (Bit 0) */ + #define R_MFWD_FWLTHTL6_LTHFRERNL_Msk (0x7fUL) /*!< LTHFRERNL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTL6_LTHFRERVL_Pos (15UL) /*!< LTHFRERVL (Bit 15) */ + #define R_MFWD_FWLTHTL6_LTHFRERVL_Msk (0x8000UL) /*!< LTHFRERVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL6_LTHMTRNL_Pos (16UL) /*!< LTHMTRNL (Bit 16) */ + #define R_MFWD_FWLTHTL6_LTHMTRNL_Msk (0x1f0000UL) /*!< LTHMTRNL (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTL6_LTHMTRVL_Pos (31UL) /*!< LTHMTRVL (Bit 31) */ + #define R_MFWD_FWLTHTL6_LTHMTRVL_Msk (0x80000000UL) /*!< LTHMTRVL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL7 ======================================================== */ + #define R_MFWD_FWLTHTL7_LTHRNL_Pos (0UL) /*!< LTHRNL (Bit 0) */ + #define R_MFWD_FWLTHTL7_LTHRNL_Msk (0xffUL) /*!< LTHRNL (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTL7_LTHRVL_Pos (15UL) /*!< LTHRVL (Bit 15) */ + #define R_MFWD_FWLTHTL7_LTHRVL_Msk (0x8000UL) /*!< LTHRVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL7_LTHSLVL_Pos (16UL) /*!< LTHSLVL (Bit 16) */ + #define R_MFWD_FWLTHTL7_LTHSLVL_Msk (0x7f0000UL) /*!< LTHSLVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTL80 ======================================================= */ + #define R_MFWD_FWLTHTL80_LTHCSDL_Pos (0UL) /*!< LTHCSDL (Bit 0) */ + #define R_MFWD_FWLTHTL80_LTHCSDL_Msk (0x7fUL) /*!< LTHCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTL9 ======================================================== */ + #define R_MFWD_FWLTHTL9_LTHDVL_Pos (0UL) /*!< LTHDVL (Bit 0) */ + #define R_MFWD_FWLTHTL9_LTHDVL_Msk (0x7fUL) /*!< LTHDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTL9_LTHIPVL_Pos (16UL) /*!< LTHIPVL (Bit 16) */ + #define R_MFWD_FWLTHTL9_LTHIPVL_Msk (0x70000UL) /*!< LTHIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTL9_LTHIPUL_Pos (19UL) /*!< LTHIPUL (Bit 19) */ + #define R_MFWD_FWLTHTL9_LTHIPUL_Msk (0x80000UL) /*!< LTHIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL9_LTHEMEL_Pos (20UL) /*!< LTHEMEL (Bit 20) */ + #define R_MFWD_FWLTHTL9_LTHEMEL_Msk (0x100000UL) /*!< LTHEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL9_LTHCMEL_Pos (21UL) /*!< LTHCMEL (Bit 21) */ + #define R_MFWD_FWLTHTL9_LTHCMEL_Msk (0x200000UL) /*!< LTHCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTLR ======================================================== */ + #define R_MFWD_FWLTHTLR_LTHLF_Pos (0UL) /*!< LTHLF (Bit 0) */ + #define R_MFWD_FWLTHTLR_LTHLF_Msk (0x1UL) /*!< LTHLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLSF_Pos (1UL) /*!< LTHLSF (Bit 1) */ + #define R_MFWD_FWLTHTLR_LTHLSF_Msk (0x2UL) /*!< LTHLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLEF_Pos (2UL) /*!< LTHLEF (Bit 2) */ + #define R_MFWD_FWLTHTLR_LTHLEF_Msk (0x4UL) /*!< LTHLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLO_Pos (3UL) /*!< LTHLO (Bit 3) */ + #define R_MFWD_FWLTHTLR_LTHLO_Msk (0x8UL) /*!< LTHLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLCN_Pos (16UL) /*!< LTHLCN (Bit 16) */ + #define R_MFWD_FWLTHTLR_LTHLCN_Msk (0x3ff0000UL) /*!< LTHLCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHTLR_LTHTL_Pos (31UL) /*!< LTHTL (Bit 31) */ + #define R_MFWD_FWLTHTLR_LTHTL_Msk (0x80000000UL) /*!< LTHTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTIM ======================================================== */ + #define R_MFWD_FWLTHTIM_LTHTIOG_Pos (0UL) /*!< LTHTIOG (Bit 0) */ + #define R_MFWD_FWLTHTIM_LTHTIOG_Msk (0x1UL) /*!< LTHTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTIM_LTHTR_Pos (1UL) /*!< LTHTR (Bit 1) */ + #define R_MFWD_FWLTHTIM_LTHTR_Msk (0x2UL) /*!< LTHTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTEM ======================================================== */ + #define R_MFWD_FWLTHTEM_LTHTEN_Pos (0UL) /*!< LTHTEN (Bit 0) */ + #define R_MFWD_FWLTHTEM_LTHTEN_Msk (0x7ffUL) /*!< LTHTEN (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWLTHTEM_LTHTUEN_Pos (16UL) /*!< LTHTUEN (Bit 16) */ + #define R_MFWD_FWLTHTEM_LTHTUEN_Msk (0x7ff0000UL) /*!< LTHTUEN (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWLTHTS0 ======================================================== */ + #define R_MFWD_FWLTHTS0_LTHSSP0_Pos (0UL) /*!< LTHSSP0 (Bit 0) */ + #define R_MFWD_FWLTHTS0_LTHSSP0_Msk (0x7UL) /*!< LTHSSP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTS0_LTHSSPFS_Pos (24UL) /*!< LTHSSPFS (Bit 24) */ + #define R_MFWD_FWLTHTS0_LTHSSPFS_Msk (0x1000000UL) /*!< LTHSSPFS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTS1 ======================================================== */ + #define R_MFWD_FWLTHTS1_LTHSSP1_Pos (0UL) /*!< LTHSSP1 (Bit 0) */ + #define R_MFWD_FWLTHTS1_LTHSSP1_Msk (0xffffffffUL) /*!< LTHSSP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS2 ======================================================== */ + #define R_MFWD_FWLTHTS2_LTHSSP2_Pos (0UL) /*!< LTHSSP2 (Bit 0) */ + #define R_MFWD_FWLTHTS2_LTHSSP2_Msk (0xffffffffUL) /*!< LTHSSP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS3 ======================================================== */ + #define R_MFWD_FWLTHTS3_LTHSSP3_Pos (0UL) /*!< LTHSSP3 (Bit 0) */ + #define R_MFWD_FWLTHTS3_LTHSSP3_Msk (0xffffffffUL) /*!< LTHSSP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS4 ======================================================== */ + #define R_MFWD_FWLTHTS4_LTHSSP4_Pos (0UL) /*!< LTHSSP4 (Bit 0) */ + #define R_MFWD_FWLTHTS4_LTHSSP4_Msk (0xffffffffUL) /*!< LTHSSP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTSR0 ======================================================= */ + #define R_MFWD_FWLTHTSR0_LTHSEF_Pos (0UL) /*!< LTHSEF (Bit 0) */ + #define R_MFWD_FWLTHTSR0_LTHSEF_Msk (0x1UL) /*!< LTHSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSNF_Pos (1UL) /*!< LTHSNF (Bit 1) */ + #define R_MFWD_FWLTHTSR0_LTHSNF_Msk (0x2UL) /*!< LTHSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSLS_Pos (8UL) /*!< LTHSLS (Bit 8) */ + #define R_MFWD_FWLTHTSR0_LTHSLS_Msk (0x100UL) /*!< LTHSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSCN_Pos (16UL) /*!< LTHSCN (Bit 16) */ + #define R_MFWD_FWLTHTSR0_LTHSCN_Msk (0x3ff0000UL) /*!< LTHSCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHTSR0_LTHTS_Pos (31UL) /*!< LTHTS (Bit 31) */ + #define R_MFWD_FWLTHTSR0_LTHTS_Msk (0x80000000UL) /*!< LTHTS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR1 ======================================================= */ + #define R_MFWD_FWLTHTSR1_LTHMSDUNS_Pos (16UL) /*!< LTHMSDUNS (Bit 16) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUNS_Msk (0xf0000UL) /*!< LTHMSDUNS (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUVS_Pos (31UL) /*!< LTHMSDUVS (Bit 31) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUVS_Msk (0x80000000UL) /*!< LTHMSDUVS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR2 ======================================================= */ + #define R_MFWD_FWLTHTSR2_LTHFRERNS_Pos (0UL) /*!< LTHFRERNS (Bit 0) */ + #define R_MFWD_FWLTHTSR2_LTHFRERNS_Msk (0x3fUL) /*!< LTHFRERNS (Bitfield-Mask: 0x3f) */ + #define R_MFWD_FWLTHTSR2_LTHFRERVS_Pos (15UL) /*!< LTHFRERVS (Bit 15) */ + #define R_MFWD_FWLTHTSR2_LTHFRERVS_Msk (0x8000UL) /*!< LTHFRERVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR2_LTHMTRNS_Pos (16UL) /*!< LTHMTRNS (Bit 16) */ + #define R_MFWD_FWLTHTSR2_LTHMTRNS_Msk (0x1f0000UL) /*!< LTHMTRNS (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTSR2_LTHMTRVS_Pos (31UL) /*!< LTHMTRVS (Bit 31) */ + #define R_MFWD_FWLTHTSR2_LTHMTRVS_Msk (0x80000000UL) /*!< LTHMTRVS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR3 ======================================================= */ + #define R_MFWD_FWLTHTSR3_LTHRNS_Pos (0UL) /*!< LTHRNS (Bit 0) */ + #define R_MFWD_FWLTHTSR3_LTHRNS_Msk (0xffUL) /*!< LTHRNS (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTSR3_LTHRVS_Pos (15UL) /*!< LTHRVS (Bit 15) */ + #define R_MFWD_FWLTHTSR3_LTHRVS_Msk (0x8000UL) /*!< LTHRVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR3_LTHSLVS_Pos (16UL) /*!< LTHSLVS (Bit 16) */ + #define R_MFWD_FWLTHTSR3_LTHSLVS_Msk (0x7f0000UL) /*!< LTHSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTSR40 ======================================================= */ + #define R_MFWD_FWLTHTSR40_LTHCSDS_Pos (0UL) /*!< LTHCSDS (Bit 0) */ + #define R_MFWD_FWLTHTSR40_LTHCSDS_Msk (0x7fUL) /*!< LTHCSDS (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTSR5 ======================================================= */ + #define R_MFWD_FWLTHTSR5_LTHDVS_Pos (0UL) /*!< LTHDVS (Bit 0) */ + #define R_MFWD_FWLTHTSR5_LTHDVS_Msk (0x7fUL) /*!< LTHDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTSR5_LTHIPVS_Pos (16UL) /*!< LTHIPVS (Bit 16) */ + #define R_MFWD_FWLTHTSR5_LTHIPVS_Msk (0x70000UL) /*!< LTHIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTSR5_LTHIPUS_Pos (19UL) /*!< LTHIPUS (Bit 19) */ + #define R_MFWD_FWLTHTSR5_LTHIPUS_Msk (0x80000UL) /*!< LTHIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR5_LTHEMES_Pos (20UL) /*!< LTHEMES (Bit 20) */ + #define R_MFWD_FWLTHTSR5_LTHEMES_Msk (0x100000UL) /*!< LTHEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR5_LTHCMES_Pos (21UL) /*!< LTHCMES (Bit 21) */ + #define R_MFWD_FWLTHTSR5_LTHCMES_Msk (0x200000UL) /*!< LTHCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWLTHTR ======================================================== */ + #define R_MFWD_FWLTHTR_LTHAR_Pos (0UL) /*!< LTHAR (Bit 0) */ + #define R_MFWD_FWLTHTR_LTHAR_Msk (0x3ffUL) /*!< LTHAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWLTHTRR0 ======================================================= */ + #define R_MFWD_FWLTHTRR0_LTHREF_Pos (0UL) /*!< LTHREF (Bit 0) */ + #define R_MFWD_FWLTHTRR0_LTHREF_Msk (0x1UL) /*!< LTHREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR0_LTHEVR_Pos (1UL) /*!< LTHEVR (Bit 1) */ + #define R_MFWD_FWLTHTRR0_LTHEVR_Msk (0x2UL) /*!< LTHEVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR0_LTHTR_Pos (31UL) /*!< LTHTR (Bit 31) */ + #define R_MFWD_FWLTHTRR0_LTHTR_Msk (0x80000000UL) /*!< LTHTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR1 ======================================================= */ + #define R_MFWD_FWLTHTRR1_LTHSRP0_Pos (0UL) /*!< LTHSRP0 (Bit 0) */ + #define R_MFWD_FWLTHTRR1_LTHSRP0_Msk (0x7UL) /*!< LTHSRP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTRR1_LTHSLR_Pos (8UL) /*!< LTHSLR (Bit 8) */ + #define R_MFWD_FWLTHTRR1_LTHSLR_Msk (0x100UL) /*!< LTHSLR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR2 ======================================================= */ + #define R_MFWD_FWLTHTRR2_LTHSRP1_Pos (0UL) /*!< LTHSRP1 (Bit 0) */ + #define R_MFWD_FWLTHTRR2_LTHSRP1_Msk (0xffffffffUL) /*!< LTHSRP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR3 ======================================================= */ + #define R_MFWD_FWLTHTRR3_LTHSRP2_Pos (0UL) /*!< LTHSRP2 (Bit 0) */ + #define R_MFWD_FWLTHTRR3_LTHSRP2_Msk (0xffffffffUL) /*!< LTHSRP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR4 ======================================================= */ + #define R_MFWD_FWLTHTRR4_LTHSRP3_Pos (0UL) /*!< LTHSRP3 (Bit 0) */ + #define R_MFWD_FWLTHTRR4_LTHSRP3_Msk (0xffffffffUL) /*!< LTHSRP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR5 ======================================================= */ + #define R_MFWD_FWLTHTRR5_LTHSRP4_Pos (0UL) /*!< LTHSRP4 (Bit 0) */ + #define R_MFWD_FWLTHTRR5_LTHSRP4_Msk (0xffffffffUL) /*!< LTHSRP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR6 ======================================================= */ + #define R_MFWD_FWLTHTRR6_LTHMSDUNR_Pos (16UL) /*!< LTHMSDUNR (Bit 16) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUNR_Msk (0xf0000UL) /*!< LTHMSDUNR (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUVR_Pos (31UL) /*!< LTHMSDUVR (Bit 31) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUVR_Msk (0x80000000UL) /*!< LTHMSDUVR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR7 ======================================================= */ + #define R_MFWD_FWLTHTRR7_LTHFRERNR_Pos (0UL) /*!< LTHFRERNR (Bit 0) */ + #define R_MFWD_FWLTHTRR7_LTHFRERNR_Msk (0x3fUL) /*!< LTHFRERNR (Bitfield-Mask: 0x3f) */ + #define R_MFWD_FWLTHTRR7_LTHFRERVR_Pos (15UL) /*!< LTHFRERVR (Bit 15) */ + #define R_MFWD_FWLTHTRR7_LTHFRERVR_Msk (0x8000UL) /*!< LTHFRERVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR7_LTHMTRNR_Pos (16UL) /*!< LTHMTRNR (Bit 16) */ + #define R_MFWD_FWLTHTRR7_LTHMTRNR_Msk (0x1f0000UL) /*!< LTHMTRNR (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTRR7_LTHMTRVR_Pos (31UL) /*!< LTHMTRVR (Bit 31) */ + #define R_MFWD_FWLTHTRR7_LTHMTRVR_Msk (0x80000000UL) /*!< LTHMTRVR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR8 ======================================================= */ + #define R_MFWD_FWLTHTRR8_LTHRNR_Pos (0UL) /*!< LTHRNR (Bit 0) */ + #define R_MFWD_FWLTHTRR8_LTHRNR_Msk (0xffUL) /*!< LTHRNR (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTRR8_LTHRVR_Pos (15UL) /*!< LTHRVR (Bit 15) */ + #define R_MFWD_FWLTHTRR8_LTHRVR_Msk (0x8000UL) /*!< LTHRVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR8_LTHSLVR_Pos (16UL) /*!< LTHSLVR (Bit 16) */ + #define R_MFWD_FWLTHTRR8_LTHSLVR_Msk (0x7f0000UL) /*!< LTHSLVR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTRR90 ======================================================= */ + #define R_MFWD_FWLTHTRR90_LTHCSDR_Pos (0UL) /*!< LTHCSDR (Bit 0) */ + #define R_MFWD_FWLTHTRR90_LTHCSDR_Msk (0x7fUL) /*!< LTHCSDR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTRR10 ======================================================= */ + #define R_MFWD_FWLTHTRR10_LTHDVR_Pos (0UL) /*!< LTHDVR (Bit 0) */ + #define R_MFWD_FWLTHTRR10_LTHDVR_Msk (0x7fUL) /*!< LTHDVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTRR10_LTHIPVR_Pos (16UL) /*!< LTHIPVR (Bit 16) */ + #define R_MFWD_FWLTHTRR10_LTHIPVR_Msk (0x70000UL) /*!< LTHIPVR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTRR10_LTHIPUR_Pos (19UL) /*!< LTHIPUR (Bit 19) */ + #define R_MFWD_FWLTHTRR10_LTHIPUR_Msk (0x80000UL) /*!< LTHIPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR10_LTHEMER_Pos (20UL) /*!< LTHEMER (Bit 20) */ + #define R_MFWD_FWLTHTRR10_LTHEMER_Msk (0x100000UL) /*!< LTHEMER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR10_LTHCMER_Pos (21UL) /*!< LTHCMER (Bit 21) */ + #define R_MFWD_FWLTHTRR10_LTHCMER_Msk (0x200000UL) /*!< LTHCMER (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACHEC ======================================================== */ + #define R_MFWD_FWMACHEC_MACHMC_Pos (0UL) /*!< MACHMC (Bit 0) */ + #define R_MFWD_FWMACHEC_MACHMC_Msk (0x7ffUL) /*!< MACHMC (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWMACHEC_MACHMUE_Pos (16UL) /*!< MACHMUE (Bit 16) */ + #define R_MFWD_FWMACHEC_MACHMUE_Msk (0xfff0000UL) /*!< MACHMUE (Bitfield-Mask: 0xfff) */ +/* ======================================================== FWMACHC ======================================================== */ + #define R_MFWD_FWMACHC_MACHE_Pos (0UL) /*!< MACHE (Bit 0) */ + #define R_MFWD_FWMACHC_MACHE_Msk (0x7ffUL) /*!< MACHE (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWMACTL0 ======================================================== */ + #define R_MFWD_FWMACTL0_MACSLL_Pos (8UL) /*!< MACSLL (Bit 8) */ + #define R_MFWD_FWMACTL0_MACSLL_Msk (0x100UL) /*!< MACSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACDEL_Pos (9UL) /*!< MACDEL (Bit 9) */ + #define R_MFWD_FWMACTL0_MACDEL_Msk (0x200UL) /*!< MACDEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACHLDL_Pos (10UL) /*!< MACHLDL (Bit 10) */ + #define R_MFWD_FWMACTL0_MACHLDL_Msk (0x400UL) /*!< MACHLDL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACED_Pos (16UL) /*!< MACED (Bit 16) */ + #define R_MFWD_FWMACTL0_MACED_Msk (0x10000UL) /*!< MACED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTL1 ======================================================== */ + #define R_MFWD_FWMACTL1_MACMALP0_Pos (0UL) /*!< MACMALP0 (Bit 0) */ + #define R_MFWD_FWMACTL1_MACMALP0_Msk (0xffffUL) /*!< MACMALP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTL2 ======================================================== */ + #define R_MFWD_FWMACTL2_MACMALP1_Pos (0UL) /*!< MACMALP1 (Bit 0) */ + #define R_MFWD_FWMACTL2_MACMALP1_Msk (0xffffffffUL) /*!< MACMALP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTL3 ======================================================== */ + #define R_MFWD_FWMACTL3_MACSSLVL_Pos (0UL) /*!< MACSSLVL (Bit 0) */ + #define R_MFWD_FWMACTL3_MACSSLVL_Msk (0x7fUL) /*!< MACSSLVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTL3_MACDSLVL_Pos (16UL) /*!< MACDSLVL (Bit 16) */ + #define R_MFWD_FWMACTL3_MACDSLVL_Msk (0x7f0000UL) /*!< MACDSLVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTL40 ======================================================= */ + #define R_MFWD_FWMACTL40_MACCSDL_Pos (0UL) /*!< MACCSDL (Bit 0) */ + #define R_MFWD_FWMACTL40_MACCSDL_Msk (0x7fUL) /*!< MACCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTL5 ======================================================== */ + #define R_MFWD_FWMACTL5_MACDVL_Pos (0UL) /*!< MACDVL (Bit 0) */ + #define R_MFWD_FWMACTL5_MACDVL_Msk (0x7fUL) /*!< MACDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTL5_MACIPVL_Pos (16UL) /*!< MACIPVL (Bit 16) */ + #define R_MFWD_FWMACTL5_MACIPVL_Msk (0x70000UL) /*!< MACIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTL5_MACIPUL_Pos (19UL) /*!< MACIPUL (Bit 19) */ + #define R_MFWD_FWMACTL5_MACIPUL_Msk (0x80000UL) /*!< MACIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL5_MACEMEL_Pos (20UL) /*!< MACEMEL (Bit 20) */ + #define R_MFWD_FWMACTL5_MACEMEL_Msk (0x100000UL) /*!< MACEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL5_MACCMEL_Pos (21UL) /*!< MACCMEL (Bit 21) */ + #define R_MFWD_FWMACTL5_MACCMEL_Msk (0x200000UL) /*!< MACCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTLR ======================================================== */ + #define R_MFWD_FWMACTLR_MACLF_Pos (0UL) /*!< MACLF (Bit 0) */ + #define R_MFWD_FWMACTLR_MACLF_Msk (0x1UL) /*!< MACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLSF_Pos (1UL) /*!< MACLSF (Bit 1) */ + #define R_MFWD_FWMACTLR_MACLSF_Msk (0x2UL) /*!< MACLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLEF_Pos (2UL) /*!< MACLEF (Bit 2) */ + #define R_MFWD_FWMACTLR_MACLEF_Msk (0x4UL) /*!< MACLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLO_Pos (3UL) /*!< MACLO (Bit 3) */ + #define R_MFWD_FWMACTLR_MACLO_Msk (0x8UL) /*!< MACLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLCN_Pos (16UL) /*!< MACLCN (Bit 16) */ + #define R_MFWD_FWMACTLR_MACLCN_Msk (0x3ff0000UL) /*!< MACLCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWMACTLR_MACTL_Pos (31UL) /*!< MACTL (Bit 31) */ + #define R_MFWD_FWMACTLR_MACTL_Msk (0x80000000UL) /*!< MACTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTIM ======================================================== */ + #define R_MFWD_FWMACTIM_MACTIOG_Pos (0UL) /*!< MACTIOG (Bit 0) */ + #define R_MFWD_FWMACTIM_MACTIOG_Msk (0x1UL) /*!< MACTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTIM_MACTR_Pos (1UL) /*!< MACTR (Bit 1) */ + #define R_MFWD_FWMACTIM_MACTR_Msk (0x2UL) /*!< MACTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTEM ======================================================== */ + #define R_MFWD_FWMACTEM_MACTEN_Pos (0UL) /*!< MACTEN (Bit 0) */ + #define R_MFWD_FWMACTEM_MACTEN_Msk (0x7ffUL) /*!< MACTEN (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWMACTEM_MACTUEN_Pos (16UL) /*!< MACTUEN (Bit 16) */ + #define R_MFWD_FWMACTEM_MACTUEN_Msk (0x7ff0000UL) /*!< MACTUEN (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWMACTS0 ======================================================== */ + #define R_MFWD_FWMACTS0_MACMASP0_Pos (0UL) /*!< MACMASP0 (Bit 0) */ + #define R_MFWD_FWMACTS0_MACMASP0_Msk (0xffffUL) /*!< MACMASP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTS1 ======================================================== */ + #define R_MFWD_FWMACTS1_MACMASP1_Pos (0UL) /*!< MACMASP1 (Bit 0) */ + #define R_MFWD_FWMACTS1_MACMASP1_Msk (0xffffffffUL) /*!< MACMASP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTSR0 ======================================================= */ + #define R_MFWD_FWMACTSR0_MACSEF_Pos (0UL) /*!< MACSEF (Bit 0) */ + #define R_MFWD_FWMACTSR0_MACSEF_Msk (0x1UL) /*!< MACSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSNF_Pos (1UL) /*!< MACSNF (Bit 1) */ + #define R_MFWD_FWMACTSR0_MACSNF_Msk (0x2UL) /*!< MACSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSLS_Pos (8UL) /*!< MACSLS (Bit 8) */ + #define R_MFWD_FWMACTSR0_MACSLS_Msk (0x100UL) /*!< MACSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACDES_Pos (9UL) /*!< MACDES (Bit 9) */ + #define R_MFWD_FWMACTSR0_MACDES_Msk (0x200UL) /*!< MACDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACHLDS_Pos (10UL) /*!< MACHLDS (Bit 10) */ + #define R_MFWD_FWMACTSR0_MACHLDS_Msk (0x400UL) /*!< MACHLDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSCN_Pos (16UL) /*!< MACSCN (Bit 16) */ + #define R_MFWD_FWMACTSR0_MACSCN_Msk (0x3ff0000UL) /*!< MACSCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWMACTSR0_MACTS_Pos (31UL) /*!< MACTS (Bit 31) */ + #define R_MFWD_FWMACTSR0_MACTS_Msk (0x80000000UL) /*!< MACTS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTSR1 ======================================================= */ + #define R_MFWD_FWMACTSR1_MACSSLVS_Pos (0UL) /*!< MACSSLVS (Bit 0) */ + #define R_MFWD_FWMACTSR1_MACSSLVS_Msk (0x7fUL) /*!< MACSSLVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTSR1_MACDSLVS_Pos (16UL) /*!< MACDSLVS (Bit 16) */ + #define R_MFWD_FWMACTSR1_MACDSLVS_Msk (0x7f0000UL) /*!< MACDSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWMACTSR20 ======================================================= */ + #define R_MFWD_FWMACTSR20_MACCSDS_Pos (0UL) /*!< MACCSDS (Bit 0) */ + #define R_MFWD_FWMACTSR20_MACCSDS_Msk (0x7fUL) /*!< MACCSDS (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTSR3 ======================================================= */ + #define R_MFWD_FWMACTSR3_MACDVS_Pos (0UL) /*!< MACDVS (Bit 0) */ + #define R_MFWD_FWMACTSR3_MACDVS_Msk (0x7fUL) /*!< MACDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTSR3_MACIPVS_Pos (16UL) /*!< MACIPVS (Bit 16) */ + #define R_MFWD_FWMACTSR3_MACIPVS_Msk (0x70000UL) /*!< MACIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTSR3_MACIPUS_Pos (19UL) /*!< MACIPUS (Bit 19) */ + #define R_MFWD_FWMACTSR3_MACIPUS_Msk (0x80000UL) /*!< MACIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR3_MACEMES_Pos (20UL) /*!< MACEMES (Bit 20) */ + #define R_MFWD_FWMACTSR3_MACEMES_Msk (0x100000UL) /*!< MACEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR3_MACCMES_Pos (21UL) /*!< MACCMES (Bit 21) */ + #define R_MFWD_FWMACTSR3_MACCMES_Msk (0x200000UL) /*!< MACCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMACTR ======================================================== */ + #define R_MFWD_FWMACTR_MACAR_Pos (0UL) /*!< MACAR (Bit 0) */ + #define R_MFWD_FWMACTR_MACAR_Msk (0x3ffUL) /*!< MACAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWMACTRR0 ======================================================= */ + #define R_MFWD_FWMACTRR0_MACEVR_Pos (0UL) /*!< MACEVR (Bit 0) */ + #define R_MFWD_FWMACTRR0_MACEVR_Msk (0x1UL) /*!< MACEVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR0_MACREF_Pos (1UL) /*!< MACREF (Bit 1) */ + #define R_MFWD_FWMACTRR0_MACREF_Msk (0x2UL) /*!< MACREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR0_MACTR_Pos (31UL) /*!< MACTR (Bit 31) */ + #define R_MFWD_FWMACTRR0_MACTR_Msk (0x80000000UL) /*!< MACTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTRR1 ======================================================= */ + #define R_MFWD_FWMACTRR1_MACSLR_Pos (8UL) /*!< MACSLR (Bit 8) */ + #define R_MFWD_FWMACTRR1_MACSLR_Msk (0x100UL) /*!< MACSLR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACDER_Pos (9UL) /*!< MACDER (Bit 9) */ + #define R_MFWD_FWMACTRR1_MACDER_Msk (0x200UL) /*!< MACDER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACHLDR_Pos (10UL) /*!< MACHLDR (Bit 10) */ + #define R_MFWD_FWMACTRR1_MACHLDR_Msk (0x400UL) /*!< MACHLDR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACABR_Pos (11UL) /*!< MACABR (Bit 11) */ + #define R_MFWD_FWMACTRR1_MACABR_Msk (0x800UL) /*!< MACABR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTRR2 ======================================================= */ + #define R_MFWD_FWMACTRR2_MACMARP0_Pos (0UL) /*!< MACMARP0 (Bit 0) */ + #define R_MFWD_FWMACTRR2_MACMARP0_Msk (0xffffUL) /*!< MACMARP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTRR3 ======================================================= */ + #define R_MFWD_FWMACTRR3_MACMARP1_Pos (0UL) /*!< MACMARP1 (Bit 0) */ + #define R_MFWD_FWMACTRR3_MACMARP1_Msk (0xffffffffUL) /*!< MACMARP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTRR4 ======================================================= */ + #define R_MFWD_FWMACTRR4_MACSSLVR_Pos (0UL) /*!< MACSSLVR (Bit 0) */ + #define R_MFWD_FWMACTRR4_MACSSLVR_Msk (0x7fUL) /*!< MACSSLVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTRR4_MACDSLVR_Pos (16UL) /*!< MACDSLVR (Bit 16) */ + #define R_MFWD_FWMACTRR4_MACDSLVR_Msk (0x7f0000UL) /*!< MACDSLVR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWMACTRR50 ======================================================= */ + #define R_MFWD_FWMACTRR50_MACCSDR_Pos (0UL) /*!< MACCSDR (Bit 0) */ + #define R_MFWD_FWMACTRR50_MACCSDR_Msk (0x7fUL) /*!< MACCSDR (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTRR6 ======================================================= */ + #define R_MFWD_FWMACTRR6_MACDVR_Pos (0UL) /*!< MACDVR (Bit 0) */ + #define R_MFWD_FWMACTRR6_MACDVR_Msk (0x7fUL) /*!< MACDVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTRR6_MACIPVR_Pos (16UL) /*!< MACIPVR (Bit 16) */ + #define R_MFWD_FWMACTRR6_MACIPVR_Msk (0x70000UL) /*!< MACIPVR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTRR6_MACIPUR_Pos (19UL) /*!< MACIPUR (Bit 19) */ + #define R_MFWD_FWMACTRR6_MACIPUR_Msk (0x80000UL) /*!< MACIPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR6_MACEMER_Pos (20UL) /*!< MACEMER (Bit 20) */ + #define R_MFWD_FWMACTRR6_MACEMER_Msk (0x100000UL) /*!< MACEMER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR6_MACCMER_Pos (21UL) /*!< MACCMER (Bit 21) */ + #define R_MFWD_FWMACTRR6_MACCMER_Msk (0x200000UL) /*!< MACCMER (Bitfield-Mask: 0x01) */ +/* ====================================================== FWMACAGUSPC ====================================================== */ + #define R_MFWD_FWMACAGUSPC_MACAGUSP_Pos (0UL) /*!< MACAGUSP (Bit 0) */ + #define R_MFWD_FWMACAGUSPC_MACAGUSP_Msk (0x3ffUL) /*!< MACAGUSP (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWMACAGC ======================================================== */ + #define R_MFWD_FWMACAGC_MACAGT_Pos (0UL) /*!< MACAGT (Bit 0) */ + #define R_MFWD_FWMACAGC_MACAGT_Msk (0xffffUL) /*!< MACAGT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWMACAGC_MACAGE_Pos (16UL) /*!< MACAGE (Bit 16) */ + #define R_MFWD_FWMACAGC_MACAGE_Msk (0x10000UL) /*!< MACAGE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGSL_Pos (17UL) /*!< MACAGSL (Bit 17) */ + #define R_MFWD_FWMACAGC_MACAGSL_Msk (0x20000UL) /*!< MACAGSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGPM_Pos (18UL) /*!< MACAGPM (Bit 18) */ + #define R_MFWD_FWMACAGC_MACAGPM_Msk (0x40000UL) /*!< MACAGPM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACDES_Pos (24UL) /*!< MACDES (Bit 24) */ + #define R_MFWD_FWMACAGC_MACDES_Msk (0x1000000UL) /*!< MACDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGOG_Pos (28UL) /*!< MACAGOG (Bit 28) */ + #define R_MFWD_FWMACAGC_MACAGOG_Msk (0x10000000UL) /*!< MACAGOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACDESOG_Pos (29UL) /*!< MACDESOG (Bit 29) */ + #define R_MFWD_FWMACAGC_MACDESOG_Msk (0x20000000UL) /*!< MACDESOG (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACAGM0 ======================================================= */ + #define R_MFWD_FWMACAGM0_AGMACAP0_Pos (0UL) /*!< AGMACAP0 (Bit 0) */ + #define R_MFWD_FWMACAGM0_AGMACAP0_Msk (0xffffUL) /*!< AGMACAP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACAGM1 ======================================================= */ + #define R_MFWD_FWMACAGM1_AGMACAP1_Pos (0UL) /*!< AGMACAP1 (Bit 0) */ + #define R_MFWD_FWMACAGM1_AGMACAP1_Msk (0xffffffffUL) /*!< AGMACAP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWVLANTEC ======================================================= */ + #define R_MFWD_FWVLANTEC_VLANTMUE_Pos (16UL) /*!< VLANTMUE (Bit 16) */ + #define R_MFWD_FWVLANTEC_VLANTMUE_Msk (0x1fff0000UL) /*!< VLANTMUE (Bitfield-Mask: 0x1fff) */ +/* ======================================================= FWVLANTL0 ======================================================= */ + #define R_MFWD_FWVLANTL0_VLANSLL_Pos (8UL) /*!< VLANSLL (Bit 8) */ + #define R_MFWD_FWVLANTL0_VLANSLL_Msk (0x100UL) /*!< VLANSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL0_VLANHLDL_Pos (10UL) /*!< VLANHLDL (Bit 10) */ + #define R_MFWD_FWVLANTL0_VLANHLDL_Msk (0x400UL) /*!< VLANHLDL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL0_VLANED_Pos (16UL) /*!< VLANED (Bit 16) */ + #define R_MFWD_FWVLANTL0_VLANED_Msk (0x10000UL) /*!< VLANED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTL1 ======================================================= */ + #define R_MFWD_FWVLANTL1_VLANVIDL_Pos (0UL) /*!< VLANVIDL (Bit 0) */ + #define R_MFWD_FWVLANTL1_VLANVIDL_Msk (0xfffUL) /*!< VLANVIDL (Bitfield-Mask: 0xfff) */ +/* ======================================================= FWVLANTL2 ======================================================= */ + #define R_MFWD_FWVLANTL2_VLANSLVL_Pos (0UL) /*!< VLANSLVL (Bit 0) */ + #define R_MFWD_FWVLANTL2_VLANSLVL_Msk (0x7fUL) /*!< VLANSLVL (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTL30 ======================================================= */ + #define R_MFWD_FWVLANTL30_VLANCSDL_Pos (0UL) /*!< VLANCSDL (Bit 0) */ + #define R_MFWD_FWVLANTL30_VLANCSDL_Msk (0x7fUL) /*!< VLANCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWVLANTL4 ======================================================= */ + #define R_MFWD_FWVLANTL4_VLANDVL_Pos (0UL) /*!< VLANDVL (Bit 0) */ + #define R_MFWD_FWVLANTL4_VLANDVL_Msk (0x7fUL) /*!< VLANDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWVLANTL4_VLANIPVL_Pos (16UL) /*!< VLANIPVL (Bit 16) */ + #define R_MFWD_FWVLANTL4_VLANIPVL_Msk (0x70000UL) /*!< VLANIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWVLANTL4_VLANIPUL_Pos (19UL) /*!< VLANIPUL (Bit 19) */ + #define R_MFWD_FWVLANTL4_VLANIPUL_Msk (0x80000UL) /*!< VLANIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL4_VLANEMEL_Pos (20UL) /*!< VLANEMEL (Bit 20) */ + #define R_MFWD_FWVLANTL4_VLANEMEL_Msk (0x100000UL) /*!< VLANEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL4_VLANCMEL_Pos (21UL) /*!< VLANCMEL (Bit 21) */ + #define R_MFWD_FWVLANTL4_VLANCMEL_Msk (0x200000UL) /*!< VLANCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTLR ======================================================= */ + #define R_MFWD_FWVLANTLR_VLANLF_Pos (0UL) /*!< VLANLF (Bit 0) */ + #define R_MFWD_FWVLANTLR_VLANLF_Msk (0x1UL) /*!< VLANLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLSF_Pos (1UL) /*!< VLANLSF (Bit 1) */ + #define R_MFWD_FWVLANTLR_VLANLSF_Msk (0x2UL) /*!< VLANLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLEF_Pos (2UL) /*!< VLANLEF (Bit 2) */ + #define R_MFWD_FWVLANTLR_VLANLEF_Msk (0x4UL) /*!< VLANLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLO_Pos (3UL) /*!< VLANLO (Bit 3) */ + #define R_MFWD_FWVLANTLR_VLANLO_Msk (0x8UL) /*!< VLANLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANTL_Pos (31UL) /*!< VLANTL (Bit 31) */ + #define R_MFWD_FWVLANTLR_VLANTL_Msk (0x80000000UL) /*!< VLANTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTIM ======================================================= */ + #define R_MFWD_FWVLANTIM_VLANTIOG_Pos (0UL) /*!< VLANTIOG (Bit 0) */ + #define R_MFWD_FWVLANTIM_VLANTIOG_Msk (0x1UL) /*!< VLANTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTIM_VLANTR_Pos (1UL) /*!< VLANTR (Bit 1) */ + #define R_MFWD_FWVLANTIM_VLANTR_Msk (0x2UL) /*!< VLANTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTEM ======================================================= */ + #define R_MFWD_FWVLANTEM_VLANTEN_Pos (0UL) /*!< VLANTEN (Bit 0) */ + #define R_MFWD_FWVLANTEM_VLANTEN_Msk (0x1fffUL) /*!< VLANTEN (Bitfield-Mask: 0x1fff) */ + #define R_MFWD_FWVLANTEM_VLANTUEN_Pos (16UL) /*!< VLANTUEN (Bit 16) */ + #define R_MFWD_FWVLANTEM_VLANTUEN_Msk (0x1fff0000UL) /*!< VLANTUEN (Bitfield-Mask: 0x1fff) */ +/* ======================================================= FWVLANTS ======================================================== */ + #define R_MFWD_FWVLANTS_VLANVIDS_Pos (0UL) /*!< VLANVIDS (Bit 0) */ + #define R_MFWD_FWVLANTS_VLANVIDS_Msk (0xfffUL) /*!< VLANVIDS (Bitfield-Mask: 0xfff) */ +/* ====================================================== FWVLANTSR0 ======================================================= */ + #define R_MFWD_FWVLANTSR0_VLANSEF_Pos (0UL) /*!< VLANSEF (Bit 0) */ + #define R_MFWD_FWVLANTSR0_VLANSEF_Msk (0x1UL) /*!< VLANSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANSNF_Pos (1UL) /*!< VLANSNF (Bit 1) */ + #define R_MFWD_FWVLANTSR0_VLANSNF_Msk (0x2UL) /*!< VLANSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANSLS_Pos (8UL) /*!< VLANSLS (Bit 8) */ + #define R_MFWD_FWVLANTSR0_VLANSLS_Msk (0x100UL) /*!< VLANSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANHLDS_Pos (10UL) /*!< VLANHLDS (Bit 10) */ + #define R_MFWD_FWVLANTSR0_VLANHLDS_Msk (0x400UL) /*!< VLANHLDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANTS_Pos (31UL) /*!< VLANTS (Bit 31) */ + #define R_MFWD_FWVLANTSR0_VLANTS_Msk (0x80000000UL) /*!< VLANTS (Bitfield-Mask: 0x01) */ +/* ====================================================== FWVLANTSR1 ======================================================= */ + #define R_MFWD_FWVLANTSR1_VLANSLVS_Pos (0UL) /*!< VLANSLVS (Bit 0) */ + #define R_MFWD_FWVLANTSR1_VLANSLVS_Msk (0x7fUL) /*!< VLANSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTSR20 ====================================================== */ + #define R_MFWD_FWVLANTSR20_VLANCSDS_Pos (0UL) /*!< VLANCSDS (Bit 0) */ + #define R_MFWD_FWVLANTSR20_VLANCSDS_Msk (0x7fUL) /*!< VLANCSDS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTSR3 ======================================================= */ + #define R_MFWD_FWVLANTSR3_VLANDVS_Pos (0UL) /*!< VLANDVS (Bit 0) */ + #define R_MFWD_FWVLANTSR3_VLANDVS_Msk (0x7fUL) /*!< VLANDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWVLANTSR3_VLANIPVS_Pos (16UL) /*!< VLANIPVS (Bit 16) */ + #define R_MFWD_FWVLANTSR3_VLANIPVS_Msk (0x70000UL) /*!< VLANIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWVLANTSR3_VLANIPUS_Pos (19UL) /*!< VLANIPUS (Bit 19) */ + #define R_MFWD_FWVLANTSR3_VLANIPUS_Msk (0x80000UL) /*!< VLANIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR3_VLANEMES_Pos (20UL) /*!< VLANEMES (Bit 20) */ + #define R_MFWD_FWVLANTSR3_VLANEMES_Msk (0x100000UL) /*!< VLANEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR3_VLANCMES_Pos (21UL) /*!< VLANCMES (Bit 21) */ + #define R_MFWD_FWVLANTSR3_VLANCMES_Msk (0x200000UL) /*!< VLANCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC0 ======================================================== */ + #define R_MFWD_FWPBFC0_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC0_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC0_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC0_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC0_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC0_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC0_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC0_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC0_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC0_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC0_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC0_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC0_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC1 ======================================================== */ + #define R_MFWD_FWPBFC1_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC1_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC1_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC1_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC1_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC1_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC1_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC1_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC1_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC1_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC1_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC1_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC1_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC2 ======================================================== */ + #define R_MFWD_FWPBFC2_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC2_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC2_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC2_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC2_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC2_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC2_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC2_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC2_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC2_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC2_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC2_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC2_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ====================================================== FWPBFCSDC00 ====================================================== */ + #define R_MFWD_FWPBFCSDC00_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC00_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWPBFCSDC01 ====================================================== */ + #define R_MFWD_FWPBFCSDC01_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC01_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWPBFCSDC02 ====================================================== */ + #define R_MFWD_FWPBFCSDC02_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC02_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWL23URL0 ======================================================= */ + #define R_MFWD_FWL23URL0_L23URNL_Pos (0UL) /*!< L23URNL (Bit 0) */ + #define R_MFWD_FWL23URL0_L23URNL_Msk (0xffUL) /*!< L23URNL (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URL0_L23URPVL_Pos (16UL) /*!< L23URPVL (Bit 16) */ + #define R_MFWD_FWL23URL0_L23URPVL_Msk (0x7f0000UL) /*!< L23URPVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWL23URL1 ======================================================= */ + #define R_MFWD_FWL23URL1_L23UMDALP0_Pos (0UL) /*!< L23UMDALP0 (Bit 0) */ + #define R_MFWD_FWL23URL1_L23UMDALP0_Msk (0xffffUL) /*!< L23UMDALP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWL23URL1_L23UTTLUL_Pos (16UL) /*!< L23UTTLUL (Bit 16) */ + #define R_MFWD_FWL23URL1_L23UTTLUL_Msk (0x10000UL) /*!< L23UTTLUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UMDAUL_Pos (17UL) /*!< L23UMDAUL (Bit 17) */ + #define R_MFWD_FWL23URL1_L23UMDAUL_Msk (0x20000UL) /*!< L23UMDAUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UMSAUL_Pos (18UL) /*!< L23UMSAUL (Bit 18) */ + #define R_MFWD_FWL23URL1_L23UMSAUL_Msk (0x40000UL) /*!< L23UMSAUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCVIDUL_Pos (19UL) /*!< L23UCVIDUL (Bit 19) */ + #define R_MFWD_FWL23URL1_L23UCVIDUL_Msk (0x80000UL) /*!< L23UCVIDUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCPCPUL_Pos (20UL) /*!< L23UCPCPUL (Bit 20) */ + #define R_MFWD_FWL23URL1_L23UCPCPUL_Msk (0x100000UL) /*!< L23UCPCPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCDEIUL_Pos (21UL) /*!< L23UCDEIUL (Bit 21) */ + #define R_MFWD_FWL23URL1_L23UCDEIUL_Msk (0x200000UL) /*!< L23UCDEIUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USVIDUL_Pos (22UL) /*!< L23USVIDUL (Bit 22) */ + #define R_MFWD_FWL23URL1_L23USVIDUL_Msk (0x400000UL) /*!< L23USVIDUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USPCPUL_Pos (23UL) /*!< L23USPCPUL (Bit 23) */ + #define R_MFWD_FWL23URL1_L23USPCPUL_Msk (0x800000UL) /*!< L23USPCPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USDEIUL_Pos (24UL) /*!< L23USDEIUL (Bit 24) */ + #define R_MFWD_FWL23URL1_L23USDEIUL_Msk (0x1000000UL) /*!< L23USDEIUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23URTUL_Pos (25UL) /*!< L23URTUL (Bit 25) */ + #define R_MFWD_FWL23URL1_L23URTUL_Msk (0x6000000UL) /*!< L23URTUL (Bitfield-Mask: 0x03) */ +/* ======================================================= FWL23URL2 ======================================================= */ + #define R_MFWD_FWL23URL2_L23UMDALP1_Pos (0UL) /*!< L23UMDALP1 (Bit 0) */ + #define R_MFWD_FWL23URL2_L23UMDALP1_Msk (0xffffffffUL) /*!< L23UMDALP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWL23URL3 ======================================================= */ + #define R_MFWD_FWL23URL3_L23UCVIDL_Pos (0UL) /*!< L23UCVIDL (Bit 0) */ + #define R_MFWD_FWL23URL3_L23UCVIDL_Msk (0xfffUL) /*!< L23UCVIDL (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URL3_L23UCPCPL_Pos (12UL) /*!< L23UCPCPL (Bit 12) */ + #define R_MFWD_FWL23URL3_L23UCPCPL_Msk (0x7000UL) /*!< L23UCPCPL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URL3_L23UCDEIL_Pos (15UL) /*!< L23UCDEIL (Bit 15) */ + #define R_MFWD_FWL23URL3_L23UCDEIL_Msk (0x8000UL) /*!< L23UCDEIL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL3_L23USVIDL_Pos (16UL) /*!< L23USVIDL (Bit 16) */ + #define R_MFWD_FWL23URL3_L23USVIDL_Msk (0xfff0000UL) /*!< L23USVIDL (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URL3_L23USPCPL_Pos (28UL) /*!< L23USPCPL (Bit 28) */ + #define R_MFWD_FWL23URL3_L23USPCPL_Msk (0x70000000UL) /*!< L23USPCPL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URL3_L23USDEIL_Pos (31UL) /*!< L23USDEIL (Bit 31) */ + #define R_MFWD_FWL23URL3_L23USDEIL_Msk (0x80000000UL) /*!< L23USDEIL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23URLR ======================================================= */ + #define R_MFWD_FWL23URLR_L23ULF_Pos (0UL) /*!< L23ULF (Bit 0) */ + #define R_MFWD_FWL23URLR_L23ULF_Msk (0x1UL) /*!< L23ULF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URLR_L23URL_Pos (31UL) /*!< L23URL (Bit 31) */ + #define R_MFWD_FWL23URLR_L23URL_Msk (0x80000000UL) /*!< L23URL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23UTIM ======================================================= */ + #define R_MFWD_FWL23UTIM_L23UTIOG_Pos (0UL) /*!< L23UTIOG (Bit 0) */ + #define R_MFWD_FWL23UTIM_L23UTIOG_Msk (0x1UL) /*!< L23UTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23UTIM_L23UTR_Pos (1UL) /*!< L23UTR (Bit 1) */ + #define R_MFWD_FWL23UTIM_L23UTR_Msk (0x2UL) /*!< L23UTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23URR ======================================================== */ + #define R_MFWD_FWL23URR_L23RNR_Pos (0UL) /*!< L23RNR (Bit 0) */ + #define R_MFWD_FWL23URR_L23RNR_Msk (0xffUL) /*!< L23RNR (Bitfield-Mask: 0xff) */ +/* ====================================================== FWL23URRR0 ======================================================= */ + #define R_MFWD_FWL23URRR0_L23URPVR_Pos (0UL) /*!< L23URPVR (Bit 0) */ + #define R_MFWD_FWL23URRR0_L23URPVR_Msk (0x7fUL) /*!< L23URPVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWL23URRR0_L23UREF_Pos (16UL) /*!< L23UREF (Bit 16) */ + #define R_MFWD_FWL23URRR0_L23UREF_Msk (0x10000UL) /*!< L23UREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR0_L23URR_Pos (31UL) /*!< L23URR (Bit 31) */ + #define R_MFWD_FWL23URRR0_L23URR_Msk (0x80000000UL) /*!< L23URR (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URRR1 ======================================================= */ + #define R_MFWD_FWL23URRR1_L23UMDARP0_Pos (0UL) /*!< L23UMDARP0 (Bit 0) */ + #define R_MFWD_FWL23URRR1_L23UMDARP0_Msk (0xffffUL) /*!< L23UMDARP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWL23URRR1_L23UTTLUR_Pos (16UL) /*!< L23UTTLUR (Bit 16) */ + #define R_MFWD_FWL23URRR1_L23UTTLUR_Msk (0x10000UL) /*!< L23UTTLUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UMDAUR_Pos (17UL) /*!< L23UMDAUR (Bit 17) */ + #define R_MFWD_FWL23URRR1_L23UMDAUR_Msk (0x20000UL) /*!< L23UMDAUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UMSAUR_Pos (18UL) /*!< L23UMSAUR (Bit 18) */ + #define R_MFWD_FWL23URRR1_L23UMSAUR_Msk (0x40000UL) /*!< L23UMSAUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCVIDUR_Pos (19UL) /*!< L23UCVIDUR (Bit 19) */ + #define R_MFWD_FWL23URRR1_L23UCVIDUR_Msk (0x80000UL) /*!< L23UCVIDUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCPCPUR_Pos (20UL) /*!< L23UCPCPUR (Bit 20) */ + #define R_MFWD_FWL23URRR1_L23UCPCPUR_Msk (0x100000UL) /*!< L23UCPCPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCDEIUR_Pos (21UL) /*!< L23UCDEIUR (Bit 21) */ + #define R_MFWD_FWL23URRR1_L23UCDEIUR_Msk (0x200000UL) /*!< L23UCDEIUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USVIDUR_Pos (22UL) /*!< L23USVIDUR (Bit 22) */ + #define R_MFWD_FWL23URRR1_L23USVIDUR_Msk (0x400000UL) /*!< L23USVIDUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USPCPUR_Pos (23UL) /*!< L23USPCPUR (Bit 23) */ + #define R_MFWD_FWL23URRR1_L23USPCPUR_Msk (0x800000UL) /*!< L23USPCPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USDEIUR_Pos (24UL) /*!< L23USDEIUR (Bit 24) */ + #define R_MFWD_FWL23URRR1_L23USDEIUR_Msk (0x1000000UL) /*!< L23USDEIUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23URTUR_Pos (25UL) /*!< L23URTUR (Bit 25) */ + #define R_MFWD_FWL23URRR1_L23URTUR_Msk (0x6000000UL) /*!< L23URTUR (Bitfield-Mask: 0x03) */ +/* ====================================================== FWL23URRR2 ======================================================= */ + #define R_MFWD_FWL23URRR2_L23UMDARP1_Pos (0UL) /*!< L23UMDARP1 (Bit 0) */ + #define R_MFWD_FWL23URRR2_L23UMDARP1_Msk (0xffffffffUL) /*!< L23UMDARP1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWL23URRR3 ======================================================= */ + #define R_MFWD_FWL23URRR3_L23UCVIDR_Pos (0UL) /*!< L23UCVIDR (Bit 0) */ + #define R_MFWD_FWL23URRR3_L23UCVIDR_Msk (0xfffUL) /*!< L23UCVIDR (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URRR3_L23UCPCPR_Pos (12UL) /*!< L23UCPCPR (Bit 12) */ + #define R_MFWD_FWL23URRR3_L23UCPCPR_Msk (0x7000UL) /*!< L23UCPCPR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URRR3_L23UCDEIR_Pos (15UL) /*!< L23UCDEIR (Bit 15) */ + #define R_MFWD_FWL23URRR3_L23UCDEIR_Msk (0x8000UL) /*!< L23UCDEIR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR3_L23USVIDR_Pos (16UL) /*!< L23USVIDR (Bit 16) */ + #define R_MFWD_FWL23URRR3_L23USVIDR_Msk (0xfff0000UL) /*!< L23USVIDR (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URRR3_L23USPCPR_Pos (28UL) /*!< L23USPCPR (Bit 28) */ + #define R_MFWD_FWL23URRR3_L23USPCPR_Msk (0x70000000UL) /*!< L23USPCPR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URRR3_L23USDEIR_Pos (31UL) /*!< L23USDEIR (Bit 31) */ + #define R_MFWD_FWL23URRR3_L23USDEIR_Msk (0x80000000UL) /*!< L23USDEIR (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC0 ======================================================= */ + #define R_MFWD_FWL23URMC0_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC0_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC0_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC0_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC0_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC0_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC0_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC0_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC1 ======================================================= */ + #define R_MFWD_FWL23URMC1_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC1_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC1_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC1_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC1_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC1_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC1_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC1_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC2 ======================================================= */ + #define R_MFWD_FWL23URMC2_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC2_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC2_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC2_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC2_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC2_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC2_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC2_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC3 ======================================================= */ + #define R_MFWD_FWL23URMC3_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC3_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC3_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC3_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC3_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC3_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC3_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC3_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC4 ======================================================= */ + #define R_MFWD_FWL23URMC4_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC4_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC4_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC4_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC4_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC4_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC4_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC4_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC5 ======================================================= */ + #define R_MFWD_FWL23URMC5_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC5_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC5_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC5_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC5_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC5_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC5_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC5_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC6 ======================================================= */ + #define R_MFWD_FWL23URMC6_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC6_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC6_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC6_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC6_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC6_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC6_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC6_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC7 ======================================================= */ + #define R_MFWD_FWL23URMC7_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC7_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC7_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC7_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC7_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC7_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC7_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC7_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC8 ======================================================= */ + #define R_MFWD_FWL23URMC8_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC8_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC8_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC8_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC8_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC8_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC8_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC8_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC9 ======================================================= */ + #define R_MFWD_FWL23URMC9_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC9_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC9_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC9_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC9_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC9_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC9_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC9_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC10 ====================================================== */ + #define R_MFWD_FWL23URMC10_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC10_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC10_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC10_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC10_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC10_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC10_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC10_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC11 ====================================================== */ + #define R_MFWD_FWL23URMC11_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC11_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC11_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC11_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC11_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC11_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC11_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC11_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC12 ====================================================== */ + #define R_MFWD_FWL23URMC12_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC12_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC12_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC12_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC12_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC12_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC12_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC12_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC13 ====================================================== */ + #define R_MFWD_FWL23URMC13_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC13_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC13_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC13_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC13_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC13_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC13_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC13_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC14 ====================================================== */ + #define R_MFWD_FWL23URMC14_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC14_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC14_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC14_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC14_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC14_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC14_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC14_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC15 ====================================================== */ + #define R_MFWD_FWL23URMC15_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC15_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC15_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC15_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC15_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC15_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC15_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC15_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC16 ====================================================== */ + #define R_MFWD_FWL23URMC16_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC16_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC16_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC16_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC16_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC16_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC16_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC16_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC17 ====================================================== */ + #define R_MFWD_FWL23URMC17_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC17_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC17_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC17_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC17_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC17_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC17_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC17_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC18 ====================================================== */ + #define R_MFWD_FWL23URMC18_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC18_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC18_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC18_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC18_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC18_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC18_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC18_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC19 ====================================================== */ + #define R_MFWD_FWL23URMC19_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC19_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC19_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC19_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC19_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC19_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC19_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC19_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC20 ====================================================== */ + #define R_MFWD_FWL23URMC20_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC20_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC20_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC20_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC20_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC20_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC20_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC20_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC21 ====================================================== */ + #define R_MFWD_FWL23URMC21_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC21_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC21_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC21_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC21_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC21_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC21_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC21_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC22 ====================================================== */ + #define R_MFWD_FWL23URMC22_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC22_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC22_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC22_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC22_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC22_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC22_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC22_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC23 ====================================================== */ + #define R_MFWD_FWL23URMC23_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC23_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC23_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC23_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC23_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC23_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC23_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC23_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC24 ====================================================== */ + #define R_MFWD_FWL23URMC24_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC24_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC24_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC24_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC24_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC24_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC24_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC24_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC25 ====================================================== */ + #define R_MFWD_FWL23URMC25_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC25_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC25_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC25_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC25_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC25_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC25_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC25_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC26 ====================================================== */ + #define R_MFWD_FWL23URMC26_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC26_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC26_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC26_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC26_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC26_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC26_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC26_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC27 ====================================================== */ + #define R_MFWD_FWL23URMC27_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC27_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC27_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC27_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC27_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC27_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC27_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC27_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC28 ====================================================== */ + #define R_MFWD_FWL23URMC28_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC28_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC28_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC28_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC28_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC28_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC28_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC28_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC29 ====================================================== */ + #define R_MFWD_FWL23URMC29_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC29_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC29_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC29_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC29_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC29_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC29_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC29_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC30 ====================================================== */ + #define R_MFWD_FWL23URMC30_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC30_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC30_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC30_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC30_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC30_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC30_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC30_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC31 ====================================================== */ + #define R_MFWD_FWL23URMC31_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC31_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC31_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC31_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC31_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC31_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC31_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC31_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC0 ======================================================== */ + #define R_MFWD_FWPMFGC0_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC0_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC0_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC0_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC1 ======================================================== */ + #define R_MFWD_FWPMFGC1_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC1_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC1_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC1_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC2 ======================================================== */ + #define R_MFWD_FWPMFGC2_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC2_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC2_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC2_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC3 ======================================================== */ + #define R_MFWD_FWPMFGC3_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC3_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC3_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC3_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC4 ======================================================== */ + #define R_MFWD_FWPMFGC4_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC4_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC4_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC4_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC5 ======================================================== */ + #define R_MFWD_FWPMFGC5_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC5_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC5_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC5_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC6 ======================================================== */ + #define R_MFWD_FWPMFGC6_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC6_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC6_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC6_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC7 ======================================================== */ + #define R_MFWD_FWPMFGC7_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC7_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC7_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC7_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC8 ======================================================== */ + #define R_MFWD_FWPMFGC8_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC8_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC8_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC8_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC9 ======================================================== */ + #define R_MFWD_FWPMFGC9_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC9_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC9_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC9_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC10 ======================================================= */ + #define R_MFWD_FWPMFGC10_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC10_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC10_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC10_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC11 ======================================================= */ + #define R_MFWD_FWPMFGC11_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC11_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC11_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC11_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC12 ======================================================= */ + #define R_MFWD_FWPMFGC12_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC12_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC12_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC12_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC13 ======================================================= */ + #define R_MFWD_FWPMFGC13_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC13_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC13_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC13_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC14 ======================================================= */ + #define R_MFWD_FWPMFGC14_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC14_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC14_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC14_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC15 ======================================================= */ + #define R_MFWD_FWPMFGC15_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC15_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC15_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC15_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMTRFC0 ======================================================= */ + #define R_MFWD_FWPMTRFC0_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC0_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC0_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC0_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC0_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC0_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC0_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC1 ======================================================= */ + #define R_MFWD_FWPMTRFC1_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC1_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC1_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC1_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC1_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC1_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC1_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC2 ======================================================= */ + #define R_MFWD_FWPMTRFC2_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC2_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC2_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC2_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC2_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC2_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC2_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC3 ======================================================= */ + #define R_MFWD_FWPMTRFC3_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC3_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC3_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC3_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC3_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC3_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC3_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC4 ======================================================= */ + #define R_MFWD_FWPMTRFC4_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC4_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC4_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC4_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC4_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC4_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC4_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC5 ======================================================= */ + #define R_MFWD_FWPMTRFC5_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC5_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC5_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC5_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC5_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC5_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC5_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC6 ======================================================= */ + #define R_MFWD_FWPMTRFC6_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC6_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC6_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC6_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC6_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC6_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC6_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC7 ======================================================= */ + #define R_MFWD_FWPMTRFC7_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC7_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC7_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC7_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC7_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC7_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC7_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC8 ======================================================= */ + #define R_MFWD_FWPMTRFC8_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC8_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC8_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC8_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC8_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC8_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC8_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC9 ======================================================= */ + #define R_MFWD_FWPMTRFC9_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC9_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC9_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC9_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC9_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC9_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC9_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC10 ======================================================= */ + #define R_MFWD_FWPMTRFC10_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC10_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC10_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC10_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC10_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC10_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC10_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC11 ======================================================= */ + #define R_MFWD_FWPMTRFC11_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC11_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC11_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC11_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC11_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC11_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC11_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC12 ======================================================= */ + #define R_MFWD_FWPMTRFC12_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC12_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC12_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC12_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC12_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC12_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC12_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC13 ======================================================= */ + #define R_MFWD_FWPMTRFC13_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC13_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC13_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC13_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC13_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC13_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC13_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC14 ======================================================= */ + #define R_MFWD_FWPMTRFC14_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC14_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC14_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC14_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC14_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC14_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC14_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC15 ======================================================= */ + #define R_MFWD_FWPMTRFC15_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC15_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC15_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC15_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC15_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC15_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC15_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC16 ======================================================= */ + #define R_MFWD_FWPMTRFC16_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC16_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC16_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC16_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC16_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC16_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC16_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC17 ======================================================= */ + #define R_MFWD_FWPMTRFC17_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC17_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC17_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC17_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC17_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC17_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC17_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC18 ======================================================= */ + #define R_MFWD_FWPMTRFC18_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC18_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC18_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC18_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC18_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC18_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC18_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC19 ======================================================= */ + #define R_MFWD_FWPMTRFC19_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC19_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC19_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC19_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC19_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC19_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC19_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC20 ======================================================= */ + #define R_MFWD_FWPMTRFC20_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC20_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC20_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC20_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC20_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC20_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC20_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC21 ======================================================= */ + #define R_MFWD_FWPMTRFC21_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC21_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC21_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC21_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC21_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC21_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC21_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC22 ======================================================= */ + #define R_MFWD_FWPMTRFC22_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC22_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC22_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC22_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC22_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC22_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC22_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC23 ======================================================= */ + #define R_MFWD_FWPMTRFC23_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC23_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC23_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC23_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC23_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC23_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC23_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC24 ======================================================= */ + #define R_MFWD_FWPMTRFC24_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC24_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC24_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC24_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC24_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC24_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC24_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC25 ======================================================= */ + #define R_MFWD_FWPMTRFC25_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC25_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC25_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC25_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC25_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC25_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC25_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC26 ======================================================= */ + #define R_MFWD_FWPMTRFC26_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC26_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC26_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC26_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC26_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC26_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC26_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC27 ======================================================= */ + #define R_MFWD_FWPMTRFC27_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC27_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC27_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC27_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC27_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC27_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC27_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC28 ======================================================= */ + #define R_MFWD_FWPMTRFC28_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC28_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC28_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC28_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC28_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC28_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC28_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC29 ======================================================= */ + #define R_MFWD_FWPMTRFC29_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC29_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC29_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC29_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC29_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC29_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC29_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC30 ======================================================= */ + #define R_MFWD_FWPMTRFC30_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC30_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC30_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC30_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC30_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC30_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC30_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC31 ======================================================= */ + #define R_MFWD_FWPMTRFC31_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC31_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC31_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC31_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC31_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC31_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC31_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRCBSC0 ====================================================== */ + #define R_MFWD_FWPMTRCBSC0_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC0_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC1 ====================================================== */ + #define R_MFWD_FWPMTRCBSC1_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC1_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC2 ====================================================== */ + #define R_MFWD_FWPMTRCBSC2_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC2_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC3 ====================================================== */ + #define R_MFWD_FWPMTRCBSC3_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC3_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC4 ====================================================== */ + #define R_MFWD_FWPMTRCBSC4_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC4_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC5 ====================================================== */ + #define R_MFWD_FWPMTRCBSC5_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC5_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC6 ====================================================== */ + #define R_MFWD_FWPMTRCBSC6_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC6_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC7 ====================================================== */ + #define R_MFWD_FWPMTRCBSC7_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC7_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC8 ====================================================== */ + #define R_MFWD_FWPMTRCBSC8_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC8_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC9 ====================================================== */ + #define R_MFWD_FWPMTRCBSC9_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC9_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC10 ====================================================== */ + #define R_MFWD_FWPMTRCBSC10_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC10_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC11 ====================================================== */ + #define R_MFWD_FWPMTRCBSC11_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC11_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC12 ====================================================== */ + #define R_MFWD_FWPMTRCBSC12_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC12_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC13 ====================================================== */ + #define R_MFWD_FWPMTRCBSC13_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC13_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC14 ====================================================== */ + #define R_MFWD_FWPMTRCBSC14_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC14_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC15 ====================================================== */ + #define R_MFWD_FWPMTRCBSC15_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC15_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC16 ====================================================== */ + #define R_MFWD_FWPMTRCBSC16_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC16_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC17 ====================================================== */ + #define R_MFWD_FWPMTRCBSC17_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC17_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC18 ====================================================== */ + #define R_MFWD_FWPMTRCBSC18_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC18_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC19 ====================================================== */ + #define R_MFWD_FWPMTRCBSC19_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC19_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC20 ====================================================== */ + #define R_MFWD_FWPMTRCBSC20_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC20_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC21 ====================================================== */ + #define R_MFWD_FWPMTRCBSC21_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC21_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC22 ====================================================== */ + #define R_MFWD_FWPMTRCBSC22_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC22_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC23 ====================================================== */ + #define R_MFWD_FWPMTRCBSC23_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC23_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC24 ====================================================== */ + #define R_MFWD_FWPMTRCBSC24_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC24_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC25 ====================================================== */ + #define R_MFWD_FWPMTRCBSC25_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC25_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC26 ====================================================== */ + #define R_MFWD_FWPMTRCBSC26_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC26_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC27 ====================================================== */ + #define R_MFWD_FWPMTRCBSC27_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC27_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC28 ====================================================== */ + #define R_MFWD_FWPMTRCBSC28_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC28_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC29 ====================================================== */ + #define R_MFWD_FWPMTRCBSC29_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC29_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC30 ====================================================== */ + #define R_MFWD_FWPMTRCBSC30_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC30_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC31 ====================================================== */ + #define R_MFWD_FWPMTRCBSC31_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC31_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCIRC0 ====================================================== */ + #define R_MFWD_FWPMTRCIRC0_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC0_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC1 ====================================================== */ + #define R_MFWD_FWPMTRCIRC1_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC1_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC2 ====================================================== */ + #define R_MFWD_FWPMTRCIRC2_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC2_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC3 ====================================================== */ + #define R_MFWD_FWPMTRCIRC3_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC3_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC4 ====================================================== */ + #define R_MFWD_FWPMTRCIRC4_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC4_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC5 ====================================================== */ + #define R_MFWD_FWPMTRCIRC5_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC5_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC6 ====================================================== */ + #define R_MFWD_FWPMTRCIRC6_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC6_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC7 ====================================================== */ + #define R_MFWD_FWPMTRCIRC7_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC7_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC8 ====================================================== */ + #define R_MFWD_FWPMTRCIRC8_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC8_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC9 ====================================================== */ + #define R_MFWD_FWPMTRCIRC9_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC9_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC10 ====================================================== */ + #define R_MFWD_FWPMTRCIRC10_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC10_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC11 ====================================================== */ + #define R_MFWD_FWPMTRCIRC11_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC11_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC12 ====================================================== */ + #define R_MFWD_FWPMTRCIRC12_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC12_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC13 ====================================================== */ + #define R_MFWD_FWPMTRCIRC13_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC13_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC14 ====================================================== */ + #define R_MFWD_FWPMTRCIRC14_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC14_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC15 ====================================================== */ + #define R_MFWD_FWPMTRCIRC15_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC15_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC16 ====================================================== */ + #define R_MFWD_FWPMTRCIRC16_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC16_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC17 ====================================================== */ + #define R_MFWD_FWPMTRCIRC17_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC17_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC18 ====================================================== */ + #define R_MFWD_FWPMTRCIRC18_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC18_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC19 ====================================================== */ + #define R_MFWD_FWPMTRCIRC19_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC19_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC20 ====================================================== */ + #define R_MFWD_FWPMTRCIRC20_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC20_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC21 ====================================================== */ + #define R_MFWD_FWPMTRCIRC21_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC21_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC22 ====================================================== */ + #define R_MFWD_FWPMTRCIRC22_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC22_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC23 ====================================================== */ + #define R_MFWD_FWPMTRCIRC23_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC23_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC24 ====================================================== */ + #define R_MFWD_FWPMTRCIRC24_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC24_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC25 ====================================================== */ + #define R_MFWD_FWPMTRCIRC25_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC25_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC26 ====================================================== */ + #define R_MFWD_FWPMTRCIRC26_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC26_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC27 ====================================================== */ + #define R_MFWD_FWPMTRCIRC27_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC27_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC28 ====================================================== */ + #define R_MFWD_FWPMTRCIRC28_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC28_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC29 ====================================================== */ + #define R_MFWD_FWPMTRCIRC29_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC29_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC30 ====================================================== */ + #define R_MFWD_FWPMTRCIRC30_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC30_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC31 ====================================================== */ + #define R_MFWD_FWPMTRCIRC31_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC31_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREBSC0 ====================================================== */ + #define R_MFWD_FWPMTREBSC0_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC0_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC1 ====================================================== */ + #define R_MFWD_FWPMTREBSC1_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC1_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC2 ====================================================== */ + #define R_MFWD_FWPMTREBSC2_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC2_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC3 ====================================================== */ + #define R_MFWD_FWPMTREBSC3_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC3_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC4 ====================================================== */ + #define R_MFWD_FWPMTREBSC4_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC4_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC5 ====================================================== */ + #define R_MFWD_FWPMTREBSC5_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC5_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC6 ====================================================== */ + #define R_MFWD_FWPMTREBSC6_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC6_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC7 ====================================================== */ + #define R_MFWD_FWPMTREBSC7_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC7_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREIRC0 ====================================================== */ + #define R_MFWD_FWPMTREIRC0_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC0_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC1 ====================================================== */ + #define R_MFWD_FWPMTREIRC1_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC1_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC2 ====================================================== */ + #define R_MFWD_FWPMTREIRC2_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC2_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC3 ====================================================== */ + #define R_MFWD_FWPMTREIRC3_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC3_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC4 ====================================================== */ + #define R_MFWD_FWPMTREIRC4_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC4_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC5 ====================================================== */ + #define R_MFWD_FWPMTREIRC5_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC5_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC6 ====================================================== */ + #define R_MFWD_FWPMTREIRC6_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC6_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC7 ====================================================== */ + #define R_MFWD_FWPMTREIRC7_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC7_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ======================================================= FWPMTRFM0 ======================================================= */ + #define R_MFWD_FWPMTRFM0_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM0_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM0_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM0_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM1 ======================================================= */ + #define R_MFWD_FWPMTRFM1_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM1_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM1_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM1_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM2 ======================================================= */ + #define R_MFWD_FWPMTRFM2_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM2_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM2_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM2_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM3 ======================================================= */ + #define R_MFWD_FWPMTRFM3_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM3_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM3_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM3_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM4 ======================================================= */ + #define R_MFWD_FWPMTRFM4_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM4_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM4_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM4_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM5 ======================================================= */ + #define R_MFWD_FWPMTRFM5_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM5_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM5_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM5_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM6 ======================================================= */ + #define R_MFWD_FWPMTRFM6_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM6_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM6_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM6_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM7 ======================================================= */ + #define R_MFWD_FWPMTRFM7_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM7_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM7_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM7_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM8 ======================================================= */ + #define R_MFWD_FWPMTRFM8_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM8_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM8_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM8_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM9 ======================================================= */ + #define R_MFWD_FWPMTRFM9_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM9_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM9_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM9_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM10 ======================================================= */ + #define R_MFWD_FWPMTRFM10_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM10_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM10_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM10_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM11 ======================================================= */ + #define R_MFWD_FWPMTRFM11_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM11_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM11_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM11_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM12 ======================================================= */ + #define R_MFWD_FWPMTRFM12_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM12_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM12_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM12_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM13 ======================================================= */ + #define R_MFWD_FWPMTRFM13_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM13_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM13_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM13_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM14 ======================================================= */ + #define R_MFWD_FWPMTRFM14_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM14_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM14_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM14_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM15 ======================================================= */ + #define R_MFWD_FWPMTRFM15_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM15_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM15_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM15_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM16 ======================================================= */ + #define R_MFWD_FWPMTRFM16_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM16_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM16_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM16_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM17 ======================================================= */ + #define R_MFWD_FWPMTRFM17_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM17_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM17_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM17_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM18 ======================================================= */ + #define R_MFWD_FWPMTRFM18_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM18_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM18_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM18_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM19 ======================================================= */ + #define R_MFWD_FWPMTRFM19_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM19_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM19_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM19_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM20 ======================================================= */ + #define R_MFWD_FWPMTRFM20_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM20_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM20_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM20_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM21 ======================================================= */ + #define R_MFWD_FWPMTRFM21_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM21_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM21_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM21_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM22 ======================================================= */ + #define R_MFWD_FWPMTRFM22_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM22_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM22_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM22_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM23 ======================================================= */ + #define R_MFWD_FWPMTRFM23_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM23_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM23_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM23_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM24 ======================================================= */ + #define R_MFWD_FWPMTRFM24_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM24_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM24_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM24_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM25 ======================================================= */ + #define R_MFWD_FWPMTRFM25_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM25_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM25_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM25_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM26 ======================================================= */ + #define R_MFWD_FWPMTRFM26_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM26_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM26_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM26_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM27 ======================================================= */ + #define R_MFWD_FWPMTRFM27_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM27_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM27_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM27_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM28 ======================================================= */ + #define R_MFWD_FWPMTRFM28_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM28_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM28_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM28_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM29 ======================================================= */ + #define R_MFWD_FWPMTRFM29_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM29_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM29_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM29_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM30 ======================================================= */ + #define R_MFWD_FWPMTRFM30_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM30_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM30_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM30_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM31 ======================================================= */ + #define R_MFWD_FWPMTRFM31_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM31_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM31_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM31_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================== FWFTL0 ========================================================= */ + #define R_MFWD_FWFTL0_FEAL_Pos (0UL) /*!< FEAL (Bit 0) */ + #define R_MFWD_FWFTL0_FEAL_Msk (0x7fUL) /*!< FEAL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWFTL0_FSRPL_Pos (16UL) /*!< FSRPL (Bit 16) */ + #define R_MFWD_FWFTL0_FSRPL_Msk (0x7f0000UL) /*!< FSRPL (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTL1 ========================================================= */ + #define R_MFWD_FWFTL1_FSHLL_Pos (0UL) /*!< FSHLL (Bit 0) */ + #define R_MFWD_FWFTL1_FSHLL_Msk (0xfUL) /*!< FSHLL (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWFTL1_FTNSL_Pos (8UL) /*!< FTNSL (Bit 8) */ + #define R_MFWD_FWFTL1_FTNSL_Msk (0x100UL) /*!< FTNSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTL1_FSRPVL_Pos (9UL) /*!< FSRPVL (Bit 9) */ + #define R_MFWD_FWFTL1_FSRPVL_Msk (0x200UL) /*!< FSRPVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTL1_FSRRTL_Pos (16UL) /*!< FSRRTL (Bit 16) */ + #define R_MFWD_FWFTL1_FSRRTL_Msk (0x3ff0000UL) /*!< FSRRTL (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FWFTLR ========================================================= */ + #define R_MFWD_FWFTLR_FLF_Pos (0UL) /*!< FLF (Bit 0) */ + #define R_MFWD_FWFTLR_FLF_Msk (0x1UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTLR_FTL_Pos (31UL) /*!< FTL (Bit 31) */ + #define R_MFWD_FWFTLR_FTL_Msk (0x80000000UL) /*!< FTL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTOC ========================================================= */ + #define R_MFWD_FWFTOC_TOT_Pos (0UL) /*!< TOT (Bit 0) */ + #define R_MFWD_FWFTOC_TOT_Msk (0xffffUL) /*!< TOT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWFTOC_TOCE_Pos (16UL) /*!< TOCE (Bit 16) */ + #define R_MFWD_FWFTOC_TOCE_Msk (0x10000UL) /*!< TOCE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTOC_TOOG_Pos (17UL) /*!< TOOG (Bit 17) */ + #define R_MFWD_FWFTOC_TOOG_Msk (0x20000UL) /*!< TOOG (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTOPC ======================================================== */ + #define R_MFWD_FWFTOPC_USP_Pos (0UL) /*!< USP (Bit 0) */ + #define R_MFWD_FWFTOPC_USP_Msk (0x3ffUL) /*!< USP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FWFTIM ========================================================= */ + #define R_MFWD_FWFTIM_FTIOG_Pos (0UL) /*!< FTIOG (Bit 0) */ + #define R_MFWD_FWFTIM_FTIOG_Msk (0x1UL) /*!< FTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTIM_FTR_Pos (1UL) /*!< FTR (Bit 1) */ + #define R_MFWD_FWFTIM_FTR_Msk (0x2UL) /*!< FTR (Bitfield-Mask: 0x01) */ +/* ========================================================= FWFTR ========================================================= */ + #define R_MFWD_FWFTR_FEAR_Pos (0UL) /*!< FEAR (Bit 0) */ + #define R_MFWD_FWFTR_FEAR_Msk (0x7fUL) /*!< FEAR (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTRR0 ======================================================== */ + #define R_MFWD_FWFTRR0_FSHLR_Pos (0UL) /*!< FSHLR (Bit 0) */ + #define R_MFWD_FWFTRR0_FSHLR_Msk (0xfUL) /*!< FSHLR (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWFTRR0_FTNSR_Pos (8UL) /*!< FTNSR (Bit 8) */ + #define R_MFWD_FWFTRR0_FTNSR_Msk (0x100UL) /*!< FTNSR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FSRPVR_Pos (9UL) /*!< FSRPVR (Bit 9) */ + #define R_MFWD_FWFTRR0_FSRPVR_Msk (0x200UL) /*!< FSRPVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FSRRTR_Pos (16UL) /*!< FSRRTR (Bit 16) */ + #define R_MFWD_FWFTRR0_FSRRTR_Msk (0x3ff0000UL) /*!< FSRRTR (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWFTRR0_FTREF_Pos (30UL) /*!< FTREF (Bit 30) */ + #define R_MFWD_FWFTRR0_FTREF_Msk (0x40000000UL) /*!< FTREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FTR_Pos (31UL) /*!< FTR (Bit 31) */ + #define R_MFWD_FWFTRR0_FTR_Msk (0x80000000UL) /*!< FTR (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTRR1 ======================================================== */ + #define R_MFWD_FWFTRR1_FSHR_Pos (0UL) /*!< FSHR (Bit 0) */ + #define R_MFWD_FWFTRR1_FSHR_Msk (0x7fffUL) /*!< FSHR (Bitfield-Mask: 0x7fff) */ + #define R_MFWD_FWFTRR1_FSRPR_Pos (16UL) /*!< FSRPR (Bit 16) */ + #define R_MFWD_FWFTRR1_FSRPR_Msk (0x7f0000UL) /*!< FSRPR (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTRR2 ======================================================== */ + #define R_MFWD_FWFTRR2_FRSNR_Pos (0UL) /*!< FRSNR (Bit 0) */ + #define R_MFWD_FWFTRR2_FRSNR_Msk (0xffffUL) /*!< FRSNR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWFTRR2_FRRTR_Pos (16UL) /*!< FRRTR (Bit 16) */ + #define R_MFWD_FWFTRR2_FRRTR_Msk (0x3ff0000UL) /*!< FRRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWSEQNGC0 ======================================================= */ + #define R_MFWD_FWSEQNGC0_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC0_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC0_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC0_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC1 ======================================================= */ + #define R_MFWD_FWSEQNGC1_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC1_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC1_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC1_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC2 ======================================================= */ + #define R_MFWD_FWSEQNGC2_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC2_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC2_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC2_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC3 ======================================================= */ + #define R_MFWD_FWSEQNGC3_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC3_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC3_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC3_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC4 ======================================================= */ + #define R_MFWD_FWSEQNGC4_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC4_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC4_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC4_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC5 ======================================================= */ + #define R_MFWD_FWSEQNGC5_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC5_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC5_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC5_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC6 ======================================================= */ + #define R_MFWD_FWSEQNGC6_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC6_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC6_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC6_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC7 ======================================================= */ + #define R_MFWD_FWSEQNGC7_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC7_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC7_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC7_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC8 ======================================================= */ + #define R_MFWD_FWSEQNGC8_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC8_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC8_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC8_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC9 ======================================================= */ + #define R_MFWD_FWSEQNGC9_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC9_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC9_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC9_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC10 ======================================================= */ + #define R_MFWD_FWSEQNGC10_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC10_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC10_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC10_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC11 ======================================================= */ + #define R_MFWD_FWSEQNGC11_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC11_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC11_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC11_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC12 ======================================================= */ + #define R_MFWD_FWSEQNGC12_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC12_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC12_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC12_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC13 ======================================================= */ + #define R_MFWD_FWSEQNGC13_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC13_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC13_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC13_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC14 ======================================================= */ + #define R_MFWD_FWSEQNGC14_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC14_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC14_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC14_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC15 ======================================================= */ + #define R_MFWD_FWSEQNGC15_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC15_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC15_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC15_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC16 ======================================================= */ + #define R_MFWD_FWSEQNGC16_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC16_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC16_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC16_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC17 ======================================================= */ + #define R_MFWD_FWSEQNGC17_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC17_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC17_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC17_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC18 ======================================================= */ + #define R_MFWD_FWSEQNGC18_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC18_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC18_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC18_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC19 ======================================================= */ + #define R_MFWD_FWSEQNGC19_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC19_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC19_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC19_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC20 ======================================================= */ + #define R_MFWD_FWSEQNGC20_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC20_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC20_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC20_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC21 ======================================================= */ + #define R_MFWD_FWSEQNGC21_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC21_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC21_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC21_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC22 ======================================================= */ + #define R_MFWD_FWSEQNGC22_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC22_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC22_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC22_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC23 ======================================================= */ + #define R_MFWD_FWSEQNGC23_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC23_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC23_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC23_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC24 ======================================================= */ + #define R_MFWD_FWSEQNGC24_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC24_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC24_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC24_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC25 ======================================================= */ + #define R_MFWD_FWSEQNGC25_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC25_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC25_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC25_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC26 ======================================================= */ + #define R_MFWD_FWSEQNGC26_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC26_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC26_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC26_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC27 ======================================================= */ + #define R_MFWD_FWSEQNGC27_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC27_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC27_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC27_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC28 ======================================================= */ + #define R_MFWD_FWSEQNGC28_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC28_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC28_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC28_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC29 ======================================================= */ + #define R_MFWD_FWSEQNGC29_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC29_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC29_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC29_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC30 ======================================================= */ + #define R_MFWD_FWSEQNGC30_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC30_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC30_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC30_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC31 ======================================================= */ + #define R_MFWD_FWSEQNGC31_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC31_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC31_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC31_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGM0 ======================================================= */ + #define R_MFWD_FWSEQNGM0_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM0_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM1 ======================================================= */ + #define R_MFWD_FWSEQNGM1_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM1_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM2 ======================================================= */ + #define R_MFWD_FWSEQNGM2_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM2_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM3 ======================================================= */ + #define R_MFWD_FWSEQNGM3_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM3_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM4 ======================================================= */ + #define R_MFWD_FWSEQNGM4_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM4_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM5 ======================================================= */ + #define R_MFWD_FWSEQNGM5_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM5_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM6 ======================================================= */ + #define R_MFWD_FWSEQNGM6_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM6_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM7 ======================================================= */ + #define R_MFWD_FWSEQNGM7_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM7_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM8 ======================================================= */ + #define R_MFWD_FWSEQNGM8_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM8_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM9 ======================================================= */ + #define R_MFWD_FWSEQNGM9_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM9_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM10 ======================================================= */ + #define R_MFWD_FWSEQNGM10_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM10_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM11 ======================================================= */ + #define R_MFWD_FWSEQNGM11_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM11_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM12 ======================================================= */ + #define R_MFWD_FWSEQNGM12_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM12_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM13 ======================================================= */ + #define R_MFWD_FWSEQNGM13_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM13_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM14 ======================================================= */ + #define R_MFWD_FWSEQNGM14_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM14_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM15 ======================================================= */ + #define R_MFWD_FWSEQNGM15_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM15_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM16 ======================================================= */ + #define R_MFWD_FWSEQNGM16_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM16_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM17 ======================================================= */ + #define R_MFWD_FWSEQNGM17_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM17_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM18 ======================================================= */ + #define R_MFWD_FWSEQNGM18_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM18_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM19 ======================================================= */ + #define R_MFWD_FWSEQNGM19_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM19_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM20 ======================================================= */ + #define R_MFWD_FWSEQNGM20_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM20_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM21 ======================================================= */ + #define R_MFWD_FWSEQNGM21_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM21_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM22 ======================================================= */ + #define R_MFWD_FWSEQNGM22_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM22_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM23 ======================================================= */ + #define R_MFWD_FWSEQNGM23_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM23_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM24 ======================================================= */ + #define R_MFWD_FWSEQNGM24_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM24_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM25 ======================================================= */ + #define R_MFWD_FWSEQNGM25_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM25_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM26 ======================================================= */ + #define R_MFWD_FWSEQNGM26_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM26_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM27 ======================================================= */ + #define R_MFWD_FWSEQNGM27_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM27_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM28 ======================================================= */ + #define R_MFWD_FWSEQNGM28_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM28_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM29 ======================================================= */ + #define R_MFWD_FWSEQNGM29_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM29_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM30 ======================================================= */ + #define R_MFWD_FWSEQNGM30_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM30_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM31 ======================================================= */ + #define R_MFWD_FWSEQNGM31_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM31_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNRC ======================================================== */ + #define R_MFWD_FWSEQNRC_SEQNR_Pos (0UL) /*!< SEQNR (Bit 0) */ + #define R_MFWD_FWSEQNRC_SEQNR_Msk (0xffffffffUL) /*!< SEQNR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTFDCN0 ======================================================= */ + #define R_MFWD_FWCTFDCN0_CTFDN_Pos (0UL) /*!< CTFDN (Bit 0) */ + #define R_MFWD_FWCTFDCN0_CTFDN_Msk (0xffffffffUL) /*!< CTFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTFDCN1 ======================================================= */ + #define R_MFWD_FWCTFDCN1_CTFDN_Pos (0UL) /*!< CTFDN (Bit 0) */ + #define R_MFWD_FWCTFDCN1_CTFDN_Msk (0xffffffffUL) /*!< CTFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN0 ======================================================= */ + #define R_MFWD_FWLTHFDCN0_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN0_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN1 ======================================================= */ + #define R_MFWD_FWLTHFDCN1_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN1_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN2 ======================================================= */ + #define R_MFWD_FWLTHFDCN2_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN2_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN0 ======================================================= */ + #define R_MFWD_FWLTWFDCN0_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN0_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN1 ======================================================= */ + #define R_MFWD_FWLTWFDCN1_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN1_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN2 ======================================================= */ + #define R_MFWD_FWLTWFDCN2_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN2_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN0 ======================================================= */ + #define R_MFWD_FWPBFDCN0_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN0_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN1 ======================================================= */ + #define R_MFWD_FWPBFDCN1_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN1_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN2 ======================================================= */ + #define R_MFWD_FWPBFDCN2_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN2_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN0 ======================================================== */ + #define R_MFWD_FWMHLCN0_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN0_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN1 ======================================================== */ + #define R_MFWD_FWMHLCN1_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN1_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN2 ======================================================== */ + #define R_MFWD_FWMHLCN2_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN2_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWDDFDCN0 ======================================================= */ + #define R_MFWD_FWDDFDCN0_DDFDN_Pos (0UL) /*!< DDFDN (Bit 0) */ + #define R_MFWD_FWDDFDCN0_DDFDN_Msk (0xffffffffUL) /*!< DDFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWWMRDCN0 ======================================================= */ + #define R_MFWD_FWWMRDCN0_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN0_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWWMRDCN1 ======================================================= */ + #define R_MFWD_FWWMRDCN1_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN1_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWWMRDCN2 ======================================================= */ + #define R_MFWD_FWWMRDCN2_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN2_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTRDCN0 ======================================================= */ + #define R_MFWD_FWCTRDCN0_CTRDN_Pos (0UL) /*!< CTRDN (Bit 0) */ + #define R_MFWD_FWCTRDCN0_CTRDN_Msk (0xffffUL) /*!< CTRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTRDCN1 ======================================================= */ + #define R_MFWD_FWCTRDCN1_CTRDN_Pos (0UL) /*!< CTRDN (Bit 0) */ + #define R_MFWD_FWCTRDCN1_CTRDN_Msk (0xffffUL) /*!< CTRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN0 ======================================================= */ + #define R_MFWD_FWLTHRDCN0_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN0_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN1 ======================================================= */ + #define R_MFWD_FWLTHRDCN1_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN1_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN2 ======================================================= */ + #define R_MFWD_FWLTHRDCN2_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN2_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN0 ======================================================= */ + #define R_MFWD_FWLTWRDCN0_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN0_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN1 ======================================================= */ + #define R_MFWD_FWLTWRDCN1_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN1_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN2 ======================================================= */ + #define R_MFWD_FWLTWRDCN2_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN2_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN0 ======================================================= */ + #define R_MFWD_FWPBRDCN0_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN0_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN1 ======================================================= */ + #define R_MFWD_FWPBRDCN1_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN1_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN2 ======================================================= */ + #define R_MFWD_FWPBRDCN2_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN2_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWDDRDCN0 ======================================================= */ + #define R_MFWD_FWDDRDCN0_DDRDN_Pos (0UL) /*!< DDRDN (Bit 0) */ + #define R_MFWD_FWDDRDCN0_DDRDN_Msk (0xffffUL) /*!< DDRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN0 ======================================================= */ + #define R_MFWD_FWPMFDCN0_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN0_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN1 ======================================================= */ + #define R_MFWD_FWPMFDCN1_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN1_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN2 ======================================================= */ + #define R_MFWD_FWPMFDCN2_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN2_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN3 ======================================================= */ + #define R_MFWD_FWPMFDCN3_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN3_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN4 ======================================================= */ + #define R_MFWD_FWPMFDCN4_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN4_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN5 ======================================================= */ + #define R_MFWD_FWPMFDCN5_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN5_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN6 ======================================================= */ + #define R_MFWD_FWPMFDCN6_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN6_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN7 ======================================================= */ + #define R_MFWD_FWPMFDCN7_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN7_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN8 ======================================================= */ + #define R_MFWD_FWPMFDCN8_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN8_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN9 ======================================================= */ + #define R_MFWD_FWPMFDCN9_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN9_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN10 ======================================================= */ + #define R_MFWD_FWPMFDCN10_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN10_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN11 ======================================================= */ + #define R_MFWD_FWPMFDCN11_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN11_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN12 ======================================================= */ + #define R_MFWD_FWPMFDCN12_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN12_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN13 ======================================================= */ + #define R_MFWD_FWPMFDCN13_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN13_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN14 ======================================================= */ + #define R_MFWD_FWPMFDCN14_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN14_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN15 ======================================================= */ + #define R_MFWD_FWPMFDCN15_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN15_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN0 ======================================================= */ + #define R_MFWD_FWPMGDCN0_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN0_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN1 ======================================================= */ + #define R_MFWD_FWPMGDCN1_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN1_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN2 ======================================================= */ + #define R_MFWD_FWPMGDCN2_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN2_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN3 ======================================================= */ + #define R_MFWD_FWPMGDCN3_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN3_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN4 ======================================================= */ + #define R_MFWD_FWPMGDCN4_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN4_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN5 ======================================================= */ + #define R_MFWD_FWPMGDCN5_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN5_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN6 ======================================================= */ + #define R_MFWD_FWPMGDCN6_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN6_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN7 ======================================================= */ + #define R_MFWD_FWPMGDCN7_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN7_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN8 ======================================================= */ + #define R_MFWD_FWPMGDCN8_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN8_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN9 ======================================================= */ + #define R_MFWD_FWPMGDCN9_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN9_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN10 ======================================================= */ + #define R_MFWD_FWPMGDCN10_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN10_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN11 ======================================================= */ + #define R_MFWD_FWPMGDCN11_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN11_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN12 ======================================================= */ + #define R_MFWD_FWPMGDCN12_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN12_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN13 ======================================================= */ + #define R_MFWD_FWPMGDCN13_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN13_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN14 ======================================================= */ + #define R_MFWD_FWPMGDCN14_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN14_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN15 ======================================================= */ + #define R_MFWD_FWPMGDCN15_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN15_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN16 ======================================================= */ + #define R_MFWD_FWPMGDCN16_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN16_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN17 ======================================================= */ + #define R_MFWD_FWPMGDCN17_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN17_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN18 ======================================================= */ + #define R_MFWD_FWPMGDCN18_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN18_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN19 ======================================================= */ + #define R_MFWD_FWPMGDCN19_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN19_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN20 ======================================================= */ + #define R_MFWD_FWPMGDCN20_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN20_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN21 ======================================================= */ + #define R_MFWD_FWPMGDCN21_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN21_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN22 ======================================================= */ + #define R_MFWD_FWPMGDCN22_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN22_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN23 ======================================================= */ + #define R_MFWD_FWPMGDCN23_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN23_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN24 ======================================================= */ + #define R_MFWD_FWPMGDCN24_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN24_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN25 ======================================================= */ + #define R_MFWD_FWPMGDCN25_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN25_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN26 ======================================================= */ + #define R_MFWD_FWPMGDCN26_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN26_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN27 ======================================================= */ + #define R_MFWD_FWPMGDCN27_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN27_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN28 ======================================================= */ + #define R_MFWD_FWPMGDCN28_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN28_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN29 ======================================================= */ + #define R_MFWD_FWPMGDCN29_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN29_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN30 ======================================================= */ + #define R_MFWD_FWPMGDCN30_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN30_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN31 ======================================================= */ + #define R_MFWD_FWPMGDCN31_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN31_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN0 ======================================================= */ + #define R_MFWD_FWPMYDCN0_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN0_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN1 ======================================================= */ + #define R_MFWD_FWPMYDCN1_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN1_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN2 ======================================================= */ + #define R_MFWD_FWPMYDCN2_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN2_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN3 ======================================================= */ + #define R_MFWD_FWPMYDCN3_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN3_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN4 ======================================================= */ + #define R_MFWD_FWPMYDCN4_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN4_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN5 ======================================================= */ + #define R_MFWD_FWPMYDCN5_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN5_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN6 ======================================================= */ + #define R_MFWD_FWPMYDCN6_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN6_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN7 ======================================================= */ + #define R_MFWD_FWPMYDCN7_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN7_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN0 ======================================================= */ + #define R_MFWD_FWPMRDCN0_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN0_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN1 ======================================================= */ + #define R_MFWD_FWPMRDCN1_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN1_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN2 ======================================================= */ + #define R_MFWD_FWPMRDCN2_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN2_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN3 ======================================================= */ + #define R_MFWD_FWPMRDCN3_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN3_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN4 ======================================================= */ + #define R_MFWD_FWPMRDCN4_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN4_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN5 ======================================================= */ + #define R_MFWD_FWPMRDCN5_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN5_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN6 ======================================================= */ + #define R_MFWD_FWPMRDCN6_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN6_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN7 ======================================================= */ + #define R_MFWD_FWPMRDCN7_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN7_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN8 ======================================================= */ + #define R_MFWD_FWPMRDCN8_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN8_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN9 ======================================================= */ + #define R_MFWD_FWPMRDCN9_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN9_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN10 ======================================================= */ + #define R_MFWD_FWPMRDCN10_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN10_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN11 ======================================================= */ + #define R_MFWD_FWPMRDCN11_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN11_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN12 ======================================================= */ + #define R_MFWD_FWPMRDCN12_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN12_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN13 ======================================================= */ + #define R_MFWD_FWPMRDCN13_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN13_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN14 ======================================================= */ + #define R_MFWD_FWPMRDCN14_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN14_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN15 ======================================================= */ + #define R_MFWD_FWPMRDCN15_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN15_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN16 ======================================================= */ + #define R_MFWD_FWPMRDCN16_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN16_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN17 ======================================================= */ + #define R_MFWD_FWPMRDCN17_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN17_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN18 ======================================================= */ + #define R_MFWD_FWPMRDCN18_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN18_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN19 ======================================================= */ + #define R_MFWD_FWPMRDCN19_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN19_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN20 ======================================================= */ + #define R_MFWD_FWPMRDCN20_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN20_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN21 ======================================================= */ + #define R_MFWD_FWPMRDCN21_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN21_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN22 ======================================================= */ + #define R_MFWD_FWPMRDCN22_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN22_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN23 ======================================================= */ + #define R_MFWD_FWPMRDCN23_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN23_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN24 ======================================================= */ + #define R_MFWD_FWPMRDCN24_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN24_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN25 ======================================================= */ + #define R_MFWD_FWPMRDCN25_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN25_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN26 ======================================================= */ + #define R_MFWD_FWPMRDCN26_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN26_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN27 ======================================================= */ + #define R_MFWD_FWPMRDCN27_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN27_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN28 ======================================================= */ + #define R_MFWD_FWPMRDCN28_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN28_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN29 ======================================================= */ + #define R_MFWD_FWPMRDCN29_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN29_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN30 ======================================================= */ + #define R_MFWD_FWPMRDCN30_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN30_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN31 ======================================================= */ + #define R_MFWD_FWPMRDCN31_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN31_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN0 ======================================================= */ + #define R_MFWD_FWFRPPCN0_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN0_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN1 ======================================================= */ + #define R_MFWD_FWFRPPCN1_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN1_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN2 ======================================================= */ + #define R_MFWD_FWFRPPCN2_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN2_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN3 ======================================================= */ + #define R_MFWD_FWFRPPCN3_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN3_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN4 ======================================================= */ + #define R_MFWD_FWFRPPCN4_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN4_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN5 ======================================================= */ + #define R_MFWD_FWFRPPCN5_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN5_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN6 ======================================================= */ + #define R_MFWD_FWFRPPCN6_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN6_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN7 ======================================================= */ + #define R_MFWD_FWFRPPCN7_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN7_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN8 ======================================================= */ + #define R_MFWD_FWFRPPCN8_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN8_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN9 ======================================================= */ + #define R_MFWD_FWFRPPCN9_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN9_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN10 ======================================================= */ + #define R_MFWD_FWFRPPCN10_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN10_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN11 ======================================================= */ + #define R_MFWD_FWFRPPCN11_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN11_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN12 ======================================================= */ + #define R_MFWD_FWFRPPCN12_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN12_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN13 ======================================================= */ + #define R_MFWD_FWFRPPCN13_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN13_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN14 ======================================================= */ + #define R_MFWD_FWFRPPCN14_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN14_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN15 ======================================================= */ + #define R_MFWD_FWFRPPCN15_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN15_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN16 ======================================================= */ + #define R_MFWD_FWFRPPCN16_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN16_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN17 ======================================================= */ + #define R_MFWD_FWFRPPCN17_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN17_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN18 ======================================================= */ + #define R_MFWD_FWFRPPCN18_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN18_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN19 ======================================================= */ + #define R_MFWD_FWFRPPCN19_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN19_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN20 ======================================================= */ + #define R_MFWD_FWFRPPCN20_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN20_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN21 ======================================================= */ + #define R_MFWD_FWFRPPCN21_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN21_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN22 ======================================================= */ + #define R_MFWD_FWFRPPCN22_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN22_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN23 ======================================================= */ + #define R_MFWD_FWFRPPCN23_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN23_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN24 ======================================================= */ + #define R_MFWD_FWFRPPCN24_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN24_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN25 ======================================================= */ + #define R_MFWD_FWFRPPCN25_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN25_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN26 ======================================================= */ + #define R_MFWD_FWFRPPCN26_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN26_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN27 ======================================================= */ + #define R_MFWD_FWFRPPCN27_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN27_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN28 ======================================================= */ + #define R_MFWD_FWFRPPCN28_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN28_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN29 ======================================================= */ + #define R_MFWD_FWFRPPCN29_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN29_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN30 ======================================================= */ + #define R_MFWD_FWFRPPCN30_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN30_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN31 ======================================================= */ + #define R_MFWD_FWFRPPCN31_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN31_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN32 ======================================================= */ + #define R_MFWD_FWFRPPCN32_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN32_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN33 ======================================================= */ + #define R_MFWD_FWFRPPCN33_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN33_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN34 ======================================================= */ + #define R_MFWD_FWFRPPCN34_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN34_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN35 ======================================================= */ + #define R_MFWD_FWFRPPCN35_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN35_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN36 ======================================================= */ + #define R_MFWD_FWFRPPCN36_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN36_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN37 ======================================================= */ + #define R_MFWD_FWFRPPCN37_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN37_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN38 ======================================================= */ + #define R_MFWD_FWFRPPCN38_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN38_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN39 ======================================================= */ + #define R_MFWD_FWFRPPCN39_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN39_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN40 ======================================================= */ + #define R_MFWD_FWFRPPCN40_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN40_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN41 ======================================================= */ + #define R_MFWD_FWFRPPCN41_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN41_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN42 ======================================================= */ + #define R_MFWD_FWFRPPCN42_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN42_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN43 ======================================================= */ + #define R_MFWD_FWFRPPCN43_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN43_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN44 ======================================================= */ + #define R_MFWD_FWFRPPCN44_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN44_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN45 ======================================================= */ + #define R_MFWD_FWFRPPCN45_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN45_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN46 ======================================================= */ + #define R_MFWD_FWFRPPCN46_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN46_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN47 ======================================================= */ + #define R_MFWD_FWFRPPCN47_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN47_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN48 ======================================================= */ + #define R_MFWD_FWFRPPCN48_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN48_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN49 ======================================================= */ + #define R_MFWD_FWFRPPCN49_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN49_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN50 ======================================================= */ + #define R_MFWD_FWFRPPCN50_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN50_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN51 ======================================================= */ + #define R_MFWD_FWFRPPCN51_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN51_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN52 ======================================================= */ + #define R_MFWD_FWFRPPCN52_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN52_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN53 ======================================================= */ + #define R_MFWD_FWFRPPCN53_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN53_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN54 ======================================================= */ + #define R_MFWD_FWFRPPCN54_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN54_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN55 ======================================================= */ + #define R_MFWD_FWFRPPCN55_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN55_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN56 ======================================================= */ + #define R_MFWD_FWFRPPCN56_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN56_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN57 ======================================================= */ + #define R_MFWD_FWFRPPCN57_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN57_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN58 ======================================================= */ + #define R_MFWD_FWFRPPCN58_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN58_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN59 ======================================================= */ + #define R_MFWD_FWFRPPCN59_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN59_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN60 ======================================================= */ + #define R_MFWD_FWFRPPCN60_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN60_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN61 ======================================================= */ + #define R_MFWD_FWFRPPCN61_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN61_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN62 ======================================================= */ + #define R_MFWD_FWFRPPCN62_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN62_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN63 ======================================================= */ + #define R_MFWD_FWFRPPCN63_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN63_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN64 ======================================================= */ + #define R_MFWD_FWFRPPCN64_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN64_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN65 ======================================================= */ + #define R_MFWD_FWFRPPCN65_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN65_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN66 ======================================================= */ + #define R_MFWD_FWFRPPCN66_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN66_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN67 ======================================================= */ + #define R_MFWD_FWFRPPCN67_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN67_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN68 ======================================================= */ + #define R_MFWD_FWFRPPCN68_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN68_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN69 ======================================================= */ + #define R_MFWD_FWFRPPCN69_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN69_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN70 ======================================================= */ + #define R_MFWD_FWFRPPCN70_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN70_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN71 ======================================================= */ + #define R_MFWD_FWFRPPCN71_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN71_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN72 ======================================================= */ + #define R_MFWD_FWFRPPCN72_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN72_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN73 ======================================================= */ + #define R_MFWD_FWFRPPCN73_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN73_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN74 ======================================================= */ + #define R_MFWD_FWFRPPCN74_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN74_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN75 ======================================================= */ + #define R_MFWD_FWFRPPCN75_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN75_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN76 ======================================================= */ + #define R_MFWD_FWFRPPCN76_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN76_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN77 ======================================================= */ + #define R_MFWD_FWFRPPCN77_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN77_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN78 ======================================================= */ + #define R_MFWD_FWFRPPCN78_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN78_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN79 ======================================================= */ + #define R_MFWD_FWFRPPCN79_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN79_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN80 ======================================================= */ + #define R_MFWD_FWFRPPCN80_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN80_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN81 ======================================================= */ + #define R_MFWD_FWFRPPCN81_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN81_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN82 ======================================================= */ + #define R_MFWD_FWFRPPCN82_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN82_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN83 ======================================================= */ + #define R_MFWD_FWFRPPCN83_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN83_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN84 ======================================================= */ + #define R_MFWD_FWFRPPCN84_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN84_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN85 ======================================================= */ + #define R_MFWD_FWFRPPCN85_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN85_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN86 ======================================================= */ + #define R_MFWD_FWFRPPCN86_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN86_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN87 ======================================================= */ + #define R_MFWD_FWFRPPCN87_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN87_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN88 ======================================================= */ + #define R_MFWD_FWFRPPCN88_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN88_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN89 ======================================================= */ + #define R_MFWD_FWFRPPCN89_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN89_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN90 ======================================================= */ + #define R_MFWD_FWFRPPCN90_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN90_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN91 ======================================================= */ + #define R_MFWD_FWFRPPCN91_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN91_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN92 ======================================================= */ + #define R_MFWD_FWFRPPCN92_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN92_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN93 ======================================================= */ + #define R_MFWD_FWFRPPCN93_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN93_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN94 ======================================================= */ + #define R_MFWD_FWFRPPCN94_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN94_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN95 ======================================================= */ + #define R_MFWD_FWFRPPCN95_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN95_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN96 ======================================================= */ + #define R_MFWD_FWFRPPCN96_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN96_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN97 ======================================================= */ + #define R_MFWD_FWFRPPCN97_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN97_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN98 ======================================================= */ + #define R_MFWD_FWFRPPCN98_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN98_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN99 ======================================================= */ + #define R_MFWD_FWFRPPCN99_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN99_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN100 ====================================================== */ + #define R_MFWD_FWFRPPCN100_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN100_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN101 ====================================================== */ + #define R_MFWD_FWFRPPCN101_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN101_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN102 ====================================================== */ + #define R_MFWD_FWFRPPCN102_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN102_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN103 ====================================================== */ + #define R_MFWD_FWFRPPCN103_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN103_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN104 ====================================================== */ + #define R_MFWD_FWFRPPCN104_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN104_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN105 ====================================================== */ + #define R_MFWD_FWFRPPCN105_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN105_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN106 ====================================================== */ + #define R_MFWD_FWFRPPCN106_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN106_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN107 ====================================================== */ + #define R_MFWD_FWFRPPCN107_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN107_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN108 ====================================================== */ + #define R_MFWD_FWFRPPCN108_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN108_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN109 ====================================================== */ + #define R_MFWD_FWFRPPCN109_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN109_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN110 ====================================================== */ + #define R_MFWD_FWFRPPCN110_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN110_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN111 ====================================================== */ + #define R_MFWD_FWFRPPCN111_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN111_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN112 ====================================================== */ + #define R_MFWD_FWFRPPCN112_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN112_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN113 ====================================================== */ + #define R_MFWD_FWFRPPCN113_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN113_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN114 ====================================================== */ + #define R_MFWD_FWFRPPCN114_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN114_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN115 ====================================================== */ + #define R_MFWD_FWFRPPCN115_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN115_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN116 ====================================================== */ + #define R_MFWD_FWFRPPCN116_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN116_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN117 ====================================================== */ + #define R_MFWD_FWFRPPCN117_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN117_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN118 ====================================================== */ + #define R_MFWD_FWFRPPCN118_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN118_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN119 ====================================================== */ + #define R_MFWD_FWFRPPCN119_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN119_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN120 ====================================================== */ + #define R_MFWD_FWFRPPCN120_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN120_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN121 ====================================================== */ + #define R_MFWD_FWFRPPCN121_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN121_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN122 ====================================================== */ + #define R_MFWD_FWFRPPCN122_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN122_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN123 ====================================================== */ + #define R_MFWD_FWFRPPCN123_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN123_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN124 ====================================================== */ + #define R_MFWD_FWFRPPCN124_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN124_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN125 ====================================================== */ + #define R_MFWD_FWFRPPCN125_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN125_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN126 ====================================================== */ + #define R_MFWD_FWFRPPCN126_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN126_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN127 ====================================================== */ + #define R_MFWD_FWFRPPCN127_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN127_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN0 ======================================================= */ + #define R_MFWD_FWFRDPCN0_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN0_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN1 ======================================================= */ + #define R_MFWD_FWFRDPCN1_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN1_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN2 ======================================================= */ + #define R_MFWD_FWFRDPCN2_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN2_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN3 ======================================================= */ + #define R_MFWD_FWFRDPCN3_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN3_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN4 ======================================================= */ + #define R_MFWD_FWFRDPCN4_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN4_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN5 ======================================================= */ + #define R_MFWD_FWFRDPCN5_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN5_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN6 ======================================================= */ + #define R_MFWD_FWFRDPCN6_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN6_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN7 ======================================================= */ + #define R_MFWD_FWFRDPCN7_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN7_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN8 ======================================================= */ + #define R_MFWD_FWFRDPCN8_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN8_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN9 ======================================================= */ + #define R_MFWD_FWFRDPCN9_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN9_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN10 ======================================================= */ + #define R_MFWD_FWFRDPCN10_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN10_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN11 ======================================================= */ + #define R_MFWD_FWFRDPCN11_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN11_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN12 ======================================================= */ + #define R_MFWD_FWFRDPCN12_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN12_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN13 ======================================================= */ + #define R_MFWD_FWFRDPCN13_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN13_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN14 ======================================================= */ + #define R_MFWD_FWFRDPCN14_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN14_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN15 ======================================================= */ + #define R_MFWD_FWFRDPCN15_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN15_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN16 ======================================================= */ + #define R_MFWD_FWFRDPCN16_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN16_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN17 ======================================================= */ + #define R_MFWD_FWFRDPCN17_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN17_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN18 ======================================================= */ + #define R_MFWD_FWFRDPCN18_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN18_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN19 ======================================================= */ + #define R_MFWD_FWFRDPCN19_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN19_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN20 ======================================================= */ + #define R_MFWD_FWFRDPCN20_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN20_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN21 ======================================================= */ + #define R_MFWD_FWFRDPCN21_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN21_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN22 ======================================================= */ + #define R_MFWD_FWFRDPCN22_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN22_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN23 ======================================================= */ + #define R_MFWD_FWFRDPCN23_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN23_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN24 ======================================================= */ + #define R_MFWD_FWFRDPCN24_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN24_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN25 ======================================================= */ + #define R_MFWD_FWFRDPCN25_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN25_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN26 ======================================================= */ + #define R_MFWD_FWFRDPCN26_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN26_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN27 ======================================================= */ + #define R_MFWD_FWFRDPCN27_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN27_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN28 ======================================================= */ + #define R_MFWD_FWFRDPCN28_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN28_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN29 ======================================================= */ + #define R_MFWD_FWFRDPCN29_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN29_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN30 ======================================================= */ + #define R_MFWD_FWFRDPCN30_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN30_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN31 ======================================================= */ + #define R_MFWD_FWFRDPCN31_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN31_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN32 ======================================================= */ + #define R_MFWD_FWFRDPCN32_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN32_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN33 ======================================================= */ + #define R_MFWD_FWFRDPCN33_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN33_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN34 ======================================================= */ + #define R_MFWD_FWFRDPCN34_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN34_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN35 ======================================================= */ + #define R_MFWD_FWFRDPCN35_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN35_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN36 ======================================================= */ + #define R_MFWD_FWFRDPCN36_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN36_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN37 ======================================================= */ + #define R_MFWD_FWFRDPCN37_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN37_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN38 ======================================================= */ + #define R_MFWD_FWFRDPCN38_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN38_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN39 ======================================================= */ + #define R_MFWD_FWFRDPCN39_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN39_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN40 ======================================================= */ + #define R_MFWD_FWFRDPCN40_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN40_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN41 ======================================================= */ + #define R_MFWD_FWFRDPCN41_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN41_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN42 ======================================================= */ + #define R_MFWD_FWFRDPCN42_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN42_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN43 ======================================================= */ + #define R_MFWD_FWFRDPCN43_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN43_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN44 ======================================================= */ + #define R_MFWD_FWFRDPCN44_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN44_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN45 ======================================================= */ + #define R_MFWD_FWFRDPCN45_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN45_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN46 ======================================================= */ + #define R_MFWD_FWFRDPCN46_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN46_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN47 ======================================================= */ + #define R_MFWD_FWFRDPCN47_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN47_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN48 ======================================================= */ + #define R_MFWD_FWFRDPCN48_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN48_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN49 ======================================================= */ + #define R_MFWD_FWFRDPCN49_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN49_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN50 ======================================================= */ + #define R_MFWD_FWFRDPCN50_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN50_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN51 ======================================================= */ + #define R_MFWD_FWFRDPCN51_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN51_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN52 ======================================================= */ + #define R_MFWD_FWFRDPCN52_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN52_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN53 ======================================================= */ + #define R_MFWD_FWFRDPCN53_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN53_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN54 ======================================================= */ + #define R_MFWD_FWFRDPCN54_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN54_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN55 ======================================================= */ + #define R_MFWD_FWFRDPCN55_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN55_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN56 ======================================================= */ + #define R_MFWD_FWFRDPCN56_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN56_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN57 ======================================================= */ + #define R_MFWD_FWFRDPCN57_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN57_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN58 ======================================================= */ + #define R_MFWD_FWFRDPCN58_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN58_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN59 ======================================================= */ + #define R_MFWD_FWFRDPCN59_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN59_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN60 ======================================================= */ + #define R_MFWD_FWFRDPCN60_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN60_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN61 ======================================================= */ + #define R_MFWD_FWFRDPCN61_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN61_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN62 ======================================================= */ + #define R_MFWD_FWFRDPCN62_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN62_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN63 ======================================================= */ + #define R_MFWD_FWFRDPCN63_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN63_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN64 ======================================================= */ + #define R_MFWD_FWFRDPCN64_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN64_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN65 ======================================================= */ + #define R_MFWD_FWFRDPCN65_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN65_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN66 ======================================================= */ + #define R_MFWD_FWFRDPCN66_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN66_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN67 ======================================================= */ + #define R_MFWD_FWFRDPCN67_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN67_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN68 ======================================================= */ + #define R_MFWD_FWFRDPCN68_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN68_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN69 ======================================================= */ + #define R_MFWD_FWFRDPCN69_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN69_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN70 ======================================================= */ + #define R_MFWD_FWFRDPCN70_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN70_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN71 ======================================================= */ + #define R_MFWD_FWFRDPCN71_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN71_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN72 ======================================================= */ + #define R_MFWD_FWFRDPCN72_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN72_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN73 ======================================================= */ + #define R_MFWD_FWFRDPCN73_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN73_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN74 ======================================================= */ + #define R_MFWD_FWFRDPCN74_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN74_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN75 ======================================================= */ + #define R_MFWD_FWFRDPCN75_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN75_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN76 ======================================================= */ + #define R_MFWD_FWFRDPCN76_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN76_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN77 ======================================================= */ + #define R_MFWD_FWFRDPCN77_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN77_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN78 ======================================================= */ + #define R_MFWD_FWFRDPCN78_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN78_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN79 ======================================================= */ + #define R_MFWD_FWFRDPCN79_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN79_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN80 ======================================================= */ + #define R_MFWD_FWFRDPCN80_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN80_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN81 ======================================================= */ + #define R_MFWD_FWFRDPCN81_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN81_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN82 ======================================================= */ + #define R_MFWD_FWFRDPCN82_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN82_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN83 ======================================================= */ + #define R_MFWD_FWFRDPCN83_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN83_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN84 ======================================================= */ + #define R_MFWD_FWFRDPCN84_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN84_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN85 ======================================================= */ + #define R_MFWD_FWFRDPCN85_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN85_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN86 ======================================================= */ + #define R_MFWD_FWFRDPCN86_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN86_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN87 ======================================================= */ + #define R_MFWD_FWFRDPCN87_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN87_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN88 ======================================================= */ + #define R_MFWD_FWFRDPCN88_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN88_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN89 ======================================================= */ + #define R_MFWD_FWFRDPCN89_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN89_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN90 ======================================================= */ + #define R_MFWD_FWFRDPCN90_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN90_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN91 ======================================================= */ + #define R_MFWD_FWFRDPCN91_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN91_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN92 ======================================================= */ + #define R_MFWD_FWFRDPCN92_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN92_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN93 ======================================================= */ + #define R_MFWD_FWFRDPCN93_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN93_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN94 ======================================================= */ + #define R_MFWD_FWFRDPCN94_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN94_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN95 ======================================================= */ + #define R_MFWD_FWFRDPCN95_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN95_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN96 ======================================================= */ + #define R_MFWD_FWFRDPCN96_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN96_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN97 ======================================================= */ + #define R_MFWD_FWFRDPCN97_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN97_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN98 ======================================================= */ + #define R_MFWD_FWFRDPCN98_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN98_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN99 ======================================================= */ + #define R_MFWD_FWFRDPCN99_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN99_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN100 ====================================================== */ + #define R_MFWD_FWFRDPCN100_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN100_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN101 ====================================================== */ + #define R_MFWD_FWFRDPCN101_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN101_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN102 ====================================================== */ + #define R_MFWD_FWFRDPCN102_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN102_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN103 ====================================================== */ + #define R_MFWD_FWFRDPCN103_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN103_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN104 ====================================================== */ + #define R_MFWD_FWFRDPCN104_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN104_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN105 ====================================================== */ + #define R_MFWD_FWFRDPCN105_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN105_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN106 ====================================================== */ + #define R_MFWD_FWFRDPCN106_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN106_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN107 ====================================================== */ + #define R_MFWD_FWFRDPCN107_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN107_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN108 ====================================================== */ + #define R_MFWD_FWFRDPCN108_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN108_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN109 ====================================================== */ + #define R_MFWD_FWFRDPCN109_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN109_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN110 ====================================================== */ + #define R_MFWD_FWFRDPCN110_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN110_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN111 ====================================================== */ + #define R_MFWD_FWFRDPCN111_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN111_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN112 ====================================================== */ + #define R_MFWD_FWFRDPCN112_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN112_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN113 ====================================================== */ + #define R_MFWD_FWFRDPCN113_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN113_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN114 ====================================================== */ + #define R_MFWD_FWFRDPCN114_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN114_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN115 ====================================================== */ + #define R_MFWD_FWFRDPCN115_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN115_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN116 ====================================================== */ + #define R_MFWD_FWFRDPCN116_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN116_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN117 ====================================================== */ + #define R_MFWD_FWFRDPCN117_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN117_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN118 ====================================================== */ + #define R_MFWD_FWFRDPCN118_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN118_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN119 ====================================================== */ + #define R_MFWD_FWFRDPCN119_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN119_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN120 ====================================================== */ + #define R_MFWD_FWFRDPCN120_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN120_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN121 ====================================================== */ + #define R_MFWD_FWFRDPCN121_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN121_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN122 ====================================================== */ + #define R_MFWD_FWFRDPCN122_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN122_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN123 ====================================================== */ + #define R_MFWD_FWFRDPCN123_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN123_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN124 ====================================================== */ + #define R_MFWD_FWFRDPCN124_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN124_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN125 ====================================================== */ + #define R_MFWD_FWFRDPCN125_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN125_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN126 ====================================================== */ + #define R_MFWD_FWFRDPCN126_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN126_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN127 ====================================================== */ + #define R_MFWD_FWFRDPCN127_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN127_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIS00 ======================================================== */ + #define R_MFWD_FWEIS00_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS00_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS00_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS00_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS00_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS00_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS00_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS00_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS00_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS00_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS00_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS00_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS00_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS00_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS00_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS00_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS00_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS00_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS00_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS00_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS00_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS01 ======================================================== */ + #define R_MFWD_FWEIS01_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS01_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS01_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS01_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS01_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS01_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS01_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS01_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS01_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS01_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS01_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS01_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS01_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS01_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS01_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS01_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS01_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS01_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS01_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS01_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS01_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS02 ======================================================== */ + #define R_MFWD_FWEIS02_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS02_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS02_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS02_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS02_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS02_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS02_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS02_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS02_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS02_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS02_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS02_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS02_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS02_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS02_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS02_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS02_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS02_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS02_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS02_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS02_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE00 ======================================================== */ + #define R_MFWD_FWEIE00_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE00_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE00_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE00_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE00_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE00_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE00_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE00_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE00_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE00_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE00_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE00_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE00_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE00_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE00_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE00_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE00_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE00_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE00_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE00_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE00_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE00_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE01 ======================================================== */ + #define R_MFWD_FWEIE01_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE01_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE01_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE01_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE01_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE01_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE01_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE01_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE01_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE01_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE01_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE01_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE01_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE01_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE01_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE01_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE01_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE01_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE01_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE01_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE01_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE01_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE02 ======================================================== */ + #define R_MFWD_FWEIE02_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE02_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE02_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE02_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE02_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE02_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE02_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE02_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE02_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE02_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE02_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE02_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE02_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE02_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE02_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE02_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE02_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE02_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE02_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE02_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE02_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE02_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID00 ======================================================== */ + #define R_MFWD_FWEID00_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID00_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID00_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID00_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID00_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID00_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID00_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID00_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID00_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID00_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID00_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID00_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID00_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID00_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID00_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID00_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID00_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID00_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID00_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID00_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID00_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID00_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID01 ======================================================== */ + #define R_MFWD_FWEID01_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID01_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID01_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID01_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID01_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID01_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID01_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID01_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID01_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID01_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID01_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID01_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID01_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID01_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID01_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID01_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID01_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID01_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID01_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID01_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID01_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID01_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID02 ======================================================== */ + #define R_MFWD_FWEID02_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID02_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID02_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID02_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID02_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID02_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID02_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID02_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID02_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID02_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID02_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID02_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID02_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID02_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID02_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID02_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID02_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID02_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID02_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID02_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID02_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID02_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS1 ========================================================= */ + #define R_MFWD_FWEIS1_LTHTEES_Pos (0UL) /*!< LTHTEES (Bit 0) */ + #define R_MFWD_FWEIS1_LTHTEES_Msk (0x1UL) /*!< LTHTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_LTHTSES_Pos (1UL) /*!< LTHTSES (Bit 1) */ + #define R_MFWD_FWEIS1_LTHTSES_Msk (0x2UL) /*!< LTHTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_MACTEES_Pos (4UL) /*!< MACTEES (Bit 4) */ + #define R_MFWD_FWEIS1_MACTEES_Msk (0x10UL) /*!< MACTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_MACTSES_Pos (5UL) /*!< MACTSES (Bit 5) */ + #define R_MFWD_FWEIS1_MACTSES_Msk (0x20UL) /*!< MACTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_VLANTEES_Pos (6UL) /*!< VLANTEES (Bit 6) */ + #define R_MFWD_FWEIS1_VLANTEES_Msk (0x40UL) /*!< VLANTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_VLANTSES_Pos (7UL) /*!< VLANTSES (Bit 7) */ + #define R_MFWD_FWEIS1_VLANTSES_Msk (0x80UL) /*!< VLANTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_L23UEES_Pos (8UL) /*!< L23UEES (Bit 8) */ + #define R_MFWD_FWEIS1_L23UEES_Msk (0x100UL) /*!< L23UEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_AREES_Pos (16UL) /*!< AREES (Bit 16) */ + #define R_MFWD_FWEIS1_AREES_Msk (0x10000UL) /*!< AREES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE1 ========================================================= */ + #define R_MFWD_FWEIE1_LTHTEEE_Pos (0UL) /*!< LTHTEEE (Bit 0) */ + #define R_MFWD_FWEIE1_LTHTEEE_Msk (0x1UL) /*!< LTHTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_LTHTSEE_Pos (1UL) /*!< LTHTSEE (Bit 1) */ + #define R_MFWD_FWEIE1_LTHTSEE_Msk (0x2UL) /*!< LTHTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_MACTEEE_Pos (4UL) /*!< MACTEEE (Bit 4) */ + #define R_MFWD_FWEIE1_MACTEEE_Msk (0x10UL) /*!< MACTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_MACTSEE_Pos (5UL) /*!< MACTSEE (Bit 5) */ + #define R_MFWD_FWEIE1_MACTSEE_Msk (0x20UL) /*!< MACTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_VLANTEEE_Pos (6UL) /*!< VLANTEEE (Bit 6) */ + #define R_MFWD_FWEIE1_VLANTEEE_Msk (0x40UL) /*!< VLANTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_VLANTSEE_Pos (7UL) /*!< VLANTSEE (Bit 7) */ + #define R_MFWD_FWEIE1_VLANTSEE_Msk (0x80UL) /*!< VLANTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_L23UEEE_Pos (8UL) /*!< L23UEEE (Bit 8) */ + #define R_MFWD_FWEIE1_L23UEEE_Msk (0x100UL) /*!< L23UEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_AREEE_Pos (16UL) /*!< AREEE (Bit 16) */ + #define R_MFWD_FWEIE1_AREEE_Msk (0x10000UL) /*!< AREEE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID1 ========================================================= */ + #define R_MFWD_FWEID1_LTHTEED_Pos (0UL) /*!< LTHTEED (Bit 0) */ + #define R_MFWD_FWEID1_LTHTEED_Msk (0x1UL) /*!< LTHTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_LTHTSED_Pos (1UL) /*!< LTHTSED (Bit 1) */ + #define R_MFWD_FWEID1_LTHTSED_Msk (0x2UL) /*!< LTHTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_MACTEED_Pos (4UL) /*!< MACTEED (Bit 4) */ + #define R_MFWD_FWEID1_MACTEED_Msk (0x10UL) /*!< MACTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_MACTSED_Pos (5UL) /*!< MACTSED (Bit 5) */ + #define R_MFWD_FWEID1_MACTSED_Msk (0x20UL) /*!< MACTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_VLANTEED_Pos (6UL) /*!< VLANTEED (Bit 6) */ + #define R_MFWD_FWEID1_VLANTEED_Msk (0x40UL) /*!< VLANTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_VLANTSED_Pos (7UL) /*!< VLANTSED (Bit 7) */ + #define R_MFWD_FWEID1_VLANTSED_Msk (0x80UL) /*!< VLANTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_L23UEED_Pos (8UL) /*!< L23UEED (Bit 8) */ + #define R_MFWD_FWEID1_L23UEED_Msk (0x100UL) /*!< L23UEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_AREED_Pos (16UL) /*!< AREED (Bit 16) */ + #define R_MFWD_FWEID1_AREED_Msk (0x10000UL) /*!< AREED (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS2 ========================================================= */ + #define R_MFWD_FWEIS2_PMFS_Pos (0UL) /*!< PMFS (Bit 0) */ + #define R_MFWD_FWEIS2_PMFS_Msk (0xffffUL) /*!< PMFS (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIE2 ========================================================= */ + #define R_MFWD_FWEIE2_PMFE_Pos (0UL) /*!< PMFE (Bit 0) */ + #define R_MFWD_FWEIE2_PMFE_Msk (0xffffUL) /*!< PMFE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEID2 ========================================================= */ + #define R_MFWD_FWEID2_PMFD_Pos (0UL) /*!< PMFD (Bit 0) */ + #define R_MFWD_FWEID2_PMFD_Msk (0xffffUL) /*!< PMFD (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIS5 ========================================================= */ + #define R_MFWD_FWEIS5_PMRFS_Pos (0UL) /*!< PMRFS (Bit 0) */ + #define R_MFWD_FWEIS5_PMRFS_Msk (0xffffffffUL) /*!< PMRFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE5 ========================================================= */ + #define R_MFWD_FWEIE5_PMRFE_Pos (0UL) /*!< PMRFE (Bit 0) */ + #define R_MFWD_FWEIE5_PMRFE_Msk (0xffffffffUL) /*!< PMRFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID5 ========================================================= */ + #define R_MFWD_FWEID5_PMRFD_Pos (0UL) /*!< PMRFD (Bit 0) */ + #define R_MFWD_FWEID5_PMRFD_Msk (0xffffffffUL) /*!< PMRFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS60 ======================================================== */ + #define R_MFWD_FWEIS60_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS60_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS61 ======================================================== */ + #define R_MFWD_FWEIS61_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS61_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS62 ======================================================== */ + #define R_MFWD_FWEIS62_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS62_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS63 ======================================================== */ + #define R_MFWD_FWEIS63_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS63_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE60 ======================================================== */ + #define R_MFWD_FWEIE60_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE60_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE61 ======================================================== */ + #define R_MFWD_FWEIE61_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE61_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE62 ======================================================== */ + #define R_MFWD_FWEIE62_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE62_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE63 ======================================================== */ + #define R_MFWD_FWEIE63_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE63_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID60 ======================================================== */ + #define R_MFWD_FWEID60_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID60_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID61 ======================================================== */ + #define R_MFWD_FWEID61_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID61_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID62 ======================================================== */ + #define R_MFWD_FWEID62_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID62_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID63 ======================================================== */ + #define R_MFWD_FWEID63_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID63_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS70 ======================================================== */ + #define R_MFWD_FWEIS70_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS70_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS71 ======================================================== */ + #define R_MFWD_FWEIS71_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS71_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS72 ======================================================== */ + #define R_MFWD_FWEIS72_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS72_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS73 ======================================================== */ + #define R_MFWD_FWEIS73_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS73_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE70 ======================================================== */ + #define R_MFWD_FWEIE70_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE70_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE71 ======================================================== */ + #define R_MFWD_FWEIE71_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE71_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE72 ======================================================== */ + #define R_MFWD_FWEIE72_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE72_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE73 ======================================================== */ + #define R_MFWD_FWEIE73_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE73_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID70 ======================================================== */ + #define R_MFWD_FWEID70_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID70_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID71 ======================================================== */ + #define R_MFWD_FWEID71_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID71_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID72 ======================================================== */ + #define R_MFWD_FWEID72_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID72_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID73 ======================================================== */ + #define R_MFWD_FWEID73_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID73_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS80 ======================================================== */ + #define R_MFWD_FWEIS80_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS80_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS81 ======================================================== */ + #define R_MFWD_FWEIS81_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS81_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS82 ======================================================== */ + #define R_MFWD_FWEIS82_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS82_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS83 ======================================================== */ + #define R_MFWD_FWEIS83_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS83_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE80 ======================================================== */ + #define R_MFWD_FWEIE80_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE80_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE81 ======================================================== */ + #define R_MFWD_FWEIE81_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE81_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE82 ======================================================== */ + #define R_MFWD_FWEIE82_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE82_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE83 ======================================================== */ + #define R_MFWD_FWEIE83_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE83_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID80 ======================================================== */ + #define R_MFWD_FWEID80_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID80_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID81 ======================================================== */ + #define R_MFWD_FWEID81_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID81_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID82 ======================================================== */ + #define R_MFWD_FWEID82_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID82_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID83 ======================================================== */ + #define R_MFWD_FWEID83_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID83_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWMIS0 ========================================================= */ + #define R_MFWD_FWMIS0_LTHTFS_Pos (0UL) /*!< LTHTFS (Bit 0) */ + #define R_MFWD_FWMIS0_LTHTFS_Msk (0x1UL) /*!< LTHTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_MACTFS_Pos (2UL) /*!< MACTFS (Bit 2) */ + #define R_MFWD_FWMIS0_MACTFS_Msk (0x4UL) /*!< MACTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_VLANTFS_Pos (3UL) /*!< VLANTFS (Bit 3) */ + #define R_MFWD_FWMIS0_VLANTFS_Msk (0x8UL) /*!< VLANTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_MACADAS_Pos (17UL) /*!< MACADAS (Bit 17) */ + #define R_MFWD_FWMIS0_MACADAS_Msk (0x20000UL) /*!< MACADAS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMIE0 ========================================================= */ + #define R_MFWD_FWMIE0_LTHTFE_Pos (0UL) /*!< LTHTFE (Bit 0) */ + #define R_MFWD_FWMIE0_LTHTFE_Msk (0x1UL) /*!< LTHTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_MACTFE_Pos (2UL) /*!< MACTFE (Bit 2) */ + #define R_MFWD_FWMIE0_MACTFE_Msk (0x4UL) /*!< MACTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_VLANTFE_Pos (3UL) /*!< VLANTFE (Bit 3) */ + #define R_MFWD_FWMIE0_VLANTFE_Msk (0x8UL) /*!< VLANTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_MACADAE_Pos (17UL) /*!< MACADAE (Bit 17) */ + #define R_MFWD_FWMIE0_MACADAE_Msk (0x20000UL) /*!< MACADAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMID0 ========================================================= */ + #define R_MFWD_FWMID0_LTHTFD_Pos (0UL) /*!< LTHTFD (Bit 0) */ + #define R_MFWD_FWMID0_LTHTFD_Msk (0x1UL) /*!< LTHTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_MACTFD_Pos (2UL) /*!< MACTFD (Bit 2) */ + #define R_MFWD_FWMID0_MACTFD_Msk (0x4UL) /*!< MACTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_VLANTFD_Pos (3UL) /*!< VLANTFD (Bit 3) */ + #define R_MFWD_FWMID0_VLANTFD_Msk (0x8UL) /*!< VLANTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_MACADAD_Pos (17UL) /*!< MACADAD (Bit 17) */ + #define R_MFWD_FWMID0_MACADAD_Msk (0x20000UL) /*!< MACADAD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ + #define R_MIPI_DSI_ISR_SQ0_Pos (0UL) /*!< SQ0 (Bit 0) */ + #define R_MIPI_DSI_ISR_SQ0_Msk (0x1UL) /*!< SQ0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_SQ1_Pos (4UL) /*!< SQ1 (Bit 4) */ + #define R_MIPI_DSI_ISR_SQ1_Msk (0x10UL) /*!< SQ1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_VM_Pos (8UL) /*!< VM (Bit 8) */ + #define R_MIPI_DSI_ISR_VM_Msk (0x100UL) /*!< VM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_RCV_Pos (12UL) /*!< RCV (Bit 12) */ + #define R_MIPI_DSI_ISR_RCV_Msk (0x1000UL) /*!< RCV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_FERR_Pos (16UL) /*!< FERR (Bit 16) */ + #define R_MIPI_DSI_ISR_FERR_Msk (0x10000UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_PPI_Pos (20UL) /*!< PPI (Bit 20) */ + #define R_MIPI_DSI_ISR_PPI_Msk (0x100000UL) /*!< PPI (Bitfield-Mask: 0x01) */ +/* ======================================================== LINKSR ========================================================= */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Pos (0UL) /*!< SQ0RUN (Bit 0) */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Msk (0x1UL) /*!< SQ0RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Pos (4UL) /*!< SQ1RUN (Bit 4) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Msk (0x10UL) /*!< SQ1RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_VRUN_Pos (8UL) /*!< VRUN (Bit 8) */ + #define R_MIPI_DSI_LINKSR_VRUN_Msk (0x100UL) /*!< VRUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Pos (12UL) /*!< HSBUSY (Bit 12) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Msk (0x1000UL) /*!< HSBUSY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Pos (13UL) /*!< LPBUSY (Bit 13) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Msk (0x2000UL) /*!< LPBUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== TXSETR ========================================================= */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Pos (0UL) /*!< NUMLANE (Bit 0) */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Msk (0x3UL) /*!< NUMLANE (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_TXSETR_CLEN_Pos (8UL) /*!< CLEN (Bit 8) */ + #define R_MIPI_DSI_TXSETR_CLEN_Msk (0x100UL) /*!< CLEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_TXSETR_DLEN_Pos (9UL) /*!< DLEN (Bit 9) */ + #define R_MIPI_DSI_TXSETR_DLEN_Msk (0x200UL) /*!< DLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= HSCLKSETR ======================================================= */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Pos (0UL) /*!< HSCLST (Bit 0) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Msk (0x1UL) /*!< HSCLST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Pos (1UL) /*!< HSCLMD (Bit 1) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Msk (0x2UL) /*!< HSCLMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPSSETR ======================================================== */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Pos (0UL) /*!< WKUP (Bit 0) */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Msk (0xffUL) /*!< WKUP (Bitfield-Mask: 0xff) */ +/* ======================================================== ULPSCR ========================================================= */ + #define R_MIPI_DSI_ULPSCR_CLENT_Pos (24UL) /*!< CLENT (Bit 24) */ + #define R_MIPI_DSI_ULPSCR_CLENT_Msk (0x1000000UL) /*!< CLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Pos (25UL) /*!< CLEXIT (Bit 25) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Msk (0x2000000UL) /*!< CLEXIT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Pos (28UL) /*!< DLENT (Bit 28) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Msk (0x10000000UL) /*!< DLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Pos (29UL) /*!< DLEXIT (Bit 29) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Msk (0x20000000UL) /*!< DLEXIT (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTCR ========================================================= */ + #define R_MIPI_DSI_RSTCR_SWRST_Pos (0UL) /*!< SWRST (Bit 0) */ + #define R_MIPI_DSI_RSTCR_SWRST_Msk (0x1UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Pos (16UL) /*!< FTXSTP (Bit 16) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Msk (0x10000UL) /*!< FTXSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTSR ========================================================= */ + #define R_MIPI_DSI_RSTSR_RSTHS_Pos (0UL) /*!< RSTHS (Bit 0) */ + #define R_MIPI_DSI_RSTSR_RSTHS_Msk (0x1UL) /*!< RSTHS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Pos (1UL) /*!< RSTLP (Bit 1) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Msk (0x2UL) /*!< RSTLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Pos (2UL) /*!< RSTAPB (Bit 2) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Msk (0x4UL) /*!< RSTAPB (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Pos (3UL) /*!< RSTAXI (Bit 3) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Msk (0x8UL) /*!< RSTAXI (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTV_Pos (4UL) /*!< RSTV (Bit 4) */ + #define R_MIPI_DSI_RSTSR_RSTV_Msk (0x10UL) /*!< RSTV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DSISETR ======================================================== */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Pos (0UL) /*!< MRPSZ (Bit 0) */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Msk (0xffffUL) /*!< MRPSZ (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Pos (16UL) /*!< ECCEN (Bit 16) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Msk (0x10000UL) /*!< ECCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Pos (20UL) /*!< VC0CRCEN (Bit 20) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Msk (0x100000UL) /*!< VC0CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Pos (21UL) /*!< VC1CRCEN (Bit 21) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Msk (0x200000UL) /*!< VC1CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Pos (22UL) /*!< VC2CRCEN (Bit 22) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Msk (0x400000UL) /*!< VC2CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Pos (23UL) /*!< VC3CRCEN (Bit 23) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Msk (0x800000UL) /*!< VC3CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_SCREN_Pos (29UL) /*!< SCREN (Bit 29) */ + #define R_MIPI_DSI_DSISETR_SCREN_Msk (0x20000000UL) /*!< SCREN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Pos (30UL) /*!< EXTEMD (Bit 30) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Msk (0x40000000UL) /*!< EXTEMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Pos (31UL) /*!< EOTPEN (Bit 31) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Msk (0x80000000UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TXPPD0R ======================================================== */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD1R ======================================================== */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD2R ======================================================== */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD3R ======================================================== */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ========================================================= RXSR ========================================================== */ + #define R_MIPI_DSI_RXSR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSCR ========================================================= */ + #define R_MIPI_DSI_RXSCR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSCR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSCR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSCR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSCR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSCR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIER ========================================================= */ + #define R_MIPI_DSI_RXIER_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXIER_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXIER_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXIER_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXIER_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXIER_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXIER_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXIER_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXIER_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXIER_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXIER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ==================================================== PRESPTOBTASETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Pos (0UL) /*!< PRTBTA (Bit 0) */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Msk (0xffffffffUL) /*!< PRTBTA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PRESPTOLPSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Pos (0UL) /*!< LPWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Msk (0xffffUL) /*!< LPWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Pos (16UL) /*!< LPRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Msk (0xffff0000UL) /*!< LPRTO (Bitfield-Mask: 0xffff) */ +/* ===================================================== PRESPTOHSSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Pos (0UL) /*!< HSWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Msk (0xffffUL) /*!< HSWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Pos (16UL) /*!< HSRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Msk (0xffff0000UL) /*!< HSRTO (Bitfield-Mask: 0xffff) */ +/* ======================================================= AKEPLATIR ======================================================= */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Pos (0UL) /*!< EREP (Bit 0) */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Msk (0xffffUL) /*!< EREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Pos (16UL) /*!< VC (Bit 16) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Msk (0xf0000UL) /*!< VC (Bitfield-Mask: 0x0f) */ +/* ======================================================= AKEPACMSR ======================================================= */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== AKEPSCR ======================================================== */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== RXRSSR ========================================================= */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSSCR ======================================================== */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRINFOOWSR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ===================================================== RXRINFOOWSCR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS0R ======================================================== */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS0R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS0R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS1R ======================================================== */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS1R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS1R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS2R ======================================================== */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS2R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS2R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS3R ======================================================== */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS3R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS3R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS0R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS1R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS2R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS3R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS0R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS1R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS2R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS3R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS0R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS1R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS2R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS3R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS0R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS1R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS2R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS3R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXPPD0R ======================================================== */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD1R ======================================================== */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD2R ======================================================== */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD3R ======================================================== */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ====================================================== HSTXTOSETR ======================================================= */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Msk (0xffffffffUL) /*!< HTXTO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== LRXHTOSETR ======================================================= */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Pos (0UL) /*!< LRXHTO (Bit 0) */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Msk (0xffffffffUL) /*!< LRXHTO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TATOSETR ======================================================== */ + #define R_MIPI_DSI_TATOSETR_TATO_Pos (0UL) /*!< TATO (Bit 0) */ + #define R_MIPI_DSI_TATOSETR_TATO_Msk (0xffffffffUL) /*!< TATO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FERRSR ========================================================= */ + #define R_MIPI_DSI_FERRSR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Pos (27UL) /*!< CLP0S (Bit 27) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Msk (0x8000000UL) /*!< CLP0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Pos (28UL) /*!< CLP1S (Bit 28) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Msk (0x10000000UL) /*!< CLP1S (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRSCR ======================================================== */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRIER ======================================================== */ + #define R_MIPI_DSI_FERRIER_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRIER_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRIER_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRIER_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRIER_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CLSTPTSETR ======================================================= */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Pos (2UL) /*!< CLKSTPT (Bit 2) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Msk (0xffcUL) /*!< CLKSTPT (Bitfield-Mask: 0x3ff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Pos (16UL) /*!< CLKBFHT (Bit 16) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Msk (0xff0000UL) /*!< CLKBFHT (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Pos (24UL) /*!< CLKKPT (Bit 24) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Msk (0xff000000UL) /*!< CLKKPT (Bitfield-Mask: 0xff) */ +/* ====================================================== LPTRNSTSETR ====================================================== */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Pos (0UL) /*!< GOLPBKT (Bit 0) */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Msk (0x3ffUL) /*!< GOLPBKT (Bitfield-Mask: 0x3ff) */ +/* ========================================================= PLSR ========================================================== */ + #define R_MIPI_DSI_PLSR_CLUAN_Pos (0UL) /*!< CLUAN (Bit 0) */ + #define R_MIPI_DSI_PLSR_CLUAN_Msk (0x1UL) /*!< CLUAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLSTP_Pos (1UL) /*!< CLSTP (Bit 1) */ + #define R_MIPI_DSI_PLSR_CLSTP_Msk (0x2UL) /*!< CLSTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Pos (2UL) /*!< DL0RLE (Bit 2) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Msk (0x4UL) /*!< DL0RLE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Pos (3UL) /*!< DL0RUE (Bit 3) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Msk (0x8UL) /*!< DL0RUE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Pos (4UL) /*!< DL0UAN (Bit 4) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Msk (0x10UL) /*!< DL0UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Pos (5UL) /*!< DL1UAN (Bit 5) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Msk (0x20UL) /*!< DL1UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_PLSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_PLSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLSCR ========================================================= */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLIER ========================================================= */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET0R ======================================================== */ + #define R_MIPI_DSI_VMSET0R_VSTART_Pos (0UL) /*!< VSTART (Bit 0) */ + #define R_MIPI_DSI_VMSET0R_VSTART_Msk (0x1UL) /*!< VSTART (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Pos (1UL) /*!< VSTOP (Bit 1) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Msk (0x2UL) /*!< VSTOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Pos (8UL) /*!< HSANOLP (Bit 8) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Msk (0x100UL) /*!< HSANOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Pos (9UL) /*!< HBPNOLP (Bit 9) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Msk (0x200UL) /*!< HBPNOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Pos (10UL) /*!< HFPNOLP (Bit 10) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Msk (0x400UL) /*!< HFPNOLP (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET1R ======================================================== */ + #define R_MIPI_DSI_VMSET1R_DLY_Pos (2UL) /*!< DLY (Bit 2) */ + #define R_MIPI_DSI_VMSET1R_DLY_Msk (0x3ffcUL) /*!< DLY (Bitfield-Mask: 0xfff) */ +/* ========================================================= VMSR ========================================================== */ + #define R_MIPI_DSI_VMSR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_VMSR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMSCR ========================================================= */ + #define R_MIPI_DSI_VMSCR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSCR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSCR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMIER ========================================================= */ + #define R_MIPI_DSI_VMIER_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMIER_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMIER_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMIER_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMIER_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= VMPPSETR ======================================================== */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Pos (15UL) /*!< TXESYNC (Bit 15) */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Msk (0x8000UL) /*!< TXESYNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMPPSETR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_VMPPSETR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_VMPPSETR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_VMPPSETR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ======================================================= VMVSSETR ======================================================== */ + #define R_MIPI_DSI_VMVSSETR_VSA_Pos (0UL) /*!< VSA (Bit 0) */ + #define R_MIPI_DSI_VMVSSETR_VSA_Msk (0xfffUL) /*!< VSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Pos (15UL) /*!< VSPOL (Bit 15) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Msk (0x8000UL) /*!< VSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Pos (16UL) /*!< VACT (Bit 16) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Msk (0x7fff0000UL) /*!< VACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMVPSETR ======================================================== */ + #define R_MIPI_DSI_VMVPSETR_VBP_Pos (0UL) /*!< VBP (Bit 0) */ + #define R_MIPI_DSI_VMVPSETR_VBP_Msk (0x1fffUL) /*!< VBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Pos (16UL) /*!< VFP (Bit 16) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Msk (0x1fff0000UL) /*!< VFP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= VMHSSETR ======================================================== */ + #define R_MIPI_DSI_VMHSSETR_HSA_Pos (0UL) /*!< HSA (Bit 0) */ + #define R_MIPI_DSI_VMHSSETR_HSA_Msk (0xfffUL) /*!< HSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Pos (15UL) /*!< HSPOL (Bit 15) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Msk (0x8000UL) /*!< HSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Pos (16UL) /*!< HACT (Bit 16) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Msk (0x7fff0000UL) /*!< HACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMHPSETR ======================================================== */ + #define R_MIPI_DSI_VMHPSETR_HBP_Pos (0UL) /*!< HBP (Bit 0) */ + #define R_MIPI_DSI_VMHPSETR_HBP_Msk (0x1fffUL) /*!< HBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Pos (16UL) /*!< HFP (Bit 16) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Msk (0x1fff0000UL) /*!< HFP (Bitfield-Mask: 0x1fff) */ +/* ====================================================== SQCH0SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH0SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH0SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH0SR ======================================================== */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0SCR ======================================================== */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0IER ======================================================== */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH1SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH1SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH1SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH1SR ======================================================== */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1SCR ======================================================== */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1IER ======================================================== */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH0DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH0DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH1DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH1DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MRMS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MRCPFB ========================================================= */ + #define R_MRMS_MRCPFB_MPFBEN_Pos (0UL) /*!< MPFBEN (Bit 0) */ + #define R_MRMS_MRCPFB_MPFBEN_Msk (0x1UL) /*!< MPFBEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCFREQ ======================================================== */ + #define R_MRMS_MRCFREQ_MRCMHZ_Pos (0UL) /*!< MRCMHZ (Bit 0) */ + #define R_MRMS_MRCFREQ_MRCMHZ_Msk (0x3ffUL) /*!< MRCMHZ (Bitfield-Mask: 0x3ff) */ + #define R_MRMS_MRCFREQ_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MRMS_MRCFREQ_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MREFREQ ======================================================== */ + #define R_MRMS_MREFREQ_MREMHZ_Pos (0UL) /*!< MREMHZ (Bit 0) */ + #define R_MRMS_MREFREQ_MREMHZ_Msk (0xffUL) /*!< MREMHZ (Bitfield-Mask: 0xff) */ + #define R_MRMS_MREFREQ_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MRMS_MREFREQ_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCDECC ======================================================== */ + #define R_MRMS_MRCDECC_DECDISC_Pos (0UL) /*!< DECDISC (Bit 0) */ + #define R_MRMS_MRCDECC_DECDISC_Msk (0x1UL) /*!< DECDISC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCDECC_ECCSELC_Pos (1UL) /*!< ECCSELC (Bit 1) */ + #define R_MRMS_MRCDECC_ECCSELC_Msk (0x2UL) /*!< ECCSELC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCDECC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCDECC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCRAEINT ======================================================= */ + #define R_MRMS_MRCRAEINT_INTENBDC_Pos (0UL) /*!< INTENBDC (Bit 0) */ + #define R_MRMS_MRCRAEINT_INTENBDC_Msk (0x1UL) /*!< INTENBDC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCRAEINT_INTENBTC_Pos (1UL) /*!< INTENBTC (Bit 1) */ + #define R_MRMS_MRCRAEINT_INTENBTC_Msk (0x2UL) /*!< INTENBTC (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCRAES ======================================================== */ + #define R_MRMS_MRCRAES_DECERRC_Pos (0UL) /*!< DECERRC (Bit 0) */ + #define R_MRMS_MRCRAES_DECERRC_Msk (0x1UL) /*!< DECERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCRAES_TEDERRC_Pos (1UL) /*!< TEDERRC (Bit 1) */ + #define R_MRMS_MRCRAES_TEDERRC_Msk (0x2UL) /*!< TEDERRC (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCRTEA ======================================================== */ + #define R_MRMS_MRCRTEA_MRCRTEA_Pos (5UL) /*!< MRCRTEA (Bit 5) */ + #define R_MRMS_MRCRTEA_MRCRTEA_Msk (0xffffffe0UL) /*!< MRCRTEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================== MRCRDEA ======================================================== */ + #define R_MRMS_MRCRDEA_MRCRDEA_Pos (5UL) /*!< MRCRDEA (Bit 5) */ + #define R_MRMS_MRCRDEA_MRCRDEA_Msk (0xffffffe0UL) /*!< MRCRDEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MRERAINT ======================================================== */ + #define R_MRMS_MRERAINT_INTENBDE_Pos (0UL) /*!< INTENBDE (Bit 0) */ + #define R_MRMS_MRERAINT_INTENBDE_Msk (0x1UL) /*!< INTENBDE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRERAINT_INTENBTE_Pos (1UL) /*!< INTENBTE (Bit 1) */ + #define R_MRMS_MRERAINT_INTENBTE_Msk (0x2UL) /*!< INTENBTE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRERAES ======================================================== */ + #define R_MRMS_MRERAES_DECERRE_Pos (0UL) /*!< DECERRE (Bit 0) */ + #define R_MRMS_MRERAES_DECERRE_Msk (0x1UL) /*!< DECERRE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRERAES_TEDERRE_Pos (1UL) /*!< TEDERRE (Bit 1) */ + #define R_MRMS_MRERAES_TEDERRE_Msk (0x2UL) /*!< TEDERRE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRERTEA ======================================================== */ + #define R_MRMS_MRERTEA_MRERTEA_Pos (4UL) /*!< MRERTEA (Bit 4) */ + #define R_MRMS_MRERTEA_MRERTEA_Msk (0xfffffff0UL) /*!< MRERTEA (Bitfield-Mask: 0xfffffff) */ +/* ======================================================== MRERDEA ======================================================== */ + #define R_MRMS_MRERDEA_MRERDEA_Pos (4UL) /*!< MRERDEA (Bit 4) */ + #define R_MRMS_MRERDEA_MRERDEA_Msk (0xfffffff0UL) /*!< MRERDEA (Bitfield-Mask: 0xfffffff) */ +/* ========================================================= MSAR ========================================================== */ + #define R_MRMS_MSAR_MREECCSA_Pos (0UL) /*!< MREECCSA (Bit 0) */ + #define R_MRMS_MSAR_MREECCSA_Msk (0x1UL) /*!< MREECCSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MREFREQSA_Pos (1UL) /*!< MREFREQSA (Bit 1) */ + #define R_MRMS_MSAR_MREFREQSA_Msk (0x2UL) /*!< MREFREQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCECCSA_Pos (2UL) /*!< MRCECCSA (Bit 2) */ + #define R_MRMS_MSAR_MRCECCSA_Msk (0x4UL) /*!< MRCECCSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCFREQSA_Pos (3UL) /*!< MRCFREQSA (Bit 3) */ + #define R_MRMS_MSAR_MRCFREQSA_Msk (0x8UL) /*!< MRCFREQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MPFBENSA_Pos (4UL) /*!< MPFBENSA (Bit 4) */ + #define R_MRMS_MSAR_MPFBENSA_Msk (0x10UL) /*!< MPFBENSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACICMISA_Pos (9UL) /*!< MACICMISA (Bit 9) */ + #define R_MRMS_MSAR_MACICMISA_Msk (0x200UL) /*!< MACICMISA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACICMRSA_Pos (10UL) /*!< MACICMRSA (Bit 10) */ + #define R_MRMS_MSAR_MACICMRSA_Msk (0x400UL) /*!< MACICMRSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACITRSA_Pos (11UL) /*!< MACITRSA (Bit 11) */ + #define R_MRMS_MSAR_MACITRSA_Msk (0x800UL) /*!< MACITRSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCPSA_Pos (13UL) /*!< MRCPSA (Bit 13) */ + #define R_MRMS_MSAR_MRCPSA_Msk (0x2000UL) /*!< MRCPSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MREPSEQSA_Pos (14UL) /*!< MREPSEQSA (Bit 14) */ + #define R_MRMS_MSAR_MREPSEQSA_Msk (0x4000UL) /*!< MREPSEQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCPSEQSA_Pos (15UL) /*!< MRCPSEQSA (Bit 15) */ + #define R_MRMS_MSAR_MRCPSEQSA_Msk (0x8000UL) /*!< MRCPSEQSA (Bitfield-Mask: 0x01) */ +/* ========================================================= MREZS ========================================================= */ + #define R_MRMS_MREZS_WHUKZF_Pos (0UL) /*!< WHUKZF (Bit 0) */ + #define R_MRMS_MREZS_WHUKZF_Msk (0x1UL) /*!< WHUKZF (Bitfield-Mask: 0x01) */ + #define R_MRMS_MREZS_WHUKEXE_Pos (1UL) /*!< WHUKEXE (Bit 1) */ + #define R_MRMS_MREZS_WHUKEXE_Msk (0x2UL) /*!< WHUKEXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MREZC ========================================================= */ + #define R_MRMS_MREZC_WHUKZE_Pos (0UL) /*!< WHUKZE (Bit 0) */ + #define R_MRMS_MREZC_WHUKZE_Msk (0x7UL) /*!< WHUKZE (Bitfield-Mask: 0x07) */ + #define R_MRMS_MREZC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MREZC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MASTAT ========================================================= */ + #define R_MRMS_MASTAT_MREAE_Pos (3UL) /*!< MREAE (Bit 3) */ + #define R_MRMS_MASTAT_MREAE_Msk (0x8UL) /*!< MREAE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_MRMS_MASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ +/* ======================================================== MPAEINT ======================================================== */ + #define R_MRMS_MPAEINT_MREAEIE_Pos (3UL) /*!< MREAEIE (Bit 3) */ + #define R_MRMS_MPAEINT_MREAEIE_Msk (0x8UL) /*!< MREAEIE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MPAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_MRMS_MPAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRDYIE ========================================================= */ + #define R_MRMS_MRDYIE_MRDYIE_Pos (0UL) /*!< MRDYIE (Bit 0) */ + #define R_MRMS_MRDYIE_MRDYIE_Msk (0x1UL) /*!< MRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSADDR ========================================================= */ + #define R_MRMS_MSADDR_MSADDR_Pos (0UL) /*!< MSADDR (Bit 0) */ + #define R_MRMS_MSADDR_MSADDR_Msk (0xffffffffUL) /*!< MSADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCNTSELR ======================================================== */ + #define R_MRMS_MCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_MRMS_MCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ======================================================= MCNTDTR0 ======================================================== */ + #define R_MRMS_MCNTDTR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_MRMS_MCNTDTR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCNTDTR1 ======================================================== */ + #define R_MRMS_MCNTDTR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_MRMS_MCNTDTR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCTRCNTR ======================================================== */ + #define R_MRMS_MCTRCNTR_TRTRG_Pos (0UL) /*!< TRTRG (Bit 0) */ + #define R_MRMS_MCTRCNTR_TRTRG_Msk (0x1UL) /*!< TRTRG (Bitfield-Mask: 0x01) */ + #define R_MRMS_MCTRCNTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MCTRCNTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MCTRLSR ======================================================== */ + #define R_MRMS_MCTRLSR_TRLIST_Pos (0UL) /*!< TRLIST (Bit 0) */ + #define R_MRMS_MCTRLSR_TRLIST_Msk (0x7UL) /*!< TRLIST (Bitfield-Mask: 0x07) */ +/* ======================================================= MCTRSTATR ======================================================= */ + #define R_MRMS_MCTRSTATR_TRBUSY_Pos (0UL) /*!< TRBUSY (Bit 0) */ + #define R_MRMS_MCTRSTATR_TRBUSY_Msk (0x1UL) /*!< TRBUSY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MCTRSTATR_TRMD_Pos (2UL) /*!< TRMD (Bit 2) */ + #define R_MRMS_MCTRSTATR_TRMD_Msk (0x4UL) /*!< TRMD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTATR ========================================================= */ + #define R_MRMS_MSTATR_CFGSETERR_Pos (5UL) /*!< CFGSETERR (Bit 5) */ + #define R_MRMS_MSTATR_CFGSETERR_Msk (0x20UL) /*!< CFGSETERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_MRMS_MSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_MRMS_MSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_MRDY_Pos (15UL) /*!< MRDY (Bit 15) */ + #define R_MRMS_MSTATR_MRDY_Msk (0x8000UL) /*!< MRDY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_TZFERR_Pos (19UL) /*!< TZFERR (Bit 19) */ + #define R_MRMS_MSTATR_TZFERR_Msk (0x80000UL) /*!< TZFERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_MRMS_MSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_MRMS_MSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_MRMS_MSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ +/* ======================================================== MENTRYR ======================================================== */ + #define R_MRMS_MENTRYR_MENTRY_Pos (7UL) /*!< MENTRY (Bit 7) */ + #define R_MRMS_MENTRYR_MENTRY_Msk (0x80UL) /*!< MENTRY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MSUINITR ======================================================== */ + #define R_MRMS_MSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_MRMS_MSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MCMDR ========================================================= */ + #define R_MRMS_MCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_MRMS_MCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ + #define R_MRMS_MCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_MRMS_MCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ +/* ======================================================= MSUASMON ======================================================== */ + #define R_MRMS_MSUASMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_MRMS_MSUASMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSUASMON_BTSIZE_Pos (29UL) /*!< BTSIZE (Bit 29) */ + #define R_MRMS_MSUASMON_BTSIZE_Msk (0x60000000UL) /*!< BTSIZE (Bitfield-Mask: 0x03) */ + #define R_MRMS_MSUASMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_MRMS_MSUASMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ +/* ======================================================== MSUACR ========================================================= */ + #define R_MRMS_MSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_MRMS_MSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_MRMS_MSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MRPSC ========================================================= */ + #define R_MRMS_MRPSC_MHSPEN_Pos (0UL) /*!< MHSPEN (Bit 0) */ + #define R_MRMS_MRPSC_MHSPEN_Msk (0x1UL) /*!< MHSPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCPC0 ========================================================= */ + #define R_MRMS_MRCPC0_MRCPNEN_Pos (0UL) /*!< MRCPNEN (Bit 0) */ + #define R_MRMS_MRCPC0_MRCPNEN_Msk (0x1UL) /*!< MRCPNEN (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPC0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCPC0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCPC1 ========================================================= */ + #define R_MRMS_MRCPC1_MRCPSEN_Pos (0UL) /*!< MRCPSEN (Bit 0) */ + #define R_MRMS_MRCPC1_MRCPSEN_Msk (0x1UL) /*!< MRCPSEN (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPC1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCPC1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCBPROT0 ======================================================= */ + #define R_MRMS_MRCBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_MRMS_MRCBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCBPROT1 ======================================================= */ + #define R_MRMS_MRCBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_MRMS_MRCBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MRCPS ========================================================= */ + #define R_MRMS_MRCPS_PRGERRC_Pos (0UL) /*!< PRGERRC (Bit 0) */ + #define R_MRMS_MRCPS_PRGERRC_Msk (0x1UL) /*!< PRGERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ECCERRC_Pos (1UL) /*!< ECCERRC (Bit 1) */ + #define R_MRMS_MRCPS_ECCERRC_Msk (0x2UL) /*!< ECCERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ABUFEMP_Pos (5UL) /*!< ABUFEMP (Bit 5) */ + #define R_MRMS_MRCPS_ABUFEMP_Msk (0x20UL) /*!< ABUFEMP (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ABUFFULL_Pos (6UL) /*!< ABUFFULL (Bit 6) */ + #define R_MRMS_MRCPS_ABUFFULL_Msk (0x40UL) /*!< ABUFFULL (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_PRGBSYC_Pos (7UL) /*!< PRGBSYC (Bit 7) */ + #define R_MRMS_MRCPS_PRGBSYC_Msk (0x80UL) /*!< PRGBSYC (Bitfield-Mask: 0x01) */ +/* ======================================================= MRCPAEINT ======================================================= */ + #define R_MRMS_MRCPAEINT_MRCAEIE_Pos (7UL) /*!< MRCAEIE (Bit 7) */ + #define R_MRMS_MRCPAEINT_MRCAEIE_Msk (0x80UL) /*!< MRCAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCPEA ========================================================= */ + #define R_MRMS_MRCPEA_MCPEA_Pos (5UL) /*!< MCPEA (Bit 5) */ + #define R_MRMS_MRCPEA_MCPEA_Msk (0xffffffe0UL) /*!< MCPEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================== MRCFLR ========================================================= */ + #define R_MRMS_MRCFLR_MRCFL_Pos (0UL) /*!< MRCFL (Bit 0) */ + #define R_MRMS_MRCFLR_MRCFL_Msk (0x1UL) /*!< MRCFL (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCFLR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCFLR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCEECC ======================================================== */ + #define R_MRMS_MRCEECC_ECCBYPC_Pos (0UL) /*!< ECCBYPC (Bit 0) */ + #define R_MRMS_MRCEECC_ECCBYPC_Msk (0x1UL) /*!< ECCBYPC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCEECC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCEECC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_NPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_NPU_ID_arch_major_rev_Pos (28UL) /*!< arch_major_rev (Bit 28) */ + #define R_NPU_ID_arch_major_rev_Msk (0xf0000000UL) /*!< arch_major_rev (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_arch_minor_rev_Pos (20UL) /*!< arch_minor_rev (Bit 20) */ + #define R_NPU_ID_arch_minor_rev_Msk (0xff00000UL) /*!< arch_minor_rev (Bitfield-Mask: 0xff) */ + #define R_NPU_ID_arch_patch_rev_Pos (16UL) /*!< arch_patch_rev (Bit 16) */ + #define R_NPU_ID_arch_patch_rev_Msk (0xf0000UL) /*!< arch_patch_rev (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_product_major_Pos (12UL) /*!< product_major (Bit 12) */ + #define R_NPU_ID_product_major_Msk (0xf000UL) /*!< product_major (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_major_Pos (8UL) /*!< version_major (Bit 8) */ + #define R_NPU_ID_version_major_Msk (0xf00UL) /*!< version_major (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_minor_Pos (4UL) /*!< version_minor (Bit 4) */ + #define R_NPU_ID_version_minor_Msk (0xf0UL) /*!< version_minor (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_status_Pos (0UL) /*!< version_status (Bit 0) */ + #define R_NPU_ID_version_status_Msk (0xfUL) /*!< version_status (Bitfield-Mask: 0x0f) */ +/* ======================================================== STATUS ========================================================= */ + #define R_NPU_STATUS_irq_history_mask_Pos (16UL) /*!< irq_history_mask (Bit 16) */ + #define R_NPU_STATUS_irq_history_mask_Msk (0xffff0000UL) /*!< irq_history_mask (Bitfield-Mask: 0xffff) */ + #define R_NPU_STATUS_faulting_channel_Pos (12UL) /*!< faulting_channel (Bit 12) */ + #define R_NPU_STATUS_faulting_channel_Msk (0xf000UL) /*!< faulting_channel (Bitfield-Mask: 0x0f) */ + #define R_NPU_STATUS_faulting_interface_Pos (11UL) /*!< faulting_interface (Bit 11) */ + #define R_NPU_STATUS_faulting_interface_Msk (0x800UL) /*!< faulting_interface (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_ecc_fault_Pos (8UL) /*!< ecc_fault (Bit 8) */ + #define R_NPU_STATUS_ecc_fault_Msk (0x100UL) /*!< ecc_fault (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_pmu_irq_raised_Pos (6UL) /*!< pmu_irq_raised (Bit 6) */ + #define R_NPU_STATUS_pmu_irq_raised_Msk (0x40UL) /*!< pmu_irq_raised (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_cmd_end_reached_Pos (5UL) /*!< cmd_end_reached (Bit 5) */ + #define R_NPU_STATUS_cmd_end_reached_Msk (0x20UL) /*!< cmd_end_reached (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_cmd_parse_error_Pos (4UL) /*!< cmd_parse_error (Bit 4) */ + #define R_NPU_STATUS_cmd_parse_error_Msk (0x10UL) /*!< cmd_parse_error (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_reset_status_Pos (3UL) /*!< reset_status (Bit 3) */ + #define R_NPU_STATUS_reset_status_Msk (0x8UL) /*!< reset_status (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_bus_status_Pos (2UL) /*!< bus_status (Bit 2) */ + #define R_NPU_STATUS_bus_status_Msk (0x4UL) /*!< bus_status (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_irq_raised_Pos (1UL) /*!< irq_raised (Bit 1) */ + #define R_NPU_STATUS_irq_raised_Msk (0x2UL) /*!< irq_raised (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_state_Pos (0UL) /*!< state (Bit 0) */ + #define R_NPU_STATUS_state_Msk (0x1UL) /*!< state (Bitfield-Mask: 0x01) */ +/* ========================================================== CMD ========================================================== */ + #define R_NPU_CMD_clear_irq_history_Pos (16UL) /*!< clear_irq_history (Bit 16) */ + #define R_NPU_CMD_clear_irq_history_Msk (0xffff0000UL) /*!< clear_irq_history (Bitfield-Mask: 0xffff) */ + #define R_NPU_CMD_power_q_enable_Pos (3UL) /*!< power_q_enable (Bit 3) */ + #define R_NPU_CMD_power_q_enable_Msk (0x8UL) /*!< power_q_enable (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_clock_q_enable_Pos (2UL) /*!< clock_q_enable (Bit 2) */ + #define R_NPU_CMD_clock_q_enable_Msk (0x4UL) /*!< clock_q_enable (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_clear_irq_Pos (1UL) /*!< clear_irq (Bit 1) */ + #define R_NPU_CMD_clear_irq_Msk (0x2UL) /*!< clear_irq (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_transition_to_running_state_Pos (0UL) /*!< transition_to_running_state (Bit 0) */ + #define R_NPU_CMD_transition_to_running_state_Msk (0x1UL) /*!< transition_to_running_state (Bitfield-Mask: 0x01) */ +/* ========================================================= RESET ========================================================= */ + #define R_NPU_RESET_pending_CSL_Pos (1UL) /*!< pending_CSL (Bit 1) */ + #define R_NPU_RESET_pending_CSL_Msk (0x2UL) /*!< pending_CSL (Bitfield-Mask: 0x01) */ + #define R_NPU_RESET_pending_CPL_Pos (0UL) /*!< pending_CPL (Bit 0) */ + #define R_NPU_RESET_pending_CPL_Msk (0x1UL) /*!< pending_CPL (Bitfield-Mask: 0x01) */ +/* ======================================================== QBASE0 ========================================================= */ + #define R_NPU_QBASE0_QBASE0_Pos (0UL) /*!< QBASE0 (Bit 0) */ + #define R_NPU_QBASE0_QBASE0_Msk (0xffffffffUL) /*!< QBASE0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== QBASE1 ========================================================= */ + #define R_NPU_QBASE1_QBASE1_Pos (0UL) /*!< QBASE1 (Bit 0) */ + #define R_NPU_QBASE1_QBASE1_Msk (0xffffffffUL) /*!< QBASE1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= QREAD ========================================================= */ + #define R_NPU_QREAD_QREAD_Pos (0UL) /*!< QREAD (Bit 0) */ + #define R_NPU_QREAD_QREAD_Msk (0xffffffffUL) /*!< QREAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== QCONFIG ======================================================== */ + #define R_NPU_QCONFIG_QCONFIG_Pos (0UL) /*!< QCONFIG (Bit 0) */ + #define R_NPU_QCONFIG_QCONFIG_Msk (0xffffffffUL) /*!< QCONFIG (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= QSIZE ========================================================= */ + #define R_NPU_QSIZE_QSIZE_Pos (0UL) /*!< QSIZE (Bit 0) */ + #define R_NPU_QSIZE_QSIZE_Msk (0xffffffffUL) /*!< QSIZE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PROT ========================================================== */ + #define R_NPU_PROT_active_CSL_Pos (1UL) /*!< active_CSL (Bit 1) */ + #define R_NPU_PROT_active_CSL_Msk (0x2UL) /*!< active_CSL (Bitfield-Mask: 0x01) */ + #define R_NPU_PROT_active_CPL_Pos (0UL) /*!< active_CPL (Bit 0) */ + #define R_NPU_PROT_active_CPL_Msk (0x1UL) /*!< active_CPL (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG ========================================================= */ + #define R_NPU_CONFIG_product_Pos (28UL) /*!< product (Bit 28) */ + #define R_NPU_CONFIG_product_Msk (0xf0000000UL) /*!< product (Bitfield-Mask: 0x0f) */ + #define R_NPU_CONFIG_custom_dma_Pos (27UL) /*!< custom_dma (Bit 27) */ + #define R_NPU_CONFIG_custom_dma_Msk (0x8000000UL) /*!< custom_dma (Bitfield-Mask: 0x01) */ + #define R_NPU_CONFIG_shram_size_Pos (8UL) /*!< shram_size (Bit 8) */ + #define R_NPU_CONFIG_shram_size_Msk (0xff00UL) /*!< shram_size (Bitfield-Mask: 0xff) */ + #define R_NPU_CONFIG_cmd_stream_version_Pos (4UL) /*!< cmd_stream_version (Bit 4) */ + #define R_NPU_CONFIG_cmd_stream_version_Msk (0xf0UL) /*!< cmd_stream_version (Bitfield-Mask: 0x0f) */ + #define R_NPU_CONFIG_macs_per_cc_Pos (0UL) /*!< macs_per_cc (Bit 0) */ + #define R_NPU_CONFIG_macs_per_cc_Msk (0xfUL) /*!< macs_per_cc (Bitfield-Mask: 0x0f) */ +/* ========================================================= LOCK ========================================================== */ + #define R_NPU_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_NPU_LOCK_LOCK_Msk (0xffffffffUL) /*!< LOCK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= REGIONCFG ======================================================= */ + #define R_NPU_REGIONCFG_region7_Pos (14UL) /*!< region7 (Bit 14) */ + #define R_NPU_REGIONCFG_region7_Msk (0xc000UL) /*!< region7 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region6_Pos (12UL) /*!< region6 (Bit 12) */ + #define R_NPU_REGIONCFG_region6_Msk (0x3000UL) /*!< region6 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region5_Pos (10UL) /*!< region5 (Bit 10) */ + #define R_NPU_REGIONCFG_region5_Msk (0xc00UL) /*!< region5 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region4_Pos (8UL) /*!< region4 (Bit 8) */ + #define R_NPU_REGIONCFG_region4_Msk (0x300UL) /*!< region4 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region3_Pos (6UL) /*!< region3 (Bit 6) */ + #define R_NPU_REGIONCFG_region3_Msk (0xc0UL) /*!< region3 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region2_Pos (4UL) /*!< region2 (Bit 4) */ + #define R_NPU_REGIONCFG_region2_Msk (0x30UL) /*!< region2 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region1_Pos (2UL) /*!< region1 (Bit 2) */ + #define R_NPU_REGIONCFG_region1_Msk (0xcUL) /*!< region1 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region0_Pos (0UL) /*!< region0 (Bit 0) */ + #define R_NPU_REGIONCFG_region0_Msk (0x3UL) /*!< region0 (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT0 ======================================================= */ + #define R_NPU_AXI_LIMIT0_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT0_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT0_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT0_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT0_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT1 ======================================================= */ + #define R_NPU_AXI_LIMIT1_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT1_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT1_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT1_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT1_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT2 ======================================================= */ + #define R_NPU_AXI_LIMIT2_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT2_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT2_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT2_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT2_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT3 ======================================================= */ + #define R_NPU_AXI_LIMIT3_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT3_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT3_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT3_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT3_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ======================================================== BASEP0 ========================================================= */ + #define R_NPU_BASEP0_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP0_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP1 ========================================================= */ + #define R_NPU_BASEP1_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP1_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP2 ========================================================= */ + #define R_NPU_BASEP2_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP2_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP3 ========================================================= */ + #define R_NPU_BASEP3_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP3_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP4 ========================================================= */ + #define R_NPU_BASEP4_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP4_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP5 ========================================================= */ + #define R_NPU_BASEP5_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP5_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP6 ========================================================= */ + #define R_NPU_BASEP6_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP6_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP7 ========================================================= */ + #define R_NPU_BASEP7_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP7_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP8 ========================================================= */ + #define R_NPU_BASEP8_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP8_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP9 ========================================================= */ + #define R_NPU_BASEP9_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP9_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP10 ======================================================== */ + #define R_NPU_BASEP10_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP10_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP11 ======================================================== */ + #define R_NPU_BASEP11_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP11_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP12 ======================================================== */ + #define R_NPU_BASEP12_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP12_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP13 ======================================================== */ + #define R_NPU_BASEP13_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP13_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP14 ======================================================== */ + #define R_NPU_BASEP14_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP14_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP15 ======================================================== */ + #define R_NPU_BASEP15_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP15_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID4 ========================================================== */ + #define R_NPU_PID4_PID4_Pos (0UL) /*!< PID4 (Bit 0) */ + #define R_NPU_PID4_PID4_Msk (0xffffffffUL) /*!< PID4 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID5 ========================================================== */ + #define R_NPU_PID5_PID5_Pos (0UL) /*!< PID5 (Bit 0) */ + #define R_NPU_PID5_PID5_Msk (0xffffffffUL) /*!< PID5 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID6 ========================================================== */ + #define R_NPU_PID6_PID6_Pos (0UL) /*!< PID6 (Bit 0) */ + #define R_NPU_PID6_PID6_Msk (0xffffffffUL) /*!< PID6 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID7 ========================================================== */ + #define R_NPU_PID7_PID7_Pos (0UL) /*!< PID7 (Bit 0) */ + #define R_NPU_PID7_PID7_Msk (0xffffffffUL) /*!< PID7 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID0 ========================================================== */ + #define R_NPU_PID0_PID0_Pos (0UL) /*!< PID0 (Bit 0) */ + #define R_NPU_PID0_PID0_Msk (0xffffffffUL) /*!< PID0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID1 ========================================================== */ + #define R_NPU_PID1_PID1_Pos (0UL) /*!< PID1 (Bit 0) */ + #define R_NPU_PID1_PID1_Msk (0xffffffffUL) /*!< PID1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID2 ========================================================== */ + #define R_NPU_PID2_PID2_Pos (0UL) /*!< PID2 (Bit 0) */ + #define R_NPU_PID2_PID2_Msk (0xffffffffUL) /*!< PID2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID3 ========================================================== */ + #define R_NPU_PID3_PID3_Pos (0UL) /*!< PID3 (Bit 0) */ + #define R_NPU_PID3_PID3_Msk (0xffffffffUL) /*!< PID3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID0 ========================================================== */ + #define R_NPU_CID0_CID0_Pos (0UL) /*!< CID0 (Bit 0) */ + #define R_NPU_CID0_CID0_Msk (0xffffffffUL) /*!< CID0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID1 ========================================================== */ + #define R_NPU_CID1_CID1_Pos (0UL) /*!< CID1 (Bit 0) */ + #define R_NPU_CID1_CID1_Msk (0xffffffffUL) /*!< CID1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID2 ========================================================== */ + #define R_NPU_CID2_CID2_Pos (0UL) /*!< CID2 (Bit 0) */ + #define R_NPU_CID2_CID2_Msk (0xffffffffUL) /*!< CID2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID3 ========================================================== */ + #define R_NPU_CID3_CID3_Pos (0UL) /*!< CID3 (Bit 0) */ + #define R_NPU_CID3_CID3_Msk (0xffffffffUL) /*!< CID3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PMCR ========================================================== */ + #define R_NPU_PMCR_num_event_cnt_Pos (11UL) /*!< num_event_cnt (Bit 11) */ + #define R_NPU_PMCR_num_event_cnt_Msk (0xf800UL) /*!< num_event_cnt (Bitfield-Mask: 0x1f) */ + #define R_NPU_PMCR_mask_en_Pos (3UL) /*!< mask_en (Bit 3) */ + #define R_NPU_PMCR_mask_en_Msk (0x8UL) /*!< mask_en (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_cycle_cnt_rst_Pos (2UL) /*!< cycle_cnt_rst (Bit 2) */ + #define R_NPU_PMCR_cycle_cnt_rst_Msk (0x4UL) /*!< cycle_cnt_rst (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_event_cnt_rst_Pos (1UL) /*!< event_cnt_rst (Bit 1) */ + #define R_NPU_PMCR_event_cnt_rst_Msk (0x2UL) /*!< event_cnt_rst (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_cnt_en_Pos (0UL) /*!< cnt_en (Bit 0) */ + #define R_NPU_PMCR_cnt_en_Msk (0x1UL) /*!< cnt_en (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCNTENSET ======================================================= */ + #define R_NPU_PMCNTENSET_CYCLE_CNT_Pos (31UL) /*!< CYCLE_CNT (Bit 31) */ + #define R_NPU_PMCNTENSET_CYCLE_CNT_Msk (0x80000000UL) /*!< CYCLE_CNT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_3_Pos (3UL) /*!< EVENT_CNT_3 (Bit 3) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_3_Msk (0x8UL) /*!< EVENT_CNT_3 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_2_Pos (2UL) /*!< EVENT_CNT_2 (Bit 2) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_2_Msk (0x4UL) /*!< EVENT_CNT_2 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_1_Pos (1UL) /*!< EVENT_CNT_1 (Bit 1) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_1_Msk (0x2UL) /*!< EVENT_CNT_1 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_0_Pos (0UL) /*!< EVENT_CNT_0 (Bit 0) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_0_Msk (0x1UL) /*!< EVENT_CNT_0 (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCNTENCLR ======================================================= */ + #define R_NPU_PMCNTENCLR_CYCLE_CNT_Pos (31UL) /*!< CYCLE_CNT (Bit 31) */ + #define R_NPU_PMCNTENCLR_CYCLE_CNT_Msk (0x80000000UL) /*!< CYCLE_CNT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_3_Pos (3UL) /*!< EVENT_CNT_3 (Bit 3) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_3_Msk (0x8UL) /*!< EVENT_CNT_3 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_2_Pos (2UL) /*!< EVENT_CNT_2 (Bit 2) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_2_Msk (0x4UL) /*!< EVENT_CNT_2 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_1_Pos (1UL) /*!< EVENT_CNT_1 (Bit 1) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_1_Msk (0x2UL) /*!< EVENT_CNT_1 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_0_Pos (0UL) /*!< EVENT_CNT_0 (Bit 0) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_0_Msk (0x1UL) /*!< EVENT_CNT_0 (Bitfield-Mask: 0x01) */ +/* ======================================================= PMOVSSET ======================================================== */ + #define R_NPU_PMOVSSET_CYCLE_CNT_OVF_Pos (31UL) /*!< CYCLE_CNT_OVF (Bit 31) */ + #define R_NPU_PMOVSSET_CYCLE_CNT_OVF_Msk (0x80000000UL) /*!< CYCLE_CNT_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_3_OVF_Pos (3UL) /*!< EVENT_CNT_3_OVF (Bit 3) */ + #define R_NPU_PMOVSSET_EVENT_CNT_3_OVF_Msk (0x8UL) /*!< EVENT_CNT_3_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_2_OVF_Pos (2UL) /*!< EVENT_CNT_2_OVF (Bit 2) */ + #define R_NPU_PMOVSSET_EVENT_CNT_2_OVF_Msk (0x4UL) /*!< EVENT_CNT_2_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_1_OVF_Pos (1UL) /*!< EVENT_CNT_1_OVF (Bit 1) */ + #define R_NPU_PMOVSSET_EVENT_CNT_1_OVF_Msk (0x2UL) /*!< EVENT_CNT_1_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_0_OVF_Pos (0UL) /*!< EVENT_CNT_0_OVF (Bit 0) */ + #define R_NPU_PMOVSSET_EVENT_CNT_0_OVF_Msk (0x1UL) /*!< EVENT_CNT_0_OVF (Bitfield-Mask: 0x01) */ +/* ======================================================= PMOVSCLR ======================================================== */ + #define R_NPU_PMOVSCLR_CYCLE_CNT_OVF_Pos (31UL) /*!< CYCLE_CNT_OVF (Bit 31) */ + #define R_NPU_PMOVSCLR_CYCLE_CNT_OVF_Msk (0x80000000UL) /*!< CYCLE_CNT_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_3_OVF_Pos (3UL) /*!< EVENT_CNT_3_OVF (Bit 3) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_3_OVF_Msk (0x8UL) /*!< EVENT_CNT_3_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_2_OVF_Pos (2UL) /*!< EVENT_CNT_2_OVF (Bit 2) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_2_OVF_Msk (0x4UL) /*!< EVENT_CNT_2_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_1_OVF_Pos (1UL) /*!< EVENT_CNT_1_OVF (Bit 1) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_1_OVF_Msk (0x2UL) /*!< EVENT_CNT_1_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_0_OVF_Pos (0UL) /*!< EVENT_CNT_0_OVF (Bit 0) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_0_OVF_Msk (0x1UL) /*!< EVENT_CNT_0_OVF (Bitfield-Mask: 0x01) */ +/* ======================================================= PMINTSET ======================================================== */ + #define R_NPU_PMINTSET_CYCLE_CNT_INT_Pos (31UL) /*!< CYCLE_CNT_INT (Bit 31) */ + #define R_NPU_PMINTSET_CYCLE_CNT_INT_Msk (0x80000000UL) /*!< CYCLE_CNT_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_3_INT_Pos (3UL) /*!< EVENT_CNT_3_INT (Bit 3) */ + #define R_NPU_PMINTSET_EVENT_CNT_3_INT_Msk (0x8UL) /*!< EVENT_CNT_3_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_2_INT_Pos (2UL) /*!< EVENT_CNT_2_INT (Bit 2) */ + #define R_NPU_PMINTSET_EVENT_CNT_2_INT_Msk (0x4UL) /*!< EVENT_CNT_2_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_1_INT_Pos (1UL) /*!< EVENT_CNT_1_INT (Bit 1) */ + #define R_NPU_PMINTSET_EVENT_CNT_1_INT_Msk (0x2UL) /*!< EVENT_CNT_1_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_0_INT_Pos (0UL) /*!< EVENT_CNT_0_INT (Bit 0) */ + #define R_NPU_PMINTSET_EVENT_CNT_0_INT_Msk (0x1UL) /*!< EVENT_CNT_0_INT (Bitfield-Mask: 0x01) */ +/* ======================================================= PMINTCLR ======================================================== */ + #define R_NPU_PMINTCLR_CYCLE_CNT_INT_Pos (31UL) /*!< CYCLE_CNT_INT (Bit 31) */ + #define R_NPU_PMINTCLR_CYCLE_CNT_INT_Msk (0x80000000UL) /*!< CYCLE_CNT_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_3_INT_Pos (3UL) /*!< EVENT_CNT_3_INT (Bit 3) */ + #define R_NPU_PMINTCLR_EVENT_CNT_3_INT_Msk (0x8UL) /*!< EVENT_CNT_3_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_2_INT_Pos (2UL) /*!< EVENT_CNT_2_INT (Bit 2) */ + #define R_NPU_PMINTCLR_EVENT_CNT_2_INT_Msk (0x4UL) /*!< EVENT_CNT_2_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_1_INT_Pos (1UL) /*!< EVENT_CNT_1_INT (Bit 1) */ + #define R_NPU_PMINTCLR_EVENT_CNT_1_INT_Msk (0x2UL) /*!< EVENT_CNT_1_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_0_INT_Pos (0UL) /*!< EVENT_CNT_0_INT (Bit 0) */ + #define R_NPU_PMINTCLR_EVENT_CNT_0_INT_Msk (0x1UL) /*!< EVENT_CNT_0_INT (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCCNTR_LO ======================================================= */ + #define R_NPU_PMCCNTR_LO_CYCLE_CNT_LO_Pos (0UL) /*!< CYCLE_CNT_LO (Bit 0) */ + #define R_NPU_PMCCNTR_LO_CYCLE_CNT_LO_Msk (0xffffffffUL) /*!< CYCLE_CNT_LO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMCCNTR_HI ======================================================= */ + #define R_NPU_PMCCNTR_HI_CYCLE_CNT_HI_Pos (0UL) /*!< CYCLE_CNT_HI (Bit 0) */ + #define R_NPU_PMCCNTR_HI_CYCLE_CNT_HI_Msk (0xffffffffUL) /*!< CYCLE_CNT_HI (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMCAXI_CHAN ====================================================== */ + #define R_NPU_PMCAXI_CHAN_BW_CH_SEL_EN_Pos (10UL) /*!< BW_CH_SEL_EN (Bit 10) */ + #define R_NPU_PMCAXI_CHAN_BW_CH_SEL_EN_Msk (0x400UL) /*!< BW_CH_SEL_EN (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCAXI_CHAN_AXI_CNT_SEL_Pos (8UL) /*!< AXI_CNT_SEL (Bit 8) */ + #define R_NPU_PMCAXI_CHAN_AXI_CNT_SEL_Msk (0x300UL) /*!< AXI_CNT_SEL (Bitfield-Mask: 0x03) */ + #define R_NPU_PMCAXI_CHAN_CH_SEL_Pos (0UL) /*!< CH_SEL (Bit 0) */ + #define R_NPU_PMCAXI_CHAN_CH_SEL_Msk (0xfUL) /*!< CH_SEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== PMU_EVCNTR0 ====================================================== */ + #define R_NPU_PMU_EVCNTR0_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR0_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR1 ====================================================== */ + #define R_NPU_PMU_EVCNTR1_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR1_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR2 ====================================================== */ + #define R_NPU_PMU_EVCNTR2_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR2_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR3 ====================================================== */ + #define R_NPU_PMU_EVCNTR3_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR3_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER0 ====================================================== */ + #define R_NPU_PMU_EVTYPER0_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER0_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER1 ====================================================== */ + #define R_NPU_PMU_EVTYPER1_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER1_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER2 ====================================================== */ + #define R_NPU_PMU_EVTYPER2_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER2_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER3 ====================================================== */ + #define R_NPU_PMU_EVTYPER3_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER3_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_PDM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PDCSTRTR ======================================================== */ + #define R_PDM_PDCSTRTR_STRTRG0_Pos (0UL) /*!< STRTRG0 (Bit 0) */ + #define R_PDM_PDCSTRTR_STRTRG0_Msk (0x1UL) /*!< STRTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTRTR_STRTRG1_Pos (1UL) /*!< STRTRG1 (Bit 1) */ + #define R_PDM_PDCSTRTR_STRTRG1_Msk (0x2UL) /*!< STRTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTRTR_STRTRG2_Pos (2UL) /*!< STRTRG2 (Bit 2) */ + #define R_PDM_PDCSTRTR_STRTRG2_Msk (0x4UL) /*!< STRTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCSTPTR ======================================================== */ + #define R_PDM_PDCSTPTR_STPTRG0_Pos (0UL) /*!< STPTRG0 (Bit 0) */ + #define R_PDM_PDCSTPTR_STPTRG0_Msk (0x1UL) /*!< STPTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTPTR_STPTRG1_Pos (1UL) /*!< STPTRG1 (Bit 1) */ + #define R_PDM_PDCSTPTR_STPTRG1_Msk (0x2UL) /*!< STPTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTPTR_STPTRG2_Pos (2UL) /*!< STPTRG2 (Bit 2) */ + #define R_PDM_PDCSTPTR_STPTRG2_Msk (0x4UL) /*!< STPTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCCHGTR ======================================================== */ + #define R_PDM_PDCCHGTR_CHGTRG0_Pos (0UL) /*!< CHGTRG0 (Bit 0) */ + #define R_PDM_PDCCHGTR_CHGTRG0_Msk (0x1UL) /*!< CHGTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCCHGTR_CHGTRG1_Pos (1UL) /*!< CHGTRG1 (Bit 1) */ + #define R_PDM_PDCCHGTR_CHGTRG1_Msk (0x2UL) /*!< CHGTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCCHGTR_CHGTRG2_Pos (2UL) /*!< CHGTRG2 (Bit 2) */ + #define R_PDM_PDCCHGTR_CHGTRG2_Msk (0x4UL) /*!< CHGTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCICR ========================================================= */ + #define R_PDM_PDCICR_ISDE0_Pos (8UL) /*!< ISDE0 (Bit 8) */ + #define R_PDM_PDCICR_ISDE0_Msk (0x100UL) /*!< ISDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_ISDE1_Pos (9UL) /*!< ISDE1 (Bit 9) */ + #define R_PDM_PDCICR_ISDE1_Msk (0x200UL) /*!< ISDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_ISDE2_Pos (10UL) /*!< ISDE2 (Bit 10) */ + #define R_PDM_PDCICR_ISDE2_Msk (0x400UL) /*!< ISDE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE0_Pos (16UL) /*!< IDRE0 (Bit 16) */ + #define R_PDM_PDCICR_IDRE0_Msk (0x10000UL) /*!< IDRE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE1_Pos (17UL) /*!< IDRE1 (Bit 17) */ + #define R_PDM_PDCICR_IDRE1_Msk (0x20000UL) /*!< IDRE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE2_Pos (18UL) /*!< IDRE2 (Bit 18) */ + #define R_PDM_PDCICR_IDRE2_Msk (0x40000UL) /*!< IDRE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE0_Pos (24UL) /*!< IEDE0 (Bit 24) */ + #define R_PDM_PDCICR_IEDE0_Msk (0x1000000UL) /*!< IEDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE1_Pos (25UL) /*!< IEDE1 (Bit 25) */ + #define R_PDM_PDCICR_IEDE1_Msk (0x2000000UL) /*!< IEDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE2_Pos (26UL) /*!< IEDE2 (Bit 26) */ + #define R_PDM_PDCICR_IEDE2_Msk (0x4000000UL) /*!< IEDE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= PDCSR ========================================================= */ + #define R_PDM_PDCSR_STATE0_Pos (0UL) /*!< STATE0 (Bit 0) */ + #define R_PDM_PDCSR_STATE0_Msk (0x1UL) /*!< STATE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_STATE1_Pos (1UL) /*!< STATE1 (Bit 1) */ + #define R_PDM_PDCSR_STATE1_Msk (0x2UL) /*!< STATE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_STATE2_Pos (2UL) /*!< STATE2 (Bit 2) */ + #define R_PDM_PDCSR_STATE2_Msk (0x4UL) /*!< STATE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF0_Pos (8UL) /*!< SDF0 (Bit 8) */ + #define R_PDM_PDCSR_SDF0_Msk (0x100UL) /*!< SDF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF1_Pos (9UL) /*!< SDF1 (Bit 9) */ + #define R_PDM_PDCSR_SDF1_Msk (0x200UL) /*!< SDF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF2_Pos (10UL) /*!< SDF2 (Bit 10) */ + #define R_PDM_PDCSR_SDF2_Msk (0x400UL) /*!< SDF2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF0_Pos (16UL) /*!< DRF0 (Bit 16) */ + #define R_PDM_PDCSR_DRF0_Msk (0x10000UL) /*!< DRF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF1_Pos (17UL) /*!< DRF1 (Bit 17) */ + #define R_PDM_PDCSR_DRF1_Msk (0x20000UL) /*!< DRF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF2_Pos (18UL) /*!< DRF2 (Bit 18) */ + #define R_PDM_PDCSR_DRF2_Msk (0x40000UL) /*!< DRF2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF0_Pos (24UL) /*!< EDF0 (Bit 24) */ + #define R_PDM_PDCSR_EDF0_Msk (0x1000000UL) /*!< EDF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF1_Pos (25UL) /*!< EDF1 (Bit 25) */ + #define R_PDM_PDCSR_EDF1_Msk (0x2000000UL) /*!< EDF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF2_Pos (26UL) /*!< EDF2 (Bit 26) */ + #define R_PDM_PDCSR_EDF2_Msk (0x4000000UL) /*!< EDF2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCSCR ========================================================= */ + #define R_PDM_PDCSCR_SDFC0_Pos (8UL) /*!< SDFC0 (Bit 8) */ + #define R_PDM_PDCSCR_SDFC0_Msk (0x100UL) /*!< SDFC0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSCR_SDFC1_Pos (9UL) /*!< SDFC1 (Bit 9) */ + #define R_PDM_PDCSCR_SDFC1_Msk (0x200UL) /*!< SDFC1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSCR_SDFC2_Pos (10UL) /*!< SDFC2 (Bit 10) */ + #define R_PDM_PDCSCR_SDFC2_Msk (0x400UL) /*!< SDFC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCSDCR ======================================================== */ + #define R_PDM_PDCSDCR_SDE0_Pos (0UL) /*!< SDE0 (Bit 0) */ + #define R_PDM_PDCSDCR_SDE0_Msk (0x1UL) /*!< SDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSDCR_SDE1_Pos (1UL) /*!< SDE1 (Bit 1) */ + #define R_PDM_PDCSDCR_SDE1_Msk (0x2UL) /*!< SDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSDCR_SDE2_Pos (2UL) /*!< SDE2 (Bit 2) */ + #define R_PDM_PDCSDCR_SDE2_Msk (0x4UL) /*!< SDE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCDRCR ======================================================== */ + #define R_PDM_PDCDRCR_DATRE0_Pos (0UL) /*!< DATRE0 (Bit 0) */ + #define R_PDM_PDCDRCR_DATRE0_Msk (0x1UL) /*!< DATRE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDRCR_DATRE1_Pos (1UL) /*!< DATRE1 (Bit 1) */ + #define R_PDM_PDCDRCR_DATRE1_Msk (0x2UL) /*!< DATRE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDRCR_DATRE2_Pos (2UL) /*!< DATRE2 (Bit 2) */ + #define R_PDM_PDCDRCR_DATRE2_Msk (0x4UL) /*!< DATRE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCDCR ========================================================= */ + #define R_PDM_PDCDCR_DATC0_Pos (0UL) /*!< DATC0 (Bit 0) */ + #define R_PDM_PDCDCR_DATC0_Msk (0x1UL) /*!< DATC0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDCR_DATC1_Pos (1UL) /*!< DATC1 (Bit 1) */ + #define R_PDM_PDCDCR_DATC1_Msk (0x2UL) /*!< DATC1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDCR_DATC2_Pos (2UL) /*!< DATC2 (Bit 2) */ + #define R_PDM_PDCDCR_DATC2_Msk (0x4UL) /*!< DATC2 (Bitfield-Mask: 0x01) */ +/* ========================================================= PDVR ========================================================== */ + #define R_PDM_PDVR_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_PDM_PDVR_VER_Msk (0xfffUL) /*!< VER (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ R_RMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MPSM ========================================================== */ + #define R_RMAC0_MPSM_PSME_Pos (0UL) /*!< PSME (Bit 0) */ + #define R_RMAC0_MPSM_PSME_Msk (0x1UL) /*!< PSME (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPSM_MFF_Pos (2UL) /*!< MFF (Bit 2) */ + #define R_RMAC0_MPSM_MFF_Msk (0x4UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPSM_PDA_Pos (3UL) /*!< PDA (Bit 3) */ + #define R_RMAC0_MPSM_PDA_Msk (0xf8UL) /*!< PDA (Bitfield-Mask: 0x1f) */ + #define R_RMAC0_MPSM_PRA_Pos (8UL) /*!< PRA (Bit 8) */ + #define R_RMAC0_MPSM_PRA_Msk (0x1f00UL) /*!< PRA (Bitfield-Mask: 0x1f) */ + #define R_RMAC0_MPSM_POP_Pos (13UL) /*!< POP (Bit 13) */ + #define R_RMAC0_MPSM_POP_Msk (0x6000UL) /*!< POP (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MPSM_PRD_Pos (16UL) /*!< PRD (Bit 16) */ + #define R_RMAC0_MPSM_PRD_Msk (0xffff0000UL) /*!< PRD (Bitfield-Mask: 0xffff) */ +/* ========================================================= MPIC ========================================================== */ + #define R_RMAC0_MPIC_PIS_Pos (0UL) /*!< PIS (Bit 0) */ + #define R_RMAC0_MPIC_PIS_Msk (0x7UL) /*!< PIS (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_LSC_Pos (3UL) /*!< LSC (Bit 3) */ + #define R_RMAC0_MPIC_LSC_Msk (0x38UL) /*!< LSC (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_PIP_Pos (8UL) /*!< PIP (Bit 8) */ + #define R_RMAC0_MPIC_PIP_Msk (0x100UL) /*!< PIP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PIPP_Pos (9UL) /*!< PIPP (Bit 9) */ + #define R_RMAC0_MPIC_PIPP_Msk (0x200UL) /*!< PIPP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PLSPP_Pos (10UL) /*!< PLSPP (Bit 10) */ + #define R_RMAC0_MPIC_PLSPP_Msk (0x400UL) /*!< PLSPP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PSMCS_Pos (16UL) /*!< PSMCS (Bit 16) */ + #define R_RMAC0_MPIC_PSMCS_Msk (0x7f0000UL) /*!< PSMCS (Bitfield-Mask: 0x7f) */ + #define R_RMAC0_MPIC_PSMDP_Pos (23UL) /*!< PSMDP (Bit 23) */ + #define R_RMAC0_MPIC_PSMDP_Msk (0x800000UL) /*!< PSMDP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PSMHT_Pos (24UL) /*!< PSMHT (Bit 24) */ + #define R_RMAC0_MPIC_PSMHT_Msk (0x7000000UL) /*!< PSMHT (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_PSMCT_Pos (28UL) /*!< PSMCT (Bit 28) */ + #define R_RMAC0_MPIC_PSMCT_Msk (0x70000000UL) /*!< PSMCT (Bitfield-Mask: 0x07) */ +/* ========================================================= MPIM ========================================================== */ + #define R_RMAC0_MPIM_PLS_Pos (0UL) /*!< PLS (Bit 0) */ + #define R_RMAC0_MPIM_PLS_Msk (0x1UL) /*!< PLS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIM_LPIA_Pos (1UL) /*!< LPIA (Bit 1) */ + #define R_RMAC0_MPIM_LPIA_Msk (0x2UL) /*!< LPIA (Bitfield-Mask: 0x01) */ +/* ========================================================= MIOC ========================================================== */ + #define R_RMAC0_MIOC_MIOC_Pos (0UL) /*!< MIOC (Bit 0) */ + #define R_RMAC0_MIOC_MIOC_Msk (0xffffffffUL) /*!< MIOC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTFFC ========================================================= */ + #define R_RMAC0_MTFFC_DPAD_Pos (0UL) /*!< DPAD (Bit 0) */ + #define R_RMAC0_MTFFC_DPAD_Msk (0x1UL) /*!< DPAD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTFFC_FCM_Pos (1UL) /*!< FCM (Bit 1) */ + #define R_RMAC0_MTFFC_FCM_Msk (0x2UL) /*!< FCM (Bitfield-Mask: 0x01) */ +/* ========================================================= MTPFC ========================================================= */ + #define R_RMAC0_MTPFC_PT_Pos (0UL) /*!< PT (Bit 0) */ + #define R_RMAC0_MTPFC_PT_Msk (0xffffUL) /*!< PT (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MTPFC_PFRT_Pos (16UL) /*!< PFRT (Bit 16) */ + #define R_RMAC0_MTPFC_PFRT_Msk (0xff0000UL) /*!< PFRT (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTPFC_PFM_Pos (26UL) /*!< PFM (Bit 26) */ + #define R_RMAC0_MTPFC_PFM_Msk (0x4000000UL) /*!< PFM (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC_PFRLV_Pos (27UL) /*!< PFRLV (Bit 27) */ + #define R_RMAC0_MTPFC_PFRLV_Msk (0xf8000000UL) /*!< PFRLV (Bitfield-Mask: 0x1f) */ +/* ======================================================== MTPFC2 ========================================================= */ + #define R_RMAC0_MTPFC2_PFCTTZ_Pos (0UL) /*!< PFCTTZ (Bit 0) */ + #define R_RMAC0_MTPFC2_PFCTTZ_Msk (0x3UL) /*!< PFCTTZ (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MTPFC2_MPFCFR0_Pos (8UL) /*!< MPFCFR0 (Bit 8) */ + #define R_RMAC0_MTPFC2_MPFCFR0_Msk (0x100UL) /*!< MPFCFR0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_MPFCFR1_Pos (9UL) /*!< MPFCFR1 (Bit 9) */ + #define R_RMAC0_MTPFC2_MPFCFR1_Msk (0x200UL) /*!< MPFCFR1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_PFTTZ_Pos (16UL) /*!< PFTTZ (Bit 16) */ + #define R_RMAC0_MTPFC2_PFTTZ_Msk (0x10000UL) /*!< PFTTZ (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_MPFR_Pos (17UL) /*!< MPFR (Bit 17) */ + #define R_RMAC0_MTPFC2_MPFR_Msk (0x20000UL) /*!< MPFR (Bitfield-Mask: 0x01) */ +/* ======================================================== MTPFC30 ======================================================== */ + #define R_RMAC0_MTPFC30_PFCPG_Pos (0UL) /*!< PFCPG (Bit 0) */ + #define R_RMAC0_MTPFC30_PFCPG_Msk (0xffUL) /*!< PFCPG (Bitfield-Mask: 0xff) */ +/* ======================================================== MTPFC31 ======================================================== */ + #define R_RMAC0_MTPFC31_PFCPG_Pos (0UL) /*!< PFCPG (Bit 0) */ + #define R_RMAC0_MTPFC31_PFCPG_Msk (0xffUL) /*!< PFCPG (Bitfield-Mask: 0xff) */ +/* ======================================================== MTATC0 ========================================================= */ + #define R_RMAC0_MTATC0_TRTP_Pos (0UL) /*!< TRTP (Bit 0) */ + #define R_RMAC0_MTATC0_TRTP_Msk (0xffUL) /*!< TRTP (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTATC0_TRTL_Pos (8UL) /*!< TRTL (Bit 8) */ + #define R_RMAC0_MTATC0_TRTL_Msk (0x700UL) /*!< TRTL (Bitfield-Mask: 0x07) */ +/* ======================================================== MTATC1 ========================================================= */ + #define R_RMAC0_MTATC1_TRTP_Pos (0UL) /*!< TRTP (Bit 0) */ + #define R_RMAC0_MTATC1_TRTP_Msk (0xffUL) /*!< TRTP (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTATC1_TRTL_Pos (8UL) /*!< TRTL (Bit 8) */ + #define R_RMAC0_MTATC1_TRTL_Msk (0x700UL) /*!< TRTL (Bitfield-Mask: 0x07) */ +/* ========================================================= MTIM ========================================================== */ + #define R_RMAC0_MTIM_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_RMAC0_MTIM_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ========================================================= MRGC ========================================================== */ + #define R_RMAC0_MRGC_RCPT_Pos (0UL) /*!< RCPT (Bit 0) */ + #define R_RMAC0_MRGC_RCPT_Msk (0x1UL) /*!< RCPT (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFRC_Pos (1UL) /*!< PFRC (Bit 1) */ + #define R_RMAC0_MRGC_PFRC_Msk (0x2UL) /*!< PFRC (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFRTZ_Pos (2UL) /*!< PFRTZ (Bit 2) */ + #define R_RMAC0_MRGC_PFRTZ_Msk (0x4UL) /*!< PFRTZ (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_MPDE_Pos (3UL) /*!< MPDE (Bit 3) */ + #define R_RMAC0_MRGC_MPDE_Msk (0x8UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_RFCFE_Pos (4UL) /*!< RFCFE (Bit 4) */ + #define R_RMAC0_MRGC_RFCFE_Msk (0x10UL) /*!< RFCFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFCRC_Pos (16UL) /*!< PFCRC (Bit 16) */ + #define R_RMAC0_MRGC_PFCRC_Msk (0xff0000UL) /*!< PFCRC (Bitfield-Mask: 0xff) */ +/* ======================================================== MRMAC0 ========================================================= */ + #define R_RMAC0_MRMAC0_MAU_Pos (0UL) /*!< MAU (Bit 0) */ + #define R_RMAC0_MRMAC0_MAU_Msk (0xffffUL) /*!< MAU (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRMAC1 ========================================================= */ + #define R_RMAC0_MRMAC1_MAL_Pos (0UL) /*!< MAL (Bit 0) */ + #define R_RMAC0_MRMAC1_MAL_Msk (0xffffffffUL) /*!< MAL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRAFC ========================================================= */ + #define R_RMAC0_MRAFC_UCENE_Pos (0UL) /*!< UCENE (Bit 0) */ + #define R_RMAC0_MRAFC_UCENE_Msk (0x1UL) /*!< UCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCENE_Pos (1UL) /*!< MCENE (Bit 1) */ + #define R_RMAC0_MRAFC_MCENE_Msk (0x2UL) /*!< MCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCENE_Pos (2UL) /*!< BCENE (Bit 2) */ + #define R_RMAC0_MRAFC_BCENE_Msk (0x4UL) /*!< BCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSTENE_Pos (3UL) /*!< MSTENE (Bit 3) */ + #define R_RMAC0_MRAFC_MSTENE_Msk (0x8UL) /*!< MSTENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BSTENE_Pos (4UL) /*!< BSTENE (Bit 4) */ + #define R_RMAC0_MRAFC_BSTENE_Msk (0x10UL) /*!< BSTENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCACE_Pos (5UL) /*!< MCACE (Bit 5) */ + #define R_RMAC0_MRAFC_MCACE_Msk (0x20UL) /*!< MCACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCACE_Pos (6UL) /*!< BCACE (Bit 6) */ + #define R_RMAC0_MRAFC_BCACE_Msk (0x40UL) /*!< BCACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NDAREE_Pos (7UL) /*!< NDAREE (Bit 7) */ + #define R_RMAC0_MRAFC_NDAREE_Msk (0x80UL) /*!< NDAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_SDSFREE_Pos (8UL) /*!< SDSFREE (Bit 8) */ + #define R_RMAC0_MRAFC_SDSFREE_Msk (0x100UL) /*!< SDSFREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NSAREE_Pos (9UL) /*!< NSAREE (Bit 9) */ + #define R_RMAC0_MRAFC_NSAREE_Msk (0x200UL) /*!< NSAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSAREE_Pos (10UL) /*!< MSAREE (Bit 10) */ + #define R_RMAC0_MRAFC_MSAREE_Msk (0x400UL) /*!< MSAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_UCENP_Pos (16UL) /*!< UCENP (Bit 16) */ + #define R_RMAC0_MRAFC_UCENP_Msk (0x10000UL) /*!< UCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCENP_Pos (17UL) /*!< MCENP (Bit 17) */ + #define R_RMAC0_MRAFC_MCENP_Msk (0x20000UL) /*!< MCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCENP_Pos (18UL) /*!< BCENP (Bit 18) */ + #define R_RMAC0_MRAFC_BCENP_Msk (0x40000UL) /*!< BCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSTENP_Pos (19UL) /*!< MSTENP (Bit 19) */ + #define R_RMAC0_MRAFC_MSTENP_Msk (0x80000UL) /*!< MSTENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BSTENP_Pos (20UL) /*!< BSTENP (Bit 20) */ + #define R_RMAC0_MRAFC_BSTENP_Msk (0x100000UL) /*!< BSTENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCACP_Pos (21UL) /*!< MCACP (Bit 21) */ + #define R_RMAC0_MRAFC_MCACP_Msk (0x200000UL) /*!< MCACP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCACP_Pos (22UL) /*!< BCACP (Bit 22) */ + #define R_RMAC0_MRAFC_BCACP_Msk (0x400000UL) /*!< BCACP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NDAREP_Pos (23UL) /*!< NDAREP (Bit 23) */ + #define R_RMAC0_MRAFC_NDAREP_Msk (0x800000UL) /*!< NDAREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_SDSFREP_Pos (24UL) /*!< SDSFREP (Bit 24) */ + #define R_RMAC0_MRAFC_SDSFREP_Msk (0x1000000UL) /*!< SDSFREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NSAREP_Pos (25UL) /*!< NSAREP (Bit 25) */ + #define R_RMAC0_MRAFC_NSAREP_Msk (0x2000000UL) /*!< NSAREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSAREP_Pos (26UL) /*!< MSAREP (Bit 26) */ + #define R_RMAC0_MRAFC_MSAREP_Msk (0x4000000UL) /*!< MSAREP (Bitfield-Mask: 0x01) */ +/* ========================================================= MRSCE ========================================================= */ + #define R_RMAC0_MRSCE_CMFE_Pos (0UL) /*!< CMFE (Bit 0) */ + #define R_RMAC0_MRSCE_CMFE_Msk (0xffffUL) /*!< CMFE (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRSCE_CBFE_Pos (16UL) /*!< CBFE (Bit 16) */ + #define R_RMAC0_MRSCE_CBFE_Msk (0xffff0000UL) /*!< CBFE (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRSCP ========================================================= */ + #define R_RMAC0_MRSCP_CMFP_Pos (0UL) /*!< CMFP (Bit 0) */ + #define R_RMAC0_MRSCP_CMFP_Msk (0xffffUL) /*!< CMFP (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRSCP_CBFP_Pos (16UL) /*!< CBFP (Bit 16) */ + #define R_RMAC0_MRSCP_CBFP_Msk (0xffff0000UL) /*!< CBFP (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRSCC ========================================================= */ + #define R_RMAC0_MRSCC_MSCCE_Pos (0UL) /*!< MSCCE (Bit 0) */ + #define R_RMAC0_MRSCC_MSCCE_Msk (0x1UL) /*!< MSCCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_BSCCE_Pos (1UL) /*!< BSCCE (Bit 1) */ + #define R_RMAC0_MRSCC_BSCCE_Msk (0x2UL) /*!< BSCCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_MSCCP_Pos (16UL) /*!< MSCCP (Bit 16) */ + #define R_RMAC0_MRSCC_MSCCP_Msk (0x10000UL) /*!< MSCCP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_BSCCP_Pos (17UL) /*!< BSCCP (Bit 17) */ + #define R_RMAC0_MRSCC_BSCCP_Msk (0x20000UL) /*!< BSCCP (Bitfield-Mask: 0x01) */ +/* ======================================================== MRFSCE ========================================================= */ + #define R_RMAC0_MRFSCE_EMXS_Pos (0UL) /*!< EMXS (Bit 0) */ + #define R_RMAC0_MRFSCE_EMXS_Msk (0xffffUL) /*!< EMXS (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRFSCE_EMNS_Pos (16UL) /*!< EMNS (Bit 16) */ + #define R_RMAC0_MRFSCE_EMNS_Msk (0xffff0000UL) /*!< EMNS (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFSCP ========================================================= */ + #define R_RMAC0_MRFSCP_PMXS_Pos (0UL) /*!< PMXS (Bit 0) */ + #define R_RMAC0_MRFSCP_PMXS_Msk (0xffffUL) /*!< PMXS (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRFSCP_PMNS_Pos (16UL) /*!< PMNS (Bit 16) */ + #define R_RMAC0_MRFSCP_PMNS_Msk (0xffff0000UL) /*!< PMNS (Bitfield-Mask: 0xffff) */ +/* ========================================================= MTRC ========================================================== */ + #define R_RMAC0_MTRC_TRHFME0_Pos (0UL) /*!< TRHFME0 (Bit 0) */ + #define R_RMAC0_MTRC_TRHFME0_Msk (0x1UL) /*!< TRHFME0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRHFME1_Pos (1UL) /*!< TRHFME1 (Bit 1) */ + #define R_RMAC0_MTRC_TRHFME1_Msk (0x2UL) /*!< TRHFME1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRDDE_Pos (24UL) /*!< TRDDE (Bit 24) */ + #define R_RMAC0_MTRC_TRDDE_Msk (0x1000000UL) /*!< TRDDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRDDP_Pos (25UL) /*!< TRDDP (Bit 25) */ + #define R_RMAC0_MTRC_TRDDP_Msk (0x2000000UL) /*!< TRDDP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TCTSE_Pos (26UL) /*!< TCTSE (Bit 26) */ + #define R_RMAC0_MTRC_TCTSE_Msk (0x4000000UL) /*!< TCTSE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TCTSP_Pos (27UL) /*!< TCTSP (Bit 27) */ + #define R_RMAC0_MTRC_TCTSP_Msk (0x8000000UL) /*!< TCTSP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_DTN_Pos (28UL) /*!< DTN (Bit 28) */ + #define R_RMAC0_MTRC_DTN_Msk (0x10000000UL) /*!< DTN (Bitfield-Mask: 0x01) */ +/* ========================================================= MRPFM ========================================================= */ + #define R_RMAC0_MRPFM_PTCA_Pos (0UL) /*!< PTCA (Bit 0) */ + #define R_RMAC0_MRPFM_PTCA_Msk (0x1UL) /*!< PTCA (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRPFM_PFCTCA_Pos (16UL) /*!< PFCTCA (Bit 16) */ + #define R_RMAC0_MRPFM_PFCTCA_Msk (0xff0000UL) /*!< PFCTCA (Bitfield-Mask: 0xff) */ +/* ========================================================= MPFC0 ========================================================= */ + #define R_RMAC0_MPFC0_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC0_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC0_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC0_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC0_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC0_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC0_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC0_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC1 ========================================================= */ + #define R_RMAC0_MPFC1_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC1_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC1_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC1_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC1_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC1_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC1_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC1_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC2 ========================================================= */ + #define R_RMAC0_MPFC2_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC2_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC2_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC2_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC2_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC2_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC2_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC2_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC3 ========================================================= */ + #define R_RMAC0_MPFC3_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC3_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC3_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC3_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC3_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC3_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC3_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC3_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC4 ========================================================= */ + #define R_RMAC0_MPFC4_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC4_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC4_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC4_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC4_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC4_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC4_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC4_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC5 ========================================================= */ + #define R_RMAC0_MPFC5_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC5_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC5_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC5_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC5_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC5_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC5_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC5_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC6 ========================================================= */ + #define R_RMAC0_MPFC6_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC6_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC6_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC6_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC6_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC6_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC6_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC6_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC7 ========================================================= */ + #define R_RMAC0_MPFC7_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC7_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC7_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC7_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC7_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC7_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC7_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC7_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC8 ========================================================= */ + #define R_RMAC0_MPFC8_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC8_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC8_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC8_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC8_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC8_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC8_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC8_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC9 ========================================================= */ + #define R_RMAC0_MPFC9_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC9_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC9_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC9_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC9_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC9_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC9_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC9_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC10 ========================================================= */ + #define R_RMAC0_MPFC10_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC10_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC10_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC10_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC10_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC10_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC10_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC10_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC11 ========================================================= */ + #define R_RMAC0_MPFC11_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC11_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC11_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC11_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC11_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC11_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC11_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC11_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC12 ========================================================= */ + #define R_RMAC0_MPFC12_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC12_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC12_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC12_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC12_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC12_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC12_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC12_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC13 ========================================================= */ + #define R_RMAC0_MPFC13_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC13_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC13_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC13_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC13_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC13_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC13_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC13_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC14 ========================================================= */ + #define R_RMAC0_MPFC14_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC14_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC14_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC14_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC14_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC14_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC14_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC14_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC15 ========================================================= */ + #define R_RMAC0_MPFC15_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC15_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC15_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC15_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC15_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC15_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC15_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC15_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MLVC ========================================================== */ + #define R_RMAC0_MLVC_LVT_Pos (0UL) /*!< LVT (Bit 0) */ + #define R_RMAC0_MLVC_LVT_Msk (0x7fUL) /*!< LVT (Bitfield-Mask: 0x7f) */ + #define R_RMAC0_MLVC_PASE_Pos (8UL) /*!< PASE (Bit 8) */ + #define R_RMAC0_MLVC_PASE_Msk (0x100UL) /*!< PASE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MLVC_PLV_Pos (16UL) /*!< PLV (Bit 16) */ + #define R_RMAC0_MLVC_PLV_Msk (0x10000UL) /*!< PLV (Bitfield-Mask: 0x01) */ +/* ========================================================= MEEEC ========================================================= */ + #define R_RMAC0_MEEEC_LPITR_Pos (0UL) /*!< LPITR (Bit 0) */ + #define R_RMAC0_MEEEC_LPITR_Msk (0x1UL) /*!< LPITR (Bitfield-Mask: 0x01) */ +/* ========================================================= MLBC ========================================================== */ + #define R_RMAC0_MLBC_LBME_Pos (0UL) /*!< LBME (Bit 0) */ + #define R_RMAC0_MLBC_LBME_Msk (0x1UL) /*!< LBME (Bitfield-Mask: 0x01) */ +/* ======================================================== MXGMIIC ======================================================== */ + #define R_RMAC0_MXGMIIC_LFS_TXRFS_Pos (0UL) /*!< LFS_TXRFS (Bit 0) */ + #define R_RMAC0_MXGMIIC_LFS_TXRFS_Msk (0x1UL) /*!< LFS_TXRFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MXGMIIC_LFS_TXIDLE_Pos (1UL) /*!< LFS_TXIDLE (Bit 1) */ + #define R_RMAC0_MXGMIIC_LFS_TXIDLE_Msk (0x2UL) /*!< LFS_TXIDLE (Bitfield-Mask: 0x01) */ +/* ========================================================= MPCH ========================================================== */ + #define R_RMAC0_MPCH_TXPCH_M_Pos (0UL) /*!< TXPCH_M (Bit 0) */ + #define R_RMAC0_MPCH_TXPCH_M_Msk (0x1UL) /*!< TXPCH_M (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_TXPCH_ETYPE_Pos (2UL) /*!< TXPCH_ETYPE (Bit 2) */ + #define R_RMAC0_MPCH_TXPCH_ETYPE_Msk (0xcUL) /*!< TXPCH_ETYPE (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MPCH_TXPCH_PID_Pos (4UL) /*!< TXPCH_PID (Bit 4) */ + #define R_RMAC0_MPCH_TXPCH_PID_Msk (0xf0UL) /*!< TXPCH_PID (Bitfield-Mask: 0x0f) */ + #define R_RMAC0_MPCH_IETPTE_Pos (8UL) /*!< IETPTE (Bit 8) */ + #define R_RMAC0_MPCH_IETPTE_Msk (0x100UL) /*!< IETPTE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_CTPTE_Pos (9UL) /*!< CTPTE (Bit 9) */ + #define R_RMAC0_MPCH_CTPTE_Msk (0x200UL) /*!< CTPTE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_IETRIOD_Pos (10UL) /*!< IETRIOD (Bit 10) */ + #define R_RMAC0_MPCH_IETRIOD_Msk (0x400UL) /*!< IETRIOD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_CTRIOD_Pos (11UL) /*!< CTRIOD (Bit 11) */ + #define R_RMAC0_MPCH_CTRIOD_Msk (0x800UL) /*!< CTRIOD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_RXPCH_TSM_Pos (16UL) /*!< RXPCH_TSM (Bit 16) */ + #define R_RMAC0_MPCH_RXPCH_TSM_Msk (0x10000UL) /*!< RXPCH_TSM (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_RPHCRCD_Pos (17UL) /*!< RPHCRCD (Bit 17) */ + #define R_RMAC0_MPCH_RPHCRCD_Msk (0x20000UL) /*!< RPHCRCD (Bitfield-Mask: 0x01) */ +/* ========================================================= MANM ========================================================== */ + #define R_RMAC0_MANM_RX_AN_MES_Pos (0UL) /*!< RX_AN_MES (Bit 0) */ + #define R_RMAC0_MANM_RX_AN_MES_Msk (0xffffUL) /*!< RX_AN_MES (Bitfield-Mask: 0xffff) */ +/* ========================================================= MEIS ========================================================== */ + #define R_RMAC0_MEIS_TSLS_Pos (0UL) /*!< TSLS (Bit 0) */ + #define R_RMAC0_MEIS_TSLS_Msk (0x1UL) /*!< TSLS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TIES_Pos (1UL) /*!< TIES (Bit 1) */ + #define R_RMAC0_MEIS_TIES_Msk (0x2UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PRES_Pos (2UL) /*!< PRES (Bit 2) */ + #define R_RMAC0_MEIS_PRES_Msk (0x4UL) /*!< PRES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PFRROS_Pos (3UL) /*!< PFRROS (Bit 3) */ + #define R_RMAC0_MEIS_PFRROS_Msk (0x8UL) /*!< PFRROS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCDS_Pos (4UL) /*!< FCDS (Bit 4) */ + #define R_RMAC0_MEIS_FCDS_Msk (0x10UL) /*!< FCDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TCES_Pos (5UL) /*!< TCES (Bit 5) */ + #define R_RMAC0_MEIS_TCES_Msk (0x20UL) /*!< TCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TBCIS_Pos (6UL) /*!< TBCIS (Bit 6) */ + #define R_RMAC0_MEIS_TBCIS_Msk (0x40UL) /*!< TBCIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_BFES_Pos (7UL) /*!< BFES (Bit 7) */ + #define R_RMAC0_MEIS_BFES_Msk (0x80UL) /*!< BFES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCES_Pos (8UL) /*!< FCES (Bit 8) */ + #define R_RMAC0_MEIS_FCES_Msk (0x100UL) /*!< FCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_REOES_Pos (9UL) /*!< REOES (Bit 9) */ + #define R_RMAC0_MEIS_REOES_Msk (0x200UL) /*!< REOES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPOES_Pos (10UL) /*!< RPOES (Bit 10) */ + #define R_RMAC0_MEIS_RPOES_Msk (0x400UL) /*!< RPOES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPCRES_Pos (11UL) /*!< RPCRES (Bit 11) */ + #define R_RMAC0_MEIS_RPCRES_Msk (0x800UL) /*!< RPCRES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CTLES0_Pos (12UL) /*!< CTLES0 (Bit 12) */ + #define R_RMAC0_MEIS_CTLES0_Msk (0x1000UL) /*!< CTLES0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CTLES1_Pos (13UL) /*!< CTLES1 (Bit 13) */ + #define R_RMAC0_MEIS_CTLES1_Msk (0x2000UL) /*!< CTLES1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PDES_Pos (20UL) /*!< PDES (Bit 20) */ + #define R_RMAC0_MEIS_PDES_Msk (0x100000UL) /*!< PDES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PNAES_Pos (21UL) /*!< PNAES (Bit 21) */ + #define R_RMAC0_MEIS_PNAES_Msk (0x200000UL) /*!< PNAES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCMCES_Pos (22UL) /*!< FCMCES (Bit 22) */ + #define R_RMAC0_MEIS_FCMCES_Msk (0x400000UL) /*!< FCMCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FFMES_Pos (23UL) /*!< FFMES (Bit 23) */ + #define R_RMAC0_MEIS_FFMES_Msk (0x800000UL) /*!< FFMES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CFCES_Pos (24UL) /*!< CFCES (Bit 24) */ + #define R_RMAC0_MEIS_CFCES_Msk (0x1000000UL) /*!< CFCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FRCES_Pos (25UL) /*!< FRCES (Bit 25) */ + #define R_RMAC0_MEIS_FRCES_Msk (0x2000000UL) /*!< FRCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPOOMS_Pos (26UL) /*!< RPOOMS (Bit 26) */ + #define R_RMAC0_MEIS_RPOOMS_Msk (0x4000000UL) /*!< RPOOMS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FFS_Pos (27UL) /*!< FFS (Bit 27) */ + #define R_RMAC0_MEIS_FFS_Msk (0x8000000UL) /*!< FFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FUES_Pos (28UL) /*!< FUES (Bit 28) */ + #define R_RMAC0_MEIS_FUES_Msk (0x10000000UL) /*!< FUES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FOES_Pos (29UL) /*!< FOES (Bit 29) */ + #define R_RMAC0_MEIS_FOES_Msk (0x20000000UL) /*!< FOES (Bitfield-Mask: 0x01) */ +/* ========================================================= MEIE ========================================================== */ + #define R_RMAC0_MEIE_TSLE_Pos (0UL) /*!< TSLE (Bit 0) */ + #define R_RMAC0_MEIE_TSLE_Msk (0x1UL) /*!< TSLE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TIEE_Pos (1UL) /*!< TIEE (Bit 1) */ + #define R_RMAC0_MEIE_TIEE_Msk (0x2UL) /*!< TIEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PMSEE_Pos (2UL) /*!< PMSEE (Bit 2) */ + #define R_RMAC0_MEIE_PMSEE_Msk (0x4UL) /*!< PMSEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PFRROE_Pos (3UL) /*!< PFRROE (Bit 3) */ + #define R_RMAC0_MEIE_PFRROE_Msk (0x8UL) /*!< PFRROE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCDE_Pos (4UL) /*!< FCDE (Bit 4) */ + #define R_RMAC0_MEIE_FCDE_Msk (0x10UL) /*!< FCDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TCEE_Pos (5UL) /*!< TCEE (Bit 5) */ + #define R_RMAC0_MEIE_TCEE_Msk (0x20UL) /*!< TCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TBCIE_Pos (6UL) /*!< TBCIE (Bit 6) */ + #define R_RMAC0_MEIE_TBCIE_Msk (0x40UL) /*!< TBCIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_BFEE_Pos (7UL) /*!< BFEE (Bit 7) */ + #define R_RMAC0_MEIE_BFEE_Msk (0x80UL) /*!< BFEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCEE_Pos (8UL) /*!< FCEE (Bit 8) */ + #define R_RMAC0_MEIE_FCEE_Msk (0x100UL) /*!< FCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_REOEE_Pos (9UL) /*!< REOEE (Bit 9) */ + #define R_RMAC0_MEIE_REOEE_Msk (0x200UL) /*!< REOEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPOEE_Pos (10UL) /*!< RPOEE (Bit 10) */ + #define R_RMAC0_MEIE_RPOEE_Msk (0x400UL) /*!< RPOEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPCREE_Pos (11UL) /*!< RPCREE (Bit 11) */ + #define R_RMAC0_MEIE_RPCREE_Msk (0x800UL) /*!< RPCREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CTLEE0_Pos (12UL) /*!< CTLEE0 (Bit 12) */ + #define R_RMAC0_MEIE_CTLEE0_Msk (0x1000UL) /*!< CTLEE0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CTLEE1_Pos (13UL) /*!< CTLEE1 (Bit 13) */ + #define R_RMAC0_MEIE_CTLEE1_Msk (0x2000UL) /*!< CTLEE1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PDEE_Pos (20UL) /*!< PDEE (Bit 20) */ + #define R_RMAC0_MEIE_PDEE_Msk (0x100000UL) /*!< PDEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PNAEE_Pos (21UL) /*!< PNAEE (Bit 21) */ + #define R_RMAC0_MEIE_PNAEE_Msk (0x200000UL) /*!< PNAEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCMCEE_Pos (22UL) /*!< FCMCEE (Bit 22) */ + #define R_RMAC0_MEIE_FCMCEE_Msk (0x400000UL) /*!< FCMCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FFMEE_Pos (23UL) /*!< FFMEE (Bit 23) */ + #define R_RMAC0_MEIE_FFMEE_Msk (0x800000UL) /*!< FFMEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CFCEE_Pos (24UL) /*!< CFCEE (Bit 24) */ + #define R_RMAC0_MEIE_CFCEE_Msk (0x1000000UL) /*!< CFCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FRCEE_Pos (25UL) /*!< FRCEE (Bit 25) */ + #define R_RMAC0_MEIE_FRCEE_Msk (0x2000000UL) /*!< FRCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPOOME_Pos (26UL) /*!< RPOOME (Bit 26) */ + #define R_RMAC0_MEIE_RPOOME_Msk (0x4000000UL) /*!< RPOOME (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FFE_Pos (27UL) /*!< FFE (Bit 27) */ + #define R_RMAC0_MEIE_FFE_Msk (0x8000000UL) /*!< FFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FUEE_Pos (28UL) /*!< FUEE (Bit 28) */ + #define R_RMAC0_MEIE_FUEE_Msk (0x10000000UL) /*!< FUEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FOEE_Pos (29UL) /*!< FOEE (Bit 29) */ + #define R_RMAC0_MEIE_FOEE_Msk (0x20000000UL) /*!< FOEE (Bitfield-Mask: 0x01) */ +/* ========================================================= MEID ========================================================== */ + #define R_RMAC0_MEID_TSLD_Pos (0UL) /*!< TSLD (Bit 0) */ + #define R_RMAC0_MEID_TSLD_Msk (0x1UL) /*!< TSLD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TIED_Pos (1UL) /*!< TIED (Bit 1) */ + #define R_RMAC0_MEID_TIED_Msk (0x2UL) /*!< TIED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PRED_Pos (2UL) /*!< PRED (Bit 2) */ + #define R_RMAC0_MEID_PRED_Msk (0x4UL) /*!< PRED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PFRROD_Pos (3UL) /*!< PFRROD (Bit 3) */ + #define R_RMAC0_MEID_PFRROD_Msk (0x8UL) /*!< PFRROD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCDD_Pos (4UL) /*!< FCDD (Bit 4) */ + #define R_RMAC0_MEID_FCDD_Msk (0x10UL) /*!< FCDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TCED_Pos (5UL) /*!< TCED (Bit 5) */ + #define R_RMAC0_MEID_TCED_Msk (0x20UL) /*!< TCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TBCID_Pos (6UL) /*!< TBCID (Bit 6) */ + #define R_RMAC0_MEID_TBCID_Msk (0x40UL) /*!< TBCID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_BFED_Pos (7UL) /*!< BFED (Bit 7) */ + #define R_RMAC0_MEID_BFED_Msk (0x80UL) /*!< BFED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCED_Pos (8UL) /*!< FCED (Bit 8) */ + #define R_RMAC0_MEID_FCED_Msk (0x100UL) /*!< FCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_REOED_Pos (9UL) /*!< REOED (Bit 9) */ + #define R_RMAC0_MEID_REOED_Msk (0x200UL) /*!< REOED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPOED_Pos (10UL) /*!< RPOED (Bit 10) */ + #define R_RMAC0_MEID_RPOED_Msk (0x400UL) /*!< RPOED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPCRED_Pos (11UL) /*!< RPCRED (Bit 11) */ + #define R_RMAC0_MEID_RPCRED_Msk (0x800UL) /*!< RPCRED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CTLED0_Pos (12UL) /*!< CTLED0 (Bit 12) */ + #define R_RMAC0_MEID_CTLED0_Msk (0x1000UL) /*!< CTLED0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CTLED1_Pos (13UL) /*!< CTLED1 (Bit 13) */ + #define R_RMAC0_MEID_CTLED1_Msk (0x2000UL) /*!< CTLED1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PDED_Pos (20UL) /*!< PDED (Bit 20) */ + #define R_RMAC0_MEID_PDED_Msk (0x100000UL) /*!< PDED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PNAED_Pos (21UL) /*!< PNAED (Bit 21) */ + #define R_RMAC0_MEID_PNAED_Msk (0x200000UL) /*!< PNAED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCMCED_Pos (22UL) /*!< FCMCED (Bit 22) */ + #define R_RMAC0_MEID_FCMCED_Msk (0x400000UL) /*!< FCMCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FFMED_Pos (23UL) /*!< FFMED (Bit 23) */ + #define R_RMAC0_MEID_FFMED_Msk (0x800000UL) /*!< FFMED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CFCED_Pos (24UL) /*!< CFCED (Bit 24) */ + #define R_RMAC0_MEID_CFCED_Msk (0x1000000UL) /*!< CFCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FRCED_Pos (25UL) /*!< FRCED (Bit 25) */ + #define R_RMAC0_MEID_FRCED_Msk (0x2000000UL) /*!< FRCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPOOMD_Pos (26UL) /*!< RPOOMD (Bit 26) */ + #define R_RMAC0_MEID_RPOOMD_Msk (0x4000000UL) /*!< RPOOMD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FFD_Pos (27UL) /*!< FFD (Bit 27) */ + #define R_RMAC0_MEID_FFD_Msk (0x8000000UL) /*!< FFD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FUED_Pos (28UL) /*!< FUED (Bit 28) */ + #define R_RMAC0_MEID_FUED_Msk (0x10000000UL) /*!< FUED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FOED_Pos (29UL) /*!< FOED (Bit 29) */ + #define R_RMAC0_MEID_FOED_Msk (0x20000000UL) /*!< FOED (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS0 ========================================================= */ + #define R_RMAC0_MMIS0_PLSCS_Pos (0UL) /*!< PLSCS (Bit 0) */ + #define R_RMAC0_MMIS0_PLSCS_Msk (0x1UL) /*!< PLSCS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_PIDS_Pos (1UL) /*!< PIDS (Bit 1) */ + #define R_RMAC0_MMIS0_PIDS_Msk (0x2UL) /*!< PIDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_LVSS_Pos (2UL) /*!< LVSS (Bit 2) */ + #define R_RMAC0_MMIS0_LVSS_Msk (0x4UL) /*!< LVSS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_LVFS_Pos (3UL) /*!< LVFS (Bit 3) */ + #define R_RMAC0_MMIS0_LVFS_Msk (0x8UL) /*!< LVFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_VFRS_Pos (4UL) /*!< VFRS (Bit 4) */ + #define R_RMAC0_MMIS0_VFRS_Msk (0x10UL) /*!< VFRS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_ANDETS_Pos (6UL) /*!< ANDETS (Bit 6) */ + #define R_RMAC0_MMIS0_ANDETS_Msk (0x40UL) /*!< ANDETS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFDS_Pos (8UL) /*!< XLFDS (Bit 8) */ + #define R_RMAC0_MMIS0_XLFDS_Msk (0x100UL) /*!< XLFDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFES_Pos (9UL) /*!< XLFES (Bit 9) */ + #define R_RMAC0_MMIS0_XLFES_Msk (0x200UL) /*!< XLFES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFSDS_Pos (10UL) /*!< XLFSDS (Bit 10) */ + #define R_RMAC0_MMIS0_XLFSDS_Msk (0x400UL) /*!< XLFSDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XRFSDS_Pos (11UL) /*!< XRFSDS (Bit 11) */ + #define R_RMAC0_MMIS0_XRFSDS_Msk (0x800UL) /*!< XRFSDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLISDS_Pos (12UL) /*!< XLISDS (Bit 12) */ + #define R_RMAC0_MMIS0_XLISDS_Msk (0x1000UL) /*!< XLISDS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE0 ========================================================= */ + #define R_RMAC0_MMIE0_PLSCE_Pos (0UL) /*!< PLSCE (Bit 0) */ + #define R_RMAC0_MMIE0_PLSCE_Msk (0x1UL) /*!< PLSCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_PIDE_Pos (1UL) /*!< PIDE (Bit 1) */ + #define R_RMAC0_MMIE0_PIDE_Msk (0x2UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_LVSE_Pos (2UL) /*!< LVSE (Bit 2) */ + #define R_RMAC0_MMIE0_LVSE_Msk (0x4UL) /*!< LVSE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_LVFE_Pos (3UL) /*!< LVFE (Bit 3) */ + #define R_RMAC0_MMIE0_LVFE_Msk (0x8UL) /*!< LVFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_VFRE_Pos (4UL) /*!< VFRE (Bit 4) */ + #define R_RMAC0_MMIE0_VFRE_Msk (0x10UL) /*!< VFRE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_ANDETE_Pos (6UL) /*!< ANDETE (Bit 6) */ + #define R_RMAC0_MMIE0_ANDETE_Msk (0x40UL) /*!< ANDETE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFDE_Pos (8UL) /*!< XLFDE (Bit 8) */ + #define R_RMAC0_MMIE0_XLFDE_Msk (0x100UL) /*!< XLFDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFEE_Pos (9UL) /*!< XLFEE (Bit 9) */ + #define R_RMAC0_MMIE0_XLFEE_Msk (0x200UL) /*!< XLFEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFSDE_Pos (10UL) /*!< XLFSDE (Bit 10) */ + #define R_RMAC0_MMIE0_XLFSDE_Msk (0x400UL) /*!< XLFSDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XRFSDE_Pos (11UL) /*!< XRFSDE (Bit 11) */ + #define R_RMAC0_MMIE0_XRFSDE_Msk (0x800UL) /*!< XRFSDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLISDE_Pos (12UL) /*!< XLISDE (Bit 12) */ + #define R_RMAC0_MMIE0_XLISDE_Msk (0x1000UL) /*!< XLISDE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID0 ========================================================= */ + #define R_RMAC0_MMID0_PLSCD_Pos (0UL) /*!< PLSCD (Bit 0) */ + #define R_RMAC0_MMID0_PLSCD_Msk (0x1UL) /*!< PLSCD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_PIDD_Pos (1UL) /*!< PIDD (Bit 1) */ + #define R_RMAC0_MMID0_PIDD_Msk (0x2UL) /*!< PIDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_LVSD_Pos (2UL) /*!< LVSD (Bit 2) */ + #define R_RMAC0_MMID0_LVSD_Msk (0x4UL) /*!< LVSD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_LVFD_Pos (3UL) /*!< LVFD (Bit 3) */ + #define R_RMAC0_MMID0_LVFD_Msk (0x8UL) /*!< LVFD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_VFRD_Pos (4UL) /*!< VFRD (Bit 4) */ + #define R_RMAC0_MMID0_VFRD_Msk (0x10UL) /*!< VFRD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_ANDETD_Pos (6UL) /*!< ANDETD (Bit 6) */ + #define R_RMAC0_MMID0_ANDETD_Msk (0x40UL) /*!< ANDETD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFDD_Pos (8UL) /*!< XLFDD (Bit 8) */ + #define R_RMAC0_MMID0_XLFDD_Msk (0x100UL) /*!< XLFDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFED_Pos (9UL) /*!< XLFED (Bit 9) */ + #define R_RMAC0_MMID0_XLFED_Msk (0x200UL) /*!< XLFED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFSDD_Pos (10UL) /*!< XLFSDD (Bit 10) */ + #define R_RMAC0_MMID0_XLFSDD_Msk (0x400UL) /*!< XLFSDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XRFSDD_Pos (11UL) /*!< XRFSDD (Bit 11) */ + #define R_RMAC0_MMID0_XRFSDD_Msk (0x800UL) /*!< XRFSDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLISDD_Pos (12UL) /*!< XLISDD (Bit 12) */ + #define R_RMAC0_MMID0_XLISDD_Msk (0x1000UL) /*!< XLISDD (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS1 ========================================================= */ + #define R_RMAC0_MMIS1_PRACS_Pos (0UL) /*!< PRACS (Bit 0) */ + #define R_RMAC0_MMIS1_PRACS_Msk (0x1UL) /*!< PRACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PWACS_Pos (1UL) /*!< PWACS (Bit 1) */ + #define R_RMAC0_MMIS1_PWACS_Msk (0x2UL) /*!< PWACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PAACS_Pos (2UL) /*!< PAACS (Bit 2) */ + #define R_RMAC0_MMIS1_PAACS_Msk (0x4UL) /*!< PAACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PPRACS_Pos (3UL) /*!< PPRACS (Bit 3) */ + #define R_RMAC0_MMIS1_PPRACS_Msk (0x8UL) /*!< PPRACS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE1 ========================================================= */ + #define R_RMAC0_MMIE1_PRACE_Pos (0UL) /*!< PRACE (Bit 0) */ + #define R_RMAC0_MMIE1_PRACE_Msk (0x1UL) /*!< PRACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PWACE_Pos (1UL) /*!< PWACE (Bit 1) */ + #define R_RMAC0_MMIE1_PWACE_Msk (0x2UL) /*!< PWACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PAACE_Pos (2UL) /*!< PAACE (Bit 2) */ + #define R_RMAC0_MMIE1_PAACE_Msk (0x4UL) /*!< PAACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PPRACE_Pos (3UL) /*!< PPRACE (Bit 3) */ + #define R_RMAC0_MMIE1_PPRACE_Msk (0x8UL) /*!< PPRACE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID1 ========================================================= */ + #define R_RMAC0_MMID1_PRACD_Pos (0UL) /*!< PRACD (Bit 0) */ + #define R_RMAC0_MMID1_PRACD_Msk (0x1UL) /*!< PRACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PWACD_Pos (1UL) /*!< PWACD (Bit 1) */ + #define R_RMAC0_MMID1_PWACD_Msk (0x2UL) /*!< PWACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PAACD_Pos (2UL) /*!< PAACD (Bit 2) */ + #define R_RMAC0_MMID1_PAACD_Msk (0x4UL) /*!< PAACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PPRACD_Pos (3UL) /*!< PPRACD (Bit 3) */ + #define R_RMAC0_MMID1_PPRACD_Msk (0x8UL) /*!< PPRACD (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS2 ========================================================= */ + #define R_RMAC0_MMIS2_MPDIS_Pos (0UL) /*!< MPDIS (Bit 0) */ + #define R_RMAC0_MMIS2_MPDIS_Msk (0x1UL) /*!< MPDIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS2_LPIAIS_Pos (1UL) /*!< LPIAIS (Bit 1) */ + #define R_RMAC0_MMIS2_LPIAIS_Msk (0x2UL) /*!< LPIAIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS2_LPIDIS_Pos (2UL) /*!< LPIDIS (Bit 2) */ + #define R_RMAC0_MMIS2_LPIDIS_Msk (0x4UL) /*!< LPIDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE2 ========================================================= */ + #define R_RMAC0_MMIE2_MPDIE_Pos (0UL) /*!< MPDIE (Bit 0) */ + #define R_RMAC0_MMIE2_MPDIE_Msk (0x1UL) /*!< MPDIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE2_LPIAIE_Pos (1UL) /*!< LPIAIE (Bit 1) */ + #define R_RMAC0_MMIE2_LPIAIE_Msk (0x2UL) /*!< LPIAIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE2_LPIDIE_Pos (2UL) /*!< LPIDIE (Bit 2) */ + #define R_RMAC0_MMIE2_LPIDIE_Msk (0x4UL) /*!< LPIDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID2 ========================================================= */ + #define R_RMAC0_MMID2_MPDID_Pos (0UL) /*!< MPDID (Bit 0) */ + #define R_RMAC0_MMID2_MPDID_Msk (0x1UL) /*!< MPDID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID2_LPIAID_Pos (1UL) /*!< LPIAID (Bit 1) */ + #define R_RMAC0_MMID2_LPIAID_Msk (0x2UL) /*!< LPIAID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID2_LPIDID_Pos (2UL) /*!< LPIDID (Bit 2) */ + #define R_RMAC0_MMID2_LPIDID_Msk (0x4UL) /*!< LPIDID (Bitfield-Mask: 0x01) */ +/* ======================================================== MMPFTCT ======================================================== */ + #define R_RMAC0_MMPFTCT_MPFTC_Pos (0UL) /*!< MPFTC (Bit 0) */ + #define R_RMAC0_MMPFTCT_MPFTC_Msk (0xffffUL) /*!< MPFTC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MAPFTCT ======================================================== */ + #define R_RMAC0_MAPFTCT_APFTC_Pos (0UL) /*!< APFTC (Bit 0) */ + #define R_RMAC0_MAPFTCT_APFTC_Msk (0xffffUL) /*!< APFTC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MPFRCT ========================================================= */ + #define R_RMAC0_MPFRCT_PFRC_Pos (0UL) /*!< PFRC (Bit 0) */ + #define R_RMAC0_MPFRCT_PFRC_Msk (0xffffUL) /*!< PFRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MFCICT ========================================================= */ + #define R_RMAC0_MFCICT_FCIC_Pos (0UL) /*!< FCIC (Bit 0) */ + #define R_RMAC0_MFCICT_FCIC_Msk (0xffffUL) /*!< FCIC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MEEECT ========================================================= */ + #define R_RMAC0_MEEECT_EEERC_Pos (0UL) /*!< EEERC (Bit 0) */ + #define R_RMAC0_MEEECT_EEERC_Msk (0xffffUL) /*!< EEERC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MMPCFTCT0 ======================================================= */ + #define R_RMAC0_MMPCFTCT0_MPCFCTC_Pos (0UL) /*!< MPCFCTC (Bit 0) */ + #define R_RMAC0_MMPCFTCT0_MPCFCTC_Msk (0xffffUL) /*!< MPCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MMPCFTCT1 ======================================================= */ + #define R_RMAC0_MMPCFTCT1_MPCFCTC_Pos (0UL) /*!< MPCFCTC (Bit 0) */ + #define R_RMAC0_MMPCFTCT1_MPCFCTC_Msk (0xffffUL) /*!< MPCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MAPCFTCT0 ======================================================= */ + #define R_RMAC0_MAPCFTCT0_APCFCTC_Pos (0UL) /*!< APCFCTC (Bit 0) */ + #define R_RMAC0_MAPCFTCT0_APCFCTC_Msk (0xffffUL) /*!< APCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MAPCFTCT1 ======================================================= */ + #define R_RMAC0_MAPCFTCT1_APCFCTC_Pos (0UL) /*!< APCFCTC (Bit 0) */ + #define R_RMAC0_MAPCFTCT1_APCFCTC_Msk (0xffffUL) /*!< APCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT0 ======================================================== */ + #define R_RMAC0_MPCFRCT0_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT0_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT1 ======================================================== */ + #define R_RMAC0_MPCFRCT1_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT1_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT2 ======================================================== */ + #define R_RMAC0_MPCFRCT2_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT2_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT3 ======================================================== */ + #define R_RMAC0_MPCFRCT3_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT3_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT4 ======================================================== */ + #define R_RMAC0_MPCFRCT4_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT4_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT5 ======================================================== */ + #define R_RMAC0_MPCFRCT5_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT5_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT6 ======================================================== */ + #define R_RMAC0_MPCFRCT6_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT6_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT7 ======================================================== */ + #define R_RMAC0_MPCFRCT7_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT7_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MROVFC ========================================================= */ + #define R_RMAC0_MROVFC_ROVFC_Pos (0UL) /*!< ROVFC (Bit 0) */ + #define R_RMAC0_MROVFC_ROVFC_Msk (0xffffffffUL) /*!< ROVFC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MRHCRCEC ======================================================== */ + #define R_RMAC0_MRHCRCEC_RHCRCEC_Pos (0UL) /*!< RHCRCEC (Bit 0) */ + #define R_RMAC0_MRHCRCEC_RHCRCEC_Msk (0xffffUL) /*!< RHCRCEC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRGFCE ========================================================= */ + #define R_RMAC0_MRGFCE_RGFNE_Pos (0UL) /*!< RGFNE (Bit 0) */ + #define R_RMAC0_MRGFCE_RGFNE_Msk (0xffffffffUL) /*!< RGFNE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGFCP ========================================================= */ + #define R_RMAC0_MRGFCP_RGFNP_Pos (0UL) /*!< RGFNP (Bit 0) */ + #define R_RMAC0_MRGFCP_RGFNP_Msk (0xffffffffUL) /*!< RGFNP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRBFC ========================================================= */ + #define R_RMAC0_MRBFC_RBFN_Pos (0UL) /*!< RBFN (Bit 0) */ + #define R_RMAC0_MRBFC_RBFN_Msk (0xffffffffUL) /*!< RBFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRMFC ========================================================= */ + #define R_RMAC0_MRMFC_RMFN_Pos (0UL) /*!< RMFN (Bit 0) */ + #define R_RMAC0_MRMFC_RMFN_Msk (0xffffffffUL) /*!< RMFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRUFC ========================================================= */ + #define R_RMAC0_MRUFC_RUFN_Pos (0UL) /*!< RUFN (Bit 0) */ + #define R_RMAC0_MRUFC_RUFN_Msk (0xffffffffUL) /*!< RUFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRPEFC ========================================================= */ + #define R_RMAC0_MRPEFC_RPEFN_Pos (0UL) /*!< RPEFN (Bit 0) */ + #define R_RMAC0_MRPEFC_RPEFN_Msk (0xffffUL) /*!< RPEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRNEFC ========================================================= */ + #define R_RMAC0_MRNEFC_RNEFN_Pos (0UL) /*!< RNEFN (Bit 0) */ + #define R_RMAC0_MRNEFC_RNEFN_Msk (0xffffUL) /*!< RNEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFMEFC ======================================================== */ + #define R_RMAC0_MRFMEFC_RFMEFN_Pos (0UL) /*!< RFMEFN (Bit 0) */ + #define R_RMAC0_MRFMEFC_RFMEFN_Msk (0xffffffffUL) /*!< RFMEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MRFFMEFC ======================================================== */ + #define R_RMAC0_MRFFMEFC_RFFMEFN_Pos (0UL) /*!< RFFMEFN (Bit 0) */ + #define R_RMAC0_MRFFMEFC_RFFMEFN_Msk (0xffffUL) /*!< RFFMEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================= MRCFCEFC ======================================================== */ + #define R_RMAC0_MRCFCEFC_RCFCEFN_Pos (0UL) /*!< RCFCEFN (Bit 0) */ + #define R_RMAC0_MRCFCEFC_RCFCEFN_Msk (0xffffUL) /*!< RCFCEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFCEFC ======================================================== */ + #define R_RMAC0_MRFCEFC_RFCEFN_Pos (0UL) /*!< RFCEFN (Bit 0) */ + #define R_RMAC0_MRFCEFC_RFCEFN_Msk (0xffffUL) /*!< RFCEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================= MRRCFEFC ======================================================== */ + #define R_RMAC0_MRRCFEFC_RRCFEFN_Pos (0UL) /*!< RRCFEFN (Bit 0) */ + #define R_RMAC0_MRRCFEFC_RRCFEFN_Msk (0xffffUL) /*!< RRCFEFN (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRFC ========================================================== */ + #define R_RMAC0_MRFC_RFN_Pos (0UL) /*!< RFN (Bit 0) */ + #define R_RMAC0_MRFC_RFN_Msk (0xffffffffUL) /*!< RFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGUEFC ======================================================== */ + #define R_RMAC0_MRGUEFC_RUEFN_Pos (0UL) /*!< RUEFN (Bit 0) */ + #define R_RMAC0_MRGUEFC_RUEFN_Msk (0xffffffffUL) /*!< RUEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRBUEFC ======================================================== */ + #define R_RMAC0_MRBUEFC_RUEFN_Pos (0UL) /*!< RUEFN (Bit 0) */ + #define R_RMAC0_MRBUEFC_RUEFN_Msk (0xffffffffUL) /*!< RUEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGOEFC ======================================================== */ + #define R_RMAC0_MRGOEFC_RGOEFN_Pos (0UL) /*!< RGOEFN (Bit 0) */ + #define R_RMAC0_MRGOEFC_RGOEFN_Msk (0xffffffffUL) /*!< RGOEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRBOEFC ======================================================== */ + #define R_RMAC0_MRBOEFC_RBOEFN_Pos (0UL) /*!< RBOEFN (Bit 0) */ + #define R_RMAC0_MRBOEFC_RBOEFN_Msk (0xffffffffUL) /*!< RBOEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCEU ======================================================== */ + #define R_RMAC0_MRXBCEU_RBNEU_Pos (0UL) /*!< RBNEU (Bit 0) */ + #define R_RMAC0_MRXBCEU_RBNEU_Msk (0xffffffffUL) /*!< RBNEU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCEL ======================================================== */ + #define R_RMAC0_MRXBCEL_RBNEL_Pos (0UL) /*!< RBNEL (Bit 0) */ + #define R_RMAC0_MRXBCEL_RBNEL_Msk (0xffffffffUL) /*!< RBNEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCPU ======================================================== */ + #define R_RMAC0_MRXBCPU_RBNPU_Pos (0UL) /*!< RBNPU (Bit 0) */ + #define R_RMAC0_MRXBCPU_RBNPU_Msk (0xffffffffUL) /*!< RBNPU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCPL ======================================================== */ + #define R_RMAC0_MRXBCPL_RBNPL_Pos (0UL) /*!< RBNPL (Bit 0) */ + #define R_RMAC0_MRXBCPL_RBNPL_Msk (0xffffffffUL) /*!< RBNPL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTGFCE ========================================================= */ + #define R_RMAC0_MTGFCE_TGFNE_Pos (0UL) /*!< TGFNE (Bit 0) */ + #define R_RMAC0_MTGFCE_TGFNE_Msk (0xffffffffUL) /*!< TGFNE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTGFCP ========================================================= */ + #define R_RMAC0_MTGFCP_TGFNP_Pos (0UL) /*!< TGFNP (Bit 0) */ + #define R_RMAC0_MTGFCP_TGFNP_Msk (0xffffffffUL) /*!< TGFNP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTBFC ========================================================= */ + #define R_RMAC0_MTBFC_TBFN_Pos (0UL) /*!< TBFN (Bit 0) */ + #define R_RMAC0_MTBFC_TBFN_Msk (0xffffffffUL) /*!< TBFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTMFC ========================================================= */ + #define R_RMAC0_MTMFC_TMFN_Pos (0UL) /*!< TMFN (Bit 0) */ + #define R_RMAC0_MTMFC_TMFN_Msk (0xffffffffUL) /*!< TMFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTUFC ========================================================= */ + #define R_RMAC0_MTUFC_TUFN_Pos (0UL) /*!< TUFN (Bit 0) */ + #define R_RMAC0_MTUFC_TUFN_Msk (0xffffffffUL) /*!< TUFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTEFC ========================================================= */ + #define R_RMAC0_MTEFC_TEFN_Pos (0UL) /*!< TEFN (Bit 0) */ + #define R_RMAC0_MTEFC_TEFN_Msk (0xffffUL) /*!< TEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MTXBCEU ======================================================== */ + #define R_RMAC0_MTXBCEU_TBNEU_Pos (0UL) /*!< TBNEU (Bit 0) */ + #define R_RMAC0_MTXBCEU_TBNEU_Msk (0xffffffffUL) /*!< TBNEU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCEL ======================================================== */ + #define R_RMAC0_MTXBCEL_TBNEL_Pos (0UL) /*!< TBNEL (Bit 0) */ + #define R_RMAC0_MTXBCEL_TBNEL_Msk (0xffffffffUL) /*!< TBNEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCPU ======================================================== */ + #define R_RMAC0_MTXBCPU_TBNPU_Pos (0UL) /*!< TBNPU (Bit 0) */ + #define R_RMAC0_MTXBCPU_TBNPU_Msk (0xffffffffUL) /*!< TBNPU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCPL ======================================================== */ + #define R_RMAC0_MTXBCPL_TBNPL_Pos (0UL) /*!< TBNPL (Bit 0) */ + #define R_RMAC0_MTXBCPL_TBNPL_Msk (0xffffffffUL) /*!< TBNPL (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TCM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= TCMPRCR_S ======================================================= */ + #define R_TCM_TCMPRCR_S_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_TCM_TCMPRCR_S_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMPRCR_S_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_TCM_TCMPRCR_S_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== TCMPRCR_NS ======================================================= */ + #define R_TCM_TCMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_TCM_TCMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_TCM_TCMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================== TCMCRC ========================================================= */ + #define R_TCM_TCMCRC_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TCM_TCMCRC_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRC_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_TCM_TCMCRC_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_TCM_TCMCRC_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_TCM_TCMCRC_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRC_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_TCM_TCMCRC_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMCRS ========================================================= */ + #define R_TCM_TCMCRS_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TCM_TCMCRS_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRS_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_TCM_TCMCRS_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_TCM_TCMCRS_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_TCM_TCMCRS_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRS_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_TCM_TCMCRS_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMESR ========================================================= */ + #define R_TCM_TCMESR_ERRC0_Pos (0UL) /*!< ERRC0 (Bit 0) */ + #define R_TCM_TCMESR_ERRC0_Msk (0x1UL) /*!< ERRC0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRC1_Pos (1UL) /*!< ERRC1 (Bit 1) */ + #define R_TCM_TCMESR_ERRC1_Msk (0x2UL) /*!< ERRC1 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRS0_Pos (2UL) /*!< ERRS0 (Bit 2) */ + #define R_TCM_TCMESR_ERRS0_Msk (0x4UL) /*!< ERRS0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRS1_Pos (3UL) /*!< ERRS1 (Bit 3) */ + #define R_TCM_TCMESR_ERRS1_Msk (0x8UL) /*!< ERRS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMESCLR ======================================================== */ + #define R_TCM_TCMESCLR_CLRC0_Pos (0UL) /*!< CLRC0 (Bit 0) */ + #define R_TCM_TCMESCLR_CLRC0_Msk (0x1UL) /*!< CLRC0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRC1_Pos (1UL) /*!< CLRC1 (Bit 1) */ + #define R_TCM_TCMESCLR_CLRC1_Msk (0x2UL) /*!< CLRC1 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRS0_Pos (2UL) /*!< CLRS0 (Bit 2) */ + #define R_TCM_TCMESCLR_CLRS0_Msk (0x4UL) /*!< CLRS0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRS1_Pos (3UL) /*!< CLRS1 (Bit 3) */ + #define R_TCM_TCMESCLR_CLRS1_Msk (0x8UL) /*!< CLRS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMEARC0 ======================================================== */ + #define R_TCM_TCMEARC0_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARC0_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARC1 ======================================================== */ + #define R_TCM_TCMEARC1_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARC1_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARS0 ======================================================== */ + #define R_TCM_TCMEARS0_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARS0_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARS1 ======================================================== */ + #define R_TCM_TCMEARS1_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARS1_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7KA8P1KF_CORE0_H */ + +/** @} */ /* End of group R7KA8P1KF_core0 */ + +/** @} */ /* End of group Renesas */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core1.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core1.h new file mode 100644 index 0000000000..883acf9c89 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7KA8P1KF_core1.h @@ -0,0 +1,94482 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause + * + * @file ./out/R7KA8P1KF_core1.h + * @brief CMSIS HeaderFile + * @version 0.1 + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7KA8P1KF_core1 + * @{ + */ + +#ifndef R7KA8P1KF_CORE1_H + #define R7KA8P1KF_CORE1_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __ICACHE_PRESENT 0 /*!< Instruction Cache present */ + #define __DCACHE_PRESENT 0 /*!< Data Cache present */ + #define __SAUREGION_PRESENT 1 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7KA8P1KF_core1 System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */ + } ADD_b; + }; + + union + { + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */ + } STAT_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */ + __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */ + uint8_t : 2; + } STAT_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x00000004) Bus Error Clear Register */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */ + __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */ + uint8_t : 2; + } CLR_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t IRQEN; /*!< (@ 0x00000008) BUS Error IRQ Enable */ + + struct + { + __IOM uint8_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when + * a bus error occurs */ + uint8_t : 7; + } IRQEN_b; + }; + __IM uint8_t RESERVED2[7]; +} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[36]; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } STAT_b; + }; + __IM uint8_t RESERVED1[7]; + + union + { + __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } CLR_b; + }; +} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */ + +/** + * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } MRE0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } FLBI_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S0BI_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S1BI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S2BI_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } S3BI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } STBYSBI_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } ECBI_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t SPI0BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI0BI_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t SPI1BI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } SPI1BI_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU0SAHBI_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } CPU1TCMBI_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t PBBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PBBI_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t PABI; /*!< (@ 0x00000080) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PABI_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t PIBI; /*!< (@ 0x00000088) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PIBI_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t PSBI; /*!< (@ 0x00000090) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */ + uint32_t : 31; + } PSBI_b; + }; +} R_BUS_BUSSABT0_Type; /*!< Size = 148 (0x94) */ + +/** + * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } FHBI_b; + }; + + union + { + __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } MRC0BI_b; + }; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S0BI_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */ + + struct + { + __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */ + uint32_t : 30; + } S1BI_b; + }; +} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */ + +/** + * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */ + + struct + { + __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */ + } ADD_b; + }; + + union + { + __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read + * Write. */ + + struct + { + __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write + * Status. */ + uint8_t : 7; + } RW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */ + + struct + { + __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */ + __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */ + __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */ + uint16_t : 13; + } BUSOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } BUSOADPT_b; + }; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection + * Register. */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */ + } MSAOAD_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key code */ + } MSAPT_b; + }; +} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */ + +/** + * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */ + + struct + { + __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */ + __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */ + __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */ + __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */ + __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */ + __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */ + __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */ + __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */ + __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */ + __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */ + __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */ + __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */ + __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */ + __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */ + __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */ + __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */ + __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */ + __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */ + __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */ + __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */ + __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */ + __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */ + __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */ + __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */ + __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */ + __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */ + __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */ + __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */ + __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */ + __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */ + __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */ + __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */ + } STAT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */ + + struct + { + __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */ + __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */ + __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */ + __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */ + __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */ + __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */ + __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */ + __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */ + __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */ + __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */ + __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */ + __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */ + __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */ + __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */ + __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */ + __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */ + __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */ + __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */ + __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */ + __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */ + __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */ + __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */ + __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */ + __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */ + __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */ + __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */ + __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */ + __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */ + __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */ + __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */ + __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */ + __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */ + } CLR_b; + }; +} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */ + uint16_t : 2; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED[3]; +} R_ELC_ELSEGR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..52]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 10; /*!< [9..0] Event Link Select */ + uint16_t : 6; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; + }; + + union + { + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ + + struct + { + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; + }; + + union + { + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position + * Register */ + + struct + { + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; + }; + + union + { + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; + }; + + union + { + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + } HSIZE_b; + }; + + union + { + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; + }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ + +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + + struct + { + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; + }; + + union + { + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + + struct + { + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; + }; + + union + { + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + + struct + { + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; + }; + + union + { + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + + struct + { + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; + }; + + union + { + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + + struct + { + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; + }; + + union + { + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + + struct + { + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; + }; + + union + { + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + + struct + { + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; + }; + + union + { + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + + struct + { + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; + }; + + union + { + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + + struct + { + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; + }; + + union + { + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + + struct + { + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; + }; + + union + { + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + + struct + { + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; + }; + + union + { + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + + struct + { + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; + }; + + union + { + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + + struct + { + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; + }; + + union + { + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + + struct + { + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; + }; + + union + { + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + + struct + { + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + + struct + { + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; + }; + + union + { + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + + struct + { + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + + struct + { + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; + }; + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + */ +typedef struct +{ + union + { + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; + }; + + union + { + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + + struct + { + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; + }; + + union + { + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; + }; + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control + * Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; + }; + + union + { + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + + struct + { + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; + }; + + union + { + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ + + struct + { + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; + }; + + union + { + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ + + struct + { + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; + }; + + union + { + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + + struct + { + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; + }; + + union + { + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ + + struct + { + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; + }; +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + + struct + { + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; + + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; + }; + + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; + + union + { + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; + }; + + union + { + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; + }; + + union + { + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; + }; + + union + { + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; + }; + + union + { + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; + + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; + }; + + union + { + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + + struct + { + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; + }; +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ + +/** + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ + + struct + { + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; + }; + + union + { + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ + + struct + { + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; + }; + + union + { + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + + struct + { + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; + }; + + union + { + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + + struct + { + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; + }; + + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ + + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 9; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 7; /*!< [6..0] GTIOCnB Output Rising Edge Delay Setting */ + uint16_t : 9; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control) + */ +typedef struct +{ + union + { + __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */ + __IOM uint16_t RP : 1; /*!< [1..1] Read protection */ + __IOM uint16_t WP : 1; /*!< [2..2] Write protection */ + __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */ + uint16_t : 12; + } AC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */ + + struct + { + __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination. + * NOTE: Some low-order bits are fixed to 0. */ + } S_b; + }; + + union + { + __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */ + + struct + { + __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region + * end, for use in region determination. NOTE: Some low-order + * bits are fixed to 1. */ + } E_b; + }; + __IM uint32_t RESERVED1; +} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } EN_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } ENPT_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } RPT_SEC_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[60]; + __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */ + __IM uint32_t RESERVED5[32]; +} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint32_t : 1; + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint16_t : 1; + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + uint8_t : 1; + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 1; + __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */ + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_XSPI0_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration register 0 */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode */ + __IOM uint32_t ARYAMD : 1; /*!< [5..5] Array address mode */ + uint32_t : 10; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration register 1 */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration register 2 */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CMCFGCS_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CDBUF [CDBUF] (xSPI BUF register) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2byte) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_CDBUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CCCTLCS [CCCTLCS] (xSPI CS register) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control register 0 */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control register 1 */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control register 2 */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3 */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control register 4 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control register 5 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control register 6 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7 */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CCCTLCS_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL) + */ +typedef struct +{ + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_ALT_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */ +} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers) + */ +typedef struct +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, the 16-bit + * counter is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */ +} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_COMA_CABPPPFLC [CABPPPFLC] ([0..2]) + */ +typedef struct +{ + union + { + __IOM uint32_t LEVEL0; /*!< (@ 0x00000000) Port 0 Buffer Pointer Pause Frame Level 0 Configuration + * Register */ + + struct + { + __IOM uint32_t PPDL : 10; /*!< [9..0] Pause De-Assertion Level */ + uint32_t : 6; + __IOM uint32_t PPAL : 10; /*!< [25..16] Pause Assertion Level */ + uint32_t : 6; + } LEVEL0_b; + }; + + union + { + __IOM uint32_t LEVEL1; /*!< (@ 0x00000004) Port 0 Buffer Pointer Pause Frame Level 1 Configuration + * Register */ + + struct + { + __IOM uint32_t PPDL : 10; /*!< [9..0] Pause De-Assertion Level */ + uint32_t : 6; + __IOM uint32_t PPAL : 10; /*!< [25..16] Pause Assertion Level */ + uint32_t : 6; + } LEVEL1_b; + }; +} R_COMA_CABPPPFLC_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_IPC_IPCNMI [IPCNMI] (Inter-Processor NMI Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STA; /*!< (@ 0x00000000) NMI Request Status Register */ + + struct + { + __IM uint32_t NMI : 1; /*!< [0..0] Status of the interrupt request */ + uint32_t : 31; + } STA_b; + }; + + union + { + __OM uint32_t SET; /*!< (@ 0x00000004) NMI Request Set Register */ + + struct + { + __OM uint32_t SET : 1; /*!< [0..0] Sets the NMI request */ + uint32_t : 31; + } SET_b; + }; + + union + { + __OM uint32_t CLR; /*!< (@ 0x00000008) NMI Request Clear Register */ + + struct + { + __OM uint32_t CLR : 1; /*!< [0..0] Clears the NMI request */ + uint32_t : 31; + } CLR_b; + }; + __IM uint32_t RESERVED; +} R_IPC_IPCNMI_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_IPC_IPC_CH [CH] (Inter-Processor Communications Channel Registers) + */ +typedef struct +{ + union + { + __IM uint32_t STA; /*!< (@ 0x00000000) Inter-Processor Status Register */ + + struct + { + __IM uint32_t IRQ0 : 1; /*!< [0..0] Indicates the status of the interrupt request */ + __IM uint32_t IRQ1 : 1; /*!< [1..1] Indicates the status of the interrupt request */ + __IM uint32_t IRQ2 : 1; /*!< [2..2] Indicates the status of the interrupt request */ + __IM uint32_t IRQ3 : 1; /*!< [3..3] Indicates the status of the interrupt request */ + __IM uint32_t IRQ4 : 1; /*!< [4..4] Indicates the status of the interrupt request */ + __IM uint32_t IRQ5 : 1; /*!< [5..5] Indicates the status of the interrupt request */ + __IM uint32_t IRQ6 : 1; /*!< [6..6] Indicates the status of the interrupt request */ + __IM uint32_t IRQ7 : 1; /*!< [7..7] Indicates the status of the interrupt request */ + uint32_t : 8; + __IM uint32_t RDY : 1; /*!< [16..16] This bit is set when FIFO is not empty */ + __IM uint32_t FULL : 1; /*!< [17..17] FIFO is full */ + uint32_t : 6; + __IM uint32_t RERR : 1; /*!< [24..24] Indicates that the message FIFO 00 tried to read Data + * despite Empty */ + __IM uint32_t FERR : 1; /*!< [25..25] Indicates that the message FIFO 00 tried to send more + * data even though it was full */ + uint32_t : 6; + } STA_b; + }; + + union + { + __OM uint32_t SET; /*!< (@ 0x00000004) Inter-Processor IRQ Request Set Register */ + + struct + { + __OM uint32_t SET0 : 1; /*!< [0..0] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET1 : 1; /*!< [1..1] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET2 : 1; /*!< [2..2] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET3 : 1; /*!< [3..3] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET4 : 1; /*!< [4..4] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET5 : 1; /*!< [5..5] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET6 : 1; /*!< [6..6] Sets IPCmSTA0.IRQn */ + __OM uint32_t SET7 : 1; /*!< [7..7] Sets IPCmSTA0.IRQn */ + uint32_t : 24; + } SET_b; + }; + + union + { + __OM uint32_t TXD; /*!< (@ 0x00000008) Inter-Processor FIFO Transfer Data Register */ + + struct + { + __OM uint32_t TXD : 32; /*!< [31..0] Transfer data */ + } TXD_b; + }; + + union + { + __IM uint32_t RXD; /*!< (@ 0x0000000C) Inter-Processor FIFO Receive Data Register */ + + struct + { + __IM uint32_t RXD : 32; /*!< [31..0] Receive data */ + } RXD_b; + }; + + union + { + __OM uint32_t CLR; /*!< (@ 0x00000010) Inter-Processor Clear Register */ + + struct + { + __OM uint32_t CLR0 : 1; /*!< [0..0] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR1 : 1; /*!< [1..1] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR2 : 1; /*!< [2..2] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR3 : 1; /*!< [3..3] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR4 : 1; /*!< [4..4] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR5 : 1; /*!< [5..5] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR6 : 1; /*!< [6..6] Clears the interrupt request for IPCmSTA0.IRQn */ + __OM uint32_t CLR7 : 1; /*!< [7..7] Clears the interrupt request for IPCmSTA0.IRQn */ + uint32_t : 8; + __OM uint32_t RST : 1; /*!< [16..16] Resets message FIFO */ + uint32_t : 7; + __OM uint32_t RCLR : 1; /*!< [24..24] Resets IPCmSTA0.RERR */ + __OM uint32_t FCLR : 1; /*!< [25..25] Resets IPCmSTA0.FERR */ + uint32_t : 6; + } CLR_b; + }; + __IM uint32_t RESERVED[3]; +} R_IPC_IPC_CH_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_IPC_IPC [IPC] (Inter-Processor Registers) + */ +typedef struct +{ + __IOM R_IPC_IPC_CH_Type CH[2]; /*!< (@ 0x00000000) Inter-Processor Communications Channel Registers */ +} R_IPC_IPC_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PDM_CH [CH] (PDM Channel-Specific Registers) + */ +typedef struct +{ + union + { + __OM uint32_t PDSTRTR; /*!< (@ 0x00000000) Software Start Trigger Register */ + + struct + { + __OM uint32_t STRTRG : 1; /*!< [0..0] Start trigger */ + uint32_t : 31; + } PDSTRTR_b; + }; + + union + { + __OM uint32_t PDSTPTR; /*!< (@ 0x00000004) Software Stop Trigger Register */ + + struct + { + __OM uint32_t STPTRG : 1; /*!< [0..0] Stop trigger */ + uint32_t : 31; + } PDSTPTR_b; + }; + + union + { + __OM uint32_t PDCHGTR; /*!< (@ 0x00000008) Software Change Trigger Register */ + + struct + { + __OM uint32_t CHGTRG : 1; /*!< [0..0] Change trigger */ + uint32_t : 31; + } PDCHGTR_b; + }; + + union + { + __IOM uint32_t PDICR; /*!< (@ 0x0000000C) Interrupt Control Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t ISDE : 1; /*!< [1..1] Sound detection interrupt enable bit */ + __IOM uint32_t IDRE : 1; /*!< [2..2] Data reception interrupt enable bit */ + uint32_t : 13; + __IOM uint32_t IEDE : 1; /*!< [16..16] Error detection interrupt enable bit */ + uint32_t : 15; + } PDICR_b; + }; + + union + { + __IOM uint32_t PDSDCR; /*!< (@ 0x00000010) Status Detection Control Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t SDE : 1; /*!< [1..1] Sound detection enable bit */ + uint32_t : 14; + __IOM uint32_t SCDE : 1; /*!< [16..16] Short circuit detection enable bit */ + __IOM uint32_t OVLDE : 1; /*!< [17..17] Overvoltage lower limit exceeded detection enable bit */ + __IOM uint32_t OVUDE : 1; /*!< [18..18] Overvoltage upper limit exceeded detection enable bit */ + uint32_t : 8; + __IOM uint32_t BFOWDE : 1; /*!< [27..27] Buffer overwriting detection enable bit */ + uint32_t : 4; + } PDSDCR_b; + }; + + union + { + __IM uint32_t PDSR; /*!< (@ 0x00000014) Status Register */ + + struct + { + __IM uint32_t STATE : 1; /*!< [0..0] State */ + __IM uint32_t SDF : 1; /*!< [1..1] Sound detection flag */ + __IM uint32_t DRF : 1; /*!< [2..2] Data reception flag */ + uint32_t : 13; + __IM uint32_t SCDF : 1; /*!< [16..16] Short circuit detection flag */ + __IM uint32_t OVLDF : 1; /*!< [17..17] Overvoltage lower limit exceeded detection flag */ + __IM uint32_t OVUDF : 1; /*!< [18..18] Overvoltage upper limit exceeded detection flag */ + uint32_t : 8; + __IM uint32_t BFOWDF : 1; /*!< [27..27] Buffer overwriting detection flag */ + uint32_t : 4; + } PDSR_b; + }; + + union + { + __OM uint32_t PDSCR; /*!< (@ 0x00000018) Status Clear Register */ + + struct + { + uint32_t : 1; + __OM uint32_t SDFC : 1; /*!< [1..1] Sound detection flag clear */ + uint32_t : 14; + __OM uint32_t SCDFC : 1; /*!< [16..16] Short circuit detection flag clear */ + __OM uint32_t OVLDFC : 1; /*!< [17..17] Overvoltage lower limit exceeded detection flag clear */ + __OM uint32_t OVUDFC : 1; /*!< [18..18] Overvoltage upper limit exceeded detection flag clear */ + uint32_t : 8; + __OM uint32_t BFOWDFC : 1; /*!< [27..27] Buffer overwriting detection flag clear */ + uint32_t : 4; + } PDSCR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PDMDSR; /*!< (@ 0x00000020) Mode Setting Register */ + + struct + { + __IOM uint32_t INPSEL : 1; /*!< [0..0] Input data select */ + uint32_t : 3; + __IOM uint32_t SFMD : 3; /*!< [6..4] Sinc filter mode setting */ + uint32_t : 1; + __IOM uint32_t HFIS : 2; /*!< [9..8] High-pass filter input shift setting */ + uint32_t : 2; + __IOM uint32_t CFIS : 2; /*!< [13..12] Compensation filter input shift setting */ + uint32_t : 2; + __IOM uint32_t LFIS : 2; /*!< [17..16] Low-pass (half-band decimation) filter input shift + * setting */ + uint32_t : 6; + __IOM uint32_t SDMAMD : 2; /*!< [25..24] Moving average mode for sound detection data */ + uint32_t : 2; + __IOM uint32_t DBIS : 4; /*!< [31..28] Data buffer input shift setting */ + } PDMDSR_b; + }; + + union + { + __IOM uint32_t PDSFCR; /*!< (@ 0x00000024) Sinc filter Control Register */ + + struct + { + __IOM uint32_t CKDIV : 4; /*!< [3..0] PDM_CLKn's dividend ratio to core clock */ + uint32_t : 12; + __IOM uint32_t SINCDEC : 8; /*!< [23..16] Sinc filter decimation ratio */ + __IOM uint32_t SINCRNG : 5; /*!< [28..24] Sinc filter output valid range */ + uint32_t : 3; + } PDSFCR_b; + }; + + union + { + __IOM uint32_t PDHFCS0R; /*!< (@ 0x00000028) High-pass filter Coefficient s(0) Register */ + + struct + { + __IOM uint32_t HFS0 : 16; /*!< [15..0] High-pass filter coefficient s(0) */ + uint32_t : 16; + } PDHFCS0R_b; + }; + + union + { + __IOM uint32_t PDHFCK1R; /*!< (@ 0x0000002C) High-pass filter Coefficient k(1) Register */ + + struct + { + __IOM uint32_t HFK1 : 16; /*!< [15..0] High-pass filter coefficient k(1) */ + uint32_t : 16; + } PDHFCK1R_b; + }; + + union + { + __IOM uint32_t PDHFCHR[2]; /*!< (@ 0x00000030) High-pass filter Coefficient h([0..1]) Registers */ + + struct + { + __IOM uint32_t HFHn : 16; /*!< [15..0] High-pass filter coefficient h(n) */ + uint32_t : 16; + } PDHFCHR_b[2]; + }; + + union + { + __IOM uint32_t PDCFCHR[11]; /*!< (@ 0x00000038) Compensation filter Coefficient h([0..10]) Registers */ + + struct + { + __IOM uint32_t CFHn : 13; /*!< [12..0] Compensation filter coefficient h(n) */ + uint32_t : 19; + } PDCFCHR_b[11]; + }; + + union + { + __IOM uint32_t PDLFCH010R; /*!< (@ 0x00000064) Low-pass filter Coefficient h0(10) Register */ + + struct + { + __IOM uint32_t LFH010 : 13; /*!< [12..0] Low-pass (half-band decimation) filter coefficient h0(10) */ + uint32_t : 19; + } PDLFCH010R_b; + }; + + union + { + __IOM uint32_t PDLFCH1R[20]; /*!< (@ 0x00000068) Low-pass filter Coefficient h1([0..19]) Registers */ + + struct + { + __IOM uint32_t LFH1n : 13; /*!< [12..0] Low-pass (half-band decimation) filter coefficient h1(n) */ + uint32_t : 19; + } PDLFCH1R_b[20]; + }; + + union + { + __IOM uint32_t PDSDLTR; /*!< (@ 0x000000B8) Sound Detection Lower Threshold Register */ + + struct + { + __IOM uint32_t SDETL : 20; /*!< [19..0] Sound detection lower limit */ + uint32_t : 12; + } PDSDLTR_b; + }; + + union + { + __IOM uint32_t PDSDUTR; /*!< (@ 0x000000BC) Sound Detection Upper Threshold Register */ + + struct + { + __IOM uint32_t SDETU : 20; /*!< [19..0] Sound detection upper limit */ + uint32_t : 12; + } PDSDUTR_b; + }; + + union + { + __IOM uint32_t PDDBCR; /*!< (@ 0x000000C0) Data Buffer Control Register */ + + struct + { + __IOM uint32_t DATRITHR : 3; /*!< [2..0] Data reception interrupt threshold */ + uint32_t : 29; + } PDDBCR_b; + }; + + union + { + __IOM uint32_t PDSCTSR; /*!< (@ 0x000000C4) Short Circuit Threshold Setting Register */ + + struct + { + __IOM uint32_t SCDL : 13; /*!< [12..0] Short circuit detection Low Continuous detection count */ + uint32_t : 3; + __IOM uint32_t SCDH : 13; /*!< [28..16] Short circuit detection High Continuous detection count */ + uint32_t : 3; + } PDSCTSR_b; + }; + + union + { + __IOM uint32_t PDOVLTR; /*!< (@ 0x000000C8) Overvoltage Lower Threshold Register */ + + struct + { + __IOM uint32_t OVDL : 20; /*!< [19..0] Overvoltage detection lower limit */ + uint32_t : 12; + } PDOVLTR_b; + }; + + union + { + __IOM uint32_t PDOVUTR; /*!< (@ 0x000000CC) Overvoltage Upper Threshold Register */ + + struct + { + __IOM uint32_t OVDU : 20; /*!< [19..0] Overvoltage detection upper limit */ + uint32_t : 12; + } PDOVUTR_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t PDDRCR; /*!< (@ 0x000000E0) Data Read Control Register */ + + struct + { + __IOM uint32_t DATRE : 1; /*!< [0..0] Data read enable bit */ + uint32_t : 31; + } PDDRCR_b; + }; + + union + { + __OM uint32_t PDDCR; /*!< (@ 0x000000E4) Data Clear Register */ + + struct + { + __OM uint32_t DATC : 1; /*!< [0..0] Data clear */ + uint32_t : 31; + } PDDCR_b; + }; + + union + { + __IM uint32_t PDDRR; /*!< (@ 0x000000E8) Data Read Register */ + + struct + { + __IM uint32_t DAT : 20; /*!< [19..0] Data */ + uint32_t : 12; + } PDDRR_b; + }; + + union + { + __IM uint32_t PDDSR; /*!< (@ 0x000000EC) Data Status Register */ + + struct + { + __IM uint32_t DATNUM : 8; /*!< [7..0] Number of data stored in buffer */ + uint32_t : 24; + } PDDSR_b; + }; + __IM uint32_t RESERVED2[4]; +} R_PDM_CH_Type; /*!< Size = 256 (0x100) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; + __IM uint8_t RESERVED4[47]; + + union + { + __IOM uint8_t CPINTCTL; /*!< (@ 0x00000040) Comparator Interrupt Control Register */ + + struct + { + __IOM uint8_t MSKE : 1; /*!< [0..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 7; + } CPINTCTL_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t CPMSKCTL; /*!< (@ 0x00000044) Comparator Interrupt Mask Control Register */ + + struct + { + __IOM uint8_t MSKSEL : 3; /*!< [2..0] Comparator Interrupt Periodic Mask Enable */ + uint8_t : 5; + } CPMSKCTL_b; + }; +} R_ACMPHS0_Type; /*!< Size = 69 (0x45) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x40204000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + __IOM uint32_t PSARB0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARB1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARB4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARB5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARB6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARB10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARB11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARB13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARB14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARB15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARB16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARB17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARB18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARB20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARB21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARB22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARC2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARC3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARC4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARC5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARC6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARC7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARC8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARC9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARC10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARC11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARC12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARC14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARC15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARC16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARC17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARC18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARC19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARC20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARC21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARC22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARC23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARC24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARC25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARC26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARC28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARC29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARC30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARC31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARD4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARD5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARD6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARD7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARD8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARD9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARD10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARD11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARD17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARD18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARD19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARD21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARD22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARD23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARD24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARD25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARD29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARD30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARD31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] Peripheral security attribution bit 0 */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] Peripheral security attribution bit 1 */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] Peripheral security attribution bit 2 */ + __IOM uint32_t PSARE3 : 1; /*!< [3..3] Peripheral security attribution bit 3 */ + __IOM uint32_t PSARE4 : 1; /*!< [4..4] Peripheral security attribution bit 4 */ + __IOM uint32_t PSARE5 : 1; /*!< [5..5] Peripheral security attribution bit 5 */ + __IOM uint32_t PSARE6 : 1; /*!< [6..6] Peripheral security attribution bit 6 */ + __IOM uint32_t PSARE7 : 1; /*!< [7..7] Peripheral security attribution bit 7 */ + __IOM uint32_t PSARE8 : 1; /*!< [8..8] Peripheral security attribution bit 8 */ + __IOM uint32_t PSARE9 : 1; /*!< [9..9] Peripheral security attribution bit 9 */ + __IOM uint32_t PSARE10 : 1; /*!< [10..10] Peripheral security attribution bit 10 */ + __IOM uint32_t PSARE11 : 1; /*!< [11..11] Peripheral security attribution bit 11 */ + __IOM uint32_t PSARE12 : 1; /*!< [12..12] Peripheral security attribution bit 12 */ + __IOM uint32_t PSARE13 : 1; /*!< [13..13] Peripheral security attribution bit 13 */ + __IOM uint32_t PSARE14 : 1; /*!< [14..14] Peripheral security attribution bit 14 */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] Peripheral security attribution bit 15 */ + __IOM uint32_t PSARE16 : 1; /*!< [16..16] Peripheral security attribution bit 16 */ + __IOM uint32_t PSARE17 : 1; /*!< [17..17] Peripheral security attribution bit 17 */ + __IOM uint32_t PSARE18 : 1; /*!< [18..18] Peripheral security attribution bit 18 */ + __IOM uint32_t PSARE19 : 1; /*!< [19..19] Peripheral security attribution bit 19 */ + __IOM uint32_t PSARE20 : 1; /*!< [20..20] Peripheral security attribution bit 20 */ + __IOM uint32_t PSARE21 : 1; /*!< [21..21] Peripheral security attribution bit 21 */ + __IOM uint32_t PSARE22 : 1; /*!< [22..22] Peripheral security attribution bit 22 */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] Peripheral security attribution bit 23 */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] Peripheral security attribution bit 24 */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] Peripheral security attribution bit 25 */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] Peripheral security attribution bit 26 */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] Peripheral security attribution bit 27 */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] Peripheral security attribution bit 28 */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] Peripheral security attribution bit 29 */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] Peripheral security attribution bit 30 */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] Peripheral security attribution bit 31 */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] Module stop security attribution bit 0 */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] Module stop security attribution bit 1 */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] Module stop security attribution bit 2 */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] Module stop security attribution bit 3 */ + __IOM uint32_t MSSAR4 : 1; /*!< [4..4] Module stop security attribution bit 4 */ + __IOM uint32_t MSSAR5 : 1; /*!< [5..5] Module stop security attribution bit 5 */ + __IOM uint32_t MSSAR6 : 1; /*!< [6..6] Module stop security attribution bit 6 */ + __IOM uint32_t MSSAR7 : 1; /*!< [7..7] Module stop security attribution bit 7 */ + __IOM uint32_t MSSAR8 : 1; /*!< [8..8] Module stop security attribution bit 8 */ + __IOM uint32_t MSSAR9 : 1; /*!< [9..9] Module stop security attribution bit 9 */ + __IOM uint32_t MSSAR10 : 1; /*!< [10..10] Module stop security attribution bit 10 */ + __IOM uint32_t MSSAR11 : 1; /*!< [11..11] Module stop security attribution bit 11 */ + __IOM uint32_t MSSAR12 : 1; /*!< [12..12] Module stop security attribution bit 12 */ + __IOM uint32_t MSSAR13 : 1; /*!< [13..13] Module stop security attribution bit 13 */ + __IOM uint32_t MSSAR14 : 1; /*!< [14..14] Module stop security attribution bit 14 */ + __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Module stop security attribution bit 15 */ + __IOM uint32_t MSSAR16 : 1; /*!< [16..16] Module stop security attribution bit 16 */ + __IOM uint32_t MSSAR17 : 1; /*!< [17..17] Module stop security attribution bit 17 */ + __IOM uint32_t MSSAR18 : 1; /*!< [18..18] Module stop security attribution bit 18 */ + __IOM uint32_t MSSAR19 : 1; /*!< [19..19] Module stop security attribution bit 19 */ + __IOM uint32_t MSSAR20 : 1; /*!< [20..20] Module stop security attribution bit 20 */ + __IOM uint32_t MSSAR21 : 1; /*!< [21..21] Module stop security attribution bit 21 */ + __IOM uint32_t MSSAR22 : 1; /*!< [22..22] Module stop security attribution bit 22 */ + __IOM uint32_t MSSAR23 : 1; /*!< [23..23] Module stop security attribution bit 23 */ + __IOM uint32_t MSSAR24 : 1; /*!< [24..24] Module stop security attribution bit 24 */ + __IOM uint32_t MSSAR25 : 1; /*!< [25..25] Module stop security attribution bit 25 */ + __IOM uint32_t MSSAR26 : 1; /*!< [26..26] Module stop security attribution bit 26 */ + __IOM uint32_t MSSAR27 : 1; /*!< [27..27] Module stop security attribution bit 27 */ + __IOM uint32_t MSSAR28 : 1; /*!< [28..28] Module stop security attribution bit 28 */ + __IOM uint32_t MSSAR29 : 1; /*!< [29..29] Module stop security attribution bit 29 */ + __IOM uint32_t MSSAR30 : 1; /*!< [30..30] Module stop security attribution bit 30 */ + __IOM uint32_t MSSAR31 : 1; /*!< [31..31] Module stop security attribution bit 31 */ + } MSSAR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */ + + struct + { + __IOM uint32_t PPARB0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARB1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARB2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARB3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARB4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARB5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARB6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARB7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARB8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARB9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARB10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARB11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARB12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARB13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARB14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARB15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARB16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARB17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARB18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARB19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARB20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARB21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARB22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARB23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARB24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARB25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARB26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARB27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARB28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARB29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARB30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARB31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARB_b; + }; + + union + { + __IOM uint32_t PPARC; /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C */ + + struct + { + __IOM uint32_t PPARC0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARC1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARC2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARC3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARC4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARC5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARC6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARC7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARC8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARC9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARC10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARC11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARC12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARC13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARC14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARC15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARC16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARC17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARC18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARC19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARC20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARC21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARC22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARC23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARC24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARC25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARC26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARC27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARC28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARC29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARC30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARC31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARC_b; + }; + + union + { + __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */ + + struct + { + __IOM uint32_t PPARD0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARD1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARD2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARD3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARD4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARD5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARD6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARD7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARD8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARD9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARD10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARD11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARD12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARD13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARD14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARD15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARD16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARD17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARD18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARD19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARD20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARD21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARD22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARD23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARD24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARD25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARD26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARD27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARD28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARD29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARD30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARD31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARD_b; + }; + + union + { + __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */ + + struct + { + __IOM uint32_t PPARE0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t PPARE1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t PPARE2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t PPARE3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t PPARE4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t PPARE5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t PPARE6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t PPARE7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t PPARE8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t PPARE9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t PPARE10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t PPARE11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t PPARE12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t PPARE13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t PPARE14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t PPARE15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t PPARE16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t PPARE17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t PPARE18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t PPARE19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t PPARE20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t PPARE21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t PPARE22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t PPARE23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t PPARE24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t PPARE25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t PPARE26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t PPARE27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t PPARE28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t PPARE29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t PPARE30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t PPARE31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } PPARE_b; + }; + + union + { + __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */ + + struct + { + __IOM uint32_t MSPAR0 : 1; /*!< [0..0] Peripheral privilege attribution bit 0 */ + __IOM uint32_t MSPAR1 : 1; /*!< [1..1] Peripheral privilege attribution bit 1 */ + __IOM uint32_t MSPAR2 : 1; /*!< [2..2] Peripheral privilege attribution bit 2 */ + __IOM uint32_t MSPAR3 : 1; /*!< [3..3] Peripheral privilege attribution bit 3 */ + __IOM uint32_t MSPAR4 : 1; /*!< [4..4] Peripheral privilege attribution bit 4 */ + __IOM uint32_t MSPAR5 : 1; /*!< [5..5] Peripheral privilege attribution bit 5 */ + __IOM uint32_t MSPAR6 : 1; /*!< [6..6] Peripheral privilege attribution bit 6 */ + __IOM uint32_t MSPAR7 : 1; /*!< [7..7] Peripheral privilege attribution bit 7 */ + __IOM uint32_t MSPAR8 : 1; /*!< [8..8] Peripheral privilege attribution bit 8 */ + __IOM uint32_t MSPAR9 : 1; /*!< [9..9] Peripheral privilege attribution bit 9 */ + __IOM uint32_t MSPAR10 : 1; /*!< [10..10] Peripheral privilege attribution bit 10 */ + __IOM uint32_t MSPAR11 : 1; /*!< [11..11] Peripheral privilege attribution bit 11 */ + __IOM uint32_t MSPAR12 : 1; /*!< [12..12] Peripheral privilege attribution bit 12 */ + __IOM uint32_t MSPAR13 : 1; /*!< [13..13] Peripheral privilege attribution bit 13 */ + __IOM uint32_t MSPAR14 : 1; /*!< [14..14] Peripheral privilege attribution bit 14 */ + __IOM uint32_t MSPAR15 : 1; /*!< [15..15] Peripheral privilege attribution bit 15 */ + __IOM uint32_t MSPAR16 : 1; /*!< [16..16] Peripheral privilege attribution bit 16 */ + __IOM uint32_t MSPAR17 : 1; /*!< [17..17] Peripheral privilege attribution bit 17 */ + __IOM uint32_t MSPAR18 : 1; /*!< [18..18] Peripheral privilege attribution bit 18 */ + __IOM uint32_t MSPAR19 : 1; /*!< [19..19] Peripheral privilege attribution bit 19 */ + __IOM uint32_t MSPAR20 : 1; /*!< [20..20] Peripheral privilege attribution bit 20 */ + __IOM uint32_t MSPAR21 : 1; /*!< [21..21] Peripheral privilege attribution bit 21 */ + __IOM uint32_t MSPAR22 : 1; /*!< [22..22] Peripheral privilege attribution bit 22 */ + __IOM uint32_t MSPAR23 : 1; /*!< [23..23] Peripheral privilege attribution bit 23 */ + __IOM uint32_t MSPAR24 : 1; /*!< [24..24] Peripheral privilege attribution bit 24 */ + __IOM uint32_t MSPAR25 : 1; /*!< [25..25] Peripheral privilege attribution bit 25 */ + __IOM uint32_t MSPAR26 : 1; /*!< [26..26] Peripheral privilege attribution bit 26 */ + __IOM uint32_t MSPAR27 : 1; /*!< [27..27] Peripheral privilege attribution bit 27 */ + __IOM uint32_t MSPAR28 : 1; /*!< [28..28] Peripheral privilege attribution bit 28 */ + __IOM uint32_t MSPAR29 : 1; /*!< [29..29] Peripheral privilege attribution bit 29 */ + __IOM uint32_t MSPAR30 : 1; /*!< [30..30] Peripheral privilege attribution bit 30 */ + __IOM uint32_t MSPAR31 : 1; /*!< [31..31] Peripheral privilege attribution bit 31 */ + } MSPAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code MRAM Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Secure area */ + uint32_t : 8; + } CFSAMONA_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; + + union + { + __IM uint32_t SFSAMON; /*!< (@ 0x0000003C) SiP Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t SFS : 9; /*!< [23..15] SiP Flash Secure Area */ + uint32_t : 8; + } SFSAMON_b; + }; +} R_PSCU_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + + union + { + __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */ + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */ + }; + __IM uint32_t RESERVED4[58]; + + union + { + union + { + __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */ + + struct + { + __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */ + uint32_t : 31; + } BUSMABT_b; + }; + __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + }; + __IM uint32_t RESERVED5[46]; + + union + { + __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */ + __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */ + }; + __IM uint32_t RESERVED6[27]; + + union + { + __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */ + + struct + { + __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */ + uint32_t : 2; + __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */ + uint32_t : 12; + __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */ + uint32_t : 15; + } BUSDIVBYP_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint16_t BUSTHRPUT; /*!< (@ 0x00001400) Graphic Bus Throughput Control Register */ + + struct + { + __IOM uint16_t DIS : 1; /*!< [0..0] Bandwidth Control Function */ + uint16_t : 15; + } BUSTHRPUT_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[255]; + __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED10[16]; + + union + { + __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address + * and Read/Write Status registers. */ + }; + __IM uint32_t RESERVED11[28]; + + union + { + __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */ + __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */ + }; + __IM uint32_t RESERVED12[16]; + __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */ +} R_BUS_Type; /*!< Size = 6924 (0x1b0c) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40202400) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) + */ + +typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 2; /*!< [1..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 30; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40310000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit D/A converter (R_DAC_B0) + */ + +typedef struct /*!< (@ 0x40233000) R_DAC_B0 Structure */ +{ + union + { + __IOM uint16_t DADR; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A converted data */ + } DADR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint32_t DACR0; /*!< (@ 0x00000004) D/A Control Register 0 */ + + struct + { + __IOM uint32_t DACEN : 1; /*!< [0..0] DA enable bit */ + uint32_t : 14; + __IOM uint32_t DAE : 1; /*!< [15..15] DA batch conversion control bit */ + uint32_t : 15; + __IOM uint32_t DAOUTDIS : 1; /*!< [31..31] Analog output disable bit */ + } DACR0_b; + }; + + union + { + __IOM uint32_t DACR1; /*!< (@ 0x00000008) D/A Control Register 1 */ + + struct + { + uint32_t : 16; + __IOM uint32_t DPSEL : 1; /*!< [16..16] Data placement selection bit */ + uint32_t : 15; + } DACR1_b; + }; + + union + { + __IOM uint32_t DACR2; /*!< (@ 0x0000000C) D/A Control Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t OFSSEL : 1; /*!< [8..8] DAC-HM operating voltage mode select bit */ + uint32_t : 23; + } DACR2_b; + }; +} R_DAC_B0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT1 : 1; /*!< [2..2] Mask bit for WDT1 reset/interrupt in the OCD run mode */ + uint32_t : 11; + __IOM uint32_t DBGSTOP_TIM : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt */ + __IOM uint32_t DBGSTOP_SIR : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interrupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interrupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + __IOM uint32_t DBGSTOP_NVMERR : 1; /*!< [26..26] Mask bit for MRAM ECC error reset/interrupt */ + uint32_t : 1; + __IOM uint32_t DBGSTOP_CTERR0 : 1; /*!< [28..28] Mask bit for CPU0's Cache/TCM ECC error reset */ + __IOM uint32_t DBGSTOP_CTERR1 : 1; /*!< [29..29] This bit is reserved. It can be R/W but no effect */ + uint32_t : 1; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DBGAUTH0; /*!< (@ 0x00000020) Debug Authentication Control Register0 */ + + struct + { + __IOM uint32_t DBGEN0 : 1; /*!< [0..0] CPU0 invasive debug enable */ + __IOM uint32_t DBGEN1 : 1; /*!< [1..1] CPU1 invasive debug enable */ + uint32_t : 2; + __IOM uint32_t NIDEN0 : 1; /*!< [4..4] CPU0 non-invasive debug enable */ + __IOM uint32_t NIDEN1 : 1; /*!< [5..5] CPU1 non-invasive debug enable */ + uint32_t : 10; + __IOM uint32_t DEVICEEN : 1; /*!< [16..16] APB-AP (AP1) authentication */ + uint32_t : 14; + __IM uint32_t SWDBG : 1; /*!< [31..31] Software control of debug function */ + } DBGAUTH0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t TRPORTCR; /*!< (@ 0x00000030) Trace Port Control Register */ + + struct + { + __IOM uint32_t OE : 1; /*!< [0..0] Data Out Enable bit indicates whether Trace Clock, Trace + * Data and SWO outputs are enabled or not. */ + uint32_t : 1; + __IOM uint32_t DRV : 2; /*!< [3..2] Port Drive Capability Control indicate trace port buffer + * speed */ + uint32_t : 4; + __IOM uint32_t PORTSEL : 2; /*!< [9..8] None */ + uint32_t : 6; + __IOM uint32_t SWOSEL : 1; /*!< [16..16] Select SWO between CPU0 and CPU1 */ + uint32_t : 15; + } TRPORTCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t TRPORTSZ; /*!< (@ 0x00000038) Trace Port Size Control Register */ + + struct + { + __IOM uint32_t PORTSIZE : 32; /*!< [31..0] Indicates how many pins of TRACEDATA are available. */ + } TRPORTSZ_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t CACHEDBGCR; /*!< (@ 0x00000040) Cache Debug Control Register */ + + struct + { + __IOM uint32_t L1RSTDIS : 1; /*!< [0..0] Disable L1 cache automatic invalidation of CPU0 */ + uint32_t : 31; + } CACHEDBGCR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t DBGNVMCR; /*!< (@ 0x00000050) Debug Non-volatile Memory Control Register */ + + struct + { + __IOM uint32_t NVMWE : 1; /*!< [0..0] Non-volatile memory write enable */ + uint32_t : 31; + } DBGNVMCR_b; + }; + __IM uint32_t RESERVED6[43]; + + union + { + __IOM uint32_t ALCTRL; /*!< (@ 0x00000100) Authentication Level Control Register */ + + struct + { + __IOM uint32_t AL : 8; /*!< [7..0] AL monitor */ + uint32_t : 22; + __IOM uint32_t FAILCNT : 2; /*!< [31..30] Number of times responding incorrect response data */ + } ALCTRL_b; + }; + __IM uint32_t RESERVED7[63]; + + union + { + __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */ + + struct + { + __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */ + __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */ + uint32_t : 6; + __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */ + uint32_t : 21; + } FSBLSTAT_b; + }; +} R_DEBUG_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x4000A800) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint8_t DMCTL; /*!< (@ 0x00000010) DMAC Control Register */ + + struct + { + __IOM uint8_t PR : 1; /*!< [0..0] Priority Control Select */ + uint8_t : 3; + __IOM uint8_t ERCH : 1; /*!< [4..4] Clear Channel Select */ + uint8_t : 3; + } DMCTL_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[11]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 4; /*!< [3..0] DMAC Error channel */ + uint32_t : 4; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; + __IM uint32_t RESERVED6[15]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; +} R_DMA_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x4000A000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x40444000) R_DRW Structure */ +{ + union + { + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ + + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; + }; + + union + { + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union + { + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; + }; + __IM uint32_t RESERVED[2]; + + union + { + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; + }; + + union + { + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; + }; + + union + { + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; + }; + + union + { + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; + }; + + union + { + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; + }; + + union + { + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; + }; + + union + { + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; + }; + + union + { + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; + }; + + union + { + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; + }; + + union + { + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; + }; + + union + { + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; + }; + + union + { + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; + }; + + union + { + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; + }; + + union + { + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; + }; + + union + { + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; + }; + + union + { + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; + }; + + union + { + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; + }; + + union + { + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; + }; + + union + { + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; + }; + + union + { + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; + }; + __IM uint32_t RESERVED1; + + union + { + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + + struct + { + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; + }; + + union + { + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + + struct + { + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + + struct + { + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; + }; + + union + { + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + + struct + { + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; + }; + + union + { + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + + struct + { + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; + + union + { + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + + struct + { + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + + struct + { + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; + }; + + union + { + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + + struct + { + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; + }; + + union + { + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + + struct + { + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; + }; + + union + { + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + + struct + { + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; + }; + + union + { + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + + struct + { + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; + }; + + union + { + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; + }; + + union + { + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; + }; + + union + { + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + + struct + { + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + + struct + { + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; + }; + + union + { + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + + struct + { + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; + }; + + union + { + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + + struct + { + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; + }; + + union + { + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + + struct + { + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; + }; + + union + { + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + + struct + { + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; + }; + + union + { + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + + struct + { + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; + }; + + union + { + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; + }; + + union + { + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; + }; + + union + { + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + + struct + { + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + + struct + { + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; + }; + + union + { + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + + struct + { + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; + }; + + union + { + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + + struct + { + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; + }; + + union + { + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + + struct + { + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t DBWER; /*!< (@ 0x00000100) DRW Bufferable Write Enable Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t BWE : 1; /*!< [2..2] Bufferable Write Enable */ + uint32_t : 29; + } DBWER_b; + }; +} R_DRW_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x4000AC00) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_b; + }; + + union + { + __IOM uint8_t DTCADMOD; /*!< (@ 0x00000008) DTC Address Mode Register */ + + struct + { + __IOM uint8_t SHORT : 1; /*!< [0..0] Short-Address Mode Set */ + uint8_t : 7; + } DTCADMOD_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address. */ + } DTCVBR_SEC_b; + }; + + union + { + __IOM uint32_t DTCDISP; /*!< (@ 0x00000018) DTC Address Displacement Register */ + + struct + { + __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement */ + } DTCDISP_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; + + union + { + __IOM uint32_t DTCIBR; /*!< (@ 0x00000024) DTC Index Table Base Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address */ + } DTCIBR_b; + }; + + union + { + __IOM uint8_t DTCOR; /*!< (@ 0x00000028) DTC Operation Register */ + + struct + { + __IOM uint8_t SQTFRL : 1; /*!< [0..0] Sequence Transfer Stop */ + uint8_t : 7; + } DTCOR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t DTCSQE; /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register */ + + struct + { + __IOM uint16_t VECN : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified */ + uint16_t : 7; + __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable */ + } DTCSQE_b; + }; + __IM uint16_t RESERVED10; +} R_DTC_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40201000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IOM R_ELC_ELSEGR_Type ELSEGR[4]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */ + __IM uint32_t RESERVED2[3]; + __IOM R_ELC_ELSR_Type ELSR[53]; /*!< (@ 0x00000020) Event Link Setting Register [0..52] */ + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t ELCSARA; /*!< (@ 0x00000100) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Security + * Attribution */ + __IOM uint32_t ELSEGR2 : 1; /*!< [3..3] Event Link Software Event Generation Register 2 Security + * Attribution */ + __IOM uint32_t ELSEGR3 : 1; /*!< [4..4] Event Link Software Event Generation Register 3 Security + * Attribution */ + uint32_t : 27; + } ELCSARA_b; + }; + + union + { + __IOM uint32_t ELCSARB; /*!< (@ 0x00000104) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Security Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Security Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Security Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Security Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Security Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Security Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Security Attribution */ + } ELCSARB_b; + }; + + union + { + __IOM uint32_t ELCSARC; /*!< (@ 0x00000108) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Security Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Security Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Security Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Security Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Security Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Security Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Security Attribution */ + } ELCSARC_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ELCPARA; /*!< (@ 0x00000110) Event Link Controller Privilege Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller Register Privilege Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Privilege + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Privilege + * Attribution */ + __IOM uint32_t ELSEGR2 : 1; /*!< [3..3] Event Link Software Event Generation Register 2 Privilege + * Attribution */ + __IOM uint32_t ELSEGR3 : 1; /*!< [4..4] Event Link Software Event Generation Register 3 Privilege + * Attribution */ + uint32_t : 27; + } ELCPARA_b; + }; + + union + { + __IOM uint32_t ELCPARB; /*!< (@ 0x00000114) Event Link Controller Privilege Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Privilege Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Privilege Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Privilege Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Privilege Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Privilege Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Privilege Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Privilege Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Privilege Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Privilege Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Privilege Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Privilege Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Privilege Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Privilege Attribution */ + } ELCPARB_b; + }; + + union + { + __IOM uint32_t ELCPARC; /*!< (@ 0x00000118) Event Link Controller Privilege Attribution Register + * C */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Privilege Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Privilege Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Privilege Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Privilege Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Privilege Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Privilege Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Privilege Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Privilege Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Privilege Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Privilege Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Privilege Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Privilege Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Privilege Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Privilege Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Privilege Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Privilege Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Privilege Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Privilege Attribution */ + __IOM uint32_t ELSR18 : 1; /*!< [18..18] Event Link Setting Register 18 Privilege Attribution */ + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 19 Privilege Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 20 Privilege Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 21 Privilege Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 22 Privilege Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 23 Privilege Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 24 Privilege Attribution */ + __IOM uint32_t ELSR25 : 1; /*!< [25..25] Event Link Setting Register 25 Privilege Attribution */ + __IOM uint32_t ELSR26 : 1; /*!< [26..26] Event Link Setting Register 26 Privilege Attribution */ + __IOM uint32_t ELSR27 : 1; /*!< [27..27] Event Link Setting Register 27 Privilege Attribution */ + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 28 Privilege Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 29 Privilege Attribution */ + __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Privilege Attribution */ + __IOM uint32_t ELSR31 : 1; /*!< [31..31] Event Link Setting Register 31 Privilege Attribution */ + } ELCPARC_b; + }; +} R_ELC_Type; /*!< Size = 284 (0x11c) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x40342000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40322000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */ + __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */ + __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */ + __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */ + __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */ + __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */ + __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */ + __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */ + __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */ + __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */ + __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */ + __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */ + __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */ + __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */ + __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */ + __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */ + __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */ + __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */ + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASOC : 1; /*!< [24..24] Other channel Source GTCCRA Input Capture Enable */ + uint32_t : 7; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSOC : 1; /*!< [24..24] Other channel Source GTCCRB Input Capture Enable */ + uint32_t : 7; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 3; + __IOM uint32_t AINV : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control */ + __IOM uint32_t BINV : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control */ + uint32_t : 2; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */ + __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */ + __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */ + __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */ + uint32_t : 2; + __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */ + __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */ + uint32_t : 3; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */ + uint32_t : 3; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection + * timing setting */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt + * Enable */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTPR Register Compare Match Interrupt Enable */ + __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous + * Clear Enable */ + __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source + * Synchronous Clear Enable */ + __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */ + __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */ + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion + * Start Request Enable */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D + * Conversion Start Request Enable */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended + * Skipping Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + + union + { + __IOM uint32_t GTADCMSC; /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Control Register */ + + struct + { + __IOM uint32_t ADCMSC1 : 2; /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter + * 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST1 : 4; /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1 + * Skipping Count Setting */ + __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping + * Counter 1 Initial Value */ + __IM uint32_t ADCMSCNT1 : 4; /*!< [15..12] A/D Conversion Start Request Compare Match Skipping + * Counter 1 */ + __IOM uint32_t ADCMSC2 : 2; /*!< [17..16] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Count Source Select */ + uint32_t : 2; + __IOM uint32_t ADCMST2 : 4; /*!< [23..20] A/D Conversion Start Request Compare Match Skipping + * 2 Skipping Count Setting */ + __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping + * Counter 2 Initial Value */ + __IM uint32_t ADCMSCNT2 : 4; /*!< [31..28] A/D Conversion Start Request Compare Match Skipping + * Counter 2 */ + } GTADCMSC_b; + }; + + union + { + __IOM uint32_t GTADCMSS; /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request + * Compare Match Skipping Setting Register */ + + struct + { + __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare + * Match Skipping Function Select */ + uint32_t : 9; + __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion + * Start Request Compare Match Skipping Function Select */ + uint32_t : 9; + } GTADCMSS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 4; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */ + uint32_t : 6; + } GTSECR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */ + + struct + { + __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */ + __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer + * Disable */ + uint32_t : 2; + __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer + * Enable */ + uint32_t : 1; + __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer + * Disable */ + __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer + * Transfer Disable */ + uint32_t : 2; + __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */ + __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */ + __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */ + __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */ + uint32_t : 2; + } GTBER2_b; + }; + + union + { + __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */ + + struct + { + __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */ + uint32_t : 11; + __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */ + uint32_t : 11; + } GTOLBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input + * Capture Control Register */ + + struct + { + __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other + * Channel GTCCRA Input Capture Source Enable */ + __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture + * Source Enable */ + __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */ + __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture + * to Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to + * Other Channel GTCCRb Input Capture Source Enable */ + __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to + * Other Channel GTCCRB Input Capture Source Enable */ + __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture + * Source Enable */ + __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input + * Capture Source Enable */ + __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input + * Capture Source Enable */ + uint32_t : 5; + __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */ + } GTICCR_b; + }; +} R_GPT0_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GTCLK (R_GPT_GTCLK) + */ + +typedef struct /*!< (@ 0x40323F10) R_GPT_GTCLK Structure */ +{ + union + { + __IOM uint32_t GTCLKCR; /*!< (@ 0x00000000) General PWM Timer Clock Control Register */ + + struct + { + __IOM uint32_t BPEN : 1; /*!< [0..0] Synchronization Circuit Bypass Enable */ + uint32_t : 31; + } GTCLKCR_b; + }; +} R_GPT_GTCLK_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x40324000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 2; /*!< [9..8] GPT core clock Frequency Range */ + uint16_t : 6; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; + __IM uint32_t RESERVED[15]; + + union + { + __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection + * Register */ + + struct + { + __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */ + uint16_t : 7; + __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */ + } GTONCWP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling + * Register */ + + struct + { + __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */ + uint16_t : 3; + __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */ + __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */ + uint16_t : 7; + } GTONCCR_b; + }; + __IM uint16_t RESERVED2; +} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCRa[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCRa_b[16]; + }; + + union + { + __IM uint8_t NMICR; /*!< (@ 0x00000010) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t IRQCRb[16]; /*!< (@ 0x00000014) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCRb_b[16]; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IOM uint32_t INTSELR[32]; /*!< (@ 0x00000040) Interrupt request select Register */ + + struct + { + __IOM uint32_t IS0 : 1; /*!< [0..0] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS16 : 1; /*!< [16..16] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS17 : 1; /*!< [17..17] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS18 : 1; /*!< [18..18] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS19 : 1; /*!< [19..19] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS20 : 1; /*!< [20..20] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS21 : 1; /*!< [21..21] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS22 : 1; /*!< [22..22] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS23 : 1; /*!< [23..23] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS24 : 1; /*!< [24..24] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS25 : 1; /*!< [25..25] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS26 : 1; /*!< [26..26] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS27 : 1; /*!< [27..27] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS28 : 1; /*!< [28..28] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS29 : 1; /*!< [29..29] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS30 : 1; /*!< [30..30] Selects which CPU receives interrupt requests */ + __IOM uint32_t IS31 : 1; /*!< [31..31] Selects which CPU receives interrupt requests */ + } INTSELR_b[32]; + }; + __IM uint32_t RESERVED3[6160]; + + union + { + __IOM uint32_t NMIER; /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint32_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint32_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint32_t PVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint32_t PVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t SOSTEN : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Enable */ + __IOM uint32_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint32_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t BUSEN : 1; /*!< [12..12] BUS error Interrupt Enable */ + __IOM uint32_t CMEN : 1; /*!< [13..13] Common Memory error Interrupt Enable */ + __IOM uint32_t LMEN : 1; /*!< [14..14] Local Memory Error Interrupt Enable */ + __IOM uint32_t LUEN : 1; /*!< [15..15] LockUp Interrupt Enable */ + __IOM uint32_t FPUFLTEN : 1; /*!< [16..16] FPU FAULT Interrupt Enable */ + __IOM uint32_t MRCRDEN : 1; /*!< [17..17] MRAM MRC read Error Interrupt Enable */ + __IOM uint32_t MRERDEN : 1; /*!< [18..18] MRAM MRE read Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t IPCEN : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Enable */ + uint32_t : 11; + } NMIER_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t NMICLR; /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __IOM uint32_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __IOM uint32_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __IOM uint32_t PVD1CLR : 1; /*!< [2..2] PVD1 Clear */ + __IOM uint32_t PVD2CLR : 1; /*!< [3..3] PVD2 Clear */ + uint32_t : 1; + __IOM uint32_t SOSTCLR : 1; /*!< [5..5] Sub OST Clear */ + __IOM uint32_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __IOM uint32_t NMICLR : 1; /*!< [7..7] NMI Clear */ + uint32_t : 4; + __IOM uint32_t BUSCLR : 1; /*!< [12..12] Bus Clear */ + __IOM uint32_t CMCLR : 1; /*!< [13..13] CM Clear */ + __IOM uint32_t LMCLR : 1; /*!< [14..14] LM Clear */ + __IOM uint32_t LUCLR : 1; /*!< [15..15] LU Clear */ + __IOM uint32_t FPUFLTCLR : 1; /*!< [16..16] FPU FAULT Clear */ + __IOM uint32_t MRCRDCLR : 1; /*!< [17..17] MRAM MRC read Error Interrupt Clear */ + __IOM uint32_t MRERDCLR : 1; /*!< [18..18] MRAM MRE read Error Interrupt Clear */ + uint32_t : 1; + __IOM uint32_t IPCCLR : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Clear */ + uint32_t : 11; + } NMICLR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IM uint32_t NMISR; /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint32_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint32_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint32_t PVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint32_t PVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t SOSTST : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + uint32_t : 4; + __IM uint32_t BUSST : 1; /*!< [12..12] BUS error Interrupt Status Flag */ + __IM uint32_t CMST : 1; /*!< [13..13] Common Memory error Interrupt Status Flag */ + __IM uint32_t LMST : 1; /*!< [14..14] Local Memory Error Interrupt Status Flag */ + __IM uint32_t LUST : 1; /*!< [15..15] LockUp Interrupt Status Flag */ + __IM uint32_t FPUFLTST : 1; /*!< [16..16] FPU FAULT Interrupt Status Flag */ + __IM uint32_t MRCRDST : 1; /*!< [17..17] MRAM MRC read Error Interrupt Status Flag */ + __IM uint32_t MRERDST : 1; /*!< [18..18] MRAM MRE read Error Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t IPCST : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Status Flag */ + uint32_t : 11; + } NMISR_b; + }; + __IM uint32_t RESERVED6[31]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable + * bit */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t WUPEN0 : 1; /*!< [16..16] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 0 */ + __IOM uint32_t WUPEN1 : 1; /*!< [17..17] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 1 */ + __IOM uint32_t WUPEN2 : 1; /*!< [18..18] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 2 */ + __IOM uint32_t WUPEN3 : 1; /*!< [19..19] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 3 */ + __IOM uint32_t WUPEN4 : 1; /*!< [20..20] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 4 */ + __IOM uint32_t WUPEN5 : 1; /*!< [21..21] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 5 */ + __IOM uint32_t WUPEN6 : 1; /*!< [22..22] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 6 */ + __IOM uint32_t WUPEN7 : 1; /*!< [23..23] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 7 */ + __IOM uint32_t WUPEN8 : 1; /*!< [24..24] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 8 */ + __IOM uint32_t WUPEN9 : 1; /*!< [25..25] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 9 */ + __IOM uint32_t WUPEN10 : 1; /*!< [26..26] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 10 */ + __IOM uint32_t WUPEN11 : 1; /*!< [27..27] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 11 */ + __IOM uint32_t WUPEN12 : 1; /*!< [28..28] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 12 */ + __IOM uint32_t WUPEN13 : 1; /*!< [29..29] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 13 */ + __IOM uint32_t WUPEN14 : 1; /*!< [30..30] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 14 */ + __IOM uint32_t WUPEN15 : 1; /*!< [31..31] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 15 */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t WUPEN16 : 1; /*!< [0..0] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 16 */ + __IOM uint32_t WUPEN17 : 1; /*!< [1..1] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 17 */ + __IOM uint32_t WUPEN18 : 1; /*!< [2..2] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 18 */ + __IOM uint32_t WUPEN19 : 1; /*!< [3..3] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 19 */ + __IOM uint32_t WUPEN20 : 1; /*!< [4..4] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 20 */ + __IOM uint32_t WUPEN21 : 1; /*!< [5..5] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 21 */ + __IOM uint32_t WUPEN22 : 1; /*!< [6..6] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 22 */ + __IOM uint32_t WUPEN23 : 1; /*!< [7..7] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 23 */ + __IOM uint32_t WUPEN24 : 1; /*!< [8..8] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 24 */ + __IOM uint32_t WUPEN25 : 1; /*!< [9..9] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 25 */ + __IOM uint32_t WUPEN26 : 1; /*!< [10..10] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 26 */ + __IOM uint32_t WUPEN27 : 1; /*!< [11..11] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 27 */ + __IOM uint32_t WUPEN28 : 1; /*!< [12..12] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 28 */ + __IOM uint32_t WUPEN29 : 1; /*!< [13..13] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 29 */ + __IOM uint32_t WUPEN30 : 1; /*!< [14..14] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 30 */ + __IOM uint32_t WUPEN31 : 1; /*!< [15..15] Peripheral Interrupt Deep Sleep/Software Standby Returns + * Enable bit 31 */ + __IOM uint32_t IRQWUPEN16 : 1; /*!< [16..16] IRQ16 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN17 : 1; /*!< [17..17] IRQ17 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN18 : 1; /*!< [18..18] IRQ18 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN19 : 1; /*!< [19..19] IRQ19 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN20 : 1; /*!< [20..20] IRQ20 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN21 : 1; /*!< [21..21] IRQ21 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN22 : 1; /*!< [22..22] IRQ22 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN23 : 1; /*!< [23..23] IRQ23 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN24 : 1; /*!< [24..24] IRQ24 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN25 : 1; /*!< [25..25] IRQ25 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN26 : 1; /*!< [26..26] IRQ26 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN27 : 1; /*!< [27..27] IRQ27 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN28 : 1; /*!< [28..28] IRQ28 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN29 : 1; /*!< [29..29] IRQ29 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN30 : 1; /*!< [30..30] IRQ30 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + __IOM uint32_t IRQWUPEN31 : 1; /*!< [31..31] IRQ31 Interrupt Deep Sleep/Software Standby Returns + * Enable bit */ + } WUPEN1_b; + }; + __IM uint32_t RESERVED7[26]; + + union + { + __IOM uint32_t DSLPWUPIRQEN[3]; /*!< (@ 0x00006210) Deep Sleep Wake Up IRQ Enable Register */ + + struct + { + __IOM uint32_t IRQ0 : 1; /*!< [0..0] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ1 : 1; /*!< [1..1] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ2 : 1; /*!< [2..2] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ3 : 1; /*!< [3..3] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ4 : 1; /*!< [4..4] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ5 : 1; /*!< [5..5] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ6 : 1; /*!< [6..6] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ7 : 1; /*!< [7..7] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ8 : 1; /*!< [8..8] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ9 : 1; /*!< [9..9] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ10 : 1; /*!< [10..10] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ11 : 1; /*!< [11..11] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ12 : 1; /*!< [12..12] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ13 : 1; /*!< [13..13] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ14 : 1; /*!< [14..14] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ15 : 1; /*!< [15..15] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ16 : 1; /*!< [16..16] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ17 : 1; /*!< [17..17] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ18 : 1; /*!< [18..18] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ19 : 1; /*!< [19..19] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ20 : 1; /*!< [20..20] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ21 : 1; /*!< [21..21] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ22 : 1; /*!< [22..22] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ23 : 1; /*!< [23..23] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ24 : 1; /*!< [24..24] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ25 : 1; /*!< [25..25] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ26 : 1; /*!< [26..26] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ27 : 1; /*!< [27..27] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ28 : 1; /*!< [28..28] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ29 : 1; /*!< [29..29] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ30 : 1; /*!< [30..30] IRQ Deep Sleep Returns Enable bit */ + __IOM uint32_t IRQ31 : 1; /*!< [31..31] IRQ Deep Sleep Returns Enable bit */ + } DSLPWUPIRQEN_b[3]; + }; + __IM uint32_t RESERVED8[25]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00006280) DMAC Event Link Setting Registers */ + + struct + { + __IOM uint32_t DELS : 10; /*!< [9..0] DMAC Event Link Select */ + uint32_t : 6; + __IOM uint32_t IR : 1; /*!< [16..16] DMAC Activation Request Status Flag */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED9[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 10; /*!< [9..0] ICU Event Link Select */ + uint32_t : 6; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 25728 (0x6480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4025E000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40202200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } IWDTCR_b; + }; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; + + union + { + __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } IWDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } IWDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_IWDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 2; + __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset */ + __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese */ + __IOM uint32_t HTDBRST : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset */ + __IOM uint32_t HRDBRST : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset */ + uint32_t : 3; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 3; /*!< [18..16] Slave Address Enable */ + uint32_t : 13; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[23]; + + union + { + __IOM uint32_t STCTL; /*!< (@ 0x00000120) Synchronous Timing Control Register */ + + struct + { + __IOM uint32_t STOE : 1; /*!< [0..0] Synchronous Timing output Enable */ + uint32_t : 31; + } STCTL_b; + }; + + union + { + __IOM uint32_t ATCTL; /*!< (@ 0x00000124) Asynchronous Timing Control Register */ + + struct + { + __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select */ + __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow) */ + __IOM uint32_t AMEOE : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable */ + uint32_t : 5; + __IOM uint32_t CDIV : 8; /*!< [15..8] TCLK Counter Divide Setting */ + uint32_t : 16; + } ATCTL_b; + }; + + union + { + __IOM uint32_t ATTRG; /*!< (@ 0x00000128) Asynchronous Timing Trigger Register */ + + struct + { + __OM uint32_t ATSTRG : 1; /*!< [0..0] Asynchronous Timing Software Trigger */ + uint32_t : 31; + } ATTRG_b; + }; + + union + { + __IOM uint32_t ATCCNTE; /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register */ + + struct + { + __IOM uint32_t ATCE : 1; /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1, + * SC2. */ + uint32_t : 31; + } ATCCNTE_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED13[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED14[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + + union + { + __OM uint32_t HCMDQP; /*!< (@ 0x00000184) High Priority Command Queue Port Register */ + + struct + { + __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port */ + } HCMDQP_b; + }; + + union + { + __IM uint32_t HRSPQP; /*!< (@ 0x00000188) High Priority Response Queue Port Register */ + + struct + { + __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port */ + } HRSPQP_b; + }; + + union + { + __IOM uint32_t HTDTBP; /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register */ + + struct + { + __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port */ + } HTDTBP_b; + }; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + + union + { + __IOM uint32_t HQTHCTL; /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold */ + uint32_t : 16; + } HQTHCTL_b; + }; + + union + { + __IOM uint32_t HTBTHCTL; /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold + * Control Register */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold */ + uint32_t : 5; + } HTBTHCTL_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 3; + __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag */ + uint32_t : 7; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable */ + uint32_t : 7; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable */ + uint32_t : 7; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 3; + __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force */ + uint32_t : 7; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint32_t HTST; /*!< (@ 0x00000200) High Priority Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag */ + __IOM uint32_t RDBFF : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag */ + uint32_t : 1; + __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] High Priority Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] High Priority Transfer Error Flag */ + uint32_t : 22; + } HTST_b; + }; + + union + { + __IOM uint32_t HTSTE; /*!< (@ 0x00000204) High Priority Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable */ + __IOM uint32_t RDBFE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] High Priority Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] High Priority Transfer Error Enable */ + uint32_t : 22; + } HTSTE_b; + }; + + union + { + __IOM uint32_t HTIE; /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable */ + __IOM uint32_t RDBFIE : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable */ + uint32_t : 22; + } HTIE_b; + }; + + union + { + __IOM uint32_t HTSTFC; /*!< (@ 0x0000020C) High Priority Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force */ + __OM uint32_t RDBFFC : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force */ + uint32_t : 1; + __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] High Priority Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] High Priority Transfer Error Force */ + uint32_t : 22; + } HTSTFC_b; + }; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 3; /*!< [18..16] Slave Address Detection Flag */ + uint32_t : 13; + } SVST_b; + }; + + union + { + __IM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Operating Status Register */ + + struct + { + __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + + union + { + __IM uint32_t MRCCPT; /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register */ + + struct + { + __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture */ + } MRCCPT_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IOM uint32_t DATBAS4; /*!< (@ 0x00000244) Device Address Table Basic Register 4 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS4_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IOM uint32_t DATBAS5; /*!< (@ 0x0000024C) Device Address Table Basic Register 5 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS5_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t DATBAS6; /*!< (@ 0x00000254) Device Address Table Basic Register 6 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS6_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IOM uint32_t DATBAS7; /*!< (@ 0x0000025C) Device Address Table Basic Register 7 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS7_b; + }; + __IM uint32_t RESERVED26[16]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED27[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED28[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + + union + { + __IOM uint32_t MSDCT4; /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT4_b; + }; + + union + { + __IOM uint32_t MSDCT5; /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT5_b; + }; + + union + { + __IOM uint32_t MSDCT6; /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT6_b; + }; + + union + { + __IOM uint32_t MSDCT7; /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t RBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t RBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT7_b; + }; + __IM uint32_t RESERVED29[12]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + __IOM uint32_t TBCR4 : 1; /*!< [12..12] Bridge Identifier */ + __IOM uint32_t TBCR5 : 1; /*!< [13..13] SDR Only / SDR and HDR Capable */ + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED30; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + + union + { + __IM uint32_t SVDVAD1; /*!< (@ 0x00000334) Slave Device Address Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD1_b; + }; + + union + { + __IM uint32_t SVDVAD2; /*!< (@ 0x00000338) Slave Device Address Register 2 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD2_b; + }; + __IM uint32_t RESERVED31[5]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + __IOM uint32_t SPTSYN : 1; /*!< [0..0] Supports Sync Mode */ + __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0 */ + __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1 */ + uint32_t : 5; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + + union + { + __IOM uint32_t CETSS; /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State) + * Register */ + + struct + { + __IOM uint32_t SYNE : 1; /*!< [0..0] Sync Mode Enabled */ + __IOM uint32_t ASYNE : 2; /*!< [2..1] Async Mode Enabled */ + uint32_t : 4; + __IOM uint32_t ICOVF : 1; /*!< [7..7] Internal Counter Overflow */ + uint32_t : 24; + } CETSS_b; + }; + + union + { + __IOM uint32_t CGHDRCAP; /*!< (@ 0x0000037C) CCC Get HDR Capability Register */ + + struct + { + __IOM uint32_t DDREN : 1; /*!< [0..0] HDR-DDR Operation Enable */ + __IOM uint32_t TSPEN : 1; /*!< [1..1] HDR-TSP Operation Enable */ + __IOM uint32_t TSLEN : 1; /*!< [2..2] HDR-TSL Operation Enable */ + uint32_t : 29; + } CGHDRCAP_b; + }; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED32[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0 */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED33[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + + union + { + __IM uint32_t HQSTLV; /*!< (@ 0x000003C4) High Priority Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQLV : 8; /*!< [7..0] High Priority Command Queue Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] High Priority Response Queue Level */ + uint32_t : 16; + } HQSTLV_b; + }; + + union + { + __IM uint32_t HDBSTLV; /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] High Priority Tx Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] High Priority Rx Data Buffer Level */ + uint32_t : 16; + } HDBSTLV_b; + }; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; + __IM uint32_t RESERVED34[3]; + + union + { + __IM uint32_t SC1CPT; /*!< (@ 0x000003E0) SC1 Capture monitor Register */ + + struct + { + __IM uint32_t SC1C : 16; /*!< [15..0] SC1 Capture */ + uint32_t : 16; + } SC1CPT_b; + }; + + union + { + __IM uint32_t SC2CPT; /*!< (@ 0x000003E4) SC2 Capture monitor Register */ + + struct + { + __IM uint32_t SC2C : 16; /*!< [15..0] SC2 Capture */ + uint32_t : 16; + } SC2CPT_b; + }; +} R_I3C0_Type; /*!< Size = 1000 (0x3e8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OADPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[62]; + __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */ + __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40203000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRD_b; + }; + + union + { + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */ + __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */ + __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */ + __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */ + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */ + __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */ + __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */ + __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */ + __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */ + __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */ + __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for + * usage. */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for + * usage. */ + } MSTPCRE_b; + }; + + union + { + __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */ + + struct + { + __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */ + __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */ + __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */ + uint16_t : 4; + __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */ + __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */ + } LSMRWDIS_b; + }; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40400000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000002) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + + union + { + __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40400800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40400D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[3]; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[13]; + __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40202000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz Flag */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz Flag */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz Flag */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz Flag */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz Flag */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz Flag */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz Flag */ + __IM uint8_t R64OVF : 1; /*!< [7..7] This bit indicates the overflow of F1HZ only when using + * time error adjustment function inlow-consumption clock + * mode. */ + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + }; + + union + { + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t RADJ2; /*!< (@ 0x00000030) Time Error Adjustment Register 2 */ + + struct + { + uint16_t : 5; + __IOM uint16_t FADJ : 11; /*!< [15..5] Fractional Adjust Value */ + } RADJ2_b; + }; + __IM uint16_t RESERVED20[7]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_MANC; /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF + * = 0, and MMR.MANEN = 1) */ + + struct + { + __IOM uint8_t MER : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_MANC_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + union + { + __IOM uint16_t TDRHL_MAN; /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IOM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint16_t MPBT : 1; /*!< [9..9] Multi-processor Transfer Bit Flag */ + uint16_t : 2; + __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit */ + uint16_t : 3; + } TDRHL_MAN_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + union + { + __IM uint16_t RDRHL_MAN; /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN + * = 1) */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial Receive Data */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor Bit */ + uint16_t : 2; + __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit */ + uint16_t : 3; + } RDRHL_MAN_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t MMR; /*!< (@ 0x00000020) Manchester Mode Register */ + + struct + { + __IOM uint8_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint8_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint8_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint8_t : 1; + __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting */ + __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint8_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + __IOM uint8_t MANEN : 1; /*!< [7..7] Manchester Mode Enable */ + } MMR_b; + }; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t TMPR; /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length */ + __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern */ + uint8_t : 2; + } TMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t RMPR; /*!< (@ 0x00000023) Receive Manchester Preface Setting Register */ + + struct + { + __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length */ + __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern */ + uint8_t : 2; + } RMPR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t MESR; /*!< (@ 0x00000024) Manchester Extended Error Status Register */ + + struct + { + __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag */ + __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag */ + uint8_t : 5; + } MESR_b; + }; + }; + + union + { + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t MECR; /*!< (@ 0x00000025) Manchester Extended Error Control Register */ + + struct + { + __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag */ + __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable */ + __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable */ + uint8_t : 5; + } MECR_b; + }; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ + __IM uint16_t RESERVED1[4]; + + union + { + __IOM uint8_t SCIMSKEN; /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register */ + + struct + { + __IOM uint8_t MSKEN : 1; /*!< [0..0] SCI5 TXD Output Mask Enable */ + uint8_t : 7; + } SCIMSKEN_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_SCI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40252000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint16_t SRAMPRCR; /*!< (@ 0x00000000) SRAM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t SRAMPRCR_NS; /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } SRAMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) SRAM Wait State Control Register */ + + struct + { + __IOM uint8_t WTEN : 1; /*!< [0..0] SRAM wait enable */ + uint8_t : 7; + } SRAMWTSC_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4; + + union + { + __IOM uint8_t SRAMCR0; /*!< (@ 0x00000010) SRAM Control Register 0 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR0_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRAMCR1; /*!< (@ 0x00000014) SRAM Control Register 1 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR1_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t SRAMCR2; /*!< (@ 0x00000018) SRAM Control Register 2 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR2_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t SRAMCR3; /*!< (@ 0x0000001C) SRAM Control Register 3 */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-bit Error Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } SRAMCR3_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[4]; + + union + { + __IOM uint8_t SRAMECCRGN0; /*!< (@ 0x00000030) SRAM ECC Region Control Register 0 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN0_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; + + union + { + __IOM uint8_t SRAMECCRGN1; /*!< (@ 0x00000034) SRAM ECC Region Control Register 1 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN1_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t SRAMECCRGN2; /*!< (@ 0x00000038) SRAM ECC Region Control Register 2 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN2_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t SRAMECCRGN3; /*!< (@ 0x0000003C) SRAM ECC Region Control Register 3 */ + + struct + { + __IOM uint8_t ECCRGN : 3; /*!< [2..0] ECC target Region select */ + uint8_t : 5; + } SRAMECCRGN3_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IM uint16_t SRAMESR; /*!< (@ 0x00000040) SRAM Error Status Register For ECC RAM */ + + struct + { + __IM uint16_t ERR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status */ + __IM uint16_t ERR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status */ + __IM uint16_t ERR10 : 1; /*!< [2..2] SRAM1 1-bit ECC Error Status */ + __IM uint16_t ERR11 : 1; /*!< [3..3] SRAM1 2-bit ECC Error Status */ + __IM uint16_t ERR20 : 1; /*!< [4..4] SRAM2 1-bit ECC Error Status */ + __IM uint16_t ERR21 : 1; /*!< [5..5] SRAM2 2-bit ECC Error Status */ + __IM uint16_t ERR30 : 1; /*!< [6..6] SRAM3 1-bit ECC Error Status */ + __IM uint16_t ERR31 : 1; /*!< [7..7] SRAM3 2-bit ECC Error Status */ + uint16_t : 8; + } SRAMESR_b; + }; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23; + + union + { + __OM uint16_t SRAMESCLR; /*!< (@ 0x00000048) SRAM Error Status Clear Register For ECC RAM */ + + struct + { + __OM uint16_t CLR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status Clear */ + __OM uint16_t CLR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status Clear */ + __OM uint16_t CLR10 : 1; /*!< [2..2] SRAM1 1-bit ECC Error Status Clear */ + __OM uint16_t CLR11 : 1; /*!< [3..3] SRAM1 2-bit ECC Error Status Clear */ + __OM uint16_t CLR20 : 1; /*!< [4..4] SRAM2 1-bit ECC Error Status Clear */ + __OM uint16_t CLR21 : 1; /*!< [5..5] SRAM2 2-bit ECC Error Status Clear */ + __OM uint16_t CLR30 : 1; /*!< [6..6] SRAM3 1-bit ECC Error Status Clear */ + __OM uint16_t CLR31 : 1; /*!< [7..7] SRAM3 2-bit ECC Error Status Clear */ + uint16_t : 8; + } SRAMESCLR_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25; + + union + { + __IM uint32_t SRAMEAR00; /*!< (@ 0x00000050) SRAM Error Address Register 00 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR00_b; + }; + + union + { + __IM uint32_t SRAMEAR01; /*!< (@ 0x00000054) SRAM Error Address Register 01 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR01_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IM uint32_t SRAMEAR10; /*!< (@ 0x00000060) SRAM Error Address Register 10 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR10_b; + }; + + union + { + __IM uint32_t SRAMEAR11; /*!< (@ 0x00000064) SRAM Error Address Register 11 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR11_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IM uint32_t SRAMEAR20; /*!< (@ 0x00000070) SRAM Error Address Register 20 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR20_b; + }; + + union + { + __IM uint32_t SRAMEAR21; /*!< (@ 0x00000074) SRAM Error Address Register 21 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR21_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IM uint32_t SRAMEAR30; /*!< (@ 0x00000080) SRAM Error Address Register 30 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR30_b; + }; + + union + { + __IM uint32_t SRAMEAR31; /*!< (@ 0x00000084) SRAM Error Address Register 31 */ + + struct + { + __IM uint32_t SRAMEAR : 32; /*!< [31..0] When an SRAM error occurs, it stores an error address */ + } SRAMEAR31_b; + }; +} R_SRAM_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4025D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint8_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t OPE : 1; /*!< [6..6] Output Port Enable */ + uint8_t : 1; + } SBYCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t SSCR2; /*!< (@ 0x0000000E) Software Standby Control Register 2 */ + + struct + { + __IOM uint8_t SS2FSR : 1; /*!< [0..0] Software Standby 2 Fast Return */ + uint8_t : 7; + } SSCR2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IM uint8_t MRSCR; /*!< (@ 0x00000010) MRAM Standby Control Register */ + + struct + { + __IM uint8_t MRSWCF : 1; /*!< [0..0] MRAM Stabilization wait completion flag */ + uint8_t : 7; + } MRSCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t VSCR; /*!< (@ 0x00000014) Voltage Scaling Control Register */ + + struct + { + __IOM uint8_t VSCM : 3; /*!< [2..0] Voltage Scaling Control Mode */ + uint8_t : 1; + __IOM uint8_t VSCMTSF : 1; /*!< [4..4] Voltage Scaling Control Mode Transition Status Flag */ + uint8_t : 3; + } VSCR_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + + union + { + __IOM uint8_t SRMONR; /*!< (@ 0x00000018) SRAM Monitor Register */ + + struct + { + __IOM uint8_t MON : 2; /*!< [1..0] SRAM Voltage Monitor */ + uint8_t : 6; + } SRMONR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 4; /*!< [3..0] Peripheral Module Clock D (PCLKD) Select */ + __IOM uint32_t PCKC : 4; /*!< [7..4] Peripheral Module Clock C (PCLKC) Select */ + __IOM uint32_t PCKB : 4; /*!< [11..8] Peripheral Module Clock B (PCLKB) Select */ + __IOM uint32_t PCKA : 4; /*!< [15..12] Peripheral Module Clock A (PCLKA) Select */ + __IOM uint32_t BCK : 4; /*!< [19..16] External Bus Clock (BCLK) Select */ + __IOM uint32_t PCKE : 4; /*!< [23..20] Peripheral Module Clock E (PCLKE) Select */ + __IOM uint32_t ICK : 4; /*!< [27..24] System Clock (ICLK) Select */ + __IOM uint32_t FCK : 4; /*!< [31..28] MRAM Clock (MRPCLK) Select */ + } SCKDIVCR_b; + }; + + union + { + __IOM uint16_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + __IOM uint16_t CPUCK : 4; /*!< [3..0] CPU0 Clock (CPUCLK0) Select */ + __IOM uint16_t CPUCK1 : 4; /*!< [7..4] CPU1 Clock (CPUCLK1) Select */ + __IOM uint16_t NPUCK : 4; /*!< [11..8] NPU Clock (NPUCLK) Select */ + __IOM uint16_t MRICK : 4; /*!< [15..12] MRAM bus Clock (MRICLK) Select */ + } SCKDIVCR2_b; + }; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL1 Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL1 Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + __IM uint8_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 6; + __IOM uint8_t EBCKASEL : 1; /*!< [7..7] External Bus Asynchronous Select */ + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock Out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock Control Register */ + uint8_t : 2; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IM uint8_t OSCMONR; /*!< (@ 0x00000043) Oscillator Monitor Register */ + + struct + { + uint8_t : 1; + __IM uint8_t MOCOMON : 1; /*!< [1..1] MOCO operation monitor */ + __IM uint8_t LOCOMON : 1; /*!< [2..2] LOCO operation monitor */ + uint8_t : 5; + } OSCMONR_b; + }; + __IM uint32_t RESERVED19; + __IM uint16_t RESERVED20; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED21; + + union + { + union + { + __IOM uint16_t PLLCCR2; /*!< (@ 0x0000004C) PLL1 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLLCCR2_b; + }; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + }; + + union + { + __IOM uint16_t PLL2CCR2; /*!< (@ 0x0000004E) PLL2 Clock Control Register 2 */ + + struct + { + __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output + * clock P */ + __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output + * clock Q */ + __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output + * clock R */ + uint16_t : 4; + } PLL2CCR2_b; + }; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED22; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] EBCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + + union + { + __IOM uint8_t SCICKDIVCR; /*!< (@ 0x00000054) SCI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] SCI clock (SCICLK) Division Select */ + uint8_t : 4; + } SCICKDIVCR_b; + }; + + union + { + __IOM uint8_t SCICKCR; /*!< (@ 0x00000055) SCI clock control register */ + + struct + { + __IOM uint8_t SCICKSEL : 4; /*!< [3..0] SCI clock (SCICLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] SCI clock (SCICLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] SCI clock (SCICLK) Switching Ready state flag */ + } SCICKCR_b; + }; + + union + { + __IOM uint8_t SPICKDIVCR; /*!< (@ 0x00000056) SPI clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] SPI clock (SPICLK) Division Select */ + uint8_t : 4; + } SPICKDIVCR_b; + }; + + union + { + __IOM uint8_t SPICKCR; /*!< (@ 0x00000057) SPI clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] SPI clock (SPICLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] SPI clock (SPICLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] SPI clock (SPICLK) Switching Ready state flag */ + } SPICKCR_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADCCKDIVCR; /*!< (@ 0x0000005A) ADC clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ADCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ADCCKCR; /*!< (@ 0x0000005B) ADC clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ADCCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000005C) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 4; /*!< [3..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 4; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x0000005D) GPT clock control register */ + + struct + { + __IOM uint8_t GPTCKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t LCDCKDIVCR; /*!< (@ 0x0000005E) LCD clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] LCD clock (LCDCLK) Division Select */ + uint8_t : 4; + } LCDCKDIVCR_b; + }; + + union + { + __IOM uint8_t LCDCKCR; /*!< (@ 0x0000005F) LCD clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] LCD clock (LCDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] LCD clock (LCDCLK) Switching Request */ + __IM uint8_t CKSRDY : 1; /*!< [7..7] LCD clock (LCDCLK) Switching Ready state flag */ + } LCDCKCR_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED25; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 4; /*!< [3..0] USB Clock (USBCLK) Division Select */ + uint8_t : 4; + } USBCKDIVCR_b; + }; + + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 4; /*!< [3..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 4; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 4; /*!< [3..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 4; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 4; /*!< [3..0] USB clock (USB60CLK) Division Select */ + uint8_t : 4; + } USB60CKDIVCR_b; + }; + + union + { + __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000070) I3C Clock Division control register */ + + struct + { + __IOM uint8_t I3CCKDIV : 4; /*!< [3..0] I3C clock (I3CCLK) Division Select */ + uint8_t : 4; + } I3CCKDIVCR_b; + }; + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 4; /*!< [3..0] USB Clock (USBCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 4; /*!< [3..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 2; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 4; /*!< [3..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 2; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000078) I3C Clock Control Register */ + + struct + { + __IOM uint8_t I3CCKSEL : 4; /*!< [3..0] I3C clock (I3CCLK) source select */ + uint8_t : 2; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t MOSCSCR; /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register */ + + struct + { + __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select */ + uint8_t : 7; + } MOSCSCR_b; + }; + + union + { + __IOM uint8_t HOCOSCR; /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t HOSCSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select */ + uint8_t : 7; + } HOCOSCR_b; + }; + __IM uint16_t RESERVED31; + __IM uint32_t RESERVED32; + + union + { + __IOM uint8_t MOCOSCR; /*!< (@ 0x00000084) Middle-Speed On-Chip Oscillator Standby Control + * Register */ + + struct + { + __IOM uint8_t MOCOSOKP : 1; /*!< [0..0] MOCO Standby Oscillation Keep select */ + uint8_t : 7; + } MOCOSCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[5]; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED37; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED38[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED39[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED40; + + union + { + __IOM uint32_t PLLCCR; /*!< (@ 0x000000AC) PLL1 Clock Control Register */ + + struct + { + __IOM uint32_t PLIDIV : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select */ + uint32_t : 1; + __IOM uint32_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select */ + __IOM uint32_t PLLMUL : 9; /*!< [16..8] PLL1 Frequency Multiplication Factor Select */ + uint32_t : 15; + } PLLCCR_b; + }; + __IM uint32_t RESERVED41[4]; + + union + { + __IOM uint32_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag */ + __IOM uint32_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect Flag */ + __IOM uint32_t SWRF : 1; /*!< [2..2] Software Reset Detect Flag */ + uint32_t : 1; + __IOM uint32_t CLURF : 1; /*!< [4..4] CPU0 Lockup Reset Detect flags */ + __IOM uint32_t LM0RF : 1; /*!< [5..5] Local memory 0 error Reset Detect Flag */ + uint32_t : 4; + __IOM uint32_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect Flag */ + uint32_t : 3; + __IOM uint32_t CMRF : 1; /*!< [14..14] Common memory error Reset Detect Flag */ + uint32_t : 2; + __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag */ + uint32_t : 2; + __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag */ + __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag */ + __IOM uint32_t NWRF : 1; /*!< [22..22] Network Reset Detect Flag */ + uint32_t : 9; + } RSTSR1_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t PLL2CCR; /*!< (@ 0x000000C8) PLL2 Clock Control Register */ + + struct + { + __IOM uint32_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint32_t : 1; + __IOM uint32_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select */ + __IOM uint32_t PLL2MUL : 9; /*!< [16..8] PLL2 Frequency Multiplication Factor Select */ + uint32_t : 15; + } PLL2CCR_b; + }; + + union + { + __IM uint8_t SYRACCR; /*!< (@ 0x000000CC) System Register Access Control Register */ + + struct + { + __IM uint8_t BUSY : 1; /*!< [0..0] Access Ready Monitor */ + uint8_t : 7; + } SYRACCR_b; + }; + __IM uint8_t RESERVED43; + __IM uint16_t RESERVED44; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED45; + + union + { + __IOM uint8_t BCKADIVCR; /*!< (@ 0x000000D4) Asynchronous external Bus clock Division control + * register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } BCKADIVCR_b; + }; + + union + { + __IOM uint8_t ESWCKDIVCR; /*!< (@ 0x000000D5) EtherSW clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESWCKDIVCR_b; + }; + + union + { + __IOM uint8_t ESWPCKDIVCR; /*!< (@ 0x000000D6) EtherSW-PHY clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESWPCKDIVCR_b; + }; + + union + { + __IOM uint8_t ESCCKDIVCR; /*!< (@ 0x000000D7) EtherCAT clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ESCCKDIVCR_b; + }; + + union + { + __IOM uint8_t ETHPCKDIVCR; /*!< (@ 0x000000D8) Ether-PHY clock Division control register */ + + struct + { + __IOM uint8_t CKDIV : 4; /*!< [3..0] Clock Division Select */ + uint8_t : 4; + } ETHPCKDIVCR_b; + }; + __IM uint8_t RESERVED46; + + union + { + __IOM uint8_t BCKACR; /*!< (@ 0x000000DA) Asynchronous external bus clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } BCKACR_b; + }; + + union + { + __IOM uint8_t ESWCKCR; /*!< (@ 0x000000DB) EtherSW clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESWCKCR_b; + }; + + union + { + __IOM uint8_t ESWPCKCR; /*!< (@ 0x000000DC) EtherSW-PHY clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESWPCKCR_b; + }; + + union + { + __IOM uint8_t ESCCKCR; /*!< (@ 0x000000DD) EtherCAT clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ESCCKCR_b; + }; + + union + { + __IOM uint8_t ETHPCKCR; /*!< (@ 0x000000DE) Ether-PHY clock control register */ + + struct + { + __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */ + uint8_t : 2; + __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */ + __IOM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */ + } ETHPCKCR_b; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + + union + { + __IOM uint8_t LVD3CR1; /*!< (@ 0x000000E4) Voltage Monitor 3 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD3CR1_b; + }; + + union + { + __IOM uint8_t LVD3SR; /*!< (@ 0x000000E5) Voltage Monitor 3 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD3SR_b; + }; + + union + { + __IOM uint8_t LVD4CR1; /*!< (@ 0x000000E6) Voltage Monitor 4 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD4CR1_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t LVD5CR1; /*!< (@ 0x000000E8) Voltage Monitor 5 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD5CR1_b; + }; + __IM uint8_t RESERVED49; + __IM uint16_t RESERVED50; + __IM uint32_t RESERVED51; + + union + { + __IOM uint8_t CRVSYSCR; /*!< (@ 0x000000F0) Clock Recovery System Control Register */ + + struct + { + __IOM uint8_t CRVEN : 1; /*!< [0..0] Clock Recovery Enable */ + uint8_t : 7; + } CRVSYSCR_b; + }; + __IM uint8_t RESERVED52; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; + + union + { + __IOM uint8_t CPUDSCR; /*!< (@ 0x00000100) CPU Deep Sleep Control Register */ + + struct + { + __IOM uint8_t PGD0 : 1; /*!< [0..0] Power Gating Disable for CPU0 */ + __IOM uint8_t PGD1 : 1; /*!< [1..1] Power Gating Disable for CPU1 */ + uint8_t : 6; + } CPUDSCR_b; + }; + __IM uint8_t RESERVED55; + __IM uint16_t RESERVED56; + __IM uint32_t RESERVED57[3]; + + union + { + __IOM uint8_t PDCTRGD; /*!< (@ 0x00000110) General Power Domain GD Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRGD_b; + }; + __IM uint8_t RESERVED58; + __IM uint16_t RESERVED59; + + union + { + __IOM uint8_t PDCTRNPU; /*!< (@ 0x00000114) General Power Domain NPU Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRNPU_b; + }; + __IM uint8_t RESERVED60; + __IM uint16_t RESERVED61; + + union + { + __IOM uint8_t PDCTRESWM; /*!< (@ 0x00000118) General Power Domain ESWM Control Register */ + + struct + { + __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */ + uint8_t : 5; + __IOM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */ + __IOM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */ + } PDCTRESWM_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[9]; + + union + { + __IOM uint16_t PDRAMSCR0; /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0 */ + + struct + { + __IOM uint16_t RKEEP0 : 1; /*!< [0..0] RAM Retention bit 0 */ + __IOM uint16_t RKEEP1 : 1; /*!< [1..1] RAM Retention bit 1 */ + __IOM uint16_t RKEEP2 : 1; /*!< [2..2] RAM Retention bit 2 */ + __IOM uint16_t RKEEP3 : 1; /*!< [3..3] RAM Retention bit 3 */ + __IOM uint16_t RKEEP4 : 1; /*!< [4..4] RAM Retention bit 4 */ + __IOM uint16_t RKEEP5 : 1; /*!< [5..5] RAM Retention bit 5 */ + __IOM uint16_t RKEEP6 : 1; /*!< [6..6] RAM Retention bit 6 */ + __IOM uint16_t RKEEP7 : 1; /*!< [7..7] RAM Retention bit 7 */ + __IOM uint16_t RKEEP8 : 1; /*!< [8..8] RAM Retention bit 8 */ + __IOM uint16_t RKEEP9 : 1; /*!< [9..9] RAM Retention bit 9 */ + __IOM uint16_t RKEEP10 : 1; /*!< [10..10] RAM Retention bit 10 */ + __IOM uint16_t RKEEP11 : 1; /*!< [11..11] RAM Retention bit 11 */ + __IOM uint16_t RKEEP12 : 1; /*!< [12..12] RAM Retention bit 12 */ + __IOM uint16_t RKEEP13 : 1; /*!< [13..13] RAM Retention bit 13 */ + __IOM uint16_t RKEEP14 : 1; /*!< [14..14] RAM Retention bit 14 */ + __IOM uint16_t RKEEP15 : 1; /*!< [15..15] RAM Retention bit 15 */ + } PDRAMSCR0_b; + }; + + union + { + __IOM uint8_t PDRAMSCR1; /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1 */ + + struct + { + __IOM uint8_t RKEEP0 : 1; /*!< [0..0] RAM Retention bit 0 */ + __IOM uint8_t RKEEP1 : 1; /*!< [1..1] RAM Retention bit 1 */ + __IOM uint8_t RKEEP2 : 1; /*!< [2..2] RAM Retention bit 2 */ + __IOM uint8_t RKEEP3 : 1; /*!< [3..3] RAM Retention bit 3 */ + __IOM uint8_t RKEEP4 : 1; /*!< [4..4] RAM Retention bit 4 */ + __IOM uint8_t RKEEP5 : 1; /*!< [5..5] RAM Retention bit 5 */ + __IOM uint8_t RKEEP6 : 1; /*!< [6..6] RAM Retention bit 6 */ + __IOM uint8_t RKEEP7 : 1; /*!< [7..7] RAM Retention bit 7 */ + } PDRAMSCR1_b; + }; + __IM uint8_t RESERVED65; + __IM uint32_t RESERVED66[155]; + + union + { + __IOM uint16_t VBRSABAR; /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary + * Address Register */ + + struct + { + __IOM uint16_t SABA : 16; /*!< [15..0] Security Attribute Boundary Address */ + } VBRSABAR_b; + }; + __IM uint16_t RESERVED67; + + union + { + __IOM uint16_t VBRPABARS; /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Secure Region */ + + struct + { + __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region */ + } VBRPABARS_b; + }; + __IM uint16_t RESERVED68; + + union + { + __IOM uint16_t VBRPABARNS; /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary + * Address Register for Non-secure Region */ + + struct + { + __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure + * Region */ + } VBRPABARNS_b; + }; + __IM uint16_t RESERVED69; + __IM uint32_t RESERVED70; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC01 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } CGFSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003C4) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 27; + } RSTSAR_b; + }; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non Secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non Secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non Secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non Secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non Secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non Secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non Secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non Secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non Secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non Secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non Secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non Secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non Secure Attribute bit 31 */ + } LPMSAR_b; + }; + + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + uint32_t : 23; + } BBFSAR_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t PGCSAR; /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */ + __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */ + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */ + __IOM uint32_t NONSEC5 : 1; /*!< [5..5] Non-secure Attribute bit 5 */ + __IOM uint32_t NONSEC6 : 1; /*!< [6..6] Non-secure Attribute bit 6 */ + __IOM uint32_t NONSEC7 : 1; /*!< [7..7] Non-secure Attribute bit 7 */ + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non-secure Attribute bit 9 */ + __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non-secure Attribute bit 10 */ + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12 */ + __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13 */ + __IOM uint32_t NONSEC14 : 1; /*!< [14..14] Non-secure Attribute bit 14 */ + __IOM uint32_t NONSEC15 : 1; /*!< [15..15] Non-secure Attribute bit 15 */ + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non-secure Attribute bit 23 */ + __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24 */ + __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25 */ + __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26 */ + __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non-secure Attribute bit 27 */ + __IOM uint32_t NONSEC28 : 1; /*!< [28..28] Non-secure Attribute bit 28 */ + __IOM uint32_t NONSEC29 : 1; /*!< [29..29] Non-secure Attribute bit 29 */ + __IOM uint32_t NONSEC30 : 1; /*!< [30..30] Non-secure Attribute bit 30 */ + __IOM uint32_t NONSEC31 : 1; /*!< [31..31] Non-secure Attribute bit 31 */ + } PGCSAR_b; + }; + __IM uint32_t RESERVED72; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + __IOM uint32_t DPFSA21 : 1; /*!< [21..21] Deep Standby Interrupt Factor Security Attribute bit + * 21 */ + __IOM uint32_t DPFSA22 : 1; /*!< [22..22] Deep Standby Interrupt Factor Security Attribute bit + * 22 */ + __IOM uint32_t DPFSA23 : 1; /*!< [23..23] Deep Standby Interrupt Factor Security Attribute bit + * 23 */ + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + __IOM uint32_t DPFSA28 : 1; /*!< [28..28] Deep Standby Interrupt Factor Security Attribute bit + * 28 */ + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + __IOM uint32_t DPFSA30 : 1; /*!< [30..30] Deep Standby Interrupt Factor Security Attribute bit + * 30 */ + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR_b; + }; + + union + { + __IOM uint32_t RSCSAR; /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register */ + + struct + { + __IOM uint32_t RSCSA0 : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 0 */ + __IOM uint32_t RSCSA1 : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 1 */ + __IOM uint32_t RSCSA2 : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 2 */ + __IOM uint32_t RSCSA3 : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 3 */ + __IOM uint32_t RSCSA4 : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 4 */ + __IOM uint32_t RSCSA5 : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 5 */ + __IOM uint32_t RSCSA6 : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 6 */ + __IOM uint32_t RSCSA7 : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 7 */ + __IOM uint32_t RSCSA8 : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 8 */ + __IOM uint32_t RSCSA9 : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 9 */ + __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10 */ + __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11 */ + __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12 */ + __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13 */ + __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14 */ + __IOM uint32_t RSCSA15 : 1; /*!< [15..15] RAM Standby Control Security Attribute bit 15 */ + __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16 */ + __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17 */ + __IOM uint32_t RSCSA18 : 1; /*!< [18..18] RAM Standby Control Security Attribute bit 18 */ + __IOM uint32_t RSCSA19 : 1; /*!< [19..19] RAM Standby Control Security Attribute bit 19 */ + __IOM uint32_t RSCSA20 : 1; /*!< [20..20] RAM Standby Control Security Attribute bit 20 */ + __IOM uint32_t RSCSA21 : 1; /*!< [21..21] RAM Standby Control Security Attribute bit 21 */ + __IOM uint32_t RSCSA22 : 1; /*!< [22..22] RAM Standby Control Security Attribute bit 22 */ + __IOM uint32_t RSCSA23 : 1; /*!< [23..23] RAM Standby Control Security Attribute bit 23 */ + __IOM uint32_t RSCSA24 : 1; /*!< [24..24] RAM Standby Control Security Attribute bit 24 */ + __IOM uint32_t RSCSA25 : 1; /*!< [25..25] RAM Standby Control Security Attribute bit 25 */ + __IOM uint32_t RSCSA26 : 1; /*!< [26..26] RAM Standby Control Security Attribute bit 26 */ + __IOM uint32_t RSCSA27 : 1; /*!< [27..27] RAM Standby Control Security Attribute bit 27 */ + __IOM uint32_t RSCSA28 : 1; /*!< [28..28] RAM Standby Control Security Attribute bit 28 */ + __IOM uint32_t RSCSA29 : 1; /*!< [29..29] RAM Standby Control Security Attribute bit 29 */ + __IOM uint32_t RSCSA30 : 1; /*!< [30..30] RAM Standby Control Security Attribute bit 30 */ + __IOM uint32_t RSCSA31 : 1; /*!< [31..31] RAM Standby Control Security Attribute bit 31 */ + } RSCSAR_b; + }; + + union + { + __IOM uint32_t DPFSAR1; /*!< (@ 0x000003E8) Deep Standby Interrupt Factor Security Attribution + * Register 1 */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + __IOM uint32_t DPFSA21 : 1; /*!< [21..21] Deep Standby Interrupt Factor Security Attribute bit + * 21 */ + __IOM uint32_t DPFSA22 : 1; /*!< [22..22] Deep Standby Interrupt Factor Security Attribute bit + * 22 */ + __IOM uint32_t DPFSA23 : 1; /*!< [23..23] Deep Standby Interrupt Factor Security Attribute bit + * 23 */ + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit + * 25 */ + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + __IOM uint32_t DPFSA28 : 1; /*!< [28..28] Deep Standby Interrupt Factor Security Attribute bit + * 28 */ + __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit + * 29 */ + __IOM uint32_t DPFSA30 : 1; /*!< [30..30] Deep Standby Interrupt Factor Security Attribute bit + * 30 */ + __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit + * 31 */ + } DPFSAR1_b; + }; + __IM uint32_t RESERVED73[3]; + __IM uint16_t RESERVED74; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FA) Protect Register for Secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the security + * and privilege setting registers. */ + __IOM uint16_t PRC5 : 1; /*!< [5..5] Enables writing to the registers related the reset control. */ + uint16_t : 2; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_b; + }; + __IM uint16_t RESERVED75; + + union + { + __IOM uint16_t PRCR_NS; /*!< (@ 0x000003FE) Protect Register for Non-secure Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power modes, and the battery backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the privilege + * setting registers. */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + } PRCR_NS_b; + }; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED76; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000402) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED77; + __IM uint32_t RESERVED78[2]; + __IM uint16_t RESERVED79; + __IM uint8_t RESERVED80; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + __IM uint32_t RESERVED81; + __IM uint16_t RESERVED82; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + __IM uint8_t RESERVED83; + __IM uint32_t RESERVED84; + __IM uint16_t RESERVED85; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED86[8]; + + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED87; + __IM uint32_t RESERVED88[15]; + __IM uint16_t RESERVED89; + + union + { + __IOM uint8_t SOMRG; /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register */ + + struct + { + __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching */ + uint8_t : 6; + } SOMRG_b; + }; + __IM uint8_t RESERVED90; + __IM uint32_t RESERVED91[11]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED92; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED93; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED94; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + __IM uint8_t RESERVED95; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + __IM uint32_t RESERVED96[336]; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000A00) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + __IOM uint8_t DCSSMODE : 2; /*!< [3..2] DCDC SSMODE */ + uint8_t : 2; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + __IM uint8_t RESERVED97; + __IM uint16_t RESERVED98; + __IM uint32_t RESERVED99; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + __IM uint8_t RESERVED100; + __IM uint16_t RESERVED101; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + __IM uint8_t RESERVED102; + __IM uint16_t RESERVED103; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DPVD1IE : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DPVD2IE : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + __IOM uint8_t DPVD3IE : 1; /*!< [5..5] PVD3 Deep Standby Cancel Signal Enable */ + uint8_t : 2; + } DPSIER2_b; + }; + __IM uint8_t RESERVED104; + __IM uint16_t RESERVED105; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT0IE : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DULPT1IE : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable */ + uint8_t : 1; + __IOM uint8_t DIWDTIE : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DSOSTDIE : 1; /*!< [6..6] Sub-clock Oscillation stop detection Deep Standby Cancel + * Signal Enable */ + __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable */ + } DPSIER3_b; + }; + __IM uint8_t RESERVED106; + __IM uint16_t RESERVED107; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + __IM uint8_t RESERVED108; + __IM uint16_t RESERVED109; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + __IM uint8_t RESERVED110; + __IM uint16_t RESERVED111; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DPVD1IF : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DPVD2IF : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + __IOM uint8_t DPVD3IF : 1; /*!< [5..5] PVD5 Deep Standby Cancel Flag */ + uint8_t : 2; + } DPSIFR2_b; + }; + __IM uint8_t RESERVED112; + __IM uint16_t RESERVED113; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DULPT0IF : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DULPT1IF : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag */ + uint8_t : 1; + __IOM uint8_t DIWDTIF : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag */ + __IOM uint8_t DSOSTDIF : 1; /*!< [6..6] Sub-clock Oscillation stop detection Deep Standby Cancel + * Flag */ + __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag */ + } DPSIFR3_b; + }; + __IM uint8_t RESERVED114; + __IM uint16_t RESERVED115; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + __IM uint8_t RESERVED116; + __IM uint16_t RESERVED117; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ8EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ9EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + __IM uint8_t RESERVED118; + __IM uint16_t RESERVED119; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + __IOM uint8_t DLVD3IEG : 1; /*!< [5..5] LVD3 Edge Select */ + uint8_t : 2; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED120; + __IM uint16_t RESERVED121; + + union + { + __IOM uint8_t DPSIEGR3; /*!< (@ 0x00000A34) Deep Standby Interrupt Edge Register 3 */ + + struct + { + __IOM uint8_t DIRQ16EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ17EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ18EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ19EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ20EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ21EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ22EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ23EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR3_b; + }; + __IM uint8_t RESERVED122; + __IM uint16_t RESERVED123; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x00000A38) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + __IM uint8_t RESERVED124; + __IM uint16_t RESERVED125; + __IM uint32_t RESERVED126; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000A40) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect Flag */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect Flag */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect Flag */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect Flag */ + uint8_t : 1; + __IOM uint8_t LVD4RF : 1; /*!< [5..5] Voltage Monitor 4 Reset Detect Flag */ + __IOM uint8_t LVD5RF : 1; /*!< [6..6] Voltage Monitor 5 Reset Detect Flag */ + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag */ + } RSTSR0_b; + }; + __IM uint8_t RESERVED127; + __IM uint16_t RESERVED128; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000A44) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED129; + __IM uint16_t RESERVED130; + + union + { + __IOM uint8_t RSTSR3; /*!< (@ 0x00000A48) Reset Status Register 3 */ + + struct + { + __IOM uint8_t CVMRF : 1; /*!< [0..0] Core Voltage Monitor Reset Detect Flag */ + uint8_t : 3; + __IOM uint8_t OCPRF : 1; /*!< [4..4] Overcurrent Protection Reset Detect Flag */ + uint8_t : 2; + __IOM uint8_t TEMPRF : 1; /*!< [7..7] Temperature Monitor Reset Detect Flag */ + } RSTSR3_b; + }; + __IM uint8_t RESERVED131; + __IM uint16_t RESERVED132; + __IM uint32_t RESERVED133; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t MODRV0 : 3; /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching */ + uint8_t : 2; + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + uint8_t : 1; + } MOMCR_b; + }; + __IM uint8_t RESERVED134; + __IM uint16_t RESERVED135; + __IM uint32_t RESERVED136; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000A58) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD1CMPCR_b; + }; + __IM uint8_t RESERVED137; + __IM uint16_t RESERVED138; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000A5C) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD2CMPCR_b; + }; + __IM uint8_t RESERVED139; + __IM uint16_t RESERVED140; + + union + { + __IOM uint8_t LVD3CMPCR; /*!< (@ 0x00000A60) Voltage Monitoring 3 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD3CMPCR_b; + }; + __IM uint8_t RESERVED141; + __IM uint16_t RESERVED142; + + union + { + __IOM uint8_t LVD4CMPCR; /*!< (@ 0x00000A64) Voltage Monitoring 4 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD4CMPCR_b; + }; + __IM uint8_t RESERVED143; + __IM uint16_t RESERVED144; + + union + { + __IOM uint8_t LVD5CMPCR; /*!< (@ 0x00000A68) Voltage Monitoring 5 Comparator Control Register */ + + struct + { + __IOM uint8_t LVDLVL : 5; /*!< [4..0] Detection Voltage Level Select(Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVDE : 1; /*!< [7..7] Voltage Detection Enable */ + } LVD5CMPCR_b; + }; + __IM uint8_t RESERVED145; + __IM uint16_t RESERVED146; + __IM uint32_t RESERVED147; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + __IM uint8_t RESERVED148; + __IM uint16_t RESERVED149; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED150; + __IM uint16_t RESERVED151; + + union + { + __IOM uint8_t LVD3CR0; /*!< (@ 0x00000A78) Voltage Monitor 3 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD3CR0_b; + }; + __IM uint8_t RESERVED152; + __IM uint16_t RESERVED153; + + union + { + __IOM uint8_t LVD4CR0; /*!< (@ 0x00000A7C) Voltage Monitor 4 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD4CR0_b; + }; + __IM uint8_t RESERVED154; + __IM uint16_t RESERVED155; + + union + { + __IOM uint8_t LVD5CR0; /*!< (@ 0x00000A80) Voltage Monitor 5 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD5CR0_b; + }; + __IM uint8_t RESERVED156; + __IM uint16_t RESERVED157; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + __IM uint8_t RESERVED158; + __IM uint16_t RESERVED159; + + union + { + __IOM uint8_t VBTBPCR1; /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop */ + uint8_t : 7; + } VBTBPCR1_b; + }; + __IM uint8_t RESERVED160; + __IM uint16_t RESERVED161; + __IM uint32_t RESERVED162; + + union + { + __IOM uint8_t LPSCR; /*!< (@ 0x00000A90) Low Power State Control Register */ + + struct + { + __IOM uint8_t LPMD : 4; /*!< [3..0] Low power mode setting bit */ + uint8_t : 4; + } LPSCR_b; + }; + __IM uint8_t RESERVED163; + __IM uint16_t RESERVED164; + __IM uint32_t RESERVED165; + + union + { + __IOM uint8_t SSCR1; /*!< (@ 0x00000A98) Software Standby Control Register 1 */ + + struct + { + __IOM uint8_t SS2FR : 1; /*!< [0..0] Software Standby 2 Fast Return */ + uint8_t : 1; + __IOM uint8_t SS2LP : 2; /*!< [3..2] Software Standby 2 Low Power Select */ + uint8_t : 4; + } SSCR1_b; + }; + __IM uint8_t RESERVED166; + __IM uint16_t RESERVED167; + + union + { + __IOM uint8_t SVSCR; /*!< (@ 0x00000A9C) SSTBY Voltage Scaling Control Register */ + + struct + { + __IOM uint8_t SVSCM : 3; /*!< [2..0] SSTBY Voltage Scaling Control Mode */ + uint8_t : 5; + } SVSCR_b; + }; + __IM uint8_t RESERVED168; + __IM uint16_t RESERVED169; + __IM uint32_t RESERVED170[4]; + + union + { + __IOM uint8_t LVOCR; /*!< (@ 0x00000AB0) Low Voltage Operation Control Register */ + + struct + { + __IOM uint8_t LVO0E : 1; /*!< [0..0] Low Voltage Operation 0 Enable */ + __IOM uint8_t LVO1E : 1; /*!< [1..1] Low Voltage Operation 1 Enable */ + uint8_t : 6; + } LVOCR_b; + }; + __IM uint8_t RESERVED171; + __IM uint16_t RESERVED172; + + union + { + __IOM uint8_t MWMCR; /*!< (@ 0x00000AB4) MRAM-OTP Write Mode Control Register */ + + struct + { + __IOM uint8_t MWM : 2; /*!< [1..0] MRAM-OTP Write Mode */ + uint8_t : 6; + } MWMCR_b; + }; + __IM uint8_t RESERVED173; + __IM uint16_t RESERVED174; + __IM uint32_t RESERVED175[6]; + + union + { + __IOM uint8_t SYRSTMSK0; /*!< (@ 0x00000AD0) System Reset Mask Control Register 0 */ + + struct + { + __IOM uint8_t IWDTMASK : 1; /*!< [0..0] Independent Watchdog Timer Reset Mask */ + __IOM uint8_t WDT0MASK : 1; /*!< [1..1] Watchdog Timer Reset Mask */ + __IOM uint8_t SWMASK : 1; /*!< [2..2] Software Reset Mask */ + uint8_t : 1; + __IOM uint8_t CLU0MASK : 1; /*!< [4..4] CPU Lockup Reset Mask */ + __IOM uint8_t LM0MASK : 1; /*!< [5..5] Local Memory 0 Error Reset Mask */ + __IOM uint8_t CMMASK : 1; /*!< [6..6] Common Memory Error Reset Mask */ + __IOM uint8_t BUSMASK : 1; /*!< [7..7] Bus Error Reset Mask */ + } SYRSTMSK0_b; + }; + __IM uint8_t RESERVED176; + __IM uint16_t RESERVED177; + + union + { + __IOM uint8_t SYRSTMSK1; /*!< (@ 0x00000AD4) System Reset Mask Control Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog Timer Reset Mask */ + uint8_t : 2; + __IOM uint8_t CLU1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */ + __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local Memory 1 Error Reset Mask */ + uint8_t : 2; + } SYRSTMSK1_b; + }; + __IM uint8_t RESERVED178; + __IM uint16_t RESERVED179; + + union + { + __IOM uint8_t SYRSTMSK2; /*!< (@ 0x00000AD8) System Reset Mask Control Register 2 */ + + struct + { + __IOM uint8_t PVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask */ + __IOM uint8_t PVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask */ + uint8_t : 6; + } SYRSTMSK2_b; + }; + __IM uint8_t RESERVED180; + __IM uint16_t RESERVED181; + + union + { + __IOM uint8_t TEMPRCR; /*!< (@ 0x00000ADC) Temperature Monitor Reset Control Register */ + + struct + { + __IOM uint8_t TEMPREN : 1; /*!< [0..0] Temperature Monitor Reset Enable */ + __IOM uint8_t TSNEN : 1; /*!< [1..1] Temperature Monitor Sensor Enable */ + __IOM uint8_t CMPEN : 1; /*!< [2..2] Comparator Enable */ + __IOM uint8_t TSNKEEP : 1; /*!< [3..3] Temperature Monitor Sensor Latch Control */ + uint8_t : 4; + } TEMPRCR_b; + }; + __IM uint8_t RESERVED182; + __IM uint16_t RESERVED183; + + union + { + __IOM uint8_t TEMPRLR; /*!< (@ 0x00000AE0) Temperature Monitor Reset Lock Register */ + + struct + { + __IOM uint8_t LOCK : 1; /*!< [0..0] Temperature Monitor Reset Control Register Lock */ + uint8_t : 7; + } TEMPRLR_b; + }; + __IM uint8_t RESERVED184; + __IM uint16_t RESERVED185; + __IM uint32_t RESERVED186[7]; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000B00) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + __IOM uint8_t LDOSTP2 : 1; /*!< [2..2] LDO2 Stop */ + __IOM uint8_t LDOSTP3 : 1; /*!< [3..3] LDO3 Stop */ + __IOM uint8_t LDOSTP4 : 1; /*!< [4..4] LDO4 Stop */ + __IOM uint8_t LDOSTP5 : 1; /*!< [5..5] LDO5 Stop */ + __IOM uint8_t LDOSTP6 : 1; /*!< [6..6] LDO6 Stop */ + __IOM uint8_t LDOSTP7 : 1; /*!< [7..7] LDO7 Stop */ + } LDOSCR_b; + }; + __IM uint8_t RESERVED187; + __IM uint16_t RESERVED188; + + union + { + __IOM uint8_t PLL1LDOCR; /*!< (@ 0x00000B04) PLL1-LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL1LDOCR_b; + }; + __IM uint8_t RESERVED189; + __IM uint16_t RESERVED190; + + union + { + __IOM uint8_t PLL2LDOCR; /*!< (@ 0x00000B08) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } PLL2LDOCR_b; + }; + __IM uint8_t RESERVED191; + __IM uint16_t RESERVED192; + + union + { + __IOM uint8_t HOCOLDOCR; /*!< (@ 0x00000B0C) HOCO-LDO Control Register */ + + struct + { + __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */ + uint8_t : 6; + } HOCOLDOCR_b; + }; + __IM uint8_t RESERVED193; + __IM uint16_t RESERVED194; + + union + { + __IOM uint8_t MOMCR2; /*!< (@ 0x00000B10) Main Clock Oscillator Mode Oscillation Control + * Register 2 */ + + struct + { + __IOM uint8_t MOMODE : 1; /*!< [0..0] Main Clock Oscillator Mode Select */ + uint8_t : 7; + } MOMCR2_b; + }; + __IM uint8_t RESERVED195; + __IM uint16_t RESERVED196; + __IM uint32_t RESERVED197[3]; + + union + { + __IOM uint8_t LVD1FCR; /*!< (@ 0x00000B20) Voltage Monitor 1 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD1FCR_b; + }; + __IM uint8_t RESERVED198; + __IM uint16_t RESERVED199; + + union + { + __IOM uint8_t LVD2FCR; /*!< (@ 0x00000B24) Voltage Monitor 2 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD2FCR_b; + }; + __IM uint8_t RESERVED200; + __IM uint16_t RESERVED201; + + union + { + __IOM uint8_t LVD3FCR; /*!< (@ 0x00000B28) Voltage Monitor 3 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD3FCR_b; + }; + __IM uint8_t RESERVED202; + __IM uint16_t RESERVED203; + + union + { + __IOM uint8_t LVD4FCR; /*!< (@ 0x00000B2C) Voltage Monitor 4 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD4FCR_b; + }; + __IM uint8_t RESERVED204; + __IM uint16_t RESERVED205; + + union + { + __IOM uint8_t LVD5FCR; /*!< (@ 0x00000B30) Voltage Monitor 5 Function Control Register */ + + struct + { + __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */ + uint8_t : 7; + } LVD5FCR_b; + }; + __IM uint8_t RESERVED206; + __IM uint16_t RESERVED207; + + union + { + __IOM uint8_t PVDLR; /*!< (@ 0x00000B34) Voltage Monitor Lock Register */ + + struct + { + __IOM uint8_t LOCK : 1; /*!< [0..0] LOCK control */ + uint8_t : 7; + } PVDLR_b; + }; + __IM uint8_t RESERVED208; + __IM uint16_t RESERVED209; + __IM uint32_t RESERVED210[2]; + + union + { + __IOM uint8_t DPSIER4; /*!< (@ 0x00000B40) Deep Standby Interrupt Enable Register 4 */ + + struct + { + __IOM uint8_t DIRQ16E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ17E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ18E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ19E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ20E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ21E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ22E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ23E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER4_b; + }; + __IM uint8_t RESERVED211; + __IM uint16_t RESERVED212; + + union + { + __IOM uint8_t DPSIER5; /*!< (@ 0x00000B44) Deep Standby Interrupt Enable Register 5 */ + + struct + { + __IOM uint8_t DIRQ24E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ25E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ26E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ27E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ28E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ29E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ30E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ31E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER5_b; + }; + __IM uint8_t RESERVED213; + __IM uint16_t RESERVED214; + + union + { + __IOM uint8_t DPSIFR4; /*!< (@ 0x00000B48) Deep Standby Interrupt Flag Register 4 */ + + struct + { + __IOM uint8_t DIRQ16F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ17F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ18F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ19F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ20F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ21F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ22F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ23F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR4_b; + }; + __IM uint8_t RESERVED215; + __IM uint16_t RESERVED216; + + union + { + __IOM uint8_t DPSIFR5; /*!< (@ 0x00000B4C) Deep Standby Interrupt Flag Register 5 */ + + struct + { + __IOM uint8_t DIRQ24F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ25F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ26F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ27F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ28F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ29F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ30F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ31F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR5_b; + }; + __IM uint8_t RESERVED217; + __IM uint16_t RESERVED218; + + union + { + __IOM uint8_t DPSIEGR4; /*!< (@ 0x00000B50) Deep Standby Interrupt Edge Register 4 */ + + struct + { + __IOM uint8_t DIRQ24EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ25EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ26EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ27EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ28EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ29EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ30EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ31EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR4_b; + }; + __IM uint8_t RESERVED219; + __IM uint16_t RESERVED220; + __IM uint32_t RESERVED221[3]; + + union + { + __IOM uint8_t VBTSWMON; /*!< (@ 0x00000B60) LVDVBATSW control Monitor Register */ + + struct + { + __IOM uint8_t VLVLMON : 3; /*!< [2..0] VDETBAT Level Monitor */ + uint8_t : 1; + __IOM uint8_t VDETEMON : 1; /*!< [4..4] Voltage drop detection enable Monitor */ + uint8_t : 3; + } VBTSWMON_b; + }; + __IM uint8_t RESERVED222; + __IM uint16_t RESERVED223; + + union + { + __IOM uint8_t VBTSWSCR; /*!< (@ 0x00000B64) LVDVBATSW Start-up stable wait Control Register */ + + struct + { + __IOM uint8_t VBTSWE : 1; /*!< [0..0] LVDVBATSW output enable */ + uint8_t : 7; + } VBTSWSCR_b; + }; + __IM uint8_t RESERVED224; + __IM uint16_t RESERVED225; + __IM uint32_t RESERVED226[38]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000C00) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 4; + __IOM uint8_t SOSEL : 1; /*!< [6..6] Sub-Clock Oscillator Switching */ + uint8_t : 1; + } SOMCR_b; + }; + __IM uint16_t RESERVED227; + + union + { + __IOM uint8_t SOSTDCR; /*!< (@ 0x00000C04) Sub-clock Oscillation Stop Detection Control + * Register */ + + struct + { + __IOM uint8_t SOSTDIE : 1; /*!< [0..0] Sub-clock Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t SOSTDE : 1; /*!< [7..7] Sub-clock Oscillation Stop Detection Function Enable */ + } SOSTDCR_b; + }; + + union + { + __IOM uint8_t SOSTDSR; /*!< (@ 0x00000C05) Sub-clock Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t SOSTDF : 1; /*!< [0..0] Sub-clock Oscillation Stop Detection Flag */ + uint8_t : 7; + } SOSTDSR_b; + }; + __IM uint16_t RESERVED228; + __IM uint32_t RESERVED229[14]; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x00000C40) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED230; + __IM uint16_t RESERVED231; + __IM uint8_t RESERVED232; + + union + { + __IOM uint8_t VBTBPCR2; /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2 */ + + struct + { + __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select */ + uint8_t : 1; + __IOM uint8_t VDETE : 1; /*!< [4..4] Voltage drop detection enable */ + uint8_t : 3; + } VBTBPCR2_b; + }; + + union + { + __IOM uint8_t VBTBPSR; /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register */ + + struct + { + __IOM uint8_t VBPORF : 1; /*!< [0..0] VBATT_POR Flag */ + uint8_t : 3; + __IOM uint8_t VBPORM : 1; /*!< [4..4] VBATT_POR Monitor */ + __IOM uint8_t BPWSWM : 1; /*!< [5..5] Battery Power Supply Switch Status Monitor */ + uint8_t : 2; + } VBTBPSR_b; + }; + __IM uint8_t RESERVED233; + + union + { + __IOM uint8_t VBTADSR; /*!< (@ 0x00000C48) VBATT Tamper detection Status Register */ + + struct + { + __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0 */ + __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1 */ + __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2 */ + uint8_t : 5; + } VBTADSR_b; + }; + + union + { + __IOM uint8_t VBTADCR1; /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1 */ + + struct + { + __IOM uint8_t VBTADIE0 : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0 */ + __IOM uint8_t VBTADIE1 : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1 */ + __IOM uint8_t VBTADIE2 : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2 */ + uint8_t : 1; + __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0 */ + __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1 */ + __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2 */ + uint8_t : 1; + } VBTADCR1_b; + }; + + union + { + __IOM uint8_t VBTADCR2; /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2 */ + + struct + { + __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0 */ + __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1 */ + __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2 */ + uint8_t : 5; + } VBTADCR2_b; + }; + __IM uint8_t RESERVED234; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x00000C4C) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTICTLR2; /*!< (@ 0x00000C4D) VBATT Input Control Register 2 */ + + struct + { + __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable */ + __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable */ + __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable */ + uint8_t : 1; + __IOM uint8_t VCH0EG : 1; /*!< [4..4] VBATT CH0 Input Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [5..5] VBATT CH1 Input Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [6..6] VBATT CH2 Input Edge Select */ + uint8_t : 1; + } VBTICTLR2_b; + }; + + union + { + __IOM uint8_t VBTIMONR; /*!< (@ 0x00000C4E) VBATT Input Monitor Register */ + + struct + { + __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor */ + __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor */ + __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor */ + uint8_t : 5; + } VBTIMONR_b; + }; + __IM uint8_t RESERVED235; + + union + { + __IOM uint8_t VBTNCWCR; /*!< (@ 0x00000C50) VBATT Noise Canceler Width Control Register */ + + struct + { + __IOM uint8_t VINCW : 3; /*!< [2..0] VBATT Input Noise Canceler Width select */ + uint8_t : 5; + } VBTNCWCR_b; + }; + __IM uint8_t RESERVED236; + __IM uint16_t RESERVED237; + + union + { + __IOM uint8_t VBTADCR3; /*!< (@ 0x00000C54) VBATT Tamper detection Control Register 3 */ + + struct + { + __IOM uint8_t VBTADZE0 : 1; /*!< [0..0] VBATT Tamper Detection Zeroization Enable 0 */ + __IOM uint8_t VBTADZE1 : 1; /*!< [1..1] VBATT Tamper Detection Zeroization Enable 1 */ + __IOM uint8_t VBTADZE2 : 1; /*!< [2..2] VBATT Tamper Detection Zeroization Enable 2 */ + uint8_t : 5; + } VBTADCR3_b; + }; + __IM uint8_t RESERVED238; + __IM uint16_t RESERVED239; + __IM uint32_t RESERVED240[42]; + + union + { + __IOM uint8_t VBTBKR[128]; /*!< (@ 0x00000D00) VBATT Backup Register [0..127] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[128]; + }; +} R_SYSTEM_Type; /*!< Size = 3456 (0xd80) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x02C1EDA0) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x40235000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t DVCHGR; /*!< (@ 0x0000004E) Device State Change Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } DVCHGR_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery */ + uint16_t : 4; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_VIN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Video Input Module (R_VIN) + */ + +typedef struct /*!< (@ 0x40347400) R_VIN Structure */ +{ + union + { + __IOM uint32_t MC; /*!< (@ 0x00000000) Main Control Register */ + + struct + { + __IOM uint32_t ME : 1; /*!< [0..0] Module Enable */ + __IOM uint32_t BPS : 1; /*!< [1..1] Color Space Conversion Bypass Mode */ + uint32_t : 1; + __IOM uint32_t IM : 2; /*!< [4..3] Interlace Mode */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [6..6] Endian Type */ + uint32_t : 7; + __IOM uint32_t DC : 2; /*!< [15..14] Dithering Mode Control */ + __IOM uint32_t INF : 3; /*!< [18..16] Input Interface Format */ + uint32_t : 1; + __IOM uint32_t LUTE : 1; /*!< [20..20] Lookup Table Enable */ + uint32_t : 1; + __OM uint32_t ST : 1; /*!< [22..22] Initialization control at STartup */ + uint32_t : 1; + __IOM uint32_t DC2 : 1; /*!< [24..24] Dithering mode Control 2 */ + __IOM uint32_t YUV444 : 1; /*!< [25..25] YUV444 conversion */ + __IOM uint32_t SCLE : 1; /*!< [26..26] This bit is used to enable or disable scaling by the + * UDS. */ + uint32_t : 1; + __IOM uint32_t CLP : 2; /*!< [29..28] Pixel Data Clipping */ + uint32_t : 2; + } MC_b; + }; + + union + { + __IM uint32_t MS; /*!< (@ 0x00000004) Module Status Register */ + + struct + { + __IM uint32_t CA : 1; /*!< [0..0] Video Capture Active Status */ + __IM uint32_t AV : 1; /*!< [1..1] Active Video Status */ + __IM uint32_t FS : 1; /*!< [2..2] Field Status */ + __IM uint32_t FBS : 2; /*!< [4..3] Frame Buffer Status */ + uint32_t : 11; + __IM uint32_t MA : 1; /*!< [16..16] External frame Memory capture Active status */ + uint32_t : 2; + __IM uint32_t FMS : 2; /*!< [20..19] External Frame Memory buffer Status */ + uint32_t : 11; + } MS_b; + }; + + union + { + __IOM uint32_t FC; /*!< (@ 0x00000008) Frame Capture Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t CC : 1; /*!< [1..1] Continuous Frame Capture Mode */ + uint32_t : 30; + } FC_b; + }; + + union + { + __IOM uint32_t SLPRC; /*!< (@ 0x0000000C) Start Line Pre-Clip Register */ + + struct + { + __IOM uint32_t SLPRC : 12; /*!< [11..0] Start Line PRe-Clip */ + uint32_t : 20; + } SLPRC_b; + }; + + union + { + __IOM uint32_t ELPRC; /*!< (@ 0x00000010) End Line Pre-Clip Register */ + + struct + { + __IOM uint32_t ELPRC : 12; /*!< [11..0] End Line PRe-Clip */ + uint32_t : 20; + } ELPRC_b; + }; + + union + { + __IOM uint32_t SPPRC; /*!< (@ 0x00000014) Start Pixel Pre-Clip Register */ + + struct + { + __IOM uint32_t SPPRC : 12; /*!< [11..0] Start Pixel Pre-Clip */ + uint32_t : 20; + } SPPRC_b; + }; + + union + { + __IOM uint32_t EPPRC; /*!< (@ 0x00000018) End Pixel Pre-Clip Register */ + + struct + { + __IOM uint32_t EPPRC : 12; /*!< [11..0] End Pixel PRe-Clip */ + uint32_t : 20; + } EPPRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CSI_IFMD; /*!< (@ 0x00000020) CSI2 Interface Mode Register */ + + struct + { + __IOM uint32_t VC_SEL : 4; /*!< [3..0] Virtual Channel SELect */ + uint32_t : 4; + __IOM uint32_t DT : 6; /*!< [13..8] Data Type select */ + uint32_t : 11; + __IOM uint32_t DES0 : 1; /*!< [25..25] Data Extension Select */ + uint32_t : 6; + } CSI_IFMD_b; + }; + + union + { + __IOM uint32_t CSIFLD; /*!< (@ 0x00000024) Field detection control Register */ + + struct + { + __IOM uint32_t FLD_EN : 1; /*!< [0..0] FieLD detect ENable */ + uint32_t : 3; + __IOM uint32_t FLD_SEL : 2; /*!< [5..4] even FieLD DETect SELect */ + uint32_t : 10; + __IOM uint32_t FLD_NUM : 1; /*!< [16..16] even FieLD NUMber setting */ + uint32_t : 15; + } CSIFLD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t IS; /*!< (@ 0x0000002C) Image Stride Register */ + + struct + { + __IOM uint32_t IS : 13; /*!< [12..0] Image Stride (Setting unit: pixel) */ + uint32_t : 19; + } IS_b; + }; + + union + { + __IOM uint32_t MB1; /*!< (@ 0x00000030) Memory Base 1 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB1 : 25; /*!< [31..7] Memory Base Address 1 */ + } MB1_b; + }; + + union + { + __IOM uint32_t MB2; /*!< (@ 0x00000034) Memory Base 2 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB2 : 25; /*!< [31..7] Memory Base Address 2 */ + } MB2_b; + }; + + union + { + __IOM uint32_t MB3; /*!< (@ 0x00000038) Memory Base 3 Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MB3 : 25; /*!< [31..7] Memory Base Address 3 */ + } MB3_b; + }; + + union + { + __IM uint32_t LC; /*!< (@ 0x0000003C) Line Count Register */ + + struct + { + __IM uint32_t LC : 12; /*!< [11..0] Line Count */ + uint32_t : 20; + } LC_b; + }; + + union + { + __IOM uint32_t IE; /*!< (@ 0x00000040) Interrupt Enable Register */ + + struct + { + __IOM uint32_t FOE : 1; /*!< [0..0] FIFO Overflow Interrupt Enable */ + __IOM uint32_t EFE : 1; /*!< [1..1] End of Frame Interrupt Enable */ + __IOM uint32_t SIE : 1; /*!< [2..2] Scanline Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t FIE : 1; /*!< [4..4] Field Interrupt Enable */ + __IOM uint32_t FME : 1; /*!< [5..5] Frame Memory write completion interrupt Enable */ + uint32_t : 2; + __IOM uint32_t PRCLIPHEE : 1; /*!< [8..8] PRCLIPH Error interrupt Enable */ + __IOM uint32_t PRCLIPVEE : 1; /*!< [9..9] PRCLIPV Error interrupt Enable */ + uint32_t : 4; + __IOM uint32_t ROE : 1; /*!< [14..14] Response Overflow interrupt Enable */ + __IOM uint32_t AREE : 1; /*!< [15..15] Axi Resp Error interrupt Enable */ + __IOM uint32_t VRE : 1; /*!< [16..16] VSYNC Deasserting Detect Interrupt Enable */ + __IOM uint32_t VFE : 1; /*!< [17..17] Vsync asserting detect interrupt Enable */ + uint32_t : 13; + __IOM uint32_t FIE2 : 1; /*!< [31..31] Field Interrupt Enable 2 */ + } IE_b; + }; + + union + { + __IOM uint32_t INTS; /*!< (@ 0x00000044) Interrupt Status Register */ + + struct + { + __IOM uint32_t FOS : 1; /*!< [0..0] FIFO Overflow Interrupt Status */ + __IOM uint32_t EFS : 1; /*!< [1..1] End of Frame Interrupt Status */ + __IOM uint32_t SIS : 1; /*!< [2..2] Scanline Interrupt Status */ + uint32_t : 1; + __IOM uint32_t FIS : 1; /*!< [4..4] Field Interrupt Status */ + __IOM uint32_t FMS : 1; /*!< [5..5] Frame Memory write completion interrupt Status */ + uint32_t : 2; + __IOM uint32_t PRCLIPHES : 1; /*!< [8..8] PRCLIPH Error interrupt Status */ + __IOM uint32_t PRCLIPVES : 1; /*!< [9..9] PRCLIPV Error interrupt Status */ + uint32_t : 4; + __IOM uint32_t ROS : 1; /*!< [14..14] Response Overflow interrupt Status */ + __IOM uint32_t ARES : 1; /*!< [15..15] Axi Resp Error interrupt Status */ + __IOM uint32_t VRS : 1; /*!< [16..16] VSYNC Deasserting Detect Interrupt Status */ + __IOM uint32_t VFS : 1; /*!< [17..17] VSYNC Asserting Detect Interrupt Status */ + uint32_t : 13; + __IOM uint32_t FIS2 : 1; /*!< [31..31] Field Interrupt Status 2 */ + } INTS_b; + }; + + union + { + __IOM uint32_t SI; /*!< (@ 0x00000048) Scanline Interrupt Register */ + + struct + { + __IOM uint32_t SI : 12; /*!< [11..0] Scanline Interrupt Setting */ + uint32_t : 20; + } SI_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t MTCSTOP; /*!< (@ 0x00000054) AXI transfer stop control register */ + + struct + { + __IOM uint32_t STOPREQ : 1; /*!< [0..0] axi forced STOP REQuest */ + __IM uint32_t STOPACK : 1; /*!< [1..1] for axi forced STOP request, ACKnowledgement */ + uint32_t : 14; + __IM uint32_t OUTSTAND : 6; /*!< [21..16] OUTSTANDing current number */ + uint32_t : 10; + } MTCSTOP_b; + }; + + union + { + __IOM uint32_t DMR; /*!< (@ 0x00000058) Data Mode Register */ + + struct + { + __IOM uint32_t DTMD : 2; /*!< [1..0] Data Conversion Mode */ + __IOM uint32_t ABIT : 1; /*!< [2..2] Alpha Bit */ + uint32_t : 1; + __IOM uint32_t BPSM : 1; /*!< [4..4] Output Data Byte Swap Mode */ + uint32_t : 3; + __IOM uint32_t EXRGB : 1; /*!< [8..8] Extension RGB Conversion Mode */ + uint32_t : 2; + __IOM uint32_t YC_THR : 1; /*!< [11..11] YC Data Through Mode */ + __IOM uint32_t YMODE : 3; /*!< [14..12] YC Data Transfer Mode */ + uint32_t : 9; + __IOM uint32_t A8BIT : 8; /*!< [31..24] Alpha 8 */ + } DMR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t UVAOF; /*!< (@ 0x00000060) UV Address Offset Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t UVAOF : 25; /*!< [31..7] UV Data Address Offset */ + } UVAOF_b; + }; + __IM uint32_t RESERVED4[7]; + + union + { + __IOM uint32_t UDS_CTRL; /*!< (@ 0x00000080) Scaling Control Registers */ + + struct + { + uint32_t : 16; + __IOM uint32_t NE_BCB : 1; /*!< [16..16] B/Cb Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + __IOM uint32_t NE_GY : 1; /*!< [17..17] G/Y Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + __IOM uint32_t NE_RCR : 1; /*!< [18..18] R/Cr Interpolation Method When Bilinear/Nearest Neighbor + * Interpolation is Selected */ + uint32_t : 1; + __IOM uint32_t BC : 1; /*!< [20..20] Pixel Component Interpolation Method at Scale-Up/Down */ + uint32_t : 7; + __IOM uint32_t BLADV : 1; /*!< [28..28] BiLinear or nearest neighbor interpolation characteristic + * ADVanced mode */ + uint32_t : 1; + __IOM uint32_t AMD : 1; /*!< [30..30] Advanced MoDe: Pixel Count at Scale-Up */ + uint32_t : 1; + } UDS_CTRL_b; + }; + + union + { + __IOM uint32_t UDS_SCALE; /*!< (@ 0x00000084) Scaling Factor Registers */ + + struct + { + __IOM uint32_t VFRAC : 12; /*!< [11..0] Multiplier (Fractional Part) of Vertical Scaling Factor */ + __IOM uint32_t VMANT : 4; /*!< [15..12] Multiplier (Integral Part) of Vertical Scaling Factor */ + __IOM uint32_t HFRAC : 12; /*!< [27..16] Multiplier (Fractional Part) of Horizontal Scaling + * Factor */ + __IOM uint32_t HMANT : 4; /*!< [31..28] Multiplier (Integral Part) of Horizontal Scaling Factor */ + } UDS_SCALE_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t UDS_PASS_BWIDTH; /*!< (@ 0x00000090) Passband Registers */ + + struct + { + __IOM uint32_t BWIDTH_V : 7; /*!< [6..0] Vertical Signal Passband at Image Scale-Up/Down */ + uint32_t : 9; + __IOM uint32_t BWIDTH_H : 7; /*!< [22..16] Horizontal Signal Passband at Image Scale-Up/Down */ + uint32_t : 9; + } UDS_PASS_BWIDTH_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t UDS_CLIP_SIZE; /*!< (@ 0x000000A4) UDS Output Size Clipping Registers */ + + struct + { + __IOM uint32_t CL_VSIZE : 12; /*!< [11..0] Clipping Size of Vertical Pixel Count after Scale-Up/-Down */ + uint32_t : 4; + __IOM uint32_t CL_HSIZE : 12; /*!< [27..16] Clipping Size of Horizontal Pixel Count after Scale-Up/-Down */ + uint32_t : 4; + } UDS_CLIP_SIZE_b; + }; + __IM uint32_t RESERVED7[22]; + + union + { + __IOM uint32_t LUTP; /*!< (@ 0x00000100) Lookup Table Pointer Register */ + + struct + { + __IOM uint32_t LTCRPR : 10; /*!< [9..0] Lookup Table Cr Pointer */ + __IOM uint32_t LTCBPR : 10; /*!< [19..10] Lookup Table Cb Pointer */ + __IOM uint32_t LTYPR : 10; /*!< [29..20] Lookup Table Y Pointer */ + uint32_t : 2; + } LUTP_b; + }; + + union + { + __IOM uint32_t LUTD; /*!< (@ 0x00000104) Lookup Table Data Register */ + + struct + { + __IOM uint32_t LTCRDT : 8; /*!< [7..0] Lookup Table Cr Data */ + __IOM uint32_t LTCBDT : 8; /*!< [15..8] Lookup Table Cb Data */ + __IOM uint32_t LTYDT : 8; /*!< [23..16] Lookup Table Y Data */ + uint32_t : 8; + } LUTD_b; + }; + __IM uint32_t RESERVED8[72]; + + union + { + __IOM uint32_t YCCR1; /*!< (@ 0x00000228) RGB to Y Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t YCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Y Calculation */ + uint32_t : 19; + } YCCR1_b; + }; + + union + { + __IOM uint32_t YCCR2; /*!< (@ 0x0000022C) RGB to Y Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t YCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Y Calculation */ + uint32_t : 3; + __IOM uint32_t YCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Y Calculation */ + uint32_t : 3; + } YCCR2_b; + }; + + union + { + __IOM uint32_t YCCR3; /*!< (@ 0x00000230) RGB to Y Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t YCLAP : 12; /*!< [11..0] Y Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t YCLHEN : 1; /*!< [23..23] Y Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t YCLSFT : 5; /*!< [28..24] Y Calculation Shift Down Volume */ + uint32_t : 3; + } YCCR3_b; + }; + + union + { + __IOM uint32_t CBCCR1; /*!< (@ 0x00000234) RGB to Cb Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t CBCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Cb Calculation */ + uint32_t : 19; + } CBCCR1_b; + }; + + union + { + __IOM uint32_t CBCCR2; /*!< (@ 0x00000238) RGB to Cb Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t CBCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Cb Calculation */ + uint32_t : 3; + __IOM uint32_t CBCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Cb Calculation */ + uint32_t : 3; + } CBCCR2_b; + }; + + union + { + __IOM uint32_t CBCCR3; /*!< (@ 0x0000023C) RGB to Cb Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t CBCLAP : 12; /*!< [11..0] Cb Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t CBCLHEN : 1; /*!< [23..23] Cb Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t CBCLSFT : 5; /*!< [28..24] Cb Calculation Shift Down Volume */ + uint32_t : 3; + } CBCCR3_b; + }; + + union + { + __IOM uint32_t CRCCR1; /*!< (@ 0x00000240) RGB to Cr Calculation Setting Register 1 */ + + struct + { + __IOM uint32_t CRCLRP : 13; /*!< [12..0] R Multiplication Coefficient for Cr Calculation */ + uint32_t : 19; + } CRCCR1_b; + }; + + union + { + __IOM uint32_t CRCCR2; /*!< (@ 0x00000244) RGB to Cr Calculation Setting Register 2 */ + + struct + { + __IOM uint32_t CRCLGP : 13; /*!< [12..0] G Multiplication Coefficient for Cr Calculation */ + uint32_t : 3; + __IOM uint32_t CRCLBP : 13; /*!< [28..16] B Multiplication Coefficient for Cr Calculation */ + uint32_t : 3; + } CRCCR2_b; + }; + + union + { + __IOM uint32_t CRCCR3; /*!< (@ 0x00000248) RGB to Cr Calculation Setting Register 3 */ + + struct + { + __IOM uint32_t CRCLAP : 12; /*!< [11..0] Cr Calculation Data Normalized Additional Value */ + uint32_t : 11; + __IOM uint32_t CRCLHEN : 1; /*!< [23..23] Cr Calculation Shift Down Result Round-Off Enable */ + __IOM uint32_t CRCLSFT : 5; /*!< [28..24] Cr Calculation Shift Down Volume */ + uint32_t : 3; + } CRCCR3_b; + }; + __IM uint32_t RESERVED9[45]; + + union + { + __IOM uint32_t CSCE1; /*!< (@ 0x00000300) YC to RGB Calculation Setting Extension Register + * 1 */ + + struct + { + __IOM uint32_t YMUL2 : 14; /*!< [13..0] Y Multiplication Coefficient 2 for RGB Calculation */ + uint32_t : 2; + __IOM uint32_t ROUND : 1; /*!< [16..16] ROUND off enable */ + uint32_t : 15; + } CSCE1_b; + }; + + union + { + __IOM uint32_t CSCE2; /*!< (@ 0x00000304) YC to RGB Calculation Setting Extension Register + * 2 */ + + struct + { + __IOM uint32_t CSUB2 : 12; /*!< [11..0] CbCr Subtraction Coefficient 2 for RGB Calculation */ + uint32_t : 4; + __IOM uint32_t YSUB2 : 12; /*!< [27..16] Y Subtraction Coefficient 2 for RGB Calculation */ + uint32_t : 4; + } CSCE2_b; + }; + + union + { + __IOM uint32_t CSCE3; /*!< (@ 0x00000308) YC to RGB Calculation Setting Extension Register + * 3 */ + + struct + { + __IOM uint32_t GCRMUL2 : 14; /*!< [13..0] Cr Multiplication Coefficient 2 for G Calculation */ + uint32_t : 2; + __IOM uint32_t RCRMUL2 : 14; /*!< [29..16] Cr Multiplication Coefficient 2 for R Calculation */ + uint32_t : 2; + } CSCE3_b; + }; + + union + { + __IOM uint32_t CSCE4; /*!< (@ 0x0000030C) YC to RGB Calculation Setting Extension Register + * 4 */ + + struct + { + __IOM uint32_t BCBMUL2 : 14; /*!< [13..0] Cb Multiplication Coefficient 2 for B Calculation */ + uint32_t : 2; + __IOM uint32_t GCBMUL2 : 14; /*!< [29..16] Cb Multiplication Coefficient 2 for G Calculation */ + uint32_t : 2; + } CSCE4_b; + }; +} R_VIN_Type; /*!< Size = 784 (0x310) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40202600) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 7; + __IOM uint32_t FC : 1; /*!< [8..8] C-Cache flush bit */ + __IOM uint32_t WB : 1; /*!< [9..9] C-cache write back */ + uint32_t : 22; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + __IOM uint32_t WB : 1; /*!< [1..1] C-Cache write back */ + uint32_t : 30; + } CCAFCT_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CCAWTA; /*!< (@ 0x0000000C) C-Cache Write Attribute */ + + struct + { + __IOM uint32_t WT : 1; /*!< [0..0] C-Cache write through */ + __IOM uint32_t WA : 1; /*!< [1..1] C-Cache write allocation */ + uint32_t : 30; + } CCAWTA_b; + }; + + union + { + __IOM uint32_t CCAEDST; /*!< (@ 0x00000010) C-Cache Error Detection Status */ + + struct + { + __IOM uint32_t ESD0 : 1; /*!< [0..0] C-Cache data error status 0 */ + __IOM uint32_t ESD1 : 1; /*!< [1..1] C-Cache data error status 1 */ + __IOM uint32_t ESTC : 1; /*!< [2..2] C-Cache Tag clean line invalidate status */ + __IOM uint32_t ESTD : 1; /*!< [3..3] C-Cache Tag dirty line invalidate status */ + __IOM uint32_t EST2 : 1; /*!< [4..4] C-Cache Tag 2bit error status */ + uint32_t : 27; + } CCAEDST_b; + }; + + union + { + __IOM uint32_t CCATAA; /*!< (@ 0x00000014) C-Cache Test Access Address */ + + struct + { + uint32_t : 2; + __IOM uint32_t OFFSET : 3; /*!< [4..2] address offset */ + __IOM uint32_t ENTRY : 7; /*!< [11..5] address entry */ + uint32_t : 4; + __IOM uint32_t TARGET : 3; /*!< [18..16] access target */ + uint32_t : 4; + __IOM uint32_t RW : 1; /*!< [23..23] read write */ + uint32_t : 6; + __IOM uint32_t WAY : 2; /*!< [31..30] address way */ + } CCATAA_b; + }; + + union + { + __IOM uint32_t CCATAD; /*!< (@ 0x00000018) C-Cache Test Access Data */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Cache data */ + } CCATAD_b; + }; + __IM uint32_t RESERVED1[9]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 7; + __IOM uint32_t FS : 1; /*!< [8..8] S-Cache flush bit */ + __IOM uint32_t WB : 1; /*!< [9..9] S-cache write back */ + uint32_t : 22; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + __IOM uint32_t WB : 1; /*!< [1..1] S-Cache write back */ + uint32_t : 30; + } SCAFCT_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SCAWTA; /*!< (@ 0x0000004C) S-Cache Write Attribute */ + + struct + { + __IOM uint32_t WT : 1; /*!< [0..0] S-Cache write through */ + __IOM uint32_t WA : 1; /*!< [1..1] S-Cache write allocation */ + uint32_t : 30; + } SCAWTA_b; + }; + + union + { + __IOM uint32_t SCAEDST; /*!< (@ 0x00000050) S-Cache Error Detection Status */ + + struct + { + __IOM uint32_t ESD0 : 1; /*!< [0..0] S-Cache data error status 0 */ + __IOM uint32_t ESD1 : 1; /*!< [1..1] S-Cache data error status 1 */ + __IOM uint32_t ESTC : 1; /*!< [2..2] S-Cache Tag clean line invalidate status */ + __IOM uint32_t ESTD : 1; /*!< [3..3] S-Cache Tag dirty line invalidate status */ + __IOM uint32_t EST2 : 1; /*!< [4..4] S-Cache Tag 2bit error status */ + uint32_t : 27; + } SCAEDST_b; + }; + + union + { + __IOM uint32_t SCATAA; /*!< (@ 0x00000054) S-Cache Test Access Address */ + + struct + { + uint32_t : 2; + __IOM uint32_t OFFSET : 3; /*!< [4..2] address offset */ + __IOM uint32_t ENTRY : 7; /*!< [11..5] address entry */ + uint32_t : 4; + __IOM uint32_t TARGET : 3; /*!< [18..16] access target */ + uint32_t : 4; + __IOM uint32_t RW : 1; /*!< [23..23] read write */ + uint32_t : 6; + __IOM uint32_t WAY : 2; /*!< [31..30] address way */ + } SCATAA_b; + }; + + union + { + __IOM uint32_t SCATAD; /*!< (@ 0x00000058) C-Cache Test Access Data */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Cache data */ + } SCATAD_b; + }; + __IM uint32_t RESERVED3[105]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 2; + __IOM uint32_t ECCMOD1 : 1; /*!< [3..3] ECC enable */ + __IOM uint32_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint32_t : 27; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] SRAM0 Register Security Attribution */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] SRAM1 Register Security Attribution */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] SRAM2 Register Security Attribution */ + __IOM uint32_t SRAMSA3 : 1; /*!< [3..3] SRAM3 Register Security Attribution */ + uint32_t : 4; + __IOM uint32_t SRAMWTSA : 1; /*!< [8..8] Security attribution for SRAMWTSC */ + uint32_t : 23; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA0 : 1; /*!< [0..0] DTC0 Security Attribution */ + uint32_t : 15; + __IOM uint32_t DTCSTSA1 : 1; /*!< [16..16] DTC1 Security Attribution */ + uint32_t : 15; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA0 : 1; /*!< [0..0] DMAC0 DMAST Security Attribution */ + uint32_t : 15; + __IOM uint32_t DMASTSA1 : 1; /*!< [16..16] DMAC1 DMAST Security Attribution */ + uint32_t : 15; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) Interrupt Controller Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t SAIRQCR0 : 1; /*!< [0..0] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR1 : 1; /*!< [1..1] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR2 : 1; /*!< [2..2] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR3 : 1; /*!< [3..3] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR4 : 1; /*!< [4..4] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR5 : 1; /*!< [5..5] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR6 : 1; /*!< [6..6] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR7 : 1; /*!< [7..7] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR8 : 1; /*!< [8..8] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR9 : 1; /*!< [9..9] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR10 : 1; /*!< [10..10] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR11 : 1; /*!< [11..11] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR12 : 1; /*!< [12..12] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR13 : 1; /*!< [13..13] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR14 : 1; /*!< [14..14] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR15 : 1; /*!< [15..15] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR16 : 1; /*!< [16..16] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR17 : 1; /*!< [17..17] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR18 : 1; /*!< [18..18] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR19 : 1; /*!< [19..19] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR20 : 1; /*!< [20..20] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR21 : 1; /*!< [21..21] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR22 : 1; /*!< [22..22] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR23 : 1; /*!< [23..23] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR24 : 1; /*!< [24..24] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR25 : 1; /*!< [25..25] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR26 : 1; /*!< [26..26] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR27 : 1; /*!< [27..27] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR28 : 1; /*!< [28..28] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR29 : 1; /*!< [29..29] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR30 : 1; /*!< [30..30] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + __IOM uint32_t SAIRQCR31 : 1; /*!< [31..31] Security attributes of registers for the IRQCR, WUPEN0, + * WUPEN1 registers */ + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) Interrupt Controller Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t SANMI0 : 1; /*!< [0..0] Security Attributes of registers */ + __IOM uint32_t SANMI1 : 1; /*!< [1..1] Security Attributes of registers */ + __IOM uint32_t SANMI2 : 1; /*!< [2..2] Security Attributes of registers */ + uint32_t : 29; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) Interrupt Controller Unit Security Attribution + * Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security attributes of registers for WUPEN0.b16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b19 */ + __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security attributes of registers for WUPEN0.b20 */ + uint32_t : 3; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security attributes of registers for WUPEN0.b24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security attributes of registers for WUPEN0.b25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security attributes of registers for WUPEN0.b27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security attributes of registers for WUPEN0.b28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security attributes of registers for WUPEN0.b29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security attributes of registers for WUPEN0.b30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security attributes of registers for WUPEN0.b31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) Interrupt Controller Unit Security Attribution + * Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b3 */ + uint32_t : 3; + __IOM uint32_t SASOSCWUP : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b7 */ + __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b8 */ + __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b9 */ + __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security attributes of registers for WUPEN1.b10 */ + __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security attributes of registers for WUPEN1.b11 */ + __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security attributes of registers for WUPEN1.b12 */ + __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security attributes of registers for WUPEN1.b13 */ + __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security attributes of registers for WUPEN1.b14 */ + __IOM uint32_t SAPDMWUP : 1; /*!< [15..15] Security attributes of registers for WUPEN1.b15 */ + uint32_t : 16; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) Interrupt Controller Unit Security Attribution + * Register G */ + + struct + { + __IOM uint32_t SAIELSR0 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR1 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR2 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR3 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR4 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR5 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR6 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR7 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR8 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR9 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR10 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR11 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR12 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR13 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR14 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR15 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR16 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR17 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR18 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR19 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR20 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR21 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR22 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR23 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR24 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR25 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR26 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR27 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR28 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR29 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR30 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting0 */ + __IOM uint32_t SAIELSR31 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) Interrupt Controller Unit Security Attribution + * Register H */ + + struct + { + __IOM uint32_t SAIELSR32 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR33 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR34 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR35 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR36 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR37 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR38 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR39 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR40 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR41 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR42 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR43 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR44 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR45 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR46 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR47 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR48 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR49 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR50 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR51 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR52 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR53 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR54 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR55 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR56 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR57 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR58 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR59 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR60 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR61 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR62 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting1 */ + __IOM uint32_t SAIELSR63 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting1 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) Interrupt Controller Unit Security Attribution + * Register I */ + + struct + { + __IOM uint32_t SAIELSR64 : 1; /*!< [0..0] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR65 : 1; /*!< [1..1] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR66 : 1; /*!< [2..2] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR67 : 1; /*!< [3..3] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR68 : 1; /*!< [4..4] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR69 : 1; /*!< [5..5] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR70 : 1; /*!< [6..6] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR71 : 1; /*!< [7..7] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR72 : 1; /*!< [8..8] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR73 : 1; /*!< [9..9] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR74 : 1; /*!< [10..10] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR75 : 1; /*!< [11..11] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR76 : 1; /*!< [12..12] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR77 : 1; /*!< [13..13] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR78 : 1; /*!< [14..14] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR79 : 1; /*!< [15..15] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR80 : 1; /*!< [16..16] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR81 : 1; /*!< [17..17] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR82 : 1; /*!< [18..18] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR83 : 1; /*!< [19..19] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR84 : 1; /*!< [20..20] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR85 : 1; /*!< [21..21] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR86 : 1; /*!< [22..22] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR87 : 1; /*!< [23..23] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR88 : 1; /*!< [24..24] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR89 : 1; /*!< [25..25] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR90 : 1; /*!< [26..26] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR91 : 1; /*!< [27..27] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR92 : 1; /*!< [28..28] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR93 : 1; /*!< [29..29] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR94 : 1; /*!< [30..30] Security attributes of registers for ICU0 event link + * setting2 */ + __IOM uint32_t SAIELSR95 : 1; /*!< [31..31] Security attributes of registers for ICU0 event link + * setting2 */ + } ICUSARI_b; + }; + + union + { + __IOM uint32_t ICUSARJ; /*!< (@ 0x0000007C) Interrupt Controller Unit Security Attribution + * Register J */ + + struct + { + __IOM uint32_t SAIELSR0 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR1 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR2 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR3 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR4 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR5 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR6 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR7 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR8 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR9 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR10 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR11 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR12 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR13 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR14 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR15 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR16 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR17 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR18 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR19 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR20 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR21 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR22 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR23 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR24 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR25 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR26 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR27 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR28 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR29 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR30 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting0 */ + __IOM uint32_t SAIELSR31 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting0 */ + } ICUSARJ_b; + }; + + union + { + __IOM uint32_t ICUSARK; /*!< (@ 0x00000080) Interrupt Controller Unit Security Attribution + * Register K */ + + struct + { + __IOM uint32_t SAIELSR32 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR33 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR34 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR35 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR36 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR37 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR38 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR39 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR40 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR41 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR42 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR43 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR44 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR45 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR46 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR47 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR48 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR49 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR50 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR51 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR52 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR53 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR54 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR55 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR56 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR57 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR58 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR59 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR60 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR61 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR62 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting1 */ + __IOM uint32_t SAIELSR63 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting1 */ + } ICUSARK_b; + }; + + union + { + __IOM uint32_t ICUSARL; /*!< (@ 0x00000084) Interrupt Controller Unit Security Attribution + * Register L */ + + struct + { + __IOM uint32_t SAIELSR64 : 1; /*!< [0..0] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR65 : 1; /*!< [1..1] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR66 : 1; /*!< [2..2] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR67 : 1; /*!< [3..3] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR68 : 1; /*!< [4..4] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR69 : 1; /*!< [5..5] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR70 : 1; /*!< [6..6] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR71 : 1; /*!< [7..7] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR72 : 1; /*!< [8..8] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR73 : 1; /*!< [9..9] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR74 : 1; /*!< [10..10] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR75 : 1; /*!< [11..11] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR76 : 1; /*!< [12..12] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR77 : 1; /*!< [13..13] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR78 : 1; /*!< [14..14] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR79 : 1; /*!< [15..15] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR80 : 1; /*!< [16..16] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR81 : 1; /*!< [17..17] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR82 : 1; /*!< [18..18] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR83 : 1; /*!< [19..19] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR84 : 1; /*!< [20..20] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR85 : 1; /*!< [21..21] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR86 : 1; /*!< [22..22] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR87 : 1; /*!< [23..23] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR88 : 1; /*!< [24..24] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR89 : 1; /*!< [25..25] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR90 : 1; /*!< [26..26] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR91 : 1; /*!< [27..27] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR92 : 1; /*!< [28..28] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR93 : 1; /*!< [29..29] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR94 : 1; /*!< [30..30] Security attributes of registers for ICU1 event link + * setting2 */ + __IOM uint32_t SAIELSR95 : 1; /*!< [31..31] Security attributes of registers for ICU1 event link + * setting2 */ + } ICUSARL_b; + }; + __IM uint32_t RESERVED4[30]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] Bus Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] Bus Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t BUSSARC; /*!< (@ 0x00000110) Bus Security Attribution Register C */ + + struct + { + __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0 */ + uint32_t : 31; + } BUSSARC_b; + }; + + union + { + __IOM uint32_t BUSPARC; /*!< (@ 0x00000114) Bus Privileged Attribution Register C */ + + struct + { + __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution */ + uint32_t : 31; + } BUSPARC_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IM uint32_t NMISR; /*!< (@ 0x00000120) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint32_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Status Flag */ + __IM uint32_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Status Flag */ + __IM uint32_t PVD1ST : 1; /*!< [2..2] Voltage Monitor 1 Interrupt Status Flag */ + __IM uint32_t PVD2ST : 1; /*!< [3..3] Voltage Monitor 2 Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t SOSTST : 1; /*!< [5..5] Sub Oscillation Stop Detection Interrupt Status Flag */ + __IM uint32_t OSTST : 1; /*!< [6..6] Main Clock Oscillation Stop Detection Interrupt Status + * Flag */ + __IM uint32_t NMIST : 1; /*!< [7..7] NMI Pin Interrupt Status Flag */ + uint32_t : 4; + __IM uint32_t BUSST : 1; /*!< [12..12] Bus Error Interrupt Status Flag */ + __IM uint32_t CMST : 1; /*!< [13..13] Common Memory Error Interrupt Status Flag */ + __IM uint32_t LMST : 1; /*!< [14..14] Local Memory Error Interrupt Status Flag */ + __IM uint32_t LUST : 1; /*!< [15..15] LockUp Error Interrupt Status Flag */ + __IM uint32_t FPUEXCST : 1; /*!< [16..16] FPU Exception Interrupt Status Flag */ + __IM uint32_t MRCRDST : 1; /*!< [17..17] MRAM MRC read Error Interrupt Status Flag */ + __IM uint32_t MRERDST : 1; /*!< [18..18] MRAM MRE read Error Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t IPCST : 1; /*!< [20..20] IPC NMI CPU mutual Interrupt Status Flag */ + uint32_t : 11; + } NMISR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUASA0 : 1; /*!< [0..0] MMPUA0 Security Attribution */ + __IOM uint32_t MMPUASA1 : 1; /*!< [1..1] MMPUA1 Security Attribution */ + __IOM uint32_t MMPUASA2 : 1; /*!< [2..2] MMPUA2 Security Attribution */ + __IOM uint32_t MMPUASA3 : 1; /*!< [3..3] MMPUA3 Security Attribution */ + __IOM uint32_t MMPUASA4 : 1; /*!< [4..4] MMPUA4 Security Attribution */ + __IOM uint32_t MMPUASA5 : 1; /*!< [5..5] MMPUA5 Security Attribution */ + __IOM uint32_t MMPUASA6 : 1; /*!< [6..6] MMPUA6 Security Attribution */ + __IOM uint32_t MMPUASA7 : 1; /*!< [7..7] MMPUA7 Security Attribution */ + __IOM uint32_t MMPUASA8 : 1; /*!< [8..8] MMPUA8 Security Attribution */ + __IOM uint32_t MMPUASA9 : 1; /*!< [9..9] MMPUA9 Security Attribution */ + __IOM uint32_t MMPUASA10 : 1; /*!< [10..10] MMPUA10 Security Attribution */ + __IOM uint32_t MMPUASA11 : 1; /*!< [11..11] MMPUA11 Security Attribution */ + __IOM uint32_t MMPUASA12 : 1; /*!< [12..12] MMPUA12 Security Attribution */ + __IOM uint32_t MMPUASA13 : 1; /*!< [13..13] MMPUA13 Security Attribution */ + __IOM uint32_t MMPUASA14 : 1; /*!< [14..14] MMPUA14 Security Attribution */ + __IOM uint32_t MMPUASA15 : 1; /*!< [15..15] MMPUA15 Security Attribution */ + __IOM uint32_t MMPUASA16 : 1; /*!< [16..16] MMPUA16 Security Attribution */ + __IOM uint32_t MMPUASA17 : 1; /*!< [17..17] MMPUA17 Security Attribution */ + __IOM uint32_t MMPUASA18 : 1; /*!< [18..18] MMPUA18 Security Attribution */ + __IOM uint32_t MMPUASA19 : 1; /*!< [19..19] MMPUA19 Security Attribution */ + __IOM uint32_t MMPUASA20 : 1; /*!< [20..20] MMPUA20 Security Attribution */ + __IOM uint32_t MMPUASA21 : 1; /*!< [21..21] MMPUA21 Security Attribution */ + __IOM uint32_t MMPUASA22 : 1; /*!< [22..22] MMPUA22 Security Attribution */ + __IOM uint32_t MMPUASA23 : 1; /*!< [23..23] MMPUA23 Security Attribution */ + __IOM uint32_t MMPUASA24 : 1; /*!< [24..24] MMPUA24 Security Attribution */ + __IOM uint32_t MMPUASA25 : 1; /*!< [25..25] MMPUA25 Security Attribution */ + __IOM uint32_t MMPUASA26 : 1; /*!< [26..26] MMPUA26 Security Attribution */ + __IOM uint32_t MMPUASA27 : 1; /*!< [27..27] MMPUA27 Security Attribution */ + __IOM uint32_t MMPUASA28 : 1; /*!< [28..28] MMPUA28 Security Attribution */ + __IOM uint32_t MMPUASA29 : 1; /*!< [29..29] MMPUA29 Security Attribution */ + __IOM uint32_t MMPUASA30 : 1; /*!< [30..30] MMPUA30 Security Attribution */ + __IOM uint32_t MMPUASA31 : 1; /*!< [31..31] MMPUA31 Security Attribution */ + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUBSA0 : 1; /*!< [0..0] MMPUB0 Security Attribution */ + __IOM uint32_t MMPUBSA1 : 1; /*!< [1..1] MMPUB1 Security Attribution */ + __IOM uint32_t MMPUBSA2 : 1; /*!< [2..2] MMPUB2 Security Attribution */ + __IOM uint32_t MMPUBSA3 : 1; /*!< [3..3] MMPUB3 Security Attribution */ + __IOM uint32_t MMPUBSA4 : 1; /*!< [4..4] MMPUB4 Security Attribution */ + __IOM uint32_t MMPUBSA5 : 1; /*!< [5..5] MMPUB5 Security Attribution */ + __IOM uint32_t MMPUBSA6 : 1; /*!< [6..6] MMPUB6 Security Attribution */ + __IOM uint32_t MMPUBSA7 : 1; /*!< [7..7] MMPUB7 Security Attribution */ + __IOM uint32_t MMPUBSA8 : 1; /*!< [8..8] MMPUB8 Security Attribution */ + __IOM uint32_t MMPUBSA9 : 1; /*!< [9..9] MMPUB9 Security Attribution */ + __IOM uint32_t MMPUBSA10 : 1; /*!< [10..10] MMPUB10 Security Attribution */ + __IOM uint32_t MMPUBSA11 : 1; /*!< [11..11] MMPUB11 Security Attribution */ + __IOM uint32_t MMPUBSA12 : 1; /*!< [12..12] MMPUB12 Security Attribution */ + __IOM uint32_t MMPUBSA13 : 1; /*!< [13..13] MMPUB13 Security Attribution */ + __IOM uint32_t MMPUBSA14 : 1; /*!< [14..14] MMPUB14 Security Attribution */ + __IOM uint32_t MMPUBSA15 : 1; /*!< [15..15] MMPUB15 Security Attribution */ + __IOM uint32_t MMPUBSA16 : 1; /*!< [16..16] MMPUB16 Security Attribution */ + __IOM uint32_t MMPUBSA17 : 1; /*!< [17..17] MMPUB17 Security Attribution */ + __IOM uint32_t MMPUBSA18 : 1; /*!< [18..18] MMPUB18 Security Attribution */ + __IOM uint32_t MMPUBSA19 : 1; /*!< [19..19] MMPUB19 Security Attribution */ + __IOM uint32_t MMPUBSA20 : 1; /*!< [20..20] MMPUB20 Security Attribution */ + __IOM uint32_t MMPUBSA21 : 1; /*!< [21..21] MMPUB21 Security Attribution */ + __IOM uint32_t MMPUBSA22 : 1; /*!< [22..22] MMPUB22 Security Attribution */ + __IOM uint32_t MMPUBSA23 : 1; /*!< [23..23] MMPUB23 Security Attribution */ + __IOM uint32_t MMPUBSA24 : 1; /*!< [24..24] MMPUB24 Security Attribution */ + __IOM uint32_t MMPUBSA25 : 1; /*!< [25..25] MMPUB25 Security Attribution */ + __IOM uint32_t MMPUBSA26 : 1; /*!< [26..26] MMPUB26 Security Attribution */ + __IOM uint32_t MMPUBSA27 : 1; /*!< [27..27] MMPUB27 Security Attribution */ + __IOM uint32_t MMPUBSA28 : 1; /*!< [28..28] MMPUB28 Security Attribution */ + __IOM uint32_t MMPUBSA29 : 1; /*!< [29..29] MMPUB29 Security Attribution */ + __IOM uint32_t MMPUBSA30 : 1; /*!< [30..30] MMPUB30 Security Attribution */ + __IOM uint32_t MMPUBSA31 : 1; /*!< [31..31] MMPUB31 Security Attribution */ + } MMPUSARB_b; + }; + __IM uint32_t RESERVED8[14]; + + union + { + __IOM uint32_t CPUSAR; /*!< (@ 0x00000170) CPU Security Attribution Register */ + + struct + { + __IOM uint32_t CPUSA0 : 1; /*!< [0..0] CPU Security Attribution 0 */ + __IOM uint32_t CPUSA1 : 1; /*!< [1..1] CPU Security Attribution 1 */ + uint32_t : 30; + } CPUSAR_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t DEBUGSAR; /*!< (@ 0x00000180) Debug Security Attribution Register */ + + struct + { + __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Security Attribution 0 */ + uint32_t : 31; + } DEBUGSAR_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMAC channel Security Attribution Register */ + + struct + { + __IOM uint32_t SADMAC00 : 1; /*!< [0..0] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC01 : 1; /*!< [1..1] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC02 : 1; /*!< [2..2] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC03 : 1; /*!< [3..3] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC04 : 1; /*!< [4..4] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC05 : 1; /*!< [5..5] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC06 : 1; /*!< [6..6] Security attributes of registers for DMAC0 channel */ + __IOM uint32_t SADMAC07 : 1; /*!< [7..7] Security attributes of registers for DMAC0 channel */ + uint32_t : 8; + __IOM uint32_t SADMAC10 : 1; /*!< [16..16] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC11 : 1; /*!< [17..17] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC12 : 1; /*!< [18..18] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC13 : 1; /*!< [19..19] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC14 : 1; /*!< [20..20] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC15 : 1; /*!< [21..21] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC16 : 1; /*!< [22..22] Security attributes of registers for DMAC1 channel */ + __IOM uint32_t SADMAC17 : 1; /*!< [23..23] Security attributes of registers for DMAC1 channel */ + uint32_t : 8; + } DMACCHSAR_b; + }; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; + __IM uint32_t RESERVED12[15]; + + union + { + __IOM uint32_t DMACCHPAR; /*!< (@ 0x000001F0) DMA Channel Privilege Attribution Register */ + + struct + { + __IOM uint32_t PADMAC00 : 1; /*!< [0..0] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC01 : 1; /*!< [1..1] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC02 : 1; /*!< [2..2] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC03 : 1; /*!< [3..3] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC04 : 1; /*!< [4..4] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC05 : 1; /*!< [5..5] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC06 : 1; /*!< [6..6] Privilege attributes of outputs and registers for DMAC0 + * channel */ + __IOM uint32_t PADMAC07 : 1; /*!< [7..7] Privilege attributes of outputs and registers for DMAC0 + * channel */ + uint32_t : 8; + __IOM uint32_t PADMAC10 : 1; /*!< [16..16] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC11 : 1; /*!< [17..17] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC12 : 1; /*!< [18..18] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC13 : 1; /*!< [19..19] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC14 : 1; /*!< [20..20] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC15 : 1; /*!< [21..21] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC16 : 1; /*!< [22..22] Privilege attributes of outputs and registers for DMAC1 + * channel */ + __IOM uint32_t PADMAC17 : 1; /*!< [23..23] Privilege attributes of outputs and registers for DMAC1 + * channel */ + uint32_t : 8; + } DMACCHPAR_b; + }; + __IM uint32_t RESERVED13[131]; + + union + { + __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR0_b; + }; + + union + { + __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR1_b; + }; + + union + { + __IOM uint32_t SRAMSABAR2; /*!< (@ 0x00000408) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR2_b; + }; + + union + { + __IOM uint32_t SRAMSABAR3; /*!< (@ 0x0000040C) SRAM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure */ + uint32_t : 11; + } SRAMSABAR3_b; + }; + __IM uint32_t RESERVED14[60]; + + union + { + __IOM uint32_t CACHESAR; /*!< (@ 0x00000500) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security attributes of registers for CACHE Control */ + uint32_t : 1; + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security attributes of registers for CACHE Error */ + uint32_t : 29; + } CACHESAR_b; + }; + + union + { + __IOM uint32_t TCMSAR; /*!< (@ 0x00000504) TCM Security Attribution Register */ + + struct + { + __IOM uint32_t TCMSA : 1; /*!< [0..0] Security attributes of registers for TCM Control */ + uint32_t : 31; + } TCMSAR_b; + }; + + union + { + __IOM uint32_t TCMSABARC; /*!< (@ 0x00000508) TCM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t TCMSABA : 6; /*!< [18..13] Boundary address between secure and non-secure. (Start + * address of non-secure region) */ + uint32_t : 13; + } TCMSABARC_b; + }; + + union + { + __IOM uint32_t TCMSABARS; /*!< (@ 0x0000050C) TCM Security Attribute Boundary Address Register */ + + struct + { + uint32_t : 13; + __IOM uint32_t TCMSABA : 6; /*!< [18..13] Boundary address between secure and non-secure. (Start + * address of non-secure region) */ + uint32_t : 13; + } TCMSABARS_b; + }; + + union + { + __IOM uint32_t SRAMESAR; /*!< (@ 0x00000510) SRAM ECC region Security Attribute Register */ + + struct + { + __IOM uint32_t SRAMESA : 1; /*!< [0..0] ECC region Security Attribution */ + uint32_t : 31; + } SRAMESAR_b; + }; + __IM uint32_t RESERVED15[59]; + + union + { + __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */ + + struct + { + __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for ELC */ + __IOM uint32_t TEVTEICU0 : 1; /*!< [1..1] Trusted Event Route Control Register for ICU0 */ + __IOM uint32_t TEVTEICU1 : 1; /*!< [2..2] Trusted Event Route Control Register for ICU1 */ + uint32_t : 29; + } TEVTRCR_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t IPCSAR; /*!< (@ 0x00000610) IPC Security Attribution Register */ + + struct + { + __IOM uint32_t SAIPCSEM0 : 1; /*!< [0..0] Security attributes of registers for IPCSEMn */ + __IOM uint32_t SAIPCSEM1 : 1; /*!< [1..1] Security attributes of registers for IPCSEMn */ + uint32_t : 6; + __IOM uint32_t SAIPCNMI0 : 1; /*!< [8..8] Security attributes of the registers */ + __IOM uint32_t SAIPCNMI1 : 1; /*!< [9..9] Security attributes of the registers */ + uint32_t : 6; + __IOM uint32_t SAIPCIR0 : 1; /*!< [16..16] Security attributes of registers for IPC0STA0, IPC0ISET0, + * IPC0TXD0, IPC0RXD0 and IPC0CLR0 */ + __IOM uint32_t SAIPCIR1 : 1; /*!< [17..17] Security attributes of registers for IPC0STA1, IPC0ISET1, + * IPC0TXD1, IPC0RXD1 and IPC0CLR1 */ + __IOM uint32_t SAIPCIR2 : 1; /*!< [18..18] Security attributes of registers for IPC1STA0, IPC1ISET0, + * IPC1TXD0, IPC1RXD0 and IPC1CLR0 */ + __IOM uint32_t SAIPCIR3 : 1; /*!< [19..19] Security attributes of registers for IPC1STA1, IPC1ISET1, + * IPC1TXD1, IPC1RXD1 and IPC1CLR1 */ + uint32_t : 12; + } IPCSAR_b; + }; + + union + { + __IOM uint32_t IPCPAR; /*!< (@ 0x00000614) IPC Privileged Attribution Register */ + + struct + { + __IOM uint32_t PAIPCSEM0 : 1; /*!< [0..0] Privileged attributes of registers for IPCSEMn */ + __IOM uint32_t PAIPCSEM1 : 1; /*!< [1..1] Privileged attributes of registers for IPCSEMn */ + uint32_t : 6; + __IOM uint32_t PAIPCNMI0 : 1; /*!< [8..8] Privileged attributes of registers */ + __IOM uint32_t PAIPCNMI1 : 1; /*!< [9..9] Privileged attributes of registers */ + uint32_t : 6; + __IOM uint32_t PAIPCIR0 : 1; /*!< [16..16] Privileged attributes of registers for IPC0STA0, IPC0ISET0, + * IPC0TXD0, IPC0RXD0 and IPC0CLR0 */ + __IOM uint32_t PAIPCIR1 : 1; /*!< [17..17] Privileged attributes of registers for IPC0STA1, IPC0ISET1, + * IPC0TXD1, IPC0RXD1 and IPC0CLR1 */ + __IOM uint32_t PAIPCIR2 : 1; /*!< [18..18] Privileged attributes of registers for IPC1STA0, IPC1ISET0, + * IPC1TXD0, IPC1RXD0 and IPC1CLR0 */ + __IOM uint32_t PAIPCIR3 : 1; /*!< [19..19] Privileged attributes of registers for IPC1STA1, IPC1ISET1, + * IPC1TXD1, IPC1RXD1 and IPC1CLR1 */ + uint32_t : 12; + } IPCPAR_b; + }; +} R_CPSCU_Type; /*!< Size = 1560 (0x618) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit A/D Converter (R_ADC_B0) + */ + +typedef struct /*!< (@ 0x40338000) R_ADC_B0 Structure */ +{ + union + { + __IOM uint32_t ADCLKENR; /*!< (@ 0x00000000) A/D Conversion Clock Enable Register */ + + struct + { + __IOM uint32_t CLKEN : 1; /*!< [0..0] ADCLK Operating Enable bit */ + uint32_t : 31; + } ADCLKENR_b; + }; + + union + { + __IM uint32_t ADCLKSR; /*!< (@ 0x00000004) A/D Conversion Clock Status Register */ + + struct + { + __IM uint32_t CLKSR : 1; /*!< [0..0] ADCLK status bit */ + uint32_t : 31; + } ADCLKSR_b; + }; + + union + { + __IOM uint32_t ADCLKCR; /*!< (@ 0x00000008) A/D Conversion Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select */ + uint32_t : 14; + __IOM uint32_t DIVR : 3; /*!< [18..16] Clock Division Ratio Select */ + uint32_t : 13; + } ADCLKCR_b; + }; + + union + { + __IOM uint32_t ADSYCR; /*!< (@ 0x0000000C) A/D Converter Synchronous Operation Control Register */ + + struct + { + __IOM uint32_t ADSYCYC : 11; /*!< [10..0] A/D Converter Synchronous Operation Period Cycle */ + uint32_t : 5; + __IOM uint32_t ADSYDIS0 : 1; /*!< [16..16] ADC0 Synchronous Operation Select */ + __IOM uint32_t ADSYDIS1 : 1; /*!< [17..17] ADC1 Synchronous Operation Select */ + uint32_t : 14; + } ADSYCR_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t ADERINTCR; /*!< (@ 0x00000020) A/D Conversion Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADEIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Error Interrupt Enable */ + __IOM uint32_t ADEIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Error Interrupt Enable */ + uint32_t : 30; + } ADERINTCR_b; + }; + + union + { + __IOM uint32_t ADOVFINTCR; /*!< (@ 0x00000024) A/D Conversion Overflow Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADOVFIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Overflow Interrupt Enable */ + __IOM uint32_t ADOVFIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Overflow Interrupt Enable */ + uint32_t : 30; + } ADOVFINTCR_b; + }; + + union + { + __IOM uint32_t ADCALINTCR; /*!< (@ 0x00000028) Calibration interrupt Enable Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CALENDIE0 : 1; /*!< [16..16] ADC0 Calibration End Interrupt Enable */ + __IOM uint32_t CALENDIE1 : 1; /*!< [17..17] ADC1 Calibration End Interrupt Enable */ + uint32_t : 14; + } ADCALINTCR_b; + }; + __IM uint32_t RESERVED1[5]; + + union + { + __IOM uint32_t ADMDR; /*!< (@ 0x00000040) A/D Converter Mode Selection Register */ + + struct + { + __IOM uint32_t ADMD0 : 4; /*!< [3..0] ADC0 Mode Selection */ + uint32_t : 4; + __IOM uint32_t ADMD1 : 4; /*!< [11..8] ADC1 Mode Selection */ + uint32_t : 20; + } ADMDR_b; + }; + + union + { + __IOM uint32_t ADGSPCR; /*!< (@ 0x00000044) A/D Group scan Priority Control Register */ + + struct + { + __IOM uint32_t PGS0 : 1; /*!< [0..0] ADC0 Group Priority Control Setting */ + __IOM uint32_t RSCN0 : 1; /*!< [1..1] ADC0 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS0 : 1; /*!< [2..2] ADC0 Group Priority Control Setting 3 */ + __IOM uint32_t GRP0 : 1; /*!< [3..3] ADC0 Group Priority Control Setting 4 */ + uint32_t : 4; + __IOM uint32_t PGS1 : 1; /*!< [8..8] ADC1 Group Priority Control Setting */ + __IOM uint32_t RSCN1 : 1; /*!< [9..9] ADC1 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS1 : 1; /*!< [10..10] ADC1 Group Priority Control Setting 3 */ + __IOM uint32_t GRP1 : 1; /*!< [11..11] ADC1 Group Priority Control Setting 4 */ + uint32_t : 20; + } ADGSPCR_b; + }; + + union + { + __IOM uint32_t ADSGER; /*!< (@ 0x00000048) Scan Group Enable Register */ + + struct + { + __IOM uint32_t SGREn : 9; /*!< [8..0] Scan Group n Enable */ + uint32_t : 23; + } ADSGER_b; + }; + + union + { + __IOM uint32_t ADSGCR0; /*!< (@ 0x0000004C) Scan Group Control Register 0 */ + + struct + { + __IOM uint32_t SGADS0 : 2; /*!< [1..0] Scan Group 0 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS1 : 2; /*!< [9..8] Scan Group 1 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS2 : 2; /*!< [17..16] Scan Group 2 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS3 : 2; /*!< [25..24] Scan Group 3 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR0_b; + }; + + union + { + __IOM uint32_t ADSGCR1; /*!< (@ 0x00000050) Scan Group Control Register 1 */ + + struct + { + __IOM uint32_t SGADS4 : 2; /*!< [1..0] Scan Group 4 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS5 : 2; /*!< [9..8] Scan Group 5 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS6 : 2; /*!< [17..16] Scan Group 6 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS7 : 2; /*!< [25..24] Scan Group 7 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR1_b; + }; + + union + { + __IOM uint32_t ADSGCR2; /*!< (@ 0x00000054) Scan Group Control Register 2 */ + + struct + { + __IOM uint32_t SGADS8 : 2; /*!< [1..0] Scan Group 8 A/D Converter Selection */ + uint32_t : 30; + } ADSGCR2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ADINTCR; /*!< (@ 0x0000005C) Scan End Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADIEn : 9; /*!< [8..0] Scan Group n Scan End Interrupt Enable */ + uint32_t : 23; + } ADINTCR_b; + }; + __IM uint32_t RESERVED3[24]; + + union + { + __IOM uint32_t ADTRGEXT0; /*!< (@ 0x000000C0) External Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT0_b; + }; + + union + { + __IOM uint32_t ADTRGELC0; /*!< (@ 0x000000C4) ELC Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC0_b; + }; + + union + { + __IOM uint32_t ADTRGGPT0; /*!< (@ 0x000000C8) GPT Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT0_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ADTRGEXT1; /*!< (@ 0x000000D0) External Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT1_b; + }; + + union + { + __IOM uint32_t ADTRGELC1; /*!< (@ 0x000000D4) ELC Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC1_b; + }; + + union + { + __IOM uint32_t ADTRGGPT1; /*!< (@ 0x000000D8) GPT Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT1_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t ADTRGEXT2; /*!< (@ 0x000000E0) External Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT2_b; + }; + + union + { + __IOM uint32_t ADTRGELC2; /*!< (@ 0x000000E4) ELC Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC2_b; + }; + + union + { + __IOM uint32_t ADTRGGPT2; /*!< (@ 0x000000E8) GPT Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT2_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t ADTRGEXT3; /*!< (@ 0x000000F0) External Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT3_b; + }; + + union + { + __IOM uint32_t ADTRGELC3; /*!< (@ 0x000000F4) ELC Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC3_b; + }; + + union + { + __IOM uint32_t ADTRGGPT3; /*!< (@ 0x000000F8) GPT Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT3_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ADTRGEXT4; /*!< (@ 0x00000100) External Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT4_b; + }; + + union + { + __IOM uint32_t ADTRGELC4; /*!< (@ 0x00000104) ELC Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC4_b; + }; + + union + { + __IOM uint32_t ADTRGGPT4; /*!< (@ 0x00000108) GPT Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT4_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ADTRGEXT5; /*!< (@ 0x00000110) External Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT5_b; + }; + + union + { + __IOM uint32_t ADTRGELC5; /*!< (@ 0x00000114) ELC Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC5_b; + }; + + union + { + __IOM uint32_t ADTRGGPT5; /*!< (@ 0x00000118) GPT Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT5_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t ADTRGEXT6; /*!< (@ 0x00000120) External Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT6_b; + }; + + union + { + __IOM uint32_t ADTRGELC6; /*!< (@ 0x00000124) ELC Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC6_b; + }; + + union + { + __IOM uint32_t ADTRGGPT6; /*!< (@ 0x00000128) GPT Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT6_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t ADTRGEXT7; /*!< (@ 0x00000130) External Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT7_b; + }; + + union + { + __IOM uint32_t ADTRGELC7; /*!< (@ 0x00000134) ELC Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC7_b; + }; + + union + { + __IOM uint32_t ADTRGGPT7; /*!< (@ 0x00000138) GPT Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT7_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t ADTRGEXT8; /*!< (@ 0x00000140) External Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT8_b; + }; + + union + { + __IOM uint32_t ADTRGELC8; /*!< (@ 0x00000144) ELC Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC8_b; + }; + + union + { + __IOM uint32_t ADTRGGPT8; /*!< (@ 0x00000148) GPT Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGGPTAm : 14; /*!< [13..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 2; + __IOM uint32_t TRGGPTBm : 14; /*!< [29..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 2; + } ADTRGGPT8_b; + }; + __IM uint32_t RESERVED12[29]; + + union + { + __IOM uint32_t ADTRGDLR0; /*!< (@ 0x000001C0) A/D Conversion Start Trigger Delay Register 0 */ + + struct + { + __IOM uint32_t TRGDLY0 : 8; /*!< [7..0] Scan Group 0 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY1 : 8; /*!< [23..16] Scan Group 1 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR0_b; + }; + + union + { + __IOM uint32_t ADTRGDLR1; /*!< (@ 0x000001C4) A/D Conversion Start Trigger Delay Register 1 */ + + struct + { + __IOM uint32_t TRGDLY2 : 8; /*!< [7..0] Scan Group 2 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY3 : 8; /*!< [23..16] Scan Group 3 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR1_b; + }; + + union + { + __IOM uint32_t ADTRGDLR2; /*!< (@ 0x000001C8) A/D Conversion Start Trigger Delay Register 2 */ + + struct + { + __IOM uint32_t TRGDLY4 : 8; /*!< [7..0] Scan Group 4 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY5 : 8; /*!< [23..16] Scan Group 5 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR2_b; + }; + + union + { + __IOM uint32_t ADTRGDLR3; /*!< (@ 0x000001CC) A/D Conversion Start Trigger Delay Register 3 */ + + struct + { + __IOM uint32_t TRGDLY6 : 8; /*!< [7..0] Scan Group 6 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY7 : 8; /*!< [23..16] Scan Group 7 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR3_b; + }; + + union + { + __IOM uint32_t ADTRGDLR4; /*!< (@ 0x000001D0) A/D Conversion Start Trigger Delay Register 4 */ + + struct + { + __IOM uint32_t TRGDLY8 : 8; /*!< [7..0] Scan Group 8 Trigger Input Delay Configuration */ + uint32_t : 24; + } ADTRGDLR4_b; + }; + __IM uint32_t RESERVED13[11]; + + union + { + __IOM uint32_t ADSGDCR0; /*!< (@ 0x00000200) Scan Group Diagnosis Function Control Register + * 0 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR0_b; + }; + + union + { + __IOM uint32_t ADSGDCR1; /*!< (@ 0x00000204) Scan Group Diagnosis Function Control Register + * 1 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR1_b; + }; + + union + { + __IOM uint32_t ADSGDCR2; /*!< (@ 0x00000208) Scan Group Diagnosis Function Control Register + * 2 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR2_b; + }; + + union + { + __IOM uint32_t ADSGDCR3; /*!< (@ 0x0000020C) Scan Group Diagnosis Function Control Register + * 3 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR3_b; + }; + + union + { + __IOM uint32_t ADSGDCR4; /*!< (@ 0x00000210) Scan Group Diagnosis Function Control Register + * 4 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR4_b; + }; + + union + { + __IOM uint32_t ADSGDCR5; /*!< (@ 0x00000214) Scan Group Diagnosis Function Control Register + * 5 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR5_b; + }; + + union + { + __IOM uint32_t ADSGDCR6; /*!< (@ 0x00000218) Scan Group Diagnosis Function Control Register + * 6 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR6_b; + }; + + union + { + __IOM uint32_t ADSGDCR7; /*!< (@ 0x0000021C) Scan Group Diagnosis Function Control Register + * 7 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR7_b; + }; + + union + { + __IOM uint32_t ADSGDCR8; /*!< (@ 0x00000220) Scan Group Diagnosis Function Control Register + * 8 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 8; /*!< [31..24] Disconnection Detection Assist Period */ + } ADSGDCR8_b; + }; + __IM uint32_t RESERVED14[7]; + + union + { + __IOM uint32_t ADSSTR0; /*!< (@ 0x00000240) Sampling State Table Register 0 */ + + struct + { + __IOM uint32_t SST0 : 10; /*!< [9..0] Sampling State Table 0 */ + uint32_t : 6; + __IOM uint32_t SST1 : 10; /*!< [25..16] Sampling State Table 1 */ + uint32_t : 6; + } ADSSTR0_b; + }; + + union + { + __IOM uint32_t ADSSTR1; /*!< (@ 0x00000244) Sampling State Table Register 1 */ + + struct + { + __IOM uint32_t SST2 : 10; /*!< [9..0] Sampling State Table 2 */ + uint32_t : 6; + __IOM uint32_t SST3 : 10; /*!< [25..16] Sampling State Table 3 */ + uint32_t : 6; + } ADSSTR1_b; + }; + + union + { + __IOM uint32_t ADSSTR2; /*!< (@ 0x00000248) Sampling State Table Register 2 */ + + struct + { + __IOM uint32_t SST4 : 10; /*!< [9..0] Sampling State Table 4 */ + uint32_t : 6; + __IOM uint32_t SST5 : 10; /*!< [25..16] Sampling State Table 5 */ + uint32_t : 6; + } ADSSTR2_b; + }; + + union + { + __IOM uint32_t ADSSTR3; /*!< (@ 0x0000024C) Sampling State Table Register 3 */ + + struct + { + __IOM uint32_t SST6 : 10; /*!< [9..0] Sampling State Table 6 */ + uint32_t : 6; + __IOM uint32_t SST7 : 10; /*!< [25..16] Sampling State Table 7 */ + uint32_t : 6; + } ADSSTR3_b; + }; + + union + { + __IOM uint32_t ADSSTR4; /*!< (@ 0x00000250) Sampling State Table Register 4 */ + + struct + { + __IOM uint32_t SST8 : 10; /*!< [9..0] Sampling State Table 8 */ + uint32_t : 6; + __IOM uint32_t SST9 : 10; /*!< [25..16] Sampling State Table 9 */ + uint32_t : 6; + } ADSSTR4_b; + }; + + union + { + __IOM uint32_t ADSSTR5; /*!< (@ 0x00000254) Sampling State Table Register 5 */ + + struct + { + __IOM uint32_t SST10 : 10; /*!< [9..0] Sampling State Table 10 */ + uint32_t : 6; + __IOM uint32_t SST11 : 10; /*!< [25..16] Sampling State Table 11 */ + uint32_t : 6; + } ADSSTR5_b; + }; + + union + { + __IOM uint32_t ADSSTR6; /*!< (@ 0x00000258) Sampling State Table Register 6 */ + + struct + { + __IOM uint32_t SST12 : 10; /*!< [9..0] Sampling State Table 12 */ + uint32_t : 6; + __IOM uint32_t SST13 : 10; /*!< [25..16] Sampling State Table 13 */ + uint32_t : 6; + } ADSSTR6_b; + }; + + union + { + __IOM uint32_t ADSSTR7; /*!< (@ 0x0000025C) Sampling State Table Register 7 */ + + struct + { + __IOM uint32_t SST14 : 10; /*!< [9..0] Sampling State Table 14 */ + uint32_t : 6; + __IOM uint32_t SST15 : 10; /*!< [25..16] Sampling State Table 15 */ + uint32_t : 6; + } ADSSTR7_b; + }; + + union + { + __IOM uint32_t ADCNVSTR; /*!< (@ 0x00000260) A/D Conversion State Register */ + + struct + { + __IOM uint32_t CST0 : 6; /*!< [5..0] A/D Converter Unit 0 (ADC0) */ + uint32_t : 2; + __IOM uint32_t CST1 : 6; /*!< [13..8] A/D Converter Unit 1 (ADC1) */ + uint32_t : 18; + } ADCNVSTR_b; + }; + + union + { + __IOM uint32_t ADCALSTCR; /*!< (@ 0x00000264) A/D Converter Calibration State Register */ + + struct + { + __IOM uint32_t CALADSST : 10; /*!< [9..0] A/D Converter Calibration Sampling Time Configuration */ + uint32_t : 6; + __IOM uint32_t CALADCST : 6; /*!< [21..16] A/D Converter Calibration Conversion Time Configuration. */ + uint32_t : 10; + } ADCALSTCR_b; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t ADSHCR0; /*!< (@ 0x00000280) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 0 */ + + struct + { + __IOM uint32_t SHEN0 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 Select */ + __IOM uint32_t SHEN1 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 1 Select */ + __IOM uint32_t SHEN2 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 2 Select */ + uint32_t : 13; + __IOM uint32_t SHMD0 : 1; /*!< [16..16] Channel-dedicated Sample-and-hold Circuit Unit 0 Input + * Mode Select */ + __IOM uint32_t SHMD1 : 1; /*!< [17..17] Channel-dedicated Sample-and-hold Circuit Unit 1 Input + * Mode Select */ + __IOM uint32_t SHMD2 : 1; /*!< [18..18] Channel-dedicated Sample-and-hold Circuit Unit 2 Input + * Mode Select */ + uint32_t : 13; + } ADSHCR0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t ADSHSTR0; /*!< (@ 0x00000288) Channel-Dedicated Sample & Hold Circuit State + * Register 0 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to 2 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to + * 2 */ + uint32_t : 13; + } ADSHSTR0_b; + }; + + union + { + __IOM uint32_t ADSHCR1; /*!< (@ 0x0000028C) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 1 */ + + struct + { + __IOM uint32_t SHEN4 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 Select */ + __IOM uint32_t SHEN5 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 5 Select */ + __IOM uint32_t SHEN6 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 6 Select */ + uint32_t : 13; + __IOM uint32_t SHMD4 : 1; /*!< [16..16] Channel-dedicated Sample-and-hold Circuit Unit 4 Input + * Mode Select */ + __IOM uint32_t SHMD5 : 1; /*!< [17..17] Channel-dedicated Sample-and-hold Circuit Unit 5 Input + * Mode Select */ + __IOM uint32_t SHMD6 : 1; /*!< [18..18] Channel-dedicated Sample-and-hold Circuit Unit 6 Input + * Mode Select */ + uint32_t : 13; + } ADSHCR1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t ADSHSTR1; /*!< (@ 0x00000294) Channel-Dedicated Sample & Hold Circuit State + * Register 1 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to 6 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to + * 6 */ + uint32_t : 13; + } ADSHSTR1_b; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t ADCALSHCR; /*!< (@ 0x000002B0) Channel-Dedicated Sample & Hold Circuit Calibration + * State Register */ + + struct + { + __IOM uint32_t CALSHSST : 8; /*!< [7..0] Channel-Dedicated Sample & Hold Circuit Calibration Sampling + * Time Configuration */ + uint32_t : 8; + __IOM uint32_t CALSHHST : 3; /*!< [18..16] Channel-Dedicated Sample & Hold Circuit Calibration + * Holding Time Configuration */ + uint32_t : 13; + } ADCALSHCR_b; + }; + __IM uint32_t RESERVED19[27]; + + union + { + __IOM uint32_t ADREFCR; /*!< (@ 0x00000320) Internal Reference Voltage Monitor Enable Register */ + + struct + { + __IOM uint32_t VDE : 1; /*!< [0..0] Internal Reference Voltage A/D Conversion Select */ + uint32_t : 31; + } ADREFCR_b; + }; + __IM uint32_t RESERVED20[7]; + + union + { + __IOM uint32_t ADDFSR0; /*!< (@ 0x00000340) A/D Converter Digital Filter Selection Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR0_b; + }; + + union + { + __IOM uint32_t ADDFSR1; /*!< (@ 0x00000344) A/D Converter Digital Filter Selection Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR1_b; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t ADUOFTR0; /*!< (@ 0x00000360) User Offset Table Register 0 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR0_b; + }; + + union + { + __IOM uint32_t ADUOFTR1; /*!< (@ 0x00000364) User Offset Table Register 1 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR1_b; + }; + + union + { + __IOM uint32_t ADUOFTR2; /*!< (@ 0x00000368) User Offset Table Register 2 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR2_b; + }; + + union + { + __IOM uint32_t ADUOFTR3; /*!< (@ 0x0000036C) User Offset Table Register 3 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR3_b; + }; + + union + { + __IOM uint32_t ADUOFTR4; /*!< (@ 0x00000370) User Offset Table Register 4 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR4_b; + }; + + union + { + __IOM uint32_t ADUOFTR5; /*!< (@ 0x00000374) User Offset Table Register 5 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR5_b; + }; + + union + { + __IOM uint32_t ADUOFTR6; /*!< (@ 0x00000378) User Offset Table Register 6 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR6_b; + }; + + union + { + __IOM uint32_t ADUOFTR7; /*!< (@ 0x0000037C) User Offset Table Register 7 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR7_b; + }; + + union + { + __IOM uint32_t ADUGTR0; /*!< (@ 0x00000380) User Gain Table Register 0 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR0_b; + }; + + union + { + __IOM uint32_t ADUGTR1; /*!< (@ 0x00000384) User Gain Table Register 1 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR1_b; + }; + + union + { + __IOM uint32_t ADUGTR2; /*!< (@ 0x00000388) User Gain Table Register 2 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR2_b; + }; + + union + { + __IOM uint32_t ADUGTR3; /*!< (@ 0x0000038C) User Gain Table Register 3 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR3_b; + }; + + union + { + __IOM uint32_t ADUGTR4; /*!< (@ 0x00000390) User Gain Table Register 4 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR4_b; + }; + + union + { + __IOM uint32_t ADUGTR5; /*!< (@ 0x00000394) User Gain Table Register 5 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR5_b; + }; + + union + { + __IOM uint32_t ADUGTR6; /*!< (@ 0x00000398) User Gain Table Register 6 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR6_b; + }; + + union + { + __IOM uint32_t ADUGTR7; /*!< (@ 0x0000039C) User Gain Table Register 7 */ + + struct + { + __IOM uint32_t UGAINF : 14; /*!< [13..0] User Gain Table n - Fractional Gain */ + __IOM uint32_t UGAINI : 2; /*!< [15..14] User Gain Table n - Integer Gain */ + uint32_t : 16; + } ADUGTR7_b; + }; + + union + { + __IOM uint32_t ADLIMINTCR; /*!< (@ 0x000003A0) Limiter Clip Interrupt Enable Register */ + + struct + { + __IOM uint32_t LIMIEn : 9; /*!< [8..0] Limiter Clip Interrupt n Enable bit */ + uint32_t : 23; + } ADLIMINTCR_b; + }; + + union + { + __IOM uint32_t ADLIMTR0; /*!< (@ 0x000003A4) Limiter Clip Table Register 0 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR0_b; + }; + + union + { + __IOM uint32_t ADLIMTR1; /*!< (@ 0x000003A8) Limiter Clip Table Register 1 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR1_b; + }; + + union + { + __IOM uint32_t ADLIMTR2; /*!< (@ 0x000003AC) Limiter Clip Table Register 2 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR2_b; + }; + + union + { + __IOM uint32_t ADLIMTR3; /*!< (@ 0x000003B0) Limiter Clip Table Register 3 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR3_b; + }; + + union + { + __IOM uint32_t ADLIMTR4; /*!< (@ 0x000003B4) Limiter Clip Table Register 4 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR4_b; + }; + + union + { + __IOM uint32_t ADLIMTR5; /*!< (@ 0x000003B8) Limiter Clip Table Register 5 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR5_b; + }; + + union + { + __IOM uint32_t ADLIMTR6; /*!< (@ 0x000003BC) Limiter Clip Table Register 6 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR6_b; + }; + + union + { + __IOM uint32_t ADLIMTR7; /*!< (@ 0x000003C0) Limiter Clip Table Register 7 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR7_b; + }; + __IM uint32_t RESERVED22[15]; + + union + { + __IOM uint32_t ADCMPENR; /*!< (@ 0x00000400) Compare Match Enable Register */ + + struct + { + __IOM uint32_t CMPENn : 8; /*!< [7..0] Compare Match n Enable */ + uint32_t : 24; + } ADCMPENR_b; + }; + + union + { + __IOM uint32_t ADCMPINTCR; /*!< (@ 0x00000404) Compare Match Interrupt Enable Register */ + + struct + { + __IOM uint32_t CMPIEn : 4; /*!< [3..0] Compare Match Interrupt n Enable */ + uint32_t : 28; + } ADCMPINTCR_b; + }; + + union + { + __IOM uint32_t ADCCMPCR0; /*!< (@ 0x00000408) Composite Compare Match Configuration Register + * 0 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR0_b; + }; + + union + { + __IOM uint32_t ADCCMPCR1; /*!< (@ 0x0000040C) Composite Compare Match Configuration Register + * 1 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR1_b; + }; + __IM uint32_t RESERVED23[14]; + + union + { + __IOM uint32_t ADCMPMDR0; /*!< (@ 0x00000448) Compare Match Mode Selection Register 0 */ + + struct + { + __IOM uint32_t CMPMD0 : 2; /*!< [1..0] Compare Match 0 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD1 : 2; /*!< [9..8] Compare Match 1 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD2 : 2; /*!< [17..16] Compare Match 2 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD3 : 2; /*!< [25..24] Compare Match 3 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR0_b; + }; + + union + { + __IOM uint32_t ADCMPMDR1; /*!< (@ 0x0000044C) Compare Match Mode Selection Register 1 */ + + struct + { + __IOM uint32_t CMPMD4 : 2; /*!< [1..0] Compare Match 4 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD5 : 2; /*!< [9..8] Compare Match 5 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD6 : 2; /*!< [17..16] Compare Match 6 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD7 : 2; /*!< [25..24] Compare Match 7 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR1_b; + }; + __IM uint32_t RESERVED24[2]; + + union + { + __IOM uint32_t ADCMPTBR0; /*!< (@ 0x00000458) Compare Match Table Register 0 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR0_b; + }; + + union + { + __IOM uint32_t ADCMPTBR1; /*!< (@ 0x0000045C) Compare Match Table Register 1 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR1_b; + }; + + union + { + __IOM uint32_t ADCMPTBR2; /*!< (@ 0x00000460) Compare Match Table Register 2 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR2_b; + }; + + union + { + __IOM uint32_t ADCMPTBR3; /*!< (@ 0x00000464) Compare Match Table Register 3 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR3_b; + }; + + union + { + __IOM uint32_t ADCMPTBR4; /*!< (@ 0x00000468) Compare Match Table Register 4 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR4_b; + }; + + union + { + __IOM uint32_t ADCMPTBR5; /*!< (@ 0x0000046C) Compare Match Table Register 5 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR5_b; + }; + + union + { + __IOM uint32_t ADCMPTBR6; /*!< (@ 0x00000470) Compare Match Table Register 6 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR6_b; + }; + + union + { + __IOM uint32_t ADCMPTBR7; /*!< (@ 0x00000474) Compare Match Table Register 7 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR7_b; + }; + __IM uint32_t RESERVED25[18]; + + union + { + __IOM uint32_t ADFIFOCR; /*!< (@ 0x000004C0) FIFO Control Register */ + + struct + { + __IOM uint32_t FIFOEN0 : 1; /*!< [0..0] Scan Group 0 FIFO Enable */ + __IOM uint32_t FIFOEN1 : 1; /*!< [1..1] Scan Group 1 FIFO Enable */ + __IOM uint32_t FIFOEN2 : 1; /*!< [2..2] Scan Group 2 FIFO Enable */ + __IOM uint32_t FIFOEN3 : 1; /*!< [3..3] Scan Group 3 FIFO Enable */ + __IOM uint32_t FIFOEN4 : 1; /*!< [4..4] Scan Group 4 FIFO Enable */ + __IOM uint32_t FIFOEN5 : 1; /*!< [5..5] Scan Group 5 FIFO Enable */ + __IOM uint32_t FIFOEN6 : 1; /*!< [6..6] Scan Group 6 FIFO Enable */ + __IOM uint32_t FIFOEN7 : 1; /*!< [7..7] Scan Group 7 FIFO Enable */ + __IOM uint32_t FIFOEN8 : 1; /*!< [8..8] Scan Group 8 FIFO Enable */ + uint32_t : 23; + } ADFIFOCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTCR; /*!< (@ 0x000004C4) FIFO Interrupt Control Register */ + + struct + { + __IOM uint32_t FIFOIE0 : 1; /*!< [0..0] Scan Group 0 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE1 : 1; /*!< [1..1] Scan Group 1 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE2 : 1; /*!< [2..2] Scan Group 2 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE3 : 1; /*!< [3..3] Scan Group 3 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE4 : 1; /*!< [4..4] Scan Group 4 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE5 : 1; /*!< [5..5] Scan Group 5 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE6 : 1; /*!< [6..6] Scan Group 6 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE7 : 1; /*!< [7..7] Scan Group 7 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE8 : 1; /*!< [8..8] Scan Group 8 FIFO Interrupt Enable */ + uint32_t : 23; + } ADFIFOINTCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR0; /*!< (@ 0x000004C8) FIFO Interrupt Generation Level Register 0 */ + + struct + { + __IOM uint32_t FIFOILV0 : 4; /*!< [3..0] Scan Group 0 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV1 : 4; /*!< [19..16] Scan Group 1 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR0_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR1; /*!< (@ 0x000004CC) FIFO Interrupt Generation Level Register 1 */ + + struct + { + __IOM uint32_t FIFOILV2 : 4; /*!< [3..0] Scan Group 2 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV3 : 4; /*!< [19..16] Scan Group 3 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR1_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR2; /*!< (@ 0x000004D0) FIFO Interrupt Generation Level Register 2 */ + + struct + { + __IOM uint32_t FIFOILV4 : 4; /*!< [3..0] Scan Group 4 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV5 : 4; /*!< [19..16] Scan Group 5 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR2_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR3; /*!< (@ 0x000004D4) FIFO Interrupt Generation Level Register 3 */ + + struct + { + __IOM uint32_t FIFOILV6 : 4; /*!< [3..0] Scan Group 6 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV7 : 4; /*!< [19..16] Scan Group 7 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR3_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR4; /*!< (@ 0x000004D8) FIFO Interrupt Generation Level Register 4 */ + + struct + { + __IOM uint32_t FIFOILV8 : 4; /*!< [3..0] Scan Group 8 FIFO Interrupt Output Timing Setting */ + uint32_t : 28; + } ADFIFOINTLR4_b; + }; + __IM uint32_t RESERVED26[73]; + + union + { + __IOM uint32_t ADCHCR0; /*!< (@ 0x00000600) A/D Conversion Channel Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR0_b; + }; + + union + { + __IOM uint32_t ADDOPCRA0; /*!< (@ 0x00000604) A/D Conversion Data Operation Control A Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA0_b; + }; + + union + { + __IOM uint32_t ADDOPCRB0; /*!< (@ 0x00000608) A/D Conversion Data Operation Control B Register + * 0 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB0_b; + }; + + union + { + __IOM uint32_t ADDOPCRC0; /*!< (@ 0x0000060C) A/D Conversion Data Operation Control C Register + * 0 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC0_b; + }; + + union + { + __IOM uint32_t ADCHCR1; /*!< (@ 0x00000610) A/D Conversion Channel Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR1_b; + }; + + union + { + __IOM uint32_t ADDOPCRA1; /*!< (@ 0x00000614) A/D Conversion Data Operation Control A Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA1_b; + }; + + union + { + __IOM uint32_t ADDOPCRB1; /*!< (@ 0x00000618) A/D Conversion Data Operation Control B Register + * 1 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB1_b; + }; + + union + { + __IOM uint32_t ADDOPCRC1; /*!< (@ 0x0000061C) A/D Conversion Data Operation Control C Register + * 1 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC1_b; + }; + + union + { + __IOM uint32_t ADCHCR2; /*!< (@ 0x00000620) A/D Conversion Channel Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR2_b; + }; + + union + { + __IOM uint32_t ADDOPCRA2; /*!< (@ 0x00000624) A/D Conversion Data Operation Control A Register + * 2 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA2_b; + }; + + union + { + __IOM uint32_t ADDOPCRB2; /*!< (@ 0x00000628) A/D Conversion Data Operation Control B Register + * 2 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB2_b; + }; + + union + { + __IOM uint32_t ADDOPCRC2; /*!< (@ 0x0000062C) A/D Conversion Data Operation Control C Register + * 2 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC2_b; + }; + + union + { + __IOM uint32_t ADCHCR3; /*!< (@ 0x00000630) A/D Conversion Channel Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR3_b; + }; + + union + { + __IOM uint32_t ADDOPCRA3; /*!< (@ 0x00000634) A/D Conversion Data Operation Control A Register + * 3 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA3_b; + }; + + union + { + __IOM uint32_t ADDOPCRB3; /*!< (@ 0x00000638) A/D Conversion Data Operation Control B Register + * 3 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB3_b; + }; + + union + { + __IOM uint32_t ADDOPCRC3; /*!< (@ 0x0000063C) A/D Conversion Data Operation Control C Register + * 3 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC3_b; + }; + + union + { + __IOM uint32_t ADCHCR4; /*!< (@ 0x00000640) A/D Conversion Channel Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR4_b; + }; + + union + { + __IOM uint32_t ADDOPCRA4; /*!< (@ 0x00000644) A/D Conversion Data Operation Control A Register + * 4 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA4_b; + }; + + union + { + __IOM uint32_t ADDOPCRB4; /*!< (@ 0x00000648) A/D Conversion Data Operation Control B Register + * 4 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB4_b; + }; + + union + { + __IOM uint32_t ADDOPCRC4; /*!< (@ 0x0000064C) A/D Conversion Data Operation Control C Register + * 4 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC4_b; + }; + + union + { + __IOM uint32_t ADCHCR5; /*!< (@ 0x00000650) A/D Conversion Channel Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR5_b; + }; + + union + { + __IOM uint32_t ADDOPCRA5; /*!< (@ 0x00000654) A/D Conversion Data Operation Control A Register + * 5 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA5_b; + }; + + union + { + __IOM uint32_t ADDOPCRB5; /*!< (@ 0x00000658) A/D Conversion Data Operation Control B Register + * 5 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB5_b; + }; + + union + { + __IOM uint32_t ADDOPCRC5; /*!< (@ 0x0000065C) A/D Conversion Data Operation Control C Register + * 5 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC5_b; + }; + + union + { + __IOM uint32_t ADCHCR6; /*!< (@ 0x00000660) A/D Conversion Channel Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR6_b; + }; + + union + { + __IOM uint32_t ADDOPCRA6; /*!< (@ 0x00000664) A/D Conversion Data Operation Control A Register + * 6 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA6_b; + }; + + union + { + __IOM uint32_t ADDOPCRB6; /*!< (@ 0x00000668) A/D Conversion Data Operation Control B Register + * 6 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB6_b; + }; + + union + { + __IOM uint32_t ADDOPCRC6; /*!< (@ 0x0000066C) A/D Conversion Data Operation Control C Register + * 6 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC6_b; + }; + + union + { + __IOM uint32_t ADCHCR7; /*!< (@ 0x00000670) A/D Conversion Channel Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR7_b; + }; + + union + { + __IOM uint32_t ADDOPCRA7; /*!< (@ 0x00000674) A/D Conversion Data Operation Control A Register + * 7 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA7_b; + }; + + union + { + __IOM uint32_t ADDOPCRB7; /*!< (@ 0x00000678) A/D Conversion Data Operation Control B Register + * 7 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB7_b; + }; + + union + { + __IOM uint32_t ADDOPCRC7; /*!< (@ 0x0000067C) A/D Conversion Data Operation Control C Register + * 7 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC7_b; + }; + + union + { + __IOM uint32_t ADCHCR8; /*!< (@ 0x00000680) A/D Conversion Channel Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR8_b; + }; + + union + { + __IOM uint32_t ADDOPCRA8; /*!< (@ 0x00000684) A/D Conversion Data Operation Control A Register + * 8 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA8_b; + }; + + union + { + __IOM uint32_t ADDOPCRB8; /*!< (@ 0x00000688) A/D Conversion Data Operation Control B Register + * 8 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB8_b; + }; + + union + { + __IOM uint32_t ADDOPCRC8; /*!< (@ 0x0000068C) A/D Conversion Data Operation Control C Register + * 8 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC8_b; + }; + + union + { + __IOM uint32_t ADCHCR9; /*!< (@ 0x00000690) A/D Conversion Channel Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR9_b; + }; + + union + { + __IOM uint32_t ADDOPCRA9; /*!< (@ 0x00000694) A/D Conversion Data Operation Control A Register + * 9 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA9_b; + }; + + union + { + __IOM uint32_t ADDOPCRB9; /*!< (@ 0x00000698) A/D Conversion Data Operation Control B Register + * 9 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB9_b; + }; + + union + { + __IOM uint32_t ADDOPCRC9; /*!< (@ 0x0000069C) A/D Conversion Data Operation Control C Register + * 9 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC9_b; + }; + + union + { + __IOM uint32_t ADCHCR10; /*!< (@ 0x000006A0) A/D Conversion Channel Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR10_b; + }; + + union + { + __IOM uint32_t ADDOPCRA10; /*!< (@ 0x000006A4) A/D Conversion Data Operation Control A Register + * 10 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA10_b; + }; + + union + { + __IOM uint32_t ADDOPCRB10; /*!< (@ 0x000006A8) A/D Conversion Data Operation Control B Register + * 10 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB10_b; + }; + + union + { + __IOM uint32_t ADDOPCRC10; /*!< (@ 0x000006AC) A/D Conversion Data Operation Control C Register + * 10 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC10_b; + }; + + union + { + __IOM uint32_t ADCHCR11; /*!< (@ 0x000006B0) A/D Conversion Channel Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR11_b; + }; + + union + { + __IOM uint32_t ADDOPCRA11; /*!< (@ 0x000006B4) A/D Conversion Data Operation Control A Register + * 11 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA11_b; + }; + + union + { + __IOM uint32_t ADDOPCRB11; /*!< (@ 0x000006B8) A/D Conversion Data Operation Control B Register + * 11 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB11_b; + }; + + union + { + __IOM uint32_t ADDOPCRC11; /*!< (@ 0x000006BC) A/D Conversion Data Operation Control C Register + * 11 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC11_b; + }; + + union + { + __IOM uint32_t ADCHCR12; /*!< (@ 0x000006C0) A/D Conversion Channel Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR12_b; + }; + + union + { + __IOM uint32_t ADDOPCRA12; /*!< (@ 0x000006C4) A/D Conversion Data Operation Control A Register + * 12 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA12_b; + }; + + union + { + __IOM uint32_t ADDOPCRB12; /*!< (@ 0x000006C8) A/D Conversion Data Operation Control B Register + * 12 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB12_b; + }; + + union + { + __IOM uint32_t ADDOPCRC12; /*!< (@ 0x000006CC) A/D Conversion Data Operation Control C Register + * 12 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC12_b; + }; + + union + { + __IOM uint32_t ADCHCR13; /*!< (@ 0x000006D0) A/D Conversion Channel Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR13_b; + }; + + union + { + __IOM uint32_t ADDOPCRA13; /*!< (@ 0x000006D4) A/D Conversion Data Operation Control A Register + * 13 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA13_b; + }; + + union + { + __IOM uint32_t ADDOPCRB13; /*!< (@ 0x000006D8) A/D Conversion Data Operation Control B Register + * 13 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB13_b; + }; + + union + { + __IOM uint32_t ADDOPCRC13; /*!< (@ 0x000006DC) A/D Conversion Data Operation Control C Register + * 13 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC13_b; + }; + + union + { + __IOM uint32_t ADCHCR14; /*!< (@ 0x000006E0) A/D Conversion Channel Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR14_b; + }; + + union + { + __IOM uint32_t ADDOPCRA14; /*!< (@ 0x000006E4) A/D Conversion Data Operation Control A Register + * 14 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA14_b; + }; + + union + { + __IOM uint32_t ADDOPCRB14; /*!< (@ 0x000006E8) A/D Conversion Data Operation Control B Register + * 14 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB14_b; + }; + + union + { + __IOM uint32_t ADDOPCRC14; /*!< (@ 0x000006EC) A/D Conversion Data Operation Control C Register + * 14 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC14_b; + }; + + union + { + __IOM uint32_t ADCHCR15; /*!< (@ 0x000006F0) A/D Conversion Channel Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR15_b; + }; + + union + { + __IOM uint32_t ADDOPCRA15; /*!< (@ 0x000006F4) A/D Conversion Data Operation Control A Register + * 15 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA15_b; + }; + + union + { + __IOM uint32_t ADDOPCRB15; /*!< (@ 0x000006F8) A/D Conversion Data Operation Control B Register + * 15 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB15_b; + }; + + union + { + __IOM uint32_t ADDOPCRC15; /*!< (@ 0x000006FC) A/D Conversion Data Operation Control C Register + * 15 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC15_b; + }; + + union + { + __IOM uint32_t ADCHCR16; /*!< (@ 0x00000700) A/D Conversion Channel Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR16_b; + }; + + union + { + __IOM uint32_t ADDOPCRA16; /*!< (@ 0x00000704) A/D Conversion Data Operation Control A Register + * 16 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA16_b; + }; + + union + { + __IOM uint32_t ADDOPCRB16; /*!< (@ 0x00000708) A/D Conversion Data Operation Control B Register + * 16 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB16_b; + }; + + union + { + __IOM uint32_t ADDOPCRC16; /*!< (@ 0x0000070C) A/D Conversion Data Operation Control C Register + * 16 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC16_b; + }; + + union + { + __IOM uint32_t ADCHCR17; /*!< (@ 0x00000710) A/D Conversion Channel Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR17_b; + }; + + union + { + __IOM uint32_t ADDOPCRA17; /*!< (@ 0x00000714) A/D Conversion Data Operation Control A Register + * 17 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA17_b; + }; + + union + { + __IOM uint32_t ADDOPCRB17; /*!< (@ 0x00000718) A/D Conversion Data Operation Control B Register + * 17 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB17_b; + }; + + union + { + __IOM uint32_t ADDOPCRC17; /*!< (@ 0x0000071C) A/D Conversion Data Operation Control C Register + * 17 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC17_b; + }; + + union + { + __IOM uint32_t ADCHCR18; /*!< (@ 0x00000720) A/D Conversion Channel Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR18_b; + }; + + union + { + __IOM uint32_t ADDOPCRA18; /*!< (@ 0x00000724) A/D Conversion Data Operation Control A Register + * 18 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA18_b; + }; + + union + { + __IOM uint32_t ADDOPCRB18; /*!< (@ 0x00000728) A/D Conversion Data Operation Control B Register + * 18 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB18_b; + }; + + union + { + __IOM uint32_t ADDOPCRC18; /*!< (@ 0x0000072C) A/D Conversion Data Operation Control C Register + * 18 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC18_b; + }; + + union + { + __IOM uint32_t ADCHCR19; /*!< (@ 0x00000730) A/D Conversion Channel Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR19_b; + }; + + union + { + __IOM uint32_t ADDOPCRA19; /*!< (@ 0x00000734) A/D Conversion Data Operation Control A Register + * 19 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA19_b; + }; + + union + { + __IOM uint32_t ADDOPCRB19; /*!< (@ 0x00000738) A/D Conversion Data Operation Control B Register + * 19 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB19_b; + }; + + union + { + __IOM uint32_t ADDOPCRC19; /*!< (@ 0x0000073C) A/D Conversion Data Operation Control C Register + * 19 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC19_b; + }; + + union + { + __IOM uint32_t ADCHCR20; /*!< (@ 0x00000740) A/D Conversion Channel Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR20_b; + }; + + union + { + __IOM uint32_t ADDOPCRA20; /*!< (@ 0x00000744) A/D Conversion Data Operation Control A Register + * 20 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA20_b; + }; + + union + { + __IOM uint32_t ADDOPCRB20; /*!< (@ 0x00000748) A/D Conversion Data Operation Control B Register + * 20 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB20_b; + }; + + union + { + __IOM uint32_t ADDOPCRC20; /*!< (@ 0x0000074C) A/D Conversion Data Operation Control C Register + * 20 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC20_b; + }; + + union + { + __IOM uint32_t ADCHCR21; /*!< (@ 0x00000750) A/D Conversion Channel Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR21_b; + }; + + union + { + __IOM uint32_t ADDOPCRA21; /*!< (@ 0x00000754) A/D Conversion Data Operation Control A Register + * 21 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA21_b; + }; + + union + { + __IOM uint32_t ADDOPCRB21; /*!< (@ 0x00000758) A/D Conversion Data Operation Control B Register + * 21 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB21_b; + }; + + union + { + __IOM uint32_t ADDOPCRC21; /*!< (@ 0x0000075C) A/D Conversion Data Operation Control C Register + * 21 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC21_b; + }; + + union + { + __IOM uint32_t ADCHCR22; /*!< (@ 0x00000760) A/D Conversion Channel Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR22_b; + }; + + union + { + __IOM uint32_t ADDOPCRA22; /*!< (@ 0x00000764) A/D Conversion Data Operation Control A Register + * 22 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA22_b; + }; + + union + { + __IOM uint32_t ADDOPCRB22; /*!< (@ 0x00000768) A/D Conversion Data Operation Control B Register + * 22 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB22_b; + }; + + union + { + __IOM uint32_t ADDOPCRC22; /*!< (@ 0x0000076C) A/D Conversion Data Operation Control C Register + * 22 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC22_b; + }; + + union + { + __IOM uint32_t ADCHCR23; /*!< (@ 0x00000770) A/D Conversion Channel Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR23_b; + }; + + union + { + __IOM uint32_t ADDOPCRA23; /*!< (@ 0x00000774) A/D Conversion Data Operation Control A Register + * 23 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA23_b; + }; + + union + { + __IOM uint32_t ADDOPCRB23; /*!< (@ 0x00000778) A/D Conversion Data Operation Control B Register + * 23 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB23_b; + }; + + union + { + __IOM uint32_t ADDOPCRC23; /*!< (@ 0x0000077C) A/D Conversion Data Operation Control C Register + * 23 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC23_b; + }; + + union + { + __IOM uint32_t ADCHCR24; /*!< (@ 0x00000780) A/D Conversion Channel Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR24_b; + }; + + union + { + __IOM uint32_t ADDOPCRA24; /*!< (@ 0x00000784) A/D Conversion Data Operation Control A Register + * 24 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA24_b; + }; + + union + { + __IOM uint32_t ADDOPCRB24; /*!< (@ 0x00000788) A/D Conversion Data Operation Control B Register + * 24 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB24_b; + }; + + union + { + __IOM uint32_t ADDOPCRC24; /*!< (@ 0x0000078C) A/D Conversion Data Operation Control C Register + * 24 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC24_b; + }; + + union + { + __IOM uint32_t ADCHCR25; /*!< (@ 0x00000790) A/D Conversion Channel Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR25_b; + }; + + union + { + __IOM uint32_t ADDOPCRA25; /*!< (@ 0x00000794) A/D Conversion Data Operation Control A Register + * 25 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA25_b; + }; + + union + { + __IOM uint32_t ADDOPCRB25; /*!< (@ 0x00000798) A/D Conversion Data Operation Control B Register + * 25 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB25_b; + }; + + union + { + __IOM uint32_t ADDOPCRC25; /*!< (@ 0x0000079C) A/D Conversion Data Operation Control C Register + * 25 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC25_b; + }; + + union + { + __IOM uint32_t ADCHCR26; /*!< (@ 0x000007A0) A/D Conversion Channel Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR26_b; + }; + + union + { + __IOM uint32_t ADDOPCRA26; /*!< (@ 0x000007A4) A/D Conversion Data Operation Control A Register + * 26 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA26_b; + }; + + union + { + __IOM uint32_t ADDOPCRB26; /*!< (@ 0x000007A8) A/D Conversion Data Operation Control B Register + * 26 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB26_b; + }; + + union + { + __IOM uint32_t ADDOPCRC26; /*!< (@ 0x000007AC) A/D Conversion Data Operation Control C Register + * 26 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC26_b; + }; + + union + { + __IOM uint32_t ADCHCR27; /*!< (@ 0x000007B0) A/D Conversion Channel Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR27_b; + }; + + union + { + __IOM uint32_t ADDOPCRA27; /*!< (@ 0x000007B4) A/D Conversion Data Operation Control A Register + * 27 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA27_b; + }; + + union + { + __IOM uint32_t ADDOPCRB27; /*!< (@ 0x000007B8) A/D Conversion Data Operation Control B Register + * 27 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB27_b; + }; + + union + { + __IOM uint32_t ADDOPCRC27; /*!< (@ 0x000007BC) A/D Conversion Data Operation Control C Register + * 27 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC27_b; + }; + + union + { + __IOM uint32_t ADCHCR28; /*!< (@ 0x000007C0) A/D Conversion Channel Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR28_b; + }; + + union + { + __IOM uint32_t ADDOPCRA28; /*!< (@ 0x000007C4) A/D Conversion Data Operation Control A Register + * 28 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA28_b; + }; + + union + { + __IOM uint32_t ADDOPCRB28; /*!< (@ 0x000007C8) A/D Conversion Data Operation Control B Register + * 28 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB28_b; + }; + + union + { + __IOM uint32_t ADDOPCRC28; /*!< (@ 0x000007CC) A/D Conversion Data Operation Control C Register + * 28 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC28_b; + }; + + union + { + __IOM uint32_t ADCHCR29; /*!< (@ 0x000007D0) A/D Conversion Channel Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR29_b; + }; + + union + { + __IOM uint32_t ADDOPCRA29; /*!< (@ 0x000007D4) A/D Conversion Data Operation Control A Register + * 29 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA29_b; + }; + + union + { + __IOM uint32_t ADDOPCRB29; /*!< (@ 0x000007D8) A/D Conversion Data Operation Control B Register + * 29 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB29_b; + }; + + union + { + __IOM uint32_t ADDOPCRC29; /*!< (@ 0x000007DC) A/D Conversion Data Operation Control C Register + * 29 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC29_b; + }; + + union + { + __IOM uint32_t ADCHCR30; /*!< (@ 0x000007E0) A/D Conversion Channel Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR30_b; + }; + + union + { + __IOM uint32_t ADDOPCRA30; /*!< (@ 0x000007E4) A/D Conversion Data Operation Control A Register + * 30 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA30_b; + }; + + union + { + __IOM uint32_t ADDOPCRB30; /*!< (@ 0x000007E8) A/D Conversion Data Operation Control B Register + * 30 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB30_b; + }; + + union + { + __IOM uint32_t ADDOPCRC30; /*!< (@ 0x000007EC) A/D Conversion Data Operation Control C Register + * 30 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC30_b; + }; + + union + { + __IOM uint32_t ADCHCR31; /*!< (@ 0x000007F0) A/D Conversion Channel Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR31_b; + }; + + union + { + __IOM uint32_t ADDOPCRA31; /*!< (@ 0x000007F4) A/D Conversion Data Operation Control A Register + * 31 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA31_b; + }; + + union + { + __IOM uint32_t ADDOPCRB31; /*!< (@ 0x000007F8) A/D Conversion Data Operation Control B Register + * 31 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB31_b; + }; + + union + { + __IOM uint32_t ADDOPCRC31; /*!< (@ 0x000007FC) A/D Conversion Data Operation Control C Register + * 31 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC31_b; + }; + + union + { + __IOM uint32_t ADCHCR32; /*!< (@ 0x00000800) A/D Conversion Channel Configuration Register + * 32 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR32_b; + }; + + union + { + __IOM uint32_t ADDOPCRA32; /*!< (@ 0x00000804) A/D Conversion Data Operation Control A Register + * 32 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA32_b; + }; + + union + { + __IOM uint32_t ADDOPCRB32; /*!< (@ 0x00000808) A/D Conversion Data Operation Control B Register + * 32 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB32_b; + }; + + union + { + __IOM uint32_t ADDOPCRC32; /*!< (@ 0x0000080C) A/D Conversion Data Operation Control C Register + * 32 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC32_b; + }; + __IM uint32_t RESERVED27[252]; + + union + { + __OM uint32_t ADCALSTR; /*!< (@ 0x00000C00) A/D Converter Calibration Start Register */ + + struct + { + __OM uint32_t ADCALST0 : 3; /*!< [2..0] A/D Converter Unit 0 (ADC0) Calibration Start Control + * bits */ + uint32_t : 5; + __OM uint32_t ADCALST1 : 3; /*!< [10..8] A/D Converter Unit 1 (ADC1) Calibration Start Control + * bits */ + uint32_t : 21; + } ADCALSTR_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t ADTRGENR; /*!< (@ 0x00000C08) A/D Conversion Start Trigger Enable Register */ + + struct + { + __IOM uint32_t STTRGENn : 9; /*!< [8..0] Scan Group n A/D Conversion Start Trigger Enable */ + uint32_t : 23; + } ADTRGENR_b; + }; + __IM uint32_t RESERVED29; + + union + { + __OM uint32_t ADSYSTR; /*!< (@ 0x00000C10) A/D Conversion Synchronous Software Start Register */ + + struct + { + __OM uint32_t ADSYSTn : 9; /*!< [8..0] Scan Group n : A/D Conversion start */ + uint32_t : 23; + } ADSYSTR_b; + }; + __IM uint32_t RESERVED30[3]; + + union + { + __OM uint32_t ADSTR[9]; /*!< (@ 0x00000C20) A/D Conversion Software Start Register [0..8] */ + + struct + { + __OM uint32_t ADST : 1; /*!< [0..0] Scan Group n A/D Conversion Start */ + uint32_t : 31; + } ADSTR_b[9]; + }; + __IM uint32_t RESERVED31[7]; + + union + { + __OM uint32_t ADSTOPR; /*!< (@ 0x00000C60) A/D Conversion Stop Register */ + + struct + { + __OM uint32_t ADSTOP0 : 1; /*!< [0..0] A/D Converter Unit 0 Force Stop bit */ + uint32_t : 7; + __OM uint32_t ADSTOP1 : 1; /*!< [8..8] A/D Converter Unit 1 Force Stop bit */ + uint32_t : 23; + } ADSTOPR_b; + }; + __IM uint32_t RESERVED32[7]; + + union + { + __IM uint32_t ADSR; /*!< (@ 0x00000C80) A/D Conversion Status Register */ + + struct + { + __IM uint32_t ADACT0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) A/D Conversion Status */ + __IM uint32_t ADACT1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) A/D Conversion Status */ + uint32_t : 14; + __IM uint32_t CALACT0 : 1; /*!< [16..16] A/D Converter Unit 0 (ADC0) : Calibration Status */ + __IM uint32_t CALACT1 : 1; /*!< [17..17] A/D Converter Unit 1 (ADC1) : Calibration Status */ + uint32_t : 14; + } ADSR_b; + }; + + union + { + __IM uint32_t ADGRSR; /*!< (@ 0x00000C84) Scan Group Status Register */ + + struct + { + __IM uint32_t ACTGRn : 9; /*!< [8..0] Scan Group n Status */ + uint32_t : 23; + } ADGRSR_b; + }; + + union + { + __IM uint32_t ADERSR; /*!< (@ 0x00000C88) A/D Conversion Error Status Register */ + + struct + { + __IM uint32_t ADERF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Error Flag */ + __IM uint32_t ADERF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Error Flag */ + uint32_t : 30; + } ADERSR_b; + }; + + union + { + __OM uint32_t ADERSCR; /*!< (@ 0x00000C8C) A/D Conversion Error Status Clear Register */ + + struct + { + __OM uint32_t ADERCLR0 : 1; /*!< [0..0] A/D Converter Unit 0 Error Flag Clear */ + __OM uint32_t ADERCLR1 : 1; /*!< [1..1] A/D Converter Unit 1 Error Flag Clear */ + uint32_t : 30; + } ADERSCR_b; + }; + __IM uint32_t RESERVED33[2]; + + union + { + __IM uint32_t ADCALENDSR; /*!< (@ 0x00000C98) A/D Converter Calibration End Status Register */ + + struct + { + __IM uint32_t CALENDF0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End flag */ + __IM uint32_t CALENDF1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End flag */ + uint32_t : 30; + } ADCALENDSR_b; + }; + + union + { + __OM uint32_t ADCALENDSCR; /*!< (@ 0x00000C9C) A/D Converter Calibration End Status Clear Register */ + + struct + { + __OM uint32_t CALENDC0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End Flag Clear */ + __OM uint32_t CALENDC1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End Flag Clear */ + uint32_t : 30; + } ADCALENDSCR_b; + }; + + union + { + __IM uint32_t ADOVFERSR; /*!< (@ 0x00000CA0) A/D Conversion Overflow Error Status Register */ + + struct + { + __IM uint32_t ADOVFEF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag */ + __IM uint32_t ADOVFEF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag */ + uint32_t : 30; + } ADOVFERSR_b; + }; + + union + { + __IM uint32_t ADOVFCHSR0; /*!< (@ 0x00000CA4) A/D Conversion Overflow Channel Status Register + * 0 */ + + struct + { + __IM uint32_t OVFCHFn : 23; /*!< [22..0] Analog Input Channel No. n : Overflow Flag */ + uint32_t : 9; + } ADOVFCHSR0_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IM uint32_t ADOVFEXSR; /*!< (@ 0x00000CB0) Extended Analog A/D Conversion Overflow Status + * Register */ + + struct + { + __IM uint32_t OVFEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Overflow Flag */ + __IM uint32_t OVFEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Overflow Flag */ + uint32_t : 2; + __IM uint32_t OVFEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Overflow Flag */ + __IM uint32_t OVFEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Overflow Flag */ + __IM uint32_t OVFEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Overflow Flag */ + uint32_t : 1; + __IM uint32_t OVFEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Overflow Flag */ + __IM uint32_t OVFEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Overflow Flag */ + uint32_t : 6; + __IM uint32_t OVFEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Overflow Flag */ + __IM uint32_t OVFEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Overflow Flag */ + __IM uint32_t OVFEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Overflow Flag */ + uint32_t : 1; + __IM uint32_t OVFEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Overflow Flag */ + __IM uint32_t OVFEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Overflow Flag */ + __IM uint32_t OVFEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Overflow Flag */ + uint32_t : 9; + } ADOVFEXSR_b; + }; + + union + { + __OM uint32_t ADOVFERSCR; /*!< (@ 0x00000CB4) A/D Conversion Overflow Error Status Clear Register */ + + struct + { + __OM uint32_t ADOVFEC0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear */ + __OM uint32_t ADOVFEC1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear */ + uint32_t : 30; + } ADOVFERSCR_b; + }; + + union + { + __OM uint32_t ADOVFCHSCR0; /*!< (@ 0x00000CB8) A/D Conversion Overflow Channel Status Clear + * Register 0 */ + + struct + { + __OM uint32_t OVFCHCn : 23; /*!< [22..0] Analog Input Channel No. n : Overflow Flag Clear */ + uint32_t : 9; + } ADOVFCHSCR0_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __OM uint32_t ADOVFEXSCR; /*!< (@ 0x00000CC4) Extended Analog A/D Conversion Overflow Status + * Clear Register */ + + struct + { + __OM uint32_t OVFEXC0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag Clear */ + __OM uint32_t OVFEXC1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag Clear */ + uint32_t : 2; + __OM uint32_t OVFEXC4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag Clear */ + __OM uint32_t OVFEXC5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag + * Clear */ + __OM uint32_t OVFEXC6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag Clear */ + uint32_t : 1; + __OM uint32_t OVFEXC8 : 1; /*!< [8..8] D/A Converter 0 Channel: Compare Match Flag Clear */ + __OM uint32_t OVFEXC9 : 1; /*!< [9..9] D/A Converter 1 Channel: Compare Match Flag Clear */ + uint32_t : 6; + __OM uint32_t OVFEXC16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag Clear */ + __OM uint32_t OVFEXC17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag Clear */ + __OM uint32_t OVFEXC18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag Clear */ + uint32_t : 1; + __OM uint32_t OVFEXC20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag Clear */ + __OM uint32_t OVFEXC21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Compare Match Flag Clear */ + __OM uint32_t OVFEXC22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Compare Match Flag Clear */ + uint32_t : 9; + } ADOVFEXSCR_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IM uint32_t ADFIFOSR0; /*!< (@ 0x00000CD0) FIFO Status Register 0 */ + + struct + { + __IM uint32_t FIFOST0 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 0 */ + uint32_t : 12; + __IM uint32_t FIFOST1 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 1 */ + uint32_t : 12; + } ADFIFOSR0_b; + }; + + union + { + __IM uint32_t ADFIFOSR1; /*!< (@ 0x00000CD4) FIFO Status Register 1 */ + + struct + { + __IM uint32_t FIFOST2 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 2 */ + uint32_t : 12; + __IM uint32_t FIFOST3 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 3 */ + uint32_t : 12; + } ADFIFOSR1_b; + }; + + union + { + __IM uint32_t ADFIFOSR2; /*!< (@ 0x00000CD8) FIFO Status Register 2 */ + + struct + { + __IM uint32_t FIFOST4 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 4 */ + uint32_t : 12; + __IM uint32_t FIFOST5 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 5 */ + uint32_t : 12; + } ADFIFOSR2_b; + }; + + union + { + __IM uint32_t ADFIFOSR3; /*!< (@ 0x00000CDC) FIFO Status Register 3 */ + + struct + { + __IM uint32_t FIFOST6 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 6 */ + uint32_t : 12; + __IM uint32_t FIFOST7 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 7 */ + uint32_t : 12; + } ADFIFOSR3_b; + }; + + union + { + __IM uint32_t ADFIFOSR4; /*!< (@ 0x00000CE0) FIFO Status Register 4 */ + + struct + { + __IM uint32_t FIFOST8 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 8 */ + uint32_t : 28; + } ADFIFOSR4_b; + }; + __IM uint32_t RESERVED37[3]; + + union + { + __OM uint32_t ADFIFODCR; /*!< (@ 0x00000CF0) FIFO Data Clear Register */ + + struct + { + __OM uint32_t FIFODCn : 9; /*!< [8..0] Scan Group n FIFO Data Clear */ + uint32_t : 23; + } ADFIFODCR_b; + }; + + union + { + __IM uint32_t ADFIFOERSR; /*!< (@ 0x00000CF4) FIFO Error Status Register */ + + struct + { + __IM uint32_t FIFOOVFn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag */ + uint32_t : 7; + __IM uint32_t FIFOFLFn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag */ + uint32_t : 7; + } ADFIFOERSR_b; + }; + + union + { + __OM uint32_t ADFIFOERSCR; /*!< (@ 0x00000CF8) FIFO Error Status Clear Register */ + + struct + { + __OM uint32_t FIFOOVFCn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag Clear */ + uint32_t : 7; + __OM uint32_t FIFOFLCn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag Clear */ + uint32_t : 7; + } ADFIFOERSCR_b; + }; + __IM uint32_t RESERVED38; + + union + { + __IM uint32_t ADCMPTBSR; /*!< (@ 0x00000D00) Compare Match Table Status Register */ + + struct + { + __IM uint32_t CMPTBFn : 8; /*!< [7..0] Compare Match Table n Match Flag */ + uint32_t : 24; + } ADCMPTBSR_b; + }; + + union + { + __OM uint32_t ADCMPTBSCR; /*!< (@ 0x00000D04) Compare Match Table Status Clear Register */ + + struct + { + __OM uint32_t CMPTBCn : 8; /*!< [7..0] Compare Match Table n : Match Flag Clear */ + uint32_t : 24; + } ADCMPTBSCR_b; + }; + + union + { + __IM uint32_t ADCMPCHSR0; /*!< (@ 0x00000D08) Compare Match Channel Status Register 0 */ + + struct + { + __IM uint32_t CMPCHFn : 23; /*!< [22..0] Analog Channel No. n : Compare Match Flag */ + uint32_t : 9; + } ADCMPCHSR0_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IM uint32_t ADCMPEXSR; /*!< (@ 0x00000D14) Extended Analog Compare Match Status Register */ + + struct + { + __IM uint32_t CMPEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag */ + __IM uint32_t CMPEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag */ + uint32_t : 2; + __IM uint32_t CMPEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag */ + __IM uint32_t CMPEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag */ + __IM uint32_t CMPEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag */ + uint32_t : 1; + __IM uint32_t CMPEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel : Compare Match Flag */ + __IM uint32_t CMPEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Compare Match Flag */ + uint32_t : 6; + __IM uint32_t CMPEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag */ + __IM uint32_t CMPEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag */ + __IM uint32_t CMPEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag */ + uint32_t : 1; + __IM uint32_t CMPEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + __IM uint32_t CMPEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + __IM uint32_t CMPEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag */ + uint32_t : 9; + } ADCMPEXSR_b; + }; + + union + { + __OM uint32_t ADCMPCHSCR0; /*!< (@ 0x00000D18) Compare Match Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t CMPCHCn : 23; /*!< [22..0] Analog Channel No. n : Compare Match Flag Clear bit */ + uint32_t : 9; + } ADCMPCHSCR0_b; + }; + __IM uint32_t RESERVED40[2]; + + union + { + __OM uint32_t ADCMPEXSCR; /*!< (@ 0x00000D24) Extended Analog Compare Match Status Clear Register */ + + struct + { + __OM uint32_t CMPEXC0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Compare Match + * Flag Clear */ + __OM uint32_t CMPEXC1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Compare Match + * Flag Clear */ + uint32_t : 2; + __OM uint32_t CMPEXC4 : 1; /*!< [4..4] Temperature Sensor Channel: Compare Match Flag Clear */ + __OM uint32_t CMPEXC5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Compare Match Flag + * Clear */ + __OM uint32_t CMPEXC6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Compare Match + * Flag Clear */ + uint32_t : 1; + __OM uint32_t CMPEXC8 : 1; /*!< [8..8] D/A Converter 0 Channel: Compare Match Flag Clear */ + __OM uint32_t CMPEXC9 : 1; /*!< [9..9] D/A Converter 1 Channel : Compare Match Flag Clear */ + uint32_t : 6; + __OM uint32_t CMPEXC16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Compare Match Flag Clear */ + __OM uint32_t CMPEXC17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Compare Match Flag Clear */ + __OM uint32_t CMPEXC18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Compare Match Flag Clear */ + uint32_t : 1; + __OM uint32_t CMPEXC20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Compare Match Flag Clear */ + __OM uint32_t CMPEXC21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Compare Match Flag Clear */ + __OM uint32_t CMPEXC22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Compare Match Flag Clear */ + uint32_t : 9; + } ADCMPEXSCR_b; + }; + + union + { + __IM uint32_t ADLIMGRSR; /*!< (@ 0x00000D28) Limiter Clip Scan Group Status Register */ + + struct + { + __IM uint32_t LIMGRFn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag */ + uint32_t : 23; + } ADLIMGRSR_b; + }; + + union + { + __IM uint32_t ADLIMCHSR0; /*!< (@ 0x00000D2C) Limiter Clip Channel Status Register 0 */ + + struct + { + __IM uint32_t LIMCHFn : 23; /*!< [22..0] Analog Channel No. n : Limiter Clip Flag bit */ + uint32_t : 9; + } ADLIMCHSR0_b; + }; + __IM uint32_t RESERVED41[2]; + + union + { + __IM uint32_t ADLIMEXSR; /*!< (@ 0x00000D38) Extended Analog Limiter Clip Status Register */ + + struct + { + __IM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Limiter Clip Flag */ + __IM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel for A/D unit 1: Limiter Clip + * Flag */ + uint32_t : 2; + __IM uint32_t LIMEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Limiter Clip + * Flag */ + uint32_t : 1; + __IM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Limiter Clip Flag */ + __IM uint32_t LIMEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Limiter Clip Flag */ + uint32_t : 6; + __IM uint32_t LIMEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Limiter Clip Flag */ + __IM uint32_t LIMEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Limiter Clip Flag */ + __IM uint32_t LIMEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Limiter Clip Flag */ + uint32_t : 1; + __IM uint32_t LIMEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Limiter Clip Flag */ + __IM uint32_t LIMEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Limiter Clip Flag */ + __IM uint32_t LIMEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Limiter Clip Flag */ + uint32_t : 9; + } ADLIMEXSR_b; + }; + + union + { + __OM uint32_t ADLIMGRSCR; /*!< (@ 0x00000D3C) Limiter Clip Scan Group Status Clear Register */ + + struct + { + __OM uint32_t LIMGRCn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag Clear */ + uint32_t : 23; + } ADLIMGRSCR_b; + }; + + union + { + __OM uint32_t ADLIMCHSCR0; /*!< (@ 0x00000D40) Limiter Clip Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t LIMCHCn : 23; /*!< [22..0] Analog Channel No. n Limiter Clip Flag Clear bit */ + uint32_t : 9; + } ADLIMCHSCR0_b; + }; + __IM uint32_t RESERVED42[2]; + + union + { + __OM uint32_t ADLIMEXSCR; /*!< (@ 0x00000D4C) Extended Analog Limiter Clip Status Clear Register */ + + struct + { + __OM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-diagnosis Channel for A/D unit 0: Limiter Clip Flag + * Clear */ + __OM uint32_t LIMEXF1 : 1; /*!< [1..1] Self-diagnosis Channel for A/D unit 1: Limiter Clip Flag + * Clear */ + uint32_t : 2; + __OM uint32_t LIMEXF4 : 1; /*!< [4..4] Temperature Sensor Channel: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF5 : 1; /*!< [5..5] Internal Reference Voltage Channel: Limiter Clip Flag + * Clear */ + __OM uint32_t LIMEXF6 : 1; /*!< [6..6] VBATT 1/3 voltage monitor output Channel: Limiter Clip + * Flag Clear */ + uint32_t : 1; + __OM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 0 Channel: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF9 : 1; /*!< [9..9] D/A Converter 1 Channel: Limiter Clip Flag Clear */ + uint32_t : 6; + __OM uint32_t LIMEXF16 : 1; /*!< [16..16] Self-diagnosis Channel for Sample-and-hold circuit + * unit0: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF17 : 1; /*!< [17..17] Self-diagnosis Channel for Sample-and-hold circuit + * unit1: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF18 : 1; /*!< [18..18] Self-diagnosis Channel for Sample-and-hold circuit + * unit2: Limiter Clip Flag Clear */ + uint32_t : 1; + __OM uint32_t LIMEXF20 : 1; /*!< [20..20] Self-diagnosis Channel for Sample-and-hold circuit + * unit4: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF21 : 1; /*!< [21..21] Self-diagnosis Channel for Sample-and-hold circuit + * unit5: Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF22 : 1; /*!< [22..22] Self-diagnosis Channel for Sample-and-hold circuit + * unit6: Limiter Clip Flag Clear */ + uint32_t : 9; + } ADLIMEXSCR_b; + }; + + union + { + __IM uint32_t ADSCANENDSR; /*!< (@ 0x00000D50) Scan End Status Register */ + + struct + { + __IM uint32_t SCENDFn : 9; /*!< [8..0] Scan Group n Scan End Flag */ + uint32_t : 23; + } ADSCANENDSR_b; + }; + + union + { + __OM uint32_t ADSCANENDSCR; /*!< (@ 0x00000D54) Scan End Status Clear Register */ + + struct + { + __OM uint32_t SCENDCn : 9; /*!< [8..0] Scan Group n Scan End Flag Clear */ + uint32_t : 23; + } ADSCANENDSCR_b; + }; + __IM uint32_t RESERVED43[1194]; + + union + { + __IM uint32_t ADDR[23]; /*!< (@ 0x00002000) A/D Data Register [0..22] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 15; + __IM uint32_t ERR : 1; /*!< [31..31] A/D conversion data error status */ + } ADDR_b[23]; + }; + __IM uint32_t RESERVED44[73]; + + union + { + __IM uint32_t ADEXDR[23]; /*!< (@ 0x00002180) A/D Extended Analog Data Register [0..22] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 8; + __IM uint32_t DIAGSR : 3; /*!< [26..24] Self-Diagnosis Status */ + uint32_t : 4; + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Error Status */ + } ADEXDR_b[23]; + }; + __IM uint32_t RESERVED45[9]; + + union + { + __IM uint32_t ADFIFODR0; /*!< (@ 0x00002200) FIFO Data Register 0 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR0_b; + }; + + union + { + __IM uint32_t ADFIFODR1; /*!< (@ 0x00002204) FIFO Data Register 1 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR1_b; + }; + + union + { + __IM uint32_t ADFIFODR2; /*!< (@ 0x00002208) FIFO Data Register 2 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR2_b; + }; + + union + { + __IM uint32_t ADFIFODR3; /*!< (@ 0x0000220C) FIFO Data Register 3 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR3_b; + }; + + union + { + __IM uint32_t ADFIFODR4; /*!< (@ 0x00002210) FIFO Data Register 4 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR4_b; + }; + + union + { + __IM uint32_t ADFIFODR5; /*!< (@ 0x00002214) FIFO Data Register 5 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR5_b; + }; + + union + { + __IM uint32_t ADFIFODR6; /*!< (@ 0x00002218) FIFO Data Register 6 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR6_b; + }; + + union + { + __IM uint32_t ADFIFODR7; /*!< (@ 0x0000221C) FIFO Data Register 7 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR7_b; + }; + + union + { + __IM uint32_t ADFIFODR8; /*!< (@ 0x00002220) FIFO Data Register 8 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR8_b; + }; +} R_ADC_B0_Type; /*!< Size = 8740 (0x2224) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC_B) + */ + +typedef struct /*!< (@ 0x40311000) R_DOC_B Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */ + __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */ + + struct + { + __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */ + uint8_t : 7; + } DOSR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */ + + struct + { + __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */ + uint8_t : 7; + } DOSCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */ + __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */ + __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */ +} R_DOC_B_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI_B0) + */ + +typedef struct /*!< (@ 0x40358000) R_SCI_B0 Structure */ +{ + union + { + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint8_t RDR_BY; /*!< (@ 0x00000000) Receive Data Register (byte access) */ + + struct + { + __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data */ + } RDR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 2; + __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */ + uint32_t : 19; + } TDR_b; + }; + + union + { + __IOM uint8_t TDR_BY; /*!< (@ 0x00000004) Transmit Data Register (byte access) */ + + struct + { + __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data */ + } TDR_BY_b; + }; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 1; + __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit. */ + uint32_t : 4; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + + union + { + __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */ + + struct + { + __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */ + uint8_t : 3; + __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */ + uint8_t : 3; + } CESR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */ + + struct + { + __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint32_t : 1; + __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */ + __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + uint32_t : 1; + __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */ + __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */ + uint32_t : 2; + __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */ + __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */ + uint32_t : 2; + __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */ + __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */ + __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */ + uint32_t : 5; + } MCR_b; + }; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + + union + { + __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */ + + struct + { + __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */ + uint32_t : 6; + __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */ + __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */ + __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */ + __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */ + __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */ + __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */ + __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */ + uint32_t : 2; + __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */ + __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */ + __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */ + uint32_t : 1; + __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */ + uint32_t : 6; + } XCR0_b; + }; + + union + { + __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */ + + struct + { + __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */ + uint32_t : 3; + __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */ + __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */ + uint32_t : 2; + __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */ + __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */ + __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */ + } XCR1_b; + }; + + union + { + __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */ + + struct + { + __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */ + __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */ + __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */ + } XCR2_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */ + __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */ + __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + + union + { + __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */ + + struct + { + __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */ + __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */ + __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */ + uint32_t : 1; + __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */ + uint32_t : 1; + __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */ + uint32_t : 25; + } MSR_b; + }; + + union + { + __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */ + + struct + { + __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */ + __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */ + uint32_t : 6; + __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */ + __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */ + __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */ + __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */ + __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */ + __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */ + __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */ + __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */ + __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */ + __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */ + } XSR0_b; + }; + + union + { + __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */ + + struct + { + __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */ + uint32_t : 16; + } XSR1_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */ + __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */ + __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */ + uint32_t : 31; + } FFCLR_b; + }; + + union + { + __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */ + + struct + { + __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */ + __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */ + __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */ + uint32_t : 1; + __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */ + uint32_t : 27; + } MFCLR_b; + }; + + union + { + __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */ + __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */ + __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */ + __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */ + __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */ + __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */ + __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */ + __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */ + uint32_t : 16; + } XFCLR_b; + }; +} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI_B0) + */ + +typedef struct /*!< (@ 0x4035C000) R_SPI_B0 Structure */ +{ + __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */ + + union + { + __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */ + + struct + { + __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */ + uint32_t : 5; + __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */ + uint32_t : 5; + __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */ + uint32_t : 5; + __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */ + uint32_t : 5; + } SPDECR_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */ + + struct + { + __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint32_t : 1; + __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */ + __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */ + __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */ + __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */ + __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */ + uint32_t : 2; + __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */ + __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */ + uint32_t : 10; + } SPCR2_b; + }; + + union + { + __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */ + + struct + { + __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */ + __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */ + __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */ + __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */ + uint32_t : 4; + __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */ + uint32_t : 8; + __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */ + uint32_t : 5; + } SPCR3_b; + }; + + union + { + __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD0_b; + }; + + union + { + __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD1_b; + }; + + union + { + __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD2_b; + }; + + union + { + __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD3_b; + }; + + union + { + __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD4_b; + }; + + union + { + __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD5_b; + }; + + union + { + __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD6_b; + }; + + union + { + __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD7_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */ + + struct + { + __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint32_t : 2; + __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */ + __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */ + uint32_t : 3; + __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */ + uint32_t : 22; + } SPDCR_b; + }; + + union + { + __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */ + + struct + { + __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint32_t : 6; + __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint32_t : 22; + } SPDCR2_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */ + uint32_t : 1; + __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */ + uint32_t : 8; + __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */ + __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */ + __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */ + __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */ + __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */ + __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */ + __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */ + + struct + { + __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint32_t : 29; + } SPTFSR_b; + }; + + union + { + __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */ + + struct + { + __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint32_t : 29; + } SPRFSR_b; + }; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */ + + struct + { + uint32_t : 23; + __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */ + __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */ + uint32_t : 1; + __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */ + __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */ + __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */ + __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */ + __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */ + __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */ + + struct + { + __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */ + uint32_t : 31; + } SPFCR_b; + }; +} R_SPI_B0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40351000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief eXpanded SPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x40268000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration register */ + + struct + { + __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 3; + __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1 */ + uint32_t : 3; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration register */ + + struct + { + __IOM uint32_t ARBMD : 2; /*!< [1..0] Channel arbitration mode */ + uint32_t : 2; + __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable */ + uint32_t : 10; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFGCH[2]; /*!< (@ 0x00000008) xSPI Bridge Map Configuration register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 7; + __IOM uint32_t CMBTIM : 8; /*!< [31..24] Combination timer */ + } BMCFGCH_b[2]; + }; + __IOM R_XSPI0_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers */ + __IM uint32_t RESERVED[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1] */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + + union + { + __IOM uint32_t ABMCFG; /*!< (@ 0x00000058) xSPI AXI Bridge Map Config */ + + struct + { + __IOM uint32_t ODRMD : 2; /*!< [1..0] AXI Transfer Ordering Mode */ + uint32_t : 14; + __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select */ + } ABMCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control register 0 */ + + struct + { + __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable */ + __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable */ + __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable */ + __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable */ + uint32_t : 24; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0 */ + __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1 */ + __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0 */ + __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1 */ + uint32_t : 20; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTLCH[2]; /*!< (@ 0x00000068) xSPI Command Map Control register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTLCH_b[2]; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED2; + __IOM R_XSPI0_CDBUF_Type CDBUF[4]; /*!< (@ 0x00000080) xSPI BUF register */ + __IM uint32_t RESERVED3[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave 0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave 1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_XSPI0_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register */ + __IM uint32_t RESERVED5[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status register */ + + struct + { + __IM uint32_t MEMACCCH0 : 1; /*!< [0..0] Memory access ongoing from ch0 */ + __IM uint32_t MEMACCCH1 : 1; /*!< [1..1] Memory access ongoing from ch1 */ + uint32_t : 2; + __IM uint32_t PBUFNECH0 : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0 */ + __IM uint32_t PBUFNECH1 : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1 */ + __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0 */ + __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1 */ + uint32_t : 8; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status register */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOFCH0 : 1; /*!< [16..16] Bridge Buffer overflow for CH0 */ + __IM uint32_t BRGOFCH1 : 1; /*!< [17..17] Bridge Buffer overflow for CH1 */ + __IM uint32_t BRGUFCH0 : 1; /*!< [18..18] Bridge Buffer underflow for CH0 */ + __IM uint32_t BRGUFCH1 : 1; /*!< [19..19] Bridge Buffer underflow for CH1 */ + __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0 */ + __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1 */ + uint32_t : 6; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFCH0C : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear */ + __OM uint32_t BRGOFCH1C : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear */ + __OM uint32_t BRGUFCH0C : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear */ + __OM uint32_t BRGUFCH1C : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear */ + __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear */ + __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear */ + uint32_t : 6; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFCH0E : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable */ + __IOM uint32_t BRGOFCH1E : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable */ + __IOM uint32_t BRGUFCH0E : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable */ + __IOM uint32_t BRGUFCH1E : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable */ + __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable */ + __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable */ + uint32_t : 6; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D-PHY Controller Top (R_MIPI_PHY) + */ + +typedef struct /*!< (@ 0x40346C00) R_MIPI_PHY Structure */ +{ + union + { + __IOM uint32_t DPHYREFCR; /*!< (@ 0x00000000) D-PHY Reference Clock Setting Register */ + + struct + { + __IOM uint32_t RFREQ : 8; /*!< [7..0] Reference Clock Frequency Setting */ + uint32_t : 24; + } DPHYREFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLFCR; /*!< (@ 0x00000004) D-PHY PLL Frequency Control Register */ + + struct + { + __IOM uint32_t IDIV : 2; /*!< [1..0] D-PHY PLL Input Frequency Division Ratio Select */ + uint32_t : 6; + __IOM uint32_t NFMUL : 2; /*!< [9..8] D-PHY PLL Frequency Multiplication Factor Select (Fractional + * Part) */ + uint32_t : 2; + __IOM uint32_t PMUL : 2; /*!< [13..12] D-PHY PLL Output Frequency Division Ratio Select */ + uint32_t : 2; + __IOM uint32_t NMUL : 9; /*!< [24..16] D-PHY PLL Frequency Multiplication Factor Select (Integer + * Part) */ + uint32_t : 7; + } DPHYPLFCR_b; + }; + + union + { + __IOM uint32_t DPHYPLOCR; /*!< (@ 0x00000008) D-PHY PLL Operation Control Register */ + + struct + { + __IOM uint32_t PLLSTP : 1; /*!< [0..0] D-PHY PLL Operation Control */ + uint32_t : 31; + } DPHYPLOCR_b; + }; + + union + { + __IOM uint32_t DPHYESCCR; /*!< (@ 0x0000000C) D-PHY Escape Mode Clock Control Register */ + + struct + { + __IOM uint32_t ESCDIV : 5; /*!< [4..0] Escape Mode Transfer Clock Division Ratio */ + uint32_t : 27; + } DPHYESCCR_b; + }; + + union + { + __IOM uint32_t DPHYPWRCR; /*!< (@ 0x00000010) D-PHY Power Supplying Control Register */ + + struct + { + __IOM uint32_t PWRSEN : 1; /*!< [0..0] D-PHY Power Supplying Control */ + uint32_t : 31; + } DPHYPWRCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IM uint32_t DPHYSFR; /*!< (@ 0x0000001C) D-PHY Status Flag Register */ + + struct + { + __IM uint32_t PWRSF : 1; /*!< [0..0] D-PHY LDO Power-on Status Flag */ + uint32_t : 7; + __IM uint32_t PLLSF : 1; /*!< [8..8] D-PHY PLL Oscillation Stabilization Flag */ + uint32_t : 23; + } DPHYSFR_b; + }; + + union + { + __IOM uint32_t DPHYOCR; /*!< (@ 0x00000020) D-PHY Operation Control Register */ + + struct + { + __IOM uint32_t DPHYEN : 1; /*!< [0..0] D-PHY Operation Control */ + uint32_t : 31; + } DPHYOCR_b; + }; + + union + { + __IOM uint32_t DPHYTIM1; /*!< (@ 0x00000024) D-PHY Timing Control Register 1 */ + + struct + { + __IOM uint32_t TINIT : 19; /*!< [18..0] D-PHY T_INIT Parameter Setting */ + uint32_t : 13; + } DPHYTIM1_b; + }; + + union + { + __IOM uint32_t DPHYTIM2; /*!< (@ 0x00000028) D-PHY Timing Control Register 2 */ + + struct + { + __IOM uint32_t TCLKPREP : 8; /*!< [7..0] D-PHY T_CLK_PREPARE Parameter Setting */ + __IOM uint32_t TCLKSETT : 8; /*!< [15..8] D-PHY T_CLK_SETTLE Parameter Setting */ + __IOM uint32_t TCLKMISS : 8; /*!< [23..16] D-PHY T_CLK_MISS Parameter Setting */ + uint32_t : 8; + } DPHYTIM2_b; + }; + + union + { + __IOM uint32_t DPHYTIM3; /*!< (@ 0x0000002C) D-PHY Timing Control Register 3 */ + + struct + { + __IOM uint32_t THSPREP : 8; /*!< [7..0] D-PHY T_THS_PREPARE Parameter Setting */ + __IOM uint32_t THSSETT : 8; /*!< [15..8] D-PHY T_THS_SETTLE Parameter Setting */ + uint32_t : 16; + } DPHYTIM3_b; + }; + + union + { + __IOM uint32_t DPHYTIM4; /*!< (@ 0x00000030) D-PHY Timing Control Register 4 */ + + struct + { + __IOM uint32_t TCLKZERO : 8; /*!< [7..0] D-PHY T_CLK_ZERO Parameter Setting */ + __IOM uint32_t TCLKPRE : 8; /*!< [15..8] D-PHY T_TCLK_PRE Parameter Setting */ + __IOM uint32_t TCLKPOST : 8; /*!< [23..16] D-PHY T_TCLK_POST Parameter Setting */ + __IOM uint32_t TCLKTRL : 8; /*!< [31..24] D-PHY T_TCLK_TRAIL Parameter Setting */ + } DPHYTIM4_b; + }; + + union + { + __IOM uint32_t DPHYTIM5; /*!< (@ 0x00000034) D-PHY Timing Control Register 5 */ + + struct + { + __IOM uint32_t THSZERO : 8; /*!< [7..0] D-PHY T_THS_ZERO Parameter Setting */ + __IOM uint32_t THSTRL : 8; /*!< [15..8] D-PHY T_THS_TRAIL Parameter Setting */ + __IOM uint32_t THSEXIT : 8; /*!< [23..16] D-PHY T_THS_EXIT Parameter Setting */ + uint32_t : 8; + } DPHYTIM5_b; + }; + + union + { + __IOM uint32_t DPHYTIM6; /*!< (@ 0x00000038) D-PHY Timing Control Register 6 */ + + struct + { + __IOM uint32_t TLPX : 8; /*!< [7..0] D-PHY T_TLPX Parameter Setting */ + uint32_t : 24; + } DPHYTIM6_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DPHYMDC; /*!< (@ 0x00000048) D-PHY Mode Control Register */ + + struct + { + __IOM uint32_t MASTEREN : 1; /*!< [0..0] D-PHY Master/Slave Select */ + uint32_t : 31; + } DPHYMDC_b; + }; +} R_MIPI_PHY_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_CSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MIPI_CSI Register area (R_MIPI_CSI) + */ + +typedef struct /*!< (@ 0x40347000) R_MIPI_CSI Structure */ +{ + union + { + __IM uint32_t MCG; /*!< (@ 0x00000000) Module Configuration Register */ + + struct + { + __IM uint32_t VER : 4; /*!< [3..0] VERsion of this ip */ + uint32_t : 4; + __IM uint32_t SDLN : 4; /*!< [11..8] Number of Supported Data Lanes */ + uint32_t : 4; + __IM uint32_t GSNM : 8; /*!< [23..16] NuMber of Generic Short packt FIFO */ + uint32_t : 8; + } MCG_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t MCT0; /*!< (@ 0x00000010) Module Control Register 0 */ + + struct + { + __IOM uint32_t VDLN : 4; /*!< [3..0] Numer of Valid Data Lanes */ + uint32_t : 12; + __IOM uint32_t ZLMD : 1; /*!< [16..16] Zero Length long packet output MoDe */ + __IOM uint32_t EDMD : 1; /*!< [17..17] ErrframeData notification MoDe */ + uint32_t : 1; + __IOM uint32_t RVMD : 1; /*!< [19..19] ReserVed packet reception MoDe */ + __IOM uint32_t GRMD : 1; /*!< [20..20] Generic csi-2 Rule MoDe */ + uint32_t : 3; + __IOM uint32_t ECCV13 : 1; /*!< [24..24] ECC check csi-2 Ver 1.3 mode */ + __IOM uint32_t LFSREN : 1; /*!< [25..25] LFSR Enable mode */ + uint32_t : 6; + } MCT0_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t MCT2; /*!< (@ 0x00000018) Module Control Register 2 */ + + struct + { + __IOM uint32_t FRRCLK : 9; /*!< [8..0] clock FRequency Rate to judge packet reception end */ + uint32_t : 7; + __IOM uint32_t FRRSKW : 9; /*!< [24..16] clock FRequency Rate to adjust data lane SKew */ + uint32_t : 7; + } MCT2_b; + }; + + union + { + __IOM uint32_t MCT3; /*!< (@ 0x0000001C) Module Control Register 3 */ + + struct + { + __IOM uint32_t RXEN : 1; /*!< [0..0] RX (reception) Enable */ + uint32_t : 31; + } MCT3_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t RTCT; /*!< (@ 0x00000028) Reset Control Register */ + + struct + { + __OM uint32_t VSRST : 1; /*!< [0..0] Video pixel interface Software ReSeT */ + uint32_t : 31; + } RTCT_b; + }; + + union + { + __IM uint32_t RTST; /*!< (@ 0x0000002C) Reset Status Register */ + + struct + { + __IM uint32_t VSRSTS : 1; /*!< [0..0] Video pixel interface Software ReSeT Status */ + uint32_t : 31; + } RTST_b; + }; + __IM uint32_t RESERVED3[4]; + + union + { + __IOM uint32_t EPCT; /*!< (@ 0x00000040) EPD Option Control Register */ + + struct + { + __IOM uint32_t SLP : 15; /*!< [14..0] Long Packet Spacers */ + __IOM uint32_t EPDOP : 1; /*!< [15..15] EPD OPtion select */ + __IOM uint32_t SSP : 15; /*!< [30..16] epd Short Packet Spacers */ + __IOM uint32_t EPDEN : 1; /*!< [31..31] ENable EPD operation */ + } EPCT_b; + }; + + union + { + __IOM uint32_t EMCT; /*!< (@ 0x00000044) EPD Misc Option Control Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t VLSIEN : 2; /*!< [5..4] ENable Variable-Length Spacer Insertions */ + __IOM uint32_t EOTPEN : 1; /*!< [6..6] ENable EOTP */ + uint32_t : 25; + } EMCT_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t MIST; /*!< (@ 0x00000050) Module Interrupt Status Register */ + + struct + { + __IM uint32_t DL0S : 1; /*!< [0..0] interrupt Status related to Data Lane 0 */ + __IM uint32_t DL1S : 1; /*!< [1..1] interrupt Status related to Data Lane 1 */ + uint32_t : 6; + __IM uint32_t PMS : 1; /*!< [8..8] interrupt Status related to Power Management */ + __IM uint32_t GSTS : 1; /*!< [9..9] interrupt Status related to Generic ShorT packet */ + __IM uint32_t RXS : 1; /*!< [10..10] interrupt Status related to RX (Reception) */ + uint32_t : 5; + __IM uint32_t VC0S : 1; /*!< [16..16] interrupt Status related to Vitrtual Channel 0 */ + __IM uint32_t VC1S : 1; /*!< [17..17] interrupt Status related to Vitrtual Channel 1 */ + __IM uint32_t VC2S : 1; /*!< [18..18] interrupt Status related to Vitrtual Channel 2 */ + __IM uint32_t VC3S : 1; /*!< [19..19] interrupt Status related to Vitrtual Channel 3 */ + __IM uint32_t VC4S : 1; /*!< [20..20] interrupt Status related to Vitrtual Channel 4 */ + __IM uint32_t VC5S : 1; /*!< [21..21] interrupt Status related to Vitrtual Channel 5 */ + __IM uint32_t VC6S : 1; /*!< [22..22] interrupt Status related to Vitrtual Channel 6 */ + __IM uint32_t VC7S : 1; /*!< [23..23] interrupt Status related to Vitrtual Channel 7 */ + __IM uint32_t VC8S : 1; /*!< [24..24] interrupt Status related to Vitrtual Channel 8 */ + __IM uint32_t VC9S : 1; /*!< [25..25] interrupt Status related to Vitrtual Channel 9 */ + __IM uint32_t VC10S : 1; /*!< [26..26] interrupt Status related to Vitrtual Channel 10 */ + __IM uint32_t VC11S : 1; /*!< [27..27] interrupt Status related to Vitrtual Channel 11 */ + __IM uint32_t VC12S : 1; /*!< [28..28] interrupt Status related to Vitrtual Channel 12 */ + __IM uint32_t VC13S : 1; /*!< [29..29] interrupt Status related to Vitrtual Channel 13 */ + __IM uint32_t VC14S : 1; /*!< [30..30] interrupt Status related to Vitrtual Channel 14 */ + __IM uint32_t VC15S : 1; /*!< [31..31] interrupt Status related to Vitrtual Channel 15 */ + } MIST_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t DTEL; /*!< (@ 0x00000060) Receive Data Type Enable Low Register */ + + struct + { + __IOM uint32_t DTEN : 32; /*!< [31..0] Data Type ENable (DT = 0x00 to 0x1F) */ + } DTEL_b; + }; + + union + { + __IOM uint32_t DTEH; /*!< (@ 0x00000064) Receive Data Type Enable High Register */ + + struct + { + __IOM uint32_t DTEN : 32; /*!< [31..0] Data Type ENable (DT = 0x20 to 0x3F) */ + } DTEH_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IM uint32_t RXST; /*!< (@ 0x00000070) Receive Status Register */ + + struct + { + __IM uint32_t FRM0 : 1; /*!< [0..0] FRaMe of virtual channel 0 active */ + __IM uint32_t FRM1 : 1; /*!< [1..1] FRaMe of virtual channel 1 active */ + __IM uint32_t FRM2 : 1; /*!< [2..2] FRaMe of virtual channel 2 active */ + __IM uint32_t FRM3 : 1; /*!< [3..3] FRaMe of virtual channel 3 active */ + __IM uint32_t FRM4 : 1; /*!< [4..4] FRaMe of virtual channel 4 active */ + __IM uint32_t FRM5 : 1; /*!< [5..5] FRaMe of virtual channel 5 active */ + __IM uint32_t FRM6 : 1; /*!< [6..6] FRaMe of virtual channel 6 active */ + __IM uint32_t FRM7 : 1; /*!< [7..7] FRaMe of virtual channel 7 active */ + __IM uint32_t FRM8 : 1; /*!< [8..8] FRaMe of virtual channel 8 active */ + __IM uint32_t FRM9 : 1; /*!< [9..9] FRaMe of virtual channel 9 active */ + __IM uint32_t FRM10 : 1; /*!< [10..10] FRaMe of virtual channel 10 active */ + __IM uint32_t FRM11 : 1; /*!< [11..11] FRaMe of virtual channel 11 active */ + __IM uint32_t FRM12 : 1; /*!< [12..12] FRaMe of virtual channel 12 active */ + __IM uint32_t FRM13 : 1; /*!< [13..13] FRaMe of virtual channel 13 active */ + __IM uint32_t FRM14 : 1; /*!< [14..14] FRaMe of virtual channel 14 active */ + __IM uint32_t FRM15 : 1; /*!< [15..15] FRaMe of virtual channel 15 active */ + __IM uint32_t RACT : 1; /*!< [16..16] Rx (Reception) ACTive status */ + __IM uint32_t RACTDET : 1; /*!< [17..17] Rx (Reception) ACTive DETect */ + uint32_t : 14; + } RXST_b; + }; + + union + { + __OM uint32_t RXSC; /*!< (@ 0x00000074) Receive Status Clear Register */ + + struct + { + uint32_t : 17; + __OM uint32_t RACTDETC : 1; /*!< [17..17] Rx (Reception) ACTive DETect status Clear */ + uint32_t : 14; + } RXSC_b; + }; + + union + { + __IOM uint32_t RXIE; /*!< (@ 0x00000078) Receive Interrupt Enable Register */ + + struct + { + uint32_t : 17; + __IOM uint32_t RACTDETE : 1; /*!< [17..17] Rx (Reception) ACTive DETect interrupt Enable */ + uint32_t : 14; + } RXIE_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t DLST0; /*!< (@ 0x00000080) Data Lane (N) Status Register */ + + struct + { + __IM uint32_t ESH : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status */ + __IM uint32_t ESS : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status */ + __IM uint32_t ECT : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status */ + __IM uint32_t EES : 1; /*!< [3..3] ErrESc detect on data lane (N) status */ + uint32_t : 12; + __IM uint32_t EUL : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status */ + __IM uint32_t RUL : 1; /*!< [17..17] entry to ULps detect on data lane (N) status */ + uint32_t : 6; + __IM uint32_t ULP : 1; /*!< [24..24] rxULPsesc of data lane (N) status */ + uint32_t : 7; + } DLST0_b; + }; + + union + { + __OM uint32_t DLSC0; /*!< (@ 0x00000084) Data Lane (N) Status Clear Register */ + + struct + { + __OM uint32_t ESHC : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status Clear */ + __OM uint32_t ESSC : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status Clear */ + __OM uint32_t ECTC : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status Clear */ + __OM uint32_t EESC : 1; /*!< [3..3] ErrESc detect on data lane (N) status Clear */ + uint32_t : 12; + __OM uint32_t EULC : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status Clear */ + __OM uint32_t RULC : 1; /*!< [17..17] Entry to ULps detect on data lane (N) status Clear */ + uint32_t : 14; + } DLSC0_b; + }; + + union + { + __IOM uint32_t DLIE0; /*!< (@ 0x00000088) Data Lane (N) Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESHE : 1; /*!< [0..0] ErrSotHs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ESSE : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ECTE : 1; /*!< [2..2] ErrConTrol detect on data lane (N) interrupt Enable */ + __IOM uint32_t EESE : 1; /*!< [3..3] ErrESc detect on data lane (N) interrupt Enable */ + uint32_t : 12; + __IOM uint32_t EULE : 1; /*!< [16..16] Exit to ULps detect on data lane (N) interrupt Enable */ + __IOM uint32_t RULE : 1; /*!< [17..17] Entry to ULps detect on data lane (N) interrupt Enable */ + uint32_t : 14; + } DLIE0_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IM uint32_t DLST1; /*!< (@ 0x00000090) Data Lane (N) Status Register */ + + struct + { + __IM uint32_t ESH : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status */ + __IM uint32_t ESS : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status */ + __IM uint32_t ECT : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status */ + __IM uint32_t EES : 1; /*!< [3..3] ErrESc detect on data lane (N) status */ + uint32_t : 12; + __IM uint32_t EUL : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status */ + __IM uint32_t RUL : 1; /*!< [17..17] entry to ULps detect on data lane (N) status */ + uint32_t : 6; + __IM uint32_t ULP : 1; /*!< [24..24] rxULPsesc of data lane (N) status */ + uint32_t : 7; + } DLST1_b; + }; + + union + { + __OM uint32_t DLSC1; /*!< (@ 0x00000094) Data Lane (N) Status Clear Register */ + + struct + { + __OM uint32_t ESHC : 1; /*!< [0..0] ErrSotHs detect on data lane (N) status Clear */ + __OM uint32_t ESSC : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) status Clear */ + __OM uint32_t ECTC : 1; /*!< [2..2] ErrConTrol detect on data lane (N) status Clear */ + __OM uint32_t EESC : 1; /*!< [3..3] ErrESc detect on data lane (N) status Clear */ + uint32_t : 12; + __OM uint32_t EULC : 1; /*!< [16..16] Exit from ULps detect on data lane (N) status Clear */ + __OM uint32_t RULC : 1; /*!< [17..17] Entry to ULps detect on data lane (N) status Clear */ + uint32_t : 14; + } DLSC1_b; + }; + + union + { + __IOM uint32_t DLIE1; /*!< (@ 0x00000098) Data Lane (N) Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESHE : 1; /*!< [0..0] ErrSotHs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ESSE : 1; /*!< [1..1] ErrSotSynchs detect on data lane (N) interrupt Enable */ + __IOM uint32_t ECTE : 1; /*!< [2..2] ErrConTrol detect on data lane (N) interrupt Enable */ + __IOM uint32_t EESE : 1; /*!< [3..3] ErrESc detect on data lane (N) interrupt Enable */ + uint32_t : 12; + __IOM uint32_t EULE : 1; /*!< [16..16] Exit to ULps detect on data lane (N) interrupt Enable */ + __IOM uint32_t RULE : 1; /*!< [17..17] Entry to ULps detect on data lane (N) interrupt Enable */ + uint32_t : 14; + } DLIE1_b; + }; + __IM uint32_t RESERVED9[25]; + + union + { + __IM uint32_t VCST0; /*!< (@ 0x00000100) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST0_b; + }; + + union + { + __OM uint32_t VCSC0; /*!< (@ 0x00000104) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC0_b; + }; + + union + { + __IOM uint32_t VCIE0; /*!< (@ 0x00000108) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE0_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IM uint32_t VCST1; /*!< (@ 0x00000110) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST1_b; + }; + + union + { + __OM uint32_t VCSC1; /*!< (@ 0x00000114) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC1_b; + }; + + union + { + __IOM uint32_t VCIE1; /*!< (@ 0x00000118) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE1_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IM uint32_t VCST2; /*!< (@ 0x00000120) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST2_b; + }; + + union + { + __OM uint32_t VCSC2; /*!< (@ 0x00000124) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC2_b; + }; + + union + { + __IOM uint32_t VCIE2; /*!< (@ 0x00000128) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE2_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t VCST3; /*!< (@ 0x00000130) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST3_b; + }; + + union + { + __OM uint32_t VCSC3; /*!< (@ 0x00000134) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC3_b; + }; + + union + { + __IOM uint32_t VCIE3; /*!< (@ 0x00000138) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE3_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IM uint32_t VCST4; /*!< (@ 0x00000140) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST4_b; + }; + + union + { + __OM uint32_t VCSC4; /*!< (@ 0x00000144) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC4_b; + }; + + union + { + __IOM uint32_t VCIE4; /*!< (@ 0x00000148) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE4_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IM uint32_t VCST5; /*!< (@ 0x00000150) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST5_b; + }; + + union + { + __OM uint32_t VCSC5; /*!< (@ 0x00000154) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC5_b; + }; + + union + { + __IOM uint32_t VCIE5; /*!< (@ 0x00000158) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE5_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IM uint32_t VCST6; /*!< (@ 0x00000160) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST6_b; + }; + + union + { + __OM uint32_t VCSC6; /*!< (@ 0x00000164) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC6_b; + }; + + union + { + __IOM uint32_t VCIE6; /*!< (@ 0x00000168) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE6_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IM uint32_t VCST7; /*!< (@ 0x00000170) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST7_b; + }; + + union + { + __OM uint32_t VCSC7; /*!< (@ 0x00000174) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC7_b; + }; + + union + { + __IOM uint32_t VCIE7; /*!< (@ 0x00000178) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE7_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t VCST8; /*!< (@ 0x00000180) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST8_b; + }; + + union + { + __OM uint32_t VCSC8; /*!< (@ 0x00000184) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC8_b; + }; + + union + { + __IOM uint32_t VCIE8; /*!< (@ 0x00000188) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE8_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IM uint32_t VCST9; /*!< (@ 0x00000190) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST9_b; + }; + + union + { + __OM uint32_t VCSC9; /*!< (@ 0x00000194) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC9_b; + }; + + union + { + __IOM uint32_t VCIE9; /*!< (@ 0x00000198) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE9_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t VCST10; /*!< (@ 0x000001A0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST10_b; + }; + + union + { + __OM uint32_t VCSC10; /*!< (@ 0x000001A4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC10_b; + }; + + union + { + __IOM uint32_t VCIE10; /*!< (@ 0x000001A8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE10_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t VCST11; /*!< (@ 0x000001B0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST11_b; + }; + + union + { + __OM uint32_t VCSC11; /*!< (@ 0x000001B4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC11_b; + }; + + union + { + __IOM uint32_t VCIE11; /*!< (@ 0x000001B8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE11_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IM uint32_t VCST12; /*!< (@ 0x000001C0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST12_b; + }; + + union + { + __OM uint32_t VCSC12; /*!< (@ 0x000001C4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC12_b; + }; + + union + { + __IOM uint32_t VCIE12; /*!< (@ 0x000001C8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE12_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t VCST13; /*!< (@ 0x000001D0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST13_b; + }; + + union + { + __OM uint32_t VCSC13; /*!< (@ 0x000001D4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC13_b; + }; + + union + { + __IOM uint32_t VCIE13; /*!< (@ 0x000001D8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE13_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t VCST14; /*!< (@ 0x000001E0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST14_b; + }; + + union + { + __OM uint32_t VCSC14; /*!< (@ 0x000001E4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC14_b; + }; + + union + { + __IOM uint32_t VCIE14; /*!< (@ 0x000001E8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE14_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IM uint32_t VCST15; /*!< (@ 0x000001F0) Virtual Channel (M) Status Register */ + + struct + { + __IM uint32_t MLF : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status */ + __IM uint32_t ECD : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status */ + __IM uint32_t CRC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status */ + __IM uint32_t IDE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status */ + __IM uint32_t WCE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status */ + __IM uint32_t ECC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status */ + __IM uint32_t ECN : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status */ + uint32_t : 1; + __IM uint32_t FRS : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status */ + __IM uint32_t FRD : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status */ + uint32_t : 6; + __IM uint32_t OVF : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status */ + uint32_t : 7; + __IM uint32_t FSR : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t FER : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status */ + __IM uint32_t LSR : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status */ + __IM uint32_t LER : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status */ + __IM uint32_t ETR : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status */ + uint32_t : 3; + } VCST15_b; + }; + + union + { + __OM uint32_t VCSC15; /*!< (@ 0x000001F4) Virtual Channel (M) Status Clear Register */ + + struct + { + __OM uint32_t MLFC : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t ECDC : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect status Clear */ + __OM uint32_t CRCC : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect status + * Clear */ + __OM uint32_t IDEC : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect status Clear */ + __OM uint32_t WCEC : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * status Clear */ + __OM uint32_t ECCC : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect status Clear */ + __OM uint32_t ECNC : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect status + * Clear */ + uint32_t : 1; + __OM uint32_t FRSC : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect status Clear */ + __OM uint32_t FRDC : 1; /*!< [9..9] errFRameData of virtual channel (M) detect status Clear */ + uint32_t : 4; + __OM uint32_t AMLFC : 1; /*!< [14..14] MaLFormed packet with any virtual channels detect status + * Clear */ + __OM uint32_t AECDC : 1; /*!< [15..15] ECc 2-bit (Double) error packet with any virtual channels + * Detect status Clear */ + __OM uint32_t OVFC : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow status Clear */ + uint32_t : 7; + __OM uint32_t FSRC : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t FERC : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LSRC : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t LERC : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * status Clear */ + __OM uint32_t ETRC : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception status + * Clear */ + uint32_t : 3; + } VCSC15_b; + }; + + union + { + __IOM uint32_t VCIE15; /*!< (@ 0x000001F8) Virtual Channel (M) Interrupt Enable Register */ + + struct + { + __IOM uint32_t MLFE : 1; /*!< [0..0] MaLFormed packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t ECDE : 1; /*!< [1..1] ECc 2-bit (Double) error packet with virtual channel + * (M) Detect interrupt Enable */ + __IOM uint32_t CRCE : 1; /*!< [2..2] CRC error packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t IDEE : 1; /*!< [3..3] ErrID packet with virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t WCEE : 1; /*!< [4..4] Word Count Error packet with virtual channel (M) detect + * interrupt Enable */ + __IOM uint32_t ECCE : 1; /*!< [5..5] ECc 1-bit error (Corrected) packet with virtual channel + * (M) detect interrupt Enable */ + __IOM uint32_t ECNE : 1; /*!< [6..6] ECc No-error packet with virtual channel (M) detect interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t FRSE : 1; /*!< [8..8] errFRameSync of virtual channel (M) detect interrupt + * Enable */ + __IOM uint32_t FRDE : 1; /*!< [9..9] errFRameData of virtual channel (M) detect interrupt + * Enable */ + uint32_t : 6; + __IOM uint32_t OVFE : 1; /*!< [16..16] generic short packet with virtual channel (M) discard + * by fifo OVerFlow interrupt Enable */ + uint32_t : 7; + __IOM uint32_t FSRE : 1; /*!< [24..24] Frame Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t FERE : 1; /*!< [25..25] Frame End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LSRE : 1; /*!< [26..26] Line Start packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t LERE : 1; /*!< [27..27] Line End packet with virtual channel (M) Reception + * interrupt Enable */ + __IOM uint32_t ETRE : 1; /*!< [28..28] EoTp packet with virtual channel (M) Reception interrupt + * Enable */ + uint32_t : 3; + } VCIE15_b; + }; + __IM uint32_t RESERVED25; + + union + { + __IM uint32_t PMST; /*!< (@ 0x00000200) Power Management Status Register */ + + struct + { + __IM uint32_t DSX : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes status */ + __IM uint32_t DSN : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes status */ + __IM uint32_t CSX : 1; /*!< [2..2] eXit from Stop state detect on Clock lane status */ + __IM uint32_t CSN : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane status */ + __IM uint32_t DUX : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes status */ + __IM uint32_t DUN : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes status */ + __IM uint32_t CUX : 1; /*!< [6..6] eXit frum Ulps detect on Clock lane status */ + __IM uint32_t CUN : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane status */ + uint32_t : 6; + __IM uint32_t CLSS : 1; /*!< [14..14] Stop State of Clock Lane status */ + __IM uint32_t CLUL : 1; /*!< [15..15] rxULpsclknot (inverted) of Clock Lane status */ + __IM uint32_t DLSS : 2; /*!< [17..16] Stop State of Data Lanes status */ + uint32_t : 6; + __IM uint32_t DLUL : 2; /*!< [25..24] rxULpsesc of Data Lanes status */ + uint32_t : 6; + } PMST_b; + }; + + union + { + __OM uint32_t PMSC; /*!< (@ 0x00000204) Power Management Status Clear Register */ + + struct + { + __OM uint32_t DSXC : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes status + * Clear */ + __OM uint32_t DSNC : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes status + * Clear */ + __OM uint32_t CSXC : 1; /*!< [2..2] eXit from Stop state detect on Clock lane status Clear */ + __OM uint32_t CSNC : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane status Clear */ + __OM uint32_t DUXC : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes status + * Clear */ + __OM uint32_t DUNC : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes status Clear */ + __OM uint32_t CUXC : 1; /*!< [6..6] eXit frum Ulps detect on Clock lane status Clear */ + __OM uint32_t CUNC : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane status Clear */ + uint32_t : 24; + } PMSC_b; + }; + + union + { + __IOM uint32_t PMIE; /*!< (@ 0x00000208) Power Management Interrupt Enable Register */ + + struct + { + __IOM uint32_t DSXE : 1; /*!< [0..0] eXit from Stop state detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t DSNE : 1; /*!< [1..1] eNtry to Stop state detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t CSXE : 1; /*!< [2..2] eXit from Stop state detect on Clock lane interrupt Enable */ + __IOM uint32_t CSNE : 1; /*!< [3..3] eNtry to Stop state detect on Clock lane interrupt Enable */ + __IOM uint32_t DUXE : 1; /*!< [4..4] eXit from Ulps detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t DUNE : 1; /*!< [5..5] eNtry to Ulps detect on all valid Data lanes interrupt + * Enable */ + __IOM uint32_t CUXE : 1; /*!< [6..6] eXit from Ulps detect on Clock lane interrupt Enable */ + __IOM uint32_t CUNE : 1; /*!< [7..7] eNtry to Ulps detect on Clock lane interrupt Enable */ + uint32_t : 24; + } PMIE_b; + }; + __IM uint32_t RESERVED26[29]; + + union + { + __IOM uint32_t GSCT; /*!< (@ 0x00000280) Generic Short Packet Control Register */ + + struct + { + __IOM uint32_t SHTH : 7; /*!< [6..0] Stored generic short packet THreshold */ + uint32_t : 9; + __IOM uint32_t GFIF : 1; /*!< [16..16] Generic short packet store in FIFo */ + uint32_t : 15; + } GSCT_b; + }; + + union + { + __IM uint32_t GSST; /*!< (@ 0x00000284) Generic Short Packet Status Register */ + + struct + { + __IM uint32_t GNE : 1; /*!< [0..0] Generic short packet fifo Not Empty */ + __IM uint32_t GTH : 1; /*!< [1..1] more than THreshold Generic short packets existed in + * fifo */ + uint32_t : 2; + __IM uint32_t GOV : 1; /*!< [4..4] Generic short packet fifo OVerflow status */ + uint32_t : 3; + __IM uint32_t PNUM : 8; /*!< [15..8] NUMber of stored generic short Packets in fifo */ + __IM uint32_t GCD : 1; /*!< [16..16] Generic short packet fifo Clear status */ + __IM uint32_t STRDS : 1; /*!< [17..17] generic short packet SToRe DiSable */ + uint32_t : 14; + } GSST_b; + }; + + union + { + __OM uint32_t GSSC; /*!< (@ 0x00000288) Generic Short Packet Status Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t GOVC : 1; /*!< [4..4] Generic short packet fifo OVerflow status Clear */ + uint32_t : 27; + } GSSC_b; + }; + + union + { + __IOM uint32_t GSIE; /*!< (@ 0x0000028C) Generic Short Packet Interrupt Enable Register */ + + struct + { + __IOM uint32_t GNEE : 1; /*!< [0..0] Generic short packet fifo Not Empty interrupt Enable */ + __IOM uint32_t GTHE : 1; /*!< [1..1] more than THreshold Generic short packets existed in + * fifo interrupt Enable */ + uint32_t : 2; + __IOM uint32_t GOVE : 1; /*!< [4..4] Generic short packet fifo OVerflow interrupt Enable */ + uint32_t : 27; + } GSIE_b; + }; + + union + { + __IM uint32_t GSHT; /*!< (@ 0x00000290) Generic Short Packet Register */ + + struct + { + __IM uint32_t SPDT : 16; /*!< [15..0] Stored Packet DaTa */ + __IM uint32_t DTYP : 6; /*!< [21..16] Stored packet Data TYPe */ + uint32_t : 2; + __IM uint32_t SPVC : 4; /*!< [27..24] Stored Packet Virtual Channel */ + uint32_t : 4; + } GSHT_b; + }; + + union + { + __IOM uint32_t GSIU; /*!< (@ 0x00000294) Generic Short Packet Information Update Register */ + + struct + { + __OM uint32_t FINC : 1; /*!< [0..0] generic short packet Fifo update (INCrement internal + * pointer) */ + uint32_t : 7; + __IOM uint32_t GFCLR : 1; /*!< [8..8] Generic short packet Fifo CLeaR */ + uint32_t : 7; + __OM uint32_t GFEN : 1; /*!< [16..16] Generic short packet Fifo ENable */ + uint32_t : 15; + } GSIU_b; + }; +} R_MIPI_CSI_Type; /*!< Size = 664 (0x298) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capture Engine Unit (R_CEU) + */ + +typedef struct /*!< (@ 0x40348000) R_CEU Structure */ +{ + union + { + __IOM uint32_t CAPSR; /*!< (@ 0x00000000) Capture Start Register */ + + struct + { + __IOM uint32_t CE : 1; /*!< [0..0] Capture enable */ + uint32_t : 15; + __IOM uint32_t CPKIL : 1; /*!< [16..16] Write 1 to this bit to perform a software reset of + * capturing. */ + uint32_t : 15; + } CAPSR_b; + }; + + union + { + __IOM uint32_t CAPCR; /*!< (@ 0x00000004) Capture Control Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CTNCP : 1; /*!< [16..16] When capturing is started with this bit set to 1, capturing + * continues until the CE bit in CAPSR is cleared to 0 or + * a software reset is initiated by the CPKIL bit in CAPSR + * (see ). Continuous capture must be set before capturing + * is started. */ + uint32_t : 3; + __IOM uint32_t MTCM : 2; /*!< [21..20] Specify the unit for transferring data to a bus bridge + * module. */ + uint32_t : 2; + __IOM uint32_t FDRP : 8; /*!< [31..24] Set the frame drop interval in continuous-frame capture. */ + } CAPCR_b; + }; + + union + { + __IOM uint32_t CAMCR; /*!< (@ 0x00000008) Capture interface control register */ + + struct + { + __IOM uint32_t HDPOL : 1; /*!< [0..0] Sets the polarity for detection of the horizontal sync + * signal input from an external module. */ + __IOM uint32_t VDPOL : 1; /*!< [1..1] Sets the polarity for detection of the vertical sync + * signal input from an external module. */ + uint32_t : 2; + __IOM uint32_t JPG : 2; /*!< [5..4] These bits select the fetched data type. */ + uint32_t : 2; + __IOM uint32_t DTARY : 2; /*!< [9..8] Set the input order of the luminance component and chrominance + * component. */ + uint32_t : 2; + __IOM uint32_t DTIF : 1; /*!< [12..12] Sets the digital image input pins from which data is + * to be captured. */ + uint32_t : 3; + __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal + * (FLD) from an external module. */ + uint32_t : 7; + __IOM uint32_t DSEL : 1; /*!< [24..24] Sets the edge for fetching the image data (D7 to D0) + * from an external module. */ + __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification + * signal (FLD) from an external module. */ + __IOM uint32_t HDSEL : 1; /*!< [26..26] Sets the edge for capturing the horizontal sync signal + * (HD) from an external module. */ + __IOM uint32_t VDSEL : 1; /*!< [27..27] Sets the edge for capturing the vertical sync signal + * (VD) from an external module. */ + uint32_t : 4; + } CAMCR_b; + }; + + union + { + __IOM uint32_t CMCYR; /*!< (@ 0x0000000C) Capture Interface Cycle Register */ + + struct + { + __IOM uint32_t HCYL : 14; /*!< [13..0] Horizontal Cycle Count of External Module */ + uint32_t : 2; + __IOM uint32_t VCYL : 14; /*!< [29..16] Vertical HD Count of External Module */ + uint32_t : 2; + } CMCYR_b; + }; + + union + { + __IOM uint32_t CAMOR; /*!< (@ 0x00000010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_b; + }; + + union + { + __IOM uint32_t CAPWR; /*!< (@ 0x00000014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_b; + }; + + union + { + __IOM uint32_t CAIFR; /*!< (@ 0x00000018) Capture Interface Input Format Register */ + + struct + { + __IOM uint32_t FCI : 2; /*!< [1..0] Set the timing to start capturing. */ + uint32_t : 2; + __IOM uint32_t CIM : 1; /*!< [4..4] Sets the images to be captured. */ + uint32_t : 3; + __IOM uint32_t IFS : 1; /*!< [8..8] Sets the input mode for capturing images. */ + uint32_t : 23; + } CAIFR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CRCNTR; /*!< (@ 0x00000028) CEU Register Control Register */ + + struct + { + __IOM uint32_t RC : 1; /*!< [0..0] Specifies switching of the register plane used by the + * CEU in synchronization with VD. */ + __IOM uint32_t RS : 1; /*!< [1..1] Specifies which register plane is used by the CEU in + * synchronization with VD. */ + uint32_t : 2; + __IOM uint32_t RVS : 1; /*!< [4..4] Sets the timing to switch the register plane in both-field + * capture. */ + uint32_t : 27; + } CRCNTR_b; + }; + + union + { + __IOM uint32_t CRCMPR; /*!< (@ 0x0000002C) CEU Register Forcible Control Register */ + + struct + { + __IOM uint32_t RA : 1; /*!< [0..0] Indicates the register plane currently specified. */ + uint32_t : 31; + } CRCMPR_b; + }; + + union + { + __IOM uint32_t CFLCR; /*!< (@ 0x00000030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_b; + }; + + union + { + __IOM uint32_t CFSZR; /*!< (@ 0x00000034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_b; + }; + + union + { + __IOM uint32_t CDWDR; /*!< (@ 0x00000038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_b; + }; + + union + { + __IOM uint32_t CDAYR; /*!< (@ 0x0000003C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_b; + }; + + union + { + __IOM uint32_t CDACR; /*!< (@ 0x00000040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_b; + }; + + union + { + __IOM uint32_t CDBYR; /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_b; + }; + + union + { + __IOM uint32_t CDBCR; /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_b; + }; + + union + { + __IOM uint32_t CBDSR; /*!< (@ 0x0000004C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFWCR; /*!< (@ 0x0000005C) Firewall Operation Control Register */ + + struct + { + __IOM uint32_t FWE : 1; /*!< [0..0] With the setting of FWE = 1, when an address exceeds + * the value set with FWV, the address is retained and an + * interrupt source FWF is set. After this, the address is + * not incremented and data is overwritten on the upper limit + * address. */ + uint32_t : 4; + __IOM uint32_t FWV : 27; /*!< [31..5] Specify the upper limit of a write address. */ + } CFWCR_b; + }; + + union + { + __IOM uint32_t CLFCR; /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_b; + }; + + union + { + __IOM uint32_t CDOCR; /*!< (@ 0x00000064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CEIER; /*!< (@ 0x00000070) Capture Event Interrupt Enable Register */ + + struct + { + __IOM uint32_t CPEIE : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable */ + __IOM uint32_t CFEIE : 1; /*!< [1..1] CFE Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t IGRWIE : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t HDIE : 1; /*!< [8..8] HD Interrupt Enable */ + __IOM uint32_t VDIE : 1; /*!< [9..9] VD Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable */ + __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable */ + __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable */ + __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable */ + __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable */ + __IOM uint32_t IGHSIE : 1; /*!< [17..17] IGHS Interrupt Enable */ + __IOM uint32_t IGVSIE : 1; /*!< [18..18] IGVS Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBPIE : 1; /*!< [20..20] VBP Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FWFIE : 1; /*!< [23..23] FWF Interrupt Enable */ + __IOM uint32_t NHDIE : 1; /*!< [24..24] Non-HD Interrupt Enable */ + __IOM uint32_t NVDIE : 1; /*!< [25..25] Non-VD Interrupt Enable */ + uint32_t : 6; + } CEIER_b; + }; + + union + { + __IOM uint32_t CETCR; /*!< (@ 0x00000074) Capture Event Flag Clear Register */ + + struct + { + __IOM uint32_t CPE : 1; /*!< [0..0] An interrupt indicating that capturing of one frame from + * an external module has finished. */ + __IOM uint32_t CFE : 1; /*!< [1..1] An interrupt indicating that capturing of one field from + * an external module has finished. */ + uint32_t : 2; + __IOM uint32_t IGRW : 1; /*!< [4..4] An interrupt indicating that during capturing, access + * was attempted to a register to which writing during operation + * is prohibited. */ + uint32_t : 3; + __IOM uint32_t HD : 1; /*!< [8..8] An interrupt indicating that HD (horizontal sync signal) + * was input from an external module. */ + __IOM uint32_t VD : 1; /*!< [9..9] An interrupt indicating that VD (vertical sync signal) + * was input from an external module. */ + uint32_t : 2; + __IOM uint32_t CPBE1 : 1; /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR + * in a bundle write has finished. */ + __IOM uint32_t CPBE2 : 1; /*!< [13..13] An interrupt indicating that writing to CDAYR2 and + * CDACR2 in a bundle write has finished. */ + __IOM uint32_t CPBE3 : 1; /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR + * in a bundle write has finished. */ + __IOM uint32_t CPBE4 : 1; /*!< [15..15] An interrupt indicating that writing to CDBYR2 and + * CDBCR2 in a bundle write has finished. */ + __IOM uint32_t CDTOF : 1; /*!< [16..16] An interrupt indicating that data overflowed in the + * CRAM of the write buffer */ + __IOM uint32_t IGHS : 1; /*!< [17..17] An interrupt generated when the number of HD cycles + * set in CMCYR differ from the number of HD cycles input + * from an external module. */ + __IOM uint32_t IGVS : 1; /*!< [18..18] An interrupt generated when the number of VD cycles + * set in CMCYR differ from the number of VD cycles input + * from an external module. */ + uint32_t : 1; + __IOM uint32_t VBP : 1; /*!< [20..20] An interrupt indicating that VD has been input while + * the CEU holds data (insufficient vertical-sync front porch). */ + uint32_t : 2; + __IOM uint32_t FWF : 1; /*!< [23..23] The interrupt is generated when data is written to + * the address that exceeds the value specified with CFWCR.FMV. */ + __IOM uint32_t NHD : 1; /*!< [24..24] An interrupt indicating that no HD was input. */ + __IOM uint32_t NVD : 1; /*!< [25..25] An interrupt indicating that no VD was input. */ + uint32_t : 6; + } CETCR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t CSTSR; /*!< (@ 0x0000007C) Capture Status Register */ + + struct + { + __IM uint32_t CPTON : 1; /*!< [0..0] Indicates that the CEU is operating. */ + uint32_t : 15; + __IM uint32_t CPFLD : 1; /*!< [16..16] Indicates which field is being captured. */ + uint32_t : 7; + __IM uint32_t CRST : 1; /*!< [24..24] Indicates which register plane is currently used. */ + uint32_t : 7; + } CSTSR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t CDSSR; /*!< (@ 0x00000084) Capture Data Size Register */ + + struct + { + __IM uint32_t CDSS : 32; /*!< [31..0] Indicate the size of data written to the memory in data + * enable fetch. */ + } CDSSR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CDAYR2; /*!< (@ 0x00000090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_b; + }; + + union + { + __IOM uint32_t CDACR2; /*!< (@ 0x00000094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_b; + }; + + union + { + __IOM uint32_t CDBYR2; /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_b; + }; + + union + { + __IOM uint32_t CDBCR2; /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_b; + }; + + union + { + __IOM uint32_t AXIBUSCTL2; /*!< (@ 0x000000A0) AXI Bus Control Register 2 */ + + struct + { + __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit */ + uint32_t : 28; + } AXIBUSCTL2_b; + }; + __IM uint32_t RESERVED6[987]; + + union + { + __IOM uint32_t CAMOR_B; /*!< (@ 0x00001010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_B_b; + }; + + union + { + __IOM uint32_t CAPWR_B; /*!< (@ 0x00001014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_B_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t CFLCR_B; /*!< (@ 0x00001030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_B_b; + }; + + union + { + __IOM uint32_t CFSZR_B; /*!< (@ 0x00001034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_B_b; + }; + + union + { + __IOM uint32_t CDWDR_B; /*!< (@ 0x00001038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_B_b; + }; + + union + { + __IOM uint32_t CDAYR_B; /*!< (@ 0x0000103C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_B_b; + }; + + union + { + __IOM uint32_t CDACR_B; /*!< (@ 0x00001040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_B_b; + }; + + union + { + __IOM uint32_t CDBYR_B; /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_B_b; + }; + + union + { + __IOM uint32_t CDBCR_B; /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_B_b; + }; + + union + { + __IOM uint32_t CBDSR_B; /*!< (@ 0x0000104C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_B_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint32_t CLFCR_B; /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_B_b; + }; + + union + { + __IOM uint32_t CDOCR_B; /*!< (@ 0x00001064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_B_b; + }; + __IM uint32_t RESERVED9[10]; + + union + { + __IOM uint32_t CDAYR2_B; /*!< (@ 0x00001090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_B_b; + }; + + union + { + __IOM uint32_t CDACR2_B; /*!< (@ 0x00001094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_B_b; + }; + + union + { + __IOM uint32_t CDBYR2_B; /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_B_b; + }; + + union + { + __IOM uint32_t CDBCR2_B; /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_B_b; + }; + __IM uint32_t RESERVED10[988]; + + union + { + __IOM uint32_t CAMOR_M; /*!< (@ 0x00002010) Capture Interface Offset Register */ + + struct + { + __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number + * of clock cycles from a horizontal sync signal (1-cycle + * units). */ + uint32_t : 3; + __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the + * HD count from a vertical sync signal (1-HD units). */ + uint32_t : 4; + } CAMOR_M_b; + }; + + union + { + __IOM uint32_t CAPWR_M; /*!< (@ 0x00002014) Capture Interface Width Register */ + + struct + { + __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */ + uint32_t : 3; + __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */ + uint32_t : 4; + } CAPWR_M_b; + }; + __IM uint32_t RESERVED11[6]; + + union + { + __IOM uint32_t CFLCR_M; /*!< (@ 0x00002030) Capture Filter Control Register */ + + struct + { + __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */ + __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */ + __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */ + __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */ + } CFLCR_M_b; + }; + + union + { + __IOM uint32_t CFSZR_M; /*!< (@ 0x00002034) Capture Filter Size Clip Register */ + + struct + { + __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter + * output size (4-pixel units). */ + uint32_t : 4; + __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output + * size (4-pixel units). */ + uint32_t : 4; + } CFSZR_M_b; + }; + + union + { + __IOM uint32_t CDWDR_M; /*!< (@ 0x00002038) Capture Destination Width Register */ + + struct + { + __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area + * where the captured image is to be stored (4-byte units). */ + uint32_t : 19; + } CDWDR_M_b; + }; + + union + { + __IOM uint32_t CDAYR_M; /*!< (@ 0x0000203C) Capture Data Address Y Register */ + + struct + { + __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR_M_b; + }; + + union + { + __IOM uint32_t CDACR_M; /*!< (@ 0x00002040) Capture Data Address C Register */ + + struct + { + __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */ + } CDACR_M_b; + }; + + union + { + __IOM uint32_t CDBYR_M; /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register */ + + struct + { + __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBYR_M_b; + }; + + union + { + __IOM uint32_t CDBCR_M; /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register */ + + struct + { + __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component + * data of the captured bottom-field data (4-pixel units). */ + } CDBCR_M_b; + }; + + union + { + __IOM uint32_t CBDSR_M; /*!< (@ 0x0000204C) Capture Bundle Destination Size Register */ + + struct + { + __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output + * to the memory in a bundle write. */ + uint32_t : 9; + } CBDSR_M_b; + }; + __IM uint32_t RESERVED12[4]; + + union + { + __IOM uint32_t CLFCR_M; /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register */ + + struct + { + __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */ + uint32_t : 31; + } CLFCR_M_b; + }; + + union + { + __IOM uint32_t CDOCR_M; /*!< (@ 0x00002064) Capture Data Output Control Register */ + + struct + { + __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from + * the CEU. */ + __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from + * the CEU. */ + __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from + * the CEU. */ + uint32_t : 1; + __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data + * captured in the YCbCr422 format to the memory. */ + uint32_t : 11; + __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be + * written to the memory. */ + uint32_t : 15; + } CDOCR_M_b; + }; + __IM uint32_t RESERVED13[10]; + + union + { + __IOM uint32_t CDAYR2_M; /*!< (@ 0x00002090) Capture Data Address Y Register 2 */ + + struct + { + __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */ + } CDAYR2_M_b; + }; + + union + { + __IOM uint32_t CDACR2_M; /*!< (@ 0x00002094) Capture Data Address C Register 2 */ + + struct + { + __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */ + } CDACR2_M_b; + }; + + union + { + __IOM uint32_t CDBYR2_M; /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register + * 2 */ + + struct + { + __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of + * the captured bottom-field data (4-pixel units). */ + } CDBYR2_M_b; + }; + + union + { + __IOM uint32_t CDBCR2_M; /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register + * 2 */ + + struct + { + __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of + * the captured bottom-field data (4-pixel units). */ + } CDBCR2_M_b; + }; +} R_CEU_Type; /*!< Size = 8352 (0x20a0) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ultra-Low Power Timer 0 (R_ULPT0) + */ + +typedef struct /*!< (@ 0x40220000) R_ULPT0 Structure */ +{ + union + { + __IOM uint32_t ULPTCNT; /*!< (@ 0x00000000) ULPT Counter Register */ + + struct + { + __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, the 32-bit counter + * is forcibly stopped and set to FFFFFFFFH. */ + } ULPTCNT_b; + }; + + union + { + __IOM uint32_t ULPTCMA; /*!< (@ 0x00000004) ULPT Compare Match A Register */ + + struct + { + __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMA_b; + }; + + union + { + __IOM uint32_t ULPTCMB; /*!< (@ 0x00000008) ULPT Compare Match B Register */ + + struct + { + __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written + * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */ + } ULPTCMB_b; + }; + + union + { + __IOM uint8_t ULPTCR; /*!< (@ 0x0000000C) ULPT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] ULPT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] ULPT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] ULPT count forced stop */ + uint8_t : 2; + __IOM uint8_t TUNDF : 1; /*!< [5..5] ULPT underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] ULPT compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] ULPT compare match B flag */ + } ULPTCR_b; + }; + + union + { + __IOM uint8_t ULPTMR1; /*!< (@ 0x0000000D) ULPT Mode Register 1 */ + + struct + { + uint8_t : 1; + __IOM uint8_t TMOD1 : 1; /*!< [1..1] ULPT operating mode select */ + uint8_t : 1; + __IOM uint8_t TEDGPL : 1; /*!< [3..3] ULPTEVI edge polarity select */ + uint8_t : 1; + __IOM uint8_t TCK1 : 1; /*!< [5..5] ULPT count source select */ + uint8_t : 2; + } ULPTMR1_b; + }; + + union + { + __IOM uint8_t ULPTMR2; /*!< (@ 0x0000000E) ULPT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] fsub/LOCO count source clock frequency division ratio + * select */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] ULPT Low Power Mode */ + } ULPTMR2_b; + }; + + union + { + __IOM uint8_t ULPTMR3; /*!< (@ 0x0000000F) ULPT Mode Register 3 */ + + struct + { + __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select */ + __IOM uint8_t TEVPOL : 1; /*!< [1..1] ULPTEVI polarity switch */ + __IOM uint8_t TOPOL : 1; /*!< [2..2] ULPTO polarity select */ + uint8_t : 1; + __IOM uint8_t TEECTL : 2; /*!< [5..4] ULPTEE function select */ + __IOM uint8_t TEEPOL : 2; /*!< [7..6] ULPTEE edge polarity select */ + } ULPTMR3_b; + }; + + union + { + __IOM uint8_t ULPTIOC; /*!< (@ 0x00000010) ULPT I/O Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t TOE : 1; /*!< [2..2] ULPTO output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] ULPTEVI input filter select */ + __IOM uint8_t TIOGT0 : 1; /*!< [6..6] ULPTEVI count control */ + uint8_t : 1; + } ULPTIOC_b; + }; + + union + { + __IOM uint8_t ULPTISR; /*!< (@ 0x00000011) ULPT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection */ + uint8_t : 5; + } ULPTISR_b; + }; + + union + { + __IOM uint8_t ULPTCMSR; /*!< (@ 0x00000012) ULPT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] ULPTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] ULPTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] ULPTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] ULPTOB polarity select */ + uint8_t : 1; + } ULPTCMSR_b; + }; + __IM uint8_t RESERVED; +} R_ULPT0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief On-Chip Debug Function (R_DEBUG_OCD) + */ + +typedef struct /*!< (@ 0x40011000) R_DEBUG_OCD Structure */ +{ + union + { + __IM uint32_t MCUERRSTAT; /*!< (@ 0x00000000) MCU Error Status Register */ + + struct + { + __IM uint32_t ZERO : 1; /*!< [0..0] Zeroization status flag */ + uint32_t : 31; + } MCUERRSTAT_b; + }; + + union + { + __IOM uint32_t MCUCTRL; /*!< (@ 0x00000004) MCU Control Register */ + + struct + { + __IOM uint32_t EDBGRQ0 : 1; /*!< [0..0] External Debug Request for CPU0 */ + __IOM uint32_t EDBGRQ1 : 1; /*!< [1..1] External Debug Request for CPU1 */ + uint32_t : 6; + __IOM uint32_t DBIRQ0 : 1; /*!< [8..8] Writing 1 to the bit wakes up the CPU0 from Deep Sleep + * mode or the MCU from Software Standby Mode or Deep Software + * Standby mode */ + __IOM uint32_t DBIRQ1 : 1; /*!< [9..9] Writing 1 to the bit wakes up the CPU1 from Deep Sleep + * mode or the MCU from Software Standby Mode or Deep Software + * Standby mode */ + uint32_t : 6; + __IOM uint32_t CPUWAIT0 : 1; /*!< [16..16] CPU0 WAIT SETTING */ + __IOM uint32_t CPUWAIT1 : 1; /*!< [17..17] CPU1 WAIT SETTING */ + uint32_t : 14; + } MCUCTRL_b; + }; + __IM uint32_t RESERVED[62]; + + union + { + __IOM uint32_t JBMDR; /*!< (@ 0x00000100) JTAG Boot Mode Entry Register */ + + struct + { + __IOM uint32_t KEY : 8; /*!< [7..0] Mode entry key */ + uint32_t : 24; + } JBMDR_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t JBRDR; /*!< (@ 0x00000120) JTAG Boot Receive Data Register */ + + struct + { + __IOM uint32_t RDAT : 32; /*!< [31..0] Received data register */ + } JBRDR_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t JBTDR; /*!< (@ 0x00000130) JTAG Boot Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 32; /*!< [31..0] Transmitted data register */ + } JBTDR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t JBSTR; /*!< (@ 0x00000140) JTAG Boot Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive buffer full */ + __IOM uint32_t TDE : 1; /*!< [1..1] Transmit data empty */ + uint32_t : 30; + } JBSTR_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t JBICR; /*!< (@ 0x00000150) JTAG Boot Interrupt Control Register */ + + struct + { + __IOM uint32_t RDFIE : 1; /*!< [0..0] Receive buffer full interrupt enabled */ + uint32_t : 31; + } JBICR_b; + }; + __IM uint32_t RESERVED5[107]; + + union + { + __IM uint32_t FSBLSTATM; /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register */ + + struct + { + __IM uint32_t CS : 1; /*!< [0..0] FSBL completion status */ + __IM uint32_t RS : 1; /*!< [1..1] FSBL result status */ + uint32_t : 30; + } FSBLSTATM_b; + }; +} R_DEBUG_OCD_Type; /*!< Size = 772 (0x304) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Decryption On The Fly (R_DOTF) + */ + +typedef struct /*!< (@ 0x40268800) R_DOTF Structure */ +{ + union + { + __IOM uint32_t CONVAREAST; /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area */ + } CONVAREAST_b; + }; + + union + { + __IOM uint32_t CONVAREAD; /*!< (@ 0x00000004) DOTF Conversion Area End Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area */ + } CONVAREAD_b; + }; + __IM uint32_t RESERVED[30]; + + union + { + __IOM uint32_t REG00; /*!< (@ 0x00000080) Register 0 */ + + struct + { + uint32_t : 9; + __IOM uint32_t B09 : 1; /*!< [9..9] Bit 09 */ + uint32_t : 6; + __IOM uint32_t B16 : 1; /*!< [16..16] Bit 09 */ + __IOM uint32_t B17 : 1; /*!< [17..17] Bit 17 */ + uint32_t : 2; + __IOM uint32_t B20 : 1; /*!< [20..20] Bit 20 */ + uint32_t : 3; + __IOM uint32_t B24 : 2; /*!< [25..24] Bit24-25 */ + uint32_t : 2; + __IOM uint32_t B28 : 2; /*!< [29..28] Bit28-29 */ + uint32_t : 2; + } REG00_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t REG03; /*!< (@ 0x0000008C) Register 03 */ + + struct + { + __IOM uint32_t B00 : 32; /*!< [31..0] Bit 0 */ + } REG03_b; + }; +} R_DOTF_Type; /*!< Size = 144 (0x90) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTX0) + */ + +typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure */ +{ + union + { + __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */ + __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */ + }; +} R_AGTX0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_COMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Common Agent (R_COMA) + */ + +typedef struct /*!< (@ 0x403C9000) R_COMA Structure */ +{ + union + { + __IM uint32_t RIPV; /*!< (@ 0x00000000) IP Version Register */ + + struct + { + __IM uint32_t TIPV : 4; /*!< [3..0] Top Module IP Version Number */ + __IM uint32_t GWIPV : 4; /*!< [7..4] Gateway CPU Agent IP Version Number */ + __IM uint32_t FWIPV : 4; /*!< [11..8] Forwarding Engine IP Version Number */ + __IM uint32_t EAIPV : 4; /*!< [15..12] Ethernet Agent IP Version Number */ + __IM uint32_t FBIPV : 4; /*!< [19..16] Fabric Bus IP Version Number */ + __IM uint32_t CAIPV : 4; /*!< [23..20] Common Agent IP Version Number */ + uint32_t : 8; + } RIPV_b; + }; + + union + { + __IOM uint32_t RRC; /*!< (@ 0x00000004) Reset Configuration Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Software Reset */ + uint32_t : 31; + } RRC_b; + }; + + union + { + __IOM uint32_t RCEC; /*!< (@ 0x00000008) Clock Enable Configuration Register */ + + struct + { + __IOM uint32_t ACE : 7; /*!< [6..0] Agent Clock Enable */ + uint32_t : 9; + __IOM uint32_t RCE : 1; /*!< [16..16] Clock Enable */ + uint32_t : 15; + } RCEC_b; + }; + + union + { + __IM uint32_t RCDC; /*!< (@ 0x0000000C) Clock Disable Configuration Register */ + + struct + { + __IM uint32_t ACD : 7; /*!< [6..0] Agent Clock Disable */ + uint32_t : 9; + __IM uint32_t RCD : 1; /*!< [16..16] Clock Disable */ + uint32_t : 15; + } RCDC_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t CABPIBWMC[8]; /*!< (@ 0x00000020) Buffer Pool IPV Based Watermark Configuration + * Register [0..7] */ + + struct + { + __IOM uint32_t IBUWMPN : 10; /*!< [9..0] IPV Based Unsecure Watermark Pointer Number */ + uint32_t : 6; + __IOM uint32_t IBSWMPN : 10; /*!< [25..16] IPV Based Secure Watermark Pointer Number */ + uint32_t : 6; + } CABPIBWMC_b[8]; + }; + + union + { + __IOM uint32_t CABPWMLC; /*!< (@ 0x00000040) Buffer Pool Watermark Level Configuration Register */ + + struct + { + __IOM uint32_t WMFL : 13; /*!< [12..0] Watermark Flush Level */ + uint32_t : 3; + __IOM uint32_t WMCL : 13; /*!< [28..16] Watermark Critical Level */ + uint32_t : 3; + } CABPWMLC_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CABPPFLC[2]; /*!< (@ 0x00000050) Buffer Pointer Pause Frame Level [0..1] Configuration + * Register */ + + struct + { + __IOM uint32_t PDL : 13; /*!< [12..0] Pause De-Assertion Level */ + uint32_t : 3; + __IOM uint32_t PAL : 13; /*!< [28..16] Pause Assertion Level */ + uint32_t : 3; + } CABPPFLC_b[2]; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t CABPPWMLC[3]; /*!< (@ 0x00000060) Port [0..2] Buffer Pool Watermark Level Configuration + * Register */ + + struct + { + __IOM uint32_t PWMFL : 13; /*!< [12..0] Watermark Flush Level */ + uint32_t : 3; + __IOM uint32_t PWMCL : 13; /*!< [28..16] Watermark Critical Level */ + uint32_t : 3; + } CABPPWMLC_b[3]; + }; + __IM uint32_t RESERVED3[13]; + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC0; /*!< (@ 0x000000A0) 0 */ + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC1; /*!< (@ 0x000000A8) 1 */ + __IOM R_COMA_CABPPPFLC_Type CABPPPFLC2; /*!< (@ 0x000000B0) 2 */ + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CABPULC[3]; /*!< (@ 0x00000100) Buffer Pointer Utilization Level Configuration + * Register [0..2] */ + + struct + { + __IOM uint32_t MXNPN : 13; /*!< [12..0] Maximum Number of Pointer for Port */ + uint32_t : 3; + __IOM uint32_t MNNPN : 13; /*!< [28..16] Minimum Number of Pointer for Port */ + uint32_t : 3; + } CABPULC_b[3]; + }; + __IM uint32_t RESERVED5[13]; + + union + { + __IOM uint32_t CABPIRM; /*!< (@ 0x00000140) Buffer Pool Initialization Register Monitoring + * Register */ + + struct + { + __IOM uint32_t BPIOG : 1; /*!< [0..0] Buffer Pool Initialization Ongoing */ + __IOM uint32_t BPR : 1; /*!< [1..1] Buffer Pool Ready */ + uint32_t : 30; + } CABPIRM_b; + }; + + union + { + __IM uint32_t CABPPCM; /*!< (@ 0x00000144) Buffer Pool Pointer Count Monitoring Register */ + + struct + { + __IM uint32_t RPC : 13; /*!< [12..0] Remaining Pointer Count */ + uint32_t : 3; + __IM uint32_t TPC : 13; /*!< [28..16] Total Pointer Count */ + uint32_t : 3; + } CABPPCM_b; + }; + + union + { + __IM uint32_t CABPLCM; /*!< (@ 0x00000148) Buffer Pool Pointer Least Count Monitoring Register */ + + struct + { + __IM uint32_t LRC : 13; /*!< [12..0] Least Remaining Pointer Count */ + uint32_t : 19; + } CABPLCM_b; + }; + __IM uint32_t RESERVED6[13]; + + union + { + __IM uint32_t CABPCPM[3]; /*!< (@ 0x00000180) Port [0..2] Buffer Pointer Count Monitoring Register */ + + struct + { + __IM uint32_t RPCP : 13; /*!< [12..0] Received Pointer Count */ + uint32_t : 19; + } CABPCPM_b[3]; + }; + __IM uint32_t RESERVED7[29]; + + union + { + __IM uint32_t CABPMCPM[3]; /*!< (@ 0x00000200) Port [0..2] Buffer Pointer Maximum Count Monitoring + * Register */ + + struct + { + __IM uint32_t RPMCP : 13; /*!< [12..0] Received Pointer Maximum Count */ + uint32_t : 19; + } CABPMCPM_b[3]; + }; + __IM uint32_t RESERVED8[61]; + + union + { + __IM uint32_t CARDNM; /*!< (@ 0x00000300) Rejected Descriptor Number Monitoring Register */ + + struct + { + __IM uint32_t RDNRR : 13; /*!< [12..0] Rejected Descriptor Number in Reject RAM */ + uint32_t : 19; + } CARDNM_b; + }; + + union + { + __IM uint32_t CARDMNM; /*!< (@ 0x00000304) Rejected Descriptor Maximum Number Monitoring + * Register */ + + struct + { + __IM uint32_t RDMNRR : 13; /*!< [12..0] Rejected Descriptor Maximum Number in Reject RAM */ + uint32_t : 19; + } CARDMNM_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IM uint32_t CARDCN; /*!< (@ 0x00000310) Rejected Descriptor Counter Register */ + + struct + { + __IM uint32_t RDN : 32; /*!< [31..0] Rejected Descriptor Number */ + } CARDCN_b; + }; + __IM uint32_t RESERVED10[59]; + + union + { + __IOM uint32_t CAEIS0; /*!< (@ 0x00000400) Error Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t PECCES : 1; /*!< [0..0] Pointer ECC Error Interrupt Status */ + __IOM uint32_t DSECCES : 1; /*!< [1..1] Descriptor ECC Error Interrupt Status */ + __IOM uint32_t BPECCES : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Status */ + uint32_t : 5; + __IOM uint32_t BPOPS : 1; /*!< [8..8] Buffer Pool Out of Pointer Status */ + __IOM uint32_t WMCLOS : 1; /*!< [9..9] Watermark Critical Level Overtook Status */ + __IOM uint32_t WMFLOS : 1; /*!< [10..10] Watermark Flush Level Overtook Status */ + uint32_t : 5; + __IM uint32_t EEIPLN : 4; /*!< [19..16] ECC Error Inducing Pointer Loss Number */ + uint32_t : 12; + } CAEIS0_b; + }; + + union + { + __IOM uint32_t CAEIE0; /*!< (@ 0x00000404) Error Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t PECCEE : 1; /*!< [0..0] Pointer ECC Error Interrupt Enable */ + __IOM uint32_t DSECCEE : 1; /*!< [1..1] Descriptor ECC Error Interrupt Enable */ + __IOM uint32_t BPECCEE : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t BPOPE : 1; /*!< [8..8] Buffer Pool Out of Pointer Enable */ + __IOM uint32_t WMCLOE : 1; /*!< [9..9] Watermark Critical Level Overtook Enable */ + __IOM uint32_t WMFLOE : 1; /*!< [10..10] Watermark Flush Level Overtook Enable */ + uint32_t : 21; + } CAEIE0_b; + }; + + union + { + __IM uint32_t CAEID0; /*!< (@ 0x00000408) Error Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t PECCED : 1; /*!< [0..0] Pointer ECC Error Interrupt Disable */ + __IM uint32_t DSECCED : 1; /*!< [1..1] Descriptor ECC Error Interrupt Disable */ + __IM uint32_t BPECCED : 1; /*!< [2..2] Buffer Pool ECC Error Interrupt Disable */ + uint32_t : 5; + __IM uint32_t BPOPD : 1; /*!< [8..8] Buffer Pool Out of Pointer Disable */ + __IM uint32_t WMCLOD : 1; /*!< [9..9] Watermark Critical Level Overtook Disable */ + __IM uint32_t WMFLOD : 1; /*!< [10..10] Watermark Flush Level Overtook Disable */ + uint32_t : 21; + } CAEID0_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CAEIS1; /*!< (@ 0x00000410) Error Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t PWMCLOS : 7; /*!< [6..0] Port Watermark Critical Level Overtook Status */ + uint32_t : 9; + __IOM uint32_t PWMFLOS : 7; /*!< [22..16] Port Watermark Flush Level Overtook Status */ + uint32_t : 9; + } CAEIS1_b; + }; + + union + { + __IOM uint32_t CAEIE1; /*!< (@ 0x00000414) Error Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t PWMCLOE : 7; /*!< [6..0] Port Watermark Critical Level Overtook Enable */ + uint32_t : 9; + __IOM uint32_t PWMFLOE : 7; /*!< [22..16] Port Watermark Flush Level Overtook Enable */ + uint32_t : 9; + } CAEIE1_b; + }; + + union + { + __IM uint32_t CAEID1; /*!< (@ 0x00000418) Error Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t PWMCLOD : 7; /*!< [6..0] Port Watermark Critical Level Overtook Disable */ + uint32_t : 9; + __IM uint32_t PWMFLOD : 7; /*!< [22..16] Port Watermark Flush Level Overtook Disable */ + uint32_t : 9; + } CAEID1_b; + }; + __IM uint32_t RESERVED12[9]; + + union + { + __IOM uint32_t CAMIS0; /*!< (@ 0x00000440) Monitoring Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t PFS : 2; /*!< [1..0] Pause Frame Status */ + uint32_t : 30; + } CAMIS0_b; + }; + + union + { + __IOM uint32_t CAMIE0; /*!< (@ 0x00000444) Monitoring Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t PFE : 2; /*!< [1..0] Pause Frame Enable */ + uint32_t : 30; + } CAMIE0_b; + }; + + union + { + __IM uint32_t CAMID0; /*!< (@ 0x00000448) Monitoring Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t PFD : 2; /*!< [1..0] Pause Frame Disable */ + uint32_t : 30; + } CAMID0_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t CAMIS1; /*!< (@ 0x00000450) Monitoring Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t PPFS : 14; /*!< [13..0] Port Pause Frame Status */ + uint32_t : 18; + } CAMIS1_b; + }; + + union + { + __IOM uint32_t CAMIE1; /*!< (@ 0x00000454) Monitoring Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t PPFE : 14; /*!< [13..0] Port Pause Frame Enable */ + uint32_t : 18; + } CAMIE1_b; + }; + + union + { + __IM uint32_t CAMID1; /*!< (@ 0x00000458) Monitoring Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t PPFD : 14; /*!< [13..0] Port Pause Frame Disable */ + uint32_t : 18; + } CAMID1_b; + }; +} R_COMA_Type; /*!< Size = 1116 (0x45c) */ + +/* =========================================================================================================================== */ +/* ================ R_CPU_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Individual CPU Control (R_CPU_CTRL) + */ + +typedef struct /*!< (@ 0x4000F000) R_CPU_CTRL Structure */ +{ + __IM uint32_t RESERVED[12]; + + union + { + __IOM uint8_t CPU0LCKUPCR; /*!< (@ 0x00000030) CPU0 Lockup Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection of CPUn lockup */ + uint8_t : 7; + } CPU0LCKUPCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t CPU1LCKUPCR; /*!< (@ 0x00000034) CPU1 Lockup Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection of CPUn lockup */ + uint8_t : 7; + } CPU1LCKUPCR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t CPU0INITVTOR; /*!< (@ 0x00000040) CPU0 Initial Vector Base Address Register */ + + struct + { + __IOM uint32_t CPUnINITVTOR : 32; /*!< [31..0] CPUn Initial Vector Base Address */ + } CPU0INITVTOR_b; + }; + + union + { + __IOM uint32_t CPU1INITVTOR; /*!< (@ 0x00000044) CPU1 Initial Vector Base Address Register */ + + struct + { + __IOM uint32_t CPUnINITVTOR : 32; /*!< [31..0] CPUn Initial Vector Base Address */ + } CPU1INITVTOR_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint8_t CPU0WAITCR; /*!< (@ 0x00000050) CPU0 CPUWAIT Control Register */ + + struct + { + __IOM uint8_t CPUWAIT : 1; /*!< [0..0] Writing 1 to stall the CPUn when it is out of reset */ + uint8_t : 7; + } CPU0WAITCR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t CPU1WAITCR; /*!< (@ 0x00000054) CPU1 CPUWAIT Control Register */ + + struct + { + __IOM uint8_t CPUWAIT : 1; /*!< [0..0] Writing 1 to stall the CPUn when it is out of reset */ + uint8_t : 7; + } CPU1WAITCR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint16_t CPU0ACTCSR; /*!< (@ 0x00000060) CPU0 Activation Control and Status Register */ + + struct + { + __IOM uint16_t ACTREQ : 1; /*!< [0..0] CPUn activation request */ + uint16_t : 6; + __IM uint16_t ACT : 1; /*!< [7..7] CPUn activation state */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key code */ + } CPU0ACTCSR_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t CPU1ACTCSR; /*!< (@ 0x00000064) CPU1 Activation Control and Status Register */ + + struct + { + __IOM uint16_t ACTREQ : 1; /*!< [0..0] CPUn activation request */ + uint16_t : 6; + __IM uint16_t ACT : 1; /*!< [7..7] CPUn activation state */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key code */ + } CPU1ACTCSR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[2]; + + union + { + __IOM uint8_t CPU0LMECR; /*!< (@ 0x00000070) CPU0 Local Memory Error Control Register */ + + struct + { + __IOM uint8_t SYRSTEN : 1; /*!< [0..0] System Reset request enable */ + uint8_t : 7; + } CPU0LMECR_b; + }; + __IM uint8_t RESERVED15; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17; + + union + { + __IOM uint8_t CPUIDR; /*!< (@ 0x00000078) CPU Identification Register */ + + struct + { + __IM uint8_t CPUID : 1; /*!< [0..0] CPU Identification */ + uint8_t : 7; + } CPUIDR_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20; + + union + { + __IOM uint8_t CPU0STATM; /*!< (@ 0x00000080) CPU0 Status Monitor Register */ + + struct + { + __IM uint8_t SLEEPING : 1; /*!< [0..0] Sleeping State */ + __IM uint8_t SLEEPDEEP : 1; /*!< [1..1] Indicates that the processor is at a Deep Sleep mode */ + uint8_t : 2; + __IM uint8_t SAHBSTP : 1; /*!< [4..4] S-AHB Status Flag */ + uint8_t : 3; + } CPU0STATM_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IOM uint8_t CPU1STATM; /*!< (@ 0x00000084) CPU1 Status Monitor Register */ + + struct + { + __IM uint8_t SLEEPING : 1; /*!< [0..0] Sleeping State */ + __IM uint8_t SLEEPDEEP : 1; /*!< [1..1] Indicates that the processor is at a Deep Sleep mode */ + uint8_t : 2; + __IM uint8_t SAHBSTP : 1; /*!< [4..4] S-AHB Status Flag */ + uint8_t : 3; + } CPU1STATM_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[2]; + + union + { + __IOM uint8_t SECEXTMON; /*!< (@ 0x00000090) CPU SECEXT Monitor Register */ + + struct + { + __IM uint8_t SECEXT0 : 1; /*!< [0..0] CPU0 Security Extension */ + __IM uint8_t SECEXT1 : 1; /*!< [1..1] CPU1 Security Extension */ + uint8_t : 6; + } SECEXTMON_b; + }; + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + + union + { + __IOM uint32_t NSCPUCR; /*!< (@ 0x00000094) Non-secure CPU Control Register */ + + struct + { + __IOM uint32_t RSTREQEN : 1; /*!< [0..0] System Reset Request Enable */ + uint32_t : 31; + } NSCPUCR_b; + }; + __IM uint32_t RESERVED28[218]; + + union + { + __IOM uint8_t CPU0LOCKCR; /*!< (@ 0x00000400) CPU0 Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKSVTAIR : 1; /*!< [0..0] Disables writes to secure registers VTOR_S, AIRCR.PRIS, + * AIRCR.BFHFNMINS */ + __IOM uint8_t LCKSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Secure MPU region */ + __IOM uint8_t LCKSAU : 1; /*!< [2..2] Disables writes to registers that are associated with + * the SAU region */ + __IOM uint8_t LCKITGU : 1; /*!< [3..3] Disables writes to registers that are associated with + * the ITCM interface */ + __IOM uint8_t LCKDTGU : 1; /*!< [4..4] Disables writes to registers that are associated with + * the DTCM interface */ + __IOM uint8_t LCKDCAIC : 1; /*!< [5..5] Disable access to the instruction cache direct cache + * access registers DCAICLR and DCAICRR */ + uint8_t : 2; + } CPU0LOCKCR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + + union + { + __IOM uint8_t CPU1LOCKCR; /*!< (@ 0x00000404) CPU1 Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKSVTAIR : 1; /*!< [0..0] Disables writes to secure registers VTOR_S, AIRCR.PRIS, + * AIRCR.BFHFNMINS */ + __IOM uint8_t LCKSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Secure MPU region */ + __IOM uint8_t LCKSAU : 1; /*!< [2..2] Disables writes to registers that are associated with + * the SAU region */ + __IOM uint8_t LCKITGU : 1; /*!< [3..3] Disables writes to registers that are associated with + * the ITCM interface */ + __IOM uint8_t LCKDTGU : 1; /*!< [4..4] Disables writes to registers that are associated with + * the DTCM interface */ + __IOM uint8_t LCKDCAIC : 1; /*!< [5..5] Disable access to the instruction cache direct cache + * access registers DCAICLR and DCAICRR */ + uint8_t : 2; + } CPU1LOCKCR_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33[62]; + + union + { + __IOM uint8_t CPU0LOCKCRNS; /*!< (@ 0x00000500) CPU0 Non-secure Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKNSVTOR : 1; /*!< [0..0] Disables writes to the VTOR_NS register */ + __IOM uint8_t LCKNSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Non-secure MPU region */ + uint8_t : 6; + } CPU0LOCKCRNS_b; + }; + __IM uint8_t RESERVED34; + __IM uint16_t RESERVED35; + + union + { + __IOM uint8_t CPU1LOCKCRNS; /*!< (@ 0x00000504) CPU1 Non-secure Function Lock Control Register */ + + struct + { + __IOM uint8_t LCKNSVTOR : 1; /*!< [0..0] Disables writes to the VTOR_NS register */ + __IOM uint8_t LCKNSMPU : 1; /*!< [1..1] Disables writes to registers that are associated with + * the Non-secure MPU region */ + uint8_t : 6; + } CPU1LOCKCRNS_b; + }; + __IM uint8_t RESERVED36; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[206]; + + union + { + __IOM uint16_t CPU0CRPT; /*!< (@ 0x00000840) CPU0 Control Register Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key to enable/disable writing to PROTECT */ + } CPU0CRPT_b; + }; + __IM uint16_t RESERVED39; + + union + { + __IOM uint16_t CPU1CRPT; /*!< (@ 0x00000844) CPU1 Control Register Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Key to enable/disable writing to PROTECT */ + } CPU1CRPT_b; + }; + __IM uint16_t RESERVED40; +} R_CPU_CTRL_Type; /*!< Size = 2120 (0x848) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CANFD ECC (R_ECCMB0) + */ + +typedef struct /*!< (@ 0x4036F200) R_ECCMB0 Structure */ +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Message Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] ECC Error Detection and Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] ECC 1-bit Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] ECC 2-bit Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] ECC 1-bit Error Correction Permission */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Judgment Enable Flag */ + uint32_t : 2; + __IOM uint32_t ECER1C : 1; /*!< [9..9] Accumulating ECC Error Detection and Correction Flag + * Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-bit ECC Error Detection Flag Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Overflow Detection Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Select bit */ + __IM uint32_t ECSEDF0 : 1; /*!< [16..16] ECC Single bit Error Address Detection Flag */ + __IM uint32_t ECDEDF0 : 1; /*!< [17..17] ECC Dual Bit Error Address Detection Flag */ + uint32_t : 14; + } EC710CTL_b; + }; + + union + { + __IOM uint16_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + uint16_t : 5; + __IOM uint16_t ECTMCE : 1; /*!< [7..7] ECC Test Mode Control Enable */ + uint16_t : 6; + __IOM uint16_t ETMA : 2; /*!< [15..14] ECC Test Mode Bit Access Control */ + } EC710TMC_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Test Substitute Data Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] ECC Test Substitute Data */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD0; /*!< (@ 0x00000010) ECC Error Address Register */ + + struct + { + __IM uint32_t ECEAD : 10; /*!< [9..0] ECC Error Address */ + uint32_t : 22; + } EC710EAD0_b; + }; +} R_ECCMB0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_ESWM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Layer 3 Ethernet Switch Module (R_ESWM) + */ + +typedef struct /*!< (@ 0x403C8000) R_ESWM Structure */ +{ + union + { + __IOM uint32_t TPEMIMC0; /*!< (@ 0x00000000) Error and Monitoring Interrupt Mapping Configuration + * Register 0 */ + + struct + { + __IOM uint32_t SEIM : 1; /*!< [0..0] Switch Error Interrupt Mapping */ + __IOM uint32_t SEIGM : 1; /*!< [1..1] Switch Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SEICM : 3; /*!< [6..4] Switch Error Interrupt Core Mapping */ + uint32_t : 9; + __IOM uint32_t SSIM0 : 1; /*!< [16..16] Switch Status Interrupt 0 Mapping */ + __IOM uint32_t SSIGM0 : 1; /*!< [17..17] Switch Status Interrupt 0 GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SSICM0 : 3; /*!< [22..20] Switch Status Interrupt 0 Core Mapping */ + uint32_t : 1; + __IOM uint32_t SSIM1 : 1; /*!< [24..24] Switch Status Interrupt 1 Mapping */ + __IOM uint32_t SSIGM1 : 1; /*!< [25..25] Switch Status Interrupt 1 GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t SSICM1 : 3; /*!< [30..28] Switch Status Interrupt 1 Core Mapping */ + uint32_t : 1; + } TPEMIMC0_b; + }; + + union + { + __IOM uint32_t TPEMIMC1; /*!< (@ 0x00000004) Error and Monitoring Interrupt Mapping Configuration + * Register 1 */ + + struct + { + __IOM uint32_t FEIM : 1; /*!< [0..0] MFWD Error Interrupt Mapping */ + __IOM uint32_t FEIGM : 1; /*!< [1..1] MFWD Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t FEICM : 3; /*!< [6..4] MFWD Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t FSIM : 1; /*!< [8..8] MFWD Status Interrupt Mapping */ + __IOM uint32_t FSIGM : 1; /*!< [9..9] MFWD Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t FSICM : 3; /*!< [14..12] MFWD Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t CEIM : 1; /*!< [16..16] COMA Error Interrupt Mapping */ + __IOM uint32_t CEIGM : 1; /*!< [17..17] COMA Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t CEICM : 3; /*!< [22..20] COMA Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t CSIM : 1; /*!< [24..24] COMA Status Interrupt Mapping */ + __IOM uint32_t CSIGM : 1; /*!< [25..25] COMA Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t CSICM : 3; /*!< [30..28] COMA Status Interrupt Core Mapping */ + uint32_t : 1; + } TPEMIMC1_b; + }; + + union + { + __IOM uint32_t TPEMIMC2; /*!< (@ 0x00000008) Error and Monitoring Interrupt Mapping Configuration + * Register 2 */ + + struct + { + __IOM uint32_t GEIM0 : 1; /*!< [0..0] GWCA0 Error Interrupt Mapping */ + __IOM uint32_t GEIGM0 : 1; /*!< [1..1] GWCA0 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t GEICM0 : 3; /*!< [6..4] GWCA0 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t GSIM0 : 1; /*!< [8..8] GWCA0 Status Interrupt Mapping */ + __IOM uint32_t GSIGM0 : 1; /*!< [9..9] GWCA0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t GSICM0 : 3; /*!< [14..12] GWCA0 Status Interrupt Core Mapping */ + uint32_t : 17; + } TPEMIMC2_b; + }; + + union + { + __IOM uint32_t TPEMIMC3; /*!< (@ 0x0000000C) Error and Monitoring Interrupt Mapping Configuration + * Register 3 */ + + struct + { + __IOM uint32_t EEIM0 : 1; /*!< [0..0] ETHA0 Error Interrupt Mapping */ + __IOM uint32_t EEIGM0 : 1; /*!< [1..1] ETHA0 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t EEICM0 : 3; /*!< [6..4] ETHA0 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t ESIM0 : 1; /*!< [8..8] ETHA0 Status Interrupt Mapping */ + __IOM uint32_t ESIGM0 : 1; /*!< [9..9] ETHA0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t ESICM0 : 3; /*!< [14..12] ETHA0 Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t RSIM0 : 1; /*!< [16..16] RMAC0 Status Interrupt Mapping */ + __IOM uint32_t RSIGM0 : 1; /*!< [17..17] RMAC0 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t RSICM0 : 3; /*!< [22..20] RMAC0 Status Interrupt Core Mapping */ + uint32_t : 9; + } TPEMIMC3_b; + }; + + union + { + __IOM uint32_t TPEMIMC4; /*!< (@ 0x00000010) Error and Monitoring Interrupt Mapping Configuration + * Register 4 */ + + struct + { + __IOM uint32_t EEIM1 : 1; /*!< [0..0] ETHA1 Error Interrupt Mapping */ + __IOM uint32_t EEIGM1 : 1; /*!< [1..1] ETHA1 Error Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t EEICM1 : 3; /*!< [6..4] ETHA1 Error Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t ESIM1 : 1; /*!< [8..8] ETHA1 Status Interrupt Mapping */ + __IOM uint32_t ESIGM1 : 1; /*!< [9..9] ETHA1 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t ESICM1 : 3; /*!< [14..12] ETHA1 Status Interrupt Core Mapping */ + uint32_t : 1; + __IOM uint32_t RSIM1 : 1; /*!< [16..16] RMAC1 Status Interrupt Mapping */ + __IOM uint32_t RSIGM1 : 1; /*!< [17..17] RMAC1 Status Interrupt GWCA Mapping */ + uint32_t : 2; + __IOM uint32_t RSICM1 : 3; /*!< [22..20] RMAC1 Status Interrupt Core Mapping */ + uint32_t : 9; + } TPEMIMC4_b; + }; + __IM uint32_t RESERVED[27]; + + union + { + __IOM uint32_t TPEMIMC60; /*!< (@ 0x00000080) Error and Monitoring Interrupt Mapping Configuration + * Register 60 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC60_b; + }; + + union + { + __IOM uint32_t TPEMIMC61; /*!< (@ 0x00000084) Error and Monitoring Interrupt Mapping Configuration + * Register 61 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC61_b; + }; + + union + { + __IOM uint32_t TPEMIMC62; /*!< (@ 0x00000088) Error and Monitoring Interrupt Mapping Configuration + * Register 62 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC62_b; + }; + + union + { + __IOM uint32_t TPEMIMC63; /*!< (@ 0x0000008C) Error and Monitoring Interrupt Mapping Configuration + * Register 63 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC63_b; + }; + + union + { + __IOM uint32_t TPEMIMC64; /*!< (@ 0x00000090) Error and Monitoring Interrupt Mapping Configuration + * Register 64 */ + + struct + { + __IOM uint32_t GTSIM0 : 1; /*!< [0..0] GWCA0 Timestamp Interrupt Mapping */ + __IOM uint32_t GTSICM0 : 3; /*!< [3..1] GWCA0 Timestamp Interrupt Core Mapping */ + uint32_t : 28; + } TPEMIMC64_b; + }; + __IM uint32_t RESERVED1[27]; + + union + { + __IOM uint32_t TPEMIMC70; /*!< (@ 0x00000100) Error and Monitoring Interrupt Mapping Configuration + * Register 70 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC70_b; + }; + + union + { + __IOM uint32_t TPEMIMC71; /*!< (@ 0x00000104) Error and Monitoring Interrupt Mapping Configuration + * Register 71 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC71_b; + }; + + union + { + __IOM uint32_t TPEMIMC72; /*!< (@ 0x00000108) Error and Monitoring Interrupt Mapping Configuration + * Register 72 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC72_b; + }; + + union + { + __IOM uint32_t TPEMIMC73; /*!< (@ 0x0000010C) Error and Monitoring Interrupt Mapping Configuration + * Register 73 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC73_b; + }; + + union + { + __IOM uint32_t TPEMIMC74; /*!< (@ 0x00000110) Error and Monitoring Interrupt Mapping Configuration + * Register 74 */ + + struct + { + __IOM uint32_t GDICM0 : 3; /*!< [2..0] GWCA0 Data Interrupt Core Mapping */ + uint32_t : 29; + } TPEMIMC74_b; + }; + __IM uint32_t RESERVED2[379]; + + union + { + __IM uint32_t TSIM; /*!< (@ 0x00000700) Summarized Interrupt Mirroring Register */ + + struct + { + __IM uint32_t FIM : 1; /*!< [0..0] MFWD Interrupt Mirroring */ + __IM uint32_t CIM : 1; /*!< [1..1] COMA Interrupt Mirroring */ + __IM uint32_t GIM0 : 1; /*!< [2..2] GWCA0 Interrupt Monitoring */ + __IM uint32_t GIM1 : 1; /*!< [3..3] GWCA1 Interrupt Monitoring */ + __IM uint32_t EIM0 : 1; /*!< [4..4] ETHA0 Interrupt Monitoring */ + __IM uint32_t EIM1 : 1; /*!< [5..5] ETHA1 Interrupt Monitoring */ + __IM uint32_t EIM2 : 1; /*!< [6..6] ETHA2 Interrupt Monitoring */ + uint32_t : 25; + } TSIM_b; + }; + + union + { + __IM uint32_t TFIM; /*!< (@ 0x00000704) MFWD Interrupt Mirroring Register */ + + struct + { + __IM uint32_t FWEISIM0 : 1; /*!< [0..0] FWEIS0 Interrupt Mirroring */ + __IM uint32_t FWEISIM1 : 1; /*!< [1..1] FWEIS1 Interrupt Mirroring */ + __IM uint32_t FWEISIM2 : 1; /*!< [2..2] FWEIS2 Interrupt Mirroring */ + __IM uint32_t FWEISIM3 : 1; /*!< [3..3] FWEIS3 Interrupt Mirroring */ + __IM uint32_t FWEISIM4 : 1; /*!< [4..4] FWEIS4 Interrupt Mirroring */ + __IM uint32_t FWEISIM5 : 1; /*!< [5..5] FWEIS5 Interrupt Mirroring */ + __IM uint32_t FWEISIM6 : 1; /*!< [6..6] FWEIS6 Interrupt Mirroring */ + __IM uint32_t FWEISIM7 : 1; /*!< [7..7] FWEIS7 Interrupt Mirroring */ + __IM uint32_t FWEISIM8 : 1; /*!< [8..8] FWEIS8 Interrupt Mirroring */ + __IM uint32_t FWMISIM0 : 1; /*!< [9..9] FWMIS0 Interrupt Mirroring */ + uint32_t : 22; + } TFIM_b; + }; + + union + { + __IM uint32_t TCIM; /*!< (@ 0x00000708) COMA Interrupt Mirroring Register */ + + struct + { + __IM uint32_t RSSISIM : 1; /*!< [0..0] RSSIS Interrupt Mirroring */ + __IM uint32_t CAEISIM0 : 1; /*!< [1..1] CAEIS0 Interrupt Mirroring */ + __IM uint32_t CAEISIM1 : 1; /*!< [2..2] CAEIS1 Interrupt Mirroring */ + __IM uint32_t CAMISIM0 : 1; /*!< [3..3] CAMIS0 Interrupt Mirroring */ + __IM uint32_t CAMISIM1 : 1; /*!< [4..4] CAMIS1 Interrupt Mirroring */ + uint32_t : 27; + } TCIM_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t TGIM0; /*!< (@ 0x00000710) GWCA0 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t GWDISIM : 1; /*!< [0..0] GWDIS Interrupt Mirroring */ + __IM uint32_t GWTSDISIM : 1; /*!< [1..1] GWTSDIS Interrupt Mirroring */ + __IM uint32_t GWEISIM0 : 1; /*!< [2..2] GWEIS0 Interrupt Mirroring */ + __IM uint32_t GWEISIM1 : 1; /*!< [3..3] GWEIS1 Interrupt Mirroring */ + __IM uint32_t GWEISIM2 : 1; /*!< [4..4] GWEIS2 Interrupt Mirroring */ + __IM uint32_t GWEISIM3 : 1; /*!< [5..5] GWEIS3 Interrupt Mirroring */ + __IM uint32_t GWEISIM4 : 1; /*!< [6..6] GWEIS4 Interrupt Mirroring */ + __IM uint32_t GWEISIM5 : 1; /*!< [7..7] GWEIS5 Interrupt Mirroring */ + uint32_t : 24; + } TGIM0_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IM uint32_t TEIM0; /*!< (@ 0x00000720) ETHA0 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t EAEISIM0 : 1; /*!< [0..0] EAEIS0 Interrupt Mirroring */ + __IM uint32_t EAEISIM1 : 1; /*!< [1..1] EAEIS1 Interrupt Mirroring */ + __IM uint32_t EAEISIM2 : 1; /*!< [2..2] EAEIS2 Interrupt Mirroring */ + __IM uint32_t MEISIM : 1; /*!< [3..3] MEIS Interrupt Mirroring */ + __IM uint32_t MMISIM : 1; /*!< [4..4] MMIS0 Interrupt Mirroring */ + uint32_t : 27; + } TEIM0_b; + }; + + union + { + __IM uint32_t TEIM1; /*!< (@ 0x00000724) ETHA1 Interrupt Mirroring Register */ + + struct + { + __IM uint32_t EAEISIM0 : 1; /*!< [0..0] EAEIS0 Interrupt Mirroring */ + __IM uint32_t EAEISIM1 : 1; /*!< [1..1] EAEIS1 Interrupt Mirroring */ + __IM uint32_t EAEISIM2 : 1; /*!< [2..2] EAEIS2 Interrupt Mirroring */ + __IM uint32_t MEISIM : 1; /*!< [3..3] MEIS Interrupt Mirroring */ + __IM uint32_t MMISIM : 1; /*!< [4..4] MMIS0 Interrupt Mirroring */ + uint32_t : 27; + } TEIM1_b; + }; + __IM uint32_t RESERVED5[25398]; + + union + { + __IOM uint32_t MIIRR; /*!< (@ 0x00019400) Media Interface Reset Register */ + + struct + { + __IOM uint32_t RGRST0 : 1; /*!< [0..0] RGMII0 Interface Reset */ + __IOM uint32_t RGRST1 : 1; /*!< [1..1] RGMII1 Interface Reset */ + uint32_t : 6; + __IOM uint32_t RMRST0 : 1; /*!< [8..8] RMII0 Interface Reset */ + __IOM uint32_t RMRST1 : 1; /*!< [9..9] RMII1 Interface Reset */ + uint32_t : 22; + } MIIRR_b; + }; + + union + { + __IOM uint32_t MIICR0; /*!< (@ 0x00019404) Media Interface Control Register 0 */ + + struct + { + __IOM uint32_t MIISEL : 2; /*!< [1..0] MII Select */ + uint32_t : 6; + __IOM uint32_t DIVSTP : 1; /*!< [8..8] Clock Divider Stop */ + uint32_t : 3; + __IOM uint32_t TXCIDE : 1; /*!< [12..12] TXC Internal Delay Enable in RGMII */ + uint32_t : 19; + } MIICR0_b; + }; + + union + { + __IOM uint32_t MIICR1; /*!< (@ 0x00019408) Media Interface Control Register 1 */ + + struct + { + __IOM uint32_t MIISEL : 2; /*!< [1..0] MII Select */ + uint32_t : 6; + __IOM uint32_t DIVSTP : 1; /*!< [8..8] Clock Divider Stop */ + uint32_t : 3; + __IOM uint32_t TXCIDE : 1; /*!< [12..12] TXC Internal Delay Enable in RGMII */ + uint32_t : 19; + } MIICR1_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t MCCESR; /*!< (@ 0x00019410) Media Clock Capture Event Select Register */ + + struct + { + __IOM uint32_t MCCES0 : 1; /*!< [0..0] Media Clock Capture Event Select 0 */ + __IOM uint32_t MCCES1 : 1; /*!< [1..1] Media Clock Capture Event Select 1 */ + uint32_t : 30; + } MCCESR_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t TASSTSR; /*!< (@ 0x00019420) TAS Status Monitor Signal Select Register */ + + struct + { + __IOM uint32_t MSS0 : 5; /*!< [4..0] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state[8 + * 0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS1 : 5; /*!< [12..8] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state[ + * :0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS2 : 5; /*!< [20..16] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state + * 8:0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + __IOM uint32_t MSS3 : 5; /*!< [28..24] Select signal to output ET_TAS_STA pin from race_etha0_tas_gate_state + * 8:0] and race_etha1_tas_gate_state[8:0] */ + uint32_t : 3; + } TASSTSR_b; + }; +} R_ESWM_Type; /*!< Size = 103460 (0x19424) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Agent (R_ETHA0) + */ + +typedef struct /*!< (@ 0x403CA000) R_ETHA0 Structure */ +{ + union + { + __IOM uint32_t EAMC; /*!< (@ 0x00000000) Ethernet Agent Mode Configuration Register (EAMC) */ + + struct + { + __IOM uint32_t OPC : 2; /*!< [1..0] OPC */ + uint32_t : 30; + } EAMC_b; + }; + + union + { + __IOM uint32_t EAMS; /*!< (@ 0x00000004) Ethernet Agent Mode Status Register (EAMS) */ + + struct + { + __IOM uint32_t OPS : 2; /*!< [1..0] OPS */ + uint32_t : 30; + } EAMS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t EAIRC; /*!< (@ 0x00000010) Ethernet Agent IPV Remapping Configuration Register + * [802.1Q] (EAIRC) */ + + struct + { + __IOM uint32_t IPVR0 : 3; /*!< [2..0] IPVR0 */ + uint32_t : 1; + __IOM uint32_t IPVR1 : 3; /*!< [6..4] IPVR1 */ + uint32_t : 1; + __IOM uint32_t IPVR2 : 3; /*!< [10..8] IPVR2 */ + uint32_t : 1; + __IOM uint32_t IPVR3 : 3; /*!< [14..12] IPVR3 */ + uint32_t : 1; + __IOM uint32_t IPVR4 : 3; /*!< [18..16] IPVR4 */ + uint32_t : 1; + __IOM uint32_t IPVR5 : 3; /*!< [22..20] IPVR5 */ + uint32_t : 1; + __IOM uint32_t IPVR6 : 3; /*!< [26..24] IPVR6 */ + uint32_t : 1; + __IOM uint32_t IPVR7 : 3; /*!< [30..28] IPVR7 */ + uint32_t : 1; + } EAIRC_b; + }; + + union + { + __IOM uint32_t EATDQSC; /*!< (@ 0x00000014) Ethernet Agent TX Descriptor Queue Security Configuration + * Register (EATDQSC) */ + + struct + { + __IOM uint32_t TDQSL0 : 1; /*!< [0..0] TDQSL0 */ + __IOM uint32_t TDQSL1 : 1; /*!< [1..1] TDQSL1 */ + __IOM uint32_t TDQSL2 : 1; /*!< [2..2] TDQSL2 */ + __IOM uint32_t TDQSL3 : 1; /*!< [3..3] TDQSL3 */ + __IOM uint32_t TDQSL4 : 1; /*!< [4..4] TDQSL4 */ + __IOM uint32_t TDQSL5 : 1; /*!< [5..5] TDQSL5 */ + __IOM uint32_t TDQSL6 : 1; /*!< [6..6] TDQSL6 */ + __IOM uint32_t TDQSL7 : 1; /*!< [7..7] TDQSL7 */ + uint32_t : 24; + } EATDQSC_b; + }; + + union + { + __IOM uint32_t EATDQC; /*!< (@ 0x00000018) Ethernet Agent TX Descriptor Queue Configuration + * Register (EATDQC) */ + + struct + { + __IOM uint32_t TDQD0 : 1; /*!< [0..0] TDQD0 */ + __IOM uint32_t TDQD1 : 1; /*!< [1..1] TDQD1 */ + __IOM uint32_t TDQD2 : 1; /*!< [2..2] TDQD2 */ + __IOM uint32_t TDQD3 : 1; /*!< [3..3] TDQD3 */ + __IOM uint32_t TDQD4 : 1; /*!< [4..4] TDQD4 */ + __IOM uint32_t TDQD5 : 1; /*!< [5..5] TDQD5 */ + __IOM uint32_t TDQD6 : 1; /*!< [6..6] TDQD6 */ + __IOM uint32_t TDQD7 : 1; /*!< [7..7] TDQD7 */ + __IOM uint32_t TCTDQD : 1; /*!< [8..8] TCTDQD */ + uint32_t : 7; + __IOM uint32_t TDQP0 : 1; /*!< [16..16] TDQP0 */ + __IOM uint32_t TDQP1 : 1; /*!< [17..17] TDQP1 */ + __IOM uint32_t TDQP2 : 1; /*!< [18..18] TDQP2 */ + __IOM uint32_t TDQP3 : 1; /*!< [19..19] TDQP3 */ + __IOM uint32_t TDQP4 : 1; /*!< [20..20] TDQP4 */ + __IOM uint32_t TDQP5 : 1; /*!< [21..21] TDQP5 */ + __IOM uint32_t TDQP6 : 1; /*!< [22..22] TDQP6 */ + __IOM uint32_t TDQP7 : 1; /*!< [23..23] TDQP7 */ + uint32_t : 8; + } EATDQC_b; + }; + + union + { + __IOM uint32_t EATDQAC; /*!< (@ 0x0000001C) Ethernet Agent TX Descriptor Queue Arbitration + * Configuration Register (EATDQAC) */ + + struct + { + __IOM uint32_t TDQA0 : 4; /*!< [3..0] TDQA0 */ + __IOM uint32_t TDQA1 : 4; /*!< [7..4] TDQA1 */ + __IOM uint32_t TDQA2 : 4; /*!< [11..8] TDQA2 */ + __IOM uint32_t TDQA3 : 4; /*!< [15..12] TDQA3 */ + __IOM uint32_t TDQA4 : 4; /*!< [19..16] TDQA4 */ + __IOM uint32_t TDQA5 : 4; /*!< [23..20] TDQA5 */ + __IOM uint32_t TDQA6 : 4; /*!< [27..24] TDQA6 */ + __IOM uint32_t TDQA7 : 4; /*!< [31..28] TDQA7 */ + } EATDQAC_b; + }; + + union + { + __IOM uint32_t EATPEC; /*!< (@ 0x00000020) Ethernet Agent TX Pre-Emption Configuration Register + * (EATPEC) */ + + struct + { + __IOM uint32_t TTQ0 : 1; /*!< [0..0] TTQ0 */ + __IOM uint32_t TTQ1 : 1; /*!< [1..1] TTQ1 */ + __IOM uint32_t TTQ2 : 1; /*!< [2..2] TTQ2 */ + __IOM uint32_t TTQ3 : 1; /*!< [3..3] TTQ3 */ + __IOM uint32_t TTQ4 : 1; /*!< [4..4] TTQ4 */ + __IOM uint32_t TTQ5 : 1; /*!< [5..5] TTQ5 */ + __IOM uint32_t TTQ6 : 1; /*!< [6..6] TTQ6 */ + __IOM uint32_t TTQ7 : 1; /*!< [7..7] TTQ7 */ + __IOM uint32_t TTQ8 : 1; /*!< [8..8] TTQ8 */ + __IOM uint32_t TTQ9 : 1; /*!< [9..9] TTQ9 */ + uint32_t : 6; + __IOM uint32_t AFS : 2; /*!< [17..16] AFS */ + uint32_t : 14; + } EATPEC_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t EATMFSC0; /*!< (@ 0x00000040) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC0_b; + }; + + union + { + __IOM uint32_t EATMFSC1; /*!< (@ 0x00000044) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC1_b; + }; + + union + { + __IOM uint32_t EATMFSC2; /*!< (@ 0x00000048) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC2_b; + }; + + union + { + __IOM uint32_t EATMFSC3; /*!< (@ 0x0000004C) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC3_b; + }; + + union + { + __IOM uint32_t EATMFSC4; /*!< (@ 0x00000050) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC4_b; + }; + + union + { + __IOM uint32_t EATMFSC5; /*!< (@ 0x00000054) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC5_b; + }; + + union + { + __IOM uint32_t EATMFSC6; /*!< (@ 0x00000058) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC6_b; + }; + + union + { + __IOM uint32_t EATMFSC7; /*!< (@ 0x0000005C) Ethernet Agent Transmission Maximum Frame Size + * Configuration Register q (EATMFSCq) (q = + * 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } EATMFSC7_b; + }; + + union + { + __IOM uint32_t EATDQDC0; /*!< (@ 0x00000060) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC0_b; + }; + + union + { + __IOM uint32_t EATDQDC1; /*!< (@ 0x00000064) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC1_b; + }; + + union + { + __IOM uint32_t EATDQDC2; /*!< (@ 0x00000068) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC2_b; + }; + + union + { + __IOM uint32_t EATDQDC3; /*!< (@ 0x0000006C) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC3_b; + }; + + union + { + __IOM uint32_t EATDQDC4; /*!< (@ 0x00000070) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC4_b; + }; + + union + { + __IOM uint32_t EATDQDC5; /*!< (@ 0x00000074) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC5_b; + }; + + union + { + __IOM uint32_t EATDQDC6; /*!< (@ 0x00000078) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC6_b; + }; + + union + { + __IOM uint32_t EATDQDC7; /*!< (@ 0x0000007C) Ethernet Agent Transmission Descriptor Queue + * Depth Configuration Register q (EATDQDCq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } EATDQDC7_b; + }; + + union + { + __IOM uint32_t EATDQM0; /*!< (@ 0x00000080) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM0_b; + }; + + union + { + __IOM uint32_t EATDQM1; /*!< (@ 0x00000084) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM1_b; + }; + + union + { + __IOM uint32_t EATDQM2; /*!< (@ 0x00000088) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM2_b; + }; + + union + { + __IOM uint32_t EATDQM3; /*!< (@ 0x0000008C) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM3_b; + }; + + union + { + __IOM uint32_t EATDQM4; /*!< (@ 0x00000090) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM4_b; + }; + + union + { + __IOM uint32_t EATDQM5; /*!< (@ 0x00000094) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM5_b; + }; + + union + { + __IOM uint32_t EATDQM6; /*!< (@ 0x00000098) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM6_b; + }; + + union + { + __IOM uint32_t EATDQM7; /*!< (@ 0x0000009C) Ethernet Agent Transmission Descriptor Queue + * q Monitoring Register (EATDQMq) (q = 0 to + * 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } EATDQM7_b; + }; + + union + { + __IOM uint32_t EATDQMLM0; /*!< (@ 0x000000A0) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM0_b; + }; + + union + { + __IOM uint32_t EATDQMLM1; /*!< (@ 0x000000A4) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM1_b; + }; + + union + { + __IOM uint32_t EATDQMLM2; /*!< (@ 0x000000A8) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM2_b; + }; + + union + { + __IOM uint32_t EATDQMLM3; /*!< (@ 0x000000AC) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM3_b; + }; + + union + { + __IOM uint32_t EATDQMLM4; /*!< (@ 0x000000B0) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM4_b; + }; + + union + { + __IOM uint32_t EATDQMLM5; /*!< (@ 0x000000B4) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM5_b; + }; + + union + { + __IOM uint32_t EATDQMLM6; /*!< (@ 0x000000B8) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM6_b; + }; + + union + { + __IOM uint32_t EATDQMLM7; /*!< (@ 0x000000BC) Ethernet Agent Transmission Descriptor Queue + * q Max Level Monitoring Register (EATDQMLMq) + * (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } EATDQMLM7_b; + }; + __IM uint32_t RESERVED2[16]; + + union + { + __IOM uint32_t EACTQC; /*!< (@ 0x00000100) Ethernet Agent Cut-Through Queue Configuration + * Register (EACTQC) */ + + struct + { + __IOM uint32_t CTQD : 16; /*!< [15..0] CTQD */ + uint32_t : 16; + } EACTQC_b; + }; + + union + { + __IOM uint32_t EACTDQDC; /*!< (@ 0x00000104) Ethernet Agent Cut-Through Descriptor Queue Depth + * Configuration Register (EACTDQDC) */ + + struct + { + __IOM uint32_t CTDQD : 4; /*!< [3..0] CTDQD */ + uint32_t : 28; + } EACTDQDC_b; + }; + + union + { + __IOM uint32_t EACTDQM; /*!< (@ 0x00000108) Ethernet Agent Cut-Through Descriptor Queue Monitoring + * Register (EACTDQM) */ + + struct + { + __IOM uint32_t CTQDN : 10; /*!< [9..0] CTQDN */ + uint32_t : 22; + } EACTDQM_b; + }; + + union + { + __IOM uint32_t EACTDQMLM; /*!< (@ 0x0000010C) Ethernet Agent Cut-Through Descriptor Queue Max + * Level Monitoring Register (EACTDQMLM) */ + + struct + { + __IOM uint32_t CTDMLQ : 4; /*!< [3..0] CTDMLQ */ + uint32_t : 28; + } EACTDQMLM_b; + }; + __IM uint32_t RESERVED3[8]; + + union + { + __IOM uint32_t EAVCC; /*!< (@ 0x00000130) Ethernet Agent VLAN Control Configuration Register + * (EAVCC) */ + + struct + { + __IOM uint32_t VIM : 1; /*!< [0..0] VIM */ + uint32_t : 15; + __IOM uint32_t VEM : 3; /*!< [18..16] VEM */ + uint32_t : 13; + } EAVCC_b; + }; + + union + { + __IOM uint32_t EAVTC; /*!< (@ 0x00000134) Ethernet Agent VLAN TAG Configuration Register + * (EAVTC) */ + + struct + { + __IOM uint32_t CTV : 12; /*!< [11..0] CTV */ + __IOM uint32_t CTP : 3; /*!< [14..12] CTP */ + __IOM uint32_t CTD : 1; /*!< [15..15] CTD */ + __IOM uint32_t STV : 12; /*!< [27..16] STV */ + __IOM uint32_t STP : 3; /*!< [30..28] STP */ + __IOM uint32_t STD : 1; /*!< [31..31] STD */ + } EAVTC_b; + }; + + union + { + __IOM uint32_t EARTFC; /*!< (@ 0x00000138) Ethernet Agent Reception TAG Filtering Configuration + * Register (EARTFC) */ + + struct + { + __IOM uint32_t NT : 1; /*!< [0..0] NT */ + __IOM uint32_t RT : 1; /*!< [1..1] RT */ + __IOM uint32_t CST : 1; /*!< [2..2] CST */ + __IOM uint32_t CSRT : 1; /*!< [3..3] CSRT */ + __IOM uint32_t CT : 1; /*!< [4..4] CT */ + __IOM uint32_t CRT : 1; /*!< [5..5] CRT */ + __IOM uint32_t SCT : 1; /*!< [6..6] SCT */ + __IOM uint32_t SCRT : 1; /*!< [7..7] SCRT */ + __IOM uint32_t UT : 1; /*!< [8..8] UT */ + uint32_t : 23; + } EARTFC_b; + }; + __IM uint32_t RESERVED4[49]; + + union + { + __IOM uint32_t EACAEC; /*!< (@ 0x00000200) Ethernet Agent CBS Admin Enable Configuration + * Register (EACAEC) */ + + struct + { + __IOM uint32_t CE0 : 1; /*!< [0..0] CE0 */ + __IOM uint32_t CE1 : 1; /*!< [1..1] CE1 */ + __IOM uint32_t CE2 : 1; /*!< [2..2] CE2 */ + __IOM uint32_t CE3 : 1; /*!< [3..3] CE3 */ + __IOM uint32_t CE4 : 1; /*!< [4..4] CE4 */ + __IOM uint32_t CE5 : 1; /*!< [5..5] CE5 */ + __IOM uint32_t CE6 : 1; /*!< [6..6] CE6 */ + __IOM uint32_t CE7 : 1; /*!< [7..7] CE7 */ + uint32_t : 24; + } EACAEC_b; + }; + + union + { + __IOM uint32_t EACC; /*!< (@ 0x00000204) Ethernet Agent CBS Configuration Register (EACC) */ + + struct + { + __IOM uint32_t CC0 : 1; /*!< [0..0] CC0 */ + __IOM uint32_t CC1 : 1; /*!< [1..1] CC1 */ + __IOM uint32_t CC2 : 1; /*!< [2..2] CC2 */ + __IOM uint32_t CC3 : 1; /*!< [3..3] CC3 */ + __IOM uint32_t CC4 : 1; /*!< [4..4] CC4 */ + __IOM uint32_t CC5 : 1; /*!< [5..5] CC5 */ + __IOM uint32_t CC6 : 1; /*!< [6..6] CC6 */ + __IOM uint32_t CC7 : 1; /*!< [7..7] CC7 */ + uint32_t : 24; + } EACC_b; + }; + __IM uint32_t RESERVED5[6]; + + union + { + __IOM uint32_t EACAIVC0; /*!< (@ 0x00000220) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC0_b; + }; + + union + { + __IOM uint32_t EACAIVC1; /*!< (@ 0x00000224) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC1_b; + }; + + union + { + __IOM uint32_t EACAIVC2; /*!< (@ 0x00000228) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC2_b; + }; + + union + { + __IOM uint32_t EACAIVC3; /*!< (@ 0x0000022C) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC3_b; + }; + + union + { + __IOM uint32_t EACAIVC4; /*!< (@ 0x00000230) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC4_b; + }; + + union + { + __IOM uint32_t EACAIVC5; /*!< (@ 0x00000234) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC5_b; + }; + + union + { + __IOM uint32_t EACAIVC6; /*!< (@ 0x00000238) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC6_b; + }; + + union + { + __IOM uint32_t EACAIVC7; /*!< (@ 0x0000023C) Ethernet Agent CBS Admin Increment Value Configuration + * Register q (EACAIVCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACAIVC7_b; + }; + + union + { + __IOM uint32_t EACAULC0; /*!< (@ 0x00000240) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC0_b; + }; + + union + { + __IOM uint32_t EACAULC1; /*!< (@ 0x00000244) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC1_b; + }; + + union + { + __IOM uint32_t EACAULC2; /*!< (@ 0x00000248) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC2_b; + }; + + union + { + __IOM uint32_t EACAULC3; /*!< (@ 0x0000024C) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC3_b; + }; + + union + { + __IOM uint32_t EACAULC4; /*!< (@ 0x00000250) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC4_b; + }; + + union + { + __IOM uint32_t EACAULC5; /*!< (@ 0x00000254) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC5_b; + }; + + union + { + __IOM uint32_t EACAULC6; /*!< (@ 0x00000258) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC6_b; + }; + + union + { + __IOM uint32_t EACAULC7; /*!< (@ 0x0000025C) Ethernet Agent CBS Admin Upper Limit Configuration + * Register q (EACAULCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACAULC7_b; + }; + + union + { + __IOM uint32_t EACOEM; /*!< (@ 0x00000260) Ethernet Agent CBS Oper Enable Monitoring Register + * (EACOEM) */ + + struct + { + __IOM uint32_t CE0 : 1; /*!< [0..0] CE0 */ + __IOM uint32_t CE1 : 1; /*!< [1..1] CE1 */ + __IOM uint32_t CE2 : 1; /*!< [2..2] CE2 */ + __IOM uint32_t CE3 : 1; /*!< [3..3] CE3 */ + __IOM uint32_t CE4 : 1; /*!< [4..4] CE4 */ + __IOM uint32_t CE5 : 1; /*!< [5..5] CE5 */ + __IOM uint32_t CE6 : 1; /*!< [6..6] CE6 */ + __IOM uint32_t CE7 : 1; /*!< [7..7] CE7 */ + uint32_t : 24; + } EACOEM_b; + }; + __IM uint32_t RESERVED6[7]; + + union + { + __IOM uint32_t EACOIVM0; /*!< (@ 0x00000280) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM0_b; + }; + + union + { + __IOM uint32_t EACOIVM1; /*!< (@ 0x00000284) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM1_b; + }; + + union + { + __IOM uint32_t EACOIVM2; /*!< (@ 0x00000288) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM2_b; + }; + + union + { + __IOM uint32_t EACOIVM3; /*!< (@ 0x0000028C) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM3_b; + }; + + union + { + __IOM uint32_t EACOIVM4; /*!< (@ 0x00000290) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM4_b; + }; + + union + { + __IOM uint32_t EACOIVM5; /*!< (@ 0x00000294) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM5_b; + }; + + union + { + __IOM uint32_t EACOIVM6; /*!< (@ 0x00000298) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM6_b; + }; + + union + { + __IOM uint32_t EACOIVM7; /*!< (@ 0x0000029C) Ethernet Agent CBS Oper Increment Value Monitoring + * Register q (EACOIVMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CIV : 20; /*!< [19..0] CIV */ + uint32_t : 12; + } EACOIVM7_b; + }; + + union + { + __IOM uint32_t EACOULM0; /*!< (@ 0x000002A0) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM0_b; + }; + + union + { + __IOM uint32_t EACOULM1; /*!< (@ 0x000002A4) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM1_b; + }; + + union + { + __IOM uint32_t EACOULM2; /*!< (@ 0x000002A8) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM2_b; + }; + + union + { + __IOM uint32_t EACOULM3; /*!< (@ 0x000002AC) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM3_b; + }; + + union + { + __IOM uint32_t EACOULM4; /*!< (@ 0x000002B0) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM4_b; + }; + + union + { + __IOM uint32_t EACOULM5; /*!< (@ 0x000002B4) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM5_b; + }; + + union + { + __IOM uint32_t EACOULM6; /*!< (@ 0x000002B8) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM6_b; + }; + + union + { + __IOM uint32_t EACOULM7; /*!< (@ 0x000002BC) Ethernet Agent CBS Oper Upper Limit Monitoring + * Register q (EACOULMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t CUL : 31; /*!< [30..0] CUL */ + uint32_t : 1; + } EACOULM7_b; + }; + + union + { + __IOM uint32_t EACGSM; /*!< (@ 0x000002C0) Ethernet Agent CBS Gate State Monitoring Register + * (EACGSM) */ + + struct + { + __IOM uint32_t CGS0 : 1; /*!< [0..0] CGS0 */ + __IOM uint32_t CGS1 : 1; /*!< [1..1] CGS1 */ + __IOM uint32_t CGS2 : 1; /*!< [2..2] CGS2 */ + __IOM uint32_t CGS3 : 1; /*!< [3..3] CGS3 */ + __IOM uint32_t CGS4 : 1; /*!< [4..4] CGS4 */ + __IOM uint32_t CGS5 : 1; /*!< [5..5] CGS5 */ + __IOM uint32_t CGS6 : 1; /*!< [6..6] CGS6 */ + __IOM uint32_t CGS7 : 1; /*!< [7..7] CGS7 */ + uint32_t : 24; + } EACGSM_b; + }; + __IM uint32_t RESERVED7[15]; + + union + { + __IOM uint32_t EATASC; /*!< (@ 0x00000300) Ethernet Agent TAS Configuration Register (EATASC) */ + + struct + { + __IOM uint32_t TASE : 1; /*!< [0..0] TASE */ + __IOM uint32_t TASCC : 1; /*!< [1..1] TASCC */ + __IOM uint32_t TASCI : 1; /*!< [2..2] TASCI */ + uint32_t : 5; + __IOM uint32_t TASTS : 1; /*!< [8..8] TASTS */ + uint32_t : 7; + __IOM uint32_t TASCA : 8; /*!< [23..16] TASCA */ + uint32_t : 8; + } EATASC_b; + }; + + union + { + __IOM uint32_t EATASIGSC; /*!< (@ 0x00000304) Ethernet Agent TAS Initial Gate State Configuration + * Register (EATASIGSC) */ + + struct + { + __IOM uint32_t TASIGS0 : 1; /*!< [0..0] TASIGS0 */ + __IOM uint32_t TASIGS1 : 1; /*!< [1..1] TASIGS1 */ + __IOM uint32_t TASIGS2 : 1; /*!< [2..2] TASIGS2 */ + __IOM uint32_t TASIGS3 : 1; /*!< [3..3] TASIGS3 */ + __IOM uint32_t TASIGS4 : 1; /*!< [4..4] TASIGS4 */ + __IOM uint32_t TASIGS5 : 1; /*!< [5..5] TASIGS5 */ + __IOM uint32_t TASIGS6 : 1; /*!< [6..6] TASIGS6 */ + __IOM uint32_t TASIGS7 : 1; /*!< [7..7] TASIGS7 */ + __IOM uint32_t TASCTIGS : 1; /*!< [8..8] TASCTIGS */ + uint32_t : 23; + } EATASIGSC_b; + }; + __IM uint32_t RESERVED8[6]; + + union + { + __IOM uint32_t EATASENC0; /*!< (@ 0x00000320) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC0_b; + }; + + union + { + __IOM uint32_t EATASENC1; /*!< (@ 0x00000324) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC1_b; + }; + + union + { + __IOM uint32_t EATASENC2; /*!< (@ 0x00000328) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC2_b; + }; + + union + { + __IOM uint32_t EATASENC3; /*!< (@ 0x0000032C) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC3_b; + }; + + union + { + __IOM uint32_t EATASENC4; /*!< (@ 0x00000330) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC4_b; + }; + + union + { + __IOM uint32_t EATASENC5; /*!< (@ 0x00000334) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC5_b; + }; + + union + { + __IOM uint32_t EATASENC6; /*!< (@ 0x00000338) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC6_b; + }; + + union + { + __IOM uint32_t EATASENC7; /*!< (@ 0x0000033C) Ethernet Agent TAS Entry Number Configuration + * Register i (EATASENCi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASAEN : 9; /*!< [8..0] TASAEN */ + uint32_t : 23; + } EATASENC7_b; + }; + + union + { + __IOM uint32_t EATASCTENC; /*!< (@ 0x00000340) Ethernet Agent TAS Cut-Through Entry Number Configuration + * Register (EATASCTENC) */ + + struct + { + __IOM uint32_t TASCTAEN : 9; /*!< [8..0] TASCTAEN */ + uint32_t : 23; + } EATASCTENC_b; + }; + __IM uint32_t RESERVED9[7]; + + union + { + __IOM uint32_t EATASENM0; /*!< (@ 0x00000360) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM0_b; + }; + + union + { + __IOM uint32_t EATASENM1; /*!< (@ 0x00000364) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM1_b; + }; + + union + { + __IOM uint32_t EATASENM2; /*!< (@ 0x00000368) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM2_b; + }; + + union + { + __IOM uint32_t EATASENM3; /*!< (@ 0x0000036C) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM3_b; + }; + + union + { + __IOM uint32_t EATASENM4; /*!< (@ 0x00000370) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM4_b; + }; + + union + { + __IOM uint32_t EATASENM5; /*!< (@ 0x00000374) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM5_b; + }; + + union + { + __IOM uint32_t EATASENM6; /*!< (@ 0x00000378) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM6_b; + }; + + union + { + __IOM uint32_t EATASENM7; /*!< (@ 0x0000037C) Ethernet Agent TAS Entry Number Monitoring Register + * i (EATASENMi) (i = 0 to 8) */ + + struct + { + __IOM uint32_t TASOEN : 9; /*!< [8..0] TASOEN */ + uint32_t : 23; + } EATASENM7_b; + }; + + union + { + __IOM uint32_t EATASCTENM; /*!< (@ 0x00000380) Ethernet Agent TAS Cut-Through Entry Number Monitoring + * Register (EATASCTENM) */ + + struct + { + __IOM uint32_t TASCTOEN : 9; /*!< [8..0] TASCTOEN */ + uint32_t : 23; + } EATASCTENM_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t EATASCSTC0; /*!< (@ 0x000003A0) Ethernet Agent TAS Cycle Start Time Configuration + * Register 0 (EATASCSTC0) */ + + struct + { + __IOM uint32_t TASACSTP0 : 32; /*!< [31..0] TASACSTP0 */ + } EATASCSTC0_b; + }; + + union + { + __IOM uint32_t EATASCSTC1; /*!< (@ 0x000003A4) Ethernet Agent TAS Cycle Start Time Configuration + * Register 1 (EATASCSTC1) */ + + struct + { + __IOM uint32_t TASACSTP1 : 32; /*!< [31..0] TASACSTP1 */ + } EATASCSTC1_b; + }; + + union + { + __IOM uint32_t EATASCSTM0; /*!< (@ 0x000003A8) Ethernet Agent TAS Cycle Start Time Monitoring + * Register 0 (EATASCSTM0) */ + + struct + { + __IOM uint32_t TASOCSTP0 : 32; /*!< [31..0] TASOCSTP0 */ + } EATASCSTM0_b; + }; + + union + { + __IOM uint32_t EATASCSTM1; /*!< (@ 0x000003AC) Ethernet Agent TAS Cycle Start Time Monitoring + * Register 1 (EATASCSTM1) */ + + struct + { + __IOM uint32_t TASOCSTP1 : 32; /*!< [31..0] TASOCSTP1 */ + } EATASCSTM1_b; + }; + + union + { + __IOM uint32_t EATASCTC; /*!< (@ 0x000003B0) Ethernet Agent TAS Cycle Time Configuration Register + * (EATASCTC) */ + + struct + { + __IOM uint32_t TASACT : 32; /*!< [31..0] TASACT */ + } EATASCTC_b; + }; + + union + { + __IOM uint32_t EATASCTM; /*!< (@ 0x000003B4) Ethernet Agent TAS Cycle Time Monitoring Register + * (EATASCTM) */ + + struct + { + __IOM uint32_t TASOCT : 32; /*!< [31..0] TASOCT */ + } EATASCTM_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t EATASGL0; /*!< (@ 0x000003C0) Ethernet Agent TAS Gate Learn Register 0 (EATASGL0) */ + + struct + { + __IOM uint32_t TASGAL : 8; /*!< [7..0] TASGAL */ + uint32_t : 24; + } EATASGL0_b; + }; + + union + { + __IOM uint32_t EATASGL1; /*!< (@ 0x000003C4) Ethernet Agent TAS Gate Learn Register 1 (EATASGL1) */ + + struct + { + __IOM uint32_t TASGTL : 28; /*!< [27..0] TASGTL */ + __IOM uint32_t TASGSL : 1; /*!< [28..28] TASGSL */ + uint32_t : 3; + } EATASGL1_b; + }; + + union + { + __IOM uint32_t EATASGLR; /*!< (@ 0x000003C8) Ethernet Agent TAS Gate Learn Result Register + * (EATASGLR) */ + + struct + { + uint32_t : 31; + __IOM uint32_t GL : 1; /*!< [31..31] GL */ + } EATASGLR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t EATASGR; /*!< (@ 0x000003D0) Ethernet Agent TAS Gate Read Register (EATASGR) */ + + struct + { + __IOM uint32_t TASGAR : 8; /*!< [7..0] TASGAR */ + uint32_t : 24; + } EATASGR_b; + }; + + union + { + __IOM uint32_t EATASGRR; /*!< (@ 0x000003D4) Ethernet Agent TAS Gate Read Result Register + * (EATASGRR) */ + + struct + { + __IOM uint32_t TASGTR : 28; /*!< [27..0] TASGTR */ + __IOM uint32_t TASGSR : 1; /*!< [28..28] TASGSR */ + __IOM uint32_t TASREF : 1; /*!< [29..29] TASREF */ + uint32_t : 1; + __IOM uint32_t GR : 1; /*!< [31..31] GR */ + } EATASGRR_b; + }; + __IM uint32_t RESERVED13[2]; + + union + { + __IOM uint32_t EATASHCC; /*!< (@ 0x000003E0) Ethernet Agent TAS Hardware Calibration Configuration + * Register (EATASHCC) */ + + struct + { + __IOM uint32_t TASJ : 16; /*!< [15..0] TASJ */ + uint32_t : 16; + } EATASHCC_b; + }; + + union + { + __IOM uint32_t EATASRIRM; /*!< (@ 0x000003E4) Ethernet Agent TAS RAM Initialization Register + * Monitoring Register (EATASRIRM) */ + + struct + { + __IOM uint32_t TASRIOG : 1; /*!< [0..0] TASRIOG */ + __IOM uint32_t TASRR : 1; /*!< [1..1] TASRR */ + uint32_t : 30; + } EATASRIRM_b; + }; + + union + { + __IOM uint32_t EATASSM; /*!< (@ 0x000003E8) Ethernet Agent TAS Status Monitoring Register + * (EATASSM) */ + + struct + { + __IOM uint32_t TASGS0 : 1; /*!< [0..0] TASGS0 */ + __IOM uint32_t TASGS1 : 1; /*!< [1..1] TASGS1 */ + __IOM uint32_t TASGS2 : 1; /*!< [2..2] TASGS2 */ + __IOM uint32_t TASGS3 : 1; /*!< [3..3] TASGS3 */ + __IOM uint32_t TASGS4 : 1; /*!< [4..4] TASGS4 */ + __IOM uint32_t TASGS5 : 1; /*!< [5..5] TASGS5 */ + __IOM uint32_t TASGS6 : 1; /*!< [6..6] TASGS6 */ + __IOM uint32_t TASGS7 : 1; /*!< [7..7] TASGS7 */ + __IOM uint32_t TASCTGS : 1; /*!< [8..8] TASCTGS */ + uint32_t : 7; + __IOM uint32_t TASSO : 1; /*!< [16..16] TASSO */ + uint32_t : 15; + } EATASSM_b; + }; + __IM uint32_t RESERVED14[5]; + + union + { + __IOM uint32_t EAUSMFSECN; /*!< (@ 0x00000400) Ethernet Agent Switch Minimum Frame Size Error + * Counter Register (EAUSMFSECN) */ + + struct + { + __IOM uint32_t USMFSEN : 16; /*!< [15..0] USMFSEN */ + uint32_t : 16; + } EAUSMFSECN_b; + }; + + union + { + __IOM uint32_t EATFECN; /*!< (@ 0x00000404) Ethernet Agent TAG Filtering Error Counter Register + * (EATFECN) */ + + struct + { + __IOM uint32_t TFEN : 16; /*!< [15..0] TFEN */ + uint32_t : 16; + } EATFECN_b; + }; + + union + { + __IOM uint32_t EAFSECN; /*!< (@ 0x00000408) Ethernet Agent Frame Size Error Counter Register + * (EAFSECN) */ + + struct + { + __IOM uint32_t FSEN : 16; /*!< [15..0] FSEN */ + uint32_t : 16; + } EAFSECN_b; + }; + + union + { + __IOM uint32_t EADQOECN; /*!< (@ 0x0000040C) Ethernet Agent Descriptor Queue Overflow Error + * Counter Register (EADQOECN) */ + + struct + { + __IOM uint32_t DQOEN : 16; /*!< [15..0] DQOEN */ + uint32_t : 16; + } EADQOECN_b; + }; + + union + { + __IOM uint32_t EADQSECN; /*!< (@ 0x00000410) Ethernet Agent Descriptor Queue Security Error + * Counter Register (EADQSECN) */ + + struct + { + __IOM uint32_t DQSEN : 16; /*!< [15..0] DQSEN */ + uint32_t : 16; + } EADQSECN_b; + }; + __IM uint32_t RESERVED15[59]; + + union + { + __IOM uint32_t EAEIS0; /*!< (@ 0x00000500) Ethernet Agent Error Interrupt Status Register + * 0 (EAEIS0) */ + + struct + { + __IOM uint32_t DECCES : 1; /*!< [0..0] DECCES */ + __IOM uint32_t TECCES : 1; /*!< [1..1] TECCES */ + __IOM uint32_t PECCES : 1; /*!< [2..2] PECCES */ + __IOM uint32_t DSECCES : 1; /*!< [3..3] DSECCES */ + __IOM uint32_t L23UECCES : 1; /*!< [4..4] L23UECCES */ + __IOM uint32_t USMFSES : 1; /*!< [5..5] USMFSES */ + __IOM uint32_t TFES : 1; /*!< [6..6] TFES */ + uint32_t : 1; + __IOM uint32_t FSES0 : 1; /*!< [8..8] FSES0 */ + __IOM uint32_t FSES1 : 1; /*!< [9..9] FSES1 */ + __IOM uint32_t FSES2 : 1; /*!< [10..10] FSES2 */ + __IOM uint32_t FSES3 : 1; /*!< [11..11] FSES3 */ + __IOM uint32_t FSES4 : 1; /*!< [12..12] FSES4 */ + __IOM uint32_t FSES5 : 1; /*!< [13..13] FSES5 */ + __IOM uint32_t FSES6 : 1; /*!< [14..14] FSES6 */ + __IOM uint32_t FSES7 : 1; /*!< [15..15] FSES7 */ + __IOM uint32_t TASGEES0 : 1; /*!< [16..16] TASGEES0 */ + __IOM uint32_t TASGEES1 : 1; /*!< [17..17] TASGEES1 */ + __IOM uint32_t TASGEES2 : 1; /*!< [18..18] TASGEES2 */ + __IOM uint32_t TASGEES3 : 1; /*!< [19..19] TASGEES3 */ + __IOM uint32_t TASGEES4 : 1; /*!< [20..20] TASGEES4 */ + __IOM uint32_t TASGEES5 : 1; /*!< [21..21] TASGEES5 */ + __IOM uint32_t TASGEES6 : 1; /*!< [22..22] TASGEES6 */ + __IOM uint32_t TASGEES7 : 1; /*!< [23..23] TASGEES7 */ + __IOM uint32_t TASCTGEES : 1; /*!< [24..24] TASCTGEES */ + uint32_t : 7; + } EAEIS0_b; + }; + + union + { + __IOM uint32_t EAEIE0; /*!< (@ 0x00000504) Ethernet Agent Error Interrupt Enable Register + * 0 (EAEIE0) */ + + struct + { + __IOM uint32_t DECCEE : 1; /*!< [0..0] DECCEE */ + __IOM uint32_t TECCEE : 1; /*!< [1..1] TECCEE */ + __IOM uint32_t PECCEE : 1; /*!< [2..2] PECCEE */ + __IOM uint32_t DSECCEE : 1; /*!< [3..3] DSECCEE */ + __IOM uint32_t L23UECCEE : 1; /*!< [4..4] L23UECCEE */ + __IOM uint32_t USMFSEE : 1; /*!< [5..5] USMFSEE */ + __IOM uint32_t TFEE : 1; /*!< [6..6] TFEE */ + uint32_t : 1; + __IOM uint32_t FSEE0 : 1; /*!< [8..8] FSEE0 */ + __IOM uint32_t FSEE1 : 1; /*!< [9..9] FSEE1 */ + __IOM uint32_t FSEE2 : 1; /*!< [10..10] FSEE2 */ + __IOM uint32_t FSEE3 : 1; /*!< [11..11] FSEE3 */ + __IOM uint32_t FSEE4 : 1; /*!< [12..12] FSEE4 */ + __IOM uint32_t FSEE5 : 1; /*!< [13..13] FSEE5 */ + __IOM uint32_t FSEE6 : 1; /*!< [14..14] FSEE6 */ + __IOM uint32_t FSEE7 : 1; /*!< [15..15] FSEE7 */ + __IOM uint32_t TASGEEE0 : 1; /*!< [16..16] TASGEEE0 */ + __IOM uint32_t TASGEEE1 : 1; /*!< [17..17] TASGEEE1 */ + __IOM uint32_t TASGEEE2 : 1; /*!< [18..18] TASGEEE2 */ + __IOM uint32_t TASGEEE3 : 1; /*!< [19..19] TASGEEE3 */ + __IOM uint32_t TASGEEE4 : 1; /*!< [20..20] TASGEEE4 */ + __IOM uint32_t TASGEEE5 : 1; /*!< [21..21] TASGEEE5 */ + __IOM uint32_t TASGEEE6 : 1; /*!< [22..22] TASGEEE6 */ + __IOM uint32_t TASGEEE7 : 1; /*!< [23..23] TASGEEE7 */ + __IOM uint32_t TASCTGEEE : 1; /*!< [24..24] TASCTGEEE */ + uint32_t : 7; + } EAEIE0_b; + }; + + union + { + __IOM uint32_t EAEID0; /*!< (@ 0x00000508) Ethernet Agent Error Interrupt Disable Register + * 0 (EAEID0) */ + + struct + { + __IOM uint32_t DECCED : 1; /*!< [0..0] DECCED */ + __IOM uint32_t TECCED : 1; /*!< [1..1] TECCED */ + __IOM uint32_t PECCED : 1; /*!< [2..2] PECCED */ + __IOM uint32_t DSECCED : 1; /*!< [3..3] DSECCED */ + __IOM uint32_t L23UECCED : 1; /*!< [4..4] L23UECCED */ + __IOM uint32_t USMFSED : 1; /*!< [5..5] USMFSED */ + __IOM uint32_t TFED : 1; /*!< [6..6] TFED */ + uint32_t : 1; + __IOM uint32_t FSED0 : 1; /*!< [8..8] FSED0 */ + __IOM uint32_t FSED1 : 1; /*!< [9..9] FSED1 */ + __IOM uint32_t FSED2 : 1; /*!< [10..10] FSED2 */ + __IOM uint32_t FSED3 : 1; /*!< [11..11] FSED3 */ + __IOM uint32_t FSED4 : 1; /*!< [12..12] FSED4 */ + __IOM uint32_t FSED5 : 1; /*!< [13..13] FSED5 */ + __IOM uint32_t FSED6 : 1; /*!< [14..14] FSED6 */ + __IOM uint32_t FSED7 : 1; /*!< [15..15] FSED7 */ + __IOM uint32_t TASGEED0 : 1; /*!< [16..16] TASGEED0 */ + __IOM uint32_t TASGEED1 : 1; /*!< [17..17] TASGEED1 */ + __IOM uint32_t TASGEED2 : 1; /*!< [18..18] TASGEED2 */ + __IOM uint32_t TASGEED3 : 1; /*!< [19..19] TASGEED3 */ + __IOM uint32_t TASGEED4 : 1; /*!< [20..20] TASGEED4 */ + __IOM uint32_t TASGEED5 : 1; /*!< [21..21] TASGEED5 */ + __IOM uint32_t TASGEED6 : 1; /*!< [22..22] TASGEED6 */ + __IOM uint32_t TASGEED7 : 1; /*!< [23..23] TASGEED7 */ + __IOM uint32_t TASCTGEED : 1; /*!< [24..24] TASCTGEED */ + uint32_t : 7; + } EAEID0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t EAEIS1; /*!< (@ 0x00000510) Ethernet Agent Error Interrupt Status Register + * 1 (EAEIS1) */ + + struct + { + __IOM uint32_t CULES0 : 1; /*!< [0..0] CULES0 */ + __IOM uint32_t CULES1 : 1; /*!< [1..1] CULES1 */ + __IOM uint32_t CULES2 : 1; /*!< [2..2] CULES2 */ + __IOM uint32_t CULES3 : 1; /*!< [3..3] CULES3 */ + __IOM uint32_t CULES4 : 1; /*!< [4..4] CULES4 */ + __IOM uint32_t CULES5 : 1; /*!< [5..5] CULES5 */ + __IOM uint32_t CULES6 : 1; /*!< [6..6] CULES6 */ + __IOM uint32_t CULES7 : 1; /*!< [7..7] CULES7 */ + uint32_t : 8; + __IOM uint32_t TASGES0 : 1; /*!< [16..16] TASGES0 */ + __IOM uint32_t TASGES1 : 1; /*!< [17..17] TASGES1 */ + __IOM uint32_t TASGES2 : 1; /*!< [18..18] TASGES2 */ + __IOM uint32_t TASGES3 : 1; /*!< [19..19] TASGES3 */ + __IOM uint32_t TASGES4 : 1; /*!< [20..20] TASGES4 */ + __IOM uint32_t TASGES5 : 1; /*!< [21..21] TASGES5 */ + __IOM uint32_t TASGES6 : 1; /*!< [22..22] TASGES6 */ + __IOM uint32_t TASGES7 : 1; /*!< [23..23] TASGES7 */ + __IOM uint32_t TASCTGES : 1; /*!< [24..24] TASCTGES */ + uint32_t : 7; + } EAEIS1_b; + }; + + union + { + __IOM uint32_t EAEIE1; /*!< (@ 0x00000514) Ethernet Agent Error Interrupt Enable Register + * 1 (EAEIE1) */ + + struct + { + __IOM uint32_t CULEE0 : 1; /*!< [0..0] CULEE0 */ + __IOM uint32_t CULEE1 : 1; /*!< [1..1] CULEE1 */ + __IOM uint32_t CULEE2 : 1; /*!< [2..2] CULEE2 */ + __IOM uint32_t CULEE3 : 1; /*!< [3..3] CULEE3 */ + __IOM uint32_t CULEE4 : 1; /*!< [4..4] CULEE4 */ + __IOM uint32_t CULEE5 : 1; /*!< [5..5] CULEE5 */ + __IOM uint32_t CULEE6 : 1; /*!< [6..6] CULEE6 */ + __IOM uint32_t CULEE7 : 1; /*!< [7..7] CULEE7 */ + uint32_t : 8; + __IOM uint32_t TASGEE0 : 1; /*!< [16..16] TASGEE0 */ + __IOM uint32_t TASGEE1 : 1; /*!< [17..17] TASGEE1 */ + __IOM uint32_t TASGEE2 : 1; /*!< [18..18] TASGEE2 */ + __IOM uint32_t TASGEE3 : 1; /*!< [19..19] TASGEE3 */ + __IOM uint32_t TASGEE4 : 1; /*!< [20..20] TASGEE4 */ + __IOM uint32_t TASGEE5 : 1; /*!< [21..21] TASGEE5 */ + __IOM uint32_t TASGEE6 : 1; /*!< [22..22] TASGEE6 */ + __IOM uint32_t TASGEE7 : 1; /*!< [23..23] TASGEE7 */ + __IOM uint32_t TASCTGEE : 1; /*!< [24..24] TASCTGEE */ + uint32_t : 7; + } EAEIE1_b; + }; + + union + { + __IOM uint32_t EAEID1; /*!< (@ 0x00000518) Ethernet Agent Error Interrupt Disable Register + * 1 (EAEID1) */ + + struct + { + __IOM uint32_t CULED0 : 1; /*!< [0..0] CULED0 */ + __IOM uint32_t CULED1 : 1; /*!< [1..1] CULED1 */ + __IOM uint32_t CULED2 : 1; /*!< [2..2] CULED2 */ + __IOM uint32_t CULED3 : 1; /*!< [3..3] CULED3 */ + __IOM uint32_t CULED4 : 1; /*!< [4..4] CULED4 */ + __IOM uint32_t CULED5 : 1; /*!< [5..5] CULED5 */ + __IOM uint32_t CULED6 : 1; /*!< [6..6] CULED6 */ + __IOM uint32_t CULED7 : 1; /*!< [7..7] CULED7 */ + uint32_t : 8; + __IOM uint32_t TASGED0 : 1; /*!< [16..16] TASGED0 */ + __IOM uint32_t TASGED1 : 1; /*!< [17..17] TASGED1 */ + __IOM uint32_t TASGED2 : 1; /*!< [18..18] TASGED2 */ + __IOM uint32_t TASGED3 : 1; /*!< [19..19] TASGED3 */ + __IOM uint32_t TASGED4 : 1; /*!< [20..20] TASGED4 */ + __IOM uint32_t TASGED5 : 1; /*!< [21..21] TASGED5 */ + __IOM uint32_t TASGED6 : 1; /*!< [22..22] TASGED6 */ + __IOM uint32_t TASGED7 : 1; /*!< [23..23] TASGED7 */ + __IOM uint32_t TASCTGED : 1; /*!< [24..24] TASCTGED */ + uint32_t : 7; + } EAEID1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t EAEIS2; /*!< (@ 0x00000520) Ethernet Agent Error Interrupt Status Register + * 2 (EAEIS2) */ + + struct + { + __IOM uint32_t DQOES0 : 1; /*!< [0..0] DQOES0 */ + __IOM uint32_t DQOES1 : 1; /*!< [1..1] DQOES1 */ + __IOM uint32_t DQOES2 : 1; /*!< [2..2] DQOES2 */ + __IOM uint32_t DQOES3 : 1; /*!< [3..3] DQOES3 */ + __IOM uint32_t DQOES4 : 1; /*!< [4..4] DQOES4 */ + __IOM uint32_t DQOES5 : 1; /*!< [5..5] DQOES5 */ + __IOM uint32_t DQOES6 : 1; /*!< [6..6] DQOES6 */ + __IOM uint32_t DQOES7 : 1; /*!< [7..7] DQOES7 */ + __IOM uint32_t CTDQOES : 1; /*!< [8..8] CTDQOES */ + uint32_t : 7; + __IOM uint32_t DQSES0 : 1; /*!< [16..16] DQSES0 */ + __IOM uint32_t DQSES1 : 1; /*!< [17..17] DQSES1 */ + __IOM uint32_t DQSES2 : 1; /*!< [18..18] DQSES2 */ + __IOM uint32_t DQSES3 : 1; /*!< [19..19] DQSES3 */ + __IOM uint32_t DQSES4 : 1; /*!< [20..20] DQSES4 */ + __IOM uint32_t DQSES5 : 1; /*!< [21..21] DQSES5 */ + __IOM uint32_t DQSES6 : 1; /*!< [22..22] DQSES6 */ + __IOM uint32_t DQSES7 : 1; /*!< [23..23] DQSES7 */ + uint32_t : 8; + } EAEIS2_b; + }; + + union + { + __IOM uint32_t EAEIE2; /*!< (@ 0x00000524) Ethernet Agent Error Interrupt Enable Register + * 2 (EAEIE2) */ + + struct + { + __IOM uint32_t DQOEE0 : 1; /*!< [0..0] DQOEE0 */ + __IOM uint32_t DQOEE1 : 1; /*!< [1..1] DQOEE1 */ + __IOM uint32_t DQOEE2 : 1; /*!< [2..2] DQOEE2 */ + __IOM uint32_t DQOEE3 : 1; /*!< [3..3] DQOEE3 */ + __IOM uint32_t DQOEE4 : 1; /*!< [4..4] DQOEE4 */ + __IOM uint32_t DQOEE5 : 1; /*!< [5..5] DQOEE5 */ + __IOM uint32_t DQOEE6 : 1; /*!< [6..6] DQOEE6 */ + __IOM uint32_t DQOEE7 : 1; /*!< [7..7] DQOEE7 */ + __IOM uint32_t CTDQOEE : 1; /*!< [8..8] CTDQOEE */ + uint32_t : 7; + __IOM uint32_t DQSEE0 : 1; /*!< [16..16] DQSEE0 */ + __IOM uint32_t DQSEE1 : 1; /*!< [17..17] DQSEE1 */ + __IOM uint32_t DQSEE2 : 1; /*!< [18..18] DQSEE2 */ + __IOM uint32_t DQSEE3 : 1; /*!< [19..19] DQSEE3 */ + __IOM uint32_t DQSEE4 : 1; /*!< [20..20] DQSEE4 */ + __IOM uint32_t DQSEE5 : 1; /*!< [21..21] DQSEE5 */ + __IOM uint32_t DQSEE6 : 1; /*!< [22..22] DQSEE6 */ + __IOM uint32_t DQSEE7 : 1; /*!< [23..23] DQSEE7 */ + uint32_t : 8; + } EAEIE2_b; + }; + + union + { + __IOM uint32_t EAEID2; /*!< (@ 0x00000528) Ethernet Agent Error Interrupt Disable Register + * 2 (EAEID2) */ + + struct + { + __IOM uint32_t DQOED0 : 1; /*!< [0..0] DQOED0 */ + __IOM uint32_t DQOED1 : 1; /*!< [1..1] DQOED1 */ + __IOM uint32_t DQOED2 : 1; /*!< [2..2] DQOED2 */ + __IOM uint32_t DQOED3 : 1; /*!< [3..3] DQOED3 */ + __IOM uint32_t DQOED4 : 1; /*!< [4..4] DQOED4 */ + __IOM uint32_t DQOED5 : 1; /*!< [5..5] DQOED5 */ + __IOM uint32_t DQOED6 : 1; /*!< [6..6] DQOED6 */ + __IOM uint32_t DQOED7 : 1; /*!< [7..7] DQOED7 */ + __IOM uint32_t CTDQOED : 1; /*!< [8..8] CTDQOED */ + uint32_t : 7; + __IOM uint32_t DQSED0 : 1; /*!< [16..16] DQSED0 */ + __IOM uint32_t DQSED1 : 1; /*!< [17..17] DQSED1 */ + __IOM uint32_t DQSED2 : 1; /*!< [18..18] DQSED2 */ + __IOM uint32_t DQSED3 : 1; /*!< [19..19] DQSED3 */ + __IOM uint32_t DQSED4 : 1; /*!< [20..20] DQSED4 */ + __IOM uint32_t DQSED5 : 1; /*!< [21..21] DQSED5 */ + __IOM uint32_t DQSED6 : 1; /*!< [22..22] DQSED6 */ + __IOM uint32_t DQSED7 : 1; /*!< [23..23] DQSED7 */ + uint32_t : 8; + } EAEID2_b; + }; + __IM uint32_t RESERVED18[21]; + + union + { + __IOM uint32_t EASCR; /*!< (@ 0x00000580) Ethernet Agent Security Configuration Register + * (EASCR) */ + + struct + { + __IOM uint32_t MRSL : 1; /*!< [0..0] MRSL */ + __IOM uint32_t TRSL : 1; /*!< [1..1] TRSL */ + __IOM uint32_t MCRSL : 1; /*!< [2..2] MCRSL */ + __IOM uint32_t TGRSL : 1; /*!< [3..3] TGRSL */ + __IOM uint32_t TASRSL : 1; /*!< [4..4] TASRSL */ + __IOM uint32_t EIRSL : 1; /*!< [5..5] EIRSL */ + __IOM uint32_t CRSL : 1; /*!< [6..6] CRSL */ + uint32_t : 9; + __IOM uint32_t DQRSL0 : 1; /*!< [16..16] DQRSL0 */ + __IOM uint32_t DQRSL1 : 1; /*!< [17..17] DQRSL1 */ + __IOM uint32_t DQRSL2 : 1; /*!< [18..18] DQRSL2 */ + __IOM uint32_t DQRSL3 : 1; /*!< [19..19] DQRSL3 */ + __IOM uint32_t DQRSL4 : 1; /*!< [20..20] DQRSL4 */ + __IOM uint32_t DQRSL5 : 1; /*!< [21..21] DQRSL5 */ + __IOM uint32_t DQRSL6 : 1; /*!< [22..22] DQRSL6 */ + __IOM uint32_t DQRSL7 : 1; /*!< [23..23] DQRSL7 */ + uint32_t : 8; + } EASCR_b; + }; +} R_ETHA0_Type; /*!< Size = 1412 (0x584) */ + +/* =========================================================================================================================== */ +/* ================ R_GPTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Generic PTP Timer (R_GPTP) + */ + +typedef struct /*!< (@ 0x403E0000) R_GPTP Structure */ +{ + union + { + __IM uint32_t PTPIPV; /*!< (@ 0x00000000) IP Version Register */ + + struct + { + __IM uint32_t IPV : 32; /*!< [31..0] IP Version */ + } PTPIPV_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t PTPTMEC; /*!< (@ 0x00000010) Timer Enable Configuration Register */ + + struct + { + __IOM uint32_t TE : 2; /*!< [1..0] Timer Enable */ + uint32_t : 30; + } PTPTMEC_b; + }; + + union + { + __IOM uint32_t PTPTMDC; /*!< (@ 0x00000014) Timer Disable Configuration Register */ + + struct + { + __OM uint32_t TD : 2; /*!< [1..0] Timer Disable */ + uint32_t : 30; + } PTPTMDC_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t PTPTIVC0; /*!< (@ 0x00000020) Timer Increment Value Configuration Register + * 0 */ + + struct + { + __IOM uint32_t TIV : 32; /*!< [31..0] Timer Increment Value */ + } PTPTIVC0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t PTPTOVCL0; /*!< (@ 0x00000030) Timer Offset Value Configuration Register L0 */ + + struct + { + __IOM uint32_t TOVL : 30; /*!< [29..0] Timer Offset Value Lower Part */ + uint32_t : 2; + } PTPTOVCL0_b; + }; + + union + { + __IOM uint32_t PTPTOVCM0; /*!< (@ 0x00000034) Timer Offset Value Configuration Register M0 */ + + struct + { + __IOM uint32_t TOVM : 32; /*!< [31..0] Timer Offset Value Middle Part */ + } PTPTOVCM0_b; + }; + + union + { + __IOM uint32_t PTPTOVCU0; /*!< (@ 0x00000038) Timer Offset Value Configuration Register U0 */ + + struct + { + __IOM uint32_t TOVU : 16; /*!< [15..0] Timer Offset Value Upper Part */ + uint32_t : 16; + } PTPTOVCU0_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t PTPAVTPTML0; /*!< (@ 0x00000040) AVTP Timer Monitoring Register L0 */ + + struct + { + __IM uint32_t AVTPL : 32; /*!< [31..0] AVTP Timer Value Lower Part */ + } PTPAVTPTML0_b; + }; + + union + { + __IM uint32_t PTPAVTPTMU0; /*!< (@ 0x00000044) AVTP Timer Monitoring Register U0 */ + + struct + { + __IM uint32_t AVTPU : 32; /*!< [31..0] AVTP Timer Value Upper Part */ + } PTPAVTPTMU0_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t PTPGPTPTML0; /*!< (@ 0x00000050) GPTP Timer Monitoring Register L0 */ + + struct + { + __IM uint32_t GPTPL : 30; /*!< [29..0] GPTP Timer Value Lower Part */ + uint32_t : 2; + } PTPGPTPTML0_b; + }; + + union + { + __IM uint32_t PTPGPTPTMM0; /*!< (@ 0x00000054) GPTP Timer Monitoring Register M0 */ + + struct + { + __IM uint32_t GPTPM : 32; /*!< [31..0] GPTP Timer Value Middle Part */ + } PTPGPTPTMM0_b; + }; + + union + { + __IM uint32_t PTPGPTPTMU0; /*!< (@ 0x00000058) GPTP Timer Monitoring Register U0 */ + + struct + { + __IM uint32_t GPTPU : 16; /*!< [15..0] GPTP Timer Value Upper Part */ + uint32_t : 16; + } PTPGPTPTMU0_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PTPTIVC1; /*!< (@ 0x00000060) Timer Increment Value Configuration Register + * 1 */ + + struct + { + __IOM uint32_t TIV : 32; /*!< [31..0] Timer Increment Value */ + } PTPTIVC1_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t PTPTOVCL1; /*!< (@ 0x00000070) Timer Offset Value Configuration Register L1 */ + + struct + { + __IOM uint32_t TOVL : 30; /*!< [29..0] Timer Offset Value Lower Part */ + uint32_t : 2; + } PTPTOVCL1_b; + }; + + union + { + __IOM uint32_t PTPTOVCM1; /*!< (@ 0x00000074) Timer Offset Value Configuration Register M1 */ + + struct + { + __IOM uint32_t TOVM : 32; /*!< [31..0] Timer Offset Value Middle Part */ + } PTPTOVCM1_b; + }; + + union + { + __IOM uint32_t PTPTOVCU1; /*!< (@ 0x00000078) Timer Offset Value Configuration Register U1 */ + + struct + { + __IOM uint32_t TOVU : 16; /*!< [15..0] Timer Offset Value Upper Part */ + uint32_t : 16; + } PTPTOVCU1_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t PTPAVTPTML1; /*!< (@ 0x00000080) AVTP Timer Monitoring Register L1 */ + + struct + { + __IM uint32_t AVTPL : 32; /*!< [31..0] AVTP Timer Value Lower Part */ + } PTPAVTPTML1_b; + }; + + union + { + __IM uint32_t PTPAVTPTMU1; /*!< (@ 0x00000084) AVTP Timer Monitoring Register U1 */ + + struct + { + __IM uint32_t AVTPU : 32; /*!< [31..0] AVTP Timer Value Upper Part */ + } PTPAVTPTMU1_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IM uint32_t PTPGPTPTML1; /*!< (@ 0x00000090) GPTP Timer Monitoring Register L1 */ + + struct + { + __IM uint32_t GPTPL : 30; /*!< [29..0] GPTP Timer Value Lower Part */ + uint32_t : 2; + } PTPGPTPTML1_b; + }; + + union + { + __IM uint32_t PTPGPTPTMM1; /*!< (@ 0x00000094) GPTP Timer Monitoring Register M1 */ + + struct + { + __IM uint32_t GPTPM : 32; /*!< [31..0] GPTP Timer Value Middle Part */ + } PTPGPTPTMM1_b; + }; + + union + { + __IM uint32_t PTPGPTPTMU1; /*!< (@ 0x00000098) GPTP Timer Monitoring Register U1 */ + + struct + { + __IM uint32_t GPTPU : 16; /*!< [15..0] GPTP Timer Value Upper Part */ + uint32_t : 16; + } PTPGPTPTMU1_b; + }; + __IM uint32_t RESERVED9[89]; + + union + { + __IOM uint32_t PTPMCCC0; /*!< (@ 0x00000200) Media Clock Capture Configuration Register 0 */ + + struct + { + __IOM uint32_t MCPEE : 1; /*!< [0..0] Media Clock Capture Positive Edge Enable */ + __IOM uint32_t MCNEE : 1; /*!< [1..1] Media Clock Capture Negative Edge Enable */ + __IOM uint32_t MCTTS : 1; /*!< [2..2] Media Clock Capture Timer Type Select */ + __IOM uint32_t MCTNS : 1; /*!< [3..3] Media Clock Capture Timer Number Select */ + uint32_t : 12; + __IOM uint32_t MCCR : 1; /*!< [16..16] Media Clock Capture Request */ + uint32_t : 15; + } PTPMCCC0_b; + }; + + union + { + __IM uint32_t PTPMCCML0; /*!< (@ 0x00000204) Media Clock Capture Monitoring Register L0 */ + + struct + { + __IM uint32_t MCCTVL : 32; /*!< [31..0] Media Clock Captured Timer Value Lower Part */ + } PTPMCCML0_b; + }; + + union + { + __IM uint32_t PTPMCCMM0; /*!< (@ 0x00000208) Media Clock Capture Monitoring Register M0 */ + + struct + { + __IM uint32_t MCCTVM : 32; /*!< [31..0] Media Clock Captured Timer Value Middle Part */ + } PTPMCCMM0_b; + }; + + union + { + __IM uint32_t PTPMCCMU0; /*!< (@ 0x0000020C) Media Clock Capture Monitoring Register U0 */ + + struct + { + __IM uint32_t MCCTVU : 16; /*!< [15..0] Media Clock Captured Timer Value Upper Part */ + __IM uint32_t MCPEC : 1; /*!< [16..16] Media Clock Positive Edge Captured */ + __IM uint32_t MCNEC : 1; /*!< [17..17] Media Clock Negative Edge Captured */ + __IM uint32_t MCSWC : 1; /*!< [18..18] Media Clock SoftWare Captured */ + uint32_t : 5; + __IM uint32_t MCCN : 2; /*!< [25..24] Media Clock Capture Number */ + uint32_t : 6; + } PTPMCCMU0_b; + }; + + union + { + __IOM uint32_t PTPMCCC1; /*!< (@ 0x00000210) Media Clock Capture Configuration Register 1 */ + + struct + { + __IOM uint32_t MCPEE : 1; /*!< [0..0] Media Clock Capture Positive Edge Enable */ + __IOM uint32_t MCNEE : 1; /*!< [1..1] Media Clock Capture Negative Edge Enable */ + __IOM uint32_t MCTTS : 1; /*!< [2..2] Media Clock Capture Timer Type Select */ + __IOM uint32_t MCTNS : 1; /*!< [3..3] Media Clock Capture Timer Number Select */ + uint32_t : 12; + __IOM uint32_t MCCR : 1; /*!< [16..16] Media Clock Capture Request */ + uint32_t : 15; + } PTPMCCC1_b; + }; + + union + { + __IM uint32_t PTPMCCML1; /*!< (@ 0x00000214) Media Clock Capture Monitoring Register L1 */ + + struct + { + __IM uint32_t MCCTVL : 32; /*!< [31..0] Media Clock Captured Timer Value Lower Part */ + } PTPMCCML1_b; + }; + + union + { + __IM uint32_t PTPMCCMM1; /*!< (@ 0x00000218) Media Clock Capture Monitoring Register M1 */ + + struct + { + __IM uint32_t MCCTVM : 32; /*!< [31..0] Media Clock Captured Timer Value Middle Part */ + } PTPMCCMM1_b; + }; + + union + { + __IM uint32_t PTPMCCMU1; /*!< (@ 0x0000021C) Media Clock Capture Monitoring Register U1 */ + + struct + { + __IM uint32_t MCCTVU : 16; /*!< [15..0] Media Clock Captured Timer Value Upper Part */ + __IM uint32_t MCPEC : 1; /*!< [16..16] Media Clock Positive Edge Captured */ + __IM uint32_t MCNEC : 1; /*!< [17..17] Media Clock Negative Edge Captured */ + __IM uint32_t MCSWC : 1; /*!< [18..18] Media Clock SoftWare Captured */ + uint32_t : 5; + __IM uint32_t MCCN : 2; /*!< [25..24] Media Clock Capture Number */ + uint32_t : 6; + } PTPMCCMU1_b; + }; + __IM uint32_t RESERVED10[56]; + + union + { + __IOM uint32_t PTPMCRC0; /*!< (@ 0x00000300) Media Clock Recovery Configuration Register 0 */ + + struct + { + __IOM uint32_t MRTTS : 1; /*!< [0..0] Media Clock Recovery Timer Type Select */ + __IOM uint32_t MRAMS : 1; /*!< [1..1] Media Clock Recovery AVTP Mode Select */ + __IOM uint32_t MRTNS : 1; /*!< [2..2] Media Clock Recovery Timer Number Select */ + uint32_t : 13; + __IOM uint32_t MRPL : 16; /*!< [31..16] Media Clock Recovery Pulse Length */ + } PTPMCRC0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCL0; /*!< (@ 0x00000304) Media Clock Recovery Time Configuration Register + * L0 */ + + struct + { + __IOM uint32_t MRTVL : 32; /*!< [31..0] Media Clock Recovery Timer Value Lower Part */ + } PTPMCRTCL0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCM0; /*!< (@ 0x00000308) Media Clock Recovery Time Configuration Register + * M0 */ + + struct + { + __IOM uint32_t MRTVM : 32; /*!< [31..0] Media Clock Recovery Timer Value Middle Part */ + } PTPMCRTCM0_b; + }; + + union + { + __IOM uint32_t PTPMCRTCU0; /*!< (@ 0x0000030C) Media Clock Recovery Time Configuration Register + * U0 */ + + struct + { + __IOM uint32_t MRTVU : 16; /*!< [15..0] Media Clock Recovery Timer Value Upper Part */ + __IOM uint32_t MRTT : 2; /*!< [17..16] Media Clock Recovery Trigger Type */ + __IM uint32_t MCRN : 3; /*!< [20..18] Media Clock Recovery Number */ + uint32_t : 10; + __IM uint32_t MRBCR : 1; /*!< [31..31] Media Clock Recovery Buffer Clear Request */ + } PTPMCRTCU0_b; + }; + + union + { + __IOM uint32_t PTPMCRC1; /*!< (@ 0x00000310) Media Clock Recovery Configuration Register 1 */ + + struct + { + __IOM uint32_t MRTTS : 1; /*!< [0..0] Media Clock Recovery Timer Type Select */ + __IOM uint32_t MRAMS : 1; /*!< [1..1] Media Clock Recovery AVTP Mode Select */ + __IOM uint32_t MRTNS : 1; /*!< [2..2] Media Clock Recovery Timer Number Select */ + uint32_t : 13; + __IOM uint32_t MRPL : 16; /*!< [31..16] Media Clock Recovery Pulse Length */ + } PTPMCRC1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCL1; /*!< (@ 0x00000314) Media Clock Recovery Time Configuration Register + * L1 */ + + struct + { + __IOM uint32_t MRTVL : 32; /*!< [31..0] Media Clock Recovery Timer Value Lower Part */ + } PTPMCRTCL1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCM1; /*!< (@ 0x00000318) Media Clock Recovery Time Configuration Register + * M1 */ + + struct + { + __IOM uint32_t MRTVM : 32; /*!< [31..0] Media Clock Recovery Timer Value Middle Part */ + } PTPMCRTCM1_b; + }; + + union + { + __IOM uint32_t PTPMCRTCU1; /*!< (@ 0x0000031C) Media Clock Recovery Time Configuration Register + * U1 */ + + struct + { + __IOM uint32_t MRTVU : 16; /*!< [15..0] Media Clock Recovery Timer Value Upper Part */ + __IOM uint32_t MRTT : 2; /*!< [17..16] Media Clock Recovery Trigger Type */ + __IM uint32_t MCRN : 3; /*!< [20..18] Media Clock Recovery Number */ + uint32_t : 10; + __IM uint32_t MRBCR : 1; /*!< [31..31] Media Clock Recovery Buffer Clear Request */ + } PTPMCRTCU1_b; + }; + __IM uint32_t RESERVED11[56]; + + union + { + __IOM uint32_t PTPMCPC0; /*!< (@ 0x00000400) Media Clock Pin Configuration Register 0 */ + + struct + { + __IOM uint32_t PE : 1; /*!< [0..0] Pin Enable */ + __IOM uint32_t MRS : 1; /*!< [1..1] Media Clock Recovery Select */ + uint32_t : 30; + } PTPMCPC0_b; + }; + + union + { + __IOM uint32_t PTPMCPC1; /*!< (@ 0x00000404) Media Clock Pin Configuration Register 1 */ + + struct + { + __IOM uint32_t PE : 1; /*!< [0..0] Pin Enable */ + __IOM uint32_t MRS : 1; /*!< [1..1] Media Clock Recovery Select */ + uint32_t : 30; + } PTPMCPC1_b; + }; + __IM uint32_t RESERVED12[62]; + + union + { + __IOM uint32_t PTPCCC00; /*!< (@ 0x00000500) Cyclic Compare Configuration Register 00 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC00_b; + }; + + union + { + __IOM uint32_t PTPCCC10; /*!< (@ 0x00000504) Cyclic Compare Configuration Register 10 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC10_b; + }; + + union + { + __IOM uint32_t PTPCCC01; /*!< (@ 0x00000508) Cyclic Compare Configuration Register 01 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC01_b; + }; + + union + { + __IOM uint32_t PTPCCC11; /*!< (@ 0x0000050C) Cyclic Compare Configuration Register 11 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC11_b; + }; + + union + { + __IOM uint32_t PTPCCC02; /*!< (@ 0x00000510) Cyclic Compare Configuration Register 02 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC02_b; + }; + + union + { + __IOM uint32_t PTPCCC12; /*!< (@ 0x00000514) Cyclic Compare Configuration Register 12 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC12_b; + }; + + union + { + __IOM uint32_t PTPCCC03; /*!< (@ 0x00000518) Cyclic Compare Configuration Register 03 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC03_b; + }; + + union + { + __IOM uint32_t PTPCCC13; /*!< (@ 0x0000051C) Cyclic Compare Configuration Register 13 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC13_b; + }; + + union + { + __IOM uint32_t PTPCCC04; /*!< (@ 0x00000520) Cyclic Compare Configuration Register 04 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC04_b; + }; + + union + { + __IOM uint32_t PTPCCC14; /*!< (@ 0x00000524) Cyclic Compare Configuration Register 14 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC14_b; + }; + + union + { + __IOM uint32_t PTPCCC05; /*!< (@ 0x00000528) Cyclic Compare Configuration Register 05 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC05_b; + }; + + union + { + __IOM uint32_t PTPCCC15; /*!< (@ 0x0000052C) Cyclic Compare Configuration Register 15 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC15_b; + }; + + union + { + __IOM uint32_t PTPCCC06; /*!< (@ 0x00000530) Cyclic Compare Configuration Register 06 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC06_b; + }; + + union + { + __IOM uint32_t PTPCCC16; /*!< (@ 0x00000534) Cyclic Compare Configuration Register 16 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC16_b; + }; + + union + { + __IOM uint32_t PTPCCC07; /*!< (@ 0x00000538) Cyclic Compare Configuration Register 07 */ + + struct + { + __IOM uint32_t CCTNS : 1; /*!< [0..0] Cyclic Compare Timer Number Select */ + uint32_t : 3; + __IOM uint32_t CCOPS : 1; /*!< [4..4] Cyclic Compare Output Pin Select */ + uint32_t : 27; + } PTPCCC07_b; + }; + + union + { + __IOM uint32_t PTPCCC17; /*!< (@ 0x0000053C) Cyclic Compare Configuration Register 17 */ + + struct + { + __IOM uint32_t CCV : 32; /*!< [31..0] Cycle Compare Value */ + } PTPCCC17_b; + }; + __IM uint32_t RESERVED13[112]; + + union + { + __IOM uint32_t PTPIS0; /*!< (@ 0x00000700) Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t MCCS : 2; /*!< [1..0] Media Clock Capture Status */ + uint32_t : 14; + __IOM uint32_t MCCOES : 2; /*!< [17..16] Media Clock Capture Overflow Error Status */ + uint32_t : 14; + } PTPIS0_b; + }; + + union + { + __IOM uint32_t PTPIE0; /*!< (@ 0x00000704) Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t MCCE : 2; /*!< [1..0] Media Clock Capture Enable */ + uint32_t : 14; + __IOM uint32_t MCCOEE : 2; /*!< [17..16] Media Clock Capture Overflow Error Enable */ + uint32_t : 14; + } PTPIE0_b; + }; + + union + { + __IM uint32_t PTPID0; /*!< (@ 0x00000708) Interrupt Disable Register 0 */ + + struct + { + __IM uint32_t MCCD : 2; /*!< [1..0] Media Clock Capture Disable */ + uint32_t : 14; + __IM uint32_t MCCOED : 2; /*!< [17..16] Media Clock Capture Overflow Error Disable */ + uint32_t : 14; + } PTPID0_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t PTPIS1; /*!< (@ 0x00000710) Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t MCRMS : 2; /*!< [1..0] Media Clock Recovery Match Status */ + uint32_t : 30; + } PTPIS1_b; + }; + + union + { + __IOM uint32_t PTPIE1; /*!< (@ 0x00000714) Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t MCRME : 2; /*!< [1..0] Media Clock Recovery Match Enable */ + uint32_t : 30; + } PTPIE1_b; + }; + + union + { + __IM uint32_t PTPID1; /*!< (@ 0x00000718) Interrupt Disable Register 1 */ + + struct + { + __IM uint32_t MCRMD : 2; /*!< [1..0] Media Clock Recovery Match Disable */ + uint32_t : 30; + } PTPID1_b; + }; + __IM uint32_t RESERVED15[25]; + + union + { + __IOM uint32_t PTPSCR0; /*!< (@ 0x00000780) Security Configuration Register 0 */ + + struct + { + __IOM uint32_t TRSL : 2; /*!< [1..0] TRSL */ + uint32_t : 14; + __IOM uint32_t MCRSL : 2; /*!< [17..16] MCRSL */ + uint32_t : 14; + } PTPSCR0_b; + }; + + union + { + __IOM uint32_t PTPSCR1; /*!< (@ 0x00000784) Security Configuration Register 1 */ + + struct + { + __IOM uint32_t MRRSL : 2; /*!< [1..0] MRRSL */ + uint32_t : 14; + __IOM uint32_t MRRRSL : 2; /*!< [17..16] MRRRSL */ + uint32_t : 14; + } PTPSCR1_b; + }; + + union + { + __IOM uint32_t PTPSCR2; /*!< (@ 0x00000788) Security Configuration Register 2 */ + + struct + { + __IOM uint32_t CCRSL : 2; /*!< [1..0] CCRSL */ + uint32_t : 14; + __IOM uint32_t VRSL : 1; /*!< [16..16] VRSL */ + uint32_t : 15; + } PTPSCR2_b; + }; + __IM uint32_t RESERVED16[541]; + + union + { + __IOM uint32_t POTCFGR; /*!< (@ 0x00001000) Pulse Output Timer Configuration Register */ + + struct + { + __IOM uint32_t REFSEL : 1; /*!< [0..0] Reference Timer Select */ + uint32_t : 31; + } POTCFGR_b; + }; + + union + { + __IOM uint32_t POTCR0; /*!< (@ 0x00001004) Pulse Output Timer Control Register 0 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR0_b; + }; + __IOM uint32_t POTSTRU0; /*!< (@ 0x00001008) Pulse Output Start Time Setting Register U0 */ + __IOM uint32_t POTSTRM0; /*!< (@ 0x0000100C) Pulse Output Start Time Setting Register M0 */ + __IOM uint32_t POTSTRL0; /*!< (@ 0x00001010) Pulse Output Start Time Setting Register L0 */ + __IOM uint32_t POTPERU0; /*!< (@ 0x00001014) Period Setting Register U0 */ + __IOM uint32_t POTPERM0; /*!< (@ 0x00001018) Period Setting Register M0 */ + __IOM uint32_t POTPERL0; /*!< (@ 0x0000101C) Period Setting Register L0 */ + __IOM uint32_t POTPWR0; /*!< (@ 0x00001020) Pulse Width Setting Register 0 */ + __IM uint32_t RESERVED17; + __IM uint32_t POTCPRU0; /*!< (@ 0x00001028) Time Capture Register U0 */ + __IM uint32_t POTCPRM0; /*!< (@ 0x0000102C) Time Capture Register M0 */ + __IM uint32_t POTCPRL0; /*!< (@ 0x00001030) Time Capture Register L0 */ + + union + { + __IOM uint32_t POTCR1; /*!< (@ 0x00001034) Pulse Output Timer Control Register 1 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR1_b; + }; + __IOM uint32_t POTSTRU1; /*!< (@ 0x00001038) Pulse Output Start Time Setting Register U1 */ + __IOM uint32_t POTSTRM1; /*!< (@ 0x0000103C) Pulse Output Start Time Setting Register M1 */ + __IOM uint32_t POTSTRL1; /*!< (@ 0x00001040) Pulse Output Start Time Setting Register L1 */ + __IOM uint32_t POTPERU1; /*!< (@ 0x00001044) Period Setting Register U1 */ + __IOM uint32_t POTPERM1; /*!< (@ 0x00001048) Period Setting Register M1 */ + __IOM uint32_t POTPERL1; /*!< (@ 0x0000104C) Period Setting Register L1 */ + __IOM uint32_t POTPWR1; /*!< (@ 0x00001050) Pulse Width Setting Register 1 */ + __IM uint32_t RESERVED18; + __IM uint32_t POTCPRU1; /*!< (@ 0x00001058) Time Capture Register U1 */ + __IM uint32_t POTCPRM1; /*!< (@ 0x0000105C) Time Capture Register M1 */ + __IM uint32_t POTCPRL1; /*!< (@ 0x00001060) Time Capture Register L1 */ + + union + { + __IOM uint32_t POTCR2; /*!< (@ 0x00001064) Pulse Output Timer Control Register 2 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR2_b; + }; + __IOM uint32_t POTSTRU2; /*!< (@ 0x00001068) Pulse Output Start Time Setting Register U2 */ + __IOM uint32_t POTSTRM2; /*!< (@ 0x0000106C) Pulse Output Start Time Setting Register M2 */ + __IOM uint32_t POTSTRL2; /*!< (@ 0x00001070) Pulse Output Start Time Setting Register L2 */ + __IOM uint32_t POTPERU2; /*!< (@ 0x00001074) Period Setting Register U2 */ + __IOM uint32_t POTPERM2; /*!< (@ 0x00001078) Period Setting Register M2 */ + __IOM uint32_t POTPERL2; /*!< (@ 0x0000107C) Period Setting Register L2 */ + __IOM uint32_t POTPWR2; /*!< (@ 0x00001080) Pulse Width Setting Register 2 */ + __IM uint32_t RESERVED19; + __IM uint32_t POTCPRU2; /*!< (@ 0x00001088) Time Capture Register U2 */ + __IM uint32_t POTCPRM2; /*!< (@ 0x0000108C) Time Capture Register M2 */ + __IM uint32_t POTCPRL2; /*!< (@ 0x00001090) Time Capture Register L2 */ + + union + { + __IOM uint32_t POTCR3; /*!< (@ 0x00001094) Pulse Output Timer Control Register 3 */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Pulse Output Enable */ + uint32_t : 31; + } POTCR3_b; + }; + __IOM uint32_t POTSTRU3; /*!< (@ 0x00001098) Pulse Output Start Time Setting Register U3 */ + __IOM uint32_t POTSTRM3; /*!< (@ 0x0000109C) Pulse Output Start Time Setting Register M3 */ + __IOM uint32_t POTSTRL3; /*!< (@ 0x000010A0) Pulse Output Start Time Setting Register L3 */ + __IOM uint32_t POTPERU3; /*!< (@ 0x000010A4) Period Setting Register U3 */ + __IOM uint32_t POTPERM3; /*!< (@ 0x000010A8) Period Setting Register M3 */ + __IOM uint32_t POTPERL3; /*!< (@ 0x000010AC) Period Setting Register L3 */ + __IOM uint32_t POTPWR3; /*!< (@ 0x000010B0) Pulse Width Setting Register 3 */ + __IM uint32_t RESERVED20; + __IM uint32_t POTCPRU3; /*!< (@ 0x000010B8) Time Capture Register U3 */ + __IM uint32_t POTCPRM3; /*!< (@ 0x000010BC) Time Capture Register M3 */ + __IM uint32_t POTCPRL3; /*!< (@ 0x000010C0) Time Capture Register L3 */ +} R_GPTP_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_GWCA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Gateway CPU Agent (R_GWCA0) + */ + +typedef struct /*!< (@ 0x403CE000) R_GWCA0 Structure */ +{ + union + { + __IOM uint32_t GWMC; /*!< (@ 0x00000000) GWCA Mode Configuration Register (GWMC) */ + + struct + { + __IOM uint32_t OPC : 2; /*!< [1..0] OPC */ + uint32_t : 30; + } GWMC_b; + }; + + union + { + __IOM uint32_t GWMS; /*!< (@ 0x00000004) GWCA Mode Status Register (GWMS) */ + + struct + { + __IOM uint32_t OPS : 2; /*!< [1..0] OPS */ + uint32_t : 30; + } GWMS_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GWIRC; /*!< (@ 0x00000010) GWCA IPV Remapping Configuration Register [802.1Q] + * (GWIRC) */ + + struct + { + __IOM uint32_t IPVR0 : 3; /*!< [2..0] IPVR0 */ + uint32_t : 1; + __IOM uint32_t IPVR1 : 3; /*!< [6..4] IPVR1 */ + uint32_t : 1; + __IOM uint32_t IPVR2 : 3; /*!< [10..8] IPVR2 */ + uint32_t : 1; + __IOM uint32_t IPVR3 : 3; /*!< [14..12] IPVR3 */ + uint32_t : 1; + __IOM uint32_t IPVR4 : 3; /*!< [18..16] IPVR4 */ + uint32_t : 1; + __IOM uint32_t IPVR5 : 3; /*!< [22..20] IPVR5 */ + uint32_t : 1; + __IOM uint32_t IPVR6 : 3; /*!< [26..24] IPVR6 */ + uint32_t : 1; + __IOM uint32_t IPVR7 : 3; /*!< [30..28] IPVR7 */ + uint32_t : 1; + } GWIRC_b; + }; + + union + { + __IOM uint32_t GWRDQSC; /*!< (@ 0x00000014) GWCA RX Descriptor Queue Security Configuration + * Register (GWRDQSC) */ + + struct + { + __IOM uint32_t RDQSL0 : 1; /*!< [0..0] RDQSL0 */ + __IOM uint32_t RDQSL1 : 1; /*!< [1..1] RDQSL1 */ + __IOM uint32_t RDQSL2 : 1; /*!< [2..2] RDQSL2 */ + __IOM uint32_t RDQSL3 : 1; /*!< [3..3] RDQSL3 */ + __IOM uint32_t RDQSL4 : 1; /*!< [4..4] RDQSL4 */ + __IOM uint32_t RDQSL5 : 1; /*!< [5..5] RDQSL5 */ + __IOM uint32_t RDQSL6 : 1; /*!< [6..6] RDQSL6 */ + __IOM uint32_t RDQSL7 : 1; /*!< [7..7] RDQSL7 */ + uint32_t : 24; + } GWRDQSC_b; + }; + + union + { + __IOM uint32_t GWRDQC; /*!< (@ 0x00000018) GWCA RX Descriptor Queue Control Register (GWRDQC) */ + + struct + { + __IOM uint32_t RDQD0 : 1; /*!< [0..0] RDQD0 */ + __IOM uint32_t RDQD1 : 1; /*!< [1..1] RDQD1 */ + __IOM uint32_t RDQD2 : 1; /*!< [2..2] RDQD2 */ + __IOM uint32_t RDQD3 : 1; /*!< [3..3] RDQD3 */ + __IOM uint32_t RDQD4 : 1; /*!< [4..4] RDQD4 */ + __IOM uint32_t RDQD5 : 1; /*!< [5..5] RDQD5 */ + __IOM uint32_t RDQD6 : 1; /*!< [6..6] RDQD6 */ + __IOM uint32_t RDQD7 : 1; /*!< [7..7] RDQD7 */ + uint32_t : 8; + __IOM uint32_t RDQP0 : 1; /*!< [16..16] RDQP0 */ + __IOM uint32_t RDQP1 : 1; /*!< [17..17] RDQP1 */ + __IOM uint32_t RDQP2 : 1; /*!< [18..18] RDQP2 */ + __IOM uint32_t RDQP3 : 1; /*!< [19..19] RDQP3 */ + __IOM uint32_t RDQP4 : 1; /*!< [20..20] RDQP4 */ + __IOM uint32_t RDQP5 : 1; /*!< [21..21] RDQP5 */ + __IOM uint32_t RDQP6 : 1; /*!< [22..22] RDQP6 */ + __IOM uint32_t RDQP7 : 1; /*!< [23..23] RDQP7 */ + uint32_t : 8; + } GWRDQC_b; + }; + + union + { + __IOM uint32_t GWRDQAC; /*!< (@ 0x0000001C) GWCA RX Descriptor Queue Arbitration Control + * Register (GWRDQAC) */ + + struct + { + __IOM uint32_t RDQA0 : 4; /*!< [3..0] RDQA0 */ + __IOM uint32_t RDQA1 : 4; /*!< [7..4] RDQA1 */ + __IOM uint32_t RDQA2 : 4; /*!< [11..8] RDQA2 */ + __IOM uint32_t RDQA3 : 4; /*!< [15..12] RDQA3 */ + __IOM uint32_t RDQA4 : 4; /*!< [19..16] RDQA4 */ + __IOM uint32_t RDQA5 : 4; /*!< [23..20] RDQA5 */ + __IOM uint32_t RDQA6 : 4; /*!< [27..24] RDQA6 */ + __IOM uint32_t RDQA7 : 4; /*!< [31..28] RDQA7 */ + } GWRDQAC_b; + }; + + union + { + __IOM uint32_t GWRGC; /*!< (@ 0x00000020) GWCA RX General Configuration Register (GWRGC) */ + + struct + { + __IOM uint32_t RCPT : 1; /*!< [0..0] RCPT */ + uint32_t : 31; + } GWRGC_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t GWRMFSC0; /*!< (@ 0x00000040) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC0_b; + }; + + union + { + __IOM uint32_t GWRMFSC1; /*!< (@ 0x00000044) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC1_b; + }; + + union + { + __IOM uint32_t GWRMFSC2; /*!< (@ 0x00000048) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC2_b; + }; + + union + { + __IOM uint32_t GWRMFSC3; /*!< (@ 0x0000004C) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC3_b; + }; + + union + { + __IOM uint32_t GWRMFSC4; /*!< (@ 0x00000050) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC4_b; + }; + + union + { + __IOM uint32_t GWRMFSC5; /*!< (@ 0x00000054) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC5_b; + }; + + union + { + __IOM uint32_t GWRMFSC6; /*!< (@ 0x00000058) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC6_b; + }; + + union + { + __IOM uint32_t GWRMFSC7; /*!< (@ 0x0000005C) GWCA Reception Maximum Frame Size Configuration + * Register q (GWRMFSCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t MFS : 16; /*!< [15..0] MFS */ + uint32_t : 16; + } GWRMFSC7_b; + }; + + union + { + __IOM uint32_t GWRDQDC0; /*!< (@ 0x00000060) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC0_b; + }; + + union + { + __IOM uint32_t GWRDQDC1; /*!< (@ 0x00000064) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC1_b; + }; + + union + { + __IOM uint32_t GWRDQDC2; /*!< (@ 0x00000068) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC2_b; + }; + + union + { + __IOM uint32_t GWRDQDC3; /*!< (@ 0x0000006C) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC3_b; + }; + + union + { + __IOM uint32_t GWRDQDC4; /*!< (@ 0x00000070) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC4_b; + }; + + union + { + __IOM uint32_t GWRDQDC5; /*!< (@ 0x00000074) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC5_b; + }; + + union + { + __IOM uint32_t GWRDQDC6; /*!< (@ 0x00000078) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC6_b; + }; + + union + { + __IOM uint32_t GWRDQDC7; /*!< (@ 0x0000007C) GWCA Reception Descriptor Queue Depth Configuration + * Register q (GWRDQDCq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DQD : 11; /*!< [10..0] DQD */ + uint32_t : 21; + } GWRDQDC7_b; + }; + + union + { + __IOM uint32_t GWRDQM0; /*!< (@ 0x00000080) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM0_b; + }; + + union + { + __IOM uint32_t GWRDQM1; /*!< (@ 0x00000084) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM1_b; + }; + + union + { + __IOM uint32_t GWRDQM2; /*!< (@ 0x00000088) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM2_b; + }; + + union + { + __IOM uint32_t GWRDQM3; /*!< (@ 0x0000008C) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM3_b; + }; + + union + { + __IOM uint32_t GWRDQM4; /*!< (@ 0x00000090) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM4_b; + }; + + union + { + __IOM uint32_t GWRDQM5; /*!< (@ 0x00000094) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM5_b; + }; + + union + { + __IOM uint32_t GWRDQM6; /*!< (@ 0x00000098) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM6_b; + }; + + union + { + __IOM uint32_t GWRDQM7; /*!< (@ 0x0000009C) GWCA RX Descriptor Queue q Monitoring Register + * (GWRDQMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DNQ : 11; /*!< [10..0] DNQ */ + uint32_t : 21; + } GWRDQM7_b; + }; + + union + { + __IOM uint32_t GWRDQMLM0; /*!< (@ 0x000000A0) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM0_b; + }; + + union + { + __IOM uint32_t GWRDQMLM1; /*!< (@ 0x000000A4) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM1_b; + }; + + union + { + __IOM uint32_t GWRDQMLM2; /*!< (@ 0x000000A8) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM2_b; + }; + + union + { + __IOM uint32_t GWRDQMLM3; /*!< (@ 0x000000AC) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM3_b; + }; + + union + { + __IOM uint32_t GWRDQMLM4; /*!< (@ 0x000000B0) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM4_b; + }; + + union + { + __IOM uint32_t GWRDQMLM5; /*!< (@ 0x000000B4) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM5_b; + }; + + union + { + __IOM uint32_t GWRDQMLM6; /*!< (@ 0x000000B8) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM6_b; + }; + + union + { + __IOM uint32_t GWRDQMLM7; /*!< (@ 0x000000BC) GWCA RX Descriptor Queue q Max Level Monitoring + * Register (GWRDQMLMq) (q = 0 to 7) */ + + struct + { + __IOM uint32_t DMLQ : 11; /*!< [10..0] DMLQ */ + uint32_t : 21; + } GWRDQMLM7_b; + }; + __IM uint32_t RESERVED2[16]; + + union + { + __IOM uint32_t GWMTIRM; /*!< (@ 0x00000100) GWCA Multicast Table Initialization Register + * Monitoring Register (GWMTIRM) */ + + struct + { + __IOM uint32_t MTIOG : 1; /*!< [0..0] MTIOG */ + __IOM uint32_t MTR : 1; /*!< [1..1] MTR */ + uint32_t : 30; + } GWMTIRM_b; + }; + + union + { + __IOM uint32_t GWMSTLS; /*!< (@ 0x00000104) GWCA Multicast Table Learning Setting Register + * (GWMSTLS) */ + + struct + { + __IOM uint32_t MNRCNL : 7; /*!< [6..0] MNRCNL */ + uint32_t : 1; + __IOM uint32_t MNL : 3; /*!< [10..8] MNL */ + uint32_t : 5; + __IOM uint32_t MSENL : 7; /*!< [22..16] MSENL */ + uint32_t : 9; + } GWMSTLS_b; + }; + + union + { + __IOM uint32_t GWMSTLR; /*!< (@ 0x00000108) GWCA Multicast Table Learning Result Register + * (GWMSTLR) */ + + struct + { + __IOM uint32_t MTLF : 1; /*!< [0..0] MTLF */ + uint32_t : 30; + __IOM uint32_t MTL : 1; /*!< [31..31] MTL */ + } GWMSTLR_b; + }; + + union + { + __IOM uint32_t GWMSTSS; /*!< (@ 0x0000010C) GWCA Multicast Table Searching Setting Register + * (GWMSTSS) */ + + struct + { + __IOM uint32_t MSENS : 7; /*!< [6..0] MSENS */ + uint32_t : 25; + } GWMSTSS_b; + }; + + union + { + __IOM uint32_t GWMSTSR; /*!< (@ 0x00000110) GWCA Multicast Table Searching Result Register + * (GWMSTSR) */ + + struct + { + __IOM uint32_t MNRCNR : 7; /*!< [6..0] MNRCNR */ + uint32_t : 1; + __IOM uint32_t MNR : 3; /*!< [10..8] MNR */ + uint32_t : 5; + __IOM uint32_t MTSEF : 1; /*!< [16..16] MTSEF */ + uint32_t : 14; + __IOM uint32_t MTS : 1; /*!< [31..31] MTS */ + } GWMSTSR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t GWMAC0; /*!< (@ 0x00000120) GWCA MAC Address Configuration Register 0 (GWMAC0) */ + + struct + { + __IOM uint32_t MAUP : 16; /*!< [15..0] MAUP */ + uint32_t : 16; + } GWMAC0_b; + }; + + union + { + __IOM uint32_t GWMAC1; /*!< (@ 0x00000124) GWCA MAC Address Configuration Register 1 (GWMAC1) */ + + struct + { + __IOM uint32_t MADP : 32; /*!< [31..0] MADP */ + } GWMAC1_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t GWVCC; /*!< (@ 0x00000130) GWCA VLAN Control Configuration Register (GWVCC) */ + + struct + { + __IOM uint32_t VIM : 1; /*!< [0..0] VIM */ + uint32_t : 7; + __IOM uint32_t CTVUM : 1; /*!< [8..8] CTVUM */ + uint32_t : 7; + __IOM uint32_t VEM : 3; /*!< [18..16] VEM */ + uint32_t : 13; + } GWVCC_b; + }; + + union + { + __IOM uint32_t GWVTC; /*!< (@ 0x00000134) GWCA VLAN TAG Configuration Register (GWVTC) */ + + struct + { + __IOM uint32_t CTV : 12; /*!< [11..0] CTV */ + __IOM uint32_t CTP : 3; /*!< [14..12] CTP */ + __IOM uint32_t CTD : 1; /*!< [15..15] CTD */ + __IOM uint32_t STV : 12; /*!< [27..16] STV */ + __IOM uint32_t STP : 3; /*!< [30..28] STP */ + __IOM uint32_t STD : 1; /*!< [31..31] STD */ + } GWVTC_b; + }; + + union + { + __IOM uint32_t GWTTFC; /*!< (@ 0x00000138) GWCA Transmission TAG Filtering Configuration + * Register (GWTTFC) */ + + struct + { + __IOM uint32_t NT : 1; /*!< [0..0] NT */ + __IOM uint32_t RT : 1; /*!< [1..1] RT */ + __IOM uint32_t CST : 1; /*!< [2..2] CST */ + __IOM uint32_t CSRT : 1; /*!< [3..3] CSRT */ + __IOM uint32_t CT : 1; /*!< [4..4] CT */ + __IOM uint32_t CRT : 1; /*!< [5..5] CRT */ + __IOM uint32_t SCT : 1; /*!< [6..6] SCT */ + __IOM uint32_t SCRT : 1; /*!< [7..7] SCRT */ + __IOM uint32_t UT : 1; /*!< [8..8] UT */ + uint32_t : 23; + } GWTTFC_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t GWTDCAC00; /*!< (@ 0x00000140) GWCA Timestamp Descriptor Chain Address Configuration + * Register 0s (GWTDCAC0s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCAUP : 8; /*!< [7..0] TSCCAUP */ + uint32_t : 24; + } GWTDCAC00_b; + }; + + union + { + __IOM uint32_t GWTDCAC10; /*!< (@ 0x00000144) GWCA Timestamp Descriptor Chain Address Configuration + * Register 1s (GWTDCAC1s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCADP : 32; /*!< [31..0] TSCCADP */ + } GWTDCAC10_b; + }; + + union + { + __IOM uint32_t GWTDCAC01; /*!< (@ 0x00000148) GWCA Timestamp Descriptor Chain Address Configuration + * Register 0s (GWTDCAC0s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCAUP : 8; /*!< [7..0] TSCCAUP */ + uint32_t : 24; + } GWTDCAC01_b; + }; + + union + { + __IOM uint32_t GWTDCAC11; /*!< (@ 0x0000014C) GWCA Timestamp Descriptor Chain Address Configuration + * Register 1s (GWTDCAC1s) (s = 0, 1) */ + + struct + { + __IOM uint32_t TSCCADP : 32; /*!< [31..0] TSCCADP */ + } GWTDCAC11_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t GWTSDCC0; /*!< (@ 0x00000160) GWCA Timestamp Descriptor Chain Configuration + * Register s (GWTSDCCs) (s = 0, 1) */ + + struct + { + __IOM uint32_t TE : 1; /*!< [0..0] TE */ + __IOM uint32_t DCS : 2; /*!< [2..1] DCS */ + uint32_t : 5; + __IOM uint32_t OSID : 3; /*!< [10..8] OSID */ + uint32_t : 21; + } GWTSDCC0_b; + }; + + union + { + __IOM uint32_t GWTSDCC1; /*!< (@ 0x00000164) GWCA Timestamp Descriptor Chain Configuration + * Register s (GWTSDCCs) (s = 0, 1) */ + + struct + { + __IOM uint32_t TE : 1; /*!< [0..0] TE */ + __IOM uint32_t DCS : 2; /*!< [2..1] DCS */ + uint32_t : 5; + __IOM uint32_t OSID : 3; /*!< [10..8] OSID */ + uint32_t : 21; + } GWTSDCC1_b; + }; + __IM uint32_t RESERVED7[6]; + + union + { + __IOM uint32_t GWTSNM; /*!< (@ 0x00000180) GWCA Timestamp Number Monitoring Register (GWTSNM) */ + + struct + { + __IOM uint32_t TNTR : 8; /*!< [7..0] TNTR */ + uint32_t : 24; + } GWTSNM_b; + }; + + union + { + __IOM uint32_t GWTSMNM; /*!< (@ 0x00000184) GWCA Timestamp Maximum Number Monitoring Register + * (GWTSMNM) */ + + struct + { + __IOM uint32_t TMNTR : 8; /*!< [7..0] TMNTR */ + uint32_t : 24; + } GWTSMNM_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t GWAC; /*!< (@ 0x00000190) GWCA AXI Control Register (GWAC) */ + + struct + { + __IOM uint32_t AMPR : 1; /*!< [0..0] AMPR */ + __IOM uint32_t AMP : 1; /*!< [1..1] AMP */ + uint32_t : 30; + } GWAC_b; + }; + + union + { + __IOM uint32_t GWDCBAC0; /*!< (@ 0x00000194) GWCA Descriptor Chain Base Address Configuration + * Register 0 (GWDCBAC0) */ + + struct + { + __IOM uint32_t DCBAUP : 8; /*!< [7..0] DCBAUP */ + uint32_t : 24; + } GWDCBAC0_b; + }; + + union + { + __IOM uint32_t GWDCBAC1; /*!< (@ 0x00000198) GWCA Descriptor Chain Base Address Configuration + * Register 1 (GWDCBAC1) */ + + struct + { + __IOM uint32_t DCBADP : 32; /*!< [31..0] DCBADP */ + } GWDCBAC1_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t GWMDNC; /*!< (@ 0x000001A0) GWCA Maximum Descriptor Number Configuration + * Register (GWMDNC) */ + + struct + { + __IOM uint32_t RXDMN : 5; /*!< [4..0] RXDMN */ + uint32_t : 3; + __IOM uint32_t TXDMN : 5; /*!< [12..8] TXDMN */ + uint32_t : 3; + __IOM uint32_t TSDMN : 2; /*!< [17..16] TSDMN */ + uint32_t : 14; + } GWMDNC_b; + }; + __IM uint32_t RESERVED10[23]; + __IOM uint32_t GWTRC0; /*!< (@ 0x00000200) GWCA Transmission Request Configuration Register + * i (GWTRCi) (i = 0, 1) */ + __IOM uint32_t GWTRC1; /*!< (@ 0x00000204) GWCA Transmission Request Configuration Register + * i (GWTRCi) (i = 0, 1) */ + __IM uint32_t RESERVED11[62]; + + union + { + __IOM uint32_t GWTPC0; /*!< (@ 0x00000300) GWCA Transmission Pause Configuration Register + * p (GWTPCp) (p = 0, 1) */ + + struct + { + __IOM uint32_t PPPL0 : 1; /*!< [0..0] PPPL0 */ + __IOM uint32_t PPPL1 : 1; /*!< [1..1] PPPL1 */ + __IOM uint32_t PPPL2 : 1; /*!< [2..2] PPPL2 */ + __IOM uint32_t PPPL3 : 1; /*!< [3..3] PPPL3 */ + __IOM uint32_t PPPL4 : 1; /*!< [4..4] PPPL4 */ + __IOM uint32_t PPPL5 : 1; /*!< [5..5] PPPL5 */ + __IOM uint32_t PPPL6 : 1; /*!< [6..6] PPPL6 */ + __IOM uint32_t PPPL7 : 1; /*!< [7..7] PPPL7 */ + __IOM uint32_t PPPL8 : 1; /*!< [8..8] PPPL8 */ + uint32_t : 23; + } GWTPC0_b; + }; + + union + { + __IOM uint32_t GWTPC1; /*!< (@ 0x00000304) GWCA Transmission Pause Configuration Register + * p (GWTPCp) (p = 0, 1) */ + + struct + { + __IOM uint32_t PPPL0 : 1; /*!< [0..0] PPPL0 */ + __IOM uint32_t PPPL1 : 1; /*!< [1..1] PPPL1 */ + __IOM uint32_t PPPL2 : 1; /*!< [2..2] PPPL2 */ + __IOM uint32_t PPPL3 : 1; /*!< [3..3] PPPL3 */ + __IOM uint32_t PPPL4 : 1; /*!< [4..4] PPPL4 */ + __IOM uint32_t PPPL5 : 1; /*!< [5..5] PPPL5 */ + __IOM uint32_t PPPL6 : 1; /*!< [6..6] PPPL6 */ + __IOM uint32_t PPPL7 : 1; /*!< [7..7] PPPL7 */ + __IOM uint32_t PPPL8 : 1; /*!< [8..8] PPPL8 */ + uint32_t : 23; + } GWTPC1_b; + }; + __IM uint32_t RESERVED12[30]; + + union + { + __IOM uint32_t GWARIRM; /*!< (@ 0x00000380) GWCA AXI RAM Initialization Register Monitoring + * Register (GWARIRM) */ + + struct + { + __IOM uint32_t ARIOG : 1; /*!< [0..0] ARIOG */ + __IOM uint32_t ARR : 1; /*!< [1..1] ARR */ + uint32_t : 30; + } GWARIRM_b; + }; + __IM uint32_t RESERVED13[31]; + + union + { + __IOM uint32_t GWDCC0; /*!< (@ 0x00000400) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC0_b; + }; + + union + { + __IOM uint32_t GWDCC1; /*!< (@ 0x00000404) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC1_b; + }; + + union + { + __IOM uint32_t GWDCC2; /*!< (@ 0x00000408) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC2_b; + }; + + union + { + __IOM uint32_t GWDCC3; /*!< (@ 0x0000040C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC3_b; + }; + + union + { + __IOM uint32_t GWDCC4; /*!< (@ 0x00000410) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC4_b; + }; + + union + { + __IOM uint32_t GWDCC5; /*!< (@ 0x00000414) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC5_b; + }; + + union + { + __IOM uint32_t GWDCC6; /*!< (@ 0x00000418) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC6_b; + }; + + union + { + __IOM uint32_t GWDCC7; /*!< (@ 0x0000041C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC7_b; + }; + + union + { + __IOM uint32_t GWDCC8; /*!< (@ 0x00000420) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC8_b; + }; + + union + { + __IOM uint32_t GWDCC9; /*!< (@ 0x00000424) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC9_b; + }; + + union + { + __IOM uint32_t GWDCC10; /*!< (@ 0x00000428) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC10_b; + }; + + union + { + __IOM uint32_t GWDCC11; /*!< (@ 0x0000042C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC11_b; + }; + + union + { + __IOM uint32_t GWDCC12; /*!< (@ 0x00000430) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC12_b; + }; + + union + { + __IOM uint32_t GWDCC13; /*!< (@ 0x00000434) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC13_b; + }; + + union + { + __IOM uint32_t GWDCC14; /*!< (@ 0x00000438) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC14_b; + }; + + union + { + __IOM uint32_t GWDCC15; /*!< (@ 0x0000043C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC15_b; + }; + + union + { + __IOM uint32_t GWDCC16; /*!< (@ 0x00000440) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC16_b; + }; + + union + { + __IOM uint32_t GWDCC17; /*!< (@ 0x00000444) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC17_b; + }; + + union + { + __IOM uint32_t GWDCC18; /*!< (@ 0x00000448) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC18_b; + }; + + union + { + __IOM uint32_t GWDCC19; /*!< (@ 0x0000044C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC19_b; + }; + + union + { + __IOM uint32_t GWDCC20; /*!< (@ 0x00000450) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC20_b; + }; + + union + { + __IOM uint32_t GWDCC21; /*!< (@ 0x00000454) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC21_b; + }; + + union + { + __IOM uint32_t GWDCC22; /*!< (@ 0x00000458) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC22_b; + }; + + union + { + __IOM uint32_t GWDCC23; /*!< (@ 0x0000045C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC23_b; + }; + + union + { + __IOM uint32_t GWDCC24; /*!< (@ 0x00000460) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC24_b; + }; + + union + { + __IOM uint32_t GWDCC25; /*!< (@ 0x00000464) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC25_b; + }; + + union + { + __IOM uint32_t GWDCC26; /*!< (@ 0x00000468) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC26_b; + }; + + union + { + __IOM uint32_t GWDCC27; /*!< (@ 0x0000046C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC27_b; + }; + + union + { + __IOM uint32_t GWDCC28; /*!< (@ 0x00000470) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC28_b; + }; + + union + { + __IOM uint32_t GWDCC29; /*!< (@ 0x00000474) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC29_b; + }; + + union + { + __IOM uint32_t GWDCC30; /*!< (@ 0x00000478) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC30_b; + }; + + union + { + __IOM uint32_t GWDCC31; /*!< (@ 0x0000047C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC31_b; + }; + + union + { + __IOM uint32_t GWDCC32; /*!< (@ 0x00000480) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC32_b; + }; + + union + { + __IOM uint32_t GWDCC33; /*!< (@ 0x00000484) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC33_b; + }; + + union + { + __IOM uint32_t GWDCC34; /*!< (@ 0x00000488) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC34_b; + }; + + union + { + __IOM uint32_t GWDCC35; /*!< (@ 0x0000048C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC35_b; + }; + + union + { + __IOM uint32_t GWDCC36; /*!< (@ 0x00000490) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC36_b; + }; + + union + { + __IOM uint32_t GWDCC37; /*!< (@ 0x00000494) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC37_b; + }; + + union + { + __IOM uint32_t GWDCC38; /*!< (@ 0x00000498) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC38_b; + }; + + union + { + __IOM uint32_t GWDCC39; /*!< (@ 0x0000049C) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC39_b; + }; + + union + { + __IOM uint32_t GWDCC40; /*!< (@ 0x000004A0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC40_b; + }; + + union + { + __IOM uint32_t GWDCC41; /*!< (@ 0x000004A4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC41_b; + }; + + union + { + __IOM uint32_t GWDCC42; /*!< (@ 0x000004A8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC42_b; + }; + + union + { + __IOM uint32_t GWDCC43; /*!< (@ 0x000004AC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC43_b; + }; + + union + { + __IOM uint32_t GWDCC44; /*!< (@ 0x000004B0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC44_b; + }; + + union + { + __IOM uint32_t GWDCC45; /*!< (@ 0x000004B4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC45_b; + }; + + union + { + __IOM uint32_t GWDCC46; /*!< (@ 0x000004B8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC46_b; + }; + + union + { + __IOM uint32_t GWDCC47; /*!< (@ 0x000004BC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC47_b; + }; + + union + { + __IOM uint32_t GWDCC48; /*!< (@ 0x000004C0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC48_b; + }; + + union + { + __IOM uint32_t GWDCC49; /*!< (@ 0x000004C4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC49_b; + }; + + union + { + __IOM uint32_t GWDCC50; /*!< (@ 0x000004C8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC50_b; + }; + + union + { + __IOM uint32_t GWDCC51; /*!< (@ 0x000004CC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC51_b; + }; + + union + { + __IOM uint32_t GWDCC52; /*!< (@ 0x000004D0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC52_b; + }; + + union + { + __IOM uint32_t GWDCC53; /*!< (@ 0x000004D4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC53_b; + }; + + union + { + __IOM uint32_t GWDCC54; /*!< (@ 0x000004D8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC54_b; + }; + + union + { + __IOM uint32_t GWDCC55; /*!< (@ 0x000004DC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC55_b; + }; + + union + { + __IOM uint32_t GWDCC56; /*!< (@ 0x000004E0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC56_b; + }; + + union + { + __IOM uint32_t GWDCC57; /*!< (@ 0x000004E4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC57_b; + }; + + union + { + __IOM uint32_t GWDCC58; /*!< (@ 0x000004E8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC58_b; + }; + + union + { + __IOM uint32_t GWDCC59; /*!< (@ 0x000004EC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC59_b; + }; + + union + { + __IOM uint32_t GWDCC60; /*!< (@ 0x000004F0) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC60_b; + }; + + union + { + __IOM uint32_t GWDCC61; /*!< (@ 0x000004F4) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC61_b; + }; + + union + { + __IOM uint32_t GWDCC62; /*!< (@ 0x000004F8) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC62_b; + }; + + union + { + __IOM uint32_t GWDCC63; /*!< (@ 0x000004FC) GWCA Descriptor Chain Configuration Register + * i (GWDCCi) (i = 0 to 63) */ + + struct + { + __IOM uint32_t SM : 2; /*!< [1..0] SM */ + uint32_t : 6; + __IOM uint32_t EDE : 1; /*!< [8..8] EDE */ + __IOM uint32_t ETS : 1; /*!< [9..9] ETS */ + __IOM uint32_t SL : 1; /*!< [10..10] SL */ + __IOM uint32_t DQT : 1; /*!< [11..11] DQT */ + uint32_t : 4; + __IOM uint32_t DCP : 3; /*!< [18..16] DCP */ + uint32_t : 5; + __IOM uint32_t BALR : 1; /*!< [24..24] BALR */ + uint32_t : 3; + __IOM uint32_t OSID : 3; /*!< [30..28] OSID */ + uint32_t : 1; + } GWDCC63_b; + }; + __IM uint32_t RESERVED14[192]; + + union + { + __IOM uint32_t GWAARSS; /*!< (@ 0x00000800) GWCA AXI Address RAM Searching Setting Register + * (GWAARSS) */ + + struct + { + __IOM uint32_t AARA : 7; /*!< [6..0] AARA */ + uint32_t : 25; + } GWAARSS_b; + }; + + union + { + __IOM uint32_t GWAARSR0; /*!< (@ 0x00000804) GWCA AXI Address RAM Searching Result Register + * 0 (GWAARSR0) */ + + struct + { + __IOM uint32_t ACARU : 8; /*!< [7..0] ACARU */ + uint32_t : 8; + __IOM uint32_t AARSEF : 1; /*!< [16..16] AARSEF */ + __IOM uint32_t AARSSF : 1; /*!< [17..17] AARSSF */ + uint32_t : 13; + __IOM uint32_t AARS : 1; /*!< [31..31] AARS */ + } GWAARSR0_b; + }; + + union + { + __IOM uint32_t GWAARSR1; /*!< (@ 0x00000808) GWCA AXI Address RAM Searching Result Register + * 1 (GWAARSR1) */ + + struct + { + __IOM uint32_t ACARD : 32; /*!< [31..0] ACARD */ + } GWAARSR1_b; + }; + __IM uint32_t RESERVED15[13]; + + union + { + __IOM uint32_t GWIDAUAS0; /*!< (@ 0x00000840) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS0_b; + }; + + union + { + __IOM uint32_t GWIDAUAS1; /*!< (@ 0x00000844) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS1_b; + }; + + union + { + __IOM uint32_t GWIDAUAS2; /*!< (@ 0x00000848) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS2_b; + }; + + union + { + __IOM uint32_t GWIDAUAS3; /*!< (@ 0x0000084C) GWCA Incremental Data Area Used Area Size Register + * i (GWIDAUASi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAUAS : 24; /*!< [23..0] IDAUAS */ + uint32_t : 8; + } GWIDAUAS3_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __IOM uint32_t GWIDASM0; /*!< (@ 0x00000880) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM0_b; + }; + + union + { + __IOM uint32_t GWIDASM1; /*!< (@ 0x00000884) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM1_b; + }; + + union + { + __IOM uint32_t GWIDASM2; /*!< (@ 0x00000888) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM2_b; + }; + + union + { + __IOM uint32_t GWIDASM3; /*!< (@ 0x0000088C) GWCA Incremental Data Area Size Monitoring Register + * i (GWIDASMi) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDAS : 24; /*!< [23..0] IDAS */ + uint32_t : 8; + } GWIDASM3_b; + }; + __IM uint32_t RESERVED17[28]; + + union + { + __IOM uint32_t GWIDASAM00; /*!< (@ 0x00000900) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM00_b; + }; + + union + { + __IOM uint32_t GWIDASAM10; /*!< (@ 0x00000904) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM10_b; + }; + + union + { + __IOM uint32_t GWIDASAM01; /*!< (@ 0x00000908) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM01_b; + }; + + union + { + __IOM uint32_t GWIDASAM11; /*!< (@ 0x0000090C) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM11_b; + }; + + union + { + __IOM uint32_t GWIDASAM02; /*!< (@ 0x00000910) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM02_b; + }; + + union + { + __IOM uint32_t GWIDASAM12; /*!< (@ 0x00000914) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM12_b; + }; + + union + { + __IOM uint32_t GWIDASAM03; /*!< (@ 0x00000918) GWCA Incremental Data Area Start Address Monitoring + * Register 0i (GWIDASAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAU : 8; /*!< [7..0] IDASAU */ + uint32_t : 24; + } GWIDASAM03_b; + }; + + union + { + __IOM uint32_t GWIDASAM13; /*!< (@ 0x0000091C) GWCA Incremental Data Area Start Address Monitoring + * Register 1i (GWIDASAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDASAL : 32; /*!< [31..0] IDASAL */ + } GWIDASAM13_b; + }; + __IM uint32_t RESERVED18[24]; + + union + { + __IOM uint32_t GWIDACAM00; /*!< (@ 0x00000980) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM00_b; + }; + + union + { + __IOM uint32_t GWIDACAM10; /*!< (@ 0x00000984) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM10_b; + }; + + union + { + __IOM uint32_t GWIDACAM01; /*!< (@ 0x00000988) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM01_b; + }; + + union + { + __IOM uint32_t GWIDACAM11; /*!< (@ 0x0000098C) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM11_b; + }; + + union + { + __IOM uint32_t GWIDACAM02; /*!< (@ 0x00000990) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM02_b; + }; + + union + { + __IOM uint32_t GWIDACAM12; /*!< (@ 0x00000994) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM12_b; + }; + + union + { + __IOM uint32_t GWIDACAM03; /*!< (@ 0x00000998) GWCA Incremental Data Area Current Address Monitoring + * Register 0i (GWIDACAM0i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAU : 8; /*!< [7..0] IDACAU */ + uint32_t : 24; + } GWIDACAM03_b; + }; + + union + { + __IOM uint32_t GWIDACAM13; /*!< (@ 0x0000099C) GWCA Incremental Data Area Current Address Monitoring + * Register 1i (GWIDACAM1i) (i = 0 to 3) */ + + struct + { + __IOM uint32_t IDACAL : 32; /*!< [31..0] IDACAL */ + } GWIDACAM13_b; + }; + __IM uint32_t RESERVED19[24]; + + union + { + __IOM uint32_t GWGRLC; /*!< (@ 0x00000A00) GWCA Global Rate Limiter Configuration Register + * (GWGRLC) */ + + struct + { + __IOM uint32_t GRLIV : 16; /*!< [15..0] GRLIV */ + __IOM uint32_t GRLE : 1; /*!< [16..16] GRLE */ + __IOM uint32_t GRLULRS : 1; /*!< [17..17] GRLULRS */ + uint32_t : 14; + } GWGRLC_b; + }; + + union + { + __IOM uint32_t GWGRLULC; /*!< (@ 0x00000A04) GWCA Global Rate Limiter Upper Limit Configuration + * Register (GWGRLULC) */ + + struct + { + __IOM uint32_t GRLUL : 24; /*!< [23..0] GRLUL */ + uint32_t : 8; + } GWGRLULC_b; + }; + __IM uint32_t RESERVED20[30]; + + union + { + __IOM uint32_t GWRLC0; /*!< (@ 0x00000A80) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC0_b; + }; + + union + { + __IOM uint32_t GWRLULC0; /*!< (@ 0x00000A84) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC0_b; + }; + + union + { + __IOM uint32_t GWRLC1; /*!< (@ 0x00000A88) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC1_b; + }; + + union + { + __IOM uint32_t GWRLULC1; /*!< (@ 0x00000A8C) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC1_b; + }; + + union + { + __IOM uint32_t GWRLC2; /*!< (@ 0x00000A90) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC2_b; + }; + + union + { + __IOM uint32_t GWRLULC2; /*!< (@ 0x00000A94) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC2_b; + }; + + union + { + __IOM uint32_t GWRLC3; /*!< (@ 0x00000A98) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC3_b; + }; + + union + { + __IOM uint32_t GWRLULC3; /*!< (@ 0x00000A9C) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC3_b; + }; + + union + { + __IOM uint32_t GWRLC4; /*!< (@ 0x00000AA0) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC4_b; + }; + + union + { + __IOM uint32_t GWRLULC4; /*!< (@ 0x00000AA4) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC4_b; + }; + + union + { + __IOM uint32_t GWRLC5; /*!< (@ 0x00000AA8) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC5_b; + }; + + union + { + __IOM uint32_t GWRLULC5; /*!< (@ 0x00000AAC) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC5_b; + }; + + union + { + __IOM uint32_t GWRLC6; /*!< (@ 0x00000AB0) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC6_b; + }; + + union + { + __IOM uint32_t GWRLULC6; /*!< (@ 0x00000AB4) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC6_b; + }; + + union + { + __IOM uint32_t GWRLC7; /*!< (@ 0x00000AB8) GWCA Rate Limiter Configuration Register i (GWRLCi) + * (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLIV : 12; /*!< [11..0] RLIV */ + uint32_t : 4; + __IOM uint32_t RLE : 1; /*!< [16..16] RLE */ + uint32_t : 15; + } GWRLC7_b; + }; + + union + { + __IOM uint32_t GWRLULC7; /*!< (@ 0x00000ABC) GWCA Rate Limiter Upper Limit Configuration Register + * i (GWRLULCi) (i = 0 to 7) */ + + struct + { + __IOM uint32_t RLUL : 24; /*!< [23..0] RLUL */ + uint32_t : 8; + } GWRLULC7_b; + }; + __IM uint32_t RESERVED21[48]; + + union + { + __IOM uint32_t GWIDPC; /*!< (@ 0x00000B80) GWCA Interrupt Delay Prescaler Configuration + * Register (GWIDPC) */ + + struct + { + __IOM uint32_t IDPV : 10; /*!< [9..0] IDPV */ + uint32_t : 22; + } GWIDPC_b; + }; + __IM uint32_t RESERVED22[31]; + + union + { + __IOM uint32_t GWIDC0; /*!< (@ 0x00000C00) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC0_b; + }; + + union + { + __IOM uint32_t GWIDC1; /*!< (@ 0x00000C04) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC1_b; + }; + + union + { + __IOM uint32_t GWIDC2; /*!< (@ 0x00000C08) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC2_b; + }; + + union + { + __IOM uint32_t GWIDC3; /*!< (@ 0x00000C0C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC3_b; + }; + + union + { + __IOM uint32_t GWIDC4; /*!< (@ 0x00000C10) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC4_b; + }; + + union + { + __IOM uint32_t GWIDC5; /*!< (@ 0x00000C14) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC5_b; + }; + + union + { + __IOM uint32_t GWIDC6; /*!< (@ 0x00000C18) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC6_b; + }; + + union + { + __IOM uint32_t GWIDC7; /*!< (@ 0x00000C1C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC7_b; + }; + + union + { + __IOM uint32_t GWIDC8; /*!< (@ 0x00000C20) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC8_b; + }; + + union + { + __IOM uint32_t GWIDC9; /*!< (@ 0x00000C24) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC9_b; + }; + + union + { + __IOM uint32_t GWIDC10; /*!< (@ 0x00000C28) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC10_b; + }; + + union + { + __IOM uint32_t GWIDC11; /*!< (@ 0x00000C2C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC11_b; + }; + + union + { + __IOM uint32_t GWIDC12; /*!< (@ 0x00000C30) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC12_b; + }; + + union + { + __IOM uint32_t GWIDC13; /*!< (@ 0x00000C34) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC13_b; + }; + + union + { + __IOM uint32_t GWIDC14; /*!< (@ 0x00000C38) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC14_b; + }; + + union + { + __IOM uint32_t GWIDC15; /*!< (@ 0x00000C3C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC15_b; + }; + + union + { + __IOM uint32_t GWIDC16; /*!< (@ 0x00000C40) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC16_b; + }; + + union + { + __IOM uint32_t GWIDC17; /*!< (@ 0x00000C44) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC17_b; + }; + + union + { + __IOM uint32_t GWIDC18; /*!< (@ 0x00000C48) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC18_b; + }; + + union + { + __IOM uint32_t GWIDC19; /*!< (@ 0x00000C4C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC19_b; + }; + + union + { + __IOM uint32_t GWIDC20; /*!< (@ 0x00000C50) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC20_b; + }; + + union + { + __IOM uint32_t GWIDC21; /*!< (@ 0x00000C54) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC21_b; + }; + + union + { + __IOM uint32_t GWIDC22; /*!< (@ 0x00000C58) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC22_b; + }; + + union + { + __IOM uint32_t GWIDC23; /*!< (@ 0x00000C5C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC23_b; + }; + + union + { + __IOM uint32_t GWIDC24; /*!< (@ 0x00000C60) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC24_b; + }; + + union + { + __IOM uint32_t GWIDC25; /*!< (@ 0x00000C64) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC25_b; + }; + + union + { + __IOM uint32_t GWIDC26; /*!< (@ 0x00000C68) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC26_b; + }; + + union + { + __IOM uint32_t GWIDC27; /*!< (@ 0x00000C6C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC27_b; + }; + + union + { + __IOM uint32_t GWIDC28; /*!< (@ 0x00000C70) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC28_b; + }; + + union + { + __IOM uint32_t GWIDC29; /*!< (@ 0x00000C74) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC29_b; + }; + + union + { + __IOM uint32_t GWIDC30; /*!< (@ 0x00000C78) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC30_b; + }; + + union + { + __IOM uint32_t GWIDC31; /*!< (@ 0x00000C7C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC31_b; + }; + + union + { + __IOM uint32_t GWIDC32; /*!< (@ 0x00000C80) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC32_b; + }; + + union + { + __IOM uint32_t GWIDC33; /*!< (@ 0x00000C84) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC33_b; + }; + + union + { + __IOM uint32_t GWIDC34; /*!< (@ 0x00000C88) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC34_b; + }; + + union + { + __IOM uint32_t GWIDC35; /*!< (@ 0x00000C8C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC35_b; + }; + + union + { + __IOM uint32_t GWIDC36; /*!< (@ 0x00000C90) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC36_b; + }; + + union + { + __IOM uint32_t GWIDC37; /*!< (@ 0x00000C94) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC37_b; + }; + + union + { + __IOM uint32_t GWIDC38; /*!< (@ 0x00000C98) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC38_b; + }; + + union + { + __IOM uint32_t GWIDC39; /*!< (@ 0x00000C9C) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC39_b; + }; + + union + { + __IOM uint32_t GWIDC40; /*!< (@ 0x00000CA0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC40_b; + }; + + union + { + __IOM uint32_t GWIDC41; /*!< (@ 0x00000CA4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC41_b; + }; + + union + { + __IOM uint32_t GWIDC42; /*!< (@ 0x00000CA8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC42_b; + }; + + union + { + __IOM uint32_t GWIDC43; /*!< (@ 0x00000CAC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC43_b; + }; + + union + { + __IOM uint32_t GWIDC44; /*!< (@ 0x00000CB0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC44_b; + }; + + union + { + __IOM uint32_t GWIDC45; /*!< (@ 0x00000CB4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC45_b; + }; + + union + { + __IOM uint32_t GWIDC46; /*!< (@ 0x00000CB8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC46_b; + }; + + union + { + __IOM uint32_t GWIDC47; /*!< (@ 0x00000CBC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC47_b; + }; + + union + { + __IOM uint32_t GWIDC48; /*!< (@ 0x00000CC0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC48_b; + }; + + union + { + __IOM uint32_t GWIDC49; /*!< (@ 0x00000CC4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC49_b; + }; + + union + { + __IOM uint32_t GWIDC50; /*!< (@ 0x00000CC8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC50_b; + }; + + union + { + __IOM uint32_t GWIDC51; /*!< (@ 0x00000CCC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC51_b; + }; + + union + { + __IOM uint32_t GWIDC52; /*!< (@ 0x00000CD0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC52_b; + }; + + union + { + __IOM uint32_t GWIDC53; /*!< (@ 0x00000CD4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC53_b; + }; + + union + { + __IOM uint32_t GWIDC54; /*!< (@ 0x00000CD8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC54_b; + }; + + union + { + __IOM uint32_t GWIDC55; /*!< (@ 0x00000CDC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC55_b; + }; + + union + { + __IOM uint32_t GWIDC56; /*!< (@ 0x00000CE0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC56_b; + }; + + union + { + __IOM uint32_t GWIDC57; /*!< (@ 0x00000CE4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC57_b; + }; + + union + { + __IOM uint32_t GWIDC58; /*!< (@ 0x00000CE8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC58_b; + }; + + union + { + __IOM uint32_t GWIDC59; /*!< (@ 0x00000CEC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC59_b; + }; + + union + { + __IOM uint32_t GWIDC60; /*!< (@ 0x00000CF0) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC60_b; + }; + + union + { + __IOM uint32_t GWIDC61; /*!< (@ 0x00000CF4) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC61_b; + }; + + union + { + __IOM uint32_t GWIDC62; /*!< (@ 0x00000CF8) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC62_b; + }; + + union + { + __IOM uint32_t GWIDC63; /*!< (@ 0x00000CFC) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC63_b; + }; + + union + { + __IOM uint32_t GWIDC64; /*!< (@ 0x00000D00) GWCA Interrupt Delay Configuration Register (GWIDCi) + * (i = 0 to 64) */ + + struct + { + __IOM uint32_t IDV : 12; /*!< [11..0] IDV */ + uint32_t : 20; + } GWIDC64_b; + }; + __IM uint32_t RESERVED23[191]; + + union + { + __IOM uint32_t GWRDCN; /*!< (@ 0x00001000) GWCA Received Data Counter Register (GWRDCN) */ + + struct + { + __IOM uint32_t RDN : 32; /*!< [31..0] RDN */ + } GWRDCN_b; + }; + + union + { + __IOM uint32_t GWTDCN; /*!< (@ 0x00001004) GWCA Transmitted Data Counter Register (GWTDCN) */ + + struct + { + __IOM uint32_t TDN : 32; /*!< [31..0] TDN */ + } GWTDCN_b; + }; + + union + { + __IOM uint32_t GWTSCN; /*!< (@ 0x00001008) GWCA Timestamp Counter Register (GWTSCN) */ + + struct + { + __IOM uint32_t TN : 32; /*!< [31..0] TN */ + } GWTSCN_b; + }; + + union + { + __IOM uint32_t GWTSOVFECN; /*!< (@ 0x0000100C) GWCA Timestamp Overflow Error Counter Register + * (GWTSOVFECN) */ + + struct + { + __IOM uint32_t TSOVFEN : 16; /*!< [15..0] TSOVFEN */ + uint32_t : 16; + } GWTSOVFECN_b; + }; + + union + { + __IOM uint32_t GWUSMFSECN; /*!< (@ 0x00001010) GWCA Under Switch Minimum Frame Size Error Counter + * Register (GWUSMFSECN) */ + + struct + { + __IOM uint32_t USMFSEN : 16; /*!< [15..0] USMFSEN */ + uint32_t : 16; + } GWUSMFSECN_b; + }; + + union + { + __IOM uint32_t GWTFECN; /*!< (@ 0x00001014) GWCA TAG Filtering Error Counter Register (GWTFECN) */ + + struct + { + __IOM uint32_t TFEN : 16; /*!< [15..0] TFEN */ + uint32_t : 16; + } GWTFECN_b; + }; + + union + { + __IOM uint32_t GWSEQECN; /*!< (@ 0x00001018) GWCA Sequence Error Counter Register (GWSEQECN) */ + + struct + { + __IOM uint32_t SEQEN : 16; /*!< [15..0] SEQEN */ + uint32_t : 16; + } GWSEQECN_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t GWTXDNECN; /*!< (@ 0x00001020) GWCA TX Descriptor Number Error Counter Register + * (GWTXDNECN) */ + + struct + { + __IOM uint32_t TXDNEN : 16; /*!< [15..0] TXDNEN */ + uint32_t : 16; + } GWTXDNECN_b; + }; + + union + { + __IOM uint32_t GWFSECN; /*!< (@ 0x00001024) GWCA Frame Size Error Counter Register (GWFSECN) */ + + struct + { + __IOM uint32_t FSEN : 16; /*!< [15..0] FSEN */ + uint32_t : 16; + } GWFSECN_b; + }; + + union + { + __IOM uint32_t GWTDFECN; /*!< (@ 0x00001028) GWCA Timestamp Descriptor Full Error Counter + * Register (GWTDFECN) */ + + struct + { + __IOM uint32_t TDFEN : 16; /*!< [15..0] TDFEN */ + uint32_t : 16; + } GWTDFECN_b; + }; + + union + { + __IOM uint32_t GWTSDNECN; /*!< (@ 0x0000102C) GWCA Timestamp Descriptor Number Error Counter + * Register (GWTSDNECN) */ + + struct + { + __IOM uint32_t TSDNEN : 16; /*!< [15..0] TSDNEN */ + uint32_t : 16; + } GWTSDNECN_b; + }; + + union + { + __IOM uint32_t GWDQOECN; /*!< (@ 0x00001030) GWCA Descriptor Queue Overflow Error Counter + * Register (GWDQOECN) */ + + struct + { + __IOM uint32_t DQOEN : 16; /*!< [15..0] DQOEN */ + uint32_t : 16; + } GWDQOECN_b; + }; + + union + { + __IOM uint32_t GWDQSECN; /*!< (@ 0x00001034) GWCA Descriptor Queue Security Error Counter + * Register (GWDQSECN) */ + + struct + { + __IOM uint32_t DQSEN : 16; /*!< [15..0] DQSEN */ + uint32_t : 16; + } GWDQSECN_b; + }; + + union + { + __IOM uint32_t GWDFECN; /*!< (@ 0x00001038) GWCA Descriptor Full Error Counter Register (GWDFECN) */ + + struct + { + __IOM uint32_t DFEN : 16; /*!< [15..0] DFEN */ + uint32_t : 16; + } GWDFECN_b; + }; + + union + { + __IOM uint32_t GWDSECN; /*!< (@ 0x0000103C) GWCA Descriptor Security Error Counter Register + * (GWDSECN) */ + + struct + { + __IOM uint32_t DSEN : 16; /*!< [15..0] DSEN */ + uint32_t : 16; + } GWDSECN_b; + }; + + union + { + __IOM uint32_t GWDSZECN; /*!< (@ 0x00001040) GWCA Data Size Error Counter Register (GWDSZECN) */ + + struct + { + __IOM uint32_t DSZEN : 16; /*!< [15..0] DSZEN */ + uint32_t : 16; + } GWDSZECN_b; + }; + + union + { + __IOM uint32_t GWDCTECN; /*!< (@ 0x00001044) GWCA Descriptor Chain Type Error Counter Register + * (GWDCTECN) */ + + struct + { + __IOM uint32_t DCTEN : 16; /*!< [15..0] DCTEN */ + uint32_t : 16; + } GWDCTECN_b; + }; + + union + { + __IOM uint32_t GWRXDNECN; /*!< (@ 0x00001048) GWCA RX Descriptor Number Error Counter Register + * (GWRXDNECN) */ + + struct + { + __IOM uint32_t RXDNEN : 16; /*!< [15..0] RXDNEN */ + uint32_t : 16; + } GWRXDNECN_b; + }; + __IM uint32_t RESERVED25[45]; + __IOM uint32_t GWDIS0; /*!< (@ 0x00001100) GWCA Data Interrupt Status Register i (GWDISi) + * (i = 0, 1) */ + __IOM uint32_t GWDIE0; /*!< (@ 0x00001104) GWCA Data Interrupt Enable Register i (GWDIEi) + * (i = 0, 1) */ + __IOM uint32_t GWDID0; /*!< (@ 0x00001108) GWCA Data Interrupt Disable Register i (GWDIDi) + * (i = 0, 1) */ + __IOM uint32_t GWDIDS0; /*!< (@ 0x0000110C) GWCA Data Interrupt Delayed Status Register i + * (GWDIDSi) (i = 0, 1) */ + __IOM uint32_t GWDIS1; /*!< (@ 0x00001110) GWCA Data Interrupt Status Register i (GWDISi) + * (i = 0, 1) */ + __IOM uint32_t GWDIE1; /*!< (@ 0x00001114) GWCA Data Interrupt Enable Register i (GWDIEi) + * (i = 0, 1) */ + __IOM uint32_t GWDID1; /*!< (@ 0x00001118) GWCA Data Interrupt Disable Register i (GWDIDi) + * (i = 0, 1) */ + __IOM uint32_t GWDIDS1; /*!< (@ 0x0000111C) GWCA Data Interrupt Delayed Status Register i + * (GWDIDSi) (i = 0, 1) */ + __IM uint32_t RESERVED26[24]; + + union + { + __IOM uint32_t GWTSDIS; /*!< (@ 0x00001180) GWCA Timestamp Data Interrupt Status Register + * (GWTSDIS) */ + + struct + { + __IOM uint32_t TSDIS0 : 1; /*!< [0..0] TSDIS0 */ + __IOM uint32_t TSDIS1 : 1; /*!< [1..1] TSDIS1 */ + uint32_t : 30; + } GWTSDIS_b; + }; + + union + { + __IOM uint32_t GWTSDIE; /*!< (@ 0x00001184) GWCA Timestamp Data Interrupt Enable Register + * (GWTSDIE) */ + + struct + { + __IOM uint32_t TSDIE0 : 1; /*!< [0..0] TSDIE0 */ + __IOM uint32_t TSDIE1 : 1; /*!< [1..1] TSDIE1 */ + uint32_t : 30; + } GWTSDIE_b; + }; + + union + { + __IOM uint32_t GWTSDID; /*!< (@ 0x00001188) GWCA Timestamp Data Interrupt Disable Register + * (GWTSDID) */ + + struct + { + __IOM uint32_t TSDID0 : 1; /*!< [0..0] TSDID0 */ + __IOM uint32_t TSDID1 : 1; /*!< [1..1] TSDID1 */ + uint32_t : 30; + } GWTSDID_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IOM uint32_t GWEIS0; /*!< (@ 0x00001190) GWCA Error Interrupt Status Register 0 (GWEIS0) */ + + struct + { + __IOM uint32_t AES : 1; /*!< [0..0] AES */ + __IOM uint32_t DECCES : 1; /*!< [1..1] DECCES */ + __IOM uint32_t TECCES : 1; /*!< [2..2] TECCES */ + __IOM uint32_t PECCES : 1; /*!< [3..3] PECCES */ + __IOM uint32_t DSECCES : 1; /*!< [4..4] DSECCES */ + __IOM uint32_t MECCES : 1; /*!< [5..5] MECCES */ + __IOM uint32_t AECCES : 1; /*!< [6..6] AECCES */ + __IOM uint32_t TSECCES : 1; /*!< [7..7] TSECCES */ + __IOM uint32_t L23UECCES : 1; /*!< [8..8] L23UECCES */ + __IOM uint32_t TSOVFES : 1; /*!< [9..9] TSOVFES */ + __IOM uint32_t USMFSES : 1; /*!< [10..10] USMFSES */ + __IOM uint32_t TFES : 1; /*!< [11..11] TFES */ + __IOM uint32_t SEQES : 1; /*!< [12..12] SEQES */ + uint32_t : 1; + __IOM uint32_t TXDNES : 1; /*!< [14..14] TXDNES */ + __IOM uint32_t TSHES : 1; /*!< [15..15] TSHES */ + __IOM uint32_t FSES0 : 1; /*!< [16..16] FSES0 */ + __IOM uint32_t FSES1 : 1; /*!< [17..17] FSES1 */ + __IOM uint32_t FSES2 : 1; /*!< [18..18] FSES2 */ + __IOM uint32_t FSES3 : 1; /*!< [19..19] FSES3 */ + __IOM uint32_t FSES4 : 1; /*!< [20..20] FSES4 */ + __IOM uint32_t FSES5 : 1; /*!< [21..21] FSES5 */ + __IOM uint32_t FSES6 : 1; /*!< [22..22] FSES6 */ + __IOM uint32_t FSES7 : 1; /*!< [23..23] FSES7 */ + __IOM uint32_t TDFES0 : 1; /*!< [24..24] TDFES0 */ + __IOM uint32_t TDFES1 : 1; /*!< [25..25] TDFES1 */ + uint32_t : 2; + __IOM uint32_t TSDNES0 : 1; /*!< [28..28] TSDNES0 */ + __IOM uint32_t TSDNES1 : 1; /*!< [29..29] TSDNES1 */ + uint32_t : 2; + } GWEIS0_b; + }; + + union + { + __IOM uint32_t GWEIE0; /*!< (@ 0x00001194) GWCA Error Interrupt Enable Register 0 (GWEIE0) */ + + struct + { + __IOM uint32_t AEE : 1; /*!< [0..0] AEE */ + __IOM uint32_t DECCEE : 1; /*!< [1..1] DECCEE */ + __IOM uint32_t TECCEE : 1; /*!< [2..2] TECCEE */ + __IOM uint32_t PECCEE : 1; /*!< [3..3] PECCEE */ + __IOM uint32_t DSECCEE : 1; /*!< [4..4] DSECCEE */ + __IOM uint32_t MECCEE : 1; /*!< [5..5] MECCEE */ + __IOM uint32_t AECCEE : 1; /*!< [6..6] AECCEE */ + __IOM uint32_t TSECCEE : 1; /*!< [7..7] TSECCEE */ + __IOM uint32_t L23UECCEE : 1; /*!< [8..8] L23UECCEE */ + __IOM uint32_t TSOVFEE : 1; /*!< [9..9] TSOVFEE */ + __IOM uint32_t USMFSEE : 1; /*!< [10..10] USMFSEE */ + __IOM uint32_t TFEE : 1; /*!< [11..11] TFEE */ + __IOM uint32_t SEQEE : 1; /*!< [12..12] SEQEE */ + uint32_t : 1; + __IOM uint32_t TXDNEE : 1; /*!< [14..14] TXDNEE */ + __IOM uint32_t TSHEE : 1; /*!< [15..15] TSHEE */ + __IOM uint32_t FSEE0 : 1; /*!< [16..16] FSEE0 */ + __IOM uint32_t FSEE1 : 1; /*!< [17..17] FSEE1 */ + __IOM uint32_t FSEE2 : 1; /*!< [18..18] FSEE2 */ + __IOM uint32_t FSEE3 : 1; /*!< [19..19] FSEE3 */ + __IOM uint32_t FSEE4 : 1; /*!< [20..20] FSEE4 */ + __IOM uint32_t FSEE5 : 1; /*!< [21..21] FSEE5 */ + __IOM uint32_t FSEE6 : 1; /*!< [22..22] FSEE6 */ + __IOM uint32_t FSEE7 : 1; /*!< [23..23] FSEE7 */ + __IOM uint32_t TDFEE0 : 1; /*!< [24..24] TDFEE0 */ + __IOM uint32_t TDFEE1 : 1; /*!< [25..25] TDFEE1 */ + uint32_t : 2; + __IOM uint32_t TSDNEE0 : 1; /*!< [28..28] TSDNEE0 */ + __IOM uint32_t TSDNEE1 : 1; /*!< [29..29] TSDNEE1 */ + uint32_t : 2; + } GWEIE0_b; + }; + + union + { + __IOM uint32_t GWEID0; /*!< (@ 0x00001198) GWCA Error Interrupt Disable Register 0 (GWEID0) */ + + struct + { + __IOM uint32_t AED : 1; /*!< [0..0] AED */ + __IOM uint32_t TECCED : 1; /*!< [1..1] TECCED */ + __IOM uint32_t DECCED : 1; /*!< [2..2] DECCED */ + __IOM uint32_t PECCED : 1; /*!< [3..3] PECCED */ + __IOM uint32_t DSECCED : 1; /*!< [4..4] DSECCED */ + __IOM uint32_t MECCED : 1; /*!< [5..5] MECCED */ + __IOM uint32_t AECCED : 1; /*!< [6..6] AECCED */ + __IOM uint32_t TSECCED : 1; /*!< [7..7] TSECCED */ + __IOM uint32_t L23UECCED : 1; /*!< [8..8] L23UECCED */ + __IOM uint32_t TSOVFED : 1; /*!< [9..9] TSOVFED */ + __IOM uint32_t USMFSED : 1; /*!< [10..10] USMFSED */ + __IOM uint32_t TFED : 1; /*!< [11..11] TFED */ + __IOM uint32_t SEQED : 1; /*!< [12..12] SEQED */ + __IOM uint32_t IIPED : 1; /*!< [13..13] IIPED */ + __IOM uint32_t TXDNED : 1; /*!< [14..14] TXDNED */ + __IOM uint32_t TSHED : 1; /*!< [15..15] TSHED */ + __IOM uint32_t FSED0 : 1; /*!< [16..16] FSED0 */ + __IOM uint32_t FSED1 : 1; /*!< [17..17] FSED1 */ + __IOM uint32_t FSED2 : 1; /*!< [18..18] FSED2 */ + __IOM uint32_t FSED3 : 1; /*!< [19..19] FSED3 */ + __IOM uint32_t FSED4 : 1; /*!< [20..20] FSED4 */ + __IOM uint32_t FSED5 : 1; /*!< [21..21] FSED5 */ + __IOM uint32_t FSED6 : 1; /*!< [22..22] FSED6 */ + __IOM uint32_t FSED7 : 1; /*!< [23..23] FSED7 */ + __IOM uint32_t TDFED0 : 1; /*!< [24..24] TDFED0 */ + __IOM uint32_t TDFED1 : 1; /*!< [25..25] TDFED1 */ + uint32_t : 2; + __IOM uint32_t TSDNED0 : 1; /*!< [28..28] TSDNED0 */ + __IOM uint32_t TSDNED1 : 1; /*!< [29..29] TSDNED1 */ + uint32_t : 2; + } GWEID0_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IOM uint32_t GWEIS1; /*!< (@ 0x000011A0) GWCA Error Interrupt Status Register 1 (GWEIS1) */ + + struct + { + __IOM uint32_t DQOES0 : 1; /*!< [0..0] DQOES0 */ + __IOM uint32_t DQOES1 : 1; /*!< [1..1] DQOES1 */ + __IOM uint32_t DQOES2 : 1; /*!< [2..2] DQOES2 */ + __IOM uint32_t DQOES3 : 1; /*!< [3..3] DQOES3 */ + __IOM uint32_t DQOES4 : 1; /*!< [4..4] DQOES4 */ + __IOM uint32_t DQOES5 : 1; /*!< [5..5] DQOES5 */ + __IOM uint32_t DQOES6 : 1; /*!< [6..6] DQOES6 */ + __IOM uint32_t DQOES7 : 1; /*!< [7..7] DQOES7 */ + uint32_t : 8; + __IOM uint32_t DQSES0 : 1; /*!< [16..16] DQSES0 */ + __IOM uint32_t DQSES1 : 1; /*!< [17..17] DQSES1 */ + __IOM uint32_t DQSES2 : 1; /*!< [18..18] DQSES2 */ + __IOM uint32_t DQSES3 : 1; /*!< [19..19] DQSES3 */ + __IOM uint32_t DQSES4 : 1; /*!< [20..20] DQSES4 */ + __IOM uint32_t DQSES5 : 1; /*!< [21..21] DQSES5 */ + __IOM uint32_t DQSES6 : 1; /*!< [22..22] DQSES6 */ + __IOM uint32_t DQSES7 : 1; /*!< [23..23] DQSES7 */ + uint32_t : 8; + } GWEIS1_b; + }; + + union + { + __IOM uint32_t GWEIE1; /*!< (@ 0x000011A4) GWCA Error Interrupt Enable Register 1 (GWEIE1) */ + + struct + { + __IOM uint32_t DQOEE0 : 1; /*!< [0..0] DQOEE0 */ + __IOM uint32_t DQOEE1 : 1; /*!< [1..1] DQOEE1 */ + __IOM uint32_t DQOEE2 : 1; /*!< [2..2] DQOEE2 */ + __IOM uint32_t DQOEE3 : 1; /*!< [3..3] DQOEE3 */ + __IOM uint32_t DQOEE4 : 1; /*!< [4..4] DQOEE4 */ + __IOM uint32_t DQOEE5 : 1; /*!< [5..5] DQOEE5 */ + __IOM uint32_t DQOEE6 : 1; /*!< [6..6] DQOEE6 */ + __IOM uint32_t DQOEE7 : 1; /*!< [7..7] DQOEE7 */ + uint32_t : 8; + __IOM uint32_t DQSEE0 : 1; /*!< [16..16] DQSEE0 */ + __IOM uint32_t DQSEE1 : 1; /*!< [17..17] DQSEE1 */ + __IOM uint32_t DQSEE2 : 1; /*!< [18..18] DQSEE2 */ + __IOM uint32_t DQSEE3 : 1; /*!< [19..19] DQSEE3 */ + __IOM uint32_t DQSEE4 : 1; /*!< [20..20] DQSEE4 */ + __IOM uint32_t DQSEE5 : 1; /*!< [21..21] DQSEE5 */ + __IOM uint32_t DQSEE6 : 1; /*!< [22..22] DQSEE6 */ + __IOM uint32_t DQSEE7 : 1; /*!< [23..23] DQSEE7 */ + uint32_t : 8; + } GWEIE1_b; + }; + + union + { + __IOM uint32_t GWEID1; /*!< (@ 0x000011A8) GWCA Error Interrupt Disable Register 1 (GWEID1) */ + + struct + { + __IOM uint32_t DQOED0 : 1; /*!< [0..0] DQOED0 */ + __IOM uint32_t DQOED1 : 1; /*!< [1..1] DQOED1 */ + __IOM uint32_t DQOED2 : 1; /*!< [2..2] DQOED2 */ + __IOM uint32_t DQOED3 : 1; /*!< [3..3] DQOED3 */ + __IOM uint32_t DQOED4 : 1; /*!< [4..4] DQOED4 */ + __IOM uint32_t DQOED5 : 1; /*!< [5..5] DQOED5 */ + __IOM uint32_t DQOED6 : 1; /*!< [6..6] DQOED6 */ + __IOM uint32_t DQOED7 : 1; /*!< [7..7] DQOED7 */ + uint32_t : 8; + __IOM uint32_t DQSED0 : 1; /*!< [16..16] DQSED0 */ + __IOM uint32_t DQSED1 : 1; /*!< [17..17] DQSED1 */ + __IOM uint32_t DQSED2 : 1; /*!< [18..18] DQSED2 */ + __IOM uint32_t DQSED3 : 1; /*!< [19..19] DQSED3 */ + __IOM uint32_t DQSED4 : 1; /*!< [20..20] DQSED4 */ + __IOM uint32_t DQSED5 : 1; /*!< [21..21] DQSED5 */ + __IOM uint32_t DQSED6 : 1; /*!< [22..22] DQSED6 */ + __IOM uint32_t DQSED7 : 1; /*!< [23..23] DQSED7 */ + uint32_t : 8; + } GWEID1_b; + }; + __IM uint32_t RESERVED29[21]; + __IOM uint32_t GWEIS20; /*!< (@ 0x00001200) GWCA Error Interrupt Status Register 2i (GWEIS2i) + * (i = 0, 1) */ + __IOM uint32_t GWEIE20; /*!< (@ 0x00001204) GWCA Error Interrupt Enable Register 2i (GWEIE2i) + * (i = 0, 1) */ + __IOM uint32_t GWEID20; /*!< (@ 0x00001208) GWCA Error Interrupt Disable Register 2i (GWEID2i) + * (i = 0, 1) */ + __IM uint32_t RESERVED30; + __IOM uint32_t GWEIS21; /*!< (@ 0x00001210) GWCA Error Interrupt Status Register 2i (GWEIS2i) + * (i = 0, 1) */ + __IOM uint32_t GWEIE21; /*!< (@ 0x00001214) GWCA Error Interrupt Enable Register 2i (GWEIE2i) + * (i = 0, 1) */ + __IOM uint32_t GWEID21; /*!< (@ 0x00001218) GWCA Error Interrupt Disable Register 2i (GWEID2i) + * (i = 0, 1) */ + __IM uint32_t RESERVED31[25]; + + union + { + __IOM uint32_t GWEIS3; /*!< (@ 0x00001280) GWCA Error Interrupt Status Register 3 (GWEIS3) */ + + struct + { + __IOM uint32_t IAOES0 : 1; /*!< [0..0] IAOES0 */ + __IOM uint32_t IAOES1 : 1; /*!< [1..1] IAOES1 */ + __IOM uint32_t IAOES2 : 1; /*!< [2..2] IAOES2 */ + __IOM uint32_t IAOES3 : 1; /*!< [3..3] IAOES3 */ + __IOM uint32_t IAOES4 : 1; /*!< [4..4] IAOES4 */ + uint32_t : 27; + } GWEIS3_b; + }; + + union + { + __IOM uint32_t GWEIE3; /*!< (@ 0x00001284) GWCA Error Interrupt Enable Register 3 (GWEIE3) */ + + struct + { + __IOM uint32_t IAOEE0 : 1; /*!< [0..0] IAOEE0 */ + __IOM uint32_t IAOEE1 : 1; /*!< [1..1] IAOEE1 */ + __IOM uint32_t IAOEE2 : 1; /*!< [2..2] IAOEE2 */ + __IOM uint32_t IAOEE3 : 1; /*!< [3..3] IAOEE3 */ + __IOM uint32_t IAOEE4 : 1; /*!< [4..4] IAOEE4 */ + uint32_t : 27; + } GWEIE3_b; + }; + + union + { + __IOM uint32_t GWEID3; /*!< (@ 0x00001288) GWCA Error Interrupt Disable Register 3 (GWEID3) */ + + struct + { + __IOM uint32_t IAOED0 : 1; /*!< [0..0] IAOED0 */ + __IOM uint32_t IAOED1 : 1; /*!< [1..1] IAOED1 */ + __IOM uint32_t IAOED2 : 1; /*!< [2..2] IAOED2 */ + __IOM uint32_t IAOED3 : 1; /*!< [3..3] IAOED3 */ + __IOM uint32_t IAOED4 : 1; /*!< [4..4] IAOED4 */ + uint32_t : 27; + } GWEID3_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t GWEIS4; /*!< (@ 0x00001290) GWCA Error Interrupt Status Register 4 (GWEIS4) */ + + struct + { + __IOM uint32_t DSSES : 1; /*!< [0..0] DSSES */ + __IOM uint32_t DSSEIOS : 1; /*!< [1..1] DSSEIOS */ + uint32_t : 6; + __IOM uint32_t DSSECN : 6; /*!< [13..8] DSSECN */ + uint32_t : 2; + __IOM uint32_t DSES : 1; /*!< [16..16] DSES */ + __IOM uint32_t DSEIOS : 1; /*!< [17..17] DSEIOS */ + uint32_t : 6; + __IOM uint32_t DSECN : 6; /*!< [29..24] DSECN */ + uint32_t : 2; + } GWEIS4_b; + }; + + union + { + __IOM uint32_t GWEIE4; /*!< (@ 0x00001294) GWCA Error Interrupt Enable Register 4 (GWEIE4) */ + + struct + { + __IOM uint32_t DSSEE : 1; /*!< [0..0] DSSEE */ + __IOM uint32_t DSSEIOE : 1; /*!< [1..1] DSSEIOE */ + uint32_t : 14; + __IOM uint32_t DSEE : 1; /*!< [16..16] DSEE */ + __IOM uint32_t DSEIOE : 1; /*!< [17..17] DSEIOE */ + uint32_t : 14; + } GWEIE4_b; + }; + + union + { + __IOM uint32_t GWEID4; /*!< (@ 0x00001298) GWCA Error Interrupt Disable Register 4 (GWEID4) */ + + struct + { + __IOM uint32_t DSSED : 1; /*!< [0..0] DSSED */ + __IOM uint32_t DSSEIOD : 1; /*!< [1..1] DSSEIOD */ + uint32_t : 14; + __IOM uint32_t DSED : 1; /*!< [16..16] DSED */ + __IOM uint32_t DSEIOD : 1; /*!< [17..17] DSEIOD */ + uint32_t : 14; + } GWEID4_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t GWEIS5; /*!< (@ 0x000012A0) GWCA Error Interrupt Status Register 5 (GWEIS5) */ + + struct + { + __IOM uint32_t DCTES : 1; /*!< [0..0] DCTES */ + __IOM uint32_t DCTEIOS : 1; /*!< [1..1] DCTEIOS */ + uint32_t : 6; + __IOM uint32_t DCTECN : 6; /*!< [13..8] DCTECN */ + uint32_t : 2; + __IOM uint32_t RXDNES : 1; /*!< [16..16] RXDNES */ + __IOM uint32_t RXDNEIOS : 1; /*!< [17..17] RXDNEIOS */ + uint32_t : 14; + } GWEIS5_b; + }; + + union + { + __IOM uint32_t GWEIE5; /*!< (@ 0x000012A4) GWCA Error Interrupt Enable Register 5 (GWEIE5) */ + + struct + { + __IOM uint32_t DCTEE : 1; /*!< [0..0] DCTEE */ + __IOM uint32_t DCTEIOE : 1; /*!< [1..1] DCTEIOE */ + uint32_t : 14; + __IOM uint32_t RXDNEE : 1; /*!< [16..16] RXDNEE */ + __IOM uint32_t RXDNEIOE : 1; /*!< [17..17] RXDNEIOE */ + uint32_t : 14; + } GWEIE5_b; + }; + + union + { + __IOM uint32_t GWEID5; /*!< (@ 0x000012A8) GWCA Error Interrupt Disable Register 5 (GWEID5) */ + + struct + { + __IOM uint32_t DCTED : 1; /*!< [0..0] DCTED */ + __IOM uint32_t DCTEIOD : 1; /*!< [1..1] DCTEIOD */ + uint32_t : 13; + __IOM uint32_t RXDNED : 1; /*!< [15..15] RXDNED */ + __IOM uint32_t RXDNEIOD : 1; /*!< [16..16] RXDNEIOD */ + uint32_t : 15; + } GWEID5_b; + }; +} R_GWCA0_Type; /*!< Size = 4780 (0x12ac) */ + +/* =========================================================================================================================== */ +/* ================ R_IPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Inter-Processor Communication (R_IPC) + */ + +typedef struct /*!< (@ 0x40020000) R_IPC Structure */ +{ + union + { + __IOM uint32_t IPCSEM[16]; /*!< (@ 0x00000000) Semaphore Registers */ + + struct + { + __IOM uint32_t LOCK : 1; /*!< [0..0] Indicates the shared resource is locked */ + uint32_t : 31; + } IPCSEM_b[16]; + }; + __IM uint32_t RESERVED[16]; + __IOM R_IPC_IPCNMI_Type IPC0NMI; /*!< (@ 0x00000080) Inter-Processor NMI Registers */ + __IOM R_IPC_IPCNMI_Type IPC1NMI; /*!< (@ 0x00000090) Inter-Processor NMI Registers */ + __IM uint32_t RESERVED1[8]; + __IOM R_IPC_IPC_Type IPC0; /*!< (@ 0x000000C0) Inter-Processor Registers */ + __IOM R_IPC_IPC_Type IPC1; /*!< (@ 0x00000100) Inter-Processor Registers */ +} R_IPC_Type; /*!< Size = 320 (0x140) */ + +/* =========================================================================================================================== */ +/* ================ R_MFWD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Message Forwarding Engine (R_MFWD) + */ + +typedef struct /*!< (@ 0x403C0000) R_MFWD Structure */ +{ + union + { + __IOM uint32_t FWGC; /*!< (@ 0x00000000) General Configuration Register */ + + struct + { + __IOM uint32_t SVM : 2; /*!< [1..0] Switch VLAN Mode */ + uint32_t : 30; + } FWGC_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t FWTTC0; /*!< (@ 0x00000010) TAG TPID Configuration Register 0 */ + + struct + { + __IOM uint32_t CTT : 16; /*!< [15..0] C-TAG TPID */ + __IOM uint32_t STT : 16; /*!< [31..16] S-TAG TPID */ + } FWTTC0_b; + }; + + union + { + __IOM uint32_t FWTTC1; /*!< (@ 0x00000014) TAG TPID Configuration Register 1 */ + + struct + { + __IOM uint32_t RTT : 16; /*!< [15..0] R-TAG TPID */ + uint32_t : 16; + } FWTTC1_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t FWCEPTC; /*!< (@ 0x00000020) CPU Exceptional Path Target Configuration Register */ + + struct + { + __IOM uint32_t EPCSD : 7; /*!< [6..0] Exceptional Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t EPIPV : 3; /*!< [14..12] Exceptional Path Internal Priority Value */ + uint32_t : 1; + __IOM uint32_t EPCS : 2; /*!< [17..16] Exceptional Path CPU Select */ + uint32_t : 6; + __IOM uint32_t EPSL : 1; /*!< [24..24] Exceptional Path Security Level */ + uint32_t : 7; + } FWCEPTC_b; + }; + + union + { + __IOM uint32_t FWCEPRC0; /*!< (@ 0x00000024) CPU Exceptional Path Reason Configuration Register + * 0 */ + + struct + { + __IOM uint32_t EPHYEEF : 1; /*!< [0..0] Ethernet PHY Error Exceptional Forwarding */ + __IOM uint32_t EPCRCEEF : 1; /*!< [1..1] Ethernet PCH CRC Error Exceptional Forwarding */ + __IOM uint32_t ENIBEEF : 1; /*!< [2..2] Ethernet Nibble Error Exceptional Forwarding */ + __IOM uint32_t EFCSEEF : 1; /*!< [3..3] Ethernet FCS Error Exceptional Forwarding */ + __IOM uint32_t EFFMEEF : 1; /*!< [4..4] Ethernet Final Fragment Missing Error Exceptional Forwarding */ + __IOM uint32_t ECFSEEF : 1; /*!< [5..5] Ethernet C-Fragment SMD Error Exceptional Forwarding */ + __IOM uint32_t ECFFCEEF : 1; /*!< [6..6] Ethernet C-Fragment FRAG_COUNT Error Exceptional Forwarding */ + __IOM uint32_t ERFFEF : 1; /*!< [7..7] Ethernet RMAC Frame Filtered Exceptional Forwarding */ + __IOM uint32_t ERPOOEF : 1; /*!< [8..8] Ethernet Reception Partially Out of Operation Exceptional + * Forwarding */ + __IOM uint32_t EBOEEF : 1; /*!< [9..9] Ethernet Buffer Overflow Error Exceptional Forwarding */ + __IOM uint32_t EUEEF : 1; /*!< [10..10] Ethernet Undersize Error Exceptional Forwarding */ + __IOM uint32_t EOEEF : 1; /*!< [11..11] Ethernet Oversize Error Exceptional Forwarding */ + __IOM uint32_t ETFEF : 1; /*!< [12..12] Ethernet TAG Filtering Exceptional Forwarding */ + uint32_t : 3; + __IOM uint32_t GAREEEF : 1; /*!< [16..16] GWCA AXI RAM ECC Error Exceptional Forwarding */ + __IOM uint32_t GAXEEF : 1; /*!< [17..17] GWCA AXI Error Exceptional Forwarding */ + __IOM uint32_t GSEQEEF : 1; /*!< [18..18] GWCA Sequence Error Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t GTFEF : 1; /*!< [20..20] GWCA TAG Filtering Exceptional Forwarding */ + __IOM uint32_t GDNEEF : 1; /*!< [21..21] GWCA Descriptor Number Error Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t DDEEF : 1; /*!< [24..24] Direct Descriptor Error Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t DDFSFEF : 1; /*!< [26..26] Direct Descriptor Format Security Filtering Exceptional + * Forwarding */ + uint32_t : 5; + } FWCEPRC0_b; + }; + + union + { + __IOM uint32_t FWCEPRC1; /*!< (@ 0x00000028) CPU Exceptional Path Reason Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FMSDUFEF : 1; /*!< [0..0] MSDU Filtering Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t FMTRFEF : 1; /*!< [2..2] Meter Filtering Exceptional Forwarding */ + uint32_t : 5; + __IOM uint32_t FIFFEF : 1; /*!< [8..8] Individual FRER Filtering Exceptional Forwarding */ + __IOM uint32_t FSFFEF : 1; /*!< [9..9] Sequence FRER Filtering Exceptional Forwarding */ + uint32_t : 22; + } FWCEPRC1_b; + }; + + union + { + __IOM uint32_t FWCEPRC2; /*!< (@ 0x0000002C) CPU Exceptional Path Reason Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FLTHUFEF : 1; /*!< [0..0] Layer 3 Unknown Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDMACUFEF : 1; /*!< [3..3] Destination MAC Unknown Filtering Exceptional Forwarding */ + __IOM uint32_t FSMACUFEF : 1; /*!< [4..4] Source MAC Unknown Filtering Exceptional Forwarding */ + __IOM uint32_t FVLANUFEF : 1; /*!< [5..5] VLAN Unknown Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDDNTFEF : 1; /*!< [8..8] Direct Descriptor No Target Filtering Exceptional Forwarding */ + __IOM uint32_t FLTHNTFEF : 1; /*!< [9..9] Layer 3 No Target Filtering Exceptional Forwarding */ + uint32_t : 1; + __IOM uint32_t FLTWNTFEF : 1; /*!< [11..11] Layer 2 No Target Filtering Exceptional Forwarding */ + __IOM uint32_t FPBNTFEF : 1; /*!< [12..12] Port Based No Target Filtering Exceptional Forwarding */ + uint32_t : 3; + __IOM uint32_t FLTHSLFEF : 1; /*!< [16..16] Layer 3 Source Lock Filtering Exceptional Forwarding */ + uint32_t : 2; + __IOM uint32_t FDMACSLFEF : 1; /*!< [19..19] Destination MAC Source Lock Filtering Exceptional Forwarding */ + __IOM uint32_t FSMACSLFEF : 1; /*!< [20..20] Source MAC Source Lock Filtering Exceptional Forwarding */ + __IOM uint32_t FVLANSLFEF : 1; /*!< [21..21] VLAN Source Lock Filtering Exceptional Forwarding */ + uint32_t : 4; + __IOM uint32_t FWMFEF : 1; /*!< [26..26] Watermark Filtering Exceptional Forwarding */ + uint32_t : 5; + } FWCEPRC2_b; + }; + + union + { + __IOM uint32_t FWCLPTC; /*!< (@ 0x00000030) CPU Learning Path Target Configuration Register */ + + struct + { + __IOM uint32_t LPCSD : 7; /*!< [6..0] Learning Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t LPIPV : 3; /*!< [14..12] Learning Path Internal Priority Value */ + uint32_t : 1; + __IOM uint32_t LPCS : 2; /*!< [17..16] Learning Path CPU Select */ + uint32_t : 6; + __IOM uint32_t LPSL : 1; /*!< [24..24] Learning Path Security Level */ + uint32_t : 7; + } FWCLPTC_b; + }; + + union + { + __IOM uint32_t FWCLPRC; /*!< (@ 0x00000034) CPU Learning Path Reason Configuration Register */ + + struct + { + __IOM uint32_t USIDLF : 1; /*!< [0..0] Unknown Stream ID Learning Forwarding */ + uint32_t : 3; + __IOM uint32_t UDMACLF : 1; /*!< [4..4] Unknown Destination MAC Learning Forwarding */ + __IOM uint32_t USMACLF : 1; /*!< [5..5] Unknown Source MAC Learning Forwarding */ + __IOM uint32_t UPSMACLF : 1; /*!< [6..6] Unknown Port for Source MAC Learning Forwarding */ + __IOM uint32_t UVLANLF : 1; /*!< [7..7] Unknown VLAN Learning Forwarding */ + uint32_t : 24; + } FWCLPRC_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t FWCMPTC; /*!< (@ 0x00000040) CPU Mirroring Path Target Configuration Register */ + + struct + { + __IOM uint32_t CMPCSD : 7; /*!< [6..0] CPU Mirroring Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t CMPIPV : 3; /*!< [14..12] CPU Mirroring Path Internal Priority Value */ + __IOM uint32_t CMPIPU : 1; /*!< [15..15] CPU Mirroring Path Internal Priority Update */ + __IOM uint32_t CMPCS : 2; /*!< [17..16] CPU Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t CMPSL : 1; /*!< [24..24] CPU Mirroring Path Security Level */ + uint32_t : 7; + } FWCMPTC_b; + }; + + union + { + __IOM uint32_t FWEMPTC; /*!< (@ 0x00000044) Ethernet Mirroring Path Target Configuration + * Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t EMPIPV : 3; /*!< [14..12] Ethernet Mirroring Path Internal Priority Value */ + __IOM uint32_t EMPIPU : 1; /*!< [15..15] Ethernet Mirroring Path Internal Priority Update */ + __IOM uint32_t EMPPS : 2; /*!< [17..16] Ethernet Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t EMPSL : 1; /*!< [24..24] Ethernet Mirroring Path Security Level */ + uint32_t : 7; + } FWEMPTC_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t FWSDMPTC; /*!< (@ 0x00000050) Source-Destination Mirroring Path Target Configuration + * Register */ + + struct + { + __IOM uint32_t SDMPCSD : 7; /*!< [6..0] Source-Destination Mirroring Path CPU Sub Destination */ + uint32_t : 5; + __IOM uint32_t SDMPIPV : 3; /*!< [14..12] Source-Destination Mirroring Path Internal Priority + * Value */ + __IOM uint32_t SDMPIPU : 1; /*!< [15..15] Source-Destination Mirroring Path Internal Priority + * Update */ + __IOM uint32_t SDMPPS : 2; /*!< [17..16] Source-Destination Mirroring Path CPU Select */ + uint32_t : 6; + __IOM uint32_t SDMPSL : 1; /*!< [24..24] Source-Destination Mirroring Path Security Level */ + uint32_t : 7; + } FWSDMPTC_b; + }; + + union + { + __IOM uint32_t FWSDMPVC; /*!< (@ 0x00000054) Source-Destination Mirroring Path Vector Configuration + * Register */ + + struct + { + __IOM uint32_t SDMDV : 7; /*!< [6..0] Source-Destination Mirroring Destination Vector */ + uint32_t : 9; + __IOM uint32_t SDMSV : 7; /*!< [22..16] Source-Destination Mirroring Source Vector */ + uint32_t : 9; + } FWSDMPVC_b; + }; + __IM uint32_t RESERVED4[10]; + + union + { + __IOM uint32_t FWLBWMC0; /*!< (@ 0x00000080) Level Based Watermark Configuration Register + * 0 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC0_b; + }; + + union + { + __IOM uint32_t FWLBWMC1; /*!< (@ 0x00000084) Level Based Watermark Configuration Register + * 1 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC1_b; + }; + + union + { + __IOM uint32_t FWLBWMC2; /*!< (@ 0x00000088) Level Based Watermark Configuration Register + * 2 */ + + struct + { + __IOM uint32_t WMCLPR : 16; /*!< [15..0] Watermark Critical Level Priority Rejected */ + __IOM uint32_t WMFLPR : 16; /*!< [31..16] Watermark Flush Level Priority Rejected */ + } FWLBWMC2_b; + }; + __IM uint32_t RESERVED5[29]; + + union + { + __IOM uint32_t FWPC00; /*!< (@ 0x00000100) Port Configuration Register 00 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC00_b; + }; + + union + { + __IOM uint32_t FWPC10; /*!< (@ 0x00000104) Port Configuration Register 10 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC10_b; + }; + + union + { + __IOM uint32_t FWPC20; /*!< (@ 0x00000108) Port Configuration Register 20 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC20_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t FWPC01; /*!< (@ 0x00000110) Port Configuration Register 01 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC01_b; + }; + + union + { + __IOM uint32_t FWPC11; /*!< (@ 0x00000114) Port Configuration Register 11 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC11_b; + }; + + union + { + __IOM uint32_t FWPC21; /*!< (@ 0x00000118) Port Configuration Register 21 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC21_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t FWPC02; /*!< (@ 0x00000120) Port Configuration Register 02 */ + + struct + { + __IOM uint32_t LTHTA : 1; /*!< [0..0] L3 Table Active */ + __IOM uint32_t LTHRUS : 1; /*!< [1..1] L3 Reject Unknown Streams */ + __IOM uint32_t LTHRUSS : 1; /*!< [2..2] L3 Reject Unknown Secure Streams */ + __IOM uint32_t IP4UE : 1; /*!< [3..3] IPv4 UDP Enabled */ + __IOM uint32_t IP4TE : 1; /*!< [4..4] IPv4 TCP Enabled */ + __IOM uint32_t IP4OE : 1; /*!< [5..5] IPv4 Other Enabled */ + __IOM uint32_t IP6UE : 1; /*!< [6..6] IPv6 UDP Enabled */ + __IOM uint32_t IP6TE : 1; /*!< [7..7] IPv6 TCP Enabled */ + __IOM uint32_t IP6OE : 1; /*!< [8..8] IPv6 Other Enabled */ + __IOM uint32_t L2SE : 1; /*!< [9..9] L2 Stream Enable */ + uint32_t : 10; + __IOM uint32_t MACDSA : 1; /*!< [20..20] MAC Destination Search Active */ + __IOM uint32_t MACRUDA : 1; /*!< [21..21] MAC Reject Unknown Destination Addresses */ + __IOM uint32_t MACRUDSA : 1; /*!< [22..22] MAC Reject Unknown Destination Secure Addresses */ + __IOM uint32_t MACSSA : 1; /*!< [23..23] MAC Source Search Active */ + __IOM uint32_t MACRUSA : 1; /*!< [24..24] MAC Reject Unknown Source Addresses */ + __IOM uint32_t MACRUSSA : 1; /*!< [25..25] MAC Reject Unknown Source Secure Addresses */ + __IOM uint32_t MACHLA : 1; /*!< [26..26] MAC Hardware Learning Active */ + __IOM uint32_t MACHMA : 1; /*!< [27..27] MAC Hardware Migration Active */ + __IOM uint32_t VLANSA : 1; /*!< [28..28] VLAN Search Active */ + __IOM uint32_t VLANRU : 1; /*!< [29..29] VLAN Reject Unknown */ + __IOM uint32_t VLANRUS : 1; /*!< [30..30] VLAN Reject Unknown Secure */ + uint32_t : 1; + } FWPC02_b; + }; + + union + { + __IOM uint32_t FWPC12; /*!< (@ 0x00000124) Port Configuration Register 12 */ + + struct + { + __IOM uint32_t DDE : 1; /*!< [0..0] Direct Descriptor Enable */ + __IOM uint32_t DDSL : 1; /*!< [1..1] Direct Descriptor Security Level */ + uint32_t : 14; + __IOM uint32_t LTHFM : 7; /*!< [22..16] Layer 3 Forwarding Mask */ + uint32_t : 9; + } FWPC12_b; + }; + + union + { + __IOM uint32_t FWPC22; /*!< (@ 0x00000128) Port Configuration Register 22 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTWFM : 7; /*!< [22..16] Layer 2 Forwarding Mask */ + uint32_t : 9; + } FWPC22_b; + }; + __IM uint32_t RESERVED8[181]; + + union + { + __IOM uint32_t FWCTGC00; /*!< (@ 0x00000400) Cut-Through General Configuration Register 00 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC00_b; + }; + + union + { + __IOM uint32_t FWCTGC10; /*!< (@ 0x00000404) Cut-Through General Configuration Register 10 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC10_b; + }; + + union + { + __IOM uint32_t FWCTTC00; /*!< (@ 0x00000408) Cut-Through Target Configuration Register 00 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC00_b; + }; + + union + { + __IOM uint32_t FWCTTC10; /*!< (@ 0x0000040C) Cut-Through Target Configuration Register 10 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC10_b; + }; + + union + { + __IOM uint32_t FWCTTC200; /*!< (@ 0x00000410) Cut-Through Target Configuration Register 200 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC200_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t FWCTSC00; /*!< (@ 0x00000420) Cut-Through Separation Configuration Register + * 00 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC00_b; + }; + + union + { + __IOM uint32_t FWCTSC10; /*!< (@ 0x00000424) Cut-Through Separation Configuration Register + * 10 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC10_b; + }; + + union + { + __IOM uint32_t FWCTSC20; /*!< (@ 0x00000428) Cut-Through Separation Configuration Register + * 20 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC20_b; + }; + + union + { + __IOM uint32_t FWCTSC30; /*!< (@ 0x0000042C) Cut-Through Separation Configuration Register + * 30 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC30_b; + }; + + union + { + __IOM uint32_t FWCTSC40; /*!< (@ 0x00000430) Cut-Through Separation Configuration Register + * 40 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC40_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t FWCTGC01; /*!< (@ 0x00000440) Cut-Through General Configuration Register 01 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC01_b; + }; + + union + { + __IOM uint32_t FWCTGC11; /*!< (@ 0x00000444) Cut-Through General Configuration Register 11 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC11_b; + }; + + union + { + __IOM uint32_t FWCTTC01; /*!< (@ 0x00000448) Cut-Through Target Configuration Register 01 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC01_b; + }; + + union + { + __IOM uint32_t FWCTTC11; /*!< (@ 0x0000044C) Cut-Through Target Configuration Register 11 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC11_b; + }; + + union + { + __IOM uint32_t FWCTTC201; /*!< (@ 0x00000450) Cut-Through Target Configuration Register 201 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC201_b; + }; + __IM uint32_t RESERVED11[3]; + + union + { + __IOM uint32_t FWCTSC01; /*!< (@ 0x00000460) Cut-Through Separation Configuration Register + * 01 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC01_b; + }; + + union + { + __IOM uint32_t FWCTSC11; /*!< (@ 0x00000464) Cut-Through Separation Configuration Register + * 11 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC11_b; + }; + + union + { + __IOM uint32_t FWCTSC21; /*!< (@ 0x00000468) Cut-Through Separation Configuration Register + * 21 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC21_b; + }; + + union + { + __IOM uint32_t FWCTSC31; /*!< (@ 0x0000046C) Cut-Through Separation Configuration Register + * 31 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC31_b; + }; + + union + { + __IOM uint32_t FWCTSC41; /*!< (@ 0x00000470) Cut-Through Separation Configuration Register + * 41 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC41_b; + }; + __IM uint32_t RESERVED12[3]; + + union + { + __IOM uint32_t FWCTGC02; /*!< (@ 0x00000480) Cut-Through General Configuration Register 02 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC02_b; + }; + + union + { + __IOM uint32_t FWCTGC12; /*!< (@ 0x00000484) Cut-Through General Configuration Register 12 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC12_b; + }; + + union + { + __IOM uint32_t FWCTTC02; /*!< (@ 0x00000488) Cut-Through Target Configuration Register 02 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC02_b; + }; + + union + { + __IOM uint32_t FWCTTC12; /*!< (@ 0x0000048C) Cut-Through Target Configuration Register 12 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC12_b; + }; + + union + { + __IOM uint32_t FWCTTC202; /*!< (@ 0x00000490) Cut-Through Target Configuration Register 202 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC202_b; + }; + __IM uint32_t RESERVED13[3]; + + union + { + __IOM uint32_t FWCTSC02; /*!< (@ 0x000004A0) Cut-Through Separation Configuration Register + * 02 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC02_b; + }; + + union + { + __IOM uint32_t FWCTSC12; /*!< (@ 0x000004A4) Cut-Through Separation Configuration Register + * 12 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC12_b; + }; + + union + { + __IOM uint32_t FWCTSC22; /*!< (@ 0x000004A8) Cut-Through Separation Configuration Register + * 22 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC22_b; + }; + + union + { + __IOM uint32_t FWCTSC32; /*!< (@ 0x000004AC) Cut-Through Separation Configuration Register + * 32 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC32_b; + }; + + union + { + __IOM uint32_t FWCTSC42; /*!< (@ 0x000004B0) Cut-Through Separation Configuration Register + * 42 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC42_b; + }; + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t FWCTGC03; /*!< (@ 0x000004C0) Cut-Through General Configuration Register 03 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC03_b; + }; + + union + { + __IOM uint32_t FWCTGC13; /*!< (@ 0x000004C4) Cut-Through General Configuration Register 13 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC13_b; + }; + + union + { + __IOM uint32_t FWCTTC03; /*!< (@ 0x000004C8) Cut-Through Target Configuration Register 03 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC03_b; + }; + + union + { + __IOM uint32_t FWCTTC13; /*!< (@ 0x000004CC) Cut-Through Target Configuration Register 13 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC13_b; + }; + + union + { + __IOM uint32_t FWCTTC203; /*!< (@ 0x000004D0) Cut-Through Target Configuration Register 203 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC203_b; + }; + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint32_t FWCTSC03; /*!< (@ 0x000004E0) Cut-Through Separation Configuration Register + * 03 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC03_b; + }; + + union + { + __IOM uint32_t FWCTSC13; /*!< (@ 0x000004E4) Cut-Through Separation Configuration Register + * 13 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC13_b; + }; + + union + { + __IOM uint32_t FWCTSC23; /*!< (@ 0x000004E8) Cut-Through Separation Configuration Register + * 23 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC23_b; + }; + + union + { + __IOM uint32_t FWCTSC33; /*!< (@ 0x000004EC) Cut-Through Separation Configuration Register + * 33 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC33_b; + }; + + union + { + __IOM uint32_t FWCTSC43; /*!< (@ 0x000004F0) Cut-Through Separation Configuration Register + * 43 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC43_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t FWCTGC04; /*!< (@ 0x00000500) Cut-Through General Configuration Register 04 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC04_b; + }; + + union + { + __IOM uint32_t FWCTGC14; /*!< (@ 0x00000504) Cut-Through General Configuration Register 14 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC14_b; + }; + + union + { + __IOM uint32_t FWCTTC04; /*!< (@ 0x00000508) Cut-Through Target Configuration Register 04 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC04_b; + }; + + union + { + __IOM uint32_t FWCTTC14; /*!< (@ 0x0000050C) Cut-Through Target Configuration Register 14 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC14_b; + }; + + union + { + __IOM uint32_t FWCTTC204; /*!< (@ 0x00000510) Cut-Through Target Configuration Register 204 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC204_b; + }; + __IM uint32_t RESERVED17[3]; + + union + { + __IOM uint32_t FWCTSC04; /*!< (@ 0x00000520) Cut-Through Separation Configuration Register + * 04 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC04_b; + }; + + union + { + __IOM uint32_t FWCTSC14; /*!< (@ 0x00000524) Cut-Through Separation Configuration Register + * 14 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC14_b; + }; + + union + { + __IOM uint32_t FWCTSC24; /*!< (@ 0x00000528) Cut-Through Separation Configuration Register + * 24 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC24_b; + }; + + union + { + __IOM uint32_t FWCTSC34; /*!< (@ 0x0000052C) Cut-Through Separation Configuration Register + * 34 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC34_b; + }; + + union + { + __IOM uint32_t FWCTSC44; /*!< (@ 0x00000530) Cut-Through Separation Configuration Register + * 44 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC44_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IOM uint32_t FWCTGC05; /*!< (@ 0x00000540) Cut-Through General Configuration Register 05 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC05_b; + }; + + union + { + __IOM uint32_t FWCTGC15; /*!< (@ 0x00000544) Cut-Through General Configuration Register 15 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC15_b; + }; + + union + { + __IOM uint32_t FWCTTC05; /*!< (@ 0x00000548) Cut-Through Target Configuration Register 05 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC05_b; + }; + + union + { + __IOM uint32_t FWCTTC15; /*!< (@ 0x0000054C) Cut-Through Target Configuration Register 15 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC15_b; + }; + + union + { + __IOM uint32_t FWCTTC205; /*!< (@ 0x00000550) Cut-Through Target Configuration Register 205 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC205_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IOM uint32_t FWCTSC05; /*!< (@ 0x00000560) Cut-Through Separation Configuration Register + * 05 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC05_b; + }; + + union + { + __IOM uint32_t FWCTSC15; /*!< (@ 0x00000564) Cut-Through Separation Configuration Register + * 15 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC15_b; + }; + + union + { + __IOM uint32_t FWCTSC25; /*!< (@ 0x00000568) Cut-Through Separation Configuration Register + * 25 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC25_b; + }; + + union + { + __IOM uint32_t FWCTSC35; /*!< (@ 0x0000056C) Cut-Through Separation Configuration Register + * 35 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC35_b; + }; + + union + { + __IOM uint32_t FWCTSC45; /*!< (@ 0x00000570) Cut-Through Separation Configuration Register + * 45 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC45_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint32_t FWCTGC06; /*!< (@ 0x00000580) Cut-Through General Configuration Register 06 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC06_b; + }; + + union + { + __IOM uint32_t FWCTGC16; /*!< (@ 0x00000584) Cut-Through General Configuration Register 16 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC16_b; + }; + + union + { + __IOM uint32_t FWCTTC06; /*!< (@ 0x00000588) Cut-Through Target Configuration Register 06 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC06_b; + }; + + union + { + __IOM uint32_t FWCTTC16; /*!< (@ 0x0000058C) Cut-Through Target Configuration Register 16 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC16_b; + }; + + union + { + __IOM uint32_t FWCTTC206; /*!< (@ 0x00000590) Cut-Through Target Configuration Register 206 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC206_b; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t FWCTSC06; /*!< (@ 0x000005A0) Cut-Through Separation Configuration Register + * 06 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC06_b; + }; + + union + { + __IOM uint32_t FWCTSC16; /*!< (@ 0x000005A4) Cut-Through Separation Configuration Register + * 16 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC16_b; + }; + + union + { + __IOM uint32_t FWCTSC26; /*!< (@ 0x000005A8) Cut-Through Separation Configuration Register + * 26 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC26_b; + }; + + union + { + __IOM uint32_t FWCTSC36; /*!< (@ 0x000005AC) Cut-Through Separation Configuration Register + * 36 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC36_b; + }; + + union + { + __IOM uint32_t FWCTSC46; /*!< (@ 0x000005B0) Cut-Through Separation Configuration Register + * 46 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC46_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint32_t FWCTGC07; /*!< (@ 0x000005C0) Cut-Through General Configuration Register 07 */ + + struct + { + __IOM uint32_t CTMDE : 1; /*!< [0..0] Cut-Through MAC Destination Enable */ + __IOM uint32_t CTMSE : 1; /*!< [1..1] Cut-Through MAC Source Enable */ + __IOM uint32_t CTCVE : 1; /*!< [2..2] Cut-Through C-TAG VLAN Enable */ + __IOM uint32_t CTCPE : 1; /*!< [3..3] Cut-Through C-TAG PCP Enable */ + __IOM uint32_t CTCDE : 1; /*!< [4..4] Cut-Through C-TAG DEI Enable */ + __IOM uint32_t CTSVE : 1; /*!< [5..5] Cut-Through S-TAG VLAN Enable */ + __IOM uint32_t CTSPE : 1; /*!< [6..6] Cut-Through S-TAG PCP Enable */ + __IOM uint32_t CTSDE : 1; /*!< [7..7] Cut-Through S-TAG DEI Enable */ + __IOM uint32_t CTETE : 1; /*!< [8..8] Cut-Through Ethernet Type Enable */ + uint32_t : 2; + __IOM uint32_t CTFI : 1; /*!< [11..11] Cut-Through FCS In */ + __IOM uint32_t CTVCTRL : 2; /*!< [13..12] Cut-Through VLAN Control [GWCA] [ETHA] */ + __IOM uint32_t CTRTGI : 1; /*!< [14..14] Cut-Through R-TAG In [GWCA] [ETHA] */ + uint32_t : 17; + } FWCTGC07_b; + }; + + union + { + __IOM uint32_t FWCTGC17; /*!< (@ 0x000005C4) Cut-Through General Configuration Register 17 */ + + struct + { + __IOM uint32_t CTMT : 26; /*!< [25..0] Cut-Through Maximum time */ + uint32_t : 6; + } FWCTGC17_b; + }; + + union + { + __IOM uint32_t FWCTTC07; /*!< (@ 0x000005C8) Cut-Through Target Configuration Register 07 */ + + struct + { + __IOM uint32_t CTDV : 7; /*!< [6..0] Cut-through Destination Vector */ + uint32_t : 9; + __IOM uint32_t CTDFM : 4; /*!< [19..16] Cut-through Destination Forwarding Mode */ + uint32_t : 12; + } FWCTTC07_b; + }; + + union + { + __IOM uint32_t FWCTTC17; /*!< (@ 0x000005CC) Cut-Through Target Configuration Register 17 */ + + struct + { + uint32_t : 12; + __IOM uint32_t CTIPV : 3; /*!< [14..12] Cut-through Internal Priority Value */ + __IOM uint32_t CTIPU : 1; /*!< [15..15] Cut-through Internal Priority Update */ + __IOM uint32_t CTCME : 1; /*!< [16..16] Cut-through CPU Mirroring Enable */ + __IOM uint32_t CTEME : 1; /*!< [17..17] Cut-through Ethernet Mirroring Enable */ + uint32_t : 14; + } FWCTTC17_b; + }; + + union + { + __IOM uint32_t FWCTTC207; /*!< (@ 0x000005D0) Cut-Through Target Configuration Register 207 */ + + struct + { + __IOM uint32_t CTCSD : 7; /*!< [6..0] Cut-Through CPU Sub Destination */ + uint32_t : 25; + } FWCTTC207_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t FWCTSC07; /*!< (@ 0x000005E0) Cut-Through Separation Configuration Register + * 07 */ + + struct + { + __IOM uint32_t CTDMAU : 32; /*!< [31..0] Cut-Through Destination MAC Address Upper Part */ + } FWCTSC07_b; + }; + + union + { + __IOM uint32_t FWCTSC17; /*!< (@ 0x000005E4) Cut-Through Separation Configuration Register + * 17 */ + + struct + { + __IOM uint32_t CTSMAU : 16; /*!< [15..0] Cut-Through Source MAC Address Upper Part */ + __IOM uint32_t CTDMAL : 16; /*!< [31..16] Cut-Through Destination MAC Address Lower Part */ + } FWCTSC17_b; + }; + + union + { + __IOM uint32_t FWCTSC27; /*!< (@ 0x000005E8) Cut-Through Separation Configuration Register + * 27 */ + + struct + { + __IOM uint32_t CTSMAL : 32; /*!< [31..0] Cut-Through Source MAC Address Lower Part */ + } FWCTSC27_b; + }; + + union + { + __IOM uint32_t FWCTSC37; /*!< (@ 0x000005EC) Cut-Through Separation Configuration Register + * 37 */ + + struct + { + __IOM uint32_t CTCV : 12; /*!< [11..0] Cut-Through C-TAG VLAN */ + __IOM uint32_t CTCP : 3; /*!< [14..12] Cut-Through C-TAG PCP */ + __IOM uint32_t CTCD : 1; /*!< [15..15] Cut-Through C-TAG DEI */ + __IOM uint32_t CTSV : 12; /*!< [27..16] Cut-Through S-TAG VLAN */ + __IOM uint32_t CTSP : 3; /*!< [30..28] Cut-Through S-TAG PCP */ + __IOM uint32_t CTSD : 1; /*!< [31..31] Cut-Through S-TAG DEI */ + } FWCTSC37_b; + }; + + union + { + __IOM uint32_t FWCTSC47; /*!< (@ 0x000005F0) Cut-Through Separation Configuration Register + * 47 */ + + struct + { + __IOM uint32_t CTET : 16; /*!< [15..0] Cut-Through Ethernet Type */ + __IOM uint32_t CTSPN : 2; /*!< [17..16] Cut-Through Source Port Number */ + uint32_t : 14; + } FWCTSC47_b; + }; + __IM uint32_t RESERVED24[643]; + + union + { + __IOM uint32_t FWTWBFC0; /*!< (@ 0x00001000) Two-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC0_b; + }; + + union + { + __IOM uint32_t FWTWBFVC0; /*!< (@ 0x00001004) Two-Byte Filter Value Configuration Register + * 0 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC0_b; + }; + __IM uint32_t RESERVED25[2]; + + union + { + __IOM uint32_t FWTWBFC1; /*!< (@ 0x00001010) Two-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC1_b; + }; + + union + { + __IOM uint32_t FWTWBFVC1; /*!< (@ 0x00001014) Two-Byte Filter Value Configuration Register + * 1 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC1_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint32_t FWTWBFC2; /*!< (@ 0x00001020) Two-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC2_b; + }; + + union + { + __IOM uint32_t FWTWBFVC2; /*!< (@ 0x00001024) Two-Byte Filter Value Configuration Register + * 2 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC2_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IOM uint32_t FWTWBFC3; /*!< (@ 0x00001030) Two-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC3_b; + }; + + union + { + __IOM uint32_t FWTWBFVC3; /*!< (@ 0x00001034) Two-Byte Filter Value Configuration Register + * 3 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC3_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t FWTWBFC4; /*!< (@ 0x00001040) Two-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC4_b; + }; + + union + { + __IOM uint32_t FWTWBFVC4; /*!< (@ 0x00001044) Two-Byte Filter Value Configuration Register + * 4 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC4_b; + }; + __IM uint32_t RESERVED29[2]; + + union + { + __IOM uint32_t FWTWBFC5; /*!< (@ 0x00001050) Two-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC5_b; + }; + + union + { + __IOM uint32_t FWTWBFVC5; /*!< (@ 0x00001054) Two-Byte Filter Value Configuration Register + * 5 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC5_b; + }; + __IM uint32_t RESERVED30[2]; + + union + { + __IOM uint32_t FWTWBFC6; /*!< (@ 0x00001060) Two-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC6_b; + }; + + union + { + __IOM uint32_t FWTWBFVC6; /*!< (@ 0x00001064) Two-Byte Filter Value Configuration Register + * 6 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC6_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IOM uint32_t FWTWBFC7; /*!< (@ 0x00001070) Two-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC7_b; + }; + + union + { + __IOM uint32_t FWTWBFVC7; /*!< (@ 0x00001074) Two-Byte Filter Value Configuration Register + * 7 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC7_b; + }; + __IM uint32_t RESERVED32[2]; + + union + { + __IOM uint32_t FWTWBFC8; /*!< (@ 0x00001080) Two-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC8_b; + }; + + union + { + __IOM uint32_t FWTWBFVC8; /*!< (@ 0x00001084) Two-Byte Filter Value Configuration Register + * 8 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC8_b; + }; + __IM uint32_t RESERVED33[2]; + + union + { + __IOM uint32_t FWTWBFC9; /*!< (@ 0x00001090) Two-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC9_b; + }; + + union + { + __IOM uint32_t FWTWBFVC9; /*!< (@ 0x00001094) Two-Byte Filter Value Configuration Register + * 9 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC9_b; + }; + __IM uint32_t RESERVED34[2]; + + union + { + __IOM uint32_t FWTWBFC10; /*!< (@ 0x000010A0) Two-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC10_b; + }; + + union + { + __IOM uint32_t FWTWBFVC10; /*!< (@ 0x000010A4) Two-Byte Filter Value Configuration Register + * 10 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC10_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IOM uint32_t FWTWBFC11; /*!< (@ 0x000010B0) Two-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC11_b; + }; + + union + { + __IOM uint32_t FWTWBFVC11; /*!< (@ 0x000010B4) Two-Byte Filter Value Configuration Register + * 11 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC11_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t FWTWBFC12; /*!< (@ 0x000010C0) Two-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC12_b; + }; + + union + { + __IOM uint32_t FWTWBFVC12; /*!< (@ 0x000010C4) Two-Byte Filter Value Configuration Register + * 12 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC12_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IOM uint32_t FWTWBFC13; /*!< (@ 0x000010D0) Two-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC13_b; + }; + + union + { + __IOM uint32_t FWTWBFVC13; /*!< (@ 0x000010D4) Two-Byte Filter Value Configuration Register + * 13 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC13_b; + }; + __IM uint32_t RESERVED38[2]; + + union + { + __IOM uint32_t FWTWBFC14; /*!< (@ 0x000010E0) Two-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC14_b; + }; + + union + { + __IOM uint32_t FWTWBFVC14; /*!< (@ 0x000010E4) Two-Byte Filter Value Configuration Register + * 14 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC14_b; + }; + __IM uint32_t RESERVED39[2]; + + union + { + __IOM uint32_t FWTWBFC15; /*!< (@ 0x000010F0) Two-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t TWBFUM : 2; /*!< [1..0] Two-Byte Filter Unit Mode */ + uint32_t : 6; + __IOM uint32_t TWBFM : 1; /*!< [8..8] Two-Byte Filtering Mode */ + uint32_t : 7; + __IOM uint32_t TWBFOV : 8; /*!< [23..16] Two-Byte Filter Offset Value */ + uint32_t : 8; + } FWTWBFC15_b; + }; + + union + { + __IOM uint32_t FWTWBFVC15; /*!< (@ 0x000010F4) Two-Byte Filter Value Configuration Register + * 15 */ + + struct + { + __IOM uint32_t TWBFV0 : 16; /*!< [15..0] Two-Byte Filter Value 0 */ + __IOM uint32_t TWBFV1 : 16; /*!< [31..16] Two-Byte Filter Value 1 */ + } FWTWBFVC15_b; + }; + __IM uint32_t RESERVED40[194]; + + union + { + __IOM uint32_t FWTHBFC0; /*!< (@ 0x00001400) Three-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC0_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C0; /*!< (@ 0x00001404) Three-Byte Filter Value 0 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C0_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C0; /*!< (@ 0x00001408) Three-Byte Filter Value 1 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C0_b; + }; + __IM uint32_t RESERVED41; + + union + { + __IOM uint32_t FWTHBFC1; /*!< (@ 0x00001410) Three-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC1_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C1; /*!< (@ 0x00001414) Three-Byte Filter Value 0 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C1_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C1; /*!< (@ 0x00001418) Three-Byte Filter Value 1 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C1_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t FWTHBFC2; /*!< (@ 0x00001420) Three-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC2_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C2; /*!< (@ 0x00001424) Three-Byte Filter Value 0 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C2_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C2; /*!< (@ 0x00001428) Three-Byte Filter Value 1 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C2_b; + }; + __IM uint32_t RESERVED43; + + union + { + __IOM uint32_t FWTHBFC3; /*!< (@ 0x00001430) Three-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC3_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C3; /*!< (@ 0x00001434) Three-Byte Filter Value 0 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C3_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C3; /*!< (@ 0x00001438) Three-Byte Filter Value 1 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C3_b; + }; + __IM uint32_t RESERVED44; + + union + { + __IOM uint32_t FWTHBFC4; /*!< (@ 0x00001440) Three-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC4_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C4; /*!< (@ 0x00001444) Three-Byte Filter Value 0 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C4_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C4; /*!< (@ 0x00001448) Three-Byte Filter Value 1 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C4_b; + }; + __IM uint32_t RESERVED45; + + union + { + __IOM uint32_t FWTHBFC5; /*!< (@ 0x00001450) Three-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC5_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C5; /*!< (@ 0x00001454) Three-Byte Filter Value 0 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C5_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C5; /*!< (@ 0x00001458) Three-Byte Filter Value 1 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C5_b; + }; + __IM uint32_t RESERVED46; + + union + { + __IOM uint32_t FWTHBFC6; /*!< (@ 0x00001460) Three-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC6_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C6; /*!< (@ 0x00001464) Three-Byte Filter Value 0 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C6_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C6; /*!< (@ 0x00001468) Three-Byte Filter Value 1 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C6_b; + }; + __IM uint32_t RESERVED47; + + union + { + __IOM uint32_t FWTHBFC7; /*!< (@ 0x00001470) Three-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC7_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C7; /*!< (@ 0x00001474) Three-Byte Filter Value 0 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C7_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C7; /*!< (@ 0x00001478) Three-Byte Filter Value 1 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C7_b; + }; + __IM uint32_t RESERVED48; + + union + { + __IOM uint32_t FWTHBFC8; /*!< (@ 0x00001480) Three-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC8_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C8; /*!< (@ 0x00001484) Three-Byte Filter Value 0 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C8_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C8; /*!< (@ 0x00001488) Three-Byte Filter Value 1 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C8_b; + }; + __IM uint32_t RESERVED49; + + union + { + __IOM uint32_t FWTHBFC9; /*!< (@ 0x00001490) Three-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC9_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C9; /*!< (@ 0x00001494) Three-Byte Filter Value 0 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C9_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C9; /*!< (@ 0x00001498) Three-Byte Filter Value 1 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C9_b; + }; + __IM uint32_t RESERVED50; + + union + { + __IOM uint32_t FWTHBFC10; /*!< (@ 0x000014A0) Three-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC10_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C10; /*!< (@ 0x000014A4) Three-Byte Filter Value 0 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C10_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C10; /*!< (@ 0x000014A8) Three-Byte Filter Value 1 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C10_b; + }; + __IM uint32_t RESERVED51; + + union + { + __IOM uint32_t FWTHBFC11; /*!< (@ 0x000014B0) Three-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC11_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C11; /*!< (@ 0x000014B4) Three-Byte Filter Value 0 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C11_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C11; /*!< (@ 0x000014B8) Three-Byte Filter Value 1 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C11_b; + }; + __IM uint32_t RESERVED52; + + union + { + __IOM uint32_t FWTHBFC12; /*!< (@ 0x000014C0) Three-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC12_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C12; /*!< (@ 0x000014C4) Three-Byte Filter Value 0 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C12_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C12; /*!< (@ 0x000014C8) Three-Byte Filter Value 1 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C12_b; + }; + __IM uint32_t RESERVED53; + + union + { + __IOM uint32_t FWTHBFC13; /*!< (@ 0x000014D0) Three-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC13_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C13; /*!< (@ 0x000014D4) Three-Byte Filter Value 0 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C13_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C13; /*!< (@ 0x000014D8) Three-Byte Filter Value 1 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C13_b; + }; + __IM uint32_t RESERVED54; + + union + { + __IOM uint32_t FWTHBFC14; /*!< (@ 0x000014E0) Three-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC14_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C14; /*!< (@ 0x000014E4) Three-Byte Filter Value 0 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C14_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C14; /*!< (@ 0x000014E8) Three-Byte Filter Value 1 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C14_b; + }; + __IM uint32_t RESERVED55; + + union + { + __IOM uint32_t FWTHBFC15; /*!< (@ 0x000014F0) Three-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t THBFUM : 2; /*!< [1..0] Three-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t THBFOV : 8; /*!< [23..16] Three-Byte Filter Offset Value */ + uint32_t : 8; + } FWTHBFC15_b; + }; + + union + { + __IOM uint32_t FWTHBFV0C15; /*!< (@ 0x000014F4) Three-Byte Filter Value 0 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t THBFV0 : 24; /*!< [23..0] Three-Byte Filter Value 0 */ + uint32_t : 8; + } FWTHBFV0C15_b; + }; + + union + { + __IOM uint32_t FWTHBFV1C15; /*!< (@ 0x000014F8) Three-Byte Filter Value 1 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t THBFV1 : 24; /*!< [23..0] Three-Byte Filter Value 1 */ + uint32_t : 8; + } FWTHBFV1C15_b; + }; + __IM uint32_t RESERVED56[193]; + + union + { + __IOM uint32_t FWFOBFC0; /*!< (@ 0x00001800) Four-Byte Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC0_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C0; /*!< (@ 0x00001804) Four-Byte Filter Value 0 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C0_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C0; /*!< (@ 0x00001808) Four-Byte Filter Value 1 Configuration Register + * 0 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C0_b; + }; + __IM uint32_t RESERVED57; + + union + { + __IOM uint32_t FWFOBFC1; /*!< (@ 0x00001810) Four-Byte Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC1_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C1; /*!< (@ 0x00001814) Four-Byte Filter Value 0 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C1_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C1; /*!< (@ 0x00001818) Four-Byte Filter Value 1 Configuration Register + * 1 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C1_b; + }; + __IM uint32_t RESERVED58; + + union + { + __IOM uint32_t FWFOBFC2; /*!< (@ 0x00001820) Four-Byte Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC2_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C2; /*!< (@ 0x00001824) Four-Byte Filter Value 0 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C2_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C2; /*!< (@ 0x00001828) Four-Byte Filter Value 1 Configuration Register + * 2 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C2_b; + }; + __IM uint32_t RESERVED59; + + union + { + __IOM uint32_t FWFOBFC3; /*!< (@ 0x00001830) Four-Byte Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC3_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C3; /*!< (@ 0x00001834) Four-Byte Filter Value 0 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C3_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C3; /*!< (@ 0x00001838) Four-Byte Filter Value 1 Configuration Register + * 3 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C3_b; + }; + __IM uint32_t RESERVED60; + + union + { + __IOM uint32_t FWFOBFC4; /*!< (@ 0x00001840) Four-Byte Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC4_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C4; /*!< (@ 0x00001844) Four-Byte Filter Value 0 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C4_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C4; /*!< (@ 0x00001848) Four-Byte Filter Value 1 Configuration Register + * 4 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C4_b; + }; + __IM uint32_t RESERVED61; + + union + { + __IOM uint32_t FWFOBFC5; /*!< (@ 0x00001850) Four-Byte Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC5_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C5; /*!< (@ 0x00001854) Four-Byte Filter Value 0 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C5_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C5; /*!< (@ 0x00001858) Four-Byte Filter Value 1 Configuration Register + * 5 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C5_b; + }; + __IM uint32_t RESERVED62; + + union + { + __IOM uint32_t FWFOBFC6; /*!< (@ 0x00001860) Four-Byte Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC6_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C6; /*!< (@ 0x00001864) Four-Byte Filter Value 0 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C6_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C6; /*!< (@ 0x00001868) Four-Byte Filter Value 1 Configuration Register + * 6 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C6_b; + }; + __IM uint32_t RESERVED63; + + union + { + __IOM uint32_t FWFOBFC7; /*!< (@ 0x00001870) Four-Byte Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC7_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C7; /*!< (@ 0x00001874) Four-Byte Filter Value 0 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C7_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C7; /*!< (@ 0x00001878) Four-Byte Filter Value 1 Configuration Register + * 7 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C7_b; + }; + __IM uint32_t RESERVED64; + + union + { + __IOM uint32_t FWFOBFC8; /*!< (@ 0x00001880) Four-Byte Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC8_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C8; /*!< (@ 0x00001884) Four-Byte Filter Value 0 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C8_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C8; /*!< (@ 0x00001888) Four-Byte Filter Value 1 Configuration Register + * 8 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C8_b; + }; + __IM uint32_t RESERVED65; + + union + { + __IOM uint32_t FWFOBFC9; /*!< (@ 0x00001890) Four-Byte Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC9_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C9; /*!< (@ 0x00001894) Four-Byte Filter Value 0 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C9_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C9; /*!< (@ 0x00001898) Four-Byte Filter Value 1 Configuration Register + * 9 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C9_b; + }; + __IM uint32_t RESERVED66; + + union + { + __IOM uint32_t FWFOBFC10; /*!< (@ 0x000018A0) Four-Byte Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC10_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C10; /*!< (@ 0x000018A4) Four-Byte Filter Value 0 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C10_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C10; /*!< (@ 0x000018A8) Four-Byte Filter Value 1 Configuration Register + * 10 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C10_b; + }; + __IM uint32_t RESERVED67; + + union + { + __IOM uint32_t FWFOBFC11; /*!< (@ 0x000018B0) Four-Byte Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC11_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C11; /*!< (@ 0x000018B4) Four-Byte Filter Value 0 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C11_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C11; /*!< (@ 0x000018B8) Four-Byte Filter Value 1 Configuration Register + * 11 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C11_b; + }; + __IM uint32_t RESERVED68; + + union + { + __IOM uint32_t FWFOBFC12; /*!< (@ 0x000018C0) Four-Byte Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC12_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C12; /*!< (@ 0x000018C4) Four-Byte Filter Value 0 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C12_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C12; /*!< (@ 0x000018C8) Four-Byte Filter Value 1 Configuration Register + * 12 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C12_b; + }; + __IM uint32_t RESERVED69; + + union + { + __IOM uint32_t FWFOBFC13; /*!< (@ 0x000018D0) Four-Byte Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC13_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C13; /*!< (@ 0x000018D4) Four-Byte Filter Value 0 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C13_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C13; /*!< (@ 0x000018D8) Four-Byte Filter Value 1 Configuration Register + * 13 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C13_b; + }; + __IM uint32_t RESERVED70; + + union + { + __IOM uint32_t FWFOBFC14; /*!< (@ 0x000018E0) Four-Byte Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC14_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C14; /*!< (@ 0x000018E4) Four-Byte Filter Value 0 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C14_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C14; /*!< (@ 0x000018E8) Four-Byte Filter Value 1 Configuration Register + * 14 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C14_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t FWFOBFC15; /*!< (@ 0x000018F0) Four-Byte Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t FOBFUM : 2; /*!< [1..0] Four-Byte Filter Unit Mode */ + uint32_t : 14; + __IOM uint32_t FOBFOV : 8; /*!< [23..16] Four-Byte Filter Offset Value */ + uint32_t : 8; + } FWFOBFC15_b; + }; + + union + { + __IOM uint32_t FWFOBFV0C15; /*!< (@ 0x000018F4) Four-Byte Filter Value 0 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t FOBFV0 : 32; /*!< [31..0] Four-Byte Filter Value 0 */ + } FWFOBFV0C15_b; + }; + + union + { + __IOM uint32_t FWFOBFV1C15; /*!< (@ 0x000018F8) Four-Byte Filter Value 1 Configuration Register + * 15 */ + + struct + { + __IOM uint32_t FOBFV1 : 32; /*!< [31..0] Four-Byte Filter Value 1 */ + } FWFOBFV1C15_b; + }; + __IM uint32_t RESERVED72[193]; + + union + { + __IOM uint32_t FWRFC0; /*!< (@ 0x00001C00) Range Filter Configuration Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RFM : 1; /*!< [8..8] Range Filtering Mode */ + uint32_t : 7; + __IOM uint32_t RFOV : 8; /*!< [23..16] Range Filter Offset Value */ + uint32_t : 8; + } FWRFC0_b; + }; + + union + { + __IOM uint32_t FWRFVC0; /*!< (@ 0x00001C04) Range Filter Value Configuration Register 0 */ + + struct + { + __IOM uint32_t RFSV0 : 8; /*!< [7..0] Range Filter Start Value 0 */ + __IOM uint32_t RFSV1 : 8; /*!< [15..8] Range Filter Start Value 1 */ + __IOM uint32_t RFRV : 4; /*!< [19..16] Range Filter Range Value */ + uint32_t : 12; + } FWRFVC0_b; + }; + __IM uint32_t RESERVED73[2]; + + union + { + __IOM uint32_t FWRFC1; /*!< (@ 0x00001C10) Range Filter Configuration Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RFM : 1; /*!< [8..8] Range Filtering Mode */ + uint32_t : 7; + __IOM uint32_t RFOV : 8; /*!< [23..16] Range Filter Offset Value */ + uint32_t : 8; + } FWRFC1_b; + }; + + union + { + __IOM uint32_t FWRFVC1; /*!< (@ 0x00001C14) Range Filter Value Configuration Register 1 */ + + struct + { + __IOM uint32_t RFSV0 : 8; /*!< [7..0] Range Filter Start Value 0 */ + __IOM uint32_t RFSV1 : 8; /*!< [15..8] Range Filter Start Value 1 */ + __IOM uint32_t RFRV : 4; /*!< [19..16] Range Filter Range Value */ + uint32_t : 12; + } FWRFVC1_b; + }; + __IM uint32_t RESERVED74[250]; + + union + { + __IOM uint32_t FWCFC0; /*!< (@ 0x00002000) Cascade Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC0_b; + }; + + union + { + __IOM uint32_t FWCFMC00; /*!< (@ 0x00002004) Cascade Filter Mapping Configuration Register + * 00 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC00_b; + }; + + union + { + __IOM uint32_t FWCFMC01; /*!< (@ 0x00002008) Cascade Filter Mapping Configuration Register + * 01 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC01_b; + }; + + union + { + __IOM uint32_t FWCFMC02; /*!< (@ 0x0000200C) Cascade Filter Mapping Configuration Register + * 02 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC02_b; + }; + + union + { + __IOM uint32_t FWCFMC03; /*!< (@ 0x00002010) Cascade Filter Mapping Configuration Register + * 03 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC03_b; + }; + + union + { + __IOM uint32_t FWCFMC04; /*!< (@ 0x00002014) Cascade Filter Mapping Configuration Register + * 04 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC04_b; + }; + + union + { + __IOM uint32_t FWCFMC05; /*!< (@ 0x00002018) Cascade Filter Mapping Configuration Register + * 05 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC05_b; + }; + + union + { + __IOM uint32_t FWCFMC06; /*!< (@ 0x0000201C) Cascade Filter Mapping Configuration Register + * 06 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC06_b; + }; + __IM uint32_t RESERVED75[8]; + + union + { + __IOM uint32_t FWCFC1; /*!< (@ 0x00002040) Cascade Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC1_b; + }; + + union + { + __IOM uint32_t FWCFMC10; /*!< (@ 0x00002044) Cascade Filter Mapping Configuration Register + * 10 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC10_b; + }; + + union + { + __IOM uint32_t FWCFMC11; /*!< (@ 0x00002048) Cascade Filter Mapping Configuration Register + * 11 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC11_b; + }; + + union + { + __IOM uint32_t FWCFMC12; /*!< (@ 0x0000204C) Cascade Filter Mapping Configuration Register + * 12 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC12_b; + }; + + union + { + __IOM uint32_t FWCFMC13; /*!< (@ 0x00002050) Cascade Filter Mapping Configuration Register + * 13 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC13_b; + }; + + union + { + __IOM uint32_t FWCFMC14; /*!< (@ 0x00002054) Cascade Filter Mapping Configuration Register + * 14 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC14_b; + }; + + union + { + __IOM uint32_t FWCFMC15; /*!< (@ 0x00002058) Cascade Filter Mapping Configuration Register + * 15 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC15_b; + }; + + union + { + __IOM uint32_t FWCFMC16; /*!< (@ 0x0000205C) Cascade Filter Mapping Configuration Register + * 16 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC16_b; + }; + __IM uint32_t RESERVED76[8]; + + union + { + __IOM uint32_t FWCFC2; /*!< (@ 0x00002080) Cascade Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC2_b; + }; + + union + { + __IOM uint32_t FWCFMC20; /*!< (@ 0x00002084) Cascade Filter Mapping Configuration Register + * 20 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC20_b; + }; + + union + { + __IOM uint32_t FWCFMC21; /*!< (@ 0x00002088) Cascade Filter Mapping Configuration Register + * 21 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC21_b; + }; + + union + { + __IOM uint32_t FWCFMC22; /*!< (@ 0x0000208C) Cascade Filter Mapping Configuration Register + * 22 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC22_b; + }; + + union + { + __IOM uint32_t FWCFMC23; /*!< (@ 0x00002090) Cascade Filter Mapping Configuration Register + * 23 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC23_b; + }; + + union + { + __IOM uint32_t FWCFMC24; /*!< (@ 0x00002094) Cascade Filter Mapping Configuration Register + * 24 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC24_b; + }; + + union + { + __IOM uint32_t FWCFMC25; /*!< (@ 0x00002098) Cascade Filter Mapping Configuration Register + * 25 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC25_b; + }; + + union + { + __IOM uint32_t FWCFMC26; /*!< (@ 0x0000209C) Cascade Filter Mapping Configuration Register + * 26 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC26_b; + }; + __IM uint32_t RESERVED77[8]; + + union + { + __IOM uint32_t FWCFC3; /*!< (@ 0x000020C0) Cascade Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC3_b; + }; + + union + { + __IOM uint32_t FWCFMC30; /*!< (@ 0x000020C4) Cascade Filter Mapping Configuration Register + * 30 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC30_b; + }; + + union + { + __IOM uint32_t FWCFMC31; /*!< (@ 0x000020C8) Cascade Filter Mapping Configuration Register + * 31 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC31_b; + }; + + union + { + __IOM uint32_t FWCFMC32; /*!< (@ 0x000020CC) Cascade Filter Mapping Configuration Register + * 32 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC32_b; + }; + + union + { + __IOM uint32_t FWCFMC33; /*!< (@ 0x000020D0) Cascade Filter Mapping Configuration Register + * 33 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC33_b; + }; + + union + { + __IOM uint32_t FWCFMC34; /*!< (@ 0x000020D4) Cascade Filter Mapping Configuration Register + * 34 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC34_b; + }; + + union + { + __IOM uint32_t FWCFMC35; /*!< (@ 0x000020D8) Cascade Filter Mapping Configuration Register + * 35 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC35_b; + }; + + union + { + __IOM uint32_t FWCFMC36; /*!< (@ 0x000020DC) Cascade Filter Mapping Configuration Register + * 36 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC36_b; + }; + __IM uint32_t RESERVED78[8]; + + union + { + __IOM uint32_t FWCFC4; /*!< (@ 0x00002100) Cascade Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC4_b; + }; + + union + { + __IOM uint32_t FWCFMC40; /*!< (@ 0x00002104) Cascade Filter Mapping Configuration Register + * 40 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC40_b; + }; + + union + { + __IOM uint32_t FWCFMC41; /*!< (@ 0x00002108) Cascade Filter Mapping Configuration Register + * 41 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC41_b; + }; + + union + { + __IOM uint32_t FWCFMC42; /*!< (@ 0x0000210C) Cascade Filter Mapping Configuration Register + * 42 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC42_b; + }; + + union + { + __IOM uint32_t FWCFMC43; /*!< (@ 0x00002110) Cascade Filter Mapping Configuration Register + * 43 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC43_b; + }; + + union + { + __IOM uint32_t FWCFMC44; /*!< (@ 0x00002114) Cascade Filter Mapping Configuration Register + * 44 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC44_b; + }; + + union + { + __IOM uint32_t FWCFMC45; /*!< (@ 0x00002118) Cascade Filter Mapping Configuration Register + * 45 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC45_b; + }; + + union + { + __IOM uint32_t FWCFMC46; /*!< (@ 0x0000211C) Cascade Filter Mapping Configuration Register + * 46 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC46_b; + }; + __IM uint32_t RESERVED79[8]; + + union + { + __IOM uint32_t FWCFC5; /*!< (@ 0x00002140) Cascade Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC5_b; + }; + + union + { + __IOM uint32_t FWCFMC50; /*!< (@ 0x00002144) Cascade Filter Mapping Configuration Register + * 50 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC50_b; + }; + + union + { + __IOM uint32_t FWCFMC51; /*!< (@ 0x00002148) Cascade Filter Mapping Configuration Register + * 51 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC51_b; + }; + + union + { + __IOM uint32_t FWCFMC52; /*!< (@ 0x0000214C) Cascade Filter Mapping Configuration Register + * 52 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC52_b; + }; + + union + { + __IOM uint32_t FWCFMC53; /*!< (@ 0x00002150) Cascade Filter Mapping Configuration Register + * 53 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC53_b; + }; + + union + { + __IOM uint32_t FWCFMC54; /*!< (@ 0x00002154) Cascade Filter Mapping Configuration Register + * 54 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC54_b; + }; + + union + { + __IOM uint32_t FWCFMC55; /*!< (@ 0x00002158) Cascade Filter Mapping Configuration Register + * 55 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC55_b; + }; + + union + { + __IOM uint32_t FWCFMC56; /*!< (@ 0x0000215C) Cascade Filter Mapping Configuration Register + * 56 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC56_b; + }; + __IM uint32_t RESERVED80[8]; + + union + { + __IOM uint32_t FWCFC6; /*!< (@ 0x00002180) Cascade Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC6_b; + }; + + union + { + __IOM uint32_t FWCFMC60; /*!< (@ 0x00002184) Cascade Filter Mapping Configuration Register + * 60 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC60_b; + }; + + union + { + __IOM uint32_t FWCFMC61; /*!< (@ 0x00002188) Cascade Filter Mapping Configuration Register + * 61 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC61_b; + }; + + union + { + __IOM uint32_t FWCFMC62; /*!< (@ 0x0000218C) Cascade Filter Mapping Configuration Register + * 62 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC62_b; + }; + + union + { + __IOM uint32_t FWCFMC63; /*!< (@ 0x00002190) Cascade Filter Mapping Configuration Register + * 63 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC63_b; + }; + + union + { + __IOM uint32_t FWCFMC64; /*!< (@ 0x00002194) Cascade Filter Mapping Configuration Register + * 64 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC64_b; + }; + + union + { + __IOM uint32_t FWCFMC65; /*!< (@ 0x00002198) Cascade Filter Mapping Configuration Register + * 65 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC65_b; + }; + + union + { + __IOM uint32_t FWCFMC66; /*!< (@ 0x0000219C) Cascade Filter Mapping Configuration Register + * 66 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC66_b; + }; + __IM uint32_t RESERVED81[8]; + + union + { + __IOM uint32_t FWCFC7; /*!< (@ 0x000021C0) Cascade Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC7_b; + }; + + union + { + __IOM uint32_t FWCFMC70; /*!< (@ 0x000021C4) Cascade Filter Mapping Configuration Register + * 70 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC70_b; + }; + + union + { + __IOM uint32_t FWCFMC71; /*!< (@ 0x000021C8) Cascade Filter Mapping Configuration Register + * 71 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC71_b; + }; + + union + { + __IOM uint32_t FWCFMC72; /*!< (@ 0x000021CC) Cascade Filter Mapping Configuration Register + * 72 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC72_b; + }; + + union + { + __IOM uint32_t FWCFMC73; /*!< (@ 0x000021D0) Cascade Filter Mapping Configuration Register + * 73 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC73_b; + }; + + union + { + __IOM uint32_t FWCFMC74; /*!< (@ 0x000021D4) Cascade Filter Mapping Configuration Register + * 74 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC74_b; + }; + + union + { + __IOM uint32_t FWCFMC75; /*!< (@ 0x000021D8) Cascade Filter Mapping Configuration Register + * 75 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC75_b; + }; + + union + { + __IOM uint32_t FWCFMC76; /*!< (@ 0x000021DC) Cascade Filter Mapping Configuration Register + * 76 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC76_b; + }; + __IM uint32_t RESERVED82[8]; + + union + { + __IOM uint32_t FWCFC8; /*!< (@ 0x00002200) Cascade Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC8_b; + }; + + union + { + __IOM uint32_t FWCFMC80; /*!< (@ 0x00002204) Cascade Filter Mapping Configuration Register + * 80 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC80_b; + }; + + union + { + __IOM uint32_t FWCFMC81; /*!< (@ 0x00002208) Cascade Filter Mapping Configuration Register + * 81 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC81_b; + }; + + union + { + __IOM uint32_t FWCFMC82; /*!< (@ 0x0000220C) Cascade Filter Mapping Configuration Register + * 82 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC82_b; + }; + + union + { + __IOM uint32_t FWCFMC83; /*!< (@ 0x00002210) Cascade Filter Mapping Configuration Register + * 83 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC83_b; + }; + + union + { + __IOM uint32_t FWCFMC84; /*!< (@ 0x00002214) Cascade Filter Mapping Configuration Register + * 84 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC84_b; + }; + + union + { + __IOM uint32_t FWCFMC85; /*!< (@ 0x00002218) Cascade Filter Mapping Configuration Register + * 85 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC85_b; + }; + + union + { + __IOM uint32_t FWCFMC86; /*!< (@ 0x0000221C) Cascade Filter Mapping Configuration Register + * 86 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC86_b; + }; + __IM uint32_t RESERVED83[8]; + + union + { + __IOM uint32_t FWCFC9; /*!< (@ 0x00002240) Cascade Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC9_b; + }; + + union + { + __IOM uint32_t FWCFMC90; /*!< (@ 0x00002244) Cascade Filter Mapping Configuration Register + * 90 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC90_b; + }; + + union + { + __IOM uint32_t FWCFMC91; /*!< (@ 0x00002248) Cascade Filter Mapping Configuration Register + * 91 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC91_b; + }; + + union + { + __IOM uint32_t FWCFMC92; /*!< (@ 0x0000224C) Cascade Filter Mapping Configuration Register + * 92 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC92_b; + }; + + union + { + __IOM uint32_t FWCFMC93; /*!< (@ 0x00002250) Cascade Filter Mapping Configuration Register + * 93 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC93_b; + }; + + union + { + __IOM uint32_t FWCFMC94; /*!< (@ 0x00002254) Cascade Filter Mapping Configuration Register + * 94 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC94_b; + }; + + union + { + __IOM uint32_t FWCFMC95; /*!< (@ 0x00002258) Cascade Filter Mapping Configuration Register + * 95 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC95_b; + }; + + union + { + __IOM uint32_t FWCFMC96; /*!< (@ 0x0000225C) Cascade Filter Mapping Configuration Register + * 96 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC96_b; + }; + __IM uint32_t RESERVED84[8]; + + union + { + __IOM uint32_t FWCFC10; /*!< (@ 0x00002280) Cascade Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC10_b; + }; + + union + { + __IOM uint32_t FWCFMC100; /*!< (@ 0x00002284) Cascade Filter Mapping Configuration Register + * 100 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC100_b; + }; + + union + { + __IOM uint32_t FWCFMC101; /*!< (@ 0x00002288) Cascade Filter Mapping Configuration Register + * 101 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC101_b; + }; + + union + { + __IOM uint32_t FWCFMC102; /*!< (@ 0x0000228C) Cascade Filter Mapping Configuration Register + * 102 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC102_b; + }; + + union + { + __IOM uint32_t FWCFMC103; /*!< (@ 0x00002290) Cascade Filter Mapping Configuration Register + * 103 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC103_b; + }; + + union + { + __IOM uint32_t FWCFMC104; /*!< (@ 0x00002294) Cascade Filter Mapping Configuration Register + * 104 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC104_b; + }; + + union + { + __IOM uint32_t FWCFMC105; /*!< (@ 0x00002298) Cascade Filter Mapping Configuration Register + * 105 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC105_b; + }; + + union + { + __IOM uint32_t FWCFMC106; /*!< (@ 0x0000229C) Cascade Filter Mapping Configuration Register + * 106 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC106_b; + }; + __IM uint32_t RESERVED85[8]; + + union + { + __IOM uint32_t FWCFC11; /*!< (@ 0x000022C0) Cascade Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC11_b; + }; + + union + { + __IOM uint32_t FWCFMC110; /*!< (@ 0x000022C4) Cascade Filter Mapping Configuration Register + * 110 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC110_b; + }; + + union + { + __IOM uint32_t FWCFMC111; /*!< (@ 0x000022C8) Cascade Filter Mapping Configuration Register + * 111 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC111_b; + }; + + union + { + __IOM uint32_t FWCFMC112; /*!< (@ 0x000022CC) Cascade Filter Mapping Configuration Register + * 112 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC112_b; + }; + + union + { + __IOM uint32_t FWCFMC113; /*!< (@ 0x000022D0) Cascade Filter Mapping Configuration Register + * 113 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC113_b; + }; + + union + { + __IOM uint32_t FWCFMC114; /*!< (@ 0x000022D4) Cascade Filter Mapping Configuration Register + * 114 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC114_b; + }; + + union + { + __IOM uint32_t FWCFMC115; /*!< (@ 0x000022D8) Cascade Filter Mapping Configuration Register + * 115 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC115_b; + }; + + union + { + __IOM uint32_t FWCFMC116; /*!< (@ 0x000022DC) Cascade Filter Mapping Configuration Register + * 116 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC116_b; + }; + __IM uint32_t RESERVED86[8]; + + union + { + __IOM uint32_t FWCFC12; /*!< (@ 0x00002300) Cascade Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC12_b; + }; + + union + { + __IOM uint32_t FWCFMC120; /*!< (@ 0x00002304) Cascade Filter Mapping Configuration Register + * 120 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC120_b; + }; + + union + { + __IOM uint32_t FWCFMC121; /*!< (@ 0x00002308) Cascade Filter Mapping Configuration Register + * 121 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC121_b; + }; + + union + { + __IOM uint32_t FWCFMC122; /*!< (@ 0x0000230C) Cascade Filter Mapping Configuration Register + * 122 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC122_b; + }; + + union + { + __IOM uint32_t FWCFMC123; /*!< (@ 0x00002310) Cascade Filter Mapping Configuration Register + * 123 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC123_b; + }; + + union + { + __IOM uint32_t FWCFMC124; /*!< (@ 0x00002314) Cascade Filter Mapping Configuration Register + * 124 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC124_b; + }; + + union + { + __IOM uint32_t FWCFMC125; /*!< (@ 0x00002318) Cascade Filter Mapping Configuration Register + * 125 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC125_b; + }; + + union + { + __IOM uint32_t FWCFMC126; /*!< (@ 0x0000231C) Cascade Filter Mapping Configuration Register + * 126 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC126_b; + }; + __IM uint32_t RESERVED87[8]; + + union + { + __IOM uint32_t FWCFC13; /*!< (@ 0x00002340) Cascade Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC13_b; + }; + + union + { + __IOM uint32_t FWCFMC130; /*!< (@ 0x00002344) Cascade Filter Mapping Configuration Register + * 130 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC130_b; + }; + + union + { + __IOM uint32_t FWCFMC131; /*!< (@ 0x00002348) Cascade Filter Mapping Configuration Register + * 131 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC131_b; + }; + + union + { + __IOM uint32_t FWCFMC132; /*!< (@ 0x0000234C) Cascade Filter Mapping Configuration Register + * 132 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC132_b; + }; + + union + { + __IOM uint32_t FWCFMC133; /*!< (@ 0x00002350) Cascade Filter Mapping Configuration Register + * 133 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC133_b; + }; + + union + { + __IOM uint32_t FWCFMC134; /*!< (@ 0x00002354) Cascade Filter Mapping Configuration Register + * 134 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC134_b; + }; + + union + { + __IOM uint32_t FWCFMC135; /*!< (@ 0x00002358) Cascade Filter Mapping Configuration Register + * 135 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC135_b; + }; + + union + { + __IOM uint32_t FWCFMC136; /*!< (@ 0x0000235C) Cascade Filter Mapping Configuration Register + * 136 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC136_b; + }; + __IM uint32_t RESERVED88[8]; + + union + { + __IOM uint32_t FWCFC14; /*!< (@ 0x00002380) Cascade Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC14_b; + }; + + union + { + __IOM uint32_t FWCFMC140; /*!< (@ 0x00002384) Cascade Filter Mapping Configuration Register + * 140 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC140_b; + }; + + union + { + __IOM uint32_t FWCFMC141; /*!< (@ 0x00002388) Cascade Filter Mapping Configuration Register + * 141 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC141_b; + }; + + union + { + __IOM uint32_t FWCFMC142; /*!< (@ 0x0000238C) Cascade Filter Mapping Configuration Register + * 142 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC142_b; + }; + + union + { + __IOM uint32_t FWCFMC143; /*!< (@ 0x00002390) Cascade Filter Mapping Configuration Register + * 143 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC143_b; + }; + + union + { + __IOM uint32_t FWCFMC144; /*!< (@ 0x00002394) Cascade Filter Mapping Configuration Register + * 144 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC144_b; + }; + + union + { + __IOM uint32_t FWCFMC145; /*!< (@ 0x00002398) Cascade Filter Mapping Configuration Register + * 145 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC145_b; + }; + + union + { + __IOM uint32_t FWCFMC146; /*!< (@ 0x0000239C) Cascade Filter Mapping Configuration Register + * 146 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC146_b; + }; + __IM uint32_t RESERVED89[8]; + + union + { + __IOM uint32_t FWCFC15; /*!< (@ 0x000023C0) Cascade Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t CFEFFV : 7; /*!< [6..0] Cascade Filter E-Frame Filter Valid */ + uint32_t : 9; + __IOM uint32_t CFPFFV : 4; /*!< [19..16] Cascade Filter P-Frame Filter Valid */ + uint32_t : 12; + } FWCFC15_b; + }; + + union + { + __IOM uint32_t FWCFMC150; /*!< (@ 0x000023C4) Cascade Filter Mapping Configuration Register + * 150 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC150_b; + }; + + union + { + __IOM uint32_t FWCFMC151; /*!< (@ 0x000023C8) Cascade Filter Mapping Configuration Register + * 151 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC151_b; + }; + + union + { + __IOM uint32_t FWCFMC152; /*!< (@ 0x000023CC) Cascade Filter Mapping Configuration Register + * 152 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC152_b; + }; + + union + { + __IOM uint32_t FWCFMC153; /*!< (@ 0x000023D0) Cascade Filter Mapping Configuration Register + * 153 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC153_b; + }; + + union + { + __IOM uint32_t FWCFMC154; /*!< (@ 0x000023D4) Cascade Filter Mapping Configuration Register + * 154 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC154_b; + }; + + union + { + __IOM uint32_t FWCFMC155; /*!< (@ 0x000023D8) Cascade Filter Mapping Configuration Register + * 155 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC155_b; + }; + + union + { + __IOM uint32_t FWCFMC156; /*!< (@ 0x000023DC) Cascade Filter Mapping Configuration Register + * 156 */ + + struct + { + __IOM uint32_t CFFN : 7; /*!< [6..0] Cascade Filter Filter Number */ + uint32_t : 8; + __IOM uint32_t CFFV : 1; /*!< [15..15] Cascade Filter Valid */ + uint32_t : 16; + } FWCFMC156_b; + }; + __IM uint32_t RESERVED90[1802]; + + union + { + __IOM uint32_t FWIP4SC; /*!< (@ 0x00004008) IPv4 Stream Configuration Register */ + + struct + { + __IOM uint32_t IP4IMDH : 1; /*!< [0..0] IPv4 Include MAC Destination in Hash */ + __IOM uint32_t IP4IMSH : 1; /*!< [1..1] IPv4 Include MAC Source in Hash */ + __IOM uint32_t IP4ISVH : 1; /*!< [2..2] IPv4 Include S-TAG VLAN ID in Hash */ + __IOM uint32_t IP4ISPH : 1; /*!< [3..3] IPv4 Include S-TAG PCP in Hash */ + __IOM uint32_t IP4ISDH : 1; /*!< [4..4] IPv4 Include S-TAG DEI in Hash */ + __IOM uint32_t IP4ICVH : 1; /*!< [5..5] IPv4 Include C-TAG VLAN ID in Hash */ + __IOM uint32_t IP4ICPH : 1; /*!< [6..6] IPv4 Include C-TAG PCP in Hash */ + __IOM uint32_t IP4ICDH : 1; /*!< [7..7] IPv4 Include C-TAG DEI in Hash */ + __IOM uint32_t IP4IISH : 1; /*!< [8..8] IPv4 Include IP Source in Hash */ + __IOM uint32_t IP4IIDH : 1; /*!< [9..9] IPv4 Include IP Destination in Hash */ + __IOM uint32_t IP4IPH : 1; /*!< [10..10] IPv4 Include Protocol in Hash */ + __IOM uint32_t IP4ISPTH : 1; /*!< [11..11] IPv4 Include Source Port in Hash */ + __IOM uint32_t IP4IDPTH : 1; /*!< [12..12] IPv4 Include Destination Port in Hash */ + uint32_t : 3; + __IOM uint32_t IP4ISVS : 1; /*!< [16..16] IPv4 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t IP4ISPS : 1; /*!< [17..17] IPv4 Include S-TAG PCP in Stream */ + __IOM uint32_t IP4ISDS : 1; /*!< [18..18] IPv4 Include S-TAG DEI in Stream */ + __IOM uint32_t IP4ICVS : 1; /*!< [19..19] IPv4 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t IP4ICPS : 1; /*!< [20..20] IPv4 Include C-TAG PCP in Stream */ + __IOM uint32_t IP4ICDS : 1; /*!< [21..21] IPv4 Include C-TAG DEI in Stream */ + __IOM uint32_t IP4IISS : 1; /*!< [22..22] IPv4 Include IP Source in Stream */ + __IOM uint32_t IP4IIDS : 1; /*!< [23..23] IPv4 Include IP Destination in Stream */ + __IOM uint32_t IP4IDPTS : 1; /*!< [24..24] IPv4 Include Destination Port in Stream */ + uint32_t : 7; + } FWIP4SC_b; + }; + __IM uint32_t RESERVED91[3]; + + union + { + __IOM uint32_t FWIP6SC; /*!< (@ 0x00004018) IPv6 Stream Configuration Register */ + + struct + { + __IOM uint32_t IP6IMDH : 1; /*!< [0..0] IPv6 Include MAC Destination in Hash */ + __IOM uint32_t IP6IMSH : 1; /*!< [1..1] IPv6 Include MAC Source in Hash */ + __IOM uint32_t IP6ISVH : 1; /*!< [2..2] IPv6 Include S-TAG VLAN ID in Hash */ + __IOM uint32_t IP6ISPH : 1; /*!< [3..3] IPv6 Include S-TAG PCP in Hash */ + __IOM uint32_t IP6ISDH : 1; /*!< [4..4] IPv6 Include S-TAG DEI in Hash */ + __IOM uint32_t IP6ICVH : 1; /*!< [5..5] IPv6 Include C-TAG VLAN ID in Hash */ + __IOM uint32_t IP6ICPH : 1; /*!< [6..6] IPv6 Include C-TAG PCP in Hash */ + __IOM uint32_t IP6ICDH : 1; /*!< [7..7] IPv6 Include C-TAG DEI in Hash */ + __IOM uint32_t IP6IISH : 1; /*!< [8..8] IPv6 Include IP Source in Hash */ + __IOM uint32_t IP6IIDH : 1; /*!< [9..9] IPv6 Include IP Destination in Hash */ + __IOM uint32_t IP6IPH : 1; /*!< [10..10] IPv6 Include Protocol in Hash */ + __IOM uint32_t IP6ISPTH : 1; /*!< [11..11] IPv6 Include Source Port in Hash */ + __IOM uint32_t IP6IDPTH : 1; /*!< [12..12] IPv6 Include Destination Port in Hash */ + uint32_t : 3; + __IOM uint32_t IP6ISVS : 1; /*!< [16..16] IPv6 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t IP6ISPS : 1; /*!< [17..17] IPv6 Include S-TAG PCP in Stream */ + __IOM uint32_t IP6ISDS : 1; /*!< [18..18] IPv6 Include S-TAG DEI in Stream */ + __IOM uint32_t IP6ICVS : 1; /*!< [19..19] IPv6 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t IP6ICPS : 1; /*!< [20..20] IPv6 Include C-TAG PCP in Stream */ + __IOM uint32_t IP6ICDS : 1; /*!< [21..21] IPv6 Include C-TAG DEI in Stream */ + __IOM uint32_t IP6II0S : 1; /*!< [22..22] IPv6 Include IP 0 in Stream */ + __IOM uint32_t IP6II1S : 1; /*!< [23..23] IPv6 Include IP 1 in Stream */ + __IOM uint32_t IP6IDPTS : 1; /*!< [24..24] IPv6 Include Destination Port in Stream */ + uint32_t : 7; + } FWIP6SC_b; + }; + + union + { + __IOM uint32_t FWIP6OC; /*!< (@ 0x0000401C) IPv6 Offset Configuration Register */ + + struct + { + __IOM uint32_t IP6IPOM0 : 1; /*!< [0..0] IPv6 IP Offset mode 0 */ + uint32_t : 3; + __IOM uint32_t IP6IPO0 : 4; /*!< [7..4] IPv6 IP Offset 0 */ + uint32_t : 8; + __IOM uint32_t IP6IPOM1 : 1; /*!< [16..16] IPv6 IP Offset mode 1 */ + uint32_t : 3; + __IOM uint32_t IP6IPO1 : 4; /*!< [23..20] IPv6 IP Offset 1 */ + uint32_t : 8; + } FWIP6OC_b; + }; + + union + { + __IOM uint32_t FWL2SC; /*!< (@ 0x00004020) Layer 2 Stream Configuration Register */ + + struct + { + __IOM uint32_t L2IMDS : 1; /*!< [0..0] Layer 2 Include MAC Destination in Stream */ + __IOM uint32_t L2IMSS : 1; /*!< [1..1] Layer 2 Include MAC Source in Stream */ + __IOM uint32_t L2ISVS : 1; /*!< [2..2] Layer 2 Include S-TAG VLAN ID in Stream */ + __IOM uint32_t L2ISPS : 1; /*!< [3..3] Layer 2 Include S-TAG PCP ID in Stream */ + __IOM uint32_t L2ISDS : 1; /*!< [4..4] Layer 2 Include S-TAG DEI in Stream */ + __IOM uint32_t L2ICVS : 1; /*!< [5..5] Layer 2 Include C-TAG VLAN ID in Stream */ + __IOM uint32_t L2ICPS : 1; /*!< [6..6] Layer 2 Include C-TAG PCP ID in Stream */ + __IOM uint32_t L2ICDS : 1; /*!< [7..7] Layer 2 Include C-TAG DEI in Stream */ + uint32_t : 24; + } FWL2SC_b; + }; + __IM uint32_t RESERVED92[3]; + + union + { + __IOM uint32_t FWSFHEC; /*!< (@ 0x00004030) Stream Filter Hash Equation Configuration Register */ + + struct + { + __IOM uint32_t IP4HE : 16; /*!< [15..0] Stream Filter Hash Equation */ + __IOM uint32_t IP6HE : 16; /*!< [31..16] Stream Filter Hash Equation */ + } FWSFHEC_b; + }; + __IM uint32_t RESERVED93[3]; + + union + { + __IOM uint32_t FWSHCR0; /*!< (@ 0x00004040) Software Hash Calculation Request Register 0 */ + + struct + { + __IOM uint32_t SHCMDP0 : 32; /*!< [31..0] Software Hash Calculation MAC Destination Part 0 */ + } FWSHCR0_b; + }; + + union + { + __IOM uint32_t FWSHCR1; /*!< (@ 0x00004044) Software Hash Calculation Request Register 1 */ + + struct + { + __IOM uint32_t SHCMSP0 : 16; /*!< [15..0] Software Hash Calculation MAC Source Part 0 */ + __IOM uint32_t SHCMDP1 : 16; /*!< [31..16] Software Hash Calculation MAC Destination Part 1 */ + } FWSHCR1_b; + }; + + union + { + __IOM uint32_t FWSHCR2; /*!< (@ 0x00004048) Software Hash Calculation Request Register 2 */ + + struct + { + __IOM uint32_t SHCMSP1 : 32; /*!< [31..0] Software Hash Calculation MAC Source Part 1 */ + } FWSHCR2_b; + }; + + union + { + __IOM uint32_t FWSHCR3; /*!< (@ 0x0000404C) Software Hash Calculation Request Register 3 */ + + struct + { + __IOM uint32_t SHCCV : 12; /*!< [11..0] Software Hash Calculation C-TAG VLAN */ + __IOM uint32_t SHCCD : 1; /*!< [12..12] Software Hash Calculation C-TAG DEI */ + __IOM uint32_t SHCCP : 3; /*!< [15..13] Software Hash Calculation C-TAG PCP */ + __IOM uint32_t SHCSV : 12; /*!< [27..16] Software Hash Calculation S-TAG VLANs */ + __IOM uint32_t SHCSD : 1; /*!< [28..28] Software Hash Calculation S-TAG DEI */ + __IOM uint32_t SHCSP : 3; /*!< [31..29] Software Hash Calculation S-TAG PCP */ + } FWSHCR3_b; + }; + + union + { + __IOM uint32_t FWSHCR4; /*!< (@ 0x00004050) Software Hash Calculation Request Register 4 */ + + struct + { + __IOM uint32_t SHCP : 8; /*!< [7..0] Software Hash Calculation Protocol (NextHeader for IPv6) */ + uint32_t : 8; + __IOM uint32_t SHCFF : 1; /*!< [16..16] Software Hash Calculation Frame Format */ + uint32_t : 15; + } FWSHCR4_b; + }; + + union + { + __IOM uint32_t FWSHCR5; /*!< (@ 0x00004054) Software Hash Calculation Request Register 5 */ + + struct + { + __IOM uint32_t SHCISP0 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 0 */ + } FWSHCR5_b; + }; + + union + { + __IOM uint32_t FWSHCR6; /*!< (@ 0x00004058) Software Hash Calculation Request Register 6 */ + + struct + { + __IOM uint32_t SHCISP1 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 1 */ + } FWSHCR6_b; + }; + + union + { + __IOM uint32_t FWSHCR7; /*!< (@ 0x0000405C) Software Hash Calculation Request Register 7 */ + + struct + { + __IOM uint32_t SHCISP2 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 2 */ + } FWSHCR7_b; + }; + + union + { + __IOM uint32_t FWSHCR8; /*!< (@ 0x00004060) Software Hash Calculation Request Register 8 */ + + struct + { + __IOM uint32_t SHCISP3 : 32; /*!< [31..0] Software Hash Calculation IP Source Part 3 */ + } FWSHCR8_b; + }; + + union + { + __IOM uint32_t FWSHCR9; /*!< (@ 0x00004064) Software Hash Calculation Request Register 9 */ + + struct + { + __IOM uint32_t SHCIDP0 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 0 */ + } FWSHCR9_b; + }; + + union + { + __IOM uint32_t FWSHCR10; /*!< (@ 0x00004068) Software Hash Calculation Request Register 10 */ + + struct + { + __IOM uint32_t SHCIDP1 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 1 */ + } FWSHCR10_b; + }; + + union + { + __IOM uint32_t FWSHCR11; /*!< (@ 0x0000406C) Software Hash Calculation Request Register 11 */ + + struct + { + __IOM uint32_t SHCIDP2 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 2 */ + } FWSHCR11_b; + }; + + union + { + __IOM uint32_t FWSHCR12; /*!< (@ 0x00004070) Software Hash Calculation Request Register 12 */ + + struct + { + __IOM uint32_t SHCIDP3 : 32; /*!< [31..0] Software Hash Calculation IP Destination Part 3 */ + } FWSHCR12_b; + }; + + union + { + __IOM uint32_t FWSHCR13; /*!< (@ 0x00004074) Software Hash Calculation Request Register 13 */ + + struct + { + __IOM uint32_t SHCDP : 16; /*!< [15..0] Software Hash Calculation Destination Port */ + __IOM uint32_t SHCSP : 16; /*!< [31..16] Software Hash Calculation Source Port */ + } FWSHCR13_b; + }; + + union + { + __IM uint32_t FWSHCRR; /*!< (@ 0x00004078) Software Hash Calculation Request Result Register */ + + struct + { + __IM uint32_t SHCR : 16; /*!< [15..0] Software Hash Calculation Result */ + uint32_t : 15; + __IM uint32_t SHC : 1; /*!< [31..31] Software Hash Calculation */ + } FWSHCRR_b; + }; + __IM uint32_t RESERVED94[5]; + + union + { + __IOM uint32_t FWLTHHEC; /*!< (@ 0x00004090) L3 Hash Entry Configuration Register */ + + struct + { + __IOM uint32_t LTHHMC : 10; /*!< [9..0] L3 Hash Maximum Collision */ + uint32_t : 6; + __IOM uint32_t LTHHMUE : 11; /*!< [26..16] L3 Hash Maximum Unsecure Entry */ + uint32_t : 5; + } FWLTHHEC_b; + }; + + union + { + __IOM uint32_t FWLTHHC; /*!< (@ 0x00004094) L3 Hash Configuration Register */ + + struct + { + __IOM uint32_t LTHHE : 10; /*!< [9..0] L3 Hash Equation */ + uint32_t : 22; + } FWLTHHC_b; + }; + __IM uint32_t RESERVED95[2]; + + union + { + __IOM uint32_t FWLTHTL0; /*!< (@ 0x000040A0) L3 Table Learn Register 0 */ + + struct + { + __IOM uint32_t LTHSLP0 : 3; /*!< [2..0] L3 Stream Learn Part 0 */ + uint32_t : 5; + __IOM uint32_t LTHSLL : 1; /*!< [8..8] L3 Security Level Learn */ + uint32_t : 7; + __IOM uint32_t LTHED : 1; /*!< [16..16] L3 Entry Delete */ + uint32_t : 15; + } FWLTHTL0_b; + }; + + union + { + __IOM uint32_t FWLTHTL1; /*!< (@ 0x000040A4) L3 Table Learn Register 1 */ + + struct + { + __IOM uint32_t LTHSLP1 : 32; /*!< [31..0] L3 Stream Learn Part 1 */ + } FWLTHTL1_b; + }; + + union + { + __IOM uint32_t FWLTHTL2; /*!< (@ 0x000040A8) L3 Table Learn Register 2 */ + + struct + { + __IOM uint32_t LTHSLP2 : 32; /*!< [31..0] L3 Stream Learn Part 2 */ + } FWLTHTL2_b; + }; + + union + { + __IOM uint32_t FWLTHTL3; /*!< (@ 0x000040AC) L3 Table Learn Register 3 */ + + struct + { + __IOM uint32_t LTHSLP3 : 32; /*!< [31..0] L3 Stream Learn Part 3 */ + } FWLTHTL3_b; + }; + + union + { + __IOM uint32_t FWLTHTL4; /*!< (@ 0x000040B0) L3 Table Learn Register 4 */ + + struct + { + __IOM uint32_t LTHSLP4 : 32; /*!< [31..0] L3 Stream Learn Part 4 */ + } FWLTHTL4_b; + }; + + union + { + __IOM uint32_t FWLTHTL5; /*!< (@ 0x000040B4) L3 Table Learn Register 5 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LTHMSDUNL : 4; /*!< [19..16] L3 MSDU Number Learn */ + uint32_t : 11; + __IOM uint32_t LTHMSDUVL : 1; /*!< [31..31] L3 MSDU Valid Learn */ + } FWLTHTL5_b; + }; + + union + { + __IOM uint32_t FWLTHTL6; /*!< (@ 0x000040B8) L3 Table Learn Register 6 */ + + struct + { + __IOM uint32_t LTHFRERNL : 7; /*!< [6..0] L3 FRER Number Learn */ + uint32_t : 8; + __IOM uint32_t LTHFRERVL : 1; /*!< [15..15] L3 FRER Valid Learn */ + __IOM uint32_t LTHMTRNL : 5; /*!< [20..16] L3 MeTeR Number Learn */ + uint32_t : 10; + __IOM uint32_t LTHMTRVL : 1; /*!< [31..31] L3 MeTeR Valid Learn */ + } FWLTHTL6_b; + }; + + union + { + __IOM uint32_t FWLTHTL7; /*!< (@ 0x000040BC) L3 Table Learn Register 7 */ + + struct + { + __IOM uint32_t LTHRNL : 8; /*!< [7..0] L3 Routing Number Learn */ + uint32_t : 7; + __IOM uint32_t LTHRVL : 1; /*!< [15..15] L3 Routing Valid Learn */ + __IOM uint32_t LTHSLVL : 7; /*!< [22..16] L3 Source Lock Vector Learn */ + uint32_t : 9; + } FWLTHTL7_b; + }; + + union + { + __IOM uint32_t FWLTHTL80; /*!< (@ 0x000040C0) L3 Table Learn Register 80 */ + + struct + { + __IOM uint32_t LTHCSDL : 7; /*!< [6..0] L3 CPU Sub-Destination Learn */ + uint32_t : 25; + } FWLTHTL80_b; + }; + __IM uint32_t RESERVED96[3]; + + union + { + __IOM uint32_t FWLTHTL9; /*!< (@ 0x000040D0) L3 Table Learn Register 9 */ + + struct + { + __IOM uint32_t LTHDVL : 7; /*!< [6..0] L3 Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t LTHIPVL : 3; /*!< [18..16] L3 Internal Priority Value Learn */ + __IOM uint32_t LTHIPUL : 1; /*!< [19..19] L3 Internal Priority Update Learn */ + __IOM uint32_t LTHEMEL : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Learn */ + __IOM uint32_t LTHCMEL : 1; /*!< [21..21] L3 CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWLTHTL9_b; + }; + + union + { + __IM uint32_t FWLTHTLR; /*!< (@ 0x000040D4) L3 Table Learn Result Register */ + + struct + { + __IM uint32_t LTHLF : 1; /*!< [0..0] L3 Learn Fail */ + __IM uint32_t LTHLSF : 1; /*!< [1..1] L3 Learn Security Fail */ + __IM uint32_t LTHLEF : 1; /*!< [2..2] L3 Learn ECC Fail */ + __IM uint32_t LTHLO : 1; /*!< [3..3] L3 Learn Overwrite */ + uint32_t : 12; + __IM uint32_t LTHLCN : 10; /*!< [25..16] L3 Learn Collision Number */ + uint32_t : 5; + __IM uint32_t LTHTL : 1; /*!< [31..31] L3 Table Learn */ + } FWLTHTLR_b; + }; + __IM uint32_t RESERVED97[2]; + + union + { + __IOM uint32_t FWLTHTIM; /*!< (@ 0x000040E0) L3 Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t LTHTIOG : 1; /*!< [0..0] L3 Table Initialization Ongoing */ + __IM uint32_t LTHTR : 1; /*!< [1..1] L3 Table Ready */ + uint32_t : 30; + } FWLTHTIM_b; + }; + + union + { + __IM uint32_t FWLTHTEM; /*!< (@ 0x000040E4) L3 Table Entry Monitoring Register */ + + struct + { + __IM uint32_t LTHTEN : 11; /*!< [10..0] L3 Table Entry Number */ + uint32_t : 5; + __IM uint32_t LTHTUEN : 11; /*!< [26..16] L3 Table Unsecure Entry Number */ + uint32_t : 5; + } FWLTHTEM_b; + }; + __IM uint32_t RESERVED98[6]; + + union + { + __IOM uint32_t FWLTHTS0; /*!< (@ 0x00004100) L3 Table Search Register 0 */ + + struct + { + __IOM uint32_t LTHSSP0 : 3; /*!< [2..0] L3 Stream Search Part 0 */ + uint32_t : 21; + __IOM uint32_t LTHSSPFS : 1; /*!< [24..24] L3 Stream Search Perfect Filter Select */ + uint32_t : 7; + } FWLTHTS0_b; + }; + + union + { + __IOM uint32_t FWLTHTS1; /*!< (@ 0x00004104) L3 Table Search Register 1 */ + + struct + { + __IOM uint32_t LTHSSP1 : 32; /*!< [31..0] L3 Stream Search Part 1 */ + } FWLTHTS1_b; + }; + + union + { + __IOM uint32_t FWLTHTS2; /*!< (@ 0x00004108) L3 Table Search Register 2 */ + + struct + { + __IOM uint32_t LTHSSP2 : 32; /*!< [31..0] L3 Stream Search Part 2 */ + } FWLTHTS2_b; + }; + + union + { + __IOM uint32_t FWLTHTS3; /*!< (@ 0x0000410C) L3 Table Search Register 3 */ + + struct + { + __IOM uint32_t LTHSSP3 : 32; /*!< [31..0] L3 Stream Search Part 3 */ + } FWLTHTS3_b; + }; + + union + { + __IOM uint32_t FWLTHTS4; /*!< (@ 0x00004110) L3 Table Search Register 4 */ + + struct + { + __IOM uint32_t LTHSSP4 : 32; /*!< [31..0] L3 Stream Search Part 4 */ + } FWLTHTS4_b; + }; + __IM uint32_t RESERVED99[3]; + + union + { + __IOM uint32_t FWLTHTSR0; /*!< (@ 0x00004120) L3 Table Search Result Register 0 */ + + struct + { + __IOM uint32_t LTHSEF : 1; /*!< [0..0] L3 Search ECC Fail */ + __IM uint32_t LTHSNF : 1; /*!< [1..1] L3 Search Not found */ + uint32_t : 6; + __IM uint32_t LTHSLS : 1; /*!< [8..8] L3 Security Level Search */ + uint32_t : 7; + __IM uint32_t LTHSCN : 10; /*!< [25..16] L3 Search Collision Number */ + uint32_t : 5; + __IM uint32_t LTHTS : 1; /*!< [31..31] L3 Table Search */ + } FWLTHTSR0_b; + }; + + union + { + __IM uint32_t FWLTHTSR1; /*!< (@ 0x00004124) L3 Table Search Result Register 1 */ + + struct + { + uint32_t : 16; + __IM uint32_t LTHMSDUNS : 4; /*!< [19..16] L3 MSDU Number Search */ + uint32_t : 11; + __IM uint32_t LTHMSDUVS : 1; /*!< [31..31] L3 MSDU Valid Search */ + } FWLTHTSR1_b; + }; + + union + { + __IM uint32_t FWLTHTSR2; /*!< (@ 0x00004128) L3 Table Search Result Register 2 */ + + struct + { + __IM uint32_t LTHFRERNS : 6; /*!< [5..0] L3 FRER Number Search */ + uint32_t : 9; + __IM uint32_t LTHFRERVS : 1; /*!< [15..15] L3 FRER Valid Search */ + __IM uint32_t LTHMTRNS : 5; /*!< [20..16] L3 MeTeR Number Search */ + uint32_t : 10; + __IM uint32_t LTHMTRVS : 1; /*!< [31..31] L3 MeTeR Valid Search */ + } FWLTHTSR2_b; + }; + + union + { + __IM uint32_t FWLTHTSR3; /*!< (@ 0x0000412C) L3 Table Search Result Register 3 */ + + struct + { + __IM uint32_t LTHRNS : 8; /*!< [7..0] L3 Routing Number Search */ + uint32_t : 7; + __IM uint32_t LTHRVS : 1; /*!< [15..15] L3 Routing Valid Search */ + __IM uint32_t LTHSLVS : 7; /*!< [22..16] L3 Source Lock Vector Search */ + uint32_t : 9; + } FWLTHTSR3_b; + }; + + union + { + __IM uint32_t FWLTHTSR40; /*!< (@ 0x00004130) L3 Table Search Result Register 40 */ + + struct + { + __IM uint32_t LTHCSDS : 7; /*!< [6..0] L3 CPU Sub-Destination Search */ + uint32_t : 25; + } FWLTHTSR40_b; + }; + __IM uint32_t RESERVED100[3]; + + union + { + __IM uint32_t FWLTHTSR5; /*!< (@ 0x00004140) L3 Table Search Result Register 5 */ + + struct + { + __IM uint32_t LTHDVS : 7; /*!< [6..0] L3 Destination Vector Search */ + uint32_t : 9; + __IM uint32_t LTHIPVS : 3; /*!< [18..16] L3 Internal Priority Value Search */ + __IM uint32_t LTHIPUS : 1; /*!< [19..19] L3 Internal Priority Update Search */ + __IM uint32_t LTHEMES : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Search */ + __IM uint32_t LTHCMES : 1; /*!< [21..21] L3 CPU Mirroring Enable Search */ + uint32_t : 10; + } FWLTHTSR5_b; + }; + __IM uint32_t RESERVED101[3]; + + union + { + __IOM uint32_t FWLTHTR; /*!< (@ 0x00004150) L3 Table Read Register */ + + struct + { + __IOM uint32_t LTHAR : 10; /*!< [9..0] L3 Address Read */ + uint32_t : 22; + } FWLTHTR_b; + }; + + union + { + __IM uint32_t FWLTHTRR0; /*!< (@ 0x00004154) L3 Table Read Result Register 0 */ + + struct + { + __IM uint32_t LTHREF : 1; /*!< [0..0] L3 Read ECC Fail */ + __IM uint32_t LTHEVR : 1; /*!< [1..1] L3 Entry Valid Read */ + uint32_t : 29; + __IM uint32_t LTHTR : 1; /*!< [31..31] L3 Table Read */ + } FWLTHTRR0_b; + }; + + union + { + __IM uint32_t FWLTHTRR1; /*!< (@ 0x00004158) L3 Table Read Result Register 1 */ + + struct + { + __IM uint32_t LTHSRP0 : 3; /*!< [2..0] L3 Stream Read Part 0 */ + uint32_t : 5; + __IM uint32_t LTHSLR : 1; /*!< [8..8] L3 Security Level Read */ + uint32_t : 23; + } FWLTHTRR1_b; + }; + + union + { + __IM uint32_t FWLTHTRR2; /*!< (@ 0x0000415C) L3 Table Read Result Register 2 */ + + struct + { + __IM uint32_t LTHSRP1 : 32; /*!< [31..0] L3 Stream Read Part 1 */ + } FWLTHTRR2_b; + }; + + union + { + __IM uint32_t FWLTHTRR3; /*!< (@ 0x00004160) L3 Table Read Result Register 3 */ + + struct + { + __IM uint32_t LTHSRP2 : 32; /*!< [31..0] L3 Stream Read Part 2 */ + } FWLTHTRR3_b; + }; + + union + { + __IM uint32_t FWLTHTRR4; /*!< (@ 0x00004164) L3 Table Read Result Register 4 */ + + struct + { + __IM uint32_t LTHSRP3 : 32; /*!< [31..0] L3 Stream Read Part 3 */ + } FWLTHTRR4_b; + }; + + union + { + __IM uint32_t FWLTHTRR5; /*!< (@ 0x00004168) L3 Table Read Result Register 5 */ + + struct + { + __IM uint32_t LTHSRP4 : 32; /*!< [31..0] L3 Stream Read Part 4 */ + } FWLTHTRR5_b; + }; + + union + { + __IM uint32_t FWLTHTRR6; /*!< (@ 0x0000416C) L3 Table Read Result Register 6 */ + + struct + { + uint32_t : 16; + __IM uint32_t LTHMSDUNR : 4; /*!< [19..16] L3 MSDU Number Read */ + uint32_t : 11; + __IM uint32_t LTHMSDUVR : 1; /*!< [31..31] L3 MSDU Valid Read */ + } FWLTHTRR6_b; + }; + + union + { + __IM uint32_t FWLTHTRR7; /*!< (@ 0x00004170) L3 Table Read Result Register 7 */ + + struct + { + __IM uint32_t LTHFRERNR : 6; /*!< [5..0] L3 FRER Number Read */ + uint32_t : 9; + __IM uint32_t LTHFRERVR : 1; /*!< [15..15] L3 FRER Valid Read */ + __IM uint32_t LTHMTRNR : 5; /*!< [20..16] L3 MeTeR Number Read */ + uint32_t : 10; + __IM uint32_t LTHMTRVR : 1; /*!< [31..31] L3 MeTeR Valid Read */ + } FWLTHTRR7_b; + }; + + union + { + __IM uint32_t FWLTHTRR8; /*!< (@ 0x00004174) L3 Table Read Result Register 8 */ + + struct + { + __IM uint32_t LTHRNR : 8; /*!< [7..0] L3 Routing Number Read */ + uint32_t : 7; + __IM uint32_t LTHRVR : 1; /*!< [15..15] L3 Routing Valid Read */ + __IM uint32_t LTHSLVR : 7; /*!< [22..16] L3 Source Lock Vector Read */ + uint32_t : 9; + } FWLTHTRR8_b; + }; + __IM uint32_t RESERVED102[2]; + + union + { + __IM uint32_t FWLTHTRR90; /*!< (@ 0x00004180) L3 Table Read Result Register 90 */ + + struct + { + __IM uint32_t LTHCSDR : 7; /*!< [6..0] L3 CPU Sub-Destination Read */ + uint32_t : 25; + } FWLTHTRR90_b; + }; + __IM uint32_t RESERVED103[3]; + + union + { + __IM uint32_t FWLTHTRR10; /*!< (@ 0x00004190) L3 Table Read Result Register 10 */ + + struct + { + __IM uint32_t LTHDVR : 7; /*!< [6..0] L3 Destination Vector Read */ + uint32_t : 9; + __IM uint32_t LTHIPVR : 3; /*!< [18..16] L3 Internal Priority Value Read */ + __IM uint32_t LTHIPUR : 1; /*!< [19..19] L3 Internal Priority Update Read */ + __IM uint32_t LTHEMER : 1; /*!< [20..20] L3 Ethernet Mirroring Enable Read */ + __IM uint32_t LTHCMER : 1; /*!< [21..21] L3 CPU Mirroring Enable Read */ + uint32_t : 10; + } FWLTHTRR10_b; + }; + __IM uint32_t RESERVED104[291]; + + union + { + __IOM uint32_t FWMACHEC; /*!< (@ 0x00004620) MAC Hash Entry Configuration Register */ + + struct + { + __IOM uint32_t MACHMC : 11; /*!< [10..0] MAC Hash Maximum Collision */ + uint32_t : 5; + __IOM uint32_t MACHMUE : 12; /*!< [27..16] MAC Hash Maximum Unsecure Entry */ + uint32_t : 4; + } FWMACHEC_b; + }; + + union + { + __IOM uint32_t FWMACHC; /*!< (@ 0x00004624) MAC Hash Configuration Register */ + + struct + { + __IOM uint32_t MACHE : 11; /*!< [10..0] MAC Hash Equation */ + uint32_t : 21; + } FWMACHC_b; + }; + __IM uint32_t RESERVED105[2]; + + union + { + __IOM uint32_t FWMACTL0; /*!< (@ 0x00004630) MAC Table Learn Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t MACSLL : 1; /*!< [8..8] MAC Security Level Learn */ + __IOM uint32_t MACDEL : 1; /*!< [9..9] MAC Dynamic Entry Limit */ + __IOM uint32_t MACHLDL : 1; /*!< [10..10] MAC Hardware Learning Disable Learn */ + uint32_t : 5; + __IOM uint32_t MACED : 1; /*!< [16..16] MAC Entry Delete */ + uint32_t : 15; + } FWMACTL0_b; + }; + + union + { + __IOM uint32_t FWMACTL1; /*!< (@ 0x00004634) MAC Table Learn Register 1 */ + + struct + { + __IOM uint32_t MACMALP0 : 16; /*!< [15..0] MAC MAC address Learn Part 0 */ + uint32_t : 16; + } FWMACTL1_b; + }; + + union + { + __IOM uint32_t FWMACTL2; /*!< (@ 0x00004638) MAC Table Learn Register 2 */ + + struct + { + __IOM uint32_t MACMALP1 : 32; /*!< [31..0] MAC MAC address Learn Part 1 */ + } FWMACTL2_b; + }; + + union + { + __IOM uint32_t FWMACTL3; /*!< (@ 0x0000463C) MAC Table Learn Register 3 */ + + struct + { + __IOM uint32_t MACSSLVL : 7; /*!< [6..0] MAC Source Source Lock Vector Learn */ + uint32_t : 9; + __IOM uint32_t MACDSLVL : 7; /*!< [22..16] MAC Destination Source Lock Vector Learn */ + uint32_t : 9; + } FWMACTL3_b; + }; + + union + { + __IOM uint32_t FWMACTL40; /*!< (@ 0x00004640) MAC Table Learn Register 40 */ + + struct + { + __IOM uint32_t MACCSDL : 7; /*!< [6..0] MAC CPU Sub-Destination Learn */ + uint32_t : 25; + } FWMACTL40_b; + }; + __IM uint32_t RESERVED106[3]; + + union + { + __IOM uint32_t FWMACTL5; /*!< (@ 0x00004650) MAC Table Learn Register 5 */ + + struct + { + __IOM uint32_t MACDVL : 7; /*!< [6..0] MAC Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t MACIPVL : 3; /*!< [18..16] MAC Internal Priority Value Learn */ + __IOM uint32_t MACIPUL : 1; /*!< [19..19] MAC Internal Priority Update Learn */ + __IOM uint32_t MACEMEL : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Learn */ + __IOM uint32_t MACCMEL : 1; /*!< [21..21] MAC CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWMACTL5_b; + }; + + union + { + __IM uint32_t FWMACTLR; /*!< (@ 0x00004654) MAC Table Learn Result Register */ + + struct + { + __IM uint32_t MACLF : 1; /*!< [0..0] MAC Learn Fail */ + __IM uint32_t MACLSF : 1; /*!< [1..1] MAC Learn Security Fail */ + __IM uint32_t MACLEF : 1; /*!< [2..2] MAC Learn ECC Fail */ + __IM uint32_t MACLO : 1; /*!< [3..3] MAC Learn Overwrite */ + uint32_t : 12; + __IM uint32_t MACLCN : 10; /*!< [25..16] MAC Learn Collision Number */ + uint32_t : 5; + __IM uint32_t MACTL : 1; /*!< [31..31] MAC Table Learn */ + } FWMACTLR_b; + }; + __IM uint32_t RESERVED107[2]; + + union + { + __IOM uint32_t FWMACTIM; /*!< (@ 0x00004660) MAC Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t MACTIOG : 1; /*!< [0..0] MAC Table Initialization Ongoing */ + __IM uint32_t MACTR : 1; /*!< [1..1] MAC Table Ready */ + uint32_t : 30; + } FWMACTIM_b; + }; + + union + { + __IM uint32_t FWMACTEM; /*!< (@ 0x00004664) MAC Table Entry Monitoring Register */ + + struct + { + __IM uint32_t MACTEN : 11; /*!< [10..0] MAC Table Entry Number */ + uint32_t : 5; + __IM uint32_t MACTUEN : 11; /*!< [26..16] MAC Table Unsecure Entry Number */ + uint32_t : 5; + } FWMACTEM_b; + }; + __IM uint32_t RESERVED108[2]; + + union + { + __IOM uint32_t FWMACTS0; /*!< (@ 0x00004670) MAC Table Search Register 0 */ + + struct + { + __IOM uint32_t MACMASP0 : 16; /*!< [15..0] MAC MAC Address Search Part 0 */ + uint32_t : 16; + } FWMACTS0_b; + }; + + union + { + __IOM uint32_t FWMACTS1; /*!< (@ 0x00004674) MAC Table Search Register 1 */ + + struct + { + __IOM uint32_t MACMASP1 : 32; /*!< [31..0] MAC MAC Address Search Part 1 */ + } FWMACTS1_b; + }; + + union + { + __IOM uint32_t FWMACTSR0; /*!< (@ 0x00004678) MAC Table Search Result Register 0 */ + + struct + { + __IOM uint32_t MACSEF : 1; /*!< [0..0] MAC Search ECC Fail */ + __IM uint32_t MACSNF : 1; /*!< [1..1] MAC Search Not found */ + uint32_t : 6; + __IM uint32_t MACSLS : 1; /*!< [8..8] MAC Security Level Search */ + __IM uint32_t MACDES : 1; /*!< [9..9] MAC Dynamic Entry Search */ + __IM uint32_t MACHLDS : 1; /*!< [10..10] MAC Hardware Learning Disable Search */ + uint32_t : 5; + __IM uint32_t MACSCN : 10; /*!< [25..16] MAC Search Collision Number */ + uint32_t : 5; + __IM uint32_t MACTS : 1; /*!< [31..31] MAC Table Search */ + } FWMACTSR0_b; + }; + + union + { + __IM uint32_t FWMACTSR1; /*!< (@ 0x0000467C) MAC Table Search Result Register 1 */ + + struct + { + __IM uint32_t MACSSLVS : 7; /*!< [6..0] MAC Source Source Lock Vector Search */ + uint32_t : 9; + __IM uint32_t MACDSLVS : 7; /*!< [22..16] MAC Destination Source Lock Vector Search */ + uint32_t : 9; + } FWMACTSR1_b; + }; + + union + { + __IM uint32_t FWMACTSR20; /*!< (@ 0x00004680) MAC Table Search Result Register 20 */ + + struct + { + __IM uint32_t MACCSDS : 7; /*!< [6..0] MAC CPU Sub-Destination Search */ + uint32_t : 25; + } FWMACTSR20_b; + }; + __IM uint32_t RESERVED109[3]; + + union + { + __IM uint32_t FWMACTSR3; /*!< (@ 0x00004690) MAC Table Search Result Register 3 */ + + struct + { + __IM uint32_t MACDVS : 7; /*!< [6..0] MAC Destination Vector Search */ + uint32_t : 9; + __IM uint32_t MACIPVS : 3; /*!< [18..16] MAC Internal Priority Value Search */ + __IM uint32_t MACIPUS : 1; /*!< [19..19] MAC Internal Priority Update Search */ + __IM uint32_t MACEMES : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Search */ + __IM uint32_t MACCMES : 1; /*!< [21..21] MAC CPU Mirroring Enable Search */ + uint32_t : 10; + } FWMACTSR3_b; + }; + __IM uint32_t RESERVED110[3]; + + union + { + __IOM uint32_t FWMACTR; /*!< (@ 0x000046A0) MAC Table Read Register */ + + struct + { + __IOM uint32_t MACAR : 10; /*!< [9..0] MAC Address Read */ + uint32_t : 22; + } FWMACTR_b; + }; + + union + { + __IM uint32_t FWMACTRR0; /*!< (@ 0x000046A4) MAC Table Read Result Register 0 */ + + struct + { + __IM uint32_t MACEVR : 1; /*!< [0..0] MAC Entry Valid Read */ + __IM uint32_t MACREF : 1; /*!< [1..1] MAC Read ECC Fail */ + uint32_t : 29; + __IM uint32_t MACTR : 1; /*!< [31..31] MAC Table Read */ + } FWMACTRR0_b; + }; + + union + { + __IM uint32_t FWMACTRR1; /*!< (@ 0x000046A8) MAC Table Read Result Register 1 */ + + struct + { + uint32_t : 8; + __IM uint32_t MACSLR : 1; /*!< [8..8] MAC Security Level Read */ + __IM uint32_t MACDER : 1; /*!< [9..9] MAC Dynamic Entry Read */ + __IM uint32_t MACHLDR : 1; /*!< [10..10] MAC Hardware Learn Disable Read */ + __IM uint32_t MACABR : 1; /*!< [11..11] MAC Aging Bit Read */ + uint32_t : 20; + } FWMACTRR1_b; + }; + + union + { + __IM uint32_t FWMACTRR2; /*!< (@ 0x000046AC) MAC Table Read Result Register 2 */ + + struct + { + __IM uint32_t MACMARP0 : 16; /*!< [15..0] MAC MAC address Read Part 0 */ + uint32_t : 16; + } FWMACTRR2_b; + }; + + union + { + __IM uint32_t FWMACTRR3; /*!< (@ 0x000046B0) MAC Table Read Result Register 3 */ + + struct + { + __IM uint32_t MACMARP1 : 32; /*!< [31..0] MAC MAC address Read Part 1 */ + } FWMACTRR3_b; + }; + + union + { + __IM uint32_t FWMACTRR4; /*!< (@ 0x000046B4) MAC Table Read Result Register 4 */ + + struct + { + __IM uint32_t MACSSLVR : 7; /*!< [6..0] MAC Source Source Lock Vector Read */ + uint32_t : 9; + __IM uint32_t MACDSLVR : 7; /*!< [22..16] MAC Destination Source Lock Vector Read */ + uint32_t : 9; + } FWMACTRR4_b; + }; + __IM uint32_t RESERVED111[2]; + + union + { + __IM uint32_t FWMACTRR50; /*!< (@ 0x000046C0) MAC Table Read Result Register 50 */ + + struct + { + __IM uint32_t MACCSDR : 7; /*!< [6..0] MAC CPU Sub-Destination Read */ + uint32_t : 25; + } FWMACTRR50_b; + }; + __IM uint32_t RESERVED112[3]; + + union + { + __IM uint32_t FWMACTRR6; /*!< (@ 0x000046D0) MAC Table Read Result Register 6 */ + + struct + { + __IM uint32_t MACDVR : 7; /*!< [6..0] MAC Destination Vector Read */ + uint32_t : 9; + __IM uint32_t MACIPVR : 3; /*!< [18..16] MAC Internal Priority Value Read */ + __IM uint32_t MACIPUR : 1; /*!< [19..19] MAC Internal Priority Update Read */ + __IM uint32_t MACEMER : 1; /*!< [20..20] MAC Ethernet Mirroring Enable Read */ + __IM uint32_t MACCMER : 1; /*!< [21..21] MAC CPU Mirroring Enable Read */ + uint32_t : 10; + } FWMACTRR6_b; + }; + __IM uint32_t RESERVED113[107]; + + union + { + __IOM uint32_t FWMACAGUSPC; /*!< (@ 0x00004880) MAC Aging US Prescaler Configuration Register */ + + struct + { + __IOM uint32_t MACAGUSP : 10; /*!< [9..0] MAC Aging US prescaler */ + uint32_t : 22; + } FWMACAGUSPC_b; + }; + + union + { + __IOM uint32_t FWMACAGC; /*!< (@ 0x00004884) MAC Aging Configuration Register */ + + struct + { + __IOM uint32_t MACAGT : 16; /*!< [15..0] MAC Aging Time */ + __IOM uint32_t MACAGE : 1; /*!< [16..16] MAC Aging Enable */ + __IOM uint32_t MACAGSL : 1; /*!< [17..17] MAC Aging Security Level */ + __IOM uint32_t MACAGPM : 1; /*!< [18..18] MAC Aging Polling Mode */ + uint32_t : 5; + __IM uint32_t MACDES : 1; /*!< [24..24] MAC Dynamic Entry Suppression */ + uint32_t : 3; + __IM uint32_t MACAGOG : 1; /*!< [28..28] MAC Aging OnGoing */ + __IM uint32_t MACDESOG : 1; /*!< [29..29] MAC Dynamic Entry Suppression OnGoing */ + uint32_t : 2; + } FWMACAGC_b; + }; + + union + { + __IM uint32_t FWMACAGM0; /*!< (@ 0x00004888) MAC Aging Monitoring Register 0 */ + + struct + { + __IM uint32_t AGMACAP0 : 16; /*!< [15..0] Aged MAC Address Part 0 */ + uint32_t : 16; + } FWMACAGM0_b; + }; + + union + { + __IM uint32_t FWMACAGM1; /*!< (@ 0x0000488C) MAC Aging Monitoring Register 1 */ + + struct + { + __IM uint32_t AGMACAP1 : 32; /*!< [31..0] Aged MAC Address Part 1 */ + } FWMACAGM1_b; + }; + __IM uint32_t RESERVED114[28]; + + union + { + __IOM uint32_t FWVLANTEC; /*!< (@ 0x00004900) VLAN Table Entry Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t VLANTMUE : 13; /*!< [28..16] VLAN Table Maximum Unsecure Entry */ + uint32_t : 3; + } FWVLANTEC_b; + }; + __IM uint32_t RESERVED115[3]; + + union + { + __IOM uint32_t FWVLANTL0; /*!< (@ 0x00004910) VLAN Table Learn Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t VLANSLL : 1; /*!< [8..8] VLAN Security Level Learn */ + uint32_t : 1; + __IOM uint32_t VLANHLDL : 1; /*!< [10..10] VLAN Hardware Learning Disable Learn */ + uint32_t : 5; + __IOM uint32_t VLANED : 1; /*!< [16..16] VLAN Entry Delete */ + uint32_t : 15; + } FWVLANTL0_b; + }; + + union + { + __IOM uint32_t FWVLANTL1; /*!< (@ 0x00004914) VLAN Table Learn Register 1 */ + + struct + { + __IOM uint32_t VLANVIDL : 12; /*!< [11..0] VLAN VID Learn */ + uint32_t : 20; + } FWVLANTL1_b; + }; + + union + { + __IOM uint32_t FWVLANTL2; /*!< (@ 0x00004918) VLAN Table Learn Register 2 */ + + struct + { + __IOM uint32_t VLANSLVL : 7; /*!< [6..0] VLAN Source Lock Vector Learn */ + uint32_t : 25; + } FWVLANTL2_b; + }; + __IM uint32_t RESERVED116; + + union + { + __IOM uint32_t FWVLANTL30; /*!< (@ 0x00004920) VLAN Table Learn Register 30 */ + + struct + { + __IOM uint32_t VLANCSDL : 7; /*!< [6..0] VLAN CPU Sub-Destination Learn */ + uint32_t : 25; + } FWVLANTL30_b; + }; + __IM uint32_t RESERVED117[3]; + + union + { + __IOM uint32_t FWVLANTL4; /*!< (@ 0x00004930) VLAN Table Learn Register 4 */ + + struct + { + __IOM uint32_t VLANDVL : 7; /*!< [6..0] VLAN Destination Vector Learn */ + uint32_t : 9; + __IOM uint32_t VLANIPVL : 3; /*!< [18..16] VLAN Internal Priority Value Learn */ + __IOM uint32_t VLANIPUL : 1; /*!< [19..19] VLAN Internal Priority Update Learn */ + __IOM uint32_t VLANEMEL : 1; /*!< [20..20] VLAN Ethernet Mirroring Enable Learn */ + __IOM uint32_t VLANCMEL : 1; /*!< [21..21] VLAN CPU Mirroring Enable Learn */ + uint32_t : 10; + } FWVLANTL4_b; + }; + + union + { + __IM uint32_t FWVLANTLR; /*!< (@ 0x00004934) VLAN Table Learn Result Register */ + + struct + { + __IM uint32_t VLANLF : 1; /*!< [0..0] VLAN Learn Fail */ + __IM uint32_t VLANLSF : 1; /*!< [1..1] VLAN Learn Security Fail */ + __IM uint32_t VLANLEF : 1; /*!< [2..2] VLAN Learn ECC Fail */ + __IM uint32_t VLANLO : 1; /*!< [3..3] VLAN Learn Overwrite */ + uint32_t : 27; + __IM uint32_t VLANTL : 1; /*!< [31..31] VLAN Table Learn */ + } FWVLANTLR_b; + }; + __IM uint32_t RESERVED118[2]; + + union + { + __IOM uint32_t FWVLANTIM; /*!< (@ 0x00004940) VLAN Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t VLANTIOG : 1; /*!< [0..0] VLAN Table Initialization Ongoing */ + __IM uint32_t VLANTR : 1; /*!< [1..1] VLAN Table Ready */ + uint32_t : 30; + } FWVLANTIM_b; + }; + + union + { + __IM uint32_t FWVLANTEM; /*!< (@ 0x00004944) VLAN Table Entry Monitoring Register */ + + struct + { + __IM uint32_t VLANTEN : 13; /*!< [12..0] VLAN Table Entry Number */ + uint32_t : 3; + __IM uint32_t VLANTUEN : 13; /*!< [28..16] VLAN Table Unsecure Entry Number */ + uint32_t : 3; + } FWVLANTEM_b; + }; + __IM uint32_t RESERVED119[2]; + + union + { + __IOM uint32_t FWVLANTS; /*!< (@ 0x00004950) VLAN Table Search Register */ + + struct + { + __IOM uint32_t VLANVIDS : 12; /*!< [11..0] VLAN VID Search */ + uint32_t : 20; + } FWVLANTS_b; + }; + + union + { + __IM uint32_t FWVLANTSR0; /*!< (@ 0x00004954) VLAN Table Search Result Register 0 */ + + struct + { + __IM uint32_t VLANSEF : 1; /*!< [0..0] VLAN Search ECC Fail */ + __IM uint32_t VLANSNF : 1; /*!< [1..1] VLAN Search Not found */ + uint32_t : 6; + __IM uint32_t VLANSLS : 1; /*!< [8..8] VLAN Security Level Search */ + uint32_t : 1; + __IM uint32_t VLANHLDS : 1; /*!< [10..10] VLAN Hardware Learning Disable Search */ + uint32_t : 20; + __IM uint32_t VLANTS : 1; /*!< [31..31] VLAN Table Search */ + } FWVLANTSR0_b; + }; + + union + { + __IM uint32_t FWVLANTSR1; /*!< (@ 0x00004958) VLAN Table Search Result Register 1 */ + + struct + { + __IM uint32_t VLANSLVS : 7; /*!< [6..0] VLAN Source Lock Vector Search */ + uint32_t : 25; + } FWVLANTSR1_b; + }; + __IM uint32_t RESERVED120; + + union + { + __IM uint32_t FWVLANTSR20; /*!< (@ 0x00004960) VLAN Table Search Result Register 20 */ + + struct + { + __IM uint32_t VLANCSDS : 7; /*!< [6..0] VLAN CPU Sub-Destination Search */ + uint32_t : 25; + } FWVLANTSR20_b; + }; + __IM uint32_t RESERVED121[3]; + + union + { + __IM uint32_t FWVLANTSR3; /*!< (@ 0x00004970) VLAN Table Search Result Register 3 */ + + struct + { + __IM uint32_t VLANDVS : 7; /*!< [6..0] VLAN Destination Vector Search */ + uint32_t : 9; + __IM uint32_t VLANIPVS : 3; /*!< [18..16] VLAN Internal Priority Value Search */ + __IM uint32_t VLANIPUS : 1; /*!< [19..19] VLAN Internal Priority Update Search */ + __IM uint32_t VLANEMES : 1; /*!< [20..20] VLAN Ethernet Mirroring Enable Search */ + __IM uint32_t VLANCMES : 1; /*!< [21..21] VLAN CPU Mirroring Enable Search */ + uint32_t : 10; + } FWVLANTSR3_b; + }; + __IM uint32_t RESERVED122[35]; + + union + { + __IOM uint32_t FWPBFC0; /*!< (@ 0x00004A00) Port Based Forwarding Configuration Register + * 0 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC0_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC00; /*!< (@ 0x00004A04) Port Based Forwarding CSD Configuration Register + * 00 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC00_b; + }; + __IM uint32_t RESERVED123[2]; + + union + { + __IOM uint32_t FWPBFC1; /*!< (@ 0x00004A10) Port Based Forwarding Configuration Register + * 1 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC1_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC01; /*!< (@ 0x00004A14) Port Based Forwarding CSD Configuration Register + * 01 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC01_b; + }; + __IM uint32_t RESERVED124[2]; + + union + { + __IOM uint32_t FWPBFC2; /*!< (@ 0x00004A20) Port Based Forwarding Configuration Register + * 2 */ + + struct + { + __IOM uint32_t PBDV : 7; /*!< [6..0] Port Based Destination Vector */ + uint32_t : 9; + __IOM uint32_t PBIPV : 3; /*!< [18..16] Port Based Internal Priority Value */ + __IOM uint32_t PBIPU : 1; /*!< [19..19] Port Based Internal Priority Update */ + __IOM uint32_t PBEME : 1; /*!< [20..20] Port Based Ethernet Mirroring Enabled */ + __IOM uint32_t PBCME : 1; /*!< [21..21] Port Based CPU Mirroring Enabled */ + __IOM uint32_t PBSL : 1; /*!< [22..22] Port Based Security Level */ + __IOM uint32_t IP4PDE : 1; /*!< [23..23] IPv4 Priority Decode Enable */ + __IOM uint32_t IP4PDM : 1; /*!< [24..24] IPv4 Priority Decode Mode */ + __IOM uint32_t IP6PDE : 1; /*!< [25..25] IPv6 Priority Decode Enable */ + __IOM uint32_t FAIFP : 1; /*!< [26..26] Force All Input Frame Priority Enable */ + uint32_t : 5; + } FWPBFC2_b; + }; + + union + { + __IOM uint32_t FWPBFCSDC02; /*!< (@ 0x00004A24) Port Based Forwarding CSD Configuration Register + * 02 */ + + struct + { + __IOM uint32_t PBCSD : 7; /*!< [6..0] Port Based CPU Sub Destination */ + uint32_t : 25; + } FWPBFCSDC02_b; + }; + __IM uint32_t RESERVED125[246]; + + union + { + __IOM uint32_t FWL23URL0; /*!< (@ 0x00004E00) Layer 2/Layer 3 Update Rule Learn Register 0 */ + + struct + { + __IOM uint32_t L23URNL : 8; /*!< [7..0] Layer 2/Layer 3 Update Routing Number Learn */ + uint32_t : 8; + __IOM uint32_t L23URPVL : 7; /*!< [22..16] Layer 2/Layer 3 Update Routing Port Valid Learn */ + uint32_t : 9; + } FWL23URL0_b; + }; + + union + { + __IOM uint32_t FWL23URL1; /*!< (@ 0x00004E04) Layer 2/Layer 3 Update Rule Learn Register 1 */ + + struct + { + __IOM uint32_t L23UMDALP0 : 16; /*!< [15..0] Layer 2/Layer 3 Update MAC Destination Address Learn + * Part 0 */ + __IOM uint32_t L23UTTLUL : 1; /*!< [16..16] Layer 2/Layer 3 Update Time To Live Update Learn */ + __IOM uint32_t L23UMDAUL : 1; /*!< [17..17] Layer 2/Layer 3 Update MAC Destination Address Update + * Learn */ + __IOM uint32_t L23UMSAUL : 1; /*!< [18..18] Layer 2/Layer 3 Update MAC Source Address Update Learn */ + __IOM uint32_t L23UCVIDUL : 1; /*!< [19..19] Layer 2/Layer 3 Update C-TAG VID Update Learn */ + __IOM uint32_t L23UCPCPUL : 1; /*!< [20..20] Layer 2/Layer 3 Update C-TAG PCP Update Learn */ + __IOM uint32_t L23UCDEIUL : 1; /*!< [21..21] Layer 2/Layer 3 Update C-TAG DEI Update Learn */ + __IOM uint32_t L23USVIDUL : 1; /*!< [22..22] Layer 2/Layer 3 Update S-TAG VID Update Learn */ + __IOM uint32_t L23USPCPUL : 1; /*!< [23..23] Layer 2/Layer 3 Update S-TAG PCP Update Learn */ + __IOM uint32_t L23USDEIUL : 1; /*!< [24..24] Layer 2/Layer 3 Update S-TAG DEI Update Learn */ + __IOM uint32_t L23URTUL : 2; /*!< [26..25] Layer 2/Layer 3 Update R-TAG Update Learn */ + uint32_t : 5; + } FWL23URL1_b; + }; + + union + { + __IOM uint32_t FWL23URL2; /*!< (@ 0x00004E08) Layer 2/Layer 3 Update Rule Learn Register 2 */ + + struct + { + __IOM uint32_t L23UMDALP1 : 32; /*!< [31..0] Layer 2/Layer 3 Update MAC Destination Address Learn + * Part 1 */ + } FWL23URL2_b; + }; + + union + { + __IOM uint32_t FWL23URL3; /*!< (@ 0x00004E0C) Layer 2/Layer 3 Update Rule Learn Register 3 */ + + struct + { + __IOM uint32_t L23UCVIDL : 12; /*!< [11..0] Layer 2/Layer 3 Update C-TAG VID Learn */ + __IOM uint32_t L23UCPCPL : 3; /*!< [14..12] Layer 2/Layer 3 Update C-TAG PCP Learn */ + __IOM uint32_t L23UCDEIL : 1; /*!< [15..15] Layer 2/Layer 3 Update C-TAG DEI Learn */ + __IOM uint32_t L23USVIDL : 12; /*!< [27..16] Layer 2/Layer 3 Update S-TAG VID Learn */ + __IOM uint32_t L23USPCPL : 3; /*!< [30..28] Layer 2/Layer 3 Update S-TAG PCP Learn */ + __IOM uint32_t L23USDEIL : 1; /*!< [31..31] Layer 2/Layer 3 Update S-TAG DEI Learn */ + } FWL23URL3_b; + }; + + union + { + __IM uint32_t FWL23URLR; /*!< (@ 0x00004E10) Layer 2/Layer 3 Update Rule Learn Result Register */ + + struct + { + __IM uint32_t L23ULF : 1; /*!< [0..0] Layer 2/Layer 3 Update Learn Fail */ + uint32_t : 30; + __IM uint32_t L23URL : 1; /*!< [31..31] Layer 2/Layer 3 Update Rule Learn */ + } FWL23URLR_b; + }; + __IM uint32_t RESERVED126[3]; + + union + { + __IOM uint32_t FWL23UTIM; /*!< (@ 0x00004E20) Layer 2/Layer 3 Update Table Initialization Monitoring + * Register */ + + struct + { + __IOM uint32_t L23UTIOG : 1; /*!< [0..0] Layer 2/Layer 3 Update Table Initialization Ongoing */ + __IM uint32_t L23UTR : 1; /*!< [1..1] Layer 2/Layer 3 Update Table Ready */ + uint32_t : 30; + } FWL23UTIM_b; + }; + __IM uint32_t RESERVED127[3]; + + union + { + __IOM uint32_t FWL23URR; /*!< (@ 0x00004E30) Layer 2/Layer 3 Update Rule Read Register */ + + struct + { + __IOM uint32_t L23RNR : 8; /*!< [7..0] Layer 2/Layer 3 Routing Number Read */ + uint32_t : 24; + } FWL23URR_b; + }; + + union + { + __IM uint32_t FWL23URRR0; /*!< (@ 0x00004E34) Layer 2/Layer 3 Update Rule Read Result Register + * 0 */ + + struct + { + __IM uint32_t L23URPVR : 7; /*!< [6..0] Layer 2/Layer 3 Update Routing Port Valid Read */ + uint32_t : 9; + __IM uint32_t L23UREF : 1; /*!< [16..16] Layer 2/Layer 3 Update Read ECC Fail */ + uint32_t : 14; + __IM uint32_t L23URR : 1; /*!< [31..31] Layer 2/Layer 3 Update Rule Read */ + } FWL23URRR0_b; + }; + + union + { + __IM uint32_t FWL23URRR1; /*!< (@ 0x00004E38) Layer 2/Layer 3 Update Rule Read Result Register + * 1 */ + + struct + { + __IM uint32_t L23UMDARP0 : 16; /*!< [15..0] Layer 2/Layer 3 MAC Destination Address Read Part 0 */ + __IM uint32_t L23UTTLUR : 1; /*!< [16..16] Layer 2/Layer 3 Time To Live Update Read */ + __IM uint32_t L23UMDAUR : 1; /*!< [17..17] Layer 2/Layer 3 MAC Destination Address Update Read */ + __IM uint32_t L23UMSAUR : 1; /*!< [18..18] Layer 2/Layer 3 MAC Source Address Update Read */ + __IM uint32_t L23UCVIDUR : 1; /*!< [19..19] Layer 2/Layer 3 C-TAG VID Update Read */ + __IM uint32_t L23UCPCPUR : 1; /*!< [20..20] Layer 2/Layer 3 C-TAG PCP Update Read */ + __IM uint32_t L23UCDEIUR : 1; /*!< [21..21] Layer 2/Layer 3 C-TAG DEI Update Read */ + __IM uint32_t L23USVIDUR : 1; /*!< [22..22] Layer 2/Layer 3 S-TAG VID Update Read */ + __IM uint32_t L23USPCPUR : 1; /*!< [23..23] Layer 2/Layer 3 S-TAG PCP Update Read */ + __IM uint32_t L23USDEIUR : 1; /*!< [24..24] Layer 2/Layer 3 S-TAG DEI Update Read */ + __IM uint32_t L23URTUR : 2; /*!< [26..25] Layer 2/Layer 3 R-TAG Update Read */ + uint32_t : 5; + } FWL23URRR1_b; + }; + + union + { + __IM uint32_t FWL23URRR2; /*!< (@ 0x00004E3C) Layer 2/Layer 3 Update Rule Read Result Register + * 2 */ + + struct + { + __IM uint32_t L23UMDARP1 : 32; /*!< [31..0] Layer 2/Layer 3 MAC Destination Address Read Part 1 */ + } FWL23URRR2_b; + }; + + union + { + __IM uint32_t FWL23URRR3; /*!< (@ 0x00004E40) Layer 2/Layer 3 Update Rule Read Result Register + * 3 */ + + struct + { + __IM uint32_t L23UCVIDR : 12; /*!< [11..0] Layer 2/Layer 3 Update MAC C-TAG VID Read */ + __IM uint32_t L23UCPCPR : 3; /*!< [14..12] Layer 2/Layer 3 Update MAC C-TAG PCP Read */ + __IM uint32_t L23UCDEIR : 1; /*!< [15..15] Layer 2/Layer 3 Update MAC C-TAG DEI Read */ + __IM uint32_t L23USVIDR : 12; /*!< [27..16] Layer 2/Layer 3 Update MAC S-TAG VID Read */ + __IM uint32_t L23USPCPR : 3; /*!< [30..28] Layer 2/Layer 3 Update MAC S-TAG PCP Read */ + __IM uint32_t L23USDEIR : 1; /*!< [31..31] Layer 2/Layer 3 Update MAC S-TAG DEI Read */ + } FWL23URRR3_b; + }; + __IM uint32_t RESERVED128[47]; + + union + { + __IOM uint32_t FWL23URMC0; /*!< (@ 0x00004F00) Layer 2/Layer 3 Update ReMapping Configuration + * Register 0 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC0_b; + }; + + union + { + __IOM uint32_t FWL23URMC1; /*!< (@ 0x00004F04) Layer 2/Layer 3 Update ReMapping Configuration + * Register 1 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC1_b; + }; + + union + { + __IOM uint32_t FWL23URMC2; /*!< (@ 0x00004F08) Layer 2/Layer 3 Update ReMapping Configuration + * Register 2 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC2_b; + }; + + union + { + __IOM uint32_t FWL23URMC3; /*!< (@ 0x00004F0C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 3 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC3_b; + }; + + union + { + __IOM uint32_t FWL23URMC4; /*!< (@ 0x00004F10) Layer 2/Layer 3 Update ReMapping Configuration + * Register 4 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC4_b; + }; + + union + { + __IOM uint32_t FWL23URMC5; /*!< (@ 0x00004F14) Layer 2/Layer 3 Update ReMapping Configuration + * Register 5 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC5_b; + }; + + union + { + __IOM uint32_t FWL23URMC6; /*!< (@ 0x00004F18) Layer 2/Layer 3 Update ReMapping Configuration + * Register 6 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC6_b; + }; + + union + { + __IOM uint32_t FWL23URMC7; /*!< (@ 0x00004F1C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 7 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC7_b; + }; + + union + { + __IOM uint32_t FWL23URMC8; /*!< (@ 0x00004F20) Layer 2/Layer 3 Update ReMapping Configuration + * Register 8 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC8_b; + }; + + union + { + __IOM uint32_t FWL23URMC9; /*!< (@ 0x00004F24) Layer 2/Layer 3 Update ReMapping Configuration + * Register 9 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC9_b; + }; + + union + { + __IOM uint32_t FWL23URMC10; /*!< (@ 0x00004F28) Layer 2/Layer 3 Update ReMapping Configuration + * Register 10 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC10_b; + }; + + union + { + __IOM uint32_t FWL23URMC11; /*!< (@ 0x00004F2C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 11 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC11_b; + }; + + union + { + __IOM uint32_t FWL23URMC12; /*!< (@ 0x00004F30) Layer 2/Layer 3 Update ReMapping Configuration + * Register 12 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC12_b; + }; + + union + { + __IOM uint32_t FWL23URMC13; /*!< (@ 0x00004F34) Layer 2/Layer 3 Update ReMapping Configuration + * Register 13 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC13_b; + }; + + union + { + __IOM uint32_t FWL23URMC14; /*!< (@ 0x00004F38) Layer 2/Layer 3 Update ReMapping Configuration + * Register 14 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC14_b; + }; + + union + { + __IOM uint32_t FWL23URMC15; /*!< (@ 0x00004F3C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 15 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC15_b; + }; + + union + { + __IOM uint32_t FWL23URMC16; /*!< (@ 0x00004F40) Layer 2/Layer 3 Update ReMapping Configuration + * Register 16 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC16_b; + }; + + union + { + __IOM uint32_t FWL23URMC17; /*!< (@ 0x00004F44) Layer 2/Layer 3 Update ReMapping Configuration + * Register 17 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC17_b; + }; + + union + { + __IOM uint32_t FWL23URMC18; /*!< (@ 0x00004F48) Layer 2/Layer 3 Update ReMapping Configuration + * Register 18 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC18_b; + }; + + union + { + __IOM uint32_t FWL23URMC19; /*!< (@ 0x00004F4C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 19 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC19_b; + }; + + union + { + __IOM uint32_t FWL23URMC20; /*!< (@ 0x00004F50) Layer 2/Layer 3 Update ReMapping Configuration + * Register 20 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC20_b; + }; + + union + { + __IOM uint32_t FWL23URMC21; /*!< (@ 0x00004F54) Layer 2/Layer 3 Update ReMapping Configuration + * Register 21 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC21_b; + }; + + union + { + __IOM uint32_t FWL23URMC22; /*!< (@ 0x00004F58) Layer 2/Layer 3 Update ReMapping Configuration + * Register 22 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC22_b; + }; + + union + { + __IOM uint32_t FWL23URMC23; /*!< (@ 0x00004F5C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 23 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC23_b; + }; + + union + { + __IOM uint32_t FWL23URMC24; /*!< (@ 0x00004F60) Layer 2/Layer 3 Update ReMapping Configuration + * Register 24 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC24_b; + }; + + union + { + __IOM uint32_t FWL23URMC25; /*!< (@ 0x00004F64) Layer 2/Layer 3 Update ReMapping Configuration + * Register 25 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC25_b; + }; + + union + { + __IOM uint32_t FWL23URMC26; /*!< (@ 0x00004F68) Layer 2/Layer 3 Update ReMapping Configuration + * Register 26 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC26_b; + }; + + union + { + __IOM uint32_t FWL23URMC27; /*!< (@ 0x00004F6C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 27 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC27_b; + }; + + union + { + __IOM uint32_t FWL23URMC28; /*!< (@ 0x00004F70) Layer 2/Layer 3 Update ReMapping Configuration + * Register 28 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC28_b; + }; + + union + { + __IOM uint32_t FWL23URMC29; /*!< (@ 0x00004F74) Layer 2/Layer 3 Update ReMapping Configuration + * Register 29 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC29_b; + }; + + union + { + __IOM uint32_t FWL23URMC30; /*!< (@ 0x00004F78) Layer 2/Layer 3 Update ReMapping Configuration + * Register 30 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC30_b; + }; + + union + { + __IOM uint32_t FWL23URMC31; /*!< (@ 0x00004F7C) Layer 2/Layer 3 Update ReMapping Configuration + * Register 31 */ + + struct + { + __IOM uint32_t RMRN : 8; /*!< [7..0] ReMaping Rule Number */ + uint32_t : 4; + __IOM uint32_t RMDPN : 3; /*!< [14..12] ReMaping Destination Port Number */ + uint32_t : 1; + __IOM uint32_t RMNRN : 8; /*!< [23..16] ReMaping New Rule Number */ + uint32_t : 4; + __IOM uint32_t RME : 1; /*!< [28..28] ReMaping Enable */ + uint32_t : 3; + } FWL23URMC31_b; + }; + __IM uint32_t RESERVED129[32]; + + union + { + __IOM uint32_t FWPMFGC0; /*!< (@ 0x00005000) PSFP MSDU Filter Global Configuration Register + * 0 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC0_b; + }; + + union + { + __IOM uint32_t FWPMFGC1; /*!< (@ 0x00005004) PSFP MSDU Filter Global Configuration Register + * 1 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC1_b; + }; + + union + { + __IOM uint32_t FWPMFGC2; /*!< (@ 0x00005008) PSFP MSDU Filter Global Configuration Register + * 2 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC2_b; + }; + + union + { + __IOM uint32_t FWPMFGC3; /*!< (@ 0x0000500C) PSFP MSDU Filter Global Configuration Register + * 3 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC3_b; + }; + + union + { + __IOM uint32_t FWPMFGC4; /*!< (@ 0x00005010) PSFP MSDU Filter Global Configuration Register + * 4 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC4_b; + }; + + union + { + __IOM uint32_t FWPMFGC5; /*!< (@ 0x00005014) PSFP MSDU Filter Global Configuration Register + * 5 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC5_b; + }; + + union + { + __IOM uint32_t FWPMFGC6; /*!< (@ 0x00005018) PSFP MSDU Filter Global Configuration Register + * 6 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC6_b; + }; + + union + { + __IOM uint32_t FWPMFGC7; /*!< (@ 0x0000501C) PSFP MSDU Filter Global Configuration Register + * 7 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC7_b; + }; + + union + { + __IOM uint32_t FWPMFGC8; /*!< (@ 0x00005020) PSFP MSDU Filter Global Configuration Register + * 8 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC8_b; + }; + + union + { + __IOM uint32_t FWPMFGC9; /*!< (@ 0x00005024) PSFP MSDU Filter Global Configuration Register + * 9 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC9_b; + }; + + union + { + __IOM uint32_t FWPMFGC10; /*!< (@ 0x00005028) PSFP MSDU Filter Global Configuration Register + * 10 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC10_b; + }; + + union + { + __IOM uint32_t FWPMFGC11; /*!< (@ 0x0000502C) PSFP MSDU Filter Global Configuration Register + * 11 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC11_b; + }; + + union + { + __IOM uint32_t FWPMFGC12; /*!< (@ 0x00005030) PSFP MSDU Filter Global Configuration Register + * 12 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC12_b; + }; + + union + { + __IOM uint32_t FWPMFGC13; /*!< (@ 0x00005034) PSFP MSDU Filter Global Configuration Register + * 13 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC13_b; + }; + + union + { + __IOM uint32_t FWPMFGC14; /*!< (@ 0x00005038) PSFP MSDU Filter Global Configuration Register + * 14 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC14_b; + }; + + union + { + __IOM uint32_t FWPMFGC15; /*!< (@ 0x0000503C) PSFP MSDU Filter Global Configuration Register + * 15 */ + + struct + { + __IOM uint32_t MSDUV : 16; /*!< [15..0] MSDU Value */ + uint32_t : 15; + __IOM uint32_t MFM : 1; /*!< [31..31] MSDU Filter Mode */ + } FWPMFGC15_b; + }; + __IM uint32_t RESERVED130[368]; + + union + { + __IOM uint32_t FWPMTRFC0; /*!< (@ 0x00005600) PSFP Meter Filter Configuration Register 0 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC0_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC0; /*!< (@ 0x00005604) PSFP Meter CBS Configuration Register 0 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC0_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC0; /*!< (@ 0x00005608) PSFP Meter CIR Configuration Register 0 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC0_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC0; /*!< (@ 0x0000560C) PSFP Meter EBS Configuration Register 0 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC0_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC0; /*!< (@ 0x00005610) PSFP Meter EIR Configuration Register 0 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC0_b; + }; + + union + { + __IM uint32_t FWPMTRFM0; /*!< (@ 0x00005614) PSFP Meter Filter Monitoring Register 0 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM0_b; + }; + __IM uint32_t RESERVED131[2]; + + union + { + __IOM uint32_t FWPMTRFC1; /*!< (@ 0x00005620) PSFP Meter Filter Configuration Register 1 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC1_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC1; /*!< (@ 0x00005624) PSFP Meter CBS Configuration Register 1 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC1_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC1; /*!< (@ 0x00005628) PSFP Meter CIR Configuration Register 1 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC1_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC1; /*!< (@ 0x0000562C) PSFP Meter EBS Configuration Register 1 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC1_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC1; /*!< (@ 0x00005630) PSFP Meter EIR Configuration Register 1 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC1_b; + }; + + union + { + __IM uint32_t FWPMTRFM1; /*!< (@ 0x00005634) PSFP Meter Filter Monitoring Register 1 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM1_b; + }; + __IM uint32_t RESERVED132[2]; + + union + { + __IOM uint32_t FWPMTRFC2; /*!< (@ 0x00005640) PSFP Meter Filter Configuration Register 2 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC2_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC2; /*!< (@ 0x00005644) PSFP Meter CBS Configuration Register 2 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC2_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC2; /*!< (@ 0x00005648) PSFP Meter CIR Configuration Register 2 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC2_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC2; /*!< (@ 0x0000564C) PSFP Meter EBS Configuration Register 2 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC2_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC2; /*!< (@ 0x00005650) PSFP Meter EIR Configuration Register 2 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC2_b; + }; + + union + { + __IM uint32_t FWPMTRFM2; /*!< (@ 0x00005654) PSFP Meter Filter Monitoring Register 2 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM2_b; + }; + __IM uint32_t RESERVED133[2]; + + union + { + __IOM uint32_t FWPMTRFC3; /*!< (@ 0x00005660) PSFP Meter Filter Configuration Register 3 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC3_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC3; /*!< (@ 0x00005664) PSFP Meter CBS Configuration Register 3 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC3_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC3; /*!< (@ 0x00005668) PSFP Meter CIR Configuration Register 3 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC3_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC3; /*!< (@ 0x0000566C) PSFP Meter EBS Configuration Register 3 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC3_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC3; /*!< (@ 0x00005670) PSFP Meter EIR Configuration Register 3 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC3_b; + }; + + union + { + __IM uint32_t FWPMTRFM3; /*!< (@ 0x00005674) PSFP Meter Filter Monitoring Register 3 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM3_b; + }; + __IM uint32_t RESERVED134[2]; + + union + { + __IOM uint32_t FWPMTRFC4; /*!< (@ 0x00005680) PSFP Meter Filter Configuration Register 4 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC4_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC4; /*!< (@ 0x00005684) PSFP Meter CBS Configuration Register 4 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC4_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC4; /*!< (@ 0x00005688) PSFP Meter CIR Configuration Register 4 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC4_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC4; /*!< (@ 0x0000568C) PSFP Meter EBS Configuration Register 4 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC4_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC4; /*!< (@ 0x00005690) PSFP Meter EIR Configuration Register 4 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC4_b; + }; + + union + { + __IM uint32_t FWPMTRFM4; /*!< (@ 0x00005694) PSFP Meter Filter Monitoring Register 4 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM4_b; + }; + __IM uint32_t RESERVED135[2]; + + union + { + __IOM uint32_t FWPMTRFC5; /*!< (@ 0x000056A0) PSFP Meter Filter Configuration Register 5 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC5_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC5; /*!< (@ 0x000056A4) PSFP Meter CBS Configuration Register 5 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC5_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC5; /*!< (@ 0x000056A8) PSFP Meter CIR Configuration Register 5 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC5_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC5; /*!< (@ 0x000056AC) PSFP Meter EBS Configuration Register 5 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC5_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC5; /*!< (@ 0x000056B0) PSFP Meter EIR Configuration Register 5 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC5_b; + }; + + union + { + __IM uint32_t FWPMTRFM5; /*!< (@ 0x000056B4) PSFP Meter Filter Monitoring Register 5 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM5_b; + }; + __IM uint32_t RESERVED136[2]; + + union + { + __IOM uint32_t FWPMTRFC6; /*!< (@ 0x000056C0) PSFP Meter Filter Configuration Register 6 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC6_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC6; /*!< (@ 0x000056C4) PSFP Meter CBS Configuration Register 6 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC6_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC6; /*!< (@ 0x000056C8) PSFP Meter CIR Configuration Register 6 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC6_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC6; /*!< (@ 0x000056CC) PSFP Meter EBS Configuration Register 6 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC6_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC6; /*!< (@ 0x000056D0) PSFP Meter EIR Configuration Register 6 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC6_b; + }; + + union + { + __IM uint32_t FWPMTRFM6; /*!< (@ 0x000056D4) PSFP Meter Filter Monitoring Register 6 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM6_b; + }; + __IM uint32_t RESERVED137[2]; + + union + { + __IOM uint32_t FWPMTRFC7; /*!< (@ 0x000056E0) PSFP Meter Filter Configuration Register 7 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC7_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC7; /*!< (@ 0x000056E4) PSFP Meter CBS Configuration Register 7 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC7_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC7; /*!< (@ 0x000056E8) PSFP Meter CIR Configuration Register 7 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC7_b; + }; + + union + { + __IOM uint32_t FWPMTREBSC7; /*!< (@ 0x000056EC) PSFP Meter EBS Configuration Register 7 */ + + struct + { + __IOM uint32_t EBS : 18; /*!< [17..0] EBS */ + uint32_t : 14; + } FWPMTREBSC7_b; + }; + + union + { + __IOM uint32_t FWPMTREIRC7; /*!< (@ 0x000056F0) PSFP Meter EIR Configuration Register 7 */ + + struct + { + __IOM uint32_t EIR : 20; /*!< [19..0] EIR */ + uint32_t : 12; + } FWPMTREIRC7_b; + }; + + union + { + __IM uint32_t FWPMTRFM7; /*!< (@ 0x000056F4) PSFP Meter Filter Monitoring Register 7 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM7_b; + }; + __IM uint32_t RESERVED138[2]; + + union + { + __IOM uint32_t FWPMTRFC8; /*!< (@ 0x00005700) PSFP Meter Filter Configuration Register 8 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC8_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC8; /*!< (@ 0x00005704) PSFP Meter CBS Configuration Register 8 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC8_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC8; /*!< (@ 0x00005708) PSFP Meter CIR Configuration Register 8 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC8_b; + }; + __IM uint32_t RESERVED139[2]; + + union + { + __IM uint32_t FWPMTRFM8; /*!< (@ 0x00005714) PSFP Meter Filter Monitoring Register 8 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM8_b; + }; + __IM uint32_t RESERVED140[2]; + + union + { + __IOM uint32_t FWPMTRFC9; /*!< (@ 0x00005720) PSFP Meter Filter Configuration Register 9 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC9_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC9; /*!< (@ 0x00005724) PSFP Meter CBS Configuration Register 9 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC9_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC9; /*!< (@ 0x00005728) PSFP Meter CIR Configuration Register 9 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC9_b; + }; + __IM uint32_t RESERVED141[2]; + + union + { + __IM uint32_t FWPMTRFM9; /*!< (@ 0x00005734) PSFP Meter Filter Monitoring Register 9 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM9_b; + }; + __IM uint32_t RESERVED142[2]; + + union + { + __IOM uint32_t FWPMTRFC10; /*!< (@ 0x00005740) PSFP Meter Filter Configuration Register 10 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC10_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC10; /*!< (@ 0x00005744) PSFP Meter CBS Configuration Register 10 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC10_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC10; /*!< (@ 0x00005748) PSFP Meter CIR Configuration Register 10 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC10_b; + }; + __IM uint32_t RESERVED143[2]; + + union + { + __IM uint32_t FWPMTRFM10; /*!< (@ 0x00005754) PSFP Meter Filter Monitoring Register 10 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM10_b; + }; + __IM uint32_t RESERVED144[2]; + + union + { + __IOM uint32_t FWPMTRFC11; /*!< (@ 0x00005760) PSFP Meter Filter Configuration Register 11 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC11_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC11; /*!< (@ 0x00005764) PSFP Meter CBS Configuration Register 11 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC11_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC11; /*!< (@ 0x00005768) PSFP Meter CIR Configuration Register 11 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC11_b; + }; + __IM uint32_t RESERVED145[2]; + + union + { + __IM uint32_t FWPMTRFM11; /*!< (@ 0x00005774) PSFP Meter Filter Monitoring Register 11 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM11_b; + }; + __IM uint32_t RESERVED146[2]; + + union + { + __IOM uint32_t FWPMTRFC12; /*!< (@ 0x00005780) PSFP Meter Filter Configuration Register 12 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC12_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC12; /*!< (@ 0x00005784) PSFP Meter CBS Configuration Register 12 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC12_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC12; /*!< (@ 0x00005788) PSFP Meter CIR Configuration Register 12 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC12_b; + }; + __IM uint32_t RESERVED147[2]; + + union + { + __IM uint32_t FWPMTRFM12; /*!< (@ 0x00005794) PSFP Meter Filter Monitoring Register 12 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM12_b; + }; + __IM uint32_t RESERVED148[2]; + + union + { + __IOM uint32_t FWPMTRFC13; /*!< (@ 0x000057A0) PSFP Meter Filter Configuration Register 13 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC13_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC13; /*!< (@ 0x000057A4) PSFP Meter CBS Configuration Register 13 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC13_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC13; /*!< (@ 0x000057A8) PSFP Meter CIR Configuration Register 13 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC13_b; + }; + __IM uint32_t RESERVED149[2]; + + union + { + __IM uint32_t FWPMTRFM13; /*!< (@ 0x000057B4) PSFP Meter Filter Monitoring Register 13 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM13_b; + }; + __IM uint32_t RESERVED150[2]; + + union + { + __IOM uint32_t FWPMTRFC14; /*!< (@ 0x000057C0) PSFP Meter Filter Configuration Register 14 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC14_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC14; /*!< (@ 0x000057C4) PSFP Meter CBS Configuration Register 14 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC14_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC14; /*!< (@ 0x000057C8) PSFP Meter CIR Configuration Register 14 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC14_b; + }; + __IM uint32_t RESERVED151[2]; + + union + { + __IM uint32_t FWPMTRFM14; /*!< (@ 0x000057D4) PSFP Meter Filter Monitoring Register 14 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM14_b; + }; + __IM uint32_t RESERVED152[2]; + + union + { + __IOM uint32_t FWPMTRFC15; /*!< (@ 0x000057E0) PSFP Meter Filter Configuration Register 15 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC15_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC15; /*!< (@ 0x000057E4) PSFP Meter CBS Configuration Register 15 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC15_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC15; /*!< (@ 0x000057E8) PSFP Meter CIR Configuration Register 15 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC15_b; + }; + __IM uint32_t RESERVED153[2]; + + union + { + __IM uint32_t FWPMTRFM15; /*!< (@ 0x000057F4) PSFP Meter Filter Monitoring Register 15 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM15_b; + }; + __IM uint32_t RESERVED154[2]; + + union + { + __IOM uint32_t FWPMTRFC16; /*!< (@ 0x00005800) PSFP Meter Filter Configuration Register 16 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC16_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC16; /*!< (@ 0x00005804) PSFP Meter CBS Configuration Register 16 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC16_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC16; /*!< (@ 0x00005808) PSFP Meter CIR Configuration Register 16 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC16_b; + }; + __IM uint32_t RESERVED155[2]; + + union + { + __IM uint32_t FWPMTRFM16; /*!< (@ 0x00005814) PSFP Meter Filter Monitoring Register 16 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM16_b; + }; + __IM uint32_t RESERVED156[2]; + + union + { + __IOM uint32_t FWPMTRFC17; /*!< (@ 0x00005820) PSFP Meter Filter Configuration Register 17 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC17_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC17; /*!< (@ 0x00005824) PSFP Meter CBS Configuration Register 17 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC17_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC17; /*!< (@ 0x00005828) PSFP Meter CIR Configuration Register 17 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC17_b; + }; + __IM uint32_t RESERVED157[2]; + + union + { + __IM uint32_t FWPMTRFM17; /*!< (@ 0x00005834) PSFP Meter Filter Monitoring Register 17 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM17_b; + }; + __IM uint32_t RESERVED158[2]; + + union + { + __IOM uint32_t FWPMTRFC18; /*!< (@ 0x00005840) PSFP Meter Filter Configuration Register 18 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC18_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC18; /*!< (@ 0x00005844) PSFP Meter CBS Configuration Register 18 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC18_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC18; /*!< (@ 0x00005848) PSFP Meter CIR Configuration Register 18 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC18_b; + }; + __IM uint32_t RESERVED159[2]; + + union + { + __IM uint32_t FWPMTRFM18; /*!< (@ 0x00005854) PSFP Meter Filter Monitoring Register 18 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM18_b; + }; + __IM uint32_t RESERVED160[2]; + + union + { + __IOM uint32_t FWPMTRFC19; /*!< (@ 0x00005860) PSFP Meter Filter Configuration Register 19 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC19_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC19; /*!< (@ 0x00005864) PSFP Meter CBS Configuration Register 19 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC19_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC19; /*!< (@ 0x00005868) PSFP Meter CIR Configuration Register 19 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC19_b; + }; + __IM uint32_t RESERVED161[2]; + + union + { + __IM uint32_t FWPMTRFM19; /*!< (@ 0x00005874) PSFP Meter Filter Monitoring Register 19 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM19_b; + }; + __IM uint32_t RESERVED162[2]; + + union + { + __IOM uint32_t FWPMTRFC20; /*!< (@ 0x00005880) PSFP Meter Filter Configuration Register 20 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC20_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC20; /*!< (@ 0x00005884) PSFP Meter CBS Configuration Register 20 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC20_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC20; /*!< (@ 0x00005888) PSFP Meter CIR Configuration Register 20 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC20_b; + }; + __IM uint32_t RESERVED163[2]; + + union + { + __IM uint32_t FWPMTRFM20; /*!< (@ 0x00005894) PSFP Meter Filter Monitoring Register 20 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM20_b; + }; + __IM uint32_t RESERVED164[2]; + + union + { + __IOM uint32_t FWPMTRFC21; /*!< (@ 0x000058A0) PSFP Meter Filter Configuration Register 21 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC21_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC21; /*!< (@ 0x000058A4) PSFP Meter CBS Configuration Register 21 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC21_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC21; /*!< (@ 0x000058A8) PSFP Meter CIR Configuration Register 21 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC21_b; + }; + __IM uint32_t RESERVED165[2]; + + union + { + __IM uint32_t FWPMTRFM21; /*!< (@ 0x000058B4) PSFP Meter Filter Monitoring Register 21 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM21_b; + }; + __IM uint32_t RESERVED166[2]; + + union + { + __IOM uint32_t FWPMTRFC22; /*!< (@ 0x000058C0) PSFP Meter Filter Configuration Register 22 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC22_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC22; /*!< (@ 0x000058C4) PSFP Meter CBS Configuration Register 22 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC22_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC22; /*!< (@ 0x000058C8) PSFP Meter CIR Configuration Register 22 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC22_b; + }; + __IM uint32_t RESERVED167[2]; + + union + { + __IM uint32_t FWPMTRFM22; /*!< (@ 0x000058D4) PSFP Meter Filter Monitoring Register 22 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM22_b; + }; + __IM uint32_t RESERVED168[2]; + + union + { + __IOM uint32_t FWPMTRFC23; /*!< (@ 0x000058E0) PSFP Meter Filter Configuration Register 23 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC23_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC23; /*!< (@ 0x000058E4) PSFP Meter CBS Configuration Register 23 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC23_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC23; /*!< (@ 0x000058E8) PSFP Meter CIR Configuration Register 23 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC23_b; + }; + __IM uint32_t RESERVED169[2]; + + union + { + __IM uint32_t FWPMTRFM23; /*!< (@ 0x000058F4) PSFP Meter Filter Monitoring Register 23 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM23_b; + }; + __IM uint32_t RESERVED170[2]; + + union + { + __IOM uint32_t FWPMTRFC24; /*!< (@ 0x00005900) PSFP Meter Filter Configuration Register 24 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC24_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC24; /*!< (@ 0x00005904) PSFP Meter CBS Configuration Register 24 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC24_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC24; /*!< (@ 0x00005908) PSFP Meter CIR Configuration Register 24 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC24_b; + }; + __IM uint32_t RESERVED171[2]; + + union + { + __IM uint32_t FWPMTRFM24; /*!< (@ 0x00005914) PSFP Meter Filter Monitoring Register 24 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM24_b; + }; + __IM uint32_t RESERVED172[2]; + + union + { + __IOM uint32_t FWPMTRFC25; /*!< (@ 0x00005920) PSFP Meter Filter Configuration Register 25 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC25_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC25; /*!< (@ 0x00005924) PSFP Meter CBS Configuration Register 25 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC25_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC25; /*!< (@ 0x00005928) PSFP Meter CIR Configuration Register 25 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC25_b; + }; + __IM uint32_t RESERVED173[2]; + + union + { + __IM uint32_t FWPMTRFM25; /*!< (@ 0x00005934) PSFP Meter Filter Monitoring Register 25 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM25_b; + }; + __IM uint32_t RESERVED174[2]; + + union + { + __IOM uint32_t FWPMTRFC26; /*!< (@ 0x00005940) PSFP Meter Filter Configuration Register 26 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC26_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC26; /*!< (@ 0x00005944) PSFP Meter CBS Configuration Register 26 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC26_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC26; /*!< (@ 0x00005948) PSFP Meter CIR Configuration Register 26 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC26_b; + }; + __IM uint32_t RESERVED175[2]; + + union + { + __IM uint32_t FWPMTRFM26; /*!< (@ 0x00005954) PSFP Meter Filter Monitoring Register 26 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM26_b; + }; + __IM uint32_t RESERVED176[2]; + + union + { + __IOM uint32_t FWPMTRFC27; /*!< (@ 0x00005960) PSFP Meter Filter Configuration Register 27 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC27_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC27; /*!< (@ 0x00005964) PSFP Meter CBS Configuration Register 27 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC27_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC27; /*!< (@ 0x00005968) PSFP Meter CIR Configuration Register 27 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC27_b; + }; + __IM uint32_t RESERVED177[2]; + + union + { + __IM uint32_t FWPMTRFM27; /*!< (@ 0x00005974) PSFP Meter Filter Monitoring Register 27 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM27_b; + }; + __IM uint32_t RESERVED178[2]; + + union + { + __IOM uint32_t FWPMTRFC28; /*!< (@ 0x00005980) PSFP Meter Filter Configuration Register 28 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC28_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC28; /*!< (@ 0x00005984) PSFP Meter CBS Configuration Register 28 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC28_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC28; /*!< (@ 0x00005988) PSFP Meter CIR Configuration Register 28 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC28_b; + }; + __IM uint32_t RESERVED179[2]; + + union + { + __IM uint32_t FWPMTRFM28; /*!< (@ 0x00005994) PSFP Meter Filter Monitoring Register 28 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM28_b; + }; + __IM uint32_t RESERVED180[2]; + + union + { + __IOM uint32_t FWPMTRFC29; /*!< (@ 0x000059A0) PSFP Meter Filter Configuration Register 29 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC29_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC29; /*!< (@ 0x000059A4) PSFP Meter CBS Configuration Register 29 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC29_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC29; /*!< (@ 0x000059A8) PSFP Meter CIR Configuration Register 29 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC29_b; + }; + __IM uint32_t RESERVED181[2]; + + union + { + __IM uint32_t FWPMTRFM29; /*!< (@ 0x000059B4) PSFP Meter Filter Monitoring Register 29 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM29_b; + }; + __IM uint32_t RESERVED182[2]; + + union + { + __IOM uint32_t FWPMTRFC30; /*!< (@ 0x000059C0) PSFP Meter Filter Configuration Register 30 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC30_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC30; /*!< (@ 0x000059C4) PSFP Meter CBS Configuration Register 30 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC30_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC30; /*!< (@ 0x000059C8) PSFP Meter CIR Configuration Register 30 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC30_b; + }; + __IM uint32_t RESERVED183[2]; + + union + { + __IM uint32_t FWPMTRFM30; /*!< (@ 0x000059D4) PSFP Meter Filter Monitoring Register 30 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM30_b; + }; + __IM uint32_t RESERVED184[2]; + + union + { + __IOM uint32_t FWPMTRFC31; /*!< (@ 0x000059E0) PSFP Meter Filter Configuration Register 31 */ + + struct + { + __IOM uint32_t MTRFE : 1; /*!< [0..0] Meter Filter Enable */ + __IOM uint32_t MTRFM : 2; /*!< [2..1] Meter Filter Mode */ + __IOM uint32_t MTRFRFD : 1; /*!< [3..3] Meter Filter Red Frame Drop */ + __IOM uint32_t MTRCF : 1; /*!< [4..4] Meter Coupling Flag */ + uint32_t : 11; + __IOM uint32_t MTRCM : 16; /*!< [31..16] Meter Color Mode */ + } FWPMTRFC31_b; + }; + + union + { + __IOM uint32_t FWPMTRCBSC31; /*!< (@ 0x000059E4) PSFP Meter CBS Configuration Register 31 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS */ + uint32_t : 14; + } FWPMTRCBSC31_b; + }; + + union + { + __IOM uint32_t FWPMTRCIRC31; /*!< (@ 0x000059E8) PSFP Meter CIR Configuration Register 31 */ + + struct + { + __IOM uint32_t CIR : 20; /*!< [19..0] CIR */ + uint32_t : 12; + } FWPMTRCIRC31_b; + }; + __IM uint32_t RESERVED185[2]; + + union + { + __IM uint32_t FWPMTRFM31; /*!< (@ 0x000059F4) PSFP Meter Filter Monitoring Register 31 */ + + struct + { + __IM uint32_t MTRARDN : 5; /*!< [4..0] MeTeR ATS RAM Descriptor Number */ + uint32_t : 11; + __IM uint32_t MTRARDNMN : 5; /*!< [20..16] MeTeR ATS RAM Descriptor Number Maximum Number i */ + uint32_t : 11; + } FWPMTRFM31_b; + }; + __IM uint32_t RESERVED186[386]; + + union + { + __IOM uint32_t FWFTL0; /*!< (@ 0x00006000) FRER Table Learn Register 0 */ + + struct + { + __IOM uint32_t FEAL : 7; /*!< [6..0] FRER Entry Address Learn */ + uint32_t : 9; + __IOM uint32_t FSRPL : 7; /*!< [22..16] FRER Sequence Recovery Pointer Learn */ + uint32_t : 9; + } FWFTL0_b; + }; + + union + { + __IOM uint32_t FWFTL1; /*!< (@ 0x00006004) FRER Table Learn Register 1 */ + + struct + { + __IOM uint32_t FSHLL : 4; /*!< [3..0] FRER Sequence History Length Learn */ + uint32_t : 4; + __IOM uint32_t FTNSL : 1; /*!< [8..8] FRER Take No Sequence Learn */ + __IOM uint32_t FSRPVL : 1; /*!< [9..9] FRER Sequence Recovery Pointer Valid Learn */ + uint32_t : 6; + __IOM uint32_t FSRRTL : 10; /*!< [25..16] FRER Sequence Recovery Remaining Ticks Learn */ + uint32_t : 6; + } FWFTL1_b; + }; + + union + { + __IM uint32_t FWFTLR; /*!< (@ 0x00006008) FRER Table Learn Result Register */ + + struct + { + __IM uint32_t FLF : 1; /*!< [0..0] FRER Learn Fail */ + uint32_t : 30; + __IM uint32_t FTL : 1; /*!< [31..31] FRER Table Learn */ + } FWFTLR_b; + }; + __IM uint32_t RESERVED187; + + union + { + __IOM uint32_t FWFTOC; /*!< (@ 0x00006010) FRER Timeout Configuration Register */ + + struct + { + __IOM uint32_t TOT : 16; /*!< [15..0] Timeout Time (ms) */ + __IOM uint32_t TOCE : 1; /*!< [16..16] Timeout Check Enable */ + __IOM uint32_t TOOG : 1; /*!< [17..17] Timeout Ongoing */ + uint32_t : 14; + } FWFTOC_b; + }; + + union + { + __IOM uint32_t FWFTOPC; /*!< (@ 0x00006014) FRER Timeout Prescaler Configuration Register + * 0 */ + + struct + { + __IOM uint32_t USP : 10; /*!< [9..0] Microsecond Prescaler */ + uint32_t : 22; + } FWFTOPC_b; + }; + __IM uint32_t RESERVED188[2]; + + union + { + __IOM uint32_t FWFTIM; /*!< (@ 0x00006020) FRER Table Initialization Monitoring Register */ + + struct + { + __IOM uint32_t FTIOG : 1; /*!< [0..0] FRER Table Initialization Ongoing */ + __IM uint32_t FTR : 1; /*!< [1..1] FRER Table Ready */ + uint32_t : 30; + } FWFTIM_b; + }; + __IM uint32_t RESERVED189[3]; + + union + { + __IOM uint32_t FWFTR; /*!< (@ 0x00006030) FRER Table Read Register */ + + struct + { + __IOM uint32_t FEAR : 7; /*!< [6..0] FRER Entry Address Read */ + uint32_t : 25; + } FWFTR_b; + }; + + union + { + __IM uint32_t FWFTRR0; /*!< (@ 0x00006034) FRER Table Read Result Register 0 */ + + struct + { + __IM uint32_t FSHLR : 4; /*!< [3..0] FRER Sequence History Length Read */ + uint32_t : 4; + __IM uint32_t FTNSR : 1; /*!< [8..8] FRER Take No Sequence Read */ + __IM uint32_t FSRPVR : 1; /*!< [9..9] FRER Sequence Recovery Pointer Valid Read */ + uint32_t : 6; + __IM uint32_t FSRRTR : 10; /*!< [25..16] FRER Set Recovery Remaining Ticks Read */ + uint32_t : 4; + __IM uint32_t FTREF : 1; /*!< [30..30] FRER Table Read ECC Fail */ + __IM uint32_t FTR : 1; /*!< [31..31] FRER Table Read */ + } FWFTRR0_b; + }; + + union + { + __IM uint32_t FWFTRR1; /*!< (@ 0x00006038) FRER Table Read Result Register 1 */ + + struct + { + __IM uint32_t FSHR : 15; /*!< [14..0] FRER Sequence History Read */ + uint32_t : 1; + __IM uint32_t FSRPR : 7; /*!< [22..16] FRER Sequence Recovery Pointer Read */ + uint32_t : 9; + } FWFTRR1_b; + }; + + union + { + __IM uint32_t FWFTRR2; /*!< (@ 0x0000603C) FRER Table Read Result Register 2 */ + + struct + { + __IM uint32_t FRSNR : 16; /*!< [15..0] FRER Recovery Sequence Number Read */ + __IM uint32_t FRRTR : 10; /*!< [25..16] FRER Recovery Remaining Ticks Read */ + uint32_t : 6; + } FWFTRR2_b; + }; + __IM uint32_t RESERVED190[48]; + + union + { + __IOM uint32_t FWSEQNGC0; /*!< (@ 0x00006100) Sequence Number Generation Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC0_b; + }; + + union + { + __IM uint32_t FWSEQNGM0; /*!< (@ 0x00006104) Sequence Number Generation Monitoring Register + * 0 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM0_b; + }; + + union + { + __IOM uint32_t FWSEQNGC1; /*!< (@ 0x00006108) Sequence Number Generation Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC1_b; + }; + + union + { + __IM uint32_t FWSEQNGM1; /*!< (@ 0x0000610C) Sequence Number Generation Monitoring Register + * 1 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM1_b; + }; + + union + { + __IOM uint32_t FWSEQNGC2; /*!< (@ 0x00006110) Sequence Number Generation Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC2_b; + }; + + union + { + __IM uint32_t FWSEQNGM2; /*!< (@ 0x00006114) Sequence Number Generation Monitoring Register + * 2 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM2_b; + }; + + union + { + __IOM uint32_t FWSEQNGC3; /*!< (@ 0x00006118) Sequence Number Generation Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC3_b; + }; + + union + { + __IM uint32_t FWSEQNGM3; /*!< (@ 0x0000611C) Sequence Number Generation Monitoring Register + * 3 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM3_b; + }; + + union + { + __IOM uint32_t FWSEQNGC4; /*!< (@ 0x00006120) Sequence Number Generation Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC4_b; + }; + + union + { + __IM uint32_t FWSEQNGM4; /*!< (@ 0x00006124) Sequence Number Generation Monitoring Register + * 4 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM4_b; + }; + + union + { + __IOM uint32_t FWSEQNGC5; /*!< (@ 0x00006128) Sequence Number Generation Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC5_b; + }; + + union + { + __IM uint32_t FWSEQNGM5; /*!< (@ 0x0000612C) Sequence Number Generation Monitoring Register + * 5 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM5_b; + }; + + union + { + __IOM uint32_t FWSEQNGC6; /*!< (@ 0x00006130) Sequence Number Generation Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC6_b; + }; + + union + { + __IM uint32_t FWSEQNGM6; /*!< (@ 0x00006134) Sequence Number Generation Monitoring Register + * 6 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM6_b; + }; + + union + { + __IOM uint32_t FWSEQNGC7; /*!< (@ 0x00006138) Sequence Number Generation Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC7_b; + }; + + union + { + __IM uint32_t FWSEQNGM7; /*!< (@ 0x0000613C) Sequence Number Generation Monitoring Register + * 7 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM7_b; + }; + + union + { + __IOM uint32_t FWSEQNGC8; /*!< (@ 0x00006140) Sequence Number Generation Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC8_b; + }; + + union + { + __IM uint32_t FWSEQNGM8; /*!< (@ 0x00006144) Sequence Number Generation Monitoring Register + * 8 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM8_b; + }; + + union + { + __IOM uint32_t FWSEQNGC9; /*!< (@ 0x00006148) Sequence Number Generation Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC9_b; + }; + + union + { + __IM uint32_t FWSEQNGM9; /*!< (@ 0x0000614C) Sequence Number Generation Monitoring Register + * 9 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM9_b; + }; + + union + { + __IOM uint32_t FWSEQNGC10; /*!< (@ 0x00006150) Sequence Number Generation Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC10_b; + }; + + union + { + __IM uint32_t FWSEQNGM10; /*!< (@ 0x00006154) Sequence Number Generation Monitoring Register + * 10 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM10_b; + }; + + union + { + __IOM uint32_t FWSEQNGC11; /*!< (@ 0x00006158) Sequence Number Generation Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC11_b; + }; + + union + { + __IM uint32_t FWSEQNGM11; /*!< (@ 0x0000615C) Sequence Number Generation Monitoring Register + * 11 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM11_b; + }; + + union + { + __IOM uint32_t FWSEQNGC12; /*!< (@ 0x00006160) Sequence Number Generation Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC12_b; + }; + + union + { + __IM uint32_t FWSEQNGM12; /*!< (@ 0x00006164) Sequence Number Generation Monitoring Register + * 12 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM12_b; + }; + + union + { + __IOM uint32_t FWSEQNGC13; /*!< (@ 0x00006168) Sequence Number Generation Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC13_b; + }; + + union + { + __IM uint32_t FWSEQNGM13; /*!< (@ 0x0000616C) Sequence Number Generation Monitoring Register + * 13 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM13_b; + }; + + union + { + __IOM uint32_t FWSEQNGC14; /*!< (@ 0x00006170) Sequence Number Generation Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC14_b; + }; + + union + { + __IM uint32_t FWSEQNGM14; /*!< (@ 0x00006174) Sequence Number Generation Monitoring Register + * 14 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM14_b; + }; + + union + { + __IOM uint32_t FWSEQNGC15; /*!< (@ 0x00006178) Sequence Number Generation Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC15_b; + }; + + union + { + __IM uint32_t FWSEQNGM15; /*!< (@ 0x0000617C) Sequence Number Generation Monitoring Register + * 15 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM15_b; + }; + + union + { + __IOM uint32_t FWSEQNGC16; /*!< (@ 0x00006180) Sequence Number Generation Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC16_b; + }; + + union + { + __IM uint32_t FWSEQNGM16; /*!< (@ 0x00006184) Sequence Number Generation Monitoring Register + * 16 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM16_b; + }; + + union + { + __IOM uint32_t FWSEQNGC17; /*!< (@ 0x00006188) Sequence Number Generation Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC17_b; + }; + + union + { + __IM uint32_t FWSEQNGM17; /*!< (@ 0x0000618C) Sequence Number Generation Monitoring Register + * 17 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM17_b; + }; + + union + { + __IOM uint32_t FWSEQNGC18; /*!< (@ 0x00006190) Sequence Number Generation Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC18_b; + }; + + union + { + __IM uint32_t FWSEQNGM18; /*!< (@ 0x00006194) Sequence Number Generation Monitoring Register + * 18 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM18_b; + }; + + union + { + __IOM uint32_t FWSEQNGC19; /*!< (@ 0x00006198) Sequence Number Generation Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC19_b; + }; + + union + { + __IM uint32_t FWSEQNGM19; /*!< (@ 0x0000619C) Sequence Number Generation Monitoring Register + * 19 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM19_b; + }; + + union + { + __IOM uint32_t FWSEQNGC20; /*!< (@ 0x000061A0) Sequence Number Generation Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC20_b; + }; + + union + { + __IM uint32_t FWSEQNGM20; /*!< (@ 0x000061A4) Sequence Number Generation Monitoring Register + * 20 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM20_b; + }; + + union + { + __IOM uint32_t FWSEQNGC21; /*!< (@ 0x000061A8) Sequence Number Generation Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC21_b; + }; + + union + { + __IM uint32_t FWSEQNGM21; /*!< (@ 0x000061AC) Sequence Number Generation Monitoring Register + * 21 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM21_b; + }; + + union + { + __IOM uint32_t FWSEQNGC22; /*!< (@ 0x000061B0) Sequence Number Generation Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC22_b; + }; + + union + { + __IM uint32_t FWSEQNGM22; /*!< (@ 0x000061B4) Sequence Number Generation Monitoring Register + * 22 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM22_b; + }; + + union + { + __IOM uint32_t FWSEQNGC23; /*!< (@ 0x000061B8) Sequence Number Generation Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC23_b; + }; + + union + { + __IM uint32_t FWSEQNGM23; /*!< (@ 0x000061BC) Sequence Number Generation Monitoring Register + * 23 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM23_b; + }; + + union + { + __IOM uint32_t FWSEQNGC24; /*!< (@ 0x000061C0) Sequence Number Generation Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC24_b; + }; + + union + { + __IM uint32_t FWSEQNGM24; /*!< (@ 0x000061C4) Sequence Number Generation Monitoring Register + * 24 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM24_b; + }; + + union + { + __IOM uint32_t FWSEQNGC25; /*!< (@ 0x000061C8) Sequence Number Generation Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC25_b; + }; + + union + { + __IM uint32_t FWSEQNGM25; /*!< (@ 0x000061CC) Sequence Number Generation Monitoring Register + * 25 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM25_b; + }; + + union + { + __IOM uint32_t FWSEQNGC26; /*!< (@ 0x000061D0) Sequence Number Generation Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC26_b; + }; + + union + { + __IM uint32_t FWSEQNGM26; /*!< (@ 0x000061D4) Sequence Number Generation Monitoring Register + * 26 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM26_b; + }; + + union + { + __IOM uint32_t FWSEQNGC27; /*!< (@ 0x000061D8) Sequence Number Generation Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC27_b; + }; + + union + { + __IM uint32_t FWSEQNGM27; /*!< (@ 0x000061DC) Sequence Number Generation Monitoring Register + * 27 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM27_b; + }; + + union + { + __IOM uint32_t FWSEQNGC28; /*!< (@ 0x000061E0) Sequence Number Generation Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC28_b; + }; + + union + { + __IM uint32_t FWSEQNGM28; /*!< (@ 0x000061E4) Sequence Number Generation Monitoring Register + * 28 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM28_b; + }; + + union + { + __IOM uint32_t FWSEQNGC29; /*!< (@ 0x000061E8) Sequence Number Generation Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC29_b; + }; + + union + { + __IM uint32_t FWSEQNGM29; /*!< (@ 0x000061EC) Sequence Number Generation Monitoring Register + * 29 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM29_b; + }; + + union + { + __IOM uint32_t FWSEQNGC30; /*!< (@ 0x000061F0) Sequence Number Generation Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC30_b; + }; + + union + { + __IM uint32_t FWSEQNGM30; /*!< (@ 0x000061F4) Sequence Number Generation Monitoring Register + * 30 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM30_b; + }; + + union + { + __IOM uint32_t FWSEQNGC31; /*!< (@ 0x000061F8) Sequence Number Generation Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SEQNGRN : 8; /*!< [7..0] SEQuence Number Generation Routing Number */ + uint32_t : 8; + __IOM uint32_t SEQNGE : 1; /*!< [16..16] SEQuence Number Generation Emable */ + uint32_t : 15; + } FWSEQNGC31_b; + }; + + union + { + __IM uint32_t FWSEQNGM31; /*!< (@ 0x000061FC) Sequence Number Generation Monitoring Register + * 31 */ + + struct + { + __IM uint32_t SEQN : 16; /*!< [15..0] SEQuence Number */ + uint32_t : 16; + } FWSEQNGM31_b; + }; + + union + { + __OM uint32_t FWSEQNRC; /*!< (@ 0x00006200) Sequence Number Reset Configuration Register */ + + struct + { + __OM uint32_t SEQNR : 32; /*!< [31..0] Sequence Number Generation Reset */ + } FWSEQNRC_b; + }; + __IM uint32_t RESERVED191[63]; + + union + { + __IM uint32_t FWCTFDCN0; /*!< (@ 0x00006300) Cut-Through Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t CTFDN : 32; /*!< [31..0] Cut-Through Forwarded Descriptor Number */ + } FWCTFDCN0_b; + }; + + union + { + __IM uint32_t FWLTHFDCN0; /*!< (@ 0x00006304) Layer 3 Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN0_b; + }; + __IM uint32_t RESERVED192; + + union + { + __IM uint32_t FWLTWFDCN0; /*!< (@ 0x0000630C) Layer 2 Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN0_b; + }; + + union + { + __IM uint32_t FWPBFDCN0; /*!< (@ 0x00006310) Port Based Forwarded Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN0_b; + }; + + union + { + __IM uint32_t FWMHLCN0; /*!< (@ 0x00006314) MAC Hardware Learn Counter Register 0 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN0_b; + }; + __IM uint32_t RESERVED193[2]; + + union + { + __IM uint32_t FWCTFDCN1; /*!< (@ 0x00006320) Cut-Through Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t CTFDN : 32; /*!< [31..0] Cut-Through Forwarded Descriptor Number */ + } FWCTFDCN1_b; + }; + + union + { + __IM uint32_t FWLTHFDCN1; /*!< (@ 0x00006324) Layer 3 Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN1_b; + }; + __IM uint32_t RESERVED194; + + union + { + __IM uint32_t FWLTWFDCN1; /*!< (@ 0x0000632C) Layer 2 Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN1_b; + }; + + union + { + __IM uint32_t FWPBFDCN1; /*!< (@ 0x00006330) Port Based Forwarded Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN1_b; + }; + + union + { + __IM uint32_t FWMHLCN1; /*!< (@ 0x00006334) MAC Hardware Learn Counter Register 1 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN1_b; + }; + __IM uint32_t RESERVED195[2]; + + union + { + __IM uint32_t FWDDFDCN0; /*!< (@ 0x00006340) Direct Descriptor Forwarded Descriptor Counter + * Register 0 */ + + struct + { + __IM uint32_t DDFDN : 32; /*!< [31..0] Direct Descriptor Forwarded Descriptor Number */ + } FWDDFDCN0_b; + }; + + union + { + __IM uint32_t FWLTHFDCN2; /*!< (@ 0x00006344) Layer 3 Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTHFDN : 32; /*!< [31..0] Layer 3 Forwarded Descriptor Number */ + } FWLTHFDCN2_b; + }; + __IM uint32_t RESERVED196; + + union + { + __IM uint32_t FWLTWFDCN2; /*!< (@ 0x0000634C) Layer 2 Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTWFDN : 32; /*!< [31..0] Layer 2 Forwarded Descriptor Number */ + } FWLTWFDCN2_b; + }; + + union + { + __IM uint32_t FWPBFDCN2; /*!< (@ 0x00006350) Port Based Forwarded Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PBFDN : 32; /*!< [31..0] Port Based Forwarded Descriptor Number */ + } FWPBFDCN2_b; + }; + + union + { + __IM uint32_t FWMHLCN2; /*!< (@ 0x00006354) MAC Hardware Learn Counter Register 2 */ + + struct + { + __IM uint32_t MHLN : 32; /*!< [31..0] MAC Hardware Learn Number */ + } FWMHLCN2_b; + }; + __IM uint32_t RESERVED197[107]; + + union + { + __IM uint32_t FWWMRDCN0; /*!< (@ 0x00006504) Watermark Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN0_b; + }; + + union + { + __IM uint32_t FWCTRDCN0; /*!< (@ 0x00006508) Cut-Through Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t CTRDN : 16; /*!< [15..0] Cut-through rejected Descriptor Number */ + uint32_t : 16; + } FWCTRDCN0_b; + }; + + union + { + __IM uint32_t FWLTHRDCN0; /*!< (@ 0x0000650C) Layer 3 Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN0_b; + }; + __IM uint32_t RESERVED198; + + union + { + __IM uint32_t FWLTWRDCN0; /*!< (@ 0x00006514) Layer 2 Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN0_b; + }; + + union + { + __IM uint32_t FWPBRDCN0; /*!< (@ 0x00006518) Port Based Rejected Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN0_b; + }; + __IM uint32_t RESERVED199[2]; + + union + { + __IM uint32_t FWWMRDCN1; /*!< (@ 0x00006524) Watermark Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN1_b; + }; + + union + { + __IM uint32_t FWCTRDCN1; /*!< (@ 0x00006528) Cut-Through Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t CTRDN : 16; /*!< [15..0] Cut-through rejected Descriptor Number */ + uint32_t : 16; + } FWCTRDCN1_b; + }; + + union + { + __IM uint32_t FWLTHRDCN1; /*!< (@ 0x0000652C) Layer 3 Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN1_b; + }; + __IM uint32_t RESERVED200; + + union + { + __IM uint32_t FWLTWRDCN1; /*!< (@ 0x00006534) Layer 2 Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN1_b; + }; + + union + { + __IM uint32_t FWPBRDCN1; /*!< (@ 0x00006538) Port Based Rejected Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN1_b; + }; + __IM uint32_t RESERVED201[2]; + + union + { + __IM uint32_t FWWMRDCN2; /*!< (@ 0x00006544) Watermark Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t WMRDN : 16; /*!< [15..0] Watermark rejected Descriptor Number */ + uint32_t : 16; + } FWWMRDCN2_b; + }; + + union + { + __IM uint32_t FWDDRDCN0; /*!< (@ 0x00006548) Direct Descriptor Rejected Descriptor Counter + * Register 0 */ + + struct + { + __IM uint32_t DDRDN : 16; /*!< [15..0] Direct Descriptor rejected Descriptor Number */ + uint32_t : 16; + } FWDDRDCN0_b; + }; + + union + { + __IM uint32_t FWLTHRDCN2; /*!< (@ 0x0000654C) Layer 3 Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTHRDN : 16; /*!< [15..0] Layer 3 rejected Descriptor Number */ + uint32_t : 16; + } FWLTHRDCN2_b; + }; + __IM uint32_t RESERVED202; + + union + { + __IM uint32_t FWLTWRDCN2; /*!< (@ 0x00006554) Layer 2 Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t LTWRDN : 16; /*!< [15..0] Layer 2 rejected Descriptor Number */ + uint32_t : 16; + } FWLTWRDCN2_b; + }; + + union + { + __IM uint32_t FWPBRDCN2; /*!< (@ 0x00006558) Port Based Rejected Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PBRDN : 16; /*!< [15..0] Port Based rejected Descriptor Number */ + uint32_t : 16; + } FWPBRDCN2_b; + }; + __IM uint32_t RESERVED203[105]; + + union + { + __IM uint32_t FWPMFDCN0; /*!< (@ 0x00006700) PSFP MSDU Filtered Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN0_b; + }; + + union + { + __IM uint32_t FWPMFDCN1; /*!< (@ 0x00006704) PSFP MSDU Filtered Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN1_b; + }; + + union + { + __IM uint32_t FWPMFDCN2; /*!< (@ 0x00006708) PSFP MSDU Filtered Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN2_b; + }; + + union + { + __IM uint32_t FWPMFDCN3; /*!< (@ 0x0000670C) PSFP MSDU Filtered Descriptor Counter Register + * 3 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN3_b; + }; + + union + { + __IM uint32_t FWPMFDCN4; /*!< (@ 0x00006710) PSFP MSDU Filtered Descriptor Counter Register + * 4 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN4_b; + }; + + union + { + __IM uint32_t FWPMFDCN5; /*!< (@ 0x00006714) PSFP MSDU Filtered Descriptor Counter Register + * 5 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN5_b; + }; + + union + { + __IM uint32_t FWPMFDCN6; /*!< (@ 0x00006718) PSFP MSDU Filtered Descriptor Counter Register + * 6 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN6_b; + }; + + union + { + __IM uint32_t FWPMFDCN7; /*!< (@ 0x0000671C) PSFP MSDU Filtered Descriptor Counter Register + * 7 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN7_b; + }; + + union + { + __IM uint32_t FWPMFDCN8; /*!< (@ 0x00006720) PSFP MSDU Filtered Descriptor Counter Register + * 8 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN8_b; + }; + + union + { + __IM uint32_t FWPMFDCN9; /*!< (@ 0x00006724) PSFP MSDU Filtered Descriptor Counter Register + * 9 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN9_b; + }; + + union + { + __IM uint32_t FWPMFDCN10; /*!< (@ 0x00006728) PSFP MSDU Filtered Descriptor Counter Register + * 10 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN10_b; + }; + + union + { + __IM uint32_t FWPMFDCN11; /*!< (@ 0x0000672C) PSFP MSDU Filtered Descriptor Counter Register + * 11 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN11_b; + }; + + union + { + __IM uint32_t FWPMFDCN12; /*!< (@ 0x00006730) PSFP MSDU Filtered Descriptor Counter Register + * 12 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN12_b; + }; + + union + { + __IM uint32_t FWPMFDCN13; /*!< (@ 0x00006734) PSFP MSDU Filtered Descriptor Counter Register + * 13 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN13_b; + }; + + union + { + __IM uint32_t FWPMFDCN14; /*!< (@ 0x00006738) PSFP MSDU Filtered Descriptor Counter Register + * 14 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN14_b; + }; + + union + { + __IM uint32_t FWPMFDCN15; /*!< (@ 0x0000673C) PSFP MSDU Filtered Descriptor Counter Register + * 15 */ + + struct + { + __IM uint32_t PMFDN : 16; /*!< [15..0] PSFP MSDU Filtered Descriptor Number */ + uint32_t : 16; + } FWPMFDCN15_b; + }; + __IM uint32_t RESERVED204[48]; + + union + { + __IM uint32_t FWPMGDCN0; /*!< (@ 0x00006800) PSFP Meter Green Descriptor Counter Register + * 0 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN0_b; + }; + + union + { + __IM uint32_t FWPMYDCN0; /*!< (@ 0x00006804) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN0_b; + }; + + union + { + __IM uint32_t FWPMRDCN0; /*!< (@ 0x00006808) PSFP Meter Red Descriptor Counter Register 0 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN0_b; + }; + __IM uint32_t RESERVED205; + + union + { + __IM uint32_t FWPMGDCN1; /*!< (@ 0x00006810) PSFP Meter Green Descriptor Counter Register + * 1 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN1_b; + }; + + union + { + __IM uint32_t FWPMYDCN1; /*!< (@ 0x00006814) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN1_b; + }; + + union + { + __IM uint32_t FWPMRDCN1; /*!< (@ 0x00006818) PSFP Meter Red Descriptor Counter Register 1 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN1_b; + }; + __IM uint32_t RESERVED206; + + union + { + __IM uint32_t FWPMGDCN2; /*!< (@ 0x00006820) PSFP Meter Green Descriptor Counter Register + * 2 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN2_b; + }; + + union + { + __IM uint32_t FWPMYDCN2; /*!< (@ 0x00006824) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN2_b; + }; + + union + { + __IM uint32_t FWPMRDCN2; /*!< (@ 0x00006828) PSFP Meter Red Descriptor Counter Register 2 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN2_b; + }; + __IM uint32_t RESERVED207; + + union + { + __IM uint32_t FWPMGDCN3; /*!< (@ 0x00006830) PSFP Meter Green Descriptor Counter Register + * 3 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN3_b; + }; + + union + { + __IM uint32_t FWPMYDCN3; /*!< (@ 0x00006834) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN3_b; + }; + + union + { + __IM uint32_t FWPMRDCN3; /*!< (@ 0x00006838) PSFP Meter Red Descriptor Counter Register 3 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN3_b; + }; + __IM uint32_t RESERVED208; + + union + { + __IM uint32_t FWPMGDCN4; /*!< (@ 0x00006840) PSFP Meter Green Descriptor Counter Register + * 4 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN4_b; + }; + + union + { + __IM uint32_t FWPMYDCN4; /*!< (@ 0x00006844) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN4_b; + }; + + union + { + __IM uint32_t FWPMRDCN4; /*!< (@ 0x00006848) PSFP Meter Red Descriptor Counter Register 4 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN4_b; + }; + __IM uint32_t RESERVED209; + + union + { + __IM uint32_t FWPMGDCN5; /*!< (@ 0x00006850) PSFP Meter Green Descriptor Counter Register + * 5 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN5_b; + }; + + union + { + __IM uint32_t FWPMYDCN5; /*!< (@ 0x00006854) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN5_b; + }; + + union + { + __IM uint32_t FWPMRDCN5; /*!< (@ 0x00006858) PSFP Meter Red Descriptor Counter Register 5 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN5_b; + }; + __IM uint32_t RESERVED210; + + union + { + __IM uint32_t FWPMGDCN6; /*!< (@ 0x00006860) PSFP Meter Green Descriptor Counter Register + * 6 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN6_b; + }; + + union + { + __IM uint32_t FWPMYDCN6; /*!< (@ 0x00006864) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN6_b; + }; + + union + { + __IM uint32_t FWPMRDCN6; /*!< (@ 0x00006868) PSFP Meter Red Descriptor Counter Register 6 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN6_b; + }; + __IM uint32_t RESERVED211; + + union + { + __IM uint32_t FWPMGDCN7; /*!< (@ 0x00006870) PSFP Meter Green Descriptor Counter Register + * 7 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN7_b; + }; + + union + { + __IM uint32_t FWPMYDCN7; /*!< (@ 0x00006874) PSFP Meter Yellow Descriptor Counter Register */ + + struct + { + __IM uint32_t PMYDN : 16; /*!< [15..0] PSFP Meter Yellow Descriptor Number */ + uint32_t : 16; + } FWPMYDCN7_b; + }; + + union + { + __IM uint32_t FWPMRDCN7; /*!< (@ 0x00006878) PSFP Meter Red Descriptor Counter Register 7 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN7_b; + }; + __IM uint32_t RESERVED212; + + union + { + __IM uint32_t FWPMGDCN8; /*!< (@ 0x00006880) PSFP Meter Green Descriptor Counter Register + * 8 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN8_b; + }; + __IM uint32_t RESERVED213; + + union + { + __IM uint32_t FWPMRDCN8; /*!< (@ 0x00006888) PSFP Meter Red Descriptor Counter Register 8 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN8_b; + }; + __IM uint32_t RESERVED214; + + union + { + __IM uint32_t FWPMGDCN9; /*!< (@ 0x00006890) PSFP Meter Green Descriptor Counter Register + * 9 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN9_b; + }; + __IM uint32_t RESERVED215; + + union + { + __IM uint32_t FWPMRDCN9; /*!< (@ 0x00006898) PSFP Meter Red Descriptor Counter Register 9 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN9_b; + }; + __IM uint32_t RESERVED216; + + union + { + __IM uint32_t FWPMGDCN10; /*!< (@ 0x000068A0) PSFP Meter Green Descriptor Counter Register + * 10 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN10_b; + }; + __IM uint32_t RESERVED217; + + union + { + __IM uint32_t FWPMRDCN10; /*!< (@ 0x000068A8) PSFP Meter Red Descriptor Counter Register 10 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN10_b; + }; + __IM uint32_t RESERVED218; + + union + { + __IM uint32_t FWPMGDCN11; /*!< (@ 0x000068B0) PSFP Meter Green Descriptor Counter Register + * 11 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN11_b; + }; + __IM uint32_t RESERVED219; + + union + { + __IM uint32_t FWPMRDCN11; /*!< (@ 0x000068B8) PSFP Meter Red Descriptor Counter Register 11 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN11_b; + }; + __IM uint32_t RESERVED220; + + union + { + __IM uint32_t FWPMGDCN12; /*!< (@ 0x000068C0) PSFP Meter Green Descriptor Counter Register + * 12 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN12_b; + }; + __IM uint32_t RESERVED221; + + union + { + __IM uint32_t FWPMRDCN12; /*!< (@ 0x000068C8) PSFP Meter Red Descriptor Counter Register 12 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN12_b; + }; + __IM uint32_t RESERVED222; + + union + { + __IM uint32_t FWPMGDCN13; /*!< (@ 0x000068D0) PSFP Meter Green Descriptor Counter Register + * 13 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN13_b; + }; + __IM uint32_t RESERVED223; + + union + { + __IM uint32_t FWPMRDCN13; /*!< (@ 0x000068D8) PSFP Meter Red Descriptor Counter Register 13 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN13_b; + }; + __IM uint32_t RESERVED224; + + union + { + __IM uint32_t FWPMGDCN14; /*!< (@ 0x000068E0) PSFP Meter Green Descriptor Counter Register + * 14 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN14_b; + }; + __IM uint32_t RESERVED225; + + union + { + __IM uint32_t FWPMRDCN14; /*!< (@ 0x000068E8) PSFP Meter Red Descriptor Counter Register 14 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN14_b; + }; + __IM uint32_t RESERVED226; + + union + { + __IM uint32_t FWPMGDCN15; /*!< (@ 0x000068F0) PSFP Meter Green Descriptor Counter Register + * 15 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN15_b; + }; + __IM uint32_t RESERVED227; + + union + { + __IM uint32_t FWPMRDCN15; /*!< (@ 0x000068F8) PSFP Meter Red Descriptor Counter Register 15 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN15_b; + }; + __IM uint32_t RESERVED228; + + union + { + __IM uint32_t FWPMGDCN16; /*!< (@ 0x00006900) PSFP Meter Green Descriptor Counter Register + * 16 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN16_b; + }; + __IM uint32_t RESERVED229; + + union + { + __IM uint32_t FWPMRDCN16; /*!< (@ 0x00006908) PSFP Meter Red Descriptor Counter Register 16 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN16_b; + }; + __IM uint32_t RESERVED230; + + union + { + __IM uint32_t FWPMGDCN17; /*!< (@ 0x00006910) PSFP Meter Green Descriptor Counter Register + * 17 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN17_b; + }; + __IM uint32_t RESERVED231; + + union + { + __IM uint32_t FWPMRDCN17; /*!< (@ 0x00006918) PSFP Meter Red Descriptor Counter Register 17 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN17_b; + }; + __IM uint32_t RESERVED232; + + union + { + __IM uint32_t FWPMGDCN18; /*!< (@ 0x00006920) PSFP Meter Green Descriptor Counter Register + * 18 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN18_b; + }; + __IM uint32_t RESERVED233; + + union + { + __IM uint32_t FWPMRDCN18; /*!< (@ 0x00006928) PSFP Meter Red Descriptor Counter Register 18 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN18_b; + }; + __IM uint32_t RESERVED234; + + union + { + __IM uint32_t FWPMGDCN19; /*!< (@ 0x00006930) PSFP Meter Green Descriptor Counter Register + * 19 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN19_b; + }; + __IM uint32_t RESERVED235; + + union + { + __IM uint32_t FWPMRDCN19; /*!< (@ 0x00006938) PSFP Meter Red Descriptor Counter Register 19 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN19_b; + }; + __IM uint32_t RESERVED236; + + union + { + __IM uint32_t FWPMGDCN20; /*!< (@ 0x00006940) PSFP Meter Green Descriptor Counter Register + * 20 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN20_b; + }; + __IM uint32_t RESERVED237; + + union + { + __IM uint32_t FWPMRDCN20; /*!< (@ 0x00006948) PSFP Meter Red Descriptor Counter Register 20 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN20_b; + }; + __IM uint32_t RESERVED238; + + union + { + __IM uint32_t FWPMGDCN21; /*!< (@ 0x00006950) PSFP Meter Green Descriptor Counter Register + * 21 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN21_b; + }; + __IM uint32_t RESERVED239; + + union + { + __IM uint32_t FWPMRDCN21; /*!< (@ 0x00006958) PSFP Meter Red Descriptor Counter Register 21 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN21_b; + }; + __IM uint32_t RESERVED240; + + union + { + __IM uint32_t FWPMGDCN22; /*!< (@ 0x00006960) PSFP Meter Green Descriptor Counter Register + * 22 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN22_b; + }; + __IM uint32_t RESERVED241; + + union + { + __IM uint32_t FWPMRDCN22; /*!< (@ 0x00006968) PSFP Meter Red Descriptor Counter Register 22 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN22_b; + }; + __IM uint32_t RESERVED242; + + union + { + __IM uint32_t FWPMGDCN23; /*!< (@ 0x00006970) PSFP Meter Green Descriptor Counter Register + * 23 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN23_b; + }; + __IM uint32_t RESERVED243; + + union + { + __IM uint32_t FWPMRDCN23; /*!< (@ 0x00006978) PSFP Meter Red Descriptor Counter Register 23 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN23_b; + }; + __IM uint32_t RESERVED244; + + union + { + __IM uint32_t FWPMGDCN24; /*!< (@ 0x00006980) PSFP Meter Green Descriptor Counter Register + * 24 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN24_b; + }; + __IM uint32_t RESERVED245; + + union + { + __IM uint32_t FWPMRDCN24; /*!< (@ 0x00006988) PSFP Meter Red Descriptor Counter Register 24 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN24_b; + }; + __IM uint32_t RESERVED246; + + union + { + __IM uint32_t FWPMGDCN25; /*!< (@ 0x00006990) PSFP Meter Green Descriptor Counter Register + * 25 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN25_b; + }; + __IM uint32_t RESERVED247; + + union + { + __IM uint32_t FWPMRDCN25; /*!< (@ 0x00006998) PSFP Meter Red Descriptor Counter Register 25 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN25_b; + }; + __IM uint32_t RESERVED248; + + union + { + __IM uint32_t FWPMGDCN26; /*!< (@ 0x000069A0) PSFP Meter Green Descriptor Counter Register + * 26 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN26_b; + }; + __IM uint32_t RESERVED249; + + union + { + __IM uint32_t FWPMRDCN26; /*!< (@ 0x000069A8) PSFP Meter Red Descriptor Counter Register 26 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN26_b; + }; + __IM uint32_t RESERVED250; + + union + { + __IM uint32_t FWPMGDCN27; /*!< (@ 0x000069B0) PSFP Meter Green Descriptor Counter Register + * 27 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN27_b; + }; + __IM uint32_t RESERVED251; + + union + { + __IM uint32_t FWPMRDCN27; /*!< (@ 0x000069B8) PSFP Meter Red Descriptor Counter Register 27 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN27_b; + }; + __IM uint32_t RESERVED252; + + union + { + __IM uint32_t FWPMGDCN28; /*!< (@ 0x000069C0) PSFP Meter Green Descriptor Counter Register + * 28 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN28_b; + }; + __IM uint32_t RESERVED253; + + union + { + __IM uint32_t FWPMRDCN28; /*!< (@ 0x000069C8) PSFP Meter Red Descriptor Counter Register 28 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN28_b; + }; + __IM uint32_t RESERVED254; + + union + { + __IM uint32_t FWPMGDCN29; /*!< (@ 0x000069D0) PSFP Meter Green Descriptor Counter Register + * 29 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN29_b; + }; + __IM uint32_t RESERVED255; + + union + { + __IM uint32_t FWPMRDCN29; /*!< (@ 0x000069D8) PSFP Meter Red Descriptor Counter Register 29 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN29_b; + }; + __IM uint32_t RESERVED256; + + union + { + __IM uint32_t FWPMGDCN30; /*!< (@ 0x000069E0) PSFP Meter Green Descriptor Counter Register + * 30 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN30_b; + }; + __IM uint32_t RESERVED257; + + union + { + __IM uint32_t FWPMRDCN30; /*!< (@ 0x000069E8) PSFP Meter Red Descriptor Counter Register 30 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN30_b; + }; + __IM uint32_t RESERVED258; + + union + { + __IM uint32_t FWPMGDCN31; /*!< (@ 0x000069F0) PSFP Meter Green Descriptor Counter Register + * 31 */ + + struct + { + __IM uint32_t PMGDN : 16; /*!< [15..0] PSFP Meter Green Descriptor Number */ + uint32_t : 16; + } FWPMGDCN31_b; + }; + __IM uint32_t RESERVED259; + + union + { + __IM uint32_t FWPMRDCN31; /*!< (@ 0x000069F8) PSFP Meter Red Descriptor Counter Register 31 */ + + struct + { + __IM uint32_t PMRDN : 16; /*!< [15..0] PSFP Meter Red Descriptor Number */ + uint32_t : 16; + } FWPMRDCN31_b; + }; + __IM uint32_t RESERVED260; + + union + { + __IM uint32_t FWFRPPCN0; /*!< (@ 0x00006A00) FRER Passed Packet Counter Register 0 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN0_b; + }; + + union + { + __IM uint32_t FWFRDPCN0; /*!< (@ 0x00006A04) FRER Discarded Packet Counter Register 0 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN0_b; + }; + + union + { + __IM uint32_t FWFRPPCN1; /*!< (@ 0x00006A08) FRER Passed Packet Counter Register 1 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN1_b; + }; + + union + { + __IM uint32_t FWFRDPCN1; /*!< (@ 0x00006A0C) FRER Discarded Packet Counter Register 1 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN1_b; + }; + + union + { + __IM uint32_t FWFRPPCN2; /*!< (@ 0x00006A10) FRER Passed Packet Counter Register 2 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN2_b; + }; + + union + { + __IM uint32_t FWFRDPCN2; /*!< (@ 0x00006A14) FRER Discarded Packet Counter Register 2 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN2_b; + }; + + union + { + __IM uint32_t FWFRPPCN3; /*!< (@ 0x00006A18) FRER Passed Packet Counter Register 3 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN3_b; + }; + + union + { + __IM uint32_t FWFRDPCN3; /*!< (@ 0x00006A1C) FRER Discarded Packet Counter Register 3 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN3_b; + }; + + union + { + __IM uint32_t FWFRPPCN4; /*!< (@ 0x00006A20) FRER Passed Packet Counter Register 4 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN4_b; + }; + + union + { + __IM uint32_t FWFRDPCN4; /*!< (@ 0x00006A24) FRER Discarded Packet Counter Register 4 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN4_b; + }; + + union + { + __IM uint32_t FWFRPPCN5; /*!< (@ 0x00006A28) FRER Passed Packet Counter Register 5 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN5_b; + }; + + union + { + __IM uint32_t FWFRDPCN5; /*!< (@ 0x00006A2C) FRER Discarded Packet Counter Register 5 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN5_b; + }; + + union + { + __IM uint32_t FWFRPPCN6; /*!< (@ 0x00006A30) FRER Passed Packet Counter Register 6 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN6_b; + }; + + union + { + __IM uint32_t FWFRDPCN6; /*!< (@ 0x00006A34) FRER Discarded Packet Counter Register 6 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN6_b; + }; + + union + { + __IM uint32_t FWFRPPCN7; /*!< (@ 0x00006A38) FRER Passed Packet Counter Register 7 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN7_b; + }; + + union + { + __IM uint32_t FWFRDPCN7; /*!< (@ 0x00006A3C) FRER Discarded Packet Counter Register 7 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN7_b; + }; + + union + { + __IM uint32_t FWFRPPCN8; /*!< (@ 0x00006A40) FRER Passed Packet Counter Register 8 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN8_b; + }; + + union + { + __IM uint32_t FWFRDPCN8; /*!< (@ 0x00006A44) FRER Discarded Packet Counter Register 8 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN8_b; + }; + + union + { + __IM uint32_t FWFRPPCN9; /*!< (@ 0x00006A48) FRER Passed Packet Counter Register 9 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN9_b; + }; + + union + { + __IM uint32_t FWFRDPCN9; /*!< (@ 0x00006A4C) FRER Discarded Packet Counter Register 9 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN9_b; + }; + + union + { + __IM uint32_t FWFRPPCN10; /*!< (@ 0x00006A50) FRER Passed Packet Counter Register 10 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN10_b; + }; + + union + { + __IM uint32_t FWFRDPCN10; /*!< (@ 0x00006A54) FRER Discarded Packet Counter Register 10 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN10_b; + }; + + union + { + __IM uint32_t FWFRPPCN11; /*!< (@ 0x00006A58) FRER Passed Packet Counter Register 11 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN11_b; + }; + + union + { + __IM uint32_t FWFRDPCN11; /*!< (@ 0x00006A5C) FRER Discarded Packet Counter Register 11 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN11_b; + }; + + union + { + __IM uint32_t FWFRPPCN12; /*!< (@ 0x00006A60) FRER Passed Packet Counter Register 12 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN12_b; + }; + + union + { + __IM uint32_t FWFRDPCN12; /*!< (@ 0x00006A64) FRER Discarded Packet Counter Register 12 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN12_b; + }; + + union + { + __IM uint32_t FWFRPPCN13; /*!< (@ 0x00006A68) FRER Passed Packet Counter Register 13 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN13_b; + }; + + union + { + __IM uint32_t FWFRDPCN13; /*!< (@ 0x00006A6C) FRER Discarded Packet Counter Register 13 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN13_b; + }; + + union + { + __IM uint32_t FWFRPPCN14; /*!< (@ 0x00006A70) FRER Passed Packet Counter Register 14 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN14_b; + }; + + union + { + __IM uint32_t FWFRDPCN14; /*!< (@ 0x00006A74) FRER Discarded Packet Counter Register 14 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN14_b; + }; + + union + { + __IM uint32_t FWFRPPCN15; /*!< (@ 0x00006A78) FRER Passed Packet Counter Register 15 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN15_b; + }; + + union + { + __IM uint32_t FWFRDPCN15; /*!< (@ 0x00006A7C) FRER Discarded Packet Counter Register 15 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN15_b; + }; + + union + { + __IM uint32_t FWFRPPCN16; /*!< (@ 0x00006A80) FRER Passed Packet Counter Register 16 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN16_b; + }; + + union + { + __IM uint32_t FWFRDPCN16; /*!< (@ 0x00006A84) FRER Discarded Packet Counter Register 16 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN16_b; + }; + + union + { + __IM uint32_t FWFRPPCN17; /*!< (@ 0x00006A88) FRER Passed Packet Counter Register 17 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN17_b; + }; + + union + { + __IM uint32_t FWFRDPCN17; /*!< (@ 0x00006A8C) FRER Discarded Packet Counter Register 17 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN17_b; + }; + + union + { + __IM uint32_t FWFRPPCN18; /*!< (@ 0x00006A90) FRER Passed Packet Counter Register 18 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN18_b; + }; + + union + { + __IM uint32_t FWFRDPCN18; /*!< (@ 0x00006A94) FRER Discarded Packet Counter Register 18 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN18_b; + }; + + union + { + __IM uint32_t FWFRPPCN19; /*!< (@ 0x00006A98) FRER Passed Packet Counter Register 19 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN19_b; + }; + + union + { + __IM uint32_t FWFRDPCN19; /*!< (@ 0x00006A9C) FRER Discarded Packet Counter Register 19 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN19_b; + }; + + union + { + __IM uint32_t FWFRPPCN20; /*!< (@ 0x00006AA0) FRER Passed Packet Counter Register 20 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN20_b; + }; + + union + { + __IM uint32_t FWFRDPCN20; /*!< (@ 0x00006AA4) FRER Discarded Packet Counter Register 20 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN20_b; + }; + + union + { + __IM uint32_t FWFRPPCN21; /*!< (@ 0x00006AA8) FRER Passed Packet Counter Register 21 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN21_b; + }; + + union + { + __IM uint32_t FWFRDPCN21; /*!< (@ 0x00006AAC) FRER Discarded Packet Counter Register 21 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN21_b; + }; + + union + { + __IM uint32_t FWFRPPCN22; /*!< (@ 0x00006AB0) FRER Passed Packet Counter Register 22 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN22_b; + }; + + union + { + __IM uint32_t FWFRDPCN22; /*!< (@ 0x00006AB4) FRER Discarded Packet Counter Register 22 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN22_b; + }; + + union + { + __IM uint32_t FWFRPPCN23; /*!< (@ 0x00006AB8) FRER Passed Packet Counter Register 23 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN23_b; + }; + + union + { + __IM uint32_t FWFRDPCN23; /*!< (@ 0x00006ABC) FRER Discarded Packet Counter Register 23 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN23_b; + }; + + union + { + __IM uint32_t FWFRPPCN24; /*!< (@ 0x00006AC0) FRER Passed Packet Counter Register 24 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN24_b; + }; + + union + { + __IM uint32_t FWFRDPCN24; /*!< (@ 0x00006AC4) FRER Discarded Packet Counter Register 24 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN24_b; + }; + + union + { + __IM uint32_t FWFRPPCN25; /*!< (@ 0x00006AC8) FRER Passed Packet Counter Register 25 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN25_b; + }; + + union + { + __IM uint32_t FWFRDPCN25; /*!< (@ 0x00006ACC) FRER Discarded Packet Counter Register 25 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN25_b; + }; + + union + { + __IM uint32_t FWFRPPCN26; /*!< (@ 0x00006AD0) FRER Passed Packet Counter Register 26 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN26_b; + }; + + union + { + __IM uint32_t FWFRDPCN26; /*!< (@ 0x00006AD4) FRER Discarded Packet Counter Register 26 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN26_b; + }; + + union + { + __IM uint32_t FWFRPPCN27; /*!< (@ 0x00006AD8) FRER Passed Packet Counter Register 27 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN27_b; + }; + + union + { + __IM uint32_t FWFRDPCN27; /*!< (@ 0x00006ADC) FRER Discarded Packet Counter Register 27 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN27_b; + }; + + union + { + __IM uint32_t FWFRPPCN28; /*!< (@ 0x00006AE0) FRER Passed Packet Counter Register 28 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN28_b; + }; + + union + { + __IM uint32_t FWFRDPCN28; /*!< (@ 0x00006AE4) FRER Discarded Packet Counter Register 28 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN28_b; + }; + + union + { + __IM uint32_t FWFRPPCN29; /*!< (@ 0x00006AE8) FRER Passed Packet Counter Register 29 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN29_b; + }; + + union + { + __IM uint32_t FWFRDPCN29; /*!< (@ 0x00006AEC) FRER Discarded Packet Counter Register 29 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN29_b; + }; + + union + { + __IM uint32_t FWFRPPCN30; /*!< (@ 0x00006AF0) FRER Passed Packet Counter Register 30 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN30_b; + }; + + union + { + __IM uint32_t FWFRDPCN30; /*!< (@ 0x00006AF4) FRER Discarded Packet Counter Register 30 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN30_b; + }; + + union + { + __IM uint32_t FWFRPPCN31; /*!< (@ 0x00006AF8) FRER Passed Packet Counter Register 31 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN31_b; + }; + + union + { + __IM uint32_t FWFRDPCN31; /*!< (@ 0x00006AFC) FRER Discarded Packet Counter Register 31 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN31_b; + }; + + union + { + __IM uint32_t FWFRPPCN32; /*!< (@ 0x00006B00) FRER Passed Packet Counter Register 32 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN32_b; + }; + + union + { + __IM uint32_t FWFRDPCN32; /*!< (@ 0x00006B04) FRER Discarded Packet Counter Register 32 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN32_b; + }; + + union + { + __IM uint32_t FWFRPPCN33; /*!< (@ 0x00006B08) FRER Passed Packet Counter Register 33 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN33_b; + }; + + union + { + __IM uint32_t FWFRDPCN33; /*!< (@ 0x00006B0C) FRER Discarded Packet Counter Register 33 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN33_b; + }; + + union + { + __IM uint32_t FWFRPPCN34; /*!< (@ 0x00006B10) FRER Passed Packet Counter Register 34 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN34_b; + }; + + union + { + __IM uint32_t FWFRDPCN34; /*!< (@ 0x00006B14) FRER Discarded Packet Counter Register 34 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN34_b; + }; + + union + { + __IM uint32_t FWFRPPCN35; /*!< (@ 0x00006B18) FRER Passed Packet Counter Register 35 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN35_b; + }; + + union + { + __IM uint32_t FWFRDPCN35; /*!< (@ 0x00006B1C) FRER Discarded Packet Counter Register 35 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN35_b; + }; + + union + { + __IM uint32_t FWFRPPCN36; /*!< (@ 0x00006B20) FRER Passed Packet Counter Register 36 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN36_b; + }; + + union + { + __IM uint32_t FWFRDPCN36; /*!< (@ 0x00006B24) FRER Discarded Packet Counter Register 36 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN36_b; + }; + + union + { + __IM uint32_t FWFRPPCN37; /*!< (@ 0x00006B28) FRER Passed Packet Counter Register 37 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN37_b; + }; + + union + { + __IM uint32_t FWFRDPCN37; /*!< (@ 0x00006B2C) FRER Discarded Packet Counter Register 37 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN37_b; + }; + + union + { + __IM uint32_t FWFRPPCN38; /*!< (@ 0x00006B30) FRER Passed Packet Counter Register 38 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN38_b; + }; + + union + { + __IM uint32_t FWFRDPCN38; /*!< (@ 0x00006B34) FRER Discarded Packet Counter Register 38 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN38_b; + }; + + union + { + __IM uint32_t FWFRPPCN39; /*!< (@ 0x00006B38) FRER Passed Packet Counter Register 39 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN39_b; + }; + + union + { + __IM uint32_t FWFRDPCN39; /*!< (@ 0x00006B3C) FRER Discarded Packet Counter Register 39 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN39_b; + }; + + union + { + __IM uint32_t FWFRPPCN40; /*!< (@ 0x00006B40) FRER Passed Packet Counter Register 40 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN40_b; + }; + + union + { + __IM uint32_t FWFRDPCN40; /*!< (@ 0x00006B44) FRER Discarded Packet Counter Register 40 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN40_b; + }; + + union + { + __IM uint32_t FWFRPPCN41; /*!< (@ 0x00006B48) FRER Passed Packet Counter Register 41 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN41_b; + }; + + union + { + __IM uint32_t FWFRDPCN41; /*!< (@ 0x00006B4C) FRER Discarded Packet Counter Register 41 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN41_b; + }; + + union + { + __IM uint32_t FWFRPPCN42; /*!< (@ 0x00006B50) FRER Passed Packet Counter Register 42 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN42_b; + }; + + union + { + __IM uint32_t FWFRDPCN42; /*!< (@ 0x00006B54) FRER Discarded Packet Counter Register 42 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN42_b; + }; + + union + { + __IM uint32_t FWFRPPCN43; /*!< (@ 0x00006B58) FRER Passed Packet Counter Register 43 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN43_b; + }; + + union + { + __IM uint32_t FWFRDPCN43; /*!< (@ 0x00006B5C) FRER Discarded Packet Counter Register 43 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN43_b; + }; + + union + { + __IM uint32_t FWFRPPCN44; /*!< (@ 0x00006B60) FRER Passed Packet Counter Register 44 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN44_b; + }; + + union + { + __IM uint32_t FWFRDPCN44; /*!< (@ 0x00006B64) FRER Discarded Packet Counter Register 44 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN44_b; + }; + + union + { + __IM uint32_t FWFRPPCN45; /*!< (@ 0x00006B68) FRER Passed Packet Counter Register 45 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN45_b; + }; + + union + { + __IM uint32_t FWFRDPCN45; /*!< (@ 0x00006B6C) FRER Discarded Packet Counter Register 45 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN45_b; + }; + + union + { + __IM uint32_t FWFRPPCN46; /*!< (@ 0x00006B70) FRER Passed Packet Counter Register 46 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN46_b; + }; + + union + { + __IM uint32_t FWFRDPCN46; /*!< (@ 0x00006B74) FRER Discarded Packet Counter Register 46 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN46_b; + }; + + union + { + __IM uint32_t FWFRPPCN47; /*!< (@ 0x00006B78) FRER Passed Packet Counter Register 47 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN47_b; + }; + + union + { + __IM uint32_t FWFRDPCN47; /*!< (@ 0x00006B7C) FRER Discarded Packet Counter Register 47 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN47_b; + }; + + union + { + __IM uint32_t FWFRPPCN48; /*!< (@ 0x00006B80) FRER Passed Packet Counter Register 48 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN48_b; + }; + + union + { + __IM uint32_t FWFRDPCN48; /*!< (@ 0x00006B84) FRER Discarded Packet Counter Register 48 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN48_b; + }; + + union + { + __IM uint32_t FWFRPPCN49; /*!< (@ 0x00006B88) FRER Passed Packet Counter Register 49 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN49_b; + }; + + union + { + __IM uint32_t FWFRDPCN49; /*!< (@ 0x00006B8C) FRER Discarded Packet Counter Register 49 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN49_b; + }; + + union + { + __IM uint32_t FWFRPPCN50; /*!< (@ 0x00006B90) FRER Passed Packet Counter Register 50 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN50_b; + }; + + union + { + __IM uint32_t FWFRDPCN50; /*!< (@ 0x00006B94) FRER Discarded Packet Counter Register 50 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN50_b; + }; + + union + { + __IM uint32_t FWFRPPCN51; /*!< (@ 0x00006B98) FRER Passed Packet Counter Register 51 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN51_b; + }; + + union + { + __IM uint32_t FWFRDPCN51; /*!< (@ 0x00006B9C) FRER Discarded Packet Counter Register 51 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN51_b; + }; + + union + { + __IM uint32_t FWFRPPCN52; /*!< (@ 0x00006BA0) FRER Passed Packet Counter Register 52 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN52_b; + }; + + union + { + __IM uint32_t FWFRDPCN52; /*!< (@ 0x00006BA4) FRER Discarded Packet Counter Register 52 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN52_b; + }; + + union + { + __IM uint32_t FWFRPPCN53; /*!< (@ 0x00006BA8) FRER Passed Packet Counter Register 53 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN53_b; + }; + + union + { + __IM uint32_t FWFRDPCN53; /*!< (@ 0x00006BAC) FRER Discarded Packet Counter Register 53 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN53_b; + }; + + union + { + __IM uint32_t FWFRPPCN54; /*!< (@ 0x00006BB0) FRER Passed Packet Counter Register 54 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN54_b; + }; + + union + { + __IM uint32_t FWFRDPCN54; /*!< (@ 0x00006BB4) FRER Discarded Packet Counter Register 54 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN54_b; + }; + + union + { + __IM uint32_t FWFRPPCN55; /*!< (@ 0x00006BB8) FRER Passed Packet Counter Register 55 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN55_b; + }; + + union + { + __IM uint32_t FWFRDPCN55; /*!< (@ 0x00006BBC) FRER Discarded Packet Counter Register 55 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN55_b; + }; + + union + { + __IM uint32_t FWFRPPCN56; /*!< (@ 0x00006BC0) FRER Passed Packet Counter Register 56 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN56_b; + }; + + union + { + __IM uint32_t FWFRDPCN56; /*!< (@ 0x00006BC4) FRER Discarded Packet Counter Register 56 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN56_b; + }; + + union + { + __IM uint32_t FWFRPPCN57; /*!< (@ 0x00006BC8) FRER Passed Packet Counter Register 57 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN57_b; + }; + + union + { + __IM uint32_t FWFRDPCN57; /*!< (@ 0x00006BCC) FRER Discarded Packet Counter Register 57 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN57_b; + }; + + union + { + __IM uint32_t FWFRPPCN58; /*!< (@ 0x00006BD0) FRER Passed Packet Counter Register 58 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN58_b; + }; + + union + { + __IM uint32_t FWFRDPCN58; /*!< (@ 0x00006BD4) FRER Discarded Packet Counter Register 58 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN58_b; + }; + + union + { + __IM uint32_t FWFRPPCN59; /*!< (@ 0x00006BD8) FRER Passed Packet Counter Register 59 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN59_b; + }; + + union + { + __IM uint32_t FWFRDPCN59; /*!< (@ 0x00006BDC) FRER Discarded Packet Counter Register 59 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN59_b; + }; + + union + { + __IM uint32_t FWFRPPCN60; /*!< (@ 0x00006BE0) FRER Passed Packet Counter Register 60 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN60_b; + }; + + union + { + __IM uint32_t FWFRDPCN60; /*!< (@ 0x00006BE4) FRER Discarded Packet Counter Register 60 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN60_b; + }; + + union + { + __IM uint32_t FWFRPPCN61; /*!< (@ 0x00006BE8) FRER Passed Packet Counter Register 61 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN61_b; + }; + + union + { + __IM uint32_t FWFRDPCN61; /*!< (@ 0x00006BEC) FRER Discarded Packet Counter Register 61 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN61_b; + }; + + union + { + __IM uint32_t FWFRPPCN62; /*!< (@ 0x00006BF0) FRER Passed Packet Counter Register 62 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN62_b; + }; + + union + { + __IM uint32_t FWFRDPCN62; /*!< (@ 0x00006BF4) FRER Discarded Packet Counter Register 62 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN62_b; + }; + + union + { + __IM uint32_t FWFRPPCN63; /*!< (@ 0x00006BF8) FRER Passed Packet Counter Register 63 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN63_b; + }; + + union + { + __IM uint32_t FWFRDPCN63; /*!< (@ 0x00006BFC) FRER Discarded Packet Counter Register 63 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN63_b; + }; + + union + { + __IM uint32_t FWFRPPCN64; /*!< (@ 0x00006C00) FRER Passed Packet Counter Register 64 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN64_b; + }; + + union + { + __IM uint32_t FWFRDPCN64; /*!< (@ 0x00006C04) FRER Discarded Packet Counter Register 64 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN64_b; + }; + + union + { + __IM uint32_t FWFRPPCN65; /*!< (@ 0x00006C08) FRER Passed Packet Counter Register 65 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN65_b; + }; + + union + { + __IM uint32_t FWFRDPCN65; /*!< (@ 0x00006C0C) FRER Discarded Packet Counter Register 65 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN65_b; + }; + + union + { + __IM uint32_t FWFRPPCN66; /*!< (@ 0x00006C10) FRER Passed Packet Counter Register 66 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN66_b; + }; + + union + { + __IM uint32_t FWFRDPCN66; /*!< (@ 0x00006C14) FRER Discarded Packet Counter Register 66 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN66_b; + }; + + union + { + __IM uint32_t FWFRPPCN67; /*!< (@ 0x00006C18) FRER Passed Packet Counter Register 67 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN67_b; + }; + + union + { + __IM uint32_t FWFRDPCN67; /*!< (@ 0x00006C1C) FRER Discarded Packet Counter Register 67 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN67_b; + }; + + union + { + __IM uint32_t FWFRPPCN68; /*!< (@ 0x00006C20) FRER Passed Packet Counter Register 68 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN68_b; + }; + + union + { + __IM uint32_t FWFRDPCN68; /*!< (@ 0x00006C24) FRER Discarded Packet Counter Register 68 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN68_b; + }; + + union + { + __IM uint32_t FWFRPPCN69; /*!< (@ 0x00006C28) FRER Passed Packet Counter Register 69 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN69_b; + }; + + union + { + __IM uint32_t FWFRDPCN69; /*!< (@ 0x00006C2C) FRER Discarded Packet Counter Register 69 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN69_b; + }; + + union + { + __IM uint32_t FWFRPPCN70; /*!< (@ 0x00006C30) FRER Passed Packet Counter Register 70 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN70_b; + }; + + union + { + __IM uint32_t FWFRDPCN70; /*!< (@ 0x00006C34) FRER Discarded Packet Counter Register 70 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN70_b; + }; + + union + { + __IM uint32_t FWFRPPCN71; /*!< (@ 0x00006C38) FRER Passed Packet Counter Register 71 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN71_b; + }; + + union + { + __IM uint32_t FWFRDPCN71; /*!< (@ 0x00006C3C) FRER Discarded Packet Counter Register 71 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN71_b; + }; + + union + { + __IM uint32_t FWFRPPCN72; /*!< (@ 0x00006C40) FRER Passed Packet Counter Register 72 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN72_b; + }; + + union + { + __IM uint32_t FWFRDPCN72; /*!< (@ 0x00006C44) FRER Discarded Packet Counter Register 72 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN72_b; + }; + + union + { + __IM uint32_t FWFRPPCN73; /*!< (@ 0x00006C48) FRER Passed Packet Counter Register 73 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN73_b; + }; + + union + { + __IM uint32_t FWFRDPCN73; /*!< (@ 0x00006C4C) FRER Discarded Packet Counter Register 73 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN73_b; + }; + + union + { + __IM uint32_t FWFRPPCN74; /*!< (@ 0x00006C50) FRER Passed Packet Counter Register 74 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN74_b; + }; + + union + { + __IM uint32_t FWFRDPCN74; /*!< (@ 0x00006C54) FRER Discarded Packet Counter Register 74 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN74_b; + }; + + union + { + __IM uint32_t FWFRPPCN75; /*!< (@ 0x00006C58) FRER Passed Packet Counter Register 75 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN75_b; + }; + + union + { + __IM uint32_t FWFRDPCN75; /*!< (@ 0x00006C5C) FRER Discarded Packet Counter Register 75 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN75_b; + }; + + union + { + __IM uint32_t FWFRPPCN76; /*!< (@ 0x00006C60) FRER Passed Packet Counter Register 76 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN76_b; + }; + + union + { + __IM uint32_t FWFRDPCN76; /*!< (@ 0x00006C64) FRER Discarded Packet Counter Register 76 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN76_b; + }; + + union + { + __IM uint32_t FWFRPPCN77; /*!< (@ 0x00006C68) FRER Passed Packet Counter Register 77 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN77_b; + }; + + union + { + __IM uint32_t FWFRDPCN77; /*!< (@ 0x00006C6C) FRER Discarded Packet Counter Register 77 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN77_b; + }; + + union + { + __IM uint32_t FWFRPPCN78; /*!< (@ 0x00006C70) FRER Passed Packet Counter Register 78 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN78_b; + }; + + union + { + __IM uint32_t FWFRDPCN78; /*!< (@ 0x00006C74) FRER Discarded Packet Counter Register 78 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN78_b; + }; + + union + { + __IM uint32_t FWFRPPCN79; /*!< (@ 0x00006C78) FRER Passed Packet Counter Register 79 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN79_b; + }; + + union + { + __IM uint32_t FWFRDPCN79; /*!< (@ 0x00006C7C) FRER Discarded Packet Counter Register 79 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN79_b; + }; + + union + { + __IM uint32_t FWFRPPCN80; /*!< (@ 0x00006C80) FRER Passed Packet Counter Register 80 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN80_b; + }; + + union + { + __IM uint32_t FWFRDPCN80; /*!< (@ 0x00006C84) FRER Discarded Packet Counter Register 80 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN80_b; + }; + + union + { + __IM uint32_t FWFRPPCN81; /*!< (@ 0x00006C88) FRER Passed Packet Counter Register 81 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN81_b; + }; + + union + { + __IM uint32_t FWFRDPCN81; /*!< (@ 0x00006C8C) FRER Discarded Packet Counter Register 81 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN81_b; + }; + + union + { + __IM uint32_t FWFRPPCN82; /*!< (@ 0x00006C90) FRER Passed Packet Counter Register 82 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN82_b; + }; + + union + { + __IM uint32_t FWFRDPCN82; /*!< (@ 0x00006C94) FRER Discarded Packet Counter Register 82 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN82_b; + }; + + union + { + __IM uint32_t FWFRPPCN83; /*!< (@ 0x00006C98) FRER Passed Packet Counter Register 83 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN83_b; + }; + + union + { + __IM uint32_t FWFRDPCN83; /*!< (@ 0x00006C9C) FRER Discarded Packet Counter Register 83 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN83_b; + }; + + union + { + __IM uint32_t FWFRPPCN84; /*!< (@ 0x00006CA0) FRER Passed Packet Counter Register 84 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN84_b; + }; + + union + { + __IM uint32_t FWFRDPCN84; /*!< (@ 0x00006CA4) FRER Discarded Packet Counter Register 84 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN84_b; + }; + + union + { + __IM uint32_t FWFRPPCN85; /*!< (@ 0x00006CA8) FRER Passed Packet Counter Register 85 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN85_b; + }; + + union + { + __IM uint32_t FWFRDPCN85; /*!< (@ 0x00006CAC) FRER Discarded Packet Counter Register 85 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN85_b; + }; + + union + { + __IM uint32_t FWFRPPCN86; /*!< (@ 0x00006CB0) FRER Passed Packet Counter Register 86 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN86_b; + }; + + union + { + __IM uint32_t FWFRDPCN86; /*!< (@ 0x00006CB4) FRER Discarded Packet Counter Register 86 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN86_b; + }; + + union + { + __IM uint32_t FWFRPPCN87; /*!< (@ 0x00006CB8) FRER Passed Packet Counter Register 87 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN87_b; + }; + + union + { + __IM uint32_t FWFRDPCN87; /*!< (@ 0x00006CBC) FRER Discarded Packet Counter Register 87 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN87_b; + }; + + union + { + __IM uint32_t FWFRPPCN88; /*!< (@ 0x00006CC0) FRER Passed Packet Counter Register 88 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN88_b; + }; + + union + { + __IM uint32_t FWFRDPCN88; /*!< (@ 0x00006CC4) FRER Discarded Packet Counter Register 88 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN88_b; + }; + + union + { + __IM uint32_t FWFRPPCN89; /*!< (@ 0x00006CC8) FRER Passed Packet Counter Register 89 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN89_b; + }; + + union + { + __IM uint32_t FWFRDPCN89; /*!< (@ 0x00006CCC) FRER Discarded Packet Counter Register 89 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN89_b; + }; + + union + { + __IM uint32_t FWFRPPCN90; /*!< (@ 0x00006CD0) FRER Passed Packet Counter Register 90 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN90_b; + }; + + union + { + __IM uint32_t FWFRDPCN90; /*!< (@ 0x00006CD4) FRER Discarded Packet Counter Register 90 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN90_b; + }; + + union + { + __IM uint32_t FWFRPPCN91; /*!< (@ 0x00006CD8) FRER Passed Packet Counter Register 91 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN91_b; + }; + + union + { + __IM uint32_t FWFRDPCN91; /*!< (@ 0x00006CDC) FRER Discarded Packet Counter Register 91 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN91_b; + }; + + union + { + __IM uint32_t FWFRPPCN92; /*!< (@ 0x00006CE0) FRER Passed Packet Counter Register 92 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN92_b; + }; + + union + { + __IM uint32_t FWFRDPCN92; /*!< (@ 0x00006CE4) FRER Discarded Packet Counter Register 92 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN92_b; + }; + + union + { + __IM uint32_t FWFRPPCN93; /*!< (@ 0x00006CE8) FRER Passed Packet Counter Register 93 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN93_b; + }; + + union + { + __IM uint32_t FWFRDPCN93; /*!< (@ 0x00006CEC) FRER Discarded Packet Counter Register 93 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN93_b; + }; + + union + { + __IM uint32_t FWFRPPCN94; /*!< (@ 0x00006CF0) FRER Passed Packet Counter Register 94 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN94_b; + }; + + union + { + __IM uint32_t FWFRDPCN94; /*!< (@ 0x00006CF4) FRER Discarded Packet Counter Register 94 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN94_b; + }; + + union + { + __IM uint32_t FWFRPPCN95; /*!< (@ 0x00006CF8) FRER Passed Packet Counter Register 95 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN95_b; + }; + + union + { + __IM uint32_t FWFRDPCN95; /*!< (@ 0x00006CFC) FRER Discarded Packet Counter Register 95 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN95_b; + }; + + union + { + __IM uint32_t FWFRPPCN96; /*!< (@ 0x00006D00) FRER Passed Packet Counter Register 96 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN96_b; + }; + + union + { + __IM uint32_t FWFRDPCN96; /*!< (@ 0x00006D04) FRER Discarded Packet Counter Register 96 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN96_b; + }; + + union + { + __IM uint32_t FWFRPPCN97; /*!< (@ 0x00006D08) FRER Passed Packet Counter Register 97 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN97_b; + }; + + union + { + __IM uint32_t FWFRDPCN97; /*!< (@ 0x00006D0C) FRER Discarded Packet Counter Register 97 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN97_b; + }; + + union + { + __IM uint32_t FWFRPPCN98; /*!< (@ 0x00006D10) FRER Passed Packet Counter Register 98 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN98_b; + }; + + union + { + __IM uint32_t FWFRDPCN98; /*!< (@ 0x00006D14) FRER Discarded Packet Counter Register 98 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN98_b; + }; + + union + { + __IM uint32_t FWFRPPCN99; /*!< (@ 0x00006D18) FRER Passed Packet Counter Register 99 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN99_b; + }; + + union + { + __IM uint32_t FWFRDPCN99; /*!< (@ 0x00006D1C) FRER Discarded Packet Counter Register 99 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN99_b; + }; + + union + { + __IM uint32_t FWFRPPCN100; /*!< (@ 0x00006D20) FRER Passed Packet Counter Register 100 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN100_b; + }; + + union + { + __IM uint32_t FWFRDPCN100; /*!< (@ 0x00006D24) FRER Discarded Packet Counter Register 100 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN100_b; + }; + + union + { + __IM uint32_t FWFRPPCN101; /*!< (@ 0x00006D28) FRER Passed Packet Counter Register 101 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN101_b; + }; + + union + { + __IM uint32_t FWFRDPCN101; /*!< (@ 0x00006D2C) FRER Discarded Packet Counter Register 101 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN101_b; + }; + + union + { + __IM uint32_t FWFRPPCN102; /*!< (@ 0x00006D30) FRER Passed Packet Counter Register 102 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN102_b; + }; + + union + { + __IM uint32_t FWFRDPCN102; /*!< (@ 0x00006D34) FRER Discarded Packet Counter Register 102 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN102_b; + }; + + union + { + __IM uint32_t FWFRPPCN103; /*!< (@ 0x00006D38) FRER Passed Packet Counter Register 103 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN103_b; + }; + + union + { + __IM uint32_t FWFRDPCN103; /*!< (@ 0x00006D3C) FRER Discarded Packet Counter Register 103 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN103_b; + }; + + union + { + __IM uint32_t FWFRPPCN104; /*!< (@ 0x00006D40) FRER Passed Packet Counter Register 104 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN104_b; + }; + + union + { + __IM uint32_t FWFRDPCN104; /*!< (@ 0x00006D44) FRER Discarded Packet Counter Register 104 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN104_b; + }; + + union + { + __IM uint32_t FWFRPPCN105; /*!< (@ 0x00006D48) FRER Passed Packet Counter Register 105 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN105_b; + }; + + union + { + __IM uint32_t FWFRDPCN105; /*!< (@ 0x00006D4C) FRER Discarded Packet Counter Register 105 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN105_b; + }; + + union + { + __IM uint32_t FWFRPPCN106; /*!< (@ 0x00006D50) FRER Passed Packet Counter Register 106 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN106_b; + }; + + union + { + __IM uint32_t FWFRDPCN106; /*!< (@ 0x00006D54) FRER Discarded Packet Counter Register 106 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN106_b; + }; + + union + { + __IM uint32_t FWFRPPCN107; /*!< (@ 0x00006D58) FRER Passed Packet Counter Register 107 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN107_b; + }; + + union + { + __IM uint32_t FWFRDPCN107; /*!< (@ 0x00006D5C) FRER Discarded Packet Counter Register 107 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN107_b; + }; + + union + { + __IM uint32_t FWFRPPCN108; /*!< (@ 0x00006D60) FRER Passed Packet Counter Register 108 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN108_b; + }; + + union + { + __IM uint32_t FWFRDPCN108; /*!< (@ 0x00006D64) FRER Discarded Packet Counter Register 108 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN108_b; + }; + + union + { + __IM uint32_t FWFRPPCN109; /*!< (@ 0x00006D68) FRER Passed Packet Counter Register 109 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN109_b; + }; + + union + { + __IM uint32_t FWFRDPCN109; /*!< (@ 0x00006D6C) FRER Discarded Packet Counter Register 109 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN109_b; + }; + + union + { + __IM uint32_t FWFRPPCN110; /*!< (@ 0x00006D70) FRER Passed Packet Counter Register 110 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN110_b; + }; + + union + { + __IM uint32_t FWFRDPCN110; /*!< (@ 0x00006D74) FRER Discarded Packet Counter Register 110 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN110_b; + }; + + union + { + __IM uint32_t FWFRPPCN111; /*!< (@ 0x00006D78) FRER Passed Packet Counter Register 111 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN111_b; + }; + + union + { + __IM uint32_t FWFRDPCN111; /*!< (@ 0x00006D7C) FRER Discarded Packet Counter Register 111 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN111_b; + }; + + union + { + __IM uint32_t FWFRPPCN112; /*!< (@ 0x00006D80) FRER Passed Packet Counter Register 112 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN112_b; + }; + + union + { + __IM uint32_t FWFRDPCN112; /*!< (@ 0x00006D84) FRER Discarded Packet Counter Register 112 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN112_b; + }; + + union + { + __IM uint32_t FWFRPPCN113; /*!< (@ 0x00006D88) FRER Passed Packet Counter Register 113 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN113_b; + }; + + union + { + __IM uint32_t FWFRDPCN113; /*!< (@ 0x00006D8C) FRER Discarded Packet Counter Register 113 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN113_b; + }; + + union + { + __IM uint32_t FWFRPPCN114; /*!< (@ 0x00006D90) FRER Passed Packet Counter Register 114 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN114_b; + }; + + union + { + __IM uint32_t FWFRDPCN114; /*!< (@ 0x00006D94) FRER Discarded Packet Counter Register 114 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN114_b; + }; + + union + { + __IM uint32_t FWFRPPCN115; /*!< (@ 0x00006D98) FRER Passed Packet Counter Register 115 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN115_b; + }; + + union + { + __IM uint32_t FWFRDPCN115; /*!< (@ 0x00006D9C) FRER Discarded Packet Counter Register 115 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN115_b; + }; + + union + { + __IM uint32_t FWFRPPCN116; /*!< (@ 0x00006DA0) FRER Passed Packet Counter Register 116 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN116_b; + }; + + union + { + __IM uint32_t FWFRDPCN116; /*!< (@ 0x00006DA4) FRER Discarded Packet Counter Register 116 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN116_b; + }; + + union + { + __IM uint32_t FWFRPPCN117; /*!< (@ 0x00006DA8) FRER Passed Packet Counter Register 117 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN117_b; + }; + + union + { + __IM uint32_t FWFRDPCN117; /*!< (@ 0x00006DAC) FRER Discarded Packet Counter Register 117 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN117_b; + }; + + union + { + __IM uint32_t FWFRPPCN118; /*!< (@ 0x00006DB0) FRER Passed Packet Counter Register 118 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN118_b; + }; + + union + { + __IM uint32_t FWFRDPCN118; /*!< (@ 0x00006DB4) FRER Discarded Packet Counter Register 118 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN118_b; + }; + + union + { + __IM uint32_t FWFRPPCN119; /*!< (@ 0x00006DB8) FRER Passed Packet Counter Register 119 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN119_b; + }; + + union + { + __IM uint32_t FWFRDPCN119; /*!< (@ 0x00006DBC) FRER Discarded Packet Counter Register 119 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN119_b; + }; + + union + { + __IM uint32_t FWFRPPCN120; /*!< (@ 0x00006DC0) FRER Passed Packet Counter Register 120 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN120_b; + }; + + union + { + __IM uint32_t FWFRDPCN120; /*!< (@ 0x00006DC4) FRER Discarded Packet Counter Register 120 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN120_b; + }; + + union + { + __IM uint32_t FWFRPPCN121; /*!< (@ 0x00006DC8) FRER Passed Packet Counter Register 121 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN121_b; + }; + + union + { + __IM uint32_t FWFRDPCN121; /*!< (@ 0x00006DCC) FRER Discarded Packet Counter Register 121 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN121_b; + }; + + union + { + __IM uint32_t FWFRPPCN122; /*!< (@ 0x00006DD0) FRER Passed Packet Counter Register 122 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN122_b; + }; + + union + { + __IM uint32_t FWFRDPCN122; /*!< (@ 0x00006DD4) FRER Discarded Packet Counter Register 122 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN122_b; + }; + + union + { + __IM uint32_t FWFRPPCN123; /*!< (@ 0x00006DD8) FRER Passed Packet Counter Register 123 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN123_b; + }; + + union + { + __IM uint32_t FWFRDPCN123; /*!< (@ 0x00006DDC) FRER Discarded Packet Counter Register 123 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN123_b; + }; + + union + { + __IM uint32_t FWFRPPCN124; /*!< (@ 0x00006DE0) FRER Passed Packet Counter Register 124 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN124_b; + }; + + union + { + __IM uint32_t FWFRDPCN124; /*!< (@ 0x00006DE4) FRER Discarded Packet Counter Register 124 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN124_b; + }; + + union + { + __IM uint32_t FWFRPPCN125; /*!< (@ 0x00006DE8) FRER Passed Packet Counter Register 125 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN125_b; + }; + + union + { + __IM uint32_t FWFRDPCN125; /*!< (@ 0x00006DEC) FRER Discarded Packet Counter Register 125 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN125_b; + }; + + union + { + __IM uint32_t FWFRPPCN126; /*!< (@ 0x00006DF0) FRER Passed Packet Counter Register 126 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN126_b; + }; + + union + { + __IM uint32_t FWFRDPCN126; /*!< (@ 0x00006DF4) FRER Discarded Packet Counter Register 126 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN126_b; + }; + + union + { + __IM uint32_t FWFRPPCN127; /*!< (@ 0x00006DF8) FRER Passed Packet Counter Register 127 */ + + struct + { + __IM uint32_t PPC : 16; /*!< [15..0] Passed Packet Count */ + uint32_t : 16; + } FWFRPPCN127_b; + }; + + union + { + __IM uint32_t FWFRDPCN127; /*!< (@ 0x00006DFC) FRER Discarded Packet Counter Register 127 */ + + struct + { + __IM uint32_t DPC : 16; /*!< [15..0] Discarded Packet Count */ + uint32_t : 16; + } FWFRDPCN127_b; + }; + __IM uint32_t RESERVED261[704]; + + union + { + __IOM uint32_t FWEIS00; /*!< (@ 0x00007900) Error Interrupt Status Register 00 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS00_b; + }; + + union + { + __IOM uint32_t FWEIE00; /*!< (@ 0x00007904) Error Interrupt Enable Register 00 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE00_b; + }; + + union + { + __IOM uint32_t FWEID00; /*!< (@ 0x00007908) Error Interrupt Disable Register 00 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID00_b; + }; + __IM uint32_t RESERVED262; + + union + { + __IOM uint32_t FWEIS01; /*!< (@ 0x00007910) Error Interrupt Status Register 01 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS01_b; + }; + + union + { + __IOM uint32_t FWEIE01; /*!< (@ 0x00007914) Error Interrupt Enable Register 01 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE01_b; + }; + + union + { + __IOM uint32_t FWEID01; /*!< (@ 0x00007918) Error Interrupt Disable Register 01 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID01_b; + }; + __IM uint32_t RESERVED263; + + union + { + __IOM uint32_t FWEIS02; /*!< (@ 0x00007920) Error Interrupt Status Register 02 */ + + struct + { + __IOM uint32_t LTHSPFS : 1; /*!< [0..0] Layer 3 Source Port Filtering Status */ + uint32_t : 1; + __IOM uint32_t LTHNTFS : 1; /*!< [2..2] Layer 3 No Target Filtering Status */ + __IOM uint32_t LTHUFS : 1; /*!< [3..3] Layer 3 Unknown Filtering Status */ + uint32_t : 6; + __IOM uint32_t LTWDSPFS : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Status */ + __IOM uint32_t LTWSSPFS : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Status */ + __IOM uint32_t LTWVSPFS : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Status */ + __IOM uint32_t LTWNTFS : 1; /*!< [13..13] Layer 2 No Target Filtering Status */ + __IOM uint32_t LTWSUFS : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Status */ + __IOM uint32_t LTWDUFS : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Status */ + __IOM uint32_t LTWVUFS : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Status */ + __IOM uint32_t PBNTFS : 1; /*!< [17..17] Port Based No Target Filtering Status */ + __IOM uint32_t SMHLFS : 1; /*!< [18..18] Source MAC Hardware Learning Fail Status */ + __IOM uint32_t SMHMFS : 1; /*!< [19..19] Source MAC Hardware Migration Fail Status */ + uint32_t : 2; + __IOM uint32_t WMCFS : 1; /*!< [22..22] Watermark Critical Filtering Status */ + __IOM uint32_t WMFFS : 1; /*!< [23..23] Watermark Flush Filtering Status */ + __IOM uint32_t WMISFS : 1; /*!< [24..24] Watermark IPV Secure Filtering Status */ + __IOM uint32_t WMIUFS : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Status */ + __IOM uint32_t DDES : 1; /*!< [26..26] Direct Descriptor Error Status i */ + uint32_t : 1; + __IOM uint32_t DDSES : 1; /*!< [28..28] Direct Descriptor Security Error Status */ + __IOM uint32_t DDNTFS : 1; /*!< [29..29] Direct Descriptor No Target Filtering Status */ + uint32_t : 2; + } FWEIS02_b; + }; + + union + { + __IOM uint32_t FWEIE02; /*!< (@ 0x00007924) Error Interrupt Enable Register 02 */ + + struct + { + __IOM uint32_t LTHSPFE : 1; /*!< [0..0] Layer 3 Source Port Filtering Enable */ + uint32_t : 1; + __IOM uint32_t LTHNTFE : 1; /*!< [2..2] Layer 3 No Target Filtering Enable */ + __IOM uint32_t LTHUFE : 1; /*!< [3..3] Layer 3 Unknown Filtering Enable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFE : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Enable */ + __IOM uint32_t LTWSSPFE : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Enable */ + __IOM uint32_t LTWVSPFE : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Enable */ + __IOM uint32_t LTWNTFE : 1; /*!< [13..13] Layer 2 No Target Filtering Enable */ + __IOM uint32_t LTWSUFE : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Enable */ + __IOM uint32_t LTWDUFE : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Enable */ + __IOM uint32_t LTWVUFE : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Enable */ + __IOM uint32_t PBNTFE : 1; /*!< [17..17] Port Based No Target Filtering Enable */ + __IOM uint32_t SMHLFE : 1; /*!< [18..18] Source MAC Hardware Learning Fail Enable */ + __IOM uint32_t SMHMFE : 1; /*!< [19..19] Source MAC Hardware Migration Fail Enable */ + uint32_t : 2; + __IOM uint32_t WMCFE : 1; /*!< [22..22] Watermark Critical Filtering Enable */ + __IOM uint32_t WMFFE : 1; /*!< [23..23] Watermark Flush Filtering Enable */ + __IOM uint32_t WMISFE : 1; /*!< [24..24] Watermark IPV Secure Filtering Enable */ + __IOM uint32_t WMIUFE : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Enable */ + __IOM uint32_t DDEE : 1; /*!< [26..26] Direct Descriptor Error Enable */ + __IOM uint32_t DDFEE : 1; /*!< [27..27] Direct Descriptor Format Error Enable */ + __IOM uint32_t DDSEE : 1; /*!< [28..28] Direct Descriptor Security Error Enable */ + __IOM uint32_t DDNTFE : 1; /*!< [29..29] Direct Descriptor No Target Filtering Enable */ + uint32_t : 2; + } FWEIE02_b; + }; + + union + { + __IOM uint32_t FWEID02; /*!< (@ 0x00007928) Error Interrupt Disable Register 02 */ + + struct + { + __IOM uint32_t LTHSPFD : 1; /*!< [0..0] Layer 3 Source Port Filtering Disable */ + uint32_t : 1; + __IOM uint32_t LTHNTFD : 1; /*!< [2..2] Layer 3 No Target Filtering Disable */ + __IOM uint32_t LTHUFD : 1; /*!< [3..3] Layer 3 Unknown Filtering Disable */ + uint32_t : 6; + __IOM uint32_t LTWDSPFD : 1; /*!< [10..10] Layer 2 Destination Source Port Filtering Disable */ + __IOM uint32_t LTWSSPFD : 1; /*!< [11..11] Layer 2 Source Source Port Filtering Disable */ + __IOM uint32_t LTWVSPFD : 1; /*!< [12..12] Layer 2 VLAN Source Port Filtering Disable */ + __IOM uint32_t LTWNTFD : 1; /*!< [13..13] Layer 2 No Target Filtering Disable */ + __IOM uint32_t LTWSUFD : 1; /*!< [14..14] Layer 2 Source Unknown Filtering Disable */ + __IOM uint32_t LTWDUFD : 1; /*!< [15..15] Layer 2 Destination Unknown Filtering Disable */ + __IOM uint32_t LTWVUFD : 1; /*!< [16..16] Layer 2 VLAN Unknown Filtering Disable */ + __IOM uint32_t PBNTFD : 1; /*!< [17..17] Port Based No Target Filtering Disable */ + __IOM uint32_t SMHLFD : 1; /*!< [18..18] Source MAC Hardware Learning Fail Disable */ + __IOM uint32_t SMHMFD : 1; /*!< [19..19] Source MAC Hardware Migration Fail Disable */ + uint32_t : 2; + __IOM uint32_t WMCFD : 1; /*!< [22..22] Watermark Critical Filtering Disable */ + __IOM uint32_t WMFFD : 1; /*!< [23..23] Watermark Flush Filtering Disable */ + __IOM uint32_t WMISFD : 1; /*!< [24..24] Watermark IPV Secure Filtering Disable */ + __IOM uint32_t WMIUFD : 1; /*!< [25..25] Watermark IPV Unsecure Filtering Disable */ + __IOM uint32_t DDED : 1; /*!< [26..26] Direct Descriptor Error Disable */ + __IOM uint32_t DDFED : 1; /*!< [27..27] Direct Descriptor Format Error Disable */ + __IOM uint32_t DDSED : 1; /*!< [28..28] Direct Descriptor Security Error Disable */ + __IOM uint32_t DDNTFD : 1; /*!< [29..29] Direct Descriptor No Target Filtering Disable */ + uint32_t : 2; + } FWEID02_b; + }; + __IM uint32_t RESERVED264[53]; + + union + { + __IOM uint32_t FWEIS1; /*!< (@ 0x00007A00) Error Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t LTHTEES : 1; /*!< [0..0] L3 Table ECC Error Status */ + __IOM uint32_t LTHTSES : 1; /*!< [1..1] L3 Table Security Error Status */ + uint32_t : 2; + __IOM uint32_t MACTEES : 1; /*!< [4..4] MAC Table ECC Error Status */ + __IOM uint32_t MACTSES : 1; /*!< [5..5] MAC Table Security Error Status */ + __IOM uint32_t VLANTEES : 1; /*!< [6..6] VLAN Table ECC Error Status */ + __IOM uint32_t VLANTSES : 1; /*!< [7..7] VLAN Table Security Error Status */ + __IOM uint32_t L23UEES : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Status */ + uint32_t : 7; + __IOM uint32_t AREES : 1; /*!< [16..16] ATS RAM ECC Error Status */ + uint32_t : 15; + } FWEIS1_b; + }; + + union + { + __IOM uint32_t FWEIE1; /*!< (@ 0x00007A04) Error Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t LTHTEEE : 1; /*!< [0..0] L3 Table ECC Error Enable */ + __IOM uint32_t LTHTSEE : 1; /*!< [1..1] L3 Table Security Error Enable */ + uint32_t : 2; + __IOM uint32_t MACTEEE : 1; /*!< [4..4] MAC Table ECC Error Enable */ + __IOM uint32_t MACTSEE : 1; /*!< [5..5] MAC Table Security Error Enable */ + __IOM uint32_t VLANTEEE : 1; /*!< [6..6] VLAN Table ECC Error Enable */ + __IOM uint32_t VLANTSEE : 1; /*!< [7..7] VLAN Table Security Error Enable */ + __IOM uint32_t L23UEEE : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Enable */ + uint32_t : 7; + __IOM uint32_t AREEE : 1; /*!< [16..16] ATS RAM ECC Error Enable */ + uint32_t : 15; + } FWEIE1_b; + }; + + union + { + __IOM uint32_t FWEID1; /*!< (@ 0x00007A08) Error Interrupt Disable Register 1 */ + + struct + { + __IOM uint32_t LTHTEED : 1; /*!< [0..0] L3 Table ECC Error Disable */ + __IOM uint32_t LTHTSED : 1; /*!< [1..1] L3 Table Security Error Disable */ + uint32_t : 2; + __IOM uint32_t MACTEED : 1; /*!< [4..4] MAC Table ECC Error Disable */ + __IOM uint32_t MACTSED : 1; /*!< [5..5] MAC Table Security Error Disable */ + __IOM uint32_t VLANTEED : 1; /*!< [6..6] VLAN Table ECC Error Disable */ + __IOM uint32_t VLANTSED : 1; /*!< [7..7] VLAN Table Security Error Disable */ + __IOM uint32_t L23UEED : 1; /*!< [8..8] Layer 2/Layer 3 Update ECC Error Disable */ + uint32_t : 7; + __IOM uint32_t AREED : 1; /*!< [16..16] ATS RAM ECC Error Disable */ + uint32_t : 15; + } FWEID1_b; + }; + __IM uint32_t RESERVED265; + + union + { + __IOM uint32_t FWEIS2; /*!< (@ 0x00007A10) Error Interrupt Status Register 2 */ + + struct + { + __IOM uint32_t PMFS : 16; /*!< [15..0] PSFP MSDU Filtering Status */ + uint32_t : 16; + } FWEIS2_b; + }; + + union + { + __IOM uint32_t FWEIE2; /*!< (@ 0x00007A14) Error Interrupt Enable Register 2 */ + + struct + { + __IOM uint32_t PMFE : 16; /*!< [15..0] PSFP MSDU Filtering Enable */ + uint32_t : 16; + } FWEIE2_b; + }; + + union + { + __IOM uint32_t FWEID2; /*!< (@ 0x00007A18) Error Interrupt Disable Register 2 */ + + struct + { + __IOM uint32_t PMFD : 16; /*!< [15..0] PSFP MSDU Filtering Disable */ + uint32_t : 16; + } FWEID2_b; + }; + __IM uint32_t RESERVED266[9]; + + union + { + __IOM uint32_t FWEIS5; /*!< (@ 0x00007A40) Error Interrupt Status Register 5 */ + + struct + { + __IOM uint32_t PMRFS : 32; /*!< [31..0] PSFP Meter Filtering Status */ + } FWEIS5_b; + }; + + union + { + __IOM uint32_t FWEIE5; /*!< (@ 0x00007A44) Error Interrupt Enable Register 5 */ + + struct + { + __IOM uint32_t PMRFE : 32; /*!< [31..0] PSFP Meter Filtering Enable */ + } FWEIE5_b; + }; + + union + { + __IOM uint32_t FWEID5; /*!< (@ 0x00007A48) Error Interrupt Disable Register 5 */ + + struct + { + __IOM uint32_t PMRFD : 32; /*!< [31..0] PSFP Meter Filtering Disable */ + } FWEID5_b; + }; + __IM uint32_t RESERVED267; + + union + { + __IOM uint32_t FWEIS60; /*!< (@ 0x00007A50) Error Interrupt Status Register 60 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS60_b; + }; + + union + { + __IOM uint32_t FWEIE60; /*!< (@ 0x00007A54) Error Interrupt Enable Register 60 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE60_b; + }; + + union + { + __IOM uint32_t FWEID60; /*!< (@ 0x00007A58) Error Interrupt Disable Register 60 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID60_b; + }; + __IM uint32_t RESERVED268; + + union + { + __IOM uint32_t FWEIS61; /*!< (@ 0x00007A60) Error Interrupt Status Register 61 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS61_b; + }; + + union + { + __IOM uint32_t FWEIE61; /*!< (@ 0x00007A64) Error Interrupt Enable Register 61 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE61_b; + }; + + union + { + __IOM uint32_t FWEID61; /*!< (@ 0x00007A68) Error Interrupt Disable Register 61 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID61_b; + }; + __IM uint32_t RESERVED269; + + union + { + __IOM uint32_t FWEIS62; /*!< (@ 0x00007A70) Error Interrupt Status Register 62 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS62_b; + }; + + union + { + __IOM uint32_t FWEIE62; /*!< (@ 0x00007A74) Error Interrupt Enable Register 62 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE62_b; + }; + + union + { + __IOM uint32_t FWEID62; /*!< (@ 0x00007A78) Error Interrupt Disable Register 62 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID62_b; + }; + __IM uint32_t RESERVED270; + + union + { + __IOM uint32_t FWEIS63; /*!< (@ 0x00007A80) Error Interrupt Status Register 63 */ + + struct + { + __IOM uint32_t FFS : 32; /*!< [31..0] FRER Filtering Status */ + } FWEIS63_b; + }; + + union + { + __IOM uint32_t FWEIE63; /*!< (@ 0x00007A84) Error Interrupt Enable Register 63 */ + + struct + { + __IOM uint32_t FFE : 32; /*!< [31..0] FRER Filtering Enable */ + } FWEIE63_b; + }; + + union + { + __IOM uint32_t FWEID63; /*!< (@ 0x00007A88) Error Interrupt Disable Register 63 */ + + struct + { + __IOM uint32_t FFD : 32; /*!< [31..0] FRER Filtering Disable */ + } FWEID63_b; + }; + __IM uint32_t RESERVED271; + + union + { + __IOM uint32_t FWEIS70; /*!< (@ 0x00007A90) Error Interrupt Status Register 70 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS70_b; + }; + + union + { + __IOM uint32_t FWEIE70; /*!< (@ 0x00007A94) Error Interrupt Enable Register 70 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE70_b; + }; + + union + { + __IOM uint32_t FWEID70; /*!< (@ 0x00007A98) Error Interrupt Disable Register 70 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID70_b; + }; + __IM uint32_t RESERVED272; + + union + { + __IOM uint32_t FWEIS71; /*!< (@ 0x00007AA0) Error Interrupt Status Register 71 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS71_b; + }; + + union + { + __IOM uint32_t FWEIE71; /*!< (@ 0x00007AA4) Error Interrupt Enable Register 71 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE71_b; + }; + + union + { + __IOM uint32_t FWEID71; /*!< (@ 0x00007AA8) Error Interrupt Disable Register 71 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID71_b; + }; + __IM uint32_t RESERVED273; + + union + { + __IOM uint32_t FWEIS72; /*!< (@ 0x00007AB0) Error Interrupt Status Register 72 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS72_b; + }; + + union + { + __IOM uint32_t FWEIE72; /*!< (@ 0x00007AB4) Error Interrupt Enable Register 72 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE72_b; + }; + + union + { + __IOM uint32_t FWEID72; /*!< (@ 0x00007AB8) Error Interrupt Disable Register 72 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID72_b; + }; + __IM uint32_t RESERVED274; + + union + { + __IOM uint32_t FWEIS73; /*!< (@ 0x00007AC0) Error Interrupt Status Register 73 */ + + struct + { + __IOM uint32_t FOORS : 32; /*!< [31..0] FRER Out Of Range Status */ + } FWEIS73_b; + }; + + union + { + __IOM uint32_t FWEIE73; /*!< (@ 0x00007AC4) Error Interrupt Enable Register 73 */ + + struct + { + __IOM uint32_t FOORE : 32; /*!< [31..0] FRER Out Of Range Enable */ + } FWEIE73_b; + }; + + union + { + __IOM uint32_t FWEID73; /*!< (@ 0x00007AC8) Error Interrupt Disable Register 73 */ + + struct + { + __IOM uint32_t FOORD : 32; /*!< [31..0] FRER Out Of Range Disable */ + } FWEID73_b; + }; + __IM uint32_t RESERVED275; + + union + { + __IOM uint32_t FWEIS80; /*!< (@ 0x00007AD0) Error Interrupt Status Register 80 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS80_b; + }; + + union + { + __IOM uint32_t FWEIE80; /*!< (@ 0x00007AD4) Error Interrupt Enable Register 80 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE80_b; + }; + + union + { + __IOM uint32_t FWEID80; /*!< (@ 0x00007AD8) Error Interrupt Disable Register 80 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID80_b; + }; + __IM uint32_t RESERVED276; + + union + { + __IOM uint32_t FWEIS81; /*!< (@ 0x00007AE0) Error Interrupt Status Register 81 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS81_b; + }; + + union + { + __IOM uint32_t FWEIE81; /*!< (@ 0x00007AE4) Error Interrupt Enable Register 81 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE81_b; + }; + + union + { + __IOM uint32_t FWEID81; /*!< (@ 0x00007AE8) Error Interrupt Disable Register 81 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID81_b; + }; + __IM uint32_t RESERVED277; + + union + { + __IOM uint32_t FWEIS82; /*!< (@ 0x00007AF0) Error Interrupt Status Register 82 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS82_b; + }; + + union + { + __IOM uint32_t FWEIE82; /*!< (@ 0x00007AF4) Error Interrupt Enable Register 82 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE82_b; + }; + + union + { + __IOM uint32_t FWEID82; /*!< (@ 0x00007AF8) Error Interrupt Disable Register 82 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID82_b; + }; + __IM uint32_t RESERVED278; + + union + { + __IOM uint32_t FWEIS83; /*!< (@ 0x00007B00) Error Interrupt Status Register 83 */ + + struct + { + __IOM uint32_t TOS : 32; /*!< [31..0] Timeout Status */ + } FWEIS83_b; + }; + + union + { + __IOM uint32_t FWEIE83; /*!< (@ 0x00007B04) Error Interrupt Enable Register 83 */ + + struct + { + __IOM uint32_t TOE : 32; /*!< [31..0] Timeout Enable */ + } FWEIE83_b; + }; + + union + { + __IOM uint32_t FWEID83; /*!< (@ 0x00007B08) Error Interrupt Disable Register 83 */ + + struct + { + __IOM uint32_t TOD : 32; /*!< [31..0] Timeout Disable */ + } FWEID83_b; + }; + __IM uint32_t RESERVED279[61]; + + union + { + __IOM uint32_t FWMIS0; /*!< (@ 0x00007C00) Monitoring Interrupt Status Register 0 */ + + struct + { + __IOM uint32_t LTHTFS : 1; /*!< [0..0] L3 Table Full Status */ + uint32_t : 1; + __IOM uint32_t MACTFS : 1; /*!< [2..2] MAC Table Full Status */ + __IOM uint32_t VLANTFS : 1; /*!< [3..3] VLAN Table Full Status */ + uint32_t : 13; + __IOM uint32_t MACADAS : 1; /*!< [17..17] MAC Address Deleted Aging Status */ + uint32_t : 14; + } FWMIS0_b; + }; + + union + { + __IOM uint32_t FWMIE0; /*!< (@ 0x00007C04) Monitoring Interrupt Enable Register 0 */ + + struct + { + __IOM uint32_t LTHTFE : 1; /*!< [0..0] L3 Table Full Enable */ + uint32_t : 1; + __IOM uint32_t MACTFE : 1; /*!< [2..2] MAC Table Full Enable */ + __IOM uint32_t VLANTFE : 1; /*!< [3..3] VLAN Table Full Enable */ + uint32_t : 13; + __IOM uint32_t MACADAE : 1; /*!< [17..17] MAC Address Deleted Aging Enable */ + uint32_t : 14; + } FWMIE0_b; + }; + + union + { + __IOM uint32_t FWMID0; /*!< (@ 0x00007C08) Monitoring Interrupt Disable Register 0 */ + + struct + { + __IOM uint32_t LTHTFD : 1; /*!< [0..0] L3 Table Full Disable */ + uint32_t : 1; + __IOM uint32_t MACTFD : 1; /*!< [2..2] MAC Table Full Disable */ + __IOM uint32_t VLANTFD : 1; /*!< [3..3] VLAN Table Full Disable */ + uint32_t : 13; + __IOM uint32_t MACADAD : 1; /*!< [17..17] MAC Address Deleted Aging Disable */ + uint32_t : 14; + } FWMID0_b; + }; +} R_MFWD_Type; /*!< Size = 31756 (0x7c0c) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DSI Link (R_MIPI_DSI) + */ + +typedef struct /*!< (@ 0x40346000) R_MIPI_DSI Structure */ +{ + union + { + __IM uint32_t ISR; /*!< (@ 0x00000000) Interrupt Status Register */ + + struct + { + __IM uint32_t SQ0 : 1; /*!< [0..0] Sequence Channel-0 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t SQ1 : 1; /*!< [4..4] Sequence Channel-1 Interrupt Flag */ + uint32_t : 3; + __IM uint32_t VM : 1; /*!< [8..8] Video Mode Interrupt Flag */ + uint32_t : 3; + __IM uint32_t RCV : 1; /*!< [12..12] Receive Interrupt Flag */ + uint32_t : 3; + __IM uint32_t FERR : 1; /*!< [16..16] Fatal Error Interrupt Flag */ + uint32_t : 3; + __IM uint32_t PPI : 1; /*!< [20..20] PPI Interrupt Flag */ + uint32_t : 11; + } ISR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IM uint32_t LINKSR; /*!< (@ 0x00000010) Link Status Register */ + + struct + { + __IM uint32_t SQ0RUN : 1; /*!< [0..0] Sequence Channel-0 Running Flag */ + uint32_t : 3; + __IM uint32_t SQ1RUN : 1; /*!< [4..4] Sequence Channel-1 Running Flag */ + uint32_t : 3; + __IM uint32_t VRUN : 1; /*!< [8..8] Video Mode Operation Running Flag */ + uint32_t : 3; + __IM uint32_t HSBUSY : 1; /*!< [12..12] HS Operation Busy Flag */ + __IM uint32_t LPBUSY : 1; /*!< [13..13] LP Operation Busy Flag */ + uint32_t : 18; + } LINKSR_b; + }; + __IM uint32_t RESERVED1[59]; + + union + { + __IOM uint32_t TXSETR; /*!< (@ 0x00000100) Transmit Set Register */ + + struct + { + __IOM uint32_t NUMLANE : 2; /*!< [1..0] Number of Lane */ + uint32_t : 6; + __IOM uint32_t CLEN : 1; /*!< [8..8] Clock Lane Enable */ + __IOM uint32_t DLEN : 1; /*!< [9..9] Data Lane Enable */ + uint32_t : 22; + } TXSETR_b; + }; + + union + { + __IOM uint32_t HSCLKSETR; /*!< (@ 0x00000104) HS Clock Set Register */ + + struct + { + __IOM uint32_t HSCLST : 1; /*!< [0..0] HS Clock Start */ + __IOM uint32_t HSCLMD : 1; /*!< [1..1] HS Clock Running Mode */ + uint32_t : 30; + } HSCLKSETR_b; + }; + + union + { + __IOM uint32_t ULPSSETR; /*!< (@ 0x00000108) ULPS Set Register */ + + struct + { + __IOM uint32_t WKUP : 8; /*!< [7..0] ULPS Wakeup Period */ + uint32_t : 24; + } ULPSSETR_b; + }; + + union + { + __OM uint32_t ULPSCR; /*!< (@ 0x0000010C) ULPS Control Register */ + + struct + { + uint32_t : 24; + __OM uint32_t CLENT : 1; /*!< [24..24] CL ULPS Enter */ + __OM uint32_t CLEXIT : 1; /*!< [25..25] CL ULPS Exit */ + uint32_t : 2; + __OM uint32_t DLENT : 1; /*!< [28..28] DL ULPS Enter */ + __OM uint32_t DLEXIT : 1; /*!< [29..29] DL ULPS Exit */ + uint32_t : 2; + } ULPSCR_b; + }; + + union + { + __IOM uint32_t RSTCR; /*!< (@ 0x00000110) Reset Control Register */ + + struct + { + __IOM uint32_t SWRST : 1; /*!< [0..0] Software Reset */ + uint32_t : 15; + __IOM uint32_t FTXSTP : 1; /*!< [16..16] Force Tx Stop Mode */ + uint32_t : 15; + } RSTCR_b; + }; + + union + { + __IM uint32_t RSTSR; /*!< (@ 0x00000114) Reset Status Register */ + + struct + { + __IM uint32_t RSTHS : 1; /*!< [0..0] HS Software Reset Status */ + __IM uint32_t RSTLP : 1; /*!< [1..1] LP Software Reset Status */ + __IM uint32_t RSTAPB : 1; /*!< [2..2] APB Software Reset Status */ + __IM uint32_t RSTAXI : 1; /*!< [3..3] AXI Software Reset Status */ + __IM uint32_t RSTV : 1; /*!< [4..4] Video Software Reset Status */ + uint32_t : 3; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 5; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 16; + } RSTSR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t DSISETR; /*!< (@ 0x00000120) DSI Set Register */ + + struct + { + __IOM uint32_t MRPSZ : 16; /*!< [15..0] Maximum Return Packet Size */ + __IOM uint32_t ECCEN : 1; /*!< [16..16] ECC Check Enable */ + uint32_t : 3; + __IOM uint32_t VC0CRCEN : 1; /*!< [20..20] VC-0 CRC Check Enable */ + __IOM uint32_t VC1CRCEN : 1; /*!< [21..21] VC-1 CRC Check Enable */ + __IOM uint32_t VC2CRCEN : 1; /*!< [22..22] VC-2 CRC Check Enable */ + __IOM uint32_t VC3CRCEN : 1; /*!< [23..23] VC-3 CRC Check Enable */ + uint32_t : 5; + __IOM uint32_t SCREN : 1; /*!< [29..29] Data Scramble Enable */ + __IOM uint32_t EXTEMD : 1; /*!< [30..30] External Tearing Effect Detection Sense Select */ + __IOM uint32_t EOTPEN : 1; /*!< [31..31] HS Transfer EoTp Enable */ + } DSISETR_b; + }; + __IM uint32_t RESERVED3[15]; + + union + { + __IOM uint32_t TXPPD0R; /*!< (@ 0x00000160) Transmit Packet Payload Data 0 Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IOM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IOM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } TXPPD0R_b; + }; + + union + { + __IOM uint32_t TXPPD1R; /*!< (@ 0x00000164) Transmit Packet Payload Data 1 Register */ + + struct + { + __IOM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 4 */ + __IOM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 5 */ + __IOM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 6 */ + __IOM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 7 */ + } TXPPD1R_b; + }; + + union + { + __IOM uint32_t TXPPD2R; /*!< (@ 0x00000168) Transmit Packet Payload Data 2 Register */ + + struct + { + __IOM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IOM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IOM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IOM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } TXPPD2R_b; + }; + + union + { + __IOM uint32_t TXPPD3R; /*!< (@ 0x0000016C) Transmit Packet Payload Data 3 Register */ + + struct + { + __IOM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IOM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IOM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IOM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } TXPPD3R_b; + }; + __IM uint32_t RESERVED4[36]; + + union + { + __IM uint32_t RXSR; /*!< (@ 0x00000200) Receive Status Register */ + + struct + { + __IM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 5; + __IM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag */ + uint32_t : 2; + __IM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag */ + __IM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag */ + __IM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag */ + __IM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag */ + __IM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag */ + __IM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag */ + __IM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag */ + __IM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag */ + __IM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag */ + __IM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag */ + __IM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag */ + __IM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag */ + uint32_t : 1; + } RXSR_b; + }; + + union + { + __IOM uint32_t RXSCR; /*!< (@ 0x00000204) Receive Status Clear Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag Clear */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag Clear */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Flag Clear */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag Clear */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Flag Clear */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Flag Clear */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Flag Clear */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag Clear */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag Clear */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag Clear */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag + * Clear */ + uint32_t : 1; + } RXSCR_b; + }; + + union + { + __IOM uint32_t RXIER; /*!< (@ 0x00000208) Receive Interrupt Enable Register */ + + struct + { + __IOM uint32_t BTAREND : 1; /*!< [0..0] BTA Request End Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t RXRESP : 1; /*!< [8..8] Response Packet Receive Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXEOTP : 1; /*!< [10..10] EoTp Receive Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RXTE : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Enable */ + __IOM uint32_t RXACK : 1; /*!< [14..14] ACK Trigger Receive Interrupt Enable */ + __IOM uint32_t EXTEDET : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Enable */ + __IOM uint32_t MLFERR : 1; /*!< [16..16] Malform Error Interrupt Enable */ + __IOM uint32_t ECCERRM : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Enable */ + __IOM uint32_t UNEXERR : 1; /*!< [18..18] Unexpected Packet Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t WCERR : 1; /*!< [20..20] Word Count Error Interrupt Enable */ + __IOM uint32_t CRCERR : 1; /*!< [21..21] CRC Error Interrupt Enable */ + __IOM uint32_t IBERR : 1; /*!< [22..22] Internal Bus Error Interrupt Enable */ + __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Enable */ + __IOM uint32_t PRTOERR : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Enable */ + __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Enable */ + __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t ECCERRS : 1; /*!< [28..28] Single Bit ECC Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXAKE : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Enable */ + uint32_t : 1; + } RXIER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t PRESPTOBTASETR; /*!< (@ 0x00000210) Peripheral Response Timeout BTA Set Register */ + + struct + { + __IOM uint32_t PRTBTA : 32; /*!< [31..0] Peripheral Response Timeout Count */ + } PRESPTOBTASETR_b; + }; + + union + { + __IOM uint32_t PRESPTOLPSETR; /*!< (@ 0x00000214) Peripheral Response Timeout LP Set Register */ + + struct + { + __IOM uint32_t LPWTO : 16; /*!< [15..0] LPDT WRITE Request Timeout */ + __IOM uint32_t LPRTO : 16; /*!< [31..16] LPDT READ Request Timeout */ + } PRESPTOLPSETR_b; + }; + + union + { + __IOM uint32_t PRESPTOHSSETR; /*!< (@ 0x00000218) Peripheral Response Timeout HS Set Register */ + + struct + { + __IOM uint32_t HSWTO : 16; /*!< [15..0] HS WRITE Request Timeout */ + __IOM uint32_t HSRTO : 16; /*!< [31..16] HS READ Request Timeout */ + } PRESPTOHSSETR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IM uint32_t AKEPLATIR; /*!< (@ 0x00000220) Acknowledge and Error Report Packet Parameter + * Latest Info Register */ + + struct + { + __IM uint32_t EREP : 16; /*!< [15..0] Error Report */ + __IM uint32_t VC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPLATIR_b; + }; + + union + { + __IM uint32_t AKEPACMSR; /*!< (@ 0x00000224) Acknowledge and Error Report Packet Parameter + * Accumulate Status Register */ + + struct + { + __IM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPACMSR_b; + }; + + union + { + __IOM uint32_t AKEPSCR; /*!< (@ 0x00000228) Acknowledge and Error Report Packet Parameter + * Status Clear Register */ + + struct + { + __IOM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report Clear */ + __IM uint32_t AVC : 4; /*!< [19..16] Virtual Channel ID */ + uint32_t : 12; + } AKEPSCR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RXRSSR; /*!< (@ 0x00000230) Receive Result Saved Status Register */ + + struct + { + __IM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag */ + __IM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag */ + __IM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag */ + __IM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag */ + uint32_t : 28; + } RXRSSR_b; + }; + + union + { + __IOM uint32_t RXRSSCR; /*!< (@ 0x00000234) Receive Result Saved Status Clear Register */ + + struct + { + __IOM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag Clear */ + __IOM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag Clear */ + __IOM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag Clear */ + __IOM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag Clear */ + uint32_t : 28; + } RXRSSCR_b; + }; + + union + { + __IM uint32_t RXRINFOOWSR; /*!< (@ 0x00000238) Receive Result Info Overwrite Status Register */ + + struct + { + __IM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag */ + __IM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag */ + __IM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag */ + __IM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag */ + uint32_t : 28; + } RXRINFOOWSR_b; + }; + + union + { + __IOM uint32_t RXRINFOOWSCR; /*!< (@ 0x0000023C) Receive Result Info Overwrite Status Clear Register */ + + struct + { + __IOM uint32_t SL0OW : 1; /*!< [0..0] Slot-0 Information Overwrite Flag Clear */ + __IOM uint32_t SL1OW : 1; /*!< [1..1] Slot-1 Information Overwrite Flag Clear */ + __IOM uint32_t SL2OW : 1; /*!< [2..2] Slot-2 Information Overwrite Flag Clear */ + __IOM uint32_t SL3OW : 1; /*!< [3..3] Slot-3 Information Overwrite Flag Clear */ + uint32_t : 28; + } RXRINFOOWSCR_b; + }; + + union + { + union + { + __IM uint32_t RXRSS0R; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS0R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS0R_L; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS0R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_LL; /*!< (@ 0x00000240) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS0R_LL_b; + }; + + union + { + __IM uint8_t RXRSS0R_LH; /*!< (@ 0x00000241) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS0R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS0R_H; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS0R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS0R_HL; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS0R_HL_b; + }; + + union + { + __IM uint8_t RXRSS0R_HH; /*!< (@ 0x00000243) Receive Result Save Slot-0 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS0R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS1R; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS1R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS1R_L; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS1R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_LL; /*!< (@ 0x00000244) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS1R_LL_b; + }; + + union + { + __IM uint8_t RXRSS1R_LH; /*!< (@ 0x00000245) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS1R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS1R_H; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS1R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS1R_HL; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS1R_HL_b; + }; + + union + { + __IM uint8_t RXRSS1R_HH; /*!< (@ 0x00000247) Receive Result Save Slot-1 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS1R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS2R; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS2R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS2R_L; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS2R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_LL; /*!< (@ 0x00000248) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS2R_LL_b; + }; + + union + { + __IM uint8_t RXRSS2R_LH; /*!< (@ 0x00000249) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS2R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS2R_H; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS2R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS2R_HL; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS2R_HL_b; + }; + + union + { + __IM uint8_t RXRSS2R_HH; /*!< (@ 0x0000024B) Receive Result Save Slot-2 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS2R_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IM uint32_t RXRSS3R; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IM uint32_t FMT : 1; /*!< [24..24] Packet Format */ + __IM uint32_t RXSUC : 1; /*!< [25..25] Receive Success */ + __IM uint32_t RXFERR : 1; /*!< [26..26] Fatal Error */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail */ + __IM uint32_t RXCERR : 1; /*!< [29..29] Receive Correctable Error */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet */ + __IM uint32_t INFOOW : 1; /*!< [31..31] Information Overwrite */ + } RXRSS3R_b; + }; + + struct + { + union + { + union + { + __IM uint16_t RXRSS3R_L; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } RXRSS3R_L_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_LL; /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } RXRSS3R_LL_b; + }; + + union + { + __IM uint8_t RXRSS3R_LH; /*!< (@ 0x0000024D) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } RXRSS3R_LH_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RXRSS3R_H; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IM uint16_t FMT : 1; /*!< [8..8] Packet Format */ + __IM uint16_t RXSUC : 1; /*!< [9..9] Receive Success */ + __IM uint16_t RXFERR : 1; /*!< [10..10] Fatal Error */ + __IM uint16_t RXFAIL : 1; /*!< [11..11] Receive Fail */ + __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail */ + __IM uint16_t RXCERR : 1; /*!< [13..13] Receive Correctable Error */ + __IM uint16_t RXAKE : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet */ + __IM uint16_t INFOOW : 1; /*!< [15..15] Information Overwrite */ + } RXRSS3R_H_b; + }; + + struct + { + union + { + __IM uint8_t RXRSS3R_HL; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } RXRSS3R_HL_b; + }; + + union + { + __IM uint8_t RXRSS3R_HH; /*!< (@ 0x0000024F) Receive Result Save Slot-3 Register */ + + struct + { + __IM uint8_t FMT : 1; /*!< [0..0] Packet Format */ + __IM uint8_t RXSUC : 1; /*!< [1..1] Receive Success */ + __IM uint8_t RXFERR : 1; /*!< [2..2] Fatal Error */ + __IM uint8_t RXFAIL : 1; /*!< [3..3] Receive Fail */ + __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail */ + __IM uint8_t RXCERR : 1; /*!< [5..5] Receive Correctable Error */ + __IM uint8_t RXAKE : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet */ + __IM uint8_t INFOOW : 1; /*!< [7..7] Information Overwrite */ + } RXRSS3R_HH_b; + }; + }; + }; + }; + }; + __IM uint32_t RESERVED8[28]; + + union + { + __IM uint32_t RXPPD0R; /*!< (@ 0x000002C0) Receive Packet Payload Data 0 Register */ + + struct + { + __IM uint32_t DATA0 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA1 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA2 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA3 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD0R_b; + }; + + union + { + __IM uint32_t RXPPD1R; /*!< (@ 0x000002C4) Receive Packet Payload Data 1 Register */ + + struct + { + __IM uint32_t DATA4 : 8; /*!< [7..0] Payload Data 0 */ + __IM uint32_t DATA5 : 8; /*!< [15..8] Payload Data 1 */ + __IM uint32_t DATA6 : 8; /*!< [23..16] Payload Data 2 */ + __IM uint32_t DATA7 : 8; /*!< [31..24] Payload Data 3 */ + } RXPPD1R_b; + }; + + union + { + __IM uint32_t RXPPD2R; /*!< (@ 0x000002C8) Receive Packet Payload Data 2 Register */ + + struct + { + __IM uint32_t DATA8 : 8; /*!< [7..0] Payload Data 8 */ + __IM uint32_t DATA9 : 8; /*!< [15..8] Payload Data 9 */ + __IM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10 */ + __IM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11 */ + } RXPPD2R_b; + }; + + union + { + __IM uint32_t RXPPD3R; /*!< (@ 0x000002CC) Receive Packet Payload Data 3 Register */ + + struct + { + __IM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12 */ + __IM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13 */ + __IM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14 */ + __IM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15 */ + } RXPPD3R_b; + }; + __IM uint32_t RESERVED9[4]; + + union + { + __IOM uint32_t HSTXTOSETR; /*!< (@ 0x000002E0) HS TX Timeout Set Register */ + + struct + { + __IOM uint32_t HTXTO : 32; /*!< [31..0] HS TX Timeout Count */ + } HSTXTOSETR_b; + }; + + union + { + __IOM uint32_t LRXHTOSETR; /*!< (@ 0x000002E4) LRX-H Timeout Set Register */ + + struct + { + __IOM uint32_t LRXHTO : 32; /*!< [31..0] LP-RX Host Processor Timeout */ + } LRXHTOSETR_b; + }; + + union + { + __IOM uint32_t TATOSETR; /*!< (@ 0x000002E8) TA Timeout Set Register */ + + struct + { + __IOM uint32_t TATO : 32; /*!< [31..0] Turnaround Acknowledge Timeout */ + } TATOSETR_b; + }; + __IM uint32_t RESERVED10[5]; + + union + { + __IM uint32_t FERRSR; /*!< (@ 0x00000300) Fatal Error Status Register */ + + struct + { + __IM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag */ + __IM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag */ + __IM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag */ + uint32_t : 13; + __IM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag */ + __IM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag */ + __IM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag */ + __IM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag */ + __IM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag */ + uint32_t : 6; + __IM uint32_t CLP0S : 1; /*!< [27..27] LP0 Contention Error Status */ + __IM uint32_t CLP1S : 1; /*!< [28..28] LP1 Contention Error Status */ + uint32_t : 3; + } FERRSR_b; + }; + + union + { + __IOM uint32_t FERRSCR; /*!< (@ 0x00000304) Fatal Error Status Clear Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Flag Clear */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag Clear */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag Clear */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Flag Clear */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag Clear */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag Clear */ + uint32_t : 11; + } FERRSCR_b; + }; + + union + { + __IOM uint32_t FERRIER; /*!< (@ 0x00000308) Fatal Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t HTXTO : 1; /*!< [0..0] HS TX Timeout Interrupt Enable */ + __IOM uint32_t LRXHTO : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable */ + __IOM uint32_t TATO : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable */ + uint32_t : 13; + __IOM uint32_t ESCENT : 1; /*!< [16..16] Escape mode Entry Error Interrupt Enable */ + __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Enable */ + __IOM uint32_t CTRL : 1; /*!< [18..18] Control Error Interrupt Enable */ + __IOM uint32_t CLP0 : 1; /*!< [19..19] LP0 Contention Error Interrupt Enable */ + __IOM uint32_t CLP1 : 1; /*!< [20..20] LP1 Contention Error Interrupt Enable */ + uint32_t : 11; + } FERRIER_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t CLSTPTSETR; /*!< (@ 0x00000314) Clock Lane Stop Time Set Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CLKSTPT : 10; /*!< [11..2] Clock Stop Time */ + uint32_t : 4; + __IOM uint32_t CLKBFHT : 8; /*!< [23..16] Clock Beforehand Time */ + __IOM uint32_t CLKKPT : 8; /*!< [31..24] Clock Keep Time */ + } CLSTPTSETR_b; + }; + + union + { + __IOM uint32_t LPTRNSTSETR; /*!< (@ 0x00000318) LP Transition Time Set Register */ + + struct + { + __IOM uint32_t GOLPBKT : 10; /*!< [9..0] Go LP and Back Time */ + uint32_t : 22; + } LPTRNSTSETR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IM uint32_t PLSR; /*!< (@ 0x00000320) Physical Lane Status Register */ + + struct + { + __IM uint32_t CLUAN : 1; /*!< [0..0] Clock Lane UlpsActiveNot Status */ + __IM uint32_t CLSTP : 1; /*!< [1..1] Clock Lane Stop Status */ + __IM uint32_t DL0RLE : 1; /*!< [2..2] Data Lane-0 RxLpdtEsc Status */ + __IM uint32_t DL0RUE : 1; /*!< [3..3] Data Lane-0 RxUlpsEsc Status */ + __IM uint32_t DL0UAN : 1; /*!< [4..4] Data Lane-0 UlpsActiveNot Status */ + __IM uint32_t DL1UAN : 1; /*!< [5..5] Data Lane-1 UlpsActiveNot Status */ + uint32_t : 2; + __IM uint32_t DL0STP : 1; /*!< [8..8] Data Lane-0 Stop Status */ + __IM uint32_t DL1STP : 1; /*!< [9..9] Data Lane-1 Stop Status */ + uint32_t : 2; + __IM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag */ + __IM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag */ + uint32_t : 1; + __IM uint32_t DL0DIR : 1; /*!< [15..15] Data Lane-0 Direction */ + uint32_t : 8; + __IM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag */ + __IM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag */ + __IM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag */ + __IM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag */ + __IM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag */ + __IM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag */ + uint32_t : 2; + } PLSR_b; + }; + + union + { + __IOM uint32_t PLSCR; /*!< (@ 0x00000324) Physical Lane Status Clear Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag Clear */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag Clear */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag Clear */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag Clear */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag Clear */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag Clear */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag Clear */ + uint32_t : 2; + } PLSCR_b; + }; + + union + { + __IOM uint32_t PLIER; /*!< (@ 0x00000328) Physical Lane Interrupt Enable Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Enable */ + __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Enable */ + __IOM uint32_t CLLP2HS : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Enable */ + __IOM uint32_t CLHS2LP : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Enable */ + __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Enable */ + __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Enable */ + uint32_t : 2; + } PLIER_b; + }; + __IM uint32_t RESERVED13[53]; + + union + { + __IOM uint32_t VMSET0R; /*!< (@ 0x00000400) Video Mode Set 0 Register */ + + struct + { + __OM uint32_t VSTART : 1; /*!< [0..0] Video Mode Operation Start */ + __OM uint32_t VSTOP : 1; /*!< [1..1] Video Mode Operation Stop */ + uint32_t : 6; + __IOM uint32_t HSANOLP : 1; /*!< [8..8] HSA period No LP */ + __IOM uint32_t HBPNOLP : 1; /*!< [9..9] HBP period No LP */ + __IOM uint32_t HFPNOLP : 1; /*!< [10..10] HFP period No LP */ + uint32_t : 21; + } VMSET0R_b; + }; + + union + { + __IOM uint32_t VMSET1R; /*!< (@ 0x00000404) Video Mode Set 1 Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t DLY : 12; /*!< [13..2] Delay Value */ + uint32_t : 18; + } VMSET1R_b; + }; + __IM uint32_t RESERVED14[2]; + + union + { + __IM uint32_t VMSR; /*!< (@ 0x00000410) Video Mode Status Register */ + + struct + { + __IM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag */ + __IM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag */ + __IM uint32_t RUNNING : 1; /*!< [2..2] Video Mode Operation Running Status */ + __IM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag */ + uint32_t : 16; + __IM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag */ + __IM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag */ + uint32_t : 8; + } VMSR_b; + }; + + union + { + __IOM uint32_t VMSCR; /*!< (@ 0x00000414) Video Mode Status Clear Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag Clear */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag Clear */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag Clear */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag Clear */ + uint32_t : 8; + } VMSCR_b; + }; + + union + { + __IOM uint32_t VMIER; /*!< (@ 0x00000418) Video Mode Interrupt Enable Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Video Mode Operation Start Interrupt Enable */ + __IOM uint32_t STOP : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VIRDY : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Enable */ + uint32_t : 16; + __IOM uint32_t TIMERR : 1; /*!< [20..20] Timing Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Enable */ + __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Enable */ + uint32_t : 8; + } VMIER_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t VMPPSETR; /*!< (@ 0x00000420) Video Mode Pixel Packet Set Register */ + + struct + { + uint32_t : 15; + __IOM uint32_t TXESYNC : 1; /*!< [15..15] Transmit End of Sync Pulse */ + __IOM uint32_t DT : 6; /*!< [21..16] Video Mode Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Video Mode Virtual Channel */ + uint32_t : 8; + } VMPPSETR_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t VMVSSETR; /*!< (@ 0x00000428) Video Mode Vertical Size Set Register */ + + struct + { + __IOM uint32_t VSA : 12; /*!< [11..0] VSA Lines */ + uint32_t : 3; + __IOM uint32_t VSPOL : 1; /*!< [15..15] VSYNC Polarity */ + __IOM uint32_t VACT : 15; /*!< [30..16] Vertical Active Lines */ + uint32_t : 1; + } VMVSSETR_b; + }; + + union + { + __IOM uint32_t VMVPSETR; /*!< (@ 0x0000042C) Video Mode Vertical Porch Set Register */ + + struct + { + __IOM uint32_t VBP : 13; /*!< [12..0] VBP Lines */ + uint32_t : 3; + __IOM uint32_t VFP : 13; /*!< [28..16] VFP Lines */ + uint32_t : 3; + } VMVPSETR_b; + }; + + union + { + __IOM uint32_t VMHSSETR; /*!< (@ 0x00000430) Video Mode Horizontal Size Set Register */ + + struct + { + __IOM uint32_t HSA : 12; /*!< [11..0] HSA Pixels */ + uint32_t : 3; + __IOM uint32_t HSPOL : 1; /*!< [15..15] HSYNC Polarity */ + __IOM uint32_t HACT : 15; /*!< [30..16] HACT Pixels */ + uint32_t : 1; + } VMHSSETR_b; + }; + + union + { + __IOM uint32_t VMHPSETR; /*!< (@ 0x00000434) Video Mode Horizontal Porch Set Register */ + + struct + { + __IOM uint32_t HBP : 13; /*!< [12..0] HBP Pixels */ + uint32_t : 3; + __IOM uint32_t HFP : 13; /*!< [28..16] HFP Pixels */ + uint32_t : 3; + } VMHPSETR_b; + }; + __IM uint32_t RESERVED17[98]; + + union + { + __IOM uint32_t SQCH0SET0R; /*!< (@ 0x000005C0) Sequence Channel 0 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH0SET0R_b; + }; + __IM uint32_t RESERVED18[3]; + + union + { + __IM uint32_t SQCH0SR; /*!< (@ 0x000005D0) Sequence Channel 0 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH0SR_b; + }; + + union + { + __IOM uint32_t SQCH0SCR; /*!< (@ 0x000005D4) Sequence Channel 0 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH0SCR_b; + }; + + union + { + __IOM uint32_t SQCH0IER; /*!< (@ 0x000005D8) Sequence Channel 0 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH0IER_b; + }; + __IM uint32_t RESERVED19[9]; + + union + { + __IOM uint32_t SQCH1SET0R; /*!< (@ 0x00000600) Sequence Channel 1 Set 0 Register */ + + struct + { + __OM uint32_t START : 1; /*!< [0..0] Sequence Operation Start */ + uint32_t : 31; + } SQCH1SET0R_b; + }; + __IM uint32_t RESERVED20[3]; + + union + { + __IM uint32_t SQCH1SR; /*!< (@ 0x00000610) Sequence Channel 1 Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t RUNNING : 1; /*!< [2..2] Sequence Operation Running Status */ + uint32_t : 1; + __IM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag */ + uint32_t : 3; + __IM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag */ + uint32_t : 7; + __IM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag */ + uint32_t : 2; + __IM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag */ + uint32_t : 4; + __IM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag */ + uint32_t : 1; + __IM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag */ + __IM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag */ + __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag */ + __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag */ + __IM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag */ + uint32_t : 1; + } SQCH1SR_b; + }; + + union + { + __IOM uint32_t SQCH1SCR; /*!< (@ 0x00000614) Sequence Channel 1 Status Clear Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Flag Clear */ + uint32_t : 1; + } SQCH1SCR_b; + }; + + union + { + __IOM uint32_t SQCH1IER; /*!< (@ 0x00000618) Sequence Channel 1 Interrupt Enable Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t AACTFIN : 1; /*!< [4..4] All Actions Finish Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t ADESFIN : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t DABORT : 1; /*!< [16..16] Descriptor Abort Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SIZEERR : 1; /*!< [19..19] Packet Size Error Interrupt Enable */ + uint32_t : 4; + __IOM uint32_t TXIBERR : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t RXFERR : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable */ + __IOM uint32_t RXFAIL : 1; /*!< [27..27] Receive Fail Interrupt Enable */ + __IOM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable */ + __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable */ + __IOM uint32_t RXAKE : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt + * Enable */ + uint32_t : 1; + } SQCH1IER_b; + }; + __IM uint32_t RESERVED21[89]; + + union + { + union + { + __IOM uint32_t SQCH0DSC0AR; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_L; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_LL; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_LH; /*!< (@ 0x00000781) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0AR_H; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0AR_HL; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0AR_HH; /*!< (@ 0x00000783) Sequence Channel 0 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC0BR; /*!< (@ 0x00000784) Sequence Channel 0 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0CR; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_L; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_LL; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0CR_H; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0CR_HL; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0CR_HH; /*!< (@ 0x0000078B) Sequence Channel 0 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC0DR; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_L; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_LL; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_LH; /*!< (@ 0x0000078D) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC0DR_H; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC0DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC0DR_HL; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC0DR_HH; /*!< (@ 0x0000078F) Sequence Channel 0 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC0DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1AR; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_L; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_LL; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_LH; /*!< (@ 0x00000791) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1AR_H; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1AR_HL; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1AR_HH; /*!< (@ 0x00000793) Sequence Channel 0 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC1BR; /*!< (@ 0x00000794) Sequence Channel 0 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1CR; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_L; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_LL; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1CR_H; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1CR_HL; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1CR_HH; /*!< (@ 0x0000079B) Sequence Channel 0 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC1DR; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_L; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_LL; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_LH; /*!< (@ 0x0000079D) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC1DR_H; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC1DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC1DR_HL; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC1DR_HH; /*!< (@ 0x0000079F) Sequence Channel 0 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC1DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2AR; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_L; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_LL; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_LH; /*!< (@ 0x000007A1) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2AR_H; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2AR_HL; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2AR_HH; /*!< (@ 0x000007A3) Sequence Channel 0 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC2BR; /*!< (@ 0x000007A4) Sequence Channel 0 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2CR; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_L; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_LL; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2CR_H; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2CR_HL; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2CR_HH; /*!< (@ 0x000007AB) Sequence Channel 0 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC2DR; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_L; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_LL; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_LH; /*!< (@ 0x000007AD) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC2DR_H; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC2DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC2DR_HL; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC2DR_HH; /*!< (@ 0x000007AF) Sequence Channel 0 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC2DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3AR; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_L; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_LL; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_LH; /*!< (@ 0x000007B1) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3AR_H; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3AR_HL; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3AR_HH; /*!< (@ 0x000007B3) Sequence Channel 0 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC3BR; /*!< (@ 0x000007B4) Sequence Channel 0 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3CR; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_L; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_LL; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3CR_H; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3CR_HL; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3CR_HH; /*!< (@ 0x000007BB) Sequence Channel 0 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC3DR; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_L; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_LL; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_LH; /*!< (@ 0x000007BD) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC3DR_H; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC3DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC3DR_HL; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC3DR_HH; /*!< (@ 0x000007BF) Sequence Channel 0 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC3DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4AR; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_L; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_LL; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_LH; /*!< (@ 0x000007C1) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4AR_H; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4AR_HL; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4AR_HH; /*!< (@ 0x000007C3) Sequence Channel 0 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC4BR; /*!< (@ 0x000007C4) Sequence Channel 0 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4CR; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_L; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_LL; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4CR_H; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4CR_HL; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4CR_HH; /*!< (@ 0x000007CB) Sequence Channel 0 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC4DR; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_L; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_LL; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_LH; /*!< (@ 0x000007CD) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC4DR_H; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC4DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC4DR_HL; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC4DR_HH; /*!< (@ 0x000007CF) Sequence Channel 0 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC4DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5AR; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_L; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_LL; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_LH; /*!< (@ 0x000007D1) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5AR_H; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5AR_HL; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5AR_HH; /*!< (@ 0x000007D3) Sequence Channel 0 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC5BR; /*!< (@ 0x000007D4) Sequence Channel 0 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5CR; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_L; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_LL; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5CR_H; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5CR_HL; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5CR_HH; /*!< (@ 0x000007DB) Sequence Channel 0 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC5DR; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_L; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_LL; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_LH; /*!< (@ 0x000007DD) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC5DR_H; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC5DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC5DR_HL; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC5DR_HH; /*!< (@ 0x000007DF) Sequence Channel 0 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC5DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6AR; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_L; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_LL; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_LH; /*!< (@ 0x000007E1) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6AR_H; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6AR_HL; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6AR_HH; /*!< (@ 0x000007E3) Sequence Channel 0 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC6BR; /*!< (@ 0x000007E4) Sequence Channel 0 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6CR; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_L; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_LL; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6CR_H; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6CR_HL; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6CR_HH; /*!< (@ 0x000007EB) Sequence Channel 0 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC6DR; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_L; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_LL; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_LH; /*!< (@ 0x000007ED) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC6DR_H; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC6DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC6DR_HL; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC6DR_HH; /*!< (@ 0x000007EF) Sequence Channel 0 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC6DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7AR; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH0DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_L; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH0DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_LL; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH0DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_LH; /*!< (@ 0x000007F1) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH0DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7AR_H; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH0DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7AR_HL; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH0DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7AR_HH; /*!< (@ 0x000007F3) Sequence Channel 0 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH0DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH0DSC7BR; /*!< (@ 0x000007F4) Sequence Channel 0 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH0DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7CR; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH0DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_L; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH0DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_LL; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH0DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7CR_H; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH0DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7CR_HL; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH0DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7CR_HH; /*!< (@ 0x000007FB) Sequence Channel 0 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH0DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH0DSC7DR; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH0DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_L; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_LL; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_LH; /*!< (@ 0x000007FD) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH0DSC7DR_H; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH0DSC7DR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH0DSC7DR_HL; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH0DSC7DR_HH; /*!< (@ 0x000007FF) Sequence Channel 0 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH0DSC7DR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0AR; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC0AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_L; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC0AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_LL; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC0AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_LH; /*!< (@ 0x00000801) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC0AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0AR_H; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC0AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0AR_HL; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC0AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0AR_HH; /*!< (@ 0x00000803) Sequence Channel 1 Descriptor-0 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC0AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC0BR; /*!< (@ 0x00000804) Sequence Channel 1 Descriptor-0 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC0BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0CR; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC0CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_L; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC0CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_LL; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC0CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC0CR_H; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC0CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0CR_HL; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC0CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0CR_HH; /*!< (@ 0x0000080B) Sequence Channel 1 Descriptor-0 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC0CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC0DR; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC0DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC0DR_L; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC0DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC0DR_LL; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_LH; /*!< (@ 0x0000080D) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HL; /*!< (@ 0x0000080E) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC0DR_HH; /*!< (@ 0x0000080F) Sequence Channel 1 Descriptor-0 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC0DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1AR; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC1AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_L; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC1AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_LL; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC1AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_LH; /*!< (@ 0x00000811) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC1AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1AR_H; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC1AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1AR_HL; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC1AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1AR_HH; /*!< (@ 0x00000813) Sequence Channel 1 Descriptor-1 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC1AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC1BR; /*!< (@ 0x00000814) Sequence Channel 1 Descriptor-1 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC1BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1CR; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC1CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_L; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC1CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_LL; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC1CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC1CR_H; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC1CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1CR_HL; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC1CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1CR_HH; /*!< (@ 0x0000081B) Sequence Channel 1 Descriptor-1 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC1CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC1DR; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC1DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC1DR_L; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC1DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC1DR_LL; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_LH; /*!< (@ 0x0000081D) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HL; /*!< (@ 0x0000081E) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC1DR_HH; /*!< (@ 0x0000081F) Sequence Channel 1 Descriptor-1 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC1DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2AR; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC2AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_L; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC2AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_LL; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC2AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_LH; /*!< (@ 0x00000821) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC2AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2AR_H; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC2AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2AR_HL; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC2AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2AR_HH; /*!< (@ 0x00000823) Sequence Channel 1 Descriptor-2 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC2AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC2BR; /*!< (@ 0x00000824) Sequence Channel 1 Descriptor-2 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC2BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2CR; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC2CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_L; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC2CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_LL; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC2CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC2CR_H; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC2CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2CR_HL; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC2CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2CR_HH; /*!< (@ 0x0000082B) Sequence Channel 1 Descriptor-2 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC2CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC2DR; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC2DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC2DR_L; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC2DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC2DR_LL; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_LH; /*!< (@ 0x0000082D) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HL; /*!< (@ 0x0000082E) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC2DR_HH; /*!< (@ 0x0000082F) Sequence Channel 1 Descriptor-2 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC2DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3AR; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC3AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_L; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC3AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_LL; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC3AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_LH; /*!< (@ 0x00000831) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC3AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3AR_H; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC3AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3AR_HL; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC3AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3AR_HH; /*!< (@ 0x00000833) Sequence Channel 1 Descriptor-3 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC3AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC3BR; /*!< (@ 0x00000834) Sequence Channel 1 Descriptor-3 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC3BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3CR; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC3CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_L; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC3CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_LL; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC3CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC3CR_H; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC3CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3CR_HL; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC3CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3CR_HH; /*!< (@ 0x0000083B) Sequence Channel 1 Descriptor-3 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC3CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC3DR; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC3DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC3DR_L; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC3DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC3DR_LL; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_LH; /*!< (@ 0x0000083D) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HL; /*!< (@ 0x0000083E) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC3DR_HH; /*!< (@ 0x0000083F) Sequence Channel 1 Descriptor-3 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC3DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4AR; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC4AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_L; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC4AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_LL; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC4AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_LH; /*!< (@ 0x00000841) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC4AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4AR_H; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC4AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4AR_HL; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC4AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4AR_HH; /*!< (@ 0x00000843) Sequence Channel 1 Descriptor-4 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC4AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC4BR; /*!< (@ 0x00000844) Sequence Channel 1 Descriptor-4 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC4BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4CR; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC4CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_L; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC4CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_LL; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC4CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC4CR_H; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC4CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4CR_HL; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC4CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4CR_HH; /*!< (@ 0x0000084B) Sequence Channel 1 Descriptor-4 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC4CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC4DR; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC4DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC4DR_L; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC4DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC4DR_LL; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_LH; /*!< (@ 0x0000084D) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HL; /*!< (@ 0x0000084E) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC4DR_HH; /*!< (@ 0x0000084F) Sequence Channel 1 Descriptor-4 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC4DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5AR; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC5AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_L; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC5AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_LL; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC5AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_LH; /*!< (@ 0x00000851) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC5AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5AR_H; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC5AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5AR_HL; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC5AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5AR_HH; /*!< (@ 0x00000853) Sequence Channel 1 Descriptor-5 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC5AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC5BR; /*!< (@ 0x00000854) Sequence Channel 1 Descriptor-5 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC5BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5CR; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC5CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_L; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC5CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_LL; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC5CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC5CR_H; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC5CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5CR_HL; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC5CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5CR_HH; /*!< (@ 0x0000085B) Sequence Channel 1 Descriptor-5 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC5CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC5DR; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC5DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC5DR_L; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC5DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC5DR_LL; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_LH; /*!< (@ 0x0000085D) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HL; /*!< (@ 0x0000085E) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC5DR_HH; /*!< (@ 0x0000085F) Sequence Channel 1 Descriptor-5 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC5DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6AR; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC6AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_L; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC6AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_LL; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC6AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_LH; /*!< (@ 0x00000861) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC6AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6AR_H; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC6AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6AR_HL; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC6AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6AR_HH; /*!< (@ 0x00000863) Sequence Channel 1 Descriptor-6 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC6AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC6BR; /*!< (@ 0x00000864) Sequence Channel 1 Descriptor-6 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC6BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6CR; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC6CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_L; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC6CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_LL; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC6CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC6CR_H; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC6CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6CR_HL; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC6CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6CR_HH; /*!< (@ 0x0000086B) Sequence Channel 1 Descriptor-6 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC6CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC6DR; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC6DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC6DR_L; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC6DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC6DR_LL; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_LH; /*!< (@ 0x0000086D) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HL; /*!< (@ 0x0000086E) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC6DR_HH; /*!< (@ 0x0000086F) Sequence Channel 1 Descriptor-6 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC6DR_HH_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7AR; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1 */ + __IOM uint32_t DT : 6; /*!< [21..16] Data Type */ + __IOM uint32_t VC : 2; /*!< [23..22] Virtual Channel */ + __IOM uint32_t FMT : 1; /*!< [24..24] Format */ + __IOM uint32_t SPD : 1; /*!< [25..25] Speed */ + __IOM uint32_t BTA : 2; /*!< [27..26] Bus Turn Around */ + __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action */ + uint32_t : 2; + } SQCH1DSC7AR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_L; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0 */ + __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1 */ + } SQCH1DSC7AR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_LL; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA0 : 8; /*!< [7..0] Data 0 */ + } SQCH1DSC7AR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_LH; /*!< (@ 0x00000871) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DATA1 : 8; /*!< [7..0] Data 1 */ + } SQCH1DSC7AR_LH_b; + }; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7AR_H; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint16_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint16_t VC : 2; /*!< [7..6] Virtual Channel */ + __IOM uint16_t FMT : 1; /*!< [8..8] Format */ + __IOM uint16_t SPD : 1; /*!< [9..9] Speed */ + __IOM uint16_t BTA : 2; /*!< [11..10] Bus Turn Around */ + __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action */ + uint16_t : 2; + } SQCH1DSC7AR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7AR_HL; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t DT : 6; /*!< [5..0] Data Type */ + __IOM uint8_t VC : 2; /*!< [7..6] Virtual Channel */ + } SQCH1DSC7AR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7AR_HH; /*!< (@ 0x00000873) Sequence Channel 1 Descriptor-7 A Register */ + + struct + { + __IOM uint8_t FMT : 1; /*!< [0..0] Format */ + __IOM uint8_t SPD : 1; /*!< [1..1] Speed */ + __IOM uint8_t BTA : 2; /*!< [3..2] Bus Turn Around */ + __IOM uint8_t NXACT : 2; /*!< [5..4] Next Action */ + uint8_t : 2; + } SQCH1DSC7AR_HH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint32_t SQCH1DSC7BR; /*!< (@ 0x00000874) Sequence Channel 1 Descriptor-7 B Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t DTSEL : 2; /*!< [25..24] Data Select */ + uint32_t : 6; + } SQCH1DSC7BR_b; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7CR; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint32_t FINACT : 1; /*!< [0..0] Finish Action */ + uint32_t : 21; + __IOM uint32_t AUXOP : 1; /*!< [22..22] Auxiliary Operation */ + uint32_t : 1; + __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code */ + } SQCH1DSC7CR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_L; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action */ + uint16_t : 15; + } SQCH1DSC7CR_L_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_LL; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action */ + uint8_t : 7; + } SQCH1DSC7CR_LL_b; + }; + }; + + union + { + union + { + __IOM uint16_t SQCH1DSC7CR_H; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint16_t : 1; + __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code */ + } SQCH1DSC7CR_H_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7CR_HL; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation */ + uint8_t : 1; + } SQCH1DSC7CR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7CR_HH; /*!< (@ 0x0000087B) Sequence Channel 1 Descriptor-7 C Register */ + + struct + { + __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code */ + } SQCH1DSC7CR_HH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t SQCH1DSC7DR; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address */ + } SQCH1DSC7DR_b; + }; + + struct + { + union + { + union + { + __IOM uint16_t SQCH1DSC7DR_L; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address */ + } SQCH1DSC7DR_L_b; + }; + + struct + { + union + { + __IOM uint8_t SQCH1DSC7DR_LL; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_LH; /*!< (@ 0x0000087D) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_LH_b; + }; + }; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HL; /*!< (@ 0x0000087E) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HL_b; + }; + + union + { + __IOM uint8_t SQCH1DSC7DR_HH; /*!< (@ 0x0000087F) Sequence Channel 1 Descriptor-7 D Register */ + + struct + { + __IOM uint8_t LADDR : 8; /*!< [7..0] Lower Address */ + } SQCH1DSC7DR_HH_b; + }; + }; + }; +} R_MIPI_DSI_Type; /*!< Size = 2176 (0x880) */ + +/* =========================================================================================================================== */ +/* ================ R_MRMS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief MRAM Control (R_MRMS) + */ + +typedef struct /*!< (@ 0x4013C000) R_MRMS Structure */ +{ + union + { + __IOM uint8_t MRCPFB; /*!< (@ 0x00000000) Code MRAM Pre-Fetch Buffer Enable Register */ + + struct + { + __IOM uint8_t MPFBEN : 1; /*!< [0..0] MRAM Pre-Fetch Buffer enable. */ + uint8_t : 7; + } MRCPFB_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t MRCFREQ; /*!< (@ 0x00000004) Code MRAM Frequency Notifications Register */ + + struct + { + __IOM uint32_t MRCMHZ : 10; /*!< [9..0] Setting the operating frequency in the order of MHz */ + uint32_t : 14; + __IOM uint32_t KEY : 8; /*!< [31..24] Key Code */ + } MRCFREQ_b; + }; + + union + { + __IOM uint32_t MREFREQ; /*!< (@ 0x00000008) Extra MRAM Frequency Notifications Register */ + + struct + { + __IOM uint32_t MREMHZ : 8; /*!< [7..0] Setting the operating frequency in the order of MHz */ + uint32_t : 16; + __IOM uint32_t KEY : 8; /*!< [31..24] Key Code */ + } MREFREQ_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint16_t MRCDECC; /*!< (@ 0x00000010) Code MRAM ECC Decoder Control Register */ + + struct + { + __IOM uint16_t DECDISC : 1; /*!< [0..0] MRC ECC Decoder disable */ + __IOM uint16_t ECCSELC : 1; /*!< [1..1] MRC ECC Data select */ + uint16_t : 6; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCDECC_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t MRCRAEINT; /*!< (@ 0x00000014) Code MRAM Read Access Error Interrupt Enable + * Register */ + + struct + { + __IOM uint8_t INTENBDC : 1; /*!< [0..0] MRC DEC error interrupt enable. */ + __IOM uint8_t INTENBTC : 1; /*!< [1..1] MRC TED error interrupt enable. */ + uint8_t : 6; + } MRCRAEINT_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t MRCRAES; /*!< (@ 0x00000018) Code MRAM Read Access Error Status Register */ + + struct + { + __IOM uint8_t DECERRC : 1; /*!< [0..0] MRC DEC error detected. */ + __IOM uint8_t TEDERRC : 1; /*!< [1..1] MRC TED error detected. */ + uint8_t : 6; + } MRCRAES_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IM uint32_t MRCRTEA; /*!< (@ 0x0000001C) Code MRAM TED Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MRCRTEA : 27; /*!< [31..5] MRC read access TED error Address. */ + } MRCRTEA_b; + }; + + union + { + __IM uint32_t MRCRDEA; /*!< (@ 0x00000020) Code MRAM DEC Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MRCRDEA : 27; /*!< [31..5] MRC read access DEC error Address. */ + } MRCRDEA_b; + }; + __IM uint32_t RESERVED8[4]; + + union + { + __IOM uint8_t MRERAINT; /*!< (@ 0x00000034) Extra MRAM Read Access Error Interrupt Enable + * Register */ + + struct + { + __IOM uint8_t INTENBDE : 1; /*!< [0..0] MRE DEC error interrupt enable. */ + __IOM uint8_t INTENBTE : 1; /*!< [1..1] MRE TED error interrupt enable. */ + uint8_t : 6; + } MRERAINT_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t MRERAES; /*!< (@ 0x00000038) Extra MRAM Read Access Error Status Register */ + + struct + { + __IOM uint8_t DECERRE : 1; /*!< [0..0] MRE DEC error detected. */ + __IOM uint8_t TEDERRE : 1; /*!< [1..1] MRE TED error detected. */ + uint8_t : 6; + } MRERAES_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t MRERTEA; /*!< (@ 0x0000003C) Extra MRAM TED Error Address Register */ + + struct + { + uint32_t : 4; + __IM uint32_t MRERTEA : 28; /*!< [31..4] MRE read access TED error Address. */ + } MRERTEA_b; + }; + + union + { + __IM uint32_t MRERDEA; /*!< (@ 0x00000040) Extra MRAM DEC Error Address Register */ + + struct + { + uint32_t : 4; + __IM uint32_t MRERDEA : 28; /*!< [31..4] MRE read access DEC error Address. */ + } MRERDEA_b; + }; + __IM uint32_t RESERVED13[47]; + + union + { + __IOM uint16_t MSAR; /*!< (@ 0x00000100) MRAM Security Attribution Register */ + + struct + { + __IOM uint16_t MREECCSA : 1; /*!< [0..0] Extra MRAM ECC Register Security Attribution */ + __IOM uint16_t MREFREQSA : 1; /*!< [1..1] MREFREQ register Security Attribution */ + __IOM uint16_t MRCECCSA : 1; /*!< [2..2] Code MRAM ECC Register Security Attribution */ + __IOM uint16_t MRCFREQSA : 1; /*!< [3..3] MRCFREQ register Security Attribution */ + __IOM uint16_t MPFBENSA : 1; /*!< [4..4] MRCPFB register Security Attribution */ + uint16_t : 4; + __IOM uint16_t MACICMISA : 1; /*!< [9..9] MACI Command Issuing Security Attribution */ + __IOM uint16_t MACICMRSA : 1; /*!< [10..10] MACI Command Registers Security Attribution */ + __IOM uint16_t MACITRSA : 1; /*!< [11..11] MACI Transfer Security Attribution */ + uint16_t : 1; + __IOM uint16_t MRCPSA : 1; /*!< [13..13] Code MRAM Program Register Security Attribution */ + __IOM uint16_t MREPSEQSA : 1; /*!< [14..14] EPSEQ Area Register Security Attribution */ + __IOM uint16_t MRCPSEQSA : 1; /*!< [15..15] CPSEQ Area Register Security Attribution */ + } MSAR_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[191]; + + union + { + __IM uint8_t MREZS; /*!< (@ 0x00000400) Extra MRAM Zeroization Status Register */ + + struct + { + __IM uint8_t WHUKZF : 1; /*!< [0..0] W-HUK Zero Flag Status. */ + __IM uint8_t WHUKEXE : 1; /*!< [1..1] W-HUK Zeroization Executing Status */ + uint8_t : 6; + } MREZS_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t MREZC; /*!< (@ 0x00000404) Extra MRAM Zeroization Control Register */ + + struct + { + __IOM uint16_t WHUKZE : 3; /*!< [2..0] W-KUK zeroization execute. */ + uint16_t : 5; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MREZC_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19[1794]; + + union + { + __IOM uint8_t MASTAT; /*!< (@ 0x00002010) Extra MRAM Access Status Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MREAE : 1; /*!< [3..3] Extra MRAM Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 3; + } MASTAT_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t MPAEINT; /*!< (@ 0x00002014) Extra MRAM Access Error Interrupt Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MREAEIE : 1; /*!< [3..3] MRE Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 3; + } MPAEINT_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t MRDYIE; /*!< (@ 0x00002018) Extra MRAM Ready Interrupt Enable Register */ + + struct + { + __IOM uint8_t MRDYIE : 1; /*!< [0..0] MRDY Interrupt Enable */ + uint8_t : 7; + } MRDYIE_b; + }; + __IM uint8_t RESERVED24; + __IM uint16_t RESERVED25; + __IM uint32_t RESERVED26[5]; + + union + { + __IOM uint32_t MSADDR; /*!< (@ 0x00002030) MACI Command Start Address Register */ + + struct + { + __IOM uint32_t MSADDR : 32; /*!< [31..0] Start Address for MACI Command Processing */ + } MSADDR_b; + }; + __IM uint32_t RESERVED27[5]; + + union + { + __IOM uint8_t MCNTSELR; /*!< (@ 0x00002048) MRAM Counter Select Register */ + + struct + { + __IOM uint8_t CNTSEL : 3; /*!< [2..0] Counter Select */ + uint8_t : 5; + } MCNTSELR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + + union + { + __IM uint32_t MCNTDTR0; /*!< (@ 0x0000204C) MRAM Counter Data Register 0 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } MCNTDTR0_b; + }; + + union + { + __IM uint32_t MCNTDTR1; /*!< (@ 0x00002050) MRAM Counter Data Register 1 */ + + struct + { + __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data */ + } MCNTDTR1_b; + }; + __IM uint32_t RESERVED30[3]; + + union + { + __IOM uint16_t MCTRCNTR; /*!< (@ 0x00002060) MRAM Configuration Update Transfer Control Register */ + + struct + { + __IOM uint16_t TRTRG : 1; /*!< [0..0] Transfer Start Trigger */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MCTRCNTR_b; + }; + __IM uint16_t RESERVED31; + + union + { + __IOM uint8_t MCTRLSR; /*!< (@ 0x00002064) MRAM Configuration Update Transfer List Select + * Register */ + + struct + { + __IOM uint8_t TRLIST : 3; /*!< [2..0] Configuration Update Transfer List */ + uint8_t : 5; + } MCTRLSR_b; + }; + __IM uint8_t RESERVED32; + __IM uint16_t RESERVED33; + __IM uint32_t RESERVED34; + + union + { + __IM uint8_t MCTRSTATR; /*!< (@ 0x0000206C) MRAM Configuration Update Transfer Status Register */ + + struct + { + __IM uint8_t TRBUSY : 1; /*!< [0..0] Transfer Busy Status */ + uint8_t : 1; + __IM uint8_t TRMD : 1; /*!< [2..2] Transfer Mode Setting Status */ + uint8_t : 5; + } MCTRSTATR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[4]; + + union + { + __IM uint32_t MSTATR; /*!< (@ 0x00002080) Extra MRAM Status Register */ + + struct + { + uint32_t : 5; + __IM uint32_t CFGSETERR : 1; /*!< [5..5] Configuration Set Error Flag */ + uint32_t : 6; + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + uint32_t : 1; + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Error */ + __IM uint32_t MRDY : 1; /*!< [15..15] MRE Ready */ + uint32_t : 3; + __IM uint32_t TZFERR : 1; /*!< [19..19] TrustZone Filter Error */ + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + uint32_t : 1; + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } MSTATR_b; + }; + + union + { + __IOM uint16_t MENTRYR; /*!< (@ 0x00002084) Extra MRAM Program Mode Entry Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t MENTRY : 1; /*!< [7..7] Extra MRAM Mode Entry */ + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MENTRYR_b; + }; + __IM uint16_t RESERVED38; + __IM uint32_t RESERVED39; + + union + { + __IOM uint16_t MSUINITR; /*!< (@ 0x0000208C) Extra MRAM Sequencer Set-Up Initialization Register */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MSUINITR_b; + }; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41[4]; + + union + { + __IM uint16_t MCMDR; /*!< (@ 0x000020A0) MACI Command Register */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Pre-command Flag */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Flag */ + } MCMDR_b; + }; + __IM uint16_t RESERVED42; + __IM uint32_t RESERVED43[14]; + + union + { + __IM uint32_t MSUASMON; /*!< (@ 0x000020DC) MRAM Start-Up Area Select Monitor Register */ + + struct + { + uint32_t : 15; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programing to set the Start-Up Area + * Select setting */ + uint32_t : 13; + __IM uint32_t BTSIZE : 2; /*!< [30..29] Size of Start-Up area select for Boot Swap */ + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } MSUASMON_b; + }; + __IM uint32_t RESERVED44[2]; + + union + { + __IOM uint16_t MSUACR; /*!< (@ 0x000020E8) MRAM Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select */ + uint16_t : 6; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MSUACR_b; + }; + __IM uint16_t RESERVED45; + __IM uint32_t RESERVED46[453]; + + union + { + __IOM uint8_t MRPSC; /*!< (@ 0x00002800) MRAM Program Speed Control Register */ + + struct + { + __IOM uint8_t MHSPEN : 1; /*!< [0..0] MRAM high speed program mode enable. */ + uint8_t : 7; + } MRPSC_b; + }; + __IM uint8_t RESERVED47; + __IM uint16_t RESERVED48; + __IM uint32_t RESERVED49[511]; + + union + { + __IOM uint16_t MRCPC0; /*!< (@ 0x00003000) Code MRAM Program Control Register */ + + struct + { + __IOM uint16_t MRCPNEN : 1; /*!< [0..0] Code MRAM Program Enable for Non-secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCPC0_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint16_t MRCPC1; /*!< (@ 0x00003004) Code MRAM Program Control for Secure Register */ + + struct + { + __IOM uint16_t MRCPSEN : 1; /*!< [0..0] Code MRAM Program Enable for Secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCPC1_b; + }; + __IM uint16_t RESERVED51; + + union + { + __IOM uint16_t MRCBPROT0; /*!< (@ 0x00003008) Code MRAM Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Code MRAM Block Protection Cancel for Non-secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCBPROT0_b; + }; + __IM uint16_t RESERVED52; + + union + { + __IOM uint16_t MRCBPROT1; /*!< (@ 0x0000300C) Code MRAM Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Code MRAM Block Protection Cancel for Secure */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCBPROT1_b; + }; + __IM uint16_t RESERVED53; + + union + { + __IOM uint8_t MRCPS; /*!< (@ 0x00003010) Code MRAM Program Status Register */ + + struct + { + __IOM uint8_t PRGERRC : 1; /*!< [0..0] Programming Error */ + __IOM uint8_t ECCERRC : 1; /*!< [1..1] ECC Error */ + uint8_t : 3; + __IM uint8_t ABUFEMP : 1; /*!< [5..5] Address Buffer Empty */ + __IM uint8_t ABUFFULL : 1; /*!< [6..6] Address Buffer Full */ + __IM uint8_t PRGBSYC : 1; /*!< [7..7] Code MRAM Program Busy */ + } MRCPS_b; + }; + __IM uint8_t RESERVED54; + __IM uint16_t RESERVED55; + + union + { + __IOM uint8_t MRCPAEINT; /*!< (@ 0x00003014) Code MRAM Program Access Error Interrupt Enable + * Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t MRCAEIE : 1; /*!< [7..7] Code MRAM Program Access Error Interrupt Enable */ + } MRCPAEINT_b; + }; + __IM uint8_t RESERVED56; + __IM uint16_t RESERVED57; + + union + { + __IM uint32_t MRCPEA; /*!< (@ 0x00003018) Code MRAM Program Error Address Register */ + + struct + { + uint32_t : 5; + __IM uint32_t MCPEA : 27; /*!< [31..5] Code MRAM Program Error Address */ + } MRCPEA_b; + }; + __IM uint32_t RESERVED58[5]; + + union + { + __IOM uint16_t MRCFLR; /*!< (@ 0x00003030) Code MRAM Flush Register */ + + struct + { + __IOM uint16_t MRCFL : 1; /*!< [0..0] Flush Write Data Buffer for code MRAM */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCFLR_b; + }; + __IM uint16_t RESERVED59; + __IM uint32_t RESERVED60[500]; + + union + { + __IOM uint16_t MRCEECC; /*!< (@ 0x00003804) Code MRAM ECC Encoder Control Register */ + + struct + { + __IOM uint16_t ECCBYPC : 1; /*!< [0..0] Code MRAM ECC encoder outputs bypass enable */ + uint16_t : 7; + __IOM uint16_t KEY : 8; /*!< [15..8] Key Code */ + } MRCEECC_b; + }; + __IM uint16_t RESERVED61; +} R_MRMS_Type; /*!< Size = 14344 (0x3808) */ + +/* =========================================================================================================================== */ +/* ================ R_NPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Neural Processing Unit (R_NPU) + */ + +typedef struct /*!< (@ 0x40140000) R_NPU Structure */ +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) ID register */ + + struct + { + __IM uint32_t version_status : 4; /*!< [3..0] This is the version of the product */ + __IM uint32_t version_minor : 4; /*!< [7..4] This is the n for the P-part of an RnPn release number */ + __IM uint32_t version_major : 4; /*!< [11..8] This is the n for the R-part of an RnPn release number */ + __IM uint32_t product_major : 4; /*!< [15..12] This is the X-part of the ML00X product number */ + __IM uint32_t arch_patch_rev : 4; /*!< [19..16] This is the patch number of the architecture version + * a.b */ + __IM uint32_t arch_minor_rev : 8; /*!< [27..20] This is the minor architecture version number, b in + * the architecture version a.b */ + __IM uint32_t arch_major_rev : 4; /*!< [31..28] This is the major architecture version number, a in + * the architecture version a.b */ + } ID_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000004) Register describes the current operating status + * of the NPU */ + + struct + { + __IM uint32_t state : 1; /*!< [0..0] NPU state; 0 = Stopped, 1 = Running */ + __IM uint32_t irq_raised : 1; /*!< [1..1] Raw IRQ status: 0 = IRQ not raised, 1 = IRQ raised. IRQ + * is cleared using command register bit 1. */ + __IM uint32_t bus_status : 1; /*!< [2..2] 0=OK, 1=Bus abort detected and processing halted (the + * NPU has reached IDLE state and does not start to process + * any more commands/AXI transactions). Can only be cleared + * by a reset. */ + __IM uint32_t reset_status : 1; /*!< [3..3] Reset is ongoing and only this register can be read (other + * registers read as 0 and writes are ignored). A value of + * 0 means the NPU is not being reset and can be accessed + * as normal. */ + __IM uint32_t cmd_parse_error : 1; /*!< [4..4] 0=No error, 1=Command-stream parsing error detected. + * Can only be cleared by a reset. */ + __IM uint32_t cmd_end_reached : 1; /*!< [5..5] 0=Not reached, 1=Reached. Cleared by writing QBASE or + * QSIZE when the NPU is in stopped state. */ + __IM uint32_t pmu_irq_raised : 1; /*!< [6..6] 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command + * register bit 1 */ + uint32_t : 1; + __IM uint32_t ecc_fault : 1; /*!< [8..8] ECC state for internal RAMs: 0=no fault, 1=ECC fault + * signalled. Can only be cleared by reset. */ + uint32_t : 2; + __IM uint32_t faulting_interface : 1; /*!< [11..11] Faulting interface on bus abort. 0=AXI-M0, 1=AXI-M1 */ + __IM uint32_t faulting_channel : 4; /*!< [15..12] Faulting channel on a bus abort. Read: 0=Cmd, 1=IFM, + * 2=Weights, 3=Scale+Bias, 4=Mem2Mem; Write: 8=OFM, 9=Mem2Mem */ + __IM uint32_t irq_history_mask : 16; /*!< [31..16] IRQ History mask */ + } STATUS_b; + }; + + union + { + __IOM uint32_t CMD; /*!< (@ 0x00000008) Command register, reads as last written command */ + + struct + { + __IOM uint32_t transition_to_running_state : 1; /*!< [0..0] Write 1 to transition the NPU to running state. Writing + * 0 has no effect */ + __IOM uint32_t clear_irq : 1; /*!< [1..1] Write 1 to clear the IRQ status in the STATUS register. + * Writing 0 has no effect */ + __IOM uint32_t clock_q_enable : 1; /*!< [2..2] Write 1 to this bit to enable clock off using the Clock + * Q-interface and enable the main clock gate */ + __IOM uint32_t power_q_enable : 1; /*!< [3..3] Write 1 to this bit to enable power off using the Power + * Q-interface */ + uint32_t : 12; + __IOM uint32_t clear_irq_history : 16; /*!< [31..16] Clears the IRQ history mask */ + } CMD_b; + }; + + union + { + __IOM uint32_t RESET; /*!< (@ 0x0000000C) Request Reset and new security mode */ + + struct + { + __IOM uint32_t pending_CPL : 1; /*!< [0..0] Current privilege level: 0=User, 1=Privileged */ + __IOM uint32_t pending_CSL : 1; /*!< [1..1] Current security level: 0=Secure, 1=Non secure */ + uint32_t : 30; + } RESET_b; + }; + + union + { + __IOM uint32_t QBASE0; /*!< (@ 0x00000010) Base address of Command-queue bits[31:0]. The + * address is 4-byte-aligned */ + + struct + { + __IOM uint32_t QBASE0 : 32; /*!< [31..0] The 4-byte-aligned lower bytes of the base address value + * for the command stream */ + } QBASE0_b; + }; + + union + { + __IOM uint32_t QBASE1; /*!< (@ 0x00000014) Address extension bits[47:32] for queue base */ + + struct + { + __IOM uint32_t QBASE1 : 32; /*!< [31..0] The 4-byte-aligned upper bytes of the base address value + * for the command stream */ + } QBASE1_b; + }; + + union + { + __IM uint32_t QREAD; /*!< (@ 0x00000018) Read offset in the command stream in bytes. Multiples + * of 4 in the range 0-16 MB */ + + struct + { + __IM uint32_t QREAD : 32; /*!< [31..0] The read offset of the current command under execution */ + } QREAD_b; + }; + + union + { + __IOM uint32_t QCONFIG; /*!< (@ 0x0000001C) AXI configuration for the command stream in the + * range 0-3. Same encoding as for REGIONCFG */ + + struct + { + __IOM uint32_t QCONFIG : 32; /*!< [31..0] AXI configuration for the command stream in the range + * 0-3 */ + } QCONFIG_b; + }; + + union + { + __IOM uint32_t QSIZE; /*!< (@ 0x00000020) Size of the command stream in bytes. Multiples + * of 4 in the range 0-16 MB */ + + struct + { + __IOM uint32_t QSIZE : 32; /*!< [31..0] Size of the next command stream to be executed by the + * NPU */ + } QSIZE_b; + }; + + union + { + __IM uint32_t PROT; /*!< (@ 0x00000024) Protection level configured for the NPU when + * acting as an AXI master */ + + struct + { + __IM uint32_t active_CPL : 1; /*!< [0..0] Current privilege level: 0=User, 1=Privileged */ + __IM uint32_t active_CSL : 1; /*!< [1..1] Current security level: 0=Secure, 1=Non-secure */ + uint32_t : 30; + } PROT_b; + }; + + union + { + __IM uint32_t CONFIG; /*!< (@ 0x00000028) RTL configuration */ + + struct + { + __IM uint32_t macs_per_cc : 4; /*!< [3..0] The log2(macs/clock cycle). Valid encoding range is 5-8 + * for 32-256 MACs/clock cycle. */ + __IM uint32_t cmd_stream_version : 4; /*!< [7..4] Command-stream version accepted by this NPU. */ + __IM uint32_t shram_size : 8; /*!< [15..8] Size in KB of SHRAM in the range 8-48. */ + uint32_t : 11; + __IM uint32_t custom_dma : 1; /*!< [27..27] Custom DMA configuration */ + __IM uint32_t product : 4; /*!< [31..28] Product configuration */ + } CONFIG_b; + }; + + union + { + __IOM uint32_t LOCK; /*!< (@ 0x0000002C) Lock register. This register is designed for + * driver use and does not affect NPU functionality */ + + struct + { + __IOM uint32_t LOCK : 32; /*!< [31..0] 32-bit value for the LOCK configuration */ + } LOCK_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t REGIONCFG; /*!< (@ 0x0000003C) Base pointer configuration. Bits[2*k+1:2*k] give + * the memory type for REGION[k] */ + + struct + { + __IOM uint32_t region0 : 2; /*!< [1..0] Bits for the Region0 configuration */ + __IOM uint32_t region1 : 2; /*!< [3..2] Bits for the Region1 configuration */ + __IOM uint32_t region2 : 2; /*!< [5..4] Bits for the Region2 configuration */ + __IOM uint32_t region3 : 2; /*!< [7..6] Bits for the Region3 configuration */ + __IOM uint32_t region4 : 2; /*!< [9..8] Bits for the Region4 configuration */ + __IOM uint32_t region5 : 2; /*!< [11..10] Bits for the Region5 configuration */ + __IOM uint32_t region6 : 2; /*!< [13..12] Bits for the Region6 configuration */ + __IOM uint32_t region7 : 2; /*!< [15..14] Bits for the Region7 configuration */ + uint32_t : 16; + } REGIONCFG_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT0; /*!< (@ 0x00000040) AXI limits for port 0 counter 0 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT0_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT1; /*!< (@ 0x00000044) AXI limits for port 0 counter 1 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT1_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT2; /*!< (@ 0x00000048) AXI limits for port 1 counter 2 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT2_b; + }; + + union + { + __IOM uint32_t AXI_LIMIT3; /*!< (@ 0x0000004C) AXI limits for port 1 counter 3 */ + + struct + { + __IOM uint32_t max_beats : 2; /*!< [1..0] Burst-split alignment: 0=64 bytes, 1=128 bytes, 2=256 + * bytes, 3=reserved */ + uint32_t : 2; + __IOM uint32_t memtype : 4; /*!< [7..4] Memtype */ + uint32_t : 8; + __IOM uint32_t max_outstanding_read_m1 : 8; /*!< [23..16] Maximum number of outstanding AXI read transactions + * - 1 in range 0-31 */ + __IOM uint32_t max_outstanding_write_m1 : 8; /*!< [31..24] Maximum number of outstanding AXI write transactions + * - 1 in range 0-15 */ + } AXI_LIMIT3_b; + }; + __IM uint32_t RESERVED1[12]; + + union + { + __IOM uint32_t BASEP0; /*!< (@ 0x00000080) Lower 32 bits of the Base pointer for region + * index 0 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP0_b; + }; + + union + { + __IOM uint32_t BASEP1; /*!< (@ 0x00000084) Upper 32 bits of the Base pointer for region + * index 0 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP1_b; + }; + + union + { + __IOM uint32_t BASEP2; /*!< (@ 0x00000088) Lower 32 bits of the Base pointer for region + * index 1 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP2_b; + }; + + union + { + __IOM uint32_t BASEP3; /*!< (@ 0x0000008C) Upper 32 bits of the Base pointer for region + * index 1 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP3_b; + }; + + union + { + __IOM uint32_t BASEP4; /*!< (@ 0x00000090) Lower 32 bits of the Base pointer for region + * index 2 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP4_b; + }; + + union + { + __IOM uint32_t BASEP5; /*!< (@ 0x00000094) Upper 32 bits of the Base pointer for region + * index 2 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP5_b; + }; + + union + { + __IOM uint32_t BASEP6; /*!< (@ 0x00000098) Lower 32 bits of the Base pointer for region + * index 3 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP6_b; + }; + + union + { + __IOM uint32_t BASEP7; /*!< (@ 0x0000009C) Upper 32 bits of the Base pointer for region + * index 3 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP7_b; + }; + + union + { + __IOM uint32_t BASEP8; /*!< (@ 0x000000A0) Lower 32 bits of the Base pointer for region + * index 4 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP8_b; + }; + + union + { + __IOM uint32_t BASEP9; /*!< (@ 0x000000A4) Upper 32 bits of the Base pointer for region + * index 4 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP9_b; + }; + + union + { + __IOM uint32_t BASEP10; /*!< (@ 0x000000A8) Lower 32 bits of the Base pointer for region + * index 5 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP10_b; + }; + + union + { + __IOM uint32_t BASEP11; /*!< (@ 0x000000AC) Upper 32 bits of the Base pointer for region + * index 5 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP11_b; + }; + + union + { + __IOM uint32_t BASEP12; /*!< (@ 0x000000B0) Lower 32 bits of the Base pointer for region + * index 6 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP12_b; + }; + + union + { + __IOM uint32_t BASEP13; /*!< (@ 0x000000B4) Upper 32 bits of the Base pointer for region + * index 6 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP13_b; + }; + + union + { + __IOM uint32_t BASEP14; /*!< (@ 0x000000B8) Lower 32 bits of the Base pointer for region + * index 7 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The low word of the 64-bit address */ + } BASEP14_b; + }; + + union + { + __IOM uint32_t BASEP15; /*!< (@ 0x000000BC) Upper 32 bits of the Base pointer for region + * index 7 */ + + struct + { + __IOM uint32_t addr_word : 32; /*!< [31..0] The high word of the 64-bit address */ + } BASEP15_b; + }; + __IM uint32_t RESERVED2[48]; + + union + { + __IOM uint32_t PMCR; /*!< (@ 0x00000180) PMU master control register */ + + struct + { + __IOM uint32_t cnt_en : 1; /*!< [0..0] Enable counter */ + __IOM uint32_t event_cnt_rst : 1; /*!< [1..1] Reset event counter */ + __IOM uint32_t cycle_cnt_rst : 1; /*!< [2..2] Reset cycle counter */ + __IOM uint32_t mask_en : 1; /*!< [3..3] PMU can be enabled/disabled by command stream operationNPU_OP_PMU_MASK */ + uint32_t : 7; + __IOM uint32_t num_event_cnt : 5; /*!< [15..11] Number of event counters available for performance + * measurement */ + uint32_t : 16; + } PMCR_b; + }; + + union + { + __IOM uint32_t PMCNTENSET; /*!< (@ 0x00000184) Count-enable set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0 : 1; /*!< [0..0] Event-counter enable bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1 : 1; /*!< [1..1] Event-counter enable bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2 : 1; /*!< [2..2] Event-counter enable bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3 : 1; /*!< [3..3] Event-counter enable bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT : 1; /*!< [31..31] PMCCNTR enable bit */ + } PMCNTENSET_b; + }; + + union + { + __IOM uint32_t PMCNTENCLR; /*!< (@ 0x00000188) Count-enable clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0 : 1; /*!< [0..0] Event-counter disable bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1 : 1; /*!< [1..1] Event-counter disable bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2 : 1; /*!< [2..2] Event-counter disable bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3 : 1; /*!< [3..3] Event-counter disable bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT : 1; /*!< [31..31] PMCCNTR disable bit */ + } PMCNTENCLR_b; + }; + + union + { + __IOM uint32_t PMOVSSET; /*!< (@ 0x0000018C) Overflow-flag status set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_OVF : 1; /*!< [0..0] Event-counter overflow set bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_OVF : 1; /*!< [1..1] Event-counter overflow set bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_OVF : 1; /*!< [2..2] Event-counter overflow set bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_OVF : 1; /*!< [3..3] Event-counter overflow set bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_OVF : 1; /*!< [31..31] PMCCNTR overflow set bit */ + } PMOVSSET_b; + }; + + union + { + __IOM uint32_t PMOVSCLR; /*!< (@ 0x00000190) Overflow-flag status clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_OVF : 1; /*!< [0..0] Event-counter overflow clear bit for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_OVF : 1; /*!< [1..1] Event-counter overflow clear bit for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_OVF : 1; /*!< [2..2] Event-counter overflow clear bit for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_OVF : 1; /*!< [3..3] Event-counter overflow clear bit for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_OVF : 1; /*!< [31..31] PMCCNTR overflow clear bit */ + } PMOVSCLR_b; + }; + + union + { + __IOM uint32_t PMINTSET; /*!< (@ 0x00000194) Interrupt-enable set register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_INT : 1; /*!< [0..0] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_INT : 1; /*!< [1..1] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_INT : 1; /*!< [2..2] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_INT : 1; /*!< [3..3] Event-counter overflow interrupt-request enable bit for + * PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_INT : 1; /*!< [31..31] PMCCNTR overflow interrupt-request enable bit */ + } PMINTSET_b; + }; + + union + { + __IOM uint32_t PMINTCLR; /*!< (@ 0x00000198) Interrupt-enable clear register */ + + struct + { + __IOM uint32_t EVENT_CNT_0_INT : 1; /*!< [0..0] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR0 */ + __IOM uint32_t EVENT_CNT_1_INT : 1; /*!< [1..1] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR1 */ + __IOM uint32_t EVENT_CNT_2_INT : 1; /*!< [2..2] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR2 */ + __IOM uint32_t EVENT_CNT_3_INT : 1; /*!< [3..3] Event-counter overflow interrupt-request disable bit + * for PMU_EVCNTR3 */ + uint32_t : 27; + __IOM uint32_t CYCLE_CNT_INT : 1; /*!< [31..31] PMCCNTR overflow interrupt-request disable bit */ + } PMINTCLR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PMCCNTR_LO; /*!< (@ 0x000001A0) Performance-monitor cycle count low register */ + + struct + { + __IOM uint32_t CYCLE_CNT_LO : 32; /*!< [31..0] Cycle count low */ + } PMCCNTR_LO_b; + }; + + union + { + __IOM uint32_t PMCCNTR_HI; /*!< (@ 0x000001A4) Performance-monitor cycle count high register */ + + struct + { + __IOM uint32_t CYCLE_CNT_HI : 32; /*!< [31..0] Cycle count high */ + } PMCCNTR_HI_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t PMCAXI_CHAN; /*!< (@ 0x000001AC) Set which AXI channel monitor */ + + struct + { + __IOM uint32_t CH_SEL : 4; /*!< [3..0] Specify the type of traffic for bandwidth or latency + * measurements (Read: 0=command traffic, 1=IFM traffic, 2=Weight + * traffic, 3=Scale+Bias, 4=Mem2Mem traffic - read direction; + * Write: 8=OFM traffic, 9=Mem2Mem traffic - write direction) */ + uint32_t : 4; + __IOM uint32_t AXI_CNT_SEL : 2; /*!< [9..8] Select AXI counter to monitor for latency measurements + * (0=AXI0 counter0, 1=AXI0 counter1, 2=AXI1 counter 2, 3=AXI1 + * counter3) */ + __IOM uint32_t BW_CH_SEL_EN : 1; /*!< [10..10] Enable bandwidth channel selector: 0=AXI bw events + * measured for all channels, 1=AXI bw events measured for + * channel specified by CH_SEL */ + uint32_t : 21; + } PMCAXI_CHAN_b; + }; + __IM uint32_t RESERVED5[84]; + + union + { + __IOM uint32_t PMU_EVCNTR0; /*!< (@ 0x00000300) Performance-monitor event counters 0 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR0_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR1; /*!< (@ 0x00000304) Performance-monitor event counters 1 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR1_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR2; /*!< (@ 0x00000308) Performance-monitor event counters 2 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR2_b; + }; + + union + { + __IOM uint32_t PMU_EVCNTR3; /*!< (@ 0x0000030C) Performance-monitor event counters 3 */ + + struct + { + __IOM uint32_t PMEVCNTR : 32; /*!< [31..0] Performance-monitor event counters. */ + } PMU_EVCNTR3_b; + }; + __IM uint32_t RESERVED6[28]; + + union + { + __IOM uint32_t PMU_EVTYPER0; /*!< (@ 0x00000380) Performance-monitor event-type control counters + * 0 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER0_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER1; /*!< (@ 0x00000384) Performance-monitor event-type control counters + * 1 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER1_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER2; /*!< (@ 0x00000388) Performance-monitor event-type control counters + * 2 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER2_b; + }; + + union + { + __IOM uint32_t PMU_EVTYPER3; /*!< (@ 0x0000038C) Performance-monitor event-type control counters + * 3 */ + + struct + { + __IOM uint32_t EV_TYPE : 32; /*!< [31..0] Event type. */ + } PMU_EVTYPER3_b; + }; + __IM uint32_t RESERVED7[784]; + + union + { + __IM uint32_t PID4; /*!< (@ 0x00000FD0) Peripheral ID byte 4 (Arm=code 4) */ + + struct + { + __IM uint32_t PID4 : 32; /*!< [31..0] Byte 4 of the Peripheral ID (Lower 8 bits valid) */ + } PID4_b; + }; + + union + { + __IM uint32_t PID5; /*!< (@ 0x00000FD4) Peripheral ID byte 5 (reserved) */ + + struct + { + __IM uint32_t PID5 : 32; /*!< [31..0] Byte 5 of the Peripheral ID (Lower 8 bits valid) */ + } PID5_b; + }; + + union + { + __IM uint32_t PID6; /*!< (@ 0x00000FD8) Peripheral ID byte 6 (reserved) */ + + struct + { + __IM uint32_t PID6 : 32; /*!< [31..0] Byte 6 of the Peripheral ID (Lower 8 bits valid) */ + } PID6_b; + }; + + union + { + __IM uint32_t PID7; /*!< (@ 0x00000FDC) Peripheral ID byte 7 (reserved) */ + + struct + { + __IM uint32_t PID7 : 32; /*!< [31..0] Byte 7 of the Peripheral ID (Lower 8 bits valid) */ + } PID7_b; + }; + + union + { + __IM uint32_t PID0; /*!< (@ 0x00000FE0) Peripheral ID byte 0. This is bits[7:0] of the + * part number. */ + + struct + { + __IM uint32_t PID0 : 32; /*!< [31..0] Byte 0 of the Peripheral ID (Lower 8 bits valid) */ + } PID0_b; + }; + + union + { + __IM uint32_t PID1; /*!< (@ 0x00000FE4) Peripheral ID byte 1. This is bits[11:8] of the + * part number in bits[3:0], and bits[3:0] + * of the Arm ID in bits[7:4]. */ + + struct + { + __IM uint32_t PID1 : 32; /*!< [31..0] Byte 1 of the Peripheral ID (Lower 8 bits valid) */ + } PID1_b; + }; + + union + { + __IM uint32_t PID2; /*!< (@ 0x00000FE8) Peripheral ID byte 2. This is bits[6:4] of the + * Arm ID in bits[2:0], and bit 3 indicates + * format B. */ + + struct + { + __IM uint32_t PID2 : 32; /*!< [31..0] Byte 2 of the Peripheral ID (Lower 8 bits valid) */ + } PID2_b; + }; + + union + { + __IM uint32_t PID3; /*!< (@ 0x00000FEC) Peripheral ID byte 3. */ + + struct + { + __IM uint32_t PID3 : 32; /*!< [31..0] Byte 3 of the Peripheral ID (Lower 8 bits valid) */ + } PID3_b; + }; + + union + { + __IM uint32_t CID0; /*!< (@ 0x00000FF0) Component ID byte 0. */ + + struct + { + __IM uint32_t CID0 : 32; /*!< [31..0] Byte 0 of the Component ID (Lower 8 bits valid) */ + } CID0_b; + }; + + union + { + __IM uint32_t CID1; /*!< (@ 0x00000FF4) Component ID byte 1. */ + + struct + { + __IM uint32_t CID1 : 32; /*!< [31..0] Byte 1 of the Component ID (Lower 8 bits valid) */ + } CID1_b; + }; + + union + { + __IM uint32_t CID2; /*!< (@ 0x00000FF8) Component ID byte 2. */ + + struct + { + __IM uint32_t CID2 : 32; /*!< [31..0] Byte 2 of the Component ID (Lower 8 bits valid) */ + } CID2_b; + }; + + union + { + __IM uint32_t CID3; /*!< (@ 0x00000FFC) Component ID byte 3. */ + + struct + { + __IM uint32_t CID3 : 32; /*!< [31..0] Byte 3 of the Component ID (Lower 8 bits valid) */ + } CID3_b; + }; +} R_NPU_Type; /*!< Size = 4096 (0x1000) */ + +/* =========================================================================================================================== */ +/* ================ R_PDM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Pulse Density Modulator Interface (R_PDM) + */ + +typedef struct /*!< (@ 0x40256000) R_PDM Structure */ +{ + union + { + __OM uint32_t PDCSTRTR; /*!< (@ 0x00000000) Channel Software Start Trigger Register */ + + struct + { + __OM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger */ + __OM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger */ + __OM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger */ + uint32_t : 29; + } PDCSTRTR_b; + }; + + union + { + __OM uint32_t PDCSTPTR; /*!< (@ 0x00000004) Channel Software Stop Trigger Register */ + + struct + { + __OM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger */ + __OM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger */ + __OM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger */ + uint32_t : 29; + } PDCSTPTR_b; + }; + + union + { + __OM uint32_t PDCCHGTR; /*!< (@ 0x00000008) Channel Software Change Trigger Register */ + + struct + { + __OM uint32_t CHGTRG0 : 1; /*!< [0..0] Channel 0 change trigger */ + __OM uint32_t CHGTRG1 : 1; /*!< [1..1] Channel 1 change trigger */ + __OM uint32_t CHGTRG2 : 1; /*!< [2..2] Channel 2 change trigger */ + uint32_t : 29; + } PDCCHGTR_b; + }; + + union + { + __IOM uint32_t PDCICR; /*!< (@ 0x0000000C) Channel Interrupt Control Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t ISDE0 : 1; /*!< [8..8] Channel 0 sound detection interrupt enable bit */ + __IOM uint32_t ISDE1 : 1; /*!< [9..9] Channel 1 sound detection interrupt enable bit */ + __IOM uint32_t ISDE2 : 1; /*!< [10..10] Channel 2 sound detection interrupt enable bit */ + uint32_t : 5; + __IOM uint32_t IDRE0 : 1; /*!< [16..16] Channel 0 data reception interrupt enable bit */ + __IOM uint32_t IDRE1 : 1; /*!< [17..17] Channel 1 data reception interrupt enable bit */ + __IOM uint32_t IDRE2 : 1; /*!< [18..18] Channel 2 data reception interrupt enable bit */ + uint32_t : 5; + __IOM uint32_t IEDE0 : 1; /*!< [24..24] Channel 0 error detection interrupt enable bit */ + __IOM uint32_t IEDE1 : 1; /*!< [25..25] Channel 1 error detection interrupt enable bit */ + __IOM uint32_t IEDE2 : 1; /*!< [26..26] Channel 2 error detection interrupt enable bit */ + uint32_t : 5; + } PDCICR_b; + }; + + union + { + __IM uint32_t PDCSR; /*!< (@ 0x00000010) Channel Status Register */ + + struct + { + __IM uint32_t STATE0 : 1; /*!< [0..0] Channel 0 state */ + __IM uint32_t STATE1 : 1; /*!< [1..1] Channel 1 state */ + __IM uint32_t STATE2 : 1; /*!< [2..2] Channel 2 state */ + uint32_t : 5; + __IM uint32_t SDF0 : 1; /*!< [8..8] Channel 0 sound detection flag */ + __IM uint32_t SDF1 : 1; /*!< [9..9] Channel 1 sound detection flag */ + __IM uint32_t SDF2 : 1; /*!< [10..10] Channel 2 sound detection flag */ + uint32_t : 5; + __IM uint32_t DRF0 : 1; /*!< [16..16] Channel 0 data reception flag */ + __IM uint32_t DRF1 : 1; /*!< [17..17] Channel 1 data reception flag */ + __IM uint32_t DRF2 : 1; /*!< [18..18] Channel 2 data reception flag */ + uint32_t : 5; + __IM uint32_t EDF0 : 1; /*!< [24..24] Channel 0 error detection flag */ + __IM uint32_t EDF1 : 1; /*!< [25..25] Channel 1 error detection flag */ + __IM uint32_t EDF2 : 1; /*!< [26..26] Channel 2 error detection flag */ + uint32_t : 5; + } PDCSR_b; + }; + + union + { + __OM uint32_t PDCSCR; /*!< (@ 0x00000014) Channel Status Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t SDFC0 : 1; /*!< [8..8] Channel 0 sound detection flag clear */ + __OM uint32_t SDFC1 : 1; /*!< [9..9] Channel 1 sound detection flag clear */ + __OM uint32_t SDFC2 : 1; /*!< [10..10] Channel 2 sound detection flag clear */ + uint32_t : 21; + } PDCSCR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t PDCSDCR; /*!< (@ 0x00000020) Channel Sound Detection Control Register */ + + struct + { + __IOM uint32_t SDE0 : 1; /*!< [0..0] Channel 0 sound detection enable bit */ + __IOM uint32_t SDE1 : 1; /*!< [1..1] Channel 1 sound detection enable bit */ + __IOM uint32_t SDE2 : 1; /*!< [2..2] Channel 2 sound detection enable bit */ + uint32_t : 29; + } PDCSDCR_b; + }; + + union + { + __IOM uint32_t PDCDRCR; /*!< (@ 0x00000024) Channel Data Read Control Register */ + + struct + { + __IOM uint32_t DATRE0 : 1; /*!< [0..0] Channel 0 data read enable bit */ + __IOM uint32_t DATRE1 : 1; /*!< [1..1] Channel 1 data read enable bit */ + __IOM uint32_t DATRE2 : 1; /*!< [2..2] Channel 2 data read enable bit */ + uint32_t : 29; + } PDCDRCR_b; + }; + + union + { + __OM uint32_t PDCDCR; /*!< (@ 0x00000028) Channel Data Clear Register */ + + struct + { + __OM uint32_t DATC0 : 1; /*!< [0..0] Channel 0 data clear */ + __OM uint32_t DATC1 : 1; /*!< [1..1] Channel 1 data clear */ + __OM uint32_t DATC2 : 1; /*!< [2..2] Channel 2 data clear */ + uint32_t : 29; + } PDCDCR_b; + }; + __IM uint32_t RESERVED1[21]; + + union + { + __IM uint32_t PDVR; /*!< (@ 0x00000080) Version Register */ + + struct + { + __IM uint32_t VER : 12; /*!< [11..0] Version */ + uint32_t : 20; + } PDVR_b; + }; + __IM uint32_t RESERVED2[31]; + __IOM R_PDM_CH_Type CH[3]; /*!< (@ 0x00000100) PDM Channel-Specific Registers */ +} R_PDM_Type; /*!< Size = 1024 (0x400) */ + +/* =========================================================================================================================== */ +/* ================ R_RMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC (R_RMAC0) + */ + +typedef struct /*!< (@ 0x403CB000) R_RMAC0 Structure */ +{ + union + { + __IOM uint32_t MPSM; /*!< (@ 0x00000000) MAC PHY Station Management Register (MPSM) */ + + struct + { + __IOM uint32_t PSME : 1; /*!< [0..0] PSME */ + uint32_t : 1; + __IOM uint32_t MFF : 1; /*!< [2..2] MFF */ + __IOM uint32_t PDA : 5; /*!< [7..3] PDA */ + __IOM uint32_t PRA : 5; /*!< [12..8] PRA */ + __IOM uint32_t POP : 2; /*!< [14..13] POP */ + uint32_t : 1; + __IOM uint32_t PRD : 16; /*!< [31..16] PRD */ + } MPSM_b; + }; + + union + { + __IOM uint32_t MPIC; /*!< (@ 0x00000004) MAC PHY Interfaces Configuration Register (MPIC) */ + + struct + { + __IOM uint32_t PIS : 3; /*!< [2..0] PIS */ + __IOM uint32_t LSC : 3; /*!< [5..3] LSC */ + uint32_t : 2; + __IOM uint32_t PIP : 1; /*!< [8..8] PIP */ + __IOM uint32_t PIPP : 1; /*!< [9..9] PIPP */ + __IOM uint32_t PLSPP : 1; /*!< [10..10] PLSPP */ + uint32_t : 5; + __IOM uint32_t PSMCS : 7; /*!< [22..16] PSMCS */ + __IOM uint32_t PSMDP : 1; /*!< [23..23] PSMDP */ + __IOM uint32_t PSMHT : 3; /*!< [26..24] PSMHT */ + uint32_t : 1; + __IOM uint32_t PSMCT : 3; /*!< [30..28] PSMCT */ + uint32_t : 1; + } MPIC_b; + }; + + union + { + __IOM uint32_t MPIM; /*!< (@ 0x00000008) MAC PHY Interfaces Monitoring Register (MPIM) */ + + struct + { + __IOM uint32_t PLS : 1; /*!< [0..0] PLS */ + __IOM uint32_t LPIA : 1; /*!< [1..1] LPIA */ + uint32_t : 30; + } MPIM_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t MIOC; /*!< (@ 0x00000010) RMAC IO Configuration Registers Register (MIOC) */ + + struct + { + __IOM uint32_t MIOC : 32; /*!< [31..0] MIOC */ + } MIOC_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t MTFFC; /*!< (@ 0x00000020) MAC Transmission Frame Format Configuration Register + * (MTFFC) */ + + struct + { + __IOM uint32_t DPAD : 1; /*!< [0..0] DPAD */ + __IOM uint32_t FCM : 1; /*!< [1..1] FCM */ + uint32_t : 30; + } MTFFC_b; + }; + + union + { + __IOM uint32_t MTPFC; /*!< (@ 0x00000024) MAC Transmission Pause or PFC Frame Configuration + * Register (MTPFC) */ + + struct + { + __IOM uint32_t PT : 16; /*!< [15..0] PT */ + __IOM uint32_t PFRT : 8; /*!< [23..16] PFRT */ + uint32_t : 2; + __IOM uint32_t PFM : 1; /*!< [26..26] PFM */ + __IOM uint32_t PFRLV : 5; /*!< [31..27] PFRLV */ + } MTPFC_b; + }; + + union + { + __IOM uint32_t MTPFC2; /*!< (@ 0x00000028) MAC Transmission Pause or PFC Frame configuration2 + * Register (MTPFC2) */ + + struct + { + __IOM uint32_t PFCTTZ : 2; /*!< [1..0] PFCTTZ */ + uint32_t : 6; + __IOM uint32_t MPFCFR0 : 1; /*!< [8..8] MPFCFR0 */ + __IOM uint32_t MPFCFR1 : 1; /*!< [9..9] MPFCFR1 */ + uint32_t : 6; + __IOM uint32_t PFTTZ : 1; /*!< [16..16] PFTTZ */ + __IOM uint32_t MPFR : 1; /*!< [17..17] MPFR */ + uint32_t : 14; + } MTPFC2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MTPFC30; /*!< (@ 0x00000030) MAC Transmission Pause or PFC Frame Configuration + * Register 3 (MTPFC3t) (t = 0, 1) */ + + struct + { + __IOM uint32_t PFCPG : 8; /*!< [7..0] PFCPG */ + uint32_t : 24; + } MTPFC30_b; + }; + + union + { + __IOM uint32_t MTPFC31; /*!< (@ 0x00000034) MAC Transmission Pause or PFC Frame Configuration + * Register 3 (MTPFC3t) (t = 0, 1) */ + + struct + { + __IOM uint32_t PFCPG : 8; /*!< [7..0] PFCPG */ + uint32_t : 24; + } MTPFC31_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t MTATC0; /*!< (@ 0x00000050) MAC Transmission Automatic Timestamp Configuration + * Register (MTATCt) (t = 0, 1) */ + + struct + { + __IOM uint32_t TRTP : 8; /*!< [7..0] TRTP */ + __IOM uint32_t TRTL : 3; /*!< [10..8] TRTL */ + uint32_t : 21; + } MTATC0_b; + }; + + union + { + __IOM uint32_t MTATC1; /*!< (@ 0x00000054) MAC Transmission Automatic Timestamp Configuration + * Register (MTATCt) (t = 0, 1) */ + + struct + { + __IOM uint32_t TRTP : 8; /*!< [7..0] TRTP */ + __IOM uint32_t TRTL : 3; /*!< [10..8] TRTL */ + uint32_t : 21; + } MTATC1_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IOM uint32_t MTIM; /*!< (@ 0x00000060) MAC Transmission Interfaces Monitoring Register + * (MTIM) */ + + struct + { + __IOM uint32_t TS : 1; /*!< [0..0] TS */ + uint32_t : 31; + } MTIM_b; + }; + __IM uint32_t RESERVED5[7]; + + union + { + __IOM uint32_t MRGC; /*!< (@ 0x00000080) MAC Reception General Configuration Register + * (MRGC) */ + + struct + { + __IOM uint32_t RCPT : 1; /*!< [0..0] RCPT */ + __IOM uint32_t PFRC : 1; /*!< [1..1] PFRC */ + __IOM uint32_t PFRTZ : 1; /*!< [2..2] PFRTZ */ + __IOM uint32_t MPDE : 1; /*!< [3..3] MPDE */ + __IOM uint32_t RFCFE : 1; /*!< [4..4] RFCFE */ + uint32_t : 11; + __IOM uint32_t PFCRC : 8; /*!< [23..16] PFCRC */ + uint32_t : 8; + } MRGC_b; + }; + + union + { + __IOM uint32_t MRMAC0; /*!< (@ 0x00000084) MAC Reception MAC Address Configuration Register + * 0 (MRMAC0) */ + + struct + { + __IOM uint32_t MAU : 16; /*!< [15..0] MAU */ + uint32_t : 16; + } MRMAC0_b; + }; + + union + { + __IOM uint32_t MRMAC1; /*!< (@ 0x00000088) MAC Reception MAC Address Configuration Register + * 1 (MRMAC1) */ + + struct + { + __IOM uint32_t MAL : 32; /*!< [31..0] MAL */ + } MRMAC1_b; + }; + + union + { + __IOM uint32_t MRAFC; /*!< (@ 0x0000008C) MAC Reception Address Filter Configuration Register + * (MRAFC) */ + + struct + { + __IOM uint32_t UCENE : 1; /*!< [0..0] UCENE */ + __IOM uint32_t MCENE : 1; /*!< [1..1] MCENE */ + __IOM uint32_t BCENE : 1; /*!< [2..2] BCENE */ + __IOM uint32_t MSTENE : 1; /*!< [3..3] MSTENE */ + __IOM uint32_t BSTENE : 1; /*!< [4..4] BSTENE */ + __IOM uint32_t MCACE : 1; /*!< [5..5] MCACE */ + __IOM uint32_t BCACE : 1; /*!< [6..6] BCACE */ + __IOM uint32_t NDAREE : 1; /*!< [7..7] NDAREE */ + __IOM uint32_t SDSFREE : 1; /*!< [8..8] SDSFREE */ + __IOM uint32_t NSAREE : 1; /*!< [9..9] NSAREE */ + __IOM uint32_t MSAREE : 1; /*!< [10..10] MSAREE */ + uint32_t : 5; + __IOM uint32_t UCENP : 1; /*!< [16..16] UCENP */ + __IOM uint32_t MCENP : 1; /*!< [17..17] MCENP */ + __IOM uint32_t BCENP : 1; /*!< [18..18] BCENP */ + __IOM uint32_t MSTENP : 1; /*!< [19..19] MSTENP */ + __IOM uint32_t BSTENP : 1; /*!< [20..20] BSTENP */ + __IOM uint32_t MCACP : 1; /*!< [21..21] MCACP */ + __IOM uint32_t BCACP : 1; /*!< [22..22] BCACP */ + __IOM uint32_t NDAREP : 1; /*!< [23..23] NDAREP */ + __IOM uint32_t SDSFREP : 1; /*!< [24..24] SDSFREP */ + __IOM uint32_t NSAREP : 1; /*!< [25..25] NSAREP */ + __IOM uint32_t MSAREP : 1; /*!< [26..26] MSAREP */ + uint32_t : 5; + } MRAFC_b; + }; + + union + { + __IOM uint32_t MRSCE; /*!< (@ 0x00000090) MAC Reception Storm Configuration for e-Frames + * Register (MRSCE) */ + + struct + { + __IOM uint32_t CMFE : 16; /*!< [15..0] CMFE */ + __IOM uint32_t CBFE : 16; /*!< [31..16] CBFE */ + } MRSCE_b; + }; + + union + { + __IOM uint32_t MRSCP; /*!< (@ 0x00000094) MAC Reception Storm Configuration for p-Frames + * Register (MRSCP) */ + + struct + { + __IOM uint32_t CMFP : 16; /*!< [15..0] CMFP */ + __IOM uint32_t CBFP : 16; /*!< [31..16] CBFP */ + } MRSCP_b; + }; + + union + { + __IOM uint32_t MRSCC; /*!< (@ 0x00000098) MAC Reception Storm Counter Configuration Register + * (MRSCC) */ + + struct + { + __IOM uint32_t MSCCE : 1; /*!< [0..0] MSCCE */ + __IOM uint32_t BSCCE : 1; /*!< [1..1] BSCCE */ + uint32_t : 14; + __IOM uint32_t MSCCP : 1; /*!< [16..16] MSCCP */ + __IOM uint32_t BSCCP : 1; /*!< [17..17] BSCCP */ + uint32_t : 14; + } MRSCC_b; + }; + + union + { + __IOM uint32_t MRFSCE; /*!< (@ 0x0000009C) MAC Reception Frame Size Configuration for e-Frames + * Register (MRFSCE) */ + + struct + { + __IOM uint32_t EMXS : 16; /*!< [15..0] EMXS */ + __IOM uint32_t EMNS : 16; /*!< [31..16] EMNS */ + } MRFSCE_b; + }; + + union + { + __IOM uint32_t MRFSCP; /*!< (@ 0x000000A0) MAC Reception Frame Size Configuration for p-Frames + * Register (MRFSCP) */ + + struct + { + __IOM uint32_t PMXS : 16; /*!< [15..0] PMXS */ + __IOM uint32_t PMNS : 16; /*!< [31..16] PMNS */ + } MRFSCP_b; + }; + + union + { + __IOM uint32_t MTRC; /*!< (@ 0x000000A4) MAC Timestamp Reception Configuration Register + * (MTRC) */ + + struct + { + __IOM uint32_t TRHFME0 : 1; /*!< [0..0] TRHFME0 */ + __IOM uint32_t TRHFME1 : 1; /*!< [1..1] TRHFME1 */ + uint32_t : 22; + __IOM uint32_t TRDDE : 1; /*!< [24..24] TRDDE */ + __IOM uint32_t TRDDP : 1; /*!< [25..25] TRDDP */ + __IOM uint32_t TCTSE : 1; /*!< [26..26] TCTSE */ + __IOM uint32_t TCTSP : 1; /*!< [27..27] TCTSP */ + __IOM uint32_t DTN : 1; /*!< [28..28] DTN */ + uint32_t : 3; + } MTRC_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t MRPFM; /*!< (@ 0x000000AC) MAC Reception Pause or PFC Frame Monitoring Register + * (MRPFM) */ + + struct + { + __IOM uint32_t PTCA : 1; /*!< [0..0] PTCA */ + uint32_t : 15; + __IOM uint32_t PFCTCA : 8; /*!< [23..16] PFCTCA */ + uint32_t : 8; + } MRPFM_b; + }; + __IM uint32_t RESERVED7[20]; + + union + { + __IOM uint32_t MPFC0; /*!< (@ 0x00000100) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC0_b; + }; + + union + { + __IOM uint32_t MPFC1; /*!< (@ 0x00000104) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC1_b; + }; + + union + { + __IOM uint32_t MPFC2; /*!< (@ 0x00000108) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC2_b; + }; + + union + { + __IOM uint32_t MPFC3; /*!< (@ 0x0000010C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC3_b; + }; + + union + { + __IOM uint32_t MPFC4; /*!< (@ 0x00000110) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC4_b; + }; + + union + { + __IOM uint32_t MPFC5; /*!< (@ 0x00000114) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC5_b; + }; + + union + { + __IOM uint32_t MPFC6; /*!< (@ 0x00000118) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC6_b; + }; + + union + { + __IOM uint32_t MPFC7; /*!< (@ 0x0000011C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC7_b; + }; + + union + { + __IOM uint32_t MPFC8; /*!< (@ 0x00000120) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC8_b; + }; + + union + { + __IOM uint32_t MPFC9; /*!< (@ 0x00000124) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC9_b; + }; + + union + { + __IOM uint32_t MPFC10; /*!< (@ 0x00000128) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC10_b; + }; + + union + { + __IOM uint32_t MPFC11; /*!< (@ 0x0000012C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC11_b; + }; + + union + { + __IOM uint32_t MPFC12; /*!< (@ 0x00000130) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC12_b; + }; + + union + { + __IOM uint32_t MPFC13; /*!< (@ 0x00000134) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC13_b; + }; + + union + { + __IOM uint32_t MPFC14; /*!< (@ 0x00000138) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC14_b; + }; + + union + { + __IOM uint32_t MPFC15; /*!< (@ 0x0000013C) MAC PTP Filtering Register Configuration Register + * t (MPFCt) (t = 0 to 15) */ + + struct + { + __IOM uint32_t PFBN : 8; /*!< [7..0] PFBN */ + __IOM uint32_t PFBV : 8; /*!< [15..8] PFBV */ + __IOM uint32_t TEF0 : 1; /*!< [16..16] TEF0 */ + __IOM uint32_t TEF1 : 1; /*!< [17..17] TEF1 */ + uint32_t : 14; + } MPFC15_b; + }; + __IM uint32_t RESERVED8[16]; + + union + { + __IOM uint32_t MLVC; /*!< (@ 0x00000180) MAC Link Verification Configuration Register + * (MLVC) */ + + struct + { + __IOM uint32_t LVT : 7; /*!< [6..0] LVT */ + uint32_t : 1; + __IOM uint32_t PASE : 1; /*!< [8..8] PASE */ + uint32_t : 7; + __IOM uint32_t PLV : 1; /*!< [16..16] PLV */ + uint32_t : 15; + } MLVC_b; + }; + + union + { + __IOM uint32_t MEEEC; /*!< (@ 0x00000184) MAC Energy Efficient Ethernet Configuration Register + * (MEEEC) */ + + struct + { + __IOM uint32_t LPITR : 1; /*!< [0..0] LPITR */ + uint32_t : 31; + } MEEEC_b; + }; + + union + { + __IOM uint32_t MLBC; /*!< (@ 0x00000188) MAC Loopback Configuration Register (MLBC) */ + + struct + { + __IOM uint32_t LBME : 1; /*!< [0..0] LBME */ + uint32_t : 31; + } MLBC_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MXGMIIC; /*!< (@ 0x00000190) XGMII Configuration Register (MXGMIIC) */ + + struct + { + __IOM uint32_t LFS_TXRFS : 1; /*!< [0..0] LFS_TXRFS */ + __IOM uint32_t LFS_TXIDLE : 1; /*!< [1..1] LFS_TXIDLE */ + uint32_t : 30; + } MXGMIIC_b; + }; + + union + { + __IOM uint32_t MPCH; /*!< (@ 0x00000194) XGMII PCH Configuration Register (MPCH) */ + + struct + { + __IOM uint32_t TXPCH_M : 1; /*!< [0..0] TXPCH_M */ + uint32_t : 1; + __IOM uint32_t TXPCH_ETYPE : 2; /*!< [3..2] TXPCH_ETYPE */ + __IOM uint32_t TXPCH_PID : 4; /*!< [7..4] TXPCH_PID */ + __IOM uint32_t IETPTE : 1; /*!< [8..8] IETPTE */ + __IOM uint32_t CTPTE : 1; /*!< [9..9] CTPTE */ + __IOM uint32_t IETRIOD : 1; /*!< [10..10] IETRIOD */ + __IOM uint32_t CTRIOD : 1; /*!< [11..11] CTRIOD */ + uint32_t : 4; + __IOM uint32_t RXPCH_TSM : 1; /*!< [16..16] RXPCH_TSM */ + __IOM uint32_t RPHCRCD : 1; /*!< [17..17] RPHCRCD */ + uint32_t : 14; + } MPCH_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t MANM; /*!< (@ 0x0000019C) Auto-Negotiation Message Register (MANM) */ + + struct + { + __IOM uint32_t RX_AN_MES : 16; /*!< [15..0] RX_AN_MES */ + uint32_t : 16; + } MANM_b; + }; + __IM uint32_t RESERVED11[24]; + + union + { + __IOM uint32_t MEIS; /*!< (@ 0x00000200) MAC Error Interrupt Status Register (MEIS) */ + + struct + { + __IOM uint32_t TSLS : 1; /*!< [0..0] TSLS */ + __IOM uint32_t TIES : 1; /*!< [1..1] TIES */ + __IOM uint32_t PRES : 1; /*!< [2..2] PRES */ + __IOM uint32_t PFRROS : 1; /*!< [3..3] PFRROS */ + __IOM uint32_t FCDS : 1; /*!< [4..4] FCDS */ + __IOM uint32_t TCES : 1; /*!< [5..5] TCES */ + __IOM uint32_t TBCIS : 1; /*!< [6..6] TBCIS */ + __IOM uint32_t BFES : 1; /*!< [7..7] BFES */ + __IOM uint32_t FCES : 1; /*!< [8..8] FCES */ + __IOM uint32_t REOES : 1; /*!< [9..9] REOES */ + __IOM uint32_t RPOES : 1; /*!< [10..10] RPOES */ + __IOM uint32_t RPCRES : 1; /*!< [11..11] RPCRES */ + __IOM uint32_t CTLES0 : 1; /*!< [12..12] CTLES0 */ + __IOM uint32_t CTLES1 : 1; /*!< [13..13] CTLES1 */ + uint32_t : 6; + __IOM uint32_t PDES : 1; /*!< [20..20] PDES */ + __IOM uint32_t PNAES : 1; /*!< [21..21] PNAES */ + __IOM uint32_t FCMCES : 1; /*!< [22..22] FCMCES */ + __IOM uint32_t FFMES : 1; /*!< [23..23] FFMES */ + __IOM uint32_t CFCES : 1; /*!< [24..24] CFCES */ + __IOM uint32_t FRCES : 1; /*!< [25..25] FRCES */ + __IOM uint32_t RPOOMS : 1; /*!< [26..26] RPOOMS */ + __IOM uint32_t FFS : 1; /*!< [27..27] FFS */ + __IOM uint32_t FUES : 1; /*!< [28..28] FUES */ + __IOM uint32_t FOES : 1; /*!< [29..29] FOES */ + uint32_t : 2; + } MEIS_b; + }; + + union + { + __IOM uint32_t MEIE; /*!< (@ 0x00000204) MAC Error Interrupt Enable Register (MEIE) */ + + struct + { + __IOM uint32_t TSLE : 1; /*!< [0..0] TSLE */ + __IOM uint32_t TIEE : 1; /*!< [1..1] TIEE */ + __IOM uint32_t PMSEE : 1; /*!< [2..2] PMSEE */ + __IOM uint32_t PFRROE : 1; /*!< [3..3] PFRROE */ + __IOM uint32_t FCDE : 1; /*!< [4..4] FCDE */ + __IOM uint32_t TCEE : 1; /*!< [5..5] TCEE */ + __IOM uint32_t TBCIE : 1; /*!< [6..6] TBCIE */ + __IOM uint32_t BFEE : 1; /*!< [7..7] BFEE */ + __IOM uint32_t FCEE : 1; /*!< [8..8] FCEE */ + __IOM uint32_t REOEE : 1; /*!< [9..9] REOEE */ + __IOM uint32_t RPOEE : 1; /*!< [10..10] RPOEE */ + __IOM uint32_t RPCREE : 1; /*!< [11..11] RPCREE */ + __IOM uint32_t CTLEE0 : 1; /*!< [12..12] CTLEE0 */ + __IOM uint32_t CTLEE1 : 1; /*!< [13..13] CTLEE1 */ + uint32_t : 6; + __IOM uint32_t PDEE : 1; /*!< [20..20] PDEE */ + __IOM uint32_t PNAEE : 1; /*!< [21..21] PNAEE */ + __IOM uint32_t FCMCEE : 1; /*!< [22..22] FCMCEE */ + __IOM uint32_t FFMEE : 1; /*!< [23..23] FFMEE */ + __IOM uint32_t CFCEE : 1; /*!< [24..24] CFCEE */ + __IOM uint32_t FRCEE : 1; /*!< [25..25] FRCEE */ + __IOM uint32_t RPOOME : 1; /*!< [26..26] RPOOME */ + __IOM uint32_t FFE : 1; /*!< [27..27] FFE */ + __IOM uint32_t FUEE : 1; /*!< [28..28] FUEE */ + __IOM uint32_t FOEE : 1; /*!< [29..29] FOEE */ + uint32_t : 2; + } MEIE_b; + }; + + union + { + __IOM uint32_t MEID; /*!< (@ 0x00000208) MAC Error Interrupt Disable Register (MEID) */ + + struct + { + __IOM uint32_t TSLD : 1; /*!< [0..0] TSLD */ + __IOM uint32_t TIED : 1; /*!< [1..1] TIED */ + __IOM uint32_t PRED : 1; /*!< [2..2] PRED */ + __IOM uint32_t PFRROD : 1; /*!< [3..3] PFRROD */ + __IOM uint32_t FCDD : 1; /*!< [4..4] FCDD */ + __IOM uint32_t TCED : 1; /*!< [5..5] TCED */ + __IOM uint32_t TBCID : 1; /*!< [6..6] TBCID */ + __IOM uint32_t BFED : 1; /*!< [7..7] BFED */ + __IOM uint32_t FCED : 1; /*!< [8..8] FCED */ + __IOM uint32_t REOED : 1; /*!< [9..9] REOED */ + __IOM uint32_t RPOED : 1; /*!< [10..10] RPOED */ + __IOM uint32_t RPCRED : 1; /*!< [11..11] RPCRED */ + __IOM uint32_t CTLED0 : 1; /*!< [12..12] CTLED0 */ + __IOM uint32_t CTLED1 : 1; /*!< [13..13] CTLED1 */ + uint32_t : 6; + __IOM uint32_t PDED : 1; /*!< [20..20] PDED */ + __IOM uint32_t PNAED : 1; /*!< [21..21] PNAED */ + __IOM uint32_t FCMCED : 1; /*!< [22..22] FCMCED */ + __IOM uint32_t FFMED : 1; /*!< [23..23] FFMED */ + __IOM uint32_t CFCED : 1; /*!< [24..24] CFCED */ + __IOM uint32_t FRCED : 1; /*!< [25..25] FRCED */ + __IOM uint32_t RPOOMD : 1; /*!< [26..26] RPOOMD */ + __IOM uint32_t FFD : 1; /*!< [27..27] FFD */ + __IOM uint32_t FUED : 1; /*!< [28..28] FUED */ + __IOM uint32_t FOED : 1; /*!< [29..29] FOED */ + uint32_t : 2; + } MEID_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t MMIS0; /*!< (@ 0x00000210) MAC Monitoring Interrupt Status Register 0 (MMIS0) */ + + struct + { + __IOM uint32_t PLSCS : 1; /*!< [0..0] PLSCS */ + __IOM uint32_t PIDS : 1; /*!< [1..1] PIDS */ + __IOM uint32_t LVSS : 1; /*!< [2..2] LVSS */ + __IOM uint32_t LVFS : 1; /*!< [3..3] LVFS */ + __IOM uint32_t VFRS : 1; /*!< [4..4] VFRS */ + uint32_t : 1; + __IOM uint32_t ANDETS : 1; /*!< [6..6] ANDETS */ + uint32_t : 1; + __IOM uint32_t XLFDS : 1; /*!< [8..8] XLFDS */ + __IOM uint32_t XLFES : 1; /*!< [9..9] XLFES */ + __IOM uint32_t XLFSDS : 1; /*!< [10..10] XLFSDS */ + __IOM uint32_t XRFSDS : 1; /*!< [11..11] XRFSDS */ + __IOM uint32_t XLISDS : 1; /*!< [12..12] XLISDS */ + uint32_t : 19; + } MMIS0_b; + }; + + union + { + __IOM uint32_t MMIE0; /*!< (@ 0x00000214) MAC Monitoring Interrupt Enable Register 0 (MMIE0) */ + + struct + { + __IOM uint32_t PLSCE : 1; /*!< [0..0] PLSCE */ + __IOM uint32_t PIDE : 1; /*!< [1..1] PIDE */ + __IOM uint32_t LVSE : 1; /*!< [2..2] LVSE */ + __IOM uint32_t LVFE : 1; /*!< [3..3] LVFE */ + __IOM uint32_t VFRE : 1; /*!< [4..4] VFRE */ + uint32_t : 1; + __IOM uint32_t ANDETE : 1; /*!< [6..6] ANDETE */ + uint32_t : 1; + __IOM uint32_t XLFDE : 1; /*!< [8..8] XLFDE */ + __IOM uint32_t XLFEE : 1; /*!< [9..9] XLFEE */ + __IOM uint32_t XLFSDE : 1; /*!< [10..10] XLFSDE */ + __IOM uint32_t XRFSDE : 1; /*!< [11..11] XRFSDE */ + __IOM uint32_t XLISDE : 1; /*!< [12..12] XLISDE */ + uint32_t : 19; + } MMIE0_b; + }; + + union + { + __IOM uint32_t MMID0; /*!< (@ 0x00000218) MAC Monitoring Interrupt Disable Register 0 (MMID0) */ + + struct + { + __IOM uint32_t PLSCD : 1; /*!< [0..0] PLSCD */ + __IOM uint32_t PIDD : 1; /*!< [1..1] PIDD */ + __IOM uint32_t LVSD : 1; /*!< [2..2] LVSD */ + __IOM uint32_t LVFD : 1; /*!< [3..3] LVFD */ + __IOM uint32_t VFRD : 1; /*!< [4..4] VFRD */ + uint32_t : 1; + __IOM uint32_t ANDETD : 1; /*!< [6..6] ANDETD */ + uint32_t : 1; + __IOM uint32_t XLFDD : 1; /*!< [8..8] XLFDD */ + __IOM uint32_t XLFED : 1; /*!< [9..9] XLFED */ + __IOM uint32_t XLFSDD : 1; /*!< [10..10] XLFSDD */ + __IOM uint32_t XRFSDD : 1; /*!< [11..11] XRFSDD */ + __IOM uint32_t XLISDD : 1; /*!< [12..12] XLISDD */ + uint32_t : 19; + } MMID0_b; + }; + __IM uint32_t RESERVED13; + + union + { + __IOM uint32_t MMIS1; /*!< (@ 0x00000220) MAC Monitoring Interrupt Status Register 1 (MMIS1) */ + + struct + { + __IOM uint32_t PRACS : 1; /*!< [0..0] PRACS */ + __IOM uint32_t PWACS : 1; /*!< [1..1] PWACS */ + __IOM uint32_t PAACS : 1; /*!< [2..2] PAACS */ + __IOM uint32_t PPRACS : 1; /*!< [3..3] PPRACS */ + uint32_t : 28; + } MMIS1_b; + }; + + union + { + __IOM uint32_t MMIE1; /*!< (@ 0x00000224) MAC Monitoring Interrupt Enable Register 1 (MMIE1) */ + + struct + { + __IOM uint32_t PRACE : 1; /*!< [0..0] PRACE */ + __IOM uint32_t PWACE : 1; /*!< [1..1] PWACE */ + __IOM uint32_t PAACE : 1; /*!< [2..2] PAACE */ + __IOM uint32_t PPRACE : 1; /*!< [3..3] PPRACE */ + uint32_t : 28; + } MMIE1_b; + }; + + union + { + __IOM uint32_t MMID1; /*!< (@ 0x00000228) MAC Monitoring Interrupt Disable Register 1 (MMID1) */ + + struct + { + __IOM uint32_t PRACD : 1; /*!< [0..0] PRACD */ + __IOM uint32_t PWACD : 1; /*!< [1..1] PWACD */ + __IOM uint32_t PAACD : 1; /*!< [2..2] PAACD */ + __IOM uint32_t PPRACD : 1; /*!< [3..3] PPRACD */ + uint32_t : 28; + } MMID1_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t MMIS2; /*!< (@ 0x00000230) MAC Monitoring Interrupt Status Register 2 (MMIS2) */ + + struct + { + __IOM uint32_t MPDIS : 1; /*!< [0..0] MPDIS */ + __IOM uint32_t LPIAIS : 1; /*!< [1..1] LPIAIS */ + __IOM uint32_t LPIDIS : 1; /*!< [2..2] LPIDIS */ + uint32_t : 29; + } MMIS2_b; + }; + + union + { + __IOM uint32_t MMIE2; /*!< (@ 0x00000234) MAC Monitoring Interrupt Enable Register 2 (MMIE2) */ + + struct + { + __IOM uint32_t MPDIE : 1; /*!< [0..0] MPDIE */ + __IOM uint32_t LPIAIE : 1; /*!< [1..1] LPIAIE */ + __IOM uint32_t LPIDIE : 1; /*!< [2..2] LPIDIE */ + uint32_t : 29; + } MMIE2_b; + }; + + union + { + __IOM uint32_t MMID2; /*!< (@ 0x00000238) MAC Monitoring Interrupt Disable Register 2 (MMID2) */ + + struct + { + __IOM uint32_t MPDID : 1; /*!< [0..0] MPDID */ + __IOM uint32_t LPIAID : 1; /*!< [1..1] LPIAID */ + __IOM uint32_t LPIDID : 1; /*!< [2..2] LPIDID */ + uint32_t : 29; + } MMID2_b; + }; + __IM uint32_t RESERVED15[49]; + + union + { + __IOM uint32_t MMPFTCT; /*!< (@ 0x00000300) MAC Manual Pause Frame Transmit Counter Register + * (MMPFTCT) */ + + struct + { + __IOM uint32_t MPFTC : 16; /*!< [15..0] MPFTC */ + uint32_t : 16; + } MMPFTCT_b; + }; + + union + { + __IOM uint32_t MAPFTCT; /*!< (@ 0x00000304) MAC Automatic Pause Frame Transmit Counter Register + * (MAPFTCT) */ + + struct + { + __IOM uint32_t APFTC : 16; /*!< [15..0] APFTC */ + uint32_t : 16; + } MAPFTCT_b; + }; + + union + { + __IOM uint32_t MPFRCT; /*!< (@ 0x00000308) MAC Pause Frame Receive Counter Register (MPFRCT) */ + + struct + { + __IOM uint32_t PFRC : 16; /*!< [15..0] PFRC */ + uint32_t : 16; + } MPFRCT_b; + }; + + union + { + __IOM uint32_t MFCICT; /*!< (@ 0x0000030C) MAC False Carrier Indication Counter Register + * (MFCICT) */ + + struct + { + __IOM uint32_t FCIC : 16; /*!< [15..0] FCIC */ + uint32_t : 16; + } MFCICT_b; + }; + + union + { + __IOM uint32_t MEEECT; /*!< (@ 0x00000310) MAC Energy Efficient Ethernet Counter Register + * (MEEECT) */ + + struct + { + __IOM uint32_t EEERC : 16; /*!< [15..0] EEERC */ + uint32_t : 16; + } MEEECT_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t MMPCFTCT0; /*!< (@ 0x00000320) MAC Manual PFC Frame Transmit Counter Register + * (MMPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t MPCFCTC : 16; /*!< [15..0] MPCFCTC */ + uint32_t : 16; + } MMPCFTCT0_b; + }; + + union + { + __IOM uint32_t MMPCFTCT1; /*!< (@ 0x00000324) MAC Manual PFC Frame Transmit Counter Register + * (MMPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t MPCFCTC : 16; /*!< [15..0] MPCFCTC */ + uint32_t : 16; + } MMPCFTCT1_b; + }; + __IM uint32_t RESERVED17[2]; + + union + { + __IOM uint32_t MAPCFTCT0; /*!< (@ 0x00000330) MAC Automatic PFC Frame Transmit Counter Register + * (MAPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t APCFCTC : 16; /*!< [15..0] APCFCTC */ + uint32_t : 16; + } MAPCFTCT0_b; + }; + + union + { + __IOM uint32_t MAPCFTCT1; /*!< (@ 0x00000334) MAC Automatic PFC Frame Transmit Counter Register + * (MAPCFTCTt) (t = 0, 1) */ + + struct + { + __IOM uint32_t APCFCTC : 16; /*!< [15..0] APCFCTC */ + uint32_t : 16; + } MAPCFTCT1_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t MPCFRCT0; /*!< (@ 0x00000340) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT0_b; + }; + + union + { + __IOM uint32_t MPCFRCT1; /*!< (@ 0x00000344) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT1_b; + }; + + union + { + __IOM uint32_t MPCFRCT2; /*!< (@ 0x00000348) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT2_b; + }; + + union + { + __IOM uint32_t MPCFRCT3; /*!< (@ 0x0000034C) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT3_b; + }; + + union + { + __IOM uint32_t MPCFRCT4; /*!< (@ 0x00000350) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT4_b; + }; + + union + { + __IOM uint32_t MPCFRCT5; /*!< (@ 0x00000354) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT5_b; + }; + + union + { + __IOM uint32_t MPCFRCT6; /*!< (@ 0x00000358) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT6_b; + }; + + union + { + __IOM uint32_t MPCFRCT7; /*!< (@ 0x0000035C) Bit Symbol Bit Name Description R/W */ + + struct + { + __IOM uint32_t PCFCRC : 16; /*!< [15..0] PCFCRC */ + uint32_t : 16; + } MPCFRCT7_b; + }; + + union + { + __IOM uint32_t MROVFC; /*!< (@ 0x00000360) Receive Overflow Counter Register (MROVFC) */ + + struct + { + __IOM uint32_t ROVFC : 32; /*!< [31..0] ROVFC */ + } MROVFC_b; + }; + + union + { + __IOM uint32_t MRHCRCEC; /*!< (@ 0x00000364) Reception Header-CRC(PCH CRC) Error Counter Register + * (MRHCRCEC) */ + + struct + { + __IOM uint32_t RHCRCEC : 16; /*!< [15..0] RHCRCEC */ + uint32_t : 16; + } MRHCRCEC_b; + }; + __IM uint32_t RESERVED19[40]; + + union + { + __IOM uint32_t MRGFCE; /*!< (@ 0x00000408) RMAC Received Good Frame Counter E-Frames Register + * (MRGFCE) */ + + struct + { + __IOM uint32_t RGFNE : 32; /*!< [31..0] RGFNE */ + } MRGFCE_b; + }; + + union + { + __IOM uint32_t MRGFCP; /*!< (@ 0x0000040C) RMAC Received Good Frame Counter P-Frames Register + * (MRGFCP) */ + + struct + { + __IOM uint32_t RGFNP : 32; /*!< [31..0] RGFNP */ + } MRGFCP_b; + }; + + union + { + __IOM uint32_t MRBFC; /*!< (@ 0x00000410) Register (MRBFC) */ + + struct + { + __IOM uint32_t RBFN : 32; /*!< [31..0] RBFN */ + } MRBFC_b; + }; + + union + { + __IOM uint32_t MRMFC; /*!< (@ 0x00000414) RMAC Received Good Multicast Frame Counter Register + * (MRMFC) */ + + struct + { + __IOM uint32_t RMFN : 32; /*!< [31..0] RMFN */ + } MRMFC_b; + }; + + union + { + __IOM uint32_t MRUFC; /*!< (@ 0x00000418) RMAC Received Good Unicast Frame Counter Register + * (MRUFC) */ + + struct + { + __IOM uint32_t RUFN : 32; /*!< [31..0] RUFN */ + } MRUFC_b; + }; + + union + { + __IOM uint32_t MRPEFC; /*!< (@ 0x0000041C) Register (MRPEFC) */ + + struct + { + __IOM uint32_t RPEFN : 16; /*!< [15..0] RPEFN */ + uint32_t : 16; + } MRPEFC_b; + }; + + union + { + __IOM uint32_t MRNEFC; /*!< (@ 0x00000420) Register (MRNEFC) */ + + struct + { + __IOM uint32_t RNEFN : 16; /*!< [15..0] RNEFN */ + uint32_t : 16; + } MRNEFC_b; + }; + + union + { + __IOM uint32_t MRFMEFC; /*!< (@ 0x00000424) Register (MRFMEFC) */ + + struct + { + __IOM uint32_t RFMEFN : 32; /*!< [31..0] RFMEFN */ + } MRFMEFC_b; + }; + + union + { + __IOM uint32_t MRFFMEFC; /*!< (@ 0x00000428) Register (MRFFMEFC) */ + + struct + { + __IOM uint32_t RFFMEFN : 16; /*!< [15..0] RFFMEFN */ + uint32_t : 16; + } MRFFMEFC_b; + }; + + union + { + __IOM uint32_t MRCFCEFC; /*!< (@ 0x0000042C) Register (MRCFCEFC) */ + + struct + { + __IOM uint32_t RCFCEFN : 16; /*!< [15..0] RCFCEFN */ + uint32_t : 16; + } MRCFCEFC_b; + }; + + union + { + __IOM uint32_t MRFCEFC; /*!< (@ 0x00000430) Register (MRFCEFC) */ + + struct + { + __IOM uint32_t RFCEFN : 16; /*!< [15..0] RFCEFN */ + uint32_t : 16; + } MRFCEFC_b; + }; + + union + { + __IOM uint32_t MRRCFEFC; /*!< (@ 0x00000434) Register (MRRCFEFC) */ + + struct + { + __IOM uint32_t RRCFEFN : 16; /*!< [15..0] RRCFEFN */ + uint32_t : 16; + } MRRCFEFC_b; + }; + + union + { + __IOM uint32_t MRFC; /*!< (@ 0x00000438) Register (MRFC) */ + + struct + { + __IOM uint32_t RFN : 32; /*!< [31..0] RFN */ + } MRFC_b; + }; + + union + { + __IOM uint32_t MRGUEFC; /*!< (@ 0x0000043C) RMAC Received Good Undersize Error Frame Count + * Register (MRGUEFC) */ + + struct + { + __IOM uint32_t RUEFN : 32; /*!< [31..0] RUEFN */ + } MRGUEFC_b; + }; + + union + { + __IOM uint32_t MRBUEFC; /*!< (@ 0x00000440) RMAC Received bad Undersize Error Frame Count + * Register (MRBUEFC) */ + + struct + { + __IOM uint32_t RUEFN : 32; /*!< [31..0] RUEFN */ + } MRBUEFC_b; + }; + + union + { + __IOM uint32_t MRGOEFC; /*!< (@ 0x00000444) Register (MRGOEFC) */ + + struct + { + __IOM uint32_t RGOEFN : 32; /*!< [31..0] RGOEFN */ + } MRGOEFC_b; + }; + + union + { + __IOM uint32_t MRBOEFC; /*!< (@ 0x00000448) Register (MRBOEFC) */ + + struct + { + __IOM uint32_t RBOEFN : 32; /*!< [31..0] RBOEFN */ + } MRBOEFC_b; + }; + + union + { + __IOM uint32_t MRXBCEU; /*!< (@ 0x0000044C) Register (MRXBCEU) */ + + struct + { + __IOM uint32_t RBNEU : 32; /*!< [31..0] RBNEU */ + } MRXBCEU_b; + }; + + union + { + __IOM uint32_t MRXBCEL; /*!< (@ 0x00000450) Register (MRXBCEL) */ + + struct + { + __IOM uint32_t RBNEL : 32; /*!< [31..0] RBNEL */ + } MRXBCEL_b; + }; + + union + { + __IOM uint32_t MRXBCPU; /*!< (@ 0x00000454) Register (MRXBCPU) */ + + struct + { + __IOM uint32_t RBNPU : 32; /*!< [31..0] RBNPU */ + } MRXBCPU_b; + }; + + union + { + __IOM uint32_t MRXBCPL; /*!< (@ 0x00000458) Register (MRXBCPL) */ + + struct + { + __IOM uint32_t RBNPL : 32; /*!< [31..0] RBNPL */ + } MRXBCPL_b; + }; + __IM uint32_t RESERVED20[43]; + + union + { + __IOM uint32_t MTGFCE; /*!< (@ 0x00000508) RMAC Transmitted Good Frame Counter E-Frames + * Register (MTGFCE) */ + + struct + { + __IOM uint32_t TGFNE : 32; /*!< [31..0] TGFNE */ + } MTGFCE_b; + }; + + union + { + __IOM uint32_t MTGFCP; /*!< (@ 0x0000050C) RMAC Transmitted Good Frame Counter P-Frames + * Register (MTGFCP) */ + + struct + { + __IOM uint32_t TGFNP : 32; /*!< [31..0] TGFNP */ + } MTGFCP_b; + }; + + union + { + __IOM uint32_t MTBFC; /*!< (@ 0x00000510) Register (MTBFC) */ + + struct + { + __IOM uint32_t TBFN : 32; /*!< [31..0] TBFN */ + } MTBFC_b; + }; + + union + { + __IOM uint32_t MTMFC; /*!< (@ 0x00000514) RMAC Transmitted Multicast Frame Counter Register + * (MTMFC) */ + + struct + { + __IOM uint32_t TMFN : 32; /*!< [31..0] TMFN */ + } MTMFC_b; + }; + + union + { + __IOM uint32_t MTUFC; /*!< (@ 0x00000518) Register (MTUFC) */ + + struct + { + __IOM uint32_t TUFN : 32; /*!< [31..0] TUFN */ + } MTUFC_b; + }; + + union + { + __IOM uint32_t MTEFC; /*!< (@ 0x0000051C) Register (MTEFC) */ + + struct + { + __IOM uint32_t TEFN : 16; /*!< [15..0] TEFN */ + uint32_t : 16; + } MTEFC_b; + }; + + union + { + __IOM uint32_t MTXBCEU; /*!< (@ 0x00000520) Register (MTXBCEU) */ + + struct + { + __IOM uint32_t TBNEU : 32; /*!< [31..0] TBNEU */ + } MTXBCEU_b; + }; + + union + { + __IOM uint32_t MTXBCEL; /*!< (@ 0x00000524) Register (MTXBCEL) */ + + struct + { + __IOM uint32_t TBNEL : 32; /*!< [31..0] TBNEL */ + } MTXBCEL_b; + }; + + union + { + __IOM uint32_t MTXBCPU; /*!< (@ 0x00000528) RMAC Transmitted Byte Counter P-Frames Upper + * Side Register (MTXBCPU) */ + + struct + { + __IOM uint32_t TBNPU : 32; /*!< [31..0] TBNPU */ + } MTXBCPU_b; + }; + + union + { + __IOM uint32_t MTXBCPL; /*!< (@ 0x0000052C) RMAC Transmitted Byte Counter P-Frames Lower + * Side Register (MTXBCPL) */ + + struct + { + __IOM uint32_t TBNPL : 32; /*!< [31..0] TBNPL */ + } MTXBCPL_b; + }; +} R_RMAC0_Type; /*!< Size = 1328 (0x530) */ + +/* =========================================================================================================================== */ +/* ================ R_TCM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Tightly Coupled Memory (R_TCM) + */ + +typedef struct /*!< (@ 0x4001C800) R_TCM Structure */ +{ + union + { + __IOM uint16_t TCMPRCR_S; /*!< (@ 0x00000000) TCM Protection Control Register for Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __IOM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } TCMPRCR_S_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TCMPRCR_NS; /*!< (@ 0x00000004) TCM Protection Control Register for Non-Secure */ + + struct + { + __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */ + uint16_t : 7; + __IOM uint16_t KW : 8; /*!< [15..8] Write Key Code */ + } TCMPRCR_NS_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint8_t TCMCRC; /*!< (@ 0x00000010) TCM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } TCMCRC_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t TCMCRS; /*!< (@ 0x00000014) TCM Control Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after ECC error detection */ + uint8_t : 1; + __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */ + __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */ + uint8_t : 2; + __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */ + } TCMCRS_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[10]; + + union + { + __IOM uint16_t TCMESR; /*!< (@ 0x00000040) TCM Error Status Register */ + + struct + { + __IOM uint16_t ERRC0 : 1; /*!< [0..0] C-TCM 1-bit ECC Error Status */ + __IOM uint16_t ERRC1 : 1; /*!< [1..1] C-TCM 2-bit ECC Error Status */ + __IOM uint16_t ERRS0 : 1; /*!< [2..2] S-TCM 1-bit ECC Error Status */ + __IOM uint16_t ERRS1 : 1; /*!< [3..3] S-TCM 2-bit ECC Error Status */ + uint16_t : 12; + } TCMESR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t TCMESCLR; /*!< (@ 0x00000048) TCM Error Status Clear Register */ + + struct + { + __IOM uint16_t CLRC0 : 1; /*!< [0..0] TCM 1-bit ECC Error Status Clear */ + __IOM uint16_t CLRC1 : 1; /*!< [1..1] TCM 2-bit ECC Error Status Clear */ + __IOM uint16_t CLRS0 : 1; /*!< [2..2] S-TCM 1-bit ECC Error Status Clear */ + __IOM uint16_t CLRS1 : 1; /*!< [3..3] S-TCM 2-bit ECC Error Status Clear */ + uint16_t : 12; + } TCMESCLR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t TCMEARC0; /*!< (@ 0x00000050) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARC0_b; + }; + + union + { + __IOM uint32_t TCMEARC1; /*!< (@ 0x00000054) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARC1_b; + }; + + union + { + __IOM uint32_t TCMEARS0; /*!< (@ 0x00000058) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARS0_b; + }; + + union + { + __IOM uint32_t TCMEARS1; /*!< (@ 0x0000005C) TCM Error Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t EAR : 16; /*!< [17..2] When an SRAM error occurs, it stores an error address */ + uint32_t : 14; + } TCMEARS1_b; + }; +} R_TCM_Type; /*!< Size = 96 (0x60) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #if defined(_RA_TZ_NONSECURE) + #define BASE_NS_OFFSET (BSP_FEATURE_TZ_NS_OFFSET) + #else + #define BASE_NS_OFFSET 0U + #endif + + #define R_ACMPHS0_BASE (0x40236000UL + BASE_NS_OFFSET) + #define R_ACMPHS1_BASE (0x40236100UL + BASE_NS_OFFSET) + #define R_ACMPHS2_BASE (0x40236200UL + BASE_NS_OFFSET) + #define R_ACMPHS3_BASE (0x40236300UL + BASE_NS_OFFSET) + #define R_ACMPHS4_BASE (0x40236400UL + BASE_NS_OFFSET) + #define R_ACMPHS5_BASE (0x40236500UL + BASE_NS_OFFSET) + #define R_PSCU_BASE (0x40204000UL + BASE_NS_OFFSET) + #define R_BUS_BASE (0x40003000UL + BASE_NS_OFFSET) + #define R_CAC_BASE (0x40202400UL + BASE_NS_OFFSET) + #define R_CANFD_BASE (0x40380000UL + BASE_NS_OFFSET) + #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET) + #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET) + #define R_DAC_B0_BASE (0x40233000UL + BASE_NS_OFFSET) + #define R_DAC_B1_BASE (0x40233100UL + BASE_NS_OFFSET) + #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET) + #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET) + #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET) + #define R_DMAC1_BASE (0x4000A040UL + BASE_NS_OFFSET) + #define R_DMAC2_BASE (0x4000A080UL + BASE_NS_OFFSET) + #define R_DMAC3_BASE (0x4000A0C0UL + BASE_NS_OFFSET) + #define R_DMAC4_BASE (0x4000A100UL + BASE_NS_OFFSET) + #define R_DMAC5_BASE (0x4000A140UL + BASE_NS_OFFSET) + #define R_DMAC6_BASE (0x4000A180UL + BASE_NS_OFFSET) + #define R_DMAC7_BASE (0x4000A1C0UL + BASE_NS_OFFSET) + #define R_DOC_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_DRW_BASE (0x40444000UL + BASE_NS_OFFSET) + #define R_DTC_BASE (0x4000AC00UL + BASE_NS_OFFSET) + #define R_ELC_BASE (0x40201000UL + BASE_NS_OFFSET) + #define R_ETHERC_EDMAC_BASE (0x40354000UL + BASE_NS_OFFSET) + #define R_GLCDC_BASE (0x40342000UL + BASE_NS_OFFSET) + #define R_GPT0_BASE (0x40322000UL + BASE_NS_OFFSET) + #define R_GPT1_BASE (0x40322100UL + BASE_NS_OFFSET) + #define R_GPT2_BASE (0x40322200UL + BASE_NS_OFFSET) + #define R_GPT3_BASE (0x40322300UL + BASE_NS_OFFSET) + #define R_GPT4_BASE (0x40322400UL + BASE_NS_OFFSET) + #define R_GPT5_BASE (0x40322500UL + BASE_NS_OFFSET) + #define R_GPT6_BASE (0x40322600UL + BASE_NS_OFFSET) + #define R_GPT7_BASE (0x40322700UL + BASE_NS_OFFSET) + #define R_GPT8_BASE (0x40322800UL + BASE_NS_OFFSET) + #define R_GPT9_BASE (0x40322900UL + BASE_NS_OFFSET) + #define R_GPT10_BASE (0x40322A00UL + BASE_NS_OFFSET) + #define R_GPT11_BASE (0x40322B00UL + BASE_NS_OFFSET) + #define R_GPT12_BASE (0x40322C00UL + BASE_NS_OFFSET) + #define R_GPT13_BASE (0x40322D00UL + BASE_NS_OFFSET) + #define R_GPT_GTCLK_BASE (0x40323F10UL + BASE_NS_OFFSET) + #define R_GPT_ODC_BASE (0x40324000UL + BASE_NS_OFFSET) + #define R_GPT_OPS_BASE (0x40323F00UL + BASE_NS_OFFSET) + #define R_GPT_POEG0_BASE (0x40212000UL + BASE_NS_OFFSET) + #define R_GPT_POEG1_BASE (0x40212100UL + BASE_NS_OFFSET) + #define R_GPT_POEG2_BASE (0x40212200UL + BASE_NS_OFFSET) + #define R_GPT_POEG3_BASE (0x40212300UL + BASE_NS_OFFSET) + #define R_ICU_BASE (0x40006000UL + BASE_NS_OFFSET) + #define R_IIC0_BASE (0x4025E000UL + BASE_NS_OFFSET) + #define R_IIC1_BASE (0x4025E100UL + BASE_NS_OFFSET) + #define R_IIC2_BASE (0x4025E200UL + BASE_NS_OFFSET) + #define R_IWDT_BASE (0x40202200UL + BASE_NS_OFFSET) + #define R_I3C0_BASE (0x4035F000UL + BASE_NS_OFFSET) + #define R_I3C1_BASE (0x4035F100UL + BASE_NS_OFFSET) + #define R_MPU_MMPU_BASE (0x40000000UL + BASE_NS_OFFSET) + #define R_MPU_SPMON_BASE (0x40000D00UL + BASE_NS_OFFSET) + #define R_MSTP_BASE (0x40203000UL + BASE_NS_OFFSET) + #define R_PORT0_BASE (0x40400000UL + BASE_NS_OFFSET) + #define R_PORT1_BASE (0x40400020UL + BASE_NS_OFFSET) + #define R_PORT2_BASE (0x40400040UL + BASE_NS_OFFSET) + #define R_PORT3_BASE (0x40400060UL + BASE_NS_OFFSET) + #define R_PORT4_BASE (0x40400080UL + BASE_NS_OFFSET) + #define R_PORT5_BASE (0x404000A0UL + BASE_NS_OFFSET) + #define R_PORT6_BASE (0x404000C0UL + BASE_NS_OFFSET) + #define R_PORT7_BASE (0x404000E0UL + BASE_NS_OFFSET) + #define R_PORT8_BASE (0x40400100UL + BASE_NS_OFFSET) + #define R_PORT9_BASE (0x40400120UL + BASE_NS_OFFSET) + #define R_PORT10_BASE (0x40400140UL + BASE_NS_OFFSET) + #define R_PORT11_BASE (0x40400160UL + BASE_NS_OFFSET) + #define R_PORT12_BASE (0x40400180UL + BASE_NS_OFFSET) + #define R_PORT13_BASE (0x404001A0UL + BASE_NS_OFFSET) + #define R_PORT14_BASE (0x404001C0UL + BASE_NS_OFFSET) + #define R_PFS_BASE (0x40400800UL + BASE_NS_OFFSET) + #define R_PMISC_BASE (0x40400D00UL + BASE_NS_OFFSET) + #define R_RTC_BASE (0x40202000UL + BASE_NS_OFFSET) + #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_SCI9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SDHI0_BASE (0x40252000UL + BASE_NS_OFFSET) + #define R_SDHI1_BASE (0x40252400UL + BASE_NS_OFFSET) + #define R_SPI0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_SPI2_BASE (0x40072200UL + BASE_NS_OFFSET) + #define R_SRAM_BASE (0x40002000UL + BASE_NS_OFFSET) + #define R_SSI0_BASE (0x4025D000UL + BASE_NS_OFFSET) + #define R_SSI1_BASE (0x4025D100UL + BASE_NS_OFFSET) + #define R_SYSTEM_BASE (0x4001E000UL + BASE_NS_OFFSET) + #define R_TSN_CAL_BASE (0x02C1EDA0UL + BASE_NS_OFFSET) + #define R_TSN_CTRL_BASE (0x40235000UL + BASE_NS_OFFSET) + #define R_USB_FS0_BASE (0x40250000UL + BASE_NS_OFFSET) + #define R_VIN_BASE (0x40347400UL + BASE_NS_OFFSET) + #define R_WDT_BASE (0x40202600UL + BASE_NS_OFFSET) + #define R_CACHE_BASE (0x4001C000UL + BASE_NS_OFFSET) + #define R_CPSCU_BASE (0x40008000UL + BASE_NS_OFFSET) + #define R_ADC_B0_BASE (0x40338000UL + BASE_NS_OFFSET) + #define R_DOC_B_BASE (0x40311000UL + BASE_NS_OFFSET) + #define R_SCI_B0_BASE (0x40358000UL + BASE_NS_OFFSET) + #define R_SCI_B1_BASE (0x40358100UL + BASE_NS_OFFSET) + #define R_SCI_B2_BASE (0x40358200UL + BASE_NS_OFFSET) + #define R_SCI_B3_BASE (0x40358300UL + BASE_NS_OFFSET) + #define R_SCI_B4_BASE (0x40358400UL + BASE_NS_OFFSET) + #define R_SCI_B9_BASE (0x40358900UL + BASE_NS_OFFSET) + #define R_SPI_B0_BASE (0x4035C000UL + BASE_NS_OFFSET) + #define R_SPI_B1_BASE (0x4035C100UL + BASE_NS_OFFSET) + #define R_USB_HS0_BASE (0x40351000UL + BASE_NS_OFFSET) + #define R_XSPI0_BASE (0x40268000UL + BASE_NS_OFFSET) + #define R_XSPI1_BASE (0x40268400UL + BASE_NS_OFFSET) + #define R_MIPI_PHY_BASE (0x40346C00UL + BASE_NS_OFFSET) + #define R_MIPI_CSI_BASE (0x40347000UL + BASE_NS_OFFSET) + #define R_CEU_BASE (0x40348000UL + BASE_NS_OFFSET) + #define R_ULPT0_BASE (0x40220000UL + BASE_NS_OFFSET) + #define R_ULPT1_BASE (0x40220100UL + BASE_NS_OFFSET) + #define R_DEBUG_OCD_BASE (0x40011000UL + BASE_NS_OFFSET) + #define R_DOTF_BASE (0x40268800UL + BASE_NS_OFFSET) + #define R_AGTX0_BASE (0x40221000UL + BASE_NS_OFFSET) + #define R_AGTX1_BASE (0x40221100UL + BASE_NS_OFFSET) + #define R_AGTX2_BASE (0x40221200UL + BASE_NS_OFFSET) + #define R_AGTX3_BASE (0x40221300UL + BASE_NS_OFFSET) + #define R_AGTX4_BASE (0x40221400UL + BASE_NS_OFFSET) + #define R_AGTX5_BASE (0x40221500UL + BASE_NS_OFFSET) + #define R_AGTX6_BASE (0x40221600UL + BASE_NS_OFFSET) + #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET) + #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET) + #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET) + #define R_COMA_BASE (0x403C9000UL + BASE_NS_OFFSET) + #define R_CPU_CTRL_BASE (0x4000F000UL + BASE_NS_OFFSET) + #define R_DOTF1_BASE (0x40268900UL + BASE_NS_OFFSET) + #define R_ECCMB0_BASE (0x4036F200UL + BASE_NS_OFFSET) + #define R_ECCMB1_BASE (0x4036F300UL + BASE_NS_OFFSET) + #define R_ESWM_BASE (0x403C8000UL + BASE_NS_OFFSET) + #define R_ETHA0_BASE (0x403CA000UL + BASE_NS_OFFSET) + #define R_ETHA1_BASE (0x403CC000UL + BASE_NS_OFFSET) + #define R_GPTP_BASE (0x403E0000UL + BASE_NS_OFFSET) + #define R_GWCA0_BASE (0x403CE000UL + BASE_NS_OFFSET) + #define R_IPC_BASE (0x40020000UL + BASE_NS_OFFSET) + #define R_MFWD_BASE (0x403C0000UL + BASE_NS_OFFSET) + #define R_MIPI_DSI_BASE (0x40346000UL + BASE_NS_OFFSET) + #define R_MRMS_BASE (0x4013C000UL + BASE_NS_OFFSET) + #define R_NPU_BASE (0x40140000UL + BASE_NS_OFFSET) + #define R_PDM_BASE (0x40256000UL + BASE_NS_OFFSET) + #define R_RMAC0_BASE (0x403CB000UL + BASE_NS_OFFSET) + #define R_RMAC1_BASE (0x403CD000UL + BASE_NS_OFFSET) + #define R_SCI_B5_BASE (0x40358500UL + BASE_NS_OFFSET) + #define R_SCI_B6_BASE (0x40358600UL + BASE_NS_OFFSET) + #define R_SCI_B7_BASE (0x40358700UL + BASE_NS_OFFSET) + #define R_SCI_B8_BASE (0x40358800UL + BASE_NS_OFFSET) + #define R_TCM_BASE (0x4001C800UL + BASE_NS_OFFSET) + #define R_WDT1_BASE (0x40202700UL + BASE_NS_OFFSET) + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC_B0 ((R_DAC_B0_Type *) R_DAC_B0_BASE) + #define R_DAC_B1 ((R_DAC_B0_Type *) R_DAC_B1_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_VIN ((R_VIN_Type *) R_VIN_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_ADC_B ((R_ADC_B0_Type *) R_ADC_B0_BASE) + #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE) + #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE) + #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE) + #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE) + #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE) + #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE) + #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE) + #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) + #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_MIPI_PHY ((R_MIPI_PHY_Type *) R_MIPI_PHY_BASE) + #define R_MIPI_CSI ((R_MIPI_CSI_Type *) R_MIPI_CSI_BASE) + #define R_CEU ((R_CEU_Type *) R_CEU_BASE) + #define R_ULPT0 ((R_ULPT0_Type *) R_ULPT0_BASE) + #define R_ULPT1 ((R_ULPT0_Type *) R_ULPT1_BASE) + #define R_DEBUG_OCD ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE) + #define R_DOTF ((R_DOTF_Type *) R_DOTF_BASE) + #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE) + #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE) + #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE) + #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE) + #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE) + #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE) + #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE) + #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE) + #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE) + #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE) + #define R_COMA ((R_COMA_Type *) R_COMA_BASE) + #define R_CPU_CTRL ((R_CPU_CTRL_Type *) R_CPU_CTRL_BASE) + #define R_DOTF1 ((R_DOTF_Type *) R_DOTF1_BASE) + #define R_ECCMB0 ((R_ECCMB0_Type *) R_ECCMB0_BASE) + #define R_ECCMB1 ((R_ECCMB0_Type *) R_ECCMB1_BASE) + #define R_ESWM ((R_ESWM_Type *) R_ESWM_BASE) + #define R_ETHA0 ((R_ETHA0_Type *) R_ETHA0_BASE) + #define R_ETHA1 ((R_ETHA0_Type *) R_ETHA1_BASE) + #define R_GPTP ((R_GPTP_Type *) R_GPTP_BASE) + #define R_GWCA0 ((R_GWCA0_Type *) R_GWCA0_BASE) + #define R_IPC ((R_IPC_Type *) R_IPC_BASE) + #define R_MFWD ((R_MFWD_Type *) R_MFWD_BASE) + #define R_MIPI_DSI ((R_MIPI_DSI_Type *) R_MIPI_DSI_BASE) + #define R_MRMS ((R_MRMS_Type *) R_MRMS_BASE) + #define R_NPU ((R_NPU_Type *) R_NPU_BASE) + #define R_PDM ((R_PDM_Type *) R_PDM_BASE) + #define R_RMAC0 ((R_RMAC0_Type *) R_RMAC0_BASE) + #define R_RMAC1 ((R_RMAC0_Type *) R_RMAC1_BASE) + #define R_SCI_B5 ((R_SCI_B0_Type *) R_SCI_B5_BASE) + #define R_SCI_B6 ((R_SCI_B0_Type *) R_SCI_B6_BASE) + #define R_SCI_B7 ((R_SCI_B0_Type *) R_SCI_B7_BASE) + #define R_SCI_B8 ((R_SCI_B0_Type *) R_SCI_B8_BASE) + #define R_TCM ((R_TCM_Type *) R_TCM_BASE) + #define R_WDT1 ((R_WDT_Type *) R_WDT1_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERRb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */ + #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */ + #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= IRQEN ========================================================= */ + #define R_BUS_BUSERRb_IRQEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_BUS_BUSERRb_IRQEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DMACDTCERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FLBI ========================================================== */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== MRE0BI ========================================================= */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S2BI ========================================================== */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= S3BI ========================================================== */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== STBYSBI ======================================================== */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ECBI ========================================================== */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI0BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================== SPI1BI ========================================================= */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0SAHBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1TCMBI ======================================================= */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PBBI ========================================================== */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PABI ========================================================== */ + #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PIBI ========================================================== */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ========================================================= PSBI ========================================================== */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSSABT1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FHBI ========================================================== */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ======================================================== MRC0BI ========================================================= */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S0BI ========================================================== */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ========================================================= S1BI ========================================================== */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ BMSAERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */ + #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RW =========================================================== */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */ + #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ OAD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== BUSOAD ========================================================= */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */ + #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */ + #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */ + #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSOADPT ======================================================== */ + #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== MSAOAD ========================================================= */ + #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= MSAPT ========================================================= */ + #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ MBWERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ + #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */ + #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x3ffUL) /*!< ELS (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ BG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= PERI ========================================================== */ + #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */ + #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */ + #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SYNC ========================================================== */ + #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */ + #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */ + #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */ +/* ========================================================= VSIZE ========================================================= */ + #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= HSIZE ========================================================= */ + #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== BGC ========================================================== */ + #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== VEN ========================================================== */ + #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */ + #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FLMRD ========================================================= */ + #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */ + #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */ +/* ========================================================= FLM1 ========================================================== */ + #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */ + #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */ +/* ========================================================= FLM2 ========================================================== */ + #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ + #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLM3 ========================================================== */ + #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */ + #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM5 ========================================================== */ + #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */ + #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */ + #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM6 ========================================================== */ + #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */ + #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */ +/* ========================================================== AB1 ========================================================== */ + #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */ + #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */ + #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== AB2 ========================================================== */ + #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */ + #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */ + #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB3 ========================================================== */ + #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */ + #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */ + #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB4 ========================================================== */ + #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */ + #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */ + #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB5 ========================================================== */ + #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */ + #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */ + #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB6 ========================================================== */ + #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */ + #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */ + #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */ + #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */ +/* ========================================================== AB7 ========================================================== */ + #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */ + #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */ + #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */ +/* ========================================================== AB8 ========================================================== */ + #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */ + #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */ + #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */ + #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */ +/* ========================================================== AB9 ========================================================== */ + #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */ + #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */ + #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */ + #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */ + #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */ +/* ========================================================= BASE ========================================================== */ + #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */ + #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */ + #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */ +/* ======================================================== CLUTINT ======================================================== */ + #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */ + #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */ + #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */ + #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */ + #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LATCH ========================================================= */ + #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ======================================================== GAM_SW ========================================================= */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */ +/* ========================================================== LUT ========================================================== */ + #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */ +/* ========================================================= AREA ========================================================== */ + #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ OUT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VLATCH ========================================================= */ + #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */ + #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */ + #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */ + #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */ + #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */ + #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */ + #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +/* ======================================================== BRIGHT1 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BRIGHT2 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CONTRAST ======================================================== */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */ +/* ========================================================= PDTHA ========================================================= */ + #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */ + #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */ + #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */ + #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */ + #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */ + #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */ + #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */ +/* ======================================================= CLKPHASE ======================================================== */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TCON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TIM ========================================================== */ + #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */ + #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA1 ========================================================= */ + #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVB1 ========================================================= */ + #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA2 ========================================================= */ + #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STVB2 ========================================================= */ + #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHA1 ========================================================= */ + #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHB1 ========================================================= */ + #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHA2 ========================================================= */ + #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHB2 ========================================================= */ + #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================== DE =========================================================== */ + #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */ + #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSCNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DTCTEN ========================================================= */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCLR ========================================================= */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= STMON ========================================================= */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */ +/* ======================================================= PANEL_CLK ======================================================= */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x7fUL) /*!< DLY (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ REGION ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AC =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */ + #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */ + #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */ + #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =========================================================== S =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */ +/* =========================================================== E =========================================================== */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */ + #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ GROUP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ENPT ========================================================== */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== RPT ========================================================== */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ======================================================== RPT_SEC ======================================================== */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */ + #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CMCFGCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Pos (4UL) /*!< WPBSTMD (Bit 4) */ + #define R_XSPI0_CMCFGCS_CMCFG0_WPBSTMD_Msk (0x10UL) /*!< WPBSTMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Pos (5UL) /*!< ARYAMD (Bit 5) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ARYAMD_Msk (0x20UL) /*!< ARYAMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CMCFGCS_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CMCFGCS_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ CDBUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_CDBUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CDBUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_CDBUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CDBUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_CDBUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_CDBUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDBUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_CDBUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_CDBUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_CDBUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_CDBUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_CDBUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_CDBUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CCCTLCS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CCCTLCS_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CCCTLCS_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CCCTLCS_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ===================================================== AGTIOSEL_ALT ====================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ AGT16 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ AGT32 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CABPPPFLC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== LEVEL0 ========================================================= */ + #define R_COMA_CABPPPFLC_LEVEL0_PPDL_Pos (0UL) /*!< PPDL (Bit 0) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPDL_Msk (0x3ffUL) /*!< PPDL (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPAL_Pos (16UL) /*!< PPAL (Bit 16) */ + #define R_COMA_CABPPPFLC_LEVEL0_PPAL_Msk (0x3ff0000UL) /*!< PPAL (Bitfield-Mask: 0x3ff) */ +/* ======================================================== LEVEL1 ========================================================= */ + #define R_COMA_CABPPPFLC_LEVEL1_PPDL_Pos (0UL) /*!< PPDL (Bit 0) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPDL_Msk (0x3ffUL) /*!< PPDL (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPAL_Pos (16UL) /*!< PPAL (Bit 16) */ + #define R_COMA_CABPPPFLC_LEVEL1_PPAL_Msk (0x3ff0000UL) /*!< PPAL (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ IPCNMI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== STA ========================================================== */ + #define R_IPC_IPCNMI_STA_NMI_Pos (0UL) /*!< NMI (Bit 0) */ + #define R_IPC_IPCNMI_STA_NMI_Msk (0x1UL) /*!< NMI (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_IPC_IPCNMI_SET_SET_Pos (0UL) /*!< SET (Bit 0) */ + #define R_IPC_IPCNMI_SET_SET_Msk (0x1UL) /*!< SET (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ + #define R_IPC_IPCNMI_CLR_CLR_Pos (0UL) /*!< CLR (Bit 0) */ + #define R_IPC_IPCNMI_CLR_CLR_Msk (0x1UL) /*!< CLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== STA ========================================================== */ + #define R_IPC_IPC_CH_STA_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ + #define R_IPC_IPC_CH_STA_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_RDY_Pos (16UL) /*!< RDY (Bit 16) */ + #define R_IPC_IPC_CH_STA_RDY_Msk (0x10000UL) /*!< RDY (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_FULL_Pos (17UL) /*!< FULL (Bit 17) */ + #define R_IPC_IPC_CH_STA_FULL_Msk (0x20000UL) /*!< FULL (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_RERR_Pos (24UL) /*!< RERR (Bit 24) */ + #define R_IPC_IPC_CH_STA_RERR_Msk (0x1000000UL) /*!< RERR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_STA_FERR_Pos (25UL) /*!< FERR (Bit 25) */ + #define R_IPC_IPC_CH_STA_FERR_Msk (0x2000000UL) /*!< FERR (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_IPC_IPC_CH_SET_SET_Pos (0UL) /*!< SET (Bit 0) */ + #define R_IPC_IPC_CH_SET_SET_Msk (0x1UL) /*!< SET (Bitfield-Mask: 0x01) */ +/* ========================================================== TXD ========================================================== */ + #define R_IPC_IPC_CH_TXD_TXD_Pos (0UL) /*!< TXD (Bit 0) */ + #define R_IPC_IPC_CH_TXD_TXD_Msk (0xffffffffUL) /*!< TXD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== RXD ========================================================== */ + #define R_IPC_IPC_CH_RXD_RXD_Pos (0UL) /*!< RXD (Bit 0) */ + #define R_IPC_IPC_CH_RXD_RXD_Msk (0xffffffffUL) /*!< RXD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== CLR ========================================================== */ + #define R_IPC_IPC_CH_CLR_CLR_Pos (0UL) /*!< CLR (Bit 0) */ + #define R_IPC_IPC_CH_CLR_CLR_Msk (0x1UL) /*!< CLR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_RST_Pos (16UL) /*!< RST (Bit 16) */ + #define R_IPC_IPC_CH_CLR_RST_Msk (0x10000UL) /*!< RST (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_RCLR_Pos (24UL) /*!< RCLR (Bit 24) */ + #define R_IPC_IPC_CH_CLR_RCLR_Msk (0x1000000UL) /*!< RCLR (Bitfield-Mask: 0x01) */ + #define R_IPC_IPC_CH_CLR_FCLR_Pos (25UL) /*!< FCLR (Bit 25) */ + #define R_IPC_IPC_CH_CLR_FCLR_Msk (0x2000000UL) /*!< FCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ IPC ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PDSTRTR ======================================================== */ + #define R_PDM_CH_PDSTRTR_STRTRG_Pos (0UL) /*!< STRTRG (Bit 0) */ + #define R_PDM_CH_PDSTRTR_STRTRG_Msk (0x1UL) /*!< STRTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== PDSTPTR ======================================================== */ + #define R_PDM_CH_PDSTPTR_STPTRG_Pos (0UL) /*!< STPTRG (Bit 0) */ + #define R_PDM_CH_PDSTPTR_STPTRG_Msk (0x1UL) /*!< STPTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCHGTR ======================================================== */ + #define R_PDM_CH_PDCHGTR_CHGTRG_Pos (0UL) /*!< CHGTRG (Bit 0) */ + #define R_PDM_CH_PDCHGTR_CHGTRG_Msk (0x1UL) /*!< CHGTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= PDICR ========================================================= */ + #define R_PDM_CH_PDICR_ISDE_Pos (1UL) /*!< ISDE (Bit 1) */ + #define R_PDM_CH_PDICR_ISDE_Msk (0x2UL) /*!< ISDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDICR_IDRE_Pos (2UL) /*!< IDRE (Bit 2) */ + #define R_PDM_CH_PDICR_IDRE_Msk (0x4UL) /*!< IDRE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDICR_IEDE_Pos (16UL) /*!< IEDE (Bit 16) */ + #define R_PDM_CH_PDICR_IEDE_Msk (0x10000UL) /*!< IEDE (Bitfield-Mask: 0x01) */ +/* ======================================================== PDSDCR ========================================================= */ + #define R_PDM_CH_PDSDCR_SDE_Pos (1UL) /*!< SDE (Bit 1) */ + #define R_PDM_CH_PDSDCR_SDE_Msk (0x2UL) /*!< SDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_SCDE_Pos (16UL) /*!< SCDE (Bit 16) */ + #define R_PDM_CH_PDSDCR_SCDE_Msk (0x10000UL) /*!< SCDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_OVLDE_Pos (17UL) /*!< OVLDE (Bit 17) */ + #define R_PDM_CH_PDSDCR_OVLDE_Msk (0x20000UL) /*!< OVLDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_OVUDE_Pos (18UL) /*!< OVUDE (Bit 18) */ + #define R_PDM_CH_PDSDCR_OVUDE_Msk (0x40000UL) /*!< OVUDE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSDCR_BFOWDE_Pos (27UL) /*!< BFOWDE (Bit 27) */ + #define R_PDM_CH_PDSDCR_BFOWDE_Msk (0x8000000UL) /*!< BFOWDE (Bitfield-Mask: 0x01) */ +/* ========================================================= PDSR ========================================================== */ + #define R_PDM_CH_PDSR_STATE_Pos (0UL) /*!< STATE (Bit 0) */ + #define R_PDM_CH_PDSR_STATE_Msk (0x1UL) /*!< STATE (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_SDF_Pos (1UL) /*!< SDF (Bit 1) */ + #define R_PDM_CH_PDSR_SDF_Msk (0x2UL) /*!< SDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_DRF_Pos (2UL) /*!< DRF (Bit 2) */ + #define R_PDM_CH_PDSR_DRF_Msk (0x4UL) /*!< DRF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_SCDF_Pos (16UL) /*!< SCDF (Bit 16) */ + #define R_PDM_CH_PDSR_SCDF_Msk (0x10000UL) /*!< SCDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_OVLDF_Pos (17UL) /*!< OVLDF (Bit 17) */ + #define R_PDM_CH_PDSR_OVLDF_Msk (0x20000UL) /*!< OVLDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_OVUDF_Pos (18UL) /*!< OVUDF (Bit 18) */ + #define R_PDM_CH_PDSR_OVUDF_Msk (0x40000UL) /*!< OVUDF (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSR_BFOWDF_Pos (27UL) /*!< BFOWDF (Bit 27) */ + #define R_PDM_CH_PDSR_BFOWDF_Msk (0x8000000UL) /*!< BFOWDF (Bitfield-Mask: 0x01) */ +/* ========================================================= PDSCR ========================================================= */ + #define R_PDM_CH_PDSCR_SDFC_Pos (1UL) /*!< SDFC (Bit 1) */ + #define R_PDM_CH_PDSCR_SDFC_Msk (0x2UL) /*!< SDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_SCDFC_Pos (16UL) /*!< SCDFC (Bit 16) */ + #define R_PDM_CH_PDSCR_SCDFC_Msk (0x10000UL) /*!< SCDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_OVLDFC_Pos (17UL) /*!< OVLDFC (Bit 17) */ + #define R_PDM_CH_PDSCR_OVLDFC_Msk (0x20000UL) /*!< OVLDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_OVUDFC_Pos (18UL) /*!< OVUDFC (Bit 18) */ + #define R_PDM_CH_PDSCR_OVUDFC_Msk (0x40000UL) /*!< OVUDFC (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDSCR_BFOWDFC_Pos (27UL) /*!< BFOWDFC (Bit 27) */ + #define R_PDM_CH_PDSCR_BFOWDFC_Msk (0x8000000UL) /*!< BFOWDFC (Bitfield-Mask: 0x01) */ +/* ======================================================== PDMDSR ========================================================= */ + #define R_PDM_CH_PDMDSR_INPSEL_Pos (0UL) /*!< INPSEL (Bit 0) */ + #define R_PDM_CH_PDMDSR_INPSEL_Msk (0x1UL) /*!< INPSEL (Bitfield-Mask: 0x01) */ + #define R_PDM_CH_PDMDSR_SFMD_Pos (4UL) /*!< SFMD (Bit 4) */ + #define R_PDM_CH_PDMDSR_SFMD_Msk (0x70UL) /*!< SFMD (Bitfield-Mask: 0x07) */ + #define R_PDM_CH_PDMDSR_HFIS_Pos (8UL) /*!< HFIS (Bit 8) */ + #define R_PDM_CH_PDMDSR_HFIS_Msk (0x300UL) /*!< HFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_CFIS_Pos (12UL) /*!< CFIS (Bit 12) */ + #define R_PDM_CH_PDMDSR_CFIS_Msk (0x3000UL) /*!< CFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_LFIS_Pos (16UL) /*!< LFIS (Bit 16) */ + #define R_PDM_CH_PDMDSR_LFIS_Msk (0x30000UL) /*!< LFIS (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_SDMAMD_Pos (24UL) /*!< SDMAMD (Bit 24) */ + #define R_PDM_CH_PDMDSR_SDMAMD_Msk (0x3000000UL) /*!< SDMAMD (Bitfield-Mask: 0x03) */ + #define R_PDM_CH_PDMDSR_DBIS_Pos (28UL) /*!< DBIS (Bit 28) */ + #define R_PDM_CH_PDMDSR_DBIS_Msk (0xf0000000UL) /*!< DBIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== PDSFCR ========================================================= */ + #define R_PDM_CH_PDSFCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_PDM_CH_PDSFCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ + #define R_PDM_CH_PDSFCR_SINCDEC_Pos (16UL) /*!< SINCDEC (Bit 16) */ + #define R_PDM_CH_PDSFCR_SINCDEC_Msk (0xff0000UL) /*!< SINCDEC (Bitfield-Mask: 0xff) */ + #define R_PDM_CH_PDSFCR_SINCRNG_Pos (24UL) /*!< SINCRNG (Bit 24) */ + #define R_PDM_CH_PDSFCR_SINCRNG_Msk (0x1f000000UL) /*!< SINCRNG (Bitfield-Mask: 0x1f) */ +/* ======================================================= PDHFCS0R ======================================================== */ + #define R_PDM_CH_PDHFCS0R_HFS0_Pos (0UL) /*!< HFS0 (Bit 0) */ + #define R_PDM_CH_PDHFCS0R_HFS0_Msk (0xffffUL) /*!< HFS0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= PDHFCK1R ======================================================== */ + #define R_PDM_CH_PDHFCK1R_HFK1_Pos (0UL) /*!< HFK1 (Bit 0) */ + #define R_PDM_CH_PDHFCK1R_HFK1_Msk (0xffffUL) /*!< HFK1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== PDHFCHR ======================================================== */ + #define R_PDM_CH_PDHFCHR_HFHn_Pos (0UL) /*!< HFHn (Bit 0) */ + #define R_PDM_CH_PDHFCHR_HFHn_Msk (0xffffUL) /*!< HFHn (Bitfield-Mask: 0xffff) */ +/* ======================================================== PDCFCHR ======================================================== */ + #define R_PDM_CH_PDCFCHR_CFHn_Pos (0UL) /*!< CFHn (Bit 0) */ + #define R_PDM_CH_PDCFCHR_CFHn_Msk (0x1fffUL) /*!< CFHn (Bitfield-Mask: 0x1fff) */ +/* ====================================================== PDLFCH010R ======================================================= */ + #define R_PDM_CH_PDLFCH010R_LFH010_Pos (0UL) /*!< LFH010 (Bit 0) */ + #define R_PDM_CH_PDLFCH010R_LFH010_Msk (0x1fffUL) /*!< LFH010 (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PDLFCH1R ======================================================== */ + #define R_PDM_CH_PDLFCH1R_LFH1n_Pos (0UL) /*!< LFH1n (Bit 0) */ + #define R_PDM_CH_PDLFCH1R_LFH1n_Msk (0x1fffUL) /*!< LFH1n (Bitfield-Mask: 0x1fff) */ +/* ======================================================== PDSDLTR ======================================================== */ + #define R_PDM_CH_PDSDLTR_SDETL_Pos (0UL) /*!< SDETL (Bit 0) */ + #define R_PDM_CH_PDSDLTR_SDETL_Msk (0xfffffUL) /*!< SDETL (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDSDUTR ======================================================== */ + #define R_PDM_CH_PDSDUTR_SDETU_Pos (0UL) /*!< SDETU (Bit 0) */ + #define R_PDM_CH_PDSDUTR_SDETU_Msk (0xfffffUL) /*!< SDETU (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDDBCR ========================================================= */ + #define R_PDM_CH_PDDBCR_DATRITHR_Pos (0UL) /*!< DATRITHR (Bit 0) */ + #define R_PDM_CH_PDDBCR_DATRITHR_Msk (0x7UL) /*!< DATRITHR (Bitfield-Mask: 0x07) */ +/* ======================================================== PDSCTSR ======================================================== */ + #define R_PDM_CH_PDSCTSR_SCDL_Pos (0UL) /*!< SCDL (Bit 0) */ + #define R_PDM_CH_PDSCTSR_SCDL_Msk (0x1fffUL) /*!< SCDL (Bitfield-Mask: 0x1fff) */ + #define R_PDM_CH_PDSCTSR_SCDH_Pos (16UL) /*!< SCDH (Bit 16) */ + #define R_PDM_CH_PDSCTSR_SCDH_Msk (0x1fff0000UL) /*!< SCDH (Bitfield-Mask: 0x1fff) */ +/* ======================================================== PDOVLTR ======================================================== */ + #define R_PDM_CH_PDOVLTR_OVDL_Pos (0UL) /*!< OVDL (Bit 0) */ + #define R_PDM_CH_PDOVLTR_OVDL_Msk (0xfffffUL) /*!< OVDL (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDOVUTR ======================================================== */ + #define R_PDM_CH_PDOVUTR_OVDU_Pos (0UL) /*!< OVDU (Bit 0) */ + #define R_PDM_CH_PDOVUTR_OVDU_Msk (0xfffffUL) /*!< OVDU (Bitfield-Mask: 0xfffff) */ +/* ======================================================== PDDRCR ========================================================= */ + #define R_PDM_CH_PDDRCR_DATRE_Pos (0UL) /*!< DATRE (Bit 0) */ + #define R_PDM_CH_PDDRCR_DATRE_Msk (0x1UL) /*!< DATRE (Bitfield-Mask: 0x01) */ +/* ========================================================= PDDCR ========================================================= */ + #define R_PDM_CH_PDDCR_DATC_Pos (0UL) /*!< DATC (Bit 0) */ + #define R_PDM_CH_PDDCR_DATC_Msk (0x1UL) /*!< DATC (Bitfield-Mask: 0x01) */ +/* ========================================================= PDDRR ========================================================= */ + #define R_PDM_CH_PDDRR_DAT_Pos (0UL) /*!< DAT (Bit 0) */ + #define R_PDM_CH_PDDRR_DAT_Msk (0xfffffUL) /*!< DAT (Bitfield-Mask: 0xfffff) */ +/* ========================================================= PDDSR ========================================================= */ + #define R_PDM_CH_PDDSR_DATNUM_Pos (0UL) /*!< DATNUM (Bit 0) */ + #define R_PDM_CH_PDDSR_DATNUM_Msk (0xffUL) /*!< DATNUM (Bitfield-Mask: 0xff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPINTCTL ======================================================== */ + #define R_ACMPHS0_CPINTCTL_MSKE_Pos (0UL) /*!< MSKE (Bit 0) */ + #define R_ACMPHS0_CPINTCTL_MSKE_Msk (0x1UL) /*!< MSKE (Bitfield-Mask: 0x01) */ +/* ======================================================= CPMSKCTL ======================================================== */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Pos (0UL) /*!< MSKSEL (Bit 0) */ + #define R_ACMPHS0_CPMSKCTL_MSKSEL_Msk (0x7UL) /*!< MSKSEL (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB_Pos (0UL) /*!< PSARB (Bit 0) */ + #define R_PSCU_PSARB_PSARB_Msk (0x1UL) /*!< PSARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC_Pos (0UL) /*!< PSARC (Bit 0) */ + #define R_PSCU_PSARC_PSARC_Msk (0x1UL) /*!< PSARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD_Pos (0UL) /*!< PSARD (Bit 0) */ + #define R_PSCU_PSARD_PSARD_Msk (0x1UL) /*!< PSARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE_Pos (0UL) /*!< PSARE (Bit 0) */ + #define R_PSCU_PSARE_PSARE_Msk (0x1UL) /*!< PSARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR_Pos (0UL) /*!< MSSAR (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR_Msk (0x1UL) /*!< MSSAR (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARB ========================================================= */ + #define R_PSCU_PPARB_PPARB_Pos (0UL) /*!< PPARB (Bit 0) */ + #define R_PSCU_PPARB_PPARB_Msk (0x1UL) /*!< PPARB (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARC ========================================================= */ + #define R_PSCU_PPARC_PPARC_Pos (0UL) /*!< PPARC (Bit 0) */ + #define R_PSCU_PPARC_PPARC_Msk (0x1UL) /*!< PPARC (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARD ========================================================= */ + #define R_PSCU_PPARD_PPARD_Pos (0UL) /*!< PPARD (Bit 0) */ + #define R_PSCU_PPARD_PPARD_Msk (0x1UL) /*!< PPARD (Bitfield-Mask: 0x01) */ +/* ========================================================= PPARE ========================================================= */ + #define R_PSCU_PPARE_PPARE_Pos (0UL) /*!< PPARE (Bit 0) */ + #define R_PSCU_PPARE_PPARE_Msk (0x1UL) /*!< PPARE (Bitfield-Mask: 0x01) */ +/* ========================================================= MSPAR ========================================================= */ + #define R_PSCU_MSPAR_MSPAR_Pos (0UL) /*!< MSPAR (Bit 0) */ + #define R_PSCU_MSPAR_MSPAR_Msk (0x1UL) /*!< MSPAR (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFSAMON ======================================================== */ + #define R_PSCU_SFSAMON_SFS_Pos (15UL) /*!< SFS (Bit 15) */ + #define R_PSCU_SFSAMON_SFS_Msk (0xff8000UL) /*!< SFS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSMABT ======================================================== */ + #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSDIVBYP ======================================================= */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */ + #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */ + #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */ + #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */ +/* ======================================================= BUSTHRPUT ======================================================= */ + #define R_BUS_BUSTHRPUT_DIS_Pos (0UL) /*!< DIS (Bit 0) */ + #define R_BUS_BUSTHRPUT_DIS_Msk (0x1UL) /*!< DIS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x3UL) /*!< RFXIF (Bitfield-Mask: 0x03) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DADR ========================================================== */ + #define R_DAC_B0_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_B0_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DACR0 ========================================================= */ + #define R_DAC_B0_DACR0_DACEN_Pos (0UL) /*!< DACEN (Bit 0) */ + #define R_DAC_B0_DACR0_DACEN_Msk (0x1UL) /*!< DACEN (Bitfield-Mask: 0x01) */ + #define R_DAC_B0_DACR0_DAE_Pos (15UL) /*!< DAE (Bit 15) */ + #define R_DAC_B0_DACR0_DAE_Msk (0x8000UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_B0_DACR0_DAOUTDIS_Pos (31UL) /*!< DAOUTDIS (Bit 31) */ + #define R_DAC_B0_DACR0_DAOUTDIS_Msk (0x80000000UL) /*!< DAOUTDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= DACR1 ========================================================= */ + #define R_DAC_B0_DACR1_DPSEL_Pos (16UL) /*!< DPSEL (Bit 16) */ + #define R_DAC_B0_DACR1_DPSEL_Msk (0x10000UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= DACR2 ========================================================= */ + #define R_DAC_B0_DACR2_OFSSEL_Pos (8UL) /*!< OFSSEL (Bit 8) */ + #define R_DAC_B0_DACR2_OFSSEL_Msk (0x100UL) /*!< OFSSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos (14UL) /*!< DBGSTOP_TIM (Bit 14) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk (0x4000UL) /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos (15UL) /*!< DBGSTOP_SIR (Bit 15) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk (0x8000UL) /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT1_Pos (2UL) /*!< DBGSTOP_WDT1 (Bit 2) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT1_Msk (0x4UL) /*!< DBGSTOP_WDT1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_NVMERR_Pos (26UL) /*!< DBGSTOP_NVMERR (Bit 26) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_NVMERR_Msk (0x4000000UL) /*!< DBGSTOP_NVMERR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR0_Pos (28UL) /*!< DBGSTOP_CTERR0 (Bit 28) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR0_Msk (0x10000000UL) /*!< DBGSTOP_CTERR0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR1_Pos (29UL) /*!< DBGSTOP_CTERR1 (Bit 29) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CTERR1_Msk (0x20000000UL) /*!< DBGSTOP_CTERR1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGAUTH0 ======================================================== */ + #define R_DEBUG_DBGAUTH0_DBGEN0_Pos (0UL) /*!< DBGEN0 (Bit 0) */ + #define R_DEBUG_DBGAUTH0_DBGEN0_Msk (0x1UL) /*!< DBGEN0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_DBGEN1_Pos (1UL) /*!< DBGEN1 (Bit 1) */ + #define R_DEBUG_DBGAUTH0_DBGEN1_Msk (0x2UL) /*!< DBGEN1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_NIDEN0_Pos (4UL) /*!< NIDEN0 (Bit 4) */ + #define R_DEBUG_DBGAUTH0_NIDEN0_Msk (0x10UL) /*!< NIDEN0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_NIDEN1_Pos (5UL) /*!< NIDEN1 (Bit 5) */ + #define R_DEBUG_DBGAUTH0_NIDEN1_Msk (0x20UL) /*!< NIDEN1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_DEVICEEN_Pos (16UL) /*!< DEVICEEN (Bit 16) */ + #define R_DEBUG_DBGAUTH0_DEVICEEN_Msk (0x10000UL) /*!< DEVICEEN (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGAUTH0_SWDBG_Pos (31UL) /*!< SWDBG (Bit 31) */ + #define R_DEBUG_DBGAUTH0_SWDBG_Msk (0x80000000UL) /*!< SWDBG (Bitfield-Mask: 0x01) */ +/* ====================================================== CACHEDBGCR ======================================================= */ + #define R_DEBUG_CACHEDBGCR_L1RSTDIS_Pos (0UL) /*!< L1RSTDIS (Bit 0) */ + #define R_DEBUG_CACHEDBGCR_L1RSTDIS_Msk (0x1UL) /*!< L1RSTDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= TRPORTCR ======================================================== */ + #define R_DEBUG_TRPORTCR_OE_Pos (0UL) /*!< OE (Bit 0) */ + #define R_DEBUG_TRPORTCR_OE_Msk (0x1UL) /*!< OE (Bitfield-Mask: 0x01) */ + #define R_DEBUG_TRPORTCR_DRV_Pos (2UL) /*!< DRV (Bit 2) */ + #define R_DEBUG_TRPORTCR_DRV_Msk (0xcUL) /*!< DRV (Bitfield-Mask: 0x03) */ + #define R_DEBUG_TRPORTCR_PORTSEL_Pos (8UL) /*!< PORTSEL (Bit 8) */ + #define R_DEBUG_TRPORTCR_PORTSEL_Msk (0x300UL) /*!< PORTSEL (Bitfield-Mask: 0x03) */ + #define R_DEBUG_TRPORTCR_SWOSEL_Pos (16UL) /*!< SWOSEL (Bit 16) */ + #define R_DEBUG_TRPORTCR_SWOSEL_Msk (0x10000UL) /*!< SWOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== ALCTRL ========================================================= */ + #define R_DEBUG_ALCTRL_AL_Pos (0UL) /*!< AL (Bit 0) */ + #define R_DEBUG_ALCTRL_AL_Msk (0xffUL) /*!< AL (Bitfield-Mask: 0xff) */ + #define R_DEBUG_ALCTRL_FAILCNT_Pos (30UL) /*!< FAILCNT (Bit 30) */ + #define R_DEBUG_ALCTRL_FAILCNT_Msk (0xc0000000UL) /*!< FAILCNT (Bitfield-Mask: 0x03) */ +/* ======================================================= FSBLSTAT ======================================================== */ + #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */ + #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */ +/* ======================================================= TRPORTSZ ======================================================== */ + #define R_DEBUG_TRPORTSZ_PORTSIZE_Pos (0UL) /*!< PORTSIZE (Bit 0) */ + #define R_DEBUG_TRPORTSZ_PORTSIZE_Msk (0xffffffffUL) /*!< PORTSIZE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DBGNVMCR ======================================================== */ + #define R_DEBUG_DBGNVMCR_NVMWE_Pos (0UL) /*!< NVMWE (Bit 0) */ + #define R_DEBUG_DBGNVMCR_NVMWE_Msk (0x1UL) /*!< NVMWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ========================================================= DMCTL ========================================================= */ + #define R_DMA_DMCTL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMA_DMCTL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMA_DMCTL_ERCH_Pos (4UL) /*!< ERCH (Bit 4) */ + #define R_DMA_DMCTL_ERCH_Msk (0x10UL) /*!< ERCH (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0xfUL) /*!< DMECH (Bitfield-Mask: 0x0f) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONTROL ======================================================== */ + #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */ + #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */ + #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */ + #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */ + #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */ + #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */ + #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */ + #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */ + #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */ + #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */ + #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */ + #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */ + #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */ + #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */ + #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */ + #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */ + #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */ + #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */ + #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */ + #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */ + #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */ + #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */ + #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */ + #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */ + #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */ + #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */ + #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */ + #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */ + #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */ + #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */ + #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCTL ========================================================= */ + #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */ + #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */ + #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CACHECTL ======================================================== */ + #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */ + #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */ + #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */ + #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */ + #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */ + #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */ + #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */ + #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */ + #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */ + #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */ + #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */ + #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */ + #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */ + #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */ +/* ====================================================== HWREVISION ======================================================= */ + #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */ + #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */ + #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */ + #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */ + #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */ + #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */ + #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */ + #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */ + #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */ + #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */ +/* ======================================================== COLOR1 ========================================================= */ + #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */ + #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */ + #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */ + #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */ + #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */ +/* ======================================================== COLOR2 ========================================================= */ + #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */ + #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */ + #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */ + #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */ + #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */ +/* ======================================================== PATTERN ======================================================== */ + #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */ + #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */ +/* ======================================================== L1START ======================================================== */ + #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2START ======================================================== */ + #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3START ======================================================== */ + #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4START ======================================================== */ + #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5START ======================================================== */ + #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6START ======================================================== */ + #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1XADD ========================================================= */ + #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2XADD ========================================================= */ + #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3XADD ========================================================= */ + #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4XADD ========================================================= */ + #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5XADD ========================================================= */ + #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6XADD ========================================================= */ + #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1YADD ========================================================= */ + #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2YADD ========================================================= */ + #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3YADD ========================================================= */ + #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4YADD ========================================================= */ + #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5YADD ========================================================= */ + #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6YADD ========================================================= */ + #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1BAND ========================================================= */ + #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2BAND ========================================================= */ + #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXORIGIN ======================================================= */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXPITCH ======================================================== */ + #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */ + #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TEXMASK ======================================================== */ + #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */ + #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */ + #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */ + #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */ +/* ======================================================== LUSTART ======================================================== */ + #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */ + #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUXADD ========================================================= */ + #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */ + #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUYADD ========================================================= */ + #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */ + #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTI ======================================================== */ + #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */ + #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTF ======================================================== */ + #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */ + #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */ +/* ======================================================== LVXADDI ======================================================== */ + #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */ + #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LVYADDI ======================================================== */ + #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */ + #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVYXADDF ======================================================== */ + #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */ + #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */ + #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */ + #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */ +/* ======================================================= TEXCLADDR ======================================================= */ + #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */ + #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */ +/* ======================================================= TEXCLDATA ======================================================= */ + #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */ + #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TEXCLOFFSET ====================================================== */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== COLKEY ========================================================= */ + #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */ + #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */ + #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */ + #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */ +/* ========================================================= SIZE ========================================================== */ + #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */ + #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */ + #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */ + #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */ +/* ========================================================= PITCH ========================================================= */ + #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */ + #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */ + #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */ + #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */ +/* ======================================================== ORIGIN ========================================================= */ + #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */ + #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLISTSTART ======================================================= */ + #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */ + #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFTRIGGER ====================================================== */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== PERFCOUNT1 ======================================================= */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFCOUNT2 ======================================================= */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DBWER ========================================================= */ + #define R_DRW_DBWER_BWE_Pos (2UL) /*!< BWE (Bit 2) */ + #define R_DRW_DBWER_BWE_Msk (0x4UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DTCADMOD ======================================================== */ + #define R_DTC_DTCADMOD_SHORT_Pos (0UL) /*!< SHORT (Bit 0) */ + #define R_DTC_DTCADMOD_SHORT_Msk (0x1UL) /*!< SHORT (Bitfield-Mask: 0x01) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_SEC_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DTCDISP ======================================================== */ + #define R_DTC_DTCDISP_DTCDISP_Pos (0UL) /*!< DTCDISP (Bit 0) */ + #define R_DTC_DTCDISP_DTCDISP_Msk (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCIBR ========================================================= */ + #define R_DTC_DTCIBR_DTCIBR_Pos (10UL) /*!< DTCIBR (Bit 10) */ + #define R_DTC_DTCIBR_DTCIBR_Msk (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= DTCOR ========================================================= */ + #define R_DTC_DTCOR_SQTFRL_Pos (0UL) /*!< SQTFRL (Bit 0) */ + #define R_DTC_DTCOR_SQTFRL_Msk (0x1UL) /*!< SQTFRL (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSQE ========================================================= */ + #define R_DTC_DTCSQE_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSQE_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSQE_ESPSEL_Pos (15UL) /*!< ESPSEL (Bit 15) */ + #define R_DTC_DTCSQE_ESPSEL_Msk (0x8000UL) /*!< ESPSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR_Pos (1UL) /*!< ELSEGR (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR_Msk (0x2UL) /*!< ELSEGR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCSARC_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARA ======================================================== */ + #define R_ELC_ELCPARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCPARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCPARA_ELSEGR_Pos (1UL) /*!< ELSEGR (Bit 1) */ + #define R_ELC_ELCPARA_ELSEGR_Msk (0x2UL) /*!< ELSEGR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARB ======================================================== */ + #define R_ELC_ELCPARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCPARC ======================================================== */ + #define R_ELC_ELCPARC_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */ + #define R_ELC_ELCPARC_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GR1_CLUT0 ======================================================= */ + #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR1_CLUT1 ======================================================= */ + #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT0 ======================================================= */ + #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT1 ======================================================= */ + #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASOC_Pos (24UL) /*!< ASOC (Bit 24) */ + #define R_GPT0_GTICASR_ASOC_Msk (0x1000000UL) /*!< ASOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSOC_Pos (24UL) /*!< BSOC (Bit 24) */ + #define R_GPT0_GTICBSR_BSOC_Msk (0x1000000UL) /*!< BSOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */ + #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */ + #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */ + #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */ + #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */ + #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_BINV_Pos (5UL) /*!< BINV (Bit 5) */ + #define R_GPT0_GTCR_BINV_Msk (0x20UL) /*!< BINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_AINV_Pos (4UL) /*!< AINV (Bit 4) */ + #define R_GPT0_GTCR_AINV_Msk (0x10UL) /*!< AINV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT0_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */ + #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */ + #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */ + #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */ + #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */ + #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT0_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINT_Pos (0UL) /*!< GTINT (Bit 0) */ + #define R_GPT0_GTINTAD_GTINT_Msk (0x1UL) /*!< GTINT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */ + #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================= GTADCMSC ======================================================== */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Pos (12UL) /*!< ADCMSCNT (Bit 12) */ + #define R_GPT0_GTADCMSC_ADCMSCNT_Msk (0xf000UL) /*!< ADCMSCNT (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos (8UL) /*!< ADCMSCNTIV (Bit 8) */ + #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk (0xf00UL) /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMST_Pos (4UL) /*!< ADCMST (Bit 4) */ + #define R_GPT0_GTADCMSC_ADCMST_Msk (0xf0UL) /*!< ADCMST (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTADCMSC_ADCMSC_Pos (0UL) /*!< ADCMSC (Bit 0) */ + #define R_GPT0_GTADCMSC_ADCMSC_Msk (0x3UL) /*!< ADCMSC (Bitfield-Mask: 0x03) */ +/* ======================================================= GTADCMSS ======================================================== */ + #define R_GPT0_GTADCMSS_ADCMSAL_Pos (0UL) /*!< ADCMSAL (Bit 0) */ + #define R_GPT0_GTADCMSS_ADCMSAL_Msk (0x7UL) /*!< ADCMSAL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Pos (4UL) /*!< ADCMSBL (Bit 4) */ + #define R_GPT0_GTADCMSS_ADCMSBL_Msk (0x70UL) /*!< ADCMSBL (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Pos (16UL) /*!< ADCMBSA (Bit 16) */ + #define R_GPT0_GTADCMSS_ADCMBSA_Msk (0x70000UL) /*!< ADCMBSA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Pos (20UL) /*!< ADCMBSB (Bit 20) */ + #define R_GPT0_GTADCMSS_ADCMBSB_Msk (0x700000UL) /*!< ADCMBSB (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */ + #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */ + #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTBER2 ========================================================= */ + #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */ + #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */ + #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */ + #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */ + #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */ + #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */ + #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */ + #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */ + #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */ + #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */ + #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */ + #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */ + #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */ + #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */ + #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */ + #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */ + #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */ + #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */ + #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */ + #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */ + #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTOLBR ========================================================= */ + #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */ + #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */ + #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTICCR ========================================================= */ + #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */ + #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */ + #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */ + #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */ + #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */ + #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */ + #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */ + #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */ + #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */ + #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */ + #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */ + #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */ + #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */ + #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */ + #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */ + #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */ + #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */ + #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */ + #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */ + #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */ + #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== GTCLKCR ======================================================== */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Pos (0UL) /*!< BPEN (Bit 0) */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Msk (0x1UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x300UL) /*!< FRANGE (Bitfield-Mask: 0x03) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ +/* ======================================================== GTONCWP ======================================================== */ + #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== GTONCCR ======================================================== */ + #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */ + #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */ + #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */ + #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */ + #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IRQCRa ========================================================= */ + #define R_ICU_IRQCRa_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCRa_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRa_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCRa_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRa_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCRa_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCRb ========================================================= */ + #define R_ICU_IRQCRb_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCRb_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRb_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCRb_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCRb_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCRb_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSELR ======================================================== */ + #define R_ICU_INTSELR_IS_Pos (0UL) /*!< IS (Bit 0) */ + #define R_ICU_INTSELR_IS_Msk (0x1UL) /*!< IS (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_PVD1EN_Pos (2UL) /*!< PVD1EN (Bit 2) */ + #define R_ICU_NMIER_PVD1EN_Msk (0x4UL) /*!< PVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_PVD2EN_Pos (3UL) /*!< PVD2EN (Bit 3) */ + #define R_ICU_NMIER_PVD2EN_Msk (0x8UL) /*!< PVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_SOSTEN_Pos (5UL) /*!< SOSTEN (Bit 5) */ + #define R_ICU_NMIER_SOSTEN_Msk (0x20UL) /*!< SOSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSEN_Pos (12UL) /*!< BUSEN (Bit 12) */ + #define R_ICU_NMIER_BUSEN_Msk (0x1000UL) /*!< BUSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CMEN_Pos (13UL) /*!< CMEN (Bit 13) */ + #define R_ICU_NMIER_CMEN_Msk (0x2000UL) /*!< CMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LMEN_Pos (14UL) /*!< LMEN (Bit 14) */ + #define R_ICU_NMIER_LMEN_Msk (0x4000UL) /*!< LMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LUEN_Pos (15UL) /*!< LUEN (Bit 15) */ + #define R_ICU_NMIER_LUEN_Msk (0x8000UL) /*!< LUEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_FPUFLTEN_Pos (16UL) /*!< FPUFLTEN (Bit 16) */ + #define R_ICU_NMIER_FPUFLTEN_Msk (0x10000UL) /*!< FPUFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_MRCRDEN_Pos (17UL) /*!< MRCRDEN (Bit 17) */ + #define R_ICU_NMIER_MRCRDEN_Msk (0x20000UL) /*!< MRCRDEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_MRERDEN_Pos (18UL) /*!< MRERDEN (Bit 18) */ + #define R_ICU_NMIER_MRERDEN_Msk (0x40000UL) /*!< MRERDEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IPCEN_Pos (20UL) /*!< IPCEN (Bit 20) */ + #define R_ICU_NMIER_IPCEN_Msk (0x100000UL) /*!< IPCEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_PVD1CLR_Pos (2UL) /*!< PVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_PVD1CLR_Msk (0x4UL) /*!< PVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_PVD2CLR_Pos (3UL) /*!< PVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_PVD2CLR_Msk (0x8UL) /*!< PVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_SOSTCLR_Pos (5UL) /*!< SOSTCLR (Bit 5) */ + #define R_ICU_NMICLR_SOSTCLR_Msk (0x20UL) /*!< SOSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSCLR_Pos (12UL) /*!< BUSCLR (Bit 12) */ + #define R_ICU_NMICLR_BUSCLR_Msk (0x1000UL) /*!< BUSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CMCLR_Pos (13UL) /*!< CMCLR (Bit 13) */ + #define R_ICU_NMICLR_CMCLR_Msk (0x2000UL) /*!< CMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LMCLR_Pos (14UL) /*!< LMCLR (Bit 14) */ + #define R_ICU_NMICLR_LMCLR_Msk (0x4000UL) /*!< LMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LUCLR_Pos (15UL) /*!< LUCLR (Bit 15) */ + #define R_ICU_NMICLR_LUCLR_Msk (0x8000UL) /*!< LUCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_FPUFLTCLR_Pos (16UL) /*!< FPUFLTCLR (Bit 16) */ + #define R_ICU_NMICLR_FPUFLTCLR_Msk (0x10000UL) /*!< FPUFLTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_MRCRDCLR_Pos (17UL) /*!< MRCRDCLR (Bit 17) */ + #define R_ICU_NMICLR_MRCRDCLR_Msk (0x20000UL) /*!< MRCRDCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_MRERDCLR_Pos (18UL) /*!< MRERDCLR (Bit 18) */ + #define R_ICU_NMICLR_MRERDCLR_Msk (0x40000UL) /*!< MRERDCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IPCCLR_Pos (20UL) /*!< IPCCLR (Bit 20) */ + #define R_ICU_NMICLR_IPCCLR_Msk (0x100000UL) /*!< IPCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_PVD1ST_Pos (2UL) /*!< PVD1ST (Bit 2) */ + #define R_ICU_NMISR_PVD1ST_Msk (0x4UL) /*!< PVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_PVD2ST_Pos (3UL) /*!< PVD2ST (Bit 3) */ + #define R_ICU_NMISR_PVD2ST_Msk (0x8UL) /*!< PVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_SOSTST_Pos (5UL) /*!< SOSTST (Bit 5) */ + #define R_ICU_NMISR_SOSTST_Msk (0x20UL) /*!< SOSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_ICU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_ICU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LMST_Pos (14UL) /*!< LMST (Bit 14) */ + #define R_ICU_NMISR_LMST_Msk (0x4000UL) /*!< LMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_ICU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_FPUFLTST_Pos (16UL) /*!< FPUFLTST (Bit 16) */ + #define R_ICU_NMISR_FPUFLTST_Msk (0x10000UL) /*!< FPUFLTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_MRCRDST_Pos (17UL) /*!< MRCRDST (Bit 17) */ + #define R_ICU_NMISR_MRCRDST_Msk (0x20000UL) /*!< MRCRDST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_MRERDST_Pos (18UL) /*!< MRERDST (Bit 18) */ + #define R_ICU_NMISR_MRERDST_Msk (0x40000UL) /*!< MRERDST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IPCST_Pos (20UL) /*!< IPCST (Bit 20) */ + #define R_ICU_NMISR_IPCST_Msk (0x100000UL) /*!< IPCST (Bitfield-Mask: 0x01) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_WUPEN_Pos (16UL) /*!< WUPEN (Bit 16) */ + #define R_ICU_WUPEN_WUPEN_Msk (0x10000UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_WUPEN_Pos (0UL) /*!< WUPEN (Bit 0) */ + #define R_ICU_WUPEN1_WUPEN_Msk (0x1UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_IRQWUPEN_Pos (16UL) /*!< IRQWUPEN (Bit 16) */ + #define R_ICU_WUPEN1_IRQWUPEN_Msk (0x10000UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ===================================================== DSLPWUPIRQEN ====================================================== */ + #define R_ICU_DSLPWUPIRQEN_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ + #define R_ICU_DSLPWUPIRQEN_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x3ffUL) /*!< DELS (Bitfield-Mask: 0x3ff) */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x3ffUL) /*!< IELS (Bitfield-Mask: 0x3ff) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTCR ========================================================= */ + #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== IWDTRCR ======================================================== */ + #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= IWDTCSTPR ======================================================= */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HCMDQRST_Pos (9UL) /*!< HCMDQRST (Bit 9) */ + #define R_I3C0_RSTCTL_HCMDQRST_Msk (0x200UL) /*!< HCMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRSPQRST_Pos (10UL) /*!< HRSPQRST (Bit 10) */ + #define R_I3C0_RSTCTL_HRSPQRST_Msk (0x400UL) /*!< HRSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HTDBRST_Pos (11UL) /*!< HTDBRST (Bit 11) */ + #define R_I3C0_RSTCTL_HTDBRST_Msk (0x800UL) /*!< HTDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_HRDBRST_Pos (12UL) /*!< HRDBRST (Bit 12) */ + #define R_I3C0_RSTCTL_HRDBRST_Msk (0x1000UL) /*!< HRDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x70000UL) /*!< SVAEn (Bitfield-Mask: 0x07) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= STCTL ========================================================= */ + #define R_I3C0_STCTL_STOE_Pos (0UL) /*!< STOE (Bit 0) */ + #define R_I3C0_STCTL_STOE_Msk (0x1UL) /*!< STOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ATCTL ========================================================= */ + #define R_I3C0_ATCTL_ATTRGS_Pos (0UL) /*!< ATTRGS (Bit 0) */ + #define R_I3C0_ATCTL_ATTRGS_Msk (0x1UL) /*!< ATTRGS (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_MREFOE_Pos (1UL) /*!< MREFOE (Bit 1) */ + #define R_I3C0_ATCTL_MREFOE_Msk (0x2UL) /*!< MREFOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_AMEOE_Pos (2UL) /*!< AMEOE (Bit 2) */ + #define R_I3C0_ATCTL_AMEOE_Msk (0x4UL) /*!< AMEOE (Bitfield-Mask: 0x01) */ + #define R_I3C0_ATCTL_CDIV_Pos (8UL) /*!< CDIV (Bit 8) */ + #define R_I3C0_ATCTL_CDIV_Msk (0xff00UL) /*!< CDIV (Bitfield-Mask: 0xff) */ +/* ========================================================= ATTRG ========================================================= */ + #define R_I3C0_ATTRG_ATSTRG_Pos (0UL) /*!< ATSTRG (Bit 0) */ + #define R_I3C0_ATTRG_ATSTRG_Msk (0x1UL) /*!< ATSTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== ATCCNTE ======================================================== */ + #define R_I3C0_ATCCNTE_ATCE_Pos (0UL) /*!< ATCE (Bit 0) */ + #define R_I3C0_ATCCNTE_ATCE_Msk (0x1UL) /*!< ATCE (Bitfield-Mask: 0x01) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== HCMDQP ========================================================= */ + #define R_I3C0_HCMDQP_HCMDQP_Pos (0UL) /*!< HCMDQP (Bit 0) */ + #define R_I3C0_HCMDQP_HCMDQP_Msk (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HRSPQP ========================================================= */ + #define R_I3C0_HRSPQP_HRSPQP_Pos (0UL) /*!< HRSPQP (Bit 0) */ + #define R_I3C0_HRSPQP_HRSPQP_Msk (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HTDTBP ========================================================= */ + #define R_I3C0_HTDTBP_HTDTBP_Pos (0UL) /*!< HTDTBP (Bit 0) */ + #define R_I3C0_HTDTBP_HTDTBP_Msk (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ======================================================== HQTHCTL ======================================================== */ + #define R_I3C0_HQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_HQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_HQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= HTBTHCTL ======================================================== */ + #define R_I3C0_HTBTHCTL_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_HTBTHCTL_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_HTBTHCTL_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_HTBTHCTL_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_HTBTHCTL_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_WUCNDDF_Pos (24UL) /*!< WUCNDDF (Bit 24) */ + #define R_I3C0_BST_WUCNDDF_Msk (0x1000000UL) /*!< WUCNDDF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_WUCNDDE_Pos (24UL) /*!< WUCNDDE (Bit 24) */ + #define R_I3C0_BSTE_WUCNDDE_Msk (0x1000000UL) /*!< WUCNDDE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_WUCNDDIE_Pos (24UL) /*!< WUCNDDIE (Bit 24) */ + #define R_I3C0_BIE_WUCNDDIE_Msk (0x1000000UL) /*!< WUCNDDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_WUCNDDFC_Pos (24UL) /*!< WUCNDDFC (Bit 24) */ + #define R_I3C0_BSTFC_WUCNDDFC_Msk (0x1000000UL) /*!< WUCNDDFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= HTST ========================================================== */ + #define R_I3C0_HTST_TDBEF_Pos (0UL) /*!< TDBEF (Bit 0) */ + #define R_I3C0_HTST_TDBEF_Msk (0x1UL) /*!< TDBEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RDBFF_Pos (1UL) /*!< RDBFF (Bit 1) */ + #define R_I3C0_HTST_RDBFF_Msk (0x2UL) /*!< RDBFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_HTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_HTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_HTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_HTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ +/* ========================================================= HTSTE ========================================================= */ + #define R_I3C0_HTSTE_TDBEE_Pos (0UL) /*!< TDBEE (Bit 0) */ + #define R_I3C0_HTSTE_TDBEE_Msk (0x1UL) /*!< TDBEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RDBFE_Pos (1UL) /*!< RDBFE (Bit 1) */ + #define R_I3C0_HTSTE_RDBFE_Msk (0x2UL) /*!< RDBFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_HTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_HTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_HTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_HTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ +/* ========================================================= HTIE ========================================================== */ + #define R_I3C0_HTIE_TDBEIE_Pos (0UL) /*!< TDBEIE (Bit 0) */ + #define R_I3C0_HTIE_TDBEIE_Msk (0x1UL) /*!< TDBEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RDBFIE_Pos (1UL) /*!< RDBFIE (Bit 1) */ + #define R_I3C0_HTIE_RDBFIE_Msk (0x2UL) /*!< RDBFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_HTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_HTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_HTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_HTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HTSTFC ========================================================= */ + #define R_I3C0_HTSTFC_TDBEFC_Pos (0UL) /*!< TDBEFC (Bit 0) */ + #define R_I3C0_HTSTFC_TDBEFC_Msk (0x1UL) /*!< TDBEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RDBFFC_Pos (1UL) /*!< RDBFFC (Bit 1) */ + #define R_I3C0_HTSTFC_RDBFFC_Msk (0x2UL) /*!< RDBFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_HTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_HTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_HTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_HTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_HTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x70000UL) /*!< SVAFn (Bitfield-Mask: 0x07) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCCPT ========================================================= */ + #define R_I3C0_MRCCPT_MRCCPT_Pos (0UL) /*!< MRCCPT (Bit 0) */ + #define R_I3C0_MRCCPT_MRCCPT_Msk (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS4 ======================================================== */ + #define R_I3C0_DATBAS4_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS4_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS4_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS4_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS4_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS4_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS4_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS4_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS4_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS4_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS4_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS4_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS4_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS5 ======================================================== */ + #define R_I3C0_DATBAS5_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS5_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS5_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS5_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS5_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS5_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS5_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS5_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS5_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS5_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS5_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS5_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS5_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS6 ======================================================== */ + #define R_I3C0_DATBAS6_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS6_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS6_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS6_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS6_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS6_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS6_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS6_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS6_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS6_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS6_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS6_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS6_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS7 ======================================================== */ + #define R_I3C0_DATBAS7_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS7_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS7_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS7_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS7_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS7_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS7_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS7_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS7_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS7_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS7_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS7_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS7_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT0_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT0_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT1_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT1_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT2_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT2_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT3_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT3_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT4 ========================================================= */ + #define R_I3C0_MSDCT4_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT4_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT4_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT4_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT4_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT4_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT4_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT4_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT4_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT5 ========================================================= */ + #define R_I3C0_MSDCT5_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT5_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT5_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT5_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT5_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT5_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT5_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT5_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT5_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT6 ========================================================= */ + #define R_I3C0_MSDCT6_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT6_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT6_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT6_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT6_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT6_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT6_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT6_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT6_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT7 ========================================================= */ + #define R_I3C0_MSDCT7_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT7_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT7_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT7_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT7_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR4_Pos (12UL) /*!< RBCR4 (Bit 12) */ + #define R_I3C0_MSDCT7_RBCR4_Msk (0x1000UL) /*!< RBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR5_Pos (13UL) /*!< RBCR5 (Bit 13) */ + #define R_I3C0_MSDCT7_RBCR5_Msk (0x2000UL) /*!< RBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT7_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT7_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR4_Pos (12UL) /*!< TBCR4 (Bit 12) */ + #define R_I3C0_SVDCT_TBCR4_Msk (0x1000UL) /*!< TBCR4 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR5_Pos (13UL) /*!< TBCR5 (Bit 13) */ + #define R_I3C0_SVDCT_TBCR5_Msk (0x2000UL) /*!< TBCR5 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD1 ======================================================== */ + #define R_I3C0_SVDVAD1_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD1_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD1_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD1_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD1_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD1_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD1_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== SVDVAD2 ======================================================== */ + #define R_I3C0_SVDVAD2_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD2_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD2_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD2_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD2_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD2_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD2_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_SPTSYN_Pos (0UL) /*!< SPTSYN (Bit 0) */ + #define R_I3C0_CETSM_SPTSYN_Msk (0x1UL) /*!< SPTSYN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN0_Pos (1UL) /*!< SPTASYN0 (Bit 1) */ + #define R_I3C0_CETSM_SPTASYN0_Msk (0x2UL) /*!< SPTASYN0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_SPTASYN1_Pos (2UL) /*!< SPTASYN1 (Bit 2) */ + #define R_I3C0_CETSM_SPTASYN1_Msk (0x4UL) /*!< SPTASYN1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ========================================================= CETSS ========================================================= */ + #define R_I3C0_CETSS_SYNE_Pos (0UL) /*!< SYNE (Bit 0) */ + #define R_I3C0_CETSS_SYNE_Msk (0x1UL) /*!< SYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CETSS_ASYNE_Pos (1UL) /*!< ASYNE (Bit 1) */ + #define R_I3C0_CETSS_ASYNE_Msk (0x6UL) /*!< ASYNE (Bitfield-Mask: 0x03) */ + #define R_I3C0_CETSS_ICOVF_Pos (7UL) /*!< ICOVF (Bit 7) */ + #define R_I3C0_CETSS_ICOVF_Msk (0x80UL) /*!< ICOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= CGHDRCAP ======================================================== */ + #define R_I3C0_CGHDRCAP_DDREN_Pos (0UL) /*!< DDREN (Bit 0) */ + #define R_I3C0_CGHDRCAP_DDREN_Msk (0x1UL) /*!< DDREN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSPEN_Pos (1UL) /*!< TSPEN (Bit 1) */ + #define R_I3C0_CGHDRCAP_TSPEN_Msk (0x2UL) /*!< TSPEN (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGHDRCAP_TSLEN_Pos (2UL) /*!< TSLEN (Bit 2) */ + #define R_I3C0_CGHDRCAP_TSLEN_Msk (0x4UL) /*!< TSLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HQSTLV ========================================================= */ + #define R_I3C0_HQSTLV_CMDQLV_Pos (0UL) /*!< CMDQLV (Bit 0) */ + #define R_I3C0_HQSTLV_CMDQLV_Msk (0xffUL) /*!< CMDQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_HQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== HDBSTLV ======================================================== */ + #define R_I3C0_HDBSTLV_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_HDBSTLV_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_HDBSTLV_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_HDBSTLV_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ +/* ======================================================== SC1CPT ========================================================= */ + #define R_I3C0_SC1CPT_SC1C_Pos (0UL) /*!< SC1C (Bit 0) */ + #define R_I3C0_SC1CPT_SC1C_Msk (0xffffUL) /*!< SC1C (Bitfield-Mask: 0xffff) */ +/* ======================================================== SC2CPT ========================================================= */ + #define R_I3C0_SC2CPT_SC2C_Pos (0UL) /*!< SC2C (Bit 0) */ + #define R_I3C0_SC2CPT_SC2C_Msk (0xffffUL) /*!< SC2C (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================= OADPT ========================================================= */ + #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */ + #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */ + #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */ +/* ======================================================= LSMRWDIS ======================================================== */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */ + #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */ + #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */ + #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */ + #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_R64OVF_Pos (7UL) /*!< R64OVF (Bit 7) */ + #define R_RTC_R64CNT_R64OVF_Msk (0x80UL) /*!< R64OVF (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_FHZ_Pos (0UL) /*!< FHZ (Bit 0) */ + #define R_RTC_R64CNT_FHZ_Msk (0x1UL) /*!< FHZ (Bitfield-Mask: 0x01) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ +/* ========================================================= RADJ2 ========================================================= */ + #define R_RTC_RADJ2_FADJ_Pos (5UL) /*!< FADJ (Bit 5) */ + #define R_RTC_RADJ2_FADJ_Msk (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_MANC ======================================================== */ + #define R_SCI0_SSR_MANC_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_MANC_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_MANC_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_MANC_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_MANC_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_MANC_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_MANC_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MANC_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MANC_MER_Pos (0UL) /*!< MER (Bit 0) */ + #define R_SCI0_SSR_MANC_MER_Msk (0x1UL) /*!< MER (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ======================================================= TDRHL_MAN ======================================================= */ + #define R_SCI0_TDRHL_MAN_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDRHL_MAN_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDRHL_MAN_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDRHL_MAN_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI0_TDRHL_MAN_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================= RDRHL_MAN ======================================================= */ + #define R_SCI0_RDRHL_MAN_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDRHL_MAN_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDRHL_MAN_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDRHL_MAN_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Pos (12UL) /*!< RSYNC (Bit 12) */ + #define R_SCI0_RDRHL_MAN_RSYNC_Msk (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ +/* ======================================================= SCIMSKEN ======================================================== */ + #define R_SCI0_SCIMSKEN_MSKEN_Pos (0UL) /*!< MSKEN (Bit 0) */ + #define R_SCI0_SCIMSKEN_MSKEN_Msk (0x1UL) /*!< MSKEN (Bitfield-Mask: 0x01) */ +/* ========================================================== MMR ========================================================== */ + #define R_SCI0_MMR_MANEN_Pos (7UL) /*!< MANEN (Bit 7) */ + #define R_SCI0_MMR_MANEN_Msk (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI0_MMR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI0_MMR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI0_MMR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI0_MMR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI0_MMR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_MMR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI0_MMR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ +/* ========================================================= TMPR ========================================================== */ + #define R_SCI0_TMPR_TPLEN_Pos (0UL) /*!< TPLEN (Bit 0) */ + #define R_SCI0_TMPR_TPLEN_Msk (0xfUL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_TMPR_TPPAT_Pos (4UL) /*!< TPPAT (Bit 4) */ + #define R_SCI0_TMPR_TPPAT_Msk (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= RMPR ========================================================== */ + #define R_SCI0_RMPR_RPLEN_Pos (0UL) /*!< RPLEN (Bit 0) */ + #define R_SCI0_RMPR_RPLEN_Msk (0xfUL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI0_RMPR_RPPAT_Pos (4UL) /*!< RPPAT (Bit 4) */ + #define R_SCI0_RMPR_RPPAT_Msk (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ +/* ========================================================= MESR ========================================================== */ + #define R_SCI0_MESR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI0_MESR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI0_MESR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI0_MESR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI0_MESR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ +/* ========================================================= MECR ========================================================== */ + #define R_SCI0_MECR_PFEREN_Pos (0UL) /*!< PFEREN (Bit 0) */ + #define R_SCI0_MECR_PFEREN_Msk (0x1UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SYEREN_Pos (1UL) /*!< SYEREN (Bit 1) */ + #define R_SCI0_MECR_SYEREN_Msk (0x2UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI0_MECR_SBEREN_Pos (2UL) /*!< SBEREN (Bit 2) */ + #define R_SCI0_MECR_SBEREN_Msk (0x4UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMPRCR_NS ====================================================== */ + #define R_SRAM_SRAMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_SRAM_SRAMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_SRAM_SRAMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================= SRAMWTSC ======================================================== */ + #define R_SRAM_SRAMWTSC_WTEN_Pos (0UL) /*!< WTEN (Bit 0) */ + #define R_SRAM_SRAMWTSC_WTEN_Msk (0x1UL) /*!< WTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR0 ======================================================== */ + #define R_SRAM_SRAMCR0_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR0_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR0_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR0_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR0_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR0_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR0_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR1 ======================================================== */ + #define R_SRAM_SRAMCR1_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR1_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR1_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR1_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR1_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR1_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR1_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR1_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR2 ======================================================== */ + #define R_SRAM_SRAMCR2_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR2_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR2_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR2_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR2_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR2_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR2_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR2_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMCR3 ======================================================== */ + #define R_SRAM_SRAMCR3_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_SRAMCR3_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR3_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_SRAM_SRAMCR3_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_SRAM_SRAMCR3_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_SRAM_SRAMCR3_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMCR3_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_SRAM_SRAMCR3_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMECCRGN0 ====================================================== */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN1 ====================================================== */ + #define R_SRAM_SRAMECCRGN1_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN1_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN2 ====================================================== */ + #define R_SRAM_SRAMECCRGN2_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN2_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ====================================================== SRAMECCRGN3 ====================================================== */ + #define R_SRAM_SRAMECCRGN3_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */ + #define R_SRAM_SRAMECCRGN3_ECCRGN_Msk (0x7UL) /*!< ECCRGN (Bitfield-Mask: 0x07) */ +/* ======================================================== SRAMESR ======================================================== */ + #define R_SRAM_SRAMESR_ERR0_Pos (0UL) /*!< ERR0 (Bit 0) */ + #define R_SRAM_SRAMESR_ERR0_Msk (0x1UL) /*!< ERR0 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESR_ERR1_Pos (1UL) /*!< ERR1 (Bit 1) */ + #define R_SRAM_SRAMESR_ERR1_Msk (0x2UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMESCLR ======================================================= */ + #define R_SRAM_SRAMESCLR_CLR0_Pos (0UL) /*!< CLR0 (Bit 0) */ + #define R_SRAM_SRAMESCLR_CLR0_Msk (0x1UL) /*!< CLR0 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMESCLR_CLR1_Pos (1UL) /*!< CLR1 (Bit 1) */ + #define R_SRAM_SRAMESCLR_CLR1_Msk (0x2UL) /*!< CLR1 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMEAR00 ======================================================= */ + #define R_SRAM_SRAMEAR00_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR00_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR10 ======================================================= */ + #define R_SRAM_SRAMEAR10_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR10_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR20 ======================================================= */ + #define R_SRAM_SRAMEAR20_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR20_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR30 ======================================================= */ + #define R_SRAM_SRAMEAR30_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR30_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR01 ======================================================= */ + #define R_SRAM_SRAMEAR01_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR01_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR11 ======================================================= */ + #define R_SRAM_SRAMEAR11_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR11_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR21 ======================================================= */ + #define R_SRAM_SRAMEAR21_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR21_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRAMEAR31 ======================================================= */ + #define R_SRAM_SRAMEAR31_SRAMEAR_Pos (0UL) /*!< SRAMEAR (Bit 0) */ + #define R_SRAM_SRAMEAR31_SRAMEAR_Msk (0xffffffffUL) /*!< SRAMEAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_OPE_Pos (6UL) /*!< OPE (Bit 6) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x40UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ========================================================= SSCR2 ========================================================= */ + #define R_SYSTEM_SSCR2_SS2FSR_Pos (0UL) /*!< SS2FSR (Bit 0) */ + #define R_SYSTEM_SSCR2_SS2FSR_Msk (0x1UL) /*!< SS2FSR (Bitfield-Mask: 0x01) */ +/* ========================================================= MRSCR ========================================================= */ + #define R_SYSTEM_MRSCR_MRSWCF_Pos (0UL) /*!< MRSWCF (Bit 0) */ + #define R_SYSTEM_MRSCR_MRSWCF_Msk (0x1UL) /*!< MRSWCF (Bitfield-Mask: 0x01) */ +/* ========================================================= VSCR ========================================================== */ + #define R_SYSTEM_VSCR_VSCM_Pos (0UL) /*!< VSCM (Bit 0) */ + #define R_SYSTEM_VSCR_VSCM_Msk (0x7UL) /*!< VSCM (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VSCR_VSCMTSF_Pos (4UL) /*!< VSCMTSF (Bit 4) */ + #define R_SYSTEM_VSCR_VSCMTSF_Msk (0x10UL) /*!< VSCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================== SRMONR ========================================================= */ + #define R_SYSTEM_SRMONR_MON_Pos (0UL) /*!< MON (Bit 0) */ + #define R_SYSTEM_SRMONR_MON_Msk (0x3UL) /*!< MON (Bitfield-Mask: 0x03) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0xfUL) /*!< PCKD (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0xf0UL) /*!< PCKC (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0xf00UL) /*!< PCKB (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0xf000UL) /*!< PCKA (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0xf0000UL) /*!< BCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Pos (20UL) /*!< PCKE (Bit 20) */ + #define R_SYSTEM_SCKDIVCR_PCKE_Msk (0xf00000UL) /*!< PCKE (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0xf000000UL) /*!< ICK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK1_Pos (4UL) /*!< CPUCK1 (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_CPUCK1_Msk (0xf0UL) /*!< CPUCK1 (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_NPUCK_Pos (8UL) /*!< NPUCK (Bit 8) */ + #define R_SYSTEM_SCKDIVCR2_NPUCK_Msk (0xf00UL) /*!< NPUCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCKDIVCR2_MRICK_Pos (12UL) /*!< MRICK (Bit 12) */ + #define R_SYSTEM_SCKDIVCR2_MRICK_Msk (0xf000UL) /*!< MRICK (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKCR_EBCKASEL_Pos (7UL) /*!< EBCKASEL (Bit 7) */ + #define R_SYSTEM_BCKCR_EBCKASEL_Msk (0x80UL) /*!< EBCKASEL (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Pos (4UL) /*!< TRCKSEL (Bit 4) */ + #define R_SYSTEM_TRCKCR_TRCKSEL_Msk (0x10UL) /*!< TRCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== OSCMONR ======================================================== */ + #define R_SYSTEM_OSCMONR_MOCOMON_Pos (1UL) /*!< MOCOMON (Bit 1) */ + #define R_SYSTEM_OSCMONR_MOCOMON_Msk (0x2UL) /*!< MOCOMON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Pos (2UL) /*!< LOCOMON (Bit 2) */ + #define R_SYSTEM_OSCMONR_LOCOMON_Msk (0x4UL) /*!< LOCOMON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Pos (0UL) /*!< PLODIVP (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLODIVP_Msk (0xfUL) /*!< PLODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos (4UL) /*!< PLODIVQ (Bit 4) */ + #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk (0xf0UL) /*!< PLODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Pos (8UL) /*!< PLODIVR (Bit 8) */ + #define R_SYSTEM_PLLCCR2_PLODIVR_Msk (0xf00UL) /*!< PLODIVR (Bitfield-Mask: 0x0f) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2CCR2 ======================================================== */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos (0UL) /*!< PL2ODIVP (Bit 0) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk (0xfUL) /*!< PL2ODIVP (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos (4UL) /*!< PL2ODIVQ (Bit 4) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk (0xf0UL) /*!< PL2ODIVQ (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos (8UL) /*!< PL2ODIVR (Bit 8) */ + #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk (0xf00UL) /*!< PL2ODIVR (Bitfield-Mask: 0x0f) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SCICKDIVCR ======================================================= */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== SCICKCR ======================================================== */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Pos (0UL) /*!< SCICKSEL (Bit 0) */ + #define R_SYSTEM_SCICKCR_SCICKSEL_Msk (0xfUL) /*!< SCICKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SCICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SCICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SPICKDIVCR ======================================================= */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== SPICKCR ======================================================== */ + #define R_SYSTEM_SPICKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SPICKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_SPICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_SPICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCCKDIVCR ======================================================= */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCCKCR ======================================================== */ + #define R_SYSTEM_ADCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ADCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ADCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ADCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0xfUL) /*!< GPTCKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0xfUL) /*!< GPTCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== LCDCKDIVCR ======================================================= */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== LCDCKCR ======================================================== */ + #define R_SYSTEM_LCDCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_LCDCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_LCDCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_LCDCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0xfUL) /*!< USBCKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0xfUL) /*!< OCTACKDIV (Bitfield-Mask: 0x0f) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0xfUL) /*!< CANFDCKDIV (Bitfield-Mask: 0x0f) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0xfUL) /*!< USB60CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== I3CCKDIVCR ======================================================= */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */ + #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0xfUL) /*!< I3CCKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0xfUL) /*!< USBCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0xfUL) /*!< OCTACKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0xfUL) /*!< CANFDCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0xfUL) /*!< I3CCKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCSCR ======================================================== */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos (0UL) /*!< MOSCSOKP (Bit 0) */ + #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk (0x1UL) /*!< MOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOSCR ======================================================== */ + #define R_SYSTEM_HOCOSCR_HOSCSOKP_Pos (0UL) /*!< HOSCSOKP (Bit 0) */ + #define R_SYSTEM_HOCOSCR_HOSCSOKP_Msk (0x1UL) /*!< HOSCSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOSCR ======================================================== */ + #define R_SYSTEM_MOCOSCR_MOCOSOKP_Pos (0UL) /*!< MOCOSOKP (Bit 0) */ + #define R_SYSTEM_MOCOSCR_MOCOSOKP_Msk (0x1UL) /*!< MOCOSOKP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Pos (6UL) /*!< PLLMULNF (Bit 6) */ + #define R_SYSTEM_PLLCCR_PLLMULNF_Msk (0xc0UL) /*!< PLLMULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x1ff00UL) /*!< PLLMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLURF_Pos (4UL) /*!< CLURF (Bit 4) */ + #define R_SYSTEM_RSTSR1_CLURF_Msk (0x10UL) /*!< CLURF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM0RF_Pos (5UL) /*!< LM0RF (Bit 5) */ + #define R_SYSTEM_RSTSR1_LM0RF_Msk (0x20UL) /*!< LM0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CMRF_Pos (14UL) /*!< CMRF (Bit 14) */ + #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */ + #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */ + #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */ + #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */ + #define R_SYSTEM_RSTSR1_NWRF_Msk (0x400000UL) /*!< NWRF (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos (6UL) /*!< PLL2MULNF (Bit 6) */ + #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk (0xc0UL) /*!< PLL2MULNF (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x1ff00UL) /*!< PLL2MUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SYRACCR ======================================================== */ + #define R_SYSTEM_SYRACCR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SYSTEM_SYRACCR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================= BCKADIVCR ======================================================= */ + #define R_SYSTEM_BCKADIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_BCKADIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESWCKDIVCR ======================================================= */ + #define R_SYSTEM_ESWCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESWCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESWPCKDIVCR ====================================================== */ + #define R_SYSTEM_ESWPCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESWPCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ESCCKDIVCR ======================================================= */ + #define R_SYSTEM_ESCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ESCCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ====================================================== ETHPCKDIVCR ====================================================== */ + #define R_SYSTEM_ETHPCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */ + #define R_SYSTEM_ETHPCKDIVCR_CKDIV_Msk (0xfUL) /*!< CKDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCKACR ========================================================= */ + #define R_SYSTEM_BCKACR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_BCKACR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_BCKACR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_BCKACR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BCKACR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_BCKACR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== ESWCKCR ======================================================== */ + #define R_SYSTEM_ESWCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESWCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESWCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESWCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESWCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESWCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= ESWPCKCR ======================================================== */ + #define R_SYSTEM_ESWPCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESWPCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESWPCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESWPCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESWPCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESWPCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== ESCCKCR ======================================================== */ + #define R_SYSTEM_ESCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ESCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ESCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ESCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ESCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ESCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= ETHPCKCR ======================================================== */ + #define R_SYSTEM_ETHPCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_ETHPCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_ETHPCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */ + #define R_SYSTEM_ETHPCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_ETHPCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */ + #define R_SYSTEM_ETHPCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3CR1 ======================================================== */ + #define R_SYSTEM_LVD3CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD3CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD3CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD3CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4CR1 ======================================================== */ + #define R_SYSTEM_LVD4CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD4CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD4CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD4CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5CR1 ======================================================== */ + #define R_SYSTEM_LVD5CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD5CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD5CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD5CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3SR ========================================================= */ + #define R_SYSTEM_LVD3SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD3SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD3SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ +/* ======================================================= CRVSYSCR ======================================================== */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Pos (0UL) /*!< CRVEN (Bit 0) */ + #define R_SYSTEM_CRVSYSCR_CRVEN_Msk (0x1UL) /*!< CRVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSCR ======================================================== */ + #define R_SYSTEM_CPUDSCR_PGD_Pos (0UL) /*!< PGD (Bit 0) */ + #define R_SYSTEM_CPUDSCR_PGD_Msk (0x1UL) /*!< PGD (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCTRGD ======================================================== */ + #define R_SYSTEM_PDCTRGD_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRGD_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRGD_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRGD_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCTRNPU ======================================================== */ + #define R_SYSTEM_PDCTRNPU_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRNPU_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRNPU_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRNPU_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRNPU_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRNPU_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCTRESWM ======================================================= */ + #define R_SYSTEM_PDCTRESWM_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */ + #define R_SYSTEM_PDCTRESWM_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRESWM_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */ + #define R_SYSTEM_PDCTRESWM_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PDCTRESWM_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */ + #define R_SYSTEM_PDCTRESWM_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR0 ======================================================= */ + #define R_SYSTEM_PDRAMSCR0_RKEEP_Pos (0UL) /*!< RKEEP (Bit 0) */ + #define R_SYSTEM_PDRAMSCR0_RKEEP_Msk (0x1UL) /*!< RKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PDRAMSCR1 ======================================================= */ + #define R_SYSTEM_PDRAMSCR1_RKEEP_Pos (0UL) /*!< RKEEP (Bit 0) */ + #define R_SYSTEM_PDRAMSCR1_RKEEP_Msk (0x1UL) /*!< RKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= VBRSABAR ======================================================== */ + #define R_SYSTEM_VBRSABAR_SABA_Pos (0UL) /*!< SABA (Bit 0) */ + #define R_SYSTEM_VBRSABAR_SABA_Msk (0xffffUL) /*!< SABA (Bitfield-Mask: 0xffff) */ +/* ======================================================= VBRPABARS ======================================================= */ + #define R_SYSTEM_VBRPABARS_PABAS_Pos (0UL) /*!< PABAS (Bit 0) */ + #define R_SYSTEM_VBRPABARS_PABAS_Msk (0xffffUL) /*!< PABAS (Bitfield-Mask: 0xffff) */ +/* ====================================================== VBRPABARNS ======================================================= */ + #define R_SYSTEM_VBRPABARNS_PABANS_Pos (0UL) /*!< PABANS (Bit 0) */ + #define R_SYSTEM_VBRPABARNS_PABANS_Msk (0xffffUL) /*!< PABANS (Bitfield-Mask: 0xffff) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC_Pos (10UL) /*!< NONSEC (Bit 10) */ + #define R_SYSTEM_CGFSAR_NONSEC_Msk (0x400UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */ + #define R_SYSTEM_BBFSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_BBFSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC5_Pos (5UL) /*!< NONSEC5 (Bit 5) */ + #define R_SYSTEM_BBFSAR_NONSEC5_Msk (0x20UL) /*!< NONSEC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC6_Pos (6UL) /*!< NONSEC6 (Bit 6) */ + #define R_SYSTEM_BBFSAR_NONSEC6_Msk (0x40UL) /*!< NONSEC6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC7_Pos (7UL) /*!< NONSEC7 (Bit 7) */ + #define R_SYSTEM_BBFSAR_NONSEC7_Msk (0x80UL) /*!< NONSEC7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_BBFSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ +/* ======================================================== PGCSAR ========================================================= */ + #define R_SYSTEM_PGCSAR_NONSEC_Pos (0UL) /*!< NONSEC (Bit 0) */ + #define R_SYSTEM_PGCSAR_NONSEC_Msk (0x1UL) /*!< NONSEC (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA_Pos (0UL) /*!< DPFSA (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA_Msk (0x1UL) /*!< DPFSA (Bitfield-Mask: 0x01) */ +/* ======================================================== RSCSAR ========================================================= */ + #define R_SYSTEM_RSCSAR_RSCSA_Pos (0UL) /*!< RSCSA (Bit 0) */ + #define R_SYSTEM_RSCSAR_RSCSA_Msk (0x1UL) /*!< RSCSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR1 ======================================================== */ + #define R_SYSTEM_DPFSAR1_DPFSA_Pos (0UL) /*!< DPFSA (Bit 0) */ + #define R_SYSTEM_DPFSAR1_DPFSA_Msk (0x1UL) /*!< DPFSA (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC5_Pos (5UL) /*!< PRC5 (Bit 5) */ + #define R_SYSTEM_PRCR_PRC5_Msk (0x20UL) /*!< PRC5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== PRCR_NS ======================================================== */ + #define R_SYSTEM_PRCR_NS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_NS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_NS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_NS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_NS_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_NS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SOMRG ========================================================= */ + #define R_SYSTEM_SOMRG_SOSCMRG_Pos (0UL) /*!< SOSCMRG (Bit 0) */ + #define R_SYSTEM_SOMRG_SOSCMRG_Msk (0x3UL) /*!< SOSCMRG (Bitfield-Mask: 0x03) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos (2UL) /*!< DCSSMODE (Bit 2) */ + #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk (0xcUL) /*!< DCSSMODE (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Pos (0UL) /*!< DPVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DPVD1IE_Msk (0x1UL) /*!< DPVD1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Pos (1UL) /*!< DPVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DPVD2IE_Msk (0x2UL) /*!< DPVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCIIE_Pos (2UL) /*!< DRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DRTCIIE_Msk (0x4UL) /*!< DRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DPVD3IE_Pos (5UL) /*!< DPVD3IE (Bit 5) */ + #define R_SYSTEM_DPSIER2_DPVD3IE_Msk (0x20UL) /*!< DPVD3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Pos (2UL) /*!< DULPT0IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DULPT0IE_Msk (0x4UL) /*!< DULPT0IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Pos (3UL) /*!< DULPT1IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DULPT1IE_Msk (0x8UL) /*!< DULPT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Pos (5UL) /*!< DIWDTIE (Bit 5) */ + #define R_SYSTEM_DPSIER3_DIWDTIE_Msk (0x20UL) /*!< DIWDTIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DSOSTDIE_Pos (6UL) /*!< DSOSTDIE (Bit 6) */ + #define R_SYSTEM_DPSIER3_DSOSTDIE_Msk (0x40UL) /*!< DSOSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos (7UL) /*!< DVBATTADIE (Bit 7) */ + #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk (0x80UL) /*!< DVBATTADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos (0UL) /*!< DPVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk (0x1UL) /*!< DPVD1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos (1UL) /*!< DPVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk (0x2UL) /*!< DPVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCIIF_Pos (2UL) /*!< DRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DRTCIIF_Msk (0x4UL) /*!< DRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DPVD3IF_Pos (5UL) /*!< DPVD3IF (Bit 5) */ + #define R_SYSTEM_DPSIFR2_DPVD3IF_Msk (0x20UL) /*!< DPVD3IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos (2UL) /*!< DULPT0IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk (0x4UL) /*!< DULPT0IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos (3UL) /*!< DULPT1IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk (0x8UL) /*!< DULPT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos (5UL) /*!< DIWDTIF (Bit 5) */ + #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk (0x20UL) /*!< DIWDTIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DSOSTDIF_Pos (6UL) /*!< DSOSTDIF (Bit 6) */ + #define R_SYSTEM_DPSIFR3_DSOSTDIF_Msk (0x40UL) /*!< DSOSTDIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos (7UL) /*!< DVBATTADIF (Bit 7) */ + #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk (0x80UL) /*!< DVBATTADIF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD3IEG_Pos (5UL) /*!< DLVD3IEG (Bit 5) */ + #define R_SYSTEM_DPSIEGR2_DLVD3IEG_Msk (0x20UL) /*!< DLVD3IEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR3 ======================================================== */ + #define R_SYSTEM_DPSIEGR3_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR3_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Pos (5UL) /*!< LVD4RF (Bit 5) */ + #define R_SYSTEM_RSTSR0_LVD4RF_Msk (0x20UL) /*!< LVD4RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Pos (6UL) /*!< LVD5RF (Bit 6) */ + #define R_SYSTEM_RSTSR0_LVD5RF_Msk (0x40UL) /*!< LVD5RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR3 ========================================================= */ + #define R_SYSTEM_RSTSR3_CVMRF_Pos (0UL) /*!< CVMRF (Bit 0) */ + #define R_SYSTEM_RSTSR3_CVMRF_Msk (0x1UL) /*!< CVMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR3_OCPRF_Pos (4UL) /*!< OCPRF (Bit 4) */ + #define R_SYSTEM_RSTSR3_OCPRF_Msk (0x10UL) /*!< OCPRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR3_TEMPRF_Pos (7UL) /*!< TEMPRF (Bit 7) */ + #define R_SYSTEM_RSTSR3_TEMPRF_Msk (0x80UL) /*!< TEMPRF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (1UL) /*!< MODRV0 (Bit 1) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0xeUL) /*!< MODRV0 (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD3CMPCR ======================================================= */ + #define R_SYSTEM_LVD3CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD3CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD3CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD3CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD4CMPCR ======================================================= */ + #define R_SYSTEM_LVD4CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD4CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD4CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD4CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD5CMPCR ======================================================= */ + #define R_SYSTEM_LVD5CMPCR_LVDLVL_Pos (0UL) /*!< LVDLVL (Bit 0) */ + #define R_SYSTEM_LVD5CMPCR_LVDLVL_Msk (0x1fUL) /*!< LVDLVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD5CMPCR_LVDE_Pos (7UL) /*!< LVDE (Bit 7) */ + #define R_SYSTEM_LVD5CMPCR_LVDE_Msk (0x80UL) /*!< LVDE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3CR0 ======================================================== */ + #define R_SYSTEM_LVD3CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD3CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD3CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD3CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD3CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD3CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD3CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD3CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD3CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4CR0 ======================================================== */ + #define R_SYSTEM_LVD4CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD4CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD4CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD4CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD4CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD4CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD4CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD4CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD4CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5CR0 ======================================================== */ + #define R_SYSTEM_LVD5CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD5CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD5CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD5CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD5CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD5CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD5CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD5CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD5CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR1 ======================================================== */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSCR ========================================================= */ + #define R_SYSTEM_LPSCR_LPMD_Pos (0UL) /*!< LPMD (Bit 0) */ + #define R_SYSTEM_LPSCR_LPMD_Msk (0xfUL) /*!< LPMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= SSCR1 ========================================================= */ + #define R_SYSTEM_SSCR1_SS2FR_Pos (0UL) /*!< SS2FR (Bit 0) */ + #define R_SYSTEM_SSCR1_SS2FR_Msk (0x1UL) /*!< SS2FR (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SSCR1_SS2LP_Pos (2UL) /*!< SS2LP (Bit 2) */ + #define R_SYSTEM_SSCR1_SS2LP_Msk (0xcUL) /*!< SS2LP (Bitfield-Mask: 0x03) */ +/* ========================================================= SVSCR ========================================================= */ + #define R_SYSTEM_SVSCR_SVSCM_Pos (0UL) /*!< SVSCM (Bit 0) */ + #define R_SYSTEM_SVSCR_SVSCM_Msk (0x7UL) /*!< SVSCM (Bitfield-Mask: 0x07) */ +/* ========================================================= LVOCR ========================================================= */ + #define R_SYSTEM_LVOCR_LVO0E_Pos (0UL) /*!< LVO0E (Bit 0) */ + #define R_SYSTEM_LVOCR_LVO0E_Msk (0x1UL) /*!< LVO0E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVOCR_LVO1E_Pos (1UL) /*!< LVO1E (Bit 1) */ + #define R_SYSTEM_LVOCR_LVO1E_Msk (0x2UL) /*!< LVO1E (Bitfield-Mask: 0x01) */ +/* ========================================================= MWMCR ========================================================= */ + #define R_SYSTEM_MWMCR_MWM_Pos (0UL) /*!< MWM (Bit 0) */ + #define R_SYSTEM_MWMCR_MWM_Msk (0x3UL) /*!< MWM (Bitfield-Mask: 0x03) */ +/* ======================================================= SYRSTMSK0 ======================================================= */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos (0UL) /*!< IWDTMASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk (0x1UL) /*!< IWDTMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos (1UL) /*!< WDT0MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk (0x2UL) /*!< WDT0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos (2UL) /*!< SWMASK (Bit 2) */ + #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk (0x4UL) /*!< SWMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CLU0MASK_Pos (4UL) /*!< CLU0MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK0_CLU0MASK_Msk (0x10UL) /*!< CLU0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos (5UL) /*!< LM0MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk (0x20UL) /*!< LM0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos (6UL) /*!< CMMASK (Bit 6) */ + #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk (0x40UL) /*!< CMMASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */ + #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK1 ======================================================= */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_CLU1MASK_Pos (4UL) /*!< CLU1MASK (Bit 4) */ + #define R_SYSTEM_SYRSTMSK1_CLU1MASK_Msk (0x10UL) /*!< CLU1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */ + #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */ +/* ======================================================= SYRSTMSK2 ======================================================= */ + #define R_SYSTEM_SYRSTMSK2_PVD1MASK_Pos (0UL) /*!< PVD1MASK (Bit 0) */ + #define R_SYSTEM_SYRSTMSK2_PVD1MASK_Msk (0x1UL) /*!< PVD1MASK (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYRSTMSK2_PVD2MASK_Pos (1UL) /*!< PVD2MASK (Bit 1) */ + #define R_SYSTEM_SYRSTMSK2_PVD2MASK_Msk (0x2UL) /*!< PVD2MASK (Bitfield-Mask: 0x01) */ +/* ======================================================== TEMPRCR ======================================================== */ + #define R_SYSTEM_TEMPRCR_TEMPREN_Pos (0UL) /*!< TEMPREN (Bit 0) */ + #define R_SYSTEM_TEMPRCR_TEMPREN_Msk (0x1UL) /*!< TEMPREN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_TSNEN_Pos (1UL) /*!< TSNEN (Bit 1) */ + #define R_SYSTEM_TEMPRCR_TSNEN_Msk (0x2UL) /*!< TSNEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_CMPEN_Pos (2UL) /*!< CMPEN (Bit 2) */ + #define R_SYSTEM_TEMPRCR_CMPEN_Msk (0x4UL) /*!< CMPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TEMPRCR_TSNKEEP_Pos (3UL) /*!< TSNKEEP (Bit 3) */ + #define R_SYSTEM_TEMPRCR_TSNKEEP_Msk (0x8UL) /*!< TSNKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== TEMPRLR ======================================================== */ + #define R_SYSTEM_TEMPRLR_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_SYSTEM_TEMPRLR_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL1LDOCR ======================================================= */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL2LDOCR ======================================================= */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================= HOCOLDOCR ======================================================= */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */ + #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */ + #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOMCR2 ========================================================= */ + #define R_SYSTEM_MOMCR2_MOMODE_Pos (0UL) /*!< MOMODE (Bit 0) */ + #define R_SYSTEM_MOMCR2_MOMODE_Msk (0x1UL) /*!< MOMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1FCR ======================================================== */ + #define R_SYSTEM_LVD1FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD1FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2FCR ======================================================== */ + #define R_SYSTEM_LVD2FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD2FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD3FCR ======================================================== */ + #define R_SYSTEM_LVD3FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD3FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD4FCR ======================================================== */ + #define R_SYSTEM_LVD4FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD4FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD5FCR ======================================================== */ + #define R_SYSTEM_LVD5FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */ + #define R_SYSTEM_LVD5FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= PVDLR ========================================================= */ + #define R_SYSTEM_PVDLR_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_SYSTEM_PVDLR_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER4 ======================================================== */ + #define R_SYSTEM_DPSIER4_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER4_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER5 ======================================================== */ + #define R_SYSTEM_DPSIER5_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER5_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR4 ======================================================== */ + #define R_SYSTEM_DPSIFR4_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR4_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR5 ======================================================== */ + #define R_SYSTEM_DPSIFR5_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR5_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR4 ======================================================== */ + #define R_SYSTEM_DPSIEGR4_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR4_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTSWMON ======================================================== */ + #define R_SYSTEM_VBTSWMON_VLVLMON_Pos (0UL) /*!< VLVLMON (Bit 0) */ + #define R_SYSTEM_VBTSWMON_VLVLMON_Msk (0x7UL) /*!< VLVLMON (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTSWMON_VDETEMON_Pos (4UL) /*!< VDETEMON (Bit 4) */ + #define R_SYSTEM_VBTSWMON_VDETEMON_Msk (0x10UL) /*!< VDETEMON (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTSWSCR ======================================================== */ + #define R_SYSTEM_VBTSWSCR_VBTSWE_Pos (0UL) /*!< VBTSWE (Bit 0) */ + #define R_SYSTEM_VBTSWSCR_VBTSWE_Msk (0x1UL) /*!< VBTSWE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_SOMCR_SOSEL_Pos (6UL) /*!< SOSEL (Bit 6) */ + #define R_SYSTEM_SOMCR_SOSEL_Msk (0x40UL) /*!< SOSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSTDCR ======================================================== */ + #define R_SYSTEM_SOSTDCR_SOSTDIE_Pos (0UL) /*!< SOSTDIE (Bit 0) */ + #define R_SYSTEM_SOSTDCR_SOSTDIE_Msk (0x1UL) /*!< SOSTDIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOSTDCR_SOSTDE_Pos (7UL) /*!< SOSTDE (Bit 7) */ + #define R_SYSTEM_SOSTDCR_SOSTDE_Msk (0x80UL) /*!< SOSTDE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSTDSR ======================================================== */ + #define R_SYSTEM_SOSTDSR_SOSTDF_Pos (0UL) /*!< SOSTDF (Bit 0) */ + #define R_SYSTEM_SOSTDSR_SOSTDF_Msk (0x1UL) /*!< SOSTDF (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTBPCR2 ======================================================== */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos (0UL) /*!< VDETLVL (Bit 0) */ + #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk (0x7UL) /*!< VDETLVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Pos (4UL) /*!< VDETE (Bit 4) */ + #define R_SYSTEM_VBTBPCR2_VDETE_Msk (0x10UL) /*!< VDETE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBPSR ======================================================== */ + #define R_SYSTEM_VBTBPSR_VBPORF_Pos (0UL) /*!< VBPORF (Bit 0) */ + #define R_SYSTEM_VBTBPSR_VBPORF_Msk (0x1UL) /*!< VBPORF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Pos (4UL) /*!< VBPORM (Bit 4) */ + #define R_SYSTEM_VBTBPSR_VBPORM_Msk (0x10UL) /*!< VBPORM (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Pos (5UL) /*!< BPWSWM (Bit 5) */ + #define R_SYSTEM_VBTBPSR_BPWSWM_Msk (0x20UL) /*!< BPWSWM (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTADSR ======================================================== */ + #define R_SYSTEM_VBTADSR_VBTADF0_Pos (0UL) /*!< VBTADF0 (Bit 0) */ + #define R_SYSTEM_VBTADSR_VBTADF0_Msk (0x1UL) /*!< VBTADF0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Pos (1UL) /*!< VBTADF1 (Bit 1) */ + #define R_SYSTEM_VBTADSR_VBTADF1_Msk (0x2UL) /*!< VBTADF1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Pos (2UL) /*!< VBTADF2 (Bit 2) */ + #define R_SYSTEM_VBTADSR_VBTADF2_Msk (0x4UL) /*!< VBTADF2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR1 ======================================================== */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos (0UL) /*!< VBTADIE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk (0x1UL) /*!< VBTADIE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos (1UL) /*!< VBTADIE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk (0x2UL) /*!< VBTADIE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos (2UL) /*!< VBTADIE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk (0x4UL) /*!< VBTADIE2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos (4UL) /*!< VBTADCLE0 (Bit 4) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk (0x10UL) /*!< VBTADCLE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos (5UL) /*!< VBTADCLE1 (Bit 5) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk (0x20UL) /*!< VBTADCLE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos (6UL) /*!< VBTADCLE2 (Bit 6) */ + #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk (0x40UL) /*!< VBTADCLE2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTADCR2 ======================================================== */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos (0UL) /*!< VBRTCES0 (Bit 0) */ + #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk (0x1UL) /*!< VBRTCES0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos (1UL) /*!< VBRTCES1 (Bit 1) */ + #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk (0x2UL) /*!< VBRTCES1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos (2UL) /*!< VBRTCES2 (Bit 2) */ + #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk (0x4UL) /*!< VBRTCES2 (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR2 ======================================================= */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos (0UL) /*!< VCH0NCE (Bit 0) */ + #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk (0x1UL) /*!< VCH0NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos (1UL) /*!< VCH1NCE (Bit 1) */ + #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk (0x2UL) /*!< VCH1NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos (2UL) /*!< VCH2NCE (Bit 2) */ + #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk (0x4UL) /*!< VCH2NCE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos (4UL) /*!< VCH0EG (Bit 4) */ + #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk (0x10UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos (5UL) /*!< VCH1EG (Bit 5) */ + #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk (0x20UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos (6UL) /*!< VCH2EG (Bit 6) */ + #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk (0x40UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTIMONR ======================================================== */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Pos (0UL) /*!< VCH0MON (Bit 0) */ + #define R_SYSTEM_VBTIMONR_VCH0MON_Msk (0x1UL) /*!< VCH0MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Pos (1UL) /*!< VCH1MON (Bit 1) */ + #define R_SYSTEM_VBTIMONR_VCH1MON_Msk (0x2UL) /*!< VCH1MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Pos (2UL) /*!< VCH2MON (Bit 2) */ + #define R_SYSTEM_VBTIMONR_VCH2MON_Msk (0x4UL) /*!< VCH2MON (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTNCWCR ======================================================== */ + #define R_SYSTEM_VBTNCWCR_VINCW_Pos (0UL) /*!< VINCW (Bit 0) */ + #define R_SYSTEM_VBTNCWCR_VINCW_Msk (0x7UL) /*!< VINCW (Bitfield-Mask: 0x07) */ +/* ======================================================= VBTADCR3 ======================================================== */ + #define R_SYSTEM_VBTADCR3_VBTADZE0_Pos (0UL) /*!< VBTADZE0 (Bit 0) */ + #define R_SYSTEM_VBTADCR3_VBTADZE0_Msk (0x1UL) /*!< VBTADZE0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR3_VBTADZE1_Pos (1UL) /*!< VBTADZE1 (Bit 1) */ + #define R_SYSTEM_VBTADCR3_VBTADZE1_Msk (0x2UL) /*!< VBTADZE1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTADCR3_VBTADZE2_Pos (2UL) /*!< VBTADZE2 (Bit 2) */ + #define R_SYSTEM_VBTADCR3_VBTADZE2_Msk (0x4UL) /*!< VBTADZE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DVCHGR ========================================================= */ + #define R_USB_FS0_DVCHGR_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_DVCHGR_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0xf00UL) /*!< STSRECOV0 (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_VIN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MC =========================================================== */ + #define R_VIN_MC_ME_Pos (0UL) /*!< ME (Bit 0) */ + #define R_VIN_MC_ME_Msk (0x1UL) /*!< ME (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_BPS_Pos (1UL) /*!< BPS (Bit 1) */ + #define R_VIN_MC_BPS_Msk (0x2UL) /*!< BPS (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_IM_Pos (3UL) /*!< IM (Bit 3) */ + #define R_VIN_MC_IM_Msk (0x18UL) /*!< IM (Bitfield-Mask: 0x03) */ + #define R_VIN_MC_EN_Pos (6UL) /*!< EN (Bit 6) */ + #define R_VIN_MC_EN_Msk (0x40UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_DC_Pos (14UL) /*!< DC (Bit 14) */ + #define R_VIN_MC_DC_Msk (0xc000UL) /*!< DC (Bitfield-Mask: 0x03) */ + #define R_VIN_MC_INF_Pos (16UL) /*!< INF (Bit 16) */ + #define R_VIN_MC_INF_Msk (0x70000UL) /*!< INF (Bitfield-Mask: 0x07) */ + #define R_VIN_MC_LUTE_Pos (20UL) /*!< LUTE (Bit 20) */ + #define R_VIN_MC_LUTE_Msk (0x100000UL) /*!< LUTE (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_ST_Pos (22UL) /*!< ST (Bit 22) */ + #define R_VIN_MC_ST_Msk (0x400000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_DC2_Pos (24UL) /*!< DC2 (Bit 24) */ + #define R_VIN_MC_DC2_Msk (0x1000000UL) /*!< DC2 (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_YUV444_Pos (25UL) /*!< YUV444 (Bit 25) */ + #define R_VIN_MC_YUV444_Msk (0x2000000UL) /*!< YUV444 (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_SCLE_Pos (26UL) /*!< SCLE (Bit 26) */ + #define R_VIN_MC_SCLE_Msk (0x4000000UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_VIN_MC_CLP_Pos (28UL) /*!< CLP (Bit 28) */ + #define R_VIN_MC_CLP_Msk (0x30000000UL) /*!< CLP (Bitfield-Mask: 0x03) */ +/* ========================================================== MS =========================================================== */ + #define R_VIN_MS_CA_Pos (0UL) /*!< CA (Bit 0) */ + #define R_VIN_MS_CA_Msk (0x1UL) /*!< CA (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_AV_Pos (1UL) /*!< AV (Bit 1) */ + #define R_VIN_MS_AV_Msk (0x2UL) /*!< AV (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FS_Pos (2UL) /*!< FS (Bit 2) */ + #define R_VIN_MS_FS_Msk (0x4UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FBS_Pos (3UL) /*!< FBS (Bit 3) */ + #define R_VIN_MS_FBS_Msk (0x18UL) /*!< FBS (Bitfield-Mask: 0x03) */ + #define R_VIN_MS_MA_Pos (16UL) /*!< MA (Bit 16) */ + #define R_VIN_MS_MA_Msk (0x10000UL) /*!< MA (Bitfield-Mask: 0x01) */ + #define R_VIN_MS_FMS_Pos (19UL) /*!< FMS (Bit 19) */ + #define R_VIN_MS_FMS_Msk (0x180000UL) /*!< FMS (Bitfield-Mask: 0x03) */ +/* ========================================================== FC =========================================================== */ + #define R_VIN_FC_CC_Pos (1UL) /*!< CC (Bit 1) */ + #define R_VIN_FC_CC_Msk (0x2UL) /*!< CC (Bitfield-Mask: 0x01) */ +/* ========================================================= SLPRC ========================================================= */ + #define R_VIN_SLPRC_SLPRC_Pos (0UL) /*!< SLPRC (Bit 0) */ + #define R_VIN_SLPRC_SLPRC_Msk (0xfffUL) /*!< SLPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= ELPRC ========================================================= */ + #define R_VIN_ELPRC_ELPRC_Pos (0UL) /*!< ELPRC (Bit 0) */ + #define R_VIN_ELPRC_ELPRC_Msk (0xfffUL) /*!< ELPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= SPPRC ========================================================= */ + #define R_VIN_SPPRC_SPPRC_Pos (0UL) /*!< SPPRC (Bit 0) */ + #define R_VIN_SPPRC_SPPRC_Msk (0xfffUL) /*!< SPPRC (Bitfield-Mask: 0xfff) */ +/* ========================================================= EPPRC ========================================================= */ + #define R_VIN_EPPRC_EPPRC_Pos (0UL) /*!< EPPRC (Bit 0) */ + #define R_VIN_EPPRC_EPPRC_Msk (0xfffUL) /*!< EPPRC (Bitfield-Mask: 0xfff) */ +/* ======================================================= CSI_IFMD ======================================================== */ + #define R_VIN_CSI_IFMD_VC_SEL_Pos (0UL) /*!< VC_SEL (Bit 0) */ + #define R_VIN_CSI_IFMD_VC_SEL_Msk (0xfUL) /*!< VC_SEL (Bitfield-Mask: 0x0f) */ + #define R_VIN_CSI_IFMD_DT_Pos (8UL) /*!< DT (Bit 8) */ + #define R_VIN_CSI_IFMD_DT_Msk (0x3f00UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_VIN_CSI_IFMD_DES0_Pos (25UL) /*!< DES0 (Bit 25) */ + #define R_VIN_CSI_IFMD_DES0_Msk (0x2000000UL) /*!< DES0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CSIFLD ========================================================= */ + #define R_VIN_CSIFLD_FLD_EN_Pos (0UL) /*!< FLD_EN (Bit 0) */ + #define R_VIN_CSIFLD_FLD_EN_Msk (0x1UL) /*!< FLD_EN (Bitfield-Mask: 0x01) */ + #define R_VIN_CSIFLD_FLD_SEL_Pos (4UL) /*!< FLD_SEL (Bit 4) */ + #define R_VIN_CSIFLD_FLD_SEL_Msk (0x30UL) /*!< FLD_SEL (Bitfield-Mask: 0x03) */ + #define R_VIN_CSIFLD_FLD_NUM_Pos (16UL) /*!< FLD_NUM (Bit 16) */ + #define R_VIN_CSIFLD_FLD_NUM_Msk (0x10000UL) /*!< FLD_NUM (Bitfield-Mask: 0x01) */ +/* ========================================================== IS =========================================================== */ + #define R_VIN_IS_IS_Pos (0UL) /*!< IS (Bit 0) */ + #define R_VIN_IS_IS_Msk (0x1fffUL) /*!< IS (Bitfield-Mask: 0x1fff) */ +/* ========================================================== MB1 ========================================================== */ + #define R_VIN_MB1_MB1_Pos (7UL) /*!< MB1 (Bit 7) */ + #define R_VIN_MB1_MB1_Msk (0xffffff80UL) /*!< MB1 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== MB2 ========================================================== */ + #define R_VIN_MB2_MB2_Pos (7UL) /*!< MB2 (Bit 7) */ + #define R_VIN_MB2_MB2_Msk (0xffffff80UL) /*!< MB2 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== MB3 ========================================================== */ + #define R_VIN_MB3_MB3_Pos (7UL) /*!< MB3 (Bit 7) */ + #define R_VIN_MB3_MB3_Msk (0xffffff80UL) /*!< MB3 (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================== LC =========================================================== */ + #define R_VIN_LC_LC_Pos (0UL) /*!< LC (Bit 0) */ + #define R_VIN_LC_LC_Msk (0xfffUL) /*!< LC (Bitfield-Mask: 0xfff) */ +/* ========================================================== IE =========================================================== */ + #define R_VIN_IE_FOE_Pos (0UL) /*!< FOE (Bit 0) */ + #define R_VIN_IE_FOE_Msk (0x1UL) /*!< FOE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_EFE_Pos (1UL) /*!< EFE (Bit 1) */ + #define R_VIN_IE_EFE_Msk (0x2UL) /*!< EFE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_SIE_Pos (2UL) /*!< SIE (Bit 2) */ + #define R_VIN_IE_SIE_Msk (0x4UL) /*!< SIE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FIE_Pos (4UL) /*!< FIE (Bit 4) */ + #define R_VIN_IE_FIE_Msk (0x10UL) /*!< FIE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FME_Pos (5UL) /*!< FME (Bit 5) */ + #define R_VIN_IE_FME_Msk (0x20UL) /*!< FME (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_PRCLIPHEE_Pos (8UL) /*!< PRCLIPHEE (Bit 8) */ + #define R_VIN_IE_PRCLIPHEE_Msk (0x100UL) /*!< PRCLIPHEE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_PRCLIPVEE_Pos (9UL) /*!< PRCLIPVEE (Bit 9) */ + #define R_VIN_IE_PRCLIPVEE_Msk (0x200UL) /*!< PRCLIPVEE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_ROE_Pos (14UL) /*!< ROE (Bit 14) */ + #define R_VIN_IE_ROE_Msk (0x4000UL) /*!< ROE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_AREE_Pos (15UL) /*!< AREE (Bit 15) */ + #define R_VIN_IE_AREE_Msk (0x8000UL) /*!< AREE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_VRE_Pos (16UL) /*!< VRE (Bit 16) */ + #define R_VIN_IE_VRE_Msk (0x10000UL) /*!< VRE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_VFE_Pos (17UL) /*!< VFE (Bit 17) */ + #define R_VIN_IE_VFE_Msk (0x20000UL) /*!< VFE (Bitfield-Mask: 0x01) */ + #define R_VIN_IE_FIE2_Pos (31UL) /*!< FIE2 (Bit 31) */ + #define R_VIN_IE_FIE2_Msk (0x80000000UL) /*!< FIE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTS ========================================================== */ + #define R_VIN_INTS_FOS_Pos (0UL) /*!< FOS (Bit 0) */ + #define R_VIN_INTS_FOS_Msk (0x1UL) /*!< FOS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_EFS_Pos (1UL) /*!< EFS (Bit 1) */ + #define R_VIN_INTS_EFS_Msk (0x2UL) /*!< EFS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_SIS_Pos (2UL) /*!< SIS (Bit 2) */ + #define R_VIN_INTS_SIS_Msk (0x4UL) /*!< SIS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FIS_Pos (4UL) /*!< FIS (Bit 4) */ + #define R_VIN_INTS_FIS_Msk (0x10UL) /*!< FIS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FMS_Pos (5UL) /*!< FMS (Bit 5) */ + #define R_VIN_INTS_FMS_Msk (0x20UL) /*!< FMS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_PRCLIPHES_Pos (8UL) /*!< PRCLIPHES (Bit 8) */ + #define R_VIN_INTS_PRCLIPHES_Msk (0x100UL) /*!< PRCLIPHES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_PRCLIPVES_Pos (9UL) /*!< PRCLIPVES (Bit 9) */ + #define R_VIN_INTS_PRCLIPVES_Msk (0x200UL) /*!< PRCLIPVES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_ROS_Pos (14UL) /*!< ROS (Bit 14) */ + #define R_VIN_INTS_ROS_Msk (0x4000UL) /*!< ROS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_ARES_Pos (15UL) /*!< ARES (Bit 15) */ + #define R_VIN_INTS_ARES_Msk (0x8000UL) /*!< ARES (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_VRS_Pos (16UL) /*!< VRS (Bit 16) */ + #define R_VIN_INTS_VRS_Msk (0x10000UL) /*!< VRS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_VFS_Pos (17UL) /*!< VFS (Bit 17) */ + #define R_VIN_INTS_VFS_Msk (0x20000UL) /*!< VFS (Bitfield-Mask: 0x01) */ + #define R_VIN_INTS_FIS2_Pos (31UL) /*!< FIS2 (Bit 31) */ + #define R_VIN_INTS_FIS2_Msk (0x80000000UL) /*!< FIS2 (Bitfield-Mask: 0x01) */ +/* ========================================================== SI =========================================================== */ + #define R_VIN_SI_SI_Pos (0UL) /*!< SI (Bit 0) */ + #define R_VIN_SI_SI_Msk (0xfffUL) /*!< SI (Bitfield-Mask: 0xfff) */ +/* ======================================================== MTCSTOP ======================================================== */ + #define R_VIN_MTCSTOP_STOPREQ_Pos (0UL) /*!< STOPREQ (Bit 0) */ + #define R_VIN_MTCSTOP_STOPREQ_Msk (0x1UL) /*!< STOPREQ (Bitfield-Mask: 0x01) */ + #define R_VIN_MTCSTOP_STOPACK_Pos (1UL) /*!< STOPACK (Bit 1) */ + #define R_VIN_MTCSTOP_STOPACK_Msk (0x2UL) /*!< STOPACK (Bitfield-Mask: 0x01) */ + #define R_VIN_MTCSTOP_OUTSTAND_Pos (16UL) /*!< OUTSTAND (Bit 16) */ + #define R_VIN_MTCSTOP_OUTSTAND_Msk (0x3f0000UL) /*!< OUTSTAND (Bitfield-Mask: 0x3f) */ +/* ========================================================== DMR ========================================================== */ + #define R_VIN_DMR_DTMD_Pos (0UL) /*!< DTMD (Bit 0) */ + #define R_VIN_DMR_DTMD_Msk (0x3UL) /*!< DTMD (Bitfield-Mask: 0x03) */ + #define R_VIN_DMR_ABIT_Pos (2UL) /*!< ABIT (Bit 2) */ + #define R_VIN_DMR_ABIT_Msk (0x4UL) /*!< ABIT (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_BPSM_Pos (4UL) /*!< BPSM (Bit 4) */ + #define R_VIN_DMR_BPSM_Msk (0x10UL) /*!< BPSM (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_EXRGB_Pos (8UL) /*!< EXRGB (Bit 8) */ + #define R_VIN_DMR_EXRGB_Msk (0x100UL) /*!< EXRGB (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_YC_THR_Pos (11UL) /*!< YC_THR (Bit 11) */ + #define R_VIN_DMR_YC_THR_Msk (0x800UL) /*!< YC_THR (Bitfield-Mask: 0x01) */ + #define R_VIN_DMR_YMODE_Pos (12UL) /*!< YMODE (Bit 12) */ + #define R_VIN_DMR_YMODE_Msk (0x7000UL) /*!< YMODE (Bitfield-Mask: 0x07) */ + #define R_VIN_DMR_A8BIT_Pos (24UL) /*!< A8BIT (Bit 24) */ + #define R_VIN_DMR_A8BIT_Msk (0xff000000UL) /*!< A8BIT (Bitfield-Mask: 0xff) */ +/* ========================================================= UVAOF ========================================================= */ + #define R_VIN_UVAOF_UVAOF_Pos (7UL) /*!< UVAOF (Bit 7) */ + #define R_VIN_UVAOF_UVAOF_Msk (0xffffff80UL) /*!< UVAOF (Bitfield-Mask: 0x1ffffff) */ +/* ========================================================= CSCE1 ========================================================= */ + #define R_VIN_CSCE1_YMUL2_Pos (0UL) /*!< YMUL2 (Bit 0) */ + #define R_VIN_CSCE1_YMUL2_Msk (0x3fffUL) /*!< YMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE1_ROUND_Pos (16UL) /*!< ROUND (Bit 16) */ + #define R_VIN_CSCE1_ROUND_Msk (0x10000UL) /*!< ROUND (Bitfield-Mask: 0x01) */ +/* ========================================================= CSCE2 ========================================================= */ + #define R_VIN_CSCE2_CSUB2_Pos (0UL) /*!< CSUB2 (Bit 0) */ + #define R_VIN_CSCE2_CSUB2_Msk (0xfffUL) /*!< CSUB2 (Bitfield-Mask: 0xfff) */ + #define R_VIN_CSCE2_YSUB2_Pos (16UL) /*!< YSUB2 (Bit 16) */ + #define R_VIN_CSCE2_YSUB2_Msk (0xfff0000UL) /*!< YSUB2 (Bitfield-Mask: 0xfff) */ +/* ========================================================= CSCE3 ========================================================= */ + #define R_VIN_CSCE3_GCRMUL2_Pos (0UL) /*!< GCRMUL2 (Bit 0) */ + #define R_VIN_CSCE3_GCRMUL2_Msk (0x3fffUL) /*!< GCRMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE3_RCRMUL2_Pos (16UL) /*!< RCRMUL2 (Bit 16) */ + #define R_VIN_CSCE3_RCRMUL2_Msk (0x3fff0000UL) /*!< RCRMUL2 (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CSCE4 ========================================================= */ + #define R_VIN_CSCE4_BCBMUL2_Pos (0UL) /*!< BCBMUL2 (Bit 0) */ + #define R_VIN_CSCE4_BCBMUL2_Msk (0x3fffUL) /*!< BCBMUL2 (Bitfield-Mask: 0x3fff) */ + #define R_VIN_CSCE4_GCBMUL2_Pos (16UL) /*!< GCBMUL2 (Bit 16) */ + #define R_VIN_CSCE4_GCBMUL2_Msk (0x3fff0000UL) /*!< GCBMUL2 (Bitfield-Mask: 0x3fff) */ +/* ======================================================= UDS_CTRL ======================================================== */ + #define R_VIN_UDS_CTRL_NE_BCB_Pos (16UL) /*!< NE_BCB (Bit 16) */ + #define R_VIN_UDS_CTRL_NE_BCB_Msk (0x10000UL) /*!< NE_BCB (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_NE_GY_Pos (17UL) /*!< NE_GY (Bit 17) */ + #define R_VIN_UDS_CTRL_NE_GY_Msk (0x20000UL) /*!< NE_GY (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_NE_RCR_Pos (18UL) /*!< NE_RCR (Bit 18) */ + #define R_VIN_UDS_CTRL_NE_RCR_Msk (0x40000UL) /*!< NE_RCR (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_BC_Pos (20UL) /*!< BC (Bit 20) */ + #define R_VIN_UDS_CTRL_BC_Msk (0x100000UL) /*!< BC (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_BLADV_Pos (28UL) /*!< BLADV (Bit 28) */ + #define R_VIN_UDS_CTRL_BLADV_Msk (0x10000000UL) /*!< BLADV (Bitfield-Mask: 0x01) */ + #define R_VIN_UDS_CTRL_AMD_Pos (30UL) /*!< AMD (Bit 30) */ + #define R_VIN_UDS_CTRL_AMD_Msk (0x40000000UL) /*!< AMD (Bitfield-Mask: 0x01) */ +/* ======================================================= UDS_SCALE ======================================================= */ + #define R_VIN_UDS_SCALE_VFRAC_Pos (0UL) /*!< VFRAC (Bit 0) */ + #define R_VIN_UDS_SCALE_VFRAC_Msk (0xfffUL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_SCALE_VMANT_Pos (12UL) /*!< VMANT (Bit 12) */ + #define R_VIN_UDS_SCALE_VMANT_Msk (0xf000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ + #define R_VIN_UDS_SCALE_HFRAC_Pos (16UL) /*!< HFRAC (Bit 16) */ + #define R_VIN_UDS_SCALE_HFRAC_Msk (0xfff0000UL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_SCALE_HMANT_Pos (28UL) /*!< HMANT (Bit 28) */ + #define R_VIN_UDS_SCALE_HMANT_Msk (0xf0000000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ +/* ==================================================== UDS_PASS_BWIDTH ==================================================== */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_V_Pos (0UL) /*!< BWIDTH_V (Bit 0) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_V_Msk (0x7fUL) /*!< BWIDTH_V (Bitfield-Mask: 0x7f) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_H_Pos (16UL) /*!< BWIDTH_H (Bit 16) */ + #define R_VIN_UDS_PASS_BWIDTH_BWIDTH_H_Msk (0x7f0000UL) /*!< BWIDTH_H (Bitfield-Mask: 0x7f) */ +/* ===================================================== UDS_CLIP_SIZE ===================================================== */ + #define R_VIN_UDS_CLIP_SIZE_CL_VSIZE_Pos (0UL) /*!< CL_VSIZE (Bit 0) */ + #define R_VIN_UDS_CLIP_SIZE_CL_VSIZE_Msk (0xfffUL) /*!< CL_VSIZE (Bitfield-Mask: 0xfff) */ + #define R_VIN_UDS_CLIP_SIZE_CL_HSIZE_Pos (16UL) /*!< CL_HSIZE (Bit 16) */ + #define R_VIN_UDS_CLIP_SIZE_CL_HSIZE_Msk (0xfff0000UL) /*!< CL_HSIZE (Bitfield-Mask: 0xfff) */ +/* ========================================================= LUTP ========================================================== */ + #define R_VIN_LUTP_LTCRPR_Pos (0UL) /*!< LTCRPR (Bit 0) */ + #define R_VIN_LUTP_LTCRPR_Msk (0x3ffUL) /*!< LTCRPR (Bitfield-Mask: 0x3ff) */ + #define R_VIN_LUTP_LTCBPR_Pos (10UL) /*!< LTCBPR (Bit 10) */ + #define R_VIN_LUTP_LTCBPR_Msk (0xffc00UL) /*!< LTCBPR (Bitfield-Mask: 0x3ff) */ + #define R_VIN_LUTP_LTYPR_Pos (20UL) /*!< LTYPR (Bit 20) */ + #define R_VIN_LUTP_LTYPR_Msk (0x3ff00000UL) /*!< LTYPR (Bitfield-Mask: 0x3ff) */ +/* ========================================================= LUTD ========================================================== */ + #define R_VIN_LUTD_LTCRDT_Pos (0UL) /*!< LTCRDT (Bit 0) */ + #define R_VIN_LUTD_LTCRDT_Msk (0xffUL) /*!< LTCRDT (Bitfield-Mask: 0xff) */ + #define R_VIN_LUTD_LTCBDT_Pos (8UL) /*!< LTCBDT (Bit 8) */ + #define R_VIN_LUTD_LTCBDT_Msk (0xff00UL) /*!< LTCBDT (Bitfield-Mask: 0xff) */ + #define R_VIN_LUTD_LTYDT_Pos (16UL) /*!< LTYDT (Bit 16) */ + #define R_VIN_LUTD_LTYDT_Msk (0xff0000UL) /*!< LTYDT (Bitfield-Mask: 0xff) */ +/* ========================================================= YCCR1 ========================================================= */ + #define R_VIN_YCCR1_YCLRP_Pos (0UL) /*!< YCLRP (Bit 0) */ + #define R_VIN_YCCR1_YCLRP_Msk (0x1fffUL) /*!< YCLRP (Bitfield-Mask: 0x1fff) */ +/* ========================================================= YCCR2 ========================================================= */ + #define R_VIN_YCCR2_YCLGP_Pos (0UL) /*!< YCLGP (Bit 0) */ + #define R_VIN_YCCR2_YCLGP_Msk (0x1fffUL) /*!< YCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_YCCR2_YCLBP_Pos (16UL) /*!< YCLBP (Bit 16) */ + #define R_VIN_YCCR2_YCLBP_Msk (0x1fff0000UL) /*!< YCLBP (Bitfield-Mask: 0x1fff) */ +/* ========================================================= YCCR3 ========================================================= */ + #define R_VIN_YCCR3_YCLAP_Pos (0UL) /*!< YCLAP (Bit 0) */ + #define R_VIN_YCCR3_YCLAP_Msk (0xfffUL) /*!< YCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_YCCR3_YCLHEN_Pos (23UL) /*!< YCLHEN (Bit 23) */ + #define R_VIN_YCCR3_YCLHEN_Msk (0x800000UL) /*!< YCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_YCCR3_YCLSFT_Pos (24UL) /*!< YCLSFT (Bit 24) */ + #define R_VIN_YCCR3_YCLSFT_Msk (0x1f000000UL) /*!< YCLSFT (Bitfield-Mask: 0x1f) */ +/* ======================================================== CBCCR1 ========================================================= */ + #define R_VIN_CBCCR1_CBCLRP_Pos (0UL) /*!< CBCLRP (Bit 0) */ + #define R_VIN_CBCCR1_CBCLRP_Msk (0x1fffUL) /*!< CBCLRP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CBCCR2 ========================================================= */ + #define R_VIN_CBCCR2_CBCLGP_Pos (0UL) /*!< CBCLGP (Bit 0) */ + #define R_VIN_CBCCR2_CBCLGP_Msk (0x1fffUL) /*!< CBCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_CBCCR2_CBCLBP_Pos (16UL) /*!< CBCLBP (Bit 16) */ + #define R_VIN_CBCCR2_CBCLBP_Msk (0x1fff0000UL) /*!< CBCLBP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CBCCR3 ========================================================= */ + #define R_VIN_CBCCR3_CBCLAP_Pos (0UL) /*!< CBCLAP (Bit 0) */ + #define R_VIN_CBCCR3_CBCLAP_Msk (0xfffUL) /*!< CBCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_CBCCR3_CBCLHEN_Pos (23UL) /*!< CBCLHEN (Bit 23) */ + #define R_VIN_CBCCR3_CBCLHEN_Msk (0x800000UL) /*!< CBCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_CBCCR3_CBCLSFT_Pos (24UL) /*!< CBCLSFT (Bit 24) */ + #define R_VIN_CBCCR3_CBCLSFT_Msk (0x1f000000UL) /*!< CBCLSFT (Bitfield-Mask: 0x1f) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_VIN_CRCCR1_CRCLRP_Pos (0UL) /*!< CRCLRP (Bit 0) */ + #define R_VIN_CRCCR1_CRCLRP_Msk (0x1fffUL) /*!< CRCLRP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CRCCR2 ========================================================= */ + #define R_VIN_CRCCR2_CRCLGP_Pos (0UL) /*!< CRCLGP (Bit 0) */ + #define R_VIN_CRCCR2_CRCLGP_Msk (0x1fffUL) /*!< CRCLGP (Bitfield-Mask: 0x1fff) */ + #define R_VIN_CRCCR2_CRCLBP_Pos (16UL) /*!< CRCLBP (Bit 16) */ + #define R_VIN_CRCCR2_CRCLBP_Msk (0x1fff0000UL) /*!< CRCLBP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CRCCR3 ========================================================= */ + #define R_VIN_CRCCR3_CRCLAP_Pos (0UL) /*!< CRCLAP (Bit 0) */ + #define R_VIN_CRCCR3_CRCLAP_Msk (0xfffUL) /*!< CRCLAP (Bitfield-Mask: 0xfff) */ + #define R_VIN_CRCCR3_CRCLHEN_Pos (23UL) /*!< CRCLHEN (Bit 23) */ + #define R_VIN_CRCCR3_CRCLHEN_Msk (0x800000UL) /*!< CRCLHEN (Bitfield-Mask: 0x01) */ + #define R_VIN_CRCCR3_CRCLSFT_Pos (24UL) /*!< CRCLSFT (Bit 24) */ + #define R_VIN_CRCCR3_CRCLSFT_Msk (0x1f000000UL) /*!< CRCLSFT (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCACTL_FC_Pos (8UL) /*!< FC (Bit 8) */ + #define R_CACHE_CCACTL_FC_Msk (0x100UL) /*!< FC (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCACTL_WB_Pos (9UL) /*!< WB (Bit 9) */ + #define R_CACHE_CCACTL_WB_Msk (0x200UL) /*!< WB (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAFCT_WB_Pos (1UL) /*!< WB (Bit 1) */ + #define R_CACHE_CCAFCT_WB_Msk (0x2UL) /*!< WB (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAWTA ========================================================= */ + #define R_CACHE_CCAWTA_WT_Pos (0UL) /*!< WT (Bit 0) */ + #define R_CACHE_CCAWTA_WT_Msk (0x1UL) /*!< WT (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAWTA_WA_Pos (1UL) /*!< WA (Bit 1) */ + #define R_CACHE_CCAWTA_WA_Msk (0x2UL) /*!< WA (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAEDST ======================================================== */ + #define R_CACHE_CCAEDST_ESD0_Pos (0UL) /*!< ESD0 (Bit 0) */ + #define R_CACHE_CCAEDST_ESD0_Msk (0x1UL) /*!< ESD0 (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAEDST_ESD1_Pos (1UL) /*!< ESD1 (Bit 1) */ + #define R_CACHE_CCAEDST_ESD1_Msk (0x2UL) /*!< ESD1 (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAEDST_ESTC_Pos (2UL) /*!< ESTC (Bit 2) */ + #define R_CACHE_CCAEDST_ESTC_Msk (0x4UL) /*!< ESTC (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAEDST_ESTD_Pos (3UL) /*!< ESTD (Bit 3) */ + #define R_CACHE_CCAEDST_ESTD_Msk (0x8UL) /*!< ESTD (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCAEDST_EST2_Pos (4UL) /*!< EST2 (Bit 4) */ + #define R_CACHE_CCAEDST_EST2_Msk (0x10UL) /*!< EST2 (Bitfield-Mask: 0x01) */ +/* ======================================================== CCATAA ========================================================= */ + #define R_CACHE_CCATAA_OFFSET_Pos (2UL) /*!< OFFSET (Bit 2) */ + #define R_CACHE_CCATAA_OFFSET_Msk (0x1cUL) /*!< OFFSET (Bitfield-Mask: 0x07) */ + #define R_CACHE_CCATAA_ENTRY_Pos (5UL) /*!< ENTRY (Bit 5) */ + #define R_CACHE_CCATAA_ENTRY_Msk (0xfe0UL) /*!< ENTRY (Bitfield-Mask: 0x7f) */ + #define R_CACHE_CCATAA_TARGET_Pos (16UL) /*!< TARGET (Bit 16) */ + #define R_CACHE_CCATAA_TARGET_Msk (0x70000UL) /*!< TARGET (Bitfield-Mask: 0x07) */ + #define R_CACHE_CCATAA_RW_Pos (23UL) /*!< RW (Bit 23) */ + #define R_CACHE_CCATAA_RW_Msk (0x800000UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_CACHE_CCATAA_WAY_Pos (30UL) /*!< WAY (Bit 30) */ + #define R_CACHE_CCATAA_WAY_Msk (0xc0000000UL) /*!< WAY (Bitfield-Mask: 0x03) */ +/* ======================================================== CCATAD ========================================================= */ + #define R_CACHE_CCATAD_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CACHE_CCATAD_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCACTL_FS_Pos (8UL) /*!< FS (Bit 8) */ + #define R_CACHE_SCACTL_FS_Msk (0x100UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCACTL_WB_Pos (9UL) /*!< WB (Bit 9) */ + #define R_CACHE_SCACTL_WB_Msk (0x200UL) /*!< WB (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAFCT_WB_Pos (1UL) /*!< WB (Bit 1) */ + #define R_CACHE_SCAFCT_WB_Msk (0x2UL) /*!< WB (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAWTA ========================================================= */ + #define R_CACHE_SCAWTA_WT_Pos (0UL) /*!< WT (Bit 0) */ + #define R_CACHE_SCAWTA_WT_Msk (0x1UL) /*!< WT (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAWTA_WA_Pos (1UL) /*!< WA (Bit 1) */ + #define R_CACHE_SCAWTA_WA_Msk (0x2UL) /*!< WA (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAEDST ======================================================== */ + #define R_CACHE_SCAEDST_ESD0_Pos (0UL) /*!< ESD0 (Bit 0) */ + #define R_CACHE_SCAEDST_ESD0_Msk (0x1UL) /*!< ESD0 (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAEDST_ESD1_Pos (1UL) /*!< ESD1 (Bit 1) */ + #define R_CACHE_SCAEDST_ESD1_Msk (0x2UL) /*!< ESD1 (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAEDST_ESTC_Pos (2UL) /*!< ESTC (Bit 2) */ + #define R_CACHE_SCAEDST_ESTC_Msk (0x4UL) /*!< ESTC (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAEDST_ESTD_Pos (3UL) /*!< ESTD (Bit 3) */ + #define R_CACHE_SCAEDST_ESTD_Msk (0x8UL) /*!< ESTD (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCAEDST_EST2_Pos (4UL) /*!< EST2 (Bit 4) */ + #define R_CACHE_SCAEDST_EST2_Msk (0x10UL) /*!< EST2 (Bitfield-Mask: 0x01) */ +/* ======================================================== SCATAA ========================================================= */ + #define R_CACHE_SCATAA_OFFSET_Pos (2UL) /*!< OFFSET (Bit 2) */ + #define R_CACHE_SCATAA_OFFSET_Msk (0x1cUL) /*!< OFFSET (Bitfield-Mask: 0x07) */ + #define R_CACHE_SCATAA_ENTRY_Pos (5UL) /*!< ENTRY (Bit 5) */ + #define R_CACHE_SCATAA_ENTRY_Msk (0xfe0UL) /*!< ENTRY (Bitfield-Mask: 0x7f) */ + #define R_CACHE_SCATAA_TARGET_Pos (16UL) /*!< TARGET (Bit 16) */ + #define R_CACHE_SCATAA_TARGET_Msk (0x70000UL) /*!< TARGET (Bitfield-Mask: 0x07) */ + #define R_CACHE_SCATAA_RW_Pos (23UL) /*!< RW (Bit 23) */ + #define R_CACHE_SCATAA_RW_Msk (0x800000UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_CACHE_SCATAA_WAY_Pos (30UL) /*!< WAY (Bit 30) */ + #define R_CACHE_SCATAA_WAY_Msk (0xc0000000UL) /*!< WAY (Bitfield-Mask: 0x03) */ +/* ======================================================== SCATAD ========================================================= */ + #define R_CACHE_SCATAD_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CACHE_SCATAD_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPOAD_ECCMOD1_Pos (3UL) /*!< ECCMOD1 (Bit 3) */ + #define R_CACHE_CAPOAD_ECCMOD1_Msk (0x8UL) /*!< ECCMOD1 (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPOAD_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_CACHE_CAPOAD_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA_Pos (0UL) /*!< SRAMSA (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA_Msk (0x1UL) /*!< SRAMSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMWTSA_Pos (8UL) /*!< SRAMWTSA (Bit 8) */ + #define R_CPSCU_SRAMSAR_SRAMWTSA_Msk (0x100UL) /*!< SRAMWTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCR_Pos (0UL) /*!< SAIRQCR (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCR_Msk (0x1UL) /*!< SAIRQCR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */ + #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */ + #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Pos (7UL) /*!< SASOSCWUP (Bit 7) */ + #define R_CPSCU_ICUSARF_SASOSCWUP_Msk (0x80UL) /*!< SASOSCWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */ + #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */ + #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */ + #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */ + #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */ + #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */ + #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */ + #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAPDMWUP_Pos (15UL) /*!< SAPDMWUP (Bit 15) */ + #define R_CPSCU_ICUSARF_SAPDMWUP_Msk (0x8000UL) /*!< SAPDMWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARJ ======================================================== */ + #define R_CPSCU_ICUSARJ_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARJ_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARK ======================================================== */ + #define R_CPSCU_ICUSARK_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARK_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARL ======================================================== */ + #define R_CPSCU_ICUSARL_SAIELSR_Pos (0UL) /*!< SAIELSR (Bit 0) */ + #define R_CPSCU_ICUSARL_SAIELSR_Msk (0x1UL) /*!< SAIELSR (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARC ======================================================== */ + #define R_CPSCU_BUSSARC_BUSSC0_Pos (0UL) /*!< BUSSC0 (Bit 0) */ + #define R_CPSCU_BUSSARC_BUSSC0_Msk (0x1UL) /*!< BUSSC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSPARC ======================================================== */ + #define R_CPSCU_BUSPARC_BUSPA0_Pos (0UL) /*!< BUSPA0 (Bit 0) */ + #define R_CPSCU_BUSPARC_BUSPA0_Msk (0x1UL) /*!< BUSPA0 (Bitfield-Mask: 0x01) */ +/* ========================================================= NMISR ========================================================= */ + #define R_CPSCU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_CPSCU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_CPSCU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_PVD1ST_Pos (2UL) /*!< PVD1ST (Bit 2) */ + #define R_CPSCU_NMISR_PVD1ST_Msk (0x4UL) /*!< PVD1ST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_PVD2ST_Pos (3UL) /*!< PVD2ST (Bit 3) */ + #define R_CPSCU_NMISR_PVD2ST_Msk (0x8UL) /*!< PVD2ST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_SOSTST_Pos (5UL) /*!< SOSTST (Bit 5) */ + #define R_CPSCU_NMISR_SOSTST_Msk (0x20UL) /*!< SOSTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_CPSCU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_CPSCU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */ + #define R_CPSCU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */ + #define R_CPSCU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_LMST_Pos (14UL) /*!< LMST (Bit 14) */ + #define R_CPSCU_NMISR_LMST_Msk (0x4000UL) /*!< LMST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */ + #define R_CPSCU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_FPUEXCST_Pos (16UL) /*!< FPUEXCST (Bit 16) */ + #define R_CPSCU_NMISR_FPUEXCST_Msk (0x10000UL) /*!< FPUEXCST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_MRCRDST_Pos (17UL) /*!< MRCRDST (Bit 17) */ + #define R_CPSCU_NMISR_MRCRDST_Msk (0x20000UL) /*!< MRCRDST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_MRERDST_Pos (18UL) /*!< MRERDST (Bit 18) */ + #define R_CPSCU_NMISR_MRERDST_Msk (0x40000UL) /*!< MRERDST (Bitfield-Mask: 0x01) */ + #define R_CPSCU_NMISR_IPCST_Pos (20UL) /*!< IPCST (Bit 20) */ + #define R_CPSCU_NMISR_IPCST_Msk (0x100000UL) /*!< IPCST (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUASA_Pos (0UL) /*!< MMPUASA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUASA_Msk (0x1UL) /*!< MMPUASA (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUBSA_Pos (0UL) /*!< MMPUBSA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUBSA_Msk (0x1UL) /*!< MMPUBSA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUSAR ========================================================= */ + #define R_CPSCU_CPUSAR_CPUSA_Pos (0UL) /*!< CPUSA (Bit 0) */ + #define R_CPSCU_CPUSAR_CPUSA_Msk (0x1UL) /*!< CPUSA (Bitfield-Mask: 0x01) */ +/* ======================================================= DEBUGSAR ======================================================== */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Pos (0UL) /*!< DBGSA0 (Bit 0) */ + #define R_CPSCU_DEBUGSAR_DBGSA0_Msk (0x1UL) /*!< DBGSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHSAR ======================================================= */ + #define R_CPSCU_DMACCHSAR_SADMAC0_Pos (0UL) /*!< SADMAC0 (Bit 0) */ + #define R_CPSCU_DMACCHSAR_SADMAC0_Msk (0x1UL) /*!< SADMAC0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_DMACCHSAR_SADMAC1_Pos (16UL) /*!< SADMAC1 (Bit 16) */ + #define R_CPSCU_DMACCHSAR_SADMAC1_Msk (0x10000UL) /*!< SADMAC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMACCHPAR ======================================================= */ + #define R_CPSCU_DMACCHPAR_PADMAC0_Pos (0UL) /*!< PADMAC0 (Bit 0) */ + #define R_CPSCU_DMACCHPAR_PADMAC0_Msk (0x1UL) /*!< PADMAC0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_DMACCHPAR_PADMAC1_Pos (16UL) /*!< PADMAC1 (Bit 16) */ + #define R_CPSCU_DMACCHPAR_PADMAC1_Msk (0x10000UL) /*!< PADMAC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== SRAMSABAR0 ======================================================= */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR1 ======================================================= */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR2 ======================================================= */ + #define R_CPSCU_SRAMSABAR2_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR2_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ====================================================== SRAMSABAR3 ======================================================= */ + #define R_CPSCU_SRAMSABAR3_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */ + #define R_CPSCU_SRAMSABAR3_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */ +/* ======================================================= CACHESAR ======================================================== */ + #define R_CPSCU_CACHESAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CACHESAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CACHESAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CACHESAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMSAR ========================================================= */ + #define R_CPSCU_TCMSAR_TCMSA_Pos (0UL) /*!< TCMSA (Bit 0) */ + #define R_CPSCU_TCMSAR_TCMSA_Msk (0x1UL) /*!< TCMSA (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMSABARC ======================================================= */ + #define R_CPSCU_TCMSABARC_TCMSABA_Pos (13UL) /*!< TCMSABA (Bit 13) */ + #define R_CPSCU_TCMSABARC_TCMSABA_Msk (0x7e000UL) /*!< TCMSABA (Bitfield-Mask: 0x3f) */ +/* ======================================================= TCMSABARS ======================================================= */ + #define R_CPSCU_TCMSABARS_TCMSABA_Pos (13UL) /*!< TCMSABA (Bit 13) */ + #define R_CPSCU_TCMSABARS_TCMSABA_Msk (0x7e000UL) /*!< TCMSABA (Bitfield-Mask: 0x3f) */ +/* ======================================================= SRAMESAR ======================================================== */ + #define R_CPSCU_SRAMESAR_SRAMESA_Pos (0UL) /*!< SRAMESA (Bit 0) */ + #define R_CPSCU_SRAMESAR_SRAMESA_Msk (0x1UL) /*!< SRAMESA (Bitfield-Mask: 0x01) */ +/* ======================================================== TEVTRCR ======================================================== */ + #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */ + #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */ + #define R_CPSCU_TEVTRCR_TEVTEICU_Pos (1UL) /*!< TEVTEICU (Bit 1) */ + #define R_CPSCU_TEVTRCR_TEVTEICU_Msk (0x2UL) /*!< TEVTEICU (Bitfield-Mask: 0x01) */ +/* ======================================================== IPCSAR ========================================================= */ + #define R_CPSCU_IPCSAR_SAIPCSEM_Pos (0UL) /*!< SAIPCSEM (Bit 0) */ + #define R_CPSCU_IPCSAR_SAIPCSEM_Msk (0x1UL) /*!< SAIPCSEM (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCNMI_Pos (8UL) /*!< SAIPCNMI (Bit 8) */ + #define R_CPSCU_IPCSAR_SAIPCNMI_Msk (0x100UL) /*!< SAIPCNMI (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR0_Pos (16UL) /*!< SAIPCIR0 (Bit 16) */ + #define R_CPSCU_IPCSAR_SAIPCIR0_Msk (0x10000UL) /*!< SAIPCIR0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR1_Pos (17UL) /*!< SAIPCIR1 (Bit 17) */ + #define R_CPSCU_IPCSAR_SAIPCIR1_Msk (0x20000UL) /*!< SAIPCIR1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR2_Pos (18UL) /*!< SAIPCIR2 (Bit 18) */ + #define R_CPSCU_IPCSAR_SAIPCIR2_Msk (0x40000UL) /*!< SAIPCIR2 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCSAR_SAIPCIR3_Pos (19UL) /*!< SAIPCIR3 (Bit 19) */ + #define R_CPSCU_IPCSAR_SAIPCIR3_Msk (0x80000UL) /*!< SAIPCIR3 (Bitfield-Mask: 0x01) */ +/* ======================================================== IPCPAR ========================================================= */ + #define R_CPSCU_IPCPAR_PAIPCSEM_Pos (0UL) /*!< PAIPCSEM (Bit 0) */ + #define R_CPSCU_IPCPAR_PAIPCSEM_Msk (0x1UL) /*!< PAIPCSEM (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCNMI_Pos (8UL) /*!< PAIPCNMI (Bit 8) */ + #define R_CPSCU_IPCPAR_PAIPCNMI_Msk (0x100UL) /*!< PAIPCNMI (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR0_Pos (16UL) /*!< PAIPCIR0 (Bit 16) */ + #define R_CPSCU_IPCPAR_PAIPCIR0_Msk (0x10000UL) /*!< PAIPCIR0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR1_Pos (17UL) /*!< PAIPCIR1 (Bit 17) */ + #define R_CPSCU_IPCPAR_PAIPCIR1_Msk (0x20000UL) /*!< PAIPCIR1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR2_Pos (18UL) /*!< PAIPCIR2 (Bit 18) */ + #define R_CPSCU_IPCPAR_PAIPCIR2_Msk (0x40000UL) /*!< PAIPCIR2 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_IPCPAR_PAIPCIR3_Pos (19UL) /*!< PAIPCIR3 (Bit 19) */ + #define R_CPSCU_IPCPAR_PAIPCIR3_Msk (0x80000UL) /*!< PAIPCIR3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ADCLKENR ======================================================== */ + #define R_ADC_B0_ADCLKENR_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */ + #define R_ADC_B0_ADCLKENR_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKSR ======================================================== */ + #define R_ADC_B0_ADCLKSR_CLKSR_Pos (0UL) /*!< CLKSR (Bit 0) */ + #define R_ADC_B0_ADCLKSR_CLKSR_Msk (0x1UL) /*!< CLKSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKCR ======================================================== */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCLKCR_DIVR_Pos (16UL) /*!< DIVR (Bit 16) */ + #define R_ADC_B0_ADCLKCR_DIVR_Msk (0x70000UL) /*!< DIVR (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSYCR ========================================================= */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Pos (0UL) /*!< ADSYCYC (Bit 0) */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Msk (0x7ffUL) /*!< ADSYCYC (Bitfield-Mask: 0x7ff) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Pos (16UL) /*!< ADSYDIS0 (Bit 16) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Msk (0x10000UL) /*!< ADSYDIS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Pos (17UL) /*!< ADSYDIS1 (Bit 17) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Msk (0x20000UL) /*!< ADSYDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADERINTCR ======================================================= */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Pos (0UL) /*!< ADEIE0 (Bit 0) */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Msk (0x1UL) /*!< ADEIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Pos (1UL) /*!< ADEIE1 (Bit 1) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Msk (0x2UL) /*!< ADEIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFINTCR ======================================================= */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Pos (0UL) /*!< ADOVFIE0 (Bit 0) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Msk (0x1UL) /*!< ADOVFIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Pos (1UL) /*!< ADOVFIE1 (Bit 1) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Msk (0x2UL) /*!< ADOVFIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALINTCR ======================================================= */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Pos (16UL) /*!< CALENDIE0 (Bit 16) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Msk (0x10000UL) /*!< CALENDIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Pos (17UL) /*!< CALENDIE1 (Bit 17) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Msk (0x20000UL) /*!< CALENDIE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADMDR ========================================================= */ + #define R_ADC_B0_ADMDR_ADMD0_Pos (0UL) /*!< ADMD0 (Bit 0) */ + #define R_ADC_B0_ADMDR_ADMD0_Msk (0xfUL) /*!< ADMD0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADMDR_ADMD1_Pos (8UL) /*!< ADMD1 (Bit 8) */ + #define R_ADC_B0_ADMDR_ADMD1_Msk (0xf00UL) /*!< ADMD1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC_B0_ADGSPCR_PGS0_Pos (0UL) /*!< PGS0 (Bit 0) */ + #define R_ADC_B0_ADGSPCR_PGS0_Msk (0x1UL) /*!< PGS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Pos (1UL) /*!< RSCN0 (Bit 1) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Msk (0x2UL) /*!< RSCN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Pos (2UL) /*!< LGRRS0 (Bit 2) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Msk (0x4UL) /*!< LGRRS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP0_Pos (3UL) /*!< GRP0 (Bit 3) */ + #define R_ADC_B0_ADGSPCR_GRP0_Msk (0x8UL) /*!< GRP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_PGS1_Pos (8UL) /*!< PGS1 (Bit 8) */ + #define R_ADC_B0_ADGSPCR_PGS1_Msk (0x100UL) /*!< PGS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Pos (9UL) /*!< RSCN1 (Bit 9) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Msk (0x200UL) /*!< RSCN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Pos (10UL) /*!< LGRRS1 (Bit 10) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Msk (0x400UL) /*!< LGRRS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP1_Pos (11UL) /*!< GRP1 (Bit 11) */ + #define R_ADC_B0_ADGSPCR_GRP1_Msk (0x800UL) /*!< GRP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSGER ========================================================= */ + #define R_ADC_B0_ADSGER_SGREn_Pos (0UL) /*!< SGREn (Bit 0) */ + #define R_ADC_B0_ADSGER_SGREn_Msk (0x1ffUL) /*!< SGREn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSGCR0 ======================================================== */ + #define R_ADC_B0_ADSGCR0_SGADS0_Pos (0UL) /*!< SGADS0 (Bit 0) */ + #define R_ADC_B0_ADSGCR0_SGADS0_Msk (0x3UL) /*!< SGADS0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Pos (8UL) /*!< SGADS1 (Bit 8) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Msk (0x300UL) /*!< SGADS1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Pos (16UL) /*!< SGADS2 (Bit 16) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Msk (0x30000UL) /*!< SGADS2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Pos (24UL) /*!< SGADS3 (Bit 24) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Msk (0x3000000UL) /*!< SGADS3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR1 ======================================================== */ + #define R_ADC_B0_ADSGCR1_SGADS4_Pos (0UL) /*!< SGADS4 (Bit 0) */ + #define R_ADC_B0_ADSGCR1_SGADS4_Msk (0x3UL) /*!< SGADS4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Pos (8UL) /*!< SGADS5 (Bit 8) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Msk (0x300UL) /*!< SGADS5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Pos (16UL) /*!< SGADS6 (Bit 16) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Msk (0x30000UL) /*!< SGADS6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Pos (24UL) /*!< SGADS7 (Bit 24) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Msk (0x3000000UL) /*!< SGADS7 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR2 ======================================================== */ + #define R_ADC_B0_ADSGCR2_SGADS8_Pos (0UL) /*!< SGADS8 (Bit 0) */ + #define R_ADC_B0_ADSGCR2_SGADS8_Msk (0x3UL) /*!< SGADS8 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADINTCR ======================================================== */ + #define R_ADC_B0_ADINTCR_ADIEn_Pos (0UL) /*!< ADIEn (Bit 0) */ + #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x1ffUL) /*!< ADIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADTRGEXT0 ======================================================= */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT1 ======================================================= */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT2 ======================================================= */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT3 ======================================================= */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT4 ======================================================= */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT5 ======================================================= */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT6 ======================================================= */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT7 ======================================================= */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT8 ======================================================= */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGELC0 ======================================================= */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC1 ======================================================= */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC2 ======================================================= */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC3 ======================================================= */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC4 ======================================================= */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC5 ======================================================= */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC6 ======================================================= */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC7 ======================================================= */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC8 ======================================================= */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGGPT0 ======================================================= */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT1 ======================================================= */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT2 ======================================================= */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT3 ======================================================= */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT4 ======================================================= */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT5 ======================================================= */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT6 ======================================================= */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT7 ======================================================= */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGGPT8 ======================================================= */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Msk (0x3fffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Msk (0x3fff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADTRGDLR0 ======================================================= */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Pos (0UL) /*!< TRGDLY0 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Msk (0xffUL) /*!< TRGDLY0 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Pos (16UL) /*!< TRGDLY1 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Msk (0xff0000UL) /*!< TRGDLY1 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR1 ======================================================= */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Pos (0UL) /*!< TRGDLY2 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Msk (0xffUL) /*!< TRGDLY2 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Pos (16UL) /*!< TRGDLY3 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Msk (0xff0000UL) /*!< TRGDLY3 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR2 ======================================================= */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Pos (0UL) /*!< TRGDLY4 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Msk (0xffUL) /*!< TRGDLY4 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Pos (16UL) /*!< TRGDLY5 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Msk (0xff0000UL) /*!< TRGDLY5 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR3 ======================================================= */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Pos (0UL) /*!< TRGDLY6 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Msk (0xffUL) /*!< TRGDLY6 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Pos (16UL) /*!< TRGDLY7 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Msk (0xff0000UL) /*!< TRGDLY7 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR4 ======================================================= */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Pos (0UL) /*!< TRGDLY8 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Msk (0xffUL) /*!< TRGDLY8 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR0 ======================================================== */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR1 ======================================================== */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR2 ======================================================== */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR3 ======================================================== */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR4 ======================================================== */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR5 ======================================================== */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR6 ======================================================== */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR7 ======================================================== */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR8 ======================================================== */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Msk (0xff000000UL) /*!< ADNDIS (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR0 ======================================================== */ + #define R_ADC_B0_ADSSTR0_SST0_Pos (0UL) /*!< SST0 (Bit 0) */ + #define R_ADC_B0_ADSSTR0_SST0_Msk (0x3ffUL) /*!< SST0 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR0_SST1_Pos (16UL) /*!< SST1 (Bit 16) */ + #define R_ADC_B0_ADSSTR0_SST1_Msk (0x3ff0000UL) /*!< SST1 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR1 ======================================================== */ + #define R_ADC_B0_ADSSTR1_SST2_Pos (0UL) /*!< SST2 (Bit 0) */ + #define R_ADC_B0_ADSSTR1_SST2_Msk (0x3ffUL) /*!< SST2 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR1_SST3_Pos (16UL) /*!< SST3 (Bit 16) */ + #define R_ADC_B0_ADSSTR1_SST3_Msk (0x3ff0000UL) /*!< SST3 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR2 ======================================================== */ + #define R_ADC_B0_ADSSTR2_SST4_Pos (0UL) /*!< SST4 (Bit 0) */ + #define R_ADC_B0_ADSSTR2_SST4_Msk (0x3ffUL) /*!< SST4 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR2_SST5_Pos (16UL) /*!< SST5 (Bit 16) */ + #define R_ADC_B0_ADSSTR2_SST5_Msk (0x3ff0000UL) /*!< SST5 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR3 ======================================================== */ + #define R_ADC_B0_ADSSTR3_SST6_Pos (0UL) /*!< SST6 (Bit 0) */ + #define R_ADC_B0_ADSSTR3_SST6_Msk (0x3ffUL) /*!< SST6 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR3_SST7_Pos (16UL) /*!< SST7 (Bit 16) */ + #define R_ADC_B0_ADSSTR3_SST7_Msk (0x3ff0000UL) /*!< SST7 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR4 ======================================================== */ + #define R_ADC_B0_ADSSTR4_SST8_Pos (0UL) /*!< SST8 (Bit 0) */ + #define R_ADC_B0_ADSSTR4_SST8_Msk (0x3ffUL) /*!< SST8 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR4_SST9_Pos (16UL) /*!< SST9 (Bit 16) */ + #define R_ADC_B0_ADSSTR4_SST9_Msk (0x3ff0000UL) /*!< SST9 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR5 ======================================================== */ + #define R_ADC_B0_ADSSTR5_SST10_Pos (0UL) /*!< SST10 (Bit 0) */ + #define R_ADC_B0_ADSSTR5_SST10_Msk (0x3ffUL) /*!< SST10 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR5_SST11_Pos (16UL) /*!< SST11 (Bit 16) */ + #define R_ADC_B0_ADSSTR5_SST11_Msk (0x3ff0000UL) /*!< SST11 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR6 ======================================================== */ + #define R_ADC_B0_ADSSTR6_SST12_Pos (0UL) /*!< SST12 (Bit 0) */ + #define R_ADC_B0_ADSSTR6_SST12_Msk (0x3ffUL) /*!< SST12 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR6_SST13_Pos (16UL) /*!< SST13 (Bit 16) */ + #define R_ADC_B0_ADSSTR6_SST13_Msk (0x3ff0000UL) /*!< SST13 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR7 ======================================================== */ + #define R_ADC_B0_ADSSTR7_SST14_Pos (0UL) /*!< SST14 (Bit 0) */ + #define R_ADC_B0_ADSSTR7_SST14_Msk (0x3ffUL) /*!< SST14 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR7_SST15_Pos (16UL) /*!< SST15 (Bit 16) */ + #define R_ADC_B0_ADSSTR7_SST15_Msk (0x3ff0000UL) /*!< SST15 (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADCNVSTR ======================================================== */ + #define R_ADC_B0_ADCNVSTR_CST0_Pos (0UL) /*!< CST0 (Bit 0) */ + #define R_ADC_B0_ADCNVSTR_CST0_Msk (0x3fUL) /*!< CST0 (Bitfield-Mask: 0x3f) */ + #define R_ADC_B0_ADCNVSTR_CST1_Pos (8UL) /*!< CST1 (Bit 8) */ + #define R_ADC_B0_ADCNVSTR_CST1_Msk (0x3f00UL) /*!< CST1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADCALSTCR ======================================================= */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Pos (0UL) /*!< CALADSST (Bit 0) */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Msk (0x3ffUL) /*!< CALADSST (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Pos (16UL) /*!< CALADCST (Bit 16) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Msk (0x3f0000UL) /*!< CALADCST (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADSHCR0 ======================================================== */ + #define R_ADC_B0_ADSHCR0_SHEN_Pos (0UL) /*!< SHEN (Bit 0) */ + #define R_ADC_B0_ADSHCR0_SHEN_Msk (0x1UL) /*!< SHEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR0_SHMD_Pos (16UL) /*!< SHMD (Bit 16) */ + #define R_ADC_B0_ADSHCR0_SHMD_Msk (0x10000UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR0 ======================================================== */ + #define R_ADC_B0_ADSHSTR0_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR0_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSHCR1 ======================================================== */ + #define R_ADC_B0_ADSHCR1_SHEN_Pos (0UL) /*!< SHEN (Bit 0) */ + #define R_ADC_B0_ADSHCR1_SHEN_Msk (0x1UL) /*!< SHEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR1_SHMD_Pos (16UL) /*!< SHMD (Bit 16) */ + #define R_ADC_B0_ADSHCR1_SHMD_Msk (0x10000UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR1 ======================================================== */ + #define R_ADC_B0_ADSHSTR1_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR1_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================= ADCALSHCR ======================================================= */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Pos (0UL) /*!< CALSHSST (Bit 0) */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Msk (0xffUL) /*!< CALSHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Pos (16UL) /*!< CALSHHST (Bit 16) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Msk (0x70000UL) /*!< CALSHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADREFCR ======================================================== */ + #define R_ADC_B0_ADREFCR_VDE_Pos (0UL) /*!< VDE (Bit 0) */ + #define R_ADC_B0_ADREFCR_VDE_Msk (0x1UL) /*!< VDE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDFSR0 ======================================================== */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADDFSR1 ======================================================== */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADUOFTR0 ======================================================== */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR1 ======================================================== */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR2 ======================================================== */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR3 ======================================================== */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR4 ======================================================== */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR5 ======================================================== */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR6 ======================================================== */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR7 ======================================================== */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADUGTR0 ======================================================== */ + #define R_ADC_B0_ADUGTR0_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR0_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR0_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR0_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR1 ======================================================== */ + #define R_ADC_B0_ADUGTR1_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR1_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR1_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR1_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR2 ======================================================== */ + #define R_ADC_B0_ADUGTR2_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR2_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR2_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR2_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR3 ======================================================== */ + #define R_ADC_B0_ADUGTR3_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR3_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR3_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR3_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR4 ======================================================== */ + #define R_ADC_B0_ADUGTR4_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR4_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR4_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR4_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR5 ======================================================== */ + #define R_ADC_B0_ADUGTR5_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR5_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR5_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR5_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR6 ======================================================== */ + #define R_ADC_B0_ADUGTR6_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR6_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR6_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR6_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ======================================================== ADUGTR7 ======================================================== */ + #define R_ADC_B0_ADUGTR7_UGAINF_Pos (0UL) /*!< UGAINF (Bit 0) */ + #define R_ADC_B0_ADUGTR7_UGAINF_Msk (0x3fffUL) /*!< UGAINF (Bitfield-Mask: 0x3fff) */ + #define R_ADC_B0_ADUGTR7_UGAINI_Pos (14UL) /*!< UGAINI (Bit 14) */ + #define R_ADC_B0_ADUGTR7_UGAINI_Msk (0xc000UL) /*!< UGAINI (Bitfield-Mask: 0x03) */ +/* ====================================================== ADLIMINTCR ======================================================= */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Pos (0UL) /*!< LIMIEn (Bit 0) */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Msk (0x1ffUL) /*!< LIMIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADLIMTR0 ======================================================== */ + #define R_ADC_B0_ADLIMTR0_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR0_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR1 ======================================================== */ + #define R_ADC_B0_ADLIMTR1_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR1_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR2 ======================================================== */ + #define R_ADC_B0_ADLIMTR2_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR2_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR3 ======================================================== */ + #define R_ADC_B0_ADLIMTR3_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR3_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR4 ======================================================== */ + #define R_ADC_B0_ADLIMTR4_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR4_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR5 ======================================================== */ + #define R_ADC_B0_ADLIMTR5_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR5_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR6 ======================================================== */ + #define R_ADC_B0_ADLIMTR6_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR6_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR7 ======================================================== */ + #define R_ADC_B0_ADLIMTR7_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR7_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPENR ======================================================== */ + #define R_ADC_B0_ADCMPENR_CMPENn_Pos (0UL) /*!< CMPENn (Bit 0) */ + #define R_ADC_B0_ADCMPENR_CMPENn_Msk (0xffUL) /*!< CMPENn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPINTCR ======================================================= */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Pos (0UL) /*!< CMPIEn (Bit 0) */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Msk (0xfUL) /*!< CMPIEn (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCCMPCR0 ======================================================= */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCCMPCR1 ======================================================= */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCMPMDR0 ======================================================= */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Pos (0UL) /*!< CMPMD0 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Msk (0x3UL) /*!< CMPMD0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Pos (8UL) /*!< CMPMD1 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Msk (0x300UL) /*!< CMPMD1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Pos (16UL) /*!< CMPMD2 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Msk (0x30000UL) /*!< CMPMD2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Pos (24UL) /*!< CMPMD3 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Msk (0x3000000UL) /*!< CMPMD3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPMDR1 ======================================================= */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Pos (0UL) /*!< CMPMD4 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Msk (0x3UL) /*!< CMPMD4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Pos (8UL) /*!< CMPMD5 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Msk (0x300UL) /*!< CMPMD5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Pos (16UL) /*!< CMPMD6 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Msk (0x30000UL) /*!< CMPMD6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Pos (24UL) /*!< CMPMD7 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Msk (0x3000000UL) /*!< CMPMD7 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPTBR0 ======================================================= */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR1 ======================================================= */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR2 ======================================================= */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR3 ======================================================= */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR4 ======================================================= */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR5 ======================================================= */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR6 ======================================================= */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR7 ======================================================= */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADFIFOCR ======================================================== */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Pos (0UL) /*!< FIFOEN0 (Bit 0) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Msk (0x1UL) /*!< FIFOEN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Pos (1UL) /*!< FIFOEN1 (Bit 1) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Msk (0x2UL) /*!< FIFOEN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Pos (2UL) /*!< FIFOEN2 (Bit 2) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Msk (0x4UL) /*!< FIFOEN2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Pos (3UL) /*!< FIFOEN3 (Bit 3) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Msk (0x8UL) /*!< FIFOEN3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Pos (4UL) /*!< FIFOEN4 (Bit 4) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Msk (0x10UL) /*!< FIFOEN4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Pos (5UL) /*!< FIFOEN5 (Bit 5) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Msk (0x20UL) /*!< FIFOEN5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Pos (6UL) /*!< FIFOEN6 (Bit 6) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Msk (0x40UL) /*!< FIFOEN6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Pos (7UL) /*!< FIFOEN7 (Bit 7) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Msk (0x80UL) /*!< FIFOEN7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Pos (8UL) /*!< FIFOEN8 (Bit 8) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Msk (0x100UL) /*!< FIFOEN8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADFIFOINTCR ====================================================== */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Pos (0UL) /*!< FIFOIE0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Msk (0x1UL) /*!< FIFOIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Pos (1UL) /*!< FIFOIE1 (Bit 1) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Msk (0x2UL) /*!< FIFOIE1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Pos (2UL) /*!< FIFOIE2 (Bit 2) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Msk (0x4UL) /*!< FIFOIE2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Pos (3UL) /*!< FIFOIE3 (Bit 3) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Msk (0x8UL) /*!< FIFOIE3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Pos (4UL) /*!< FIFOIE4 (Bit 4) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Msk (0x10UL) /*!< FIFOIE4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Pos (5UL) /*!< FIFOIE5 (Bit 5) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Msk (0x20UL) /*!< FIFOIE5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Pos (6UL) /*!< FIFOIE6 (Bit 6) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Msk (0x40UL) /*!< FIFOIE6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Pos (7UL) /*!< FIFOIE7 (Bit 7) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Msk (0x80UL) /*!< FIFOIE7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Pos (8UL) /*!< FIFOIE8 (Bit 8) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Msk (0x100UL) /*!< FIFOIE8 (Bitfield-Mask: 0x01) */ +/* ===================================================== ADFIFOINTLR0 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Pos (0UL) /*!< FIFOILV0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Msk (0xfUL) /*!< FIFOILV0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Pos (16UL) /*!< FIFOILV1 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Msk (0xf0000UL) /*!< FIFOILV1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR1 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Pos (0UL) /*!< FIFOILV2 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Msk (0xfUL) /*!< FIFOILV2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Pos (16UL) /*!< FIFOILV3 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Msk (0xf0000UL) /*!< FIFOILV3 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR2 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Pos (0UL) /*!< FIFOILV4 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Msk (0xfUL) /*!< FIFOILV4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Pos (16UL) /*!< FIFOILV5 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Msk (0xf0000UL) /*!< FIFOILV5 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR3 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Pos (0UL) /*!< FIFOILV6 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Msk (0xfUL) /*!< FIFOILV6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Pos (16UL) /*!< FIFOILV7 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Msk (0xf0000UL) /*!< FIFOILV7 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR4 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Pos (0UL) /*!< FIFOILV8 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Msk (0xfUL) /*!< FIFOILV8 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR0 ======================================================== */ + #define R_ADC_B0_ADCHCR0_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR0_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR0_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR0_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR1 ======================================================== */ + #define R_ADC_B0_ADCHCR1_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR1_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR1_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR1_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR2 ======================================================== */ + #define R_ADC_B0_ADCHCR2_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR2_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR2_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR2_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR3 ======================================================== */ + #define R_ADC_B0_ADCHCR3_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR3_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR3_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR3_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR4 ======================================================== */ + #define R_ADC_B0_ADCHCR4_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR4_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR4_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR4_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR5 ======================================================== */ + #define R_ADC_B0_ADCHCR5_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR5_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR5_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR5_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR6 ======================================================== */ + #define R_ADC_B0_ADCHCR6_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR6_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR6_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR6_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR7 ======================================================== */ + #define R_ADC_B0_ADCHCR7_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR7_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR7_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR7_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR8 ======================================================== */ + #define R_ADC_B0_ADCHCR8_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR8_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR8_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR8_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR9 ======================================================== */ + #define R_ADC_B0_ADCHCR9_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR9_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR9_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR9_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR10 ======================================================== */ + #define R_ADC_B0_ADCHCR10_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR10_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR10_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR10_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR11 ======================================================== */ + #define R_ADC_B0_ADCHCR11_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR11_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR11_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR11_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR12 ======================================================== */ + #define R_ADC_B0_ADCHCR12_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR12_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR12_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR12_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR13 ======================================================== */ + #define R_ADC_B0_ADCHCR13_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR13_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR13_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR13_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR14 ======================================================== */ + #define R_ADC_B0_ADCHCR14_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR14_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR14_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR14_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR15 ======================================================== */ + #define R_ADC_B0_ADCHCR15_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR15_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR15_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR15_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR16 ======================================================== */ + #define R_ADC_B0_ADCHCR16_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR16_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR16_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR16_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR17 ======================================================== */ + #define R_ADC_B0_ADCHCR17_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR17_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR17_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR17_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR18 ======================================================== */ + #define R_ADC_B0_ADCHCR18_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR18_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR18_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR18_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR19 ======================================================== */ + #define R_ADC_B0_ADCHCR19_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR19_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR19_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR19_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR20 ======================================================== */ + #define R_ADC_B0_ADCHCR20_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR20_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR20_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR20_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR21 ======================================================== */ + #define R_ADC_B0_ADCHCR21_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR21_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR21_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR21_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR22 ======================================================== */ + #define R_ADC_B0_ADCHCR22_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR22_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR22_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR22_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR23 ======================================================== */ + #define R_ADC_B0_ADCHCR23_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR23_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR23_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR23_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR24 ======================================================== */ + #define R_ADC_B0_ADCHCR24_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR24_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR24_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR24_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR25 ======================================================== */ + #define R_ADC_B0_ADCHCR25_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR25_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR25_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR25_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR26 ======================================================== */ + #define R_ADC_B0_ADCHCR26_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR26_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR26_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR26_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR27 ======================================================== */ + #define R_ADC_B0_ADCHCR27_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR27_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR27_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR27_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR28 ======================================================== */ + #define R_ADC_B0_ADCHCR28_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR28_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR28_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR28_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR29 ======================================================== */ + #define R_ADC_B0_ADCHCR29_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR29_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR29_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR29_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR30 ======================================================== */ + #define R_ADC_B0_ADCHCR30_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR30_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR30_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR30_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR31 ======================================================== */ + #define R_ADC_B0_ADCHCR31_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR31_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR31_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR31_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR32 ======================================================== */ + #define R_ADC_B0_ADCHCR32_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR32_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR32_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR32_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA0 ======================================================= */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA1 ======================================================= */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA2 ======================================================= */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA3 ======================================================= */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA4 ======================================================= */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA5 ======================================================= */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA6 ======================================================= */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA7 ======================================================= */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA8 ======================================================= */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA9 ======================================================= */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA10 ======================================================= */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA11 ======================================================= */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA12 ======================================================= */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA13 ======================================================= */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA14 ======================================================= */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA15 ======================================================= */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA16 ======================================================= */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA17 ======================================================= */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA18 ======================================================= */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA19 ======================================================= */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA20 ======================================================= */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA21 ======================================================= */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA22 ======================================================= */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA23 ======================================================= */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA24 ======================================================= */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA25 ======================================================= */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA26 ======================================================= */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA27 ======================================================= */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA28 ======================================================= */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA29 ======================================================= */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA30 ======================================================= */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA31 ======================================================= */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA32 ======================================================= */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRB0 ======================================================= */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB1 ======================================================= */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB2 ======================================================= */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB3 ======================================================= */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB4 ======================================================= */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB5 ======================================================= */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB6 ======================================================= */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB7 ======================================================= */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB8 ======================================================= */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB9 ======================================================= */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB10 ======================================================= */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB11 ======================================================= */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB12 ======================================================= */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB13 ======================================================= */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB14 ======================================================= */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB15 ======================================================= */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB16 ======================================================= */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB17 ======================================================= */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB18 ======================================================= */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB19 ======================================================= */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB20 ======================================================= */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB21 ======================================================= */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB22 ======================================================= */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB23 ======================================================= */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB24 ======================================================= */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB25 ======================================================= */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB26 ======================================================= */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB27 ======================================================= */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB28 ======================================================= */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB29 ======================================================= */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB30 ======================================================= */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB31 ======================================================= */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB32 ======================================================= */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRC0 ======================================================= */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC1 ======================================================= */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC2 ======================================================= */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC3 ======================================================= */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC4 ======================================================= */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC5 ======================================================= */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC6 ======================================================= */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC7 ======================================================= */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC8 ======================================================= */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC9 ======================================================= */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC10 ======================================================= */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC11 ======================================================= */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC12 ======================================================= */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC13 ======================================================= */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC14 ======================================================= */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC15 ======================================================= */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC16 ======================================================= */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC17 ======================================================= */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC18 ======================================================= */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC19 ======================================================= */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC20 ======================================================= */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC21 ======================================================= */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC22 ======================================================= */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC23 ======================================================= */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC24 ======================================================= */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC25 ======================================================= */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC26 ======================================================= */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC27 ======================================================= */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC28 ======================================================= */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC29 ======================================================= */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC30 ======================================================= */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC31 ======================================================= */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC32 ======================================================= */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALSTR ======================================================== */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Pos (0UL) /*!< ADCALST0 (Bit 0) */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Msk (0x7UL) /*!< ADCALST0 (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Pos (8UL) /*!< ADCALST1 (Bit 8) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Msk (0x700UL) /*!< ADCALST1 (Bitfield-Mask: 0x07) */ +/* ======================================================= ADTRGENR ======================================================== */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Pos (0UL) /*!< STTRGENn (Bit 0) */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Msk (0x1ffUL) /*!< STTRGENn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSYSTR ======================================================== */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Pos (0UL) /*!< ADSYSTn (Bit 0) */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Msk (0x1ffUL) /*!< ADSYSTn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADSTR ========================================================= */ + #define R_ADC_B0_ADSTR_ADST_Pos (0UL) /*!< ADST (Bit 0) */ + #define R_ADC_B0_ADSTR_ADST_Msk (0x1UL) /*!< ADST (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTOPR ======================================================== */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Pos (0UL) /*!< ADSTOP0 (Bit 0) */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Msk (0x1UL) /*!< ADSTOP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Pos (8UL) /*!< ADSTOP1 (Bit 8) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Msk (0x100UL) /*!< ADSTOP1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADSR ========================================================== */ + #define R_ADC_B0_ADSR_ADACT0_Pos (0UL) /*!< ADACT0 (Bit 0) */ + #define R_ADC_B0_ADSR_ADACT0_Msk (0x1UL) /*!< ADACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_ADACT1_Pos (1UL) /*!< ADACT1 (Bit 1) */ + #define R_ADC_B0_ADSR_ADACT1_Msk (0x2UL) /*!< ADACT1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT0_Pos (16UL) /*!< CALACT0 (Bit 16) */ + #define R_ADC_B0_ADSR_CALACT0_Msk (0x10000UL) /*!< CALACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT1_Pos (17UL) /*!< CALACT1 (Bit 17) */ + #define R_ADC_B0_ADSR_CALACT1_Msk (0x20000UL) /*!< CALACT1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGRSR ========================================================= */ + #define R_ADC_B0_ADGRSR_ACTGRn_Pos (0UL) /*!< ACTGRn (Bit 0) */ + #define R_ADC_B0_ADGRSR_ACTGRn_Msk (0x1ffUL) /*!< ACTGRn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADERSR ========================================================= */ + #define R_ADC_B0_ADERSR_ADERF0_Pos (0UL) /*!< ADERF0 (Bit 0) */ + #define R_ADC_B0_ADERSR_ADERF0_Msk (0x1UL) /*!< ADERF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSR_ADERF1_Pos (1UL) /*!< ADERF1 (Bit 1) */ + #define R_ADC_B0_ADERSR_ADERF1_Msk (0x2UL) /*!< ADERF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADERSCR ======================================================== */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Pos (0UL) /*!< ADERCLR0 (Bit 0) */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Msk (0x1UL) /*!< ADERCLR0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Pos (1UL) /*!< ADERCLR1 (Bit 1) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Msk (0x2UL) /*!< ADERCLR1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSR ======================================================= */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Pos (0UL) /*!< CALENDF0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Msk (0x1UL) /*!< CALENDF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Pos (1UL) /*!< CALENDF1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Msk (0x2UL) /*!< CALENDF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSCR ====================================================== */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Pos (0UL) /*!< CALENDC0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Msk (0x1UL) /*!< CALENDC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Pos (1UL) /*!< CALENDC1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Msk (0x2UL) /*!< CALENDC1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADOVFERSR ======================================================= */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Pos (0UL) /*!< ADOVFEF0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Msk (0x1UL) /*!< ADOVFEF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Pos (1UL) /*!< ADOVFEF1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Msk (0x2UL) /*!< ADOVFEF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSR0 ======================================================= */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Pos (0UL) /*!< OVFCHFn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Msk (0x7fffffUL) /*!< OVFCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADOVFEXSR ======================================================= */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Pos (0UL) /*!< OVFEXF0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Msk (0x1UL) /*!< OVFEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Pos (1UL) /*!< OVFEXF1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Msk (0x2UL) /*!< OVFEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF4_Pos (4UL) /*!< OVFEXF4 (Bit 4) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF4_Msk (0x10UL) /*!< OVFEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Pos (5UL) /*!< OVFEXF5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Msk (0x20UL) /*!< OVFEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Pos (6UL) /*!< OVFEXF6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Msk (0x40UL) /*!< OVFEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Pos (8UL) /*!< OVFEXF8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Msk (0x100UL) /*!< OVFEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF9_Pos (9UL) /*!< OVFEXF9 (Bit 9) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF9_Msk (0x200UL) /*!< OVFEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF16_Pos (16UL) /*!< OVFEXF16 (Bit 16) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF16_Msk (0x10000UL) /*!< OVFEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF17_Pos (17UL) /*!< OVFEXF17 (Bit 17) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF17_Msk (0x20000UL) /*!< OVFEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF18_Pos (18UL) /*!< OVFEXF18 (Bit 18) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF18_Msk (0x40000UL) /*!< OVFEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF20_Pos (20UL) /*!< OVFEXF20 (Bit 20) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF20_Msk (0x100000UL) /*!< OVFEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF21_Pos (21UL) /*!< OVFEXF21 (Bit 21) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF21_Msk (0x200000UL) /*!< OVFEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF22_Pos (22UL) /*!< OVFEXF22 (Bit 22) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF22_Msk (0x400000UL) /*!< OVFEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFERSCR ======================================================= */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Pos (0UL) /*!< ADOVFEC0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Msk (0x1UL) /*!< ADOVFEC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Pos (1UL) /*!< ADOVFEC1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Msk (0x2UL) /*!< ADOVFEC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSCR0 ====================================================== */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Pos (0UL) /*!< OVFCHCn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Msk (0x7fffffUL) /*!< OVFCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADOVFEXSCR ======================================================= */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Pos (0UL) /*!< OVFEXC0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Msk (0x1UL) /*!< OVFEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Pos (1UL) /*!< OVFEXC1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Msk (0x2UL) /*!< OVFEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC4_Pos (4UL) /*!< OVFEXC4 (Bit 4) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC4_Msk (0x10UL) /*!< OVFEXC4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Pos (5UL) /*!< OVFEXC5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Msk (0x20UL) /*!< OVFEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Pos (6UL) /*!< OVFEXC6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Msk (0x40UL) /*!< OVFEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Pos (8UL) /*!< OVFEXC8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Msk (0x100UL) /*!< OVFEXC8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC9_Pos (9UL) /*!< OVFEXC9 (Bit 9) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC9_Msk (0x200UL) /*!< OVFEXC9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC16_Pos (16UL) /*!< OVFEXC16 (Bit 16) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC16_Msk (0x10000UL) /*!< OVFEXC16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC17_Pos (17UL) /*!< OVFEXC17 (Bit 17) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC17_Msk (0x20000UL) /*!< OVFEXC17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC18_Pos (18UL) /*!< OVFEXC18 (Bit 18) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC18_Msk (0x40000UL) /*!< OVFEXC18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC20_Pos (20UL) /*!< OVFEXC20 (Bit 20) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC20_Msk (0x100000UL) /*!< OVFEXC20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC21_Pos (21UL) /*!< OVFEXC21 (Bit 21) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC21_Msk (0x200000UL) /*!< OVFEXC21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC22_Pos (22UL) /*!< OVFEXC22 (Bit 22) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC22_Msk (0x400000UL) /*!< OVFEXC22 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFOSR0 ======================================================= */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Pos (0UL) /*!< FIFOST0 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Msk (0xfUL) /*!< FIFOST0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Pos (16UL) /*!< FIFOST1 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Msk (0xf0000UL) /*!< FIFOST1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR1 ======================================================= */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Pos (0UL) /*!< FIFOST2 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Msk (0xfUL) /*!< FIFOST2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Pos (16UL) /*!< FIFOST3 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Msk (0xf0000UL) /*!< FIFOST3 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR2 ======================================================= */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Pos (0UL) /*!< FIFOST4 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Msk (0xfUL) /*!< FIFOST4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Pos (16UL) /*!< FIFOST5 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Msk (0xf0000UL) /*!< FIFOST5 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR3 ======================================================= */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Pos (0UL) /*!< FIFOST6 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Msk (0xfUL) /*!< FIFOST6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Pos (16UL) /*!< FIFOST7 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Msk (0xf0000UL) /*!< FIFOST7 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR4 ======================================================= */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Pos (0UL) /*!< FIFOST8 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Msk (0xfUL) /*!< FIFOST8 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFODCR ======================================================= */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Pos (0UL) /*!< FIFODCn (Bit 0) */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Msk (0x1ffUL) /*!< FIFODCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSR ======================================================= */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Pos (0UL) /*!< FIFOOVFn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Msk (0x1ffUL) /*!< FIFOOVFn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Pos (16UL) /*!< FIFOFLFn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Msk (0x1ff0000UL) /*!< FIFOFLFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSCR ====================================================== */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Pos (0UL) /*!< FIFOOVFCn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Msk (0x1ffUL) /*!< FIFOOVFCn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Pos (16UL) /*!< FIFOFLCn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Msk (0x1ff0000UL) /*!< FIFOFLCn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADCMPTBSR ======================================================= */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Pos (0UL) /*!< CMPTBFn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Msk (0xffUL) /*!< CMPTBFn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPTBSCR ======================================================= */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Pos (0UL) /*!< CMPTBCn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Msk (0xffUL) /*!< CMPTBCn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPCHSR0 ======================================================= */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Pos (0UL) /*!< CMPCHFn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Msk (0x7fffffUL) /*!< CMPCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADCMPEXSR ======================================================= */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Pos (0UL) /*!< CMPEXF0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Msk (0x1UL) /*!< CMPEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Pos (1UL) /*!< CMPEXF1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Msk (0x2UL) /*!< CMPEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF4_Pos (4UL) /*!< CMPEXF4 (Bit 4) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF4_Msk (0x10UL) /*!< CMPEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Pos (5UL) /*!< CMPEXF5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Msk (0x20UL) /*!< CMPEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Pos (6UL) /*!< CMPEXF6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Msk (0x40UL) /*!< CMPEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Pos (8UL) /*!< CMPEXF8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Msk (0x100UL) /*!< CMPEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF9_Pos (9UL) /*!< CMPEXF9 (Bit 9) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF9_Msk (0x200UL) /*!< CMPEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF16_Pos (16UL) /*!< CMPEXF16 (Bit 16) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF16_Msk (0x10000UL) /*!< CMPEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF17_Pos (17UL) /*!< CMPEXF17 (Bit 17) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF17_Msk (0x20000UL) /*!< CMPEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF18_Pos (18UL) /*!< CMPEXF18 (Bit 18) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF18_Msk (0x40000UL) /*!< CMPEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF20_Pos (20UL) /*!< CMPEXF20 (Bit 20) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF20_Msk (0x100000UL) /*!< CMPEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF21_Pos (21UL) /*!< CMPEXF21 (Bit 21) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF21_Msk (0x200000UL) /*!< CMPEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF22_Pos (22UL) /*!< CMPEXF22 (Bit 22) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF22_Msk (0x400000UL) /*!< CMPEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCMPCHSCR0 ====================================================== */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Pos (0UL) /*!< CMPCHCn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Msk (0x7fffffUL) /*!< CMPCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADCMPEXSCR ======================================================= */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Pos (0UL) /*!< CMPEXC0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Msk (0x1UL) /*!< CMPEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Pos (1UL) /*!< CMPEXC1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Msk (0x2UL) /*!< CMPEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC4_Pos (4UL) /*!< CMPEXC4 (Bit 4) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC4_Msk (0x10UL) /*!< CMPEXC4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Pos (5UL) /*!< CMPEXC5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Msk (0x20UL) /*!< CMPEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Pos (6UL) /*!< CMPEXC6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Msk (0x40UL) /*!< CMPEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Pos (8UL) /*!< CMPEXC8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Msk (0x100UL) /*!< CMPEXC8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC9_Pos (9UL) /*!< CMPEXC9 (Bit 9) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC9_Msk (0x200UL) /*!< CMPEXC9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC16_Pos (16UL) /*!< CMPEXC16 (Bit 16) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC16_Msk (0x10000UL) /*!< CMPEXC16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC17_Pos (17UL) /*!< CMPEXC17 (Bit 17) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC17_Msk (0x20000UL) /*!< CMPEXC17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC18_Pos (18UL) /*!< CMPEXC18 (Bit 18) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC18_Msk (0x40000UL) /*!< CMPEXC18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC20_Pos (20UL) /*!< CMPEXC20 (Bit 20) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC20_Msk (0x100000UL) /*!< CMPEXC20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC21_Pos (21UL) /*!< CMPEXC21 (Bit 21) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC21_Msk (0x200000UL) /*!< CMPEXC21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC22_Pos (22UL) /*!< CMPEXC22 (Bit 22) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC22_Msk (0x400000UL) /*!< CMPEXC22 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADLIMGRSR ======================================================= */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Pos (0UL) /*!< LIMGRFn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Msk (0x1ffUL) /*!< LIMGRFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSR0 ======================================================= */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Pos (0UL) /*!< LIMCHFn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Msk (0x7fffffUL) /*!< LIMCHFn (Bitfield-Mask: 0x7fffff) */ +/* ======================================================= ADLIMEXSR ======================================================= */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF4_Pos (4UL) /*!< LIMEXF4 (Bit 4) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF4_Msk (0x10UL) /*!< LIMEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF9_Pos (9UL) /*!< LIMEXF9 (Bit 9) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF9_Msk (0x200UL) /*!< LIMEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF16_Pos (16UL) /*!< LIMEXF16 (Bit 16) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF16_Msk (0x10000UL) /*!< LIMEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF17_Pos (17UL) /*!< LIMEXF17 (Bit 17) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF17_Msk (0x20000UL) /*!< LIMEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF18_Pos (18UL) /*!< LIMEXF18 (Bit 18) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF18_Msk (0x40000UL) /*!< LIMEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF20_Pos (20UL) /*!< LIMEXF20 (Bit 20) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF20_Msk (0x100000UL) /*!< LIMEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF21_Pos (21UL) /*!< LIMEXF21 (Bit 21) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF21_Msk (0x200000UL) /*!< LIMEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF22_Pos (22UL) /*!< LIMEXF22 (Bit 22) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF22_Msk (0x400000UL) /*!< LIMEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADLIMGRSCR ======================================================= */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Pos (0UL) /*!< LIMGRCn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Msk (0x1ffUL) /*!< LIMGRCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSCR0 ====================================================== */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Pos (0UL) /*!< LIMCHCn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Msk (0x7fffffUL) /*!< LIMCHCn (Bitfield-Mask: 0x7fffff) */ +/* ====================================================== ADLIMEXSCR ======================================================= */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF4_Pos (4UL) /*!< LIMEXF4 (Bit 4) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF4_Msk (0x10UL) /*!< LIMEXF4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF9_Pos (9UL) /*!< LIMEXF9 (Bit 9) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF9_Msk (0x200UL) /*!< LIMEXF9 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF16_Pos (16UL) /*!< LIMEXF16 (Bit 16) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF16_Msk (0x10000UL) /*!< LIMEXF16 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF17_Pos (17UL) /*!< LIMEXF17 (Bit 17) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF17_Msk (0x20000UL) /*!< LIMEXF17 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF18_Pos (18UL) /*!< LIMEXF18 (Bit 18) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF18_Msk (0x40000UL) /*!< LIMEXF18 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF20_Pos (20UL) /*!< LIMEXF20 (Bit 20) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF20_Msk (0x100000UL) /*!< LIMEXF20 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF21_Pos (21UL) /*!< LIMEXF21 (Bit 21) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF21_Msk (0x200000UL) /*!< LIMEXF21 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF22_Pos (22UL) /*!< LIMEXF22 (Bit 22) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF22_Msk (0x400000UL) /*!< LIMEXF22 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADSCANENDSR ====================================================== */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Pos (0UL) /*!< SCENDFn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Msk (0x1ffUL) /*!< SCENDFn (Bitfield-Mask: 0x1ff) */ +/* ===================================================== ADSCANENDSCR ====================================================== */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Pos (0UL) /*!< SCENDCn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Msk (0x1ffUL) /*!< SCENDCn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC_B0_ADDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXDR ========================================================= */ + #define R_ADC_B0_ADEXDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADEXDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Pos (24UL) /*!< DIAGSR (Bit 24) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Msk (0x7000000UL) /*!< DIAGSR (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADEXDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADEXDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR0 ======================================================= */ + #define R_ADC_B0_ADFIFODR0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR0_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR0_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR0_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR0_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR0_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR1 ======================================================= */ + #define R_ADC_B0_ADFIFODR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR1_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR1_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR1_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR1_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR1_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR2 ======================================================= */ + #define R_ADC_B0_ADFIFODR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR2_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR2_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR2_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR2_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR2_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR3 ======================================================= */ + #define R_ADC_B0_ADFIFODR3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR3_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR3_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR3_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR3_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR3_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR4 ======================================================= */ + #define R_ADC_B0_ADFIFODR4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR4_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR4_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR4_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR4_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR4_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR5 ======================================================= */ + #define R_ADC_B0_ADFIFODR5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR5_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR5_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR5_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR5_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR5_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR6 ======================================================= */ + #define R_ADC_B0_ADFIFODR6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR6_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR6_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR6_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR6_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR6_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR7 ======================================================= */ + #define R_ADC_B0_ADFIFODR7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR7_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR7_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR7_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR7_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR7_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR8 ======================================================= */ + #define R_ADC_B0_ADFIFODR8_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR8_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR8_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR8_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR8_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR8_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */ + #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */ + #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */ + #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */ +/* ========================================================= DOSR ========================================================== */ + #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */ + #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSCR ========================================================= */ + #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */ + #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ======================================================== DODSR0 ========================================================= */ +/* ======================================================== DODSR1 ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ======================================================== RDR_BY ========================================================= */ + #define R_SCI_B0_RDR_BY_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_BY_RDAT_Msk (0xffUL) /*!< RDAT (Bitfield-Mask: 0xff) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== TDR_BY ========================================================= */ + #define R_SCI_B0_TDR_BY_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_BY_TDAT_Msk (0xffUL) /*!< TDAT (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_SCKSEL_Pos (19UL) /*!< SCKSEL (Bit 19) */ + #define R_SCI_B0_CCR4_SCKSEL_Msk (0x80000UL) /*!< SCKSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= CESR ========================================================== */ + #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */ + #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */ + #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCR ========================================================== */ + #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */ + #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */ + #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */ + #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */ + #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */ + #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */ + #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */ + #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================= XCR0 ========================================================== */ + #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */ + #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */ + #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */ + #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */ + #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */ + #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */ + #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */ + #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */ + #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */ + #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */ + #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */ + #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */ + #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */ +/* ========================================================= XCR1 ========================================================== */ + #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */ + #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */ + #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */ + #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */ + #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */ + #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */ +/* ========================================================= XCR2 ========================================================== */ + #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */ + #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */ + #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */ + #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================== MSR ========================================================== */ + #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */ + #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */ + #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= XSR0 ========================================================== */ + #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */ + #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */ + #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */ + #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */ + #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */ + #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */ + #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */ + #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */ + #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */ + #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */ + #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */ + #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */ + #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */ +/* ========================================================= XSR1 ========================================================== */ + #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */ + #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ +/* ========================================================= MFCLR ========================================================= */ + #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */ + #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */ + #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */ + #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */ + #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */ +/* ========================================================= XFCLR ========================================================= */ + #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */ + #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */ + #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */ + #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */ + #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */ + #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */ + #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */ + #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */ + #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDECR ========================================================= */ + #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */ + #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */ + #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */ + #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */ + #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */ + #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */ + #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */ + #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */ + #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */ + #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD0 ========================================================= */ + #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD1 ========================================================= */ + #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD2 ========================================================= */ + #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD3 ========================================================= */ + #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD4 ========================================================= */ + #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD5 ========================================================= */ + #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD6 ========================================================= */ + #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD7 ========================================================= */ + #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */ + #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */ + #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */ + #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */ + #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */ + #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */ + #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */ + #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */ + #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */ + #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */ + #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */ + #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */ + #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */ + #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */ + #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */ + #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */ + #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */ + #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */ + #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */ + #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Pos (0UL) /*!< CKSFTCS0 (Bit 0) */ + #define R_XSPI0_WRAPCFG_CKSFTCS0_Msk (0x1fUL) /*!< CKSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Pos (16UL) /*!< CKSFTCS1 (Bit 16) */ + #define R_XSPI0_WRAPCFG_CKSFTCS1_Msk (0x1f0000UL) /*!< CKSFTCS1 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_ARBMD_Pos (0UL) /*!< ARBMD (Bit 0) */ + #define R_XSPI0_COMCFG_ARBMD_Msk (0x3UL) /*!< ARBMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Pos (4UL) /*!< ECSINTOUTEN (Bit 4) */ + #define R_XSPI0_COMCFG_ECSINTOUTEN_Msk (0x30UL) /*!< ECSINTOUTEN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ======================================================== BMCFGCH ======================================================== */ + #define R_XSPI0_BMCFGCH_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFGCH_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFGCH_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFGCH_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFGCH_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFGCH_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Pos (24UL) /*!< CMBTIM (Bit 24) */ + #define R_XSPI0_BMCFGCH_CMBTIM_Msk (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== ABMCFG ========================================================= */ + #define R_XSPI0_ABMCFG_ODRMD_Pos (0UL) /*!< ODRMD (Bit 0) */ + #define R_XSPI0_ABMCFG_ODRMD_Msk (0x3UL) /*!< ODRMD (Bitfield-Mask: 0x03) */ + #define R_XSPI0_ABMCFG_CHSEL_Pos (16UL) /*!< CHSEL (Bit 16) */ + #define R_XSPI0_ABMCFG_CHSEL_Msk (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Pos (0UL) /*!< CH0CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CH0CS0ACC_Msk (0x3UL) /*!< CH0CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Pos (2UL) /*!< CH0CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CH0CS1ACC_Msk (0xcUL) /*!< CH0CS1ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Pos (4UL) /*!< CH1CS0ACC (Bit 4) */ + #define R_XSPI0_BMCTL0_CH1CS0ACC_Msk (0x30UL) /*!< CH1CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Pos (6UL) /*!< CH1CS1ACC (Bit 6) */ + #define R_XSPI0_BMCTL0_CH1CS1ACC_Msk (0xc0UL) /*!< CH1CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Pos (8UL) /*!< MWRPUSHCH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSHCH_Msk (0x100UL) /*!< MWRPUSHCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Pos (10UL) /*!< PBUFCLRCH (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLRCH_Msk (0x400UL) /*!< PBUFCLRCH (Bitfield-Mask: 0x01) */ +/* ======================================================== CMCTLCH ======================================================== */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTLCH_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTLCH_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTLCH_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTLCH_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS_Pos (0UL) /*!< WPCS (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS_Msk (0x1UL) /*!< WPCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS_Pos (16UL) /*!< RSTCS (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS_Msk (0x10000UL) /*!< RSTCS (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACCCH_Pos (0UL) /*!< MEMACCCH (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACCCH_Msk (0x1UL) /*!< MEMACCCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNECH_Pos (4UL) /*!< PBUFNECH (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNECH_Msk (0x10UL) /*!< PBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Pos (6UL) /*!< WRBUFNECH (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNECH_Msk (0x40UL) /*!< WRBUFNECH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS_Pos (16UL) /*!< ECSCS (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS_Msk (0x10000UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS_Pos (17UL) /*!< INTCS (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS_Msk (0x20000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS_Pos (18UL) /*!< RSTOCS (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS_Msk (0x40000UL) /*!< RSTOCS (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS_Pos (4UL) /*!< DSTOCS (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS_Msk (0x10UL) /*!< DSTOCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS_Pos (8UL) /*!< ECSCS (Bit 8) */ + #define R_XSPI0_INTS_ECSCS_Msk (0x100UL) /*!< ECSCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS_Pos (12UL) /*!< INTCS (Bit 12) */ + #define R_XSPI0_INTS_INTCS_Msk (0x1000UL) /*!< INTCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOFCH_Pos (16UL) /*!< BRGOFCH (Bit 16) */ + #define R_XSPI0_INTS_BRGOFCH_Msk (0x10000UL) /*!< BRGOFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUFCH_Pos (18UL) /*!< BRGUFCH (Bit 18) */ + #define R_XSPI0_INTS_BRGUFCH_Msk (0x40000UL) /*!< BRGUFCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERRCH_Pos (20UL) /*!< BUSERRCH (Bit 20) */ + #define R_XSPI0_INTS_BUSERRCH_Msk (0x100000UL) /*!< BUSERRCH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS_Pos (28UL) /*!< CAFAILCS (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS_Msk (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS_Pos (30UL) /*!< CASUCCS (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS_Msk (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCSC_Pos (4UL) /*!< DSTOCSC (Bit 4) */ + #define R_XSPI0_INTC_DSTOCSC_Msk (0x10UL) /*!< DSTOCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCSC_Pos (8UL) /*!< ECSCSC (Bit 8) */ + #define R_XSPI0_INTC_ECSCSC_Msk (0x100UL) /*!< ECSCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCSC_Pos (12UL) /*!< INTCSC (Bit 12) */ + #define R_XSPI0_INTC_INTCSC_Msk (0x1000UL) /*!< INTCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFCHC_Pos (16UL) /*!< BRGOFCHC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFCHC_Msk (0x10000UL) /*!< BRGOFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFCHC_Pos (18UL) /*!< BRGUFCHC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFCHC_Msk (0x40000UL) /*!< BRGUFCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRCHC_Pos (20UL) /*!< BUSERRCHC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRCHC_Msk (0x100000UL) /*!< BUSERRCHC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCSC_Pos (28UL) /*!< CAFAILCSC (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCSC_Msk (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCSC_Pos (30UL) /*!< CASUCCSC (Bit 30) */ + #define R_XSPI0_INTC_CASUCCSC_Msk (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCSE_Pos (4UL) /*!< DSTOCSE (Bit 4) */ + #define R_XSPI0_INTE_DSTOCSE_Msk (0x10UL) /*!< DSTOCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCSE_Pos (8UL) /*!< ECSCSE (Bit 8) */ + #define R_XSPI0_INTE_ECSCSE_Msk (0x100UL) /*!< ECSCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCSE_Pos (12UL) /*!< INTCSE (Bit 12) */ + #define R_XSPI0_INTE_INTCSE_Msk (0x1000UL) /*!< INTCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFCHE_Pos (16UL) /*!< BRGOFCHE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFCHE_Msk (0x10000UL) /*!< BRGOFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFCHE_Pos (18UL) /*!< BRGUFCHE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFCHE_Msk (0x40000UL) /*!< BRGUFCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRCHE_Pos (20UL) /*!< BUSERRCHE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRCHE_Msk (0x100000UL) /*!< BUSERRCHE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCSE_Pos (28UL) /*!< CAFAILCSE (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCSE_Msk (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCSE_Pos (30UL) /*!< CASUCCSE (Bit 30) */ + #define R_XSPI0_INTE_CASUCCSE_Msk (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_PHY ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= DPHYREFCR ======================================================= */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Pos (0UL) /*!< RFREQ (Bit 0) */ + #define R_MIPI_PHY_DPHYREFCR_RFREQ_Msk (0xffUL) /*!< RFREQ (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYPLFCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Pos (0UL) /*!< IDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYPLFCR_IDIV_Msk (0x3UL) /*!< IDIV (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Pos (8UL) /*!< NFMUL (Bit 8) */ + #define R_MIPI_PHY_DPHYPLFCR_NFMUL_Msk (0x300UL) /*!< NFMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Pos (12UL) /*!< PMUL (Bit 12) */ + #define R_MIPI_PHY_DPHYPLFCR_PMUL_Msk (0x3000UL) /*!< PMUL (Bitfield-Mask: 0x03) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Pos (16UL) /*!< NMUL (Bit 16) */ + #define R_MIPI_PHY_DPHYPLFCR_NMUL_Msk (0x1ff0000UL) /*!< NMUL (Bitfield-Mask: 0x1ff) */ +/* ======================================================= DPHYPLOCR ======================================================= */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_MIPI_PHY_DPHYPLOCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYESCCR ======================================================= */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Pos (0UL) /*!< ESCDIV (Bit 0) */ + #define R_MIPI_PHY_DPHYESCCR_ESCDIV_Msk (0x1fUL) /*!< ESCDIV (Bitfield-Mask: 0x1f) */ +/* ======================================================= DPHYPWRCR ======================================================= */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Pos (0UL) /*!< PWRSEN (Bit 0) */ + #define R_MIPI_PHY_DPHYPWRCR_PWRSEN_Msk (0x1UL) /*!< PWRSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYSFR ======================================================== */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Pos (0UL) /*!< PWRSF (Bit 0) */ + #define R_MIPI_PHY_DPHYSFR_PWRSF_Msk (0x1UL) /*!< PWRSF (Bitfield-Mask: 0x01) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Pos (8UL) /*!< PLLSF (Bit 8) */ + #define R_MIPI_PHY_DPHYSFR_PLLSF_Msk (0x100UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPHYOCR ======================================================== */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Pos (0UL) /*!< DPHYEN (Bit 0) */ + #define R_MIPI_PHY_DPHYOCR_DPHYEN_Msk (0x1UL) /*!< DPHYEN (Bitfield-Mask: 0x01) */ +/* ======================================================= DPHYTIM1 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Pos (0UL) /*!< TINIT (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM1_TINIT_Msk (0x7ffffUL) /*!< TINIT (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DPHYTIM2 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Pos (0UL) /*!< TCLKPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKPREP_Msk (0xffUL) /*!< TCLKPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Pos (8UL) /*!< TCLKSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKSETT_Msk (0xff00UL) /*!< TCLKSETT (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Pos (16UL) /*!< TCLKMISS (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM2_TCLKMISS_Msk (0xff0000UL) /*!< TCLKMISS (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM3 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Pos (0UL) /*!< THSPREP (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM3_THSPREP_Msk (0xffUL) /*!< THSPREP (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Pos (8UL) /*!< THSSETT (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM3_THSSETT_Msk (0xff00UL) /*!< THSSETT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM4 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Pos (0UL) /*!< TCLKZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKZERO_Msk (0xffUL) /*!< TCLKZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Pos (8UL) /*!< TCLKPRE (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPRE_Msk (0xff00UL) /*!< TCLKPRE (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Pos (16UL) /*!< TCLKPOST (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKPOST_Msk (0xff0000UL) /*!< TCLKPOST (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Pos (24UL) /*!< TCLKTRL (Bit 24) */ + #define R_MIPI_PHY_DPHYTIM4_TCLKTRL_Msk (0xff000000UL) /*!< TCLKTRL (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM5 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Pos (0UL) /*!< THSZERO (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM5_THSZERO_Msk (0xffUL) /*!< THSZERO (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Pos (8UL) /*!< THSTRL (Bit 8) */ + #define R_MIPI_PHY_DPHYTIM5_THSTRL_Msk (0xff00UL) /*!< THSTRL (Bitfield-Mask: 0xff) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Pos (16UL) /*!< THSEXIT (Bit 16) */ + #define R_MIPI_PHY_DPHYTIM5_THSEXIT_Msk (0xff0000UL) /*!< THSEXIT (Bitfield-Mask: 0xff) */ +/* ======================================================= DPHYTIM6 ======================================================== */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Pos (0UL) /*!< TLPX (Bit 0) */ + #define R_MIPI_PHY_DPHYTIM6_TLPX_Msk (0xffUL) /*!< TLPX (Bitfield-Mask: 0xff) */ +/* ======================================================== DPHYMDC ======================================================== */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Pos (0UL) /*!< MASTEREN (Bit 0) */ + #define R_MIPI_PHY_DPHYMDC_MASTEREN_Msk (0x1UL) /*!< MASTEREN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_CSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MCG ========================================================== */ + #define R_MIPI_CSI_MCG_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_MIPI_CSI_MCG_VER_Msk (0xfUL) /*!< VER (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCG_SDLN_Pos (8UL) /*!< SDLN (Bit 8) */ + #define R_MIPI_CSI_MCG_SDLN_Msk (0xf00UL) /*!< SDLN (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCG_GSNM_Pos (16UL) /*!< GSNM (Bit 16) */ + #define R_MIPI_CSI_MCG_GSNM_Msk (0xff0000UL) /*!< GSNM (Bitfield-Mask: 0xff) */ +/* ========================================================= MCT0 ========================================================== */ + #define R_MIPI_CSI_MCT0_VDLN_Pos (0UL) /*!< VDLN (Bit 0) */ + #define R_MIPI_CSI_MCT0_VDLN_Msk (0xfUL) /*!< VDLN (Bitfield-Mask: 0x0f) */ + #define R_MIPI_CSI_MCT0_ZLMD_Pos (16UL) /*!< ZLMD (Bit 16) */ + #define R_MIPI_CSI_MCT0_ZLMD_Msk (0x10000UL) /*!< ZLMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_EDMD_Pos (17UL) /*!< EDMD (Bit 17) */ + #define R_MIPI_CSI_MCT0_EDMD_Msk (0x20000UL) /*!< EDMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_RVMD_Pos (19UL) /*!< RVMD (Bit 19) */ + #define R_MIPI_CSI_MCT0_RVMD_Msk (0x80000UL) /*!< RVMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_GRMD_Pos (20UL) /*!< GRMD (Bit 20) */ + #define R_MIPI_CSI_MCT0_GRMD_Msk (0x100000UL) /*!< GRMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_ECCV13_Pos (24UL) /*!< ECCV13 (Bit 24) */ + #define R_MIPI_CSI_MCT0_ECCV13_Msk (0x1000000UL) /*!< ECCV13 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MCT0_LFSREN_Pos (25UL) /*!< LFSREN (Bit 25) */ + #define R_MIPI_CSI_MCT0_LFSREN_Msk (0x2000000UL) /*!< LFSREN (Bitfield-Mask: 0x01) */ +/* ========================================================= MCT2 ========================================================== */ + #define R_MIPI_CSI_MCT2_FRRCLK_Pos (0UL) /*!< FRRCLK (Bit 0) */ + #define R_MIPI_CSI_MCT2_FRRCLK_Msk (0x1ffUL) /*!< FRRCLK (Bitfield-Mask: 0x1ff) */ + #define R_MIPI_CSI_MCT2_FRRSKW_Pos (16UL) /*!< FRRSKW (Bit 16) */ + #define R_MIPI_CSI_MCT2_FRRSKW_Msk (0x1ff0000UL) /*!< FRRSKW (Bitfield-Mask: 0x1ff) */ +/* ========================================================= MCT3 ========================================================== */ + #define R_MIPI_CSI_MCT3_RXEN_Pos (0UL) /*!< RXEN (Bit 0) */ + #define R_MIPI_CSI_MCT3_RXEN_Msk (0x1UL) /*!< RXEN (Bitfield-Mask: 0x01) */ +/* ========================================================= RTCT ========================================================== */ + #define R_MIPI_CSI_RTCT_VSRST_Pos (0UL) /*!< VSRST (Bit 0) */ + #define R_MIPI_CSI_RTCT_VSRST_Msk (0x1UL) /*!< VSRST (Bitfield-Mask: 0x01) */ +/* ========================================================= RTST ========================================================== */ + #define R_MIPI_CSI_RTST_VSRSTS_Pos (0UL) /*!< VSRSTS (Bit 0) */ + #define R_MIPI_CSI_RTST_VSRSTS_Msk (0x1UL) /*!< VSRSTS (Bitfield-Mask: 0x01) */ +/* ========================================================= EPCT ========================================================== */ + #define R_MIPI_CSI_EPCT_SLP_Pos (0UL) /*!< SLP (Bit 0) */ + #define R_MIPI_CSI_EPCT_SLP_Msk (0x7fffUL) /*!< SLP (Bitfield-Mask: 0x7fff) */ + #define R_MIPI_CSI_EPCT_EPDOP_Pos (15UL) /*!< EPDOP (Bit 15) */ + #define R_MIPI_CSI_EPCT_EPDOP_Msk (0x8000UL) /*!< EPDOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_EPCT_SSP_Pos (16UL) /*!< SSP (Bit 16) */ + #define R_MIPI_CSI_EPCT_SSP_Msk (0x7fff0000UL) /*!< SSP (Bitfield-Mask: 0x7fff) */ + #define R_MIPI_CSI_EPCT_EPDEN_Pos (31UL) /*!< EPDEN (Bit 31) */ + #define R_MIPI_CSI_EPCT_EPDEN_Msk (0x80000000UL) /*!< EPDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= EMCT ========================================================== */ + #define R_MIPI_CSI_EMCT_VLSIEN_Pos (4UL) /*!< VLSIEN (Bit 4) */ + #define R_MIPI_CSI_EMCT_VLSIEN_Msk (0x30UL) /*!< VLSIEN (Bitfield-Mask: 0x03) */ + #define R_MIPI_CSI_EMCT_EOTPEN_Pos (6UL) /*!< EOTPEN (Bit 6) */ + #define R_MIPI_CSI_EMCT_EOTPEN_Msk (0x40UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= MIST ========================================================== */ + #define R_MIPI_CSI_MIST_DL0S_Pos (0UL) /*!< DL0S (Bit 0) */ + #define R_MIPI_CSI_MIST_DL0S_Msk (0x1UL) /*!< DL0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_DL1S_Pos (1UL) /*!< DL1S (Bit 1) */ + #define R_MIPI_CSI_MIST_DL1S_Msk (0x2UL) /*!< DL1S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_PMS_Pos (8UL) /*!< PMS (Bit 8) */ + #define R_MIPI_CSI_MIST_PMS_Msk (0x100UL) /*!< PMS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_GSTS_Pos (9UL) /*!< GSTS (Bit 9) */ + #define R_MIPI_CSI_MIST_GSTS_Msk (0x200UL) /*!< GSTS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_RXS_Pos (10UL) /*!< RXS (Bit 10) */ + #define R_MIPI_CSI_MIST_RXS_Msk (0x400UL) /*!< RXS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC0S_Pos (16UL) /*!< VC0S (Bit 16) */ + #define R_MIPI_CSI_MIST_VC0S_Msk (0x10000UL) /*!< VC0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC1S_Pos (17UL) /*!< VC1S (Bit 17) */ + #define R_MIPI_CSI_MIST_VC1S_Msk (0x20000UL) /*!< VC1S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC2S_Pos (18UL) /*!< VC2S (Bit 18) */ + #define R_MIPI_CSI_MIST_VC2S_Msk (0x40000UL) /*!< VC2S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC3S_Pos (19UL) /*!< VC3S (Bit 19) */ + #define R_MIPI_CSI_MIST_VC3S_Msk (0x80000UL) /*!< VC3S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC4S_Pos (20UL) /*!< VC4S (Bit 20) */ + #define R_MIPI_CSI_MIST_VC4S_Msk (0x100000UL) /*!< VC4S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC5S_Pos (21UL) /*!< VC5S (Bit 21) */ + #define R_MIPI_CSI_MIST_VC5S_Msk (0x200000UL) /*!< VC5S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC6S_Pos (22UL) /*!< VC6S (Bit 22) */ + #define R_MIPI_CSI_MIST_VC6S_Msk (0x400000UL) /*!< VC6S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC7S_Pos (23UL) /*!< VC7S (Bit 23) */ + #define R_MIPI_CSI_MIST_VC7S_Msk (0x800000UL) /*!< VC7S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC8S_Pos (24UL) /*!< VC8S (Bit 24) */ + #define R_MIPI_CSI_MIST_VC8S_Msk (0x1000000UL) /*!< VC8S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC9S_Pos (25UL) /*!< VC9S (Bit 25) */ + #define R_MIPI_CSI_MIST_VC9S_Msk (0x2000000UL) /*!< VC9S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC10S_Pos (26UL) /*!< VC10S (Bit 26) */ + #define R_MIPI_CSI_MIST_VC10S_Msk (0x4000000UL) /*!< VC10S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC11S_Pos (27UL) /*!< VC11S (Bit 27) */ + #define R_MIPI_CSI_MIST_VC11S_Msk (0x8000000UL) /*!< VC11S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC12S_Pos (28UL) /*!< VC12S (Bit 28) */ + #define R_MIPI_CSI_MIST_VC12S_Msk (0x10000000UL) /*!< VC12S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC13S_Pos (29UL) /*!< VC13S (Bit 29) */ + #define R_MIPI_CSI_MIST_VC13S_Msk (0x20000000UL) /*!< VC13S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC14S_Pos (30UL) /*!< VC14S (Bit 30) */ + #define R_MIPI_CSI_MIST_VC14S_Msk (0x40000000UL) /*!< VC14S (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_MIST_VC15S_Pos (31UL) /*!< VC15S (Bit 31) */ + #define R_MIPI_CSI_MIST_VC15S_Msk (0x80000000UL) /*!< VC15S (Bitfield-Mask: 0x01) */ +/* ========================================================= DTEL ========================================================== */ + #define R_MIPI_CSI_DTEL_DTEN_Pos (0UL) /*!< DTEN (Bit 0) */ + #define R_MIPI_CSI_DTEL_DTEN_Msk (0xffffffffUL) /*!< DTEN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTEH ========================================================== */ + #define R_MIPI_CSI_DTEH_DTEN_Pos (0UL) /*!< DTEN (Bit 0) */ + #define R_MIPI_CSI_DTEH_DTEN_Msk (0xffffffffUL) /*!< DTEN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RXST ========================================================== */ + #define R_MIPI_CSI_RXST_FRM0_Pos (0UL) /*!< FRM0 (Bit 0) */ + #define R_MIPI_CSI_RXST_FRM0_Msk (0x1UL) /*!< FRM0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM1_Pos (1UL) /*!< FRM1 (Bit 1) */ + #define R_MIPI_CSI_RXST_FRM1_Msk (0x2UL) /*!< FRM1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM2_Pos (2UL) /*!< FRM2 (Bit 2) */ + #define R_MIPI_CSI_RXST_FRM2_Msk (0x4UL) /*!< FRM2 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM3_Pos (3UL) /*!< FRM3 (Bit 3) */ + #define R_MIPI_CSI_RXST_FRM3_Msk (0x8UL) /*!< FRM3 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM4_Pos (4UL) /*!< FRM4 (Bit 4) */ + #define R_MIPI_CSI_RXST_FRM4_Msk (0x10UL) /*!< FRM4 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM5_Pos (5UL) /*!< FRM5 (Bit 5) */ + #define R_MIPI_CSI_RXST_FRM5_Msk (0x20UL) /*!< FRM5 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM6_Pos (6UL) /*!< FRM6 (Bit 6) */ + #define R_MIPI_CSI_RXST_FRM6_Msk (0x40UL) /*!< FRM6 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM7_Pos (7UL) /*!< FRM7 (Bit 7) */ + #define R_MIPI_CSI_RXST_FRM7_Msk (0x80UL) /*!< FRM7 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM8_Pos (8UL) /*!< FRM8 (Bit 8) */ + #define R_MIPI_CSI_RXST_FRM8_Msk (0x100UL) /*!< FRM8 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM9_Pos (9UL) /*!< FRM9 (Bit 9) */ + #define R_MIPI_CSI_RXST_FRM9_Msk (0x200UL) /*!< FRM9 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM10_Pos (10UL) /*!< FRM10 (Bit 10) */ + #define R_MIPI_CSI_RXST_FRM10_Msk (0x400UL) /*!< FRM10 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM11_Pos (11UL) /*!< FRM11 (Bit 11) */ + #define R_MIPI_CSI_RXST_FRM11_Msk (0x800UL) /*!< FRM11 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM12_Pos (12UL) /*!< FRM12 (Bit 12) */ + #define R_MIPI_CSI_RXST_FRM12_Msk (0x1000UL) /*!< FRM12 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM13_Pos (13UL) /*!< FRM13 (Bit 13) */ + #define R_MIPI_CSI_RXST_FRM13_Msk (0x2000UL) /*!< FRM13 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM14_Pos (14UL) /*!< FRM14 (Bit 14) */ + #define R_MIPI_CSI_RXST_FRM14_Msk (0x4000UL) /*!< FRM14 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_FRM15_Pos (15UL) /*!< FRM15 (Bit 15) */ + #define R_MIPI_CSI_RXST_FRM15_Msk (0x8000UL) /*!< FRM15 (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_RACT_Pos (16UL) /*!< RACT (Bit 16) */ + #define R_MIPI_CSI_RXST_RACT_Msk (0x10000UL) /*!< RACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_RXST_RACTDET_Pos (17UL) /*!< RACTDET (Bit 17) */ + #define R_MIPI_CSI_RXST_RACTDET_Msk (0x20000UL) /*!< RACTDET (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSC ========================================================== */ + #define R_MIPI_CSI_RXSC_RACTDETC_Pos (17UL) /*!< RACTDETC (Bit 17) */ + #define R_MIPI_CSI_RXSC_RACTDETC_Msk (0x20000UL) /*!< RACTDETC (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIE ========================================================== */ + #define R_MIPI_CSI_RXIE_RACTDETE_Pos (17UL) /*!< RACTDETE (Bit 17) */ + #define R_MIPI_CSI_RXIE_RACTDETE_Msk (0x20000UL) /*!< RACTDETE (Bitfield-Mask: 0x01) */ +/* ========================================================= DLST0 ========================================================= */ + #define R_MIPI_CSI_DLST0_ESH_Pos (0UL) /*!< ESH (Bit 0) */ + #define R_MIPI_CSI_DLST0_ESH_Msk (0x1UL) /*!< ESH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ESS_Pos (1UL) /*!< ESS (Bit 1) */ + #define R_MIPI_CSI_DLST0_ESS_Msk (0x2UL) /*!< ESS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ECT_Pos (2UL) /*!< ECT (Bit 2) */ + #define R_MIPI_CSI_DLST0_ECT_Msk (0x4UL) /*!< ECT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_EES_Pos (3UL) /*!< EES (Bit 3) */ + #define R_MIPI_CSI_DLST0_EES_Msk (0x8UL) /*!< EES (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_EUL_Pos (16UL) /*!< EUL (Bit 16) */ + #define R_MIPI_CSI_DLST0_EUL_Msk (0x10000UL) /*!< EUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_RUL_Pos (17UL) /*!< RUL (Bit 17) */ + #define R_MIPI_CSI_DLST0_RUL_Msk (0x20000UL) /*!< RUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST0_ULP_Pos (24UL) /*!< ULP (Bit 24) */ + #define R_MIPI_CSI_DLST0_ULP_Msk (0x1000000UL) /*!< ULP (Bitfield-Mask: 0x01) */ +/* ========================================================= DLST1 ========================================================= */ + #define R_MIPI_CSI_DLST1_ESH_Pos (0UL) /*!< ESH (Bit 0) */ + #define R_MIPI_CSI_DLST1_ESH_Msk (0x1UL) /*!< ESH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ESS_Pos (1UL) /*!< ESS (Bit 1) */ + #define R_MIPI_CSI_DLST1_ESS_Msk (0x2UL) /*!< ESS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ECT_Pos (2UL) /*!< ECT (Bit 2) */ + #define R_MIPI_CSI_DLST1_ECT_Msk (0x4UL) /*!< ECT (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_EES_Pos (3UL) /*!< EES (Bit 3) */ + #define R_MIPI_CSI_DLST1_EES_Msk (0x8UL) /*!< EES (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_EUL_Pos (16UL) /*!< EUL (Bit 16) */ + #define R_MIPI_CSI_DLST1_EUL_Msk (0x10000UL) /*!< EUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_RUL_Pos (17UL) /*!< RUL (Bit 17) */ + #define R_MIPI_CSI_DLST1_RUL_Msk (0x20000UL) /*!< RUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLST1_ULP_Pos (24UL) /*!< ULP (Bit 24) */ + #define R_MIPI_CSI_DLST1_ULP_Msk (0x1000000UL) /*!< ULP (Bitfield-Mask: 0x01) */ +/* ========================================================= DLSC0 ========================================================= */ + #define R_MIPI_CSI_DLSC0_ESHC_Pos (0UL) /*!< ESHC (Bit 0) */ + #define R_MIPI_CSI_DLSC0_ESHC_Msk (0x1UL) /*!< ESHC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_ESSC_Pos (1UL) /*!< ESSC (Bit 1) */ + #define R_MIPI_CSI_DLSC0_ESSC_Msk (0x2UL) /*!< ESSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_ECTC_Pos (2UL) /*!< ECTC (Bit 2) */ + #define R_MIPI_CSI_DLSC0_ECTC_Msk (0x4UL) /*!< ECTC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_EESC_Pos (3UL) /*!< EESC (Bit 3) */ + #define R_MIPI_CSI_DLSC0_EESC_Msk (0x8UL) /*!< EESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_EULC_Pos (16UL) /*!< EULC (Bit 16) */ + #define R_MIPI_CSI_DLSC0_EULC_Msk (0x10000UL) /*!< EULC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC0_RULC_Pos (17UL) /*!< RULC (Bit 17) */ + #define R_MIPI_CSI_DLSC0_RULC_Msk (0x20000UL) /*!< RULC (Bitfield-Mask: 0x01) */ +/* ========================================================= DLSC1 ========================================================= */ + #define R_MIPI_CSI_DLSC1_ESHC_Pos (0UL) /*!< ESHC (Bit 0) */ + #define R_MIPI_CSI_DLSC1_ESHC_Msk (0x1UL) /*!< ESHC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_ESSC_Pos (1UL) /*!< ESSC (Bit 1) */ + #define R_MIPI_CSI_DLSC1_ESSC_Msk (0x2UL) /*!< ESSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_ECTC_Pos (2UL) /*!< ECTC (Bit 2) */ + #define R_MIPI_CSI_DLSC1_ECTC_Msk (0x4UL) /*!< ECTC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_EESC_Pos (3UL) /*!< EESC (Bit 3) */ + #define R_MIPI_CSI_DLSC1_EESC_Msk (0x8UL) /*!< EESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_EULC_Pos (16UL) /*!< EULC (Bit 16) */ + #define R_MIPI_CSI_DLSC1_EULC_Msk (0x10000UL) /*!< EULC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLSC1_RULC_Pos (17UL) /*!< RULC (Bit 17) */ + #define R_MIPI_CSI_DLSC1_RULC_Msk (0x20000UL) /*!< RULC (Bitfield-Mask: 0x01) */ +/* ========================================================= DLIE0 ========================================================= */ + #define R_MIPI_CSI_DLIE0_ESHE_Pos (0UL) /*!< ESHE (Bit 0) */ + #define R_MIPI_CSI_DLIE0_ESHE_Msk (0x1UL) /*!< ESHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_ESSE_Pos (1UL) /*!< ESSE (Bit 1) */ + #define R_MIPI_CSI_DLIE0_ESSE_Msk (0x2UL) /*!< ESSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_ECTE_Pos (2UL) /*!< ECTE (Bit 2) */ + #define R_MIPI_CSI_DLIE0_ECTE_Msk (0x4UL) /*!< ECTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_EESE_Pos (3UL) /*!< EESE (Bit 3) */ + #define R_MIPI_CSI_DLIE0_EESE_Msk (0x8UL) /*!< EESE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_EULE_Pos (16UL) /*!< EULE (Bit 16) */ + #define R_MIPI_CSI_DLIE0_EULE_Msk (0x10000UL) /*!< EULE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE0_RULE_Pos (17UL) /*!< RULE (Bit 17) */ + #define R_MIPI_CSI_DLIE0_RULE_Msk (0x20000UL) /*!< RULE (Bitfield-Mask: 0x01) */ +/* ========================================================= DLIE1 ========================================================= */ + #define R_MIPI_CSI_DLIE1_ESHE_Pos (0UL) /*!< ESHE (Bit 0) */ + #define R_MIPI_CSI_DLIE1_ESHE_Msk (0x1UL) /*!< ESHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_ESSE_Pos (1UL) /*!< ESSE (Bit 1) */ + #define R_MIPI_CSI_DLIE1_ESSE_Msk (0x2UL) /*!< ESSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_ECTE_Pos (2UL) /*!< ECTE (Bit 2) */ + #define R_MIPI_CSI_DLIE1_ECTE_Msk (0x4UL) /*!< ECTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_EESE_Pos (3UL) /*!< EESE (Bit 3) */ + #define R_MIPI_CSI_DLIE1_EESE_Msk (0x8UL) /*!< EESE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_EULE_Pos (16UL) /*!< EULE (Bit 16) */ + #define R_MIPI_CSI_DLIE1_EULE_Msk (0x10000UL) /*!< EULE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_DLIE1_RULE_Pos (17UL) /*!< RULE (Bit 17) */ + #define R_MIPI_CSI_DLIE1_RULE_Msk (0x20000UL) /*!< RULE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST0 ========================================================= */ + #define R_MIPI_CSI_VCST0_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST0_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST0_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST0_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST0_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST0_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST0_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST0_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST0_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST0_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST0_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST0_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST0_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST0_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST0_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST0_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST0_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST1 ========================================================= */ + #define R_MIPI_CSI_VCST1_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST1_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST1_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST1_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST1_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST1_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST1_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST1_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST1_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST1_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST1_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST1_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST1_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST1_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST1_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST1_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST1_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST2 ========================================================= */ + #define R_MIPI_CSI_VCST2_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST2_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST2_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST2_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST2_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST2_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST2_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST2_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST2_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST2_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST2_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST2_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST2_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST2_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST2_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST2_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST2_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST3 ========================================================= */ + #define R_MIPI_CSI_VCST3_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST3_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST3_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST3_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST3_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST3_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST3_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST3_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST3_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST3_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST3_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST3_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST3_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST3_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST3_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST3_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST3_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST4 ========================================================= */ + #define R_MIPI_CSI_VCST4_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST4_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST4_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST4_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST4_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST4_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST4_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST4_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST4_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST4_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST4_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST4_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST4_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST4_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST4_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST4_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST4_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST5 ========================================================= */ + #define R_MIPI_CSI_VCST5_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST5_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST5_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST5_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST5_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST5_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST5_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST5_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST5_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST5_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST5_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST5_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST5_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST5_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST5_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST5_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST5_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST6 ========================================================= */ + #define R_MIPI_CSI_VCST6_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST6_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST6_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST6_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST6_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST6_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST6_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST6_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST6_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST6_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST6_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST6_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST6_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST6_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST6_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST6_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST6_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST7 ========================================================= */ + #define R_MIPI_CSI_VCST7_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST7_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST7_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST7_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST7_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST7_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST7_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST7_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST7_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST7_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST7_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST7_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST7_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST7_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST7_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST7_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST7_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST8 ========================================================= */ + #define R_MIPI_CSI_VCST8_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST8_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST8_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST8_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST8_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST8_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST8_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST8_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST8_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST8_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST8_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST8_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST8_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST8_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST8_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST8_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST8_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCST9 ========================================================= */ + #define R_MIPI_CSI_VCST9_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST9_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST9_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST9_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST9_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST9_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST9_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST9_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST9_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST9_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST9_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST9_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST9_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST9_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST9_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST9_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST9_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST10 ========================================================= */ + #define R_MIPI_CSI_VCST10_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST10_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST10_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST10_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST10_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST10_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST10_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST10_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST10_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST10_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST10_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST10_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST10_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST10_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST10_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST10_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST10_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST11 ========================================================= */ + #define R_MIPI_CSI_VCST11_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST11_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST11_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST11_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST11_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST11_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST11_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST11_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST11_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST11_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST11_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST11_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST11_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST11_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST11_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST11_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST11_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST12 ========================================================= */ + #define R_MIPI_CSI_VCST12_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST12_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST12_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST12_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST12_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST12_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST12_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST12_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST12_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST12_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST12_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST12_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST12_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST12_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST12_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST12_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST12_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST13 ========================================================= */ + #define R_MIPI_CSI_VCST13_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST13_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST13_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST13_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST13_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST13_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST13_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST13_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST13_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST13_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST13_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST13_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST13_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST13_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST13_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST13_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST13_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST14 ========================================================= */ + #define R_MIPI_CSI_VCST14_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST14_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST14_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST14_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST14_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST14_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST14_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST14_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST14_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST14_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST14_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST14_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST14_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST14_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST14_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST14_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST14_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ======================================================== VCST15 ========================================================= */ + #define R_MIPI_CSI_VCST15_MLF_Pos (0UL) /*!< MLF (Bit 0) */ + #define R_MIPI_CSI_VCST15_MLF_Msk (0x1UL) /*!< MLF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECD_Pos (1UL) /*!< ECD (Bit 1) */ + #define R_MIPI_CSI_VCST15_ECD_Msk (0x2UL) /*!< ECD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_CRC_Pos (2UL) /*!< CRC (Bit 2) */ + #define R_MIPI_CSI_VCST15_CRC_Msk (0x4UL) /*!< CRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_IDE_Pos (3UL) /*!< IDE (Bit 3) */ + #define R_MIPI_CSI_VCST15_IDE_Msk (0x8UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_WCE_Pos (4UL) /*!< WCE (Bit 4) */ + #define R_MIPI_CSI_VCST15_WCE_Msk (0x10UL) /*!< WCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECC_Pos (5UL) /*!< ECC (Bit 5) */ + #define R_MIPI_CSI_VCST15_ECC_Msk (0x20UL) /*!< ECC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ECN_Pos (6UL) /*!< ECN (Bit 6) */ + #define R_MIPI_CSI_VCST15_ECN_Msk (0x40UL) /*!< ECN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FRS_Pos (8UL) /*!< FRS (Bit 8) */ + #define R_MIPI_CSI_VCST15_FRS_Msk (0x100UL) /*!< FRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FRD_Pos (9UL) /*!< FRD (Bit 9) */ + #define R_MIPI_CSI_VCST15_FRD_Msk (0x200UL) /*!< FRD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_OVF_Pos (16UL) /*!< OVF (Bit 16) */ + #define R_MIPI_CSI_VCST15_OVF_Msk (0x10000UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FSR_Pos (24UL) /*!< FSR (Bit 24) */ + #define R_MIPI_CSI_VCST15_FSR_Msk (0x1000000UL) /*!< FSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_FER_Pos (25UL) /*!< FER (Bit 25) */ + #define R_MIPI_CSI_VCST15_FER_Msk (0x2000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_LSR_Pos (26UL) /*!< LSR (Bit 26) */ + #define R_MIPI_CSI_VCST15_LSR_Msk (0x4000000UL) /*!< LSR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_LER_Pos (27UL) /*!< LER (Bit 27) */ + #define R_MIPI_CSI_VCST15_LER_Msk (0x8000000UL) /*!< LER (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCST15_ETR_Pos (28UL) /*!< ETR (Bit 28) */ + #define R_MIPI_CSI_VCST15_ETR_Msk (0x10000000UL) /*!< ETR (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC0 ========================================================= */ + #define R_MIPI_CSI_VCSC0_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC0_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC0_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC0_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC0_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC0_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC0_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC0_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC0_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC0_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC0_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC0_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC0_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC0_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC0_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC0_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC0_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC0_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC0_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC1 ========================================================= */ + #define R_MIPI_CSI_VCSC1_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC1_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC1_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC1_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC1_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC1_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC1_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC1_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC1_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC1_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC1_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC1_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC1_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC1_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC1_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC1_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC1_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC1_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC1_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC2 ========================================================= */ + #define R_MIPI_CSI_VCSC2_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC2_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC2_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC2_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC2_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC2_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC2_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC2_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC2_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC2_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC2_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC2_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC2_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC2_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC2_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC2_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC2_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC2_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC2_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC3 ========================================================= */ + #define R_MIPI_CSI_VCSC3_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC3_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC3_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC3_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC3_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC3_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC3_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC3_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC3_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC3_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC3_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC3_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC3_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC3_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC3_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC3_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC3_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC3_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC3_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC4 ========================================================= */ + #define R_MIPI_CSI_VCSC4_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC4_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC4_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC4_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC4_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC4_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC4_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC4_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC4_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC4_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC4_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC4_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC4_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC4_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC4_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC4_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC4_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC4_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC4_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC5 ========================================================= */ + #define R_MIPI_CSI_VCSC5_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC5_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC5_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC5_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC5_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC5_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC5_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC5_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC5_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC5_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC5_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC5_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC5_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC5_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC5_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC5_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC5_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC5_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC5_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC6 ========================================================= */ + #define R_MIPI_CSI_VCSC6_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC6_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC6_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC6_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC6_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC6_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC6_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC6_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC6_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC6_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC6_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC6_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC6_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC6_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC6_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC6_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC6_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC6_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC6_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC7 ========================================================= */ + #define R_MIPI_CSI_VCSC7_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC7_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC7_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC7_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC7_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC7_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC7_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC7_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC7_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC7_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC7_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC7_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC7_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC7_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC7_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC7_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC7_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC7_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC7_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC8 ========================================================= */ + #define R_MIPI_CSI_VCSC8_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC8_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC8_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC8_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC8_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC8_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC8_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC8_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC8_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC8_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC8_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC8_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC8_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC8_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC8_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC8_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC8_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC8_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC8_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCSC9 ========================================================= */ + #define R_MIPI_CSI_VCSC9_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC9_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC9_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC9_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC9_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC9_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC9_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC9_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC9_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC9_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC9_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC9_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC9_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC9_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC9_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC9_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC9_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC9_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC9_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC10 ========================================================= */ + #define R_MIPI_CSI_VCSC10_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC10_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC10_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC10_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC10_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC10_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC10_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC10_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC10_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC10_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC10_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC10_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC10_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC10_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC10_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC10_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC10_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC10_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC10_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC11 ========================================================= */ + #define R_MIPI_CSI_VCSC11_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC11_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC11_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC11_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC11_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC11_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC11_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC11_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC11_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC11_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC11_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC11_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC11_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC11_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC11_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC11_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC11_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC11_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC11_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC12 ========================================================= */ + #define R_MIPI_CSI_VCSC12_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC12_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC12_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC12_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC12_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC12_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC12_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC12_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC12_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC12_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC12_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC12_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC12_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC12_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC12_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC12_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC12_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC12_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC12_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC13 ========================================================= */ + #define R_MIPI_CSI_VCSC13_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC13_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC13_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC13_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC13_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC13_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC13_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC13_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC13_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC13_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC13_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC13_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC13_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC13_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC13_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC13_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC13_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC13_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC13_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC14 ========================================================= */ + #define R_MIPI_CSI_VCSC14_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC14_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC14_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC14_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC14_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC14_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC14_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC14_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC14_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC14_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC14_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC14_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC14_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC14_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC14_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC14_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC14_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC14_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC14_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ======================================================== VCSC15 ========================================================= */ + #define R_MIPI_CSI_VCSC15_MLFC_Pos (0UL) /*!< MLFC (Bit 0) */ + #define R_MIPI_CSI_VCSC15_MLFC_Msk (0x1UL) /*!< MLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECDC_Pos (1UL) /*!< ECDC (Bit 1) */ + #define R_MIPI_CSI_VCSC15_ECDC_Msk (0x2UL) /*!< ECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_CRCC_Pos (2UL) /*!< CRCC (Bit 2) */ + #define R_MIPI_CSI_VCSC15_CRCC_Msk (0x4UL) /*!< CRCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_IDEC_Pos (3UL) /*!< IDEC (Bit 3) */ + #define R_MIPI_CSI_VCSC15_IDEC_Msk (0x8UL) /*!< IDEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_WCEC_Pos (4UL) /*!< WCEC (Bit 4) */ + #define R_MIPI_CSI_VCSC15_WCEC_Msk (0x10UL) /*!< WCEC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECCC_Pos (5UL) /*!< ECCC (Bit 5) */ + #define R_MIPI_CSI_VCSC15_ECCC_Msk (0x20UL) /*!< ECCC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ECNC_Pos (6UL) /*!< ECNC (Bit 6) */ + #define R_MIPI_CSI_VCSC15_ECNC_Msk (0x40UL) /*!< ECNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FRSC_Pos (8UL) /*!< FRSC (Bit 8) */ + #define R_MIPI_CSI_VCSC15_FRSC_Msk (0x100UL) /*!< FRSC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FRDC_Pos (9UL) /*!< FRDC (Bit 9) */ + #define R_MIPI_CSI_VCSC15_FRDC_Msk (0x200UL) /*!< FRDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_AMLFC_Pos (14UL) /*!< AMLFC (Bit 14) */ + #define R_MIPI_CSI_VCSC15_AMLFC_Msk (0x4000UL) /*!< AMLFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_AECDC_Pos (15UL) /*!< AECDC (Bit 15) */ + #define R_MIPI_CSI_VCSC15_AECDC_Msk (0x8000UL) /*!< AECDC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_OVFC_Pos (16UL) /*!< OVFC (Bit 16) */ + #define R_MIPI_CSI_VCSC15_OVFC_Msk (0x10000UL) /*!< OVFC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FSRC_Pos (24UL) /*!< FSRC (Bit 24) */ + #define R_MIPI_CSI_VCSC15_FSRC_Msk (0x1000000UL) /*!< FSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_FERC_Pos (25UL) /*!< FERC (Bit 25) */ + #define R_MIPI_CSI_VCSC15_FERC_Msk (0x2000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_LSRC_Pos (26UL) /*!< LSRC (Bit 26) */ + #define R_MIPI_CSI_VCSC15_LSRC_Msk (0x4000000UL) /*!< LSRC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_LERC_Pos (27UL) /*!< LERC (Bit 27) */ + #define R_MIPI_CSI_VCSC15_LERC_Msk (0x8000000UL) /*!< LERC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCSC15_ETRC_Pos (28UL) /*!< ETRC (Bit 28) */ + #define R_MIPI_CSI_VCSC15_ETRC_Msk (0x10000000UL) /*!< ETRC (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE0 ========================================================= */ + #define R_MIPI_CSI_VCIE0_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE0_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE0_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE0_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE0_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE0_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE0_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE0_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE0_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE0_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE0_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE0_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE0_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE0_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE0_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE0_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE0_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE1 ========================================================= */ + #define R_MIPI_CSI_VCIE1_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE1_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE1_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE1_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE1_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE1_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE1_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE1_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE1_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE1_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE1_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE1_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE1_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE1_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE1_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE1_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE1_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE2 ========================================================= */ + #define R_MIPI_CSI_VCIE2_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE2_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE2_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE2_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE2_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE2_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE2_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE2_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE2_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE2_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE2_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE2_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE2_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE2_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE2_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE2_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE2_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE3 ========================================================= */ + #define R_MIPI_CSI_VCIE3_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE3_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE3_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE3_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE3_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE3_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE3_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE3_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE3_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE3_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE3_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE3_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE3_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE3_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE3_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE3_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE3_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE4 ========================================================= */ + #define R_MIPI_CSI_VCIE4_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE4_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE4_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE4_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE4_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE4_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE4_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE4_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE4_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE4_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE4_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE4_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE4_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE4_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE4_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE4_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE4_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE5 ========================================================= */ + #define R_MIPI_CSI_VCIE5_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE5_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE5_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE5_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE5_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE5_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE5_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE5_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE5_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE5_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE5_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE5_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE5_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE5_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE5_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE5_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE5_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE6 ========================================================= */ + #define R_MIPI_CSI_VCIE6_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE6_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE6_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE6_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE6_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE6_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE6_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE6_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE6_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE6_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE6_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE6_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE6_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE6_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE6_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE6_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE6_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE7 ========================================================= */ + #define R_MIPI_CSI_VCIE7_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE7_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE7_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE7_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE7_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE7_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE7_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE7_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE7_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE7_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE7_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE7_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE7_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE7_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE7_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE7_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE7_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE8 ========================================================= */ + #define R_MIPI_CSI_VCIE8_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE8_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE8_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE8_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE8_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE8_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE8_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE8_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE8_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE8_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE8_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE8_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE8_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE8_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE8_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE8_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE8_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= VCIE9 ========================================================= */ + #define R_MIPI_CSI_VCIE9_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE9_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE9_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE9_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE9_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE9_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE9_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE9_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE9_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE9_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE9_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE9_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE9_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE9_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE9_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE9_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE9_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE10 ========================================================= */ + #define R_MIPI_CSI_VCIE10_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE10_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE10_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE10_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE10_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE10_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE10_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE10_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE10_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE10_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE10_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE10_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE10_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE10_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE10_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE10_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE10_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE11 ========================================================= */ + #define R_MIPI_CSI_VCIE11_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE11_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE11_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE11_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE11_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE11_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE11_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE11_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE11_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE11_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE11_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE11_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE11_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE11_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE11_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE11_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE11_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE12 ========================================================= */ + #define R_MIPI_CSI_VCIE12_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE12_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE12_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE12_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE12_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE12_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE12_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE12_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE12_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE12_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE12_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE12_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE12_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE12_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE12_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE12_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE12_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE13 ========================================================= */ + #define R_MIPI_CSI_VCIE13_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE13_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE13_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE13_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE13_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE13_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE13_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE13_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE13_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE13_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE13_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE13_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE13_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE13_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE13_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE13_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE13_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE14 ========================================================= */ + #define R_MIPI_CSI_VCIE14_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE14_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE14_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE14_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE14_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE14_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE14_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE14_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE14_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE14_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE14_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE14_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE14_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE14_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE14_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE14_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE14_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ======================================================== VCIE15 ========================================================= */ + #define R_MIPI_CSI_VCIE15_MLFE_Pos (0UL) /*!< MLFE (Bit 0) */ + #define R_MIPI_CSI_VCIE15_MLFE_Msk (0x1UL) /*!< MLFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECDE_Pos (1UL) /*!< ECDE (Bit 1) */ + #define R_MIPI_CSI_VCIE15_ECDE_Msk (0x2UL) /*!< ECDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_CRCE_Pos (2UL) /*!< CRCE (Bit 2) */ + #define R_MIPI_CSI_VCIE15_CRCE_Msk (0x4UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_IDEE_Pos (3UL) /*!< IDEE (Bit 3) */ + #define R_MIPI_CSI_VCIE15_IDEE_Msk (0x8UL) /*!< IDEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_WCEE_Pos (4UL) /*!< WCEE (Bit 4) */ + #define R_MIPI_CSI_VCIE15_WCEE_Msk (0x10UL) /*!< WCEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECCE_Pos (5UL) /*!< ECCE (Bit 5) */ + #define R_MIPI_CSI_VCIE15_ECCE_Msk (0x20UL) /*!< ECCE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ECNE_Pos (6UL) /*!< ECNE (Bit 6) */ + #define R_MIPI_CSI_VCIE15_ECNE_Msk (0x40UL) /*!< ECNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FRSE_Pos (8UL) /*!< FRSE (Bit 8) */ + #define R_MIPI_CSI_VCIE15_FRSE_Msk (0x100UL) /*!< FRSE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FRDE_Pos (9UL) /*!< FRDE (Bit 9) */ + #define R_MIPI_CSI_VCIE15_FRDE_Msk (0x200UL) /*!< FRDE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_OVFE_Pos (16UL) /*!< OVFE (Bit 16) */ + #define R_MIPI_CSI_VCIE15_OVFE_Msk (0x10000UL) /*!< OVFE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FSRE_Pos (24UL) /*!< FSRE (Bit 24) */ + #define R_MIPI_CSI_VCIE15_FSRE_Msk (0x1000000UL) /*!< FSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_FERE_Pos (25UL) /*!< FERE (Bit 25) */ + #define R_MIPI_CSI_VCIE15_FERE_Msk (0x2000000UL) /*!< FERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_LSRE_Pos (26UL) /*!< LSRE (Bit 26) */ + #define R_MIPI_CSI_VCIE15_LSRE_Msk (0x4000000UL) /*!< LSRE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_LERE_Pos (27UL) /*!< LERE (Bit 27) */ + #define R_MIPI_CSI_VCIE15_LERE_Msk (0x8000000UL) /*!< LERE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_VCIE15_ETRE_Pos (28UL) /*!< ETRE (Bit 28) */ + #define R_MIPI_CSI_VCIE15_ETRE_Msk (0x10000000UL) /*!< ETRE (Bitfield-Mask: 0x01) */ +/* ========================================================= PMST ========================================================== */ + #define R_MIPI_CSI_PMST_DSX_Pos (0UL) /*!< DSX (Bit 0) */ + #define R_MIPI_CSI_PMST_DSX_Msk (0x1UL) /*!< DSX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DSN_Pos (1UL) /*!< DSN (Bit 1) */ + #define R_MIPI_CSI_PMST_DSN_Msk (0x2UL) /*!< DSN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CSX_Pos (2UL) /*!< CSX (Bit 2) */ + #define R_MIPI_CSI_PMST_CSX_Msk (0x4UL) /*!< CSX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CSN_Pos (3UL) /*!< CSN (Bit 3) */ + #define R_MIPI_CSI_PMST_CSN_Msk (0x8UL) /*!< CSN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DUX_Pos (4UL) /*!< DUX (Bit 4) */ + #define R_MIPI_CSI_PMST_DUX_Msk (0x10UL) /*!< DUX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DUN_Pos (5UL) /*!< DUN (Bit 5) */ + #define R_MIPI_CSI_PMST_DUN_Msk (0x20UL) /*!< DUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CUX_Pos (6UL) /*!< CUX (Bit 6) */ + #define R_MIPI_CSI_PMST_CUX_Msk (0x40UL) /*!< CUX (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CUN_Pos (7UL) /*!< CUN (Bit 7) */ + #define R_MIPI_CSI_PMST_CUN_Msk (0x80UL) /*!< CUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CLSS_Pos (14UL) /*!< CLSS (Bit 14) */ + #define R_MIPI_CSI_PMST_CLSS_Msk (0x4000UL) /*!< CLSS (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_CLUL_Pos (15UL) /*!< CLUL (Bit 15) */ + #define R_MIPI_CSI_PMST_CLUL_Msk (0x8000UL) /*!< CLUL (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMST_DLSS_Pos (16UL) /*!< DLSS (Bit 16) */ + #define R_MIPI_CSI_PMST_DLSS_Msk (0x30000UL) /*!< DLSS (Bitfield-Mask: 0x03) */ + #define R_MIPI_CSI_PMST_DLUL_Pos (24UL) /*!< DLUL (Bit 24) */ + #define R_MIPI_CSI_PMST_DLUL_Msk (0x3000000UL) /*!< DLUL (Bitfield-Mask: 0x03) */ +/* ========================================================= PMSC ========================================================== */ + #define R_MIPI_CSI_PMSC_DSXC_Pos (0UL) /*!< DSXC (Bit 0) */ + #define R_MIPI_CSI_PMSC_DSXC_Msk (0x1UL) /*!< DSXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DSNC_Pos (1UL) /*!< DSNC (Bit 1) */ + #define R_MIPI_CSI_PMSC_DSNC_Msk (0x2UL) /*!< DSNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CSXC_Pos (2UL) /*!< CSXC (Bit 2) */ + #define R_MIPI_CSI_PMSC_CSXC_Msk (0x4UL) /*!< CSXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CSNC_Pos (3UL) /*!< CSNC (Bit 3) */ + #define R_MIPI_CSI_PMSC_CSNC_Msk (0x8UL) /*!< CSNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DUXC_Pos (4UL) /*!< DUXC (Bit 4) */ + #define R_MIPI_CSI_PMSC_DUXC_Msk (0x10UL) /*!< DUXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_DUNC_Pos (5UL) /*!< DUNC (Bit 5) */ + #define R_MIPI_CSI_PMSC_DUNC_Msk (0x20UL) /*!< DUNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CUXC_Pos (6UL) /*!< CUXC (Bit 6) */ + #define R_MIPI_CSI_PMSC_CUXC_Msk (0x40UL) /*!< CUXC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMSC_CUNC_Pos (7UL) /*!< CUNC (Bit 7) */ + #define R_MIPI_CSI_PMSC_CUNC_Msk (0x80UL) /*!< CUNC (Bitfield-Mask: 0x01) */ +/* ========================================================= PMIE ========================================================== */ + #define R_MIPI_CSI_PMIE_DSXE_Pos (0UL) /*!< DSXE (Bit 0) */ + #define R_MIPI_CSI_PMIE_DSXE_Msk (0x1UL) /*!< DSXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DSNE_Pos (1UL) /*!< DSNE (Bit 1) */ + #define R_MIPI_CSI_PMIE_DSNE_Msk (0x2UL) /*!< DSNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CSXE_Pos (2UL) /*!< CSXE (Bit 2) */ + #define R_MIPI_CSI_PMIE_CSXE_Msk (0x4UL) /*!< CSXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CSNE_Pos (3UL) /*!< CSNE (Bit 3) */ + #define R_MIPI_CSI_PMIE_CSNE_Msk (0x8UL) /*!< CSNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DUXE_Pos (4UL) /*!< DUXE (Bit 4) */ + #define R_MIPI_CSI_PMIE_DUXE_Msk (0x10UL) /*!< DUXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_DUNE_Pos (5UL) /*!< DUNE (Bit 5) */ + #define R_MIPI_CSI_PMIE_DUNE_Msk (0x20UL) /*!< DUNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CUXE_Pos (6UL) /*!< CUXE (Bit 6) */ + #define R_MIPI_CSI_PMIE_CUXE_Msk (0x40UL) /*!< CUXE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_PMIE_CUNE_Pos (7UL) /*!< CUNE (Bit 7) */ + #define R_MIPI_CSI_PMIE_CUNE_Msk (0x80UL) /*!< CUNE (Bitfield-Mask: 0x01) */ +/* ========================================================= GSCT ========================================================== */ + #define R_MIPI_CSI_GSCT_SHTH_Pos (0UL) /*!< SHTH (Bit 0) */ + #define R_MIPI_CSI_GSCT_SHTH_Msk (0x7fUL) /*!< SHTH (Bitfield-Mask: 0x7f) */ + #define R_MIPI_CSI_GSCT_GFIF_Pos (16UL) /*!< GFIF (Bit 16) */ + #define R_MIPI_CSI_GSCT_GFIF_Msk (0x10000UL) /*!< GFIF (Bitfield-Mask: 0x01) */ +/* ========================================================= GSST ========================================================== */ + #define R_MIPI_CSI_GSST_GNE_Pos (0UL) /*!< GNE (Bit 0) */ + #define R_MIPI_CSI_GSST_GNE_Msk (0x1UL) /*!< GNE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_GTH_Pos (1UL) /*!< GTH (Bit 1) */ + #define R_MIPI_CSI_GSST_GTH_Msk (0x2UL) /*!< GTH (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_GOV_Pos (4UL) /*!< GOV (Bit 4) */ + #define R_MIPI_CSI_GSST_GOV_Msk (0x10UL) /*!< GOV (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_MIPI_CSI_GSST_PNUM_Msk (0xff00UL) /*!< PNUM (Bitfield-Mask: 0xff) */ + #define R_MIPI_CSI_GSST_GCD_Pos (16UL) /*!< GCD (Bit 16) */ + #define R_MIPI_CSI_GSST_GCD_Msk (0x10000UL) /*!< GCD (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSST_STRDS_Pos (17UL) /*!< STRDS (Bit 17) */ + #define R_MIPI_CSI_GSST_STRDS_Msk (0x20000UL) /*!< STRDS (Bitfield-Mask: 0x01) */ +/* ========================================================= GSSC ========================================================== */ + #define R_MIPI_CSI_GSSC_GOVC_Pos (4UL) /*!< GOVC (Bit 4) */ + #define R_MIPI_CSI_GSSC_GOVC_Msk (0x10UL) /*!< GOVC (Bitfield-Mask: 0x01) */ +/* ========================================================= GSIE ========================================================== */ + #define R_MIPI_CSI_GSIE_GNEE_Pos (0UL) /*!< GNEE (Bit 0) */ + #define R_MIPI_CSI_GSIE_GNEE_Msk (0x1UL) /*!< GNEE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIE_GTHE_Pos (1UL) /*!< GTHE (Bit 1) */ + #define R_MIPI_CSI_GSIE_GTHE_Msk (0x2UL) /*!< GTHE (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIE_GOVE_Pos (4UL) /*!< GOVE (Bit 4) */ + #define R_MIPI_CSI_GSIE_GOVE_Msk (0x10UL) /*!< GOVE (Bitfield-Mask: 0x01) */ +/* ========================================================= GSHT ========================================================== */ + #define R_MIPI_CSI_GSHT_SPDT_Pos (0UL) /*!< SPDT (Bit 0) */ + #define R_MIPI_CSI_GSHT_SPDT_Msk (0xffffUL) /*!< SPDT (Bitfield-Mask: 0xffff) */ + #define R_MIPI_CSI_GSHT_DTYP_Pos (16UL) /*!< DTYP (Bit 16) */ + #define R_MIPI_CSI_GSHT_DTYP_Msk (0x3f0000UL) /*!< DTYP (Bitfield-Mask: 0x3f) */ + #define R_MIPI_CSI_GSHT_SPVC_Pos (24UL) /*!< SPVC (Bit 24) */ + #define R_MIPI_CSI_GSHT_SPVC_Msk (0xf000000UL) /*!< SPVC (Bitfield-Mask: 0x0f) */ +/* ========================================================= GSIU ========================================================== */ + #define R_MIPI_CSI_GSIU_FINC_Pos (0UL) /*!< FINC (Bit 0) */ + #define R_MIPI_CSI_GSIU_FINC_Msk (0x1UL) /*!< FINC (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIU_GFCLR_Pos (8UL) /*!< GFCLR (Bit 8) */ + #define R_MIPI_CSI_GSIU_GFCLR_Msk (0x100UL) /*!< GFCLR (Bitfield-Mask: 0x01) */ + #define R_MIPI_CSI_GSIU_GFEN_Pos (16UL) /*!< GFEN (Bit 16) */ + #define R_MIPI_CSI_GSIU_GFEN_Msk (0x10000UL) /*!< GFEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CAPSR ========================================================= */ + #define R_CEU_CAPSR_CE_Pos (0UL) /*!< CE (Bit 0) */ + #define R_CEU_CAPSR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPSR_CPKIL_Pos (16UL) /*!< CPKIL (Bit 16) */ + #define R_CEU_CAPSR_CPKIL_Msk (0x10000UL) /*!< CPKIL (Bitfield-Mask: 0x01) */ +/* ========================================================= CAPCR ========================================================= */ + #define R_CEU_CAPCR_CTNCP_Pos (16UL) /*!< CTNCP (Bit 16) */ + #define R_CEU_CAPCR_CTNCP_Msk (0x10000UL) /*!< CTNCP (Bitfield-Mask: 0x01) */ + #define R_CEU_CAPCR_MTCM_Pos (20UL) /*!< MTCM (Bit 20) */ + #define R_CEU_CAPCR_MTCM_Msk (0x300000UL) /*!< MTCM (Bitfield-Mask: 0x03) */ + #define R_CEU_CAPCR_FDRP_Pos (24UL) /*!< FDRP (Bit 24) */ + #define R_CEU_CAPCR_FDRP_Msk (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff) */ +/* ========================================================= CAMCR ========================================================= */ + #define R_CEU_CAMCR_HDPOL_Pos (0UL) /*!< HDPOL (Bit 0) */ + #define R_CEU_CAMCR_HDPOL_Msk (0x1UL) /*!< HDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDPOL_Pos (1UL) /*!< VDPOL (Bit 1) */ + #define R_CEU_CAMCR_VDPOL_Msk (0x2UL) /*!< VDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_JPG_Pos (4UL) /*!< JPG (Bit 4) */ + #define R_CEU_CAMCR_JPG_Msk (0x30UL) /*!< JPG (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTARY_Pos (8UL) /*!< DTARY (Bit 8) */ + #define R_CEU_CAMCR_DTARY_Msk (0x300UL) /*!< DTARY (Bitfield-Mask: 0x03) */ + #define R_CEU_CAMCR_DTIF_Pos (12UL) /*!< DTIF (Bit 12) */ + #define R_CEU_CAMCR_DTIF_Msk (0x1000UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDPOL_Pos (16UL) /*!< FLDPOL (Bit 16) */ + #define R_CEU_CAMCR_FLDPOL_Msk (0x10000UL) /*!< FLDPOL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_DSEL_Pos (24UL) /*!< DSEL (Bit 24) */ + #define R_CEU_CAMCR_DSEL_Msk (0x1000000UL) /*!< DSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_FLDSEL_Pos (25UL) /*!< FLDSEL (Bit 25) */ + #define R_CEU_CAMCR_FLDSEL_Msk (0x2000000UL) /*!< FLDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_HDSEL_Pos (26UL) /*!< HDSEL (Bit 26) */ + #define R_CEU_CAMCR_HDSEL_Msk (0x4000000UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_CEU_CAMCR_VDSEL_Pos (27UL) /*!< VDSEL (Bit 27) */ + #define R_CEU_CAMCR_VDSEL_Msk (0x8000000UL) /*!< VDSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCYR ========================================================= */ + #define R_CEU_CMCYR_HCYL_Pos (0UL) /*!< HCYL (Bit 0) */ + #define R_CEU_CMCYR_HCYL_Msk (0x3fffUL) /*!< HCYL (Bitfield-Mask: 0x3fff) */ + #define R_CEU_CMCYR_VCYL_Pos (16UL) /*!< VCYL (Bit 16) */ + #define R_CEU_CMCYR_VCYL_Msk (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff) */ +/* ========================================================= CAMOR ========================================================= */ + #define R_CEU_CAMOR_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAPWR ========================================================= */ + #define R_CEU_CAPWR_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ========================================================= CAIFR ========================================================= */ + #define R_CEU_CAIFR_FCI_Pos (0UL) /*!< FCI (Bit 0) */ + #define R_CEU_CAIFR_FCI_Msk (0x3UL) /*!< FCI (Bitfield-Mask: 0x03) */ + #define R_CEU_CAIFR_CIM_Pos (4UL) /*!< CIM (Bit 4) */ + #define R_CEU_CAIFR_CIM_Msk (0x10UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_CEU_CAIFR_IFS_Pos (8UL) /*!< IFS (Bit 8) */ + #define R_CEU_CAIFR_IFS_Msk (0x100UL) /*!< IFS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCNTR ========================================================= */ + #define R_CEU_CRCNTR_RC_Pos (0UL) /*!< RC (Bit 0) */ + #define R_CEU_CRCNTR_RC_Msk (0x1UL) /*!< RC (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_CEU_CRCNTR_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_CEU_CRCNTR_RVS_Pos (4UL) /*!< RVS (Bit 4) */ + #define R_CEU_CRCNTR_RVS_Msk (0x10UL) /*!< RVS (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCMPR ========================================================= */ + #define R_CEU_CRCMPR_RA_Pos (0UL) /*!< RA (Bit 0) */ + #define R_CEU_CRCMPR_RA_Msk (0x1UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ========================================================= CFLCR ========================================================= */ + #define R_CEU_CFLCR_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFSZR ========================================================= */ + #define R_CEU_CFSZR_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ========================================================= CDWDR ========================================================= */ + #define R_CEU_CDWDR_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ========================================================= CDAYR ========================================================= */ + #define R_CEU_CDAYR_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDACR ========================================================= */ + #define R_CEU_CDACR_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBYR ========================================================= */ + #define R_CEU_CDBYR_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDBCR ========================================================= */ + #define R_CEU_CDBCR_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CBDSR ========================================================= */ + #define R_CEU_CBDSR_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= CFWCR ========================================================= */ + #define R_CEU_CFWCR_FWE_Pos (0UL) /*!< FWE (Bit 0) */ + #define R_CEU_CFWCR_FWE_Msk (0x1UL) /*!< FWE (Bitfield-Mask: 0x01) */ + #define R_CEU_CFWCR_FWV_Pos (5UL) /*!< FWV (Bit 5) */ + #define R_CEU_CFWCR_FWV_Msk (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff) */ +/* ========================================================= CLFCR ========================================================= */ + #define R_CEU_CLFCR_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ========================================================= CDOCR ========================================================= */ + #define R_CEU_CDOCR_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ========================================================= CEIER ========================================================= */ + #define R_CEU_CEIER_CPEIE_Pos (0UL) /*!< CPEIE (Bit 0) */ + #define R_CEU_CEIER_CPEIE_Msk (0x1UL) /*!< CPEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CFEIE_Pos (1UL) /*!< CFEIE (Bit 1) */ + #define R_CEU_CEIER_CFEIE_Msk (0x2UL) /*!< CFEIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGRWIE_Pos (4UL) /*!< IGRWIE (Bit 4) */ + #define R_CEU_CEIER_IGRWIE_Msk (0x10UL) /*!< IGRWIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_HDIE_Pos (8UL) /*!< HDIE (Bit 8) */ + #define R_CEU_CEIER_HDIE_Msk (0x100UL) /*!< HDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VDIE_Pos (9UL) /*!< VDIE (Bit 9) */ + #define R_CEU_CEIER_VDIE_Msk (0x200UL) /*!< VDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE1IE_Pos (12UL) /*!< CPBE1IE (Bit 12) */ + #define R_CEU_CEIER_CPBE1IE_Msk (0x1000UL) /*!< CPBE1IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE2IE_Pos (13UL) /*!< CPBE2IE (Bit 13) */ + #define R_CEU_CEIER_CPBE2IE_Msk (0x2000UL) /*!< CPBE2IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE3IE_Pos (14UL) /*!< CPBE3IE (Bit 14) */ + #define R_CEU_CEIER_CPBE3IE_Msk (0x4000UL) /*!< CPBE3IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CPBE4IE_Pos (15UL) /*!< CPBE4IE (Bit 15) */ + #define R_CEU_CEIER_CPBE4IE_Msk (0x8000UL) /*!< CPBE4IE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_CDTOFIE_Pos (16UL) /*!< CDTOFIE (Bit 16) */ + #define R_CEU_CEIER_CDTOFIE_Msk (0x10000UL) /*!< CDTOFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGHSIE_Pos (17UL) /*!< IGHSIE (Bit 17) */ + #define R_CEU_CEIER_IGHSIE_Msk (0x20000UL) /*!< IGHSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_IGVSIE_Pos (18UL) /*!< IGVSIE (Bit 18) */ + #define R_CEU_CEIER_IGVSIE_Msk (0x40000UL) /*!< IGVSIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_VBPIE_Pos (20UL) /*!< VBPIE (Bit 20) */ + #define R_CEU_CEIER_VBPIE_Msk (0x100000UL) /*!< VBPIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_FWFIE_Pos (23UL) /*!< FWFIE (Bit 23) */ + #define R_CEU_CEIER_FWFIE_Msk (0x800000UL) /*!< FWFIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NHDIE_Pos (24UL) /*!< NHDIE (Bit 24) */ + #define R_CEU_CEIER_NHDIE_Msk (0x1000000UL) /*!< NHDIE (Bitfield-Mask: 0x01) */ + #define R_CEU_CEIER_NVDIE_Pos (25UL) /*!< NVDIE (Bit 25) */ + #define R_CEU_CEIER_NVDIE_Msk (0x2000000UL) /*!< NVDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETCR ========================================================= */ + #define R_CEU_CETCR_CPE_Pos (0UL) /*!< CPE (Bit 0) */ + #define R_CEU_CETCR_CPE_Msk (0x1UL) /*!< CPE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CFE_Pos (1UL) /*!< CFE (Bit 1) */ + #define R_CEU_CETCR_CFE_Msk (0x2UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGRW_Pos (4UL) /*!< IGRW (Bit 4) */ + #define R_CEU_CETCR_IGRW_Msk (0x10UL) /*!< IGRW (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_HD_Pos (8UL) /*!< HD (Bit 8) */ + #define R_CEU_CETCR_HD_Msk (0x100UL) /*!< HD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VD_Pos (9UL) /*!< VD (Bit 9) */ + #define R_CEU_CETCR_VD_Msk (0x200UL) /*!< VD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE1_Pos (12UL) /*!< CPBE1 (Bit 12) */ + #define R_CEU_CETCR_CPBE1_Msk (0x1000UL) /*!< CPBE1 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE2_Pos (13UL) /*!< CPBE2 (Bit 13) */ + #define R_CEU_CETCR_CPBE2_Msk (0x2000UL) /*!< CPBE2 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE3_Pos (14UL) /*!< CPBE3 (Bit 14) */ + #define R_CEU_CETCR_CPBE3_Msk (0x4000UL) /*!< CPBE3 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CPBE4_Pos (15UL) /*!< CPBE4 (Bit 15) */ + #define R_CEU_CETCR_CPBE4_Msk (0x8000UL) /*!< CPBE4 (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_CDTOF_Pos (16UL) /*!< CDTOF (Bit 16) */ + #define R_CEU_CETCR_CDTOF_Msk (0x10000UL) /*!< CDTOF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGHS_Pos (17UL) /*!< IGHS (Bit 17) */ + #define R_CEU_CETCR_IGHS_Msk (0x20000UL) /*!< IGHS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_IGVS_Pos (18UL) /*!< IGVS (Bit 18) */ + #define R_CEU_CETCR_IGVS_Msk (0x40000UL) /*!< IGVS (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_VBP_Pos (20UL) /*!< VBP (Bit 20) */ + #define R_CEU_CETCR_VBP_Msk (0x100000UL) /*!< VBP (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_FWF_Pos (23UL) /*!< FWF (Bit 23) */ + #define R_CEU_CETCR_FWF_Msk (0x800000UL) /*!< FWF (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NHD_Pos (24UL) /*!< NHD (Bit 24) */ + #define R_CEU_CETCR_NHD_Msk (0x1000000UL) /*!< NHD (Bitfield-Mask: 0x01) */ + #define R_CEU_CETCR_NVD_Pos (25UL) /*!< NVD (Bit 25) */ + #define R_CEU_CETCR_NVD_Msk (0x2000000UL) /*!< NVD (Bitfield-Mask: 0x01) */ +/* ========================================================= CSTSR ========================================================= */ + #define R_CEU_CSTSR_CPTON_Pos (0UL) /*!< CPTON (Bit 0) */ + #define R_CEU_CSTSR_CPTON_Msk (0x1UL) /*!< CPTON (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CPFLD_Pos (16UL) /*!< CPFLD (Bit 16) */ + #define R_CEU_CSTSR_CPFLD_Msk (0x10000UL) /*!< CPFLD (Bitfield-Mask: 0x01) */ + #define R_CEU_CSTSR_CRST_Pos (24UL) /*!< CRST (Bit 24) */ + #define R_CEU_CSTSR_CRST_Msk (0x1000000UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CDSSR ========================================================= */ + #define R_CEU_CDSSR_CDSS_Pos (0UL) /*!< CDSS (Bit 0) */ + #define R_CEU_CDSSR_CDSS_Msk (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDAYR2 ========================================================= */ + #define R_CEU_CDAYR2_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR2 ========================================================= */ + #define R_CEU_CDACR2_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR2 ========================================================= */ + #define R_CEU_CDBYR2_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR2 ========================================================= */ + #define R_CEU_CDBCR2_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== AXIBUSCTL2 ======================================================= */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Pos (0UL) /*!< AWCACHE (Bit 0) */ + #define R_CEU_AXIBUSCTL2_AWCACHE_Msk (0xfUL) /*!< AWCACHE (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAMOR_B ======================================================== */ + #define R_CEU_CAMOR_B_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_B_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_B_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_B_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_B ======================================================== */ + #define R_CEU_CAPWR_B_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_B_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_B_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_B_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_B ======================================================== */ + #define R_CEU_CFLCR_B_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_B_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_B_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_B_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_B_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_B_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_B_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_B ======================================================== */ + #define R_CEU_CFSZR_B_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_B_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_B_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_B_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_B ======================================================== */ + #define R_CEU_CDWDR_B_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_B_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_B ======================================================== */ + #define R_CEU_CDAYR_B_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_B_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_B ======================================================== */ + #define R_CEU_CDACR_B_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_B_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_B ======================================================== */ + #define R_CEU_CDBYR_B_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_B_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_B ======================================================== */ + #define R_CEU_CDBCR_B_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_B_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_B ======================================================== */ + #define R_CEU_CBDSR_B_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_B_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_B ======================================================== */ + #define R_CEU_CLFCR_B_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_B_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_B ======================================================== */ + #define R_CEU_CDOCR_B_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_B_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_B_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_B_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_B_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_B_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_B_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_B ======================================================== */ + #define R_CEU_CDAYR2_B_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_B_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_B ======================================================== */ + #define R_CEU_CDACR2_B_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_B_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_B ======================================================== */ + #define R_CEU_CDBYR2_B_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_B_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_B ======================================================== */ + #define R_CEU_CDBCR2_B_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_B_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAMOR_M ======================================================== */ + #define R_CEU_CAMOR_M_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */ + #define R_CEU_CAMOR_M_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAMOR_M_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */ + #define R_CEU_CAMOR_M_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */ +/* ======================================================== CAPWR_M ======================================================== */ + #define R_CEU_CAPWR_M_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */ + #define R_CEU_CAPWR_M_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */ + #define R_CEU_CAPWR_M_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */ + #define R_CEU_CAPWR_M_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */ +/* ======================================================== CFLCR_M ======================================================== */ + #define R_CEU_CFLCR_M_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */ + #define R_CEU_CFLCR_M_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */ + #define R_CEU_CFLCR_M_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */ + #define R_CEU_CFLCR_M_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */ + #define R_CEU_CFLCR_M_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFLCR_M_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */ + #define R_CEU_CFLCR_M_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFSZR_M ======================================================== */ + #define R_CEU_CFSZR_M_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */ + #define R_CEU_CFSZR_M_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */ + #define R_CEU_CFSZR_M_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */ + #define R_CEU_CFSZR_M_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */ +/* ======================================================== CDWDR_M ======================================================== */ + #define R_CEU_CDWDR_M_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */ + #define R_CEU_CDWDR_M_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CDAYR_M ======================================================== */ + #define R_CEU_CDAYR_M_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */ + #define R_CEU_CDAYR_M_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDACR_M ======================================================== */ + #define R_CEU_CDACR_M_CACR_Pos (0UL) /*!< CACR (Bit 0) */ + #define R_CEU_CDACR_M_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBYR_M ======================================================== */ + #define R_CEU_CDBYR_M_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */ + #define R_CEU_CDBYR_M_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDBCR_M ======================================================== */ + #define R_CEU_CDBCR_M_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */ + #define R_CEU_CDBCR_M_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CBDSR_M ======================================================== */ + #define R_CEU_CBDSR_M_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */ + #define R_CEU_CBDSR_M_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */ +/* ======================================================== CLFCR_M ======================================================== */ + #define R_CEU_CLFCR_M_LPF_Pos (0UL) /*!< LPF (Bit 0) */ + #define R_CEU_CLFCR_M_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */ +/* ======================================================== CDOCR_M ======================================================== */ + #define R_CEU_CDOCR_M_COBS_Pos (0UL) /*!< COBS (Bit 0) */ + #define R_CEU_CDOCR_M_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COWS_Pos (1UL) /*!< COWS (Bit 1) */ + #define R_CEU_CDOCR_M_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_COLS_Pos (2UL) /*!< COLS (Bit 2) */ + #define R_CEU_CDOCR_M_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CDS_Pos (4UL) /*!< CDS (Bit 4) */ + #define R_CEU_CDOCR_M_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */ + #define R_CEU_CDOCR_M_CBE_Pos (16UL) /*!< CBE (Bit 16) */ + #define R_CEU_CDOCR_M_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */ +/* ======================================================= CDAYR2_M ======================================================== */ + #define R_CEU_CDAYR2_M_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */ + #define R_CEU_CDAYR2_M_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDACR2_M ======================================================== */ + #define R_CEU_CDACR2_M_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */ + #define R_CEU_CDACR2_M_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBYR2_M ======================================================== */ + #define R_CEU_CDBYR2_M_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */ + #define R_CEU_CDBYR2_M_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CDBCR2_M ======================================================== */ + #define R_CEU_CDBCR2_M_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */ + #define R_CEU_CDBCR2_M_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ULPT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ULPTCNT ======================================================== */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Pos (0UL) /*!< ULPTCNT (Bit 0) */ + #define R_ULPT0_ULPTCNT_ULPTCNT_Msk (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMA ======================================================== */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Pos (0UL) /*!< ULPTCMA (Bit 0) */ + #define R_ULPT0_ULPTCMA_ULPTCMA_Msk (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCMB ======================================================== */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Pos (0UL) /*!< ULPTCMB (Bit 0) */ + #define R_ULPT0_ULPTCMB_ULPTCMB_Msk (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ULPTCR ========================================================= */ + #define R_ULPT0_ULPTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_ULPT0_ULPTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_ULPT0_ULPTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_ULPT0_ULPTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_ULPT0_ULPTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_ULPT0_ULPTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_ULPT0_ULPTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR1 ======================================================== */ + #define R_ULPT0_ULPTMR1_TMOD1_Pos (1UL) /*!< TMOD1 (Bit 1) */ + #define R_ULPT0_ULPTMR1_TMOD1_Msk (0x2UL) /*!< TMOD1 (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_ULPT0_ULPTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR1_TCK1_Pos (5UL) /*!< TCK1 (Bit 5) */ + #define R_ULPT0_ULPTMR1_TCK1_Msk (0x20UL) /*!< TCK1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR2 ======================================================== */ + #define R_ULPT0_ULPTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_ULPT0_ULPTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_ULPT0_ULPTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_ULPT0_ULPTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTMR3 ======================================================== */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Pos (0UL) /*!< TCNTCTL (Bit 0) */ + #define R_ULPT0_ULPTMR3_TCNTCTL_Msk (0x1UL) /*!< TCNTCTL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Pos (1UL) /*!< TEVPOL (Bit 1) */ + #define R_ULPT0_ULPTMR3_TEVPOL_Msk (0x2UL) /*!< TEVPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TOPOL_Pos (2UL) /*!< TOPOL (Bit 2) */ + #define R_ULPT0_ULPTMR3_TOPOL_Msk (0x4UL) /*!< TOPOL (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTMR3_TEECTL_Pos (4UL) /*!< TEECTL (Bit 4) */ + #define R_ULPT0_ULPTMR3_TEECTL_Msk (0x30UL) /*!< TEECTL (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Pos (6UL) /*!< TEEPOL (Bit 6) */ + #define R_ULPT0_ULPTMR3_TEEPOL_Msk (0xc0UL) /*!< TEEPOL (Bitfield-Mask: 0x03) */ +/* ======================================================== ULPTIOC ======================================================== */ + #define R_ULPT0_ULPTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_ULPT0_ULPTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_ULPT0_ULPTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Pos (6UL) /*!< TIOGT0 (Bit 6) */ + #define R_ULPT0_ULPTIOC_TIOGT0_Msk (0x40UL) /*!< TIOGT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ULPTISR ======================================================== */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Pos (2UL) /*!< RCCPSEL2 (Bit 2) */ + #define R_ULPT0_ULPTISR_RCCPSEL2_Msk (0x4UL) /*!< RCCPSEL2 (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPTCMSR ======================================================== */ + #define R_ULPT0_ULPTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_ULPT0_ULPTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_ULPT0_ULPTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_ULPT0_ULPTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_ULPT0_ULPTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_ULPT0_ULPTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_ULPT0_ULPTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG_OCD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== MCUERRSTAT ======================================================= */ + #define R_DEBUG_OCD_MCUERRSTAT_ZERO_Pos (0UL) /*!< ZERO (Bit 0) */ + #define R_DEBUG_OCD_MCUERRSTAT_ZERO_Msk (0x1UL) /*!< ZERO (Bitfield-Mask: 0x01) */ +/* ======================================================== MCUCTRL ======================================================== */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ0_Pos (0UL) /*!< EDBGRQ0 (Bit 0) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ0_Msk (0x1UL) /*!< EDBGRQ0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ1_Pos (1UL) /*!< EDBGRQ1 (Bit 1) */ + #define R_DEBUG_OCD_MCUCTRL_EDBGRQ1_Msk (0x2UL) /*!< EDBGRQ1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ0_Pos (8UL) /*!< DBIRQ0 (Bit 8) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ0_Msk (0x100UL) /*!< DBIRQ0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ1_Pos (9UL) /*!< DBIRQ1 (Bit 9) */ + #define R_DEBUG_OCD_MCUCTRL_DBIRQ1_Msk (0x200UL) /*!< DBIRQ1 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT0_Pos (16UL) /*!< CPUWAIT0 (Bit 16) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT0_Msk (0x10000UL) /*!< CPUWAIT0 (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT1_Pos (17UL) /*!< CPUWAIT1 (Bit 17) */ + #define R_DEBUG_OCD_MCUCTRL_CPUWAIT1_Msk (0x20000UL) /*!< CPUWAIT1 (Bitfield-Mask: 0x01) */ +/* ========================================================= JBMDR ========================================================= */ + #define R_DEBUG_OCD_JBMDR_KEY_Pos (0UL) /*!< KEY (Bit 0) */ + #define R_DEBUG_OCD_JBMDR_KEY_Msk (0xffUL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= JBRDR ========================================================= */ + #define R_DEBUG_OCD_JBRDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_DEBUG_OCD_JBRDR_RDAT_Msk (0xffffffffUL) /*!< RDAT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= JBTDR ========================================================= */ + #define R_DEBUG_OCD_JBTDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_DEBUG_OCD_JBTDR_TDAT_Msk (0xffffffffUL) /*!< TDAT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= JBSTR ========================================================= */ + #define R_DEBUG_OCD_JBSTR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_DEBUG_OCD_JBSTR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_JBSTR_TDE_Pos (1UL) /*!< TDE (Bit 1) */ + #define R_DEBUG_OCD_JBSTR_TDE_Msk (0x2UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= JBICR ========================================================= */ + #define R_DEBUG_OCD_JBICR_RDFIE_Pos (0UL) /*!< RDFIE (Bit 0) */ + #define R_DEBUG_OCD_JBICR_RDFIE_Msk (0x1UL) /*!< RDFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= FSBLSTATM ======================================================= */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_DEBUG_OCD_FSBLSTATM_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Pos (1UL) /*!< RS (Bit 1) */ + #define R_DEBUG_OCD_FSBLSTATM_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOTF ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CONVAREAST ======================================================= */ + #define R_DOTF_CONVAREAST_CONVAREAST_Pos (12UL) /*!< CONVAREAST (Bit 12) */ + #define R_DOTF_CONVAREAST_CONVAREAST_Msk (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff) */ +/* ======================================================= CONVAREAD ======================================================= */ + #define R_DOTF_CONVAREAD_CONVAREAD_Pos (12UL) /*!< CONVAREAD (Bit 12) */ + #define R_DOTF_CONVAREAD_CONVAREAD_Msk (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= REG00 ========================================================= */ + #define R_DOTF_REG00_B09_Pos (9UL) /*!< B09 (Bit 9) */ + #define R_DOTF_REG00_B09_Msk (0x200UL) /*!< B09 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B16_Pos (16UL) /*!< B16 (Bit 16) */ + #define R_DOTF_REG00_B16_Msk (0x10000UL) /*!< B16 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B17_Pos (17UL) /*!< B17 (Bit 17) */ + #define R_DOTF_REG00_B17_Msk (0x20000UL) /*!< B17 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B20_Pos (20UL) /*!< B20 (Bit 20) */ + #define R_DOTF_REG00_B20_Msk (0x100000UL) /*!< B20 (Bitfield-Mask: 0x01) */ + #define R_DOTF_REG00_B24_Pos (24UL) /*!< B24 (Bit 24) */ + #define R_DOTF_REG00_B24_Msk (0x3000000UL) /*!< B24 (Bitfield-Mask: 0x03) */ + #define R_DOTF_REG00_B28_Pos (28UL) /*!< B28 (Bit 28) */ + #define R_DOTF_REG00_B28_Msk (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03) */ +/* ========================================================= REG03 ========================================================= */ + #define R_DOTF_REG03_B00_Pos (0UL) /*!< B00 (Bit 0) */ + #define R_DOTF_REG03_B00_Msk (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTX0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_COMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RIPV ========================================================== */ + #define R_COMA_RIPV_TIPV_Pos (0UL) /*!< TIPV (Bit 0) */ + #define R_COMA_RIPV_TIPV_Msk (0xfUL) /*!< TIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_GWIPV_Pos (4UL) /*!< GWIPV (Bit 4) */ + #define R_COMA_RIPV_GWIPV_Msk (0xf0UL) /*!< GWIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_FWIPV_Pos (8UL) /*!< FWIPV (Bit 8) */ + #define R_COMA_RIPV_FWIPV_Msk (0xf00UL) /*!< FWIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_EAIPV_Pos (12UL) /*!< EAIPV (Bit 12) */ + #define R_COMA_RIPV_EAIPV_Msk (0xf000UL) /*!< EAIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_FBIPV_Pos (16UL) /*!< FBIPV (Bit 16) */ + #define R_COMA_RIPV_FBIPV_Msk (0xf0000UL) /*!< FBIPV (Bitfield-Mask: 0x0f) */ + #define R_COMA_RIPV_CAIPV_Pos (20UL) /*!< CAIPV (Bit 20) */ + #define R_COMA_RIPV_CAIPV_Msk (0xf00000UL) /*!< CAIPV (Bitfield-Mask: 0x0f) */ +/* ========================================================== RRC ========================================================== */ + #define R_COMA_RRC_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_COMA_RRC_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= RCEC ========================================================== */ + #define R_COMA_RCEC_ACE_Pos (0UL) /*!< ACE (Bit 0) */ + #define R_COMA_RCEC_ACE_Msk (0x7fUL) /*!< ACE (Bitfield-Mask: 0x7f) */ + #define R_COMA_RCEC_RCE_Pos (16UL) /*!< RCE (Bit 16) */ + #define R_COMA_RCEC_RCE_Msk (0x10000UL) /*!< RCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCDC ========================================================== */ + #define R_COMA_RCDC_ACD_Pos (0UL) /*!< ACD (Bit 0) */ + #define R_COMA_RCDC_ACD_Msk (0x7fUL) /*!< ACD (Bitfield-Mask: 0x7f) */ + #define R_COMA_RCDC_RCD_Pos (16UL) /*!< RCD (Bit 16) */ + #define R_COMA_RCDC_RCD_Msk (0x10000UL) /*!< RCD (Bitfield-Mask: 0x01) */ +/* ======================================================= CABPIBWMC ======================================================= */ + #define R_COMA_CABPIBWMC_IBUWMPN_Pos (0UL) /*!< IBUWMPN (Bit 0) */ + #define R_COMA_CABPIBWMC_IBUWMPN_Msk (0x3ffUL) /*!< IBUWMPN (Bitfield-Mask: 0x3ff) */ + #define R_COMA_CABPIBWMC_IBSWMPN_Pos (16UL) /*!< IBSWMPN (Bit 16) */ + #define R_COMA_CABPIBWMC_IBSWMPN_Msk (0x3ff0000UL) /*!< IBSWMPN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CABPWMLC ======================================================== */ + #define R_COMA_CABPWMLC_WMFL_Pos (0UL) /*!< WMFL (Bit 0) */ + #define R_COMA_CABPWMLC_WMFL_Msk (0x1fffUL) /*!< WMFL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPWMLC_WMCL_Pos (16UL) /*!< WMCL (Bit 16) */ + #define R_COMA_CABPWMLC_WMCL_Msk (0x1fff0000UL) /*!< WMCL (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPPFLC ======================================================== */ + #define R_COMA_CABPPFLC_PDL_Pos (0UL) /*!< PDL (Bit 0) */ + #define R_COMA_CABPPFLC_PDL_Msk (0x1fffUL) /*!< PDL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPFLC_PAL_Pos (16UL) /*!< PAL (Bit 16) */ + #define R_COMA_CABPPFLC_PAL_Msk (0x1fff0000UL) /*!< PAL (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPPWMLC ======================================================= */ + #define R_COMA_CABPPWMLC_PWMFL_Pos (0UL) /*!< PWMFL (Bit 0) */ + #define R_COMA_CABPPWMLC_PWMFL_Msk (0x1fffUL) /*!< PWMFL (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPWMLC_PWMCL_Pos (16UL) /*!< PWMCL (Bit 16) */ + #define R_COMA_CABPPWMLC_PWMCL_Msk (0x1fff0000UL) /*!< PWMCL (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPULC ======================================================== */ + #define R_COMA_CABPULC_MXNPN_Pos (0UL) /*!< MXNPN (Bit 0) */ + #define R_COMA_CABPULC_MXNPN_Msk (0x1fffUL) /*!< MXNPN (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPULC_MNNPN_Pos (16UL) /*!< MNNPN (Bit 16) */ + #define R_COMA_CABPULC_MNNPN_Msk (0x1fff0000UL) /*!< MNNPN (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPIRM ======================================================== */ + #define R_COMA_CABPIRM_BPIOG_Pos (0UL) /*!< BPIOG (Bit 0) */ + #define R_COMA_CABPIRM_BPIOG_Msk (0x1UL) /*!< BPIOG (Bitfield-Mask: 0x01) */ + #define R_COMA_CABPIRM_BPR_Pos (1UL) /*!< BPR (Bit 1) */ + #define R_COMA_CABPIRM_BPR_Msk (0x2UL) /*!< BPR (Bitfield-Mask: 0x01) */ +/* ======================================================== CABPPCM ======================================================== */ + #define R_COMA_CABPPCM_RPC_Pos (0UL) /*!< RPC (Bit 0) */ + #define R_COMA_CABPPCM_RPC_Msk (0x1fffUL) /*!< RPC (Bitfield-Mask: 0x1fff) */ + #define R_COMA_CABPPCM_TPC_Pos (16UL) /*!< TPC (Bit 16) */ + #define R_COMA_CABPPCM_TPC_Msk (0x1fff0000UL) /*!< TPC (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPLCM ======================================================== */ + #define R_COMA_CABPLCM_LRC_Pos (0UL) /*!< LRC (Bit 0) */ + #define R_COMA_CABPLCM_LRC_Msk (0x1fffUL) /*!< LRC (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CABPCPM ======================================================== */ + #define R_COMA_CABPCPM_RPCP_Pos (0UL) /*!< RPCP (Bit 0) */ + #define R_COMA_CABPCPM_RPCP_Msk (0x1fffUL) /*!< RPCP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= CABPMCPM ======================================================== */ + #define R_COMA_CABPMCPM_RPMCP_Pos (0UL) /*!< RPMCP (Bit 0) */ + #define R_COMA_CABPMCPM_RPMCP_Msk (0x1fffUL) /*!< RPMCP (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDNM ========================================================= */ + #define R_COMA_CARDNM_RDNRR_Pos (0UL) /*!< RDNRR (Bit 0) */ + #define R_COMA_CARDNM_RDNRR_Msk (0x1fffUL) /*!< RDNRR (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDMNM ======================================================== */ + #define R_COMA_CARDMNM_RDMNRR_Pos (0UL) /*!< RDMNRR (Bit 0) */ + #define R_COMA_CARDMNM_RDMNRR_Msk (0x1fffUL) /*!< RDMNRR (Bitfield-Mask: 0x1fff) */ +/* ======================================================== CARDCN ========================================================= */ + #define R_COMA_CARDCN_RDN_Pos (0UL) /*!< RDN (Bit 0) */ + #define R_COMA_CARDCN_RDN_Msk (0xffffffffUL) /*!< RDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CAEIS0 ========================================================= */ + #define R_COMA_CAEIS0_PECCES_Pos (0UL) /*!< PECCES (Bit 0) */ + #define R_COMA_CAEIS0_PECCES_Msk (0x1UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_DSECCES_Pos (1UL) /*!< DSECCES (Bit 1) */ + #define R_COMA_CAEIS0_DSECCES_Msk (0x2UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_BPECCES_Pos (2UL) /*!< BPECCES (Bit 2) */ + #define R_COMA_CAEIS0_BPECCES_Msk (0x4UL) /*!< BPECCES (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_BPOPS_Pos (8UL) /*!< BPOPS (Bit 8) */ + #define R_COMA_CAEIS0_BPOPS_Msk (0x100UL) /*!< BPOPS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_WMCLOS_Pos (9UL) /*!< WMCLOS (Bit 9) */ + #define R_COMA_CAEIS0_WMCLOS_Msk (0x200UL) /*!< WMCLOS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_WMFLOS_Pos (10UL) /*!< WMFLOS (Bit 10) */ + #define R_COMA_CAEIS0_WMFLOS_Msk (0x400UL) /*!< WMFLOS (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIS0_EEIPLN_Pos (16UL) /*!< EEIPLN (Bit 16) */ + #define R_COMA_CAEIS0_EEIPLN_Msk (0xf0000UL) /*!< EEIPLN (Bitfield-Mask: 0x0f) */ +/* ======================================================== CAEIE0 ========================================================= */ + #define R_COMA_CAEIE0_PECCEE_Pos (0UL) /*!< PECCEE (Bit 0) */ + #define R_COMA_CAEIE0_PECCEE_Msk (0x1UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_DSECCEE_Pos (1UL) /*!< DSECCEE (Bit 1) */ + #define R_COMA_CAEIE0_DSECCEE_Msk (0x2UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_BPECCEE_Pos (2UL) /*!< BPECCEE (Bit 2) */ + #define R_COMA_CAEIE0_BPECCEE_Msk (0x4UL) /*!< BPECCEE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_BPOPE_Pos (8UL) /*!< BPOPE (Bit 8) */ + #define R_COMA_CAEIE0_BPOPE_Msk (0x100UL) /*!< BPOPE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_WMCLOE_Pos (9UL) /*!< WMCLOE (Bit 9) */ + #define R_COMA_CAEIE0_WMCLOE_Msk (0x200UL) /*!< WMCLOE (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEIE0_WMFLOE_Pos (10UL) /*!< WMFLOE (Bit 10) */ + #define R_COMA_CAEIE0_WMFLOE_Msk (0x400UL) /*!< WMFLOE (Bitfield-Mask: 0x01) */ +/* ======================================================== CAEID0 ========================================================= */ + #define R_COMA_CAEID0_PECCED_Pos (0UL) /*!< PECCED (Bit 0) */ + #define R_COMA_CAEID0_PECCED_Msk (0x1UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_DSECCED_Pos (1UL) /*!< DSECCED (Bit 1) */ + #define R_COMA_CAEID0_DSECCED_Msk (0x2UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_BPECCED_Pos (2UL) /*!< BPECCED (Bit 2) */ + #define R_COMA_CAEID0_BPECCED_Msk (0x4UL) /*!< BPECCED (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_BPOPD_Pos (8UL) /*!< BPOPD (Bit 8) */ + #define R_COMA_CAEID0_BPOPD_Msk (0x100UL) /*!< BPOPD (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_WMCLOD_Pos (9UL) /*!< WMCLOD (Bit 9) */ + #define R_COMA_CAEID0_WMCLOD_Msk (0x200UL) /*!< WMCLOD (Bitfield-Mask: 0x01) */ + #define R_COMA_CAEID0_WMFLOD_Pos (10UL) /*!< WMFLOD (Bit 10) */ + #define R_COMA_CAEID0_WMFLOD_Msk (0x400UL) /*!< WMFLOD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAEIS1 ========================================================= */ + #define R_COMA_CAEIS1_PWMCLOS_Pos (0UL) /*!< PWMCLOS (Bit 0) */ + #define R_COMA_CAEIS1_PWMCLOS_Msk (0x7fUL) /*!< PWMCLOS (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEIS1_PWMFLOS_Pos (16UL) /*!< PWMFLOS (Bit 16) */ + #define R_COMA_CAEIS1_PWMFLOS_Msk (0x7f0000UL) /*!< PWMFLOS (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAEIE1 ========================================================= */ + #define R_COMA_CAEIE1_PWMCLOE_Pos (0UL) /*!< PWMCLOE (Bit 0) */ + #define R_COMA_CAEIE1_PWMCLOE_Msk (0x7fUL) /*!< PWMCLOE (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEIE1_PWMFLOE_Pos (16UL) /*!< PWMFLOE (Bit 16) */ + #define R_COMA_CAEIE1_PWMFLOE_Msk (0x7f0000UL) /*!< PWMFLOE (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAEID1 ========================================================= */ + #define R_COMA_CAEID1_PWMCLOD_Pos (0UL) /*!< PWMCLOD (Bit 0) */ + #define R_COMA_CAEID1_PWMCLOD_Msk (0x7fUL) /*!< PWMCLOD (Bitfield-Mask: 0x7f) */ + #define R_COMA_CAEID1_PWMFLOD_Pos (16UL) /*!< PWMFLOD (Bit 16) */ + #define R_COMA_CAEID1_PWMFLOD_Msk (0x7f0000UL) /*!< PWMFLOD (Bitfield-Mask: 0x7f) */ +/* ======================================================== CAMIS0 ========================================================= */ + #define R_COMA_CAMIS0_PFS_Pos (0UL) /*!< PFS (Bit 0) */ + #define R_COMA_CAMIS0_PFS_Msk (0x3UL) /*!< PFS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMIE0 ========================================================= */ + #define R_COMA_CAMIE0_PFE_Pos (0UL) /*!< PFE (Bit 0) */ + #define R_COMA_CAMIE0_PFE_Msk (0x3UL) /*!< PFE (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMID0 ========================================================= */ + #define R_COMA_CAMID0_PFD_Pos (0UL) /*!< PFD (Bit 0) */ + #define R_COMA_CAMID0_PFD_Msk (0x3UL) /*!< PFD (Bitfield-Mask: 0x03) */ +/* ======================================================== CAMIS1 ========================================================= */ + #define R_COMA_CAMIS1_PPFS_Pos (0UL) /*!< PPFS (Bit 0) */ + #define R_COMA_CAMIS1_PPFS_Msk (0x3fffUL) /*!< PPFS (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CAMIE1 ========================================================= */ + #define R_COMA_CAMIE1_PPFE_Pos (0UL) /*!< PPFE (Bit 0) */ + #define R_COMA_CAMIE1_PPFE_Msk (0x3fffUL) /*!< PPFE (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CAMID1 ========================================================= */ + #define R_COMA_CAMID1_PPFD_Pos (0UL) /*!< PPFD (Bit 0) */ + #define R_COMA_CAMID1_PPFD_Msk (0x3fffUL) /*!< PPFD (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CPU_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== CPU0LCKUPCR ====================================================== */ + #define R_CPU_CTRL_CPU0LCKUPCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CPU_CTRL_CPU0LCKUPCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1LCKUPCR ====================================================== */ + #define R_CPU_CTRL_CPU1LCKUPCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CPU_CTRL_CPU1LCKUPCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0INITVTOR ====================================================== */ + #define R_CPU_CTRL_CPU0INITVTOR_CPUnINITVTOR_Pos (0UL) /*!< CPUnINITVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU0INITVTOR_CPUnINITVTOR_Msk (0xffffffffUL) /*!< CPUnINITVTOR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CPU1INITVTOR ====================================================== */ + #define R_CPU_CTRL_CPU1INITVTOR_CPUnINITVTOR_Pos (0UL) /*!< CPUnINITVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU1INITVTOR_CPUnINITVTOR_Msk (0xffffffffUL) /*!< CPUnINITVTOR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CPU0WAITCR ======================================================= */ + #define R_CPU_CTRL_CPU0WAITCR_CPUWAIT_Pos (0UL) /*!< CPUWAIT (Bit 0) */ + #define R_CPU_CTRL_CPU0WAITCR_CPUWAIT_Msk (0x1UL) /*!< CPUWAIT (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1WAITCR ======================================================= */ + #define R_CPU_CTRL_CPU1WAITCR_CPUWAIT_Pos (0UL) /*!< CPUWAIT (Bit 0) */ + #define R_CPU_CTRL_CPU1WAITCR_CPUWAIT_Msk (0x1UL) /*!< CPUWAIT (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0ACTCSR ======================================================= */ + #define R_CPU_CTRL_CPU0ACTCSR_ACTREQ_Pos (0UL) /*!< ACTREQ (Bit 0) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACTREQ_Msk (0x1UL) /*!< ACTREQ (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_CPU_CTRL_CPU0ACTCSR_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0ACTCSR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU0ACTCSR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ====================================================== CPU1ACTCSR ======================================================= */ + #define R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Pos (0UL) /*!< ACTREQ (Bit 0) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Msk (0x1UL) /*!< ACTREQ (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_CPU_CTRL_CPU1ACTCSR_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1ACTCSR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU1ACTCSR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CPU0LMECR ======================================================= */ + #define R_CPU_CTRL_CPU0LMECR_SYRSTEN_Pos (0UL) /*!< SYRSTEN (Bit 0) */ + #define R_CPU_CTRL_CPU0LMECR_SYRSTEN_Msk (0x1UL) /*!< SYRSTEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUIDR ========================================================= */ + #define R_CPU_CTRL_CPUIDR_CPUID_Pos (0UL) /*!< CPUID (Bit 0) */ + #define R_CPU_CTRL_CPUIDR_CPUID_Msk (0x1UL) /*!< CPUID (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0STATM ======================================================= */ + #define R_CPU_CTRL_CPU0STATM_SLEEPING_Pos (0UL) /*!< SLEEPING (Bit 0) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPING_Msk (0x1UL) /*!< SLEEPING (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPDEEP_Pos (1UL) /*!< SLEEPDEEP (Bit 1) */ + #define R_CPU_CTRL_CPU0STATM_SLEEPDEEP_Msk (0x2UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0STATM_SAHBSTP_Pos (4UL) /*!< SAHBSTP (Bit 4) */ + #define R_CPU_CTRL_CPU0STATM_SAHBSTP_Msk (0x10UL) /*!< SAHBSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU1STATM ======================================================= */ + #define R_CPU_CTRL_CPU1STATM_SLEEPING_Pos (0UL) /*!< SLEEPING (Bit 0) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPING_Msk (0x1UL) /*!< SLEEPING (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPDEEP_Pos (1UL) /*!< SLEEPDEEP (Bit 1) */ + #define R_CPU_CTRL_CPU1STATM_SLEEPDEEP_Msk (0x2UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1STATM_SAHBSTP_Pos (4UL) /*!< SAHBSTP (Bit 4) */ + #define R_CPU_CTRL_CPU1STATM_SAHBSTP_Msk (0x10UL) /*!< SAHBSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= SECEXTMON ======================================================= */ + #define R_CPU_CTRL_SECEXTMON_SECEXT_Pos (0UL) /*!< SECEXT (Bit 0) */ + #define R_CPU_CTRL_SECEXTMON_SECEXT_Msk (0x1UL) /*!< SECEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== NSCPUCR ======================================================== */ + #define R_CPU_CTRL_NSCPUCR_RSTREQEN_Pos (0UL) /*!< RSTREQEN (Bit 0) */ + #define R_CPU_CTRL_NSCPUCR_RSTREQEN_Msk (0x1UL) /*!< RSTREQEN (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0LOCKCR ======================================================= */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSVTAIR_Pos (0UL) /*!< LCKSVTAIR (Bit 0) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSVTAIR_Msk (0x1UL) /*!< LCKSVTAIR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSMPU_Pos (1UL) /*!< LCKSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSMPU_Msk (0x2UL) /*!< LCKSMPU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSAU_Pos (2UL) /*!< LCKSAU (Bit 2) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKSAU_Msk (0x4UL) /*!< LCKSAU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKITGU_Pos (3UL) /*!< LCKITGU (Bit 3) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKITGU_Msk (0x8UL) /*!< LCKITGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDTGU_Pos (4UL) /*!< LCKDTGU (Bit 4) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDTGU_Msk (0x10UL) /*!< LCKDTGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDCAIC_Pos (5UL) /*!< LCKDCAIC (Bit 5) */ + #define R_CPU_CTRL_CPU0LOCKCR_LCKDCAIC_Msk (0x20UL) /*!< LCKDCAIC (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1LOCKCR ======================================================= */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSVTAIR_Pos (0UL) /*!< LCKSVTAIR (Bit 0) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSVTAIR_Msk (0x1UL) /*!< LCKSVTAIR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSMPU_Pos (1UL) /*!< LCKSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSMPU_Msk (0x2UL) /*!< LCKSMPU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSAU_Pos (2UL) /*!< LCKSAU (Bit 2) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKSAU_Msk (0x4UL) /*!< LCKSAU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKITGU_Pos (3UL) /*!< LCKITGU (Bit 3) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKITGU_Msk (0x8UL) /*!< LCKITGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDTGU_Pos (4UL) /*!< LCKDTGU (Bit 4) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDTGU_Msk (0x10UL) /*!< LCKDTGU (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDCAIC_Pos (5UL) /*!< LCKDCAIC (Bit 5) */ + #define R_CPU_CTRL_CPU1LOCKCR_LCKDCAIC_Msk (0x20UL) /*!< LCKDCAIC (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0LOCKCRNS ====================================================== */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSVTOR_Pos (0UL) /*!< LCKNSVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSVTOR_Msk (0x1UL) /*!< LCKNSVTOR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSMPU_Pos (1UL) /*!< LCKNSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU0LOCKCRNS_LCKNSMPU_Msk (0x2UL) /*!< LCKNSMPU (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU1LOCKCRNS ====================================================== */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSVTOR_Pos (0UL) /*!< LCKNSVTOR (Bit 0) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSVTOR_Msk (0x1UL) /*!< LCKNSVTOR (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSMPU_Pos (1UL) /*!< LCKNSMPU (Bit 1) */ + #define R_CPU_CTRL_CPU1LOCKCRNS_LCKNSMPU_Msk (0x2UL) /*!< LCKNSMPU (Bitfield-Mask: 0x01) */ +/* ======================================================= CPU0CRPT ======================================================== */ + #define R_CPU_CTRL_CPU0CRPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_CPU_CTRL_CPU0CRPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU0CRPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU0CRPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CPU1CRPT ======================================================== */ + #define R_CPU_CTRL_CPU1CRPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_CPU_CTRL_CPU1CRPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_CPU_CTRL_CPU1CRPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CPU_CTRL_CPU1CRPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_ECCMB0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_ECCMB0_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_ECCMB0_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_ECCMB0_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_ECCMB0_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_ECCMB0_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_ECCMB0_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_ECCMB0_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_ECCMB0_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_ECCMB0_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_ECCMB0_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_ECCMB0_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_ECCMB0_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Pos (16UL) /*!< ECSEDF0 (Bit 16) */ + #define R_ECCMB0_EC710CTL_ECSEDF0_Msk (0x10000UL) /*!< ECSEDF0 (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Pos (17UL) /*!< ECDEDF0 (Bit 17) */ + #define R_ECCMB0_EC710CTL_ECDEDF0_Msk (0x20000UL) /*!< ECDEDF0 (Bitfield-Mask: 0x01) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_ECCMB0_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_ECCMB0_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_ECCMB0_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_ECCMB0_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_ECCMB0_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_ECCMB0_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_ECCMB0_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD0 ======================================================= */ + #define R_ECCMB0_EC710EAD0_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_ECCMB0_EC710EAD0_ECEAD_Msk (0x3ffUL) /*!< ECEAD (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_ESWM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= TPEMIMC0 ======================================================== */ + #define R_ESWM_TPEMIMC0_SEIM_Pos (0UL) /*!< SEIM (Bit 0) */ + #define R_ESWM_TPEMIMC0_SEIM_Msk (0x1UL) /*!< SEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SEIGM_Pos (1UL) /*!< SEIGM (Bit 1) */ + #define R_ESWM_TPEMIMC0_SEIGM_Msk (0x2UL) /*!< SEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SEICM_Pos (4UL) /*!< SEICM (Bit 4) */ + #define R_ESWM_TPEMIMC0_SEICM_Msk (0x70UL) /*!< SEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC0_SSIM_Pos (16UL) /*!< SSIM (Bit 16) */ + #define R_ESWM_TPEMIMC0_SSIM_Msk (0x10000UL) /*!< SSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SSIGM_Pos (17UL) /*!< SSIGM (Bit 17) */ + #define R_ESWM_TPEMIMC0_SSIGM_Msk (0x20000UL) /*!< SSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC0_SSICM_Pos (20UL) /*!< SSICM (Bit 20) */ + #define R_ESWM_TPEMIMC0_SSICM_Msk (0x700000UL) /*!< SSICM (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC1 ======================================================== */ + #define R_ESWM_TPEMIMC1_FEIM_Pos (0UL) /*!< FEIM (Bit 0) */ + #define R_ESWM_TPEMIMC1_FEIM_Msk (0x1UL) /*!< FEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FEIGM_Pos (1UL) /*!< FEIGM (Bit 1) */ + #define R_ESWM_TPEMIMC1_FEIGM_Msk (0x2UL) /*!< FEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FEICM_Pos (4UL) /*!< FEICM (Bit 4) */ + #define R_ESWM_TPEMIMC1_FEICM_Msk (0x70UL) /*!< FEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_FSIM_Pos (8UL) /*!< FSIM (Bit 8) */ + #define R_ESWM_TPEMIMC1_FSIM_Msk (0x100UL) /*!< FSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FSIGM_Pos (9UL) /*!< FSIGM (Bit 9) */ + #define R_ESWM_TPEMIMC1_FSIGM_Msk (0x200UL) /*!< FSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_FSICM_Pos (12UL) /*!< FSICM (Bit 12) */ + #define R_ESWM_TPEMIMC1_FSICM_Msk (0x7000UL) /*!< FSICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_CEIM_Pos (16UL) /*!< CEIM (Bit 16) */ + #define R_ESWM_TPEMIMC1_CEIM_Msk (0x10000UL) /*!< CEIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CEIGM_Pos (17UL) /*!< CEIGM (Bit 17) */ + #define R_ESWM_TPEMIMC1_CEIGM_Msk (0x20000UL) /*!< CEIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CEICM_Pos (20UL) /*!< CEICM (Bit 20) */ + #define R_ESWM_TPEMIMC1_CEICM_Msk (0x700000UL) /*!< CEICM (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC1_CSIM_Pos (24UL) /*!< CSIM (Bit 24) */ + #define R_ESWM_TPEMIMC1_CSIM_Msk (0x1000000UL) /*!< CSIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CSIGM_Pos (25UL) /*!< CSIGM (Bit 25) */ + #define R_ESWM_TPEMIMC1_CSIGM_Msk (0x2000000UL) /*!< CSIGM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC1_CSICM_Pos (28UL) /*!< CSICM (Bit 28) */ + #define R_ESWM_TPEMIMC1_CSICM_Msk (0x70000000UL) /*!< CSICM (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC2 ======================================================== */ + #define R_ESWM_TPEMIMC2_GEIM0_Pos (0UL) /*!< GEIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC2_GEIM0_Msk (0x1UL) /*!< GEIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GEIGM0_Pos (1UL) /*!< GEIGM0 (Bit 1) */ + #define R_ESWM_TPEMIMC2_GEIGM0_Msk (0x2UL) /*!< GEIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GEICM0_Pos (4UL) /*!< GEICM0 (Bit 4) */ + #define R_ESWM_TPEMIMC2_GEICM0_Msk (0x70UL) /*!< GEICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC2_GSIM0_Pos (8UL) /*!< GSIM0 (Bit 8) */ + #define R_ESWM_TPEMIMC2_GSIM0_Msk (0x100UL) /*!< GSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GSIGM0_Pos (9UL) /*!< GSIGM0 (Bit 9) */ + #define R_ESWM_TPEMIMC2_GSIGM0_Msk (0x200UL) /*!< GSIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC2_GSICM0_Pos (12UL) /*!< GSICM0 (Bit 12) */ + #define R_ESWM_TPEMIMC2_GSICM0_Msk (0x7000UL) /*!< GSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC3 ======================================================== */ + #define R_ESWM_TPEMIMC3_EEIM0_Pos (0UL) /*!< EEIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC3_EEIM0_Msk (0x1UL) /*!< EEIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_EEIGM0_Pos (1UL) /*!< EEIGM0 (Bit 1) */ + #define R_ESWM_TPEMIMC3_EEIGM0_Msk (0x2UL) /*!< EEIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_EEICM0_Pos (4UL) /*!< EEICM0 (Bit 4) */ + #define R_ESWM_TPEMIMC3_EEICM0_Msk (0x70UL) /*!< EEICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC3_ESIM0_Pos (8UL) /*!< ESIM0 (Bit 8) */ + #define R_ESWM_TPEMIMC3_ESIM0_Msk (0x100UL) /*!< ESIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_ESIGM0_Pos (9UL) /*!< ESIGM0 (Bit 9) */ + #define R_ESWM_TPEMIMC3_ESIGM0_Msk (0x200UL) /*!< ESIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_ESICM0_Pos (12UL) /*!< ESICM0 (Bit 12) */ + #define R_ESWM_TPEMIMC3_ESICM0_Msk (0x7000UL) /*!< ESICM0 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC3_RSIM0_Pos (16UL) /*!< RSIM0 (Bit 16) */ + #define R_ESWM_TPEMIMC3_RSIM0_Msk (0x10000UL) /*!< RSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_RSIGM0_Pos (17UL) /*!< RSIGM0 (Bit 17) */ + #define R_ESWM_TPEMIMC3_RSIGM0_Msk (0x20000UL) /*!< RSIGM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC3_RSICM0_Pos (20UL) /*!< RSICM0 (Bit 20) */ + #define R_ESWM_TPEMIMC3_RSICM0_Msk (0x700000UL) /*!< RSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC4 ======================================================== */ + #define R_ESWM_TPEMIMC4_EEIM1_Pos (0UL) /*!< EEIM1 (Bit 0) */ + #define R_ESWM_TPEMIMC4_EEIM1_Msk (0x1UL) /*!< EEIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_EEIGM1_Pos (1UL) /*!< EEIGM1 (Bit 1) */ + #define R_ESWM_TPEMIMC4_EEIGM1_Msk (0x2UL) /*!< EEIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_EEICM1_Pos (4UL) /*!< EEICM1 (Bit 4) */ + #define R_ESWM_TPEMIMC4_EEICM1_Msk (0x70UL) /*!< EEICM1 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC4_ESIM1_Pos (8UL) /*!< ESIM1 (Bit 8) */ + #define R_ESWM_TPEMIMC4_ESIM1_Msk (0x100UL) /*!< ESIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_ESIGM1_Pos (9UL) /*!< ESIGM1 (Bit 9) */ + #define R_ESWM_TPEMIMC4_ESIGM1_Msk (0x200UL) /*!< ESIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_ESICM1_Pos (12UL) /*!< ESICM1 (Bit 12) */ + #define R_ESWM_TPEMIMC4_ESICM1_Msk (0x7000UL) /*!< ESICM1 (Bitfield-Mask: 0x07) */ + #define R_ESWM_TPEMIMC4_RSIM1_Pos (16UL) /*!< RSIM1 (Bit 16) */ + #define R_ESWM_TPEMIMC4_RSIM1_Msk (0x10000UL) /*!< RSIM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_RSIGM1_Pos (17UL) /*!< RSIGM1 (Bit 17) */ + #define R_ESWM_TPEMIMC4_RSIGM1_Msk (0x20000UL) /*!< RSIGM1 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC4_RSICM1_Pos (20UL) /*!< RSICM1 (Bit 20) */ + #define R_ESWM_TPEMIMC4_RSICM1_Msk (0x700000UL) /*!< RSICM1 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC60 ======================================================= */ + #define R_ESWM_TPEMIMC60_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC60_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC60_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC60_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC61 ======================================================= */ + #define R_ESWM_TPEMIMC61_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC61_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC61_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC61_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC62 ======================================================= */ + #define R_ESWM_TPEMIMC62_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC62_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC62_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC62_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC63 ======================================================= */ + #define R_ESWM_TPEMIMC63_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC63_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC63_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC63_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC64 ======================================================= */ + #define R_ESWM_TPEMIMC64_GTSIM0_Pos (0UL) /*!< GTSIM0 (Bit 0) */ + #define R_ESWM_TPEMIMC64_GTSIM0_Msk (0x1UL) /*!< GTSIM0 (Bitfield-Mask: 0x01) */ + #define R_ESWM_TPEMIMC64_GTSICM0_Pos (1UL) /*!< GTSICM0 (Bit 1) */ + #define R_ESWM_TPEMIMC64_GTSICM0_Msk (0xeUL) /*!< GTSICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC70 ======================================================= */ + #define R_ESWM_TPEMIMC70_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC70_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC71 ======================================================= */ + #define R_ESWM_TPEMIMC71_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC71_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC72 ======================================================= */ + #define R_ESWM_TPEMIMC72_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC72_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC73 ======================================================= */ + #define R_ESWM_TPEMIMC73_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC73_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ======================================================= TPEMIMC74 ======================================================= */ + #define R_ESWM_TPEMIMC74_GDICM0_Pos (0UL) /*!< GDICM0 (Bit 0) */ + #define R_ESWM_TPEMIMC74_GDICM0_Msk (0x7UL) /*!< GDICM0 (Bitfield-Mask: 0x07) */ +/* ========================================================= TSIM ========================================================== */ + #define R_ESWM_TSIM_FIM_Pos (0UL) /*!< FIM (Bit 0) */ + #define R_ESWM_TSIM_FIM_Msk (0x1UL) /*!< FIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_CIM_Pos (1UL) /*!< CIM (Bit 1) */ + #define R_ESWM_TSIM_CIM_Msk (0x2UL) /*!< CIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_GIM_Pos (2UL) /*!< GIM (Bit 2) */ + #define R_ESWM_TSIM_GIM_Msk (0x4UL) /*!< GIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TSIM_EIM_Pos (4UL) /*!< EIM (Bit 4) */ + #define R_ESWM_TSIM_EIM_Msk (0x10UL) /*!< EIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TFIM ========================================================== */ + #define R_ESWM_TFIM_FWEISIM_Pos (0UL) /*!< FWEISIM (Bit 0) */ + #define R_ESWM_TFIM_FWEISIM_Msk (0x1UL) /*!< FWEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TFIM_FWMISIM0_Pos (9UL) /*!< FWMISIM0 (Bit 9) */ + #define R_ESWM_TFIM_FWMISIM0_Msk (0x200UL) /*!< FWMISIM0 (Bitfield-Mask: 0x01) */ +/* ========================================================= TCIM ========================================================== */ + #define R_ESWM_TCIM_RSSISIM_Pos (0UL) /*!< RSSISIM (Bit 0) */ + #define R_ESWM_TCIM_RSSISIM_Msk (0x1UL) /*!< RSSISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TCIM_CAEISIM_Pos (1UL) /*!< CAEISIM (Bit 1) */ + #define R_ESWM_TCIM_CAEISIM_Msk (0x2UL) /*!< CAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TCIM_CAMISIM_Pos (3UL) /*!< CAMISIM (Bit 3) */ + #define R_ESWM_TCIM_CAMISIM_Msk (0x8UL) /*!< CAMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TGIM0 ========================================================= */ + #define R_ESWM_TGIM0_GWDISIM_Pos (0UL) /*!< GWDISIM (Bit 0) */ + #define R_ESWM_TGIM0_GWDISIM_Msk (0x1UL) /*!< GWDISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TGIM0_GWTSDISIM_Pos (1UL) /*!< GWTSDISIM (Bit 1) */ + #define R_ESWM_TGIM0_GWTSDISIM_Msk (0x2UL) /*!< GWTSDISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TGIM0_GWEISIM_Pos (2UL) /*!< GWEISIM (Bit 2) */ + #define R_ESWM_TGIM0_GWEISIM_Msk (0x4UL) /*!< GWEISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TEIM0 ========================================================= */ + #define R_ESWM_TEIM0_EAEISIM_Pos (0UL) /*!< EAEISIM (Bit 0) */ + #define R_ESWM_TEIM0_EAEISIM_Msk (0x1UL) /*!< EAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM0_MEISIM_Pos (3UL) /*!< MEISIM (Bit 3) */ + #define R_ESWM_TEIM0_MEISIM_Msk (0x8UL) /*!< MEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM0_MMISIM_Pos (4UL) /*!< MMISIM (Bit 4) */ + #define R_ESWM_TEIM0_MMISIM_Msk (0x10UL) /*!< MMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= TEIM1 ========================================================= */ + #define R_ESWM_TEIM1_EAEISIM_Pos (0UL) /*!< EAEISIM (Bit 0) */ + #define R_ESWM_TEIM1_EAEISIM_Msk (0x1UL) /*!< EAEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM1_MEISIM_Pos (3UL) /*!< MEISIM (Bit 3) */ + #define R_ESWM_TEIM1_MEISIM_Msk (0x8UL) /*!< MEISIM (Bitfield-Mask: 0x01) */ + #define R_ESWM_TEIM1_MMISIM_Pos (4UL) /*!< MMISIM (Bit 4) */ + #define R_ESWM_TEIM1_MMISIM_Msk (0x10UL) /*!< MMISIM (Bitfield-Mask: 0x01) */ +/* ========================================================= MIIRR ========================================================= */ + #define R_ESWM_MIIRR_RGRST_Pos (0UL) /*!< RGRST (Bit 0) */ + #define R_ESWM_MIIRR_RGRST_Msk (0x1UL) /*!< RGRST (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIIRR_RMRST_Pos (8UL) /*!< RMRST (Bit 8) */ + #define R_ESWM_MIIRR_RMRST_Msk (0x100UL) /*!< RMRST (Bitfield-Mask: 0x01) */ +/* ======================================================== MIICR0 ========================================================= */ + #define R_ESWM_MIICR0_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_ESWM_MIICR0_MIISEL_Msk (0x3UL) /*!< MIISEL (Bitfield-Mask: 0x03) */ + #define R_ESWM_MIICR0_DIVSTP_Pos (8UL) /*!< DIVSTP (Bit 8) */ + #define R_ESWM_MIICR0_DIVSTP_Msk (0x100UL) /*!< DIVSTP (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIICR0_TXCIDE_Pos (12UL) /*!< TXCIDE (Bit 12) */ + #define R_ESWM_MIICR0_TXCIDE_Msk (0x1000UL) /*!< TXCIDE (Bitfield-Mask: 0x01) */ +/* ======================================================== MIICR1 ========================================================= */ + #define R_ESWM_MIICR1_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_ESWM_MIICR1_MIISEL_Msk (0x3UL) /*!< MIISEL (Bitfield-Mask: 0x03) */ + #define R_ESWM_MIICR1_DIVSTP_Pos (8UL) /*!< DIVSTP (Bit 8) */ + #define R_ESWM_MIICR1_DIVSTP_Msk (0x100UL) /*!< DIVSTP (Bitfield-Mask: 0x01) */ + #define R_ESWM_MIICR1_TXCIDE_Pos (12UL) /*!< TXCIDE (Bit 12) */ + #define R_ESWM_MIICR1_TXCIDE_Msk (0x1000UL) /*!< TXCIDE (Bitfield-Mask: 0x01) */ +/* ======================================================== MCCESR ========================================================= */ + #define R_ESWM_MCCESR_MCCES_Pos (0UL) /*!< MCCES (Bit 0) */ + #define R_ESWM_MCCESR_MCCES_Msk (0x1UL) /*!< MCCES (Bitfield-Mask: 0x01) */ +/* ======================================================== TASSTSR ======================================================== */ + #define R_ESWM_TASSTSR_MSS_Pos (0UL) /*!< MSS (Bit 0) */ + #define R_ESWM_TASSTSR_MSS_Msk (0x1fUL) /*!< MSS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EAMC ========================================================== */ + #define R_ETHA0_EAMC_OPC_Pos (0UL) /*!< OPC (Bit 0) */ + #define R_ETHA0_EAMC_OPC_Msk (0x3UL) /*!< OPC (Bitfield-Mask: 0x03) */ +/* ========================================================= EAMS ========================================================== */ + #define R_ETHA0_EAMS_OPS_Pos (0UL) /*!< OPS (Bit 0) */ + #define R_ETHA0_EAMS_OPS_Msk (0x3UL) /*!< OPS (Bitfield-Mask: 0x03) */ +/* ========================================================= EAIRC ========================================================= */ + #define R_ETHA0_EAIRC_IPVR0_Pos (0UL) /*!< IPVR0 (Bit 0) */ + #define R_ETHA0_EAIRC_IPVR0_Msk (0x7UL) /*!< IPVR0 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR1_Pos (4UL) /*!< IPVR1 (Bit 4) */ + #define R_ETHA0_EAIRC_IPVR1_Msk (0x70UL) /*!< IPVR1 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR2_Pos (8UL) /*!< IPVR2 (Bit 8) */ + #define R_ETHA0_EAIRC_IPVR2_Msk (0x700UL) /*!< IPVR2 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR3_Pos (12UL) /*!< IPVR3 (Bit 12) */ + #define R_ETHA0_EAIRC_IPVR3_Msk (0x7000UL) /*!< IPVR3 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR4_Pos (16UL) /*!< IPVR4 (Bit 16) */ + #define R_ETHA0_EAIRC_IPVR4_Msk (0x70000UL) /*!< IPVR4 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR5_Pos (20UL) /*!< IPVR5 (Bit 20) */ + #define R_ETHA0_EAIRC_IPVR5_Msk (0x700000UL) /*!< IPVR5 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR6_Pos (24UL) /*!< IPVR6 (Bit 24) */ + #define R_ETHA0_EAIRC_IPVR6_Msk (0x7000000UL) /*!< IPVR6 (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAIRC_IPVR7_Pos (28UL) /*!< IPVR7 (Bit 28) */ + #define R_ETHA0_EAIRC_IPVR7_Msk (0x70000000UL) /*!< IPVR7 (Bitfield-Mask: 0x07) */ +/* ======================================================== EATDQSC ======================================================== */ + #define R_ETHA0_EATDQSC_TDQSL0_Pos (0UL) /*!< TDQSL0 (Bit 0) */ + #define R_ETHA0_EATDQSC_TDQSL0_Msk (0x1UL) /*!< TDQSL0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL1_Pos (1UL) /*!< TDQSL1 (Bit 1) */ + #define R_ETHA0_EATDQSC_TDQSL1_Msk (0x2UL) /*!< TDQSL1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL2_Pos (2UL) /*!< TDQSL2 (Bit 2) */ + #define R_ETHA0_EATDQSC_TDQSL2_Msk (0x4UL) /*!< TDQSL2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL3_Pos (3UL) /*!< TDQSL3 (Bit 3) */ + #define R_ETHA0_EATDQSC_TDQSL3_Msk (0x8UL) /*!< TDQSL3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL4_Pos (4UL) /*!< TDQSL4 (Bit 4) */ + #define R_ETHA0_EATDQSC_TDQSL4_Msk (0x10UL) /*!< TDQSL4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL5_Pos (5UL) /*!< TDQSL5 (Bit 5) */ + #define R_ETHA0_EATDQSC_TDQSL5_Msk (0x20UL) /*!< TDQSL5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL6_Pos (6UL) /*!< TDQSL6 (Bit 6) */ + #define R_ETHA0_EATDQSC_TDQSL6_Msk (0x40UL) /*!< TDQSL6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQSC_TDQSL7_Pos (7UL) /*!< TDQSL7 (Bit 7) */ + #define R_ETHA0_EATDQSC_TDQSL7_Msk (0x80UL) /*!< TDQSL7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATDQC ========================================================= */ + #define R_ETHA0_EATDQC_TDQD0_Pos (0UL) /*!< TDQD0 (Bit 0) */ + #define R_ETHA0_EATDQC_TDQD0_Msk (0x1UL) /*!< TDQD0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD1_Pos (1UL) /*!< TDQD1 (Bit 1) */ + #define R_ETHA0_EATDQC_TDQD1_Msk (0x2UL) /*!< TDQD1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD2_Pos (2UL) /*!< TDQD2 (Bit 2) */ + #define R_ETHA0_EATDQC_TDQD2_Msk (0x4UL) /*!< TDQD2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD3_Pos (3UL) /*!< TDQD3 (Bit 3) */ + #define R_ETHA0_EATDQC_TDQD3_Msk (0x8UL) /*!< TDQD3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD4_Pos (4UL) /*!< TDQD4 (Bit 4) */ + #define R_ETHA0_EATDQC_TDQD4_Msk (0x10UL) /*!< TDQD4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD5_Pos (5UL) /*!< TDQD5 (Bit 5) */ + #define R_ETHA0_EATDQC_TDQD5_Msk (0x20UL) /*!< TDQD5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD6_Pos (6UL) /*!< TDQD6 (Bit 6) */ + #define R_ETHA0_EATDQC_TDQD6_Msk (0x40UL) /*!< TDQD6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQD7_Pos (7UL) /*!< TDQD7 (Bit 7) */ + #define R_ETHA0_EATDQC_TDQD7_Msk (0x80UL) /*!< TDQD7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TCTDQD_Pos (8UL) /*!< TCTDQD (Bit 8) */ + #define R_ETHA0_EATDQC_TCTDQD_Msk (0x100UL) /*!< TCTDQD (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP0_Pos (16UL) /*!< TDQP0 (Bit 16) */ + #define R_ETHA0_EATDQC_TDQP0_Msk (0x10000UL) /*!< TDQP0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP1_Pos (17UL) /*!< TDQP1 (Bit 17) */ + #define R_ETHA0_EATDQC_TDQP1_Msk (0x20000UL) /*!< TDQP1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP2_Pos (18UL) /*!< TDQP2 (Bit 18) */ + #define R_ETHA0_EATDQC_TDQP2_Msk (0x40000UL) /*!< TDQP2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP3_Pos (19UL) /*!< TDQP3 (Bit 19) */ + #define R_ETHA0_EATDQC_TDQP3_Msk (0x80000UL) /*!< TDQP3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP4_Pos (20UL) /*!< TDQP4 (Bit 20) */ + #define R_ETHA0_EATDQC_TDQP4_Msk (0x100000UL) /*!< TDQP4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP5_Pos (21UL) /*!< TDQP5 (Bit 21) */ + #define R_ETHA0_EATDQC_TDQP5_Msk (0x200000UL) /*!< TDQP5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP6_Pos (22UL) /*!< TDQP6 (Bit 22) */ + #define R_ETHA0_EATDQC_TDQP6_Msk (0x400000UL) /*!< TDQP6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATDQC_TDQP7_Pos (23UL) /*!< TDQP7 (Bit 23) */ + #define R_ETHA0_EATDQC_TDQP7_Msk (0x800000UL) /*!< TDQP7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATDQAC ======================================================== */ + #define R_ETHA0_EATDQAC_TDQA0_Pos (0UL) /*!< TDQA0 (Bit 0) */ + #define R_ETHA0_EATDQAC_TDQA0_Msk (0xfUL) /*!< TDQA0 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA1_Pos (4UL) /*!< TDQA1 (Bit 4) */ + #define R_ETHA0_EATDQAC_TDQA1_Msk (0xf0UL) /*!< TDQA1 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA2_Pos (8UL) /*!< TDQA2 (Bit 8) */ + #define R_ETHA0_EATDQAC_TDQA2_Msk (0xf00UL) /*!< TDQA2 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA3_Pos (12UL) /*!< TDQA3 (Bit 12) */ + #define R_ETHA0_EATDQAC_TDQA3_Msk (0xf000UL) /*!< TDQA3 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA4_Pos (16UL) /*!< TDQA4 (Bit 16) */ + #define R_ETHA0_EATDQAC_TDQA4_Msk (0xf0000UL) /*!< TDQA4 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA5_Pos (20UL) /*!< TDQA5 (Bit 20) */ + #define R_ETHA0_EATDQAC_TDQA5_Msk (0xf00000UL) /*!< TDQA5 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA6_Pos (24UL) /*!< TDQA6 (Bit 24) */ + #define R_ETHA0_EATDQAC_TDQA6_Msk (0xf000000UL) /*!< TDQA6 (Bitfield-Mask: 0x0f) */ + #define R_ETHA0_EATDQAC_TDQA7_Pos (28UL) /*!< TDQA7 (Bit 28) */ + #define R_ETHA0_EATDQAC_TDQA7_Msk (0xf0000000UL) /*!< TDQA7 (Bitfield-Mask: 0x0f) */ +/* ======================================================== EATPEC ========================================================= */ + #define R_ETHA0_EATPEC_TTQ0_Pos (0UL) /*!< TTQ0 (Bit 0) */ + #define R_ETHA0_EATPEC_TTQ0_Msk (0x1UL) /*!< TTQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ1_Pos (1UL) /*!< TTQ1 (Bit 1) */ + #define R_ETHA0_EATPEC_TTQ1_Msk (0x2UL) /*!< TTQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ2_Pos (2UL) /*!< TTQ2 (Bit 2) */ + #define R_ETHA0_EATPEC_TTQ2_Msk (0x4UL) /*!< TTQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ3_Pos (3UL) /*!< TTQ3 (Bit 3) */ + #define R_ETHA0_EATPEC_TTQ3_Msk (0x8UL) /*!< TTQ3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ4_Pos (4UL) /*!< TTQ4 (Bit 4) */ + #define R_ETHA0_EATPEC_TTQ4_Msk (0x10UL) /*!< TTQ4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ5_Pos (5UL) /*!< TTQ5 (Bit 5) */ + #define R_ETHA0_EATPEC_TTQ5_Msk (0x20UL) /*!< TTQ5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ6_Pos (6UL) /*!< TTQ6 (Bit 6) */ + #define R_ETHA0_EATPEC_TTQ6_Msk (0x40UL) /*!< TTQ6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ7_Pos (7UL) /*!< TTQ7 (Bit 7) */ + #define R_ETHA0_EATPEC_TTQ7_Msk (0x80UL) /*!< TTQ7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ8_Pos (8UL) /*!< TTQ8 (Bit 8) */ + #define R_ETHA0_EATPEC_TTQ8_Msk (0x100UL) /*!< TTQ8 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_TTQ9_Pos (9UL) /*!< TTQ9 (Bit 9) */ + #define R_ETHA0_EATPEC_TTQ9_Msk (0x200UL) /*!< TTQ9 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATPEC_AFS_Pos (16UL) /*!< AFS (Bit 16) */ + #define R_ETHA0_EATPEC_AFS_Msk (0x30000UL) /*!< AFS (Bitfield-Mask: 0x03) */ +/* ======================================================= EATMFSC0 ======================================================== */ + #define R_ETHA0_EATMFSC0_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC0_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC1 ======================================================== */ + #define R_ETHA0_EATMFSC1_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC1_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC2 ======================================================== */ + #define R_ETHA0_EATMFSC2_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC2_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC3 ======================================================== */ + #define R_ETHA0_EATMFSC3_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC3_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC4 ======================================================== */ + #define R_ETHA0_EATMFSC4_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC4_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC5 ======================================================== */ + #define R_ETHA0_EATMFSC5_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC5_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC6 ======================================================== */ + #define R_ETHA0_EATMFSC6_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC6_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATMFSC7 ======================================================== */ + #define R_ETHA0_EATMFSC7_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_ETHA0_EATMFSC7_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATDQDC0 ======================================================== */ + #define R_ETHA0_EATDQDC0_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC0_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC1 ======================================================== */ + #define R_ETHA0_EATDQDC1_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC1_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC2 ======================================================== */ + #define R_ETHA0_EATDQDC2_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC2_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC3 ======================================================== */ + #define R_ETHA0_EATDQDC3_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC3_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC4 ======================================================== */ + #define R_ETHA0_EATDQDC4_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC4_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC5 ======================================================== */ + #define R_ETHA0_EATDQDC5_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC5_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC6 ======================================================== */ + #define R_ETHA0_EATDQDC6_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC6_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQDC7 ======================================================== */ + #define R_ETHA0_EATDQDC7_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_ETHA0_EATDQDC7_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM0 ======================================================== */ + #define R_ETHA0_EATDQM0_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM0_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM1 ======================================================== */ + #define R_ETHA0_EATDQM1_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM1_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM2 ======================================================== */ + #define R_ETHA0_EATDQM2_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM2_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM3 ======================================================== */ + #define R_ETHA0_EATDQM3_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM3_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM4 ======================================================== */ + #define R_ETHA0_EATDQM4_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM4_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM5 ======================================================== */ + #define R_ETHA0_EATDQM5_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM5_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM6 ======================================================== */ + #define R_ETHA0_EATDQM6_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM6_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EATDQM7 ======================================================== */ + #define R_ETHA0_EATDQM7_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_ETHA0_EATDQM7_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM0 ======================================================= */ + #define R_ETHA0_EATDQMLM0_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM0_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM1 ======================================================= */ + #define R_ETHA0_EATDQMLM1_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM1_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM2 ======================================================= */ + #define R_ETHA0_EATDQMLM2_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM2_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM3 ======================================================= */ + #define R_ETHA0_EATDQMLM3_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM3_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM4 ======================================================= */ + #define R_ETHA0_EATDQMLM4_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM4_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM5 ======================================================= */ + #define R_ETHA0_EATDQMLM5_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM5_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM6 ======================================================= */ + #define R_ETHA0_EATDQMLM6_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM6_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= EATDQMLM7 ======================================================= */ + #define R_ETHA0_EATDQMLM7_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_ETHA0_EATDQMLM7_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== EACTQC ========================================================= */ + #define R_ETHA0_EACTQC_CTQD_Pos (0UL) /*!< CTQD (Bit 0) */ + #define R_ETHA0_EACTQC_CTQD_Msk (0xffffUL) /*!< CTQD (Bitfield-Mask: 0xffff) */ +/* ======================================================= EACTDQDC ======================================================== */ + #define R_ETHA0_EACTDQDC_CTDQD_Pos (0UL) /*!< CTDQD (Bit 0) */ + #define R_ETHA0_EACTDQDC_CTDQD_Msk (0xfUL) /*!< CTDQD (Bitfield-Mask: 0x0f) */ +/* ======================================================== EACTDQM ======================================================== */ + #define R_ETHA0_EACTDQM_CTQDN_Pos (0UL) /*!< CTQDN (Bit 0) */ + #define R_ETHA0_EACTDQM_CTQDN_Msk (0x3ffUL) /*!< CTQDN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= EACTDQMLM ======================================================= */ + #define R_ETHA0_EACTDQMLM_CTDMLQ_Pos (0UL) /*!< CTDMLQ (Bit 0) */ + #define R_ETHA0_EACTDQMLM_CTDMLQ_Msk (0xfUL) /*!< CTDMLQ (Bitfield-Mask: 0x0f) */ +/* ========================================================= EAVCC ========================================================= */ + #define R_ETHA0_EAVCC_VIM_Pos (0UL) /*!< VIM (Bit 0) */ + #define R_ETHA0_EAVCC_VIM_Msk (0x1UL) /*!< VIM (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAVCC_VEM_Pos (16UL) /*!< VEM (Bit 16) */ + #define R_ETHA0_EAVCC_VEM_Msk (0x70000UL) /*!< VEM (Bitfield-Mask: 0x07) */ +/* ========================================================= EAVTC ========================================================= */ + #define R_ETHA0_EAVTC_CTV_Pos (0UL) /*!< CTV (Bit 0) */ + #define R_ETHA0_EAVTC_CTV_Msk (0xfffUL) /*!< CTV (Bitfield-Mask: 0xfff) */ + #define R_ETHA0_EAVTC_CTP_Pos (12UL) /*!< CTP (Bit 12) */ + #define R_ETHA0_EAVTC_CTP_Msk (0x7000UL) /*!< CTP (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAVTC_CTD_Pos (15UL) /*!< CTD (Bit 15) */ + #define R_ETHA0_EAVTC_CTD_Msk (0x8000UL) /*!< CTD (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAVTC_STV_Pos (16UL) /*!< STV (Bit 16) */ + #define R_ETHA0_EAVTC_STV_Msk (0xfff0000UL) /*!< STV (Bitfield-Mask: 0xfff) */ + #define R_ETHA0_EAVTC_STP_Pos (28UL) /*!< STP (Bit 28) */ + #define R_ETHA0_EAVTC_STP_Msk (0x70000000UL) /*!< STP (Bitfield-Mask: 0x07) */ + #define R_ETHA0_EAVTC_STD_Pos (31UL) /*!< STD (Bit 31) */ + #define R_ETHA0_EAVTC_STD_Msk (0x80000000UL) /*!< STD (Bitfield-Mask: 0x01) */ +/* ======================================================== EARTFC ========================================================= */ + #define R_ETHA0_EARTFC_NT_Pos (0UL) /*!< NT (Bit 0) */ + #define R_ETHA0_EARTFC_NT_Msk (0x1UL) /*!< NT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_RT_Pos (1UL) /*!< RT (Bit 1) */ + #define R_ETHA0_EARTFC_RT_Msk (0x2UL) /*!< RT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CST_Pos (2UL) /*!< CST (Bit 2) */ + #define R_ETHA0_EARTFC_CST_Msk (0x4UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CSRT_Pos (3UL) /*!< CSRT (Bit 3) */ + #define R_ETHA0_EARTFC_CSRT_Msk (0x8UL) /*!< CSRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CT_Pos (4UL) /*!< CT (Bit 4) */ + #define R_ETHA0_EARTFC_CT_Msk (0x10UL) /*!< CT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_CRT_Pos (5UL) /*!< CRT (Bit 5) */ + #define R_ETHA0_EARTFC_CRT_Msk (0x20UL) /*!< CRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_SCT_Pos (6UL) /*!< SCT (Bit 6) */ + #define R_ETHA0_EARTFC_SCT_Msk (0x40UL) /*!< SCT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_SCRT_Pos (7UL) /*!< SCRT (Bit 7) */ + #define R_ETHA0_EARTFC_SCRT_Msk (0x80UL) /*!< SCRT (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EARTFC_UT_Pos (8UL) /*!< UT (Bit 8) */ + #define R_ETHA0_EARTFC_UT_Msk (0x100UL) /*!< UT (Bitfield-Mask: 0x01) */ +/* ======================================================== EACAEC ========================================================= */ + #define R_ETHA0_EACAEC_CE0_Pos (0UL) /*!< CE0 (Bit 0) */ + #define R_ETHA0_EACAEC_CE0_Msk (0x1UL) /*!< CE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE1_Pos (1UL) /*!< CE1 (Bit 1) */ + #define R_ETHA0_EACAEC_CE1_Msk (0x2UL) /*!< CE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE2_Pos (2UL) /*!< CE2 (Bit 2) */ + #define R_ETHA0_EACAEC_CE2_Msk (0x4UL) /*!< CE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE3_Pos (3UL) /*!< CE3 (Bit 3) */ + #define R_ETHA0_EACAEC_CE3_Msk (0x8UL) /*!< CE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE4_Pos (4UL) /*!< CE4 (Bit 4) */ + #define R_ETHA0_EACAEC_CE4_Msk (0x10UL) /*!< CE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE5_Pos (5UL) /*!< CE5 (Bit 5) */ + #define R_ETHA0_EACAEC_CE5_Msk (0x20UL) /*!< CE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE6_Pos (6UL) /*!< CE6 (Bit 6) */ + #define R_ETHA0_EACAEC_CE6_Msk (0x40UL) /*!< CE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACAEC_CE7_Pos (7UL) /*!< CE7 (Bit 7) */ + #define R_ETHA0_EACAEC_CE7_Msk (0x80UL) /*!< CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= EACC ========================================================== */ + #define R_ETHA0_EACC_CC0_Pos (0UL) /*!< CC0 (Bit 0) */ + #define R_ETHA0_EACC_CC0_Msk (0x1UL) /*!< CC0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC1_Pos (1UL) /*!< CC1 (Bit 1) */ + #define R_ETHA0_EACC_CC1_Msk (0x2UL) /*!< CC1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC2_Pos (2UL) /*!< CC2 (Bit 2) */ + #define R_ETHA0_EACC_CC2_Msk (0x4UL) /*!< CC2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC3_Pos (3UL) /*!< CC3 (Bit 3) */ + #define R_ETHA0_EACC_CC3_Msk (0x8UL) /*!< CC3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC4_Pos (4UL) /*!< CC4 (Bit 4) */ + #define R_ETHA0_EACC_CC4_Msk (0x10UL) /*!< CC4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC5_Pos (5UL) /*!< CC5 (Bit 5) */ + #define R_ETHA0_EACC_CC5_Msk (0x20UL) /*!< CC5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC6_Pos (6UL) /*!< CC6 (Bit 6) */ + #define R_ETHA0_EACC_CC6_Msk (0x40UL) /*!< CC6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACC_CC7_Pos (7UL) /*!< CC7 (Bit 7) */ + #define R_ETHA0_EACC_CC7_Msk (0x80UL) /*!< CC7 (Bitfield-Mask: 0x01) */ +/* ======================================================= EACAIVC0 ======================================================== */ + #define R_ETHA0_EACAIVC0_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC0_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC1 ======================================================== */ + #define R_ETHA0_EACAIVC1_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC1_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC2 ======================================================== */ + #define R_ETHA0_EACAIVC2_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC2_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC3 ======================================================== */ + #define R_ETHA0_EACAIVC3_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC3_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC4 ======================================================== */ + #define R_ETHA0_EACAIVC4_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC4_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC5 ======================================================== */ + #define R_ETHA0_EACAIVC5_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC5_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC6 ======================================================== */ + #define R_ETHA0_EACAIVC6_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC6_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAIVC7 ======================================================== */ + #define R_ETHA0_EACAIVC7_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACAIVC7_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACAULC0 ======================================================== */ + #define R_ETHA0_EACAULC0_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC0_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC1 ======================================================== */ + #define R_ETHA0_EACAULC1_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC1_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC2 ======================================================== */ + #define R_ETHA0_EACAULC2_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC2_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC3 ======================================================== */ + #define R_ETHA0_EACAULC3_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC3_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC4 ======================================================== */ + #define R_ETHA0_EACAULC4_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC4_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC5 ======================================================== */ + #define R_ETHA0_EACAULC5_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC5_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC6 ======================================================== */ + #define R_ETHA0_EACAULC6_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC6_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACAULC7 ======================================================== */ + #define R_ETHA0_EACAULC7_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACAULC7_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================== EACOEM ========================================================= */ + #define R_ETHA0_EACOEM_CE0_Pos (0UL) /*!< CE0 (Bit 0) */ + #define R_ETHA0_EACOEM_CE0_Msk (0x1UL) /*!< CE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE1_Pos (1UL) /*!< CE1 (Bit 1) */ + #define R_ETHA0_EACOEM_CE1_Msk (0x2UL) /*!< CE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE2_Pos (2UL) /*!< CE2 (Bit 2) */ + #define R_ETHA0_EACOEM_CE2_Msk (0x4UL) /*!< CE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE3_Pos (3UL) /*!< CE3 (Bit 3) */ + #define R_ETHA0_EACOEM_CE3_Msk (0x8UL) /*!< CE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE4_Pos (4UL) /*!< CE4 (Bit 4) */ + #define R_ETHA0_EACOEM_CE4_Msk (0x10UL) /*!< CE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE5_Pos (5UL) /*!< CE5 (Bit 5) */ + #define R_ETHA0_EACOEM_CE5_Msk (0x20UL) /*!< CE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE6_Pos (6UL) /*!< CE6 (Bit 6) */ + #define R_ETHA0_EACOEM_CE6_Msk (0x40UL) /*!< CE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACOEM_CE7_Pos (7UL) /*!< CE7 (Bit 7) */ + #define R_ETHA0_EACOEM_CE7_Msk (0x80UL) /*!< CE7 (Bitfield-Mask: 0x01) */ +/* ======================================================= EACOIVM0 ======================================================== */ + #define R_ETHA0_EACOIVM0_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM0_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM1 ======================================================== */ + #define R_ETHA0_EACOIVM1_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM1_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM2 ======================================================== */ + #define R_ETHA0_EACOIVM2_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM2_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM3 ======================================================== */ + #define R_ETHA0_EACOIVM3_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM3_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM4 ======================================================== */ + #define R_ETHA0_EACOIVM4_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM4_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM5 ======================================================== */ + #define R_ETHA0_EACOIVM5_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM5_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM6 ======================================================== */ + #define R_ETHA0_EACOIVM6_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM6_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOIVM7 ======================================================== */ + #define R_ETHA0_EACOIVM7_CIV_Pos (0UL) /*!< CIV (Bit 0) */ + #define R_ETHA0_EACOIVM7_CIV_Msk (0xfffffUL) /*!< CIV (Bitfield-Mask: 0xfffff) */ +/* ======================================================= EACOULM0 ======================================================== */ + #define R_ETHA0_EACOULM0_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM0_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM1 ======================================================== */ + #define R_ETHA0_EACOULM1_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM1_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM2 ======================================================== */ + #define R_ETHA0_EACOULM2_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM2_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM3 ======================================================== */ + #define R_ETHA0_EACOULM3_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM3_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM4 ======================================================== */ + #define R_ETHA0_EACOULM4_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM4_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM5 ======================================================== */ + #define R_ETHA0_EACOULM5_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM5_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM6 ======================================================== */ + #define R_ETHA0_EACOULM6_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM6_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= EACOULM7 ======================================================== */ + #define R_ETHA0_EACOULM7_CUL_Pos (0UL) /*!< CUL (Bit 0) */ + #define R_ETHA0_EACOULM7_CUL_Msk (0x7fffffffUL) /*!< CUL (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================== EACGSM ========================================================= */ + #define R_ETHA0_EACGSM_CGS0_Pos (0UL) /*!< CGS0 (Bit 0) */ + #define R_ETHA0_EACGSM_CGS0_Msk (0x1UL) /*!< CGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS1_Pos (1UL) /*!< CGS1 (Bit 1) */ + #define R_ETHA0_EACGSM_CGS1_Msk (0x2UL) /*!< CGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS2_Pos (2UL) /*!< CGS2 (Bit 2) */ + #define R_ETHA0_EACGSM_CGS2_Msk (0x4UL) /*!< CGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS3_Pos (3UL) /*!< CGS3 (Bit 3) */ + #define R_ETHA0_EACGSM_CGS3_Msk (0x8UL) /*!< CGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS4_Pos (4UL) /*!< CGS4 (Bit 4) */ + #define R_ETHA0_EACGSM_CGS4_Msk (0x10UL) /*!< CGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS5_Pos (5UL) /*!< CGS5 (Bit 5) */ + #define R_ETHA0_EACGSM_CGS5_Msk (0x20UL) /*!< CGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS6_Pos (6UL) /*!< CGS6 (Bit 6) */ + #define R_ETHA0_EACGSM_CGS6_Msk (0x40UL) /*!< CGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EACGSM_CGS7_Pos (7UL) /*!< CGS7 (Bit 7) */ + #define R_ETHA0_EACGSM_CGS7_Msk (0x80UL) /*!< CGS7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASC ========================================================= */ + #define R_ETHA0_EATASC_TASE_Pos (0UL) /*!< TASE (Bit 0) */ + #define R_ETHA0_EATASC_TASE_Msk (0x1UL) /*!< TASE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCC_Pos (1UL) /*!< TASCC (Bit 1) */ + #define R_ETHA0_EATASC_TASCC_Msk (0x2UL) /*!< TASCC (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCI_Pos (2UL) /*!< TASCI (Bit 2) */ + #define R_ETHA0_EATASC_TASCI_Msk (0x4UL) /*!< TASCI (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASTS_Pos (8UL) /*!< TASTS (Bit 8) */ + #define R_ETHA0_EATASC_TASTS_Msk (0x100UL) /*!< TASTS (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASC_TASCA_Pos (16UL) /*!< TASCA (Bit 16) */ + #define R_ETHA0_EATASC_TASCA_Msk (0xff0000UL) /*!< TASCA (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASIGSC ======================================================= */ + #define R_ETHA0_EATASIGSC_TASIGS0_Pos (0UL) /*!< TASIGS0 (Bit 0) */ + #define R_ETHA0_EATASIGSC_TASIGS0_Msk (0x1UL) /*!< TASIGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS1_Pos (1UL) /*!< TASIGS1 (Bit 1) */ + #define R_ETHA0_EATASIGSC_TASIGS1_Msk (0x2UL) /*!< TASIGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS2_Pos (2UL) /*!< TASIGS2 (Bit 2) */ + #define R_ETHA0_EATASIGSC_TASIGS2_Msk (0x4UL) /*!< TASIGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS3_Pos (3UL) /*!< TASIGS3 (Bit 3) */ + #define R_ETHA0_EATASIGSC_TASIGS3_Msk (0x8UL) /*!< TASIGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS4_Pos (4UL) /*!< TASIGS4 (Bit 4) */ + #define R_ETHA0_EATASIGSC_TASIGS4_Msk (0x10UL) /*!< TASIGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS5_Pos (5UL) /*!< TASIGS5 (Bit 5) */ + #define R_ETHA0_EATASIGSC_TASIGS5_Msk (0x20UL) /*!< TASIGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS6_Pos (6UL) /*!< TASIGS6 (Bit 6) */ + #define R_ETHA0_EATASIGSC_TASIGS6_Msk (0x40UL) /*!< TASIGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASIGS7_Pos (7UL) /*!< TASIGS7 (Bit 7) */ + #define R_ETHA0_EATASIGSC_TASIGS7_Msk (0x80UL) /*!< TASIGS7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASIGSC_TASCTIGS_Pos (8UL) /*!< TASCTIGS (Bit 8) */ + #define R_ETHA0_EATASIGSC_TASCTIGS_Msk (0x100UL) /*!< TASCTIGS (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASENC0 ======================================================= */ + #define R_ETHA0_EATASENC0_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC0_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC1 ======================================================= */ + #define R_ETHA0_EATASENC1_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC1_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC2 ======================================================= */ + #define R_ETHA0_EATASENC2_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC2_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC3 ======================================================= */ + #define R_ETHA0_EATASENC3_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC3_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC4 ======================================================= */ + #define R_ETHA0_EATASENC4_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC4_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC5 ======================================================= */ + #define R_ETHA0_EATASENC5_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC5_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC6 ======================================================= */ + #define R_ETHA0_EATASENC6_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC6_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENC7 ======================================================= */ + #define R_ETHA0_EATASENC7_TASAEN_Pos (0UL) /*!< TASAEN (Bit 0) */ + #define R_ETHA0_EATASENC7_TASAEN_Msk (0x1ffUL) /*!< TASAEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCTENC ======================================================= */ + #define R_ETHA0_EATASCTENC_TASCTAEN_Pos (0UL) /*!< TASCTAEN (Bit 0) */ + #define R_ETHA0_EATASCTENC_TASCTAEN_Msk (0x1ffUL) /*!< TASCTAEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM0 ======================================================= */ + #define R_ETHA0_EATASENM0_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM0_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM1 ======================================================= */ + #define R_ETHA0_EATASENM1_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM1_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM2 ======================================================= */ + #define R_ETHA0_EATASENM2_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM2_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM3 ======================================================= */ + #define R_ETHA0_EATASENM3_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM3_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM4 ======================================================= */ + #define R_ETHA0_EATASENM4_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM4_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM5 ======================================================= */ + #define R_ETHA0_EATASENM5_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM5_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM6 ======================================================= */ + #define R_ETHA0_EATASENM6_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM6_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ======================================================= EATASENM7 ======================================================= */ + #define R_ETHA0_EATASENM7_TASOEN_Pos (0UL) /*!< TASOEN (Bit 0) */ + #define R_ETHA0_EATASENM7_TASOEN_Msk (0x1ffUL) /*!< TASOEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCTENM ======================================================= */ + #define R_ETHA0_EATASCTENM_TASCTOEN_Pos (0UL) /*!< TASCTOEN (Bit 0) */ + #define R_ETHA0_EATASCTENM_TASCTOEN_Msk (0x1ffUL) /*!< TASCTOEN (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EATASCSTC0 ======================================================= */ + #define R_ETHA0_EATASCSTC0_TASACSTP0_Pos (0UL) /*!< TASACSTP0 (Bit 0) */ + #define R_ETHA0_EATASCSTC0_TASACSTP0_Msk (0xffffffffUL) /*!< TASACSTP0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTC1 ======================================================= */ + #define R_ETHA0_EATASCSTC1_TASACSTP1_Pos (0UL) /*!< TASACSTP1 (Bit 0) */ + #define R_ETHA0_EATASCSTC1_TASACSTP1_Msk (0xffffffffUL) /*!< TASACSTP1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTM0 ======================================================= */ + #define R_ETHA0_EATASCSTM0_TASOCSTP0_Pos (0UL) /*!< TASOCSTP0 (Bit 0) */ + #define R_ETHA0_EATASCSTM0_TASOCSTP0_Msk (0xffffffffUL) /*!< TASOCSTP0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== EATASCSTM1 ======================================================= */ + #define R_ETHA0_EATASCSTM1_TASOCSTP1_Pos (0UL) /*!< TASOCSTP1 (Bit 0) */ + #define R_ETHA0_EATASCSTM1_TASOCSTP1_Msk (0xffffffffUL) /*!< TASOCSTP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASCTC ======================================================== */ + #define R_ETHA0_EATASCTC_TASACT_Pos (0UL) /*!< TASACT (Bit 0) */ + #define R_ETHA0_EATASCTC_TASACT_Msk (0xffffffffUL) /*!< TASACT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASCTM ======================================================== */ + #define R_ETHA0_EATASCTM_TASOCT_Pos (0UL) /*!< TASOCT (Bit 0) */ + #define R_ETHA0_EATASCTM_TASOCT_Msk (0xffffffffUL) /*!< TASOCT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EATASGL0 ======================================================== */ + #define R_ETHA0_EATASGL0_TASGAL_Pos (0UL) /*!< TASGAL (Bit 0) */ + #define R_ETHA0_EATASGL0_TASGAL_Msk (0xffUL) /*!< TASGAL (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASGL1 ======================================================== */ + #define R_ETHA0_EATASGL1_TASGTL_Pos (0UL) /*!< TASGTL (Bit 0) */ + #define R_ETHA0_EATASGL1_TASGTL_Msk (0xfffffffUL) /*!< TASGTL (Bitfield-Mask: 0xfffffff) */ + #define R_ETHA0_EATASGL1_TASGSL_Pos (28UL) /*!< TASGSL (Bit 28) */ + #define R_ETHA0_EATASGL1_TASGSL_Msk (0x10000000UL) /*!< TASGSL (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASGLR ======================================================== */ + #define R_ETHA0_EATASGLR_GL_Pos (31UL) /*!< GL (Bit 31) */ + #define R_ETHA0_EATASGLR_GL_Msk (0x80000000UL) /*!< GL (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASGR ======================================================== */ + #define R_ETHA0_EATASGR_TASGAR_Pos (0UL) /*!< TASGAR (Bit 0) */ + #define R_ETHA0_EATASGR_TASGAR_Msk (0xffUL) /*!< TASGAR (Bitfield-Mask: 0xff) */ +/* ======================================================= EATASGRR ======================================================== */ + #define R_ETHA0_EATASGRR_TASGTR_Pos (0UL) /*!< TASGTR (Bit 0) */ + #define R_ETHA0_EATASGRR_TASGTR_Msk (0xfffffffUL) /*!< TASGTR (Bitfield-Mask: 0xfffffff) */ + #define R_ETHA0_EATASGRR_TASGSR_Pos (28UL) /*!< TASGSR (Bit 28) */ + #define R_ETHA0_EATASGRR_TASGSR_Msk (0x10000000UL) /*!< TASGSR (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASGRR_TASREF_Pos (29UL) /*!< TASREF (Bit 29) */ + #define R_ETHA0_EATASGRR_TASREF_Msk (0x20000000UL) /*!< TASREF (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASGRR_GR_Pos (31UL) /*!< GR (Bit 31) */ + #define R_ETHA0_EATASGRR_GR_Msk (0x80000000UL) /*!< GR (Bitfield-Mask: 0x01) */ +/* ======================================================= EATASHCC ======================================================== */ + #define R_ETHA0_EATASHCC_TASJ_Pos (0UL) /*!< TASJ (Bit 0) */ + #define R_ETHA0_EATASHCC_TASJ_Msk (0xffffUL) /*!< TASJ (Bitfield-Mask: 0xffff) */ +/* ======================================================= EATASRIRM ======================================================= */ + #define R_ETHA0_EATASRIRM_TASRIOG_Pos (0UL) /*!< TASRIOG (Bit 0) */ + #define R_ETHA0_EATASRIRM_TASRIOG_Msk (0x1UL) /*!< TASRIOG (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASRIRM_TASRR_Pos (1UL) /*!< TASRR (Bit 1) */ + #define R_ETHA0_EATASRIRM_TASRR_Msk (0x2UL) /*!< TASRR (Bitfield-Mask: 0x01) */ +/* ======================================================== EATASSM ======================================================== */ + #define R_ETHA0_EATASSM_TASGS0_Pos (0UL) /*!< TASGS0 (Bit 0) */ + #define R_ETHA0_EATASSM_TASGS0_Msk (0x1UL) /*!< TASGS0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS1_Pos (1UL) /*!< TASGS1 (Bit 1) */ + #define R_ETHA0_EATASSM_TASGS1_Msk (0x2UL) /*!< TASGS1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS2_Pos (2UL) /*!< TASGS2 (Bit 2) */ + #define R_ETHA0_EATASSM_TASGS2_Msk (0x4UL) /*!< TASGS2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS3_Pos (3UL) /*!< TASGS3 (Bit 3) */ + #define R_ETHA0_EATASSM_TASGS3_Msk (0x8UL) /*!< TASGS3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS4_Pos (4UL) /*!< TASGS4 (Bit 4) */ + #define R_ETHA0_EATASSM_TASGS4_Msk (0x10UL) /*!< TASGS4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS5_Pos (5UL) /*!< TASGS5 (Bit 5) */ + #define R_ETHA0_EATASSM_TASGS5_Msk (0x20UL) /*!< TASGS5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS6_Pos (6UL) /*!< TASGS6 (Bit 6) */ + #define R_ETHA0_EATASSM_TASGS6_Msk (0x40UL) /*!< TASGS6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASGS7_Pos (7UL) /*!< TASGS7 (Bit 7) */ + #define R_ETHA0_EATASSM_TASGS7_Msk (0x80UL) /*!< TASGS7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASCTGS_Pos (8UL) /*!< TASCTGS (Bit 8) */ + #define R_ETHA0_EATASSM_TASCTGS_Msk (0x100UL) /*!< TASCTGS (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EATASSM_TASSO_Pos (16UL) /*!< TASSO (Bit 16) */ + #define R_ETHA0_EATASSM_TASSO_Msk (0x10000UL) /*!< TASSO (Bitfield-Mask: 0x01) */ +/* ====================================================== EAUSMFSECN ======================================================= */ + #define R_ETHA0_EAUSMFSECN_USMFSEN_Pos (0UL) /*!< USMFSEN (Bit 0) */ + #define R_ETHA0_EAUSMFSECN_USMFSEN_Msk (0xffffUL) /*!< USMFSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EATFECN ======================================================== */ + #define R_ETHA0_EATFECN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ + #define R_ETHA0_EATFECN_TFEN_Msk (0xffffUL) /*!< TFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EAFSECN ======================================================== */ + #define R_ETHA0_EAFSECN_FSEN_Pos (0UL) /*!< FSEN (Bit 0) */ + #define R_ETHA0_EAFSECN_FSEN_Msk (0xffffUL) /*!< FSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= EADQOECN ======================================================== */ + #define R_ETHA0_EADQOECN_DQOEN_Pos (0UL) /*!< DQOEN (Bit 0) */ + #define R_ETHA0_EADQOECN_DQOEN_Msk (0xffffUL) /*!< DQOEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= EADQSECN ======================================================== */ + #define R_ETHA0_EADQSECN_DQSEN_Pos (0UL) /*!< DQSEN (Bit 0) */ + #define R_ETHA0_EADQSECN_DQSEN_Msk (0xffffUL) /*!< DQSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== EAEIS0 ========================================================= */ + #define R_ETHA0_EAEIS0_DECCES_Pos (0UL) /*!< DECCES (Bit 0) */ + #define R_ETHA0_EAEIS0_DECCES_Msk (0x1UL) /*!< DECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TECCES_Pos (1UL) /*!< TECCES (Bit 1) */ + #define R_ETHA0_EAEIS0_TECCES_Msk (0x2UL) /*!< TECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_PECCES_Pos (2UL) /*!< PECCES (Bit 2) */ + #define R_ETHA0_EAEIS0_PECCES_Msk (0x4UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_DSECCES_Pos (3UL) /*!< DSECCES (Bit 3) */ + #define R_ETHA0_EAEIS0_DSECCES_Msk (0x8UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_L23UECCES_Pos (4UL) /*!< L23UECCES (Bit 4) */ + #define R_ETHA0_EAEIS0_L23UECCES_Msk (0x10UL) /*!< L23UECCES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_USMFSES_Pos (5UL) /*!< USMFSES (Bit 5) */ + #define R_ETHA0_EAEIS0_USMFSES_Msk (0x20UL) /*!< USMFSES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TFES_Pos (6UL) /*!< TFES (Bit 6) */ + #define R_ETHA0_EAEIS0_TFES_Msk (0x40UL) /*!< TFES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES0_Pos (8UL) /*!< FSES0 (Bit 8) */ + #define R_ETHA0_EAEIS0_FSES0_Msk (0x100UL) /*!< FSES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES1_Pos (9UL) /*!< FSES1 (Bit 9) */ + #define R_ETHA0_EAEIS0_FSES1_Msk (0x200UL) /*!< FSES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES2_Pos (10UL) /*!< FSES2 (Bit 10) */ + #define R_ETHA0_EAEIS0_FSES2_Msk (0x400UL) /*!< FSES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES3_Pos (11UL) /*!< FSES3 (Bit 11) */ + #define R_ETHA0_EAEIS0_FSES3_Msk (0x800UL) /*!< FSES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES4_Pos (12UL) /*!< FSES4 (Bit 12) */ + #define R_ETHA0_EAEIS0_FSES4_Msk (0x1000UL) /*!< FSES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES5_Pos (13UL) /*!< FSES5 (Bit 13) */ + #define R_ETHA0_EAEIS0_FSES5_Msk (0x2000UL) /*!< FSES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES6_Pos (14UL) /*!< FSES6 (Bit 14) */ + #define R_ETHA0_EAEIS0_FSES6_Msk (0x4000UL) /*!< FSES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_FSES7_Pos (15UL) /*!< FSES7 (Bit 15) */ + #define R_ETHA0_EAEIS0_FSES7_Msk (0x8000UL) /*!< FSES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES0_Pos (16UL) /*!< TASGEES0 (Bit 16) */ + #define R_ETHA0_EAEIS0_TASGEES0_Msk (0x10000UL) /*!< TASGEES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES1_Pos (17UL) /*!< TASGEES1 (Bit 17) */ + #define R_ETHA0_EAEIS0_TASGEES1_Msk (0x20000UL) /*!< TASGEES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES2_Pos (18UL) /*!< TASGEES2 (Bit 18) */ + #define R_ETHA0_EAEIS0_TASGEES2_Msk (0x40000UL) /*!< TASGEES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES3_Pos (19UL) /*!< TASGEES3 (Bit 19) */ + #define R_ETHA0_EAEIS0_TASGEES3_Msk (0x80000UL) /*!< TASGEES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES4_Pos (20UL) /*!< TASGEES4 (Bit 20) */ + #define R_ETHA0_EAEIS0_TASGEES4_Msk (0x100000UL) /*!< TASGEES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES5_Pos (21UL) /*!< TASGEES5 (Bit 21) */ + #define R_ETHA0_EAEIS0_TASGEES5_Msk (0x200000UL) /*!< TASGEES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES6_Pos (22UL) /*!< TASGEES6 (Bit 22) */ + #define R_ETHA0_EAEIS0_TASGEES6_Msk (0x400000UL) /*!< TASGEES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASGEES7_Pos (23UL) /*!< TASGEES7 (Bit 23) */ + #define R_ETHA0_EAEIS0_TASGEES7_Msk (0x800000UL) /*!< TASGEES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS0_TASCTGEES_Pos (24UL) /*!< TASCTGEES (Bit 24) */ + #define R_ETHA0_EAEIS0_TASCTGEES_Msk (0x1000000UL) /*!< TASCTGEES (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE0 ========================================================= */ + #define R_ETHA0_EAEIE0_DECCEE_Pos (0UL) /*!< DECCEE (Bit 0) */ + #define R_ETHA0_EAEIE0_DECCEE_Msk (0x1UL) /*!< DECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TECCEE_Pos (1UL) /*!< TECCEE (Bit 1) */ + #define R_ETHA0_EAEIE0_TECCEE_Msk (0x2UL) /*!< TECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_PECCEE_Pos (2UL) /*!< PECCEE (Bit 2) */ + #define R_ETHA0_EAEIE0_PECCEE_Msk (0x4UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_DSECCEE_Pos (3UL) /*!< DSECCEE (Bit 3) */ + #define R_ETHA0_EAEIE0_DSECCEE_Msk (0x8UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_L23UECCEE_Pos (4UL) /*!< L23UECCEE (Bit 4) */ + #define R_ETHA0_EAEIE0_L23UECCEE_Msk (0x10UL) /*!< L23UECCEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_USMFSEE_Pos (5UL) /*!< USMFSEE (Bit 5) */ + #define R_ETHA0_EAEIE0_USMFSEE_Msk (0x20UL) /*!< USMFSEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TFEE_Pos (6UL) /*!< TFEE (Bit 6) */ + #define R_ETHA0_EAEIE0_TFEE_Msk (0x40UL) /*!< TFEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE0_Pos (8UL) /*!< FSEE0 (Bit 8) */ + #define R_ETHA0_EAEIE0_FSEE0_Msk (0x100UL) /*!< FSEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE1_Pos (9UL) /*!< FSEE1 (Bit 9) */ + #define R_ETHA0_EAEIE0_FSEE1_Msk (0x200UL) /*!< FSEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE2_Pos (10UL) /*!< FSEE2 (Bit 10) */ + #define R_ETHA0_EAEIE0_FSEE2_Msk (0x400UL) /*!< FSEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE3_Pos (11UL) /*!< FSEE3 (Bit 11) */ + #define R_ETHA0_EAEIE0_FSEE3_Msk (0x800UL) /*!< FSEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE4_Pos (12UL) /*!< FSEE4 (Bit 12) */ + #define R_ETHA0_EAEIE0_FSEE4_Msk (0x1000UL) /*!< FSEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE5_Pos (13UL) /*!< FSEE5 (Bit 13) */ + #define R_ETHA0_EAEIE0_FSEE5_Msk (0x2000UL) /*!< FSEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE6_Pos (14UL) /*!< FSEE6 (Bit 14) */ + #define R_ETHA0_EAEIE0_FSEE6_Msk (0x4000UL) /*!< FSEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_FSEE7_Pos (15UL) /*!< FSEE7 (Bit 15) */ + #define R_ETHA0_EAEIE0_FSEE7_Msk (0x8000UL) /*!< FSEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE0_Pos (16UL) /*!< TASGEEE0 (Bit 16) */ + #define R_ETHA0_EAEIE0_TASGEEE0_Msk (0x10000UL) /*!< TASGEEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE1_Pos (17UL) /*!< TASGEEE1 (Bit 17) */ + #define R_ETHA0_EAEIE0_TASGEEE1_Msk (0x20000UL) /*!< TASGEEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE2_Pos (18UL) /*!< TASGEEE2 (Bit 18) */ + #define R_ETHA0_EAEIE0_TASGEEE2_Msk (0x40000UL) /*!< TASGEEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE3_Pos (19UL) /*!< TASGEEE3 (Bit 19) */ + #define R_ETHA0_EAEIE0_TASGEEE3_Msk (0x80000UL) /*!< TASGEEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE4_Pos (20UL) /*!< TASGEEE4 (Bit 20) */ + #define R_ETHA0_EAEIE0_TASGEEE4_Msk (0x100000UL) /*!< TASGEEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE5_Pos (21UL) /*!< TASGEEE5 (Bit 21) */ + #define R_ETHA0_EAEIE0_TASGEEE5_Msk (0x200000UL) /*!< TASGEEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE6_Pos (22UL) /*!< TASGEEE6 (Bit 22) */ + #define R_ETHA0_EAEIE0_TASGEEE6_Msk (0x400000UL) /*!< TASGEEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASGEEE7_Pos (23UL) /*!< TASGEEE7 (Bit 23) */ + #define R_ETHA0_EAEIE0_TASGEEE7_Msk (0x800000UL) /*!< TASGEEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE0_TASCTGEEE_Pos (24UL) /*!< TASCTGEEE (Bit 24) */ + #define R_ETHA0_EAEIE0_TASCTGEEE_Msk (0x1000000UL) /*!< TASCTGEEE (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID0 ========================================================= */ + #define R_ETHA0_EAEID0_DECCED_Pos (0UL) /*!< DECCED (Bit 0) */ + #define R_ETHA0_EAEID0_DECCED_Msk (0x1UL) /*!< DECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TECCED_Pos (1UL) /*!< TECCED (Bit 1) */ + #define R_ETHA0_EAEID0_TECCED_Msk (0x2UL) /*!< TECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_PECCED_Pos (2UL) /*!< PECCED (Bit 2) */ + #define R_ETHA0_EAEID0_PECCED_Msk (0x4UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_DSECCED_Pos (3UL) /*!< DSECCED (Bit 3) */ + #define R_ETHA0_EAEID0_DSECCED_Msk (0x8UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_L23UECCED_Pos (4UL) /*!< L23UECCED (Bit 4) */ + #define R_ETHA0_EAEID0_L23UECCED_Msk (0x10UL) /*!< L23UECCED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_USMFSED_Pos (5UL) /*!< USMFSED (Bit 5) */ + #define R_ETHA0_EAEID0_USMFSED_Msk (0x20UL) /*!< USMFSED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TFED_Pos (6UL) /*!< TFED (Bit 6) */ + #define R_ETHA0_EAEID0_TFED_Msk (0x40UL) /*!< TFED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED0_Pos (8UL) /*!< FSED0 (Bit 8) */ + #define R_ETHA0_EAEID0_FSED0_Msk (0x100UL) /*!< FSED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED1_Pos (9UL) /*!< FSED1 (Bit 9) */ + #define R_ETHA0_EAEID0_FSED1_Msk (0x200UL) /*!< FSED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED2_Pos (10UL) /*!< FSED2 (Bit 10) */ + #define R_ETHA0_EAEID0_FSED2_Msk (0x400UL) /*!< FSED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED3_Pos (11UL) /*!< FSED3 (Bit 11) */ + #define R_ETHA0_EAEID0_FSED3_Msk (0x800UL) /*!< FSED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED4_Pos (12UL) /*!< FSED4 (Bit 12) */ + #define R_ETHA0_EAEID0_FSED4_Msk (0x1000UL) /*!< FSED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED5_Pos (13UL) /*!< FSED5 (Bit 13) */ + #define R_ETHA0_EAEID0_FSED5_Msk (0x2000UL) /*!< FSED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED6_Pos (14UL) /*!< FSED6 (Bit 14) */ + #define R_ETHA0_EAEID0_FSED6_Msk (0x4000UL) /*!< FSED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_FSED7_Pos (15UL) /*!< FSED7 (Bit 15) */ + #define R_ETHA0_EAEID0_FSED7_Msk (0x8000UL) /*!< FSED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED0_Pos (16UL) /*!< TASGEED0 (Bit 16) */ + #define R_ETHA0_EAEID0_TASGEED0_Msk (0x10000UL) /*!< TASGEED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED1_Pos (17UL) /*!< TASGEED1 (Bit 17) */ + #define R_ETHA0_EAEID0_TASGEED1_Msk (0x20000UL) /*!< TASGEED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED2_Pos (18UL) /*!< TASGEED2 (Bit 18) */ + #define R_ETHA0_EAEID0_TASGEED2_Msk (0x40000UL) /*!< TASGEED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED3_Pos (19UL) /*!< TASGEED3 (Bit 19) */ + #define R_ETHA0_EAEID0_TASGEED3_Msk (0x80000UL) /*!< TASGEED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED4_Pos (20UL) /*!< TASGEED4 (Bit 20) */ + #define R_ETHA0_EAEID0_TASGEED4_Msk (0x100000UL) /*!< TASGEED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED5_Pos (21UL) /*!< TASGEED5 (Bit 21) */ + #define R_ETHA0_EAEID0_TASGEED5_Msk (0x200000UL) /*!< TASGEED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED6_Pos (22UL) /*!< TASGEED6 (Bit 22) */ + #define R_ETHA0_EAEID0_TASGEED6_Msk (0x400000UL) /*!< TASGEED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASGEED7_Pos (23UL) /*!< TASGEED7 (Bit 23) */ + #define R_ETHA0_EAEID0_TASGEED7_Msk (0x800000UL) /*!< TASGEED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID0_TASCTGEED_Pos (24UL) /*!< TASCTGEED (Bit 24) */ + #define R_ETHA0_EAEID0_TASCTGEED_Msk (0x1000000UL) /*!< TASCTGEED (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIS1 ========================================================= */ + #define R_ETHA0_EAEIS1_CULES0_Pos (0UL) /*!< CULES0 (Bit 0) */ + #define R_ETHA0_EAEIS1_CULES0_Msk (0x1UL) /*!< CULES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES1_Pos (1UL) /*!< CULES1 (Bit 1) */ + #define R_ETHA0_EAEIS1_CULES1_Msk (0x2UL) /*!< CULES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES2_Pos (2UL) /*!< CULES2 (Bit 2) */ + #define R_ETHA0_EAEIS1_CULES2_Msk (0x4UL) /*!< CULES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES3_Pos (3UL) /*!< CULES3 (Bit 3) */ + #define R_ETHA0_EAEIS1_CULES3_Msk (0x8UL) /*!< CULES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES4_Pos (4UL) /*!< CULES4 (Bit 4) */ + #define R_ETHA0_EAEIS1_CULES4_Msk (0x10UL) /*!< CULES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES5_Pos (5UL) /*!< CULES5 (Bit 5) */ + #define R_ETHA0_EAEIS1_CULES5_Msk (0x20UL) /*!< CULES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES6_Pos (6UL) /*!< CULES6 (Bit 6) */ + #define R_ETHA0_EAEIS1_CULES6_Msk (0x40UL) /*!< CULES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_CULES7_Pos (7UL) /*!< CULES7 (Bit 7) */ + #define R_ETHA0_EAEIS1_CULES7_Msk (0x80UL) /*!< CULES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES0_Pos (16UL) /*!< TASGES0 (Bit 16) */ + #define R_ETHA0_EAEIS1_TASGES0_Msk (0x10000UL) /*!< TASGES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES1_Pos (17UL) /*!< TASGES1 (Bit 17) */ + #define R_ETHA0_EAEIS1_TASGES1_Msk (0x20000UL) /*!< TASGES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES2_Pos (18UL) /*!< TASGES2 (Bit 18) */ + #define R_ETHA0_EAEIS1_TASGES2_Msk (0x40000UL) /*!< TASGES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES3_Pos (19UL) /*!< TASGES3 (Bit 19) */ + #define R_ETHA0_EAEIS1_TASGES3_Msk (0x80000UL) /*!< TASGES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES4_Pos (20UL) /*!< TASGES4 (Bit 20) */ + #define R_ETHA0_EAEIS1_TASGES4_Msk (0x100000UL) /*!< TASGES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES5_Pos (21UL) /*!< TASGES5 (Bit 21) */ + #define R_ETHA0_EAEIS1_TASGES5_Msk (0x200000UL) /*!< TASGES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES6_Pos (22UL) /*!< TASGES6 (Bit 22) */ + #define R_ETHA0_EAEIS1_TASGES6_Msk (0x400000UL) /*!< TASGES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASGES7_Pos (23UL) /*!< TASGES7 (Bit 23) */ + #define R_ETHA0_EAEIS1_TASGES7_Msk (0x800000UL) /*!< TASGES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS1_TASCTGES_Pos (24UL) /*!< TASCTGES (Bit 24) */ + #define R_ETHA0_EAEIS1_TASCTGES_Msk (0x1000000UL) /*!< TASCTGES (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE1 ========================================================= */ + #define R_ETHA0_EAEIE1_CULEE0_Pos (0UL) /*!< CULEE0 (Bit 0) */ + #define R_ETHA0_EAEIE1_CULEE0_Msk (0x1UL) /*!< CULEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE1_Pos (1UL) /*!< CULEE1 (Bit 1) */ + #define R_ETHA0_EAEIE1_CULEE1_Msk (0x2UL) /*!< CULEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE2_Pos (2UL) /*!< CULEE2 (Bit 2) */ + #define R_ETHA0_EAEIE1_CULEE2_Msk (0x4UL) /*!< CULEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE3_Pos (3UL) /*!< CULEE3 (Bit 3) */ + #define R_ETHA0_EAEIE1_CULEE3_Msk (0x8UL) /*!< CULEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE4_Pos (4UL) /*!< CULEE4 (Bit 4) */ + #define R_ETHA0_EAEIE1_CULEE4_Msk (0x10UL) /*!< CULEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE5_Pos (5UL) /*!< CULEE5 (Bit 5) */ + #define R_ETHA0_EAEIE1_CULEE5_Msk (0x20UL) /*!< CULEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE6_Pos (6UL) /*!< CULEE6 (Bit 6) */ + #define R_ETHA0_EAEIE1_CULEE6_Msk (0x40UL) /*!< CULEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_CULEE7_Pos (7UL) /*!< CULEE7 (Bit 7) */ + #define R_ETHA0_EAEIE1_CULEE7_Msk (0x80UL) /*!< CULEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE0_Pos (16UL) /*!< TASGEE0 (Bit 16) */ + #define R_ETHA0_EAEIE1_TASGEE0_Msk (0x10000UL) /*!< TASGEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE1_Pos (17UL) /*!< TASGEE1 (Bit 17) */ + #define R_ETHA0_EAEIE1_TASGEE1_Msk (0x20000UL) /*!< TASGEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE2_Pos (18UL) /*!< TASGEE2 (Bit 18) */ + #define R_ETHA0_EAEIE1_TASGEE2_Msk (0x40000UL) /*!< TASGEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE3_Pos (19UL) /*!< TASGEE3 (Bit 19) */ + #define R_ETHA0_EAEIE1_TASGEE3_Msk (0x80000UL) /*!< TASGEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE4_Pos (20UL) /*!< TASGEE4 (Bit 20) */ + #define R_ETHA0_EAEIE1_TASGEE4_Msk (0x100000UL) /*!< TASGEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE5_Pos (21UL) /*!< TASGEE5 (Bit 21) */ + #define R_ETHA0_EAEIE1_TASGEE5_Msk (0x200000UL) /*!< TASGEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE6_Pos (22UL) /*!< TASGEE6 (Bit 22) */ + #define R_ETHA0_EAEIE1_TASGEE6_Msk (0x400000UL) /*!< TASGEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASGEE7_Pos (23UL) /*!< TASGEE7 (Bit 23) */ + #define R_ETHA0_EAEIE1_TASGEE7_Msk (0x800000UL) /*!< TASGEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE1_TASCTGEE_Pos (24UL) /*!< TASCTGEE (Bit 24) */ + #define R_ETHA0_EAEIE1_TASCTGEE_Msk (0x1000000UL) /*!< TASCTGEE (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID1 ========================================================= */ + #define R_ETHA0_EAEID1_CULED0_Pos (0UL) /*!< CULED0 (Bit 0) */ + #define R_ETHA0_EAEID1_CULED0_Msk (0x1UL) /*!< CULED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED1_Pos (1UL) /*!< CULED1 (Bit 1) */ + #define R_ETHA0_EAEID1_CULED1_Msk (0x2UL) /*!< CULED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED2_Pos (2UL) /*!< CULED2 (Bit 2) */ + #define R_ETHA0_EAEID1_CULED2_Msk (0x4UL) /*!< CULED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED3_Pos (3UL) /*!< CULED3 (Bit 3) */ + #define R_ETHA0_EAEID1_CULED3_Msk (0x8UL) /*!< CULED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED4_Pos (4UL) /*!< CULED4 (Bit 4) */ + #define R_ETHA0_EAEID1_CULED4_Msk (0x10UL) /*!< CULED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED5_Pos (5UL) /*!< CULED5 (Bit 5) */ + #define R_ETHA0_EAEID1_CULED5_Msk (0x20UL) /*!< CULED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED6_Pos (6UL) /*!< CULED6 (Bit 6) */ + #define R_ETHA0_EAEID1_CULED6_Msk (0x40UL) /*!< CULED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_CULED7_Pos (7UL) /*!< CULED7 (Bit 7) */ + #define R_ETHA0_EAEID1_CULED7_Msk (0x80UL) /*!< CULED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED0_Pos (16UL) /*!< TASGED0 (Bit 16) */ + #define R_ETHA0_EAEID1_TASGED0_Msk (0x10000UL) /*!< TASGED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED1_Pos (17UL) /*!< TASGED1 (Bit 17) */ + #define R_ETHA0_EAEID1_TASGED1_Msk (0x20000UL) /*!< TASGED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED2_Pos (18UL) /*!< TASGED2 (Bit 18) */ + #define R_ETHA0_EAEID1_TASGED2_Msk (0x40000UL) /*!< TASGED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED3_Pos (19UL) /*!< TASGED3 (Bit 19) */ + #define R_ETHA0_EAEID1_TASGED3_Msk (0x80000UL) /*!< TASGED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED4_Pos (20UL) /*!< TASGED4 (Bit 20) */ + #define R_ETHA0_EAEID1_TASGED4_Msk (0x100000UL) /*!< TASGED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED5_Pos (21UL) /*!< TASGED5 (Bit 21) */ + #define R_ETHA0_EAEID1_TASGED5_Msk (0x200000UL) /*!< TASGED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED6_Pos (22UL) /*!< TASGED6 (Bit 22) */ + #define R_ETHA0_EAEID1_TASGED6_Msk (0x400000UL) /*!< TASGED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASGED7_Pos (23UL) /*!< TASGED7 (Bit 23) */ + #define R_ETHA0_EAEID1_TASGED7_Msk (0x800000UL) /*!< TASGED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID1_TASCTGED_Pos (24UL) /*!< TASCTGED (Bit 24) */ + #define R_ETHA0_EAEID1_TASCTGED_Msk (0x1000000UL) /*!< TASCTGED (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIS2 ========================================================= */ + #define R_ETHA0_EAEIS2_DQOES0_Pos (0UL) /*!< DQOES0 (Bit 0) */ + #define R_ETHA0_EAEIS2_DQOES0_Msk (0x1UL) /*!< DQOES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES1_Pos (1UL) /*!< DQOES1 (Bit 1) */ + #define R_ETHA0_EAEIS2_DQOES1_Msk (0x2UL) /*!< DQOES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES2_Pos (2UL) /*!< DQOES2 (Bit 2) */ + #define R_ETHA0_EAEIS2_DQOES2_Msk (0x4UL) /*!< DQOES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES3_Pos (3UL) /*!< DQOES3 (Bit 3) */ + #define R_ETHA0_EAEIS2_DQOES3_Msk (0x8UL) /*!< DQOES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES4_Pos (4UL) /*!< DQOES4 (Bit 4) */ + #define R_ETHA0_EAEIS2_DQOES4_Msk (0x10UL) /*!< DQOES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES5_Pos (5UL) /*!< DQOES5 (Bit 5) */ + #define R_ETHA0_EAEIS2_DQOES5_Msk (0x20UL) /*!< DQOES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES6_Pos (6UL) /*!< DQOES6 (Bit 6) */ + #define R_ETHA0_EAEIS2_DQOES6_Msk (0x40UL) /*!< DQOES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQOES7_Pos (7UL) /*!< DQOES7 (Bit 7) */ + #define R_ETHA0_EAEIS2_DQOES7_Msk (0x80UL) /*!< DQOES7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_CTDQOES_Pos (8UL) /*!< CTDQOES (Bit 8) */ + #define R_ETHA0_EAEIS2_CTDQOES_Msk (0x100UL) /*!< CTDQOES (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES0_Pos (16UL) /*!< DQSES0 (Bit 16) */ + #define R_ETHA0_EAEIS2_DQSES0_Msk (0x10000UL) /*!< DQSES0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES1_Pos (17UL) /*!< DQSES1 (Bit 17) */ + #define R_ETHA0_EAEIS2_DQSES1_Msk (0x20000UL) /*!< DQSES1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES2_Pos (18UL) /*!< DQSES2 (Bit 18) */ + #define R_ETHA0_EAEIS2_DQSES2_Msk (0x40000UL) /*!< DQSES2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES3_Pos (19UL) /*!< DQSES3 (Bit 19) */ + #define R_ETHA0_EAEIS2_DQSES3_Msk (0x80000UL) /*!< DQSES3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES4_Pos (20UL) /*!< DQSES4 (Bit 20) */ + #define R_ETHA0_EAEIS2_DQSES4_Msk (0x100000UL) /*!< DQSES4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES5_Pos (21UL) /*!< DQSES5 (Bit 21) */ + #define R_ETHA0_EAEIS2_DQSES5_Msk (0x200000UL) /*!< DQSES5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES6_Pos (22UL) /*!< DQSES6 (Bit 22) */ + #define R_ETHA0_EAEIS2_DQSES6_Msk (0x400000UL) /*!< DQSES6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIS2_DQSES7_Pos (23UL) /*!< DQSES7 (Bit 23) */ + #define R_ETHA0_EAEIS2_DQSES7_Msk (0x800000UL) /*!< DQSES7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEIE2 ========================================================= */ + #define R_ETHA0_EAEIE2_DQOEE0_Pos (0UL) /*!< DQOEE0 (Bit 0) */ + #define R_ETHA0_EAEIE2_DQOEE0_Msk (0x1UL) /*!< DQOEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE1_Pos (1UL) /*!< DQOEE1 (Bit 1) */ + #define R_ETHA0_EAEIE2_DQOEE1_Msk (0x2UL) /*!< DQOEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE2_Pos (2UL) /*!< DQOEE2 (Bit 2) */ + #define R_ETHA0_EAEIE2_DQOEE2_Msk (0x4UL) /*!< DQOEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE3_Pos (3UL) /*!< DQOEE3 (Bit 3) */ + #define R_ETHA0_EAEIE2_DQOEE3_Msk (0x8UL) /*!< DQOEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE4_Pos (4UL) /*!< DQOEE4 (Bit 4) */ + #define R_ETHA0_EAEIE2_DQOEE4_Msk (0x10UL) /*!< DQOEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE5_Pos (5UL) /*!< DQOEE5 (Bit 5) */ + #define R_ETHA0_EAEIE2_DQOEE5_Msk (0x20UL) /*!< DQOEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE6_Pos (6UL) /*!< DQOEE6 (Bit 6) */ + #define R_ETHA0_EAEIE2_DQOEE6_Msk (0x40UL) /*!< DQOEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQOEE7_Pos (7UL) /*!< DQOEE7 (Bit 7) */ + #define R_ETHA0_EAEIE2_DQOEE7_Msk (0x80UL) /*!< DQOEE7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_CTDQOEE_Pos (8UL) /*!< CTDQOEE (Bit 8) */ + #define R_ETHA0_EAEIE2_CTDQOEE_Msk (0x100UL) /*!< CTDQOEE (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE0_Pos (16UL) /*!< DQSEE0 (Bit 16) */ + #define R_ETHA0_EAEIE2_DQSEE0_Msk (0x10000UL) /*!< DQSEE0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE1_Pos (17UL) /*!< DQSEE1 (Bit 17) */ + #define R_ETHA0_EAEIE2_DQSEE1_Msk (0x20000UL) /*!< DQSEE1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE2_Pos (18UL) /*!< DQSEE2 (Bit 18) */ + #define R_ETHA0_EAEIE2_DQSEE2_Msk (0x40000UL) /*!< DQSEE2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE3_Pos (19UL) /*!< DQSEE3 (Bit 19) */ + #define R_ETHA0_EAEIE2_DQSEE3_Msk (0x80000UL) /*!< DQSEE3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE4_Pos (20UL) /*!< DQSEE4 (Bit 20) */ + #define R_ETHA0_EAEIE2_DQSEE4_Msk (0x100000UL) /*!< DQSEE4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE5_Pos (21UL) /*!< DQSEE5 (Bit 21) */ + #define R_ETHA0_EAEIE2_DQSEE5_Msk (0x200000UL) /*!< DQSEE5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE6_Pos (22UL) /*!< DQSEE6 (Bit 22) */ + #define R_ETHA0_EAEIE2_DQSEE6_Msk (0x400000UL) /*!< DQSEE6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEIE2_DQSEE7_Pos (23UL) /*!< DQSEE7 (Bit 23) */ + #define R_ETHA0_EAEIE2_DQSEE7_Msk (0x800000UL) /*!< DQSEE7 (Bitfield-Mask: 0x01) */ +/* ======================================================== EAEID2 ========================================================= */ + #define R_ETHA0_EAEID2_DQOED0_Pos (0UL) /*!< DQOED0 (Bit 0) */ + #define R_ETHA0_EAEID2_DQOED0_Msk (0x1UL) /*!< DQOED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED1_Pos (1UL) /*!< DQOED1 (Bit 1) */ + #define R_ETHA0_EAEID2_DQOED1_Msk (0x2UL) /*!< DQOED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED2_Pos (2UL) /*!< DQOED2 (Bit 2) */ + #define R_ETHA0_EAEID2_DQOED2_Msk (0x4UL) /*!< DQOED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED3_Pos (3UL) /*!< DQOED3 (Bit 3) */ + #define R_ETHA0_EAEID2_DQOED3_Msk (0x8UL) /*!< DQOED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED4_Pos (4UL) /*!< DQOED4 (Bit 4) */ + #define R_ETHA0_EAEID2_DQOED4_Msk (0x10UL) /*!< DQOED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED5_Pos (5UL) /*!< DQOED5 (Bit 5) */ + #define R_ETHA0_EAEID2_DQOED5_Msk (0x20UL) /*!< DQOED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED6_Pos (6UL) /*!< DQOED6 (Bit 6) */ + #define R_ETHA0_EAEID2_DQOED6_Msk (0x40UL) /*!< DQOED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQOED7_Pos (7UL) /*!< DQOED7 (Bit 7) */ + #define R_ETHA0_EAEID2_DQOED7_Msk (0x80UL) /*!< DQOED7 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_CTDQOED_Pos (8UL) /*!< CTDQOED (Bit 8) */ + #define R_ETHA0_EAEID2_CTDQOED_Msk (0x100UL) /*!< CTDQOED (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED0_Pos (16UL) /*!< DQSED0 (Bit 16) */ + #define R_ETHA0_EAEID2_DQSED0_Msk (0x10000UL) /*!< DQSED0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED1_Pos (17UL) /*!< DQSED1 (Bit 17) */ + #define R_ETHA0_EAEID2_DQSED1_Msk (0x20000UL) /*!< DQSED1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED2_Pos (18UL) /*!< DQSED2 (Bit 18) */ + #define R_ETHA0_EAEID2_DQSED2_Msk (0x40000UL) /*!< DQSED2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED3_Pos (19UL) /*!< DQSED3 (Bit 19) */ + #define R_ETHA0_EAEID2_DQSED3_Msk (0x80000UL) /*!< DQSED3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED4_Pos (20UL) /*!< DQSED4 (Bit 20) */ + #define R_ETHA0_EAEID2_DQSED4_Msk (0x100000UL) /*!< DQSED4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED5_Pos (21UL) /*!< DQSED5 (Bit 21) */ + #define R_ETHA0_EAEID2_DQSED5_Msk (0x200000UL) /*!< DQSED5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED6_Pos (22UL) /*!< DQSED6 (Bit 22) */ + #define R_ETHA0_EAEID2_DQSED6_Msk (0x400000UL) /*!< DQSED6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EAEID2_DQSED7_Pos (23UL) /*!< DQSED7 (Bit 23) */ + #define R_ETHA0_EAEID2_DQSED7_Msk (0x800000UL) /*!< DQSED7 (Bitfield-Mask: 0x01) */ +/* ========================================================= EASCR ========================================================= */ + #define R_ETHA0_EASCR_MRSL_Pos (0UL) /*!< MRSL (Bit 0) */ + #define R_ETHA0_EASCR_MRSL_Msk (0x1UL) /*!< MRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TRSL_Pos (1UL) /*!< TRSL (Bit 1) */ + #define R_ETHA0_EASCR_TRSL_Msk (0x2UL) /*!< TRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_MCRSL_Pos (2UL) /*!< MCRSL (Bit 2) */ + #define R_ETHA0_EASCR_MCRSL_Msk (0x4UL) /*!< MCRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TGRSL_Pos (3UL) /*!< TGRSL (Bit 3) */ + #define R_ETHA0_EASCR_TGRSL_Msk (0x8UL) /*!< TGRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_TASRSL_Pos (4UL) /*!< TASRSL (Bit 4) */ + #define R_ETHA0_EASCR_TASRSL_Msk (0x10UL) /*!< TASRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_EIRSL_Pos (5UL) /*!< EIRSL (Bit 5) */ + #define R_ETHA0_EASCR_EIRSL_Msk (0x20UL) /*!< EIRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_CRSL_Pos (6UL) /*!< CRSL (Bit 6) */ + #define R_ETHA0_EASCR_CRSL_Msk (0x40UL) /*!< CRSL (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL0_Pos (16UL) /*!< DQRSL0 (Bit 16) */ + #define R_ETHA0_EASCR_DQRSL0_Msk (0x10000UL) /*!< DQRSL0 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL1_Pos (17UL) /*!< DQRSL1 (Bit 17) */ + #define R_ETHA0_EASCR_DQRSL1_Msk (0x20000UL) /*!< DQRSL1 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL2_Pos (18UL) /*!< DQRSL2 (Bit 18) */ + #define R_ETHA0_EASCR_DQRSL2_Msk (0x40000UL) /*!< DQRSL2 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL3_Pos (19UL) /*!< DQRSL3 (Bit 19) */ + #define R_ETHA0_EASCR_DQRSL3_Msk (0x80000UL) /*!< DQRSL3 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL4_Pos (20UL) /*!< DQRSL4 (Bit 20) */ + #define R_ETHA0_EASCR_DQRSL4_Msk (0x100000UL) /*!< DQRSL4 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL5_Pos (21UL) /*!< DQRSL5 (Bit 21) */ + #define R_ETHA0_EASCR_DQRSL5_Msk (0x200000UL) /*!< DQRSL5 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL6_Pos (22UL) /*!< DQRSL6 (Bit 22) */ + #define R_ETHA0_EASCR_DQRSL6_Msk (0x400000UL) /*!< DQRSL6 (Bitfield-Mask: 0x01) */ + #define R_ETHA0_EASCR_DQRSL7_Pos (23UL) /*!< DQRSL7 (Bit 23) */ + #define R_ETHA0_EASCR_DQRSL7_Msk (0x800000UL) /*!< DQRSL7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PTPIPV ========================================================= */ + #define R_GPTP_PTPIPV_IPV_Pos (0UL) /*!< IPV (Bit 0) */ + #define R_GPTP_PTPIPV_IPV_Msk (0xffffffffUL) /*!< IPV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PTPTMEC ======================================================== */ + #define R_GPTP_PTPTMEC_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GPTP_PTPTMEC_TE_Msk (0x3UL) /*!< TE (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPTMDC ======================================================== */ + #define R_GPTP_PTPTMDC_TD_Pos (0UL) /*!< TD (Bit 0) */ + #define R_GPTP_PTPTMDC_TD_Msk (0x3UL) /*!< TD (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPTIVC0 ======================================================== */ + #define R_GPTP_PTPTIVC0_TIV_Pos (0UL) /*!< TIV (Bit 0) */ + #define R_GPTP_PTPTIVC0_TIV_Msk (0xffffffffUL) /*!< TIV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTIVC1 ======================================================== */ + #define R_GPTP_PTPTIVC1_TIV_Pos (0UL) /*!< TIV (Bit 0) */ + #define R_GPTP_PTPTIVC1_TIV_Msk (0xffffffffUL) /*!< TIV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCL0 ======================================================= */ + #define R_GPTP_PTPTOVCL0_TOVL_Pos (0UL) /*!< TOVL (Bit 0) */ + #define R_GPTP_PTPTOVCL0_TOVL_Msk (0x3fffffffUL) /*!< TOVL (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= PTPTOVCL1 ======================================================= */ + #define R_GPTP_PTPTOVCL1_TOVL_Pos (0UL) /*!< TOVL (Bit 0) */ + #define R_GPTP_PTPTOVCL1_TOVL_Msk (0x3fffffffUL) /*!< TOVL (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= PTPTOVCM0 ======================================================= */ + #define R_GPTP_PTPTOVCM0_TOVM_Pos (0UL) /*!< TOVM (Bit 0) */ + #define R_GPTP_PTPTOVCM0_TOVM_Msk (0xffffffffUL) /*!< TOVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCM1 ======================================================= */ + #define R_GPTP_PTPTOVCM1_TOVM_Pos (0UL) /*!< TOVM (Bit 0) */ + #define R_GPTP_PTPTOVCM1_TOVM_Msk (0xffffffffUL) /*!< TOVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPTOVCU0 ======================================================= */ + #define R_GPTP_PTPTOVCU0_TOVU_Pos (0UL) /*!< TOVU (Bit 0) */ + #define R_GPTP_PTPTOVCU0_TOVU_Msk (0xffffUL) /*!< TOVU (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPTOVCU1 ======================================================= */ + #define R_GPTP_PTPTOVCU1_TOVU_Pos (0UL) /*!< TOVU (Bit 0) */ + #define R_GPTP_PTPTOVCU1_TOVU_Msk (0xffffUL) /*!< TOVU (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPAVTPTML0 ====================================================== */ + #define R_GPTP_PTPAVTPTML0_AVTPL_Pos (0UL) /*!< AVTPL (Bit 0) */ + #define R_GPTP_PTPAVTPTML0_AVTPL_Msk (0xffffffffUL) /*!< AVTPL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTML1 ====================================================== */ + #define R_GPTP_PTPAVTPTML1_AVTPL_Pos (0UL) /*!< AVTPL (Bit 0) */ + #define R_GPTP_PTPAVTPTML1_AVTPL_Msk (0xffffffffUL) /*!< AVTPL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTMU0 ====================================================== */ + #define R_GPTP_PTPAVTPTMU0_AVTPU_Pos (0UL) /*!< AVTPU (Bit 0) */ + #define R_GPTP_PTPAVTPTMU0_AVTPU_Msk (0xffffffffUL) /*!< AVTPU (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPAVTPTMU1 ====================================================== */ + #define R_GPTP_PTPAVTPTMU1_AVTPU_Pos (0UL) /*!< AVTPU (Bit 0) */ + #define R_GPTP_PTPAVTPTMU1_AVTPU_Msk (0xffffffffUL) /*!< AVTPU (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTML0 ====================================================== */ + #define R_GPTP_PTPGPTPTML0_GPTPL_Pos (0UL) /*!< GPTPL (Bit 0) */ + #define R_GPTP_PTPGPTPTML0_GPTPL_Msk (0x3fffffffUL) /*!< GPTPL (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== PTPGPTPTML1 ====================================================== */ + #define R_GPTP_PTPGPTPTML1_GPTPL_Pos (0UL) /*!< GPTPL (Bit 0) */ + #define R_GPTP_PTPGPTPTML1_GPTPL_Msk (0x3fffffffUL) /*!< GPTPL (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== PTPGPTPTMM0 ====================================================== */ + #define R_GPTP_PTPGPTPTMM0_GPTPM_Pos (0UL) /*!< GPTPM (Bit 0) */ + #define R_GPTP_PTPGPTPTMM0_GPTPM_Msk (0xffffffffUL) /*!< GPTPM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTMM1 ====================================================== */ + #define R_GPTP_PTPGPTPTMM1_GPTPM_Pos (0UL) /*!< GPTPM (Bit 0) */ + #define R_GPTP_PTPGPTPTMM1_GPTPM_Msk (0xffffffffUL) /*!< GPTPM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPGPTPTMU0 ====================================================== */ + #define R_GPTP_PTPGPTPTMU0_GPTPU_Pos (0UL) /*!< GPTPU (Bit 0) */ + #define R_GPTP_PTPGPTPTMU0_GPTPU_Msk (0xffffUL) /*!< GPTPU (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPGPTPTMU1 ====================================================== */ + #define R_GPTP_PTPGPTPTMU1_GPTPU_Pos (0UL) /*!< GPTPU (Bit 0) */ + #define R_GPTP_PTPGPTPTMU1_GPTPU_Msk (0xffffUL) /*!< GPTPU (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPMCCC0 ======================================================== */ + #define R_GPTP_PTPMCCC0_MCPEE_Pos (0UL) /*!< MCPEE (Bit 0) */ + #define R_GPTP_PTPMCCC0_MCPEE_Msk (0x1UL) /*!< MCPEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCNEE_Pos (1UL) /*!< MCNEE (Bit 1) */ + #define R_GPTP_PTPMCCC0_MCNEE_Msk (0x2UL) /*!< MCNEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCTTS_Pos (2UL) /*!< MCTTS (Bit 2) */ + #define R_GPTP_PTPMCCC0_MCTTS_Msk (0x4UL) /*!< MCTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCTNS_Pos (3UL) /*!< MCTNS (Bit 3) */ + #define R_GPTP_PTPMCCC0_MCTNS_Msk (0x8UL) /*!< MCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC0_MCCR_Pos (16UL) /*!< MCCR (Bit 16) */ + #define R_GPTP_PTPMCCC0_MCCR_Msk (0x10000UL) /*!< MCCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCCC1 ======================================================== */ + #define R_GPTP_PTPMCCC1_MCPEE_Pos (0UL) /*!< MCPEE (Bit 0) */ + #define R_GPTP_PTPMCCC1_MCPEE_Msk (0x1UL) /*!< MCPEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCNEE_Pos (1UL) /*!< MCNEE (Bit 1) */ + #define R_GPTP_PTPMCCC1_MCNEE_Msk (0x2UL) /*!< MCNEE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCTTS_Pos (2UL) /*!< MCTTS (Bit 2) */ + #define R_GPTP_PTPMCCC1_MCTTS_Msk (0x4UL) /*!< MCTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCTNS_Pos (3UL) /*!< MCTNS (Bit 3) */ + #define R_GPTP_PTPMCCC1_MCTNS_Msk (0x8UL) /*!< MCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCC1_MCCR_Pos (16UL) /*!< MCCR (Bit 16) */ + #define R_GPTP_PTPMCCC1_MCCR_Msk (0x10000UL) /*!< MCCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCCML0 ======================================================= */ + #define R_GPTP_PTPMCCML0_MCCTVL_Pos (0UL) /*!< MCCTVL (Bit 0) */ + #define R_GPTP_PTPMCCML0_MCCTVL_Msk (0xffffffffUL) /*!< MCCTVL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCML1 ======================================================= */ + #define R_GPTP_PTPMCCML1_MCCTVL_Pos (0UL) /*!< MCCTVL (Bit 0) */ + #define R_GPTP_PTPMCCML1_MCCTVL_Msk (0xffffffffUL) /*!< MCCTVL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMM0 ======================================================= */ + #define R_GPTP_PTPMCCMM0_MCCTVM_Pos (0UL) /*!< MCCTVM (Bit 0) */ + #define R_GPTP_PTPMCCMM0_MCCTVM_Msk (0xffffffffUL) /*!< MCCTVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMM1 ======================================================= */ + #define R_GPTP_PTPMCCMM1_MCCTVM_Pos (0UL) /*!< MCCTVM (Bit 0) */ + #define R_GPTP_PTPMCCMM1_MCCTVM_Msk (0xffffffffUL) /*!< MCCTVM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPMCCMU0 ======================================================= */ + #define R_GPTP_PTPMCCMU0_MCCTVU_Pos (0UL) /*!< MCCTVU (Bit 0) */ + #define R_GPTP_PTPMCCMU0_MCCTVU_Msk (0xffffUL) /*!< MCCTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCCMU0_MCPEC_Pos (16UL) /*!< MCPEC (Bit 16) */ + #define R_GPTP_PTPMCCMU0_MCPEC_Msk (0x10000UL) /*!< MCPEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCNEC_Pos (17UL) /*!< MCNEC (Bit 17) */ + #define R_GPTP_PTPMCCMU0_MCNEC_Msk (0x20000UL) /*!< MCNEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCSWC_Pos (18UL) /*!< MCSWC (Bit 18) */ + #define R_GPTP_PTPMCCMU0_MCSWC_Msk (0x40000UL) /*!< MCSWC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU0_MCCN_Pos (24UL) /*!< MCCN (Bit 24) */ + #define R_GPTP_PTPMCCMU0_MCCN_Msk (0x3000000UL) /*!< MCCN (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPMCCMU1 ======================================================= */ + #define R_GPTP_PTPMCCMU1_MCCTVU_Pos (0UL) /*!< MCCTVU (Bit 0) */ + #define R_GPTP_PTPMCCMU1_MCCTVU_Msk (0xffffUL) /*!< MCCTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCCMU1_MCPEC_Pos (16UL) /*!< MCPEC (Bit 16) */ + #define R_GPTP_PTPMCCMU1_MCPEC_Msk (0x10000UL) /*!< MCPEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCNEC_Pos (17UL) /*!< MCNEC (Bit 17) */ + #define R_GPTP_PTPMCCMU1_MCNEC_Msk (0x20000UL) /*!< MCNEC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCSWC_Pos (18UL) /*!< MCSWC (Bit 18) */ + #define R_GPTP_PTPMCCMU1_MCSWC_Msk (0x40000UL) /*!< MCSWC (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCCMU1_MCCN_Pos (24UL) /*!< MCCN (Bit 24) */ + #define R_GPTP_PTPMCCMU1_MCCN_Msk (0x3000000UL) /*!< MCCN (Bitfield-Mask: 0x03) */ +/* ======================================================= PTPMCRC0 ======================================================== */ + #define R_GPTP_PTPMCRC0_MRTTS_Pos (0UL) /*!< MRTTS (Bit 0) */ + #define R_GPTP_PTPMCRC0_MRTTS_Msk (0x1UL) /*!< MRTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRAMS_Pos (1UL) /*!< MRAMS (Bit 1) */ + #define R_GPTP_PTPMCRC0_MRAMS_Msk (0x2UL) /*!< MRAMS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRTNS_Pos (2UL) /*!< MRTNS (Bit 2) */ + #define R_GPTP_PTPMCRC0_MRTNS_Msk (0x4UL) /*!< MRTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC0_MRPL_Pos (16UL) /*!< MRPL (Bit 16) */ + #define R_GPTP_PTPMCRC0_MRPL_Msk (0xffff0000UL) /*!< MRPL (Bitfield-Mask: 0xffff) */ +/* ======================================================= PTPMCRC1 ======================================================== */ + #define R_GPTP_PTPMCRC1_MRTTS_Pos (0UL) /*!< MRTTS (Bit 0) */ + #define R_GPTP_PTPMCRC1_MRTTS_Msk (0x1UL) /*!< MRTTS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRAMS_Pos (1UL) /*!< MRAMS (Bit 1) */ + #define R_GPTP_PTPMCRC1_MRAMS_Msk (0x2UL) /*!< MRAMS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRTNS_Pos (2UL) /*!< MRTNS (Bit 2) */ + #define R_GPTP_PTPMCRC1_MRTNS_Msk (0x4UL) /*!< MRTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCRC1_MRPL_Pos (16UL) /*!< MRPL (Bit 16) */ + #define R_GPTP_PTPMCRC1_MRPL_Msk (0xffff0000UL) /*!< MRPL (Bitfield-Mask: 0xffff) */ +/* ====================================================== PTPMCRTCL0 ======================================================= */ + #define R_GPTP_PTPMCRTCL0_MRTVL_Pos (0UL) /*!< MRTVL (Bit 0) */ + #define R_GPTP_PTPMCRTCL0_MRTVL_Msk (0xffffffffUL) /*!< MRTVL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCL1 ======================================================= */ + #define R_GPTP_PTPMCRTCL1_MRTVL_Pos (0UL) /*!< MRTVL (Bit 0) */ + #define R_GPTP_PTPMCRTCL1_MRTVL_Msk (0xffffffffUL) /*!< MRTVL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCM0 ======================================================= */ + #define R_GPTP_PTPMCRTCM0_MRTVM_Pos (0UL) /*!< MRTVM (Bit 0) */ + #define R_GPTP_PTPMCRTCM0_MRTVM_Msk (0xffffffffUL) /*!< MRTVM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCM1 ======================================================= */ + #define R_GPTP_PTPMCRTCM1_MRTVM_Pos (0UL) /*!< MRTVM (Bit 0) */ + #define R_GPTP_PTPMCRTCM1_MRTVM_Msk (0xffffffffUL) /*!< MRTVM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTPMCRTCU0 ======================================================= */ + #define R_GPTP_PTPMCRTCU0_MRTVU_Pos (0UL) /*!< MRTVU (Bit 0) */ + #define R_GPTP_PTPMCRTCU0_MRTVU_Msk (0xffffUL) /*!< MRTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCRTCU0_MRTT_Pos (16UL) /*!< MRTT (Bit 16) */ + #define R_GPTP_PTPMCRTCU0_MRTT_Msk (0x30000UL) /*!< MRTT (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPMCRTCU0_MCRN_Pos (18UL) /*!< MCRN (Bit 18) */ + #define R_GPTP_PTPMCRTCU0_MCRN_Msk (0x1c0000UL) /*!< MCRN (Bitfield-Mask: 0x07) */ + #define R_GPTP_PTPMCRTCU0_MRBCR_Pos (31UL) /*!< MRBCR (Bit 31) */ + #define R_GPTP_PTPMCRTCU0_MRBCR_Msk (0x80000000UL) /*!< MRBCR (Bitfield-Mask: 0x01) */ +/* ====================================================== PTPMCRTCU1 ======================================================= */ + #define R_GPTP_PTPMCRTCU1_MRTVU_Pos (0UL) /*!< MRTVU (Bit 0) */ + #define R_GPTP_PTPMCRTCU1_MRTVU_Msk (0xffffUL) /*!< MRTVU (Bitfield-Mask: 0xffff) */ + #define R_GPTP_PTPMCRTCU1_MRTT_Pos (16UL) /*!< MRTT (Bit 16) */ + #define R_GPTP_PTPMCRTCU1_MRTT_Msk (0x30000UL) /*!< MRTT (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPMCRTCU1_MCRN_Pos (18UL) /*!< MCRN (Bit 18) */ + #define R_GPTP_PTPMCRTCU1_MCRN_Msk (0x1c0000UL) /*!< MCRN (Bitfield-Mask: 0x07) */ + #define R_GPTP_PTPMCRTCU1_MRBCR_Pos (31UL) /*!< MRBCR (Bit 31) */ + #define R_GPTP_PTPMCRTCU1_MRBCR_Msk (0x80000000UL) /*!< MRBCR (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCPC0 ======================================================== */ + #define R_GPTP_PTPMCPC0_PE_Pos (0UL) /*!< PE (Bit 0) */ + #define R_GPTP_PTPMCPC0_PE_Msk (0x1UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCPC0_MRS_Pos (1UL) /*!< MRS (Bit 1) */ + #define R_GPTP_PTPMCPC0_MRS_Msk (0x2UL) /*!< MRS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCPC1 ======================================================== */ + #define R_GPTP_PTPMCPC1_PE_Pos (0UL) /*!< PE (Bit 0) */ + #define R_GPTP_PTPMCPC1_PE_Msk (0x1UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPMCPC1_MRS_Pos (1UL) /*!< MRS (Bit 1) */ + #define R_GPTP_PTPMCPC1_MRS_Msk (0x2UL) /*!< MRS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC00 ======================================================== */ + #define R_GPTP_PTPCCC00_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC00_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC00_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC00_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC01 ======================================================== */ + #define R_GPTP_PTPCCC01_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC01_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC01_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC01_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC02 ======================================================== */ + #define R_GPTP_PTPCCC02_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC02_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC02_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC02_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC03 ======================================================== */ + #define R_GPTP_PTPCCC03_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC03_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC03_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC03_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC04 ======================================================== */ + #define R_GPTP_PTPCCC04_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC04_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC04_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC04_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC05 ======================================================== */ + #define R_GPTP_PTPCCC05_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC05_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC05_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC05_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC06 ======================================================== */ + #define R_GPTP_PTPCCC06_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC06_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC06_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC06_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC07 ======================================================== */ + #define R_GPTP_PTPCCC07_CCTNS_Pos (0UL) /*!< CCTNS (Bit 0) */ + #define R_GPTP_PTPCCC07_CCTNS_Msk (0x1UL) /*!< CCTNS (Bitfield-Mask: 0x01) */ + #define R_GPTP_PTPCCC07_CCOPS_Pos (4UL) /*!< CCOPS (Bit 4) */ + #define R_GPTP_PTPCCC07_CCOPS_Msk (0x10UL) /*!< CCOPS (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPCCC10 ======================================================== */ + #define R_GPTP_PTPCCC10_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC10_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC11 ======================================================== */ + #define R_GPTP_PTPCCC11_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC11_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC12 ======================================================== */ + #define R_GPTP_PTPCCC12_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC12_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC13 ======================================================== */ + #define R_GPTP_PTPCCC13_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC13_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC14 ======================================================== */ + #define R_GPTP_PTPCCC14_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC14_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC15 ======================================================== */ + #define R_GPTP_PTPCCC15_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC15_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC16 ======================================================== */ + #define R_GPTP_PTPCCC16_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC16_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PTPCCC17 ======================================================== */ + #define R_GPTP_PTPCCC17_CCV_Pos (0UL) /*!< CCV (Bit 0) */ + #define R_GPTP_PTPCCC17_CCV_Msk (0xffffffffUL) /*!< CCV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PTPIS0 ========================================================= */ + #define R_GPTP_PTPIS0_MCCS_Pos (0UL) /*!< MCCS (Bit 0) */ + #define R_GPTP_PTPIS0_MCCS_Msk (0x3UL) /*!< MCCS (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPIS0_MCCOES_Pos (16UL) /*!< MCCOES (Bit 16) */ + #define R_GPTP_PTPIS0_MCCOES_Msk (0x30000UL) /*!< MCCOES (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIE0 ========================================================= */ + #define R_GPTP_PTPIE0_MCCE_Pos (0UL) /*!< MCCE (Bit 0) */ + #define R_GPTP_PTPIE0_MCCE_Msk (0x3UL) /*!< MCCE (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPIE0_MCCOEE_Pos (16UL) /*!< MCCOEE (Bit 16) */ + #define R_GPTP_PTPIE0_MCCOEE_Msk (0x30000UL) /*!< MCCOEE (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPID0 ========================================================= */ + #define R_GPTP_PTPID0_MCCD_Pos (0UL) /*!< MCCD (Bit 0) */ + #define R_GPTP_PTPID0_MCCD_Msk (0x3UL) /*!< MCCD (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPID0_MCCOED_Pos (16UL) /*!< MCCOED (Bit 16) */ + #define R_GPTP_PTPID0_MCCOED_Msk (0x30000UL) /*!< MCCOED (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIS1 ========================================================= */ + #define R_GPTP_PTPIS1_MCRMS_Pos (0UL) /*!< MCRMS (Bit 0) */ + #define R_GPTP_PTPIS1_MCRMS_Msk (0x3UL) /*!< MCRMS (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPIE1 ========================================================= */ + #define R_GPTP_PTPIE1_MCRME_Pos (0UL) /*!< MCRME (Bit 0) */ + #define R_GPTP_PTPIE1_MCRME_Msk (0x3UL) /*!< MCRME (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPID1 ========================================================= */ + #define R_GPTP_PTPID1_MCRMD_Pos (0UL) /*!< MCRMD (Bit 0) */ + #define R_GPTP_PTPID1_MCRMD_Msk (0x3UL) /*!< MCRMD (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR0 ======================================================== */ + #define R_GPTP_PTPSCR0_TRSL_Pos (0UL) /*!< TRSL (Bit 0) */ + #define R_GPTP_PTPSCR0_TRSL_Msk (0x3UL) /*!< TRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR0_MCRSL_Pos (16UL) /*!< MCRSL (Bit 16) */ + #define R_GPTP_PTPSCR0_MCRSL_Msk (0x30000UL) /*!< MCRSL (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR1 ======================================================== */ + #define R_GPTP_PTPSCR1_MRRSL_Pos (0UL) /*!< MRRSL (Bit 0) */ + #define R_GPTP_PTPSCR1_MRRSL_Msk (0x3UL) /*!< MRRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR1_MRRRSL_Pos (16UL) /*!< MRRRSL (Bit 16) */ + #define R_GPTP_PTPSCR1_MRRRSL_Msk (0x30000UL) /*!< MRRRSL (Bitfield-Mask: 0x03) */ +/* ======================================================== PTPSCR2 ======================================================== */ + #define R_GPTP_PTPSCR2_CCRSL_Pos (0UL) /*!< CCRSL (Bit 0) */ + #define R_GPTP_PTPSCR2_CCRSL_Msk (0x3UL) /*!< CCRSL (Bitfield-Mask: 0x03) */ + #define R_GPTP_PTPSCR2_VRSL_Pos (16UL) /*!< VRSL (Bit 16) */ + #define R_GPTP_PTPSCR2_VRSL_Msk (0x10000UL) /*!< VRSL (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCFGR ======================================================== */ + #define R_GPTP_POTCFGR_REFSEL_Pos (0UL) /*!< REFSEL (Bit 0) */ + #define R_GPTP_POTCFGR_REFSEL_Msk (0x1UL) /*!< REFSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR0 ========================================================= */ + #define R_GPTP_POTCR0_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR1 ========================================================= */ + #define R_GPTP_POTCR1_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR2 ========================================================= */ + #define R_GPTP_POTCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== POTCR3 ========================================================= */ + #define R_GPTP_POTCR3_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_GPTP_POTCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================= POTSTRU0 ======================================================== */ +/* ======================================================= POTSTRU1 ======================================================== */ +/* ======================================================= POTSTRU2 ======================================================== */ +/* ======================================================= POTSTRU3 ======================================================== */ +/* ======================================================= POTSTRM0 ======================================================== */ +/* ======================================================= POTSTRM1 ======================================================== */ +/* ======================================================= POTSTRM2 ======================================================== */ +/* ======================================================= POTSTRM3 ======================================================== */ +/* ======================================================= POTSTRL0 ======================================================== */ +/* ======================================================= POTSTRL1 ======================================================== */ +/* ======================================================= POTSTRL2 ======================================================== */ +/* ======================================================= POTSTRL3 ======================================================== */ +/* ======================================================= POTPERU0 ======================================================== */ +/* ======================================================= POTPERU1 ======================================================== */ +/* ======================================================= POTPERU2 ======================================================== */ +/* ======================================================= POTPERU3 ======================================================== */ +/* ======================================================= POTPERM0 ======================================================== */ +/* ======================================================= POTPERM1 ======================================================== */ +/* ======================================================= POTPERM2 ======================================================== */ +/* ======================================================= POTPERM3 ======================================================== */ +/* ======================================================= POTPERL0 ======================================================== */ +/* ======================================================= POTPERL1 ======================================================== */ +/* ======================================================= POTPERL2 ======================================================== */ +/* ======================================================= POTPERL3 ======================================================== */ +/* ======================================================== POTPWR0 ======================================================== */ +/* ======================================================== POTPWR1 ======================================================== */ +/* ======================================================== POTPWR2 ======================================================== */ +/* ======================================================== POTPWR3 ======================================================== */ +/* ======================================================= POTCPRU0 ======================================================== */ +/* ======================================================= POTCPRU1 ======================================================== */ +/* ======================================================= POTCPRU2 ======================================================== */ +/* ======================================================= POTCPRU3 ======================================================== */ +/* ======================================================= POTCPRM0 ======================================================== */ +/* ======================================================= POTCPRM1 ======================================================== */ +/* ======================================================= POTCPRM2 ======================================================== */ +/* ======================================================= POTCPRM3 ======================================================== */ +/* ======================================================= POTCPRL0 ======================================================== */ +/* ======================================================= POTCPRL1 ======================================================== */ +/* ======================================================= POTCPRL2 ======================================================== */ +/* ======================================================= POTCPRL3 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_GWCA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GWMC ========================================================== */ + #define R_GWCA0_GWMC_OPC_Pos (0UL) /*!< OPC (Bit 0) */ + #define R_GWCA0_GWMC_OPC_Msk (0x3UL) /*!< OPC (Bitfield-Mask: 0x03) */ +/* ========================================================= GWMS ========================================================== */ + #define R_GWCA0_GWMS_OPS_Pos (0UL) /*!< OPS (Bit 0) */ + #define R_GWCA0_GWMS_OPS_Msk (0x3UL) /*!< OPS (Bitfield-Mask: 0x03) */ +/* ========================================================= GWIRC ========================================================= */ + #define R_GWCA0_GWIRC_IPVR0_Pos (0UL) /*!< IPVR0 (Bit 0) */ + #define R_GWCA0_GWIRC_IPVR0_Msk (0x7UL) /*!< IPVR0 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR1_Pos (4UL) /*!< IPVR1 (Bit 4) */ + #define R_GWCA0_GWIRC_IPVR1_Msk (0x70UL) /*!< IPVR1 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR2_Pos (8UL) /*!< IPVR2 (Bit 8) */ + #define R_GWCA0_GWIRC_IPVR2_Msk (0x700UL) /*!< IPVR2 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR3_Pos (12UL) /*!< IPVR3 (Bit 12) */ + #define R_GWCA0_GWIRC_IPVR3_Msk (0x7000UL) /*!< IPVR3 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR4_Pos (16UL) /*!< IPVR4 (Bit 16) */ + #define R_GWCA0_GWIRC_IPVR4_Msk (0x70000UL) /*!< IPVR4 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR5_Pos (20UL) /*!< IPVR5 (Bit 20) */ + #define R_GWCA0_GWIRC_IPVR5_Msk (0x700000UL) /*!< IPVR5 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR6_Pos (24UL) /*!< IPVR6 (Bit 24) */ + #define R_GWCA0_GWIRC_IPVR6_Msk (0x7000000UL) /*!< IPVR6 (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWIRC_IPVR7_Pos (28UL) /*!< IPVR7 (Bit 28) */ + #define R_GWCA0_GWIRC_IPVR7_Msk (0x70000000UL) /*!< IPVR7 (Bitfield-Mask: 0x07) */ +/* ======================================================== GWRDQSC ======================================================== */ + #define R_GWCA0_GWRDQSC_RDQSL0_Pos (0UL) /*!< RDQSL0 (Bit 0) */ + #define R_GWCA0_GWRDQSC_RDQSL0_Msk (0x1UL) /*!< RDQSL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL1_Pos (1UL) /*!< RDQSL1 (Bit 1) */ + #define R_GWCA0_GWRDQSC_RDQSL1_Msk (0x2UL) /*!< RDQSL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL2_Pos (2UL) /*!< RDQSL2 (Bit 2) */ + #define R_GWCA0_GWRDQSC_RDQSL2_Msk (0x4UL) /*!< RDQSL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL3_Pos (3UL) /*!< RDQSL3 (Bit 3) */ + #define R_GWCA0_GWRDQSC_RDQSL3_Msk (0x8UL) /*!< RDQSL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL4_Pos (4UL) /*!< RDQSL4 (Bit 4) */ + #define R_GWCA0_GWRDQSC_RDQSL4_Msk (0x10UL) /*!< RDQSL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL5_Pos (5UL) /*!< RDQSL5 (Bit 5) */ + #define R_GWCA0_GWRDQSC_RDQSL5_Msk (0x20UL) /*!< RDQSL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL6_Pos (6UL) /*!< RDQSL6 (Bit 6) */ + #define R_GWCA0_GWRDQSC_RDQSL6_Msk (0x40UL) /*!< RDQSL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQSC_RDQSL7_Pos (7UL) /*!< RDQSL7 (Bit 7) */ + #define R_GWCA0_GWRDQSC_RDQSL7_Msk (0x80UL) /*!< RDQSL7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWRDQC ========================================================= */ + #define R_GWCA0_GWRDQC_RDQD0_Pos (0UL) /*!< RDQD0 (Bit 0) */ + #define R_GWCA0_GWRDQC_RDQD0_Msk (0x1UL) /*!< RDQD0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD1_Pos (1UL) /*!< RDQD1 (Bit 1) */ + #define R_GWCA0_GWRDQC_RDQD1_Msk (0x2UL) /*!< RDQD1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD2_Pos (2UL) /*!< RDQD2 (Bit 2) */ + #define R_GWCA0_GWRDQC_RDQD2_Msk (0x4UL) /*!< RDQD2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD3_Pos (3UL) /*!< RDQD3 (Bit 3) */ + #define R_GWCA0_GWRDQC_RDQD3_Msk (0x8UL) /*!< RDQD3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD4_Pos (4UL) /*!< RDQD4 (Bit 4) */ + #define R_GWCA0_GWRDQC_RDQD4_Msk (0x10UL) /*!< RDQD4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD5_Pos (5UL) /*!< RDQD5 (Bit 5) */ + #define R_GWCA0_GWRDQC_RDQD5_Msk (0x20UL) /*!< RDQD5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD6_Pos (6UL) /*!< RDQD6 (Bit 6) */ + #define R_GWCA0_GWRDQC_RDQD6_Msk (0x40UL) /*!< RDQD6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQD7_Pos (7UL) /*!< RDQD7 (Bit 7) */ + #define R_GWCA0_GWRDQC_RDQD7_Msk (0x80UL) /*!< RDQD7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP0_Pos (16UL) /*!< RDQP0 (Bit 16) */ + #define R_GWCA0_GWRDQC_RDQP0_Msk (0x10000UL) /*!< RDQP0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP1_Pos (17UL) /*!< RDQP1 (Bit 17) */ + #define R_GWCA0_GWRDQC_RDQP1_Msk (0x20000UL) /*!< RDQP1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP2_Pos (18UL) /*!< RDQP2 (Bit 18) */ + #define R_GWCA0_GWRDQC_RDQP2_Msk (0x40000UL) /*!< RDQP2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP3_Pos (19UL) /*!< RDQP3 (Bit 19) */ + #define R_GWCA0_GWRDQC_RDQP3_Msk (0x80000UL) /*!< RDQP3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP4_Pos (20UL) /*!< RDQP4 (Bit 20) */ + #define R_GWCA0_GWRDQC_RDQP4_Msk (0x100000UL) /*!< RDQP4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP5_Pos (21UL) /*!< RDQP5 (Bit 21) */ + #define R_GWCA0_GWRDQC_RDQP5_Msk (0x200000UL) /*!< RDQP5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP6_Pos (22UL) /*!< RDQP6 (Bit 22) */ + #define R_GWCA0_GWRDQC_RDQP6_Msk (0x400000UL) /*!< RDQP6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWRDQC_RDQP7_Pos (23UL) /*!< RDQP7 (Bit 23) */ + #define R_GWCA0_GWRDQC_RDQP7_Msk (0x800000UL) /*!< RDQP7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWRDQAC ======================================================== */ + #define R_GWCA0_GWRDQAC_RDQA0_Pos (0UL) /*!< RDQA0 (Bit 0) */ + #define R_GWCA0_GWRDQAC_RDQA0_Msk (0xfUL) /*!< RDQA0 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA1_Pos (4UL) /*!< RDQA1 (Bit 4) */ + #define R_GWCA0_GWRDQAC_RDQA1_Msk (0xf0UL) /*!< RDQA1 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA2_Pos (8UL) /*!< RDQA2 (Bit 8) */ + #define R_GWCA0_GWRDQAC_RDQA2_Msk (0xf00UL) /*!< RDQA2 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA3_Pos (12UL) /*!< RDQA3 (Bit 12) */ + #define R_GWCA0_GWRDQAC_RDQA3_Msk (0xf000UL) /*!< RDQA3 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA4_Pos (16UL) /*!< RDQA4 (Bit 16) */ + #define R_GWCA0_GWRDQAC_RDQA4_Msk (0xf0000UL) /*!< RDQA4 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA5_Pos (20UL) /*!< RDQA5 (Bit 20) */ + #define R_GWCA0_GWRDQAC_RDQA5_Msk (0xf00000UL) /*!< RDQA5 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA6_Pos (24UL) /*!< RDQA6 (Bit 24) */ + #define R_GWCA0_GWRDQAC_RDQA6_Msk (0xf000000UL) /*!< RDQA6 (Bitfield-Mask: 0x0f) */ + #define R_GWCA0_GWRDQAC_RDQA7_Pos (28UL) /*!< RDQA7 (Bit 28) */ + #define R_GWCA0_GWRDQAC_RDQA7_Msk (0xf0000000UL) /*!< RDQA7 (Bitfield-Mask: 0x0f) */ +/* ========================================================= GWRGC ========================================================= */ + #define R_GWCA0_GWRGC_RCPT_Pos (0UL) /*!< RCPT (Bit 0) */ + #define R_GWCA0_GWRGC_RCPT_Msk (0x1UL) /*!< RCPT (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRMFSC0 ======================================================== */ + #define R_GWCA0_GWRMFSC0_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC0_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC1 ======================================================== */ + #define R_GWCA0_GWRMFSC1_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC1_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC2 ======================================================== */ + #define R_GWCA0_GWRMFSC2_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC2_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC3 ======================================================== */ + #define R_GWCA0_GWRMFSC3_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC3_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC4 ======================================================== */ + #define R_GWCA0_GWRMFSC4_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC4_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC5 ======================================================== */ + #define R_GWCA0_GWRMFSC5_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC5_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC6 ======================================================== */ + #define R_GWCA0_GWRMFSC6_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC6_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRMFSC7 ======================================================== */ + #define R_GWCA0_GWRMFSC7_MFS_Pos (0UL) /*!< MFS (Bit 0) */ + #define R_GWCA0_GWRMFSC7_MFS_Msk (0xffffUL) /*!< MFS (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRDQDC0 ======================================================== */ + #define R_GWCA0_GWRDQDC0_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC0_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC1 ======================================================== */ + #define R_GWCA0_GWRDQDC1_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC1_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC2 ======================================================== */ + #define R_GWCA0_GWRDQDC2_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC2_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC3 ======================================================== */ + #define R_GWCA0_GWRDQDC3_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC3_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC4 ======================================================== */ + #define R_GWCA0_GWRDQDC4_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC4_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC5 ======================================================== */ + #define R_GWCA0_GWRDQDC5_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC5_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC6 ======================================================== */ + #define R_GWCA0_GWRDQDC6_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC6_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQDC7 ======================================================== */ + #define R_GWCA0_GWRDQDC7_DQD_Pos (0UL) /*!< DQD (Bit 0) */ + #define R_GWCA0_GWRDQDC7_DQD_Msk (0x7ffUL) /*!< DQD (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM0 ======================================================== */ + #define R_GWCA0_GWRDQM0_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM0_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM1 ======================================================== */ + #define R_GWCA0_GWRDQM1_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM1_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM2 ======================================================== */ + #define R_GWCA0_GWRDQM2_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM2_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM3 ======================================================== */ + #define R_GWCA0_GWRDQM3_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM3_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM4 ======================================================== */ + #define R_GWCA0_GWRDQM4_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM4_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM5 ======================================================== */ + #define R_GWCA0_GWRDQM5_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM5_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM6 ======================================================== */ + #define R_GWCA0_GWRDQM6_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM6_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWRDQM7 ======================================================== */ + #define R_GWCA0_GWRDQM7_DNQ_Pos (0UL) /*!< DNQ (Bit 0) */ + #define R_GWCA0_GWRDQM7_DNQ_Msk (0x7ffUL) /*!< DNQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM0 ======================================================= */ + #define R_GWCA0_GWRDQMLM0_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM0_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM1 ======================================================= */ + #define R_GWCA0_GWRDQMLM1_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM1_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM2 ======================================================= */ + #define R_GWCA0_GWRDQMLM2_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM2_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM3 ======================================================= */ + #define R_GWCA0_GWRDQMLM3_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM3_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM4 ======================================================= */ + #define R_GWCA0_GWRDQMLM4_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM4_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM5 ======================================================= */ + #define R_GWCA0_GWRDQMLM5_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM5_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM6 ======================================================= */ + #define R_GWCA0_GWRDQMLM6_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM6_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================= GWRDQMLM7 ======================================================= */ + #define R_GWCA0_GWRDQMLM7_DMLQ_Pos (0UL) /*!< DMLQ (Bit 0) */ + #define R_GWCA0_GWRDQMLM7_DMLQ_Msk (0x7ffUL) /*!< DMLQ (Bitfield-Mask: 0x7ff) */ +/* ======================================================== GWMTIRM ======================================================== */ + #define R_GWCA0_GWMTIRM_MTIOG_Pos (0UL) /*!< MTIOG (Bit 0) */ + #define R_GWCA0_GWMTIRM_MTIOG_Msk (0x1UL) /*!< MTIOG (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMTIRM_MTR_Pos (1UL) /*!< MTR (Bit 1) */ + #define R_GWCA0_GWMTIRM_MTR_Msk (0x2UL) /*!< MTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMSTLS ======================================================== */ + #define R_GWCA0_GWMSTLS_MNRCNL_Pos (0UL) /*!< MNRCNL (Bit 0) */ + #define R_GWCA0_GWMSTLS_MNRCNL_Msk (0x7fUL) /*!< MNRCNL (Bitfield-Mask: 0x7f) */ + #define R_GWCA0_GWMSTLS_MNL_Pos (8UL) /*!< MNL (Bit 8) */ + #define R_GWCA0_GWMSTLS_MNL_Msk (0x700UL) /*!< MNL (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWMSTLS_MSENL_Pos (16UL) /*!< MSENL (Bit 16) */ + #define R_GWCA0_GWMSTLS_MSENL_Msk (0x7f0000UL) /*!< MSENL (Bitfield-Mask: 0x7f) */ +/* ======================================================== GWMSTLR ======================================================== */ + #define R_GWCA0_GWMSTLR_MTLF_Pos (0UL) /*!< MTLF (Bit 0) */ + #define R_GWCA0_GWMSTLR_MTLF_Msk (0x1UL) /*!< MTLF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMSTLR_MTL_Pos (31UL) /*!< MTL (Bit 31) */ + #define R_GWCA0_GWMSTLR_MTL_Msk (0x80000000UL) /*!< MTL (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMSTSS ======================================================== */ + #define R_GWCA0_GWMSTSS_MSENS_Pos (0UL) /*!< MSENS (Bit 0) */ + #define R_GWCA0_GWMSTSS_MSENS_Msk (0x7fUL) /*!< MSENS (Bitfield-Mask: 0x7f) */ +/* ======================================================== GWMSTSR ======================================================== */ + #define R_GWCA0_GWMSTSR_MNRCNR_Pos (0UL) /*!< MNRCNR (Bit 0) */ + #define R_GWCA0_GWMSTSR_MNRCNR_Msk (0x7fUL) /*!< MNRCNR (Bitfield-Mask: 0x7f) */ + #define R_GWCA0_GWMSTSR_MNR_Pos (8UL) /*!< MNR (Bit 8) */ + #define R_GWCA0_GWMSTSR_MNR_Msk (0x700UL) /*!< MNR (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWMSTSR_MTSEF_Pos (16UL) /*!< MTSEF (Bit 16) */ + #define R_GWCA0_GWMSTSR_MTSEF_Msk (0x10000UL) /*!< MTSEF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWMSTSR_MTS_Pos (31UL) /*!< MTS (Bit 31) */ + #define R_GWCA0_GWMSTSR_MTS_Msk (0x80000000UL) /*!< MTS (Bitfield-Mask: 0x01) */ +/* ======================================================== GWMAC0 ========================================================= */ + #define R_GWCA0_GWMAC0_MAUP_Pos (0UL) /*!< MAUP (Bit 0) */ + #define R_GWCA0_GWMAC0_MAUP_Msk (0xffffUL) /*!< MAUP (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWMAC1 ========================================================= */ + #define R_GWCA0_GWMAC1_MADP_Pos (0UL) /*!< MADP (Bit 0) */ + #define R_GWCA0_GWMAC1_MADP_Msk (0xffffffffUL) /*!< MADP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GWVCC ========================================================= */ + #define R_GWCA0_GWVCC_VIM_Pos (0UL) /*!< VIM (Bit 0) */ + #define R_GWCA0_GWVCC_VIM_Msk (0x1UL) /*!< VIM (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVCC_CTVUM_Pos (8UL) /*!< CTVUM (Bit 8) */ + #define R_GWCA0_GWVCC_CTVUM_Msk (0x100UL) /*!< CTVUM (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVCC_VEM_Pos (16UL) /*!< VEM (Bit 16) */ + #define R_GWCA0_GWVCC_VEM_Msk (0x70000UL) /*!< VEM (Bitfield-Mask: 0x07) */ +/* ========================================================= GWVTC ========================================================= */ + #define R_GWCA0_GWVTC_CTV_Pos (0UL) /*!< CTV (Bit 0) */ + #define R_GWCA0_GWVTC_CTV_Msk (0xfffUL) /*!< CTV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWVTC_CTP_Pos (12UL) /*!< CTP (Bit 12) */ + #define R_GWCA0_GWVTC_CTP_Msk (0x7000UL) /*!< CTP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWVTC_CTD_Pos (15UL) /*!< CTD (Bit 15) */ + #define R_GWCA0_GWVTC_CTD_Msk (0x8000UL) /*!< CTD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWVTC_STV_Pos (16UL) /*!< STV (Bit 16) */ + #define R_GWCA0_GWVTC_STV_Msk (0xfff0000UL) /*!< STV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWVTC_STP_Pos (28UL) /*!< STP (Bit 28) */ + #define R_GWCA0_GWVTC_STP_Msk (0x70000000UL) /*!< STP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWVTC_STD_Pos (31UL) /*!< STD (Bit 31) */ + #define R_GWCA0_GWVTC_STD_Msk (0x80000000UL) /*!< STD (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTTFC ========================================================= */ + #define R_GWCA0_GWTTFC_NT_Pos (0UL) /*!< NT (Bit 0) */ + #define R_GWCA0_GWTTFC_NT_Msk (0x1UL) /*!< NT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_RT_Pos (1UL) /*!< RT (Bit 1) */ + #define R_GWCA0_GWTTFC_RT_Msk (0x2UL) /*!< RT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CST_Pos (2UL) /*!< CST (Bit 2) */ + #define R_GWCA0_GWTTFC_CST_Msk (0x4UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CSRT_Pos (3UL) /*!< CSRT (Bit 3) */ + #define R_GWCA0_GWTTFC_CSRT_Msk (0x8UL) /*!< CSRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CT_Pos (4UL) /*!< CT (Bit 4) */ + #define R_GWCA0_GWTTFC_CT_Msk (0x10UL) /*!< CT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_CRT_Pos (5UL) /*!< CRT (Bit 5) */ + #define R_GWCA0_GWTTFC_CRT_Msk (0x20UL) /*!< CRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_SCT_Pos (6UL) /*!< SCT (Bit 6) */ + #define R_GWCA0_GWTTFC_SCT_Msk (0x40UL) /*!< SCT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_SCRT_Pos (7UL) /*!< SCRT (Bit 7) */ + #define R_GWCA0_GWTTFC_SCRT_Msk (0x80UL) /*!< SCRT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTTFC_UT_Pos (8UL) /*!< UT (Bit 8) */ + #define R_GWCA0_GWTTFC_UT_Msk (0x100UL) /*!< UT (Bitfield-Mask: 0x01) */ +/* ======================================================= GWTDCAC00 ======================================================= */ + #define R_GWCA0_GWTDCAC00_TSCCAUP_Pos (0UL) /*!< TSCCAUP (Bit 0) */ + #define R_GWCA0_GWTDCAC00_TSCCAUP_Msk (0xffUL) /*!< TSCCAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWTDCAC10 ======================================================= */ + #define R_GWCA0_GWTDCAC10_TSCCADP_Pos (0UL) /*!< TSCCADP (Bit 0) */ + #define R_GWCA0_GWTDCAC10_TSCCADP_Msk (0xffffffffUL) /*!< TSCCADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWTDCAC01 ======================================================= */ + #define R_GWCA0_GWTDCAC01_TSCCAUP_Pos (0UL) /*!< TSCCAUP (Bit 0) */ + #define R_GWCA0_GWTDCAC01_TSCCAUP_Msk (0xffUL) /*!< TSCCAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWTDCAC11 ======================================================= */ + #define R_GWCA0_GWTDCAC11_TSCCADP_Pos (0UL) /*!< TSCCADP (Bit 0) */ + #define R_GWCA0_GWTDCAC11_TSCCADP_Msk (0xffffffffUL) /*!< TSCCADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWTSDCC0 ======================================================== */ + #define R_GWCA0_GWTSDCC0_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GWCA0_GWTSDCC0_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDCC0_DCS_Pos (1UL) /*!< DCS (Bit 1) */ + #define R_GWCA0_GWTSDCC0_DCS_Msk (0x6UL) /*!< DCS (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWTSDCC0_OSID_Pos (8UL) /*!< OSID (Bit 8) */ + #define R_GWCA0_GWTSDCC0_OSID_Msk (0x700UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================= GWTSDCC1 ======================================================== */ + #define R_GWCA0_GWTSDCC1_TE_Pos (0UL) /*!< TE (Bit 0) */ + #define R_GWCA0_GWTSDCC1_TE_Msk (0x1UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDCC1_DCS_Pos (1UL) /*!< DCS (Bit 1) */ + #define R_GWCA0_GWTSDCC1_DCS_Msk (0x6UL) /*!< DCS (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWTSDCC1_OSID_Pos (8UL) /*!< OSID (Bit 8) */ + #define R_GWCA0_GWTSDCC1_OSID_Msk (0x700UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWTSNM ========================================================= */ + #define R_GWCA0_GWTSNM_TNTR_Pos (0UL) /*!< TNTR (Bit 0) */ + #define R_GWCA0_GWTSNM_TNTR_Msk (0xffUL) /*!< TNTR (Bitfield-Mask: 0xff) */ +/* ======================================================== GWTSMNM ======================================================== */ + #define R_GWCA0_GWTSMNM_TMNTR_Pos (0UL) /*!< TMNTR (Bit 0) */ + #define R_GWCA0_GWTSMNM_TMNTR_Msk (0xffUL) /*!< TMNTR (Bitfield-Mask: 0xff) */ +/* ========================================================= GWAC ========================================================== */ + #define R_GWCA0_GWAC_AMPR_Pos (0UL) /*!< AMPR (Bit 0) */ + #define R_GWCA0_GWAC_AMPR_Msk (0x1UL) /*!< AMPR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAC_AMP_Pos (1UL) /*!< AMP (Bit 1) */ + #define R_GWCA0_GWAC_AMP_Msk (0x2UL) /*!< AMP (Bitfield-Mask: 0x01) */ +/* ======================================================= GWDCBAC0 ======================================================== */ + #define R_GWCA0_GWDCBAC0_DCBAUP_Pos (0UL) /*!< DCBAUP (Bit 0) */ + #define R_GWCA0_GWDCBAC0_DCBAUP_Msk (0xffUL) /*!< DCBAUP (Bitfield-Mask: 0xff) */ +/* ======================================================= GWDCBAC1 ======================================================== */ + #define R_GWCA0_GWDCBAC1_DCBADP_Pos (0UL) /*!< DCBADP (Bit 0) */ + #define R_GWCA0_GWDCBAC1_DCBADP_Msk (0xffffffffUL) /*!< DCBADP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWMDNC ========================================================= */ + #define R_GWCA0_GWMDNC_RXDMN_Pos (0UL) /*!< RXDMN (Bit 0) */ + #define R_GWCA0_GWMDNC_RXDMN_Msk (0x1fUL) /*!< RXDMN (Bitfield-Mask: 0x1f) */ + #define R_GWCA0_GWMDNC_TXDMN_Pos (8UL) /*!< TXDMN (Bit 8) */ + #define R_GWCA0_GWMDNC_TXDMN_Msk (0x1f00UL) /*!< TXDMN (Bitfield-Mask: 0x1f) */ + #define R_GWCA0_GWMDNC_TSDMN_Pos (16UL) /*!< TSDMN (Bit 16) */ + #define R_GWCA0_GWMDNC_TSDMN_Msk (0x30000UL) /*!< TSDMN (Bitfield-Mask: 0x03) */ +/* ======================================================== GWTRC0 ========================================================= */ +/* ======================================================== GWTRC1 ========================================================= */ +/* ======================================================== GWTPC0 ========================================================= */ + #define R_GWCA0_GWTPC0_PPPL0_Pos (0UL) /*!< PPPL0 (Bit 0) */ + #define R_GWCA0_GWTPC0_PPPL0_Msk (0x1UL) /*!< PPPL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL1_Pos (1UL) /*!< PPPL1 (Bit 1) */ + #define R_GWCA0_GWTPC0_PPPL1_Msk (0x2UL) /*!< PPPL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL2_Pos (2UL) /*!< PPPL2 (Bit 2) */ + #define R_GWCA0_GWTPC0_PPPL2_Msk (0x4UL) /*!< PPPL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL3_Pos (3UL) /*!< PPPL3 (Bit 3) */ + #define R_GWCA0_GWTPC0_PPPL3_Msk (0x8UL) /*!< PPPL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL4_Pos (4UL) /*!< PPPL4 (Bit 4) */ + #define R_GWCA0_GWTPC0_PPPL4_Msk (0x10UL) /*!< PPPL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL5_Pos (5UL) /*!< PPPL5 (Bit 5) */ + #define R_GWCA0_GWTPC0_PPPL5_Msk (0x20UL) /*!< PPPL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL6_Pos (6UL) /*!< PPPL6 (Bit 6) */ + #define R_GWCA0_GWTPC0_PPPL6_Msk (0x40UL) /*!< PPPL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL7_Pos (7UL) /*!< PPPL7 (Bit 7) */ + #define R_GWCA0_GWTPC0_PPPL7_Msk (0x80UL) /*!< PPPL7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC0_PPPL8_Pos (8UL) /*!< PPPL8 (Bit 8) */ + #define R_GWCA0_GWTPC0_PPPL8_Msk (0x100UL) /*!< PPPL8 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTPC1 ========================================================= */ + #define R_GWCA0_GWTPC1_PPPL0_Pos (0UL) /*!< PPPL0 (Bit 0) */ + #define R_GWCA0_GWTPC1_PPPL0_Msk (0x1UL) /*!< PPPL0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL1_Pos (1UL) /*!< PPPL1 (Bit 1) */ + #define R_GWCA0_GWTPC1_PPPL1_Msk (0x2UL) /*!< PPPL1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL2_Pos (2UL) /*!< PPPL2 (Bit 2) */ + #define R_GWCA0_GWTPC1_PPPL2_Msk (0x4UL) /*!< PPPL2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL3_Pos (3UL) /*!< PPPL3 (Bit 3) */ + #define R_GWCA0_GWTPC1_PPPL3_Msk (0x8UL) /*!< PPPL3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL4_Pos (4UL) /*!< PPPL4 (Bit 4) */ + #define R_GWCA0_GWTPC1_PPPL4_Msk (0x10UL) /*!< PPPL4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL5_Pos (5UL) /*!< PPPL5 (Bit 5) */ + #define R_GWCA0_GWTPC1_PPPL5_Msk (0x20UL) /*!< PPPL5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL6_Pos (6UL) /*!< PPPL6 (Bit 6) */ + #define R_GWCA0_GWTPC1_PPPL6_Msk (0x40UL) /*!< PPPL6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL7_Pos (7UL) /*!< PPPL7 (Bit 7) */ + #define R_GWCA0_GWTPC1_PPPL7_Msk (0x80UL) /*!< PPPL7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTPC1_PPPL8_Pos (8UL) /*!< PPPL8 (Bit 8) */ + #define R_GWCA0_GWTPC1_PPPL8_Msk (0x100UL) /*!< PPPL8 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWARIRM ======================================================== */ + #define R_GWCA0_GWARIRM_ARIOG_Pos (0UL) /*!< ARIOG (Bit 0) */ + #define R_GWCA0_GWARIRM_ARIOG_Msk (0x1UL) /*!< ARIOG (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWARIRM_ARR_Pos (1UL) /*!< ARR (Bit 1) */ + #define R_GWCA0_GWARIRM_ARR_Msk (0x2UL) /*!< ARR (Bitfield-Mask: 0x01) */ +/* ======================================================== GWDCC0 ========================================================= */ + #define R_GWCA0_GWDCC0_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC0_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC0_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC0_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC0_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC0_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC0_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC0_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC0_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC0_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC0_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC0_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC1 ========================================================= */ + #define R_GWCA0_GWDCC1_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC1_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC1_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC1_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC1_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC1_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC1_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC1_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC1_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC1_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC1_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC1_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC2 ========================================================= */ + #define R_GWCA0_GWDCC2_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC2_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC2_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC2_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC2_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC2_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC2_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC2_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC2_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC2_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC2_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC2_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC3 ========================================================= */ + #define R_GWCA0_GWDCC3_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC3_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC3_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC3_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC3_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC3_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC3_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC3_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC3_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC3_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC3_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC3_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC4 ========================================================= */ + #define R_GWCA0_GWDCC4_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC4_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC4_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC4_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC4_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC4_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC4_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC4_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC4_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC4_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC4_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC4_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC5 ========================================================= */ + #define R_GWCA0_GWDCC5_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC5_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC5_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC5_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC5_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC5_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC5_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC5_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC5_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC5_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC5_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC5_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC6 ========================================================= */ + #define R_GWCA0_GWDCC6_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC6_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC6_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC6_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC6_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC6_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC6_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC6_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC6_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC6_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC6_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC6_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC7 ========================================================= */ + #define R_GWCA0_GWDCC7_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC7_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC7_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC7_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC7_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC7_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC7_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC7_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC7_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC7_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC7_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC7_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC8 ========================================================= */ + #define R_GWCA0_GWDCC8_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC8_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC8_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC8_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC8_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC8_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC8_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC8_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC8_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC8_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC8_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC8_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC9 ========================================================= */ + #define R_GWCA0_GWDCC9_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC9_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC9_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC9_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC9_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC9_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC9_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC9_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC9_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC9_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC9_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC9_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC10 ======================================================== */ + #define R_GWCA0_GWDCC10_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC10_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC10_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC10_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC10_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC10_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC10_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC10_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC10_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC10_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC10_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC10_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC11 ======================================================== */ + #define R_GWCA0_GWDCC11_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC11_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC11_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC11_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC11_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC11_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC11_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC11_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC11_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC11_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC11_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC11_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC12 ======================================================== */ + #define R_GWCA0_GWDCC12_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC12_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC12_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC12_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC12_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC12_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC12_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC12_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC12_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC12_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC12_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC12_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC13 ======================================================== */ + #define R_GWCA0_GWDCC13_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC13_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC13_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC13_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC13_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC13_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC13_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC13_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC13_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC13_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC13_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC13_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC14 ======================================================== */ + #define R_GWCA0_GWDCC14_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC14_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC14_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC14_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC14_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC14_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC14_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC14_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC14_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC14_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC14_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC14_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC15 ======================================================== */ + #define R_GWCA0_GWDCC15_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC15_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC15_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC15_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC15_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC15_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC15_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC15_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC15_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC15_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC15_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC15_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC16 ======================================================== */ + #define R_GWCA0_GWDCC16_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC16_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC16_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC16_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC16_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC16_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC16_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC16_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC16_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC16_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC16_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC16_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC17 ======================================================== */ + #define R_GWCA0_GWDCC17_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC17_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC17_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC17_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC17_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC17_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC17_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC17_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC17_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC17_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC17_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC17_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC18 ======================================================== */ + #define R_GWCA0_GWDCC18_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC18_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC18_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC18_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC18_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC18_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC18_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC18_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC18_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC18_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC18_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC18_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC19 ======================================================== */ + #define R_GWCA0_GWDCC19_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC19_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC19_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC19_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC19_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC19_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC19_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC19_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC19_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC19_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC19_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC19_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC20 ======================================================== */ + #define R_GWCA0_GWDCC20_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC20_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC20_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC20_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC20_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC20_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC20_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC20_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC20_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC20_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC20_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC20_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC21 ======================================================== */ + #define R_GWCA0_GWDCC21_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC21_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC21_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC21_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC21_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC21_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC21_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC21_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC21_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC21_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC21_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC21_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC22 ======================================================== */ + #define R_GWCA0_GWDCC22_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC22_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC22_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC22_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC22_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC22_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC22_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC22_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC22_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC22_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC22_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC22_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC23 ======================================================== */ + #define R_GWCA0_GWDCC23_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC23_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC23_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC23_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC23_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC23_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC23_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC23_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC23_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC23_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC23_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC23_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC24 ======================================================== */ + #define R_GWCA0_GWDCC24_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC24_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC24_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC24_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC24_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC24_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC24_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC24_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC24_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC24_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC24_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC24_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC25 ======================================================== */ + #define R_GWCA0_GWDCC25_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC25_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC25_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC25_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC25_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC25_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC25_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC25_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC25_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC25_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC25_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC25_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC26 ======================================================== */ + #define R_GWCA0_GWDCC26_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC26_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC26_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC26_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC26_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC26_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC26_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC26_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC26_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC26_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC26_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC26_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC27 ======================================================== */ + #define R_GWCA0_GWDCC27_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC27_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC27_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC27_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC27_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC27_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC27_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC27_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC27_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC27_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC27_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC27_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC28 ======================================================== */ + #define R_GWCA0_GWDCC28_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC28_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC28_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC28_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC28_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC28_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC28_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC28_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC28_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC28_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC28_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC28_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC29 ======================================================== */ + #define R_GWCA0_GWDCC29_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC29_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC29_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC29_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC29_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC29_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC29_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC29_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC29_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC29_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC29_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC29_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC30 ======================================================== */ + #define R_GWCA0_GWDCC30_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC30_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC30_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC30_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC30_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC30_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC30_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC30_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC30_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC30_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC30_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC30_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC31 ======================================================== */ + #define R_GWCA0_GWDCC31_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC31_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC31_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC31_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC31_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC31_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC31_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC31_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC31_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC31_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC31_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC31_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC32 ======================================================== */ + #define R_GWCA0_GWDCC32_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC32_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC32_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC32_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC32_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC32_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC32_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC32_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC32_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC32_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC32_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC32_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC33 ======================================================== */ + #define R_GWCA0_GWDCC33_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC33_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC33_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC33_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC33_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC33_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC33_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC33_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC33_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC33_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC33_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC33_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC34 ======================================================== */ + #define R_GWCA0_GWDCC34_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC34_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC34_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC34_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC34_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC34_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC34_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC34_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC34_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC34_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC34_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC34_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC35 ======================================================== */ + #define R_GWCA0_GWDCC35_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC35_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC35_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC35_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC35_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC35_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC35_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC35_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC35_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC35_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC35_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC35_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC36 ======================================================== */ + #define R_GWCA0_GWDCC36_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC36_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC36_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC36_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC36_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC36_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC36_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC36_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC36_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC36_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC36_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC36_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC37 ======================================================== */ + #define R_GWCA0_GWDCC37_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC37_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC37_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC37_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC37_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC37_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC37_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC37_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC37_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC37_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC37_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC37_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC38 ======================================================== */ + #define R_GWCA0_GWDCC38_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC38_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC38_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC38_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC38_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC38_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC38_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC38_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC38_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC38_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC38_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC38_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC39 ======================================================== */ + #define R_GWCA0_GWDCC39_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC39_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC39_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC39_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC39_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC39_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC39_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC39_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC39_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC39_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC39_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC39_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC40 ======================================================== */ + #define R_GWCA0_GWDCC40_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC40_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC40_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC40_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC40_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC40_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC40_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC40_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC40_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC40_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC40_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC40_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC41 ======================================================== */ + #define R_GWCA0_GWDCC41_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC41_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC41_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC41_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC41_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC41_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC41_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC41_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC41_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC41_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC41_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC41_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC42 ======================================================== */ + #define R_GWCA0_GWDCC42_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC42_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC42_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC42_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC42_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC42_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC42_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC42_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC42_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC42_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC42_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC42_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC43 ======================================================== */ + #define R_GWCA0_GWDCC43_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC43_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC43_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC43_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC43_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC43_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC43_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC43_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC43_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC43_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC43_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC43_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC44 ======================================================== */ + #define R_GWCA0_GWDCC44_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC44_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC44_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC44_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC44_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC44_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC44_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC44_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC44_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC44_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC44_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC44_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC45 ======================================================== */ + #define R_GWCA0_GWDCC45_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC45_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC45_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC45_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC45_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC45_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC45_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC45_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC45_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC45_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC45_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC45_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC46 ======================================================== */ + #define R_GWCA0_GWDCC46_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC46_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC46_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC46_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC46_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC46_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC46_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC46_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC46_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC46_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC46_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC46_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC47 ======================================================== */ + #define R_GWCA0_GWDCC47_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC47_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC47_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC47_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC47_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC47_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC47_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC47_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC47_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC47_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC47_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC47_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC48 ======================================================== */ + #define R_GWCA0_GWDCC48_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC48_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC48_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC48_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC48_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC48_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC48_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC48_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC48_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC48_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC48_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC48_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC49 ======================================================== */ + #define R_GWCA0_GWDCC49_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC49_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC49_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC49_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC49_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC49_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC49_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC49_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC49_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC49_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC49_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC49_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC50 ======================================================== */ + #define R_GWCA0_GWDCC50_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC50_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC50_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC50_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC50_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC50_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC50_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC50_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC50_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC50_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC50_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC50_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC51 ======================================================== */ + #define R_GWCA0_GWDCC51_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC51_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC51_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC51_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC51_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC51_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC51_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC51_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC51_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC51_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC51_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC51_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC52 ======================================================== */ + #define R_GWCA0_GWDCC52_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC52_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC52_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC52_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC52_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC52_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC52_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC52_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC52_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC52_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC52_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC52_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC53 ======================================================== */ + #define R_GWCA0_GWDCC53_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC53_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC53_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC53_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC53_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC53_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC53_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC53_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC53_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC53_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC53_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC53_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC54 ======================================================== */ + #define R_GWCA0_GWDCC54_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC54_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC54_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC54_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC54_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC54_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC54_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC54_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC54_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC54_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC54_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC54_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC55 ======================================================== */ + #define R_GWCA0_GWDCC55_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC55_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC55_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC55_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC55_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC55_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC55_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC55_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC55_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC55_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC55_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC55_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC56 ======================================================== */ + #define R_GWCA0_GWDCC56_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC56_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC56_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC56_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC56_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC56_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC56_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC56_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC56_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC56_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC56_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC56_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC57 ======================================================== */ + #define R_GWCA0_GWDCC57_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC57_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC57_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC57_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC57_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC57_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC57_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC57_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC57_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC57_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC57_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC57_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC58 ======================================================== */ + #define R_GWCA0_GWDCC58_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC58_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC58_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC58_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC58_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC58_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC58_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC58_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC58_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC58_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC58_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC58_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC59 ======================================================== */ + #define R_GWCA0_GWDCC59_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC59_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC59_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC59_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC59_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC59_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC59_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC59_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC59_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC59_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC59_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC59_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC60 ======================================================== */ + #define R_GWCA0_GWDCC60_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC60_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC60_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC60_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC60_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC60_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC60_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC60_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC60_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC60_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC60_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC60_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC61 ======================================================== */ + #define R_GWCA0_GWDCC61_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC61_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC61_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC61_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC61_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC61_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC61_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC61_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC61_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC61_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC61_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC61_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC62 ======================================================== */ + #define R_GWCA0_GWDCC62_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC62_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC62_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC62_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC62_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC62_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC62_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC62_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC62_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC62_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC62_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC62_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWDCC63 ======================================================== */ + #define R_GWCA0_GWDCC63_SM_Pos (0UL) /*!< SM (Bit 0) */ + #define R_GWCA0_GWDCC63_SM_Msk (0x3UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_GWCA0_GWDCC63_EDE_Pos (8UL) /*!< EDE (Bit 8) */ + #define R_GWCA0_GWDCC63_EDE_Msk (0x100UL) /*!< EDE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_ETS_Pos (9UL) /*!< ETS (Bit 9) */ + #define R_GWCA0_GWDCC63_ETS_Msk (0x200UL) /*!< ETS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_SL_Pos (10UL) /*!< SL (Bit 10) */ + #define R_GWCA0_GWDCC63_SL_Msk (0x400UL) /*!< SL (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_DQT_Pos (11UL) /*!< DQT (Bit 11) */ + #define R_GWCA0_GWDCC63_DQT_Msk (0x800UL) /*!< DQT (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_DCP_Pos (16UL) /*!< DCP (Bit 16) */ + #define R_GWCA0_GWDCC63_DCP_Msk (0x70000UL) /*!< DCP (Bitfield-Mask: 0x07) */ + #define R_GWCA0_GWDCC63_BALR_Pos (24UL) /*!< BALR (Bit 24) */ + #define R_GWCA0_GWDCC63_BALR_Msk (0x1000000UL) /*!< BALR (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWDCC63_OSID_Pos (28UL) /*!< OSID (Bit 28) */ + #define R_GWCA0_GWDCC63_OSID_Msk (0x70000000UL) /*!< OSID (Bitfield-Mask: 0x07) */ +/* ======================================================== GWAARSS ======================================================== */ + #define R_GWCA0_GWAARSS_AARA_Pos (0UL) /*!< AARA (Bit 0) */ + #define R_GWCA0_GWAARSS_AARA_Msk (0x7fUL) /*!< AARA (Bitfield-Mask: 0x7f) */ +/* ======================================================= GWAARSR0 ======================================================== */ + #define R_GWCA0_GWAARSR0_ACARU_Pos (0UL) /*!< ACARU (Bit 0) */ + #define R_GWCA0_GWAARSR0_ACARU_Msk (0xffUL) /*!< ACARU (Bitfield-Mask: 0xff) */ + #define R_GWCA0_GWAARSR0_AARSEF_Pos (16UL) /*!< AARSEF (Bit 16) */ + #define R_GWCA0_GWAARSR0_AARSEF_Msk (0x10000UL) /*!< AARSEF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAARSR0_AARSSF_Pos (17UL) /*!< AARSSF (Bit 17) */ + #define R_GWCA0_GWAARSR0_AARSSF_Msk (0x20000UL) /*!< AARSSF (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWAARSR0_AARS_Pos (31UL) /*!< AARS (Bit 31) */ + #define R_GWCA0_GWAARSR0_AARS_Msk (0x80000000UL) /*!< AARS (Bitfield-Mask: 0x01) */ +/* ======================================================= GWAARSR1 ======================================================== */ + #define R_GWCA0_GWAARSR1_ACARD_Pos (0UL) /*!< ACARD (Bit 0) */ + #define R_GWCA0_GWAARSR1_ACARD_Msk (0xffffffffUL) /*!< ACARD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GWIDAUAS0 ======================================================= */ + #define R_GWCA0_GWIDAUAS0_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS0_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS1 ======================================================= */ + #define R_GWCA0_GWIDAUAS1_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS1_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS2 ======================================================= */ + #define R_GWCA0_GWIDAUAS2_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS2_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDAUAS3 ======================================================= */ + #define R_GWCA0_GWIDAUAS3_IDAUAS_Pos (0UL) /*!< IDAUAS (Bit 0) */ + #define R_GWCA0_GWIDAUAS3_IDAUAS_Msk (0xffffffUL) /*!< IDAUAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM0 ======================================================== */ + #define R_GWCA0_GWIDASM0_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM0_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM1 ======================================================== */ + #define R_GWCA0_GWIDASM1_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM1_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM2 ======================================================== */ + #define R_GWCA0_GWIDASM2_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM2_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ======================================================= GWIDASM3 ======================================================== */ + #define R_GWCA0_GWIDASM3_IDAS_Pos (0UL) /*!< IDAS (Bit 0) */ + #define R_GWCA0_GWIDASM3_IDAS_Msk (0xffffffUL) /*!< IDAS (Bitfield-Mask: 0xffffff) */ +/* ====================================================== GWIDASAM00 ======================================================= */ + #define R_GWCA0_GWIDASAM00_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM00_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM10 ======================================================= */ + #define R_GWCA0_GWIDASAM10_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM10_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM01 ======================================================= */ + #define R_GWCA0_GWIDASAM01_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM01_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM11 ======================================================= */ + #define R_GWCA0_GWIDASAM11_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM11_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM02 ======================================================= */ + #define R_GWCA0_GWIDASAM02_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM02_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM12 ======================================================= */ + #define R_GWCA0_GWIDASAM12_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM12_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDASAM03 ======================================================= */ + #define R_GWCA0_GWIDASAM03_IDASAU_Pos (0UL) /*!< IDASAU (Bit 0) */ + #define R_GWCA0_GWIDASAM03_IDASAU_Msk (0xffUL) /*!< IDASAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDASAM13 ======================================================= */ + #define R_GWCA0_GWIDASAM13_IDASAL_Pos (0UL) /*!< IDASAL (Bit 0) */ + #define R_GWCA0_GWIDASAM13_IDASAL_Msk (0xffffffffUL) /*!< IDASAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM00 ======================================================= */ + #define R_GWCA0_GWIDACAM00_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM00_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM10 ======================================================= */ + #define R_GWCA0_GWIDACAM10_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM10_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM01 ======================================================= */ + #define R_GWCA0_GWIDACAM01_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM01_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM11 ======================================================= */ + #define R_GWCA0_GWIDACAM11_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM11_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM02 ======================================================= */ + #define R_GWCA0_GWIDACAM02_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM02_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM12 ======================================================= */ + #define R_GWCA0_GWIDACAM12_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM12_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWIDACAM03 ======================================================= */ + #define R_GWCA0_GWIDACAM03_IDACAU_Pos (0UL) /*!< IDACAU (Bit 0) */ + #define R_GWCA0_GWIDACAM03_IDACAU_Msk (0xffUL) /*!< IDACAU (Bitfield-Mask: 0xff) */ +/* ====================================================== GWIDACAM13 ======================================================= */ + #define R_GWCA0_GWIDACAM13_IDACAL_Pos (0UL) /*!< IDACAL (Bit 0) */ + #define R_GWCA0_GWIDACAM13_IDACAL_Msk (0xffffffffUL) /*!< IDACAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWGRLC ========================================================= */ + #define R_GWCA0_GWGRLC_GRLIV_Pos (0UL) /*!< GRLIV (Bit 0) */ + #define R_GWCA0_GWGRLC_GRLIV_Msk (0xffffUL) /*!< GRLIV (Bitfield-Mask: 0xffff) */ + #define R_GWCA0_GWGRLC_GRLE_Pos (16UL) /*!< GRLE (Bit 16) */ + #define R_GWCA0_GWGRLC_GRLE_Msk (0x10000UL) /*!< GRLE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWGRLC_GRLULRS_Pos (17UL) /*!< GRLULRS (Bit 17) */ + #define R_GWCA0_GWGRLC_GRLULRS_Msk (0x20000UL) /*!< GRLULRS (Bitfield-Mask: 0x01) */ +/* ======================================================= GWGRLULC ======================================================== */ + #define R_GWCA0_GWGRLULC_GRLUL_Pos (0UL) /*!< GRLUL (Bit 0) */ + #define R_GWCA0_GWGRLULC_GRLUL_Msk (0xffffffUL) /*!< GRLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC0 ========================================================= */ + #define R_GWCA0_GWRLC0_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC0_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC0_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC0_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC0 ======================================================== */ + #define R_GWCA0_GWRLULC0_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC0_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC1 ========================================================= */ + #define R_GWCA0_GWRLC1_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC1_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC1_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC1_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC1 ======================================================== */ + #define R_GWCA0_GWRLULC1_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC1_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC2 ========================================================= */ + #define R_GWCA0_GWRLC2_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC2_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC2_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC2_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC2 ======================================================== */ + #define R_GWCA0_GWRLULC2_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC2_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC3 ========================================================= */ + #define R_GWCA0_GWRLC3_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC3_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC3_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC3_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC3 ======================================================== */ + #define R_GWCA0_GWRLULC3_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC3_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC4 ========================================================= */ + #define R_GWCA0_GWRLC4_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC4_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC4_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC4_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC4 ======================================================== */ + #define R_GWCA0_GWRLULC4_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC4_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC5 ========================================================= */ + #define R_GWCA0_GWRLC5_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC5_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC5_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC5_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC5 ======================================================== */ + #define R_GWCA0_GWRLULC5_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC5_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC6 ========================================================= */ + #define R_GWCA0_GWRLC6_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC6_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC6_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC6_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC6 ======================================================== */ + #define R_GWCA0_GWRLULC6_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC6_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWRLC7 ========================================================= */ + #define R_GWCA0_GWRLC7_RLIV_Pos (0UL) /*!< RLIV (Bit 0) */ + #define R_GWCA0_GWRLC7_RLIV_Msk (0xfffUL) /*!< RLIV (Bitfield-Mask: 0xfff) */ + #define R_GWCA0_GWRLC7_RLE_Pos (16UL) /*!< RLE (Bit 16) */ + #define R_GWCA0_GWRLC7_RLE_Msk (0x10000UL) /*!< RLE (Bitfield-Mask: 0x01) */ +/* ======================================================= GWRLULC7 ======================================================== */ + #define R_GWCA0_GWRLULC7_RLUL_Pos (0UL) /*!< RLUL (Bit 0) */ + #define R_GWCA0_GWRLULC7_RLUL_Msk (0xffffffUL) /*!< RLUL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== GWIDPC ========================================================= */ + #define R_GWCA0_GWIDPC_IDPV_Pos (0UL) /*!< IDPV (Bit 0) */ + #define R_GWCA0_GWIDPC_IDPV_Msk (0x3ffUL) /*!< IDPV (Bitfield-Mask: 0x3ff) */ +/* ======================================================== GWIDC0 ========================================================= */ + #define R_GWCA0_GWIDC0_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC0_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC1 ========================================================= */ + #define R_GWCA0_GWIDC1_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC1_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC2 ========================================================= */ + #define R_GWCA0_GWIDC2_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC2_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC3 ========================================================= */ + #define R_GWCA0_GWIDC3_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC3_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC4 ========================================================= */ + #define R_GWCA0_GWIDC4_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC4_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC5 ========================================================= */ + #define R_GWCA0_GWIDC5_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC5_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC6 ========================================================= */ + #define R_GWCA0_GWIDC6_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC6_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC7 ========================================================= */ + #define R_GWCA0_GWIDC7_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC7_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC8 ========================================================= */ + #define R_GWCA0_GWIDC8_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC8_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC9 ========================================================= */ + #define R_GWCA0_GWIDC9_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC9_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC10 ======================================================== */ + #define R_GWCA0_GWIDC10_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC10_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC11 ======================================================== */ + #define R_GWCA0_GWIDC11_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC11_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC12 ======================================================== */ + #define R_GWCA0_GWIDC12_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC12_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC13 ======================================================== */ + #define R_GWCA0_GWIDC13_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC13_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC14 ======================================================== */ + #define R_GWCA0_GWIDC14_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC14_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC15 ======================================================== */ + #define R_GWCA0_GWIDC15_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC15_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC16 ======================================================== */ + #define R_GWCA0_GWIDC16_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC16_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC17 ======================================================== */ + #define R_GWCA0_GWIDC17_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC17_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC18 ======================================================== */ + #define R_GWCA0_GWIDC18_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC18_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC19 ======================================================== */ + #define R_GWCA0_GWIDC19_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC19_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC20 ======================================================== */ + #define R_GWCA0_GWIDC20_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC20_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC21 ======================================================== */ + #define R_GWCA0_GWIDC21_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC21_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC22 ======================================================== */ + #define R_GWCA0_GWIDC22_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC22_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC23 ======================================================== */ + #define R_GWCA0_GWIDC23_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC23_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC24 ======================================================== */ + #define R_GWCA0_GWIDC24_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC24_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC25 ======================================================== */ + #define R_GWCA0_GWIDC25_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC25_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC26 ======================================================== */ + #define R_GWCA0_GWIDC26_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC26_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC27 ======================================================== */ + #define R_GWCA0_GWIDC27_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC27_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC28 ======================================================== */ + #define R_GWCA0_GWIDC28_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC28_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC29 ======================================================== */ + #define R_GWCA0_GWIDC29_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC29_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC30 ======================================================== */ + #define R_GWCA0_GWIDC30_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC30_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC31 ======================================================== */ + #define R_GWCA0_GWIDC31_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC31_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC32 ======================================================== */ + #define R_GWCA0_GWIDC32_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC32_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC33 ======================================================== */ + #define R_GWCA0_GWIDC33_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC33_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC34 ======================================================== */ + #define R_GWCA0_GWIDC34_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC34_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC35 ======================================================== */ + #define R_GWCA0_GWIDC35_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC35_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC36 ======================================================== */ + #define R_GWCA0_GWIDC36_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC36_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC37 ======================================================== */ + #define R_GWCA0_GWIDC37_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC37_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC38 ======================================================== */ + #define R_GWCA0_GWIDC38_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC38_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC39 ======================================================== */ + #define R_GWCA0_GWIDC39_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC39_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC40 ======================================================== */ + #define R_GWCA0_GWIDC40_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC40_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC41 ======================================================== */ + #define R_GWCA0_GWIDC41_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC41_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC42 ======================================================== */ + #define R_GWCA0_GWIDC42_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC42_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC43 ======================================================== */ + #define R_GWCA0_GWIDC43_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC43_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC44 ======================================================== */ + #define R_GWCA0_GWIDC44_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC44_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC45 ======================================================== */ + #define R_GWCA0_GWIDC45_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC45_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC46 ======================================================== */ + #define R_GWCA0_GWIDC46_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC46_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC47 ======================================================== */ + #define R_GWCA0_GWIDC47_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC47_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC48 ======================================================== */ + #define R_GWCA0_GWIDC48_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC48_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC49 ======================================================== */ + #define R_GWCA0_GWIDC49_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC49_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC50 ======================================================== */ + #define R_GWCA0_GWIDC50_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC50_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC51 ======================================================== */ + #define R_GWCA0_GWIDC51_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC51_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC52 ======================================================== */ + #define R_GWCA0_GWIDC52_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC52_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC53 ======================================================== */ + #define R_GWCA0_GWIDC53_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC53_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC54 ======================================================== */ + #define R_GWCA0_GWIDC54_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC54_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC55 ======================================================== */ + #define R_GWCA0_GWIDC55_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC55_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC56 ======================================================== */ + #define R_GWCA0_GWIDC56_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC56_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC57 ======================================================== */ + #define R_GWCA0_GWIDC57_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC57_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC58 ======================================================== */ + #define R_GWCA0_GWIDC58_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC58_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC59 ======================================================== */ + #define R_GWCA0_GWIDC59_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC59_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC60 ======================================================== */ + #define R_GWCA0_GWIDC60_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC60_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC61 ======================================================== */ + #define R_GWCA0_GWIDC61_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC61_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC62 ======================================================== */ + #define R_GWCA0_GWIDC62_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC62_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC63 ======================================================== */ + #define R_GWCA0_GWIDC63_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC63_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWIDC64 ======================================================== */ + #define R_GWCA0_GWIDC64_IDV_Pos (0UL) /*!< IDV (Bit 0) */ + #define R_GWCA0_GWIDC64_IDV_Msk (0xfffUL) /*!< IDV (Bitfield-Mask: 0xfff) */ +/* ======================================================== GWRDCN ========================================================= */ + #define R_GWCA0_GWRDCN_RDN_Pos (0UL) /*!< RDN (Bit 0) */ + #define R_GWCA0_GWRDCN_RDN_Msk (0xffffffffUL) /*!< RDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWTDCN ========================================================= */ + #define R_GWCA0_GWTDCN_TDN_Pos (0UL) /*!< TDN (Bit 0) */ + #define R_GWCA0_GWTDCN_TDN_Msk (0xffffffffUL) /*!< TDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GWTSCN ========================================================= */ + #define R_GWCA0_GWTSCN_TN_Pos (0UL) /*!< TN (Bit 0) */ + #define R_GWCA0_GWTSCN_TN_Msk (0xffffffffUL) /*!< TN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GWTSOVFECN ======================================================= */ + #define R_GWCA0_GWTSOVFECN_TSOVFEN_Pos (0UL) /*!< TSOVFEN (Bit 0) */ + #define R_GWCA0_GWTSOVFECN_TSOVFEN_Msk (0xffffUL) /*!< TSOVFEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== GWUSMFSECN ======================================================= */ + #define R_GWCA0_GWUSMFSECN_USMFSEN_Pos (0UL) /*!< USMFSEN (Bit 0) */ + #define R_GWCA0_GWUSMFSECN_USMFSEN_Msk (0xffffUL) /*!< USMFSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWTFECN ======================================================== */ + #define R_GWCA0_GWTFECN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ + #define R_GWCA0_GWTFECN_TFEN_Msk (0xffffUL) /*!< TFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWSEQECN ======================================================== */ + #define R_GWCA0_GWSEQECN_SEQEN_Pos (0UL) /*!< SEQEN (Bit 0) */ + #define R_GWCA0_GWSEQECN_SEQEN_Msk (0xffffUL) /*!< SEQEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTXDNECN ======================================================= */ + #define R_GWCA0_GWTXDNECN_TXDNEN_Pos (0UL) /*!< TXDNEN (Bit 0) */ + #define R_GWCA0_GWTXDNECN_TXDNEN_Msk (0xffffUL) /*!< TXDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWFSECN ======================================================== */ + #define R_GWCA0_GWFSECN_FSEN_Pos (0UL) /*!< FSEN (Bit 0) */ + #define R_GWCA0_GWFSECN_FSEN_Msk (0xffffUL) /*!< FSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTDFECN ======================================================== */ + #define R_GWCA0_GWTDFECN_TDFEN_Pos (0UL) /*!< TDFEN (Bit 0) */ + #define R_GWCA0_GWTDFECN_TDFEN_Msk (0xffffUL) /*!< TDFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWTSDNECN ======================================================= */ + #define R_GWCA0_GWTSDNECN_TSDNEN_Pos (0UL) /*!< TSDNEN (Bit 0) */ + #define R_GWCA0_GWTSDNECN_TSDNEN_Msk (0xffffUL) /*!< TSDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDQOECN ======================================================== */ + #define R_GWCA0_GWDQOECN_DQOEN_Pos (0UL) /*!< DQOEN (Bit 0) */ + #define R_GWCA0_GWDQOECN_DQOEN_Msk (0xffffUL) /*!< DQOEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDQSECN ======================================================== */ + #define R_GWCA0_GWDQSECN_DQSEN_Pos (0UL) /*!< DQSEN (Bit 0) */ + #define R_GWCA0_GWDQSECN_DQSEN_Msk (0xffffUL) /*!< DQSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDFECN ======================================================== */ + #define R_GWCA0_GWDFECN_DFEN_Pos (0UL) /*!< DFEN (Bit 0) */ + #define R_GWCA0_GWDFECN_DFEN_Msk (0xffffUL) /*!< DFEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDSECN ======================================================== */ + #define R_GWCA0_GWDSECN_DSEN_Pos (0UL) /*!< DSEN (Bit 0) */ + #define R_GWCA0_GWDSECN_DSEN_Msk (0xffffUL) /*!< DSEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDSZECN ======================================================== */ + #define R_GWCA0_GWDSZECN_DSZEN_Pos (0UL) /*!< DSZEN (Bit 0) */ + #define R_GWCA0_GWDSZECN_DSZEN_Msk (0xffffUL) /*!< DSZEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWDCTECN ======================================================== */ + #define R_GWCA0_GWDCTECN_DCTEN_Pos (0UL) /*!< DCTEN (Bit 0) */ + #define R_GWCA0_GWDCTECN_DCTEN_Msk (0xffffUL) /*!< DCTEN (Bitfield-Mask: 0xffff) */ +/* ======================================================= GWRXDNECN ======================================================= */ + #define R_GWCA0_GWRXDNECN_RXDNEN_Pos (0UL) /*!< RXDNEN (Bit 0) */ + #define R_GWCA0_GWRXDNECN_RXDNEN_Msk (0xffffUL) /*!< RXDNEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== GWDIS0 ========================================================= */ +/* ======================================================== GWDIE0 ========================================================= */ +/* ======================================================== GWDID0 ========================================================= */ +/* ======================================================== GWDIDS0 ======================================================== */ +/* ======================================================== GWDIS1 ========================================================= */ +/* ======================================================== GWDIE1 ========================================================= */ +/* ======================================================== GWDID1 ========================================================= */ +/* ======================================================== GWDIDS1 ======================================================== */ +/* ======================================================== GWTSDIS ======================================================== */ + #define R_GWCA0_GWTSDIS_TSDIS0_Pos (0UL) /*!< TSDIS0 (Bit 0) */ + #define R_GWCA0_GWTSDIS_TSDIS0_Msk (0x1UL) /*!< TSDIS0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDIS_TSDIS1_Pos (1UL) /*!< TSDIS1 (Bit 1) */ + #define R_GWCA0_GWTSDIS_TSDIS1_Msk (0x2UL) /*!< TSDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTSDIE ======================================================== */ + #define R_GWCA0_GWTSDIE_TSDIE0_Pos (0UL) /*!< TSDIE0 (Bit 0) */ + #define R_GWCA0_GWTSDIE_TSDIE0_Msk (0x1UL) /*!< TSDIE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDIE_TSDIE1_Pos (1UL) /*!< TSDIE1 (Bit 1) */ + #define R_GWCA0_GWTSDIE_TSDIE1_Msk (0x2UL) /*!< TSDIE1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWTSDID ======================================================== */ + #define R_GWCA0_GWTSDID_TSDID0_Pos (0UL) /*!< TSDID0 (Bit 0) */ + #define R_GWCA0_GWTSDID_TSDID0_Msk (0x1UL) /*!< TSDID0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWTSDID_TSDID1_Pos (1UL) /*!< TSDID1 (Bit 1) */ + #define R_GWCA0_GWTSDID_TSDID1_Msk (0x2UL) /*!< TSDID1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS0 ========================================================= */ + #define R_GWCA0_GWEIS0_AES_Pos (0UL) /*!< AES (Bit 0) */ + #define R_GWCA0_GWEIS0_AES_Msk (0x1UL) /*!< AES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_DECCES_Pos (1UL) /*!< DECCES (Bit 1) */ + #define R_GWCA0_GWEIS0_DECCES_Msk (0x2UL) /*!< DECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TECCES_Pos (2UL) /*!< TECCES (Bit 2) */ + #define R_GWCA0_GWEIS0_TECCES_Msk (0x4UL) /*!< TECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_PECCES_Pos (3UL) /*!< PECCES (Bit 3) */ + #define R_GWCA0_GWEIS0_PECCES_Msk (0x8UL) /*!< PECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_DSECCES_Pos (4UL) /*!< DSECCES (Bit 4) */ + #define R_GWCA0_GWEIS0_DSECCES_Msk (0x10UL) /*!< DSECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_MECCES_Pos (5UL) /*!< MECCES (Bit 5) */ + #define R_GWCA0_GWEIS0_MECCES_Msk (0x20UL) /*!< MECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_AECCES_Pos (6UL) /*!< AECCES (Bit 6) */ + #define R_GWCA0_GWEIS0_AECCES_Msk (0x40UL) /*!< AECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSECCES_Pos (7UL) /*!< TSECCES (Bit 7) */ + #define R_GWCA0_GWEIS0_TSECCES_Msk (0x80UL) /*!< TSECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_L23UECCES_Pos (8UL) /*!< L23UECCES (Bit 8) */ + #define R_GWCA0_GWEIS0_L23UECCES_Msk (0x100UL) /*!< L23UECCES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSOVFES_Pos (9UL) /*!< TSOVFES (Bit 9) */ + #define R_GWCA0_GWEIS0_TSOVFES_Msk (0x200UL) /*!< TSOVFES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_USMFSES_Pos (10UL) /*!< USMFSES (Bit 10) */ + #define R_GWCA0_GWEIS0_USMFSES_Msk (0x400UL) /*!< USMFSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TFES_Pos (11UL) /*!< TFES (Bit 11) */ + #define R_GWCA0_GWEIS0_TFES_Msk (0x800UL) /*!< TFES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_SEQES_Pos (12UL) /*!< SEQES (Bit 12) */ + #define R_GWCA0_GWEIS0_SEQES_Msk (0x1000UL) /*!< SEQES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TXDNES_Pos (14UL) /*!< TXDNES (Bit 14) */ + #define R_GWCA0_GWEIS0_TXDNES_Msk (0x4000UL) /*!< TXDNES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSHES_Pos (15UL) /*!< TSHES (Bit 15) */ + #define R_GWCA0_GWEIS0_TSHES_Msk (0x8000UL) /*!< TSHES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES0_Pos (16UL) /*!< FSES0 (Bit 16) */ + #define R_GWCA0_GWEIS0_FSES0_Msk (0x10000UL) /*!< FSES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES1_Pos (17UL) /*!< FSES1 (Bit 17) */ + #define R_GWCA0_GWEIS0_FSES1_Msk (0x20000UL) /*!< FSES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES2_Pos (18UL) /*!< FSES2 (Bit 18) */ + #define R_GWCA0_GWEIS0_FSES2_Msk (0x40000UL) /*!< FSES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES3_Pos (19UL) /*!< FSES3 (Bit 19) */ + #define R_GWCA0_GWEIS0_FSES3_Msk (0x80000UL) /*!< FSES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES4_Pos (20UL) /*!< FSES4 (Bit 20) */ + #define R_GWCA0_GWEIS0_FSES4_Msk (0x100000UL) /*!< FSES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES5_Pos (21UL) /*!< FSES5 (Bit 21) */ + #define R_GWCA0_GWEIS0_FSES5_Msk (0x200000UL) /*!< FSES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES6_Pos (22UL) /*!< FSES6 (Bit 22) */ + #define R_GWCA0_GWEIS0_FSES6_Msk (0x400000UL) /*!< FSES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_FSES7_Pos (23UL) /*!< FSES7 (Bit 23) */ + #define R_GWCA0_GWEIS0_FSES7_Msk (0x800000UL) /*!< FSES7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TDFES0_Pos (24UL) /*!< TDFES0 (Bit 24) */ + #define R_GWCA0_GWEIS0_TDFES0_Msk (0x1000000UL) /*!< TDFES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TDFES1_Pos (25UL) /*!< TDFES1 (Bit 25) */ + #define R_GWCA0_GWEIS0_TDFES1_Msk (0x2000000UL) /*!< TDFES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSDNES0_Pos (28UL) /*!< TSDNES0 (Bit 28) */ + #define R_GWCA0_GWEIS0_TSDNES0_Msk (0x10000000UL) /*!< TSDNES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS0_TSDNES1_Pos (29UL) /*!< TSDNES1 (Bit 29) */ + #define R_GWCA0_GWEIS0_TSDNES1_Msk (0x20000000UL) /*!< TSDNES1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE0 ========================================================= */ + #define R_GWCA0_GWEIE0_AEE_Pos (0UL) /*!< AEE (Bit 0) */ + #define R_GWCA0_GWEIE0_AEE_Msk (0x1UL) /*!< AEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_DECCEE_Pos (1UL) /*!< DECCEE (Bit 1) */ + #define R_GWCA0_GWEIE0_DECCEE_Msk (0x2UL) /*!< DECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TECCEE_Pos (2UL) /*!< TECCEE (Bit 2) */ + #define R_GWCA0_GWEIE0_TECCEE_Msk (0x4UL) /*!< TECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_PECCEE_Pos (3UL) /*!< PECCEE (Bit 3) */ + #define R_GWCA0_GWEIE0_PECCEE_Msk (0x8UL) /*!< PECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_DSECCEE_Pos (4UL) /*!< DSECCEE (Bit 4) */ + #define R_GWCA0_GWEIE0_DSECCEE_Msk (0x10UL) /*!< DSECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_MECCEE_Pos (5UL) /*!< MECCEE (Bit 5) */ + #define R_GWCA0_GWEIE0_MECCEE_Msk (0x20UL) /*!< MECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_AECCEE_Pos (6UL) /*!< AECCEE (Bit 6) */ + #define R_GWCA0_GWEIE0_AECCEE_Msk (0x40UL) /*!< AECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSECCEE_Pos (7UL) /*!< TSECCEE (Bit 7) */ + #define R_GWCA0_GWEIE0_TSECCEE_Msk (0x80UL) /*!< TSECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_L23UECCEE_Pos (8UL) /*!< L23UECCEE (Bit 8) */ + #define R_GWCA0_GWEIE0_L23UECCEE_Msk (0x100UL) /*!< L23UECCEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSOVFEE_Pos (9UL) /*!< TSOVFEE (Bit 9) */ + #define R_GWCA0_GWEIE0_TSOVFEE_Msk (0x200UL) /*!< TSOVFEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_USMFSEE_Pos (10UL) /*!< USMFSEE (Bit 10) */ + #define R_GWCA0_GWEIE0_USMFSEE_Msk (0x400UL) /*!< USMFSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TFEE_Pos (11UL) /*!< TFEE (Bit 11) */ + #define R_GWCA0_GWEIE0_TFEE_Msk (0x800UL) /*!< TFEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_SEQEE_Pos (12UL) /*!< SEQEE (Bit 12) */ + #define R_GWCA0_GWEIE0_SEQEE_Msk (0x1000UL) /*!< SEQEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TXDNEE_Pos (14UL) /*!< TXDNEE (Bit 14) */ + #define R_GWCA0_GWEIE0_TXDNEE_Msk (0x4000UL) /*!< TXDNEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSHEE_Pos (15UL) /*!< TSHEE (Bit 15) */ + #define R_GWCA0_GWEIE0_TSHEE_Msk (0x8000UL) /*!< TSHEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE0_Pos (16UL) /*!< FSEE0 (Bit 16) */ + #define R_GWCA0_GWEIE0_FSEE0_Msk (0x10000UL) /*!< FSEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE1_Pos (17UL) /*!< FSEE1 (Bit 17) */ + #define R_GWCA0_GWEIE0_FSEE1_Msk (0x20000UL) /*!< FSEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE2_Pos (18UL) /*!< FSEE2 (Bit 18) */ + #define R_GWCA0_GWEIE0_FSEE2_Msk (0x40000UL) /*!< FSEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE3_Pos (19UL) /*!< FSEE3 (Bit 19) */ + #define R_GWCA0_GWEIE0_FSEE3_Msk (0x80000UL) /*!< FSEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE4_Pos (20UL) /*!< FSEE4 (Bit 20) */ + #define R_GWCA0_GWEIE0_FSEE4_Msk (0x100000UL) /*!< FSEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE5_Pos (21UL) /*!< FSEE5 (Bit 21) */ + #define R_GWCA0_GWEIE0_FSEE5_Msk (0x200000UL) /*!< FSEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE6_Pos (22UL) /*!< FSEE6 (Bit 22) */ + #define R_GWCA0_GWEIE0_FSEE6_Msk (0x400000UL) /*!< FSEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_FSEE7_Pos (23UL) /*!< FSEE7 (Bit 23) */ + #define R_GWCA0_GWEIE0_FSEE7_Msk (0x800000UL) /*!< FSEE7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TDFEE0_Pos (24UL) /*!< TDFEE0 (Bit 24) */ + #define R_GWCA0_GWEIE0_TDFEE0_Msk (0x1000000UL) /*!< TDFEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TDFEE1_Pos (25UL) /*!< TDFEE1 (Bit 25) */ + #define R_GWCA0_GWEIE0_TDFEE1_Msk (0x2000000UL) /*!< TDFEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSDNEE0_Pos (28UL) /*!< TSDNEE0 (Bit 28) */ + #define R_GWCA0_GWEIE0_TSDNEE0_Msk (0x10000000UL) /*!< TSDNEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE0_TSDNEE1_Pos (29UL) /*!< TSDNEE1 (Bit 29) */ + #define R_GWCA0_GWEIE0_TSDNEE1_Msk (0x20000000UL) /*!< TSDNEE1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID0 ========================================================= */ + #define R_GWCA0_GWEID0_AED_Pos (0UL) /*!< AED (Bit 0) */ + #define R_GWCA0_GWEID0_AED_Msk (0x1UL) /*!< AED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TECCED_Pos (1UL) /*!< TECCED (Bit 1) */ + #define R_GWCA0_GWEID0_TECCED_Msk (0x2UL) /*!< TECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_DECCED_Pos (2UL) /*!< DECCED (Bit 2) */ + #define R_GWCA0_GWEID0_DECCED_Msk (0x4UL) /*!< DECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_PECCED_Pos (3UL) /*!< PECCED (Bit 3) */ + #define R_GWCA0_GWEID0_PECCED_Msk (0x8UL) /*!< PECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_DSECCED_Pos (4UL) /*!< DSECCED (Bit 4) */ + #define R_GWCA0_GWEID0_DSECCED_Msk (0x10UL) /*!< DSECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_MECCED_Pos (5UL) /*!< MECCED (Bit 5) */ + #define R_GWCA0_GWEID0_MECCED_Msk (0x20UL) /*!< MECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_AECCED_Pos (6UL) /*!< AECCED (Bit 6) */ + #define R_GWCA0_GWEID0_AECCED_Msk (0x40UL) /*!< AECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSECCED_Pos (7UL) /*!< TSECCED (Bit 7) */ + #define R_GWCA0_GWEID0_TSECCED_Msk (0x80UL) /*!< TSECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_L23UECCED_Pos (8UL) /*!< L23UECCED (Bit 8) */ + #define R_GWCA0_GWEID0_L23UECCED_Msk (0x100UL) /*!< L23UECCED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSOVFED_Pos (9UL) /*!< TSOVFED (Bit 9) */ + #define R_GWCA0_GWEID0_TSOVFED_Msk (0x200UL) /*!< TSOVFED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_USMFSED_Pos (10UL) /*!< USMFSED (Bit 10) */ + #define R_GWCA0_GWEID0_USMFSED_Msk (0x400UL) /*!< USMFSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TFED_Pos (11UL) /*!< TFED (Bit 11) */ + #define R_GWCA0_GWEID0_TFED_Msk (0x800UL) /*!< TFED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_SEQED_Pos (12UL) /*!< SEQED (Bit 12) */ + #define R_GWCA0_GWEID0_SEQED_Msk (0x1000UL) /*!< SEQED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_IIPED_Pos (13UL) /*!< IIPED (Bit 13) */ + #define R_GWCA0_GWEID0_IIPED_Msk (0x2000UL) /*!< IIPED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TXDNED_Pos (14UL) /*!< TXDNED (Bit 14) */ + #define R_GWCA0_GWEID0_TXDNED_Msk (0x4000UL) /*!< TXDNED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSHED_Pos (15UL) /*!< TSHED (Bit 15) */ + #define R_GWCA0_GWEID0_TSHED_Msk (0x8000UL) /*!< TSHED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED0_Pos (16UL) /*!< FSED0 (Bit 16) */ + #define R_GWCA0_GWEID0_FSED0_Msk (0x10000UL) /*!< FSED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED1_Pos (17UL) /*!< FSED1 (Bit 17) */ + #define R_GWCA0_GWEID0_FSED1_Msk (0x20000UL) /*!< FSED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED2_Pos (18UL) /*!< FSED2 (Bit 18) */ + #define R_GWCA0_GWEID0_FSED2_Msk (0x40000UL) /*!< FSED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED3_Pos (19UL) /*!< FSED3 (Bit 19) */ + #define R_GWCA0_GWEID0_FSED3_Msk (0x80000UL) /*!< FSED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED4_Pos (20UL) /*!< FSED4 (Bit 20) */ + #define R_GWCA0_GWEID0_FSED4_Msk (0x100000UL) /*!< FSED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED5_Pos (21UL) /*!< FSED5 (Bit 21) */ + #define R_GWCA0_GWEID0_FSED5_Msk (0x200000UL) /*!< FSED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED6_Pos (22UL) /*!< FSED6 (Bit 22) */ + #define R_GWCA0_GWEID0_FSED6_Msk (0x400000UL) /*!< FSED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_FSED7_Pos (23UL) /*!< FSED7 (Bit 23) */ + #define R_GWCA0_GWEID0_FSED7_Msk (0x800000UL) /*!< FSED7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TDFED0_Pos (24UL) /*!< TDFED0 (Bit 24) */ + #define R_GWCA0_GWEID0_TDFED0_Msk (0x1000000UL) /*!< TDFED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TDFED1_Pos (25UL) /*!< TDFED1 (Bit 25) */ + #define R_GWCA0_GWEID0_TDFED1_Msk (0x2000000UL) /*!< TDFED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSDNED0_Pos (28UL) /*!< TSDNED0 (Bit 28) */ + #define R_GWCA0_GWEID0_TSDNED0_Msk (0x10000000UL) /*!< TSDNED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID0_TSDNED1_Pos (29UL) /*!< TSDNED1 (Bit 29) */ + #define R_GWCA0_GWEID0_TSDNED1_Msk (0x20000000UL) /*!< TSDNED1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS1 ========================================================= */ + #define R_GWCA0_GWEIS1_DQOES0_Pos (0UL) /*!< DQOES0 (Bit 0) */ + #define R_GWCA0_GWEIS1_DQOES0_Msk (0x1UL) /*!< DQOES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES1_Pos (1UL) /*!< DQOES1 (Bit 1) */ + #define R_GWCA0_GWEIS1_DQOES1_Msk (0x2UL) /*!< DQOES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES2_Pos (2UL) /*!< DQOES2 (Bit 2) */ + #define R_GWCA0_GWEIS1_DQOES2_Msk (0x4UL) /*!< DQOES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES3_Pos (3UL) /*!< DQOES3 (Bit 3) */ + #define R_GWCA0_GWEIS1_DQOES3_Msk (0x8UL) /*!< DQOES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES4_Pos (4UL) /*!< DQOES4 (Bit 4) */ + #define R_GWCA0_GWEIS1_DQOES4_Msk (0x10UL) /*!< DQOES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES5_Pos (5UL) /*!< DQOES5 (Bit 5) */ + #define R_GWCA0_GWEIS1_DQOES5_Msk (0x20UL) /*!< DQOES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES6_Pos (6UL) /*!< DQOES6 (Bit 6) */ + #define R_GWCA0_GWEIS1_DQOES6_Msk (0x40UL) /*!< DQOES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQOES7_Pos (7UL) /*!< DQOES7 (Bit 7) */ + #define R_GWCA0_GWEIS1_DQOES7_Msk (0x80UL) /*!< DQOES7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES0_Pos (16UL) /*!< DQSES0 (Bit 16) */ + #define R_GWCA0_GWEIS1_DQSES0_Msk (0x10000UL) /*!< DQSES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES1_Pos (17UL) /*!< DQSES1 (Bit 17) */ + #define R_GWCA0_GWEIS1_DQSES1_Msk (0x20000UL) /*!< DQSES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES2_Pos (18UL) /*!< DQSES2 (Bit 18) */ + #define R_GWCA0_GWEIS1_DQSES2_Msk (0x40000UL) /*!< DQSES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES3_Pos (19UL) /*!< DQSES3 (Bit 19) */ + #define R_GWCA0_GWEIS1_DQSES3_Msk (0x80000UL) /*!< DQSES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES4_Pos (20UL) /*!< DQSES4 (Bit 20) */ + #define R_GWCA0_GWEIS1_DQSES4_Msk (0x100000UL) /*!< DQSES4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES5_Pos (21UL) /*!< DQSES5 (Bit 21) */ + #define R_GWCA0_GWEIS1_DQSES5_Msk (0x200000UL) /*!< DQSES5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES6_Pos (22UL) /*!< DQSES6 (Bit 22) */ + #define R_GWCA0_GWEIS1_DQSES6_Msk (0x400000UL) /*!< DQSES6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS1_DQSES7_Pos (23UL) /*!< DQSES7 (Bit 23) */ + #define R_GWCA0_GWEIS1_DQSES7_Msk (0x800000UL) /*!< DQSES7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE1 ========================================================= */ + #define R_GWCA0_GWEIE1_DQOEE0_Pos (0UL) /*!< DQOEE0 (Bit 0) */ + #define R_GWCA0_GWEIE1_DQOEE0_Msk (0x1UL) /*!< DQOEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE1_Pos (1UL) /*!< DQOEE1 (Bit 1) */ + #define R_GWCA0_GWEIE1_DQOEE1_Msk (0x2UL) /*!< DQOEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE2_Pos (2UL) /*!< DQOEE2 (Bit 2) */ + #define R_GWCA0_GWEIE1_DQOEE2_Msk (0x4UL) /*!< DQOEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE3_Pos (3UL) /*!< DQOEE3 (Bit 3) */ + #define R_GWCA0_GWEIE1_DQOEE3_Msk (0x8UL) /*!< DQOEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE4_Pos (4UL) /*!< DQOEE4 (Bit 4) */ + #define R_GWCA0_GWEIE1_DQOEE4_Msk (0x10UL) /*!< DQOEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE5_Pos (5UL) /*!< DQOEE5 (Bit 5) */ + #define R_GWCA0_GWEIE1_DQOEE5_Msk (0x20UL) /*!< DQOEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE6_Pos (6UL) /*!< DQOEE6 (Bit 6) */ + #define R_GWCA0_GWEIE1_DQOEE6_Msk (0x40UL) /*!< DQOEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQOEE7_Pos (7UL) /*!< DQOEE7 (Bit 7) */ + #define R_GWCA0_GWEIE1_DQOEE7_Msk (0x80UL) /*!< DQOEE7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE0_Pos (16UL) /*!< DQSEE0 (Bit 16) */ + #define R_GWCA0_GWEIE1_DQSEE0_Msk (0x10000UL) /*!< DQSEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE1_Pos (17UL) /*!< DQSEE1 (Bit 17) */ + #define R_GWCA0_GWEIE1_DQSEE1_Msk (0x20000UL) /*!< DQSEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE2_Pos (18UL) /*!< DQSEE2 (Bit 18) */ + #define R_GWCA0_GWEIE1_DQSEE2_Msk (0x40000UL) /*!< DQSEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE3_Pos (19UL) /*!< DQSEE3 (Bit 19) */ + #define R_GWCA0_GWEIE1_DQSEE3_Msk (0x80000UL) /*!< DQSEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE4_Pos (20UL) /*!< DQSEE4 (Bit 20) */ + #define R_GWCA0_GWEIE1_DQSEE4_Msk (0x100000UL) /*!< DQSEE4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE5_Pos (21UL) /*!< DQSEE5 (Bit 21) */ + #define R_GWCA0_GWEIE1_DQSEE5_Msk (0x200000UL) /*!< DQSEE5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE6_Pos (22UL) /*!< DQSEE6 (Bit 22) */ + #define R_GWCA0_GWEIE1_DQSEE6_Msk (0x400000UL) /*!< DQSEE6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE1_DQSEE7_Pos (23UL) /*!< DQSEE7 (Bit 23) */ + #define R_GWCA0_GWEIE1_DQSEE7_Msk (0x800000UL) /*!< DQSEE7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID1 ========================================================= */ + #define R_GWCA0_GWEID1_DQOED0_Pos (0UL) /*!< DQOED0 (Bit 0) */ + #define R_GWCA0_GWEID1_DQOED0_Msk (0x1UL) /*!< DQOED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED1_Pos (1UL) /*!< DQOED1 (Bit 1) */ + #define R_GWCA0_GWEID1_DQOED1_Msk (0x2UL) /*!< DQOED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED2_Pos (2UL) /*!< DQOED2 (Bit 2) */ + #define R_GWCA0_GWEID1_DQOED2_Msk (0x4UL) /*!< DQOED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED3_Pos (3UL) /*!< DQOED3 (Bit 3) */ + #define R_GWCA0_GWEID1_DQOED3_Msk (0x8UL) /*!< DQOED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED4_Pos (4UL) /*!< DQOED4 (Bit 4) */ + #define R_GWCA0_GWEID1_DQOED4_Msk (0x10UL) /*!< DQOED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED5_Pos (5UL) /*!< DQOED5 (Bit 5) */ + #define R_GWCA0_GWEID1_DQOED5_Msk (0x20UL) /*!< DQOED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED6_Pos (6UL) /*!< DQOED6 (Bit 6) */ + #define R_GWCA0_GWEID1_DQOED6_Msk (0x40UL) /*!< DQOED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQOED7_Pos (7UL) /*!< DQOED7 (Bit 7) */ + #define R_GWCA0_GWEID1_DQOED7_Msk (0x80UL) /*!< DQOED7 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED0_Pos (16UL) /*!< DQSED0 (Bit 16) */ + #define R_GWCA0_GWEID1_DQSED0_Msk (0x10000UL) /*!< DQSED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED1_Pos (17UL) /*!< DQSED1 (Bit 17) */ + #define R_GWCA0_GWEID1_DQSED1_Msk (0x20000UL) /*!< DQSED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED2_Pos (18UL) /*!< DQSED2 (Bit 18) */ + #define R_GWCA0_GWEID1_DQSED2_Msk (0x40000UL) /*!< DQSED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED3_Pos (19UL) /*!< DQSED3 (Bit 19) */ + #define R_GWCA0_GWEID1_DQSED3_Msk (0x80000UL) /*!< DQSED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED4_Pos (20UL) /*!< DQSED4 (Bit 20) */ + #define R_GWCA0_GWEID1_DQSED4_Msk (0x100000UL) /*!< DQSED4 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED5_Pos (21UL) /*!< DQSED5 (Bit 21) */ + #define R_GWCA0_GWEID1_DQSED5_Msk (0x200000UL) /*!< DQSED5 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED6_Pos (22UL) /*!< DQSED6 (Bit 22) */ + #define R_GWCA0_GWEID1_DQSED6_Msk (0x400000UL) /*!< DQSED6 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID1_DQSED7_Pos (23UL) /*!< DQSED7 (Bit 23) */ + #define R_GWCA0_GWEID1_DQSED7_Msk (0x800000UL) /*!< DQSED7 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS20 ======================================================== */ +/* ======================================================== GWEIE20 ======================================================== */ +/* ======================================================== GWEID20 ======================================================== */ +/* ======================================================== GWEIS21 ======================================================== */ +/* ======================================================== GWEIE21 ======================================================== */ +/* ======================================================== GWEID21 ======================================================== */ +/* ======================================================== GWEIS3 ========================================================= */ + #define R_GWCA0_GWEIS3_IAOES0_Pos (0UL) /*!< IAOES0 (Bit 0) */ + #define R_GWCA0_GWEIS3_IAOES0_Msk (0x1UL) /*!< IAOES0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES1_Pos (1UL) /*!< IAOES1 (Bit 1) */ + #define R_GWCA0_GWEIS3_IAOES1_Msk (0x2UL) /*!< IAOES1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES2_Pos (2UL) /*!< IAOES2 (Bit 2) */ + #define R_GWCA0_GWEIS3_IAOES2_Msk (0x4UL) /*!< IAOES2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES3_Pos (3UL) /*!< IAOES3 (Bit 3) */ + #define R_GWCA0_GWEIS3_IAOES3_Msk (0x8UL) /*!< IAOES3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS3_IAOES4_Pos (4UL) /*!< IAOES4 (Bit 4) */ + #define R_GWCA0_GWEIS3_IAOES4_Msk (0x10UL) /*!< IAOES4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE3 ========================================================= */ + #define R_GWCA0_GWEIE3_IAOEE0_Pos (0UL) /*!< IAOEE0 (Bit 0) */ + #define R_GWCA0_GWEIE3_IAOEE0_Msk (0x1UL) /*!< IAOEE0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE1_Pos (1UL) /*!< IAOEE1 (Bit 1) */ + #define R_GWCA0_GWEIE3_IAOEE1_Msk (0x2UL) /*!< IAOEE1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE2_Pos (2UL) /*!< IAOEE2 (Bit 2) */ + #define R_GWCA0_GWEIE3_IAOEE2_Msk (0x4UL) /*!< IAOEE2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE3_Pos (3UL) /*!< IAOEE3 (Bit 3) */ + #define R_GWCA0_GWEIE3_IAOEE3_Msk (0x8UL) /*!< IAOEE3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE3_IAOEE4_Pos (4UL) /*!< IAOEE4 (Bit 4) */ + #define R_GWCA0_GWEIE3_IAOEE4_Msk (0x10UL) /*!< IAOEE4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID3 ========================================================= */ + #define R_GWCA0_GWEID3_IAOED0_Pos (0UL) /*!< IAOED0 (Bit 0) */ + #define R_GWCA0_GWEID3_IAOED0_Msk (0x1UL) /*!< IAOED0 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED1_Pos (1UL) /*!< IAOED1 (Bit 1) */ + #define R_GWCA0_GWEID3_IAOED1_Msk (0x2UL) /*!< IAOED1 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED2_Pos (2UL) /*!< IAOED2 (Bit 2) */ + #define R_GWCA0_GWEID3_IAOED2_Msk (0x4UL) /*!< IAOED2 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED3_Pos (3UL) /*!< IAOED3 (Bit 3) */ + #define R_GWCA0_GWEID3_IAOED3_Msk (0x8UL) /*!< IAOED3 (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID3_IAOED4_Pos (4UL) /*!< IAOED4 (Bit 4) */ + #define R_GWCA0_GWEID3_IAOED4_Msk (0x10UL) /*!< IAOED4 (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS4 ========================================================= */ + #define R_GWCA0_GWEIS4_DSSES_Pos (0UL) /*!< DSSES (Bit 0) */ + #define R_GWCA0_GWEIS4_DSSES_Msk (0x1UL) /*!< DSSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSSEIOS_Pos (1UL) /*!< DSSEIOS (Bit 1) */ + #define R_GWCA0_GWEIS4_DSSEIOS_Msk (0x2UL) /*!< DSSEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSSECN_Pos (8UL) /*!< DSSECN (Bit 8) */ + #define R_GWCA0_GWEIS4_DSSECN_Msk (0x3f00UL) /*!< DSSECN (Bitfield-Mask: 0x3f) */ + #define R_GWCA0_GWEIS4_DSES_Pos (16UL) /*!< DSES (Bit 16) */ + #define R_GWCA0_GWEIS4_DSES_Msk (0x10000UL) /*!< DSES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSEIOS_Pos (17UL) /*!< DSEIOS (Bit 17) */ + #define R_GWCA0_GWEIS4_DSEIOS_Msk (0x20000UL) /*!< DSEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS4_DSECN_Pos (24UL) /*!< DSECN (Bit 24) */ + #define R_GWCA0_GWEIS4_DSECN_Msk (0x3f000000UL) /*!< DSECN (Bitfield-Mask: 0x3f) */ +/* ======================================================== GWEIE4 ========================================================= */ + #define R_GWCA0_GWEIE4_DSSEE_Pos (0UL) /*!< DSSEE (Bit 0) */ + #define R_GWCA0_GWEIE4_DSSEE_Msk (0x1UL) /*!< DSSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSSEIOE_Pos (1UL) /*!< DSSEIOE (Bit 1) */ + #define R_GWCA0_GWEIE4_DSSEIOE_Msk (0x2UL) /*!< DSSEIOE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSEE_Pos (16UL) /*!< DSEE (Bit 16) */ + #define R_GWCA0_GWEIE4_DSEE_Msk (0x10000UL) /*!< DSEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE4_DSEIOE_Pos (17UL) /*!< DSEIOE (Bit 17) */ + #define R_GWCA0_GWEIE4_DSEIOE_Msk (0x20000UL) /*!< DSEIOE (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID4 ========================================================= */ + #define R_GWCA0_GWEID4_DSSED_Pos (0UL) /*!< DSSED (Bit 0) */ + #define R_GWCA0_GWEID4_DSSED_Msk (0x1UL) /*!< DSSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSSEIOD_Pos (1UL) /*!< DSSEIOD (Bit 1) */ + #define R_GWCA0_GWEID4_DSSEIOD_Msk (0x2UL) /*!< DSSEIOD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSED_Pos (16UL) /*!< DSED (Bit 16) */ + #define R_GWCA0_GWEID4_DSED_Msk (0x10000UL) /*!< DSED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID4_DSEIOD_Pos (17UL) /*!< DSEIOD (Bit 17) */ + #define R_GWCA0_GWEID4_DSEIOD_Msk (0x20000UL) /*!< DSEIOD (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIS5 ========================================================= */ + #define R_GWCA0_GWEIS5_DCTES_Pos (0UL) /*!< DCTES (Bit 0) */ + #define R_GWCA0_GWEIS5_DCTES_Msk (0x1UL) /*!< DCTES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_DCTEIOS_Pos (1UL) /*!< DCTEIOS (Bit 1) */ + #define R_GWCA0_GWEIS5_DCTEIOS_Msk (0x2UL) /*!< DCTEIOS (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_DCTECN_Pos (8UL) /*!< DCTECN (Bit 8) */ + #define R_GWCA0_GWEIS5_DCTECN_Msk (0x3f00UL) /*!< DCTECN (Bitfield-Mask: 0x3f) */ + #define R_GWCA0_GWEIS5_RXDNES_Pos (16UL) /*!< RXDNES (Bit 16) */ + #define R_GWCA0_GWEIS5_RXDNES_Msk (0x10000UL) /*!< RXDNES (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIS5_RXDNEIOS_Pos (17UL) /*!< RXDNEIOS (Bit 17) */ + #define R_GWCA0_GWEIS5_RXDNEIOS_Msk (0x20000UL) /*!< RXDNEIOS (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEIE5 ========================================================= */ + #define R_GWCA0_GWEIE5_DCTEE_Pos (0UL) /*!< DCTEE (Bit 0) */ + #define R_GWCA0_GWEIE5_DCTEE_Msk (0x1UL) /*!< DCTEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_DCTEIOE_Pos (1UL) /*!< DCTEIOE (Bit 1) */ + #define R_GWCA0_GWEIE5_DCTEIOE_Msk (0x2UL) /*!< DCTEIOE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_RXDNEE_Pos (16UL) /*!< RXDNEE (Bit 16) */ + #define R_GWCA0_GWEIE5_RXDNEE_Msk (0x10000UL) /*!< RXDNEE (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEIE5_RXDNEIOE_Pos (17UL) /*!< RXDNEIOE (Bit 17) */ + #define R_GWCA0_GWEIE5_RXDNEIOE_Msk (0x20000UL) /*!< RXDNEIOE (Bitfield-Mask: 0x01) */ +/* ======================================================== GWEID5 ========================================================= */ + #define R_GWCA0_GWEID5_DCTED_Pos (0UL) /*!< DCTED (Bit 0) */ + #define R_GWCA0_GWEID5_DCTED_Msk (0x1UL) /*!< DCTED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_DCTEIOD_Pos (1UL) /*!< DCTEIOD (Bit 1) */ + #define R_GWCA0_GWEID5_DCTEIOD_Msk (0x2UL) /*!< DCTEIOD (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_RXDNED_Pos (15UL) /*!< RXDNED (Bit 15) */ + #define R_GWCA0_GWEID5_RXDNED_Msk (0x8000UL) /*!< RXDNED (Bitfield-Mask: 0x01) */ + #define R_GWCA0_GWEID5_RXDNEIOD_Pos (16UL) /*!< RXDNEIOD (Bit 16) */ + #define R_GWCA0_GWEID5_RXDNEIOD_Msk (0x10000UL) /*!< RXDNEIOD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IPC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IPCSEM ========================================================= */ + #define R_IPC_IPCSEM_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_IPC_IPCSEM_LOCK_Msk (0x1UL) /*!< LOCK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MFWD ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= FWGC ========================================================== */ + #define R_MFWD_FWGC_SVM_Pos (0UL) /*!< SVM (Bit 0) */ + #define R_MFWD_FWGC_SVM_Msk (0x3UL) /*!< SVM (Bitfield-Mask: 0x03) */ +/* ======================================================== FWTTC0 ========================================================= */ + #define R_MFWD_FWTTC0_CTT_Pos (0UL) /*!< CTT (Bit 0) */ + #define R_MFWD_FWTTC0_CTT_Msk (0xffffUL) /*!< CTT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTTC0_STT_Pos (16UL) /*!< STT (Bit 16) */ + #define R_MFWD_FWTTC0_STT_Msk (0xffff0000UL) /*!< STT (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWTTC1 ========================================================= */ + #define R_MFWD_FWTTC1_RTT_Pos (0UL) /*!< RTT (Bit 0) */ + #define R_MFWD_FWTTC1_RTT_Msk (0xffffUL) /*!< RTT (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWCEPTC ======================================================== */ + #define R_MFWD_FWCEPTC_EPCSD_Pos (0UL) /*!< EPCSD (Bit 0) */ + #define R_MFWD_FWCEPTC_EPCSD_Msk (0x7fUL) /*!< EPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCEPTC_EPIPV_Pos (12UL) /*!< EPIPV (Bit 12) */ + #define R_MFWD_FWCEPTC_EPIPV_Msk (0x7000UL) /*!< EPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCEPTC_EPCS_Pos (16UL) /*!< EPCS (Bit 16) */ + #define R_MFWD_FWCEPTC_EPCS_Msk (0x30000UL) /*!< EPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCEPTC_EPSL_Pos (24UL) /*!< EPSL (Bit 24) */ + #define R_MFWD_FWCEPTC_EPSL_Msk (0x1000000UL) /*!< EPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC0 ======================================================== */ + #define R_MFWD_FWCEPRC0_EPHYEEF_Pos (0UL) /*!< EPHYEEF (Bit 0) */ + #define R_MFWD_FWCEPRC0_EPHYEEF_Msk (0x1UL) /*!< EPHYEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EPCRCEEF_Pos (1UL) /*!< EPCRCEEF (Bit 1) */ + #define R_MFWD_FWCEPRC0_EPCRCEEF_Msk (0x2UL) /*!< EPCRCEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ENIBEEF_Pos (2UL) /*!< ENIBEEF (Bit 2) */ + #define R_MFWD_FWCEPRC0_ENIBEEF_Msk (0x4UL) /*!< ENIBEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EFCSEEF_Pos (3UL) /*!< EFCSEEF (Bit 3) */ + #define R_MFWD_FWCEPRC0_EFCSEEF_Msk (0x8UL) /*!< EFCSEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EFFMEEF_Pos (4UL) /*!< EFFMEEF (Bit 4) */ + #define R_MFWD_FWCEPRC0_EFFMEEF_Msk (0x10UL) /*!< EFFMEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ECFSEEF_Pos (5UL) /*!< ECFSEEF (Bit 5) */ + #define R_MFWD_FWCEPRC0_ECFSEEF_Msk (0x20UL) /*!< ECFSEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ECFFCEEF_Pos (6UL) /*!< ECFFCEEF (Bit 6) */ + #define R_MFWD_FWCEPRC0_ECFFCEEF_Msk (0x40UL) /*!< ECFFCEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ERFFEF_Pos (7UL) /*!< ERFFEF (Bit 7) */ + #define R_MFWD_FWCEPRC0_ERFFEF_Msk (0x80UL) /*!< ERFFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ERPOOEF_Pos (8UL) /*!< ERPOOEF (Bit 8) */ + #define R_MFWD_FWCEPRC0_ERPOOEF_Msk (0x100UL) /*!< ERPOOEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EBOEEF_Pos (9UL) /*!< EBOEEF (Bit 9) */ + #define R_MFWD_FWCEPRC0_EBOEEF_Msk (0x200UL) /*!< EBOEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EUEEF_Pos (10UL) /*!< EUEEF (Bit 10) */ + #define R_MFWD_FWCEPRC0_EUEEF_Msk (0x400UL) /*!< EUEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_EOEEF_Pos (11UL) /*!< EOEEF (Bit 11) */ + #define R_MFWD_FWCEPRC0_EOEEF_Msk (0x800UL) /*!< EOEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_ETFEF_Pos (12UL) /*!< ETFEF (Bit 12) */ + #define R_MFWD_FWCEPRC0_ETFEF_Msk (0x1000UL) /*!< ETFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GAREEEF_Pos (16UL) /*!< GAREEEF (Bit 16) */ + #define R_MFWD_FWCEPRC0_GAREEEF_Msk (0x10000UL) /*!< GAREEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GAXEEF_Pos (17UL) /*!< GAXEEF (Bit 17) */ + #define R_MFWD_FWCEPRC0_GAXEEF_Msk (0x20000UL) /*!< GAXEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GSEQEEF_Pos (18UL) /*!< GSEQEEF (Bit 18) */ + #define R_MFWD_FWCEPRC0_GSEQEEF_Msk (0x40000UL) /*!< GSEQEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GTFEF_Pos (20UL) /*!< GTFEF (Bit 20) */ + #define R_MFWD_FWCEPRC0_GTFEF_Msk (0x100000UL) /*!< GTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_GDNEEF_Pos (21UL) /*!< GDNEEF (Bit 21) */ + #define R_MFWD_FWCEPRC0_GDNEEF_Msk (0x200000UL) /*!< GDNEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_DDEEF_Pos (24UL) /*!< DDEEF (Bit 24) */ + #define R_MFWD_FWCEPRC0_DDEEF_Msk (0x1000000UL) /*!< DDEEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC0_DDFSFEF_Pos (26UL) /*!< DDFSFEF (Bit 26) */ + #define R_MFWD_FWCEPRC0_DDFSFEF_Msk (0x4000000UL) /*!< DDFSFEF (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC1 ======================================================== */ + #define R_MFWD_FWCEPRC1_FMSDUFEF_Pos (0UL) /*!< FMSDUFEF (Bit 0) */ + #define R_MFWD_FWCEPRC1_FMSDUFEF_Msk (0x1UL) /*!< FMSDUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FMTRFEF_Pos (2UL) /*!< FMTRFEF (Bit 2) */ + #define R_MFWD_FWCEPRC1_FMTRFEF_Msk (0x4UL) /*!< FMTRFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FIFFEF_Pos (8UL) /*!< FIFFEF (Bit 8) */ + #define R_MFWD_FWCEPRC1_FIFFEF_Msk (0x100UL) /*!< FIFFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC1_FSFFEF_Pos (9UL) /*!< FSFFEF (Bit 9) */ + #define R_MFWD_FWCEPRC1_FSFFEF_Msk (0x200UL) /*!< FSFFEF (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCEPRC2 ======================================================== */ + #define R_MFWD_FWCEPRC2_FLTHUFEF_Pos (0UL) /*!< FLTHUFEF (Bit 0) */ + #define R_MFWD_FWCEPRC2_FLTHUFEF_Msk (0x1UL) /*!< FLTHUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDMACUFEF_Pos (3UL) /*!< FDMACUFEF (Bit 3) */ + #define R_MFWD_FWCEPRC2_FDMACUFEF_Msk (0x8UL) /*!< FDMACUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FSMACUFEF_Pos (4UL) /*!< FSMACUFEF (Bit 4) */ + #define R_MFWD_FWCEPRC2_FSMACUFEF_Msk (0x10UL) /*!< FSMACUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FVLANUFEF_Pos (5UL) /*!< FVLANUFEF (Bit 5) */ + #define R_MFWD_FWCEPRC2_FVLANUFEF_Msk (0x20UL) /*!< FVLANUFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDDNTFEF_Pos (8UL) /*!< FDDNTFEF (Bit 8) */ + #define R_MFWD_FWCEPRC2_FDDNTFEF_Msk (0x100UL) /*!< FDDNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTHNTFEF_Pos (9UL) /*!< FLTHNTFEF (Bit 9) */ + #define R_MFWD_FWCEPRC2_FLTHNTFEF_Msk (0x200UL) /*!< FLTHNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTWNTFEF_Pos (11UL) /*!< FLTWNTFEF (Bit 11) */ + #define R_MFWD_FWCEPRC2_FLTWNTFEF_Msk (0x800UL) /*!< FLTWNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FPBNTFEF_Pos (12UL) /*!< FPBNTFEF (Bit 12) */ + #define R_MFWD_FWCEPRC2_FPBNTFEF_Msk (0x1000UL) /*!< FPBNTFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FLTHSLFEF_Pos (16UL) /*!< FLTHSLFEF (Bit 16) */ + #define R_MFWD_FWCEPRC2_FLTHSLFEF_Msk (0x10000UL) /*!< FLTHSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FDMACSLFEF_Pos (19UL) /*!< FDMACSLFEF (Bit 19) */ + #define R_MFWD_FWCEPRC2_FDMACSLFEF_Msk (0x80000UL) /*!< FDMACSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FSMACSLFEF_Pos (20UL) /*!< FSMACSLFEF (Bit 20) */ + #define R_MFWD_FWCEPRC2_FSMACSLFEF_Msk (0x100000UL) /*!< FSMACSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FVLANSLFEF_Pos (21UL) /*!< FVLANSLFEF (Bit 21) */ + #define R_MFWD_FWCEPRC2_FVLANSLFEF_Msk (0x200000UL) /*!< FVLANSLFEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCEPRC2_FWMFEF_Pos (26UL) /*!< FWMFEF (Bit 26) */ + #define R_MFWD_FWCEPRC2_FWMFEF_Msk (0x4000000UL) /*!< FWMFEF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCLPTC ======================================================== */ + #define R_MFWD_FWCLPTC_LPCSD_Pos (0UL) /*!< LPCSD (Bit 0) */ + #define R_MFWD_FWCLPTC_LPCSD_Msk (0x7fUL) /*!< LPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCLPTC_LPIPV_Pos (12UL) /*!< LPIPV (Bit 12) */ + #define R_MFWD_FWCLPTC_LPIPV_Msk (0x7000UL) /*!< LPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCLPTC_LPCS_Pos (16UL) /*!< LPCS (Bit 16) */ + #define R_MFWD_FWCLPTC_LPCS_Msk (0x30000UL) /*!< LPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCLPTC_LPSL_Pos (24UL) /*!< LPSL (Bit 24) */ + #define R_MFWD_FWCLPTC_LPSL_Msk (0x1000000UL) /*!< LPSL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCLPRC ======================================================== */ + #define R_MFWD_FWCLPRC_USIDLF_Pos (0UL) /*!< USIDLF (Bit 0) */ + #define R_MFWD_FWCLPRC_USIDLF_Msk (0x1UL) /*!< USIDLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UDMACLF_Pos (4UL) /*!< UDMACLF (Bit 4) */ + #define R_MFWD_FWCLPRC_UDMACLF_Msk (0x10UL) /*!< UDMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_USMACLF_Pos (5UL) /*!< USMACLF (Bit 5) */ + #define R_MFWD_FWCLPRC_USMACLF_Msk (0x20UL) /*!< USMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UPSMACLF_Pos (6UL) /*!< UPSMACLF (Bit 6) */ + #define R_MFWD_FWCLPRC_UPSMACLF_Msk (0x40UL) /*!< UPSMACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCLPRC_UVLANLF_Pos (7UL) /*!< UVLANLF (Bit 7) */ + #define R_MFWD_FWCLPRC_UVLANLF_Msk (0x80UL) /*!< UVLANLF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWCMPTC ======================================================== */ + #define R_MFWD_FWCMPTC_CMPCSD_Pos (0UL) /*!< CMPCSD (Bit 0) */ + #define R_MFWD_FWCMPTC_CMPCSD_Msk (0x7fUL) /*!< CMPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCMPTC_CMPIPV_Pos (12UL) /*!< CMPIPV (Bit 12) */ + #define R_MFWD_FWCMPTC_CMPIPV_Msk (0x7000UL) /*!< CMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCMPTC_CMPIPU_Pos (15UL) /*!< CMPIPU (Bit 15) */ + #define R_MFWD_FWCMPTC_CMPIPU_Msk (0x8000UL) /*!< CMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCMPTC_CMPCS_Pos (16UL) /*!< CMPCS (Bit 16) */ + #define R_MFWD_FWCMPTC_CMPCS_Msk (0x30000UL) /*!< CMPCS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCMPTC_CMPSL_Pos (24UL) /*!< CMPSL (Bit 24) */ + #define R_MFWD_FWCMPTC_CMPSL_Msk (0x1000000UL) /*!< CMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEMPTC ======================================================== */ + #define R_MFWD_FWEMPTC_EMPIPV_Pos (12UL) /*!< EMPIPV (Bit 12) */ + #define R_MFWD_FWEMPTC_EMPIPV_Msk (0x7000UL) /*!< EMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWEMPTC_EMPIPU_Pos (15UL) /*!< EMPIPU (Bit 15) */ + #define R_MFWD_FWEMPTC_EMPIPU_Msk (0x8000UL) /*!< EMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEMPTC_EMPPS_Pos (16UL) /*!< EMPPS (Bit 16) */ + #define R_MFWD_FWEMPTC_EMPPS_Msk (0x30000UL) /*!< EMPPS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWEMPTC_EMPSL_Pos (24UL) /*!< EMPSL (Bit 24) */ + #define R_MFWD_FWEMPTC_EMPSL_Msk (0x1000000UL) /*!< EMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSDMPTC ======================================================== */ + #define R_MFWD_FWSDMPTC_SDMPCSD_Pos (0UL) /*!< SDMPCSD (Bit 0) */ + #define R_MFWD_FWSDMPTC_SDMPCSD_Msk (0x7fUL) /*!< SDMPCSD (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWSDMPTC_SDMPIPV_Pos (12UL) /*!< SDMPIPV (Bit 12) */ + #define R_MFWD_FWSDMPTC_SDMPIPV_Msk (0x7000UL) /*!< SDMPIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWSDMPTC_SDMPIPU_Pos (15UL) /*!< SDMPIPU (Bit 15) */ + #define R_MFWD_FWSDMPTC_SDMPIPU_Msk (0x8000UL) /*!< SDMPIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSDMPTC_SDMPPS_Pos (16UL) /*!< SDMPPS (Bit 16) */ + #define R_MFWD_FWSDMPTC_SDMPPS_Msk (0x30000UL) /*!< SDMPPS (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWSDMPTC_SDMPSL_Pos (24UL) /*!< SDMPSL (Bit 24) */ + #define R_MFWD_FWSDMPTC_SDMPSL_Msk (0x1000000UL) /*!< SDMPSL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSDMPVC ======================================================== */ + #define R_MFWD_FWSDMPVC_SDMDV_Pos (0UL) /*!< SDMDV (Bit 0) */ + #define R_MFWD_FWSDMPVC_SDMDV_Msk (0x7fUL) /*!< SDMDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWSDMPVC_SDMSV_Pos (16UL) /*!< SDMSV (Bit 16) */ + #define R_MFWD_FWSDMPVC_SDMSV_Msk (0x7f0000UL) /*!< SDMSV (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLBWMC0 ======================================================== */ + #define R_MFWD_FWLBWMC0_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC0_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC0_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC0_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWLBWMC1 ======================================================== */ + #define R_MFWD_FWLBWMC1_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC1_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC1_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC1_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWLBWMC2 ======================================================== */ + #define R_MFWD_FWLBWMC2_WMCLPR_Pos (0UL) /*!< WMCLPR (Bit 0) */ + #define R_MFWD_FWLBWMC2_WMCLPR_Msk (0xffffUL) /*!< WMCLPR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWLBWMC2_WMFLPR_Pos (16UL) /*!< WMFLPR (Bit 16) */ + #define R_MFWD_FWLBWMC2_WMFLPR_Msk (0xffff0000UL) /*!< WMFLPR (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWPC00 ========================================================= */ + #define R_MFWD_FWPC00_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC00_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC00_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC00_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC00_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC00_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC00_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC00_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC00_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC00_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC00_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC00_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC00_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC00_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC00_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC00_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC00_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC00_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC00_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC00_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC00_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC00_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC00_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC01 ========================================================= */ + #define R_MFWD_FWPC01_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC01_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC01_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC01_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC01_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC01_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC01_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC01_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC01_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC01_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC01_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC01_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC01_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC01_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC01_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC01_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC01_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC01_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC01_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC01_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC01_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC01_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC01_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC02 ========================================================= */ + #define R_MFWD_FWPC02_LTHTA_Pos (0UL) /*!< LTHTA (Bit 0) */ + #define R_MFWD_FWPC02_LTHTA_Msk (0x1UL) /*!< LTHTA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_LTHRUS_Pos (1UL) /*!< LTHRUS (Bit 1) */ + #define R_MFWD_FWPC02_LTHRUS_Msk (0x2UL) /*!< LTHRUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_LTHRUSS_Pos (2UL) /*!< LTHRUSS (Bit 2) */ + #define R_MFWD_FWPC02_LTHRUSS_Msk (0x4UL) /*!< LTHRUSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4UE_Pos (3UL) /*!< IP4UE (Bit 3) */ + #define R_MFWD_FWPC02_IP4UE_Msk (0x8UL) /*!< IP4UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4TE_Pos (4UL) /*!< IP4TE (Bit 4) */ + #define R_MFWD_FWPC02_IP4TE_Msk (0x10UL) /*!< IP4TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP4OE_Pos (5UL) /*!< IP4OE (Bit 5) */ + #define R_MFWD_FWPC02_IP4OE_Msk (0x20UL) /*!< IP4OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6UE_Pos (6UL) /*!< IP6UE (Bit 6) */ + #define R_MFWD_FWPC02_IP6UE_Msk (0x40UL) /*!< IP6UE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6TE_Pos (7UL) /*!< IP6TE (Bit 7) */ + #define R_MFWD_FWPC02_IP6TE_Msk (0x80UL) /*!< IP6TE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_IP6OE_Pos (8UL) /*!< IP6OE (Bit 8) */ + #define R_MFWD_FWPC02_IP6OE_Msk (0x100UL) /*!< IP6OE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_L2SE_Pos (9UL) /*!< L2SE (Bit 9) */ + #define R_MFWD_FWPC02_L2SE_Msk (0x200UL) /*!< L2SE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACDSA_Pos (20UL) /*!< MACDSA (Bit 20) */ + #define R_MFWD_FWPC02_MACDSA_Msk (0x100000UL) /*!< MACDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUDA_Pos (21UL) /*!< MACRUDA (Bit 21) */ + #define R_MFWD_FWPC02_MACRUDA_Msk (0x200000UL) /*!< MACRUDA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUDSA_Pos (22UL) /*!< MACRUDSA (Bit 22) */ + #define R_MFWD_FWPC02_MACRUDSA_Msk (0x400000UL) /*!< MACRUDSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACSSA_Pos (23UL) /*!< MACSSA (Bit 23) */ + #define R_MFWD_FWPC02_MACSSA_Msk (0x800000UL) /*!< MACSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUSA_Pos (24UL) /*!< MACRUSA (Bit 24) */ + #define R_MFWD_FWPC02_MACRUSA_Msk (0x1000000UL) /*!< MACRUSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACRUSSA_Pos (25UL) /*!< MACRUSSA (Bit 25) */ + #define R_MFWD_FWPC02_MACRUSSA_Msk (0x2000000UL) /*!< MACRUSSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACHLA_Pos (26UL) /*!< MACHLA (Bit 26) */ + #define R_MFWD_FWPC02_MACHLA_Msk (0x4000000UL) /*!< MACHLA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_MACHMA_Pos (27UL) /*!< MACHMA (Bit 27) */ + #define R_MFWD_FWPC02_MACHMA_Msk (0x8000000UL) /*!< MACHMA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANSA_Pos (28UL) /*!< VLANSA (Bit 28) */ + #define R_MFWD_FWPC02_VLANSA_Msk (0x10000000UL) /*!< VLANSA (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANRU_Pos (29UL) /*!< VLANRU (Bit 29) */ + #define R_MFWD_FWPC02_VLANRU_Msk (0x20000000UL) /*!< VLANRU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC02_VLANRUS_Pos (30UL) /*!< VLANRUS (Bit 30) */ + #define R_MFWD_FWPC02_VLANRUS_Msk (0x40000000UL) /*!< VLANRUS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPC10 ========================================================= */ + #define R_MFWD_FWPC10_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC10_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC10_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC10_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC10_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC10_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC11 ========================================================= */ + #define R_MFWD_FWPC11_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC11_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC11_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC11_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC11_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC11_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC12 ========================================================= */ + #define R_MFWD_FWPC12_DDE_Pos (0UL) /*!< DDE (Bit 0) */ + #define R_MFWD_FWPC12_DDE_Msk (0x1UL) /*!< DDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC12_DDSL_Pos (1UL) /*!< DDSL (Bit 1) */ + #define R_MFWD_FWPC12_DDSL_Msk (0x2UL) /*!< DDSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPC12_LTHFM_Pos (16UL) /*!< LTHFM (Bit 16) */ + #define R_MFWD_FWPC12_LTHFM_Msk (0x7f0000UL) /*!< LTHFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC20 ========================================================= */ + #define R_MFWD_FWPC20_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC20_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC21 ========================================================= */ + #define R_MFWD_FWPC21_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC21_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWPC22 ========================================================= */ + #define R_MFWD_FWPC22_LTWFM_Pos (16UL) /*!< LTWFM (Bit 16) */ + #define R_MFWD_FWPC22_LTWFM_Msk (0x7f0000UL) /*!< LTWFM (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTGC00 ======================================================== */ + #define R_MFWD_FWCTGC00_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC00_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC00_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC00_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC00_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC00_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC00_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC00_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC00_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC00_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC00_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC00_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC00_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC00_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC00_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC01 ======================================================== */ + #define R_MFWD_FWCTGC01_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC01_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC01_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC01_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC01_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC01_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC01_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC01_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC01_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC01_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC01_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC01_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC01_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC01_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC01_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC02 ======================================================== */ + #define R_MFWD_FWCTGC02_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC02_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC02_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC02_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC02_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC02_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC02_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC02_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC02_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC02_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC02_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC02_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC02_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC02_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC02_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC03 ======================================================== */ + #define R_MFWD_FWCTGC03_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC03_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC03_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC03_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC03_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC03_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC03_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC03_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC03_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC03_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC03_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC03_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC03_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC03_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC03_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC04 ======================================================== */ + #define R_MFWD_FWCTGC04_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC04_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC04_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC04_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC04_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC04_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC04_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC04_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC04_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC04_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC04_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC04_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC04_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC04_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC04_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC05 ======================================================== */ + #define R_MFWD_FWCTGC05_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC05_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC05_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC05_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC05_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC05_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC05_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC05_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC05_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC05_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC05_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC05_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC05_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC05_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC05_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC06 ======================================================== */ + #define R_MFWD_FWCTGC06_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC06_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC06_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC06_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC06_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC06_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC06_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC06_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC06_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC06_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC06_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC06_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC06_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC06_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC06_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC07 ======================================================== */ + #define R_MFWD_FWCTGC07_CTMDE_Pos (0UL) /*!< CTMDE (Bit 0) */ + #define R_MFWD_FWCTGC07_CTMDE_Msk (0x1UL) /*!< CTMDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTMSE_Pos (1UL) /*!< CTMSE (Bit 1) */ + #define R_MFWD_FWCTGC07_CTMSE_Msk (0x2UL) /*!< CTMSE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCVE_Pos (2UL) /*!< CTCVE (Bit 2) */ + #define R_MFWD_FWCTGC07_CTCVE_Msk (0x4UL) /*!< CTCVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCPE_Pos (3UL) /*!< CTCPE (Bit 3) */ + #define R_MFWD_FWCTGC07_CTCPE_Msk (0x8UL) /*!< CTCPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTCDE_Pos (4UL) /*!< CTCDE (Bit 4) */ + #define R_MFWD_FWCTGC07_CTCDE_Msk (0x10UL) /*!< CTCDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSVE_Pos (5UL) /*!< CTSVE (Bit 5) */ + #define R_MFWD_FWCTGC07_CTSVE_Msk (0x20UL) /*!< CTSVE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSPE_Pos (6UL) /*!< CTSPE (Bit 6) */ + #define R_MFWD_FWCTGC07_CTSPE_Msk (0x40UL) /*!< CTSPE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTSDE_Pos (7UL) /*!< CTSDE (Bit 7) */ + #define R_MFWD_FWCTGC07_CTSDE_Msk (0x80UL) /*!< CTSDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTETE_Pos (8UL) /*!< CTETE (Bit 8) */ + #define R_MFWD_FWCTGC07_CTETE_Msk (0x100UL) /*!< CTETE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTFI_Pos (11UL) /*!< CTFI (Bit 11) */ + #define R_MFWD_FWCTGC07_CTFI_Msk (0x800UL) /*!< CTFI (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTGC07_CTVCTRL_Pos (12UL) /*!< CTVCTRL (Bit 12) */ + #define R_MFWD_FWCTGC07_CTVCTRL_Msk (0x3000UL) /*!< CTVCTRL (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWCTGC07_CTRTGI_Pos (14UL) /*!< CTRTGI (Bit 14) */ + #define R_MFWD_FWCTGC07_CTRTGI_Msk (0x4000UL) /*!< CTRTGI (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTGC10 ======================================================== */ + #define R_MFWD_FWCTGC10_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC10_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC11 ======================================================== */ + #define R_MFWD_FWCTGC11_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC11_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC12 ======================================================== */ + #define R_MFWD_FWCTGC12_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC12_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC13 ======================================================== */ + #define R_MFWD_FWCTGC13_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC13_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC14 ======================================================== */ + #define R_MFWD_FWCTGC14_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC14_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC15 ======================================================== */ + #define R_MFWD_FWCTGC15_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC15_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC16 ======================================================== */ + #define R_MFWD_FWCTGC16_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC16_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTGC17 ======================================================== */ + #define R_MFWD_FWCTGC17_CTMT_Pos (0UL) /*!< CTMT (Bit 0) */ + #define R_MFWD_FWCTGC17_CTMT_Msk (0x3ffffffUL) /*!< CTMT (Bitfield-Mask: 0x3ffffff) */ +/* ======================================================= FWCTTC00 ======================================================== */ + #define R_MFWD_FWCTTC00_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC00_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC00_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC00_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC01 ======================================================== */ + #define R_MFWD_FWCTTC01_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC01_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC01_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC01_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC02 ======================================================== */ + #define R_MFWD_FWCTTC02_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC02_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC02_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC02_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC03 ======================================================== */ + #define R_MFWD_FWCTTC03_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC03_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC03_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC03_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC04 ======================================================== */ + #define R_MFWD_FWCTTC04_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC04_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC04_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC04_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC05 ======================================================== */ + #define R_MFWD_FWCTTC05_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC05_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC05_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC05_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC06 ======================================================== */ + #define R_MFWD_FWCTTC06_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC06_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC06_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC06_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC07 ======================================================== */ + #define R_MFWD_FWCTTC07_CTDV_Pos (0UL) /*!< CTDV (Bit 0) */ + #define R_MFWD_FWCTTC07_CTDV_Msk (0x7fUL) /*!< CTDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCTTC07_CTDFM_Pos (16UL) /*!< CTDFM (Bit 16) */ + #define R_MFWD_FWCTTC07_CTDFM_Msk (0xf0000UL) /*!< CTDFM (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCTTC10 ======================================================== */ + #define R_MFWD_FWCTTC10_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC10_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC10_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC10_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC10_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC10_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC10_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC10_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC11 ======================================================== */ + #define R_MFWD_FWCTTC11_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC11_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC11_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC11_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC11_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC11_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC11_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC11_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC12 ======================================================== */ + #define R_MFWD_FWCTTC12_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC12_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC12_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC12_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC12_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC12_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC12_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC12_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC13 ======================================================== */ + #define R_MFWD_FWCTTC13_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC13_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC13_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC13_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC13_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC13_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC13_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC13_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC14 ======================================================== */ + #define R_MFWD_FWCTTC14_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC14_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC14_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC14_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC14_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC14_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC14_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC14_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC15 ======================================================== */ + #define R_MFWD_FWCTTC15_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC15_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC15_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC15_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC15_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC15_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC15_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC15_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC16 ======================================================== */ + #define R_MFWD_FWCTTC16_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC16_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC16_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC16_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC16_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC16_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC16_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC16_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC17 ======================================================== */ + #define R_MFWD_FWCTTC17_CTIPV_Pos (12UL) /*!< CTIPV (Bit 12) */ + #define R_MFWD_FWCTTC17_CTIPV_Msk (0x7000UL) /*!< CTIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTTC17_CTIPU_Pos (15UL) /*!< CTIPU (Bit 15) */ + #define R_MFWD_FWCTTC17_CTIPU_Msk (0x8000UL) /*!< CTIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC17_CTCME_Pos (16UL) /*!< CTCME (Bit 16) */ + #define R_MFWD_FWCTTC17_CTCME_Msk (0x10000UL) /*!< CTCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTTC17_CTEME_Pos (17UL) /*!< CTEME (Bit 17) */ + #define R_MFWD_FWCTTC17_CTEME_Msk (0x20000UL) /*!< CTEME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTTC200 ======================================================= */ + #define R_MFWD_FWCTTC200_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC200_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC201 ======================================================= */ + #define R_MFWD_FWCTTC201_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC201_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC202 ======================================================= */ + #define R_MFWD_FWCTTC202_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC202_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC203 ======================================================= */ + #define R_MFWD_FWCTTC203_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC203_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC204 ======================================================= */ + #define R_MFWD_FWCTTC204_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC204_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC205 ======================================================= */ + #define R_MFWD_FWCTTC205_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC205_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC206 ======================================================= */ + #define R_MFWD_FWCTTC206_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC206_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTTC207 ======================================================= */ + #define R_MFWD_FWCTTC207_CTCSD_Pos (0UL) /*!< CTCSD (Bit 0) */ + #define R_MFWD_FWCTTC207_CTCSD_Msk (0x7fUL) /*!< CTCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWCTSC00 ======================================================== */ + #define R_MFWD_FWCTSC00_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC00_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC01 ======================================================== */ + #define R_MFWD_FWCTSC01_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC01_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC02 ======================================================== */ + #define R_MFWD_FWCTSC02_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC02_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC03 ======================================================== */ + #define R_MFWD_FWCTSC03_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC03_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC04 ======================================================== */ + #define R_MFWD_FWCTSC04_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC04_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC05 ======================================================== */ + #define R_MFWD_FWCTSC05_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC05_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC06 ======================================================== */ + #define R_MFWD_FWCTSC06_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC06_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC07 ======================================================== */ + #define R_MFWD_FWCTSC07_CTDMAU_Pos (0UL) /*!< CTDMAU (Bit 0) */ + #define R_MFWD_FWCTSC07_CTDMAU_Msk (0xffffffffUL) /*!< CTDMAU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC10 ======================================================== */ + #define R_MFWD_FWCTSC10_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC10_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC10_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC10_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC11 ======================================================== */ + #define R_MFWD_FWCTSC11_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC11_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC11_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC11_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC12 ======================================================== */ + #define R_MFWD_FWCTSC12_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC12_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC12_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC12_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC13 ======================================================== */ + #define R_MFWD_FWCTSC13_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC13_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC13_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC13_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC14 ======================================================== */ + #define R_MFWD_FWCTSC14_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC14_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC14_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC14_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC15 ======================================================== */ + #define R_MFWD_FWCTSC15_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC15_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC15_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC15_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC16 ======================================================== */ + #define R_MFWD_FWCTSC16_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC16_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC16_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC16_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC17 ======================================================== */ + #define R_MFWD_FWCTSC17_CTSMAU_Pos (0UL) /*!< CTSMAU (Bit 0) */ + #define R_MFWD_FWCTSC17_CTSMAU_Msk (0xffffUL) /*!< CTSMAU (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC17_CTDMAL_Pos (16UL) /*!< CTDMAL (Bit 16) */ + #define R_MFWD_FWCTSC17_CTDMAL_Msk (0xffff0000UL) /*!< CTDMAL (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTSC20 ======================================================== */ + #define R_MFWD_FWCTSC20_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC20_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC21 ======================================================== */ + #define R_MFWD_FWCTSC21_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC21_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC22 ======================================================== */ + #define R_MFWD_FWCTSC22_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC22_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC23 ======================================================== */ + #define R_MFWD_FWCTSC23_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC23_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC24 ======================================================== */ + #define R_MFWD_FWCTSC24_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC24_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC25 ======================================================== */ + #define R_MFWD_FWCTSC25_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC25_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC26 ======================================================== */ + #define R_MFWD_FWCTSC26_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC26_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC27 ======================================================== */ + #define R_MFWD_FWCTSC27_CTSMAL_Pos (0UL) /*!< CTSMAL (Bit 0) */ + #define R_MFWD_FWCTSC27_CTSMAL_Msk (0xffffffffUL) /*!< CTSMAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTSC30 ======================================================== */ + #define R_MFWD_FWCTSC30_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC30_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC30_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC30_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC30_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC30_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC30_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC30_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC30_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC30_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC30_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC30_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC31 ======================================================== */ + #define R_MFWD_FWCTSC31_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC31_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC31_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC31_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC31_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC31_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC31_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC31_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC31_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC31_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC31_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC31_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC32 ======================================================== */ + #define R_MFWD_FWCTSC32_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC32_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC32_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC32_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC32_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC32_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC32_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC32_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC32_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC32_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC32_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC32_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC33 ======================================================== */ + #define R_MFWD_FWCTSC33_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC33_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC33_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC33_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC33_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC33_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC33_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC33_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC33_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC33_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC33_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC33_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC34 ======================================================== */ + #define R_MFWD_FWCTSC34_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC34_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC34_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC34_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC34_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC34_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC34_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC34_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC34_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC34_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC34_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC34_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC35 ======================================================== */ + #define R_MFWD_FWCTSC35_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC35_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC35_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC35_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC35_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC35_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC35_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC35_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC35_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC35_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC35_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC35_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC36 ======================================================== */ + #define R_MFWD_FWCTSC36_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC36_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC36_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC36_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC36_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC36_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC36_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC36_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC36_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC36_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC36_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC36_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC37 ======================================================== */ + #define R_MFWD_FWCTSC37_CTCV_Pos (0UL) /*!< CTCV (Bit 0) */ + #define R_MFWD_FWCTSC37_CTCV_Msk (0xfffUL) /*!< CTCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC37_CTCP_Pos (12UL) /*!< CTCP (Bit 12) */ + #define R_MFWD_FWCTSC37_CTCP_Msk (0x7000UL) /*!< CTCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC37_CTCD_Pos (15UL) /*!< CTCD (Bit 15) */ + #define R_MFWD_FWCTSC37_CTCD_Msk (0x8000UL) /*!< CTCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWCTSC37_CTSV_Pos (16UL) /*!< CTSV (Bit 16) */ + #define R_MFWD_FWCTSC37_CTSV_Msk (0xfff0000UL) /*!< CTSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWCTSC37_CTSP_Pos (28UL) /*!< CTSP (Bit 28) */ + #define R_MFWD_FWCTSC37_CTSP_Msk (0x70000000UL) /*!< CTSP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWCTSC37_CTSD_Pos (31UL) /*!< CTSD (Bit 31) */ + #define R_MFWD_FWCTSC37_CTSD_Msk (0x80000000UL) /*!< CTSD (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCTSC40 ======================================================== */ + #define R_MFWD_FWCTSC40_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC40_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC40_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC40_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC41 ======================================================== */ + #define R_MFWD_FWCTSC41_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC41_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC41_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC41_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC42 ======================================================== */ + #define R_MFWD_FWCTSC42_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC42_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC42_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC42_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC43 ======================================================== */ + #define R_MFWD_FWCTSC43_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC43_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC43_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC43_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC44 ======================================================== */ + #define R_MFWD_FWCTSC44_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC44_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC44_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC44_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC45 ======================================================== */ + #define R_MFWD_FWCTSC45_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC45_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC45_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC45_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC46 ======================================================== */ + #define R_MFWD_FWCTSC46_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC46_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC46_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC46_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWCTSC47 ======================================================== */ + #define R_MFWD_FWCTSC47_CTET_Pos (0UL) /*!< CTET (Bit 0) */ + #define R_MFWD_FWCTSC47_CTET_Msk (0xffffUL) /*!< CTET (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWCTSC47_CTSPN_Pos (16UL) /*!< CTSPN (Bit 16) */ + #define R_MFWD_FWCTSC47_CTSPN_Msk (0x30000UL) /*!< CTSPN (Bitfield-Mask: 0x03) */ +/* ======================================================= FWTWBFC0 ======================================================== */ + #define R_MFWD_FWTWBFC0_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC0_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC0_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC0_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC0_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC0_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC1 ======================================================== */ + #define R_MFWD_FWTWBFC1_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC1_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC1_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC1_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC1_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC1_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC2 ======================================================== */ + #define R_MFWD_FWTWBFC2_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC2_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC2_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC2_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC2_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC2_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC3 ======================================================== */ + #define R_MFWD_FWTWBFC3_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC3_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC3_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC3_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC3_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC3_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC4 ======================================================== */ + #define R_MFWD_FWTWBFC4_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC4_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC4_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC4_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC4_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC4_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC5 ======================================================== */ + #define R_MFWD_FWTWBFC5_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC5_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC5_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC5_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC5_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC5_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC6 ======================================================== */ + #define R_MFWD_FWTWBFC6_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC6_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC6_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC6_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC6_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC6_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC7 ======================================================== */ + #define R_MFWD_FWTWBFC7_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC7_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC7_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC7_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC7_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC7_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC8 ======================================================== */ + #define R_MFWD_FWTWBFC8_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC8_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC8_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC8_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC8_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC8_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC9 ======================================================== */ + #define R_MFWD_FWTWBFC9_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC9_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC9_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC9_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC9_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC9_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC10 ======================================================= */ + #define R_MFWD_FWTWBFC10_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC10_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC10_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC10_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC10_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC10_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC11 ======================================================= */ + #define R_MFWD_FWTWBFC11_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC11_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC11_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC11_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC11_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC11_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC12 ======================================================= */ + #define R_MFWD_FWTWBFC12_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC12_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC12_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC12_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC12_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC12_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC13 ======================================================= */ + #define R_MFWD_FWTWBFC13_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC13_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC13_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC13_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC13_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC13_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC14 ======================================================= */ + #define R_MFWD_FWTWBFC14_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC14_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC14_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC14_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC14_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC14_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFC15 ======================================================= */ + #define R_MFWD_FWTWBFC15_TWBFUM_Pos (0UL) /*!< TWBFUM (Bit 0) */ + #define R_MFWD_FWTWBFC15_TWBFUM_Msk (0x3UL) /*!< TWBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTWBFC15_TWBFM_Pos (8UL) /*!< TWBFM (Bit 8) */ + #define R_MFWD_FWTWBFC15_TWBFM_Msk (0x100UL) /*!< TWBFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWTWBFC15_TWBFOV_Pos (16UL) /*!< TWBFOV (Bit 16) */ + #define R_MFWD_FWTWBFC15_TWBFOV_Msk (0xff0000UL) /*!< TWBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTWBFVC0 ======================================================= */ + #define R_MFWD_FWTWBFVC0_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC0_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC0_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC0_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC1 ======================================================= */ + #define R_MFWD_FWTWBFVC1_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC1_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC1_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC1_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC2 ======================================================= */ + #define R_MFWD_FWTWBFVC2_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC2_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC2_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC2_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC3 ======================================================= */ + #define R_MFWD_FWTWBFVC3_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC3_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC3_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC3_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC4 ======================================================= */ + #define R_MFWD_FWTWBFVC4_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC4_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC4_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC4_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC5 ======================================================= */ + #define R_MFWD_FWTWBFVC5_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC5_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC5_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC5_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC6 ======================================================= */ + #define R_MFWD_FWTWBFVC6_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC6_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC6_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC6_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC7 ======================================================= */ + #define R_MFWD_FWTWBFVC7_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC7_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC7_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC7_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC8 ======================================================= */ + #define R_MFWD_FWTWBFVC8_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC8_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC8_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC8_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTWBFVC9 ======================================================= */ + #define R_MFWD_FWTWBFVC9_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC9_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC9_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC9_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC10 ======================================================= */ + #define R_MFWD_FWTWBFVC10_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC10_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC10_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC10_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC11 ======================================================= */ + #define R_MFWD_FWTWBFVC11_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC11_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC11_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC11_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC12 ======================================================= */ + #define R_MFWD_FWTWBFVC12_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC12_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC12_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC12_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC13 ======================================================= */ + #define R_MFWD_FWTWBFVC13_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC13_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC13_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC13_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC14 ======================================================= */ + #define R_MFWD_FWTWBFVC14_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC14_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC14_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC14_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWTWBFVC15 ======================================================= */ + #define R_MFWD_FWTWBFVC15_TWBFV0_Pos (0UL) /*!< TWBFV0 (Bit 0) */ + #define R_MFWD_FWTWBFVC15_TWBFV0_Msk (0xffffUL) /*!< TWBFV0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWTWBFVC15_TWBFV1_Pos (16UL) /*!< TWBFV1 (Bit 16) */ + #define R_MFWD_FWTWBFVC15_TWBFV1_Msk (0xffff0000UL) /*!< TWBFV1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWTHBFC0 ======================================================== */ + #define R_MFWD_FWTHBFC0_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC0_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC0_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC0_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC1 ======================================================== */ + #define R_MFWD_FWTHBFC1_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC1_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC1_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC1_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC2 ======================================================== */ + #define R_MFWD_FWTHBFC2_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC2_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC2_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC2_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC3 ======================================================== */ + #define R_MFWD_FWTHBFC3_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC3_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC3_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC3_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC4 ======================================================== */ + #define R_MFWD_FWTHBFC4_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC4_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC4_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC4_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC5 ======================================================== */ + #define R_MFWD_FWTHBFC5_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC5_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC5_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC5_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC6 ======================================================== */ + #define R_MFWD_FWTHBFC6_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC6_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC6_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC6_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC7 ======================================================== */ + #define R_MFWD_FWTHBFC7_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC7_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC7_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC7_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC8 ======================================================== */ + #define R_MFWD_FWTHBFC8_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC8_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC8_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC8_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC9 ======================================================== */ + #define R_MFWD_FWTHBFC9_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC9_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC9_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC9_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC10 ======================================================= */ + #define R_MFWD_FWTHBFC10_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC10_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC10_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC10_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC11 ======================================================= */ + #define R_MFWD_FWTHBFC11_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC11_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC11_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC11_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC12 ======================================================= */ + #define R_MFWD_FWTHBFC12_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC12_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC12_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC12_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC13 ======================================================= */ + #define R_MFWD_FWTHBFC13_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC13_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC13_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC13_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC14 ======================================================= */ + #define R_MFWD_FWTHBFC14_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC14_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC14_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC14_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWTHBFC15 ======================================================= */ + #define R_MFWD_FWTHBFC15_THBFUM_Pos (0UL) /*!< THBFUM (Bit 0) */ + #define R_MFWD_FWTHBFC15_THBFUM_Msk (0x3UL) /*!< THBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWTHBFC15_THBFOV_Pos (16UL) /*!< THBFOV (Bit 16) */ + #define R_MFWD_FWTHBFC15_THBFOV_Msk (0xff0000UL) /*!< THBFOV (Bitfield-Mask: 0xff) */ +/* ====================================================== FWTHBFV0C0 ======================================================= */ + #define R_MFWD_FWTHBFV0C0_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C0_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C1 ======================================================= */ + #define R_MFWD_FWTHBFV0C1_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C1_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C2 ======================================================= */ + #define R_MFWD_FWTHBFV0C2_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C2_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C3 ======================================================= */ + #define R_MFWD_FWTHBFV0C3_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C3_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C4 ======================================================= */ + #define R_MFWD_FWTHBFV0C4_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C4_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C5 ======================================================= */ + #define R_MFWD_FWTHBFV0C5_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C5_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C6 ======================================================= */ + #define R_MFWD_FWTHBFV0C6_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C6_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C7 ======================================================= */ + #define R_MFWD_FWTHBFV0C7_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C7_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C8 ======================================================= */ + #define R_MFWD_FWTHBFV0C8_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C8_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C9 ======================================================= */ + #define R_MFWD_FWTHBFV0C9_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C9_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C10 ====================================================== */ + #define R_MFWD_FWTHBFV0C10_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C10_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C11 ====================================================== */ + #define R_MFWD_FWTHBFV0C11_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C11_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C12 ====================================================== */ + #define R_MFWD_FWTHBFV0C12_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C12_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C13 ====================================================== */ + #define R_MFWD_FWTHBFV0C13_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C13_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C14 ====================================================== */ + #define R_MFWD_FWTHBFV0C14_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C14_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV0C15 ====================================================== */ + #define R_MFWD_FWTHBFV0C15_THBFV0_Pos (0UL) /*!< THBFV0 (Bit 0) */ + #define R_MFWD_FWTHBFV0C15_THBFV0_Msk (0xffffffUL) /*!< THBFV0 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C0 ======================================================= */ + #define R_MFWD_FWTHBFV1C0_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C0_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C1 ======================================================= */ + #define R_MFWD_FWTHBFV1C1_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C1_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C2 ======================================================= */ + #define R_MFWD_FWTHBFV1C2_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C2_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C3 ======================================================= */ + #define R_MFWD_FWTHBFV1C3_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C3_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C4 ======================================================= */ + #define R_MFWD_FWTHBFV1C4_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C4_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C5 ======================================================= */ + #define R_MFWD_FWTHBFV1C5_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C5_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C6 ======================================================= */ + #define R_MFWD_FWTHBFV1C6_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C6_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C7 ======================================================= */ + #define R_MFWD_FWTHBFV1C7_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C7_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C8 ======================================================= */ + #define R_MFWD_FWTHBFV1C8_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C8_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C9 ======================================================= */ + #define R_MFWD_FWTHBFV1C9_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C9_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C10 ====================================================== */ + #define R_MFWD_FWTHBFV1C10_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C10_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C11 ====================================================== */ + #define R_MFWD_FWTHBFV1C11_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C11_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C12 ====================================================== */ + #define R_MFWD_FWTHBFV1C12_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C12_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C13 ====================================================== */ + #define R_MFWD_FWTHBFV1C13_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C13_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C14 ====================================================== */ + #define R_MFWD_FWTHBFV1C14_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C14_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ====================================================== FWTHBFV1C15 ====================================================== */ + #define R_MFWD_FWTHBFV1C15_THBFV1_Pos (0UL) /*!< THBFV1 (Bit 0) */ + #define R_MFWD_FWTHBFV1C15_THBFV1_Msk (0xffffffUL) /*!< THBFV1 (Bitfield-Mask: 0xffffff) */ +/* ======================================================= FWFOBFC0 ======================================================== */ + #define R_MFWD_FWFOBFC0_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC0_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC0_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC0_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC1 ======================================================== */ + #define R_MFWD_FWFOBFC1_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC1_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC1_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC1_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC2 ======================================================== */ + #define R_MFWD_FWFOBFC2_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC2_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC2_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC2_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC3 ======================================================== */ + #define R_MFWD_FWFOBFC3_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC3_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC3_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC3_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC4 ======================================================== */ + #define R_MFWD_FWFOBFC4_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC4_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC4_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC4_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC5 ======================================================== */ + #define R_MFWD_FWFOBFC5_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC5_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC5_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC5_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC6 ======================================================== */ + #define R_MFWD_FWFOBFC6_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC6_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC6_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC6_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC7 ======================================================== */ + #define R_MFWD_FWFOBFC7_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC7_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC7_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC7_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC8 ======================================================== */ + #define R_MFWD_FWFOBFC8_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC8_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC8_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC8_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC9 ======================================================== */ + #define R_MFWD_FWFOBFC9_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC9_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC9_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC9_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC10 ======================================================= */ + #define R_MFWD_FWFOBFC10_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC10_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC10_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC10_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC11 ======================================================= */ + #define R_MFWD_FWFOBFC11_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC11_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC11_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC11_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC12 ======================================================= */ + #define R_MFWD_FWFOBFC12_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC12_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC12_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC12_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC13 ======================================================= */ + #define R_MFWD_FWFOBFC13_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC13_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC13_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC13_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC14 ======================================================= */ + #define R_MFWD_FWFOBFC14_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC14_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC14_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC14_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ======================================================= FWFOBFC15 ======================================================= */ + #define R_MFWD_FWFOBFC15_FOBFUM_Pos (0UL) /*!< FOBFUM (Bit 0) */ + #define R_MFWD_FWFOBFC15_FOBFUM_Msk (0x3UL) /*!< FOBFUM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWFOBFC15_FOBFOV_Pos (16UL) /*!< FOBFOV (Bit 16) */ + #define R_MFWD_FWFOBFC15_FOBFOV_Msk (0xff0000UL) /*!< FOBFOV (Bitfield-Mask: 0xff) */ +/* ====================================================== FWFOBFV0C0 ======================================================= */ + #define R_MFWD_FWFOBFV0C0_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C0_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C1 ======================================================= */ + #define R_MFWD_FWFOBFV0C1_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C1_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C2 ======================================================= */ + #define R_MFWD_FWFOBFV0C2_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C2_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C3 ======================================================= */ + #define R_MFWD_FWFOBFV0C3_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C3_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C4 ======================================================= */ + #define R_MFWD_FWFOBFV0C4_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C4_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C5 ======================================================= */ + #define R_MFWD_FWFOBFV0C5_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C5_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C6 ======================================================= */ + #define R_MFWD_FWFOBFV0C6_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C6_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C7 ======================================================= */ + #define R_MFWD_FWFOBFV0C7_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C7_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C8 ======================================================= */ + #define R_MFWD_FWFOBFV0C8_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C8_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C9 ======================================================= */ + #define R_MFWD_FWFOBFV0C9_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C9_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C10 ====================================================== */ + #define R_MFWD_FWFOBFV0C10_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C10_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C11 ====================================================== */ + #define R_MFWD_FWFOBFV0C11_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C11_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C12 ====================================================== */ + #define R_MFWD_FWFOBFV0C12_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C12_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C13 ====================================================== */ + #define R_MFWD_FWFOBFV0C13_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C13_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C14 ====================================================== */ + #define R_MFWD_FWFOBFV0C14_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C14_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV0C15 ====================================================== */ + #define R_MFWD_FWFOBFV0C15_FOBFV0_Pos (0UL) /*!< FOBFV0 (Bit 0) */ + #define R_MFWD_FWFOBFV0C15_FOBFV0_Msk (0xffffffffUL) /*!< FOBFV0 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C0 ======================================================= */ + #define R_MFWD_FWFOBFV1C0_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C0_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C1 ======================================================= */ + #define R_MFWD_FWFOBFV1C1_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C1_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C2 ======================================================= */ + #define R_MFWD_FWFOBFV1C2_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C2_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C3 ======================================================= */ + #define R_MFWD_FWFOBFV1C3_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C3_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C4 ======================================================= */ + #define R_MFWD_FWFOBFV1C4_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C4_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C5 ======================================================= */ + #define R_MFWD_FWFOBFV1C5_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C5_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C6 ======================================================= */ + #define R_MFWD_FWFOBFV1C6_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C6_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C7 ======================================================= */ + #define R_MFWD_FWFOBFV1C7_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C7_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C8 ======================================================= */ + #define R_MFWD_FWFOBFV1C8_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C8_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C9 ======================================================= */ + #define R_MFWD_FWFOBFV1C9_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C9_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C10 ====================================================== */ + #define R_MFWD_FWFOBFV1C10_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C10_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C11 ====================================================== */ + #define R_MFWD_FWFOBFV1C11_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C11_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C12 ====================================================== */ + #define R_MFWD_FWFOBFV1C12_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C12_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C13 ====================================================== */ + #define R_MFWD_FWFOBFV1C13_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C13_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C14 ====================================================== */ + #define R_MFWD_FWFOBFV1C14_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C14_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWFOBFV1C15 ====================================================== */ + #define R_MFWD_FWFOBFV1C15_FOBFV1_Pos (0UL) /*!< FOBFV1 (Bit 0) */ + #define R_MFWD_FWFOBFV1C15_FOBFV1_Msk (0xffffffffUL) /*!< FOBFV1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWRFC0 ========================================================= */ + #define R_MFWD_FWRFC0_RFM_Pos (8UL) /*!< RFM (Bit 8) */ + #define R_MFWD_FWRFC0_RFM_Msk (0x100UL) /*!< RFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWRFC0_RFOV_Pos (16UL) /*!< RFOV (Bit 16) */ + #define R_MFWD_FWRFC0_RFOV_Msk (0xff0000UL) /*!< RFOV (Bitfield-Mask: 0xff) */ +/* ======================================================== FWRFC1 ========================================================= */ + #define R_MFWD_FWRFC1_RFM_Pos (8UL) /*!< RFM (Bit 8) */ + #define R_MFWD_FWRFC1_RFM_Msk (0x100UL) /*!< RFM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWRFC1_RFOV_Pos (16UL) /*!< RFOV (Bit 16) */ + #define R_MFWD_FWRFC1_RFOV_Msk (0xff0000UL) /*!< RFOV (Bitfield-Mask: 0xff) */ +/* ======================================================== FWRFVC0 ======================================================== */ + #define R_MFWD_FWRFVC0_RFSV_Pos (0UL) /*!< RFSV (Bit 0) */ + #define R_MFWD_FWRFVC0_RFSV_Msk (0xffUL) /*!< RFSV (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWRFVC0_RFRV_Pos (16UL) /*!< RFRV (Bit 16) */ + #define R_MFWD_FWRFVC0_RFRV_Msk (0xf0000UL) /*!< RFRV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWRFVC1 ======================================================== */ + #define R_MFWD_FWRFVC1_RFSV_Pos (0UL) /*!< RFSV (Bit 0) */ + #define R_MFWD_FWRFVC1_RFSV_Msk (0xffUL) /*!< RFSV (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWRFVC1_RFRV_Pos (16UL) /*!< RFRV (Bit 16) */ + #define R_MFWD_FWRFVC1_RFRV_Msk (0xf0000UL) /*!< RFRV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC0 ========================================================= */ + #define R_MFWD_FWCFC0_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC0_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC0_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC0_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC1 ========================================================= */ + #define R_MFWD_FWCFC1_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC1_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC1_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC1_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC2 ========================================================= */ + #define R_MFWD_FWCFC2_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC2_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC2_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC2_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC3 ========================================================= */ + #define R_MFWD_FWCFC3_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC3_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC3_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC3_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC4 ========================================================= */ + #define R_MFWD_FWCFC4_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC4_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC4_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC4_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC5 ========================================================= */ + #define R_MFWD_FWCFC5_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC5_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC5_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC5_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC6 ========================================================= */ + #define R_MFWD_FWCFC6_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC6_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC6_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC6_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC7 ========================================================= */ + #define R_MFWD_FWCFC7_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC7_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC7_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC7_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC8 ========================================================= */ + #define R_MFWD_FWCFC8_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC8_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC8_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC8_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC9 ========================================================= */ + #define R_MFWD_FWCFC9_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC9_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC9_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC9_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC10 ======================================================== */ + #define R_MFWD_FWCFC10_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC10_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC10_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC10_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC11 ======================================================== */ + #define R_MFWD_FWCFC11_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC11_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC11_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC11_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC12 ======================================================== */ + #define R_MFWD_FWCFC12_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC12_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC12_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC12_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC13 ======================================================== */ + #define R_MFWD_FWCFC13_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC13_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC13_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC13_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC14 ======================================================== */ + #define R_MFWD_FWCFC14_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC14_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC14_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC14_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWCFC15 ======================================================== */ + #define R_MFWD_FWCFC15_CFEFFV_Pos (0UL) /*!< CFEFFV (Bit 0) */ + #define R_MFWD_FWCFC15_CFEFFV_Msk (0x7fUL) /*!< CFEFFV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFC15_CFPFFV_Pos (16UL) /*!< CFPFFV (Bit 16) */ + #define R_MFWD_FWCFC15_CFPFFV_Msk (0xf0000UL) /*!< CFPFFV (Bitfield-Mask: 0x0f) */ +/* ======================================================= FWCFMC00 ======================================================== */ + #define R_MFWD_FWCFMC00_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC00_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC00_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC00_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC10 ======================================================== */ + #define R_MFWD_FWCFMC10_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC10_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC10_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC10_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC20 ======================================================== */ + #define R_MFWD_FWCFMC20_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC20_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC20_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC20_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC30 ======================================================== */ + #define R_MFWD_FWCFMC30_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC30_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC30_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC30_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC40 ======================================================== */ + #define R_MFWD_FWCFMC40_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC40_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC40_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC40_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC50 ======================================================== */ + #define R_MFWD_FWCFMC50_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC50_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC50_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC50_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC60 ======================================================== */ + #define R_MFWD_FWCFMC60_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC60_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC60_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC60_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC70 ======================================================== */ + #define R_MFWD_FWCFMC70_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC70_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC70_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC70_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC80 ======================================================== */ + #define R_MFWD_FWCFMC80_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC80_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC80_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC80_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC90 ======================================================== */ + #define R_MFWD_FWCFMC90_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC90_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC90_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC90_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC100 ======================================================= */ + #define R_MFWD_FWCFMC100_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC100_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC100_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC100_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC110 ======================================================= */ + #define R_MFWD_FWCFMC110_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC110_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC110_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC110_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC120 ======================================================= */ + #define R_MFWD_FWCFMC120_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC120_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC120_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC120_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC130 ======================================================= */ + #define R_MFWD_FWCFMC130_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC130_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC130_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC130_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC140 ======================================================= */ + #define R_MFWD_FWCFMC140_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC140_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC140_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC140_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC150 ======================================================= */ + #define R_MFWD_FWCFMC150_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC150_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC150_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC150_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC01 ======================================================== */ + #define R_MFWD_FWCFMC01_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC01_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC01_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC01_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC11 ======================================================== */ + #define R_MFWD_FWCFMC11_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC11_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC11_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC11_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC21 ======================================================== */ + #define R_MFWD_FWCFMC21_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC21_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC21_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC21_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC31 ======================================================== */ + #define R_MFWD_FWCFMC31_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC31_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC31_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC31_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC41 ======================================================== */ + #define R_MFWD_FWCFMC41_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC41_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC41_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC41_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC51 ======================================================== */ + #define R_MFWD_FWCFMC51_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC51_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC51_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC51_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC61 ======================================================== */ + #define R_MFWD_FWCFMC61_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC61_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC61_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC61_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC71 ======================================================== */ + #define R_MFWD_FWCFMC71_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC71_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC71_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC71_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC81 ======================================================== */ + #define R_MFWD_FWCFMC81_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC81_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC81_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC81_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC91 ======================================================== */ + #define R_MFWD_FWCFMC91_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC91_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC91_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC91_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC101 ======================================================= */ + #define R_MFWD_FWCFMC101_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC101_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC101_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC101_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC111 ======================================================= */ + #define R_MFWD_FWCFMC111_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC111_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC111_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC111_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC121 ======================================================= */ + #define R_MFWD_FWCFMC121_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC121_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC121_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC121_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC131 ======================================================= */ + #define R_MFWD_FWCFMC131_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC131_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC131_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC131_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC141 ======================================================= */ + #define R_MFWD_FWCFMC141_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC141_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC141_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC141_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC151 ======================================================= */ + #define R_MFWD_FWCFMC151_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC151_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC151_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC151_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC02 ======================================================== */ + #define R_MFWD_FWCFMC02_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC02_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC02_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC02_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC12 ======================================================== */ + #define R_MFWD_FWCFMC12_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC12_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC12_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC12_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC22 ======================================================== */ + #define R_MFWD_FWCFMC22_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC22_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC22_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC22_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC32 ======================================================== */ + #define R_MFWD_FWCFMC32_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC32_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC32_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC32_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC42 ======================================================== */ + #define R_MFWD_FWCFMC42_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC42_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC42_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC42_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC52 ======================================================== */ + #define R_MFWD_FWCFMC52_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC52_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC52_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC52_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC62 ======================================================== */ + #define R_MFWD_FWCFMC62_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC62_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC62_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC62_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC72 ======================================================== */ + #define R_MFWD_FWCFMC72_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC72_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC72_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC72_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC82 ======================================================== */ + #define R_MFWD_FWCFMC82_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC82_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC82_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC82_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC92 ======================================================== */ + #define R_MFWD_FWCFMC92_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC92_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC92_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC92_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC102 ======================================================= */ + #define R_MFWD_FWCFMC102_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC102_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC102_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC102_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC112 ======================================================= */ + #define R_MFWD_FWCFMC112_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC112_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC112_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC112_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC122 ======================================================= */ + #define R_MFWD_FWCFMC122_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC122_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC122_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC122_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC132 ======================================================= */ + #define R_MFWD_FWCFMC132_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC132_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC132_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC132_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC142 ======================================================= */ + #define R_MFWD_FWCFMC142_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC142_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC142_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC142_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC152 ======================================================= */ + #define R_MFWD_FWCFMC152_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC152_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC152_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC152_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC03 ======================================================== */ + #define R_MFWD_FWCFMC03_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC03_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC03_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC03_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC13 ======================================================== */ + #define R_MFWD_FWCFMC13_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC13_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC13_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC13_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC23 ======================================================== */ + #define R_MFWD_FWCFMC23_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC23_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC23_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC23_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC33 ======================================================== */ + #define R_MFWD_FWCFMC33_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC33_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC33_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC33_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC43 ======================================================== */ + #define R_MFWD_FWCFMC43_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC43_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC43_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC43_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC53 ======================================================== */ + #define R_MFWD_FWCFMC53_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC53_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC53_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC53_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC63 ======================================================== */ + #define R_MFWD_FWCFMC63_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC63_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC63_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC63_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC73 ======================================================== */ + #define R_MFWD_FWCFMC73_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC73_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC73_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC73_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC83 ======================================================== */ + #define R_MFWD_FWCFMC83_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC83_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC83_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC83_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC93 ======================================================== */ + #define R_MFWD_FWCFMC93_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC93_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC93_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC93_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC103 ======================================================= */ + #define R_MFWD_FWCFMC103_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC103_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC103_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC103_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC113 ======================================================= */ + #define R_MFWD_FWCFMC113_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC113_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC113_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC113_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC123 ======================================================= */ + #define R_MFWD_FWCFMC123_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC123_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC123_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC123_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC133 ======================================================= */ + #define R_MFWD_FWCFMC133_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC133_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC133_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC133_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC143 ======================================================= */ + #define R_MFWD_FWCFMC143_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC143_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC143_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC143_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC153 ======================================================= */ + #define R_MFWD_FWCFMC153_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC153_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC153_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC153_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC04 ======================================================== */ + #define R_MFWD_FWCFMC04_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC04_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC04_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC04_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC14 ======================================================== */ + #define R_MFWD_FWCFMC14_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC14_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC14_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC14_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC24 ======================================================== */ + #define R_MFWD_FWCFMC24_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC24_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC24_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC24_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC34 ======================================================== */ + #define R_MFWD_FWCFMC34_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC34_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC34_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC34_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC44 ======================================================== */ + #define R_MFWD_FWCFMC44_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC44_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC44_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC44_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC54 ======================================================== */ + #define R_MFWD_FWCFMC54_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC54_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC54_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC54_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC64 ======================================================== */ + #define R_MFWD_FWCFMC64_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC64_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC64_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC64_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC74 ======================================================== */ + #define R_MFWD_FWCFMC74_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC74_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC74_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC74_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC84 ======================================================== */ + #define R_MFWD_FWCFMC84_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC84_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC84_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC84_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC94 ======================================================== */ + #define R_MFWD_FWCFMC94_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC94_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC94_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC94_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC104 ======================================================= */ + #define R_MFWD_FWCFMC104_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC104_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC104_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC104_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC114 ======================================================= */ + #define R_MFWD_FWCFMC114_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC114_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC114_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC114_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC124 ======================================================= */ + #define R_MFWD_FWCFMC124_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC124_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC124_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC124_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC134 ======================================================= */ + #define R_MFWD_FWCFMC134_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC134_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC134_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC134_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC144 ======================================================= */ + #define R_MFWD_FWCFMC144_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC144_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC144_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC144_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC154 ======================================================= */ + #define R_MFWD_FWCFMC154_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC154_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC154_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC154_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC05 ======================================================== */ + #define R_MFWD_FWCFMC05_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC05_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC05_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC05_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC15 ======================================================== */ + #define R_MFWD_FWCFMC15_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC15_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC15_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC15_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC25 ======================================================== */ + #define R_MFWD_FWCFMC25_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC25_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC25_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC25_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC35 ======================================================== */ + #define R_MFWD_FWCFMC35_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC35_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC35_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC35_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC45 ======================================================== */ + #define R_MFWD_FWCFMC45_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC45_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC45_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC45_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC55 ======================================================== */ + #define R_MFWD_FWCFMC55_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC55_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC55_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC55_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC65 ======================================================== */ + #define R_MFWD_FWCFMC65_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC65_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC65_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC65_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC75 ======================================================== */ + #define R_MFWD_FWCFMC75_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC75_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC75_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC75_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC85 ======================================================== */ + #define R_MFWD_FWCFMC85_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC85_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC85_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC85_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC95 ======================================================== */ + #define R_MFWD_FWCFMC95_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC95_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC95_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC95_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC105 ======================================================= */ + #define R_MFWD_FWCFMC105_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC105_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC105_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC105_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC115 ======================================================= */ + #define R_MFWD_FWCFMC115_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC115_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC115_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC115_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC125 ======================================================= */ + #define R_MFWD_FWCFMC125_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC125_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC125_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC125_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC135 ======================================================= */ + #define R_MFWD_FWCFMC135_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC135_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC135_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC135_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC145 ======================================================= */ + #define R_MFWD_FWCFMC145_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC145_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC145_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC145_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC155 ======================================================= */ + #define R_MFWD_FWCFMC155_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC155_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC155_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC155_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC06 ======================================================== */ + #define R_MFWD_FWCFMC06_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC06_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC06_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC06_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC16 ======================================================== */ + #define R_MFWD_FWCFMC16_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC16_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC16_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC16_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC26 ======================================================== */ + #define R_MFWD_FWCFMC26_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC26_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC26_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC26_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC36 ======================================================== */ + #define R_MFWD_FWCFMC36_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC36_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC36_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC36_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC46 ======================================================== */ + #define R_MFWD_FWCFMC46_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC46_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC46_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC46_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC56 ======================================================== */ + #define R_MFWD_FWCFMC56_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC56_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC56_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC56_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC66 ======================================================== */ + #define R_MFWD_FWCFMC66_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC66_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC66_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC66_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC76 ======================================================== */ + #define R_MFWD_FWCFMC76_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC76_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC76_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC76_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC86 ======================================================== */ + #define R_MFWD_FWCFMC86_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC86_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC86_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC86_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC96 ======================================================== */ + #define R_MFWD_FWCFMC96_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC96_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC96_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC96_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC106 ======================================================= */ + #define R_MFWD_FWCFMC106_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC106_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC106_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC106_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC116 ======================================================= */ + #define R_MFWD_FWCFMC116_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC116_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC116_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC116_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC126 ======================================================= */ + #define R_MFWD_FWCFMC126_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC126_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC126_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC126_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC136 ======================================================= */ + #define R_MFWD_FWCFMC136_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC136_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC136_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC136_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC146 ======================================================= */ + #define R_MFWD_FWCFMC146_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC146_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC146_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC146_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================= FWCFMC156 ======================================================= */ + #define R_MFWD_FWCFMC156_CFFN_Pos (0UL) /*!< CFFN (Bit 0) */ + #define R_MFWD_FWCFMC156_CFFN_Msk (0x7fUL) /*!< CFFN (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWCFMC156_CFFV_Pos (15UL) /*!< CFFV (Bit 15) */ + #define R_MFWD_FWCFMC156_CFFV_Msk (0x8000UL) /*!< CFFV (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP4SC ======================================================== */ + #define R_MFWD_FWIP4SC_IP4IMDH_Pos (0UL) /*!< IP4IMDH (Bit 0) */ + #define R_MFWD_FWIP4SC_IP4IMDH_Msk (0x1UL) /*!< IP4IMDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IMSH_Pos (1UL) /*!< IP4IMSH (Bit 1) */ + #define R_MFWD_FWIP4SC_IP4IMSH_Msk (0x2UL) /*!< IP4IMSH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISVH_Pos (2UL) /*!< IP4ISVH (Bit 2) */ + #define R_MFWD_FWIP4SC_IP4ISVH_Msk (0x4UL) /*!< IP4ISVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPH_Pos (3UL) /*!< IP4ISPH (Bit 3) */ + #define R_MFWD_FWIP4SC_IP4ISPH_Msk (0x8UL) /*!< IP4ISPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISDH_Pos (4UL) /*!< IP4ISDH (Bit 4) */ + #define R_MFWD_FWIP4SC_IP4ISDH_Msk (0x10UL) /*!< IP4ISDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICVH_Pos (5UL) /*!< IP4ICVH (Bit 5) */ + #define R_MFWD_FWIP4SC_IP4ICVH_Msk (0x20UL) /*!< IP4ICVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICPH_Pos (6UL) /*!< IP4ICPH (Bit 6) */ + #define R_MFWD_FWIP4SC_IP4ICPH_Msk (0x40UL) /*!< IP4ICPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICDH_Pos (7UL) /*!< IP4ICDH (Bit 7) */ + #define R_MFWD_FWIP4SC_IP4ICDH_Msk (0x80UL) /*!< IP4ICDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IISH_Pos (8UL) /*!< IP4IISH (Bit 8) */ + #define R_MFWD_FWIP4SC_IP4IISH_Msk (0x100UL) /*!< IP4IISH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IIDH_Pos (9UL) /*!< IP4IIDH (Bit 9) */ + #define R_MFWD_FWIP4SC_IP4IIDH_Msk (0x200UL) /*!< IP4IIDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IPH_Pos (10UL) /*!< IP4IPH (Bit 10) */ + #define R_MFWD_FWIP4SC_IP4IPH_Msk (0x400UL) /*!< IP4IPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPTH_Pos (11UL) /*!< IP4ISPTH (Bit 11) */ + #define R_MFWD_FWIP4SC_IP4ISPTH_Msk (0x800UL) /*!< IP4ISPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IDPTH_Pos (12UL) /*!< IP4IDPTH (Bit 12) */ + #define R_MFWD_FWIP4SC_IP4IDPTH_Msk (0x1000UL) /*!< IP4IDPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISVS_Pos (16UL) /*!< IP4ISVS (Bit 16) */ + #define R_MFWD_FWIP4SC_IP4ISVS_Msk (0x10000UL) /*!< IP4ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISPS_Pos (17UL) /*!< IP4ISPS (Bit 17) */ + #define R_MFWD_FWIP4SC_IP4ISPS_Msk (0x20000UL) /*!< IP4ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ISDS_Pos (18UL) /*!< IP4ISDS (Bit 18) */ + #define R_MFWD_FWIP4SC_IP4ISDS_Msk (0x40000UL) /*!< IP4ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICVS_Pos (19UL) /*!< IP4ICVS (Bit 19) */ + #define R_MFWD_FWIP4SC_IP4ICVS_Msk (0x80000UL) /*!< IP4ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICPS_Pos (20UL) /*!< IP4ICPS (Bit 20) */ + #define R_MFWD_FWIP4SC_IP4ICPS_Msk (0x100000UL) /*!< IP4ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4ICDS_Pos (21UL) /*!< IP4ICDS (Bit 21) */ + #define R_MFWD_FWIP4SC_IP4ICDS_Msk (0x200000UL) /*!< IP4ICDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IISS_Pos (22UL) /*!< IP4IISS (Bit 22) */ + #define R_MFWD_FWIP4SC_IP4IISS_Msk (0x400000UL) /*!< IP4IISS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IIDS_Pos (23UL) /*!< IP4IIDS (Bit 23) */ + #define R_MFWD_FWIP4SC_IP4IIDS_Msk (0x800000UL) /*!< IP4IIDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP4SC_IP4IDPTS_Pos (24UL) /*!< IP4IDPTS (Bit 24) */ + #define R_MFWD_FWIP4SC_IP4IDPTS_Msk (0x1000000UL) /*!< IP4IDPTS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP6SC ======================================================== */ + #define R_MFWD_FWIP6SC_IP6IMDH_Pos (0UL) /*!< IP6IMDH (Bit 0) */ + #define R_MFWD_FWIP6SC_IP6IMDH_Msk (0x1UL) /*!< IP6IMDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IMSH_Pos (1UL) /*!< IP6IMSH (Bit 1) */ + #define R_MFWD_FWIP6SC_IP6IMSH_Msk (0x2UL) /*!< IP6IMSH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISVH_Pos (2UL) /*!< IP6ISVH (Bit 2) */ + #define R_MFWD_FWIP6SC_IP6ISVH_Msk (0x4UL) /*!< IP6ISVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPH_Pos (3UL) /*!< IP6ISPH (Bit 3) */ + #define R_MFWD_FWIP6SC_IP6ISPH_Msk (0x8UL) /*!< IP6ISPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISDH_Pos (4UL) /*!< IP6ISDH (Bit 4) */ + #define R_MFWD_FWIP6SC_IP6ISDH_Msk (0x10UL) /*!< IP6ISDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICVH_Pos (5UL) /*!< IP6ICVH (Bit 5) */ + #define R_MFWD_FWIP6SC_IP6ICVH_Msk (0x20UL) /*!< IP6ICVH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICPH_Pos (6UL) /*!< IP6ICPH (Bit 6) */ + #define R_MFWD_FWIP6SC_IP6ICPH_Msk (0x40UL) /*!< IP6ICPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICDH_Pos (7UL) /*!< IP6ICDH (Bit 7) */ + #define R_MFWD_FWIP6SC_IP6ICDH_Msk (0x80UL) /*!< IP6ICDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IISH_Pos (8UL) /*!< IP6IISH (Bit 8) */ + #define R_MFWD_FWIP6SC_IP6IISH_Msk (0x100UL) /*!< IP6IISH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IIDH_Pos (9UL) /*!< IP6IIDH (Bit 9) */ + #define R_MFWD_FWIP6SC_IP6IIDH_Msk (0x200UL) /*!< IP6IIDH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IPH_Pos (10UL) /*!< IP6IPH (Bit 10) */ + #define R_MFWD_FWIP6SC_IP6IPH_Msk (0x400UL) /*!< IP6IPH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPTH_Pos (11UL) /*!< IP6ISPTH (Bit 11) */ + #define R_MFWD_FWIP6SC_IP6ISPTH_Msk (0x800UL) /*!< IP6ISPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IDPTH_Pos (12UL) /*!< IP6IDPTH (Bit 12) */ + #define R_MFWD_FWIP6SC_IP6IDPTH_Msk (0x1000UL) /*!< IP6IDPTH (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISVS_Pos (16UL) /*!< IP6ISVS (Bit 16) */ + #define R_MFWD_FWIP6SC_IP6ISVS_Msk (0x10000UL) /*!< IP6ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISPS_Pos (17UL) /*!< IP6ISPS (Bit 17) */ + #define R_MFWD_FWIP6SC_IP6ISPS_Msk (0x20000UL) /*!< IP6ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ISDS_Pos (18UL) /*!< IP6ISDS (Bit 18) */ + #define R_MFWD_FWIP6SC_IP6ISDS_Msk (0x40000UL) /*!< IP6ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICVS_Pos (19UL) /*!< IP6ICVS (Bit 19) */ + #define R_MFWD_FWIP6SC_IP6ICVS_Msk (0x80000UL) /*!< IP6ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICPS_Pos (20UL) /*!< IP6ICPS (Bit 20) */ + #define R_MFWD_FWIP6SC_IP6ICPS_Msk (0x100000UL) /*!< IP6ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6ICDS_Pos (21UL) /*!< IP6ICDS (Bit 21) */ + #define R_MFWD_FWIP6SC_IP6ICDS_Msk (0x200000UL) /*!< IP6ICDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6II0S_Pos (22UL) /*!< IP6II0S (Bit 22) */ + #define R_MFWD_FWIP6SC_IP6II0S_Msk (0x400000UL) /*!< IP6II0S (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6II1S_Pos (23UL) /*!< IP6II1S (Bit 23) */ + #define R_MFWD_FWIP6SC_IP6II1S_Msk (0x800000UL) /*!< IP6II1S (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6SC_IP6IDPTS_Pos (24UL) /*!< IP6IDPTS (Bit 24) */ + #define R_MFWD_FWIP6SC_IP6IDPTS_Msk (0x1000000UL) /*!< IP6IDPTS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWIP6OC ======================================================== */ + #define R_MFWD_FWIP6OC_IP6IPOM_Pos (0UL) /*!< IP6IPOM (Bit 0) */ + #define R_MFWD_FWIP6OC_IP6IPOM_Msk (0x1UL) /*!< IP6IPOM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWIP6OC_IP6IPO_Pos (4UL) /*!< IP6IPO (Bit 4) */ + #define R_MFWD_FWIP6OC_IP6IPO_Msk (0xf0UL) /*!< IP6IPO (Bitfield-Mask: 0x0f) */ +/* ======================================================== FWL2SC ========================================================= */ + #define R_MFWD_FWL2SC_L2IMDS_Pos (0UL) /*!< L2IMDS (Bit 0) */ + #define R_MFWD_FWL2SC_L2IMDS_Msk (0x1UL) /*!< L2IMDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2IMSS_Pos (1UL) /*!< L2IMSS (Bit 1) */ + #define R_MFWD_FWL2SC_L2IMSS_Msk (0x2UL) /*!< L2IMSS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISVS_Pos (2UL) /*!< L2ISVS (Bit 2) */ + #define R_MFWD_FWL2SC_L2ISVS_Msk (0x4UL) /*!< L2ISVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISPS_Pos (3UL) /*!< L2ISPS (Bit 3) */ + #define R_MFWD_FWL2SC_L2ISPS_Msk (0x8UL) /*!< L2ISPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ISDS_Pos (4UL) /*!< L2ISDS (Bit 4) */ + #define R_MFWD_FWL2SC_L2ISDS_Msk (0x10UL) /*!< L2ISDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICVS_Pos (5UL) /*!< L2ICVS (Bit 5) */ + #define R_MFWD_FWL2SC_L2ICVS_Msk (0x20UL) /*!< L2ICVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICPS_Pos (6UL) /*!< L2ICPS (Bit 6) */ + #define R_MFWD_FWL2SC_L2ICPS_Msk (0x40UL) /*!< L2ICPS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL2SC_L2ICDS_Pos (7UL) /*!< L2ICDS (Bit 7) */ + #define R_MFWD_FWL2SC_L2ICDS_Msk (0x80UL) /*!< L2ICDS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWSFHEC ======================================================== */ + #define R_MFWD_FWSFHEC_IP4HE_Pos (0UL) /*!< IP4HE (Bit 0) */ + #define R_MFWD_FWSFHEC_IP4HE_Msk (0xffffUL) /*!< IP4HE (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSFHEC_IP6HE_Pos (16UL) /*!< IP6HE (Bit 16) */ + #define R_MFWD_FWSFHEC_IP6HE_Msk (0xffff0000UL) /*!< IP6HE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCR0 ======================================================== */ + #define R_MFWD_FWSHCR0_SHCMDP0_Pos (0UL) /*!< SHCMDP0 (Bit 0) */ + #define R_MFWD_FWSHCR0_SHCMDP0_Msk (0xffffffffUL) /*!< SHCMDP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR1 ======================================================== */ + #define R_MFWD_FWSHCR1_SHCMSP0_Pos (0UL) /*!< SHCMSP0 (Bit 0) */ + #define R_MFWD_FWSHCR1_SHCMSP0_Msk (0xffffUL) /*!< SHCMSP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCR1_SHCMDP1_Pos (16UL) /*!< SHCMDP1 (Bit 16) */ + #define R_MFWD_FWSHCR1_SHCMDP1_Msk (0xffff0000UL) /*!< SHCMDP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCR2 ======================================================== */ + #define R_MFWD_FWSHCR2_SHCMSP1_Pos (0UL) /*!< SHCMSP1 (Bit 0) */ + #define R_MFWD_FWSHCR2_SHCMSP1_Msk (0xffffffffUL) /*!< SHCMSP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR3 ======================================================== */ + #define R_MFWD_FWSHCR3_SHCCV_Pos (0UL) /*!< SHCCV (Bit 0) */ + #define R_MFWD_FWSHCR3_SHCCV_Msk (0xfffUL) /*!< SHCCV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWSHCR3_SHCCD_Pos (12UL) /*!< SHCCD (Bit 12) */ + #define R_MFWD_FWSHCR3_SHCCD_Msk (0x1000UL) /*!< SHCCD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSHCR3_SHCCP_Pos (13UL) /*!< SHCCP (Bit 13) */ + #define R_MFWD_FWSHCR3_SHCCP_Msk (0xe000UL) /*!< SHCCP (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWSHCR3_SHCSV_Pos (16UL) /*!< SHCSV (Bit 16) */ + #define R_MFWD_FWSHCR3_SHCSV_Msk (0xfff0000UL) /*!< SHCSV (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWSHCR3_SHCSD_Pos (28UL) /*!< SHCSD (Bit 28) */ + #define R_MFWD_FWSHCR3_SHCSD_Msk (0x10000000UL) /*!< SHCSD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWSHCR3_SHCSP_Pos (29UL) /*!< SHCSP (Bit 29) */ + #define R_MFWD_FWSHCR3_SHCSP_Msk (0xe0000000UL) /*!< SHCSP (Bitfield-Mask: 0x07) */ +/* ======================================================== FWSHCR4 ======================================================== */ + #define R_MFWD_FWSHCR4_SHCP_Pos (0UL) /*!< SHCP (Bit 0) */ + #define R_MFWD_FWSHCR4_SHCP_Msk (0xffUL) /*!< SHCP (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSHCR4_SHCFF_Pos (16UL) /*!< SHCFF (Bit 16) */ + #define R_MFWD_FWSHCR4_SHCFF_Msk (0x10000UL) /*!< SHCFF (Bitfield-Mask: 0x01) */ +/* ======================================================== FWSHCR5 ======================================================== */ + #define R_MFWD_FWSHCR5_SHCISP0_Pos (0UL) /*!< SHCISP0 (Bit 0) */ + #define R_MFWD_FWSHCR5_SHCISP0_Msk (0xffffffffUL) /*!< SHCISP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR6 ======================================================== */ + #define R_MFWD_FWSHCR6_SHCISP1_Pos (0UL) /*!< SHCISP1 (Bit 0) */ + #define R_MFWD_FWSHCR6_SHCISP1_Msk (0xffffffffUL) /*!< SHCISP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR7 ======================================================== */ + #define R_MFWD_FWSHCR7_SHCISP2_Pos (0UL) /*!< SHCISP2 (Bit 0) */ + #define R_MFWD_FWSHCR7_SHCISP2_Msk (0xffffffffUL) /*!< SHCISP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR8 ======================================================== */ + #define R_MFWD_FWSHCR8_SHCISP3_Pos (0UL) /*!< SHCISP3 (Bit 0) */ + #define R_MFWD_FWSHCR8_SHCISP3_Msk (0xffffffffUL) /*!< SHCISP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWSHCR9 ======================================================== */ + #define R_MFWD_FWSHCR9_SHCIDP0_Pos (0UL) /*!< SHCIDP0 (Bit 0) */ + #define R_MFWD_FWSHCR9_SHCIDP0_Msk (0xffffffffUL) /*!< SHCIDP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR10 ======================================================== */ + #define R_MFWD_FWSHCR10_SHCIDP1_Pos (0UL) /*!< SHCIDP1 (Bit 0) */ + #define R_MFWD_FWSHCR10_SHCIDP1_Msk (0xffffffffUL) /*!< SHCIDP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR11 ======================================================== */ + #define R_MFWD_FWSHCR11_SHCIDP2_Pos (0UL) /*!< SHCIDP2 (Bit 0) */ + #define R_MFWD_FWSHCR11_SHCIDP2_Msk (0xffffffffUL) /*!< SHCIDP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR12 ======================================================== */ + #define R_MFWD_FWSHCR12_SHCIDP3_Pos (0UL) /*!< SHCIDP3 (Bit 0) */ + #define R_MFWD_FWSHCR12_SHCIDP3_Msk (0xffffffffUL) /*!< SHCIDP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWSHCR13 ======================================================== */ + #define R_MFWD_FWSHCR13_SHCDP_Pos (0UL) /*!< SHCDP (Bit 0) */ + #define R_MFWD_FWSHCR13_SHCDP_Msk (0xffffUL) /*!< SHCDP (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCR13_SHCSP_Pos (16UL) /*!< SHCSP (Bit 16) */ + #define R_MFWD_FWSHCR13_SHCSP_Msk (0xffff0000UL) /*!< SHCSP (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWSHCRR ======================================================== */ + #define R_MFWD_FWSHCRR_SHCR_Pos (0UL) /*!< SHCR (Bit 0) */ + #define R_MFWD_FWSHCRR_SHCR_Msk (0xffffUL) /*!< SHCR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWSHCRR_SHC_Pos (31UL) /*!< SHC (Bit 31) */ + #define R_MFWD_FWSHCRR_SHC_Msk (0x80000000UL) /*!< SHC (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHHEC ======================================================== */ + #define R_MFWD_FWLTHHEC_LTHHMC_Pos (0UL) /*!< LTHHMC (Bit 0) */ + #define R_MFWD_FWLTHHEC_LTHHMC_Msk (0x3ffUL) /*!< LTHHMC (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHHEC_LTHHMUE_Pos (16UL) /*!< LTHHMUE (Bit 16) */ + #define R_MFWD_FWLTHHEC_LTHHMUE_Msk (0x7ff0000UL) /*!< LTHHMUE (Bitfield-Mask: 0x7ff) */ +/* ======================================================== FWLTHHC ======================================================== */ + #define R_MFWD_FWLTHHC_LTHHE_Pos (0UL) /*!< LTHHE (Bit 0) */ + #define R_MFWD_FWLTHHC_LTHHE_Msk (0x3ffUL) /*!< LTHHE (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWLTHTL0 ======================================================== */ + #define R_MFWD_FWLTHTL0_LTHSLP0_Pos (0UL) /*!< LTHSLP0 (Bit 0) */ + #define R_MFWD_FWLTHTL0_LTHSLP0_Msk (0x7UL) /*!< LTHSLP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTL0_LTHSLL_Pos (8UL) /*!< LTHSLL (Bit 8) */ + #define R_MFWD_FWLTHTL0_LTHSLL_Msk (0x100UL) /*!< LTHSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL0_LTHED_Pos (16UL) /*!< LTHED (Bit 16) */ + #define R_MFWD_FWLTHTL0_LTHED_Msk (0x10000UL) /*!< LTHED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL1 ======================================================== */ + #define R_MFWD_FWLTHTL1_LTHSLP1_Pos (0UL) /*!< LTHSLP1 (Bit 0) */ + #define R_MFWD_FWLTHTL1_LTHSLP1_Msk (0xffffffffUL) /*!< LTHSLP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL2 ======================================================== */ + #define R_MFWD_FWLTHTL2_LTHSLP2_Pos (0UL) /*!< LTHSLP2 (Bit 0) */ + #define R_MFWD_FWLTHTL2_LTHSLP2_Msk (0xffffffffUL) /*!< LTHSLP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL3 ======================================================== */ + #define R_MFWD_FWLTHTL3_LTHSLP3_Pos (0UL) /*!< LTHSLP3 (Bit 0) */ + #define R_MFWD_FWLTHTL3_LTHSLP3_Msk (0xffffffffUL) /*!< LTHSLP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL4 ======================================================== */ + #define R_MFWD_FWLTHTL4_LTHSLP4_Pos (0UL) /*!< LTHSLP4 (Bit 0) */ + #define R_MFWD_FWLTHTL4_LTHSLP4_Msk (0xffffffffUL) /*!< LTHSLP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTL5 ======================================================== */ + #define R_MFWD_FWLTHTL5_LTHMSDUNL_Pos (16UL) /*!< LTHMSDUNL (Bit 16) */ + #define R_MFWD_FWLTHTL5_LTHMSDUNL_Msk (0xf0000UL) /*!< LTHMSDUNL (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTL5_LTHMSDUVL_Pos (31UL) /*!< LTHMSDUVL (Bit 31) */ + #define R_MFWD_FWLTHTL5_LTHMSDUVL_Msk (0x80000000UL) /*!< LTHMSDUVL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL6 ======================================================== */ + #define R_MFWD_FWLTHTL6_LTHFRERNL_Pos (0UL) /*!< LTHFRERNL (Bit 0) */ + #define R_MFWD_FWLTHTL6_LTHFRERNL_Msk (0x7fUL) /*!< LTHFRERNL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTL6_LTHFRERVL_Pos (15UL) /*!< LTHFRERVL (Bit 15) */ + #define R_MFWD_FWLTHTL6_LTHFRERVL_Msk (0x8000UL) /*!< LTHFRERVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL6_LTHMTRNL_Pos (16UL) /*!< LTHMTRNL (Bit 16) */ + #define R_MFWD_FWLTHTL6_LTHMTRNL_Msk (0x1f0000UL) /*!< LTHMTRNL (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTL6_LTHMTRVL_Pos (31UL) /*!< LTHMTRVL (Bit 31) */ + #define R_MFWD_FWLTHTL6_LTHMTRVL_Msk (0x80000000UL) /*!< LTHMTRVL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTL7 ======================================================== */ + #define R_MFWD_FWLTHTL7_LTHRNL_Pos (0UL) /*!< LTHRNL (Bit 0) */ + #define R_MFWD_FWLTHTL7_LTHRNL_Msk (0xffUL) /*!< LTHRNL (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTL7_LTHRVL_Pos (15UL) /*!< LTHRVL (Bit 15) */ + #define R_MFWD_FWLTHTL7_LTHRVL_Msk (0x8000UL) /*!< LTHRVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL7_LTHSLVL_Pos (16UL) /*!< LTHSLVL (Bit 16) */ + #define R_MFWD_FWLTHTL7_LTHSLVL_Msk (0x7f0000UL) /*!< LTHSLVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTL80 ======================================================= */ + #define R_MFWD_FWLTHTL80_LTHCSDL_Pos (0UL) /*!< LTHCSDL (Bit 0) */ + #define R_MFWD_FWLTHTL80_LTHCSDL_Msk (0x7fUL) /*!< LTHCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTL9 ======================================================== */ + #define R_MFWD_FWLTHTL9_LTHDVL_Pos (0UL) /*!< LTHDVL (Bit 0) */ + #define R_MFWD_FWLTHTL9_LTHDVL_Msk (0x7fUL) /*!< LTHDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTL9_LTHIPVL_Pos (16UL) /*!< LTHIPVL (Bit 16) */ + #define R_MFWD_FWLTHTL9_LTHIPVL_Msk (0x70000UL) /*!< LTHIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTL9_LTHIPUL_Pos (19UL) /*!< LTHIPUL (Bit 19) */ + #define R_MFWD_FWLTHTL9_LTHIPUL_Msk (0x80000UL) /*!< LTHIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL9_LTHEMEL_Pos (20UL) /*!< LTHEMEL (Bit 20) */ + #define R_MFWD_FWLTHTL9_LTHEMEL_Msk (0x100000UL) /*!< LTHEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTL9_LTHCMEL_Pos (21UL) /*!< LTHCMEL (Bit 21) */ + #define R_MFWD_FWLTHTL9_LTHCMEL_Msk (0x200000UL) /*!< LTHCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTLR ======================================================== */ + #define R_MFWD_FWLTHTLR_LTHLF_Pos (0UL) /*!< LTHLF (Bit 0) */ + #define R_MFWD_FWLTHTLR_LTHLF_Msk (0x1UL) /*!< LTHLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLSF_Pos (1UL) /*!< LTHLSF (Bit 1) */ + #define R_MFWD_FWLTHTLR_LTHLSF_Msk (0x2UL) /*!< LTHLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLEF_Pos (2UL) /*!< LTHLEF (Bit 2) */ + #define R_MFWD_FWLTHTLR_LTHLEF_Msk (0x4UL) /*!< LTHLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLO_Pos (3UL) /*!< LTHLO (Bit 3) */ + #define R_MFWD_FWLTHTLR_LTHLO_Msk (0x8UL) /*!< LTHLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTLR_LTHLCN_Pos (16UL) /*!< LTHLCN (Bit 16) */ + #define R_MFWD_FWLTHTLR_LTHLCN_Msk (0x3ff0000UL) /*!< LTHLCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHTLR_LTHTL_Pos (31UL) /*!< LTHTL (Bit 31) */ + #define R_MFWD_FWLTHTLR_LTHTL_Msk (0x80000000UL) /*!< LTHTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTIM ======================================================== */ + #define R_MFWD_FWLTHTIM_LTHTIOG_Pos (0UL) /*!< LTHTIOG (Bit 0) */ + #define R_MFWD_FWLTHTIM_LTHTIOG_Msk (0x1UL) /*!< LTHTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTIM_LTHTR_Pos (1UL) /*!< LTHTR (Bit 1) */ + #define R_MFWD_FWLTHTIM_LTHTR_Msk (0x2UL) /*!< LTHTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTEM ======================================================== */ + #define R_MFWD_FWLTHTEM_LTHTEN_Pos (0UL) /*!< LTHTEN (Bit 0) */ + #define R_MFWD_FWLTHTEM_LTHTEN_Msk (0x7ffUL) /*!< LTHTEN (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWLTHTEM_LTHTUEN_Pos (16UL) /*!< LTHTUEN (Bit 16) */ + #define R_MFWD_FWLTHTEM_LTHTUEN_Msk (0x7ff0000UL) /*!< LTHTUEN (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWLTHTS0 ======================================================== */ + #define R_MFWD_FWLTHTS0_LTHSSP0_Pos (0UL) /*!< LTHSSP0 (Bit 0) */ + #define R_MFWD_FWLTHTS0_LTHSSP0_Msk (0x7UL) /*!< LTHSSP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTS0_LTHSSPFS_Pos (24UL) /*!< LTHSSPFS (Bit 24) */ + #define R_MFWD_FWLTHTS0_LTHSSPFS_Msk (0x1000000UL) /*!< LTHSSPFS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTS1 ======================================================== */ + #define R_MFWD_FWLTHTS1_LTHSSP1_Pos (0UL) /*!< LTHSSP1 (Bit 0) */ + #define R_MFWD_FWLTHTS1_LTHSSP1_Msk (0xffffffffUL) /*!< LTHSSP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS2 ======================================================== */ + #define R_MFWD_FWLTHTS2_LTHSSP2_Pos (0UL) /*!< LTHSSP2 (Bit 0) */ + #define R_MFWD_FWLTHTS2_LTHSSP2_Msk (0xffffffffUL) /*!< LTHSSP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS3 ======================================================== */ + #define R_MFWD_FWLTHTS3_LTHSSP3_Pos (0UL) /*!< LTHSSP3 (Bit 0) */ + #define R_MFWD_FWLTHTS3_LTHSSP3_Msk (0xffffffffUL) /*!< LTHSSP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTS4 ======================================================== */ + #define R_MFWD_FWLTHTS4_LTHSSP4_Pos (0UL) /*!< LTHSSP4 (Bit 0) */ + #define R_MFWD_FWLTHTS4_LTHSSP4_Msk (0xffffffffUL) /*!< LTHSSP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTSR0 ======================================================= */ + #define R_MFWD_FWLTHTSR0_LTHSEF_Pos (0UL) /*!< LTHSEF (Bit 0) */ + #define R_MFWD_FWLTHTSR0_LTHSEF_Msk (0x1UL) /*!< LTHSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSNF_Pos (1UL) /*!< LTHSNF (Bit 1) */ + #define R_MFWD_FWLTHTSR0_LTHSNF_Msk (0x2UL) /*!< LTHSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSLS_Pos (8UL) /*!< LTHSLS (Bit 8) */ + #define R_MFWD_FWLTHTSR0_LTHSLS_Msk (0x100UL) /*!< LTHSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR0_LTHSCN_Pos (16UL) /*!< LTHSCN (Bit 16) */ + #define R_MFWD_FWLTHTSR0_LTHSCN_Msk (0x3ff0000UL) /*!< LTHSCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWLTHTSR0_LTHTS_Pos (31UL) /*!< LTHTS (Bit 31) */ + #define R_MFWD_FWLTHTSR0_LTHTS_Msk (0x80000000UL) /*!< LTHTS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR1 ======================================================= */ + #define R_MFWD_FWLTHTSR1_LTHMSDUNS_Pos (16UL) /*!< LTHMSDUNS (Bit 16) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUNS_Msk (0xf0000UL) /*!< LTHMSDUNS (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUVS_Pos (31UL) /*!< LTHMSDUVS (Bit 31) */ + #define R_MFWD_FWLTHTSR1_LTHMSDUVS_Msk (0x80000000UL) /*!< LTHMSDUVS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR2 ======================================================= */ + #define R_MFWD_FWLTHTSR2_LTHFRERNS_Pos (0UL) /*!< LTHFRERNS (Bit 0) */ + #define R_MFWD_FWLTHTSR2_LTHFRERNS_Msk (0x3fUL) /*!< LTHFRERNS (Bitfield-Mask: 0x3f) */ + #define R_MFWD_FWLTHTSR2_LTHFRERVS_Pos (15UL) /*!< LTHFRERVS (Bit 15) */ + #define R_MFWD_FWLTHTSR2_LTHFRERVS_Msk (0x8000UL) /*!< LTHFRERVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR2_LTHMTRNS_Pos (16UL) /*!< LTHMTRNS (Bit 16) */ + #define R_MFWD_FWLTHTSR2_LTHMTRNS_Msk (0x1f0000UL) /*!< LTHMTRNS (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTSR2_LTHMTRVS_Pos (31UL) /*!< LTHMTRVS (Bit 31) */ + #define R_MFWD_FWLTHTSR2_LTHMTRVS_Msk (0x80000000UL) /*!< LTHMTRVS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTSR3 ======================================================= */ + #define R_MFWD_FWLTHTSR3_LTHRNS_Pos (0UL) /*!< LTHRNS (Bit 0) */ + #define R_MFWD_FWLTHTSR3_LTHRNS_Msk (0xffUL) /*!< LTHRNS (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTSR3_LTHRVS_Pos (15UL) /*!< LTHRVS (Bit 15) */ + #define R_MFWD_FWLTHTSR3_LTHRVS_Msk (0x8000UL) /*!< LTHRVS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR3_LTHSLVS_Pos (16UL) /*!< LTHSLVS (Bit 16) */ + #define R_MFWD_FWLTHTSR3_LTHSLVS_Msk (0x7f0000UL) /*!< LTHSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTSR40 ======================================================= */ + #define R_MFWD_FWLTHTSR40_LTHCSDS_Pos (0UL) /*!< LTHCSDS (Bit 0) */ + #define R_MFWD_FWLTHTSR40_LTHCSDS_Msk (0x7fUL) /*!< LTHCSDS (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWLTHTSR5 ======================================================= */ + #define R_MFWD_FWLTHTSR5_LTHDVS_Pos (0UL) /*!< LTHDVS (Bit 0) */ + #define R_MFWD_FWLTHTSR5_LTHDVS_Msk (0x7fUL) /*!< LTHDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTSR5_LTHIPVS_Pos (16UL) /*!< LTHIPVS (Bit 16) */ + #define R_MFWD_FWLTHTSR5_LTHIPVS_Msk (0x70000UL) /*!< LTHIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTSR5_LTHIPUS_Pos (19UL) /*!< LTHIPUS (Bit 19) */ + #define R_MFWD_FWLTHTSR5_LTHIPUS_Msk (0x80000UL) /*!< LTHIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR5_LTHEMES_Pos (20UL) /*!< LTHEMES (Bit 20) */ + #define R_MFWD_FWLTHTSR5_LTHEMES_Msk (0x100000UL) /*!< LTHEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTSR5_LTHCMES_Pos (21UL) /*!< LTHCMES (Bit 21) */ + #define R_MFWD_FWLTHTSR5_LTHCMES_Msk (0x200000UL) /*!< LTHCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWLTHTR ======================================================== */ + #define R_MFWD_FWLTHTR_LTHAR_Pos (0UL) /*!< LTHAR (Bit 0) */ + #define R_MFWD_FWLTHTR_LTHAR_Msk (0x3ffUL) /*!< LTHAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWLTHTRR0 ======================================================= */ + #define R_MFWD_FWLTHTRR0_LTHREF_Pos (0UL) /*!< LTHREF (Bit 0) */ + #define R_MFWD_FWLTHTRR0_LTHREF_Msk (0x1UL) /*!< LTHREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR0_LTHEVR_Pos (1UL) /*!< LTHEVR (Bit 1) */ + #define R_MFWD_FWLTHTRR0_LTHEVR_Msk (0x2UL) /*!< LTHEVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR0_LTHTR_Pos (31UL) /*!< LTHTR (Bit 31) */ + #define R_MFWD_FWLTHTRR0_LTHTR_Msk (0x80000000UL) /*!< LTHTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR1 ======================================================= */ + #define R_MFWD_FWLTHTRR1_LTHSRP0_Pos (0UL) /*!< LTHSRP0 (Bit 0) */ + #define R_MFWD_FWLTHTRR1_LTHSRP0_Msk (0x7UL) /*!< LTHSRP0 (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTRR1_LTHSLR_Pos (8UL) /*!< LTHSLR (Bit 8) */ + #define R_MFWD_FWLTHTRR1_LTHSLR_Msk (0x100UL) /*!< LTHSLR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR2 ======================================================= */ + #define R_MFWD_FWLTHTRR2_LTHSRP1_Pos (0UL) /*!< LTHSRP1 (Bit 0) */ + #define R_MFWD_FWLTHTRR2_LTHSRP1_Msk (0xffffffffUL) /*!< LTHSRP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR3 ======================================================= */ + #define R_MFWD_FWLTHTRR3_LTHSRP2_Pos (0UL) /*!< LTHSRP2 (Bit 0) */ + #define R_MFWD_FWLTHTRR3_LTHSRP2_Msk (0xffffffffUL) /*!< LTHSRP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR4 ======================================================= */ + #define R_MFWD_FWLTHTRR4_LTHSRP3_Pos (0UL) /*!< LTHSRP3 (Bit 0) */ + #define R_MFWD_FWLTHTRR4_LTHSRP3_Msk (0xffffffffUL) /*!< LTHSRP3 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR5 ======================================================= */ + #define R_MFWD_FWLTHTRR5_LTHSRP4_Pos (0UL) /*!< LTHSRP4 (Bit 0) */ + #define R_MFWD_FWLTHTRR5_LTHSRP4_Msk (0xffffffffUL) /*!< LTHSRP4 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWLTHTRR6 ======================================================= */ + #define R_MFWD_FWLTHTRR6_LTHMSDUNR_Pos (16UL) /*!< LTHMSDUNR (Bit 16) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUNR_Msk (0xf0000UL) /*!< LTHMSDUNR (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUVR_Pos (31UL) /*!< LTHMSDUVR (Bit 31) */ + #define R_MFWD_FWLTHTRR6_LTHMSDUVR_Msk (0x80000000UL) /*!< LTHMSDUVR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR7 ======================================================= */ + #define R_MFWD_FWLTHTRR7_LTHFRERNR_Pos (0UL) /*!< LTHFRERNR (Bit 0) */ + #define R_MFWD_FWLTHTRR7_LTHFRERNR_Msk (0x3fUL) /*!< LTHFRERNR (Bitfield-Mask: 0x3f) */ + #define R_MFWD_FWLTHTRR7_LTHFRERVR_Pos (15UL) /*!< LTHFRERVR (Bit 15) */ + #define R_MFWD_FWLTHTRR7_LTHFRERVR_Msk (0x8000UL) /*!< LTHFRERVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR7_LTHMTRNR_Pos (16UL) /*!< LTHMTRNR (Bit 16) */ + #define R_MFWD_FWLTHTRR7_LTHMTRNR_Msk (0x1f0000UL) /*!< LTHMTRNR (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWLTHTRR7_LTHMTRVR_Pos (31UL) /*!< LTHMTRVR (Bit 31) */ + #define R_MFWD_FWLTHTRR7_LTHMTRVR_Msk (0x80000000UL) /*!< LTHMTRVR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWLTHTRR8 ======================================================= */ + #define R_MFWD_FWLTHTRR8_LTHRNR_Pos (0UL) /*!< LTHRNR (Bit 0) */ + #define R_MFWD_FWLTHTRR8_LTHRNR_Msk (0xffUL) /*!< LTHRNR (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWLTHTRR8_LTHRVR_Pos (15UL) /*!< LTHRVR (Bit 15) */ + #define R_MFWD_FWLTHTRR8_LTHRVR_Msk (0x8000UL) /*!< LTHRVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR8_LTHSLVR_Pos (16UL) /*!< LTHSLVR (Bit 16) */ + #define R_MFWD_FWLTHTRR8_LTHSLVR_Msk (0x7f0000UL) /*!< LTHSLVR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTRR90 ======================================================= */ + #define R_MFWD_FWLTHTRR90_LTHCSDR_Pos (0UL) /*!< LTHCSDR (Bit 0) */ + #define R_MFWD_FWLTHTRR90_LTHCSDR_Msk (0x7fUL) /*!< LTHCSDR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWLTHTRR10 ======================================================= */ + #define R_MFWD_FWLTHTRR10_LTHDVR_Pos (0UL) /*!< LTHDVR (Bit 0) */ + #define R_MFWD_FWLTHTRR10_LTHDVR_Msk (0x7fUL) /*!< LTHDVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWLTHTRR10_LTHIPVR_Pos (16UL) /*!< LTHIPVR (Bit 16) */ + #define R_MFWD_FWLTHTRR10_LTHIPVR_Msk (0x70000UL) /*!< LTHIPVR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWLTHTRR10_LTHIPUR_Pos (19UL) /*!< LTHIPUR (Bit 19) */ + #define R_MFWD_FWLTHTRR10_LTHIPUR_Msk (0x80000UL) /*!< LTHIPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR10_LTHEMER_Pos (20UL) /*!< LTHEMER (Bit 20) */ + #define R_MFWD_FWLTHTRR10_LTHEMER_Msk (0x100000UL) /*!< LTHEMER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWLTHTRR10_LTHCMER_Pos (21UL) /*!< LTHCMER (Bit 21) */ + #define R_MFWD_FWLTHTRR10_LTHCMER_Msk (0x200000UL) /*!< LTHCMER (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACHEC ======================================================== */ + #define R_MFWD_FWMACHEC_MACHMC_Pos (0UL) /*!< MACHMC (Bit 0) */ + #define R_MFWD_FWMACHEC_MACHMC_Msk (0x7ffUL) /*!< MACHMC (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWMACHEC_MACHMUE_Pos (16UL) /*!< MACHMUE (Bit 16) */ + #define R_MFWD_FWMACHEC_MACHMUE_Msk (0xfff0000UL) /*!< MACHMUE (Bitfield-Mask: 0xfff) */ +/* ======================================================== FWMACHC ======================================================== */ + #define R_MFWD_FWMACHC_MACHE_Pos (0UL) /*!< MACHE (Bit 0) */ + #define R_MFWD_FWMACHC_MACHE_Msk (0x7ffUL) /*!< MACHE (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWMACTL0 ======================================================== */ + #define R_MFWD_FWMACTL0_MACSLL_Pos (8UL) /*!< MACSLL (Bit 8) */ + #define R_MFWD_FWMACTL0_MACSLL_Msk (0x100UL) /*!< MACSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACDEL_Pos (9UL) /*!< MACDEL (Bit 9) */ + #define R_MFWD_FWMACTL0_MACDEL_Msk (0x200UL) /*!< MACDEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACHLDL_Pos (10UL) /*!< MACHLDL (Bit 10) */ + #define R_MFWD_FWMACTL0_MACHLDL_Msk (0x400UL) /*!< MACHLDL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL0_MACED_Pos (16UL) /*!< MACED (Bit 16) */ + #define R_MFWD_FWMACTL0_MACED_Msk (0x10000UL) /*!< MACED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTL1 ======================================================== */ + #define R_MFWD_FWMACTL1_MACMALP0_Pos (0UL) /*!< MACMALP0 (Bit 0) */ + #define R_MFWD_FWMACTL1_MACMALP0_Msk (0xffffUL) /*!< MACMALP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTL2 ======================================================== */ + #define R_MFWD_FWMACTL2_MACMALP1_Pos (0UL) /*!< MACMALP1 (Bit 0) */ + #define R_MFWD_FWMACTL2_MACMALP1_Msk (0xffffffffUL) /*!< MACMALP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTL3 ======================================================== */ + #define R_MFWD_FWMACTL3_MACSSLVL_Pos (0UL) /*!< MACSSLVL (Bit 0) */ + #define R_MFWD_FWMACTL3_MACSSLVL_Msk (0x7fUL) /*!< MACSSLVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTL3_MACDSLVL_Pos (16UL) /*!< MACDSLVL (Bit 16) */ + #define R_MFWD_FWMACTL3_MACDSLVL_Msk (0x7f0000UL) /*!< MACDSLVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTL40 ======================================================= */ + #define R_MFWD_FWMACTL40_MACCSDL_Pos (0UL) /*!< MACCSDL (Bit 0) */ + #define R_MFWD_FWMACTL40_MACCSDL_Msk (0x7fUL) /*!< MACCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTL5 ======================================================== */ + #define R_MFWD_FWMACTL5_MACDVL_Pos (0UL) /*!< MACDVL (Bit 0) */ + #define R_MFWD_FWMACTL5_MACDVL_Msk (0x7fUL) /*!< MACDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTL5_MACIPVL_Pos (16UL) /*!< MACIPVL (Bit 16) */ + #define R_MFWD_FWMACTL5_MACIPVL_Msk (0x70000UL) /*!< MACIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTL5_MACIPUL_Pos (19UL) /*!< MACIPUL (Bit 19) */ + #define R_MFWD_FWMACTL5_MACIPUL_Msk (0x80000UL) /*!< MACIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL5_MACEMEL_Pos (20UL) /*!< MACEMEL (Bit 20) */ + #define R_MFWD_FWMACTL5_MACEMEL_Msk (0x100000UL) /*!< MACEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTL5_MACCMEL_Pos (21UL) /*!< MACCMEL (Bit 21) */ + #define R_MFWD_FWMACTL5_MACCMEL_Msk (0x200000UL) /*!< MACCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTLR ======================================================== */ + #define R_MFWD_FWMACTLR_MACLF_Pos (0UL) /*!< MACLF (Bit 0) */ + #define R_MFWD_FWMACTLR_MACLF_Msk (0x1UL) /*!< MACLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLSF_Pos (1UL) /*!< MACLSF (Bit 1) */ + #define R_MFWD_FWMACTLR_MACLSF_Msk (0x2UL) /*!< MACLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLEF_Pos (2UL) /*!< MACLEF (Bit 2) */ + #define R_MFWD_FWMACTLR_MACLEF_Msk (0x4UL) /*!< MACLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLO_Pos (3UL) /*!< MACLO (Bit 3) */ + #define R_MFWD_FWMACTLR_MACLO_Msk (0x8UL) /*!< MACLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTLR_MACLCN_Pos (16UL) /*!< MACLCN (Bit 16) */ + #define R_MFWD_FWMACTLR_MACLCN_Msk (0x3ff0000UL) /*!< MACLCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWMACTLR_MACTL_Pos (31UL) /*!< MACTL (Bit 31) */ + #define R_MFWD_FWMACTLR_MACTL_Msk (0x80000000UL) /*!< MACTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTIM ======================================================== */ + #define R_MFWD_FWMACTIM_MACTIOG_Pos (0UL) /*!< MACTIOG (Bit 0) */ + #define R_MFWD_FWMACTIM_MACTIOG_Msk (0x1UL) /*!< MACTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTIM_MACTR_Pos (1UL) /*!< MACTR (Bit 1) */ + #define R_MFWD_FWMACTIM_MACTR_Msk (0x2UL) /*!< MACTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTEM ======================================================== */ + #define R_MFWD_FWMACTEM_MACTEN_Pos (0UL) /*!< MACTEN (Bit 0) */ + #define R_MFWD_FWMACTEM_MACTEN_Msk (0x7ffUL) /*!< MACTEN (Bitfield-Mask: 0x7ff) */ + #define R_MFWD_FWMACTEM_MACTUEN_Pos (16UL) /*!< MACTUEN (Bit 16) */ + #define R_MFWD_FWMACTEM_MACTUEN_Msk (0x7ff0000UL) /*!< MACTUEN (Bitfield-Mask: 0x7ff) */ +/* ======================================================= FWMACTS0 ======================================================== */ + #define R_MFWD_FWMACTS0_MACMASP0_Pos (0UL) /*!< MACMASP0 (Bit 0) */ + #define R_MFWD_FWMACTS0_MACMASP0_Msk (0xffffUL) /*!< MACMASP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTS1 ======================================================== */ + #define R_MFWD_FWMACTS1_MACMASP1_Pos (0UL) /*!< MACMASP1 (Bit 0) */ + #define R_MFWD_FWMACTS1_MACMASP1_Msk (0xffffffffUL) /*!< MACMASP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTSR0 ======================================================= */ + #define R_MFWD_FWMACTSR0_MACSEF_Pos (0UL) /*!< MACSEF (Bit 0) */ + #define R_MFWD_FWMACTSR0_MACSEF_Msk (0x1UL) /*!< MACSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSNF_Pos (1UL) /*!< MACSNF (Bit 1) */ + #define R_MFWD_FWMACTSR0_MACSNF_Msk (0x2UL) /*!< MACSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSLS_Pos (8UL) /*!< MACSLS (Bit 8) */ + #define R_MFWD_FWMACTSR0_MACSLS_Msk (0x100UL) /*!< MACSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACDES_Pos (9UL) /*!< MACDES (Bit 9) */ + #define R_MFWD_FWMACTSR0_MACDES_Msk (0x200UL) /*!< MACDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACHLDS_Pos (10UL) /*!< MACHLDS (Bit 10) */ + #define R_MFWD_FWMACTSR0_MACHLDS_Msk (0x400UL) /*!< MACHLDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR0_MACSCN_Pos (16UL) /*!< MACSCN (Bit 16) */ + #define R_MFWD_FWMACTSR0_MACSCN_Msk (0x3ff0000UL) /*!< MACSCN (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWMACTSR0_MACTS_Pos (31UL) /*!< MACTS (Bit 31) */ + #define R_MFWD_FWMACTSR0_MACTS_Msk (0x80000000UL) /*!< MACTS (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTSR1 ======================================================= */ + #define R_MFWD_FWMACTSR1_MACSSLVS_Pos (0UL) /*!< MACSSLVS (Bit 0) */ + #define R_MFWD_FWMACTSR1_MACSSLVS_Msk (0x7fUL) /*!< MACSSLVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTSR1_MACDSLVS_Pos (16UL) /*!< MACDSLVS (Bit 16) */ + #define R_MFWD_FWMACTSR1_MACDSLVS_Msk (0x7f0000UL) /*!< MACDSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWMACTSR20 ======================================================= */ + #define R_MFWD_FWMACTSR20_MACCSDS_Pos (0UL) /*!< MACCSDS (Bit 0) */ + #define R_MFWD_FWMACTSR20_MACCSDS_Msk (0x7fUL) /*!< MACCSDS (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTSR3 ======================================================= */ + #define R_MFWD_FWMACTSR3_MACDVS_Pos (0UL) /*!< MACDVS (Bit 0) */ + #define R_MFWD_FWMACTSR3_MACDVS_Msk (0x7fUL) /*!< MACDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTSR3_MACIPVS_Pos (16UL) /*!< MACIPVS (Bit 16) */ + #define R_MFWD_FWMACTSR3_MACIPVS_Msk (0x70000UL) /*!< MACIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTSR3_MACIPUS_Pos (19UL) /*!< MACIPUS (Bit 19) */ + #define R_MFWD_FWMACTSR3_MACIPUS_Msk (0x80000UL) /*!< MACIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR3_MACEMES_Pos (20UL) /*!< MACEMES (Bit 20) */ + #define R_MFWD_FWMACTSR3_MACEMES_Msk (0x100000UL) /*!< MACEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTSR3_MACCMES_Pos (21UL) /*!< MACCMES (Bit 21) */ + #define R_MFWD_FWMACTSR3_MACCMES_Msk (0x200000UL) /*!< MACCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMACTR ======================================================== */ + #define R_MFWD_FWMACTR_MACAR_Pos (0UL) /*!< MACAR (Bit 0) */ + #define R_MFWD_FWMACTR_MACAR_Msk (0x3ffUL) /*!< MACAR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWMACTRR0 ======================================================= */ + #define R_MFWD_FWMACTRR0_MACEVR_Pos (0UL) /*!< MACEVR (Bit 0) */ + #define R_MFWD_FWMACTRR0_MACEVR_Msk (0x1UL) /*!< MACEVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR0_MACREF_Pos (1UL) /*!< MACREF (Bit 1) */ + #define R_MFWD_FWMACTRR0_MACREF_Msk (0x2UL) /*!< MACREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR0_MACTR_Pos (31UL) /*!< MACTR (Bit 31) */ + #define R_MFWD_FWMACTRR0_MACTR_Msk (0x80000000UL) /*!< MACTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTRR1 ======================================================= */ + #define R_MFWD_FWMACTRR1_MACSLR_Pos (8UL) /*!< MACSLR (Bit 8) */ + #define R_MFWD_FWMACTRR1_MACSLR_Msk (0x100UL) /*!< MACSLR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACDER_Pos (9UL) /*!< MACDER (Bit 9) */ + #define R_MFWD_FWMACTRR1_MACDER_Msk (0x200UL) /*!< MACDER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACHLDR_Pos (10UL) /*!< MACHLDR (Bit 10) */ + #define R_MFWD_FWMACTRR1_MACHLDR_Msk (0x400UL) /*!< MACHLDR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR1_MACABR_Pos (11UL) /*!< MACABR (Bit 11) */ + #define R_MFWD_FWMACTRR1_MACABR_Msk (0x800UL) /*!< MACABR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACTRR2 ======================================================= */ + #define R_MFWD_FWMACTRR2_MACMARP0_Pos (0UL) /*!< MACMARP0 (Bit 0) */ + #define R_MFWD_FWMACTRR2_MACMARP0_Msk (0xffffUL) /*!< MACMARP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACTRR3 ======================================================= */ + #define R_MFWD_FWMACTRR3_MACMARP1_Pos (0UL) /*!< MACMARP1 (Bit 0) */ + #define R_MFWD_FWMACTRR3_MACMARP1_Msk (0xffffffffUL) /*!< MACMARP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMACTRR4 ======================================================= */ + #define R_MFWD_FWMACTRR4_MACSSLVR_Pos (0UL) /*!< MACSSLVR (Bit 0) */ + #define R_MFWD_FWMACTRR4_MACSSLVR_Msk (0x7fUL) /*!< MACSSLVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTRR4_MACDSLVR_Pos (16UL) /*!< MACDSLVR (Bit 16) */ + #define R_MFWD_FWMACTRR4_MACDSLVR_Msk (0x7f0000UL) /*!< MACDSLVR (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWMACTRR50 ======================================================= */ + #define R_MFWD_FWMACTRR50_MACCSDR_Pos (0UL) /*!< MACCSDR (Bit 0) */ + #define R_MFWD_FWMACTRR50_MACCSDR_Msk (0x7fUL) /*!< MACCSDR (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWMACTRR6 ======================================================= */ + #define R_MFWD_FWMACTRR6_MACDVR_Pos (0UL) /*!< MACDVR (Bit 0) */ + #define R_MFWD_FWMACTRR6_MACDVR_Msk (0x7fUL) /*!< MACDVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWMACTRR6_MACIPVR_Pos (16UL) /*!< MACIPVR (Bit 16) */ + #define R_MFWD_FWMACTRR6_MACIPVR_Msk (0x70000UL) /*!< MACIPVR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWMACTRR6_MACIPUR_Pos (19UL) /*!< MACIPUR (Bit 19) */ + #define R_MFWD_FWMACTRR6_MACIPUR_Msk (0x80000UL) /*!< MACIPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR6_MACEMER_Pos (20UL) /*!< MACEMER (Bit 20) */ + #define R_MFWD_FWMACTRR6_MACEMER_Msk (0x100000UL) /*!< MACEMER (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACTRR6_MACCMER_Pos (21UL) /*!< MACCMER (Bit 21) */ + #define R_MFWD_FWMACTRR6_MACCMER_Msk (0x200000UL) /*!< MACCMER (Bitfield-Mask: 0x01) */ +/* ====================================================== FWMACAGUSPC ====================================================== */ + #define R_MFWD_FWMACAGUSPC_MACAGUSP_Pos (0UL) /*!< MACAGUSP (Bit 0) */ + #define R_MFWD_FWMACAGUSPC_MACAGUSP_Msk (0x3ffUL) /*!< MACAGUSP (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWMACAGC ======================================================== */ + #define R_MFWD_FWMACAGC_MACAGT_Pos (0UL) /*!< MACAGT (Bit 0) */ + #define R_MFWD_FWMACAGC_MACAGT_Msk (0xffffUL) /*!< MACAGT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWMACAGC_MACAGE_Pos (16UL) /*!< MACAGE (Bit 16) */ + #define R_MFWD_FWMACAGC_MACAGE_Msk (0x10000UL) /*!< MACAGE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGSL_Pos (17UL) /*!< MACAGSL (Bit 17) */ + #define R_MFWD_FWMACAGC_MACAGSL_Msk (0x20000UL) /*!< MACAGSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGPM_Pos (18UL) /*!< MACAGPM (Bit 18) */ + #define R_MFWD_FWMACAGC_MACAGPM_Msk (0x40000UL) /*!< MACAGPM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACDES_Pos (24UL) /*!< MACDES (Bit 24) */ + #define R_MFWD_FWMACAGC_MACDES_Msk (0x1000000UL) /*!< MACDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACAGOG_Pos (28UL) /*!< MACAGOG (Bit 28) */ + #define R_MFWD_FWMACAGC_MACAGOG_Msk (0x10000000UL) /*!< MACAGOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMACAGC_MACDESOG_Pos (29UL) /*!< MACDESOG (Bit 29) */ + #define R_MFWD_FWMACAGC_MACDESOG_Msk (0x20000000UL) /*!< MACDESOG (Bitfield-Mask: 0x01) */ +/* ======================================================= FWMACAGM0 ======================================================= */ + #define R_MFWD_FWMACAGM0_AGMACAP0_Pos (0UL) /*!< AGMACAP0 (Bit 0) */ + #define R_MFWD_FWMACAGM0_AGMACAP0_Msk (0xffffUL) /*!< AGMACAP0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWMACAGM1 ======================================================= */ + #define R_MFWD_FWMACAGM1_AGMACAP1_Pos (0UL) /*!< AGMACAP1 (Bit 0) */ + #define R_MFWD_FWMACAGM1_AGMACAP1_Msk (0xffffffffUL) /*!< AGMACAP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWVLANTEC ======================================================= */ + #define R_MFWD_FWVLANTEC_VLANTMUE_Pos (16UL) /*!< VLANTMUE (Bit 16) */ + #define R_MFWD_FWVLANTEC_VLANTMUE_Msk (0x1fff0000UL) /*!< VLANTMUE (Bitfield-Mask: 0x1fff) */ +/* ======================================================= FWVLANTL0 ======================================================= */ + #define R_MFWD_FWVLANTL0_VLANSLL_Pos (8UL) /*!< VLANSLL (Bit 8) */ + #define R_MFWD_FWVLANTL0_VLANSLL_Msk (0x100UL) /*!< VLANSLL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL0_VLANHLDL_Pos (10UL) /*!< VLANHLDL (Bit 10) */ + #define R_MFWD_FWVLANTL0_VLANHLDL_Msk (0x400UL) /*!< VLANHLDL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL0_VLANED_Pos (16UL) /*!< VLANED (Bit 16) */ + #define R_MFWD_FWVLANTL0_VLANED_Msk (0x10000UL) /*!< VLANED (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTL1 ======================================================= */ + #define R_MFWD_FWVLANTL1_VLANVIDL_Pos (0UL) /*!< VLANVIDL (Bit 0) */ + #define R_MFWD_FWVLANTL1_VLANVIDL_Msk (0xfffUL) /*!< VLANVIDL (Bitfield-Mask: 0xfff) */ +/* ======================================================= FWVLANTL2 ======================================================= */ + #define R_MFWD_FWVLANTL2_VLANSLVL_Pos (0UL) /*!< VLANSLVL (Bit 0) */ + #define R_MFWD_FWVLANTL2_VLANSLVL_Msk (0x7fUL) /*!< VLANSLVL (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTL30 ======================================================= */ + #define R_MFWD_FWVLANTL30_VLANCSDL_Pos (0UL) /*!< VLANCSDL (Bit 0) */ + #define R_MFWD_FWVLANTL30_VLANCSDL_Msk (0x7fUL) /*!< VLANCSDL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWVLANTL4 ======================================================= */ + #define R_MFWD_FWVLANTL4_VLANDVL_Pos (0UL) /*!< VLANDVL (Bit 0) */ + #define R_MFWD_FWVLANTL4_VLANDVL_Msk (0x7fUL) /*!< VLANDVL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWVLANTL4_VLANIPVL_Pos (16UL) /*!< VLANIPVL (Bit 16) */ + #define R_MFWD_FWVLANTL4_VLANIPVL_Msk (0x70000UL) /*!< VLANIPVL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWVLANTL4_VLANIPUL_Pos (19UL) /*!< VLANIPUL (Bit 19) */ + #define R_MFWD_FWVLANTL4_VLANIPUL_Msk (0x80000UL) /*!< VLANIPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL4_VLANEMEL_Pos (20UL) /*!< VLANEMEL (Bit 20) */ + #define R_MFWD_FWVLANTL4_VLANEMEL_Msk (0x100000UL) /*!< VLANEMEL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTL4_VLANCMEL_Pos (21UL) /*!< VLANCMEL (Bit 21) */ + #define R_MFWD_FWVLANTL4_VLANCMEL_Msk (0x200000UL) /*!< VLANCMEL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTLR ======================================================= */ + #define R_MFWD_FWVLANTLR_VLANLF_Pos (0UL) /*!< VLANLF (Bit 0) */ + #define R_MFWD_FWVLANTLR_VLANLF_Msk (0x1UL) /*!< VLANLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLSF_Pos (1UL) /*!< VLANLSF (Bit 1) */ + #define R_MFWD_FWVLANTLR_VLANLSF_Msk (0x2UL) /*!< VLANLSF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLEF_Pos (2UL) /*!< VLANLEF (Bit 2) */ + #define R_MFWD_FWVLANTLR_VLANLEF_Msk (0x4UL) /*!< VLANLEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANLO_Pos (3UL) /*!< VLANLO (Bit 3) */ + #define R_MFWD_FWVLANTLR_VLANLO_Msk (0x8UL) /*!< VLANLO (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTLR_VLANTL_Pos (31UL) /*!< VLANTL (Bit 31) */ + #define R_MFWD_FWVLANTLR_VLANTL_Msk (0x80000000UL) /*!< VLANTL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTIM ======================================================= */ + #define R_MFWD_FWVLANTIM_VLANTIOG_Pos (0UL) /*!< VLANTIOG (Bit 0) */ + #define R_MFWD_FWVLANTIM_VLANTIOG_Msk (0x1UL) /*!< VLANTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTIM_VLANTR_Pos (1UL) /*!< VLANTR (Bit 1) */ + #define R_MFWD_FWVLANTIM_VLANTR_Msk (0x2UL) /*!< VLANTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWVLANTEM ======================================================= */ + #define R_MFWD_FWVLANTEM_VLANTEN_Pos (0UL) /*!< VLANTEN (Bit 0) */ + #define R_MFWD_FWVLANTEM_VLANTEN_Msk (0x1fffUL) /*!< VLANTEN (Bitfield-Mask: 0x1fff) */ + #define R_MFWD_FWVLANTEM_VLANTUEN_Pos (16UL) /*!< VLANTUEN (Bit 16) */ + #define R_MFWD_FWVLANTEM_VLANTUEN_Msk (0x1fff0000UL) /*!< VLANTUEN (Bitfield-Mask: 0x1fff) */ +/* ======================================================= FWVLANTS ======================================================== */ + #define R_MFWD_FWVLANTS_VLANVIDS_Pos (0UL) /*!< VLANVIDS (Bit 0) */ + #define R_MFWD_FWVLANTS_VLANVIDS_Msk (0xfffUL) /*!< VLANVIDS (Bitfield-Mask: 0xfff) */ +/* ====================================================== FWVLANTSR0 ======================================================= */ + #define R_MFWD_FWVLANTSR0_VLANSEF_Pos (0UL) /*!< VLANSEF (Bit 0) */ + #define R_MFWD_FWVLANTSR0_VLANSEF_Msk (0x1UL) /*!< VLANSEF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANSNF_Pos (1UL) /*!< VLANSNF (Bit 1) */ + #define R_MFWD_FWVLANTSR0_VLANSNF_Msk (0x2UL) /*!< VLANSNF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANSLS_Pos (8UL) /*!< VLANSLS (Bit 8) */ + #define R_MFWD_FWVLANTSR0_VLANSLS_Msk (0x100UL) /*!< VLANSLS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANHLDS_Pos (10UL) /*!< VLANHLDS (Bit 10) */ + #define R_MFWD_FWVLANTSR0_VLANHLDS_Msk (0x400UL) /*!< VLANHLDS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR0_VLANTS_Pos (31UL) /*!< VLANTS (Bit 31) */ + #define R_MFWD_FWVLANTSR0_VLANTS_Msk (0x80000000UL) /*!< VLANTS (Bitfield-Mask: 0x01) */ +/* ====================================================== FWVLANTSR1 ======================================================= */ + #define R_MFWD_FWVLANTSR1_VLANSLVS_Pos (0UL) /*!< VLANSLVS (Bit 0) */ + #define R_MFWD_FWVLANTSR1_VLANSLVS_Msk (0x7fUL) /*!< VLANSLVS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTSR20 ====================================================== */ + #define R_MFWD_FWVLANTSR20_VLANCSDS_Pos (0UL) /*!< VLANCSDS (Bit 0) */ + #define R_MFWD_FWVLANTSR20_VLANCSDS_Msk (0x7fUL) /*!< VLANCSDS (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWVLANTSR3 ======================================================= */ + #define R_MFWD_FWVLANTSR3_VLANDVS_Pos (0UL) /*!< VLANDVS (Bit 0) */ + #define R_MFWD_FWVLANTSR3_VLANDVS_Msk (0x7fUL) /*!< VLANDVS (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWVLANTSR3_VLANIPVS_Pos (16UL) /*!< VLANIPVS (Bit 16) */ + #define R_MFWD_FWVLANTSR3_VLANIPVS_Msk (0x70000UL) /*!< VLANIPVS (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWVLANTSR3_VLANIPUS_Pos (19UL) /*!< VLANIPUS (Bit 19) */ + #define R_MFWD_FWVLANTSR3_VLANIPUS_Msk (0x80000UL) /*!< VLANIPUS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR3_VLANEMES_Pos (20UL) /*!< VLANEMES (Bit 20) */ + #define R_MFWD_FWVLANTSR3_VLANEMES_Msk (0x100000UL) /*!< VLANEMES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWVLANTSR3_VLANCMES_Pos (21UL) /*!< VLANCMES (Bit 21) */ + #define R_MFWD_FWVLANTSR3_VLANCMES_Msk (0x200000UL) /*!< VLANCMES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC0 ======================================================== */ + #define R_MFWD_FWPBFC0_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC0_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC0_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC0_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC0_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC0_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC0_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC0_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC0_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC0_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC0_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC0_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC0_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC0_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC1 ======================================================== */ + #define R_MFWD_FWPBFC1_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC1_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC1_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC1_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC1_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC1_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC1_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC1_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC1_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC1_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC1_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC1_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC1_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC1_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ======================================================== FWPBFC2 ======================================================== */ + #define R_MFWD_FWPBFC2_PBDV_Pos (0UL) /*!< PBDV (Bit 0) */ + #define R_MFWD_FWPBFC2_PBDV_Msk (0x7fUL) /*!< PBDV (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWPBFC2_PBIPV_Pos (16UL) /*!< PBIPV (Bit 16) */ + #define R_MFWD_FWPBFC2_PBIPV_Msk (0x70000UL) /*!< PBIPV (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWPBFC2_PBIPU_Pos (19UL) /*!< PBIPU (Bit 19) */ + #define R_MFWD_FWPBFC2_PBIPU_Msk (0x80000UL) /*!< PBIPU (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBEME_Pos (20UL) /*!< PBEME (Bit 20) */ + #define R_MFWD_FWPBFC2_PBEME_Msk (0x100000UL) /*!< PBEME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBCME_Pos (21UL) /*!< PBCME (Bit 21) */ + #define R_MFWD_FWPBFC2_PBCME_Msk (0x200000UL) /*!< PBCME (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_PBSL_Pos (22UL) /*!< PBSL (Bit 22) */ + #define R_MFWD_FWPBFC2_PBSL_Msk (0x400000UL) /*!< PBSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP4PDE_Pos (23UL) /*!< IP4PDE (Bit 23) */ + #define R_MFWD_FWPBFC2_IP4PDE_Msk (0x800000UL) /*!< IP4PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP4PDM_Pos (24UL) /*!< IP4PDM (Bit 24) */ + #define R_MFWD_FWPBFC2_IP4PDM_Msk (0x1000000UL) /*!< IP4PDM (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_IP6PDE_Pos (25UL) /*!< IP6PDE (Bit 25) */ + #define R_MFWD_FWPBFC2_IP6PDE_Msk (0x2000000UL) /*!< IP6PDE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPBFC2_FAIFP_Pos (26UL) /*!< FAIFP (Bit 26) */ + #define R_MFWD_FWPBFC2_FAIFP_Msk (0x4000000UL) /*!< FAIFP (Bitfield-Mask: 0x01) */ +/* ====================================================== FWPBFCSDC00 ====================================================== */ + #define R_MFWD_FWPBFCSDC00_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC00_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWPBFCSDC01 ====================================================== */ + #define R_MFWD_FWPBFCSDC01_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC01_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ====================================================== FWPBFCSDC02 ====================================================== */ + #define R_MFWD_FWPBFCSDC02_PBCSD_Pos (0UL) /*!< PBCSD (Bit 0) */ + #define R_MFWD_FWPBFCSDC02_PBCSD_Msk (0x7fUL) /*!< PBCSD (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWL23URL0 ======================================================= */ + #define R_MFWD_FWL23URL0_L23URNL_Pos (0UL) /*!< L23URNL (Bit 0) */ + #define R_MFWD_FWL23URL0_L23URNL_Msk (0xffUL) /*!< L23URNL (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URL0_L23URPVL_Pos (16UL) /*!< L23URPVL (Bit 16) */ + #define R_MFWD_FWL23URL0_L23URPVL_Msk (0x7f0000UL) /*!< L23URPVL (Bitfield-Mask: 0x7f) */ +/* ======================================================= FWL23URL1 ======================================================= */ + #define R_MFWD_FWL23URL1_L23UMDALP0_Pos (0UL) /*!< L23UMDALP0 (Bit 0) */ + #define R_MFWD_FWL23URL1_L23UMDALP0_Msk (0xffffUL) /*!< L23UMDALP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWL23URL1_L23UTTLUL_Pos (16UL) /*!< L23UTTLUL (Bit 16) */ + #define R_MFWD_FWL23URL1_L23UTTLUL_Msk (0x10000UL) /*!< L23UTTLUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UMDAUL_Pos (17UL) /*!< L23UMDAUL (Bit 17) */ + #define R_MFWD_FWL23URL1_L23UMDAUL_Msk (0x20000UL) /*!< L23UMDAUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UMSAUL_Pos (18UL) /*!< L23UMSAUL (Bit 18) */ + #define R_MFWD_FWL23URL1_L23UMSAUL_Msk (0x40000UL) /*!< L23UMSAUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCVIDUL_Pos (19UL) /*!< L23UCVIDUL (Bit 19) */ + #define R_MFWD_FWL23URL1_L23UCVIDUL_Msk (0x80000UL) /*!< L23UCVIDUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCPCPUL_Pos (20UL) /*!< L23UCPCPUL (Bit 20) */ + #define R_MFWD_FWL23URL1_L23UCPCPUL_Msk (0x100000UL) /*!< L23UCPCPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23UCDEIUL_Pos (21UL) /*!< L23UCDEIUL (Bit 21) */ + #define R_MFWD_FWL23URL1_L23UCDEIUL_Msk (0x200000UL) /*!< L23UCDEIUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USVIDUL_Pos (22UL) /*!< L23USVIDUL (Bit 22) */ + #define R_MFWD_FWL23URL1_L23USVIDUL_Msk (0x400000UL) /*!< L23USVIDUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USPCPUL_Pos (23UL) /*!< L23USPCPUL (Bit 23) */ + #define R_MFWD_FWL23URL1_L23USPCPUL_Msk (0x800000UL) /*!< L23USPCPUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23USDEIUL_Pos (24UL) /*!< L23USDEIUL (Bit 24) */ + #define R_MFWD_FWL23URL1_L23USDEIUL_Msk (0x1000000UL) /*!< L23USDEIUL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL1_L23URTUL_Pos (25UL) /*!< L23URTUL (Bit 25) */ + #define R_MFWD_FWL23URL1_L23URTUL_Msk (0x6000000UL) /*!< L23URTUL (Bitfield-Mask: 0x03) */ +/* ======================================================= FWL23URL2 ======================================================= */ + #define R_MFWD_FWL23URL2_L23UMDALP1_Pos (0UL) /*!< L23UMDALP1 (Bit 0) */ + #define R_MFWD_FWL23URL2_L23UMDALP1_Msk (0xffffffffUL) /*!< L23UMDALP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWL23URL3 ======================================================= */ + #define R_MFWD_FWL23URL3_L23UCVIDL_Pos (0UL) /*!< L23UCVIDL (Bit 0) */ + #define R_MFWD_FWL23URL3_L23UCVIDL_Msk (0xfffUL) /*!< L23UCVIDL (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URL3_L23UCPCPL_Pos (12UL) /*!< L23UCPCPL (Bit 12) */ + #define R_MFWD_FWL23URL3_L23UCPCPL_Msk (0x7000UL) /*!< L23UCPCPL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URL3_L23UCDEIL_Pos (15UL) /*!< L23UCDEIL (Bit 15) */ + #define R_MFWD_FWL23URL3_L23UCDEIL_Msk (0x8000UL) /*!< L23UCDEIL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URL3_L23USVIDL_Pos (16UL) /*!< L23USVIDL (Bit 16) */ + #define R_MFWD_FWL23URL3_L23USVIDL_Msk (0xfff0000UL) /*!< L23USVIDL (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URL3_L23USPCPL_Pos (28UL) /*!< L23USPCPL (Bit 28) */ + #define R_MFWD_FWL23URL3_L23USPCPL_Msk (0x70000000UL) /*!< L23USPCPL (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URL3_L23USDEIL_Pos (31UL) /*!< L23USDEIL (Bit 31) */ + #define R_MFWD_FWL23URL3_L23USDEIL_Msk (0x80000000UL) /*!< L23USDEIL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23URLR ======================================================= */ + #define R_MFWD_FWL23URLR_L23ULF_Pos (0UL) /*!< L23ULF (Bit 0) */ + #define R_MFWD_FWL23URLR_L23ULF_Msk (0x1UL) /*!< L23ULF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URLR_L23URL_Pos (31UL) /*!< L23URL (Bit 31) */ + #define R_MFWD_FWL23URLR_L23URL_Msk (0x80000000UL) /*!< L23URL (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23UTIM ======================================================= */ + #define R_MFWD_FWL23UTIM_L23UTIOG_Pos (0UL) /*!< L23UTIOG (Bit 0) */ + #define R_MFWD_FWL23UTIM_L23UTIOG_Msk (0x1UL) /*!< L23UTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23UTIM_L23UTR_Pos (1UL) /*!< L23UTR (Bit 1) */ + #define R_MFWD_FWL23UTIM_L23UTR_Msk (0x2UL) /*!< L23UTR (Bitfield-Mask: 0x01) */ +/* ======================================================= FWL23URR ======================================================== */ + #define R_MFWD_FWL23URR_L23RNR_Pos (0UL) /*!< L23RNR (Bit 0) */ + #define R_MFWD_FWL23URR_L23RNR_Msk (0xffUL) /*!< L23RNR (Bitfield-Mask: 0xff) */ +/* ====================================================== FWL23URRR0 ======================================================= */ + #define R_MFWD_FWL23URRR0_L23URPVR_Pos (0UL) /*!< L23URPVR (Bit 0) */ + #define R_MFWD_FWL23URRR0_L23URPVR_Msk (0x7fUL) /*!< L23URPVR (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWL23URRR0_L23UREF_Pos (16UL) /*!< L23UREF (Bit 16) */ + #define R_MFWD_FWL23URRR0_L23UREF_Msk (0x10000UL) /*!< L23UREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR0_L23URR_Pos (31UL) /*!< L23URR (Bit 31) */ + #define R_MFWD_FWL23URRR0_L23URR_Msk (0x80000000UL) /*!< L23URR (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URRR1 ======================================================= */ + #define R_MFWD_FWL23URRR1_L23UMDARP0_Pos (0UL) /*!< L23UMDARP0 (Bit 0) */ + #define R_MFWD_FWL23URRR1_L23UMDARP0_Msk (0xffffUL) /*!< L23UMDARP0 (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWL23URRR1_L23UTTLUR_Pos (16UL) /*!< L23UTTLUR (Bit 16) */ + #define R_MFWD_FWL23URRR1_L23UTTLUR_Msk (0x10000UL) /*!< L23UTTLUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UMDAUR_Pos (17UL) /*!< L23UMDAUR (Bit 17) */ + #define R_MFWD_FWL23URRR1_L23UMDAUR_Msk (0x20000UL) /*!< L23UMDAUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UMSAUR_Pos (18UL) /*!< L23UMSAUR (Bit 18) */ + #define R_MFWD_FWL23URRR1_L23UMSAUR_Msk (0x40000UL) /*!< L23UMSAUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCVIDUR_Pos (19UL) /*!< L23UCVIDUR (Bit 19) */ + #define R_MFWD_FWL23URRR1_L23UCVIDUR_Msk (0x80000UL) /*!< L23UCVIDUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCPCPUR_Pos (20UL) /*!< L23UCPCPUR (Bit 20) */ + #define R_MFWD_FWL23URRR1_L23UCPCPUR_Msk (0x100000UL) /*!< L23UCPCPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23UCDEIUR_Pos (21UL) /*!< L23UCDEIUR (Bit 21) */ + #define R_MFWD_FWL23URRR1_L23UCDEIUR_Msk (0x200000UL) /*!< L23UCDEIUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USVIDUR_Pos (22UL) /*!< L23USVIDUR (Bit 22) */ + #define R_MFWD_FWL23URRR1_L23USVIDUR_Msk (0x400000UL) /*!< L23USVIDUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USPCPUR_Pos (23UL) /*!< L23USPCPUR (Bit 23) */ + #define R_MFWD_FWL23URRR1_L23USPCPUR_Msk (0x800000UL) /*!< L23USPCPUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23USDEIUR_Pos (24UL) /*!< L23USDEIUR (Bit 24) */ + #define R_MFWD_FWL23URRR1_L23USDEIUR_Msk (0x1000000UL) /*!< L23USDEIUR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR1_L23URTUR_Pos (25UL) /*!< L23URTUR (Bit 25) */ + #define R_MFWD_FWL23URRR1_L23URTUR_Msk (0x6000000UL) /*!< L23URTUR (Bitfield-Mask: 0x03) */ +/* ====================================================== FWL23URRR2 ======================================================= */ + #define R_MFWD_FWL23URRR2_L23UMDARP1_Pos (0UL) /*!< L23UMDARP1 (Bit 0) */ + #define R_MFWD_FWL23URRR2_L23UMDARP1_Msk (0xffffffffUL) /*!< L23UMDARP1 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWL23URRR3 ======================================================= */ + #define R_MFWD_FWL23URRR3_L23UCVIDR_Pos (0UL) /*!< L23UCVIDR (Bit 0) */ + #define R_MFWD_FWL23URRR3_L23UCVIDR_Msk (0xfffUL) /*!< L23UCVIDR (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URRR3_L23UCPCPR_Pos (12UL) /*!< L23UCPCPR (Bit 12) */ + #define R_MFWD_FWL23URRR3_L23UCPCPR_Msk (0x7000UL) /*!< L23UCPCPR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URRR3_L23UCDEIR_Pos (15UL) /*!< L23UCDEIR (Bit 15) */ + #define R_MFWD_FWL23URRR3_L23UCDEIR_Msk (0x8000UL) /*!< L23UCDEIR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWL23URRR3_L23USVIDR_Pos (16UL) /*!< L23USVIDR (Bit 16) */ + #define R_MFWD_FWL23URRR3_L23USVIDR_Msk (0xfff0000UL) /*!< L23USVIDR (Bitfield-Mask: 0xfff) */ + #define R_MFWD_FWL23URRR3_L23USPCPR_Pos (28UL) /*!< L23USPCPR (Bit 28) */ + #define R_MFWD_FWL23URRR3_L23USPCPR_Msk (0x70000000UL) /*!< L23USPCPR (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URRR3_L23USDEIR_Pos (31UL) /*!< L23USDEIR (Bit 31) */ + #define R_MFWD_FWL23URRR3_L23USDEIR_Msk (0x80000000UL) /*!< L23USDEIR (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC0 ======================================================= */ + #define R_MFWD_FWL23URMC0_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC0_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC0_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC0_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC0_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC0_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC0_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC0_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC1 ======================================================= */ + #define R_MFWD_FWL23URMC1_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC1_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC1_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC1_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC1_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC1_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC1_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC1_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC2 ======================================================= */ + #define R_MFWD_FWL23URMC2_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC2_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC2_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC2_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC2_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC2_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC2_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC2_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC3 ======================================================= */ + #define R_MFWD_FWL23URMC3_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC3_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC3_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC3_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC3_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC3_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC3_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC3_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC4 ======================================================= */ + #define R_MFWD_FWL23URMC4_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC4_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC4_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC4_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC4_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC4_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC4_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC4_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC5 ======================================================= */ + #define R_MFWD_FWL23URMC5_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC5_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC5_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC5_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC5_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC5_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC5_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC5_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC6 ======================================================= */ + #define R_MFWD_FWL23URMC6_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC6_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC6_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC6_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC6_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC6_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC6_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC6_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC7 ======================================================= */ + #define R_MFWD_FWL23URMC7_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC7_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC7_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC7_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC7_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC7_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC7_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC7_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC8 ======================================================= */ + #define R_MFWD_FWL23URMC8_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC8_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC8_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC8_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC8_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC8_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC8_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC8_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC9 ======================================================= */ + #define R_MFWD_FWL23URMC9_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC9_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC9_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC9_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC9_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC9_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC9_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC9_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC10 ====================================================== */ + #define R_MFWD_FWL23URMC10_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC10_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC10_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC10_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC10_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC10_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC10_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC10_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC11 ====================================================== */ + #define R_MFWD_FWL23URMC11_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC11_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC11_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC11_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC11_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC11_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC11_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC11_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC12 ====================================================== */ + #define R_MFWD_FWL23URMC12_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC12_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC12_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC12_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC12_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC12_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC12_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC12_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC13 ====================================================== */ + #define R_MFWD_FWL23URMC13_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC13_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC13_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC13_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC13_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC13_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC13_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC13_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC14 ====================================================== */ + #define R_MFWD_FWL23URMC14_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC14_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC14_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC14_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC14_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC14_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC14_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC14_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC15 ====================================================== */ + #define R_MFWD_FWL23URMC15_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC15_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC15_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC15_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC15_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC15_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC15_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC15_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC16 ====================================================== */ + #define R_MFWD_FWL23URMC16_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC16_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC16_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC16_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC16_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC16_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC16_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC16_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC17 ====================================================== */ + #define R_MFWD_FWL23URMC17_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC17_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC17_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC17_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC17_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC17_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC17_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC17_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC18 ====================================================== */ + #define R_MFWD_FWL23URMC18_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC18_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC18_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC18_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC18_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC18_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC18_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC18_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC19 ====================================================== */ + #define R_MFWD_FWL23URMC19_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC19_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC19_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC19_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC19_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC19_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC19_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC19_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC20 ====================================================== */ + #define R_MFWD_FWL23URMC20_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC20_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC20_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC20_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC20_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC20_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC20_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC20_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC21 ====================================================== */ + #define R_MFWD_FWL23URMC21_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC21_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC21_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC21_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC21_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC21_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC21_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC21_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC22 ====================================================== */ + #define R_MFWD_FWL23URMC22_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC22_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC22_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC22_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC22_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC22_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC22_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC22_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC23 ====================================================== */ + #define R_MFWD_FWL23URMC23_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC23_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC23_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC23_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC23_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC23_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC23_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC23_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC24 ====================================================== */ + #define R_MFWD_FWL23URMC24_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC24_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC24_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC24_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC24_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC24_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC24_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC24_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC25 ====================================================== */ + #define R_MFWD_FWL23URMC25_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC25_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC25_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC25_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC25_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC25_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC25_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC25_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC26 ====================================================== */ + #define R_MFWD_FWL23URMC26_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC26_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC26_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC26_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC26_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC26_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC26_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC26_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC27 ====================================================== */ + #define R_MFWD_FWL23URMC27_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC27_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC27_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC27_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC27_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC27_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC27_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC27_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC28 ====================================================== */ + #define R_MFWD_FWL23URMC28_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC28_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC28_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC28_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC28_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC28_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC28_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC28_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC29 ====================================================== */ + #define R_MFWD_FWL23URMC29_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC29_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC29_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC29_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC29_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC29_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC29_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC29_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC30 ====================================================== */ + #define R_MFWD_FWL23URMC30_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC30_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC30_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC30_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC30_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC30_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC30_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC30_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ====================================================== FWL23URMC31 ====================================================== */ + #define R_MFWD_FWL23URMC31_RMRN_Pos (0UL) /*!< RMRN (Bit 0) */ + #define R_MFWD_FWL23URMC31_RMRN_Msk (0xffUL) /*!< RMRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC31_RMDPN_Pos (12UL) /*!< RMDPN (Bit 12) */ + #define R_MFWD_FWL23URMC31_RMDPN_Msk (0x7000UL) /*!< RMDPN (Bitfield-Mask: 0x07) */ + #define R_MFWD_FWL23URMC31_RMNRN_Pos (16UL) /*!< RMNRN (Bit 16) */ + #define R_MFWD_FWL23URMC31_RMNRN_Msk (0xff0000UL) /*!< RMNRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWL23URMC31_RME_Pos (28UL) /*!< RME (Bit 28) */ + #define R_MFWD_FWL23URMC31_RME_Msk (0x10000000UL) /*!< RME (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC0 ======================================================== */ + #define R_MFWD_FWPMFGC0_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC0_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC0_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC0_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC1 ======================================================== */ + #define R_MFWD_FWPMFGC1_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC1_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC1_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC1_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC2 ======================================================== */ + #define R_MFWD_FWPMFGC2_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC2_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC2_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC2_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC3 ======================================================== */ + #define R_MFWD_FWPMFGC3_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC3_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC3_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC3_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC4 ======================================================== */ + #define R_MFWD_FWPMFGC4_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC4_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC4_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC4_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC5 ======================================================== */ + #define R_MFWD_FWPMFGC5_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC5_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC5_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC5_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC6 ======================================================== */ + #define R_MFWD_FWPMFGC6_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC6_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC6_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC6_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC7 ======================================================== */ + #define R_MFWD_FWPMFGC7_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC7_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC7_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC7_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC8 ======================================================== */ + #define R_MFWD_FWPMFGC8_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC8_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC8_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC8_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC9 ======================================================== */ + #define R_MFWD_FWPMFGC9_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC9_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC9_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC9_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC10 ======================================================= */ + #define R_MFWD_FWPMFGC10_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC10_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC10_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC10_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC11 ======================================================= */ + #define R_MFWD_FWPMFGC11_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC11_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC11_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC11_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC12 ======================================================= */ + #define R_MFWD_FWPMFGC12_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC12_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC12_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC12_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC13 ======================================================= */ + #define R_MFWD_FWPMFGC13_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC13_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC13_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC13_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC14 ======================================================= */ + #define R_MFWD_FWPMFGC14_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC14_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC14_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC14_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMFGC15 ======================================================= */ + #define R_MFWD_FWPMFGC15_MSDUV_Pos (0UL) /*!< MSDUV (Bit 0) */ + #define R_MFWD_FWPMFGC15_MSDUV_Msk (0xffffUL) /*!< MSDUV (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWPMFGC15_MFM_Pos (31UL) /*!< MFM (Bit 31) */ + #define R_MFWD_FWPMFGC15_MFM_Msk (0x80000000UL) /*!< MFM (Bitfield-Mask: 0x01) */ +/* ======================================================= FWPMTRFC0 ======================================================= */ + #define R_MFWD_FWPMTRFC0_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC0_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC0_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC0_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC0_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC0_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC0_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC0_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC1 ======================================================= */ + #define R_MFWD_FWPMTRFC1_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC1_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC1_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC1_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC1_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC1_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC1_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC1_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC2 ======================================================= */ + #define R_MFWD_FWPMTRFC2_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC2_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC2_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC2_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC2_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC2_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC2_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC2_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC3 ======================================================= */ + #define R_MFWD_FWPMTRFC3_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC3_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC3_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC3_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC3_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC3_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC3_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC3_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC4 ======================================================= */ + #define R_MFWD_FWPMTRFC4_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC4_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC4_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC4_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC4_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC4_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC4_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC4_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC5 ======================================================= */ + #define R_MFWD_FWPMTRFC5_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC5_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC5_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC5_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC5_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC5_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC5_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC5_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC6 ======================================================= */ + #define R_MFWD_FWPMTRFC6_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC6_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC6_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC6_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC6_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC6_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC6_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC6_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC7 ======================================================= */ + #define R_MFWD_FWPMTRFC7_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC7_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC7_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC7_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC7_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC7_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC7_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC7_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC8 ======================================================= */ + #define R_MFWD_FWPMTRFC8_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC8_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC8_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC8_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC8_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC8_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC8_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC8_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMTRFC9 ======================================================= */ + #define R_MFWD_FWPMTRFC9_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC9_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC9_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC9_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC9_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC9_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC9_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC9_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC10 ======================================================= */ + #define R_MFWD_FWPMTRFC10_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC10_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC10_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC10_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC10_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC10_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC10_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC10_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC11 ======================================================= */ + #define R_MFWD_FWPMTRFC11_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC11_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC11_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC11_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC11_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC11_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC11_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC11_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC12 ======================================================= */ + #define R_MFWD_FWPMTRFC12_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC12_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC12_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC12_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC12_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC12_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC12_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC12_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC13 ======================================================= */ + #define R_MFWD_FWPMTRFC13_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC13_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC13_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC13_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC13_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC13_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC13_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC13_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC14 ======================================================= */ + #define R_MFWD_FWPMTRFC14_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC14_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC14_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC14_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC14_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC14_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC14_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC14_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC15 ======================================================= */ + #define R_MFWD_FWPMTRFC15_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC15_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC15_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC15_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC15_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC15_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC15_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC15_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC16 ======================================================= */ + #define R_MFWD_FWPMTRFC16_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC16_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC16_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC16_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC16_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC16_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC16_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC16_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC17 ======================================================= */ + #define R_MFWD_FWPMTRFC17_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC17_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC17_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC17_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC17_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC17_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC17_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC17_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC18 ======================================================= */ + #define R_MFWD_FWPMTRFC18_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC18_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC18_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC18_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC18_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC18_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC18_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC18_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC19 ======================================================= */ + #define R_MFWD_FWPMTRFC19_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC19_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC19_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC19_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC19_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC19_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC19_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC19_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC20 ======================================================= */ + #define R_MFWD_FWPMTRFC20_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC20_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC20_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC20_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC20_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC20_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC20_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC20_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC21 ======================================================= */ + #define R_MFWD_FWPMTRFC21_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC21_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC21_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC21_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC21_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC21_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC21_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC21_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC22 ======================================================= */ + #define R_MFWD_FWPMTRFC22_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC22_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC22_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC22_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC22_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC22_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC22_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC22_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC23 ======================================================= */ + #define R_MFWD_FWPMTRFC23_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC23_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC23_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC23_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC23_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC23_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC23_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC23_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC24 ======================================================= */ + #define R_MFWD_FWPMTRFC24_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC24_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC24_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC24_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC24_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC24_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC24_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC24_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC25 ======================================================= */ + #define R_MFWD_FWPMTRFC25_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC25_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC25_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC25_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC25_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC25_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC25_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC25_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC26 ======================================================= */ + #define R_MFWD_FWPMTRFC26_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC26_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC26_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC26_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC26_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC26_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC26_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC26_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC27 ======================================================= */ + #define R_MFWD_FWPMTRFC27_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC27_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC27_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC27_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC27_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC27_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC27_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC27_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC28 ======================================================= */ + #define R_MFWD_FWPMTRFC28_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC28_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC28_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC28_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC28_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC28_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC28_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC28_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC29 ======================================================= */ + #define R_MFWD_FWPMTRFC29_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC29_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC29_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC29_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC29_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC29_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC29_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC29_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC30 ======================================================= */ + #define R_MFWD_FWPMTRFC30_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC30_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC30_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC30_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC30_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC30_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC30_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC30_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRFC31 ======================================================= */ + #define R_MFWD_FWPMTRFC31_MTRFE_Pos (0UL) /*!< MTRFE (Bit 0) */ + #define R_MFWD_FWPMTRFC31_MTRFE_Msk (0x1UL) /*!< MTRFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRFM_Pos (1UL) /*!< MTRFM (Bit 1) */ + #define R_MFWD_FWPMTRFC31_MTRFM_Msk (0x6UL) /*!< MTRFM (Bitfield-Mask: 0x03) */ + #define R_MFWD_FWPMTRFC31_MTRFRFD_Pos (3UL) /*!< MTRFRFD (Bit 3) */ + #define R_MFWD_FWPMTRFC31_MTRFRFD_Msk (0x8UL) /*!< MTRFRFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRCF_Pos (4UL) /*!< MTRCF (Bit 4) */ + #define R_MFWD_FWPMTRFC31_MTRCF_Msk (0x10UL) /*!< MTRCF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWPMTRFC31_MTRCM_Pos (16UL) /*!< MTRCM (Bit 16) */ + #define R_MFWD_FWPMTRFC31_MTRCM_Msk (0xffff0000UL) /*!< MTRCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMTRCBSC0 ====================================================== */ + #define R_MFWD_FWPMTRCBSC0_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC0_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC1 ====================================================== */ + #define R_MFWD_FWPMTRCBSC1_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC1_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC2 ====================================================== */ + #define R_MFWD_FWPMTRCBSC2_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC2_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC3 ====================================================== */ + #define R_MFWD_FWPMTRCBSC3_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC3_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC4 ====================================================== */ + #define R_MFWD_FWPMTRCBSC4_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC4_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC5 ====================================================== */ + #define R_MFWD_FWPMTRCBSC5_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC5_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC6 ====================================================== */ + #define R_MFWD_FWPMTRCBSC6_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC6_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC7 ====================================================== */ + #define R_MFWD_FWPMTRCBSC7_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC7_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC8 ====================================================== */ + #define R_MFWD_FWPMTRCBSC8_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC8_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCBSC9 ====================================================== */ + #define R_MFWD_FWPMTRCBSC9_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC9_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC10 ====================================================== */ + #define R_MFWD_FWPMTRCBSC10_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC10_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC11 ====================================================== */ + #define R_MFWD_FWPMTRCBSC11_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC11_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC12 ====================================================== */ + #define R_MFWD_FWPMTRCBSC12_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC12_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC13 ====================================================== */ + #define R_MFWD_FWPMTRCBSC13_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC13_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC14 ====================================================== */ + #define R_MFWD_FWPMTRCBSC14_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC14_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC15 ====================================================== */ + #define R_MFWD_FWPMTRCBSC15_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC15_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC16 ====================================================== */ + #define R_MFWD_FWPMTRCBSC16_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC16_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC17 ====================================================== */ + #define R_MFWD_FWPMTRCBSC17_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC17_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC18 ====================================================== */ + #define R_MFWD_FWPMTRCBSC18_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC18_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC19 ====================================================== */ + #define R_MFWD_FWPMTRCBSC19_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC19_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC20 ====================================================== */ + #define R_MFWD_FWPMTRCBSC20_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC20_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC21 ====================================================== */ + #define R_MFWD_FWPMTRCBSC21_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC21_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC22 ====================================================== */ + #define R_MFWD_FWPMTRCBSC22_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC22_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC23 ====================================================== */ + #define R_MFWD_FWPMTRCBSC23_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC23_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC24 ====================================================== */ + #define R_MFWD_FWPMTRCBSC24_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC24_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC25 ====================================================== */ + #define R_MFWD_FWPMTRCBSC25_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC25_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC26 ====================================================== */ + #define R_MFWD_FWPMTRCBSC26_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC26_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC27 ====================================================== */ + #define R_MFWD_FWPMTRCBSC27_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC27_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC28 ====================================================== */ + #define R_MFWD_FWPMTRCBSC28_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC28_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC29 ====================================================== */ + #define R_MFWD_FWPMTRCBSC29_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC29_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC30 ====================================================== */ + #define R_MFWD_FWPMTRCBSC30_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC30_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ===================================================== FWPMTRCBSC31 ====================================================== */ + #define R_MFWD_FWPMTRCBSC31_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_MFWD_FWPMTRCBSC31_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTRCIRC0 ====================================================== */ + #define R_MFWD_FWPMTRCIRC0_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC0_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC1 ====================================================== */ + #define R_MFWD_FWPMTRCIRC1_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC1_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC2 ====================================================== */ + #define R_MFWD_FWPMTRCIRC2_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC2_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC3 ====================================================== */ + #define R_MFWD_FWPMTRCIRC3_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC3_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC4 ====================================================== */ + #define R_MFWD_FWPMTRCIRC4_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC4_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC5 ====================================================== */ + #define R_MFWD_FWPMTRCIRC5_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC5_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC6 ====================================================== */ + #define R_MFWD_FWPMTRCIRC6_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC6_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC7 ====================================================== */ + #define R_MFWD_FWPMTRCIRC7_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC7_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC8 ====================================================== */ + #define R_MFWD_FWPMTRCIRC8_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC8_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTRCIRC9 ====================================================== */ + #define R_MFWD_FWPMTRCIRC9_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC9_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC10 ====================================================== */ + #define R_MFWD_FWPMTRCIRC10_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC10_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC11 ====================================================== */ + #define R_MFWD_FWPMTRCIRC11_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC11_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC12 ====================================================== */ + #define R_MFWD_FWPMTRCIRC12_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC12_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC13 ====================================================== */ + #define R_MFWD_FWPMTRCIRC13_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC13_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC14 ====================================================== */ + #define R_MFWD_FWPMTRCIRC14_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC14_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC15 ====================================================== */ + #define R_MFWD_FWPMTRCIRC15_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC15_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC16 ====================================================== */ + #define R_MFWD_FWPMTRCIRC16_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC16_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC17 ====================================================== */ + #define R_MFWD_FWPMTRCIRC17_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC17_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC18 ====================================================== */ + #define R_MFWD_FWPMTRCIRC18_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC18_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC19 ====================================================== */ + #define R_MFWD_FWPMTRCIRC19_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC19_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC20 ====================================================== */ + #define R_MFWD_FWPMTRCIRC20_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC20_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC21 ====================================================== */ + #define R_MFWD_FWPMTRCIRC21_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC21_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC22 ====================================================== */ + #define R_MFWD_FWPMTRCIRC22_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC22_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC23 ====================================================== */ + #define R_MFWD_FWPMTRCIRC23_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC23_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC24 ====================================================== */ + #define R_MFWD_FWPMTRCIRC24_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC24_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC25 ====================================================== */ + #define R_MFWD_FWPMTRCIRC25_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC25_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC26 ====================================================== */ + #define R_MFWD_FWPMTRCIRC26_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC26_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC27 ====================================================== */ + #define R_MFWD_FWPMTRCIRC27_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC27_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC28 ====================================================== */ + #define R_MFWD_FWPMTRCIRC28_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC28_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC29 ====================================================== */ + #define R_MFWD_FWPMTRCIRC29_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC29_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC30 ====================================================== */ + #define R_MFWD_FWPMTRCIRC30_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC30_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ===================================================== FWPMTRCIRC31 ====================================================== */ + #define R_MFWD_FWPMTRCIRC31_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_MFWD_FWPMTRCIRC31_CIR_Msk (0xfffffUL) /*!< CIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREBSC0 ====================================================== */ + #define R_MFWD_FWPMTREBSC0_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC0_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC1 ====================================================== */ + #define R_MFWD_FWPMTREBSC1_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC1_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC2 ====================================================== */ + #define R_MFWD_FWPMTREBSC2_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC2_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC3 ====================================================== */ + #define R_MFWD_FWPMTREBSC3_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC3_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC4 ====================================================== */ + #define R_MFWD_FWPMTREBSC4_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC4_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC5 ====================================================== */ + #define R_MFWD_FWPMTREBSC5_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC5_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC6 ====================================================== */ + #define R_MFWD_FWPMTREBSC6_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC6_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREBSC7 ====================================================== */ + #define R_MFWD_FWPMTREBSC7_EBS_Pos (0UL) /*!< EBS (Bit 0) */ + #define R_MFWD_FWPMTREBSC7_EBS_Msk (0x3ffffUL) /*!< EBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== FWPMTREIRC0 ====================================================== */ + #define R_MFWD_FWPMTREIRC0_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC0_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC1 ====================================================== */ + #define R_MFWD_FWPMTREIRC1_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC1_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC2 ====================================================== */ + #define R_MFWD_FWPMTREIRC2_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC2_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC3 ====================================================== */ + #define R_MFWD_FWPMTREIRC3_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC3_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC4 ====================================================== */ + #define R_MFWD_FWPMTREIRC4_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC4_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC5 ====================================================== */ + #define R_MFWD_FWPMTREIRC5_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC5_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC6 ====================================================== */ + #define R_MFWD_FWPMTREIRC6_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC6_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ====================================================== FWPMTREIRC7 ====================================================== */ + #define R_MFWD_FWPMTREIRC7_EIR_Pos (0UL) /*!< EIR (Bit 0) */ + #define R_MFWD_FWPMTREIRC7_EIR_Msk (0xfffffUL) /*!< EIR (Bitfield-Mask: 0xfffff) */ +/* ======================================================= FWPMTRFM0 ======================================================= */ + #define R_MFWD_FWPMTRFM0_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM0_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM0_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM0_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM1 ======================================================= */ + #define R_MFWD_FWPMTRFM1_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM1_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM1_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM1_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM2 ======================================================= */ + #define R_MFWD_FWPMTRFM2_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM2_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM2_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM2_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM3 ======================================================= */ + #define R_MFWD_FWPMTRFM3_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM3_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM3_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM3_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM4 ======================================================= */ + #define R_MFWD_FWPMTRFM4_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM4_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM4_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM4_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM5 ======================================================= */ + #define R_MFWD_FWPMTRFM5_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM5_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM5_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM5_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM6 ======================================================= */ + #define R_MFWD_FWPMTRFM6_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM6_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM6_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM6_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM7 ======================================================= */ + #define R_MFWD_FWPMTRFM7_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM7_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM7_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM7_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM8 ======================================================= */ + #define R_MFWD_FWPMTRFM8_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM8_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM8_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM8_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================= FWPMTRFM9 ======================================================= */ + #define R_MFWD_FWPMTRFM9_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM9_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM9_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM9_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM10 ======================================================= */ + #define R_MFWD_FWPMTRFM10_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM10_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM10_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM10_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM11 ======================================================= */ + #define R_MFWD_FWPMTRFM11_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM11_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM11_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM11_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM12 ======================================================= */ + #define R_MFWD_FWPMTRFM12_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM12_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM12_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM12_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM13 ======================================================= */ + #define R_MFWD_FWPMTRFM13_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM13_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM13_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM13_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM14 ======================================================= */ + #define R_MFWD_FWPMTRFM14_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM14_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM14_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM14_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM15 ======================================================= */ + #define R_MFWD_FWPMTRFM15_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM15_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM15_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM15_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM16 ======================================================= */ + #define R_MFWD_FWPMTRFM16_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM16_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM16_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM16_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM17 ======================================================= */ + #define R_MFWD_FWPMTRFM17_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM17_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM17_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM17_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM18 ======================================================= */ + #define R_MFWD_FWPMTRFM18_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM18_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM18_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM18_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM19 ======================================================= */ + #define R_MFWD_FWPMTRFM19_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM19_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM19_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM19_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM20 ======================================================= */ + #define R_MFWD_FWPMTRFM20_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM20_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM20_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM20_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM21 ======================================================= */ + #define R_MFWD_FWPMTRFM21_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM21_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM21_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM21_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM22 ======================================================= */ + #define R_MFWD_FWPMTRFM22_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM22_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM22_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM22_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM23 ======================================================= */ + #define R_MFWD_FWPMTRFM23_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM23_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM23_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM23_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM24 ======================================================= */ + #define R_MFWD_FWPMTRFM24_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM24_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM24_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM24_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM25 ======================================================= */ + #define R_MFWD_FWPMTRFM25_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM25_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM25_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM25_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM26 ======================================================= */ + #define R_MFWD_FWPMTRFM26_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM26_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM26_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM26_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM27 ======================================================= */ + #define R_MFWD_FWPMTRFM27_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM27_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM27_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM27_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM28 ======================================================= */ + #define R_MFWD_FWPMTRFM28_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM28_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM28_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM28_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM29 ======================================================= */ + #define R_MFWD_FWPMTRFM29_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM29_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM29_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM29_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM30 ======================================================= */ + #define R_MFWD_FWPMTRFM30_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM30_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM30_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM30_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ====================================================== FWPMTRFM31 ======================================================= */ + #define R_MFWD_FWPMTRFM31_MTRARDN_Pos (0UL) /*!< MTRARDN (Bit 0) */ + #define R_MFWD_FWPMTRFM31_MTRARDN_Msk (0x1fUL) /*!< MTRARDN (Bitfield-Mask: 0x1f) */ + #define R_MFWD_FWPMTRFM31_MTRARDNMN_Pos (16UL) /*!< MTRARDNMN (Bit 16) */ + #define R_MFWD_FWPMTRFM31_MTRARDNMN_Msk (0x1f0000UL) /*!< MTRARDNMN (Bitfield-Mask: 0x1f) */ +/* ======================================================== FWFTL0 ========================================================= */ + #define R_MFWD_FWFTL0_FEAL_Pos (0UL) /*!< FEAL (Bit 0) */ + #define R_MFWD_FWFTL0_FEAL_Msk (0x7fUL) /*!< FEAL (Bitfield-Mask: 0x7f) */ + #define R_MFWD_FWFTL0_FSRPL_Pos (16UL) /*!< FSRPL (Bit 16) */ + #define R_MFWD_FWFTL0_FSRPL_Msk (0x7f0000UL) /*!< FSRPL (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTL1 ========================================================= */ + #define R_MFWD_FWFTL1_FSHLL_Pos (0UL) /*!< FSHLL (Bit 0) */ + #define R_MFWD_FWFTL1_FSHLL_Msk (0xfUL) /*!< FSHLL (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWFTL1_FTNSL_Pos (8UL) /*!< FTNSL (Bit 8) */ + #define R_MFWD_FWFTL1_FTNSL_Msk (0x100UL) /*!< FTNSL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTL1_FSRPVL_Pos (9UL) /*!< FSRPVL (Bit 9) */ + #define R_MFWD_FWFTL1_FSRPVL_Msk (0x200UL) /*!< FSRPVL (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTL1_FSRRTL_Pos (16UL) /*!< FSRRTL (Bit 16) */ + #define R_MFWD_FWFTL1_FSRRTL_Msk (0x3ff0000UL) /*!< FSRRTL (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FWFTLR ========================================================= */ + #define R_MFWD_FWFTLR_FLF_Pos (0UL) /*!< FLF (Bit 0) */ + #define R_MFWD_FWFTLR_FLF_Msk (0x1UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTLR_FTL_Pos (31UL) /*!< FTL (Bit 31) */ + #define R_MFWD_FWFTLR_FTL_Msk (0x80000000UL) /*!< FTL (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTOC ========================================================= */ + #define R_MFWD_FWFTOC_TOT_Pos (0UL) /*!< TOT (Bit 0) */ + #define R_MFWD_FWFTOC_TOT_Msk (0xffffUL) /*!< TOT (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWFTOC_TOCE_Pos (16UL) /*!< TOCE (Bit 16) */ + #define R_MFWD_FWFTOC_TOCE_Msk (0x10000UL) /*!< TOCE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTOC_TOOG_Pos (17UL) /*!< TOOG (Bit 17) */ + #define R_MFWD_FWFTOC_TOOG_Msk (0x20000UL) /*!< TOOG (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTOPC ======================================================== */ + #define R_MFWD_FWFTOPC_USP_Pos (0UL) /*!< USP (Bit 0) */ + #define R_MFWD_FWFTOPC_USP_Msk (0x3ffUL) /*!< USP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FWFTIM ========================================================= */ + #define R_MFWD_FWFTIM_FTIOG_Pos (0UL) /*!< FTIOG (Bit 0) */ + #define R_MFWD_FWFTIM_FTIOG_Msk (0x1UL) /*!< FTIOG (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTIM_FTR_Pos (1UL) /*!< FTR (Bit 1) */ + #define R_MFWD_FWFTIM_FTR_Msk (0x2UL) /*!< FTR (Bitfield-Mask: 0x01) */ +/* ========================================================= FWFTR ========================================================= */ + #define R_MFWD_FWFTR_FEAR_Pos (0UL) /*!< FEAR (Bit 0) */ + #define R_MFWD_FWFTR_FEAR_Msk (0x7fUL) /*!< FEAR (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTRR0 ======================================================== */ + #define R_MFWD_FWFTRR0_FSHLR_Pos (0UL) /*!< FSHLR (Bit 0) */ + #define R_MFWD_FWFTRR0_FSHLR_Msk (0xfUL) /*!< FSHLR (Bitfield-Mask: 0x0f) */ + #define R_MFWD_FWFTRR0_FTNSR_Pos (8UL) /*!< FTNSR (Bit 8) */ + #define R_MFWD_FWFTRR0_FTNSR_Msk (0x100UL) /*!< FTNSR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FSRPVR_Pos (9UL) /*!< FSRPVR (Bit 9) */ + #define R_MFWD_FWFTRR0_FSRPVR_Msk (0x200UL) /*!< FSRPVR (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FSRRTR_Pos (16UL) /*!< FSRRTR (Bit 16) */ + #define R_MFWD_FWFTRR0_FSRRTR_Msk (0x3ff0000UL) /*!< FSRRTR (Bitfield-Mask: 0x3ff) */ + #define R_MFWD_FWFTRR0_FTREF_Pos (30UL) /*!< FTREF (Bit 30) */ + #define R_MFWD_FWFTRR0_FTREF_Msk (0x40000000UL) /*!< FTREF (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWFTRR0_FTR_Pos (31UL) /*!< FTR (Bit 31) */ + #define R_MFWD_FWFTRR0_FTR_Msk (0x80000000UL) /*!< FTR (Bitfield-Mask: 0x01) */ +/* ======================================================== FWFTRR1 ======================================================== */ + #define R_MFWD_FWFTRR1_FSHR_Pos (0UL) /*!< FSHR (Bit 0) */ + #define R_MFWD_FWFTRR1_FSHR_Msk (0x7fffUL) /*!< FSHR (Bitfield-Mask: 0x7fff) */ + #define R_MFWD_FWFTRR1_FSRPR_Pos (16UL) /*!< FSRPR (Bit 16) */ + #define R_MFWD_FWFTRR1_FSRPR_Msk (0x7f0000UL) /*!< FSRPR (Bitfield-Mask: 0x7f) */ +/* ======================================================== FWFTRR2 ======================================================== */ + #define R_MFWD_FWFTRR2_FRSNR_Pos (0UL) /*!< FRSNR (Bit 0) */ + #define R_MFWD_FWFTRR2_FRSNR_Msk (0xffffUL) /*!< FRSNR (Bitfield-Mask: 0xffff) */ + #define R_MFWD_FWFTRR2_FRRTR_Pos (16UL) /*!< FRRTR (Bit 16) */ + #define R_MFWD_FWFTRR2_FRRTR_Msk (0x3ff0000UL) /*!< FRRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= FWSEQNGC0 ======================================================= */ + #define R_MFWD_FWSEQNGC0_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC0_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC0_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC0_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC1 ======================================================= */ + #define R_MFWD_FWSEQNGC1_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC1_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC1_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC1_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC2 ======================================================= */ + #define R_MFWD_FWSEQNGC2_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC2_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC2_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC2_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC3 ======================================================= */ + #define R_MFWD_FWSEQNGC3_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC3_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC3_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC3_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC4 ======================================================= */ + #define R_MFWD_FWSEQNGC4_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC4_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC4_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC4_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC5 ======================================================= */ + #define R_MFWD_FWSEQNGC5_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC5_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC5_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC5_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC6 ======================================================= */ + #define R_MFWD_FWSEQNGC6_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC6_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC6_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC6_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC7 ======================================================= */ + #define R_MFWD_FWSEQNGC7_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC7_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC7_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC7_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC8 ======================================================= */ + #define R_MFWD_FWSEQNGC8_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC8_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC8_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC8_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGC9 ======================================================= */ + #define R_MFWD_FWSEQNGC9_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC9_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC9_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC9_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC10 ======================================================= */ + #define R_MFWD_FWSEQNGC10_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC10_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC10_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC10_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC11 ======================================================= */ + #define R_MFWD_FWSEQNGC11_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC11_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC11_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC11_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC12 ======================================================= */ + #define R_MFWD_FWSEQNGC12_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC12_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC12_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC12_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC13 ======================================================= */ + #define R_MFWD_FWSEQNGC13_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC13_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC13_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC13_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC14 ======================================================= */ + #define R_MFWD_FWSEQNGC14_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC14_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC14_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC14_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC15 ======================================================= */ + #define R_MFWD_FWSEQNGC15_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC15_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC15_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC15_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC16 ======================================================= */ + #define R_MFWD_FWSEQNGC16_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC16_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC16_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC16_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC17 ======================================================= */ + #define R_MFWD_FWSEQNGC17_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC17_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC17_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC17_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC18 ======================================================= */ + #define R_MFWD_FWSEQNGC18_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC18_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC18_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC18_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC19 ======================================================= */ + #define R_MFWD_FWSEQNGC19_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC19_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC19_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC19_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC20 ======================================================= */ + #define R_MFWD_FWSEQNGC20_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC20_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC20_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC20_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC21 ======================================================= */ + #define R_MFWD_FWSEQNGC21_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC21_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC21_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC21_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC22 ======================================================= */ + #define R_MFWD_FWSEQNGC22_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC22_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC22_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC22_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC23 ======================================================= */ + #define R_MFWD_FWSEQNGC23_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC23_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC23_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC23_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC24 ======================================================= */ + #define R_MFWD_FWSEQNGC24_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC24_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC24_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC24_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC25 ======================================================= */ + #define R_MFWD_FWSEQNGC25_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC25_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC25_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC25_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC26 ======================================================= */ + #define R_MFWD_FWSEQNGC26_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC26_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC26_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC26_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC27 ======================================================= */ + #define R_MFWD_FWSEQNGC27_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC27_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC27_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC27_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC28 ======================================================= */ + #define R_MFWD_FWSEQNGC28_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC28_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC28_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC28_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC29 ======================================================= */ + #define R_MFWD_FWSEQNGC29_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC29_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC29_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC29_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC30 ======================================================= */ + #define R_MFWD_FWSEQNGC30_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC30_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC30_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC30_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ====================================================== FWSEQNGC31 ======================================================= */ + #define R_MFWD_FWSEQNGC31_SEQNGRN_Pos (0UL) /*!< SEQNGRN (Bit 0) */ + #define R_MFWD_FWSEQNGC31_SEQNGRN_Msk (0xffUL) /*!< SEQNGRN (Bitfield-Mask: 0xff) */ + #define R_MFWD_FWSEQNGC31_SEQNGE_Pos (16UL) /*!< SEQNGE (Bit 16) */ + #define R_MFWD_FWSEQNGC31_SEQNGE_Msk (0x10000UL) /*!< SEQNGE (Bitfield-Mask: 0x01) */ +/* ======================================================= FWSEQNGM0 ======================================================= */ + #define R_MFWD_FWSEQNGM0_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM0_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM1 ======================================================= */ + #define R_MFWD_FWSEQNGM1_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM1_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM2 ======================================================= */ + #define R_MFWD_FWSEQNGM2_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM2_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM3 ======================================================= */ + #define R_MFWD_FWSEQNGM3_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM3_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM4 ======================================================= */ + #define R_MFWD_FWSEQNGM4_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM4_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM5 ======================================================= */ + #define R_MFWD_FWSEQNGM5_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM5_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM6 ======================================================= */ + #define R_MFWD_FWSEQNGM6_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM6_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM7 ======================================================= */ + #define R_MFWD_FWSEQNGM7_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM7_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM8 ======================================================= */ + #define R_MFWD_FWSEQNGM8_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM8_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNGM9 ======================================================= */ + #define R_MFWD_FWSEQNGM9_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM9_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM10 ======================================================= */ + #define R_MFWD_FWSEQNGM10_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM10_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM11 ======================================================= */ + #define R_MFWD_FWSEQNGM11_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM11_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM12 ======================================================= */ + #define R_MFWD_FWSEQNGM12_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM12_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM13 ======================================================= */ + #define R_MFWD_FWSEQNGM13_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM13_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM14 ======================================================= */ + #define R_MFWD_FWSEQNGM14_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM14_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM15 ======================================================= */ + #define R_MFWD_FWSEQNGM15_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM15_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM16 ======================================================= */ + #define R_MFWD_FWSEQNGM16_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM16_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM17 ======================================================= */ + #define R_MFWD_FWSEQNGM17_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM17_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM18 ======================================================= */ + #define R_MFWD_FWSEQNGM18_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM18_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM19 ======================================================= */ + #define R_MFWD_FWSEQNGM19_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM19_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM20 ======================================================= */ + #define R_MFWD_FWSEQNGM20_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM20_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM21 ======================================================= */ + #define R_MFWD_FWSEQNGM21_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM21_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM22 ======================================================= */ + #define R_MFWD_FWSEQNGM22_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM22_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM23 ======================================================= */ + #define R_MFWD_FWSEQNGM23_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM23_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM24 ======================================================= */ + #define R_MFWD_FWSEQNGM24_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM24_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM25 ======================================================= */ + #define R_MFWD_FWSEQNGM25_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM25_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM26 ======================================================= */ + #define R_MFWD_FWSEQNGM26_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM26_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM27 ======================================================= */ + #define R_MFWD_FWSEQNGM27_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM27_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM28 ======================================================= */ + #define R_MFWD_FWSEQNGM28_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM28_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM29 ======================================================= */ + #define R_MFWD_FWSEQNGM29_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM29_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM30 ======================================================= */ + #define R_MFWD_FWSEQNGM30_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM30_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWSEQNGM31 ======================================================= */ + #define R_MFWD_FWSEQNGM31_SEQN_Pos (0UL) /*!< SEQN (Bit 0) */ + #define R_MFWD_FWSEQNGM31_SEQN_Msk (0xffffUL) /*!< SEQN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWSEQNRC ======================================================== */ + #define R_MFWD_FWSEQNRC_SEQNR_Pos (0UL) /*!< SEQNR (Bit 0) */ + #define R_MFWD_FWSEQNRC_SEQNR_Msk (0xffffffffUL) /*!< SEQNR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTFDCN0 ======================================================= */ + #define R_MFWD_FWCTFDCN0_CTFDN_Pos (0UL) /*!< CTFDN (Bit 0) */ + #define R_MFWD_FWCTFDCN0_CTFDN_Msk (0xffffffffUL) /*!< CTFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWCTFDCN1 ======================================================= */ + #define R_MFWD_FWCTFDCN1_CTFDN_Pos (0UL) /*!< CTFDN (Bit 0) */ + #define R_MFWD_FWCTFDCN1_CTFDN_Msk (0xffffffffUL) /*!< CTFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN0 ======================================================= */ + #define R_MFWD_FWLTHFDCN0_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN0_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN1 ======================================================= */ + #define R_MFWD_FWLTHFDCN1_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN1_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTHFDCN2 ======================================================= */ + #define R_MFWD_FWLTHFDCN2_LTHFDN_Pos (0UL) /*!< LTHFDN (Bit 0) */ + #define R_MFWD_FWLTHFDCN2_LTHFDN_Msk (0xffffffffUL) /*!< LTHFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN0 ======================================================= */ + #define R_MFWD_FWLTWFDCN0_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN0_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN1 ======================================================= */ + #define R_MFWD_FWLTWFDCN1_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN1_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== FWLTWFDCN2 ======================================================= */ + #define R_MFWD_FWLTWFDCN2_LTWFDN_Pos (0UL) /*!< LTWFDN (Bit 0) */ + #define R_MFWD_FWLTWFDCN2_LTWFDN_Msk (0xffffffffUL) /*!< LTWFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN0 ======================================================= */ + #define R_MFWD_FWPBFDCN0_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN0_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN1 ======================================================= */ + #define R_MFWD_FWPBFDCN1_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN1_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWPBFDCN2 ======================================================= */ + #define R_MFWD_FWPBFDCN2_PBFDN_Pos (0UL) /*!< PBFDN (Bit 0) */ + #define R_MFWD_FWPBFDCN2_PBFDN_Msk (0xffffffffUL) /*!< PBFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN0 ======================================================== */ + #define R_MFWD_FWMHLCN0_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN0_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN1 ======================================================== */ + #define R_MFWD_FWMHLCN1_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN1_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWMHLCN2 ======================================================== */ + #define R_MFWD_FWMHLCN2_MHLN_Pos (0UL) /*!< MHLN (Bit 0) */ + #define R_MFWD_FWMHLCN2_MHLN_Msk (0xffffffffUL) /*!< MHLN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWDDFDCN0 ======================================================= */ + #define R_MFWD_FWDDFDCN0_DDFDN_Pos (0UL) /*!< DDFDN (Bit 0) */ + #define R_MFWD_FWDDFDCN0_DDFDN_Msk (0xffffffffUL) /*!< DDFDN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= FWWMRDCN0 ======================================================= */ + #define R_MFWD_FWWMRDCN0_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN0_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWWMRDCN1 ======================================================= */ + #define R_MFWD_FWWMRDCN1_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN1_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWWMRDCN2 ======================================================= */ + #define R_MFWD_FWWMRDCN2_WMRDN_Pos (0UL) /*!< WMRDN (Bit 0) */ + #define R_MFWD_FWWMRDCN2_WMRDN_Msk (0xffffUL) /*!< WMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTRDCN0 ======================================================= */ + #define R_MFWD_FWCTRDCN0_CTRDN_Pos (0UL) /*!< CTRDN (Bit 0) */ + #define R_MFWD_FWCTRDCN0_CTRDN_Msk (0xffffUL) /*!< CTRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWCTRDCN1 ======================================================= */ + #define R_MFWD_FWCTRDCN1_CTRDN_Pos (0UL) /*!< CTRDN (Bit 0) */ + #define R_MFWD_FWCTRDCN1_CTRDN_Msk (0xffffUL) /*!< CTRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN0 ======================================================= */ + #define R_MFWD_FWLTHRDCN0_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN0_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN1 ======================================================= */ + #define R_MFWD_FWLTHRDCN1_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN1_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTHRDCN2 ======================================================= */ + #define R_MFWD_FWLTHRDCN2_LTHRDN_Pos (0UL) /*!< LTHRDN (Bit 0) */ + #define R_MFWD_FWLTHRDCN2_LTHRDN_Msk (0xffffUL) /*!< LTHRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN0 ======================================================= */ + #define R_MFWD_FWLTWRDCN0_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN0_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN1 ======================================================= */ + #define R_MFWD_FWLTWRDCN1_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN1_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWLTWRDCN2 ======================================================= */ + #define R_MFWD_FWLTWRDCN2_LTWRDN_Pos (0UL) /*!< LTWRDN (Bit 0) */ + #define R_MFWD_FWLTWRDCN2_LTWRDN_Msk (0xffffUL) /*!< LTWRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN0 ======================================================= */ + #define R_MFWD_FWPBRDCN0_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN0_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN1 ======================================================= */ + #define R_MFWD_FWPBRDCN1_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN1_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPBRDCN2 ======================================================= */ + #define R_MFWD_FWPBRDCN2_PBRDN_Pos (0UL) /*!< PBRDN (Bit 0) */ + #define R_MFWD_FWPBRDCN2_PBRDN_Msk (0xffffUL) /*!< PBRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWDDRDCN0 ======================================================= */ + #define R_MFWD_FWDDRDCN0_DDRDN_Pos (0UL) /*!< DDRDN (Bit 0) */ + #define R_MFWD_FWDDRDCN0_DDRDN_Msk (0xffffUL) /*!< DDRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN0 ======================================================= */ + #define R_MFWD_FWPMFDCN0_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN0_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN1 ======================================================= */ + #define R_MFWD_FWPMFDCN1_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN1_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN2 ======================================================= */ + #define R_MFWD_FWPMFDCN2_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN2_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN3 ======================================================= */ + #define R_MFWD_FWPMFDCN3_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN3_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN4 ======================================================= */ + #define R_MFWD_FWPMFDCN4_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN4_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN5 ======================================================= */ + #define R_MFWD_FWPMFDCN5_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN5_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN6 ======================================================= */ + #define R_MFWD_FWPMFDCN6_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN6_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN7 ======================================================= */ + #define R_MFWD_FWPMFDCN7_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN7_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN8 ======================================================= */ + #define R_MFWD_FWPMFDCN8_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN8_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMFDCN9 ======================================================= */ + #define R_MFWD_FWPMFDCN9_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN9_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN10 ======================================================= */ + #define R_MFWD_FWPMFDCN10_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN10_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN11 ======================================================= */ + #define R_MFWD_FWPMFDCN11_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN11_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN12 ======================================================= */ + #define R_MFWD_FWPMFDCN12_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN12_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN13 ======================================================= */ + #define R_MFWD_FWPMFDCN13_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN13_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN14 ======================================================= */ + #define R_MFWD_FWPMFDCN14_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN14_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMFDCN15 ======================================================= */ + #define R_MFWD_FWPMFDCN15_PMFDN_Pos (0UL) /*!< PMFDN (Bit 0) */ + #define R_MFWD_FWPMFDCN15_PMFDN_Msk (0xffffUL) /*!< PMFDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN0 ======================================================= */ + #define R_MFWD_FWPMGDCN0_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN0_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN1 ======================================================= */ + #define R_MFWD_FWPMGDCN1_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN1_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN2 ======================================================= */ + #define R_MFWD_FWPMGDCN2_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN2_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN3 ======================================================= */ + #define R_MFWD_FWPMGDCN3_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN3_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN4 ======================================================= */ + #define R_MFWD_FWPMGDCN4_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN4_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN5 ======================================================= */ + #define R_MFWD_FWPMGDCN5_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN5_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN6 ======================================================= */ + #define R_MFWD_FWPMGDCN6_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN6_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN7 ======================================================= */ + #define R_MFWD_FWPMGDCN7_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN7_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN8 ======================================================= */ + #define R_MFWD_FWPMGDCN8_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN8_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMGDCN9 ======================================================= */ + #define R_MFWD_FWPMGDCN9_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN9_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN10 ======================================================= */ + #define R_MFWD_FWPMGDCN10_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN10_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN11 ======================================================= */ + #define R_MFWD_FWPMGDCN11_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN11_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN12 ======================================================= */ + #define R_MFWD_FWPMGDCN12_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN12_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN13 ======================================================= */ + #define R_MFWD_FWPMGDCN13_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN13_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN14 ======================================================= */ + #define R_MFWD_FWPMGDCN14_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN14_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN15 ======================================================= */ + #define R_MFWD_FWPMGDCN15_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN15_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN16 ======================================================= */ + #define R_MFWD_FWPMGDCN16_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN16_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN17 ======================================================= */ + #define R_MFWD_FWPMGDCN17_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN17_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN18 ======================================================= */ + #define R_MFWD_FWPMGDCN18_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN18_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN19 ======================================================= */ + #define R_MFWD_FWPMGDCN19_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN19_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN20 ======================================================= */ + #define R_MFWD_FWPMGDCN20_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN20_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN21 ======================================================= */ + #define R_MFWD_FWPMGDCN21_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN21_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN22 ======================================================= */ + #define R_MFWD_FWPMGDCN22_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN22_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN23 ======================================================= */ + #define R_MFWD_FWPMGDCN23_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN23_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN24 ======================================================= */ + #define R_MFWD_FWPMGDCN24_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN24_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN25 ======================================================= */ + #define R_MFWD_FWPMGDCN25_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN25_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN26 ======================================================= */ + #define R_MFWD_FWPMGDCN26_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN26_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN27 ======================================================= */ + #define R_MFWD_FWPMGDCN27_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN27_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN28 ======================================================= */ + #define R_MFWD_FWPMGDCN28_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN28_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN29 ======================================================= */ + #define R_MFWD_FWPMGDCN29_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN29_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN30 ======================================================= */ + #define R_MFWD_FWPMGDCN30_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN30_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMGDCN31 ======================================================= */ + #define R_MFWD_FWPMGDCN31_PMGDN_Pos (0UL) /*!< PMGDN (Bit 0) */ + #define R_MFWD_FWPMGDCN31_PMGDN_Msk (0xffffUL) /*!< PMGDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN0 ======================================================= */ + #define R_MFWD_FWPMYDCN0_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN0_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN1 ======================================================= */ + #define R_MFWD_FWPMYDCN1_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN1_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN2 ======================================================= */ + #define R_MFWD_FWPMYDCN2_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN2_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN3 ======================================================= */ + #define R_MFWD_FWPMYDCN3_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN3_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN4 ======================================================= */ + #define R_MFWD_FWPMYDCN4_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN4_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN5 ======================================================= */ + #define R_MFWD_FWPMYDCN5_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN5_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN6 ======================================================= */ + #define R_MFWD_FWPMYDCN6_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN6_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMYDCN7 ======================================================= */ + #define R_MFWD_FWPMYDCN7_PMYDN_Pos (0UL) /*!< PMYDN (Bit 0) */ + #define R_MFWD_FWPMYDCN7_PMYDN_Msk (0xffffUL) /*!< PMYDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN0 ======================================================= */ + #define R_MFWD_FWPMRDCN0_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN0_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN1 ======================================================= */ + #define R_MFWD_FWPMRDCN1_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN1_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN2 ======================================================= */ + #define R_MFWD_FWPMRDCN2_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN2_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN3 ======================================================= */ + #define R_MFWD_FWPMRDCN3_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN3_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN4 ======================================================= */ + #define R_MFWD_FWPMRDCN4_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN4_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN5 ======================================================= */ + #define R_MFWD_FWPMRDCN5_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN5_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN6 ======================================================= */ + #define R_MFWD_FWPMRDCN6_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN6_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN7 ======================================================= */ + #define R_MFWD_FWPMRDCN7_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN7_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN8 ======================================================= */ + #define R_MFWD_FWPMRDCN8_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN8_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWPMRDCN9 ======================================================= */ + #define R_MFWD_FWPMRDCN9_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN9_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN10 ======================================================= */ + #define R_MFWD_FWPMRDCN10_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN10_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN11 ======================================================= */ + #define R_MFWD_FWPMRDCN11_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN11_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN12 ======================================================= */ + #define R_MFWD_FWPMRDCN12_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN12_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN13 ======================================================= */ + #define R_MFWD_FWPMRDCN13_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN13_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN14 ======================================================= */ + #define R_MFWD_FWPMRDCN14_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN14_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN15 ======================================================= */ + #define R_MFWD_FWPMRDCN15_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN15_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN16 ======================================================= */ + #define R_MFWD_FWPMRDCN16_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN16_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN17 ======================================================= */ + #define R_MFWD_FWPMRDCN17_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN17_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN18 ======================================================= */ + #define R_MFWD_FWPMRDCN18_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN18_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN19 ======================================================= */ + #define R_MFWD_FWPMRDCN19_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN19_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN20 ======================================================= */ + #define R_MFWD_FWPMRDCN20_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN20_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN21 ======================================================= */ + #define R_MFWD_FWPMRDCN21_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN21_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN22 ======================================================= */ + #define R_MFWD_FWPMRDCN22_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN22_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN23 ======================================================= */ + #define R_MFWD_FWPMRDCN23_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN23_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN24 ======================================================= */ + #define R_MFWD_FWPMRDCN24_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN24_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN25 ======================================================= */ + #define R_MFWD_FWPMRDCN25_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN25_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN26 ======================================================= */ + #define R_MFWD_FWPMRDCN26_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN26_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN27 ======================================================= */ + #define R_MFWD_FWPMRDCN27_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN27_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN28 ======================================================= */ + #define R_MFWD_FWPMRDCN28_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN28_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN29 ======================================================= */ + #define R_MFWD_FWPMRDCN29_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN29_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN30 ======================================================= */ + #define R_MFWD_FWPMRDCN30_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN30_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWPMRDCN31 ======================================================= */ + #define R_MFWD_FWPMRDCN31_PMRDN_Pos (0UL) /*!< PMRDN (Bit 0) */ + #define R_MFWD_FWPMRDCN31_PMRDN_Msk (0xffffUL) /*!< PMRDN (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN0 ======================================================= */ + #define R_MFWD_FWFRPPCN0_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN0_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN1 ======================================================= */ + #define R_MFWD_FWFRPPCN1_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN1_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN2 ======================================================= */ + #define R_MFWD_FWFRPPCN2_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN2_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN3 ======================================================= */ + #define R_MFWD_FWFRPPCN3_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN3_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN4 ======================================================= */ + #define R_MFWD_FWFRPPCN4_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN4_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN5 ======================================================= */ + #define R_MFWD_FWFRPPCN5_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN5_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN6 ======================================================= */ + #define R_MFWD_FWFRPPCN6_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN6_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN7 ======================================================= */ + #define R_MFWD_FWFRPPCN7_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN7_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN8 ======================================================= */ + #define R_MFWD_FWFRPPCN8_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN8_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRPPCN9 ======================================================= */ + #define R_MFWD_FWFRPPCN9_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN9_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN10 ======================================================= */ + #define R_MFWD_FWFRPPCN10_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN10_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN11 ======================================================= */ + #define R_MFWD_FWFRPPCN11_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN11_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN12 ======================================================= */ + #define R_MFWD_FWFRPPCN12_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN12_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN13 ======================================================= */ + #define R_MFWD_FWFRPPCN13_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN13_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN14 ======================================================= */ + #define R_MFWD_FWFRPPCN14_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN14_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN15 ======================================================= */ + #define R_MFWD_FWFRPPCN15_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN15_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN16 ======================================================= */ + #define R_MFWD_FWFRPPCN16_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN16_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN17 ======================================================= */ + #define R_MFWD_FWFRPPCN17_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN17_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN18 ======================================================= */ + #define R_MFWD_FWFRPPCN18_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN18_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN19 ======================================================= */ + #define R_MFWD_FWFRPPCN19_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN19_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN20 ======================================================= */ + #define R_MFWD_FWFRPPCN20_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN20_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN21 ======================================================= */ + #define R_MFWD_FWFRPPCN21_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN21_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN22 ======================================================= */ + #define R_MFWD_FWFRPPCN22_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN22_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN23 ======================================================= */ + #define R_MFWD_FWFRPPCN23_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN23_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN24 ======================================================= */ + #define R_MFWD_FWFRPPCN24_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN24_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN25 ======================================================= */ + #define R_MFWD_FWFRPPCN25_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN25_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN26 ======================================================= */ + #define R_MFWD_FWFRPPCN26_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN26_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN27 ======================================================= */ + #define R_MFWD_FWFRPPCN27_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN27_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN28 ======================================================= */ + #define R_MFWD_FWFRPPCN28_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN28_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN29 ======================================================= */ + #define R_MFWD_FWFRPPCN29_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN29_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN30 ======================================================= */ + #define R_MFWD_FWFRPPCN30_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN30_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN31 ======================================================= */ + #define R_MFWD_FWFRPPCN31_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN31_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN32 ======================================================= */ + #define R_MFWD_FWFRPPCN32_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN32_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN33 ======================================================= */ + #define R_MFWD_FWFRPPCN33_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN33_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN34 ======================================================= */ + #define R_MFWD_FWFRPPCN34_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN34_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN35 ======================================================= */ + #define R_MFWD_FWFRPPCN35_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN35_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN36 ======================================================= */ + #define R_MFWD_FWFRPPCN36_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN36_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN37 ======================================================= */ + #define R_MFWD_FWFRPPCN37_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN37_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN38 ======================================================= */ + #define R_MFWD_FWFRPPCN38_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN38_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN39 ======================================================= */ + #define R_MFWD_FWFRPPCN39_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN39_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN40 ======================================================= */ + #define R_MFWD_FWFRPPCN40_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN40_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN41 ======================================================= */ + #define R_MFWD_FWFRPPCN41_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN41_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN42 ======================================================= */ + #define R_MFWD_FWFRPPCN42_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN42_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN43 ======================================================= */ + #define R_MFWD_FWFRPPCN43_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN43_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN44 ======================================================= */ + #define R_MFWD_FWFRPPCN44_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN44_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN45 ======================================================= */ + #define R_MFWD_FWFRPPCN45_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN45_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN46 ======================================================= */ + #define R_MFWD_FWFRPPCN46_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN46_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN47 ======================================================= */ + #define R_MFWD_FWFRPPCN47_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN47_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN48 ======================================================= */ + #define R_MFWD_FWFRPPCN48_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN48_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN49 ======================================================= */ + #define R_MFWD_FWFRPPCN49_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN49_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN50 ======================================================= */ + #define R_MFWD_FWFRPPCN50_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN50_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN51 ======================================================= */ + #define R_MFWD_FWFRPPCN51_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN51_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN52 ======================================================= */ + #define R_MFWD_FWFRPPCN52_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN52_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN53 ======================================================= */ + #define R_MFWD_FWFRPPCN53_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN53_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN54 ======================================================= */ + #define R_MFWD_FWFRPPCN54_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN54_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN55 ======================================================= */ + #define R_MFWD_FWFRPPCN55_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN55_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN56 ======================================================= */ + #define R_MFWD_FWFRPPCN56_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN56_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN57 ======================================================= */ + #define R_MFWD_FWFRPPCN57_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN57_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN58 ======================================================= */ + #define R_MFWD_FWFRPPCN58_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN58_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN59 ======================================================= */ + #define R_MFWD_FWFRPPCN59_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN59_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN60 ======================================================= */ + #define R_MFWD_FWFRPPCN60_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN60_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN61 ======================================================= */ + #define R_MFWD_FWFRPPCN61_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN61_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN62 ======================================================= */ + #define R_MFWD_FWFRPPCN62_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN62_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN63 ======================================================= */ + #define R_MFWD_FWFRPPCN63_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN63_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN64 ======================================================= */ + #define R_MFWD_FWFRPPCN64_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN64_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN65 ======================================================= */ + #define R_MFWD_FWFRPPCN65_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN65_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN66 ======================================================= */ + #define R_MFWD_FWFRPPCN66_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN66_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN67 ======================================================= */ + #define R_MFWD_FWFRPPCN67_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN67_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN68 ======================================================= */ + #define R_MFWD_FWFRPPCN68_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN68_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN69 ======================================================= */ + #define R_MFWD_FWFRPPCN69_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN69_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN70 ======================================================= */ + #define R_MFWD_FWFRPPCN70_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN70_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN71 ======================================================= */ + #define R_MFWD_FWFRPPCN71_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN71_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN72 ======================================================= */ + #define R_MFWD_FWFRPPCN72_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN72_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN73 ======================================================= */ + #define R_MFWD_FWFRPPCN73_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN73_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN74 ======================================================= */ + #define R_MFWD_FWFRPPCN74_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN74_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN75 ======================================================= */ + #define R_MFWD_FWFRPPCN75_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN75_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN76 ======================================================= */ + #define R_MFWD_FWFRPPCN76_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN76_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN77 ======================================================= */ + #define R_MFWD_FWFRPPCN77_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN77_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN78 ======================================================= */ + #define R_MFWD_FWFRPPCN78_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN78_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN79 ======================================================= */ + #define R_MFWD_FWFRPPCN79_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN79_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN80 ======================================================= */ + #define R_MFWD_FWFRPPCN80_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN80_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN81 ======================================================= */ + #define R_MFWD_FWFRPPCN81_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN81_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN82 ======================================================= */ + #define R_MFWD_FWFRPPCN82_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN82_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN83 ======================================================= */ + #define R_MFWD_FWFRPPCN83_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN83_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN84 ======================================================= */ + #define R_MFWD_FWFRPPCN84_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN84_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN85 ======================================================= */ + #define R_MFWD_FWFRPPCN85_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN85_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN86 ======================================================= */ + #define R_MFWD_FWFRPPCN86_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN86_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN87 ======================================================= */ + #define R_MFWD_FWFRPPCN87_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN87_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN88 ======================================================= */ + #define R_MFWD_FWFRPPCN88_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN88_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN89 ======================================================= */ + #define R_MFWD_FWFRPPCN89_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN89_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN90 ======================================================= */ + #define R_MFWD_FWFRPPCN90_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN90_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN91 ======================================================= */ + #define R_MFWD_FWFRPPCN91_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN91_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN92 ======================================================= */ + #define R_MFWD_FWFRPPCN92_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN92_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN93 ======================================================= */ + #define R_MFWD_FWFRPPCN93_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN93_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN94 ======================================================= */ + #define R_MFWD_FWFRPPCN94_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN94_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN95 ======================================================= */ + #define R_MFWD_FWFRPPCN95_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN95_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN96 ======================================================= */ + #define R_MFWD_FWFRPPCN96_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN96_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN97 ======================================================= */ + #define R_MFWD_FWFRPPCN97_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN97_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN98 ======================================================= */ + #define R_MFWD_FWFRPPCN98_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN98_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN99 ======================================================= */ + #define R_MFWD_FWFRPPCN99_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN99_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN100 ====================================================== */ + #define R_MFWD_FWFRPPCN100_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN100_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN101 ====================================================== */ + #define R_MFWD_FWFRPPCN101_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN101_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN102 ====================================================== */ + #define R_MFWD_FWFRPPCN102_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN102_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN103 ====================================================== */ + #define R_MFWD_FWFRPPCN103_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN103_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN104 ====================================================== */ + #define R_MFWD_FWFRPPCN104_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN104_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN105 ====================================================== */ + #define R_MFWD_FWFRPPCN105_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN105_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN106 ====================================================== */ + #define R_MFWD_FWFRPPCN106_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN106_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN107 ====================================================== */ + #define R_MFWD_FWFRPPCN107_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN107_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN108 ====================================================== */ + #define R_MFWD_FWFRPPCN108_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN108_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN109 ====================================================== */ + #define R_MFWD_FWFRPPCN109_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN109_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN110 ====================================================== */ + #define R_MFWD_FWFRPPCN110_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN110_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN111 ====================================================== */ + #define R_MFWD_FWFRPPCN111_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN111_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN112 ====================================================== */ + #define R_MFWD_FWFRPPCN112_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN112_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN113 ====================================================== */ + #define R_MFWD_FWFRPPCN113_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN113_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN114 ====================================================== */ + #define R_MFWD_FWFRPPCN114_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN114_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN115 ====================================================== */ + #define R_MFWD_FWFRPPCN115_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN115_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN116 ====================================================== */ + #define R_MFWD_FWFRPPCN116_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN116_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN117 ====================================================== */ + #define R_MFWD_FWFRPPCN117_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN117_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN118 ====================================================== */ + #define R_MFWD_FWFRPPCN118_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN118_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN119 ====================================================== */ + #define R_MFWD_FWFRPPCN119_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN119_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN120 ====================================================== */ + #define R_MFWD_FWFRPPCN120_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN120_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN121 ====================================================== */ + #define R_MFWD_FWFRPPCN121_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN121_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN122 ====================================================== */ + #define R_MFWD_FWFRPPCN122_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN122_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN123 ====================================================== */ + #define R_MFWD_FWFRPPCN123_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN123_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN124 ====================================================== */ + #define R_MFWD_FWFRPPCN124_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN124_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN125 ====================================================== */ + #define R_MFWD_FWFRPPCN125_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN125_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN126 ====================================================== */ + #define R_MFWD_FWFRPPCN126_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN126_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRPPCN127 ====================================================== */ + #define R_MFWD_FWFRPPCN127_PPC_Pos (0UL) /*!< PPC (Bit 0) */ + #define R_MFWD_FWFRPPCN127_PPC_Msk (0xffffUL) /*!< PPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN0 ======================================================= */ + #define R_MFWD_FWFRDPCN0_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN0_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN1 ======================================================= */ + #define R_MFWD_FWFRDPCN1_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN1_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN2 ======================================================= */ + #define R_MFWD_FWFRDPCN2_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN2_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN3 ======================================================= */ + #define R_MFWD_FWFRDPCN3_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN3_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN4 ======================================================= */ + #define R_MFWD_FWFRDPCN4_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN4_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN5 ======================================================= */ + #define R_MFWD_FWFRDPCN5_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN5_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN6 ======================================================= */ + #define R_MFWD_FWFRDPCN6_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN6_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN7 ======================================================= */ + #define R_MFWD_FWFRDPCN7_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN7_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN8 ======================================================= */ + #define R_MFWD_FWFRDPCN8_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN8_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= FWFRDPCN9 ======================================================= */ + #define R_MFWD_FWFRDPCN9_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN9_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN10 ======================================================= */ + #define R_MFWD_FWFRDPCN10_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN10_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN11 ======================================================= */ + #define R_MFWD_FWFRDPCN11_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN11_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN12 ======================================================= */ + #define R_MFWD_FWFRDPCN12_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN12_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN13 ======================================================= */ + #define R_MFWD_FWFRDPCN13_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN13_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN14 ======================================================= */ + #define R_MFWD_FWFRDPCN14_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN14_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN15 ======================================================= */ + #define R_MFWD_FWFRDPCN15_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN15_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN16 ======================================================= */ + #define R_MFWD_FWFRDPCN16_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN16_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN17 ======================================================= */ + #define R_MFWD_FWFRDPCN17_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN17_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN18 ======================================================= */ + #define R_MFWD_FWFRDPCN18_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN18_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN19 ======================================================= */ + #define R_MFWD_FWFRDPCN19_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN19_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN20 ======================================================= */ + #define R_MFWD_FWFRDPCN20_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN20_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN21 ======================================================= */ + #define R_MFWD_FWFRDPCN21_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN21_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN22 ======================================================= */ + #define R_MFWD_FWFRDPCN22_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN22_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN23 ======================================================= */ + #define R_MFWD_FWFRDPCN23_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN23_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN24 ======================================================= */ + #define R_MFWD_FWFRDPCN24_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN24_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN25 ======================================================= */ + #define R_MFWD_FWFRDPCN25_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN25_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN26 ======================================================= */ + #define R_MFWD_FWFRDPCN26_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN26_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN27 ======================================================= */ + #define R_MFWD_FWFRDPCN27_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN27_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN28 ======================================================= */ + #define R_MFWD_FWFRDPCN28_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN28_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN29 ======================================================= */ + #define R_MFWD_FWFRDPCN29_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN29_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN30 ======================================================= */ + #define R_MFWD_FWFRDPCN30_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN30_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN31 ======================================================= */ + #define R_MFWD_FWFRDPCN31_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN31_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN32 ======================================================= */ + #define R_MFWD_FWFRDPCN32_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN32_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN33 ======================================================= */ + #define R_MFWD_FWFRDPCN33_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN33_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN34 ======================================================= */ + #define R_MFWD_FWFRDPCN34_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN34_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN35 ======================================================= */ + #define R_MFWD_FWFRDPCN35_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN35_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN36 ======================================================= */ + #define R_MFWD_FWFRDPCN36_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN36_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN37 ======================================================= */ + #define R_MFWD_FWFRDPCN37_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN37_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN38 ======================================================= */ + #define R_MFWD_FWFRDPCN38_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN38_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN39 ======================================================= */ + #define R_MFWD_FWFRDPCN39_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN39_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN40 ======================================================= */ + #define R_MFWD_FWFRDPCN40_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN40_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN41 ======================================================= */ + #define R_MFWD_FWFRDPCN41_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN41_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN42 ======================================================= */ + #define R_MFWD_FWFRDPCN42_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN42_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN43 ======================================================= */ + #define R_MFWD_FWFRDPCN43_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN43_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN44 ======================================================= */ + #define R_MFWD_FWFRDPCN44_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN44_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN45 ======================================================= */ + #define R_MFWD_FWFRDPCN45_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN45_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN46 ======================================================= */ + #define R_MFWD_FWFRDPCN46_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN46_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN47 ======================================================= */ + #define R_MFWD_FWFRDPCN47_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN47_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN48 ======================================================= */ + #define R_MFWD_FWFRDPCN48_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN48_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN49 ======================================================= */ + #define R_MFWD_FWFRDPCN49_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN49_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN50 ======================================================= */ + #define R_MFWD_FWFRDPCN50_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN50_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN51 ======================================================= */ + #define R_MFWD_FWFRDPCN51_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN51_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN52 ======================================================= */ + #define R_MFWD_FWFRDPCN52_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN52_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN53 ======================================================= */ + #define R_MFWD_FWFRDPCN53_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN53_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN54 ======================================================= */ + #define R_MFWD_FWFRDPCN54_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN54_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN55 ======================================================= */ + #define R_MFWD_FWFRDPCN55_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN55_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN56 ======================================================= */ + #define R_MFWD_FWFRDPCN56_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN56_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN57 ======================================================= */ + #define R_MFWD_FWFRDPCN57_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN57_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN58 ======================================================= */ + #define R_MFWD_FWFRDPCN58_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN58_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN59 ======================================================= */ + #define R_MFWD_FWFRDPCN59_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN59_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN60 ======================================================= */ + #define R_MFWD_FWFRDPCN60_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN60_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN61 ======================================================= */ + #define R_MFWD_FWFRDPCN61_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN61_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN62 ======================================================= */ + #define R_MFWD_FWFRDPCN62_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN62_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN63 ======================================================= */ + #define R_MFWD_FWFRDPCN63_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN63_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN64 ======================================================= */ + #define R_MFWD_FWFRDPCN64_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN64_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN65 ======================================================= */ + #define R_MFWD_FWFRDPCN65_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN65_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN66 ======================================================= */ + #define R_MFWD_FWFRDPCN66_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN66_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN67 ======================================================= */ + #define R_MFWD_FWFRDPCN67_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN67_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN68 ======================================================= */ + #define R_MFWD_FWFRDPCN68_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN68_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN69 ======================================================= */ + #define R_MFWD_FWFRDPCN69_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN69_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN70 ======================================================= */ + #define R_MFWD_FWFRDPCN70_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN70_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN71 ======================================================= */ + #define R_MFWD_FWFRDPCN71_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN71_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN72 ======================================================= */ + #define R_MFWD_FWFRDPCN72_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN72_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN73 ======================================================= */ + #define R_MFWD_FWFRDPCN73_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN73_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN74 ======================================================= */ + #define R_MFWD_FWFRDPCN74_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN74_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN75 ======================================================= */ + #define R_MFWD_FWFRDPCN75_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN75_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN76 ======================================================= */ + #define R_MFWD_FWFRDPCN76_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN76_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN77 ======================================================= */ + #define R_MFWD_FWFRDPCN77_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN77_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN78 ======================================================= */ + #define R_MFWD_FWFRDPCN78_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN78_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN79 ======================================================= */ + #define R_MFWD_FWFRDPCN79_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN79_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN80 ======================================================= */ + #define R_MFWD_FWFRDPCN80_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN80_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN81 ======================================================= */ + #define R_MFWD_FWFRDPCN81_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN81_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN82 ======================================================= */ + #define R_MFWD_FWFRDPCN82_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN82_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN83 ======================================================= */ + #define R_MFWD_FWFRDPCN83_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN83_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN84 ======================================================= */ + #define R_MFWD_FWFRDPCN84_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN84_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN85 ======================================================= */ + #define R_MFWD_FWFRDPCN85_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN85_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN86 ======================================================= */ + #define R_MFWD_FWFRDPCN86_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN86_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN87 ======================================================= */ + #define R_MFWD_FWFRDPCN87_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN87_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN88 ======================================================= */ + #define R_MFWD_FWFRDPCN88_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN88_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN89 ======================================================= */ + #define R_MFWD_FWFRDPCN89_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN89_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN90 ======================================================= */ + #define R_MFWD_FWFRDPCN90_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN90_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN91 ======================================================= */ + #define R_MFWD_FWFRDPCN91_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN91_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN92 ======================================================= */ + #define R_MFWD_FWFRDPCN92_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN92_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN93 ======================================================= */ + #define R_MFWD_FWFRDPCN93_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN93_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN94 ======================================================= */ + #define R_MFWD_FWFRDPCN94_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN94_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN95 ======================================================= */ + #define R_MFWD_FWFRDPCN95_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN95_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN96 ======================================================= */ + #define R_MFWD_FWFRDPCN96_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN96_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN97 ======================================================= */ + #define R_MFWD_FWFRDPCN97_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN97_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN98 ======================================================= */ + #define R_MFWD_FWFRDPCN98_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN98_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN99 ======================================================= */ + #define R_MFWD_FWFRDPCN99_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN99_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN100 ====================================================== */ + #define R_MFWD_FWFRDPCN100_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN100_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN101 ====================================================== */ + #define R_MFWD_FWFRDPCN101_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN101_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN102 ====================================================== */ + #define R_MFWD_FWFRDPCN102_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN102_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN103 ====================================================== */ + #define R_MFWD_FWFRDPCN103_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN103_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN104 ====================================================== */ + #define R_MFWD_FWFRDPCN104_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN104_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN105 ====================================================== */ + #define R_MFWD_FWFRDPCN105_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN105_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN106 ====================================================== */ + #define R_MFWD_FWFRDPCN106_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN106_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN107 ====================================================== */ + #define R_MFWD_FWFRDPCN107_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN107_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN108 ====================================================== */ + #define R_MFWD_FWFRDPCN108_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN108_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN109 ====================================================== */ + #define R_MFWD_FWFRDPCN109_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN109_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN110 ====================================================== */ + #define R_MFWD_FWFRDPCN110_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN110_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN111 ====================================================== */ + #define R_MFWD_FWFRDPCN111_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN111_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN112 ====================================================== */ + #define R_MFWD_FWFRDPCN112_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN112_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN113 ====================================================== */ + #define R_MFWD_FWFRDPCN113_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN113_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN114 ====================================================== */ + #define R_MFWD_FWFRDPCN114_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN114_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN115 ====================================================== */ + #define R_MFWD_FWFRDPCN115_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN115_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN116 ====================================================== */ + #define R_MFWD_FWFRDPCN116_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN116_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN117 ====================================================== */ + #define R_MFWD_FWFRDPCN117_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN117_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN118 ====================================================== */ + #define R_MFWD_FWFRDPCN118_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN118_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN119 ====================================================== */ + #define R_MFWD_FWFRDPCN119_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN119_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN120 ====================================================== */ + #define R_MFWD_FWFRDPCN120_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN120_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN121 ====================================================== */ + #define R_MFWD_FWFRDPCN121_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN121_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN122 ====================================================== */ + #define R_MFWD_FWFRDPCN122_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN122_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN123 ====================================================== */ + #define R_MFWD_FWFRDPCN123_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN123_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN124 ====================================================== */ + #define R_MFWD_FWFRDPCN124_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN124_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN125 ====================================================== */ + #define R_MFWD_FWFRDPCN125_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN125_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN126 ====================================================== */ + #define R_MFWD_FWFRDPCN126_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN126_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== FWFRDPCN127 ====================================================== */ + #define R_MFWD_FWFRDPCN127_DPC_Pos (0UL) /*!< DPC (Bit 0) */ + #define R_MFWD_FWFRDPCN127_DPC_Msk (0xffffUL) /*!< DPC (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIS00 ======================================================== */ + #define R_MFWD_FWEIS00_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS00_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS00_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS00_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS00_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS00_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS00_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS00_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS00_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS00_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS00_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS00_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS00_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS00_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS00_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS00_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS00_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS00_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS00_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS00_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS00_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS00_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS01 ======================================================== */ + #define R_MFWD_FWEIS01_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS01_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS01_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS01_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS01_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS01_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS01_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS01_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS01_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS01_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS01_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS01_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS01_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS01_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS01_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS01_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS01_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS01_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS01_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS01_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS01_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS01_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS02 ======================================================== */ + #define R_MFWD_FWEIS02_LTHSPFS_Pos (0UL) /*!< LTHSPFS (Bit 0) */ + #define R_MFWD_FWEIS02_LTHSPFS_Msk (0x1UL) /*!< LTHSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTHNTFS_Pos (2UL) /*!< LTHNTFS (Bit 2) */ + #define R_MFWD_FWEIS02_LTHNTFS_Msk (0x4UL) /*!< LTHNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTHUFS_Pos (3UL) /*!< LTHUFS (Bit 3) */ + #define R_MFWD_FWEIS02_LTHUFS_Msk (0x8UL) /*!< LTHUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWDSPFS_Pos (10UL) /*!< LTWDSPFS (Bit 10) */ + #define R_MFWD_FWEIS02_LTWDSPFS_Msk (0x400UL) /*!< LTWDSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWSSPFS_Pos (11UL) /*!< LTWSSPFS (Bit 11) */ + #define R_MFWD_FWEIS02_LTWSSPFS_Msk (0x800UL) /*!< LTWSSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWVSPFS_Pos (12UL) /*!< LTWVSPFS (Bit 12) */ + #define R_MFWD_FWEIS02_LTWVSPFS_Msk (0x1000UL) /*!< LTWVSPFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWNTFS_Pos (13UL) /*!< LTWNTFS (Bit 13) */ + #define R_MFWD_FWEIS02_LTWNTFS_Msk (0x2000UL) /*!< LTWNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWSUFS_Pos (14UL) /*!< LTWSUFS (Bit 14) */ + #define R_MFWD_FWEIS02_LTWSUFS_Msk (0x4000UL) /*!< LTWSUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWDUFS_Pos (15UL) /*!< LTWDUFS (Bit 15) */ + #define R_MFWD_FWEIS02_LTWDUFS_Msk (0x8000UL) /*!< LTWDUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_LTWVUFS_Pos (16UL) /*!< LTWVUFS (Bit 16) */ + #define R_MFWD_FWEIS02_LTWVUFS_Msk (0x10000UL) /*!< LTWVUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_PBNTFS_Pos (17UL) /*!< PBNTFS (Bit 17) */ + #define R_MFWD_FWEIS02_PBNTFS_Msk (0x20000UL) /*!< PBNTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_SMHLFS_Pos (18UL) /*!< SMHLFS (Bit 18) */ + #define R_MFWD_FWEIS02_SMHLFS_Msk (0x40000UL) /*!< SMHLFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_SMHMFS_Pos (19UL) /*!< SMHMFS (Bit 19) */ + #define R_MFWD_FWEIS02_SMHMFS_Msk (0x80000UL) /*!< SMHMFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMCFS_Pos (22UL) /*!< WMCFS (Bit 22) */ + #define R_MFWD_FWEIS02_WMCFS_Msk (0x400000UL) /*!< WMCFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMFFS_Pos (23UL) /*!< WMFFS (Bit 23) */ + #define R_MFWD_FWEIS02_WMFFS_Msk (0x800000UL) /*!< WMFFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMISFS_Pos (24UL) /*!< WMISFS (Bit 24) */ + #define R_MFWD_FWEIS02_WMISFS_Msk (0x1000000UL) /*!< WMISFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_WMIUFS_Pos (25UL) /*!< WMIUFS (Bit 25) */ + #define R_MFWD_FWEIS02_WMIUFS_Msk (0x2000000UL) /*!< WMIUFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDES_Pos (26UL) /*!< DDES (Bit 26) */ + #define R_MFWD_FWEIS02_DDES_Msk (0x4000000UL) /*!< DDES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDSES_Pos (28UL) /*!< DDSES (Bit 28) */ + #define R_MFWD_FWEIS02_DDSES_Msk (0x10000000UL) /*!< DDSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS02_DDNTFS_Pos (29UL) /*!< DDNTFS (Bit 29) */ + #define R_MFWD_FWEIS02_DDNTFS_Msk (0x20000000UL) /*!< DDNTFS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE00 ======================================================== */ + #define R_MFWD_FWEIE00_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE00_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE00_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE00_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE00_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE00_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE00_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE00_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE00_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE00_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE00_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE00_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE00_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE00_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE00_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE00_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE00_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE00_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE00_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE00_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE00_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE00_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE00_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE01 ======================================================== */ + #define R_MFWD_FWEIE01_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE01_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE01_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE01_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE01_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE01_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE01_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE01_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE01_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE01_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE01_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE01_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE01_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE01_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE01_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE01_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE01_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE01_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE01_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE01_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE01_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE01_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE01_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE02 ======================================================== */ + #define R_MFWD_FWEIE02_LTHSPFE_Pos (0UL) /*!< LTHSPFE (Bit 0) */ + #define R_MFWD_FWEIE02_LTHSPFE_Msk (0x1UL) /*!< LTHSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTHNTFE_Pos (2UL) /*!< LTHNTFE (Bit 2) */ + #define R_MFWD_FWEIE02_LTHNTFE_Msk (0x4UL) /*!< LTHNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTHUFE_Pos (3UL) /*!< LTHUFE (Bit 3) */ + #define R_MFWD_FWEIE02_LTHUFE_Msk (0x8UL) /*!< LTHUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWDSPFE_Pos (10UL) /*!< LTWDSPFE (Bit 10) */ + #define R_MFWD_FWEIE02_LTWDSPFE_Msk (0x400UL) /*!< LTWDSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWSSPFE_Pos (11UL) /*!< LTWSSPFE (Bit 11) */ + #define R_MFWD_FWEIE02_LTWSSPFE_Msk (0x800UL) /*!< LTWSSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWVSPFE_Pos (12UL) /*!< LTWVSPFE (Bit 12) */ + #define R_MFWD_FWEIE02_LTWVSPFE_Msk (0x1000UL) /*!< LTWVSPFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWNTFE_Pos (13UL) /*!< LTWNTFE (Bit 13) */ + #define R_MFWD_FWEIE02_LTWNTFE_Msk (0x2000UL) /*!< LTWNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWSUFE_Pos (14UL) /*!< LTWSUFE (Bit 14) */ + #define R_MFWD_FWEIE02_LTWSUFE_Msk (0x4000UL) /*!< LTWSUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWDUFE_Pos (15UL) /*!< LTWDUFE (Bit 15) */ + #define R_MFWD_FWEIE02_LTWDUFE_Msk (0x8000UL) /*!< LTWDUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_LTWVUFE_Pos (16UL) /*!< LTWVUFE (Bit 16) */ + #define R_MFWD_FWEIE02_LTWVUFE_Msk (0x10000UL) /*!< LTWVUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_PBNTFE_Pos (17UL) /*!< PBNTFE (Bit 17) */ + #define R_MFWD_FWEIE02_PBNTFE_Msk (0x20000UL) /*!< PBNTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_SMHLFE_Pos (18UL) /*!< SMHLFE (Bit 18) */ + #define R_MFWD_FWEIE02_SMHLFE_Msk (0x40000UL) /*!< SMHLFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_SMHMFE_Pos (19UL) /*!< SMHMFE (Bit 19) */ + #define R_MFWD_FWEIE02_SMHMFE_Msk (0x80000UL) /*!< SMHMFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMCFE_Pos (22UL) /*!< WMCFE (Bit 22) */ + #define R_MFWD_FWEIE02_WMCFE_Msk (0x400000UL) /*!< WMCFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMFFE_Pos (23UL) /*!< WMFFE (Bit 23) */ + #define R_MFWD_FWEIE02_WMFFE_Msk (0x800000UL) /*!< WMFFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMISFE_Pos (24UL) /*!< WMISFE (Bit 24) */ + #define R_MFWD_FWEIE02_WMISFE_Msk (0x1000000UL) /*!< WMISFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_WMIUFE_Pos (25UL) /*!< WMIUFE (Bit 25) */ + #define R_MFWD_FWEIE02_WMIUFE_Msk (0x2000000UL) /*!< WMIUFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDEE_Pos (26UL) /*!< DDEE (Bit 26) */ + #define R_MFWD_FWEIE02_DDEE_Msk (0x4000000UL) /*!< DDEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDFEE_Pos (27UL) /*!< DDFEE (Bit 27) */ + #define R_MFWD_FWEIE02_DDFEE_Msk (0x8000000UL) /*!< DDFEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDSEE_Pos (28UL) /*!< DDSEE (Bit 28) */ + #define R_MFWD_FWEIE02_DDSEE_Msk (0x10000000UL) /*!< DDSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE02_DDNTFE_Pos (29UL) /*!< DDNTFE (Bit 29) */ + #define R_MFWD_FWEIE02_DDNTFE_Msk (0x20000000UL) /*!< DDNTFE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID00 ======================================================== */ + #define R_MFWD_FWEID00_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID00_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID00_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID00_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID00_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID00_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID00_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID00_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID00_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID00_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID00_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID00_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID00_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID00_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID00_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID00_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID00_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID00_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID00_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID00_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID00_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID00_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID00_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID01 ======================================================== */ + #define R_MFWD_FWEID01_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID01_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID01_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID01_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID01_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID01_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID01_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID01_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID01_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID01_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID01_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID01_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID01_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID01_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID01_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID01_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID01_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID01_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID01_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID01_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID01_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID01_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID01_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID02 ======================================================== */ + #define R_MFWD_FWEID02_LTHSPFD_Pos (0UL) /*!< LTHSPFD (Bit 0) */ + #define R_MFWD_FWEID02_LTHSPFD_Msk (0x1UL) /*!< LTHSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTHNTFD_Pos (2UL) /*!< LTHNTFD (Bit 2) */ + #define R_MFWD_FWEID02_LTHNTFD_Msk (0x4UL) /*!< LTHNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTHUFD_Pos (3UL) /*!< LTHUFD (Bit 3) */ + #define R_MFWD_FWEID02_LTHUFD_Msk (0x8UL) /*!< LTHUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWDSPFD_Pos (10UL) /*!< LTWDSPFD (Bit 10) */ + #define R_MFWD_FWEID02_LTWDSPFD_Msk (0x400UL) /*!< LTWDSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWSSPFD_Pos (11UL) /*!< LTWSSPFD (Bit 11) */ + #define R_MFWD_FWEID02_LTWSSPFD_Msk (0x800UL) /*!< LTWSSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWVSPFD_Pos (12UL) /*!< LTWVSPFD (Bit 12) */ + #define R_MFWD_FWEID02_LTWVSPFD_Msk (0x1000UL) /*!< LTWVSPFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWNTFD_Pos (13UL) /*!< LTWNTFD (Bit 13) */ + #define R_MFWD_FWEID02_LTWNTFD_Msk (0x2000UL) /*!< LTWNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWSUFD_Pos (14UL) /*!< LTWSUFD (Bit 14) */ + #define R_MFWD_FWEID02_LTWSUFD_Msk (0x4000UL) /*!< LTWSUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWDUFD_Pos (15UL) /*!< LTWDUFD (Bit 15) */ + #define R_MFWD_FWEID02_LTWDUFD_Msk (0x8000UL) /*!< LTWDUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_LTWVUFD_Pos (16UL) /*!< LTWVUFD (Bit 16) */ + #define R_MFWD_FWEID02_LTWVUFD_Msk (0x10000UL) /*!< LTWVUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_PBNTFD_Pos (17UL) /*!< PBNTFD (Bit 17) */ + #define R_MFWD_FWEID02_PBNTFD_Msk (0x20000UL) /*!< PBNTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_SMHLFD_Pos (18UL) /*!< SMHLFD (Bit 18) */ + #define R_MFWD_FWEID02_SMHLFD_Msk (0x40000UL) /*!< SMHLFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_SMHMFD_Pos (19UL) /*!< SMHMFD (Bit 19) */ + #define R_MFWD_FWEID02_SMHMFD_Msk (0x80000UL) /*!< SMHMFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMCFD_Pos (22UL) /*!< WMCFD (Bit 22) */ + #define R_MFWD_FWEID02_WMCFD_Msk (0x400000UL) /*!< WMCFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMFFD_Pos (23UL) /*!< WMFFD (Bit 23) */ + #define R_MFWD_FWEID02_WMFFD_Msk (0x800000UL) /*!< WMFFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMISFD_Pos (24UL) /*!< WMISFD (Bit 24) */ + #define R_MFWD_FWEID02_WMISFD_Msk (0x1000000UL) /*!< WMISFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_WMIUFD_Pos (25UL) /*!< WMIUFD (Bit 25) */ + #define R_MFWD_FWEID02_WMIUFD_Msk (0x2000000UL) /*!< WMIUFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDED_Pos (26UL) /*!< DDED (Bit 26) */ + #define R_MFWD_FWEID02_DDED_Msk (0x4000000UL) /*!< DDED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDFED_Pos (27UL) /*!< DDFED (Bit 27) */ + #define R_MFWD_FWEID02_DDFED_Msk (0x8000000UL) /*!< DDFED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDSED_Pos (28UL) /*!< DDSED (Bit 28) */ + #define R_MFWD_FWEID02_DDSED_Msk (0x10000000UL) /*!< DDSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID02_DDNTFD_Pos (29UL) /*!< DDNTFD (Bit 29) */ + #define R_MFWD_FWEID02_DDNTFD_Msk (0x20000000UL) /*!< DDNTFD (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS1 ========================================================= */ + #define R_MFWD_FWEIS1_LTHTEES_Pos (0UL) /*!< LTHTEES (Bit 0) */ + #define R_MFWD_FWEIS1_LTHTEES_Msk (0x1UL) /*!< LTHTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_LTHTSES_Pos (1UL) /*!< LTHTSES (Bit 1) */ + #define R_MFWD_FWEIS1_LTHTSES_Msk (0x2UL) /*!< LTHTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_MACTEES_Pos (4UL) /*!< MACTEES (Bit 4) */ + #define R_MFWD_FWEIS1_MACTEES_Msk (0x10UL) /*!< MACTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_MACTSES_Pos (5UL) /*!< MACTSES (Bit 5) */ + #define R_MFWD_FWEIS1_MACTSES_Msk (0x20UL) /*!< MACTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_VLANTEES_Pos (6UL) /*!< VLANTEES (Bit 6) */ + #define R_MFWD_FWEIS1_VLANTEES_Msk (0x40UL) /*!< VLANTEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_VLANTSES_Pos (7UL) /*!< VLANTSES (Bit 7) */ + #define R_MFWD_FWEIS1_VLANTSES_Msk (0x80UL) /*!< VLANTSES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_L23UEES_Pos (8UL) /*!< L23UEES (Bit 8) */ + #define R_MFWD_FWEIS1_L23UEES_Msk (0x100UL) /*!< L23UEES (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIS1_AREES_Pos (16UL) /*!< AREES (Bit 16) */ + #define R_MFWD_FWEIS1_AREES_Msk (0x10000UL) /*!< AREES (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIE1 ========================================================= */ + #define R_MFWD_FWEIE1_LTHTEEE_Pos (0UL) /*!< LTHTEEE (Bit 0) */ + #define R_MFWD_FWEIE1_LTHTEEE_Msk (0x1UL) /*!< LTHTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_LTHTSEE_Pos (1UL) /*!< LTHTSEE (Bit 1) */ + #define R_MFWD_FWEIE1_LTHTSEE_Msk (0x2UL) /*!< LTHTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_MACTEEE_Pos (4UL) /*!< MACTEEE (Bit 4) */ + #define R_MFWD_FWEIE1_MACTEEE_Msk (0x10UL) /*!< MACTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_MACTSEE_Pos (5UL) /*!< MACTSEE (Bit 5) */ + #define R_MFWD_FWEIE1_MACTSEE_Msk (0x20UL) /*!< MACTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_VLANTEEE_Pos (6UL) /*!< VLANTEEE (Bit 6) */ + #define R_MFWD_FWEIE1_VLANTEEE_Msk (0x40UL) /*!< VLANTEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_VLANTSEE_Pos (7UL) /*!< VLANTSEE (Bit 7) */ + #define R_MFWD_FWEIE1_VLANTSEE_Msk (0x80UL) /*!< VLANTSEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_L23UEEE_Pos (8UL) /*!< L23UEEE (Bit 8) */ + #define R_MFWD_FWEIE1_L23UEEE_Msk (0x100UL) /*!< L23UEEE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEIE1_AREEE_Pos (16UL) /*!< AREEE (Bit 16) */ + #define R_MFWD_FWEIE1_AREEE_Msk (0x10000UL) /*!< AREEE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEID1 ========================================================= */ + #define R_MFWD_FWEID1_LTHTEED_Pos (0UL) /*!< LTHTEED (Bit 0) */ + #define R_MFWD_FWEID1_LTHTEED_Msk (0x1UL) /*!< LTHTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_LTHTSED_Pos (1UL) /*!< LTHTSED (Bit 1) */ + #define R_MFWD_FWEID1_LTHTSED_Msk (0x2UL) /*!< LTHTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_MACTEED_Pos (4UL) /*!< MACTEED (Bit 4) */ + #define R_MFWD_FWEID1_MACTEED_Msk (0x10UL) /*!< MACTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_MACTSED_Pos (5UL) /*!< MACTSED (Bit 5) */ + #define R_MFWD_FWEID1_MACTSED_Msk (0x20UL) /*!< MACTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_VLANTEED_Pos (6UL) /*!< VLANTEED (Bit 6) */ + #define R_MFWD_FWEID1_VLANTEED_Msk (0x40UL) /*!< VLANTEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_VLANTSED_Pos (7UL) /*!< VLANTSED (Bit 7) */ + #define R_MFWD_FWEID1_VLANTSED_Msk (0x80UL) /*!< VLANTSED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_L23UEED_Pos (8UL) /*!< L23UEED (Bit 8) */ + #define R_MFWD_FWEID1_L23UEED_Msk (0x100UL) /*!< L23UEED (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWEID1_AREED_Pos (16UL) /*!< AREED (Bit 16) */ + #define R_MFWD_FWEID1_AREED_Msk (0x10000UL) /*!< AREED (Bitfield-Mask: 0x01) */ +/* ======================================================== FWEIS2 ========================================================= */ + #define R_MFWD_FWEIS2_PMFS_Pos (0UL) /*!< PMFS (Bit 0) */ + #define R_MFWD_FWEIS2_PMFS_Msk (0xffffUL) /*!< PMFS (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIE2 ========================================================= */ + #define R_MFWD_FWEIE2_PMFE_Pos (0UL) /*!< PMFE (Bit 0) */ + #define R_MFWD_FWEIE2_PMFE_Msk (0xffffUL) /*!< PMFE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEID2 ========================================================= */ + #define R_MFWD_FWEID2_PMFD_Pos (0UL) /*!< PMFD (Bit 0) */ + #define R_MFWD_FWEID2_PMFD_Msk (0xffffUL) /*!< PMFD (Bitfield-Mask: 0xffff) */ +/* ======================================================== FWEIS5 ========================================================= */ + #define R_MFWD_FWEIS5_PMRFS_Pos (0UL) /*!< PMRFS (Bit 0) */ + #define R_MFWD_FWEIS5_PMRFS_Msk (0xffffffffUL) /*!< PMRFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE5 ========================================================= */ + #define R_MFWD_FWEIE5_PMRFE_Pos (0UL) /*!< PMRFE (Bit 0) */ + #define R_MFWD_FWEIE5_PMRFE_Msk (0xffffffffUL) /*!< PMRFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID5 ========================================================= */ + #define R_MFWD_FWEID5_PMRFD_Pos (0UL) /*!< PMRFD (Bit 0) */ + #define R_MFWD_FWEID5_PMRFD_Msk (0xffffffffUL) /*!< PMRFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS60 ======================================================== */ + #define R_MFWD_FWEIS60_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS60_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS61 ======================================================== */ + #define R_MFWD_FWEIS61_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS61_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS62 ======================================================== */ + #define R_MFWD_FWEIS62_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS62_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS63 ======================================================== */ + #define R_MFWD_FWEIS63_FFS_Pos (0UL) /*!< FFS (Bit 0) */ + #define R_MFWD_FWEIS63_FFS_Msk (0xffffffffUL) /*!< FFS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE60 ======================================================== */ + #define R_MFWD_FWEIE60_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE60_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE61 ======================================================== */ + #define R_MFWD_FWEIE61_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE61_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE62 ======================================================== */ + #define R_MFWD_FWEIE62_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE62_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE63 ======================================================== */ + #define R_MFWD_FWEIE63_FFE_Pos (0UL) /*!< FFE (Bit 0) */ + #define R_MFWD_FWEIE63_FFE_Msk (0xffffffffUL) /*!< FFE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID60 ======================================================== */ + #define R_MFWD_FWEID60_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID60_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID61 ======================================================== */ + #define R_MFWD_FWEID61_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID61_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID62 ======================================================== */ + #define R_MFWD_FWEID62_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID62_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID63 ======================================================== */ + #define R_MFWD_FWEID63_FFD_Pos (0UL) /*!< FFD (Bit 0) */ + #define R_MFWD_FWEID63_FFD_Msk (0xffffffffUL) /*!< FFD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS70 ======================================================== */ + #define R_MFWD_FWEIS70_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS70_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS71 ======================================================== */ + #define R_MFWD_FWEIS71_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS71_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS72 ======================================================== */ + #define R_MFWD_FWEIS72_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS72_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS73 ======================================================== */ + #define R_MFWD_FWEIS73_FOORS_Pos (0UL) /*!< FOORS (Bit 0) */ + #define R_MFWD_FWEIS73_FOORS_Msk (0xffffffffUL) /*!< FOORS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE70 ======================================================== */ + #define R_MFWD_FWEIE70_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE70_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE71 ======================================================== */ + #define R_MFWD_FWEIE71_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE71_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE72 ======================================================== */ + #define R_MFWD_FWEIE72_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE72_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE73 ======================================================== */ + #define R_MFWD_FWEIE73_FOORE_Pos (0UL) /*!< FOORE (Bit 0) */ + #define R_MFWD_FWEIE73_FOORE_Msk (0xffffffffUL) /*!< FOORE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID70 ======================================================== */ + #define R_MFWD_FWEID70_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID70_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID71 ======================================================== */ + #define R_MFWD_FWEID71_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID71_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID72 ======================================================== */ + #define R_MFWD_FWEID72_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID72_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID73 ======================================================== */ + #define R_MFWD_FWEID73_FOORD_Pos (0UL) /*!< FOORD (Bit 0) */ + #define R_MFWD_FWEID73_FOORD_Msk (0xffffffffUL) /*!< FOORD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS80 ======================================================== */ + #define R_MFWD_FWEIS80_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS80_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS81 ======================================================== */ + #define R_MFWD_FWEIS81_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS81_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS82 ======================================================== */ + #define R_MFWD_FWEIS82_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS82_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIS83 ======================================================== */ + #define R_MFWD_FWEIS83_TOS_Pos (0UL) /*!< TOS (Bit 0) */ + #define R_MFWD_FWEIS83_TOS_Msk (0xffffffffUL) /*!< TOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE80 ======================================================== */ + #define R_MFWD_FWEIE80_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE80_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE81 ======================================================== */ + #define R_MFWD_FWEIE81_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE81_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE82 ======================================================== */ + #define R_MFWD_FWEIE82_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE82_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEIE83 ======================================================== */ + #define R_MFWD_FWEIE83_TOE_Pos (0UL) /*!< TOE (Bit 0) */ + #define R_MFWD_FWEIE83_TOE_Msk (0xffffffffUL) /*!< TOE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID80 ======================================================== */ + #define R_MFWD_FWEID80_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID80_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID81 ======================================================== */ + #define R_MFWD_FWEID81_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID81_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID82 ======================================================== */ + #define R_MFWD_FWEID82_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID82_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWEID83 ======================================================== */ + #define R_MFWD_FWEID83_TOD_Pos (0UL) /*!< TOD (Bit 0) */ + #define R_MFWD_FWEID83_TOD_Msk (0xffffffffUL) /*!< TOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FWMIS0 ========================================================= */ + #define R_MFWD_FWMIS0_LTHTFS_Pos (0UL) /*!< LTHTFS (Bit 0) */ + #define R_MFWD_FWMIS0_LTHTFS_Msk (0x1UL) /*!< LTHTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_MACTFS_Pos (2UL) /*!< MACTFS (Bit 2) */ + #define R_MFWD_FWMIS0_MACTFS_Msk (0x4UL) /*!< MACTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_VLANTFS_Pos (3UL) /*!< VLANTFS (Bit 3) */ + #define R_MFWD_FWMIS0_VLANTFS_Msk (0x8UL) /*!< VLANTFS (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIS0_MACADAS_Pos (17UL) /*!< MACADAS (Bit 17) */ + #define R_MFWD_FWMIS0_MACADAS_Msk (0x20000UL) /*!< MACADAS (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMIE0 ========================================================= */ + #define R_MFWD_FWMIE0_LTHTFE_Pos (0UL) /*!< LTHTFE (Bit 0) */ + #define R_MFWD_FWMIE0_LTHTFE_Msk (0x1UL) /*!< LTHTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_MACTFE_Pos (2UL) /*!< MACTFE (Bit 2) */ + #define R_MFWD_FWMIE0_MACTFE_Msk (0x4UL) /*!< MACTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_VLANTFE_Pos (3UL) /*!< VLANTFE (Bit 3) */ + #define R_MFWD_FWMIE0_VLANTFE_Msk (0x8UL) /*!< VLANTFE (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMIE0_MACADAE_Pos (17UL) /*!< MACADAE (Bit 17) */ + #define R_MFWD_FWMIE0_MACADAE_Msk (0x20000UL) /*!< MACADAE (Bitfield-Mask: 0x01) */ +/* ======================================================== FWMID0 ========================================================= */ + #define R_MFWD_FWMID0_LTHTFD_Pos (0UL) /*!< LTHTFD (Bit 0) */ + #define R_MFWD_FWMID0_LTHTFD_Msk (0x1UL) /*!< LTHTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_MACTFD_Pos (2UL) /*!< MACTFD (Bit 2) */ + #define R_MFWD_FWMID0_MACTFD_Msk (0x4UL) /*!< MACTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_VLANTFD_Pos (3UL) /*!< VLANTFD (Bit 3) */ + #define R_MFWD_FWMID0_VLANTFD_Msk (0x8UL) /*!< VLANTFD (Bitfield-Mask: 0x01) */ + #define R_MFWD_FWMID0_MACADAD_Pos (17UL) /*!< MACADAD (Bit 17) */ + #define R_MFWD_FWMID0_MACADAD_Msk (0x20000UL) /*!< MACADAD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MIPI_DSI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ISR ========================================================== */ + #define R_MIPI_DSI_ISR_SQ0_Pos (0UL) /*!< SQ0 (Bit 0) */ + #define R_MIPI_DSI_ISR_SQ0_Msk (0x1UL) /*!< SQ0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_SQ1_Pos (4UL) /*!< SQ1 (Bit 4) */ + #define R_MIPI_DSI_ISR_SQ1_Msk (0x10UL) /*!< SQ1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_VM_Pos (8UL) /*!< VM (Bit 8) */ + #define R_MIPI_DSI_ISR_VM_Msk (0x100UL) /*!< VM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_RCV_Pos (12UL) /*!< RCV (Bit 12) */ + #define R_MIPI_DSI_ISR_RCV_Msk (0x1000UL) /*!< RCV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_FERR_Pos (16UL) /*!< FERR (Bit 16) */ + #define R_MIPI_DSI_ISR_FERR_Msk (0x10000UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ISR_PPI_Pos (20UL) /*!< PPI (Bit 20) */ + #define R_MIPI_DSI_ISR_PPI_Msk (0x100000UL) /*!< PPI (Bitfield-Mask: 0x01) */ +/* ======================================================== LINKSR ========================================================= */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Pos (0UL) /*!< SQ0RUN (Bit 0) */ + #define R_MIPI_DSI_LINKSR_SQ0RUN_Msk (0x1UL) /*!< SQ0RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Pos (4UL) /*!< SQ1RUN (Bit 4) */ + #define R_MIPI_DSI_LINKSR_SQ1RUN_Msk (0x10UL) /*!< SQ1RUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_VRUN_Pos (8UL) /*!< VRUN (Bit 8) */ + #define R_MIPI_DSI_LINKSR_VRUN_Msk (0x100UL) /*!< VRUN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Pos (12UL) /*!< HSBUSY (Bit 12) */ + #define R_MIPI_DSI_LINKSR_HSBUSY_Msk (0x1000UL) /*!< HSBUSY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Pos (13UL) /*!< LPBUSY (Bit 13) */ + #define R_MIPI_DSI_LINKSR_LPBUSY_Msk (0x2000UL) /*!< LPBUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== TXSETR ========================================================= */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Pos (0UL) /*!< NUMLANE (Bit 0) */ + #define R_MIPI_DSI_TXSETR_NUMLANE_Msk (0x3UL) /*!< NUMLANE (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_TXSETR_CLEN_Pos (8UL) /*!< CLEN (Bit 8) */ + #define R_MIPI_DSI_TXSETR_CLEN_Msk (0x100UL) /*!< CLEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_TXSETR_DLEN_Pos (9UL) /*!< DLEN (Bit 9) */ + #define R_MIPI_DSI_TXSETR_DLEN_Msk (0x200UL) /*!< DLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= HSCLKSETR ======================================================= */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Pos (0UL) /*!< HSCLST (Bit 0) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLST_Msk (0x1UL) /*!< HSCLST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Pos (1UL) /*!< HSCLMD (Bit 1) */ + #define R_MIPI_DSI_HSCLKSETR_HSCLMD_Msk (0x2UL) /*!< HSCLMD (Bitfield-Mask: 0x01) */ +/* ======================================================= ULPSSETR ======================================================== */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Pos (0UL) /*!< WKUP (Bit 0) */ + #define R_MIPI_DSI_ULPSSETR_WKUP_Msk (0xffUL) /*!< WKUP (Bitfield-Mask: 0xff) */ +/* ======================================================== ULPSCR ========================================================= */ + #define R_MIPI_DSI_ULPSCR_CLENT_Pos (24UL) /*!< CLENT (Bit 24) */ + #define R_MIPI_DSI_ULPSCR_CLENT_Msk (0x1000000UL) /*!< CLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Pos (25UL) /*!< CLEXIT (Bit 25) */ + #define R_MIPI_DSI_ULPSCR_CLEXIT_Msk (0x2000000UL) /*!< CLEXIT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Pos (28UL) /*!< DLENT (Bit 28) */ + #define R_MIPI_DSI_ULPSCR_DLENT_Msk (0x10000000UL) /*!< DLENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Pos (29UL) /*!< DLEXIT (Bit 29) */ + #define R_MIPI_DSI_ULPSCR_DLEXIT_Msk (0x20000000UL) /*!< DLEXIT (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTCR ========================================================= */ + #define R_MIPI_DSI_RSTCR_SWRST_Pos (0UL) /*!< SWRST (Bit 0) */ + #define R_MIPI_DSI_RSTCR_SWRST_Msk (0x1UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Pos (16UL) /*!< FTXSTP (Bit 16) */ + #define R_MIPI_DSI_RSTCR_FTXSTP_Msk (0x10000UL) /*!< FTXSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= RSTSR ========================================================= */ + #define R_MIPI_DSI_RSTSR_RSTHS_Pos (0UL) /*!< RSTHS (Bit 0) */ + #define R_MIPI_DSI_RSTSR_RSTHS_Msk (0x1UL) /*!< RSTHS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Pos (1UL) /*!< RSTLP (Bit 1) */ + #define R_MIPI_DSI_RSTSR_RSTLP_Msk (0x2UL) /*!< RSTLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Pos (2UL) /*!< RSTAPB (Bit 2) */ + #define R_MIPI_DSI_RSTSR_RSTAPB_Msk (0x4UL) /*!< RSTAPB (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Pos (3UL) /*!< RSTAXI (Bit 3) */ + #define R_MIPI_DSI_RSTSR_RSTAXI_Msk (0x8UL) /*!< RSTAXI (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_RSTV_Pos (4UL) /*!< RSTV (Bit 4) */ + #define R_MIPI_DSI_RSTSR_RSTV_Msk (0x10UL) /*!< RSTV (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_RSTSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_RSTSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_RSTSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DSISETR ======================================================== */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Pos (0UL) /*!< MRPSZ (Bit 0) */ + #define R_MIPI_DSI_DSISETR_MRPSZ_Msk (0xffffUL) /*!< MRPSZ (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Pos (16UL) /*!< ECCEN (Bit 16) */ + #define R_MIPI_DSI_DSISETR_ECCEN_Msk (0x10000UL) /*!< ECCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Pos (20UL) /*!< VC0CRCEN (Bit 20) */ + #define R_MIPI_DSI_DSISETR_VC0CRCEN_Msk (0x100000UL) /*!< VC0CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Pos (21UL) /*!< VC1CRCEN (Bit 21) */ + #define R_MIPI_DSI_DSISETR_VC1CRCEN_Msk (0x200000UL) /*!< VC1CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Pos (22UL) /*!< VC2CRCEN (Bit 22) */ + #define R_MIPI_DSI_DSISETR_VC2CRCEN_Msk (0x400000UL) /*!< VC2CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Pos (23UL) /*!< VC3CRCEN (Bit 23) */ + #define R_MIPI_DSI_DSISETR_VC3CRCEN_Msk (0x800000UL) /*!< VC3CRCEN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_SCREN_Pos (29UL) /*!< SCREN (Bit 29) */ + #define R_MIPI_DSI_DSISETR_SCREN_Msk (0x20000000UL) /*!< SCREN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Pos (30UL) /*!< EXTEMD (Bit 30) */ + #define R_MIPI_DSI_DSISETR_EXTEMD_Msk (0x40000000UL) /*!< EXTEMD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Pos (31UL) /*!< EOTPEN (Bit 31) */ + #define R_MIPI_DSI_DSISETR_EOTPEN_Msk (0x80000000UL) /*!< EOTPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== TXPPD0R ======================================================== */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_TXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_TXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_TXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_TXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD1R ======================================================== */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_TXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_TXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_TXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_TXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD2R ======================================================== */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_TXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_TXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_TXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_TXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== TXPPD3R ======================================================== */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_TXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_TXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_TXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_TXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ========================================================= RXSR ========================================================== */ + #define R_MIPI_DSI_RXSR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSCR ========================================================= */ + #define R_MIPI_DSI_RXSCR_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXSCR_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXSCR_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXSCR_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXSCR_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXSCR_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXSCR_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXSCR_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXSCR_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXSCR_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXSCR_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXSCR_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXSCR_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXSCR_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXSCR_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXSCR_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXSCR_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXSCR_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXSCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ========================================================= RXIER ========================================================= */ + #define R_MIPI_DSI_RXIER_BTAREND_Pos (0UL) /*!< BTAREND (Bit 0) */ + #define R_MIPI_DSI_RXIER_BTAREND_Msk (0x1UL) /*!< BTAREND (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_RXIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_RXIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXRESP_Pos (8UL) /*!< RXRESP (Bit 8) */ + #define R_MIPI_DSI_RXIER_RXRESP_Msk (0x100UL) /*!< RXRESP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Pos (10UL) /*!< RXEOTP (Bit 10) */ + #define R_MIPI_DSI_RXIER_RXEOTP_Msk (0x400UL) /*!< RXEOTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXTE_Pos (13UL) /*!< RXTE (Bit 13) */ + #define R_MIPI_DSI_RXIER_RXTE_Msk (0x2000UL) /*!< RXTE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXACK_Pos (14UL) /*!< RXACK (Bit 14) */ + #define R_MIPI_DSI_RXIER_RXACK_Msk (0x4000UL) /*!< RXACK (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Pos (15UL) /*!< EXTEDET (Bit 15) */ + #define R_MIPI_DSI_RXIER_EXTEDET_Msk (0x8000UL) /*!< EXTEDET (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_MLFERR_Pos (16UL) /*!< MLFERR (Bit 16) */ + #define R_MIPI_DSI_RXIER_MLFERR_Msk (0x10000UL) /*!< MLFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Pos (17UL) /*!< ECCERRM (Bit 17) */ + #define R_MIPI_DSI_RXIER_ECCERRM_Msk (0x20000UL) /*!< ECCERRM (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Pos (18UL) /*!< UNEXERR (Bit 18) */ + #define R_MIPI_DSI_RXIER_UNEXERR_Msk (0x40000UL) /*!< UNEXERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_WCERR_Pos (20UL) /*!< WCERR (Bit 20) */ + #define R_MIPI_DSI_RXIER_WCERR_Msk (0x100000UL) /*!< WCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_CRCERR_Pos (21UL) /*!< CRCERR (Bit 21) */ + #define R_MIPI_DSI_RXIER_CRCERR_Msk (0x200000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_IBERR_Pos (22UL) /*!< IBERR (Bit 22) */ + #define R_MIPI_DSI_RXIER_IBERR_Msk (0x400000UL) /*!< IBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Pos (23UL) /*!< RXOVFERR (Bit 23) */ + #define R_MIPI_DSI_RXIER_RXOVFERR_Msk (0x800000UL) /*!< RXOVFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Pos (24UL) /*!< PRTOERR (Bit 24) */ + #define R_MIPI_DSI_RXIER_PRTOERR_Msk (0x1000000UL) /*!< PRTOERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_NORESERR_Pos (25UL) /*!< NORESERR (Bit 25) */ + #define R_MIPI_DSI_RXIER_NORESERR_Msk (0x2000000UL) /*!< NORESERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Pos (26UL) /*!< RSIZEERR (Bit 26) */ + #define R_MIPI_DSI_RXIER_RSIZEERR_Msk (0x4000000UL) /*!< RSIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Pos (28UL) /*!< ECCERRS (Bit 28) */ + #define R_MIPI_DSI_RXIER_ECCERRS_Msk (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXIER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXIER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ==================================================== PRESPTOBTASETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Pos (0UL) /*!< PRTBTA (Bit 0) */ + #define R_MIPI_DSI_PRESPTOBTASETR_PRTBTA_Msk (0xffffffffUL) /*!< PRTBTA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PRESPTOLPSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Pos (0UL) /*!< LPWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPWTO_Msk (0xffffUL) /*!< LPWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Pos (16UL) /*!< LPRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOLPSETR_LPRTO_Msk (0xffff0000UL) /*!< LPRTO (Bitfield-Mask: 0xffff) */ +/* ===================================================== PRESPTOHSSETR ===================================================== */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Pos (0UL) /*!< HSWTO (Bit 0) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSWTO_Msk (0xffffUL) /*!< HSWTO (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Pos (16UL) /*!< HSRTO (Bit 16) */ + #define R_MIPI_DSI_PRESPTOHSSETR_HSRTO_Msk (0xffff0000UL) /*!< HSRTO (Bitfield-Mask: 0xffff) */ +/* ======================================================= AKEPLATIR ======================================================= */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Pos (0UL) /*!< EREP (Bit 0) */ + #define R_MIPI_DSI_AKEPLATIR_EREP_Msk (0xffffUL) /*!< EREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Pos (16UL) /*!< VC (Bit 16) */ + #define R_MIPI_DSI_AKEPLATIR_VC_Msk (0xf0000UL) /*!< VC (Bitfield-Mask: 0x0f) */ +/* ======================================================= AKEPACMSR ======================================================= */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPACMSR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPACMSR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== AKEPSCR ======================================================== */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Pos (0UL) /*!< AEREP (Bit 0) */ + #define R_MIPI_DSI_AKEPSCR_AEREP_Msk (0xffffUL) /*!< AEREP (Bitfield-Mask: 0xffff) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Pos (16UL) /*!< AVC (Bit 16) */ + #define R_MIPI_DSI_AKEPSCR_AVC_Msk (0xf0000UL) /*!< AVC (Bitfield-Mask: 0x0f) */ +/* ======================================================== RXRSSR ========================================================= */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSSCR ======================================================== */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Pos (0UL) /*!< SLT0VLD (Bit 0) */ + #define R_MIPI_DSI_RXRSSCR_SLT0VLD_Msk (0x1UL) /*!< SLT0VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Pos (1UL) /*!< SLT1VLD (Bit 1) */ + #define R_MIPI_DSI_RXRSSCR_SLT1VLD_Msk (0x2UL) /*!< SLT1VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Pos (2UL) /*!< SLT2VLD (Bit 2) */ + #define R_MIPI_DSI_RXRSSCR_SLT2VLD_Msk (0x4UL) /*!< SLT2VLD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Pos (3UL) /*!< SLT3VLD (Bit 3) */ + #define R_MIPI_DSI_RXRSSCR_SLT3VLD_Msk (0x8UL) /*!< SLT3VLD (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRINFOOWSR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ===================================================== RXRINFOOWSCR ====================================================== */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Pos (0UL) /*!< SL0OW (Bit 0) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Msk (0x1UL) /*!< SL0OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Pos (1UL) /*!< SL1OW (Bit 1) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL1OW_Msk (0x2UL) /*!< SL1OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Pos (2UL) /*!< SL2OW (Bit 2) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL2OW_Msk (0x4UL) /*!< SL2OW (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Pos (3UL) /*!< SL3OW (Bit 3) */ + #define R_MIPI_DSI_RXRINFOOWSCR_SL3OW_Msk (0x8UL) /*!< SL3OW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS0R ======================================================== */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS0R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS0R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS0R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS0R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS0R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS0R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS0R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS0R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS0R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS0R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS1R ======================================================== */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS1R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS1R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS1R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS1R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS1R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS1R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS1R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS1R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS1R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS1R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS2R ======================================================== */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS2R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS2R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS2R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS2R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS2R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS2R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS2R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS2R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS2R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS2R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXRSS3R ======================================================== */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_RXRSS3R_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_RXRSS3R_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_RXRSS3R_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Pos (25UL) /*!< RXSUC (Bit 25) */ + #define R_MIPI_DSI_RXRSS3R_RXSUC_Msk (0x2000000UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_RXRSS3R_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_RXRSS3R_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_RXRSS3R_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Pos (29UL) /*!< RXCERR (Bit 29) */ + #define R_MIPI_DSI_RXRSS3R_RXCERR_Msk (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_RXRSS3R_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Pos (31UL) /*!< INFOOW (Bit 31) */ + #define R_MIPI_DSI_RXRSS3R_INFOOW_Msk (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS0R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS1R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS2R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS3R_L ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS0R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS1R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS2R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ====================================================== RXRSS3R_LH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ======================================================= RXRSS0R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS0R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS0R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS0R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS0R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS0R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS0R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS0R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS1R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS1R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS1R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS1R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS1R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS1R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS1R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS1R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS2R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS2R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS2R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS2R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS2R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS2R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS2R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS2R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================= RXRSS3R_H ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_RXRSS3R_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Pos (9UL) /*!< RXSUC (Bit 9) */ + #define R_MIPI_DSI_RXRSS3R_H_RXSUC_Msk (0x200UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Pos (10UL) /*!< RXFERR (Bit 10) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFERR_Msk (0x400UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Pos (11UL) /*!< RXFAIL (Bit 11) */ + #define R_MIPI_DSI_RXRSS3R_H_RXFAIL_Msk (0x800UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Pos (12UL) /*!< RXPFAIL (Bit 12) */ + #define R_MIPI_DSI_RXRSS3R_H_RXPFAIL_Msk (0x1000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Pos (13UL) /*!< RXCERR (Bit 13) */ + #define R_MIPI_DSI_RXRSS3R_H_RXCERR_Msk (0x2000UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Pos (14UL) /*!< RXAKE (Bit 14) */ + #define R_MIPI_DSI_RXRSS3R_H_RXAKE_Msk (0x4000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Pos (15UL) /*!< INFOOW (Bit 15) */ + #define R_MIPI_DSI_RXRSS3R_H_INFOOW_Msk (0x8000UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS0R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS1R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS2R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS3R_HL ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ====================================================== RXRSS0R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS0R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS0R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS0R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS1R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS1R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS1R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS1R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS2R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS2R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS2R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS2R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ====================================================== RXRSS3R_HH ======================================================= */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_RXRSS3R_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Pos (1UL) /*!< RXSUC (Bit 1) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXSUC_Msk (0x2UL) /*!< RXSUC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Pos (2UL) /*!< RXFERR (Bit 2) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFERR_Msk (0x4UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Pos (3UL) /*!< RXFAIL (Bit 3) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXFAIL_Msk (0x8UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Pos (4UL) /*!< RXPFAIL (Bit 4) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXPFAIL_Msk (0x10UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Pos (5UL) /*!< RXCERR (Bit 5) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXCERR_Msk (0x20UL) /*!< RXCERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Pos (6UL) /*!< RXAKE (Bit 6) */ + #define R_MIPI_DSI_RXRSS3R_HH_RXAKE_Msk (0x40UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Pos (7UL) /*!< INFOOW (Bit 7) */ + #define R_MIPI_DSI_RXRSS3R_HH_INFOOW_Msk (0x80UL) /*!< INFOOW (Bitfield-Mask: 0x01) */ +/* ======================================================== RXPPD0R ======================================================== */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_RXPPD0R_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_RXPPD0R_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Pos (16UL) /*!< DATA2 (Bit 16) */ + #define R_MIPI_DSI_RXPPD0R_DATA2_Msk (0xff0000UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Pos (24UL) /*!< DATA3 (Bit 24) */ + #define R_MIPI_DSI_RXPPD0R_DATA3_Msk (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD1R ======================================================== */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Pos (0UL) /*!< DATA4 (Bit 0) */ + #define R_MIPI_DSI_RXPPD1R_DATA4_Msk (0xffUL) /*!< DATA4 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Pos (8UL) /*!< DATA5 (Bit 8) */ + #define R_MIPI_DSI_RXPPD1R_DATA5_Msk (0xff00UL) /*!< DATA5 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Pos (16UL) /*!< DATA6 (Bit 16) */ + #define R_MIPI_DSI_RXPPD1R_DATA6_Msk (0xff0000UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Pos (24UL) /*!< DATA7 (Bit 24) */ + #define R_MIPI_DSI_RXPPD1R_DATA7_Msk (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD2R ======================================================== */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Pos (0UL) /*!< DATA8 (Bit 0) */ + #define R_MIPI_DSI_RXPPD2R_DATA8_Msk (0xffUL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Pos (8UL) /*!< DATA9 (Bit 8) */ + #define R_MIPI_DSI_RXPPD2R_DATA9_Msk (0xff00UL) /*!< DATA9 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Pos (16UL) /*!< DATA10 (Bit 16) */ + #define R_MIPI_DSI_RXPPD2R_DATA10_Msk (0xff0000UL) /*!< DATA10 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Pos (24UL) /*!< DATA11 (Bit 24) */ + #define R_MIPI_DSI_RXPPD2R_DATA11_Msk (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff) */ +/* ======================================================== RXPPD3R ======================================================== */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Pos (0UL) /*!< DATA12 (Bit 0) */ + #define R_MIPI_DSI_RXPPD3R_DATA12_Msk (0xffUL) /*!< DATA12 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Pos (8UL) /*!< DATA13 (Bit 8) */ + #define R_MIPI_DSI_RXPPD3R_DATA13_Msk (0xff00UL) /*!< DATA13 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Pos (16UL) /*!< DATA14 (Bit 16) */ + #define R_MIPI_DSI_RXPPD3R_DATA14_Msk (0xff0000UL) /*!< DATA14 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Pos (24UL) /*!< DATA15 (Bit 24) */ + #define R_MIPI_DSI_RXPPD3R_DATA15_Msk (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff) */ +/* ====================================================== HSTXTOSETR ======================================================= */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_HSTXTOSETR_HTXTO_Msk (0xffffffffUL) /*!< HTXTO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== LRXHTOSETR ======================================================= */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Pos (0UL) /*!< LRXHTO (Bit 0) */ + #define R_MIPI_DSI_LRXHTOSETR_LRXHTO_Msk (0xffffffffUL) /*!< LRXHTO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TATOSETR ======================================================== */ + #define R_MIPI_DSI_TATOSETR_TATO_Pos (0UL) /*!< TATO (Bit 0) */ + #define R_MIPI_DSI_TATOSETR_TATO_Msk (0xffffffffUL) /*!< TATO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FERRSR ========================================================= */ + #define R_MIPI_DSI_FERRSR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Pos (27UL) /*!< CLP0S (Bit 27) */ + #define R_MIPI_DSI_FERRSR_CLP0S_Msk (0x8000000UL) /*!< CLP0S (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Pos (28UL) /*!< CLP1S (Bit 28) */ + #define R_MIPI_DSI_FERRSR_CLP1S_Msk (0x10000000UL) /*!< CLP1S (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRSCR ======================================================== */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRSCR_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRSCR_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRSCR_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRSCR_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRSCR_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRSCR_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRSCR_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRSCR_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FERRIER ======================================================== */ + #define R_MIPI_DSI_FERRIER_HTXTO_Pos (0UL) /*!< HTXTO (Bit 0) */ + #define R_MIPI_DSI_FERRIER_HTXTO_Msk (0x1UL) /*!< HTXTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Pos (1UL) /*!< LRXHTO (Bit 1) */ + #define R_MIPI_DSI_FERRIER_LRXHTO_Msk (0x2UL) /*!< LRXHTO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_TATO_Pos (2UL) /*!< TATO (Bit 2) */ + #define R_MIPI_DSI_FERRIER_TATO_Msk (0x4UL) /*!< TATO (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Pos (16UL) /*!< ESCENT (Bit 16) */ + #define R_MIPI_DSI_FERRIER_ESCENT_Msk (0x10000UL) /*!< ESCENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Pos (17UL) /*!< SYNCESC (Bit 17) */ + #define R_MIPI_DSI_FERRIER_SYNCESC_Msk (0x20000UL) /*!< SYNCESC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CTRL_Pos (18UL) /*!< CTRL (Bit 18) */ + #define R_MIPI_DSI_FERRIER_CTRL_Msk (0x40000UL) /*!< CTRL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP0_Pos (19UL) /*!< CLP0 (Bit 19) */ + #define R_MIPI_DSI_FERRIER_CLP0_Msk (0x80000UL) /*!< CLP0 (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_FERRIER_CLP1_Pos (20UL) /*!< CLP1 (Bit 20) */ + #define R_MIPI_DSI_FERRIER_CLP1_Msk (0x100000UL) /*!< CLP1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CLSTPTSETR ======================================================= */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Pos (2UL) /*!< CLKSTPT (Bit 2) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Msk (0xffcUL) /*!< CLKSTPT (Bitfield-Mask: 0x3ff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Pos (16UL) /*!< CLKBFHT (Bit 16) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Msk (0xff0000UL) /*!< CLKBFHT (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Pos (24UL) /*!< CLKKPT (Bit 24) */ + #define R_MIPI_DSI_CLSTPTSETR_CLKKPT_Msk (0xff000000UL) /*!< CLKKPT (Bitfield-Mask: 0xff) */ +/* ====================================================== LPTRNSTSETR ====================================================== */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Pos (0UL) /*!< GOLPBKT (Bit 0) */ + #define R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Msk (0x3ffUL) /*!< GOLPBKT (Bitfield-Mask: 0x3ff) */ +/* ========================================================= PLSR ========================================================== */ + #define R_MIPI_DSI_PLSR_CLUAN_Pos (0UL) /*!< CLUAN (Bit 0) */ + #define R_MIPI_DSI_PLSR_CLUAN_Msk (0x1UL) /*!< CLUAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLSTP_Pos (1UL) /*!< CLSTP (Bit 1) */ + #define R_MIPI_DSI_PLSR_CLSTP_Msk (0x2UL) /*!< CLSTP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Pos (2UL) /*!< DL0RLE (Bit 2) */ + #define R_MIPI_DSI_PLSR_DL0RLE_Msk (0x4UL) /*!< DL0RLE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Pos (3UL) /*!< DL0RUE (Bit 3) */ + #define R_MIPI_DSI_PLSR_DL0RUE_Msk (0x8UL) /*!< DL0RUE (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Pos (4UL) /*!< DL0UAN (Bit 4) */ + #define R_MIPI_DSI_PLSR_DL0UAN_Msk (0x10UL) /*!< DL0UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Pos (5UL) /*!< DL1UAN (Bit 5) */ + #define R_MIPI_DSI_PLSR_DL1UAN_Msk (0x20UL) /*!< DL1UAN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0STP_Pos (8UL) /*!< DL0STP (Bit 8) */ + #define R_MIPI_DSI_PLSR_DL0STP_Msk (0x100UL) /*!< DL0STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL1STP_Pos (9UL) /*!< DL1STP (Bit 9) */ + #define R_MIPI_DSI_PLSR_DL1STP_Msk (0x200UL) /*!< DL1STP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Pos (15UL) /*!< DL0DIR (Bit 15) */ + #define R_MIPI_DSI_PLSR_DL0DIR_Msk (0x8000UL) /*!< DL0DIR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLSCR ========================================================= */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLSCR_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLSCR_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLSCR_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLSCR_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLSCR_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLSCR_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLSCR_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLSCR_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ========================================================= PLIER ========================================================= */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Pos (12UL) /*!< DL0RX2TX (Bit 12) */ + #define R_MIPI_DSI_PLIER_DL0RX2TX_Msk (0x1000UL) /*!< DL0RX2TX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Pos (13UL) /*!< DL0TX2RX (Bit 13) */ + #define R_MIPI_DSI_PLIER_DL0TX2RX_Msk (0x2000UL) /*!< DL0TX2RX (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Pos (24UL) /*!< CLULPENT (Bit 24) */ + #define R_MIPI_DSI_PLIER_CLULPENT_Msk (0x1000000UL) /*!< CLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Pos (25UL) /*!< CLULPEXT (Bit 25) */ + #define R_MIPI_DSI_PLIER_CLULPEXT_Msk (0x2000000UL) /*!< CLULPEXT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Pos (26UL) /*!< CLLP2HS (Bit 26) */ + #define R_MIPI_DSI_PLIER_CLLP2HS_Msk (0x4000000UL) /*!< CLLP2HS (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Pos (27UL) /*!< CLHS2LP (Bit 27) */ + #define R_MIPI_DSI_PLIER_CLHS2LP_Msk (0x8000000UL) /*!< CLHS2LP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Pos (28UL) /*!< DLULPENT (Bit 28) */ + #define R_MIPI_DSI_PLIER_DLULPENT_Msk (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Pos (29UL) /*!< DLULPEXT (Bit 29) */ + #define R_MIPI_DSI_PLIER_DLULPEXT_Msk (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET0R ======================================================== */ + #define R_MIPI_DSI_VMSET0R_VSTART_Pos (0UL) /*!< VSTART (Bit 0) */ + #define R_MIPI_DSI_VMSET0R_VSTART_Msk (0x1UL) /*!< VSTART (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Pos (1UL) /*!< VSTOP (Bit 1) */ + #define R_MIPI_DSI_VMSET0R_VSTOP_Msk (0x2UL) /*!< VSTOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Pos (8UL) /*!< HSANOLP (Bit 8) */ + #define R_MIPI_DSI_VMSET0R_HSANOLP_Msk (0x100UL) /*!< HSANOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Pos (9UL) /*!< HBPNOLP (Bit 9) */ + #define R_MIPI_DSI_VMSET0R_HBPNOLP_Msk (0x200UL) /*!< HBPNOLP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Pos (10UL) /*!< HFPNOLP (Bit 10) */ + #define R_MIPI_DSI_VMSET0R_HFPNOLP_Msk (0x400UL) /*!< HFPNOLP (Bitfield-Mask: 0x01) */ +/* ======================================================== VMSET1R ======================================================== */ + #define R_MIPI_DSI_VMSET1R_DLY_Pos (2UL) /*!< DLY (Bit 2) */ + #define R_MIPI_DSI_VMSET1R_DLY_Msk (0x3ffcUL) /*!< DLY (Bitfield-Mask: 0xfff) */ +/* ========================================================= VMSR ========================================================== */ + #define R_MIPI_DSI_VMSR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_VMSR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMSCR ========================================================= */ + #define R_MIPI_DSI_VMSCR_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMSCR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMSCR_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMSCR_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMSCR_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMSCR_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMSCR_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ========================================================= VMIER ========================================================= */ + #define R_MIPI_DSI_VMIER_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_VMIER_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_STOP_Pos (1UL) /*!< STOP (Bit 1) */ + #define R_MIPI_DSI_VMIER_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VIRDY_Pos (3UL) /*!< VIRDY (Bit 3) */ + #define R_MIPI_DSI_VMIER_VIRDY_Msk (0x8UL) /*!< VIRDY (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_TIMERR_Pos (20UL) /*!< TIMERR (Bit 20) */ + #define R_MIPI_DSI_VMIER_TIMERR_Msk (0x100000UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Pos (22UL) /*!< VBUFUDF (Bit 22) */ + #define R_MIPI_DSI_VMIER_VBUFUDF_Msk (0x400000UL) /*!< VBUFUDF (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Pos (23UL) /*!< VBUFOVF (Bit 23) */ + #define R_MIPI_DSI_VMIER_VBUFOVF_Msk (0x800000UL) /*!< VBUFOVF (Bitfield-Mask: 0x01) */ +/* ======================================================= VMPPSETR ======================================================== */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Pos (15UL) /*!< TXESYNC (Bit 15) */ + #define R_MIPI_DSI_VMPPSETR_TXESYNC_Msk (0x8000UL) /*!< TXESYNC (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMPPSETR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_VMPPSETR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_VMPPSETR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_VMPPSETR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ======================================================= VMVSSETR ======================================================== */ + #define R_MIPI_DSI_VMVSSETR_VSA_Pos (0UL) /*!< VSA (Bit 0) */ + #define R_MIPI_DSI_VMVSSETR_VSA_Msk (0xfffUL) /*!< VSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Pos (15UL) /*!< VSPOL (Bit 15) */ + #define R_MIPI_DSI_VMVSSETR_VSPOL_Msk (0x8000UL) /*!< VSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Pos (16UL) /*!< VACT (Bit 16) */ + #define R_MIPI_DSI_VMVSSETR_VACT_Msk (0x7fff0000UL) /*!< VACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMVPSETR ======================================================== */ + #define R_MIPI_DSI_VMVPSETR_VBP_Pos (0UL) /*!< VBP (Bit 0) */ + #define R_MIPI_DSI_VMVPSETR_VBP_Msk (0x1fffUL) /*!< VBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Pos (16UL) /*!< VFP (Bit 16) */ + #define R_MIPI_DSI_VMVPSETR_VFP_Msk (0x1fff0000UL) /*!< VFP (Bitfield-Mask: 0x1fff) */ +/* ======================================================= VMHSSETR ======================================================== */ + #define R_MIPI_DSI_VMHSSETR_HSA_Pos (0UL) /*!< HSA (Bit 0) */ + #define R_MIPI_DSI_VMHSSETR_HSA_Msk (0xfffUL) /*!< HSA (Bitfield-Mask: 0xfff) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Pos (15UL) /*!< HSPOL (Bit 15) */ + #define R_MIPI_DSI_VMHSSETR_HSPOL_Msk (0x8000UL) /*!< HSPOL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Pos (16UL) /*!< HACT (Bit 16) */ + #define R_MIPI_DSI_VMHSSETR_HACT_Msk (0x7fff0000UL) /*!< HACT (Bitfield-Mask: 0x7fff) */ +/* ======================================================= VMHPSETR ======================================================== */ + #define R_MIPI_DSI_VMHPSETR_HBP_Pos (0UL) /*!< HBP (Bit 0) */ + #define R_MIPI_DSI_VMHPSETR_HBP_Msk (0x1fffUL) /*!< HBP (Bitfield-Mask: 0x1fff) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Pos (16UL) /*!< HFP (Bit 16) */ + #define R_MIPI_DSI_VMHPSETR_HFP_Msk (0x1fff0000UL) /*!< HFP (Bitfield-Mask: 0x1fff) */ +/* ====================================================== SQCH0SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH0SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH0SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH0SR ======================================================== */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH0SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0SCR ======================================================== */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH0IER ======================================================== */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH0IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH0IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH0IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH0IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH0IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH0IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH0IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH0IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH0IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH0IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH1SET0R ======================================================= */ + #define R_MIPI_DSI_SQCH1SET0R_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_MIPI_DSI_SQCH1SET0R_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== SQCH1SR ======================================================== */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Pos (2UL) /*!< RUNNING (Bit 2) */ + #define R_MIPI_DSI_SQCH1SR_RUNNING_Msk (0x4UL) /*!< RUNNING (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1SCR ======================================================== */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1SCR_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1SCR_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1SCR_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1SCR_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1SCR_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1SCR_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1SCR_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1SCR_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1SCR_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1SCR_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ======================================================= SQCH1IER ======================================================== */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Pos (4UL) /*!< AACTFIN (Bit 4) */ + #define R_MIPI_DSI_SQCH1IER_AACTFIN_Msk (0x10UL) /*!< AACTFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Pos (8UL) /*!< ADESFIN (Bit 8) */ + #define R_MIPI_DSI_SQCH1IER_ADESFIN_Msk (0x100UL) /*!< ADESFIN (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Pos (16UL) /*!< DABORT (Bit 16) */ + #define R_MIPI_DSI_SQCH1IER_DABORT_Msk (0x10000UL) /*!< DABORT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Pos (19UL) /*!< SIZEERR (Bit 19) */ + #define R_MIPI_DSI_SQCH1IER_SIZEERR_Msk (0x80000UL) /*!< SIZEERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Pos (24UL) /*!< TXIBERR (Bit 24) */ + #define R_MIPI_DSI_SQCH1IER_TXIBERR_Msk (0x1000000UL) /*!< TXIBERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Pos (26UL) /*!< RXFERR (Bit 26) */ + #define R_MIPI_DSI_SQCH1IER_RXFERR_Msk (0x4000000UL) /*!< RXFERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Pos (27UL) /*!< RXFAIL (Bit 27) */ + #define R_MIPI_DSI_SQCH1IER_RXFAIL_Msk (0x8000000UL) /*!< RXFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Pos (28UL) /*!< RXPFAIL (Bit 28) */ + #define R_MIPI_DSI_SQCH1IER_RXPFAIL_Msk (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Pos (29UL) /*!< RXCORERR (Bit 29) */ + #define R_MIPI_DSI_SQCH1IER_RXCORERR_Msk (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Pos (30UL) /*!< RXAKE (Bit 30) */ + #define R_MIPI_DSI_SQCH1IER_RXAKE_Msk (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01) */ +/* ====================================================== SQCH0DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH0DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH0DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH0DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH0DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH0DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH0DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH0DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH0DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH0DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH0DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH0DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH0DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH0DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH0DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH0DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH0DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH0DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH0DSC0DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC1DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC2DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC3DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC4DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC5DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC6DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH0DSC7DR_H ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_H_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH0DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH0DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH0DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC0AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC0AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC0AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC0AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC1AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC1AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC1AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC1AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC2AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC2AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC2AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC2AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC3AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC3AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC3AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC3AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC4AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC4AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC4AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC4AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC5AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC5AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC5AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC5AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC6AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC6AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC6AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC6AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7AR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Pos (16UL) /*!< DT (Bit 16) */ + #define R_MIPI_DSI_SQCH1DSC7AR_DT_Msk (0x3f0000UL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Pos (22UL) /*!< VC (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7AR_VC_Msk (0xc00000UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Pos (24UL) /*!< FMT (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7AR_FMT_Msk (0x1000000UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Pos (25UL) /*!< SPD (Bit 25) */ + #define R_MIPI_DSI_SQCH1DSC7AR_SPD_Msk (0x2000000UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Pos (26UL) /*!< BTA (Bit 26) */ + #define R_MIPI_DSI_SQCH1DSC7AR_BTA_Msk (0xc000000UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Pos (28UL) /*!< NXACT (Bit 28) */ + #define R_MIPI_DSI_SQCH1DSC7AR_NXACT_Msk (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC0AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7AR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Pos (8UL) /*!< DATA1 (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_L_DATA1_Msk (0xff00UL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LL_DATA0_Msk (0xffUL) /*!< DATA0 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7AR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_LH_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC0AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC1AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC1AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC2AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC2AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC3AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC3AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC4AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC4AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC5AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC5AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC6AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC6AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ===================================================== SQCH1DSC7AR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Pos (8UL) /*!< FMT (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_FMT_Msk (0x100UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Pos (9UL) /*!< SPD (Bit 9) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_SPD_Msk (0x200UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Pos (10UL) /*!< BTA (Bit 10) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_BTA_Msk (0xc00UL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Pos (12UL) /*!< NXACT (Bit 12) */ + #define R_MIPI_DSI_SQCH1DSC7AR_H_NXACT_Msk (0x3000UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Pos (0UL) /*!< DT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_DT_Msk (0x3fUL) /*!< DT (Bitfield-Mask: 0x3f) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Pos (6UL) /*!< VC (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HL_VC_Msk (0xc0UL) /*!< VC (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC0AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC0AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC1AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC1AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC2AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC2AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC3AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC3AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC4AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC4AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC5AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC5AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC6AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC6AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ==================================================== SQCH1DSC7AR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Pos (0UL) /*!< FMT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_FMT_Msk (0x1UL) /*!< FMT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Pos (1UL) /*!< SPD (Bit 1) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_SPD_Msk (0x2UL) /*!< SPD (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Pos (2UL) /*!< BTA (Bit 2) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_BTA_Msk (0xcUL) /*!< BTA (Bitfield-Mask: 0x03) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Pos (4UL) /*!< NXACT (Bit 4) */ + #define R_MIPI_DSI_SQCH1DSC7AR_HH_NXACT_Msk (0x30UL) /*!< NXACT (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC1BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC2BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC3BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC4BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC5BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC6BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC7BR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Pos (24UL) /*!< DTSEL (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7BR_DTSEL_Msk (0x3000000UL) /*!< DTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== SQCH1DSC0CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC0CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC0CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC1CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC1CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC1CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC2CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC2CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC2CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC3CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC3CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC3CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC4CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC4CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC4CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC5CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC5CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC5CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC6CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC6CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC6CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC7CR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Pos (22UL) /*!< AUXOP (Bit 22) */ + #define R_MIPI_DSI_SQCH1DSC7CR_AUXOP_Msk (0x400000UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Pos (24UL) /*!< ACTCODE (Bit 24) */ + #define R_MIPI_DSI_SQCH1DSC7CR_ACTCODE_Msk (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC0CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC1CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC2CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC3CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC4CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC5CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC6CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC7CR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_L_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Pos (0UL) /*!< FINACT (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_LL_FINACT_Msk (0x1UL) /*!< FINACT (Bitfield-Mask: 0x01) */ +/* ===================================================== SQCH1DSC0CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC0CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC1CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC1CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC2CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC2CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC3CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC3CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC4CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC4CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC5CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC5CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC6CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC6CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ===================================================== SQCH1DSC7CR_H ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Pos (8UL) /*!< ACTCODE (Bit 8) */ + #define R_MIPI_DSI_SQCH1DSC7CR_H_ACTCODE_Msk (0xff00UL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC1CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC2CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC3CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC4CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC5CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC6CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC7CR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Pos (6UL) /*!< AUXOP (Bit 6) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HL_AUXOP_Msk (0x40UL) /*!< AUXOP (Bitfield-Mask: 0x01) */ +/* ==================================================== SQCH1DSC0CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7CR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Pos (0UL) /*!< ACTCODE (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7CR_HH_ACTCODE_Msk (0xffUL) /*!< ACTCODE (Bitfield-Mask: 0xff) */ +/* ====================================================== SQCH1DSC0DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC1DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC2DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC3DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC4DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC5DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC6DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== SQCH1DSC7DR ====================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LADDR_Msk (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SQCH1DSC0DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC1DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC2DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC3DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC4DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC5DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC6DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== SQCH1DSC7DR_L ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_L_LADDR_Msk (0xffffUL) /*!< LADDR (Bitfield-Mask: 0xffff) */ +/* ==================================================== SQCH1DSC0DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_LH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_LH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HL ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HL_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC0DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC0DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC1DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC1DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC2DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC2DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC3DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC3DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC4DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC4DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC5DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC5DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC6DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC6DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ +/* ==================================================== SQCH1DSC7DR_HH ===================================================== */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Pos (0UL) /*!< LADDR (Bit 0) */ + #define R_MIPI_DSI_SQCH1DSC7DR_HH_LADDR_Msk (0xffUL) /*!< LADDR (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MRMS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MRCPFB ========================================================= */ + #define R_MRMS_MRCPFB_MPFBEN_Pos (0UL) /*!< MPFBEN (Bit 0) */ + #define R_MRMS_MRCPFB_MPFBEN_Msk (0x1UL) /*!< MPFBEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCFREQ ======================================================== */ + #define R_MRMS_MRCFREQ_MRCMHZ_Pos (0UL) /*!< MRCMHZ (Bit 0) */ + #define R_MRMS_MRCFREQ_MRCMHZ_Msk (0x3ffUL) /*!< MRCMHZ (Bitfield-Mask: 0x3ff) */ + #define R_MRMS_MRCFREQ_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MRMS_MRCFREQ_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MREFREQ ======================================================== */ + #define R_MRMS_MREFREQ_MREMHZ_Pos (0UL) /*!< MREMHZ (Bit 0) */ + #define R_MRMS_MREFREQ_MREMHZ_Msk (0xffUL) /*!< MREMHZ (Bitfield-Mask: 0xff) */ + #define R_MRMS_MREFREQ_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MRMS_MREFREQ_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCDECC ======================================================== */ + #define R_MRMS_MRCDECC_DECDISC_Pos (0UL) /*!< DECDISC (Bit 0) */ + #define R_MRMS_MRCDECC_DECDISC_Msk (0x1UL) /*!< DECDISC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCDECC_ECCSELC_Pos (1UL) /*!< ECCSELC (Bit 1) */ + #define R_MRMS_MRCDECC_ECCSELC_Msk (0x2UL) /*!< ECCSELC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCDECC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCDECC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCRAEINT ======================================================= */ + #define R_MRMS_MRCRAEINT_INTENBDC_Pos (0UL) /*!< INTENBDC (Bit 0) */ + #define R_MRMS_MRCRAEINT_INTENBDC_Msk (0x1UL) /*!< INTENBDC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCRAEINT_INTENBTC_Pos (1UL) /*!< INTENBTC (Bit 1) */ + #define R_MRMS_MRCRAEINT_INTENBTC_Msk (0x2UL) /*!< INTENBTC (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCRAES ======================================================== */ + #define R_MRMS_MRCRAES_DECERRC_Pos (0UL) /*!< DECERRC (Bit 0) */ + #define R_MRMS_MRCRAES_DECERRC_Msk (0x1UL) /*!< DECERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCRAES_TEDERRC_Pos (1UL) /*!< TEDERRC (Bit 1) */ + #define R_MRMS_MRCRAES_TEDERRC_Msk (0x2UL) /*!< TEDERRC (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCRTEA ======================================================== */ + #define R_MRMS_MRCRTEA_MRCRTEA_Pos (5UL) /*!< MRCRTEA (Bit 5) */ + #define R_MRMS_MRCRTEA_MRCRTEA_Msk (0xffffffe0UL) /*!< MRCRTEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================== MRCRDEA ======================================================== */ + #define R_MRMS_MRCRDEA_MRCRDEA_Pos (5UL) /*!< MRCRDEA (Bit 5) */ + #define R_MRMS_MRCRDEA_MRCRDEA_Msk (0xffffffe0UL) /*!< MRCRDEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================= MRERAINT ======================================================== */ + #define R_MRMS_MRERAINT_INTENBDE_Pos (0UL) /*!< INTENBDE (Bit 0) */ + #define R_MRMS_MRERAINT_INTENBDE_Msk (0x1UL) /*!< INTENBDE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRERAINT_INTENBTE_Pos (1UL) /*!< INTENBTE (Bit 1) */ + #define R_MRMS_MRERAINT_INTENBTE_Msk (0x2UL) /*!< INTENBTE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRERAES ======================================================== */ + #define R_MRMS_MRERAES_DECERRE_Pos (0UL) /*!< DECERRE (Bit 0) */ + #define R_MRMS_MRERAES_DECERRE_Msk (0x1UL) /*!< DECERRE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRERAES_TEDERRE_Pos (1UL) /*!< TEDERRE (Bit 1) */ + #define R_MRMS_MRERAES_TEDERRE_Msk (0x2UL) /*!< TEDERRE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRERTEA ======================================================== */ + #define R_MRMS_MRERTEA_MRERTEA_Pos (4UL) /*!< MRERTEA (Bit 4) */ + #define R_MRMS_MRERTEA_MRERTEA_Msk (0xfffffff0UL) /*!< MRERTEA (Bitfield-Mask: 0xfffffff) */ +/* ======================================================== MRERDEA ======================================================== */ + #define R_MRMS_MRERDEA_MRERDEA_Pos (4UL) /*!< MRERDEA (Bit 4) */ + #define R_MRMS_MRERDEA_MRERDEA_Msk (0xfffffff0UL) /*!< MRERDEA (Bitfield-Mask: 0xfffffff) */ +/* ========================================================= MSAR ========================================================== */ + #define R_MRMS_MSAR_MREECCSA_Pos (0UL) /*!< MREECCSA (Bit 0) */ + #define R_MRMS_MSAR_MREECCSA_Msk (0x1UL) /*!< MREECCSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MREFREQSA_Pos (1UL) /*!< MREFREQSA (Bit 1) */ + #define R_MRMS_MSAR_MREFREQSA_Msk (0x2UL) /*!< MREFREQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCECCSA_Pos (2UL) /*!< MRCECCSA (Bit 2) */ + #define R_MRMS_MSAR_MRCECCSA_Msk (0x4UL) /*!< MRCECCSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCFREQSA_Pos (3UL) /*!< MRCFREQSA (Bit 3) */ + #define R_MRMS_MSAR_MRCFREQSA_Msk (0x8UL) /*!< MRCFREQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MPFBENSA_Pos (4UL) /*!< MPFBENSA (Bit 4) */ + #define R_MRMS_MSAR_MPFBENSA_Msk (0x10UL) /*!< MPFBENSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACICMISA_Pos (9UL) /*!< MACICMISA (Bit 9) */ + #define R_MRMS_MSAR_MACICMISA_Msk (0x200UL) /*!< MACICMISA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACICMRSA_Pos (10UL) /*!< MACICMRSA (Bit 10) */ + #define R_MRMS_MSAR_MACICMRSA_Msk (0x400UL) /*!< MACICMRSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MACITRSA_Pos (11UL) /*!< MACITRSA (Bit 11) */ + #define R_MRMS_MSAR_MACITRSA_Msk (0x800UL) /*!< MACITRSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCPSA_Pos (13UL) /*!< MRCPSA (Bit 13) */ + #define R_MRMS_MSAR_MRCPSA_Msk (0x2000UL) /*!< MRCPSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MREPSEQSA_Pos (14UL) /*!< MREPSEQSA (Bit 14) */ + #define R_MRMS_MSAR_MREPSEQSA_Msk (0x4000UL) /*!< MREPSEQSA (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSAR_MRCPSEQSA_Pos (15UL) /*!< MRCPSEQSA (Bit 15) */ + #define R_MRMS_MSAR_MRCPSEQSA_Msk (0x8000UL) /*!< MRCPSEQSA (Bitfield-Mask: 0x01) */ +/* ========================================================= MREZS ========================================================= */ + #define R_MRMS_MREZS_WHUKZF_Pos (0UL) /*!< WHUKZF (Bit 0) */ + #define R_MRMS_MREZS_WHUKZF_Msk (0x1UL) /*!< WHUKZF (Bitfield-Mask: 0x01) */ + #define R_MRMS_MREZS_WHUKEXE_Pos (1UL) /*!< WHUKEXE (Bit 1) */ + #define R_MRMS_MREZS_WHUKEXE_Msk (0x2UL) /*!< WHUKEXE (Bitfield-Mask: 0x01) */ +/* ========================================================= MREZC ========================================================= */ + #define R_MRMS_MREZC_WHUKZE_Pos (0UL) /*!< WHUKZE (Bit 0) */ + #define R_MRMS_MREZC_WHUKZE_Msk (0x7UL) /*!< WHUKZE (Bitfield-Mask: 0x07) */ + #define R_MRMS_MREZC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MREZC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MASTAT ========================================================= */ + #define R_MRMS_MASTAT_MREAE_Pos (3UL) /*!< MREAE (Bit 3) */ + #define R_MRMS_MASTAT_MREAE_Msk (0x8UL) /*!< MREAE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_MRMS_MASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ +/* ======================================================== MPAEINT ======================================================== */ + #define R_MRMS_MPAEINT_MREAEIE_Pos (3UL) /*!< MREAEIE (Bit 3) */ + #define R_MRMS_MPAEINT_MREAEIE_Msk (0x8UL) /*!< MREAEIE (Bitfield-Mask: 0x01) */ + #define R_MRMS_MPAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_MRMS_MPAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRDYIE ========================================================= */ + #define R_MRMS_MRDYIE_MRDYIE_Pos (0UL) /*!< MRDYIE (Bit 0) */ + #define R_MRMS_MRDYIE_MRDYIE_Msk (0x1UL) /*!< MRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSADDR ========================================================= */ + #define R_MRMS_MSADDR_MSADDR_Pos (0UL) /*!< MSADDR (Bit 0) */ + #define R_MRMS_MSADDR_MSADDR_Msk (0xffffffffUL) /*!< MSADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCNTSELR ======================================================== */ + #define R_MRMS_MCNTSELR_CNTSEL_Pos (0UL) /*!< CNTSEL (Bit 0) */ + #define R_MRMS_MCNTSELR_CNTSEL_Msk (0x7UL) /*!< CNTSEL (Bitfield-Mask: 0x07) */ +/* ======================================================= MCNTDTR0 ======================================================== */ + #define R_MRMS_MCNTDTR0_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_MRMS_MCNTDTR0_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCNTDTR1 ======================================================== */ + #define R_MRMS_MCNTDTR1_CNTRDAT_Pos (0UL) /*!< CNTRDAT (Bit 0) */ + #define R_MRMS_MCNTDTR1_CNTRDAT_Msk (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MCTRCNTR ======================================================== */ + #define R_MRMS_MCTRCNTR_TRTRG_Pos (0UL) /*!< TRTRG (Bit 0) */ + #define R_MRMS_MCTRCNTR_TRTRG_Msk (0x1UL) /*!< TRTRG (Bitfield-Mask: 0x01) */ + #define R_MRMS_MCTRCNTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MCTRCNTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MCTRLSR ======================================================== */ + #define R_MRMS_MCTRLSR_TRLIST_Pos (0UL) /*!< TRLIST (Bit 0) */ + #define R_MRMS_MCTRLSR_TRLIST_Msk (0x7UL) /*!< TRLIST (Bitfield-Mask: 0x07) */ +/* ======================================================= MCTRSTATR ======================================================= */ + #define R_MRMS_MCTRSTATR_TRBUSY_Pos (0UL) /*!< TRBUSY (Bit 0) */ + #define R_MRMS_MCTRSTATR_TRBUSY_Msk (0x1UL) /*!< TRBUSY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MCTRSTATR_TRMD_Pos (2UL) /*!< TRMD (Bit 2) */ + #define R_MRMS_MCTRSTATR_TRMD_Msk (0x4UL) /*!< TRMD (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTATR ========================================================= */ + #define R_MRMS_MSTATR_CFGSETERR_Pos (5UL) /*!< CFGSETERR (Bit 5) */ + #define R_MRMS_MSTATR_CFGSETERR_Msk (0x20UL) /*!< CFGSETERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_MRMS_MSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_MRMS_MSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_MRDY_Pos (15UL) /*!< MRDY (Bit 15) */ + #define R_MRMS_MSTATR_MRDY_Msk (0x8000UL) /*!< MRDY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_TZFERR_Pos (19UL) /*!< TZFERR (Bit 19) */ + #define R_MRMS_MSTATR_TZFERR_Msk (0x80000UL) /*!< TZFERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_MRMS_MSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_MRMS_MSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_MRMS_MSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ +/* ======================================================== MENTRYR ======================================================== */ + #define R_MRMS_MENTRYR_MENTRY_Pos (7UL) /*!< MENTRY (Bit 7) */ + #define R_MRMS_MENTRYR_MENTRY_Msk (0x80UL) /*!< MENTRY (Bitfield-Mask: 0x01) */ + #define R_MRMS_MENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MSUINITR ======================================================== */ + #define R_MRMS_MSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_MRMS_MSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MCMDR ========================================================= */ + #define R_MRMS_MCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_MRMS_MCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ + #define R_MRMS_MCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_MRMS_MCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ +/* ======================================================= MSUASMON ======================================================== */ + #define R_MRMS_MSUASMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_MRMS_MSUASMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_MRMS_MSUASMON_BTSIZE_Pos (29UL) /*!< BTSIZE (Bit 29) */ + #define R_MRMS_MSUASMON_BTSIZE_Msk (0x60000000UL) /*!< BTSIZE (Bitfield-Mask: 0x03) */ + #define R_MRMS_MSUASMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_MRMS_MSUASMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ +/* ======================================================== MSUACR ========================================================= */ + #define R_MRMS_MSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_MRMS_MSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_MRMS_MSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MRPSC ========================================================= */ + #define R_MRMS_MRPSC_MHSPEN_Pos (0UL) /*!< MHSPEN (Bit 0) */ + #define R_MRMS_MRPSC_MHSPEN_Msk (0x1UL) /*!< MHSPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCPC0 ========================================================= */ + #define R_MRMS_MRCPC0_MRCPNEN_Pos (0UL) /*!< MRCPNEN (Bit 0) */ + #define R_MRMS_MRCPC0_MRCPNEN_Msk (0x1UL) /*!< MRCPNEN (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPC0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCPC0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCPC1 ========================================================= */ + #define R_MRMS_MRCPC1_MRCPSEN_Pos (0UL) /*!< MRCPSEN (Bit 0) */ + #define R_MRMS_MRCPC1_MRCPSEN_Msk (0x1UL) /*!< MRCPSEN (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPC1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCPC1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCBPROT0 ======================================================= */ + #define R_MRMS_MRCBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_MRMS_MRCBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= MRCBPROT1 ======================================================= */ + #define R_MRMS_MRCBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_MRMS_MRCBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= MRCPS ========================================================= */ + #define R_MRMS_MRCPS_PRGERRC_Pos (0UL) /*!< PRGERRC (Bit 0) */ + #define R_MRMS_MRCPS_PRGERRC_Msk (0x1UL) /*!< PRGERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ECCERRC_Pos (1UL) /*!< ECCERRC (Bit 1) */ + #define R_MRMS_MRCPS_ECCERRC_Msk (0x2UL) /*!< ECCERRC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ABUFEMP_Pos (5UL) /*!< ABUFEMP (Bit 5) */ + #define R_MRMS_MRCPS_ABUFEMP_Msk (0x20UL) /*!< ABUFEMP (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_ABUFFULL_Pos (6UL) /*!< ABUFFULL (Bit 6) */ + #define R_MRMS_MRCPS_ABUFFULL_Msk (0x40UL) /*!< ABUFFULL (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCPS_PRGBSYC_Pos (7UL) /*!< PRGBSYC (Bit 7) */ + #define R_MRMS_MRCPS_PRGBSYC_Msk (0x80UL) /*!< PRGBSYC (Bitfield-Mask: 0x01) */ +/* ======================================================= MRCPAEINT ======================================================= */ + #define R_MRMS_MRCPAEINT_MRCAEIE_Pos (7UL) /*!< MRCAEIE (Bit 7) */ + #define R_MRMS_MRCPAEINT_MRCAEIE_Msk (0x80UL) /*!< MRCAEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCPEA ========================================================= */ + #define R_MRMS_MRCPEA_MCPEA_Pos (5UL) /*!< MCPEA (Bit 5) */ + #define R_MRMS_MRCPEA_MCPEA_Msk (0xffffffe0UL) /*!< MCPEA (Bitfield-Mask: 0x7ffffff) */ +/* ======================================================== MRCFLR ========================================================= */ + #define R_MRMS_MRCFLR_MRCFL_Pos (0UL) /*!< MRCFL (Bit 0) */ + #define R_MRMS_MRCFLR_MRCFL_Msk (0x1UL) /*!< MRCFL (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCFLR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCFLR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== MRCEECC ======================================================== */ + #define R_MRMS_MRCEECC_ECCBYPC_Pos (0UL) /*!< ECCBYPC (Bit 0) */ + #define R_MRMS_MRCEECC_ECCBYPC_Msk (0x1UL) /*!< ECCBYPC (Bitfield-Mask: 0x01) */ + #define R_MRMS_MRCEECC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MRMS_MRCEECC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_NPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_NPU_ID_arch_major_rev_Pos (28UL) /*!< arch_major_rev (Bit 28) */ + #define R_NPU_ID_arch_major_rev_Msk (0xf0000000UL) /*!< arch_major_rev (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_arch_minor_rev_Pos (20UL) /*!< arch_minor_rev (Bit 20) */ + #define R_NPU_ID_arch_minor_rev_Msk (0xff00000UL) /*!< arch_minor_rev (Bitfield-Mask: 0xff) */ + #define R_NPU_ID_arch_patch_rev_Pos (16UL) /*!< arch_patch_rev (Bit 16) */ + #define R_NPU_ID_arch_patch_rev_Msk (0xf0000UL) /*!< arch_patch_rev (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_product_major_Pos (12UL) /*!< product_major (Bit 12) */ + #define R_NPU_ID_product_major_Msk (0xf000UL) /*!< product_major (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_major_Pos (8UL) /*!< version_major (Bit 8) */ + #define R_NPU_ID_version_major_Msk (0xf00UL) /*!< version_major (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_minor_Pos (4UL) /*!< version_minor (Bit 4) */ + #define R_NPU_ID_version_minor_Msk (0xf0UL) /*!< version_minor (Bitfield-Mask: 0x0f) */ + #define R_NPU_ID_version_status_Pos (0UL) /*!< version_status (Bit 0) */ + #define R_NPU_ID_version_status_Msk (0xfUL) /*!< version_status (Bitfield-Mask: 0x0f) */ +/* ======================================================== STATUS ========================================================= */ + #define R_NPU_STATUS_irq_history_mask_Pos (16UL) /*!< irq_history_mask (Bit 16) */ + #define R_NPU_STATUS_irq_history_mask_Msk (0xffff0000UL) /*!< irq_history_mask (Bitfield-Mask: 0xffff) */ + #define R_NPU_STATUS_faulting_channel_Pos (12UL) /*!< faulting_channel (Bit 12) */ + #define R_NPU_STATUS_faulting_channel_Msk (0xf000UL) /*!< faulting_channel (Bitfield-Mask: 0x0f) */ + #define R_NPU_STATUS_faulting_interface_Pos (11UL) /*!< faulting_interface (Bit 11) */ + #define R_NPU_STATUS_faulting_interface_Msk (0x800UL) /*!< faulting_interface (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_ecc_fault_Pos (8UL) /*!< ecc_fault (Bit 8) */ + #define R_NPU_STATUS_ecc_fault_Msk (0x100UL) /*!< ecc_fault (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_pmu_irq_raised_Pos (6UL) /*!< pmu_irq_raised (Bit 6) */ + #define R_NPU_STATUS_pmu_irq_raised_Msk (0x40UL) /*!< pmu_irq_raised (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_cmd_end_reached_Pos (5UL) /*!< cmd_end_reached (Bit 5) */ + #define R_NPU_STATUS_cmd_end_reached_Msk (0x20UL) /*!< cmd_end_reached (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_cmd_parse_error_Pos (4UL) /*!< cmd_parse_error (Bit 4) */ + #define R_NPU_STATUS_cmd_parse_error_Msk (0x10UL) /*!< cmd_parse_error (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_reset_status_Pos (3UL) /*!< reset_status (Bit 3) */ + #define R_NPU_STATUS_reset_status_Msk (0x8UL) /*!< reset_status (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_bus_status_Pos (2UL) /*!< bus_status (Bit 2) */ + #define R_NPU_STATUS_bus_status_Msk (0x4UL) /*!< bus_status (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_irq_raised_Pos (1UL) /*!< irq_raised (Bit 1) */ + #define R_NPU_STATUS_irq_raised_Msk (0x2UL) /*!< irq_raised (Bitfield-Mask: 0x01) */ + #define R_NPU_STATUS_state_Pos (0UL) /*!< state (Bit 0) */ + #define R_NPU_STATUS_state_Msk (0x1UL) /*!< state (Bitfield-Mask: 0x01) */ +/* ========================================================== CMD ========================================================== */ + #define R_NPU_CMD_clear_irq_history_Pos (16UL) /*!< clear_irq_history (Bit 16) */ + #define R_NPU_CMD_clear_irq_history_Msk (0xffff0000UL) /*!< clear_irq_history (Bitfield-Mask: 0xffff) */ + #define R_NPU_CMD_power_q_enable_Pos (3UL) /*!< power_q_enable (Bit 3) */ + #define R_NPU_CMD_power_q_enable_Msk (0x8UL) /*!< power_q_enable (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_clock_q_enable_Pos (2UL) /*!< clock_q_enable (Bit 2) */ + #define R_NPU_CMD_clock_q_enable_Msk (0x4UL) /*!< clock_q_enable (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_clear_irq_Pos (1UL) /*!< clear_irq (Bit 1) */ + #define R_NPU_CMD_clear_irq_Msk (0x2UL) /*!< clear_irq (Bitfield-Mask: 0x01) */ + #define R_NPU_CMD_transition_to_running_state_Pos (0UL) /*!< transition_to_running_state (Bit 0) */ + #define R_NPU_CMD_transition_to_running_state_Msk (0x1UL) /*!< transition_to_running_state (Bitfield-Mask: 0x01) */ +/* ========================================================= RESET ========================================================= */ + #define R_NPU_RESET_pending_CSL_Pos (1UL) /*!< pending_CSL (Bit 1) */ + #define R_NPU_RESET_pending_CSL_Msk (0x2UL) /*!< pending_CSL (Bitfield-Mask: 0x01) */ + #define R_NPU_RESET_pending_CPL_Pos (0UL) /*!< pending_CPL (Bit 0) */ + #define R_NPU_RESET_pending_CPL_Msk (0x1UL) /*!< pending_CPL (Bitfield-Mask: 0x01) */ +/* ======================================================== QBASE0 ========================================================= */ + #define R_NPU_QBASE0_QBASE0_Pos (0UL) /*!< QBASE0 (Bit 0) */ + #define R_NPU_QBASE0_QBASE0_Msk (0xffffffffUL) /*!< QBASE0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== QBASE1 ========================================================= */ + #define R_NPU_QBASE1_QBASE1_Pos (0UL) /*!< QBASE1 (Bit 0) */ + #define R_NPU_QBASE1_QBASE1_Msk (0xffffffffUL) /*!< QBASE1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= QREAD ========================================================= */ + #define R_NPU_QREAD_QREAD_Pos (0UL) /*!< QREAD (Bit 0) */ + #define R_NPU_QREAD_QREAD_Msk (0xffffffffUL) /*!< QREAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== QCONFIG ======================================================== */ + #define R_NPU_QCONFIG_QCONFIG_Pos (0UL) /*!< QCONFIG (Bit 0) */ + #define R_NPU_QCONFIG_QCONFIG_Msk (0xffffffffUL) /*!< QCONFIG (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= QSIZE ========================================================= */ + #define R_NPU_QSIZE_QSIZE_Pos (0UL) /*!< QSIZE (Bit 0) */ + #define R_NPU_QSIZE_QSIZE_Msk (0xffffffffUL) /*!< QSIZE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PROT ========================================================== */ + #define R_NPU_PROT_active_CSL_Pos (1UL) /*!< active_CSL (Bit 1) */ + #define R_NPU_PROT_active_CSL_Msk (0x2UL) /*!< active_CSL (Bitfield-Mask: 0x01) */ + #define R_NPU_PROT_active_CPL_Pos (0UL) /*!< active_CPL (Bit 0) */ + #define R_NPU_PROT_active_CPL_Msk (0x1UL) /*!< active_CPL (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG ========================================================= */ + #define R_NPU_CONFIG_product_Pos (28UL) /*!< product (Bit 28) */ + #define R_NPU_CONFIG_product_Msk (0xf0000000UL) /*!< product (Bitfield-Mask: 0x0f) */ + #define R_NPU_CONFIG_custom_dma_Pos (27UL) /*!< custom_dma (Bit 27) */ + #define R_NPU_CONFIG_custom_dma_Msk (0x8000000UL) /*!< custom_dma (Bitfield-Mask: 0x01) */ + #define R_NPU_CONFIG_shram_size_Pos (8UL) /*!< shram_size (Bit 8) */ + #define R_NPU_CONFIG_shram_size_Msk (0xff00UL) /*!< shram_size (Bitfield-Mask: 0xff) */ + #define R_NPU_CONFIG_cmd_stream_version_Pos (4UL) /*!< cmd_stream_version (Bit 4) */ + #define R_NPU_CONFIG_cmd_stream_version_Msk (0xf0UL) /*!< cmd_stream_version (Bitfield-Mask: 0x0f) */ + #define R_NPU_CONFIG_macs_per_cc_Pos (0UL) /*!< macs_per_cc (Bit 0) */ + #define R_NPU_CONFIG_macs_per_cc_Msk (0xfUL) /*!< macs_per_cc (Bitfield-Mask: 0x0f) */ +/* ========================================================= LOCK ========================================================== */ + #define R_NPU_LOCK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_NPU_LOCK_LOCK_Msk (0xffffffffUL) /*!< LOCK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= REGIONCFG ======================================================= */ + #define R_NPU_REGIONCFG_region7_Pos (14UL) /*!< region7 (Bit 14) */ + #define R_NPU_REGIONCFG_region7_Msk (0xc000UL) /*!< region7 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region6_Pos (12UL) /*!< region6 (Bit 12) */ + #define R_NPU_REGIONCFG_region6_Msk (0x3000UL) /*!< region6 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region5_Pos (10UL) /*!< region5 (Bit 10) */ + #define R_NPU_REGIONCFG_region5_Msk (0xc00UL) /*!< region5 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region4_Pos (8UL) /*!< region4 (Bit 8) */ + #define R_NPU_REGIONCFG_region4_Msk (0x300UL) /*!< region4 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region3_Pos (6UL) /*!< region3 (Bit 6) */ + #define R_NPU_REGIONCFG_region3_Msk (0xc0UL) /*!< region3 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region2_Pos (4UL) /*!< region2 (Bit 4) */ + #define R_NPU_REGIONCFG_region2_Msk (0x30UL) /*!< region2 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region1_Pos (2UL) /*!< region1 (Bit 2) */ + #define R_NPU_REGIONCFG_region1_Msk (0xcUL) /*!< region1 (Bitfield-Mask: 0x03) */ + #define R_NPU_REGIONCFG_region0_Pos (0UL) /*!< region0 (Bit 0) */ + #define R_NPU_REGIONCFG_region0_Msk (0x3UL) /*!< region0 (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT0 ======================================================= */ + #define R_NPU_AXI_LIMIT0_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT0_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT0_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT0_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT0_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT0_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT1 ======================================================= */ + #define R_NPU_AXI_LIMIT1_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT1_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT1_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT1_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT1_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT1_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT2 ======================================================= */ + #define R_NPU_AXI_LIMIT2_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT2_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT2_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT2_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT2_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT2_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ====================================================== AXI_LIMIT3 ======================================================= */ + #define R_NPU_AXI_LIMIT3_max_outstanding_write_m1_Pos (24UL) /*!< max_outstanding_write_m1 (Bit 24) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_write_m1_Msk (0xff000000UL) /*!< max_outstanding_write_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_read_m1_Pos (16UL) /*!< max_outstanding_read_m1 (Bit 16) */ + #define R_NPU_AXI_LIMIT3_max_outstanding_read_m1_Msk (0xff0000UL) /*!< max_outstanding_read_m1 (Bitfield-Mask: 0xff) */ + #define R_NPU_AXI_LIMIT3_memtype_Pos (4UL) /*!< memtype (Bit 4) */ + #define R_NPU_AXI_LIMIT3_memtype_Msk (0xf0UL) /*!< memtype (Bitfield-Mask: 0x0f) */ + #define R_NPU_AXI_LIMIT3_max_beats_Pos (0UL) /*!< max_beats (Bit 0) */ + #define R_NPU_AXI_LIMIT3_max_beats_Msk (0x3UL) /*!< max_beats (Bitfield-Mask: 0x03) */ +/* ======================================================== BASEP0 ========================================================= */ + #define R_NPU_BASEP0_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP0_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP1 ========================================================= */ + #define R_NPU_BASEP1_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP1_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP2 ========================================================= */ + #define R_NPU_BASEP2_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP2_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP3 ========================================================= */ + #define R_NPU_BASEP3_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP3_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP4 ========================================================= */ + #define R_NPU_BASEP4_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP4_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP5 ========================================================= */ + #define R_NPU_BASEP5_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP5_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP6 ========================================================= */ + #define R_NPU_BASEP6_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP6_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP7 ========================================================= */ + #define R_NPU_BASEP7_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP7_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP8 ========================================================= */ + #define R_NPU_BASEP8_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP8_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP9 ========================================================= */ + #define R_NPU_BASEP9_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP9_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP10 ======================================================== */ + #define R_NPU_BASEP10_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP10_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP11 ======================================================== */ + #define R_NPU_BASEP11_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP11_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP12 ======================================================== */ + #define R_NPU_BASEP12_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP12_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP13 ======================================================== */ + #define R_NPU_BASEP13_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP13_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP14 ======================================================== */ + #define R_NPU_BASEP14_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP14_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BASEP15 ======================================================== */ + #define R_NPU_BASEP15_addr_word_Pos (0UL) /*!< addr_word (Bit 0) */ + #define R_NPU_BASEP15_addr_word_Msk (0xffffffffUL) /*!< addr_word (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID4 ========================================================== */ + #define R_NPU_PID4_PID4_Pos (0UL) /*!< PID4 (Bit 0) */ + #define R_NPU_PID4_PID4_Msk (0xffffffffUL) /*!< PID4 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID5 ========================================================== */ + #define R_NPU_PID5_PID5_Pos (0UL) /*!< PID5 (Bit 0) */ + #define R_NPU_PID5_PID5_Msk (0xffffffffUL) /*!< PID5 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID6 ========================================================== */ + #define R_NPU_PID6_PID6_Pos (0UL) /*!< PID6 (Bit 0) */ + #define R_NPU_PID6_PID6_Msk (0xffffffffUL) /*!< PID6 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID7 ========================================================== */ + #define R_NPU_PID7_PID7_Pos (0UL) /*!< PID7 (Bit 0) */ + #define R_NPU_PID7_PID7_Msk (0xffffffffUL) /*!< PID7 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID0 ========================================================== */ + #define R_NPU_PID0_PID0_Pos (0UL) /*!< PID0 (Bit 0) */ + #define R_NPU_PID0_PID0_Msk (0xffffffffUL) /*!< PID0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID1 ========================================================== */ + #define R_NPU_PID1_PID1_Pos (0UL) /*!< PID1 (Bit 0) */ + #define R_NPU_PID1_PID1_Msk (0xffffffffUL) /*!< PID1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID2 ========================================================== */ + #define R_NPU_PID2_PID2_Pos (0UL) /*!< PID2 (Bit 0) */ + #define R_NPU_PID2_PID2_Msk (0xffffffffUL) /*!< PID2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PID3 ========================================================== */ + #define R_NPU_PID3_PID3_Pos (0UL) /*!< PID3 (Bit 0) */ + #define R_NPU_PID3_PID3_Msk (0xffffffffUL) /*!< PID3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID0 ========================================================== */ + #define R_NPU_CID0_CID0_Pos (0UL) /*!< CID0 (Bit 0) */ + #define R_NPU_CID0_CID0_Msk (0xffffffffUL) /*!< CID0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID1 ========================================================== */ + #define R_NPU_CID1_CID1_Pos (0UL) /*!< CID1 (Bit 0) */ + #define R_NPU_CID1_CID1_Msk (0xffffffffUL) /*!< CID1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID2 ========================================================== */ + #define R_NPU_CID2_CID2_Pos (0UL) /*!< CID2 (Bit 0) */ + #define R_NPU_CID2_CID2_Msk (0xffffffffUL) /*!< CID2 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CID3 ========================================================== */ + #define R_NPU_CID3_CID3_Pos (0UL) /*!< CID3 (Bit 0) */ + #define R_NPU_CID3_CID3_Msk (0xffffffffUL) /*!< CID3 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PMCR ========================================================== */ + #define R_NPU_PMCR_num_event_cnt_Pos (11UL) /*!< num_event_cnt (Bit 11) */ + #define R_NPU_PMCR_num_event_cnt_Msk (0xf800UL) /*!< num_event_cnt (Bitfield-Mask: 0x1f) */ + #define R_NPU_PMCR_mask_en_Pos (3UL) /*!< mask_en (Bit 3) */ + #define R_NPU_PMCR_mask_en_Msk (0x8UL) /*!< mask_en (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_cycle_cnt_rst_Pos (2UL) /*!< cycle_cnt_rst (Bit 2) */ + #define R_NPU_PMCR_cycle_cnt_rst_Msk (0x4UL) /*!< cycle_cnt_rst (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_event_cnt_rst_Pos (1UL) /*!< event_cnt_rst (Bit 1) */ + #define R_NPU_PMCR_event_cnt_rst_Msk (0x2UL) /*!< event_cnt_rst (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCR_cnt_en_Pos (0UL) /*!< cnt_en (Bit 0) */ + #define R_NPU_PMCR_cnt_en_Msk (0x1UL) /*!< cnt_en (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCNTENSET ======================================================= */ + #define R_NPU_PMCNTENSET_CYCLE_CNT_Pos (31UL) /*!< CYCLE_CNT (Bit 31) */ + #define R_NPU_PMCNTENSET_CYCLE_CNT_Msk (0x80000000UL) /*!< CYCLE_CNT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_3_Pos (3UL) /*!< EVENT_CNT_3 (Bit 3) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_3_Msk (0x8UL) /*!< EVENT_CNT_3 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_2_Pos (2UL) /*!< EVENT_CNT_2 (Bit 2) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_2_Msk (0x4UL) /*!< EVENT_CNT_2 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_1_Pos (1UL) /*!< EVENT_CNT_1 (Bit 1) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_1_Msk (0x2UL) /*!< EVENT_CNT_1 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_0_Pos (0UL) /*!< EVENT_CNT_0 (Bit 0) */ + #define R_NPU_PMCNTENSET_EVENT_CNT_0_Msk (0x1UL) /*!< EVENT_CNT_0 (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCNTENCLR ======================================================= */ + #define R_NPU_PMCNTENCLR_CYCLE_CNT_Pos (31UL) /*!< CYCLE_CNT (Bit 31) */ + #define R_NPU_PMCNTENCLR_CYCLE_CNT_Msk (0x80000000UL) /*!< CYCLE_CNT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_3_Pos (3UL) /*!< EVENT_CNT_3 (Bit 3) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_3_Msk (0x8UL) /*!< EVENT_CNT_3 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_2_Pos (2UL) /*!< EVENT_CNT_2 (Bit 2) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_2_Msk (0x4UL) /*!< EVENT_CNT_2 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_1_Pos (1UL) /*!< EVENT_CNT_1 (Bit 1) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_1_Msk (0x2UL) /*!< EVENT_CNT_1 (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_0_Pos (0UL) /*!< EVENT_CNT_0 (Bit 0) */ + #define R_NPU_PMCNTENCLR_EVENT_CNT_0_Msk (0x1UL) /*!< EVENT_CNT_0 (Bitfield-Mask: 0x01) */ +/* ======================================================= PMOVSSET ======================================================== */ + #define R_NPU_PMOVSSET_CYCLE_CNT_OVF_Pos (31UL) /*!< CYCLE_CNT_OVF (Bit 31) */ + #define R_NPU_PMOVSSET_CYCLE_CNT_OVF_Msk (0x80000000UL) /*!< CYCLE_CNT_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_3_OVF_Pos (3UL) /*!< EVENT_CNT_3_OVF (Bit 3) */ + #define R_NPU_PMOVSSET_EVENT_CNT_3_OVF_Msk (0x8UL) /*!< EVENT_CNT_3_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_2_OVF_Pos (2UL) /*!< EVENT_CNT_2_OVF (Bit 2) */ + #define R_NPU_PMOVSSET_EVENT_CNT_2_OVF_Msk (0x4UL) /*!< EVENT_CNT_2_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_1_OVF_Pos (1UL) /*!< EVENT_CNT_1_OVF (Bit 1) */ + #define R_NPU_PMOVSSET_EVENT_CNT_1_OVF_Msk (0x2UL) /*!< EVENT_CNT_1_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSSET_EVENT_CNT_0_OVF_Pos (0UL) /*!< EVENT_CNT_0_OVF (Bit 0) */ + #define R_NPU_PMOVSSET_EVENT_CNT_0_OVF_Msk (0x1UL) /*!< EVENT_CNT_0_OVF (Bitfield-Mask: 0x01) */ +/* ======================================================= PMOVSCLR ======================================================== */ + #define R_NPU_PMOVSCLR_CYCLE_CNT_OVF_Pos (31UL) /*!< CYCLE_CNT_OVF (Bit 31) */ + #define R_NPU_PMOVSCLR_CYCLE_CNT_OVF_Msk (0x80000000UL) /*!< CYCLE_CNT_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_3_OVF_Pos (3UL) /*!< EVENT_CNT_3_OVF (Bit 3) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_3_OVF_Msk (0x8UL) /*!< EVENT_CNT_3_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_2_OVF_Pos (2UL) /*!< EVENT_CNT_2_OVF (Bit 2) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_2_OVF_Msk (0x4UL) /*!< EVENT_CNT_2_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_1_OVF_Pos (1UL) /*!< EVENT_CNT_1_OVF (Bit 1) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_1_OVF_Msk (0x2UL) /*!< EVENT_CNT_1_OVF (Bitfield-Mask: 0x01) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_0_OVF_Pos (0UL) /*!< EVENT_CNT_0_OVF (Bit 0) */ + #define R_NPU_PMOVSCLR_EVENT_CNT_0_OVF_Msk (0x1UL) /*!< EVENT_CNT_0_OVF (Bitfield-Mask: 0x01) */ +/* ======================================================= PMINTSET ======================================================== */ + #define R_NPU_PMINTSET_CYCLE_CNT_INT_Pos (31UL) /*!< CYCLE_CNT_INT (Bit 31) */ + #define R_NPU_PMINTSET_CYCLE_CNT_INT_Msk (0x80000000UL) /*!< CYCLE_CNT_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_3_INT_Pos (3UL) /*!< EVENT_CNT_3_INT (Bit 3) */ + #define R_NPU_PMINTSET_EVENT_CNT_3_INT_Msk (0x8UL) /*!< EVENT_CNT_3_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_2_INT_Pos (2UL) /*!< EVENT_CNT_2_INT (Bit 2) */ + #define R_NPU_PMINTSET_EVENT_CNT_2_INT_Msk (0x4UL) /*!< EVENT_CNT_2_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_1_INT_Pos (1UL) /*!< EVENT_CNT_1_INT (Bit 1) */ + #define R_NPU_PMINTSET_EVENT_CNT_1_INT_Msk (0x2UL) /*!< EVENT_CNT_1_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTSET_EVENT_CNT_0_INT_Pos (0UL) /*!< EVENT_CNT_0_INT (Bit 0) */ + #define R_NPU_PMINTSET_EVENT_CNT_0_INT_Msk (0x1UL) /*!< EVENT_CNT_0_INT (Bitfield-Mask: 0x01) */ +/* ======================================================= PMINTCLR ======================================================== */ + #define R_NPU_PMINTCLR_CYCLE_CNT_INT_Pos (31UL) /*!< CYCLE_CNT_INT (Bit 31) */ + #define R_NPU_PMINTCLR_CYCLE_CNT_INT_Msk (0x80000000UL) /*!< CYCLE_CNT_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_3_INT_Pos (3UL) /*!< EVENT_CNT_3_INT (Bit 3) */ + #define R_NPU_PMINTCLR_EVENT_CNT_3_INT_Msk (0x8UL) /*!< EVENT_CNT_3_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_2_INT_Pos (2UL) /*!< EVENT_CNT_2_INT (Bit 2) */ + #define R_NPU_PMINTCLR_EVENT_CNT_2_INT_Msk (0x4UL) /*!< EVENT_CNT_2_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_1_INT_Pos (1UL) /*!< EVENT_CNT_1_INT (Bit 1) */ + #define R_NPU_PMINTCLR_EVENT_CNT_1_INT_Msk (0x2UL) /*!< EVENT_CNT_1_INT (Bitfield-Mask: 0x01) */ + #define R_NPU_PMINTCLR_EVENT_CNT_0_INT_Pos (0UL) /*!< EVENT_CNT_0_INT (Bit 0) */ + #define R_NPU_PMINTCLR_EVENT_CNT_0_INT_Msk (0x1UL) /*!< EVENT_CNT_0_INT (Bitfield-Mask: 0x01) */ +/* ====================================================== PMCCNTR_LO ======================================================= */ + #define R_NPU_PMCCNTR_LO_CYCLE_CNT_LO_Pos (0UL) /*!< CYCLE_CNT_LO (Bit 0) */ + #define R_NPU_PMCCNTR_LO_CYCLE_CNT_LO_Msk (0xffffffffUL) /*!< CYCLE_CNT_LO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMCCNTR_HI ======================================================= */ + #define R_NPU_PMCCNTR_HI_CYCLE_CNT_HI_Pos (0UL) /*!< CYCLE_CNT_HI (Bit 0) */ + #define R_NPU_PMCCNTR_HI_CYCLE_CNT_HI_Msk (0xffffffffUL) /*!< CYCLE_CNT_HI (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMCAXI_CHAN ====================================================== */ + #define R_NPU_PMCAXI_CHAN_BW_CH_SEL_EN_Pos (10UL) /*!< BW_CH_SEL_EN (Bit 10) */ + #define R_NPU_PMCAXI_CHAN_BW_CH_SEL_EN_Msk (0x400UL) /*!< BW_CH_SEL_EN (Bitfield-Mask: 0x01) */ + #define R_NPU_PMCAXI_CHAN_AXI_CNT_SEL_Pos (8UL) /*!< AXI_CNT_SEL (Bit 8) */ + #define R_NPU_PMCAXI_CHAN_AXI_CNT_SEL_Msk (0x300UL) /*!< AXI_CNT_SEL (Bitfield-Mask: 0x03) */ + #define R_NPU_PMCAXI_CHAN_CH_SEL_Pos (0UL) /*!< CH_SEL (Bit 0) */ + #define R_NPU_PMCAXI_CHAN_CH_SEL_Msk (0xfUL) /*!< CH_SEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== PMU_EVCNTR0 ====================================================== */ + #define R_NPU_PMU_EVCNTR0_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR0_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR1 ====================================================== */ + #define R_NPU_PMU_EVCNTR1_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR1_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR2 ====================================================== */ + #define R_NPU_PMU_EVCNTR2_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR2_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PMU_EVCNTR3 ====================================================== */ + #define R_NPU_PMU_EVCNTR3_PMEVCNTR_Pos (0UL) /*!< PMEVCNTR (Bit 0) */ + #define R_NPU_PMU_EVCNTR3_PMEVCNTR_Msk (0xffffffffUL) /*!< PMEVCNTR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER0 ====================================================== */ + #define R_NPU_PMU_EVTYPER0_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER0_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER1 ====================================================== */ + #define R_NPU_PMU_EVTYPER1_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER1_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER2 ====================================================== */ + #define R_NPU_PMU_EVTYPER2_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER2_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PMU_EVTYPER3 ====================================================== */ + #define R_NPU_PMU_EVTYPER3_EV_TYPE_Pos (0UL) /*!< EV_TYPE (Bit 0) */ + #define R_NPU_PMU_EVTYPER3_EV_TYPE_Msk (0xffffffffUL) /*!< EV_TYPE (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_PDM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PDCSTRTR ======================================================== */ + #define R_PDM_PDCSTRTR_STRTRG0_Pos (0UL) /*!< STRTRG0 (Bit 0) */ + #define R_PDM_PDCSTRTR_STRTRG0_Msk (0x1UL) /*!< STRTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTRTR_STRTRG1_Pos (1UL) /*!< STRTRG1 (Bit 1) */ + #define R_PDM_PDCSTRTR_STRTRG1_Msk (0x2UL) /*!< STRTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTRTR_STRTRG2_Pos (2UL) /*!< STRTRG2 (Bit 2) */ + #define R_PDM_PDCSTRTR_STRTRG2_Msk (0x4UL) /*!< STRTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCSTPTR ======================================================== */ + #define R_PDM_PDCSTPTR_STPTRG0_Pos (0UL) /*!< STPTRG0 (Bit 0) */ + #define R_PDM_PDCSTPTR_STPTRG0_Msk (0x1UL) /*!< STPTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTPTR_STPTRG1_Pos (1UL) /*!< STPTRG1 (Bit 1) */ + #define R_PDM_PDCSTPTR_STPTRG1_Msk (0x2UL) /*!< STPTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSTPTR_STPTRG2_Pos (2UL) /*!< STPTRG2 (Bit 2) */ + #define R_PDM_PDCSTPTR_STPTRG2_Msk (0x4UL) /*!< STPTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= PDCCHGTR ======================================================== */ + #define R_PDM_PDCCHGTR_CHGTRG0_Pos (0UL) /*!< CHGTRG0 (Bit 0) */ + #define R_PDM_PDCCHGTR_CHGTRG0_Msk (0x1UL) /*!< CHGTRG0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCCHGTR_CHGTRG1_Pos (1UL) /*!< CHGTRG1 (Bit 1) */ + #define R_PDM_PDCCHGTR_CHGTRG1_Msk (0x2UL) /*!< CHGTRG1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCCHGTR_CHGTRG2_Pos (2UL) /*!< CHGTRG2 (Bit 2) */ + #define R_PDM_PDCCHGTR_CHGTRG2_Msk (0x4UL) /*!< CHGTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCICR ========================================================= */ + #define R_PDM_PDCICR_ISDE0_Pos (8UL) /*!< ISDE0 (Bit 8) */ + #define R_PDM_PDCICR_ISDE0_Msk (0x100UL) /*!< ISDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_ISDE1_Pos (9UL) /*!< ISDE1 (Bit 9) */ + #define R_PDM_PDCICR_ISDE1_Msk (0x200UL) /*!< ISDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_ISDE2_Pos (10UL) /*!< ISDE2 (Bit 10) */ + #define R_PDM_PDCICR_ISDE2_Msk (0x400UL) /*!< ISDE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE0_Pos (16UL) /*!< IDRE0 (Bit 16) */ + #define R_PDM_PDCICR_IDRE0_Msk (0x10000UL) /*!< IDRE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE1_Pos (17UL) /*!< IDRE1 (Bit 17) */ + #define R_PDM_PDCICR_IDRE1_Msk (0x20000UL) /*!< IDRE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IDRE2_Pos (18UL) /*!< IDRE2 (Bit 18) */ + #define R_PDM_PDCICR_IDRE2_Msk (0x40000UL) /*!< IDRE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE0_Pos (24UL) /*!< IEDE0 (Bit 24) */ + #define R_PDM_PDCICR_IEDE0_Msk (0x1000000UL) /*!< IEDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE1_Pos (25UL) /*!< IEDE1 (Bit 25) */ + #define R_PDM_PDCICR_IEDE1_Msk (0x2000000UL) /*!< IEDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCICR_IEDE2_Pos (26UL) /*!< IEDE2 (Bit 26) */ + #define R_PDM_PDCICR_IEDE2_Msk (0x4000000UL) /*!< IEDE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= PDCSR ========================================================= */ + #define R_PDM_PDCSR_STATE0_Pos (0UL) /*!< STATE0 (Bit 0) */ + #define R_PDM_PDCSR_STATE0_Msk (0x1UL) /*!< STATE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_STATE1_Pos (1UL) /*!< STATE1 (Bit 1) */ + #define R_PDM_PDCSR_STATE1_Msk (0x2UL) /*!< STATE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_STATE2_Pos (2UL) /*!< STATE2 (Bit 2) */ + #define R_PDM_PDCSR_STATE2_Msk (0x4UL) /*!< STATE2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF0_Pos (8UL) /*!< SDF0 (Bit 8) */ + #define R_PDM_PDCSR_SDF0_Msk (0x100UL) /*!< SDF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF1_Pos (9UL) /*!< SDF1 (Bit 9) */ + #define R_PDM_PDCSR_SDF1_Msk (0x200UL) /*!< SDF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_SDF2_Pos (10UL) /*!< SDF2 (Bit 10) */ + #define R_PDM_PDCSR_SDF2_Msk (0x400UL) /*!< SDF2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF0_Pos (16UL) /*!< DRF0 (Bit 16) */ + #define R_PDM_PDCSR_DRF0_Msk (0x10000UL) /*!< DRF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF1_Pos (17UL) /*!< DRF1 (Bit 17) */ + #define R_PDM_PDCSR_DRF1_Msk (0x20000UL) /*!< DRF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_DRF2_Pos (18UL) /*!< DRF2 (Bit 18) */ + #define R_PDM_PDCSR_DRF2_Msk (0x40000UL) /*!< DRF2 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF0_Pos (24UL) /*!< EDF0 (Bit 24) */ + #define R_PDM_PDCSR_EDF0_Msk (0x1000000UL) /*!< EDF0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF1_Pos (25UL) /*!< EDF1 (Bit 25) */ + #define R_PDM_PDCSR_EDF1_Msk (0x2000000UL) /*!< EDF1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSR_EDF2_Pos (26UL) /*!< EDF2 (Bit 26) */ + #define R_PDM_PDCSR_EDF2_Msk (0x4000000UL) /*!< EDF2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCSCR ========================================================= */ + #define R_PDM_PDCSCR_SDFC0_Pos (8UL) /*!< SDFC0 (Bit 8) */ + #define R_PDM_PDCSCR_SDFC0_Msk (0x100UL) /*!< SDFC0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSCR_SDFC1_Pos (9UL) /*!< SDFC1 (Bit 9) */ + #define R_PDM_PDCSCR_SDFC1_Msk (0x200UL) /*!< SDFC1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSCR_SDFC2_Pos (10UL) /*!< SDFC2 (Bit 10) */ + #define R_PDM_PDCSCR_SDFC2_Msk (0x400UL) /*!< SDFC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCSDCR ======================================================== */ + #define R_PDM_PDCSDCR_SDE0_Pos (0UL) /*!< SDE0 (Bit 0) */ + #define R_PDM_PDCSDCR_SDE0_Msk (0x1UL) /*!< SDE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSDCR_SDE1_Pos (1UL) /*!< SDE1 (Bit 1) */ + #define R_PDM_PDCSDCR_SDE1_Msk (0x2UL) /*!< SDE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCSDCR_SDE2_Pos (2UL) /*!< SDE2 (Bit 2) */ + #define R_PDM_PDCSDCR_SDE2_Msk (0x4UL) /*!< SDE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCDRCR ======================================================== */ + #define R_PDM_PDCDRCR_DATRE0_Pos (0UL) /*!< DATRE0 (Bit 0) */ + #define R_PDM_PDCDRCR_DATRE0_Msk (0x1UL) /*!< DATRE0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDRCR_DATRE1_Pos (1UL) /*!< DATRE1 (Bit 1) */ + #define R_PDM_PDCDRCR_DATRE1_Msk (0x2UL) /*!< DATRE1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDRCR_DATRE2_Pos (2UL) /*!< DATRE2 (Bit 2) */ + #define R_PDM_PDCDRCR_DATRE2_Msk (0x4UL) /*!< DATRE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== PDCDCR ========================================================= */ + #define R_PDM_PDCDCR_DATC0_Pos (0UL) /*!< DATC0 (Bit 0) */ + #define R_PDM_PDCDCR_DATC0_Msk (0x1UL) /*!< DATC0 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDCR_DATC1_Pos (1UL) /*!< DATC1 (Bit 1) */ + #define R_PDM_PDCDCR_DATC1_Msk (0x2UL) /*!< DATC1 (Bitfield-Mask: 0x01) */ + #define R_PDM_PDCDCR_DATC2_Pos (2UL) /*!< DATC2 (Bit 2) */ + #define R_PDM_PDCDCR_DATC2_Msk (0x4UL) /*!< DATC2 (Bitfield-Mask: 0x01) */ +/* ========================================================= PDVR ========================================================== */ + #define R_PDM_PDVR_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_PDM_PDVR_VER_Msk (0xfffUL) /*!< VER (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ R_RMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MPSM ========================================================== */ + #define R_RMAC0_MPSM_PSME_Pos (0UL) /*!< PSME (Bit 0) */ + #define R_RMAC0_MPSM_PSME_Msk (0x1UL) /*!< PSME (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPSM_MFF_Pos (2UL) /*!< MFF (Bit 2) */ + #define R_RMAC0_MPSM_MFF_Msk (0x4UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPSM_PDA_Pos (3UL) /*!< PDA (Bit 3) */ + #define R_RMAC0_MPSM_PDA_Msk (0xf8UL) /*!< PDA (Bitfield-Mask: 0x1f) */ + #define R_RMAC0_MPSM_PRA_Pos (8UL) /*!< PRA (Bit 8) */ + #define R_RMAC0_MPSM_PRA_Msk (0x1f00UL) /*!< PRA (Bitfield-Mask: 0x1f) */ + #define R_RMAC0_MPSM_POP_Pos (13UL) /*!< POP (Bit 13) */ + #define R_RMAC0_MPSM_POP_Msk (0x6000UL) /*!< POP (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MPSM_PRD_Pos (16UL) /*!< PRD (Bit 16) */ + #define R_RMAC0_MPSM_PRD_Msk (0xffff0000UL) /*!< PRD (Bitfield-Mask: 0xffff) */ +/* ========================================================= MPIC ========================================================== */ + #define R_RMAC0_MPIC_PIS_Pos (0UL) /*!< PIS (Bit 0) */ + #define R_RMAC0_MPIC_PIS_Msk (0x7UL) /*!< PIS (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_LSC_Pos (3UL) /*!< LSC (Bit 3) */ + #define R_RMAC0_MPIC_LSC_Msk (0x38UL) /*!< LSC (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_PIP_Pos (8UL) /*!< PIP (Bit 8) */ + #define R_RMAC0_MPIC_PIP_Msk (0x100UL) /*!< PIP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PIPP_Pos (9UL) /*!< PIPP (Bit 9) */ + #define R_RMAC0_MPIC_PIPP_Msk (0x200UL) /*!< PIPP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PLSPP_Pos (10UL) /*!< PLSPP (Bit 10) */ + #define R_RMAC0_MPIC_PLSPP_Msk (0x400UL) /*!< PLSPP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PSMCS_Pos (16UL) /*!< PSMCS (Bit 16) */ + #define R_RMAC0_MPIC_PSMCS_Msk (0x7f0000UL) /*!< PSMCS (Bitfield-Mask: 0x7f) */ + #define R_RMAC0_MPIC_PSMDP_Pos (23UL) /*!< PSMDP (Bit 23) */ + #define R_RMAC0_MPIC_PSMDP_Msk (0x800000UL) /*!< PSMDP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIC_PSMHT_Pos (24UL) /*!< PSMHT (Bit 24) */ + #define R_RMAC0_MPIC_PSMHT_Msk (0x7000000UL) /*!< PSMHT (Bitfield-Mask: 0x07) */ + #define R_RMAC0_MPIC_PSMCT_Pos (28UL) /*!< PSMCT (Bit 28) */ + #define R_RMAC0_MPIC_PSMCT_Msk (0x70000000UL) /*!< PSMCT (Bitfield-Mask: 0x07) */ +/* ========================================================= MPIM ========================================================== */ + #define R_RMAC0_MPIM_PLS_Pos (0UL) /*!< PLS (Bit 0) */ + #define R_RMAC0_MPIM_PLS_Msk (0x1UL) /*!< PLS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPIM_LPIA_Pos (1UL) /*!< LPIA (Bit 1) */ + #define R_RMAC0_MPIM_LPIA_Msk (0x2UL) /*!< LPIA (Bitfield-Mask: 0x01) */ +/* ========================================================= MIOC ========================================================== */ + #define R_RMAC0_MIOC_MIOC_Pos (0UL) /*!< MIOC (Bit 0) */ + #define R_RMAC0_MIOC_MIOC_Msk (0xffffffffUL) /*!< MIOC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTFFC ========================================================= */ + #define R_RMAC0_MTFFC_DPAD_Pos (0UL) /*!< DPAD (Bit 0) */ + #define R_RMAC0_MTFFC_DPAD_Msk (0x1UL) /*!< DPAD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTFFC_FCM_Pos (1UL) /*!< FCM (Bit 1) */ + #define R_RMAC0_MTFFC_FCM_Msk (0x2UL) /*!< FCM (Bitfield-Mask: 0x01) */ +/* ========================================================= MTPFC ========================================================= */ + #define R_RMAC0_MTPFC_PT_Pos (0UL) /*!< PT (Bit 0) */ + #define R_RMAC0_MTPFC_PT_Msk (0xffffUL) /*!< PT (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MTPFC_PFRT_Pos (16UL) /*!< PFRT (Bit 16) */ + #define R_RMAC0_MTPFC_PFRT_Msk (0xff0000UL) /*!< PFRT (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTPFC_PFM_Pos (26UL) /*!< PFM (Bit 26) */ + #define R_RMAC0_MTPFC_PFM_Msk (0x4000000UL) /*!< PFM (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC_PFRLV_Pos (27UL) /*!< PFRLV (Bit 27) */ + #define R_RMAC0_MTPFC_PFRLV_Msk (0xf8000000UL) /*!< PFRLV (Bitfield-Mask: 0x1f) */ +/* ======================================================== MTPFC2 ========================================================= */ + #define R_RMAC0_MTPFC2_PFCTTZ_Pos (0UL) /*!< PFCTTZ (Bit 0) */ + #define R_RMAC0_MTPFC2_PFCTTZ_Msk (0x3UL) /*!< PFCTTZ (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MTPFC2_MPFCFR0_Pos (8UL) /*!< MPFCFR0 (Bit 8) */ + #define R_RMAC0_MTPFC2_MPFCFR0_Msk (0x100UL) /*!< MPFCFR0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_MPFCFR1_Pos (9UL) /*!< MPFCFR1 (Bit 9) */ + #define R_RMAC0_MTPFC2_MPFCFR1_Msk (0x200UL) /*!< MPFCFR1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_PFTTZ_Pos (16UL) /*!< PFTTZ (Bit 16) */ + #define R_RMAC0_MTPFC2_PFTTZ_Msk (0x10000UL) /*!< PFTTZ (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTPFC2_MPFR_Pos (17UL) /*!< MPFR (Bit 17) */ + #define R_RMAC0_MTPFC2_MPFR_Msk (0x20000UL) /*!< MPFR (Bitfield-Mask: 0x01) */ +/* ======================================================== MTPFC30 ======================================================== */ + #define R_RMAC0_MTPFC30_PFCPG_Pos (0UL) /*!< PFCPG (Bit 0) */ + #define R_RMAC0_MTPFC30_PFCPG_Msk (0xffUL) /*!< PFCPG (Bitfield-Mask: 0xff) */ +/* ======================================================== MTPFC31 ======================================================== */ + #define R_RMAC0_MTPFC31_PFCPG_Pos (0UL) /*!< PFCPG (Bit 0) */ + #define R_RMAC0_MTPFC31_PFCPG_Msk (0xffUL) /*!< PFCPG (Bitfield-Mask: 0xff) */ +/* ======================================================== MTATC0 ========================================================= */ + #define R_RMAC0_MTATC0_TRTP_Pos (0UL) /*!< TRTP (Bit 0) */ + #define R_RMAC0_MTATC0_TRTP_Msk (0xffUL) /*!< TRTP (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTATC0_TRTL_Pos (8UL) /*!< TRTL (Bit 8) */ + #define R_RMAC0_MTATC0_TRTL_Msk (0x700UL) /*!< TRTL (Bitfield-Mask: 0x07) */ +/* ======================================================== MTATC1 ========================================================= */ + #define R_RMAC0_MTATC1_TRTP_Pos (0UL) /*!< TRTP (Bit 0) */ + #define R_RMAC0_MTATC1_TRTP_Msk (0xffUL) /*!< TRTP (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MTATC1_TRTL_Pos (8UL) /*!< TRTL (Bit 8) */ + #define R_RMAC0_MTATC1_TRTL_Msk (0x700UL) /*!< TRTL (Bitfield-Mask: 0x07) */ +/* ========================================================= MTIM ========================================================== */ + #define R_RMAC0_MTIM_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_RMAC0_MTIM_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ========================================================= MRGC ========================================================== */ + #define R_RMAC0_MRGC_RCPT_Pos (0UL) /*!< RCPT (Bit 0) */ + #define R_RMAC0_MRGC_RCPT_Msk (0x1UL) /*!< RCPT (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFRC_Pos (1UL) /*!< PFRC (Bit 1) */ + #define R_RMAC0_MRGC_PFRC_Msk (0x2UL) /*!< PFRC (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFRTZ_Pos (2UL) /*!< PFRTZ (Bit 2) */ + #define R_RMAC0_MRGC_PFRTZ_Msk (0x4UL) /*!< PFRTZ (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_MPDE_Pos (3UL) /*!< MPDE (Bit 3) */ + #define R_RMAC0_MRGC_MPDE_Msk (0x8UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_RFCFE_Pos (4UL) /*!< RFCFE (Bit 4) */ + #define R_RMAC0_MRGC_RFCFE_Msk (0x10UL) /*!< RFCFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRGC_PFCRC_Pos (16UL) /*!< PFCRC (Bit 16) */ + #define R_RMAC0_MRGC_PFCRC_Msk (0xff0000UL) /*!< PFCRC (Bitfield-Mask: 0xff) */ +/* ======================================================== MRMAC0 ========================================================= */ + #define R_RMAC0_MRMAC0_MAU_Pos (0UL) /*!< MAU (Bit 0) */ + #define R_RMAC0_MRMAC0_MAU_Msk (0xffffUL) /*!< MAU (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRMAC1 ========================================================= */ + #define R_RMAC0_MRMAC1_MAL_Pos (0UL) /*!< MAL (Bit 0) */ + #define R_RMAC0_MRMAC1_MAL_Msk (0xffffffffUL) /*!< MAL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRAFC ========================================================= */ + #define R_RMAC0_MRAFC_UCENE_Pos (0UL) /*!< UCENE (Bit 0) */ + #define R_RMAC0_MRAFC_UCENE_Msk (0x1UL) /*!< UCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCENE_Pos (1UL) /*!< MCENE (Bit 1) */ + #define R_RMAC0_MRAFC_MCENE_Msk (0x2UL) /*!< MCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCENE_Pos (2UL) /*!< BCENE (Bit 2) */ + #define R_RMAC0_MRAFC_BCENE_Msk (0x4UL) /*!< BCENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSTENE_Pos (3UL) /*!< MSTENE (Bit 3) */ + #define R_RMAC0_MRAFC_MSTENE_Msk (0x8UL) /*!< MSTENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BSTENE_Pos (4UL) /*!< BSTENE (Bit 4) */ + #define R_RMAC0_MRAFC_BSTENE_Msk (0x10UL) /*!< BSTENE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCACE_Pos (5UL) /*!< MCACE (Bit 5) */ + #define R_RMAC0_MRAFC_MCACE_Msk (0x20UL) /*!< MCACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCACE_Pos (6UL) /*!< BCACE (Bit 6) */ + #define R_RMAC0_MRAFC_BCACE_Msk (0x40UL) /*!< BCACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NDAREE_Pos (7UL) /*!< NDAREE (Bit 7) */ + #define R_RMAC0_MRAFC_NDAREE_Msk (0x80UL) /*!< NDAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_SDSFREE_Pos (8UL) /*!< SDSFREE (Bit 8) */ + #define R_RMAC0_MRAFC_SDSFREE_Msk (0x100UL) /*!< SDSFREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NSAREE_Pos (9UL) /*!< NSAREE (Bit 9) */ + #define R_RMAC0_MRAFC_NSAREE_Msk (0x200UL) /*!< NSAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSAREE_Pos (10UL) /*!< MSAREE (Bit 10) */ + #define R_RMAC0_MRAFC_MSAREE_Msk (0x400UL) /*!< MSAREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_UCENP_Pos (16UL) /*!< UCENP (Bit 16) */ + #define R_RMAC0_MRAFC_UCENP_Msk (0x10000UL) /*!< UCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCENP_Pos (17UL) /*!< MCENP (Bit 17) */ + #define R_RMAC0_MRAFC_MCENP_Msk (0x20000UL) /*!< MCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCENP_Pos (18UL) /*!< BCENP (Bit 18) */ + #define R_RMAC0_MRAFC_BCENP_Msk (0x40000UL) /*!< BCENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSTENP_Pos (19UL) /*!< MSTENP (Bit 19) */ + #define R_RMAC0_MRAFC_MSTENP_Msk (0x80000UL) /*!< MSTENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BSTENP_Pos (20UL) /*!< BSTENP (Bit 20) */ + #define R_RMAC0_MRAFC_BSTENP_Msk (0x100000UL) /*!< BSTENP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MCACP_Pos (21UL) /*!< MCACP (Bit 21) */ + #define R_RMAC0_MRAFC_MCACP_Msk (0x200000UL) /*!< MCACP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_BCACP_Pos (22UL) /*!< BCACP (Bit 22) */ + #define R_RMAC0_MRAFC_BCACP_Msk (0x400000UL) /*!< BCACP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NDAREP_Pos (23UL) /*!< NDAREP (Bit 23) */ + #define R_RMAC0_MRAFC_NDAREP_Msk (0x800000UL) /*!< NDAREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_SDSFREP_Pos (24UL) /*!< SDSFREP (Bit 24) */ + #define R_RMAC0_MRAFC_SDSFREP_Msk (0x1000000UL) /*!< SDSFREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_NSAREP_Pos (25UL) /*!< NSAREP (Bit 25) */ + #define R_RMAC0_MRAFC_NSAREP_Msk (0x2000000UL) /*!< NSAREP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRAFC_MSAREP_Pos (26UL) /*!< MSAREP (Bit 26) */ + #define R_RMAC0_MRAFC_MSAREP_Msk (0x4000000UL) /*!< MSAREP (Bitfield-Mask: 0x01) */ +/* ========================================================= MRSCE ========================================================= */ + #define R_RMAC0_MRSCE_CMFE_Pos (0UL) /*!< CMFE (Bit 0) */ + #define R_RMAC0_MRSCE_CMFE_Msk (0xffffUL) /*!< CMFE (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRSCE_CBFE_Pos (16UL) /*!< CBFE (Bit 16) */ + #define R_RMAC0_MRSCE_CBFE_Msk (0xffff0000UL) /*!< CBFE (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRSCP ========================================================= */ + #define R_RMAC0_MRSCP_CMFP_Pos (0UL) /*!< CMFP (Bit 0) */ + #define R_RMAC0_MRSCP_CMFP_Msk (0xffffUL) /*!< CMFP (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRSCP_CBFP_Pos (16UL) /*!< CBFP (Bit 16) */ + #define R_RMAC0_MRSCP_CBFP_Msk (0xffff0000UL) /*!< CBFP (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRSCC ========================================================= */ + #define R_RMAC0_MRSCC_MSCCE_Pos (0UL) /*!< MSCCE (Bit 0) */ + #define R_RMAC0_MRSCC_MSCCE_Msk (0x1UL) /*!< MSCCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_BSCCE_Pos (1UL) /*!< BSCCE (Bit 1) */ + #define R_RMAC0_MRSCC_BSCCE_Msk (0x2UL) /*!< BSCCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_MSCCP_Pos (16UL) /*!< MSCCP (Bit 16) */ + #define R_RMAC0_MRSCC_MSCCP_Msk (0x10000UL) /*!< MSCCP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRSCC_BSCCP_Pos (17UL) /*!< BSCCP (Bit 17) */ + #define R_RMAC0_MRSCC_BSCCP_Msk (0x20000UL) /*!< BSCCP (Bitfield-Mask: 0x01) */ +/* ======================================================== MRFSCE ========================================================= */ + #define R_RMAC0_MRFSCE_EMXS_Pos (0UL) /*!< EMXS (Bit 0) */ + #define R_RMAC0_MRFSCE_EMXS_Msk (0xffffUL) /*!< EMXS (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRFSCE_EMNS_Pos (16UL) /*!< EMNS (Bit 16) */ + #define R_RMAC0_MRFSCE_EMNS_Msk (0xffff0000UL) /*!< EMNS (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFSCP ========================================================= */ + #define R_RMAC0_MRFSCP_PMXS_Pos (0UL) /*!< PMXS (Bit 0) */ + #define R_RMAC0_MRFSCP_PMXS_Msk (0xffffUL) /*!< PMXS (Bitfield-Mask: 0xffff) */ + #define R_RMAC0_MRFSCP_PMNS_Pos (16UL) /*!< PMNS (Bit 16) */ + #define R_RMAC0_MRFSCP_PMNS_Msk (0xffff0000UL) /*!< PMNS (Bitfield-Mask: 0xffff) */ +/* ========================================================= MTRC ========================================================== */ + #define R_RMAC0_MTRC_TRHFME0_Pos (0UL) /*!< TRHFME0 (Bit 0) */ + #define R_RMAC0_MTRC_TRHFME0_Msk (0x1UL) /*!< TRHFME0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRHFME1_Pos (1UL) /*!< TRHFME1 (Bit 1) */ + #define R_RMAC0_MTRC_TRHFME1_Msk (0x2UL) /*!< TRHFME1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRDDE_Pos (24UL) /*!< TRDDE (Bit 24) */ + #define R_RMAC0_MTRC_TRDDE_Msk (0x1000000UL) /*!< TRDDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TRDDP_Pos (25UL) /*!< TRDDP (Bit 25) */ + #define R_RMAC0_MTRC_TRDDP_Msk (0x2000000UL) /*!< TRDDP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TCTSE_Pos (26UL) /*!< TCTSE (Bit 26) */ + #define R_RMAC0_MTRC_TCTSE_Msk (0x4000000UL) /*!< TCTSE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_TCTSP_Pos (27UL) /*!< TCTSP (Bit 27) */ + #define R_RMAC0_MTRC_TCTSP_Msk (0x8000000UL) /*!< TCTSP (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MTRC_DTN_Pos (28UL) /*!< DTN (Bit 28) */ + #define R_RMAC0_MTRC_DTN_Msk (0x10000000UL) /*!< DTN (Bitfield-Mask: 0x01) */ +/* ========================================================= MRPFM ========================================================= */ + #define R_RMAC0_MRPFM_PTCA_Pos (0UL) /*!< PTCA (Bit 0) */ + #define R_RMAC0_MRPFM_PTCA_Msk (0x1UL) /*!< PTCA (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MRPFM_PFCTCA_Pos (16UL) /*!< PFCTCA (Bit 16) */ + #define R_RMAC0_MRPFM_PFCTCA_Msk (0xff0000UL) /*!< PFCTCA (Bitfield-Mask: 0xff) */ +/* ========================================================= MPFC0 ========================================================= */ + #define R_RMAC0_MPFC0_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC0_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC0_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC0_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC0_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC0_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC0_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC0_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC1 ========================================================= */ + #define R_RMAC0_MPFC1_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC1_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC1_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC1_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC1_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC1_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC1_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC1_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC2 ========================================================= */ + #define R_RMAC0_MPFC2_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC2_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC2_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC2_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC2_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC2_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC2_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC2_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC3 ========================================================= */ + #define R_RMAC0_MPFC3_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC3_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC3_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC3_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC3_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC3_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC3_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC3_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC4 ========================================================= */ + #define R_RMAC0_MPFC4_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC4_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC4_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC4_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC4_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC4_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC4_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC4_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC5 ========================================================= */ + #define R_RMAC0_MPFC5_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC5_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC5_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC5_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC5_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC5_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC5_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC5_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC6 ========================================================= */ + #define R_RMAC0_MPFC6_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC6_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC6_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC6_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC6_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC6_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC6_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC6_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC7 ========================================================= */ + #define R_RMAC0_MPFC7_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC7_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC7_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC7_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC7_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC7_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC7_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC7_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC8 ========================================================= */ + #define R_RMAC0_MPFC8_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC8_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC8_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC8_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC8_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC8_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC8_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC8_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MPFC9 ========================================================= */ + #define R_RMAC0_MPFC9_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC9_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC9_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC9_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC9_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC9_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC9_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC9_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC10 ========================================================= */ + #define R_RMAC0_MPFC10_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC10_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC10_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC10_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC10_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC10_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC10_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC10_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC11 ========================================================= */ + #define R_RMAC0_MPFC11_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC11_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC11_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC11_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC11_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC11_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC11_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC11_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC12 ========================================================= */ + #define R_RMAC0_MPFC12_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC12_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC12_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC12_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC12_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC12_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC12_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC12_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC13 ========================================================= */ + #define R_RMAC0_MPFC13_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC13_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC13_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC13_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC13_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC13_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC13_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC13_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC14 ========================================================= */ + #define R_RMAC0_MPFC14_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC14_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC14_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC14_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC14_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC14_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC14_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC14_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MPFC15 ========================================================= */ + #define R_RMAC0_MPFC15_PFBN_Pos (0UL) /*!< PFBN (Bit 0) */ + #define R_RMAC0_MPFC15_PFBN_Msk (0xffUL) /*!< PFBN (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC15_PFBV_Pos (8UL) /*!< PFBV (Bit 8) */ + #define R_RMAC0_MPFC15_PFBV_Msk (0xff00UL) /*!< PFBV (Bitfield-Mask: 0xff) */ + #define R_RMAC0_MPFC15_TEF0_Pos (16UL) /*!< TEF0 (Bit 16) */ + #define R_RMAC0_MPFC15_TEF0_Msk (0x10000UL) /*!< TEF0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPFC15_TEF1_Pos (17UL) /*!< TEF1 (Bit 17) */ + #define R_RMAC0_MPFC15_TEF1_Msk (0x20000UL) /*!< TEF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= MLVC ========================================================== */ + #define R_RMAC0_MLVC_LVT_Pos (0UL) /*!< LVT (Bit 0) */ + #define R_RMAC0_MLVC_LVT_Msk (0x7fUL) /*!< LVT (Bitfield-Mask: 0x7f) */ + #define R_RMAC0_MLVC_PASE_Pos (8UL) /*!< PASE (Bit 8) */ + #define R_RMAC0_MLVC_PASE_Msk (0x100UL) /*!< PASE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MLVC_PLV_Pos (16UL) /*!< PLV (Bit 16) */ + #define R_RMAC0_MLVC_PLV_Msk (0x10000UL) /*!< PLV (Bitfield-Mask: 0x01) */ +/* ========================================================= MEEEC ========================================================= */ + #define R_RMAC0_MEEEC_LPITR_Pos (0UL) /*!< LPITR (Bit 0) */ + #define R_RMAC0_MEEEC_LPITR_Msk (0x1UL) /*!< LPITR (Bitfield-Mask: 0x01) */ +/* ========================================================= MLBC ========================================================== */ + #define R_RMAC0_MLBC_LBME_Pos (0UL) /*!< LBME (Bit 0) */ + #define R_RMAC0_MLBC_LBME_Msk (0x1UL) /*!< LBME (Bitfield-Mask: 0x01) */ +/* ======================================================== MXGMIIC ======================================================== */ + #define R_RMAC0_MXGMIIC_LFS_TXRFS_Pos (0UL) /*!< LFS_TXRFS (Bit 0) */ + #define R_RMAC0_MXGMIIC_LFS_TXRFS_Msk (0x1UL) /*!< LFS_TXRFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MXGMIIC_LFS_TXIDLE_Pos (1UL) /*!< LFS_TXIDLE (Bit 1) */ + #define R_RMAC0_MXGMIIC_LFS_TXIDLE_Msk (0x2UL) /*!< LFS_TXIDLE (Bitfield-Mask: 0x01) */ +/* ========================================================= MPCH ========================================================== */ + #define R_RMAC0_MPCH_TXPCH_M_Pos (0UL) /*!< TXPCH_M (Bit 0) */ + #define R_RMAC0_MPCH_TXPCH_M_Msk (0x1UL) /*!< TXPCH_M (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_TXPCH_ETYPE_Pos (2UL) /*!< TXPCH_ETYPE (Bit 2) */ + #define R_RMAC0_MPCH_TXPCH_ETYPE_Msk (0xcUL) /*!< TXPCH_ETYPE (Bitfield-Mask: 0x03) */ + #define R_RMAC0_MPCH_TXPCH_PID_Pos (4UL) /*!< TXPCH_PID (Bit 4) */ + #define R_RMAC0_MPCH_TXPCH_PID_Msk (0xf0UL) /*!< TXPCH_PID (Bitfield-Mask: 0x0f) */ + #define R_RMAC0_MPCH_IETPTE_Pos (8UL) /*!< IETPTE (Bit 8) */ + #define R_RMAC0_MPCH_IETPTE_Msk (0x100UL) /*!< IETPTE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_CTPTE_Pos (9UL) /*!< CTPTE (Bit 9) */ + #define R_RMAC0_MPCH_CTPTE_Msk (0x200UL) /*!< CTPTE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_IETRIOD_Pos (10UL) /*!< IETRIOD (Bit 10) */ + #define R_RMAC0_MPCH_IETRIOD_Msk (0x400UL) /*!< IETRIOD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_CTRIOD_Pos (11UL) /*!< CTRIOD (Bit 11) */ + #define R_RMAC0_MPCH_CTRIOD_Msk (0x800UL) /*!< CTRIOD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_RXPCH_TSM_Pos (16UL) /*!< RXPCH_TSM (Bit 16) */ + #define R_RMAC0_MPCH_RXPCH_TSM_Msk (0x10000UL) /*!< RXPCH_TSM (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MPCH_RPHCRCD_Pos (17UL) /*!< RPHCRCD (Bit 17) */ + #define R_RMAC0_MPCH_RPHCRCD_Msk (0x20000UL) /*!< RPHCRCD (Bitfield-Mask: 0x01) */ +/* ========================================================= MANM ========================================================== */ + #define R_RMAC0_MANM_RX_AN_MES_Pos (0UL) /*!< RX_AN_MES (Bit 0) */ + #define R_RMAC0_MANM_RX_AN_MES_Msk (0xffffUL) /*!< RX_AN_MES (Bitfield-Mask: 0xffff) */ +/* ========================================================= MEIS ========================================================== */ + #define R_RMAC0_MEIS_TSLS_Pos (0UL) /*!< TSLS (Bit 0) */ + #define R_RMAC0_MEIS_TSLS_Msk (0x1UL) /*!< TSLS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TIES_Pos (1UL) /*!< TIES (Bit 1) */ + #define R_RMAC0_MEIS_TIES_Msk (0x2UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PRES_Pos (2UL) /*!< PRES (Bit 2) */ + #define R_RMAC0_MEIS_PRES_Msk (0x4UL) /*!< PRES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PFRROS_Pos (3UL) /*!< PFRROS (Bit 3) */ + #define R_RMAC0_MEIS_PFRROS_Msk (0x8UL) /*!< PFRROS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCDS_Pos (4UL) /*!< FCDS (Bit 4) */ + #define R_RMAC0_MEIS_FCDS_Msk (0x10UL) /*!< FCDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TCES_Pos (5UL) /*!< TCES (Bit 5) */ + #define R_RMAC0_MEIS_TCES_Msk (0x20UL) /*!< TCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_TBCIS_Pos (6UL) /*!< TBCIS (Bit 6) */ + #define R_RMAC0_MEIS_TBCIS_Msk (0x40UL) /*!< TBCIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_BFES_Pos (7UL) /*!< BFES (Bit 7) */ + #define R_RMAC0_MEIS_BFES_Msk (0x80UL) /*!< BFES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCES_Pos (8UL) /*!< FCES (Bit 8) */ + #define R_RMAC0_MEIS_FCES_Msk (0x100UL) /*!< FCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_REOES_Pos (9UL) /*!< REOES (Bit 9) */ + #define R_RMAC0_MEIS_REOES_Msk (0x200UL) /*!< REOES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPOES_Pos (10UL) /*!< RPOES (Bit 10) */ + #define R_RMAC0_MEIS_RPOES_Msk (0x400UL) /*!< RPOES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPCRES_Pos (11UL) /*!< RPCRES (Bit 11) */ + #define R_RMAC0_MEIS_RPCRES_Msk (0x800UL) /*!< RPCRES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CTLES0_Pos (12UL) /*!< CTLES0 (Bit 12) */ + #define R_RMAC0_MEIS_CTLES0_Msk (0x1000UL) /*!< CTLES0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CTLES1_Pos (13UL) /*!< CTLES1 (Bit 13) */ + #define R_RMAC0_MEIS_CTLES1_Msk (0x2000UL) /*!< CTLES1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PDES_Pos (20UL) /*!< PDES (Bit 20) */ + #define R_RMAC0_MEIS_PDES_Msk (0x100000UL) /*!< PDES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_PNAES_Pos (21UL) /*!< PNAES (Bit 21) */ + #define R_RMAC0_MEIS_PNAES_Msk (0x200000UL) /*!< PNAES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FCMCES_Pos (22UL) /*!< FCMCES (Bit 22) */ + #define R_RMAC0_MEIS_FCMCES_Msk (0x400000UL) /*!< FCMCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FFMES_Pos (23UL) /*!< FFMES (Bit 23) */ + #define R_RMAC0_MEIS_FFMES_Msk (0x800000UL) /*!< FFMES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_CFCES_Pos (24UL) /*!< CFCES (Bit 24) */ + #define R_RMAC0_MEIS_CFCES_Msk (0x1000000UL) /*!< CFCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FRCES_Pos (25UL) /*!< FRCES (Bit 25) */ + #define R_RMAC0_MEIS_FRCES_Msk (0x2000000UL) /*!< FRCES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_RPOOMS_Pos (26UL) /*!< RPOOMS (Bit 26) */ + #define R_RMAC0_MEIS_RPOOMS_Msk (0x4000000UL) /*!< RPOOMS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FFS_Pos (27UL) /*!< FFS (Bit 27) */ + #define R_RMAC0_MEIS_FFS_Msk (0x8000000UL) /*!< FFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FUES_Pos (28UL) /*!< FUES (Bit 28) */ + #define R_RMAC0_MEIS_FUES_Msk (0x10000000UL) /*!< FUES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIS_FOES_Pos (29UL) /*!< FOES (Bit 29) */ + #define R_RMAC0_MEIS_FOES_Msk (0x20000000UL) /*!< FOES (Bitfield-Mask: 0x01) */ +/* ========================================================= MEIE ========================================================== */ + #define R_RMAC0_MEIE_TSLE_Pos (0UL) /*!< TSLE (Bit 0) */ + #define R_RMAC0_MEIE_TSLE_Msk (0x1UL) /*!< TSLE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TIEE_Pos (1UL) /*!< TIEE (Bit 1) */ + #define R_RMAC0_MEIE_TIEE_Msk (0x2UL) /*!< TIEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PMSEE_Pos (2UL) /*!< PMSEE (Bit 2) */ + #define R_RMAC0_MEIE_PMSEE_Msk (0x4UL) /*!< PMSEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PFRROE_Pos (3UL) /*!< PFRROE (Bit 3) */ + #define R_RMAC0_MEIE_PFRROE_Msk (0x8UL) /*!< PFRROE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCDE_Pos (4UL) /*!< FCDE (Bit 4) */ + #define R_RMAC0_MEIE_FCDE_Msk (0x10UL) /*!< FCDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TCEE_Pos (5UL) /*!< TCEE (Bit 5) */ + #define R_RMAC0_MEIE_TCEE_Msk (0x20UL) /*!< TCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_TBCIE_Pos (6UL) /*!< TBCIE (Bit 6) */ + #define R_RMAC0_MEIE_TBCIE_Msk (0x40UL) /*!< TBCIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_BFEE_Pos (7UL) /*!< BFEE (Bit 7) */ + #define R_RMAC0_MEIE_BFEE_Msk (0x80UL) /*!< BFEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCEE_Pos (8UL) /*!< FCEE (Bit 8) */ + #define R_RMAC0_MEIE_FCEE_Msk (0x100UL) /*!< FCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_REOEE_Pos (9UL) /*!< REOEE (Bit 9) */ + #define R_RMAC0_MEIE_REOEE_Msk (0x200UL) /*!< REOEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPOEE_Pos (10UL) /*!< RPOEE (Bit 10) */ + #define R_RMAC0_MEIE_RPOEE_Msk (0x400UL) /*!< RPOEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPCREE_Pos (11UL) /*!< RPCREE (Bit 11) */ + #define R_RMAC0_MEIE_RPCREE_Msk (0x800UL) /*!< RPCREE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CTLEE0_Pos (12UL) /*!< CTLEE0 (Bit 12) */ + #define R_RMAC0_MEIE_CTLEE0_Msk (0x1000UL) /*!< CTLEE0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CTLEE1_Pos (13UL) /*!< CTLEE1 (Bit 13) */ + #define R_RMAC0_MEIE_CTLEE1_Msk (0x2000UL) /*!< CTLEE1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PDEE_Pos (20UL) /*!< PDEE (Bit 20) */ + #define R_RMAC0_MEIE_PDEE_Msk (0x100000UL) /*!< PDEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_PNAEE_Pos (21UL) /*!< PNAEE (Bit 21) */ + #define R_RMAC0_MEIE_PNAEE_Msk (0x200000UL) /*!< PNAEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FCMCEE_Pos (22UL) /*!< FCMCEE (Bit 22) */ + #define R_RMAC0_MEIE_FCMCEE_Msk (0x400000UL) /*!< FCMCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FFMEE_Pos (23UL) /*!< FFMEE (Bit 23) */ + #define R_RMAC0_MEIE_FFMEE_Msk (0x800000UL) /*!< FFMEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_CFCEE_Pos (24UL) /*!< CFCEE (Bit 24) */ + #define R_RMAC0_MEIE_CFCEE_Msk (0x1000000UL) /*!< CFCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FRCEE_Pos (25UL) /*!< FRCEE (Bit 25) */ + #define R_RMAC0_MEIE_FRCEE_Msk (0x2000000UL) /*!< FRCEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_RPOOME_Pos (26UL) /*!< RPOOME (Bit 26) */ + #define R_RMAC0_MEIE_RPOOME_Msk (0x4000000UL) /*!< RPOOME (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FFE_Pos (27UL) /*!< FFE (Bit 27) */ + #define R_RMAC0_MEIE_FFE_Msk (0x8000000UL) /*!< FFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FUEE_Pos (28UL) /*!< FUEE (Bit 28) */ + #define R_RMAC0_MEIE_FUEE_Msk (0x10000000UL) /*!< FUEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEIE_FOEE_Pos (29UL) /*!< FOEE (Bit 29) */ + #define R_RMAC0_MEIE_FOEE_Msk (0x20000000UL) /*!< FOEE (Bitfield-Mask: 0x01) */ +/* ========================================================= MEID ========================================================== */ + #define R_RMAC0_MEID_TSLD_Pos (0UL) /*!< TSLD (Bit 0) */ + #define R_RMAC0_MEID_TSLD_Msk (0x1UL) /*!< TSLD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TIED_Pos (1UL) /*!< TIED (Bit 1) */ + #define R_RMAC0_MEID_TIED_Msk (0x2UL) /*!< TIED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PRED_Pos (2UL) /*!< PRED (Bit 2) */ + #define R_RMAC0_MEID_PRED_Msk (0x4UL) /*!< PRED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PFRROD_Pos (3UL) /*!< PFRROD (Bit 3) */ + #define R_RMAC0_MEID_PFRROD_Msk (0x8UL) /*!< PFRROD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCDD_Pos (4UL) /*!< FCDD (Bit 4) */ + #define R_RMAC0_MEID_FCDD_Msk (0x10UL) /*!< FCDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TCED_Pos (5UL) /*!< TCED (Bit 5) */ + #define R_RMAC0_MEID_TCED_Msk (0x20UL) /*!< TCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_TBCID_Pos (6UL) /*!< TBCID (Bit 6) */ + #define R_RMAC0_MEID_TBCID_Msk (0x40UL) /*!< TBCID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_BFED_Pos (7UL) /*!< BFED (Bit 7) */ + #define R_RMAC0_MEID_BFED_Msk (0x80UL) /*!< BFED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCED_Pos (8UL) /*!< FCED (Bit 8) */ + #define R_RMAC0_MEID_FCED_Msk (0x100UL) /*!< FCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_REOED_Pos (9UL) /*!< REOED (Bit 9) */ + #define R_RMAC0_MEID_REOED_Msk (0x200UL) /*!< REOED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPOED_Pos (10UL) /*!< RPOED (Bit 10) */ + #define R_RMAC0_MEID_RPOED_Msk (0x400UL) /*!< RPOED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPCRED_Pos (11UL) /*!< RPCRED (Bit 11) */ + #define R_RMAC0_MEID_RPCRED_Msk (0x800UL) /*!< RPCRED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CTLED0_Pos (12UL) /*!< CTLED0 (Bit 12) */ + #define R_RMAC0_MEID_CTLED0_Msk (0x1000UL) /*!< CTLED0 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CTLED1_Pos (13UL) /*!< CTLED1 (Bit 13) */ + #define R_RMAC0_MEID_CTLED1_Msk (0x2000UL) /*!< CTLED1 (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PDED_Pos (20UL) /*!< PDED (Bit 20) */ + #define R_RMAC0_MEID_PDED_Msk (0x100000UL) /*!< PDED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_PNAED_Pos (21UL) /*!< PNAED (Bit 21) */ + #define R_RMAC0_MEID_PNAED_Msk (0x200000UL) /*!< PNAED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FCMCED_Pos (22UL) /*!< FCMCED (Bit 22) */ + #define R_RMAC0_MEID_FCMCED_Msk (0x400000UL) /*!< FCMCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FFMED_Pos (23UL) /*!< FFMED (Bit 23) */ + #define R_RMAC0_MEID_FFMED_Msk (0x800000UL) /*!< FFMED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_CFCED_Pos (24UL) /*!< CFCED (Bit 24) */ + #define R_RMAC0_MEID_CFCED_Msk (0x1000000UL) /*!< CFCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FRCED_Pos (25UL) /*!< FRCED (Bit 25) */ + #define R_RMAC0_MEID_FRCED_Msk (0x2000000UL) /*!< FRCED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_RPOOMD_Pos (26UL) /*!< RPOOMD (Bit 26) */ + #define R_RMAC0_MEID_RPOOMD_Msk (0x4000000UL) /*!< RPOOMD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FFD_Pos (27UL) /*!< FFD (Bit 27) */ + #define R_RMAC0_MEID_FFD_Msk (0x8000000UL) /*!< FFD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FUED_Pos (28UL) /*!< FUED (Bit 28) */ + #define R_RMAC0_MEID_FUED_Msk (0x10000000UL) /*!< FUED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MEID_FOED_Pos (29UL) /*!< FOED (Bit 29) */ + #define R_RMAC0_MEID_FOED_Msk (0x20000000UL) /*!< FOED (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS0 ========================================================= */ + #define R_RMAC0_MMIS0_PLSCS_Pos (0UL) /*!< PLSCS (Bit 0) */ + #define R_RMAC0_MMIS0_PLSCS_Msk (0x1UL) /*!< PLSCS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_PIDS_Pos (1UL) /*!< PIDS (Bit 1) */ + #define R_RMAC0_MMIS0_PIDS_Msk (0x2UL) /*!< PIDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_LVSS_Pos (2UL) /*!< LVSS (Bit 2) */ + #define R_RMAC0_MMIS0_LVSS_Msk (0x4UL) /*!< LVSS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_LVFS_Pos (3UL) /*!< LVFS (Bit 3) */ + #define R_RMAC0_MMIS0_LVFS_Msk (0x8UL) /*!< LVFS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_VFRS_Pos (4UL) /*!< VFRS (Bit 4) */ + #define R_RMAC0_MMIS0_VFRS_Msk (0x10UL) /*!< VFRS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_ANDETS_Pos (6UL) /*!< ANDETS (Bit 6) */ + #define R_RMAC0_MMIS0_ANDETS_Msk (0x40UL) /*!< ANDETS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFDS_Pos (8UL) /*!< XLFDS (Bit 8) */ + #define R_RMAC0_MMIS0_XLFDS_Msk (0x100UL) /*!< XLFDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFES_Pos (9UL) /*!< XLFES (Bit 9) */ + #define R_RMAC0_MMIS0_XLFES_Msk (0x200UL) /*!< XLFES (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLFSDS_Pos (10UL) /*!< XLFSDS (Bit 10) */ + #define R_RMAC0_MMIS0_XLFSDS_Msk (0x400UL) /*!< XLFSDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XRFSDS_Pos (11UL) /*!< XRFSDS (Bit 11) */ + #define R_RMAC0_MMIS0_XRFSDS_Msk (0x800UL) /*!< XRFSDS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS0_XLISDS_Pos (12UL) /*!< XLISDS (Bit 12) */ + #define R_RMAC0_MMIS0_XLISDS_Msk (0x1000UL) /*!< XLISDS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE0 ========================================================= */ + #define R_RMAC0_MMIE0_PLSCE_Pos (0UL) /*!< PLSCE (Bit 0) */ + #define R_RMAC0_MMIE0_PLSCE_Msk (0x1UL) /*!< PLSCE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_PIDE_Pos (1UL) /*!< PIDE (Bit 1) */ + #define R_RMAC0_MMIE0_PIDE_Msk (0x2UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_LVSE_Pos (2UL) /*!< LVSE (Bit 2) */ + #define R_RMAC0_MMIE0_LVSE_Msk (0x4UL) /*!< LVSE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_LVFE_Pos (3UL) /*!< LVFE (Bit 3) */ + #define R_RMAC0_MMIE0_LVFE_Msk (0x8UL) /*!< LVFE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_VFRE_Pos (4UL) /*!< VFRE (Bit 4) */ + #define R_RMAC0_MMIE0_VFRE_Msk (0x10UL) /*!< VFRE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_ANDETE_Pos (6UL) /*!< ANDETE (Bit 6) */ + #define R_RMAC0_MMIE0_ANDETE_Msk (0x40UL) /*!< ANDETE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFDE_Pos (8UL) /*!< XLFDE (Bit 8) */ + #define R_RMAC0_MMIE0_XLFDE_Msk (0x100UL) /*!< XLFDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFEE_Pos (9UL) /*!< XLFEE (Bit 9) */ + #define R_RMAC0_MMIE0_XLFEE_Msk (0x200UL) /*!< XLFEE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLFSDE_Pos (10UL) /*!< XLFSDE (Bit 10) */ + #define R_RMAC0_MMIE0_XLFSDE_Msk (0x400UL) /*!< XLFSDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XRFSDE_Pos (11UL) /*!< XRFSDE (Bit 11) */ + #define R_RMAC0_MMIE0_XRFSDE_Msk (0x800UL) /*!< XRFSDE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE0_XLISDE_Pos (12UL) /*!< XLISDE (Bit 12) */ + #define R_RMAC0_MMIE0_XLISDE_Msk (0x1000UL) /*!< XLISDE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID0 ========================================================= */ + #define R_RMAC0_MMID0_PLSCD_Pos (0UL) /*!< PLSCD (Bit 0) */ + #define R_RMAC0_MMID0_PLSCD_Msk (0x1UL) /*!< PLSCD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_PIDD_Pos (1UL) /*!< PIDD (Bit 1) */ + #define R_RMAC0_MMID0_PIDD_Msk (0x2UL) /*!< PIDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_LVSD_Pos (2UL) /*!< LVSD (Bit 2) */ + #define R_RMAC0_MMID0_LVSD_Msk (0x4UL) /*!< LVSD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_LVFD_Pos (3UL) /*!< LVFD (Bit 3) */ + #define R_RMAC0_MMID0_LVFD_Msk (0x8UL) /*!< LVFD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_VFRD_Pos (4UL) /*!< VFRD (Bit 4) */ + #define R_RMAC0_MMID0_VFRD_Msk (0x10UL) /*!< VFRD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_ANDETD_Pos (6UL) /*!< ANDETD (Bit 6) */ + #define R_RMAC0_MMID0_ANDETD_Msk (0x40UL) /*!< ANDETD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFDD_Pos (8UL) /*!< XLFDD (Bit 8) */ + #define R_RMAC0_MMID0_XLFDD_Msk (0x100UL) /*!< XLFDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFED_Pos (9UL) /*!< XLFED (Bit 9) */ + #define R_RMAC0_MMID0_XLFED_Msk (0x200UL) /*!< XLFED (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLFSDD_Pos (10UL) /*!< XLFSDD (Bit 10) */ + #define R_RMAC0_MMID0_XLFSDD_Msk (0x400UL) /*!< XLFSDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XRFSDD_Pos (11UL) /*!< XRFSDD (Bit 11) */ + #define R_RMAC0_MMID0_XRFSDD_Msk (0x800UL) /*!< XRFSDD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID0_XLISDD_Pos (12UL) /*!< XLISDD (Bit 12) */ + #define R_RMAC0_MMID0_XLISDD_Msk (0x1000UL) /*!< XLISDD (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS1 ========================================================= */ + #define R_RMAC0_MMIS1_PRACS_Pos (0UL) /*!< PRACS (Bit 0) */ + #define R_RMAC0_MMIS1_PRACS_Msk (0x1UL) /*!< PRACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PWACS_Pos (1UL) /*!< PWACS (Bit 1) */ + #define R_RMAC0_MMIS1_PWACS_Msk (0x2UL) /*!< PWACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PAACS_Pos (2UL) /*!< PAACS (Bit 2) */ + #define R_RMAC0_MMIS1_PAACS_Msk (0x4UL) /*!< PAACS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS1_PPRACS_Pos (3UL) /*!< PPRACS (Bit 3) */ + #define R_RMAC0_MMIS1_PPRACS_Msk (0x8UL) /*!< PPRACS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE1 ========================================================= */ + #define R_RMAC0_MMIE1_PRACE_Pos (0UL) /*!< PRACE (Bit 0) */ + #define R_RMAC0_MMIE1_PRACE_Msk (0x1UL) /*!< PRACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PWACE_Pos (1UL) /*!< PWACE (Bit 1) */ + #define R_RMAC0_MMIE1_PWACE_Msk (0x2UL) /*!< PWACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PAACE_Pos (2UL) /*!< PAACE (Bit 2) */ + #define R_RMAC0_MMIE1_PAACE_Msk (0x4UL) /*!< PAACE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE1_PPRACE_Pos (3UL) /*!< PPRACE (Bit 3) */ + #define R_RMAC0_MMIE1_PPRACE_Msk (0x8UL) /*!< PPRACE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID1 ========================================================= */ + #define R_RMAC0_MMID1_PRACD_Pos (0UL) /*!< PRACD (Bit 0) */ + #define R_RMAC0_MMID1_PRACD_Msk (0x1UL) /*!< PRACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PWACD_Pos (1UL) /*!< PWACD (Bit 1) */ + #define R_RMAC0_MMID1_PWACD_Msk (0x2UL) /*!< PWACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PAACD_Pos (2UL) /*!< PAACD (Bit 2) */ + #define R_RMAC0_MMID1_PAACD_Msk (0x4UL) /*!< PAACD (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID1_PPRACD_Pos (3UL) /*!< PPRACD (Bit 3) */ + #define R_RMAC0_MMID1_PPRACD_Msk (0x8UL) /*!< PPRACD (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIS2 ========================================================= */ + #define R_RMAC0_MMIS2_MPDIS_Pos (0UL) /*!< MPDIS (Bit 0) */ + #define R_RMAC0_MMIS2_MPDIS_Msk (0x1UL) /*!< MPDIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS2_LPIAIS_Pos (1UL) /*!< LPIAIS (Bit 1) */ + #define R_RMAC0_MMIS2_LPIAIS_Msk (0x2UL) /*!< LPIAIS (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIS2_LPIDIS_Pos (2UL) /*!< LPIDIS (Bit 2) */ + #define R_RMAC0_MMIS2_LPIDIS_Msk (0x4UL) /*!< LPIDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= MMIE2 ========================================================= */ + #define R_RMAC0_MMIE2_MPDIE_Pos (0UL) /*!< MPDIE (Bit 0) */ + #define R_RMAC0_MMIE2_MPDIE_Msk (0x1UL) /*!< MPDIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE2_LPIAIE_Pos (1UL) /*!< LPIAIE (Bit 1) */ + #define R_RMAC0_MMIE2_LPIAIE_Msk (0x2UL) /*!< LPIAIE (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMIE2_LPIDIE_Pos (2UL) /*!< LPIDIE (Bit 2) */ + #define R_RMAC0_MMIE2_LPIDIE_Msk (0x4UL) /*!< LPIDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= MMID2 ========================================================= */ + #define R_RMAC0_MMID2_MPDID_Pos (0UL) /*!< MPDID (Bit 0) */ + #define R_RMAC0_MMID2_MPDID_Msk (0x1UL) /*!< MPDID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID2_LPIAID_Pos (1UL) /*!< LPIAID (Bit 1) */ + #define R_RMAC0_MMID2_LPIAID_Msk (0x2UL) /*!< LPIAID (Bitfield-Mask: 0x01) */ + #define R_RMAC0_MMID2_LPIDID_Pos (2UL) /*!< LPIDID (Bit 2) */ + #define R_RMAC0_MMID2_LPIDID_Msk (0x4UL) /*!< LPIDID (Bitfield-Mask: 0x01) */ +/* ======================================================== MMPFTCT ======================================================== */ + #define R_RMAC0_MMPFTCT_MPFTC_Pos (0UL) /*!< MPFTC (Bit 0) */ + #define R_RMAC0_MMPFTCT_MPFTC_Msk (0xffffUL) /*!< MPFTC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MAPFTCT ======================================================== */ + #define R_RMAC0_MAPFTCT_APFTC_Pos (0UL) /*!< APFTC (Bit 0) */ + #define R_RMAC0_MAPFTCT_APFTC_Msk (0xffffUL) /*!< APFTC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MPFRCT ========================================================= */ + #define R_RMAC0_MPFRCT_PFRC_Pos (0UL) /*!< PFRC (Bit 0) */ + #define R_RMAC0_MPFRCT_PFRC_Msk (0xffffUL) /*!< PFRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MFCICT ========================================================= */ + #define R_RMAC0_MFCICT_FCIC_Pos (0UL) /*!< FCIC (Bit 0) */ + #define R_RMAC0_MFCICT_FCIC_Msk (0xffffUL) /*!< FCIC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MEEECT ========================================================= */ + #define R_RMAC0_MEEECT_EEERC_Pos (0UL) /*!< EEERC (Bit 0) */ + #define R_RMAC0_MEEECT_EEERC_Msk (0xffffUL) /*!< EEERC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MMPCFTCT0 ======================================================= */ + #define R_RMAC0_MMPCFTCT0_MPCFCTC_Pos (0UL) /*!< MPCFCTC (Bit 0) */ + #define R_RMAC0_MMPCFTCT0_MPCFCTC_Msk (0xffffUL) /*!< MPCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MMPCFTCT1 ======================================================= */ + #define R_RMAC0_MMPCFTCT1_MPCFCTC_Pos (0UL) /*!< MPCFCTC (Bit 0) */ + #define R_RMAC0_MMPCFTCT1_MPCFCTC_Msk (0xffffUL) /*!< MPCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MAPCFTCT0 ======================================================= */ + #define R_RMAC0_MAPCFTCT0_APCFCTC_Pos (0UL) /*!< APCFCTC (Bit 0) */ + #define R_RMAC0_MAPCFTCT0_APCFCTC_Msk (0xffffUL) /*!< APCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MAPCFTCT1 ======================================================= */ + #define R_RMAC0_MAPCFTCT1_APCFCTC_Pos (0UL) /*!< APCFCTC (Bit 0) */ + #define R_RMAC0_MAPCFTCT1_APCFCTC_Msk (0xffffUL) /*!< APCFCTC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT0 ======================================================== */ + #define R_RMAC0_MPCFRCT0_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT0_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT1 ======================================================== */ + #define R_RMAC0_MPCFRCT1_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT1_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT2 ======================================================== */ + #define R_RMAC0_MPCFRCT2_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT2_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT3 ======================================================== */ + #define R_RMAC0_MPCFRCT3_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT3_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT4 ======================================================== */ + #define R_RMAC0_MPCFRCT4_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT4_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT5 ======================================================== */ + #define R_RMAC0_MPCFRCT5_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT5_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT6 ======================================================== */ + #define R_RMAC0_MPCFRCT6_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT6_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================= MPCFRCT7 ======================================================== */ + #define R_RMAC0_MPCFRCT7_PCFCRC_Pos (0UL) /*!< PCFCRC (Bit 0) */ + #define R_RMAC0_MPCFRCT7_PCFCRC_Msk (0xffffUL) /*!< PCFCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MROVFC ========================================================= */ + #define R_RMAC0_MROVFC_ROVFC_Pos (0UL) /*!< ROVFC (Bit 0) */ + #define R_RMAC0_MROVFC_ROVFC_Msk (0xffffffffUL) /*!< ROVFC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MRHCRCEC ======================================================== */ + #define R_RMAC0_MRHCRCEC_RHCRCEC_Pos (0UL) /*!< RHCRCEC (Bit 0) */ + #define R_RMAC0_MRHCRCEC_RHCRCEC_Msk (0xffffUL) /*!< RHCRCEC (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRGFCE ========================================================= */ + #define R_RMAC0_MRGFCE_RGFNE_Pos (0UL) /*!< RGFNE (Bit 0) */ + #define R_RMAC0_MRGFCE_RGFNE_Msk (0xffffffffUL) /*!< RGFNE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGFCP ========================================================= */ + #define R_RMAC0_MRGFCP_RGFNP_Pos (0UL) /*!< RGFNP (Bit 0) */ + #define R_RMAC0_MRGFCP_RGFNP_Msk (0xffffffffUL) /*!< RGFNP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRBFC ========================================================= */ + #define R_RMAC0_MRBFC_RBFN_Pos (0UL) /*!< RBFN (Bit 0) */ + #define R_RMAC0_MRBFC_RBFN_Msk (0xffffffffUL) /*!< RBFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRMFC ========================================================= */ + #define R_RMAC0_MRMFC_RMFN_Pos (0UL) /*!< RMFN (Bit 0) */ + #define R_RMAC0_MRMFC_RMFN_Msk (0xffffffffUL) /*!< RMFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MRUFC ========================================================= */ + #define R_RMAC0_MRUFC_RUFN_Pos (0UL) /*!< RUFN (Bit 0) */ + #define R_RMAC0_MRUFC_RUFN_Msk (0xffffffffUL) /*!< RUFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRPEFC ========================================================= */ + #define R_RMAC0_MRPEFC_RPEFN_Pos (0UL) /*!< RPEFN (Bit 0) */ + #define R_RMAC0_MRPEFC_RPEFN_Msk (0xffffUL) /*!< RPEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRNEFC ========================================================= */ + #define R_RMAC0_MRNEFC_RNEFN_Pos (0UL) /*!< RNEFN (Bit 0) */ + #define R_RMAC0_MRNEFC_RNEFN_Msk (0xffffUL) /*!< RNEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFMEFC ======================================================== */ + #define R_RMAC0_MRFMEFC_RFMEFN_Pos (0UL) /*!< RFMEFN (Bit 0) */ + #define R_RMAC0_MRFMEFC_RFMEFN_Msk (0xffffffffUL) /*!< RFMEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MRFFMEFC ======================================================== */ + #define R_RMAC0_MRFFMEFC_RFFMEFN_Pos (0UL) /*!< RFFMEFN (Bit 0) */ + #define R_RMAC0_MRFFMEFC_RFFMEFN_Msk (0xffffUL) /*!< RFFMEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================= MRCFCEFC ======================================================== */ + #define R_RMAC0_MRCFCEFC_RCFCEFN_Pos (0UL) /*!< RCFCEFN (Bit 0) */ + #define R_RMAC0_MRCFCEFC_RCFCEFN_Msk (0xffffUL) /*!< RCFCEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MRFCEFC ======================================================== */ + #define R_RMAC0_MRFCEFC_RFCEFN_Pos (0UL) /*!< RFCEFN (Bit 0) */ + #define R_RMAC0_MRFCEFC_RFCEFN_Msk (0xffffUL) /*!< RFCEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================= MRRCFEFC ======================================================== */ + #define R_RMAC0_MRRCFEFC_RRCFEFN_Pos (0UL) /*!< RRCFEFN (Bit 0) */ + #define R_RMAC0_MRRCFEFC_RRCFEFN_Msk (0xffffUL) /*!< RRCFEFN (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRFC ========================================================== */ + #define R_RMAC0_MRFC_RFN_Pos (0UL) /*!< RFN (Bit 0) */ + #define R_RMAC0_MRFC_RFN_Msk (0xffffffffUL) /*!< RFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGUEFC ======================================================== */ + #define R_RMAC0_MRGUEFC_RUEFN_Pos (0UL) /*!< RUEFN (Bit 0) */ + #define R_RMAC0_MRGUEFC_RUEFN_Msk (0xffffffffUL) /*!< RUEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRBUEFC ======================================================== */ + #define R_RMAC0_MRBUEFC_RUEFN_Pos (0UL) /*!< RUEFN (Bit 0) */ + #define R_RMAC0_MRBUEFC_RUEFN_Msk (0xffffffffUL) /*!< RUEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRGOEFC ======================================================== */ + #define R_RMAC0_MRGOEFC_RGOEFN_Pos (0UL) /*!< RGOEFN (Bit 0) */ + #define R_RMAC0_MRGOEFC_RGOEFN_Msk (0xffffffffUL) /*!< RGOEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRBOEFC ======================================================== */ + #define R_RMAC0_MRBOEFC_RBOEFN_Pos (0UL) /*!< RBOEFN (Bit 0) */ + #define R_RMAC0_MRBOEFC_RBOEFN_Msk (0xffffffffUL) /*!< RBOEFN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCEU ======================================================== */ + #define R_RMAC0_MRXBCEU_RBNEU_Pos (0UL) /*!< RBNEU (Bit 0) */ + #define R_RMAC0_MRXBCEU_RBNEU_Msk (0xffffffffUL) /*!< RBNEU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCEL ======================================================== */ + #define R_RMAC0_MRXBCEL_RBNEL_Pos (0UL) /*!< RBNEL (Bit 0) */ + #define R_RMAC0_MRXBCEL_RBNEL_Msk (0xffffffffUL) /*!< RBNEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCPU ======================================================== */ + #define R_RMAC0_MRXBCPU_RBNPU_Pos (0UL) /*!< RBNPU (Bit 0) */ + #define R_RMAC0_MRXBCPU_RBNPU_Msk (0xffffffffUL) /*!< RBNPU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRXBCPL ======================================================== */ + #define R_RMAC0_MRXBCPL_RBNPL_Pos (0UL) /*!< RBNPL (Bit 0) */ + #define R_RMAC0_MRXBCPL_RBNPL_Msk (0xffffffffUL) /*!< RBNPL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTGFCE ========================================================= */ + #define R_RMAC0_MTGFCE_TGFNE_Pos (0UL) /*!< TGFNE (Bit 0) */ + #define R_RMAC0_MTGFCE_TGFNE_Msk (0xffffffffUL) /*!< TGFNE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTGFCP ========================================================= */ + #define R_RMAC0_MTGFCP_TGFNP_Pos (0UL) /*!< TGFNP (Bit 0) */ + #define R_RMAC0_MTGFCP_TGFNP_Msk (0xffffffffUL) /*!< TGFNP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTBFC ========================================================= */ + #define R_RMAC0_MTBFC_TBFN_Pos (0UL) /*!< TBFN (Bit 0) */ + #define R_RMAC0_MTBFC_TBFN_Msk (0xffffffffUL) /*!< TBFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTMFC ========================================================= */ + #define R_RMAC0_MTMFC_TMFN_Pos (0UL) /*!< TMFN (Bit 0) */ + #define R_RMAC0_MTMFC_TMFN_Msk (0xffffffffUL) /*!< TMFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTUFC ========================================================= */ + #define R_RMAC0_MTUFC_TUFN_Pos (0UL) /*!< TUFN (Bit 0) */ + #define R_RMAC0_MTUFC_TUFN_Msk (0xffffffffUL) /*!< TUFN (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTEFC ========================================================= */ + #define R_RMAC0_MTEFC_TEFN_Pos (0UL) /*!< TEFN (Bit 0) */ + #define R_RMAC0_MTEFC_TEFN_Msk (0xffffUL) /*!< TEFN (Bitfield-Mask: 0xffff) */ +/* ======================================================== MTXBCEU ======================================================== */ + #define R_RMAC0_MTXBCEU_TBNEU_Pos (0UL) /*!< TBNEU (Bit 0) */ + #define R_RMAC0_MTXBCEU_TBNEU_Msk (0xffffffffUL) /*!< TBNEU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCEL ======================================================== */ + #define R_RMAC0_MTXBCEL_TBNEL_Pos (0UL) /*!< TBNEL (Bit 0) */ + #define R_RMAC0_MTXBCEL_TBNEL_Msk (0xffffffffUL) /*!< TBNEL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCPU ======================================================== */ + #define R_RMAC0_MTXBCPU_TBNPU_Pos (0UL) /*!< TBNPU (Bit 0) */ + #define R_RMAC0_MTXBCPU_TBNPU_Msk (0xffffffffUL) /*!< TBNPU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTXBCPL ======================================================== */ + #define R_RMAC0_MTXBCPL_TBNPL_Pos (0UL) /*!< TBNPL (Bit 0) */ + #define R_RMAC0_MTXBCPL_TBNPL_Msk (0xffffffffUL) /*!< TBNPL (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TCM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= TCMPRCR_S ======================================================= */ + #define R_TCM_TCMPRCR_S_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_TCM_TCMPRCR_S_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMPRCR_S_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_TCM_TCMPRCR_S_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ====================================================== TCMPRCR_NS ======================================================= */ + #define R_TCM_TCMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_TCM_TCMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */ + #define R_TCM_TCMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */ +/* ======================================================== TCMCRC ========================================================= */ + #define R_TCM_TCMCRC_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TCM_TCMCRC_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRC_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_TCM_TCMCRC_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_TCM_TCMCRC_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_TCM_TCMCRC_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRC_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_TCM_TCMCRC_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMCRS ========================================================= */ + #define R_TCM_TCMCRS_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TCM_TCMCRS_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRS_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */ + #define R_TCM_TCMCRS_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ + #define R_TCM_TCMCRS_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */ + #define R_TCM_TCMCRS_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMCRS_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */ + #define R_TCM_TCMCRS_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== TCMESR ========================================================= */ + #define R_TCM_TCMESR_ERRC0_Pos (0UL) /*!< ERRC0 (Bit 0) */ + #define R_TCM_TCMESR_ERRC0_Msk (0x1UL) /*!< ERRC0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRC1_Pos (1UL) /*!< ERRC1 (Bit 1) */ + #define R_TCM_TCMESR_ERRC1_Msk (0x2UL) /*!< ERRC1 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRS0_Pos (2UL) /*!< ERRS0 (Bit 2) */ + #define R_TCM_TCMESR_ERRS0_Msk (0x4UL) /*!< ERRS0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESR_ERRS1_Pos (3UL) /*!< ERRS1 (Bit 3) */ + #define R_TCM_TCMESR_ERRS1_Msk (0x8UL) /*!< ERRS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMESCLR ======================================================== */ + #define R_TCM_TCMESCLR_CLRC0_Pos (0UL) /*!< CLRC0 (Bit 0) */ + #define R_TCM_TCMESCLR_CLRC0_Msk (0x1UL) /*!< CLRC0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRC1_Pos (1UL) /*!< CLRC1 (Bit 1) */ + #define R_TCM_TCMESCLR_CLRC1_Msk (0x2UL) /*!< CLRC1 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRS0_Pos (2UL) /*!< CLRS0 (Bit 2) */ + #define R_TCM_TCMESCLR_CLRS0_Msk (0x4UL) /*!< CLRS0 (Bitfield-Mask: 0x01) */ + #define R_TCM_TCMESCLR_CLRS1_Pos (3UL) /*!< CLRS1 (Bit 3) */ + #define R_TCM_TCMESCLR_CLRS1_Msk (0x8UL) /*!< CLRS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= TCMEARC0 ======================================================== */ + #define R_TCM_TCMEARC0_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARC0_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARC1 ======================================================== */ + #define R_TCM_TCMEARC1_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARC1_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARS0 ======================================================== */ + #define R_TCM_TCMEARS0_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARS0_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ +/* ======================================================= TCMEARS1 ======================================================== */ + #define R_TCM_TCMEARS1_EAR_Pos (2UL) /*!< EAR (Bit 2) */ + #define R_TCM_TCMEARS1_EAR_Msk (0x3fffcUL) /*!< EAR (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7KA8P1KF_CORE1_H */ + +/** @} */ /* End of group R7KA8P1KF_core1 */ + +/** @} */ /* End of group Renesas */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 0000000000..c424780f8b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,198 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup RA + * @{ + */ + +#ifndef RA_H + #define RA_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include "cmsis_compiler.h" + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if BSP_MCU_GROUP_RA0E1 + #include "R7FA0E107.h" + #elif BSP_MCU_GROUP_RA0E2 + #include "R7FA0E209.h" + #elif BSP_MCU_GROUP_RA0L1 + #include "R7FA0L107.h" + #elif BSP_MCU_GROUP_RA2A1 + #include "R7FA2A1AB.h" + #elif BSP_MCU_GROUP_RA2A2 + #include "R7FA2A2AD.h" + #elif BSP_MCU_GROUP_RA2E1 + #include "R7FA2E1A9.h" + #elif BSP_MCU_GROUP_RA2E2 + #include "R7FA2E2A7.h" + #elif BSP_MCU_GROUP_RA2E3 + #include "R7FA2E307.h" + #elif BSP_MCU_GROUP_RA2L1 + #include "R7FA2L1AB.h" + #elif BSP_MCU_GROUP_RA2L2 + #include "R7FA2L209.h" + #elif BSP_MCU_GROUP_RA2T1 + #include "R7FA2T107.h" + #elif BSP_MCU_GROUP_RA4C1 + #include "R7FA4C1BD.h" + #elif BSP_MCU_GROUP_RA4E1 + #include "R7FA4E10D.h" + #elif BSP_MCU_GROUP_RA4E2 + #include "R7FA4E2B9.h" + #elif BSP_MCU_GROUP_RA4M1 + #include "R7FA4M1AB.h" + #elif BSP_MCU_GROUP_RA4M2 + #include "R7FA4M2AD.h" + #elif BSP_MCU_GROUP_RA4M3 + #include "R7FA4M3AF.h" + #elif BSP_MCU_GROUP_RA4T1 + #include "R7FA4T1BB.h" + #elif BSP_MCU_GROUP_RA4W1 + #include "R7FA4W1AD.h" + #elif BSP_MCU_GROUP_RA4L1 + #include "R7FA4L1BD.h" + #elif BSP_MCU_GROUP_RA6E1 + #include "R7FA6E10F.h" + #elif BSP_MCU_GROUP_RA6E2 + #include "R7FA6E2BB.h" + #elif BSP_MCU_GROUP_RA6M1 + #include "R7FA6M1AD.h" + #elif BSP_MCU_GROUP_RA6M2 + #include "R7FA6M2AF.h" + #elif BSP_MCU_GROUP_RA6M3 + #include "R7FA6M3AH.h" + #elif BSP_MCU_GROUP_RA6M4 + #include "R7FA6M4AF.h" + #elif BSP_MCU_GROUP_RA6M5 + #include "R7FA6M5BH.h" + #elif BSP_MCU_GROUP_RA6T1 + #include "R7FA6T1AD.h" + #elif BSP_MCU_GROUP_RA6T2 + #include "R7FA6T2BD.h" + #elif BSP_MCU_GROUP_RA6T3 + #include "R7FA6T3BB.h" + #elif BSP_MCU_GROUP_RA8D1 + #include "R7FA8D1BH.h" + #elif BSP_MCU_GROUP_RA8E1 + #include "R7FA8E1AF.h" + #elif BSP_MCU_GROUP_RA8E2 + #include "R7FA8E2AF.h" + #elif BSP_MCU_GROUP_RA8M1 + #include "R7FA8M1AH.h" + #elif BSP_MCU_GROUP_RA8P1 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8P1KF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8P1KF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA8T1 + #include "R7FA8T1AH.h" + #elif BSP_MCU_GROUP_RA8T2 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8T2LF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8T2LF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA8M2 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8M2JF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8M2JF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #elif BSP_MCU_GROUP_RA8D2 + #if 0U == BSP_CFG_CPU_CORE + #include "R7KA8D2KF_core0.h" + #elif 1U == BSP_CFG_CPU_CORE + #include "R7KA8D2KF_core1.h" + #else + #warning "Unsupported CPU number" + #endif + #else + #if __has_include("renesas_internal.h") + #include "renesas_internal.h" + #else + #warning "Unsupported MCU" + #endif + #endif + +/* + * ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB + * macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85 + * and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85: + * + * | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ | + * |-----------|------------|------------------------| + * | GCC | 8 | __ARM_ARCH_8M_MAIN__ | + * | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ | + * | IAR | 801 | __ARM_ARCH_8M_MAIN__ | + * + * The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__ + * + * IAR is currently the only toolchain producing the correct __ARM_ARCH value. + * + *- See https://github.com/ARM-software/CMSIS_6/issues/159 + */ + #if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1 + #undef __ARM_ARCH + #define __ARM_ARCH 801 + #endif + + #if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M4 + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1) + #define RENESAS_CORTEX_M23 + #elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M33 + #elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2) + #define RENESAS_CORTEX_M85 + #else + #warning Unsupported Architecture + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* RA_H */ + +/** @} */ /* End of group RA */ + +/** @} */ /* End of group Renesas */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 0000000000..68d603720c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c new file mode 100644 index 0000000000..cc5f304e61 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c @@ -0,0 +1,141 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if BSP_TZ_SECURE_BUILD + #define BSP_TZ_STACK_SEAL_SIZE (8U) +#else + #define BSP_TZ_STACK_SEAL_SIZE (0U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Defines function pointers to be used with vector table. */ +typedef void (* exc_ptr_t)(void); + +extern void __libc_init_array(void); +extern void __wrap_main(void); + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void Reset_Handler(void); +void Default_Handler(void); +int32_t main(void); + +/*******************************************************************************************************************//** + * MCU starts executing here out of reset. Main stack pointer is set up already. + **********************************************************************************************************************/ +void Reset_Handler (void) +{ + /* Initialize system using BSP. */ + SystemInit(); + + /* Call software init hook explicitly(GCC only). */ + extern int software_init_hook(); + software_init_hook(); + +#if !MBED_CONF_RTOS_PRESENT + /* Call user application(GCC only). */ + __wrap_main(); +#endif + + while (1) + { + /* Infinite Loop. */ + } +} + +/*******************************************************************************************************************//** + * Default exception handler. + **********************************************************************************************************************/ +void Default_Handler (void) +{ + /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption + * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status + * registers for more information. + */ + BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0); +} + +/* Main stack */ +uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); + +/* Heap */ +BSP_DONT_REMOVE uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT); + +/* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle + * these exceptions in their code they should define their own function with the same name. + */ +#if defined(__ICCARM__) + #define WEAK_REF_ATTRIBUTE + + #pragma weak HardFault_Handler = Default_Handler + #pragma weak MemManage_Handler = Default_Handler + #pragma weak BusFault_Handler = Default_Handler + #pragma weak UsageFault_Handler = Default_Handler + #pragma weak SecureFault_Handler = Default_Handler + #pragma weak SVC_Handler = Default_Handler + #pragma weak DebugMon_Handler = Default_Handler + #pragma weak PendSV_Handler = Default_Handler + #pragma weak SysTick_Handler = Default_Handler +#elif defined(__GNUC__) + + #define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler"))) +#endif + +void NMI_Handler(void); // NMI has many sources and is handled by BSP +void HardFault_Handler(void) WEAK_REF_ATTRIBUTE; +void MemManage_Handler(void) WEAK_REF_ATTRIBUTE; +void BusFault_Handler(void) WEAK_REF_ATTRIBUTE; +void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE; +void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE; +void SVC_Handler(void) WEAK_REF_ATTRIBUTE; +void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE; +void PendSV_Handler(void) WEAK_REF_ATTRIBUTE; +void SysTick_Handler(void) WEAK_REF_ATTRIBUTE; + +/* Vector table. */ +BSP_DONT_REMOVE const exc_ptr_t __VECTOR_TABLE[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION( + BSP_SECTION_FIXED_VECTORS) = +{ + (exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + SecureFault_Handler, /* Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ +}; + +/** @} (end addtogroup BSP_MCU) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c new file mode 100644 index 0000000000..777a6ae517 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -0,0 +1,720 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include +#if defined(__GNUC__) && defined(__llvm__) && !defined(__ARMCC_VERSION) && !defined(__CLANG_TIDY__) + #include +#endif +#if defined(__ARMCC_VERSION) + #if defined(__ARMCC_USING_STANDARDLIB) + #include + #endif +#endif +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Mask to select CP bits( 0xF00000 ) */ +#define CP_MASK (0xFU << 20) + +/* Startup value for CCR to enable instruction cache, branch prediction and LOB extension */ +#define CCR_CACHE_ENABLE (0x000E0201) + +/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */ +#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_STACK_LIMIT ((uint32_t) &g_main_stack[0]) +#define BSP_PRV_STACK_TOP ((uint32_t) (uint32_t) &g_main_stack[BSP_CFG_STACK_MAIN_BYTES]) +#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5) + +#define ARMV8_MPU_REGION_MIN_SIZE (32U) + +#if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) + #define BSP_PRV_ITCM_START_ADDRESS (0x00000000UL) + #define BSP_PRV_DTCM_START_ADDRESS (0x20000000UL) + #define BSP_PRV_VTOR_FIRST_PROJECT (0x02000000UL) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; + +#if defined(__GNUC__) + +/* Nested in __GNUC__ because LLVM generates both __GNUC__ and __llvm__*/ + #if defined(__llvm__) && !defined(__CLANG_TIDY__) +extern uint32_t __tls_base; + #endif + +#endif + +/* Initialize static constructors */ +#if defined(__GNUC__) + +extern void (* __init_array_start[])(void); + +extern void (* __init_array_end[])(void); +#elif defined(__ICCARM__) +extern void __call_ctors(void const *, void const *); + + #pragma section = "SHT$$PREINIT_ARRAY" const + #pragma section = "SHT$$INIT_ARRAY" const +#endif + +extern void * __VECTOR_TABLE[]; +extern uint8_t g_main_stack[]; + +extern void R_BSP_SAUInit(void); +extern void R_BSP_SecurityInit(void); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#if BSP_FEATURE_BSP_RESET_TRNG +static void bsp_reset_trng_circuit(void); + +#endif + +#if defined(__ICCARM__) + +void R_BSP_WarmStart(bsp_warm_start_event_t event); + + #pragma weak R_BSP_WarmStart + +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) + +void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak)); + +#endif + +#if BSP_CFG_EARLY_INIT +static void bsp_init_uninitialized_vars(void); + +#endif + +#if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) + #if !BSP_TZ_NONSECURE_BUILD +static void memset_64(uint64_t * destination, const uint64_t value, size_t count); + + #endif +#endif + +#if BSP_CFG_DCACHE_ENABLED +static void bsp_init_mpu(void); + +#endif + +#if BSP_CFG_C_RUNTIME_INIT +static void SystemRuntimeInit(const uint32_t external); + +#endif + +#if BSP_CFG_C_RUNTIME_INIT +static void SystemRuntimeInit (const uint32_t external) +{ + /* Initialize C runtime environment. */ + for (uint32_t i = 0; i < g_init_info.zero_count; i++) + { + if (external == g_init_info.p_zero_list[i].type.external) + { + memset(g_init_info.p_zero_list[i].p_base, 0U, + ((uint32_t) g_init_info.p_zero_list[i].p_limit - (uint32_t) g_init_info.p_zero_list[i].p_base)); + } + } + + for (uint32_t i = 0; i < g_init_info.copy_count; i++) + { + if (external == g_init_info.p_copy_list[i].type.external) + { + memcpy(g_init_info.p_copy_list[i].p_base, g_init_info.p_copy_list[i].p_load, + ((uint32_t) g_init_info.p_copy_list[i].p_limit - (uint32_t) g_init_info.p_copy_list[i].p_base)); + } + } +} + +#endif + +/*******************************************************************************************************************//** + * Initialize the MCU and the runtime environment. + **********************************************************************************************************************/ +void SystemInit (void) +{ +#if defined(RENESAS_CORTEX_M85) + + /* Enable the instruction cache, branch prediction, and the branch cache (required for Low Overhead Branch (LOB) extension). + * See sections 6.5, 6.6, and 6.7 in the Arm Cortex-M85 Processor Technical Reference Manual (Document ID: 101924_0002_05_en, Issue: 05) + * See section D1.2.9 in the Armv8-M Architecture Reference Manual (Document number: DDI0553B.w, Document version: ID07072023) */ + SCB->CCR = (uint32_t) CCR_CACHE_ENABLE; + __DSB(); + __ISB(); + + #if !BSP_TZ_NONSECURE_BUILD + + /* If Cortex-M85 revision is r1p1 or newer. */ + const uint32_t cpuid = SCB->CPUID; + const uint32_t cpuid_variant = ((cpuid & SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); + const uint32_t cpuid_revision = ((cpuid & SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); + if (((cpuid_variant == 1) && (cpuid_revision >= 1)) || (cpuid_variant > 1)) + { + /* Set D-Cache forced write-through according to BSP configuration. */ + #if BSP_CFG_DCACHE_FORCE_WRITETHROUGH + MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk; + #else + MEMSYSCTL->MSCR &= ~(MEMSYSCTL_MSCR_FORCEWT_Msk); + #endif + __DSB(); + __ISB(); + } + else + { + /* Apply Arm Cortex-M85 errata workarounds for D-Cache. + * See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641 Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0, Document ID: SDEN-2236668). */ + MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk; + __DSB(); + __ISB(); + ICB->ACTLR |= (1U << 16U); + __DSB(); + __ISB(); + } + #endif +#endif + +#if __FPU_USED + + /* Enable the FPU only when it is used. + * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ + + /* Set bits 20-23 (CP10 and CP11) to enable FPU. */ + SCB->CPACR = (uint32_t) CP_MASK; +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Seal the main stack for secure projects. Reference: + * https://developer.arm.com/documentation/100720/0300 + * https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */ + uint32_t * p_main_stack_top = (uint32_t *) &g_main_stack[BSP_CFG_STACK_MAIN_BYTES]; + *p_main_stack_top = BSP_TZ_STACK_SEAL_VALUE; + + #if BSP_SECONDARY_CORE_BUILD + + /* Configure SAU early for secondary core since primary has already configured SAR registers */ + R_BSP_SAUInit(); + #endif +#endif + +#if !BSP_TZ_NONSECURE_BUILD + + /* VTOR is in undefined state out of RESET: + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-control-block-registers-summary?lang=en. + * Set the Secure/Non-Secure VTOR to the vector table address based on the build. This is skipped for non-secure + * projects because SCB_NS->VTOR is set by the secure project before the non-secure project runs. */ + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if !BSP_TZ_CFG_SKIP_INIT && !BSP_CFG_SKIP_INIT + #if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP + + /* Unlock VBTCR1 register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; + + /* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have VBTCR1.BPWSWSTP. Reference section 11.2.1 + * "VBATT Control Register 1 (VBTCR1)" and Figure 11.2 "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA4M1 manual + * R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR, LOCOUTCR, SOSCCR, and SOMCR cannot + * be accessed until VBTSR.VBTRVLD is set. */ + R_SYSTEM->VBTCR1 = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VBTSR_b.VBTRVLD, 1U); + + /* Lock VBTCR1 register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + #endif +#endif + +#if BSP_FEATURE_TFU_SUPPORTED + R_BSP_MODULE_START(FSP_IP_TFU, 0U); +#endif + +#if BSP_FEATURE_MACL_SUPPORTED + #if __has_include("arm_math_types.h") + R_BSP_MODULE_START(FSP_IP_MACL, 0U); + #endif +#endif + +#if BSP_CFG_EARLY_INIT + + /* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */ + bsp_init_uninitialized_vars(); +#endif + + /* Call pre clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_RESET); + +#if BSP_TZ_CFG_SKIP_INIT || BSP_CFG_SKIP_INIT + + /* Initialize clock variables to be used with R_BSP_SoftwareDelay. */ + bsp_clock_freq_var_init(); + + #if !BSP_TZ_CFG_SKIP_INIT && defined(R_CACHE) + + /* Enable C-Cache if secondary core has one. + * Do not enable CM33 C-Cache for secondary core TrustZone projects because of limitations listed in + * RA8P1 UM 2.16.5.3 Restrictions Relating to Security Attribution of C-Cache and S-Cache */ + #if !(BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) + + /* Enable cache */ + R_BSP_FlashCacheEnable(); + #endif + #endif +#else + + /* Configure system clocks. */ + bsp_clock_init(); + + #if BSP_FEATURE_BSP_RESET_TRNG + + /* To prevent an undesired current draw, this MCU requires a reset + * of the TRNG circuit after the clocks are initialized */ + + bsp_reset_trng_circuit(); + #endif +#endif + +#if BSP_FEATURE_IOPORT_HAS_LVOCR + #if !BSP_TZ_NONSECURE_BUILD && !BSP_SECONDARY_CORE_BUILD + + /* Unlock LVOCR register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; + + /* Set LVOCR according to BSP configuration. + * Configure prior to warm start post clock, since OSPI_B may initialize within and begin using I/O. */ + R_SYSTEM->LVOCR = ((BSP_CFG_IOPORT_VOLTAGE_MODE_VCC2 << R_SYSTEM_LVOCR_LVO1E_Pos) & R_SYSTEM_LVOCR_LVO1E_Msk) | + ((BSP_CFG_IOPORT_VOLTAGE_MODE_VCC << R_SYSTEM_LVOCR_LVO0E_Pos) & R_SYSTEM_LVOCR_LVO0E_Msk); + + /* Lock LVOCR register. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + #endif +#endif + + /* Call post clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK); + +#if BSP_FEATURE_BSP_HAS_SP_MON + + /* Disable MSP monitoring */ + R_MPU_SPMON->SP[0].CTL = 0; + + /* Setup NMI interrupt */ + R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; + + /* Setup start address */ + R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT; + + /* Setup end address */ + R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP; + + /* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk; + + /* Enable MSP monitoring */ + R_MPU_SPMON->SP[0].CTL = 1U; +#endif + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + __set_MSPLIM(BSP_PRV_STACK_LIMIT); +#endif + +#if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) + #if !BSP_TZ_NONSECURE_BUILD + + /* Zero initialize all available Cortex-M85 TCM memory if ECC is enabled for it and the very first project is executing. + * This may be either a bootloader if present, or a Flat or Secure application. */ + if ((MEMSYSCTL->MSCR & MEMSYSCTL_MSCR_ECCEN_Msk) && + (SCB->VTOR == BSP_PRV_VTOR_FIRST_PROJECT)) + { + const size_t itcm_num_doublewords = + (1U << (((MEMSYSCTL->ITCMCR & MEMSYSCTL_ITCMCR_SZ_Msk) >> MEMSYSCTL_ITCMCR_SZ_Pos) + 9U)) / + sizeof(uint64_t); + const size_t dtcm_num_doublewords = + (1U << (((MEMSYSCTL->DTCMCR & MEMSYSCTL_DTCMCR_SZ_Msk) >> MEMSYSCTL_DTCMCR_SZ_Pos) + 9U)) / + sizeof(uint64_t); + memset_64((uint64_t *) BSP_PRV_ITCM_START_ADDRESS, 0, itcm_num_doublewords); + memset_64((uint64_t *) BSP_PRV_DTCM_START_ADDRESS, 0, dtcm_num_doublewords); + } + #endif +#endif + +#if BSP_CFG_C_RUNTIME_INIT + + /* Initialize data placed in internal memories. */ + SystemRuntimeInit(0); +#endif + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); + +#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_RTC_HAS_VBTICTLR + + /* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */ + #if !BSP_TZ_NONSECURE_BUILD && !BSP_CFG_BOOT_IMAGE && !BSP_CFG_SKIP_INIT + + /* Perform RTC reset sequence to avoid unintended operation. */ + R_BSP_Init_RTC(); + #endif +#endif + +#if !BSP_CFG_PFS_PROTECT && defined(R_PMISC) && !BSP_CFG_SKIP_INIT + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) + R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #endif +#endif + +#if FSP_PRIV_TZ_USE_SECURE_REGS && !BSP_CFG_SKIP_INIT + + /* Ensure that the PMSAR registers are set to their default value. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if BSP_FEATURE_TZ_VERSION == 2 + R_PMISC->PMSAR[i].PMSAR = 0U; + #else + R_PMISC->PMSAR[i].PMSAR = UINT16_MAX; + #endif + } + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Initialize security features. */ + R_BSP_SecurityInit(); +#else + #if FSP_PRIV_TZ_USE_SECURE_REGS && !BSP_SECONDARY_CORE_BUILD + + /* Initialize peripherals to secure mode for flat projects */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + R_PSCU->PSARB = 0; + R_PSCU->PSARC = 0; + R_PSCU->PSARD = 0; + R_PSCU->PSARE = 0; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + #endif +#endif + +#if BSP_CFG_DCACHE_ENABLED + bsp_init_mpu(); + + SCB_EnableDCache(); +#endif + +#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN && !BSP_CFG_SKIP_INIT + if ((((0 == R_SYSTEM->PGCSAR_b.NONSEC1) && FSP_PRIV_TZ_USE_SECURE_REGS) || + ((1 == R_SYSTEM->PGCSAR_b.NONSEC1) && BSP_TZ_NONSECURE_BUILD)) && (0 != R_SYSTEM->PDCTRGD)) + { + /* Turn on graphics power domain. + * This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), + R_SYSTEM_PDCTRGD_PDPGSF_Msk); + R_SYSTEM->PDCTRGD = 0; + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), 0); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } +#endif + +#if BSP_FEATURE_CGC_HAS_NPUCLK && !BSP_CFG_SKIP_INIT + if ((((0 == R_SYSTEM->PGCSAR_b.NONSEC2) && FSP_PRIV_TZ_USE_SECURE_REGS) || + ((1 == R_SYSTEM->PGCSAR_b.NONSEC2) && BSP_TZ_NONSECURE_BUILD)) && (0 != R_SYSTEM->PDCTRNPU)) + { + /* Turn on NPU power domain */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRNPU & (R_SYSTEM_PDCTRNPU_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), + R_SYSTEM_PDCTRGD_PDPGSF_Msk); + R_SYSTEM->PDCTRNPU = 0; + FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRNPU & (R_SYSTEM_PDCTRNPU_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), + 0); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } +#endif + + /* Call Post C runtime initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_C); + +#if BSP_CFG_C_RUNTIME_INIT + + /* Initialize data placed in external memories. */ + SystemRuntimeInit(1); + + #if defined(__GNUC__) && defined(__llvm__) && !defined(__CLANG_TIDY__) && !(defined __ARMCC_VERSION) + + /* Initialize TLS memory. */ + _init_tls(&__tls_base); + _set_tls(&__tls_base); + #endif +#endif + +#if defined(__ICCARM__) + + /* Copy main thread TLS to RAM. */ + #pragma section="__DLIB_PERTHREAD_init" + #pragma section="__DLIB_PERTHREAD" + memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"), + (uint32_t) __section_size("__DLIB_PERTHREAD_init")); +#endif + +#if defined(RENESAS_CORTEX_M85) + + /* Invalidate I-Cache after initializing the .ram_from_flash section. */ + SCB_InvalidateICache(); +#endif + + // Initialize static constructors +#if !defined(MBED_CONF_RTOS_PRESENT) +#if defined(__ARMCC_VERSION) + + // TODO: should be replaced with some macro generated by e2studio + #if defined(__ARMCC_USING_STANDARDLIB) + + // C++ requires default lib: https://developer.arm.com/documentation/dui0475/i/the-arm-c-micro-library/differences-between-microlib-and-the-default-c-library?lang=en + extern uint8_t g_heap[BSP_CFG_HEAP_BYTES]; + __rt_lib_init((uint32_t) g_heap, (uint32_t) g_heap + BSP_CFG_HEAP_BYTES); + #endif +#elif defined(__GNUC__) + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } + +#elif defined(__ICCARM__) + void const * pibase = __section_begin("SHT$$PREINIT_ARRAY"); + void const * ilimit = __section_end("SHT$$INIT_ARRAY"); + __call_ctors(pibase, ilimit); +#endif +#endif + + /* Initialize ELC events that will be used to trigger NVIC interrupts. */ + bsp_irq_cfg(); + + /* Call any BSP specific code. No arguments are needed so NULL is sent. */ + bsp_init(NULL); +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to call functional safety code during the startup + * process. To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] event Where the code currently is in the start up process + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { + /* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */ + } + + if (BSP_WARM_START_POST_CLOCK == event) + { + /* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */ + } + else if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment, system clocks, and pins are all setup. */ + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module + * is not in use. + **********************************************************************************************************************/ +#if BSP_FEATURE_BSP_RESET_TRNG +static void bsp_reset_trng_circuit (void) +{ + volatile uint8_t read_port = 0U; + FSP_PARAMETER_NOT_USED(read_port); /// Prevent compiler 'unused' warning + + /* Release register protection for low power modes (as per Figure "Example + * of initial setting flow for an unused circuit" in the LPM section of the relevant hardware manual) */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Enable TRNG function (disable stop function) */ + #if (BSP_FEATURE_RSIP_AES_SUPPORTED || BSP_FEATURE_RSIP_AES_B_SUPPORTED || BSP_FEATURE_RSIP_TRNG_SUPPORTED) + R_BSP_MODULE_START(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series. + #elif BSP_FEATURE_RSIP_SCE5_SUPPORTED + R_BSP_MODULE_START(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series. + #else + #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled." + #endif + + /* Wait for at least 3 PCLKB cycles */ + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR; + + /* Disable TRNG function */ + #if (BSP_FEATURE_RSIP_AES_SUPPORTED || BSP_FEATURE_RSIP_AES_B_SUPPORTED || BSP_FEATURE_RSIP_TRNG_SUPPORTED) + R_BSP_MODULE_STOP(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series. + #elif BSP_FEATURE_RSIP_SCE5_SUPPORTED + R_BSP_MODULE_STOP(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series. + #else + #error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled." + #endif + + /* Reapply register protection for low power modes (as per Figure "Example + * of initial setting flow for an unused circuit" in the LPM section of the relevant hardware manual) */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); +} + +#endif + +#if BSP_CFG_EARLY_INIT + +/*******************************************************************************************************************//** + * Initialize BSP variables not handled by C runtime startup. + **********************************************************************************************************************/ +static void bsp_init_uninitialized_vars (void) +{ + g_protect_pfswe_counter = 0; + + extern volatile uint16_t g_protect_counters[]; + for (uint32_t i = 0; i < 4; i++) + { + g_protect_counters[i] = 0; + } + + extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[]; + for (uint32_t i = 0; i < 16; i++) + { + g_bsp_group_irq_sources[i] = 0; + } + + #if BSP_FEATURE_CGC_HAS_MOCO + + /* Set SystemCoreClock to MOCO */ + SystemCoreClock = BSP_MOCO_HZ; + #else + + /* Set SystemCoreClock to HOCO */ + SystemCoreClock = BSP_HOCO_HZ; + #endif +} + +#endif + +#if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM) + #if !BSP_TZ_NONSECURE_BUILD + +/*******************************************************************************************************************//** + * 64-bit memory set for Armv8.1-M using low overhead loop instructions. + * + * @param[in] destination set destination start address, word aligned + * @param[in] value value to set + * @param[in] count number of doublewords to set + **********************************************************************************************************************/ +static void memset_64 (uint64_t * destination, const uint64_t value, size_t count) +{ + __asm volatile ( + "wls lr, %[count], memset_64_loop_end_%=\n" + #if (defined(__ARMCC_VERSION) || defined(__GNUC__)) + + /* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */ + /* IAR does not support alignment control within inline assembly. */ + ".balign 8\n" + #endif + "memset_64_loop_start_%=:\n" + "strd %Q[value], %R[value], [%[destination]], #+8\n" + "le lr, memset_64_loop_start_%=\n" + "memset_64_loop_end_%=:" + :[destination] "+&r" (destination) + :[count] "r" (count), [value] "r" (value) + : "lr", "memory" + ); +} + + #endif +#endif + +#if BSP_CFG_DCACHE_ENABLED + +/*******************************************************************************************************************//** + * Initialize MPU for Armv8-M devices. + **********************************************************************************************************************/ +static void bsp_init_mpu (void) +{ + /* Maximum of eight attributes. */ + const uint8_t bsp_mpu_mair_attributes[] = + { + /* Normal, Non-cacheable */ + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE) + }; + + /* Initialize MPU_MAIR0 and MPU_MAIR1 from attributes table. */ + uint8_t num_attr = (sizeof(bsp_mpu_mair_attributes) / sizeof(bsp_mpu_mair_attributes[0])); + for (uint8_t i = 0; i < num_attr; i++) + { + ARM_MPU_SetMemAttr(i, bsp_mpu_mair_attributes[i]); + } + + /* Initialize MPU from configuration table. */ + for (uint8_t i = 0; i < g_init_info.nocache_count; i++) + { + uint32_t rbar = ARM_MPU_RBAR((uint32_t) (g_init_info.p_nocache_list[i].p_base), ARM_MPU_SH_NON, 0U, 0U, 1U); + uint32_t rlar = ARM_MPU_RLAR((((uint32_t) g_init_info.p_nocache_list[i].p_limit) - ARMV8_MPU_REGION_MIN_SIZE), + 0U); + + /* Only configure regions of non-zero size. */ + if ((((rlar & MPU_RLAR_LIMIT_Msk) >> MPU_RLAR_LIMIT_Pos) + ARMV8_MPU_REGION_MIN_SIZE) > + ((rbar & MPU_RBAR_BASE_Msk) >> MPU_RBAR_BASE_Pos)) + { + ARM_MPU_SetRegion(i, rbar, rlar); + } + } + + /* + * SHCSR.MEMFAULTENA is set inside ARM_MPU_Enable(). + * Leave SHPR1.PRI_4 at reset value of zero. + * Leave MPU_CTRL.HFNMIENA at reset value of zero. + * Provide MPU_CTRL_PRIVDEFENA_Msk to ARM_MPU_Enable() to set MPU_CTRL.PRIVDEFENA. + */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_clocks.c new file mode 100644 index 0000000000..0e8fc7eca7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -0,0 +1,3532 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clocks.h" + +#if BSP_TZ_NONSECURE_BUILD + #include "bsp_guard.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +/* Key code for writing LSMRWDIS register. */ +#define BSP_PRV_LSMRDIS_KEY (0xA500U) + +/* Wait state definitions for MEMWAIT. */ +#define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_MEMWAIT_ONE_WAIT_CYCLES (1U) +#define BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES (2U) +#define BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ (32000000U) +#define BSP_PRV_MEMWAIT_MAX_ONE_WAIT_FREQ (48000000U) + +/* Wait state definitions for FLDWAITR. */ +#define BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES (0U) +#define BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES (1U) +#define BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ (32000000U) + +/* Temporary solution until R_FACI is added to renesas.h. */ +#define BSP_PRV_FLDWAITR_REG_ACCESS (*((volatile uint8_t *) (0x407EFFC4U))) + +/* Wait state definitions for MCUS with SRAMWTSC and FLWT. */ +#define BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE (0U) +#define BSP_PRV_ROM_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_ROM_ONE_WAIT_CYCLES (1U) +#define BSP_PRV_ROM_TWO_WAIT_CYCLES (2U) +#define BSP_PRV_ROM_THREE_WAIT_CYCLES (3U) +#define BSP_PRV_ROM_FOUR_WAIT_CYCLES (4U) +#define BSP_PRV_ROM_FIVE_WAIT_CYCLES (5U) +#define BSP_PRV_SRAM_UNLOCK (((BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE) << \ + BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET) | 0x1U) +#define BSP_PRV_SRAM_LOCK (((BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE) << \ + BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET) | 0x0U) + +/* Determine whether SRAM wait states should be enabled */ +#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS + #define BSP_PRV_SRAM_WAIT_CYCLES BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE +#else + #define BSP_PRV_SRAM_WAIT_CYCLES BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE +#endif + +/* Calculate value to write to MOMCR/CMC (MODRV controls main clock drive strength and MOSEL determines the source of the + * main oscillator). */ +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) + +#if BSP_CFG_AUTODRVEN + #define BSP_PRV_AUTODRVEN (BSP_CFG_AUTODRVEN << R_SYSTEM_MOMCR_AUTODRVEN_Pos) +#else + #define BSP_PRV_AUTODRVEN (0U) +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_PRV_MOSEL (BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE << R_SYSTEM_MOMCR_MOSEL_Pos) + #define BSP_PRV_MOMCR (BSP_PRV_MODRV | BSP_PRV_MOSEL | BSP_PRV_AUTODRVEN) +#else + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #if BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_PRV_MOSEL (3U << R_SYSTEM_CMC_MOSEL_Pos) // External clock input mode + #else + #define BSP_PRV_MOSEL (1U << R_SYSTEM_CMC_MOSEL_Pos) // Oscillation mode + #endif + #define BSP_PRV_CMC_MOSC (BSP_PRV_MODRV | BSP_PRV_MOSEL) + #endif + +/* Calculate value to write to CMC (SODRV controls sub-clock oscillator drive capability and SOSEL determines the source of the + * sub-clock oscillator). */ + #if (0 == BSP_CLOCK_CFG_SUBCLOCK_DRIVE) + #define BSP_PRV_SODRV (1U << R_SYSTEM_CMC_SODRV_Pos) // Sub-Clock Oscillator Drive Capability Normal mode + #elif (1 == BSP_CLOCK_CFG_SUBCLOCK_DRIVE) + #define BSP_PRV_SODRV (0U << R_SYSTEM_CMC_SODRV_Pos) // Sub-Clock Oscillator Drive Capability Low Power Mode 1 + #else + #define BSP_PRV_SODRV (BSP_CLOCK_CFG_SUBCLOCK_DRIVE << R_SYSTEM_CMC_SODRV_Pos) + #endif + #define BSP_PRV_CMC_SOSC (BSP_PRV_SODRV | \ + (BSP_CLOCK_CFG_SUBCLOCK_POPULATED << R_SYSTEM_CMC_SOSEL_Pos) | \ + (BSP_CLOCK_CFG_SUBCLOCK_POPULATED << R_SYSTEM_CMC_XTSEL_Pos)) + + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_FSXP_SOURCE) + #define BSP_PRV_OSMC (0U << R_SYSTEM_OSMC_WUTMMCK0_Pos) // Use Sub-clock oscillator (SOSC) as Subsystem Clock (FSXP) source. + #elif (BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_FSXP_SOURCE) + #define BSP_PRV_OSMC (1U << R_SYSTEM_OSMC_WUTMMCK0_Pos) // Use Low-speed on-chip oscillator clock (LOCO) as Subsystem Clock (FSXP) source. + #endif + + #if (BSP_CFG_CLKOUT_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && (BSP_CFG_CLKOUT_SOURCE != BSP_CFG_CLOCK_SOURCE) + #define BSP_PRV_CLKOUT_SOURCE_SET (1U) + #elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \ + (BSP_CFG_CLKOUT1_SOURCE != BSP_CFG_CLOCK_SOURCE) + #define BSP_PRV_CLKOUT_SOURCE_SET (2U) + #else + #define BSP_PRV_CLKOUT_SOURCE_SET (0U) + #endif +#endif + +/* Locations of bitfields used to configure CLKOUT. */ +#define BSP_PRV_CKOCR_CKODIV_BIT (4U) +#define BSP_PRV_CKOCR_CKOEN_BIT (7U) + +/* Stop interval of at least 5 SOSC clock cycles between stop and restart of SOSC. + * Calculated based on 8Mhz of MOCO clock. */ +#define BSP_PRV_SUBCLOCK_STOP_INTERVAL_US (200U) + +/* Locations of bitfields used to configure Peripheral Clocks. */ +#define BSP_PRV_PERIPHERAL_CLK_REQ_BIT_POS (6U) +#define BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK (1U << BSP_PRV_PERIPHERAL_CLK_REQ_BIT_POS) +#define BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS (7U) +#define BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK (1U << BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS) + +#ifdef BSP_CFG_UCLK_DIV + +/* If the MCU has SCKDIVCR2 for USBCK configuration. */ + #if !BSP_FEATURE_USB_HAS_USBCKDIVCR + +/* Location of bitfield used to configure USB clock divider. */ + #define BSP_PRV_SCKDIVCR2_UCK_BIT (4U) + #define BSP_PRV_UCK_DIV (BSP_CFG_UCLK_DIV) + +/* If the MCU has USBCKDIVCR. */ + #elif BSP_FEATURE_USB_HAS_USBCKDIVCR + #if BSP_CLOCKS_USB_CLOCK_DIV_1 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (0U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_2 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (1U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_3 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (5U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_4 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (2U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_5 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (6U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_6 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (3U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_8 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (4U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_10 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (7U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_16 == BSP_CFG_UCLK_DIV + #define BSP_PRV_UCK_DIV (8U) + #else + + #error "BSP_CFG_UCLK_DIV not supported." + + #endif + #endif +#endif + +/* Choose the value to write to FLLCR2 (if applicable). */ +#if BSP_PRV_HOCO_USE_FLL + #if 1U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x226U) + #elif 2U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x263U) + #elif 4U == BSP_CFG_HOCO_FREQUENCY + #define BSP_PRV_FLL_FLLCR2 (0x263U) + #else + +/* When BSP_CFG_HOCO_FREQUENCY is 0, 4, 7 */ + #define BSP_PRV_FLL_FLLCR2 (0x1E9U) + #endif +#endif + +/* Calculate the value to write to SCKDIVCR. */ +#define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 0xFU) << 24U) +#if BSP_FEATURE_CGC_HAS_PCLKE + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS ((BSP_CFG_PCLKE_DIV & 0xFU) << 20U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKD + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (BSP_CFG_PCLKD_DIV & 0xFU) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKC + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS ((BSP_CFG_PCLKC_DIV & 0xFU) << 4U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKB + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 8U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKA + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS ((BSP_CFG_PCLKA_DIV & 0xFU) << 12U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_BCLK + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_BCLK_DIV & 0xFU) << 16U) +#elif BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + +/* Some MCUs have a requirement that bits 18-16 be set to the same value as the bits for configuring the PCLKB divisor. */ + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS ((BSP_CFG_PCLKB_DIV & 0xFU) << 16U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS (0U) +#endif +#if BSP_FEATURE_CGC_HAS_FCLK + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK_DIV & 0xFU) << 28U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS (0U) +#endif +#define BSP_PRV_STARTUP_SCKDIVCR (BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKE_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKD_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKC_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKB_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_PCLKA_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_BCLK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS) +#if BSP_FEATURE_CGC_HAS_CPUCLK + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (BSP_CFG_CPUCLK_DIV & 0xFU) +#else + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS (0) +#endif +#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + +/* Key codes for MRAM registers. */ + #define BSP_PRV_MRCFREQ_KEY (0x1E000000) + #define BSP_PRV_MREFREQ_KEY (0xE1000000) + #ifndef BSP_PRV_MRCPFB_LIMIT + #define BSP_PRV_MRCPFB_LIMIT (0x65) + #endif + #define BSP_PRV_MRFREQ_MIN_HZ (32768) + +/* Set npuclk to the same value as mriclk if the MCU does not support npuclk. */ + #if (BSP_FEATURE_CGC_HAS_NPUCLK == 0) + #define BSP_CFG_NPUCLK_DIV (BSP_CFG_MRICLK_DIV) + #endif + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK1_BITS ((BSP_CFG_CPUCLK1_DIV & 0xFU) << 4U) + #define BSP_PRV_STARTUP_SCKDIVCR2_NPUCK_BITS ((BSP_CFG_NPUCLK_DIV & 0xFU) << 8U) + #define BSP_PRV_STARTUP_SCKDIVCR2_MRICK_BITS ((BSP_CFG_MRICLK_DIV & 0xFU) << 12U) +#else + #define BSP_PRV_STARTUP_SCKDIVCR2_CPUCK1_BITS (0) + #define BSP_PRV_STARTUP_SCKDIVCR2_NPUCK_BITS (0) + #define BSP_PRV_STARTUP_SCKDIVCR2_MRICK_BITS (0) +#endif +#define BSP_PRV_STARTUP_SCKDIVCR2 (BSP_PRV_STARTUP_SCKDIVCR2_CPUCK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_CPUCK1_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_NPUCK_BITS | \ + BSP_PRV_STARTUP_SCKDIVCR2_MRICK_BITS) + +/* The number of clocks is used to size the g_clock_freq array. */ +#if BSP_PRV_PLL2_SUPPORTED + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL2 + \ + (BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS - 1) + \ + BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) +#elif BSP_PRV_PLL_SUPPORTED + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_PLL + \ + BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS) +#else + #define BSP_PRV_NUM_CLOCKS ((uint8_t) BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK + 1U) +#endif + +/* Calculate PLLCCR value. */ +#if BSP_PRV_PLL_SUPPORTED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #define BSP_PRV_PLL_USED (1) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (1) + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + #define BSP_PRV_PLLCCR_PLLMUL_MASK (0x3F) // PLLMUL in PLLCCR is 6 bits wide + #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL in PLLCCR starts at bit 8 + #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + BSP_CFG_PLL_DIV) + #endif + #if (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + #define BSP_PRV_PLLCCR2_PLLMUL_MASK (0x1F) // PLLMUL in PLLCCR2 is 5 bits wide + #define BSP_PRV_PLLCCR2_PLODIV_BIT (6) // PLODIV in PLLCCR2 starts at bit 6 + + #define BSP_PRV_PLLCCR2_PLLMUL (BSP_CFG_PLL_MUL >> 1) + #define BSP_PRV_PLLCCR ((BSP_PRV_PLLCCR2_PLLMUL & BSP_PRV_PLLCCR2_PLLMUL_MASK) | \ + (BSP_CFG_PLL_DIV << BSP_PRV_PLLCCR2_PLODIV_BIT)) + #endif + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #define BSP_PRV_PLL_USED (1) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (1) + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL_MUL_CFG_MACRO_PLLMUL_MASK (0x3FFU) + #elif (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL_MUL_CFG_MACRO_PLLMUL_MASK (0x7FFU) + #endif + + #define BSP_PRV_PLLCCR_PLLMULNF_BIT (6) // PLLMULNF in PLLCCR starts at bit 6 + #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLL_MUL_CFG_MACRO_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMULNF_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + BSP_CFG_PLL_DIV) + #define BSP_PRV_PLLCCR2_PLL_DIV_MASK (0x0F) // PLL DIV in PLLCCR2/PLL2CCR2 is 4 bits wide + #define BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT (4) // PLL DIV Q in PLLCCR2/PLL2CCR2 starts at bit 4 + #define BSP_PRV_PLLCCR2_PLL_DIV_R_BIT (8) // PLL DIV R in PLLCCR2/PLL2CCR2 starts at bit 8 + #define BSP_PRV_PLLCCR2 (((BSP_CFG_PLODIVR & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \ + BSP_PRV_PLLCCR2_PLL_DIV_R_BIT) | \ + ((BSP_CFG_PLODIVQ & BSP_PRV_PLLCCR2_PLL_DIV_MASK) << \ + BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT) | \ + (BSP_CFG_PLODIVP & BSP_PRV_PLLCCR2_PLL_DIV_MASK)) + #endif + #if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + + #define BSP_PRV_PLLCCR_PLLMUL_MASK (0xFFU) // PLLMUL is 8 bits wide + #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL starts at bit 8 + #define BSP_PRV_PLLCCR_RESET (0x0004U) // Bit 2 must be written as 1 + #define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + BSP_PRV_PLLCCR_RESET) + #endif + + #if (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (0) + #define BSP_PRV_PLL_USED (1) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLSRCSEL (1) + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + #define BSP_PRV_PLLCCR_PLLMUL_MASK (0x1F) // PLLMUL in PLLCCR is 5 bits wide + #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL in PLLCCR starts at bit 8 + #define BSP_PRV_PLLCCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #if (BSP_CFG_PLL_DIV == BSP_CLOCKS_PLL_DIV_1) + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + (0U)) + #elif (BSP_CFG_PLL_DIV == BSP_CLOCKS_PLL_DIV_4) + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + (1U)) + #elif (BSP_CFG_PLL_DIV == BSP_CLOCKS_PLL_DIV_6) + #define BSP_PRV_PLLCCR ((((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + (BSP_PRV_PLSRCSEL << BSP_PRV_PLLCCR_PLSRCSEL_BIT)) | \ + (2U)) + #endif + #endif +#endif + +#if BSP_FEATURE_CGC_HAS_PLL2 + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PL2SRCSEL (0) + #define BSP_PRV_PLL2_USED (1) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PL2SRCSEL (1) + #define BSP_PRV_PLL2_USED (1) + #else + #define BSP_PRV_PLL2_USED (0) + #endif + + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK (0x3FFU) + #elif (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK (0x7FFU) + #endif + + #define BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMULNF_MASK (0x003U) + #define BSP_PRV_PLL2CCR_PLLMULNF_BIT (6) // PLLMULNF in PLLCCR starts at bit 6 + #define BSP_PRV_PLL2CCR_PLSRCSEL_BIT (4) // PLSRCSEL in PLLCCR starts at bit 4 + #define BSP_PRV_PLL2CCR ((((BSP_CFG_PLL2_MUL & BSP_PRV_PLL2_MUL_CFG_MACRO_PLLMUL_MASK) << \ + BSP_PRV_PLL2CCR_PLLMULNF_BIT) | \ + (BSP_PRV_PL2SRCSEL << BSP_PRV_PLL2CCR_PLSRCSEL_BIT)) | \ + BSP_CFG_PLL2_DIV) + #define BSP_PRV_PLL2CCR2_PLL_DIV_MASK (0x0F) // PLL DIV in PLL2CCR2 is 4 bits wide + #define BSP_PRV_PLL2CCR2_PLL_DIV_Q_BIT (4) // PLL DIV Q in PLL2CCR2 starts at bit 4 + #define BSP_PRV_PLL2CCR2_PLL_DIV_R_BIT (8) // PLL DIV R in PLL2CCR2 starts at bit 8 + #define BSP_PRV_PLL2CCR2 (((BSP_CFG_PL2ODIVR & BSP_PRV_PLL2CCR2_PLL_DIV_MASK) << \ + BSP_PRV_PLL2CCR2_PLL_DIV_R_BIT) | \ + ((BSP_CFG_PL2ODIVQ & BSP_PRV_PLL2CCR2_PLL_DIV_MASK) << \ + BSP_PRV_PLL2CCR2_PLL_DIV_Q_BIT) | \ + (BSP_CFG_PL2ODIVP & BSP_PRV_PLL2CCR2_PLL_DIV_MASK)) + #else + #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \ + (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \ + (BSP_PRV_PL2SRCSEL << R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos)) + #endif +#endif + +/* All clocks with configurable source except PLL and CLKOUT can use PLL. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL) + #define BSP_PRV_STABILIZE_PLL (1) +#endif + +/* All clocks with configurable source can use the main oscillator. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) + #define BSP_PRV_STABILIZE_MAIN_OSC (1) +#elif defined(BSP_CFG_UCLK_SOURCE) && BSP_FEATURE_USB_HAS_CLOCK_REQ && \ + (BSP_CFG_UCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL_USED + #define BSP_PRV_MAIN_OSC_USED (1) + #define BSP_PRV_STABILIZE_MAIN_OSC (1) +#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) && BSP_PRV_PLL2_USED + #define BSP_PRV_MAIN_OSC_USED (1) + #define BSP_PRV_STABILIZE_MAIN_OSC (1) +#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CECCLK_SOURCE) && (BSP_CFG_CECCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_USB60CLK_SOURCE) && (BSP_CFG_USB60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_OCTACLK_SOURCE) && (BSP_CFG_OCTACLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_SDADC_CLOCK_SOURCE) && (BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_ETHPHY_SOURCE) && (BSP_CFG_ETHPHY_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) +#else + #define BSP_PRV_MAIN_OSC_USED (0) +#endif + +/* All clocks with configurable source can use HOCO except the CECCLK and I3CCLK. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) + #define BSP_PRV_STABILIZE_HOCO (1) +#elif defined(BSP_CFG_PLL_SOURCE) && (BSP_CFG_PLL_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL_USED + #define BSP_PRV_HOCO_USED (1) + #define BSP_PRV_STABILIZE_HOCO (1) +#elif defined(BSP_CFG_PLL2_SOURCE) && (BSP_CFG_PLL2_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) && BSP_PRV_PLL2_USED + #define BSP_PRV_HOCO_USED (1) + #define BSP_PRV_STABILIZE_HOCO (1) +#elif defined(BSP_CFG_UCLK_SOURCE) && BSP_FEATURE_USB_HAS_CLOCK_REQ && \ + (BSP_CFG_UCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_USB60CLK_SOURCE) && (BSP_CFG_USB60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_OCTACLK_SOURCE) && (BSP_CFG_OCTACLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_SDADC_CLOCK_SOURCE) && (BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_HOCO) + #define BSP_PRV_HOCO_USED (1) +#else + #define BSP_PRV_HOCO_USED (0) +#endif + +/* All clocks with configurable source except PLL can use MOCO. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) + #define BSP_PRV_STABILIZE_MOCO (1) +#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_UCLK_SOURCE) && BSP_FEATURE_USB_HAS_CLOCK_REQ && \ + (BSP_CFG_UCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_USB60CLK_SOURCE) && (BSP_CFG_USB60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_OCTACLK_SOURCE) && (BSP_CFG_OCTACLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_TML_FITL0_SOURCE) && (BSP_CFG_TML_FITL0_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_TML_FITL1_SOURCE) && (BSP_CFG_TML_FITL1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_ESWCLK_SOURCE) && (BSP_CFG_ESWCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_ESWPHYCLK_SOURCE) && (BSP_CFG_ESWPHYCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_ESCCLK_SOURCE) && (BSP_CFG_ESCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_ETHPHYCLK_SOURCE) && (BSP_CFG_ETHPHYCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#elif defined(BSP_CFG_BCLKA_SOURCE) && (BSP_CFG_BCLKA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) + #define BSP_PRV_MOCO_USED (1) +#else + #define BSP_PRV_MOCO_USED (0) +#endif + +/* All clocks with configurable source except UCK, CANFD, LCDCLK, USBHSCLK, I3CCLK and PLL can use LOCO. */ +#if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) + #define BSP_PRV_STABILIZE_LOCO (1) +#elif defined(BSP_CFG_CLKOUT_SOURCE) && (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_CLKOUT1_SOURCE) && (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_SCISPICLK_SOURCE) && (BSP_CFG_SCISPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_SPICLK_SOURCE) && (BSP_CFG_SPICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_SCICLK_SOURCE) && (BSP_CFG_SCICLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_CANFDCLK_SOURCE) && (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_GPTCLK_SOURCE) && (BSP_CFG_GPTCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_OCTACLK_SOURCE) && (BSP_CFG_OCTACLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_UARTA0_CLOCK_SOURCE) && (BSP_CFG_UARTA0_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif defined(BSP_CFG_UARTA1_CLOCK_SOURCE) && (BSP_CFG_UARTA1_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) + #define BSP_PRV_LOCO_USED (1) +#elif (defined(BSP_CFG_FSXP_SOURCE) && (BSP_CFG_FSXP_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO)) + #define BSP_PRV_LOCO_USED (1) +#else + #define BSP_PRV_LOCO_USED (0) +#endif + +/* Determine the optimal operating speed mode to apply after clock configuration based on the startup clock + * frequency. */ +#if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ && !BSP_PRV_PLL_USED && !BSP_PRV_PLL2_USED && \ + (BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC || !BSP_PRV_MAIN_OSC_USED) + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_LOW_SPEED) +#elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) +#else + #define BSP_PRV_STARTUP_OPERATING_MODE (BSP_PRV_OPERATING_MODE_HIGH_SPEED) +#endif + +#if defined(BSP_CFG_OPTION_SETTING_OFS1_ICSATS) && BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB + #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0 == BSP_CFG_OPTION_SETTING_OFS1_ICSATS) +#else + #define BSP_PRV_CLOCK_SUPPLY_TYPE_B (0) +#endif + +#if (BSP_FEATURE_CANFD_HAS_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \ + (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC)) || \ + (BSP_FEATURE_SCI_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_SCI_HAS_CLOCK && (BSP_CFG_SCICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_SPI_HAS_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_PERIPHERAL_GPT_GTCLK_PRESENT && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_IIC_HAS_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_CEC_HAS_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_I3C_HAS_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_USB_HAS_USB60_CLOCK && (BSP_CFG_USB60CLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_LCD_HAS_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_ADC_HAS_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_ESWM_HAS_CLOCK && (BSP_CFG_ESWCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK && (BSP_CFG_ESWPHYCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (defined(BSP_CFG_BCLKA_SOURCE) && (BSP_CFG_BCLKA_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_BSP_HAS_DSMIF_CLOCK && \ + (BSP_CFG_DSMIFCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_BSP_HAS_ESC_CLOCK && \ + (BSP_CFG_ESCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) + + #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (1U) +#else + #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (0U) +#endif + +#define BSP_PRV_HZ_PER_MHZ (1000000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if !BSP_FEATURE_CGC_REGISTER_SET_B +static uint8_t bsp_clock_set_prechange(uint32_t requested_freq_hz); +static void bsp_clock_set_postchange(uint32_t updated_freq_hz, uint8_t new_rom_wait_state); + + #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B +static void bsp_clock_set_memwait(uint32_t updated_freq_hz); + + #endif + + #if !BSP_CFG_USE_LOW_VOLTAGE_MODE +static void bsp_prv_operating_mode_opccr_set(uint8_t operating_mode); + + #endif +void bsp_prv_clock_dividers_set(uint32_t sckdivcr, uint16_t sckdivcr2); + +#else +static void bsp_prv_cmc_init(void); +static void bsp_prv_operating_mode_flmode_set(uint8_t operating_mode); + +static void bsp_prv_clkout_set(void); + +#endif + +static void bsp_prv_sosc_init(void); + +#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #if defined(__ICCARM__) + +void R_BSP_SubClockStabilizeWait(uint32_t delay_ms); +void R_BSP_SubClockStabilizeWaitAfterReset(uint32_t delay_ms); + + #pragma weak R_BSP_SubClockStabilizeWait + #pragma weak R_BSP_SubClockStabilizeWaitAfterReset + + #elif defined(__GNUC__) || defined(__ARMCC_VERSION) + +void R_BSP_SubClockStabilizeWait(uint32_t delay_ms) __attribute__((weak)); +void R_BSP_SubClockStabilizeWaitAfterReset(uint32_t delay_ms) __attribute__((weak)); + + #endif +#endif + +#if (BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS == 1U) +static void bsp_peripheral_clock_set(volatile uint8_t * p_clk_ctrl_reg, + volatile uint8_t * p_clk_div_reg, + uint8_t peripheral_clk_div, + uint8_t peripheral_clk_source); + +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET +static void bsp_prv_clock_set_hard_reset(void); + + #else +void bsp_soft_reset_prepare(void); + + #endif +#endif + +/* This array stores the clock frequency of each system clock. This section of RAM should not be initialized by the C + * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime + * environment is initialized. */ +static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS] BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +#if BSP_TZ_SECURE_BUILD + +/* Callback used to notify the nonsecure project that the clock settings have changed. */ +static bsp_clock_update_callback_t g_bsp_clock_update_callback = NULL; + +/* Pointer to nonsecure memory to store the callback args. */ +static bsp_clock_update_callback_args_t * gp_callback_memory = NULL; + +/* Reentrant method of calling the clock_update_callback. */ +static void r_bsp_clock_update_callback_call (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_args) +{ + /* Allocate memory for saving global callback args on the secure stack. */ + bsp_clock_update_callback_args_t callback_args; + + /* Save current info stored in callback memory. */ + callback_args = *gp_callback_memory; + + /* Write the callback args to the nonsecure callback memory. */ + *gp_callback_memory = *p_callback_args; + + /* Call the callback to notifiy ns project about clock changes. */ + p_callback(gp_callback_memory); + + /* Restore the info in callback memory. */ + *gp_callback_memory = callback_args; +} + +/* Initialize the callback, callback memory and invoke the callback to ensure the nonsecure project has the correct clock settings. */ +void r_bsp_clock_update_callback_set (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory) +{ + /* Store pointer to nonsecure callback memory. */ + gp_callback_memory = p_callback_memory; + + /* Store callback. */ + g_bsp_clock_update_callback = p_callback; + + /* Set callback args. */ + bsp_clock_update_callback_args_t callback_args = + { + .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] + }; + + /* Call the callback. */ + r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args); +} + +#elif BSP_TZ_NONSECURE_BUILD && BSP_CFG_CLOCKS_SECURE == 1 + +bsp_clock_update_callback_args_t g_callback_memory; + #if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +static void BSP_CMSE_NONSECURE_CALL g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args) + #elif defined(__GNUC__) + +static BSP_CMSE_NONSECURE_CALL void g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args) + #endif + +{ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = p_callback_args->pll_freq; + + /* Update the SystemCoreClock value based on the new g_clock_freq settings. */ + SystemCoreClockUpdate(); +} + + #endif +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/* List of MSTP bits that must be set before entering low power modes or changing SCKDIVCR. */ +static const uint8_t g_bsp_prv_power_change_mstp_data[][2] = BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY; + +static const uint8_t g_bsp_prv_power_change_mstp_length = sizeof(g_bsp_prv_power_change_mstp_data) / + sizeof(g_bsp_prv_power_change_mstp_data[0]); + +static volatile uint32_t * const gp_bsp_prv_mstp = &R_MSTP->MSTPCRB; +#endif + +#if (BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE) && \ + BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS +static uint16_t g_pre_sleep_sckdivcr2; +#endif + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if !BSP_CFG_USE_LOW_VOLTAGE_MODE + +/*********************************************************************************************************************** + * Changes the operating speed in OPCCR. Assumes the LPM registers are unlocked in PRCR and cache is off. + * + * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros, cannot be + * BSP_PRV_OPERATING_MODE_SUBOSC_SPEED + **********************************************************************************************************************/ +static void bsp_prv_operating_mode_opccr_set (uint8_t operating_mode) +{ + #if BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR + + /* If the desired operating mode is already set, return. */ + if (operating_mode == R_SYSTEM->OPCCR) + { + return; + } + + /* On some MCUs, the HOCO must be stable before updating OPCCR.OPCM. */ + if (0U == R_SYSTEM->HOCOCR) + { + /* Wait for HOCO to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + } + #endif + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); + + /* Apply requested operating speed mode. */ + R_SYSTEM->OPCCR = operating_mode; + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); +} + + #endif +#endif + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + +/*********************************************************************************************************************** + * Changes the operating speed mode. Assumes the LPM registers are unlocked in PRCR and cache is off. + * + * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros + **********************************************************************************************************************/ +void bsp_prv_operating_mode_set (uint8_t operating_mode) +{ + #if BSP_PRV_POWER_USE_DCDC + static bsp_power_mode_t power_mode = BSP_POWER_MODE_LDO; + + /* Disable DCDC if transitioning to an incompatible mode. */ + if ((operating_mode > BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCTL_DCDCON_Msk)) + { + /* LDO boost must be used if entering subclock speed mode (see "Switching from High-speed/Middle-speed mode + * in DCDC power mode to Subosc-speed mode or Software Standby mode" in the LPM section of the relevant hardware manual). */ + power_mode = R_BSP_PowerModeSet((BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode) ? + BSP_POWER_MODE_LDO_BOOST : BSP_POWER_MODE_LDO); + } + #endif + + #if BSP_FEATURE_CGC_HAS_SOPCCR + if (BSP_PRV_OPERATING_MODE_SUBOSC_SPEED == operating_mode) + { + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + + /* Set subosc speed mode. */ + R_SYSTEM->SOPCCR = 0x1U; + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + } + else + #endif + { + #if BSP_FEATURE_CGC_HAS_SOPCCR + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); + + /* Exit subosc speed mode first. */ + R_SYSTEM->SOPCCR = 0U; + + /* Wait for transition to complete. Check the entire register here since it should be set to 0 at this point. + * Checking the entire register is slightly more efficient. This will also hang the program if the LPM + * registers are not unlocked, which can help catch programming errors. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR, 0U); + #endif + + #if BSP_FEATURE_CGC_REGISTER_SET_B + bsp_prv_operating_mode_flmode_set(operating_mode); + #else + bsp_prv_operating_mode_opccr_set(operating_mode); + #endif + } + + #if BSP_PRV_POWER_USE_DCDC + + /* Enable DCDC if it was previously enabled. */ + if ((operating_mode <= BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) && (power_mode < BSP_POWER_MODE_LDO)) + { + R_BSP_PowerModeSet(power_mode); + power_mode = BSP_POWER_MODE_LDO; + } + #endif +} + +#endif + +#if BSP_PRV_PLL_SUPPORTED + +/*********************************************************************************************************************** + * Updates the operating frequency of the specified PLL and all its output channels. + * + * @param[in] clock PLL being configured + * @param[in] p_pll_hz Array of values of the new PLL output clock frequencies + **********************************************************************************************************************/ +void bsp_prv_prepare_pll (uint32_t clock, uint32_t const * const p_pll_hz) +{ + if (BSP_CLOCKS_SOURCE_CLOCK_PLL == clock) + { + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = p_pll_hz[0]; + #if 3 == BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = p_pll_hz[1]; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = p_pll_hz[2]; + #endif + } + + #if BSP_PRV_PLL2_SUPPORTED + else + { + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = p_pll_hz[0]; + #if 3 == BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2Q] = p_pll_hz[1]; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2R] = p_pll_hz[2]; + #endif + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Update SystemCoreClock variable based on current clock settings. + **********************************************************************************************************************/ +void SystemCoreClockUpdate (void) +{ +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_FEATURE_TZ_HAS_TRUSTZONE && (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 + bool secure = !R_SYSTEM->CGFSAR_b.NONSEC00; + #endif + + uint32_t clock_index = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKSCR, secure); + + #if !BSP_FEATURE_CGC_HAS_CPUCLK + uint32_t ick = + (FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, secure) & R_SYSTEM_SCKDIVCR_ICK_Msk) >> R_SYSTEM_SCKDIVCR_ICK_Pos; + SystemCoreClock = g_clock_freq[clock_index] >> ick; + #else + #if (BSP_CFG_CPU_CORE == 1) + uint8_t cpuck = (FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, secure) & R_SYSTEM_SCKDIVCR2_CPUCK1_Msk) >> + R_SYSTEM_SCKDIVCR2_CPUCK1_Pos; + #else + uint8_t cpuck = (FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, secure) & R_SYSTEM_SCKDIVCR2_CPUCK_Msk) >> + R_SYSTEM_SCKDIVCR2_CPUCK_Pos; + #endif + uint8_t cpuclk_div = cpuck; + + if (8U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 3U; + } + else if (9U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 6U; + } + else if (10U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 12U; + } + else if (11U == cpuclk_div) + { + SystemCoreClock = g_clock_freq[clock_index] / 24U; + } + else + { + SystemCoreClock = g_clock_freq[clock_index] >> cpuclk_div; + } + #endif +#else + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + SystemCoreClock = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] >> R_SYSTEM->MOSCDIV; + #endif + if (BSP_CLOCKS_SOURCE_CLOCK_FSUB == R_SYSTEM->ICLKSCR_b.CKST) + { + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + SystemCoreClock = R_SYSTEM->FSUBSCR ? g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO] : \ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK]; + #else + SystemCoreClock = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO]; + #endif + } + else + { + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + if (BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO == R_SYSTEM->FMAINSCR_b.CKST) + #endif + { + #if BSP_FEATURE_CGC_HAS_MOCO + SystemCoreClock = R_SYSTEM->FOCOSCR_b.CKST ? \ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MOCO] >> R_SYSTEM->MOCODIV : \ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] >> R_SYSTEM->HOCODIV; + #else + SystemCoreClock = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] >> R_SYSTEM->HOCODIV; + #endif + } + } +#endif +} + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/*******************************************************************************************************************//** + * Sets MSTP bits as required by the hardware manual for the MCU (refer Figure "Example flow for changing the + * value of SCKDIVCR" in the CGC section of the relevant hardware manual). + * + * This function must be called before entering standby or changing SCKDIVCR. + * + * @return bitmask of bits set, where each bit corresponds to an index in g_bsp_prv_power_change_mstp_data + **********************************************************************************************************************/ +uint32_t bsp_prv_power_change_mstp_set (void) +{ + uint32_t mstp_set_bitmask = 0U; + for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++) + { + /* Get the MSTP register index and the bit to test from the MCU specific array. */ + uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0]; + uint32_t mstp_bit = 1U << g_bsp_prv_power_change_mstp_data[i][1]; + + /* Only set the bit if it's currently cleared. */ + if (!(gp_bsp_prv_mstp[mstp_index] & mstp_bit)) + { + gp_bsp_prv_mstp[mstp_index] |= mstp_bit; + mstp_set_bitmask |= 1U << i; + } + + /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being set. It was measured + * at 58 cycles for default IAR build configurations and 59 cycles for default GCC build configurations. */ + } + + /* The time between setting last MSTP bit and setting SCKDIVCR takes over 750 ns (90 cycles at 120 MHz). It was + * measured at 96 cycles for default IAR build configurations and 102 cycles for default GCC build + * configurations. */ + + return mstp_set_bitmask; +} + +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + +/*******************************************************************************************************************//** + * Clears MSTP bits set by bsp_prv_power_change_mstp_set as required by the hardware manual for the MCU (reference + * Figure "Example flow for changing the value of SCKDIVCR" in the CGC section of the relevant hardware manual). + * + * This function must be called after exiting standby or changing SCKDIVCR. + * + * @param[in] mstp_clear_bitmask bitmask of bits to clear, where each bit corresponds to an index in + * g_bsp_prv_power_change_mstp_data + **********************************************************************************************************************/ +void bsp_prv_power_change_mstp_clear (uint32_t mstp_clear_bitmask) +{ + /* The time between setting SCKDIVCR and clearing the first MSTP bit takes over 250 ns (30 cycles at 120 MHz). It + * was measured at 38 cycles for default IAR build configurations and 68 cycles for default GCC build + * configurations. */ + + for (uint32_t i = 0U; i < g_bsp_prv_power_change_mstp_length; i++) + { + /* Only clear the bit if it was set in bsp_prv_power_change_mstp_set. */ + if ((1U << i) & mstp_clear_bitmask) + { + /* Get the MSTP register index and the bit to test from the MCU specific array. */ + uint32_t mstp_index = g_bsp_prv_power_change_mstp_data[i][0]; + uint32_t mstp_bit = 1U << g_bsp_prv_power_change_mstp_data[i][1]; + + gp_bsp_prv_mstp[mstp_index] &= ~mstp_bit; + } + + /* This loop takes over 250 ns (30 cycles at 120 MHz) between 2 consecutive bits being cleared. It was measured + * at 44 cycles for default IAR build configurations and 53 cycles for default GCC build configurations. */ + } +} + +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + +/*******************************************************************************************************************//** + * Write SCKDIVCR and SCKDIVCR2 in the correct order to ensure that CPUCLK frequency is greater than ICLK frequency. + * + * @param[in] sckdivcr The new SCKDIVCR setting. + * @param[in] sckdivcr2 The new SCKDIVCR2 setting. + **********************************************************************************************************************/ +void bsp_prv_clock_dividers_set (uint32_t sckdivcr, uint16_t sckdivcr2) +{ + #if BSP_FEATURE_CGC_HAS_CPUCLK + uint32_t requested_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE( + (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK); + uint32_t current_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE(R_SYSTEM->SCKDIVCR_b.ICK); + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + uint16_t temp_sckdivcr2 = sckdivcr2; + #else + uint8_t temp_sckdivcr2 = ((uint8_t) sckdivcr2) & R_SYSTEM_SCKDIVCR2_CPUCK_Msk; + #endif + + if (requested_iclk_div >= current_iclk_div) + { + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR = sckdivcr; + R_SYSTEM->SCKDIVCR2 = temp_sckdivcr2; + } + else + { + /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first + * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR2 = temp_sckdivcr2; + R_SYSTEM->SCKDIVCR = sckdivcr; + } + + #else + FSP_PARAMETER_NOT_USED(sckdivcr2); + + R_SYSTEM->SCKDIVCR = sckdivcr; + #endif +} + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + +/*******************************************************************************************************************//** + * Clears the PFB for MRAM. + **********************************************************************************************************************/ +void bsp_prv_clear_pfb (void) +{ + /* Clear MRAM pre-fetch buffer, see 54.4.3 Frequency Change Procedure for MRAM */ + R_MRMS->MRCPFB = 0x00; + (void) R_MRMS->MRCPFB; + (void) R_MRMS->MRCPFB; + (void) R_MRMS->MRCPFB; +} + +/*******************************************************************************************************************//** + * Sets the PFB for MRAM if the frequency exceeds the threshold. + **********************************************************************************************************************/ +void bsp_prv_set_pfb (void) +{ + uint32_t mrcfreq = R_MRMS->MRCFREQ_b.MRCMHZ; + + /* Do not enable Prefetch Buffer when MRAM read frequency is set to 100MHz or less. */ + if (mrcfreq >= BSP_PRV_MRCPFB_LIMIT) + { + R_MRMS->MRCPFB = 0x01; + } +} + +/*******************************************************************************************************************//** + * Sets the wait states for MRAM. + **********************************************************************************************************************/ +__STATIC_INLINE void bsp_prv_set_wait_state_frequency (uint32_t mriclk_frequency_hz, uint32_t mrpclk_frequency_hz) +{ + uint32_t freq_mhz; + + /* Set Code MRAM wait states */ + if (mriclk_frequency_hz <= BSP_PRV_MRFREQ_MIN_HZ) + { + /* When under the minimum set MRCFREQ to 0 */ + freq_mhz = 0; + } + else + { + /* Round up the result when converting to MHz */ + freq_mhz = (mriclk_frequency_hz + BSP_PRV_HZ_PER_MHZ - 1) / BSP_PRV_HZ_PER_MHZ; + } + + /* Write MRCFREQ */ + while (freq_mhz != R_MRMS->MRCFREQ) + { + R_MRMS->MRCFREQ = BSP_PRV_MRCFREQ_KEY | freq_mhz; + } + + /* Set Extra MRAM wait states */ + if (mrpclk_frequency_hz <= BSP_PRV_MRFREQ_MIN_HZ) + { + /* When under the minimum set MREFREQ to 0 */ + freq_mhz = 0; + } + else + { + /* Round up the result when converting to MHz */ + freq_mhz = (mrpclk_frequency_hz + BSP_PRV_HZ_PER_MHZ - 1) / BSP_PRV_HZ_PER_MHZ; + } + + /* Write MREFREQ */ + while (freq_mhz != R_MRMS->MREFREQ) + { + R_MRMS->MREFREQ = BSP_PRV_MREFREQ_KEY | freq_mhz; + } +} + + #endif + +/*******************************************************************************************************************//** + * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this + * configuration and the CGC registers are expected to be unlocked in PRCR. + * + * @param[in] clock Desired system clock + * @param[in] sckdivcr Value to set in SCKDIVCR register + * @param[in] sckdivcr2 Value to set in SCKDIVCR2 register + **********************************************************************************************************************/ +void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2) +{ + #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + + /* Set MSTP bits as required by the hardware manual. This is done first to ensure the 750 ns delay required after + * increasing any division ratio in SCKDIVCR is met. */ + uint32_t mstp_set_bitmask = bsp_prv_power_change_mstp_set(); + #endif + + uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; + uint32_t iclk_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(iclk_div); + #if BSP_FEATURE_CGC_HAS_CPUCLK + uint32_t cpuclk_div = sckdivcr2 & R_SYSTEM_SCKDIVCR2_CPUCK_Msk; + uint32_t clock_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(cpuclk_div); + #else + uint32_t clock_freq_hz_post_change = iclk_freq_hz_post_change; + #endif + + /* Adjust the MCU specific wait state right before the system clock is set, if the system clock frequency to be + * set is higher than before. */ + uint8_t new_rom_wait_state = bsp_clock_set_prechange(iclk_freq_hz_post_change); + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + uint32_t mriclk_div = (sckdivcr2 & R_SYSTEM_SCKDIVCR2_MRICK_Msk) >> + R_SYSTEM_SCKDIVCR2_MRICK_Pos; + uint32_t mriclk_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(mriclk_div); + + uint32_t mrpclk_div = (sckdivcr & R_SYSTEM_SCKDIVCR_FCK_Msk) >> R_SYSTEM_SCKDIVCR_FCK_Pos; + uint32_t mrpclk_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(mrpclk_div); + + /* Clear the PFB before doing any clock changes according to Frequency Change Procedure. */ + bsp_prv_clear_pfb(); + #endif + + /* Switching to a faster source clock. */ + if (g_clock_freq[clock] >= g_clock_freq[R_SYSTEM->SCKSCR]) + { + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be faster so set wait state frequency according to Frequency Change Procedure. */ + bsp_prv_set_wait_state_frequency(mriclk_freq_hz_post_change, mrpclk_freq_hz_post_change); + #endif + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE && 0 == BSP_MCU_GROUP_RA8_GEN2 + bool post_div_set_delay = false; + + if ((clock_freq_hz_post_change > SystemCoreClock) && + ((clock_freq_hz_post_change - SystemCoreClock) > BSP_MAX_CLOCK_CHANGE_THRESHOLD)) + { + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + + if (iclk_div == cpuclk_div) + { + /* If dividers are equal, bump both down 1 notch. + * /1 and /2 are the only possible options. */ + uint32_t new_div = BSP_CLOCKS_SYS_CLOCK_DIV_2; + if (cpuclk_div == BSP_CLOCKS_SYS_CLOCK_DIV_1) + { + new_div = BSP_CLOCKS_SYS_CLOCK_DIV_4; + } + + R_SYSTEM->SCKDIVCR = (sckdivcr & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (new_div << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; + } + else + { + R_SYSTEM->SCKDIVCR = sckdivcr; + if (cpuclk_div == BSP_CLOCKS_SYS_CLOCK_DIV_1) + { + /* Determine what the other dividers are using and stay aligned with that. */ + R_SYSTEM->SCKDIVCR2 = + (iclk_div & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + } + else + { + /* If not /1, can just add 1 to it. */ + R_SYSTEM->SCKDIVCR2 = (uint8_t) sckdivcr2 + 1; + } + } + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = (uint8_t) clock; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Trigger delay after setting dividers */ + post_div_set_delay = true; + } + /* Continue and set clock to actual target speed. */ + #endif + + /* Set the clock dividers before switching to the new clock source. */ + bsp_prv_clock_dividers_set(sckdivcr, sckdivcr2); + + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE + #if BSP_MCU_GROUP_RA8_GEN2 + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #else + if (post_div_set_delay) + { + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClock = clock_freq_hz_post_change; + + /* Wait for settling delay. */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else + #endif + #endif + { + /* Switch to the new clock source. */ + R_SYSTEM->SCKSCR = (uint8_t) clock; + } + } + /* Switching to a slower source clock. */ + else + { + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE + #if 0 == BSP_MCU_GROUP_RA8_GEN2 + if ((SystemCoreClock > clock_freq_hz_post_change) && + ((SystemCoreClock - clock_freq_hz_post_change) > BSP_MAX_CLOCK_CHANGE_THRESHOLD)) + { + uint32_t current_sckdivcr = R_SYSTEM->SCKDIVCR; + + /* Must first step CPUCLK down by factor of 2 or 3 if it is currently above threshold. */ + if (R_SYSTEM->SCKDIVCR2 == ((current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF)) + { + /* If ICLK and CPUCLK have same divider currently, move ICLK down 1 notch first. */ + uint32_t current_iclk_div = (current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF; + uint32_t new_div = (uint16_t) current_iclk_div + 1; + if (current_iclk_div == 0) + { + /* Align with already selected divider for PCLKA because it must have one > 1 already. */ + new_div = + (current_sckdivcr & + (0x8 << R_SYSTEM_SCKDIVCR_PCKA_Pos)) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + } + + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + R_SYSTEM->SCKDIVCR = (current_sckdivcr & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (new_div << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; + + SystemCoreClockUpdate(); + } + } + #endif + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + R_SYSTEM->SCKSCR = (uint8_t) clock; + + /* Set the clock dividers after switching to the new clock source. */ + bsp_prv_clock_dividers_set(sckdivcr, sckdivcr2); + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be slower so set wait state frequency after changing clock frequency according to Frequency Change Procedure. */ + bsp_prv_set_wait_state_frequency(mriclk_freq_hz_post_change, mrpclk_freq_hz_post_change); + #endif + } + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + bsp_prv_set_pfb(); + #endif + + /* Clock is now at requested frequency. */ + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClock = clock_freq_hz_post_change; + + #if BSP_TZ_SECURE_BUILD + if (NULL != g_bsp_clock_update_callback) + { + /* Set callback args. */ + bsp_clock_update_callback_args_t callback_args = + { + .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] + }; + + /* Call the callback. */ + r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args); + } + #endif + + /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be + * set is lower than previous. */ + bsp_clock_set_postchange(iclk_freq_hz_post_change, new_rom_wait_state); + + #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED + + /* Clear MSTP bits as required by the hardware manual. This is done last to ensure the 250 ns delay required after + * decreasing any division ratio in SCKDIVCR is met. */ + bsp_prv_power_change_mstp_clear(mstp_set_bitmask); + #endif +} + + #if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE + +bool bsp_prv_clock_prepare_pre_sleep (void) +{ + /* Must wait before entering or exiting sleep modes. + * See "Notes on transitioning to or canceling low power state" in the LPM section of the relevant hardware manual */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Need to slow CPUCLK down before sleeping if it is above 240MHz. */ + bool cpuclk_slowed = false; + if (SystemCoreClock > BSP_MAX_CLOCK_CHANGE_THRESHOLD) + { + #if BSP_MCU_GROUP_RA8_GEN2 + g_pre_sleep_sckdivcr2 = R_SYSTEM->SCKDIVCR2; + uint32_t iclk_div = (R_SYSTEM->SCKDIVCR & R_SYSTEM_SCKDIVCR_ICK_Msk) >> R_SYSTEM_SCKDIVCR_ICK_Pos; + + /* Drop all dividers which could be higher than ICLK to match ICLK. */ + R_SYSTEM->SCKDIVCR2 = + (uint16_t) ((iclk_div << R_SYSTEM_SCKDIVCR2_CPUCK_Pos) | (iclk_div << R_SYSTEM_SCKDIVCR2_CPUCK1_Pos) | + (iclk_div << R_SYSTEM_SCKDIVCR2_NPUCK_Pos) | (iclk_div << R_SYSTEM_SCKDIVCR2_MRICK_Pos)); + #else + + /* Reduce speed of CPUCLK to /2 or /3 of current, select which ones based on what ICLK divider is. */ + R_SYSTEM->SCKDIVCR2 = + (R_SYSTEM->SCKDIVCR & + (0x8 << R_SYSTEM_SCKDIVCR_ICK_Pos)) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + #endif + cpuclk_slowed = true; + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + + return cpuclk_slowed; +} + +void bsp_prv_clock_prepare_post_sleep (bool cpuclk_slowed) +{ + /* Set CPUCLK back to original speed here if it was slowed down before sleeping (dropped to below 240MHz) + * Add delays as described in "Notes on transitioning to or canceling low power state" in the LPM section of the relevant hardware manual */ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + if (cpuclk_slowed) + { + #if BSP_MCU_GROUP_RA8_GEN2 + R_SYSTEM->SCKDIVCR2 = g_pre_sleep_sckdivcr2; + #else + + /* Set divider of CPUCLK back to /1. This is the only possible value for it to have been over 240MHz before sleeping. */ + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_1; + #endif + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } +} + + #endif + +#else + +/*******************************************************************************************************************//** + * Get system core clock source. + * + **********************************************************************************************************************/ +uint32_t bsp_prv_clock_source_get (void) +{ + /* + * | System clock source | FOCOSCR.CKSEL | FMAINSCR.CKSEL | FSUBSCR.CKSEL | ICLKSCR.CKSEL | + * | ------------------- | ------------- | -------------- | ------------- | ------------- | + * | HOCO | 0U | 0U | x | 0U | + * | MOCO | 1U | 0U | x | 0U | + * | MOSC | x | 1U | x | 0U | + * | LOCO | x | x | 1U | 1U | + * | SOSC | x | x | 0U | 1U | + * + * */ + #if BSP_FEATURE_CGC_HAS_MOSC + uint32_t clock = BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC; + #else + uint32_t clock = BSP_CLOCKS_SOURCE_CLOCK_HOCO; + #endif + + if (BSP_CLOCKS_SOURCE_CLOCK_FSUB == R_SYSTEM->ICLKSCR_b.CKST) + { + #if BSP_FEATURE_CGC_HAS_SOSC + clock = R_SYSTEM->FSUBSCR ? BSP_CLOCKS_SOURCE_CLOCK_LOCO : BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK; + #else + clock = BSP_CLOCKS_SOURCE_CLOCK_LOCO; + #endif + } + + #if BSP_FEATURE_CGC_HAS_MOCO + else if (BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO == R_SYSTEM->FMAINSCR_b.CKST) + { + clock = R_SYSTEM->FOCOSCR_b.CKST ? BSP_CLOCKS_SOURCE_CLOCK_MOCO : BSP_CLOCKS_SOURCE_CLOCK_HOCO; + } + #endif + else + { + /* Do nothing. */ + } + + return clock; +} + +/*******************************************************************************************************************//** + * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this + * configuration and the CGC registers are expected to be unlocked in PRCR. + * + * @param[in] clock Desired system clock + * @param[in] hocodiv The new HOCODIV setting. + * @param[in] mocodiv The new MOCODIV setting. + * @param[in] moscdiv The new MOSCDIV setting. + **********************************************************************************************************************/ +void bsp_prv_clock_set (uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv) +{ + /* + * | System clock source | FOCOSCR.CKSEL | FMAINSCR.CKSEL | FSUBSCR.CKSEL | ICLKSCR.CKSEL | + * | ------------------- | ------------- | -------------- | ------------- | ------------- | + * | HOCO | 0U | 0U | x | 0U | + * | MOCO | 1U | 0U | x | 0U | + * | MOSC | x | 1U | x | 0U | + * | LOCO | x | x | 1U | 1U | + * | SOSC | x | x | 0U | 1U | + * + * */ + R_SYSTEM->ICLKSCR_b.CKSEL = BSP_CLOCKS_SOURCE_CLOCK_FMAIN; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->ICLKSCR_b.CKST, BSP_CLOCKS_SOURCE_CLOCK_FMAIN); + + #if BSP_FEATURE_CGC_HAS_MOCO + if ((BSP_CLOCKS_SOURCE_CLOCK_HOCO == clock) || (BSP_CLOCKS_SOURCE_CLOCK_MOCO == clock)) + { + R_SYSTEM->FMAINSCR_b.CKSEL = BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->FMAINSCR_b.CKST, BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO); + + if (BSP_CLOCKS_SOURCE_CLOCK_HOCO == clock) + { + R_SYSTEM->FOCOSCR_b.CKSEL = BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->FOCOSCR_b.CKST, BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO); + + /* Due to register access restrictions, only set the HOCODIV when system clock source is HOCO. * + * See in hardware manual: Clock Generation Circuit > Usage Notes > Register Access */ + R_SYSTEM->HOCODIV = hocodiv; + } + else + { + R_SYSTEM->FOCOSCR_b.CKSEL = BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->FOCOSCR_b.CKST, BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO); + } + } + + #else + if (BSP_CLOCKS_SOURCE_CLOCK_HOCO == clock) + { + /* Due to register access restrictions, only set the HOCODIV when system clock source is HOCO. * + * See in hardware manual: Clock Generation Circuit > Usage Notes > Register Access */ + R_SYSTEM->HOCODIV = hocodiv; + } + #endif + + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + else if (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == clock) + { + R_SYSTEM->FMAINSCR_b.CKSEL = BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->FMAINSCR_b.CKST, BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC); + } + #endif + else + { + if (BSP_CLOCKS_SOURCE_CLOCK_LOCO == clock) + { + R_SYSTEM->FSUBSCR = BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO; + } + + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + else + { + R_SYSTEM->FSUBSCR = BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK; + } + #endif + + R_SYSTEM->ICLKSCR_b.CKSEL = BSP_CLOCKS_SOURCE_CLOCK_FSUB; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->ICLKSCR_b.CKST, BSP_CLOCKS_SOURCE_CLOCK_FSUB); + } + + #if BSP_FEATURE_CGC_HAS_MOCO + R_SYSTEM->MOCODIV = mocodiv; + #else + FSP_PARAMETER_NOT_USED(mocodiv); + #endif + + #if BSP_FEATURE_CGC_HAS_MOSC + R_SYSTEM->MOSCDIV = moscdiv; + #else + FSP_PARAMETER_NOT_USED(moscdiv); + #endif + + /* Clock is now at requested frequency. Update the CMSIS core clock variable so that it reflects the new ICLK frequency.*/ + SystemCoreClockUpdate(); +} + +/*******************************************************************************************************************//** + * Setting for CLKOUT/CLKOUT1 + **********************************************************************************************************************/ +static void bsp_prv_clkout_set (void) +{ + #if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLOCK_DISABLED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + R_PCLBUZ->CKS[0] = 0U; + #endif + #else + uint8_t cks0 = (BSP_CFG_CLKOUT_DIV << R_PCLBUZ_CKS_CCS_Pos); + #if (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) || \ + (BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK) + cks0 |= (BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB << R_PCLBUZ_CKS_CSEL_Pos); + #else + cks0 |= (BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN << R_PCLBUZ_CKS_CSEL_Pos); + #endif + R_PCLBUZ->CKS[0] = cks0; + R_PCLBUZ->CKS[0] |= (1U << R_PCLBUZ_CKS_PCLOE_Pos); + #endif + + #if defined(BSP_CFG_CLKOUT1_SOURCE) + #if BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_CLOCK_DISABLED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + R_PCLBUZ->CKS[1] = 0U; + #endif + #else + uint8_t cks1 = (BSP_CFG_CLKOUT1_DIV << R_PCLBUZ_CKS_CCS_Pos); + #if (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_LOCO) || \ + (BSP_CFG_CLKOUT1_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK) + cks1 |= (BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB << R_PCLBUZ_CKS_CSEL_Pos); + #else + cks1 |= (BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN << R_PCLBUZ_CKS_CSEL_Pos); + #endif + R_PCLBUZ->CKS[1] = cks1; + R_PCLBUZ->CKS[1] |= (1U << R_PCLBUZ_CKS_PCLOE_Pos); + #endif + #endif +} + +#endif + +#if !BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET && !BSP_FEATURE_CGC_REGISTER_SET_B +static void bsp_prv_clock_set_hard_reset (void) +{ + /* Wait states in SRAMWTSC are set after hard reset. No change required here. */ + + /* Calculate the wait states for ROM */ + #if BSP_FEATURE_CGC_HAS_FLWT + #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS + + /* Do nothing. Default setting in FLWT is correct. */ + #elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS || \ + BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS == 0 + R_FCACHE->FLWT = BSP_PRV_ROM_ONE_WAIT_CYCLES; + #elif 0 == BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS || \ + (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS) + R_FCACHE->FLWT = BSP_PRV_ROM_TWO_WAIT_CYCLES; + #elif 0 == BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS || \ + (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS) + R_FCACHE->FLWT = BSP_PRV_ROM_THREE_WAIT_CYCLES; + #elif 0 == BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS || \ + (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS) + R_FCACHE->FLWT = BSP_PRV_ROM_FOUR_WAIT_CYCLES; + #else + R_FCACHE->FLWT = BSP_PRV_ROM_FIVE_WAIT_CYCLES; + #endif + #endif + + #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + #if BSP_STARTUP_ICLK_HZ > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ + #if ((BSP_STARTUP_ICLK_HZ > BSP_PRV_MEMWAIT_MAX_ONE_WAIT_FREQ) && \ + (BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES & R_SYSTEM_MEMWAIT_MEMWAIT_Msk)) + + /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */ + R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES; + #else + R_SYSTEM->MEMWAIT = BSP_PRV_MEMWAIT_ONE_WAIT_CYCLES; + #endif + #endif + #endif + + #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + #if BSP_STARTUP_ICLK_HZ > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ + + /* The MCU must be in high speed mode to set wait states to 2. High speed mode is the default out of reset. */ + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES; + #endif + #endif + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* Clear the PFB before doing any clock changes according to Frequency Change Procedure. */ + bsp_prv_clear_pfb(); + #endif + + /* In order to avoid a system clock (momentarily) higher than expected, the order of switching the clock and + * dividers must be so that the frequency of the clock goes lower, instead of higher, before being correct. */ + + /* MOCO is the source clock after reset. If the new source clock is faster than the current source clock, + * then set the clock dividers before switching to the new source clock. */ + #if BSP_MOCO_FREQ_HZ <= BSP_STARTUP_SOURCE_CLOCK_HZ + #if BSP_FEATURE_CGC_HAS_CPUCLK + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be faster so set wait state frequency before changing clock frequency + * according to Frequency Change Procedure. */ + bsp_prv_set_wait_state_frequency(BSP_STARTUP_MRICLK_HZ, BSP_STARTUP_FCLK_HZ); + #endif + #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE && (BSP_STARTUP_CPUCLK_HZ >= BSP_MAX_CLOCK_CHANGE_THRESHOLD) && \ + (0 == BSP_MCU_GROUP_RA8_GEN2) + + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + #if BSP_CFG_ICLK_DIV == BSP_CFG_CPUCLK_DIV + + /* If dividers are equal, bump both down 1 notch. + * /1 and /2 are the only possible options. */ + #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (BSP_CLOCKS_SYS_CLOCK_DIV_2 << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_2; + #else + R_SYSTEM->SCKDIVCR = (BSP_PRV_STARTUP_SCKDIVCR & ~(R_SYSTEM_SCKDIVCR_ICK_Msk)) | + (BSP_CLOCKS_SYS_CLOCK_DIV_4 << R_SYSTEM_SCKDIVCR_ICK_Pos); + R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_4; + #endif + #else + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + + #if BSP_CFG_CPUCLK_DIV == BSP_CLOCKS_SYS_CLOCK_DIV_1 + + /* Determine what the other dividers are using and stay aligned with that. */ + R_SYSTEM->SCKDIVCR2 = (BSP_CFG_ICLK_DIV & 0x8) ? BSP_CLOCKS_SYS_CLOCK_DIV_3 : BSP_CLOCKS_SYS_CLOCK_DIV_2; + #else + + /* If not /1, can just add 1 to it. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2 + 1; + #endif + #endif + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Continue and set clock to actual target speed. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #else + #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) + + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + #else + + /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first + * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + #endif + #else + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + #endif + + /* Set the system source clock */ + R_SYSTEM->SCKSCR = BSP_CFG_CLOCK_SOURCE; + + #if BSP_MCU_GROUP_RA8_GEN2 && BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE && \ + (BSP_CLOCKS_SOURCE_CLOCK_PLL1P == BSP_CFG_CLOCK_SOURCE) + + /* Wait for settling delay. */ + SystemCoreClockUpdate(); + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + + /* MOCO is the source clock after reset. If the new source clock is slower than the current source clock, + * then set the clock dividers after switching to the new source clock. */ + #if BSP_MOCO_FREQ_HZ > BSP_STARTUP_SOURCE_CLOCK_HZ + #if BSP_FEATURE_CGC_HAS_CPUCLK + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* New source clock will be slower so set wait state frequency after changing clock frequency according to Frequency Change Procedure. */ + bsp_prv_set_wait_state_frequency(BSP_STARTUP_MRICLK_HZ, BSP_STARTUP_FCLK_HZ); + #endif + #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) + + /* If the requested ICLK divider is greater than or equal to the current ICLK divider, then writing to + * SCKDIVCR first will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + #else + + /* If the requested ICLK divider is less than the current ICLK divider, then writing to SCKDIVCR2 first + * will always satisfy the constraint: CPUCLK frequency >= ICLK frequency. */ + R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2; + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + #else + R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; + #endif + #endif + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + bsp_prv_set_pfb(); + #endif + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClockUpdate(); + + /* Clocks are now at requested frequencies. */ + + /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be + * set is lower than previous. */ + #if BSP_FEATURE_CGC_HAS_SRAMWTSC + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAM_WAIT_CYCLES; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif + + /* Execute data memory barrier before and after setting the wait states, See "Note of write to SRAMCR0, SRAMCR1 and SRAMECCRGN0 registers" + * in the SRAM section of the relevant hardware manual */ + __DMB(); + R_SRAM->SRAMWTSC = BSP_PRV_SRAM_WAIT_CYCLES; + __DMB(); + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif + #endif + #endif + + /* ROM wait states are 0 by default. No change required here. */ +} + +#endif + +/*******************************************************************************************************************//** + * Initializes variable to store system clock frequencies. + **********************************************************************************************************************/ +#if BSP_TZ_NONSECURE_BUILD || BSP_SECONDARY_CORE_BUILD +void bsp_clock_freq_var_init (void) +#else +static void bsp_clock_freq_var_init (void) +#endif +{ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] = BSP_HOCO_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MOCO] = BSP_MOCO_FREQ_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO] = BSP_LOCO_FREQ_HZ; +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = BSP_CFG_XTAL_HZ; +#else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = 0U; +#endif +#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = BSP_SUBCLOCK_FREQ_HZ; +#else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = 0U; +#endif +#if BSP_PRV_PLL_SUPPORTED + #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + #if (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) + + /* The PLL Is the startup clock. */ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ; + #else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ; + #endif + #else + + /* The PLL value will be calculated at initialization. */ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_XTAL_HZ; + #endif +#endif + +#if BSP_TZ_NONSECURE_BUILD && BSP_CFG_CLOCKS_SECURE == 1 + + /* If the CGC is secure and this is a non secure project, register a callback for getting clock settings. */ + R_BSP_ClockUpdateCallbackSet(g_bsp_clock_update_callback, &g_callback_memory); +#endif + + /* Update PLL Clock Frequency based on BSP Configuration. */ +#if BSP_PRV_PLL_SUPPORTED && BSP_CLOCKS_SOURCE_CLOCK_PLL != BSP_CFG_CLOCK_SOURCE && BSP_PRV_PLL_USED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = + ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) / + (BSP_CFG_PLL_DIV + 1U); + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ; + #elif (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> + 1U; + #else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = + ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >> + BSP_CFG_PLL_DIV; + #endif +#endif + + /* Update PLL2 Clock Frequency based on BSP Configuration. */ +#if BSP_PRV_PLL2_SUPPORTED && BSP_PRV_PLL2_USED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = + ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) / + (BSP_CFG_PLL2_DIV + 1U); + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = BSP_CFG_PLL2P_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2Q] = BSP_CFG_PLL2Q_FREQUENCY_HZ; + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2R] = BSP_CFG_PLL2R_FREQUENCY_HZ; + #else + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL2] = + ((g_clock_freq[BSP_CFG_PLL2_SOURCE] * (BSP_CFG_PLL2_MUL + 1U)) >> 1U) >> BSP_CFG_PLL2_DIV; + #endif +#endif + + /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */ + SystemCoreClockUpdate(); +} + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + +/* + * If the clock registers are not guaranteed to be set to their value after reset (Ie. the application is executing after a bootloader), + * then the current state of the registers must be taken into consideration before writing the clock configuration. + * + * The HOCO must be stopped in the following situations: + * - The application configures the HOCO to be stopped. + * - The application enables the FLL, but the HOCO is already running. In order to enable the FLL, the HOCO must be stopped. + * The PLL must be stopped in the following situations: + * - The application configures the PLL to be stopped. + * - The application configures settings that are different than the current settings, but the PLL is already running. In order to + * write new PLL settings, the PLL must be stopped. + * - The HOCO is the PLL source clock and the HOCO is being stopped. + * The PLL2 must be stopped in the following situations: + * - The application configures the PLL2 to be stopped. + * - The application configures settings that are different than the current settings, but the PLL2 is already running. In order to + * write new PLL2 settings, the PLL2 must be stopped. + * - The HOCO is the PLL2 source clock and the HOCO is being stopped. + * + * If the HOCO or PLL are being used as the system clock source and they need to be stopped, then the system clock source needs to be switched + * to the default system clock source before the current system clock source is disabled. + */ +void bsp_soft_reset_prepare (void) +{ + bool stop_hoco = false; + #if BSP_PRV_PLL_SUPPORTED + bool stop_pll = false; + #endif + #if BSP_PRV_PLL2_SUPPORTED + bool stop_pll2 = false; + #endif + + #if BSP_PRV_HOCO_USE_FLL || !BSP_PRV_HOCO_USED + #if BSP_PRV_HOCO_USE_FLL + + /* Determine if the FLL needs to be enabled. */ + bool enable_fll = (0 == R_SYSTEM->FLLCR1 && BSP_PRV_HOCO_USE_FLL); + #else + bool enable_fll = false; + #endif + + /* If the HOCO is already enabled and either the FLL needs to be enabled or the HOCO is not used, then stop the HOCO. */ + if ((0 == R_SYSTEM->HOCOCR) && (enable_fll || !BSP_PRV_HOCO_USED)) + { + stop_hoco = true; + } + #endif + + #if BSP_PRV_PLL_SUPPORTED + if (0 == R_SYSTEM->PLLCR) + { + /* + * If any of the following conditions are true, then the PLL needs to be stopped: + * - The PLL is not used + * - The PLL settings need to be changed + * - The HOCO is selected as the PLL clock source and the HOCO needs to be stopped + * - Note that PLL type 2 does not support running off of the HOCO + */ + #if BSP_PRV_PLL_USED + #if (3 == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6 == BSP_FEATURE_CGC_PLLCCR_TYPE) + if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (BSP_PRV_PLLCCR2 != R_SYSTEM->PLLCCR2) || + (stop_hoco && (1 == R_SYSTEM->PLLCCR_b.PLSRCSEL))) + #elif 2 == BSP_FEATURE_CGC_PLLCCR_TYPE + if (BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR2) + #else + if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (stop_hoco && (1 == R_SYSTEM->PLLCCR_b.PLSRCSEL))) + #endif + #endif + { + stop_pll = true; + } + } + #endif + + #if BSP_PRV_PLL2_SUPPORTED + if (0 == R_SYSTEM->PLL2CR) + { + /* + * If any of the following conditions are true, then the PLL2 needs to be stopped: + * - The PLL2 is not used + * - The PLL2 settings need to be changed + * - The HOCO is selected as the PLL2 clock source and the HOCO needs to be stopped + * - Note that PLL type 2 does not support running off of the HOCO + */ + #if BSP_PRV_PLL2_USED + #if (3 == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6 == BSP_FEATURE_CGC_PLLCCR_TYPE) + if ((BSP_PRV_PLL2CCR != R_SYSTEM->PLL2CCR) || (BSP_PRV_PLL2CCR2 != R_SYSTEM->PLL2CCR2) || + (stop_hoco && (1 == R_SYSTEM->PLL2CCR_b.PL2SRCSEL))) + #else + if ((BSP_PRV_PLL2CCR != R_SYSTEM->PLL2CCR) || (stop_hoco && (1 == R_SYSTEM->PLL2CCR_b.PL2SRCSEL))) + #endif + #endif + { + stop_pll2 = true; + } + } + #endif + + uint8_t sckscr = R_SYSTEM->SCKSCR; + + /* If the System Clock source needs to be stopped, then switch to the MOCO. */ + #if BSP_PRV_PLL_SUPPORTED + if ((stop_hoco && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == sckscr)) || + (stop_pll && (BSP_CLOCKS_SOURCE_CLOCK_PLL == sckscr))) + #else + if (stop_hoco && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == sckscr)) + #endif + { + bsp_prv_clock_set(BSP_FEATURE_CGC_STARTUP_SCKSCR, + BSP_FEATURE_CGC_STARTUP_SCKDIVCR, + BSP_FEATURE_CGC_STARTUP_SCKDIVCR2); + } + + /* Disable the oscillators so that the application can write the new clock configuration. */ + + #if BSP_PRV_PLL_SUPPORTED + if (stop_pll) + { + R_SYSTEM->PLLCR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 0); + } + #endif + + #if BSP_PRV_PLL2_SUPPORTED + if (stop_pll2) + { + R_SYSTEM->PLL2CR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 0); + } + #endif + + if (stop_hoco) + { + R_SYSTEM->HOCOCR = 1; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 0); + } +} + + #endif +#else + +/*******************************************************************************************************************//** + * Initializes CMC and OSMC registers according to the BSP configuration. + **********************************************************************************************************************/ +void bsp_prv_cmc_init (void) +{ + #if BSP_FEATURE_CGC_HAS_MOSC || BSP_FEATURE_CGC_HAS_SOSC + + /* The CMC register can be written only once after release from the reset state. If clock registers not reset + * values during startup, assume CMC register has already been set appropriately. */ + uint8_t cmc_reg = 0x00U; + + /* Set main clock oscillator drive capability */ + #if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + cmc_reg |= BSP_PRV_CMC_MOSC; + #endif + + /* Set sub-clock oscillator drive capability and pin switching */ + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + cmc_reg |= BSP_PRV_CMC_SOSC; + #endif + + R_SYSTEM->CMC = cmc_reg; + #endif + + #if (BSP_CFG_FSXP_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + uint8_t osmc = R_SYSTEM->OSMC; + + if (BSP_PRV_OSMC != osmc) + { + #if BSP_PERIPHERAL_RTC_C_PRESENT || BSP_PERIPHERAL_RTC_PRESENT + + /* Stop RTC counter operation to update the OSMC register. */ + BSP_MSTP_REG_FSP_IP_RTC(0) &= ~BSP_MSTP_BIT_FSP_IP_RTC(0); + FSP_REGISTER_READ(BSP_MSTP_REG_FSP_IP_RTC(0)); + R_RTC_C->RTCC0_b.RTCE = 0U; + BSP_MSTP_REG_FSP_IP_RTC(0) |= BSP_MSTP_BIT_FSP_IP_RTC(0); + FSP_REGISTER_READ(BSP_MSTP_REG_FSP_IP_RTC(0)); + #endif + + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + if (0U == osmc) + { + /* Current Subsystem Clock (FSXP) source is SOSC. */ + if (0U == R_SYSTEM->SOSCCR) + { + /* Stop the Sub-Clock Oscillator to update the OSMC register. */ + R_SYSTEM->SOSCCR = 1U; + + /* Allow a stop interval of at least 5 SOSC clock cycles before restarting Sub-Clock Oscillator. */ + R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* When changing the value of the SOSTP bit, only execute subsequent + * instructions after reading the bit to check that the value is updated. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOSCCR, 1U); + } + } + #endif + + R_SYSTEM->OSMC = BSP_PRV_OSMC; + } + #endif +} + +/*********************************************************************************************************************** + * Changes the operating speed in FLMODE. Assumes the LPM registers are unlocked in PRCR. + * + * @param[in] operating_mode Desired operating mode, must be one of the BSP_PRV_OPERATING_MODE_* macros, cannot be + * BSP_PRV_OPERATING_MODE_SUBOSC_SPEED + **********************************************************************************************************************/ +static void bsp_prv_operating_mode_flmode_set (uint8_t operating_mode) +{ + if (operating_mode != R_FACI_LP->FLMODE_b.MODE) + { + /* Enable FLMWRP.FLMWEN bit to before rewrite to FLMODE register */ + R_FACI_LP->FLMWRP_b.FLMWEN = 0x1U; + + if ((BSP_PRV_OPERATING_MODE_MIDDLE_SPEED != operating_mode) && + (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED != R_FACI_LP->FLMODE_b.MODE)) + { + /* Set flash operating mode to middle-speed mode first */ + R_FACI_LP->FLMODE = (uint8_t) (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED << R_FACI_LP_FLMODE_MODE_Pos); + } + + /* Set flash operating mode */ + R_FACI_LP->FLMODE = (uint8_t) (operating_mode << R_FACI_LP_FLMODE_MODE_Pos); + + /* Disable FLMWRP.FLMWEN bit to after rewrite to FLMODE register */ + R_FACI_LP->FLMWRP_b.FLMWEN = 0x0U; + } +} + +#endif + +/*******************************************************************************************************************//** + * Initializes system clocks. Makes no assumptions about current register settings. + **********************************************************************************************************************/ +void bsp_clock_init (void) +{ + /* Unlock CGC and LPM protection registers. */ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_UNLOCK; +#else + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; +#endif + +#if BSP_FEATURE_FLASH_CACHE || defined(R_CACHE) + #if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_FLASH_CACHE_DISABLE_OPM + + /* Disable flash cache before modifying MEMWAIT, SOPCCR, or OPCCR. */ + R_BSP_FlashCacheDisable(); + #else + + /* Do not enable CM33 C-Cache for secondary core TrustZone projects because of limitations listed in + * RA8P1 UM 2.16.5.3 Restrictions Relating to Security Attribution of C-Cache and S-Cache */ + #if !((BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2) && (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD)) + + /* Enable the flash cache and don't disable it while running from flash. On these MCUs, the flash cache does not + * need to be disabled when adjusting the operating power mode. */ + R_BSP_FlashCacheEnable(); + #endif + #endif +#endif + +#if BSP_FEATURE_FLASH_PREFETCH_BUFFER + + /* Enable the flash prefetch buffer. */ + R_FACI_LP->PFBER = 1; +#endif + + bsp_clock_freq_var_init(); + +#if BSP_FEATURE_CGC_REGISTER_SET_B + bsp_prv_cmc_init(); +#else + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* Transition to an intermediate clock configuration in order to prepare for writing the new clock configuration. */ + bsp_soft_reset_prepare(); + #endif +#endif + +#if BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* Update the main oscillator drive, source, and wait states if the main oscillator is stopped. If the main + * oscillator is running, the drive, source, and wait states are assumed to be already set appropriately. */ + if (R_SYSTEM->MOSCCR) + { + #if BSP_FEATURE_CGC_REGISTER_SET_B + + /* Set the main oscillator wait time. */ + R_SYSTEM->OSTS = BSP_CLOCK_CFG_MAIN_OSC_WAIT; + #else + + /* Don't write to MOSCWTCR unless MOSTP is 1 and MOSCSF = 0. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 0U); + + /* Configure main oscillator drive. */ + R_SYSTEM->MOMCR = BSP_PRV_MOMCR; + + /* Set the main oscillator wait time. */ + R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT; + #endif + } + + #else + #if BSP_FEATURE_CGC_REGISTER_SET_B + + /* Set the main oscillator wait time. */ + R_SYSTEM->OSTS = BSP_CLOCK_CFG_MAIN_OSC_WAIT; + #else + + /* Configure main oscillator drive. */ + R_SYSTEM->MOMCR = BSP_PRV_MOMCR; + + /* Set the stabilization time for XTAL. */ + R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT; + #endif + #endif +#endif + + /* Initialize the sub-clock according to the BSP configuration. */ + bsp_prv_sosc_init(); + +#if BSP_FEATURE_CGC_HAS_HOCOWTCR + #if BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY + + /* These MCUs only require writes to HOCOWTCR if HOCO is set to 64 MHz. */ + #if 64000000 == BSP_HOCO_HZ + #if BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* Wait for HOCO to stabilize before writing to HOCOWTCR. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + #else + + /* HOCO is assumed to be stable because these MCUs also require the HOCO to be stable before changing the operating + * power control mode. */ + #endif + R_SYSTEM->HOCOWTCR = BSP_FEATURE_CGC_HOCOWTCR_VALUE; + #endif + #else + + /* These MCUs require HOCOWTCR to be set to the maximum value except in snooze mode. There is no restriction to + * writing this register. */ + R_SYSTEM->HOCOWTCR = BSP_FEATURE_CGC_HOCOWTCR_VALUE; + #endif +#endif + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* Switch to high-speed to prevent any issues with the subsequent clock configurations. */ + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + #elif BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ > 0U + + /* MCUs that support low voltage mode start up in low voltage mode. */ + bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + + #if !BSP_PRV_HOCO_USED + + /* HOCO must be running during startup in low voltage mode. If HOCO is not used, turn it off after exiting low + * voltage mode. */ + R_SYSTEM->HOCOCR = 1U; + #endif + #elif BSP_FEATURE_CGC_STARTUP_OPCCR_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED + + /* Some MCUs do not start in high speed mode. */ + #if !BSP_FEATURE_CGC_REGISTER_SET_B + bsp_prv_operating_mode_opccr_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + #else + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); + #endif + #endif +#endif + + /* The FLL function can only be used when the subclock is running. */ +#if BSP_PRV_HOCO_USE_FLL + + /* If FLL is to be used configure FLLCR1 and FLLCR2 before starting HOCO. */ + R_SYSTEM->FLLCR2 = BSP_PRV_FLL_FLLCR2; + R_SYSTEM->FLLCR1 = 1U; +#endif + + /* Start all clocks used by other clocks first. */ +#if BSP_PRV_HOCO_USED + R_SYSTEM->HOCOCR = 0U; + + #if BSP_PRV_HOCO_USE_FLL && (BSP_CLOCKS_SOURCE_CLOCK_HOCO != BSP_CFG_PLL_SOURCE) + + /* If FLL is enabled, wait for the FLL stabilization delay (1.8 ms) */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + + #if BSP_PRV_STABILIZE_HOCO + + /* Wait for HOCO to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.HOCOSF, 1U); + #endif +#endif +#if BSP_PRV_MOCO_USED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* If the MOCO is not running, start it and wait for it to stabilize using a software delay. */ + if (0U != R_SYSTEM->MOCOCR) + { + R_SYSTEM->MOCOCR = 0U; + #if BSP_PRV_STABILIZE_MOCO + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + } + + #else + #if BSP_FEATURE_CGC_REGISTER_SET_B + R_SYSTEM->MOCOCR = 0U; + #if BSP_PRV_STABILIZE_MOCO + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + #endif + #endif +#endif +#if BSP_PRV_LOCO_USED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + + /* If the LOCO is not running, start it and wait for it to stabilize using a software delay. */ + if (0U != R_SYSTEM->LOCOCR) + { + R_SYSTEM->LOCOCR = 0U; + #if BSP_PRV_STABILIZE_LOCO + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + } + + #else + R_SYSTEM->LOCOCR = 0U; + #if BSP_PRV_STABILIZE_LOCO + R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + #endif +#endif +#if BSP_PRV_MAIN_OSC_USED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->MOSCCR) + #endif + { + R_SYSTEM->MOSCCR = 0U; + + #if BSP_PRV_STABILIZE_MAIN_OSC + + /* Wait for main oscillator to stabilize. */ + #if BSP_FEATURE_CGC_REGISTER_SET_B + #if !BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + + /* + * The main oscillation stabilization time countered by OSTC + * 0x80: 2^8/fx min + * 0xC0: 2^9/fx min + * 0xE0: 2^10/fx min + * 0xF0: 2^11/fx min + * 0xF8: 2^13/fx min + * 0xFC: 2^15/fx min + * 0xFE: 2^17/fx min + * 0xFF: 2^18/fx min + * Note: The oscillation stabilization time counter is not applied for External clock input. + */ + uint8_t mainosc_stable_value = (uint8_t) ~(BSP_PRV_OSTC_OFFSET >> BSP_CLOCK_CFG_MAIN_OSC_WAIT); + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSTC, mainosc_stable_value); + #endif + #else + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U); + #endif + #endif + } +#endif + + /* Start clocks that require other clocks. At this point, all dependent clocks are running and stable if needed. */ + +#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED + #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->PLL2CR) + #endif + { + R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR; + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + R_SYSTEM->PLL2CCR2 = BSP_PRV_PLL2CCR2; + #endif + + /* Start PLL2. */ + R_SYSTEM->PLL2CR = 0U; + } + #endif /* BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_ENABLE */ +#endif + +#if BSP_PRV_PLL_SUPPORTED && BSP_PRV_PLL_USED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + if (R_SYSTEM->PLLCR) + #endif + { + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR2 = (uint8_t) BSP_PRV_PLLCCR; + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if 6U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR = BSP_PRV_PLLCCR; + #else + R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; + #endif + R_SYSTEM->PLLCCR2 = (uint16_t) BSP_PRV_PLLCCR2; + #endif + + #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0 + + /* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some + * MCUs (see PLLSTP notes in "PLL Control Register (PLLCR)" description in the CGC section of the relevant hardware manual). + * Five loops are needed here to ensure the most efficient path takes at least 1 us from the setting of + * PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running + * while setting PLLCCR. */ + bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US)); + #endif + + #if BSP_MCU_GROUP_RA8_GEN2 && (BSP_CFG_CPU_CORE == 0) + + /* Do not access the CM85 ITCM, DTCM, I-Cache, or D-Cache during voltage scaling change. */ + /* Disable CM85 I-Cache allocations and invalidate for later coherence. */ + SCB_DisableICache(); + + /* Disable CM85 I-Cache and D-Cache lookups and allocations. D-Cache should already be clean and allocations disabled, so no cache maintenance required. */ + MEMSYSCTL->MSCR &= ~(MEMSYSCTL_MSCR_ICACTIVE_Msk | MEMSYSCTL_MSCR_DCACTIVE_Msk); + __DSB(); + __ISB(); + + /* Always set not high VSCR_1 (non-default), change before enabling PLL. + * - Note this will consume more power than necessary for certain configurations. See User Manual for more information. */ + R_SYSTEM->VSCR_b.VSCM = 0x1U; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VSCR_b.VSCMTSF, 0U); + + /* Re-enable CM85 I-Cache and D-Cache lookups and allow allocations per CCR.xC (TZ banked) bits . */ + MEMSYSCTL->MSCR |= (MEMSYSCTL_MSCR_ICACTIVE_Msk | MEMSYSCTL_MSCR_DCACTIVE_Msk); + __DSB(); + __ISB(); + SCB_EnableICache(); + #endif + + R_SYSTEM->PLLCR = 0U; + + #if BSP_PRV_STABILIZE_PLL + + /* Wait for PLL to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLLSF, 1U); + #endif + } +#endif + + /* Set source clock and dividers. */ +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + #if BSP_TZ_SECURE_BUILD + + /* In case of soft reset, make sure callback pointer is NULL initially. */ + g_bsp_clock_update_callback = NULL; + #endif + + #if BSP_FEATURE_CGC_HAS_CPUCLK + bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR, BSP_PRV_STARTUP_SCKDIVCR2); + #else + bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_PRV_STARTUP_SCKDIVCR, 0); + #endif + #else + bsp_prv_clock_set_hard_reset(); + #endif +#else + #if (1U == BSP_PRV_CLKOUT_SOURCE_SET) + bsp_prv_clock_set(BSP_CFG_CLKOUT_SOURCE, BSP_CFG_HOCO_DIV, BSP_CFG_MOCO_DIV, BSP_CFG_XTAL_DIV); + #elif (2U == BSP_PRV_CLKOUT_SOURCE_SET) + bsp_prv_clock_set(BSP_CFG_CLKOUT1_SOURCE, BSP_CFG_HOCO_DIV, BSP_CFG_MOCO_DIV, BSP_CFG_XTAL_DIV); + #endif + bsp_prv_clock_set(BSP_CFG_CLOCK_SOURCE, BSP_CFG_HOCO_DIV, BSP_CFG_MOCO_DIV, BSP_CFG_XTAL_DIV); +#endif + + /* If the MCU can run in a lower power mode, apply the optimal operating speed mode. */ +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_HIGH_SPEED + bsp_prv_operating_mode_set(BSP_PRV_STARTUP_OPERATING_MODE); + #endif +#endif + +#if defined(BSP_PRV_POWER_USE_DCDC) && (BSP_PRV_POWER_USE_DCDC == BSP_PRV_POWER_DCDC_STARTUP) && \ + (BSP_PRV_STARTUP_OPERATING_MODE <= BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) + + /* Start DCDC as part of BSP startup when configured (BSP_CFG_DCDC_ENABLE == 2). */ + R_BSP_PowerModeSet(BSP_CFG_DCDC_VOLTAGE_RANGE); +#endif + + /* Need to start BCLKA before selecting which BCLK will be used. */ +#if defined(BSP_CFG_BCLKA_SOURCE) && (BSP_CFG_BCLKA_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->BCKACR, &R_SYSTEM->BCKADIVCR, BSP_CFG_BCLKA_DIV, BSP_CFG_BCLKA_SOURCE); +#endif + + /* Configure BCLK if it exists on the MCU. */ +#ifdef BSP_CFG_BCLK_OUTPUT + #if BSP_CFG_BCLK_OUTPUT > 0U + #ifdef BSP_CFG_EBCLKA_SEL + R_SYSTEM->BCKCR = (BSP_CFG_BCLK_OUTPUT - 1U) | (BSP_CFG_EBCLKA_SEL << R_SYSTEM_BCKCR_EBCKASEL_Pos); + #else + R_SYSTEM->BCKCR = BSP_CFG_BCLK_OUTPUT - 1U; + #endif + R_SYSTEM->EBCKOCR = 1U; + #else + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + R_SYSTEM->EBCKOCR = 0U; + #endif + #endif +#endif + + /* Configure SDRAM clock if it exists on the MCU. */ +#ifdef BSP_CFG_SDCLK_OUTPUT + R_SYSTEM->SDCKOCR = BSP_CFG_SDCLK_OUTPUT; +#endif + + /* Configure CLKOUT. */ +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLOCK_DISABLED + #if BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET + R_SYSTEM->CKOCR = 0U; + #endif + #else + uint8_t ckocr = BSP_CFG_CLKOUT_SOURCE | (BSP_CFG_CLKOUT_DIV << BSP_PRV_CKOCR_CKODIV_BIT); + R_SYSTEM->CKOCR = ckocr; + ckocr |= (1U << BSP_PRV_CKOCR_CKOEN_BIT); + R_SYSTEM->CKOCR = ckocr; + #endif +#else + bsp_prv_clkout_set(); +#endif + +#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED + #if BSP_CFG_UCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + + /* If the USB clock has a divider setting in SCKDIVCR2. */ + #if BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV + R_SYSTEM->SCKDIVCR2 = BSP_PRV_UCK_DIV << BSP_PRV_SCKDIVCR2_UCK_BIT; + #endif /* BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV */ + + /* If there is a REQ bit in USBCKCR, then follow sequence from "USBCKCR : USB Clock Control Register" description in the CGC section of the relevant hardware manual. */ + #if BSP_FEATURE_USB_HAS_CLOCK_REQ + + /* Request to change the USB Clock. */ + R_SYSTEM->USBCKCR_b.USBCKSREQ = 1; + + /* Wait for the clock to be stopped. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->USBCKCR_b.USBCKSRDY, 1U); + + #if BSP_FEATURE_USB_HAS_USBCKDIVCR + + /* Write the settings. */ + R_SYSTEM->USBCKDIVCR = BSP_PRV_UCK_DIV; + #endif /* BSP_FEATURE_USB_HAS_USBCKDIVCR */ + + /* Select the USB Clock without enabling it. */ + R_SYSTEM->USBCKCR = BSP_CFG_UCLK_SOURCE | R_SYSTEM_USBCKCR_USBCKSREQ_Msk; + #endif /* BSP_FEATURE_USB_HAS_CLOCK_REQ */ + + #if BSP_FEATURE_USB_HAS_CLOCK_SEL + + /* Some MCUs use an alternate register for selecting the USB clock source. */ + #if BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT + #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_UCLK_SOURCE + + /* Write to USBCKCR to select the PLL. */ + R_SYSTEM->USBCKCR_ALT = 0; + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_UCLK_SOURCE + + /* Write to USBCKCR to select the HOCO. */ + R_SYSTEM->USBCKCR_ALT = 1; + #endif + #else + + /* Select the USB Clock. */ + R_SYSTEM->USBCKCR = BSP_CFG_UCLK_SOURCE; + #endif + #endif /* BSP_FEATURE_USB_HAS_CLOCK_REQ */ + + #if BSP_FEATURE_USB_HAS_CLOCK_REQ + + /* Wait for the USB Clock to be started. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->USBCKCR_b.USBCKSRDY, 0U); + #endif /* BSP_FEATURE_USB_HAS_CLOCK_REQ */ + #endif /* BSP_CFG_USB_ENABLE */ +#endif /* BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED */ + + /* Set the OCTASPI clock if it exists on the MCU (See "OCTACKCR : Octal-SPI Clock Control Register" description in the CGC section of the relevant hardware manual). */ +#if BSP_FEATURE_OSPI_HAS_CLOCK && BSP_CFG_OCTACLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + bsp_octaclk_settings_t octaclk_settings = + { + .source_clock = (bsp_clocks_source_t) BSP_CFG_OCTACLK_SOURCE, + .divider = (bsp_clocks_octaclk_div_t) BSP_CFG_OCTACLK_DIV + }; + R_BSP_OctaclkUpdate(&octaclk_settings); +#endif /* BSP_FEATURE_OSPI_HAS_CLOCK && BSP_CFG_OCTASPI_CLOCK_ENABLE */ + + /* Set the CANFD clock if it exists on the MCU */ +#if BSP_FEATURE_CANFD_HAS_CLOCK && (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) && \ + (BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + + bsp_peripheral_clock_set(&R_SYSTEM->CANFDCKCR, + &R_SYSTEM->CANFDCKDIVCR, + BSP_CFG_CANFDCLK_DIV, + BSP_CFG_CANFDCLK_SOURCE); +#endif + + /* Set the SCISPI clock if it exists on the MCU */ +#if BSP_FEATURE_SCI_HAS_SCISPI_CLOCK && (BSP_CFG_SCISPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->SCISPICKCR, + &R_SYSTEM->SCISPICKDIVCR, + BSP_CFG_SCISPICLK_DIV, + BSP_CFG_SCISPICLK_SOURCE); +#endif + + /* Set the SCI clock if it exists on the MCU */ +#if BSP_FEATURE_SCI_HAS_CLOCK && (BSP_CFG_SCICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->SCICKCR, &R_SYSTEM->SCICKDIVCR, BSP_CFG_SCICLK_DIV, BSP_CFG_SCICLK_SOURCE); +#endif + + /* Set the SPI clock if it exists on the MCU */ +#if BSP_FEATURE_SPI_HAS_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->SPICKCR, &R_SYSTEM->SPICKDIVCR, BSP_CFG_SPICLK_DIV, BSP_CFG_SPICLK_SOURCE); +#endif + + /* Set the GPT clock if it exists on the MCU */ +#if BSP_PERIPHERAL_GPT_GTCLK_PRESENT && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->GPTCKCR, &R_SYSTEM->GPTCKDIVCR, BSP_CFG_GPTCLK_DIV, BSP_CFG_GPTCLK_SOURCE); +#endif + + /* Set the IIC clock if it exists on the MCU */ +#if BSP_FEATURE_IIC_HAS_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->IICCKCR, &R_SYSTEM->IICCKDIVCR, BSP_CFG_IICCLK_DIV, BSP_CFG_IICCLK_SOURCE); +#endif + + /* Set the CEC clock if it exists on the MCU */ +#if BSP_FEATURE_CEC_HAS_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->CECCKCR, &R_SYSTEM->CECCKDIVCR, BSP_CFG_CECCLK_DIV, BSP_CFG_CECCLK_SOURCE); +#endif + + /* Set the I3C clock if it exists on the MCU */ +#if BSP_FEATURE_I3C_HAS_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->I3CCKCR, &R_SYSTEM->I3CCKDIVCR, BSP_CFG_I3CCLK_DIV, BSP_CFG_I3CCLK_SOURCE); +#endif + + /* Set the LCD clock if it exists on the MCU */ +#if BSP_FEATURE_LCD_HAS_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->LCDCKCR, &R_SYSTEM->LCDCKDIVCR, BSP_CFG_LCDCLK_DIV, BSP_CFG_LCDCLK_SOURCE); +#endif + + /* Set the USB-HS clock if it exists on the MCU */ +#if BSP_FEATURE_USB_HAS_USB60_CLOCK && (BSP_CFG_USB60CLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->USB60CKCR, + &R_SYSTEM->USB60CKDIVCR, + BSP_CFG_USB60CLK_DIV, + BSP_CFG_USB60CLK_SOURCE); +#endif + + /* Set the ADC clock if it exists on the MCU */ +#if BSP_FEATURE_ADC_HAS_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ADCCKCR, &R_SYSTEM->ADCCKDIVCR, BSP_CFG_ADCCLK_DIV, BSP_CFG_ADCCLK_SOURCE); +#endif + + /* Set the ESW clock if it exists on the MCU */ +#if BSP_FEATURE_ESWM_HAS_CLOCK && (BSP_CFG_ESWCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ESWCKCR, &R_SYSTEM->ESWCKDIVCR, BSP_CFG_ESWCLK_DIV, BSP_CFG_ESWCLK_SOURCE); +#endif + + /* Set the ESWPHY clock if it exists on the MCU */ +#if BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK && (BSP_CFG_ESWPHYCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ESWPCKCR, + &R_SYSTEM->ESWPCKDIVCR, + BSP_CFG_ESWPHYCLK_DIV, + BSP_CFG_ESWPHYCLK_SOURCE); +#endif + + /* Set the ETHPHY clock if it exists on the MCU */ +#if BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK && (BSP_CFG_ETHPHYCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ETHPCKCR, + &R_SYSTEM->ETHPCKDIVCR, + BSP_CFG_ETHPHYCLK_DIV, + BSP_CFG_ETHPHYCLK_SOURCE); +#endif + +#if BSP_FEATURE_BSP_HAS_DSMIF_CLOCK && \ + (BSP_CFG_DSMIFCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->DSMIFCKCR, + &R_SYSTEM->DSMIFCKDIVCR, + BSP_CFG_DSMIFCLK_DIV, + BSP_CFG_DSMIFCLK_SOURCE); +#endif + +#if BSP_FEATURE_BSP_HAS_ESC_CLOCK && \ + (BSP_CFG_ESCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->ESCCKCR, &R_SYSTEM->ESCCKDIVCR, BSP_CFG_ESCCLK_DIV, BSP_CFG_ESCCLK_SOURCE); +#endif + + /* Set the SDADC clock if it exists on the MCU. */ +#if BSP_FEATURE_SDADC_HAS_CLOCK && (BSP_CFG_SDADC_CLOCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + #if BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO + uint8_t sdadcckcr = 1U; + #elif BSP_CFG_SDADC_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_PLL + uint8_t sdadcckcr = 2U; + #else /* BSP_CLOCK_SOURCE_CLOCK_MOSC */ + uint8_t sdadcckcr = 0U; + #endif + + /* SDADC isn't controlled like the other peripheral clocks so we cannot use the generic setter. */ + R_SYSTEM->SDADCCKCR = sdadcckcr & R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk; +#endif + + /* Lock CGC and LPM protection registers. */ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_LOCK; +#else + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +#endif + +#if (BSP_FEATURE_FLASH_CACHE || defined(R_CACHE)) && BSP_FEATURE_FLASH_CACHE_DISABLE_OPM + R_BSP_FlashCacheEnable(); +#endif +} + +#if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + +/*******************************************************************************************************************//** + * This function is called during SOSC stabilization when Sub-Clock oscillator is populated. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to update the IWDT/WDT Refresh Register if an + * application starts IWDT/WDT automatically after reset. To use this function just copy this function into your own + * code and modify it to meet your needs. + * + * @param[in] delay_ms Stabilization Time for the clock. + **********************************************************************************************************************/ +void R_BSP_SubClockStabilizeWait (uint32_t delay_ms) +{ + /* Wait for clock to stabilize. */ + R_BSP_SoftwareDelay(delay_ms, BSP_DELAY_UNITS_MILLISECONDS); +} + +/*******************************************************************************************************************//** + * This function is called during SOSC registers initialization when Sub-Clock oscillator is populated. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to skip waiting for stabilization time after reset. + * To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] delay_ms Stabilization Time for the clock. + **********************************************************************************************************************/ +void R_BSP_SubClockStabilizeWaitAfterReset (uint32_t delay_ms) +{ + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) + + /* Wait for clock to stabilize after reset. */ + R_BSP_SoftwareDelay(delay_ms, BSP_DELAY_UNITS_MILLISECONDS); + #else + FSP_PARAMETER_NOT_USED(delay_ms); + #endif +} + +#endif + +#if (BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS == 1U) + +/*******************************************************************************************************************//** + * Set the peripheral clock on the MCU + * + * @param[in] p_clk_ctrl_reg Pointer to peripheral clock control register + * @param[in] p_clk_div_reg Pointer to peripheral clock division control register + * @param[in] peripheral_clk_div Peripheral clock division + * @param[in] peripheral_clk_source Peripheral clock source + * + * @return The wait states for FLWT required after the clock change (or 0 if FLWT does not exist). + **********************************************************************************************************************/ +static void bsp_peripheral_clock_set (volatile uint8_t * p_clk_ctrl_reg, + volatile uint8_t * p_clk_div_reg, + uint8_t peripheral_clk_div, + uint8_t peripheral_clk_source) +{ + /* Request to stop the peripheral clock. */ + *p_clk_ctrl_reg |= (uint8_t) BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK; + + /* Wait for the peripheral clock to stop. */ + FSP_HARDWARE_REGISTER_WAIT((uint8_t) ((*p_clk_ctrl_reg & BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK) >> + BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS), + 1U); + + /* Select the peripheral clock divisor and source. */ + *p_clk_div_reg = peripheral_clk_div; + *p_clk_ctrl_reg = peripheral_clk_source | BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK | + BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK; + + /* Request to start the peripheral clock. */ + *p_clk_ctrl_reg &= (uint8_t) ~BSP_PRV_PERIPHERAL_CLK_REQ_BIT_MASK; + + /* Wait for the peripheral clock to start. */ + FSP_HARDWARE_REGISTER_WAIT((uint8_t) ((*p_clk_ctrl_reg & BSP_PRV_PERIPHERAL_CLK_RDY_BIT_MASK) >> + BSP_PRV_PERIPHERAL_CLK_RDY_BIT_POS), + 0U); +} + +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + +/*******************************************************************************************************************//** + * Increases the ROM and RAM wait state settings to the minimum required based on the requested clock change. + * + * @param[in] requested_freq_hz New core clock frequency after the clock change. + * + * @return The wait states for FLWT required after the clock change (or 0 if FLWT does not exist). + **********************************************************************************************************************/ +static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz) +{ + uint8_t new_rom_wait_state = 0U; + + FSP_PARAMETER_NOT_USED(requested_freq_hz); + + #if BSP_FEATURE_CGC_HAS_SRAMWTSC + + /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */ + if (requested_freq_hz > BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS) + { + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif + + /* Execute data memory barrier before and after setting the wait states, See "Note of write to SRAMCR0, SRAMCR1 and SRAMECCRGN0 registers" + * in the SRAM section of the relevant hardware manual */ + __DMB(); + R_SRAM->SRAMWTSC = BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE; + __DMB(); + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif + #endif + } + #endif + + #if BSP_FEATURE_CGC_HAS_FLWT + + /* Calculate the wait states for ROM */ + #if BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS == 0 + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + + #elif BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS == 0 + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + + #elif BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS == 0 + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES; + } + + #elif BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS == 0 + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_FOUR_WAIT_CYCLES; + } + + #else + if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES; + } + else if (requested_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS) + { + new_rom_wait_state = BSP_PRV_ROM_FOUR_WAIT_CYCLES; + } + else + { + new_rom_wait_state = BSP_PRV_ROM_FIVE_WAIT_CYCLES; + } + #endif + + /* If more wait states are required after the change, then set the wait states before changing the clock. */ + if (new_rom_wait_state > R_FCACHE->FLWT) + { + R_FCACHE->FLWT = new_rom_wait_state; + } + #endif + + #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + + /* Set the wait state to MEMWAIT */ + bsp_clock_set_memwait(requested_freq_hz); + #endif + + #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + if (requested_freq_hz > BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ) + { + /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as + * a precondition to bsp_prv_clock_set. */ + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES; + } + #endif + + return new_rom_wait_state; +} + +/*******************************************************************************************************************//** + * Decreases the ROM and RAM wait state settings to the minimum supported based on the applied clock change. + * + * @param[in] updated_freq_hz New clock frequency after clock change + * @param[in] new_rom_wait_state Optimal value for FLWT if it exists, 0 if FLWT does not exist on the MCU + **********************************************************************************************************************/ +static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_wait_state) +{ + /* These variables are unused for some MCUs. */ + FSP_PARAMETER_NOT_USED(new_rom_wait_state); + FSP_PARAMETER_NOT_USED(updated_freq_hz); + + #if BSP_FEATURE_CGC_HAS_SRAMWTSC + + /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */ + if (updated_freq_hz <= BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS) + { + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_UNLOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; + #endif + + /* Execute data memory barrier before and after setting the wait states, See "Note of write to SRAMCR0, SRAMCR1 and SRAMECCRGN0 registers" + * in the SRAM section of the relevant hardware manual*/ + __DMB(); + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_WAIT_CYCLES_DISABLE; + __DMB(); + + /* Devices with TrustZone version 2 have a separate non-secure register for SRAM register protection. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SRAM->SRAMPRCR_NS = BSP_PRV_SRAM_LOCK; + #else + R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif + #endif + } + #endif + + #if BSP_FEATURE_CGC_HAS_FLWT + if (new_rom_wait_state != R_FCACHE->FLWT) + { + R_FCACHE->FLWT = new_rom_wait_state; + } + #endif + + #if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + + /* Set the wait state to MEMWAIT */ + bsp_clock_set_memwait(updated_freq_hz); + #endif + + #if BSP_FEATURE_CGC_HAS_FLDWAITR && !BSP_PRV_CLOCK_SUPPLY_TYPE_B + if (updated_freq_hz <= BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ) + { + BSP_PRV_FLDWAITR_REG_ACCESS = BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES; + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Set the wait state to MEMWAIT. + **********************************************************************************************************************/ +#if BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_PRV_CLOCK_SUPPLY_TYPE_B +static void bsp_clock_set_memwait (uint32_t updated_freq_hz) +{ + uint8_t memwait; + if ((updated_freq_hz > BSP_PRV_MEMWAIT_MAX_ONE_WAIT_FREQ) && + ((BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES & R_SYSTEM_MEMWAIT_MEMWAIT_Msk) != 0)) + { + /* The MCU must be in high speed mode to set wait states to 2. The MCU should already be in high speed mode as + * a precondition to bsp_prv_clock_set. */ + memwait = BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES; + } + else if (updated_freq_hz > BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ) + { + memwait = BSP_PRV_MEMWAIT_ONE_WAIT_CYCLES; + } + else + { + memwait = BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES; + } + + R_SYSTEM->MEMWAIT = memwait; +} + +#endif + +/*******************************************************************************************************************//** + * Initializes sub-clock according to the BSP configuration. + **********************************************************************************************************************/ +static void bsp_prv_sosc_init (void) +{ +#if BSP_FEATURE_CGC_HAS_SOSC + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #if BSP_FEATURE_RTC_IS_IRTC + #if ((BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL)) + + /* If sub-clock is used as system clock source or HOCO FLL source, wait for VRTC-domain become valid */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VRTSR_b.VRTVLD, 1); + #else + + /* Check if VRTC-domain area is valid. */ + if (1U == R_SYSTEM->VRTSR_b.VRTVLD) + #endif + #endif + { + #if !BSP_FEATURE_CGC_REGISTER_SET_B + if (R_SYSTEM->SOSCCR || (BSP_CLOCK_CFG_SUBCLOCK_DRIVE != R_SYSTEM->SOMCR_b.SODRV)) + { + /* If Sub-Clock Oscillator is started at reset, stop it before configuring the subclock drive. */ + if (0U == R_SYSTEM->SOSCCR) + { + /* Stop the Sub-Clock Oscillator to update the SOMCR register. */ + R_SYSTEM->SOSCCR = 1U; + + /* Allow a stop interval of at least 5 SOSC clock cycles before configuring the drive capacity + * and restarting Sub-Clock Oscillator. */ + R_BSP_SoftwareDelay(BSP_PRV_SUBCLOCK_STOP_INTERVAL_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* + * In the CGC section of the relevant hardware manual, SOSCCR : Sub-Clock Oscillator Control Register: + * When changing the value of the SOSTP bit, execute subsequent instructions + * only after reading the bit to check that the value is updated. + */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOSCCR, 1U); + } + + /* Configure the subclock drive as subclock is not running. */ + R_SYSTEM->SOMCR = + ((BSP_CLOCK_CFG_SUBCLOCK_DRIVE << BSP_FEATURE_CGC_SODRV_SHIFT) & BSP_FEATURE_CGC_SODRV_MASK); + #else + if (R_SYSTEM->SOSCCR) + { + #endif + + R_SYSTEM->SOSCCR = 0U; + + /* In the CGC sectin of the relevant hardware manual "SOSCCR : Sub-Clock Oscillator Control Register": + * After setting the SOSTP bit to 0, use the sub-clock only after the sub-clock + * oscillation stabilization time has elapsed. + */ + #if (BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE) || (BSP_PRV_HOCO_USE_FLL) + R_BSP_SubClockStabilizeWait(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); + #endif + } + else + { + /* + * RA MCUs like RA6M5 requires to use sub-clock after oscillation stabilization time + * has elapsed on Power-On-Reset. But, POR is not well supported on EK boards, so BSP + * has to wait on any reset. Please override this function in application if waiting + * for stabilization is not required. + */ + R_BSP_SubClockStabilizeWaitAfterReset(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS); + } + } + + #else + R_SYSTEM->SOSCCR = 1U; + #endif +#endif +} + +/*******************************************************************************************************************//** + * Octa-SPI clock update. + * @param[in] p_octaclk_setting Pointer to Octaclk setting structure which provides information regarding + * Octaclk source and divider settings to be applied. + * @note The requested Octaclk source must be started before calling this function. + **********************************************************************************************************************/ +void R_BSP_OctaclkUpdate (bsp_octaclk_settings_t * p_octaclk_setting) +{ +#if BSP_FEATURE_OSPI_HAS_CLOCK + #if BSP_FEATURE_OSPI_B_IS_AVAILABLE + #define OSPI_UNIT_COUNT BSP_FEATURE_OSPI_B_UNIT_COUNT + #else + #define OSPI_UNIT_COUNT (1U) + #endif + + /* Store initial value of CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + uint16_t bsp_prv_prcr_orig = R_SYSTEM->PRCR_NS; + #else + uint16_t bsp_prv_prcr_orig = R_SYSTEM->PRCR; + #endif + + /* Unlock CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = (uint16_t) BSP_PRV_PRCR_UNLOCK; + #else + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + #endif + + /* All OSPI_B peripherals need to be stopped before the clock change. + * Technical Update TN-RA*-A0147A/E. */ + uint32_t started_modules = 0; + for (uint32_t i = 0; i < OSPI_UNIT_COUNT; i++) + { + /* BSP_MSTP_BIT_FSP_IP_OSPI has a semi-colon at the end of the macro which messes up using + * it in an expression. Save the flag then if it is zero the IP is stopped. */ + const uint32_t ip_stopped = BSP_MSTP_REG_FSP_IP_OSPI(i) & BSP_MSTP_BIT_FSP_IP_OSPI(i); + if (0 == ip_stopped) + { + /* Save the module index as a flag then stop it. */ + started_modules |= (1U << i); + R_BSP_MODULE_STOP(FSP_IP_OSPI, i); + } + } + + /* Must wait 2 OCTACLK cycles after the module has been stopped before changing the clock: TU TN-RA*-A0147A/E. */ + const uint32_t octaclk_freq_hz = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) R_SYSTEM->OCTACKCR_b.OCTACKSEL) / + R_FSP_ClockDividerGet(R_SYSTEM->OCTACKDIVCR_b.OCTACKDIV); + const uint32_t octaclk_period_us = octaclk_freq_hz / BSP_PRV_HZ_PER_MHZ; + + R_BSP_SoftwareDelay(2U * octaclk_period_us, BSP_DELAY_UNITS_MICROSECONDS); + + /* Request to change the OCTASPI Clock. */ + R_SYSTEM->OCTACKCR_b.OCTACKSREQ = 1; + + /* Wait for the clock to be stopped. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 1U); + + /* Write the settings. */ + R_SYSTEM->OCTACKDIVCR = (uint8_t) p_octaclk_setting->divider; + R_SYSTEM->OCTACKCR = (uint8_t) (p_octaclk_setting->source_clock | R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk); + + /* Start the OCTASPI Clock by setting OCTACKSREQ to zero. */ + R_SYSTEM->OCTACKCR = (uint8_t) p_octaclk_setting->source_clock; + + /* Wait for the OCTASPI Clock to be started. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 0U); + + /* Restore any OSPI_B peripherals that were stopped. */ + for (uint32_t i = 0; i < OSPI_UNIT_COUNT; i++) + { + if (started_modules & (1U << i)) + { + R_BSP_MODULE_START(FSP_IP_OSPI, i); + } + } + + /* Restore CGC and LPM protection registers. */ + #if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + R_SYSTEM->PRCR_NS = BSP_PRV_PRCR_KEY | bsp_prv_prcr_orig; + #else + R_SYSTEM->PRCR = BSP_PRV_PRCR_KEY | bsp_prv_prcr_orig; + #endif +#else + FSP_PARAMETER_NOT_USED(p_octaclk_setting); +#endif +} + +/*******************************************************************************************************************//** + * Gets the frequency of a source clock. + * @param[in] clock Pointer to Octaclk setting structure which provides information regarding + * Octaclk source and divider settings to be applied. + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock) +{ + uint32_t source_clock = g_clock_freq[clock]; + + return source_clock; +} + +#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_RTC_HAS_VBTICTLR + +/*******************************************************************************************************************//** + * RTC Initialization + * + * Some RTC registers must be initialized after reset to ensure correct operation. + * This reset is not performed automatically if the RTC is used in a project as it will + * be handled by the RTC driver if needed. + **********************************************************************************************************************/ +void R_BSP_Init_RTC (void) +{ + /* Figure "Initialization procedure" in the RTC section of the relevant hardware manual */ + + /* RCKSEL bit is not initialized after reset. Use LOCO as the default + * clock source if it is available. Note RCR4.ROPSEL is also cleared. + */ + + #if BSP_FEATURE_RTC_IS_IRTC + if (0U == R_SYSTEM->VRTSR_b.VRTVLD) // Return if VRTC-domain is invalid + { + return; + } + #endif + #if !BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_PRV_LOCO_USED && !BSP_FEATURE_RTC_IS_IRTC + R_RTC->RCR4 = 1 << R_RTC_RCR4_RCKSEL_Pos; + #else + + /* Sses SOSC as clock source, or there is no clock source. */ + R_RTC->RCR4 = 0; + #endif + #endif + + #if !BSP_CFG_RTC_USED + #if BSP_PRV_LOCO_USED || (BSP_FEATURE_CGC_HAS_SOSC && BSP_CLOCK_CFG_SUBCLOCK_POPULATED) + #if !BSP_FEATURE_CGC_REGISTER_SET_B + + /*Wait for 6 clocks: 200 > (6*1000000) / 32K */ + R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + R_RTC->RCR2 = 0; + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2, 0); + + R_RTC->RCR2_b.RESET = 1; + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.RESET, 0); + + /* Disable RTC interrupts */ + R_RTC->RCR1 = 0; + + /* When the RCR1 register is modified, check that all the bits are updated before proceeding + * (see "RTC Control Register 1 (RCR1)" description in the RTC section of the relevant hardware manual)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR1, 0); + #endif + + #if BSP_FEATURE_RTC_HAS_TCEN + for (uint8_t index = 0U; index < BSP_FEATURE_RTC_RTCCR_CHANNELS; index++) + { + /* RTCCRn.TCEN must be cleared after reset. */ + R_RTC->RTCCR[index].RTCCR_b.TCEN = 0U; + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[index].RTCCR_b.TCEN, 0); + } + #endif + #endif + #endif + + #if BSP_FEATURE_RTC_HAS_VBTICTLR + + /* VBTICTLR.VCHnINEN must be cleared after reset. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + R_SYSTEM->VBTICTLR = 0U; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + #endif + + #if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable low power counter measures. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->LPOPT = R_SYSTEM_LPOPT_LPOPTEN_Msk; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /* Disable RTC Register Read/Write Clock to reduce power consumption. */ + bsp_prv_rtc_register_clock_set(false); + + /* Enable Asynchronous interrupts */ + R_ICU->IELEN = R_ICU_IELEN_RTCINTEN_Msk | R_ICU_IELEN_IELEN_Msk; + #endif +} + +#endif + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + +/*******************************************************************************************************************//** + * Enable or disable the RTC Register Read/Write Clock in order to save power. + **********************************************************************************************************************/ +bool bsp_prv_rtc_register_clock_set (bool enable) +{ + /* Save the previous state of RTCRWDIS. + * - RTCRWDIS = 0: Register Clock enabled. + * - RTCRWDIS = 1: Register Clock disabled. + */ + bool previous_state = !R_MSTP->LSMRWDIS_b.RTCRWDIS; + + if (previous_state == enable) + { + return previous_state; + } + + /* Critical section required when writing to registers that are shared between modules. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Set WREN. */ + R_MSTP->LSMRWDIS = BSP_PRV_LSMRDIS_KEY | R_MSTP_LSMRWDIS_WREN_Msk; + + /* Set RTCRWDIS and clear WREN. */ + R_MSTP->LSMRWDIS = BSP_PRV_LSMRDIS_KEY | !enable; + + /* Wait 2 cycles of PCLKB (See Table 3.2 "Access Cycles" in the RA2A2 user manual). */ + FSP_REGISTER_READ(R_MSTP->LSMRWDIS); + + FSP_CRITICAL_SECTION_EXIT; + + return previous_state; +} + +#endif + +#if BSP_FEATURE_RTC_IS_IRTC + +/*******************************************************************************************************************//** + * To check sub-clock status. + * + * @retval FSP_SUCCESS Sub-clock is ready to use. + * @retval FSP_ERR_INVALID_HW_CONDITION VRTC-domain area is invalid. + * @retval FSP_ERR_NOT_INITIALIZED Sub-clock has not been inititalized yet. + **********************************************************************************************************************/ +fsp_err_t R_BSP_SubclockStatusGet () +{ + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + + /* Check if VRTC-domain area is invalid */ + FSP_ERROR_RETURN(1U == R_SYSTEM->VRTSR_b.VRTVLD, FSP_ERR_INVALID_HW_CONDITION); + + /* Check if SOSC has been configured */ + if ((0U == R_SYSTEM->SOSCCR) && (BSP_CLOCK_CFG_SUBCLOCK_DRIVE == R_SYSTEM->SOMCR_b.SODRV)) + { + return FSP_SUCCESS; + } + #endif + + return FSP_ERR_NOT_INITIALIZED; +} + +/*******************************************************************************************************************//** + * To initialize the sub-clock. + * + * @retval FSP_SUCCESS Sub-clock successfully initialized. + * @retval FSP_ERR_INVALID_HW_CONDITION Sub-clock cannot be initialized. + **********************************************************************************************************************/ +fsp_err_t R_BSP_SubclockInitialize () +{ + #if BSP_CLOCK_CFG_SUBCLOCK_POPULATED + + /* Check if VRTC-domain area is valid */ + FSP_ERROR_RETURN(1U == R_SYSTEM->VRTSR_b.VRTVLD, FSP_ERR_INVALID_HW_CONDITION); + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + bsp_prv_sosc_init(); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + return FSP_SUCCESS; + #else + + return FSP_ERR_INVALID_HW_CONDITION; + #endif +} + +#endif + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_clocks.h new file mode 100644 index 0000000000..406618cec1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -0,0 +1,1793 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_CLOCKS_H +#define BSP_CLOCKS_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_clock_cfg.h" +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ +/* Must match SCKCR.CKSEL values. */ +#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if 0 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS + #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. + #endif + #if 0 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS + #define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. + #endif + #if (1 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS && 1 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) + #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P (BSP_CLOCKS_SOURCE_CLOCK_PLL) + #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P (BSP_CLOCKS_SOURCE_CLOCK_PLL2) + #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q (7) // The PLL1Q oscillator. + #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R (8) // The PLL1R oscillator. + #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q (9) // The PLL2Q oscillator. + #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R (10) // The PLL2R oscillator. + #endif +#else + +/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ +/* Must match ICLKSCR.CKSEL, FMAINSCR.CKSEL, FOCOSCR.CKSEL, FSUBSCR.CKSEL, OSMC.WUTMMCK0 and CKS0.CSEL values. */ + #define BSP_CLOCKS_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as System clock (ICLK) source. + #define BSP_CLOCKS_SOURCE_CLOCK_FSUB (1) // Use Sub System clock (FSUB) as System clock (ICLK) source. + #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO (0) // Use Main on-chip oscillator clock (FOCO) as Main System clock (FMAIN) source. + #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC (1) // Use Main clock oscillator (MOSC) as Main System clock (FMAIN) source. + #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO (0) // Use High-speed on-chip oscillator (HOCO) as Main on-chip oscillator clock (FOCO) source. + #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO (1) // Use Middle-speed on-chip oscillator (MOCO) as Main on-chip oscillator clock (FOCO) source. + #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK (0) // Use Sub-clock oscillator (SOSC) as Sub System clock (FSUB) source. + #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO (1) // Use Low-speed on-chip oscillator clock (LOCO) as Sub System clock (FSUB) source. + #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN (0) // Use Main System clock (FMAIN) as Clock Out (CLKOUT) source. + #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB (1) // Use Subsystem Clock (FSUB) as Clock Out (CLKOUT) source. + +/* Offset to convert OSTS setting to OSTC value (OSTC = ~(BSP_PRV_OSTC_OFFSET >> OSTS)) */ + #define BSP_PRV_OSTC_OFFSET (0x7FU) + +#endif + +/* PLLs are not supported in the following scenarios: + * - When using low voltage mode + * - When using an MCU that does not have a PLL + * - When the PLL only accepts the main oscillator as a source and XTAL is not used + */ +#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ + !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) + #define BSP_PRV_PLL_SUPPORTED (1) + #if BSP_FEATURE_CGC_HAS_PLL2 + #define BSP_PRV_PLL2_SUPPORTED (1) + #else + #define BSP_PRV_PLL2_SUPPORTED (0) + #endif +#else + #define BSP_PRV_PLL_SUPPORTED (0) + #define BSP_PRV_PLL2_SUPPORTED (0) +#endif + +/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency + * calculated here is also used to initialize the g_clock_freq array. */ +#if BSP_PRV_PLL_SUPPORTED + #if ((1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)) && \ + (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #else + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #endif +#endif +#if BSP_PRV_PLL2_SUPPORTED + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #else + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #endif +#endif + +#define BSP_MOCO_FREQ_HZ (BSP_MOCO_HZ) + +/* Frequencies of clocks with fixed freqencies. */ +#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz +#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz + +#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #endif + #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ + (BSP_CFG_PLL_DIV + 1U)) + #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ + (BSP_CFG_PLL_DIV)) + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_PLL1P_FREQUENCY_HZ) + #endif +#endif + +/* Convert divisor bitfield settings into divisor values to calculate startup clocks */ +#define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div))) +#define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV) + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV) +#else + #define BSP_PRV_ICLK_DIV_VALUE (1U << BSP_CFG_ICLK_DIV) +#endif + +#define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV) +#define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV) +#define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV) +#define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV) +#define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV) +#define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV) +#define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV) +#define BSP_PRV_MRICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_MRICLK_DIV) + +/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have + * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ +#define BSP_STARTUP_CPUCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE) +#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE) +#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE) +#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE) +#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE) +#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE) +#define BSP_STARTUP_PCLKE_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE) +#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE) +#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE) +#define BSP_STARTUP_MRICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_MRICLK_DIV_VALUE) + +/* System clock divider options. */ +#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. +#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. +#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. +#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. +#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. +#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. +#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. +#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). +#define BSP_CLOCKS_SYS_CLOCK_DIV_3 (8) // System clock divided by 3. +#define BSP_CLOCKS_SYS_CLOCK_DIV_6 (9) // System clock divided by 6. +#define BSP_CLOCKS_SYS_CLOCK_DIV_12 (10) // System clock divided by 12. +#define BSP_CLOCKS_SYS_CLOCK_DIV_24 (11) // System clock divided by 24. + +/* USB clock divider options. */ +#define BSP_CLOCKS_USB_CLOCK_DIV_1 (0) // Divide USB source clock by 1 +#define BSP_CLOCKS_USB_CLOCK_DIV_2 (1) // Divide USB source clock by 2 +#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 +#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 +#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 +#define BSP_CLOCKS_USB_CLOCK_DIV_6 (5) // Divide USB source clock by 6 +#define BSP_CLOCKS_USB_CLOCK_DIV_8 (7) // Divide USB source clock by 8 +#define BSP_CLOCKS_USB_CLOCK_DIV_10 (9) // Divide USB source clock by 10 +#define BSP_CLOCKS_USB_CLOCK_DIV_16 (15) // Divide USB source clock by 16 +#define BSP_CLOCKS_USB_CLOCK_DIV_32 (9) // Divide USB source clock by 32 + +/* USB60 clock divider options. */ +#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 +#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2 +#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3 +#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4 +#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 +#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 +#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 +#define BSP_CLOCKS_USB60_CLOCK_DIV_10 (7) // Divide USB60 source clock by 10 +#define BSP_CLOCKS_USB60_CLOCK_DIV_16 (8) // Divide USB60 source clock by 16 +#define BSP_CLOCKS_USB60_CLOCK_DIV_32 (9) // Divide USB60 source clock by 32 + +/* GLCD clock divider options. */ +#define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 +#define BSP_CLOCKS_LCD_CLOCK_DIV_2 (1) // Divide LCD source clock by 2 +#define BSP_CLOCKS_LCD_CLOCK_DIV_3 (5) // Divide LCD source clock by 3 +#define BSP_CLOCKS_LCD_CLOCK_DIV_4 (2) // Divide LCD source clock by 4 +#define BSP_CLOCKS_LCD_CLOCK_DIV_5 (6) // Divide LCD source clock by 5 +#define BSP_CLOCKS_LCD_CLOCK_DIV_6 (3) // Divide LCD source clock by 6 +#define BSP_CLOCKS_LCD_CLOCK_DIV_8 (4) // Divide LCD source clock by 8 +#define BSP_CLOCKS_LCD_CLOCK_DIV_10 (7) // Divide LCD source clock by 10 +#define BSP_CLOCKS_LCD_CLOCK_DIV_16 (8) // Divide LCD source clock by 16 +#define BSP_CLOCKS_LCD_CLOCK_DIV_32 (9) // Divide LCD source clock by 32 + +/* OCTA clock divider options. */ +#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_3 (5) // Divide OCTA source clock by 3 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_5 (6) // Divide OCTA source clock by 5 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_10 (7) // Divide OCTA source clock by 10 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_16 (8) // Divide OCTA source clock by 16 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_32 (9) // Divide OCTA source clock by 32 + +/* CANFD clock divider options. */ +#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_10 (7) // Divide CANFD source clock by 10 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_16 (8) // Divide CANFD source clock by 16 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_32 (9) // Divide CANFD source clock by 32 + +/* SCI clock divider options. */ +#define BSP_CLOCKS_SCI_CLOCK_DIV_1 (0) // Divide SCI source clock by 1 +#define BSP_CLOCKS_SCI_CLOCK_DIV_2 (1) // Divide SCI source clock by 2 +#define BSP_CLOCKS_SCI_CLOCK_DIV_3 (5) // Divide SCI source clock by 3 +#define BSP_CLOCKS_SCI_CLOCK_DIV_4 (2) // Divide SCI source clock by 4 +#define BSP_CLOCKS_SCI_CLOCK_DIV_5 (6) // Divide SCI source clock by 5 +#define BSP_CLOCKS_SCI_CLOCK_DIV_6 (3) // Divide SCI source clock by 6 +#define BSP_CLOCKS_SCI_CLOCK_DIV_8 (4) // Divide SCI source clock by 8 +#define BSP_CLOCKS_SCI_CLOCK_DIV_10 (7) // Divide SCI source clock by 10 +#define BSP_CLOCKS_SCI_CLOCK_DIV_16 (8) // Divide SCI source clock by 16 +#define BSP_CLOCKS_SCI_CLOCK_DIV_32 (9) // Divide SCI source clock by 32 + +/* SPI clock divider options. */ +#define BSP_CLOCKS_SPI_CLOCK_DIV_1 (0) // Divide SPI source clock by 1 +#define BSP_CLOCKS_SPI_CLOCK_DIV_2 (1) // Divide SPI source clock by 2 +#define BSP_CLOCKS_SPI_CLOCK_DIV_3 (5) // Divide SPI source clock by 3 +#define BSP_CLOCKS_SPI_CLOCK_DIV_4 (2) // Divide SPI source clock by 4 +#define BSP_CLOCKS_SPI_CLOCK_DIV_5 (6) // Divide SPI source clock by 5 +#define BSP_CLOCKS_SPI_CLOCK_DIV_6 (3) // Divide SPI source clock by 6 +#define BSP_CLOCKS_SPI_CLOCK_DIV_8 (4) // Divide SPI source clock by 8 +#define BSP_CLOCKS_SPI_CLOCK_DIV_10 (7) // Divide SPI source clock by 10 +#define BSP_CLOCKS_SPI_CLOCK_DIV_16 (8) // Divide SPI source clock by 16 +#define BSP_CLOCKS_SPI_CLOCK_DIV_32 (9) // Divide SPI source clock by 32 + +/* SCISPI clock divider options. */ +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 + +/* GPT clock divider options. */ +#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 +#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 +#define BSP_CLOCKS_GPT_CLOCK_DIV_3 (5) // Divide GPT source clock by 3 +#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 +#define BSP_CLOCKS_GPT_CLOCK_DIV_5 (6) // Divide GPT source clock by 5 +#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 +#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 +#define BSP_CLOCKS_GPT_CLOCK_DIV_10 (7) // Divide GPT source clock by 10 +#define BSP_CLOCKS_GPT_CLOCK_DIV_16 (8) // Divide GPT source clock by 16 +#define BSP_CLOCKS_GPT_CLOCK_DIV_32 (9) // Divide GPT source clock by 32 + +/* IIC clock divider options. */ +#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 +#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 +#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 +#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 +#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 + +/* CEC clock divider options. */ +#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1 +#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2 + +/* I3C clock divider options. */ +#define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1 +#define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2 +#define BSP_CLOCKS_I3C_CLOCK_DIV_3 (5) // Divide I3C source clock by 3 +#define BSP_CLOCKS_I3C_CLOCK_DIV_4 (2) // Divide I3C source clock by 4 +#define BSP_CLOCKS_I3C_CLOCK_DIV_5 (6) // Divide I3C source clock by 5 +#define BSP_CLOCKS_I3C_CLOCK_DIV_6 (3) // Divide I3C source clock by 6 +#define BSP_CLOCKS_I3C_CLOCK_DIV_8 (4) // Divide I3C source clock by 8 +#define BSP_CLOCKS_I3C_CLOCK_DIV_10 (7) // Divide I3C source clock by 10 +#define BSP_CLOCKS_I3C_CLOCK_DIV_16 (8) // Divide I3C source clock by 16 +#define BSP_CLOCKS_I3C_CLOCK_DIV_32 (9) // Divide I3C source clock by 32 + +/* ADC clock divider options. */ +#define BSP_CLOCKS_ADC_CLOCK_DIV_1 (0) // Divide ADC source clock by 1 +#define BSP_CLOCKS_ADC_CLOCK_DIV_2 (1) // Divide ADC source clock by 2 +#define BSP_CLOCKS_ADC_CLOCK_DIV_3 (5) // Divide ADC source clock by 3 +#define BSP_CLOCKS_ADC_CLOCK_DIV_4 (2) // Divide ADC source clock by 4 +#define BSP_CLOCKS_ADC_CLOCK_DIV_5 (6) // Divide ADC source clock by 5 +#define BSP_CLOCKS_ADC_CLOCK_DIV_6 (3) // Divide ADC source clock by 6 +#define BSP_CLOCKS_ADC_CLOCK_DIV_8 (4) // Divide ADC source clock by 8 +#define BSP_CLOCKS_ADC_CLOCK_DIV_10 (7) // Divide ADC source clock by 10 +#define BSP_CLOCKS_ADC_CLOCK_DIV_16 (8) // Divide ADC source clock by 16 +#define BSP_CLOCKS_ADC_CLOCK_DIV_32 (9) // Divide ADC source clock by 32 + +/* ESW clock divider options. */ +#define BSP_CLOCKS_ESW_CLOCK_DIV_1 (0) // Divide ESW source clock by 1 +#define BSP_CLOCKS_ESW_CLOCK_DIV_2 (1) // Divide ESW source clock by 2 +#define BSP_CLOCKS_ESW_CLOCK_DIV_3 (5) // Divide ESW source clock by 3 +#define BSP_CLOCKS_ESW_CLOCK_DIV_4 (2) // Divide ESW source clock by 4 +#define BSP_CLOCKS_ESW_CLOCK_DIV_5 (6) // Divide ESW source clock by 5 +#define BSP_CLOCKS_ESW_CLOCK_DIV_6 (3) // Divide ESW source clock by 6 +#define BSP_CLOCKS_ESW_CLOCK_DIV_8 (4) // Divide ESW source clock by 8 +#define BSP_CLOCKS_ESW_CLOCK_DIV_10 (7) // Divide ESW source clock by 10 +#define BSP_CLOCKS_ESW_CLOCK_DIV_16 (8) // Divide ESW source clock by 16 +#define BSP_CLOCKS_ESW_CLOCK_DIV_32 (9) // Divide ESW source clock by 32 + +/* ESWPHY clock divider options. */ +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_1 (0) // Divide ESWPHY source clock by 1 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_2 (1) // Divide ESWPHY source clock by 2 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_3 (5) // Divide ESWPHY source clock by 3 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_4 (2) // Divide ESWPHY source clock by 4 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_5 (6) // Divide ESWPHY source clock by 5 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_6 (3) // Divide ESWPHY source clock by 6 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_8 (4) // Divide ESWPHY source clock by 8 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_10 (7) // Divide ESWPHY source clock by 10 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_16 (8) // Divide ESWPHY source clock by 16 +#define BSP_CLOCKS_ESWPHY_CLOCK_DIV_32 (9) // Divide ESWPHY source clock by 32 + +/* ETHPHY clock divider options. */ +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_1 (0) // Divide ETHPHY source clock by 1 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_2 (1) // Divide ETHPHY source clock by 2 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_3 (5) // Divide ETHPHY source clock by 3 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_4 (2) // Divide ETHPHY source clock by 4 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_5 (6) // Divide ETHPHY source clock by 5 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_6 (3) // Divide ETHPHY source clock by 6 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_8 (4) // Divide ETHPHY source clock by 8 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_10 (7) // Divide ETHPHY source clock by 10 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_16 (8) // Divide ETHPHY source clock by 16 +#define BSP_CLOCKS_ETHPHY_CLOCK_DIV_32 (9) // Divide ETHPHY source clock by 32 + +/* BCLKA clock divider options. */ +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_1 (0) // Divide BCLKA source clock by 1 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_2 (1) // Divide BCLKA source clock by 2 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_3 (5) // Divide BCLKA source clock by 3 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_4 (2) // Divide BCLKA source clock by 4 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_5 (6) // Divide BCLKA source clock by 5 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_6 (3) // Divide BCLKA source clock by 6 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_8 (4) // Divide BCLKA source clock by 8 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_10 (7) // Divide BCLKA source clock by 10 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_16 (8) // Divide BCLKA source clock by 16 +#define BSP_CLOCKS_BCLKA_CLOCK_DIV_32 (9) // Divide BCLKA source clock by 32 + +/* SAU clock divider options. */ +#define BSP_CLOCKS_SAU_CLOCK_DIV_1 (0) // Divide SAU source clock by 1 +#define BSP_CLOCKS_SAU_CLOCK_DIV_2 (1) // Divide SAU source clock by 2 +#define BSP_CLOCKS_SAU_CLOCK_DIV_4 (2) // Divide SAU source clock by 4 +#define BSP_CLOCKS_SAU_CLOCK_DIV_8 (3) // Divide SAU source clock by 8 +#define BSP_CLOCKS_SAU_CLOCK_DIV_16 (4) // Divide SAU source clock by 16 +#define BSP_CLOCKS_SAU_CLOCK_DIV_32 (5) // Divide SAU source clock by 32 +#define BSP_CLOCKS_SAU_CLOCK_DIV_64 (6) // Divide SAU source clock by 64 +#define BSP_CLOCKS_SAU_CLOCK_DIV_128 (7) // Divide SAU source clock by 128 +#define BSP_CLOCKS_SAU_CLOCK_DIV_256 (8) // Divide SAU source clock by 256 +#define BSP_CLOCKS_SAU_CLOCK_DIV_512 (9) // Divide SAU source clock by 512 +#define BSP_CLOCKS_SAU_CLOCK_DIV_1024 (10) // Divide SAU source clock by 1024 +#define BSP_CLOCKS_SAU_CLOCK_DIV_2048 (11) // Divide SAU source clock by 2048 +#define BSP_CLOCKS_SAU_CLOCK_DIV_4096 (12) // Divide SAU source clock by 4096 +#define BSP_CLOCKS_SAU_CLOCK_DIV_8192 (13) // Divide SAU source clock by 8192 +#define BSP_CLOCKS_SAU_CLOCK_DIV_16384 (14) // Divide SAU source clock by 16384 +#define BSP_CLOCKS_SAU_CLOCK_DIV_32768 (15) // Divide SAU source clock by 32768 + +/* Extra peripheral 0 clock divider options. */ +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_1 (0) // Divide extra peripheral 0 source clock by 1 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_2 (1) // Divide extra peripheral 0 source clock by 2 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_3 (5) // Divide extra peripheral 0 source clock by 3 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_4 (2) // Divide extra peripheral 0 source clock by 4 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_5 (6) // Divide extra peripheral 0 source clock by 5 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_6 (3) // Divide extra peripheral 0 source clock by 6 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_8 (4) // Divide extra peripheral 0 source clock by 8 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_10 (7) // Divide extra peripheral 0 source clock by 10 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_16 (8) // Divide extra peripheral 0 source clock by 16 +#define BSP_CLOCKS_DSMIF_CLOCK_DIV_32 (9) // Divide extra peripheral 0 source clock by 32 + +/* Extra peripheral 1 clock divider options. */ +#define BSP_CLOCKS_ESC_CLOCK_DIV_1 (0) // Divide extra peripheral 1 source clock by 1 +#define BSP_CLOCKS_ESC_CLOCK_DIV_2 (1) // Divide extra peripheral 1 source clock by 2 +#define BSP_CLOCKS_ESC_CLOCK_DIV_3 (5) // Divide extra peripheral 1 source clock by 3 +#define BSP_CLOCKS_ESC_CLOCK_DIV_4 (2) // Divide extra peripheral 1 source clock by 4 +#define BSP_CLOCKS_ESC_CLOCK_DIV_5 (6) // Divide extra peripheral 1 source clock by 5 +#define BSP_CLOCKS_ESC_CLOCK_DIV_6 (3) // Divide extra peripheral 1 source clock by 6 +#define BSP_CLOCKS_ESC_CLOCK_DIV_8 (4) // Divide extra peripheral 1 source clock by 8 +#define BSP_CLOCKS_ESC_CLOCK_DIV_10 (7) // Divide extra peripheral 1 source clock by 10 +#define BSP_CLOCKS_ESC_CLOCK_DIV_16 (8) // Divide extra peripheral 1 source clock by 16 +#define BSP_CLOCKS_ESC_CLOCK_DIV_32 (9) // Divide extra peripheral 1 source clock by 32 + +/* PLL divider options. */ +#define BSP_CLOCKS_PLL_DIV_1 (0) +#define BSP_CLOCKS_PLL_DIV_2 (1) +#define BSP_CLOCKS_PLL_DIV_3 (2) +#define BSP_CLOCKS_PLL_DIV_4 (3) +#define BSP_CLOCKS_PLL_DIV_5 (4) +#define BSP_CLOCKS_PLL_DIV_6 (5) +#define BSP_CLOCKS_PLL_DIV_8 (7) +#define BSP_CLOCKS_PLL_DIV_9 (8) +#define BSP_CLOCKS_PLL_DIV_1_5 (9) +#define BSP_CLOCKS_PLL_DIV_16 (15) + +/* PLL multiplier options. */ +#if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) + +/* Offset from decimal multiplier to register value for PLLCCR type 4. */ + #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET (574) + +/** + * X=Integer portion of the multiplier. + * Y=Fractional portion of the multiplier. (not used for this PLLCCR type) + */ + #define BSP_CLOCKS_PLL_MUL(X, Y) (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET) + +#elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) + +/** + * X=Integer portion of the multiplier. + * Y=Fractional portion of the multiplier. + */ + #define BSP_CLOCKS_PLL_MUL(X, Y) (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U) + +#else + + #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT (2U) + #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK (0x3U) + #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT (0U) + +/** + * X=Integer portion of the multiplier. + * Y=Fractional portion of the multiplier. + */ + #define BSP_CLOCKS_PLL_MUL(X, Y) ((((X) -1U) << 2UL) | ((Y) == 50U ? 3U : ((Y) / 33UL))) + +#endif + +/* Configuration option used to disable clock output. */ +#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) + +/* HOCO cycles per microsecond. */ +#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) + +/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ +#if BSP_HOCO_HZ < 48000000U + #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) +#else + #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) +#endif + +/* Create a mask of valid bits in SCKDIVCR. */ +#define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) +#if BSP_FEATURE_CGC_HAS_PCLKD + #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0) +#else + #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKC + #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4) +#else + #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKB + #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8) +#else + #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKA + #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12) +#else + #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16) +#else + #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKE + #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24) +#else + #define BSP_PRV_SCKDIVCR_PCLKE_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_FCLK + #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28) +#else + #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) +#endif +#define BSP_PRV_SCKDIVCR_MASK (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK | \ + BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \ + BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK | \ + BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK) + +/* FLL is only used when enabled, present and the subclock is populated. */ +#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_PRV_HOCO_USE_FLL (1) + #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US + #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) + #endif +#else + #define BSP_PRV_HOCO_USE_FLL (0) + #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) +#endif + +#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_RTC_HAS_VBTICTLR + #define BSP_PRV_RTC_RESET_DELAY_US (200) +#endif + +/* Operating power control modes. */ +#if BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_PRV_OPERATING_MODE_LOW_SPEED (1U) // Should match FLMODE low speed + #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (2U) // Should match FLMODE middle speed + #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (3U) // Should match FLMODE high speed +#else + #define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed + #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed + #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage + #define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed +#endif +#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +typedef struct +{ + uint32_t pll_freq; +} bsp_clock_update_callback_args_t; + + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #endif + +#endif + +/** PLL multiplier values */ +typedef enum e_cgc_pll_mul +{ + CGC_PLL_MUL_4_0 = BSP_CLOCKS_PLL_MUL(4U, 0U), ///< PLL multiplier of 4.00 + CGC_PLL_MUL_4_5 = BSP_CLOCKS_PLL_MUL(4U, 50U), ///< PLL multiplier of 4.50 + CGC_PLL_MUL_5_0 = BSP_CLOCKS_PLL_MUL(5U, 0U), ///< PLL multiplier of 5.00 + CGC_PLL_MUL_5_5 = BSP_CLOCKS_PLL_MUL(5U, 50U), ///< PLL multiplier of 5.50 + CGC_PLL_MUL_6_0 = BSP_CLOCKS_PLL_MUL(6U, 0U), ///< PLL multiplier of 6.00 + CGC_PLL_MUL_6_5 = BSP_CLOCKS_PLL_MUL(6U, 50U), ///< PLL multiplier of 6.50 + CGC_PLL_MUL_7_0 = BSP_CLOCKS_PLL_MUL(7U, 0U), ///< PLL multiplier of 7.00 + CGC_PLL_MUL_7_5 = BSP_CLOCKS_PLL_MUL(7U, 50U), ///< PLL multiplier of 7.50 + CGC_PLL_MUL_8_0 = BSP_CLOCKS_PLL_MUL(8U, 0U), ///< PLL multiplier of 8.00 + CGC_PLL_MUL_8_5 = BSP_CLOCKS_PLL_MUL(8U, 50U), ///< PLL multiplier of 8.50 + CGC_PLL_MUL_9_0 = BSP_CLOCKS_PLL_MUL(9U, 0U), ///< PLL multiplier of 9.00 + CGC_PLL_MUL_9_5 = BSP_CLOCKS_PLL_MUL(9U, 50U), ///< PLL multiplier of 9.50 + CGC_PLL_MUL_10_0 = BSP_CLOCKS_PLL_MUL(10U, 0U), ///< PLL multiplier of 10.00 + CGC_PLL_MUL_10_5 = BSP_CLOCKS_PLL_MUL(10U, 50U), ///< PLL multiplier of 10.50 + CGC_PLL_MUL_11_0 = BSP_CLOCKS_PLL_MUL(11U, 0U), ///< PLL multiplier of 11.00 + CGC_PLL_MUL_11_5 = BSP_CLOCKS_PLL_MUL(11U, 50U), ///< PLL multiplier of 11.50 + CGC_PLL_MUL_12_0 = BSP_CLOCKS_PLL_MUL(12U, 0U), ///< PLL multiplier of 12.00 + CGC_PLL_MUL_12_5 = BSP_CLOCKS_PLL_MUL(12U, 50U), ///< PLL multiplier of 12.50 + CGC_PLL_MUL_13_0 = BSP_CLOCKS_PLL_MUL(13U, 0U), ///< PLL multiplier of 13.00 + CGC_PLL_MUL_13_5 = BSP_CLOCKS_PLL_MUL(13U, 50U), ///< PLL multiplier of 13.50 + CGC_PLL_MUL_14_0 = BSP_CLOCKS_PLL_MUL(14U, 0U), ///< PLL multiplier of 14.00 + CGC_PLL_MUL_14_5 = BSP_CLOCKS_PLL_MUL(14U, 50U), ///< PLL multiplier of 14.50 + CGC_PLL_MUL_15_0 = BSP_CLOCKS_PLL_MUL(15U, 0U), ///< PLL multiplier of 15.00 + CGC_PLL_MUL_15_5 = BSP_CLOCKS_PLL_MUL(15U, 50U), ///< PLL multiplier of 15.50 + CGC_PLL_MUL_16_0 = BSP_CLOCKS_PLL_MUL(16U, 0U), ///< PLL multiplier of 16.00 + CGC_PLL_MUL_16_5 = BSP_CLOCKS_PLL_MUL(16U, 50U), ///< PLL multiplier of 16.50 + CGC_PLL_MUL_17_0 = BSP_CLOCKS_PLL_MUL(17U, 0U), ///< PLL multiplier of 17.00 + CGC_PLL_MUL_17_5 = BSP_CLOCKS_PLL_MUL(17U, 50U), ///< PLL multiplier of 17.50 + CGC_PLL_MUL_18_0 = BSP_CLOCKS_PLL_MUL(18U, 0U), ///< PLL multiplier of 18.00 + CGC_PLL_MUL_18_5 = BSP_CLOCKS_PLL_MUL(18U, 50U), ///< PLL multiplier of 18.50 + CGC_PLL_MUL_19_0 = BSP_CLOCKS_PLL_MUL(19U, 0U), ///< PLL multiplier of 19.00 + CGC_PLL_MUL_19_5 = BSP_CLOCKS_PLL_MUL(19U, 50U), ///< PLL multiplier of 19.50 + CGC_PLL_MUL_20_0 = BSP_CLOCKS_PLL_MUL(20U, 0U), ///< PLL multiplier of 20.00 + CGC_PLL_MUL_20_5 = BSP_CLOCKS_PLL_MUL(20U, 50U), ///< PLL multiplier of 20.50 + CGC_PLL_MUL_21_0 = BSP_CLOCKS_PLL_MUL(21U, 0U), ///< PLL multiplier of 21.00 + CGC_PLL_MUL_21_5 = BSP_CLOCKS_PLL_MUL(21U, 50U), ///< PLL multiplier of 21.50 + CGC_PLL_MUL_22_0 = BSP_CLOCKS_PLL_MUL(22U, 0U), ///< PLL multiplier of 22.00 + CGC_PLL_MUL_22_5 = BSP_CLOCKS_PLL_MUL(22U, 50U), ///< PLL multiplier of 22.50 + CGC_PLL_MUL_23_0 = BSP_CLOCKS_PLL_MUL(23U, 0U), ///< PLL multiplier of 23.00 + CGC_PLL_MUL_23_5 = BSP_CLOCKS_PLL_MUL(23U, 50U), ///< PLL multiplier of 23.50 + CGC_PLL_MUL_24_0 = BSP_CLOCKS_PLL_MUL(24U, 0U), ///< PLL multiplier of 24.00 + CGC_PLL_MUL_24_5 = BSP_CLOCKS_PLL_MUL(24U, 50U), ///< PLL multiplier of 24.50 + CGC_PLL_MUL_25_0 = BSP_CLOCKS_PLL_MUL(25U, 0U), ///< PLL multiplier of 25.00 + CGC_PLL_MUL_25_5 = BSP_CLOCKS_PLL_MUL(25U, 50U), ///< PLL multiplier of 25.50 + CGC_PLL_MUL_26_0 = BSP_CLOCKS_PLL_MUL(26U, 0U), ///< PLL multiplier of 26.00 + CGC_PLL_MUL_26_33 = BSP_CLOCKS_PLL_MUL(26U, 33U), ///< PLL multiplier of 26.33 + CGC_PLL_MUL_26_5 = BSP_CLOCKS_PLL_MUL(26U, 50U), ///< PLL multiplier of 26.50 + CGC_PLL_MUL_26_66 = BSP_CLOCKS_PLL_MUL(26U, 66U), ///< PLL multiplier of 26.66 + CGC_PLL_MUL_27_0 = BSP_CLOCKS_PLL_MUL(27U, 0U), ///< PLL multiplier of 27.00 + CGC_PLL_MUL_27_33 = BSP_CLOCKS_PLL_MUL(27U, 33U), ///< PLL multiplier of 27.33 + CGC_PLL_MUL_27_5 = BSP_CLOCKS_PLL_MUL(27U, 50U), ///< PLL multiplier of 27.50 + CGC_PLL_MUL_27_66 = BSP_CLOCKS_PLL_MUL(27U, 66U), ///< PLL multiplier of 27.66 + CGC_PLL_MUL_28_0 = BSP_CLOCKS_PLL_MUL(28U, 0U), ///< PLL multiplier of 28.00 + CGC_PLL_MUL_28_33 = BSP_CLOCKS_PLL_MUL(28U, 33U), ///< PLL multiplier of 28.33 + CGC_PLL_MUL_28_5 = BSP_CLOCKS_PLL_MUL(28U, 50U), ///< PLL multiplier of 28.50 + CGC_PLL_MUL_28_66 = BSP_CLOCKS_PLL_MUL(28U, 66U), ///< PLL multiplier of 28.66 + CGC_PLL_MUL_29_0 = BSP_CLOCKS_PLL_MUL(29U, 0U), ///< PLL multiplier of 29.00 + CGC_PLL_MUL_29_33 = BSP_CLOCKS_PLL_MUL(29U, 33U), ///< PLL multiplier of 29.33 + CGC_PLL_MUL_29_5 = BSP_CLOCKS_PLL_MUL(29U, 50U), ///< PLL multiplier of 29.50 + CGC_PLL_MUL_29_66 = BSP_CLOCKS_PLL_MUL(29U, 66U), ///< PLL multiplier of 29.66 + CGC_PLL_MUL_30_0 = BSP_CLOCKS_PLL_MUL(30U, 0U), ///< PLL multiplier of 30.00 + CGC_PLL_MUL_30_33 = BSP_CLOCKS_PLL_MUL(30U, 33U), ///< PLL multiplier of 30.33 + CGC_PLL_MUL_30_5 = BSP_CLOCKS_PLL_MUL(30U, 50U), ///< PLL multiplier of 30.50 + CGC_PLL_MUL_30_66 = BSP_CLOCKS_PLL_MUL(30U, 66U), ///< PLL multiplier of 30.66 + CGC_PLL_MUL_31_0 = BSP_CLOCKS_PLL_MUL(31U, 0U), ///< PLL multiplier of 31.00 + CGC_PLL_MUL_31_33 = BSP_CLOCKS_PLL_MUL(31U, 33U), ///< PLL multiplier of 31.33 + CGC_PLL_MUL_31_5 = BSP_CLOCKS_PLL_MUL(31U, 50U), ///< PLL multiplier of 31.50 + CGC_PLL_MUL_31_66 = BSP_CLOCKS_PLL_MUL(31U, 66U), ///< PLL multiplier of 31.66 + CGC_PLL_MUL_32_0 = BSP_CLOCKS_PLL_MUL(32U, 0U), ///< PLL multiplier of 32.00 + CGC_PLL_MUL_32_33 = BSP_CLOCKS_PLL_MUL(32U, 33U), ///< PLL multiplier of 32.33 + CGC_PLL_MUL_32_5 = BSP_CLOCKS_PLL_MUL(32U, 50U), ///< PLL multiplier of 32.50 + CGC_PLL_MUL_32_66 = BSP_CLOCKS_PLL_MUL(32U, 66U), ///< PLL multiplier of 32.66 + CGC_PLL_MUL_33_0 = BSP_CLOCKS_PLL_MUL(33U, 0U), ///< PLL multiplier of 33.00 + CGC_PLL_MUL_33_33 = BSP_CLOCKS_PLL_MUL(33U, 33U), ///< PLL multiplier of 33.33 + CGC_PLL_MUL_33_5 = BSP_CLOCKS_PLL_MUL(33U, 50U), ///< PLL multiplier of 33.50 + CGC_PLL_MUL_33_66 = BSP_CLOCKS_PLL_MUL(33U, 66U), ///< PLL multiplier of 33.66 + CGC_PLL_MUL_34_0 = BSP_CLOCKS_PLL_MUL(34U, 0U), ///< PLL multiplier of 34.00 + CGC_PLL_MUL_34_33 = BSP_CLOCKS_PLL_MUL(34U, 33U), ///< PLL multiplier of 34.33 + CGC_PLL_MUL_34_5 = BSP_CLOCKS_PLL_MUL(34U, 50U), ///< PLL multiplier of 34.50 + CGC_PLL_MUL_34_66 = BSP_CLOCKS_PLL_MUL(34U, 66U), ///< PLL multiplier of 34.66 + CGC_PLL_MUL_35_0 = BSP_CLOCKS_PLL_MUL(35U, 0U), ///< PLL multiplier of 35.00 + CGC_PLL_MUL_35_33 = BSP_CLOCKS_PLL_MUL(35U, 33U), ///< PLL multiplier of 35.33 + CGC_PLL_MUL_35_5 = BSP_CLOCKS_PLL_MUL(35U, 50U), ///< PLL multiplier of 35.50 + CGC_PLL_MUL_35_66 = BSP_CLOCKS_PLL_MUL(35U, 66U), ///< PLL multiplier of 35.66 + CGC_PLL_MUL_36_0 = BSP_CLOCKS_PLL_MUL(36U, 0U), ///< PLL multiplier of 36.00 + CGC_PLL_MUL_36_33 = BSP_CLOCKS_PLL_MUL(36U, 33U), ///< PLL multiplier of 36.33 + CGC_PLL_MUL_36_5 = BSP_CLOCKS_PLL_MUL(36U, 50U), ///< PLL multiplier of 36.50 + CGC_PLL_MUL_36_66 = BSP_CLOCKS_PLL_MUL(36U, 66U), ///< PLL multiplier of 36.66 + CGC_PLL_MUL_37_0 = BSP_CLOCKS_PLL_MUL(37U, 0U), ///< PLL multiplier of 37.00 + CGC_PLL_MUL_37_33 = BSP_CLOCKS_PLL_MUL(37U, 33U), ///< PLL multiplier of 37.33 + CGC_PLL_MUL_37_5 = BSP_CLOCKS_PLL_MUL(37U, 50U), ///< PLL multiplier of 37.50 + CGC_PLL_MUL_37_66 = BSP_CLOCKS_PLL_MUL(37U, 66U), ///< PLL multiplier of 37.66 + CGC_PLL_MUL_38_0 = BSP_CLOCKS_PLL_MUL(38U, 0U), ///< PLL multiplier of 38.00 + CGC_PLL_MUL_38_33 = BSP_CLOCKS_PLL_MUL(38U, 33U), ///< PLL multiplier of 38.33 + CGC_PLL_MUL_38_5 = BSP_CLOCKS_PLL_MUL(38U, 50U), ///< PLL multiplier of 38.50 + CGC_PLL_MUL_38_66 = BSP_CLOCKS_PLL_MUL(38U, 66U), ///< PLL multiplier of 38.66 + CGC_PLL_MUL_39_0 = BSP_CLOCKS_PLL_MUL(39U, 0U), ///< PLL multiplier of 39.00 + CGC_PLL_MUL_39_33 = BSP_CLOCKS_PLL_MUL(39U, 33U), ///< PLL multiplier of 39.33 + CGC_PLL_MUL_39_5 = BSP_CLOCKS_PLL_MUL(39U, 50U), ///< PLL multiplier of 39.50 + CGC_PLL_MUL_39_66 = BSP_CLOCKS_PLL_MUL(39U, 66U), ///< PLL multiplier of 39.66 + CGC_PLL_MUL_40_0 = BSP_CLOCKS_PLL_MUL(40U, 0U), ///< PLL multiplier of 40.00 + CGC_PLL_MUL_40_33 = BSP_CLOCKS_PLL_MUL(40U, 33U), ///< PLL multiplier of 40.33 + CGC_PLL_MUL_40_5 = BSP_CLOCKS_PLL_MUL(40U, 50U), ///< PLL multiplier of 40.50 + CGC_PLL_MUL_40_66 = BSP_CLOCKS_PLL_MUL(40U, 66U), ///< PLL multiplier of 40.66 + CGC_PLL_MUL_41_0 = BSP_CLOCKS_PLL_MUL(41U, 0U), ///< PLL multiplier of 41.00 + CGC_PLL_MUL_41_33 = BSP_CLOCKS_PLL_MUL(41U, 33U), ///< PLL multiplier of 41.33 + CGC_PLL_MUL_41_5 = BSP_CLOCKS_PLL_MUL(41U, 50U), ///< PLL multiplier of 41.50 + CGC_PLL_MUL_41_66 = BSP_CLOCKS_PLL_MUL(41U, 66U), ///< PLL multiplier of 41.66 + CGC_PLL_MUL_42_0 = BSP_CLOCKS_PLL_MUL(42U, 0U), ///< PLL multiplier of 42.00 + CGC_PLL_MUL_42_33 = BSP_CLOCKS_PLL_MUL(42U, 33U), ///< PLL multiplier of 42.33 + CGC_PLL_MUL_42_5 = BSP_CLOCKS_PLL_MUL(42U, 50U), ///< PLL multiplier of 42.50 + CGC_PLL_MUL_42_66 = BSP_CLOCKS_PLL_MUL(42U, 66U), ///< PLL multiplier of 42.66 + CGC_PLL_MUL_43_0 = BSP_CLOCKS_PLL_MUL(43U, 0U), ///< PLL multiplier of 43.00 + CGC_PLL_MUL_43_33 = BSP_CLOCKS_PLL_MUL(43U, 33U), ///< PLL multiplier of 43.33 + CGC_PLL_MUL_43_5 = BSP_CLOCKS_PLL_MUL(43U, 50U), ///< PLL multiplier of 43.50 + CGC_PLL_MUL_43_66 = BSP_CLOCKS_PLL_MUL(43U, 66U), ///< PLL multiplier of 43.66 + CGC_PLL_MUL_44_0 = BSP_CLOCKS_PLL_MUL(44U, 0U), ///< PLL multiplier of 44.00 + CGC_PLL_MUL_44_33 = BSP_CLOCKS_PLL_MUL(44U, 33U), ///< PLL multiplier of 44.33 + CGC_PLL_MUL_44_5 = BSP_CLOCKS_PLL_MUL(44U, 50U), ///< PLL multiplier of 44.50 + CGC_PLL_MUL_44_66 = BSP_CLOCKS_PLL_MUL(44U, 66U), ///< PLL multiplier of 44.66 + CGC_PLL_MUL_45_0 = BSP_CLOCKS_PLL_MUL(45U, 0U), ///< PLL multiplier of 45.00 + CGC_PLL_MUL_45_33 = BSP_CLOCKS_PLL_MUL(45U, 33U), ///< PLL multiplier of 45.33 + CGC_PLL_MUL_45_5 = BSP_CLOCKS_PLL_MUL(45U, 50U), ///< PLL multiplier of 45.50 + CGC_PLL_MUL_45_66 = BSP_CLOCKS_PLL_MUL(45U, 66U), ///< PLL multiplier of 45.66 + CGC_PLL_MUL_46_0 = BSP_CLOCKS_PLL_MUL(46U, 0U), ///< PLL multiplier of 46.00 + CGC_PLL_MUL_46_33 = BSP_CLOCKS_PLL_MUL(46U, 33U), ///< PLL multiplier of 46.33 + CGC_PLL_MUL_46_5 = BSP_CLOCKS_PLL_MUL(46U, 50U), ///< PLL multiplier of 46.50 + CGC_PLL_MUL_46_66 = BSP_CLOCKS_PLL_MUL(46U, 66U), ///< PLL multiplier of 46.66 + CGC_PLL_MUL_47_0 = BSP_CLOCKS_PLL_MUL(47U, 0U), ///< PLL multiplier of 47.00 + CGC_PLL_MUL_47_33 = BSP_CLOCKS_PLL_MUL(47U, 33U), ///< PLL multiplier of 47.33 + CGC_PLL_MUL_47_5 = BSP_CLOCKS_PLL_MUL(47U, 50U), ///< PLL multiplier of 47.50 + CGC_PLL_MUL_47_66 = BSP_CLOCKS_PLL_MUL(47U, 66U), ///< PLL multiplier of 47.66 + CGC_PLL_MUL_48_0 = BSP_CLOCKS_PLL_MUL(48U, 0U), ///< PLL multiplier of 48.00 + CGC_PLL_MUL_48_33 = BSP_CLOCKS_PLL_MUL(48U, 33U), ///< PLL multiplier of 48.33 + CGC_PLL_MUL_48_5 = BSP_CLOCKS_PLL_MUL(48U, 50U), ///< PLL multiplier of 48.50 + CGC_PLL_MUL_48_66 = BSP_CLOCKS_PLL_MUL(48U, 66U), ///< PLL multiplier of 48.66 + CGC_PLL_MUL_49_0 = BSP_CLOCKS_PLL_MUL(49U, 0U), ///< PLL multiplier of 49.00 + CGC_PLL_MUL_49_33 = BSP_CLOCKS_PLL_MUL(49U, 33U), ///< PLL multiplier of 49.33 + CGC_PLL_MUL_49_5 = BSP_CLOCKS_PLL_MUL(49U, 50U), ///< PLL multiplier of 49.50 + CGC_PLL_MUL_49_66 = BSP_CLOCKS_PLL_MUL(49U, 66U), ///< PLL multiplier of 49.66 + CGC_PLL_MUL_50_0 = BSP_CLOCKS_PLL_MUL(50U, 0U), ///< PLL multiplier of 50.00 + CGC_PLL_MUL_50_33 = BSP_CLOCKS_PLL_MUL(50U, 33U), ///< PLL multiplier of 50.33 + CGC_PLL_MUL_50_5 = BSP_CLOCKS_PLL_MUL(50U, 50U), ///< PLL multiplier of 50.50 + CGC_PLL_MUL_50_66 = BSP_CLOCKS_PLL_MUL(50U, 66U), ///< PLL multiplier of 50.66 + CGC_PLL_MUL_51_0 = BSP_CLOCKS_PLL_MUL(51U, 0U), ///< PLL multiplier of 51.00 + CGC_PLL_MUL_51_33 = BSP_CLOCKS_PLL_MUL(51U, 33U), ///< PLL multiplier of 51.33 + CGC_PLL_MUL_51_5 = BSP_CLOCKS_PLL_MUL(51U, 50U), ///< PLL multiplier of 51.50 + CGC_PLL_MUL_51_66 = BSP_CLOCKS_PLL_MUL(51U, 66U), ///< PLL multiplier of 51.66 + CGC_PLL_MUL_52_0 = BSP_CLOCKS_PLL_MUL(52U, 0U), ///< PLL multiplier of 52.00 + CGC_PLL_MUL_52_33 = BSP_CLOCKS_PLL_MUL(52U, 33U), ///< PLL multiplier of 52.33 + CGC_PLL_MUL_52_5 = BSP_CLOCKS_PLL_MUL(52U, 50U), ///< PLL multiplier of 52.50 + CGC_PLL_MUL_52_66 = BSP_CLOCKS_PLL_MUL(52U, 66U), ///< PLL multiplier of 52.66 + CGC_PLL_MUL_53_0 = BSP_CLOCKS_PLL_MUL(53U, 0U), ///< PLL multiplier of 53.00 + CGC_PLL_MUL_53_33 = BSP_CLOCKS_PLL_MUL(53U, 33U), ///< PLL multiplier of 53.33 + CGC_PLL_MUL_53_5 = BSP_CLOCKS_PLL_MUL(53U, 50U), ///< PLL multiplier of 53.50 + CGC_PLL_MUL_53_66 = BSP_CLOCKS_PLL_MUL(53U, 66U), ///< PLL multiplier of 53.66 + CGC_PLL_MUL_54_0 = BSP_CLOCKS_PLL_MUL(54U, 0U), ///< PLL multiplier of 54.00 + CGC_PLL_MUL_54_33 = BSP_CLOCKS_PLL_MUL(54U, 33U), ///< PLL multiplier of 54.33 + CGC_PLL_MUL_54_5 = BSP_CLOCKS_PLL_MUL(54U, 50U), ///< PLL multiplier of 54.50 + CGC_PLL_MUL_54_66 = BSP_CLOCKS_PLL_MUL(54U, 66U), ///< PLL multiplier of 54.66 + CGC_PLL_MUL_55_0 = BSP_CLOCKS_PLL_MUL(55U, 0U), ///< PLL multiplier of 55.00 + CGC_PLL_MUL_55_33 = BSP_CLOCKS_PLL_MUL(55U, 33U), ///< PLL multiplier of 55.33 + CGC_PLL_MUL_55_5 = BSP_CLOCKS_PLL_MUL(55U, 50U), ///< PLL multiplier of 55.50 + CGC_PLL_MUL_55_66 = BSP_CLOCKS_PLL_MUL(55U, 66U), ///< PLL multiplier of 55.66 + CGC_PLL_MUL_56_0 = BSP_CLOCKS_PLL_MUL(56U, 0U), ///< PLL multiplier of 56.00 + CGC_PLL_MUL_56_33 = BSP_CLOCKS_PLL_MUL(56U, 33U), ///< PLL multiplier of 56.33 + CGC_PLL_MUL_56_5 = BSP_CLOCKS_PLL_MUL(56U, 50U), ///< PLL multiplier of 56.50 + CGC_PLL_MUL_56_66 = BSP_CLOCKS_PLL_MUL(56U, 66U), ///< PLL multiplier of 56.66 + CGC_PLL_MUL_57_0 = BSP_CLOCKS_PLL_MUL(57U, 0U), ///< PLL multiplier of 57.00 + CGC_PLL_MUL_57_33 = BSP_CLOCKS_PLL_MUL(57U, 33U), ///< PLL multiplier of 57.33 + CGC_PLL_MUL_57_5 = BSP_CLOCKS_PLL_MUL(57U, 50U), ///< PLL multiplier of 57.50 + CGC_PLL_MUL_57_66 = BSP_CLOCKS_PLL_MUL(57U, 66U), ///< PLL multiplier of 57.66 + CGC_PLL_MUL_58_0 = BSP_CLOCKS_PLL_MUL(58U, 0U), ///< PLL multiplier of 58.00 + CGC_PLL_MUL_58_33 = BSP_CLOCKS_PLL_MUL(58U, 33U), ///< PLL multiplier of 58.33 + CGC_PLL_MUL_58_5 = BSP_CLOCKS_PLL_MUL(58U, 50U), ///< PLL multiplier of 58.50 + CGC_PLL_MUL_58_66 = BSP_CLOCKS_PLL_MUL(58U, 66U), ///< PLL multiplier of 58.66 + CGC_PLL_MUL_59_0 = BSP_CLOCKS_PLL_MUL(59U, 0U), ///< PLL multiplier of 59.00 + CGC_PLL_MUL_59_33 = BSP_CLOCKS_PLL_MUL(59U, 33U), ///< PLL multiplier of 59.33 + CGC_PLL_MUL_59_5 = BSP_CLOCKS_PLL_MUL(59U, 50U), ///< PLL multiplier of 59.50 + CGC_PLL_MUL_59_66 = BSP_CLOCKS_PLL_MUL(59U, 66U), ///< PLL multiplier of 59.66 + CGC_PLL_MUL_60_0 = BSP_CLOCKS_PLL_MUL(60U, 0U), ///< PLL multiplier of 60.00 + CGC_PLL_MUL_60_33 = BSP_CLOCKS_PLL_MUL(60U, 33U), ///< PLL multiplier of 60.33 + CGC_PLL_MUL_60_5 = BSP_CLOCKS_PLL_MUL(60U, 50U), ///< PLL multiplier of 60.50 + CGC_PLL_MUL_60_66 = BSP_CLOCKS_PLL_MUL(60U, 66U), ///< PLL multiplier of 60.66 + CGC_PLL_MUL_61_0 = BSP_CLOCKS_PLL_MUL(61U, 0U), ///< PLL multiplier of 61.00 + CGC_PLL_MUL_61_33 = BSP_CLOCKS_PLL_MUL(61U, 33U), ///< PLL multiplier of 61.33 + CGC_PLL_MUL_61_5 = BSP_CLOCKS_PLL_MUL(61U, 50U), ///< PLL multiplier of 61.50 + CGC_PLL_MUL_61_66 = BSP_CLOCKS_PLL_MUL(61U, 66U), ///< PLL multiplier of 61.66 + CGC_PLL_MUL_62_0 = BSP_CLOCKS_PLL_MUL(62U, 0U), ///< PLL multiplier of 62.00 + CGC_PLL_MUL_62_33 = BSP_CLOCKS_PLL_MUL(62U, 33U), ///< PLL multiplier of 62.33 + CGC_PLL_MUL_62_5 = BSP_CLOCKS_PLL_MUL(62U, 50U), ///< PLL multiplier of 62.50 + CGC_PLL_MUL_62_66 = BSP_CLOCKS_PLL_MUL(62U, 66U), ///< PLL multiplier of 62.66 + CGC_PLL_MUL_63_0 = BSP_CLOCKS_PLL_MUL(63U, 0U), ///< PLL multiplier of 63.00 + CGC_PLL_MUL_63_33 = BSP_CLOCKS_PLL_MUL(63U, 33U), ///< PLL multiplier of 63.33 + CGC_PLL_MUL_63_5 = BSP_CLOCKS_PLL_MUL(63U, 50U), ///< PLL multiplier of 63.50 + CGC_PLL_MUL_63_66 = BSP_CLOCKS_PLL_MUL(63U, 66U), ///< PLL multiplier of 63.66 + CGC_PLL_MUL_64_0 = BSP_CLOCKS_PLL_MUL(64U, 0U), ///< PLL multiplier of 64.00 + CGC_PLL_MUL_64_33 = BSP_CLOCKS_PLL_MUL(64U, 33U), ///< PLL multiplier of 64.33 + CGC_PLL_MUL_64_5 = BSP_CLOCKS_PLL_MUL(64U, 50U), ///< PLL multiplier of 64.50 + CGC_PLL_MUL_64_66 = BSP_CLOCKS_PLL_MUL(64U, 66U), ///< PLL multiplier of 64.66 + CGC_PLL_MUL_65_0 = BSP_CLOCKS_PLL_MUL(65U, 0U), ///< PLL multiplier of 65.00 + CGC_PLL_MUL_65_33 = BSP_CLOCKS_PLL_MUL(65U, 33U), ///< PLL multiplier of 65.33 + CGC_PLL_MUL_65_5 = BSP_CLOCKS_PLL_MUL(65U, 50U), ///< PLL multiplier of 65.50 + CGC_PLL_MUL_65_66 = BSP_CLOCKS_PLL_MUL(65U, 66U), ///< PLL multiplier of 65.66 + CGC_PLL_MUL_66_0 = BSP_CLOCKS_PLL_MUL(66U, 0U), ///< PLL multiplier of 66.00 + CGC_PLL_MUL_66_33 = BSP_CLOCKS_PLL_MUL(66U, 33U), ///< PLL multiplier of 66.33 + CGC_PLL_MUL_66_5 = BSP_CLOCKS_PLL_MUL(66U, 50U), ///< PLL multiplier of 66.50 + CGC_PLL_MUL_66_66 = BSP_CLOCKS_PLL_MUL(66U, 66U), ///< PLL multiplier of 66.66 + CGC_PLL_MUL_67_0 = BSP_CLOCKS_PLL_MUL(67U, 0U), ///< PLL multiplier of 67.00 + CGC_PLL_MUL_67_33 = BSP_CLOCKS_PLL_MUL(67U, 33U), ///< PLL multiplier of 67.33 + CGC_PLL_MUL_67_5 = BSP_CLOCKS_PLL_MUL(67U, 50U), ///< PLL multiplier of 67.50 + CGC_PLL_MUL_67_66 = BSP_CLOCKS_PLL_MUL(67U, 66U), ///< PLL multiplier of 67.66 + CGC_PLL_MUL_68_0 = BSP_CLOCKS_PLL_MUL(68U, 0U), ///< PLL multiplier of 68.00 + CGC_PLL_MUL_68_33 = BSP_CLOCKS_PLL_MUL(68U, 33U), ///< PLL multiplier of 68.33 + CGC_PLL_MUL_68_5 = BSP_CLOCKS_PLL_MUL(68U, 50U), ///< PLL multiplier of 68.50 + CGC_PLL_MUL_68_66 = BSP_CLOCKS_PLL_MUL(68U, 66U), ///< PLL multiplier of 68.66 + CGC_PLL_MUL_69_0 = BSP_CLOCKS_PLL_MUL(69U, 0U), ///< PLL multiplier of 69.00 + CGC_PLL_MUL_69_33 = BSP_CLOCKS_PLL_MUL(69U, 33U), ///< PLL multiplier of 69.33 + CGC_PLL_MUL_69_5 = BSP_CLOCKS_PLL_MUL(69U, 50U), ///< PLL multiplier of 69.50 + CGC_PLL_MUL_69_66 = BSP_CLOCKS_PLL_MUL(69U, 66U), ///< PLL multiplier of 69.66 + CGC_PLL_MUL_70_0 = BSP_CLOCKS_PLL_MUL(70U, 0U), ///< PLL multiplier of 70.00 + CGC_PLL_MUL_70_33 = BSP_CLOCKS_PLL_MUL(70U, 33U), ///< PLL multiplier of 70.33 + CGC_PLL_MUL_70_5 = BSP_CLOCKS_PLL_MUL(70U, 50U), ///< PLL multiplier of 70.50 + CGC_PLL_MUL_70_66 = BSP_CLOCKS_PLL_MUL(70U, 66U), ///< PLL multiplier of 70.66 + CGC_PLL_MUL_71_0 = BSP_CLOCKS_PLL_MUL(71U, 0U), ///< PLL multiplier of 71.00 + CGC_PLL_MUL_71_33 = BSP_CLOCKS_PLL_MUL(71U, 33U), ///< PLL multiplier of 71.33 + CGC_PLL_MUL_71_5 = BSP_CLOCKS_PLL_MUL(71U, 50U), ///< PLL multiplier of 71.50 + CGC_PLL_MUL_71_66 = BSP_CLOCKS_PLL_MUL(71U, 66U), ///< PLL multiplier of 71.66 + CGC_PLL_MUL_72_0 = BSP_CLOCKS_PLL_MUL(72U, 0U), ///< PLL multiplier of 72.00 + CGC_PLL_MUL_72_33 = BSP_CLOCKS_PLL_MUL(72U, 33U), ///< PLL multiplier of 72.33 + CGC_PLL_MUL_72_5 = BSP_CLOCKS_PLL_MUL(72U, 50U), ///< PLL multiplier of 72.50 + CGC_PLL_MUL_72_66 = BSP_CLOCKS_PLL_MUL(72U, 66U), ///< PLL multiplier of 72.66 + CGC_PLL_MUL_73_0 = BSP_CLOCKS_PLL_MUL(73U, 0U), ///< PLL multiplier of 73.00 + CGC_PLL_MUL_73_33 = BSP_CLOCKS_PLL_MUL(73U, 33U), ///< PLL multiplier of 73.33 + CGC_PLL_MUL_73_5 = BSP_CLOCKS_PLL_MUL(73U, 50U), ///< PLL multiplier of 73.50 + CGC_PLL_MUL_73_66 = BSP_CLOCKS_PLL_MUL(73U, 66U), ///< PLL multiplier of 73.66 + CGC_PLL_MUL_74_0 = BSP_CLOCKS_PLL_MUL(74U, 0U), ///< PLL multiplier of 74.00 + CGC_PLL_MUL_74_33 = BSP_CLOCKS_PLL_MUL(74U, 33U), ///< PLL multiplier of 74.33 + CGC_PLL_MUL_74_5 = BSP_CLOCKS_PLL_MUL(74U, 50U), ///< PLL multiplier of 74.50 + CGC_PLL_MUL_74_66 = BSP_CLOCKS_PLL_MUL(74U, 66U), ///< PLL multiplier of 74.66 + CGC_PLL_MUL_75_0 = BSP_CLOCKS_PLL_MUL(75U, 0U), ///< PLL multiplier of 75.00 + CGC_PLL_MUL_75_33 = BSP_CLOCKS_PLL_MUL(75U, 33U), ///< PLL multiplier of 75.33 + CGC_PLL_MUL_75_5 = BSP_CLOCKS_PLL_MUL(75U, 50U), ///< PLL multiplier of 75.50 + CGC_PLL_MUL_75_66 = BSP_CLOCKS_PLL_MUL(75U, 66U), ///< PLL multiplier of 75.66 + CGC_PLL_MUL_76_0 = BSP_CLOCKS_PLL_MUL(76U, 0U), ///< PLL multiplier of 76.00 + CGC_PLL_MUL_76_33 = BSP_CLOCKS_PLL_MUL(76U, 33U), ///< PLL multiplier of 76.33 + CGC_PLL_MUL_76_5 = BSP_CLOCKS_PLL_MUL(76U, 50U), ///< PLL multiplier of 76.50 + CGC_PLL_MUL_76_66 = BSP_CLOCKS_PLL_MUL(76U, 66U), ///< PLL multiplier of 76.66 + CGC_PLL_MUL_77_0 = BSP_CLOCKS_PLL_MUL(77U, 0U), ///< PLL multiplier of 77.00 + CGC_PLL_MUL_77_33 = BSP_CLOCKS_PLL_MUL(77U, 33U), ///< PLL multiplier of 77.33 + CGC_PLL_MUL_77_5 = BSP_CLOCKS_PLL_MUL(77U, 50U), ///< PLL multiplier of 77.50 + CGC_PLL_MUL_77_66 = BSP_CLOCKS_PLL_MUL(77U, 66U), ///< PLL multiplier of 77.66 + CGC_PLL_MUL_78_0 = BSP_CLOCKS_PLL_MUL(78U, 0U), ///< PLL multiplier of 78.00 + CGC_PLL_MUL_78_33 = BSP_CLOCKS_PLL_MUL(78U, 33U), ///< PLL multiplier of 78.33 + CGC_PLL_MUL_78_5 = BSP_CLOCKS_PLL_MUL(78U, 50U), ///< PLL multiplier of 78.50 + CGC_PLL_MUL_78_66 = BSP_CLOCKS_PLL_MUL(78U, 66U), ///< PLL multiplier of 78.66 + CGC_PLL_MUL_79_0 = BSP_CLOCKS_PLL_MUL(79U, 0U), ///< PLL multiplier of 79.00 + CGC_PLL_MUL_79_33 = BSP_CLOCKS_PLL_MUL(79U, 33U), ///< PLL multiplier of 79.33 + CGC_PLL_MUL_79_5 = BSP_CLOCKS_PLL_MUL(79U, 50U), ///< PLL multiplier of 79.50 + CGC_PLL_MUL_79_66 = BSP_CLOCKS_PLL_MUL(79U, 66U), ///< PLL multiplier of 79.66 + CGC_PLL_MUL_80_0 = BSP_CLOCKS_PLL_MUL(80U, 0U), ///< PLL multiplier of 80.00 + CGC_PLL_MUL_80_33 = BSP_CLOCKS_PLL_MUL(80U, 33U), ///< PLL multiplier of 80.33 + CGC_PLL_MUL_80_5 = BSP_CLOCKS_PLL_MUL(80U, 50U), ///< PLL multiplier of 80.50 + CGC_PLL_MUL_80_66 = BSP_CLOCKS_PLL_MUL(80U, 66U), ///< PLL multiplier of 80.66 + CGC_PLL_MUL_81_0 = BSP_CLOCKS_PLL_MUL(81U, 0U), ///< PLL multiplier of 81.00 + CGC_PLL_MUL_81_33 = BSP_CLOCKS_PLL_MUL(81U, 33U), ///< PLL multiplier of 81.33 + CGC_PLL_MUL_81_5 = BSP_CLOCKS_PLL_MUL(81U, 50U), ///< PLL multiplier of 81.50 + CGC_PLL_MUL_81_66 = BSP_CLOCKS_PLL_MUL(81U, 66U), ///< PLL multiplier of 81.66 + CGC_PLL_MUL_82_0 = BSP_CLOCKS_PLL_MUL(82U, 0U), ///< PLL multiplier of 82.00 + CGC_PLL_MUL_82_33 = BSP_CLOCKS_PLL_MUL(82U, 33U), ///< PLL multiplier of 82.33 + CGC_PLL_MUL_82_5 = BSP_CLOCKS_PLL_MUL(82U, 50U), ///< PLL multiplier of 82.50 + CGC_PLL_MUL_82_66 = BSP_CLOCKS_PLL_MUL(82U, 66U), ///< PLL multiplier of 82.66 + CGC_PLL_MUL_83_0 = BSP_CLOCKS_PLL_MUL(83U, 0U), ///< PLL multiplier of 83.00 + CGC_PLL_MUL_83_33 = BSP_CLOCKS_PLL_MUL(83U, 33U), ///< PLL multiplier of 83.33 + CGC_PLL_MUL_83_5 = BSP_CLOCKS_PLL_MUL(83U, 50U), ///< PLL multiplier of 83.50 + CGC_PLL_MUL_83_66 = BSP_CLOCKS_PLL_MUL(83U, 66U), ///< PLL multiplier of 83.66 + CGC_PLL_MUL_84_0 = BSP_CLOCKS_PLL_MUL(84U, 0U), ///< PLL multiplier of 84.00 + CGC_PLL_MUL_84_33 = BSP_CLOCKS_PLL_MUL(84U, 33U), ///< PLL multiplier of 84.33 + CGC_PLL_MUL_84_5 = BSP_CLOCKS_PLL_MUL(84U, 50U), ///< PLL multiplier of 84.50 + CGC_PLL_MUL_84_66 = BSP_CLOCKS_PLL_MUL(84U, 66U), ///< PLL multiplier of 84.66 + CGC_PLL_MUL_85_0 = BSP_CLOCKS_PLL_MUL(85U, 0U), ///< PLL multiplier of 85.00 + CGC_PLL_MUL_85_33 = BSP_CLOCKS_PLL_MUL(85U, 33U), ///< PLL multiplier of 85.33 + CGC_PLL_MUL_85_5 = BSP_CLOCKS_PLL_MUL(85U, 50U), ///< PLL multiplier of 85.50 + CGC_PLL_MUL_85_66 = BSP_CLOCKS_PLL_MUL(85U, 66U), ///< PLL multiplier of 85.66 + CGC_PLL_MUL_86_0 = BSP_CLOCKS_PLL_MUL(86U, 0U), ///< PLL multiplier of 86.00 + CGC_PLL_MUL_86_33 = BSP_CLOCKS_PLL_MUL(86U, 33U), ///< PLL multiplier of 86.33 + CGC_PLL_MUL_86_5 = BSP_CLOCKS_PLL_MUL(86U, 50U), ///< PLL multiplier of 86.50 + CGC_PLL_MUL_86_66 = BSP_CLOCKS_PLL_MUL(86U, 66U), ///< PLL multiplier of 86.66 + CGC_PLL_MUL_87_0 = BSP_CLOCKS_PLL_MUL(87U, 0U), ///< PLL multiplier of 87.00 + CGC_PLL_MUL_87_33 = BSP_CLOCKS_PLL_MUL(87U, 33U), ///< PLL multiplier of 87.33 + CGC_PLL_MUL_87_5 = BSP_CLOCKS_PLL_MUL(87U, 50U), ///< PLL multiplier of 87.50 + CGC_PLL_MUL_87_66 = BSP_CLOCKS_PLL_MUL(87U, 66U), ///< PLL multiplier of 87.66 + CGC_PLL_MUL_88_0 = BSP_CLOCKS_PLL_MUL(88U, 0U), ///< PLL multiplier of 88.00 + CGC_PLL_MUL_88_33 = BSP_CLOCKS_PLL_MUL(88U, 33U), ///< PLL multiplier of 88.33 + CGC_PLL_MUL_88_5 = BSP_CLOCKS_PLL_MUL(88U, 50U), ///< PLL multiplier of 88.50 + CGC_PLL_MUL_88_66 = BSP_CLOCKS_PLL_MUL(88U, 66U), ///< PLL multiplier of 88.66 + CGC_PLL_MUL_89_0 = BSP_CLOCKS_PLL_MUL(89U, 0U), ///< PLL multiplier of 89.00 + CGC_PLL_MUL_89_33 = BSP_CLOCKS_PLL_MUL(89U, 33U), ///< PLL multiplier of 89.33 + CGC_PLL_MUL_89_5 = BSP_CLOCKS_PLL_MUL(89U, 50U), ///< PLL multiplier of 89.50 + CGC_PLL_MUL_89_66 = BSP_CLOCKS_PLL_MUL(89U, 66U), ///< PLL multiplier of 89.66 + CGC_PLL_MUL_90_0 = BSP_CLOCKS_PLL_MUL(90U, 0U), ///< PLL multiplier of 90.00 + CGC_PLL_MUL_90_33 = BSP_CLOCKS_PLL_MUL(90U, 33U), ///< PLL multiplier of 90.33 + CGC_PLL_MUL_90_5 = BSP_CLOCKS_PLL_MUL(90U, 50U), ///< PLL multiplier of 90.50 + CGC_PLL_MUL_90_66 = BSP_CLOCKS_PLL_MUL(90U, 66U), ///< PLL multiplier of 90.66 + CGC_PLL_MUL_91_0 = BSP_CLOCKS_PLL_MUL(91U, 0U), ///< PLL multiplier of 91.00 + CGC_PLL_MUL_91_33 = BSP_CLOCKS_PLL_MUL(91U, 33U), ///< PLL multiplier of 91.33 + CGC_PLL_MUL_91_5 = BSP_CLOCKS_PLL_MUL(91U, 50U), ///< PLL multiplier of 91.50 + CGC_PLL_MUL_91_66 = BSP_CLOCKS_PLL_MUL(91U, 66U), ///< PLL multiplier of 91.66 + CGC_PLL_MUL_92_0 = BSP_CLOCKS_PLL_MUL(92U, 0U), ///< PLL multiplier of 92.00 + CGC_PLL_MUL_92_33 = BSP_CLOCKS_PLL_MUL(92U, 33U), ///< PLL multiplier of 92.33 + CGC_PLL_MUL_92_5 = BSP_CLOCKS_PLL_MUL(92U, 50U), ///< PLL multiplier of 92.50 + CGC_PLL_MUL_92_66 = BSP_CLOCKS_PLL_MUL(92U, 66U), ///< PLL multiplier of 92.66 + CGC_PLL_MUL_93_0 = BSP_CLOCKS_PLL_MUL(93U, 0U), ///< PLL multiplier of 93.00 + CGC_PLL_MUL_93_33 = BSP_CLOCKS_PLL_MUL(93U, 33U), ///< PLL multiplier of 93.33 + CGC_PLL_MUL_93_5 = BSP_CLOCKS_PLL_MUL(93U, 50U), ///< PLL multiplier of 93.50 + CGC_PLL_MUL_93_66 = BSP_CLOCKS_PLL_MUL(93U, 66U), ///< PLL multiplier of 93.66 + CGC_PLL_MUL_94_0 = BSP_CLOCKS_PLL_MUL(94U, 0U), ///< PLL multiplier of 94.00 + CGC_PLL_MUL_94_33 = BSP_CLOCKS_PLL_MUL(94U, 33U), ///< PLL multiplier of 94.33 + CGC_PLL_MUL_94_5 = BSP_CLOCKS_PLL_MUL(94U, 50U), ///< PLL multiplier of 94.50 + CGC_PLL_MUL_94_66 = BSP_CLOCKS_PLL_MUL(94U, 66U), ///< PLL multiplier of 94.66 + CGC_PLL_MUL_95_0 = BSP_CLOCKS_PLL_MUL(95U, 0U), ///< PLL multiplier of 95.00 + CGC_PLL_MUL_95_33 = BSP_CLOCKS_PLL_MUL(95U, 33U), ///< PLL multiplier of 95.33 + CGC_PLL_MUL_95_5 = BSP_CLOCKS_PLL_MUL(95U, 50U), ///< PLL multiplier of 95.50 + CGC_PLL_MUL_95_66 = BSP_CLOCKS_PLL_MUL(95U, 66U), ///< PLL multiplier of 95.66 + CGC_PLL_MUL_96_0 = BSP_CLOCKS_PLL_MUL(96U, 0U), ///< PLL multiplier of 96.00 + CGC_PLL_MUL_96_33 = BSP_CLOCKS_PLL_MUL(96U, 33U), ///< PLL multiplier of 96.33 + CGC_PLL_MUL_96_5 = BSP_CLOCKS_PLL_MUL(96U, 50U), ///< PLL multiplier of 96.50 + CGC_PLL_MUL_96_66 = BSP_CLOCKS_PLL_MUL(96U, 66U), ///< PLL multiplier of 96.66 + CGC_PLL_MUL_97_0 = BSP_CLOCKS_PLL_MUL(97U, 0U), ///< PLL multiplier of 97.00 + CGC_PLL_MUL_97_33 = BSP_CLOCKS_PLL_MUL(97U, 33U), ///< PLL multiplier of 97.33 + CGC_PLL_MUL_97_5 = BSP_CLOCKS_PLL_MUL(97U, 50U), ///< PLL multiplier of 97.50 + CGC_PLL_MUL_97_66 = BSP_CLOCKS_PLL_MUL(97U, 66U), ///< PLL multiplier of 97.66 + CGC_PLL_MUL_98_0 = BSP_CLOCKS_PLL_MUL(98U, 0U), ///< PLL multiplier of 98.00 + CGC_PLL_MUL_98_33 = BSP_CLOCKS_PLL_MUL(98U, 33U), ///< PLL multiplier of 98.33 + CGC_PLL_MUL_98_5 = BSP_CLOCKS_PLL_MUL(98U, 50U), ///< PLL multiplier of 98.50 + CGC_PLL_MUL_98_66 = BSP_CLOCKS_PLL_MUL(98U, 66U), ///< PLL multiplier of 98.66 + CGC_PLL_MUL_99_0 = BSP_CLOCKS_PLL_MUL(99U, 0U), ///< PLL multiplier of 99.00 + CGC_PLL_MUL_99_33 = BSP_CLOCKS_PLL_MUL(99U, 33U), ///< PLL multiplier of 99.33 + CGC_PLL_MUL_99_5 = BSP_CLOCKS_PLL_MUL(99U, 50U), ///< PLL multiplier of 99.50 + CGC_PLL_MUL_99_66 = BSP_CLOCKS_PLL_MUL(99U, 66U), ///< PLL multiplier of 99.66 + CGC_PLL_MUL_100_0 = BSP_CLOCKS_PLL_MUL(100U, 0U), ///< PLL multiplier of 100.00 + CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33 + CGC_PLL_MUL_100_5 = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50 + CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66 + CGC_PLL_MUL_101_0 = BSP_CLOCKS_PLL_MUL(101U, 0U), ///< PLL multiplier of 101.00 + CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33 + CGC_PLL_MUL_101_5 = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50 + CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66 + CGC_PLL_MUL_102_0 = BSP_CLOCKS_PLL_MUL(102U, 0U), ///< PLL multiplier of 102.00 + CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33 + CGC_PLL_MUL_102_5 = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50 + CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66 + CGC_PLL_MUL_103_0 = BSP_CLOCKS_PLL_MUL(103U, 0U), ///< PLL multiplier of 103.00 + CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33 + CGC_PLL_MUL_103_5 = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50 + CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66 + CGC_PLL_MUL_104_0 = BSP_CLOCKS_PLL_MUL(104U, 0U), ///< PLL multiplier of 104.00 + CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33 + CGC_PLL_MUL_104_5 = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50 + CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66 + CGC_PLL_MUL_105_0 = BSP_CLOCKS_PLL_MUL(105U, 0U), ///< PLL multiplier of 105.00 + CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33 + CGC_PLL_MUL_105_5 = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50 + CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66 + CGC_PLL_MUL_106_0 = BSP_CLOCKS_PLL_MUL(106U, 0U), ///< PLL multiplier of 106.00 + CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33 + CGC_PLL_MUL_106_5 = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50 + CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66 + CGC_PLL_MUL_107_0 = BSP_CLOCKS_PLL_MUL(107U, 0U), ///< PLL multiplier of 107.00 + CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33 + CGC_PLL_MUL_107_5 = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50 + CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66 + CGC_PLL_MUL_108_0 = BSP_CLOCKS_PLL_MUL(108U, 0U), ///< PLL multiplier of 108.00 + CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33 + CGC_PLL_MUL_108_5 = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50 + CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66 + CGC_PLL_MUL_109_0 = BSP_CLOCKS_PLL_MUL(109U, 0U), ///< PLL multiplier of 109.00 + CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33 + CGC_PLL_MUL_109_5 = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50 + CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66 + CGC_PLL_MUL_110_0 = BSP_CLOCKS_PLL_MUL(110U, 0U), ///< PLL multiplier of 110.00 + CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33 + CGC_PLL_MUL_110_5 = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50 + CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66 + CGC_PLL_MUL_111_0 = BSP_CLOCKS_PLL_MUL(111U, 0U), ///< PLL multiplier of 111.00 + CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33 + CGC_PLL_MUL_111_5 = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50 + CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66 + CGC_PLL_MUL_112_0 = BSP_CLOCKS_PLL_MUL(112U, 0U), ///< PLL multiplier of 112.00 + CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33 + CGC_PLL_MUL_112_5 = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50 + CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66 + CGC_PLL_MUL_113_0 = BSP_CLOCKS_PLL_MUL(113U, 0U), ///< PLL multiplier of 113.00 + CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33 + CGC_PLL_MUL_113_5 = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50 + CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66 + CGC_PLL_MUL_114_0 = BSP_CLOCKS_PLL_MUL(114U, 0U), ///< PLL multiplier of 114.00 + CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33 + CGC_PLL_MUL_114_5 = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50 + CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66 + CGC_PLL_MUL_115_0 = BSP_CLOCKS_PLL_MUL(115U, 0U), ///< PLL multiplier of 115.00 + CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33 + CGC_PLL_MUL_115_5 = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50 + CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66 + CGC_PLL_MUL_116_0 = BSP_CLOCKS_PLL_MUL(116U, 0U), ///< PLL multiplier of 116.00 + CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33 + CGC_PLL_MUL_116_5 = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50 + CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66 + CGC_PLL_MUL_117_0 = BSP_CLOCKS_PLL_MUL(117U, 0U), ///< PLL multiplier of 117.00 + CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33 + CGC_PLL_MUL_117_5 = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50 + CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66 + CGC_PLL_MUL_118_0 = BSP_CLOCKS_PLL_MUL(118U, 0U), ///< PLL multiplier of 118.00 + CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33 + CGC_PLL_MUL_118_5 = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50 + CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66 + CGC_PLL_MUL_119_0 = BSP_CLOCKS_PLL_MUL(119U, 0U), ///< PLL multiplier of 119.00 + CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33 + CGC_PLL_MUL_119_5 = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50 + CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66 + CGC_PLL_MUL_120_0 = BSP_CLOCKS_PLL_MUL(120U, 0U), ///< PLL multiplier of 120.00 + CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33 + CGC_PLL_MUL_120_5 = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50 + CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66 + CGC_PLL_MUL_121_0 = BSP_CLOCKS_PLL_MUL(121U, 0U), ///< PLL multiplier of 121.00 + CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33 + CGC_PLL_MUL_121_5 = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50 + CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66 + CGC_PLL_MUL_122_0 = BSP_CLOCKS_PLL_MUL(122U, 0U), ///< PLL multiplier of 122.00 + CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33 + CGC_PLL_MUL_122_5 = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50 + CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66 + CGC_PLL_MUL_123_0 = BSP_CLOCKS_PLL_MUL(123U, 0U), ///< PLL multiplier of 123.00 + CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33 + CGC_PLL_MUL_123_5 = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50 + CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66 + CGC_PLL_MUL_124_0 = BSP_CLOCKS_PLL_MUL(124U, 0U), ///< PLL multiplier of 124.00 + CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33 + CGC_PLL_MUL_124_5 = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50 + CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66 + CGC_PLL_MUL_125_0 = BSP_CLOCKS_PLL_MUL(125U, 0U), ///< PLL multiplier of 125.00 + CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33 + CGC_PLL_MUL_125_5 = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50 + CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66 + CGC_PLL_MUL_126_0 = BSP_CLOCKS_PLL_MUL(126U, 0U), ///< PLL multiplier of 126.00 + CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33 + CGC_PLL_MUL_126_5 = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50 + CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66 + CGC_PLL_MUL_127_0 = BSP_CLOCKS_PLL_MUL(127U, 0U), ///< PLL multiplier of 127.00 + CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33 + CGC_PLL_MUL_127_5 = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50 + CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66 + CGC_PLL_MUL_128_0 = BSP_CLOCKS_PLL_MUL(128U, 0U), ///< PLL multiplier of 128.00 + CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33 + CGC_PLL_MUL_128_5 = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50 + CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66 + CGC_PLL_MUL_129_0 = BSP_CLOCKS_PLL_MUL(129U, 0U), ///< PLL multiplier of 129.00 + CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33 + CGC_PLL_MUL_129_5 = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50 + CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66 + CGC_PLL_MUL_130_0 = BSP_CLOCKS_PLL_MUL(130U, 0U), ///< PLL multiplier of 130.00 + CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33 + CGC_PLL_MUL_130_5 = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50 + CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66 + CGC_PLL_MUL_131_0 = BSP_CLOCKS_PLL_MUL(131U, 0U), ///< PLL multiplier of 131.00 + CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33 + CGC_PLL_MUL_131_5 = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50 + CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66 + CGC_PLL_MUL_132_0 = BSP_CLOCKS_PLL_MUL(132U, 0U), ///< PLL multiplier of 132.00 + CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33 + CGC_PLL_MUL_132_5 = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50 + CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66 + CGC_PLL_MUL_133_0 = BSP_CLOCKS_PLL_MUL(133U, 0U), ///< PLL multiplier of 133.00 + CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33 + CGC_PLL_MUL_133_5 = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50 + CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66 + CGC_PLL_MUL_134_0 = BSP_CLOCKS_PLL_MUL(134U, 0U), ///< PLL multiplier of 134.00 + CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33 + CGC_PLL_MUL_134_5 = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50 + CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66 + CGC_PLL_MUL_135_0 = BSP_CLOCKS_PLL_MUL(135U, 0U), ///< PLL multiplier of 135.00 + CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33 + CGC_PLL_MUL_135_5 = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50 + CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66 + CGC_PLL_MUL_136_0 = BSP_CLOCKS_PLL_MUL(136U, 0U), ///< PLL multiplier of 136.00 + CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33 + CGC_PLL_MUL_136_5 = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50 + CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66 + CGC_PLL_MUL_137_0 = BSP_CLOCKS_PLL_MUL(137U, 0U), ///< PLL multiplier of 137.00 + CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33 + CGC_PLL_MUL_137_5 = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50 + CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66 + CGC_PLL_MUL_138_0 = BSP_CLOCKS_PLL_MUL(138U, 0U), ///< PLL multiplier of 138.00 + CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33 + CGC_PLL_MUL_138_5 = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50 + CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66 + CGC_PLL_MUL_139_0 = BSP_CLOCKS_PLL_MUL(139U, 0U), ///< PLL multiplier of 139.00 + CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33 + CGC_PLL_MUL_139_5 = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50 + CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66 + CGC_PLL_MUL_140_0 = BSP_CLOCKS_PLL_MUL(140U, 0U), ///< PLL multiplier of 140.00 + CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33 + CGC_PLL_MUL_140_5 = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50 + CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66 + CGC_PLL_MUL_141_0 = BSP_CLOCKS_PLL_MUL(141U, 0U), ///< PLL multiplier of 141.00 + CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33 + CGC_PLL_MUL_141_5 = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50 + CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66 + CGC_PLL_MUL_142_0 = BSP_CLOCKS_PLL_MUL(142U, 0U), ///< PLL multiplier of 142.00 + CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33 + CGC_PLL_MUL_142_5 = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50 + CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66 + CGC_PLL_MUL_143_0 = BSP_CLOCKS_PLL_MUL(143U, 0U), ///< PLL multiplier of 143.00 + CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33 + CGC_PLL_MUL_143_5 = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50 + CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66 + CGC_PLL_MUL_144_0 = BSP_CLOCKS_PLL_MUL(144U, 0U), ///< PLL multiplier of 144.00 + CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33 + CGC_PLL_MUL_144_5 = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50 + CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66 + CGC_PLL_MUL_145_0 = BSP_CLOCKS_PLL_MUL(145U, 0U), ///< PLL multiplier of 145.00 + CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33 + CGC_PLL_MUL_145_5 = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50 + CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66 + CGC_PLL_MUL_146_0 = BSP_CLOCKS_PLL_MUL(146U, 0U), ///< PLL multiplier of 146.00 + CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33 + CGC_PLL_MUL_146_5 = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50 + CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66 + CGC_PLL_MUL_147_0 = BSP_CLOCKS_PLL_MUL(147U, 0U), ///< PLL multiplier of 147.00 + CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33 + CGC_PLL_MUL_147_5 = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50 + CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66 + CGC_PLL_MUL_148_0 = BSP_CLOCKS_PLL_MUL(148U, 0U), ///< PLL multiplier of 148.00 + CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33 + CGC_PLL_MUL_148_5 = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50 + CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66 + CGC_PLL_MUL_149_0 = BSP_CLOCKS_PLL_MUL(149U, 0U), ///< PLL multiplier of 149.00 + CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33 + CGC_PLL_MUL_149_5 = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50 + CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66 + CGC_PLL_MUL_150_0 = BSP_CLOCKS_PLL_MUL(150U, 0U), ///< PLL multiplier of 150.00 + CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33 + CGC_PLL_MUL_150_5 = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50 + CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66 + CGC_PLL_MUL_151_0 = BSP_CLOCKS_PLL_MUL(151U, 0U), ///< PLL multiplier of 151.00 + CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33 + CGC_PLL_MUL_151_5 = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50 + CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66 + CGC_PLL_MUL_152_0 = BSP_CLOCKS_PLL_MUL(152U, 0U), ///< PLL multiplier of 152.00 + CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33 + CGC_PLL_MUL_152_5 = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50 + CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66 + CGC_PLL_MUL_153_0 = BSP_CLOCKS_PLL_MUL(153U, 0U), ///< PLL multiplier of 153.00 + CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33 + CGC_PLL_MUL_153_5 = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50 + CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66 + CGC_PLL_MUL_154_0 = BSP_CLOCKS_PLL_MUL(154U, 0U), ///< PLL multiplier of 154.00 + CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33 + CGC_PLL_MUL_154_5 = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50 + CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66 + CGC_PLL_MUL_155_0 = BSP_CLOCKS_PLL_MUL(155U, 0U), ///< PLL multiplier of 155.00 + CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33 + CGC_PLL_MUL_155_5 = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50 + CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66 + CGC_PLL_MUL_156_0 = BSP_CLOCKS_PLL_MUL(156U, 0U), ///< PLL multiplier of 156.00 + CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33 + CGC_PLL_MUL_156_5 = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50 + CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66 + CGC_PLL_MUL_157_0 = BSP_CLOCKS_PLL_MUL(157U, 0U), ///< PLL multiplier of 157.00 + CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33 + CGC_PLL_MUL_157_5 = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50 + CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66 + CGC_PLL_MUL_158_0 = BSP_CLOCKS_PLL_MUL(158U, 0U), ///< PLL multiplier of 158.00 + CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33 + CGC_PLL_MUL_158_5 = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50 + CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66 + CGC_PLL_MUL_159_0 = BSP_CLOCKS_PLL_MUL(159U, 0U), ///< PLL multiplier of 159.00 + CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33 + CGC_PLL_MUL_159_5 = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50 + CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66 + CGC_PLL_MUL_160_0 = BSP_CLOCKS_PLL_MUL(160U, 0U), ///< PLL multiplier of 160.00 + CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33 + CGC_PLL_MUL_160_5 = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50 + CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66 + CGC_PLL_MUL_161_0 = BSP_CLOCKS_PLL_MUL(161U, 0U), ///< PLL multiplier of 161.00 + CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33 + CGC_PLL_MUL_161_5 = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50 + CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66 + CGC_PLL_MUL_162_0 = BSP_CLOCKS_PLL_MUL(162U, 0U), ///< PLL multiplier of 162.00 + CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33 + CGC_PLL_MUL_162_5 = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50 + CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66 + CGC_PLL_MUL_163_0 = BSP_CLOCKS_PLL_MUL(163U, 0U), ///< PLL multiplier of 163.00 + CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33 + CGC_PLL_MUL_163_5 = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50 + CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66 + CGC_PLL_MUL_164_0 = BSP_CLOCKS_PLL_MUL(164U, 0U), ///< PLL multiplier of 164.00 + CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33 + CGC_PLL_MUL_164_5 = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50 + CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66 + CGC_PLL_MUL_165_0 = BSP_CLOCKS_PLL_MUL(165U, 0U), ///< PLL multiplier of 165.00 + CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33 + CGC_PLL_MUL_165_5 = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50 + CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66 + CGC_PLL_MUL_166_0 = BSP_CLOCKS_PLL_MUL(166U, 0U), ///< PLL multiplier of 166.00 + CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33 + CGC_PLL_MUL_166_5 = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50 + CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66 + CGC_PLL_MUL_167_0 = BSP_CLOCKS_PLL_MUL(167U, 0U), ///< PLL multiplier of 167.00 + CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33 + CGC_PLL_MUL_167_5 = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50 + CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66 + CGC_PLL_MUL_168_0 = BSP_CLOCKS_PLL_MUL(168U, 0U), ///< PLL multiplier of 168.00 + CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33 + CGC_PLL_MUL_168_5 = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50 + CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66 + CGC_PLL_MUL_169_0 = BSP_CLOCKS_PLL_MUL(169U, 0U), ///< PLL multiplier of 169.00 + CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33 + CGC_PLL_MUL_169_5 = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50 + CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66 + CGC_PLL_MUL_170_0 = BSP_CLOCKS_PLL_MUL(170U, 0U), ///< PLL multiplier of 170.00 + CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33 + CGC_PLL_MUL_170_5 = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50 + CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66 + CGC_PLL_MUL_171_0 = BSP_CLOCKS_PLL_MUL(171U, 0U), ///< PLL multiplier of 171.00 + CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33 + CGC_PLL_MUL_171_5 = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50 + CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66 + CGC_PLL_MUL_172_0 = BSP_CLOCKS_PLL_MUL(172U, 0U), ///< PLL multiplier of 172.00 + CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33 + CGC_PLL_MUL_172_5 = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50 + CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66 + CGC_PLL_MUL_173_0 = BSP_CLOCKS_PLL_MUL(173U, 0U), ///< PLL multiplier of 173.00 + CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33 + CGC_PLL_MUL_173_5 = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50 + CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66 + CGC_PLL_MUL_174_0 = BSP_CLOCKS_PLL_MUL(174U, 0U), ///< PLL multiplier of 174.00 + CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33 + CGC_PLL_MUL_174_5 = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50 + CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66 + CGC_PLL_MUL_175_0 = BSP_CLOCKS_PLL_MUL(175U, 0U), ///< PLL multiplier of 175.00 + CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33 + CGC_PLL_MUL_175_5 = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50 + CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66 + CGC_PLL_MUL_176_0 = BSP_CLOCKS_PLL_MUL(176U, 0U), ///< PLL multiplier of 176.00 + CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33 + CGC_PLL_MUL_176_5 = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50 + CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66 + CGC_PLL_MUL_177_0 = BSP_CLOCKS_PLL_MUL(177U, 0U), ///< PLL multiplier of 177.00 + CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33 + CGC_PLL_MUL_177_5 = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50 + CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66 + CGC_PLL_MUL_178_0 = BSP_CLOCKS_PLL_MUL(178U, 0U), ///< PLL multiplier of 178.00 + CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33 + CGC_PLL_MUL_178_5 = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50 + CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66 + CGC_PLL_MUL_179_0 = BSP_CLOCKS_PLL_MUL(179U, 0U), ///< PLL multiplier of 179.00 + CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33 + CGC_PLL_MUL_179_5 = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50 + CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66 + CGC_PLL_MUL_180_0 = BSP_CLOCKS_PLL_MUL(180U, 0U), ///< PLL multiplier of 180.00 + CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 + CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 + CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 + CGC_PLL_MUL_181_0 = BSP_CLOCKS_PLL_MUL(181U, 0U), ///< PLL multiplier of 181.00 + CGC_PLL_MUL_181_33 = BSP_CLOCKS_PLL_MUL(181U, 33U), ///< PLL multiplier of 181.33 + CGC_PLL_MUL_181_5 = BSP_CLOCKS_PLL_MUL(181U, 50U), ///< PLL multiplier of 181.50 + CGC_PLL_MUL_181_66 = BSP_CLOCKS_PLL_MUL(181U, 66U), ///< PLL multiplier of 181.66 + CGC_PLL_MUL_182_0 = BSP_CLOCKS_PLL_MUL(182U, 0U), ///< PLL multiplier of 182.00 + CGC_PLL_MUL_182_33 = BSP_CLOCKS_PLL_MUL(182U, 33U), ///< PLL multiplier of 182.33 + CGC_PLL_MUL_182_5 = BSP_CLOCKS_PLL_MUL(182U, 50U), ///< PLL multiplier of 182.50 + CGC_PLL_MUL_182_66 = BSP_CLOCKS_PLL_MUL(182U, 66U), ///< PLL multiplier of 182.66 + CGC_PLL_MUL_183_0 = BSP_CLOCKS_PLL_MUL(183U, 0U), ///< PLL multiplier of 183.00 + CGC_PLL_MUL_183_33 = BSP_CLOCKS_PLL_MUL(183U, 33U), ///< PLL multiplier of 183.33 + CGC_PLL_MUL_183_5 = BSP_CLOCKS_PLL_MUL(183U, 50U), ///< PLL multiplier of 183.50 + CGC_PLL_MUL_183_66 = BSP_CLOCKS_PLL_MUL(183U, 66U), ///< PLL multiplier of 183.66 + CGC_PLL_MUL_184_0 = BSP_CLOCKS_PLL_MUL(184U, 0U), ///< PLL multiplier of 184.00 + CGC_PLL_MUL_184_33 = BSP_CLOCKS_PLL_MUL(184U, 33U), ///< PLL multiplier of 184.33 + CGC_PLL_MUL_184_5 = BSP_CLOCKS_PLL_MUL(184U, 50U), ///< PLL multiplier of 184.50 + CGC_PLL_MUL_184_66 = BSP_CLOCKS_PLL_MUL(184U, 66U), ///< PLL multiplier of 184.66 + CGC_PLL_MUL_185_0 = BSP_CLOCKS_PLL_MUL(185U, 0U), ///< PLL multiplier of 185.00 + CGC_PLL_MUL_185_33 = BSP_CLOCKS_PLL_MUL(185U, 33U), ///< PLL multiplier of 185.33 + CGC_PLL_MUL_185_5 = BSP_CLOCKS_PLL_MUL(185U, 50U), ///< PLL multiplier of 185.50 + CGC_PLL_MUL_185_66 = BSP_CLOCKS_PLL_MUL(185U, 66U), ///< PLL multiplier of 185.66 + CGC_PLL_MUL_186_0 = BSP_CLOCKS_PLL_MUL(186U, 0U), ///< PLL multiplier of 186.00 + CGC_PLL_MUL_186_33 = BSP_CLOCKS_PLL_MUL(186U, 33U), ///< PLL multiplier of 186.33 + CGC_PLL_MUL_186_5 = BSP_CLOCKS_PLL_MUL(186U, 50U), ///< PLL multiplier of 186.50 + CGC_PLL_MUL_186_66 = BSP_CLOCKS_PLL_MUL(186U, 66U), ///< PLL multiplier of 186.66 + CGC_PLL_MUL_187_0 = BSP_CLOCKS_PLL_MUL(187U, 0U), ///< PLL multiplier of 187.00 + CGC_PLL_MUL_187_33 = BSP_CLOCKS_PLL_MUL(187U, 33U), ///< PLL multiplier of 187.33 + CGC_PLL_MUL_187_5 = BSP_CLOCKS_PLL_MUL(187U, 50U), ///< PLL multiplier of 187.50 + CGC_PLL_MUL_187_66 = BSP_CLOCKS_PLL_MUL(187U, 66U), ///< PLL multiplier of 187.66 + CGC_PLL_MUL_188_0 = BSP_CLOCKS_PLL_MUL(188U, 0U), ///< PLL multiplier of 188.00 + CGC_PLL_MUL_188_33 = BSP_CLOCKS_PLL_MUL(188U, 33U), ///< PLL multiplier of 188.33 + CGC_PLL_MUL_188_5 = BSP_CLOCKS_PLL_MUL(188U, 50U), ///< PLL multiplier of 188.50 + CGC_PLL_MUL_188_66 = BSP_CLOCKS_PLL_MUL(188U, 66U), ///< PLL multiplier of 188.66 + CGC_PLL_MUL_189_0 = BSP_CLOCKS_PLL_MUL(189U, 0U), ///< PLL multiplier of 189.00 + CGC_PLL_MUL_189_33 = BSP_CLOCKS_PLL_MUL(189U, 33U), ///< PLL multiplier of 189.33 + CGC_PLL_MUL_189_5 = BSP_CLOCKS_PLL_MUL(189U, 50U), ///< PLL multiplier of 189.50 + CGC_PLL_MUL_189_66 = BSP_CLOCKS_PLL_MUL(189U, 66U), ///< PLL multiplier of 189.66 + CGC_PLL_MUL_190_0 = BSP_CLOCKS_PLL_MUL(190U, 0U), ///< PLL multiplier of 190.00 + CGC_PLL_MUL_190_33 = BSP_CLOCKS_PLL_MUL(190U, 33U), ///< PLL multiplier of 190.33 + CGC_PLL_MUL_190_5 = BSP_CLOCKS_PLL_MUL(190U, 50U), ///< PLL multiplier of 190.50 + CGC_PLL_MUL_190_66 = BSP_CLOCKS_PLL_MUL(190U, 66U), ///< PLL multiplier of 190.66 + CGC_PLL_MUL_191_0 = BSP_CLOCKS_PLL_MUL(191U, 0U), ///< PLL multiplier of 191.00 + CGC_PLL_MUL_191_33 = BSP_CLOCKS_PLL_MUL(191U, 33U), ///< PLL multiplier of 191.33 + CGC_PLL_MUL_191_5 = BSP_CLOCKS_PLL_MUL(191U, 50U), ///< PLL multiplier of 191.50 + CGC_PLL_MUL_191_66 = BSP_CLOCKS_PLL_MUL(191U, 66U), ///< PLL multiplier of 191.66 + CGC_PLL_MUL_192_0 = BSP_CLOCKS_PLL_MUL(192U, 0U), ///< PLL multiplier of 192.00 + CGC_PLL_MUL_192_33 = BSP_CLOCKS_PLL_MUL(192U, 33U), ///< PLL multiplier of 192.33 + CGC_PLL_MUL_192_5 = BSP_CLOCKS_PLL_MUL(192U, 50U), ///< PLL multiplier of 192.50 + CGC_PLL_MUL_192_66 = BSP_CLOCKS_PLL_MUL(192U, 66U), ///< PLL multiplier of 192.66 + CGC_PLL_MUL_193_0 = BSP_CLOCKS_PLL_MUL(193U, 0U), ///< PLL multiplier of 193.00 + CGC_PLL_MUL_193_33 = BSP_CLOCKS_PLL_MUL(193U, 33U), ///< PLL multiplier of 193.33 + CGC_PLL_MUL_193_5 = BSP_CLOCKS_PLL_MUL(193U, 50U), ///< PLL multiplier of 193.50 + CGC_PLL_MUL_193_66 = BSP_CLOCKS_PLL_MUL(193U, 66U), ///< PLL multiplier of 193.66 + CGC_PLL_MUL_194_0 = BSP_CLOCKS_PLL_MUL(194U, 0U), ///< PLL multiplier of 194.00 + CGC_PLL_MUL_194_33 = BSP_CLOCKS_PLL_MUL(194U, 33U), ///< PLL multiplier of 194.33 + CGC_PLL_MUL_194_5 = BSP_CLOCKS_PLL_MUL(194U, 50U), ///< PLL multiplier of 194.50 + CGC_PLL_MUL_194_66 = BSP_CLOCKS_PLL_MUL(194U, 66U), ///< PLL multiplier of 194.66 + CGC_PLL_MUL_195_0 = BSP_CLOCKS_PLL_MUL(195U, 0U), ///< PLL multiplier of 195.00 + CGC_PLL_MUL_195_33 = BSP_CLOCKS_PLL_MUL(195U, 33U), ///< PLL multiplier of 195.33 + CGC_PLL_MUL_195_5 = BSP_CLOCKS_PLL_MUL(195U, 50U), ///< PLL multiplier of 195.50 + CGC_PLL_MUL_195_66 = BSP_CLOCKS_PLL_MUL(195U, 66U), ///< PLL multiplier of 195.66 + CGC_PLL_MUL_196_0 = BSP_CLOCKS_PLL_MUL(196U, 0U), ///< PLL multiplier of 196.00 + CGC_PLL_MUL_196_33 = BSP_CLOCKS_PLL_MUL(196U, 33U), ///< PLL multiplier of 196.33 + CGC_PLL_MUL_196_5 = BSP_CLOCKS_PLL_MUL(196U, 50U), ///< PLL multiplier of 196.50 + CGC_PLL_MUL_196_66 = BSP_CLOCKS_PLL_MUL(196U, 66U), ///< PLL multiplier of 196.66 + CGC_PLL_MUL_197_0 = BSP_CLOCKS_PLL_MUL(197U, 0U), ///< PLL multiplier of 197.00 + CGC_PLL_MUL_197_33 = BSP_CLOCKS_PLL_MUL(197U, 33U), ///< PLL multiplier of 197.33 + CGC_PLL_MUL_197_5 = BSP_CLOCKS_PLL_MUL(197U, 50U), ///< PLL multiplier of 197.50 + CGC_PLL_MUL_197_66 = BSP_CLOCKS_PLL_MUL(197U, 66U), ///< PLL multiplier of 197.66 + CGC_PLL_MUL_198_0 = BSP_CLOCKS_PLL_MUL(198U, 0U), ///< PLL multiplier of 198.00 + CGC_PLL_MUL_198_33 = BSP_CLOCKS_PLL_MUL(198U, 33U), ///< PLL multiplier of 198.33 + CGC_PLL_MUL_198_5 = BSP_CLOCKS_PLL_MUL(198U, 50U), ///< PLL multiplier of 198.50 + CGC_PLL_MUL_198_66 = BSP_CLOCKS_PLL_MUL(198U, 66U), ///< PLL multiplier of 198.66 + CGC_PLL_MUL_199_0 = BSP_CLOCKS_PLL_MUL(199U, 0U), ///< PLL multiplier of 199.00 + CGC_PLL_MUL_199_33 = BSP_CLOCKS_PLL_MUL(199U, 33U), ///< PLL multiplier of 199.33 + CGC_PLL_MUL_199_5 = BSP_CLOCKS_PLL_MUL(199U, 50U), ///< PLL multiplier of 199.50 + CGC_PLL_MUL_199_66 = BSP_CLOCKS_PLL_MUL(199U, 66U), ///< PLL multiplier of 199.66 + CGC_PLL_MUL_200_0 = BSP_CLOCKS_PLL_MUL(200U, 0U), ///< PLL multiplier of 200.00 + CGC_PLL_MUL_200_33 = BSP_CLOCKS_PLL_MUL(200U, 33U), ///< PLL multiplier of 200.33 + CGC_PLL_MUL_200_5 = BSP_CLOCKS_PLL_MUL(200U, 50U), ///< PLL multiplier of 200.50 + CGC_PLL_MUL_200_66 = BSP_CLOCKS_PLL_MUL(200U, 66U), ///< PLL multiplier of 200.66 + CGC_PLL_MUL_201_0 = BSP_CLOCKS_PLL_MUL(201U, 0U), ///< PLL multiplier of 201.00 + CGC_PLL_MUL_201_33 = BSP_CLOCKS_PLL_MUL(201U, 33U), ///< PLL multiplier of 201.33 + CGC_PLL_MUL_201_5 = BSP_CLOCKS_PLL_MUL(201U, 50U), ///< PLL multiplier of 201.50 + CGC_PLL_MUL_201_66 = BSP_CLOCKS_PLL_MUL(201U, 66U), ///< PLL multiplier of 201.66 + CGC_PLL_MUL_202_0 = BSP_CLOCKS_PLL_MUL(202U, 0U), ///< PLL multiplier of 202.00 + CGC_PLL_MUL_202_33 = BSP_CLOCKS_PLL_MUL(202U, 33U), ///< PLL multiplier of 202.33 + CGC_PLL_MUL_202_5 = BSP_CLOCKS_PLL_MUL(202U, 50U), ///< PLL multiplier of 202.50 + CGC_PLL_MUL_202_66 = BSP_CLOCKS_PLL_MUL(202U, 66U), ///< PLL multiplier of 202.66 + CGC_PLL_MUL_203_0 = BSP_CLOCKS_PLL_MUL(203U, 0U), ///< PLL multiplier of 203.00 + CGC_PLL_MUL_203_33 = BSP_CLOCKS_PLL_MUL(203U, 33U), ///< PLL multiplier of 203.33 + CGC_PLL_MUL_203_5 = BSP_CLOCKS_PLL_MUL(203U, 50U), ///< PLL multiplier of 203.50 + CGC_PLL_MUL_203_66 = BSP_CLOCKS_PLL_MUL(203U, 66U), ///< PLL multiplier of 203.66 + CGC_PLL_MUL_204_0 = BSP_CLOCKS_PLL_MUL(204U, 0U), ///< PLL multiplier of 204.00 + CGC_PLL_MUL_204_33 = BSP_CLOCKS_PLL_MUL(204U, 33U), ///< PLL multiplier of 204.33 + CGC_PLL_MUL_204_5 = BSP_CLOCKS_PLL_MUL(204U, 50U), ///< PLL multiplier of 204.50 + CGC_PLL_MUL_204_66 = BSP_CLOCKS_PLL_MUL(204U, 66U), ///< PLL multiplier of 204.66 + CGC_PLL_MUL_205_0 = BSP_CLOCKS_PLL_MUL(205U, 0U), ///< PLL multiplier of 205.00 + CGC_PLL_MUL_205_33 = BSP_CLOCKS_PLL_MUL(205U, 33U), ///< PLL multiplier of 205.33 + CGC_PLL_MUL_205_5 = BSP_CLOCKS_PLL_MUL(205U, 50U), ///< PLL multiplier of 205.50 + CGC_PLL_MUL_205_66 = BSP_CLOCKS_PLL_MUL(205U, 66U), ///< PLL multiplier of 205.66 + CGC_PLL_MUL_206_0 = BSP_CLOCKS_PLL_MUL(206U, 0U), ///< PLL multiplier of 206.00 + CGC_PLL_MUL_206_33 = BSP_CLOCKS_PLL_MUL(206U, 33U), ///< PLL multiplier of 206.33 + CGC_PLL_MUL_206_5 = BSP_CLOCKS_PLL_MUL(206U, 50U), ///< PLL multiplier of 206.50 + CGC_PLL_MUL_206_66 = BSP_CLOCKS_PLL_MUL(206U, 66U), ///< PLL multiplier of 206.66 + CGC_PLL_MUL_207_0 = BSP_CLOCKS_PLL_MUL(207U, 0U), ///< PLL multiplier of 207.00 + CGC_PLL_MUL_207_33 = BSP_CLOCKS_PLL_MUL(207U, 33U), ///< PLL multiplier of 207.33 + CGC_PLL_MUL_207_5 = BSP_CLOCKS_PLL_MUL(207U, 50U), ///< PLL multiplier of 207.50 + CGC_PLL_MUL_207_66 = BSP_CLOCKS_PLL_MUL(207U, 66U), ///< PLL multiplier of 207.66 + CGC_PLL_MUL_208_0 = BSP_CLOCKS_PLL_MUL(208U, 0U), ///< PLL multiplier of 208.00 + CGC_PLL_MUL_208_33 = BSP_CLOCKS_PLL_MUL(208U, 33U), ///< PLL multiplier of 208.33 + CGC_PLL_MUL_208_5 = BSP_CLOCKS_PLL_MUL(208U, 50U), ///< PLL multiplier of 208.50 + CGC_PLL_MUL_208_66 = BSP_CLOCKS_PLL_MUL(208U, 66U), ///< PLL multiplier of 208.66 + CGC_PLL_MUL_209_0 = BSP_CLOCKS_PLL_MUL(209U, 0U), ///< PLL multiplier of 209.00 + CGC_PLL_MUL_209_33 = BSP_CLOCKS_PLL_MUL(209U, 33U), ///< PLL multiplier of 209.33 + CGC_PLL_MUL_209_5 = BSP_CLOCKS_PLL_MUL(209U, 50U), ///< PLL multiplier of 209.50 + CGC_PLL_MUL_209_66 = BSP_CLOCKS_PLL_MUL(209U, 66U), ///< PLL multiplier of 209.66 + CGC_PLL_MUL_210_0 = BSP_CLOCKS_PLL_MUL(210U, 0U), ///< PLL multiplier of 210.00 + CGC_PLL_MUL_210_33 = BSP_CLOCKS_PLL_MUL(210U, 33U), ///< PLL multiplier of 210.33 + CGC_PLL_MUL_210_5 = BSP_CLOCKS_PLL_MUL(210U, 50U), ///< PLL multiplier of 210.50 + CGC_PLL_MUL_210_66 = BSP_CLOCKS_PLL_MUL(210U, 66U), ///< PLL multiplier of 210.66 + CGC_PLL_MUL_211_0 = BSP_CLOCKS_PLL_MUL(211U, 0U), ///< PLL multiplier of 211.00 + CGC_PLL_MUL_211_33 = BSP_CLOCKS_PLL_MUL(211U, 33U), ///< PLL multiplier of 211.33 + CGC_PLL_MUL_211_5 = BSP_CLOCKS_PLL_MUL(211U, 50U), ///< PLL multiplier of 211.50 + CGC_PLL_MUL_211_66 = BSP_CLOCKS_PLL_MUL(211U, 66U), ///< PLL multiplier of 211.66 + CGC_PLL_MUL_212_0 = BSP_CLOCKS_PLL_MUL(212U, 0U), ///< PLL multiplier of 212.00 + CGC_PLL_MUL_212_33 = BSP_CLOCKS_PLL_MUL(212U, 33U), ///< PLL multiplier of 212.33 + CGC_PLL_MUL_212_5 = BSP_CLOCKS_PLL_MUL(212U, 50U), ///< PLL multiplier of 212.50 + CGC_PLL_MUL_212_66 = BSP_CLOCKS_PLL_MUL(212U, 66U), ///< PLL multiplier of 212.66 + CGC_PLL_MUL_213_0 = BSP_CLOCKS_PLL_MUL(213U, 0U), ///< PLL multiplier of 213.00 + CGC_PLL_MUL_213_33 = BSP_CLOCKS_PLL_MUL(213U, 33U), ///< PLL multiplier of 213.33 + CGC_PLL_MUL_213_5 = BSP_CLOCKS_PLL_MUL(213U, 50U), ///< PLL multiplier of 213.50 + CGC_PLL_MUL_213_66 = BSP_CLOCKS_PLL_MUL(213U, 66U), ///< PLL multiplier of 213.66 + CGC_PLL_MUL_214_0 = BSP_CLOCKS_PLL_MUL(214U, 0U), ///< PLL multiplier of 214.00 + CGC_PLL_MUL_214_33 = BSP_CLOCKS_PLL_MUL(214U, 33U), ///< PLL multiplier of 214.33 + CGC_PLL_MUL_214_5 = BSP_CLOCKS_PLL_MUL(214U, 50U), ///< PLL multiplier of 214.50 + CGC_PLL_MUL_214_66 = BSP_CLOCKS_PLL_MUL(214U, 66U), ///< PLL multiplier of 214.66 + CGC_PLL_MUL_215_0 = BSP_CLOCKS_PLL_MUL(215U, 0U), ///< PLL multiplier of 215.00 + CGC_PLL_MUL_215_33 = BSP_CLOCKS_PLL_MUL(215U, 33U), ///< PLL multiplier of 215.33 + CGC_PLL_MUL_215_5 = BSP_CLOCKS_PLL_MUL(215U, 50U), ///< PLL multiplier of 215.50 + CGC_PLL_MUL_215_66 = BSP_CLOCKS_PLL_MUL(215U, 66U), ///< PLL multiplier of 215.66 + CGC_PLL_MUL_216_0 = BSP_CLOCKS_PLL_MUL(216U, 0U), ///< PLL multiplier of 216.00 + CGC_PLL_MUL_216_33 = BSP_CLOCKS_PLL_MUL(216U, 33U), ///< PLL multiplier of 216.33 + CGC_PLL_MUL_216_5 = BSP_CLOCKS_PLL_MUL(216U, 50U), ///< PLL multiplier of 216.50 + CGC_PLL_MUL_216_66 = BSP_CLOCKS_PLL_MUL(216U, 66U), ///< PLL multiplier of 216.66 + CGC_PLL_MUL_217_0 = BSP_CLOCKS_PLL_MUL(217U, 0U), ///< PLL multiplier of 217.00 + CGC_PLL_MUL_217_33 = BSP_CLOCKS_PLL_MUL(217U, 33U), ///< PLL multiplier of 217.33 + CGC_PLL_MUL_217_5 = BSP_CLOCKS_PLL_MUL(217U, 50U), ///< PLL multiplier of 217.50 + CGC_PLL_MUL_217_66 = BSP_CLOCKS_PLL_MUL(217U, 66U), ///< PLL multiplier of 217.66 + CGC_PLL_MUL_218_0 = BSP_CLOCKS_PLL_MUL(218U, 0U), ///< PLL multiplier of 218.00 + CGC_PLL_MUL_218_33 = BSP_CLOCKS_PLL_MUL(218U, 33U), ///< PLL multiplier of 218.33 + CGC_PLL_MUL_218_5 = BSP_CLOCKS_PLL_MUL(218U, 50U), ///< PLL multiplier of 218.50 + CGC_PLL_MUL_218_66 = BSP_CLOCKS_PLL_MUL(218U, 66U), ///< PLL multiplier of 218.66 + CGC_PLL_MUL_219_0 = BSP_CLOCKS_PLL_MUL(219U, 0U), ///< PLL multiplier of 219.00 + CGC_PLL_MUL_219_33 = BSP_CLOCKS_PLL_MUL(219U, 33U), ///< PLL multiplier of 219.33 + CGC_PLL_MUL_219_5 = BSP_CLOCKS_PLL_MUL(219U, 50U), ///< PLL multiplier of 219.50 + CGC_PLL_MUL_219_66 = BSP_CLOCKS_PLL_MUL(219U, 66U), ///< PLL multiplier of 219.66 + CGC_PLL_MUL_220_0 = BSP_CLOCKS_PLL_MUL(220U, 0U), ///< PLL multiplier of 220.00 + CGC_PLL_MUL_220_33 = BSP_CLOCKS_PLL_MUL(220U, 33U), ///< PLL multiplier of 220.33 + CGC_PLL_MUL_220_5 = BSP_CLOCKS_PLL_MUL(220U, 50U), ///< PLL multiplier of 220.50 + CGC_PLL_MUL_220_66 = BSP_CLOCKS_PLL_MUL(220U, 66U), ///< PLL multiplier of 220.66 + CGC_PLL_MUL_221_0 = BSP_CLOCKS_PLL_MUL(221U, 0U), ///< PLL multiplier of 221.00 + CGC_PLL_MUL_221_33 = BSP_CLOCKS_PLL_MUL(221U, 33U), ///< PLL multiplier of 221.33 + CGC_PLL_MUL_221_5 = BSP_CLOCKS_PLL_MUL(221U, 50U), ///< PLL multiplier of 221.50 + CGC_PLL_MUL_221_66 = BSP_CLOCKS_PLL_MUL(221U, 66U), ///< PLL multiplier of 221.66 + CGC_PLL_MUL_222_0 = BSP_CLOCKS_PLL_MUL(222U, 0U), ///< PLL multiplier of 222.00 + CGC_PLL_MUL_222_33 = BSP_CLOCKS_PLL_MUL(222U, 33U), ///< PLL multiplier of 222.33 + CGC_PLL_MUL_222_5 = BSP_CLOCKS_PLL_MUL(222U, 50U), ///< PLL multiplier of 222.50 + CGC_PLL_MUL_222_66 = BSP_CLOCKS_PLL_MUL(222U, 66U), ///< PLL multiplier of 222.66 + CGC_PLL_MUL_223_0 = BSP_CLOCKS_PLL_MUL(223U, 0U), ///< PLL multiplier of 223.00 + CGC_PLL_MUL_223_33 = BSP_CLOCKS_PLL_MUL(223U, 33U), ///< PLL multiplier of 223.33 + CGC_PLL_MUL_223_5 = BSP_CLOCKS_PLL_MUL(223U, 50U), ///< PLL multiplier of 223.50 + CGC_PLL_MUL_223_66 = BSP_CLOCKS_PLL_MUL(223U, 66U), ///< PLL multiplier of 223.66 + CGC_PLL_MUL_224_0 = BSP_CLOCKS_PLL_MUL(224U, 0U), ///< PLL multiplier of 224.00 + CGC_PLL_MUL_224_33 = BSP_CLOCKS_PLL_MUL(224U, 33U), ///< PLL multiplier of 224.33 + CGC_PLL_MUL_224_5 = BSP_CLOCKS_PLL_MUL(224U, 50U), ///< PLL multiplier of 224.50 + CGC_PLL_MUL_224_66 = BSP_CLOCKS_PLL_MUL(224U, 66U), ///< PLL multiplier of 224.66 + CGC_PLL_MUL_225_0 = BSP_CLOCKS_PLL_MUL(225U, 0U), ///< PLL multiplier of 225.00 + CGC_PLL_MUL_225_33 = BSP_CLOCKS_PLL_MUL(225U, 33U), ///< PLL multiplier of 225.33 + CGC_PLL_MUL_225_5 = BSP_CLOCKS_PLL_MUL(225U, 50U), ///< PLL multiplier of 225.50 + CGC_PLL_MUL_225_66 = BSP_CLOCKS_PLL_MUL(225U, 66U), ///< PLL multiplier of 225.66 + CGC_PLL_MUL_226_0 = BSP_CLOCKS_PLL_MUL(226U, 0U), ///< PLL multiplier of 226.00 + CGC_PLL_MUL_226_33 = BSP_CLOCKS_PLL_MUL(226U, 33U), ///< PLL multiplier of 226.33 + CGC_PLL_MUL_226_5 = BSP_CLOCKS_PLL_MUL(226U, 50U), ///< PLL multiplier of 226.50 + CGC_PLL_MUL_226_66 = BSP_CLOCKS_PLL_MUL(226U, 66U), ///< PLL multiplier of 226.66 + CGC_PLL_MUL_227_0 = BSP_CLOCKS_PLL_MUL(227U, 0U), ///< PLL multiplier of 227.00 + CGC_PLL_MUL_227_33 = BSP_CLOCKS_PLL_MUL(227U, 33U), ///< PLL multiplier of 227.33 + CGC_PLL_MUL_227_5 = BSP_CLOCKS_PLL_MUL(227U, 50U), ///< PLL multiplier of 227.50 + CGC_PLL_MUL_227_66 = BSP_CLOCKS_PLL_MUL(227U, 66U), ///< PLL multiplier of 227.66 + CGC_PLL_MUL_228_0 = BSP_CLOCKS_PLL_MUL(228U, 0U), ///< PLL multiplier of 228.00 + CGC_PLL_MUL_228_33 = BSP_CLOCKS_PLL_MUL(228U, 33U), ///< PLL multiplier of 228.33 + CGC_PLL_MUL_228_5 = BSP_CLOCKS_PLL_MUL(228U, 50U), ///< PLL multiplier of 228.50 + CGC_PLL_MUL_228_66 = BSP_CLOCKS_PLL_MUL(228U, 66U), ///< PLL multiplier of 228.66 + CGC_PLL_MUL_229_0 = BSP_CLOCKS_PLL_MUL(229U, 0U), ///< PLL multiplier of 229.00 + CGC_PLL_MUL_229_33 = BSP_CLOCKS_PLL_MUL(229U, 33U), ///< PLL multiplier of 229.33 + CGC_PLL_MUL_229_5 = BSP_CLOCKS_PLL_MUL(229U, 50U), ///< PLL multiplier of 229.50 + CGC_PLL_MUL_229_66 = BSP_CLOCKS_PLL_MUL(229U, 66U), ///< PLL multiplier of 229.66 + CGC_PLL_MUL_230_0 = BSP_CLOCKS_PLL_MUL(230U, 0U), ///< PLL multiplier of 230.00 + CGC_PLL_MUL_230_33 = BSP_CLOCKS_PLL_MUL(230U, 33U), ///< PLL multiplier of 230.33 + CGC_PLL_MUL_230_5 = BSP_CLOCKS_PLL_MUL(230U, 50U), ///< PLL multiplier of 230.50 + CGC_PLL_MUL_230_66 = BSP_CLOCKS_PLL_MUL(230U, 66U), ///< PLL multiplier of 230.66 + CGC_PLL_MUL_231_0 = BSP_CLOCKS_PLL_MUL(231U, 0U), ///< PLL multiplier of 231.00 + CGC_PLL_MUL_231_33 = BSP_CLOCKS_PLL_MUL(231U, 33U), ///< PLL multiplier of 231.33 + CGC_PLL_MUL_231_5 = BSP_CLOCKS_PLL_MUL(231U, 50U), ///< PLL multiplier of 231.50 + CGC_PLL_MUL_231_66 = BSP_CLOCKS_PLL_MUL(231U, 66U), ///< PLL multiplier of 231.66 + CGC_PLL_MUL_232_0 = BSP_CLOCKS_PLL_MUL(232U, 0U), ///< PLL multiplier of 232.00 + CGC_PLL_MUL_232_33 = BSP_CLOCKS_PLL_MUL(232U, 33U), ///< PLL multiplier of 232.33 + CGC_PLL_MUL_232_5 = BSP_CLOCKS_PLL_MUL(232U, 50U), ///< PLL multiplier of 232.50 + CGC_PLL_MUL_232_66 = BSP_CLOCKS_PLL_MUL(232U, 66U), ///< PLL multiplier of 232.66 + CGC_PLL_MUL_233_0 = BSP_CLOCKS_PLL_MUL(233U, 0U), ///< PLL multiplier of 233.00 + CGC_PLL_MUL_233_33 = BSP_CLOCKS_PLL_MUL(233U, 33U), ///< PLL multiplier of 233.33 + CGC_PLL_MUL_233_5 = BSP_CLOCKS_PLL_MUL(233U, 50U), ///< PLL multiplier of 233.50 + CGC_PLL_MUL_233_66 = BSP_CLOCKS_PLL_MUL(233U, 66U), ///< PLL multiplier of 233.66 + CGC_PLL_MUL_234_0 = BSP_CLOCKS_PLL_MUL(234U, 0U), ///< PLL multiplier of 234.00 + CGC_PLL_MUL_234_33 = BSP_CLOCKS_PLL_MUL(234U, 33U), ///< PLL multiplier of 234.33 + CGC_PLL_MUL_234_5 = BSP_CLOCKS_PLL_MUL(234U, 50U), ///< PLL multiplier of 234.50 + CGC_PLL_MUL_234_66 = BSP_CLOCKS_PLL_MUL(234U, 66U), ///< PLL multiplier of 234.66 + CGC_PLL_MUL_235_0 = BSP_CLOCKS_PLL_MUL(235U, 0U), ///< PLL multiplier of 235.00 + CGC_PLL_MUL_235_33 = BSP_CLOCKS_PLL_MUL(235U, 33U), ///< PLL multiplier of 235.33 + CGC_PLL_MUL_235_5 = BSP_CLOCKS_PLL_MUL(235U, 50U), ///< PLL multiplier of 235.50 + CGC_PLL_MUL_235_66 = BSP_CLOCKS_PLL_MUL(235U, 66U), ///< PLL multiplier of 235.66 + CGC_PLL_MUL_236_0 = BSP_CLOCKS_PLL_MUL(236U, 0U), ///< PLL multiplier of 236.00 + CGC_PLL_MUL_236_33 = BSP_CLOCKS_PLL_MUL(236U, 33U), ///< PLL multiplier of 236.33 + CGC_PLL_MUL_236_5 = BSP_CLOCKS_PLL_MUL(236U, 50U), ///< PLL multiplier of 236.50 + CGC_PLL_MUL_236_66 = BSP_CLOCKS_PLL_MUL(236U, 66U), ///< PLL multiplier of 236.66 + CGC_PLL_MUL_237_0 = BSP_CLOCKS_PLL_MUL(237U, 0U), ///< PLL multiplier of 237.00 + CGC_PLL_MUL_237_33 = BSP_CLOCKS_PLL_MUL(237U, 33U), ///< PLL multiplier of 237.33 + CGC_PLL_MUL_237_5 = BSP_CLOCKS_PLL_MUL(237U, 50U), ///< PLL multiplier of 237.50 + CGC_PLL_MUL_237_66 = BSP_CLOCKS_PLL_MUL(237U, 66U), ///< PLL multiplier of 237.66 + CGC_PLL_MUL_238_0 = BSP_CLOCKS_PLL_MUL(238U, 0U), ///< PLL multiplier of 238.00 + CGC_PLL_MUL_238_33 = BSP_CLOCKS_PLL_MUL(238U, 33U), ///< PLL multiplier of 238.33 + CGC_PLL_MUL_238_5 = BSP_CLOCKS_PLL_MUL(238U, 50U), ///< PLL multiplier of 238.50 + CGC_PLL_MUL_238_66 = BSP_CLOCKS_PLL_MUL(238U, 66U), ///< PLL multiplier of 238.66 + CGC_PLL_MUL_239_0 = BSP_CLOCKS_PLL_MUL(239U, 0U), ///< PLL multiplier of 239.00 + CGC_PLL_MUL_239_33 = BSP_CLOCKS_PLL_MUL(239U, 33U), ///< PLL multiplier of 239.33 + CGC_PLL_MUL_239_5 = BSP_CLOCKS_PLL_MUL(239U, 50U), ///< PLL multiplier of 239.50 + CGC_PLL_MUL_239_66 = BSP_CLOCKS_PLL_MUL(239U, 66U), ///< PLL multiplier of 239.66 + CGC_PLL_MUL_240_0 = BSP_CLOCKS_PLL_MUL(240U, 0U), ///< PLL multiplier of 240.00 + CGC_PLL_MUL_240_33 = BSP_CLOCKS_PLL_MUL(240U, 33U), ///< PLL multiplier of 240.33 + CGC_PLL_MUL_240_5 = BSP_CLOCKS_PLL_MUL(240U, 50U), ///< PLL multiplier of 240.50 + CGC_PLL_MUL_240_66 = BSP_CLOCKS_PLL_MUL(240U, 66U), ///< PLL multiplier of 240.66 + CGC_PLL_MUL_241_0 = BSP_CLOCKS_PLL_MUL(241U, 0U), ///< PLL multiplier of 241.00 + CGC_PLL_MUL_241_33 = BSP_CLOCKS_PLL_MUL(241U, 33U), ///< PLL multiplier of 241.33 + CGC_PLL_MUL_241_5 = BSP_CLOCKS_PLL_MUL(241U, 50U), ///< PLL multiplier of 241.50 + CGC_PLL_MUL_241_66 = BSP_CLOCKS_PLL_MUL(241U, 66U), ///< PLL multiplier of 241.66 + CGC_PLL_MUL_242_0 = BSP_CLOCKS_PLL_MUL(242U, 0U), ///< PLL multiplier of 242.00 + CGC_PLL_MUL_242_33 = BSP_CLOCKS_PLL_MUL(242U, 33U), ///< PLL multiplier of 242.33 + CGC_PLL_MUL_242_5 = BSP_CLOCKS_PLL_MUL(242U, 50U), ///< PLL multiplier of 242.50 + CGC_PLL_MUL_242_66 = BSP_CLOCKS_PLL_MUL(242U, 66U), ///< PLL multiplier of 242.66 + CGC_PLL_MUL_243_0 = BSP_CLOCKS_PLL_MUL(243U, 0U), ///< PLL multiplier of 243.00 + CGC_PLL_MUL_243_33 = BSP_CLOCKS_PLL_MUL(243U, 33U), ///< PLL multiplier of 243.33 + CGC_PLL_MUL_243_5 = BSP_CLOCKS_PLL_MUL(243U, 50U), ///< PLL multiplier of 243.50 + CGC_PLL_MUL_243_66 = BSP_CLOCKS_PLL_MUL(243U, 66U), ///< PLL multiplier of 243.66 + CGC_PLL_MUL_244_0 = BSP_CLOCKS_PLL_MUL(244U, 0U), ///< PLL multiplier of 244.00 + CGC_PLL_MUL_244_33 = BSP_CLOCKS_PLL_MUL(244U, 33U), ///< PLL multiplier of 244.33 + CGC_PLL_MUL_244_5 = BSP_CLOCKS_PLL_MUL(244U, 50U), ///< PLL multiplier of 244.50 + CGC_PLL_MUL_244_66 = BSP_CLOCKS_PLL_MUL(244U, 66U), ///< PLL multiplier of 244.66 + CGC_PLL_MUL_245_0 = BSP_CLOCKS_PLL_MUL(245U, 0U), ///< PLL multiplier of 245.00 + CGC_PLL_MUL_245_33 = BSP_CLOCKS_PLL_MUL(245U, 33U), ///< PLL multiplier of 245.33 + CGC_PLL_MUL_245_5 = BSP_CLOCKS_PLL_MUL(245U, 50U), ///< PLL multiplier of 245.50 + CGC_PLL_MUL_245_66 = BSP_CLOCKS_PLL_MUL(245U, 66U), ///< PLL multiplier of 245.66 + CGC_PLL_MUL_246_0 = BSP_CLOCKS_PLL_MUL(246U, 0U), ///< PLL multiplier of 246.00 + CGC_PLL_MUL_246_33 = BSP_CLOCKS_PLL_MUL(246U, 33U), ///< PLL multiplier of 246.33 + CGC_PLL_MUL_246_5 = BSP_CLOCKS_PLL_MUL(246U, 50U), ///< PLL multiplier of 246.50 + CGC_PLL_MUL_246_66 = BSP_CLOCKS_PLL_MUL(246U, 66U), ///< PLL multiplier of 246.66 + CGC_PLL_MUL_247_0 = BSP_CLOCKS_PLL_MUL(247U, 0U), ///< PLL multiplier of 247.00 + CGC_PLL_MUL_247_33 = BSP_CLOCKS_PLL_MUL(247U, 33U), ///< PLL multiplier of 247.33 + CGC_PLL_MUL_247_5 = BSP_CLOCKS_PLL_MUL(247U, 50U), ///< PLL multiplier of 247.50 + CGC_PLL_MUL_247_66 = BSP_CLOCKS_PLL_MUL(247U, 66U), ///< PLL multiplier of 247.66 + CGC_PLL_MUL_248_0 = BSP_CLOCKS_PLL_MUL(248U, 0U), ///< PLL multiplier of 248.00 + CGC_PLL_MUL_248_33 = BSP_CLOCKS_PLL_MUL(248U, 33U), ///< PLL multiplier of 248.33 + CGC_PLL_MUL_248_5 = BSP_CLOCKS_PLL_MUL(248U, 50U), ///< PLL multiplier of 248.50 + CGC_PLL_MUL_248_66 = BSP_CLOCKS_PLL_MUL(248U, 66U), ///< PLL multiplier of 248.66 + CGC_PLL_MUL_249_0 = BSP_CLOCKS_PLL_MUL(249U, 0U), ///< PLL multiplier of 249.00 + CGC_PLL_MUL_249_33 = BSP_CLOCKS_PLL_MUL(249U, 33U), ///< PLL multiplier of 249.33 + CGC_PLL_MUL_249_5 = BSP_CLOCKS_PLL_MUL(249U, 50U), ///< PLL multiplier of 249.50 + CGC_PLL_MUL_249_66 = BSP_CLOCKS_PLL_MUL(249U, 66U), ///< PLL multiplier of 249.66 + CGC_PLL_MUL_250_0 = BSP_CLOCKS_PLL_MUL(250U, 0U), ///< PLL multiplier of 250.00 + CGC_PLL_MUL_250_33 = BSP_CLOCKS_PLL_MUL(250U, 33U), ///< PLL multiplier of 250.33 + CGC_PLL_MUL_250_5 = BSP_CLOCKS_PLL_MUL(250U, 50U), ///< PLL multiplier of 250.50 + CGC_PLL_MUL_250_66 = BSP_CLOCKS_PLL_MUL(250U, 66U), ///< PLL multiplier of 250.66 + CGC_PLL_MUL_251_0 = BSP_CLOCKS_PLL_MUL(251U, 0U), ///< PLL multiplier of 251.00 + CGC_PLL_MUL_251_33 = BSP_CLOCKS_PLL_MUL(251U, 33U), ///< PLL multiplier of 251.33 + CGC_PLL_MUL_251_5 = BSP_CLOCKS_PLL_MUL(251U, 50U), ///< PLL multiplier of 251.50 + CGC_PLL_MUL_251_66 = BSP_CLOCKS_PLL_MUL(251U, 66U), ///< PLL multiplier of 251.66 + CGC_PLL_MUL_252_0 = BSP_CLOCKS_PLL_MUL(252U, 0U), ///< PLL multiplier of 252.00 + CGC_PLL_MUL_252_33 = BSP_CLOCKS_PLL_MUL(252U, 33U), ///< PLL multiplier of 252.33 + CGC_PLL_MUL_252_5 = BSP_CLOCKS_PLL_MUL(252U, 50U), ///< PLL multiplier of 252.50 + CGC_PLL_MUL_252_66 = BSP_CLOCKS_PLL_MUL(252U, 66U), ///< PLL multiplier of 252.66 + CGC_PLL_MUL_253_0 = BSP_CLOCKS_PLL_MUL(253U, 0U), ///< PLL multiplier of 253.00 + CGC_PLL_MUL_253_33 = BSP_CLOCKS_PLL_MUL(253U, 33U), ///< PLL multiplier of 253.33 + CGC_PLL_MUL_253_5 = BSP_CLOCKS_PLL_MUL(253U, 50U), ///< PLL multiplier of 253.50 + CGC_PLL_MUL_253_66 = BSP_CLOCKS_PLL_MUL(253U, 66U), ///< PLL multiplier of 253.66 + CGC_PLL_MUL_254_0 = BSP_CLOCKS_PLL_MUL(254U, 0U), ///< PLL multiplier of 254.00 + CGC_PLL_MUL_254_33 = BSP_CLOCKS_PLL_MUL(254U, 33U), ///< PLL multiplier of 254.33 + CGC_PLL_MUL_254_5 = BSP_CLOCKS_PLL_MUL(254U, 50U), ///< PLL multiplier of 254.50 + CGC_PLL_MUL_254_66 = BSP_CLOCKS_PLL_MUL(254U, 66U), ///< PLL multiplier of 254.66 + CGC_PLL_MUL_255_0 = BSP_CLOCKS_PLL_MUL(255U, 0U), ///< PLL multiplier of 255.00 + CGC_PLL_MUL_255_33 = BSP_CLOCKS_PLL_MUL(255U, 33U), ///< PLL multiplier of 255.33 + CGC_PLL_MUL_255_5 = BSP_CLOCKS_PLL_MUL(255U, 50U), ///< PLL multiplier of 255.50 + CGC_PLL_MUL_255_66 = BSP_CLOCKS_PLL_MUL(255U, 66U), ///< PLL multiplier of 255.66 + CGC_PLL_MUL_256_0 = BSP_CLOCKS_PLL_MUL(256U, 0U), ///< PLL multiplier of 256.00 + CGC_PLL_MUL_256_33 = BSP_CLOCKS_PLL_MUL(256U, 33U), ///< PLL multiplier of 256.33 + CGC_PLL_MUL_256_5 = BSP_CLOCKS_PLL_MUL(256U, 50U), ///< PLL multiplier of 256.50 + CGC_PLL_MUL_256_66 = BSP_CLOCKS_PLL_MUL(256U, 66U), ///< PLL multiplier of 256.66 + CGC_PLL_MUL_257_0 = BSP_CLOCKS_PLL_MUL(257U, 0U), ///< PLL multiplier of 257.00 + CGC_PLL_MUL_257_33 = BSP_CLOCKS_PLL_MUL(257U, 33U), ///< PLL multiplier of 257.33 + CGC_PLL_MUL_257_5 = BSP_CLOCKS_PLL_MUL(257U, 50U), ///< PLL multiplier of 257.50 + CGC_PLL_MUL_257_66 = BSP_CLOCKS_PLL_MUL(257U, 66U), ///< PLL multiplier of 257.66 + CGC_PLL_MUL_258_0 = BSP_CLOCKS_PLL_MUL(258U, 0U), ///< PLL multiplier of 258.00 + CGC_PLL_MUL_258_33 = BSP_CLOCKS_PLL_MUL(258U, 33U), ///< PLL multiplier of 258.33 + CGC_PLL_MUL_258_5 = BSP_CLOCKS_PLL_MUL(258U, 50U), ///< PLL multiplier of 258.50 + CGC_PLL_MUL_258_66 = BSP_CLOCKS_PLL_MUL(258U, 66U), ///< PLL multiplier of 258.66 + CGC_PLL_MUL_259_0 = BSP_CLOCKS_PLL_MUL(259U, 0U), ///< PLL multiplier of 259.00 + CGC_PLL_MUL_259_33 = BSP_CLOCKS_PLL_MUL(259U, 33U), ///< PLL multiplier of 259.33 + CGC_PLL_MUL_259_5 = BSP_CLOCKS_PLL_MUL(259U, 50U), ///< PLL multiplier of 259.50 + CGC_PLL_MUL_259_66 = BSP_CLOCKS_PLL_MUL(259U, 66U), ///< PLL multiplier of 259.66 + CGC_PLL_MUL_260_0 = BSP_CLOCKS_PLL_MUL(260U, 0U), ///< PLL multiplier of 260.00 + CGC_PLL_MUL_260_33 = BSP_CLOCKS_PLL_MUL(260U, 33U), ///< PLL multiplier of 260.33 + CGC_PLL_MUL_260_5 = BSP_CLOCKS_PLL_MUL(260U, 50U), ///< PLL multiplier of 260.50 + CGC_PLL_MUL_260_66 = BSP_CLOCKS_PLL_MUL(260U, 66U), ///< PLL multiplier of 260.66 + CGC_PLL_MUL_261_0 = BSP_CLOCKS_PLL_MUL(261U, 0U), ///< PLL multiplier of 261.00 + CGC_PLL_MUL_261_33 = BSP_CLOCKS_PLL_MUL(261U, 33U), ///< PLL multiplier of 261.33 + CGC_PLL_MUL_261_5 = BSP_CLOCKS_PLL_MUL(261U, 50U), ///< PLL multiplier of 261.50 + CGC_PLL_MUL_261_66 = BSP_CLOCKS_PLL_MUL(261U, 66U), ///< PLL multiplier of 261.66 + CGC_PLL_MUL_262_0 = BSP_CLOCKS_PLL_MUL(262U, 0U), ///< PLL multiplier of 262.00 + CGC_PLL_MUL_262_33 = BSP_CLOCKS_PLL_MUL(262U, 33U), ///< PLL multiplier of 262.33 + CGC_PLL_MUL_262_5 = BSP_CLOCKS_PLL_MUL(262U, 50U), ///< PLL multiplier of 262.50 + CGC_PLL_MUL_262_66 = BSP_CLOCKS_PLL_MUL(262U, 66U), ///< PLL multiplier of 262.66 + CGC_PLL_MUL_263_0 = BSP_CLOCKS_PLL_MUL(263U, 0U), ///< PLL multiplier of 263.00 + CGC_PLL_MUL_263_33 = BSP_CLOCKS_PLL_MUL(263U, 33U), ///< PLL multiplier of 263.33 + CGC_PLL_MUL_263_5 = BSP_CLOCKS_PLL_MUL(263U, 50U), ///< PLL multiplier of 263.50 + CGC_PLL_MUL_263_66 = BSP_CLOCKS_PLL_MUL(263U, 66U), ///< PLL multiplier of 263.66 + CGC_PLL_MUL_264_0 = BSP_CLOCKS_PLL_MUL(264U, 0U), ///< PLL multiplier of 264.00 + CGC_PLL_MUL_264_33 = BSP_CLOCKS_PLL_MUL(264U, 33U), ///< PLL multiplier of 264.33 + CGC_PLL_MUL_264_5 = BSP_CLOCKS_PLL_MUL(264U, 50U), ///< PLL multiplier of 264.50 + CGC_PLL_MUL_264_66 = BSP_CLOCKS_PLL_MUL(264U, 66U), ///< PLL multiplier of 264.66 + CGC_PLL_MUL_265_0 = BSP_CLOCKS_PLL_MUL(265U, 0U), ///< PLL multiplier of 265.00 + CGC_PLL_MUL_265_33 = BSP_CLOCKS_PLL_MUL(265U, 33U), ///< PLL multiplier of 265.33 + CGC_PLL_MUL_265_5 = BSP_CLOCKS_PLL_MUL(265U, 50U), ///< PLL multiplier of 265.50 + CGC_PLL_MUL_265_66 = BSP_CLOCKS_PLL_MUL(265U, 66U), ///< PLL multiplier of 265.66 + CGC_PLL_MUL_266_0 = BSP_CLOCKS_PLL_MUL(266U, 0U), ///< PLL multiplier of 266.00 + CGC_PLL_MUL_266_33 = BSP_CLOCKS_PLL_MUL(266U, 33U), ///< PLL multiplier of 266.33 + CGC_PLL_MUL_266_5 = BSP_CLOCKS_PLL_MUL(266U, 50U), ///< PLL multiplier of 266.50 + CGC_PLL_MUL_266_66 = BSP_CLOCKS_PLL_MUL(266U, 66U), ///< PLL multiplier of 266.66 + CGC_PLL_MUL_267_0 = BSP_CLOCKS_PLL_MUL(267U, 0U), ///< PLL multiplier of 267.00 + CGC_PLL_MUL_267_33 = BSP_CLOCKS_PLL_MUL(267U, 33U), ///< PLL multiplier of 267.33 + CGC_PLL_MUL_267_5 = BSP_CLOCKS_PLL_MUL(267U, 50U), ///< PLL multiplier of 267.50 + CGC_PLL_MUL_267_66 = BSP_CLOCKS_PLL_MUL(267U, 66U), ///< PLL multiplier of 267.66 + CGC_PLL_MUL_268_0 = BSP_CLOCKS_PLL_MUL(268U, 0U), ///< PLL multiplier of 268.00 + CGC_PLL_MUL_268_33 = BSP_CLOCKS_PLL_MUL(268U, 33U), ///< PLL multiplier of 268.33 + CGC_PLL_MUL_268_5 = BSP_CLOCKS_PLL_MUL(268U, 50U), ///< PLL multiplier of 268.50 + CGC_PLL_MUL_268_66 = BSP_CLOCKS_PLL_MUL(268U, 66U), ///< PLL multiplier of 268.66 + CGC_PLL_MUL_269_0 = BSP_CLOCKS_PLL_MUL(269U, 0U), ///< PLL multiplier of 269.00 + CGC_PLL_MUL_269_33 = BSP_CLOCKS_PLL_MUL(269U, 33U), ///< PLL multiplier of 269.33 + CGC_PLL_MUL_269_5 = BSP_CLOCKS_PLL_MUL(269U, 50U), ///< PLL multiplier of 269.50 + CGC_PLL_MUL_269_66 = BSP_CLOCKS_PLL_MUL(269U, 66U), ///< PLL multiplier of 269.66 + CGC_PLL_MUL_270_0 = BSP_CLOCKS_PLL_MUL(270U, 0U), ///< PLL multiplier of 270.00 + CGC_PLL_MUL_270_33 = BSP_CLOCKS_PLL_MUL(270U, 33U), ///< PLL multiplier of 270.33 + CGC_PLL_MUL_270_5 = BSP_CLOCKS_PLL_MUL(270U, 50U), ///< PLL multiplier of 270.50 + CGC_PLL_MUL_270_66 = BSP_CLOCKS_PLL_MUL(270U, 66U), ///< PLL multiplier of 270.66 + CGC_PLL_MUL_271_0 = BSP_CLOCKS_PLL_MUL(271U, 0U), ///< PLL multiplier of 271.00 + CGC_PLL_MUL_271_33 = BSP_CLOCKS_PLL_MUL(271U, 33U), ///< PLL multiplier of 271.33 + CGC_PLL_MUL_271_5 = BSP_CLOCKS_PLL_MUL(271U, 50U), ///< PLL multiplier of 271.50 + CGC_PLL_MUL_271_66 = BSP_CLOCKS_PLL_MUL(271U, 66U), ///< PLL multiplier of 271.66 + CGC_PLL_MUL_272_0 = BSP_CLOCKS_PLL_MUL(272U, 0U), ///< PLL multiplier of 272.00 + CGC_PLL_MUL_272_33 = BSP_CLOCKS_PLL_MUL(272U, 33U), ///< PLL multiplier of 272.33 + CGC_PLL_MUL_272_5 = BSP_CLOCKS_PLL_MUL(272U, 50U), ///< PLL multiplier of 272.50 + CGC_PLL_MUL_272_66 = BSP_CLOCKS_PLL_MUL(272U, 66U), ///< PLL multiplier of 272.66 + CGC_PLL_MUL_273_0 = BSP_CLOCKS_PLL_MUL(273U, 0U), ///< PLL multiplier of 273.00 + CGC_PLL_MUL_273_33 = BSP_CLOCKS_PLL_MUL(273U, 33U), ///< PLL multiplier of 273.33 + CGC_PLL_MUL_273_5 = BSP_CLOCKS_PLL_MUL(273U, 50U), ///< PLL multiplier of 273.50 + CGC_PLL_MUL_273_66 = BSP_CLOCKS_PLL_MUL(273U, 66U), ///< PLL multiplier of 273.66 + CGC_PLL_MUL_274_0 = BSP_CLOCKS_PLL_MUL(274U, 0U), ///< PLL multiplier of 274.00 + CGC_PLL_MUL_274_33 = BSP_CLOCKS_PLL_MUL(274U, 33U), ///< PLL multiplier of 274.33 + CGC_PLL_MUL_274_5 = BSP_CLOCKS_PLL_MUL(274U, 50U), ///< PLL multiplier of 274.50 + CGC_PLL_MUL_274_66 = BSP_CLOCKS_PLL_MUL(274U, 66U), ///< PLL multiplier of 274.66 + CGC_PLL_MUL_275_0 = BSP_CLOCKS_PLL_MUL(275U, 0U), ///< PLL multiplier of 275.00 + CGC_PLL_MUL_275_33 = BSP_CLOCKS_PLL_MUL(275U, 33U), ///< PLL multiplier of 275.33 + CGC_PLL_MUL_275_5 = BSP_CLOCKS_PLL_MUL(275U, 50U), ///< PLL multiplier of 275.50 + CGC_PLL_MUL_275_66 = BSP_CLOCKS_PLL_MUL(275U, 66U), ///< PLL multiplier of 275.66 + CGC_PLL_MUL_276_0 = BSP_CLOCKS_PLL_MUL(276U, 0U), ///< PLL multiplier of 276.00 + CGC_PLL_MUL_276_33 = BSP_CLOCKS_PLL_MUL(276U, 33U), ///< PLL multiplier of 276.33 + CGC_PLL_MUL_276_5 = BSP_CLOCKS_PLL_MUL(276U, 50U), ///< PLL multiplier of 276.50 + CGC_PLL_MUL_276_66 = BSP_CLOCKS_PLL_MUL(276U, 66U), ///< PLL multiplier of 276.66 + CGC_PLL_MUL_277_0 = BSP_CLOCKS_PLL_MUL(277U, 0U), ///< PLL multiplier of 277.00 + CGC_PLL_MUL_277_33 = BSP_CLOCKS_PLL_MUL(277U, 33U), ///< PLL multiplier of 277.33 + CGC_PLL_MUL_277_5 = BSP_CLOCKS_PLL_MUL(277U, 50U), ///< PLL multiplier of 277.50 + CGC_PLL_MUL_277_66 = BSP_CLOCKS_PLL_MUL(277U, 66U), ///< PLL multiplier of 277.66 + CGC_PLL_MUL_278_0 = BSP_CLOCKS_PLL_MUL(278U, 0U), ///< PLL multiplier of 278.00 + CGC_PLL_MUL_278_33 = BSP_CLOCKS_PLL_MUL(278U, 33U), ///< PLL multiplier of 278.33 + CGC_PLL_MUL_278_5 = BSP_CLOCKS_PLL_MUL(278U, 50U), ///< PLL multiplier of 278.50 + CGC_PLL_MUL_278_66 = BSP_CLOCKS_PLL_MUL(278U, 66U), ///< PLL multiplier of 278.66 + CGC_PLL_MUL_279_0 = BSP_CLOCKS_PLL_MUL(279U, 0U), ///< PLL multiplier of 279.00 + CGC_PLL_MUL_279_33 = BSP_CLOCKS_PLL_MUL(279U, 33U), ///< PLL multiplier of 279.33 + CGC_PLL_MUL_279_5 = BSP_CLOCKS_PLL_MUL(279U, 50U), ///< PLL multiplier of 279.50 + CGC_PLL_MUL_279_66 = BSP_CLOCKS_PLL_MUL(279U, 66U), ///< PLL multiplier of 279.66 + CGC_PLL_MUL_280_0 = BSP_CLOCKS_PLL_MUL(280U, 0U), ///< PLL multiplier of 280.00 + CGC_PLL_MUL_280_33 = BSP_CLOCKS_PLL_MUL(280U, 33U), ///< PLL multiplier of 280.33 + CGC_PLL_MUL_280_5 = BSP_CLOCKS_PLL_MUL(280U, 50U), ///< PLL multiplier of 280.50 + CGC_PLL_MUL_280_66 = BSP_CLOCKS_PLL_MUL(280U, 66U), ///< PLL multiplier of 280.66 + CGC_PLL_MUL_281_0 = BSP_CLOCKS_PLL_MUL(281U, 0U), ///< PLL multiplier of 281.00 + CGC_PLL_MUL_281_33 = BSP_CLOCKS_PLL_MUL(281U, 33U), ///< PLL multiplier of 281.33 + CGC_PLL_MUL_281_5 = BSP_CLOCKS_PLL_MUL(281U, 50U), ///< PLL multiplier of 281.50 + CGC_PLL_MUL_281_66 = BSP_CLOCKS_PLL_MUL(281U, 66U), ///< PLL multiplier of 281.66 + CGC_PLL_MUL_282_0 = BSP_CLOCKS_PLL_MUL(282U, 0U), ///< PLL multiplier of 282.00 + CGC_PLL_MUL_282_33 = BSP_CLOCKS_PLL_MUL(282U, 33U), ///< PLL multiplier of 282.33 + CGC_PLL_MUL_282_5 = BSP_CLOCKS_PLL_MUL(282U, 50U), ///< PLL multiplier of 282.50 + CGC_PLL_MUL_282_66 = BSP_CLOCKS_PLL_MUL(282U, 66U), ///< PLL multiplier of 282.66 + CGC_PLL_MUL_283_0 = BSP_CLOCKS_PLL_MUL(283U, 0U), ///< PLL multiplier of 283.00 + CGC_PLL_MUL_283_33 = BSP_CLOCKS_PLL_MUL(283U, 33U), ///< PLL multiplier of 283.33 + CGC_PLL_MUL_283_5 = BSP_CLOCKS_PLL_MUL(283U, 50U), ///< PLL multiplier of 283.50 + CGC_PLL_MUL_283_66 = BSP_CLOCKS_PLL_MUL(283U, 66U), ///< PLL multiplier of 283.66 + CGC_PLL_MUL_284_0 = BSP_CLOCKS_PLL_MUL(284U, 0U), ///< PLL multiplier of 284.00 + CGC_PLL_MUL_284_33 = BSP_CLOCKS_PLL_MUL(284U, 33U), ///< PLL multiplier of 284.33 + CGC_PLL_MUL_284_5 = BSP_CLOCKS_PLL_MUL(284U, 50U), ///< PLL multiplier of 284.50 + CGC_PLL_MUL_284_66 = BSP_CLOCKS_PLL_MUL(284U, 66U), ///< PLL multiplier of 284.66 + CGC_PLL_MUL_285_0 = BSP_CLOCKS_PLL_MUL(285U, 0U), ///< PLL multiplier of 285.00 + CGC_PLL_MUL_285_33 = BSP_CLOCKS_PLL_MUL(285U, 33U), ///< PLL multiplier of 285.33 + CGC_PLL_MUL_285_5 = BSP_CLOCKS_PLL_MUL(285U, 50U), ///< PLL multiplier of 285.50 + CGC_PLL_MUL_285_66 = BSP_CLOCKS_PLL_MUL(285U, 66U), ///< PLL multiplier of 285.66 + CGC_PLL_MUL_286_0 = BSP_CLOCKS_PLL_MUL(286U, 0U), ///< PLL multiplier of 286.00 + CGC_PLL_MUL_286_33 = BSP_CLOCKS_PLL_MUL(286U, 33U), ///< PLL multiplier of 286.33 + CGC_PLL_MUL_286_5 = BSP_CLOCKS_PLL_MUL(286U, 50U), ///< PLL multiplier of 286.50 + CGC_PLL_MUL_286_66 = BSP_CLOCKS_PLL_MUL(286U, 66U), ///< PLL multiplier of 286.66 + CGC_PLL_MUL_287_0 = BSP_CLOCKS_PLL_MUL(287U, 0U), ///< PLL multiplier of 287.00 + CGC_PLL_MUL_287_33 = BSP_CLOCKS_PLL_MUL(287U, 33U), ///< PLL multiplier of 287.33 + CGC_PLL_MUL_287_5 = BSP_CLOCKS_PLL_MUL(287U, 50U), ///< PLL multiplier of 287.50 + CGC_PLL_MUL_287_66 = BSP_CLOCKS_PLL_MUL(287U, 66U), ///< PLL multiplier of 287.66 + CGC_PLL_MUL_288_0 = BSP_CLOCKS_PLL_MUL(288U, 0U), ///< PLL multiplier of 288.00 + CGC_PLL_MUL_288_33 = BSP_CLOCKS_PLL_MUL(288U, 33U), ///< PLL multiplier of 288.33 + CGC_PLL_MUL_288_5 = BSP_CLOCKS_PLL_MUL(288U, 50U), ///< PLL multiplier of 288.50 + CGC_PLL_MUL_288_66 = BSP_CLOCKS_PLL_MUL(288U, 66U), ///< PLL multiplier of 288.66 + CGC_PLL_MUL_289_0 = BSP_CLOCKS_PLL_MUL(289U, 0U), ///< PLL multiplier of 289.00 + CGC_PLL_MUL_289_33 = BSP_CLOCKS_PLL_MUL(289U, 33U), ///< PLL multiplier of 289.33 + CGC_PLL_MUL_289_5 = BSP_CLOCKS_PLL_MUL(289U, 50U), ///< PLL multiplier of 289.50 + CGC_PLL_MUL_289_66 = BSP_CLOCKS_PLL_MUL(289U, 66U), ///< PLL multiplier of 289.66 + CGC_PLL_MUL_290_0 = BSP_CLOCKS_PLL_MUL(290U, 0U), ///< PLL multiplier of 290.00 + CGC_PLL_MUL_290_33 = BSP_CLOCKS_PLL_MUL(290U, 33U), ///< PLL multiplier of 290.33 + CGC_PLL_MUL_290_5 = BSP_CLOCKS_PLL_MUL(290U, 50U), ///< PLL multiplier of 290.50 + CGC_PLL_MUL_290_66 = BSP_CLOCKS_PLL_MUL(290U, 66U), ///< PLL multiplier of 290.66 + CGC_PLL_MUL_291_0 = BSP_CLOCKS_PLL_MUL(291U, 0U), ///< PLL multiplier of 291.00 + CGC_PLL_MUL_291_33 = BSP_CLOCKS_PLL_MUL(291U, 33U), ///< PLL multiplier of 291.33 + CGC_PLL_MUL_291_5 = BSP_CLOCKS_PLL_MUL(291U, 50U), ///< PLL multiplier of 291.50 + CGC_PLL_MUL_291_66 = BSP_CLOCKS_PLL_MUL(291U, 66U), ///< PLL multiplier of 291.66 + CGC_PLL_MUL_292_0 = BSP_CLOCKS_PLL_MUL(292U, 0U), ///< PLL multiplier of 292.00 + CGC_PLL_MUL_292_33 = BSP_CLOCKS_PLL_MUL(292U, 33U), ///< PLL multiplier of 292.33 + CGC_PLL_MUL_292_5 = BSP_CLOCKS_PLL_MUL(292U, 50U), ///< PLL multiplier of 292.50 + CGC_PLL_MUL_292_66 = BSP_CLOCKS_PLL_MUL(292U, 66U), ///< PLL multiplier of 292.66 + CGC_PLL_MUL_293_0 = BSP_CLOCKS_PLL_MUL(293U, 0U), ///< PLL multiplier of 293.00 + CGC_PLL_MUL_293_33 = BSP_CLOCKS_PLL_MUL(293U, 33U), ///< PLL multiplier of 293.33 + CGC_PLL_MUL_293_5 = BSP_CLOCKS_PLL_MUL(293U, 50U), ///< PLL multiplier of 293.50 + CGC_PLL_MUL_293_66 = BSP_CLOCKS_PLL_MUL(293U, 66U), ///< PLL multiplier of 293.66 + CGC_PLL_MUL_294_0 = BSP_CLOCKS_PLL_MUL(294U, 0U), ///< PLL multiplier of 294.00 + CGC_PLL_MUL_294_33 = BSP_CLOCKS_PLL_MUL(294U, 33U), ///< PLL multiplier of 294.33 + CGC_PLL_MUL_294_5 = BSP_CLOCKS_PLL_MUL(294U, 50U), ///< PLL multiplier of 294.50 + CGC_PLL_MUL_294_66 = BSP_CLOCKS_PLL_MUL(294U, 66U), ///< PLL multiplier of 294.66 + CGC_PLL_MUL_295_0 = BSP_CLOCKS_PLL_MUL(295U, 0U), ///< PLL multiplier of 295.00 + CGC_PLL_MUL_295_33 = BSP_CLOCKS_PLL_MUL(295U, 33U), ///< PLL multiplier of 295.33 + CGC_PLL_MUL_295_5 = BSP_CLOCKS_PLL_MUL(295U, 50U), ///< PLL multiplier of 295.50 + CGC_PLL_MUL_295_66 = BSP_CLOCKS_PLL_MUL(295U, 66U), ///< PLL multiplier of 295.66 + CGC_PLL_MUL_296_0 = BSP_CLOCKS_PLL_MUL(296U, 0U), ///< PLL multiplier of 296.00 + CGC_PLL_MUL_296_33 = BSP_CLOCKS_PLL_MUL(296U, 33U), ///< PLL multiplier of 296.33 + CGC_PLL_MUL_296_5 = BSP_CLOCKS_PLL_MUL(296U, 50U), ///< PLL multiplier of 296.50 + CGC_PLL_MUL_296_66 = BSP_CLOCKS_PLL_MUL(296U, 66U), ///< PLL multiplier of 296.66 + CGC_PLL_MUL_297_0 = BSP_CLOCKS_PLL_MUL(297U, 0U), ///< PLL multiplier of 297.00 + CGC_PLL_MUL_297_33 = BSP_CLOCKS_PLL_MUL(297U, 33U), ///< PLL multiplier of 297.33 + CGC_PLL_MUL_297_5 = BSP_CLOCKS_PLL_MUL(297U, 50U), ///< PLL multiplier of 297.50 + CGC_PLL_MUL_297_66 = BSP_CLOCKS_PLL_MUL(297U, 66U), ///< PLL multiplier of 297.66 + CGC_PLL_MUL_298_0 = BSP_CLOCKS_PLL_MUL(298U, 0U), ///< PLL multiplier of 298.00 + CGC_PLL_MUL_298_33 = BSP_CLOCKS_PLL_MUL(298U, 33U), ///< PLL multiplier of 298.33 + CGC_PLL_MUL_298_5 = BSP_CLOCKS_PLL_MUL(298U, 50U), ///< PLL multiplier of 298.50 + CGC_PLL_MUL_298_66 = BSP_CLOCKS_PLL_MUL(298U, 66U), ///< PLL multiplier of 298.66 + CGC_PLL_MUL_299_0 = BSP_CLOCKS_PLL_MUL(299U, 0U), ///< PLL multiplier of 299.00 + CGC_PLL_MUL_299_33 = BSP_CLOCKS_PLL_MUL(299U, 33U), ///< PLL multiplier of 299.33 + CGC_PLL_MUL_299_5 = BSP_CLOCKS_PLL_MUL(299U, 50U), ///< PLL multiplier of 299.50 + CGC_PLL_MUL_299_66 = BSP_CLOCKS_PLL_MUL(299U, 66U), ///< PLL multiplier of 299.66 + CGC_PLL_MUL_300_0 = BSP_CLOCKS_PLL_MUL(300U, 0U), ///< PLL multiplier of 300.00 + CGC_PLL_MUL_300_33 = BSP_CLOCKS_PLL_MUL(300U, 33U), ///< PLL multiplier of 300.33 + CGC_PLL_MUL_300_5 = BSP_CLOCKS_PLL_MUL(300U, 50U), ///< PLL multiplier of 300.50 + CGC_PLL_MUL_300_66 = BSP_CLOCKS_PLL_MUL(300U, 66U), ///< PLL multiplier of 300.66 + CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 + CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 +} cgc_pll_mul_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_clock_init(void); // Used internally by BSP + +#if BSP_TZ_NONSECURE_BUILD || BSP_SECONDARY_CORE_BUILD +void bsp_clock_freq_var_init(void); // Used internally by BSP + +#endif + +#if BSP_TZ_SECURE_BUILD +void r_bsp_clock_update_callback_set(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/* Used internally by CGC */ + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE +void bsp_prv_operating_mode_set(uint8_t operating_mode); + +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED +uint32_t bsp_prv_power_change_mstp_set(void); +void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); + +#endif + +void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz); + +#if !BSP_FEATURE_CGC_REGISTER_SET_B +void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint16_t sckdivcr2); + +#else +void bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv); +uint32_t bsp_prv_clock_source_get(void); + +#endif + +/* RTC Initialization */ +#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_RTC_HAS_VBTICTLR +void R_BSP_Init_RTC(void); + +#endif + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE +bool bsp_prv_rtc_register_clock_set(bool enable); + +#endif + +#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE +bool bsp_prv_clock_prepare_pre_sleep(void); +void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed); + +#endif + +/* The public function is used to get state or initialize the sub-clock. */ +#if BSP_FEATURE_RTC_IS_IRTC +fsp_err_t R_BSP_SubclockStatusGet(); +fsp_err_t R_BSP_SubclockInitialize(); + +#endif + +#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS +void bsp_prv_clear_pfb(void); +void bsp_prv_set_pfb(void); + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_common.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_common.c new file mode 100644 index 0000000000..4368950994 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_common.c @@ -0,0 +1,311 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #define WEAK_ERROR_ATTRIBUTE + #define WEAK_INIT_ATTRIBUTE + #pragma weak fsp_error_log = fsp_error_log_internal + #pragma weak bsp_init = bsp_init_internal +#elif defined(__GNUC__) + + #define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal"))) + + #define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal"))) +#endif + +#define FSP_SECTION_VERSION ".version" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/** Prototype of initialization function called before main. This prototype sets the weak association of this + * function to an internal example implementation. If this function is defined in the application code, the + * application code version is used. */ + +void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE; + +void bsp_init_internal(void * p_args); /// Default initialization function + +#if (1 == BSP_CFG_ASSERT) + +/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ASSERT is set to 1. This + * prototype sets the weak association of this function to an internal example implementation. */ + +void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE; + +void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function + +#endif +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 +static bool bsp_valid_register_check(uint32_t register_address, + uint32_t const * const p_register_table, + uint32_t register_table_length); + +#endif + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* FSP pack version structure. */ +static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) = +{ + .version_id_b = + { + .minor = FSP_VERSION_MINOR, + .major = FSP_VERSION_MAJOR, + .build = FSP_VERSION_BUILD, + .patch = FSP_VERSION_PATCH + } +}; + +/* Public FSP version name. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_STRING; + +/* Unique FSP version ID. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_BUILD_STRING; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the FSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + *p_version = g_fsp_version; + + return FSP_SUCCESS; +} + +#if (1 == BSP_CFG_ASSERT) + +/*******************************************************************************************************************//** + * Default error logger function, used only if fsp_error_log is not defined in the user application. + * + * @param[in] err The error code encountered. + * @param[in] file The file name in which the error code was encountered. + * @param[in] line The line number at which the error code was encountered. + **********************************************************************************************************************/ +void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line) +{ + /** Do nothing. Do not generate any 'unused' warnings. */ + FSP_PARAMETER_NOT_USED(err); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); +} + +#endif + +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 + +/*******************************************************************************************************************//** + * Read a secure 8-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read (uint8_t volatile const * p_reg) +{ + uint8_t volatile * p_reg_s = (uint8_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_SYSTEM->SCKDIVCR2, + (uint32_t) &R_SYSTEM->SCKSCR, + (uint32_t) &R_SYSTEM->SPICKDIVCR, + (uint32_t) &R_SYSTEM->SPICKCR, + (uint32_t) &R_SYSTEM->SCICKDIVCR, + (uint32_t) &R_SYSTEM->SCICKCR, + (uint32_t) &R_SYSTEM->CANFDCKCR, + (uint32_t) &R_SYSTEM->PLLCR, + (uint32_t) &R_SYSTEM->PLL2CR, + (uint32_t) &R_SYSTEM->MOCOCR, + (uint32_t) &R_SYSTEM->OPCCR, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint8_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +/*******************************************************************************************************************//** + * Read a secure 16-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read (uint16_t volatile const * p_reg) +{ + uint16_t volatile * p_reg_s = (uint16_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_DTC->DTCSTS, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint16_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +/*******************************************************************************************************************//** + * Read a secure 32-bit STYPE3 register in the non-secure state. + * + * @param[in] p_reg The address of the secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read (uint32_t volatile const * p_reg) +{ + uint32_t volatile * p_reg_s = (uint32_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET); + + /* Table of secure registers that may be read from the non-secure application. */ + static const uint32_t valid_addresses[] = + { + (uint32_t) &R_SYSTEM->SCKDIVCR, + }; + + if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses, + sizeof(valid_addresses) / sizeof(valid_addresses[0]))) + { + return *p_reg_s; + } + + /* Generate a trustzone access violation by accessing the non-secure aliased address. */ + return *((uint32_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET)); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Default initialization function, used only if bsp_init is not defined in the user application. + **********************************************************************************************************************/ +void bsp_init_internal (void * p_args) +{ + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(p_args); +} + +#if defined(__ARMCC_VERSION) + +/*******************************************************************************************************************//** + * Default implementation of assert for AC6. + **********************************************************************************************************************/ +__attribute__((weak, noreturn)) +void __aeabi_assert (const char * expr, const char * file, int line) +{ + FSP_PARAMETER_NOT_USED(expr); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + +#elif defined(__GNUC__) + +/* The default assert implementation for GCC brings in printing/formatting code. FSP overrides the default assert + * behavior to reduce code size. */ + + #if !BSP_CFG_USE_STANDARD_ASSERT + +/*******************************************************************************************************************//** + * Default implementation of assert for GCC. + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE void __assert_func (const char * file, int line, const char * func, const char * expr) +{ + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + FSP_PARAMETER_NOT_USED(func); + FSP_PARAMETER_NOT_USED(expr); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + + #endif + +#endif + +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1 + +/*******************************************************************************************************************//** + * Check if a register address should be accessible by the non-secure application. + **********************************************************************************************************************/ +static bool bsp_valid_register_check (uint32_t register_address, + uint32_t const * const p_register_table, + uint32_t register_table_length) +{ + bool valid = false; + + /* Check if the given address is valid. */ + for (uint32_t i = 0; i < register_table_length; i++) + { + if (p_register_table[i] == register_address) + { + valid = true; + break; + } + } + + return valid; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_common.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_common.h new file mode 100644 index 0000000000..e92fe1470e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_common.h @@ -0,0 +1,767 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include +#include + +/* Different compiler support. */ +#include "../../inc/api/fsp_common_api.h" +#include "bsp_compiler_support.h" + +/* BSP module includes */ +#include "../../src/bsp/mcu/all/bsp_tfu.h" +#include "../../src/bsp/mcu/all/bsp_sdram.h" +#include "../../src/bsp/mcu/all/bsp_mmf.h" +#include "../../src/bsp/mcu/all/bsp_ipc.h" +#include "../../src/bsp/mcu/all/bsp_ospi_b.h" + +#include "bsp_linker_info.h" + +#include "bsp_cfg.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used to signify that an ELC event is not able to be used as an interrupt. */ +#define BSP_IRQ_DISABLED (0xFFU) + +/* Version of this module's code and API. */ + +#if 1 == BSP_CFG_RTOS /* ThreadX */ + #include "tx_user.h" + #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) + #include "tx_port.h" + #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); + #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); + #else + #define FSP_CONTEXT_SAVE + #define FSP_CONTEXT_RESTORE + #endif +#else + #define FSP_CONTEXT_SAVE + #define FSP_CONTEXT_RESTORE +#endif + +/** Macro that can be defined in order to enable logging in FSP modules. */ +#ifndef FSP_LOG_PRINT + #define FSP_LOG_PRINT(X) +#endif + +/** Macro to log and return error without an assertion. */ +#ifndef FSP_RETURN + + #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ + return err; +#endif + +/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in + * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ +#if (1 == BSP_CFG_ASSERT) + + #ifndef FSP_ERROR_LOG + #define FSP_ERROR_LOG(err) \ + fsp_error_log((err), __FILE__, __LINE__); + #endif +#else + + #define FSP_ERROR_LOG(err) +#endif + +/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP + * functions. */ +#if (3 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) +#elif (2 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) {assert(a);} +#else + #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) +#endif // ifndef FSP_ASSERT + +/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used + * to identify runtime errors in FSP functions. */ + +#define FSP_ERROR_RETURN(a, err) \ + { \ + if ((a)) \ + { \ + (void) 0; /* Do nothing */ \ + } \ + else \ + { \ + FSP_ERROR_LOG(err); \ + return err; \ + } \ + } + +/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates. + * This macro can be redefined to add a timeout if necessary. */ +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +#ifndef FSP_REGISTER_READ + +/* Read a register and discard the result. */ + #define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A)); +#endif + +/**************************************************************** + * + * This check is performed to select suitable ASM API with respect to core + * + * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so + * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ + +#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4) + #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) + #endif +#else + #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #endif + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) +#endif + +/* This macro defines a variable for saving previous mask value */ +#ifndef FSP_CRITICAL_SECTION_DEFINE + + #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U +#endif + +/* These macros abstract methods to save and restore the interrupt state for different architectures. */ +#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK + #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) +#else + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI + #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ + (8U - __NVIC_PRIO_BITS))) +#endif + +/** This macro temporarily saves the current interrupt state and disables interrupts. */ +#ifndef FSP_CRITICAL_SECTION_ENTER + #define FSP_CRITICAL_SECTION_ENTER \ + old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ + FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) +#endif + +/** This macro restores the previously saved interrupt state, reenabling interrupts. */ +#ifndef FSP_CRITICAL_SECTION_EXIT + #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) +#endif + +/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ +#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) + +/** Used to signify that the requested IRQ vector is not defined in this system. */ +#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) + +/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */ +#if (BSP_CFG_MCU_PART_SERIES == 8) + #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) +#else + #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U) +#endif + +/* Use the secure registers for secure projects and flat projects. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + #define FSP_PRIV_TZ_USE_SECURE_REGS (1) +#else + #define FSP_PRIV_TZ_USE_SECURE_REGS (0) +#endif + +/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ +#if BSP_CFG_EARLY_INIT + #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) +#else + #define BSP_SECTION_EARLY_INIT +#endif + +/* Used to determine if this project is part of a multicore FSP Solution. */ +#if defined(BSP_PARTITION_FLASH_CPU1_S_START) + #define BSP_MULTICORE_PROJECT (1) +#else + #define BSP_MULTICORE_PROJECT (0) +#endif + +#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2 +BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg); +BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg); +BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg); + +#endif + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + +/* + * If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register + * from the secure application using the provided non-secure callable functions. + */ + #define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X))) + #define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X))) + #define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X))) +#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + +/*******************************************************************************************************************//** + * Read a non-secure 8-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) +{ + p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/*******************************************************************************************************************//** + * Read a non-secure 16-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) +{ + p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/*******************************************************************************************************************//** + * Read a non-secure 32-bit STYPE3 register in the secure state. + * + * @param[in] p_reg The address of the non-secure register. + * + * @return Value read from the register. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) +{ + p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); + + return *p_reg; +} + +/* + * If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register + * using the non-secure aliased address. + */ + #define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X)) + #define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X)) + #define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X)) +#else + #define FSP_STYPE3_REG8_READ(X, S) (X) + #define FSP_STYPE3_REG16_READ(X, S) (X) + #define FSP_STYPE3_REG32_READ(X, S) (X) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Different warm start entry locations in the BSP. */ +typedef enum e_bsp_warm_start_event +{ + BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. + BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. + BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up +} bsp_warm_start_event_t; + +/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_PCLKD = 0, + FSP_PRIV_CLOCK_PCLKC = 4, + FSP_PRIV_CLOCK_PCLKB = 8, + FSP_PRIV_CLOCK_PCLKA = 12, + FSP_PRIV_CLOCK_BCLK = 16, + FSP_PRIV_CLOCK_PCLKE = 20, + FSP_PRIV_CLOCK_ICLK = 24, + FSP_PRIV_CLOCK_FCLK = 28, + FSP_PRIV_CLOCK_CPUCLK = 32, + FSP_PRIV_CLOCK_UNUSED = 255, ///< Sentinel value for unused clock +} fsp_priv_clock_t; + +/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ +typedef enum e_fsp_priv_source_clock +{ + FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator + FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator + FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator + FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator + FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator + FSP_PRIV_CLOCK_PLL = 5, ///< The PLL output + FSP_PRIV_CLOCK_PLL1P = 5, ///< The PLL1P output + FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 output + FSP_PRIV_CLOCK_PLL2P = 6, ///< The PLL2P output + FSP_PRIV_CLOCK_PLL1Q = 7, ///< The PLL1Q output + FSP_PRIV_CLOCK_PLL1R = 8, ///< The PLL1R output + FSP_PRIV_CLOCK_PLL2Q = 9, ///< The PLL2Q output + FSP_PRIV_CLOCK_PLL2R = 10, ///< The PLL2R output +} fsp_priv_source_clock_t; + +typedef struct st_bsp_unique_id +{ + union + { + uint32_t unique_id_words[4]; + uint8_t unique_id_bytes[16]; + }; +} bsp_unique_id_t; + +typedef struct st_bsp_part_number +{ + union + { + uint32_t part_number_words[4]; + uint8_t part_number_bytes[16]; + }; +} bsp_part_number_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); + +/*********************************************************************************************************************** + * Global variables (defined in other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Return active interrupt vector number value + * + * @return Active interrupt vector number value + **********************************************************************************************************************/ +__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) +{ + xPSR_Type xpsr_value; + xpsr_value.w = __get_xPSR(); + + return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); +} + +/*******************************************************************************************************************//** + * Gets the frequency of a system clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) +{ + /* Check if the provided clock is an unused clock. */ + if (FSP_PRIV_CLOCK_UNUSED == clock) + { + return 0; + } + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); + uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; + + #if BSP_FEATURE_CGC_HAS_CPUCLK + if (FSP_PRIV_CLOCK_CPUCLK == clock) + { + return SystemCoreClock; + } + + /* Get CPUCLK divisor */ + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + #if (BSP_CFG_CPU_CORE == 1) + uint32_t cpuclk_div = + (FSP_STYPE3_REG16_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCKDIVCR2_CPUCK1_Msk) >> + R_SYSTEM_SCKDIVCR2_CPUCK1_Pos; + #else + uint32_t cpuclk_div = FSP_STYPE3_REG16_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; + #endif + #else + uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; + #endif + + /* Determine if either divisor is a multiple of 3 */ + if ((cpuclk_div | clock_div) & 8U) + { + /* Convert divisor settings to their actual values */ + cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div); + clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div); + + /* Calculate clock with multiplication and division instead of shifting */ + return (SystemCoreClock * cpuclk_div) / clock_div; + } + else + { + return (SystemCoreClock << cpuclk_div) >> clock_div; + } + + #else + uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; + + return (SystemCoreClock << iclk_div) >> clock_div; + #endif +#else + FSP_PARAMETER_NOT_USED(clock); + + return SystemCoreClock; +#endif +} + +/*******************************************************************************************************************//** + * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). + * + * @return Clock Divider + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) +{ + if (2U >= ckdivcr) + { + + /* clock_div: + * - Clock Divided by 1: 0 + * - Clock Divided by 2: 1 + * - Clock Divided by 4: 2 + */ + return 1U << ckdivcr; + } + else if (3U == ckdivcr) + { + + /* Clock Divided by 6 */ + return 6U; + } + else if (4U == ckdivcr) + { + + /* Clock Divided by 8 */ + return 8U; + } + else if (5U == ckdivcr) + { + + /* Clock Divided by 3 */ + return 3U; + } + else if (6U == ckdivcr) + { + + /* Clock Divided by 5 */ + return 5U; + } + else if (7U == ckdivcr) + { + + /* Clock Divided by 10 */ + return 10U; + } + else + { + + /* clock_div: + * - Clock Divided by 16: 8 + * - Clock Divided by 32: 9 + */ + return 16U << (ckdivcr - 8U); + } +} + +#if BSP_FEATURE_SCI_HAS_SCISPI_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SCI/SPI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) +{ + uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; + uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; + + return R_BSP_SourceClockHzGet(scispicksel) / clock_div; +} + +#endif +#if BSP_FEATURE_SPI_HAS_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SPI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void) +{ + uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); + uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t spicksel = + (fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR, + BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> + R_SYSTEM_SPICKCR_CKSEL_Pos); + + return R_BSP_SourceClockHzGet(spicksel) / clock_div; +} + +#endif +#if BSP_FEATURE_SCI_HAS_CLOCK + +/*******************************************************************************************************************//** + * Gets the frequency of a SCI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void) +{ + uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); + uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t scicksel = + (fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR, + BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> + R_SYSTEM_SCICKCR_SCICKSEL_Pos); + + return R_BSP_SourceClockHzGet(scicksel) / clock_div; +} + +#endif + +/*******************************************************************************************************************//** + * Get unique ID for this device. + * + * @return A pointer to the unique identifier structure + **********************************************************************************************************************/ +__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) +{ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + + return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET); +#else + + return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; +#endif +} + +/*******************************************************************************************************************//** + * Get part number for this device. + * + * @param[out] p_part_number Memory address to return MCU's part number to. + * + * @retval FSP_SUCCESS Part number information stored. + * @retval FSP_ERR_ASSERTION The parameter p_part_number is NULL. + * @retval FSP_ERR_NOT_FOUND An error occurred when retrieving data from part number register. + **********************************************************************************************************************/ +__STATIC_INLINE fsp_err_t R_BSP_PartNumberGet (bsp_part_number_t * const p_part_number) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + if (NULL == p_part_number) + { + return FSP_ERR_ASSERTION; + } +#endif + + /* Pointer to Part Numbering Register PNR */ +#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1 + bsp_part_number_t * p_pnr = (bsp_part_number_t *) (BSP_FEATURE_BSP_PART_NUMBER_POINTER | BSP_FEATURE_TZ_NS_OFFSET); +#else + bsp_part_number_t * p_pnr = (bsp_part_number_t *) BSP_FEATURE_BSP_PART_NUMBER_POINTER; +#endif + + /* In case part number is following the right order + * for example: R 7 F A 8 E 1 A F D C F B_ _ _ */ + if (p_pnr->part_number_bytes[0] == 'R') + { + memcpy(p_part_number, p_pnr, sizeof(bsp_part_number_t)); + } + /* In case part number is in reverse order, 'R' letter should be in position 12 + * for example: K N C 3 7 0 1 E 0 A F 7 R _ _ _ */ + else if (p_pnr->part_number_bytes[12] == 'R') + { + for (uint8_t i = 0; i < sizeof(bsp_part_number_t); i++) + { + if (i <= 12) + { + p_part_number->part_number_bytes[i] = p_pnr->part_number_bytes[12 - i]; + } + else + { + p_part_number->part_number_bytes[i] = p_pnr->part_number_bytes[i]; + } + } + } + else + { + return FSP_ERR_NOT_FOUND; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheDisable (void) +{ +#if BSP_FEATURE_FLASH_CACHE + R_FCACHE->FCACHEE = 0U; +#endif + +#ifdef R_CACHE + #if BSP_FEATURE_FLASH_CODE_CACHE_VERSION == 2 + uint32_t volatile * p_ccactl = &R_CACHE->CCACTL; + uint32_t volatile * p_ccawta = &R_CACHE->CCAWTA; + + #if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + if (1 == R_CPSCU->CACHESAR_b.CACHESA) + { + /* Access CCACTL using the non-secure alias. */ + p_ccactl = (uint32_t volatile *) ((uint32_t) p_ccactl | BSP_FEATURE_TZ_NS_OFFSET); + + /* Access CCAWTA using the non-secure alias. */ + p_ccawta = (uint32_t volatile *) ((uint32_t) p_ccawta | BSP_FEATURE_TZ_NS_OFFSET); + } + #endif + + /* Writeback and flush cache when disabling + * Refer to the CCAFCT register description in the relevant hardware manual */ + if (*p_ccawta & R_CACHE_CCAWTA_WT_Msk) + { + *p_ccactl = R_CACHE_CCACTL_FC_Msk; + } + else + { + *p_ccactl = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk; + } + + FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); + #else + + /* Disable the C-Cache. */ + R_CACHE->CCACTL = 0U; + #endif +#endif +} + +/*******************************************************************************************************************//** + * Enables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheEnable (void) +{ +#if BSP_FEATURE_FLASH_CACHE + + /* Invalidate the flash cache and wait until it is invalidated. (See "Operation" in the Flash Memory section + * of the relevant hardware manual). */ + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + /* Enable flash cache. */ + R_FCACHE->FCACHEE = 1U; +#endif + +#ifdef R_CACHE + #if BSP_FEATURE_FLASH_CODE_CACHE_VERSION == 1 + + /* Configure the C-Cache line size. */ + R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; + + /* Enable the C-Cache. */ + R_CACHE->CCACTL = 1U; + #else + uint32_t volatile * p_ccactl = &R_CACHE->CCACTL; + + /* Flush cache before enabling */ + R_CACHE->CCAFCT_b.FC = 1; + + /* Check that no flush or writeback are ongoing before enabling + * Refer to the CCAFCT register description in the relevant hardware manual */ + FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); + + #if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + if (1 == R_CPSCU->CACHESAR_b.CACHESA) + { + /* Access CCACTL using the non-secure alias. */ + p_ccactl = (uint32_t volatile *) ((uint32_t) p_ccactl | BSP_FEATURE_TZ_NS_OFFSET); + } + #endif + + /* Enable the C-Cache. */ + *p_ccactl = 1U; + #endif +#endif +} + +#if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS && !BSP_SECONDARY_CORE_BUILD && defined(BSP_PARTITION_FLASH_CPU1_S_START) + #define BSP_CPU1ACTCSR_KEY_CODE 0xA5 + +/*******************************************************************************************************************//** + * Sets the secondary core VTOR and activates the secondary core. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_SecondaryCoreStart (void) +{ + /* Setup secondary CPU vector table */ + R_CPU_CTRL->CPU1INITVTOR = (uint32_t) BSP_PARTITION_FLASH_CPU1_S_START; + + /* When debugging multicore projects, CPU1 may already be activated by the debugger with CPU1WAITCR set to 1. + * This allows the debugger to connect to CPU1 prior to it being started by CPU0. + * If this is the case, then the secondary core must be started by clearing CPU1WAITCR. */ + R_CPU_CTRL->CPU1WAITCR = 0; + + /* Activate secondary CPU by setting key code and activation request in CPU1ACTCSR */ + R_CPU_CTRL->CPU1ACTCSR = (BSP_CPU1ACTCSR_KEY_CODE << R_CPU_CTRL_CPU1ACTCSR_KEY_Pos) | + R_CPU_CTRL_CPU1ACTCSR_ACTREQ_Msk; +} + +#endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if (1 == BSP_CFG_ASSERT) + +/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ +void fsp_error_log(fsp_err_t err, const char * file, int32_t line); + +#endif + +/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will + * alert the user of the error. The user can override this default behavior by defining their own + * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. + */ +#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) + + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h new file mode 100644 index 0000000000..9ddff68ed5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h @@ -0,0 +1,90 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_COMPILER_SUPPORT_H + #define BSP_COMPILER_SUPPORT_H + + #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #include "arm_cmse.h" + #endif + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #if defined(__ARMCC_VERSION) /* AC6 compiler */ + +/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load + * memory (ROM) is reserved unnecessarily. */ + #define BSP_UNINIT_SECTION_PREFIX ".bss" + #define BSP_DONT_REMOVE __attribute__((used)) + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #elif defined(__GNUC__) /* GCC compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_DONT_REMOVE __attribute__((used)) + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_DONT_REMOVE __root + #define BSP_ATTRIBUTE_STACKLESS __stackless + #define BSP_FORCE_INLINE _Pragma("inline=forced") + #endif + + #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".ram_noinit" + #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" + #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" + +/* Compiler neutral macros. */ + #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + + #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) + + #define BSP_WEAK_REFERENCE __attribute__((weak)) + +/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ + #define BSP_STACK_ALIGNMENT (8) + +/*********************************************************************************************************************** + * TrustZone definitions + **********************************************************************************************************************/ + #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) + #if defined(__ICCARM__) /* IAR compiler */ + #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call + #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry + #else + #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) + #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) + #endif + #else + #define BSP_CMSE_NONSECURE_CALL + #define BSP_CMSE_NONSECURE_ENTRY + #endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end of addtogroup BSP_MCU) */ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_delay.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_delay.c new file mode 100644 index 0000000000..f3cbc18ce0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_delay.c @@ -0,0 +1,207 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_delay.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_DELAY_NS_PER_SECOND (1000000000) +#define BSP_DELAY_US_PER_SECOND (1000000) +#define BSP_DELAY_NS_PER_US (1000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Delay for at least the specified duration in units and return. It is recommended to only use this + * function for short delays since it can be inaccurate and it can block the CPU from executing + * other tasks. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are: + * BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n + * For example:@n + * At 1 MHz one cycle takes 1 microsecond (.000001 seconds).@n + * At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds.@n + * Therefore one run through bsp_prv_software_delay_loop() takes: + * ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns. + * A delay of 2 us therefore requires 2000ns/332ns or 6 loops. + * + * @note The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. + * - @120MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds. + * - @32MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds. + * - @1GHz: ((0xFFFFFFFF loops * 1 cycles /loop) / 1000000000) = 4.29 seconds. + * + * @note Number of cycles per loop is defined based on the CPU core in the following macro: BSP_DELAY_LOOP_CYCLES + * + * @note Requests for very large delays will be affected by rounding in the calculations and the actual delay + * achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds. + * + * @note If the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called + * at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the + * overhead associated with executing the code to just get to this point has certainly satisfied the requested delay. + * + * @note This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires + * that the BSP has already initialized the CGC (which it does as part of the Sysinit). + * Care should be taken to ensure this remains the case if in the future this function were to be called as part + * of the BSP initialization. + * + * @note This function will delay for **at least** the specified duration. Due to overhead in calculating the correct number + * of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified. + * Approximate overhead for this function is as follows: + * - CM4: 20-50 cycles + * - CM33: 10-60 cycles + * - CM23: 75-200 cycles + * + * @note If more accurate microsecond timing must be performed in software it is recommended to use + * bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE() + * to convert a calculated delay cycle count to a number of software delay loops. + * + * @note Delay timing may be significantly affected by compiler optimization levels. Higher levels of optimization will + * result in more accurate software delays. + **********************************************************************************************************************/ + +void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) +{ + uint32_t iclk_hz; + uint32_t loops_required = 0; + uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */ + + iclk_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */ + +#if (BSP_CFG_MCU_PART_SERIES == 8) || (BSP_CFG_MCU_PART_SERIES == 6) + if (iclk_hz >= BSP_MOCO_HZ) + { + /* For larger system clock values the below calculation in the else causes inaccurate delays due to rounding errors: + * + * ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz + * + * For system clock values greater than the MOCO speed the following delay calculation is used instead. + * The value is always rounded up to ensure the delay is at least the supplied value. + */ + uint32_t cycles_per_us = (iclk_hz + (BSP_DELAY_US_PER_SECOND * BSP_DELAY_LOOP_CYCLES) - 1) / + (BSP_DELAY_US_PER_SECOND * BSP_DELAY_LOOP_CYCLES); + + uint64_t loops_required_u64 = ((uint64_t) total_us) * cycles_per_us; + + if (loops_required_u64 > UINT32_MAX) + { + loops_required = UINT32_MAX; + } + else + { + loops_required = (uint32_t) loops_required_u64; + } + } + else +#endif + { + uint32_t cycles_requested; + uint32_t ns_per_cycle; + uint64_t ns_64bits; + + /* Running on the Sub-clock (32768 Hz) there are 30517 ns/cycle. This means one cycle takes 31 us. One execution + * loop of the delay_loop takes 6 cycles which at 32768 Hz is 180 us. That does not include the overhead below prior to even getting + * to the delay loop. Given this, at this frequency anything less then a delay request of 122 us will not even generate a single + * pass through the delay loop. For this reason small delays (<=~200 us) at this slow clock rate will not be possible and such a request + * will generate a minimum delay of ~200 us.*/ + ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz; /** Get the # of nanoseconds/cycle. */ + + /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */ + /* division as that pulls in a division library. */ + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + cycles_requested = ((uint32_t) ns_64bits / ns_per_cycle); + loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES; + } + else + { + /* We did overflow. Try dividing down first. */ + total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)); + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + loops_required = (uint32_t) ns_64bits; + } + else + { + /* We still overflowed, use the max count for cycles */ + loops_required = UINT32_MAX; + } + } + } + + /** Only delay if the supplied parameters constitute a delay. */ + if (loops_required > (uint32_t) 0) + { + bsp_prv_software_delay_loop(loops_required); + } +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles + * occur when the loop exits. The 'naked' attribute indicates that the specified function does not need + * prologue/epilogue sequences generated by the compiler. + * @param[in] loop_cnt The number of loops to iterate. + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__( + (unused)) uint32_t loop_cnt) +{ + __asm volatile ( +#if defined(RENESAS_CORTEX_M85) && (defined(__ARMCC_VERSION) || defined(__GNUC__)) + + /* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */ + /* IAR does not support alignment control within inline assembly. */ + ".balign 8\n" +#endif + "sw_delay_loop: \n" +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || (defined(__llvm__) && !defined(__CLANG_TIDY__)) + " subs r0, #1 \n" ///< 1 cycle +#elif defined(__GNUC__) + " sub r0, r0, #1 \n" ///< 1 cycle +#endif + + " cmp r0, #0 \n" ///< 1 cycle + +/* CM0 and CM23 have a different instruction set */ +#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC) + " bne sw_delay_loop \n" ///< 2 cycles +#else + " bne.n sw_delay_loop \n" ///< 2 cycles +#endif + " bx lr \n"); ///< 2 cycles +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_delay.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_delay.h new file mode 100644 index 0000000000..a2f699765a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_delay.h @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_DELAY_H +#define BSP_DELAY_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "bsp_compiler_support.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of cycles required per software delay loop. */ +#ifndef BSP_DELAY_LOOP_CYCLES + #if defined(RENESAS_CORTEX_M85) + +/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for + * GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in + * this case. */ + #if defined(__ICCARM__) + #define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1) + #else + #define BSP_DELAY_LOOP_CYCLES (1) + #endif + +/* On devices with Flash LP, ROM reads take an additional cycle when ICLK is greater than 32 MHz. */ + #elif BSP_FEATURE_CGC_HAS_MEMWAIT && !BSP_FEATURE_FLASH_CACHE && (BSP_FEATURE_FLASH_CODE_CACHE_VERSION == 0) + #define BSP_DELAY_LOOP_CYCLES (4 + (2 * (uint32_t) (SystemCoreClock > 32000000))) + #else + #define BSP_DELAY_LOOP_CYCLES (4) + #endif +#endif + +/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle + * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures + * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count + * of 0. */ +#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) + +/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ +typedef enum +{ + BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds + BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds + BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds +} bsp_delay_units_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h new file mode 100644 index 0000000000..f388be3293 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_exceptions.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_EXCEPTIONS_H + #define BSP_EXCEPTIONS_H + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c new file mode 100644 index 0000000000..6b6f6d8c46 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c @@ -0,0 +1,122 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#if (BSP_FEATURE_ICU_NMIER_MAX_INDEX > 15U) + #define BSP_PRV_NMIER_T uint32_t +#else + #define BSP_PRV_NMIER_T uint16_t +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** This array holds callback functions. */ +bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_FEATURE_ICU_NMIER_MAX_INDEX + 1] BSP_SECTION_EARLY_INIT; + +void NMI_Handler(void); +static void bsp_group_irq_call(bsp_grp_irq_t irq); + +/*******************************************************************************************************************//** + * Calls the callback function for an interrupt if a callback has been registered. + * + * @param[in] irq Which interrupt to check and possibly call. + * + * @retval FSP_SUCCESS Callback was called. + * @retval FSP_ERR_INVALID_ARGUMENT No valid callback has been registered for this interrupt source. + * + * @warning This function is called from within an interrupt + **********************************************************************************************************************/ +static void bsp_group_irq_call (bsp_grp_irq_t irq) +{ + /** Check for valid callback */ + if (NULL != g_bsp_group_irq_sources[irq]) + { + /** Callback has been found. Call it. */ + g_bsp_group_irq_sources[irq](irq); + } +} + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Register a callback function for supported interrupts. If NULL is passed for the callback argument then any + * previously registered callbacks are unregistered. + * + * @param[in] irq Interrupt for which to register a callback. + * @param[in] p_callback Pointer to function to call when interrupt occurs. + * + * @retval FSP_SUCCESS Callback registered + * @retval FSP_ERR_ASSERTION Callback pointer is NULL + **********************************************************************************************************************/ +fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Check pointer for NULL value. */ + FSP_ASSERT(p_callback); +#endif + + /* Register callback. */ + g_bsp_group_irq_sources[irq] = p_callback; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because + * there are many sources that map to the NMI exception. + **********************************************************************************************************************/ +void NMI_Handler (void) +{ + /* NMISR is masked by NMIER to prevent iterating over NMI status flags that are not enabled. */ + BSP_PRV_NMIER_T nmier = R_ICU->NMIER; + BSP_PRV_NMIER_T nmisr = R_ICU->NMISR & nmier; + + /* Loop over all NMI status flags */ + for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= (bsp_grp_irq_t) (BSP_FEATURE_ICU_NMIER_MAX_INDEX); irq++) + { + /* If the current irq status register is set call the irq callback. */ + if (0U != (nmisr & (1U << irq))) + { + (void) bsp_group_irq_call(irq); + } + } + + /* Clear status flags that have been handled. */ + R_ICU->NMICLR = nmisr; + +#if BSP_CFG_MCU_PART_SERIES == 8 + + /* Wait for NMISR to be cleared before exiting the ISR to prevent the IRQ from being regenerated. + * See "NMICLR : Non-Maskable Interrupt Status Clear Register" description in the ICU section + * of the relevant hardware manual */ + FSP_HARDWARE_REGISTER_WAIT((R_ICU->NMISR & nmisr), 0); +#endif +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h new file mode 100644 index 0000000000..5aede0736c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h @@ -0,0 +1,69 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_GROUP_IRQ_H +#define BSP_GROUP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_GROUP_IRQ_T + +/** Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error + BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error + BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error + BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error + BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error + BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error + BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error +} bsp_grp_irq_t; + +#endif + +/* Callback type. */ +typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_group_interrupt_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_guard.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_guard.c new file mode 100644 index 0000000000..605fc63af2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_guard.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_guard.h" + +/* Only the secure project has nonsecure callable functions. */ +#if BSP_TZ_SECURE_BUILD + +/* If the CGG Security Attribution is configured to secure access only. */ + #if BSP_CFG_CLOCKS_SECURE == 1 + +/*******************************************************************************************************************//** + * Set the callback used by the secure project to notify the nonsecure project when the clock settings have changed. + * + * @retval FSP_SUCCESS Callback set. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory) +{ + bsp_clock_update_callback_t p_callback_checked = + (bsp_clock_update_callback_t) cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE); + + bsp_clock_update_callback_args_t * p_callback_memory_checked = + (bsp_clock_update_callback_args_t *) cmse_check_address_range(p_callback_memory, + sizeof(bsp_clock_update_callback_args_t), + CMSE_AU_NONSECURE); + FSP_ASSERT(p_callback == p_callback_checked); + FSP_ASSERT(p_callback_memory == p_callback_memory_checked); + + r_bsp_clock_update_callback_set(p_callback_checked, p_callback_memory_checked); + + return FSP_SUCCESS; +} + + #endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_guard.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_guard.h new file mode 100644 index 0000000000..bb9617de61 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_guard.h @@ -0,0 +1,32 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_GUARD_H +#define BSP_GUARD_H + +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_io.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_io.c new file mode 100644 index 0000000000..b53d7b9805 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_io.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_io.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_io.h new file mode 100644 index 0000000000..418c753808 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_io.h @@ -0,0 +1,465 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write access to port pins. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_H +#define BSP_IO_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) +#define BSP_IO_PRV_8BIT_MASK (0xFF) +#define BSP_IO_PWPR_B0WI_OFFSET (7U) +#define BSP_IO_PWPR_PFSWE_OFFSET (6U) +#define BSP_IO_PFS_PDR_OUTPUT (4U) +#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Levels that can be set and read for individual pins */ +typedef enum e_bsp_io_level +{ + BSP_IO_LEVEL_LOW = 0, ///< Low + BSP_IO_LEVEL_HIGH ///< High +} bsp_io_level_t; + +/** Direction of individual pins */ +typedef enum e_bsp_io_dir +{ + BSP_IO_DIRECTION_INPUT = 0, ///< Input + BSP_IO_DIRECTION_OUTPUT ///< Output +} bsp_io_direction_t; + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x0000, ///< IO port 0 + BSP_IO_PORT_01 = 0x0100, ///< IO port 1 + BSP_IO_PORT_02 = 0x0200, ///< IO port 2 + BSP_IO_PORT_03 = 0x0300, ///< IO port 3 + BSP_IO_PORT_04 = 0x0400, ///< IO port 4 + BSP_IO_PORT_05 = 0x0500, ///< IO port 5 + BSP_IO_PORT_06 = 0x0600, ///< IO port 6 + BSP_IO_PORT_07 = 0x0700, ///< IO port 7 + BSP_IO_PORT_08 = 0x0800, ///< IO port 8 + BSP_IO_PORT_09 = 0x0900, ///< IO port 9 + BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 + BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 + BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 + BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 + BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 +} bsp_io_port_t; + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin_t +{ + BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 + BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 + BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 + BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 + BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 + BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 + BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 + BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 + BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 + BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 + BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 + BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 + BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 + BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 + + BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 + BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 + BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 + BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 + BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 + BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 + BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 + BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 + BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 + BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 + BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 + BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 + BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 + BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 + + BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 + BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 + BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 + BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 + BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 + BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 + BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 + BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 + BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 + BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 + BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 + BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 + BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 + BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 + + BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 + BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 + BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 + BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 + BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 + BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 + BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 + BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 + BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 + BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 + BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 + BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 + BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 + BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 + + BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 + BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 + BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 + BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 + BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 + BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 + BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 + BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 + BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 + BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 + BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 + BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 + BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 + BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 + + BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 + BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 + BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 + BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 + BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 + BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 + BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 + BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 + BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 + BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 + BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 + BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 + BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 + + BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 + BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 + BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 + BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 + BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 + BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 + BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 + BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 + BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 + BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 + BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 + BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 + BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 + BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 + + BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 + BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 + BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 + BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 + BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 + BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 + BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 + BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 + BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 + BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 + BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 + BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 + BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 + + BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 + BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 + BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 + BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 + BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 + BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 + BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 + BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 + BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 + BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 + BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 + BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 + BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 + + BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 + BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 + BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 + BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 + BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 + BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 + BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 + BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 + BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 + BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 + BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 + BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 + BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 + BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 + + BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 + BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 + BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 + BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 + BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 + BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 + BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 + BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 + BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 + BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 + BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 + BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 + BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 + BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 + + BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 + BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 + BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 + BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 + BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 + BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 + BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 + BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 + BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 + BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 + BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 + BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 + BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 + BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 + + BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 + BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 + BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 + BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 + BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 + BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 + BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 + BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 + BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 + BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 + BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 + BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 + BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 + BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 + BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 + BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 + + BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 + BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 + BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 + BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 + BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 + BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 + BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 + BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 + BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 + BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 + BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 + BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 + BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 + BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 + BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 + BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 + + BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 + BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 + BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 + BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 + BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 + BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 + BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 + BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 + BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 + BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 + BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 + BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 + BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 + BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 + BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 + BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 + BSP_IO_PORT_FF_PIN_FF = 0xFFFF, ///< Invalid IO port +} bsp_io_port_pin_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern volatile uint32_t g_protect_pfswe_counter; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Read the current input level of the pin. + * + * @param[in] pin The pin + * + * @retval Current input level + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) +{ + /* Read pin level. */ + return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; +} + +/*******************************************************************************************************************//** + * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS + * protection using R_BSP_PinAccessEnable() before calling this function. + * + * @param[in] pin The pin + * @param[in] level The level + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) +{ + /* Clear PMR, ASEL, ISEL and PODR bits. */ + uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; + pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK; + + /* Set output level and pin direction to output. */ + uint32_t lvl = ((uint32_t) level | pfs_bits); +#if (3U == BSP_FEATURE_IOPORT_VERSION) + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) (BSP_IO_PFS_PDR_OUTPUT | lvl); +#else + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl); +#endif +} + +/*******************************************************************************************************************//** + * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling + * this function. + * + * @param[in] pin The pin + * @param[in] cfg Configuration for the pin (PmnPFS register setting) + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) +{ + /* Configure a pin. */ +#if (3U == BSP_FEATURE_IOPORT_VERSION) + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) cfg; +#else + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg; +#endif +} + +/*******************************************************************************************************************//** + * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur + * via multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessEnable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** If this is first entry then allow writing of PFS. */ + if (0 == g_protect_pfswe_counter) + { + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) + R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #endif + } + + /** Increment the protect counter */ + g_protect_pfswe_counter++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via + * multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessDisable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** Is it safe to disable PFS register? */ + if (0 != g_protect_pfswe_counter) + { + /* Decrement the protect counter */ + g_protect_pfswe_counter--; + } + + /** Is it safe to disable writing of PFS? */ + if (0 == g_protect_pfswe_counter) + { + #if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS) + R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled + #endif + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/** @} (end addtogroup BSP_IO) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ipc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ipc.c new file mode 100644 index 0000000000..5e8a7da2b7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ipc.c @@ -0,0 +1,148 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#ifdef R_IPC + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* IPC0NMI is Core1 -> Core0, IPC1NMI is Core0 -> Core1 */ + #if (BSP_CFG_CPU_CORE == 0) + #define BSP_IPC_PRV_NMI_REG_SET IPC1NMI + #define BSP_IPC_PRV_NMI_REG_CLEAR IPC0NMI + #else + #define BSP_IPC_PRV_NMI_REG_SET IPC0NMI + #define BSP_IPC_PRV_NMI_REG_CLEAR IPC1NMI + #endif + + #define BSP_IPC_PRV_SEMAPHORE_CLEAR 1 + #define BSP_IPC_PRV_VALID_SEMAPHORE_MASK (0xFFFFU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +static void ipc_nmi_internal_callback(bsp_grp_irq_t irq); + +static bsp_ipc_nmi_cb_t gp_nmi_callback = NULL; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Attempt to take IPC semaphore + * + * @param[in] p_semaphore_handle Semaphore handle corresponding to IPCSEMn to use. + * + * @retval FSP_SUCCESS Semaphore successfully taken + * @retval FSP_ERR_IN_USE Semaphore already taken + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Specified semaphore doesn't exist on device + **********************************************************************************************************************/ +fsp_err_t R_BSP_IpcSemaphoreTake (bsp_ipc_semaphore_handle_t const * const p_semaphore_handle) +{ + #if BSP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_semaphore_handle); + FSP_ERROR_RETURN(BSP_IPC_PRV_VALID_SEMAPHORE_MASK & (1 << p_semaphore_handle->semaphore_num), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #endif + + FSP_ERROR_RETURN(!R_IPC->IPCSEM[p_semaphore_handle->semaphore_num], FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Give/clear the IPC semaphore + * + * @param[in] p_semaphore_handle Semaphore handle corresponding to IPCSEMn to use. + * + * @retval FSP_SUCCESS Semaphore successfully given + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Specified semaphore doesn't exist on device + **********************************************************************************************************************/ +fsp_err_t R_BSP_IpcSemaphoreGive (bsp_ipc_semaphore_handle_t const * const p_semaphore_handle) +{ + #if BSP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_semaphore_handle); + FSP_ERROR_RETURN(BSP_IPC_PRV_VALID_SEMAPHORE_MASK & (1 << p_semaphore_handle->semaphore_num), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #endif + + R_IPC->IPCSEM[p_semaphore_handle->semaphore_num] = BSP_IPC_PRV_SEMAPHORE_CLEAR; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable NMI for current core + * + * @param[in] p_callback Pointer to callback to use for NMI. + * + * @retval FSP_SUCCESS NMI request set + **********************************************************************************************************************/ +fsp_err_t R_BSP_IpcNmiEnable (bsp_ipc_nmi_cb_t p_callback) +{ + #if BSP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_callback); + #endif + + gp_nmi_callback = p_callback; + + /* Setup NMI callback */ + R_BSP_GroupIrqWrite(BSP_GRP_IRQ_IPC, ipc_nmi_internal_callback); + + /* Set IPCEN bit to enable NMI. NMIER bits cannot be cleared after reset, so no need to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_IPCEN_Msk; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set NMI request for the opposing core + * + * @retval FSP_SUCCESS NMI request set + **********************************************************************************************************************/ +fsp_err_t R_BSP_IpcNmiRequestSet (void) +{ + R_IPC->BSP_IPC_PRV_NMI_REG_SET.SET = 1; + + return FSP_SUCCESS; +} + +/** @} (end addtogroup BSP_MCU) */ + +static void ipc_nmi_internal_callback (bsp_grp_irq_t irq) +{ + if (BSP_GRP_IRQ_IPC == irq) + { + /* Clear NMI request */ + R_IPC->BSP_IPC_PRV_NMI_REG_CLEAR.CLR = 1; + + if (NULL != gp_nmi_callback) + { + /* Call user callback */ + gp_nmi_callback(); + } + } +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ipc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ipc.h new file mode 100644 index 0000000000..f243dfbe20 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ipc.h @@ -0,0 +1,60 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IPC_H +#define BSP_IPC_H + +#ifdef R_IPC + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Semaphore handle for IPC semaphores. */ +typedef struct st_bsp_ipc_semaphore_handle +{ + uint8_t semaphore_num; ///< Semaphore number, controls which IPCSEMn register is used. +} bsp_ipc_semaphore_handle_t; + +/** IPC NMI callback type. */ +typedef void (* bsp_ipc_nmi_cb_t)(void); + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +fsp_err_t R_BSP_IpcSemaphoreTake(bsp_ipc_semaphore_handle_t const * const p_semaphore_handle); +fsp_err_t R_BSP_IpcSemaphoreGive(bsp_ipc_semaphore_handle_t const * const p_semaphore_handle); +fsp_err_t R_BSP_IpcNmiRequestSet(void); +fsp_err_t R_BSP_IpcNmiEnable(bsp_ipc_nmi_cb_t p_callback); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_irq.c new file mode 100644 index 0000000000..eb75239165 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_irq.c @@ -0,0 +1,310 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** ELC event definitions. */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU) +#define BSP_PRV_BITS_PER_WORD (32) + +#if (BSP_CFG_CPU_CORE == 1) + #define BSP_EVENT_NUM_TO_INTSELR(x) (x >> 5) // Convert event number to INTSELR register number + #define BSP_EVENT_NUM_TO_INTSELR_MASK(x) (1 << (x % 32)) // Convert event number to INTSELR bit mask +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* This table is used to store the context in the ISR. */ +void * gp_renesas_isr_context[BSP_ICU_VECTOR_NUM_ENTRIES]; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if (BSP_CFG_CPU_CORE == 1) +BSP_CMSE_NONSECURE_ENTRY void bsp_prv_intselr_set(bsp_interrupt_event_t interrupt_event_link_select); + +#endif + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_NUM_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ +#if 0 == BSP_CFG_INLINE_IRQ_FUNCTIONS + #if BSP_FEATURE_ICU_HAS_IELSR + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit + * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqStatusClear (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_ICU->IELSR_b[irq].IR = 0U; + + /* Read back the IELSR register to ensure that the IR bit is cleared. + * See "Operations During an Interrupt" in the ICU section of the relevant hardware manual. */ + FSP_REGISTER_READ(R_ICU->IELSR[irq]); +} + + #endif + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqClearPending (IRQn_Type irq) +{ + #if BSP_FEATURE_ICU_HAS_IELSR + + /* Clear the IR bit in the selected IELSR register. */ + R_BSP_IrqStatusClear(irq); + + /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ + __DMB(); + #endif + + /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ to configure. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions + * every time a priority is configured in the NVIC. */ + #if (4U == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + #elif (33 == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + #elif (23 == __CORTEX_M) + NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); + #else + NVIC_SetPriority(irq, priority); + #endif + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the NVIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex + * Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions + * every time an interrupt is enabled in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + + __COMPILER_BARRIER(); + NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + __COMPILER_BARRIER(); +} + +/*******************************************************************************************************************//** + * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed + * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the ICU and NVIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the NVIC. + * + * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqDisable (IRQn_Type const irq) +{ + /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +#endif // 0 == BSP_CFG_INLINE_IRQ_FUNCTIONS + +/** @} (end addtogroup BSP_MCU) */ + +#if (BSP_CFG_CPU_CORE == 1) && !BSP_TZ_NONSECURE_BUILD + +/*******************************************************************************************************************//** + * INTSELR is a S-TYPE-6 register but it needs to be set based on interrupts that are used in each project. + * By making this into a NSC, INTSELR can be set from NS. + **********************************************************************************************************************/ +BSP_CMSE_NONSECURE_ENTRY void bsp_prv_intselr_set (bsp_interrupt_event_t interrupt_event_link_select) +{ + uint32_t inteslr_num_max = sizeof(R_ICU->INTSELR) / sizeof(R_ICU->INTSELR[0]); + + /* Calculate which INTSELRn to use */ + uint32_t intselr_num = BSP_EVENT_NUM_TO_INTSELR((uint32_t) interrupt_event_link_select); + + /* Only set if a valid INTSELRn */ + if (intselr_num < inteslr_num_max) + { + /* Set INTSELR for selected events. */ + uint32_t intselr = R_ICU->INTSELR[intselr_num]; + + intselr |= BSP_EVENT_NUM_TO_INTSELR_MASK((uint32_t) interrupt_event_link_select); + R_ICU->INTSELR[intselr_num] = intselr; + } +} + +#endif + +/*******************************************************************************************************************//** + * Using the vector table information section that has been built by the linker and placed into ROM in the + * .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts + * in the NVIC. + * + **********************************************************************************************************************/ +void bsp_irq_cfg (void) +{ +#if FSP_PRIV_TZ_USE_SECURE_REGS + #if (BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 0) + + /* On MCUs with this implementation of TrustZone, IRQ security attribution is set to secure by default. + * This means that flat projects do not need to set security attribution to secure. */ + #else + + /* Unprotect security registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + #if !BSP_TZ_SECURE_BUILD + + /* Set the DMAC channels to secure access. */ + #ifdef BSP_TZ_CFG_ICUSARC + R_CPSCU->ICUSARC = ~R_CPSCU_ICUSARC_SADMACn_Msk; + #endif + #endif + + /* Place all vectors in non-secure state unless they are used in the secure project. */ + uint32_t interrupt_security_state[BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD]; + memset(&interrupt_security_state, UINT8_MAX, sizeof(interrupt_security_state)); + + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_NUM_ENTRIES; i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + /* This is a secure vector. Clear the associated bit. */ + uint32_t index = i / BSP_PRV_BITS_PER_WORD; + uint32_t bit = i % BSP_PRV_BITS_PER_WORD; + interrupt_security_state[index] &= ~(1U << bit); + } + } + + /* The Secure Attribute managed within the ARM CPU NVIC must match the security attribution of IELSEn + * (Refer "ICUSARI : Interrupt Controller Unit Security Attribution Register I" description in the ICU section of the relevant hardware manual). */ + #if (BSP_CFG_CPU_CORE == 1) + uint32_t volatile * p_icusarg = &R_CPSCU->ICUSARJ; + #else + uint32_t volatile * p_icusarg = &R_CPSCU->ICUSARG; + #endif + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD; i++) + { + p_icusarg[i] = interrupt_security_state[i]; + NVIC->ITNS[i] = interrupt_security_state[i]; + } + + /* Protect security registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + #endif +#endif +#if BSP_FEATURE_ICU_HAS_IELSR + + /* Calculate the number of IELSR registers that need to be initialized. */ + uint32_t ielsr_count = BSP_ICU_VECTOR_MAX_ENTRIES - BSP_FEATURE_ICU_FIXED_IELSR_COUNT; + if (ielsr_count > BSP_ICU_VECTOR_NUM_ENTRIES) + { + ielsr_count = BSP_ICU_VECTOR_NUM_ENTRIES; + } + + for (uint32_t i = 0U; i < ielsr_count; i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; + + #if (BSP_CFG_CPU_CORE == 1) + bsp_prv_intselr_set(g_interrupt_event_link_select[i]); + #endif + } + } +#endif +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_irq.h new file mode 100644 index 0000000000..ec4a5b9678 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_irq.h @@ -0,0 +1,238 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IRQ_H +#define BSP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_NUM_ENTRIES]; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + gp_renesas_isr_context[irq] = p_context; +} + +/*******************************************************************************************************************//** + * @brief Finds the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @return ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + return gp_renesas_isr_context[irq]; +} + +#if BSP_CFG_INLINE_IRQ_FUNCTIONS + + #if BSP_FEATURE_ICU_HAS_IELSR + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit + * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_ICU->IELSR_b[irq].IR = 0U; + + /* Read back the IELSR register to ensure that the IR bit is cleared. + * See "Operations During an Interrupt" in the ICU section of the relevant hardware manual. */ + FSP_REGISTER_READ(R_ICU->IELSR[irq]); +} + + #endif + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) +{ + #if BSP_FEATURE_ICU_HAS_IELSR + + /* Clear the IR bit in the selected IELSR register. */ + R_BSP_IrqStatusClear(irq); + + /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */ + __DMB(); + #endif + + /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ to configure. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions + * every time a priority is configured in the NVIC. */ + #if (4U == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + #elif (33 == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); + #elif (23 == __CORTEX_M) + NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); + #else + NVIC_SetPriority(irq, priority); + #endif + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the NVIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex + * Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions + * every time an interrupt is enabled in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + + __COMPILER_BARRIER(); + NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + __COMPILER_BARRIER(); +} + +/*******************************************************************************************************************//** + * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed + * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the ICU and NVIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the NVIC. + * + * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) +{ + /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +#else + #if BSP_FEATURE_ICU_HAS_IELSR +void R_BSP_IrqStatusClear(IRQn_Type irq); + + #endif +void R_BSP_IrqClearPending(IRQn_Type irq); +void R_BSP_IrqCfg(IRQn_Type const irq, uint32_t priority, void * p_context); +void R_BSP_IrqEnableNoClear(IRQn_Type const irq); +void R_BSP_IrqEnable(IRQn_Type const irq); +void R_BSP_IrqDisable(IRQn_Type const irq); +void R_BSP_IrqCfgEnable(IRQn_Type const irq, uint32_t priority, void * p_context); + +#endif + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_macl.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_macl.c new file mode 100644 index 0000000000..045e84ba72 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_macl.c @@ -0,0 +1,2050 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_macl.h" + +#if BSP_FEATURE_MACL_SUPPORTED + #if __has_include("arm_math_types.h") + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + + #ifndef INDEX_MASK + +/* This used to be defined in CMSIS DSP. But they have added an undef of the macro in utils.h and therefore it is no longer + * in scope for the uses of this file. */ + #define INDEX_MASK 0x0000003F + #endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static inline void r_macl_wait_operation(void); + +static void r_macl_mul_q31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); + +static void r_macl_scale_q31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); + +static void r_macl_mat_mul_q31(const arm_matrix_instance_q31 * p_src_a, + const arm_matrix_instance_q31 * p_src_b, + arm_matrix_instance_q31 * p_dst); + +static void r_macl_mat_mul_acc_q31(const q31_t * p_in_a, + const q31_t * p_in_b, + q31_t * p_out, + uint16_t num_cols_a, + uint16_t num_cols_b); + +static void r_macl_mat_scale_q31(const arm_matrix_instance_q31 * p_src, + q31_t scale_fract, + int32_t shift, + arm_matrix_instance_q31 * p_dst); +static void r_macl_conv_q31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint8_t block_size); + +static uint32_t r_macl_recip_q31(q31_t in, q31_t * dst, const q31_t * p_recip_table); + +/*******************************************************************************************************************//** + * @addtogroup BSP_MACL + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Perform multiplication via MACL module. + * + * @param[in] p_src_a Pointer which point to data A. + * @param[in] p_src_b Pointer which point to data B. + * @param[out] p_dst Pointer to buffer which will hold the calculation result. + * @param[in] block_size Numbers of elements to be calculated. + **********************************************************************************************************************/ +void R_BSP_MaclMulQ31 (const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size) +{ + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + r_macl_mul_q31(p_src_a, p_src_b, p_dst, block_size); + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; +} + +/*******************************************************************************************************************//** + * Perform scaling a vector by multiplying scalar via MACL module. + * + * @param[in] p_src Pointer which point to a vector. + * @param[in] scale_fract Pointer to the scalar number. + * @param[in] shift Number of bits to shift the result by + * @param[out] p_dst Pointer to buffer which will hold the calculation result. + * @param[in] block_size Numbers of elements to be calculated. + **********************************************************************************************************************/ +void R_BSP_MaclScaleQ31 (const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size) +{ + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + r_macl_scale_q31(p_src, scale_fract, shift, p_dst, block_size); +} + +/*******************************************************************************************************************//** + * Perform Q31 matrix multiplication via MACL module. + * + * @param[in] p_src_a Points to the first input matrix structure A. + * @param[in] p_src_b Points to the second input matrix structure B. + * @param[out] p_dst Points to the buffer which hold output matrix structure. + **********************************************************************************************************************/ +void R_BSP_MaclMatMulQ31 (const arm_matrix_instance_q31 * p_src_a, + const arm_matrix_instance_q31 * p_src_b, + arm_matrix_instance_q31 * p_dst) +{ + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + r_macl_mat_mul_q31(p_src_a, p_src_b, p_dst); +} + +/*******************************************************************************************************************//** + * Perform Q31 matrix and vector multiplication via MACL module. + * + * @param[in] p_src_mat Points to the first input matrix structure. + * @param[in] p_vec Points to the input vector. + * @param[out] p_dst Points to the buffer which hold the output vector. + **********************************************************************************************************************/ +void R_BSP_MaclMatVecMulQ31 (const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst) +{ + uint16_t num_rows = p_src_mat->numRows; // Number of rows of input matrix + uint16_t num_cols = p_src_mat->numCols; // Number of columns of input matrix + const q31_t * p_src = p_src_mat->pData; // Input data matrix + const q31_t * p_in_vec = p_vec; // Input data vector + q31_t * p_out = p_dst; // Output data vector + uint16_t row = num_rows; // Loop counters + uint16_t num_cols_vec = 1; + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* Row loop of the matrix */ + do + { + /* Perform the multiply-accumulates a row in p_src with the input vector */ + r_macl_mat_mul_acc_q31(p_src, p_in_vec, p_out, num_cols, num_cols_vec); + + p_out++; + row--; + p_src += num_cols; + } while (row > 0U); +} + +/*******************************************************************************************************************//** + * Perform scaling a matrix by multiplying scalar via MACL module. + * + * @param[in] p_src Points to the vector. + * @param[in] scale_fract Points to the scalar number. + * @param[in] shift Number of bits to shift the result by + * @param[out] p_dst Points to the buffer which will hold the calculation result. + **********************************************************************************************************************/ +void R_BSP_MaclMatScaleQ31 (const arm_matrix_instance_q31 * p_src, + q31_t scale_fract, + int32_t shift, + arm_matrix_instance_q31 * p_dst) +{ + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + r_macl_mat_scale_q31(p_src, scale_fract, shift, p_dst); +} + +/*******************************************************************************************************************//** + * Perform the biquad cascade direct form I filter in Q31 via MACL module + * + * @param[in] p_biquad_csd_df1_inst Point to instance of the Q31 Biquad cascade structure + * @param[in] p_src Point to input sample to be filtered. + * @param[out] p_dst Point to buffer for storing filtered sample. + * @param[in] block_size Numbers of input sample. + **********************************************************************************************************************/ +void R_BSP_MaclBiquadCsdDf1Q31 (const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size) +{ + const q31_t * p_coeffs = p_biquad_csd_df1_inst->pCoeffs; // Coefficient pointer + q31_t * p_state = p_biquad_csd_df1_inst->pState; // State pointer + const q31_t * p_src_local = p_src; // Local pointer for p_src + q31_t * p_dst_local = p_dst; // Local pointer for p_dst + uint32_t stage = p_biquad_csd_df1_inst->numStages; // Loop counter + uint32_t sample; // Loop counter + uint32_t state_update_element; // Update state buffer + uint32_t src_ctrl; // Control the value of source + uint32_t sample_ctrl; // Control the value of sample + uint32_t coeffs_ctrl; // Control the value of coefficient + uint32_t shift = ((uint32_t) p_biquad_csd_df1_inst->postShift + 1U); // Shift to be applied to the output + uint32_t r_shift = BSP_MACL_32_BIT - shift; // Shift to be applied to the output + volatile uint64_t * p_result_in_q62 = (uint64_t *) &(R_MACL->MULR0.MULRL); // Assign to address of MULR0 + + state_update_element = 0U; + coeffs_ctrl = 0U; + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + while (stage > 0U) + { + sample = block_size; + src_ctrl = 0U; + sample_ctrl = 0U; + + /** + * y[n] = b0 * x[n] + b1 * x[n - 1] + b2 * x[n -2] + a1 * y[n - 1] + a2 * y[n - 2] + */ + while (sample > 0U) + { + /* Clean result reg */ + R_MACL->MULRCLR = 0U; + + /* Calculate b0.x[n] */ + R_MACL->MAC32S = (uint32_t) p_src_local[src_ctrl]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl]; + r_macl_wait_operation(); + + /* Calculate for b1.x[n-1] and a1.y[n-1] */ + if (sample_ctrl >= 1U) + { + /* b1 * x[n - 1] */ + R_MACL->MAC32S = (uint32_t) p_state[state_update_element]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl + 1U]; + r_macl_wait_operation(); + + /* a1 * y[n - 1] */ + R_MACL->MAC32S = (uint32_t) p_state[state_update_element + 2U]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl + 3U]; + r_macl_wait_operation(); + } + + /* Calculate for b2 * x[n - 2] and a2 * y[n - 2]*/ + if (sample_ctrl >= 2U) + { + /* b2 * x[n - 2] */ + R_MACL->MAC32S = (uint32_t) p_state[state_update_element + 1U]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl + 2U]; + r_macl_wait_operation(); + + /* a2 * y[n - 2] */ + R_MACL->MAC32S = (uint32_t) p_state[state_update_element + 3U]; + R_MACL->MULB0 = (uint32_t) p_coeffs[coeffs_ctrl + 4U]; + r_macl_wait_operation(); + } + + /* Update state buffer */ + p_state[state_update_element + 1U] = p_state[state_update_element]; // x[n - 2] = x[n - 1] + p_state[state_update_element] = p_src_local[src_ctrl]; // x[n - 1] = x[n] + + /* Shift and write result to buffer */ + *p_dst_local = (q31_t) (*p_result_in_q62 >> r_shift); + + /* Update state buffer */ + p_state[state_update_element + 3U] = p_state[state_update_element + 2U]; // y[n - 2] = y[n - 1] + p_state[state_update_element + 2U] = *p_dst_local; // Update value of y[n-1] + + sample--; + src_ctrl++; + sample_ctrl++; + + /* Check before update addr of p_dst to prevent segmentation fault */ + if (sample != 0U) + { + p_dst_local++; + } + } + + p_src_local = p_dst; + p_dst_local = p_dst; + state_update_element += 4U; + coeffs_ctrl += 5U; + stage--; + } +} + +/*******************************************************************************************************************//** + * Perform the convolution in Q31 via MACL module. + * + * @param[in] p_src_a Point to input source A + * @param[in] src_a_len Length of source A + * @param[in] p_src_b Point to input source B + * @param[in] src_b_len Length of source B + * @param[out] p_dst Point to result buffer + **********************************************************************************************************************/ +void R_BSP_MaclConvQ31 (const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst) +{ + uint8_t src_a_ctrl; // Control the value of source A + uint8_t src_b_ctrl; // Control the value of source B + uint8_t element_ctrl; // Control the value of element + uint32_t src_a_len_local; // Local length of source A + uint32_t src_b_len_local; // Local length of source B + const q31_t * p_data_a; // Input source A pointer + const q31_t * p_data_b; // Input source B pointer + q31_t * p_dst_local = p_dst; // Output pointer + + src_a_ctrl = 1U; + src_b_ctrl = 1U; + element_ctrl = 1U; + + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + /* The algorithm implementation is based on the lengths of the inputs. src B is always made to slide across src A. + * Therefore, length of B is always considered as shorter or equal to length of A */ + if (src_a_len >= src_b_len) + { + p_data_a = p_src_a; + p_data_b = p_src_b; + src_a_len_local = src_a_len; + src_b_len_local = src_b_len; + } + else + { + p_data_a = p_src_b; + p_data_b = p_src_a; + src_a_len_local = src_b_len; + src_b_len_local = src_a_len; + } + + /* Stage 1 */ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + while (src_b_ctrl < src_b_len_local) + { + /* Perform multiply-accumulate via MACL for convolution operation */ + r_macl_conv_q31(p_data_a, p_data_b, p_dst_local, element_ctrl); + + p_data_b++; + p_dst_local++; + element_ctrl++; + src_b_ctrl++; + src_a_ctrl++; + } + + /* Stage 2 */ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + while (src_a_ctrl <= src_a_len_local) + { + /* Perform multiply-accumulate via MACL for convolution operation */ + r_macl_conv_q31(p_data_a, p_data_b, p_dst_local, element_ctrl); + + p_data_a++; + p_dst_local++; + src_a_ctrl++; + } + + element_ctrl--; + + /* Stage 3 */ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + while (element_ctrl > 0U) + { + /* Perform multiply-accumulate via MACL for convolution operation */ + r_macl_conv_q31(p_data_a, p_data_b, p_dst_local, element_ctrl); + + p_data_a++; + element_ctrl--; + p_dst_local++; + } + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; +} + +/*******************************************************************************************************************//** + * Perform the partial convolution in Q31 via MACL module. + * + * @param[in] p_src_a Point to input source A + * @param[in] src_a_len Length of source A + * @param[in] p_src_b Point to input source B + * @param[in] src_b_len Length of source B + * @param[out] p_dst Point to result buffer + * @param[in] first_idx The first output sample to start with + * @param[in] num_points The number of output points to be computed + * + * @retval ARM_MATH_SUCCESS Operation successful + * @retval ARM_MATH_ARGUMENT_ERROR Requested compute points is bigger than result size + **********************************************************************************************************************/ +arm_status R_BSP_MaclConvPartialQ31 (const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst, + uint32_t first_idx, + uint32_t num_points) +{ + /* Status of Partial convolution */ + arm_status status; + + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + /* Check for range of output samples to be calculated */ + if ((first_idx + num_points) > (src_a_len + (src_b_len - 1U))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (uint32_t i = first_idx; i <= (first_idx + num_points - 1U); i++) + { + /* Clear the Result registers. */ + R_MACL->MULRCLR = 0U; + + /* Loop to perform MAC operations according to convolution equation */ + for (uint32_t j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < src_b_len) && (j < src_a_len)) + { + /* z[i] += x[i-j] * y[j] */ + R_MACL->MAC32S = (uint32_t) (p_src_a[j]); + R_MACL->MULB0 = (uint32_t) (p_src_b[i - j]); + r_macl_wait_operation(); + } + } + + /* Store the output in the destination buffer */ + p_dst[i] = (q31_t) R_MACL->MULR0.MULRH; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + return status; +} + +/*******************************************************************************************************************//** + * Perform the Q31 FIR Decimate Q31 via MACL module. + * + * @param[in] p_fir_decimate_ins_q31 Pointer which point to an instance of the Q31 FIR Decimate structure. + * @param[in] p_src Pointer which point to the input vector. + * @param[out] p_dst Pointer to buffer which hold the output vector. + * @param[in] block_size Numbers of samples to be calculated. + **********************************************************************************************************************/ +void R_BSP_MaclFirDecimateQ31 (const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size) +{ + q31_t * p_state = p_fir_decimate_ins_q31->pState; // State pointer + const q31_t * p_coeffs = p_fir_decimate_ins_q31->pCoeffs; // Coefficient pointer + q31_t * p_state_cur; // Points to the current sample of the state + q31_t * p_state_buffer; // Temporary pointer for state buffer + const q31_t * p_coeff_buffer; // Temporary pointer for coefficient buffer + uint32_t num_taps = p_fir_decimate_ins_q31->numTaps; // Number of filter coefficients in the filter + uint32_t num_of_decimate_factor; // Number of decimation factor + uint32_t tap_cnt; // Loop counters + uint32_t blk_cnt; // Loop counters + + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + /* p_fir_decimate_ins_q31->pState buffer contains previous frame (num_taps - 1) samples */ + /* p_state_cur points to the location where the new input data should be written */ + p_state_cur = p_fir_decimate_ins_q31->pState + (num_taps - 1U); + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size / p_fir_decimate_ins_q31->M; + + while (blk_cnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + num_of_decimate_factor = p_fir_decimate_ins_q31->M; + + do + { + *p_state_cur++ = *p_src++; + --num_of_decimate_factor; + } while (num_of_decimate_factor > 0); + + /* Set accumulator to zero */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize state pointer */ + p_state_buffer = p_state; + + /* Initialize coeff pointer */ + p_coeff_buffer = p_coeffs; + + /* Initialize tap_cnt with number of taps */ + tap_cnt = num_taps; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + /* Write state variable to register A */ + R_MACL->MAC32S = (uint32_t) *p_state_buffer++; + + /* Write coeficients to register B*/ + R_MACL->MULB0 = (uint32_t) *p_coeff_buffer++; + r_macl_wait_operation(); + + /* Decrement loop counter */ + tap_cnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + p_state = p_state + p_fir_decimate_ins_q31->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *p_dst++ = (q31_t) (R_MACL->MULR0.MULRH); + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Processing is complete. + * Now copy the last num_taps - 1 samples to the satrt of the state buffer. + * This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + p_state_cur = p_fir_decimate_ins_q31->pState; + + /* Initialize tap_cnt with number of taps */ + tap_cnt = (num_taps - 1U); + + /* Copy data */ + while (tap_cnt > 0U) + { + *p_state_cur++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } + + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; +} + +/*******************************************************************************************************************//** + * Perform the Q31 FIR interpolator via MACL module. + * + * @param[in] p_fir_interpolate_ins_q31 Pointer which point to an instance of the Q31 FIR interpolator structure. + * @param[in] p_src Pointer which point to the input vector. + * @param[out] p_dst Pointer to buffer which hold the output vector. + * @param[in] block_size Numbers of samples to be calculated. + **********************************************************************************************************************/ +void R_BSP_MaclFirInterpolateQ31 (const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size) +{ + /* Disable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + q31_t * p_state = p_fir_interpolate_ins_q31->pState; // State pointer + const q31_t * p_coeffs = p_fir_interpolate_ins_q31->pCoeffs; // Coefficient pointer + q31_t * p_state_cur; // Points to the current sample of the state + q31_t * p_state_tmp; // Temporary pointer for state buffer + const q31_t * p_coef_tmp; // Temporary pointer for coefficient buffer + uint32_t coef_idx; // Index of coefficient + uint32_t factor_cnt; // Loop counters + uint32_t blk_cnt; // Loop counters + uint32_t tap_cnt; // Loop counters + uint32_t phase_len = p_fir_interpolate_ins_q31->phaseLength; // Length of each polyphase filter component + volatile uint64_t * p_result_r0 = (uint64_t *) &(R_MACL->MULR0.MULRL); // Assign to address of MULR0 + + /* p_state_cur points to the location where the new input data should be written */ + p_state_cur = p_fir_interpolate_ins_q31->pState + (phase_len - 1U); + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Copy new input sample into the state buffer */ + *p_state_cur++ = *p_src++; + + /* Address modifier index of coefficient buffer */ + coef_idx = 1U; + + /* Loop over the Interpolation factor. */ + factor_cnt = p_fir_interpolate_ins_q31->L; + + while (factor_cnt > 0U) + { + /* Clear registers */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize state pointer */ + p_state_tmp = p_state; + + /* Initialize coefficient pointer */ + p_coef_tmp = p_coeffs + (p_fir_interpolate_ins_q31->L - coef_idx); + + /* Initialize tap_cnt with number of samples */ + tap_cnt = phase_len; + + while (tap_cnt > 0U) + { + R_MACL->MAC32S = (uint32_t) (*p_state_tmp); + R_MACL->MULB0 = (uint32_t) (*p_coef_tmp); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + tap_cnt--; + p_state_tmp++; + p_coef_tmp += p_fir_interpolate_ins_q31->L; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *p_dst++ = (q31_t) (*p_result_r0 >> BSP_MACL_SHIFT_31_BIT); + + /* Increment the address modifier index of coefficient buffer */ + coef_idx++; + + /* Decrement the loop counter */ + factor_cnt--; + } + + /* Advance the state pointer by 1 to process the next group of interpolation factor number samples */ + p_state = p_state + 1; + + /* Decrement the loop counter */ + blk_cnt--; + } + + /* Points to the start of the state buffer */ + p_state_cur = p_fir_interpolate_ins_q31->pState; + + /* Initialize tap_cnt with number of samples */ + tap_cnt = (phase_len - 1U); + + /* Copy data */ + while (tap_cnt > 0U) + { + *p_state_cur++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } +} + +/*******************************************************************************************************************//** + * Perform the Q31 Correlate via MACL module. + * + * @param[in] p_src_a Point to the first input sequence. + * @param[in] src_a_len Length of the first input sequence. + * @param[in] p_src_b Point to the second input sequence. + * @param[in] src_b_len Length of the second input sequence. + * @param[out] p_dst Points to the location where the output result is written. + * Length 2 * max(src_a_len, src_b_len) - 1. + **********************************************************************************************************************/ +void R_BSP_MaclCorrelateQ31 (const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst) +{ + const q31_t * p_in1; // InputA pointer + const q31_t * p_in2; // InputB pointer + q31_t * p_out = p_dst; // Output pointer + const q31_t * p_in_a_buf; // Intermediate inputA pointer + const q31_t * p_in_b_buf; // Intermediate inputB pointer + const q31_t * p_src1; // Intermediate pointers + uint32_t block_size1; // Loop counters + uint32_t block_size2; // Loop counters + uint32_t block_size3; // Loop counters + uint32_t len_diff_cnt; // Number of output samples + uint32_t cal_cnt; // Loop counters + uint32_t count; // Loop counters + int32_t inc = 1; // Destination address modifier + + /* Enable Fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + /* If src_a_len > src_b_len, + * (src_a_len - src_b_len) zeroes has to included in the starting of the output buffer */ + + /* If src_a_len < src_b_len, + * (src_b_len - src_a_len) zeroes has to included in the ending of the output buffer */ + if (src_a_len >= src_b_len) + { + /* Initialization of inputA pointer */ + p_in1 = p_src_a; + + /* Initialization of inputB pointer */ + p_in2 = p_src_b; + + /* When src_a_len > src_b_len, zero padding is done to srcB + * to make their lengths equal. + * Instead, (src_a_len - src_b_len) + * number of output samples are made zero */ + len_diff_cnt = src_a_len - src_b_len; + + /* Updating the pointer position to non zero value */ + p_out += len_diff_cnt; + } + else + { + /* Initialization of inputA pointer */ + p_in1 = p_src_b; + + /* Initialization of inputB pointer */ + p_in2 = p_src_a; + + /* src_b_len is always considered as shorter or equal to src_a_len */ + len_diff_cnt = src_b_len; + src_b_len = src_a_len; + src_a_len = len_diff_cnt; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + p_out = p_dst + ((src_a_len + src_b_len) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, src_b_len number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. + * The algorithm is implemented in three stages. + * The loop counters of each stage is initiated here. */ + block_size1 = src_b_len - 1U; + block_size2 = src_a_len - (src_b_len - 1U); + block_size3 = block_size1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[src_b_len - 1] + * sum = x[0] * y[src_b_len - 2] + x[1] * y[src_b_len - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[src_b_len - 1] * y[src_b_len - 1] + *//* In this stage the MAC operations are increased by 1 for every iteration. + * The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + p_in_a_buf = p_in1; + + /* Working pointer of inputB */ + p_src1 = p_in2 + (src_b_len - 1U); + p_in_b_buf = p_src1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (block_size1 > 0U) + { + /* Accumulator is made zero for every iteration */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize cal_cnt with number of samples */ + cal_cnt = count; + + while (cal_cnt > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[src_b_len - 1] */ + R_MACL->MAC32S = (uint32_t) *p_in_a_buf++; + R_MACL->MULB0 = (uint32_t) *p_in_b_buf++; + r_macl_wait_operation(); + + /* Decrement loop counter */ + cal_cnt--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *p_out = (q31_t) (R_MACL->MULR0.MULRH); + + /* Destination pointer is updated according to the address modifier, inc */ + p_out += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + p_in_b_buf = p_src1 - count; + p_in_a_buf = p_in1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + block_size1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[src_b_len-1] * y[src_b_len-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[src_b_len] * y[src_b_len-1] + * .... + * sum = x[src_a_len-src_b_len-2] * y[0] + x[src_a_len-src_b_len-1] * y[1] +...+ x[src_a_len-1] * y[src_b_len-1] + *//* Working pointer of inputA */ + p_in_a_buf = p_in1; + + /* Working pointer of inputB */ + p_in_b_buf = p_in2; + + /* count is index by which the pointer p_in1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on src_b_len as in this stage src_b_len number of MACS are performed. */ + + while (block_size2 > 0U) + { + /* Accumulator is made zero for every iteration */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize cal_cnt with number of samples */ + cal_cnt = src_b_len; + + while (cal_cnt > 0U) + { + /* Perform the multiply-accumulate */ + R_MACL->MAC32S = (uint32_t) *p_in_a_buf++; + R_MACL->MULB0 = (uint32_t) *p_in_b_buf++; + r_macl_wait_operation(); + + /* Decrement the loop counter */ + cal_cnt--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *p_out = (q31_t) (R_MACL->MULR0.MULRH); + + /* Destination pointer is updated according to the address modifier, inc */ + p_out += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + p_in_a_buf = p_in1 + count; + p_in_b_buf = p_in2; + + /* Decrement loop counter */ + block_size2--; + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[src_a_len-src_b_len+1] * y[0] + x[src_a_len-src_b_len+2] * y[1] +...+ x[src_a_len-1] * y[src_b_len-1] + * sum += x[src_a_len-src_b_len+2] * y[0] + x[src_a_len-src_b_len+3] * y[1] +...+ x[src_a_len-1] * y[src_b_len-1] + * .... + * sum += x[src_a_len-2] * y[0] + x[src_a_len-1] * y[1] + * sum += x[src_a_len-1] * y[0] + *//* In this stage the MAC operations are decreased by 1 for every iteration. + * The count variable holds the number of MAC operations performed */ + count = src_b_len - 1U; + + /* Working pointer of inputA */ + p_src1 = p_in1 + (src_a_len - (src_b_len - 1U)); + p_in_a_buf = p_src1; + + /* Working pointer of inputB */ + p_in_b_buf = p_in2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (block_size3 > 0U) + { + /* Accumulator is made zero for every iteration */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize cal_cnt with number of samples */ + cal_cnt = count; + + while (cal_cnt > 0U) + { + /* Perform the multiply-accumulate */ + R_MACL->MAC32S = (uint32_t) *p_in_a_buf++; + R_MACL->MULB0 = (uint32_t) *p_in_b_buf++; + r_macl_wait_operation(); + + /* Decrement loop counter */ + cal_cnt--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *p_out = (q31_t) (R_MACL->MULR0.MULRH); + + /* Destination pointer is updated according to the address modifier, inc */ + p_out += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + p_in_a_buf = ++p_src1; + p_in_b_buf = p_in2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + block_size3--; + } + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; +} + +/*******************************************************************************************************************//** + * Perform the Q31 FIR Sparse filter via MACL module. + * + * @note The number of p_fir_sparse_ins_q31->numTaps must be greater than or equal to 2 + * + * @param[in] p_fir_sparse_ins_q31 points to an instance of the Q31 sparse FIR structure + * @param[in] p_src points to the block of input data + * @param[out] p_dst points to the block of output data + * @param[in] p_scratch_in points to a temporary buffer of size blockSize + * @param[in] block_size number of input samples to process + **********************************************************************************************************************/ +void R_BSP_MaclFirSparseQ31 (arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + q31_t * p_scratch_in, + uint32_t block_size) +{ + q31_t * p_state = p_fir_sparse_ins_q31->pState; + const q31_t * p_coeffs = p_fir_sparse_ins_q31->pCoeffs; + q31_t * p_scratch_tmp; + q31_t * p_state_tmp = p_state; + q31_t * p_scratch_in_tmp = p_scratch_in; + q31_t * p_out; + int32_t * p_tap_delay = p_fir_sparse_ins_q31->pTapDelay; + uint32_t delay_size = p_fir_sparse_ins_q31->maxDelay + block_size; + uint16_t num_taps = p_fir_sparse_ins_q31->numTaps; + int32_t read_index; + uint32_t tap_cnt; + uint32_t blk_cnt; + q31_t coeff = *p_coeffs++; + q31_t in; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* block_size of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) p_state_tmp, (int32_t) delay_size, &p_fir_sparse_ins_q31->stateIndex, 1, + (int32_t *) p_src, 1, block_size); + + /* Read Index, from where the state buffer should be read, is calculated. */ + read_index = (int32_t) (p_fir_sparse_ins_q31->stateIndex - block_size) - *p_tap_delay++; + + /* Wraparound of read_index */ + if (read_index < 0) + { + read_index += (int32_t) delay_size; + } + + /* Working pointer for state buffer is updated */ + p_state_tmp = p_state; + + /* block_size samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) p_state_tmp, (int32_t) delay_size, &read_index, 1, (int32_t *) p_scratch_in_tmp, + (int32_t *) p_scratch_in_tmp, (int32_t) block_size, 1, block_size); + + /* Working pointer for the scratch buffer of state values */ + p_scratch_tmp = p_scratch_in_tmp; + + /* Working pointer for scratch buffer of output values */ + p_out = p_dst; + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + R_MACL->MUL32S = (uint32_t) *p_scratch_tmp++; + R_MACL->MULB0 = (uint32_t) coeff; + r_macl_wait_operation(); + *p_out++ = (q31_t) R_MACL->MULR0.MULRH; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *p_coeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + read_index = (int32_t) (p_fir_sparse_ins_q31->stateIndex - block_size) - *p_tap_delay++; + + /* Wraparound of read_index */ + if (read_index < 0) + { + read_index += (int32_t) delay_size; + } + + /* Loop over the number of taps. */ + tap_cnt = (uint32_t) num_taps - 2U; + + while (tap_cnt > 0U) + { + /* Working pointer for state buffer is updated */ + p_state_tmp = p_state; + + /* block_size samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) p_state_tmp, + (int32_t) delay_size, + &read_index, + 1, + (int32_t *) p_scratch_in_tmp, + (int32_t *) p_scratch_in_tmp, + (int32_t) block_size, + 1, + block_size); + + /* Working pointer for the scratch buffer of state values */ + p_scratch_tmp = p_scratch_in_tmp; + + /* Working pointer for scratch buffer of output values */ + p_out = p_dst; + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Perform Multiply-Accumulate */ + /* Initialize out value*/ + R_MACL->MULR0.MULRH = (uint32_t) *p_out; + R_MACL->MULR0.MULRL = 0x0; + + /* Assign p_scratch_tmp value to register*/ + R_MACL->MAC32S = (uint32_t) *p_scratch_tmp++; + + /* Assign coeff value to register. */ + R_MACL->MULB0 = (uint32_t) coeff; + r_macl_wait_operation(); + + /* Read the result in Q31*/ + *p_out++ = (q31_t) R_MACL->MULR0.MULRH; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *p_coeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + read_index = (int32_t) (p_fir_sparse_ins_q31->stateIndex - block_size) - *p_tap_delay++; + + /* Wraparound of read_index */ + if (read_index < 0) + { + read_index += (int32_t) delay_size; + } + + /* Decrement tap loop counter */ + tap_cnt--; + } + + /* Compute last tap without the final read of p_tap_delay */ + + /* Working pointer for state buffer is updated */ + p_state_tmp = p_state; + + /* block_size samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) p_state_tmp, (int32_t) delay_size, &read_index, 1, (int32_t *) p_scratch_in_tmp, + (int32_t *) p_scratch_in_tmp, (int32_t) block_size, 1, block_size); + + /* Working pointer for the scratch buffer of state values */ + p_scratch_tmp = p_scratch_in_tmp; + + /* Working pointer for scratch buffer of output values */ + p_out = p_dst; + + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Perform Multiply-Accumulate */ + /* Initialize out value*/ + R_MACL->MULR0.MULRH = (uint32_t) *p_out; + R_MACL->MULR0.MULRL = 0x0; + + /* Assign p_scratch_tmp value to register*/ + R_MACL->MAC32S = (uint32_t) *p_scratch_tmp++; + + /* Assign coeff value to register. */ + R_MACL->MULB0 = (uint32_t) coeff; + r_macl_wait_operation(); + + /* Read the result in Q31*/ + *p_out++ = (q31_t) R_MACL->MULR0.MULRH; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Working output pointer is updated */ + p_out = p_dst; + + /* Output is converted into 1.31 format. */ + /* Initialize blk_cnt with number of samples */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + in = *p_out << BSP_MACL_SHIFT_1_BIT; + *p_out++ = in; + + /* Decrement loop counter */ + blk_cnt--; + } +} + +/*******************************************************************************************************************//** + * Perform the Q31 normalized LMS filter via MACL module. + * @param[in] p_lms_norm_ins_q31 points to an instance of the Q31 normalized LMS filter structure + * @param[in] p_src points to the block of input data + * @param[in] p_ref points to the block of reference data + * @param[out] p_out points to the block of output data + * @param[out] p_err points to the block of error data + * @param[in] block_size number of samples to process + **********************************************************************************************************************/ +void R_BSP_MaclLmsNormQ31 (arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, + const q31_t * p_src, + q31_t * p_ref, + q31_t * p_out, + q31_t * p_err, + uint32_t block_size) +{ + q31_t * p_state = p_lms_norm_ins_q31->pState; // State pointer + q31_t * p_coeffs = p_lms_norm_ins_q31->pCoeffs; // Coefficient pointer + q31_t * p_state_curnt; // Points to the current sample of the state + q31_t * p_state_buf; // Temporary pointers for state + q31_t * p_coeffs_buf; // Coefficient buffers + q31_t mu = p_lms_norm_ins_q31->mu; // Adaptive factor + uint32_t num_taps = p_lms_norm_ins_q31->numTaps; // Number of filter coefficients in the filter + uint32_t tap_cnt; // Loop counters + uint32_t blk_cnt; // Loop counters + q31_t acc; // Accumulator + q63_t energy; // Energy of the input + q31_t err_data; // Error data sample + q31_t weight_factor; // Weight factor and state + q31_t data_in; + q31_t x0; // Temporary variable to hold input sample + q31_t error_x_mu; // Temporary variable to store error + q31_t one_by_energy; // Temporary variables to store mu product and reciprocal of energy + q31_t post_shift; // Post shift to be applied to weight after reciprocal calculation + q31_t acc_l; // Low accumulator + q31_t acc_h; // High accumulator + uint32_t u_shift = ((uint32_t) p_lms_norm_ins_q31->postShift + 1U); + uint32_t l_shift = BSP_MACL_32_BIT - u_shift; // Shift to be applied to the output + q63_t result_temp; // Temporary variable to read result register + volatile uint64_t * p_result_r4 = (uint64_t *) &(R_MACL->MULR4.MULRL); // Assign to address of MULR4 + uint32_t tmp_check; // Check overflow/underflow value + q63_t mul_tmp = 0; + energy = p_lms_norm_ins_q31->energy; // Frame energy + x0 = p_lms_norm_ins_q31->x0; // Input sample + + /* p_lms_norm_ins_q31->pState points to buffer which contains previous frame (num_taps - 1) samples */ + /* p_state_curnt points to the location where the new input data should be written */ + p_state_curnt = &(p_lms_norm_ins_q31->pState[(num_taps - 1U)]); + + /* Initialise loop count */ + blk_cnt = block_size; + + /* Clear the Result registers. */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + while (blk_cnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *p_state_curnt++ = *p_src; + + /* Initialize p_state pointer */ + p_state_buf = p_state; + + /* Initialize coefficient pointer */ + p_coeffs_buf = p_coeffs; + + /* Read the sample from input buffer */ + data_in = *p_src++; + + /* Update the energy calculation */ + R_MACL->MUL32S = (uint32_t) x0; + R_MACL->MULB1 = (uint32_t) x0; + r_macl_wait_operation(); + mul_tmp = (q63_t) R_MACL->MULR1.MULRH << BSP_MACL_SHIFT_32_BIT; + mul_tmp |= R_MACL->MULR1.MULRL; + energy = (energy << BSP_MACL_SHIFT_32_BIT) - (mul_tmp << 1); + R_MACL->MUL32S = (uint32_t) data_in; + R_MACL->MULB1 = (uint32_t) data_in; + r_macl_wait_operation(); + mul_tmp = (q63_t) R_MACL->MULR1.MULRH << BSP_MACL_SHIFT_32_BIT; + mul_tmp |= R_MACL->MULR1.MULRL; + + energy = (energy + (mul_tmp << 1)) >> BSP_MACL_SHIFT_32_BIT; + + /* Set the accumulator to zero */ + R_MACL->MULR0.MULRH = BSP_MACL_CLEAR_MULR_REG; + R_MACL->MULR0.MULRL = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize tap_cnt with number of samples */ + tap_cnt = num_taps; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + R_MACL->MAC32S = (uint32_t) *p_state_buf++; + R_MACL->MULB0 = (uint32_t) *p_coeffs_buf++; + r_macl_wait_operation(); + + /* Decrement the loop counter */ + tap_cnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = (q31_t) (R_MACL->MULR0.MULRL >> l_shift); + + /* Calc upper part of acc */ + acc_h = (q31_t) R_MACL->MULR0.MULRH << u_shift; + + acc = acc_l | acc_h; + + /* Store the result from accumulator into the destination buffer. */ + *p_out++ = acc; + + /* Compute and store error */ + err_data = *p_ref++ - acc; + *p_err++ = err_data; + + /* Calculates the reciprocal of energy */ + post_shift = (q31_t) r_macl_recip_q31((q31_t) energy + DELTA_Q31, + &one_by_energy, + &p_lms_norm_ins_q31->recipTable[0]); + + /* Calculation of product of (e * mu) */ + /* Enable Fixed Point Mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + R_MACL->MUL32S = (uint32_t) err_data; + R_MACL->MULB4 = (uint32_t) mu; + r_macl_wait_operation(); + error_x_mu = (q31_t) R_MACL->MULR4.MULRH; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* Weighting factor for the normalized version */ + R_MACL->MUL32S = (uint32_t) error_x_mu; + R_MACL->MULB4 = (uint32_t) one_by_energy; + r_macl_wait_operation(); + result_temp = (q63_t) *p_result_r4; + weight_factor = clip_q63_to_q31(result_temp >> (31 - post_shift)); + + /* Initialize p_state pointer */ + p_state_buf = p_state; + + /* Initialize coefficient pointer */ + p_coeffs_buf = p_coeffs; + + /* Initialize tap_cnt with number of samples */ + tap_cnt = num_taps; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + R_MACL->MULR5.MULRH = (uint32_t) (*p_coeffs_buf >> BSP_MACL_SHIFT_1_BIT); + R_MACL->MULR5.MULRL = (uint32_t) *p_coeffs_buf << BSP_MACL_SHIFT_31_BIT; + R_MACL->MAC32S = (uint32_t) weight_factor; + R_MACL->MULB5 = (uint32_t) *p_state_buf++; + r_macl_wait_operation(); + + tmp_check = (R_MACL->MULR5.MULRH >> BSP_MACL_SHIFT_30_BIT); + + /* Check overflow/underflow coefficient value */ + if (BSP_MACL_OVERFLOW_VALUE == tmp_check) + { + *p_coeffs_buf = (q31_t) BSP_MACL_Q31_MAX_VALUE; + } + else if (BSP_MACL_UNDERFLOW_VALUE == tmp_check) + { + *p_coeffs_buf = (q31_t) BSP_MACL_Q31_MIN_VALUE; + } + else + { + /* Enable fixed point mode. */ + R_MACL->MULC |= (uint8_t) R_MACL_MULC_MULFRAC_Msk; + + *p_coeffs_buf = (q31_t) R_MACL->MULR5.MULRH; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + } + + /* Increment the coefficient buffer */ + p_coeffs_buf++; + + /* Decrement loop counter */ + tap_cnt--; + } + + /* Read the sample from state buffer */ + x0 = *p_state; + + /* Advance state pointer by 1 for the next sample */ + p_state = p_state + 1; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Save energy and x0 values for the next frame */ + p_lms_norm_ins_q31->energy = (q31_t) energy; + p_lms_norm_ins_q31->x0 = x0; + + /* Processing is complete. + * Now copy the last num_taps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. */ + + /* Points to the start of the p_state buffer */ + p_state_curnt = p_lms_norm_ins_q31->pState; + + /* Initialize tap_cnt with number of samples */ + tap_cnt = (num_taps - 1U); + + while (tap_cnt > 0U) + { + *p_state_curnt++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } +} + +/*******************************************************************************************************************//** + * Perform the Q31 LMS filter via MACL module. + * @param[in] p_lms_ins_q31 points to an instance of the Q31 normalized LMS filter structure + * @param[in] p_src points to the block of input data + * @param[in] p_ref points to the block of reference data + * @param[out] p_out points to the block of output data + * @param[out] p_err points to the block of error data + * @param[in] block_size number of samples to process + **********************************************************************************************************************/ +void R_BSP_MaclLmsQ31 (const arm_lms_instance_q31 * p_lms_ins_q31, + const q31_t * p_src, + q31_t * p_ref, + q31_t * p_out, + q31_t * p_err, + uint32_t block_size) +{ + q31_t * p_state = p_lms_ins_q31->pState; // State pointer + q31_t * p_coeffs = p_lms_ins_q31->pCoeffs; // Coefficient pointer + q31_t * p_state_curnt; // Points to the current sample of the state + q31_t * p_state_buf; // Temporary pointers for state + q31_t * p_coeffs_buf; // Coefficient buffers + q31_t mu = p_lms_ins_q31->mu; // Adaptive factor + uint32_t num_taps = p_lms_ins_q31->numTaps; // Number of filter coefficients in the filter + uint32_t tap_cnt; // Loop counters + uint32_t blk_cnt; // Loop counters + q63_t acc; // Accumulator + q31_t err_data = 0; // Error data sample + q31_t alpha; // Intermediate constant for taps update + q31_t acc_l; // Low accumulator + q31_t acc_h; // High accumulator + uint32_t u_shift = (p_lms_ins_q31->postShift + 1); + uint32_t l_shift = BSP_MACL_32_BIT - u_shift; // Shift to be applied to the output + uint32_t tmp_check; // Check overflow/underflow value + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* p_lms_ins_q31->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + p_state_curnt = &(p_lms_ins_q31->pState[(num_taps - 1U)]); + + /* initialise loop count */ + blk_cnt = block_size; + + while (blk_cnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *p_state_curnt++ = *p_src++; + + /* Initialize pState pointer */ + p_state_buf = p_state; + + /* Initialize coefficient pointer */ + p_coeffs_buf = p_coeffs; + + /* Set the accumulator to zero */ + R_MACL->MULRCLR = BSP_MACL_CLEAR_MULR_REG; + + /* Initialize tapCnt with number of samples */ + tap_cnt = num_taps; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + + R_MACL->MAC32S = (uint32_t) *p_state_buf++; + R_MACL->MULB0 = (uint32_t) *p_coeffs_buf++; + r_macl_wait_operation(); + + /* Decrement the loop counter */ + tap_cnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = (q31_t) (R_MACL->MULR0.MULRL >> l_shift); + + /* Calc upper part of acc */ + acc_h = (q31_t) R_MACL->MULR0.MULRH << u_shift; + + acc = acc_l | acc_h; + + /* Store the result from accumulator into the destination buffer. */ + *p_out++ = (q31_t) acc; + + /* Compute and store error */ + err_data = *p_ref++ - (q31_t) acc; + *p_err++ = err_data; + + /* Compute alpha i.e. intermediate constant for taps update */ + /* Enable Fixed Point Mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + R_MACL->MUL32S = (uint32_t) err_data; + R_MACL->MULB4 = (uint32_t) mu; + r_macl_wait_operation(); + alpha = (q31_t) R_MACL->MULR4.MULRH; + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + p_state_buf = p_state++; + + /* Initialize coefficient pointer */ + p_coeffs_buf = p_coeffs; + + /* Initialize tapCnt with number of samples */ + tap_cnt = num_taps; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + while (tap_cnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + * pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); */ + R_MACL->MULR5.MULRH = (uint32_t) (*p_coeffs_buf >> BSP_MACL_SHIFT_1_BIT); + R_MACL->MULR5.MULRL = (uint32_t) *p_coeffs_buf << BSP_MACL_SHIFT_31_BIT; + + R_MACL->MAC32S = (uint32_t) alpha; + R_MACL->MULB5 = (uint32_t) *p_state_buf++; + r_macl_wait_operation(); + + tmp_check = (R_MACL->MULR5.MULRH >> BSP_MACL_SHIFT_30_BIT); + + /* Check overflow/underflow coefficient value */ + if (BSP_MACL_OVERFLOW_VALUE == tmp_check) + { + *p_coeffs_buf = (q31_t) BSP_MACL_Q31_MAX_VALUE; + } + else if (BSP_MACL_UNDERFLOW_VALUE == tmp_check) + { + *p_coeffs_buf = (q31_t) BSP_MACL_Q31_MIN_VALUE; + } + else + { + /* Enable fixed point mode. */ + R_MACL->MULC |= (uint8_t) R_MACL_MULC_MULFRAC_Msk; + + *p_coeffs_buf = (q31_t) R_MACL->MULR5.MULRH; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + } + + /* Increment the coefficient buffer */ + p_coeffs_buf++; + + /* Decrement loop counter */ + tap_cnt--; + } + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + p_state_curnt = p_lms_ins_q31->pState; + + /* copy data */ + /* Initialize tapCnt with number of samples */ + tap_cnt = (num_taps - 1U); + + while (tap_cnt > 0U) + { + *p_state_curnt++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } +} + +/*******************************************************************************************************************//** + * Perform the Q31 FIR filter via MACL module. + * + * @param[in] p_fir_inst Points to an instance of the Q31 FIR filter structure + * @param[in] p_src Points to the block of input data + * @param[in] p_ref Points to the block of reference data + * @param[out] p_out Points to the block of output data + * @param[out] p_err Points to the block of error data + * @param[in] block_size Number of samples to process + **********************************************************************************************************************/ +void R_BSP_MaclFirQ31 (const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size) +{ + q31_t * p_state; // Pointer to state buffer which will be used to hold calculated sample + q31_t * p_state_curnt; // Intermediate pointer used to write sample into state buffer + q31_t * p_state_tmp; // Intermediate pointer to write sample value into register MAC32S + const q31_t * p_coeff_tmp; // Intermediate pointer to write coefficient into register MULB0 + const q31_t * p_coeffs; // Local pointer for p_Coeff of instance p_fir_inst + uint16_t num_taps; // Numbers of coefficient + uint32_t tap_cnt; // Loop count + uint32_t blk_cnt; // Loop count + + p_state = p_fir_inst->pState; + p_coeffs = p_fir_inst->pCoeffs; + + num_taps = p_fir_inst->numTaps; + blk_cnt = block_size; + + /* p_fir_inst->pState points to state array which contains previous frame (num_taps - 1) samples */ + /* p_state_curnt points to the location where the new input data should be written */ + p_state_curnt = &(p_fir_inst->pState[(num_taps - 1U)]); + + /* Enable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + + while (blk_cnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *p_state_curnt++ = *p_src++; + + /* Initialize state pointer */ + p_state_tmp = p_state; + + /* Initialize Coefficient pointer */ + p_coeff_tmp = p_coeffs; + + tap_cnt = num_taps; + + /* Clean result reg */ + R_MACL->MULRCLR = 0U; + + /* Perform the multiply-accumulates */ + do + { + /* y[n] = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + R_MACL->MAC32S = (uint32_t) (*p_state_tmp++); + R_MACL->MULB0 = (uint32_t) (*p_coeff_tmp++); + + r_macl_wait_operation(); + + tap_cnt--; + } while (tap_cnt > 0U); + + /* Store result into destination buffer. */ + *p_dst++ = (q31_t) R_MACL->MULR0.MULRH; + + /* Advance state pointer by 1 for the next sample */ + p_state++; + + /* Decrement loop counter */ + blk_cnt--; + } + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + + /* Processing is complete. Now copy the last num_taps - 1 samples to the start of the state buffer. This prepares + * the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + p_state_curnt = p_fir_inst->pState; + + /* Initialize tapCnt with number of taps */ + tap_cnt = (num_taps - 1U); + + /* Copy remaining data */ + while (tap_cnt > 0U) + { + *p_state_curnt++ = *p_state++; + + /* Decrement loop counter */ + tap_cnt--; + } +} + +/*******************************************************************************************************************//** + * Waiting for MACL module finish 5 cycles of processing. + * + **********************************************************************************************************************/ +static inline void r_macl_wait_operation () +{ + /* Wait for 5 cycles */ + __asm volatile ( + "nop \n" + "nop \n" + "nop \n" + "nop \n" + "nop \n" + ); +} + +/*******************************************************************************************************************//** + * Multiplication operation of MACL module. + * + * @param[in] p_src_a Pointer to multiplied number. + * @param[in] p_src_b Pointer to multiplicand number. + * @param[out] p_dst Pointer to buffer which will hold the calculation result. + * @param[in] block_size Numbers of elements to be calculated. + **********************************************************************************************************************/ +static void r_macl_mul_q31 (const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size) +{ + const q31_t * p_src_a_local; + const q31_t * p_src_b_local; + q31_t * p_dst_local; + uint32_t block_size_cnt; + + block_size_cnt = block_size; + + p_src_a_local = p_src_a; + p_src_b_local = p_src_b; + p_dst_local = p_dst; + + /* Clean result register before perform the calculation */ + R_MACL->MULRCLR = 0U; + + while (block_size_cnt > 0U) + { + if ((*p_src_a_local == (q31_t) BSP_MACL_Q31_MIN_VALUE) && (*p_src_b_local == (q31_t) BSP_MACL_Q31_MIN_VALUE)) + { + /* Overflow case */ + *p_dst_local = (q31_t) BSP_MACL_Q31_MAX_VALUE; + } + else + { + /* Write value to perform the multiply operation */ + R_MACL->MUL32S = (uint32_t) (*p_src_a_local); + R_MACL->MULB0 = (uint32_t) (*p_src_b_local); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + *p_dst_local = (q31_t) R_MACL->MULR0.MULRH; + } + + block_size_cnt--; + p_src_a_local++; + p_src_b_local++; + p_dst_local++; + } +} + +/*******************************************************************************************************************//** + * Perform scaling a vector by multiplying scalar via MACL module. + * + * @param[in] p_src Pointer which point to a vector. + * @param[in] scale_fract Pointer to the scalar number. + * @param[in] shift Number of bits to shift the result by + * @param[out] p_dst Pointer to buffer which will hold the calculation result. + * @param[in] block_size Numbers of elements to be calculated. + **********************************************************************************************************************/ +static void r_macl_scale_q31 (const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size) +{ + const q31_t * p_src_local; + q31_t * p_dst_local; + q31_t out; + uint32_t block_size_cnt; + bool shift_signed; + int32_t scale_shift; /* Shift to apply after scaling */ + + volatile uint32_t * p_result = &(R_MACL->MULR0.MULRH); + + block_size_cnt = block_size; + shift_signed = (bool) (shift & BSP_MACL_SHIFT_SIGN); + scale_shift = shift + 1; + + p_src_local = p_src; + p_dst_local = p_dst; + + /* Clean result register before perform the calculation */ + R_MACL->MULRCLR = 0U; + + /* Write data to register MUL32S. */ + R_MACL->MUL32S = (uint32_t) scale_fract; + + while (block_size_cnt > 0U) + { + /* Write data to register B */ + R_MACL->MULB0 = (uint32_t) (*p_src_local); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + if (shift_signed == BSP_MACL_POSITIVE_NUM) + { + /* Read data to register MULRLn.MULRH */ + out = (q31_t) (*p_result) << scale_shift; + + if (*p_result != (uint32_t) (out >> scale_shift)) + { + /* Overflow/underflow check for shifting result */ + if (BSP_MACL_POSITIVE_NUM == (*p_result >> BSP_MACL_SHIFT_31_BIT)) + { + out = (q31_t) (BSP_MACL_Q31_MAX_VALUE); + } + else + { + out = (q31_t) (BSP_MACL_Q31_MIN_VALUE); + } + } + + /* Write out the result */ + *p_dst_local = out; + } + else + { + /* Read data to register MULRLn.MULRH. */ + out = (q31_t) (*p_result) >> -scale_shift; + + /* Write out the result */ + *p_dst_local = out; + } + + block_size_cnt--; + p_src_local++; + p_dst_local++; + } +} + +/*******************************************************************************************************************//** + * Perform Q31 matrix multiplication via MACL module. + * + * @param[in] p_src_a Points to the first input matrix structure A. + * @param[in] p_src_b Points to the second input matrix structure B. + * @param[out] p_dst Points to the buffer which hold output matrix structure. + **********************************************************************************************************************/ +static void r_macl_mat_mul_q31 (const arm_matrix_instance_q31 * p_src_a, + const arm_matrix_instance_q31 * p_src_b, + arm_matrix_instance_q31 * p_dst) +{ + const q31_t * p_in_a = p_src_a->pData; // Input data matrix pointer A + const q31_t * p_in_b; // Input data matrix pointer B + q31_t * p_out = p_dst->pData; // Output data matrix pointer + uint16_t num_rows_a = p_src_a->numRows; // Number of rows of input matrix A + uint16_t num_cols_b = p_src_b->numCols; // Number of columns of input matrix B + uint16_t num_cols_a = p_src_a->numCols; // Number of columns of input matrix A + uint16_t col; // Column loop counters + uint16_t row = num_rows_a; // Row loop counters + + /* Row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = num_cols_b; + + /* For every row wise process, p_in_b pointer is set to starting address of p_src_b data */ + p_in_b = p_src_b->pData; + + /* Column loop */ + do + { + /* Perform the multiply-accumulates a row in p_src_a with a column in p_src_b */ + r_macl_mat_mul_acc_q31(p_in_a, p_in_b, p_out, num_cols_a, num_cols_b); + + p_in_b++; + p_out++; + col--; + } while (col > 0U); + + row--; + p_in_a += num_cols_a; + } while (row > 0U); +} + +/*******************************************************************************************************************//** + * Perform the multiply-accumulates a row with a column. + * + * @param[in] p_in_a Points to the input data matrix pointer A. + * @param[in] p_in_b Points to the input data matrix pointer B. + * @param[out] p_out Points to the output data matrix pointer. + * @param[in] num_cols_a Number of columns of input matrix A. + * @param[in] num_cols_b Number of columns of input matrix B. + **********************************************************************************************************************/ +static void r_macl_mat_mul_acc_q31 (const q31_t * p_in_a, + const q31_t * p_in_b, + q31_t * p_out, + uint16_t num_cols_a, + uint16_t num_cols_b) +{ + uint16_t cnt = num_cols_a; + const q31_t * p_tmp_a = p_in_a; + const q31_t * p_tmp_b = p_in_b; + q31_t out_h; + q31_t out_l; + + R_MACL->MULRCLR = 0U; + + while (cnt > 0U) + { + R_MACL->MAC32S = (uint32_t) (*p_tmp_a); + R_MACL->MULB0 = (uint32_t) (*p_tmp_b); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + cnt--; + p_tmp_a++; + p_tmp_b += num_cols_b; + } + + /* Read data to register MULR0. */ + out_h = (q31_t) (R_MACL->MULR0.MULRH << BSP_MACL_SHIFT_1_BIT); + out_l = (q31_t) (R_MACL->MULR0.MULRL >> BSP_MACL_SHIFT_31_BIT); + *p_out = (out_h | out_l); +} + +/*******************************************************************************************************************//** + * Perform scaling a matrix by multiplying scalar via MACL module. + * + * @param[in] p_src Points to the input matrix. + * @param[in] scale_fract Fractional portion of the scale factor. + * @param[in] shift Number of bits to shift the result by + * @param[out] p_dst Points to the output matrix structure which will hold the calculation result. + **********************************************************************************************************************/ +static void r_macl_mat_scale_q31 (const arm_matrix_instance_q31 * p_src, + q31_t scale_fract, + int32_t shift, + arm_matrix_instance_q31 * p_dst) +{ + q31_t * p_in = p_src->pData; // Input data matrix pointer + q31_t * p_out = p_dst->pData; // Output data matrix pointer + uint32_t block_size; // Loop counter + q31_t out; // Temporary output data + int32_t scale_shift; // Shift to apply after scaling + volatile uint32_t * p_result = &(R_MACL->MULR0.MULRH); + + scale_shift = shift + 1; + + /* Total number of samples in input matrix */ + block_size = (uint32_t) (p_src->numRows * p_src->numCols); + + /* Clean result register before perform the calculation */ + R_MACL->MULRCLR = 0U; + + /* Write data to register MUL32S. */ + R_MACL->MUL32S = (uint32_t) scale_fract; + + while (block_size > 0U) + { + /* Write data to register B. */ + R_MACL->MULB0 = (uint32_t) (*p_in); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + /* Read data to register MULRL.MULRH. */ + out = (q31_t) (*p_result) << scale_shift; + + if (*p_result != (uint32_t) (out >> scale_shift)) + { + /* Overflow/underflow check for shifting result */ + if (BSP_MACL_POSITIVE_NUM == (*p_result >> BSP_MACL_SHIFT_31_BIT)) + { + out = (q31_t) (BSP_MACL_Q31_MAX_VALUE); + } + else + { + out = (q31_t) (BSP_MACL_Q31_MIN_VALUE); + } + } + + /* Write out the result. */ + *p_out = out; + + block_size--; + p_in++; + p_out++; + } +} + +/*******************************************************************************************************************//** + * Perform multiply-accumulate via MACL for convolution operation. + * + * @param[in] check_value Value which got from result register MULRH. + * @param[out] p_dst Pointer to destination buffer. + **********************************************************************************************************************/ +void r_macl_conv_q31 (const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint8_t block_size) +{ + uint8_t cnt; + const q31_t * p_src_a_local; + const q31_t * p_src_b_local; + q31_t * p_dst_local; + + p_src_a_local = p_src_a; + p_src_b_local = p_src_b; + p_dst_local = p_dst; + + cnt = block_size; + + /* Clean register result */ + R_MACL->MULRCLR = 0U; + + /* Perform multiply-accumulate */ + while (cnt > 0) + { + R_MACL->MAC32S = (uint32_t) (*p_src_a_local); + R_MACL->MULB0 = (uint32_t) (*p_src_b_local); + + /* Wait for the calculation. */ + r_macl_wait_operation(); + + p_src_a_local++; + p_src_b_local--; + cnt--; + } + + /* Store result into desire buffer */ + *p_dst_local = (q31_t) R_MACL->MULR0.MULRH; +} + +/*******************************************************************************************************************//** + * Function to Calculates 1/in (reciprocal) value of Q31 Data type. + * + * @param[in] in Input data. + * @param[out] dst Point to output data. + * @param[in] p_recip_table Points to the reciprocal initial value table. + **********************************************************************************************************************/ + +uint32_t r_macl_recip_q31 (q31_t in, q31_t * dst, const q31_t * p_recip_table) +{ + q31_t out; + uint32_t temp_val; + uint32_t index; + uint32_t sign_bits; + uint64_t reg_val; + volatile uint64_t * p_result_r3 = (uint64_t *) &(R_MACL->MULR3.MULRL); + + /* Enable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_ENABLE; + if (in > 0) + { + sign_bits = ((uint32_t) (__CLZ((uint32_t) in) - 1)); + } + else + { + sign_bits = ((uint32_t) (__CLZ((uint32_t) (-in)) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << sign_bits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = p_recip_table[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (uint32_t i = 0U; i < 2U; i++) + { + R_MACL->MUL32S = (uint32_t) in; + R_MACL->MULB3 = (uint32_t) out; + r_macl_wait_operation(); + temp_val = R_MACL->MULR3.MULRH; + + /* Disable fixed point mode. */ + R_MACL->MULC = BSP_MACL_FIXED_POINT_MODE_DISABLE; + temp_val = BSP_MACL_Q31_MAX_VALUE - temp_val; + + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * temp_val) >> 30); */ + R_MACL->MUL32S = (uint32_t) out; + R_MACL->MULB3 = temp_val; + r_macl_wait_operation(); + reg_val = *p_result_r3; + out = clip_q63_to_q31(((q63_t) reg_val) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of sign_bits of out = 1/in value */ + return sign_bits + 1U; +} + + #endif +#endif + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MACL) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_macl.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_macl.h new file mode 100644 index 0000000000..416228d5c7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_macl.h @@ -0,0 +1,164 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef RENESAS_MACL +#define RENESAS_MACL + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include +#include "bsp_api.h" + +#if BSP_FEATURE_MACL_SUPPORTED + #if __has_include("arm_math_types.h") + +/* Ignore certain math warnings in ARM CMSIS DSP headers */ + #if defined(__ARMCC_VERSION) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wsign-conversion" + #pragma clang diagnostic ignored "-Wimplicit-int-conversion" + #pragma clang diagnostic ignored "-Wimplicit-int-float-conversion" + #elif defined(__GNUC__) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wfloat-conversion" + #endif + #if defined(__IAR_SYSTEMS_ICC__) + #pragma diag_suppress=Pe223 + #endif + + #include "arm_math_types.h" + #include "dsp/basic_math_functions.h" + #include "dsp/matrix_functions.h" + #include "dsp/filtering_functions.h" + #include "dsp/support_functions.h" + #include "dsp/fast_math_functions.h" + + #if defined(__IAR_SYSTEMS_ICC__) + #pragma diag_default=Pe223 + #endif + #if defined(__ARMCC_VERSION) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + #pragma GCC diagnostic pop + #endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MACL + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Common macro used by MACL */ + #define BSP_MACL_FIXED_POINT_MODE_DISABLE (0x0) + #define BSP_MACL_FIXED_POINT_MODE_ENABLE (0x10) + + #define BSP_MACL_SHIFT_SIGN (0x80) + #define BSP_MACL_SHIFT_1_BIT (1U) + #define BSP_MACL_SHIFT_30_BIT (30U) + #define BSP_MACL_SHIFT_31_BIT (31U) + #define BSP_MACL_SHIFT_32_BIT (32U) + + #define BSP_MACL_32_BIT (32U) + + #define BSP_MACL_Q31_MAX_VALUE (0x7FFFFFFF) // Max value is 0.999999999534 + #define BSP_MACL_Q31_MIN_VALUE (0x80000000) // Min value is -1.0 + + #define BSP_MACL_OVERFLOW_VALUE (0x1) // 0b01 + #define BSP_MACL_UNDERFLOW_VALUE (0x2) // 0b10 + + #define BSP_MACL_CLEAR_MULR_REG (0x0U) + + #define BSP_MACL_POSITIVE_NUM (0U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +void R_BSP_MaclMulQ31(const q31_t * p_src_a, const q31_t * p_src_b, q31_t * p_dst, uint32_t block_size); +void R_BSP_MaclScaleQ31(const q31_t * p_src, q31_t scale_fract, int8_t shift, q31_t * p_dst, uint32_t block_size); +void R_BSP_MaclMatMulQ31(const arm_matrix_instance_q31 * p_src_a, + const arm_matrix_instance_q31 * p_src_b, + arm_matrix_instance_q31 * p_dst); +void R_BSP_MaclMatVecMulQ31(const arm_matrix_instance_q31 * p_src_mat, const q31_t * p_vec, q31_t * p_dst); +void R_BSP_MaclMatScaleQ31(const arm_matrix_instance_q31 * p_src, + q31_t scale_fract, + int32_t shift, + arm_matrix_instance_q31 * p_dst); +void R_BSP_MaclBiquadCsdDf1Q31(const arm_biquad_casd_df1_inst_q31 * p_biquad_csd_df1_inst, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size); +void R_BSP_MaclConvQ31(const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst); +arm_status R_BSP_MaclConvPartialQ31(const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst, + uint32_t first_idx, + uint32_t num_points); + +void R_BSP_MaclFirDecimateQ31(const arm_fir_decimate_instance_q31 * p_fir_decimate_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size); + +void R_BSP_MaclFirInterpolateQ31(const arm_fir_interpolate_instance_q31 * p_fir_interpolate_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + uint32_t block_size); + +void R_BSP_MaclCorrelateQ31(const q31_t * p_src_a, + uint32_t src_a_len, + const q31_t * p_src_b, + uint32_t src_b_len, + q31_t * p_dst); + +void R_BSP_MaclFirSparseQ31(arm_fir_sparse_instance_q31 * p_fir_sparse_ins_q31, + const q31_t * p_src, + q31_t * p_dst, + q31_t * p_scratch_in, + uint32_t block_size); + +void R_BSP_MaclLmsNormQ31(arm_lms_norm_instance_q31 * p_lms_norm_ins_q31, + const q31_t * p_src, + q31_t * p_ref, + q31_t * p_out, + q31_t * p_err, + uint32_t block_size); + +void R_BSP_MaclLmsQ31(const arm_lms_instance_q31 * p_lms_ins_q31, + const q31_t * p_src, + q31_t * p_ref, + q31_t * p_out, + q31_t * p_err, + uint32_t block_size); + +void R_BSP_MaclFirQ31(const arm_fir_instance_q31 * p_fir_inst, const q31_t * p_src, q31_t * p_dst, uint32_t block_size); + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MACL) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + + #endif +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h new file mode 100644 index 0000000000..b548ca79dc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h @@ -0,0 +1,87 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MCU_API_H +#define BSP_MCU_API_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Linker Includes. */ +#include "bsp_linker_info.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if BSP_PERIPHERAL_ELC_PRESENT || BSP_PERIPHERAL_ELC_B_PRESENT +typedef struct st_bsp_event_info +{ + IRQn_Type irq; + elc_event_t event; +} bsp_event_info_t; +#endif + +#ifndef BSP_OVERRIDE_BSP_CLOCKS_OCTACLK_DIV_T + +typedef enum e_bsp_clocks_octaclk_div +{ + BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 + BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 + BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 + BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 + BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 + BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 + BSP_CLOCKS_OCTACLK_DIV_5, ///< Divide OCTA source clock by 5 + BSP_CLOCKS_OCTACLK_DIV_10, ///< Divide OCTA source clock by 10 + BSP_CLOCKS_OCTACLK_DIV_16, ///< Divide OCTA source clock by 16 + BSP_CLOCKS_OCTACLK_DIV_32, ///< Divide OCTA source clock by 32 +} bsp_clocks_octaclk_div_t; +#endif + +typedef enum e_bsp_clocks_source +{ + BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator. + BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator. + BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator. + BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator. + BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator. + BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator. + BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator. +} bsp_clocks_source_t; + +typedef struct st_bsp_octaclk_settings +{ + bsp_clocks_source_t source_clock; ///< OCTACLK source clock + bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider +} bsp_octaclk_settings_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); +void R_BSP_OctaclkUpdate(bsp_octaclk_settings_t * p_octaclk_setting); +void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_mmf.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_mmf.h new file mode 100644 index 0000000000..9b7f1b143f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_mmf.h @@ -0,0 +1,141 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MMF_H +#define BSP_MMF_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define MEMORY_MIRROR_REG_KEY (0xDBU) +#define MEMORY_MIRROR_BOUNDARY (0x80U) // 128 bytes +#define MEMORY_MIRROR_ADDR_MASK (0x007FFFFFU) + +/* The highest address which MMF able to support is the last address of code flash area which aligns with 128. */ +#define MEMORY_MIRROR_MAX_ADDR (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES - MEMORY_MIRROR_BOUNDARY) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enum for state of Memory Mirror Function. */ +typedef enum e_mmf_state +{ + MEMORY_MIRROR_DISABLED = 0, + MEMORY_MIRROR_ENABLED = 1, +} mmf_state_t; + +/** Status instance of Memory Mirror Function. */ +typedef struct st_mmf_status +{ + mmf_state_t mmf_state; // Current state of Memory Mirror Region. + uint32_t mmf_cur_addr; // Current address in register MMSFR. +} mmf_status_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the current status of Memory Mirror. + * + * @param[out] p_mmf_status Pointer to instance which used for storing the state of MMF after invoked this function. + * + * @retval FSP_SUCCESS MMF status retrieved successfully. + * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. + * @retval FSP_ERR_ASSERTION NULL pointer passed as argument. + * + * This function retrieves the current state of the MMF and the mirrored address into a user provided structure. + **********************************************************************************************************************/ +__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorStatusGet (mmf_status_t * p_mmf_status) +{ +#if BSP_FEATURE_BSP_MMF_SUPPORTED + #if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Ensure that variable for storing the status of MMF was provided. */ + if (NULL == p_mmf_status) + { + return FSP_ERR_ASSERTION; + } + #endif + + p_mmf_status->mmf_state = (mmf_state_t) R_MMF->MMEN_b.EN; + p_mmf_status->mmf_cur_addr = R_MMF->MMSFR & MEMORY_MIRROR_ADDR_MASK; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_mmf_status); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Set address for MMF region. + * + * @param[in] addr Address of memory region to be mirrored into MMF region. + * + * @retval FSP_SUCCESS Address is set successfully. + * @retval FSP_ERR_UNSUPPORTED MCU does not support MMF. + * @retval FSP_ERR_INVALID_ADDRESS Requested address is out of supported range. + * + * This function sets the memory address to be mirrored by MMF. + **********************************************************************************************************************/ +__STATIC_INLINE fsp_err_t R_BSP_MemoryMirrorAddrSet (const uint32_t addr) +{ +#if BSP_FEATURE_BSP_MMF_SUPPORTED + #if BSP_CFG_PARAM_CHECKING_ENABLE + + /* Ensure that requested address is in supported range and must align with 128 */ + if ((MEMORY_MIRROR_MAX_ADDR < addr) || (0 != addr % MEMORY_MIRROR_BOUNDARY)) + { + return FSP_ERR_INVALID_ADDRESS; + } + #endif + + /* If MMF is enabled, disable MMF before updating the address register. + * For disabling MMF, write 0xDB00 to register MMEN. */ + if (1U == R_MMF->MMEN_b.EN) + { + R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 0U); + } + + R_MMF->MMSFR = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | addr); + + /* Enable MMF by writing 0xDB01 to register MMEN. After this point target memory address will be reflected into + * MMF region. */ + R_MMF->MMEN = ((uint32_t) (MEMORY_MIRROR_REG_KEY << R_MMF_MMSFR_KEY_Pos) | 1U); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(addr); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif + +/** @} (end addtogroup BSP_MCU) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h new file mode 100644 index 0000000000..ab3b22b4e2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -0,0 +1,389 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_MODULE_H +#define BSP_MODULE_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + +/* MSTPCRA is located in R_MSTP for Star devices. */ + #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) +#else + +/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ + #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) +#endif + +/*******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE + #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ + BSP_DELAY_UNITS_MICROSECONDS); \ + FSP_CRITICAL_SECTION_EXIT;} +#else + #define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= \ + (BSP_MSTP_REG_TYPE_ ## ip(channel)) ~BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} +#endif + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#if BSP_CFG_MSTP_CHANGE_DELAY_ENABLE + #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, \ + BSP_DELAY_UNITS_MICROSECONDS); \ + FSP_CRITICAL_SECTION_EXIT;} +#else + #define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + FSP_REGISTER_READ(BSP_MSTP_REG_ ## ip(channel)); \ + FSP_CRITICAL_SECTION_EXIT;} +#endif + +/** @} (end addtogroup BSP_MCU) */ + +#if 0U == BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD + #if !BSP_FEATURE_GPT_MSTP_MSTPD5 + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 6U) + #else + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH >= \ + channel) ? (1U << 5U) : (1U << 6U)); + #endif + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + + #if BSP_MCU_GROUP_RA2A2 + +/* RA2A2 has a combination of AGT and AGTW. + * Ch 0-1: MSTPD[ 3: 2] (AGTW0, AGTW1) + * Ch 2-3: MSTPD[19:18] (AGT0, AGT1) + * Ch 4-5: MSTPD[ 1: 0] (AGT2, AGT3) + * Ch 6-9: MSTPD[10: 7] (AGT4, AGT5, AGT6, AGT7) + */ + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << \ + ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ + ? (3U - channel) \ + : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 2U) \ + ? (19U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT) \ + : ((channel < BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + 4U) \ + ? (1U - channel + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ + 2U) \ + : (10U - channel + \ + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + \ + 4U))))); + + #else + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #endif + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #if BSP_FEATURE_POEG_MSTP_MSTPD13 + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #else + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); + #endif + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t +#else + #if (2U == BSP_FEATURE_ELC_VERSION) + #if BSP_MCU_GROUP_RA6T2 + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #elif BSP_MCU_GROUP_RA8_GEN2 + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << \ + (31 - ((channel >= 4U && channel <= 9U) ? 4U : channel))) // GPT Channels 4-9 share stop bits on this MCU + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (6U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #else + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (5U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #endif + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); + #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_ULPT(channel) uint32_t + #else + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_GPT_PDG(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT_PDG(channel) (1U << (31U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_GPT_PDG(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ + channel) ? (1U << (3U - channel)) : (1U << \ + (15U - \ + (channel - 4U)))); + #define BSP_MSTP_REG_TYPE_FSP_IP_AGT(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_KEY(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_TYPE_FSP_IP_POEG(channel) uint32_t + #endif +#endif + +#if (1U == BSP_FEATURE_CGC_HAS_OSTDCSE) + #define BSP_MSTP_REG_FSP_IP_SOSTD(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_SOSTD(channel) (1U << (16U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_SOSTD(channel) uint32_t + #define BSP_MSTP_REG_FSP_IP_MOSTD(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_MOSTD(channel) (1U << (17U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_MOSTD(channel) uint32_t +#endif + +#define BSP_MSTP_REG_FSP_IP_NPU(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_NPU(channel) (1U << (16U)); + +#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA +#if BSP_MCU_GROUP_RA8_GEN2 && (1U == BSP_CFG_CPU_CORE) + #define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (23U)); +#else + #define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); +#endif + +#define BSP_MSTP_REG_TYPE_FSP_IP_DMAC(channel) uint32_t + +#if BSP_FEATURE_CGC_REGISTER_SET_B + #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA + #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (6U)) + #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint16_t +#else + #define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA + #if BSP_MCU_GROUP_RA8_GEN2 && (1U == BSP_CFG_CPU_CORE) + #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (23U)); + #else + #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); + #endif + #define BSP_MSTP_REG_TYPE_FSP_IP_DTC(channel) uint32_t +#endif +#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CAN(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CEC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_I3C(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_I3C(channel) (1U << (BSP_FEATURE_I3C_MSTP_OFFSET - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_I3C(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IRDA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_QSPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SAU(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SAU(channel) (1U << (6U + channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SAU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IIC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IICA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IICA(channel) (1U << (10U + channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IICA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBFS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBHS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_EPTPC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_USBCC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBCC(channel) (1U << (14U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_USBCC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ETHER(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_UARTA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_UARTA(channel) (1U << BSP_FEATURE_UARTA_MSTP_OFFSET); +#define BSP_MSTP_REG_TYPE_FSP_IP_UARTA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U + channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_OSPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SPI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_REG_TYPE_FSP_IP_SCI(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CAC(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); +#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CRC(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); +#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_PDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CTSU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SLCDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_GLCDC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_JPEG(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DRW(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SSI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SRC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_MIPI_DSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MIPI_DSI(channel) (1U << (10U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_DSI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SDHIMMC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DOC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ELC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_MACL(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MACL(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_MACL(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CEU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_REG_TYPE_FSP_IP_CEU(channel) uint32_t +#define BSP_MSTP_BIT_FSP_IP_CEU(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_MIPI_CSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MIPI_CSI(channel) (1U << (17U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_MIPI_CSI(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TFU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_IIRFA(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_PDM(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDM(channel) (1U << (24U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_PDM(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_CANFD(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TRNG(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SCE(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_AES(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TAU(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TAU(channel) (1U << (0U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TAU(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_TML(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TML(channel) (1U << (4U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TML(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DSMIF(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DSMIF(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD +#if BSP_MCU_GROUP_RA8_GEN2 + #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (21U - channel)); +#else + #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); +#endif +#define BSP_MSTP_REG_TYPE_FSP_IP_ADC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_SDADC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_DAC(channel) uint32_t +#if (BSP_PERIPHERAL_DAC8_PRESENT) + #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); + #define BSP_MSTP_REG_TYPE_FSP_IP_DAC8(channel) uint32_t +#endif +#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_TSN(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (23U)); +#define BSP_MSTP_REG_TYPE_FSP_IP_RTC(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPHS(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); +#define BSP_MSTP_REG_TYPE_FSP_IP_ACMPLP(channel) uint32_t +#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_TYPE_FSP_IP_OPAMP(channel) uint32_t + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c new file mode 100644 index 0000000000..11e0362681 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_OSPI_B BSP OSPI_B support + * @ingroup RENESAS_COMMON + * @brief Code that initializes the OSPI_B device memory. + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if 0 != BSP_FEATURE_OSPI_B_IS_AVAILABLE + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Initializes OSPI_B. + * @param p_startup_fn Function pointer to the method which starts the OSPI and transitions it to the + * appropriate mode. + * @param init_from_sip_memory If true, this function will initialize internal memory regions sourced from SiP Flash. + * + * This function initializes an attached OSPI_B memory device. + * + * @note This function must only be called once after reset. + **********************************************************************************************************************/ +void R_BSP_OspiBInit (bsp_ospi_b_startup_fn_t p_startup_fn, bool init_from_sip_memory) +{ + /* Call the startup function to open the OSPI_B peripheral and put it into the correct mode. */ + if (FSP_SUCCESS != p_startup_fn()) + { + /* If startup fails memory cannot be initialized so return. */ + return; + } + + if (init_from_sip_memory) + { + /* Initialize internal memory regions sourced from SiP Flash. */ + for (uint32_t i = 0; i < g_init_info.copy_count; i++) + { + const bsp_init_copy_info_t * const p_copy = &g_init_info.p_copy_list[i]; + if ((INIT_MEM_SIP_FLASH == p_copy->type.source_type) && !p_copy->type.external) + { + memcpy(p_copy->p_base, p_copy->p_load, ((uint32_t) p_copy->p_limit - (uint32_t) p_copy->p_base)); + } + } + } +} + +#endif + +/** @} (end addtogroup BSP_OSPI_B) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h new file mode 100644 index 0000000000..ce3e62ad0c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_OSPI_B_H +#define BSP_OSPI_B_H + +#include "bsp_api.h" + +#if 0 != BSP_FEATURE_OSPI_B_IS_AVAILABLE + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef fsp_err_t (* bsp_ospi_b_startup_fn_t)(void); + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_OspiBInit(bsp_ospi_b_startup_fn_t p_startup_fn, bool init_from_sip_memory); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c new file mode 100644 index 0000000000..f1747b8bc1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c @@ -0,0 +1,120 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Used for holding reference counters for protection bits. */ +volatile uint16_t g_protect_counters[5] BSP_SECTION_EARLY_INIT; + +/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t g_prcr_masks[] = +{ + 0x0001U, /* PRC0. */ + 0x0002U, /* PRC1. */ + 0x0008U, /* PRC3. */ + 0x0010U, /* PRC4. */ + 0x0020U, /* PRC5. */ +}; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enable register protection. Registers that are protected cannot be written to. Register protection is + * enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_protect Registers which have write protection enabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ + /** Get/save the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Is it safe to disable write access? */ + if (0U != g_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + g_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0U == g_protect_counters[regs_to_protect]) + { + /** Enable protection using PRCR register. + * + * When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ +#if BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + R_SYSTEM->PRCR_NS = ((R_SYSTEM->PRCR_NS | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); +#else + R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); +#endif + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * Disable register protection. Registers that are protected cannot be written to. Register protection is + * disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_unprotect Registers which have write protection disabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ + /** Get/save the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* If this is first entry then disable protection. */ + if (0U == g_protect_counters[regs_to_unprotect]) + { + /** Disable protection using PRCR register. + * + * When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ +#if BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + R_SYSTEM->PRCR_NS = ((R_SYSTEM->PRCR_NS | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); +#else + R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); +#endif + } + + /** Increment the protect counter */ + g_protect_counters[regs_to_unprotect]++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h new file mode 100644 index 0000000000..171a2f69ba --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_REGISTER_PROTECTION_H +#define BSP_REGISTER_PROTECTION_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** The different types of registers that can be protected. */ +typedef enum e_bsp_reg_protect +{ + /** Enables writing to the registers related to the clock generation circuit. */ + BSP_REG_PROTECT_CGC = 0, + + /** Enables writing to the registers related to operating modes, low power consumption, and battery backup + * function. */ + BSP_REG_PROTECT_OM_LPC_BATT, + + /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + * LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /** Enables writing to the registers related to the security function. */ + BSP_REG_PROTECT_SAR, + + /** Enables writing to the registers related to reset control. */ + BSP_REG_PROTECT_RESET, +} bsp_reg_protect_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_register_protect_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_sdram.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_sdram.c new file mode 100644 index 0000000000..22999c9274 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_sdram.c @@ -0,0 +1,199 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @defgroup BSP_SDRAM BSP SDRAM support + * @ingroup RENESAS_COMMON + * @brief Code that initializes the SDRAMC and SDR SDRAM device memory. + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Due to hardware limitations of the SDRAM peripheral, + * it is not expected any of these need to be changeable by end user. + * Only sequential, single access at a time is supported. */ +#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */ +#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */ +#define BSP_PRV_SDRAM_MR_BT_SEQUENTIAL (0U) /* MR.M3 Burst Type : Sequential */ +#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS + +/*******************************************************************************************************************//** + * @brief Initializes SDRAM. + * @param init_memory If true, this function will execute the initialization of the external modules. + * Otherwise, it will only initialize the SDRAMC and leave the memory in self-refresh mode. + * + * This function initializes SDRAMC and SDR SDRAM device. + * + * @note This function must only be called once after reset. + **********************************************************************************************************************/ +void R_BSP_SdramInit (bool init_memory) +{ + /** Setting for SDRAM initialization sequence */ + while (R_BUS->SDRAM.SDSR) + { + /* According to h/w manual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */ + } + + /* Must only write to SDIR once after reset. */ + R_BUS->SDRAM.SDIR = ((BSP_CFG_SDRAM_INIT_ARFI - 3U) << R_BUS_SDRAM_SDIR_ARFI_Pos) | + (BSP_CFG_SDRAM_INIT_ARFC << R_BUS_SDRAM_SDIR_ARFC_Pos) | + ((BSP_CFG_SDRAM_INIT_PRC - 3U) << R_BUS_SDRAM_SDIR_PRC_Pos); + + R_BUS->SDRAM.SDCCR = (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); /* set SDRAM bus width */ + + if (init_memory) + { + /* Enable the SDCLK output. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->SDCKOCR = 1; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /** If requested, start SDRAM initialization sequence. */ + R_BUS->SDRAM.SDICR = 1U; + while (R_BUS->SDRAM.SDSR_b.INIST) + { + /* Wait the end of initialization sequence. */ + } + } + + /** Setting for SDRAM controller */ + R_BUS->SDRAM.SDAMOD = BSP_CFG_SDRAM_ACCESS_MODE; /* enable continuous access */ + R_BUS->SDRAM.SDCMOD = BSP_CFG_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */ + + while (R_BUS->SDRAM.SDSR) + { + /* According to h/w manual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */ + } + + if (init_memory) + { + /** Using LMR command, program the mode register */ + R_BUS->SDRAM.SDMOD = (BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) | + (BSP_PRV_SDRAM_MR_OP_MODE << 7) | + (BSP_CFG_SDRAM_TCL << 4) | + (BSP_PRV_SDRAM_MR_BT_SEQUENTIAL << 3) | + (BSP_PRV_SDRAM_MR_BURST_LENGTH << 0); + + /** wait at least tMRD time */ + while (R_BUS->SDRAM.SDSR_b.MRSST) + { + /* Wait until Mode Register setting done. */ + } + } + + /** Set timing parameters for SDRAM. Must do in single write. */ + R_BUS->SDRAM.SDTR = ((BSP_CFG_SDRAM_TRAS - 1U) << R_BUS_SDRAM_SDTR_RAS_Pos) | + ((BSP_CFG_SDRAM_TRCD - 1U) << R_BUS_SDRAM_SDTR_RCD_Pos) | + ((BSP_CFG_SDRAM_TRP - 1U) << R_BUS_SDRAM_SDTR_RP_Pos) | + ((BSP_CFG_SDRAM_TWR - 1U) << R_BUS_SDRAM_SDTR_WR_Pos) | + (BSP_CFG_SDRAM_TCL << R_BUS_SDRAM_SDTR_CL_Pos); + + /** Set row address offset for target SDRAM */ + R_BUS->SDRAM.SDADR = BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT; + + /* Set Auto-Refresh timings. */ + R_BUS->SDRAM.SDRFCR = ((BSP_CFG_SDRAM_TREFW - 1U) << R_BUS_SDRAM_SDRFCR_REFW_Pos) | + ((BSP_CFG_SDRAM_TRFC - 1U) << R_BUS_SDRAM_SDRFCR_RFC_Pos); + + /** Start Auto-refresh */ + R_BUS->SDRAM.SDRFEN = 1U; + + if (init_memory) + { + /** Enable SDRAM access */ + R_BUS->SDRAM.SDCCR = R_BUS_SDRAM_SDCCR_EXENB_Msk | (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); + } + else + { + /* If not initializing memory modules, start in self-refresh mode. */ + while (R_BUS->SDRAM.SDCCR_b.EXENB || (0U != R_BUS->SDRAM.SDSR)) + { + /* Wait for access to be disabled and no status bits set. */ + } + + /* Enable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 1U; + } +} + +/*******************************************************************************************************************//** + * @brief Changes SDRAM from Auto-refresh to Self-refresh + * + * This function allows Software Standby and Deep Software Standby modes to be entered without data loss. + * + * @note SDRAM cannot be accessed after calling this function. Use @ref R_BSP_SdramSelfRefreshDisable to resume normal + * SDRAM operation. + **********************************************************************************************************************/ +void R_BSP_SdramSelfRefreshEnable (void) +{ + R_BUS->SDRAM.SDCCR = (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); + while (R_BUS->SDRAM.SDCCR_b.EXENB || (0U != R_BUS->SDRAM.SDSR)) + { + /* Wait for access to be disabled and no status bits set. */ + } + + /* Enable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 1U; +} + +/*******************************************************************************************************************//** + * @brief Changes SDRAM from Self-refresh to Auto-refresh + * + * This function changes back to Auto-refresh and allows normal SDRAM operation to resume. + * + **********************************************************************************************************************/ +void R_BSP_SdramSelfRefreshDisable (void) +{ + if (0 == R_SYSTEM->SDCKOCR) + { + /* Enable the SDCLK output. It may not already be enabled here if recovering from Deep Software Standby. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->SDCKOCR = 1; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + } + + while (0U != R_BUS->SDRAM.SDSR) + { + /* Wait for all status bits to be cleared. */ + } + + /* Disable the self-refresh mode. */ + R_BUS->SDRAM.SDSELF = 0U; + + /* Reenable SDRAM bus access. */ + R_BUS->SDRAM.SDCCR = R_BUS_SDRAM_SDCCR_EXENB_Msk | (BSP_CFG_SDRAM_BUS_WIDTH << R_BUS_SDRAM_SDCCR_BSIZE_Pos); +} + +#endif + +/** @} (end addtogroup BSP_SDRAM) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_sdram.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_sdram.h new file mode 100644 index 0000000000..5ba56a6383 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_sdram.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_SDRAM_H +#define BSP_SDRAM_H + +#if 0 != BSP_FEATURE_SDRAM_START_ADDRESS + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_SdramInit(bool init_memory); +void R_BSP_SdramSelfRefreshEnable(void); +void R_BSP_SdramSelfRefreshDisable(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_security.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_security.c new file mode 100644 index 0000000000..5feceda11c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_security.c @@ -0,0 +1,563 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #define BSP_PRV_TZ_REG_KEY (0xA500U) + #define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U) + #define RA_NOT_DEFINED (0) + +/* Branch T3 Instruction (IMM11=-2) */ + #define BSP_PRV_INFINITE_LOOP (0xE7FE) + + #define BSP_SAU_REGION_CODE_FLASH_NSC (0U) + #define BSP_SAU_REGION_1_NS (1U) + #define BSP_SAU_REGION_SRAM_NSC (2U) + #define BSP_SAU_REGION_2_NS (3U) + #define BSP_SAU_REGION_3_NS (4U) + +/* Non-secure regions defined by the IDAU. These regions must be defined as non-secure in the SAU. */ + #define BSP_PRV_SAU_NS_REGION_1_BASE_ADDRESS (0x10000000U) + #define BSP_PRV_SAU_NS_REGION_1_LIMIT_ADDRESS (0x1FFFFFFFU) + #define BSP_PRV_SAU_NS_REGION_2_BASE_ADDRESS (0x30000000U) + #define BSP_PRV_SAU_NS_REGION_2_LIMIT_ADDRESS (0x3FFFFFFFU) + #define BSP_PRV_SAU_NS_REGION_3_BASE_ADDRESS (0x50000000U) + #define BSP_PRV_SAU_NS_REGION_3_LIMIT_ADDRESS (0xDFFFFFFFU) + +/* Protect DMAST/DTCST from nonsecure write access. */ + #if (1U == BSP_CFG_CPU_CORE) + #define DMACX_REGISTER_SHIFT (16) + #define DTCX_REGISTER_SHIFT (16) + #else + #define DMACX_REGISTER_SHIFT (0) + #define DTCX_REGISTER_SHIFT (0) + #endif + +/* Macros to align to next memory region for TZ (mainly to "find" NS locations) */ + #if defined(BSP_PARTITION_FLASH_CPU0_S_START) && (0U == BSP_CFG_CPU_CORE) + +/* Use partition macros for primary core */ + #define FLASH_NSC_START ((uint32_t *) BSP_PARTITION_FLASH_CPU0_C_START) + #define FLASH_NSC_LIMIT ((uint32_t) BSP_PARTITION_FLASH_CPU0_C_START + BSP_PARTITION_FLASH_CPU0_C_SIZE - 1) + #define FLASH_NS_START ((uint32_t *) BSP_PARTITION_FLASH_CPU0_N_START) + #define RAM_NSC_START ((uint32_t *) BSP_PARTITION_RAM_CPU0_C_START) + #define RAM_NSC_LIMIT ((uint32_t) BSP_PARTITION_RAM_CPU0_C_START + BSP_PARTITION_RAM_CPU0_C_SIZE - 1) + #define RAM_NS_START ((uint32_t *) BSP_PARTITION_RAM_CPU0_N_START) + #define DATA_FLASH_NS_START ((uint32_t *) BSP_PARTITION_DATA_FLASH_CPU0_N_START) + + #elif defined(BSP_PARTITION_FLASH_CPU1_S_START) && (1U == BSP_CFG_CPU_CORE) + +/* Use partition macros for secondary core */ + #define FLASH_NSC_START ((uint32_t *) BSP_PARTITION_FLASH_CPU1_C_START) + #define FLASH_NSC_LIMIT ((uint32_t) BSP_PARTITION_FLASH_CPU1_C_START + BSP_PARTITION_FLASH_CPU1_C_SIZE - 1) + #define FLASH_NS_START ((uint32_t *) BSP_PARTITION_FLASH_CPU1_N_START) + #define RAM_NSC_START ((uint32_t *) BSP_PARTITION_RAM_CPU1_C_START) + #define RAM_NSC_LIMIT ((uint32_t) BSP_PARTITION_RAM_CPU1_C_START + BSP_PARTITION_RAM_CPU1_C_SIZE - 1) + #define RAM_NS_START ((uint32_t *) BSP_PARTITION_RAM_CPU1_N_START) + #define DATA_FLASH_NS_START ((uint32_t *) BSP_PARTITION_DATA_FLASH_CPU1_N_START) + + #else + +/* Use legacy tail-chaining to find NS */ + #define FLASH_NS_START ((uint32_t *) ((((uint32_t) gp_ddsc_FLASH_END + 0x8000 - 1) & \ + 0xFFFF8000) | BSP_FEATURE_TZ_NS_OFFSET)) + #define FLASH_NSC_START ((uint32_t *) gp_ddsc_FLASH_NSC) + #define FLASH_NSC_LIMIT (((uint32_t) FLASH_NS_START & ~BSP_FEATURE_TZ_NS_OFFSET) - 1U) + #define RAM_NS_START ((uint32_t *) ((((uint32_t) gp_ddsc_RAM_END + 0x2000 - 1) & \ + 0xFFFFE000) | BSP_FEATURE_TZ_NS_OFFSET)) + #define RAM_NSC_START ((uint32_t *) gp_ddsc_RAM_NSC) + #define RAM_NSC_LIMIT (((uint32_t) RAM_NS_START & ~BSP_FEATURE_TZ_NS_OFFSET) - 1U) + #define DATA_FLASH_NS_START ((uint32_t *) ((((uint32_t) gp_ddsc_DATA_FLASH_END + 0x400 - 1) & \ + 0xFFFFFC00) | BSP_FEATURE_TZ_NS_OFFSET)) + + #endif + + #define RAM_NS_START_S_ALIAS ((uint32_t *) ((uint32_t) RAM_NS_START & ~BSP_FEATURE_TZ_NS_OFFSET)) + +/* Operation after detection registers. + * RA8 devices have the registers under MSA/BUS while other devices have them under TZF. */ + #ifdef R_TZF + #define BSP_PRV_OAD_REG R_TZF->TZFOAD + #define BSP_PRV_OAD_PT_REG R_TZF->TZFPT + #else + #define BSP_PRV_OAD_REG R_BUS->OAD.MSAOAD + #define BSP_PRV_OAD_PT_REG R_BUS->OAD.MSAPT + #endif + + #if BSP_SECONDARY_CORE_BUILD + +/* For a secure secondary core the SAR has already been written so it + * only needs to modify the security attributes it is using: + * - Secure (0) will always stay Secure + * - Non-secure (1) will either stay non-secure or become secure + * This is the same as using a bitwise AND. + */ + #define BSP_PRV_SAR_WRITE(register, value) register &= value + #else + #define BSP_PRV_SAR_WRITE(register, value) register = value + #endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_SAUInit(void); +void R_BSP_SecurityInit(void); +void R_BSP_PinCfgSecurityInit(void); +void R_BSP_ElcCfgSecurityInit(void); + +/*********************************************************************************************************************** + * External symbols + **********************************************************************************************************************/ + + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * bsp_nonsecure_func_t)(void); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void); + #endif + + #if BSP_TZ_SECURE_BUILD + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enter the non-secure code environment. + * + * This function configures the non-secure MSP and vector table then jumps to the non-secure project's Reset_Handler. + * + * @note This function (and therefore the non-secure code) should not return. + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter (void) +{ + /* The NS vector table is at the start of the NS section in flash */ + uint32_t const * p_ns_vector_table = FLASH_NS_START; + + /* Set up the NS Reset_Handler to be called */ + uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t)); + bsp_nonsecure_func_t p_ns_reset = (bsp_nonsecure_func_t) (*p_ns_reset_address); + + #if BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK + + /* Check if the NS application exists. If the address of the Reset_Handler is all '1's, then assume that + * the NS application has not been programmed. + * + * If the secure application attempts to jump to an invalid instruction, a HardFault will occur. If the + * MCU is in NSECSD state, then the debugger will be unable to connect and program the NS Application. Jumping to + * a valid instruction ensures that the debugger will be able to connect. + */ + if (UINT32_MAX == *p_ns_reset_address) + { + p_ns_reset = (bsp_nonsecure_func_t) ((uint32_t) RAM_NS_START); + + /* Write an infinite loop into start of NS RAM (Branch T3 Instruction (b.n )). */ + uint16_t * infinite_loop = (uint16_t *) ((uint32_t) RAM_NS_START); + *infinite_loop = BSP_PRV_INFINITE_LOOP; + + /* Set the NS stack pointer to a valid location in NS RAM. */ + __TZ_set_MSP_NS((uint32_t) RAM_NS_START + 0x20U); + + /* Jump to the infinite loop. */ + p_ns_reset(); + } + #endif + + /* Set the NS vector table address */ + SCB_NS->VTOR = (uint32_t) p_ns_vector_table; + + /* Set the NS stack pointer to the first entry in the NS vector table */ + __TZ_set_MSP_NS(p_ns_vector_table[0]); + + /* Jump to the NS Reset_Handler */ + p_ns_reset(); +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Initialize SAU regions for TrustZone. + * + * This function initializes ARM SAU regions for secure projects. + * + * @note IDAU settings must be configured to match project settings with a separate configuration tool. + **********************************************************************************************************************/ +void R_BSP_SAUInit (void) +{ + #if __SAUREGION_PRESENT + #if !BSP_SECONDARY_CORE_BUILD + + /* Configure IDAU to divide SRAM region into NSC/NS. */ + R_CPSCU->SRAMSABAR0 = (uint32_t) RAM_NS_START_S_ALIAS & R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk; + R_CPSCU->SRAMSABAR1 = (uint32_t) RAM_NS_START_S_ALIAS & R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk; + #if BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR + R_CPSCU->SRAMSABAR2 = (uint32_t) RAM_NS_START_S_ALIAS & R_CPSCU_SRAMSABAR2_SRAMSABAR_Msk; + R_CPSCU->SRAMSABAR3 = (uint32_t) RAM_NS_START_S_ALIAS & R_CPSCU_SRAMSABAR3_SRAMSABAR_Msk; + #endif + + #ifdef BSP_TZ_CFG_SRAMESAR + + /* Configure SRAM ECC Region as S/NS */ + R_CPSCU->SRAMESAR = BSP_TZ_CFG_SRAMESAR; + #endif + #endif + + /* Configure SAU region used for Code Flash Non-secure callable. */ + SAU->RNR = BSP_SAU_REGION_CODE_FLASH_NSC; + SAU->RBAR = (uint32_t) FLASH_NSC_START & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (FLASH_NSC_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 1: + * - ITCM + * - Code Flash + * - On-chip flash (Factory Flash) + * - On-chip flash (option-setting memory) + */ + SAU->RNR = BSP_SAU_REGION_1_NS; + SAU->RBAR = (uint32_t) BSP_PRV_SAU_NS_REGION_1_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = ((BSP_PRV_SAU_NS_REGION_1_LIMIT_ADDRESS) &SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure callable SRAM. */ + SAU->RNR = BSP_SAU_REGION_SRAM_NSC; + SAU->RBAR = (uint32_t) RAM_NSC_START & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (RAM_NSC_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_NSC_Msk | + SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 2: + * - DTCM + * - On-chip SRAM + * - Standby SRAM + * - On-chip flash (data flash) + */ + SAU->RNR = BSP_SAU_REGION_2_NS; + SAU->RBAR = ((uint32_t) BSP_PRV_SAU_NS_REGION_2_BASE_ADDRESS & SAU_RBAR_BADDR_Msk) | BSP_FEATURE_TZ_NS_OFFSET; + SAU->RLAR = (BSP_PRV_SAU_NS_REGION_2_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure SAU region used for Non-secure region 3: + * - Peripheral I/O registers + * - Flash I/O registers + * - External address space (CS area) + * - External address space (SDRAM area) + * - External address space (OSPI area) + */ + SAU->RNR = BSP_SAU_REGION_3_NS; + SAU->RBAR = BSP_PRV_SAU_NS_REGION_3_BASE_ADDRESS & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (BSP_PRV_SAU_NS_REGION_3_LIMIT_ADDRESS & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Enable the SAU. */ + SAU->CTRL = SAU_CTRL_ENABLE_Msk; + + #if __ICACHE_PRESENT == 1U + + /* Cache maintenance is required when changing security attribution of an address. + * Barrier instructions are required to guarantee intended operation + * (See Arm Cortex-M85 Technical Reference Manual Section 10.9.3). */ + SCB_InvalidateICache(); + #endif + #else + + /* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the + * system. */ + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + #endif +} + +/*******************************************************************************************************************//** + * Initialize security features for TrustZone. + * + * This function initializes ARM security register and Renesas SAR registers for secure projects. + * + * @note IDAU settings must be configured to match project settings with a separate configuration tool. + **********************************************************************************************************************/ +void R_BSP_SecurityInit (void) +{ + /* Disable PRCR for SARs. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + #if 0 == BSP_FEATURE_TZ_HAS_DLM + + /* If DLM is not implemented, then the TrustZone partitions must be set at run-time. */ + R_PSCU->CFSAMONA = (uint32_t) FLASH_NS_START & ~BSP_FEATURE_TZ_NS_OFFSET & R_PSCU_CFSAMONA_CFS2_Msk; + R_PSCU->CFSAMONB = (uint32_t) FLASH_NSC_START & R_PSCU_CFSAMONB_CFS1_Msk; + R_PSCU->DFSAMON = (uint32_t) DATA_FLASH_NS_START & R_PSCU_DFSAMON_DFS_Msk; + R_PSCU->SSAMONA = (uint32_t) RAM_NS_START_S_ALIAS & R_PSCU_SSAMONA_SS2_Msk; + R_PSCU->SSAMONB = (uint32_t) RAM_NSC_START & R_PSCU_SSAMONB_SS1_Msk; + #endif + + #if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_ITCM) + + /* Total ITCM block size in bytes is equal to 2 ^ (BLKSZ + 5). */ + uint32_t itcm_block_exponent = + ((MEMSYSCTL->ITGU_CFG & MEMSYSCTL_ITGU_CFG_BLKSZ_Msk) >> MEMSYSCTL_ITGU_CFG_BLKSZ_Pos) + + 5U; + uint32_t itcm_block_size = (1U << itcm_block_exponent); + + /* The number of secure ITCM blocks is equal to size of the secure region in bytes divided by the ITCM block size. */ + uint32_t itcm_num_sec_blocks = + ((uint32_t) gp_ddsc_ITCM_END + itcm_block_size - 1 - (uint32_t) gp_ddsc_ITCM_START) >> + itcm_block_exponent; + + /* Set all secure blocks to '0' and all non-secure blocks to 1. */ + MEMSYSCTL->ITGU_LUT[0] = ~((1U << itcm_num_sec_blocks) - 1U); + #endif + + #if (BSP_CFG_CPU_CORE == 0) && (BSP_FEATURE_BSP_HAS_DTCM) + + /* Total DTCM block size in bytes is equal to 2 ^ (BLKSZ + 5). */ + uint32_t dtcm_block_exponent = + ((MEMSYSCTL->DTGU_CFG & MEMSYSCTL_DTGU_CFG_BLKSZ_Msk) >> MEMSYSCTL_DTGU_CFG_BLKSZ_Pos) + + 5U; + uint32_t dtcm_block_size = (1U << dtcm_block_exponent); + + /* The number of secure DTCM blocks is equal to size of the secure region in bytes divided by the DTCM block size. */ + uint32_t dtcm_num_sec_blocks = + ((uint32_t) gp_ddsc_DTCM_END + dtcm_block_size - 1 - (uint32_t) gp_ddsc_DTCM_START) >> + dtcm_block_exponent; + + /* Set all secure blocks to '0' and all non-secure blocks to 1. */ + MEMSYSCTL->DTGU_LUT[0] = ~((1U << dtcm_num_sec_blocks) - 1U); + #endif + + #if (BSP_CFG_CPU_CORE == 1) && defined(R_TCM) + #ifdef BSP_PARTITION_CTCM_CPU1_S_START + + /* Set boundary address for CTCM S/NS */ + R_CPSCU->TCMSABARC = BSP_PARTITION_CTCM_CPU1_S_START + BSP_PARTITION_CTCM_CPU1_S_SIZE; + #endif + #ifdef BSP_PARTITION_STCM_CPU1_S_START + + /* Set boundary address for STCM S/NS */ + R_CPSCU->TCMSABARS = BSP_PARTITION_STCM_CPU1_S_START + BSP_PARTITION_STCM_CPU1_S_SIZE; + #endif + #endif + + #if !BSP_SECONDARY_CORE_BUILD + + /* Skip SAU init on secondary build since it is being done earlier in system initialization. */ + R_BSP_SAUInit(); + #endif + + /* The following section of code to configure SCB->AIRCR, SCB->NSACR, and FPU->FPCCR is taken from + * system_ARMCM33.c in the CMSIS_5 repository. SCB->SCR SLEEPDEEPS bit is not configured because the + * SCB->SCR SLEEPDEEP bit is ignored on RA MCUs. */ + #if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + + /* Configure whether non-secure projects have access to system reset, whether bus fault, hard fault, and NMI target + * secure or non-secure, and whether non-secure interrupt priorities are reduced to the lowest 8 priority levels. */ + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) | + BSP_PRV_AIRCR_VECTKEY | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif + + #if defined(__FPU_USED) && (__FPU_USED == 1U) && \ + defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + /* Configure whether the FPU can be accessed in the non-secure project. */ + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + /* Configure whether FPU registers are always treated as non-secure (and therefore not preserved on the stack when + * switching from secure to non-secure), and whether the FPU registers should be cleared on exception return. */ + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); + #endif + + #if !BSP_SECONDARY_CORE_BUILD + #if BSP_FEATURE_TZ_HAS_TZFSAR + + /* Set TrustZone filter to Secure. */ + R_CPSCU->TZFSAR = ~R_CPSCU_TZFSAR_TZFSA0_Msk; + #endif + + /* Set TrustZone filter exception response. */ + BSP_PRV_OAD_PT_REG = BSP_PRV_TZ_REG_KEY + 1U; + BSP_PRV_OAD_REG = BSP_PRV_TZ_REG_KEY + BSP_TZ_CFG_EXCEPTION_RESPONSE; + BSP_PRV_OAD_PT_REG = BSP_PRV_TZ_REG_KEY + 0U; + #endif + + /* Initialize PSARs. */ + BSP_PRV_SAR_WRITE(R_PSCU->PSARB, BSP_TZ_CFG_PSARB); + BSP_PRV_SAR_WRITE(R_PSCU->PSARC, BSP_TZ_CFG_PSARC); + BSP_PRV_SAR_WRITE(R_PSCU->PSARD, BSP_TZ_CFG_PSARD); + BSP_PRV_SAR_WRITE(R_PSCU->PSARE, BSP_TZ_CFG_PSARE); + + #if !BSP_SECONDARY_CORE_BUILD + R_PSCU->MSSAR = BSP_TZ_CFG_MSSAR; + #endif + + /* Initialize Type 2 SARs. */ + #ifdef BSP_TZ_CFG_CSAR + R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_CACHESAR + R_CPSCU->CACHESAR = BSP_TZ_CFG_CACHESAR; /* Cache Security Attribution. */ + #endif + #if !BSP_SECONDARY_CORE_BUILD + R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */ + #endif + BSP_PRV_SAR_WRITE(R_SYSTEM->LVDSAR, BSP_TZ_CFG_LVDSAR); /* LVD Security Attribution. */ + + #if !BSP_SECONDARY_CORE_BUILD + R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */ + R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */ + #ifdef BSP_TZ_CFG_DPFSAR + R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_RSCSAR + R_SYSTEM->RSCSAR = BSP_TZ_CFG_RSCSAR; /* RAM Standby Control Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_PGCSAR + R_SYSTEM->PGCSAR = BSP_TZ_CFG_PGCSAR; /* Power Gating Control Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_BBFSAR + R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_VBRSABAR + R_SYSTEM->VBRSABAR = BSP_TZ_CFG_VBRSABAR; /* Battery Backup Security Attribution (VBTBKRn). */ + #endif + #endif + + BSP_PRV_SAR_WRITE(R_CPSCU->ICUSARA, BSP_TZ_CFG_ICUSARA); /* External IRQ Security Attribution. */ + BSP_PRV_SAR_WRITE(R_CPSCU->ICUSARB, BSP_TZ_CFG_ICUSARB); /* NMI Security Attribution. */ + + #if !BSP_SECONDARY_CORE_BUILD + #ifdef BSP_TZ_CFG_ICUSARC + R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */ + #endif + #endif + + #ifdef BSP_TZ_CFG_DMACCHSAR + R_CPSCU->DMACCHSAR |= (BSP_TZ_CFG_DMACCHSAR << DMACX_REGISTER_SHIFT); /* DMAC Channel Security Attribution. */ + #endif + + #if !BSP_SECONDARY_CORE_BUILD + #ifdef BSP_TZ_CFG_ICUSARD + R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */ + #endif + R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */ + #ifdef BSP_TZ_CFG_ICUSARF + R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_TEVTRCR + R_CPSCU->TEVTRCR = BSP_TZ_CFG_TEVTRCR; /* Trusted Event Route Enable. */ + #endif + #ifdef BSP_TZ_CFG_ELCSARA + R_ELC->ELCSARA = BSP_TZ_CFG_ELCSARA; /* ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_FSAR + R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */ + #endif + #ifdef BSP_TZ_CFG_MSAR + R_MRMS->MSAR = BSP_TZ_CFG_MSAR; /* MRAM Security Attribution. */ + #endif + + R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */ + #ifdef BSP_TZ_CFG_STBRAMSAR + R_CPSCU->STBRAMSAR = BSP_TZ_CFG_STBRAMSAR; /* Standby RAM Security Attribution. */ + #endif + #endif + + R_CPSCU->MMPUSARA |= (BSP_TZ_CFG_MMPUSARA << DMACX_REGISTER_SHIFT); /* Security Attribution for the DMAC Bus Master MPU. */ + + #if !BSP_SECONDARY_CORE_BUILD + R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */ + R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */ + #ifdef BSP_TZ_CFG_BUSSARC + R_CPSCU->BUSSARC = BSP_TZ_CFG_BUSSARC; /* Security Attribution Register C for the BUS Control Registers. */ + #endif + #endif + + #ifdef BSP_TZ_CFG_IPCSAR + BSP_PRV_SAR_WRITE(R_CPSCU->IPCSAR, BSP_TZ_CFG_IPCSAR); /* IPC Security Attribution */ + #endif + + #if (defined(BSP_TZ_CFG_ICUSARC) && (BSP_TZ_CFG_ICUSARC != UINT32_MAX)) || \ + (defined(BSP_TZ_CFG_DMACCHSAR) && \ + ((BSP_TZ_CFG_DMACCHSAR & R_CPSCU_DMACCHSAR_DMACCHSARn_Msk) != R_CPSCU_DMACCHSAR_DMACCHSARn_Msk)) + + R_BSP_MODULE_START(FSP_IP_DMAC, 0); + + #if BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DMAST security attribution is set to secure after reset. */ + #else + + /* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST + * in order to prevent the nonsecure program from disabling all DMAC channels. */ + R_CPSCU->DMACSAR &= ~(1U << DMACX_REGISTER_SHIFT); /* Protect DMAST from nonsecure write access. */ + #endif + + /* Ensure that DMAST is set so that the nonsecure program can use DMA. */ + R_DMA->DMAST = 1U; + #else + + /* On MCUs with this implementation of trustzone, DMACSAR security attribution is set to secure after reset. + * If the DMAC is not used in the secure application,then configure DMAST security attribution to non-secure. */ + R_CPSCU->DMACSAR = 1U; + #endif + + #if BSP_TZ_CFG_DTC_USED + R_BSP_MODULE_START(FSP_IP_DTC, 0); + + #if BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DTCST security attribution is set to secure after reset. */ + #else + + /* If the DTC is used by the secure program, disable nonsecure write access to DTCST + * in order to prevent the nonsecure program from disabling all DTC transfers. */ + R_CPSCU->DTCSAR &= ~(1U << DTCX_REGISTER_SHIFT); + #endif + + /* Ensure that DTCST is set so that the nonsecure program can use DTC. */ + R_DTC->DTCST = 1U; + #elif BSP_FEATURE_TZ_VERSION == 2 + + /* On MCUs with this implementation of trustzone, DTCST security attribution is set to secure after reset. + * If the DTC is not used in the secure application,then configure DTCST security attribution to non-secure. */ + R_CPSCU->DTCSAR |= (1U << DTCX_REGISTER_SHIFT); + #endif + + /* Initialize security attribution registers for Pins. */ + R_BSP_PinCfgSecurityInit(); + + /* Initialize security attribution registers for ELC. */ + R_BSP_ElcCfgSecurityInit(); + + /* Reenable PRCR for SARs. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_PinCfgSecurityInit (void) +{ +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_ElcCfgSecurityInit (void) +{ +} + + #endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_security.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_security.h new file mode 100644 index 0000000000..3ceb51f921 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_security.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_SECURITY_H +#define BSP_SECURITY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_tfu.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_tfu.h new file mode 100644 index 0000000000..98b09caee3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/all/bsp_tfu.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef RENESAS_TFU +#define RENESAS_TFU + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* Mathematical Functions includes. */ +#ifdef __cplusplus + #include +#else + #include +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#if BSP_FEATURE_TFU_SUPPORTED + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + + #define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f + + #ifdef __GNUC__ /* and (arm)clang */ + #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) + +/* No form of inline is available, it happens only when -std=c89, gnu89 and + * above are OK */ + #warning \ + "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" + #else + #ifdef __GNUC_GNU_INLINE__ + +/* gnu89 semantics of inline and extern inline are essentially the exact + * opposite of those in C99 */ + #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) + #else /* __GNUC_STDC_INLINE__ */ + #define BSP_TFU_INLINE static inline __attribute__((always_inline)) + #endif + #endif + #elif __ICCARM__ + #define BSP_TFU_INLINE + #else + #error "Compiler not supported!" + #endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Calculates sine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Sine value of an angle. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE float __sinf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + return R_TFU->SCDT1; +} + +/*******************************************************************************************************************//** + * Calculates cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Cosine value of an angle. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE float __cosf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read cos from R_TFU->SCDT1 */ + return R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates sine and cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * @param[out] sin Sine value of an angle. + * @param[out] cos Cosine value of an angle. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + *sin = R_TFU->SCDT1; + + /* Read sin from R_TFU->SCDT1 */ + *cos = R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-Axis cordinate value. + * @param[in] x_cord X-Axis cordinate value. + * + * @retval Arc tangent for given values. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) +{ + /* Set X-cordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-cordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + return R_TFU->ATDT1; +} + +/*******************************************************************************************************************//** + * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * + * @retval Hypotenuse for given values. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * @param[out] atan2 Arc tangent for given values. + * @param[out] hypot Hypotenuse for given values. + **********************************************************************************************************************/ + #if __ICCARM__ + #pragma inline = forced + #endif +BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + *atan2 = R_TFU->ATDT1; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + + #if BSP_CFG_USE_TFU_MATHLIB + #define sinf(x) __sinf(x) + #define cosf(x) __cosf(x) + #define atan2f(y, x) __atan2f(y, x) + #define hypotf(x, y) __hypotf(x, y) + #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) + #define sincosf(a, s, c) __sincosf(a, s, c) + #endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* RENESAS_TFU */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/RA4E1.ld b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/RA4E1.ld new file mode 100644 index 0000000000..8c85d5b587 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/RA4E1.ld @@ -0,0 +1,487 @@ +RAM_START = 0x20000000; +RAM_LENGTH = 0x00020000; +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x00080000; +DATA_FLASH_START = 0x08000000; +DATA_FLASH_LENGTH = 0x00002000; +QSPI_FLASH_START = 0x60000000; +QSPI_FLASH_LENGTH = 0x04000000; +OPTION_SETTING_OFS0_START = 0x0100a100; +OPTION_SETTING_OFS0_LENGTH = 0x00000004; +OPTION_SETTING_OFS1_START = 0x0100a180; +OPTION_SETTING_OFS1_LENGTH = 0x00000004; +OPTION_SETTING_BPS_START = 0x0100a1c0; +OPTION_SETTING_BPS_LENGTH = 0x00000004; +OPTION_SETTING_PBPS_START = 0x0100a1e0; +OPTION_SETTING_PBPS_LENGTH = 0x00000004; +OPTION_SETTING_OFS1_SEC_START = 0x0100a200; +OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; +OPTION_SETTING_BPS_SEC_START = 0x0100a240; +OPTION_SETTING_BPS_SEC_LENGTH = 0x00000004; +OPTION_SETTING_PBPS_SEC_START = 0x0100a260; +OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000004; +OPTION_SETTING_OFS1_SEL_START = 0x0100a280; +OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; +OPTION_SETTING_BPS_SEL_START = 0x0100a2c0; +OPTION_SETTING_BPS_SEL_LENGTH = 0x00000004; +__vector_table_size__ = 112 * 4; + +MEMORY +{ + RAM (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_SRAM1_START, LENGTH = MBED_CONFIGURED_RAM_BANK_SRAM1_SIZE + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_Flash_START, LENGTH = MBED_CONFIGURED_ROM_BANK_Flash_SIZE + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH +} + +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + + +SECTIONS +{ + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + /* Stick the vector table at start of SRAM */ + .vector_ram (NOLOAD) : + { + __vector_ram_start__ = .; + . += __vector_table_size__; + __vector_ram_end__ = .; + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + .text (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + + .text (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* .ARM.extab sections contain exception unwinding information. */ + __flash_arm.extab$$ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + } > FLASH + /* .ARM.exidx sections contains index entries for section unwinding. */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + __exidx_end = . ; + } > FLASH + + __etext = .; + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + .data : + { + __data_start__ = .; + _sdata = .; + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(.data) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + __ram_from_flash$$Limit = . ; + __data_end__ = .; + _edata = .; + } > RAM AT > FLASH + /* Non-initialized ram */ + .bss (NOLOAD) : + { + __bss_start__ = .; + _sbss = .; + __ram_noinit$$Base = . ; + /* Main stack region */ + __StackLimit = .; + *(.bss.g_main_stack) + __StackTop = .; + _estack = __StackTop; + PROVIDE(__stack = __StackTop); + /* Other no-init data */ + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + __bss_end__ = .; + _ebss = .; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,512) : + { + __ddsc_RAM_END = . ; + /* Heap region */ + __HeapBase = .; + __end__ = .; + PROVIDE(end = .); + *(.bss.g_heap) + __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); + } > RAM + + .flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Security Attribution */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Security Attribution */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL + +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h new file mode 100644 index 0000000000..a009fc2fff --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_elc.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA4E1 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* UNCRUSTIFY-OFF */ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list is device specific. + * */ +typedef enum e_elc_event_ra4e1 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x0A1), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x0A2), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x0A3), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x0A4), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x0A5), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Receive data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Receive data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB) // Data operation circuit interrupt +} elc_event_t; + +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) + +#define ELC_PERIPHERAL_NUM (18U) +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +/** Possible peripherals to be linked to event signals + * @note This list is device specific. + * */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17) +} elc_peripheral_t; + +/** Positions of event link set registers (ELSRs) available on this MCU */ +#define BSP_ELC_PERIPHERAL_MASK (0x0003D3FFU) + +/* UNCRUSTIFY-ON */ +/** @} (end addtogroup BSP_MCU_RA4E1) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h new file mode 100644 index 0000000000..c187dfc10c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h @@ -0,0 +1,629 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_peripheral.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#if (BSP_CFG_XTAL_HZ >= (20000000)) + #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (16000000)) + #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (8000000)) + #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#else + #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#endif + +// *UNCRUSTIFY-OFF* + +#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_NONE) // Feature not available on this device. + +#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. +#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. +#define BSP_FEATURE_ADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the ADC. +#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. +#define BSP_FEATURE_ADC_TSN_SLOPE (0UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK (0x0001381FUL) // Mask of available channels in ADC unit 0. +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK (0x00UL) // Mask of available channels in ADC unit 1. +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x01UL) // Mask of whole, physical ADC units present in the MCU. + +#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS_MASK (0x00ULL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS_MASK (0x00ULL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_D_CHANNELS_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_IS_ADC12 (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (6U) // Number of channels for only AGT (not AGTW) peripherals. +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x2FUL) // A mask of all valid AGTx channels. + +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. +#define BSP_FEATURE_BSP_HAS_DSMIF_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. +#define BSP_FEATURE_BSP_HAS_ESC_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. +#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. +#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. +#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. +#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. +#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. +#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. +#define BSP_FEATURE_BSP_NUM_PMSAR (6UL) // Number of available Port Security Attribution Registers. +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. +#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. +#define BSP_FEATURE_BSP_PART_NUMBER_OFFSET (0x00UL) // Bit offset of the Part Number in the mcu info block. +#define BSP_FEATURE_BSP_PART_NUMBER_POINTER (0x010080F0UL) // Address of the Part Numbering register (PNR). +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. +#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. + +#define BSP_FEATURE_CAN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG (0UL) // Flag indicating that the ratio between PCLKA (or ICLK) and PCLKB must be 2:1 during CAN operation. +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Source clock for the CAN peripheral. +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Indicates that the only clock source for can is the CANMCLK. +#define BSP_FEATURE_CAN_NUM_CHANNELS (1UL) // Number of CAN peripherals. + +#define BSP_FEATURE_CANFD_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CANFD_FD_SUPPORT (0) // Feature not available on this device. +#define BSP_FEATURE_CANFD_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_LITE (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CEC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CEC_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. +#define BSP_FEATURE_CGC_HAS_BCLK (0UL) // External Bus Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK1 (0UL) // CPU1 Clock is available. +#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. +#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. +#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. +#define BSP_FEATURE_CGC_HAS_MOCO (1UL) // Middle clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MOSC (1UL) // Main clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MRICLK (0UL) // MRAM bus clock is available. +#define BSP_FEATURE_CGC_HAS_NPUCLK (0UL) // NPU clock is available. +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. +#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. +#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. +#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. +#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. +#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. +#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. +#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. +#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. +#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1UL) // SRAMPRCR2 register is available. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. +#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ (24000000UL) // Maximum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ (8000000UL) // Minimum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ (0UL) // Maximum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ (0UL) // Minimum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000UL) // Maximum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000UL) // Minimum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. +#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL2. +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0UL) // PLL VCO maximum frequency. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. +#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIVCR.PCLKB. +#define BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK (0UL) // Requires the SCKDIVCR2.CPUCLK1 bits to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. +#define BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK (0UL) // Requires the bits [11:8] to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. +#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222UL) // Reset value for the SCKDIVCR register. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. + +#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. +#define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. +#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. + +#define BSP_FEATURE_CTSU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x01UL) // DAADSCR register is available. +#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. +#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. +#define BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL (0UL) // DAC output can be routed to specific extra internal modules using DAASWCR register. +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. + +#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (1UL) // Number of available channels per DAC12 instance. +#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. + +#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). +#define BSP_FEATURE_DMAC_NUM_CHANNELS (8UL) // Number of DMAC channels available. + +#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. + +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. + +#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. + +#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. + +#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESC_NUM_PORTS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ESWM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_FRER_TABLE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_TIMER_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GWCA_PORT (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_DOMAIN (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ETHER_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Feature not available on this device. + +#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. +#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. +#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. +#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. +#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. +#define BSP_FEATURE_FLASH_CACHE (1UL) // Flash cache is present. +#define BSP_FEATURE_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. +#define BSP_FEATURE_FLASH_CODE_CACHE_VERSION (0UL) // Version of C-Cache implemented in a CM33 core. +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. +#define BSP_FEATURE_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). +#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. + +#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00UL) // Start of the second code flash bank. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. +#define BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE (0UL) // Constraints exist for flash cache operation during flash programming access. +#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (0UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0UL) // Device contains two code banks. +#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. + +#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x06UL) // Mask of 32-bit GPT channel indices. +#define BSP_FEATURE_GPT_AD_CONVERSION_START_CHANNEL_MASK (0x00UL) // Mask of GPT channels supporting A/D conversion start. +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // GPT A/D conversion start request is directly output to ADC instead of via the ELC. +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x36UL) // Mask of channels that support event count input (has GTUPSR register). +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. +#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available, GPTE implementations have a GTITC register. +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available, GPTEH implementations have a PDG module. +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x36UL) // Mask of channels that support dead time control. +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. +#define BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. +#define BSP_FEATURE_GPT_MSTP_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. +#define BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x00UL) // Mask of channels supporting output phase switching. +#define BSP_FEATURE_GPT_OPS_SUPPORTED (0UL) // At least one GPT channel with OPS support is available. +#define BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED (0UL) // At least one GPT channel supports polarity inversion of the GTIOCnA or GTIOCnB I/O pins. +#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. + +#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) +#define BSP_FEATURE_I3C_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. +#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. +#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. +#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x23FFUL) // Mask of available IRQ control registers. +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (13UL) // Maximum bit field index of valid fields of the NMIER register. +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. +#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000007FB0D23FFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. + +#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER (0UL) // Multiplication factor to calculate SDA bus free time. +#define BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA (0UL) // SCL status needs to be checked before writing the transmission data in master mode. +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. +#define BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_HAS_CLOCK (0UL) // Indicates there is a separate IIC clock. +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x01UL) // Mask of available IIC channels. + +#define BSP_FEATURE_IOPORT_CCD_PINS_MASK (0x00UL) // Mask of valid indices for CCD pins. +#define BSP_FEATURE_IOPORT_ELC_PORTS_MASK (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. +#define BSP_FEATURE_IOPORT_HAS_LVOCR (0UL) // The LVOCR register is available. +#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. + +#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. + +#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. + +#define BSP_FEATURE_LCD_HAS_CLOCK (0UL) // Indicates there is a separate clock for the LCD. + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x001303F3ULL) // Mask of valid bit-fields of the DPSIEGRn registers. +#define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1F03F3ULL) // Mask of valid bit-fields of the DPSIERn registers. +#define BSP_FEATURE_LPM_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE (0UL) // The DPSBYCR.DCSSMODE field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. +#define BSP_FEATURE_LPM_HAS_LDO_SKEEP (0UL) // PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers are available. +#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0UL) // The SBYCR.OPE field is available. +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. +#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1UL) // The SNZEDCR1 register is available. +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1UL) // The SNZREQCR1 register is available. +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. +#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1UL) // Indicates that bit 14 of the SBYCR register should always be set. +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x019FUL) // Mask of valid bits for the SNZEDCRn registers. +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x00000007730023FFULL) // Mask of valid bits for the SNZREQCRn registers. +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. + +#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. +#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage low threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage low threshold. +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. +#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. +#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. +#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. + +#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. + +#define BSP_FEATURE_MIPI_CSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_DSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_PHY_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MRAM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_B_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. +#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. +#define BSP_FEATURE_POEG_MSTP_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. + +#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. + +#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. +#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. +#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E11A. +#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E31A. +#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP-E50D. +#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E51A. +#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. +#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. +#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. +#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (1UL) // The device supports cryptography using SCE9. +#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_RTC_HAS_ALARM1 (0UL) // Alarm 1 is available. +#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. +#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. +#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. +#define BSP_FEATURE_RTC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. +#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (1UL) // Number of RTCCRn registers that are available. + +#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK (0x0219UL) // Mask of channels with data compare match (DCCR) available. +#define BSP_FEATURE_SCI_CHANNELS_MASK (0x0219UL) // Mask of available SCI channels. +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. +#define BSP_FEATURE_SCI_HAS_CLOCK (0UL) // Indicates there is a separate SCI clock. +#define BSP_FEATURE_SCI_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. +#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. +#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. +#define BSP_FEATURE_SCI_LIN_CHANNELS_MASK (0x00UL) // Mask of channels that can support LIN. +#define BSP_FEATURE_SCI_SPI_SCKSEL_MASK (0UL) // Mask indicating CCR4.SCKSEL is available. +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK (0x06UL) // List of channels that do not support ABCSE functionality. +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK (0x0219UL) // Mask of channels which support CTS external pins. +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK (0x0219UL) // Mask of channels which support the UART FIFO. +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. +#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. + +#define BSP_FEATURE_SDADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. + +#define BSP_FEATURE_SDHI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. + +#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED (1UL) // Burst transfer without delay between frames is supported. +#define BSP_FEATURE_SPI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. +#define BSP_FEATURE_SPI_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SPI. +#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. +#define BSP_FEATURE_SPI_NUM_CHANNELS (1UL) // Number of available SPI channels. +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x01UL) // Mask of channel indices that support SSL Level Keep. + +#define BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR (0UL) // Flag indicating that SRAMSABAR2 and SRAMSABAR3 are present. +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. + +#define BSP_FEATURE_SSI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0UL) // Feature not available on this device. +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS (50000000UL) // Maximum frequency allowed before requiring one wait cycle. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring three wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS (0UL) // Maximum frequency allowed before requiring two wait cycles. + +#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. + +#define BSP_FEATURE_TSN_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TSN_CALIBRATION_AVAILABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_TSN_CALIBRATION32_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_TSN_CONTROL_AVAILABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_TSN_HAS_LOW_TEMP_REG (0UL) // Feature not available on this device. +#define BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG (0UL) // Feature not available on this device. +#define BSP_FEATURE_TSN_SLOPE (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. +#define BSP_FEATURE_TZ_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. +#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. +#define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. + +#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ULPT_NUM_CHANNELS_AVAILABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) +#define BSP_FEATURE_USB_HAS_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. +#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. +#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. +#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. +#define BSP_FEATURE_USB_HAS_USB60_CLOCK (0UL) // Indicates the USB60 clock is available. +#define BSP_FEATURE_USB_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. +#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. +#define BSP_FEATURE_USB_HAS_USBFS_BC (1UL) // Supports battery charging in full-speed mode. +#define BSP_FEATURE_USB_HAS_USBHS (0UL) // Supports USB 2.0 High-Speed mode. +#define BSP_FEATURE_USB_HAS_USBHS_BC (0UL) // Supports battery charging in high-speed mode. +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1UL) // Indicates the PHYSECTRL.CNEN field is available. +#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. +#define BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR2 register. + +#define BSP_FEATURE_VIN_IS_AVAILABLE (0UL) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_linker.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_linker.c new file mode 100644 index 0000000000..1c7a82ffdb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_linker.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#if defined BSP_CFG_OPTION_SETTING_OFS0 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_cfg_option_setting_ofs0[] = {BSP_CFG_OPTION_SETTING_OFS0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1 +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_cfg_option_setting_ofs1[] = {BSP_CFG_OPTION_SETTING_OFS1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps") g_bsp_cfg_option_setting_bps[] = {BSP_CFG_OPTION_SETTING_BPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps") g_bsp_cfg_option_setting_pbps[] = {BSP_CFG_OPTION_SETTING_PBPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_cfg_option_setting_ofs1_sec[] = {BSP_CFG_OPTION_SETTING_OFS1_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec") g_bsp_cfg_option_setting_bps_sec[] = {BSP_CFG_OPTION_SETTING_BPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec") g_bsp_cfg_option_setting_pbps_sec[] = {BSP_CFG_OPTION_SETTING_PBPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_cfg_option_setting_ofs1_sel[] = {BSP_CFG_OPTION_SETTING_OFS1_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel") g_bsp_cfg_option_setting_bps_sel[] = {BSP_CFG_OPTION_SETTING_BPS_SEL}; +#endif +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_linker_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_linker_info.h new file mode 100644 index 0000000000..2ff0a8fae7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_linker_info.h @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/* UNCRUSTIFY-OFF */ +#ifndef BSP_LINKER_H + #define BSP_LINKER_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/******* Solution Definitions *************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +/* linker generated initialization table data structures types */ +typedef enum e_bsp_init_mem +{ + INIT_MEM_ZERO, + INIT_MEM_FLASH, + INIT_MEM_DATA_FLASH, + INIT_MEM_RAM, + INIT_MEM_DTCM, + INIT_MEM_ITCM, + INIT_MEM_CTCM, + INIT_MEM_STCM, + INIT_MEM_OSPI0_CS0, + INIT_MEM_OSPI0_CS1, + INIT_MEM_OSPI1_CS0, + INIT_MEM_OSPI1_CS1, + INIT_MEM_QSPI_FLASH, + INIT_MEM_SDRAM, + INIT_MEM_SIP_FLASH, +} bsp_init_mem_t; + +typedef struct st_bsp_init_type +{ + uint32_t copy_64 : 8; /* if 1, must use 64 bit copy operation (to keep ecc happy) */ + uint32_t external : 8; /* =1 if either source or destination is external, else 0 */ + uint32_t source_type : 8; + uint32_t destination_type : 8; +} bsp_init_type_t; + +typedef struct st_bsp_init_zero_info +{ + uint32_t * const p_base; + uint32_t * const p_limit; + bsp_init_type_t type; +} bsp_init_zero_info_t; + +typedef struct st_bsp_init_copy_info +{ + uint32_t * const p_base; + uint32_t * const p_limit; + uint32_t * const p_load; + bsp_init_type_t type; +} bsp_init_copy_info_t; + +typedef struct st_bsp_init_info +{ + uint32_t zero_count; + bsp_init_zero_info_t const * const p_zero_list; + uint32_t copy_count; + bsp_init_copy_info_t const * const p_copy_list; +} bsp_init_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern bsp_init_info_t const g_init_info; +/* These symbols are used for sau/idau configuration in a secure project */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#endif // BSP_LINKER_H +#ifdef BSP_LINKER_C +/*********************************************************************************************************************** + * Objects allocated by bsp_linker.c + **********************************************************************************************************************/ +/* DDSC symbol definitions */ +/* Zero initialization tables */ +extern uint32_t __ram_zero$$Base; +extern uint32_t __ram_zero$$Limit; +static const bsp_init_zero_info_t zero_list[] = +{ + {.p_base = &__ram_zero$$Base, .p_limit = &__ram_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}} +}; +/* Load initialization tables */ +extern uint32_t __ram_from_qspi_flash$$Base; +extern uint32_t __ram_from_qspi_flash$$Limit; +extern uint32_t __ram_from_qspi_flash$$Load; +extern uint32_t __ram_from_data_flash$$Base; +extern uint32_t __ram_from_data_flash$$Limit; +extern uint32_t __ram_from_data_flash$$Load; +extern uint32_t __ram_from_flash$$Base; +extern uint32_t __ram_from_flash$$Limit; +extern uint32_t __ram_from_flash$$Load; +static const bsp_init_copy_info_t copy_list[] = +{ + //{.p_base = &__ram_from_qspi_flash$$Base, .p_limit = &__ram_from_qspi_flash$$Limit, .p_load = &__ram_from_qspi_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_QSPI_FLASH, .destination_type = INIT_MEM_RAM}}, + //{.p_base = &__ram_from_data_flash$$Base, .p_limit = &__ram_from_data_flash$$Limit, .p_load = &__ram_from_data_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_from_flash$$Base, .p_limit = &__ram_from_flash$$Limit, .p_load = &__ram_from_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_RAM}} +}; + +/* initialization data structure */ +const bsp_init_info_t g_init_info = +{ + .zero_count = sizeof(zero_list) / sizeof(zero_list[0]), + .p_zero_list = zero_list, + .copy_count = sizeof(copy_list) / sizeof(copy_list[0]), + .p_copy_list = copy_list +}; + +#endif // BSP_LINKER_C + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_mcu_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_mcu_info.h new file mode 100644 index 0000000000..14a2f0a0c2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_mcu_info.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA4E1 RA4E1 + * @includedoc config_bsp_ra4e1_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA4E1) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_peripheral.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_peripheral.h new file mode 100644 index 0000000000..657dff17c4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4e1/bsp_peripheral.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_PERIPHERAL_H +#define BSP_PERIPHERAL_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// *UNCRUSTIFY-OFF* + +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x2FU) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DAC_B_PRESENT (0) +#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ESWM_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x36U) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x23FFU) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IPC_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_CSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_PHY_PRESENT (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MRMS_PRESENT (0) +#define BSP_PERIPHERAL_MRRGE_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_NPU_PRESENT (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDM_PRESENT (0) +#define BSP_PERIPHERAL_PDM_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x3FU) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RSIP_PRESENT (1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x219U) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSN_PRESENT (0) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_USBCC_PRESENT (0) +#define BSP_PERIPHERAL_VIN_PRESENT (0) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h new file mode 100644 index 0000000000..db5b3af5c3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_elc.h @@ -0,0 +1,315 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA4M3 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* UNCRUSTIFY-OFF */ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list is device specific. + * */ +typedef enum e_elc_event_ra4m3 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x0A1), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x0A2), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x0A3), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x0A4), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x0A5), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x0A6), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x0A7), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x0A8), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x0A9), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x0AA), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x186), // Receive data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Receive data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Receive data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCI1_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCI1_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCI1_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCI1_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCI2_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCI2_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCI2_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SCI2_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt + ELC_EVENT_SCE_TADI = (0x1E9) // SCE Tamper Detection +} elc_event_t; + +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) + +#define ELC_PERIPHERAL_NUM (19U) +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +/** Possible peripherals to be linked to event signals + * @note This list is device specific. + * */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_ADC1 = (10), + ELC_PERIPHERAL_ADC1_B = (11), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_CTSU = (18) +} elc_peripheral_t; + +/** Positions of event link set registers (ELSRs) available on this MCU */ +#define BSP_ELC_PERIPHERAL_MASK (0x0007FFFFU) + +/* UNCRUSTIFY-ON */ +/** @} (end addtogroup BSP_MCU_RA4M3) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h new file mode 100644 index 0000000000..c425853491 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h @@ -0,0 +1,629 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_peripheral.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#if (BSP_CFG_XTAL_HZ >= (20000000)) + #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (16000000)) + #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (8000000)) + #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#else + #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#endif + +// *UNCRUSTIFY-OFF* + +#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_NONE) // Feature not available on this device. + +#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. +#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. +#define BSP_FEATURE_ADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the ADC. +#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. +#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK (0x33FFUL) // Mask of available channels in ADC unit 0. +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK (0x007F0007UL) // Mask of available channels in ADC unit 1. +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. + +#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS_MASK (0x00ULL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS_MASK (0x00ULL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_D_CHANNELS_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_IS_ADC12 (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (6U) // Number of channels for only AGT (not AGTW) peripherals. +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3FUL) // A mask of all valid AGTx channels. + +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. +#define BSP_FEATURE_BSP_HAS_DSMIF_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. +#define BSP_FEATURE_BSP_HAS_ESC_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. +#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. +#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. +#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. +#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. +#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. +#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. +#define BSP_FEATURE_BSP_NUM_PMSAR (9UL) // Number of available Port Security Attribution Registers. +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. +#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. +#define BSP_FEATURE_BSP_PART_NUMBER_OFFSET (0x00UL) // Bit offset of the Part Number in the mcu info block. +#define BSP_FEATURE_BSP_PART_NUMBER_POINTER (0x010080F0UL) // Address of the Part Numbering register (PNR). +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. +#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. + +#define BSP_FEATURE_CAN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG (0UL) // Flag indicating that the ratio between PCLKA (or ICLK) and PCLKB must be 2:1 during CAN operation. +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Source clock for the CAN peripheral. +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Indicates that the only clock source for can is the CANMCLK. +#define BSP_FEATURE_CAN_NUM_CHANNELS (2UL) // Number of CAN peripherals. + +#define BSP_FEATURE_CANFD_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CANFD_FD_SUPPORT (0) // Feature not available on this device. +#define BSP_FEATURE_CANFD_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_LITE (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CEC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CEC_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. +#define BSP_FEATURE_CGC_HAS_BCLK (0UL) // External Bus Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK1 (0UL) // CPU1 Clock is available. +#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. +#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. +#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. +#define BSP_FEATURE_CGC_HAS_MOCO (1UL) // Middle clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MOSC (1UL) // Main clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MRICLK (0UL) // MRAM bus clock is available. +#define BSP_FEATURE_CGC_HAS_NPUCLK (0UL) // NPU clock is available. +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. +#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. +#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. +#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. +#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. +#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. +#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. +#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. +#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. +#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1UL) // SRAMPRCR2 register is available. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. +#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ (24000000UL) // Maximum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ (8000000UL) // Minimum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ (0UL) // Maximum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ (0UL) // Minimum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (200000000UL) // Maximum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (100000000UL) // Minimum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. +#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL2. +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0UL) // PLL VCO maximum frequency. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. +#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIVCR.PCLKB. +#define BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK (0UL) // Requires the SCKDIVCR2.CPUCLK1 bits to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. +#define BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK (0UL) // Requires the bits [11:8] to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. +#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222UL) // Reset value for the SCKDIVCR register. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. + +#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. +#define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. +#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. + +#define BSP_FEATURE_CTSU_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3UL) // Number of CTSUCHAC registers. +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3UL) // Number of CTSUCHTRC registers. +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1UL) // CTSUCR0.CTSUTXVSEL field is available. +#define BSP_FEATURE_CTSU_VERSION (1UL) // Version of the CTSU peripheral. + +#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. +#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. +#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. +#define BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL (0UL) // DAC output can be routed to specific extra internal modules using DAASWCR register. +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. + +#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. +#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. + +#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). +#define BSP_FEATURE_DMAC_NUM_CHANNELS (8UL) // Number of DMAC channels available. + +#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. + +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. + +#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. + +#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. + +#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESC_NUM_PORTS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ESWM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_FRER_TABLE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_TIMER_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GWCA_PORT (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_DOMAIN (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ETHER_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Feature not available on this device. + +#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. +#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. +#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. +#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. +#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. +#define BSP_FEATURE_FLASH_CACHE (1UL) // Flash cache is present. +#define BSP_FEATURE_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. +#define BSP_FEATURE_FLASH_CODE_CACHE_VERSION (1UL) // Version of C-Cache implemented in a CM33 core. +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. +#define BSP_FEATURE_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). +#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. + +#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00UL) // Start of the second code flash bank. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. +#define BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE (0UL) // Constraints exist for flash cache operation during flash programming access. +#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0UL) // Device contains two code banks. +#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. + +#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FUL) // Mask of 32-bit GPT channel indices. +#define BSP_FEATURE_GPT_AD_CONVERSION_START_CHANNEL_MASK (0x00UL) // Mask of GPT channels supporting A/D conversion start. +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // GPT A/D conversion start request is directly output to ADC instead of via the ELC. +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0xFFUL) // Mask of channels that support event count input (has GTUPSR register). +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. +#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available, GPTE implementations have a GTITC register. +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available, GPTEH implementations have a PDG module. +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0xFFUL) // Mask of channels that support dead time control. +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. +#define BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. +#define BSP_FEATURE_GPT_MSTP_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. +#define BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. +#define BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED (0UL) // At least one GPT channel supports polarity inversion of the GTIOCnA or GTIOCnB I/O pins. +#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. + +#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) +#define BSP_FEATURE_I3C_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. +#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. +#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. +#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. +#define BSP_FEATURE_ICU_WUPEN_MASK (0x00000007FB0DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. + +#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER (0UL) // Multiplication factor to calculate SDA bus free time. +#define BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA (0UL) // SCL status needs to be checked before writing the transmission data in master mode. +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. +#define BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_HAS_CLOCK (0UL) // Indicates there is a separate IIC clock. +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03UL) // Mask of available IIC channels. + +#define BSP_FEATURE_IOPORT_CCD_PINS_MASK (0x00UL) // Mask of valid indices for CCD pins. +#define BSP_FEATURE_IOPORT_ELC_PORTS_MASK (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. +#define BSP_FEATURE_IOPORT_HAS_LVOCR (0UL) // The LVOCR register is available. +#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. + +#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. + +#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. + +#define BSP_FEATURE_LCD_HAS_CLOCK (0UL) // Indicates there is a separate clock for the LCD. + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x0013FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. +#define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. +#define BSP_FEATURE_LPM_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE (0UL) // The DPSBYCR.DCSSMODE field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. +#define BSP_FEATURE_LPM_HAS_LDO_SKEEP (0UL) // PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers are available. +#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0UL) // The SBYCR.OPE field is available. +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. +#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1UL) // The SNZEDCR1 register is available. +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1UL) // The SNZREQCR1 register is available. +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. +#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x01FFUL) // Mask of valid bits for the SNZEDCRn registers. +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x000000077300FFFFULL) // Mask of valid bits for the SNZREQCRn registers. +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. + +#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. +#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage low threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage low threshold. +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. +#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. +#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. +#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. + +#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. + +#define BSP_FEATURE_MIPI_CSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_DSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_PHY_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MRAM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_B_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. +#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. +#define BSP_FEATURE_POEG_MSTP_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. + +#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. + +#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. +#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. +#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E11A. +#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E31A. +#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP-E50D. +#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E51A. +#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. +#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. +#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. +#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (1UL) // The device supports cryptography using SCE9. +#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_RTC_HAS_ALARM1 (0UL) // Alarm 1 is available. +#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. +#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. +#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. +#define BSP_FEATURE_RTC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. +#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. + +#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK (0x0219UL) // Mask of channels with data compare match (DCCR) available. +#define BSP_FEATURE_SCI_CHANNELS_MASK (0x021FUL) // Mask of available SCI channels. +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. +#define BSP_FEATURE_SCI_HAS_CLOCK (0UL) // Indicates there is a separate SCI clock. +#define BSP_FEATURE_SCI_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. +#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. +#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. +#define BSP_FEATURE_SCI_LIN_CHANNELS_MASK (0x06UL) // Mask of channels that can support LIN. +#define BSP_FEATURE_SCI_SPI_SCKSEL_MASK (0UL) // Mask indicating CCR4.SCKSEL is available. +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK (0x06UL) // List of channels that do not support ABCSE functionality. +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK (0x0219UL) // Mask of channels which support CTS external pins. +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK (0x0219UL) // Mask of channels which support the UART FIFO. +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. +#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. + +#define BSP_FEATURE_SDADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. + +#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01UL) // Mask of valid SDHI channels. + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. + +#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED (1UL) // Burst transfer without delay between frames is supported. +#define BSP_FEATURE_SPI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. +#define BSP_FEATURE_SPI_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SPI. +#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. +#define BSP_FEATURE_SPI_NUM_CHANNELS (1UL) // Number of available SPI channels. +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x01UL) // Mask of channel indices that support SSL Level Keep. + +#define BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR (0UL) // Flag indicating that SRAMSABAR2 and SRAMSABAR3 are present. +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. + +#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1UL) // Mask of valid SSI channel indices. + +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS (50000000UL) // Maximum frequency allowed before requiring one wait cycle. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring three wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS (0UL) // Maximum frequency allowed before requiring two wait cycles. + +#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. + +#define BSP_FEATURE_TSN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. +#define BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available for TSN. +#define BSP_FEATURE_TSN_CALIBRATION32_MASK (0xFFFFUL) // Mask of valid bits for TSN calibration. +#define BSP_FEATURE_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. +#define BSP_FEATURE_TSN_HAS_LOW_TEMP_REG (0UL) // Determine if the TSCDRL (Low Temperature) is present. +#define BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG (0UL) // Determine if the TSCDRR (Room Temperature) is present. +#define BSP_FEATURE_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. + +#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. +#define BSP_FEATURE_TZ_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. +#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. +#define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. + +#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ULPT_NUM_CHANNELS_AVAILABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) +#define BSP_FEATURE_USB_HAS_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. +#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. +#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. +#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. +#define BSP_FEATURE_USB_HAS_USB60_CLOCK (0UL) // Indicates the USB60 clock is available. +#define BSP_FEATURE_USB_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. +#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. +#define BSP_FEATURE_USB_HAS_USBFS_BC (1UL) // Supports battery charging in full-speed mode. +#define BSP_FEATURE_USB_HAS_USBHS (0UL) // Supports USB 2.0 High-Speed mode. +#define BSP_FEATURE_USB_HAS_USBHS_BC (0UL) // Supports battery charging in high-speed mode. +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1UL) // Indicates the PHYSECTRL.CNEN field is available. +#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. +#define BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR2 register. + +#define BSP_FEATURE_VIN_IS_AVAILABLE (0UL) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_linker.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_linker.c new file mode 100644 index 0000000000..0f7352609b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_linker.c @@ -0,0 +1,57 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#if defined BSP_CFG_OPTION_SETTING_OFS0 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_cfg_option_setting_ofs0[] = {BSP_CFG_OPTION_SETTING_OFS0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1 +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_cfg_option_setting_ofs1[] = {BSP_CFG_OPTION_SETTING_OFS1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel") g_bsp_cfg_option_setting_banksel[] = {BSP_CFG_OPTION_SETTING_BANKSEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps") g_bsp_cfg_option_setting_bps[] = {BSP_CFG_OPTION_SETTING_BPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps") g_bsp_cfg_option_setting_pbps[] = {BSP_CFG_OPTION_SETTING_PBPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_cfg_option_setting_ofs1_sec[] = {BSP_CFG_OPTION_SETTING_OFS1_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sec") g_bsp_cfg_option_setting_banksel_sec[] = {BSP_CFG_OPTION_SETTING_BANKSEL_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec") g_bsp_cfg_option_setting_bps_sec[] = {BSP_CFG_OPTION_SETTING_BPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec") g_bsp_cfg_option_setting_pbps_sec[] = {BSP_CFG_OPTION_SETTING_PBPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_cfg_option_setting_ofs1_sel[] = {BSP_CFG_OPTION_SETTING_OFS1_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_cfg_option_setting_banksel_sel[] = {BSP_CFG_OPTION_SETTING_BANKSEL_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel") g_bsp_cfg_option_setting_bps_sel[] = {BSP_CFG_OPTION_SETTING_BPS_SEL}; +#endif +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h new file mode 100644 index 0000000000..8ee635235a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA4M3 RA4M3 + * @includedoc config_bsp_ra4m3_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA4M3) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_peripheral.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_peripheral.h new file mode 100644 index 0000000000..f0b4c2caec --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra4m3/bsp_peripheral.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_PERIPHERAL_H +#define BSP_PERIPHERAL_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// *UNCRUSTIFY-OFF* + +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3FU) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DAC_B_PRESENT (0) +#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ESWM_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IPC_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_CSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_PHY_PRESENT (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MRMS_PRESENT (0) +#define BSP_PERIPHERAL_MRRGE_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_NPU_PRESENT (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDM_PRESENT (0) +#define BSP_PERIPHERAL_PDM_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x1FFU) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RSIP_PRESENT (1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x21FU) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_USBCC_PRESENT (0) +#define BSP_PERIPHERAL_VIN_PRESENT (0) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/RA6E2.ld b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/RA6E2.ld new file mode 100644 index 0000000000..8f9338020d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/RA6E2.ld @@ -0,0 +1,415 @@ +RAM_START = 0x20000000; +RAM_LENGTH = 0x0000a000; +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x00040000; +DATA_FLASH_START = 0x08000000; +DATA_FLASH_LENGTH = 0x00001000; +QSPI_FLASH_START = 0x60000000; +QSPI_FLASH_LENGTH = 0x04000000; +OPTION_SETTING_OFS0_START = 0x0100a100; +OPTION_SETTING_OFS0_LENGTH = 0x00000004; +OPTION_SETTING_OSIS_START = 0x0100a120; +OPTION_SETTING_OSIS_LENGTH = 0x00000010; +OPTION_SETTING_OFS1_SEC_START = 0x0100a200; +OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; +OPTION_SETTING_BPS_SEC_START = 0x0100a240; +OPTION_SETTING_BPS_SEC_LENGTH = 0x00000004; +OPTION_SETTING_PBPS_SEC_START = 0x0100a260; +OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000004; +__vector_table_size__ = 112 * 4; + +MEMORY +{ + RAM (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_SRAM1_START, LENGTH = MBED_CONFIGURED_RAM_BANK_SRAM1_SIZE + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_Flash_START, LENGTH = MBED_CONFIGURED_ROM_BANK_Flash_SIZE + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_OSIS (r) : ORIGIN = OPTION_SETTING_OSIS_START, LENGTH = OPTION_SETTING_OSIS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH +} + +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + + +SECTIONS +{ + /***** QSPI_FLASH memory section allocations ******/ + .qspi_flash.startof (READONLY) : + { + __ddsc_QSPI_FLASH_START = . ; + + } > QSPI_FLASH + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + /* Stick the vector table at start of SRAM */ + .vector_ram (NOLOAD) : + { + __vector_ram_start__ = .; + . += __vector_table_size__; + __vector_ram_end__ = .; + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from qspi_flash */ + __ram_from_qspi_flash$$ : + { + __ram_from_qspi_flash$$Base = . ;__ram_from_qspi_flash$$Load = LOADADDR(__ram_from_qspi_flash$$) ; + /* section.ram.from_qspi_flash */ + *(.ram_from_qspi_flash) + /* section.ram.code_from_qspi_flash */ + *(.ram_code_from_qspi_flash) + __ram_from_qspi_flash$$Limit = . ; + } > RAM AT > QSPI_FLASH + + __qspi_flash_readonly$$ (READONLY) : + { + __qspi_flash_readonly$$Base = . ; + /* section.qspi_flash.readonly */ + *(.qspi_flash) + /* section.qspi_flash.code */ + *(.qspi_flash_code) + __qspi_flash_readonly$$Limit = . ; + } > QSPI_FLASH + __qspi_flash_noinit$$ (NOLOAD) : + { + __qspi_flash_noinit$$Base = . ; + /* section.qspi_flash.noinit */ + *(.qspi_flash_noinit) + __qspi_flash_noinit$$Limit = . ; + } > QSPI_FLASH + .qspi_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_QSPI_FLASH_END = . ; + + } > QSPI_FLASH + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + .text (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + + .text (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* .ARM.extab sections contain exception unwinding information. */ + __flash_arm.extab$$ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + } > FLASH + /* .ARM.exidx sections contains index entries for section unwinding. */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + __exidx_end = . ; + } > FLASH + + __etext = .; + + /***** RAM memory section allocations ******/ + /* ram initialized from flash */ + .data : + { + __data_start__ = .; + _sdata = .; + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(.data) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + __ram_from_flash$$Limit = . ; + __data_end__ = .; + _edata = .; + } > RAM AT > FLASH + /* Non-initialized, non-cached ram */ + __ram_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + .bss (NOLOAD) : + { + __bss_start__ = .; + _sbss = .; + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + .bss (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* Main stack region */ + __StackLimit = .; + *(.bss.g_main_stack) + __StackTop = .; + /* Other no-init data */ + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + .bss (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + __ram_zero$$Limit = . ; + __bss_end__ = .; + _ebss = .; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,512) : + { + __ddsc_RAM_END = . ; + /* Heap region */ + __HeapBase = .; + __end__ = .; + PROVIDE(end = .); + *(.bss.g_heap) + __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); + } > RAM + + .flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 Secure */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_OSIS memory section allocations ******/ + .option_setting_osis.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OSIS_START = . ; + + } > OPTION_SETTING_OSIS + /* OCD/Serial Programmer ID setting register Secure */ + __option_setting_osis_reg$$ (READONLY) : + { + __option_setting_osis_reg$$Base = . ; + KEEP(*(.option_setting_osis)) + __option_setting_osis_reg$$Limit = . ; + } > OPTION_SETTING_OSIS + .option_setting_osis.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OSIS_END = . ; + + } > OPTION_SETTING_OSIS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + +} + diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h new file mode 100644 index 0000000000..377e50513e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_elc.h @@ -0,0 +1,265 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA6E2 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* UNCRUSTIFY-OFF */ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list is device specific. + * */ +typedef enum e_elc_event_ra6e2 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DMA_TRANSERR = (0x02B), // DMA/DTC transfer error + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_CAN_RXF = (0x059), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x05A), // Global error + ELC_EVENT_CAN_DMAREQ0 = (0x05B), // RX fifo DMA request 0 + ELC_EVENT_CAN_DMAREQ1 = (0x05C), // RX fifo DMA request 1 + ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x064), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request + ELC_EVENT_CAN0_RXMB = (0x067), // Receive message buffer interrupt + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt + ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt + ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT0_AD_TRIG_A = (0x0C9), // A/D converter start request A + ELC_EVENT_GPT0_AD_TRIG_B = (0x0CA), // A/D converter start request B + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0CB), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CC), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CD), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CE), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CF), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0D0), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0D1), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D2), // Underflow + ELC_EVENT_GPT1_PC = (0x0D3), // Period count function finish + ELC_EVENT_GPT1_AD_TRIG_A = (0x0D4), // A/D converter start request A + ELC_EVENT_GPT1_AD_TRIG_B = (0x0D5), // A/D converter start request B + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D6), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D7), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D8), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D9), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0DA), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0DB), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0DC), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0DD), // Underflow + ELC_EVENT_GPT2_AD_TRIG_A = (0x0DF), // A/D converter start request A + ELC_EVENT_GPT2_AD_TRIG_B = (0x0E0), // A/D converter start request B + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0E1), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0E2), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0E3), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0E4), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0E5), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E6), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E7), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E8), // Underflow + ELC_EVENT_GPT3_AD_TRIG_A = (0x0EA), // A/D converter start request A + ELC_EVENT_GPT3_AD_TRIG_B = (0x0EB), // A/D converter start request B + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0EE), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0EF), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0F0), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0F1), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0F2), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0F3), // Underflow + ELC_EVENT_GPT4_PC = (0x0F4), // Period count function finish + ELC_EVENT_GPT4_AD_TRIG_A = (0x0F5), // A/D converter start request A + ELC_EVENT_GPT4_AD_TRIG_B = (0x0F6), // A/D converter start request B + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0F7), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0F8), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0F9), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0FA), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0FB), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0FC), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0FD), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0FE), // Underflow + ELC_EVENT_GPT5_PC = (0x0FF), // Period count function finish + ELC_EVENT_GPT5_AD_TRIG_A = (0x100), // A/D converter start request A + ELC_EVENT_GPT5_AD_TRIG_B = (0x101), // A/D converter start request B + ELC_EVENT_OPS_UVW_EDGE = (0x15C), // UVW edge event + ELC_EVENT_ADC0_SCAN_END = (0x160), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive error + ELC_EVENT_SCI9_RXI = (0x1B6), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_EVENT_CAN0_MRAM_ERI = (0x1D0), // CANFD0 ECC error + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt + ELC_EVENT_I3C0_RESPONSE = (0x1DC), // Response status buffer full + ELC_EVENT_I3C0_COMMAND = (0x1DD), // Command buffer empty + ELC_EVENT_I3C0_IBI = (0x1DE), // IBI status buffer full + ELC_EVENT_I3C0_RX = (0x1DF), // Receive + ELC_EVENT_IICB0_RXI = (0x1DF), // Receive + ELC_EVENT_I3C0_TX = (0x1E0), // Transmit + ELC_EVENT_IICB0_TXI = (0x1E0), // Transmit + ELC_EVENT_I3C0_RCV_STATUS = (0x1E1), // Receive status buffer full + ELC_EVENT_I3C0_HRESP = (0x1E2), // High priority response queue full + ELC_EVENT_I3C0_HCMD = (0x1E3), // High priority command queue empty + ELC_EVENT_I3C0_HRX = (0x1E4), // High priority rx data buffer full + ELC_EVENT_I3C0_HTX = (0x1E5), // High priority tx data buffer empty + ELC_EVENT_I3C0_TEND = (0x1E6), // Transmit end + ELC_EVENT_IICB0_TEI = (0x1E6), // Transmit end + ELC_EVENT_I3C0_EEI = (0x1E7), // Error + ELC_EVENT_IICB0_ERI = (0x1E7), // Error + ELC_EVENT_I3C0_STEV = (0x1E8), // Synchronous timing + ELC_EVENT_I3C0_MREFOVF = (0x1E9), // MREF counter overflow + ELC_EVENT_I3C0_MREFCPT = (0x1EA), // MREF capture + ELC_EVENT_I3C0_AMEV = (0x1EB), // Additional master-initiated bus event + ELC_EVENT_I3C0_WU = (0x1EC), // Wake-up Condition Detection interrupt + ELC_EVENT_TRNG_RDREQ = (0x1F3) // TRNG Read Request +} elc_event_t; + +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) + +#define ELC_PERIPHERAL_NUM (24U) +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +/** Possible peripherals to be linked to event signals + * @note This list is device specific. + * */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_I3C = (23) +} elc_peripheral_t; + +/** Positions of event link set registers (ELSRs) available on this MCU */ +#define BSP_ELC_PERIPHERAL_MASK (0x0083F3FFU) + +/* UNCRUSTIFY-ON */ +/** @} (end addtogroup BSP_MCU_RA6E2) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h new file mode 100644 index 0000000000..48e413533a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_feature.h @@ -0,0 +1,629 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_peripheral.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#if (BSP_CFG_XTAL_HZ >= (20000000)) + #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (16000000)) + #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (8000000)) + #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#else + #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#endif + +// *UNCRUSTIFY-OFF* + +#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_NONE) // Feature not available on this device. + +#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. +#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. +#define BSP_FEATURE_ADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the ADC. +#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. +#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK (0x000139F7UL) // Mask of available channels in ADC unit 0. +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK (0x00UL) // Mask of available channels in ADC unit 1. +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x01UL) // Mask of whole, physical ADC units present in the MCU. + +#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS_MASK (0x00ULL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS_MASK (0x00ULL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_D_CHANNELS_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_IS_ADC12 (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (0U) // Number of channels for only AGT (not AGTW) peripherals. +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (2U) // Number of channels for only AGTW (not AGT) peripherals. +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03UL) // A mask of all valid AGTx channels. + +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. +#define BSP_FEATURE_BSP_HAS_DSMIF_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. +#define BSP_FEATURE_BSP_HAS_ESC_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. +#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. +#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. +#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. +#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. +#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. +#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. +#define BSP_FEATURE_BSP_NUM_PMSAR (9UL) // Number of available Port Security Attribution Registers. +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0UL) // Indicates security attribution settings for banks are present in the OFS registers. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. +#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. +#define BSP_FEATURE_BSP_PART_NUMBER_OFFSET (0x00UL) // Bit offset of the Part Number in the mcu info block. +#define BSP_FEATURE_BSP_PART_NUMBER_POINTER (0x010080F0UL) // Address of the Part Numbering register (PNR). +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. +#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. + +#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') // Flexible data rate support. +#define BSP_FEATURE_CANFD_HAS_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. +#define BSP_FEATURE_CANFD_LITE (1UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. +#define BSP_FEATURE_CANFD_NUM_CHANNELS (1UL) // Number of CANFD channels per CANFD peripheral instance. +#define BSP_FEATURE_CANFD_NUM_INSTANCES (1UL) // Number of hardware instances of the CANFD peripheral. + +#define BSP_FEATURE_CEC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CEC_HAS_CLOCK (1UL) // Indicates there is a separate clock for the CEC. + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. +#define BSP_FEATURE_CGC_HAS_BCLK (0UL) // External Bus Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK1 (0UL) // CPU1 Clock is available. +#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. +#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. +#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. +#define BSP_FEATURE_CGC_HAS_MOCO (1UL) // Middle clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MOSC (1UL) // Main clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MRICLK (0UL) // MRAM bus clock is available. +#define BSP_FEATURE_CGC_HAS_NPUCLK (0UL) // NPU clock is available. +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. +#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. +#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. +#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. +#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. +#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. +#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. +#define BSP_FEATURE_CGC_HAS_PLL2 (0UL) // PLL2 is available. +#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. +#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1UL) // SRAMPRCR2 register is available. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. +#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ (24000000UL) // Maximum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ (8000000UL) // Minimum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ (0UL) // Maximum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ (0UL) // Minimum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. +#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0UL) // Number of output clocks for PLL2. +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0UL) // Maximum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0UL) // Minimum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0UL) // PLL VCO maximum frequency. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. +#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIVCR.PCLKB. +#define BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK (0UL) // Requires the SCKDIVCR2.CPUCLK1 bits to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. +#define BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK (0UL) // Requires the bits [11:8] to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. +#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22002222UL) // Reset value for the SCKDIVCR register. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. + +#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. +#define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. +#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. + +#define BSP_FEATURE_CTSU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x01UL) // DAADSCR register is available. +#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. +#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. +#define BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL (0UL) // DAC output can be routed to specific extra internal modules using DAASWCR register. +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. + +#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. +#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. + +#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). +#define BSP_FEATURE_DMAC_NUM_CHANNELS (8UL) // Number of DMAC channels available. + +#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. + +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. + +#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. + +#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. + +#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESC_NUM_PORTS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ESWM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_FRER_TABLE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_TIMER_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GWCA_PORT (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_DOMAIN (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ETHER_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Feature not available on this device. + +#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. +#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. +#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. +#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. +#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. +#define BSP_FEATURE_FLASH_CACHE (1UL) // Flash cache is present. +#define BSP_FEATURE_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. +#define BSP_FEATURE_FLASH_CODE_CACHE_VERSION (1UL) // Version of C-Cache implemented in a CM33 core. +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. +#define BSP_FEATURE_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). +#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1UL) // ID code is supported (OSIS register is available). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. + +#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00UL) // Start of the second code flash bank. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. +#define BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE (0UL) // Constraints exist for flash cache operation during flash programming access. +#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (0UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0UL) // Device contains two code banks. +#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. + +#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x00UL) // Mask of 32-bit GPT channel indices. +#define BSP_FEATURE_GPT_AD_CONVERSION_START_CHANNEL_MASK (0x3FUL) // Mask of GPT channels supporting A/D conversion start. +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // GPT A/D conversion start request is directly output to ADC instead of via the ELC. +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FUL) // Mask of channels that support event count input (has GTUPSR register). +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. +#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x3FUL) // Mask of GPT channels that are the GPTE implementation. +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1UL) // At least one GPTE implementation is available, GPTE implementations have a GTITC register. +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available, GPTEH implementations have a PDG module. +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FUL) // Mask of channels that support dead time control. +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. +#define BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. +#define BSP_FEATURE_GPT_MSTP_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. +#define BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. +#define BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED (0UL) // At least one GPT channel supports polarity inversion of the GTIOCnA or GTIOCnB I/O pins. +#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. + +#define BSP_FEATURE_I3C_IS_AVAILABLE (1UL) +#define BSP_FEATURE_I3C_HAS_CLOCK (1UL) // Indicates there is a separate clock for the I3C. +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // I3C support high data rate mode. +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (8UL) // Maximum number of bus devices. +#define BSP_FEATURE_I3C_MSTP_OFFSET (4UL) // Offset of the MSTP bit for the I3C peripherals. +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16UL) // Depth of the normal transmit data buffer. +#define BSP_FEATURE_I3C_NUM_CHANNELS (1UL) // Total number of available channels. + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. +#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. +#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. +#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x7FFFUL) // Mask of available IRQ control registers. +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. +#define BSP_FEATURE_ICU_WUPEN_MASK (0x000008007B0D7FFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. + +#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER (5UL) // Multiplication factor to calculate SDA bus free time. +#define BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA (0UL) // SCL status needs to be checked before writing the transmission data in master mode. +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK (0x01UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x01UL) // Mask of available IIC_B or compatible I3C channels. +#define BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK (0UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_HAS_CLOCK (0UL) // Indicates there is a separate IIC clock. +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC channels. + +#define BSP_FEATURE_IOPORT_CCD_PINS_MASK (0x00UL) // Mask of valid indices for CCD pins. +#define BSP_FEATURE_IOPORT_ELC_PORTS_MASK (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. +#define BSP_FEATURE_IOPORT_HAS_LVOCR (0UL) // The LVOCR register is available. +#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. + +#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. + +#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. + +#define BSP_FEATURE_LCD_HAS_CLOCK (0UL) // Indicates there is a separate clock for the LCD. + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00135FF3ULL) // Mask of valid bit-fields of the DPSIEGRn registers. +#define BSP_FEATURE_LPM_DPSIER_MASK (0x051F5FF3ULL) // Mask of valid bit-fields of the DPSIERn registers. +#define BSP_FEATURE_LPM_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE (0UL) // The DPSBYCR.DCSSMODE field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. +#define BSP_FEATURE_LPM_HAS_LDO_SKEEP (0UL) // PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers are available. +#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0UL) // The SBYCR.OPE field is available. +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. +#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0UL) // The SNZEDCR1 register is available. +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0UL) // The SNZREQCR1 register is available. +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. +#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1UL) // Indicates that bit 14 of the SBYCR register should always be set. +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x9FUL) // Mask of valid bits for the SNZEDCRn registers. +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x73007FFFULL) // Mask of valid bits for the SNZREQCRn registers. +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. + +#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. +#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage low threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage low threshold. +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. +#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. +#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. +#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. + +#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. + +#define BSP_FEATURE_MIPI_CSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_DSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_PHY_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MRAM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_B_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. +#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. +#define BSP_FEATURE_POEG_MSTP_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. + +#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. + +#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. +#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. +#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E11A. +#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E31A. +#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP-E50D. +#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E51A. +#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. +#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. +#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. +#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (0UL) // The device supports cryptography using SCE9. +#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (1UL) // The device supports a TRNG module. + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_RTC_HAS_ALARM1 (0UL) // Alarm 1 is available. +#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. +#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. +#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. +#define BSP_FEATURE_RTC_HAS_VBTICTLR (0UL) // System supports VBATT input control to the RTC. +#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (2UL) // Number of RTCCRn registers that are available. + +#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK (0x0201UL) // Mask of channels with data compare match (DCCR) available. +#define BSP_FEATURE_SCI_CHANNELS_MASK (0x0201UL) // Mask of available SCI channels. +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. +#define BSP_FEATURE_SCI_HAS_CLOCK (0UL) // Indicates there is a separate SCI clock. +#define BSP_FEATURE_SCI_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. +#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. +#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. +#define BSP_FEATURE_SCI_LIN_CHANNELS_MASK (0x00UL) // Mask of channels that can support LIN. +#define BSP_FEATURE_SCI_SPI_SCKSEL_MASK (0UL) // Mask indicating CCR4.SCKSEL is available. +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK (0x00UL) // List of channels that do not support ABCSE functionality. +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK (0x0201UL) // Mask of channels which support CTS external pins. +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK (0x0201UL) // Mask of channels which support the UART FIFO. +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. +#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. + +#define BSP_FEATURE_SDADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. + +#define BSP_FEATURE_SDHI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. + +#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED (1UL) // Burst transfer without delay between frames is supported. +#define BSP_FEATURE_SPI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. +#define BSP_FEATURE_SPI_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SPI. +#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. +#define BSP_FEATURE_SPI_NUM_CHANNELS (2UL) // Number of available SPI channels. +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. + +#define BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR (0UL) // Flag indicating that SRAMSABAR2 and SRAMSABAR3 are present. +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. + +#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1UL) // Mask of valid SSI channel indices. + +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS (50000000UL) // Maximum frequency allowed before requiring one wait cycle. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS (150000000UL) // Maximum frequency allowed before requiring three wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS (100000000UL) // Maximum frequency allowed before requiring two wait cycles. + +#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (1UL) // A module stop control is available for TRNG. + +#define BSP_FEATURE_TSN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. +#define BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available for TSN. +#define BSP_FEATURE_TSN_CALIBRATION32_MASK (0xFFFFUL) // Mask of valid bits for TSN calibration. +#define BSP_FEATURE_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. +#define BSP_FEATURE_TSN_HAS_LOW_TEMP_REG (0UL) // Determine if the TSCDRL (Low Temperature) is present. +#define BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG (0UL) // Determine if the TSCDRR (Room Temperature) is present. +#define BSP_FEATURE_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. + +#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TZ_HAS_DLM (0UL) // Device Lifecycle Management Monitor (DLMMON) register is available. +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. +#define BSP_FEATURE_TZ_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. +#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. +#define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. + +#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ULPT_NUM_CHANNELS_AVAILABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) +#define BSP_FEATURE_USB_HAS_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. +#define BSP_FEATURE_USB_HAS_NOT_HOST (1UL) // Indicates that USB Host mode is not available. +#define BSP_FEATURE_USB_HAS_PIPE04567 (1UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. +#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. +#define BSP_FEATURE_USB_HAS_USB60_CLOCK (0UL) // Indicates the USB60 clock is available. +#define BSP_FEATURE_USB_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. +#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. +#define BSP_FEATURE_USB_HAS_USBFS_BC (0UL) // Supports battery charging in full-speed mode. +#define BSP_FEATURE_USB_HAS_USBHS (0UL) // Supports USB 2.0 High-Speed mode. +#define BSP_FEATURE_USB_HAS_USBHS_BC (0UL) // Supports battery charging in high-speed mode. +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (1UL) // Indicates the PHYSECTRL.CNEN field is available. +#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. +#define BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR2 register. + +#define BSP_FEATURE_VIN_IS_AVAILABLE (0UL) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_linker.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_linker.c new file mode 100644 index 0000000000..a6a693aafc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_linker.c @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#if defined BSP_CFG_OPTION_SETTING_OFS0 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_cfg_option_setting_ofs0[] = {BSP_CFG_OPTION_SETTING_OFS0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OSIS && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_osis") g_bsp_cfg_option_setting_osis[] = {BSP_CFG_OPTION_SETTING_OSIS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_cfg_option_setting_ofs1_sec[] = {BSP_CFG_OPTION_SETTING_OFS1_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec") g_bsp_cfg_option_setting_bps_sec[] = {BSP_CFG_OPTION_SETTING_BPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec") g_bsp_cfg_option_setting_pbps_sec[] = {BSP_CFG_OPTION_SETTING_PBPS_SEC}; +#endif +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_linker_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_linker_info.h new file mode 100644 index 0000000000..a526124dfc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_linker_info.h @@ -0,0 +1,142 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/* UNCRUSTIFY-OFF */ +#ifndef BSP_LINKER_H + #define BSP_LINKER_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/******* Solution Definitions *************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +/* linker generated initialization table data structures types */ +typedef enum e_bsp_init_mem +{ + INIT_MEM_ZERO, + INIT_MEM_FLASH, + INIT_MEM_DATA_FLASH, + INIT_MEM_RAM, + INIT_MEM_DTCM, + INIT_MEM_ITCM, + INIT_MEM_CTCM, + INIT_MEM_STCM, + INIT_MEM_OSPI0_CS0, + INIT_MEM_OSPI0_CS1, + INIT_MEM_OSPI1_CS0, + INIT_MEM_OSPI1_CS1, + INIT_MEM_QSPI_FLASH, + INIT_MEM_SDRAM, + INIT_MEM_SIP_FLASH, +} bsp_init_mem_t; + +typedef struct st_bsp_init_type +{ + uint32_t copy_64 : 8; /* if 1, must use 64 bit copy operation (to keep ecc happy) */ + uint32_t external : 8; /* =1 if either source or destination is external, else 0 */ + uint32_t source_type : 8; + uint32_t destination_type : 8; +} bsp_init_type_t; + +typedef struct st_bsp_init_zero_info +{ + uint32_t * const p_base; + uint32_t * const p_limit; + bsp_init_type_t type; +} bsp_init_zero_info_t; + +typedef struct st_bsp_init_copy_info +{ + uint32_t * const p_base; + uint32_t * const p_limit; + uint32_t * const p_load; + bsp_init_type_t type; +} bsp_init_copy_info_t; +typedef struct st_bsp_init_nocache_info +{ + uint32_t * const p_base; + uint32_t * const p_limit; +} bsp_mpu_nocache_info_t; + +typedef struct st_bsp_init_info +{ + uint32_t zero_count; + bsp_init_zero_info_t const * const p_zero_list; + uint32_t copy_count; + bsp_init_copy_info_t const * const p_copy_list; + uint32_t nocache_count; + bsp_mpu_nocache_info_t const * const p_nocache_list; +} bsp_init_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern bsp_init_info_t const g_init_info; +/* These symbols are used for sau/idau configuration in a secure project */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#endif // BSP_LINKER_H +#ifdef BSP_LINKER_C +/*********************************************************************************************************************** + * Objects allocated by bsp_linker.c + **********************************************************************************************************************/ +/* DDSC symbol definitions */ +/* Zero initialization tables */ +extern uint32_t __ram_zero_nocache$$Base; +extern uint32_t __ram_zero_nocache$$Limit; +extern uint32_t __ram_zero$$Base; +extern uint32_t __ram_zero$$Limit; +static const bsp_init_zero_info_t zero_list[] = +{ + {.p_base = &__ram_zero_nocache$$Base, .p_limit = &__ram_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_zero$$Base, .p_limit = &__ram_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}} +}; +/* Load initialization tables */ +extern uint32_t __ram_from_qspi_flash$$Base; +extern uint32_t __ram_from_qspi_flash$$Limit; +extern uint32_t __ram_from_qspi_flash$$Load; +extern uint32_t __ram_from_data_flash$$Base; +extern uint32_t __ram_from_data_flash$$Limit; +extern uint32_t __ram_from_data_flash$$Load; +extern uint32_t __ram_from_flash$$Base; +extern uint32_t __ram_from_flash$$Limit; +extern uint32_t __ram_from_flash$$Load; +static const bsp_init_copy_info_t copy_list[] = +{ + {.p_base = &__ram_from_qspi_flash$$Base, .p_limit = &__ram_from_qspi_flash$$Limit, .p_load = &__ram_from_qspi_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_QSPI_FLASH, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_from_data_flash$$Base, .p_limit = &__ram_from_data_flash$$Limit, .p_load = &__ram_from_data_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_from_flash$$Base, .p_limit = &__ram_from_flash$$Limit, .p_load = &__ram_from_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_RAM}} +}; +/* nocache regions */ +extern uint32_t __ram_noinit_nocache$$Base; +extern uint32_t __ram_noinit_nocache$$Limit; +extern uint32_t __ram_zero_nocache$$Base; +extern uint32_t __ram_zero_nocache$$Limit; +static const bsp_mpu_nocache_info_t nocache_list[] = +{ + {.p_base = &__ram_noinit_nocache$$Base, .p_limit = &__ram_zero_nocache$$Limit}, +}; + +/* initialization data structure */ +const bsp_init_info_t g_init_info = +{ + .zero_count = sizeof(zero_list) / sizeof(zero_list[0]), + .p_zero_list = zero_list, + .copy_count = sizeof(copy_list) / sizeof(copy_list[0]), + .p_copy_list = copy_list, + .nocache_count = sizeof(nocache_list) / sizeof(nocache_list[0]), + .p_nocache_list = nocache_list +}; + +#endif // BSP_LINKER_C + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_mcu_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_mcu_info.h new file mode 100644 index 0000000000..cc300baca7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_mcu_info.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA6E2 RA6E2 + * @includedoc config_bsp_ra6e2_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA6E2) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_peripheral.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_peripheral.h new file mode 100644 index 0000000000..b519f037cb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6e2/bsp_peripheral.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_PERIPHERAL_H +#define BSP_PERIPHERAL_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// *UNCRUSTIFY-OFF* + +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (1) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_PRESENT (1) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_CEC_PRESENT (1) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DAC_B_PRESENT (0) +#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ESWM_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FU) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0x7FFFU) +#define BSP_PERIPHERAL_IIC_PRESENT (0) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IPC_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_CSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_PHY_PRESENT (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MRMS_PRESENT (0) +#define BSP_PERIPHERAL_MRRGE_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_NPU_PRESENT (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDM_PRESENT (0) +#define BSP_PERIPHERAL_PDM_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x13FU) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RSIP_PRESENT (1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x201U) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_USBCC_PRESENT (0) +#define BSP_PERIPHERAL_VIN_PRESENT (0) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h new file mode 100644 index 0000000000..bd781b9e62 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h @@ -0,0 +1,423 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA6M3 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* UNCRUSTIFY-OFF */ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list is device specific. + * */ +typedef enum e_elc_event_ra6m3 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x021), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x022), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x023), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x024), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x025), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x026), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x027), // DMAC7 transfer end + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x046), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x047), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x048), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x049), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x04A), // Carry interrupt + ELC_EVENT_ADC0_SCAN_END = (0x04B), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x04C), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x04D), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x04E), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x04F), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x050), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x051), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x052), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x053), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x054), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x055), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x056), // Compare mismatch + ELC_EVENT_ACMPHS0_INT = (0x057), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x058), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ACMPHS2_INT = (0x059), // High Speed Comparator channel 2 interrupt + ELC_EVENT_ACMPHS3_INT = (0x05A), // High Speed Comparator channel 3 interrupt + ELC_EVENT_ACMPHS4_INT = (0x05B), // High Speed Comparator channel 4 interrupt + ELC_EVENT_ACMPHS5_INT = (0x05C), // High Speed Comparator channel 5 interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x05F), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x060), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x061), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x062), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x063), // Receive data full + ELC_EVENT_IIC0_TXI = (0x064), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x065), // Transmit end + ELC_EVENT_IIC0_ERI = (0x066), // Transfer error + ELC_EVENT_IIC0_WUI = (0x067), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x068), // Receive data full + ELC_EVENT_IIC1_TXI = (0x069), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x06A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x06B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x06D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x06E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x06F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x070), // Transfer error + ELC_EVENT_SSI0_TXI = (0x072), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x073), // Receive data full + ELC_EVENT_SSI0_INT = (0x075), // Error interrupt + ELC_EVENT_SSI1_TXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x078), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x079), // Error interrupt + ELC_EVENT_SRC_INPUT_FIFO_EMPTY = (0x07A), // Input FIFO empty + ELC_EVENT_SRC_OUTPUT_FIFO_FULL = (0x07B), // Output FIFO full + ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW = (0x07C), // Output FIFO overflow + ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW = (0x07D), // Output FIFO underflow + ELC_EVENT_SRC_CONVERSION_END = (0x07E), // Conversion end + ELC_EVENT_PDC_RECEIVE_DATA_READY = (0x07F), // Receive data ready interrupt + ELC_EVENT_PDC_FRAME_END = (0x080), // Frame end interrupt + ELC_EVENT_PDC_INT = (0x081), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x082), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x083), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x084), // Measurement end interrupt + ELC_EVENT_KEY_INT = (0x085), // Key interrupt + ELC_EVENT_DOC_INT = (0x086), // Data operation circuit interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x087), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x088), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x089), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x08A), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x08B), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x08C), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x08D), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x08E), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x08F), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x090), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x091), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x092), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x093), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x094), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x095), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x096), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x097), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x098), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x099), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x09A), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x09B), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x09C), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x09D), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0B0), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0B1), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0B2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0B3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0B4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0B5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0B6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0B7), // Underflow + ELC_EVENT_GPT0_AD_TRIG_A = (0x0B8), // A/D converter start request A + ELC_EVENT_GPT0_AD_TRIG_B = (0x0B9), // A/D converter start request B + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0BA), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0BB), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0BC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0BD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0BE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0BF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0C0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0C1), // Underflow + ELC_EVENT_GPT1_AD_TRIG_A = (0x0C2), // A/D converter start request A + ELC_EVENT_GPT1_AD_TRIG_B = (0x0C3), // A/D converter start request B + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0C4), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0C5), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0C6), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0C7), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0C8), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0C9), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0CA), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0CB), // Underflow + ELC_EVENT_GPT2_AD_TRIG_A = (0x0CC), // A/D converter start request A + ELC_EVENT_GPT2_AD_TRIG_B = (0x0CD), // A/D converter start request B + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT3_AD_TRIG_A = (0x0D6), // A/D converter start request A + ELC_EVENT_GPT3_AD_TRIG_B = (0x0D7), // A/D converter start request B + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0D8), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0D9), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0DA), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0DB), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0DC), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0DD), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0DE), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0DF), // Underflow + ELC_EVENT_GPT4_AD_TRIG_A = (0x0E0), // A/D converter start request A + ELC_EVENT_GPT4_AD_TRIG_B = (0x0E1), // A/D converter start request B + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0E2), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0E3), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0E4), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0E5), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0E6), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0E7), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0E8), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0E9), // Underflow + ELC_EVENT_GPT5_AD_TRIG_A = (0x0EA), // A/D converter start request A + ELC_EVENT_GPT5_AD_TRIG_B = (0x0EB), // A/D converter start request B + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0EC), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0ED), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0EE), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0EF), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0F0), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0F1), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0F2), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0F3), // Underflow + ELC_EVENT_GPT6_AD_TRIG_A = (0x0F4), // A/D converter start request A + ELC_EVENT_GPT6_AD_TRIG_B = (0x0F5), // A/D converter start request B + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0F6), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0F7), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT7_AD_TRIG_A = (0x0FE), // A/D converter start request A + ELC_EVENT_GPT7_AD_TRIG_B = (0x0FF), // A/D converter start request B + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x100), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x101), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x102), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x103), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x104), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x105), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x106), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x107), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x10A), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x10B), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x10C), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x10D), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x10E), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x10F), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x110), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x111), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x114), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x115), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x116), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x117), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x118), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x119), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x11A), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x11B), // Underflow + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x11E), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x11F), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x120), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x121), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x122), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x123), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x124), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x125), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x128), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x129), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x12A), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x12B), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x12C), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x12D), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x12E), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x12F), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x132), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x133), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x134), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x135), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x136), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x137), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x138), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x139), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_EPTPC_IPLS = (0x160), // STCA interrupt + ELC_EVENT_EPTPC_MINT = (0x161), // SYNFP0/1 interrupt + ELC_EVENT_EPTPC_PINT = (0x162), // PTPEDMAC interrupt + ELC_EVENT_EDMAC0_EINT = (0x163), // EDMAC 0 interrupt + ELC_EVENT_EPTPC_TIMER0_RISE = (0x165), // Pulse output timer 0 rising edge detection + ELC_EVENT_EPTPC_TIMER1_RISE = (0x166), // Pulse output timer 1 rising edge detection + ELC_EVENT_EPTPC_TIMER2_RISE = (0x167), // Pulse output timer 2 rising edge detection + ELC_EVENT_EPTPC_TIMER3_RISE = (0x168), // Pulse output timer 3 rising edge detection + ELC_EVENT_EPTPC_TIMER4_RISE = (0x169), // Pulse output timer 4 rising edge detection + ELC_EVENT_EPTPC_TIMER5_RISE = (0x16A), // Pulse output timer 5 rising edge detection + ELC_EVENT_EPTPC_TIMER0_FALL = (0x16B), // Pulse output timer 0 falling edge detection + ELC_EVENT_EPTPC_TIMER1_FALL = (0x16C), // Pulse output timer 1 falling edge detection + ELC_EVENT_EPTPC_TIMER2_FALL = (0x16D), // Pulse output timer 2 falling edge detection + ELC_EVENT_EPTPC_TIMER3_FALL = (0x16E), // Pulse output timer 3 falling edge detection + ELC_EVENT_EPTPC_TIMER4_FALL = (0x16F), // Pulse output timer 4 falling edge detection + ELC_EVENT_EPTPC_TIMER5_FALL = (0x170), // Pulse output timer 5 falling edge detection + ELC_EVENT_USBHS_FIFO_0 = (0x171), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x172), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x173), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x174), // Receive data full + ELC_EVENT_SCI0_TXI = (0x175), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x176), // Transmit end + ELC_EVENT_SCI0_ERI = (0x177), // Receive error + ELC_EVENT_SCI0_AM = (0x178), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x179), // Receive data full/Receive error + ELC_EVENT_SCI1_RXI = (0x17A), // Receive data full + ELC_EVENT_SCI1_TXI = (0x17B), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x17C), // Transmit end + ELC_EVENT_SCI1_ERI = (0x17D), // Receive error + ELC_EVENT_SCI1_AM = (0x17E), // Address match event + ELC_EVENT_SCI2_RXI = (0x180), // Receive data full + ELC_EVENT_SCI2_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x182), // Transmit end + ELC_EVENT_SCI2_ERI = (0x183), // Receive error + ELC_EVENT_SCI2_AM = (0x184), // Address match event + ELC_EVENT_SCI3_RXI = (0x186), // Receive data full + ELC_EVENT_SCI3_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x188), // Transmit end + ELC_EVENT_SCI3_ERI = (0x189), // Receive error + ELC_EVENT_SCI3_AM = (0x18A), // Address match event + ELC_EVENT_SCI4_RXI = (0x18C), // Receive data full + ELC_EVENT_SCI4_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI4_ERI = (0x18F), // Receive error + ELC_EVENT_SCI4_AM = (0x190), // Address match event + ELC_EVENT_SCI5_RXI = (0x192), // Receive data full + ELC_EVENT_SCI5_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x194), // Transmit end + ELC_EVENT_SCI5_ERI = (0x195), // Receive error + ELC_EVENT_SCI5_AM = (0x196), // Address match event + ELC_EVENT_SCI6_RXI = (0x198), // Receive data full + ELC_EVENT_SCI6_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI6_ERI = (0x19B), // Receive error + ELC_EVENT_SCI6_AM = (0x19C), // Address match event + ELC_EVENT_SCI7_RXI = (0x19E), // Receive data full + ELC_EVENT_SCI7_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI7_AM = (0x1A2), // Address match event + ELC_EVENT_SCI8_RXI = (0x1A4), // Receive data full + ELC_EVENT_SCI8_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI8_AM = (0x1A8), // Address match event + ELC_EVENT_SCI9_RXI = (0x1AA), // Receive data full + ELC_EVENT_SCI9_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI9_AM = (0x1AE), // Address match event + ELC_EVENT_SPI0_RXI = (0x1BC), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1BD), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1BE), // Idle + ELC_EVENT_SPI0_ERI = (0x1BF), // Error + ELC_EVENT_SPI0_TEI = (0x1C0), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C1), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1C2), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1C3), // Idle + ELC_EVENT_SPI1_ERI = (0x1C4), // Error + ELC_EVENT_SPI1_TEI = (0x1C5), // Transmission complete event + ELC_EVENT_QSPI_INT = (0x1C6), // QSPI interrupt + ELC_EVENT_SDHIMMC0_ACCS = (0x1C7), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x1C8), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x1C9), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x1CA), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x1CB), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x1CC), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x1CD), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x1CE), // DMA transfer request + ELC_EVENT_SCE_TADI = (0x1E2), // SCE Tamper Detection + ELC_EVENT_GLCDC_LINE_DETECT = (0x1FA), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1FB), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1FC), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x1FD), // DRW interrupt + ELC_EVENT_JPEG_JEDI = (0x1FE), // Compression/decompression process interrupt + ELC_EVENT_JPEG_JDTI = (0x1FF) // Data transfer interrupt +} elc_event_t; + +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) + +#define ELC_PERIPHERAL_NUM (19U) +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +/** Possible peripherals to be linked to event signals + * @note This list is device specific. + * */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_ADC1 = (10), + ELC_PERIPHERAL_ADC1_B = (11), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_CTSU = (18) +} elc_peripheral_t; + +/** Positions of event link set registers (ELSRs) available on this MCU */ +#define BSP_ELC_PERIPHERAL_MASK (0x0007FFFFU) + +/* UNCRUSTIFY-ON */ +/** @} (end addtogroup BSP_MCU_RA6M3) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h new file mode 100644 index 0000000000..5febc40512 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -0,0 +1,629 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_peripheral.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) +#if (BSP_CFG_XTAL_HZ >= (20000000)) + #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (16000000)) + #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (8000000)) + #define CGC_MAINCLOCK_DRIVE (0x2U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#else + #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#endif + +// *UNCRUSTIFY-OFF* + +#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1UL) // Operation stabilization wait time. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) // The IVREF selection that corresponds to the internal voltage reference. + +#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. +#define BSP_FEATURE_ADC_HAS_ADBUF (0UL) // Determine if the ADBUFn registers are present. +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. +#define BSP_FEATURE_ADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the ADC. +#define BSP_FEATURE_ADC_HAS_PGA (1UL) // Determine if ADPGACR is present. +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. +#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK (0x001F00FFUL) // Mask of available channels in ADC unit 0. +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK (0x000F00EFUL) // Mask of available channels in ADC unit 1. +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. + +#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS_MASK (0x00ULL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS_MASK (0x00ULL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_D_CHANNELS_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_IS_ADC12 (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2U) // Number of channels for only AGT (not AGTW) peripherals. +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03UL) // A mask of all valid AGTx channels. + +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. +#define BSP_FEATURE_BSP_HAS_DSMIF_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. +#define BSP_FEATURE_BSP_HAS_ESC_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. +#define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. +#define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. +#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1UL) // Indicates the MCU has security MPU systems available. +#define BSP_FEATURE_BSP_HAS_SP_MON (1UL) // Indicates the Stack Pointer monitor is available. +#define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19CU) // Location of the FMIFRT register. +#define BSP_FEATURE_BSP_MMF_SUPPORTED (1UL) // Memory-mirror function is available. +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFUL) // Mask for allowed address range of the MPU. +#define BSP_FEATURE_BSP_NUM_PMSAR (0UL) // Number of available Port Security Attribution Registers. +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0UL) // Indicates security attribution settings for banks are present in the OFS registers. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. +#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. +#define BSP_FEATURE_BSP_PART_NUMBER_OFFSET (0x24UL) // Bit offset of the Part Number in the mcu info block. +#define BSP_FEATURE_BSP_PART_NUMBER_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) + BSP_FEATURE_BSP_PART_NUMBER_OFFSET) // Address of the Part Numbering register (PNR). +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. +#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x14UL) // Bit offset of the Unique ID in the mcu info block. +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) + BSP_FEATURE_BSP_UNIQUE_ID_OFFSET) // Address of the MCU Unique ID register (UIDR). +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. + +#define BSP_FEATURE_CAN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG (0UL) // Flag indicating that the ratio between PCLKA (or ICLK) and PCLKB must be 2:1 during CAN operation. +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Source clock for the CAN peripheral. +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Indicates that the only clock source for can is the CANMCLK. +#define BSP_FEATURE_CAN_NUM_CHANNELS (2UL) // Number of CAN peripherals. + +#define BSP_FEATURE_CANFD_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CANFD_FD_SUPPORT (0) // Feature not available on this device. +#define BSP_FEATURE_CANFD_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_LITE (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CEC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CEC_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. +#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK1 (0UL) // CPU1 Clock is available. +#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. +#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. +#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1UL) // HOCOWTCR register is available. +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. +#define BSP_FEATURE_CGC_HAS_MOCO (1UL) // Middle clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MOSC (1UL) // Main clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MRICLK (0UL) // MRAM bus clock is available. +#define BSP_FEATURE_CGC_HAS_NPUCLK (0UL) // NPU clock is available. +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. +#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. +#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. +#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. +#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. +#define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. +#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. +#define BSP_FEATURE_CGC_HAS_PLL2 (0UL) // PLL2 is available. +#define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. +#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0UL) // SRAMPRCR2 register is available. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2UL) // HOCO stabilization wait time when using SCI0. +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6UL) // HOCO stabilization wait time register value for 64 MHz. +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) // Reset value of the ICLK divider. +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. +#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ (24000000UL) // Maximum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ (8000000UL) // Minimum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ (0UL) // Maximum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ (0UL) // Minimum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (240000000UL) // Maximum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (120000000UL) // Minimum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. +#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0UL) // Number of output clocks for PLL2. +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0UL) // Maximum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0UL) // Minimum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1UL) // Indicates the type of PLLCCR register and PLL. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (0UL) // PLL VCO maximum frequency. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. +#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIVCR.PCLKB. +#define BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK (0UL) // Requires the SCKDIVCR2.CPUCLK1 bits to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. +#define BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK (0UL) // Requires the bits [11:8] to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SODRV_MASK (0x02UL) // Sub-clock drive field mask. +#define BSP_FEATURE_CGC_SODRV_SHIFT (1UL) // Sub-clock drive field shift. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x22022222UL) // Reset value for the SCKDIVCR register. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x40UL) // Reset value for the SCKDIVCR2 register. +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. + +#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. +#define BSP_FEATURE_CRC_HAS_SNOOP (1UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. +#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x03UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. + +#define BSP_FEATURE_CTSU_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3UL) // Number of CTSUCHAC registers. +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3UL) // Number of CTSUCHTRC registers. +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1UL) // CTSUCR0.CTSUTXVSEL field is available. +#define BSP_FEATURE_CTSU_VERSION (1UL) // Version of the CTSU peripheral. + +#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. +#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. +#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. +#define BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL (0UL) // DAC output can be routed to specific extra internal modules using DAASWCR register. +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. + +#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. +#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. + +#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (0UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). +#define BSP_FEATURE_DMAC_NUM_CHANNELS (8UL) // Number of DMAC channels available. + +#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DOC_VERSION (1UL) // The version of the DOC peripheral. + +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. + +#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. + +#define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. + +#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESC_NUM_PORTS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ESWM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_FRER_TABLE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_TIMER_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GWCA_PORT (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_DOMAIN (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. +#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // The number of AXI bus descriptors available to Ethernet components. +#define BSP_FEATURE_ETHER_NUM_CHANNELS (1UL) // Number of available ethernet PHYs. +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. + +#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. +#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. +#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. +#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. +#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. +#define BSP_FEATURE_FLASH_CACHE (1UL) // Flash cache is present. +#define BSP_FEATURE_FLASH_CACHE_DISABLE_OPM (1UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. +#define BSP_FEATURE_FLASH_CODE_CACHE_VERSION (0UL) // Version of C-Cache implemented in a CM33 core. +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000UL) // Start address of the Data Flash region. +#define BSP_FEATURE_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1UL) // Flash supports protected access window (AWS register is available). +#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1UL) // ID code is supported (OSIS register is available). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. + +#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00UL) // Start of the second code flash bank. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. +#define BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE (1UL) // Constraints exist for flash cache operation during flash programming access. +#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (0UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0UL) // FMEPROT register is present. +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0UL) // Device contains two code banks. +#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. + +#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFFUL) // Mask of 32-bit GPT channel indices. +#define BSP_FEATURE_GPT_AD_CONVERSION_START_CHANNEL_MASK (0xFFUL) // Mask of GPT channels supporting A/D conversion start. +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // GPT A/D conversion start request is directly output to ADC instead of via the ELC. +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (4UL) // Multiplicative step size of the clock divider (GTCR.TPCS). +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFFUL) // Mask of channels that support event count input (has GTUPSR register). +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. +#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0xF0UL) // Mask of GPT channels that are the GPTE implementation. +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1UL) // At least one GPTE implementation is available, GPTE implementations have a GTITC register. +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x0FUL) // Mask of GPT channels that are the GPTEH implementation. +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (1UL) // At least one GPTEH implementation is available, GPTEH implementations have a PDG module. +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFFUL) // Mask of channels that support dead time control. +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. +#define BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE (0UL) // Indicates the MSTP peripheral has an MSTPCRE register. +#define BSP_FEATURE_GPT_MSTP_MSTPD5 (1UL) // GPT stop bits use MSTPCRD.MSTPD5. +#define BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH (7UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (120000000UL) // Maximum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000UL) // Minimum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. +#define BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED (0UL) // At least one GPT channel supports polarity inversion of the GTIOCnA or GTIOCnB I/O pins. +#define BSP_FEATURE_GPT_TPCS_SHIFT (1UL) // Shift value to convert TPCS bit values to real multiplicative values. + +#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) +#define BSP_FEATURE_I3C_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. +#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. +#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. +#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0UL) // WUPEN1 register is available. +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (12UL) // Maximum bit field index of valid fields of the NMIER register. +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. + +#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER (0UL) // Multiplication factor to calculate SDA bus free time. +#define BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA (0UL) // SCL status needs to be checked before writing the transmission data in master mode. +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. +#define BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_HAS_CLOCK (0UL) // Indicates there is a separate IIC clock. +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07UL) // Mask of available IIC channels. + +#define BSP_FEATURE_IOPORT_CCD_PINS_MASK (0x00UL) // Mask of valid indices for CCD pins. +#define BSP_FEATURE_IOPORT_ELC_PORTS_MASK (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. +#define BSP_FEATURE_IOPORT_HAS_LVOCR (0UL) // The LVOCR register is available. +#define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. + +#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. + +#define BSP_FEATURE_KINT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // A module stop bit is provided for the KINT peripheral. + +#define BSP_FEATURE_LCD_HAS_CLOCK (0UL) // Indicates there is a separate clock for the LCD. + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{(0UL), (15UL)}, {(0UL), (13UL)}, {(1UL), (31UL)}, {(1UL), (6UL)}, {(1UL), (5UL)}, {(1UL), (4UL)}, {(2UL), (5UL)}} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00137FFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. +#define BSP_FEATURE_LPM_DPSIER_MASK (0x071F7FFFULL) // Mask of valid bit-fields of the DPSIERn registers. +#define BSP_FEATURE_LPM_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE (0UL) // The DPSBYCR.DCSSMODE field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1UL) // The DPSBYCR.DEEPCUT field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1UL) // The DPSBYCR.DPSBY field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. +#define BSP_FEATURE_LPM_HAS_LDO_SKEEP (0UL) // PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers are available. +#define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. +#define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0UL) // The SNZEDCR1 register is available. +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0UL) // The SNZREQCR1 register is available. +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. +#define BSP_FEATURE_LPM_HAS_STCONR (1UL) // The STCONR register is available. +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0xFFUL) // Mask of valid bits for the SNZEDCRn registers. +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFULL) // Mask of valid bits for the SNZREQCRn registers. +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. + +#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. +#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage low threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage low threshold. +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1UL) // LVDLVLR register is available. +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD1 is enabled. +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // Typical higher bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // Typical lower bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (10UL) // Maximum stabilization time to wait after LVD2 is enabled. +#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. +#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. +#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. + +#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. + +#define BSP_FEATURE_MIPI_CSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_DSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_PHY_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MRAM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_OSPI_B_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. +#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. +#define BSP_FEATURE_POEG_MSTP_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. + +#define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. + +#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. +#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. +#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E11A. +#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E31A. +#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP-E50D. +#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E51A. +#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. +#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. +#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (1UL) // The device supports cryptography using SCE7. +#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (0UL) // The device supports cryptography using SCE9. +#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_RTC_HAS_ALARM1 (0UL) // Alarm 1 is available. +#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. +#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. +#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. +#define BSP_FEATURE_RTC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. +#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. + +#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK (0x03FFUL) // Mask of channels with data compare match (DCCR) available. +#define BSP_FEATURE_SCI_CHANNELS_MASK (0x03FFUL) // Mask of available SCI channels. +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. +#define BSP_FEATURE_SCI_HAS_CLOCK (0UL) // Indicates there is a separate SCI clock. +#define BSP_FEATURE_SCI_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. +#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x02UL) // Mask of channels that support IrDA. +#define BSP_FEATURE_SCI_IRDA_SUPPORTED (1UL) // Indicates IrDA is supported on at least one SCI channel. +#define BSP_FEATURE_SCI_LIN_CHANNELS_MASK (0x00UL) // Mask of channels that can support LIN. +#define BSP_FEATURE_SCI_SPI_SCKSEL_MASK (0UL) // Mask indicating CCR4.SCKSEL is available. +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK (0x00UL) // List of channels that do not support ABCSE functionality. +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK (0x00UL) // Mask of channels which support CTS external pins. +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK (0x03FFUL) // Mask of channels which support the UART FIFO. +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. +#define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. + +#define BSP_FEATURE_SDADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. + +#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for the SDHI peripheral clock. +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (1UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x03UL) // Mask of valid SDHI channels. + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x90000000UL) // Start address of the external address space for SDRAM memory. + +#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED (0UL) // Burst transfer without delay between frames is supported. +#define BSP_FEATURE_SPI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. +#define BSP_FEATURE_SPI_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SPI. +#define BSP_FEATURE_SPI_HAS_SPCR3 (0UL) // SPCR3 register is available. +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. +#define BSP_FEATURE_SPI_NUM_CHANNELS (2UL) // Number of available SPI channels. +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. + +#define BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR (0UL) // Flag indicating that SRAMSABAR2 and SRAMSABAR3 are present. +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x0EUL) // Mask of bits needed to enable SRAM wait for all regions. + +#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3UL) // Mask of valid SSI channel indices. + +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS (60000000UL) // The maximum frequency that can be used before wait cycles are necessary. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS (40000000UL) // Maximum frequency allowed before requiring one wait cycle. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring three wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS (80000000UL) // Maximum frequency allowed before requiring two wait cycles. + +#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. + +#define BSP_FEATURE_TSN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. +#define BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available for TSN. +#define BSP_FEATURE_TSN_CALIBRATION32_MASK (0x0FFFUL) // Mask of valid bits for TSN calibration. +#define BSP_FEATURE_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. +#define BSP_FEATURE_TSN_HAS_LOW_TEMP_REG (0UL) // Determine if the TSCDRL (Low Temperature) is present. +#define BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG (0UL) // Determine if the TSCDRR (Room Temperature) is present. +#define BSP_FEATURE_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. + +#define BSP_FEATURE_TZ_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TZ_HAS_DLM (0UL) // Feature not available on this device. +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0UL) // Feature not available on this device. +#define BSP_FEATURE_TZ_HAS_TZFSAR (0UL) // Feature not available on this device. +#define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_TZ_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ULPT_NUM_CHANNELS_AVAILABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) +#define BSP_FEATURE_USB_HAS_CLOCK_REQ (0UL) // Indicates that a request bit must be set before changing USB clock settings. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL (0UL) // Indicates the USB clock has a selectable source. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. +#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. +#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. +#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. +#define BSP_FEATURE_USB_HAS_USB60_CLOCK (0UL) // Indicates the USB60 clock is available. +#define BSP_FEATURE_USB_HAS_USBCKDIVCR (0UL) // USBCKDIVCR register is available. +#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. +#define BSP_FEATURE_USB_HAS_USBFS_BC (0UL) // Supports battery charging in full-speed mode. +#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. +#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0UL) // Indicates the PHYSECTRL.CNEN field is available. +#define BSP_FEATURE_USB_REG_PHYSLEW (1UL) // Indicates the PHYSLEW register is available. +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x0EUL) // Reset value of the PHYSLEW register. +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. +#define BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV (1UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR2 register. + +#define BSP_FEATURE_VIN_IS_AVAILABLE (0UL) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_linker.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_linker.c new file mode 100644 index 0000000000..3c4a673846 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_linker.c @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#if defined BSP_CFG_OPTION_SETTING_OFS0 +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_cfg_option_setting_ofs0[] = {BSP_CFG_OPTION_SETTING_OFS0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1 +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_cfg_option_setting_ofs1[] = {BSP_CFG_OPTION_SETTING_OFS1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_SECMPU +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_secmpu") g_bsp_cfg_option_setting_secmpu[] = {BSP_CFG_OPTION_SETTING_SECMPU}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OSIS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_osis") g_bsp_cfg_option_setting_osis[] = {BSP_CFG_OPTION_SETTING_OSIS}; +#endif +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h new file mode 100644 index 0000000000..28ce595d95 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA6M3 RA6M3 + * @includedoc config_bsp_ra6m3_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA6M3) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_peripheral.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_peripheral.h new file mode 100644 index 0000000000..cbe2f14b35 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra6m3/bsp_peripheral.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_PERIPHERAL_H +#define BSP_PERIPHERAL_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// *UNCRUSTIFY-OFF* + +#define BSP_PERIPHERAL_ACMP_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3FU) +#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AMI_PRESENT (1) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_PRESENT (1) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_CANFD_PRESENT (0) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_PRESENT (0) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (0) +#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (0) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_PRESENT (1) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DAC_B_PRESENT (0) +#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DRW_PRESENT (1) +#define BSP_PERIPHERAL_DSMIF_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ECCMB_PRESENT (0) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ESWM_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFFU) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7U) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (0) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IPC_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (1) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_PRESENT (1) +#define BSP_PERIPHERAL_KINT_PRESENT (1) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_CSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_PHY_PRESENT (0) +#define BSP_PERIPHERAL_MMF_PRESENT (1) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MRMS_PRESENT (0) +#define BSP_PERIPHERAL_MRRGE_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_NPU_PRESENT (0) +#define BSP_PERIPHERAL_OCD_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_PRESENT (1) +#define BSP_PERIPHERAL_PDM_PRESENT (0) +#define BSP_PERIPHERAL_PDM_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (1) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFFU) +#define BSP_PERIPHERAL_PSCU_PRESENT (0) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (1) +#define BSP_PERIPHERAL_QSPI_PRESENT (1) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RSIP_PRESENT (1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_PRESENT (1) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x3FFU) +#define BSP_PERIPHERAL_SCI_B_PRESENT (0) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_PRESENT (1) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SPI_B_PRESENT (0) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SPMON_PRESENT (1) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRC_PRESENT (1) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (1) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_PRESENT (0) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TZF_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ULPT_PRESENT (0) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_USBCC_PRESENT (0) +#define BSP_PERIPHERAL_VIN_PRESENT (0) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h new file mode 100644 index 0000000000..552afc809e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h @@ -0,0 +1,406 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8D1 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* UNCRUSTIFY-OFF */ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list is device specific. + * */ +typedef enum e_elc_event_ra8d1 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x011), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x012), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x013), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x014), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x015), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x016), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x017), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x018), // DMAC7 transfer end + ELC_EVENT_DTC_END = (0x021), // DTC transfer end + ELC_EVENT_DTC_COMPLETE = (0x022), // DTC transfer complete + ELC_EVENT_DMA_TRANSERR = (0x027), // DMA/DTC transfer error + ELC_EVENT_DBG_CTIIRQ0 = (0x029), // Coresight Crosstrigger Event + ELC_EVENT_DBG_CTIIRQ1 = (0x02A), // Coresight Crosstrigger Event + ELC_EVENT_DBG_JBRXI = (0x02B), // JB RXI + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_VBATT_TADI = (0x03D), // VBATT Tamper Detection + ELC_EVENT_CGC_MOSC_STOP = (0x03E), // Main Clock oscillation stop + ELC_EVENT_ULPT0_INT = (0x040), // ULPT0 Underflow + ELC_EVENT_ULPT0_COMPARE_A = (0x041), // ULPT0 Compare match A + ELC_EVENT_ULPT0_COMPARE_B = (0x042), // ULPT0 Compare match B + ELC_EVENT_ULPT1_INT = (0x043), // ULPT1 Underflow + ELC_EVENT_ULPT1_COMPARE_A = (0x044), // ULPT1 Compare match A + ELC_EVENT_ULPT1_COMPARE_B = (0x045), // ULPT1 Compare match B + ELC_EVENT_AGT0_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT1_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT0_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_RTC_ALARM = (0x055), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x056), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x057), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x058), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x059), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x05A), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x05B), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x05C), // Receive data full + ELC_EVENT_IIC0_TXI = (0x05D), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x05E), // Transmit end + ELC_EVENT_IIC0_ERI = (0x05F), // Transfer error + ELC_EVENT_IIC0_WUI = (0x060), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x061), // Receive data full + ELC_EVENT_IIC1_TXI = (0x062), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x063), // Transmit end + ELC_EVENT_IIC1_ERI = (0x064), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x06B), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x06C), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x06D), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x06E), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x06F), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x070), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x071), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x072), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x073), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x074), // Receive data full + ELC_EVENT_SSI0_INT = (0x076), // Error interrupt + ELC_EVENT_SSI1_TXI = (0x079), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x079), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x07A), // Error interrupt + ELC_EVENT_ACMPHS0_INT = (0x07B), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x07C), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x083), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x084), // Software event 1 + ELC_EVENT_IOPORT_EVENT_1 = (0x088), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x089), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x08A), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x08B), // Port 4 event + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x08C), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x08D), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x08E), // Overflow interrupt + ELC_EVENT_POEG0_EVENT = (0x08F), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x090), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x091), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x092), // Port Output disable 3 interrupt + ELC_EVENT_OPS_UVW_EDGE = (0x0A0), // UVW edge event + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0A1), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0A2), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0A3), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0A4), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0A5), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0A6), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0A7), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0A8), // Underflow + ELC_EVENT_GPT0_PC = (0x0A9), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0AA), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0AB), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0AC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0AD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0AE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0AF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0B0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0B1), // Underflow + ELC_EVENT_GPT1_PC = (0x0B2), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0B3), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0B4), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0B5), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0B6), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0B7), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0B8), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0B9), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0BA), // Underflow + ELC_EVENT_GPT2_PC = (0x0BB), // Period count function finish + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0BC), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0BD), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0BE), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0BF), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0C0), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0C1), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0C2), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0C3), // Underflow + ELC_EVENT_GPT3_PC = (0x0C4), // Period count function finish + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0C5), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0C6), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0C7), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0C8), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0C9), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0CA), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0CB), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0CC), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0D7), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0D8), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0D9), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0DA), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0DB), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0DC), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0DD), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0DE), // Underflow + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0E0), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x0E1), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x0E2), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x0E3), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x0E4), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x0E5), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x0E6), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x0E7), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x0E9), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x0EA), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x0EB), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x0EC), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x0ED), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x0EE), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x0EF), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x0F0), // Underflow + ELC_EVENT_GPT8_PC = (0x0F1), // Period count function finish + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x0F2), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x0F3), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x0F4), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x0F5), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x0F6), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x0F7), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x0F8), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x0F9), // Underflow + ELC_EVENT_GPT9_PC = (0x0FA), // Period count function finish + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x0FB), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x0FC), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x0FD), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x0FE), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x0FF), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x100), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x101), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x102), // Underflow + ELC_EVENT_GPT10_PC = (0x103), // Period count function finish + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x104), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x105), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x106), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x107), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x108), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x109), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x10A), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x10B), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x10D), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x10E), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x10F), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x110), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x111), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x112), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x113), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x114), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x116), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x117), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x118), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x119), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x11A), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x11B), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x11C), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x11D), // Underflow + ELC_EVENT_EDMAC0_EINT = (0x120), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x121), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x122), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x123), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x124), // Receive data full + ELC_EVENT_SCI0_TXI = (0x125), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x126), // Transmit end + ELC_EVENT_SCI0_ERI = (0x127), // Receive error + ELC_EVENT_SCI0_AED = (0x128), // Active edge detection + ELC_EVENT_SCI0_BFD = (0x129), // Break field detection + ELC_EVENT_SCI0_AM = (0x12A), // Address match event + ELC_EVENT_SCI1_RXI = (0x12B), // Receive data full + ELC_EVENT_SCI1_TXI = (0x12C), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x12D), // Transmit end + ELC_EVENT_SCI1_ERI = (0x12E), // Receive error + ELC_EVENT_SCI1_AED = (0x12F), // Active edge detection + ELC_EVENT_SCI1_BFD = (0x130), // Break field detection + ELC_EVENT_SCI1_AM = (0x131), // Address match event + ELC_EVENT_SCI2_RXI = (0x132), // Receive data full + ELC_EVENT_SCI2_TXI = (0x133), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x134), // Transmit end + ELC_EVENT_SCI2_ERI = (0x135), // Receive error + ELC_EVENT_SCI2_AM = (0x138), // Address match event + ELC_EVENT_SCI3_RXI = (0x139), // Receive data full + ELC_EVENT_SCI3_TXI = (0x13A), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x13B), // Transmit end + ELC_EVENT_SCI3_ERI = (0x13C), // Receive error + ELC_EVENT_SCI3_AM = (0x13F), // Address match event + ELC_EVENT_SCI4_RXI = (0x140), // Receive data full + ELC_EVENT_SCI4_TXI = (0x141), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x142), // Transmit end + ELC_EVENT_SCI4_ERI = (0x143), // Receive error + ELC_EVENT_SCI4_AM = (0x146), // Address match event + ELC_EVENT_SCI9_RXI = (0x163), // Receive data full + ELC_EVENT_SCI9_TXI = (0x164), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x165), // Transmit end + ELC_EVENT_SCI9_ERI = (0x166), // Receive error + ELC_EVENT_SCI9_AM = (0x169), // Address match event + ELC_EVENT_SPI0_RXI = (0x178), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x179), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x17A), // Idle + ELC_EVENT_SPI0_ERI = (0x17B), // Error + ELC_EVENT_SPI0_TEI = (0x17C), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x17D), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x17E), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x17F), // Idle + ELC_EVENT_SPI1_ERI = (0x180), // Error + ELC_EVENT_SPI1_TEI = (0x181), // Transmission complete event + ELC_EVENT_XSPI_ERR = (0x182), // xSPI Error + ELC_EVENT_XSPI_CMP = (0x183), // xSPI Complete + ELC_EVENT_CAN_RXF = (0x185), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x186), // Global error + ELC_EVENT_CAN0_DMAREQ0 = (0x187), // RX fifo DMA request 0 + ELC_EVENT_CAN0_DMAREQ1 = (0x188), // RX fifo DMA request 1 + ELC_EVENT_CAN1_DMAREQ0 = (0x18B), // RX fifo DMA request 0 + ELC_EVENT_CAN1_DMAREQ1 = (0x18C), // RX fifo DMA request 1 + ELC_EVENT_CAN0_TX = (0x18F), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x190), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x191), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x192), // Channel DMA request + ELC_EVENT_CAN0_RXMB = (0x193), // Receive message buffer interrupt + ELC_EVENT_CAN1_TX = (0x194), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x195), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x196), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x197), // Channel DMA request + ELC_EVENT_CAN1_RXMB = (0x198), // Receive message buffer interrupt + ELC_EVENT_CAN0_MRAM_ERI = (0x19B), // CANFD0 ECC error + ELC_EVENT_CAN1_MRAM_ERI = (0x19C), // CANFD1 ECC error + ELC_EVENT_I3C0_RESPONSE = (0x19D), // Response status buffer full + ELC_EVENT_I3C0_COMMAND = (0x19E), // Command buffer empty + ELC_EVENT_I3C0_IBI = (0x19F), // IBI status buffer full + ELC_EVENT_I3C0_RX = (0x1A0), // Receive + ELC_EVENT_IICB0_RXI = (0x1A0), // Receive + ELC_EVENT_I3C0_TX = (0x1A1), // Transmit + ELC_EVENT_IICB0_TXI = (0x1A1), // Transmit + ELC_EVENT_I3C0_RCV_STATUS = (0x1A2), // Receive status buffer full + ELC_EVENT_I3C0_HRESP = (0x1A3), // High priority response queue full + ELC_EVENT_I3C0_HCMD = (0x1A4), // High priority command queue empty + ELC_EVENT_I3C0_HRX = (0x1A5), // High priority rx data buffer full + ELC_EVENT_I3C0_HTX = (0x1A6), // High priority tx data buffer empty + ELC_EVENT_I3C0_TEND = (0x1A7), // Transmit end + ELC_EVENT_IICB0_TEI = (0x1A7), // Transmit end + ELC_EVENT_I3C0_EEI = (0x1A8), // Error + ELC_EVENT_IICB0_ERI = (0x1A8), // Error + ELC_EVENT_I3C0_STEV = (0x1A9), // Synchronous timing + ELC_EVENT_I3C0_MREFOVF = (0x1AA), // MREF counter overflow + ELC_EVENT_I3C0_MREFCPT = (0x1AB), // MREF capture + ELC_EVENT_I3C0_AMEV = (0x1AC), // Additional master-initiated bus event + ELC_EVENT_I3C0_WU = (0x1AD), // Wake-up Condition Detection interrupt + ELC_EVENT_ADC0_SCAN_END = (0x1AE), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x1AF), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x1B0), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x1B1), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x1B2), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x1B3), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x1B4), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x1B5), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x1B6), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x1B7), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x1B8), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x1B9), // Compare mismatch + ELC_EVENT_DOC_INT = (0x1BA), // Data operation circuit interrupt + ELC_EVENT_RSIP_TADI = (0x1BC), // RSIP Tamper Detection + ELC_EVENT_GLCDC_LINE_DETECT = (0x1CD), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x1CE), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x1CF), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x1D0), // DRW interrupt + ELC_EVENT_MIPIDSI_SEQ0 = (0x1D3), // Sequence operation channel 0 interrupt + ELC_EVENT_MIPIDSI_SEQ1 = (0x1D4), // Sequence operation channel 1 interrupt + ELC_EVENT_MIPIDSI_VIN1 = (0x1D5), // Video-Input operation channel1 interrupt + ELC_EVENT_MIPIDSI_RCV = (0x1D6), // DSI packet receive interrupt + ELC_EVENT_MIPIDSI_FERR = (0x1D7), // DSI fatal error interrupt + ELC_EVENT_MIPIDSI_PPI = (0x1D8), // DSI D-PHY PPI interrupt + ELC_EVENT_CEU_CEUI = (0x1DA) // CEU interrupt +} elc_event_t; + +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) + +#define ELC_PERIPHERAL_NUM (31U) +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +/** Possible peripherals to be linked to event signals + * @note This list is device specific. + * */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_ADC1 = (10), + ELC_PERIPHERAL_ADC1_B = (11), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_I3C = (30) +} elc_peripheral_t; + +/** Positions of event link set registers (ELSRs) available on this MCU */ +#define BSP_ELC_PERIPHERAL_MASK (0x4003FFFFU) + +/* UNCRUSTIFY-ON */ +/** @} (end addtogroup BSP_MCU_RA8D1) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h new file mode 100644 index 0000000000..905f50ab04 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h @@ -0,0 +1,627 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_peripheral.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x10U) +#if (BSP_CFG_XTAL_HZ >= (24000000)) + #define CGC_MAINCLOCK_DRIVE (0x5U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (8000000)) + #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#else + #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#endif + +// *UNCRUSTIFY-OFF* + +#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1UL) // Operation stabilization wait time. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) // The IVREF selection that corresponds to the internal voltage reference. + +#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. +#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. +#define BSP_FEATURE_ADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the ADC. +#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. +#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK (0x000F01FFUL) // Mask of available channels in ADC unit 0. +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK (0x007F007FUL) // Mask of available channels in ADC unit 1. +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. + +#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS_MASK (0x00ULL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS_MASK (0x00ULL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_D_CHANNELS_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_IS_ADC12 (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2U) // Number of channels for only AGT (not AGTW) peripherals. +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03UL) // A mask of all valid AGTx channels. + +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. +#define BSP_FEATURE_BSP_HAS_DSMIF_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_DTCM (1UL) // Indicates DTCM is available. +#define BSP_FEATURE_BSP_HAS_ESC_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (1UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. +#define BSP_FEATURE_BSP_HAS_ITCM (1UL) // Indicates ITCM is available. +#define BSP_FEATURE_BSP_HAS_OFS2 (1UL) // Indicates the OFS2 register is available. +#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. +#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. +#define BSP_FEATURE_BSP_HAS_SYRACCR (1UL) // SYRACCR register is available. +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. +#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. +#define BSP_FEATURE_BSP_NUM_PMSAR (12UL) // Number of available Port Security Attribution Registers. +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. +#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. +#define BSP_FEATURE_BSP_PART_NUMBER_OFFSET (0x00UL) // Bit offset of the Part Number in the mcu info block. +#define BSP_FEATURE_BSP_PART_NUMBER_POINTER (0x030080F0UL) // Address of the Part Numbering register (PNR). +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. +#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x03008190UL) // Address of the MCU Unique ID register (UIDR). +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. + +#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CANFD_FD_SUPPORT (1UL) // Flexible data rate support. +#define BSP_FEATURE_CANFD_HAS_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. +#define BSP_FEATURE_CANFD_LITE (1UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. +#define BSP_FEATURE_CANFD_NUM_CHANNELS (1UL) // Number of CANFD channels per CANFD peripheral instance. +#define BSP_FEATURE_CANFD_NUM_INSTANCES (2UL) // Number of hardware instances of the CANFD peripheral. + +#define BSP_FEATURE_CEC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CEC_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0UL) // Indicates the system clock can be sourced by the LOCO. +#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK (1UL) // CPU Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK1 (0UL) // CPU1 Clock is available. +#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. +#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. +#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. +#define BSP_FEATURE_CGC_HAS_MOCO (1UL) // Middle clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MOSC (1UL) // Main clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MRICLK (0UL) // MRAM bus clock is available. +#define BSP_FEATURE_CGC_HAS_NPUCLK (0UL) // NPU clock is available. +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. +#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. +#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. +#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. +#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. +#define BSP_FEATURE_CGC_HAS_PCLKE (1UL) // Peripheral module clock E is available. +#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. +#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. +#define BSP_FEATURE_CGC_HAS_SOPCCR (0UL) // SOPCCR register is available. +#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0UL) // SRAMPRCR2 register is available. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_1) // Reset value of the ICLK divider. +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. +#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ (12000000UL) // Maximum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ (6000000UL) // Minimum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ (48000000UL) // Maximum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ (8000000UL) // Minimum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000UL) // Maximum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000UL) // Minimum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (3UL) // Number of output clocks for PLL1. +#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (3UL) // Number of output clocks for PLL2. +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (480000000UL) // Maximum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (40000000UL) // Minimum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLLCCR_TYPE (3UL) // Indicates the type of PLLCCR register and PLL. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (1440000000UL) // PLL VCO maximum frequency. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (640000000UL) // PLL VCO minimum frequency. +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. +#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIVCR.PCLKB. +#define BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK (0UL) // Requires the SCKDIVCR2.CPUCLK1 bits to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. +#define BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK (0UL) // Requires the bits [11:8] to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SODRV_MASK (0x03UL) // Sub-clock drive field mask. +#define BSP_FEATURE_CGC_SODRV_SHIFT (0UL) // Sub-clock drive field shift. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8UL) // Bit offset for SRAMPRCR.KW field. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5U) // Write enable key code for SRAMPRCR bit. +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00UL) // Reset value for the SCKDIVCR register. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. + +#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. +#define BSP_FEATURE_CRC_HAS_SNOOP (1UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. +#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x04UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. + +#define BSP_FEATURE_CTSU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. +#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. +#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. +#define BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL (1UL) // DAC output can be routed to specific extra internal modules using DAASWCR register. +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. + +#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (2UL) // Number of available channels per DAC12 instance. +#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. + +#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DMAC_HAS_DELSR (1UL) // DELSRn registers are available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). +#define BSP_FEATURE_DMAC_NUM_CHANNELS (8UL) // Number of DMAC channels available. + +#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DOC_VERSION (2UL) // The version of the DOC peripheral. + +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. + +#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. + +#define BSP_FEATURE_ELC_VERSION (2UL) // Version of the ELC peripheral. + +#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESC_NUM_PORTS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ESWM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_FRER_TABLE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_TIMER_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GWCA_PORT (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_DOMAIN (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. +#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // The number of AXI bus descriptors available to Ethernet components. +#define BSP_FEATURE_ETHER_NUM_CHANNELS (1UL) // Number of available ethernet PHYs. +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (1UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. + +#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (64UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. +#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (4L) // Number of non-secure application anti-rollback counters that can be configured. +#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (256UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. +#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (64UL) // Number of counter bits for the ARC_OEMBL counter. +#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (64UL) // Number of counter bits for the ARC_SEC counter. +#define BSP_FEATURE_FLASH_CACHE (1UL) // Flash cache is present. +#define BSP_FEATURE_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. +#define BSP_FEATURE_FLASH_CODE_CACHE_VERSION (0UL) // Version of C-Cache implemented in a CM33 core. +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x02000000UL) // Start address of the Code Flash region. +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x27000000UL) // Start address of the Data Flash region. +#define BSP_FEATURE_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). +#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (1UL) // Flash supports anti-rollback counter (ARC_* registers are available). +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (712UL) // Size of the user lockable areas (non-OFS registers). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x27030098UL) // Start address of the first non-OFS lockable word by LK_CD_A0. + +#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x02200000UL) // Start of the second code flash bank. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. +#define BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE (0UL) // Constraints exist for flash cache operation during flash programming access. +#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1UL) // Device contains two code banks. +#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. + +#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0xFFUL) // Mask of 32-bit GPT channel indices. +#define BSP_FEATURE_GPT_AD_CONVERSION_START_CHANNEL_MASK (0xFFUL) // Mask of GPT channels supporting A/D conversion start. +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (1UL) // GPT A/D conversion start request is directly output to ADC instead of via the ELC. +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFFUL) // Mask of channels that support event count input (has GTUPSR register). +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. +#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available, GPTE implementations have a GTITC register. +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available, GPTEH implementations have a PDG module. +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFFUL) // Mask of channels that support dead time control. +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. +#define BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. +#define BSP_FEATURE_GPT_MSTP_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. +#define BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. +#define BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED (0UL) // At least one GPT channel supports polarity inversion of the GTIOCnA or GTIOCnB I/O pins. +#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. + +#define BSP_FEATURE_I3C_IS_AVAILABLE (1UL) +#define BSP_FEATURE_I3C_HAS_CLOCK (1UL) // Indicates there is a separate clock for the I3C. +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1UL) // I3C support high data rate mode. +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (8UL) // Maximum number of bus devices. +#define BSP_FEATURE_I3C_MSTP_OFFSET (4UL) // Offset of the MSTP bit for the I3C peripherals. +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16UL) // Depth of the normal transmit data buffer. +#define BSP_FEATURE_I3C_NUM_CHANNELS (1UL) // Total number of available channels. + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. +#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. +#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. +#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. +#define BSP_FEATURE_ICU_WUPEN_MASK (0x00007F08FF1DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. + +#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER (5UL) // Multiplication factor to calculate SDA bus free time. +#define BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA (0UL) // SCL status needs to be checked before writing the transmission data in master mode. +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK (0x01UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x01UL) // Mask of available IIC_B or compatible I3C channels. +#define BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK (3UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_HAS_CLOCK (0UL) // Indicates there is a separate IIC clock. +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03UL) // Mask of available IIC channels. + +#define BSP_FEATURE_IOPORT_CCD_PINS_MASK (0x00UL) // Mask of valid indices for CCD pins. +#define BSP_FEATURE_IOPORT_ELC_PORTS_MASK (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. +#define BSP_FEATURE_IOPORT_HAS_LVOCR (1UL) // The LVOCR register is available. +#define BSP_FEATURE_IOPORT_VERSION (2UL) // Version of the system PFS block. + +#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) // Frequency of the independent watchdog clock source. +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (1UL) // IWDT peripheral supports register start mode. + +#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. + +#define BSP_FEATURE_LCD_HAS_CLOCK (1UL) // Indicates there is a separate clock for the LCD. + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x0013FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. +#define BSP_FEATURE_LPM_DPSIER_MASK (0xAF1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. +#define BSP_FEATURE_LPM_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (1UL) // The device supports deep sleep mode. +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE (1UL) // The DPSBYCR.DCSSMODE field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0UL) // The DPSBYCR.DEEPCUT field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0UL) // The DPSBYCR.DPSBY field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (1UL) // The DPSBYCR.SRKEEP field is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. +#define BSP_FEATURE_LPM_HAS_LDO_SKEEP (1UL) // PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers are available. +#define BSP_FEATURE_LPM_HAS_LPSCR (1UL) // The LPSCR register is available. +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (1UL) // The PDRAMSCRn registers are available. +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (0UL) // The SBYCR.SSBY field is available. +#define BSP_FEATURE_LPM_HAS_SNOOZE (0UL) // The MCU supports Snooze. +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0UL) // The SNZEDCR1 register is available. +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0UL) // The SNZREQCR1 register is available. +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. +#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x00UL) // Mask of valid bits for the SNZEDCRn registers. +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x00ULL) // Mask of valid bits for the SNZREQCRn registers. +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. + +#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. +#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage low threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage low threshold. +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_3_86V) // Typical higher bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_1_71V) // Typical lower bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (30UL) // Maximum stabilization time to wait after LVD1 is enabled. +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_3_86V) // Typical higher bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_1_71V) // Typical lower bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (30UL) // Maximum stabilization time to wait after LVD2 is enabled. +#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1UL) // Voltage monitors support rising edge detections (i.e. +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. +#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. +#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. + +#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. + +#define BSP_FEATURE_MIPI_CSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_DSI_IS_AVAILABLE (1UL) + +#define BSP_FEATURE_MIPI_PHY_IS_AVAILABLE (1UL) + +#define BSP_FEATURE_MRAM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x80000000UL) // Start address of the CS0 memory mapped region for OSPI. +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x90000000UL) // Start address of the CS1 memory mapped region for OSPI. +#define BSP_FEATURE_OSPI_HAS_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. + +#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (1UL) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000UL) // Start address of the CS0 memory mapped region for OSPI_B. +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000UL) // Start address of the CS1 memory mapped region for OSPI_B. +#define BSP_FEATURE_OSPI_B_UNIT_COUNT (1UL) // Number of OSPI_B peripheral units available. + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. +#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. +#define BSP_FEATURE_POEG_MSTP_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. + +#define BSP_FEATURE_QSPI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. +#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. +#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E11A. +#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E31A. +#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP-E50D. +#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (1UL) // The device supports cryptography using RSIP-E51A. +#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. +#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. +#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. +#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (0UL) // The device supports cryptography using SCE9. +#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_RTC_HAS_ALARM1 (0UL) // Alarm 1 is available. +#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. +#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. +#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. +#define BSP_FEATURE_RTC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. +#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. + +#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK (0x00UL) // Mask of channels with data compare match (DCCR) available. +#define BSP_FEATURE_SCI_CHANNELS_MASK (0x021FUL) // Mask of available SCI channels. +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. +#define BSP_FEATURE_SCI_HAS_CLOCK (1UL) // Indicates there is a separate SCI clock. +#define BSP_FEATURE_SCI_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. +#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. +#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. +#define BSP_FEATURE_SCI_LIN_CHANNELS_MASK (0x03UL) // Mask of channels that can support LIN. +#define BSP_FEATURE_SCI_SPI_SCKSEL_MASK (1UL) // Mask indicating CCR4.SCKSEL is available. +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK (0x00UL) // List of channels that do not support ABCSE functionality. +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK (0x021FUL) // Mask of channels which support CTS external pins. +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK (0x021FUL) // Mask of channels which support the UART FIFO. +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. +#define BSP_FEATURE_SCI_VERSION (2UL) // Version of the SCI peripheral. + +#define BSP_FEATURE_SDADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. + +#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x03UL) // Mask of valid SDHI channels. + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x68000000UL) // Start address of the external address space for SDRAM memory. + +#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED (1UL) // Burst transfer without delay between frames is supported. +#define BSP_FEATURE_SPI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. +#define BSP_FEATURE_SPI_HAS_CLOCK (1UL) // Indicates there is a separate clock for the SPI. +#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. +#define BSP_FEATURE_SPI_NUM_CHANNELS (2UL) // Number of available SPI channels. +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. + +#define BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR (0UL) // Flag indicating that SRAMSABAR2 and SRAMSABAR3 are present. +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. + +#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3UL) // Mask of valid SSI channel indices. + +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS (240000000UL) // Maximum frequency allowed before requiring five wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS (192000000UL) // The maximum frequency allowed without having four ROM wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS (120000000UL) // The maximum frequency that can be used before wait cycles are necessary. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS (48000000UL) // Maximum frequency allowed before requiring one wait cycle. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS (144000000UL) // Maximum frequency allowed before requiring three wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS (96000000UL) // Maximum frequency allowed before requiring two wait cycles. + +#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. + +#define BSP_FEATURE_TSN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. +#define BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available for TSN. +#define BSP_FEATURE_TSN_CALIBRATION32_MASK (0xFFFFUL) // Mask of valid bits for TSN calibration. +#define BSP_FEATURE_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. +#define BSP_FEATURE_TSN_HAS_LOW_TEMP_REG (0UL) // Determine if the TSCDRL (Low Temperature) is present. +#define BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG (0UL) // Determine if the TSCDRR (Room Temperature) is present. +#define BSP_FEATURE_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. + +#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. +#define BSP_FEATURE_TZ_HAS_TZFSAR (0UL) // Specifies the TrustZone filter can be secured. +#define BSP_FEATURE_TZ_NS_OFFSET (0x10000000UL) // Offset for the Non-secure address space of a peripheral. +#define BSP_FEATURE_TZ_VERSION (2UL) // Version of the TrustZone implementation. + +#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ULPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ULPT_NUM_CHANNELS_AVAILABLE (2UL) // Number of channels available for ULPT. +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (3UL) // Mask of available channels for ULPT. + +#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) +#define BSP_FEATURE_USB_HAS_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. +#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. +#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. +#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. +#define BSP_FEATURE_USB_HAS_USB60_CLOCK (1UL) // Indicates the USB60 clock is available. +#define BSP_FEATURE_USB_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. +#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. +#define BSP_FEATURE_USB_HAS_USBFS_BC (0UL) // Supports battery charging in full-speed mode. +#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. +#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0UL) // Indicates the PHYSECTRL.CNEN field is available. +#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. +#define BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR2 register. + +#define BSP_FEATURE_VIN_IS_AVAILABLE (0UL) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_linker.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_linker.c new file mode 100644 index 0000000000..1c0e7b48c3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_linker.c @@ -0,0 +1,81 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#if defined BSP_CFG_OPTION_SETTING_OFS0 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_cfg_option_setting_ofs0[] = {BSP_CFG_OPTION_SETTING_OFS0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS2 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs2") g_bsp_cfg_option_setting_ofs2[] = {BSP_CFG_OPTION_SETTING_OFS2}; +#endif +#if defined BSP_CFG_OPTION_SETTING_DUALSEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_dualsel") g_bsp_cfg_option_setting_dualsel[] = {BSP_CFG_OPTION_SETTING_DUALSEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1 +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_cfg_option_setting_ofs1[] = {BSP_CFG_OPTION_SETTING_OFS1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel") g_bsp_cfg_option_setting_banksel[] = {BSP_CFG_OPTION_SETTING_BANKSEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps") g_bsp_cfg_option_setting_bps[] = {BSP_CFG_OPTION_SETTING_BPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps") g_bsp_cfg_option_setting_pbps[] = {BSP_CFG_OPTION_SETTING_PBPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_cfg_option_setting_ofs1_sec[] = {BSP_CFG_OPTION_SETTING_OFS1_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sec") g_bsp_cfg_option_setting_banksel_sec[] = {BSP_CFG_OPTION_SETTING_BANKSEL_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec") g_bsp_cfg_option_setting_bps_sec[] = {BSP_CFG_OPTION_SETTING_BPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec") g_bsp_cfg_option_setting_pbps_sec[] = {BSP_CFG_OPTION_SETTING_PBPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_cfg_option_setting_ofs1_sel[] = {BSP_CFG_OPTION_SETTING_OFS1_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_cfg_option_setting_banksel_sel[] = {BSP_CFG_OPTION_SETTING_BANKSEL_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel") g_bsp_cfg_option_setting_bps_sel[] = {BSP_CFG_OPTION_SETTING_BPS_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_DATA_FLASH_FSBLCTRL0 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl0") g_bsp_cfg_option_setting_data_flash_fsblctrl0[] = {BSP_CFG_OPTION_SETTING_DATA_FLASH_FSBLCTRL0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_DATA_FLASH_FSBLCTRL1 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl1") g_bsp_cfg_option_setting_data_flash_fsblctrl1[] = {BSP_CFG_OPTION_SETTING_DATA_FLASH_FSBLCTRL1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_DATA_FLASH_FSBLCTRL2 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_fsblctrl2") g_bsp_cfg_option_setting_data_flash_fsblctrl2[] = {BSP_CFG_OPTION_SETTING_DATA_FLASH_FSBLCTRL2}; +#endif +#if defined BSP_CFG_OPTION_SETTING_DATA_FLASH_SACC0 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_sacc0") g_bsp_cfg_option_setting_data_flash_sacc0[] = {BSP_CFG_OPTION_SETTING_DATA_FLASH_SACC0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_DATA_FLASH_SACC1 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_sacc1") g_bsp_cfg_option_setting_data_flash_sacc1[] = {BSP_CFG_OPTION_SETTING_DATA_FLASH_SACC1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_DATA_FLASH_SAMR && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_data_flash_samr") g_bsp_cfg_option_setting_data_flash_samr[] = {BSP_CFG_OPTION_SETTING_DATA_FLASH_SAMR}; +#endif +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_mcu_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_mcu_info.h new file mode 100644 index 0000000000..0dcf62f2de --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_mcu_info.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA8D1 RA8D1 + * @includedoc config_bsp_ra8d1_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA8D1) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_override.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_override.h new file mode 100644 index 0000000000..9a1bcb5b3e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_override.h @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8D1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8D1) */ + +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#if __has_include("r_ospi_b_device_types.h") + #include "r_ospi_b_device_types.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MCU. */ + +#define BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T +#define BSP_OVERRIDE_GROUP_IRQ_T +#define BSP_OVERRIDE_LVD_PERIPHERAL_T + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, + * PCLKS A-D. */ +typedef enum e_cgc_sys_clock_div +{ + CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1 + CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2 + CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4 + CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8 + CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 + CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 + CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 + CGC_SYS_CLOCK_DIV_3 = 8, ///< System clock divided by 3 + CGC_SYS_CLOCK_DIV_6 = 9, ///< System clock divided by 6 + CGC_SYS_CLOCK_DIV_12 = 10, ///< System clock divided by 12 +} cgc_sys_clock_div_t; + +/* Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_MPU_BUS_TZF = 12, ///< MPU Bus or TrustZone Filter Error + BSP_GRP_IRQ_COMMON_MEMORY = 13, ///< SRAM ECC or SRAM Parity Error + BSP_GRP_IRQ_LOCKUP = 15, ///< LockUp Error +} bsp_grp_irq_t; + +/** The thresholds supported by each MCU are in the MCU User's Manual as well as + * in the r_lvd module description on the stack tab of the RA project. */ +typedef enum +{ + LVD_THRESHOLD_MONITOR_LEVEL_3_86V = 0x03UL, ///< 3.86V + LVD_THRESHOLD_MONITOR_LEVEL_3_14V = 0x04UL, ///< 3.14V + LVD_THRESHOLD_MONITOR_LEVEL_3_10V = 0x05UL, ///< 3.10V + LVD_THRESHOLD_MONITOR_LEVEL_3_08V = 0x06UL, ///< 3.08V + LVD_THRESHOLD_MONITOR_LEVEL_2_85V = 0x07UL, ///< 2.85V + LVD_THRESHOLD_MONITOR_LEVEL_2_83V = 0x08UL, ///< 2.83V + LVD_THRESHOLD_MONITOR_LEVEL_2_80V = 0x09UL, ///< 2.80V + LVD_THRESHOLD_MONITOR_LEVEL_2_62V = 0x0AUL, ///< 2.62V + LVD_THRESHOLD_MONITOR_LEVEL_2_33V = 0x0BUL, ///< 2.33V + LVD_THRESHOLD_MONITOR_LEVEL_1_90V = 0x0CUL, ///< 1.90V + LVD_THRESHOLD_MONITOR_LEVEL_1_86V = 0x0DUL, ///< 1.86V + LVD_THRESHOLD_MONITOR_LEVEL_1_74V = 0x0EUL, ///< 1.74V + LVD_THRESHOLD_MONITOR_LEVEL_1_71V = 0x0FUL, ///< 1.71V + LVD_THRESHOLD_NOT_AVAILABLE = 0xFFUL, ///< Not Used +} lvd_threshold_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_peripheral.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_peripheral.h new file mode 100644 index 0000000000..25bf4dc681 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/bsp_peripheral.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_PERIPHERAL_H +#define BSP_PERIPHERAL_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// *UNCRUSTIFY-OFF* + +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_PRESENT (1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DAC_B_PRESENT (0) +#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DRW_PRESENT (1) +#define BSP_PERIPHERAL_DSMIF_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ESWM_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFFU) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IPC_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_CSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (1) +#define BSP_PERIPHERAL_MIPI_PHY_PRESENT (1) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MRMS_PRESENT (0) +#define BSP_PERIPHERAL_MRRGE_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_NPU_PRESENT (0) +#define BSP_PERIPHERAL_OCD_PRESENT (1) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDM_PRESENT (0) +#define BSP_PERIPHERAL_PDM_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0xFFFU) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RSIP_PRESENT (1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_B_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x21FU) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SPI_B_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ULPT_PRESENT (1) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_USBCC_PRESENT (0) +#define BSP_PERIPHERAL_VIN_PRESENT (0) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/r_ospi_b_device_types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/r_ospi_b_device_types.h new file mode 100644 index 0000000000..854fbc88e3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8d1/r_ospi_b_device_types.h @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8D1 + * @{ + **********************************************************************************************************************/ + +#ifndef R_OSPI_B_DEVICE_TYPES_H +#define R_OSPI_B_DEVICE_TYPES_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_OVERRIDE_BSP_CLOCKS_OCTACLK_DIV_T + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** OCTACLK divider values. */ +typedef enum e_bsp_clocks_octaclk_div +{ + BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 + BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 + BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 + BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 + BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 + BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 + BSP_CLOCKS_OCTACLK_DIV_5, ///< Divide OCTA source clock by 5 +} bsp_clocks_octaclk_div_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BSP_MCU_RA8D1) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/RA8E1.ld b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/RA8E1.ld new file mode 100644 index 0000000000..16408b5afb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/RA8E1.ld @@ -0,0 +1,838 @@ +RAM_START = 0x22060000; +RAM_LENGTH = 0x00080000; +FLASH_START = 0x02000000; +FLASH_LENGTH = 0x00100000; +DATA_FLASH_START = 0x27000000; +DATA_FLASH_LENGTH = 0x00003000; +OSPI0_CS0_START = 0x80000000; +OSPI0_CS0_LENGTH = 0x10000000; +OSPI0_CS1_START = 0x90000000; +OSPI0_CS1_LENGTH = 0x10000000; +ITCM_START = 0x00000000; +ITCM_LENGTH = 0x00004000; +DTCM_START = 0x20000000; +DTCM_LENGTH = 0x00004000; +OPTION_SETTING_OFS0_START = 0x0300a100; +OPTION_SETTING_OFS0_LENGTH = 0x00000004; +OPTION_SETTING_OFS2_START = 0x0300a104; +OPTION_SETTING_OFS2_LENGTH = 0x00000004; +OPTION_SETTING_DUALSEL_START = 0x0300a110; +OPTION_SETTING_DUALSEL_LENGTH = 0x00000004; +OPTION_SETTING_OFS1_START = 0x1300a180; +OPTION_SETTING_OFS1_LENGTH = 0x00000004; +OPTION_SETTING_BANKSEL_START = 0x1300a190; +OPTION_SETTING_BANKSEL_LENGTH = 0x00000004; +OPTION_SETTING_BPS_START = 0x1300a1c0; +OPTION_SETTING_BPS_LENGTH = 0x00000010; +OPTION_SETTING_PBPS_START = 0x1300a1e0; +OPTION_SETTING_PBPS_LENGTH = 0x00000010; +OPTION_SETTING_OFS1_SEC_START = 0x0300a200; +OPTION_SETTING_OFS1_SEC_LENGTH = 0x00000004; +OPTION_SETTING_BANKSEL_SEC_START = 0x0300a210; +OPTION_SETTING_BANKSEL_SEC_LENGTH = 0x00000004; +OPTION_SETTING_BPS_SEC_START = 0x0300a240; +OPTION_SETTING_BPS_SEC_LENGTH = 0x00000010; +OPTION_SETTING_PBPS_SEC_START = 0x0300a260; +OPTION_SETTING_PBPS_SEC_LENGTH = 0x00000010; +OPTION_SETTING_OFS1_SEL_START = 0x0300a280; +OPTION_SETTING_OFS1_SEL_LENGTH = 0x00000004; +OPTION_SETTING_BANKSEL_SEL_START = 0x0300a290; +OPTION_SETTING_BANKSEL_SEL_LENGTH = 0x00000004; +OPTION_SETTING_BPS_SEL_START = 0x0300a2c0; +OPTION_SETTING_BPS_SEL_LENGTH = 0x00000010; +__vector_table_size__ = 112 * 4; + +MEMORY +{ + RAM (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_SRAM_START, LENGTH = MBED_CONFIGURED_RAM_BANK_SRAM_SIZE + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_Flash_START, LENGTH = MBED_CONFIGURED_ROM_BANK_Flash_SIZE + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + OSPI0_CS0 (rwx) : ORIGIN = OSPI0_CS0_START, LENGTH = OSPI0_CS0_LENGTH + OSPI0_CS1 (rx) : ORIGIN = OSPI0_CS1_START, LENGTH = OSPI0_CS1_LENGTH + OPTION_SETTING_OFS0 (r) : ORIGIN = OPTION_SETTING_OFS0_START, LENGTH = OPTION_SETTING_OFS0_LENGTH + OPTION_SETTING_OFS2 (r) : ORIGIN = OPTION_SETTING_OFS2_START, LENGTH = OPTION_SETTING_OFS2_LENGTH + OPTION_SETTING_DUALSEL (r) : ORIGIN = OPTION_SETTING_DUALSEL_START, LENGTH = OPTION_SETTING_DUALSEL_LENGTH + OPTION_SETTING_OFS1 (r) : ORIGIN = OPTION_SETTING_OFS1_START, LENGTH = OPTION_SETTING_OFS1_LENGTH + OPTION_SETTING_BANKSEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_START, LENGTH = OPTION_SETTING_BANKSEL_LENGTH + OPTION_SETTING_BPS (r) : ORIGIN = OPTION_SETTING_BPS_START, LENGTH = OPTION_SETTING_BPS_LENGTH + OPTION_SETTING_PBPS (r) : ORIGIN = OPTION_SETTING_PBPS_START, LENGTH = OPTION_SETTING_PBPS_LENGTH + OPTION_SETTING_OFS1_SEC (r) : ORIGIN = OPTION_SETTING_OFS1_SEC_START, LENGTH = OPTION_SETTING_OFS1_SEC_LENGTH + OPTION_SETTING_BANKSEL_SEC (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEC_START, LENGTH = OPTION_SETTING_BANKSEL_SEC_LENGTH + OPTION_SETTING_BPS_SEC (r) : ORIGIN = OPTION_SETTING_BPS_SEC_START, LENGTH = OPTION_SETTING_BPS_SEC_LENGTH + OPTION_SETTING_PBPS_SEC (r) : ORIGIN = OPTION_SETTING_PBPS_SEC_START, LENGTH = OPTION_SETTING_PBPS_SEC_LENGTH + OPTION_SETTING_OFS1_SEL (r) : ORIGIN = OPTION_SETTING_OFS1_SEL_START, LENGTH = OPTION_SETTING_OFS1_SEL_LENGTH + OPTION_SETTING_BANKSEL_SEL (r) : ORIGIN = OPTION_SETTING_BANKSEL_SEL_START, LENGTH = OPTION_SETTING_BANKSEL_SEL_LENGTH + OPTION_SETTING_BPS_SEL (r) : ORIGIN = OPTION_SETTING_BPS_SEL_START, LENGTH = OPTION_SETTING_BPS_SEL_LENGTH + ITCM (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_ITCM_START, LENGTH = MBED_CONFIGURED_RAM_BANK_ITCM_SIZE + DTCM (rwx) : ORIGIN = MBED_CONFIGURED_RAM_BANK_DTCM_START, LENGTH = MBED_CONFIGURED_RAM_BANK_DTCM_SIZE +} + +/* code entry point...need to define to keep crt0 _start out */ +ENTRY(Reset_Handler) +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + + +SECTIONS +{ + /***** OSPI0_CS1 memory section allocations ******/ + .ospi0_cs1.startof (READONLY) : + { + __ddsc_OSPI0_CS1_START = . ; + + } > OSPI0_CS1 + /***** OSPI0_CS0 memory section allocations ******/ + .ospi0_cs0.startof : + { + __ddsc_OSPI0_CS0_START = . ; + + } > OSPI0_CS0 + /* ospi0_cs0 initialized from ospi0_cs1 */ + __ospi0_cs0_from_ospi0_cs1$$ : + { + __ospi0_cs0_from_ospi0_cs1$$Base = . ;__ospi0_cs0_from_ospi0_cs1$$Load = LOADADDR(__ospi0_cs0_from_ospi0_cs1$$) ; + /* section.ospi0_cs0.from_ospi0_cs1 */ + *(.ospi0_cs0_from_ospi0_cs1) + /* section.ospi0_cs0.code_from_ospi0_cs1 */ + *(.ospi0_cs0_code_from_ospi0_cs1) + __ospi0_cs0_from_ospi0_cs1$$Limit = . ; + } > OSPI0_CS0 AT > OSPI0_CS1 + + /***** ITCM memory section allocations ******/ + .itcm.startof : + { + __ddsc_ITCM_START = . ; + + } > ITCM + /* itcm initialized from ospi0_cs1 */ + __itcm_from_ospi0_cs1$$ : + { + __itcm_from_ospi0_cs1$$Base = . ;__itcm_from_ospi0_cs1$$Load = LOADADDR(__itcm_from_ospi0_cs1$$) ; + /* section.itcm.from_ospi0_cs1 */ + *(.itcm_from_ospi0_cs1) + /* section.itcm.code_from_ospi0_cs1 */ + *(.itcm_code_from_ospi0_cs1) + __itcm_from_ospi0_cs1$$Limit = . ; + } > ITCM AT > OSPI0_CS1 + + /***** DTCM memory section allocations ******/ + .dtcm.startof : + { + __ddsc_DTCM_START = . ; + + } > DTCM + + /* Stick the vector table at start of DTCM */ + .vector_ram (NOLOAD) : + { + __vector_ram_start__ = .; + . += __vector_table_size__; + __vector_ram_end__ = .; + } > DTCM + + /* dtcm initialized from ospi0_cs1 */ + __dtcm_from_ospi0_cs1$$ : + { + __dtcm_from_ospi0_cs1$$Base = . ;__dtcm_from_ospi0_cs1$$Load = LOADADDR(__dtcm_from_ospi0_cs1$$) ; + /* section.dtcm.from_ospi0_cs1 */ + *(.dtcm_from_ospi0_cs1) + /* section.dtcm.code_from_ospi0_cs1 */ + *(.dtcm_code_from_ospi0_cs1) + __dtcm_from_ospi0_cs1$$Limit = . ; + } > DTCM AT > OSPI0_CS1 + + /***** RAM memory section allocations ******/ + .ram.startof : + { + __ddsc_RAM_START = . ; + + } > RAM + __ram_dtc_vector$$ (NOLOAD) : + { + __ram_dtc_vector$$Base = . ; + *(.fsp_dtc_vector_table) + __ram_dtc_vector$$Limit = . ; + } > RAM + /* ram initialized from ospi0_cs1 */ + __ram_from_ospi0_cs1$$ : + { + __ram_from_ospi0_cs1$$Base = . ;__ram_from_ospi0_cs1$$Load = LOADADDR(__ram_from_ospi0_cs1$$) ; + /* section.ram.from_ospi0_cs1 */ + *(.ram_from_ospi0_cs1) + /* section.ram.code_from_ospi0_cs1 */ + *(.ram_code_from_ospi0_cs1) + __ram_from_ospi0_cs1$$Limit = . ; + } > RAM AT > OSPI0_CS1 + + __ospi0_cs1_readonly$$ (READONLY) : + { + __ospi0_cs1_readonly$$Base = . ; + /* section.ospi0_cs1.readonly */ + *(.ospi0_cs1) + /* section.ospi0_cs1.code */ + *(.ospi0_cs1_code) + __ospi0_cs1_readonly$$Limit = . ; + } > OSPI0_CS1 + __ospi0_cs1_noinit$$ (NOLOAD) : + { + __ospi0_cs1_noinit$$Base = . ; + /* section.ospi0_cs1.noinit */ + *(.ospi0_cs1_noinit) + __ospi0_cs1_noinit$$Limit = . ; + } > OSPI0_CS1 + .ospi0_cs1.endof ALIGN(.,512) (READONLY) : + { + __ddsc_OSPI0_CS1_END = . ; + + } > OSPI0_CS1 + + /***** DATA_FLASH memory section allocations ******/ + .data_flash.startof (READONLY) : + { + __ddsc_DATA_FLASH_START = . ; + + } > DATA_FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from data_flash */ + __ospi0_cs0_from_data_flash$$ : + { + __ospi0_cs0_from_data_flash$$Base = . ;__ospi0_cs0_from_data_flash$$Load = LOADADDR(__ospi0_cs0_from_data_flash$$) ; + /* section.ospi0_cs0.from_data_flash */ + *(.ospi0_cs0_from_data_flash) + /* section.ospi0_cs0.code_from_data_flash */ + *(.ospi0_cs0_code_from_data_flash) + __ospi0_cs0_from_data_flash$$Limit = . ; + } > OSPI0_CS0 AT > DATA_FLASH + + /***** ITCM memory section allocations ******/ + /* itcm initialized from data_flash */ + __itcm_from_data_flash$$ : + { + __itcm_from_data_flash$$Base = . ;__itcm_from_data_flash$$Load = LOADADDR(__itcm_from_data_flash$$) ; + /* section.itcm.from_data_flash */ + *(.itcm_from_data_flash) + /* section.itcm.code_from_data_flash */ + *(.itcm_code_from_data_flash) + __itcm_from_data_flash$$Limit = . ; + } > ITCM AT > DATA_FLASH + + /***** DTCM memory section allocations ******/ + /* dtcm initialized from data_flash */ + __dtcm_from_data_flash$$ : + { + __dtcm_from_data_flash$$Base = . ;__dtcm_from_data_flash$$Load = LOADADDR(__dtcm_from_data_flash$$) ; + /* section.dtcm.from_data_flash */ + *(.dtcm_from_data_flash) + /* section.dtcm.code_from_data_flash */ + *(.dtcm_code_from_data_flash) + __dtcm_from_data_flash$$Limit = . ; + } > DTCM AT > DATA_FLASH + + /***** RAM memory section allocations ******/ + /* ram initialized from data_flash */ + __ram_from_data_flash$$ : + { + __ram_from_data_flash$$Base = . ;__ram_from_data_flash$$Load = LOADADDR(__ram_from_data_flash$$) ; + /* section.ram.from_data_flash */ + *(.ram_from_data_flash) + /* section.ram.code_from_data_flash */ + *(.ram_code_from_data_flash) + __ram_from_data_flash$$Limit = . ; + } > RAM AT > DATA_FLASH + + __data_flash_readonly$$ (READONLY) : + { + __data_flash_readonly$$Base = . ; + /* section.data_flash.readonly */ + *(.data_flash) + /* section.data_flash.code */ + *(.data_flash_code) + __data_flash_readonly$$Limit = . ; + } > DATA_FLASH + __data_flash_noinit$$ (NOLOAD) : + { + __data_flash_noinit$$Base = . ; + /* section.data_flash.noinit */ + *(.data_flash_noinit) + __data_flash_noinit$$Limit = . ; + } > DATA_FLASH + .data_flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_DATA_FLASH_END = . ; + + } > DATA_FLASH + + /***** FLASH memory section allocations ******/ + .flash.startof (READONLY) : + { + __ddsc_FLASH_START = . ; + + } > FLASH + /* MCU vector table */ + .text (READONLY) : + { + __flash_vectors$$Base = . ; _VECTORS = . ; + KEEP(*(.fixed_vectors)) + KEEP(*(.application_vectors)) + __flash_vectors$$Limit = . ; + } > FLASH + __flash_noinit$$ (NOLOAD) : + { + __flash_noinit$$Base = . ; + /* section.flash.noinit */ + *(.flash_noinit) + __flash_noinit$$Limit = . ; + } > FLASH + /***** OSPI0_CS0 memory section allocations ******/ + /* ospi0_cs0 initialized from flash */ + __ospi0_cs0_from_flash$$ : + { + __ospi0_cs0_from_flash$$Base = . ;__ospi0_cs0_from_flash$$Load = LOADADDR(__ospi0_cs0_from_flash$$) ; + /* section.ospi0_cs0.from_flash */ + *(.ospi0_cs0_from_flash) + /* section.ospi0_cs0.code_from_flash */ + *(.ospi0_cs0_code_from_flash) + __ospi0_cs0_from_flash$$Limit = . ; + } > OSPI0_CS0 AT > FLASH + /* Non-initialized, non-cached ospi0_cs0 */ + __ospi0_cs0_noinit_nocache$$ (NOLOAD) : ALIGN(32) + { + __ospi0_cs0_noinit_nocache$$Base = . ; + /* section.ospi0_cs0.noinit_nocache */ + *(.ospi0_cs0_noinit_nocache) + __ospi0_cs0_noinit_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed, non-cached ospi0_cs0 */ + __ospi0_cs0_zero_nocache$$ (NOLOAD) : + { + __ospi0_cs0_zero_nocache$$Base = . ; + /* section.ospi0_cs0.zero_nocache */ + *(.ospi0_cs0_nocache) + . = ALIGN(32); + __ospi0_cs0_zero_nocache$$Limit = . ; + } > OSPI0_CS0 + /* Non-initialized ospi0_cs0 */ + __ospi0_cs0_noinit$$ (NOLOAD) : + { + __ospi0_cs0_noinit$$Base = . ; + /* section.ospi0_cs0.noinit */ + *(.ospi0_cs0_noinit) + __ospi0_cs0_noinit$$Limit = . ; + } > OSPI0_CS0 + /* Zeroed ospi0_cs0 */ + __ospi0_cs0_zero$$ (NOLOAD) : + { + __ospi0_cs0_zero$$Base = . ; + /* section.ospi0_cs0.zero */ + *(.ospi0_cs0) + __ospi0_cs0_zero$$Limit = . ; + } > OSPI0_CS0 + .ospi0_cs0.endof ALIGN(.,512) : + { + __ddsc_OSPI0_CS0_END = . ; + + } > OSPI0_CS0 + + /***** ITCM memory section allocations ******/ + /* itcm initialized from flash */ + __itcm_from_flash$$ : + { + __itcm_from_flash$$Base = . ;__itcm_from_flash$$Load = LOADADDR(__itcm_from_flash$$) ; + /* section.itcm.from_flash */ + *(.itcm_from_flash) + /* section.itcm.code_from_flash */ + *(.itcm_code_from_flash) + __itcm_from_flash$$Limit = . ; + } > ITCM AT > FLASH + /* Non-initialized itcm */ + __itcm_noinit$$ (NOLOAD) : + { + __itcm_noinit$$Base = . ; + /* section.itcm.noinit */ + *(.itcm_noinit) + __itcm_noinit$$Limit = . ; + } > ITCM + /* Zeroed itcm */ + __itcm_zero$$ (NOLOAD) : + { + __itcm_zero$$Base = . ; + /* section.itcm.zero */ + *(.itcm) + __itcm_zero$$Limit = . ; + } > ITCM + .itcm.endof ALIGN(.,512) : + { + __ddsc_ITCM_END = . ; + + } > ITCM + + /***** DTCM memory section allocations ******/ + /* dtcm initialized from flash */ + __dtcm_from_flash$$ : + { + __dtcm_from_flash$$Base = . ;__dtcm_from_flash$$Load = LOADADDR(__dtcm_from_flash$$) ; + /* section.dtcm.from_flash */ + *(.dtcm_from_flash) + /* section.dtcm.code_from_flash */ + *(.dtcm_code_from_flash) + __dtcm_from_flash$$Limit = . ; + } > DTCM AT > FLASH + /* Non-initialized dtcm */ + __dtcm_noinit$$ (NOLOAD) : + { + __dtcm_noinit$$Base = . ; + /* section.dtcm.noinit */ + *(.dtcm_noinit) + __dtcm_noinit$$Limit = . ; + } > DTCM + /* Zeroed dtcm */ + __dtcm_zero$$ (NOLOAD) : + { + __dtcm_zero$$Base = . ; + /* section.dtcm.zero */ + *(.dtcm) + __dtcm_zero$$Limit = . ; + } > DTCM + .dtcm.endof ALIGN(.,512) : + { + __ddsc_DTCM_END = . ; + + } > DTCM + + .text (READONLY) : + { + __flash_readonly$$Base = . ; + /* section.flash.readonly */ + *(.flash) + /* section.flash.code */ + *(.flash_code) + *(.text*) + *(.rodata*) + KEEP(*(.mcuboot_sce9_key)) + KEEP(*(.version)) + __flash_readonly$$Limit = . ; + } > FLASH + __flash_ctor$$ (READONLY) : + { + + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + EXCLUDE_FILE (*crtend?.o *crtend.o) *(.dtors) + *(SORT(.dtors.*)) + *(.dtors) + + } > FLASH + __flash_preinit_array$$ (READONLY) : + { + __preinit_array_start = . ; + KEEP(*(.preinit_array)) + __preinit_array_end = . ; + } > FLASH + __flash_.got$$ (READONLY) : + { + + *(.got.plt) + *(.got) + + } > FLASH + __flash_init_array$$ (READONLY) : + { + __init_array_start = . ; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = . ; + } > FLASH + __flash_fini_array$$ (READONLY) : + { + __fini_array_start = . ; + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + __fini_array_end = . ; + } > FLASH + /* .ARM.extab sections contain exception unwinding information. */ + __flash_arm.extab$$ (READONLY) : + { + + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + } > FLASH + /* .ARM.exidx sections contains index entries for section unwinding. */ + __flash_arm.exidx$$ (READONLY) : + { + __exidx_start = . ; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + __exidx_end = . ; + } > FLASH + + __etext = .; + +/***** RAM memory section allocations ******/ + /* ram initialized from flash */ + .data : + { + __data_start__ = .; + _sdata = .; + __ram_from_flash$$Base = . ;__ram_from_flash$$Load = LOADADDR(.data) ; + /* section.ram.from_flash */ + *(.ram_from_flash) + /* section.ram.code_from_flash */ + *(.ram_code_from_flash) + *(.data*) + __ram_from_flash$$Limit = . ; + /* All data end */ + __data_end__ = .; + _edata = .; + } > RAM AT > FLASH + + .flash.endof ALIGN(.,512) (READONLY) : + { + __ddsc_FLASH_END = . ; + + } > FLASH + + /* Non-cached ram for Mbed noncached memory support */ + .noncached(NOLOAD): ALIGN(32) + { + __noncached_start = .; + *(.noncached) + . = ALIGN(32); + __noncached_end = .; + } > RAM + /* Non-initialized, non-cached ram */ + .bss (NOLOAD) : ALIGN(32) + { + __bss_start__ = .; + _sbss = .; + __ram_noinit_nocache$$Base = . ; + /* section.ram.noinit_nocache */ + *(.ram_noinit_nocache) + __ram_noinit_nocache$$Limit = . ; + } > RAM + /* Zeroed, non-cached ram */ + __ram_zero_nocache$$ (NOLOAD) : + { + __ram_zero_nocache$$Base = . ; + /* section.ram.zero_nocache */ + *(.ram_nocache) + . = ALIGN(32); + __ram_zero_nocache$$Limit = . ; + } > RAM + /* Non-initialized ram */ + __ram_noinit$$ (NOLOAD) : + { + __ram_noinit$$Base = . ; + /* Main stack region */ + __StackLimit = .; + *(.bss.g_main_stack) + __StackTop = .; + _estack = __StackTop; + PROVIDE(__stack = __StackTop); + /* Other no-init data */ + *(.ram_noinit) + *(.noinit) + __ram_noinit$$Limit = . ; + } > RAM + /* Zeroed ram */ + __ram_zero$$ (NOLOAD) : + { + __ram_zero$$Base = . ; + /* section.ram.zero */ + *(.ram) + *(.bss*) + . = ALIGN(32); + __ram_zero$$Limit = . ; + __bss_end__ = .; + _ebss = .; + } > RAM + /* Thread Stacks */ + __ram_thread_stack$$ (NOLOAD) : ALIGN(8) + { + __ram_thread_stack$$Base = . ; + KEEP(*(.stack?*)) + __ram_thread_stack$$Limit = . ; + } > RAM + .ram.endof ALIGN(.,512) : + { + __ddsc_RAM_END = . ; + /* Heap region */ + __HeapBase = .; + __end__ = .; + PROVIDE(end = .); + *(.bss.g_heap) + __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); + } > RAM + + /***** OPTION_SETTING_OFS0 memory section allocations ******/ + .option_setting_ofs0.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_START = . ; + + } > OPTION_SETTING_OFS0 + /* Option Function Select Register 0 */ + __option_setting_ofs0_reg$$ (READONLY) : + { + __option_setting_ofs0_reg$$Base = . ; + KEEP(*(.option_setting_ofs0)) + __option_setting_ofs0_reg$$Limit = . ; + } > OPTION_SETTING_OFS0 + .option_setting_ofs0.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS0_END = . ; + + } > OPTION_SETTING_OFS0 + + /***** OPTION_SETTING_OFS2 memory section allocations ******/ + .option_setting_ofs2.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS2_START = . ; + + } > OPTION_SETTING_OFS2 + /* Option Function Select Register 2 */ + __option_setting_ofs2_reg$$ (READONLY) : + { + __option_setting_ofs2_reg$$Base = . ; + KEEP(*(.option_setting_ofs2)) + __option_setting_ofs2_reg$$Limit = . ; + } > OPTION_SETTING_OFS2 + .option_setting_ofs2.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS2_END = . ; + + } > OPTION_SETTING_OFS2 + + /***** OPTION_SETTING_DUALSEL memory section allocations ******/ + .option_setting_dualsel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_START = . ; + + } > OPTION_SETTING_DUALSEL + /* Dual Mode Select Register */ + __option_setting_dualsel_reg$$ (READONLY) : + { + __option_setting_dualsel_reg$$Base = . ; + KEEP(*(.option_setting_dualsel)) + __option_setting_dualsel_reg$$Limit = . ; + } > OPTION_SETTING_DUALSEL + .option_setting_dualsel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_DUALSEL_END = . ; + + } > OPTION_SETTING_DUALSEL + + /***** OPTION_SETTING_OFS1 memory section allocations ******/ + .option_setting_ofs1.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_START = . ; + + } > OPTION_SETTING_OFS1 + /* Option Function Select Register 1 */ + __option_setting_ofs1_reg$$ (READONLY) : + { + __option_setting_ofs1_reg$$Base = . ; + KEEP(*(.option_setting_ofs1)) + __option_setting_ofs1_reg$$Limit = . ; + } > OPTION_SETTING_OFS1 + .option_setting_ofs1.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_END = . ; + + } > OPTION_SETTING_OFS1 + + /***** OPTION_SETTING_BANKSEL memory section allocations ******/ + .option_setting_banksel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_START = . ; + + } > OPTION_SETTING_BANKSEL + /* Bank Select Register */ + __option_setting_banksel_reg$$ (READONLY) : + { + __option_setting_banksel_reg$$Base = . ; + KEEP(*(.option_setting_banksel)) + __option_setting_banksel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL + .option_setting_banksel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_END = . ; + + } > OPTION_SETTING_BANKSEL + + /***** OPTION_SETTING_BPS memory section allocations ******/ + .option_setting_bps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_START = . ; + + } > OPTION_SETTING_BPS + /* Block Protect Setting Register */ + __option_setting_bps_reg$$ (READONLY) : + { + __option_setting_bps_reg$$Base = . ; + KEEP(*(.option_setting_bps)) + __option_setting_bps_reg$$Limit = . ; + } > OPTION_SETTING_BPS + .option_setting_bps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_END = . ; + + } > OPTION_SETTING_BPS + + /***** OPTION_SETTING_PBPS memory section allocations ******/ + .option_setting_pbps.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_START = . ; + + } > OPTION_SETTING_PBPS + /* Permanent Block Protect Setting Register */ + __option_setting_pbps_reg$$ (READONLY) : + { + __option_setting_pbps_reg$$Base = . ; + KEEP(*(.option_setting_pbps)) + __option_setting_pbps_reg$$Limit = . ; + } > OPTION_SETTING_PBPS + .option_setting_pbps.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_END = . ; + + } > OPTION_SETTING_PBPS + + /***** OPTION_SETTING_OFS1_SEC memory section allocations ******/ + .option_setting_ofs1_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_START = . ; + + } > OPTION_SETTING_OFS1_SEC + /* Option Function Select Register 1 Secure */ + __option_setting_ofs1_sec_reg$$ (READONLY) : + { + __option_setting_ofs1_sec_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sec)) + __option_setting_ofs1_sec_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEC + .option_setting_ofs1_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEC_END = . ; + + } > OPTION_SETTING_OFS1_SEC + + /***** OPTION_SETTING_BANKSEL_SEC memory section allocations ******/ + .option_setting_banksel_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_START = . ; + + } > OPTION_SETTING_BANKSEL_SEC + /* Bank Select Register Secure */ + __option_setting_banksel_sec_reg$$ (READONLY) : + { + __option_setting_banksel_sec_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sec)) + __option_setting_banksel_sec_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEC + .option_setting_banksel_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEC_END = . ; + + } > OPTION_SETTING_BANKSEL_SEC + + /***** OPTION_SETTING_BPS_SEC memory section allocations ******/ + .option_setting_bps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_START = . ; + + } > OPTION_SETTING_BPS_SEC + /* Block Protect Setting Register Secure */ + __option_setting_bps_sec_reg$$ (READONLY) : + { + __option_setting_bps_sec_reg$$Base = . ; + KEEP(*(.option_setting_bps_sec)) + __option_setting_bps_sec_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEC + .option_setting_bps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEC_END = . ; + + } > OPTION_SETTING_BPS_SEC + + /***** OPTION_SETTING_PBPS_SEC memory section allocations ******/ + .option_setting_pbps_sec.startof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_START = . ; + + } > OPTION_SETTING_PBPS_SEC + /* Permanent Block Protect Setting Register Secure */ + __option_setting_pbps_sec_reg$$ (READONLY) : + { + __option_setting_pbps_sec_reg$$Base = . ; + KEEP(*(.option_setting_pbps_sec)) + __option_setting_pbps_sec_reg$$Limit = . ; + } > OPTION_SETTING_PBPS_SEC + .option_setting_pbps_sec.endof (READONLY) : + { + __ddsc_OPTION_SETTING_PBPS_SEC_END = . ; + + } > OPTION_SETTING_PBPS_SEC + + /***** OPTION_SETTING_OFS1_SEL memory section allocations ******/ + .option_setting_ofs1_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_START = . ; + + } > OPTION_SETTING_OFS1_SEL + /* OFS1 Security Attribution */ + __option_setting_ofs1_sel_reg$$ (READONLY) : + { + __option_setting_ofs1_sel_reg$$Base = . ; + KEEP(*(.option_setting_ofs1_sel)) + __option_setting_ofs1_sel_reg$$Limit = . ; + } > OPTION_SETTING_OFS1_SEL + .option_setting_ofs1_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_OFS1_SEL_END = . ; + + } > OPTION_SETTING_OFS1_SEL + + /***** OPTION_SETTING_BANKSEL_SEL memory section allocations ******/ + .option_setting_banksel_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_START = . ; + + } > OPTION_SETTING_BANKSEL_SEL + /* Banksel Security Attribution */ + __option_setting_banksel_sel_reg$$ (READONLY) : + { + __option_setting_banksel_sel_reg$$Base = . ; + KEEP(*(.option_setting_banksel_sel)) + __option_setting_banksel_sel_reg$$Limit = . ; + } > OPTION_SETTING_BANKSEL_SEL + .option_setting_banksel_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BANKSEL_SEL_END = . ; + + } > OPTION_SETTING_BANKSEL_SEL + + /***** OPTION_SETTING_BPS_SEL memory section allocations ******/ + .option_setting_bps_sel.startof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_START = . ; + + } > OPTION_SETTING_BPS_SEL + /* BPS Security Attribution */ + __option_setting_bps_sel_reg$$ (READONLY) : + { + __option_setting_bps_sel_reg$$Base = . ; + KEEP(*(.option_setting_bps_sel)) + __option_setting_bps_sel_reg$$Limit = . ; + } > OPTION_SETTING_BPS_SEL + .option_setting_bps_sel.endof (READONLY) : + { + __ddsc_OPTION_SETTING_BPS_SEL_END = . ; + + } > OPTION_SETTING_BPS_SEL + +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_elc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_elc.h new file mode 100644 index 0000000000..ce9ffb1792 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_elc.h @@ -0,0 +1,327 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8E1 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* UNCRUSTIFY-OFF */ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list is device specific. + * */ +typedef enum e_elc_event_ra8e1 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x011), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x012), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x013), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x014), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x015), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x016), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x017), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x018), // DMAC7 transfer end + ELC_EVENT_DTC_END = (0x021), // DTC transfer end + ELC_EVENT_DTC_COMPLETE = (0x022), // DTC transfer complete + ELC_EVENT_DMA_TRANSERR = (0x027), // DMA/DTC transfer error + ELC_EVENT_DBG_CTIIRQ0 = (0x029), // Coresight Crosstrigger Event + ELC_EVENT_DBG_CTIIRQ1 = (0x02A), // Coresight Crosstrigger Event + ELC_EVENT_DBG_JBRXI = (0x02B), // JB RXI + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_VBATT_TADI = (0x03D), // VBATT Tamper Detection + ELC_EVENT_CGC_MOSC_STOP = (0x03E), // Main Clock oscillation stop + ELC_EVENT_ULPT0_INT = (0x040), // ULPT0 Underflow + ELC_EVENT_ULPT0_COMPARE_A = (0x041), // ULPT0 Compare match A + ELC_EVENT_ULPT0_COMPARE_B = (0x042), // ULPT0 Compare match B + ELC_EVENT_ULPT1_INT = (0x043), // ULPT1 Underflow + ELC_EVENT_ULPT1_COMPARE_A = (0x044), // ULPT1 Compare match A + ELC_EVENT_ULPT1_COMPARE_B = (0x045), // ULPT1 Compare match B + ELC_EVENT_AGT0_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT1_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT0_UNDERFLOW = (0x053), // WDT0 underflow + ELC_EVENT_RTC_ALARM = (0x055), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x056), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x057), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x058), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x059), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x05A), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x05B), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x05C), // Receive data full + ELC_EVENT_IIC0_TXI = (0x05D), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x05E), // Transmit end + ELC_EVENT_IIC0_ERI = (0x05F), // Transfer error + ELC_EVENT_IIC0_WUI = (0x060), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x061), // Receive data full + ELC_EVENT_IIC1_TXI = (0x062), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x063), // Transmit end + ELC_EVENT_IIC1_ERI = (0x064), // Transfer error + ELC_EVENT_SSI0_TXI = (0x073), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x074), // Receive data full + ELC_EVENT_SSI0_INT = (0x076), // Error interrupt + ELC_EVENT_SSI1_TXI = (0x079), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x079), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x07A), // Error interrupt + ELC_EVENT_ACMPHS0_INT = (0x07B), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x07C), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x083), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x084), // Software event 1 + ELC_EVENT_IOPORT_EVENT_1 = (0x088), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x089), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x08A), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x08B), // Port 4 event + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x08C), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x08D), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x08E), // Overflow interrupt + ELC_EVENT_POEG0_EVENT = (0x08F), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x090), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x091), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x092), // Port Output disable 3 interrupt + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0A1), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0A2), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0A3), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0A4), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0A5), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0A6), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0A7), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0A8), // Underflow + ELC_EVENT_GPT0_PC = (0x0A9), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0AA), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0AB), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0AC), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0AD), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0AE), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0AF), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0B0), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0B1), // Underflow + ELC_EVENT_GPT1_PC = (0x0B2), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0B3), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0B4), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0B5), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0B6), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0B7), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0B8), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0B9), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0BA), // Underflow + ELC_EVENT_GPT2_PC = (0x0BB), // Period count function finish + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0BC), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0BD), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0BE), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0BF), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0C0), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0C1), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0C2), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0C3), // Underflow + ELC_EVENT_GPT3_PC = (0x0C4), // Period count function finish + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0C5), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0C6), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0C7), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0C8), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0C9), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0CA), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0CB), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0CC), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0CE), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0CF), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0D0), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0D1), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0D2), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0D3), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0D4), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0D5), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x0FB), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x0FC), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x0FD), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x0FE), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x0FF), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x100), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x101), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x102), // Underflow + ELC_EVENT_GPT10_PC = (0x103), // Period count function finish + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x104), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x105), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x106), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x107), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x108), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x109), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x10A), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x10B), // Underflow + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x10D), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x10E), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x10F), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x110), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x111), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x112), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x113), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x114), // Underflow + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x116), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x117), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x118), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x119), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x11A), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x11B), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x11C), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x11D), // Underflow + ELC_EVENT_EDMAC0_EINT = (0x120), // EDMAC 0 interrupt + ELC_EVENT_SCI0_RXI = (0x124), // Receive data full + ELC_EVENT_SCI0_TXI = (0x125), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x126), // Transmit end + ELC_EVENT_SCI0_ERI = (0x127), // Receive error + ELC_EVENT_SCI0_AED = (0x128), // Active edge detection + ELC_EVENT_SCI0_BFD = (0x129), // Break field detection + ELC_EVENT_SCI0_AM = (0x12A), // Address match event + ELC_EVENT_SCI1_RXI = (0x12B), // Receive data full + ELC_EVENT_SCI1_TXI = (0x12C), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x12D), // Transmit end + ELC_EVENT_SCI1_ERI = (0x12E), // Receive error + ELC_EVENT_SCI1_AED = (0x12F), // Active edge detection + ELC_EVENT_SCI1_BFD = (0x130), // Break field detection + ELC_EVENT_SCI1_AM = (0x131), // Address match event + ELC_EVENT_SCI2_RXI = (0x132), // Receive data full + ELC_EVENT_SCI2_TXI = (0x133), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x134), // Transmit end + ELC_EVENT_SCI2_ERI = (0x135), // Receive error + ELC_EVENT_SCI2_AM = (0x138), // Address match event + ELC_EVENT_SCI3_RXI = (0x139), // Receive data full + ELC_EVENT_SCI3_TXI = (0x13A), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x13B), // Transmit end + ELC_EVENT_SCI3_ERI = (0x13C), // Receive error + ELC_EVENT_SCI3_AM = (0x13F), // Address match event + ELC_EVENT_SCI4_RXI = (0x140), // Receive data full + ELC_EVENT_SCI4_TXI = (0x141), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x142), // Transmit end + ELC_EVENT_SCI4_ERI = (0x143), // Receive error + ELC_EVENT_SCI4_AM = (0x146), // Address match event + ELC_EVENT_SCI9_RXI = (0x163), // Receive data full + ELC_EVENT_SCI9_TXI = (0x164), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x165), // Transmit end + ELC_EVENT_SCI9_ERI = (0x166), // Receive error + ELC_EVENT_SCI9_AM = (0x169), // Address match event + ELC_EVENT_SPI0_RXI = (0x178), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x179), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x17A), // Idle + ELC_EVENT_SPI0_ERI = (0x17B), // Error + ELC_EVENT_SPI0_TEI = (0x17C), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x17D), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x17E), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x17F), // Idle + ELC_EVENT_SPI1_ERI = (0x180), // Error + ELC_EVENT_SPI1_TEI = (0x181), // Transmission complete event + ELC_EVENT_XSPI_ERR = (0x182), // xSPI Error + ELC_EVENT_XSPI_CMP = (0x183), // xSPI Complete + ELC_EVENT_CAN_RXF = (0x185), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x186), // Global error + ELC_EVENT_CAN0_DMAREQ0 = (0x187), // RX fifo DMA request 0 + ELC_EVENT_CAN0_DMAREQ1 = (0x188), // RX fifo DMA request 1 + ELC_EVENT_CAN1_DMAREQ0 = (0x18B), // RX fifo DMA request 0 + ELC_EVENT_CAN1_DMAREQ1 = (0x18C), // RX fifo DMA request 1 + ELC_EVENT_CAN0_TX = (0x18F), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x190), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x191), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x192), // Channel DMA request + ELC_EVENT_CAN0_RXMB = (0x193), // Receive message buffer interrupt + ELC_EVENT_CAN1_TX = (0x194), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x195), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x196), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x197), // Channel DMA request + ELC_EVENT_CAN1_RXMB = (0x198), // Receive message buffer interrupt + ELC_EVENT_CAN0_MRAM_ERI = (0x19B), // CANFD0 ECC error + ELC_EVENT_CAN1_MRAM_ERI = (0x19C), // CANFD1 ECC error + ELC_EVENT_ADC0_SCAN_END = (0x1AE), // End of A/D scanning operation + ELC_EVENT_ADC0_SCAN_END_B = (0x1AF), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x1B0), // Window A Compare match interrupt + ELC_EVENT_ADC0_WINDOW_B = (0x1B1), // Window B Compare match interrupt + ELC_EVENT_ADC0_COMPARE_MATCH = (0x1B2), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x1B3), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x1B4), // End of A/D scanning operation + ELC_EVENT_ADC1_SCAN_END_B = (0x1B5), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x1B6), // Window A Compare match interrupt + ELC_EVENT_ADC1_WINDOW_B = (0x1B7), // Window B Compare match interrupt + ELC_EVENT_ADC1_COMPARE_MATCH = (0x1B8), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x1B9), // Compare mismatch + ELC_EVENT_DOC_INT = (0x1BA), // Data operation circuit interrupt + ELC_EVENT_RSIP_TADI = (0x1BC), // RSIP Tamper Detection + ELC_EVENT_CEU_CEUI = (0x1DA) // CEU interrupt +} elc_event_t; + +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) + +#define ELC_PERIPHERAL_NUM (18U) +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +/** Possible peripherals to be linked to event signals + * @note This list is device specific. + * */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_ADC1 = (10), + ELC_PERIPHERAL_ADC1_B = (11), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17) +} elc_peripheral_t; + +/** Positions of event link set registers (ELSRs) available on this MCU */ +#define BSP_ELC_PERIPHERAL_MASK (0x0003DFFFU) + +/* UNCRUSTIFY-ON */ +/** @} (end addtogroup BSP_MCU_RA8E1) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_feature.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_feature.h new file mode 100644 index 0000000000..7aa9347e64 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_feature.h @@ -0,0 +1,627 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_peripheral.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x10U) +#if (BSP_CFG_XTAL_HZ >= (24000000)) + #define CGC_MAINCLOCK_DRIVE (0x5U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (8000000)) + #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#else + #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#endif + +// *UNCRUSTIFY-OFF* + +#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1UL) // Operation stabilization wait time. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) // The IVREF selection that corresponds to the internal voltage reference. + +#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. +#define BSP_FEATURE_ADC_HAS_ADBUF (1UL) // Determine if the ADBUFn registers are present. +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1UL) // Determine if the ADPRC field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. +#define BSP_FEATURE_ADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the ADC. +#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. +#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK (0x01F7UL) // Mask of available channels in ADC unit 0. +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK (0x7FUL) // Mask of available channels in ADC unit 1. +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. + +#define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS_MASK (0x00ULL) // Feature not available on this device. +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS_MASK (0x00ULL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_D_CHANNELS_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_IS_ADC12 (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2U) // Number of channels for only AGT (not AGTW) peripherals. +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03UL) // A mask of all valid AGTx channels. + +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. +#define BSP_FEATURE_BSP_HAS_DSMIF_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_DTCM (1UL) // Indicates DTCM is available. +#define BSP_FEATURE_BSP_HAS_ESC_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. +#define BSP_FEATURE_BSP_HAS_ITCM (1UL) // Indicates ITCM is available. +#define BSP_FEATURE_BSP_HAS_OFS2 (1UL) // Indicates the OFS2 register is available. +#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. +#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. +#define BSP_FEATURE_BSP_HAS_SYRACCR (1UL) // SYRACCR register is available. +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. +#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. +#define BSP_FEATURE_BSP_NUM_PMSAR (10UL) // Number of available Port Security Attribution Registers. +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. +#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. +#define BSP_FEATURE_BSP_PART_NUMBER_OFFSET (0x00UL) // Bit offset of the Part Number in the mcu info block. +#define BSP_FEATURE_BSP_PART_NUMBER_POINTER (0x030080F0UL) // Address of the Part Numbering register (PNR). +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. +#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x03008190UL) // Address of the MCU Unique ID register (UIDR). +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. + +#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CANFD_FD_SUPPORT (1UL) // Flexible data rate support. +#define BSP_FEATURE_CANFD_HAS_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. +#define BSP_FEATURE_CANFD_LITE (1UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. +#define BSP_FEATURE_CANFD_NUM_CHANNELS (1UL) // Number of CANFD channels per CANFD peripheral instance. +#define BSP_FEATURE_CANFD_NUM_INSTANCES (2UL) // Number of hardware instances of the CANFD peripheral. + +#define BSP_FEATURE_CEC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CEC_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0UL) // Indicates the system clock can be sourced by the LOCO. +#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK (1UL) // CPU Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK1 (0UL) // CPU1 Clock is available. +#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. +#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. +#define BSP_FEATURE_CGC_HAS_FLWT (1UL) // FLWT register is available. +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. +#define BSP_FEATURE_CGC_HAS_MOCO (1UL) // Middle clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MOSC (1UL) // Main clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MRICLK (0UL) // MRAM bus clock is available. +#define BSP_FEATURE_CGC_HAS_NPUCLK (0UL) // NPU clock is available. +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. +#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. +#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. +#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. +#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. +#define BSP_FEATURE_CGC_HAS_PCLKE (1UL) // Peripheral module clock E is available. +#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. +#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. +#define BSP_FEATURE_CGC_HAS_SOPCCR (0UL) // SOPCCR register is available. +#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0UL) // SRAMPRCR2 register is available. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_1) // Reset value of the ICLK divider. +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. +#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (360000000UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ (12000000UL) // Maximum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ (6000000UL) // Minimum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ (48000000UL) // Maximum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ (8000000UL) // Minimum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (480000000UL) // Maximum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (40000000UL) // Minimum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (3UL) // Number of output clocks for PLL1. +#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (3UL) // Number of output clocks for PLL2. +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (480000000UL) // Maximum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (40000000UL) // Minimum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLLCCR_TYPE (3UL) // Indicates the type of PLLCCR register and PLL. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (1440000000UL) // PLL VCO maximum frequency. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (640000000UL) // PLL VCO minimum frequency. +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. +#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIVCR.PCLKB. +#define BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK (0UL) // Requires the SCKDIVCR2.CPUCLK1 bits to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. +#define BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK (0UL) // Requires the bits [11:8] to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SODRV_MASK (0x03UL) // Sub-clock drive field mask. +#define BSP_FEATURE_CGC_SODRV_SHIFT (0UL) // Sub-clock drive field shift. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8UL) // Bit offset for SRAMPRCR.KW field. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5U) // Write enable key code for SRAMPRCR bit. +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00UL) // Reset value for the SCKDIVCR register. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. + +#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. +#define BSP_FEATURE_CRC_HAS_SNOOP (1UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. +#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x04UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. + +#define BSP_FEATURE_CTSU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02UL) // DAADSCR register is available. +#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. +#define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. +#define BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL (1UL) // DAC output can be routed to specific extra internal modules using DAASWCR register. +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1UL) // DAAMPCR register is available. + +#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (1UL) // Number of available channels per DAC12 instance. +#define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. + +#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DMAC_HAS_DELSR (1UL) // DELSRn registers are available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). +#define BSP_FEATURE_DMAC_NUM_CHANNELS (8UL) // Number of DMAC channels available. + +#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DOC_VERSION (2UL) // The version of the DOC peripheral. + +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. + +#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. + +#define BSP_FEATURE_ELC_VERSION (2UL) // Version of the ELC peripheral. + +#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESC_NUM_PORTS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ESWM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_FRER_TABLE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GPTP_TIMER_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_GWCA_PORT (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_DOMAIN (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_MAX_QUEUE_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM (0UL) // Feature not available on this device. +#define BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. +#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // The number of AXI bus descriptors available to Ethernet components. +#define BSP_FEATURE_ETHER_NUM_CHANNELS (1UL) // Number of available ethernet PHYs. +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (1UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. + +#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (64UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. +#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (4L) // Number of non-secure application anti-rollback counters that can be configured. +#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (256UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. +#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. +#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (64UL) // Number of counter bits for the ARC_SEC counter. +#define BSP_FEATURE_FLASH_CACHE (1UL) // Flash cache is present. +#define BSP_FEATURE_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. +#define BSP_FEATURE_FLASH_CODE_CACHE_VERSION (0UL) // Version of C-Cache implemented in a CM33 core. +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x02000000UL) // Start address of the Code Flash region. +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x27000000UL) // Start address of the Data Flash region. +#define BSP_FEATURE_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). +#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (1UL) // Flash supports anti-rollback counter (ARC_* registers are available). +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (712UL) // Size of the user lockable areas (non-OFS registers). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x27030098UL) // Start address of the first non-OFS lockable word by LK_CD_A0. + +#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x02200000UL) // Start of the second code flash bank. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000UL) // Block size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000UL) // Block size of region 1. +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128UL) // Write size for code flash. +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64UL) // Block size of data flash. +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4UL) // Write size for data flash. +#define BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE (0UL) // Constraints exist for flash cache operation during flash programming access. +#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1UL) // Device contains two code banks. +#define BSP_FEATURE_FLASH_HP_VERSION (40UL) // Version of the FLASH_HP (FACI) peripheral/hardware. + +#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FUL) // Mask of 32-bit GPT channel indices. +#define BSP_FEATURE_GPT_AD_CONVERSION_START_CHANNEL_MASK (0x3FUL) // Mask of GPT channels supporting A/D conversion start. +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (1UL) // GPT A/D conversion start request is directly output to ADC instead of via the ELC. +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3C3FUL) // Mask of channels that support event count input (has GTUPSR register). +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. +#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available, GPTE implementations have a GTITC register. +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available, GPTEH implementations have a PDG module. +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3C3FUL) // Mask of channels that support dead time control. +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. +#define BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. +#define BSP_FEATURE_GPT_MSTP_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. +#define BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x00UL) // Mask of channels supporting output phase switching. +#define BSP_FEATURE_GPT_OPS_SUPPORTED (0UL) // At least one GPT channel with OPS support is available. +#define BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED (0UL) // At least one GPT channel supports polarity inversion of the GTIOCnA or GTIOCnB I/O pins. +#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. + +#define BSP_FEATURE_I3C_IS_AVAILABLE (0UL) +#define BSP_FEATURE_I3C_HAS_CLOCK (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_HAS_HDR_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0UL) // Feature not available on this device. +#define BSP_FEATURE_I3C_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. +#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. +#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. +#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. +#define BSP_FEATURE_ICU_WUPEN_MASK (0x00007708FB1DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. + +#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER (5UL) // Multiplication factor to calculate SDA bus free time. +#define BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA (0UL) // SCL status needs to be checked before writing the transmission data in master mode. +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK (0x00UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x00UL) // Mask of available IIC_B or compatible I3C channels. +#define BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK (3UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_HAS_CLOCK (0UL) // Indicates there is a separate IIC clock. +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03UL) // Mask of available IIC channels. + +#define BSP_FEATURE_IOPORT_CCD_PINS_MASK (0x00UL) // Mask of valid indices for CCD pins. +#define BSP_FEATURE_IOPORT_ELC_PORTS_MASK (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. +#define BSP_FEATURE_IOPORT_HAS_LVOCR (1UL) // The LVOCR register is available. +#define BSP_FEATURE_IOPORT_VERSION (2UL) // Version of the system PFS block. + +#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) // Frequency of the independent watchdog clock source. +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (1UL) // IWDT peripheral supports register start mode. + +#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. + +#define BSP_FEATURE_LCD_HAS_CLOCK (0UL) // Indicates there is a separate clock for the LCD. + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x0013FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. +#define BSP_FEATURE_LPM_DPSIER_MASK (0xAD1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. +#define BSP_FEATURE_LPM_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (1UL) // The device supports deep sleep mode. +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE (1UL) // The DPSBYCR.DCSSMODE field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0UL) // The DPSBYCR.DEEPCUT field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0UL) // The DPSBYCR.DPSBY field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (1UL) // The DPSBYCR.SRKEEP field is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. +#define BSP_FEATURE_LPM_HAS_LDO_SKEEP (1UL) // PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers are available. +#define BSP_FEATURE_LPM_HAS_LPSCR (1UL) // The LPSCR register is available. +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (1UL) // The PDRAMSCRn registers are available. +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0UL) // The SBYCR.OPE field is available. +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (0UL) // The SBYCR.SSBY field is available. +#define BSP_FEATURE_LPM_HAS_SNOOZE (0UL) // The MCU supports Snooze. +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0UL) // The SNZEDCR1 register is available. +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0UL) // The SNZREQCR1 register is available. +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. +#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x00UL) // Mask of valid bits for the SNZEDCRn registers. +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x00ULL) // Mask of valid bits for the SNZREQCRn registers. +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. + +#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. +#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage low threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage low threshold. +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_3_86V) // Typical higher bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_1_71V) // Typical lower bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (20UL) // Maximum stabilization time to wait after LVD1 is enabled. +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_3_86V) // Typical higher bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_1_71V) // Typical lower bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (20UL) // Maximum stabilization time to wait after LVD2 is enabled. +#define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1UL) // Voltage monitors support rising edge detections (i.e. +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. +#define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. +#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. + +#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. + +#define BSP_FEATURE_MIPI_CSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_DSI_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MIPI_PHY_IS_AVAILABLE (0UL) + +#define BSP_FEATURE_MRAM_IS_AVAILABLE (0UL) +#define BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES (0UL) // Feature not available on this device. + +#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x80000000UL) // Start address of the CS0 memory mapped region for OSPI. +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x90000000UL) // Start address of the CS1 memory mapped region for OSPI. +#define BSP_FEATURE_OSPI_HAS_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. + +#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (1UL) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000UL) // Start address of the CS0 memory mapped region for OSPI_B. +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000UL) // Start address of the CS1 memory mapped region for OSPI_B. +#define BSP_FEATURE_OSPI_B_UNIT_COUNT (1UL) // Number of OSPI_B peripheral units available. + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. +#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. +#define BSP_FEATURE_POEG_MSTP_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. + +#define BSP_FEATURE_QSPI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. +#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. +#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E11A. +#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E31A. +#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP-E50D. +#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (1UL) // The device supports cryptography using RSIP-E51A. +#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. +#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. +#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. +#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (0UL) // The device supports cryptography using SCE9. +#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_RTC_HAS_ALARM1 (0UL) // Alarm 1 is available. +#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. +#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. +#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. +#define BSP_FEATURE_RTC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. +#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. + +#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK (0x00UL) // Mask of channels with data compare match (DCCR) available. +#define BSP_FEATURE_SCI_CHANNELS_MASK (0x021FUL) // Mask of available SCI channels. +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. +#define BSP_FEATURE_SCI_HAS_CLOCK (1UL) // Indicates there is a separate SCI clock. +#define BSP_FEATURE_SCI_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. +#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. +#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. +#define BSP_FEATURE_SCI_LIN_CHANNELS_MASK (0x03UL) // Mask of channels that can support LIN. +#define BSP_FEATURE_SCI_SPI_SCKSEL_MASK (1UL) // Mask indicating CCR4.SCKSEL is available. +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK (0x00UL) // List of channels that do not support ABCSE functionality. +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK (0x021FUL) // Mask of channels which support CTS external pins. +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK (0x021FUL) // Mask of channels which support the UART FIFO. +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. +#define BSP_FEATURE_SCI_VERSION (2UL) // Version of the SCI peripheral. + +#define BSP_FEATURE_SDADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. + +#define BSP_FEATURE_SDHI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0UL) // Feature not available on this device. +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. + +#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED (1UL) // Burst transfer without delay between frames is supported. +#define BSP_FEATURE_SPI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. +#define BSP_FEATURE_SPI_HAS_CLOCK (1UL) // Indicates there is a separate clock for the SPI. +#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. +#define BSP_FEATURE_SPI_NUM_CHANNELS (2UL) // Number of available SPI channels. +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. + +#define BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR (0UL) // Flag indicating that SRAMSABAR2 and SRAMSABAR3 are present. +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. + +#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3UL) // Mask of valid SSI channel indices. + +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS (240000000UL) // Maximum frequency allowed before requiring five wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS (192000000UL) // The maximum frequency allowed without having four ROM wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS (120000000UL) // The maximum frequency that can be used before wait cycles are necessary. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS (48000000UL) // Maximum frequency allowed before requiring one wait cycle. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS (144000000UL) // Maximum frequency allowed before requiring three wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS (96000000UL) // Maximum frequency allowed before requiring two wait cycles. + +#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. + +#define BSP_FEATURE_TSN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. +#define BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available for TSN. +#define BSP_FEATURE_TSN_CALIBRATION32_MASK (0xFFFFUL) // Mask of valid bits for TSN calibration. +#define BSP_FEATURE_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. +#define BSP_FEATURE_TSN_HAS_LOW_TEMP_REG (0UL) // Determine if the TSCDRL (Low Temperature) is present. +#define BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG (0UL) // Determine if the TSCDRR (Room Temperature) is present. +#define BSP_FEATURE_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. + +#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. +#define BSP_FEATURE_TZ_HAS_TZFSAR (0UL) // Specifies the TrustZone filter can be secured. +#define BSP_FEATURE_TZ_NS_OFFSET (0x10000000UL) // Offset for the Non-secure address space of a peripheral. +#define BSP_FEATURE_TZ_VERSION (2UL) // Version of the TrustZone implementation. + +#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ULPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ULPT_NUM_CHANNELS_AVAILABLE (2UL) // Number of channels available for ULPT. +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (3UL) // Mask of available channels for ULPT. + +#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) +#define BSP_FEATURE_USB_HAS_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. +#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. +#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. +#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. +#define BSP_FEATURE_USB_HAS_USB60_CLOCK (0UL) // Indicates the USB60 clock is available. +#define BSP_FEATURE_USB_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. +#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. +#define BSP_FEATURE_USB_HAS_USBFS_BC (0UL) // Supports battery charging in full-speed mode. +#define BSP_FEATURE_USB_HAS_USBHS (0UL) // Supports USB 2.0 High-Speed mode. +#define BSP_FEATURE_USB_HAS_USBHS_BC (0UL) // Supports battery charging in high-speed mode. +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0UL) // Indicates the PHYSECTRL.CNEN field is available. +#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. +#define BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR2 register. + +#define BSP_FEATURE_VIN_IS_AVAILABLE (0UL) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_linker.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_linker.c new file mode 100644 index 0000000000..3c6f9ddeff --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_linker.c @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#if defined BSP_CFG_OPTION_SETTING_OFS0 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_cfg_option_setting_ofs0[] = {BSP_CFG_OPTION_SETTING_OFS0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS2 && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs2") g_bsp_cfg_option_setting_ofs2[] = {BSP_CFG_OPTION_SETTING_OFS2}; +#endif +#if defined BSP_CFG_OPTION_SETTING_DUALSEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_dualsel") g_bsp_cfg_option_setting_dualsel[] = {BSP_CFG_OPTION_SETTING_DUALSEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1 +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_cfg_option_setting_ofs1[] = {BSP_CFG_OPTION_SETTING_OFS1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel") g_bsp_cfg_option_setting_banksel[] = {BSP_CFG_OPTION_SETTING_BANKSEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps") g_bsp_cfg_option_setting_bps[] = {BSP_CFG_OPTION_SETTING_BPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps") g_bsp_cfg_option_setting_pbps[] = {BSP_CFG_OPTION_SETTING_PBPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_cfg_option_setting_ofs1_sec[] = {BSP_CFG_OPTION_SETTING_OFS1_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sec") g_bsp_cfg_option_setting_banksel_sec[] = {BSP_CFG_OPTION_SETTING_BANKSEL_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec") g_bsp_cfg_option_setting_bps_sec[] = {BSP_CFG_OPTION_SETTING_BPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_PBPS_SEC && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec") g_bsp_cfg_option_setting_pbps_sec[] = {BSP_CFG_OPTION_SETTING_PBPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_cfg_option_setting_ofs1_sel[] = {BSP_CFG_OPTION_SETTING_OFS1_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BANKSEL_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_cfg_option_setting_banksel_sel[] = {BSP_CFG_OPTION_SETTING_BANKSEL_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEL && !BSP_TZ_NONSECURE_BUILD +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel") g_bsp_cfg_option_setting_bps_sel[] = {BSP_CFG_OPTION_SETTING_BPS_SEL}; +#endif +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_linker_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_linker_info.h new file mode 100644 index 0000000000..4d844708d7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_linker_info.h @@ -0,0 +1,195 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/* UNCRUSTIFY-OFF */ +#ifndef BSP_LINKER_H + #define BSP_LINKER_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/******* Solution Definitions *************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +/* linker generated initialization table data structures types */ +typedef enum e_bsp_init_mem +{ + INIT_MEM_ZERO, + INIT_MEM_FLASH, + INIT_MEM_DATA_FLASH, + INIT_MEM_RAM, + INIT_MEM_DTCM, + INIT_MEM_ITCM, + INIT_MEM_CTCM, + INIT_MEM_STCM, + INIT_MEM_OSPI0_CS0, + INIT_MEM_OSPI0_CS1, + INIT_MEM_OSPI1_CS0, + INIT_MEM_OSPI1_CS1, + INIT_MEM_QSPI_FLASH, + INIT_MEM_SDRAM, + INIT_MEM_SIP_FLASH, +} bsp_init_mem_t; + +typedef struct st_bsp_init_type +{ + uint32_t copy_64 : 8; /* if 1, must use 64 bit copy operation (to keep ecc happy) */ + uint32_t external : 8; /* =1 if either source or destination is external, else 0 */ + uint32_t source_type : 8; + uint32_t destination_type : 8; +} bsp_init_type_t; + +typedef struct st_bsp_init_zero_info +{ + uint32_t * const p_base; + uint32_t * const p_limit; + bsp_init_type_t type; +} bsp_init_zero_info_t; + +typedef struct st_bsp_init_copy_info +{ + uint32_t * const p_base; + uint32_t * const p_limit; + uint32_t * const p_load; + bsp_init_type_t type; +} bsp_init_copy_info_t; +typedef struct st_bsp_init_nocache_info +{ + uint32_t * const p_base; + uint32_t * const p_limit; +} bsp_mpu_nocache_info_t; + +typedef struct st_bsp_init_info +{ + uint32_t zero_count; + bsp_init_zero_info_t const * const p_zero_list; + uint32_t copy_count; + bsp_init_copy_info_t const * const p_copy_list; + uint32_t nocache_count; + bsp_mpu_nocache_info_t const * const p_nocache_list; +} bsp_init_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern bsp_init_info_t const g_init_info; +/* These symbols are used for sau/idau configuration in a secure project */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#endif // BSP_LINKER_H +#ifdef BSP_LINKER_C +/*********************************************************************************************************************** + * Objects allocated by bsp_linker.c + **********************************************************************************************************************/ +/* DDSC symbol definitions */ +/* Zero initialization tables */ +extern uint32_t __ospi0_cs0_zero_nocache$$Base; +extern uint32_t __ospi0_cs0_zero_nocache$$Limit; +extern uint32_t __ospi0_cs0_zero$$Base; +extern uint32_t __ospi0_cs0_zero$$Limit; +extern uint32_t __itcm_zero$$Base; +extern uint32_t __itcm_zero$$Limit; +extern uint32_t __dtcm_zero$$Base; +extern uint32_t __dtcm_zero$$Limit; +extern uint32_t __ram_zero_nocache$$Base; +extern uint32_t __ram_zero_nocache$$Limit; +extern uint32_t __ram_zero$$Base; +extern uint32_t __ram_zero$$Limit; +static const bsp_init_zero_info_t zero_list[] = +{ + {.p_base = &__ospi0_cs0_zero_nocache$$Base, .p_limit = &__ospi0_cs0_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi0_cs0_zero$$Base, .p_limit = &__ospi0_cs0_zero$$Limit,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__itcm_zero$$Base, .p_limit = &__itcm_zero$$Limit,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_ITCM}}, + {.p_base = &__dtcm_zero$$Base, .p_limit = &__dtcm_zero$$Limit,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_DTCM}}, + {.p_base = &__ram_zero_nocache$$Base, .p_limit = &__ram_zero_nocache$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_zero$$Base, .p_limit = &__ram_zero$$Limit,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_ZERO, .destination_type = INIT_MEM_RAM}} +}; +/* Load initialization tables */ +extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Base; +extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Limit; +extern uint32_t __ospi0_cs0_from_ospi0_cs1$$Load; +extern uint32_t __ospi0_cs0_from_data_flash$$Base; +extern uint32_t __ospi0_cs0_from_data_flash$$Limit; +extern uint32_t __ospi0_cs0_from_data_flash$$Load; +extern uint32_t __ospi0_cs0_from_flash$$Base; +extern uint32_t __ospi0_cs0_from_flash$$Limit; +extern uint32_t __ospi0_cs0_from_flash$$Load; +extern uint32_t __itcm_from_ospi0_cs1$$Base; +extern uint32_t __itcm_from_ospi0_cs1$$Limit; +extern uint32_t __itcm_from_ospi0_cs1$$Load; +extern uint32_t __itcm_from_data_flash$$Base; +extern uint32_t __itcm_from_data_flash$$Limit; +extern uint32_t __itcm_from_data_flash$$Load; +extern uint32_t __itcm_from_flash$$Base; +extern uint32_t __itcm_from_flash$$Limit; +extern uint32_t __itcm_from_flash$$Load; +extern uint32_t __dtcm_from_ospi0_cs1$$Base; +extern uint32_t __dtcm_from_ospi0_cs1$$Limit; +extern uint32_t __dtcm_from_ospi0_cs1$$Load; +extern uint32_t __dtcm_from_data_flash$$Base; +extern uint32_t __dtcm_from_data_flash$$Limit; +extern uint32_t __dtcm_from_data_flash$$Load; +extern uint32_t __dtcm_from_flash$$Base; +extern uint32_t __dtcm_from_flash$$Limit; +extern uint32_t __dtcm_from_flash$$Load; +extern uint32_t __ram_from_ospi0_cs1$$Base; +extern uint32_t __ram_from_ospi0_cs1$$Limit; +extern uint32_t __ram_from_ospi0_cs1$$Load; +extern uint32_t __ram_from_data_flash$$Base; +extern uint32_t __ram_from_data_flash$$Limit; +extern uint32_t __ram_from_data_flash$$Load; +extern uint32_t __ram_from_flash$$Base; +extern uint32_t __ram_from_flash$$Limit; +extern uint32_t __ram_from_flash$$Load; +static const bsp_init_copy_info_t copy_list[] = +{ + {.p_base = &__ospi0_cs0_from_ospi0_cs1$$Base, .p_limit = &__ospi0_cs0_from_ospi0_cs1$$Limit, .p_load = &__ospi0_cs0_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi0_cs0_from_data_flash$$Base, .p_limit = &__ospi0_cs0_from_data_flash$$Limit, .p_load = &__ospi0_cs0_from_data_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__ospi0_cs0_from_flash$$Base, .p_limit = &__ospi0_cs0_from_flash$$Limit, .p_load = &__ospi0_cs0_from_flash$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_OSPI0_CS0}}, + {.p_base = &__itcm_from_ospi0_cs1$$Base, .p_limit = &__itcm_from_ospi0_cs1$$Limit, .p_load = &__itcm_from_ospi0_cs1$$Load,.type={.copy_64 = 1, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_ITCM}}, + {.p_base = &__itcm_from_data_flash$$Base, .p_limit = &__itcm_from_data_flash$$Limit, .p_load = &__itcm_from_data_flash$$Load,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_ITCM}}, + {.p_base = &__itcm_from_flash$$Base, .p_limit = &__itcm_from_flash$$Limit, .p_load = &__itcm_from_flash$$Load,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_ITCM}}, + {.p_base = &__dtcm_from_ospi0_cs1$$Base, .p_limit = &__dtcm_from_ospi0_cs1$$Limit, .p_load = &__dtcm_from_ospi0_cs1$$Load,.type={.copy_64 = 1, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_DTCM}}, + {.p_base = &__dtcm_from_data_flash$$Base, .p_limit = &__dtcm_from_data_flash$$Limit, .p_load = &__dtcm_from_data_flash$$Load,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_DTCM}}, + {.p_base = &__dtcm_from_flash$$Base, .p_limit = &__dtcm_from_flash$$Limit, .p_load = &__dtcm_from_flash$$Load,.type={.copy_64 = 1, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_DTCM}}, + {.p_base = &__ram_from_ospi0_cs1$$Base, .p_limit = &__ram_from_ospi0_cs1$$Limit, .p_load = &__ram_from_ospi0_cs1$$Load,.type={.copy_64 = 0, .external = 1, .source_type = INIT_MEM_OSPI0_CS1, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_from_data_flash$$Base, .p_limit = &__ram_from_data_flash$$Limit, .p_load = &__ram_from_data_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_DATA_FLASH, .destination_type = INIT_MEM_RAM}}, + {.p_base = &__ram_from_flash$$Base, .p_limit = &__ram_from_flash$$Limit, .p_load = &__ram_from_flash$$Load,.type={.copy_64 = 0, .external = 0, .source_type = INIT_MEM_FLASH, .destination_type = INIT_MEM_RAM}} +}; +/* nocache regions */ +extern uint32_t __ospi0_cs0_noinit_nocache$$Base; +extern uint32_t __ospi0_cs0_noinit_nocache$$Limit; +extern uint32_t __ospi0_cs0_zero_nocache$$Base; +extern uint32_t __ospi0_cs0_zero_nocache$$Limit; +extern uint32_t __ram_noinit_nocache$$Base; +extern uint32_t __ram_noinit_nocache$$Limit; +extern uint32_t __ram_zero_nocache$$Base; +extern uint32_t __ram_zero_nocache$$Limit; +static const bsp_mpu_nocache_info_t nocache_list[] = +{ + {.p_base = &__ospi0_cs0_noinit_nocache$$Base, .p_limit = &__ospi0_cs0_zero_nocache$$Limit}, + {.p_base = &__ram_noinit_nocache$$Base, .p_limit = &__ram_zero_nocache$$Limit}, +}; + +/* initialization data structure */ +const bsp_init_info_t g_init_info = +{ + .zero_count = sizeof(zero_list) / sizeof(zero_list[0]), + .p_zero_list = zero_list, + .copy_count = sizeof(copy_list) / sizeof(copy_list[0]), + .p_copy_list = copy_list, + .nocache_count = sizeof(nocache_list) / sizeof(nocache_list[0]), + .p_nocache_list = nocache_list +}; + +#endif // BSP_LINKER_C + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_mcu_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_mcu_info.h new file mode 100644 index 0000000000..7ff5032818 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_mcu_info.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA8E1 RA8E1 + * @includedoc config_bsp_ra8e1_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA8E1) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_override.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_override.h new file mode 100644 index 0000000000..7cc03db5ff --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_override.h @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8E1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8E1) */ + +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#if __has_include("r_ospi_b_device_types.h") + #include "r_ospi_b_device_types.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MCU. */ + +#define BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T +#define BSP_OVERRIDE_GROUP_IRQ_T +#define BSP_OVERRIDE_LVD_PERIPHERAL_T + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, + * PCLKS A-D. */ +typedef enum e_cgc_sys_clock_div +{ + CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1 + CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2 + CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4 + CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8 + CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 + CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 + CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 + CGC_SYS_CLOCK_DIV_3 = 8, ///< System clock divided by 3 + CGC_SYS_CLOCK_DIV_6 = 9, ///< System clock divided by 6 + CGC_SYS_CLOCK_DIV_12 = 10, ///< System clock divided by 12 +} cgc_sys_clock_div_t; + +/* Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_MPU_BUS_TZF = 12, ///< MPU Bus or TrustZone Filter Error + BSP_GRP_IRQ_COMMON_MEMORY = 13, ///< SRAM ECC or SRAM Parity Error + BSP_GRP_IRQ_LOCKUP = 15, ///< LockUp Error +} bsp_grp_irq_t; + +/** The thresholds supported by each MCU are in the MCU User's Manual as well as + * in the r_lvd module description on the stack tab of the RA project. */ +typedef enum +{ + LVD_THRESHOLD_MONITOR_LEVEL_3_86V = 0x03UL, ///< 3.86V + LVD_THRESHOLD_MONITOR_LEVEL_3_14V = 0x04UL, ///< 3.14V + LVD_THRESHOLD_MONITOR_LEVEL_3_10V = 0x05UL, ///< 3.10V + LVD_THRESHOLD_MONITOR_LEVEL_3_08V = 0x06UL, ///< 3.08V + LVD_THRESHOLD_MONITOR_LEVEL_2_85V = 0x07UL, ///< 2.85V + LVD_THRESHOLD_MONITOR_LEVEL_2_83V = 0x08UL, ///< 2.83V + LVD_THRESHOLD_MONITOR_LEVEL_2_80V = 0x09UL, ///< 2.80V + LVD_THRESHOLD_MONITOR_LEVEL_2_62V = 0x0AUL, ///< 2.62V + LVD_THRESHOLD_MONITOR_LEVEL_2_33V = 0x0BUL, ///< 2.33V + LVD_THRESHOLD_MONITOR_LEVEL_1_90V = 0x0CUL, ///< 1.90V + LVD_THRESHOLD_MONITOR_LEVEL_1_86V = 0x0DUL, ///< 1.86V + LVD_THRESHOLD_MONITOR_LEVEL_1_74V = 0x0EUL, ///< 1.74V + LVD_THRESHOLD_MONITOR_LEVEL_1_71V = 0x0FUL, ///< 1.71V + LVD_THRESHOLD_NOT_AVAILABLE = 0xFFUL, ///< Not Used +} lvd_threshold_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_peripheral.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_peripheral.h new file mode 100644 index 0000000000..f36e9bc3c3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/bsp_peripheral.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_PERIPHERAL_H +#define BSP_PERIPHERAL_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// *UNCRUSTIFY-OFF* + +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_PRESENT (1) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ADC_B_PRESENT (0) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_PRESENT (1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC_PRESENT (1) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DAC_B_PRESENT (0) +#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC12_PRESENT (1) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DRW_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ESWM_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_FACI_PRESENT (1) +#define BSP_PERIPHERAL_FCACHE_PRESENT (1) +#define BSP_PERIPHERAL_FLAD_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (1) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3C3FU) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (0) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (0) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_I3C_PRESENT (0) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFU) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_IIC_B_PRESENT (0) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IPC_PRESENT (0) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_CSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_PHY_PRESENT (0) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MRMS_PRESENT (0) +#define BSP_PERIPHERAL_MRRGE_PRESENT (0) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_NPU_PRESENT (0) +#define BSP_PERIPHERAL_OCD_PRESENT (1) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDM_PRESENT (0) +#define BSP_PERIPHERAL_PDM_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x3FFU) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RSIP_PRESENT (1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_B_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x21FU) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDHI_PRESENT (0) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SPI_B_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ULPT_PRESENT (1) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (0) +#define BSP_PERIPHERAL_USBCC_PRESENT (0) +#define BSP_PERIPHERAL_VIN_PRESENT (0) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x1U) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/r_ospi_b_device_types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/r_ospi_b_device_types.h new file mode 100644 index 0000000000..4f5e8d8afc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8e1/r_ospi_b_device_types.h @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8E1 + * @{ + **********************************************************************************************************************/ + +#ifndef R_OSPI_B_DEVICE_TYPES_H +#define R_OSPI_B_DEVICE_TYPES_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_OVERRIDE_BSP_CLOCKS_OCTACLK_DIV_T + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** OCTACLK divider values. */ +typedef enum e_bsp_clocks_octaclk_div +{ + BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 + BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 + BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 + BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 + BSP_CLOCKS_OCTACLK_DIV_8, ///< Divide OCTA source clock by 8 + BSP_CLOCKS_OCTACLK_DIV_3, ///< Divide OCTA source clock by 3 + BSP_CLOCKS_OCTACLK_DIV_5, ///< Divide OCTA source clock by 5 +} bsp_clocks_octaclk_div_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BSP_MCU_RA8E1) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h new file mode 100644 index 0000000000..f641ae90e7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h @@ -0,0 +1,583 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8P1 + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* UNCRUSTIFY-OFF */ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list is device specific. + * */ +typedef enum e_elc_event_ra8p1 +{ + ELC_EVENT_NONE = (0x0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_ICU_IRQ16 = (0x011), // External pin interrupt 16 + ELC_EVENT_ICU_IRQ17 = (0x012), // External pin interrupt 17 + ELC_EVENT_ICU_IRQ18 = (0x013), // External pin interrupt 18 + ELC_EVENT_ICU_IRQ19 = (0x014), // External pin interrupt 19 + ELC_EVENT_ICU_IRQ20 = (0x015), // External pin interrupt 20 + ELC_EVENT_ICU_IRQ21 = (0x016), // External pin interrupt 21 + ELC_EVENT_ICU_IRQ22 = (0x017), // External pin interrupt 22 + ELC_EVENT_ICU_IRQ23 = (0x018), // External pin interrupt 23 + ELC_EVENT_ICU_IRQ24 = (0x019), // External pin interrupt 24 + ELC_EVENT_ICU_IRQ25 = (0x01A), // External pin interrupt 25 + ELC_EVENT_ICU_IRQ26 = (0x01B), // External pin interrupt 26 + ELC_EVENT_ICU_IRQ27 = (0x01C), // External pin interrupt 27 + ELC_EVENT_ICU_IRQ28 = (0x01D), // External pin interrupt 28 + ELC_EVENT_ICU_IRQ29 = (0x01E), // External pin interrupt 29 + ELC_EVENT_ICU_IRQ30 = (0x01F), // External pin interrupt 30 + ELC_EVENT_ICU_IRQ31 = (0x020), // External pin interrupt 31 + ELC_EVENT_DMAC0_INT = (0x040), // DMAC0 transfer end + ELC_EVENT_DMAC1_INT = (0x041), // DMAC1 transfer end + ELC_EVENT_DMAC2_INT = (0x042), // DMAC2 transfer end + ELC_EVENT_DMAC3_INT = (0x043), // DMAC3 transfer end + ELC_EVENT_DMAC4_INT = (0x044), // DMAC4 transfer end + ELC_EVENT_DMAC5_INT = (0x045), // DMAC5 transfer end + ELC_EVENT_DMAC6_INT = (0x046), // DMAC6 transfer end + ELC_EVENT_DMAC7_INT = (0x047), // DMAC7 transfer end + ELC_EVENT_DMAC10_INT = (0x048), // DMAC10 transfer end + ELC_EVENT_DMAC11_INT = (0x049), // DMAC11 transfer end + ELC_EVENT_DMAC12_INT = (0x04A), // DMAC12 transfer end + ELC_EVENT_DMAC13_INT = (0x04B), // DMAC13 transfer end + ELC_EVENT_DMAC14_INT = (0x04C), // DMAC14 transfer end + ELC_EVENT_DMAC15_INT = (0x04D), // DMAC15 transfer end + ELC_EVENT_DMAC16_INT = (0x04E), // DMAC16 transfer end + ELC_EVENT_DMAC17_INT = (0x04F), // DMAC17 transfer end + ELC_EVENT_DTC_END = (0x052), // DTC transfer end + ELC_EVENT_DTC1_END = (0x055), // DTC1 transfer end + ELC_EVENT_DMA_TRANSERR = (0x056), // DMA/DTC transfer error + ELC_EVENT_DMA1_TRANSERR = (0x057), // DMA1/DTC1 transfer error + ELC_EVENT_DBG_CTIIRQ0 = (0x058), // Coresight Crosstrigger Event + ELC_EVENT_DBG_CTIIRQ1 = (0x059), // Coresight Crosstrigger Event + ELC_EVENT_DBG_JBRXI = (0x05A), // JB RXI + ELC_EVENT_IPC_IRQ0 = (0x05B), // CPU Mutual Interrupt 0 + ELC_EVENT_IPC_IRQ1 = (0x05C), // CPU Mutual Interrupt 1 + ELC_EVENT_LM0_ERR = (0x05F), // Local memory 0 error + ELC_EVENT_LM1_ERR = (0x060), // Local memory 1 error + ELC_EVENT_CPU0_LOCKUP = (0x061), // CPU 0 lockup + ELC_EVENT_CPU1_LOCKUP = (0x062), // CPU 1 lockup + ELC_EVENT_BUS_ERR = (0x063), // BUS error + ELC_EVENT_CM_ERR = (0x064), // Common memory error + ELC_EVENT_FPU_EXC = (0x065), // FPU exception + ELC_EVENT_NPU_IRQ = (0x067), // NPU IRQ + ELC_EVENT_MRAM_MRCRD = (0x068), // MRAM read error interrupt for MRC + ELC_EVENT_MRAM_MRERD = (0x069), // MRAM read error interrupt for MRE + ELC_EVENT_MRAM_MRCPR = (0x06B), // MRAM sequencer error interrupt for MRC + ELC_EVENT_MRAM_MREPR = (0x06C), // MRAM sequencer error interrupt for MRE + ELC_EVENT_MRAM_ENDOFPE = (0x06D), // MRAM sequencer ready + ELC_EVENT_LVD_LVD1 = (0x070), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x071), // Voltage monitor 2 interrupt + ELC_EVENT_VBATT_TADI = (0x075), // VBATT Tamper Detection + ELC_EVENT_CGC_MOSC_STOP = (0x076), // Main Clock oscillation stop + ELC_EVENT_CGC_SOSC_STOP = (0x077), // Sub oscillation stop + ELC_EVENT_ULPT0_INT = (0x080), // ULPT0 Underflow + ELC_EVENT_ULPT0_COMPARE_A = (0x081), // ULPT0 Compare match A + ELC_EVENT_ULPT0_COMPARE_B = (0x082), // ULPT0 Compare match B + ELC_EVENT_ULPT1_INT = (0x083), // ULPT1 Underflow + ELC_EVENT_ULPT1_COMPARE_A = (0x084), // ULPT1 Compare match A + ELC_EVENT_ULPT1_COMPARE_B = (0x085), // ULPT1 Compare match B + ELC_EVENT_AGT0_INT = (0x086), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x087), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x088), // Compare match B + ELC_EVENT_AGT1_INT = (0x089), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x08A), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x08B), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x092), // IWDT underflow + ELC_EVENT_WDT0_UNDERFLOW = (0x093), // WDT0 underflow + ELC_EVENT_WDT1_UNDERFLOW = (0x094), // WDT1 underflow + ELC_EVENT_RTC_ALARM = (0x095), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x096), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x097), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x098), // DMA/DTC transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x099), // DMA/DTC transfer request 1 + ELC_EVENT_USBFS_INT = (0x09A), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x09B), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x09C), // Receive data full + ELC_EVENT_IIC0_TXI = (0x09D), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x09E), // Transmit end + ELC_EVENT_IIC0_ERI = (0x09F), // Transfer error + ELC_EVENT_IIC0_WUI = (0x0A0), // Wakeup interrupt + ELC_EVENT_IIC1_RXI = (0x0A1), // Receive data full + ELC_EVENT_IIC1_TXI = (0x0A2), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x0A3), // Transmit end + ELC_EVENT_IIC1_ERI = (0x0A4), // Transfer error + ELC_EVENT_IIC2_RXI = (0x0A6), // Receive data full + ELC_EVENT_IIC2_TXI = (0x0A7), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x0A8), // Transmit end + ELC_EVENT_IIC2_ERI = (0x0A9), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x0AB), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x0AC), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x0AD), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x0AE), // DMA transfer request + ELC_EVENT_SDHIMMC1_ACCS = (0x0AF), // Card access + ELC_EVENT_SDHIMMC1_SDIO = (0x0B0), // SDIO access + ELC_EVENT_SDHIMMC1_CARD = (0x0B1), // Card detect + ELC_EVENT_SDHIMMC1_DMA_REQ = (0x0B2), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x0B3), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x0B4), // Receive data full + ELC_EVENT_SSI0_INT = (0x0B6), // Error interrupt + ELC_EVENT_SSI1_TXI = (0x0B9), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_RXI = (0x0B9), // Receive data full/Transmit data empty + ELC_EVENT_SSI1_INT = (0x0BA), // Error interrupt + ELC_EVENT_XSPI_ERR = (0x0BB), // xSPI Error + ELC_EVENT_XSPI_CMP = (0x0BC), // xSPI Complete + ELC_EVENT_XSPI1_ERR = (0x0BD), // xSPI1 Error + ELC_EVENT_XSPI1_CMP = (0x0BE), // xSPI1 Complete + ELC_EVENT_PDM_DAT0 = (0x0BF), // Data reception interrupt channel 0 + ELC_EVENT_PDM_DAT1 = (0x0C0), // Data reception interrupt channel 1 + ELC_EVENT_PDM_DAT2 = (0x0C1), // Data reception interrupt channel 2 + ELC_EVENT_PDM_SDET = (0x0C2), // Sound detection interrupt + ELC_EVENT_PDM_ERR0 = (0x0C3), // Error detection interrupt channel 0 + ELC_EVENT_PDM_ERR1 = (0x0C4), // Error detection interrupt channel 1 + ELC_EVENT_PDM_ERR2 = (0x0C5), // Error detection interrupt channel 2 + ELC_EVENT_ACMPHS0_INT = (0x0C6), // High Speed Comparator channel 0 interrupt + ELC_EVENT_ACMPHS1_INT = (0x0C7), // High Speed Comparator channel 1 interrupt + ELC_EVENT_ACMPHS2_INT = (0x0C8), // High Speed Comparator channel 2 interrupt + ELC_EVENT_ACMPHS3_INT = (0x0C9), // High Speed Comparator channel 3 interrupt + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0CC), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0CD), // Software event 1 + ELC_EVENT_ELC_SOFTWARE_EVENT_2 = (0x0CE), // Software event 2 + ELC_EVENT_ELC_SOFTWARE_EVENT_3 = (0x0CF), // Software event 3 + ELC_EVENT_IOPORT_EVENT_1 = (0x0D0), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0D1), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0D2), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0D3), // Port 4 event + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x0D4), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x0D5), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0D6), // Overflow interrupt + ELC_EVENT_POEG0_EVENT = (0x0D7), // Port Output disable 0 interrupt + ELC_EVENT_POEG1_EVENT = (0x0D8), // Port Output disable 1 interrupt + ELC_EVENT_POEG2_EVENT = (0x0D9), // Port Output disable 2 interrupt + ELC_EVENT_POEG3_EVENT = (0x0DA), // Port Output disable 3 interrupt + ELC_EVENT_OPS_UVW_EDGE = (0x180), // UVW edge event + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x181), // Capture/Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x182), // Capture/Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x183), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x184), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x185), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x186), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x187), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x188), // Underflow + ELC_EVENT_GPT0_PC = (0x189), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x18A), // Capture/Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x18B), // Capture/Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x18C), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x18D), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x18E), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x18F), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x190), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x191), // Underflow + ELC_EVENT_GPT1_PC = (0x192), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x193), // Capture/Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x194), // Capture/Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x195), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x196), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x197), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x198), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x199), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x19A), // Underflow + ELC_EVENT_GPT2_PC = (0x19B), // Period count function finish + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x19C), // Capture/Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x19D), // Capture/Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x19E), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x19F), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x1A0), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x1A1), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x1A2), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x1A3), // Underflow + ELC_EVENT_GPT3_PC = (0x1A4), // Period count function finish + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x1A5), // Capture/Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x1A6), // Capture/Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x1A7), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x1A8), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x1A9), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x1AA), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x1AB), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x1AC), // Underflow + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x1AE), // Capture/Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x1AF), // Capture/Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x1B0), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x1B1), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x1B2), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x1B3), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x1B4), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x1B5), // Underflow + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x1B7), // Capture/Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x1B8), // Capture/Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x1B9), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x1BA), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x1BB), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x1BC), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x1BD), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x1BE), // Underflow + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x1C0), // Capture/Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x1C1), // Capture/Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x1C2), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x1C3), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x1C4), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x1C5), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x1C6), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x1C7), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x1C9), // Capture/Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x1CA), // Capture/Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x1CB), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x1CC), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x1CD), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x1CE), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x1CF), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x1D0), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x1D2), // Capture/Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x1D3), // Capture/Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x1D4), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x1D5), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x1D6), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x1D7), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x1D8), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x1D9), // Underflow + ELC_EVENT_GPT10_CAPTURE_COMPARE_A = (0x1DB), // Capture/Compare match A + ELC_EVENT_GPT10_CAPTURE_COMPARE_B = (0x1DC), // Capture/Compare match B + ELC_EVENT_GPT10_COMPARE_C = (0x1DD), // Compare match C + ELC_EVENT_GPT10_COMPARE_D = (0x1DE), // Compare match D + ELC_EVENT_GPT10_COMPARE_E = (0x1DF), // Compare match E + ELC_EVENT_GPT10_COMPARE_F = (0x1E0), // Compare match F + ELC_EVENT_GPT10_COUNTER_OVERFLOW = (0x1E1), // Overflow + ELC_EVENT_GPT10_COUNTER_UNDERFLOW = (0x1E2), // Underflow + ELC_EVENT_GPT10_PC = (0x1E3), // Period count function finish + ELC_EVENT_GPT11_CAPTURE_COMPARE_A = (0x1E4), // Capture/Compare match A + ELC_EVENT_GPT11_CAPTURE_COMPARE_B = (0x1E5), // Capture/Compare match B + ELC_EVENT_GPT11_COMPARE_C = (0x1E6), // Compare match C + ELC_EVENT_GPT11_COMPARE_D = (0x1E7), // Compare match D + ELC_EVENT_GPT11_COMPARE_E = (0x1E8), // Compare match E + ELC_EVENT_GPT11_COMPARE_F = (0x1E9), // Compare match F + ELC_EVENT_GPT11_COUNTER_OVERFLOW = (0x1EA), // Overflow + ELC_EVENT_GPT11_COUNTER_UNDERFLOW = (0x1EB), // Underflow + ELC_EVENT_GPT11_PC = (0x1EC), // Period count function finish + ELC_EVENT_GPT12_CAPTURE_COMPARE_A = (0x1ED), // Capture/Compare match A + ELC_EVENT_GPT12_CAPTURE_COMPARE_B = (0x1EE), // Capture/Compare match B + ELC_EVENT_GPT12_COMPARE_C = (0x1EF), // Compare match C + ELC_EVENT_GPT12_COMPARE_D = (0x1F0), // Compare match D + ELC_EVENT_GPT12_COMPARE_E = (0x1F1), // Compare match E + ELC_EVENT_GPT12_COMPARE_F = (0x1F2), // Compare match F + ELC_EVENT_GPT12_COUNTER_OVERFLOW = (0x1F3), // Overflow + ELC_EVENT_GPT12_COUNTER_UNDERFLOW = (0x1F4), // Underflow + ELC_EVENT_GPT12_PC = (0x1F5), // Period count function finish + ELC_EVENT_GPT13_CAPTURE_COMPARE_A = (0x1F6), // Capture/Compare match A + ELC_EVENT_GPT13_CAPTURE_COMPARE_B = (0x1F7), // Capture/Compare match B + ELC_EVENT_GPT13_COMPARE_C = (0x1F8), // Compare match C + ELC_EVENT_GPT13_COMPARE_D = (0x1F9), // Compare match D + ELC_EVENT_GPT13_COMPARE_E = (0x1FA), // Compare match E + ELC_EVENT_GPT13_COMPARE_F = (0x1FB), // Compare match F + ELC_EVENT_GPT13_COUNTER_OVERFLOW = (0x1FC), // Overflow + ELC_EVENT_GPT13_COUNTER_UNDERFLOW = (0x1FD), // Underflow + ELC_EVENT_GPT13_PC = (0x1FE), // Period count function finish + ELC_EVENT_ETHER_FWEI = (0x29A), // Forwarding Error Interrupt + ELC_EVENT_ETHER_CAEI = (0x29B), // Common Error Interrupt + ELC_EVENT_ETHER_GWEI = (0x29C), // GWCA0 Error Interrupt + ELC_EVENT_ETHER_EAEI0 = (0x29D), // ETHA0 Error Interrupt + ELC_EVENT_ETHER_EAEI1 = (0x29E), // ETHA1 Error Interrupt + ELC_EVENT_ETHER_PTPSI0 = (0x29F), // gPTP Status Interrupt 0 + ELC_EVENT_ETHER_PTPSI1 = (0x2A0), // gPTP Status Interrupt 1 + ELC_EVENT_ETHER_FWSI = (0x2A1), // Forwarding Status Interrupt + ELC_EVENT_ETHER_SWSI = (0x2A2), // Switch Status Interrupt + ELC_EVENT_ETHER_CAMI = (0x2A3), // Common Status Interrupt + ELC_EVENT_ETHER_EASI0 = (0x2A4), // ETHA0 Status Interrupt + ELC_EVENT_ETHER_EASI1 = (0x2A5), // ETHA1 Status Interrupt + ELC_EVENT_ETHER_GWDI0 = (0x2A6), // GWCA Data Interrupt 0 + ELC_EVENT_ETHER_GWDI1 = (0x2A7), // GWCA Data Interrupt 1 + ELC_EVENT_ETHER_GWDI2 = (0x2A8), // GWCA Data Interrupt 2 + ELC_EVENT_ETHER_GWDI3 = (0x2A9), // GWCA Data Interrupt 3 + ELC_EVENT_ETHER_GWDI4 = (0x2AA), // GWCA Data Interrupt 4 + ELC_EVENT_ETHER_GWDI5 = (0x2AB), // GWCA Data Interrupt 5 + ELC_EVENT_ETHER_GWDI6 = (0x2AC), // GWCA Data Interrupt 6 + ELC_EVENT_ETHER_GWDI7 = (0x2AD), // GWCA Data Interrupt 7 + ELC_EVENT_ETHER_TSDI0 = (0x2AE), // Time Stamp Data Interrupt 0 + ELC_EVENT_ETHER_TSDI1 = (0x2AF), // Time Stamp Data Interrupt 1 + ELC_EVENT_ETHER_MDIO0 = (0x2B0), // MDIO Interrupt 0 + ELC_EVENT_ETHER_MDIO1 = (0x2B1), // MDIO Interrupt 1 + ELC_EVENT_ETHER_RMPI0 = (0x2B2), // RMAC0 PHY Interrupt + ELC_EVENT_ETHER_RMPI1 = (0x2B3), // RMAC1 PHY Interrupt + ELC_EVENT_GPTP_PTPOUT0 = (0x2B4), // PTP Pulse Out 0 + ELC_EVENT_GPTP_PTPOUT1 = (0x2B5), // PTP Pulse Out 1 + ELC_EVENT_GPTP_PTPOUT2 = (0x2B6), // PTP Pulse Out 2 + ELC_EVENT_GPTP_PTPOUT3 = (0x2B7), // PTP Pulse Out 3 + ELC_EVENT_GPTP0_MATCH = (0x2B8), // Media Clock Recovery Match + ELC_EVENT_GPTP1_MATCH = (0x2B9), // Media Clock Recovery Match + ELC_EVENT_USBHS_FIFO_0 = (0x2C1), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x2C2), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x2C3), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x2C4), // Receive data full + ELC_EVENT_SCI0_TXI = (0x2C5), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x2C6), // Transmit end + ELC_EVENT_SCI0_ERI = (0x2C7), // Receive error + ELC_EVENT_SCI0_AED = (0x2C8), // Active edge detection + ELC_EVENT_SCI0_BFD = (0x2C9), // Break field detection + ELC_EVENT_SCI0_AM = (0x2CA), // Address match event + ELC_EVENT_SCI1_RXI = (0x2CB), // Receive data full + ELC_EVENT_SCI1_TXI = (0x2CC), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x2CD), // Transmit end + ELC_EVENT_SCI1_ERI = (0x2CE), // Receive error + ELC_EVENT_SCI1_AED = (0x2CF), // Active edge detection + ELC_EVENT_SCI1_BFD = (0x2D0), // Break field detection + ELC_EVENT_SCI1_AM = (0x2D1), // Address match event + ELC_EVENT_SCI2_RXI = (0x2D2), // Receive data full + ELC_EVENT_SCI2_TXI = (0x2D3), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x2D4), // Transmit end + ELC_EVENT_SCI2_ERI = (0x2D5), // Receive error + ELC_EVENT_SCI2_AED = (0x2D6), // Active edge detection + ELC_EVENT_SCI2_BFD = (0x2D7), // Break field detection + ELC_EVENT_SCI2_AM = (0x2D8), // Address match event + ELC_EVENT_SCI3_RXI = (0x2D9), // Receive data full + ELC_EVENT_SCI3_TXI = (0x2DA), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x2DB), // Transmit end + ELC_EVENT_SCI3_ERI = (0x2DC), // Receive error + ELC_EVENT_SCI3_AED = (0x2DD), // Active edge detection + ELC_EVENT_SCI3_BFD = (0x2DE), // Break field detection + ELC_EVENT_SCI3_AM = (0x2DF), // Address match event + ELC_EVENT_SCI4_RXI = (0x2E0), // Receive data full + ELC_EVENT_SCI4_TXI = (0x2E1), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x2E2), // Transmit end + ELC_EVENT_SCI4_ERI = (0x2E3), // Receive error + ELC_EVENT_SCI4_AED = (0x2E4), // Active edge detection + ELC_EVENT_SCI4_BFD = (0x2E5), // Break field detection + ELC_EVENT_SCI4_AM = (0x2E6), // Address match event + ELC_EVENT_SCI5_RXI = (0x2E7), // Receive data full + ELC_EVENT_SCI5_TXI = (0x2E8), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x2E9), // Transmit end + ELC_EVENT_SCI5_ERI = (0x2EA), // Receive error + ELC_EVENT_SCI5_AED = (0x2EB), // Active edge detection + ELC_EVENT_SCI5_BFD = (0x2EC), // Break field detection + ELC_EVENT_SCI5_AM = (0x2ED), // Address match event + ELC_EVENT_SCI6_RXI = (0x2EE), // Receive data full + ELC_EVENT_SCI6_TXI = (0x2EF), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x2F0), // Transmit end + ELC_EVENT_SCI6_ERI = (0x2F1), // Receive error + ELC_EVENT_SCI6_AED = (0x2F2), // Active edge detection + ELC_EVENT_SCI6_BFD = (0x2F3), // Break field detection + ELC_EVENT_SCI6_AM = (0x2F4), // Address match event + ELC_EVENT_SCI7_RXI = (0x2F5), // Receive data full + ELC_EVENT_SCI7_TXI = (0x2F6), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x2F7), // Transmit end + ELC_EVENT_SCI7_ERI = (0x2F8), // Receive error + ELC_EVENT_SCI7_AED = (0x2F9), // Active edge detection + ELC_EVENT_SCI7_BFD = (0x2FA), // Break field detection + ELC_EVENT_SCI7_AM = (0x2FB), // Address match event + ELC_EVENT_SCI8_RXI = (0x2FC), // Receive data full + ELC_EVENT_SCI8_TXI = (0x2FD), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x2FE), // Transmit end + ELC_EVENT_SCI8_ERI = (0x2FF), // Receive error + ELC_EVENT_SCI8_AED = (0x300), // Active edge detection + ELC_EVENT_SCI8_BFD = (0x301), // Break field detection + ELC_EVENT_SCI8_AM = (0x302), // Address match event + ELC_EVENT_SCI9_RXI = (0x303), // Receive data full + ELC_EVENT_SCI9_TXI = (0x304), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x305), // Transmit end + ELC_EVENT_SCI9_ERI = (0x306), // Receive error + ELC_EVENT_SCI9_AED = (0x307), // Active edge detection + ELC_EVENT_SCI9_BFD = (0x308), // Break field detection + ELC_EVENT_SCI9_AM = (0x309), // Address match event + ELC_EVENT_SCI10_RXI = (0x30A), // Receive data full + ELC_EVENT_SCI10_TXI = (0x30B), // Transmit data empty + ELC_EVENT_SCI10_TEI = (0x30C), // Transmit end + ELC_EVENT_SCI10_ERI = (0x30D), // Receive error + ELC_EVENT_SCI10_AED = (0x30E), // Active edge detection + ELC_EVENT_SCI10_BFD = (0x30F), // Break field detection + ELC_EVENT_SCI10_AM = (0x310), // Address match event + ELC_EVENT_SCI11_RXI = (0x311), // Receive data full + ELC_EVENT_SCI11_TXI = (0x312), // Transmit data empty + ELC_EVENT_SCI11_TEI = (0x313), // Transmit end + ELC_EVENT_SCI11_ERI = (0x314), // Receive error + ELC_EVENT_SCI11_AED = (0x315), // Active edge detection + ELC_EVENT_SCI11_BFD = (0x316), // Break field detection + ELC_EVENT_SCI11_AM = (0x317), // Address match event + ELC_EVENT_SPI0_RXI = (0x318), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x319), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x31A), // Idle + ELC_EVENT_SPI0_ERI = (0x31B), // Error + ELC_EVENT_SPI0_TEI = (0x31C), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x31D), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x31E), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x31F), // Idle + ELC_EVENT_SPI1_ERI = (0x320), // Error + ELC_EVENT_SPI1_TEI = (0x321), // Transmission complete event + ELC_EVENT_CAN_RXF = (0x322), // Global receive FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x323), // Global error + ELC_EVENT_CAN0_DMAREQ0 = (0x324), // RX fifo DMA request 0 + ELC_EVENT_CAN0_DMAREQ1 = (0x325), // RX fifo DMA request 1 + ELC_EVENT_CAN1_DMAREQ0 = (0x328), // RX fifo DMA request 0 + ELC_EVENT_CAN1_DMAREQ1 = (0x329), // RX fifo DMA request 1 + ELC_EVENT_CAN0_TX = (0x32C), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x32D), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x32E), // Common FIFO receive interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x32F), // Channel DMA request + ELC_EVENT_CAN0_RXMB = (0x330), // Receive message buffer interrupt + ELC_EVENT_CAN1_TX = (0x331), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x332), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x333), // Common FIFO receive interrupt + ELC_EVENT_CAN1_CF_DMAREQ = (0x334), // Channel DMA request + ELC_EVENT_CAN1_RXMB = (0x335), // Receive message buffer interrupt + ELC_EVENT_CAN0_MRAM_ERI = (0x338), // CANFD0 ECC error + ELC_EVENT_CAN1_MRAM_ERI = (0x339), // CANFD1 ECC error + ELC_EVENT_I3C0_RESPONSE = (0x33A), // Response status buffer full + ELC_EVENT_I3C0_COMMAND = (0x33B), // Command buffer empty + ELC_EVENT_I3C0_IBI = (0x33C), // IBI status buffer full + ELC_EVENT_I3C0_RX = (0x33D), // Receive + ELC_EVENT_IICB0_RXI = (0x33D), // Receive + ELC_EVENT_I3C0_TX = (0x33E), // Transmit + ELC_EVENT_IICB0_TXI = (0x33E), // Transmit + ELC_EVENT_I3C0_RCV_STATUS = (0x33F), // Receive status buffer full + ELC_EVENT_I3C0_HRESP = (0x340), // High priority response queue full + ELC_EVENT_I3C0_HCMD = (0x341), // High priority command queue empty + ELC_EVENT_I3C0_HRX = (0x342), // High priority rx data buffer full + ELC_EVENT_I3C0_HTX = (0x343), // High priority tx data buffer empty + ELC_EVENT_I3C0_TEND = (0x344), // Transmit end + ELC_EVENT_IICB0_TEI = (0x344), // Transmit end + ELC_EVENT_I3C0_EEI = (0x345), // Error + ELC_EVENT_IICB0_ERI = (0x345), // Error + ELC_EVENT_I3C0_STEV = (0x346), // Synchronous timing + ELC_EVENT_I3C0_MREFOVF = (0x347), // MREF counter overflow + ELC_EVENT_I3C0_MREFCPT = (0x348), // MREF capture + ELC_EVENT_I3C0_AMEV = (0x349), // Additional master-initiated bus event + ELC_EVENT_I3C0_WU = (0x34A), // Wake-up Condition Detection interrupt + ELC_EVENT_ADC_LIMCLPI = (0x34B), // Limiter clip interrupt with the limit table 0 to 7 + ELC_EVENT_ADC_FIFOOVF = (0x34C), // FIFO data overflow + ELC_EVENT_ADC_ADI0 = (0x34D), // End of A/D scanning operation(Gr.0) + ELC_EVENT_ADC_ADI1 = (0x34E), // End of A/D scanning operation(Gr.1) + ELC_EVENT_ADC_ADI2 = (0x34F), // End of A/D scanning operation(Gr.2) + ELC_EVENT_ADC_ADI3 = (0x350), // End of A/D scanning operation(Gr.3) + ELC_EVENT_ADC_ADI4 = (0x351), // End of A/D scanning operation(Gr.4) + ELC_EVENT_ADC_ADI5 = (0x352), // End of A/D scanning operation(Gr.5) + ELC_EVENT_ADC_ADI6 = (0x353), // End of A/D scanning operation(Gr.6) + ELC_EVENT_ADC_ADI7 = (0x354), // End of A/D scanning operation(Gr.7) + ELC_EVENT_ADC_ADI8 = (0x355), // End of A/D scanning operation(Gr.8) + ELC_EVENT_ADC_FIFOREQ0 = (0x356), // FIFO data read request interrupt(Gr.0) + ELC_EVENT_ADC_FIFOREQ1 = (0x357), // FIFO data read request interrupt(Gr.1) + ELC_EVENT_ADC_FIFOREQ2 = (0x358), // FIFO data read request interrupt(Gr.2) + ELC_EVENT_ADC_FIFOREQ3 = (0x359), // FIFO data read request interrupt(Gr.3) + ELC_EVENT_ADC_FIFOREQ4 = (0x35A), // FIFO data read request interrupt(Gr.4) + ELC_EVENT_ADC_FIFOREQ5 = (0x35B), // FIFO data read request interrupt(Gr.5) + ELC_EVENT_ADC_FIFOREQ6 = (0x35C), // FIFO data read request interrupt(Gr.6) + ELC_EVENT_ADC_FIFOREQ7 = (0x35D), // FIFO data read request interrupt(Gr.7) + ELC_EVENT_ADC_FIFOREQ8 = (0x35E), // FIFO data read request interrupt(Gr.8) + ELC_EVENT_ADC_CMPI0 = (0x35F), // Compare match interrupt with compare table 0 + ELC_EVENT_ADC_CMPI1 = (0x360), // Compare match interrupt with compare table 1 + ELC_EVENT_ADC_CCMPM0 = (0x361), // Composite compare match 0 + ELC_EVENT_ADC_CCMPUM0 = (0x362), // Composite condition compare mismatch 0 + ELC_EVENT_ADC_ERR0 = (0x363), // A/D converter unit 0 Error + ELC_EVENT_ADC_RESOVF0 = (0x364), // A/D conversion overflow on A/D converter unit 0 + ELC_EVENT_ADC_CALREQ0 = (0x365), // Calibration request unit 0 + ELC_EVENT_ADC_CALEND0 = (0x366), // End of calibration of A/D converter unit 0 + ELC_EVENT_ADC_CMPI2 = (0x367), // Compare match interrupt with compare table 2 + ELC_EVENT_ADC_CMPI3 = (0x368), // Compare match interrupt with compare table 3 + ELC_EVENT_ADC_CCMPM1 = (0x369), // Composite compare match 1 + ELC_EVENT_ADC_CCMPUM1 = (0x36A), // Composite condition compare mismatch 1 + ELC_EVENT_ADC_ERR1 = (0x36B), // A/D converter unit 1 Error + ELC_EVENT_ADC_RESOVF1 = (0x36C), // A/D conversion overflow on A/D converter unit 1 + ELC_EVENT_ADC_CALREQ1 = (0x36D), // Calibration request unit 1 + ELC_EVENT_ADC_CALEND1 = (0x36E), // End of calibration of A/D converter unit 1 + ELC_EVENT_DOC_INT = (0x36F), // Data operation circuit interrupt + ELC_EVENT_RSIP_TADI = (0x371), // RSIP Tamper Detection + ELC_EVENT_GLCDC_LINE_DETECT = (0x382), // Specified line + ELC_EVENT_GLCDC_UNDERFLOW_1 = (0x383), // Graphic 1 underflow + ELC_EVENT_GLCDC_UNDERFLOW_2 = (0x384), // Graphic 2 underflow + ELC_EVENT_DRW_INT = (0x385), // DRW interrupt + ELC_EVENT_MIPIDSI_SEQ0 = (0x388), // Sequence operation channel 0 interrupt + ELC_EVENT_MIPIDSI_SEQ1 = (0x389), // Sequence operation channel 1 interrupt + ELC_EVENT_MIPIDSI_VIN1 = (0x38A), // Video-Input operation channel1 interrupt + ELC_EVENT_MIPIDSI_RCV = (0x38B), // DSI packet receive interrupt + ELC_EVENT_MIPIDSI_FERR = (0x38C), // DSI fatal error interrupt + ELC_EVENT_MIPIDSI_PPI = (0x38D), // DSI D-PHY PPI interrupt + ELC_EVENT_MIPICSI_RX = (0x38F), // Receive interrupt + ELC_EVENT_MIPICSI_DL = (0x390), // Data Lane interrupt + ELC_EVENT_MIPICSI_VC = (0x391), // Virtual Channel interrupt + ELC_EVENT_MIPICSI_PM = (0x392), // Power Management interrupt + ELC_EVENT_MIPICSI_GST = (0x393), // Generic Short Packet interrupt + ELC_EVENT_VIN_IRQ = (0x395), // Interrupt Request + ELC_EVENT_VIN_ERR = (0x396), // Interrupt Request for SYNC Error + ELC_EVENT_CEU_CEUI = (0x397) // CEU interrupt +} elc_event_t; + +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) + +#define ELC_PERIPHERAL_NUM (33U) +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +/** Possible peripherals to be linked to event signals + * @note This list is device specific. + * */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_ADC0 = (19), + ELC_PERIPHERAL_ADC0_B = (20), + ELC_PERIPHERAL_ADC0_C = (21), + ELC_PERIPHERAL_ADC1 = (22), + ELC_PERIPHERAL_ADC1_B = (23), + ELC_PERIPHERAL_ADC1_C = (24), + ELC_PERIPHERAL_ADC2 = (25), + ELC_PERIPHERAL_ADC2_B = (26), + ELC_PERIPHERAL_ADC2_C = (27), + ELC_PERIPHERAL_I3C = (30), + ELC_PERIPHERAL_GPTP0 = (31), + ELC_PERIPHERAL_GPTP1 = (32) +} elc_peripheral_t; + +/** Positions of event link set registers (ELSRs) available on this MCU */ +#define BSP_ELC_PERIPHERAL_MASK (0x1CFFBF0FFU) + +/* UNCRUSTIFY-ON */ +/** @} (end addtogroup BSP_MCU_RA8P1) */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h new file mode 100644 index 0000000000..893e156034 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_feature.h @@ -0,0 +1,627 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_peripheral.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ +#define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x10U) +#if (BSP_CFG_XTAL_HZ >= (24000000)) + #define CGC_MAINCLOCK_DRIVE (0x5U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#elif (BSP_CFG_XTAL_HZ >= (8000000)) + #define CGC_MAINCLOCK_DRIVE (0x3U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#else + #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) +#endif + +// *UNCRUSTIFY-OFF* + +#define BSP_FEATURE_ACMPHS_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1UL) // Operation stabilization wait time. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) // The IVREF selection that corresponds to the internal voltage reference. + +#define BSP_FEATURE_ACMPLP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // Feature not available on this device. +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (0UL) // Check to see if the ADADC register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_UNUSED) // Clock source used for the ADC peripheral. +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. +#define BSP_FEATURE_ADC_HAS_ADBUF (0UL) // Determine if the ADBUFn registers are present. +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (0UL) // Determine if the ADPRC field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (0UL) // Determine if the ADRFMT field exists on the ADCER register. +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0UL) // Determine if the ADHVREFCNT register is available. +#define BSP_FEATURE_ADC_HAS_CLOCK (1UL) // Indicates there is a separate clock for the ADC. +#define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (0UL) // Maximum ADC resolution supported. +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. +#define BSP_FEATURE_ADC_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK (0x00UL) // Mask of available channels in ADC unit 0. +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK (0x00UL) // Mask of available channels in ADC unit 1. +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x03UL) // Mask of whole, physical ADC units present in the MCU. + +#define BSP_FEATURE_ADC_B_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Mask of ADC_B peripherals that support PGA. +#define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Programmable Gain Amplifier is supported. +#define BSP_FEATURE_ADC_B_TSN_SLOPE (4000UL) // DEPRECATED; use BSP_FEATURE_TSN_SLOPE. +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS_MASK (0x00770373007F503FULL) // Mask of channels available to ADC_B Unit 0. +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS_MASK (0x00770373007FAFC0ULL) // Mask of channels available to ADC_B Unit 1. + +#define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ADC_D_CHANNELS_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_IS_ADC12 (0UL) // Feature not available on this device. +#define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (2U) // Number of channels for only AGT (not AGTW) peripherals. +#define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (0U) // Number of channels for only AGTW (not AGT) peripherals. +#define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03UL) // A mask of all valid AGTx channels. + +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. +#define BSP_FEATURE_BSP_HAS_DSMIF_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_DTCM (1UL) // Indicates DTCM is available. +#define BSP_FEATURE_BSP_HAS_ESC_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_ETHPHY_CLOCK (1UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. +#define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (1UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. +#define BSP_FEATURE_BSP_HAS_ITCM (1UL) // Indicates ITCM is available. +#define BSP_FEATURE_BSP_HAS_OFS2 (1UL) // Indicates the OFS2 register is available. +#define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. +#define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. +#define BSP_FEATURE_BSP_HAS_SYRACCR (1UL) // SYRACCR register is available. +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. +#define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. +#define BSP_FEATURE_BSP_NUM_PMSAR (14UL) // Number of available Port Security Attribution Registers. +#define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. +#define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. +#define BSP_FEATURE_BSP_PART_NUMBER_OFFSET (0x00UL) // Bit offset of the Part Number in the mcu info block. +#define BSP_FEATURE_BSP_PART_NUMBER_POINTER (0x02C1EC38UL) // Address of the Part Numbering register (PNR). +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. +#define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x02F07B00UL) // Address of the MCU Unique ID register (UIDR). +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. + +#define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. +#define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CANFD_FD_SUPPORT (1UL) // Flexible data rate support. +#define BSP_FEATURE_CANFD_HAS_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. +#define BSP_FEATURE_CANFD_LITE (1UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. +#define BSP_FEATURE_CANFD_NUM_CHANNELS (1UL) // Number of CANFD channels per CANFD peripheral instance. +#define BSP_FEATURE_CANFD_NUM_INSTANCES (2UL) // Number of hardware instances of the CANFD peripheral. + +#define BSP_FEATURE_CEC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CEC_HAS_CLOCK (0UL) // Feature not available on this device. + +#define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (0UL) // Indicates the system clock can be sourced by the LOCO. +#define BSP_FEATURE_CGC_HAS_BCLK (1UL) // External Bus Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK (1UL) // CPU Clock is available. +#define BSP_FEATURE_CGC_HAS_CPUCLK1 (1UL) // CPU1 Clock is available. +#define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0UL) // FLDWAITR register is available. +#define BSP_FEATURE_CGC_HAS_FLL (1UL) // FLL is available. +#define BSP_FEATURE_CGC_HAS_FLWT (0UL) // FLWT register is available. +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0UL) // MEMWAIT register is available. +#define BSP_FEATURE_CGC_HAS_MOCO (1UL) // Middle clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MOSC (1UL) // Main clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_MRICLK (1UL) // MRAM bus clock is available. +#define BSP_FEATURE_CGC_HAS_NPUCLK (1UL) // NPU clock is available. +#define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. +#define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. +#define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. +#define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. +#define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. +#define BSP_FEATURE_CGC_HAS_PCLKE (1UL) // Peripheral module clock E is available. +#define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. +#define BSP_FEATURE_CGC_HAS_PLL2 (1UL) // PLL2 is available. +#define BSP_FEATURE_CGC_HAS_SOPCCR (0UL) // SOPCCR register is available. +#define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0UL) // SRAMPRCR2 register is available. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1UL) // SRAM Wait State Control Register is available. +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_1) // Reset value of the ICLK divider. +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. +#define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0UL) // Middle speed clock maximum frequency. +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15UL) // MOCO stabilization time in microseconds. +#define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV0_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. +#define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV0_Pos) // Shift used for MODRV register. +#define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. +#define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (960000000UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ (24000000UL) // Maximum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ (8000000UL) // Minimum input frequency for PLL (after input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ (48000000UL) // Maximum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ (8000000UL) // Minimum input frequency of the PLL (before input divider). +#define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (1200000000UL) // Maximum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (60000000UL) // Minimum output frequency for PLL unit 1. +#define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (3UL) // Number of output clocks for PLL1. +#define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (3UL) // Number of output clocks for PLL2. +#define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (1200000000UL) // Maximum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (60000000UL) // Minimum output frequency for PLL unit 2. +#define BSP_FEATURE_CGC_PLLCCR_TYPE (6UL) // Indicates the type of PLLCCR register and PLL. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (2400000000UL) // PLL VCO maximum frequency. +#define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (960000000UL) // PLL VCO minimum frequency. +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. +#define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIVCR.PCLKB. +#define BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK (BSP_NUMBER_OF_CORES == 2U ? 0U : 1U) // Requires the SCKDIVCR2.CPUCLK1 bits to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (1UL) // Indicates the SCKDIVCR2 register has additional clocks. +#define BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK (0UL) // Requires the bits [11:8] to match SCKDIVCR2.MRICLK. +#define BSP_FEATURE_CGC_SODRV_MASK (0x03UL) // Sub-clock drive field mask. +#define BSP_FEATURE_CGC_SODRV_SHIFT (0UL) // Sub-clock drive field shift. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (8UL) // Bit offset for SRAMPRCR.KW field. +#define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0xA5U) // Write enable key code for SRAMPRCR bit. +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x00UL) // Reset value for the OPCCR regsiter. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x00UL) // Reset value for the SCKDIVCR register. +#define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. +#define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. + +#define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. +#define BSP_FEATURE_CRC_HAS_SNOOP (1UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. +#define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. +#define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x04UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. + +#define BSP_FEATURE_CTSU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_CTSU_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x00UL) // DAADSCR register is available. +#define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (1UL) // Number of available channels per DAC_B instance. +#define BSP_FEATURE_DAC_B_UNIT_COUNT (2UL) // Number of available DAC_B instance. +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (0UL) // At least one channel supports A/D synchronization with the DAC. +#define BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL (0UL) // DAC output can be routed to specific extra internal modules using DAASWCR register. +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0UL) // DAVREFCR register is available. +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0UL) // DAAMPCR register is available. + +#define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DAC12_IS_AVAILABLE (0UL) +#define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. +#define BSP_FEATURE_DAC12_UNIT_COUNT (0UL) // Feature not available on this device. + +#define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_DMCTL (1UL) // DMCTL register is available in the DMA peripheral block. +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). +#define BSP_FEATURE_DMAC_NUM_CHANNELS (8UL) // Number of DMAC channels available. + +#define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_DOC_VERSION (2UL) // The version of the DOC peripheral. + +#define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (16UL) // Byte alignment that must be used for DTC transfer info structs. + +#define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. + +#define BSP_FEATURE_ELC_VERSION (2UL) // Version of the ELC peripheral. + +#define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_ESC_NUM_PORTS (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ESWM_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM (8UL) // Number of IPV based transmission queue for each port. +#define BSP_FEATURE_ESWM_FRER_TABLE_SIZE (128UL) // Maximum number of FRER table entry. +#define BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM (4UL) // Number of Pulse Generator. +#define BSP_FEATURE_ESWM_GPTP_TIMER_NUM (2UL) // Number of gPTP timer. +#define BSP_FEATURE_ESWM_GWCA_PORT (2UL) // Port number of the CPU. +#define BSP_FEATURE_ESWM_HAS_CLOCK (1UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_ESWM_HAS_DOMAIN (1UL) // Indicates that the MCU has a power domain specifically for ESWM peripherals. +#define BSP_FEATURE_ESWM_HAS_ESWPHY_CLOCK (1UL) // Flag indicating an extra peripheral clock is present. +#define BSP_FEATURE_ESWM_MAX_QUEUE_NUM (64UL) // The number of AXI bus descriptors available to Ethernet components. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM (8UL) // Maximum number of PSFP Meter filter which supports double bucket meters. +#define BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM (32UL) // Maximum number of PSFP Meter filter. +#define BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM (16UL) // Maximum number of PSFP MSDU filter. +#define BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM (2UL) // Number of TS reception descriptor queue. + +#define BSP_FEATURE_ETHER_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x070FUL) // Valid value of EDMACn.FDR register. +#define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (64UL) // The number of AXI bus descriptors available to Ethernet components. +#define BSP_FEATURE_ETHER_NUM_CHANNELS (2UL) // Number of available ethernet PHYs. +#define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (1UL) // Whether or not the ETHERC peripheral supports TrustZone secure access. + +#define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (64UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. +#define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (4L) // Number of non-secure application anti-rollback counters that can be configured. +#define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (256UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. +#define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (64UL) // Number of counter bits for the ARC_OEMBL counter. +#define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (64UL) // Number of counter bits for the ARC_SEC counter. +#define BSP_FEATURE_FLASH_CACHE (0UL) // Flash cache is present. +#define BSP_FEATURE_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. +#define BSP_FEATURE_FLASH_CODE_CACHE_VERSION (2UL) // Version of C-Cache implemented in a CM33 core. +#define BSP_FEATURE_FLASH_CODE_FLASH_START (0x02000000UL) // Start address of the Code Flash region. +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x27000000UL) // Start address of the Data Flash region. +#define BSP_FEATURE_FLASH_PREFETCH_BUFFER (0UL) // Indicates the prefetch buffer is available on the flash. +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). +#define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (1UL) // Flash supports anti-rollback counter (ARC_* registers are available). +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). +#define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. + +#define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_HP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (FSP_PRIV_CLOCK_UNUSED) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. +#define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFFUL) // Mask of 32-bit GPT channel indices. +#define BSP_FEATURE_GPT_AD_CONVERSION_START_CHANNEL_MASK (0x3FFFUL) // Mask of GPT channels supporting A/D conversion start. +#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (1UL) // GPT A/D conversion start request is directly output to ADC instead of via the ELC. +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FFFUL) // Mask of channels that support event count input (has GTUPSR register). +#define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. +#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x3FF0UL) // Mask of GPT channels that are the GPTE implementation. +#define BSP_FEATURE_GPT_GPTE_SUPPORTED (1UL) // At least one GPTE implementation is available, GPTE implementations have a GTITC register. +#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x0FUL) // Mask of GPT channels that are the GPTEH implementation. +#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (1UL) // At least one GPTEH implementation is available, GPTEH implementations have a PDG module. +#define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FFFUL) // Mask of channels that support dead time control. +#define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. +#define BSP_FEATURE_GPT_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. +#define BSP_FEATURE_GPT_MSTP_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. +#define BSP_FEATURE_GPT_MSTP_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. +#define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (160000000UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. +#define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) ((BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN <= (gpt_frequency)) ? 1UL : 0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (300000000UL) // Maximum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (80000000UL) // Minimum supported frequency of the PWM Delay Generation circuit. +#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. +#define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. +#define BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED (1UL) // At least one GPT channel supports polarity inversion of the GTIOCnA or GTIOCnB I/O pins. +#define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. + +#define BSP_FEATURE_I3C_IS_AVAILABLE (1UL) +#define BSP_FEATURE_I3C_HAS_CLOCK (1UL) // Indicates there is a separate clock for the I3C. +#define BSP_FEATURE_I3C_HAS_HDR_MODE (1UL) // I3C support high data rate mode. +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (8UL) // Maximum number of bus devices. +#define BSP_FEATURE_I3C_MSTP_OFFSET (4UL) // Offset of the MSTP bit for the I3C peripherals. +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (16UL) // Depth of the normal transmit data buffer. +#define BSP_FEATURE_I3C_NUM_CHANNELS (1UL) // Total number of available channels. + +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. +#define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. +#define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. +#define BSP_FEATURE_ICU_HAS_LOCO_FILTER (0UL) // Register IRQCR has LOCOSEL. +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. +#define BSP_FEATURE_ICU_HAS_WUPEN2 (0UL) // WUPEN2 register is available. +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFFFFFUL) // Mask of available IRQ control registers. +#define BSP_FEATURE_ICU_NMIER_MAX_INDEX (20UL) // Maximum bit field index of valid fields of the NMIER register. +#define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFFFFFF88FF1DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. + +#define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER (5UL) // Multiplication factor to calculate SDA bus free time. +#define BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA (0UL) // SCL status needs to be checked before writing the transmission data in master mode. +#define BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK (0x01UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x01UL) // Mask of available IIC_B or compatible I3C channels. +#define BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK (7UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. +#define BSP_FEATURE_IIC_HAS_CLOCK (0UL) // Indicates there is a separate IIC clock. +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07UL) // Mask of available IIC channels. + +#define BSP_FEATURE_IOPORT_CCD_PINS_MASK (0x00UL) // Mask of valid indices for CCD pins. +#define BSP_FEATURE_IOPORT_ELC_PORTS_MASK (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. +#define BSP_FEATURE_IOPORT_HAS_LVOCR (1UL) // The LVOCR register is available. +#define BSP_FEATURE_IOPORT_VERSION (2UL) // Version of the system PFS block. + +#define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (16384UL) // Frequency of the independent watchdog clock source. +#define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (1UL) // IWDT peripheral supports register start mode. + +#define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) +#define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. + +#define BSP_FEATURE_LCD_HAS_CLOCK (1UL) // Indicates there is a separate clock for the LCD. + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x000000FFFF13FFFFULL) // Mask of valid bit-fields of the DPSIEGRn registers. +#define BSP_FEATURE_LPM_DPSIER_MASK (0x0000FFFFEF1FFFFFULL) // Mask of valid bit-fields of the DPSIERn registers. +#define BSP_FEATURE_LPM_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (1UL) // The device supports deep sleep mode. +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1UL) // The device supports deep standby mode. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE (1UL) // The DPSBYCR.DCSSMODE field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0UL) // The DPSBYCR.DEEPCUT field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0UL) // The DPSBYCR.DPSBY field is available. +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR3 (1UL) // The DPSIEGR3 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIEGR4 (1UL) // The DPSIEGR4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER4 (1UL) // The DPSIER4 register is available. +#define BSP_FEATURE_LPM_HAS_DPSIER5 (1UL) // The DPSIER5 register is available. +#define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. +#define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. +#define BSP_FEATURE_LPM_HAS_LDO_SKEEP (1UL) // PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers are available. +#define BSP_FEATURE_LPM_HAS_LPSCR (1UL) // The LPSCR register is available. +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (1UL) // The PDRAMSCRn registers are available. +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1UL) // The SBYCR.OPE field is available. +#define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (0UL) // The SBYCR.SSBY field is available. +#define BSP_FEATURE_LPM_HAS_SNOOZE (0UL) // The MCU supports Snooze. +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0UL) // The SNZEDCR1 register is available. +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0UL) // The SNZREQCR1 register is available. +#define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. +#define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. +#define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x00UL) // Mask of valid bits for the SNZEDCRn registers. +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x00ULL) // Mask of valid bits for the SNZREQCRn registers. +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (1UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. +#define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. + +#define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) +#define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. +#define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VBAT reference voltage low threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage high threshold. +#define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD (LVD_THRESHOLD_NOT_AVAILABLE) // External LVD for VRTC reference voltage low threshold. +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1UL) // Digital input filtering is available. +#define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_3_86V) // Typical higher bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_1_71V) // Typical lower bound of the detection threshold for LVD1. +#define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (30UL) // Maximum stabilization time to wait after LVD1 is enabled. +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_3_86V) // Typical higher bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_LEVEL_1_71V) // Typical lower bound of the detection threshold for LVD2. +#define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (30UL) // Maximum stabilization time to wait after LVD2 is enabled. +#define BSP_FEATURE_LVD_MONITOR_MASK (0x1BUL) // Mask of programmable monitors. +#define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (1UL) // Voltage monitors support rising edge detections (i.e. +#define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. +#define BSP_FEATURE_LVD_VERSION (3UL) // Version of the LVD peripheral. +#define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. +#define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. + +#define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. + +#define BSP_FEATURE_MIPI_CSI_IS_AVAILABLE (1UL) + +#define BSP_FEATURE_MIPI_DSI_IS_AVAILABLE (1UL) + +#define BSP_FEATURE_MIPI_PHY_IS_AVAILABLE (1UL) + +#define BSP_FEATURE_MRAM_IS_AVAILABLE (1UL) +#define BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES (32UL) // Write size for code MRAM. + +#define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_OSPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x80000000UL) // Start address of the CS0 memory mapped region for OSPI. +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x90000000UL) // Start address of the CS1 memory mapped region for OSPI. +#define BSP_FEATURE_OSPI_HAS_CLOCK (1UL) // Indicates there is a separate clock for the OSPI. + +#define BSP_FEATURE_OSPI_B_IS_AVAILABLE (1UL) +#define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x80000000UL) // Start address of the CS0 memory mapped region for OSPI_B. +#define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x90000000UL) // Start address of the CS1 memory mapped region for OSPI_B. +#define BSP_FEATURE_OSPI_B_UNIT_COUNT (2UL) // Number of OSPI_B peripheral units available. + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. +#define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. +#define BSP_FEATURE_POEG_MSTP_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. + +#define BSP_FEATURE_QSPI_IS_AVAILABLE (0UL) +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. +#define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. +#define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E11A. +#define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E31A. +#define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (1UL) // The device supports cryptography using RSIP-E50D. +#define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP-E51A. +#define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. +#define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. +#define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. +#define BSP_FEATURE_RSIP_SCE9_SUPPORTED (0UL) // The device supports cryptography using SCE9. +#define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. + +#define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) +#define BSP_FEATURE_RTC_HAS_ALARM1 (0UL) // Alarm 1 is available. +#define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. +#define BSP_FEATURE_RTC_HAS_ROPSEL (0UL) // The RCR4.ROPSEL field is available. +#define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. +#define BSP_FEATURE_RTC_HAS_VBTICTLR (1UL) // System supports VBATT input control to the RTC. +#define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. +#define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. + +#define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK (0x00UL) // Mask of channels with data compare match (DCCR) available. +#define BSP_FEATURE_SCI_CHANNELS_MASK (0x03FFUL) // Mask of available SCI channels. +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. +#define BSP_FEATURE_SCI_HAS_CLOCK (1UL) // Indicates there is a separate SCI clock. +#define BSP_FEATURE_SCI_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. +#define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x00UL) // Mask of channels that support IrDA. +#define BSP_FEATURE_SCI_IRDA_SUPPORTED (0UL) // Indicates IrDA is supported on at least one SCI channel. +#define BSP_FEATURE_SCI_LIN_CHANNELS_MASK (0x03FFUL) // Mask of channels that can support LIN. +#define BSP_FEATURE_SCI_SPI_SCKSEL_MASK (1UL) // Mask indicating CCR4.SCKSEL is available. +#define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK (0x00UL) // List of channels that do not support ABCSE functionality. +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK (0x03FFUL) // Mask of channels which support CTS external pins. +#define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK (0x03FFUL) // Mask of channels which support the UART FIFO. +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. +#define BSP_FEATURE_SCI_VERSION (2UL) // Version of the SCI peripheral. + +#define BSP_FEATURE_SDADC_HAS_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. + +#define BSP_FEATURE_SDHI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) // Clock source for the SDHI peripheral clock. +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1UL) // Peripheral can detect if a card is present or not based on signal pull-ups. +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Smallest shift value for the divider pre-scaller available on the SDHI clock. +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1UL) // Supports 8-bit data bus width to the MMC device. +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x03UL) // Mask of valid SDHI channels. + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x68000000UL) // Start address of the external address space for SDRAM memory. + +#define BSP_FEATURE_SLCDC_IS_AVAILABLE (0UL) +#define BSP_FEATURE_SLCDC_CONTRAST_MAX (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (0UL) // Feature not available on this device. +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0UL) // Feature not available on this device. + +#define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED (1UL) // Burst transfer without delay between frames is supported. +#define BSP_FEATURE_SPI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. +#define BSP_FEATURE_SPI_HAS_CLOCK (1UL) // Indicates there is a separate clock for the SPI. +#define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. +#define BSP_FEATURE_SPI_NUM_CHANNELS (2UL) // Number of available SPI channels. +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x03UL) // Mask of channel indices that support SSL Level Keep. + +#define BSP_FEATURE_SRAM_HAS_EXTRA_SRAMSABAR (1UL) // Flag indicating that SRAMSABAR2 and SRAMSABAR3 are present. +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01UL) // Mask of bits needed to enable SRAM wait for all regions. + +#define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3UL) // Mask of valid SSI channel indices. + +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FIVE_ROM_WAITS (240000000UL) // Maximum frequency allowed before requiring five wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_FOUR_ROM_WAITS (192000000UL) // The maximum frequency allowed without having four ROM wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_NO_RAM_WAITS (100000000UL) // The maximum frequency that can be used before wait cycles are necessary. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_ONE_ROM_WAITS (48000000UL) // Maximum frequency allowed before requiring one wait cycle. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_THREE_ROM_WAITS (144000000UL) // Maximum frequency allowed before requiring three wait cycles. +#define BSP_FEATURE_SYSC_CLOCK_FREQ_TWO_ROM_WAITS (96000000UL) // Maximum frequency allowed before requiring two wait cycles. + +#define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. + +#define BSP_FEATURE_TML_IS_AVAILABLE (0UL) +#define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. +#define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. + +#define BSP_FEATURE_TSN_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. +#define BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE (1UL) // Determine if TSCDR is available for TSN. +#define BSP_FEATURE_TSN_CALIBRATION32_MASK (0xFFFFUL) // Mask of valid bits for TSN calibration. +#define BSP_FEATURE_TSN_CONTROL_AVAILABLE (1UL) // Determine if the TSCR register is present. +#define BSP_FEATURE_TSN_HAS_LOW_TEMP_REG (0UL) // Determine if the TSCDRL (Low Temperature) is present. +#define BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG (0UL) // Determine if the TSCDRR (Room Temperature) is present. +#define BSP_FEATURE_TSN_SLOPE (4000UL) // Typical slope for the temperature sensor, in uV/degC. + +#define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) +#define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. +#define BSP_FEATURE_TZ_HAS_TZFSAR (0UL) // Specifies the TrustZone filter can be secured. +#define BSP_FEATURE_TZ_NS_OFFSET (0x10000000UL) // Offset for the Non-secure address space of a peripheral. +#define BSP_FEATURE_TZ_VERSION (2UL) // Version of the TrustZone implementation. + +#define BSP_FEATURE_UARTA_IS_AVAILABLE (0UL) +#define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Feature not available on this device. +#define BSP_FEATURE_UARTA_PCLK_RESTRICTION (0UL) // Feature not available on this device. + +#define BSP_FEATURE_ULPT_IS_AVAILABLE (1UL) +#define BSP_FEATURE_ULPT_NUM_CHANNELS_AVAILABLE (2UL) // Number of channels available for ULPT. +#define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (3UL) // Mask of available channels for ULPT. + +#define BSP_FEATURE_USB_IS_AVAILABLE (1UL) +#define BSP_FEATURE_USB_HAS_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. +#define BSP_FEATURE_USB_HAS_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. +#define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. +#define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. +#define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. +#define BSP_FEATURE_USB_HAS_USB60_CLOCK (1UL) // Indicates the USB60 clock is available. +#define BSP_FEATURE_USB_HAS_USBCKDIVCR (1UL) // USBCKDIVCR register is available. +#define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. +#define BSP_FEATURE_USB_HAS_USBFS_BC (0UL) // Supports battery charging in full-speed mode. +#define BSP_FEATURE_USB_HAS_USBHS (1UL) // Supports USB 2.0 High-Speed mode. +#define BSP_FEATURE_USB_HAS_USBHS_BC (1UL) // Supports battery charging in high-speed mode. +#define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. +#define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0UL) // Indicates the PHYSECTRL.CNEN field is available. +#define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. +#define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. +#define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (0UL) // Indicates the UCKSEL.UCKSELC bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. +#define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. +#define BSP_FEATURE_USB_SCKDIVCR2_HAS_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR2 register. + +#define BSP_FEATURE_VIN_IS_AVAILABLE (1UL) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c new file mode 100644 index 0000000000..4cee90e3e3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_linker.c @@ -0,0 +1,99 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/* UNCRUSTIFY-OFF */ + +/* boot loaded applications cannot set ofs registers (only do so in the boot loader) */ +#ifndef BSP_BOOTLOADED_APPLICATION +/** configuration register output to sections */ +#if defined BSP_CFG_OPTION_SETTING_OFS0 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_cfg_option_setting_ofs0[] = {BSP_CFG_OPTION_SETTING_OFS0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS2 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs2") g_bsp_cfg_option_setting_ofs2[] = {BSP_CFG_OPTION_SETTING_OFS2}; +#endif +#if defined BSP_CFG_OPTION_SETTING_SAS && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_cfg_option_setting_sas[] = {BSP_CFG_OPTION_SETTING_SAS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1 && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_cfg_option_setting_ofs1[] = {BSP_CFG_OPTION_SETTING_OFS1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEC && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_cfg_option_setting_ofs1_sec[] = {BSP_CFG_OPTION_SETTING_OFS1_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS1_SEL && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_cfg_option_setting_ofs1_sel[] = {BSP_CFG_OPTION_SETTING_OFS1_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS3 && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3") g_bsp_cfg_option_setting_ofs3[] = {BSP_CFG_OPTION_SETTING_OFS3}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS3_SEC && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sec") g_bsp_cfg_option_setting_ofs3_sec[] = {BSP_CFG_OPTION_SETTING_OFS3_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OFS3_SEL && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs3_sel") g_bsp_cfg_option_setting_ofs3_sel[] = {BSP_CFG_OPTION_SETTING_OFS3_SEL}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps") g_bsp_cfg_option_setting_bps[] = {BSP_CFG_OPTION_SETTING_BPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_BPS_SEC && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec") g_bsp_cfg_option_setting_bps_sec[] = {BSP_CFG_OPTION_SETTING_BPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL0 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_fsblctrl0") g_bsp_cfg_option_setting_otp_fsblctrl0[] = {BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL0}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL1 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_fsblctrl1") g_bsp_cfg_option_setting_otp_fsblctrl1[] = {BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL1}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL2 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_fsblctrl2") g_bsp_cfg_option_setting_otp_fsblctrl2[] = {BSP_CFG_OPTION_SETTING_OTP_FSBLCTRL2}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SAMR && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_samr") g_bsp_cfg_option_setting_otp_samr[] = {BSP_CFG_OPTION_SETTING_OTP_SAMR}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC00 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc00") g_bsp_cfg_option_setting_otp_sacc00[] = {BSP_CFG_OPTION_SETTING_OTP_SACC00}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC10 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc10") g_bsp_cfg_option_setting_otp_sacc10[] = {BSP_CFG_OPTION_SETTING_OTP_SACC10}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC01 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc01") g_bsp_cfg_option_setting_otp_sacc01[] = {BSP_CFG_OPTION_SETTING_OTP_SACC01}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC11 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc11") g_bsp_cfg_option_setting_otp_sacc11[] = {BSP_CFG_OPTION_SETTING_OTP_SACC11}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC02 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc02") g_bsp_cfg_option_setting_otp_sacc02[] = {BSP_CFG_OPTION_SETTING_OTP_SACC02}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC12 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc12") g_bsp_cfg_option_setting_otp_sacc12[] = {BSP_CFG_OPTION_SETTING_OTP_SACC12}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC03 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc03") g_bsp_cfg_option_setting_otp_sacc03[] = {BSP_CFG_OPTION_SETTING_OTP_SACC03}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_SACC13 && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_sacc13") g_bsp_cfg_option_setting_otp_sacc13[] = {BSP_CFG_OPTION_SETTING_OTP_SACC13}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_PBPS_SEC && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_pbps_sec") g_bsp_cfg_option_setting_otp_pbps_sec[] = {BSP_CFG_OPTION_SETTING_OTP_PBPS_SEC}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_PBPS && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_pbps") g_bsp_cfg_option_setting_otp_pbps[] = {BSP_CFG_OPTION_SETTING_OTP_PBPS}; +#endif +#if defined BSP_CFG_OPTION_SETTING_OTP_ZHUK && !BSP_TZ_NONSECURE_BUILD && (BSP_CFG_CPU_CORE == 0) +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_otp_zhuk") g_bsp_cfg_option_setting_otp_zhuk[] = {BSP_CFG_OPTION_SETTING_OTP_ZHUK}; +#endif +#endif // BSP_BOOTLOADED_APPLICATION + +/******************************/ +/* the init tables are located in bsp_linker_info.h */ +#define BSP_LINKER_C +#include "bsp_linker_info.h" + +/* UNCRUSTIFY-ON */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h new file mode 100644 index 0000000000..86a5235fae --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_mcu_info.h @@ -0,0 +1,45 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA8P1 RA8P1 + * @{ + **********************************************************************************************************************/ + +// RA8P1_TODO: includedoc config_bsp_ra8p1_fsp.html + +/** @} (end defgroup BSP_MCU_RA8P1) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h new file mode 100644 index 0000000000..a9a64d1895 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_override.h @@ -0,0 +1,298 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8P1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8P1) */ + +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#if __has_include("r_lpm_device_types.h") + #include "r_lpm_device_types.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MCU. */ + +#define BSP_OVERRIDE_CGC_DIVIDER_CFG_T +#define BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T +#define BSP_OVERRIDE_GROUP_IRQ_T +#define BSP_OVERRIDE_IOPORT_PERIPHERAL_T +#define BSP_OVERRIDE_LVD_PERIPHERAL_T + +/* Override definitions. */ + +/* Private definition to set enumeration values. */ +#define IOPORT_PRV_PFS_PSEL_OFFSET (24) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, + * PCLKS A-D. */ +typedef enum e_cgc_sys_clock_div +{ + CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1 + CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2 + CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4 + CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8 + CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 + CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 + CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 + CGC_SYS_CLOCK_DIV_3 = 8, ///< System clock divided by 3 + CGC_SYS_CLOCK_DIV_6 = 9, ///< System clock divided by 6 + CGC_SYS_CLOCK_DIV_12 = 10, ///< System clock divided by 12 + CGC_SYS_CLOCK_DIV_24 = 11, ///< System clock divided by 24 +} cgc_sys_clock_div_t; + +/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::systemClockSet and @ref cgc_api_t::systemClockGet + * functions. */ +typedef struct st_cgc_divider_cfg +{ + union + { + uint32_t sckdivcr_w; ///< System clock Division control register + + struct + { + cgc_sys_clock_div_t pclkd_div : 4; ///< Divider value for PCLKD + cgc_sys_clock_div_t pclkc_div : 4; ///< Divider value for PCLKC + cgc_sys_clock_div_t pclkb_div : 4; ///< Divider value for PCLKB + cgc_sys_clock_div_t pclka_div : 4; ///< Divider value for PCLKA + cgc_sys_clock_div_t bclk_div : 4; ///< Divider value for BCLK + cgc_sys_clock_div_t pclke_div : 4; ///< Divider value for PCLKE + cgc_sys_clock_div_t iclk_div : 4; ///< Divider value for ICLK + cgc_sys_clock_div_t fclk_div : 4; ///< Divider value for FCLK + } sckdivcr_b; + }; + + union + { + uint16_t sckdivcr2; ///< System clock Division control register 2 + + struct + { + cgc_sys_clock_div_t cpuclk_div : 4; ///< Divider value for CPUCLK0 + cgc_sys_clock_div_t cpuclk1_div : 4; ///< Divider value for CPUCLK1 + cgc_sys_clock_div_t npuclk_div : 4; ///< Divider value for NPUCLK + cgc_sys_clock_div_t mriclk_div : 4; ///< Divider value for MRICLK + } sckdivcr2_b; + }; +} cgc_divider_cfg_t; + +/* Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_SOSC_STOP_DETECT = 5, ///< Sub Oscillation stop is detected + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_MPU_BUS_TZF = 12, ///< MPU Bus or TrustZone Filter Error + BSP_GRP_IRQ_COMMON_MEMORY = 13, ///< SRAM ECC or SRAM Parity Error + BSP_GRP_IRQ_LOCAL_MEMORY = 14, ///< Local Memory Error + BSP_GRP_IRQ_LOCKUP = 15, ///< LockUp Error + BSP_GRP_IRQ_FPU = 16, ///< FPU Exception + BSP_GRP_IRQ_MRC = 17, ///< MRAM Code read error + BSP_GRP_IRQ_MRE = 18, ///< MRAM Extra read error + BSP_GRP_IRQ_IPC = 20, ///< IPC Interrupt +} bsp_grp_irq_t; + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_peripheral +{ + /** Pin will functions as an IO pin */ + IOPORT_PERIPHERAL_IO = 0x00, + + /** Pin will function as a DEBUG pin */ + IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a SPI peripheral pin */ + IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a IIC peripheral pin */ + IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a KEY peripheral pin */ + IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a clock/comparator/RTC peripheral pin */ + IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC/ADC peripheral pin */ + IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a BUS peripheral pin */ + IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CTSU peripheral pin */ + IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CMPHS peripheral pin */ + IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a segment LCD peripheral pin */ + IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + +#if BSP_FEATURE_SCI_UART_DE_IS_INVERTED + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), +#else + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), +#endif + + /** Pin will function as a DALI peripheral pin */ + IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEU peripheral pin */ + IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAN peripheral pin */ + IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a QSPI peripheral pin */ + IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SSI peripheral pin */ + IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB full speed peripheral pin */ + IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB high speed peripheral pin */ + IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SD/MMC peripheral pin */ + IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet MMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet RMMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PDC peripheral pin */ + IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a graphics LCD peripheral pin */ + IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC peripheral pin */ + IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a debug trace peripheral pin */ + IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a OSPI peripheral pin */ + IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEC peripheral pin */ + IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a ULPT peripheral pin */ + IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a MIPI DSI peripheral pin */ + IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a RGMII peripheral pin */ + IOPORT_PERIPHERAL_ETHER_RGMII = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a ETHERNET slave controller peripheral pin */ + IOPORT_PERIPHERAL_ESC = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PDM peripheral pin */ + IOPORT_PERIPHERAL_PDM = (0x1BUL << IOPORT_PRV_PFS_PSEL_OFFSET), +} ioport_peripheral_t; + +/** The thresholds supported by each MCU are in the MCU User's Manual as well as + * in the r_lvd module description on the stack tab of the RA project. */ +typedef enum +{ + LVD_THRESHOLD_MONITOR_LEVEL_3_86V = 0x03UL, ///< 3.86V + LVD_THRESHOLD_MONITOR_LEVEL_3_14V = 0x04UL, ///< 3.14V + LVD_THRESHOLD_MONITOR_LEVEL_3_10V = 0x05UL, ///< 3.10V + LVD_THRESHOLD_MONITOR_LEVEL_3_08V = 0x06UL, ///< 3.08V + LVD_THRESHOLD_MONITOR_LEVEL_2_85V = 0x07UL, ///< 2.85V + LVD_THRESHOLD_MONITOR_LEVEL_2_83V = 0x08UL, ///< 2.83V + LVD_THRESHOLD_MONITOR_LEVEL_2_80V = 0x09UL, ///< 2.80V + LVD_THRESHOLD_MONITOR_LEVEL_2_62V = 0x0AUL, ///< 2.62V + LVD_THRESHOLD_MONITOR_LEVEL_2_33V = 0x0BUL, ///< 2.33V + LVD_THRESHOLD_MONITOR_LEVEL_1_90V = 0x0CUL, ///< 1.90V + LVD_THRESHOLD_MONITOR_LEVEL_1_86V = 0x0DUL, ///< 1.86V + LVD_THRESHOLD_MONITOR_LEVEL_1_74V = 0x0EUL, ///< 1.74V + LVD_THRESHOLD_MONITOR_LEVEL_1_71V = 0x0FUL, ///< 1.71V + LVD_THRESHOLD_NOT_AVAILABLE = 0xFFUL, ///< Not Used +} lvd_threshold_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h new file mode 100644 index 0000000000..71f2edda2e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/bsp_peripheral.h @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * + * AUTOGENERATED FILE. DO NOT EDIT. + * + **********************************************************************************************************************/ + +#ifndef BSP_PERIPHERAL_H +#define BSP_PERIPHERAL_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +// *UNCRUSTIFY-OFF* + +#define BSP_PERIPHERAL_ACMP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_PRESENT (1) +#define BSP_PERIPHERAL_ACMPHS_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_ACMPHS_B_PRESENT (0) +#define BSP_PERIPHERAL_ACMPHS_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ACMPLP_PRESENT (0) +#define BSP_PERIPHERAL_ACMPLP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_PRESENT (0) +#define BSP_PERIPHERAL_ADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ADC_B_PRESENT (1) +#define BSP_PERIPHERAL_ADC_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ADC_D_PRESENT (0) +#define BSP_PERIPHERAL_ADC_D_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AGT_PRESENT (1) +#define BSP_PERIPHERAL_AGT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_AGTW_PRESENT (0) +#define BSP_PERIPHERAL_AGTW_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_AMI_PRESENT (0) +#define BSP_PERIPHERAL_ANALOG_PRESENT (0) +#define BSP_PERIPHERAL_BUS_PRESENT (1) +#define BSP_PERIPHERAL_CAC_PRESENT (1) +#define BSP_PERIPHERAL_CACHE_PRESENT (0) +#define BSP_PERIPHERAL_CAN_PRESENT (0) +#define BSP_PERIPHERAL_CAN_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_CANFD_PRESENT (1) +#define BSP_PERIPHERAL_CANFD_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_CEC_PRESENT (0) +#define BSP_PERIPHERAL_CEU_PRESENT (1) +#define BSP_PERIPHERAL_CGC_PRESENT (1) +#define BSP_PERIPHERAL_CPSCU_PRESENT (1) +#define BSP_PERIPHERAL_CPU_CTRL_PRESENT (1) +#define BSP_PERIPHERAL_CRC_PRESENT (1) +#define BSP_PERIPHERAL_CTSU_PRESENT (0) +#define BSP_PERIPHERAL_DAC_PRESENT (0) +#define BSP_PERIPHERAL_DAC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC_B_PRESENT (1) +#define BSP_PERIPHERAL_DAC_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_DAC8_PRESENT (0) +#define BSP_PERIPHERAL_DAC8_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DAC12_PRESENT (0) +#define BSP_PERIPHERAL_DAC12_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DEBUG_PRESENT (1) +#define BSP_PERIPHERAL_DMA_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_PRESENT (1) +#define BSP_PERIPHERAL_DMA_DMAC_CHANNEL_MASK (0xFFU) +#define BSP_PERIPHERAL_DOC_PRESENT (1) +#define BSP_PERIPHERAL_DOC_B_PRESENT (0) +#define BSP_PERIPHERAL_DRW_PRESENT (1) +#define BSP_PERIPHERAL_DSMIF_PRESENT (0) +#define BSP_PERIPHERAL_DSMIF_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_DTC_PRESENT (1) +#define BSP_PERIPHERAL_ECCAFL_PRESENT (0) +#define BSP_PERIPHERAL_ECCAFL_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ECCMB_PRESENT (1) +#define BSP_PERIPHERAL_ECCMB_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_ELC_PRESENT (1) +#define BSP_PERIPHERAL_ELC_B_PRESENT (0) +#define BSP_PERIPHERAL_ESWM_PRESENT (1) +#define BSP_PERIPHERAL_ETHERC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EDMAC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EDMAC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_EPTPC_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_EPTPC_CFG_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_MII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ETHERC_RMII_PRESENT (0) +#define BSP_PERIPHERAL_ETHERC_RMII_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_FACI_PRESENT (0) +#define BSP_PERIPHERAL_FCACHE_PRESENT (0) +#define BSP_PERIPHERAL_FLAD_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_HP_PRESENT (0) +#define BSP_PERIPHERAL_FLASH_LP_PRESENT (0) +#define BSP_PERIPHERAL_GLCDC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_PRESENT (1) +#define BSP_PERIPHERAL_GPT_CHANNEL_MASK (0x3FFFU) +#define BSP_PERIPHERAL_GPT_GTCLK_PRESENT (1) +#define BSP_PERIPHERAL_GPT_ODC_PRESENT (1) +#define BSP_PERIPHERAL_GPT_ODC_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_GPT_OPS_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_PRESENT (1) +#define BSP_PERIPHERAL_GPT_POEG_CHANNEL_MASK (0xFU) +#define BSP_PERIPHERAL_I3C_PRESENT (1) +#define BSP_PERIPHERAL_I3C_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_ICU_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_PRESENT (1) +#define BSP_PERIPHERAL_ICU_EXT_IRQ_CHANNEL_MASK (0xFFFFFFFFU) +#define BSP_PERIPHERAL_IIC_PRESENT (1) +#define BSP_PERIPHERAL_IIC_CHANNEL_MASK (0x7U) +#define BSP_PERIPHERAL_IIC_B_PRESENT (1) +#define BSP_PERIPHERAL_IIC_B_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_IIC0WU_PRESENT (1) +#define BSP_PERIPHERAL_IIC0WU_B_PRESENT (0) +#define BSP_PERIPHERAL_IICA_PRESENT (0) +#define BSP_PERIPHERAL_IICA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IIRFA_PRESENT (0) +#define BSP_PERIPHERAL_IIRFA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_IPC_PRESENT (1) +#define BSP_PERIPHERAL_IRDA_PRESENT (0) +#define BSP_PERIPHERAL_IRTC_PRESENT (0) +#define BSP_PERIPHERAL_IWDT_PRESENT (1) +#define BSP_PERIPHERAL_JPEG_PRESENT (0) +#define BSP_PERIPHERAL_KINT_PRESENT (0) +#define BSP_PERIPHERAL_KINT_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_MACL_PRESENT (0) +#define BSP_PERIPHERAL_MIPI_CSI_PRESENT (1) +#define BSP_PERIPHERAL_MIPI_DSI_PRESENT (1) +#define BSP_PERIPHERAL_MIPI_PHY_PRESENT (1) +#define BSP_PERIPHERAL_MMF_PRESENT (0) +#define BSP_PERIPHERAL_MPU_PRESENT (1) +#define BSP_PERIPHERAL_MPU_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_MRMS_PRESENT (1) +#define BSP_PERIPHERAL_MRRGE_PRESENT (1) +#define BSP_PERIPHERAL_MSTP_PRESENT (1) +#define BSP_PERIPHERAL_NPU_PRESENT (1) +#define BSP_PERIPHERAL_OCD_PRESENT (1) +#define BSP_PERIPHERAL_OPAMP_PRESENT (0) +#define BSP_PERIPHERAL_OPAMP_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_OSPI_PRESENT (0) +#define BSP_PERIPHERAL_OSPI_B_PRESENT (1) +#define BSP_PERIPHERAL_OSPI_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_PCLBUZ_PRESENT (0) +#define BSP_PERIPHERAL_PDC_PRESENT (0) +#define BSP_PERIPHERAL_PDM_PRESENT (1) +#define BSP_PERIPHERAL_PDM_CHANNEL_MASK (0x7U) +#define BSP_PERIPHERAL_PFS_PRESENT (1) +#define BSP_PERIPHERAL_PFS_B_PRESENT (0) +#define BSP_PERIPHERAL_PMISC_PRESENT (0) +#define BSP_PERIPHERAL_PORGA_PRESENT (0) +#define BSP_PERIPHERAL_PORT_PRESENT (1) +#define BSP_PERIPHERAL_PORT_CHANNEL_MASK (0x3FFFU) +#define BSP_PERIPHERAL_PSCU_PRESENT (1) +#define BSP_PERIPHERAL_PTPEDMAC_PRESENT (0) +#define BSP_PERIPHERAL_QSPI_PRESENT (0) +#define BSP_PERIPHERAL_RADIO_PRESENT (0) +#define BSP_PERIPHERAL_RSIP_PRESENT (1) +#define BSP_PERIPHERAL_RTC_PRESENT (1) +#define BSP_PERIPHERAL_RTC_C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_PRESENT (0) +#define BSP_PERIPHERAL_SAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_I2C_PRESENT (0) +#define BSP_PERIPHERAL_SAU_I2C_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SAU_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SAU_UART_PRESENT (0) +#define BSP_PERIPHERAL_SAU_UART_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_PRESENT (0) +#define BSP_PERIPHERAL_SCI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SCI_B_PRESENT (1) +#define BSP_PERIPHERAL_SCI_B_CHANNEL_MASK (0x3FFU) +#define BSP_PERIPHERAL_SDADC_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDADC_B_PRESENT (0) +#define BSP_PERIPHERAL_SDADC_B_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SDHI_PRESENT (1) +#define BSP_PERIPHERAL_SDHI_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SLCDC_PRESENT (0) +#define BSP_PERIPHERAL_SPI_PRESENT (0) +#define BSP_PERIPHERAL_SPI_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_SPI_B_PRESENT (1) +#define BSP_PERIPHERAL_SPI_B_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SPMON_PRESENT (0) +#define BSP_PERIPHERAL_SRAM_PRESENT (1) +#define BSP_PERIPHERAL_SRC_PRESENT (0) +#define BSP_PERIPHERAL_SRCRAM_PRESENT (0) +#define BSP_PERIPHERAL_SSI_COMMON_PRESENT (0) +#define BSP_PERIPHERAL_SSIE_PRESENT (1) +#define BSP_PERIPHERAL_SSIE_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_SYSTEM_PRESENT (1) +#define BSP_PERIPHERAL_TAU_PRESENT (0) +#define BSP_PERIPHERAL_TAU_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TFU_PRESENT (0) +#define BSP_PERIPHERAL_TML_PRESENT (0) +#define BSP_PERIPHERAL_TML_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_TRNG_PRESENT (0) +#define BSP_PERIPHERAL_TSD_PRESENT (1) +#define BSP_PERIPHERAL_TSN_PRESENT (1) +#define BSP_PERIPHERAL_TZF_PRESENT (1) +#define BSP_PERIPHERAL_UARTA_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_UARTA_CK_PRESENT (0) +#define BSP_PERIPHERAL_UARTA_CK_CHANNEL_MASK (0x0U) +#define BSP_PERIPHERAL_ULPT_PRESENT (1) +#define BSP_PERIPHERAL_ULPT_CHANNEL_MASK (0x3U) +#define BSP_PERIPHERAL_USB_PRESENT (1) +#define BSP_PERIPHERAL_USB_CHANNEL_MASK (0x1U) +#define BSP_PERIPHERAL_USB_FS_PRESENT (1) +#define BSP_PERIPHERAL_USB_HS_PRESENT (1) +#define BSP_PERIPHERAL_USBCC_PRESENT (0) +#define BSP_PERIPHERAL_VIN_PRESENT (1) +#define BSP_PERIPHERAL_WDT_PRESENT (1) +#define BSP_PERIPHERAL_WDT_CHANNEL_MASK (0x3U) + +// *UNCRUSTIFY-ON* + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h new file mode 100644 index 0000000000..959e34888f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/r_adc_device_types.h @@ -0,0 +1,182 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8P1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8P1) */ + +#ifndef R_ADC_DEVICE_TYPES +#define R_ADC_DEVICE_TYPES + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define ADC_B_CHANNEL_MASK_EXT_OFFSET (32U) + +/* Define overrides required for this MCU. */ +#define BSP_OVERRIDE_ADC_CHANNEL_T + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** ADC Clock source selection */ +typedef enum e_adc_b_clock_source +{ + ADC_B_CLOCK_SOURCE_ADC = 0, ///< ADC Clock Source ADCCLK + ADC_B_CLOCK_SOURCE_GPT = 1, ///< ADC Clock Source GPT + ADC_B_CLOCK_SOURCE_PCLKA = 2 ///< ADC Clock Source PCLKA +} adc_b_clock_source_t; + +/** ADC channels */ +typedef enum e_adc_b_virtual_channel +{ + ADC_B_VIRTUAL_CHANNEL_0 = 0, ///< ADC B virtual channel 0 + ADC_B_VIRTUAL_CHANNEL_1 = 1, ///< ADC B virtual channel 1 + ADC_B_VIRTUAL_CHANNEL_2 = 2, ///< ADC B virtual channel 2 + ADC_B_VIRTUAL_CHANNEL_3 = 3, ///< ADC B virtual channel 3 + ADC_B_VIRTUAL_CHANNEL_4 = 4, ///< ADC B virtual channel 4 + ADC_B_VIRTUAL_CHANNEL_5 = 5, ///< ADC B virtual channel 5 + ADC_B_VIRTUAL_CHANNEL_6 = 6, ///< ADC B virtual channel 6 + ADC_B_VIRTUAL_CHANNEL_7 = 7, ///< ADC B virtual channel 7 + ADC_B_VIRTUAL_CHANNEL_8 = 8, ///< ADC B virtual channel 8 + ADC_B_VIRTUAL_CHANNEL_9 = 9, ///< ADC B virtual channel 9 + ADC_B_VIRTUAL_CHANNEL_10 = 10, ///< ADC B virtual channel 10 + ADC_B_VIRTUAL_CHANNEL_11 = 11, ///< ADC B virtual channel 11 + ADC_B_VIRTUAL_CHANNEL_12 = 12, ///< ADC B virtual channel 12 + ADC_B_VIRTUAL_CHANNEL_13 = 13, ///< ADC B virtual channel 13 + ADC_B_VIRTUAL_CHANNEL_14 = 14, ///< ADC B virtual channel 14 + ADC_B_VIRTUAL_CHANNEL_15 = 15, ///< ADC B virtual channel 15 + ADC_B_VIRTUAL_CHANNEL_16 = 16, ///< ADC B virtual channel 16 + ADC_B_VIRTUAL_CHANNEL_17 = 17, ///< ADC B virtual channel 17 + ADC_B_VIRTUAL_CHANNEL_18 = 18, ///< ADC B virtual channel 18 + ADC_B_VIRTUAL_CHANNEL_19 = 19, ///< ADC B virtual channel 19 + ADC_B_VIRTUAL_CHANNEL_20 = 20, ///< ADC B virtual channel 20 + ADC_B_VIRTUAL_CHANNEL_21 = 21, ///< ADC B virtual channel 21 + ADC_B_VIRTUAL_CHANNEL_22 = 22, ///< ADC B virtual channel 22 + ADC_B_VIRTUAL_CHANNEL_23 = 23, ///< ADC B virtual channel 23 + ADC_B_VIRTUAL_CHANNEL_24 = 24, ///< ADC B virtual channel 24 + ADC_B_VIRTUAL_CHANNEL_25 = 25, ///< ADC B virtual channel 25 + ADC_B_VIRTUAL_CHANNEL_26 = 26, ///< ADC B virtual channel 26 + ADC_B_VIRTUAL_CHANNEL_27 = 27, ///< ADC B virtual channel 27 + ADC_B_VIRTUAL_CHANNEL_28 = 28, ///< ADC B virtual channel 28 + ADC_B_VIRTUAL_CHANNEL_29 = 29, ///< ADC B virtual channel 29 + ADC_B_VIRTUAL_CHANNEL_30 = 30, ///< ADC B virtual channel 30 + ADC_B_VIRTUAL_CHANNEL_31 = 31, ///< ADC B virtual channel 31 + ADC_B_VIRTUAL_CHANNEL_32 = 32, ///< ADC B virtual channel 32 + ADC_B_VIRTUAL_CHANNEL_COUNT // Number of available ADC B virtual channels +} adc_b_virtual_channel_t; + +/** ADC channels */ +typedef enum e_adc_channel +{ + /* These channels map to physical pins */ + ADC_CHANNEL_0 = 0, ///< ADC channel 0 + ADC_CHANNEL_1 = 1, ///< ADC channel 1 + ADC_CHANNEL_2 = 2, ///< ADC channel 2 + ADC_CHANNEL_3 = 3, ///< ADC channel 3 + ADC_CHANNEL_4 = 4, ///< ADC channel 4 + ADC_CHANNEL_5 = 5, ///< ADC channel 5 + ADC_CHANNEL_6 = 6, ///< ADC channel 6 + ADC_CHANNEL_7 = 7, ///< ADC channel 7 + ADC_CHANNEL_8 = 8, ///< ADC channel 8 + ADC_CHANNEL_9 = 9, ///< ADC channel 9 + ADC_CHANNEL_10 = 10, ///< ADC channel 10 + ADC_CHANNEL_11 = 11, ///< ADC channel 11 + ADC_CHANNEL_12 = 12, ///< ADC channel 12 + ADC_CHANNEL_13 = 13, ///< ADC channel 13 + ADC_CHANNEL_14 = 14, ///< ADC channel 14 + ADC_CHANNEL_15 = 15, ///< ADC channel 15 + ADC_CHANNEL_16 = 16, ///< ADC channel 16 + ADC_CHANNEL_17 = 17, ///< ADC channel 17 + ADC_CHANNEL_18 = 18, ///< ADC channel 18 + ADC_CHANNEL_19 = 19, ///< ADC channel 19 + ADC_CHANNEL_20 = 20, ///< ADC channel 20 + ADC_CHANNEL_21 = 21, ///< ADC channel 21 + ADC_CHANNEL_22 = 22, ///< ADC channel 22 + + /* Extended Channels, See Implementation for details */ + /* Implementation specific extended channels */ + ADC_CHANNEL_SELF_DIAGNOSIS_ADC0 = 0x60, ///< Self-Diagnosis channel for ADC Unit 0 + ADC_CHANNEL_SELF_DIAGNOSIS_ADC1 = 0x61, ///< Self-Diagnosis channel for ADC Unit 1 + ADC_CHANNEL_TEMPERATURE = 0x64, ///< Temperature sensor output + ADC_CHANNEL_VOLT = 0x65, ///< Internal reference voltage + ADC_CHANNEL_VBATT = 0x66, ///< VBATT 1/3 voltage monitor + ADC_CHANNEL_DA0 = 0x68, ///< D/A converter channel 0 + ADC_CHANNEL_DA1 = 0x69, ///< D/A converter channel 1 + + ADC_CHANNEL_SELF_DIAGNOSIS_SH0 = 0x70, ///< Self-Diagnosis Sample-and-hold Circuit Unit 0 + ADC_CHANNEL_SELF_DIAGNOSIS_SH1 = 0x71, ///< Self-Diagnosis Sample-and-hold Circuit Unit 1 + ADC_CHANNEL_SELF_DIAGNOSIS_SH2 = 0x72, ///< Self-Diagnosis Sample-and-hold Circuit Unit 2 + ADC_CHANNEL_SELF_DIAGNOSIS_SH4 = 0x74, ///< Self-Diagnosis Sample-and-hold Circuit Unit 4 + ADC_CHANNEL_SELF_DIAGNOSIS_SH5 = 0x75, ///< Self-Diagnosis Sample-and-hold Circuit Unit 5 + ADC_CHANNEL_SELF_DIAGNOSIS_SH6 = 0x76, ///< Self-Diagnosis Sample-and-hold Circuit Unit 6 + + ADC_CHANNEL_LAST_EXTERNAL = ADC_CHANNEL_22, /// Highest physical channel + ADC_CHANNEL_FIRST_INTERNAL = ADC_CHANNEL_SELF_DIAGNOSIS_ADC0, /// First internal channel + ADC_CHANNEL_LAST_INTERNAL = ADC_CHANNEL_SELF_DIAGNOSIS_SH6, /// Last internal channel +} adc_channel_t; + +/** ADC channel mask */ +typedef enum e_adc_b_channel_mask +{ + ADC_B_CHANNEL_MASK_NONE = 0ULL, + ADC_B_CHANNEL_MASK_0 = (1ULL << 0), ///< Channel 0 + ADC_B_CHANNEL_MASK_1 = (1ULL << 1), ///< Channel 1 + ADC_B_CHANNEL_MASK_2 = (1ULL << 2), ///< Channel 2 + ADC_B_CHANNEL_MASK_3 = (1ULL << 3), ///< Channel 3 + ADC_B_CHANNEL_MASK_4 = (1ULL << 4), ///< Channel 4 + ADC_B_CHANNEL_MASK_5 = (1ULL << 5), ///< Channel 5 + ADC_B_CHANNEL_MASK_6 = (1ULL << 6), ///< Channel 6 + ADC_B_CHANNEL_MASK_7 = (1ULL << 7), ///< Channel 7 + ADC_B_CHANNEL_MASK_8 = (1ULL << 8), ///< Channel 8 + ADC_B_CHANNEL_MASK_9 = (1ULL << 9), ///< Channel 9 + ADC_B_CHANNEL_MASK_10 = (1ULL << 10), ///< Channel 10 + ADC_B_CHANNEL_MASK_11 = (1ULL << 11), ///< Channel 11 + ADC_B_CHANNEL_MASK_12 = (1ULL << 12), ///< Channel 12 + ADC_B_CHANNEL_MASK_13 = (1ULL << 13), ///< Channel 13 + ADC_B_CHANNEL_MASK_14 = (1ULL << 14), ///< Channel 14 + ADC_B_CHANNEL_MASK_15 = (1ULL << 15), ///< Channel 15 + ADC_B_CHANNEL_MASK_16 = (1ULL << 16), ///< Channel 16 + ADC_B_CHANNEL_MASK_17 = (1ULL << 17), ///< Channel 17 + ADC_B_CHANNEL_MASK_18 = (1ULL << 18), ///< Channel 18 + ADC_B_CHANNEL_MASK_19 = (1ULL << 19), ///< Channel 19 + ADC_B_CHANNEL_MASK_20 = (1ULL << 20), ///< Channel 20 + ADC_B_CHANNEL_MASK_21 = (1ULL << 21), ///< Channel 21 + ADC_B_CHANNEL_MASK_22 = (1ULL << 22), ///< Channel 22 + + ADC_B_CHANNEL_MASK_DIAGNOSIS_ADC0 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 0)), ///< Converter 0 Self-Diagnosis Channel + ADC_B_CHANNEL_MASK_DIAGNOSIS_ADC1 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 1)), ///< Converter 1 Self-Diagnosis Channel + ADC_B_CHANNEL_MASK_TEMPERATURE = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 4)), ///< Temperature sensor channel + ADC_B_CHANNEL_MASK_VOLT = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 5)), ///< Voltage Reference channel + ADC_B_CHANNEL_MASK_VBATT = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 6)), ///< VBATT 1/3 voltage monitor + ADC_B_CHANNEL_MASK_DAC0 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 8)), ///< DAC 1 Channel + ADC_B_CHANNEL_MASK_DAC1 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 9)), ///< DAC 2 Channel + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH0 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 16)), ///< Sample-and-hold 0 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH1 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 17)), ///< Sample-and-hold 1 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH2 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 18)), ///< Sample-and-hold 2 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH4 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 20)), ///< Sample-and-hold 3 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH5 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 21)), ///< Sample-and-hold 4 Self-Diagnosis + ADC_B_CHANNEL_MASK_DIAGNOSIS_SH6 = (1ULL << (ADC_B_CHANNEL_MASK_EXT_OFFSET + 22)), ///< Sample-and-hold 5 Self-Diagnosis +} adc_b_channel_mask_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h new file mode 100644 index 0000000000..76e9561b73 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/bsp/mcu/ra8p1/r_lpm_device_types.h @@ -0,0 +1,104 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RA8P1 + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RA8P1) */ + +#ifndef R_LPM_DEVICE_TYPES_H +#define R_LPM_DEVICE_TYPES_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_OVERRIDE_LPM_STANDBY_WAKE_SOURCE_T +#define BSP_OVERRIDE_LPM_SNOOZE_CANCEL_T + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Wake from deep sleep or standby mode sources, does not apply to sleep or deep standby modes */ +typedef enum e_lpm_standby_wake_source +{ + LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 + LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 + LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 + LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 + LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 + LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 + LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 + LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 + LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 + LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 + LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 + LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 + LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 + LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 + LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 + LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 + LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt + LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt + LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt + LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt + LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt + LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt + LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt + LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 Underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 Compare Match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 Compare Match B interrupt + LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt + LPM_STANDBY_WAKE_SOURCE_COMPHS0 = 0x800000000ULL, ///< Comparator-HS0 Interrupt + LPM_STANDBY_WAKE_SOURCE_SOSTD = 0x8000000000ULL, ///< SOSTD interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0U = 0x10000000000ULL, ///< ULPT0 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0A = 0x20000000000ULL, ///< ULPT0 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0B = 0x40000000000ULL, ///< ULPT0 Compare Match B Interrupt + LPM_STANDBY_WAKE_SOURCE_I3C0 = 0x80000000000ULL, ///< I3C0 address match interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1U = 0x100000000000ULL, ///< ULPT1 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1A = 0x200000000000ULL, ///< ULPT1 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1B = 0x400000000000ULL, ///< ULPT1 Compare Match B Interrupt + LPM_STANDBY_WAKE_SOURCE_PDM = 0x800000000000ULL, ///< PDM Sound Detection + LPM_STANDBY_WAKE_SOURCE_IRQ16 = 0x1000000000000ULL, ///< IRQ16 + LPM_STANDBY_WAKE_SOURCE_IRQ17 = 0x2000000000000ULL, ///< IRQ17 + LPM_STANDBY_WAKE_SOURCE_IRQ18 = 0x4000000000000ULL, ///< IRQ18 + LPM_STANDBY_WAKE_SOURCE_IRQ19 = 0x8000000000000ULL, ///< IRQ19 + LPM_STANDBY_WAKE_SOURCE_IRQ20 = 0x10000000000000ULL, ///< IRQ20 + LPM_STANDBY_WAKE_SOURCE_IRQ21 = 0x20000000000000ULL, ///< IRQ21 + LPM_STANDBY_WAKE_SOURCE_IRQ22 = 0x40000000000000ULL, ///< IRQ22 + LPM_STANDBY_WAKE_SOURCE_IRQ23 = 0x80000000000000ULL, ///< IRQ23 + LPM_STANDBY_WAKE_SOURCE_IRQ24 = 0x100000000000000ULL, ///< IRQ24 + LPM_STANDBY_WAKE_SOURCE_IRQ25 = 0x200000000000000ULL, ///< IRQ25 + LPM_STANDBY_WAKE_SOURCE_IRQ26 = 0x400000000000000ULL, ///< IRQ26 + LPM_STANDBY_WAKE_SOURCE_IRQ27 = 0x800000000000000ULL, ///< IRQ27 + LPM_STANDBY_WAKE_SOURCE_IRQ28 = 0x1000000000000000ULL, ///< IRQ28 + LPM_STANDBY_WAKE_SOURCE_IRQ29 = 0x2000000000000000ULL, ///< IRQ29 + LPM_STANDBY_WAKE_SOURCE_IRQ30 = 0x4000000000000000ULL, ///< IRQ30 + LPM_STANDBY_WAKE_SOURCE_IRQ31 = 0x8000000000000000ULL, ///< IRQ31 +} lpm_standby_wake_source_t; + +typedef uint64_t lpm_standby_wake_source_bits_t; + +/** Snooze cancel control */ +typedef enum e_lpm_snooze_cancel +{ + LPM_SNOOZE_CANCEL_SOURCE_NONE = 0, ///< No snooze cancel source +} lpm_snooze_cancel_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_acmphs/r_acmphs.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_acmphs/r_acmphs.c new file mode 100644 index 0000000000..f42da3a52c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_acmphs/r_acmphs.c @@ -0,0 +1,407 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_acmphs_cfg.h" +#include "r_acmphs.h" + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ACMPHS_OPEN (0x434d5048U) + +/* ACMPHS base register access macro. */ +#define ACMPHS_REG(channel) ((R_ACMPHS0_Type *) ((uint32_t) R_ACMPHS0 + \ + ((uint32_t) R_ACMPHS1 - (uint32_t) R_ACMPHS0) * \ + (channel))) + +#define ACMPHS_PRIV_MAX_STATUS_RETRIES (1024U) + +#define ACMPHS_PRIV_US_PER_S (1000000U) +#define ACMPHS_PRIV_FILTER_WAIT_CLOCKS (4U) +#define ACMPHS_PRIV_FILTER_DIVISOR_BASE (4U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void comp_hs_int_isr(void); +static void acmphs_hardware_initialize(acmphs_instance_ctrl_t * const p_instance_ctrl); + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* ACMPHS Implementation of comparator interface. */ +const comparator_api_t g_comparator_on_acmphs = +{ + .open = R_ACMPHS_Open, + .outputEnable = R_ACMPHS_OutputEnable, + .infoGet = R_ACMPHS_InfoGet, + .statusGet = R_ACMPHS_StatusGet, + .close = R_ACMPHS_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup ACMPHS + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the comparator and starts operation. Callbacks and pin output are not active until outputEnable() is + * called. @ref comparator_api_t::outputEnable() should be called after the output has stabilized. Implements + * @ref comparator_api_t::open(). + * + * Comparator inputs must be configured in the application code prior to calling this function. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An input pointer is NULL + * @retval FSP_ERR_INVALID_ARGUMENT An argument is invalid. Window mode (COMPARATOR_MODE_WINDOW) and filter of 1 + * (COMPARATOR_FILTER_1) are not supported in this implementation. + * @retval FSP_ERR_ALREADY_OPEN The control block is already open or the hardware lock is taken. + **********************************************************************************************************************/ +fsp_err_t R_ACMPHS_Open (comparator_ctrl_t * const p_ctrl, comparator_cfg_t const * const p_cfg) +{ + acmphs_instance_ctrl_t * p_instance_ctrl = (acmphs_instance_ctrl_t *) p_ctrl; + +#if ACMPHS_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + + /* COMPARATOR_FILTER_1 and COMPARATOR_MODE_WINDOW are not supported in this implementation. */ + FSP_ERROR_RETURN(COMPARATOR_FILTER_1 != p_cfg->filter, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(COMPARATOR_MODE_WINDOW != p_cfg->mode, FSP_ERR_INVALID_ARGUMENT); + + /* Callback should not be NULL when interrupt is configured */ + if (p_cfg->irq >= 0) + { + FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT); + FSP_ASSERT(NULL != p_cfg->p_callback); + } + + /* Verify the control block has not already been initialized. */ + FSP_ERROR_RETURN(ACMPHS_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Save the configuration */ + p_instance_ctrl->p_cfg = p_cfg; + + /* Initialize control block. */ + p_instance_ctrl->p_reg = ACMPHS_REG(p_instance_ctrl->p_cfg->channel); + + /* Configure interrupt priority. The interrupt is disabled until @ref comparator_api_t::outputEnable() is called. */ + if (p_instance_ctrl->p_cfg->irq >= 0) + { + R_BSP_IrqCfg(p_instance_ctrl->p_cfg->irq, p_instance_ctrl->p_cfg->ipl, p_instance_ctrl); + } + + /* Enable clocks to the ACMPHS hardware. */ + R_BSP_MODULE_START(FSP_IP_ACMPHS, p_cfg->channel); + + acmphs_hardware_initialize(p_instance_ctrl); + + /* Mark the control block as open */ + p_instance_ctrl->open = ACMPHS_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the minimum stabilization wait time in microseconds. Implements @ref comparator_api_t::infoGet(). + * + * @retval FSP_SUCCESS Information stored in p_info. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_ACMPHS_InfoGet (comparator_ctrl_t * const p_ctrl, comparator_info_t * const p_info) +{ + acmphs_instance_ctrl_t * p_instance_ctrl = (acmphs_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking */ +#if (1 == ACMPHS_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ACMPHS is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(ACMPHS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Get the base stabilization time. */ + uint32_t filter_stabilization_us = 0U; + comparator_filter_t filter = (comparator_filter_t) p_instance_ctrl->p_reg->CMPCTL_b.CDFS; + if (COMPARATOR_FILTER_OFF != filter) + { + uint32_t pclk_freq_hz = 0; + pclk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + + /* Add 4 filter clocks if the filter is enabled. */ + uint32_t divisor; + divisor = ACMPHS_PRIV_FILTER_DIVISOR_BASE << (uint32_t) filter; + filter_stabilization_us = (ACMPHS_PRIV_FILTER_WAIT_CLOCKS * ACMPHS_PRIV_US_PER_S * divisor) / pclk_freq_hz; + + /* Round up. */ + filter_stabilization_us += 1U; + } + + p_info->min_stabilization_wait_us = BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US + filter_stabilization_us; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables the comparator output, which can be polled using @ref comparator_api_t::statusGet(). Also enables pin output and + * interrupts as configured during @ref comparator_api_t::open(). Implements @ref comparator_api_t::outputEnable(). + * + * @retval FSP_SUCCESS Comparator output is enabled. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_ACMPHS_OutputEnable (comparator_ctrl_t * const p_ctrl) +{ + acmphs_instance_ctrl_t * p_instance_ctrl = (acmphs_instance_ctrl_t *) p_ctrl; + +#if (1 == ACMPHS_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ACMPHS is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ACMPHS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* NOTE: All write instructions to registers with bits for more than one channel must be + * in critical sections to ensure the driver is reentrant for different channels. */ + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Enable the ACMPHS output. */ + p_instance_ctrl->p_reg->CMPCTL_b.COE = 1U; + + /* Set the VCOUT output setting for this channel (enabled or disabled). */ + p_instance_ctrl->p_reg->CPIOC_b.CPOE = (uint8_t) (p_instance_ctrl->p_cfg->pin_output & 1); + + FSP_CRITICAL_SECTION_EXIT; + + /* Enable interrupts for this channel. */ + + if (p_instance_ctrl->p_cfg->irq >= 0) + { + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->irq); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the operating status of the comparator. Implements @ref comparator_api_t::statusGet(). + * + * @retval FSP_SUCCESS Operating status of the comparator is provided in p_status. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + * @retval FSP_ERR_TIMEOUT The debounce filter is off and 2 consecutive matching values were not read within + * 1024 attempts. + **********************************************************************************************************************/ +fsp_err_t R_ACMPHS_StatusGet (comparator_ctrl_t * const p_ctrl, comparator_status_t * const p_status) +{ + acmphs_instance_ctrl_t * p_instance_ctrl = (acmphs_instance_ctrl_t *) p_ctrl; + +#if (1 == ACMPHS_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ACMPHS is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(ACMPHS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Read the operating status of the comparator. */ + if (0U == p_instance_ctrl->p_reg->CMPCTL_b.COE) + { + p_status->state = COMPARATOR_STATE_OUTPUT_DISABLED; + } + else + { + uint8_t state = p_instance_ctrl->p_reg->CMPMON; + if (COMPARATOR_FILTER_OFF == (comparator_filter_t) p_instance_ctrl->p_reg->CMPCTL_b.CDFS) + { + /* Software debounce of 2 consecutive reads is required by the hardware manual if the hardware debounce filter is off. */ + /* See "Comparator Output Monitor Register (CMPMON)" description in the ACMPHS section of the relevant hardware manual. */ + uint8_t state2 = p_instance_ctrl->p_reg->CMPMON; + + r_acmphs_extended_cfg_t * p_extend = ((r_acmphs_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend); + uint32_t retries = p_extend->maximum_status_retries; + + while ((state2 != state) && (retries > 0U)) + { + state = state2; + state2 = p_instance_ctrl->p_reg->CMPMON; + retries--; + } + + FSP_ERROR_RETURN(0U != retries, FSP_ERR_TIMEOUT); + } + + if (1U == state) + { + p_status->state = COMPARATOR_STATE_OUTPUT_HIGH; + } + else + { + p_status->state = COMPARATOR_STATE_OUTPUT_LOW; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops the comparator. Implements @ref comparator_api_t::close(). + * + * @retval FSP_SUCCESS Instance control block closed successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_ACMPHS_Close (comparator_ctrl_t * p_ctrl) +{ + acmphs_instance_ctrl_t * p_instance_ctrl = (acmphs_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking*/ +#if (1 == ACMPHS_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ACMPHS is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ACMPHS_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Mark driver as closed */ + p_instance_ctrl->open = 0U; + + /* Disable interrupts. */ + if (p_instance_ctrl->p_cfg->irq >= 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->irq, NULL); + } + + /* Added this to a separate block to avoid redeclaration of + * critical section variable under module stop macro. */ + { + /* Stop the comparator and disable output to VCOUT. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + p_instance_ctrl->p_reg->CMPCTL = 0U; + p_instance_ctrl->p_reg->CPIOC_b.CPOE = 0U; + + FSP_CRITICAL_SECTION_EXIT; + } + + /* Enter the module-stop state. */ + R_BSP_MODULE_STOP(FSP_IP_ACMPHS, p_instance_ctrl->p_cfg->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup ACMPHS) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Performs hardware initialization of the ACMPLP. + * + * @param[in] p_instance_ctrl Instance control block. + **********************************************************************************************************************/ +static void acmphs_hardware_initialize (acmphs_instance_ctrl_t * const p_instance_ctrl) +{ + /* Set registers controlled by this driver to their default values. */ + p_instance_ctrl->p_reg->CMPCTL = 0U; + p_instance_ctrl->p_reg->CPIOC_b.CPOE = 0U; + p_instance_ctrl->p_reg->CMPSEL0 = 0U; + p_instance_ctrl->p_reg->CMPSEL1 = 0U; + + uint8_t cmpctl = 0; + + /* Configure the output polarity. */ + cmpctl = (uint8_t) p_instance_ctrl->p_cfg->invert; + + /* Configure the trigger edge. */ + cmpctl |= (uint8_t) (p_instance_ctrl->p_cfg->trigger << R_ACMPHS0_CMPCTL_CEG_Pos); + + /* Configure the hardware debounce filter. */ + cmpctl |= (uint8_t) (p_instance_ctrl->p_cfg->filter << R_ACMPHS0_CMPCTL_CDFS_Pos); + + /* Enable the comparator. */ + cmpctl |= 1 << R_ACMPHS0_CMPCTL_HCMPON_Pos; + + r_acmphs_extended_cfg_t * p_extend = ((r_acmphs_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend); + + /* Configure the internal reference voltage enable */ + + /* For ACMPHS modules 0 to 5, VREFEN exists only in ACMPHS0.CPIOC. When using the internal Vref in COMP0 to COMP5, + * set the VREFEN bit in ACMPHS0.CPIOC to 1. Bit [7] in ACMPHS1.CPIOC to ACMPHS5.CPIOC should be 0 regardless of + * whether or not the internal Vref is used + * See "Comparator Output Control Register (CPIOC)" description in the ACMPHS section of the relevant hardware manual. */ + if (BSP_FEATURE_ACMPHS_VREF == p_extend->reference_voltage) + { + R_MSTP->MSTPCRD_b.MSTPD28 = 0; + + /* Read back the register to ensure that the write has completed. + * See the read back Note of "Module Stop Control Register A (MSTPCRA)" in the LPM section of + * the relevant hardware manual. */ + FSP_REGISTER_READ(R_MSTP->MSTPCRD); + + /*Writes to VREFEN bit must be in critical sections to ensure the driver is reentrant for different channels.*/ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + R_ACMPHS0->CPIOC_b.VREFEN = 1; + + FSP_CRITICAL_SECTION_EXIT; + } + + /* Configure the input and reference voltage for comparator*/ + p_instance_ctrl->p_reg->CMPSEL0 = (uint8_t) p_extend->input_voltage; + p_instance_ctrl->p_reg->CMPSEL1 = (uint8_t) p_extend->reference_voltage; + + p_instance_ctrl->p_reg->CMPCTL = cmpctl; +} + +/*******************************************************************************************************************//** + * Comparator interrupt + **********************************************************************************************************************/ +void comp_hs_int_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + acmphs_instance_ctrl_t * p_ctrl = (acmphs_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the IRQ flag. */ + R_BSP_IrqStatusClear(irq); + + /* Call user callback if one was provided. */ + comparator_callback_args_t args; + args.channel = p_ctrl->p_cfg->channel; + args.p_context = p_ctrl->p_cfg->p_context; + p_ctrl->p_cfg->p_callback(&args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_acmplp/r_acmplp.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_acmplp/r_acmplp.c new file mode 100644 index 0000000000..fdf42adeb7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_acmplp/r_acmplp.c @@ -0,0 +1,538 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_acmplp_cfg.h" +#include "r_acmplp.h" + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ACMPLP_OPEN (0x434d504CU) + +/* Number of channels. */ +#define ACMPLP_CHANNELS (2U) + +/* Mask for clearing ACMPLP registers*/ +#define ACMPLP_COMPMDR_CH0_CLEAR (0xF1U) +#define ACMPLP_COMPFIR_CH0_CLEAR (0xF0U) +#define ACMPLP_COMPOCR_CH0_CLEAR (0xF9U) +#define ACMPLP_COMPMDR_CH1_CLEAR (0x1FU) +#define ACMPLP_COMPFIR_CH1_CLEAR (0x0FU) +#define ACMPLP_COMPOCR_CH1_CLEAR (0x9FU) +#define ACMPLP_COMPSEL_CH0_CLEAR (0xF0) +#define ACMPLP_COMPSEL_CH1_CLEAR (0x0F) + +/* Set Speed mode to high-speed*/ +#define ACMPLP_CPMPOCR_SPDMD_SET (0x80U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void acmplp_hardware_initialize(acmplp_instance_ctrl_t * const p_instance_ctrl); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void comp_lp_int_isr(void); + +/* Maps valid enums to register values. */ +static const uint8_t acmplp_filter_map[] = +{ + [COMPARATOR_FILTER_OFF] = 0U, + [COMPARATOR_FILTER_1] = 1U, + [COMPARATOR_FILTER_8] = 2U, + [COMPARATOR_FILTER_32] = 3U, +}; + +/* Used to keep track of opened channels. */ +static acmplp_instance_ctrl_t * gp_acmplp_ctrl[ACMPLP_CHANNELS]; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* ACMPLP Implementation of comparator interface. */ +const comparator_api_t g_comparator_on_acmplp = +{ + .open = R_ACMPLP_Open, + .outputEnable = R_ACMPLP_OutputEnable, + .infoGet = R_ACMPLP_InfoGet, + .statusGet = R_ACMPLP_StatusGet, + .close = R_ACMPLP_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup ACMPLP + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the comparator and starts operation. Callbacks and pin output are not active until outputEnable() is + * called. @ref comparator_api_t::outputEnable() should be called after the output has stabilized. Implements + * @ref comparator_api_t::open(). + * + * Comparator inputs must be configured in the application code prior to calling this function. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An input pointer is NULL + * @retval FSP_ERR_INVALID_ARGUMENT An argument is invalid. Window mode (COMPARATOR_MODE_WINDOW) and filter of 1 + * (COMPARATOR_FILTER_1) are not supported in this implementation. + * p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to + * use callback function. + * @retval FSP_ERR_ALREADY_OPEN The control block is already open or the hardware lock is taken. + * @retval FSP_ERR_IN_USE The channel is already in use. + **********************************************************************************************************************/ +fsp_err_t R_ACMPLP_Open (comparator_ctrl_t * const p_ctrl, comparator_cfg_t const * const p_cfg) +{ + acmplp_instance_ctrl_t * p_instance_ctrl = (acmplp_instance_ctrl_t *) p_ctrl; + +#if ACMPLP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_instance_ctrl); + + /* Verify the control block has not already been initialized. */ + FSP_ERROR_RETURN(ACMPLP_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(NULL == gp_acmplp_ctrl[p_cfg->channel], FSP_ERR_IN_USE); + + /* COMPARATOR_FILTER_16 is not supported for this implementation. */ + FSP_ERROR_RETURN(COMPARATOR_FILTER_16 != p_cfg->filter, FSP_ERR_INVALID_ARGUMENT); + + /* Callback should not be NULL when interrupt is configured */ + if (p_cfg->irq >= 0) + { + FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT); + FSP_ASSERT(NULL != p_cfg->p_callback); + } + + #if ACMPLP_CFG_CH1_IVREF0_ENABLE + + /* If ACMPLP1 uses IVREF0 as a reference input, ACMPLP0 and ACMPLP1 must use the same reference input settings. */ + uint32_t alt_channel = (p_cfg->channel + 1U) % ACMPLP_CHANNELS; + if (NULL != gp_acmplp_ctrl[alt_channel]) + { + r_acmplp_extended_cfg_t const * p_extended_cfg = (r_acmplp_extended_cfg_t const *) p_cfg->p_extend; + r_acmplp_extended_cfg_t const * p_extended_cfg_alt = + (r_acmplp_extended_cfg_t const *) gp_acmplp_ctrl[alt_channel]->p_cfg->p_extend; + FSP_ERROR_RETURN(p_extended_cfg_alt->reference_voltage == p_extended_cfg->reference_voltage, + FSP_ERR_INVALID_ARGUMENT); + } + #endif +#endif + + /* Save ctrl instance. */ + gp_acmplp_ctrl[p_cfg->channel] = p_instance_ctrl; + + /* Save the configuration */ + p_instance_ctrl->p_cfg = p_cfg; + + /* Disable Output at initialization */ + p_instance_ctrl->output_enabled = 0U; + + /* Configure interrupt priority. The interrupt is disabled until @ref comparator_api_t::outputEnable() is called. */ + if (p_instance_ctrl->p_cfg->irq >= 0) + { + R_BSP_IrqCfg(p_instance_ctrl->p_cfg->irq, p_cfg->ipl, p_instance_ctrl); + } + + /* Power on ACMPLP before setting any hardware registers.*/ + R_BSP_MODULE_START(FSP_IP_ACMPLP, p_cfg->channel); + + /* ACMPLP register settings described in table "Procedure for setting the ACMPLP associated registers + * (i = 0, 1)" section of the relevant hardware manual are done here with the exception of enabling interrupts and VCOUT. + * Interrupts and VCOUT are enabled as configured in R_ACMPLP_OutputEnable() because they should only be enabled + * after the stabilization wait time has elapsed.*/ + acmplp_hardware_initialize(p_instance_ctrl); + + /* Mark the control block as open */ + p_instance_ctrl->open = ACMPLP_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the minimum stabilization wait time in microseconds. Implements @ref comparator_api_t::infoGet(). + * + * @retval FSP_SUCCESS Information stored in p_info. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_ACMPLP_InfoGet (comparator_ctrl_t * const p_ctrl, comparator_info_t * const p_info) +{ + acmplp_instance_ctrl_t * p_instance_ctrl = (acmplp_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking */ +#if (1 == ACMPLP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ACMPLP is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(ACMPLP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* This comes from the Operation section in the hardware manual. */ + p_info->min_stabilization_wait_us = BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables the comparator output, which can be polled using @ref comparator_api_t::statusGet(). Also enables pin output and + * interrupts as configured during @ref comparator_api_t::open(). Implements @ref comparator_api_t::outputEnable(). + * + * @retval FSP_SUCCESS Comparator output is enabled. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_ACMPLP_OutputEnable (comparator_ctrl_t * const p_ctrl) +{ + acmplp_instance_ctrl_t * p_instance_ctrl = (acmplp_instance_ctrl_t *) p_ctrl; + +#if (1 == ACMPLP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ACMPLP is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ACMPLP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* NOTE: All write instructions to registers with bits for more than one channel must be + * in critical sections to ensure the driver is reentrant for different channels. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Set the VCOUT output setting for this channel (enabled or disabled). */ + if (0U == p_instance_ctrl->p_cfg->channel) + { + R_ACMPLP->COMPOCR_b.C0OE = (uint8_t) p_instance_ctrl->p_cfg->pin_output & 1U; + } + else + { + R_ACMPLP->COMPOCR_b.C1OE = (uint8_t) p_instance_ctrl->p_cfg->pin_output & 1U; + } + + FSP_CRITICAL_SECTION_EXIT; + + /* Enable interrupts for this channel. */ + if (p_instance_ctrl->p_cfg->irq >= 0) + { + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->irq); + } + + p_instance_ctrl->output_enabled = 1U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the operating status of the comparator. Implements @ref comparator_api_t::statusGet(). + * + * @retval FSP_SUCCESS Operating status of the comparator is provided in p_status. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_ACMPLP_StatusGet (comparator_ctrl_t * const p_ctrl, comparator_status_t * const p_status) +{ + acmplp_instance_ctrl_t * p_instance_ctrl = (acmplp_instance_ctrl_t *) p_ctrl; + +#if (1 == ACMPLP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ACMPLP is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(ACMPLP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint8_t state = 0; + + if (0U == p_instance_ctrl->output_enabled) + { + p_status->state = COMPARATOR_STATE_OUTPUT_DISABLED; + } + else + { + /* Read the operating status of the comparator. */ + if (0U == p_instance_ctrl->p_cfg->channel) + { + state = R_ACMPLP->COMPMDR_b.C0MON; + } + else + { + state = R_ACMPLP->COMPMDR_b.C1MON; + } + + /* Check for Output Polarity Selection */ + if (COMPARATOR_POLARITY_INVERT_ON == p_instance_ctrl->p_cfg->invert) + { + state = !state; + } + + p_status->state = (comparator_state_t) state; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops the comparator. Implements @ref comparator_api_t::close(). + * + * @retval FSP_SUCCESS Instance control block closed successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_ACMPLP_Close (comparator_ctrl_t * p_ctrl) +{ + acmplp_instance_ctrl_t * p_instance_ctrl = (acmplp_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking*/ +#if (1 == ACMPLP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ACMPLP is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ACMPLP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + { + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Stop the comparator and disable output to VCOUT. */ + if (0U == p_instance_ctrl->p_cfg->channel) + { + /* Clear the Operation enable and output enable for channel 0. */ + R_ACMPLP->COMPMDR_b.C0ENB = 0U; + R_ACMPLP->COMPOCR_b.C0OE = 0U; + } + else + { + /* Clear the Operation enable and output enable for channel 1. */ + R_ACMPLP->COMPMDR_b.C1ENB = 0U; + R_ACMPLP->COMPOCR_b.C1OE = 0U; + } + + FSP_CRITICAL_SECTION_EXIT; + } + + /* Disable interrupt. */ + if (p_instance_ctrl->p_cfg->irq >= 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->irq, NULL); + } + + /* Check if the other channel is in use. */ + acmplp_instance_ctrl_t * alt_channel = gp_acmplp_ctrl[!p_instance_ctrl->p_cfg->channel]; + if (NULL == alt_channel) + { + /* No other channels open. */ + R_BSP_MODULE_STOP(FSP_IP_ACMPLP, 0); + } + + /* Mark driver as closed */ + p_instance_ctrl->open = 0U; + gp_acmplp_ctrl[p_instance_ctrl->p_cfg->channel] = NULL; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup ACMPLP) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Performs hardware initialization of the ACMPLP. + * + * @param[in] p_instance_ctrl Instance control block. + **********************************************************************************************************************/ +static void acmplp_hardware_initialize (acmplp_instance_ctrl_t * const p_instance_ctrl) +{ + uint8_t temp_reg = 0; + + /* Configure the trigger edge and the hardware debounce filter + * Set CiEPO and CiEDG at the same time since they are controlled by the same enum. + * The register value to write is one less than the value in the interface. */ + uint8_t compfir = (uint8_t) ((p_instance_ctrl->p_cfg->trigger - 1) << 2); + compfir |= acmplp_filter_map[p_instance_ctrl->p_cfg->filter]; + + /* Configure Window function mode */ + uint8_t compmdr = (uint8_t) ((p_instance_ctrl->p_cfg->mode) << 1); + + /* Configure Reference Voltage Selection */ + compmdr |= (uint8_t) ((p_instance_ctrl->p_cfg->vref_select) << R_ACMPLP_COMPMDR_C0VRF_Pos); + + /* Configure the output polarity. */ + uint8_t compocr = (uint8_t) p_instance_ctrl->p_cfg->invert; + +#if BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS + r_acmplp_extended_cfg_t * p_extend = ((r_acmplp_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend); + uint8_t compsel1 = 0; +#endif + + /* NOTE: All read-modify-write instructions to registers with bits for more than one channel must be + * in critical sections to ensure the driver is reentrant for different channels. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if (0U == p_instance_ctrl->p_cfg->channel) + { +#if BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS + + /* Configure the input voltage to the comparator */ + R_ACMPLP->COMPSEL0 &= ACMPLP_COMPSEL_CH0_CLEAR; + R_ACMPLP->COMPSEL0 |= (uint8_t) p_extend->input_voltage; + + /* Clear the COMPSEL1 to update the CiWDE bit + * See note 5 & 6 in section "ACMPLP Mode Setting Register (COMPMDR)" description of the relevant hardware manual.*/ + compsel1 = R_ACMPLP->COMPSEL1; + compsel1 &= ACMPLP_COMPSEL_CH0_CLEAR; + R_ACMPLP->COMPSEL1 = compsel1; +#endif + + /* Configure the filter select (CnFCK), edge polarity (CnEPO) and egde detection (CnEDG) */ + temp_reg = R_ACMPLP->COMPFIR; + temp_reg &= ACMPLP_COMPFIR_CH0_CLEAR; + temp_reg |= compfir; + R_ACMPLP->COMPFIR = temp_reg; + + /* Configure the Output polarity and set comparator to high-speed mode*/ + temp_reg = R_ACMPLP->COMPOCR; + temp_reg &= ACMPLP_COMPOCR_CH0_CLEAR; + temp_reg |= (uint8_t) (compocr << R_ACMPLP_COMPOCR_C0OP_Pos); + R_ACMPLP->COMPOCR = temp_reg | ACMPLP_CPMPOCR_SPDMD_SET; + + /* Configure Window mode and enable comparator */ + temp_reg = R_ACMPLP->COMPMDR; + temp_reg &= ACMPLP_COMPMDR_CH0_CLEAR; + temp_reg |= compmdr; + R_ACMPLP->COMPMDR = temp_reg; + +#if BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS + compsel1 |= (p_extend->reference_voltage); + R_ACMPLP->COMPSEL1 = compsel1; +#endif + + /* Enable the comparator. */ + R_ACMPLP->COMPMDR |= 1; + } + else + { +#if BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS + + /* Configure the input voltage to the comparator */ + R_ACMPLP->COMPSEL0 &= ACMPLP_COMPSEL_CH1_CLEAR; + R_ACMPLP->COMPSEL0 |= (uint8_t) (p_extend->input_voltage << R_ACMPLP_COMPSEL0_IVCMP1_Pos); + + compsel1 = R_ACMPLP->COMPSEL1; + compsel1 &= ACMPLP_COMPSEL_CH1_CLEAR; + + if ((ACMPLP_CFG_CH1_IVREF0_ENABLE == R_ACMPLP->COMPSEL1_b.C1VRF2) && + (p_instance_ctrl->p_cfg->mode == R_ACMPLP->COMPMDR_b.C1WDE) && + (p_instance_ctrl->p_cfg->vref_select == R_ACMPLP->COMPMDR_b.C1VRF)) + { + /* If C1VRF2 and C1WDE already has desired value then do not clear COMPSEL1 */ + R_ACMPLP->COMPSEL1 = compsel1; + } + else + { + /* To change C1WDE and C1VRF, the CRV[6:4] and CRV[2:0] bits must be 000b. + * See note 5 & 6 in section "ACMPLP Mode Setting Register (COMPMDR)" of the relevant hardware manual.*/ + + /* To change C1VRF2, bits CRVS[6:4] and CRVS[2:0] must be 000b + * See note 3 in "Comparator Reference Voltage Select Register (COMPSEL1)" in the ACMPLP section of the relevant hardware manual. */ + R_ACMPLP->COMPSEL1 = 0; + } +#endif + + /* Configure the filter select (CnFCK), edge polarity (CnEPO) and egde detection (CnEDG) */ + temp_reg = R_ACMPLP->COMPFIR; + temp_reg &= ACMPLP_COMPFIR_CH1_CLEAR; + temp_reg |= (uint8_t) (compfir << R_ACMPLP_COMPFIR_C1FCK_Pos); + R_ACMPLP->COMPFIR = temp_reg; + + /* Configure the Output polarity and set comparator to high-speed mode*/ + temp_reg = R_ACMPLP->COMPOCR; + temp_reg &= ACMPLP_COMPOCR_CH1_CLEAR; + temp_reg |= (uint8_t) (compocr << R_ACMPLP_COMPOCR_C1OP_Pos); + R_ACMPLP->COMPOCR = temp_reg | ACMPLP_CPMPOCR_SPDMD_SET; + + /* Configure Window mode and enable comparator */ + temp_reg = R_ACMPLP->COMPMDR; + temp_reg &= ACMPLP_COMPMDR_CH1_CLEAR; + temp_reg |= (uint8_t) (compmdr << R_ACMPLP_COMPMDR_C1ENB_Pos); + R_ACMPLP->COMPMDR = temp_reg; + +#if BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS + + /* Read the current state of COMPSEL1. */ + temp_reg = R_ACMPLP->COMPSEL1; + #if (ACMPLP_CFG_CH1_IVREF0_ENABLE) + + /* If channel 0 is not open, then set the voltage reference for channel 0. */ + if (NULL == gp_acmplp_ctrl[0]) + { + temp_reg &= (uint8_t) (~R_ACMPLP_COMPSEL1_IVREF0_Msk); + temp_reg |= (uint8_t) (p_extend->reference_voltage); // IVREF0 + } + + #else + + /* Configure the reference voltage to the comparator and Reference Voltage Selection 2 for channel 1 */ + temp_reg |= (uint8_t) 1 << R_ACMPLP_COMPSEL1_C1VRF2_Pos; + temp_reg &= (uint8_t) (~R_ACMPLP_COMPSEL1_IVREF1_Msk); + temp_reg |= (uint8_t) (p_extend->reference_voltage << R_ACMPLP_COMPSEL1_IVREF1_Pos); // IVREF1 + #endif + + /* Write settings to COMPSEL1. */ + R_ACMPLP->COMPSEL1 = temp_reg; +#endif + + /* Enable the comparator. */ + R_ACMPLP->COMPMDR |= (1 << R_ACMPLP_COMPMDR_C1ENB_Pos); + } + + FSP_CRITICAL_SECTION_EXIT; +} + +/*******************************************************************************************************************//** + * Comparator interrupt + **********************************************************************************************************************/ +void comp_lp_int_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + acmplp_instance_ctrl_t * p_instance_ctrl = (acmplp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + /* Call user callback if one was provided. */ + comparator_callback_args_t args; + args.channel = p_instance_ctrl->p_cfg->channel; + args.p_context = p_instance_ctrl->p_cfg->p_context; + p_instance_ctrl->p_cfg->p_callback(&args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_adc/r_adc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_adc/r_adc.c new file mode 100644 index 0000000000..17c4053fbe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_adc/r_adc.c @@ -0,0 +1,1786 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_api.h" + +/* Configuration for this package. */ +#include "r_adc_cfg.h" + +/* Private header file for this package. */ +#include "r_adc.h" + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define ADC_PRV_USEC_PER_SEC (1000000U) +#define ADC_PRV_MIN_ADCLK_HZ (1000000U) +#define ADC_MAX_CALIBRATION_CLOCKS_MILLISECS (780U) + +#define ADC_PRV_HZ_PER_KHZ (1000U) + +#define ADC_SHIFT_LEFT_ALIGNED_32_BIT (16U) + +#define ADC_OPEN (0x52414443U) + +#define ADC_ADADC_AVEE_BIT (0x80U) + +/* Sample and hold bypass applies to these channels. */ +#define ADC_MASK_SAMPLE_HOLD_BYPASS_CHANNELS (0x7U) + +/* Sample and hold bypass starts at bit 8. */ +#define ADC_MASK_SAMPLE_HOLD_BYPASS_SHIFT (8U) + +/* Value for ADPGADCR0 to disable PGA */ +#define ADC_ADPGADCR0_DISABLE_PGA (0x0000) + +/* Value for ADPGACR to disable PGA */ +#define ADC_ADPGACR_DISABLE_PGA (0x9999) + +/* Position of ADCALEXE to start calibration-CALEXE bit */ +#define ADC_ADCALEXE_SET_CALEXE (0x80U) + +/* Position of ADCALEXE calibration-CALMON bit */ +#define ADC_ADCALEXE_CALIBRATION_STATUS (0x40U) + +/* Value of ADICR with interrupt at end of calibration */ +#define ADC_ADICR_CALIBRATION_INTERRUPT_ENABLED (0x03U) + +/* Value of ADICR with no interrupt at end of calibration */ +#define ADC_ADICR_CALIBRATION_INTERRUPT_DISABLED (0x00U) + +/* Stabilization time when BGR is enabled */ +#define ADC_BGR_STABILIZATION_DELAY_US (150U) + +/* Bit set in adc_vref_control if the internal voltage reference is used for VREFH. */ +#define ADC_PRV_ADHVREFCNT_VREF_INTERNAL_BIT_1 (1U << 1) + +#define ADC_PRV_ADCSR_ADST_TRGE_MASK (R_ADC0_ADCSR_ADST_Msk | R_ADC0_ADCSR_TRGE_Msk) +#define ADC_PRV_ADCSR_CLEAR_ADST_TRGE (~ADC_PRV_ADCSR_ADST_TRGE_MASK) + +#define ADC_PRV_TSCR_TSN_ENABLE (R_TSN_CTRL_TSCR_TSEN_Msk | R_TSN_CTRL_TSCR_TSOE_Msk) + +#define ADC_PRV_ADBUF_ENABLED (1U) + +#define ADC_MASK_FIRST_SENSOR_BIT (29U) + +#if 1U == BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE + #define R_TSN (R_TSN_CAL) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * adc_prv_ns_callback)(adc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile adc_prv_ns_callback)(adc_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if ADC_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_adc_open_cfg_check(adc_cfg_t const * const p_cfg); +static fsp_err_t r_adc_open_cfg_resolution_check(adc_cfg_t const * const p_cfg); +static fsp_err_t r_adc_sample_state_cfg_check(adc_instance_ctrl_t * p_instance_ctrl, adc_sample_state_t * p_sample); + +static fsp_err_t r_adc_scan_cfg_check_sample_hold(adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg); + +static fsp_err_t r_adc_scan_cfg_check_sensors(adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg); + +#endif + +static void r_adc_open_sub(adc_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg); + +static void r_adc_sensor_cfg(adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg); + +#if ADC_CFG_PARAM_CHECKING_ENABLE + +static fsp_err_t r_adc_scan_cfg_check(adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg); + +#endif + +static void r_adc_scan_cfg(adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg); +static void r_adc_sensor_sample_state_calculation(uint32_t * const p_sample_states); +void adc_scan_end_b_isr(void); +void adc_scan_end_isr(void); +void adc_window_compare_isr(void); +static void r_adc_irq_enable(IRQn_Type irq, uint8_t ipl, void * p_context); +static void r_adc_irq_disable(IRQn_Type irq); +static uint32_t r_adc_lowest_channel_get(uint32_t adc_mask); +static void r_adc_scan_end_common_isr(adc_event_t event); + +#if ADC_CFG_PARAM_CHECKING_ENABLE + +/** Mask of valid channels on this MCU. */ +static const uint32_t g_adc_valid_channels[] = +{ + BSP_FEATURE_ADC_UNIT_0_CHANNELS_MASK, + #if BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK + BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK + #endif +}; +#endif + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** ADC Implementation of ADC. */ +const adc_api_t g_adc_on_adc = +{ + .open = R_ADC_Open, + .scanCfg = R_ADC_ScanCfg, + .infoGet = R_ADC_InfoGet, + .scanStart = R_ADC_ScanStart, + .scanGroupStart = R_ADC_ScanGroupStart, + .scanStop = R_ADC_ScanStop, + .scanStatusGet = R_ADC_StatusGet, + .read = R_ADC_Read, + .read32 = R_ADC_Read32, + .close = R_ADC_Close, + .calibrate = R_ADC_Calibrate, + .offsetSet = R_ADC_OffsetSet, + .callbackSet = R_ADC_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup ADC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Sets the operational mode, trigger sources, interrupt priority, and configurations for the peripheral as a whole. + * If interrupt is enabled, the function registers a callback function pointer for notifying the user whenever a scan + * has completed. + * + * @retval FSP_SUCCESS Module is ready for use. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_ALREADY_OPEN The instance control structure has already been opened. + * @retval FSP_ERR_IRQ_BSP_DISABLED A callback is provided, but the interrupt is not enabled. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested unit does not exist on this MCU. + * @retval FSP_ERR_INVALID_HW_CONDITION The ADC clock must be at least 1 MHz + **********************************************************************************************************************/ +fsp_err_t R_ADC_Open (adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg) +{ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking */ +#if ADC_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(NULL != p_instance_ctrl); + + /* Verify the configuration parameters are valid */ + fsp_err_t err = r_adc_open_cfg_check(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check for valid argument values for options that are unique to the IP */ + err = r_adc_open_cfg_resolution_check(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify this unit has not already been initialized */ + FSP_ERROR_RETURN(ADC_OPEN != p_instance_ctrl->opened, FSP_ERR_ALREADY_OPEN); + + /* If a callback is used, then make sure an interrupt is enabled */ + adc_extended_cfg_t const * p_extend = (adc_extended_cfg_t const *) p_cfg->p_extend; + if (NULL != p_cfg->p_callback) + { + FSP_ERROR_RETURN((p_cfg->scan_end_irq >= 0) || (p_extend->window_a_irq >= 0) || (p_extend->window_b_irq >= 0), + FSP_ERR_IRQ_BSP_DISABLED); + + /* Group B interrupts are never required since group B can be configured in continuous scan mode when group A + * has priority over group B. */ + } + +#else + adc_extended_cfg_t const * p_extend = (adc_extended_cfg_t const *) p_cfg->p_extend; +#endif + + /* Save configurations. */ + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + /* Calculate the register base address. */ + uint32_t address_gap = (uint32_t) R_ADC1 - (uint32_t) R_ADC0; + p_instance_ctrl->p_reg = (R_ADC0_Type *) ((uint32_t) R_ADC0 + (address_gap * p_cfg->unit)); + + /* Initialize the hardware based on the configuration. */ + r_adc_open_sub(p_instance_ctrl, p_cfg); + + /* Enable interrupts */ + r_adc_irq_enable(p_cfg->scan_end_irq, p_cfg->scan_end_ipl, p_instance_ctrl); + r_adc_irq_enable(p_cfg->scan_end_b_irq, p_cfg->scan_end_b_ipl, p_instance_ctrl); + r_adc_irq_enable(p_extend->window_a_irq, p_extend->window_a_ipl, p_instance_ctrl); + r_adc_irq_enable(p_extend->window_b_irq, p_extend->window_b_ipl, p_instance_ctrl); + + /* Invalid scan mask (initialized for later). */ + p_instance_ctrl->scan_mask = 0U; + + /* Mark driver as opened by initializing it to "RADC" in its ASCII equivalent for this unit. */ + p_instance_ctrl->opened = ADC_OPEN; + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the ADC scan parameters. Channel specific settings are set in this function. Pass a pointer to + * @ref adc_channel_cfg_t to p_channel_cfg. + * + * @note This starts group B scans if adc_channel_cfg_t::priority_group_a is set to ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN. + * + * @retval FSP_SUCCESS Channel specific settings applied. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_ScanCfg (adc_ctrl_t * p_ctrl, void const * const p_channel_cfg) +{ + adc_channel_cfg_t const * p_adc_channel_cfg = (adc_channel_cfg_t const *) p_channel_cfg; + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if ADC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_adc_channel_cfg); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + + err = r_adc_scan_cfg_check(p_instance_ctrl, p_adc_channel_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Configure the hardware based on the configuration */ + r_adc_scan_cfg(p_instance_ctrl, p_adc_channel_cfg); + + /* Save the scan mask locally; this is required for the infoGet function. */ + p_instance_ctrl->scan_mask = p_adc_channel_cfg->scan_mask; + + /* Return the error code */ + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements adc_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_ADC_CallbackSet (adc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(adc_callback_args_t *), + void * const p_context, + adc_callback_args_t * const p_callback_memory) +{ + adc_instance_ctrl_t * p_ctrl = (adc_instance_ctrl_t *) p_api_ctrl; + +#if (ADC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(ADC_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if ADC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + adc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif + + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(adc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts a software scan or enables the hardware trigger for a scan depending on how the triggers were configured in + * the R_ADC_Open call. If the unit was configured for ELC or external hardware triggering, then this function allows + * the trigger signal to get to the ADC unit. The function is not able to control the generation of the trigger itself. + * If the unit was configured for software triggering, then this function starts the software triggered scan. + * + * @pre Call R_ADC_ScanCfg after R_ADC_Open before starting a scan. + * + * @pre On MCUs that support calibration, call R_ADC_Calibrate and wait for calibration to complete before starting + * a scan. + * + * @retval FSP_SUCCESS Scan started (software trigger) or hardware triggers enabled. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized. + * @retval FSP_ERR_IN_USE Another scan is still in progress (software trigger). + **********************************************************************************************************************/ +fsp_err_t R_ADC_ScanStart (adc_ctrl_t * p_ctrl) +{ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking */ +#if ADC_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); + if (ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN != p_instance_ctrl->p_reg->ADGSPCR) + { + FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->ADCSR_b.ADST, FSP_ERR_IN_USE); + } +#endif + + /* Enable hardware trigger or start software scan depending on mode. */ + p_instance_ctrl->p_reg->ADCSR = p_instance_ctrl->scan_start_adcsr; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::scanStart is not supported on the ADCH. Use scanStart instead. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_ADC_ScanGroupStart (adc_ctrl_t * p_ctrl, adc_group_mask_t group_id) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(group_id); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Stops the software scan or disables the unit from being triggered by the hardware trigger (ELC or external) based on + * what type of trigger the unit was configured for in the R_ADC_Open function. Stopping a hardware triggered scan via + * this function does not abort an ongoing scan, but prevents the next scan from occurring. Stopping a software + * triggered scan aborts an ongoing scan. + * + * @retval FSP_SUCCESS Scan stopped (software trigger) or hardware triggers disabled. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_ScanStop (adc_ctrl_t * p_ctrl) +{ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking */ +#if ADC_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); +#endif + + /* Disable hardware trigger or stop software scan depending on mode. */ + p_instance_ctrl->p_reg->ADCSR = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the status of any scan process that was started, including scans started by ELC or external triggers and + * calibration scans on MCUs that support calibration. + * + * @retval FSP_SUCCESS Module status stored in the provided pointer p_status + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_StatusGet (adc_ctrl_t * p_ctrl, adc_status_t * p_status) +{ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + +#if ADC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Read the status of the ADST bit. ADST is set when a scan is in progress, including calibration scans. */ + p_status->state = (adc_state_t) p_instance_ctrl->p_reg->ADCSR_b.ADST; + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads conversion results from a single channel or sensor. + * + * @retval FSP_SUCCESS Data read into provided p_data. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_Read (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data) +{ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking. */ +#if ADC_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); + + /* Verify that the channel is valid for this MCU */ + if ((reg_id >= ADC_CHANNEL_0) && ((uint32_t) reg_id <= 31U)) + { + uint32_t requested_channel_mask = (1U << (uint32_t) reg_id); + FSP_ASSERT(0 != (requested_channel_mask & g_adc_valid_channels[p_instance_ctrl->p_cfg->unit])); + } + else + { + FSP_ASSERT((reg_id == ADC_CHANNEL_TEMPERATURE) || (reg_id == ADC_CHANNEL_VOLT) || + (reg_id == ADC_CHANNEL_DUPLEX) || (reg_id == ADC_CHANNEL_DUPLEX_A) || + (reg_id == ADC_CHANNEL_DUPLEX_B)); + } + + /* Data is not available to be read from ADDRn registers when ADBUF is enabled. Read API cannot be used with ADBUF enabled. */ + adc_extended_cfg_t * p_extend = (adc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + FSP_ASSERT(1U != p_extend->enable_adbuf); +#endif + + /* Read the data from the requested ADC conversion register and return it */ + *p_data = p_instance_ctrl->p_reg->ADDR[reg_id]; + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads conversion results from a single channel or sensor register into a 32-bit result. + * + * @retval FSP_SUCCESS Data read into provided p_data. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_ADC_Read32 (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data) +{ + uint16_t result = 0U; + uint32_t result_32 = 0U; + +#if ADC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_data); +#endif + + fsp_err_t err = R_ADC_Read(p_ctrl, reg_id, &result); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + result_32 = result; + + /* Left shift the result into the upper 16 bits if the unit is configured for left alignment. */ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + if (ADC_ALIGNMENT_LEFT == p_instance_ctrl->p_cfg->alignment) + { + result_32 <<= ADC_SHIFT_LEFT_ALIGNED_32_BIT; + } + + *p_data = result_32; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the sample state count for individual channels. This only needs to be set for special use cases. Normally, use + * the default values out of reset. + * + * @note The sample states for the temperature and voltage sensor are set in R_ADC_ScanCfg. + * + * @retval FSP_SUCCESS Sample state count updated. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_SampleStateCountSet (adc_ctrl_t * p_ctrl, adc_sample_state_t * p_sample) +{ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + + /* Perform parameter checking */ +#if ADC_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are valid */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_sample); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED); + + /* Verify arguments are legal */ + err = r_adc_sample_state_cfg_check(p_instance_ctrl, p_sample); + if (FSP_SUCCESS != err) + { + return err; + } +#endif + + /* Set the sample state count for the specified register */ + p_instance_ctrl->p_reg->ADSSTR[p_sample->reg_id] = p_sample->num_states; + + /* Return the error code */ + return err; +} + +/*******************************************************************************************************************//** + * Returns the address of the lowest number configured channel and the total number of bytes to be read in order to + * read the results of the configured channels and return the ELC Event name. If no channels are configured, then a + * length of 0 is returned. + * + * Also provides the temperature sensor slope and the calibration data for the sensor if available on this MCU. + * Otherwise, invalid calibration data of 0xFFFFFFFF will be returned. + * + * @note In group mode, information is returned for group A only. Calculating information for group B is not currently + * supported. + * + * @retval FSP_SUCCESS Information stored in p_adc_info. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_InfoGet (adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info) +{ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + uint32_t adc_mask = 0; + +#if ADC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_adc_info); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Retrieve the scan mask of active channels from the control structure */ + adc_mask = p_instance_ctrl->scan_mask; + + /* If at least one channel is configured, determine the highest and lowest configured channels. */ + if (adc_mask != 0U) + { + /* Determine the lowest channel that is configured. The lowest sensor is the temperature sensor, at -3 from + * channel 0. To get all channels in register order, shift up by 3, then add in the sensors in the bottom + * 2 bits. */ + uint32_t adc_mask_in_order = adc_mask & ~(uint32_t) ADC_MASK_SENSORS; + adc_mask_in_order <<= 3U; + adc_mask_in_order |= adc_mask >> ADC_MASK_FIRST_SENSOR_BIT; + uint32_t lowest_channel = r_adc_lowest_channel_get(adc_mask_in_order); + p_adc_info->p_address = &p_instance_ctrl->p_reg->ADDR[lowest_channel - 3]; + + /* Determine the highest channel that is configured. */ + uint32_t highest_channel = 31 - __CLZ(adc_mask_in_order); + + /* Determine the size of data that must be read to read all the channels between and including the + * highest and lowest channels.*/ + p_adc_info->length = (uint32_t) ((highest_channel - lowest_channel) + 1); + } + else + { + /* If no channels are configured, set the return length 0. */ + p_adc_info->length = 0U; + } + + p_adc_info->transfer_size = TRANSFER_SIZE_2_BYTE; + +#if BSP_FEATURE_ADC_UNIT_1_CHANNELS_MASK + + /* Specify the peripheral name in the ELC list */ + p_adc_info->elc_event = + (elc_event_t) ((uint32_t) ELC_EVENT_ADC0_SCAN_END + + (p_instance_ctrl->p_cfg->unit * + ((uint32_t) ELC_EVENT_ADC1_SCAN_END - (uint32_t) ELC_EVENT_ADC0_SCAN_END))); +#else + p_adc_info->elc_event = ELC_EVENT_ADC0_SCAN_END; +#endif + + p_adc_info->elc_peripheral = (elc_peripheral_t) (ELC_PERIPHERAL_ADC0 + (2U * p_instance_ctrl->p_cfg->unit)); + + /* Set Temp Sensor calibration data to invalid value */ + p_adc_info->calibration_data = UINT32_MAX; + + /* If calibration register is available, retrieve it from the MCU */ +#if 1U == BSP_FEATURE_TSN_CALIBRATION_AVAILABLE + + /* Read into memory. */ + uint32_t data = R_TSN->TSCDR; + + #if 1U == BSP_FEATURE_TSN_CALIBRATION32_AVAILABLE + + /* Read the temperature calibration data from ROM. */ + p_adc_info->calibration_data = (data & BSP_FEATURE_TSN_CALIBRATION32_MASK); + #else + + /* Read the temperature calibration data from ROM. */ + p_adc_info->calibration_data = data; + + #if 1U == BSP_FEATURE_TSN_HAS_ROOM_TEMP_REG + + /* Read the temperature calibration data from ROM. */ + p_adc_info->room_calibration_data = R_TSN->TSCDRR; + #endif + + #if 1U == BSP_FEATURE_TSN_HAS_LOW_TEMP_REG + + /* Read the temperature calibration data from ROM. */ + p_adc_info->low_calibration_data = R_TSN->TSCDRL; + #endif + #endif +#endif + + /* Provide the previously retrieved slope information */ + p_adc_info->slope_microvolts = BSP_FEATURE_TSN_SLOPE; + + return err; +} + +/*******************************************************************************************************************//** + * This function ends any scan in progress, disables interrupts, and removes power to the A/D peripheral. + * + * @retval FSP_SUCCESS Module closed. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_Close (adc_ctrl_t * p_ctrl) +{ + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + +#if ADC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Mark driver as closed */ + p_instance_ctrl->opened = 0U; + p_instance_ctrl->initialized = 0U; + + /* Disable interrupts. */ + adc_extended_cfg_t * p_extend = (adc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + r_adc_irq_disable(p_instance_ctrl->p_cfg->scan_end_irq); + r_adc_irq_disable(p_instance_ctrl->p_cfg->scan_end_b_irq); + r_adc_irq_disable(p_extend->window_a_irq); + r_adc_irq_disable(p_extend->window_b_irq); + + /* Disable triggers. */ + p_instance_ctrl->p_reg->ADSTRGR = 0U; + + /* Stop the ADC. */ + p_instance_ctrl->p_reg->ADCSR = 0U; + +#if BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG + + /* Disable sample and hold before entering module stop state to reduce power consumption (See + * "Available Functions and Register Settings of AN000 to AN002, AN007, AN100 to AN102, and AN107" in the ADC section of + * the relevant hardware manual. */ + p_instance_ctrl->p_reg->ADSHCR = 0U; +#endif + +#if BSP_FEATURE_ADC_HAS_VREFAMPCNT + + /* If VREFADC is selected as the high-potential reference voltage revert it to reduce power consumption. */ + p_instance_ctrl->p_reg->VREFAMPCNT = 0U; +#endif + + R_BSP_MODULE_STOP(FSP_IP_ADC, p_instance_ctrl->p_cfg->unit); + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Initiates calibration of the ADC on MCUs that require calibration. This function must be called before starting + * a scan on MCUs that require calibration. + * + * Calibration is complete when the callback is called with ADC_EVENT_CALIBRATION_COMPLETE or when R_ADC_StatusGet + * returns ADC_STATUS_IDLE. See figure "Software flow and operation example of calibration operation." + * in the ADC section of the relevant hardware manual. + * + * ADC calibration time: 12 PCLKB + 774,930 ADCLK. See table "Required calibration time (shown + * as the number of ADCLK and PCLKB cycles)" in the ADC section of the relevant hardware manual. + * The lowest supported ADCLK is 1MHz. + * + * Calibration will take a minimum of 24 milliseconds at 32 MHz PCLKB and ADCLK. This wait could take up to 780 + * milliseconds for a 1 MHz PCLKD (ADCLK). + * + * @param[in] p_ctrl Pointer to the instance control structure + * @param[in] p_extend Unused argument. Pass NULL. + * + * @retval FSP_SUCCESS Calibration successfully initiated. + * @retval FSP_ERR_INVALID_HW_CONDITION A scan is in progress or hardware triggers are enabled. + * @retval FSP_ERR_UNSUPPORTED Calibration not supported on this MCU. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN Unit is not open. + **********************************************************************************************************************/ +fsp_err_t R_ADC_Calibrate (adc_ctrl_t * const p_ctrl, void const * p_extend) +{ + FSP_PARAMETER_NOT_USED(p_extend); + +#if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl; + #if ADC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + #endif + + /* ADC Calibration can only happen if there is no ongoing scan and if the scan trigger is disabled */ + FSP_ERROR_RETURN(!(p_instance_ctrl->p_reg->ADCSR & ADC_PRV_ADCSR_ADST_TRGE_MASK), FSP_ERR_INVALID_HW_CONDITION); + + /* Set the normal mode interrupt request to occur when calibration is complete */ + p_instance_ctrl->p_reg->ADICR = ADC_ADICR_CALIBRATION_INTERRUPT_ENABLED; + + /* Initiate calibration */ + p_instance_ctrl->p_reg->ADCALEXE = ADC_ADCALEXE_SET_CALEXE; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_ERROR_LOG(FSP_ERR_UNSUPPORTED); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::offsetSet is not supported on the ADC. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_ADC_OffsetSet (adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(reg_id); + FSP_PARAMETER_NOT_USED(offset); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup ADC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if ADC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Checks the sample state configuration. + * + * @param[in] p_instance_ctrl Pointer to instance control structure + * @param[in] p_sample Pointer to sample state configuration + * + * @retval FSP_SUCCESS No configuration errors detected + * @retval FSP_ERR_ASSERTION An input argument is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_adc_sample_state_cfg_check (adc_instance_ctrl_t * p_instance_ctrl, adc_sample_state_t * p_sample) +{ + /* Used to prevent compiler warning */ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + + adc_sample_state_reg_t reg_id = p_sample->reg_id; + + /* Verify the requested channel exists on the MCU. */ + if (reg_id >= ADC_SAMPLE_STATE_CHANNEL_0) + { + uint32_t requested_channel_mask = (1U << (uint32_t) reg_id); + FSP_ASSERT(0 != (requested_channel_mask & g_adc_valid_channels[p_instance_ctrl->p_cfg->unit])); + } + + /* Verify the requested sample states is not less than the minimum. */ + FSP_ASSERT(p_sample->num_states >= ADC_SAMPLE_STATE_COUNT_MIN); + + return FSP_SUCCESS; +} + +#endif + +#if ADC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Validates the configuration arguments for illegal combinations or options. + * + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS No configuration errors detected + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT ADC unit not present on this MCU + * @retval FSP_ERR_INVALID_HW_CONDITION The ADC clock must be at least 1 MHz + **********************************************************************************************************************/ +static fsp_err_t r_adc_open_cfg_check (adc_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_cfg); + + /* Verify the unit exists on the MCU. */ + FSP_ERROR_RETURN(((1U << p_cfg->unit) & BSP_FEATURE_ADC_VALID_UNIT_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Verify the ADC clock frequency is at least 1 MHz (See "Frequency" row of table "ADC12 + * Characteristics" in the relevant hardware manual.) The maximum frequency is the maximum frequency supported + * by the ADCLK, so it is not verified here. */ + uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_ADC_CLOCK_SOURCE); + FSP_ERROR_RETURN(freq_hz >= ADC_PRV_MIN_ADCLK_HZ, FSP_ERR_INVALID_HW_CONDITION); + + /* Check for valid argument values for addition/averaging. See "A/D-Converted Value + * Addition/Average Count Select Register (ADADC)" desciption in the ADC section of the relevant hardware manual and + * "A/D-Converted Value Average Count Select Register (ADADC)" in the ADC section of the relevant hardware manual. */ + adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_cfg->p_extend; + if (ADC_ADD_OFF != p_cfg_extend->add_average_count) + { + #if BSP_FEATURE_ADC_ADDITION_SUPPORTED + + /* The ADC12 and ADC14 do not support averaging 8 or 16 samples. */ + FSP_ASSERT(p_cfg_extend->add_average_count <= ADC_ADD_AVERAGE_FOUR); + #else + + /* The ADC16 supports averaging only, it does not support addition. */ + FSP_ASSERT(0U != (ADC_ADADC_AVEE_BIT & p_cfg_extend->add_average_count)); + #endif + } + + /* If 16 time addition is used only 12 bit accuracy can be selected. See Note 1 of + * "A/D-Converted Value Addition/Average Count Select Register (ADADC)" description in the ADC section of the relevant hardware manual. */ + if (ADC_ADD_SIXTEEN == p_cfg_extend->add_average_count) + { + FSP_ASSERT(ADC_RESOLUTION_12_BIT == p_cfg->resolution); + } + + /* Only synchronous triggers (ELC) allowed in group scan mode (See + * "A/D Conversion Start Trigger Select Register (ADSTRGR)" desciption in the ADC section of the relevant hardware manual.) */ + if ((ADC_MODE_GROUP_SCAN == p_cfg->mode) || (ADC_DOUBLE_TRIGGER_DISABLED != p_cfg_extend->double_trigger_mode)) + { + FSP_ASSERT((ADC_START_SOURCE_DISABLED != p_cfg_extend->trigger) && + (ADC_START_SOURCE_ASYNC_EXTERNAL != p_cfg_extend->trigger)); + + if ((ADC_MODE_GROUP_SCAN == p_cfg->mode)) + { + FSP_ASSERT((ADC_START_SOURCE_DISABLED != p_cfg_extend->trigger_group_b) && \ + (ADC_START_SOURCE_ASYNC_EXTERNAL != p_cfg_extend->trigger_group_b)); + } + } + + return FSP_SUCCESS; +} + +#endif + +#if ADC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * This function validates the resolution configuration arguments for illegal combinations or options. + * + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS No configuration errors detected + * @retval FSP_ERR_ASSERTION An input argument is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_adc_open_cfg_resolution_check (adc_cfg_t const * const p_cfg) +{ + #if 12U == BSP_FEATURE_ADC_MAX_RESOLUTION_BITS + #if BSP_FEATURE_ADC_HAS_ADCER_ADPRC + + /* Resolution options for ADC12 (reference section "A/D Control Extended Register (ADCER)" in the relevant hardware manual.) */ + FSP_ASSERT((ADC_RESOLUTION_12_BIT == p_cfg->resolution) || + (ADC_RESOLUTION_10_BIT == p_cfg->resolution) || + (ADC_RESOLUTION_8_BIT == p_cfg->resolution)); + #else + FSP_ASSERT(ADC_RESOLUTION_12_BIT == p_cfg->resolution); + #endif + #endif + + #if 14U == BSP_FEATURE_ADC_MAX_RESOLUTION_BITS + + /* Resolution options for ADC14 (reference section "A/D Control Extended Register (ADCER)" in the relevant hardware manual.) */ + FSP_ASSERT((ADC_RESOLUTION_12_BIT == p_cfg->resolution) || + (ADC_RESOLUTION_14_BIT == p_cfg->resolution)); + #endif + + #if 16U == BSP_FEATURE_ADC_MAX_RESOLUTION_BITS + + /* ADC16 only offers 16-bit resolution (refer "ADC16 specifications" in the relevant hardware manual.) */ + FSP_ASSERT(ADC_RESOLUTION_16_BIT == p_cfg->resolution); + #endif + + return FSP_SUCCESS; +} + +#endif + +#if ADC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Checks the sample and hold arguments + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_channel_cfg Pointer to channel configuration + * + * @retval FSP_SUCCESS No configuration errors detected + * @retval FSP_ERR_ASSERTION An input argument is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_adc_scan_cfg_check_sample_hold (adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg) +{ + #if !BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG + + /* If the MCU does not have sample and hold, verify the sample and hold feature is not used. */ + FSP_ASSERT(0U == p_channel_cfg->sample_hold_mask); + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #else + if (0U != p_channel_cfg->sample_hold_mask) + { + /* Sample and Hold channels can only be 0, 1, 2 and must have at least minimum state count specified (reference + * section "A/D Sample and Hold Circuit Control Register (ADSHCR)" description in the ADC section of the relevant hardware manual.) */ + FSP_ASSERT(p_channel_cfg->sample_hold_mask <= ADC_SAMPLE_HOLD_CHANNELS); + FSP_ASSERT(p_channel_cfg->sample_hold_states >= ADC_SAMPLE_STATE_HOLD_COUNT_MIN); + + uint32_t b_mask = p_channel_cfg->sample_hold_mask & p_channel_cfg->scan_mask_group_b; + if (ADC_MODE_GROUP_SCAN == p_instance_ctrl->p_cfg->mode) + { + if (ADC_GROUP_A_PRIORITY_OFF != p_channel_cfg->priority_group_a) + { + /* Sample and hold channels cannot be in GroupB if GroupA priority enabled. (reference SHANS[2:0] bits + * in section "A/D Sample and Hold Circuit Control Register (ADSHCR)" description in the ADC section of the relevant + * hardware manual.*/ + FSP_ASSERT(0 == b_mask); + } + } + } + #endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enforces constraints on Window Compare function usage per section "Constraints on the compare function" in + * the relevant hardware manual + * + * @param[in] p_window_cfg Pointer to window compare configuration + * + * @retval FSP_SUCCESS No configuration errors detected + * @retval FSP_ERR_ASSERTION An input argument is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_adc_scan_cfg_check_window_compare (adc_window_cfg_t const * const p_window_cfg) +{ + if (p_window_cfg) + { + uint32_t compare_cfg = p_window_cfg->compare_cfg; + if (0U != compare_cfg) + { + if ((compare_cfg & R_ADC0_ADCMPCR_CMPAE_Msk) && (compare_cfg & R_ADC0_ADCMPCR_CMPBE_Msk)) + { + /* Ensure channels selected for Window A do not conflict with Window B */ + uint32_t compare_b_ch = p_window_cfg->compare_b_channel; + compare_b_ch -= compare_b_ch > 31 ? 4 : 0; + FSP_ASSERT(!(p_window_cfg->compare_mask & (uint32_t) (1 << compare_b_ch))); + } + + if (compare_cfg & R_ADC0_ADCMPCR_WCMPE_Msk) + { + /* Ensure lower reference values are less than or equal to the high reference values */ + FSP_ASSERT((p_window_cfg->compare_ref_low <= p_window_cfg->compare_ref_high) && + (p_window_cfg->compare_b_ref_low <= p_window_cfg->compare_b_ref_high)); + } + } + } + + return FSP_SUCCESS; +} + +#endif + +#if ADC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * This function checks the Temperature and Voltage sensor arguments + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_channel_cfg Pointer to channel configuration + * + * @retval FSP_SUCCESS No configuration errors detected + * @retval FSP_ERR_ASSERTION Sensor configuration has been selected for Group B on an MCU which does not allow + * Group B configuration or sensor is used in Normal/Group A with the double trigger + * not enabled or MCU does not allow both the sensors to be used simultaneously + **********************************************************************************************************************/ +static fsp_err_t r_adc_scan_cfg_check_sensors (adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg) +{ + /* Some MCUs have nothing to check here. */ + FSP_PARAMETER_NOT_USED(p_channel_cfg); + + #if !BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED + + /* Sensors are not supported in Group B in some MCUs. Reference section "A/D Conversion Extended Input + * Control Register (ADEXICR)" description in the ADC section of the relevant hardware manual. */ + FSP_ASSERT(0U == (p_channel_cfg->scan_mask_group_b & ADC_MASK_SENSORS)); + #endif + + #if BSP_FEATURE_ADC_SENSORS_EXCLUSIVE + uint32_t sensor_mask = p_channel_cfg->scan_mask & ADC_MASK_SENSORS; + if (0U != sensor_mask) + { + /* If the temperature sensor or the internal voltage reference is used, then none of the channels can be used + * at the same time. The temperature sensor and the internal voltage reference can only be used in single scan + * mode. Reference TSSA and OCSA bits in section "A/D Conversion Extended Input Control Register + * (ADEXICR)" description in the ADC section of the relevant hardware manual. */ + FSP_ASSERT(ADC_MASK_SENSORS != sensor_mask); + FSP_ASSERT(p_channel_cfg->scan_mask == sensor_mask); + FSP_ASSERT(ADC_MODE_SINGLE_SCAN == p_instance_ctrl->p_cfg->mode); + } + #endif + + /* When using double-trigger modes the sensors must not be configured or used in Group A. */ + adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + if (ADC_DOUBLE_TRIGGER_DISABLED != p_cfg_extend->double_trigger_mode) + { + FSP_ASSERT(0U == (p_channel_cfg->scan_mask & ADC_MASK_SENSORS)); + } + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * The Open function applies power to the A/D peripheral, sets the operational mode, trigger sources, and + * configurations common to all channels and sensors. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration structure + **********************************************************************************************************************/ +static void r_adc_open_sub (adc_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg) +{ + adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_cfg->p_extend; + + /* Determine the value for ADCSR: + * * The configured mode is set in ADCSR.ADCS. + * * Low-power conversion mode must be selected when internal reference voltage is selected as the high-potential + * reference voltage. + * * ADCSR.GBADIE is always set by this driver. It will only trigger an interrupt in group mode if the group B + * interrupt is enabled. + * * If double-trigger mode is selected ADCSR.DBLANS is set to the chosen double-trigger scan channel and + * ADCSR.DBLE is set to 1; otherwise, both are set to 0. + * * The configured trigger mode is set in ADCSR.EXTRG and ADCSR.TRGE. + * * The value to set in ADCSR to start a scan is stored in the control structure. ADCSR.ADST is set in + * R_ADC_ScanStart if software trigger mode is used. + */ + uint32_t adcsr = (uint32_t) (p_cfg->mode << R_ADC0_ADCSR_ADCS_Pos); + adcsr |= (uint32_t) (R_ADC0_ADCSR_GBADIE_Msk | R_ADC0_ADCSR_TRGE_Msk); + adcsr |= ((uint32_t) (ADC_START_SOURCE_ASYNC_EXTERNAL == p_cfg_extend->trigger) << R_ADC0_ADCSR_EXTRG_Pos); // Only check GroupA. GroupB is never external. + adcsr |= ((uint32_t) (ADC_START_SOURCE_DISABLED != p_cfg_extend->trigger) << R_ADC0_ADCSR_TRGE_Pos); // Only check GroupA. GroupB is never external. + +#if BSP_FEATURE_ADC_HAS_ADHVREFCNT + if (ADC_PRV_ADHVREFCNT_VREF_INTERNAL_BIT_1 & p_cfg_extend->adc_vref_control) + { + adcsr |= R_ADC0_ADCSR_ADHSC_Msk; + } +#endif + + if (ADC_DOUBLE_TRIGGER_DISABLED != p_cfg_extend->double_trigger_mode) + { + adcsr |= R_ADC0_ADCSR_DBLE_Msk; + } + else if (ADC_START_SOURCE_DISABLED == p_cfg_extend->trigger) + { + adcsr |= R_ADC0_ADCSR_ADST_Msk; + } + else + { + /* Do nothing. */ + } + + p_instance_ctrl->scan_start_adcsr = (uint16_t) adcsr; + + /* The default value for ADSTRGR is 0 out of reset. Update it only if the ADC is triggered on ELC events. */ + + /* Set ADSTRGR per the following: + * Extended double-trigger mode: + * - Normal (Group A): ELC_PERIPHERAL_ADCn and ELC_PERIPHERAL_ADCn_B + * - Group B: None + * All other modes: + * - Normal (Group A): ELC_PERIPHERAL_ADCn + * - Group B: ELC_PERIPHERAL_ADCn_B + */ + uint32_t adstrgr = + ((R_ADC0_ADSTRGR_TRSA_Msk & ((uint32_t) p_cfg_extend->trigger << R_ADC0_ADSTRGR_TRSA_Pos)) | \ + (R_ADC0_ADSTRGR_TRSB_Msk & ((uint32_t) p_cfg_extend->trigger_group_b << R_ADC0_ADSTRGR_TRSB_Pos))); + + /* Determine the value for ADCER: + * * The resolution is set as configured in ADCER.ADPRC (on MCUs that have this bitfield). + * * The alignment is set as configured in ADCER.ADFMT (on MCUs that have this bitfield). + * * The clearing option is set as configured in ADCER.ACE. + * * Always select data range of 0 - 32767 in ADCER.INV (on MCUs that have this bitfield). + * * Always disable self-diagnosis (unsupported in this module). + */ + uint32_t adcer = 0U; +#if BSP_FEATURE_ADC_HAS_ADCER_ADPRC + adcer |= (uint32_t) p_cfg->resolution << R_ADC0_ADCER_ADPRC_Pos; +#endif +#if BSP_FEATURE_ADC_HAS_ADCER_ADRFMT + adcer |= (uint32_t) p_cfg->alignment << R_ADC0_ADCER_ADRFMT_Pos; +#endif + adcer |= (uint32_t) p_cfg_extend->clearing << R_ADC0_ADCER_ACE_Pos; + +#if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE + adcer |= 1U << R_ADC0_ADCER_ADINV_Pos; +#endif + + /* Determine the value for ADADC: + * * The addition/averaging modes are set as configured in ADADC.ADC and ADADC.AVEE. + * * On MCUs that do not have the ADADC.AVEE bit (addition not supported), the ADADC.AVEE bit is cleared. + */ + uint32_t adadc = p_cfg_extend->add_average_count; +#if !BSP_FEATURE_ADC_ADDITION_SUPPORTED + adadc &= ~ADC_ADADC_AVEE_BIT; +#endif + + /* Apply clock to peripheral. */ + R_BSP_MODULE_START(FSP_IP_ADC, p_cfg->unit); + + /* Set the predetermined values for ADCSR, ADSTRGR, ADCER, and ADADC without setting ADCSR.ADST or ADCSR.TRGE. + * ADCSR.ADST or ADCSR.TRGE are set as configured in R_ADC_ScanStart. */ + p_instance_ctrl->p_reg->ADCSR = (uint16_t) (adcsr & ADC_PRV_ADCSR_CLEAR_ADST_TRGE); + p_instance_ctrl->p_reg->ADSTRGR = (uint16_t) adstrgr; + p_instance_ctrl->p_reg->ADCER = (uint16_t) adcer; + p_instance_ctrl->p_reg->ADADC = (uint8_t) adadc; + +#if BSP_FEATURE_ADC_HAS_PGA + + /* Disable the unused ADC PGA feature (on MCUs where it is available) since the feature is enabled out of reset on + * some MCUs and disabled on others and affects the operation of the normal ADC channels that are multiplexed with + * the PGA. */ + p_instance_ctrl->p_reg->ADPGADCR0 = ADC_ADPGADCR0_DISABLE_PGA; + p_instance_ctrl->p_reg->ADPGACR = ADC_ADPGACR_DISABLE_PGA; +#endif + +#if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE + + /* Use ADC in single-ended mode. */ + p_instance_ctrl->p_reg->ADANIM = 0U; +#endif + +#if BSP_FEATURE_ADC_HAS_VREFAMPCNT + + /* If VREFADC is selected as the high-potential reference voltage. */ + if (ADC_VREF_CONTROL_VREFH != p_cfg_extend->adc_vref_control) + { + /* Configure Reference Voltage controls + * See "Selecting Reference Voltage" in the ADC section of the relevant hardware manual. */ + p_instance_ctrl->p_reg->VREFAMPCNT = + (uint8_t) (p_cfg_extend->adc_vref_control & + (R_ADC0_VREFAMPCNT_BGREN_Msk | R_ADC0_VREFAMPCNT_VREFADCG_Msk)); + + R_BSP_SoftwareDelay(ADC_BGR_STABILIZATION_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + /* Enable Over current detection and VREFADC output */ + p_instance_ctrl->p_reg->VREFAMPCNT = (uint8_t) (p_cfg_extend->adc_vref_control); + } +#endif + +#if BSP_FEATURE_ADC_HAS_ADHVREFCNT + + /* If the internal voltage is set as VREFH, discharge the VREF node for 1 us before setting ADHVREFCNT.HVSEL to 2. + * See "A/D Conversion Procedure when Selecting Internal Reference Voltage as High-Potential + * Reference Voltage" in the ADC section of the relevant hardware manual. + * + * Also wait 5 us before using the ADC. This wait is the responsibility of the application. */ + if (ADC_PRV_ADHVREFCNT_VREF_INTERNAL_BIT_1 & p_cfg_extend->adc_vref_control) + { + p_instance_ctrl->p_reg->ADHVREFCNT = (uint8_t) (p_cfg_extend->adc_vref_control | R_ADC0_ADHVREFCNT_HVSEL_Msk); + + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); + } + p_instance_ctrl->p_reg->ADHVREFCNT = (uint8_t) p_cfg_extend->adc_vref_control; +#endif + +#if BSP_FEATURE_ADC_HAS_ADBUF + uint8_t adbuf = 0; + if (1U == p_cfg_extend->enable_adbuf) + { + adbuf = R_ADC0_ADBUFEN_BUFEN_Msk; + } + p_instance_ctrl->p_reg->ADBUFEN = adbuf; +#endif +} + +/*******************************************************************************************************************//** + * This function set the sensor bits taking into account group inclusion and addition/average mode. + * This function must only be called if it has been verified that sensors are used in this configuration + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_channel_cfg Pointer to channel configuration + **********************************************************************************************************************/ +static void r_adc_sensor_cfg (adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg) +{ + /* Calculate sample states required for temperature and voltage sensor at the current ADCLK speed. */ + uint32_t sample_states = 0U; + r_adc_sensor_sample_state_calculation(&sample_states); + + /* Check if the temperature sensor channel is enabled */ + uint32_t combined_scan_mask = p_channel_cfg->scan_mask | p_channel_cfg->scan_mask_group_b; + uint32_t adexicr = 0U; + if (combined_scan_mask & ADC_MASK_TEMPERATURE) + { +#if BSP_FEATURE_TSN_CONTROL_AVAILABLE + + /* Power on the temperature sensor. This is only needed for TSNs that have the control register */ + R_BSP_MODULE_START(FSP_IP_TSN, 0U); + + /* Enable the temperature sensor output to the ADC */ + R_TSN_CTRL->TSCR = ADC_PRV_TSCR_TSN_ENABLE; +#endif + + /* Set sample state register to the calculated value */ + p_instance_ctrl->p_reg->ADSSTRT = (uint8_t) sample_states; + +#if BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED + if (p_channel_cfg->scan_mask & ADC_MASK_TEMPERATURE) + { + /* Scan the temperature sensor in normal/group A. */ + adexicr |= R_ADC0_ADEXICR_TSSA_Msk; + } + else + { + /* Scan the temperature sensor in group B */ + adexicr |= R_ADC0_ADEXICR_TSSB_Msk; + } + +#else + + /* Scan the temperature sensor in normal/group A. */ + adexicr |= R_ADC0_ADEXICR_TSSA_Msk; +#endif + + /* Enable temperature addition mode if configured. */ + if (p_channel_cfg->add_mask & ADC_MASK_TEMPERATURE) + { + adexicr |= R_ADC0_ADEXICR_TSSAD_Msk; + } + } + + /* Check if the voltage sensor channel is enabled */ + if (combined_scan_mask & ADC_MASK_VOLT) + { + /*sample state registers are set to the calculated value */ + p_instance_ctrl->p_reg->ADSSTRO = (uint8_t) sample_states; +#if BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED + if (p_channel_cfg->scan_mask & ADC_MASK_VOLT) + { + /* Scan the internal reference voltage in normal/group A. */ + adexicr |= R_ADC0_ADEXICR_OCSA_Msk; + } + else + { + /* Scan the internal reference voltage in group B. */ + adexicr |= R_ADC0_ADEXICR_OCSB_Msk; + } + +#else + + /* Scan the internal reference voltage in normal/group A. */ + adexicr |= R_ADC0_ADEXICR_OCSA_Msk; +#endif + + /* Enable temperature addition mode if configured. */ + if (p_channel_cfg->add_mask & ADC_MASK_VOLT) + { + adexicr |= R_ADC0_ADEXICR_OCSAD_Msk; + } + } + + p_instance_ctrl->p_reg->ADEXICR = (uint16_t) adexicr; +} + +/*******************************************************************************************************************//** + * This function calculates the sample states value for the internal sensors and returns an error if the calculated + * value is outside the limit supported by the hardware + * + * @param[out] p_sample_states: The calculates sample state count. + **********************************************************************************************************************/ +static void r_adc_sensor_sample_state_calculation (uint32_t * const p_sample_states) +{ + /* Calculate sample state values such that the sample time for the temperature and voltage sensor is the + * minimum defined by the hardware manual. The minimum is 4.15 microseconds for MF3 devices and + * 5 microseconds for RV40. The sample states will be calculated to allow sampling for this duration. */ + + /* Retrieve the clock source and frequency used by the ADC peripheral and sampling time required for the sensor. */ + uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_ADC_CLOCK_SOURCE); + + /* Calculate sample states required for the current ADC conversion clock (See "A/D Sampling + * State Register n (ADSSTRn) (n = 00 to 07, L, T, O)" description in the ADC section of the relevant hardware manual). + * + * sample_states = required_sample_time / adclk_period + * = required_sample_time (nsec) * adclk_frequency (kHz) / 1000000 (usec / sec) + 1 + * (refactored to avoid overflowing 32 bits, 1 added to round up) + */ + uint32_t sample_states = ((BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME * (freq_hz / ADC_PRV_HZ_PER_KHZ)) / + ADC_PRV_USEC_PER_SEC) + 1U; + + /* The fastest ADC conversion clock is 60 MHz, and the associated sampling time is 4.15 microseconds. The number + * of sample states in this case is 0.00000415 / (1 / 60000000) = 249. This is the maximum number of sample states + * required for the on chip sensors, so this calculation will never overflow 8 bits (255). */ + + /* If sample states are less than the min number of states required, then set them to the minimum. */ + if (sample_states < ADC_SAMPLE_STATE_COUNT_MIN) + { + sample_states = ADC_SAMPLE_STATE_COUNT_MIN; + } + + *p_sample_states = sample_states; +} + +#if ADC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * This function does extensive checking on channel mask settings based upon operational mode. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_channel_cfg Pointer to channel configuration + * + * @retval FSP_SUCCESS No configuration errors detected + * @retval FSP_ERR_ASSERTION An input argument is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_adc_scan_cfg_check (adc_instance_ctrl_t * const p_instance_ctrl, + adc_channel_cfg_t const * const p_channel_cfg) +{ + fsp_err_t err; + uint16_t unit = p_instance_ctrl->p_cfg->unit; + + /* Verify at least one channel is selected for normal / group A. */ + uint32_t valid_channels = g_adc_valid_channels[unit] | ADC_MASK_TEMPERATURE | ADC_MASK_VOLT; + FSP_ASSERT((0U != p_channel_cfg->scan_mask) && (0U == (p_channel_cfg->scan_mask & (~valid_channels)))); + + if (ADC_MODE_GROUP_SCAN == p_instance_ctrl->p_cfg->mode) + { + /* Verify at least one channel is selected for group B. */ + FSP_ASSERT((0U != p_channel_cfg->scan_mask_group_b) && + (0U == (p_channel_cfg->scan_mask_group_b & (~valid_channels)))); + + /* Cannot have the same channel in both groups. */ + FSP_ASSERT(0 == (p_channel_cfg->scan_mask & p_channel_cfg->scan_mask_group_b)); + } + else + { + /* If group mode is not enabled, no channels can be selected for group B. */ + FSP_ASSERT(ADC_MASK_OFF == p_channel_cfg->scan_mask_group_b); + } + + /* Verify sensor configuration. */ + err = r_adc_scan_cfg_check_sensors(p_instance_ctrl, p_channel_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify that if addition is enabled, then at least one channel is selected. */ + adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + if (ADC_ADD_OFF != p_cfg_extend->add_average_count) + { + /* Addition mask should not include bits from inactive channels. + * This also serves as a check for valid channels in the addition mask */ + uint32_t tmp_mask = p_channel_cfg->scan_mask_group_b | p_channel_cfg->scan_mask; + FSP_ASSERT((0U == (p_channel_cfg->add_mask & ~tmp_mask)) && (0U != p_channel_cfg->add_mask)); + } + else + { + /* Channels cannot be selected for addition if addition is not used. */ + FSP_ASSERT(ADC_MASK_OFF == p_channel_cfg->add_mask); + } + + /* Check sample and hold settings. */ + err = r_adc_scan_cfg_check_sample_hold(p_instance_ctrl, p_channel_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check window compare settings. */ + err = r_adc_scan_cfg_check_window_compare(p_channel_cfg->p_window_cfg); + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * This function does extensive checking on channel mask settings based upon operational mode. Mask registers are + * initialized and interrupts enabled in peripheral. Interrupts are also enabled in ICU if corresponding priority + * is not 0. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_channel_cfg Pointer to channel configuration + **********************************************************************************************************************/ +static void r_adc_scan_cfg (adc_instance_ctrl_t * const p_instance_ctrl, adc_channel_cfg_t const * const p_channel_cfg) +{ + /* Set mask for Group A channels. */ + uint32_t scan_mask = p_channel_cfg->scan_mask & ~(uint32_t) ADC_MASK_SENSORS; + adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + + /* Set other channel masks. */ + uint32_t scan_mask_group_b = p_channel_cfg->scan_mask_group_b & ~(uint32_t) ADC_MASK_SENSORS; + uint32_t add_mask = p_channel_cfg->add_mask & ~(uint32_t) ADC_MASK_SENSORS; + + p_instance_ctrl->p_reg->ADANSA[0] = (uint16_t) (scan_mask); + p_instance_ctrl->p_reg->ADANSB[0] = (uint16_t) (scan_mask_group_b); + p_instance_ctrl->p_reg->ADADS[0] = (uint16_t) (add_mask); + p_instance_ctrl->p_reg->ADANSA[1] = (uint16_t) ((scan_mask >> 16)); + p_instance_ctrl->p_reg->ADANSB[1] = (uint16_t) ((scan_mask_group_b >> 16)); + p_instance_ctrl->p_reg->ADADS[1] = (uint16_t) ((add_mask >> 16)); + + /* Configure voltage and/or temperature sensors, if used. */ + r_adc_sensor_cfg(p_instance_ctrl, p_channel_cfg); + +#if BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG + + /* Configure sample and hold. */ + uint32_t adshcr = p_channel_cfg->sample_hold_states; + adshcr |= (p_channel_cfg->sample_hold_mask & ADC_MASK_SAMPLE_HOLD_BYPASS_CHANNELS) << + ADC_MASK_SAMPLE_HOLD_BYPASS_SHIFT; + p_instance_ctrl->p_reg->ADSHCR = (uint16_t) adshcr; +#endif + + /* Get window compare configuration */ + adc_window_cfg_t * p_window_cfg = p_channel_cfg->p_window_cfg; + + uint16_t adcmpcr = 0; + + if (p_window_cfg) + { + /* Save window compare config */ + adcmpcr = (uint16_t) p_window_cfg->compare_cfg; + + if (p_window_cfg->compare_cfg & R_ADC0_ADCMPCR_CMPAE_Msk) + { + /* Set Window A boundary values */ + p_instance_ctrl->p_reg->ADCMPCR = p_window_cfg->compare_cfg & UINT16_MAX; + p_instance_ctrl->p_reg->ADCMPDR0 = p_window_cfg->compare_ref_low; + p_instance_ctrl->p_reg->ADCMPDR1 = p_window_cfg->compare_ref_high; + + /* Set Window A channel mask */ + uint32_t compare_mask = p_window_cfg->compare_mask; + p_instance_ctrl->p_reg->ADCMPANSR[0] = compare_mask & UINT16_MAX; + p_instance_ctrl->p_reg->ADCMPANSR[1] = (uint16_t) (((uint32_t) ~ADC_MASK_SENSORS & compare_mask) >> 16); + p_instance_ctrl->p_reg->ADCMPANSER = + (uint8_t) ((ADC_MASK_SENSORS & compare_mask) >> ADC_MASK_FIRST_SENSOR_BIT); + + /* Set Window A channel inequality mode mask */ + uint32_t compare_mode_mask = p_window_cfg->compare_mode_mask; + p_instance_ctrl->p_reg->ADCMPLR[0] = compare_mode_mask & UINT16_MAX; + p_instance_ctrl->p_reg->ADCMPLR[1] = (uint16_t) (((uint32_t) ~ADC_MASK_SENSORS & compare_mode_mask) >> 16); + p_instance_ctrl->p_reg->ADCMPLER = + (uint8_t) ((ADC_MASK_SENSORS & compare_mode_mask) >> ADC_MASK_FIRST_SENSOR_BIT); + } + + if (p_window_cfg->compare_cfg & R_ADC0_ADCMPCR_CMPBE_Msk) + { + /* Set Window B channel and mode */ + p_instance_ctrl->p_reg->ADCMPBNSR = (uint8_t) ((adc_window_b_mode_t) p_window_cfg->compare_b_channel | + p_window_cfg->compare_b_mode); + + /* Set Window B boundary values */ + p_instance_ctrl->p_reg->ADWINLLB = p_window_cfg->compare_b_ref_low; + p_instance_ctrl->p_reg->ADWINULB = p_window_cfg->compare_b_ref_high; + } + } + + /* Set window compare config */ + p_instance_ctrl->p_reg->ADCMPCR = adcmpcr; + + /* Set group A priority action (not interrupt priority!) + * This will also start the Group B scans if configured for ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN. + */ + p_instance_ctrl->p_reg->ADGSPCR = (uint16_t) p_channel_cfg->priority_group_a; + + /* In double-trigger mode set the channel select bits to the highest selected channel number then return. */ + if (ADC_DOUBLE_TRIGGER_DISABLED != p_cfg_extend->double_trigger_mode) + { + uint32_t adcsr = p_instance_ctrl->p_reg->ADCSR; + adcsr = (adcsr & ~R_ADC0_ADCSR_DBLANS_Msk) + (31U - __CLZ(scan_mask)); + + p_instance_ctrl->p_reg->ADCSR = (uint16_t) adcsr; + p_instance_ctrl->scan_start_adcsr |= (uint16_t) adcsr; + } + + p_instance_ctrl->initialized = ADC_OPEN; +} + +/*******************************************************************************************************************//** + * Disables and clears context for the requested IRQ. + * + * @param[in] irq IRQ to enable + * @param[in] ipl Interrupt priority + * @param[in] p_context Pointer to interrupt context + **********************************************************************************************************************/ +static void r_adc_irq_enable (IRQn_Type irq, uint8_t ipl, void * p_context) +{ + if (irq >= 0) + { + R_BSP_IrqCfgEnable(irq, ipl, p_context); + } +} + +/*******************************************************************************************************************//** + * Disables and clears context for the requested IRQ. + * + * @param[in] irq IRQ to disable + **********************************************************************************************************************/ +static void r_adc_irq_disable (IRQn_Type irq) +{ + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + R_FSP_IsrContextSet(irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Returns the lowest channel index that is configured in order to read the results of the configured channels. + * + * @param[in] adc_mask scan mask of active channels retrieved from the control structure + * + * @retval adc_mask_count index value of lowest channel + **********************************************************************************************************************/ +static uint32_t r_adc_lowest_channel_get (uint32_t adc_mask) +{ + /* Initialize the mask result */ + uint32_t adc_mask_result = 0U; + int32_t adc_mask_count = -1; + while (0U == adc_mask_result) + { + /* Increment channel until a channel is found in the mask. */ + adc_mask_count++; + adc_mask_result = (uint32_t) (adc_mask & (1U << adc_mask_count)); + } + + return (uint32_t) adc_mask_count; +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to ADC instance control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void r_adc_call_callback (adc_instance_ctrl_t * p_ctrl, adc_callback_args_t * p_args) +{ + adc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + adc_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + adc_prv_ns_callback p_callback = (adc_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Clears interrupt flag and calls a callback to notify application of the event. + * + * @param[in] event Event that triggered the ISR + **********************************************************************************************************************/ +static void r_adc_scan_end_common_isr (adc_event_t event) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) R_FSP_IsrContextGet(R_FSP_CurrentIrqGet()); + + /* Clear the BSP IRQ Flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + adc_callback_args_t args; + args.event = event; +#if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE + + /* Store the correct event into the callback argument */ + if (ADC_ADICR_CALIBRATION_INTERRUPT_DISABLED != p_instance_ctrl->p_reg->ADICR) + { + args.event = ADC_EVENT_CALIBRATION_COMPLETE; + + /* Restore the interrupt source to disable interrupts after calibration is done. */ + p_instance_ctrl->p_reg->ADICR = 0U; + } +#endif + + /* Store the unit number into the callback argument */ + args.unit = p_instance_ctrl->p_cfg->unit; + + /* Initialize the channel to 0. It is not used in this implementation. */ + args.channel = ADC_CHANNEL_0; + + /* Populate the context field. */ + args.p_context = p_instance_ctrl->p_context; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_callback) + { + r_adc_call_callback(p_instance_ctrl, &args); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * This function implements the unit 0 interrupt handler for normal/Group A/double trigger scan complete. + **********************************************************************************************************************/ +void adc_scan_end_isr (void) +{ + r_adc_scan_end_common_isr(ADC_EVENT_SCAN_COMPLETE); +} + +/*******************************************************************************************************************//** + * This function implements the interrupt handler for Group B scan complete. + **********************************************************************************************************************/ +void adc_scan_end_b_isr (void) +{ + r_adc_scan_end_common_isr(ADC_EVENT_SCAN_COMPLETE_GROUP_B); +} + +/*******************************************************************************************************************//** + * This function implements the interrupt handler for window compare events. + **********************************************************************************************************************/ +void adc_window_compare_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + adc_extended_cfg_t * p_extend = (adc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + adc_callback_args_t args; + args.event = (irq == p_extend->window_a_irq) ? ADC_EVENT_WINDOW_COMPARE_A : ADC_EVENT_WINDOW_COMPARE_B; + + /* Store the unit number into the callback argument */ + args.unit = p_instance_ctrl->p_cfg->unit; + + if (ADC_EVENT_WINDOW_COMPARE_A == args.event) + { + args.channel = (adc_channel_t) 0; + + R_ADC0_Type * p_reg = p_instance_ctrl->p_reg; + + /* Get all Window A status registers */ + uint16_t adcmpsr0 = p_reg->ADCMPSR[0]; + uint16_t adcmpsr1 = p_reg->ADCMPSR[1]; + uint8_t adcmpser = p_reg->ADCMPSER; + + /* Get the lowest channel that meets Window A criteria */ + uint32_t lowest_channel = __CLZ(__RBIT(adcmpsr0 + (uint32_t) (adcmpsr1 << 16) + (uint32_t) (adcmpser << 29))); + + /* Clear the status flag corresponding to the lowest channel */ + if (lowest_channel < 16) + { + p_reg->ADCMPSR[0] = (uint16_t) (adcmpsr0 & ~(1 << (lowest_channel & 0xF))); + } + else if (lowest_channel < 29) + { + p_reg->ADCMPSR[1] = (uint16_t) (adcmpsr1 & ~(1 << (lowest_channel & 0xF))); + } + else + { + p_reg->ADCMPSER = (uint8_t) (adcmpser & ~(lowest_channel & 0x3)); + } + + args.channel = (adc_channel_t) lowest_channel; + + if (args.channel > 29) + { + /* Adjust sensor channels to align with the adc_channel_t enumeration */ + args.channel = (adc_channel_t) (ADC_CHANNEL_TEMPERATURE + (args.channel - 29)); + } + } + else + { + /* Get channel selected for Window B */ + args.channel = (adc_channel_t) p_instance_ctrl->p_reg->ADCMPBNSR_b.CMPCHB; + + if (args.channel > 31) + { + /* Adjust sensor channels to align with the adc_channel_t enumeration */ + args.channel = (adc_channel_t) (ADC_CHANNEL_TEMPERATURE + (args.channel & 0xF)); + } + + /* Clear IRQ */ + p_instance_ctrl->p_reg->ADCMPBSR_b.CMPSTB = 0; + } + + /* Populate the context field. */ + args.p_context = p_instance_ctrl->p_context; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_callback) + { + r_adc_call_callback(p_instance_ctrl, &args); + } + + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_agt/r_agt.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_agt/r_agt.c new file mode 100644 index 0000000000..78b9d13f8c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_agt/r_agt.c @@ -0,0 +1,1169 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_agt.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "AGT" in ASCII, used to determine if channel is open. */ +#define AGT_OPEN (0x00414754ULL) + +#define AGT_COMPARE_MATCH_A_OUTPUT (0x03U) ///< Enabling AGTOAn pin +#define AGT_COMPARE_MATCH_B_OUTPUT (0x30U) ///< Enabling AGTOBn pin + +#define AGT_SOURCE_CLOCK_PCLKB_BITS (0x3U) + +#define FSUB_FREQUENCY_HZ (32768U) + +#define AGT_PRV_CLOCK_PCLKB_DIV_8 (1U) +#define AGT_PRV_CLOCK_PCLKB_DIV_2 (3U) + +#define AGT_PRV_AGTMR1_TMOD_EVENT_COUNTER (2U) +#define AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH (3U) + +#define AGT_PRV_AGTCR_FORCE_STOP (0xF4U) +#define AGT_PRV_AGTCR_FORCE_STOP_CLEAR_FLAGS (0x4U) +#define AGT_PRV_AGTCR_STATUS_FLAGS (0xF0U) +#define AGT_PRV_AGTCR_STOP_TIMER (0xF0U) +#define AGT_PRV_AGTCR_START_TIMER (0xF1U) + +#define AGT_PRV_AGTCMSR_PIN_B_OFFSET (4U) +#define AGT_PRV_AGTCMSR_VALID_BITS (0x77U) + +#define AGT_PRV_MIN_CLOCK_FREQ (0U) + +#define AGT_PRV_CHANNEL_SIZE ((uint32_t) R_AGTX1_BASE - (uint32_t) R_AGTX0_BASE) + +#if BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + #if BSP_FEATURE_AGT_AGT_CHANNEL_COUNT + #define AGT_PRV_DETERMINE_IS_AGTW(p_cfg) (((agt_extended_cfg_t const *) (p_cfg)->p_extend)-> \ + counter_bit_width == AGT_COUNTER_BIT_WIDTH_32) + #else + #define AGT_PRV_DETERMINE_IS_AGTW(p_cfg) (true) + #endif +#else + #define AGT_PRV_DETERMINE_IS_AGTW(p_cfg) (false) +#endif + +#define AGT_PRV_IS_AGTW(p_instance_ctrl) ((p_instance_ctrl)->is_agtw) + +#define AGT_PRV_CHANNEL_OFFSET_AGT_AGTW(p_instance_ctrl, channel) \ + ((uint8_t) ((AGT_PRV_IS_AGTW(p_instance_ctrl)) ? (channel) : ((channel) + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT))) + +#define AGT_PRV_CTRL_PTR(p_instance_ctrl) ((agt_prv_reg_ctrl_ptr_t) (AGT_PRV_IS_AGTW((p_instance_ctrl)) \ + ? &(p_instance_ctrl)->p_reg->AGT32.CTRL \ + : &(p_instance_ctrl)->p_reg->AGT16.CTRL)) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * agt_prv_ns_callback)(timer_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile agt_prv_ns_callback)(timer_callback_args_t * p_args); +#endif + +typedef volatile R_AGTX0_AGT16_CTRL_Type * const agt_prv_reg_ctrl_ptr_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_agt_period_register_set(agt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts); + +static void r_agt_hardware_cfg(agt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg); + +static uint32_t r_agt_clock_frequency_get(R_AGTX0_Type * p_agt_regs, bool is_agtw); + +static fsp_err_t r_agt_common_preamble(agt_instance_ctrl_t * p_instance_ctrl); + +#if AGT_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_agt_open_param_checking(agt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg); + +#endif + +/* ISRs. */ +void agt_int_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* The period for even channels must be known to calculate the frequency of odd channels if the count source is AGT + * underflow. */ +static uint32_t gp_prv_agt_periods[BSP_FEATURE_AGT_AGT_CHANNEL_COUNT + BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT]; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** AGT Implementation of General Timer Driver */ +const timer_api_t g_timer_on_agt = +{ + .open = R_AGT_Open, + .stop = R_AGT_Stop, + .start = R_AGT_Start, + .reset = R_AGT_Reset, + .enable = R_AGT_Enable, + .disable = R_AGT_Disable, + .periodSet = R_AGT_PeriodSet, + .dutyCycleSet = R_AGT_DutyCycleSet, + .compareMatchSet = R_AGT_CompareMatchSet, + .infoGet = R_AGT_InfoGet, + .statusGet = R_AGT_StatusGet, + .callbackSet = R_AGT_CallbackSet, + .close = R_AGT_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup AGT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the AGT module instance. Implements @ref timer_api_t::open. + * + * The AGT hardware does not support one-shot functionality natively. The one-shot feature is therefore implemented in + * the AGT HAL layer. For a timer configured as a one-shot timer, the timer is stopped upon the first timer expiration. + * + * The AGT implementation of the general timer can accept an optional agt_extended_cfg_t extension parameter. For + * AGT, the extension specifies the clock to be used as timer source and the output pin configurations. If the + * extension parameter is not specified (NULL), the default clock PCLKB is used and the output pins are disabled. + * + * Example: + * @snippet r_agt_example.c R_AGT_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the period is not in the valid range of + * 1 to 0xFFFF. + * @retval FSP_ERR_ALREADY_OPEN R_AGT_Open has already been called for this p_ctrl. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt has not been enabled in the vector table. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel number is not available on AGT. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + +#if AGT_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_agt_open_param_checking(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->is_agtw = AGT_PRV_DETERMINE_IS_AGTW(p_cfg); +#endif + +#if BSP_FEATURE_AGT_AGT_CHANNEL_COUNT && BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + uint32_t base_address = (uint32_t) ((AGT_PRV_IS_AGTW(p_instance_ctrl)) ? R_AGTW0 : R_AGT0); +#elif BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT + uint32_t base_address = (uint32_t) R_AGTW0; +#else + uint32_t base_address = (uint32_t) R_AGT0; +#endif + uint32_t channel_base_address = base_address + (p_cfg->channel * AGT_PRV_CHANNEL_SIZE); + p_instance_ctrl->p_reg = (R_AGTX0_Type *) channel_base_address; + + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + /* Power on the AGT channel. */ + R_BSP_MODULE_START(FSP_IP_AGT, AGT_PRV_CHANNEL_OFFSET_AGT_AGTW(p_instance_ctrl, p_cfg->channel)); + + /* Clear AGTCR. This stops the timer if it is running and clears the flags. */ + p_reg_ctrl->AGTCR = 0U; + + /* The timer is stopped in sync with the count clock, or in sync with PCLK in event and external count modes. */ + FSP_HARDWARE_REGISTER_WAIT(0U, p_reg_ctrl->AGTCR_b.TCSTF); + + /* Clear AGTMR2 before AGTMR1 is set. See Note 3 of "AGT Mode Register 2 (AGTMR2)" description + * of the relevant hardware manual. */ + p_reg_ctrl->AGTMR2 = 0U; + + /* Set count source and divider and configure pins. */ + r_agt_hardware_cfg(p_instance_ctrl, p_cfg); + + /* Set period register and update duty cycle if output mode is used for one-shot or periodic mode. */ + r_agt_period_register_set(p_instance_ctrl, p_cfg->period_counts); + + if (p_cfg->cycle_end_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + } + + /* Set callback and context pointers */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + p_instance_ctrl->open = AGT_OPEN; + + /* All done. */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts timer. Implements @ref timer_api_t::start. + * + * Example: + * @snippet r_agt_example.c R_AGT_Start + * + * @retval FSP_SUCCESS Timer started. + * @retval FSP_ERR_ASSERTION p_ctrl is null. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Start (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + /* Reload period register for one-shot timers. This must be done here instead of in the underflow interrupt because + * setting AGTCR.TSTOP causes AGT to be reset after 3 cycles of the count source. When the AGT count source is much + * slower than the core clock, 3 cycles of the count source is too long to wait in an interrupt. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + /* Set counter to period minus one. */ + r_agt_period_register_set(p_instance_ctrl, p_instance_ctrl->period); + } + + /* Start timer */ + p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_START_TIMER; + +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + + /* If using output compare in one-shot mode, update the compare match registers after starting the timer. This + * ensures the output pin will not toggle again right after the period ends. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + /* Verify the timer is started before modifying any other AGT registers. See "Count + * Operation Start and Stop Control" in the AGT Usage Notes section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(1U, p_reg_ctrl->AGTCR_b.TCSTF); + + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + p_instance_ctrl->p_reg->AGT32.AGTCMA = UINT32_MAX; + p_instance_ctrl->p_reg->AGT32.AGTCMB = UINT32_MAX; + } + else + { + p_instance_ctrl->p_reg->AGT16.AGTCMA = UINT16_MAX; + p_instance_ctrl->p_reg->AGT16.AGTCMB = UINT16_MAX; + } + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops the timer. Implements @ref timer_api_t::stop. + * + * Example: + * @snippet r_agt_example.c R_AGT_Stop + * + * @retval FSP_SUCCESS Timer stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Stop (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + /* Stop timer */ + p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_STOP_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter value to the period minus one. Implements @ref timer_api_t::reset. + * + * @retval FSP_SUCCESS Counter reset. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Reset (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Reset counter to period minus one. */ + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + p_instance_ctrl->p_reg->AGT32.AGT = (uint32_t) (p_instance_ctrl->period - 1U); + } + else + { + p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) (p_instance_ctrl->period - 1U); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable. + * + * Example: + * @snippet r_agt_example.c R_AGT_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Enable (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + /* Reset counter to period minus one. */ + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + p_instance_ctrl->p_reg->AGT32.AGT = (uint32_t) (p_instance_ctrl->period - 1U); + } + else + { + p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) (p_instance_ctrl->period - 1U); + } + + /* Enable captures. */ + p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_START_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable. + * + * Example: + * @snippet r_agt_example.c R_AGT_Disable + * + * @retval FSP_SUCCESS External events successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Disable (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + /* Disable captures. */ + p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_STOP_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates period. The new period is updated immediately and the counter is reset to the maximum value. Implements + * @ref timer_api_t::periodSet. + * + * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register. + * If this function is called while the timer is running and an AGT underflow occurs during processing, the duty cycle + * will not be the desired 50% duty cycle until the counter underflow after processing completes. + * + * @warning Stop the timer before calling this function if one-shot output is used. + * + * Example: + * @snippet r_agt_example.c R_AGT_PeriodSet + * + * @retval FSP_SUCCESS Period value updated. + * @retval FSP_ERR_ASSERTION A required pointer was NULL, or the period was not in the valid range of + * 1 to 0xFFFF. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + +#if AGT_CFG_PARAM_CHECKING_ENABLE + if (!AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + /* Validate period parameter. */ + FSP_ASSERT(0U != period_counts); + FSP_ASSERT(period_counts <= AGT_MAX_PERIOD_16BIT); + } +#endif + + /* Set period. */ + r_agt_period_register_set(p_instance_ctrl, period_counts); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates duty cycle. If the timer is counting, the new duty cycle is reflected after the next counter underflow. + * Implements @ref timer_api_t::dutyCycleSet. + * + * Example: + * @snippet r_agt_example.c R_AGT_DutyCycleSet + * + * @retval FSP_SUCCESS Duty cycle updated. + * @retval FSP_ERR_ASSERTION A required pointer was NULL, or the pin was not AGT_AGTO_AGTOA or AGT_AGTO_AGTOB. + * @retval FSP_ERR_INVALID_ARGUMENT Duty cycle was not in the valid range of 0 to period (counts) - 1 + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + * @retval FSP_ERR_UNSUPPORTED AGT_CFG_OUTPUT_SUPPORT_ENABLE is 0. + **********************************************************************************************************************/ +fsp_err_t R_AGT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + #if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT((pin == AGT_OUTPUT_PIN_AGTOA) || (pin == AGT_OUTPUT_PIN_AGTOB)); + #endif + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if AGT_CFG_PARAM_CHECKING_ENABLE + if (0U != p_instance_ctrl->period) + { + FSP_ERROR_RETURN(duty_cycle_counts < (p_instance_ctrl->period), FSP_ERR_INVALID_ARGUMENT); + } + #endif + + /* Set duty cycle. */ + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + volatile uint32_t * const p_agtcm = &p_instance_ctrl->p_reg->AGT32.AGTCMA; + p_agtcm[pin] = duty_cycle_counts; + } + else + { + volatile uint16_t * const p_agtcm = &p_instance_ctrl->p_reg->AGT16.AGTCMA; + p_agtcm[pin] = (uint16_t) duty_cycle_counts; + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(duty_cycle_counts); + FSP_PARAMETER_NOT_USED(pin); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported compareMatch function. Implements @ref timer_api_t::compareMatchSet. + * + * @retval FSP_ERR_UNSUPPORTED AGT compare match is not supported. + **********************************************************************************************************************/ +fsp_err_t R_AGT_CompareMatchSet (timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel) +{ + /* This function isn't supported. It is defined only to implement a required function of timer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(compare_match_value); + FSP_PARAMETER_NOT_USED(match_channel); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Gets timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_agt_example.c R_AGT_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, and frequency stored in p_info. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_info); +#endif + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Get and store period */ + p_info->period_counts = p_instance_ctrl->period; + + /* Get and store clock frequency */ + agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + if (AGT_CLOCK_AGT_UNDERFLOW == p_extend->count_source) + { + /* Clock frequency of this channel is the clock frequency divided by the timer period of the source channel. */ + + /* Source instance is the channel immediately preceding this one. */ + if (0U == + gp_prv_agt_periods[AGT_PRV_CHANNEL_OFFSET_AGT_AGTW(p_instance_ctrl, p_instance_ctrl->p_cfg->channel - 1U)]) + { + p_info->clock_frequency = AGT_PRV_MIN_CLOCK_FREQ; + } + else + { + R_AGTX0_Type * p_source_channel_reg = + (R_AGTX0_Type *) ((uint32_t) p_instance_ctrl->p_reg - AGT_PRV_CHANNEL_SIZE); + p_info->clock_frequency = + r_agt_clock_frequency_get(p_source_channel_reg, AGT_PRV_IS_AGTW(p_instance_ctrl)) / + gp_prv_agt_periods[AGT_PRV_CHANNEL_OFFSET_AGT_AGTW(p_instance_ctrl, + p_instance_ctrl->p_cfg->channel - 1U)]; + } + } + else + { + p_info->clock_frequency = r_agt_clock_frequency_get(p_instance_ctrl->p_reg, AGT_PRV_IS_AGTW(p_instance_ctrl)); + } + + /* AGT supports only counting down direction */ + p_info->count_direction = TIMER_DIRECTION_DOWN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Retrieves the current state and counter value stores them in p_status. Implements @ref timer_api_t::statusGet. + * + * Example: + * @snippet r_agt_example.c R_AGT_StatusGet + * + * @retval FSP_SUCCESS Current status and counter value provided in p_status. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_status); +#endif + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + /* Read the state. */ + p_status->state = (timer_state_t) p_reg_ctrl->AGTCR_b.TCSTF; + + /* Read counter value */ + p_status->counter = + AGT_PRV_IS_AGTW(p_instance_ctrl) ? p_instance_ctrl->p_reg->AGT32.AGT : p_instance_ctrl->p_reg->AGT16.AGT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_AGT_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + agt_instance_ctrl_t * p_ctrl = (agt_instance_ctrl_t *) p_api_ctrl; + +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(AGT_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if AGT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(timer_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops counter, disables interrupts, disables output pins, and clears internal driver data. Implements + * @ref timer_api_t::close. + * + * + * + * @retval FSP_SUCCESS Timer closed. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_AGT_Close (timer_ctrl_t * const p_ctrl) +{ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_agt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + /* Cleanup the device: Stop counter, disable interrupts, and power down if no other channels are in use. */ + + /* Stop timer */ + p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_FORCE_STOP; + + /* Clear AGT output. */ + p_reg_ctrl->AGTIOC = 0U; + + if (FSP_INVALID_VECTOR != p_instance_ctrl->p_cfg->cycle_end_irq) + { + NVIC_DisableIRQ(p_instance_ctrl->p_cfg->cycle_end_irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->cycle_end_irq, p_instance_ctrl); + } + + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/** @} (end addtogroup AGT) */ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if AGT_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking for R_AGT_Open. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * @param[in] p_cfg Configuration structure for this instance + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the period is not in the valid range of + * 1 to 0xFFFF. + * @retval FSP_ERR_ALREADY_OPEN R_AGT_Open has already been called for this p_ctrl. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt has not been enabled in the vector table. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel number is not available on AGT. + **********************************************************************************************************************/ +static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(AGT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Enable IRQ if user supplied a callback function, + * or if the timer is a one-shot timer (so the driver is able to + * turn off the timer after one period. */ + if ((NULL != p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode)) + { + /* Return error if IRQ is required and not in the vector table. */ + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + /* Save pointer to config struct */ + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->is_agtw = AGT_PRV_DETERMINE_IS_AGTW(p_cfg); + + if (!AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + FSP_ASSERT(0U != p_cfg->period_counts); + + /* Validate period parameter. */ + FSP_ASSERT(p_cfg->period_counts <= AGT_MAX_PERIOD_16BIT); + } + + /* Validate channel number. */ + FSP_ERROR_RETURN(((1U << p_cfg->channel) & BSP_FEATURE_AGT_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* AGT_CLOCK_AGT_UNDERFLOW is not allowed on even AGT channels. */ + agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend; + FSP_ASSERT((AGT_CLOCK_AGT_UNDERFLOW != p_extend->count_source) || (p_cfg->channel & 1U)); + + /* Validate divider. */ + if (AGT_CLOCK_PCLKB == p_extend->count_source) + { + /* Allowed dividers for PCLKB are 1, 2, and 8. */ + FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_8); + FSP_ASSERT(p_cfg->source_div != TIMER_SOURCE_DIV_4); + } + else if (AGT_CLOCK_AGT_UNDERFLOW == p_extend->count_source) + { + /* Divider not used if AGT0 underflow is selected as count source. */ + FSP_ASSERT(p_cfg->source_div == TIMER_SOURCE_DIV_1); + } + else + { + /* Allowed dividers for LOCO and SUBCLOCK are 1, 2, 4, 8, 16, 32, 64, and 128. */ + FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_128); + } + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Common code at the beginning of all AGT functions except open. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * + * @retval FSP_SUCCESS No invalid conditions detected, timer state matches expected state. + * @retval FSP_ERR_ASSERTION p_ctrl is null. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +static fsp_err_t r_agt_common_preamble (agt_instance_ctrl_t * p_instance_ctrl) +{ +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(AGT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + uint32_t agtcr = 0U; + bool tstart = false; + bool tcstf = false; + + /* Ensure timer state reflects expected status. See "Count + * Operation Start and Stop Control" in the AGT Usage Notes section of the relevant hardware manual. */ + do + { + agtcr = p_reg_ctrl->AGTCR; + tstart = (bool) (agtcr & R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk); + tcstf = (bool) (agtcr & R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk); + } while (tstart != tcstf); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets count source and divider. + * + * @note Counter must be stopped before entering this function. + * + * @param[in] p_instance_ctrl Control block for this instance + * @param[in] p_cfg Configuration structure for this instance + **********************************************************************************************************************/ +static void r_agt_hardware_cfg (agt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + /* Update the divider for PCLKB. */ + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend; + uint32_t count_source_int = (uint32_t) p_extend->count_source; + uint32_t agtmr2 = 0U; + uint32_t agtcmsr = 0U; + uint32_t tedgsel = 0U; + uint32_t agtioc = p_extend->agtio_filter; + + uint32_t mode = p_extend->measurement_mode & R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk; + + uint32_t edge = 0U; + if (AGT_CLOCK_PCLKB == p_extend->count_source) + { + if (TIMER_SOURCE_DIV_1 != p_cfg->source_div) + { + /* Toggle the second bit if the count_source_int is not 0 to map PCLKB / 8 to 1 and PCLKB / 2 to 3. */ + count_source_int = p_cfg->source_div ^ 2U; + count_source_int <<= R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos; + } + } + +#if AGT_CFG_INPUT_SUPPORT_ENABLE + else if (AGT_CLOCK_AGTIO & p_extend->count_source) + { + /* If the count source is external, configure the AGT for event counter mode. */ + mode = AGT_PRV_AGTMR1_TMOD_EVENT_COUNTER; + count_source_int = 0U; + + edge |= (p_extend->trigger_edge & R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk); + agtioc |= (p_extend->enable_pin & R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk); + p_reg_ctrl->AGTISR = (p_extend->enable_pin & R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk); + if (AGT_PRV_IS_AGTW(p_instance_ctrl) && BSP_FEATURE_AGT_USE_AGTIOSEL_ALT) + { + /* The ALT register is only used for devices with an AGTW whose AGTIOSEL is at offset 0x0F. */ + p_reg_ctrl->AGTIOSEL_ALT = (uint8_t) (p_extend->count_source & (uint8_t) ~AGT_CLOCK_AGTIO); + } + else + { + p_reg_ctrl->AGTIOSEL = (uint8_t) (p_extend->count_source & (uint8_t) ~AGT_CLOCK_AGTIO); + } + } +#endif + else if (AGT_CLOCK_AGT_UNDERFLOW != p_extend->count_source) + { + /* Update the divider for LOCO/subclock. */ + agtmr2 = p_cfg->source_div; + } + else + { + /* No divider can be used when count source is AGT_CLOCK_AGT_UNDERFLOW. */ + } + + uint32_t agtmr1 = (count_source_int | edge) | mode; + + /* Configure output settings. */ + +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Set output if requested */ + agtcmsr = p_extend->agtoab_settings & AGT_PRV_AGTCMSR_VALID_BITS; + + /* Set initial duty cycle for PWM mode in open. Duty cycle is set for other modes in r_agt_period_register_set. */ + if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + uint32_t inverted_duty_cycle = p_instance_ctrl->p_cfg->period_counts - + p_instance_ctrl->p_cfg->duty_cycle_counts - 1; + uint32_t agtcma = p_instance_ctrl->p_cfg->duty_cycle_counts; + uint32_t agtcmb = p_instance_ctrl->p_cfg->duty_cycle_counts; + if (AGT_PIN_CFG_START_LEVEL_HIGH == p_extend->agtoab_settings_b.agtoa) + { + agtcma = inverted_duty_cycle; + } + + if (AGT_PIN_CFG_START_LEVEL_HIGH == p_extend->agtoab_settings_b.agtob) + { + agtcmb = inverted_duty_cycle; + } + + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + p_instance_ctrl->p_reg->AGT32.AGTCMA = agtcma; + p_instance_ctrl->p_reg->AGT32.AGTCMB = agtcmb; + } + else + { + p_instance_ctrl->p_reg->AGT16.AGTCMA = (uint16_t) agtcma; + p_instance_ctrl->p_reg->AGT16.AGTCMB = (uint16_t) agtcmb; + } + } + + /* Configure TEDGSEL bit based on user input. */ + if (AGT_PIN_CFG_DISABLED != p_extend->agto) + { + /* Set the TOE bit if AGTO is enabled. AGTO can be enabled in any mode. */ + agtioc |= (1U << R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos); + + if (AGT_PIN_CFG_START_LEVEL_LOW == p_extend->agto) + { + /* Configure the start level of AGTO. */ + tedgsel |= (1U << R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos); + } + } +#endif +#if AGT_CFG_INPUT_SUPPORT_ENABLE && AGT_CFG_OUTPUT_SUPPORT_ENABLE + else +#endif +#if AGT_CFG_INPUT_SUPPORT_ENABLE + { + /* This if statement applies when p_extend->measurement_mode is AGT_MEASURE_PULSE_WIDTH_LOW_LEVEL or + * AGT_MEASURE_PULSE_WIDTH_HIGH_LEVEL because the high level bit is in bit 4 and was masked off of mode. */ + if (AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH == mode) + { + /* Level is stored with measurement mode for pulse width mode. */ + tedgsel = p_extend->measurement_mode >> 4U; + } + else + { + /* Use the trigger edge for pulse period or event counting modes. */ + tedgsel = (p_extend->trigger_edge & R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk); + } + } +#endif + + agtioc |= tedgsel; + + p_reg_ctrl->AGTIOC = (uint8_t) agtioc; + p_reg_ctrl->AGTCMSR = (uint8_t) agtcmsr; + p_reg_ctrl->AGTMR1 = (uint8_t) agtmr1; + p_reg_ctrl->AGTMR2 = (uint8_t) agtmr2; +} + +/*******************************************************************************************************************//** + * Sets period register and updates compare match registers in one-shot and periodic mode. + * + * @param[in] p_instance_ctrl Control block for this instance + * @param[in] period_counts AGT period in counts + **********************************************************************************************************************/ +static void r_agt_period_register_set (agt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts) +{ + /* Store the period value so it can be retrieved later. */ + p_instance_ctrl->period = period_counts; + gp_prv_agt_periods[AGT_PRV_CHANNEL_OFFSET_AGT_AGTW(p_instance_ctrl, + p_instance_ctrl->p_cfg->channel)] = period_counts; + + uint32_t period_reg = (period_counts - 1U); + +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + uint32_t duty_cycle_counts = 0U; + if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode) + { + duty_cycle_counts = (period_counts >> 1); + } + else if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + duty_cycle_counts = period_reg; + } + else + { + /* Do nothing, duty cycle should not be updated in R_AGT_PeriodSet. */ + } + + if (TIMER_MODE_PWM != p_instance_ctrl->p_cfg->mode) + { + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + p_instance_ctrl->p_reg->AGT32.AGTCMA = duty_cycle_counts; + p_instance_ctrl->p_reg->AGT32.AGTCMB = duty_cycle_counts; + } + else + { + p_instance_ctrl->p_reg->AGT16.AGTCMA = (uint16_t) duty_cycle_counts; + p_instance_ctrl->p_reg->AGT16.AGTCMB = (uint16_t) duty_cycle_counts; + } + } +#endif + + /* Set counter to period minus one. */ + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + p_instance_ctrl->p_reg->AGT32.AGT = period_reg; + } + else + { + p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) period_reg; + } +} + +/*******************************************************************************************************************//** + * Obtains the clock frequency of AGT for all clock sources except AGT0 underflow, with divisor applied. + * + * @param[in] p_agt_regs Registers of AGT channel used + * @param[in] is_agtw Specifies this AGT channel is using the AGTW peripheral. + * + * @return Source clock frequency of AGT in Hz, divider applied. + **********************************************************************************************************************/ +static uint32_t r_agt_clock_frequency_get (R_AGTX0_Type * p_agt_regs, bool is_agtw) +{ + agt_prv_reg_ctrl_ptr_t p_agt_regs_ctrl = is_agtw ? &p_agt_regs->AGT32.CTRL : &p_agt_regs->AGT16.CTRL; + + uint32_t clock_freq_hz = 0U; + uint8_t count_source_int = p_agt_regs_ctrl->AGTMR1_b.TCK; + timer_source_div_t divider = TIMER_SOURCE_DIV_1; + if (0U == (count_source_int & (~AGT_SOURCE_CLOCK_PCLKB_BITS))) + { + /* Call CGC function to obtain current PCLKB clock frequency. */ + clock_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + + /* If Clock source is PCLKB or derived from PCLKB */ + divider = (timer_source_div_t) count_source_int; + if (0U != divider) + { + /* Set divider to 3 to divide by 8 when AGTMR1.TCK is 1 (PCLKB / 8). Set divider to 1 to divide by 2 when + * AGTMR1.TCK is 3 (PCLKB / 2). XOR with 2 to convert 1 to 3 and 3 to 1. */ + divider ^= 2U; + } + } + else + { + /* Else either fSUB clock or LOCO clock is used. The frequency is set to 32Khz (32768). This function does not + * support AGT0 underflow as count source. */ + clock_freq_hz = FSUB_FREQUENCY_HZ; + + divider = (timer_source_div_t) p_agt_regs_ctrl->AGTMR2_b.CKS; + } + + clock_freq_hz >>= divider; + + return clock_freq_hz; +} + +/********************************************************************************************************************* + * AGT counter underflow interrupt. + **********************************************************************************************************************/ +void agt_int_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + agt_instance_ctrl_t * p_instance_ctrl = (agt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + agt_prv_reg_ctrl_ptr_t p_reg_ctrl = AGT_PRV_CTRL_PTR(p_instance_ctrl); + + /* Save AGTCR to determine the source of the interrupt. */ + uint32_t agtcr = p_reg_ctrl->AGTCR; + + /* If the channel is configured to be one-shot mode, stop the timer. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Forcibly stopping the timer resets AGTCMSR, AGTCMA, and AGTCMB. AGTCMA and AGTCMB are based on the + * timer period, but AGTCMSR must be saved so it can be restored. */ + uint8_t agtcmsr = p_reg_ctrl->AGTCMSR; +#endif + + /* Stop timer. This resets the timer period (AGT register). The AGT register is reconfigured in R_AGT_Start(). */ + p_reg_ctrl->AGTCR = AGT_PRV_AGTCR_FORCE_STOP; + agtcr &= AGT_PRV_AGTCR_STATUS_FLAGS; + p_reg_ctrl->AGTCR = (uint8_t) agtcr; + +#if AGT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Restore AGTCMSR. */ + p_reg_ctrl->AGTCMSR = agtcmsr; +#endif + } + + /* Invoke the callback function if it is set. */ + if (NULL != p_instance_ctrl->p_callback) + { + /* Setup parameters for the user-supplied callback function. */ + timer_callback_args_t callback_args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + timer_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &callback_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + callback_args = *p_args; + } + + if (agtcr & R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk) + { + p_args->event = TIMER_EVENT_CYCLE_END; + } + +#if AGT_CFG_INPUT_SUPPORT_ENABLE + else + { + p_args->event = TIMER_EVENT_CAPTURE_A; + uint32_t reload_value = p_instance_ctrl->period - 1U; + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + p_args->capture = reload_value - p_instance_ctrl->p_reg->AGT32.AGT; + } + else + { + p_args->capture = reload_value - p_instance_ctrl->p_reg->AGT16.AGT; + } + + /* The AGT counter is not reset in pulse width measurement mode. Reset it by software. Note that this + * will restart the counter if a new capture has already started. Application writers must ensure that + * this interrupt processing completes before the next capture begins. */ + if (AGT_PRV_AGTMR1_TMOD_PULSE_WIDTH == p_reg_ctrl->AGTMR1_b.TMOD) + { + if (AGT_PRV_IS_AGTW(p_instance_ctrl)) + { + p_instance_ctrl->p_reg->AGT32.AGT = reload_value; + } + else + { + p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) reload_value; + } + } + else + { + /* Period of input pulse = (initial value of counter [AGT register] - reading value of the read-out buffer) + 1 + * Reference section "How to Calculate Event Number, Pulse Width, and Pulse Period" in the AGT Usage Notes section + * of the relevant hardware manual. */ + p_args->capture++; + } + } +#endif + + p_args->p_context = p_instance_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + agt_prv_ns_callback p_callback = (agt_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = callback_args; + } + + /* Retrieve AGTCR in case it was modified in the callback. */ + agtcr = p_reg_ctrl->AGTCR; + } + + /* Clear flags in AGTCR. */ + p_reg_ctrl->AGTCR = (uint8_t) (agtcr & ~AGT_PRV_AGTCR_STATUS_FLAGS); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cac/r_cac.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cac/r_cac.c new file mode 100644 index 0000000000..3b5e2ce5d2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cac/r_cac.c @@ -0,0 +1,509 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_cac.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "CAC" in ASCII, used to determine if channel is open. */ +#define CAC_OPEN (0x00434143ULL) + +/* CAC Control Register 0 Bit Field Definitions */ +#define CAC_PRV_CACR0_CFME_OFFSET (0U) +#define CAC_PRV_CACR0_CFME_MASK (1U << CAC_PRV_CACR0_CFME_OFFSET) + +/* CAC Control Register 1 Bit Field Definitions */ +#define CAC_PRV_CACR1_CACREFE_OFFSET (0U) +#define CAC_PRV_CACR1_CACREFE_MASK (1U << CAC_PRV_CACR1_CACREFE_OFFSET) +#define CAC_PRV_CACR1_FMCS_OFFSET (1U) +#define CAC_PRV_CACR1_FMCS_MASK (0x07U << CAC_PRV_CACR1_FMCS_OFFSET) +#define CAC_PRV_CACR1_TCSS_OFFSET (4U) +#define CAC_PRV_CACR1_TCSS_MASK (0x03U << CAC_PRV_CACR1_TCSS_OFFSET) +#define CAC_PRV_CACR1_EDGES_OFFSET (6U) +#define CAC_PRV_CACR1_EDGES_MASK (0x03U << CAC_PRV_CACR1_EDGES_OFFSET) + +/* CAC Control Register 2 Bit Field Definitions */ +#define CAC_PRV_CACR2_RPS_OFFSET (0U) +#define CAC_PRV_CACR2_RPS_MASK (1U << CAC_PRV_CACR2_RPS_OFFSET) +#define CAC_PRV_CACR2_RSCS_OFFSET (1U) +#define CAC_PRV_CACR2_RCSC_MASK (0x07U << CAC_PRV_CACR2_RSCS_OFFSET) +#define CAC_PRV_CACR2_RCDS_OFFSET (4U) +#define CAC_PRV_CACR2_RCDS_MASK (0x03U << CAC_PRV_CACR2_RCDS_OFFSET) +#define CAC_PRV_CACR2_DFS_OFFSET (6U) +#define CAC_PRV_CACR2_DFS_MASK (0x03U << CAC_PRV_CACR2_DFS_OFFSET) + +/* CAC Interrupt Control Register Bit Field Definitions */ +#define CAC_PRV_CAICR_FERRIE_OFFSET (0U) +#define CAC_PRV_CAICR_FERRIE_MASK (1U << CAC_PRV_CAICR_FERRIE_OFFSET) +#define CAC_PRV_CAICR_MENDIE_OFFSET (1U) +#define CAC_PRV_CAICR_MENDIE_MASK (1U << CAC_PRV_CAICR_MENDIE_OFFSET) +#define CAC_PRV_CAICR_OVFIE_OFFSET (2U) +#define CAC_PRV_CAICR_OVFIE_MASK (1U << CAC_PRV_CAICR_OVFIE_OFFSET) +#define CAC_PRV_CAICR_FERRFCL_OFFSET (4U) +#define CAC_PRV_CAICR_FERRFCL_MASK (1U << CAC_PRV_CAICR_FERRFCL_OFFSET) +#define CAC_PRV_CAICR_MENDFCL_OFFSET (5U) +#define CAC_PRV_CAICR_MENDFCL_MASK (1U << CAC_PRV_CAICR_MENDFCL_OFFSET) +#define CAC_PRV_CAICR_OVFFCL_OFFSET (6U) +#define CAC_PRV_CAICR_OVFFCL_MASK (1U << CAC_PRV_CAICR_OVFFCL_OFFSET) +#define CAC_PRV_CAICR_FLAGS_CLEAR_MASK (CAC_PRV_CAICR_FERRFCL_MASK | CAC_PRV_CAICR_MENDFCL_MASK | \ + CAC_PRV_CAICR_OVFFCL_MASK) + +/* CAC Status Register Bit Field Definitions */ +#define CAC_PRV_CASTR_FERRF_OFFSET (0U) +#define CAC_PRV_CASTR_FERRF_MASK (1U << CAC_PRV_CASTR_FERRF_OFFSET) +#define CAC_PRV_CASTR_MENDF_OFFSET (1U) +#define CAC_PRV_CASTR_MENDF_MASK (1U << CAC_PRV_CASTR_MENDF_OFFSET) +#define CAC_PRV_CASTR_OVFF_OFFSET (2U) +#define CAC_PRV_CASTR_OVFF_MASK (1U << CAC_PRV_CASTR_OVFF_OFFSET) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * cac_prv_ns_callback)(cac_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile cac_prv_ns_callback)(cac_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +void cac_ferri_isr(void); +void cac_mendi_isr(void); +void cac_ovfi_isr(void); + +static void r_cac_hw_configure(cac_instance_ctrl_t * const p_instance_ctrl); +static void r_cac_isr_handler(cac_event_t event, uint32_t clear_mask); + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* CAC Implementation. */ +const cac_api_t g_cac_on_cac = +{ + .open = R_CAC_Open, + .startMeasurement = R_CAC_StartMeasurement, + .stopMeasurement = R_CAC_StopMeasurement, + .read = R_CAC_Read, + .callbackSet = R_CAC_CallbackSet, + .close = R_CAC_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup CAC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * The Open function configures the CAC based on the provided user configuration settings. + * + * @retval FSP_SUCCESS CAC is available and available for measurement(s). + * @retval FSP_ERR_ASSERTION An argument is invalid. + * @retval FSP_ERR_ALREADY_OPEN The CAC has already been opened. + * + * @note There is only a single CAC peripheral. + **********************************************************************************************************************/ +fsp_err_t R_CAC_Open (cac_ctrl_t * const p_ctrl, cac_cfg_t const * const p_cfg) +{ + cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (CAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(CAC_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + + /* Ensure that upper limit is not less than the lower limit. If they are both the same (ie. 0) we will allow + * measurement to proceed. */ + FSP_ASSERT(p_cfg->cac_upper_limit >= p_cfg->cac_lower_limit); +#endif + + p_instance_ctrl->p_cfg = p_cfg; + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + /* Configure the CAC per the configuration. */ + r_cac_hw_configure(p_instance_ctrl); + + /* Mark driver as open by initializing it to "CAC" - its ASCII equivalent. */ + p_instance_ctrl->open = CAC_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Start the CAC measurement process. + * + * @retval FSP_SUCCESS CAC measurement started. + * @retval FSP_ERR_ASSERTION NULL provided for p_instance_ctrl or p_cfg. + * @retval FSP_ERR_NOT_OPEN R_CAC_Open() has not been successfully called. + **********************************************************************************************************************/ +fsp_err_t R_CAC_StartMeasurement (cac_ctrl_t * const p_ctrl) +{ + cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) p_ctrl; + +#if (CAC_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN((CAC_OPEN == p_instance_ctrl->open), FSP_ERR_NOT_OPEN); +#endif + + cac_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + + /* Enable the CAC interrupts and clear the status flags */ + R_CAC->CAICR = (uint8_t) (((p_cfg->mendi_irq >= 0) << CAC_PRV_CAICR_MENDIE_OFFSET) | + ((p_cfg->ovfi_irq >= 0) << CAC_PRV_CAICR_OVFIE_OFFSET) | + ((p_cfg->ferri_irq >= 0) << CAC_PRV_CAICR_FERRIE_OFFSET) | + (uint8_t) CAC_PRV_CAICR_FLAGS_CLEAR_MASK); + + /* Start CAC measurement. */ + R_CAC->CACR0 = 1U; + + /* Read CFME bit to confirm the bit value has changed. See "CAC Control Register 0 (CACR0)" description of the + * relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(R_CAC->CACR0, 1U); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stop the CAC measurement process. + * + * @retval FSP_SUCCESS CAC measuring has been stopped. + * @retval FSP_ERR_ASSERTION NULL provided for p_instance_ctrl or p_cfg. + * @retval FSP_ERR_NOT_OPEN R_CAC_Open() has not been successfully called. + **********************************************************************************************************************/ +fsp_err_t R_CAC_StopMeasurement (cac_ctrl_t * const p_ctrl) +{ +#if (CAC_CFG_PARAM_CHECKING_ENABLE == 1) + cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN((CAC_OPEN == p_instance_ctrl->open), FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Disable the CAC interrupts */ + R_CAC->CAICR = 0U; + + /* Disable measurements. */ + R_CAC->CACR0 = 0U; + + /* Read CFME bit to confirm the bit value has changed. See "CAC Control Register 0 (CACR0)" description of the relevant + * hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(R_CAC->CACR0, 0); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read and return the CAC status and counter registers. + * + * @retval FSP_SUCCESS CAC read successful. + * @retval FSP_ERR_ASSERTION An argument is NULL. + * @retval FSP_ERR_NOT_OPEN R_CAC_Open() has not been successfully called. + **********************************************************************************************************************/ +fsp_err_t R_CAC_Read (cac_ctrl_t * const p_ctrl, uint32_t * const p_counter) +{ +#if (CAC_CFG_PARAM_CHECKING_ENABLE == 1) + cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_counter); + FSP_ERROR_RETURN((CAC_OPEN == p_instance_ctrl->open), FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Read the CAC count buffer. */ + *p_counter = R_CAC->CACNTBR; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref cac_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_CAC_CallbackSet (cac_ctrl_t * const p_ctrl, + void ( * p_callback)(cac_callback_args_t *), + void * const p_context, + cac_callback_args_t * const p_callback_memory) +{ + cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) p_ctrl; + +#if CAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CAC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + cac_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif + + /* Store callback and context */ + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(cac_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Release any resources that were allocated by the Open() or any subsequent CAC operations. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION NULL provided for p_instance_ctrl or p_cfg. + * @retval FSP_ERR_NOT_OPEN R_CAC_Open() has not been successfully called. + **********************************************************************************************************************/ +fsp_err_t R_CAC_Close (cac_ctrl_t * const p_ctrl) +{ + cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) p_ctrl; +#if (CAC_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN((CAC_OPEN == p_instance_ctrl->open), FSP_ERR_NOT_OPEN); +#endif + + /* Disable measurements. */ + R_CAC->CACR0 = 0U; + + /* Disable interrupts in NVIC. */ + NVIC_DisableIRQ(p_instance_ctrl->p_cfg->ferri_irq); + NVIC_DisableIRQ(p_instance_ctrl->p_cfg->mendi_irq); + NVIC_DisableIRQ(p_instance_ctrl->p_cfg->ovfi_irq); + + /* Read CFME bit to confirm the bit value has changed. See "CAC Control Register 0 (CACR0)" description of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(R_CAC->CACR0, 0); + + /* Power down peripheral. */ + R_BSP_MODULE_STOP(FSP_IP_CAC, 0); + + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup CAC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Write the configuration to CAC registers. + * @param[in] p_instance_ctrl A pointer to the instance control structure. + **********************************************************************************************************************/ +static void r_cac_hw_configure (cac_instance_ctrl_t * const p_instance_ctrl) +{ + cac_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + + uint32_t cacr1 = 0; + uint32_t cacr2 = 0; + + /* Apply power to the peripheral */ + R_BSP_MODULE_START(FSP_IP_CAC, 0); + + /* Disable measurements. */ + R_CAC->CACR0 = 0; + + /* Read CFME bit to confirm the bit value has changed. See "CAC Control Register 0 (CACR0)" description + * of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(R_CAC->CACR0, 0); + + /* Clear interrupt status flags and disable CAC interrupts. */ + R_CAC->CAICR = CAC_PRV_CAICR_FLAGS_CLEAR_MASK; + + /* Configure measurement clock divider. */ + cacr1 |= (uint32_t) (p_instance_ctrl->p_cfg->cac_meas_clock.divider << CAC_PRV_CACR1_TCSS_OFFSET); + + if (p_cfg->cac_ref_clock.clock == CAC_CLOCK_SOURCE_EXTERNAL) + { + /* Enable CACREF. */ + cacr1 |= CAC_PRV_CACR1_CACREFE_MASK; + } + else + { + /* Configure the CAC reference clock. */ + cacr2 |= (uint32_t) (p_cfg->cac_ref_clock.clock << CAC_PRV_CACR2_RSCS_OFFSET) | + CAC_PRV_CACR2_RPS_MASK; + } + + /* Configure edge detection. */ + cacr1 |= (uint32_t) (p_cfg->cac_ref_clock.edge << CAC_PRV_CACR1_EDGES_OFFSET); + + /* Configure the digital filter. */ + cacr2 |= (uint32_t) (p_cfg->cac_ref_clock.digfilter << CAC_PRV_CACR2_DFS_OFFSET); + + /* Configure reference clock divider. */ + cacr2 |= (uint32_t) (p_cfg->cac_ref_clock.divider << CAC_PRV_CACR2_RCDS_OFFSET); + + /* Configure the measurement clock. */ + cacr1 |= (uint32_t) (p_cfg->cac_meas_clock.clock << CAC_PRV_CACR1_FMCS_OFFSET); + + if (p_cfg->mendi_irq >= 0) + { + /* Enable the measurement end interrupt. */ + R_BSP_IrqCfgEnable(p_cfg->mendi_irq, p_cfg->mendi_ipl, p_instance_ctrl); + } + + if (p_cfg->ovfi_irq >= 0) + { + /* Enable the measurement overflow interrupt. */ + R_BSP_IrqCfgEnable(p_cfg->ovfi_irq, p_cfg->ovfi_ipl, p_instance_ctrl); + } + + if (p_cfg->ferri_irq >= 0) + { + /* Enable the frequency error interrupt. */ + R_BSP_IrqCfgEnable(p_cfg->ferri_irq, p_cfg->ferri_ipl, p_instance_ctrl); + } + + /* Write settings to registers. */ + R_CAC->CACR1 = (uint8_t) cacr1; + R_CAC->CACR2 = (uint8_t) cacr2; + R_CAC->CAULVR = p_cfg->cac_upper_limit; + R_CAC->CALLVR = p_cfg->cac_lower_limit; +} + +/*******************************************************************************************************************//** + * Generic routine for handling all of the CAC interrupts. + * + * @param[in] event The event to pass into the callback args. + * @param[in] clear_mask The status bit to clear. + **********************************************************************************************************************/ +static void r_cac_isr_handler (cac_event_t event, uint32_t clear_mask) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + volatile cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if (NULL != p_instance_ctrl->p_callback) + { + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + cac_callback_args_t args; + cac_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->p_context = p_instance_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + cac_prv_ns_callback p_callback = (cac_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } + } + + /* Clear the status flag. */ + R_CAC->CAICR |= (uint8_t) clear_mask; + + R_BSP_IrqStatusClear(irq); +} + +/*******************************************************************************************************************//** + * CAC Frequency error ISR. + **********************************************************************************************************************/ +void cac_ferri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Call isr handler */ + r_cac_isr_handler(CAC_EVENT_FREQUENCY_ERROR, CAC_PRV_CAICR_FERRFCL_MASK); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * CAC Overflow ISR. + **********************************************************************************************************************/ +void cac_ovfi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Call isr handler */ + r_cac_isr_handler(CAC_EVENT_COUNTER_OVERFLOW, CAC_PRV_CAICR_OVFFCL_MASK); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * CAC Measurement Complete ISR. + **********************************************************************************************************************/ +void cac_mendi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Call isr handler */ + r_cac_isr_handler(CAC_EVENT_MEASUREMENT_COMPLETE, CAC_PRV_CAICR_MENDFCL_MASK); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_can/r_can.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_can/r_can.c new file mode 100644 index 0000000000..f818d13ac9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_can/r_can.c @@ -0,0 +1,1140 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_can.h" +#include "r_can_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define CAN_OPEN (0x5243414EU) +#define CAN_TEST_NORMAL (0U) +#define CAN_TEST_LISTEN_ONLY (3U) +#define CAN_TEST_LOOPBACK_EXTERNAL (5U) +#define CAN_TEST_LOOPBACK_INTERNAL (7U) +#define CAN_MAX_DATA_LENGTH (8) + +#if CAN_CFG_FIFO_SUPPORT + #define CAN_MAX_NO_MAILBOXES (24U) +#else + #define CAN_MAX_NO_MAILBOXES (32U) +#endif + +#define CAN_BAUD_RATE_PRESCALER_MIN (1U) +#define CAN_BAUD_RATE_PRESCALER_MAX (1024U) + +#define CAN_SID_MASK (0x000007FFU) // Maximum Standard ID +#define CAN_XID_MASK (0x1FFFFFFFU) // Maximum Extended ID +#define CAN_INVALID_MASK (0xFFFFFFFFU) // Mask used to determine invalid masks in MKRk +#define CAN_GROUP_MASK (0x0000000FU) +#define CAN_MAILBOX_GROUP_SIZE (4U) +#define CAN_DEFAULT_MASK (0x1FFFFFFFU) +#define CAN_MAILBOX_RX (0x40U) +#define CAN_MAILBOX_RX_MASK_MSGLOST (0x44U) +#define CAN_MAILBOX_TX (0x80U) +#define CAN_ERROR_MASK (0x7FU) // Ignore Error Display Mode Select Bit +#define CAN_ACCUMULATED_ERROR_CODE (0x80U) // Set Error Display Mode to Accumulated Error Code +#define CAN_ERROR_SEARCH (2U) +#define CAN_RECEIVE_SEARCH (0U) +#define CAN_TRANSMIT_SEARCH (1U) +#define CAN_RECOVERY_NORMAL (0U) +#define CAN_MAILBOX_MODE_NORMAL (0U) +#define CAN_ID_PRIORITY_TRANSMIT (0U) +#define CAN_TIMESTAMP_RESET (1U) +#define CAN_TIMESTAMP_RUNNING (0U) + +#define CAN_CHECK_MODE_MASK (0x0700U) + +#define CAN_MKIVLR_FIFO_MASK (0x00FFFFFFU) + +#define CAN_CANM_SETTING_MASK (0x03U) +#define CAN_PCLKB_RATIO (2U) // The ratio between PCLKA or ICLK and PCLKB + +#define CAN_TRANSMIT_CLEAR (0U) +#define CAN_TX_RX_INTERRUPTS_ENABLE (0xFFFFFFFFU) +#define CAN_TX_RX_INTERRUPTS_ENABLE_FIFO (0x00FFFFFFU) + +#define CAN_BAUD_RATE_PRESCALER_MASK (0x3FFU) + +#define CAN_TIMESTAMP_PRESCALER_8BITTIME (0x3) + +/* Error-Warning | Error-Passive | Bus-Off Entry | Bus-Off Recovery | Overrun */ +#define CAN_ERROR_INTERRUPTS_ENABLE (0x3EU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef enum e_can_sleep +{ + CAN_SLEEP_AWAKEN, + CAN_SLEEP_SLEEP +} can_sleep_t; + +typedef union +{ + uint32_t status; + struct st_int_status_b + { + uint32_t bus_error : 1; + uint32_t error_warning : 1; + uint32_t error_passive : 1; + uint32_t bus_off_entry : 1; + uint32_t bus_off_recovery : 1; + uint32_t receive_overrun : 1; + uint32_t overload_frame : 1; + uint32_t bus_lock : 1; + uint32_t reserved_3 : 24; + } int_status_b; +} can_error_interrrupt_status_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * can_prv_ns_callback)(can_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile can_prv_ns_callback)(can_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_can_mailbox_id_set(can_extended_cfg_t * p_extend, volatile uint32_t * p_reg, can_mailbox_t * p_id_data); +static void r_can_mailbox_read(can_instance_ctrl_t * p_ctrl, uint32_t mailbox, can_frame_t * p_frame); +static void r_can_call_callback(can_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args); +static void r_can_switch_to_operation_mode(can_instance_ctrl_t * p_ctrl, can_operation_mode_t canm_mode_setting); +static void r_can_mode_transition(can_instance_ctrl_t * p_ctrl, + can_operation_mode_t operation_mode, + can_test_mode_t test_mode); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void can_error_isr(void); +void can_rx_isr(void); +void can_tx_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* CAN function pointers */ +const can_api_t g_can_on_can = +{ + .open = R_CAN_Open, + .close = R_CAN_Close, + .write = R_CAN_Write, + .read = R_CAN_Read, + .modeTransition = R_CAN_ModeTransition, + .infoGet = R_CAN_InfoGet, + .callbackSet = R_CAN_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup CAN + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/***************************************************************************************************************//** + * Open and configure the CAN channel for operation. + * + * Example: + * @snippet r_can_example.c R_CAN_Open + * + * @retval FSP_SUCCESS Channel opened successfully + * @retval FSP_ERR_ALREADY_OPEN Driver already open. + * @retval FSP_ERR_CAN_INIT_FAILED Channel failed to initialize. + * @retval FSP_ERR_ASSERTION Null pointer presented. + *****************************************************************************************************************/ +fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_cfg) +{ + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if CAN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(NULL != p_cfg->p_bit_timing); + FSP_ASSERT(p_cfg->error_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->rx_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->tx_irq >= (IRQn_Type) 0); + + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_cfg->p_extend; + + /* Check for valid mailbox count. Must be a multiple of 4 and maximum of 32. */ + FSP_ERROR_RETURN(p_extend->mailbox_count <= CAN_MAX_NO_MAILBOXES, FSP_ERR_CAN_INIT_FAILED); + FSP_ERROR_RETURN((p_extend->mailbox_count % CAN_MAILBOX_GROUP_SIZE) == 0, FSP_ERR_CAN_INIT_FAILED); + + /* Check control block isn't already open */ + FSP_ERROR_RETURN(p_ctrl->open != CAN_OPEN, FSP_ERR_ALREADY_OPEN); + + for (uint32_t i = 0U; i < (p_extend->mailbox_count / CAN_MAILBOX_GROUP_SIZE); i++) + { + FSP_ERROR_RETURN(p_extend->p_mailbox_mask[i] <= CAN_DEFAULT_MASK, FSP_ERR_CAN_INIT_FAILED); + } + + /* Check the bit timing settings are within range. */ + /* Check baud Rate Pre-scaler. */ + FSP_ERROR_RETURN(p_cfg->p_bit_timing->baud_rate_prescaler <= CAN_BAUD_RATE_PRESCALER_MAX, FSP_ERR_CAN_INIT_FAILED); + FSP_ERROR_RETURN(p_cfg->p_bit_timing->baud_rate_prescaler >= CAN_BAUD_RATE_PRESCALER_MIN, FSP_ERR_CAN_INIT_FAILED); + + /* 'Setting of TSEG1 and TSEG2: TSEG1 > TSEG2 > SJW' as described in hardware manual (See "Bit Timing Setting" + * in the Data Transfer Rate Configuration section of the relevant hardware manual). */ + + /* Check Time Segment 1 is greater than Time Segment 2. */ + FSP_ERROR_RETURN((uint32_t) p_cfg->p_bit_timing->time_segment_1 > (uint32_t) p_cfg->p_bit_timing->time_segment_2, + FSP_ERR_CAN_INIT_FAILED); + + /* Check Time Segment 2 is greater than or equal to the synchronization jump width */ + FSP_ERROR_RETURN( + (uint32_t) p_cfg->p_bit_timing->time_segment_2 >= (uint32_t) p_cfg->p_bit_timing->synchronization_jump_width, + FSP_ERR_CAN_INIT_FAILED); + + /* Get the frequency of pclkb for later validation */ + uint32_t pclkb_frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + #if BSP_FEATURE_CAN_CHECK_PCLKB_RATIO_FLAG + + /* Check the hardware manual usage note requirements are met. */ + uint32_t pclka_iclk_frequency = 0U; + + /* 'The clock frequency ratio of ICLK and PCLKB must be 2:1' - See "Settings for the Operating Clock" in the CAN Usage notes of the relevant hardware manual. */ + /* 'The clock frequency ratio of PCLKA and PCLKB must be 2:1' - See "Settings for the Operating Clock" in the CAN Usage notes of the relevant hardware manual. */ + + /* Get the other clock defined by the hardware manual from the bsp and verify there is a 2:1 ratio */ + pclka_iclk_frequency = R_FSP_SystemClockHzGet(BSP_FEATURE_CAN_CLOCK); + FSP_ERROR_RETURN((pclka_iclk_frequency / pclkb_frequency) == CAN_PCLKB_RATIO, FSP_ERR_CAN_INIT_FAILED); + #endif + #if BSP_FEATURE_CAN_MCLOCK_ONLY + FSP_ERROR_RETURN(CAN_CLOCK_SOURCE_CANMCLK == ((can_extended_cfg_t *) p_cfg->p_extend)->clock_source, + FSP_ERR_CAN_INIT_FAILED); + #endif + + /* If the device is configured for CANMCLK or supports only CANMCLK */ + if (CAN_CLOCK_SOURCE_CANMCLK == ((can_extended_cfg_t *) p_cfg->p_extend)->clock_source) + { + /* 'fPCLKB >= fCANMCLK' - See "Settings for the Operating Clock" in the CAN Usage notes section of the relevant hardware manual. */ + FSP_ERROR_RETURN(pclkb_frequency >= (BSP_CFG_XTAL_HZ), FSP_ERR_CAN_INIT_FAILED); + } + + #if BSP_FEATURE_CGC_HAS_PLL + else + { + /* Otherwise the device is configured for PCLKB. Verify the source clock is the PLL */ + /* See "Clock Setting" in the Data Transfer Rate Configuration section of the relevant hardware manual. */ + FSP_ERROR_RETURN(R_SYSTEM->SCKSCR == BSP_CLOCKS_SOURCE_CLOCK_PLL, FSP_ERR_CAN_INIT_FAILED); + } + #endif +#else + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_cfg->p_extend; +#endif + + R_CAN0_Type * p_reg = + (R_CAN0_Type *) ((uint32_t) R_CAN0 + (p_cfg->channel * ((uint32_t) R_CAN1 - (uint32_t) R_CAN0))); + p_ctrl->p_reg = p_reg; + + R_BSP_MODULE_START(FSP_IP_CAN, p_cfg->channel); + + /* Initialize the control block */ + p_ctrl->p_cfg = p_cfg; + + /* Set callback and context pointers, if configured */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Set the clock source to the user configured source. */ + p_ctrl->clock_source = p_extend->clock_source; + + r_can_mode_transition(p_ctrl, CAN_OPERATION_MODE_RESET, CAN_TEST_MODE_DISABLED); + + /* Set up control register fields in reset mode as described in the hardware manual. + * (See Note 1 of "Control Register (CTLR)" description in the CAN section of the relevant hardware manual) + * + * MBM: Select requested mailbox mode + * Select ID mode. Standard or extended + * Select message overwrite or overrun mode + * TPM: ID priority mode + * Set time stamp, Time Stamp Pre Scaler: Update every 8 bit times + * BOM: Bus Off recovery mode acc. to IEC11898-1 + * Retain awaken state and reset mode + */ + p_reg->CTLR = (uint16_t) ((CAN_CFG_FIFO_SUPPORT << R_CAN0_CTLR_MBM_Pos) | + (p_extend->global_id_mode << R_CAN0_CTLR_IDFM_Pos) | + (p_extend->message_mode << R_CAN0_CTLR_MLM_Pos) | + (CAN_TIMESTAMP_PRESCALER_8BITTIME << R_CAN0_CTLR_TSPS_Pos) | + (CAN_OPERATION_MODE_RESET << R_CAN0_CTLR_CANM_Pos)); + + /* Set timing bits */ + can_bit_timing_cfg_t * p_bit_timing = p_cfg->p_bit_timing; + p_reg->BCR = + (uint32_t) (((p_bit_timing->baud_rate_prescaler - 1) & CAN_BAUD_RATE_PRESCALER_MASK) << R_CAN0_BCR_BRP_Pos) | + ((p_bit_timing->time_segment_1 - 1U) << R_CAN0_BCR_TSEG1_Pos) | + ((p_bit_timing->time_segment_2 - 1U) << R_CAN0_BCR_TSEG2_Pos) | + (uint32_t) ((p_bit_timing->synchronization_jump_width - 1U) << R_CAN0_BCR_SJW_Pos) | + (uint32_t) (p_ctrl->clock_source << R_CAN0_BCR_CCLKS_Pos); + + /* Enter Halt mode */ + r_can_mode_transition(p_ctrl, CAN_OPERATION_MODE_HALT, CAN_TEST_MODE_DISABLED); + + /* Set Error Display mode in Halt mode. */ + p_reg->ECSR = CAN_ACCUMULATED_ERROR_CODE; + + /* Configure mailboxes. */ + + /* Clear all mailboxes in Halt mode (FIFO mailboxes are cleared automatically). */ + memset((void *) p_reg->MB, 0, sizeof(R_CAN0_MB_Type) * CAN_MAX_NO_MAILBOXES); + + /* Set the direction and ID (if applicable) for each mailbox. */ + for (uint32_t i = 0U; i < CAN_MAX_NO_MAILBOXES; i++) + { + uint8_t mctl; + + if ((CAN_MAILBOX_RECEIVE == (p_extend->p_mailbox[i].mailbox_type)) && (i < p_extend->mailbox_count)) + { + r_can_mailbox_id_set(p_extend, &p_reg->MB[i].ID, &p_extend->p_mailbox[i]); + + /* Configure mailbox for receive */ + mctl = CAN_MAILBOX_RX; + } + else + { + /* Clear NEWDATA if set */ + mctl = 0U; + } + + /* Configure mailbox for transmit or receive (MCTL_RX and MCTL_TX are the same array) */ + p_reg->MCTL_RX[i] = mctl; + } + + /* Set all masks to disabled. */ + uint32_t mask_enabled = 0; + + /* Set the masks for each mailbox group and initialize the mask invalid register. */ + for (uint32_t i = 0; i < p_extend->mailbox_count / CAN_MAILBOX_GROUP_SIZE; i++) + { + /* If the user has defined a mask */ + if (p_extend->p_mailbox_mask[i] < CAN_DEFAULT_MASK) + { + uint32_t mask = p_extend->p_mailbox_mask[i]; + + /* In Mixed ID mode the Standard ID mask (SID) is the upper 11 bits of the full Extended ID (SID+XID) */ + if (CAN_GLOBAL_ID_MODE_STANDARD == p_extend->global_id_mode) + { + /* Set standard ID mask. Set unused bits low */ + mask = (mask & CAN_SID_MASK) << R_CAN0_MB_ID_SID_Pos; + } + + p_reg->MKR[i] = mask; + + /* Enable the mask for this group */ + mask_enabled |= CAN_GROUP_MASK << (i << 2); + } + } + +#if CAN_CFG_FIFO_SUPPORT + + /* Set the Mask as invalid for mailboxes that do not use the mask. + * Bits 24:31 in MKIVLR must not be set in FIFO mode (See "Mask Invalid Register (MKIVLR)" description in the CAN section of the relevant hardware manual). */ + p_reg->MKIVLR = ~(mask_enabled) & CAN_MKIVLR_FIFO_MASK; + + /* Get pointer to RX FIFO configuration */ + can_rx_fifo_cfg_t * p_rx_fifo_cfg = p_extend->p_rx_fifo_cfg; + + /* Set RX FIFO ID and mask registers */ + r_can_mailbox_id_set(p_extend, &p_reg->FIDCR[0], &p_rx_fifo_cfg->rx_fifo_id1); + r_can_mailbox_id_set(p_extend, &p_reg->FIDCR[1], &p_rx_fifo_cfg->rx_fifo_id2); + + uint32_t mask1 = p_rx_fifo_cfg->rx_fifo_mask1; + uint32_t mask2 = p_rx_fifo_cfg->rx_fifo_mask2; + + /* In Mixed ID mode the Standard ID mask (SID) is the upper 11 bits of the full Extended ID (SID+XID) */ + if (CAN_GLOBAL_ID_MODE_STANDARD == p_extend->global_id_mode) + { + /* Set standard ID mask. Set unused bits low */ + mask1 = (mask1 & CAN_SID_MASK) << R_CAN0_MB_ID_SID_Pos; + mask2 = (mask2 & CAN_SID_MASK) << R_CAN0_MB_ID_SID_Pos; + } + + p_reg->MKR[6] = mask1; + p_reg->MKR[7] = mask2; +#else + + /* Set the Mask as invalid for mailboxes that do not use the mask. */ + p_reg->MKIVLR = ~(mask_enabled); +#endif + + /* Go to normal operation. */ + r_can_mode_transition(p_ctrl, CAN_OPERATION_MODE_NORMAL, CAN_TEST_MODE_DISABLED); + + /* Time Stamp Counter reset. Set the TSRC bit to 1 in CAN Operation mode. */ + + /* 'Set the TSRC bit to 1 in CAN operation mode.' (See 'Note 4' of "Control Register (CTLR)" description in the CAN section of the relevant hardware manual). */ + p_reg->CTLR_b.TSRC = CAN_TIMESTAMP_RESET; /* Set Timestamp counter reset command */ + FSP_HARDWARE_REGISTER_WAIT(p_reg->CTLR_b.TSRC, !CAN_TIMESTAMP_RESET); + + /* If successful, Lookup and store IRQ numbers. Enable interrupts. */ + R_BSP_IrqCfgEnable(p_cfg->error_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->rx_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->tx_irq, p_cfg->ipl, p_ctrl); + + /* Error-Warning | Error-Passive | Bus-Off Entry | Bus-Off Recovery | Overrun */ + p_reg->EIER = CAN_ERROR_INTERRUPTS_ENABLE; + +#if CAN_CFG_FIFO_SUPPORT + + /* Get pointer to FIFO interrupt config */ + can_fifo_interrupt_cfg_t const * p_fifo_int_cfg = p_extend->p_fifo_int_cfg; + + /* Enable interrupts */ + R_BSP_IrqCfgEnable(p_fifo_int_cfg->rx_fifo_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_fifo_int_cfg->tx_fifo_irq, p_cfg->ipl, p_ctrl); + + /* Set FIFO interrupt mode and enable mailbox interrupts */ + p_reg->MIER = p_fifo_int_cfg->fifo_int_mode | CAN_TX_RX_INTERRUPTS_ENABLE_FIFO; + + /* Set FIFO enable bits */ + p_reg->TFCR = 1U; + p_reg->RFCR = 1U; +#else + + /* Set interrupt enable bits */ + p_reg->MIER = CAN_TX_RX_INTERRUPTS_ENABLE; +#endif + + /* If successful, Mark the control block as open */ + p_ctrl->open = CAN_OPEN; + + return err; +} + +/***************************************************************************************************************//** + * Close the CAN channel. + * @retval FSP_SUCCESS Channel closed successfully. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented. + *****************************************************************************************************************/ +fsp_err_t R_CAN_Close (can_ctrl_t * const p_api_ctrl) +{ + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) p_api_ctrl; + +#if CAN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == CAN_OPEN, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->open = 0U; + + R_BSP_IrqDisable(p_ctrl->p_cfg->error_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->rx_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tx_irq); + +#if CAN_CFG_FIFO_SUPPORT + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + can_fifo_interrupt_cfg_t const * p_fifo_int_cfg = p_extend->p_fifo_int_cfg; + R_BSP_IrqDisable(p_fifo_int_cfg->rx_fifo_irq); + R_BSP_IrqDisable(p_fifo_int_cfg->tx_fifo_irq); +#endif + + R_CAN0_Type * p_reg = p_ctrl->p_reg; + +#if CAN_CFG_FIFO_SUPPORT + + /* Clear FIFO enable bits */ + p_reg->TFCR = 0U; + p_reg->RFCR = 0U; +#endif + + /* Clear interrupt enable bits */ + p_reg->EIER = 0U; + p_reg->MIER = 0U; + + R_BSP_MODULE_STOP(FSP_IP_CAN, p_ctrl->p_cfg->channel); + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Write data to the CAN channel. Write up to eight bytes to the channel mailbox. + * + * Example: + * @snippet r_can_example.c R_CAN_Write + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_CAN_TRANSMIT_NOT_READY Transmit in progress, cannot write data at this time. + * @retval FSP_ERR_CAN_TRANSMIT_FIFO_FULL Transmit FIFO is full. + * @retval FSP_ERR_CAN_RECEIVE_MAILBOX Mailbox is setup for receive and cannot send. + * @retval FSP_ERR_INVALID_ARGUMENT Data length or frame type invalid. + * @retval FSP_ERR_ASSERTION Null pointer presented + *****************************************************************************************************************/ +fsp_err_t R_CAN_Write (can_ctrl_t * const p_api_ctrl, uint32_t mailbox, can_frame_t * const p_frame) +{ + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) p_api_ctrl; + +#if CAN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_frame); + FSP_ERROR_RETURN(p_ctrl->open == CAN_OPEN, FSP_ERR_NOT_OPEN); + + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + #if CAN_CFG_FIFO_SUPPORT + FSP_ERROR_RETURN(mailbox < p_extend->mailbox_count || (mailbox == CAN_MAILBOX_ID_TX_FIFO), + FSP_ERR_INVALID_ARGUMENT); + #else + FSP_ERROR_RETURN(mailbox < p_extend->mailbox_count, FSP_ERR_INVALID_ARGUMENT); + #endif + + R_CAN0_Type * p_reg = p_ctrl->p_reg; + FSP_ERROR_RETURN(1U != p_reg->MCTL_TX_b[mailbox].RECREQ, FSP_ERR_CAN_RECEIVE_MAILBOX); + + FSP_ERROR_RETURN((p_frame->data_length_code <= CAN_MAX_DATA_LENGTH), FSP_ERR_INVALID_ARGUMENT); +#else + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + R_CAN0_Type * p_reg = p_ctrl->p_reg; +#endif + +#if CAN_CFG_FIFO_SUPPORT + if (CAN_MAILBOX_ID_TX_FIFO == mailbox) + { + /* Check if FIFO is full */ + FSP_ERROR_RETURN(1U != p_reg->TFCR_b.TFFST, FSP_ERR_CAN_TRANSMIT_FIFO_FULL); + } + else +#endif + { + /* Check if MB is ready */ + FSP_ERROR_RETURN(0U == p_reg->MCTL_TX_b[mailbox].TRMREQ, FSP_ERR_CAN_TRANSMIT_NOT_READY); + } + + /* Setup the frame to be transmitted. */ + + /* Set the ID register */ + r_can_mailbox_id_set(p_extend, &p_reg->MB[mailbox].ID, (can_mailbox_t *) p_frame); + + /* Put mailbox data length code */ + p_reg->MB[mailbox].DL_b.DLC = (p_frame->data_length_code & 0x0FU); + + /* Put mailbox data. */ + uint32_t len = p_frame->data_length_code; + uint8_t * p_dest = (uint8_t *) p_reg->MB[mailbox].D; + uint8_t * p_src = p_frame->data; + while (len--) + { + *p_dest++ = *p_src++; + } + +#if CAN_CFG_FIFO_SUPPORT + if (CAN_MAILBOX_ID_TX_FIFO == mailbox) + { + /* Increment the FIFO pointer */ + p_reg->TFPCR = UINT8_MAX; + } + else +#endif + { + /* Transmit the frame */ + p_reg->MCTL_TX[mailbox] = CAN_MAILBOX_TX; + } + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Read data from a mailbox or FIFO. + * + * @note This function is not supported. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported. + *****************************************************************************************************************/ +fsp_err_t R_CAN_Read (can_ctrl_t * const p_api_ctrl, uint32_t mailbox, can_frame_t * const p_frame) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(mailbox); + FSP_PARAMETER_NOT_USED(p_frame); + + /* Normal mailbox mode is interrupt-driven only. */ + return FSP_ERR_UNSUPPORTED; +} + +/***************************************************************************************************************//** + * CAN Mode Transition is used to change CAN driver state. + * + * Example: + * @snippet r_can_example.c R_CAN_ModeTransition + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented + *****************************************************************************************************************/ +fsp_err_t R_CAN_ModeTransition (can_ctrl_t * const p_api_ctrl, + can_operation_mode_t operation_mode, + can_test_mode_t test_mode) +{ + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; +#if CAN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == CAN_OPEN, FSP_ERR_NOT_OPEN); +#endif + + r_can_mode_transition(p_ctrl, operation_mode, test_mode); + + return err; +} + +/***************************************************************************************************************//** + * Get CAN state and status information for the channel. + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented + *****************************************************************************************************************/ +fsp_err_t R_CAN_InfoGet (can_ctrl_t * const p_api_ctrl, can_info_t * const p_info) +{ + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) p_api_ctrl; + +#if CAN_CFG_PARAM_CHECKING_ENABLE + + /* Check pointers for NULL values */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_info); + + /* If channel is not open, return an error */ + FSP_ERROR_RETURN(p_ctrl->open == CAN_OPEN, FSP_ERR_NOT_OPEN); +#endif + + R_CAN0_Type * p_reg = p_ctrl->p_reg; + + p_info->status = (can_status_t) p_reg->STR; // Status register value + p_info->error_count_receive = p_reg->RECR; // Report receive error count + p_info->error_count_transmit = p_reg->TECR; // Report transmit error count + p_info->error_code = (can_error_t) p_reg->ECSR & CAN_ERROR_MASK; // Report error code + + /* Since the error flags were read, we clear them to ensure that we won't read them again + * Because register is volatile, we clear only the flags that we already read. Preserve the value + * of EDPM bit. Clear error bits by writing 0 to bits that were found to be 1 + */ + p_reg->ECSR = (uint8_t) (p_info->error_code) ^ CAN_ERROR_MASK; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref can_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_CAN_CallbackSet (can_ctrl_t * const p_api_ctrl, + void ( * p_callback)(can_callback_args_t *), + void * const p_context, + can_callback_args_t * const p_callback_memory) +{ + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) p_api_ctrl; + +#if CAN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CAN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CAN_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + can_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(can_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup CAN) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Sets the ID register for a mailbox or FIFO. + * + * @param[in] p_extend Pointer to CAN extended config + * @param[in] p_reg Pointer to target ID register + * @param[in] p_id_data Pointer to ID settings + **********************************************************************************************************************/ +static void r_can_mailbox_id_set (can_extended_cfg_t * p_extend, volatile uint32_t * p_reg, can_mailbox_t * p_id_data) +{ + can_global_id_mode_t global_mode = p_extend->global_id_mode; + + uint32_t ide = 0U; + uint32_t id; + + if ((CAN_GLOBAL_ID_MODE_STANDARD == global_mode) || + ((global_mode == CAN_GLOBAL_ID_MODE_MIXED) && (p_id_data->id_mode == CAN_ID_MODE_STANDARD))) + { + id = (uint32_t) ((p_id_data->mailbox_id & CAN_SID_MASK) << R_CAN0_MB_ID_SID_Pos); + } + else + { + if ((global_mode == CAN_GLOBAL_ID_MODE_MIXED) && (p_id_data->id_mode == CAN_ID_MODE_EXTENDED)) + { + /* The IDE bit is only set when configuring an extended ID mailbox in Mixed ID mode. */ + ide = R_CAN0_MB_ID_IDE_Msk; + } + + id = p_id_data->mailbox_id & CAN_XID_MASK; + } + + uint32_t frame_type = (uint32_t) (p_id_data->frame_type << R_CAN0_MB_ID_RTR_Pos); + + *p_reg = (ide | frame_type | id); +} + +/*******************************************************************************************************************//** + * Read a mailbox or FIFO. + * + * @param[in] p_ctrl Pointer to CAN control struct + * @param[in] mailbox CAN mailbox ID + * @param[in] p_frame Pointer to destination frame + **********************************************************************************************************************/ +static inline void r_can_mailbox_read (can_instance_ctrl_t * p_ctrl, uint32_t mailbox, can_frame_t * p_frame) +{ + volatile R_CAN0_Type * p_reg = p_ctrl->p_reg; + + /* Get frame ID. */ + uint32_t mbox_id = p_reg->MB[mailbox].ID; + + /* Get the frame type */ + p_frame->type = (can_frame_type_t) ((mbox_id & R_CAN0_MB_ID_RTR_Msk) >> R_CAN0_MB_ID_RTR_Pos); + + /* Get the ID mode */ + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + p_frame->id_mode = (can_id_mode_t) ((p_extend->global_id_mode | p_reg->MB[mailbox].ID_b.IDE) & 1); + + /* Get the ID based on the mode */ + if (CAN_ID_MODE_STANDARD == p_frame->id_mode) + { + p_frame->id = (mbox_id & R_CAN0_MB_ID_SID_Msk) >> R_CAN0_MB_ID_SID_Pos; + } + else + { + p_frame->id = mbox_id & (R_CAN0_MB_ID_SID_Msk | R_CAN0_MB_ID_EID_Msk); + } + + /* Get the frame data length code */ + p_frame->data_length_code = p_reg->MB[mailbox].DL_b.DLC; + + /* See Note 1 about DLC[3:0] of + * "Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31; m = 0 to 7)" + * in the CAN section of the relevant hardware manual. */ + if (p_frame->data_length_code > CAN_MAX_DATA_LENGTH) + { + p_frame->data_length_code = CAN_MAX_DATA_LENGTH; + } + + /* Be sure to check data_length_code in calling function */ + for (uint32_t i = 0U; i < p_frame->data_length_code; i++) + { + p_frame->data[i] = p_reg->MB[mailbox].D[i]; // Copy receive data to buffer + } + +#if CAN_CFG_FIFO_SUPPORT + if (CAN_MAILBOX_ID_RX_FIFO == mailbox) + { + /* Increment receive FIFO pointer */ + p_reg->RFPCR = UINT8_MAX; + } + else +#endif + { + /* Clear rx data flag. Do not modify message-lost flag as this keeps track of + * error interrupts to be fired. + * This flag will be cleared in the error isr. + * Message Lost flag is written as 1 as that has no effect on this bit. + * See 'Note 1. Write 0 only. Writing 1 has no effect.' of + * "Message Control Register for Receive (MCTL_RXj) (j = 0 to 31)" + * in the CAN section of the relevant hardware manual. + */ + p_reg->MCTL_RX[mailbox] = CAN_MAILBOX_RX_MASK_MSGLOST; + } + + p_frame->options = 0; +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to CAN instance control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void r_can_call_callback (can_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args) +{ + can_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + can_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + can_prv_ns_callback p_callback = (can_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Error ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common error function, and restores context if RTOS is used. + **********************************************************************************************************************/ +void can_error_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear interrupt */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + can_callback_args_t args = {0U}; + uint32_t mailbox = 0U; + + R_CAN0_Type * p_reg = p_ctrl->p_reg; + + /* Get source of error interrupt. */ + args.event = (can_event_t) p_reg->EIFR; // Read Error Interrupt Factor Judge register + + p_reg->EIFR = 0x00U; // Clear Error Interrupt Factor Judge register + + /* Although NMLST detects both Overwrite and Overrun conditions, + * in such a scenario this interrupt is fired only when the peripheral is in the overrun mode + * (Either on its own or manually by setting NVIC_SetPendingIRQ below). + * The receive_overrun bit may not be checked here. + */ + if (p_reg->STR_b.NMLST) + { + args.event |= CAN_EVENT_MAILBOX_MESSAGE_LOST; + uint8_t saved_msmr = p_reg->MSMR; // Save the current MSMR value + p_reg->MSMR = CAN_ERROR_SEARCH; // search for lowest numbered mailbox with message lost + mailbox = p_reg->MSSR_b.MBNST; // get mailbox number + p_reg->MSMR = saved_msmr; // Restore the previous MSMR value + p_reg->MCTL_RX_b[mailbox].MSGLOST = 0U; // Clear the error so that NMLST is not set again for an already handled error. + } + + args.channel = p_ctrl->p_cfg->channel; + args.p_context = p_ctrl->p_context; + args.mailbox = mailbox; + r_can_call_callback(p_ctrl, &args); + + /* Get extended config */ + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Check for mailboxes with data loss due to overrun, + * if true, fire this interrupt again. + * Do not re-trigger this interrupt due to message loss in overwrite mode. + */ + if (p_reg->STR_b.NMLST && (CAN_MESSAGE_MODE_OVERWRITE != p_extend->message_mode)) + { + NVIC_SetPendingIRQ(p_ctrl->p_cfg->error_irq); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Receive ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common receive function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void can_rx_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear interrupt */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + can_callback_args_t args; + uint32_t mailbox; + + args.event = CAN_EVENT_RX_COMPLETE; + + R_CAN0_Type * p_reg = p_ctrl->p_reg; + +#if CAN_CFG_FIFO_SUPPORT + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + can_fifo_interrupt_cfg_t const * p_fifo_int_cfg = p_extend->p_fifo_int_cfg; + if (irq == p_fifo_int_cfg->rx_fifo_irq) + { + /* Set the mailbox number to 28 (RX FIFO). */ + mailbox = CAN_MAILBOX_ID_RX_FIFO; + + uint8_t rfcr = p_reg->RFCR; + if (rfcr & R_CAN0_RFCR_RFMLF_Msk) + { + /* Clear the Receive FIFO Message Lost Flag if set (See "Receive FIFO Pointer Control + * Register (RFPCR)" description in the CAN section of the relevant hardware manual). */ + p_reg->RFCR_b.RFMLF = 0; + + /* Add a FIFO message lost flag to the event */ + args.event |= CAN_EVENT_FIFO_MESSAGE_LOST; + } + } + else +#endif + { + uint8_t saved_msmr = p_reg->MSMR; // Save the current MSMR value + p_reg->MSMR = CAN_RECEIVE_SEARCH; // search for lowest numbered &mailbox with message received + mailbox = p_reg->MSSR_b.MBNST; // get mailbox number + p_reg->MSMR = saved_msmr; // Restore the previous MSMR value + } + + /* Read frame to args */ + r_can_mailbox_read(p_ctrl, mailbox, &args.frame); + + /* Save the receive mailbox number. */ + args.mailbox = mailbox; + + args.channel = p_ctrl->p_cfg->channel; + args.p_context = p_ctrl->p_context; + r_can_call_callback(p_ctrl, &args); + +#if CAN_CFG_FIFO_SUPPORT + if (irq == p_fifo_int_cfg->rx_fifo_irq) + { + if (!p_reg->RFCR_b.RFEST) + { + /* Reset FIFO IRQ if the FIFO is not empty. */ + NVIC_SetPendingIRQ(irq); + } + } + else +#endif + { + if (p_reg->STR_b.NDST) + { + /* Reset MB IRQ if another MB has requested it. */ + NVIC_SetPendingIRQ(irq); + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Transmit ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common transmit function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void can_tx_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear interrupt */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + can_callback_args_t args; + args.event = (can_event_t) 0; + + R_CAN0_Type * p_reg = p_ctrl->p_reg; + +#if CAN_CFG_FIFO_SUPPORT + can_extended_cfg_t * p_extend = (can_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + can_fifo_interrupt_cfg_t const * p_fifo_int_cfg = p_extend->p_fifo_int_cfg; + + if (irq == p_fifo_int_cfg->tx_fifo_irq) + { + /* Set the mailbox number to 24 (TX FIFO). */ + args.mailbox = CAN_MAILBOX_ID_TX_FIFO; + + if (p_fifo_int_cfg->fifo_int_mode & R_CAN0_MIER_FIFO_MB25_Msk) + { + /* When MB25 is set the TX FIFO ISR only fires when the last message has been transmitted. */ + args.event = CAN_EVENT_TX_FIFO_EMPTY; + } + } + else +#endif + { + uint8_t saved_msmr = p_reg->MSMR; // Save the current MSMR value + p_reg->MSMR = CAN_TRANSMIT_SEARCH; // search for lowest numbered &mailbox with message transmitted + uint32_t mailbox = p_reg->MSSR_b.MBNST; // get mailbox number + p_reg->MSMR = saved_msmr; // Restore the previous MSMR value + + /* Clear SENTDATA. + * Do a byte-write to avoid read-modify-write with HW writing another bit in between. + * TRMREQ must be set to 0 (or will send again). + * Do it twice since bits SENTDATA and TRMREQ cannot be set to 0 simultaneously + * See "Message Control Register for Transmit (MCTL_TXj) (j = 0 to 31)" + * under "SENTDATA flag (Transmission Complete Flag)" in the CAN section of the relevant hardware manual. + */ + p_reg->MCTL_TX[mailbox] = CAN_TRANSMIT_CLEAR; + p_reg->MCTL_TX[mailbox] = CAN_TRANSMIT_CLEAR; // Clear SENTDATA and TRMREQ. + + /* Save the transmit mailbox number. */ + args.mailbox = mailbox; + } + + /* Set event argument to transmit complete. */ + args.event |= CAN_EVENT_TX_COMPLETE; + + args.channel = p_ctrl->p_cfg->channel; + args.p_context = p_ctrl->p_context; + r_can_call_callback(p_ctrl, &args); + + /* Check for other mailboxes with pending transmit complete flags. */ +#if CAN_CFG_FIFO_SUPPORT + if ((irq != p_fifo_int_cfg->tx_fifo_irq) && p_reg->STR_b.SDST) +#else + if (p_reg->STR_b.SDST) +#endif + { + NVIC_SetPendingIRQ(p_ctrl->p_cfg->tx_irq); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * This function is used to switch the CAN peripheral operation and test modes. + * @param[in] p_ctrl - pointer to control structure + * @param[in] operation_mode - destination operation mode + * @param[in] test_mode - destination test mode + **********************************************************************************************************************/ +static void r_can_mode_transition (can_instance_ctrl_t * p_ctrl, + can_operation_mode_t operation_mode, + can_test_mode_t test_mode) +{ + R_CAN0_Type * p_reg = p_ctrl->p_reg; + + if (p_ctrl->test_mode != test_mode) + { + /* Switch to halt mode */ + r_can_switch_to_operation_mode(p_ctrl, CAN_OPERATION_MODE_HALT); + + /* 'Write to TCR in CAN halt mode only.' (See "Test Control Register (TCR)" description in the CAN section of the relevant hardware manual). */ + p_reg->TCR = (uint8_t) test_mode; /* Destination test mode */ + + /* Set current test mode. */ + p_ctrl->test_mode = test_mode; + p_ctrl->operation_mode = CAN_OPERATION_MODE_HALT; + } + + if (p_ctrl->operation_mode != operation_mode) + { + if (CAN_OPERATION_MODE_SLEEP == operation_mode) + { + r_can_switch_to_operation_mode(p_ctrl, CAN_OPERATION_MODE_HALT); + + /* 'Write to the SLPM bit in CAN reset mode and CAN halt mode.' + * See "CAN Sleep Mode" in the CAN Operation Modes section of the relevant hardware manual + */ + p_reg->CTLR_b.SLPM = CAN_SLEEP_SLEEP; + FSP_HARDWARE_REGISTER_WAIT(p_reg->STR_b.SLPST, 1U); + } + else + { + r_can_switch_to_operation_mode(p_ctrl, operation_mode); + } + + /* Set current test mode. */ + p_ctrl->operation_mode = operation_mode; + } +} + +/*******************************************************************************************************************//** + * This function causes the CAN peripheral to transition to operation mode + * @param[in] p_ctrl - pointer to control structure + * @param[in] canm_mode_setting - destination CAN mode + **********************************************************************************************************************/ +static void r_can_switch_to_operation_mode (can_instance_ctrl_t * p_ctrl, can_operation_mode_t canm_mode_setting) +{ + R_CAN0_Type * p_reg = p_ctrl->p_reg; + + p_reg->CTLR_b.SLPM = CAN_SLEEP_AWAKEN; + p_reg->CTLR_b.CANM = (uint16_t) (canm_mode_setting & CAN_CANM_SETTING_MASK); + + /* See "Control Register (CTLR)" description in the CAN section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT((p_reg->STR & CAN_CHECK_MODE_MASK), + (uint32_t) ((uint8_t) canm_mode_setting << R_CAN0_CTLR_CANM_Pos)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_canfd/r_canfd.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_canfd/r_canfd.c new file mode 100644 index 0000000000..23e5de6843 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_canfd/r_canfd.c @@ -0,0 +1,1659 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_canfd.h" +#include "r_canfd_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define CANFD_OPEN (0x52434644U) // "RCFD" in ASCII + +#define CANFD_BAUD_RATE_PRESCALER_MIN (1U) +#define CANFD_BAUD_RATE_PRESCALER_MAX (1024U) + +#define CANFD_PRV_CTR_MODE_MASK (R_CANFD_CFDGCTR_GSLPR_Msk + R_CANFD_CFDGCTR_GMDC_Msk) +#define CANFD_PRV_CTR_RESET_BIT (1U) +#define CANFD_PRV_RXMB_MAX (32U) +#define CANFD_PRV_TXMB_OFFSET (32U) +#define CANFD_PRV_TXMB_CHANNEL_OFFSET (64U) +#define CANFD_PRV_STANDARD_ID_MAX (0x7FFU) + +/** Whether or not the peripheral contains CFDCFTISTS and CFDCFRISTS registers. */ +#define CANFD_PRV_CFIFO_HAS_ISTS (!(BSP_FEATURE_CANFD_LITE && BSP_FEATURE_CANFD_NUM_CHANNELS == 1)) + +#if BSP_FEATURE_CANFD_LITE + #define CANFD_PRV_CFIFO_CHANNEL_OFFSET (1U) + + #define R_CANFD_CFDRM_RM_TYPE R_CANFD_CFDRM_RM_Type + + #define CANFD_PRV_RXMB_PTR(buffer) ((volatile R_CANFD_CFDRM_RM_TYPE *) &p_reg->CFDRM[buffer >> 3].RM[buffer & 7U]) + #define CANFD_PRV_RX_FIFO_MAX (2U) + #define CANFD_PRV_COMMON_FIFO_MAX (1U) + #define CANFD_PRV_CFDTMIEC_LENGTH (1) + #define CANFD_PRV_RMID_POSITION (R_CANFD_CFDRM_RM_ID_RMID_Pos) + #define CANFD_PRV_RMID_MASK (R_CANFD_CFDRM_RM_ID_RMID_Msk) + #define CANFD_PRV_RMRTR_POSITION (R_CANFD_CFDRM_RM_ID_RMRTR_Pos) + #define CANFD_PRV_RMRTR_MASK (R_CANFD_CFDRM_RM_ID_RMRTR_Msk) + #define CANFD_PRV_RMIDE_POSITION (R_CANFD_CFDRM_RM_ID_RMIDE_Pos) + #define CANFD_PRV_RMIDE_MASK (R_CANFD_CFDRM_RM_ID_RMIDE_Msk) + #define CANFD_PRV_RMDLC_POSITION (R_CANFD_CFDRM_RM_PTR_RMDLC_Pos) + #define CANFD_PRV_RMDLC_MASK (R_CANFD_CFDRM_RM_PTR_RMDLC_Msk) +#else + #define CANFD_PRV_CFIFO_CHANNEL_OFFSET (3U) + + #define R_CANFD_CFDRM_RM_TYPE R_CANFD_CFDRM_Type + + #define CANFD_PRV_RXMB_PTR(buffer) (&p_reg->CFDRM[buffer]) + #define CANFD_PRV_RX_FIFO_MAX (8U) + #define CANFD_PRV_COMMON_FIFO_MAX (3U) + #define CANFD_PRV_CFDTMIEC_LENGTH (2) + #define CANFD_PRV_RMID_POSITION (R_CANFD_CFDRM_ID_RMID_Pos) + #define CANFD_PRV_RMID_MASK (R_CANFD_CFDRM_ID_RMID_Msk) + #define CANFD_PRV_RMRTR_POSITION (R_CANFD_CFDRM_ID_RMRTR_Pos) + #define CANFD_PRV_RMRTR_MASK (R_CANFD_CFDRM_ID_RMRTR_Msk) + #define CANFD_PRV_RMIDE_POSITION (R_CANFD_CFDRM_ID_RMIDE_Pos) + #define CANFD_PRV_RMIDE_MASK (R_CANFD_CFDRM_ID_RMIDE_Msk) + #define CANFD_PRV_RMDLC_POSITION (R_CANFD_CFDRM_PTR_RMDLC_Pos) + #define CANFD_PRV_RMDLC_MASK (R_CANFD_CFDRM_PTR_RMDLC_Msk) +#endif + +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + #define CANFD_INTER_CH(channel) (0U) +#else + #define CANFD_INTER_CH(channel) (channel) +#endif + +#define CANFD_PRV_CFIFO_INDEX(buffer, channel) ((buffer) + ((channel) * CANFD_PRV_CFIFO_CHANNEL_OFFSET)) + +/*********************************************************************************************************************** + * Const data + **********************************************************************************************************************/ + +/* LUT to convert DLC values to payload size in bytes */ +static const uint8_t dlc_to_bytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + +/* LUT to determine the hierarchy of can_operation_mode_t modes. */ +static const uint8_t g_mode_order[] = {0, 2, 1, 0, 0, 3}; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * canfd_prv_ns_callback)(can_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile canfd_prv_ns_callback)(can_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if CANFD_CFG_PARAM_CHECKING_ENABLE +static bool r_canfd_bit_timing_parameter_check(can_bit_timing_cfg_t * p_bit_timing, bool is_data_phase); + +#endif + +#if BSP_FEATURE_CANFD_FD_SUPPORT +static uint8_t r_canfd_bytes_to_dlc(uint8_t bytes); + +#endif + +static void r_candfd_global_error_handler(uint32_t instance); +static void r_canfd_rx_fifo_handler(uint32_t instance); +static void r_canfd_mb_read(R_CANFD_Type * p_reg, uint32_t buffer, can_frame_t * const frame); +static void r_canfd_call_callback(canfd_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args); +static void r_canfd_mode_transition(canfd_instance_ctrl_t * p_ctrl, can_operation_mode_t operation_mode); +static void r_canfd_mode_ctr_set(volatile uint32_t * p_ctr_reg, can_operation_mode_t operation_mode); +void canfd_error_isr(void); +void canfd_rx_fifo_isr(void); +void canfd_common_fifo_rx_isr(void); +void canfd_channel_tx_isr(void); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* Channel control struct array */ +static canfd_instance_ctrl_t * gp_ctrl[BSP_FEATURE_CANFD_NUM_INSTANCES * BSP_FEATURE_CANFD_NUM_CHANNELS] = {NULL}; + +/* CAN function pointers */ +const can_api_t g_canfd_on_canfd = +{ + .open = R_CANFD_Open, + .close = R_CANFD_Close, + .write = R_CANFD_Write, + .read = R_CANFD_Read, + .modeTransition = R_CANFD_ModeTransition, + .infoGet = R_CANFD_InfoGet, + .callbackSet = R_CANFD_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup CANFD + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/***************************************************************************************************************//** + * Open and configure the CANFD channel for operation. + * + * Example: + * @snippet r_canfd_example.c R_CANFD_Open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ALREADY_OPEN Driver already open. + * @retval FSP_ERR_IN_USE Channel is already in use. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel does not exist on this MCU. + * @retval FSP_ERR_ASSERTION A required pointer was NULL. + * @retval FSP_ERR_CAN_INIT_FAILED The provided nominal or data bitrate is invalid. + * @retval FSP_ERR_CLOCK_INACTIVE CANFD source clock is disabled (PLL or PLL2). + *****************************************************************************************************************/ +fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_cfg) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(p_cfg->p_callback); + FSP_ASSERT(p_cfg->p_bit_timing); + + uint32_t channel = p_cfg->channel; + + /* Check that the module is not open, the channel is present and that it is not in use */ + FSP_ERROR_RETURN(CANFD_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(channel < BSP_FEATURE_CANFD_NUM_CHANNELS * BSP_FEATURE_CANFD_NUM_INSTANCES, + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(NULL == gp_ctrl[channel], FSP_ERR_IN_USE); + + /* Check that mandatory interrupts are enabled */ + FSP_ERROR_RETURN(VECTOR_NUMBER_CAN_RXF >= 0, FSP_ERR_CAN_INIT_FAILED); + FSP_ERROR_RETURN(VECTOR_NUMBER_CAN_GLERR >= 0, FSP_ERR_CAN_INIT_FAILED); + + /* Check that the global config is present */ + canfd_extended_cfg_t * p_extend = (canfd_extended_cfg_t *) p_cfg->p_extend; + FSP_ASSERT(p_extend->p_global_cfg); + + #if BSP_CFG_CANFDCLK_SOURCE != BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC + #if (BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS > 1U) || (BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS > 1U) + #if (BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS == 3U) /* PLL1 has 3 possible outputs that can be used for DLL */ + uint8_t canFdClockSelect = FSP_STYPE3_REG8_READ(R_SYSTEM->CANFDCKCR, !R_SYSTEM->CGFSAR_b.NONSEC18); + + /* Check that PLL is running when it is selected as the DLL source clock */ + FSP_ERROR_RETURN(0U == + (((canFdClockSelect == BSP_CLOCKS_SOURCE_CLOCK_PLL1P) || + (canFdClockSelect == BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) || + (canFdClockSelect == BSP_CLOCKS_SOURCE_CLOCK_PLL1R)) ? + FSP_STYPE3_REG8_READ(R_SYSTEM->PLLCR, !R_SYSTEM->CGFSAR_b.NONSEC08) : 0), + FSP_ERR_CLOCK_INACTIVE); + #endif + #if (BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS == 3U) /* PLL2 has 3 possible outputs that can be used for DLL */ + /* Check that PLL2 is running when it is selected as the DLL source clock */ + FSP_ERROR_RETURN(0U == + (((canFdClockSelect == BSP_CLOCKS_SOURCE_CLOCK_PLL2P) || + (canFdClockSelect == BSP_CLOCKS_SOURCE_CLOCK_PLL2Q) || + (canFdClockSelect == BSP_CLOCKS_SOURCE_CLOCK_PLL2R)) ? + FSP_STYPE3_REG8_READ(R_SYSTEM->PLLCR, !R_SYSTEM->CGFSAR_b.NONSEC09) : 0), + FSP_ERR_CLOCK_INACTIVE); + #endif + #else + #if (BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS == 1U) + + /* PLL/PLL2 has 1 possible output that can be used for DLL */ + + /* Check that PLL/PLL2 is running when it is selected as the DLL source clock */ + FSP_ERROR_RETURN(0U == + (FSP_STYPE3_REG8_READ(R_SYSTEM->CANFDCKCR, + !R_SYSTEM->CGFSAR_b.NONSEC18) == BSP_CLOCKS_SOURCE_CLOCK_PLL ? + FSP_STYPE3_REG8_READ(R_SYSTEM->PLLCR, !R_SYSTEM->CGFSAR_b.NONSEC08) : + FSP_STYPE3_REG8_READ(R_SYSTEM->PLL2CR, !R_SYSTEM->CGFSAR_b.NONSEC09)), + FSP_ERR_CLOCK_INACTIVE); + #else + + /* The PLL is available and it has 1 possible output that can be used for DLL */ + + /* Check that PLL is running when it is seclected as the DLL source clock */ + FSP_ERROR_RETURN(0U == + (FSP_STYPE3_REG8_READ(R_SYSTEM->CANFDCKCR, + !R_SYSTEM->CGFSAR_b.NONSEC18) == BSP_CLOCKS_SOURCE_CLOCK_PLL ? + FSP_STYPE3_REG8_READ(R_SYSTEM->PLLCR, !R_SYSTEM->CGFSAR_b.NONSEC08) : 0), + FSP_ERR_CLOCK_INACTIVE); + #endif + #endif + #endif + + /* Check nominal bit timing parameters for correctness */ + FSP_ERROR_RETURN(r_canfd_bit_timing_parameter_check(p_cfg->p_bit_timing, false), FSP_ERR_CAN_INIT_FAILED); + + #if BSP_FEATURE_CANFD_FD_SUPPORT + + /* Check that bit timing for FD bitrate switching is present and correct */ + can_bit_timing_cfg_t * p_data_timing = p_extend->p_data_timing; + FSP_ASSERT(p_data_timing); + FSP_ERROR_RETURN(r_canfd_bit_timing_parameter_check(p_data_timing, true), FSP_ERR_CAN_INIT_FAILED); + + can_bit_timing_cfg_t * p_bit_timing = p_cfg->p_bit_timing; + + /* Check that data rate > nominal rate */ + uint32_t data_rate_clocks = p_data_timing->baud_rate_prescaler * + (p_data_timing->time_segment_1 + p_data_timing->time_segment_2 + 1U); + uint32_t nominal_rate_clocks = p_bit_timing->baud_rate_prescaler * + (p_bit_timing->time_segment_1 + p_bit_timing->time_segment_2 + 1U); + FSP_ERROR_RETURN(data_rate_clocks <= nominal_rate_clocks, FSP_ERR_CAN_INIT_FAILED); + #endif +#else + uint32_t channel = p_cfg->channel; + + /* Get extended config */ + canfd_extended_cfg_t * p_extend = (canfd_extended_cfg_t *) p_cfg->p_extend; +#endif + + fsp_err_t err = FSP_SUCCESS; + + /* Save the base register for this channel. */ +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + R_CANFD_Type * p_reg = + (R_CANFD_Type *) ((uint32_t) R_CANFD0 + (channel * ((uint32_t) R_CANFD1 - (uint32_t) R_CANFD0))); +#else + R_CANFD_Type * p_reg = R_CANFD; +#endif + p_ctrl->p_reg = p_reg; + + /* Initialize the control block */ + p_ctrl->p_cfg = p_cfg; + + /* Set callback and context pointers, if configured */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Get global config */ + canfd_global_cfg_t * p_global_cfg = p_extend->p_global_cfg; + + /* Start module */ +#if BSP_FEATURE_CANFD_LITE + R_BSP_MODULE_START(FSP_IP_CANFD, channel); +#else + R_BSP_MODULE_START(FSP_IP_CANFD, 0); +#endif + + /* Perform global config only if the module is in Global Sleep or Global Reset */ +#if !BSP_FEATURE_CANFD_LITE + if (p_reg->CFDGSTS & R_CANFD_CFDGSTS_GRSTSTS_Msk) +#endif + { + /* Wait for RAM initialization (see Note 2 of "Timing of Global Mode Change" in the CANFD section of the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT((p_reg->CFDGSTS & R_CANFD_CFDGSTS_GRAMINIT_Msk), 0); + + /* Cancel Global Sleep and wait for transition to Global Reset */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_RESET); + + /* Configure global TX priority, DLC check/replace functions, external/internal clock select and payload + * overflow behavior */ + p_reg->CFDGCFG = p_global_cfg->global_config; + + /* Configure rule count for both channels */ +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + if (channel == 1) + { + /* On MCUs with more than one instance of CANFD the registers are duplicated + * and the RNC for each instance is on the appropriate CFDGAFLCFG0. + * + * Currently only two instances per device are supported by this driver. */ + p_reg->CFDGAFLCFG0 = (CANFD_CFG_AFL_CH1_RULE_NUM << R_CANFD_CFDGAFLCFG0_RNC0_Pos); + } + else + { + p_reg->CFDGAFLCFG0 = (CANFD_CFG_AFL_CH0_RULE_NUM << R_CANFD_CFDGAFLCFG0_RNC0_Pos); + } + +#else + p_reg->CFDGAFLCFG0 = (CANFD_CFG_AFL_CH0_RULE_NUM << R_CANFD_CFDGAFLCFG0_RNC0_Pos) | + CANFD_CFG_AFL_CH1_RULE_NUM; +#endif + + /* Set CAN FD Protocol Exception response (ISO exception state or send error frame) */ + p_reg->CFDGFDCFG = CANFD_CFG_FD_PROTOCOL_EXCEPTION; + + /* Set number and size of RX message buffers */ + p_reg->CFDRMNB = p_global_cfg->rx_mb_config; + + /* Configure RX FIFOs and interrupt */ + for (uint32_t i = 0; i < CANFD_PRV_RX_FIFO_MAX; i++) + { + p_reg->CFDRFCC[i] = p_global_cfg->rx_fifo_config[i]; + } + + R_BSP_IrqCfgEnable(VECTOR_NUMBER_CAN_RXF, p_global_cfg->rx_fifo_ipl, NULL); + + /* Set global error interrupts */ + p_reg->CFDGCTR = p_global_cfg->global_interrupts; + + /* Configure Common FIFOs */ + for (uint32_t i = 0; i < R_CANFD_NUM_COMMON_FIFOS; i++) + { + /* Configure the Common FIFOs. Mask out the enable bit because it can only be set once operating. + * See "CFDCFCCn : Common FIFO Configuration/Control Registers n (n = 0 to 5)" description in the CANFD section of the relevant hardware manual */ + p_reg->CFDCFCC[i] = p_global_cfg->common_fifo_config[i] & ~R_CANFD_CFDCFCC_CFE_Msk; + } + } + +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + if (CANFD_CFG_GLOBAL_ERROR_CH == channel) +#endif + { + /* Configure global error interrupt */ + R_BSP_IrqCfgEnable(VECTOR_NUMBER_CAN_GLERR, p_global_cfg->global_err_ipl, p_ctrl); + } + + /* Track ctrl struct */ + gp_ctrl[channel] = p_ctrl; + + /* Get AFL entry and limit */ + uint32_t afl_entry = 0; +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + uint32_t afl_max = CANFD_CFG_AFL_CH0_RULE_NUM; + if (1U == channel) + { + afl_max = CANFD_CFG_AFL_CH1_RULE_NUM; + } + +#else + uint32_t afl_max = CANFD_CFG_AFL_CH0_RULE_NUM; + if (1U == channel) + { + afl_entry += CANFD_CFG_AFL_CH0_RULE_NUM; + afl_max += CANFD_CFG_AFL_CH1_RULE_NUM; + } +#endif + + /* Unlock AFL */ + p_reg->CFDGAFLECTR = R_CANFD_CFDGAFLECTR_AFLDAE_Msk; + + /* Write all configured AFL entries */ + R_CANFD_CFDGAFL_Type * p_afl = (R_CANFD_CFDGAFL_Type *) p_extend->p_afl; + for ( ; afl_entry < afl_max; afl_entry++) + { + /* AFL register access is performed through a page window comprised of 16 entries. See "Entering + * Entries in the AFL" in the CANFD section of the relevant hardware manual. */ + + /* Set AFL page */ + p_reg->CFDGAFLECTR = (afl_entry >> 4) | R_CANFD_CFDGAFLECTR_AFLDAE_Msk; + + /* Get pointer to current AFL rule and set it to the rule pointed to by p_afl */ + volatile R_CANFD_CFDGAFL_Type * cfdgafl = &p_reg->CFDGAFL[afl_entry & 0xF]; + *cfdgafl = *p_afl++; + + /* Set Information Label 0 to the channel being configured */ + cfdgafl->P0_b.GAFLIFL0 = channel & 1U; + } + + /* Lock AFL */ + p_reg->CFDGAFLECTR = 0; + + /* Cancel Channel Sleep and wait for transition to Channel Reset */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_RESET); + + uint32_t interlaced_channel = CANFD_INTER_CH(channel); + + /* Configure bitrate */ + p_reg->CFDC[interlaced_channel].NCFG = + (uint32_t) (((p_cfg->p_bit_timing->baud_rate_prescaler - 1) & R_CANFD_CFDC_NCFG_NBRP_Msk) << + R_CANFD_CFDC_NCFG_NBRP_Pos) | + ((p_cfg->p_bit_timing->time_segment_1 - 1U) << R_CANFD_CFDC_NCFG_NTSEG1_Pos) | + ((p_cfg->p_bit_timing->time_segment_2 - 1U) << R_CANFD_CFDC_NCFG_NTSEG2_Pos) | + ((p_cfg->p_bit_timing->synchronization_jump_width - 1U) << R_CANFD_CFDC_NCFG_NSJW_Pos); + +#if BSP_FEATURE_CANFD_FD_SUPPORT + + /* Configure data bitrate for rate switching on FD frames */ + p_reg->CFDC2[interlaced_channel].DCFG = + (uint32_t) (((p_extend->p_data_timing->baud_rate_prescaler - 1) & R_CANFD_CFDC2_DCFG_DBRP_Msk) << + R_CANFD_CFDC2_DCFG_DBRP_Pos) | + ((p_extend->p_data_timing->time_segment_1 - 1U) << R_CANFD_CFDC2_DCFG_DTSEG1_Pos) | + ((p_extend->p_data_timing->time_segment_2 - 1U) << R_CANFD_CFDC2_DCFG_DTSEG2_Pos) | + ((p_extend->p_data_timing->synchronization_jump_width - 1U) << R_CANFD_CFDC2_DCFG_DSJW_Pos); + + /* Ensure transceiver delay offset is not larger than 8 bits */ + uint32_t tdco = p_extend->p_data_timing->time_segment_1; + if (tdco > UINT8_MAX) + { + tdco = UINT8_MAX; + } + + /* Configure transceiver delay compensation; allow user to set ESI bit manually */ + p_reg->CFDC2[interlaced_channel].FDCFG = + (tdco << R_CANFD_CFDC2_FDCFG_TDCO_Pos) | + (uint32_t) (p_extend->delay_compensation << R_CANFD_CFDC2_FDCFG_TDCE_Pos) | + R_CANFD_CFDC2_FDCFG_ESIC_Msk | 1U; +#endif + + /* Write TX message buffer interrupt enable bits */ + memcpy((void *) &p_reg->CFDTMIEC[interlaced_channel * CANFD_PRV_CFDTMIEC_LENGTH], + &p_extend->txmb_txi_enable, + CANFD_PRV_CFDTMIEC_LENGTH * sizeof(uint32_t)); + + /* Configure channel error interrupts */ + p_reg->CFDC[interlaced_channel].CTR = p_extend->error_interrupts | R_CANFD_CFDC_CTR_CHMDC_Msk; + + /* Enable channel interrupts */ + + if (p_cfg->error_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->error_irq, p_cfg->ipl, p_ctrl); + } + + if (p_cfg->tx_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->tx_irq, p_cfg->ipl, p_ctrl); + } + + /* Use the CAN RX IRQ for Common FIFO RX. */ + if (p_cfg->rx_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->rx_irq, p_cfg->ipl, p_ctrl); + } + + /* Set global mode to Operation and wait for transition */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_OPERATION); + + /* Transition to Channel Operation */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_NORMAL); + + /* Set current operation modes */ + p_ctrl->operation_mode = CAN_OPERATION_MODE_NORMAL; + p_ctrl->test_mode = CAN_TEST_MODE_DISABLED; + + /* Set driver to open */ + p_ctrl->open = CANFD_OPEN; + + return err; +} + +/***************************************************************************************************************//** + * Close the CANFD channel. + * + * @retval FSP_SUCCESS Channel closed successfully. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented. + *****************************************************************************************************************/ +fsp_err_t R_CANFD_Close (can_ctrl_t * const p_api_ctrl) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /* Set driver to closed */ + p_ctrl->open = 0U; + + /* Get config struct */ + can_cfg_t * p_cfg = (can_cfg_t *) p_ctrl->p_cfg; + + /* Disable channel interrupts */ + + if (p_cfg->error_irq >= 0) + { + R_BSP_IrqDisable(p_cfg->error_irq); + } + + if (p_cfg->tx_irq >= 0) + { + R_BSP_IrqDisable(p_cfg->tx_irq); + } + + if (p_cfg->rx_irq >= 0) + { + R_BSP_IrqDisable(p_cfg->rx_irq); + } + + /* Disable Global Error interrupt if the handler channel is being closed */ +#if !BSP_FEATURE_CANFD_LITE + if (CANFD_CFG_GLOBAL_ERROR_CH == p_cfg->channel) +#elif BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + + /* Only disable the Global Error interrupt if both channels are closed. */ + if (NULL == gp_ctrl[!p_cfg->channel]) +#endif + { + R_BSP_IrqDisable(VECTOR_NUMBER_CAN_GLERR); + +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + + /* Disable RX FIFO interrupt */ + R_BSP_IrqDisable(VECTOR_NUMBER_CAN_RXF); +#endif + } + +#if !BSP_FEATURE_CANFD_LITE + + /* Set channel to Sleep if other is open, otherwise reset/stop CANFD module */ + if (gp_ctrl[!p_cfg->channel]) + { + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_SLEEP); + } + else +#endif + { +#if BSP_FEATURE_CANFD_NUM_INSTANCES == 1 + + /* Disable RX FIFO interrupt */ + R_BSP_IrqDisable(VECTOR_NUMBER_CAN_RXF); +#endif + + /* Transition to Global Sleep */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_RESET); + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_SLEEP); + + /* Stop CANFD module */ +#if BSP_FEATURE_CANFD_LITE + R_BSP_MODULE_STOP(FSP_IP_CANFD, p_cfg->channel); +#else + R_BSP_MODULE_STOP(FSP_IP_CANFD, 0); +#endif + } + + /* Reset global control struct pointer */ + gp_ctrl[p_cfg->channel] = NULL; + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Write data to the CANFD channel. + * + * Example: + * @snippet r_canfd_example.c R_CANFD_Write + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_CAN_TRANSMIT_NOT_READY Transmit in progress, cannot write data at this time. + * @retval FSP_ERR_INVALID_ARGUMENT Data length or buffer number invalid. + * @retval FSP_ERR_INVALID_MODE An FD option was set on a non-FD frame. + * @retval FSP_ERR_ASSERTION One or more pointer arguments is NULL. + * @retval FSP_ERR_UNSUPPORTED FD is not supported on this MCU. + *****************************************************************************************************************/ +fsp_err_t R_CANFD_Write (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_frame_t * const p_frame) +{ +#if CANFD_CFG_PARAM_CHECKING_ENABLE + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_frame); + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); + + #if !BSP_FEATURE_CANFD_LITE + + /* CANFD channels have 16 TX message buffers + 3 common FIFOs each (0-7, 32-39, 40-42) */ + FSP_ERROR_RETURN((buffer <= 7U) || + (buffer - 32U <= 7U) || + (buffer - (uint32_t) CANFD_TX_BUFFER_FIFO_COMMON_0 <= 2U), + FSP_ERR_INVALID_ARGUMENT); + #else + + /* CANFD Lite has 4 TX message buffers + 1 common FIFO */ + FSP_ERROR_RETURN((buffer <= 3U) || + (buffer - (uint32_t) CANFD_TX_BUFFER_FIFO_COMMON_0 <= 0U), + FSP_ERR_INVALID_ARGUMENT); + #endif + + /* Check DLC field */ + #if BSP_FEATURE_CANFD_FD_SUPPORT + if (!(p_frame->options & CANFD_FRAME_OPTION_FD)) + { + FSP_ERROR_RETURN(p_frame->data_length_code <= 8, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_frame->options == 0, FSP_ERR_INVALID_MODE); + } + else if (p_frame->data_length_code > 0) + { + /* Make sure the supplied data size corresponds to a valid DLC value */ + FSP_ERROR_RETURN(0U != r_canfd_bytes_to_dlc(p_frame->data_length_code), FSP_ERR_INVALID_ARGUMENT); + } + else + { + /* Do nothing. */ + } + + #else + FSP_ERROR_RETURN(p_frame->data_length_code <= 8, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_frame->options == 0, FSP_ERR_UNSUPPORTED); + #endif +#else + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; +#endif + + /* Provide variables to store common values. */ + const bool is_cfifo = buffer >= (uint32_t) CANFD_TX_BUFFER_FIFO_COMMON_0; + const uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); + + const uint32_t id = p_frame->id | ((uint32_t) p_frame->type << R_CANFD_CFDTM_ID_TMRTR_Pos) | + ((uint32_t) p_frame->id_mode << R_CANFD_CFDTM_ID_TMIDE_Pos); + + uint32_t buffer_idx = 0; + uint8_t * p_dest = NULL; + + if (!is_cfifo) + { + /* Calculate global TX message buffer number */ + buffer_idx = buffer + (interlaced_channel * CANFD_PRV_TXMB_CHANNEL_OFFSET); + + /* Ensure MB is ready */ + FSP_ERROR_RETURN(0U == p_ctrl->p_reg->CFDTMSTS_b[buffer_idx].TMTRM, FSP_ERR_CAN_TRANSMIT_NOT_READY); + + /* Set ID */ + p_ctrl->p_reg->CFDTM[buffer_idx].ID = id; +#if BSP_FEATURE_CANFD_FD_SUPPORT + + /* Set DLC */ + p_ctrl->p_reg->CFDTM[buffer_idx].PTR = (uint32_t) r_canfd_bytes_to_dlc(p_frame->data_length_code) << + R_CANFD_CFDTM_PTR_TMDLC_Pos; + + /* Set FD bits (ESI, BRS and FDF) */ + p_ctrl->p_reg->CFDTM[buffer_idx].FDCTR = p_frame->options & 7U; +#else + + /* Set DLC */ + p_ctrl->p_reg->CFDTM[buffer_idx].PTR = (uint32_t) p_frame->data_length_code << R_CANFD_CFDTM_PTR_TMDLC_Pos; +#endif + + /* Store the data pointer. */ + p_dest = (uint8_t *) p_ctrl->p_reg->CFDTM[buffer_idx].DF; + } + else + { + /* Calculate the Common FIFO index. */ + buffer_idx = buffer - (uint32_t) CANFD_TX_BUFFER_FIFO_COMMON_0 + + (interlaced_channel * CANFD_PRV_CFIFO_CHANNEL_OFFSET); + + /* Set ID. */ + p_ctrl->p_reg->CFDCF[buffer_idx].ID = id; + +#if BSP_FEATURE_CANFD_FD_SUPPORT + + /* Set DLC. */ + p_ctrl->p_reg->CFDCF[buffer_idx].PTR = (uint32_t) r_canfd_bytes_to_dlc(p_frame->data_length_code) << + R_CANFD_CFDCF_PTR_CFDLC_Pos; + + /* Set the FD bits (ESI, BRS and FDF). */ + p_ctrl->p_reg->CFDCF[buffer_idx].FDSTS = p_frame->options & 7U; +#else + + /* Set DLC. */ + p_ctrl->p_reg->CFDTM[buffer_idx].PTR = (uint32_t) p_frame->data_length_code << R_CANFD_CFDCF_PTR_CFDLC_Pos; +#endif + + /* Store the data poitner. */ + p_dest = (uint8_t *) p_ctrl->p_reg->CFDCF[buffer_idx].DF; + } + + /* Copy data to register buffer */ + uint32_t len = p_frame->data_length_code; + uint8_t * p_src = p_frame->data; + while (len--) + { + *p_dest++ = *p_src++; + } + + if (!is_cfifo) + { + /* Request transmission */ + p_ctrl->p_reg->CFDTMC[buffer_idx] = 1; + } + else + { + /* Increment the FIFO pointer by writing 0xFF to CFPC. */ + p_ctrl->p_reg->CFDCFPCTR[buffer_idx] = R_CANFD_CFDCFPCTR_CFPC_Msk; + } + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Read data from a CANFD Message Buffer or FIFO. + * + * Example: + * snippet r_canfd_example.c R_CANFD_Read + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_INVALID_ARGUMENT Buffer number invalid. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_frame is NULL. + * @retval FSP_ERR_BUFFER_EMPTY Buffer or FIFO is empty. + *****************************************************************************************************************/ +fsp_err_t R_CANFD_Read (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_frame_t * const p_frame) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_frame); + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((buffer < CANFD_PRV_RXMB_MAX + CANFD_PRV_RX_FIFO_MAX) || + ((buffer >= CANFD_RX_BUFFER_FIFO_COMMON_0) && + (buffer < CANFD_RX_BUFFER_FIFO_COMMON_0 + CANFD_PRV_COMMON_FIFO_MAX)), + FSP_ERR_INVALID_ARGUMENT); +#endif + + uint32_t not_empty; + + /* Return an error if the buffer or FIFO is empty */ + if (buffer < CANFD_PRV_RXMB_MAX) + { + not_empty = p_ctrl->p_reg->CFDRMND0 & (1U << buffer); + } + else if (buffer < (uint32_t) CANFD_RX_BUFFER_FIFO_COMMON_0) + { + not_empty = !(p_ctrl->p_reg->CFDFESTS & (1U << (buffer - CANFD_PRV_RXMB_MAX))); + } + else + { + /* Common FIFO status are grouped together and not channelized, so calculate the index based on the channel. */ + const uint32_t cfifo_idx = CANFD_PRV_CFIFO_INDEX(buffer - (uint32_t) CANFD_RX_BUFFER_FIFO_COMMON_0, + CANFD_INTER_CH(p_ctrl->p_cfg->channel)); + + /* Update the buffer to be effectively the cfifo index calculated above. */ + /* This is needed since r_canfd_mb_read(...) doesn't take a channel number. */ + buffer = cfifo_idx + (uint32_t) CANFD_RX_BUFFER_FIFO_COMMON_0; + + not_empty = (~p_ctrl->p_reg->CFDFESTS & (1U << (R_CANFD_CFDFESTS_CFXEMP_Pos + cfifo_idx))) != 0; + } + + FSP_ERROR_RETURN(not_empty, FSP_ERR_BUFFER_EMPTY); + + /* Retrieve message from buffer */ + r_canfd_mb_read(p_ctrl->p_reg, buffer, p_frame); + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Switch to a different channel, global or test mode. + * + * Example: + * @snippet r_canfd_example.c R_CANFD_ModeTransition + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented + * @retval FSP_ERR_INVALID_MODE Cannot change to the requested mode from the current global mode. + *****************************************************************************************************************/ +fsp_err_t R_CANFD_ModeTransition (can_ctrl_t * const p_api_ctrl, + can_operation_mode_t operation_mode, + can_test_mode_t test_mode) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); + + /* Get Global Status */ + uint32_t cfdgsts = p_ctrl->p_reg->CFDGSTS; + + #if !BSP_FEATURE_CANFD_LITE + + /* Check to ensure the current mode is Global Halt when transitioning into or out of Internal Bus mode */ + FSP_ERROR_RETURN((cfdgsts & R_CANFD_CFDGSTS_GHLTSTS_Msk) || !((p_ctrl->test_mode != test_mode) && + ((CAN_TEST_MODE_INTERNAL_BUS == p_ctrl->test_mode) || + (CAN_TEST_MODE_INTERNAL_BUS == test_mode))), + FSP_ERR_INVALID_MODE); + #else + + /* Internal Bus mode is not supported on this MCU */ + FSP_ERROR_RETURN(CAN_TEST_MODE_INTERNAL_BUS != test_mode, FSP_ERR_INVALID_MODE); + #endif + + /* Check to ensure the current mode is Global Reset when transitioning into or out of Global Sleep (see + * "Global Modes" in the CANFD 'Modes Of Operation' section of the relevant hardware manual) */ + FSP_ERROR_RETURN(((cfdgsts & R_CANFD_CFDGSTS_GRSTSTS_Msk) && (CAN_OPERATION_MODE_RESET & operation_mode)) || + (!(cfdgsts & R_CANFD_CFDGSTS_GSLPSTS_Msk) && (CAN_OPERATION_MODE_GLOBAL_SLEEP != operation_mode)), + FSP_ERR_INVALID_MODE); + + /* Check to ensure the current Global mode supports the requested Channel mode, if applicable. The requested mode + * and the current global mode are converted into a number 0-3 corresponding to Operation, Halt, Reset and Sleep + * respectively. The channel mode cannot be switched to a mode with an index lower than the current global mode. */ + if (operation_mode < CAN_OPERATION_MODE_GLOBAL_OPERATION) + { + FSP_ERROR_RETURN(g_mode_order[operation_mode] >= g_mode_order[cfdgsts & CANFD_PRV_CTR_MODE_MASK], + FSP_ERR_INVALID_MODE); + } +#endif + + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); + + if (p_ctrl->test_mode != test_mode) + { +#if !BSP_FEATURE_CANFD_LITE + + /* Follow the procedure for switching to Internal Bus mode given in "Internal CAN Bus + * Communication Test Mode" in the CANFD section of the relevant hardware manual, */ + if (CAN_TEST_MODE_INTERNAL_BUS == test_mode) + { + /* Disable channel test mode */ + p_ctrl->p_reg->CFDC[interlaced_channel].CTR_b.CTME = 0; + + /* Link channel to internal bus */ + p_ctrl->p_reg->CFDGTSTCFG |= 1U << interlaced_channel; + + /* Enable internal bus test mode */ + p_ctrl->p_reg->CFDGTSTCTR = 1; + } + else +#endif + { +#if !BSP_FEATURE_CANFD_LITE + if (p_ctrl->test_mode == CAN_TEST_MODE_INTERNAL_BUS) + { + /* Unlink channel from internal bus */ + p_ctrl->p_reg->CFDGTSTCFG &= ~(1U << interlaced_channel); + + /* Disable global test mode if no channels are linked */ + if (!p_ctrl->p_reg->CFDGTSTCFG) + { + p_ctrl->p_reg->CFDGTSTCTR = 0; + } + } +#endif + + /* Transition to Channel Halt when changing test modes */ + r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_HALT); + + /* Set channel test mode */ + uint32_t cfdcnctr = p_ctrl->p_reg->CFDC[interlaced_channel].CTR; + cfdcnctr &= ~(R_CANFD_CFDC_CTR_CTME_Msk | R_CANFD_CFDC_CTR_CTMS_Msk); + p_ctrl->p_reg->CFDC[interlaced_channel].CTR = cfdcnctr | + ((uint32_t) test_mode << R_CANFD_CFDC_CTR_CTME_Pos); + } + + p_ctrl->test_mode = test_mode; + } + + if (p_ctrl->operation_mode != operation_mode) + { + r_canfd_mode_transition(p_ctrl, operation_mode); + } + + return err; +} + +/***************************************************************************************************************//** + * Get CANFD state and status information for the channel. + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION Null pointer presented + *****************************************************************************************************************/ +fsp_err_t R_CANFD_InfoGet (can_ctrl_t * const p_api_ctrl, can_info_t * const p_info) +{ +#if CANFD_CFG_PARAM_CHECKING_ENABLE + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + + /* Check pointers for NULL values */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_info); + + /* If channel is not open, return an error */ + FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); +#else + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; +#endif + + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); + + uint32_t cfdcnsts = p_ctrl->p_reg->CFDC[interlaced_channel].STS; + p_info->status = cfdcnsts & UINT16_MAX; + p_info->error_count_receive = (uint8_t) ((cfdcnsts & R_CANFD_CFDC_STS_REC_Msk) >> R_CANFD_CFDC_STS_REC_Pos); + p_info->error_count_transmit = (uint8_t) ((cfdcnsts & R_CANFD_CFDC_STS_TEC_Msk) >> R_CANFD_CFDC_STS_TEC_Pos); + p_info->error_code = p_ctrl->p_reg->CFDC[interlaced_channel].ERFL & UINT16_MAX; + p_info->rx_mb_status = p_ctrl->p_reg->CFDRMND0; + p_info->rx_fifo_status = (~p_ctrl->p_reg->CFDFESTS) & + (R_CANFD_CFDFESTS_RFXEMP_Msk | R_CANFD_CFDFESTS_CFXEMP_Msk); + + /* Clear error flags if the error IRQ is not enabled. */ + if (p_ctrl->p_cfg->error_irq < 0) + { + p_ctrl->p_reg->CFDC[interlaced_channel].ERFL = 0; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref can_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_CANFD_CallbackSet (can_ctrl_t * const p_api_ctrl, + void ( * p_callback)(can_callback_args_t *), + void * const p_context, + can_callback_args_t * const p_callback_memory) +{ + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; + +#if CANFD_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CANFD_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CANFD_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + can_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(can_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup CAN) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ +#if CANFD_CFG_PARAM_CHECKING_ENABLE +static bool r_canfd_bit_timing_parameter_check (can_bit_timing_cfg_t * const p_bit_timing, bool is_data_phase) +{ + /* Check that prescaler is in range */ + FSP_ERROR_RETURN((p_bit_timing->baud_rate_prescaler <= CANFD_BAUD_RATE_PRESCALER_MAX) && + (p_bit_timing->baud_rate_prescaler >= CANFD_BAUD_RATE_PRESCALER_MIN), + false); + + /* Check that TSEG1 > TSEG2 >= SJW for nominal bitrate and that TSEG1 >= TSEG2 >= SJW for data bitrate per section + * "Bit Timing Conditions" in the CANFD section of the relevant hardware manual. */ + + #if BSP_FEATURE_CANFD_FD_SUPPORT + if (is_data_phase) + { + /* Check Time Segment 1 is greater than or equal to Time Segment 2 */ + FSP_ERROR_RETURN((uint32_t) p_bit_timing->time_segment_1 >= (uint32_t) p_bit_timing->time_segment_2, false); + } + else + #else + + /* Data phase is only available for FD mode. */ + FSP_PARAMETER_NOT_USED(is_data_phase); + #endif + { + /* Check Time Segment 1 is greater than Time Segment 2 */ + FSP_ERROR_RETURN((uint32_t) p_bit_timing->time_segment_1 > (uint32_t) p_bit_timing->time_segment_2, false); + } + + /* Check Time Segment 2 is greater than or equal to the synchronization jump width */ + FSP_ERROR_RETURN((uint32_t) p_bit_timing->time_segment_2 >= (uint32_t) p_bit_timing->synchronization_jump_width, + false); + + return true; +} + +#endif + +/*******************************************************************************************************************//** + * Read from a Message Buffer or FIFO. + * + * NOTE: Does not index FIFOs. + * + * @param[in] p_reg Pointer to the CANFD registers + * @param[in] buffer Index of buffer to read from (MBs 0-31, FIFOs 32+) + * @param[in] frame Pointer to CAN frame to write to + **********************************************************************************************************************/ +static void r_canfd_mb_read (R_CANFD_Type * p_reg, uint32_t buffer, can_frame_t * const frame) +{ + const bool is_mb = buffer < CANFD_PRV_RXMB_MAX; + const bool is_cfifo = buffer >= (uint32_t) CANFD_RX_BUFFER_FIFO_COMMON_0; + + /* Get pointer to message buffer (FIFOs use the same buffer structure) */ + volatile R_CANFD_CFDRM_RM_TYPE * mb_regs; + if (is_mb) + { + mb_regs = CANFD_PRV_RXMB_PTR(buffer); + } + else if (is_cfifo) + { + mb_regs = (volatile R_CANFD_CFDRM_RM_TYPE *) &(p_reg->CFDCF[buffer - (uint32_t) CANFD_RX_BUFFER_FIFO_COMMON_0]); + } + else + { + mb_regs = (volatile R_CANFD_CFDRM_RM_TYPE *) &(p_reg->CFDRF[buffer - CANFD_PRV_RXMB_MAX]); + } + + /* Get frame data. */ + uint32_t id = mb_regs->ID; + + /* Get the frame type */ + frame->type = (can_frame_type_t) ((id & CANFD_PRV_RMRTR_MASK) >> CANFD_PRV_RMRTR_POSITION); + +#if BSP_FEATURE_CANFD_FD_SUPPORT + + /* Get FD status bits (ESI, BRS and FDF) */ + frame->options = mb_regs->FDSTS & 7U; +#else + frame->options = 0U; +#endif + + /* Get the frame ID */ + frame->id = id & CANFD_PRV_RMID_MASK; + + /* Get the frame ID mode (IDE bit) */ + frame->id_mode = (can_id_mode_t) (id >> CANFD_PRV_RMIDE_POSITION); + + /* Get the frame data length code */ + frame->data_length_code = dlc_to_bytes[mb_regs->PTR >> CANFD_PRV_RMDLC_POSITION]; + + /* Copy data to frame */ + uint32_t len = frame->data_length_code; + uint8_t * p_dest = frame->data; + uint8_t * p_src = (uint8_t *) mb_regs->DF; + while (len--) + { + *p_dest++ = *p_src++; + } + + if (is_mb) + { + /* Clear RXMB New Data bit */ + p_reg->CFDRMND0 = ~(1U << buffer); + } + else if (is_cfifo) + { + /* Increment the Common FIFO pointer. */ + p_reg->CFDCFPCTR[buffer - (uint32_t) CANFD_RX_BUFFER_FIFO_COMMON_0] = R_CANFD_CFDCFPCTR_CFPC_Msk; + } + else + { + /* Increment RX FIFO pointer */ + p_reg->CFDRFPCTR[buffer - CANFD_PRV_RXMB_MAX] = UINT8_MAX; + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to CAN instance control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void r_canfd_call_callback (canfd_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args) +{ + can_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + can_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + canfd_prv_ns_callback p_callback = (canfd_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Global Error Handler. + * + * Handles the Global Error IRQ for a given instance of CANFD. + **********************************************************************************************************************/ +static void r_candfd_global_error_handler (uint32_t instance) +{ + canfd_instance_ctrl_t * p_ctrl = gp_ctrl[instance]; + + can_callback_args_t args = {0U}; + + args.event = CAN_EVENT_ERR_GLOBAL; + + /* Read global error flags. */ + uint32_t cfdgerfl = p_ctrl->p_reg->CFDGERFL; + + /* Global errors are in the top halfword of canfd_error_t; move and preserve ECC error flags. */ + args.error = ((cfdgerfl & UINT16_MAX) << 16) + ((cfdgerfl >> 16) << 28); + + /* Clear global error flags. */ + p_ctrl->p_reg->CFDGERFL = 0; + + if (args.error & CANFD_ERROR_GLOBAL_MESSAGE_LOST) + { + /* Get lowest RX FIFO with Message Lost condition and clear the flag */ + args.buffer = __CLZ(__RBIT(p_ctrl->p_reg->CFDFMSTS)); + p_ctrl->p_reg->CFDRFSTS[args.buffer] &= ~R_CANFD_CFDRFSTS_RFMLT_Msk; + } + + /* Set channel and context based on selected global error handler channel. */ + args.channel = CANFD_CFG_GLOBAL_ERROR_CH; + args.p_context = p_ctrl->p_context; + + /* Set remaining arguments and call callback */ + r_canfd_call_callback(p_ctrl, &args); +} + +/*******************************************************************************************************************//** + * Error ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common error function, and restores context if RTOS is used. + **********************************************************************************************************************/ +void canfd_error_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + /* Get IRQ and context */ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + if (VECTOR_NUMBER_CAN_GLERR == irq) + { +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + + /* If there are separate instances of CANFD, then loop over each instance to handle the source of the global + * error IRQ. */ + for (uint32_t i = 0; i < BSP_FEATURE_CANFD_NUM_INSTANCES; i++) + { + if (NULL != gp_ctrl[i]) + { + r_candfd_global_error_handler(i); + } + } + +#else + r_candfd_global_error_handler(CANFD_CFG_GLOBAL_ERROR_CH); +#endif + } + else + { + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + can_callback_args_t args = {0U}; + canfd_instance_ctrl_t * p_callback_ctrl; + + args.event = CAN_EVENT_ERR_CHANNEL; + + /* Read and clear channel error flags. */ + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); + args.error = p_ctrl->p_reg->CFDC[interlaced_channel].ERFL & UINT16_MAX; // Upper halfword contains latest CRC + p_ctrl->p_reg->CFDC[interlaced_channel].ERFL = 0; + + /* Choose the channel provided by the interrupt context. */ + p_callback_ctrl = p_ctrl; + + args.channel = interlaced_channel; + args.p_context = p_ctrl->p_context; + args.buffer = 0U; + + /* Set remaining arguments and call callback */ + r_canfd_call_callback(p_callback_ctrl, &args); + } + + /* Clear IRQ */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Receive FIFO handler. + * + * Handles the Receive IRQ for a given instance of CANFD. + **********************************************************************************************************************/ +static void r_canfd_rx_fifo_handler (uint32_t instance) +{ + can_callback_args_t args; +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + R_CANFD_Type * p_reg = + (R_CANFD_Type *) ((uint32_t) R_CANFD0 + (instance * ((uint32_t) R_CANFD1 - (uint32_t) R_CANFD0))); +#else + FSP_PARAMETER_NOT_USED(instance); + R_CANFD_Type * p_reg = R_CANFD; +#endif + + /* Get lowest FIFO requesting interrupt */ + uint32_t fifo = __CLZ(__RBIT(p_reg->CFDRFISTS)); + + /* Only perform ISR duties if a FIFO has requested it */ + if (fifo < CANFD_PRV_RX_FIFO_MAX) + { + /* Set static arguments */ + args.event = CAN_EVENT_RX_COMPLETE; + args.buffer = fifo + CANFD_PRV_RXMB_MAX; + + /* Read from the FIFO until it is empty */ + while (!(p_reg->CFDFESTS & (1U << fifo))) + { + /* Get channel associated with the AFL entry */ +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + args.channel = instance; +#else + args.channel = p_reg->CFDRF[fifo].FDSTS_b.RFIFL; +#endif + + /* Read and index FIFO */ + r_canfd_mb_read(p_reg, fifo + CANFD_PRV_RXMB_MAX, &args.frame); + + /* Set the remaining callback arguments */ + args.p_context = gp_ctrl[args.channel]->p_context; + r_canfd_call_callback(gp_ctrl[args.channel], &args); + } + + /* Clear RX FIFO Interrupt Flag */ + p_reg->CFDRFSTS[fifo] &= ~R_CANFD_CFDRFSTS_RFIF_Msk; + } + + if (!p_reg->CFDRFISTS) + { + /* Clear interrupt in NVIC if there are no pending RX FIFO IRQs */ + R_BSP_IrqStatusClear(VECTOR_NUMBER_CAN_RXF); + } +} + +/*******************************************************************************************************************//** + * Receive ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common receive function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void canfd_rx_fifo_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + + /* If there are separate instances of CANFD, then loop over each instance to handle the source of the global + * receive IRQ. */ + for (uint32_t i = 0; i < BSP_FEATURE_CANFD_NUM_INSTANCES; i++) + { + if (NULL != gp_ctrl[i]) + { + r_canfd_rx_fifo_handler(i); + } + } + +#else + r_canfd_rx_fifo_handler(0U); +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Transmit ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common transmit function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void canfd_channel_tx_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + canfd_extended_cfg_t * p_extend = (canfd_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + uint32_t channel = p_ctrl->p_cfg->channel; + + /* Set static arguments */ + can_callback_args_t args; + args.channel = channel; + args.p_context = p_ctrl->p_context; + + uint32_t interlaced_channel = CANFD_INTER_CH(channel); + + /* Check the byte of CFDGTINTSTS0 that corresponds to the interrupting channel */ + volatile uint8_t * p_cfdgtintsts = (((volatile uint8_t *) &p_ctrl->p_reg->CFDGTINTSTS0) + interlaced_channel); + while (*p_cfdgtintsts) + { + bool is_cfifo = false; + uint32_t txmb; + volatile uint32_t * p_cfdtm_sts; + const uint32_t cfdgtintsts = *p_cfdgtintsts; + + interlaced_channel <<= 1; + + /* Get relevant TX status register bank */ + if (cfdgtintsts & R_CANFD_CFDGTINTSTS0_TSIF0_Msk) + { + p_cfdtm_sts = (volatile uint32_t *) &p_ctrl->p_reg->CFDTMTCSTS[interlaced_channel]; + args.event = CAN_EVENT_TX_COMPLETE; + } + else if (cfdgtintsts & R_CANFD_CFDGTINTSTS0_CFTIF0_Msk) + { + is_cfifo = true; +#if CANFD_PRV_CFIFO_HAS_ISTS + p_cfdtm_sts = &p_ctrl->p_reg->CFDCFTISTS; +#endif + args.event = (p_extend->p_global_cfg->common_fifo_config[interlaced_channel] & R_CANFD_CFDCFCC_CFIM_Msk) ? + CAN_EVENT_TX_COMPLETE : CAN_EVENT_TX_FIFO_EMPTY; + } + else + { + p_cfdtm_sts = (volatile uint32_t *) &p_ctrl->p_reg->CFDTMTASTS[interlaced_channel]; + args.event = CAN_EVENT_TX_ABORTED; + } + + interlaced_channel >>= 1; + + /* Calculate lowest TXMB with the specified event */ + if (!is_cfifo) + { + txmb = __CLZ(__RBIT(*p_cfdtm_sts)); + txmb = (txmb < 8) ? txmb : __CLZ(__RBIT(*(p_cfdtm_sts + 1))) + CANFD_PRV_TXMB_OFFSET; + + /* Clear TX complete/abort flags */ + p_ctrl->p_reg->CFDTMSTS_b[txmb + (CANFD_PRV_TXMB_CHANNEL_OFFSET * interlaced_channel)].TMTRF = 0; + } + else + { +#if CANFD_PRV_CFIFO_HAS_ISTS + + /* Adjust txmb with the lowest indexed Common FIFO that could have triggered this event. + * Mask out only the Common FIFOs associated with this channel. */ + uint32_t cfdtm_mask = ((1U << CANFD_PRV_COMMON_FIFO_MAX) - 1U) << + (interlaced_channel * CANFD_PRV_COMMON_FIFO_MAX); + txmb = __CLZ(__RBIT(*p_cfdtm_sts & cfdtm_mask)); +#else + txmb = 0; +#endif + + /* Clear the interrupt flag for Common FIFO TX. */ + p_ctrl->p_reg->CFDCFSTS[txmb] &= ~R_CANFD_CFDCFSTS_CFTXIF_Msk; + + /* Add the Common FIFO offset so the correct type of buffer will be available in the callback. */ + txmb += CANFD_TX_BUFFER_FIFO_COMMON_0; + } + + /* Set the callback arguments */ + args.buffer = txmb; + r_canfd_call_callback(p_ctrl, &args); + } + + /* Clear interrupt */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Common FIFO Receive ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common receive function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void canfd_common_fifo_rx_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + uint32_t channel = p_ctrl->p_cfg->channel; + can_callback_args_t args; + +#if CANFD_PRV_CFIFO_HAS_ISTS + + /* Get lowest FIFO requesting interrupt */ + + /* To satisfy clang-tidy mask out the index. A value of 32 only happens if no flag is set which shouldn't happen in + * this ISR. If it does for some reason, the while loop below will be bypassed since the associated flag being + * checked will be ignored. */ + uint32_t fifo = __CLZ(__RBIT(p_ctrl->p_reg->CFDCFRISTS & R_CANFD_CFDCFRISTS_CFXRXIF_Msk)) & 0x1FU; +#else + uint32_t fifo = 0; +#endif + + /* Set static arguments */ + args.event = CAN_EVENT_RX_COMPLETE; + args.channel = channel; + +#if BSP_FEATURE_CANFD_NUM_CHANNELS > 1 + + /* Get the channel based fifo index to get the currect buffer value. */ + if (fifo > CANFD_PRV_CFIFO_CHANNEL_OFFSET) + { + args.buffer = fifo % (CANFD_PRV_CFIFO_CHANNEL_OFFSET + 1); + } + else + { + args.buffer = fifo; + } + +#else + args.buffer = fifo; +#endif + + /* Move buffer up to the correct range. */ + args.buffer += (uint32_t) CANFD_RX_BUFFER_FIFO_COMMON_0; + + /* Read from the FIFO until it is empty */ + while (!(p_ctrl->p_reg->CFDFESTS & (1U << (R_CANFD_CFDFESTS_CFXEMP_Pos + fifo)))) + { + /* Read and index FIFO */ + /* buffer is slightly different in this function since it operates globally. */ + r_canfd_mb_read(p_ctrl->p_reg, fifo + (uint32_t) CANFD_RX_BUFFER_FIFO_COMMON_0, &args.frame); + + /* Set the remaining callback arguments */ + args.p_context = gp_ctrl[args.channel]->p_context; + r_canfd_call_callback(gp_ctrl[args.channel], &args); + } + + /* Clear Common FIFO RX Interrupt Flag */ + p_ctrl->p_reg->CFDCFSTS[fifo] &= ~R_CANFD_CFDCFSTS_CFRXIF_Msk; + +#if CANFD_PRV_CFIFO_HAS_ISTS + if (!p_ctrl->p_reg->CFDCFRISTS) +#else + + /* This device is single channel and single Common FIFO. */ + if (!(p_ctrl->p_reg->CFDCFSTS[0] & R_CANFD_CFDCFSTS_CFRXIF_Msk)) +#endif + { + /* Clear interrupt in NVIC if there are no pending RX FIFO IRQs */ + R_BSP_IrqStatusClear(irq); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * This function is used to switch the CANFD peripheral operation mode. + * @param[in] p_ctrl - pointer to control structure + * @param[in] operation_mode - destination operation mode + **********************************************************************************************************************/ +static void r_canfd_mode_transition (canfd_instance_ctrl_t * p_ctrl, can_operation_mode_t operation_mode) +{ + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); + + /* Get bit 7 from operation_mode to determine if this is a global mode change request */ + bool global_mode = (bool) (operation_mode >> 7); + operation_mode &= 0xF; + + if (global_mode) + { + uint32_t cfdgctr = p_ctrl->p_reg->CFDGCTR; + + /* If CANFD is transitioning to Global Reset, make sure the FIFOs are disabled. */ + if (!(cfdgctr & R_CANFD_CFDGSTS_GRSTSTS_Msk) && (operation_mode & CAN_OPERATION_MODE_RESET)) + { + /* Disable RX FIFOs */ + for (uint32_t i = 0; i < CANFD_PRV_RX_FIFO_MAX; i++) + { + p_ctrl->p_reg->CFDRFCC[i] &= ~R_CANFD_CFDRFCC_RFE_Msk; + } + + /* Disable Common FIFOs */ + for (uint32_t i = 0; i < CANFD_PRV_COMMON_FIFO_MAX * BSP_FEATURE_CANFD_NUM_CHANNELS; i++) + { + p_ctrl->p_reg->CFDCFCC[i] &= ~R_CANFD_CFDCFCC_CFE_Msk; + } + } + + r_canfd_mode_ctr_set(&p_ctrl->p_reg->CFDGCTR, operation_mode); + + /* If CANFD is transitioning out of Reset the FIFOs need to be enabled. */ + if ((cfdgctr & R_CANFD_CFDGSTS_GRSTSTS_Msk) && !(operation_mode & CAN_OPERATION_MODE_RESET)) + { + /* Get global config */ + canfd_global_cfg_t * p_global_cfg = + ((canfd_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->p_global_cfg; + + /* Enable RX FIFOs */ + for (uint32_t i = 0; i < CANFD_PRV_RX_FIFO_MAX; i++) + { + p_ctrl->p_reg->CFDRFCC[i] = p_global_cfg->rx_fifo_config[i]; + } + } + } + else + { + uint32_t cfdcnctr = p_ctrl->p_reg->CFDC[interlaced_channel].CTR; + + if (((cfdcnctr & R_CANFD_CFDC_CTR_CSLPR_Msk) && (!(CAN_OPERATION_MODE_RESET & operation_mode))) || + ((!(cfdcnctr & CANFD_PRV_CTR_RESET_BIT)) && (CAN_OPERATION_MODE_SLEEP == operation_mode))) + { + /* Transition channel to Reset if a transition to/from Sleep is requested (see "Channel + * Modes" in the CANFD section of the relevant hardware manual) */ + r_canfd_mode_ctr_set(&p_ctrl->p_reg->CFDC[interlaced_channel].CTR, CAN_OPERATION_MODE_RESET); + } + + /* Request transition to selected mode */ + r_canfd_mode_ctr_set(&p_ctrl->p_reg->CFDC[interlaced_channel].CTR, operation_mode); + + /* If CANFD is transitioning from Reset, make sure the Common FIFOs are enabled. + * The FIFOs will be disabled automatically if configured for TX and the channel is transitioned to reset. */ + if ((cfdcnctr & R_CANFD_CFDC_CTR_CHMDC_Msk) && !(operation_mode & CAN_OPERATION_MODE_RESET)) + { + /* Get global config */ + canfd_global_cfg_t * p_global_cfg = + ((canfd_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->p_global_cfg; + + const uint32_t ch_offset = interlaced_channel * CANFD_PRV_COMMON_FIFO_MAX; + + /* Enable Common FIFOs */ + for (uint32_t i = 0; i < CANFD_PRV_COMMON_FIFO_MAX; i++) + { + p_ctrl->p_reg->CFDCFCC[ch_offset + i] |= + (p_global_cfg->common_fifo_config[ch_offset + i] & R_CANFD_CFDCFCC_CFE_Msk); + } + } + } + + p_ctrl->operation_mode = + (can_operation_mode_t) (p_ctrl->p_reg->CFDC[interlaced_channel].CTR & CANFD_PRV_CTR_MODE_MASK); +} + +/*******************************************************************************************************************//** + * Sets the provided CTR register to the requested mode and waits for the associated STS register to reflect the change + * @param[in] p_ctr_reg - pointer to control register + * @param[in] operation_mode - requested mode (not including global bits) + **********************************************************************************************************************/ +static void r_canfd_mode_ctr_set (volatile uint32_t * p_ctr_reg, can_operation_mode_t operation_mode) +{ + volatile uint32_t * p_sts_reg = p_ctr_reg + 1; + + /* See definitions for CFDCnCTR, CFDCnSTS, CFDGCTR and CFDGSTS in the CANFD section of the relevant hardware manual */ + *p_ctr_reg = (*p_ctr_reg & ~CANFD_PRV_CTR_MODE_MASK) | operation_mode; + FSP_HARDWARE_REGISTER_WAIT((*p_sts_reg & CANFD_PRV_CTR_MODE_MASK), operation_mode); +} + +#if BSP_FEATURE_CANFD_FD_SUPPORT + +/*******************************************************************************************************************//** + * Converts bytes into a DLC value + * @param[in] bytes Number of payload bytes + **********************************************************************************************************************/ +static uint8_t r_canfd_bytes_to_dlc (uint8_t bytes) +{ + if (bytes <= 8) + { + return bytes; + } + + if (bytes <= 24) + { + return (uint8_t) (8U + ((bytes - 8U) / 4U)); + } + + return (uint8_t) (0xDU + ((bytes / 16U) - 2U)); +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cec/r_cec.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cec/r_cec.c new file mode 100644 index 0000000000..83214c733c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cec/r_cec.c @@ -0,0 +1,595 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_cec.h" +#include "r_cec_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define CEC_OPEN (0x52434543U) /* "RCEC" in ascii */ + +/* CADR and Local Address Macros */ +#define CEC_CADR_UNREGISTERED (0U) +#define CEC_CADR_TO_LOCAL_ADDRESS(cadr) (cadr != 0U ? p_instance_ctrl->local_address : CEC_ADDR_UNREGISTERED) +#define CEC_LOCAL_ADDR_TO_CADR(a) ((uint16_t) (0x01 << p_instance_ctrl->local_address)) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * cec_prv_ns_callback_t)(cec_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile cec_prv_ns_callback_t)(cec_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ + +static void r_cec_call_callback(cec_instance_ctrl_t * p_ctrl, cec_callback_args_t * p_args); + +void cec_data_isr(void); +void cec_error_isr(void); +void cec_message_isr(void); + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* CEC function pointers */ +const cec_api_t g_cec_on_cec = +{ + .open = R_CEC_Open, + .mediaInit = R_CEC_MediaInit, + .close = R_CEC_Close, + .write = R_CEC_Write, + .statusGet = R_CEC_StatusGet, + .callbackSet = R_CEC_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup CEC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/***************************************************************************************************************//** + * Open and configure the CEC module for operation. + * + * Example: + * @snippet r_cec_example.c R_CEC_Open + * + * @retval FSP_SUCCESS CEC Module opened successfully. + * @retval FSP_ERR_ALREADY_OPEN Driver already open. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_IRQ_BSP_DISABLED Interrupts are not enabled. + *****************************************************************************************************************/ +fsp_err_t R_CEC_Open (cec_ctrl_t * const p_ctrl, cec_cfg_t const * const p_cfg) +{ + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) p_ctrl; + +#if CEC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN((IRQn_Type) 0 <= p_cfg->data_irq, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ERROR_RETURN((IRQn_Type) 0 <= p_cfg->msg_irq, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ERROR_RETURN((IRQn_Type) 0 <= p_cfg->error_irq, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ERROR_RETURN(CEC_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + cec_extended_cfg_t * p_extend = p_cfg->p_extend; + p_instance_ctrl->p_cfg = p_cfg; + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + R_BSP_MODULE_START(FSP_IP_CEC, 0); + + /* Initialize Local Address to unregistered */ + R_CEC->CADR = CEC_CADR_UNREGISTERED; + + /* Set bit-width registers. + * These are only rewritable when the CEC module is stopped (CECCTL0.CECE == 0), which is ensured by parameter checking above. + * Configured width for these settings can be calculated: (Register_Value + 1) * CEC_Clock_Cycle */ + R_CEC->STATL = p_cfg->bit_timing_cfg->bit_width_tx_start_low; + R_CEC->STATB = p_cfg->bit_timing_cfg->bit_width_tx_start_high; + R_CEC->LGC0L = p_cfg->bit_timing_cfg->bit_width_tx_zero_low; + R_CEC->LGC1L = p_cfg->bit_timing_cfg->bit_width_tx_one_low; + R_CEC->DATB = p_cfg->bit_timing_cfg->bit_width_tx_bit_overall; + R_CEC->STATLL = p_cfg->bit_timing_cfg->bit_width_rx_start_low_min; + R_CEC->STATLH = p_cfg->bit_timing_cfg->bit_width_rx_start_low_max; + R_CEC->STATBL = p_cfg->bit_timing_cfg->bit_width_rx_start_overall_min; + R_CEC->STATBH = p_cfg->bit_timing_cfg->bit_width_rx_start_overall_max; + R_CEC->LGC0LL = p_cfg->bit_timing_cfg->bit_width_rx_zero_low_min; + R_CEC->LGC0LH = p_cfg->bit_timing_cfg->bit_width_rx_zero_low_max; + R_CEC->LGC1LL = p_cfg->bit_timing_cfg->bit_width_rx_one_low_min; + R_CEC->LGC1LH = p_cfg->bit_timing_cfg->bit_width_rx_one_low_max; + R_CEC->DATBL = p_cfg->bit_timing_cfg->bit_width_rx_bit_overall_min; + R_CEC->DATBH = p_cfg->bit_timing_cfg->bit_width_rx_bit_overall_max; + + /* CEC Data sampling time */ + R_CEC->NOMT = p_cfg->rx_data_sample_time; + + /* CEC Data Bit Reference Width Setting + * This 1-data bit width is used when counting the number of bits for errors handling, signal-free time, and bus locking + * detection. This register is only rewritable when the CEC module is stopped (CECCTL0.CECE == 0), which is ensured by parameter + * checking above. */ + R_CEC->NOMP = p_cfg->rx_data_bit_reference_width; + + /* CEC Extension Mode Register + * This register is only rewritable when the CEC module is stopped (CECCTL0.CECE == 0), which is ensured by parameter checking above. */ + R_CEC->CECEXMD = (uint8_t) ((p_extend->err_detect_lerplen) | + (p_extend->err_detect_rercven) | + (p_extend->intda_timing_select)); + + /* CEC Control Register One + * See "CEC Control Register 1 (CECCTL1)" description of the relevant hardware manual. Rewrite SFT bits only after confirming + * that the Signal-Free Time Rewrite Disable Report Flag (CECS.SFTST) is 0. */ + FSP_HARDWARE_REGISTER_WAIT(R_CEC->CECS_b.SFTST, 0x0); + R_CEC->CECCTL1 = p_extend->ctl1; + + /* Ensure the module starts without pending errors */ + R_CEC->CECFC = CEC_CECFC_MASK_ALL; + + /* CEC Control Register Zero */ + p_instance_ctrl->cecctl0 = (uint8_t) ((p_extend->ctl0_clock_select) | + (p_extend->ctl0_ackten) | + (1U << R_CEC_CECCTL0_CECE_Pos)); + R_CEC->CECCTL0 = p_instance_ctrl->cecctl0; + + /* Enable Interrupts */ + cec_instance_ctrl_t * p_isr_context = p_instance_ctrl; + R_BSP_IrqCfgEnable(p_cfg->data_irq, p_instance_ctrl->p_cfg->ipl, p_isr_context); + R_BSP_IrqCfgEnable(p_cfg->msg_irq, p_instance_ctrl->p_cfg->ipl, p_isr_context); + R_BSP_IrqCfgEnable(p_cfg->error_irq, p_instance_ctrl->p_cfg->ipl, p_isr_context); + + /* Mark the control block as open and status to uninitialized */ + p_instance_ctrl->state = CEC_STATE_UNINIT; + p_instance_ctrl->open = CEC_OPEN; + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Allocate provided CEC Local Address and Initialize the CEC module for operation. + * + * @note After calling R_CEC_Open this function may return FSP_ERR_IN_USE for up to 45 milliseconds. + * + * Example: + * @snippet r_cec_example.c R_CEC_MediaInit + * + * @retval FSP_SUCCESS CEC Module Initialized successfully. + * @retval FSP_ERR_ASSERTION An input argument is invalid or callback has not been set. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_IN_USE HDMI CEC Bus is currently in use. Try again later. + *****************************************************************************************************************/ +fsp_err_t R_CEC_MediaInit (cec_ctrl_t * const p_ctrl, cec_addr_t local_address) +{ + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) p_ctrl; + +#if CEC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(CEC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(local_address <= CEC_ADDR_UNREGISTERED); + FSP_ASSERT(NULL != p_instance_ctrl->p_callback); +#endif + FSP_ERROR_RETURN(0U == R_CEC->CECS_b.BUSST, FSP_ERR_IN_USE); + + /* Set local address register to zero for now - the actual value is set by MediaInit */ + p_instance_ctrl->local_address = local_address; + + /* Disable reception and reset the CEC address to 'unregistered' */ + p_instance_ctrl->cecctl0 &= (uint8_t) ~R_CEC_CECCTL0_CECRXEN_Msk; + R_CEC->CECCTL0 = p_instance_ctrl->cecctl0; + R_CEC->CADR = CEC_CADR_UNREGISTERED; + + /* Set EOM and load address into CTXD as both initiator and follower */ + p_instance_ctrl->state = CEC_STATE_UNINIT; + R_CEC->CECCTL0 = p_instance_ctrl->cecctl0 | R_CEC_CECCTL0_EOM_Msk; + R_CEC->CTXD = (uint8_t) ((p_instance_ctrl->local_address) | (p_instance_ctrl->local_address << 4U)); + + /* Start Transmission */ + R_CEC->CECCTL0 = p_instance_ctrl->cecctl0 | R_CEC_CECCTL0_EOM_Msk | R_CEC_CECCTL0_TXTRG_Msk; + + /* Message transmitted successfully. Use callback to determine address allocation success/failure */ + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Close the CEC module. + * + * @retval FSP_SUCCESS CEC Module closed successfully. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + *****************************************************************************************************************/ +fsp_err_t R_CEC_Close (cec_ctrl_t * const p_ctrl) +{ + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) p_ctrl; + +#if CEC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); +#endif + + /* Mark the module as closed */ + p_instance_ctrl->open = 0U; + p_instance_ctrl->state = CEC_STATE_UNINIT; + + /* Disable CEC Interrupts */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->data_irq); + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->msg_irq); + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->error_irq); + + /* Clear the CEC address and Disable Operation */ + R_CEC->CADR = CEC_CADR_UNREGISTERED; + R_CEC->CECCTL0 = (uint8_t) (p_instance_ctrl->cecctl0 & ~R_CEC_CECCTL0_CECE_Msk); + + /* Turn off the peripheral to save power */ + R_BSP_MODULE_STOP(FSP_IP_CEC, 0); + + return FSP_SUCCESS; +} + +/***************************************************************************************************************//** + * Write data to the CEC bus. Data transmission is asynchronous. Provided message buffer should not be modified + * until transmission is complete. + * + * Data Transmission follows the pattern defined be the HDMI CEC Specification: + * + * | Data | Description | Size | + * |--------------|---------------------------------|--------------------------------| + * | Start Bit | Managed by Hardware, per config | N/A | + * | Header Block | Source/Destination Identifier | 1 Byte | + * | Data Block 1 | Opcode Value (Optional) | 1 Byte | + * | Data Block 2 | Operands (Optional) | Variable (0-14 Bytes Typical) | + * + * Example: + * @snippet r_cec_example.c R_CEC_Write + * + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_NOT_INITIALIZED Module has not been successfully initialized. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_INVALID_SIZE Invalid message size. + * @retval FSP_ERR_IN_USE HDMI CEC Bus is currently in use. Try again later. + *****************************************************************************************************************/ +fsp_err_t R_CEC_Write (cec_ctrl_t * const p_ctrl, cec_message_t const * const p_message, uint32_t message_size) +{ + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) p_ctrl; + +#if CEC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_message); + FSP_ERROR_RETURN(CEC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(CEC_STATE_UNINIT != p_instance_ctrl->state, FSP_ERR_NOT_INITIALIZED); + FSP_ERROR_RETURN(CEC_STATE_READY == p_instance_ctrl->state, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(0 < message_size, FSP_ERR_INVALID_SIZE); + FSP_ERROR_RETURN(sizeof(cec_message_t) >= message_size, FSP_ERR_INVALID_SIZE); +#endif + FSP_ERROR_RETURN(0U == R_CEC->CECS_b.BUSST, FSP_ERR_IN_USE); + + /* Set control block state to transmitting */ + p_instance_ctrl->state = CEC_STATE_TX_ACTIVE; + + /* Prepare internal state for transmission - will continue via ISR */ + p_instance_ctrl->p_tx_buf = p_message->raw_data + 1; + p_instance_ctrl->tx_bytes = message_size - 1; + + /* Set EOM Bit if needed */ + R_CEC->CECCTL0 = (uint8_t) (p_instance_ctrl->cecctl0 | (p_instance_ctrl->tx_bytes ? 0 : R_CEC_CECCTL0_EOM_Msk)); + + /* Load header block - always transmitted first */ + R_CEC->CTXD = (uint8_t) (p_instance_ctrl->local_address << 4U | p_message->destination); + + /* Start transmission */ + R_CEC->CECCTL0 = p_instance_ctrl->cecctl0 | R_CEC_CECCTL0_TXTRG_Msk; + + return FSP_SUCCESS; +}; + +/***************************************************************************************************************//** + * Provides the state and status information according to the provided CEC control instance. + * @retval FSP_SUCCESS Operation succeeded. + * @retval FSP_ERR_NOT_OPEN Control block not open. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + *****************************************************************************************************************/ +fsp_err_t R_CEC_StatusGet (cec_ctrl_t * const p_ctrl, cec_status_t * const p_status) +{ + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) p_ctrl; + +#if CEC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(CEC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_status->local_address = (cec_addr_t) CEC_CADR_TO_LOCAL_ADDRESS(R_CEC->CADR); + p_status->state = p_instance_ctrl->state; + if (CEC_STATE_READY == p_instance_ctrl->state) + { + p_status->state = R_CEC->CECS_b.BUSST ? CEC_STATE_BUSY : p_instance_ctrl->state; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref cec_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_CEC_CallbackSet (cec_ctrl_t * const p_ctrl, + void ( * p_callback)(cec_callback_args_t *), + void * const p_context, + cec_callback_args_t * const p_callback_memory) +{ + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) p_ctrl; + +#if CEC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CEC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CEC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + cec_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(cec_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup CEC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to CEC instance control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void r_cec_call_callback (cec_instance_ctrl_t * p_ctrl, cec_callback_args_t * p_args) +{ + cec_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + cec_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save previous arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the current stack args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + cec_prv_ns_callback_t p_callback = (cec_prv_ns_callback_t) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Data ISR - Invoked after start bit of all tx data and after data for all rx data + **********************************************************************************************************************/ +void cec_data_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + /* Clear interrupt */ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if (CEC_STATE_UNINIT != p_instance_ctrl->state) /* Do nothing if not initialized */ + { + uint8_t cecs_b = R_CEC->CECS; + + /* Tx Processing - Tx flag can deassert quickly, so we check module state also to catch certain possible error cases */ + if ((cecs_b & R_CEC_CECS_TXST_Msk) || (CEC_STATE_TX_ACTIVE == p_instance_ctrl->state)) + { + if (p_instance_ctrl->tx_bytes > 0) + { + /* Indicate EOM if this is the last byte to be transmitted */ + if (--p_instance_ctrl->tx_bytes == 0) + { + R_CEC->CECCTL0 = p_instance_ctrl->cecctl0 | (uint8_t) R_CEC_CECCTL0_EOM_Msk; + } + + /* Load next data before current transmission ends */ + R_CEC->CTXD = *p_instance_ctrl->p_tx_buf++; + } + } + /* Rx Processing */ + else + { + cec_callback_args_t cb_args; + cb_args.event = CEC_EVENT_RX_DATA; + cb_args.p_context = p_instance_ctrl->p_context; + cb_args.addr_match = cecs_b & R_CEC_CECS_ADRF_Msk; + cb_args.data_byte = R_CEC->CRXD; + cb_args.status.local_address = (cec_addr_t) CEC_CADR_TO_LOCAL_ADDRESS(R_CEC->CADR); + cb_args.errors = CEC_ERROR_NONE; + + p_instance_ctrl->state = CEC_STATE_RX_ACTIVE; + + /* Rx data maintained and processed by application*/ + r_cec_call_callback(p_instance_ctrl, &cb_args); + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Message Complete ISR - Invoked after EOM message has been sent or received + **********************************************************************************************************************/ +void cec_message_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + /* Clear interrupt */ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + bool tx_actv = (R_CEC->CECS & R_CEC_CECS_TXST_Msk) || (p_instance_ctrl->state == CEC_STATE_TX_ACTIVE); + bool rx_actv = p_instance_ctrl->state == CEC_STATE_RX_ACTIVE; + + /* Notify application that message processing is complete */ + cec_callback_args_t cb_args; + cb_args.event = tx_actv ? CEC_EVENT_TX_COMPLETE : CEC_EVENT_RX_COMPLETE; + cb_args.p_context = p_instance_ctrl->p_context; + cb_args.addr_match = false; + cb_args.data_byte = 0U; + cb_args.status.state = p_instance_ctrl->state; + cb_args.errors = CEC_ERROR_NONE; /* Errors will be sent by error ISR */ + + /* Assign local address if allocation successful */ + if ((CEC_STATE_UNINIT == p_instance_ctrl->state) && + ((CEC_ADDR_UNREGISTERED == p_instance_ctrl->local_address) || R_CEC->CECEXMON_b.ACKF)) + { + /* See "CEC Control Register 0 (CECCTL0)" description of the relevant hardware manual. Setting the CECRXEN bit to 1 enables + * reception. Set this bit to 1 after determining the local address (setting the CADR register). */ + R_CEC->CADR = CEC_LOCAL_ADDR_TO_CADR(p_instance_ctrl->local_address); + p_instance_ctrl->cecctl0 |= (uint8_t) R_CEC_CECCTL0_CECRXEN_Msk; + R_CEC->CECCTL0 = p_instance_ctrl->cecctl0; + + /* Clear ack error */ + R_CEC->CECFC |= R_CEC_CECFC_ACKCTRG_Msk; + + /* Mark module as ready and update callback args */ + p_instance_ctrl->state = CEC_STATE_READY; + cb_args.event = CEC_EVENT_READY; + cb_args.status.local_address = p_instance_ctrl->local_address; + cb_args.status.state = p_instance_ctrl->state; + } + + if ((p_instance_ctrl->state != CEC_STATE_UNINIT)) + { + cb_args.event = tx_actv ? CEC_EVENT_TX_COMPLETE : (rx_actv ? CEC_EVENT_RX_COMPLETE : CEC_EVENT_READY); + r_cec_call_callback(p_instance_ctrl, &cb_args); + + /* Tx/Rx complete. Module is now idle */ + p_instance_ctrl->state = CEC_STATE_READY; + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Error ISR - Invoked after error detected. + **********************************************************************************************************************/ +void cec_error_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + /* Clear interrupt */ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + cec_instance_ctrl_t * p_instance_ctrl = (cec_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Capture error and send to application via callback */ + cec_callback_args_t cb_args; + cb_args.event = CEC_EVENT_ERR; + cb_args.p_context = p_instance_ctrl->p_context; + cb_args.status.local_address = (cec_addr_t) CEC_CADR_TO_LOCAL_ADDRESS(R_CEC->CADR); + cb_args.status.state = p_instance_ctrl->state; + cb_args.errors = (cec_error_t) R_CEC->CECES; + + /* Ignore ACKERR if address is not yet allocated (ackerr indicates address allocation success)*/ + if ((CEC_STATE_UNINIT != p_instance_ctrl->state) || (cb_args.errors & ~R_CEC_CECES_ACKERR_Msk)) + { + r_cec_call_callback(p_instance_ctrl, &cb_args); + + /* Mark module as idle if tx and rx inactive and mediaInit has succeeded */ + if (CEC_STATE_UNINIT != p_instance_ctrl->state) + { + p_instance_ctrl->state = CEC_STATE_READY; + } + + /* Clear errors after application processing */ + R_CEC->CECFC = CEC_CECFC_MASK_ALL; + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ceu/r_ceu.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ceu/r_ceu.c new file mode 100644 index 0000000000..8db01e0d1a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ceu/r_ceu.c @@ -0,0 +1,526 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*************************************************************************************************************************** + * Includes , "Project Includes" + ***************************************************************************************************************************/ +#include "r_ceu.h" +#include "r_ceu_cfg.h" + +/*************************************************************************************************************************** + * Macro definitions + ***************************************************************************************************************************/ +#define CEU_OPEN (0x52434555) // RCEU in hex + +/*************************************************************************************************************************** + * Typedef definitions + ***************************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * ceu_prv_ns_callback)(capture_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile ceu_prv_ns_callback)(capture_callback_args_t * p_args); +#endif + +/*************************************************************************************************************************** + * Imported global variables and functions (from other files) + ***************************************************************************************************************************/ + +/*************************************************************************************************************************** + * Exported global variables and functions (to be accessed by other files) + ***************************************************************************************************************************/ + +/* CEU API */ +const capture_api_t g_ceu_on_capture = +{ + .open = R_CEU_Open, + .close = R_CEU_Close, + .captureStart = R_CEU_CaptureStart, + .callbackSet = R_CEU_CallbackSet, + .statusGet = R_CEU_StatusGet +}; + +void ceu_isr(void); + +/*************************************************************************************************************************** + * Private global variables and functions + ***************************************************************************************************************************/ +static void ceu_call_callback(ceu_instance_ctrl_t * p_instance_ctrl, capture_callback_args_t * p_args); + +static void ceu_disable_interrupts(ceu_instance_ctrl_t * p_instance_ctrl); +static void ceu_enable_interrupts(ceu_instance_ctrl_t * p_instance_ctrl); + +/***********************************************************************************************************************//** + * @addtogroup CEU + * @{ + ***************************************************************************************************************************/ + +/*************************************************************************************************************************** + * Functions + ***************************************************************************************************************************/ + +/***********************************************************************************************************************//** + * CEU module initialization. + * + * Implements @ref capture_api_t::open + * + * The function provides initial configuration for the CEU module. Further initialization may be performed in + * @ref capture_api_t::captureStart. This function should be called once prior to calling any other CEU API functions. After + * the CEU is opened the Open function should not be called again without first calling the Close function. + * + * Example: + * @snippet r_ceu_example.c R_CEU_Open + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION One or more parameters is NULL. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **************************************************************************************************************************/ +fsp_err_t R_CEU_Open (capture_ctrl_t * const p_ctrl, capture_cfg_t const * const p_cfg) +{ + ceu_instance_ctrl_t * p_instance_ctrl = (ceu_instance_ctrl_t *) p_ctrl; + +#if CEU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(0 <= ((ceu_extended_cfg_t *) p_cfg->p_extend)->ceu_irq); + FSP_ERROR_RETURN(CEU_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Local variables */ + p_instance_ctrl->p_cfg = p_cfg; + ceu_extended_cfg_t * p_extend = (ceu_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + bool bus_width_8_bit = (CEU_DATA_BUS_SIZE_8_BIT == p_extend->data_bus_width); + uint32_t bytes_per_cycle = p_extend->data_bus_width + 1; + uint32_t bytes_per_line = p_cfg->x_capture_pixels * p_cfg->bytes_per_pixel; + uint32_t cycles_per_byte = (bus_width_8_bit ? 2 : 1); + uint32_t cycles_per_line = bytes_per_line / bytes_per_cycle; + uint32_t lines_per_image = p_cfg->y_capture_pixels; + uint32_t hfclp = cycles_per_line / cycles_per_byte; // Div by 2 for CEU_DATA_BUS_SIZE_8_BIT + uint32_t vfclp = lines_per_image; + uint32_t bytes_per_output_line = bytes_per_line; + uint32_t lines_per_output_image = lines_per_image; + + if ((CEU_CAPTURE_FORMAT_IMAGE_CAPTURE == p_extend->capture_format)) + { + uint32_t scale_down_factor = p_extend->scale_down_factor; + if (scale_down_factor & (R_CEU_CFLCR_HMANT_Msk | R_CEU_CFLCR_HFRAC_Msk)) + { + /* Horizontal scale down is enabled */ + hfclp = p_extend->h_output_size; + bytes_per_output_line = hfclp * p_cfg->bytes_per_pixel; + } + + if (scale_down_factor & (R_CEU_CFLCR_VMANT_Msk | R_CEU_CFLCR_VFRAC_Msk)) + { + /* Vertical scale down is enabled */ + vfclp = p_extend->v_output_size; + lines_per_output_image = vfclp; + } + } + + /* Initialize control structure data */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + + if (CEU_CAPTURE_FORMAT_DATA_ENABLE == p_extend->capture_format) + { + p_instance_ctrl->image_area_size = p_extend->image_area_size; + } + else + { + p_instance_ctrl->image_area_size = lines_per_output_image * bytes_per_output_line; + } + + /* Start the peripheral */ + R_BSP_MODULE_START(FSP_IP_CEU, 0U); + + /* Wait for module reset, if in progress + * See figure "Timing of software reset and restart of capturing" in the CEU section of the relevant hardware manual.. */ + FSP_HARDWARE_REGISTER_WAIT(R_CEU->CSTSR_b.CPTON, 0); + FSP_HARDWARE_REGISTER_WAIT(R_CEU->CAPSR_b.CPKIL, 0); + + /* Capture Filter Control Register (CFLCR) + * [Note] Must be 0 in data fetch modes and for interlace formats + */ + R_CEU->CFLCR = p_extend->scale_down_factor; + + /* Capture interface format register (CAIFR)*/ + R_CEU->CAIFR = 0; // Disable progressive capture + + /* capture control register (CAPCR) + * [Note] Continuous capture operations are possible only in image capture mode. */ + R_CEU->CAPCR = ((uint32_t) (p_extend->burst_mode << R_CEU_CAPCR_MTCM_Pos) & R_CEU_CAPCR_MTCM_Msk); // Unit for transferring data to bus bridge module; + + /* Capture Interface Control Register (CAMCR) */ + R_CEU->CAMCR = ((uint32_t) (p_extend->hsync_polarity << R_CEU_CAMCR_HDPOL_Pos) & R_CEU_CAMCR_HDPOL_Msk) | // Polarity for detection of the horizontal sync signal input + ((uint32_t) (p_extend->vsync_polarity << R_CEU_CAMCR_VDPOL_Pos) & R_CEU_CAMCR_VDPOL_Msk) | // Polarity for detection of the vertical sync signal input + ((uint32_t) (p_extend->capture_format << R_CEU_CAMCR_JPG_Pos) & R_CEU_CAMCR_JPG_Msk) | // Fetched data type + ((uint32_t) (p_extend->input_order << R_CEU_CAMCR_DTARY_Pos) & R_CEU_CAMCR_DTARY_Msk) | // Input order for Image Capture Mode + ((uint32_t) (p_extend->data_bus_width << R_CEU_CAMCR_DTIF_Pos) & R_CEU_CAMCR_DTIF_Msk) | // Digital image input pins from which data is to be captured + ((uint32_t) (p_extend->edge_info.dsel << R_CEU_CAMCR_DSEL_Pos) & R_CEU_CAMCR_DSEL_Msk) | // Edge for fetching external image data (D7 to D0) + ((uint32_t) (p_extend->edge_info.hdsel << R_CEU_CAMCR_HDSEL_Pos) & R_CEU_CAMCR_HDSEL_Msk) | // Edge for capturing external horizontal sync signal (HD) + ((uint32_t) (p_extend->edge_info.vdsel << R_CEU_CAMCR_VDSEL_Pos) & R_CEU_CAMCR_VDSEL_Msk); // Edge for capturing external vertical sync signal (VD) + + /* Capture Interface Cycle Register (CMCYR) - Used to detect illegal VD and illegal HD + * [Note] Should be 0 (disabled) for Data Enable Fetch mode. */ + R_CEU->CMCYR = (((uint32_t) p_cfg->x_capture_pixels << R_CEU_CMCYR_HCYL_Pos) & R_CEU_CMCYR_HCYL_Msk) | + (((uint32_t) p_cfg->y_capture_pixels << R_CEU_CMCYR_VCYL_Pos) & R_CEU_CMCYR_VCYL_Msk); + + /* Capture Interface Offset Register (CAMOR) + * [Note] Should be 0 for Data Enable Fetch mode. */ + uint32_t x_cycle_start = (uint32_t) p_cfg->x_capture_start_pixel * cycles_per_byte; + R_CEU->CAMOR = ((x_cycle_start << R_CEU_CAMOR_HOFST_Pos) & R_CEU_CAMOR_HOFST_Msk) | // capture start location from a horizontal sync signal (1-cycle units) + (((uint32_t) p_cfg->y_capture_start_pixel << R_CEU_CAMOR_VOFST_Pos) & R_CEU_CAMOR_VOFST_Msk); // capture start location from a vertical sync signal (1-HD units) + + /* Capture Interface Width Register (CAPWR) + * [Note] This register is used during Data synchronous fetch mode and image capture mode. */ + R_CEU->CAPWR = ((cycles_per_line << R_CEU_CAPWR_HWDTH_Pos) & R_CEU_CAPWR_HWDTH_Msk) | // Number of HD cycles to be captured, starting from CAMOR.HOFST + ((lines_per_image << R_CEU_CAPWR_VWDTH_Pos) & R_CEU_CAPWR_VWDTH_Msk); // Number of VD cycles (HD count) to be captured from CAMOR.VOFST + + /* Firewall Operation Control Register (CFWCR) + * Disable firewall in this call to open. If applicable, it will be re-enabled in the call to captureStart() */ + R_CEU->CFWCR = 0; + + /* Capture Filter Size Clip Register (CFSZR) + * [Note] In data synchronous fetch mode, set HFCLP to CAPWR.HWDTH/2 in 8-bit interface mode + * [Note] Only when the scale-down filter is used, if image is larger than VGA, the output image must be equal to or larger than SubQCIF and equal to or smaller than VGA + * [Note] The clipping size specified in CFSZR must be equal to or smaller than the number of pixels output from the capture filter.*/ + R_CEU->CFSZR = ((vfclp << R_CEU_CFSZR_VFCLP_Pos) & R_CEU_CFSZR_VFCLP_Msk) | // Vertical clipping value of the filter output size (4-pixel units) + ((hfclp << R_CEU_CFSZR_HFCLP_Pos) & R_CEU_CFSZR_HFCLP_Msk); // Horizontal clipping value of the filter output size (4-pixel units) + + /* Capture Destination Width Register (CDWDR) + * [Note] In data synchronous fetch mode, set CHDW to CAPWR.HWDTH * 2 for 16-bit interface mode */ + R_CEU->CDWDR = (CEU_CAPTURE_FORMAT_IMAGE_CAPTURE == p_extend->capture_format) ? + bytes_per_output_line / 2 : bytes_per_output_line; // Horizontal image size in the memory where image is to be stored (4-byte units) + + /* Capture Low-Pass Filter Control Register (CLFCR) */ + R_CEU->CLFCR = 0U; + + /* Capture Data Output Control Register (CDOCR) */ + R_CEU->CDOCR = + (((uint32_t) p_extend->byte_swapping.swap_8bit_units << R_CEU_CDOCR_COBS_Pos) & R_CEU_CDOCR_COBS_Msk) | // Swapping 8-bit units for data output from the CEU + (((uint32_t) p_extend->byte_swapping.swap_16bit_units << R_CEU_CDOCR_COWS_Pos) & R_CEU_CDOCR_COWS_Msk) | // Swapping 16-bit units for data output from the CEU + (((uint32_t) p_extend->byte_swapping.swap_32bit_units << R_CEU_CDOCR_COLS_Pos) & R_CEU_CDOCR_COLS_Msk) | // Swapping 32-bit units for data output from the CEU + (((uint32_t) p_extend->output_format << R_CEU_CDOCR_CDS_Pos) & R_CEU_CDOCR_CDS_Msk); // Image format for data captured in the YCbCr 422 format (Must be set to 1 in Data Fetch capture modes) + + /* Clear any previous buffer address */ + p_instance_ctrl->p_buffer = 0U; + + /* Mark driver as open + * [Note] Open driver prior to enabling interrupts to fascilitate any required callback processing */ + p_instance_ctrl->open = CEU_OPEN; + + ceu_enable_interrupts(p_instance_ctrl); + + return FSP_SUCCESS; +} /* End of function R_CEU_Open() */ + +/***********************************************************************************************************************//** + * Stops and closes the transfer interface. + * + * Implements @ref capture_api_t::close + * + * Stops any active captures, clears internal driver state-data, disables interrupts, and powers off the CEU peripheral. + * + * Example: + * @snippet r_ceu_example.c R_CEU_Close + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION One or more parameters is NULL. + * @retval FSP_ERR_NOT_OPEN Open has not been successfully called. + **************************************************************************************************************************/ +fsp_err_t R_CEU_Close (capture_ctrl_t * const p_ctrl) +{ + ceu_instance_ctrl_t * p_instance_ctrl = (ceu_instance_ctrl_t *) p_ctrl; + +#if CEU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(CEU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + ceu_disable_interrupts(p_instance_ctrl); + + R_CEU->CAPSR = R_CEU_CAPSR_CPKIL_Msk; // Setting the CPKIL stops capture + + /* Mark driver as closed + * [Note] Set interface as closed after disabling interrupts to fascilitate any API calls in the application callback */ + p_instance_ctrl->open = 0U; + + R_BSP_MODULE_STOP(FSP_IP_CEU, 0U); + + return FSP_SUCCESS; +} + +/***********************************************************************************************************************//** + * Starts a capture. + * + * Implements @ref capture_api_t::captureStart. + * + * Sets up the interface to transfer data from the CEU into the specifiec buffer. Configures the CEU settings as previously + * set by the @ref capture_api_t::open API. When a capture is complete the callback registered during @ref capture_api_t::open API + * call or by @ref capture_api_t::callbackSet API will be called. + * + * Example: + * @snippet r_ceu_example.c R_CEU_CaptureStart + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION One or more parameters is NULL. + * @retval FSP_ERR_NOT_OPEN Open has not been successfully called. + * @retval FSP_ERR_INVALID_ADDRESS Invalid buffer address alignment. + * @retval FSP_ERR_IN_USE Capture is in progress. + * @retval FSP_ERR_INVALID_STATE Capture is pending. + * @retval FSP_ERR_NOT_INITIALIZED Callback function has not been set. + **************************************************************************************************************************/ +fsp_err_t R_CEU_CaptureStart (capture_ctrl_t * const p_ctrl, uint8_t * const p_buffer) +{ + ceu_instance_ctrl_t * p_instance_ctrl = (ceu_instance_ctrl_t *) p_ctrl; + +#if CEU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT((NULL != p_buffer)); // buffer must not be NULL + FSP_ERROR_RETURN(0 == ((uint32_t) p_buffer & 0x07), FSP_ERR_INVALID_ADDRESS); // Buffer must be 8 byte aligned + FSP_ERROR_RETURN(CEU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_instance_ctrl->p_callback, FSP_ERR_NOT_INITIALIZED); +#endif + + /* Return error if peripheral is in use + * See figure "Timing of software reset and restart of capturing" in the CEU section of the relevant hardware manual.. */ + FSP_ERROR_RETURN(R_CEU->CSTSR_b.CPTON == 0x0, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(R_CEU->CAPSR_b.CPKIL == 0x0, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(R_CEU->CAPSR_b.CE == 0x0, FSP_ERR_INVALID_STATE); + + ceu_extended_cfg_t * p_extend = (ceu_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + p_instance_ctrl->p_buffer = p_buffer; + if ((CEU_CAPTURE_FORMAT_DATA_ENABLE == p_extend->capture_format)) + { + /* Firewall Operation Control Register (CFWCR) + * [Note] Set CFWCR to zero in Image Capture or Data Synchronous Fetch modes + * P [Note] Firewall address is upper 27-bits of memory address. Lowest 5 bits assumed to be be 0x1F. */ + uint32_t firewall_address = (uint32_t) p_buffer + p_instance_ctrl->image_area_size - 1; + R_CEU->CFWCR = R_CEU_CFWCR_FWE_Msk | (firewall_address & R_CEU_CFWCR_FWV_Msk); + } + + /* Image capture mode: Set luminance component start address + * Data fetch modes: Set capture start address */ + R_CEU->CDAYR = (uint32_t) p_instance_ctrl->p_buffer; // Set start address of memory area for write + + if ((CEU_CAPTURE_FORMAT_IMAGE_CAPTURE == p_extend->capture_format)) + { + /* Set chrominance component start address */ + R_CEU->CDACR = (uint32_t) (&p_instance_ctrl->p_buffer[p_instance_ctrl->image_area_size / 2]); + } + + /* Clear pending flags before starting capture */ + R_CEU->CETCR = 0; + + /* Start Capturing (at next V-Sync) */ + R_CEU->CAPSR = R_CEU_CAPSR_CE_Msk; + + return FSP_SUCCESS; +} /* End of function R_CEU_CaptureStart() */ + +/***********************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * + * Implements @ref capture_api_t::callbackSet. + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION One or more parameters is NULL. + * @retval FSP_ERR_NOT_OPEN Open has not been successfully called. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **************************************************************************************************************************/ +fsp_err_t R_CEU_CallbackSet (capture_ctrl_t * const p_ctrl, + void ( * p_callback)(capture_callback_args_t *), + void * const p_context, + capture_callback_args_t * const p_callback_memory) +{ + ceu_instance_ctrl_t * p_instance_ctrl = (ceu_instance_ctrl_t *) p_ctrl; + +#if (CEU_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(CEU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(p_callback); +#endif + (void) p_instance_ctrl; + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CEU_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + capture_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif + + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(capture_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} /* End of function R_CEU_CallbackSet() */ + +/***********************************************************************************************************************//** + * Provides the ceu operating status. + * + * Implements @ref capture_api_t::statusGet. + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION One or more parameters is NULL. + * @retval FSP_ERR_NOT_OPEN Open has not been successfully called. + **************************************************************************************************************************/ +fsp_err_t R_CEU_StatusGet (capture_ctrl_t * const p_ctrl, capture_status_t * p_status) +{ + ceu_instance_ctrl_t * p_instance_ctrl = (ceu_instance_ctrl_t *) p_ctrl; + +#if (CEU_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_status); + FSP_ERROR_RETURN(CEU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + if (R_CEU->CAPSR_b.CPKIL) + { + p_status->state = CAPTURE_STATE_BUSY; + } + else + { + p_status->state = (capture_state_t) (R_CEU->CSTSR_b.CPTON || R_CEU->CAPSR_b.CE); + } + + p_status->p_buffer = (uint32_t *) p_instance_ctrl->p_buffer; + p_status->data_size = R_CEU->CDSSR; + + return FSP_SUCCESS; +} /* End of function R_CEU_StatusGet() */ + +/*******************************************************************************************************************//** + * @} (end addtogroup CEU) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Disable all ceu interrupts + **********************************************************************************************************************/ +static void ceu_disable_interrupts (ceu_instance_ctrl_t * p_instance_ctrl) +{ + R_CEU->CEIER = 0U; /* Disable all */ + + ceu_extended_cfg_t * p_extend = (ceu_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + R_BSP_IrqDisable(p_extend->ceu_irq); + R_FSP_IsrContextSet(p_extend->ceu_irq, NULL); +} + +/*********************************************************************************************************************** + * Enable ceu interrupts + **********************************************************************************************************************/ +static void ceu_enable_interrupts (ceu_instance_ctrl_t * p_instance_ctrl) +{ + ceu_extended_cfg_t * p_extend = (ceu_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + p_instance_ctrl->interrupts_enabled = p_extend->interrupts_enabled; + + R_BSP_IrqCfgEnable(p_extend->ceu_irq, p_extend->ceu_ipl, p_instance_ctrl); + + /* Capture Event Flag CLear Register (CETCR) */ + R_CEU->CETCR = 0U; /* clear all */ + R_CEU->CEIER = p_instance_ctrl->interrupts_enabled; /* Set enabled interrupts */ +} + +/*********************************************************************************************************************** + * Common ISR callback wrapper. Manages callback argument memory and security context. + **********************************************************************************************************************/ +static void ceu_call_callback (ceu_instance_ctrl_t * p_instance_ctrl, capture_callback_args_t * p_args) +{ + capture_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + capture_callback_args_t * p_args_memory = p_instance_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + ceu_prv_ns_callback p_callback = (ceu_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } +} + +/*********************************************************************************************************************** + * interrupt service routine + **********************************************************************************************************************/ +extern void ceu_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + ceu_event_t events = (ceu_event_t) R_CEU->CETCR; + R_CEU->CETCR = ~events; + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + ceu_instance_ctrl_t * p_instance_ctrl = (ceu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if (NULL != p_instance_ctrl->p_callback) + { + capture_callback_args_t args; + args.event = (capture_event_t) (events & p_instance_ctrl->interrupts_enabled); + args.event_status = 0; // Unused + args.interrupt_status = 0; // Unused + args.p_buffer = p_instance_ctrl->p_buffer; + args.p_context = p_instance_ctrl->p_context; + ceu_call_callback(p_instance_ctrl, &args); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cgc/r_cgc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cgc/r_cgc.c new file mode 100644 index 0000000000..1cfaed503f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_cgc/r_cgc.c @@ -0,0 +1,2834 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_cgc.h" +#include "r_cgc_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "CGC" in ASCII, used to determine if the module is open. */ +#define CGC_OPEN (0x00434743U) + +#define CGC_PRV_SUBCLOCK_LOCO_HZ (32768U) + +#define CGC_PRV_OSTDCR_OSC_STOP_ENABLE (0x81U) + +#if 3U == BSP_FEATURE_CGC_PLLCCR_TYPE + +/* PLLMUL starts at bit 8, but PLLMULNF at bits 7:6 which can be treated as part of PLLMUL when setting it. */ + #define CGC_PRV_PLLCCR_PLLMUL_BIT (6U) + +/* PLLMUL + PLLMULNF in PLLCCR is 10 bits wide. */ + #define CGC_PRV_PLLCCR_PLLMUL_MASK (0x3FFU) +#elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + +/* PLLMUL in PLLCCR is 8 bits wide. */ + #define CGC_PRV_PLLCCR_PLLMUL_MASK (0xFFU) + +/* BIT 2 in PLLCCR is 1 by default */ + #define CGC_PRV_PLLCCR_PLLMUL_DEFAULT_BIT (0x04U) +#elif 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + +/* PLLMUL in PLLCCR is 5 bits wide. */ + #define CGC_PRV_PLLCCR_PLLMUL_MASK (0x1FU) +#elif 6U == BSP_FEATURE_CGC_PLLCCR_TYPE + +/* PLLMUL starts at bit 8, but PLLMULNF at bits 7:6 which can be treated as part of PLLMUL when setting it. */ + #define CGC_PRV_PLLCCR_PLLMUL_BIT (6U) + +/* PLLMUL + PLLMULNF in PLLCCR is 11 bits wide. */ + #define CGC_PRV_PLLCCR_PLLMUL_MASK (0x7FFU) +#else + +/* PLLMUL in PLLCCR is 6 bits wide. */ + #define CGC_PRV_PLLCCR_PLLMUL_MASK (0x3FU) +#endif + +#if (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (6U != BSP_FEATURE_CGC_PLLCCR_TYPE) + +/* PLLMUL in PLLCCR starts at bit 8. */ + #define CGC_PRV_PLLCCR_PLLMUL_BIT (8U) +#endif + +/* PLSRCSEL in PLLCCR starts at bit 4. */ +#define CGC_PRV_PLLCCR_PLSRCSEL_BIT (4U) + +/* PLLMUL in PLLCCR2 is 5 bits wide. */ +#define CGC_PRV_PLLCCR2_PLLMUL_MASK (0x1FU) + +/* PLODIV in PLLCCR2 starts at bit 6. */ +#define CGC_PRV_PLLCCR2_PLODIV_BIT (6U) + +/* PLODIVx in PLLCCR2 are 4 bits wide. */ +#define CGC_PRV_PLLCCR2_PLODIVX_MASK (0xFU) + +/* PLODIVP in PLLCCR2 starts at bit 0. */ +#define CGC_PRV_PLLCCR2_PLODIVP_BIT (0U) + +/* PLODIVP in PLLCCR2 starts at bit 4. */ +#define CGC_PRV_PLLCCR2_PLODIVQ_BIT (4U) + +/* PLODIVP in PLLCCR2 starts at bit 8. */ +#define CGC_PRV_PLLCCR2_PLODIVR_BIT (8U) + +#if 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + +/* Bit-mask of values that must be 1 for PLLCCR type 4. */ + #define CGC_PRV_PLLCCR_RESET_VALUE (0x04U) +#endif + +#if BSP_PRV_PLL_SUPPORTED + #if BSP_PRV_PLL2_SUPPORTED + #define CGC_PRV_NUM_CLOCKS ((uint8_t) CGC_CLOCK_PLL2 + 1U) + #define CGC_PRV_MAX_PLL_OUTPUTS ((BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS > \ + BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) ? \ + BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS \ + : BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS) + #else + #define CGC_PRV_NUM_CLOCKS ((uint8_t) CGC_CLOCK_PLL + 1U) + #define CGC_PRV_MAX_PLL_OUTPUTS (BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS) + #endif +#else + #define CGC_PRV_NUM_CLOCKS ((uint8_t) CGC_CLOCK_SUBCLOCK + 1U) +#endif + +/* Mask used to isolate dividers for ICLK and FCLK. */ +#define CGC_PRV_SCKDIVCR_ICLK_FCLK_MASK (0x77000000U) + +#define CGC_PRV_HOCOCR ((uint8_t *) &R_SYSTEM->HOCOCR) +#define CGC_PRV_MOCOCR ((uint8_t *) &R_SYSTEM->MOCOCR) +#define CGC_PRV_LOCOCR ((uint8_t *) &R_SYSTEM->LOCOCR) +#define CGC_PRV_MOSCCR ((uint8_t *) &R_SYSTEM->MOSCCR) +#define CGC_PRV_SOSCCR ((uint8_t *) &R_SYSTEM->SOSCCR) +#define CGC_PRV_PLLCR ((uint8_t *) &R_SYSTEM->PLLCR) +#define CGC_PRV_PLL2CR ((uint8_t *) &R_SYSTEM->PLL2CR) + +/* The closest supported power mode to use when exiting low speed or low voltage mode. */ +#if BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ > 0U + #define CGC_PRV_EXIT_LOW_SPEED_MODE (BSP_PRV_OPERATING_MODE_MIDDLE_SPEED) +#else + #define CGC_PRV_EXIT_LOW_SPEED_MODE (BSP_PRV_OPERATING_MODE_HIGH_SPEED) +#endif + +/* Scaling factor for calculating the multiplier for PLLCCR type 3. */ +#define CGC_PRV_PLL_MUL_FACTOR (6U) + +/* Scaling factor for PLLMUL values; using scaling of 6. */ +#define CGC_PRV_PLL_MUL_COEFF (6U) +#define CGC_PRV_PLL_MUL_NF_COEFF (2U) + +/* Mask of the uppermost bit of all dividers in SCKDIVCR that are valid when oscillation stop detection is enabled. */ +#define CGC_PRV_SCKDIVCR_UPPER_BIT (BSP_PRV_SCKDIVCR_MASK & 0x44444444U) +#define CGC_PRV_SCKDIVCR_DIV_3_BITS (0x88888888U) + +#if BSP_FEATURE_CGC_HAS_CPUCLK + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + #define CGC_PRV_SCKDIVCR2_DIV_3_BITS (0x8888U) + #define CGC_PRV_SCKDIVCR2_NUM_CLOCKS (4U) + #else + #define CGC_PRV_SCKDIVCR2_DIV_3_BITS (0x8U) + #define CGC_PRV_SCKDIVCR2_NUM_CLOCKS (1U) + #endif +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Private enumeration used to tell if a clock is running or not. */ +typedef enum e_cgc_prv_clock_state +{ + CGC_PRV_CLOCK_STATE_STOPPED = 0, + CGC_PRV_CLOCK_STATE_RUNNING = 1, +} cgc_prv_clock_state_t; + +/* Private enumeration used to specify whether changing just LPM operating modes or both LPM operating modes and CGC. */ +typedef enum e_cgc_prv_change +{ + CGC_PRV_CHANGE_LPM = 0, + CGC_PRV_CHANGE_LPM_CGC = 1, +} cgc_prv_change_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * cgc_prv_ns_callback)(cgc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile cgc_prv_ns_callback)(cgc_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if !BSP_FEATURE_CGC_REGISTER_SET_B +static bool r_cgc_low_speed_or_voltage_mode_possible(uint32_t sckdivcr, uint8_t ostdcr); + + #if BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT +static void r_cgc_nmi_internal_callback(bsp_grp_irq_t irq); + + #endif + + #if BSP_FEATURE_CGC_HAS_OSTDCSE +static fsp_err_t r_cgc_open_irq_cfg(cgc_instance_ctrl_t * const p_instance_ctrl, cgc_extended_cfg_t * const p_extend); +static void r_cgc_disable_irq(IRQn_Type irq); + + #endif +#endif + +static fsp_err_t r_cgc_clock_check(cgc_clock_t const clock_source); +static bool r_cgc_stabilization_check(cgc_clock_t clock, cgc_prv_clock_state_t status); +static void r_cgc_clock_change(cgc_clock_t clock, cgc_clock_change_t state); +static cgc_prv_clock_state_t r_cgc_clock_run_state_get(cgc_clock_t clock); +static void r_cgc_post_change(cgc_prv_change_t change); +static void r_cgc_pre_change(cgc_prv_change_t change); + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + + #if BSP_FEATURE_CGC_HAS_SOPCCR +static bool r_cgc_subosc_mode_possible(uint32_t sckdivcr); + + #endif + +static void r_cgc_operating_mode_reduce(uint32_t sckdivcr); + +#endif + +#if CGC_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_cgc_common_parameter_checking(cgc_instance_ctrl_t * p_instance_ctrl); +static fsp_err_t r_cgc_check_config_dividers(cgc_divider_cfg_t const * const p_divider_cfg); +static fsp_err_t r_cgc_clock_source_has_support(cgc_clock_t const clock_source); + + #if BSP_FEATURE_CGC_HAS_CPUCLK +static fsp_err_t r_cgc_divider_constraint_check(cgc_divider_cfg_t const * const p_divider_cfg); + + #endif + + #if BSP_PRV_PLL_SUPPORTED +static fsp_err_t r_cgc_pll_parameter_check(cgc_pll_cfg_t const * const p_pll_cfg, bool verify_source_stable); + + #endif +#endif + +#if BSP_PRV_PLL_SUPPORTED || BSP_PRV_PLL2_SUPPORTED +static uint32_t r_cgc_pllccr_calculate(cgc_pll_cfg_t const * const p_pll_cfg); + + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) +static uint16_t r_cgc_pllccr2_calculate(cgc_pll_cfg_t const * const p_pll_cfg); + + #endif + #if BSP_PRV_PLL_SUPPORTED + +static inline cgc_clock_t r_cgc_pll_clocksource_get(void); + + #endif + + #if BSP_PRV_PLL2_SUPPORTED && CGC_CFG_PARAM_CHECKING_ENABLE + +static inline cgc_clock_t r_cgc_pll2_clocksource_get(void); + + #endif + +static fsp_err_t r_cgc_pll_hz_calculate(cgc_pll_cfg_t const * const p_pll_cfg, + cgc_clock_t pll, + uint32_t * const p_pll_hz); +static void r_cgc_pll_cfg(cgc_pll_cfg_t const * const p_pll_cfg, + cgc_clock_t pll, + uint32_t const * const pll_hz, + uint32_t pllccr); +static fsp_err_t r_cgc_pllccr_pll_hz_calculate(cgc_pll_cfg_t const * const p_pll_cfg, + cgc_clock_t pll, + uint32_t * const p_pll_hz, + uint32_t * const p_pllccr); + +#endif + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void cgc_mostd_isr(void); +void cgc_sostd_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +#if BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT + +/** Global pointer to control structure for use by the NMI callback. */ +static cgc_instance_ctrl_t * gp_cgc_ctrl = NULL; +#endif + +/* This array stores the address of the register containing the stop bit for each clock. All of these registers are + * 8-bit registers and only bit 0 is valid. All other bits are read as 0 and should be written to 0. Bit 0 of each + * of these registers indicates that the corresponding clock is stopped when set, or that the corresponding clock + * is operating when cleared. */ +static uint8_t volatile * const gp_cgc_clock_stp_registers[CGC_PRV_NUM_CLOCKS] = +{ + [CGC_CLOCK_HOCO] = CGC_PRV_HOCOCR, + [CGC_CLOCK_MOCO] = CGC_PRV_MOCOCR, + [CGC_CLOCK_LOCO] = CGC_PRV_LOCOCR, + [CGC_CLOCK_MAIN_OSC] = CGC_PRV_MOSCCR, + [CGC_CLOCK_SUBCLOCK] = CGC_PRV_SOSCCR, +#if BSP_PRV_PLL_SUPPORTED + [CGC_CLOCK_PLL] = CGC_PRV_PLLCR, +#endif +#if BSP_PRV_PLL2_SUPPORTED + [CGC_CLOCK_PLL2] = CGC_PRV_PLL2CR, +#endif +}; + +/* How long of a software delay is required after starting each clock before activating it as the system clock. */ +static const uint8_t g_cgc_software_wait_us[CGC_PRV_NUM_CLOCKS] = +{ + [CGC_CLOCK_HOCO] = 0U, // HOCO has a stabilization wait flag + [CGC_CLOCK_MOCO] = BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US, + [CGC_CLOCK_LOCO] = BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, + [CGC_CLOCK_MAIN_OSC] = 0U, // Main oscillator has a stabilization wait flag + [CGC_CLOCK_SUBCLOCK] = 0U, // Subclock is assumed to be stable +#if BSP_PRV_PLL_SUPPORTED + [CGC_CLOCK_PLL] = 0U, // PLL has a stabilization wait flag +#endif +#if BSP_PRV_PLL2_SUPPORTED + [CGC_CLOCK_PLL2] = 0U, // PLL2 has a stabilization wait flag +#endif +}; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +const cgc_api_t g_cgc_on_cgc = +{ + .open = R_CGC_Open, + .clocksCfg = R_CGC_ClocksCfg, + .clockStart = R_CGC_ClockStart, + .clockStop = R_CGC_ClockStop, + .clockCheck = R_CGC_ClockCheck, + .systemClockSet = R_CGC_SystemClockSet, + .systemClockGet = R_CGC_SystemClockGet, + .oscStopDetectEnable = R_CGC_OscStopDetectEnable, + .oscStopDetectDisable = R_CGC_OscStopDetectDisable, + .oscStopStatusClear = R_CGC_OscStopStatusClear, + .callbackSet = R_CGC_CallbackSet, + .close = R_CGC_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup CGC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize the CGC API. Implements @ref cgc_api_t::open. + * + * Example: + * @snippet r_cgc_example.c R_CGC_Open + * + * @retval FSP_SUCCESS CGC successfully initialized. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **********************************************************************************************************************/ +fsp_err_t R_CGC_Open (cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg) +{ + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + +#if CGC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN(CGC_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + +#if BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT + + /* Store the control structure in a private global variable so the oscillation stop detection function can be + * called from the NMI callback. */ + gp_cgc_ctrl = p_instance_ctrl; +#endif + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + +#if BSP_FEATURE_CGC_HAS_OSTDCSE + p_instance_ctrl->p_extend = p_cfg->p_extend; + fsp_err_t err = FSP_SUCCESS; + + /* Configure and enable interrupts. */ + err = r_cgc_open_irq_cfg(p_instance_ctrl, (cgc_extended_cfg_t *) p_instance_ctrl->p_extend); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Mark the module as open so other APIs can be used. */ + p_instance_ctrl->open = CGC_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reconfigures all main system clocks. This API can be used for any of the following purposes: + * - start or stop clocks + * - change the system clock source + * - configure the PLL/PLL2 multiplication and division ratios when starting the PLL + * - configure the division ratios when starting the HOCO/MOCO/MOSC + * - change the system dividers + * + * If the requested system clock source has a stabilization flag, this function blocks waiting for the stabilization + * flag of the requested system clock source to be set. If the requested system clock source was just started and it + * has no stabilization flag, this function blocks for the stabilization time required by the requested system clock + * source according to the Electrical Characteristics section of the hardware manual. If the requested system clock + * source has no stabilization flag and it is already running, it is assumed to be stable and this function will not + * block. If the requested system clock is the subclock, the subclock must be stable prior to calling this function. + * + * The internal dividers (cgc_clocks_cfg_t::divider_cfg) are subject to constraints described in footnotes of the + * hardware manual table detailing specifications for the clock generation circuit for the internal clocks for the MCU. + * For example: + * - RA6M3: see footnotes of table "Specifications of the clock generation circuit for the internal clocks" + * in the CGC section of the relevant hardware manual. + * - RA2A1: see footnotes of table "Clock generation circuit specifications for the internal clocks" + * in the CGC section of the relevant hardware manual. + * + * Do not attempt to stop the requested clock source or the source of a PLL if the PLL will be running after this + * operation completes. + * + * Implements @ref cgc_api_t::clocksCfg. + * + * Example: + * @snippet r_cgc_example.c R_CGC_ClocksCfg + * + * @retval FSP_SUCCESS Clock configuration applied successfully. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_IN_USE Attempt to stop the current system clock or the PLL source clock. + * @retval FSP_ERR_CLOCK_ACTIVE PLL configuration cannot be changed while PLL is running. + * @retval FSP_ERR_OSC_STOP_DET_ENABLED PLL multiplier must be less than 20 if oscillation stop detect is enabled and + * the input frequency is less than 12.5 MHz. + * @retval FSP_ERR_NOT_STABILIZED PLL clock source is not stable. + * @retval FSP_ERR_PLL_SRC_INACTIVE PLL clock source is not running. + * @retval FSP_ERR_INVALID_STATE The subclock must be running before activating HOCO with FLL. + **********************************************************************************************************************/ +fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * const p_clock_cfg) +{ + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = FSP_SUCCESS; + FSP_PARAMETER_NOT_USED(err); // unused in some build configurations +#if CGC_CFG_PARAM_CHECKING_ENABLE + err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_clock_cfg); + + #if 0 == BSP_FEATURE_CGC_EXECUTE_FROM_LOCO + FSP_ASSERT(CGC_CLOCK_LOCO != p_clock_cfg->system_clock); + #endif + + /* Check the system clock source */ + err = r_cgc_clock_source_has_support(p_clock_cfg->system_clock); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if !BSP_FEATURE_CGC_HAS_MOCO + FSP_ASSERT(CGC_CLOCK_CHANGE_NONE == p_clock_cfg->moco_state); + #endif + #if !BSP_FEATURE_CGC_HAS_MOSC + FSP_ASSERT(CGC_CLOCK_CHANGE_NONE == p_clock_cfg->mainosc_state); + #endif +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + cgc_divider_cfg_t divider_cfg; + divider_cfg = p_clock_cfg->divider_cfg; + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + #if !BSP_FEATURE_CGC_HAS_CPUCLK + divider_cfg.sckdivcr2 = 0; + #endif + + #if BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + + /* Some MCUs require the bits normally used for BCLK to be set the same as PCLKB. */ + divider_cfg.sckdivcr_b.bclk_div = divider_cfg.sckdivcr_b.pclkb_div; + #endif + + #if BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK + + /* Some MCUs require the bits normally used for NPUCLK to be set the same as MRICLK. */ + divider_cfg.sckdivcr2_b.npuclk_div = divider_cfg.sckdivcr2_b.mriclk_div; + #endif +#endif + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Check dividers. */ + err = r_cgc_check_config_dividers(÷r_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + cgc_clock_t requested_system_clock = p_clock_cfg->system_clock; +#if !BSP_FEATURE_CGC_REGISTER_SET_B + cgc_clock_t current_system_clock = (cgc_clock_t) R_SYSTEM->SCKSCR; +#else + cgc_clock_t current_system_clock = (cgc_clock_t) bsp_prv_clock_source_get(); +#endif + + cgc_clock_change_t options[CGC_PRV_NUM_CLOCKS]; + options[CGC_CLOCK_HOCO] = p_clock_cfg->hoco_state; + options[CGC_CLOCK_LOCO] = p_clock_cfg->loco_state; + options[CGC_CLOCK_MOCO] = p_clock_cfg->moco_state; + options[CGC_CLOCK_MAIN_OSC] = p_clock_cfg->mainosc_state; + options[CGC_CLOCK_SUBCLOCK] = CGC_CLOCK_CHANGE_NONE; +#if CGC_CFG_PARAM_CHECKING_ENABLE + #if BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* HOCO must be running in low voltage mode. */ + FSP_ASSERT(CGC_CLOCK_CHANGE_STOP != p_clock_cfg->hoco_state); + #endif + #if BSP_PRV_HOCO_USE_FLL + + /* Determine if HOCO will be started. */ + #if BSP_PRV_PLL2_SUPPORTED + uint8_t start_hoco = (CGC_CLOCK_CHANGE_START == p_clock_cfg->hoco_state) || + ((CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) && + (CGC_CLOCK_HOCO == p_clock_cfg->pll_cfg.source_clock)) || + ((CGC_CLOCK_CHANGE_START == p_clock_cfg->pll2_state) && + (CGC_CLOCK_HOCO == p_clock_cfg->pll2_cfg.source_clock)); + #else + uint8_t start_hoco = (CGC_CLOCK_CHANGE_START == p_clock_cfg->hoco_state) || + ((CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) && + (CGC_CLOCK_HOCO == p_clock_cfg->pll_cfg.source_clock)); + #endif + + /* Subclock must be running to use FLL. */ + FSP_ERROR_RETURN(!(start_hoco && R_SYSTEM->SOSCCR), FSP_ERR_INVALID_STATE); + #endif +#endif +#if BSP_PRV_PLL_SUPPORTED + options[CGC_CLOCK_PLL] = p_clock_cfg->pll_state; + + /* The PLL source variable is used to prevent stopping the PLL source if the PLL is the current system clock until + * after the system clock is changed. Set PLL source to subclock if PLL source is not used since the subclock + * cannot be changed in this function. */ + cgc_clock_t current_pll_source = CGC_CLOCK_SUBCLOCK; + bool pll_active = r_cgc_clock_run_state_get(CGC_CLOCK_PLL); + if (pll_active) + { + current_pll_source = r_cgc_pll_clocksource_get(); + } + + uint32_t pll_hz[BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS] = {0U}; + uint32_t pllccr = 0U; + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) + { + err = + r_cgc_pllccr_pll_hz_calculate(&p_clock_cfg->pll_cfg, CGC_CLOCK_PLL, pll_hz, &pllccr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Check the PLL parameters if starting the PLL. */ + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) + { + err = + r_cgc_pll_parameter_check(&p_clock_cfg->pll_cfg, + (CGC_CLOCK_CHANGE_START != options[p_clock_cfg->pll_cfg.source_clock])); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif +#endif + +#if BSP_PRV_PLL2_SUPPORTED + options[CGC_CLOCK_PLL2] = p_clock_cfg->pll2_state; + + uint32_t pll2_hz[BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS] = {0U}; + uint32_t pll2ccr = 0U; + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll2_state) + { + err = + r_cgc_pllccr_pll_hz_calculate(&p_clock_cfg->pll2_cfg, CGC_CLOCK_PLL2, pll2_hz, &pll2ccr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Check the PLL2 parameters if starting PLL2. */ + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll2_state) + { + err = + r_cgc_pll_parameter_check(&p_clock_cfg->pll2_cfg, + (CGC_CLOCK_CHANGE_START != options[p_clock_cfg->pll2_cfg.source_clock])); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif +#endif + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Do not attempt to stop the new system clock. */ + FSP_ERROR_RETURN(CGC_CLOCK_CHANGE_STOP != options[p_clock_cfg->system_clock], FSP_ERR_IN_USE); + #if BSP_PRV_PLL_SUPPORTED + + /* Do not attempt to stop the source of the PLL if the PLL will be running after this operation completes. */ + if (CGC_CLOCK_CHANGE_STOP != options[CGC_CLOCK_PLL]) + { + if ((CGC_CLOCK_CHANGE_START == options[CGC_CLOCK_PLL]) || pll_active) + { + FSP_ERROR_RETURN(CGC_CLOCK_CHANGE_STOP != options[p_clock_cfg->pll_cfg.source_clock], FSP_ERR_IN_USE); + } + } + #endif + #if BSP_PRV_PLL2_SUPPORTED + + /* Do not attempt to stop the source of PLL2 if PLL2 will be running after this operation completes. */ + if (CGC_CLOCK_CHANGE_STOP != options[CGC_CLOCK_PLL2]) + { + if ((CGC_CLOCK_CHANGE_START == options[CGC_CLOCK_PLL2]) || r_cgc_clock_run_state_get(CGC_CLOCK_PLL2)) + { + FSP_ERROR_RETURN(CGC_CLOCK_CHANGE_STOP != options[p_clock_cfg->pll2_cfg.source_clock], FSP_ERR_IN_USE); + } + } + #endif +#endif + + /* Prerequisite to starting clocks or changing the system clock. */ + r_cgc_pre_change(CGC_PRV_CHANGE_LPM_CGC); + +#if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->hoco_state) + { + /* If FLL is to be used set FLLCR1 before starting HOCO. */ + R_SYSTEM->FLLCR1 = 1U; + } +#endif + +#if BSP_PRV_PLL_SUPPORTED + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) + { + /* Configure PLL and store PLL frequency in BSP. */ + r_cgc_pll_cfg(&p_clock_cfg->pll_cfg, CGC_CLOCK_PLL, pll_hz, pllccr); + + #if 4U != BSP_FEATURE_CGC_PLLCCR_TYPE + if (CGC_CLOCK_CHANGE_START == options[p_clock_cfg->pll_cfg.source_clock]) + { + /* Need to start PLL source clock and let it stabilize before starting PLL. */ + r_cgc_clock_change(p_clock_cfg->pll_cfg.source_clock, CGC_CLOCK_CHANGE_START); + + #if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_HOCO == p_clock_cfg->pll_cfg.source_clock) + { + /* If FLL is enabled and HOCO is turned on an additional stabilization wait is required before + * checking the flag and starting the PLL. */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + } + #endif + + FSP_HARDWARE_REGISTER_WAIT(r_cgc_clock_check(p_clock_cfg->pll_cfg.source_clock), FSP_SUCCESS); + } + #endif + } +#endif +#if BSP_PRV_PLL2_SUPPORTED + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll2_state) + { + /* Configure PLL and store PLL frequency in BSP. */ + r_cgc_pll_cfg(&p_clock_cfg->pll2_cfg, CGC_CLOCK_PLL2, pll2_hz, pll2ccr); + + if (CGC_CLOCK_CHANGE_START == options[p_clock_cfg->pll2_cfg.source_clock]) + { + /* Need to start PLL source clock and let it stabilize before starting PLL. */ + r_cgc_clock_change(p_clock_cfg->pll2_cfg.source_clock, CGC_CLOCK_CHANGE_START); + + #if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_HOCO == p_clock_cfg->pll2_cfg.source_clock) + { + /* If FLL is enabled and HOCO is turned on an additional stabilization wait is required before + * checking the flag and starting PLL2. */ + R_BSP_SoftwareDelay(BSP_PRV_FLL_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + } + #endif + + FSP_HARDWARE_REGISTER_WAIT(r_cgc_clock_check(p_clock_cfg->pll2_cfg.source_clock), FSP_SUCCESS); + } + } +#endif + + /* Start or stop clocks based on the input configuration. Start with PLL clock, so it can be stopped before trying + * to stop the PLL source clock. */ + for (int32_t i = (CGC_PRV_NUM_CLOCKS - 1); i >= 0; i--) + { + cgc_clock_change_t clock_state = options[i]; + cgc_clock_t clock_to_change = (cgc_clock_t) i; + if (CGC_CLOCK_CHANGE_STOP == clock_state) + { + /* Current system clock and current PLL source will be stopped after changing the system clock. */ + if ((current_system_clock != clock_to_change) +#if BSP_PRV_PLL_SUPPORTED + && (current_pll_source != clock_to_change) +#endif + ) + { + r_cgc_clock_change(clock_to_change, CGC_CLOCK_CHANGE_STOP); + } + } + + if (CGC_CLOCK_CHANGE_START == clock_state) + { + r_cgc_clock_change(clock_to_change, CGC_CLOCK_CHANGE_START); + } + } + +#if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_CHANGE_STOP == p_clock_cfg->hoco_state) + { + /* If HOCO is disabled then disable FLL as well. */ + R_SYSTEM->FLLCR1 = 0U; + } +#endif + + /* Verify the requested clock is stable if it has a stabilization flag. */ + FSP_HARDWARE_REGISTER_WAIT(r_cgc_clock_check(requested_system_clock), FSP_SUCCESS); + + /* If the requested clock is not the subclock and it was just started and it has no stabilization flag, wait + * for the required stabilization time in software. */ + if (g_cgc_software_wait_us[requested_system_clock] > 0U) + { + if (options[requested_system_clock] == CGC_CLOCK_CHANGE_START) + { + R_BSP_SoftwareDelay(g_cgc_software_wait_us[requested_system_clock], BSP_DELAY_UNITS_MICROSECONDS); + } + } + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + bsp_prv_clock_set(requested_system_clock, divider_cfg.sckdivcr_w, divider_cfg.sckdivcr2); +#else + #if BSP_FEATURE_CGC_HAS_MOSC && !BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + if ((requested_system_clock == CGC_CLOCK_MAIN_OSC) && (options[requested_system_clock] == CGC_CLOCK_CHANGE_START)) + { + uint8_t mainosc_stable_value = (uint8_t) ~(BSP_PRV_OSTC_OFFSET >> BSP_CLOCK_CFG_MAIN_OSC_WAIT); + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSTC, mainosc_stable_value); + } + #endif + + /* Set which clock to use for system clock and dividers. */ + uint8_t hoco_divider = (uint8_t) divider_cfg.hoco_divider; + uint8_t moco_divider = CGC_SYS_CLOCK_DIV_1; + uint8_t mosc_divider = CGC_SYS_CLOCK_DIV_1; + #if BSP_FEATURE_CGC_HAS_MOCO + moco_divider = (uint8_t) divider_cfg.moco_divider; + #endif + #if BSP_FEATURE_CGC_HAS_MOSC + mosc_divider = (uint8_t) divider_cfg.mosc_divider; + #endif + bsp_prv_clock_set(requested_system_clock, hoco_divider, moco_divider, mosc_divider); +#endif + + /* If the system clock has changed, stop previous system clock if requested. */ + if (requested_system_clock != current_system_clock) + { + if (CGC_CLOCK_CHANGE_STOP == options[current_system_clock]) + { + r_cgc_clock_change(current_system_clock, CGC_CLOCK_CHANGE_STOP); + +#if BSP_PRV_PLL_SUPPORTED + + /* This could stop the PLL source a second time, but it is more efficient than storing a variable to + * remember if it needs to be stopped. */ + if (CGC_CLOCK_CHANGE_STOP == options[current_pll_source]) + { + r_cgc_clock_change(current_pll_source, CGC_CLOCK_CHANGE_STOP); + } +#endif + } + } + + /* Reduce the operating speed mode to the optimal setting for these clock configurations and restore the cache to + * its previous state. */ + r_cgc_post_change(CGC_PRV_CHANGE_LPM_CGC); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Start the specified clock if it is not currently active. The PLL configuration cannot be changed while the PLL + * is running. Implements @ref cgc_api_t::clockStart. + * + * The PLL source clock must be operating and stable prior to starting the PLL. + * + * Example: + * @snippet r_cgc_example.c R_CGC_ClockStart + * + * @retval FSP_SUCCESS Clock initialized successfully. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_NOT_STABILIZED The clock source is not stabilized after being turned off or PLL clock source + * is not stable. + * @retval FSP_ERR_PLL_SRC_INACTIVE PLL clock source is not running. + * @retval FSP_ERR_CLOCK_ACTIVE PLL configuration cannot be changed while PLL is running. + * @retval FSP_ERR_OSC_STOP_DET_ENABLED PLL multiplier must be less than 20 if oscillation stop detect is enabled and + * the input frequency is less than 12.5 MHz. + * @retval FSP_ERR_INVALID_STATE The subclock must be running before activating HOCO with FLL. + **********************************************************************************************************************/ +fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, cgc_pll_cfg_t const * const p_pll_cfg) +{ + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = FSP_SUCCESS; + FSP_PARAMETER_NOT_USED(err); // unused in some build configurations +#if !BSP_PRV_PLL_SUPPORTED && !BSP_PRV_PLL2_SUPPORTED + FSP_PARAMETER_NOT_USED(p_pll_cfg); +#endif +#if CGC_CFG_PARAM_CHECKING_ENABLE + err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check the target clock source */ + err = r_cgc_clock_source_has_support(clock_source); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if BSP_PRV_PLL_SUPPORTED + if ((CGC_CLOCK_PLL == clock_source) + #if BSP_PRV_PLL2_SUPPORTED + || (CGC_CLOCK_PLL2 == clock_source) + #endif + ) + { + /* p_pll_cfg is required to start PLL. */ + FSP_ASSERT(NULL != p_pll_cfg); + + err = r_cgc_pll_parameter_check(p_pll_cfg, true); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + #if BSP_PRV_HOCO_USE_FLL + FSP_ERROR_RETURN(!((CGC_CLOCK_HOCO == clock_source) && R_SYSTEM->SOSCCR), FSP_ERR_INVALID_STATE); + #endif + + #if BSP_FEATURE_CGC_REGISTER_SET_B + + /* If the current operating mode is Subosc-speed mode, the HOCO, MOCO and main oscillator can not be started */ + if (1U == R_SYSTEM->ICLKSCR_b.CKST) + { + FSP_ERROR_RETURN((CGC_CLOCK_HOCO == clock_source) || (CGC_CLOCK_MOCO == clock_source) || + (CGC_CLOCK_MAIN_OSC == clock_source), + FSP_ERR_ASSERTION); + } + #endif +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + +#if BSP_PRV_PLL_SUPPORTED + uint32_t pll_hz[CGC_PRV_MAX_PLL_OUTPUTS]; + uint32_t pllccr = 0; + if ((CGC_CLOCK_PLL == clock_source) + #if BSP_PRV_PLL2_SUPPORTED + || (CGC_CLOCK_PLL2 == clock_source) + #endif + ) + { + err = + r_cgc_pllccr_pll_hz_calculate(p_pll_cfg, clock_source, pll_hz, &pllccr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + /* Make sure the oscillator is stable. */ + FSP_ERROR_RETURN(r_cgc_stabilization_check(clock_source, r_cgc_clock_run_state_get(clock_source)), + FSP_ERR_NOT_STABILIZED); +#endif + + /* Prerequisite to starting clocks or changing the system clock. */ + r_cgc_pre_change(CGC_PRV_CHANGE_LPM_CGC); + +#if BSP_PRV_PLL_SUPPORTED + if (CGC_CLOCK_PLL == clock_source + #if BSP_PRV_PLL2_SUPPORTED + || CGC_CLOCK_PLL2 == clock_source + #endif + ) + { + r_cgc_pll_cfg(p_pll_cfg, clock_source, pll_hz, pllccr); + } +#endif + +#if BSP_PRV_HOCO_USE_FLL + if (CGC_CLOCK_HOCO == clock_source) + { + /* If FLL is to be used set FLLCR1 before starting HOCO. */ + R_SYSTEM->FLLCR1 = 1U; + } +#endif + + /* Start the clock. */ + r_cgc_clock_change(clock_source, CGC_CLOCK_CHANGE_START); + + /* Reduce the operating speed mode to the optimal setting for these clock configurations and restore the cache to + * it's previous state. */ + r_cgc_post_change(CGC_PRV_CHANGE_LPM_CGC); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stop the specified clock if it is active. Implements @ref cgc_api_t::clockStop. + * + * Do not attempt to stop the current system clock source. Do not attempt to stop the source clock of a PLL if the + * PLL is running. + * + * @retval FSP_SUCCESS Clock stopped successfully. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_IN_USE Attempt to stop the current system clock or the PLL source clock. + * @retval FSP_ERR_OSC_STOP_DET_ENABLED Attempt to stop MOCO when Oscillation stop is enabled. + * @retval FSP_ERR_NOT_STABILIZED Clock not stabilized after starting. + **********************************************************************************************************************/ +fsp_err_t R_CGC_ClockStop (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source) +{ + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_instance_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check the target clock source */ + err = r_cgc_clock_source_has_support(clock_source); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* HOCO must be running in low voltage mode. */ + FSP_ASSERT(CGC_CLOCK_HOCO != clock_source); + #endif + + /* If clock source is the current system clock, return error */ + cgc_clock_t current_clock; + #if !BSP_FEATURE_CGC_REGISTER_SET_B + current_clock = (cgc_clock_t) R_SYSTEM->SCKSCR; + #else + current_clock = (cgc_clock_t) bsp_prv_clock_source_get(); + #endif + FSP_ERROR_RETURN(clock_source != current_clock, FSP_ERR_IN_USE); + + #if BSP_PRV_PLL_SUPPORTED + + /* If PLL is operating, the PLL clock source cannot be stopped. */ + FSP_ERROR_RETURN(!((r_cgc_clock_run_state_get(CGC_CLOCK_PLL) && (r_cgc_pll_clocksource_get() == clock_source))) + #if BSP_PRV_PLL2_SUPPORTED + && !((r_cgc_clock_run_state_get(CGC_CLOCK_PLL2) && (r_cgc_pll2_clocksource_get() == clock_source))) + #endif + , + FSP_ERR_IN_USE); + #endif + + #if !BSP_FEATURE_CGC_REGISTER_SET_B + + /* MOCO cannot be stopped if oscillation stop detection is enabled. */ + FSP_ERROR_RETURN(!((clock_source == CGC_CLOCK_MOCO) && (R_SYSTEM->OSTDCR_b.OSTDE == 1U)), + FSP_ERR_OSC_STOP_DET_ENABLED); + + /* Make sure the oscillator is stable. */ + FSP_ERROR_RETURN(r_cgc_stabilization_check(clock_source, r_cgc_clock_run_state_get(clock_source)), + FSP_ERR_NOT_STABILIZED); + #endif +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Stop the clock. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + r_cgc_clock_change(clock_source, CGC_CLOCK_CHANGE_STOP); + +#if BSP_PRV_HOCO_USE_FLL + + /* FLL must be disabled after stopping HOCO. */ + if (CGC_CLOCK_HOCO == clock_source) + { + R_SYSTEM->FLLCR1 = 0U; + } +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* Reduce the operating speed mode if possible based on the new clock configuration. */ + r_cgc_pre_change(CGC_PRV_CHANGE_LPM); + #if !BSP_FEATURE_CGC_REGISTER_SET_B + r_cgc_operating_mode_reduce(R_SYSTEM->SCKDIVCR); + #else + r_cgc_operating_mode_reduce(0U); + #endif + r_cgc_post_change(CGC_PRV_CHANGE_LPM); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the specified clock as the system clock and configure the internal dividers for ICLK, PCLKA, PCLKB, PCLKC, + * PCLKD, BCLK, and FCLK. Implements @ref cgc_api_t::systemClockSet. + * + * The requested clock source must be running and stable prior to calling this function. The internal dividers are + * subject to constraints described in the hardware manual table "Specifications of the Clock Generation Circuit for + * the internal clocks". + * + * The internal dividers (p_divider_cfg) are subject to constraints described in footnotes of the hardware manual table + * detailing specifications for the clock generation circuit for the internal clocks for the MCU. + * For example: + * - RA6M3: see footnotes "Specifications of the clock generation circuit for the internal clocks" + * in the CGC section of the relevant hardware manual. + * - RA2A1: see footnotes "Clock generation circuit specifications for the internal clocks" + * in the CGC section of the relevant hardware manual. + * + * This function also updates the RAM and ROM wait states, the operating power control mode, and the SystemCoreClock + * CMSIS global variable. + * + * Example: + * @snippet r_cgc_example.c R_CGC_SystemClockSet + * + * @retval FSP_SUCCESS Operation performed successfully. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CLOCK_INACTIVE The specified clock source is inactive. + * @retval FSP_ERR_NOT_STABILIZED The clock source has not stabilized + **********************************************************************************************************************/ +fsp_err_t R_CGC_SystemClockSet (cgc_ctrl_t * const p_ctrl, + cgc_clock_t clock_source, + cgc_divider_cfg_t const * const p_divider_cfg) +{ + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_instance_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_divider_cfg); + + #if 0 == BSP_FEATURE_CGC_EXECUTE_FROM_LOCO + FSP_ASSERT(CGC_CLOCK_LOCO != clock_source); + #endif +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + cgc_divider_cfg_t divider_cfg; +#if !BSP_FEATURE_CGC_REGISTER_SET_B + divider_cfg.sckdivcr_w = p_divider_cfg->sckdivcr_w; + #if BSP_FEATURE_CGC_HAS_CPUCLK + divider_cfg.sckdivcr2 = p_divider_cfg->sckdivcr2; + #else + divider_cfg.sckdivcr2 = 0; + #endif +#else + divider_cfg.hoco_divider = p_divider_cfg->hoco_divider; + #if BSP_FEATURE_CGC_HAS_MOCO + divider_cfg.moco_divider = p_divider_cfg->moco_divider; + #endif + #if BSP_FEATURE_CGC_HAS_MOSC + divider_cfg.mosc_divider = p_divider_cfg->mosc_divider; + #endif +#endif + +#if BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + + /* Some MCUs require the bits normally used for BCLK to be set the same as PCLKB. */ + divider_cfg.sckdivcr_b.bclk_div = divider_cfg.sckdivcr_b.pclkb_div; +#endif + +#if BSP_FEATURE_CGC_SCKDIVCR2_CPUCLK1_MATCHES_MRICLK + + /* Some MCUs require the bits normally used for CPUCLK1 to be set the same as MRICLK. */ + divider_cfg.sckdivcr2_b.cpuclk1_div = divider_cfg.sckdivcr2_b.mriclk_div; +#endif + +#if BSP_FEATURE_CGC_SCKDIVCR2_NPUCLK_MATCHES_MRICLK + + /* Some MCUs require the bits normally used for NPUCLK to be set the same as MRICLK. */ + divider_cfg.sckdivcr2_b.npuclk_div = divider_cfg.sckdivcr2_b.mriclk_div; +#endif + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Check the system clock source */ + err = r_cgc_clock_source_has_support(clock_source); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check divider constraints. */ + err = r_cgc_check_config_dividers(÷r_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if BSP_FEATURE_CGC_HAS_CPUCLK + if (CGC_CLOCK_PLL == clock_source) + { + /* CPUCLK frequency must be less than threshold when XTAL is not the source for PLL. */ + uint8_t cpuclk_div = divider_cfg.sckdivcr2_b.cpuclk_div; + uint32_t new_cpuclk_freq_hz = R_BSP_SourceClockHzGet(FSP_PRIV_CLOCK_PLL1P) / + ((cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div)); + FSP_ASSERT((0 == R_SYSTEM->PLLCCR_b.PLSRCSEL) || + (BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ >= new_cpuclk_freq_hz)); + } + #endif + + /* Confirm the requested clock is stable. */ + err = r_cgc_clock_check(clock_source); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Prerequisite to starting clocks or changing the system clock. */ + r_cgc_pre_change(CGC_PRV_CHANGE_LPM_CGC); + +#if BSP_FEATURE_CGC_REGISTER_SET_B + uint8_t hoco_divider = (uint8_t) divider_cfg.hoco_divider; + uint8_t moco_divider = CGC_SYS_CLOCK_DIV_1; + uint8_t mosc_divider = CGC_SYS_CLOCK_DIV_1; + #if BSP_FEATURE_CGC_HAS_MOCO + moco_divider = (uint8_t) divider_cfg.moco_divider; + #endif + #if BSP_FEATURE_CGC_HAS_MOSC + mosc_divider = (uint8_t) divider_cfg.mosc_divider; + #endif + bsp_prv_clock_set(clock_source, hoco_divider, moco_divider, mosc_divider); +#else + bsp_prv_clock_set(clock_source, divider_cfg.sckdivcr_w, divider_cfg.sckdivcr2); +#endif + + /* Apply the optimal operating power mode and restore the cache to it's previous state. */ + r_cgc_post_change(CGC_PRV_CHANGE_LPM_CGC); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Return the current system clock source and configuration. Implements @ref cgc_api_t::systemClockGet. + * + * @retval FSP_SUCCESS Parameters returned successfully. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t R_CGC_SystemClockGet (cgc_ctrl_t * const p_ctrl, + cgc_clock_t * const p_clock_source, + cgc_divider_cfg_t * const p_divider_cfg) +{ + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_instance_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Get the system clock source */ + if (NULL != p_clock_source) + { +#if BSP_FEATURE_CGC_REGISTER_SET_B + *p_clock_source = (cgc_clock_t) bsp_prv_clock_source_get(); +#else + *p_clock_source = (cgc_clock_t) R_SYSTEM->SCKSCR; +#endif + } + + /* Get current dividers. */ + if (NULL != p_divider_cfg) + { +#if BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_FEATURE_CGC_HAS_MOCO + p_divider_cfg->moco_divider = (cgc_sys_clock_div_t) R_SYSTEM->MOCODIV; + #endif + #if BSP_FEATURE_CGC_HAS_MOSC + p_divider_cfg->mosc_divider = (cgc_sys_clock_div_t) R_SYSTEM->MOSCDIV; + #endif + p_divider_cfg->hoco_divider = (cgc_sys_clock_div_t) R_SYSTEM->HOCODIV; +#else + p_divider_cfg->sckdivcr_w = R_SYSTEM->SCKDIVCR; + #if BSP_FEATURE_CGC_HAS_CPUCLK + p_divider_cfg->sckdivcr2 = R_SYSTEM->SCKDIVCR2; + #endif +#endif + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Check the specified clock for stability. Implements @ref cgc_api_t::clockCheck. + * + * @retval FSP_SUCCESS Clock is running and stable. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_NOT_STABILIZED Clock not stabilized. + * @retval FSP_ERR_CLOCK_INACTIVE Clock not turned on. + **********************************************************************************************************************/ +fsp_err_t R_CGC_ClockCheck (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source) +{ + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + fsp_err_t err; + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_instance_ctrl is not NULL and the module is open. */ + err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Ensure the clock is running and stable. */ + err = r_cgc_clock_check(clock_source); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable the oscillation stop detection for the main clock. Implements @ref cgc_api_t::oscStopDetectEnable. + * + * The MCU will automatically switch the system clock to MOCO when a stop is detected if Main Clock is + * the system clock. If the system clock is the PLL, then the clock source will not be changed and the + * PLL free running frequency will be the system clock frequency. + * + * Example: + * @snippet r_cgc_example.c R_CGC_OscStopDetectEnable + * + * @retval FSP_SUCCESS Operation performed successfully. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_LOW_VOLTAGE_MODE Settings not allowed in low voltage mode. + * @retval FSP_ERR_UNSUPPORTED Function not supported. + **********************************************************************************************************************/ +fsp_err_t R_CGC_OscStopDetectEnable (cgc_ctrl_t * const p_ctrl) +{ +#if BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_instance_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if defined(BSP_TZ_NONSECURE_BUILD) && BSP_TZ_NONSECURE_BUILD + + /* The NMI must be configured to TrustZone Non-secure in order to be used in a Non-secure project. */ + FSP_ASSERT(0U != (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk)); + #elif defined(BSP_TZ_SECURE_BUILD) && BSP_TZ_SECURE_BUILD + + /* The NMI must be configured to TrustZone Secure in order to be used in a Secure project. */ + FSP_ASSERT(0U == (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk)); + #endif + #else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #endif + + #if BSP_FEATURE_CGC_HAS_OSTDCSE + cgc_extended_cfg_t * p_extend = (cgc_extended_cfg_t *) p_instance_ctrl->p_extend; + if (p_extend->ostd_enable) + #endif + { + /* Low speed and low voltage mode have divider restrictions when using oscillation stop detection. */ + #if BSP_CFG_USE_LOW_VOLTAGE_MODE + FSP_ERROR_RETURN(r_cgc_low_speed_or_voltage_mode_possible(R_SYSTEM->SCKDIVCR, CGC_PRV_OSTDCR_OSC_STOP_ENABLE), + FSP_ERR_LOW_VOLTAGE_MODE); + #else + + /* When low voltage mode is not used, switch to the next available power mode if currently in low speed mode and + * this mode is not supported when oscillation stop is enabled to ensure the operating power control mode remains + * in spec. */ + uint32_t operating_mode = R_SYSTEM->OPCCR_b.OPCM; + uint32_t sckdivcr = R_SYSTEM->SCKDIVCR; + if (operating_mode == BSP_PRV_OPERATING_MODE_LOW_SPEED) + { + if (!(r_cgc_low_speed_or_voltage_mode_possible(sckdivcr, CGC_PRV_OSTDCR_OSC_STOP_ENABLE))) + { + r_cgc_pre_change(CGC_PRV_CHANGE_LPM); + bsp_prv_operating_mode_set(CGC_PRV_EXIT_LOW_SPEED_MODE); + r_cgc_post_change(CGC_PRV_CHANGE_LPM); + } + } + #endif + + /* Add callback function to BSP */ + (void) R_BSP_GroupIrqWrite(BSP_GRP_IRQ_OSC_STOP_DETECT, r_cgc_nmi_internal_callback); + + /* Enable the oscillation stop NMI. */ + + /* Set OSTEN bit to enable NMI on oscillation stop detection. NMIER bits cannot be cleared after reset, so no need + * to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_OSTEN_Msk; + + /* Enable oscillation stop detection */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->OSTDCR = CGC_PRV_OSTDCR_OSC_STOP_ENABLE; + } + + #if BSP_FEATURE_CGC_HAS_OSTDCSE + if (p_extend->mostd_enable) + { + /* Power on peripheral. */ + R_BSP_MODULE_START(FSP_IP_MOSTD, 0); + + /* Configure Oscillation Stop Detection Time */ + + /* Oscillation stop detection time = + * High speed on-chip oscillator clock (HOCO) cycle × ((value of OSDCCMP) + 1) + */ + uint16_t mostd_detection_en = p_extend->mostd_detection_time - 1; + + /* Start operation of the oscillation stop detector */ + mostd_detection_en |= R_SYSTEM_MOSTD_OSDCE_Msk; + R_SYSTEM->MOSTD = mostd_detection_en; + } + + if (p_extend->sostd_enable) + { + /* Power on peripheral. */ + R_BSP_MODULE_START(FSP_IP_SOSTD, 0); + + /* Configure Oscillation Stop Detection Time */ + + /* Oscillation stop detection time = + * Low-speed on-chip oscillator clock (LOCO) cycle × ((value of OSDCCMP) + 1) + */ + uint16_t sostd_detection_en = p_extend->sostd_detection_time - 1; + + /* Start operation of the oscillation stop detector */ + sostd_detection_en |= R_SYSTEM_SOSTD_OSDCE_Msk; + R_SYSTEM->SOSTD = sostd_detection_en; + } + + /* Enable clock switch when oscillation stop detection occurs */ + R_SYSTEM->SDADCCKCR_b.OSTDCSE = p_extend->sdadc_b_clock_switch_enable & 0x1U; + #endif + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + return FSP_SUCCESS; +#else /* Device does not support Oscillation Stop Detection Function */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Disable the oscillation stop detection for the main clock. Implements @ref cgc_api_t::oscStopDetectDisable. + * + * Example: + * @snippet r_cgc_example.c R_CGC_OscStopDetectDisable + * + * @retval FSP_SUCCESS Operation performed successfully. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_OSC_STOP_DETECTED The Oscillation stop detect status flag is set. Under this condition it is not + * possible to disable the Oscillation stop detection function. + * @retval FSP_ERR_UNSUPPORTED Function not supported. + **********************************************************************************************************************/ +fsp_err_t R_CGC_OscStopDetectDisable (cgc_ctrl_t * const p_ctrl) +{ +#if BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_instance_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If the oscillation stop flag is set, oscillation stop cannot be disabled. */ + FSP_ERROR_RETURN((R_SYSTEM->OSTDSR != 1U), FSP_ERR_OSC_STOP_DETECTED); + #else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #endif + + /* Disable oscillation stop detection. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->OSTDCR = 0U; // disable osc stop detection + #if BSP_FEATURE_CGC_HAS_OSTDCSE + + /* Stop operation of the oscillation stop detector */ + R_SYSTEM->SOSTD_b.OSDCE = 0U; + R_SYSTEM->MOSTD_b.OSDCE = 0U; + + /* Power down peripheral. */ + R_BSP_MODULE_STOP(FSP_IP_SOSTD, 0); + R_BSP_MODULE_STOP(FSP_IP_MOSTD, 0); + #endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + #if !BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* Attempt to reduce the operating power control mode. */ + r_cgc_pre_change(CGC_PRV_CHANGE_LPM); + r_cgc_operating_mode_reduce(R_SYSTEM->SCKDIVCR); + r_cgc_post_change(CGC_PRV_CHANGE_LPM); + #endif + + return FSP_SUCCESS; +#else /* Device does not support Oscillation Stop Detection Function */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Clear the Oscillation Stop Detection Status register. This register is not cleared automatically if the stopped + * clock is restarted. Implements @ref cgc_api_t::oscStopStatusClear. + * + * After clearing the status, oscillation stop detection is no longer enabled. + * + * This register cannot be cleared while the main oscillator is the system clock or the PLL source clock. + * + * Example: + * @snippet r_cgc_example.c R_CGC_OscStopStatusClear + * + * @retval FSP_SUCCESS Operation performed successfully. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CLOCK_INACTIVE Main oscillator must be running to clear the oscillation stop detection + * flag. + * @retval FSP_ERR_OSC_STOP_CLOCK_ACTIVE The Oscillation Detect Status flag cannot be cleared if the + * Main Osc or PLL is set as the system clock. Change the + * system clock before attempting to clear this bit. + * @retval FSP_ERR_INVALID_HW_CONDITION Oscillation stop status was not cleared. Check preconditions and try again. + * @retval FSP_ERR_UNSUPPORTED Function not supported. + **********************************************************************************************************************/ +fsp_err_t R_CGC_OscStopStatusClear (cgc_ctrl_t * const p_ctrl) +{ +#if BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_instance_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #endif + + if (R_SYSTEM->OSTDSR == 1U) + { + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify the main oscillator is running. */ + FSP_ERROR_RETURN(CGC_PRV_CLOCK_STATE_RUNNING == r_cgc_clock_run_state_get(CGC_CLOCK_MAIN_OSC), + FSP_ERR_CLOCK_INACTIVE); + + /* Get the system clock source */ + cgc_clock_t current_clock = (cgc_clock_t) R_SYSTEM->SCKSCR; + + #if BSP_PRV_PLL_SUPPORTED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + /* Oscillation stop status cannot be cleared if PLL is the current source clock and main oscillator is the + * source of the PLL. */ + FSP_ERROR_RETURN(!((CGC_CLOCK_PLL == current_clock) && (0U == R_SYSTEM->PLLCCR_b.PLSRCSEL)), + FSP_ERR_OSC_STOP_CLOCK_ACTIVE); + #else + + /* Oscillation stop status cannot be cleared if PLL is the current source clock. */ + FSP_ERROR_RETURN(!(CGC_CLOCK_PLL == current_clock), FSP_ERR_OSC_STOP_CLOCK_ACTIVE); + #endif + #endif + + /* Oscillation stop status cannot be cleared if the main oscillator is the current source clock. */ + FSP_ERROR_RETURN(!(CGC_CLOCK_MAIN_OSC == current_clock), FSP_ERR_OSC_STOP_CLOCK_ACTIVE); + #endif + + /* Clear the oscillation stop status flag. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->OSTDCR = 0U; + R_SYSTEM->OSTDSR = 0U; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /* At least 3 ICLK cycles of wait time are required between writing 0 to OSTDF and reading it as 0 (see + * "Oscillation Stop Detection Status Register (OSTDSR)" description in the CGC section of the relevant hardware manual.) The call to enable register + * protection for CGC registers above takes more than 3 ICLK cycles. */ + + /* Verify the flag was cleared (see figure "Flow of recovery on detection of oscillator stop" + * in the CGC section of the relevant hardware manual). If not, return an error. */ + FSP_ERROR_RETURN(0U == R_SYSTEM->OSTDSR, FSP_ERR_INVALID_HW_CONDITION); + } + + return FSP_SUCCESS; +#else /* Device does not support Oscillation Stop Detection Function */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements cgc_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + * @retval FSP_ERR_UNSUPPORTED Function not supported. + **********************************************************************************************************************/ +fsp_err_t R_CGC_CallbackSet (cgc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(cgc_callback_args_t *), + void * const p_context, + cgc_callback_args_t * const p_callback_memory) +{ +#if !BSP_FEATURE_CGC_REGISTER_SET_B + cgc_instance_ctrl_t * p_ctrl = (cgc_instance_ctrl_t *) p_api_ctrl; + + #if BSP_TZ_SECURE_BUILD + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + #endif + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify that the callback is not NULL. */ + FSP_ASSERT(NULL != p_callback); + + #if BSP_TZ_SECURE_BUILD + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + cgc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif + #endif + + #if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(cgc_callback_args_t *))cmse_nsfptr_create(p_callback); + #else + p_ctrl->p_callback = p_callback; + #endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_context); + FSP_PARAMETER_NOT_USED(p_callback_memory); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/******************************************************************************************************************//** + * Closes the CGC module. Implements @ref cgc_api_t::close. + * + * @retval FSP_SUCCESS The module is successfully closed. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t R_CGC_Close (cgc_ctrl_t * const p_ctrl) +{ + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) p_ctrl; + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_instance_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + p_instance_ctrl->open = 0U; + +#if BSP_FEATURE_CGC_HAS_OSTDCSE + cgc_extended_cfg_t * p_extend = (cgc_extended_cfg_t *) p_instance_ctrl->p_extend; + + /* Disable interrupts. */ + r_cgc_disable_irq(p_extend->mostd_irq); + r_cgc_disable_irq(p_extend->sostd_irq); +#endif + + /* All done, return success. */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup CGC) + **********************************************************************************************************************/ + +#if CGC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Verifies the control structure is not NULL and the module is open. This reduces code size when the error logger is + * used. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * + * @retval FSP_SUCCESS No error detected. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +static fsp_err_t r_cgc_common_parameter_checking (cgc_instance_ctrl_t * p_instance_ctrl) +{ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(CGC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Sets operating mode to high speed mode, unlocks CGC and LPM protection registers, disables the flash cache, and + * returns the previous state of the flash cache. Must be paired with r_cgc_post_change(). + * + * @param[in] change Whether or not to enter high speed mode and unprotect CGC registers. + * + * @return Cache state to restore + **********************************************************************************************************************/ +static void r_cgc_pre_change (cgc_prv_change_t change) +{ +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if BSP_FEATURE_FLASH_CACHE_DISABLE_OPM + + /* Disable flash cache. */ + R_BSP_FlashCacheDisable(); + #endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); +#endif + if (CGC_PRV_CHANGE_LPM_CGC == change) + { +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* Switch to high-speed to prevent any issues with the subsequent system clock change. */ + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_HIGH_SPEED); +#endif + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + } +} + +/*******************************************************************************************************************//** + * Reduces operating speed mode to the optimal value based on current configurations, locks CGC and LPM protection + * registers, and restores the cache state. Must be paired with r_cgc_pre_change(). + * + * @param[in] change Whether or not to protect CGC registers. + **********************************************************************************************************************/ +static void r_cgc_post_change (cgc_prv_change_t change) +{ + /* Set the operating speed mode based on the new system clock source */ + if (CGC_PRV_CHANGE_LPM_CGC == change) + { + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if !BSP_FEATURE_CGC_REGISTER_SET_B + r_cgc_operating_mode_reduce(R_SYSTEM->SCKDIVCR); + #else + r_cgc_operating_mode_reduce(0U); + #endif +#endif + } + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + #if BSP_FEATURE_FLASH_CACHE_DISABLE_OPM && BSP_FEATURE_FLASH_CACHE + R_BSP_FlashCacheEnable(); + #endif +#endif +} + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_CGC_HAS_SOPCCR + +/*******************************************************************************************************************//** + * Verifies if Subosc speed mode is possible + * + * @param[in] sckdivcr Requested SCKDIVCR register setting + * + * @return true if subosc speed mode is can be used based on current clock configurations + **********************************************************************************************************************/ +static bool r_cgc_subosc_mode_possible (uint32_t sckdivcr) +{ + /* Subosc speed mode is only supported on the LOCO or the subclock. */ + if (CGC_PRV_SUBCLOCK_LOCO_HZ != SystemCoreClock) + { + return false; + } + + /* If the stop bit is cleared for HOCO, MOCO, MOSC, or PLL, subosc speed mode is not possible. All of these clocks + * must be stopped to enter subosc speed mode. */ + if ((((!R_SYSTEM->HOCOCR) || (!R_SYSTEM->MOCOCR)) || (!R_SYSTEM->MOSCCR)) + #if BSP_PRV_PLL_SUPPORTED + || (!R_SYSTEM->PLLCR) + #endif + #if BSP_PRV_PLL2_SUPPORTED + || (!R_SYSTEM->PLL2CR) + #endif + ) + { + return false; + } + + /* If the ICLK or FCLK divider is not 1, sub-oscillator mode is not possible. */ + if (0U != (sckdivcr & CGC_PRV_SCKDIVCR_ICLK_FCLK_MASK)) + { + return false; + } + + return true; +} + +#endif + +#if !BSP_FEATURE_CGC_REGISTER_SET_B + +/*******************************************************************************************************************//** + * Verifies divisor, oscillation stop, and PLL settings to determine if low-speed or low-voltage mode is possible. + * Maximum frequency must be verified outside this function. Checks if low voltage mode is possible if + * BSP_CFG_USE_LOW_VOLTAGE_MODE is set, otherwise checks if low speed mode is possible. + * + * @param[in] sckdivcr Requested SCKDIVCR register setting + * @param[in] ostdcr Requested OSTDCR register setting + * + * @return true if the requested mode can be used based on the specified clock configurations + **********************************************************************************************************************/ +static bool r_cgc_low_speed_or_voltage_mode_possible (uint32_t sckdivcr, uint8_t ostdcr) +{ + #if BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* HOCO must be operating in low voltage mode. */ + if (0U != R_SYSTEM->HOCOCR) + { + return false; + } + #endif + + #if !BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC + + /* MOSC must be stopped in low speed mode. */ + if (1U != R_SYSTEM->MOSCCR) + { + return false; + } + #endif + + /* When oscillation stop detection is enabled, clock division of 1, 2, 4, or 8 is prohibited for all clocks in + * low speed mode. The remaining dividers (16, 32, and 64) all have the upper bit of the bitfield set. */ + if (0U != ostdcr) + { + uint32_t test = sckdivcr; + #if BSP_CFG_USE_LOW_VOLTAGE_MODE + + /* When oscillation stop detection is enabled, clock division of 1 or 2 is prohibited for all clocks in + * low voltage mode. The remaining dividers (4, 8, 16, 32, and 64) all have either bit 2 or bit 1 of + * the bitfield set. */ + test = sckdivcr | (sckdivcr << 1); + #endif + if ((CGC_PRV_SCKDIVCR_UPPER_BIT & test) != CGC_PRV_SCKDIVCR_UPPER_BIT) + { + return false; + } + } + + #if BSP_PRV_PLL_SUPPORTED + + /* Low speed mode is only possible if the PLL is stopped. */ + return (bool) R_SYSTEM->PLLCR + #if BSP_PRV_PLL2_SUPPORTED + || R_SYSTEM->PLL2CR + #endif + ; + #else /* BSP_PRV_PLL_SUPPORTED */ + return true; + #endif +} + +#endif + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE + +/*******************************************************************************************************************//** + * Sets the optimum operating speed mode based on the current system clock. + * + * @param[in] sckdivcr Requested SCKDIVCR register setting + **********************************************************************************************************************/ +static void r_cgc_operating_mode_reduce (uint32_t sckdivcr) +{ + #if !BSP_FEATURE_CGC_REGISTER_SET_B + uint8_t ostdcr = R_SYSTEM->OSTDCR; + + #if BSP_FEATURE_CGC_HAS_SOPCCR + + /* Switch to subosc-speed mode if possible. */ + if (r_cgc_subosc_mode_possible(sckdivcr)) + { + /* Switch to sub oscillator mode */ + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_SUBOSC_SPEED); + } + else + #endif + + /* Switch to low-speed mode if possible. */ + if (r_cgc_low_speed_or_voltage_mode_possible(sckdivcr, ostdcr) && + (SystemCoreClock <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ)) + #else + FSP_PARAMETER_NOT_USED(sckdivcr); + if ((SystemCoreClock <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ) + #if !BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC + && (0U != R_SYSTEM->MOSCCR) + #endif + ) + #endif + { + /* Switch to low speed mode */ + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_LOW_SPEED); + } + + #if BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ > 0U + + /* Switch to middle-speed mode if the ICLK frequency supports it. */ + else if (SystemCoreClock <= BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ) + { + bsp_prv_operating_mode_set(BSP_PRV_OPERATING_MODE_MIDDLE_SPEED); + } + #endif + else + { + /* Do nothing, remain in high speed mode. */ + } +} + +#endif + +/*******************************************************************************************************************//** + * Check if the specified clock is running and stable + * + * @param[in] clock_source Clock to be verified + * + * @retval FSP_SUCCESS Clock is running and stable. + * @retval FSP_ERR_NOT_STABILIZED Clock not stabilized. + * @retval FSP_ERR_CLOCK_INACTIVE Clock not turned on. + **********************************************************************************************************************/ +static fsp_err_t r_cgc_clock_check (cgc_clock_t const clock_source) +{ + cgc_prv_clock_state_t running = r_cgc_clock_run_state_get(clock_source); + + /* Ensure the clock is stable if the clock has a stabilization flag. */ + FSP_ERROR_RETURN(r_cgc_stabilization_check(clock_source, running), FSP_ERR_NOT_STABILIZED); + + /* Ensure the clock is running. */ + FSP_ERROR_RETURN(running, FSP_ERR_CLOCK_INACTIVE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function returns the run state of the selected clock + * + * @param[in] clock Clock to check + * + * @return 1 if running, 0 if stopped + **********************************************************************************************************************/ +static cgc_prv_clock_state_t r_cgc_clock_run_state_get (cgc_clock_t clock) +{ + + /* Get clock run state. */ + return (cgc_prv_clock_state_t) !(*gp_cgc_clock_stp_registers[clock]); +} + +/*******************************************************************************************************************//** + * This function checks the selected clock for stability. + * + * @param[in] clock Clock to check + * @param[in] status Current state of the clock + * + * @return true if stable or the clock has no stability flag, false if not stable + **********************************************************************************************************************/ +static bool r_cgc_stabilization_check (cgc_clock_t clock, cgc_prv_clock_state_t status) +{ +#if BSP_FEATURE_CGC_REGISTER_SET_B + if (CGC_PRV_CLOCK_STATE_STOPPED == status) + { + return true; + } + + #if BSP_FEATURE_CGC_HAS_MOSC + if (CGC_CLOCK_MAIN_OSC == clock) + { + return BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE ? true : (R_SYSTEM->OSTC == + (uint8_t) ~(BSP_PRV_OSTC_OFFSET >> + BSP_CLOCK_CFG_MAIN_OSC_WAIT)); + } + #endif +#endif + + /* MOCO, LOCO, and subclock have no stabilization flags, so return true if the clock is any of these. */ + uint32_t bitmask_moco_loco_subclock = + ((1U << CGC_CLOCK_MOCO) | (1U << CGC_CLOCK_LOCO) | (1U << CGC_CLOCK_SUBCLOCK)); + if (bitmask_moco_loco_subclock & (1U << clock)) + { + return true; + } + + /* Check for stability of selected clock. */ + uint32_t oscsf = R_SYSTEM->OSCSF; + uint32_t oscsf_bit = (oscsf >> clock) & 1U; + + return oscsf_bit == (uint32_t) status; +} + +/*******************************************************************************************************************//** + * This function starts or stops the selected clock. Do not call this subroutine with CGC_CLOCK_CHANGE_NONE. + * + * @param[in] clock Clock to start or stop + * @param[in] state 1 to stop clock, 0 to start clock + **********************************************************************************************************************/ +static void r_cgc_clock_change (cgc_clock_t clock, cgc_clock_change_t state) +{ + *gp_cgc_clock_stp_registers[clock] = (uint8_t) state; + + /* Wait setting to be reflected in hardware registers. */ + FSP_HARDWARE_REGISTER_WAIT(*gp_cgc_clock_stp_registers[clock], state); + +#if BSP_FEATURE_BSP_HAS_SYRACCR + if (CGC_CLOCK_LOCO == clock) + { + /* Wait for the BUSY flag to be cleared (See "SYRACCR : System Register Access Control Register" description in the CGC section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SYRACCR, 0); + } +#endif +} + +#if CGC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Check divider values against hardware manual constraints. + * + * @param[in] p_divider_cfg Pointer to clock divider configuration + * + * @retval FSP_SUCCESS Dividers satisfy hardware manual constraints. + * @retval FSP_ERR_ASSERTION One or more divider values do not satisfy constraints specified in the + * hardware manual. + **********************************************************************************************************************/ +static fsp_err_t r_cgc_check_config_dividers (cgc_divider_cfg_t const * const p_divider_cfg) +{ + FSP_PARAMETER_NOT_USED(p_divider_cfg); // unused if FSP_ASSERT is compiled out + + #if BSP_FEATURE_CGC_HAS_CPUCLK + fsp_err_t err = FSP_SUCCESS; + err = r_cgc_divider_constraint_check(p_divider_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + #if BSP_FEATURE_CGC_HAS_PCLKA + + /* Check dividers against hardware constraints (see footnotes of table "Specifications of the clock generation + * circuit for the internal clocks" in the CGC section of the relevant hardware manual). */ + + /* ICLK frequency must be >= PCLKA, so ICLK divider must be <= PCLKA. */ + FSP_ASSERT(p_divider_cfg->sckdivcr_b.iclk_div <= p_divider_cfg->sckdivcr_b.pclka_div); + + /* PCLKA frequency must be >= PCLKB, so PCLKA divider must be <= PCLKB. */ + FSP_ASSERT(p_divider_cfg->sckdivcr_b.pclka_div <= p_divider_cfg->sckdivcr_b.pclkb_div); + + /* PCLKD frequency must be >= PCLKA, so PCLKD divider must be <= PCLKA. */ + FSP_ASSERT(p_divider_cfg->sckdivcr_b.pclkd_div <= p_divider_cfg->sckdivcr_b.pclka_div); + #elif BSP_FEATURE_CGC_HAS_PCLKB + + /* Check dividers against hardware constraints (see footnotes of table "Clock generation circuit specifications + * for the internal clocks" in the CGC section of the relevant hardware manual.). */ + + /* ICLK frequency must be >= PCLKB, so ICLK divider must be <= PCLKB. */ + FSP_ASSERT(p_divider_cfg->sckdivcr_b.iclk_div <= p_divider_cfg->sckdivcr_b.pclkb_div); + + /* PCLKD frequency must be >= PCLKB, so PCLKD divider must be <= PCLKB. */ + FSP_ASSERT(p_divider_cfg->sckdivcr_b.pclkd_div <= p_divider_cfg->sckdivcr_b.pclkb_div); + #endif + + #if BSP_FEATURE_CGC_HAS_FCLK + + /* ICLK frequency must be >= FCLK, so ICLK divider must be <= FCLK. */ + FSP_ASSERT(p_divider_cfg->sckdivcr_b.iclk_div <= p_divider_cfg->sckdivcr_b.fclk_div); + #endif + + #if BSP_FEATURE_CGC_HAS_BCLK + + /* ICLK frequency must be >= BCLK, so ICLK divider must be <= BCLK. */ + FSP_ASSERT(p_divider_cfg->sckdivcr_b.iclk_div <= p_divider_cfg->sckdivcr_b.bclk_div); + #endif + + #if BSP_FEATURE_CGC_REGISTER_SET_B + #if BSP_FEATURE_CGC_HAS_MOCO + + /* MOCODIV only supports CGC_SYS_CLOCK_DIV_1, CGC_SYS_CLOCK_DIV_2, CGC_SYS_CLOCK_DIV_4 */ + FSP_ASSERT((p_divider_cfg->moco_divider == CGC_SYS_CLOCK_DIV_1) || + (p_divider_cfg->moco_divider == CGC_SYS_CLOCK_DIV_2) || + (p_divider_cfg->moco_divider == CGC_SYS_CLOCK_DIV_4)); + #endif + #if BSP_FEATURE_CGC_HAS_MOSC + + /* MOSCDIV only supports CGC_SYS_CLOCK_DIV_1, CGC_SYS_CLOCK_DIV_2, CGC_SYS_CLOCK_DIV_4, CGC_SYS_CLOCK_DIV_8, CGC_SYS_CLOCK_DIV_16 */ + FSP_ASSERT((p_divider_cfg->mosc_divider == CGC_SYS_CLOCK_DIV_1) || + (p_divider_cfg->mosc_divider == CGC_SYS_CLOCK_DIV_2) || + (p_divider_cfg->mosc_divider == CGC_SYS_CLOCK_DIV_4) || + (p_divider_cfg->mosc_divider == CGC_SYS_CLOCK_DIV_8) || + (p_divider_cfg->mosc_divider == CGC_SYS_CLOCK_DIV_16)); + #endif + + #if (BSP_CFG_HOCO_FREQUENCY == 0) + + /* When OFS1.HOCOFRQ1[2:0] = 000b (HOCO = 24 MHz), HOCODIV only supports CGC_SYS_CLOCK_DIV_1, CGC_SYS_CLOCK_DIV_2, CGC_SYS_CLOCK_DIV_4, CGC_SYS_CLOCK_DIV_8 */ + FSP_ASSERT((p_divider_cfg->hoco_divider == CGC_SYS_CLOCK_DIV_1) || + (p_divider_cfg->hoco_divider == CGC_SYS_CLOCK_DIV_2) || + (p_divider_cfg->hoco_divider == CGC_SYS_CLOCK_DIV_4)); + #endif + #endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Check if the specified clock is valid + * + * @param[in] clock_source Clock to be verified + * + * @retval FSP_SUCCESS Clock source is supported. + * @retval FSP_ERR_ASSERTION Clock source is not supported. + **********************************************************************************************************************/ +static fsp_err_t r_cgc_clock_source_has_support (cgc_clock_t const clock_source) +{ + #if !BSP_FEATURE_CGC_HAS_MOCO + FSP_ASSERT(CGC_CLOCK_MOCO != clock_source); + #endif + #if !BSP_FEATURE_CGC_HAS_MOSC + FSP_ASSERT(CGC_CLOCK_MAIN_OSC != clock_source); + #endif + #if !BSP_PRV_PLL_SUPPORTED + FSP_ASSERT(CGC_CLOCK_PLL != clock_source); + #endif + #if !BSP_PRV_PLL2_SUPPORTED + FSP_ASSERT(CGC_CLOCK_PLL2 != clock_source); + #endif + FSP_PARAMETER_NOT_USED(clock_source); // unused in some build configurations + + return FSP_SUCCESS; +} + +#endif + +#if CGC_CFG_PARAM_CHECKING_ENABLE + #if BSP_PRV_PLL_SUPPORTED + +/*******************************************************************************************************************//** + * Check PLL configuration against hardware manual constraints. Also verify the PLL source clock is running and stable + * if requested. + * + * @param[in] p_pll_cfg Pointer to PLL configuration + * @param[in] verify_source_stable Whether or not to verify the source clock is running and stable + * + * @retval FSP_SUCCESS PLL configuration satisfies hardware manual constraints. + * @retval FSP_ERR_ASSERTION One or more divider PLL configurations do not satisfy constraints specified + * in the hardware manual. + * @retval FSP_ERR_OSC_STOP_DET_ENABLED PLL multiplier must be less than 20 if oscillation stop detect is enabled and + * the input frequency is less than 12.5 MHz. + * @retval FSP_ERR_PLL_SRC_INACTIVE PLL clock source is not running. + * @retval FSP_ERR_NOT_STABILIZED PLL clock source is not stable. + **********************************************************************************************************************/ +static fsp_err_t r_cgc_pll_parameter_check (cgc_pll_cfg_t const * const p_pll_cfg, bool verify_source_stable) +{ + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + /* Ensure PLL configuration is supported on this MCU (see "PLL Clock Control Register (PLLCCR)" description + * in the CGC section of the relevant hardware manual). */ + + /* PLLCCR clock source can only be main oscillator or HOCO. */ + FSP_ASSERT((CGC_CLOCK_MAIN_OSC == p_pll_cfg->source_clock) || (CGC_CLOCK_HOCO == p_pll_cfg->source_clock)); + + #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE + + /* Divider of 4 is not supported for PLLCCR. */ + FSP_ASSERT(CGC_PLL_DIV_4 != p_pll_cfg->divider); + + /* PLLCCR multiplier must be between 10 and 30. */ + FSP_ASSERT(p_pll_cfg->multiplier >= CGC_PLL_MUL_10_0); + FSP_ASSERT(p_pll_cfg->multiplier <= CGC_PLL_MUL_30_0); + #elif 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + + /* Divider of 2,3 is not supported for PLLCCR. */ + FSP_ASSERT(CGC_PLL_DIV_2 != p_pll_cfg->divider); + FSP_ASSERT(CGC_PLL_DIV_3 != p_pll_cfg->divider); + + /* PLLCCR multiplier must be between 4.0 and 15.5 */ + FSP_ASSERT(p_pll_cfg->multiplier >= CGC_PLL_MUL_4_0); + FSP_ASSERT(p_pll_cfg->multiplier <= CGC_PLL_MUL_15_5); + #endif + + #if BSP_CFG_XTAL_HZ < 12000000 + + /* PLLMUL must be 20 or less if oscillation stop detect is enabled and the input frequency is less than 12 MHz. HOCO + * cannot run at less than 16 MHz, so this only applies for the main oscillator. */ + if (R_SYSTEM->OSTDCR_b.OSTDE == 1U) + { + if (CGC_CLOCK_MAIN_OSC == p_pll_cfg->source_clock) + { + FSP_ERROR_RETURN(p_pll_cfg->multiplier <= CGC_PLL_MUL_20_0, FSP_ERR_OSC_STOP_DET_ENABLED); + } + } + #endif + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + /* Ensure PLL configuration is supported on this MCU, + * see "PLL Clock Control Register (PLLCCR)" description in the CGC section of the relevant hardware manual. */ + + /* PLLCCR clock source can only be main oscillator or HOCO. */ + FSP_ASSERT((CGC_CLOCK_MAIN_OSC == p_pll_cfg->source_clock) || (CGC_CLOCK_HOCO == p_pll_cfg->source_clock)); + + /* PLL Output dividers cannot be 16 for PLLQ and PLLR */ + FSP_ASSERT(CGC_PLL_OUT_DIV_16 != p_pll_cfg->out_div_q); + FSP_ASSERT(CGC_PLL_OUT_DIV_16 != p_pll_cfg->out_div_r); + + /* PLL Output dividers must not be 1.5, 5 or 9 for PLL*P. */ + FSP_ASSERT((CGC_PLL_OUT_DIV_5 != p_pll_cfg->out_div_p) && \ + (CGC_PLL_OUT_DIV_9 != p_pll_cfg->out_div_p) && \ + (CGC_PLL_OUT_DIV_1_5 != p_pll_cfg->out_div_p)); + + #if (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + /* PLL Output dividers 1.5 is not supported on this MCU */ + FSP_ASSERT(CGC_PLL_OUT_DIV_1_5 != p_pll_cfg->out_div_q); + FSP_ASSERT(CGC_PLL_OUT_DIV_1_5 != p_pll_cfg->out_div_r); + + /* PLL Output dividers must be even for PLL*P. */ + FSP_ASSERT(0 == (1U & p_pll_cfg->out_div_p)); + + /* PLLCCR multiplier must be between 53.00 and 180.00. */ + FSP_ASSERT(p_pll_cfg->multiplier >= CGC_PLL_MUL_53_0); + FSP_ASSERT(p_pll_cfg->multiplier <= CGC_PLL_MUL_180_0); + #else + + /* PLLCCR multiplier must be between 40.00 and 300.00. */ + FSP_ASSERT(p_pll_cfg->multiplier >= CGC_PLL_MUL_40_0); + FSP_ASSERT(p_pll_cfg->multiplier <= CGC_PLL_MUL_300_0); + #endif + #elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + + /* Ensure PLL configuration is supported on this MCU. + * Refer to the "PLL Clock Control Register (PLLCCR)" register definition in CGC section of the relevant hardware manual. */ + + /* PLLCCR clock source can only be the subclock. */ + FSP_ASSERT(CGC_CLOCK_SUBCLOCK == p_pll_cfg->source_clock); + + /* Divider of 2 is the only supported value for PLLCCR. */ + FSP_ASSERT(CGC_PLL_DIV_2 == p_pll_cfg->divider); + + /* PLLCCR multiplier must be 732 or 781. */ + FSP_ASSERT((p_pll_cfg->multiplier == CGC_PLL_MUL_732_0) || (p_pll_cfg->multiplier == CGC_PLL_MUL_781_0)); + #else + + /* Ensure PLL configuration is supported on this MCU (see "PLL Clock Control Register 2 (PLLCCR2)" description + * in the CGC section of the relevant hardware manual.). */ + + /* PLLCCR2 clock source can only be main oscillator. */ + FSP_ASSERT(CGC_CLOCK_MAIN_OSC == p_pll_cfg->source_clock); + + /* Only dividers of 2 and 4 supported for PLLCCR2. */ + FSP_ASSERT((CGC_PLL_DIV_2 == p_pll_cfg->divider) || (CGC_PLL_DIV_4 == p_pll_cfg->divider)); + + /* Only integer multipliers are supported for PLLCCR2. Integer multipliers have the lowest bit set in the enum + * value. */ + FSP_ASSERT(1U == (p_pll_cfg->multiplier & 1U)); + #endif + + if (verify_source_stable) + { + /* If the PLL source clock isn't running, the PLL cannot be started. */ + FSP_ERROR_RETURN(CGC_PRV_CLOCK_STATE_RUNNING == r_cgc_clock_run_state_get(p_pll_cfg->source_clock), + FSP_ERR_PLL_SRC_INACTIVE); + + /* Make sure the PLL source is stable before starting the PLL. */ + FSP_ERROR_RETURN((r_cgc_stabilization_check(p_pll_cfg->source_clock, CGC_PRV_CLOCK_STATE_RUNNING)), + FSP_ERR_NOT_STABILIZED); + } + + return FSP_SUCCESS; +} + + #endif +#endif + +#if BSP_PRV_PLL_SUPPORTED + +/*******************************************************************************************************************//** + * Calculates the new PLL frequency. + * + * @param[in] p_pll_cfg PLL configuration + * @param[in] pll PLL being configured + * @param[out] p_pll_hz Pointer to store PLL frequency in Hz + * + * @retval FSP_SUCCESS Requested PLL configuration meets hardware manual requirements. + * @retval FSP_ERR_ASSERTION Requested PLL configuration violates hardware manual constraints. + **********************************************************************************************************************/ +static fsp_err_t r_cgc_pll_hz_calculate (cgc_pll_cfg_t const * const p_pll_cfg, + cgc_clock_t pll, + uint32_t * const p_pll_hz) +{ + /* Calculate the PLL frequency and set PLLCCR. The PLL frequency is required to update SystemCoreClock after + * switching to PLL. */ + uint32_t pll_src_freq_hz = BSP_CFG_XTAL_HZ; + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + if (CGC_CLOCK_HOCO == p_pll_cfg->source_clock) + { + pll_src_freq_hz = BSP_HOCO_HZ; + } + + /* The nominal values of the PLL multiplier are equal to (the PLLMUL bitfield + 1) / 2. + * The highest value for PLLMUL + 1 is 60, and the maximum PLL source clock is 24 MHz. + * 60 * 24000000 = 1440000000 = 0x55D4A800, which does not overflow 32-bits. + */ + uint32_t clock_freq_multiplied = (pll_src_freq_hz * (p_pll_cfg->multiplier + 1U)) >> 1; + uint32_t divider = p_pll_cfg->divider + 1U; + + uint32_t pll_hz = clock_freq_multiplied / divider; + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify that the output PLL frequency is within the specified frequency range for this device. */ + #if BSP_FEATURE_CGC_HAS_PLL2 + if (CGC_CLOCK_PLL2 == pll) + { + FSP_ASSERT(pll_hz >= BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ); + FSP_ASSERT(pll_hz <= BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ); + } + else + #endif + { + FSP_ASSERT(pll_hz >= BSP_FEATURE_CGC_PLL_OUT_MIN_HZ); + FSP_ASSERT(pll_hz <= BSP_FEATURE_CGC_PLL_OUT_MAX_HZ); + } + #endif + FSP_PARAMETER_NOT_USED(pll); + + /* Store the calculated frequency in the provided pointer if there are no violations. */ + p_pll_hz[0] = pll_hz; + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + FSP_PARAMETER_NOT_USED(pll); + if (CGC_CLOCK_HOCO == p_pll_cfg->source_clock) + { + pll_src_freq_hz = BSP_HOCO_HZ; + } + + uint32_t input_divider = p_pll_cfg->divider + 1U; + + #if CGC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT((pll_src_freq_hz <= BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MAX_HZ) && + (pll_src_freq_hz >= BSP_FEATURE_CGC_PLL_INPUT_PRE_DIV_MIN_HZ)); + uint32_t reference_clock_hz = pll_src_freq_hz / input_divider; + FSP_ASSERT(BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ >= reference_clock_hz); + FSP_ASSERT(BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ <= reference_clock_hz); + #endif + + /* The multiplier can have a fractional component of either 1/3, 2/3, or 1/2. All of + * these fractions have a common multiple of 6, so scale the multiplier by that value. */ + uint32_t multiplier = ((p_pll_cfg->multiplier >> BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT) + 1) * CGC_PRV_PLL_MUL_COEFF; + uint8_t fractional = (uint8_t) (p_pll_cfg->multiplier & BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK); + + /* Convert the MULNF value to use a common multiple of 6. */ + if (fractional < 3U) + { + /* Values for 1/3 and 2/3 are 1 and 2 respectively therefore it only needs a coefficient of 2 applied. */ + fractional *= CGC_PRV_PLL_MUL_NF_COEFF; + } + else + { + /* Do nothing: the value of 1/2 is 3 so it will work without a coeficient being applied (3/6 = 1/2). */ + } + + /* Add the fractional value into the scaled integer multiplier. */ + multiplier += fractional; + + /* The highest value for PLLMUL + 1 is 180, the highest fraction for PLLMULNF is 0.66, and the maximum PLL source + * clock is 48 MHz. The VCO frequency can be calculated to be more than 32-bits. Not using reference_clock_hz + * to avoid rounding errors. + */ + uint64_t vco_hz = ((uint64_t) pll_src_freq_hz * (uint64_t) multiplier) / CGC_PRV_PLL_MUL_FACTOR / input_divider; + + uint32_t out_div_q = p_pll_cfg->out_div_q; + uint32_t out_div_r = p_pll_cfg->out_div_r; + uint32_t pllq_k_coff = 1U; + uint32_t pllr_k_coff = 1U; + #if (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + if (CGC_PLL_OUT_DIV_1_5 == out_div_q) + { + pllq_k_coff = 2U; + out_div_q = CGC_PLL_OUT_DIV_3; + } + + if (CGC_PLL_OUT_DIV_1_5 == out_div_r) + { + pllr_k_coff = 2U; + out_div_r = CGC_PLL_OUT_DIV_3; + } + #endif + p_pll_hz[0] = (uint32_t) (vco_hz / p_pll_cfg->out_div_p); + p_pll_hz[1] = (uint32_t) ((pllq_k_coff * vco_hz) / out_div_q); + p_pll_hz[2] = (uint32_t) ((pllr_k_coff * vco_hz) / out_div_r); + + #if CGC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ >= vco_hz); + FSP_ASSERT(BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ <= vco_hz); + uint32_t pll_out_limit_hz = BSP_FEATURE_CGC_PLL_OUT_MAX_HZ; + if (CGC_CLOCK_PLL2 == pll) + { + pll_out_limit_hz = BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ; + } + + FSP_ASSERT(pll_out_limit_hz >= p_pll_hz[0]); + FSP_ASSERT(pll_out_limit_hz >= p_pll_hz[1]); + FSP_ASSERT(pll_out_limit_hz >= p_pll_hz[2]); + #endif + #elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + FSP_PARAMETER_NOT_USED(pll); + + /* PLLCCR type 4 only supports the subclock as a source. */ + pll_src_freq_hz = BSP_SUB_CLOCK_HZ; + + uint32_t multiplier = (p_pll_cfg->multiplier + BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET); + uint32_t clock_freq_multiplied = pll_src_freq_hz * multiplier; + + uint32_t pll_hz = clock_freq_multiplied >> 1; // Always div-by-2 for this PLLCCR type. + + /* Store the calculated frequency in the provided pointer if there are no violations. */ + p_pll_hz[0] = pll_hz; + #else // 2U == BSP_FEATURE_CGC_PLLCCR_TYPE + FSP_PARAMETER_NOT_USED(pll); + + uint32_t multiplier = (p_pll_cfg->multiplier + 1U) >> 1; + uint32_t clock_freq_multiplied = pll_src_freq_hz * multiplier; + uint32_t divider_shift = p_pll_cfg->divider; + if (CGC_PLL_DIV_4 == p_pll_cfg->divider) + { + divider_shift = 2; + } + + uint32_t pll_hz = clock_freq_multiplied >> divider_shift; + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* The following restrictions apply to the PLL on this MCU (see table "Clock generation circuit specifications + * for the clock sources" in the CGC section of the relevant hardware manual.): + * - The PLL input frequency must be between 4 MHz and 12.5 MHz. + * - The maximum frequency after multiplication is 128 MHz. + * - The minimum frequency is 24 MHz. + */ + FSP_ASSERT((pll_src_freq_hz <= BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MAX_HZ) && + (pll_src_freq_hz >= BSP_FEATURE_CGC_PLL_INPUT_POST_DIV_MIN_HZ)); + FSP_ASSERT(clock_freq_multiplied <= (BSP_FEATURE_CGC_PLL_OUT_MAX_HZ * 2U)); + FSP_ASSERT(pll_hz >= BSP_FEATURE_CGC_PLL_OUT_MIN_HZ); + #endif + FSP_PARAMETER_NOT_USED(pll); + + /* Store the calculated frequency in the provided pointer if there are no violations. */ + p_pll_hz[0] = pll_hz; + #endif + + return FSP_SUCCESS; +} + +#endif + +#if BSP_PRV_PLL_SUPPORTED + +/*******************************************************************************************************************//** + * Calculate PLL registers for PLL clock start + * + * @param[in] p_pll_cfg Pointer to clock system configuration + * + * @return PLLCCR register value + **********************************************************************************************************************/ +static uint32_t r_cgc_pllccr_calculate (cgc_pll_cfg_t const * const p_pll_cfg) +{ + /* Set the PLL control register. */ + #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE || 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 5U == BSP_FEATURE_CGC_PLLCCR_TYPE || \ + 6U == BSP_FEATURE_CGC_PLLCCR_TYPE + uint16_t plsrcsel = 0U; + if (CGC_CLOCK_HOCO == p_pll_cfg->source_clock) + { + plsrcsel = 1U; + } + + uint16_t pllmul = (uint16_t) p_pll_cfg->multiplier; + #if 5U == BSP_FEATURE_CGC_PLLCCR_TYPE + + /* Type 5 has a different register value mapping than anything else for the PLIDIV. */ + uint16_t plidiv = (uint16_t) p_pll_cfg->divider >> 1; + #else + uint16_t plidiv = (uint16_t) p_pll_cfg->divider; + #endif + uint32_t register_value = ((((pllmul & CGC_PRV_PLLCCR_PLLMUL_MASK) << CGC_PRV_PLLCCR_PLLMUL_BIT) | + (uint32_t) (plsrcsel << CGC_PRV_PLLCCR_PLSRCSEL_BIT)) | plidiv); + + return register_value; + #elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + uint8_t pllmul = (uint8_t) (p_pll_cfg->multiplier); + + uint32_t register_value = ((pllmul & CGC_PRV_PLLCCR_PLLMUL_MASK) << CGC_PRV_PLLCCR_PLLMUL_BIT) | + CGC_PRV_PLLCCR_PLLMUL_DEFAULT_BIT; + + return register_value; + #else // 2U == BSP_FEATURE_CGC_PLLCCR_TYPE + uint8_t pllmul = (uint8_t) p_pll_cfg->multiplier >> 1; + uint8_t plodiv = (uint8_t) p_pll_cfg->divider; + if (CGC_PLL_DIV_4 == p_pll_cfg->divider) + { + plodiv = 2U; + } + + uint32_t register_value = + ((pllmul & CGC_PRV_PLLCCR2_PLLMUL_MASK) | (uint32_t) (plodiv << CGC_PRV_PLLCCR2_PLODIV_BIT)); + + return register_value; + #endif +} + + #if 3U == BSP_FEATURE_CGC_PLLCCR_TYPE || 6U == BSP_FEATURE_CGC_PLLCCR_TYPE + +/*******************************************************************************************************************//** + * Calculate PLL registers for PLL clock start + * + * @param[in] p_pll_cfg Pointer to clock system configuration + * + * @return PLLCCR register value + **********************************************************************************************************************/ +static uint16_t r_cgc_pllccr2_calculate (cgc_pll_cfg_t const * const p_pll_cfg) +{ + + /* Configure the output clock dividers. */ + return (uint16_t) ((((p_pll_cfg->out_div_p - 1) & CGC_PRV_PLLCCR2_PLODIVX_MASK) << CGC_PRV_PLLCCR2_PLODIVP_BIT) | + (((p_pll_cfg->out_div_q - 1) & CGC_PRV_PLLCCR2_PLODIVX_MASK) << CGC_PRV_PLLCCR2_PLODIVQ_BIT) | + (((p_pll_cfg->out_div_r - 1) & CGC_PRV_PLLCCR2_PLODIVX_MASK) << CGC_PRV_PLLCCR2_PLODIVR_BIT)); +} + + #endif +#endif + +#if BSP_PRV_PLL_SUPPORTED + +/*******************************************************************************************************************//** + * This function returns the PLL clock source. + * + * @return PLL clock source + **********************************************************************************************************************/ +static inline cgc_clock_t r_cgc_pll_clocksource_get (void) +{ + /* PLL source selection only available on PLLCCR */ + cgc_clock_t pll_src = CGC_CLOCK_MAIN_OSC; + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + /* Get the PLL clock source */ + if (R_SYSTEM->PLLCCR_b.PLSRCSEL == 1U) + { + pll_src = CGC_CLOCK_HOCO; + } + + #elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + pll_src = CGC_CLOCK_SUBCLOCK; + #endif + + return pll_src; +} + +#endif + +#if BSP_PRV_PLL2_SUPPORTED && CGC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * This function returns the PLL2 clock source. + * + * @return PLL2 clock source + **********************************************************************************************************************/ +static inline cgc_clock_t r_cgc_pll2_clocksource_get (void) +{ + return R_SYSTEM->PLL2CCR_b.PL2SRCSEL == 1U ? CGC_CLOCK_HOCO : CGC_CLOCK_MAIN_OSC; +} + +#endif + +#if BSP_PRV_PLL_SUPPORTED + +/*******************************************************************************************************************//** + * Calculate requested PLL frequency and PLLCCR value. + * + * @param[in] p_pll_cfg Pointer to clock system configuration. + * @param[in] pll PLL to be configured (if PLL2 is supported). + * @param[out] p_pll_hz Pointer to store calculated PLL output frequency. + * @param[out] p_pllccr Pointer to store calculated PLLCCR value. + * + * @retval FSP_SUCCESS No errors detected in PLL configuration. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_CLOCK_ACTIVE PLL configuration cannot be changed while PLL is running. + **********************************************************************************************************************/ +static fsp_err_t r_cgc_pllccr_pll_hz_calculate (cgc_pll_cfg_t const * const p_pll_cfg, + cgc_clock_t pll, + uint32_t * const p_pll_hz, + uint32_t * const p_pllccr) +{ + #if !BSP_PRV_PLL2_SUPPORTED + FSP_PARAMETER_NOT_USED(pll); + #endif + + /* Calculate the PLLCCR register. */ + uint32_t pllccr = r_cgc_pllccr_calculate(p_pll_cfg); + + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + volatile uint16_t * p_pllccr_reg; + #elif (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + volatile uint32_t * p_pllccr_reg; + #else + volatile uint8_t * p_pllccr_reg; + #endif + + #if BSP_PRV_PLL2_SUPPORTED + if (CGC_CLOCK_PLL == pll) + #endif + { + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) || \ + (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + + p_pllccr_reg = &(R_SYSTEM->PLLCCR); + #else + p_pllccr_reg = &(R_SYSTEM->PLLCCR2); + #endif + } + + #if BSP_PRV_PLL2_SUPPORTED + else + { + p_pllccr_reg = &(R_SYSTEM->PLL2CCR); + } + #endif + + /* PLLCCR cannot be changed while PLL is running. Verify requested PLLCCR value is unchanged or the PLL is + * currently stopped. */ + FSP_ERROR_RETURN((*p_pllccr_reg == pllccr) || (CGC_PRV_CLOCK_STATE_STOPPED == r_cgc_clock_run_state_get(pll)), + FSP_ERR_CLOCK_ACTIVE); + + /* Calculate the new PLL frequency. Parameter checking is performed during this calculation if parameter + * checking is enabled, but the calculation is required even if parameter checking is not enabled. */ + fsp_err_t err = r_cgc_pll_hz_calculate(p_pll_cfg, pll, p_pll_hz); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + *p_pllccr = pllccr; + + return FSP_SUCCESS; +} + +#endif + +#if BSP_PRV_PLL_SUPPORTED + +/*******************************************************************************************************************//** + * Set PLLCCR/PLLCCR2 and store PLL frequency in the BSP. + * + * @param[in] p_pll_cfg Pointer to PLL configuration. + * @param[in] pll Which PLL is being configured. + * @param[in] pll_hz Previously calculated PLL frequency + * @param[in] pllccr Previously calculated PLLCCR value + **********************************************************************************************************************/ +static void r_cgc_pll_cfg (cgc_pll_cfg_t const * const p_pll_cfg, + cgc_clock_t pll, + uint32_t const * const pll_hz, + uint32_t pllccr) +{ + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_PRV_PLL2_SUPPORTED + if (CGC_CLOCK_PLL == pll) + #endif + { + R_SYSTEM->PLLCCR = (uint16_t) pllccr; + } + + #if BSP_PRV_PLL2_SUPPORTED + else + { + R_SYSTEM->PLL2CCR = (uint16_t) pllccr; + } + #endif + FSP_PARAMETER_NOT_USED(p_pll_cfg); + #elif 2U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR2 = (uint8_t) pllccr; + FSP_PARAMETER_NOT_USED(p_pll_cfg); + #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (6U == BSP_FEATURE_CGC_PLLCCR_TYPE) + uint16_t pllccr2 = r_cgc_pllccr2_calculate(p_pll_cfg); + #if BSP_PRV_PLL2_SUPPORTED + if (CGC_CLOCK_PLL == pll) + #endif + { + #if 6U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR = pllccr; + #else + R_SYSTEM->PLLCCR = (uint16_t) pllccr; + #endif + R_SYSTEM->PLLCCR2 = pllccr2; + } + + #if BSP_PRV_PLL2_SUPPORTED + else + { + #if 6U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLL2CCR = pllccr; + #else + R_SYSTEM->PLL2CCR = (uint16_t) pllccr; + #endif + R_SYSTEM->PLL2CCR2 = pllccr2; + } + #endif + #elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + R_SYSTEM->PLLCCR = (uint16_t) pllccr | CGC_PRV_PLLCCR_RESET_VALUE; + FSP_PARAMETER_NOT_USED(p_pll_cfg); + #endif + + /* Update the PLL frequency in the BSP. */ + bsp_prv_prepare_pll(pll, pll_hz); + + #if BSP_FEATURE_CGC_PLLCCR_WAIT_US > 0 + + /* This loop is provided to ensure at least 1 us passes between setting PLLMUL and clearing PLLSTP on some + * MCUs (see PLLSTP notes in "PLL Control Register (PLLCR)" description in the CGC section of the relevant hardware manual.) + * Five loops are needed here to ensure the most efficient path takes at least 1 us from the setting of + * PLLMUL to the clearing of PLLSTP. HOCO is the fastest clock we can be using here since PLL cannot be running + * while setting PLLCCR. */ + bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(BSP_PRV_MAX_HOCO_CYCLES_PER_US)); + #endif +} + +#endif + +#if BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT + +/*******************************************************************************************************************//** + * Internal NMI ISR callback which calls the user provided callback passing the context provided by the user. + * + * @param[in] irq IRQ which has triggered the NMI interrupt. + **********************************************************************************************************************/ +static void r_cgc_nmi_internal_callback (bsp_grp_irq_t irq) +{ + FSP_PARAMETER_NOT_USED(irq); + + /* Call user registered callback */ + if (NULL != gp_cgc_ctrl) + { + if (NULL != gp_cgc_ctrl->p_callback) + { + cgc_callback_args_t args; + + cgc_callback_args_t * p_args = gp_cgc_ctrl->p_callback_memory; + if (NULL == p_args) + { + p_args = &args; + } + else + { + args = *p_args; + } + + p_args->event = CGC_EVENT_OSC_STOP_DETECT_NMI; + p_args->p_context = gp_cgc_ctrl->p_context; + + #if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(gp_cgc_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + gp_cgc_ctrl->p_callback(&args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + cgc_prv_ns_callback p_callback = (cgc_prv_ns_callback) (gp_cgc_ctrl->p_callback); + p_callback(p_args); + } + + #else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + gp_cgc_ctrl->p_callback(&args); + #endif + + if (NULL != gp_cgc_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *gp_cgc_ctrl->p_callback_memory = args; + } + } + } +} + +#endif + +#if BSP_FEATURE_CGC_HAS_OSTDCSE + +/*******************************************************************************************************************//** + * Configures interrupts and ensures required interrupts are enabled. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_extend Pointer to configuration structure + * + * @retval FSP_SUCCESS All required interrupts enabled. + **********************************************************************************************************************/ +static fsp_err_t r_cgc_open_irq_cfg (cgc_instance_ctrl_t * const p_instance_ctrl, cgc_extended_cfg_t * const p_extend) +{ + /* Set the interrupt priorities. */ + if (p_extend->mostd_irq >= 0) + { + R_BSP_IrqCfgEnable(p_extend->mostd_irq, p_extend->mostd_ipl, p_instance_ctrl); + } + + if (p_extend->sostd_irq >= 0) + { + R_BSP_IrqCfgEnable(p_extend->sostd_irq, p_extend->sostd_ipl, p_instance_ctrl); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables an interrupt. + * + * @param[in] irq Interrupt to disable + **********************************************************************************************************************/ +static void r_cgc_disable_irq (IRQn_Type irq) +{ + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + R_FSP_IsrContextSet(irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Clears interrupt flag and calls a callback to notify application of the event. + * + * @param[in] event Event that triggered the ISR + **********************************************************************************************************************/ +static void r_cgc_ostd_common_isr (cgc_event_t event) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + cgc_instance_ctrl_t * p_instance_ctrl = (cgc_instance_ctrl_t *) R_FSP_IsrContextGet(R_FSP_CurrentIrqGet()); + + /* Clear the BSP IRQ Flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + cgc_callback_args_t args; + args.event = event; + + /* Populate the context field. */ + args.p_context = p_instance_ctrl->p_context; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_callback) + { + p_instance_ctrl->p_callback(&args); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * This function implements maskable interrupt handler for Main Oscillation Stop Detection for SDADCCLK Clock + * + **********************************************************************************************************************/ +void cgc_mostd_isr (void) +{ + /* Call common isr handler. */ + r_cgc_ostd_common_isr(CGC_EVENT_OSC_STOP_DETECT_MAIN_OSC); +} + +/*******************************************************************************************************************//** + * This function implements maskable interrupt handler for Sub Clock Oscillation Stop Detection for SDADCCLK Clock + * + **********************************************************************************************************************/ +void cgc_sostd_isr (void) +{ + /* Call common isr handler. */ + r_cgc_ostd_common_isr(CGC_EVENT_OSC_STOP_DETECT_SUBCLOCK); +} + +#endif + +#if CGC_CFG_PARAM_CHECKING_ENABLE && BSP_FEATURE_CGC_HAS_CPUCLK + +/*******************************************************************************************************************//** + * Check the requested division and ensure that new configuration will not violate the clock constraint. + * + * @param[in] p_divider_cfg Pointer to new configuration struct. + * + * @retval FSP_ERR_ASSERTION Requested division violates the clock constraint. + * @retval FSP_SUCCESS Requested division is valid. + ***********************************************************************************************************************/ +static fsp_err_t r_cgc_divider_constraint_check (cgc_divider_cfg_t const * const p_divider_cfg) +{ + /* CPUCLK0 frequency must be >= ICLK, so CPUCLK0 divider must be <= ICLK divider. */ + FSP_ASSERT(p_divider_cfg->sckdivcr2_b.cpuclk_div <= p_divider_cfg->sckdivcr_b.iclk_div); + + /* If any divider is using /3, /6, /12 or /24, all must use /1, /3, /6, /12 or /24. */ + if ((0U != (p_divider_cfg->sckdivcr2 & CGC_PRV_SCKDIVCR2_DIV_3_BITS)) || + (0U != (p_divider_cfg->sckdivcr_w & CGC_PRV_SCKDIVCR_DIV_3_BITS))) + { + uint32_t tmp_divider = p_divider_cfg->sckdivcr_w; + + /* Loop through SCKDIVCR and check the division value of each clock. */ + for (uint8_t i = 0U; i < 8U; i++) + { + FSP_ASSERT((0U == (tmp_divider & 0xFU)) || (0x8U <= (tmp_divider & 0xFU))); + tmp_divider >>= 4U; + } + + tmp_divider = p_divider_cfg->sckdivcr2; + + /* Loop through SCKDIVCR2 and check the division value of each clock. */ + for (uint8_t j = 0U; j < CGC_PRV_SCKDIVCR2_NUM_CLOCKS; j++) + { + FSP_ASSERT((0 == (tmp_divider & 0xFU)) || (0x8U <= (tmp_divider & 0xFU))); + tmp_divider >>= 4U; + } + } + + #if BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS + + /* CPUCLK1 divider must be less than or equal to ICLK divider. */ + FSP_ASSERT(p_divider_cfg->sckdivcr2_b.cpuclk1_div <= p_divider_cfg->sckdivcr_b.iclk_div); + + /* NPUCLK divider must be less than or equal to ICLK divider. */ + FSP_ASSERT(p_divider_cfg->sckdivcr2_b.npuclk_div <= p_divider_cfg->sckdivcr_b.iclk_div); + + /* MRICLK divider must be less than or equal to ICLK divider. */ + FSP_ASSERT(p_divider_cfg->sckdivcr2_b.mriclk_div <= p_divider_cfg->sckdivcr_b.iclk_div); + + /* CPUCLK divider must be less than or equal to MRICLK divider. */ + FSP_ASSERT(p_divider_cfg->sckdivcr2_b.cpuclk_div <= p_divider_cfg->sckdivcr2_b.mriclk_div); + + /* CPUCLK1 divider must be less than or equal to MRICLK divider. */ + FSP_ASSERT(p_divider_cfg->sckdivcr2_b.cpuclk1_div <= p_divider_cfg->sckdivcr2_b.mriclk_div); + + /* NPUCLK divider must be less than or equal to MRICLK divider. */ + FSP_ASSERT(p_divider_cfg->sckdivcr2_b.npuclk_div <= p_divider_cfg->sckdivcr2_b.mriclk_div); + #endif + + return FSP_SUCCESS; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_crc/r_crc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_crc/r_crc.c new file mode 100644 index 0000000000..d89d7cb5ce --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_crc/r_crc.c @@ -0,0 +1,482 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_crc.h" +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "CRC" in ASCII, used to determine if channel is open. */ +#define CRC_OPEN (0x00435243ULL) + +#define CRC_CRCCR1_CRCSWR_SHIFT (5) + +/* Snoop address + * TDR and RDR depends on MCU. + * FTDRL is always 0x**F while FRDRL is always 0x**1. + */ +#define CRC_SNOOP_ADDRESS_TYPE_MASK (0x0FU) +#define CRC_SNOOP_ADDRESS_TYPE_FTDRL (0x0FU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void crc_calculate_polynomial(crc_instance_ctrl_t * const p_instance_ctrl, + crc_input_t * const p_crc_input, + uint32_t * calculatedValue); + +static void crc_seed_value_update(crc_instance_ctrl_t * const p_instance_ctrl, uint32_t crc_seed); +static uint32_t crc_calculated_value_get(crc_instance_ctrl_t * const p_instance_ctrl); + +#if CRC_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_crc_open_cfg_check(crc_cfg_t const * const p_cfg); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Filled in Interface API structure for this Instance. */ +const crc_api_t g_crc_on_crc = +{ + .open = R_CRC_Open, + .close = R_CRC_Close, + .calculate = R_CRC_Calculate, + .crcResultGet = R_CRC_CalculatedValueGet, + .snoopEnable = R_CRC_SnoopEnable, + .snoopDisable = R_CRC_SnoopDisable, +}; + +/*******************************************************************************************************************//** + * @addtogroup CRC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Open the CRC driver module + * + * Implements @ref crc_api_t::open + * + * Open the CRC driver module and initialize the driver control block according to the passed-in + * configuration structure. + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION p_ctrl or p_cfg is NULL. + * @retval FSP_ERR_ALREADY_OPEN Module already open + * @retval FSP_ERR_UNSUPPORTED Hardware not support this feature. + **********************************************************************************************************************/ +fsp_err_t R_CRC_Open (crc_ctrl_t * const p_ctrl, crc_cfg_t const * const p_cfg) +{ + crc_instance_ctrl_t * p_instance_ctrl = (crc_instance_ctrl_t *) p_ctrl; + +#if CRC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + + /* Verify the configuration parameters are valid */ + fsp_err_t err = r_crc_open_cfg_check(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify the control block has not already been initialized. */ + FSP_ERROR_RETURN(CRC_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Save the configuration */ + p_instance_ctrl->p_cfg = p_cfg; + + /* Mark driver as initialized by setting the open value to the ASCII equivalent of "CRC" */ + p_instance_ctrl->open = CRC_OPEN; + + /* Power on CRC */ + R_BSP_MODULE_START(FSP_IP_CRC, 0); + + uint8_t crccr0 = 0; +#if BSP_FEATURE_CRC_HAS_CRCCR0_LMS + + /* Set bit order value */ + crccr0 = (uint8_t) (p_instance_ctrl->p_cfg->bit_order << R_CRC_CRCCR0_LMS_Pos); +#endif + + /* Set CRC polynomial */ + crccr0 |= (uint8_t) (p_instance_ctrl->p_cfg->polynomial << R_CRC_CRCCR0_GPS_Pos); + + /* Set DORCLR to clear CRCDOR */ + crccr0 |= (uint8_t) (1 << R_CRC_CRCCR0_DORCLR_Pos); + + R_CRC->CRCCR0 = crccr0; + +#if BSP_FEATURE_CRC_HAS_SNOOP + + /* Disable snooping */ + R_CRC->CRCCR1 = 0; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Close the CRC module driver. + * + * Implements @ref crc_api_t::close + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The driver is not opened. + * + **********************************************************************************************************************/ +fsp_err_t R_CRC_Close (crc_ctrl_t * const p_ctrl) +{ + crc_instance_ctrl_t * p_instance_ctrl = (crc_instance_ctrl_t *) p_ctrl; + +#if CRC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(CRC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + R_BSP_MODULE_STOP(FSP_IP_CRC, 0); + + /* Mark driver as closed */ + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Perform a CRC calculation on a block of 8-bit/32-bit (for 32-bit polynomial) data. + * + * Implements @ref crc_api_t::calculate + * + * This function performs a CRC calculation on an array of 8-bit/32-bit (for 32-bit polynomial) values and + * returns an 8-bit/32-bit (for 32-bit polynomial) calculated value + * + * @retval FSP_SUCCESS Calculation successful. + * @retval FSP_ERR_ASSERTION Either p_ctrl, inputBuffer, or calculatedValue is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT length value is NULL, or not 4-byte aligned when 32-bit CRC polynomial function is configured. + * @retval FSP_ERR_NOT_OPEN The driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_CRC_Calculate (crc_ctrl_t * const p_ctrl, crc_input_t * const p_crc_input, uint32_t * calculatedValue) +{ + crc_instance_ctrl_t * p_instance_ctrl = (crc_instance_ctrl_t *) p_ctrl; +#if CRC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_crc_input->p_input_buffer); + FSP_ASSERT(calculatedValue); + FSP_ERROR_RETURN((0UL != p_crc_input->num_bytes), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(CRC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + if ((p_instance_ctrl->p_cfg->polynomial == CRC_POLYNOMIAL_CRC_32) || + (p_instance_ctrl->p_cfg->polynomial == CRC_POLYNOMIAL_CRC_32C)) + { + FSP_ERROR_RETURN((p_crc_input->num_bytes & 0x03) == 0, FSP_ERR_INVALID_ARGUMENT); + } +#endif + + /* Calculate CRC value for the input buffer */ + crc_calculate_polynomial(p_instance_ctrl, p_crc_input, calculatedValue); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Return the current calculated value. + * + * Implements @ref crc_api_t::crcResultGet + * + * CRC calculation operates on a running value. This function returns the current calculated value. + * + * @retval FSP_SUCCESS Return of calculated value successful. + * @retval FSP_ERR_ASSERTION Either p_ctrl or calculatedValue is NULL. + * @retval FSP_ERR_NOT_OPEN The driver is not opened. + * + **********************************************************************************************************************/ +fsp_err_t R_CRC_CalculatedValueGet (crc_ctrl_t * const p_ctrl, uint32_t * calculatedValue) +{ + crc_instance_ctrl_t * p_instance_ctrl = (crc_instance_ctrl_t *) p_ctrl; + +#if CRC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(calculatedValue); + FSP_ERROR_RETURN(CRC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Based on the selected polynomial, return the calculated CRC value */ + *calculatedValue = crc_calculated_value_get(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configure the snoop channel and set the CRC seed. + * + * Implements @ref crc_api_t::snoopEnable + * + * The CRC calculator can operate on reads and writes over any of the first ten SCI channels. + * For example, if set to channel 0, transmit, every byte written out SCI channel 0 is also + * sent to the CRC calculator as if the value was explicitly written directly to the CRC calculator. + * + * @retval FSP_SUCCESS Snoop configured successfully. + * @retval FSP_ERR_ASSERTION Pointer to control structure is NULL + * @retval FSP_ERR_NOT_OPEN The driver is not opened. + * @retval FSP_ERR_UNSUPPORTED SNOOP operation is not supported. + * + **********************************************************************************************************************/ +fsp_err_t R_CRC_SnoopEnable (crc_ctrl_t * const p_ctrl, uint32_t crc_seed) +{ +#if BSP_FEATURE_CRC_HAS_SNOOP + crc_instance_ctrl_t * p_instance_ctrl = (crc_instance_ctrl_t *) p_ctrl; + + #if CRC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(CRC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + crc_seed_value_update(p_instance_ctrl, crc_seed); + + /* Set CRC snoop address */ + R_CRC->CRCSAR = + (uint16_t) ((p_instance_ctrl->p_cfg->snoop_address & R_CRC_CRCSAR_CRCSA_Msk) << + R_CRC_CRCSAR_CRCSA_Pos); + + /* + * Enable snoop operation and set direction: + */ + uint8_t addr = (uint8_t) p_instance_ctrl->p_cfg->snoop_address & CRC_SNOOP_ADDRESS_TYPE_MASK; + if ((BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR == addr) || (CRC_SNOOP_ADDRESS_TYPE_FTDRL == addr)) + { + R_CRC->CRCCR1 = (uint8_t) ((1UL << R_CRC_CRCCR1_CRCSEN_Pos) | (1UL << R_CRC_CRCCR1_CRCSWR_Pos)); + } + else + { + R_CRC->CRCCR1 = (uint8_t) (1 << R_CRC_CRCCR1_CRCSEN_Pos); + } + + FSP_REGISTER_READ(R_CRC->CRCCR1_b.CRCSWR); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(crc_seed); + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Disable snooping. + * + * Implements @ref crc_api_t::snoopDisable + * + * @retval FSP_SUCCESS Snoop disabled. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The driver is not opened. + * @retval FSP_ERR_UNSUPPORTED SNOOP operation is not supported. + * + **********************************************************************************************************************/ +fsp_err_t R_CRC_SnoopDisable (crc_ctrl_t * const p_ctrl) +{ +#if BSP_FEATURE_CRC_HAS_SNOOP + #if CRC_CFG_PARAM_CHECKING_ENABLE + crc_instance_ctrl_t * p_instance_ctrl = (crc_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(CRC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + FSP_PARAMETER_NOT_USED(p_ctrl); + + /* Clear CRCSEN to disable snoop operation */ + R_CRC->CRCCR1 = 0; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/** @} (end addtogroup CRC) */ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Update CRC seed value + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] crc_seed CRC seed value + **********************************************************************************************************************/ +static void crc_seed_value_update (crc_instance_ctrl_t * const p_instance_ctrl, uint32_t crc_seed) +{ + uint32_t crcdor = 0; + + /* Based on the selected polynomial, set the initial CRC seed value */ + switch (p_instance_ctrl->p_cfg->polynomial) + { + case CRC_POLYNOMIAL_CRC_8: + { + /* CRC seed is masked to use only the lower 8 bits*/ + /* Set the starting 8-bit CRC Calculated value */ + crcdor |= (uint32_t) (R_CRC_CRCDOR_BY_CRCDOR_BY_Msk & crc_seed); + R_CRC->CRCDOR_BY = (uint8_t) crcdor; + break; + } + + case CRC_POLYNOMIAL_CRC_16: + case CRC_POLYNOMIAL_CRC_CCITT: + { + /* CRC seed is masked to use only the lower 16 bits*/ + /* Set the starting 16-bit CRC Calculated value. */ + crcdor |= (uint32_t) (R_CRC_CRCDOR_HA_CRCDOR_HA_Msk & crc_seed); + R_CRC->CRCDOR_HA = (uint16_t) crcdor; + break; + } + + default: + { + /* CRC seed uses the 32 bits*/ + R_CRC->CRCDOR = crc_seed; + break; + } + } +} + +/*******************************************************************************************************************//** + * Get CRC value + * + * @param[in] p_instance_ctrl Pointer to instance control block + **********************************************************************************************************************/ +static uint32_t crc_calculated_value_get (crc_instance_ctrl_t * const p_instance_ctrl) +{ + uint32_t calculatedValue = 0; + + /* Based on the selected polynomial, return the calculated CRC value */ + switch (p_instance_ctrl->p_cfg->polynomial) + { + case CRC_POLYNOMIAL_CRC_8: + { + /* Set bit order value */ + calculatedValue = (uint32_t) R_CRC->CRCDOR_BY; + break; + } + + case CRC_POLYNOMIAL_CRC_16: + case CRC_POLYNOMIAL_CRC_CCITT: + { + /* Set bit order value */ + calculatedValue = (uint32_t) R_CRC->CRCDOR_HA; + break; + } + + default: + { + /* Set bit order value */ + calculatedValue = R_CRC->CRCDOR; + break; + } + } + + return calculatedValue; +} + +/*******************************************************************************************************************//** + * Perform a CRC calculation on a block of data. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_crc_input Pointer to input data structure + * @param[out] calculatedValue Pointer to the CRC result + * + **********************************************************************************************************************/ +static void crc_calculate_polynomial (crc_instance_ctrl_t * const p_instance_ctrl, + crc_input_t * const p_crc_input, + uint32_t * calculatedValue) +{ + uint32_t i; + const void * inputBuffer = p_crc_input->p_input_buffer; + uint32_t length = p_crc_input->num_bytes; + uint32_t crc_seed = p_crc_input->crc_seed; + crc_seed_value_update(p_instance_ctrl, crc_seed); + + /* Write each element of the inputBuffer to the CRC Data Input Register. Each write to the + * Data Input Register generates a new calculated value in the Data Output Register. */ + switch (p_instance_ctrl->p_cfg->polynomial) + { + case CRC_POLYNOMIAL_CRC_8: + case CRC_POLYNOMIAL_CRC_16: + case CRC_POLYNOMIAL_CRC_CCITT: + { + const uint8_t * p_data = inputBuffer; + for (i = (uint32_t) 0; i < length; i++) + { + /* CRCDIR is a 32-bit read/write register to write data to for CRC-32 or CRC-32C calculation. + * CRCDIR_BY is an 8-bit read/write register to write data to for CRC-8, CRC-16, or CRC-CCITT + * calculation. Reference section "CRC Data Input Register (CRCDIR/CRCDIR_BY)" + * of the relevant hardware manual. Write an 8-bit value to the input register of the CRC Calculator */ + R_CRC->CRCDIR_BY = *p_data; + p_data = (p_data + 1UL); + } + + break; + } + + default: + { + const uint32_t * p_data = inputBuffer; + + for (i = (uint32_t) 0; i < (length / 4); i++) + { + /* Write a 32-bit value to the input register of the CRC Calculator */ + R_CRC->CRCDIR = *p_data; + p_data = p_data + 1; + } + + break; + } + } + + /* Return the calculated value */ + *calculatedValue = crc_calculated_value_get(p_instance_ctrl); +} + +#if CRC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Validates the configuration arguments for illegal combinations or options. + * + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS No configuration errors detected + * @retval FSP_ERR_ASSERTION An input argument is invalid. + * @retval FSP_ERR_UNSUPPORTED Hardware not support this feature. + **********************************************************************************************************************/ +static fsp_err_t r_crc_open_cfg_check (crc_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_cfg); + + #if !BSP_FEATURE_CRC_HAS_CRCCR0_LMS + + /* Verify the configuration bit order */ + FSP_ERROR_RETURN(CRC_BIT_ORDER_LMS_LSB == p_cfg->bit_order, FSP_ERR_UNSUPPORTED); + #endif + + /* Verify the configuration polynomial */ + FSP_ERROR_RETURN((1 << p_cfg->polynomial) & BSP_FEATURE_CRC_POLYNOMIAL_MASK, FSP_ERR_UNSUPPORTED); + + return FSP_SUCCESS; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ctsu/r_ctsu.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ctsu/r_ctsu.c new file mode 100644 index 0000000000..a66b4492c5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ctsu/r_ctsu.c @@ -0,0 +1,8115 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#ifdef QE_TOUCH_CONFIGURATION + #include "qe_touch_define.h" +#endif +#include "r_ctsu.h" +#include "r_ioport.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "CTSU" in ASCII, used to determine if device is open. */ +#define CTSU_OPEN (0x43545355U) + +/* Macro definitions for register setting */ +#define CTSU_PON_OFF (0) // CTSU hardware macro power off +#define CTSU_PON_ON (1) // CTSU hardware macro power on +#define CTSU_CSW_OFF (0) // Capacitance switch turned off +#define CTSU_CSW_ON (1) // Capacitance switch turned on + +#define CTSU_CR1_MODIFY_BIT (0xC8) // MD1, MD0, ATUNE1 +#define CTSU_SOVF (0x20) // Overflow bit +#define CTSU_CORRECTION_AVERAGE (32) +#define CTSU_SHIFT_AMOUNT (15) + +#define CTSU_PCLKB_FREQ_MHZ (1000000) +#define CTSU_PCLKB_FREQ_RANGE1 (32) +#define CTSU_PCLKB_FREQ_RANGE2 (64) +#define CTSU_PCLKB_FREQ_RANGE3 (128) +#define CTSU_WAIT_TIME (500) + +/* Macro definitions for initial offset tuning */ +#define CTSU_TUNING_MAX (0x03FF) +#define CTSU_TUNING_MIN (0x0000) +#define CTSU_TUNING_VALUE_SELF (15360) +#define CTSU_TUNING_VALUE_MUTUAL (10240) + +#define CTSU_CFG_DECIMAL_POINT (16) +#define CTSU_CFG_DECIMAL_POINT_MASK (0x0000FFFF) + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #define CTSU_SST_RECOMMEND (0x1F) // The recommend value of SST + #define CTSU_SST_RECOMMEND_CURRENT (0x3F) // The recommend value of SST with current + #define CTSU_SNUM_RECOMMEND (0x07) // The value of SNUM should be fixed + #define CTSU_SNUM_MAX (0xFF) // The maximum value of SNUM + #define CTSU_ICOMP0 (0x80) // ICOMP0 bit + #define CTSU_ICOMP1 (0x40) // ICOMP1 bit + #define CTSU_ICOMPRST (0x20) // ICOMPRST bit + #define CTSU_CR0_MODIFY_BIT (0xC0) // TXVSEL + #define CTSU_CR2_MODIFY_BIT (0x33) // POSEL, ATUNE2, MD2 + #define CTSU_SUADJ_MAX (0xFF) // The maximum value of SUADJx + #define CTSU_SUADJ_SSCNT_ADJ (0x20) // The value of Adjusting SCADJx by SSCNT + #define CTSU_MUTUAL_BUF_SIZE (CTSU_CFG_NUM_SUMULTI * 2) + +/* Macro definitions for correction */ + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CORRECTION_STD_VAL (19200) // 20UC standard value + #define CTSU_CORRECTION_STD_UNIT (1920) // 2UC value + #define CTSU_CORRECTION_STD_EXREG (14400) // External registance standard value + #define CTSU_CORRECTION_OFFSET_UNIT (120) // (7680 / 64) + #else + #define CTSU_CORRECTION_STD_VAL (15360) // 20UC standard value * 0.8 + #define CTSU_CORRECTION_STD_UNIT (1536) // 2UC value * 0.8 + #define CTSU_CORRECTION_STD_EXREG (11520) // External registance standard value + #define CTSU_CORRECTION_OFFSET_UNIT (96) // (7680 / 64) * 0.8 + #endif + #define CTSU_CORRECTION_SUMULTI (0x20) // SUMULTI step + #define CTSU_CORRECTION_TRIMB_MAX (0xFF) + #define CTSU_CORRECTION_TRIMB_SIGN_BIT (0x80) + #define CTSU_CORRECTION_RTRIM_THRESHOLD1 (0xA0) + #define CTSU_CORRECTION_RTRIM_THRESHOLD2 (0x50) + #define CTSU_CORRECTION_TRIMB_THRESHOLD1 (0xC0) + #define CTSU_CORRECTION_TRIMB_THRESHOLD2 (0x3F) + #define CTSU_CORRECTION_BIT16 (0x10000) + #define CTSU_CORRECTION_BIT10 (0x0400) + #define CTSU_CORRECTION_BIT9 (0x0200) + #define CTSU_CORRECTION_BIT8 (0x0100) + #define CTSU_CORRECTION_BIT7 (0x0080) + #define CTSU_CORRECTION_BIT6_0 (0x007F) + #define CTSU_CORRECTION_DIV_PRECISION (12) + + #if (CTSU_CFG_NUM_CFC != 0) + #define CTSU_CORRCFC_CENTER_POINT ((CTSU_CORRCFC_POINT_NUM - 1) / 2) // number of center point + #define CTSU_CORRCFC_TS_MAX (36) // Maximum number of TS terminal + #define CTSU_CORRCFC_SHIFT8 (8) // Definition of 8bit shift + #endif + + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CALIB_REF ((6144000 * 10) / CTSU_CFG_VCC_MV) // 1.5V Reference value (4096 * 1500 * 10) + #else + #define CTSU_CALIB_REF ((4915200 * 10) / CTSU_CFG_VCC_MV) // 1.2V Reference value (4096 * 1200 * 10) + #endif + #define CTSU_CALIB_AVERAGE_TIME (64) // ADC average time + #define CTSU_CALIB_THRESHOLD ((0x1000 * 4) / CTSU_CFG_VCC_MV) // RTRIM calib threshold + #define CTSU_CALIB_CTSUSO (0x3C0) // 150uA offset + #define CTSU_CALIB_ADSSTRL (0x3F) // Sampling time + #endif + +#endif +#if (BSP_FEATURE_CTSU_VERSION == 1) + #define CTSU_TXVSEL (0x80) // TXVSEL bit + #define CTSU_SST_RECOMMEND (0x10) // The value of SST should be fixed to 00010000b + #define CTSU_SNUM_MAX (0x3F) // The maximum value of SNUM + #define CTSU_SDPA_MAX (0x1F) // The maximum value of SDPA + #define CTSU_PRRATIO_RECOMMEND (3) // Recommended setting value + #define CTSU_PRMODE_62_PULSES (2) // 62 pulses (recommended setting value) + #define CTSU_SOFF_ON (0) // High-pass noise reduction function turned on + #define CTSU_SSMOD (0) // The value of SSMOD should be fixed to 00b + #define CTSU_SSCNT (3) // The value of SSCNT should be fixed to 11b + #define CTSU_RICOA_RECOMMEND (0x0F) // Recommended setting value + #define CTSU_ICOG_100 (0) // ICOG = 100% + #define CTSU_ICOG_66 (1) // ICOG = 66% + #define CTSU_ICOG_50 (2) // ICOG = 50% + #define CTSU_ICOG_40 (3) // ICOG = 40% + #define CTSU_MUTUAL_BUF_SIZE (1) + +/* Macro definitions for correction */ + #if (BSP_CFG_MCU_PART_SERIES == 2) || (BSP_CFG_MCU_PART_SERIES == 4) + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CORRECTION_1ST_STD_VAL (40960UL) // ICOG = 66% + #define CTSU_CORRECTION_2ND_STD_VAL (24824) // ICOG = 40%, (x = 40960 * 40 / 66) + #else + #define CTSU_CORRECTION_1ST_STD_VAL (32768UL) // ICOG = 66% + #define CTSU_CORRECTION_2ND_STD_VAL (19859) // ICOG = 40%, (x = 40960 * 40 / 66) + #endif + #define CTSU_WAFER_PARAMETER (0.96523525) + #define CTSU_ICOG_RECOMMEND (CTSU_ICOG_66) // Recommended setting value + #endif + #if (BSP_CFG_MCU_PART_SERIES == 6) + #define CTSU_CORRECTION_1ST_STD_VAL (27306UL) // ICOG = 66%, (x = 40960 * 66 / 100) + #define CTSU_CORRECTION_2ND_STD_VAL (16384) // ICOG = 40%, (x = 40960 * 40 / 100) + #define CTSU_WAFER_PARAMETER (1) + #define CTSU_ICOG_RECOMMEND (CTSU_ICOG_100) // Recommended setting value + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + + #define CTSU_DIAG_DAC_1UC (0x10) // 0x10 for so dac value + #define CTSU_DIAG_DAC_2UC (0x20) // 0x20 for so dac value + #define CTSU_DIAG_DAC_4UC (0x40) // 0x40 for so dac value + #define CTSU_DIAG_DAC_8UC (0x80) // 0x80 for so dac value + #define CTSU_DIAG_DAC_16UC (0x100) // 0x100 for so dac value + + #define CTSU_DIAG_DAC_SO_MAX (0x3FF) // so dac max + + #define CTSU_DIAG_DAC_INIT_VALUE (241) // SO value of dac test + #define CTSU_DIAG_DAC_TARGET_VALUE (15360) // 6UC value dac test target + #define CTSU_DIAG_DAC_START_VALUE (0x100) // so value dac test tuning + #define CTSU_DAC_TEST_ATUNE1 (0x08) // ATUNE1 bit 1 + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + #define CTSU_DIAG_ADSSTRL (0xff) // ADC scan ADSSTAL register + #define CTSU_DIAG_DAC_INIT_0 (0x0) // so dac Lower current source0 init + #define CTSU_DIAG_DAC_INIT_1 (0x100) // so dac Lower current source1 init + #define CTSU_DIAG_DAC_INIT_2 (0x200) // so dac Lower current source2 init + #define CTSU_DIAG_DAC_INIT_3 (0x300) // so dac Lower current source3 init + + #define CTSU_DIAG_DAC_DATA_MAX_0 (0x0ff) // so dac Lower current source0 max num + #define CTSU_DIAG_DAC_DATA_MAX_1 (0x1ff) // so dac Lower current source1 max num + #define CTSU_DIAG_DAC_DATA_MAX_2 (0x2ff) // so dac Lower current source2 max num + #define CTSU_DIAG_DAC_DATA_MAX_3 (0x3ff) // so dac Lower current source3 max num + + #define CTSU_DIAG_CURRENT_CLIB_REG (0x818) // current test calib register + + #define CTSU_DIAG_DELAY_MS (5) // delay time (ms) + #define CTSU_DIAG_SUCLK0_REG1 (0xff00) // cco gain test SUCLK0 + #define CTSU_DIAG_SUCLK0_REG2 (0x20) // cco gain test SUCLK0 + #define CTSU_DIAG_STCLK_FREQ (500) // stclk frequency (Hz) + #define CTSU_DIAG_LVM_MASK (0x400) // LVmode mask + #define CTSU_DIAG_CFC_SDPA_REG (0x3F) // cfc scan sdpa + #define CTSU_DIAG_CHACA_TSMAX (32) // ts max chaca byte + + #define CTSU_DIAG_DAC_0BIT (0x1) // 0x1 for SO register + #define CTSU_DIAG_DAC_1BIT (0x2) // 0x2 for SO register + #define CTSU_DIAG_DAC_2BIT (0x4) // 0x4 for SO register + #define CTSU_DIAG_DAC_3BIT (0x8) // 0x8 for SO register + #define CTSU_DIAG_DAC_4BIT (0x10) // 0x10 for SO register + #define CTSU_DIAG_DAC_5BIT (0x20) // 0x20 for SO register + #define CTSU_DIAG_DAC_6BIT (0x40) // 0x40 for SO register + #define CTSU_DIAG_DAC_7BIT (0x80) // 0x80 for SO register + + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + #define CTSU_TRANSFER_TUNING_CH_REG_MAX_NUM (32) + #endif +#endif + +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + #define CTSU_SERIAL_TUNING_ELEMENT (1) // To avoid reading outside the array in the case of mutual 1 x N configuration +#else + #define CTSU_SERIAL_TUNING_ELEMENT (0) // No additional buffer is required +#endif + +#if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + #define CTSU_AUTO_JUDGE_ELEMENT_NUM (CTSU_CFG_NUM_AUTOJUDGE_SELF_ELEMENTS + \ + CTSU_CFG_NUM_AUTOJUDGE_MUTUAL_ELEMENTS) + #define CTSU_AUTO_FINAL_JUDGE_BIT (4) // Definition for bit-shifting the final judgement bit of the automatic judgement result register + #define CTSU_AUTO_MINUS_BIT_MASK (0x0000FFFF) // Mask to assign to the CTSUAJTHR register +#endif + +#if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + #define CTSU_AUTO_DECIMAL_POINT_NUM (12) // Number of bits after the decimal point of the sensor counter auto correction table register + #define CTSU_AUTO_DECIMAL_BIT_MASK (0xFFF) // Decimal point setting for SCNTACCOEFF (b11-b0) +#endif +#if (CTSU_CFG_MULTIPLE_ELECTRODE_CONNECTION_ENABLE == 1) + #define CTSU_MEC_BIT6_MASK (0x3F) +#endif + +#if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + #define CTSU_AUTO_CURRENT_MODE_20UA (20) + #define CTSU_AUTO_CURRENT_MODE_40UA (40) + #define CTSU_AUTO_CURRENT_MODE_80UA (80) + #define CTSU_AUTO_CURRENT_MODE_160UA (160) + #define CTSU_AUTO_REF_COEFFICIENT (15) // RefFullScaleCount / OffsetDAC Resolution (15360 / 1024) + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_AUTO_CORRECTION_OFFSET_DAC_MAX (160) // OffsetDAC maximum output current [uA] + #else + #define CTSU_AUTO_CORRECTION_OFFSET_DAC_MAX (128) // 160 * 0.8 + #endif + #define CTSU_AUTO_INT32_OVERFLOW_VALUE (2147483648) + #define CTSU_AUTO_INT16_OVERFLOW_VALUE (32767) + #define CTSU_AUTO_INT16_UNDERFLOW_VALUE (-32768) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ +typedef struct st_ctsu_correction_calc +{ + ctsu_range_t range; + uint16_t snum; + uint16_t sdpa; + uint16_t cfc; + ctsu_md_t md; +} ctsu_correction_calc_t; + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) +typedef struct st_ctsu_diag_save_reg +{ + uint8_t ctsucr0; + uint8_t ctsucr1; + uint8_t ctsusdprs; + uint8_t ctsusst; + uint8_t ctsuchac0; + uint8_t ctsuchac1; + uint8_t ctsuchac2; + uint8_t ctsuchtrc0; + uint8_t ctsuchtrc1; + uint8_t ctsuchtrc2; + uint8_t ctsudclkc; + uint16_t ctsuerrs; +} ctsu_diag_save_reg_t; + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) +typedef struct st_ctsu_diag_save_reg +{ + uint32_t ctsucra; + uint32_t ctsucrb; + uint32_t ctsuchaca; + uint32_t ctsuchacb; + uint32_t ctsuchtrca; + uint32_t ctsuchtrcb; + uint32_t ctsumch; + uint32_t ctsucalib; + uint32_t ctsusuclka; + uint32_t ctsusuclkb; +} ctsu_diag_save_reg_t; + #endif +#endif + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * ctsu_prv_ns_callback)(ctsu_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile ctsu_prv_ns_callback)(ctsu_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) +static fsp_err_t ctsu_transfer_open(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_transfer_close(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_transfer_configure(ctsu_instance_ctrl_t * const p_instance_ctrl); + + #if (BSP_FEATURE_CTSU_VERSION == 2) +static fsp_err_t ctsu_transfer_normal(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_transfer_normal_ctsuwr(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_transfer_normal_ctsurd(ctsu_instance_ctrl_t * const p_instance_ctrl); + + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) +static fsp_err_t ctsu_transfer_autojudge(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_transfer_autojudge_ctsuwr(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_transfer_autojudge_ctsurd(ctsu_instance_ctrl_t * const p_instance_ctrl); +static void ctsu_transfer_autojudge_ctsuwr_value_set(transfer_info_t * p_info, + uint8_t array_number, + uint16_t set_transfer_count); +static void ctsu_transfer_autojudge_ctsuso_set(transfer_info_t * p_info, + uint8_t array_number, + uint16_t set_transfer_count); +static void ctsu_transfer_autojudge_ctsurd_value_set(transfer_info_t * p_info, + uint8_t array_number, + uint16_t set_transfer_count); +static void ctsu_transfer_autojudge_ctsuscnt_set(transfer_info_t * p_info, + uint8_t array_number, + uint16_t set_transfer_count); + + #endif + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) +static void ctsu_transfer_mcact_set(transfer_info_t * p_info, uint8_t array_number, uint16_t set_transfer_count); + + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) +static void ctsu_transer_count_element(uint32_t element_mask, uint16_t * num_element); + + #endif + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) +static fsp_err_t ctsu_transfer_ctsu1(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_transfer_ctsu1_ctsuwr(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_transfer_ctsu1_ctsurd(ctsu_instance_ctrl_t * const p_instance_ctrl); + + #endif +static void ctsu_transfer_ctsuso_set(transfer_info_t * p_info, uint8_t array_number, uint16_t set_transfer_count); +static void ctsu_transfer_ctsuscnt_set(transfer_info_t * p_info, uint8_t array_number, uint16_t set_transfer_count); +static void ctsu_transfer_address_set(transfer_info_t * p_info, + uint8_t array_number, + void * p_set_source_addr, + void * p_set_dest_addr); + +#endif +static void ctsu_initial_offset_tuning(ctsu_instance_ctrl_t * const p_instance_ctrl); +static void ctsu_moving_average(ctsu_data_t * p_average, uint16_t new_data, uint16_t average_num); +void ctsu_write_isr(void); +void ctsu_read_isr(void); +void ctsu_end_isr(void); +void ctsu_end_interrupt(ctsu_instance_ctrl_t * const p_instance_ctrl); +static void ctsu_correction_process(ctsu_instance_ctrl_t * const p_instance_ctrl); +static void ctsu_correction_measurement(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * data); + +static void ctsu_correction_exec(ctsu_instance_ctrl_t * const p_instance_ctrl); + +#if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) +static void ctsu_correction_calc(uint16_t * correction_data, uint16_t raw_data, ctsu_correction_calc_t * p_calc); + +#endif +#if (BSP_FEATURE_CTSU_VERSION == 1) +static void ctsu_correction_ctsu1_exec(ctsu_instance_ctrl_t * const p_instance_ctrl); + +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) +static void ctsu_correction_ctsu2_exec(ctsu_instance_ctrl_t * const p_instance_ctrl); + +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 0) +static void ctsu_correction_freq(uint16_t * p_corr, uint32_t * p_so_value, uint16_t * p_mfc); + + #endif +static uint8_t ctsu_correction_multi(uint16_t * p_pri_mfc, + uint16_t * p_snd_mfc, + uint16_t * p_pri_data, + uint16_t * p_snd_data); + + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) +static void ctsu_correction_scan_start(void); +static fsp_err_t ctsu_correction_data_get(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data); + + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) +static fsp_err_t ctsu_correction_calib_rtrim(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data); + + #endif + #endif + #if (CTSU_CFG_NUM_CFC != 0) +static void ctsu_corrcfc_process(ctsu_instance_ctrl_t * const p_instance_ctrl); +static void ctsu_corrcfc_measurement(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * data, uint8_t point_num); + + #endif + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) +static void ctsu_auto_correction_register_set(ctsu_instance_ctrl_t * const p_instance_ctrl); + + #endif + + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) +static void ctsu_auto_judge_threshold_calc(ctsu_instance_ctrl_t * const p_instance_ctrl); + + #endif + + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) +static void ctsu_multiclock_auto_correction_register_set(ctsu_instance_ctrl_t * const p_instance_ctrl); +static int16_t ctsu_multiclock_auto_correction_calc(ctsu_instance_ctrl_t * const p_instance_ctrl, + uint16_t element_id, + uint8_t freq); + + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) +static void ctsu_diag_dac_initial_tuning(void); + +static void ctsu_diag_ldo_over_voltage_scan_start(void); +static void ctsu_diag_oscillator_high_scan_start(void); +static void ctsu_diag_oscillator_low_scan_start(void); +static void ctsu_diag_sscg_scan_start(void); +static void ctsu_diag_dac_scan_start(ctsu_instance_ctrl_t * const p_instance_ctrl); + +static void ctsu_diag_ldo_over_voltage_data_get(void); +static void ctsu_diag_oscillator_high_data_get(void); +static void ctsu_diag_oscillator_low_data_get(void); +static void ctsu_diag_sscg_data_get(void); +static void ctsu_diag_dac_data_get(void); + +static fsp_err_t ctsu_diag_ldo_over_voltage_result(void); +static fsp_err_t ctsu_diag_oscillator_high_result(void); +static fsp_err_t ctsu_diag_oscillator_low_result(void); +static fsp_err_t ctsu_diag_sscg_result(void); +static fsp_err_t ctsu_diag_dac_result(void); + +static void ctsu_diag_scan_start1(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_diag_data_get1(void); + + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + +static void ctsu_diag_regi_store2(void); +static void ctsu_diag_regi_restore2(void); + +static fsp_err_t ctsu_diag_output_voltage_scan_start(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_diag_output_voltage_result(void); + +static void ctsu_diag_over_voltage_scan_start(void); +static fsp_err_t ctsu_diag_over_voltage_result(void); + +static void ctsu_diag_over_current_scan_start(void); +static fsp_err_t ctsu_diag_over_current_result(void); + +static void ctsu_diag_load_resistance_scan_start(void); +static void ctsu_diag_load_resistance_data_get(void); +static fsp_err_t ctsu_diag_load_resistance_result(void); + +static void ctsu_diag_current_source_scan_start(void); +static void ctsu_diag_current_source_data_get(void); +static fsp_err_t ctsu_diag_current_source_result(void); + +static void ctsu_diag_cco_gain_scan_start(void); +static void ctsu_diag_cco_gain_data_get(void); +static fsp_err_t ctsu_diag_cco_gain_result(void); + +static void ctsu_diag_clock_recovery_scan_start(void); +static void ctsu_diag_clock_recovery_data_get(void); +static fsp_err_t ctsu_diag_clock_recovery_result(void); + + #if (CTSU_CFG_NUM_CFC != 0) +static fsp_err_t ctsu_diag_cfc_gain_result(void); +static void ctsu_diag_cfc_gain_scan_start(void); +static void ctsu_diag_cfc_gain_data_get(void); + + #endif + +static fsp_err_t ctsu_diag_scan_start2(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_diag_data_get2(uint16_t * p_data); + + #endif +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static uint16_t g_ctsu_element_index = 0; +static uint8_t g_ctsu_element_complete_flag[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; +#if (BSP_FEATURE_CTSU_VERSION == 2) +static uint8_t g_ctsu_frequency_complete_flag[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; +#endif +static int32_t g_ctsu_tuning_diff[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; +static ctsu_ctsuwr_t g_ctsu_ctsuwr[(CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS + + CTSU_SERIAL_TUNING_ELEMENT) * CTSU_CFG_NUM_SUMULTI]; +#if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) +static uint16_t g_ctsu_self_element_index = 0; +static ctsu_self_buf_t g_ctsu_self_raw[CTSU_CFG_NUM_SELF_ELEMENTS * CTSU_CFG_NUM_SUMULTI]; +static uint16_t g_ctsu_self_corr[CTSU_CFG_NUM_SELF_ELEMENTS * CTSU_CFG_NUM_SUMULTI]; +static uint16_t g_ctsu_self_mfc[CTSU_CFG_NUM_SELF_ELEMENTS * CTSU_CFG_NUM_SUMULTI]; +static ctsu_data_t g_ctsu_self_data[CTSU_CFG_NUM_SELF_ELEMENTS * CTSU_MAJORITY_MODE_ELEMENTS]; +#endif +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) +static uint16_t g_ctsu_mutual_element_index = 0; +static ctsu_mutual_buf_t g_ctsu_mutual_raw[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_MUTUAL_BUF_SIZE]; +static uint16_t g_ctsu_mutual_pri_corr[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_CFG_NUM_SUMULTI]; +static uint16_t g_ctsu_mutual_snd_corr[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_CFG_NUM_SUMULTI]; +static uint16_t g_ctsu_mutual_pri_mfc[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_CFG_NUM_SUMULTI]; +static uint16_t g_ctsu_mutual_snd_mfc[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_CFG_NUM_SUMULTI]; +static ctsu_data_t g_ctsu_mutual_pri_data[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_MAJORITY_MODE_ELEMENTS]; +static ctsu_data_t g_ctsu_mutual_snd_data[CTSU_CFG_NUM_MUTUAL_ELEMENTS * CTSU_MAJORITY_MODE_ELEMENTS]; +#endif +static ctsu_correction_info_t g_ctsu_correction_info; + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) +static ctsu_diag_info_t g_ctsu_diag_info; +static ctsu_diag_save_reg_t g_ctsu_diag_reg; + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_NUM_CFC != 0) +static ctsu_corrcfc_info_t g_ctsu_corrcfc_info; + #endif + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) +static ctsu_diag_info_t g_ctsu_diag_info; +static ctsu_diag_save_reg_t g_ctsu_diag_reg; + #endif + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) +static uint32_t g_ctsu_temp_reg_ctsucra; + #endif + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) +static uint32_t g_ctsu_ajthr[CTSU_AUTO_JUDGE_ELEMENT_NUM * CTSU_MAJORITY_MODE_ELEMENTS]; +static uint32_t g_ctsu_ajmmar[CTSU_AUTO_JUDGE_ELEMENT_NUM * CTSU_MAJORITY_MODE_ELEMENTS]; +static uint32_t g_ctsu_ajblact[CTSU_AUTO_JUDGE_ELEMENT_NUM * CTSU_MAJORITY_MODE_ELEMENTS]; +static uint32_t g_ctsu_ajblar[CTSU_AUTO_JUDGE_ELEMENT_NUM * CTSU_MAJORITY_MODE_ELEMENTS]; +static uint32_t g_ctsu_ajrr[CTSU_AUTO_JUDGE_ELEMENT_NUM * CTSU_MAJORITY_MODE_ELEMENTS]; + #endif + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) +static uint32_t g_ctsu_mcact1[(CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS) * CTSU_CFG_NUM_SUMULTI]; +static uint32_t g_ctsu_mcact2[(CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS) * CTSU_CFG_NUM_SUMULTI]; + #endif + + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) +uint8_t g_ctsu_selected_freq_self[CTSU_CFG_NUM_SELF_ELEMENTS]; + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) +uint8_t g_ctsu_selected_freq_mutual[CTSU_CFG_NUM_MUTUAL_ELEMENTS]; + #endif +#endif + +static ioport_instance_ctrl_t g_ctsu_tscap_ioport_ctrl; +static ioport_pin_cfg_t g_ctsu_tscap_pin_cfg_data = +{ + .pin = (bsp_io_port_pin_t) CTSU_CFG_TSCAP_PORT, +}; +static const ioport_cfg_t g_ctsu_tscap_pin_cfg = +{ + .number_of_pins = 1, + .p_pin_cfg_data = &g_ctsu_tscap_pin_cfg_data, +}; + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) +static const uint16_t dac_oscil_table[6][2] = +{ + {CTSU_CFG_DIAG_DAC1_MAX, CTSU_CFG_DIAG_DAC1_MIN}, + {CTSU_CFG_DIAG_DAC2_MAX, CTSU_CFG_DIAG_DAC2_MIN}, + {CTSU_CFG_DIAG_DAC3_MAX, CTSU_CFG_DIAG_DAC3_MIN}, + {CTSU_CFG_DIAG_DAC4_MAX, CTSU_CFG_DIAG_DAC4_MIN}, + {CTSU_CFG_DIAG_DAC5_MAX, CTSU_CFG_DIAG_DAC5_MIN}, + {CTSU_CFG_DIAG_DAC6_MAX, CTSU_CFG_DIAG_DAC6_MIN}, +}; + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) +static const uint16_t cco_gain_table[12][2] = +{ + {CTSU_CFG_DIAG_DAC1_MIN, CTSU_CFG_DIAG_DAC1_MAX }, + {CTSU_CFG_DIAG_DAC2_MIN, CTSU_CFG_DIAG_DAC2_MAX }, + {CTSU_CFG_DIAG_DAC3_MIN, CTSU_CFG_DIAG_DAC3_MAX }, + {CTSU_CFG_DIAG_DAC4_MIN, CTSU_CFG_DIAG_DAC4_MAX }, + {CTSU_CFG_DIAG_DAC5_MIN, CTSU_CFG_DIAG_DAC5_MAX }, + {CTSU_CFG_DIAG_DAC6_MIN, CTSU_CFG_DIAG_DAC6_MAX }, + {CTSU_CFG_DIAG_DAC7_MIN, CTSU_CFG_DIAG_DAC7_MAX }, + {CTSU_CFG_DIAG_DAC8_MIN, CTSU_CFG_DIAG_DAC8_MAX }, + {CTSU_CFG_DIAG_DAC9_MIN, CTSU_CFG_DIAG_DAC9_MAX }, + {CTSU_CFG_DIAG_DAC10_MIN, CTSU_CFG_DIAG_DAC10_MAX }, + {CTSU_CFG_DIAG_DAC11_MIN, CTSU_CFG_DIAG_DAC11_MAX }, + {CTSU_CFG_DIAG_DAC12_MIN, CTSU_CFG_DIAG_DAC12_MAX }, +}; + +static const uint16_t cco_gain_diff_table[11][2] = +{ + {CTSU_CFG_DIAG_DAC1_2_DIFF_MIN, CTSU_CFG_DIAG_DAC1_2_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC2_3_DIFF_MIN, CTSU_CFG_DIAG_DAC2_3_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC3_4_DIFF_MIN, CTSU_CFG_DIAG_DAC3_4_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC4_5_DIFF_MIN, CTSU_CFG_DIAG_DAC4_5_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC5_6_DIFF_MIN, CTSU_CFG_DIAG_DAC5_6_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC6_7_DIFF_MIN, CTSU_CFG_DIAG_DAC6_7_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC7_8_DIFF_MIN, CTSU_CFG_DIAG_DAC7_8_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC8_9_DIFF_MIN, CTSU_CFG_DIAG_DAC8_9_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC9_10_DIFF_MIN, CTSU_CFG_DIAG_DAC9_10_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC10_11_DIFF_MIN, CTSU_CFG_DIAG_DAC10_11_DIFF_MAX }, + {CTSU_CFG_DIAG_DAC11_12_DIFF_MIN, CTSU_CFG_DIAG_DAC11_12_DIFF_MAX }, +}; + #endif +#endif + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +const ctsu_api_t g_ctsu_on_ctsu = +{ + .open = R_CTSU_Open, + .scanStart = R_CTSU_ScanStart, + .dataGet = R_CTSU_DataGet, + .scanStop = R_CTSU_ScanStop, + .diagnosis = R_CTSU_Diagnosis, + .close = R_CTSU_Close, + .callbackSet = R_CTSU_CallbackSet, + .specificDataGet = R_CTSU_SpecificDataGet, + .dataInsert = R_CTSU_DataInsert, + .offsetTuning = R_CTSU_OffsetTuning, + .autoJudgementDataGet = R_CTSU_AutoJudgementDataGet +}; + +/*******************************************************************************************************************//** + * @addtogroup CTSU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Opens and configures the CTSU driver module. Implements @ref ctsu_api_t::open. + * + * Example: + * @snippet r_ctsu_example.c R_CTSU_Open + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_ARGUMENT Configuration parameter error. + * + * @note + * - In the first Open, measurement for correction works, and it takes several tens of milliseconds. + * - When the touch interface configuration is diagnosis mode, execute the R_CTSU_Open() of the other touch interface configuration first. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cfg) +{ + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + uint16_t element_id; + const ctsu_element_cfg_t * element_cfgs; +#if (BSP_FEATURE_CTSU_VERSION == 2) + uint16_t i; + uint32_t pclkb_mhz; + uint16_t suadj[3]; +#endif + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_cfg); +#endif + FSP_ERROR_RETURN(CTSU_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Check element number */ +#if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_cfg->md)) + { + FSP_ERROR_RETURN(CTSU_CFG_NUM_SELF_ELEMENTS >= + (uint8_t) (g_ctsu_self_element_index + p_cfg->num_rx), + FSP_ERR_INVALID_ARGUMENT); + } +#endif +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_cfg->md)) + { + FSP_ERROR_RETURN(CTSU_CFG_NUM_MUTUAL_ELEMENTS >= + (uint8_t) (g_ctsu_mutual_element_index + (p_cfg->num_rx * p_cfg->num_tx)), + FSP_ERR_INVALID_ARGUMENT); + } +#endif + p_instance_ctrl->state = CTSU_STATE_INIT; + + /* Save configurations */ + p_instance_ctrl->p_ctsu_cfg = p_cfg; + + /* Initialize driver control structure (address setting) */ +#if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_cfg->md)) + { + p_instance_ctrl->p_self_raw = &g_ctsu_self_raw[g_ctsu_self_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->p_self_corr = &g_ctsu_self_corr[g_ctsu_self_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->p_self_mfc = &g_ctsu_self_mfc[g_ctsu_self_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->p_self_data = &g_ctsu_self_data[g_ctsu_self_element_index * CTSU_MAJORITY_MODE_ELEMENTS]; + p_instance_ctrl->num_elements = p_cfg->num_rx; + #if (BSP_FEATURE_CTSU_VERSION == 2) + p_instance_ctrl->p_selected_freq_self = &g_ctsu_selected_freq_self[g_ctsu_self_element_index]; + #endif + g_ctsu_self_element_index = (uint8_t) (g_ctsu_self_element_index + p_instance_ctrl->num_elements); + p_instance_ctrl->self_elem_index = g_ctsu_self_element_index; + + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + p_instance_ctrl->p_mutual_raw = &g_ctsu_mutual_raw[0]; + p_instance_ctrl->p_mutual_pri_corr = &g_ctsu_mutual_pri_corr[0]; + p_instance_ctrl->p_mutual_snd_corr = &g_ctsu_mutual_snd_corr[0]; + p_instance_ctrl->p_mutual_pri_mfc = &g_ctsu_mutual_pri_mfc[0]; + p_instance_ctrl->p_mutual_snd_mfc = &g_ctsu_mutual_snd_mfc[0]; + p_instance_ctrl->p_mutual_pri_data = &g_ctsu_mutual_pri_data[0]; + p_instance_ctrl->p_mutual_snd_data = &g_ctsu_mutual_snd_data[0]; + #endif + } +#endif +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_cfg->md)) + { + p_instance_ctrl->p_mutual_raw = &g_ctsu_mutual_raw[g_ctsu_mutual_element_index * CTSU_MUTUAL_BUF_SIZE]; + p_instance_ctrl->p_mutual_pri_corr = + &g_ctsu_mutual_pri_corr[g_ctsu_mutual_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->p_mutual_snd_corr = + &g_ctsu_mutual_snd_corr[g_ctsu_mutual_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->p_mutual_pri_mfc = + &g_ctsu_mutual_pri_mfc[g_ctsu_mutual_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->p_mutual_snd_mfc = + &g_ctsu_mutual_snd_mfc[g_ctsu_mutual_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->p_mutual_pri_data = + &g_ctsu_mutual_pri_data[g_ctsu_mutual_element_index * CTSU_MAJORITY_MODE_ELEMENTS]; + p_instance_ctrl->p_mutual_snd_data = + &g_ctsu_mutual_snd_data[g_ctsu_mutual_element_index * CTSU_MAJORITY_MODE_ELEMENTS]; + p_instance_ctrl->num_elements = (uint8_t) (p_cfg->num_rx * p_cfg->num_tx); + #if (BSP_FEATURE_CTSU_VERSION == 2) + p_instance_ctrl->p_selected_freq_mutual = &g_ctsu_selected_freq_mutual[g_ctsu_mutual_element_index]; + #endif + g_ctsu_mutual_element_index = (uint8_t) (g_ctsu_mutual_element_index + p_instance_ctrl->num_elements); + p_instance_ctrl->mutual_elem_index = g_ctsu_mutual_element_index; + + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + p_instance_ctrl->p_self_raw = &g_ctsu_self_raw[0]; + p_instance_ctrl->p_self_corr = &g_ctsu_self_corr[0]; + p_instance_ctrl->p_self_mfc = &g_ctsu_self_mfc[0]; + p_instance_ctrl->p_self_data = &g_ctsu_self_data[0]; + #endif + } +#endif + + p_instance_ctrl->p_element_complete_flag = &g_ctsu_element_complete_flag[g_ctsu_element_index]; +#if (BSP_FEATURE_CTSU_VERSION == 2) + p_instance_ctrl->p_frequency_complete_flag = &g_ctsu_frequency_complete_flag[g_ctsu_element_index]; +#endif + p_instance_ctrl->p_tuning_diff = &g_ctsu_tuning_diff[g_ctsu_element_index]; + p_instance_ctrl->p_ctsuwr = &g_ctsu_ctsuwr[g_ctsu_element_index * CTSU_CFG_NUM_SUMULTI]; +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + + /* Secure DTC transfer area for automatic judgement, store start address and transfer count */ + p_instance_ctrl->p_ajthr = &g_ctsu_ajthr[g_ctsu_element_index * CTSU_MAJORITY_MODE_ELEMENTS]; + p_instance_ctrl->p_ajmmar = &g_ctsu_ajmmar[g_ctsu_element_index * CTSU_MAJORITY_MODE_ELEMENTS]; + p_instance_ctrl->p_ajblact = &g_ctsu_ajblact[g_ctsu_element_index * CTSU_MAJORITY_MODE_ELEMENTS]; + p_instance_ctrl->p_ajblar = &g_ctsu_ajblar[g_ctsu_element_index * CTSU_MAJORITY_MODE_ELEMENTS]; + p_instance_ctrl->p_ajrr = &g_ctsu_ajrr[g_ctsu_element_index * CTSU_MAJORITY_MODE_ELEMENTS]; + + /* Copy to ctrl variable for setting change for automatic judgement */ + p_instance_ctrl->ajmmat = p_cfg->ajmmat; + p_instance_ctrl->ajbmat = p_cfg->ajbmat; + #endif + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + p_instance_ctrl->p_mcact1 = &g_ctsu_mcact1[g_ctsu_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->p_mcact2 = &g_ctsu_mcact2[g_ctsu_element_index * CTSU_CFG_NUM_SUMULTI]; + p_instance_ctrl->mcact_flag = 0; + #endif +#endif + g_ctsu_element_index = (uint8_t) (g_ctsu_element_index + p_instance_ctrl->num_elements); + p_instance_ctrl->ctsu_elem_index = g_ctsu_element_index; + + /* Set Value */ + p_instance_ctrl->cap = p_cfg->cap; + p_instance_ctrl->num_moving_average = p_cfg->num_moving_average; + p_instance_ctrl->average = 0; + if (true == p_cfg->tunning_enable) + { + p_instance_ctrl->tuning = CTSU_TUNING_INCOMPLETE; + } + else + { + p_instance_ctrl->tuning = CTSU_TUNING_COMPLETE; + } + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_NUM_CFC != 0) + if (CTSU_MODE_MUTUAL_CFC_SCAN == p_cfg->md) + { + p_instance_ctrl->tuning = CTSU_TUNING_COMPLETE; + } + #endif + + if (CTSU_MODE_CURRENT_SCAN == p_cfg->md) + { + p_instance_ctrl->tuning = CTSU_TUNING_COMPLETE; + } +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 1) + p_instance_ctrl->ctsucr1 = (uint8_t) (p_cfg->atune1 << 3); +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + p_instance_ctrl->ctsucr1 = (uint8_t) ((p_cfg->atune12 & 0x01) << 3); +#endif + p_instance_ctrl->ctsucr1 |= (uint8_t) (p_cfg->md << 6); + + p_instance_ctrl->txvsel = p_instance_ctrl->p_ctsu_cfg->txvsel; + p_instance_ctrl->txvsel2 = p_instance_ctrl->p_ctsu_cfg->txvsel2; + + p_instance_ctrl->ctsuchac0 = p_instance_ctrl->p_ctsu_cfg->ctsuchac0; + p_instance_ctrl->ctsuchac1 = p_instance_ctrl->p_ctsu_cfg->ctsuchac1; + p_instance_ctrl->ctsuchac2 = p_instance_ctrl->p_ctsu_cfg->ctsuchac2; + p_instance_ctrl->ctsuchac3 = p_instance_ctrl->p_ctsu_cfg->ctsuchac3; + p_instance_ctrl->ctsuchac4 = p_instance_ctrl->p_ctsu_cfg->ctsuchac4; + + p_instance_ctrl->ctsuchtrc0 = p_instance_ctrl->p_ctsu_cfg->ctsuchtrc0; + p_instance_ctrl->ctsuchtrc1 = p_instance_ctrl->p_ctsu_cfg->ctsuchtrc1; + p_instance_ctrl->ctsuchtrc2 = p_instance_ctrl->p_ctsu_cfg->ctsuchtrc2; + p_instance_ctrl->ctsuchtrc3 = p_instance_ctrl->p_ctsu_cfg->ctsuchtrc3; + p_instance_ctrl->ctsuchtrc4 = p_instance_ctrl->p_ctsu_cfg->ctsuchtrc4; + + p_instance_ctrl->md = p_instance_ctrl->p_ctsu_cfg->md; + +#if (BSP_FEATURE_CTSU_VERSION == 2) + p_instance_ctrl->ctsucr2 = (uint8_t) (p_cfg->atune12 & 0x02); + p_instance_ctrl->ctsucr2 |= (uint8_t) ((p_cfg->md & 0x04) >> 2); + p_instance_ctrl->ctsucr2 |= (uint8_t) (p_cfg->posel << 4); + + if (CTSU_ATUNE12_80UA == p_cfg->atune12) + { + p_instance_ctrl->range = CTSU_RANGE_80UA; + } + else if (CTSU_ATUNE12_40UA == p_cfg->atune12) + { + p_instance_ctrl->range = CTSU_RANGE_40UA; + } + else if (CTSU_ATUNE12_20UA == p_cfg->atune12) + { + p_instance_ctrl->range = CTSU_RANGE_20UA; + } + else if (CTSU_ATUNE12_160UA == p_cfg->atune12) + { + p_instance_ctrl->range = CTSU_RANGE_160UA; + } + else + { + } + + #if (CTSU_CFG_MULTIPLE_ELECTRODE_CONNECTION_ENABLE == 1) + + /* Copy the variables used for the MEC function to the ctrl instance */ + p_instance_ctrl->tsod = p_instance_ctrl->p_ctsu_cfg->tsod; + p_instance_ctrl->mec_ts = p_instance_ctrl->p_ctsu_cfg->mec_ts; + p_instance_ctrl->mec_shield_ts = p_instance_ctrl->p_ctsu_cfg->mec_shield_ts; + #endif +#endif + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + p_instance_ctrl->p_element_complete_flag[element_id] = 0; +#if (BSP_FEATURE_CTSU_VERSION == 2) + p_instance_ctrl->p_frequency_complete_flag[element_id] = 0; +#endif + p_instance_ctrl->p_tuning_diff[element_id] = 0; + element_cfgs = (p_cfg->p_elements + element_id); +#if (BSP_FEATURE_CTSU_VERSION == 2) + if (CTSU_MODE_CURRENT_SCAN == p_cfg->md) + { + /* Current scan does not run multiple frequency */ + p_instance_ctrl->p_ctsuwr[element_id].ctsuso = + (uint32_t) (((uint32_t) element_cfgs->sdpa << (uint32_t) 24) | + ((uint32_t) element_cfgs->snum << (uint32_t) 10) | element_cfgs->so); + } + else + { + if (CTSU_MODE_MUTUAL_CFC_SCAN != p_cfg->md) + { + p_instance_ctrl->p_ctsuwr[element_id * CTSU_CFG_NUM_SUMULTI].ctsuso = + (uint32_t) (((uint32_t) element_cfgs->sdpa << (uint32_t) 24) | + ((uint32_t) element_cfgs->snum << (uint32_t) 10) | element_cfgs->so); + } + + #if (CTSU_CFG_NUM_CFC != 0) + else + { + /* CFC scan does not use CTSUSO */ + p_instance_ctrl->p_ctsuwr[element_id * CTSU_CFG_NUM_SUMULTI].ctsuso = + (uint32_t) (((uint32_t) element_cfgs->sdpa << (uint32_t) 24) | + ((uint32_t) element_cfgs->snum << (uint32_t) 10)); + } + #endif + + for (i = 1; i < CTSU_CFG_NUM_SUMULTI; i++) + { + p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI) + i].ctsuso = + p_instance_ctrl->p_ctsuwr[element_id * CTSU_CFG_NUM_SUMULTI].ctsuso; + } + } +#endif +#if (BSP_FEATURE_CTSU_VERSION == 1) + p_instance_ctrl->p_ctsuwr[element_id].ctsussc = (uint16_t) (element_cfgs->ssdiv << 8); + p_instance_ctrl->p_ctsuwr[element_id].ctsuso0 = (uint16_t) ((element_cfgs->snum << 10) | element_cfgs->so); + p_instance_ctrl->p_ctsuwr[element_id].ctsuso1 = + (uint16_t) ((CTSU_ICOG_RECOMMEND << 13) | (element_cfgs->sdpa << 8) | CTSU_RICOA_RECOMMEND); +#endif + } + + p_instance_ctrl->write_irq = p_cfg->write_irq; + p_instance_ctrl->read_irq = p_cfg->read_irq; + p_instance_ctrl->end_irq = p_cfg->end_irq; + + /* Enable interrupts for CTSUWR, CTSURD, CTSUFN */ + R_BSP_IrqCfgEnable(p_cfg->write_irq, CTSU_CFG_INT_PRIORITY_LEVEL, p_instance_ctrl); + R_BSP_IrqCfgEnable(p_cfg->read_irq, CTSU_CFG_INT_PRIORITY_LEVEL, p_instance_ctrl); + R_BSP_IrqCfgEnable(p_cfg->end_irq, CTSU_CFG_INT_PRIORITY_LEVEL, p_instance_ctrl); + + p_instance_ctrl->interrupt_reverse_flag = 0; + + if (p_instance_ctrl->num_elements == g_ctsu_element_index) + { + /* TSCAP discharge process */ + g_ctsu_tscap_pin_cfg_data.pin_cfg = + ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW); + R_IOPORT_Open(&g_ctsu_tscap_ioport_ctrl, &g_ctsu_tscap_pin_cfg); + R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MICROSECONDS); + g_ctsu_tscap_pin_cfg_data.pin_cfg = + ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU); + R_IOPORT_PinsCfg(&g_ctsu_tscap_ioport_ctrl, &g_ctsu_tscap_pin_cfg); + R_IOPORT_Close(&g_ctsu_tscap_ioport_ctrl); + + /* Get CTSU out of stop state (supply power/clock) */ + R_BSP_MODULE_START(FSP_IP_CTSU, 0); + +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + err = ctsu_transfer_open(p_instance_ctrl); +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + R_CTSU->CTSUCRA_b.ATUNE0 = CTSU_CFG_LOW_VOLTAGE_MODE; + R_CTSU->CTSUCRA_b.PUMPON = 1; + + pclkb_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / CTSU_PCLKB_FREQ_MHZ; + + if (CTSU_PCLKB_FREQ_RANGE1 >= pclkb_mhz) + { + R_CTSU->CTSUCRA_b.CLK = 0; + R_CTSU->CTSUCR3 = (uint8_t) (pclkb_mhz - 1); + } + else if ((CTSU_PCLKB_FREQ_RANGE1 < pclkb_mhz) && (CTSU_PCLKB_FREQ_RANGE2 >= pclkb_mhz)) + { + R_CTSU->CTSUCRA_b.CLK = 1; + R_CTSU->CTSUCR3 = (uint8_t) ((pclkb_mhz >> 1) - 1); + } + else if ((CTSU_PCLKB_FREQ_RANGE2 < pclkb_mhz) && (CTSU_PCLKB_FREQ_RANGE3 >= pclkb_mhz)) + { + R_CTSU->CTSUCRA_b.CLK = 2; + R_CTSU->CTSUCR3 = (uint8_t) ((pclkb_mhz >> 2) - 1); + } + else + { + R_CTSU->CTSUCRA_b.CLK = 3; + R_CTSU->CTSUCR3 = (uint8_t) ((pclkb_mhz >> 3) - 1); + } +#endif +#if (BSP_FEATURE_CTSU_VERSION == 1) + + /* Set power on */ + R_CTSU->CTSUCR1 = ((CTSU_CFG_LOW_VOLTAGE_MODE << 2) | (CTSU_CSW_ON << 1) | CTSU_PON_ON); + + /* Synchronous Noise Reduction Setting */ + R_CTSU->CTSUSDPRS = ((CTSU_SOFF_ON << 6) | (CTSU_PRMODE_62_PULSES << 4) | CTSU_PRRATIO_RECOMMEND); + + /* High Pass Noise Reduction- ALWAYS 0x30 as per HW Manual */ + R_CTSU->CTSUDCLKC = ((CTSU_SSCNT << 4) | CTSU_SSMOD); + + /* Sensor Stabilization- ALWAYS 0x10 as per HW Manual */ + R_CTSU->CTSUSST = (CTSU_SST_RECOMMEND); + + if (CTSU_CORRECTION_INIT == g_ctsu_correction_info.status) + { + ctsu_correction_process(p_instance_ctrl); + } + + /* Since CLK is rewritten by correction, set here. */ + R_CTSU->CTSUCR1 |= (uint8_t) (CTSU_CFG_PCLK_DIVISION << 4); +#endif + } + +#if (BSP_FEATURE_CTSU_VERSION == 2) + if (CTSU_MODE_MUTUAL_CFC_SCAN != p_cfg->md) + { + /* Set power on */ + R_CTSU->CTSUCRA_b.CSW = CTSU_CSW_ON; + R_CTSU->CTSUCRA_b.PON = CTSU_PON_ON; + R_BSP_SoftwareDelay(30, BSP_DELAY_UNITS_MICROSECONDS); + } + + #if (CTSU_CFG_NUM_CFC != 0) + else + { + R_CTSU->CTSUCALIB_b.CFCRDMD = 1; + R_CTSU->CTSUCRA_b.CFCON = 1; + R_BSP_SoftwareDelay(30, BSP_DELAY_UNITS_MICROSECONDS); + } + #endif + + /* High resolution pulse mode */ + R_CTSU->CTSUCRA_b.SDPSEL = 1; + R_CTSU->CTSUCRA_b.PCSEL = 1; + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND; + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCALIB_b.SUCLKEN = 0; + + if (CTSU_MODE_MUTUAL_CFC_SCAN != p_cfg->md) + { + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + if (CTSU_MODE_CORRECTION_SCAN == p_cfg->md) + { + g_ctsu_correction_info.scan_index = CTSU_CORRECTION_POINT_NUM; + } + #endif + if (CTSU_CORRECTION_INIT == g_ctsu_correction_info.status) + { + ctsu_correction_process(p_instance_ctrl); + } + } + + #if (CTSU_CFG_NUM_CFC != 0) + else + { + ctsu_corrcfc_process(p_instance_ctrl); + } + p_instance_ctrl->p_corrcfc_info = &g_ctsu_corrcfc_info; + #endif + + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRB_b.SSCNT = 1; + R_CTSU->CTSUCALIB_b.SUCARRY = 0; + R_CTSU->CTSUCALIB_b.CCOCALIB = 0; + R_CTSU->CTSUCALIB_b.CCOCLK = 1; + R_CTSU->CTSUCALIB_b.TSOC = 0; + R_CTSU->CTSUCALIB_b.SUCLKEN = 1; + + /* Read SUADJD byte */ + suadj[0] = R_CTSUTRIM->CTSUTRIMA_b.SUADJD; + + /* Adjust multi freq */ + suadj[1] = (uint16_t) ((suadj[0] * (CTSU_CFG_SUMULTI1 + 1)) / (CTSU_CFG_SUMULTI0 + 1)); + suadj[2] = (uint16_t) ((suadj[0] * (CTSU_CFG_SUMULTI2 + 1)) / (CTSU_CFG_SUMULTI0 + 1)); + + /* Adjust SSCNT setting */ + suadj[0] = (uint16_t) (suadj[0] - (CTSU_SUADJ_SSCNT_ADJ * R_CTSU->CTSUCRB_b.SSCNT)); + suadj[1] = (uint16_t) (suadj[1] - (CTSU_SUADJ_SSCNT_ADJ * R_CTSU->CTSUCRB_b.SSCNT)); + suadj[2] = (uint16_t) (suadj[2] - (CTSU_SUADJ_SSCNT_ADJ * R_CTSU->CTSUCRB_b.SSCNT)); + + /* Set CTSUSUCLK register */ + R_CTSU->CTSUCRA_b.SDPSEL = 0; + R_CTSU->CTSUSUCLK0 = (uint16_t) (CTSU_CFG_SUMULTI0 << 8) | suadj[0]; + R_CTSU->CTSUSUCLK1 = (uint16_t) (CTSU_CFG_SUMULTI1 << 8) | suadj[1]; + R_CTSU->CTSUSUCLK2 = (uint16_t) (CTSU_CFG_SUMULTI2 << 8) | suadj[2]; + R_CTSU->CTSUCRA_b.SDPSEL = 1; + + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + /* Fixed parameter setting for automatic judgement */ + R_CTSU->CTSUAJCR_b.TLOT = p_instance_ctrl->p_ctsu_cfg->tlot; + R_CTSU->CTSUAJCR_b.THOT = p_instance_ctrl->p_ctsu_cfg->thot; + R_CTSU->CTSUAJCR_b.JC = (uint8_t) (p_instance_ctrl->p_ctsu_cfg->jc & 0x3); + + p_instance_ctrl->blini_flag = 1; + } + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + /* Initialize diagnosis information */ + p_instance_ctrl->p_diag_info = &g_ctsu_diag_info; + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + g_ctsu_diag_info.ctsuwr.ctsussc = 0; + g_ctsu_diag_info.ctsuwr.ctsuso0 = 0; + g_ctsu_diag_info.ctsuwr.ctsuso1 = 0; + g_ctsu_diag_info.loop_count = 0; + g_ctsu_diag_info.scanbuf.sen = 0; + g_ctsu_diag_info.scanbuf.ref = 0; + g_ctsu_diag_info.correct_data = 0; + g_ctsu_diag_info.icomp = 0; + g_ctsu_diag_info.cco_high = 0; + g_ctsu_diag_info.cco_low = 0; + g_ctsu_diag_info.sscg = 0; + g_ctsu_diag_info.dac_cnt[0] = 0; + g_ctsu_diag_info.dac_cnt[1] = 0; + g_ctsu_diag_info.dac_cnt[2] = 0; + g_ctsu_diag_info.dac_cnt[3] = 0; + g_ctsu_diag_info.dac_cnt[4] = 0; + g_ctsu_diag_info.dac_cnt[5] = 0; + g_ctsu_diag_info.so0_4uc_val = 0; + g_ctsu_diag_info.dac_init = 0; + g_ctsu_diag_info.tuning = CTSU_TUNING_INCOMPLETE; + g_ctsu_diag_info.tuning_diff = 0; + } + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + p_instance_ctrl->p_diag_info = &g_ctsu_diag_info; + g_ctsu_diag_info.lvmode = CTSU_CFG_LOW_VOLTAGE_MODE; + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + } + else + { + /* Once chac is set, it will not be set after that */ + if ((0 == g_ctsu_diag_info.chaca) && (0 == g_ctsu_diag_info.chacb)) + { + /* From the CHAC information configured in the normal measurement, */ + /* find the minimum TS pin on the CTSU peripheral for the OverCuurent test and clock recovery test. */ + + /* Get CHACA register info */ + ((uint8_t *) &(g_ctsu_diag_info.chaca))[0] = p_instance_ctrl->p_ctsu_cfg->ctsuchac0; + ((uint8_t *) &(g_ctsu_diag_info.chaca))[1] = p_instance_ctrl->p_ctsu_cfg->ctsuchac1; + ((uint8_t *) &(g_ctsu_diag_info.chaca))[2] = p_instance_ctrl->p_ctsu_cfg->ctsuchac2; + ((uint8_t *) &(g_ctsu_diag_info.chaca))[3] = p_instance_ctrl->p_ctsu_cfg->ctsuchac3; + + /* Get CHACB register info */ + g_ctsu_diag_info.chacb = (uint32_t) (p_instance_ctrl->p_ctsu_cfg->ctsuchac4); + + /* Get the number of measurable elements from enabled CHACA */ + if (0 != g_ctsu_diag_info.chaca) + { + /* Get the number of measurable elements from enabled CHACA */ + for (i = 0; i < CTSU_DIAG_CHACA_TSMAX; i++) + { + if ((g_ctsu_diag_info.chaca >> i) & (uint32_t) 0x00000001) + { + g_ctsu_diag_info.chaca = (uint32_t) (0x00000001 << i); + g_ctsu_diag_info.chacb = 0; + break; + } + } + } + else /* Check the measurable elements from enabled CHACB. */ + { + for (i = 0; i < 8; i++) + { + /* Get the number of measurable elements from enabled CHACB */ + if ((g_ctsu_diag_info.chacb >> i) & (uint32_t) 0x00000001) + { + g_ctsu_diag_info.chaca = 0; + g_ctsu_diag_info.chacb = (uint32_t) (0x00000001 << i); + break; + } + } + } + } + } + #endif +#endif + + p_instance_ctrl->p_correction_info = &g_ctsu_correction_info; + p_instance_ctrl->rd_index = 0; + p_instance_ctrl->wr_index = 0; + p_instance_ctrl->state = CTSU_STATE_IDLE; + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + p_instance_ctrl->serial_tuning_enable = 0; + p_instance_ctrl->serial_tuning_mutual_cnt = 0; + +#if defined(CTSU_CFG_TARGET_VALUE_QE_SUPPORT) + p_instance_ctrl->tuning_self_target_value = p_cfg->tuning_self_target_value; + p_instance_ctrl->tuning_mutual_target_value = p_cfg->tuning_mutual_target_value; +#else + p_instance_ctrl->tuning_self_target_value = CTSU_TUNING_VALUE_SELF; + p_instance_ctrl->tuning_mutual_target_value = CTSU_TUNING_VALUE_MUTUAL; +#endif + + /* Mark driver as open */ + p_instance_ctrl->open = CTSU_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * @brief This function should be called each time a periodic timer expires. + * If initial offset tuning is enabled, The first several calls are used to tuning for the sensors. + * Before starting the next scan, first get the data with R_CTSU_DataGet(). + * If a different control block scan should be run, check the scan is complete before executing. + * Implements @ref ctsu_api_t::scanStart. + * + * Example: + * @snippet r_ctsu_example.c R_CTSU_ScanStart + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CTSU_SCANNING Scanning this instance or other. + * @retval FSP_ERR_CTSU_NOT_GET_DATA The previous data has not been retrieved by DataGet. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_ScanStart (ctsu_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; + uint8_t temp; +#if (BSP_FEATURE_CTSU_VERSION == 2) + uint8_t txvsel; +#endif + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + if (CTSU_CAP_SOFTWARE == p_instance_ctrl->cap) + { + /* Can be checked if the previous measurement was a software trigger */ + if (0 == (0x02 & R_CTSU->CTSUCR0)) + { + FSP_ERROR_RETURN(0x01 != (R_CTSU->CTSUCR0 & 0x01), FSP_ERR_CTSU_SCANNING); + } + } + + FSP_ERROR_RETURN(CTSU_STATE_SCANNED != p_instance_ctrl->state, FSP_ERR_CTSU_NOT_GET_DATA); + + R_FSP_IsrContextSet(p_instance_ctrl->write_irq, p_instance_ctrl); + R_FSP_IsrContextSet(p_instance_ctrl->read_irq, p_instance_ctrl); + R_FSP_IsrContextSet(p_instance_ctrl->end_irq, p_instance_ctrl); + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + ctsu_auto_correction_register_set(p_instance_ctrl); + + /* Sensor counter auto correction enabled */ + R_CTSU->CTSUOPT_b.CCOCFEN = 1; + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + if (((1 == p_instance_ctrl->p_ctsu_cfg->ajfen) && (1 == p_instance_ctrl->p_ctsu_cfg->majirimd)) || + ((0 == p_instance_ctrl->p_ctsu_cfg->ajfen) && (0 == p_instance_ctrl->p_ctsu_cfg->majority_mode))) + { + if (0 == p_instance_ctrl->mcact_flag) + { + if (CTSU_TUNING_COMPLETE == p_instance_ctrl->tuning) + { + ctsu_multiclock_auto_correction_register_set(p_instance_ctrl); + p_instance_ctrl->mcact_flag = 1; + R_CTSU->CTSUOPT_b.MCACEFN = 1; + R_CTSU->CTSUOPT_b.MAJIRIMD = (uint8_t) (p_instance_ctrl->p_ctsu_cfg->majirimd & 0x1); + } + else + { + R_CTSU->CTSUOPT_b.MAJIRIMD = 0; + R_CTSU->CTSUOPT_b.MCACEFN = 0; + } + } + else + { + R_CTSU->CTSUOPT_b.MCACEFN = 1; + R_CTSU->CTSUOPT_b.MAJIRIMD = (uint8_t) (p_instance_ctrl->p_ctsu_cfg->majirimd & 0x1); + } + } + else + { + R_CTSU->CTSUOPT_b.MAJIRIMD = 0; + R_CTSU->CTSUOPT_b.MCACEFN = 0; + } + #endif +#endif + +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + err = ctsu_transfer_configure(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + if (CTSU_CAP_SOFTWARE == p_instance_ctrl->cap) + { + R_CTSU->CTSUCR0 &= (uint8_t) ~0x06; // specify Software trigger usage + } + else + { + R_CTSU->CTSUCR0 |= 0x06; // specify external trigger usage and enable power saving + R_CTSU->CTSUCR0 &= (uint8_t) ~0x01; // To write CTSUCR1 + } + + /* Write CTSU Control Register 1 and save mode */ +#if (BSP_FEATURE_CTSU_VERSION == 2) + if ((CTSU_MODE_CORRECTION_SCAN != p_instance_ctrl->md) && + (CTSU_MODE_DIAGNOSIS_SCAN != p_instance_ctrl->md)) + { + txvsel = + (uint8_t) ((p_instance_ctrl->txvsel2 << 6) | (p_instance_ctrl->txvsel << 7)); + temp = (uint8_t) (R_CTSU->CTSUCR0 & ~(CTSU_CR0_MODIFY_BIT)); + R_CTSU->CTSUCR0 = (uint8_t) (temp | (txvsel & CTSU_CR0_MODIFY_BIT)); // TXVSEL + temp = (uint8_t) (R_CTSU->CTSUCR1 & ~(CTSU_CR1_MODIFY_BIT)); + R_CTSU->CTSUCR1 = (uint8_t) (temp | (p_instance_ctrl->ctsucr1 & CTSU_CR1_MODIFY_BIT)); // MD1, MD0, ATUNE1 + temp = (uint8_t) (R_CTSU->CTSUCR2 & ~(CTSU_CR2_MODIFY_BIT)); + R_CTSU->CTSUCR2 = (uint8_t) (temp | (p_instance_ctrl->ctsucr2 & CTSU_CR2_MODIFY_BIT)); // POSEL, ATUNE2, MD2 + if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->md) + { + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND_CURRENT; + R_CTSU->CTSUCRA_b.DCMODE = 1; + R_CTSU->CTSUCRA_b.DCBACK = 1; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + } + else + { + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND; + R_CTSU->CTSUCRA_b.DCMODE = 0; + R_CTSU->CTSUCRA_b.DCBACK = 0; + R_CTSU->CTSUMCH_b.MCA0 = 1; + #if (CTSU_CFG_NUM_SUMULTI >= 2) + R_CTSU->CTSUMCH_b.MCA1 = 1; + #endif + #if (CTSU_CFG_NUM_SUMULTI >= 3) + R_CTSU->CTSUMCH_b.MCA2 = 1; + #endif + } + + /* Write Channel setting */ + R_CTSU->CTSUCHAC0 = p_instance_ctrl->ctsuchac0; + R_CTSU->CTSUCHAC1 = p_instance_ctrl->ctsuchac1; + R_CTSU->CTSUCHAC2 = p_instance_ctrl->ctsuchac2; + R_CTSU->CTSUCHAC3 = p_instance_ctrl->ctsuchac3; + R_CTSU->CTSUCHAC4 = p_instance_ctrl->ctsuchac4; + R_CTSU->CTSUCHTRC0 = p_instance_ctrl->ctsuchtrc0; + R_CTSU->CTSUCHTRC1 = p_instance_ctrl->ctsuchtrc1; + R_CTSU->CTSUCHTRC2 = p_instance_ctrl->ctsuchtrc2; + R_CTSU->CTSUCHTRC3 = p_instance_ctrl->ctsuchtrc3; + R_CTSU->CTSUCHTRC4 = p_instance_ctrl->ctsuchtrc4; + } + + #if (CTSU_CFG_NUM_CFC != 0) + if (CTSU_MODE_MUTUAL_CFC_SCAN == p_instance_ctrl->md) + { + R_CTSU->CTSUSR_b.CFCRDCH = 0x00; + } + #endif + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + err = ctsu_diag_scan_start2(p_instance_ctrl); + } + #endif + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + if (CTSU_MODE_CORRECTION_SCAN == p_instance_ctrl->md) + { + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND; + ctsu_correction_scan_start(); + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + + /* Disable automatic correction during temperature correction */ + R_CTSU->CTSUOPT_b.CCOCFEN = 0; + #endif + } + #endif + + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + if (CTSU_TUNING_COMPLETE == p_instance_ctrl->tuning) + { + /* Enable / disable switching of automatic judgement */ + R_CTSU->CTSUOPT_b.MTUCFEN = (uint8_t) (p_instance_ctrl->p_ctsu_cfg->mtucfen & 0x1); + R_CTSU->CTSUOPT_b.AJFEN = (uint8_t) (p_instance_ctrl->p_ctsu_cfg->ajfen & 0x1); + + if (1 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + /* Setting the number of moving averages and the number of baseline averages for automatic judgement */ + R_CTSU->CTSUAJCR_b.AJMMAT = (uint8_t) (p_instance_ctrl->ajmmat & 0xF); + R_CTSU->CTSUAJCR_b.AJBMAT = (uint8_t) (p_instance_ctrl->ajbmat & 0xF); + R_CTSU->CTSUAJCR_b.JC = (uint8_t) (p_instance_ctrl->p_ctsu_cfg->jc & 0x3); + R_CTSU->CTSUAJRR_b.TJR0 = 0; + R_CTSU->CTSUAJRR_b.TJR1 = 0; + R_CTSU->CTSUAJRR_b.TJR2 = 0; + } + } + else + { + /* If tuning incomplete, auto judgement register set OFF */ + R_CTSU->CTSUOPT_b.MTUCFEN = 0; + R_CTSU->CTSUOPT_b.AJFEN = 0; + } + + if (1 == p_instance_ctrl->blini_flag) + { + /* Set blini to 1 at the first judgement of automatic judgement */ + R_CTSU->CTSUAJCR_b.BLINI = 1; + } + #endif + + #if (CTSU_CFG_MULTIPLE_ELECTRODE_CONNECTION_ENABLE == 1) + + /* Parameter setting for multiple electrode connection */ + R_CTSU->CTSUCALIB_b.TSOD = (uint8_t) (p_instance_ctrl->tsod & 0x01); + R_CTSU->CTSUCALIB_b.IOCSEL = 0; + if (1 == p_instance_ctrl->tsod) + { + /* When using MEC, MD0 bit is set to single scan mode. */ + R_CTSU->CTSUCRA_b.MD0 = 0; + R_CTSU->CTSUMCH_b.MCH0 = (uint8_t) (p_instance_ctrl->mec_ts & CTSU_MEC_BIT6_MASK); + + /* Set MCH1 when using both MEC and Active Shield.*/ + if ((0 != p_instance_ctrl->ctsuchtrc0) || + (0 != p_instance_ctrl->ctsuchtrc1) || + (0 != p_instance_ctrl->ctsuchtrc2) || + (0 != p_instance_ctrl->ctsuchtrc3) || + (0 != p_instance_ctrl->ctsuchtrc4)) + { + R_CTSU->CTSUMCH_b.MCH1 = (uint8_t) (p_instance_ctrl->mec_shield_ts & CTSU_MEC_BIT6_MASK); + } + } + #endif + + p_instance_ctrl->state = CTSU_STATE_SCANNING; +#endif +#if (BSP_FEATURE_CTSU_VERSION == 1) + if (CTSU_MODE_DIAGNOSIS_SCAN != p_instance_ctrl->md) + { + temp = (uint8_t) (R_CTSU->CTSUCR1 & ~(CTSU_CR1_MODIFY_BIT)); + R_CTSU->CTSUCR1 = (uint8_t) (temp | (p_instance_ctrl->ctsucr1 & CTSU_CR1_MODIFY_BIT)); // MD1, MD0, ATUNE1 + + #if BSP_FEATURE_CTSU_HAS_TXVSEL + R_CTSU->CTSUCR0 = + (uint8_t) ((R_CTSU->CTSUCR0 & ~(CTSU_TXVSEL)) | (p_instance_ctrl->txvsel & CTSU_TXVSEL)); + #endif + + /* Write Channel setting */ + R_CTSU->CTSUCHAC[0] = p_instance_ctrl->ctsuchac0; + R_CTSU->CTSUCHAC[1] = p_instance_ctrl->ctsuchac1; + #if (BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT >= 3) + R_CTSU->CTSUCHAC[2] = p_instance_ctrl->ctsuchac2; + #endif + #if (BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT >= 4) + R_CTSU->CTSUCHAC[3] = p_instance_ctrl->ctsuchac3; + #endif + #if (BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT >= 5) + R_CTSU->CTSUCHAC[4] = p_instance_ctrl->ctsuchac4; + #endif + + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + R_CTSU->CTSUCHTRC[0] = p_instance_ctrl->ctsuchtrc0; + R_CTSU->CTSUCHTRC[1] = p_instance_ctrl->ctsuchtrc1; + #if (BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT >= 3) + R_CTSU->CTSUCHTRC[2] = p_instance_ctrl->ctsuchtrc2; + #endif + #if (BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT >= 4) + R_CTSU->CTSUCHTRC[3] = p_instance_ctrl->ctsuchtrc3; + #endif + #if (BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT >= 5) + R_CTSU->CTSUCHTRC[4] = p_instance_ctrl->ctsuchtrc4; + #endif + #endif + } + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + ctsu_diag_scan_start1(p_instance_ctrl); + } + #endif +#endif + + p_instance_ctrl->state = CTSU_STATE_SCANNING; + + /* Set CTSU_STRT bit to start scan */ + R_CTSU->CTSUCR0 |= 0x01; ///< CTSU_STRT + + return err; +} + +/*******************************************************************************************************************//** + * @brief This function gets the sensor values as scanned by the CTSU. + * If initial offset tuning is enabled, The first several calls are used to tuning for the sensors. + * Implements @ref ctsu_api_t::dataGet. + * + * Example: + * @snippet r_ctsu_example.c R_CTSU_DataGet + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CTSU_SCANNING Scanning this instance. + * @retval FSP_ERR_CTSU_INCOMPLETE_TUNING Incomplete initial offset tuning. + * @retval FSP_ERR_CTSU_DIAG_NOT_YET Diagnosis of data collected no yet. + * @retval FSP_ERR_INVALID_MODE The mode of automatic judgement on is invalid. + * @retval FSP_ERR_ABORTED Operate error of Diagnosis ADC data collection ,since ADC use other + **********************************************************************************************************************/ +fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data) +{ + fsp_err_t err = FSP_SUCCESS; + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; + uint16_t element_id; + uint16_t majority_mode_id; + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_data); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_ERROR_RETURN(CTSU_STATE_SCANNING != p_instance_ctrl->state, FSP_ERR_CTSU_SCANNING); + FSP_ERROR_RETURN(0 == p_instance_ctrl->p_ctsu_cfg->ajfen, FSP_ERR_INVALID_MODE); + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + if (CTSU_MODE_CORRECTION_SCAN == p_instance_ctrl->md) + { + err = ctsu_correction_data_get(p_instance_ctrl, p_data); + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + + /* Enable automatic correction after temperature correction is completed */ + R_CTSU->CTSUOPT_b.CCOCFEN = 1; + #endif + p_instance_ctrl->state = CTSU_STATE_IDLE; + + return err; + } + #endif + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + err = ctsu_diag_data_get2(p_data); + p_instance_ctrl->state = CTSU_STATE_IDLE; + if (FSP_ERR_CTSU_DIAG_NOT_YET == err) + { + err = FSP_ERR_CTSU_DIAG_NOT_YET; + } + else if (FSP_ERR_ABORTED == err) + { + err = FSP_ERR_ABORTED; + } + else + { + err = FSP_SUCCESS; + } + + return err; + } + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + err = ctsu_diag_data_get1(); + p_instance_ctrl->state = CTSU_STATE_IDLE; + if (FSP_ERR_CTSU_DIAG_NOT_YET == err) + { + err = FSP_ERR_CTSU_DIAG_NOT_YET; + } + else + { + err = FSP_SUCCESS; + } + + return err; + } + #endif +#endif + + if (CTSU_STATE_SCANNED == p_instance_ctrl->state) + { + if (CTSU_TUNING_COMPLETE == p_instance_ctrl->tuning) + { + if (p_instance_ctrl->average == p_instance_ctrl->num_moving_average) + { + /* Do nothing */ + } + else if (p_instance_ctrl->average < p_instance_ctrl->num_moving_average) + { + (p_instance_ctrl->average)++; + } + else + { + p_instance_ctrl->average = p_instance_ctrl->num_moving_average; + } + } + + ctsu_correction_exec(p_instance_ctrl); + + if (CTSU_TUNING_INCOMPLETE == p_instance_ctrl->tuning) + { + if ((CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) || + (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md)) + { + ctsu_initial_offset_tuning(p_instance_ctrl); + } + } + + p_instance_ctrl->state = CTSU_STATE_IDLE; + } + + FSP_ERROR_RETURN(0 < p_instance_ctrl->average, FSP_ERR_CTSU_INCOMPLETE_TUNING); + +#if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + for (majority_mode_id = 0; majority_mode_id < CTSU_MAJORITY_MODE_ELEMENTS; majority_mode_id++) + { + *p_data = + (p_instance_ctrl->p_self_data + element_id * CTSU_MAJORITY_MODE_ELEMENTS + + majority_mode_id)->int_data; + p_data++; + } + } + } +#endif +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + /* Serial Tuning Phase1 */ + if ((0 == p_instance_ctrl->ctsuchtrc0) && (0 == p_instance_ctrl->ctsuchtrc1) && + (0 == p_instance_ctrl->ctsuchtrc2) && (0 == p_instance_ctrl->ctsuchtrc3) && + (0 == p_instance_ctrl->ctsuchtrc4)) + { + return FSP_SUCCESS; + } + } + + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + for (majority_mode_id = 0; majority_mode_id < CTSU_MAJORITY_MODE_ELEMENTS; majority_mode_id++) + { + *p_data = + (p_instance_ctrl->p_mutual_pri_data + element_id * CTSU_MAJORITY_MODE_ELEMENTS + + majority_mode_id)->int_data; + p_data++; + *p_data = + (p_instance_ctrl->p_mutual_snd_data + element_id * CTSU_MAJORITY_MODE_ELEMENTS + + majority_mode_id)->int_data; + p_data++; + } + } + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * @brief This function gets the result of automatic judgement button. Call after the scan is completed. + * The result is 64-bit bitmaps and is stored in order of TS number for specified ctsu control. + * After the initial judgement, the baseline initialization bit is set and the automatic judgement threshold is set. + * This function is called only for automatic judgement. + * Implements @ref ctsu_api_t::autoJudgementDataGet. + * + * Example: + * @snippet r_ctsu_example.c R_CTSU_AutoJudgementDataGet + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CTSU_SCANNING Scanning this instance. + * @retval FSP_ERR_INVALID_MODE The mode of automatic judgement off is invalid. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_AutoJudgementDataGet (ctsu_ctrl_t * const p_ctrl, uint64_t * p_button_status) +{ + fsp_err_t err = FSP_SUCCESS; + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + uint16_t element_id; + #endif +#endif + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_button_status); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_ERROR_RETURN(CTSU_STATE_SCANNING != p_instance_ctrl->state, FSP_ERR_CTSU_SCANNING); + FSP_ERROR_RETURN(1 == p_instance_ctrl->p_ctsu_cfg->ajfen, FSP_ERR_INVALID_MODE); + +#if ((BSP_FEATURE_CTSU_VERSION == 2) && (CTSU_CFG_AUTO_JUDGE_ENABLE == 1)) + if (1 == p_instance_ctrl->blini_flag) + { + p_instance_ctrl->blini_flag = 0; + + /* After the initial judgement of automatic judgement, set the baseline initialization bit to 0. */ + R_CTSU->CTSUAJCR_b.BLINI = 0; + + ctsu_auto_judge_threshold_calc(p_instance_ctrl); + } + + if (CTSU_STATE_SCANNED == p_instance_ctrl->state) + { + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->majirimd) + { + /* Reflect the final result bit of automatic judgement in buttun_status */ + if (1 == (((p_instance_ctrl->p_ajrr[element_id]) >> CTSU_AUTO_FINAL_JUDGE_BIT) & 0x1)) + { + *p_button_status |= ((uint64_t) 1 << element_id); + } + else + { + *p_button_status &= ~((uint64_t) 1 << element_id); + } + } + else + #endif + { + /* Reflect the final result bit of automatic judgement in buttun_status */ + /* Since the final result of the automatic judgement is output to the FJR bit of the final multi-clock, */ + /* the result of the final multi-clock is taken out. */ + if (1 == + (((p_instance_ctrl->p_ajrr[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + + (CTSU_MAJORITY_MODE_ELEMENTS - 1)]) >> CTSU_AUTO_FINAL_JUDGE_BIT) & 0x1)) + { + *p_button_status |= ((uint64_t) 1 << element_id); + } + else + { + *p_button_status &= ~((uint64_t) 1 << element_id); + } + } + } + + p_instance_ctrl->state = CTSU_STATE_IDLE; + } + +#else + FSP_PARAMETER_NOT_USED(p_button_status); +#endif + + return err; +} + +/*******************************************************************************************************************//** + * @brief This function tunes the offset register(SO). Call after the measurement is completed. + * If the return value is FSP_ERR_CTSU_INCOMPLETE_TUNING, tuning is not complete. + * Execute the measurement and this function call routine until the return value becomes FSP_SUCCESS. + * It is recommended to run this routine after R_CTSU_Open(). + * It can be recalled and tuned again. + * When the automatic judgement is enabled, after the offset tuning is completed,the baseline initialization bit flag is set. + * Implements @ref ctsu_api_t::offsetTuning. + * + * Example: + * @snippet r_ctsu_example.c R_CTSU_OffsetTuning + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CTSU_SCANNING Scanning this instance. + * @retval FSP_ERR_CTSU_INCOMPLETE_TUNING Incomplete initial offset tuning. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_OffsetTuning (ctsu_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; + uint16_t element_id; +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + uint16_t i; + #endif +#endif + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_ERROR_RETURN(CTSU_STATE_SCANNING != p_instance_ctrl->state, FSP_ERR_CTSU_SCANNING); + + if (CTSU_TUNING_COMPLETE == p_instance_ctrl->tuning) + { + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + /* Counter clear for re-offset tuning */ + *(p_instance_ctrl->p_element_complete_flag + element_id) = 0; +#if (BSP_FEATURE_CTSU_VERSION == 2) + *(p_instance_ctrl->p_frequency_complete_flag + element_id) = 0; +#endif + *(p_instance_ctrl->p_tuning_diff + element_id) = 0; + } + } + + p_instance_ctrl->tuning = CTSU_TUNING_INCOMPLETE; + + if (CTSU_STATE_SCANNED == p_instance_ctrl->state) + { + if (0 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + ctsu_correction_exec(p_instance_ctrl); + } + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + else + { + R_CTSU->CTSUOPT_b.AJFEN = 0; + R_CTSU->CTSUOPT_b.MTUCFEN = 0; + + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + p_instance_ctrl->p_self_corr[(element_id * CTSU_CFG_NUM_SUMULTI) + + i] = + p_instance_ctrl->p_self_raw[(element_id * CTSU_CFG_NUM_SUMULTI) + i]; + } + + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + else + { + p_instance_ctrl->p_mutual_pri_corr[(element_id * CTSU_CFG_NUM_SUMULTI) + + i] = + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2)]; + } + #endif + #if (CTSU_CFG_MAJORITY_MODE & CTSU_JUDGEMENT_MAJORITY_MODE) + + /* Initial value setting of DTC transfer information for automatic judgement */ + p_instance_ctrl->p_ajthr[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + i] = 0; + p_instance_ctrl->p_ajmmar[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + i] = 0; + p_instance_ctrl->p_ajblact[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + i] = 0; + p_instance_ctrl->p_ajblar[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + i] = 0; + p_instance_ctrl->p_ajrr[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + i] = 0; + #endif + } + + #if ((CTSU_CFG_MAJORITY_MODE & CTSU_JUDGEMENT_MAJORITY_MODE) == 0) + p_instance_ctrl->p_ajthr[element_id] = 0; + p_instance_ctrl->p_ajmmar[element_id] = 0; + p_instance_ctrl->p_ajblact[element_id] = 0; + p_instance_ctrl->p_ajblar[element_id] = 0; + p_instance_ctrl->p_ajrr[element_id] = 0; + #endif + } + } + #endif +#endif + + if (CTSU_TUNING_INCOMPLETE == p_instance_ctrl->tuning) + { + if ((CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) || + (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md)) + { + ctsu_initial_offset_tuning(p_instance_ctrl); + } + } + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + if (CTSU_TUNING_COMPLETE == p_instance_ctrl->tuning) + { + /* Initialization of baseline mean for automatic judgement */ + p_instance_ctrl->blini_flag = 1; + } + } + #endif + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + p_instance_ctrl->mcact_flag = 0; + #endif +#endif + p_instance_ctrl->state = CTSU_STATE_IDLE; + } + + FSP_ERROR_RETURN(CTSU_TUNING_COMPLETE == p_instance_ctrl->tuning, FSP_ERR_CTSU_INCOMPLETE_TUNING); + + return err; +} + +/*******************************************************************************************************************//** + * @brief This function scan stops the sensor as scanning by the CTSU. + * Implements @ref ctsu_api_t::scanStop. + * @retval FSP_SUCCESS CTSU successfully scan stop. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_ScanStop (ctsu_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; +#if (CTSU_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + if (CTSU_STATE_SCANNING == p_instance_ctrl->state) + { +#if (BSP_FEATURE_CTSU_VERSION == 2) + R_CTSU->CTSUCRA ^= 0x11; +#else + R_CTSU->CTSUCR0 ^= 0x11; +#endif + +#if (BSP_FEATURE_ICU_HAS_IELSR) + R_BSP_IrqStatusClear(p_instance_ctrl->p_ctsu_cfg->write_irq); + R_BSP_IrqStatusClear(p_instance_ctrl->p_ctsu_cfg->read_irq); + R_BSP_IrqStatusClear(p_instance_ctrl->p_ctsu_cfg->end_irq); +#endif + p_instance_ctrl->state = CTSU_STATE_IDLE; + p_instance_ctrl->wr_index = 0; + p_instance_ctrl->rd_index = 0; + } + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements ctsu_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_CallbackSet (ctsu_ctrl_t * const p_api_ctrl, + void ( * p_callback)(ctsu_callback_args_t *), + void * const p_context, + ctsu_callback_args_t * const p_callback_memory) +{ + ctsu_instance_ctrl_t * p_ctrl = (ctsu_instance_ctrl_t *) p_api_ctrl; + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CTSU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CTSU_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + ctsu_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(ctsu_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Disables specified CTSU control block. Implements @ref ctsu_api_t::close. + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_Close (ctsu_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + g_ctsu_element_index = (uint8_t) (g_ctsu_element_index - p_instance_ctrl->num_elements); +#if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + g_ctsu_self_element_index = (uint8_t) (g_ctsu_self_element_index - p_instance_ctrl->num_elements); + } +#endif +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + g_ctsu_mutual_element_index = (uint8_t) (g_ctsu_mutual_element_index - p_instance_ctrl->num_elements); + } +#endif + if (0 == g_ctsu_element_index) + { +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + err = ctsu_transfer_close(p_instance_ctrl); +#endif + } + + p_instance_ctrl->state = CTSU_STATE_INIT; + p_instance_ctrl->open = false; + + return err; +} + +/*******************************************************************************************************************//** + * @brief This function gets the sensor specific data values as scanned by the CTSU. + * Call this function after calling the R_CTSU_DataGet() function. + * + * By setting the third argument to CTSU_SPECIFIC_RAW_DATA, + * RAW data can be output from the second argument. + * + * By setting the third argument to CTSU_SPECIFIC_CCO_CORRECTION_DATA, + * the cco corrected data can be output from the second argument. + * + * By setting the third argument to CTSU_SPECIFIC_CORRECTION_DATA, + * the frequency corrected data can be output from the second argument. + * + * By setting the third argument to CTSU_SPECIFIC_SELECTED_FREQ, + * Get bitmap of the frequency values used in majority decision from the second argument.(CTSU2 Only) + * The bitmap is shown as follows. + * + * | 2bit | 1bit | 0bit | + * |---------------------|---------------------|---------------------| + * | 3rd frequency value | 2nd frequency value | 1st frequency value | + * + * Implements @ref ctsu_api_t::specificDataGet. + * + * Example: + * @snippet r_ctsu_example.c R_CTSU_SpecificDataGet + * + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CTSU_SCANNING Scanning this instance. + * @retval FSP_ERR_CTSU_INCOMPLETE_TUNING Incomplete initial offset tuning. + * @retval FSP_ERR_NOT_ENABLED CTSU_SPECIFIC_SELECTED_FREQ is not enabled in CTSU1.(CTSU2 Only) + **********************************************************************************************************************/ +fsp_err_t R_CTSU_SpecificDataGet (ctsu_ctrl_t * const p_ctrl, + uint16_t * p_specific_data, + ctsu_specific_data_type_t specific_data_type) +{ + fsp_err_t err = FSP_SUCCESS; + uint16_t element_id; + uint16_t i; + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_specific_data); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_ERROR_RETURN(CTSU_STATE_SCANNING != p_instance_ctrl->state, FSP_ERR_CTSU_SCANNING); + FSP_ERROR_RETURN(CTSU_TUNING_INCOMPLETE != p_instance_ctrl->tuning, FSP_ERR_CTSU_INCOMPLETE_TUNING); + +#if (BSP_FEATURE_CTSU_VERSION == 1) + FSP_ERROR_RETURN(CTSU_SPECIFIC_SELECTED_FREQ != specific_data_type, FSP_ERR_NOT_ENABLED); +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_MAJORITY_MODE & CTSU_JUDGEMENT_MAJORITY_MODE) + FSP_ERROR_RETURN(CTSU_SPECIFIC_SELECTED_FREQ != specific_data_type, FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(CTSU_SPECIFIC_CORRECTION_DATA != specific_data_type, FSP_ERR_NOT_ENABLED); + #endif + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + FSP_ERROR_RETURN(CTSU_SPECIFIC_RAW_DATA != specific_data_type, FSP_ERR_NOT_ENABLED); + #endif + + #if (CTSU_CFG_MAJORITY_MODE & (CTSU_JUDGEMENT_MAJORITY_MODE | CTSU_VALUE_MAJORITY_MODE)) + if (p_instance_ctrl->p_ctsu_cfg->majority_mode == 1) + { + FSP_ERROR_RETURN(CTSU_SPECIFIC_CORRECTION_DATA != specific_data_type, FSP_ERR_NOT_ENABLED); + } + #endif + + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + if (1 == p_instance_ctrl->p_ctsu_cfg->majirimd) + { + FSP_ERROR_RETURN(CTSU_SPECIFIC_CCO_CORRECTION_DATA != specific_data_type, FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(CTSU_SPECIFIC_CORRECTION_DATA != specific_data_type, FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(CTSU_SPECIFIC_SELECTED_FREQ != specific_data_type, FSP_ERR_NOT_ENABLED); + } + } + else + { + if (0 == p_instance_ctrl->p_ctsu_cfg->majority_mode) + { + FSP_ERROR_RETURN(CTSU_SPECIFIC_CCO_CORRECTION_DATA != specific_data_type, FSP_ERR_NOT_ENABLED); + } + } + #endif + + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + if (0 == p_instance_ctrl->p_ctsu_cfg->majirimd) + { + FSP_ERROR_RETURN(CTSU_SPECIFIC_CORRECTION_DATA != specific_data_type, FSP_ERR_NOT_ENABLED); + FSP_ERROR_RETURN(CTSU_SPECIFIC_SELECTED_FREQ != specific_data_type, FSP_ERR_NOT_ENABLED); + } + } + #endif +#endif + + if (CTSU_SPECIFIC_RAW_DATA == specific_data_type) + { +#if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + #if (BSP_FEATURE_CTSU_VERSION == 1) + *p_specific_data = (p_instance_ctrl->p_self_raw + element_id)->sen; + p_specific_data++; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 2) + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + *p_specific_data = *(p_instance_ctrl->p_self_raw + (element_id * CTSU_CFG_NUM_SUMULTI) + i); + p_specific_data++; + } + #endif + } + } +#endif +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + #if (BSP_FEATURE_CTSU_VERSION == 1) + *p_specific_data = (p_instance_ctrl->p_mutual_raw + element_id)->pri_sen; + p_specific_data++; + *p_specific_data = (p_instance_ctrl->p_mutual_raw + element_id)->snd_sen; + p_specific_data++; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 2) + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + *p_specific_data = + *(p_instance_ctrl->p_mutual_raw + (element_id * CTSU_CFG_NUM_SUMULTI * 2) + (i * 2)); + p_specific_data++; + *p_specific_data = + *(p_instance_ctrl->p_mutual_raw + (element_id * CTSU_CFG_NUM_SUMULTI * 2) + (i * 2) + 1); + p_specific_data++; + } + #endif + } + } +#endif + } + else if (CTSU_SPECIFIC_CCO_CORRECTION_DATA == specific_data_type) + { +#if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + for (element_id = 0; element_id < (p_instance_ctrl->num_elements); element_id++) + { + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + #if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + *p_specific_data = + *(p_instance_ctrl->p_self_raw + (element_id * CTSU_CFG_NUM_SUMULTI) + i); + p_specific_data++; + } + else + #endif + #endif + { + *p_specific_data = + *(p_instance_ctrl->p_self_corr + (element_id * CTSU_CFG_NUM_SUMULTI) + i); + p_specific_data++; + } + } + } + } +#endif +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + for (element_id = 0; element_id < (p_instance_ctrl->num_elements); element_id++) + { + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + #if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + *p_specific_data = + *(p_instance_ctrl->p_mutual_raw + + ((element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2))); + p_specific_data++; + *p_specific_data = + *(p_instance_ctrl->p_mutual_raw + + ((element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2) + 1)); + p_specific_data++; + } + else + #endif + #endif + { + *p_specific_data = + *(p_instance_ctrl->p_mutual_pri_corr + (element_id * CTSU_CFG_NUM_SUMULTI) + + i); + p_specific_data++; + *p_specific_data = + *(p_instance_ctrl->p_mutual_snd_corr + (element_id * CTSU_CFG_NUM_SUMULTI) + + i); + p_specific_data++; + } + } + } + } +#endif + } + +#if (BSP_FEATURE_CTSU_VERSION == 2) + else if (CTSU_SPECIFIC_CORRECTION_DATA == specific_data_type) + { + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + for (element_id = 0; element_id < (p_instance_ctrl->num_elements); element_id++) + { + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + *p_specific_data = *(p_instance_ctrl->p_self_mfc + (element_id * CTSU_CFG_NUM_SUMULTI) + i); + p_specific_data++; + } + } + } + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + for (element_id = 0; element_id < (p_instance_ctrl->num_elements); element_id++) + { + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + *p_specific_data = *(p_instance_ctrl->p_mutual_pri_mfc + (element_id * CTSU_CFG_NUM_SUMULTI) + i); + p_specific_data++; + *p_specific_data = *(p_instance_ctrl->p_mutual_snd_mfc + (element_id * CTSU_CFG_NUM_SUMULTI) + i); + p_specific_data++; + } + } + } + #endif + } + else if (CTSU_SPECIFIC_SELECTED_FREQ == specific_data_type) + { + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + for (element_id = 0; element_id < (p_instance_ctrl->num_elements); element_id++) + { + *p_specific_data = *(p_instance_ctrl->p_selected_freq_self + element_id); + p_specific_data++; + } + } + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + for (element_id = 0; element_id < (p_instance_ctrl->num_elements); element_id++) + { + *p_specific_data = *(p_instance_ctrl->p_selected_freq_mutual + element_id); + p_specific_data++; + } + } + #endif + } +#endif + else + { + } + + return err; +} + +/*******************************************************************************************************************//** + * @brief This function inserts the value of the second argument as the measurement result value. + * Call this function after calling the R_CTSU_DataInsert() function. + * Implements @ref ctsu_api_t::dataInsert. + * + * Example: + * @snippet r_ctsu_example.c R_CTSU_DataInsert + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CTSU_SCANNING Scanning this instance. + * @retval FSP_ERR_CTSU_INCOMPLETE_TUNING Incomplete initial offset tuning. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_DataInsert (ctsu_ctrl_t * const p_ctrl, uint16_t * p_insert_data) +{ + fsp_err_t err = FSP_SUCCESS; + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; + uint16_t element_id; + uint16_t majority_mode_elem_id; +#if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_insert_data); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_ERROR_RETURN(CTSU_STATE_SCANNING != p_instance_ctrl->state, FSP_ERR_CTSU_SCANNING); + FSP_ERROR_RETURN(CTSU_TUNING_INCOMPLETE != p_instance_ctrl->tuning, FSP_ERR_CTSU_INCOMPLETE_TUNING); + +#if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + /* Data output */ + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + for (majority_mode_elem_id = 0; + majority_mode_elem_id < CTSU_MAJORITY_MODE_ELEMENTS; + majority_mode_elem_id++) + { + (p_instance_ctrl->p_self_data + (element_id * CTSU_MAJORITY_MODE_ELEMENTS) + + majority_mode_elem_id)->int_data = *p_insert_data; + p_insert_data++; + } + } + } +#endif +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + for (majority_mode_elem_id = 0; + majority_mode_elem_id < CTSU_MAJORITY_MODE_ELEMENTS; + majority_mode_elem_id++) + { + (p_instance_ctrl->p_mutual_pri_data + (element_id * CTSU_MAJORITY_MODE_ELEMENTS) + + majority_mode_elem_id)->int_data = *p_insert_data; + p_insert_data++; + (p_instance_ctrl->p_mutual_snd_data + (element_id * CTSU_MAJORITY_MODE_ELEMENTS) + + majority_mode_elem_id)->int_data = *p_insert_data; + p_insert_data++; + } + } + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup CTSU) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Internal ctsu private function. + **********************************************************************************************************************/ + +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_transfer_open + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_open (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + transfer_instance_t const * p_transfer; + transfer_cfg_t cfg; + transfer_info_t * p_info_bk; + + /* CTSUWR setting */ + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_tx; + cfg = *(p_transfer->p_cfg); + p_info_bk = cfg.p_info; + cfg.p_info = NULL; + + err = p_transfer->p_api->open(p_transfer->p_ctrl, &cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + cfg.p_info = p_info_bk; + + /* CTSURD setting */ + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_rx; + cfg = *(p_transfer->p_cfg); + p_info_bk = cfg.p_info; + cfg.p_info = NULL; + + err = p_transfer->p_api->open(p_transfer->p_ctrl, &cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + cfg.p_info = p_info_bk; + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * ctsu_transfer_close + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_close (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + transfer_instance_t const * p_transfer; + + /* CTSUWR setting */ + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_tx; + err = p_transfer->p_api->close(p_transfer->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* CTSURD setting */ + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_rx; + err = p_transfer->p_api->close(p_transfer->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * ctsu_transfer_configure + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_configure (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + + #if (BSP_FEATURE_CTSU_VERSION == 2) + + /* After the initial offset tuning is completed, set the DTC for automatic judgement. */ + /* In addition, the method for which automatic judgement is disabled does not set the DTC for automatic judgement. */ + /* Alternatively, DTC for automatic judgment will not be set during correction measurement. */ + if ((0 == p_instance_ctrl->p_ctsu_cfg->ajfen) || (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) || + (CTSU_TUNING_INCOMPLETE == p_instance_ctrl->tuning)) + { + err = ctsu_transfer_normal(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + else + { + err = ctsu_transfer_autojudge(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + #endif + + #if (BSP_FEATURE_CTSU_VERSION == 1) + err = ctsu_transfer_ctsu1(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + return FSP_SUCCESS; +} + + #if (BSP_FEATURE_CTSU_VERSION == 2) + +/*********************************************************************************************************************** + * ctsu_transfer_normal + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_normal (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + + err = ctsu_transfer_normal_ctsuwr(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = ctsu_transfer_normal_ctsurd(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * ctsu_transfer_normal_ctsuwr + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_normal_ctsuwr (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + transfer_instance_t const * p_transfer; + transfer_info_t * p_info; + uint16_t calc_transfer_count; + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + uint16_t transfer_mutual_num_elements = 0; + #endif + + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_tx; + p_info = p_transfer->p_cfg->p_info; + + calc_transfer_count = p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI; + + ctsu_transfer_ctsuso_set(p_info, 0, calc_transfer_count); + ctsu_transfer_address_set(p_info, 0, p_instance_ctrl->p_ctsuwr, (void *) &R_CTSU->CTSUSO); + + if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) + { + p_info[0].num_blocks = 1; + p_info[0].p_src = (void *) &(g_ctsu_correction_info.ctsuwr); + } + + #if (CTSU_CFG_NUM_CFC != 0) + else if (CTSU_CORRECTION_RUN == g_ctsu_corrcfc_info.status) + { + p_info[0].num_blocks = 1; + p_info[0].p_src = (void *) &(g_ctsu_corrcfc_info.ctsuwr); + } + #endif + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + else if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + if (CTSU_DIAG_CLOCK_RECOVERY == g_ctsu_diag_info.state) + { + p_info[0].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info[0].num_blocks = 3; + } + else if ((CTSU_DIAG_INIT == g_ctsu_diag_info.state) || (CTSU_DIAG_OUTPUT_VOLTAGE == g_ctsu_diag_info.state) || + (CTSU_DIAG_OVER_VOLTAGE == g_ctsu_diag_info.state) || + (CTSU_DIAG_OVER_CURRENT == g_ctsu_diag_info.state)) + { + p_info[0].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info[0].num_blocks = 2; + } + else + { + p_info[0].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info[0].num_blocks = 1; + } + + p_info[0].p_src = (void *) &(g_ctsu_diag_info.ctsuwr); + } + #endif + else + { + if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->md) + { + p_info[0].num_blocks = p_instance_ctrl->num_elements; + } + else + { + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + if (0 == ((p_instance_ctrl->ctsucr1 >> 7) & 0x01)) + { + ctsu_transer_count_element(p_instance_ctrl->ctsuchac0, &transfer_mutual_num_elements); + ctsu_transer_count_element(p_instance_ctrl->ctsuchac1, &transfer_mutual_num_elements); + ctsu_transer_count_element(p_instance_ctrl->ctsuchac2, &transfer_mutual_num_elements); + ctsu_transer_count_element(p_instance_ctrl->ctsuchac3, &transfer_mutual_num_elements); + ctsu_transer_count_element(p_instance_ctrl->ctsuchac4, &transfer_mutual_num_elements); + + p_info[0].num_blocks = transfer_mutual_num_elements * CTSU_CFG_NUM_SUMULTI; + } + } + } + #endif + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + if ((0 == p_instance_ctrl->p_ctsu_cfg->majority_mode) && + (CTSU_TUNING_INCOMPLETE != p_instance_ctrl->tuning)) + { + ctsu_transfer_mcact_set(p_info, 0, calc_transfer_count); + ctsu_transfer_address_set(p_info, 0, p_instance_ctrl->p_mcact1, (void *) &R_CTSU->CTSUMACT1); + + ctsu_transfer_ctsuso_set(p_info, 1, calc_transfer_count); + ctsu_transfer_address_set(p_info, 1, p_instance_ctrl->p_ctsuwr, (void *) &R_CTSU->CTSUSO); + + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + if (0 == ((p_instance_ctrl->ctsucr1 >> 7) & 0x01)) + { + p_info[0].num_blocks = transfer_mutual_num_elements * CTSU_CFG_NUM_SUMULTI; + p_info[1].num_blocks = transfer_mutual_num_elements * CTSU_CFG_NUM_SUMULTI; + } + } + } + #endif + } + #endif + } + } + + err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * ctsu_transfer_normal_ctsurd + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_normal_ctsurd (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + transfer_instance_t const * p_transfer; + transfer_info_t * p_info; + uint16_t calc_transfer_count; + + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_rx; + p_info = p_transfer->p_cfg->p_info; + + calc_transfer_count = p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI; + + ctsu_transfer_ctsuscnt_set(p_info, 0, calc_transfer_count); + ctsu_transfer_address_set(p_info, 0, (void *) &R_CTSU->CTSUSC, p_instance_ctrl->p_self_raw); + + if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) + { + p_info[0].transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + p_info[0].num_blocks = 1; + p_info[0].p_dest = (void *) &g_ctsu_correction_info.scanbuf; + p_info[0].p_src = (void *) &R_CTSU->CTSUSC; + } + + #if (CTSU_CFG_NUM_CFC != 0) + else if (CTSU_CORRECTION_RUN == g_ctsu_corrcfc_info.status) + { + p_info[0].transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + p_info[0].length = g_ctsu_corrcfc_info.num_ts; + p_info[0].num_blocks = 1; + p_info[0].p_dest = (void *) g_ctsu_corrcfc_info.scanbuf; + p_info[0].p_src = (void *) &R_CTSU->CTSUCFCCNT; + } + #endif + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + else if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + p_info->transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + if (CTSU_DIAG_CLOCK_RECOVERY == g_ctsu_diag_info.state) + { + p_info[0].num_blocks = 3; + } + else if ((CTSU_DIAG_INIT == g_ctsu_diag_info.state) || (CTSU_DIAG_OUTPUT_VOLTAGE == g_ctsu_diag_info.state) || + (CTSU_DIAG_OVER_VOLTAGE == g_ctsu_diag_info.state) || + (CTSU_DIAG_OVER_CURRENT == g_ctsu_diag_info.state)) + { + p_info[0].num_blocks = 2; + } + else + { + p_info[0].num_blocks = 1; + } + + p_info[0].p_dest = (void *) &g_ctsu_diag_info.ctsuscnt; + if (CTSU_DIAG_CFC == g_ctsu_diag_info.state) + { + p_info[0].p_src = (void *) &R_CTSU->CTSUCFCCNT; + } + else + { + p_info[0].p_src = (void *) &R_CTSU->CTSUSCNT; + } + } + #endif + else + { + if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->md) + { + p_info[0].num_blocks = p_instance_ctrl->num_elements; + } + else + { + p_info[0].num_blocks = (uint16_t) (p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI); + } + + p_info[0].p_dest = (void *) p_instance_ctrl->p_self_raw; + p_info[0].p_src = (void *) &R_CTSU->CTSUSC; + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + p_info[0].p_dest = (void *) p_instance_ctrl->p_mutual_raw; + p_info[0].num_blocks = (uint16_t) (p_info->num_blocks * 2); ///< Primary and Secondary + } + + #if (CTSU_CFG_NUM_CFC != 0) + if (CTSU_MODE_MUTUAL_CFC_SCAN == p_instance_ctrl->md) + { + p_info[0].length = p_instance_ctrl->p_ctsu_cfg->num_rx; + p_info[0].num_blocks = (uint16_t) (p_info[0].num_blocks / p_instance_ctrl->p_ctsu_cfg->num_rx); + p_info[0].p_src = (void *) &R_CTSU->CTSUCFCCNT; + } + #endif + #endif + } + + err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_transfer_autojudge + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_autojudge (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + + err = ctsu_transfer_autojudge_ctsuwr(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = ctsu_transfer_autojudge_ctsurd(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * ctsu_transfer_autojudge_ctsuwr + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_autojudge_ctsuwr (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + transfer_instance_t const * p_transfer; + transfer_info_t * p_info; + uint16_t calc_transfer_count; + + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_tx; + p_info = p_transfer->p_cfg->p_info; + + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->majirimd) + { + calc_transfer_count = p_instance_ctrl->num_elements; + + /* For automatic judgement register transfer */ + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 0, calc_transfer_count); + ctsu_transfer_address_set(p_info, 0, (void *) p_instance_ctrl->p_ajthr, (void *) &R_CTSU->CTSUAJTHR); + + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 1, calc_transfer_count); + ctsu_transfer_address_set(p_info, 1, (void *) p_instance_ctrl->p_ajmmar, (void *) &R_CTSU->CTSUAJMMAR); + + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 2, calc_transfer_count); + ctsu_transfer_address_set(p_info, 2, (void *) p_instance_ctrl->p_ajblact, (void *) &R_CTSU->CTSUAJBLACT); + + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 3, calc_transfer_count); + ctsu_transfer_address_set(p_info, 3, (void *) p_instance_ctrl->p_ajblar, (void *) &R_CTSU->CTSUAJBLAR); + + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 4, calc_transfer_count); + ctsu_transfer_address_set(p_info, 4, (void *) p_instance_ctrl->p_ajrr, (void *) &R_CTSU->CTSUAJRR); + + /* For CTSUMCACT1 register transfer */ + ctsu_transfer_mcact_set(p_info, 5, calc_transfer_count); + ctsu_transfer_address_set(p_info, 5, p_instance_ctrl->p_mcact1, (void *) &R_CTSU->CTSUMACT1); + + /* For CTSUMCACT2 register transfer */ + ctsu_transfer_mcact_set(p_info, 6, calc_transfer_count); + ctsu_transfer_address_set(p_info, 6, p_instance_ctrl->p_mcact2, (void *) &R_CTSU->CTSUMACT2); + + /* For CTSUSO register transfer */ + ctsu_transfer_autojudge_ctsuso_set(p_info, 7, calc_transfer_count); + ctsu_transfer_address_set(p_info, 7, (void *) p_instance_ctrl->p_ctsuwr, (void *) &R_CTSU->CTSUSO); + } + else + #endif + { + calc_transfer_count = p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI; + + /* For automatic judgement register transfer */ + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 0, calc_transfer_count); + ctsu_transfer_address_set(p_info, 0, (void *) p_instance_ctrl->p_ajthr, (void *) &R_CTSU->CTSUAJTHR); + + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 1, calc_transfer_count); + ctsu_transfer_address_set(p_info, 1, (void *) p_instance_ctrl->p_ajmmar, (void *) &R_CTSU->CTSUAJMMAR); + + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 2, calc_transfer_count); + ctsu_transfer_address_set(p_info, 2, (void *) p_instance_ctrl->p_ajblact, (void *) &R_CTSU->CTSUAJBLACT); + + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 3, calc_transfer_count); + ctsu_transfer_address_set(p_info, 3, (void *) p_instance_ctrl->p_ajblar, (void *) &R_CTSU->CTSUAJBLAR); + + ctsu_transfer_autojudge_ctsuwr_value_set(p_info, 4, calc_transfer_count); + ctsu_transfer_address_set(p_info, 4, (void *) p_instance_ctrl->p_ajrr, (void *) &R_CTSU->CTSUAJRR); + + /* For CTSUSO register transfer */ + ctsu_transfer_autojudge_ctsuso_set(p_info, 5, calc_transfer_count); + ctsu_transfer_address_set(p_info, 5, (void *) p_instance_ctrl->p_ctsuwr, (void *) &R_CTSU->CTSUSO); + } + + err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * ctsu_transfer_autojudge_ctsurd + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_autojudge_ctsurd (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + transfer_instance_t const * p_transfer; + transfer_info_t * p_info; + uint16_t calc_transfer_count; + + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_rx; + p_info = p_transfer->p_cfg->p_info; + + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->majirimd) + { + calc_transfer_count = p_instance_ctrl->num_elements; + } + else + #endif + { + calc_transfer_count = p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI; + } + + /* For automatic judgement register transfer */ + ctsu_transfer_autojudge_ctsurd_value_set(p_info, 0, calc_transfer_count); + ctsu_transfer_address_set(p_info, 0, (void *) &R_CTSU->CTSUAJMMAR, (void *) p_instance_ctrl->p_ajmmar); + + ctsu_transfer_autojudge_ctsurd_value_set(p_info, 1, calc_transfer_count); + ctsu_transfer_address_set(p_info, 1, (void *) &R_CTSU->CTSUAJBLACT, (void *) p_instance_ctrl->p_ajblact); + + ctsu_transfer_autojudge_ctsurd_value_set(p_info, 2, calc_transfer_count); + ctsu_transfer_address_set(p_info, 2, (void *) &R_CTSU->CTSUAJBLAR, (void *) p_instance_ctrl->p_ajblar); + + ctsu_transfer_autojudge_ctsurd_value_set(p_info, 3, calc_transfer_count); + ctsu_transfer_address_set(p_info, 3, (void *) &R_CTSU->CTSUAJRR, (void *) p_instance_ctrl->p_ajrr); + + /* For CTSUSCNT register transfer */ + ctsu_transfer_autojudge_ctsuscnt_set(p_info, 4, calc_transfer_count); + ctsu_transfer_address_set(p_info, 4, (void *) &R_CTSU->CTSUSC, (void *) p_instance_ctrl->p_self_raw); + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + p_info[4].p_dest = (void *) p_instance_ctrl->p_mutual_raw; + } + #endif + + err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + + #endif + #endif + + #if (BSP_FEATURE_CTSU_VERSION == 1) + +/*********************************************************************************************************************** + * ctsu_transfer_ctsu1 + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_ctsu1 (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + + err = ctsu_transfer_ctsu1_ctsuwr(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = ctsu_transfer_ctsu1_ctsurd(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * ctsu_transfer_ctsu1_ctsuwr + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_ctsu1_ctsuwr (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + transfer_instance_t const * p_transfer; + transfer_info_t * p_info; + uint16_t calc_transfer_count; + + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_tx; + p_info = p_transfer->p_cfg->p_info; + + calc_transfer_count = p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI; + + ctsu_transfer_ctsuso_set(p_info, 0, calc_transfer_count); + ctsu_transfer_address_set(p_info, 0, p_instance_ctrl->p_ctsuwr, (void *) &R_CTSU->CTSUSSC); + + if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) + { + p_info[0].num_blocks = 1; + p_info[0].p_src = (void *) &(g_ctsu_correction_info.ctsuwr); + } + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + else if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + p_info[0].num_blocks = 1; + p_info[0].p_src = (void *) &(g_ctsu_diag_info.ctsuwr); + } + #endif + else if ((CTSU_CORRECTION_RUN != g_ctsu_correction_info.status) && + (CTSU_MODE_DIAGNOSIS_SCAN != p_instance_ctrl->md)) + { + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + if (0 == ((p_instance_ctrl->ctsucr1 >> 7) & 0x01)) + { + p_info[0].num_blocks = p_instance_ctrl->num_elements * 2; + } + } + } + #endif + } + else + { + } + + err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * ctsu_transfer_ctsu1_ctsurd + ***********************************************************************************************************************/ +fsp_err_t ctsu_transfer_ctsu1_ctsurd (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err; + transfer_instance_t const * p_transfer; + transfer_info_t * p_info; + uint16_t calc_transfer_count; + + p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_rx; + p_info = p_transfer->p_cfg->p_info; + + calc_transfer_count = p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI; + + ctsu_transfer_ctsuscnt_set(p_info, 0, calc_transfer_count); + ctsu_transfer_address_set(p_info, 0, (void *) &R_CTSU->CTSUSC, p_instance_ctrl->p_self_raw); + + if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) + { + p_info[0].num_blocks = 1; + p_info[0].p_dest = (void *) &g_ctsu_correction_info.scanbuf; + } + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + else if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + p_info[0].num_blocks = 1; + p_info[0].p_dest = (void *) &g_ctsu_diag_info.scanbuf; + } + #endif + else if ((CTSU_CORRECTION_RUN != g_ctsu_correction_info.status) && + (CTSU_MODE_DIAGNOSIS_SCAN != p_instance_ctrl->md)) + { + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + p_info[0].p_dest = p_instance_ctrl->p_mutual_raw; + p_info[0].num_blocks = (uint16_t) (p_info->num_blocks * 2); ///< Primary and Secondary + + if (true == p_instance_ctrl->serial_tuning_enable) + { + if (0 == ((p_instance_ctrl->ctsucr1 >> 7) & 0x01)) + { + p_info[0].num_blocks = p_instance_ctrl->num_elements * 2; + } + } + } + #endif + } + else + { + } + + err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + + #endif + +/*********************************************************************************************************************** + * ctsu_transfer_ctsuso_set + ***********************************************************************************************************************/ +void ctsu_transfer_ctsuso_set (transfer_info_t * p_info, uint8_t array_number, uint16_t set_transfer_count) +{ + p_info[array_number].transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED; + p_info[array_number].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + #if (BSP_FEATURE_CTSU_VERSION == 2) + p_info[array_number].transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + p_info[array_number].transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + #endif + p_info[array_number].transfer_settings_word_b.irq = TRANSFER_IRQ_END; + p_info[array_number].transfer_settings_word_b.mode = TRANSFER_MODE_BLOCK; + p_info[array_number].transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION; + #if (BSP_FEATURE_CTSU_VERSION == 2) + p_info[array_number].transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + p_info[array_number].transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 2) + p_info[array_number].length = 1; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + p_info[array_number].length = 3; + #endif + p_info[array_number].num_blocks = set_transfer_count; +} + +/*********************************************************************************************************************** + * ctsu_transfer_ctsuscnt_set + ***********************************************************************************************************************/ +void ctsu_transfer_ctsuscnt_set (transfer_info_t * p_info, uint8_t array_number, uint16_t set_transfer_count) +{ + p_info[array_number].transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED; + #if (BSP_FEATURE_CTSU_VERSION == 2) + p_info[array_number].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + p_info[array_number].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + #endif + p_info[array_number].transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info[array_number].transfer_settings_word_b.irq = TRANSFER_IRQ_END; + p_info[array_number].transfer_settings_word_b.mode = TRANSFER_MODE_BLOCK; + p_info[array_number].transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE; + p_info[array_number].transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + #if (BSP_FEATURE_CTSU_VERSION == 2) + p_info[array_number].length = 1; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + p_info[array_number].length = 2; + #endif + p_info[array_number].num_blocks = set_transfer_count; +} + +/*********************************************************************************************************************** + * ctsu_transfer_address_set + ***********************************************************************************************************************/ +void ctsu_transfer_address_set (transfer_info_t * p_info, + uint8_t array_number, + void * p_set_source_addr, + void * p_set_dest_addr) +{ + p_info[array_number].p_src = p_set_source_addr; + p_info[array_number].p_dest = p_set_dest_addr; +} + + #if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_transfer_autojudge_value_set + ***********************************************************************************************************************/ +void ctsu_transfer_autojudge_ctsuwr_value_set (transfer_info_t * p_info, + uint8_t array_number, + uint16_t set_transfer_count) +{ + p_info[array_number].transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_EACH; + p_info[array_number].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info[array_number].transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info[array_number].transfer_settings_word_b.irq = TRANSFER_IRQ_END; + p_info[array_number].transfer_settings_word_b.mode = TRANSFER_MODE_REPEAT; + p_info[array_number].transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE; + p_info[array_number].transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + p_info[array_number].length = set_transfer_count; +} + +/*********************************************************************************************************************** + * ctsu_transfer_autojudge_ctsuso_set + ***********************************************************************************************************************/ +void ctsu_transfer_autojudge_ctsuso_set (transfer_info_t * p_info, uint8_t array_number, uint16_t set_transfer_count) +{ + p_info[array_number].transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED; + p_info[array_number].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info[array_number].transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info[array_number].transfer_settings_word_b.irq = TRANSFER_IRQ_END; + p_info[array_number].transfer_settings_word_b.mode = TRANSFER_MODE_REPEAT; + p_info[array_number].transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE; + p_info[array_number].transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + p_info[array_number].length = set_transfer_count; +} + +/*********************************************************************************************************************** + * ctsu_transfer_autojudge_ctsurd_value_set + ***********************************************************************************************************************/ +void ctsu_transfer_autojudge_ctsurd_value_set (transfer_info_t * p_info, + uint8_t array_number, + uint16_t set_transfer_count) +{ + p_info[array_number].transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_EACH; + p_info[array_number].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info[array_number].transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info[array_number].transfer_settings_word_b.irq = TRANSFER_IRQ_END; + p_info[array_number].transfer_settings_word_b.mode = TRANSFER_MODE_REPEAT; + p_info[array_number].transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION; + p_info[array_number].transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + p_info[array_number].length = set_transfer_count; +} + +/*********************************************************************************************************************** + * ctsu_transfer_autojudge_ctsuscnt_set + ***********************************************************************************************************************/ +void ctsu_transfer_autojudge_ctsuscnt_set (transfer_info_t * p_info, uint8_t array_number, uint16_t set_transfer_count) +{ + p_info[array_number].transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED; + p_info[array_number].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info[array_number].transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info[array_number].transfer_settings_word_b.irq = TRANSFER_IRQ_END; + p_info[array_number].transfer_settings_word_b.mode = TRANSFER_MODE_REPEAT; + p_info[array_number].transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION; + p_info[array_number].transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + p_info[array_number].length = set_transfer_count; +} + + #endif + + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_transfer_mcact_set + ***********************************************************************************************************************/ +void ctsu_transfer_mcact_set (transfer_info_t * p_info, uint8_t array_number, uint16_t set_transfer_count) +{ + p_info[array_number].transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_EACH; + p_info[array_number].transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info[array_number].transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info[array_number].transfer_settings_word_b.irq = TRANSFER_IRQ_END; + p_info[array_number].transfer_settings_word_b.mode = TRANSFER_MODE_REPEAT; + p_info[array_number].transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE; + p_info[array_number].transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + p_info[array_number].length = set_transfer_count; +} + + #endif + + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) +static void ctsu_transer_count_element (uint32_t element_mask, uint16_t * num_element) +{ + uint8_t n; + + /* Get the number of measurable elements from enabled CHAC or CHTRC */ + for (n = 0; n < CTSU_TRANSFER_TUNING_CH_REG_MAX_NUM; n++) + { + if (0x00000001 == ((element_mask >> n) & 0x00000001)) + { + (*num_element)++; + } + } +} + + #endif + #endif + +#endif + +/*********************************************************************************************************************** + * ctsu_initial_offset_tuning + ***********************************************************************************************************************/ +void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint16_t element_id; + int32_t diff = 0; + uint32_t complete_flag = 0; + uint32_t num_complete = 0; + uint16_t target_val; +#if (BSP_FEATURE_CTSU_VERSION == 1) + uint16_t ctsuso; + ctsu_correction_calc_t calc; +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + uint16_t i; + uint16_t element_top; + uint16_t corr_data[CTSU_CFG_NUM_SUMULTI]; + int32_t ctsuso; + uint32_t snum; + int32_t offset_unit; +#endif + + /* element_id through each element for control block */ + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + if (0 == *(p_instance_ctrl->p_element_complete_flag + element_id)) + { +#if (BSP_FEATURE_CTSU_VERSION == 1) + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + target_val = (p_instance_ctrl->tuning_self_target_value); + } + else + { + target_val = (p_instance_ctrl->tuning_mutual_target_value); + } + + calc.snum = (p_instance_ctrl->p_ctsuwr[element_id].ctsuso0 >> 10) & CTSU_SNUM_MAX; + calc.sdpa = (p_instance_ctrl->p_ctsuwr[element_id].ctsuso1 >> 8) & CTSU_SDPA_MAX; + target_val = (uint16_t) (target_val * + (uint32_t) ((calc.snum + 1) * (calc.sdpa + 1)) / + g_ctsu_correction_info.ctsu_clock); + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + diff = (p_instance_ctrl->p_self_data + element_id)->int_data - target_val; + } + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md) + { + diff = (p_instance_ctrl->p_mutual_pri_data + element_id)->int_data - target_val; + } + #endif + ctsuso = (p_instance_ctrl->p_ctsuwr[element_id].ctsuso0 & CTSU_TUNING_MAX); + if (0 < diff) + { + if (*(p_instance_ctrl->p_tuning_diff + element_id) < 0) + { + if ((-diff) > *(p_instance_ctrl->p_tuning_diff + element_id)) + { + ctsuso++; ///< Decrease count + } + + complete_flag = 1; + } + else + { + if (CTSU_TUNING_MAX == ctsuso) /* CTSUSO limit check */ + { + complete_flag = 1; + } + else + { + ctsuso++; ///< Decrease count + (*(p_instance_ctrl->p_tuning_diff + element_id)) = diff; ///< Plus + } + } + } + else if (0 == diff) + { + complete_flag = 1; + } + else + { + if (*(p_instance_ctrl->p_tuning_diff + element_id) > 0) + { + if ((-diff) > *(p_instance_ctrl->p_tuning_diff + element_id)) + { + ctsuso--; ///< Increase count + } + + complete_flag = 1; + } + else + { + if (CTSU_TUNING_MIN == ctsuso) /* CTSUSO limit check */ + { + complete_flag = 1; + } + else + { + ctsuso--; ///< Increase count + (*(p_instance_ctrl->p_tuning_diff + element_id)) = diff; ///< Minus + } + } + } + + p_instance_ctrl->p_ctsuwr[element_id].ctsuso0 &= (uint16_t) (~CTSU_TUNING_MAX); + p_instance_ctrl->p_ctsuwr[element_id].ctsuso0 |= ctsuso; +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + element_top = (uint16_t) (element_id * CTSU_CFG_NUM_SUMULTI); + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + /* Adjust only frequencies for which offset tuning is not completed */ + if (0 == (p_instance_ctrl->p_frequency_complete_flag[element_id] & (1 << i))) + { + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + target_val = (p_instance_ctrl->tuning_self_target_value / 2); + } + else + { + target_val = (p_instance_ctrl->tuning_mutual_target_value / 2); + } + + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + corr_data[i] = p_instance_ctrl->p_self_corr[element_top + i]; + } + else + { + corr_data[i] = p_instance_ctrl->p_mutual_pri_corr[element_top + i]; + } + + snum = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI)].ctsuso >> 10) & + CTSU_SNUM_MAX; + target_val = (uint16_t) (((uint32_t) target_val * (snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + offset_unit = (int32_t) ((CTSU_CORRECTION_OFFSET_UNIT * (snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + + /* Calculate CTSUSO equivalent difference between current value and target value */ + diff = (int32_t) ((int32_t) corr_data[i] - (int32_t) target_val) / + (offset_unit >> p_instance_ctrl->range); + + ctsuso = (int32_t) (p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso & CTSU_TUNING_MAX); + ctsuso += diff; + + /* If the CTSUSO exceeds the minimum value or the maximum value, tuning complete */ + if (ctsuso < 0) + { + ctsuso = 0; + p_instance_ctrl->p_frequency_complete_flag[element_id] += (uint8_t) (1 << i); + } + else if (ctsuso > CTSU_TUNING_MAX) + { + ctsuso = CTSU_TUNING_MAX; + p_instance_ctrl->p_frequency_complete_flag[element_id] += (uint8_t) (1 << i); + } + else + { + /* If the difference is large, tuning value may not be able to match, so create the next opportunity */ + if (0 == diff) + { + p_instance_ctrl->p_frequency_complete_flag[element_id] += (uint8_t) (1 << i); + } + } + + /* Set the result of the calculated CTSUSO */ + p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso &= (uint32_t) (~CTSU_TUNING_MAX); + p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso |= (uint32_t) ctsuso; + } + + /* Add completion status for each frequency */ + complete_flag += ((p_instance_ctrl->p_frequency_complete_flag[element_id] >> i) & 1); + } +#endif + } + else + { + complete_flag = CTSU_CFG_NUM_SUMULTI; + } + + if (CTSU_CFG_NUM_SUMULTI == complete_flag) + { + num_complete++; + *(p_instance_ctrl->p_element_complete_flag + element_id) = 1; + } + + complete_flag = 0; + } + + if (num_complete == p_instance_ctrl->num_elements) + { + p_instance_ctrl->tuning = CTSU_TUNING_COMPLETE; + } +} + +/*********************************************************************************************************************** + * ctsu_moving_average + ***********************************************************************************************************************/ +void ctsu_moving_average (ctsu_data_t * p_average, uint16_t new_data, uint16_t average_num) +{ + uint32_t work; + + work = (uint32_t) (((uint32_t) p_average->int_data << CTSU_CFG_DECIMAL_POINT) + p_average->decimal_point_data); + work -= (uint32_t) (work / average_num); + work += (uint32_t) (((uint32_t) new_data << CTSU_CFG_DECIMAL_POINT) / average_num); + + p_average->int_data = (uint16_t) (work >> CTSU_CFG_DECIMAL_POINT); + p_average->decimal_point_data = (uint16_t) (work & CTSU_CFG_DECIMAL_POINT_MASK); +} + +/*********************************************************************************************************************** + * CTSUWR interrupt handler. This service routine sets the tuning for the next element to be scanned by hardware. + ***********************************************************************************************************************/ +void ctsu_write_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /** Clear the BSP IRQ Flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + #endif +#else + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /** Clear the BSP IRQ Flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + #endif + + /* Write settings for current element */ + if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) + { + #if (BSP_FEATURE_CTSU_VERSION == 2) + R_CTSU->CTSUSO = g_ctsu_correction_info.ctsuwr.ctsuso; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + R_CTSU->CTSUSSC = g_ctsu_correction_info.ctsuwr.ctsussc; + R_CTSU->CTSUSO0 = g_ctsu_correction_info.ctsuwr.ctsuso0; + R_CTSU->CTSUSO1 = g_ctsu_correction_info.ctsuwr.ctsuso1; + #endif + } + + #if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_NUM_CFC != 0) + else if ((CTSU_CORRECTION_RUN == g_ctsu_corrcfc_info.status)) + { + R_CTSU->CTSUSO = g_ctsu_corrcfc_info.ctsuwr.ctsuso; + } + #endif + #endif + else if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + #if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + R_CTSU->CTSUSO = g_ctsu_diag_info.ctsuwr.ctsuso; + p_instance_ctrl->wr_index++; + #endif + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + R_CTSU->CTSUSSC = g_ctsu_diag_info.ctsuwr.ctsussc; + R_CTSU->CTSUSO0 = g_ctsu_diag_info.ctsuwr.ctsuso0; + R_CTSU->CTSUSO1 = g_ctsu_diag_info.ctsuwr.ctsuso1; + #endif + #endif + } + else + { + #if (BSP_FEATURE_CTSU_VERSION == 2) + R_CTSU->CTSUSO = p_instance_ctrl->p_ctsuwr[p_instance_ctrl->wr_index].ctsuso; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + R_CTSU->CTSUSSC = p_instance_ctrl->p_ctsuwr[p_instance_ctrl->wr_index].ctsussc; + R_CTSU->CTSUSO0 = p_instance_ctrl->p_ctsuwr[p_instance_ctrl->wr_index].ctsuso0; + R_CTSU->CTSUSO1 = p_instance_ctrl->p_ctsuwr[p_instance_ctrl->wr_index].ctsuso1; + #endif + p_instance_ctrl->wr_index++; + } +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*********************************************************************************************************************** + * CTSURD interrupt handler. This service routine reads the sensor count and reference counter for + * the current element and places the value in the scan data buffer. Note that the reference counter + * does not work properly but is saved anyway for backward compatibility and potential future use. + * Additionally, the SC register cannot be read again until RC is read. + ***********************************************************************************************************************/ +void ctsu_read_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + + /** Clear the BSP IRQ Flag */ + #if (BSP_FEATURE_ICU_HAS_IELSR) + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + #endif +#else + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /** Clear the BSP IRQ Flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + #endif + + /* read current channel/element value */ + /* Store the reference counter for possible future use. Register must be read or scan will hang. */ + + #if (BSP_FEATURE_CTSU_VERSION == 1) + if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) + { + g_ctsu_correction_info.scanbuf.sen = R_CTSU->CTSUSC; + g_ctsu_correction_info.scanbuf.ref = R_CTSU->CTSURC; + } + + #if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + else if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + g_ctsu_diag_info.scanbuf.sen = R_CTSU->CTSUSC; + g_ctsu_diag_info.scanbuf.ref = R_CTSU->CTSURC; + } + #endif + #endif + else + { + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + (p_instance_ctrl->p_self_raw + p_instance_ctrl->rd_index)->sen = R_CTSU->CTSUSC; + (p_instance_ctrl->p_self_raw + p_instance_ctrl->rd_index)->ref = R_CTSU->CTSURC; + p_instance_ctrl->rd_index++; + } + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md) + { + if (false == p_instance_ctrl->serial_tuning_enable) + { + if (1 == R_CTSU->CTSUST_b.CTSUPS) + { + (p_instance_ctrl->p_mutual_raw + p_instance_ctrl->rd_index)->pri_sen = R_CTSU->CTSUSC; + (p_instance_ctrl->p_mutual_raw + p_instance_ctrl->rd_index)->pri_ref = R_CTSU->CTSURC; + } + else + { + (p_instance_ctrl->p_mutual_raw + p_instance_ctrl->rd_index)->snd_sen = R_CTSU->CTSUSC; + (p_instance_ctrl->p_mutual_raw + p_instance_ctrl->rd_index)->snd_ref = R_CTSU->CTSURC; + p_instance_ctrl->rd_index++; + } + } + else + { + p_instance_ctrl->serial_tuning_mutual_cnt++; + if (p_instance_ctrl->serial_tuning_mutual_cnt % 2) + { + (p_instance_ctrl->p_mutual_raw + p_instance_ctrl->rd_index)->pri_sen = R_CTSU->CTSUSC; + (p_instance_ctrl->p_mutual_raw + p_instance_ctrl->rd_index)->pri_ref = R_CTSU->CTSURC; + } + else + { + (p_instance_ctrl->p_mutual_raw + p_instance_ctrl->rd_index)->snd_sen = R_CTSU->CTSUSC; + (p_instance_ctrl->p_mutual_raw + p_instance_ctrl->rd_index)->snd_ref = R_CTSU->CTSURC; + p_instance_ctrl->rd_index++; + } + } + } + #endif + } + #endif + + #if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_NUM_CFC != 0) + uint16_t i; + #endif + if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) + { + g_ctsu_correction_info.scanbuf = R_CTSU->CTSUSC; + } + + #if (CTSU_CFG_NUM_CFC != 0) + else if (CTSU_CORRECTION_RUN == g_ctsu_corrcfc_info.status) + { + for (i = 0; i < g_ctsu_corrcfc_info.num_ts; i++) + { + g_ctsu_corrcfc_info.scanbuf[i] = R_CTSU->CTSUCFCCNT_b.CFCCNT; + } + } + #endif + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + else if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + if (CTSU_DIAG_CFC == g_ctsu_diag_info.state) + { + g_ctsu_diag_info.ctsuscnt[p_instance_ctrl->rd_index] = R_CTSU->CTSUCFCCNT; + p_instance_ctrl->rd_index++; + } + else + { + g_ctsu_diag_info.ctsuscnt[p_instance_ctrl->rd_index] = R_CTSU->CTSUSCNT; + p_instance_ctrl->rd_index++; + } + } + #endif + else + { + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->md)) + { + p_instance_ctrl->p_self_raw[p_instance_ctrl->rd_index] = R_CTSU->CTSUSC; + p_instance_ctrl->rd_index++; + } + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md) + { + p_instance_ctrl->p_mutual_raw[p_instance_ctrl->rd_index] = R_CTSU->CTSUSC; + p_instance_ctrl->rd_index++; + } + + #if (CTSU_CFG_NUM_CFC != 0) + if (CTSU_MODE_MUTUAL_CFC_SCAN == p_instance_ctrl->md) + { + for (i = 0; i < p_instance_ctrl->p_ctsu_cfg->num_rx; i++) + { + p_instance_ctrl->p_mutual_raw[p_instance_ctrl->rd_index] = R_CTSU->CTSUCFCCNT_b.CFCCNT; + p_instance_ctrl->rd_index++; + } + } + #endif + #endif + } + #endif + if (1 == p_instance_ctrl->interrupt_reverse_flag) + { + p_instance_ctrl->interrupt_reverse_flag = 0; + + ctsu_end_interrupt(p_instance_ctrl); + } +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*********************************************************************************************************************** + * CTSUFN interrupt handler. This service routine occurs when all elements have been scanned (finished). + * The user's callback function is called if available. + ***********************************************************************************************************************/ +void ctsu_end_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + uint16_t rd_index; +#if (BSP_FEATURE_ICU_HAS_IELSR) + + /** Clear the BSP IRQ Flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); +#endif + + /* In CTSU1 and CTSU2 self-capacity and current measurement mode and diagnostic mode, */ + /* rd_index has the same value as wr_index. */ + rd_index = p_instance_ctrl->rd_index; + +#if (BSP_FEATURE_CTSU_VERSION == 1) + if (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + if (0 == ((p_instance_ctrl->ctsucr1 >> 7) & 0x01)) + { + rd_index = p_instance_ctrl->serial_tuning_mutual_cnt; + } + } + } +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + if (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + if (0 == ((p_instance_ctrl->ctsucr1 >> 7) & 0x01)) + { + rd_index = p_instance_ctrl->rd_index; + } + else + { + rd_index = p_instance_ctrl->rd_index / 2; + } + } + else + { + /* In the mutual capacity of CTSU2, the value of rd_index is twice the value of wr_index. */ + rd_index = p_instance_ctrl->rd_index / 2; + } + } + + #if (CTSU_CFG_NUM_CFC != 0) + if (CTSU_MODE_MUTUAL_CFC_SCAN == p_instance_ctrl->md) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + if (0 == ((p_instance_ctrl->ctsucr1 >> 7) & 0x01)) + { + rd_index = p_instance_ctrl->rd_index; + } + else + { + rd_index = (uint16_t) (p_instance_ctrl->rd_index / (p_instance_ctrl->p_ctsu_cfg->num_rx * 2)); + } + } + else + { + /* In the CFC mutual capacity of CTSU2, rd_index is twice the number of RX terminals in each wr_index. */ + rd_index = (uint16_t) (p_instance_ctrl->rd_index / (p_instance_ctrl->p_ctsu_cfg->num_rx * 2)); + } + } + #endif + #endif +#endif + + /* Countermeasure for the problem that RD interrupt and FN interrupt are reversed. */ + if (rd_index != p_instance_ctrl->wr_index) + { + p_instance_ctrl->interrupt_reverse_flag = 1; + + return; + } + + ctsu_end_interrupt(p_instance_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +void ctsu_end_interrupt (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + ctsu_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + ctsu_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_DIAG_OVER_VOLTAGE == g_ctsu_diag_info.state) + { + if (R_CTSU->CTSUERRS_b.CTSUICOMP == 1) + { + g_ctsu_diag_info.icomp = 1; + } + } + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) + { + if (CTSU_DIAG_OVER_CURRENT == g_ctsu_diag_info.state) + { + if (R_CTSU->CTSUSR0 & CTSU_ICOMP1) + { + g_ctsu_diag_info.icomp1_value = R_CTSU->CTSUSR_b.ICOMP1; + } + } + } + #endif +#endif + + p_args->event = CTSU_EVENT_SCAN_COMPLETE; + + if (R_CTSU->CTSUST & CTSU_SOVF) + { + p_args->event |= CTSU_EVENT_OVERFLOW; + R_CTSU->CTSUST &= (uint8_t) (~CTSU_SOVF); + } + +#if (BSP_FEATURE_CTSU_VERSION == 2) + if (R_CTSU->CTSUSR0 & (CTSU_ICOMP0 | CTSU_ICOMP1)) + { + if (R_CTSU->CTSUSR0 & CTSU_ICOMP0) + { + p_args->event |= CTSU_EVENT_ICOMP; + } + + if (R_CTSU->CTSUSR0 & CTSU_ICOMP1) + { + p_args->event |= CTSU_EVENT_ICOMP1; + } + + R_CTSU->CTSUSR0 |= CTSU_ICOMPRST; + } +#endif +#if (BSP_FEATURE_CTSU_VERSION == 1) + if (R_CTSU->CTSUERRS_b.CTSUICOMP == 1) + { + R_CTSU->CTSUCR1 &= (uint8_t) (~0x01); + __NOP(); + __NOP(); + R_CTSU->CTSUCR1 |= 0x01; + p_args->event |= CTSU_EVENT_ICOMP; + } +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + if (CTSU_CORRECTION_RUN != g_ctsu_correction_info.status) + { + if (CTSU_MODE_CORRECTION_SCAN == p_instance_ctrl->md) + { + R_CTSU->CTSUCRA_b.SDPSEL = 0; + R_CTSU->CTSUSUCLK0 = (uint16_t) ((CTSU_CFG_SUMULTI0 << 8) | g_ctsu_correction_info.suadj0); + R_CTSU->CTSUCRB_b.SSCNT = 1; + R_CTSU->CTSUCALIB_b.SUCARRY = 0; + R_CTSU->CTSUCALIB_b.CCOCALIB = 0; + R_CTSU->CTSUCALIB_b.CCOCLK = 1; + R_CTSU->CTSUCALIB_b.TSOC = 0; + R_CTSU->CTSUCRA_b.SDPSEL = 1; + } + } + #endif +#endif + +#if (CTSU_CFG_MULTIPLE_ELECTRODE_CONNECTION_ENABLE == 1) + if ((1 == p_instance_ctrl->tsod) && (CTSU_CAP_EXTERNAL == p_instance_ctrl->cap)) + { + /* When using MEC, MD0 bit is set to single scan mode. */ + R_CTSU->CTSUMCH_b.MCH0 = (uint8_t) (p_instance_ctrl->mec_ts & CTSU_MEC_BIT6_MASK); + + /* Set MCH1 when using both MEC and Active Shield.*/ + if ((0 != p_instance_ctrl->ctsuchtrc0) || + (0 != p_instance_ctrl->ctsuchtrc1) || + (0 != p_instance_ctrl->ctsuchtrc2) || + (0 != p_instance_ctrl->ctsuchtrc3) || + (0 != p_instance_ctrl->ctsuchtrc4)) + { + R_CTSU->CTSUMCH_b.MCH1 = (uint8_t) (p_instance_ctrl->mec_shield_ts & CTSU_MEC_BIT6_MASK); + } + } +#endif + + p_instance_ctrl->state = CTSU_STATE_SCANNED; + p_instance_ctrl->error_status = args.event; + p_args->p_context = p_instance_ctrl->p_context; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_callback) + { +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + ctsu_prv_ns_callback p_callback = (ctsu_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + } + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } + + /* reset indexes */ + p_instance_ctrl->wr_index = 0; + p_instance_ctrl->rd_index = 0; +#if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + p_instance_ctrl->serial_tuning_mutual_cnt = 0; +#endif +} + +/*********************************************************************************************************************** + * ctsu_correction_process + ***********************************************************************************************************************/ +void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ +#if (BSP_FEATURE_CTSU_VERSION == 2) + uint32_t i; + uint32_t j; + uint32_t trimb; + uint8_t rtrim; + uint16_t x1; + uint16_t x0; + uint16_t y0; + uint16_t y1; + uint16_t dac2vdc; + uint8_t trimb_byte; + uint16_t dac_value; + uint32_t ref_value; + uint16_t c0; + uint16_t c1; + + g_ctsu_correction_info.status = CTSU_CORRECTION_RUN; + + R_CTSU->CTSUCRA_b.MD0 = 1; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + R_CTSU->CTSUCRA_b.LOAD = 1; + + /* Setting time of measurement */ + g_ctsu_correction_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10); + + /* Measure the current input to the ICO by passing current through the internal resistance in each range. */ + /* The theoretical value of the current is 12.5uA. */ + R_CTSU->CTSUCHACA = 1; + R_CTSU->CTSUCHACB = 0; + R_CTSU->CTSUCALIB_b.TSOC = 1; + for (i = 0; i < CTSU_RANGE_NUM; i++) + { + if (CTSU_RANGE_20UA == i) + { + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; + } + else if (CTSU_RANGE_40UA == i) + { + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + } + else if (CTSU_RANGE_80UA == i) + { + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + } + else + { + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; + } + + R_CTSU->CTSUCRA_b.LOAD = 3; + ctsu_correction_measurement(p_instance_ctrl, &g_ctsu_correction_info.base_value[i]); + R_CTSU->CTSUCRA_b.LOAD = 1; + } + + /* Measure by inputting each constant current from internal DAC to ICO. */ + R_CTSU->CTSUCRB_b.SSCNT = 0; + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCALIB_b.CCOCALIB = 1; + + /* 2.5uA * (j + 1), SUCARRY and SSCNT = 3 are required for greater than 20uA */ + for (j = 0; j < CTSU_CORRECTION_POINT_NUM; j++) + { + R_CTSU->CTSUCRA_b.SDPSEL = 0; + if (8 > j) + { + R_CTSU->CTSUSUCLK0 = (uint16_t) (((j + 1) * CTSU_CORRECTION_SUMULTI) - 1); + } + else + { + R_CTSU->CTSUCRB_b.SSCNT = 3; + R_CTSU->CTSUCALIB_b.SUCARRY = 1; + R_CTSU->CTSUSUCLK0 = (uint16_t) (((j - 3) * CTSU_CORRECTION_SUMULTI) - 1); + } + + R_CTSU->CTSUCRA_b.SDPSEL = 1; + + // store CCODAC path value to tha last array of dac_value + ctsu_correction_measurement(p_instance_ctrl, &(g_ctsu_correction_info.dac_value[CTSU_RANGE_NUM - 1][j])); + } + + /* Calculate the coefficient between step2 and step3 in each range. */ + trimb = R_CTSUTRIM->CTSUTRIMB; + rtrim = R_CTSUTRIM->CTSUTRIMA_b.RTRIM; + + for (i = 0; i < CTSU_RANGE_NUM; i++) + { + /* Get resistance value from TRIMB register. */ + /* Error rate calculation on VCD path as UQ1.9 */ + trimb_byte = (uint8_t) ((trimb >> ((CTSU_RANGE_NUM - 1 - i) * 8)) & CTSU_CORRECTION_TRIMB_MAX); + + switch (trimb_byte & CTSU_CORRECTION_TRIMB_THRESHOLD1) + { + case CTSU_CORRECTION_TRIMB_THRESHOLD1: + { + if (rtrim > CTSU_CORRECTION_RTRIM_THRESHOLD1) + { + x1 = CTSU_CORRECTION_BIT8; /* 0.05 */ + } + else + { + x1 = CTSU_CORRECTION_BIT9; /* 1.00 */ + } + + break; + } + + case 0x00: + { + if (rtrim < CTSU_CORRECTION_RTRIM_THRESHOLD2) + { + x1 = (CTSU_CORRECTION_BIT7 | CTSU_CORRECTION_BIT8); /* 0.25 and 0.50 */ + } + else + { + x1 = (CTSU_CORRECTION_BIT7 | CTSU_CORRECTION_BIT9); /* 0.25 and 1.00 */ + } + + break; + } + + case CTSU_CORRECTION_TRIMB_SIGN_BIT: + { + x1 = CTSU_CORRECTION_BIT9; /* 1.00 */ + break; + } + + default: /* 0x40 */ + { + x1 = (CTSU_CORRECTION_BIT7 | CTSU_CORRECTION_BIT8); /* 0.25 and 0.50 */ + break; + } + } + + g_ctsu_correction_info.error_rate[i] = x1 + (trimb_byte & CTSU_CORRECTION_BIT6_0); + + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + + /* Store error rate (6bit left shift) for diagnosis feature */ + g_ctsu_diag_info.error_registance[i] = (uint32_t) (g_ctsu_correction_info.error_rate[i] << 6); + #endif + + // searching for upper index of CCODAC path value containing VDC path value + // Possibility of base_value > g_ctsu_correction_info.dac_value[][CTSU_CORRECTION_POINT_NUM - 1] + + // Theoretical value at VDC path measurement + x1 = (uint16_t) (((uint32_t) CTSU_CORRECTION_STD_VAL << 9) / g_ctsu_correction_info.error_rate[i]); + + j = x1 / CTSU_CORRECTION_STD_UNIT; // upper index of theoretical value + + x0 = (uint16_t) (CTSU_CORRECTION_STD_UNIT * j); // lower side Theoretical value + y0 = g_ctsu_correction_info.dac_value[CTSU_RANGE_NUM - 1][j - 1]; + y1 = g_ctsu_correction_info.dac_value[CTSU_RANGE_NUM - 1][j]; + + // Calculate CCODAC path value on VDC path current by linear interpolation + dac2vdc = (uint16_t) (y0 + ((uint32_t) (y1 - y0) * (x1 - x0)) / CTSU_CORRECTION_STD_UNIT); + + // calculate VDC path conversion ratio + dac2vdc = + (uint16_t) (((int32_t) g_ctsu_correction_info.base_value[i] << CTSU_CORRECTION_DIV_PRECISION) / dac2vdc); + + // Correct CCODAC path value using conversion ratio, and make correction coefficients + for (j = 0; j < CTSU_CORRECTION_POINT_NUM; j++) + { + dac_value = + (uint16_t) (((uint32_t) g_ctsu_correction_info.dac_value[CTSU_RANGE_NUM - 1][j] * dac2vdc) >> + CTSU_CORRECTION_DIV_PRECISION); + ref_value = (CTSU_CORRECTION_STD_UNIT * (j + 1)); + + g_ctsu_correction_info.dac_value[i][j] = dac_value; + g_ctsu_correction_info.coef[i][j] = + (uint16_t) ((ref_value << CTSU_CORRECTION_DIV_PRECISION) / dac_value); + } + + // expand correction range + c0 = g_ctsu_correction_info.coef[i][0]; + c1 = g_ctsu_correction_info.coef[i][1]; + x0 = g_ctsu_correction_info.dac_value[i][0]; + x1 = g_ctsu_correction_info.dac_value[i][1]; + + g_ctsu_correction_info.coef[i][0] = (uint16_t) (c1 - ((uint32_t) (c1 - c0) * x1) / (x1 - x0)); + g_ctsu_correction_info.dac_value[i][0] = 0; + + c0 = g_ctsu_correction_info.coef[i][10]; + c1 = g_ctsu_correction_info.coef[i][11]; + x0 = g_ctsu_correction_info.dac_value[i][10]; + x1 = g_ctsu_correction_info.dac_value[i][11]; + + g_ctsu_correction_info.coef[i][11] = + (uint16_t) (c1 + ((uint32_t) (c1 - c0) * (CTSU_COUNT_MAX - x1)) / (x1 - x0)); + g_ctsu_correction_info.dac_value[i][11] = CTSU_COUNT_MAX; + } + + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + for (i = 0; i < (CTSU_RANGE_NUM - 1); i++) + { + g_ctsu_correction_info.range_ratio[i] = + (uint16_t) (((uint32_t) g_ctsu_correction_info.error_rate[i] << CTSU_SHIFT_AMOUNT) / + g_ctsu_correction_info.error_rate[CTSU_RANGE_160UA]); + } + #endif + g_ctsu_correction_info.status = CTSU_CORRECTION_COMPLETE; +#endif +#if (BSP_FEATURE_CTSU_VERSION == 1) + uint16_t second_std_val; + uint32_t ctsu_sdpa; + uint32_t pclkb_mhz; + + #if BSP_FEATURE_CTSU_HAS_TRMR + uint8_t ctsutrimr_def; + #endif + + g_ctsu_correction_info.status = CTSU_CORRECTION_RUN; + + pclkb_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / CTSU_PCLKB_FREQ_MHZ; + if (CTSU_PCLKB_FREQ_RANGE1 >= pclkb_mhz) + { + R_CTSU->CTSUCR1 |= (0 << 4); + ctsu_sdpa = pclkb_mhz - 1; + } + else if ((CTSU_PCLKB_FREQ_RANGE1 < pclkb_mhz) && (CTSU_PCLKB_FREQ_RANGE2 >= pclkb_mhz)) + { + R_CTSU->CTSUCR1 |= (1 << 4); + ctsu_sdpa = (pclkb_mhz / 2) - 1; + } + else + { + R_CTSU->CTSUCR1 |= (2 << 4); + ctsu_sdpa = (pclkb_mhz / 4) - 1; + } + + g_ctsu_correction_info.ctsu_clock = pclkb_mhz >> CTSU_CFG_PCLK_DIVISION; + + R_CTSU->CTSUCR1 |= (CTSU_MODE_SELF_MULTI_SCAN << 6); + R_CTSU->CTSUCHAC[0] = 0x01; + + g_ctsu_correction_info.ctsuwr.ctsussc = (CTSU_SSDIV_0500 << 8); + g_ctsu_correction_info.ctsuwr.ctsuso0 = 0x0000; + + /* Set CTSUSO1 */ + g_ctsu_correction_info.ctsuwr.ctsuso1 = (uint16_t) ((CTSU_ICOG_66 << 13) | (ctsu_sdpa << 8) | CTSU_RICOA_RECOMMEND); + + /* Correction measurement setting */ + R_CTSU->CTSUERRS_b.CTSUSPMD = 2; + R_CTSU->CTSUERRS_b.CTSUTSOC = 1; + R_BSP_SoftwareDelay(CTSU_WAIT_TIME, BSP_DELAY_UNITS_MICROSECONDS); + + /* First value measurement */ + ctsu_correction_measurement(p_instance_ctrl, &g_ctsu_correction_info.first_val); + + /* Second standard value create */ + #if BSP_FEATURE_CTSU_HAS_TRMR + uint32_t work; + + /* ctsutrimr_def + 273 ((ctsutrimr_def + 273) * 2560 * 128) */ + /* second_std_val = ------------------- * 40960 = ------------------------------------ + 64 */ + /* 528 33 * 128 */ + + work = (ctsutrimr_def + 273) * 9930 + 64; + second_std_val = (uint16_t) (work >> 7); + + /* Current trimming value storage */ + ctsutrimr_def = CTSU.CTSUTRMR; + + /* 0xFF set in the current trimming register */ + CTSU.CTSUTRMR = 0xFF; + #else + second_std_val = (uint16_t) (CTSU_CORRECTION_2ND_STD_VAL * CTSU_WAFER_PARAMETER); + g_ctsu_correction_info.ctsuwr.ctsuso1 |= (uint16_t) (CTSU_ICOG_40 << 13); /* ICO gain 66% -> 40% */ + #endif + + /* Second value measurement */ + ctsu_correction_measurement(p_instance_ctrl, &g_ctsu_correction_info.second_val); + #if BSP_FEATURE_CTSU_HAS_TRMR + + /* Return the current trimming register to the initial value */ + CTSU.CTSUTRMR = ctsutrimr_def; + #endif + + /* Normal measurement setting */ + R_CTSU->CTSUERRS_b.CTSUTSOC = 0; + R_CTSU->CTSUERRS_b.CTSUSPMD = 0; + + R_BSP_SoftwareDelay(CTSU_WAIT_TIME, BSP_DELAY_UNITS_MICROSECONDS); + + if ((0 != g_ctsu_correction_info.first_val) && (0 != g_ctsu_correction_info.second_val)) + { + if (g_ctsu_correction_info.second_val < g_ctsu_correction_info.first_val) + { + /* 1st coefficient create */ + g_ctsu_correction_info.first_coefficient = (CTSU_CORRECTION_1ST_STD_VAL << CTSU_SHIFT_AMOUNT) / + g_ctsu_correction_info.first_val; + + /* 2nd coefficient create */ + g_ctsu_correction_info.second_coefficient = ((uint32_t) second_std_val << CTSU_SHIFT_AMOUNT) / + g_ctsu_correction_info.second_val; + + g_ctsu_correction_info.status = CTSU_CORRECTION_COMPLETE; + } + else + { + g_ctsu_correction_info.status = CTSU_CORRECTION_ERROR; + } + } + else + { + g_ctsu_correction_info.status = CTSU_CORRECTION_ERROR; + } +#endif +} + +/*********************************************************************************************************************** + * ctsu_correction_measurement + ***********************************************************************************************************************/ +void ctsu_correction_measurement (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * data) +{ + uint16_t i; + uint32_t sum = 0; + + for (i = 0; i < CTSU_CORRECTION_AVERAGE; i++) + { +#if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + ctsu_transfer_configure(p_instance_ctrl); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + p_instance_ctrl->state = CTSU_STATE_SCANNING; + R_CTSU->CTSUCR0 |= 0x01; + while (p_instance_ctrl->state != CTSU_STATE_SCANNED) + { + } + +#if (BSP_FEATURE_CTSU_VERSION == 2) + sum += g_ctsu_correction_info.scanbuf; +#endif +#if (BSP_FEATURE_CTSU_VERSION == 1) + sum += g_ctsu_correction_info.scanbuf.sen; +#endif + } + + *data = (uint16_t) (sum / CTSU_CORRECTION_AVERAGE); +} + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + +/*********************************************************************************************************************** + * ctsu_correction_scan_start + ***********************************************************************************************************************/ +void ctsu_correction_scan_start (void) +{ + g_ctsu_temp_reg_ctsucra = R_CTSU->CTSUCRA; + + R_CTSU->CTSUCRA_b.MD0 = 1; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + + /* Setting time of measurement */ + g_ctsu_correction_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10); + g_ctsu_correction_info.suadj0 = (uint8_t) (R_CTSU->CTSUSUCLK0 & CTSU_SUADJ_MAX); + + if (g_ctsu_correction_info.scan_index < CTSU_CORRECTION_POINT_NUM) + { + /* Dummy setting */ + R_CTSU->CTSUCHACA = 1; + R_CTSU->CTSUCHACB = 0; + R_CTSU->CTSUCHTRCA = 0; + R_CTSU->CTSUCHTRCB = 0; + + /* Step3 : Measure by inputting each constant current from internal DAC to ICO. */ + R_CTSU->CTSUCRB_b.SSCNT = 0; + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCALIB_b.CCOCALIB = 1; + R_CTSU->CTSUCALIB_b.TSOC = 1; + + R_CTSU->CTSUCRA_b.SDPSEL = 0; + if (8 > g_ctsu_correction_info.scan_index) + { + R_CTSU->CTSUSUCLK0 = (uint16_t) (((g_ctsu_correction_info.scan_index + 1) * CTSU_CORRECTION_SUMULTI) - 1); + } + else + { + /* SUCARRY is required for greater than 10uA */ + R_CTSU->CTSUCRB_b.SSCNT = 3; + R_CTSU->CTSUCALIB_b.SUCARRY = 1; + R_CTSU->CTSUSUCLK0 = + (uint16_t) (((g_ctsu_correction_info.scan_index - 3) * CTSU_CORRECTION_SUMULTI) - 1); + } + + R_CTSU->CTSUCRA_b.SDPSEL = 1; + } + else + { + /* Step2-b : Measure the current input to the ICO by passing current through the external resistance. */ + /* The theoretical value of the current is 9.375uA. */ + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; + #if (CTSU_CFG_TEMP_CORRECTION_TS < 32) + R_CTSU->CTSUCHACA = (uint32_t) (1 << CTSU_CFG_TEMP_CORRECTION_TS); + R_CTSU->CTSUCHACB = 0; + #else + R_CTSU->CTSUCHACA = 0; + R_CTSU->CTSUCHACB = (uint32_t) (1 << (CTSU_CFG_TEMP_CORRECTION_TS - 32)); + #endif + R_CTSU->CTSUCRA_b.DCMODE = 1; + R_CTSU->CTSUCRA_b.DCBACK = 1; + R_CTSU->CTSUSO_b.SO = 0; + } +} + +/*********************************************************************************************************************** + * ctsu_correction_data_get + ***********************************************************************************************************************/ +fsp_err_t ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data) +{ + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; + #endif + uint32_t i; + uint32_t j; + uint16_t x0; + uint16_t x1; + uint16_t y0; + uint16_t y1; + uint16_t dac2vdc; + uint16_t dac_value; + uint32_t ref_value; + uint16_t c0; + uint16_t c1; + ctsu_data_t temp_avg_data = {0, 0}; + fsp_err_t err = FSP_SUCCESS; + + if (g_ctsu_correction_info.scan_index < CTSU_CORRECTION_POINT_NUM) + { + temp_avg_data.int_data = g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][g_ctsu_correction_info.scan_index]; + ctsu_moving_average(&temp_avg_data, *p_instance_ctrl->p_self_raw, 4); + g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][g_ctsu_correction_info.scan_index] = temp_avg_data.int_data; + g_ctsu_correction_info.scan_index++; + } + else + { + if (0 == g_ctsu_correction_info.ex_base_value) + { + g_ctsu_correction_info.ex_base_value = *p_instance_ctrl->p_self_raw; + g_ctsu_correction_info.update_counter = CTSU_CFG_TEMP_CORRECTION_TIME; + } + else + { + temp_avg_data.int_data = g_ctsu_correction_info.ex_base_value; + ctsu_moving_average(&temp_avg_data, *p_instance_ctrl->p_self_raw, 4); + g_ctsu_correction_info.ex_base_value = temp_avg_data.int_data; + } + + g_ctsu_correction_info.scan_index = 0; + g_ctsu_correction_info.update_counter++; + } + + /* Step4 : Calculate the coefficient between step2 and step3. */ + if (g_ctsu_correction_info.update_counter > CTSU_CFG_TEMP_CORRECTION_TIME) + { + // Theoretical value at VDC path measurement + x1 = + (uint16_t) (((uint32_t) CTSU_CORRECTION_STD_VAL << 9) / + g_ctsu_correction_info.error_rate[CTSU_RANGE_160UA]); + + j = x1 / CTSU_CORRECTION_STD_UNIT; // upper index of theoretical value + + x0 = (uint16_t) (CTSU_CORRECTION_STD_UNIT * j); // lower side Theoretical value + y0 = g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][j - 1]; + y1 = g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][j]; + + // Calculate CCODAC path value on VDC path current by linear interpolation + dac2vdc = (uint16_t) (y0 + ((uint32_t) (y1 - y0) * (x1 - x0)) / CTSU_CORRECTION_STD_UNIT); + + // calculate VDC path conversion ratio + dac2vdc = + (uint16_t) (((int32_t) g_ctsu_correction_info.base_value[CTSU_RANGE_160UA] << + CTSU_CORRECTION_DIV_PRECISION) / + dac2vdc); + + // Correct CCODAC path value using conversion ratio, and make correction coefficients + for (j = 0; j < CTSU_CORRECTION_POINT_NUM; j++) + { + dac_value = + (uint16_t) ((uint32_t) (g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][j] * dac2vdc) >> + CTSU_CORRECTION_DIV_PRECISION); + ref_value = (CTSU_CORRECTION_STD_UNIT * (j + 1)); + + g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][j] = dac_value; + g_ctsu_correction_info.coef[CTSU_RANGE_160UA][j] = + (uint16_t) ((ref_value << CTSU_CORRECTION_DIV_PRECISION) / dac_value); + } + + // expand correction range + c0 = g_ctsu_correction_info.coef[CTSU_RANGE_160UA][0]; + c1 = g_ctsu_correction_info.coef[CTSU_RANGE_160UA][1]; + x0 = g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][0]; + x1 = g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][1]; + + g_ctsu_correction_info.coef[CTSU_RANGE_160UA][0] = + (uint16_t) (c1 - ((uint32_t) (c1 - c0) * x1) / (x1 - x0)); + g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][0] = 0; + + c0 = g_ctsu_correction_info.coef[CTSU_RANGE_160UA][10]; + c1 = g_ctsu_correction_info.coef[CTSU_RANGE_160UA][11]; + x0 = g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][10]; + x1 = g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][11]; + + g_ctsu_correction_info.coef[CTSU_RANGE_160UA][11] = + (uint16_t) (c1 + ((uint32_t) (c1 - c0) * (CTSU_COUNT_MAX - x1)) / (x1 - x0)); + g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][11] = CTSU_COUNT_MAX; + + for (j = 1; j < (CTSU_CORRECTION_POINT_NUM - 1); j++) + { + for (i = 0; i < (CTSU_RANGE_NUM - 1); i++) + { + g_ctsu_correction_info.dac_value[i][j] = + (uint16_t) (((uint32_t) g_ctsu_correction_info.dac_value[CTSU_RANGE_160UA][j] * + (uint32_t) g_ctsu_correction_info.range_ratio[i]) >> CTSU_SHIFT_AMOUNT); + g_ctsu_correction_info.coef[i][j] = + (uint16_t) (((uint32_t) g_ctsu_correction_info.coef[CTSU_RANGE_160UA][j] * + (uint32_t) g_ctsu_correction_info.range_ratio[i]) >> CTSU_SHIFT_AMOUNT); + } + } + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + ctsu_auto_correction_register_set(p_instance_ctrl); + #endif + + g_ctsu_correction_info.update_counter = 0; + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + err = ctsu_correction_calib_rtrim(p_instance_ctrl, p_data); + if (FSP_ERR_ALREADY_OPEN != err) + { + p_adc->p_api->close(p_adc->p_ctrl); + } + + if (FSP_SUCCESS != err) + { + err = FSP_ERR_ABORTED; + } + #endif + } + else + { + /* Indicates that ADC measurement was not performed. */ + *p_data = CTSU_COUNT_MAX; + } + + R_CTSU->CTSUCRA = g_ctsu_temp_reg_ctsucra; + + return err; +} + + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + +/*********************************************************************************************************************** + * ctsu_correction_calib_rtrim + ***********************************************************************************************************************/ +fsp_err_t ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data) +{ + adc_status_t status; + adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; + uint16_t i; + uint16_t adctdr_result; + uint16_t adctdr_ave; + uint32_t adctdr_sum; + int16_t diff; + int16_t dir = 0; + uint16_t comp = 0; + fsp_err_t err; + + /* Initialize ADC for CTSU TSCAP */ + err = p_adc->p_api->open(p_adc->p_ctrl, p_adc->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = p_adc->p_api->scanCfg(p_adc->p_ctrl, p_adc->p_channel_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if (0 == BSP_FEATURE_ADC_D_IS_AVAILABLE) + R_ADC0->ADSSTRL = CTSU_CALIB_ADSSTRL; + #endif + + /* Self single scan mode */ + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.MD0 = 0; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + + /* Set Channel */ + #if (CTSU_CFG_TEMP_CORRECTION_TS < 32) + R_CTSU->CTSUCHACA |= (uint32_t) (1 << CTSU_CFG_TEMP_CORRECTION_TS); + R_CTSU->CTSUCHTRCA &= (uint32_t) ~(1 << CTSU_CFG_TEMP_CORRECTION_TS); + #else + R_CTSU->CTSUCHACB |= (uint32_t) (1 << (CTSU_CFG_TEMP_CORRECTION_TS - 32)); + R_CTSU->CTSUCHTRCB &= (uint32_t) ~(1 << (CTSU_CFG_TEMP_CORRECTION_TS - 32)); + #endif + R_CTSU->CTSUMCH0 = CTSU_CFG_TEMP_CORRECTION_TS; + + /* 150uA current measurement */ + R_CTSU->CTSUCRA_b.DCMODE = 1; + R_CTSU->CTSUCRA_b.DCBACK = 1; + R_CTSU->CTSUSO_b.SO = CTSU_CALIB_CTSUSO; + R_CTSU->CTSUCRA_b.CSW = 0; + R_CTSU->CTSUCALIB_b.DRV = 1; + + /* ADC scan */ + while (!comp) + { + adctdr_sum = 0; + for (i = 0; i < CTSU_CALIB_AVERAGE_TIME; i++) + { + /* Software trigger start scan */ + err = p_adc->p_api->scanStart(p_adc->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Wait for conversion to complete. */ + status.state = ADC_STATE_SCAN_IN_PROGRESS; + while (ADC_STATE_SCAN_IN_PROGRESS == status.state) + { + err = p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + /* Read A/D data then scan normal end */ + #if (1 == BSP_FEATURE_ADC_D_IS_AVAILABLE) + err = p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_TSCAP_VOLT, &adctdr_result); + #else + err = p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &adctdr_result); + #endif + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + adctdr_sum += adctdr_result; + } + + adctdr_ave = (uint16_t) ((adctdr_sum * 10) / CTSU_CALIB_AVERAGE_TIME); + diff = (int16_t) ((adctdr_ave - CTSU_CALIB_REF) / 10); + + /* The change unit of the voltage by the RTRIM register is about 4mV (4096 * 4) = 16.384 */ + if (diff > CTSU_CALIB_THRESHOLD) + { + if (0 <= dir) + { + R_CTSUTRIM->CTSUTRIMA_b.RTRIM = (uint8_t) (R_CTSUTRIM->CTSUTRIMA_b.RTRIM + 1); + dir = 1; + } + else + { + comp = 1; + } + } + else if (diff < -(CTSU_CALIB_THRESHOLD)) + { + if (0 >= dir) + { + R_CTSUTRIM->CTSUTRIMA_b.RTRIM = (uint8_t) (R_CTSUTRIM->CTSUTRIMA_b.RTRIM - 1); + dir = -1; + } + else + { + comp = 1; + } + } + else + { + comp = 1; + } + } + + /* Restore register settings */ + R_CTSU->CTSUCALIB_b.DRV = 0; + R_CTSU->CTSUCRA_b.CSW = 1; + R_CTSU->CTSUCRA_b.DCMODE = 0; + R_CTSU->CTSUCRA_b.DCBACK = 0; + + /* Indicates that ADC measurement was performed */ + *p_data = R_CTSUTRIM->CTSUTRIMA_b.RTRIM; + + /* Close ADC for CTSU TSCAP */ + p_adc->p_api->close(p_adc->p_ctrl); + + return err; +} + + #endif + #endif +#endif + +#if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) + +/*********************************************************************************************************************** + * ctsu_correction_calc + ***********************************************************************************************************************/ +void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_correction_calc_t * p_calc) +{ + uint32_t answer = 0; + uint32_t cmp_data; + uint8_t calc_flag = 0; + #if (BSP_FEATURE_CTSU_VERSION == 1) + uint16_t diff_val; + int32_t diff_coefficient; + int32_t mul_diffcoff_diff1valsval; + uint32_t mul_coff1val_diffcorr; + uint16_t coefficient; + #endif + #if (BSP_FEATURE_CTSU_VERSION == 2) + int32_t y0 = 0; + int32_t y1 = 0; + int32_t x0 = 0; + int32_t x1 = 0; + uint16_t i; + uint32_t scaled_data; + uint32_t coef; + bool flag; + #endif + + #if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_NUM_CFC != 0) + if ((CTSU_CORRECTION_COMPLETE == g_ctsu_correction_info.status) || + (CTSU_CORRECTION_COMPLETE == g_ctsu_corrcfc_info.status)) + { + calc_flag = 1; + } + + #else + if (CTSU_CORRECTION_COMPLETE == g_ctsu_correction_info.status) + { + calc_flag = 1; + } + #endif + #endif + #if (BSP_FEATURE_CTSU_VERSION == 1) + if (CTSU_CORRECTION_COMPLETE == g_ctsu_correction_info.status) + { + calc_flag = 1; + } + #endif + + if (calc_flag) + { + #if (BSP_FEATURE_CTSU_VERSION == 1) + + /* Since the correction coefficient table is created with the recommended measurement time, */ + /* If the measurement time is different, adjust the value level. */ + cmp_data = (uint32_t) ((raw_data * g_ctsu_correction_info.ctsu_clock) / + (uint32_t) ((p_calc->snum + 1) * (p_calc->sdpa + 1))); + + /* g_mul_coff1val_diffcorr - g_diff_cofficient * (g_ctsu_correction_info.first_val - raw_data) */ + /* coefficient= ------------------------------------------------------------------------------------------ */ + /* g_diff_correct_val */ + /* */ + + diff_val = (uint16_t) (g_ctsu_correction_info.first_val - g_ctsu_correction_info.second_val); + + /* Get multiplication of g_ctsu_correction_info.first_coefficient and difference of Correction value */ + mul_coff1val_diffcorr = g_ctsu_correction_info.first_coefficient * diff_val; + + /* Get difference of Correction coefficient */ + diff_coefficient = + (int32_t) (g_ctsu_correction_info.first_coefficient - g_ctsu_correction_info.second_coefficient); + + /* Get multiplication of g_diff_cofficient and (g_ctsu_correction_info.first_val - raw_data_coff) */ + mul_diffcoff_diff1valsval = (diff_coefficient * (int32_t) (g_ctsu_correction_info.first_val - cmp_data)); + + /* Get correction coefficient of scan data */ + coefficient = (uint16_t) (((int32_t) mul_coff1val_diffcorr - mul_diffcoff_diff1valsval) / diff_val); + + /* Get output count data */ + answer = (uint32_t) (((uint32_t) raw_data * (uint32_t) coefficient) >> CTSU_SHIFT_AMOUNT); + #endif + #if (BSP_FEATURE_CTSU_VERSION == 2) + + // Normalization measurement data to recommended measurement timed + cmp_data = (uint32_t) raw_data * (CTSU_SNUM_RECOMMEND + 1); + + /* searching for upper index of measurement value containing raw_data by scaled measurement value */ + /* if without scaling, should use binary search */ + /* index search must be stopped when i = 11 because dac_value[11] = 65535 */ + + if (CTSU_MODE_MUTUAL_CFC_SCAN != p_calc->md) + { + for (i = 1; i < CTSU_CORRECTION_POINT_NUM - 1; i++) + { + scaled_data = (uint32_t) (g_ctsu_correction_info.dac_value[p_calc->range][i]) * (p_calc->snum + 1); + if (scaled_data > cmp_data) + { + break; + } + } + + x0 = g_ctsu_correction_info.dac_value[p_calc->range][i - 1]; + x1 = g_ctsu_correction_info.dac_value[p_calc->range][i]; + + // coef + y0 = g_ctsu_correction_info.coef[p_calc->range][i - 1]; + y1 = g_ctsu_correction_info.coef[p_calc->range][i]; + + x0 = (x0 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1); + x1 = (x1 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1); + { + coef = (uint32_t) (((y1 - y0) * (raw_data - x0)) / (x1 - x0) + y0); + flag = false; + + if (p_calc->snum < CTSU_SNUM_RECOMMEND) // 1st condition + { + if (raw_data < coef) + { + answer = (coef >> CTSU_CORRECTION_DIV_PRECISION) * raw_data; + } + else + { + answer = coef * (raw_data >> CTSU_CORRECTION_DIV_PRECISION); + } + + if (answer > CTSU_COUNT_MAX) // 2nd condition + { + flag = true; + answer = CTSU_COUNT_MAX; + g_ctsu_correction_info.calculation_error = 1; + } + } + + if (false == flag) + { + answer = (uint32_t) (coef * raw_data) >> CTSU_CORRECTION_DIV_PRECISION; + } + } + } + + #if (CTSU_CFG_NUM_CFC != 0) + else + { + i = 0; + while (1) + { + if ((cmp_data < g_ctsu_corrcfc_info.dac_value[p_calc->cfc][i]) || ((CTSU_CORRCFC_POINT_NUM - 1) == i)) + { + y0 = g_ctsu_corrcfc_info.ref_value[p_calc->cfc][i]; + x0 = g_ctsu_corrcfc_info.dac_value[p_calc->cfc][i]; + if (0 == i) + { + x1 = 0; + y1 = 0; + } + else + { + x1 = g_ctsu_corrcfc_info.dac_value[p_calc->cfc][i - 1]; + y1 = g_ctsu_corrcfc_info.ref_value[p_calc->cfc][i - 1]; + } + + break; + } + + i++; + } + + if (CTSU_SNUM_RECOMMEND != p_calc->snum) + { + x0 = ((x0 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + y0 = ((y0 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + x1 = ((x1 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + y1 = ((y1 * (p_calc->snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + } + + answer = (uint32_t) (y0 - (((y0 - y1) * (x0 - raw_data)) / (x0 - x1))); + } + #endif + #endif + + /* Value Overflow Check */ + if (CTSU_COUNT_MAX < answer) + { + *correction_data = CTSU_COUNT_MAX; + g_ctsu_correction_info.calculation_error = 1; + } + else + { + *correction_data = (uint16_t) answer; + } + } + else + { + *correction_data = raw_data; + } +} + +#endif + +/*********************************************************************************************************************** + * ctsu_correction_exec + ***********************************************************************************************************************/ +void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ +#if (BSP_FEATURE_CTSU_VERSION == 1) + ctsu_correction_ctsu1_exec(p_instance_ctrl); +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + ctsu_correction_ctsu2_exec(p_instance_ctrl); +#endif +} + +#if (BSP_FEATURE_CTSU_VERSION == 1) +void ctsu_correction_ctsu1_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint16_t element_id; + + ctsu_correction_calc_t calc; + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + ctsu_data_t * p_self_data; + ctsu_data_t average_self = {0, 0}; + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + ctsu_data_t * p_pri_data; + ctsu_data_t * p_snd_data; + ctsu_data_t average_pri = {0, 0}; + ctsu_data_t average_snd = {0, 0}; + #endif + + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + calc.snum = (p_instance_ctrl->p_ctsuwr[element_id].ctsuso0 >> 10) & CTSU_SNUM_MAX; + calc.sdpa = (p_instance_ctrl->p_ctsuwr[element_id].ctsuso1 >> 8) & CTSU_SDPA_MAX; + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + p_self_data = (p_instance_ctrl->p_self_data + element_id); + average_self = *p_self_data; + ctsu_correction_calc((p_instance_ctrl->p_self_corr + element_id), + (p_instance_ctrl->p_self_raw + element_id)->sen, + &calc); + p_self_data->int_data = *(p_instance_ctrl->p_self_corr + element_id); + if (1 < p_instance_ctrl->average) + { + ctsu_moving_average(&average_self, p_self_data->int_data, p_instance_ctrl->average); + *p_self_data = average_self; + } + } + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + p_pri_data = (p_instance_ctrl->p_mutual_pri_data + element_id); + p_snd_data = (p_instance_ctrl->p_mutual_snd_data + element_id); + if (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md) + { + average_pri = *p_pri_data; + average_snd = *p_snd_data; + ctsu_correction_calc((p_instance_ctrl->p_mutual_pri_corr + element_id), + (p_instance_ctrl->p_mutual_raw + element_id)->pri_sen, &calc); + ctsu_correction_calc((p_instance_ctrl->p_mutual_snd_corr + element_id), + (p_instance_ctrl->p_mutual_raw + element_id)->snd_sen, &calc); + p_pri_data->int_data = *(p_instance_ctrl->p_mutual_pri_corr + element_id); + p_snd_data->int_data = *(p_instance_ctrl->p_mutual_snd_corr + element_id); + + if (1 < p_instance_ctrl->average) + { + ctsu_moving_average(&average_pri, p_pri_data->int_data, p_instance_ctrl->average); + ctsu_moving_average(&average_snd, p_snd_data->int_data, p_instance_ctrl->average); + *p_pri_data = average_pri; + *p_snd_data = average_snd; + } + } + #endif + } +} + +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) +void ctsu_correction_ctsu2_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint16_t i; + uint16_t element_id; + uint16_t majority_mode_element_num; + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 0) + ctsu_correction_calc_t calc; + uint32_t ctsuso; + uint32_t snum; + uint32_t so_value[CTSU_CFG_NUM_SUMULTI]; + #else + uint16_t j; + #endif + + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + uint16_t * p_self_corr; + uint16_t * p_self_mfc; + ctsu_data_t * p_self_data; + ctsu_data_t average_self; + #endif + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + uint16_t * p_pri_corr; + uint16_t * p_snd_corr; + uint16_t * p_pri_mfc; + uint16_t * p_snd_mfc; + ctsu_data_t * p_pri_data; + ctsu_data_t * p_snd_data; + ctsu_data_t average_pri; + ctsu_data_t average_snd; + + #if (CTSU_CFG_NUM_CFC != 0) + uint8_t ts_id; + uint8_t table_id; + uint8_t cfc_ts_table[CTSU_CFG_NUM_CFC]; + uint16_t offset = 0; + uint16_t cfc_id = 0; + uint16_t num_rx = 0; + + /* By inspection, calc.cfc is only used when calc.md == CTSU_MODE_MUTUAL_CFC_SCAN. It is initialized in this case. + * However, GCC expects calc.cfc to be initialized before calling ctsu_correction_calc regardless of calc.md to + * avoid the warning -Werror=maybe-uninitialized. */ + calc.cfc = 0; + + /* Create CFC-Rx table in ascending order at this instance */ + for (ts_id = 0; ts_id < CTSU_CORRCFC_TS_MAX; ts_id++) + { + if (1 == ((p_instance_ctrl->cfc_rx_bitmap >> ts_id) & 1)) + { + for (table_id = 0; table_id < CTSU_CFG_NUM_CFC; table_id++) + { + if (g_ctsu_corrcfc_info.ts_table[table_id] == ts_id) + { + cfc_ts_table[cfc_id] = table_id; + cfc_id++; + } + } + } + } + #endif + #endif + #if (CTSU_CFG_MAJORITY_MODE & CTSU_JUDGEMENT_MAJORITY_MODE) + if (1 == p_instance_ctrl->p_ctsu_cfg->majority_mode) + { + majority_mode_element_num = CTSU_MAJORITY_MODE_ELEMENTS; + } + else + #endif + { + majority_mode_element_num = 1; + } + + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 0) + calc.range = p_instance_ctrl->range; + calc.md = p_instance_ctrl->md; + #endif + + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 0) + calc.snum = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI)].ctsuso >> 10) & CTSU_SNUM_MAX; + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + ctsuso = + (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI) + i].ctsuso & CTSU_TUNING_MAX); + snum = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI)].ctsuso >> 10) & + CTSU_SNUM_MAX; + so_value[i] = (ctsuso * CTSU_CORRECTION_OFFSET_UNIT * (snum + 1)) >> calc.range; + } + #endif + + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) + p_self_corr = p_instance_ctrl->p_self_corr + (element_id * CTSU_CFG_NUM_SUMULTI); + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) + ctsu_correction_calc(&p_self_corr[i], + p_instance_ctrl->p_self_raw[(element_id * CTSU_CFG_NUM_SUMULTI) + i], &calc); + #else + *(p_self_corr + i) = + p_instance_ctrl->p_self_raw[(element_id * CTSU_CFG_NUM_SUMULTI) + i]; + #endif + } + + for (i = 0; i < majority_mode_element_num; i++) + { + if (0 != p_instance_ctrl->average) + { + p_self_data = (p_instance_ctrl->p_self_data + (element_id * majority_mode_element_num) + i); + + /* Store last moving averaged data */ + average_self.int_data = p_self_data->int_data; + average_self.decimal_point_data = p_self_data->decimal_point_data; + #if (CTSU_CFG_MAJORITY_MODE & CTSU_JUDGEMENT_MAJORITY_MODE) + if (p_instance_ctrl->p_ctsu_cfg->majority_mode == 1) + { + /* Skip the ctsu_correction_multi at Software JMM */ + p_self_data->int_data = p_self_corr[i]; + } + else + #endif + { + p_self_mfc = (p_instance_ctrl->p_self_mfc + (element_id * CTSU_CFG_NUM_SUMULTI)); + + /* Matching values */ + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 0) + ctsu_correction_freq(p_self_corr, so_value, p_self_mfc); + #else + for (j = 0; j < CTSU_CFG_NUM_SUMULTI; j++) + { + p_self_mfc[j] = p_self_corr[j]; + } + #endif + *(p_instance_ctrl->p_selected_freq_self + element_id) = + ctsu_correction_multi(p_self_mfc, NULL, &(p_self_data->int_data), NULL); + } + + /* Update moving averaged data */ + ctsu_moving_average(&average_self, p_self_data->int_data, p_instance_ctrl->average); + *p_self_data = average_self; + } + } + } + else if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->md) + { + p_self_data = (p_instance_ctrl->p_self_data + (element_id * CTSU_CFG_NUM_SUMULTI)); + + /* Store last moving averaged data */ + average_self = *p_self_data; + + /* Correction */ + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) + ctsu_correction_calc(&(p_self_data->int_data), p_instance_ctrl->p_self_raw[element_id], &calc); + #else + p_self_data->int_data = p_instance_ctrl->p_self_raw[element_id]; + #endif + + /* Update moving averaged data */ + if (1 < p_instance_ctrl->average) + { + ctsu_moving_average(&average_self, p_self_data->int_data, p_instance_ctrl->average); + *p_self_data = average_self; + } + #endif + } + else if (CTSU_MODE_MUTUAL_FULL_SCAN == p_instance_ctrl->md) + { + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + p_pri_corr = p_instance_ctrl->p_mutual_pri_corr + (element_id * CTSU_CFG_NUM_SUMULTI); + p_snd_corr = p_instance_ctrl->p_mutual_snd_corr + (element_id * CTSU_CFG_NUM_SUMULTI); + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + if ((0 == p_instance_ctrl->ctsuchtrc0) && (0 == p_instance_ctrl->ctsuchtrc1) && + (0 == p_instance_ctrl->ctsuchtrc2) && (0 == p_instance_ctrl->ctsuchtrc3) && + (0 == p_instance_ctrl->ctsuchtrc4)) + { + /* Serial tuning Phase1 */ + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) + ctsu_correction_calc(&p_instance_ctrl->p_mutual_pri_corr[element_id], + p_instance_ctrl->p_mutual_raw[element_id * CTSU_CFG_NUM_SUMULTI], + &calc); + #else + p_instance_ctrl->p_mutual_pri_corr[element_id] = + p_instance_ctrl->p_mutual_raw[element_id * CTSU_CFG_NUM_SUMULTI]; + #endif + break; + } + } + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) + ctsu_correction_calc(&p_pri_corr[i], + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2)], + &calc); + #else + p_pri_corr[i] = + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2)]; + #endif + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) + ctsu_correction_calc(&p_snd_corr[i], + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2) + 1], + &calc); + #else + p_snd_corr[i] = + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2) + 1]; + #endif + } + + for (i = 0; i < majority_mode_element_num; i++) + { + if (true == p_instance_ctrl->serial_tuning_enable) + { + /* Serial Tuning Phase1 */ + if ((0 == p_instance_ctrl->ctsuchtrc0) && (0 == p_instance_ctrl->ctsuchtrc1) && + (0 == p_instance_ctrl->ctsuchtrc2) && (0 == p_instance_ctrl->ctsuchtrc3) && + (0 == p_instance_ctrl->ctsuchtrc4)) + { + break; + } + } + + if (0 != p_instance_ctrl->average) + { + p_pri_data = (p_instance_ctrl->p_mutual_pri_data + (element_id * majority_mode_element_num) + i); + p_snd_data = (p_instance_ctrl->p_mutual_snd_data + (element_id * majority_mode_element_num) + i); + + /* Store last moving averaged data */ + average_pri = *p_pri_data; + average_snd = *p_snd_data; + #if (CTSU_CFG_MAJORITY_MODE & CTSU_JUDGEMENT_MAJORITY_MODE) + if (p_instance_ctrl->p_ctsu_cfg->majority_mode == 1) + { + /* Skip the ctsu_correction_multi at Software JMM */ + p_pri_data->int_data = p_pri_corr[i]; + p_snd_data->int_data = p_snd_corr[i]; + } + else + #endif + { + p_pri_mfc = (p_instance_ctrl->p_mutual_pri_mfc + (element_id * CTSU_CFG_NUM_SUMULTI)); + p_snd_mfc = (p_instance_ctrl->p_mutual_snd_mfc + (element_id * CTSU_CFG_NUM_SUMULTI)); + + /* Matching values */ + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 0) + ctsu_correction_freq(p_pri_corr, so_value, p_pri_mfc); + ctsu_correction_freq(p_snd_corr, so_value, p_snd_mfc); + #else + for (j = 0; j < CTSU_CFG_NUM_SUMULTI; j++) + { + p_pri_mfc[j] = p_pri_corr[j]; + p_snd_mfc[j] = p_snd_corr[j]; + } + #endif + *(p_instance_ctrl->p_selected_freq_mutual + element_id) = + ctsu_correction_multi(p_pri_mfc, p_snd_mfc, &(p_pri_data->int_data), + &(p_snd_data->int_data)); + } + + /* Update moving averaged data */ + ctsu_moving_average(&average_pri, p_pri_data->int_data, p_instance_ctrl->average); + *p_pri_data = average_pri; + ctsu_moving_average(&average_snd, p_snd_data->int_data, p_instance_ctrl->average); + *p_snd_data = average_snd; + } + } + #endif + } + else if (CTSU_MODE_MUTUAL_CFC_SCAN == p_instance_ctrl->md) + { + #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) + #if (CTSU_CFG_NUM_CFC != 0) + if (CTSU_MODE_MUTUAL_CFC_SCAN == p_instance_ctrl->md) + { + num_rx = p_instance_ctrl->p_ctsu_cfg->num_rx; + cfc_id = (uint16_t) (element_id % num_rx); + if (0 == cfc_id) + { + if (0 == element_id) + { + offset = 0; + } + else + { + offset = (uint16_t) (offset + (num_rx * CTSU_MUTUAL_BUF_SIZE)); + } + } + } + + calc.cfc = cfc_ts_table[cfc_id]; + + p_pri_corr = p_instance_ctrl->p_mutual_pri_corr + (element_id * CTSU_CFG_NUM_SUMULTI); + p_snd_corr = p_instance_ctrl->p_mutual_snd_corr + (element_id * CTSU_CFG_NUM_SUMULTI); + + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + ctsu_correction_calc(&p_pri_corr[i], + p_instance_ctrl->p_mutual_raw[offset + cfc_id + (num_rx * i * 2)], + &calc); + + ctsu_correction_calc(&p_snd_corr[i], + p_instance_ctrl->p_mutual_raw[offset + cfc_id + (num_rx * i * 2) + num_rx], &calc); + } + + if (0 != p_instance_ctrl->average) + { + p_pri_data = (p_instance_ctrl->p_mutual_pri_data + element_id); + p_snd_data = (p_instance_ctrl->p_mutual_snd_data + element_id); + + /* Store last moving averaged data */ + average_pri = *p_pri_data; + average_snd = *p_snd_data; + + p_pri_mfc = (p_instance_ctrl->p_mutual_pri_mfc + (element_id * CTSU_CFG_NUM_SUMULTI)); + p_snd_mfc = (p_instance_ctrl->p_mutual_snd_mfc + (element_id * CTSU_CFG_NUM_SUMULTI)); + + /* Matching values */ + ctsu_correction_freq(p_pri_corr, so_value, p_pri_mfc); + ctsu_correction_freq(p_snd_corr, so_value, p_snd_mfc); + *(p_instance_ctrl->p_selected_freq_mutual + element_id) = + ctsu_correction_multi(p_pri_mfc, p_snd_mfc, &(p_pri_data->int_data), &(p_snd_data->int_data)); + + /* Update moving averaged data */ + ctsu_moving_average(&average_pri, p_pri_data->int_data, p_instance_ctrl->average); + *p_pri_data = average_pri; + ctsu_moving_average(&average_snd, p_snd_data->int_data, p_instance_ctrl->average); + *p_snd_data = average_snd; + } + #endif + #endif + } + else + { + } + } +} + +#endif +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 0) + +/*********************************************************************************************************************** + * ctsu_correction_freq + ***********************************************************************************************************************/ +void ctsu_correction_freq (uint16_t * p_corr, uint32_t * p_so_value, uint16_t * p_mfc) +{ + uint32_t i; + uint32_t sumulti[CTSU_CFG_NUM_SUMULTI]; + int32_t calc[CTSU_CFG_NUM_SUMULTI]; + uint32_t total; + + sumulti[0] = CTSU_CFG_SUMULTI0 + 1; + #if CTSU_CFG_NUM_SUMULTI >= 2 + sumulti[1] = CTSU_CFG_SUMULTI1 + 1; + #endif + #if CTSU_CFG_NUM_SUMULTI >= 3 + sumulti[2] = CTSU_CFG_SUMULTI2 + 1; + #endif + + p_mfc[0] = p_corr[0]; + + for (i = 1; i < CTSU_CFG_NUM_SUMULTI; i++) + { + total = ((p_corr[i] * (CTSU_SNUM_RECOMMEND + 1) + p_so_value[i]) * sumulti[0]) / sumulti[i]; + + if (total > p_so_value[0]) + { + calc[i] = (int32_t) ((total - p_so_value[0]) / (CTSU_SNUM_RECOMMEND + 1)); + if (calc[i] < CTSU_COUNT_MAX) + { + p_mfc[i] = (uint16_t) calc[i]; + } + else + { + /* over flow */ + p_mfc[i] = CTSU_COUNT_MAX; + } + } + else + { + /* under flow */ + calc[i] = 0; + p_mfc[i] = 0; + } + } +} + + #endif + +/*********************************************************************************************************************** + * ctsu_correction_multi + ***********************************************************************************************************************/ +uint8_t ctsu_correction_multi (uint16_t * p_pri_mfc, uint16_t * p_snd_mfc, uint16_t * p_pri_data, uint16_t * p_snd_data) +{ + uint8_t selected_freq; + int32_t add_pri; + int32_t add_snd; + #if CTSU_CFG_NUM_SUMULTI >= 3 + uint32_t i; + int32_t pri_calc[CTSU_CFG_NUM_SUMULTI]; + int32_t snd_calc[CTSU_CFG_NUM_SUMULTI]; + int32_t diff[CTSU_CFG_NUM_SUMULTI]; + #endif + + #if CTSU_CFG_NUM_SUMULTI == 1 + add_pri = p_pri_mfc[0]; + if (NULL != p_snd_mfc) + { + add_snd = p_snd_mfc[0]; + } + #endif + #if CTSU_CFG_NUM_SUMULTI == 2 + add_pri = p_pri_mfc[0] + p_pri_mfc[1]; + if (NULL != p_snd_mfc) + { + add_snd = p_snd_mfc[0] + p_snd_mfc[1]; + } + #endif + #if CTSU_CFG_NUM_SUMULTI >= 3 + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + pri_calc[i] = (int32_t) p_pri_mfc[i]; + if (NULL == p_snd_mfc) + { + snd_calc[i] = 0; + } + else + { + snd_calc[i] = (int32_t) p_snd_mfc[i]; + } + } + + diff[0] = (snd_calc[1] - pri_calc[1]) - (snd_calc[0] - pri_calc[0]); + diff[1] = (snd_calc[2] - pri_calc[2]) - (snd_calc[0] - pri_calc[0]); + diff[2] = (snd_calc[2] - pri_calc[2]) - (snd_calc[1] - pri_calc[1]); + + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + if (diff[i] < 0) + { + diff[i] = -diff[i]; + } + } + + /* Normally select freq0 and freq1 addition */ + /* If the following conditions are false, it is estimated to be a noise environment. */ + /* Compare with the combination with the other frequency difference (including margin). */ + if ((diff[0] < (diff[1] * 2)) && (diff[0] < ((diff[2] * 3) / 2))) + { + add_pri = pri_calc[0] + pri_calc[1]; + add_snd = snd_calc[0] + snd_calc[1]; + + selected_freq = 0x3; + } + else + { + if (diff[1] < diff[2]) + { + add_pri = pri_calc[0] + pri_calc[2]; + add_snd = snd_calc[0] + snd_calc[2]; + + selected_freq = 0x5; + } + else + { + add_pri = pri_calc[1] + pri_calc[2]; + add_snd = snd_calc[1] + snd_calc[2]; + + selected_freq = 0x6; + } + } + #endif + + if (CTSU_COUNT_MAX < add_pri) + { + *p_pri_data = CTSU_COUNT_MAX; + } + else + { + *p_pri_data = (uint16_t) add_pri; + } + + if (NULL != p_snd_data) + { + if (CTSU_COUNT_MAX < add_snd) + { + *p_snd_data = CTSU_COUNT_MAX; + } + else + { + *p_snd_data = (uint16_t) add_snd; + } + } + + return selected_freq; +} + + #if (CTSU_CFG_NUM_CFC != 0) + +/*********************************************************************************************************************** + * ctsu_corrcfc_process + ***********************************************************************************************************************/ +void ctsu_corrcfc_process (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint8_t i; + uint8_t j; + uint8_t ts_id; + uint8_t index; + uint64_t new_bitmap; + ctsu_cfg_t const * p_cfg; + uint16_t base_value; + uint16_t base_conv_dac; + int32_t x0; + int32_t x1; + int32_t y0; + + g_ctsu_corrcfc_info.status = CTSU_CORRECTION_RUN; + + p_cfg = p_instance_ctrl->p_ctsu_cfg; + index = g_ctsu_corrcfc_info.index; + + /* Get CFC-Rx bitmap at this instance. */ + p_instance_ctrl->cfc_rx_bitmap = + ((uint64_t) (p_cfg->ctsuchac0 & (~p_cfg->ctsuchtrc0)) | + ((uint64_t) (p_cfg->ctsuchac1 & (~p_cfg->ctsuchtrc1)) << (CTSU_CORRCFC_SHIFT8)) | + ((uint64_t) (p_cfg->ctsuchac2 & (~p_cfg->ctsuchtrc2)) << (CTSU_CORRCFC_SHIFT8 * 2)) | + ((uint64_t) (p_cfg->ctsuchac3 & (~p_cfg->ctsuchtrc3)) << (CTSU_CORRCFC_SHIFT8 * 3)) | + ((uint64_t) (p_cfg->ctsuchac4 & (~p_cfg->ctsuchtrc4)) << (CTSU_CORRCFC_SHIFT8 * 4))); + + /* Get RX bitmap at this correction. */ + new_bitmap = p_instance_ctrl->cfc_rx_bitmap & (~g_ctsu_corrcfc_info.stored_rx_bitmap); + + /* Get TS id and number of TS in this instance. */ + g_ctsu_corrcfc_info.num_ts = 0; + for (ts_id = 0; ts_id < CTSU_CORRCFC_TS_MAX; ts_id++) + { + if (1 == ((new_bitmap >> ts_id) & 1)) + { + g_ctsu_corrcfc_info.ts_table[index + g_ctsu_corrcfc_info.num_ts] = ts_id; + g_ctsu_corrcfc_info.num_ts++; + } + } + + /* Add the bitmap of this instance to the entire CFC correction information. */ + g_ctsu_corrcfc_info.stored_rx_bitmap |= p_instance_ctrl->cfc_rx_bitmap; + + /* Write Channel setting */ + R_CTSU->CTSUCHAC0 = (uint8_t) (new_bitmap); + R_CTSU->CTSUCHAC1 = (uint8_t) (new_bitmap >> (CTSU_CORRCFC_SHIFT8)); + R_CTSU->CTSUCHAC2 = (uint8_t) (new_bitmap >> (CTSU_CORRCFC_SHIFT8 * 2)); + R_CTSU->CTSUCHAC3 = (uint8_t) (new_bitmap >> (CTSU_CORRCFC_SHIFT8 * 3)); + R_CTSU->CTSUCHAC4 = (uint8_t) (new_bitmap >> (CTSU_CORRCFC_SHIFT8 * 4)); + + /* Set register of CFC self mode */ + R_CTSU->CTSUCRA_b.MD0 = 1; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 1; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + + /* Set time of measurement */ + g_ctsu_corrcfc_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10); + + /* Step1 : Measure the current input to the CFC-ICO by passing bias current. */ + /* The theoretical value of the current is 6uA. */ + ctsu_corrcfc_measurement(p_instance_ctrl, &g_ctsu_corrcfc_info.base_value[index], 1); + + /* Step2 : Measure by inputting each constant current from internal DAC to CFC-ICO. */ + R_CTSU->CTSUCRB_b.SSCNT = 0; + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCALIB_b.CFCMODE = 1; + + for (j = 0; j < CTSU_CORRCFC_POINT_NUM; j++) + { + R_CTSU->CTSUCRA_b.SDPSEL = 0; + R_CTSU->CTSUSUCLK0 = (uint16_t) (((j + CTSU_CORRCFC_CENTER_POINT) * CTSU_CORRECTION_SUMULTI) - 1); + R_CTSU->CTSUCRA_b.SDPSEL = 1; + + ctsu_corrcfc_measurement(p_instance_ctrl, &g_ctsu_corrcfc_info.dac_value[index][j], CTSU_CORRCFC_POINT_NUM); + } + + /* Reset register */ + R_CTSU->CTSUCALIB_b.CFCMODE = 0; + R_CTSU->CTSUCALIB_b.CCOCLK = 1; + + /* Step3 : Calculate the error between step1 and step2. */ + for (i = index; i < (index + g_ctsu_corrcfc_info.num_ts); i++) + { + /* Linear interpolation calculation */ + base_value = g_ctsu_corrcfc_info.base_value[i]; + j = 1; + while (1) + { + if ((base_value < g_ctsu_corrcfc_info.dac_value[index][j]) || ((CTSU_CORRCFC_POINT_NUM - 1) == j)) + { + y0 = (uint16_t) (CTSU_CORRECTION_STD_UNIT * (j + CTSU_CORRCFC_CENTER_POINT)); + x0 = g_ctsu_corrcfc_info.dac_value[index][j]; + x1 = g_ctsu_corrcfc_info.dac_value[index][j - 1]; + break; + } + + j++; + } + + base_conv_dac = (uint16_t) (y0 - ((CTSU_CORRECTION_STD_UNIT * (x0 - base_value)) / (x0 - x1))); + + /* Error rate calculation */ + g_ctsu_corrcfc_info.error_rate[i] = + (uint16_t) (((CTSU_CORRECTION_STD_UNIT * 4) << CTSU_SHIFT_AMOUNT) / base_conv_dac); + + for (j = 0; j < CTSU_CORRCFC_POINT_NUM; j++) + { + g_ctsu_corrcfc_info.ref_value[i][j] = + (uint16_t) ((CTSU_CORRECTION_STD_UNIT * (j + CTSU_CORRCFC_CENTER_POINT) * + g_ctsu_corrcfc_info.error_rate[i]) >> CTSU_SHIFT_AMOUNT); + } + } + + g_ctsu_corrcfc_info.index = (uint8_t) (index + g_ctsu_corrcfc_info.num_ts); + + g_ctsu_corrcfc_info.status = CTSU_CORRECTION_COMPLETE; +} + +/*********************************************************************************************************************** + * ctsu_corrcfc_measurement + ***********************************************************************************************************************/ +void ctsu_corrcfc_measurement (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * data, uint8_t point_num) +{ + uint16_t i; + uint8_t cfc_id; + uint32_t sum[CTSU_CFG_NUM_CFC]; + + /* initialize sum array */ + for (cfc_id = 0; cfc_id < CTSU_CFG_NUM_CFC; cfc_id++) + { + sum[cfc_id] = 0; + } + + for (i = 0; i < CTSU_CORRECTION_AVERAGE; i++) + { + #if (CTSU_CFG_DTC_SUPPORT_ENABLE == 1) + ctsu_transfer_configure(p_instance_ctrl); + #else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #endif + p_instance_ctrl->state = CTSU_STATE_SCANNING; + R_CTSU->CTSUCR0 |= 0x01; + while (p_instance_ctrl->state != CTSU_STATE_SCANNED) + { + } + + /* Get sum */ + for (cfc_id = 0; cfc_id < CTSU_CFG_NUM_CFC; cfc_id++) + { + sum[cfc_id] += g_ctsu_corrcfc_info.scanbuf[cfc_id]; + } + } + + /* Average sum data */ + for (cfc_id = 0; cfc_id < g_ctsu_corrcfc_info.num_ts; cfc_id++) + { + *(data + (cfc_id * point_num)) = (uint16_t) (sum[cfc_id] / CTSU_CORRECTION_AVERAGE); + } +} + + #endif + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_auto_correction_register_set + ***********************************************************************************************************************/ +void ctsu_auto_correction_register_set (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint16_t j; + uint32_t corr_dac; + uint32_t corr_coef; + int16_t range; + + /* Initialization of sensor counter auto correction table register number */ + R_CTSU->CTSUOPT_b.SCACTB = 0; + + /* Enter the correction factor and dac_value in CTSUSCNTACT for 12 correction tables */ + range = (int16_t) p_instance_ctrl->range; + for (j = 0; j < CTSU_CORRECTION_POINT_NUM; j++) + { + corr_dac = g_ctsu_correction_info.dac_value[range][j]; + corr_coef = g_ctsu_correction_info.coef[range][j]; + + R_CTSU->CTSUSCNTACT = (corr_dac << 16) | (corr_coef); + } +} + + #endif + + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_multiclock_auto_correction_register_set + ***********************************************************************************************************************/ +void ctsu_multiclock_auto_correction_register_set (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint16_t element_id; + int16_t offsetcoeff_1; + int16_t offsetcoeff_2; + uint16_t elem_w_sumulti; + + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + elem_w_sumulti = element_id * CTSU_CFG_NUM_SUMULTI; + + /* Calculating the Second Frequency */ + offsetcoeff_1 = ctsu_multiclock_auto_correction_calc(p_instance_ctrl, element_id, 2); + + /* Calculating the Third Frequency */ + offsetcoeff_2 = ctsu_multiclock_auto_correction_calc(p_instance_ctrl, element_id, 3); + + if (0 == p_instance_ctrl->p_ctsu_cfg->ajfen) + { + p_instance_ctrl->p_mcact1[elem_w_sumulti + 0] = 0; + p_instance_ctrl->p_mcact1[elem_w_sumulti + 1] = ((uint32_t) offsetcoeff_1 << 16) | + (p_instance_ctrl->p_ctsuwr[elem_w_sumulti + 1].ctsuso & + CTSU_TUNING_MAX); + + p_instance_ctrl->p_mcact1[elem_w_sumulti + 2] = ((uint32_t) offsetcoeff_2 << 16) | + (p_instance_ctrl->p_ctsuwr[elem_w_sumulti + 2].ctsuso & + CTSU_TUNING_MAX); + } + else + { + p_instance_ctrl->p_mcact1[element_id] = ((uint32_t) offsetcoeff_1 << 16) | + (p_instance_ctrl->p_ctsuwr[elem_w_sumulti + 1].ctsuso & + CTSU_TUNING_MAX); + + p_instance_ctrl->p_mcact2[element_id] = ((uint32_t) offsetcoeff_2 << 16) | + (p_instance_ctrl->p_ctsuwr[elem_w_sumulti + 2].ctsuso & + CTSU_TUNING_MAX); + } + } +} + +/*********************************************************************************************************************** + * ctsu_multiclock_auto_correction_calc + ***********************************************************************************************************************/ +int16_t ctsu_multiclock_auto_correction_calc (ctsu_instance_ctrl_t * const p_instance_ctrl, + uint16_t element_id, + uint8_t freq) +{ + uint8_t current_mode; + uint8_t first_sumulti; + uint8_t freq_sumulti; + uint16_t first_so; + uint16_t freq_so; + uint8_t snum_recommend; + uint8_t snum; + int32_t numerator_1; // ((SUMULTIn + 1)SO0 - (SUMULTI0 + 1)SOn) + int32_t numerator_2; // ((Gcco * 20uA * 128us) / 1024)(OffsetDACmax / CurrentMode)) + int32_t numerator_3; // (SNUM + 1) + int32_t denominator; // ((SUMULTIn + 1)(SNUM0 + 1) + int16_t offsetcoeff; + int32_t offsetcoeff_tmp; + uint16_t elem_w_sumulti; + elem_w_sumulti = element_id * CTSU_CFG_NUM_SUMULTI; + + if (CTSU_ATUNE12_80UA == p_instance_ctrl->p_ctsu_cfg->atune12) + { + current_mode = CTSU_AUTO_CURRENT_MODE_80UA; + } + else if (CTSU_ATUNE12_40UA == p_instance_ctrl->p_ctsu_cfg->atune12) + { + current_mode = CTSU_AUTO_CURRENT_MODE_40UA; + } + else if (CTSU_ATUNE12_20UA == p_instance_ctrl->p_ctsu_cfg->atune12) + { + current_mode = CTSU_AUTO_CURRENT_MODE_20UA; + } + else // (CTSU_ATUNE12_160UA == p_instance_ctrl->p_ctsu_cfg->atune12) + { + current_mode = CTSU_AUTO_CURRENT_MODE_160UA; + } + + if (2 == freq) + { + freq_sumulti = CTSU_CFG_SUMULTI1 + 1; + freq_so = p_instance_ctrl->p_ctsuwr[elem_w_sumulti + 1].ctsuso & CTSU_TUNING_MAX; + } + else // 3 == freq + { + freq_sumulti = CTSU_CFG_SUMULTI2 + 1; + freq_so = p_instance_ctrl->p_ctsuwr[elem_w_sumulti + 2].ctsuso & CTSU_TUNING_MAX; + } + + first_so = p_instance_ctrl->p_ctsuwr[elem_w_sumulti].ctsuso & CTSU_TUNING_MAX; + first_sumulti = CTSU_CFG_SUMULTI0 + 1; + snum_recommend = CTSU_SNUM_RECOMMEND + 1; + snum = (p_instance_ctrl->p_ctsuwr[elem_w_sumulti].ctsuso >> 10) & CTSU_SNUM_MAX; + + numerator_1 = ((int32_t) freq_sumulti * first_so) - ((int32_t) first_sumulti * freq_so); + numerator_2 = (int32_t) (CTSU_AUTO_REF_COEFFICIENT * CTSU_AUTO_CORRECTION_OFFSET_DAC_MAX / current_mode); + numerator_3 = (int32_t) snum + 1; + denominator = (int32_t) (freq_sumulti * snum_recommend); + + /* overflow check int32 */ + if ((CTSU_AUTO_INT32_OVERFLOW_VALUE / numerator_2) <= (numerator_1 * numerator_3)) + { + offsetcoeff = CTSU_AUTO_INT16_OVERFLOW_VALUE; + p_instance_ctrl->p_correction_info->calculation_error = 1; + } + else if (-(CTSU_AUTO_INT32_OVERFLOW_VALUE / numerator_2) >= (numerator_1 * numerator_3)) + { + offsetcoeff = CTSU_AUTO_INT16_UNDERFLOW_VALUE; + p_instance_ctrl->p_correction_info->calculation_error = 1; + } + else + { + /* calculate offset coefficient with int32 */ + offsetcoeff_tmp = (numerator_1 * numerator_2 * numerator_3 / denominator); + + /* overflow check int16 */ + if (CTSU_AUTO_INT16_OVERFLOW_VALUE <= offsetcoeff_tmp) + { + offsetcoeff = CTSU_AUTO_INT16_OVERFLOW_VALUE; + p_instance_ctrl->p_correction_info->calculation_error = 1; + } + else if (CTSU_AUTO_INT16_UNDERFLOW_VALUE >= offsetcoeff_tmp) + { + offsetcoeff = CTSU_AUTO_INT16_UNDERFLOW_VALUE; + p_instance_ctrl->p_correction_info->calculation_error = 1; + } + else + { + offsetcoeff = (int16_t) offsetcoeff_tmp; + } + } + + return offsetcoeff; +} + + #endif + + #if (CTSU_CFG_AUTO_JUDGE_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_auto_judge_threshold_calc + ***********************************************************************************************************************/ +void ctsu_auto_judge_threshold_calc (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint8_t element_id; + uint8_t i; + int16_t ajthr_h; + int16_t ajthr_l; + + for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) + { + #if (CTSU_CFG_AUTO_MULTI_CLOCK_CORRECTION_ENABLE == 1) + if (1 == p_instance_ctrl->p_ctsu_cfg->majirimd) + { + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->p_ctsu_cfg->md) + { + p_instance_ctrl->p_ajthr[element_id] = + ((uint32_t) p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[element_id].threshold << 16) | + (p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[element_id]. + threshold - p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[element_id].hysteresis); + } + else + { + ajthr_h = + (int16_t) (-(p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[element_id].threshold) + + p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[element_id].hysteresis); + ajthr_l = (int16_t) (-(p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[element_id].threshold)); + p_instance_ctrl->p_ajthr[element_id] = ((uint32_t) ajthr_h << 16) | + (ajthr_l & CTSU_AUTO_MINUS_BIT_MASK); + } + } + else + #endif + { + for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) + { + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->p_ctsu_cfg->md) + { + p_instance_ctrl->p_ajthr[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + i] = + ((uint32_t) p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[(element_id * + CTSU_MAJORITY_MODE_ELEMENTS) + + i].threshold << 16) | + (p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + + i].threshold - + p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + + i].hysteresis); + } + else + { + ajthr_h = + (int16_t) (-(p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[(element_id * + CTSU_MAJORITY_MODE_ELEMENTS) + + i].threshold) + + p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[(element_id * + CTSU_MAJORITY_MODE_ELEMENTS) + + i].hysteresis); + ajthr_l = + (int16_t) (-(p_instance_ctrl->p_ctsu_cfg->p_ctsu_auto_buttons[(element_id * + CTSU_MAJORITY_MODE_ELEMENTS) + + i].threshold)); + p_instance_ctrl->p_ajthr[(element_id * CTSU_MAJORITY_MODE_ELEMENTS) + i] = + ((uint32_t) ajthr_h << 16) | (ajthr_l & CTSU_AUTO_MINUS_BIT_MASK); + } + } + } + } +} + + #endif + +#endif + +/*******************************************************************************************************************//** + * @brief Diagnosis the CTSU peripheral. + * Implements @ref ctsu_api_t::diagnosis. + * + * + * Example: + * @snippet r_ctsu_example.c R_CTSU_Diagnosis + * + * @retval FSP_SUCCESS CTSU successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CTSU_NOT_GET_DATA The previous data has not been retrieved by DataGet. + * @retval FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE Diagnosis of LDO over voltage failed. + * @retval FSP_ERR_CTSU_DIAG_CCO_HIGH Diagnosis of CCO into 19.2uA failed. + * @retval FSP_ERR_CTSU_DIAG_CCO_LOW Diagnosis of CCO into 2.4uA failed. + * @retval FSP_ERR_CTSU_DIAG_SSCG Diagnosis of SSCG frequency failed. + * @retval FSP_ERR_CTSU_DIAG_DAC Diagnosis of non-touch count value failed. + * @retval FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE Diagnosis of LDO output voltage failed. + * @retval FSP_ERR_CTSU_DIAG_OVER_VOLTAGE Diagnosis of over voltage detection circuit failed. + * @retval FSP_ERR_CTSU_DIAG_OVER_CURRENT Diagnosis of over current detection circuit failed. + * @retval FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE Diagnosis of LDO internal resistance value failed. + * @retval FSP_ERR_CTSU_DIAG_CURRENT_SOURCE Diagnosis of LDO internal resistance value failed. + * @retval FSP_ERR_CTSU_DIAG_SENSCLK_GAIN Diagnosis of SENSCLK frequency gain failed. + * @retval FSP_ERR_CTSU_DIAG_SUCLK_GAIN Diagnosis of SUCLK frequency gain failed. + * @retval FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY Diagnosis of SUCLK clock recovery function failed. + * @retval FSP_ERR_CTSU_DIAG_CFC_GAIN Diagnosis of CFC oscillator gain failed. + **********************************************************************************************************************/ + +fsp_err_t R_CTSU_Diagnosis (ctsu_ctrl_t * const p_ctrl) +{ +#if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + fsp_err_t diag_err; +#endif + ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) p_ctrl; + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(CTSU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_ERROR_RETURN(CTSU_STATE_SCANNED != p_instance_ctrl->state, FSP_ERR_CTSU_NOT_GET_DATA); + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_DIAG_COMPLETE == g_ctsu_diag_info.state) + { + diag_err = ctsu_diag_ldo_over_voltage_result(); + if (FSP_SUCCESS != diag_err) + { + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE; + } + + diag_err = ctsu_diag_oscillator_high_result(); + if (FSP_SUCCESS != diag_err) + { + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_CCO_HIGH; + } + + diag_err = ctsu_diag_oscillator_low_result(); + if (FSP_SUCCESS != diag_err) + { + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_CCO_LOW; + } + + diag_err = ctsu_diag_sscg_result(); + if (FSP_SUCCESS != diag_err) + { + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_SSCG; + } + + diag_err = ctsu_diag_dac_result(); + if (FSP_SUCCESS != diag_err) + { + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_DAC; + } + + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + } + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + if (CTSU_DIAG_COMPLETE == g_ctsu_diag_info.state) + { + ctsu_diag_regi_store2(); + + g_ctsu_diag_info.state = CTSU_DIAG_OUTPUT_VOLTAGE; + diag_err = ctsu_diag_output_voltage_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE; + } + + g_ctsu_diag_info.state = CTSU_DIAG_OVER_VOLTAGE; + diag_err = ctsu_diag_over_voltage_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_OVER_VOLTAGE; + } + + g_ctsu_diag_info.state = CTSU_DIAG_OVER_CURRENT; + diag_err = ctsu_diag_over_current_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_OVER_CURRENT; + } + + g_ctsu_diag_info.state = CTSU_DIAG_LOAD_RESISTANCE; + diag_err = ctsu_diag_load_resistance_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE; + } + + g_ctsu_diag_info.state = CTSU_DIAG_CURRENT_SOURCE; + diag_err = ctsu_diag_current_source_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_CURRENT_SOURCE; + } + + g_ctsu_diag_info.state = CTSU_DIAG_SENSCLK; + diag_err = ctsu_diag_cco_gain_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_SENSCLK_GAIN; + } + + g_ctsu_diag_info.state = CTSU_DIAG_SUCLK; + diag_err = ctsu_diag_cco_gain_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_SUCLK_GAIN; + } + + g_ctsu_diag_info.state = CTSU_DIAG_CLOCK_RECOVERY; + diag_err = ctsu_diag_clock_recovery_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY; + } + + #if (CTSU_CFG_NUM_CFC != 0) + g_ctsu_diag_info.state = CTSU_DIAG_CFC; + diag_err = ctsu_diag_cfc_gain_result(); + if (FSP_SUCCESS != diag_err) + { + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + + return FSP_ERR_CTSU_DIAG_CFC_GAIN; + } + #endif + + ctsu_diag_regi_restore2(); + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + } + #endif +#endif + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +#if (BSP_FEATURE_CTSU_VERSION == 1) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_diag_scan_start1 + ***********************************************************************************************************************/ +static void ctsu_diag_scan_start1 (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + if (CTSU_DIAG_INIT == g_ctsu_diag_info.state) + { + g_ctsu_diag_info.state = CTSU_DIAG_OVER_VOLTAGE; + } + + /* ctsu normal scan register save */ + g_ctsu_diag_reg.ctsucr0 = R_CTSU->CTSUCR0; + g_ctsu_diag_reg.ctsucr1 = R_CTSU->CTSUCR1; + g_ctsu_diag_reg.ctsusdprs = R_CTSU->CTSUSDPRS; + g_ctsu_diag_reg.ctsusst = R_CTSU->CTSUSST; + g_ctsu_diag_reg.ctsuchac0 = R_CTSU->CTSUCHAC[0]; + g_ctsu_diag_reg.ctsuchac1 = R_CTSU->CTSUCHAC[1]; + g_ctsu_diag_reg.ctsuchac2 = R_CTSU->CTSUCHAC[2]; + g_ctsu_diag_reg.ctsuchtrc0 = R_CTSU->CTSUCHTRC[0]; + g_ctsu_diag_reg.ctsuchtrc1 = R_CTSU->CTSUCHTRC[1]; + g_ctsu_diag_reg.ctsuchtrc2 = R_CTSU->CTSUCHTRC[2]; + g_ctsu_diag_reg.ctsudclkc = R_CTSU->CTSUDCLKC; + g_ctsu_diag_reg.ctsuerrs = R_CTSU->CTSUERRS; + + /* scan register setting */ + if (CTSU_DIAG_OVER_VOLTAGE == g_ctsu_diag_info.state) + { + ctsu_diag_ldo_over_voltage_scan_start(); + } + + if (CTSU_DIAG_CCO_HIGH == g_ctsu_diag_info.state) + { + ctsu_diag_oscillator_high_scan_start(); + } + + if (CTSU_DIAG_CCO_LOW == g_ctsu_diag_info.state) + { + ctsu_diag_oscillator_low_scan_start(); + } + + if (CTSU_DIAG_SSCG == g_ctsu_diag_info.state) + { + ctsu_diag_sscg_scan_start(); + } + + if (CTSU_DIAG_DAC == g_ctsu_diag_info.state) + { + ctsu_diag_dac_scan_start(p_instance_ctrl); + } +} + +/*********************************************************************************************************************** + * ctsu_diag_data_get1 + ***********************************************************************************************************************/ +static fsp_err_t ctsu_diag_data_get1 (void) +{ + fsp_err_t err; + + /* data get */ + if (CTSU_DIAG_OVER_VOLTAGE == g_ctsu_diag_info.state) + { + ctsu_diag_ldo_over_voltage_data_get(); + + g_ctsu_diag_info.state = CTSU_DIAG_CCO_HIGH; + } + else if (CTSU_DIAG_CCO_HIGH == g_ctsu_diag_info.state) + { + ctsu_diag_oscillator_high_data_get(); + + g_ctsu_diag_info.state = CTSU_DIAG_CCO_LOW; + } + else if (CTSU_DIAG_CCO_LOW == g_ctsu_diag_info.state) + { + ctsu_diag_oscillator_low_data_get(); + + g_ctsu_diag_info.state = CTSU_DIAG_SSCG; + } + else if (CTSU_DIAG_SSCG == g_ctsu_diag_info.state) + { + ctsu_diag_sscg_data_get(); + + g_ctsu_diag_info.state = CTSU_DIAG_DAC; + } + else if (CTSU_DIAG_DAC == g_ctsu_diag_info.state) + { + ctsu_diag_dac_data_get(); + if (CTSU_TUNING_INCOMPLETE == g_ctsu_diag_info.tuning) + { + g_ctsu_diag_info.state = CTSU_DIAG_DAC; + } + else + { + g_ctsu_diag_info.loop_count++; + if (6 <= g_ctsu_diag_info.loop_count) + { + g_ctsu_diag_info.state = CTSU_DIAG_COMPLETE; + g_ctsu_diag_info.loop_count = 0; + } + } + } + else + { + } + + /* register restore */ + R_CTSU->CTSUCR0 = g_ctsu_diag_reg.ctsucr0; + R_CTSU->CTSUCR1 = g_ctsu_diag_reg.ctsucr1; + R_CTSU->CTSUSDPRS = g_ctsu_diag_reg.ctsusdprs; + R_CTSU->CTSUSST = g_ctsu_diag_reg.ctsusst; + R_CTSU->CTSUCHAC[0] = g_ctsu_diag_reg.ctsuchac0; + R_CTSU->CTSUCHAC[1] = g_ctsu_diag_reg.ctsuchac1; + R_CTSU->CTSUCHAC[2] = g_ctsu_diag_reg.ctsuchac2; + R_CTSU->CTSUCHTRC[0] = g_ctsu_diag_reg.ctsuchtrc0; + R_CTSU->CTSUCHTRC[1] = g_ctsu_diag_reg.ctsuchtrc1; + R_CTSU->CTSUCHTRC[2] = g_ctsu_diag_reg.ctsuchtrc2; + R_CTSU->CTSUDCLKC = g_ctsu_diag_reg.ctsudclkc; + R_CTSU->CTSUERRS_b.CTSUSPMD = 0; + R_CTSU->CTSUERRS_b.CTSUTSOD = 0; + R_CTSU->CTSUERRS_b.CTSUDRV = 0; + R_CTSU->CTSUERRS_b.CTSUTSOC = 0; + R_CTSU->CTSUERRS_b.CTSUCLKSEL1 = 0; + + if (CTSU_DIAG_COMPLETE == g_ctsu_diag_info.state) + { + err = FSP_SUCCESS; + } + else + { + err = FSP_ERR_CTSU_DIAG_NOT_YET; + } + + return err; +} + +static void ctsu_diag_ldo_over_voltage_scan_start (void) +{ + uint32_t pclkb_mhz; + uint32_t ctsu_sdpa; + + /* Set power on */ + R_CTSU->CTSUCR1 = ((CTSU_CFG_LOW_VOLTAGE_MODE << 2) | (CTSU_CSW_ON << 1) | CTSU_PON_ON); + + /* Synchronous Noise Reduction Setting */ + R_CTSU->CTSUSDPRS = ((CTSU_SOFF_ON << 6) | (CTSU_PRMODE_62_PULSES << 4) | CTSU_PRRATIO_RECOMMEND); + + /* High Pass Noise Reduction- ALWAYS 0x30 as per HW Manual */ + R_CTSU->CTSUDCLKC = ((CTSU_SSCNT << 4) | CTSU_SSMOD); + + /* Sensor Stabilization- ALWAYS 0x10 as per HW Manual */ + R_CTSU->CTSUSST = (CTSU_SST_RECOMMEND); + + /* Since CLK is rewritten by correction, set here. */ + R_CTSU->CTSUCR1 |= (uint8_t) (CTSU_CFG_PCLK_DIVISION << 4); + + pclkb_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / CTSU_PCLKB_FREQ_MHZ; + if (CTSU_PCLKB_FREQ_RANGE1 >= pclkb_mhz) + { + R_CTSU->CTSUCR1 |= (0 << 4); + ctsu_sdpa = pclkb_mhz - 1; + } + else if ((CTSU_PCLKB_FREQ_RANGE1 < pclkb_mhz) && (CTSU_PCLKB_FREQ_RANGE2 >= pclkb_mhz)) + { + R_CTSU->CTSUCR1 |= (1 << 4); + ctsu_sdpa = (pclkb_mhz / 2) - 1; + } + else + { + R_CTSU->CTSUCR1 |= (2 << 4); + ctsu_sdpa = (pclkb_mhz / 4) - 1; + } + + R_CTSU->CTSUCR1 |= (CTSU_MODE_SELF_MULTI_SCAN << 6); + R_CTSU->CTSUCHAC[0] = 0x01; + R_CTSU->CTSUCHAC[1] = 0x00; + R_CTSU->CTSUCHAC[2] = 0x00; + R_CTSU->CTSUCHAC[3] = 0x00; + R_CTSU->CTSUCHAC[4] = 0x00; + R_CTSU->CTSUCHTRC[0] = 0x00; + R_CTSU->CTSUCHTRC[1] = 0x00; + R_CTSU->CTSUCHTRC[2] = 0x00; + R_CTSU->CTSUCHTRC[3] = 0x00; + R_CTSU->CTSUCHTRC[4] = 0x00; + + /* Correction measurement setting */ + R_CTSU->CTSUERRS_b.CTSUSPMD = 0; + R_CTSU->CTSUERRS_b.CTSUTSOD = 0; + R_CTSU->CTSUERRS_b.CTSUDRV = 0; + R_CTSU->CTSUERRS_b.CTSUCLKSEL1 = 0; + R_CTSU->CTSUERRS_b.CTSUTSOC = 1; + g_ctsu_diag_info.icomp = 0; + + g_ctsu_diag_info.ctsuwr.ctsussc = (CTSU_SSDIV_0500 << 8); + g_ctsu_diag_info.ctsuwr.ctsuso0 = CTSU_DIAG_DAC_SO_MAX; + g_ctsu_diag_info.ctsuwr.ctsuso1 = (uint16_t) ((CTSU_ICOG_66 << 13) | (ctsu_sdpa << 8) | CTSU_RICOA_RECOMMEND); +} + +static void ctsu_diag_ldo_over_voltage_data_get (void) +{ + /* Nothing */ +} + +static fsp_err_t ctsu_diag_ldo_over_voltage_result (void) +{ + if (1 != g_ctsu_diag_info.icomp) + { + return FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE; + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_oscillator_high_scan_start (void) +{ + uint32_t ctsu_sdpa; + uint32_t pclkb_mhz; + + /* Set power on */ + R_CTSU->CTSUCR1 = ((CTSU_CFG_LOW_VOLTAGE_MODE << 2) | (CTSU_CSW_ON << 1) | CTSU_PON_ON); + + /* Synchronous Noise Reduction Setting */ + R_CTSU->CTSUSDPRS = ((CTSU_SOFF_ON << 6) | (CTSU_PRMODE_62_PULSES << 4) | CTSU_PRRATIO_RECOMMEND); + + /* High Pass Noise Reduction- ALWAYS 0x30 as per HW Manual */ + R_CTSU->CTSUDCLKC = ((CTSU_SSCNT << 4) | CTSU_SSMOD); + + /* Sensor Stabilization- ALWAYS 0x10 as per HW Manual */ + R_CTSU->CTSUSST = (CTSU_SST_RECOMMEND); + + /* Since CLK is rewritten by correction, set here. */ + R_CTSU->CTSUCR1 |= (uint8_t) (CTSU_CFG_PCLK_DIVISION << 4); + + pclkb_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / CTSU_PCLKB_FREQ_MHZ; + if (CTSU_PCLKB_FREQ_RANGE1 >= pclkb_mhz) + { + R_CTSU->CTSUCR1 |= (0 << 4); + ctsu_sdpa = pclkb_mhz - 1; + } + else if ((CTSU_PCLKB_FREQ_RANGE1 < pclkb_mhz) && (CTSU_PCLKB_FREQ_RANGE2 >= pclkb_mhz)) + { + R_CTSU->CTSUCR1 |= (1 << 4); + ctsu_sdpa = (pclkb_mhz / 2) - 1; + } + else + { + R_CTSU->CTSUCR1 |= (2 << 4); + ctsu_sdpa = (pclkb_mhz / 4) - 1; + } + + R_CTSU->CTSUCR1 |= (CTSU_MODE_SELF_MULTI_SCAN << 6); + R_CTSU->CTSUCHAC[0] = 0x01; + R_CTSU->CTSUCHAC[1] = 0x00; + R_CTSU->CTSUCHAC[2] = 0x00; + R_CTSU->CTSUCHAC[3] = 0x00; + R_CTSU->CTSUCHAC[4] = 0x00; + R_CTSU->CTSUCHTRC[0] = 0x00; + R_CTSU->CTSUCHTRC[1] = 0x00; + R_CTSU->CTSUCHTRC[2] = 0x00; + R_CTSU->CTSUCHTRC[3] = 0x00; + R_CTSU->CTSUCHTRC[4] = 0x00; + + R_CTSU->CTSUSO0_b.CTSUSO = 0; + + g_ctsu_diag_info.ctsuwr.ctsussc = (CTSU_SSDIV_0500 << 8); + g_ctsu_diag_info.ctsuwr.ctsuso0 = 0x0000; + g_ctsu_diag_info.ctsuwr.ctsuso1 = (uint16_t) ((CTSU_ICOG_66 << 13) | (ctsu_sdpa << 8) | CTSU_RICOA_RECOMMEND); + + /* Correction measurement setting */ + R_CTSU->CTSUERRS_b.CTSUSPMD = 2; // 0x82 + R_CTSU->CTSUERRS_b.CTSUTSOC = 1; + R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS); +} + +static void ctsu_diag_oscillator_high_data_get (void) +{ + g_ctsu_diag_info.cco_high = g_ctsu_diag_info.scanbuf.sen; +} + +static fsp_err_t ctsu_diag_oscillator_high_result (void) +{ + if ((g_ctsu_diag_info.cco_high < CTSU_CFG_DIAG_CCO_HIGH_MAX) && + (g_ctsu_diag_info.cco_high > CTSU_CFG_DIAG_CCO_HIGH_MIN)) + { + } + else + { + return FSP_ERR_CTSU_DIAG_CCO_HIGH; + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_oscillator_low_scan_start (void) +{ + uint32_t ctsu_sdpa; + uint32_t pclkb_mhz; + + /* Set power on */ + R_CTSU->CTSUCR1 = ((CTSU_CFG_LOW_VOLTAGE_MODE << 2) | (CTSU_CSW_ON << 1) | CTSU_PON_ON); + + /* Synchronous Noise Reduction Setting */ + R_CTSU->CTSUSDPRS = ((CTSU_SOFF_ON << 6) | (CTSU_PRMODE_62_PULSES << 4) | CTSU_PRRATIO_RECOMMEND); + + /* High Pass Noise Reduction- ALWAYS 0x30 as per HW Manual */ + R_CTSU->CTSUDCLKC = ((CTSU_SSCNT << 4) | CTSU_SSMOD); + + /* Sensor Stabilization- ALWAYS 0x10 as per HW Manual */ + R_CTSU->CTSUSST = (CTSU_SST_RECOMMEND); + + /* Since CLK is rewritten by correction, set here. */ + R_CTSU->CTSUCR1 |= (uint8_t) (CTSU_CFG_PCLK_DIVISION << 4); + + pclkb_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / CTSU_PCLKB_FREQ_MHZ; + if (CTSU_PCLKB_FREQ_RANGE1 >= pclkb_mhz) + { + R_CTSU->CTSUCR1 |= (0 << 4); + ctsu_sdpa = pclkb_mhz - 1; + } + else if ((CTSU_PCLKB_FREQ_RANGE1 < pclkb_mhz) && (CTSU_PCLKB_FREQ_RANGE2 >= pclkb_mhz)) + { + R_CTSU->CTSUCR1 |= (1 << 4); + ctsu_sdpa = (pclkb_mhz / 2) - 1; + } + else + { + R_CTSU->CTSUCR1 |= (2 << 4); + ctsu_sdpa = (pclkb_mhz / 4) - 1; + } + + R_CTSU->CTSUCR1 |= (CTSU_MODE_SELF_MULTI_SCAN << 6); + R_CTSU->CTSUCHAC[0] = 0x01; + R_CTSU->CTSUCHAC[1] = 0x00; + R_CTSU->CTSUCHAC[2] = 0x00; + R_CTSU->CTSUCHAC[3] = 0x00; + R_CTSU->CTSUCHAC[4] = 0x00; + R_CTSU->CTSUCHTRC[0] = 0x00; + R_CTSU->CTSUCHTRC[1] = 0x00; + R_CTSU->CTSUCHTRC[2] = 0x00; + R_CTSU->CTSUCHTRC[3] = 0x00; + R_CTSU->CTSUCHTRC[4] = 0x00; + + R_CTSU->CTSUSO0_b.CTSUSO = 0; + + g_ctsu_diag_info.ctsuwr.ctsussc = (CTSU_SSDIV_0500 << 8); + g_ctsu_diag_info.ctsuwr.ctsuso0 = 0x0000; + g_ctsu_diag_info.ctsuwr.ctsuso1 = (uint16_t) ((CTSU_ICOG_66 << 13) | (ctsu_sdpa << 8) | CTSU_RICOA_RECOMMEND); + + /* Correction measurement setting */ + R_CTSU->CTSUERRS_b.CTSUSPMD = 0; // 0x80 + R_CTSU->CTSUERRS_b.CTSUTSOC = 1; + R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS); +} + +static void ctsu_diag_oscillator_low_data_get (void) +{ + g_ctsu_diag_info.cco_low = g_ctsu_diag_info.scanbuf.sen; +} + +static fsp_err_t ctsu_diag_oscillator_low_result (void) +{ + if ((g_ctsu_diag_info.cco_low < CTSU_CFG_DIAG_CCO_LOW_MAX) && + (g_ctsu_diag_info.cco_low > CTSU_CFG_DIAG_CCO_LOW_MIN)) + { + } + else + { + return FSP_ERR_CTSU_DIAG_CCO_LOW; + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_sscg_scan_start (void) +{ + uint32_t ctsu_sdpa; + uint32_t pclkb_mhz; + + /* Set power on */ + R_CTSU->CTSUCR1 = ((CTSU_CFG_LOW_VOLTAGE_MODE << 2) | (CTSU_CSW_ON << 1) | CTSU_PON_ON); + + /* Synchronous Noise Reduction Setting */ + R_CTSU->CTSUSDPRS = ((CTSU_SOFF_ON << 6) | (CTSU_PRMODE_62_PULSES << 4) | CTSU_PRRATIO_RECOMMEND); + + /* High Pass Noise Reduction- ALWAYS 0x30 as per HW Manual */ + R_CTSU->CTSUDCLKC = ((CTSU_SSCNT << 4) | CTSU_SSMOD); + + /* Sensor Stabilization- ALWAYS 0x10 as per HW Manual */ + R_CTSU->CTSUSST = (CTSU_SST_RECOMMEND); + + /* Since CLK is rewritten by correction, set here. */ + R_CTSU->CTSUCR1 |= (uint8_t) (CTSU_CFG_PCLK_DIVISION << 4); + + pclkb_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / CTSU_PCLKB_FREQ_MHZ; + if (CTSU_PCLKB_FREQ_RANGE1 >= pclkb_mhz) + { + R_CTSU->CTSUCR1 |= (0 << 4); + ctsu_sdpa = pclkb_mhz - 1; + } + else if ((CTSU_PCLKB_FREQ_RANGE1 < pclkb_mhz) && (CTSU_PCLKB_FREQ_RANGE2 >= pclkb_mhz)) + { + R_CTSU->CTSUCR1 |= (1 << 4); + ctsu_sdpa = (pclkb_mhz / 2) - 1; + } + else + { + R_CTSU->CTSUCR1 |= (2 << 4); + ctsu_sdpa = (pclkb_mhz / 4) - 1; + } + + R_CTSU->CTSUCR1 |= (CTSU_MODE_SELF_MULTI_SCAN << 6); + + R_CTSU->CTSUCHAC[0] = 0x01; + R_CTSU->CTSUCHAC[1] = 0x00; + R_CTSU->CTSUCHAC[2] = 0x00; + R_CTSU->CTSUCHAC[3] = 0x00; + R_CTSU->CTSUCHAC[4] = 0x00; + R_CTSU->CTSUCHTRC[0] = 0x00; + R_CTSU->CTSUCHTRC[1] = 0x00; + R_CTSU->CTSUCHTRC[2] = 0x00; + R_CTSU->CTSUCHTRC[3] = 0x00; + R_CTSU->CTSUCHTRC[4] = 0x00; + + R_CTSU->CTSUSO0_b.CTSUSO = 0; + + g_ctsu_diag_info.ctsuwr.ctsussc = (CTSU_SSDIV_0500 << 8); + g_ctsu_diag_info.ctsuwr.ctsuso0 = 0x0000; + g_ctsu_diag_info.ctsuwr.ctsuso1 = (uint16_t) ((CTSU_ICOG_66 << 13) | (ctsu_sdpa << 8) | CTSU_RICOA_RECOMMEND); + + /* Correction measurement setting */ + R_CTSU->CTSUERRS_b.CTSUSPMD = 0; + R_CTSU->CTSUERRS_b.CTSUTSOD = 0; + R_CTSU->CTSUERRS_b.CTSUDRV = 0; + R_CTSU->CTSUERRS_b.CTSUTSOC = 1; + R_CTSU->CTSUERRS_b.CTSUCLKSEL1 = 1; +} + +static void ctsu_diag_sscg_data_get (void) +{ + g_ctsu_diag_info.sscg = g_ctsu_diag_info.scanbuf.ref; +} + +static fsp_err_t ctsu_diag_sscg_result (void) +{ + if ((g_ctsu_diag_info.sscg > CTSU_CFG_DIAG_SSCG_MAX) || (g_ctsu_diag_info.sscg < CTSU_CFG_DIAG_SSCG_MIN)) + { + return FSP_ERR_CTSU_DIAG_SSCG; + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_dac_initial_tuning (void) +{ + int32_t diff = 0; + uint32_t complete_flag = 0; + uint16_t ctsuso; + + diff = g_ctsu_diag_info.correct_data - CTSU_DIAG_DAC_TARGET_VALUE; + + ctsuso = g_ctsu_diag_info.ctsuwr.ctsuso0 & CTSU_TUNING_MAX; + if (0 < diff) + { + if (g_ctsu_diag_info.tuning_diff < 0) + { + if ((-diff) > g_ctsu_diag_info.tuning_diff) + { + ctsuso++; + } + + complete_flag = 1; + } + else + { + if (CTSU_TUNING_MAX == ctsuso) + { + complete_flag = 1; + } + else + { + ctsuso++; + g_ctsu_diag_info.tuning_diff = diff; + } + } + } + else if (0 == diff) + { + complete_flag = 1; + } + else + { + if (g_ctsu_diag_info.tuning_diff > 0) + { + if ((-diff) > g_ctsu_diag_info.tuning_diff) + { + ctsuso--; + } + + complete_flag = 1; + } + else + { + complete_flag = 1; + } + } + + g_ctsu_diag_info.ctsuwr.ctsuso0 &= (uint16_t) (~CTSU_TUNING_MAX); + g_ctsu_diag_info.ctsuwr.ctsuso0 |= ctsuso; + + if (CTSU_CFG_NUM_SUMULTI == complete_flag) + { + g_ctsu_diag_info.tuning_diff = 0; + g_ctsu_diag_info.so0_4uc_val = ctsuso; + g_ctsu_diag_info.dac_init = 3; + g_ctsu_diag_info.tuning = CTSU_TUNING_COMPLETE; + g_ctsu_diag_info.loop_count = 0; + g_ctsu_diag_info.dac_cnt[0] = g_ctsu_diag_info.correct_data; + } +} + +static void ctsu_diag_dac_scan_start (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint8_t temp; + + /* Set power on */ + R_CTSU->CTSUCR1 = ((CTSU_CFG_LOW_VOLTAGE_MODE << 2) | (CTSU_CSW_ON << 1) | CTSU_PON_ON); + + /* Synchronous Noise Reduction Setting */ + R_CTSU->CTSUSDPRS = ((CTSU_SOFF_ON << 6) | (CTSU_PRMODE_62_PULSES << 4) | CTSU_PRRATIO_RECOMMEND); + + /* High Pass Noise Reduction- ALWAYS 0x30 as per HW Manual */ + R_CTSU->CTSUDCLKC = ((CTSU_SSCNT << 4) | CTSU_SSMOD); + + /* Sensor Stabilization- ALWAYS 0x10 as per HW Manual */ + R_CTSU->CTSUSST = (CTSU_SST_RECOMMEND); + + /* Since CLK is rewritten by correction, set here. */ + R_CTSU->CTSUCR1 |= (uint8_t) (CTSU_CFG_PCLK_DIVISION << 4); + + temp = (uint8_t) (R_CTSU->CTSUCR1 & ~(CTSU_CR1_MODIFY_BIT)); + R_CTSU->CTSUCR1 = (uint8_t) (temp | (p_instance_ctrl->ctsucr1 & CTSU_CR1_MODIFY_BIT) | CTSU_DAC_TEST_ATUNE1); // MD1, MD0, ATUNE1=1 + #if BSP_FEATURE_CTSU_HAS_TXVSEL + R_CTSU->CTSUCR0 = + (uint8_t) ((R_CTSU->CTSUCR0 & ~(CTSU_TXVSEL)) | (p_instance_ctrl->p_ctsu_cfg->txvsel & CTSU_TXVSEL)); + #endif + + /* Write Channel setting */ + #if (CTSU_CFG_DIAG_DAC_TS >= 0) && (CTSU_CFG_DIAG_DAC_TS < 8) + R_CTSU->CTSUCHAC[0] = 1 << CTSU_CFG_DIAG_DAC_TS; + #else + R_CTSU->CTSUCHAC[0] = 0; + #endif + #if (CTSU_CFG_DIAG_DAC_TS >= 8) && (CTSU_CFG_DIAG_DAC_TS < 16) + R_CTSU->CTSUCHAC[1] = 1 << (CTSU_CFG_DIAG_DAC_TS - 8); + #else + R_CTSU->CTSUCHAC[1] = 0; + #endif + #if (CTSU_CFG_DIAG_DAC_TS >= 16) && (CTSU_CFG_DIAG_DAC_TS < 24) + R_CTSU->CTSUCHAC[2] = 1 << (CTSU_CFG_DIAG_DAC_TS - 16); + #else + R_CTSU->CTSUCHAC[2] = 0; + #endif + #if (CTSU_CFG_DIAG_DAC_TS >= 24) && (CTSU_CFG_DIAG_DAC_TS < 32) + R_CTSU->CTSUCHAC[3] = 1 << (CTSU_CFG_DIAG_DAC_TS - 24); + #else + R_CTSU->CTSUCHAC[3] = 0; + #endif + R_CTSU->CTSUCHAC[4] = 0; + R_CTSU->CTSUCHTRC[0] = 0; + R_CTSU->CTSUCHTRC[1] = 0; + R_CTSU->CTSUCHTRC[2] = 0; + R_CTSU->CTSUCHTRC[3] = 0; + R_CTSU->CTSUCHTRC[4] = 0; + + g_ctsu_diag_info.ctsuwr.ctsussc = (uint16_t) (CTSU_SSDIV_1330 << 8); + g_ctsu_diag_info.ctsuwr.ctsuso1 = (uint16_t) ((CTSU_ICOG_RECOMMEND << 13) | (7 << 8) | CTSU_RICOA_RECOMMEND); + + if (g_ctsu_diag_info.dac_init > 2) + { + /* Apply DAC current */ + if (0 == g_ctsu_diag_info.loop_count) + { + g_ctsu_diag_info.ctsuwr.ctsuso0 = (uint16_t) ((3 << 10) | g_ctsu_diag_info.so0_4uc_val); + } + else if (1 == g_ctsu_diag_info.loop_count) + { + g_ctsu_diag_info.ctsuwr.ctsuso0 = + (uint16_t) ((3 << 10) | (g_ctsu_diag_info.so0_4uc_val - CTSU_DIAG_DAC_1UC)); + } + else if (2 == g_ctsu_diag_info.loop_count) + { + g_ctsu_diag_info.ctsuwr.ctsuso0 = + (uint16_t) ((3 << 10) | (g_ctsu_diag_info.so0_4uc_val - CTSU_DIAG_DAC_2UC)); + } + else if (3 == g_ctsu_diag_info.loop_count) + { + g_ctsu_diag_info.ctsuwr.ctsuso0 = + (uint16_t) ((3 << 10) | (g_ctsu_diag_info.so0_4uc_val - CTSU_DIAG_DAC_4UC)); + } + else if (4 == g_ctsu_diag_info.loop_count) + { + g_ctsu_diag_info.ctsuwr.ctsuso0 = + (uint16_t) ((3 << 10) | (g_ctsu_diag_info.so0_4uc_val - CTSU_DIAG_DAC_8UC)); + } + else if (5 == g_ctsu_diag_info.loop_count) + { + g_ctsu_diag_info.ctsuwr.ctsuso0 = + (uint16_t) ((3 << 10) | (g_ctsu_diag_info.so0_4uc_val - CTSU_DIAG_DAC_16UC)); + } + else + { + } + } + + if (g_ctsu_diag_info.dac_init == 0) + { + g_ctsu_diag_info.dac_init = 1; + g_ctsu_diag_info.so0_4uc_val = 0; + g_ctsu_diag_info.tuning_diff = 0; + g_ctsu_diag_info.ctsuwr.ctsuso0 = (3 << 10) + CTSU_DIAG_DAC_START_VALUE; + } +} + +static void ctsu_diag_dac_data_get (void) +{ + ctsu_correction_calc_t calc; + + calc.snum = (g_ctsu_diag_info.ctsuwr.ctsuso0 >> 10) & CTSU_SNUM_MAX; + + if (CTSU_DIAG_DAC == g_ctsu_diag_info.state) + { + calc.snum = 3; + } + + calc.sdpa = (g_ctsu_diag_info.ctsuwr.ctsuso1 >> 8) & CTSU_SDPA_MAX; + + /* Correction process */ + ctsu_correction_calc(&g_ctsu_diag_info.correct_data, g_ctsu_diag_info.scanbuf.sen, &calc); + + if (g_ctsu_diag_info.tuning == CTSU_TUNING_COMPLETE) + { + g_ctsu_diag_info.dac_cnt[g_ctsu_diag_info.loop_count] = g_ctsu_diag_info.correct_data; + } + else + { + ctsu_diag_dac_initial_tuning(); + } +} + +static fsp_err_t ctsu_diag_dac_result (void) +{ + uint8_t k; + if (g_ctsu_diag_info.tuning == CTSU_TUNING_COMPLETE) + { + for (k = 0; k < 6; k++) + { + if ((g_ctsu_diag_info.dac_cnt[k] > dac_oscil_table[k][0]) || + (g_ctsu_diag_info.dac_cnt[k] < dac_oscil_table[k][1])) + { + return FSP_ERR_CTSU_DIAG_DAC; + } + } + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + + #endif +#endif + +#if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) + +/*********************************************************************************************************************** + * ctsu_diag_scan_start2 + ***********************************************************************************************************************/ +static fsp_err_t ctsu_diag_scan_start2 (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; + fsp_err_t err = FSP_SUCCESS; + + /* initial state change*/ + if (CTSU_DIAG_INIT == g_ctsu_diag_info.state) + { + g_ctsu_diag_info.state = CTSU_DIAG_OUTPUT_VOLTAGE; + } + + /* ctsu normal scan register save */ + ctsu_diag_regi_store2(); + + /* scan register setting */ + if (CTSU_DIAG_OUTPUT_VOLTAGE == g_ctsu_diag_info.state) + { + err = ctsu_diag_output_voltage_scan_start(p_instance_ctrl); + if (FSP_SUCCESS == err) + { + g_ctsu_diag_info.state = CTSU_DIAG_OVER_VOLTAGE; + } + else + { + if (FSP_ERR_ALREADY_OPEN != err) + { + p_adc->p_api->close(p_adc->p_ctrl); + } + + err = FSP_SUCCESS; + + g_ctsu_diag_info.state = CTSU_DIAG_OUTPUT_VOLTAGE; + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + R_CTSU->CTSUCRA_b.LOAD = 0; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + R_CTSU->CTSUCHACA = g_ctsu_diag_info.chaca; + R_CTSU->CTSUCHACB = g_ctsu_diag_info.chacb; + R_CTSU->CTSUCHTRC0 = 0; + R_CTSU->CTSUCHTRC1 = 0; + R_CTSU->CTSUCHTRC2 = 0; + R_CTSU->CTSUCHTRC3 = 0; + R_CTSU->CTSUCHTRC4 = 0; + } + } + + if (CTSU_DIAG_OVER_VOLTAGE == g_ctsu_diag_info.state) + { + ctsu_diag_over_voltage_scan_start(); + g_ctsu_diag_info.state = CTSU_DIAG_OVER_CURRENT; + } + + if (CTSU_DIAG_OVER_CURRENT == g_ctsu_diag_info.state) + { + ctsu_diag_over_current_scan_start(); + } + + if (CTSU_DIAG_LOAD_RESISTANCE == g_ctsu_diag_info.state) + { + ctsu_diag_load_resistance_scan_start(); + } + + if (CTSU_DIAG_CURRENT_SOURCE == g_ctsu_diag_info.state) + { + ctsu_diag_current_source_scan_start(); + } + + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + ctsu_diag_cco_gain_scan_start(); + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + ctsu_diag_cco_gain_scan_start(); + } + + if (CTSU_DIAG_CLOCK_RECOVERY == g_ctsu_diag_info.state) + { + ctsu_diag_clock_recovery_scan_start(); + } + + #if (CTSU_CFG_NUM_CFC != 0) + if (CTSU_DIAG_CFC == g_ctsu_diag_info.state) + { + ctsu_diag_cfc_gain_scan_start(); + } + #endif + + return err; +} + +/*********************************************************************************************************************** + * ctsu_diag_data_get2 + ***********************************************************************************************************************/ +static fsp_err_t ctsu_diag_data_get2 (uint16_t * p_data) +{ + fsp_err_t err; + + if (CTSU_DIAG_LOAD_RESISTANCE == g_ctsu_diag_info.state) + { + ctsu_diag_load_resistance_data_get(); + } + + if (CTSU_DIAG_CURRENT_SOURCE == g_ctsu_diag_info.state) + { + ctsu_diag_current_source_data_get(); + } + + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + ctsu_diag_cco_gain_data_get(); + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + ctsu_diag_cco_gain_data_get(); + } + + if (CTSU_DIAG_CLOCK_RECOVERY == g_ctsu_diag_info.state) + { + ctsu_diag_clock_recovery_data_get(); + } + + #if (CTSU_CFG_NUM_CFC != 0) + if (CTSU_DIAG_CFC == g_ctsu_diag_info.state) + { + ctsu_diag_cfc_gain_data_get(); + } + #endif + + /* DIagnosis state transition */ + if (CTSU_DIAG_OVER_CURRENT == g_ctsu_diag_info.state) + { + g_ctsu_diag_info.loop_count = 0; + g_ctsu_diag_info.state = CTSU_DIAG_LOAD_RESISTANCE; + } + else if ((CTSU_DIAG_LOAD_RESISTANCE == g_ctsu_diag_info.state) && (CTSU_RANGE_NUM <= g_ctsu_diag_info.loop_count)) + { + g_ctsu_diag_info.loop_count = 0; + g_ctsu_diag_info.state = CTSU_DIAG_CURRENT_SOURCE; + } + else if ((CTSU_DIAG_CURRENT_SOURCE == g_ctsu_diag_info.state) && + ((CTSU_DIAG_HIGH_CURRENT_SOURCE + CTSU_DIAG_LOW_CURRENT_SOURCE) <= g_ctsu_diag_info.loop_count)) + { + g_ctsu_diag_info.loop_count = 0; + g_ctsu_diag_info.state = CTSU_DIAG_SENSCLK; + } + else if ((CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) && + (CTSU_CORRECTION_POINT_NUM <= g_ctsu_diag_info.loop_count)) + { + g_ctsu_diag_info.loop_count = 0; + g_ctsu_diag_info.state = CTSU_DIAG_SUCLK; + } + else if ((CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) && (CTSU_CORRECTION_POINT_NUM <= g_ctsu_diag_info.loop_count)) + { + g_ctsu_diag_info.loop_count = 0; + g_ctsu_diag_info.state = CTSU_DIAG_CLOCK_RECOVERY; + } + else if (CTSU_DIAG_CLOCK_RECOVERY == g_ctsu_diag_info.state) + { + #if (CTSU_CFG_NUM_CFC != 0) + g_ctsu_diag_info.state = CTSU_DIAG_CFC; + #else + g_ctsu_diag_info.state = CTSU_DIAG_COMPLETE; + #endif + } + + #if (CTSU_CFG_NUM_CFC != 0) + else if ((CTSU_DIAG_CFC == g_ctsu_diag_info.state) && (CTSU_CORRCFC_POINT_NUM <= g_ctsu_diag_info.loop_count)) + { + g_ctsu_diag_info.loop_count = 0; + g_ctsu_diag_info.state = CTSU_DIAG_COMPLETE; + } + #endif + else + { + } + + if ((CTSU_DIAG_OUTPUT_VOLTAGE <= g_ctsu_diag_info.state) && (CTSU_DIAG_OVER_CURRENT >= g_ctsu_diag_info.state)) + { + *p_data = g_ctsu_diag_info.output_voltage_cnt[0]; + } + else + { + /* Indicates that ADC measurement was not performed. */ + *p_data = CTSU_COUNT_MAX; + } + + /* register restore */ + ctsu_diag_regi_restore2(); + + if (CTSU_DIAG_COMPLETE == g_ctsu_diag_info.state) + { + err = FSP_SUCCESS; + } + else if (CTSU_DIAG_OUTPUT_VOLTAGE == g_ctsu_diag_info.state) + { + err = FSP_ERR_ABORTED; + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + } + else + { + err = FSP_ERR_CTSU_DIAG_NOT_YET; + } + + return err; +} + +static void ctsu_diag_regi_store2 (void) +{ + g_ctsu_diag_reg.ctsucra = R_CTSU->CTSUCRA; + g_ctsu_diag_reg.ctsucrb = R_CTSU->CTSUCRB; + g_ctsu_diag_reg.ctsuchaca = R_CTSU->CTSUCHACA; + g_ctsu_diag_reg.ctsuchacb = R_CTSU->CTSUCHACB; + g_ctsu_diag_reg.ctsuchtrca = R_CTSU->CTSUCHTRCA; + g_ctsu_diag_reg.ctsuchtrcb = R_CTSU->CTSUCHTRCB; + g_ctsu_diag_reg.ctsumch = R_CTSU->CTSUMCH; + g_ctsu_diag_reg.ctsucalib = R_CTSU->CTSUCALIB; + g_ctsu_diag_reg.ctsusuclka = R_CTSU->CTSUSUCLKA; + g_ctsu_diag_reg.ctsusuclkb = R_CTSU->CTSUSUCLKB; +} + +static void ctsu_diag_regi_restore2 (void) +{ + /* register restore */ + R_CTSU->CTSUCRA = g_ctsu_diag_reg.ctsucra; + R_CTSU->CTSUCRB = g_ctsu_diag_reg.ctsucrb; + R_CTSU->CTSUCHACA = g_ctsu_diag_reg.ctsuchaca; + R_CTSU->CTSUCHACB = g_ctsu_diag_reg.ctsuchacb; + R_CTSU->CTSUCHTRCA = g_ctsu_diag_reg.ctsuchtrca; + R_CTSU->CTSUCHTRCB = g_ctsu_diag_reg.ctsuchtrcb; + R_CTSU->CTSUMCH = g_ctsu_diag_reg.ctsumch; + R_CTSU->CTSUCALIB = g_ctsu_diag_reg.ctsucalib; + R_CTSU->CTSUSUCLKA = g_ctsu_diag_reg.ctsusuclka; + R_CTSU->CTSUSUCLKB = g_ctsu_diag_reg.ctsusuclkb; +} + +static fsp_err_t ctsu_diag_output_voltage_scan_start (ctsu_instance_ctrl_t * const p_instance_ctrl) +{ + uint8_t k; + adc_status_t status; + adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; + fsp_err_t err; + + /* Initialize ADC for CTSU TSCAP */ + err = p_adc->p_api->open(p_adc->p_ctrl, p_adc->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = p_adc->p_api->scanCfg(p_adc->p_ctrl, p_adc->p_channel_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if (0 == BSP_FEATURE_ADC_D_IS_AVAILABLE) + R_ADC0->ADSSTRL = CTSU_DIAG_ADSSTRL; + #endif + + /* CTSU setting */ + R_CTSU->CTSUCRA_b.PUMPON = 1; + R_CTSU->CTSUCRA_b.CSW = 1; + R_CTSU->CTSUCRA_b.PON = 1; + R_CTSU->CTSUCALIB = 0; + + /* Self single scan mode */ + R_CTSU->CTSUCRA_b.MD0 = 0; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_0; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + + /* LDO setting */ + R_CTSU->CTSUCALIB_b.DRV = 0; + + for (k = 0; k < 8; k++) + { + switch (k) + { + case 0: + { + /*select normal mode */ + R_CTSU->CTSUCRA_b.LOAD = 0; + + /* LDO Setting (20uA)*/ + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; + break; + } + + case 1: + { + /*select normal mode */ + R_CTSU->CTSUCRA_b.LOAD = 0; + + /* LDO Setting (40uA) */ + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + break; + } + + case 2: + { + /*select normal mode */ + R_CTSU->CTSUCRA_b.LOAD = 0; + + /* LDO Setting (80uA) */ + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + break; + } + + case 3: + { + /*select normal mode */ + R_CTSU->CTSUCRA_b.LOAD = 0; + + /* LDO Setting (160uA) */ + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; + break; + } + + case 4: + { + /*select normal mode */ + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.LOAD = 3; + + /* LDO Setting (20uA) */ + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; + break; + } + + case 5: + { + /* select Resistive load mode */ + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.LOAD = 3; + + /* LDO Setting (40uA) */ + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + break; + } + + case 6: + { + /* select Resistive load mode */ + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.LOAD = 3; + + /* LDO Setting (80uA) */ + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + break; + } + + case 7: + { + /* select Resistive load mode */ + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.LOAD = 3; + + /* LDO Setting (160uA) */ + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; + break; + } + + default: + { + break; + } + } + + R_CTSU->CTSUCALIB_b.DRV = 1; + + /* Measure TSCAP Voltage with ADC */ + err = p_adc->p_api->scanStart(p_adc->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Wait for conversion to complete. */ + status.state = ADC_STATE_SCAN_IN_PROGRESS; + while (ADC_STATE_SCAN_IN_PROGRESS == status.state) + { + err = p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + #if (1 == BSP_FEATURE_ADC_D_IS_AVAILABLE) + err = p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_TSCAP_VOLT, &g_ctsu_diag_info.output_voltage_cnt[k]); + #else + err = p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &g_ctsu_diag_info.output_voltage_cnt[k]); + #endif + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + /* Close ADC for CTSU TSCAP */ + p_adc->p_api->close(p_adc->p_ctrl); + + return err; +} + +static fsp_err_t ctsu_diag_output_voltage_result (void) +{ + uint8_t k; + + for (k = 0; k < 8; k++) + { + if ((g_ctsu_diag_info.output_voltage_cnt[k] <= CTSU_DIAG_TSCAP_RANGE_LOW) || + (g_ctsu_diag_info.output_voltage_cnt[k] >= CTSU_DIAG_TSCAP_RANGE_HIGH)) + { + return FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE; + } + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_over_voltage_scan_start (void) +{ + g_ctsu_diag_info.icomp0_value = 1; + + R_CTSU->CTSUCRA_b.PUMPON = 1; + R_CTSU->CTSUCRA_b.CSW = 1; + R_CTSU->CTSUCRA_b.PON = 1; + R_CTSU->CTSUCALIB = 0; + R_CTSU->CTSUCALIB_b.DRV = 1; + R_CTSU->CTSUCALIB_b.DCOFF = 1; + + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + R_CTSU->CTSUCRA_b.LOAD = 3; + + R_CTSU->CTSUSR_b.ICOMPRST = 1; + R_CTSU->CTSUCALIB = CTSU_DIAG_CURRENT_CLIB_REG; + R_CTSU->CTSUSO = 0; + R_CTSU->CTSUSO = 0; + + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS); + + if (R_CTSU->CTSUSR_b.ICOMP0 != 0) + { + g_ctsu_diag_info.icomp0_value = 0; + } + + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; + R_CTSU->CTSUCRA_b.LOAD = 3; + + R_CTSU->CTSUCALIB = CTSU_DIAG_CURRENT_CLIB_REG; + + R_CTSU->CTSUCRA_b.LOAD = 2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_3; + + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS); + + if (R_CTSU->CTSUSR_b.ICOMP0 != 1) + { + g_ctsu_diag_info.icomp0_value = 0; + } + + R_CTSU->CTSUSR_b.ICOMPRST = 1; + + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS); + + if (R_CTSU->CTSUSR_b.ICOMP0 != 1) + { + g_ctsu_diag_info.icomp0_value = 0; + } + + /* 30kohm setting */ + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCALIB = CTSU_DIAG_CURRENT_CLIB_REG; + + /* 0uA setting */ + R_CTSU->CTSUSO = 0x00000000; + R_CTSU->CTSUSO = 0x00000000; + + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS); + + if (R_CTSU->CTSUSR_b.ICOMP0 != 1) + { + g_ctsu_diag_info.icomp0_value = 0; + } + + R_CTSU->CTSUSR_b.ICOMPRST = 1; + + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS); + + if (R_CTSU->CTSUSR_b.ICOMP0 != 0) + { + g_ctsu_diag_info.icomp0_value = 0; + } +} + +static fsp_err_t ctsu_diag_over_voltage_result (void) +{ + if (0 == g_ctsu_diag_info.icomp0_value) + { + return FSP_ERR_CTSU_DIAG_OVER_VOLTAGE; + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_over_current_scan_start (void) +{ + R_CTSU->CTSUCALIB = 0; + R_CTSU->CTSUCALIB_b.DRV = 0; + R_CTSU->CTSUCALIB_b.DCOFF = 0; + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + R_CTSU->CTSUCRA_b.LOAD = 0; + R_CTSU->CTSUSR_b.ICOMPRST = 1; + + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + + R_CTSU->CTSUCRA_b.MD0 = 1; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + + R_CTSU->CTSUCHACA = g_ctsu_diag_info.chaca; + R_CTSU->CTSUCHACB = g_ctsu_diag_info.chacb; + R_CTSU->CTSUCHTRC0 = 0; + R_CTSU->CTSUCHTRC1 = 0; + R_CTSU->CTSUCHTRC2 = 0; + R_CTSU->CTSUCHTRC3 = 0; + R_CTSU->CTSUCHTRC4 = 0; + + R_CTSU->CTSUCRA_b.CSW = 0; + R_CTSU->CTSUCRA_b.PON = 0; + + /* TSCAP discharge process */ + g_ctsu_tscap_pin_cfg_data.pin_cfg = + ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW); + R_IOPORT_Open(&g_ctsu_tscap_ioport_ctrl, &g_ctsu_tscap_pin_cfg); + R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MICROSECONDS); + g_ctsu_tscap_pin_cfg_data.pin_cfg = + ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU); + R_IOPORT_PinsCfg(&g_ctsu_tscap_ioport_ctrl, &g_ctsu_tscap_pin_cfg); + R_IOPORT_Close(&g_ctsu_tscap_ioport_ctrl); + + R_CTSU->CTSUCRA_b.CSW = 1; + R_CTSU->CTSUCRA_b.PON = 1; +} + +static fsp_err_t ctsu_diag_over_current_result (void) +{ + if (g_ctsu_diag_info.icomp1_value == 0) + { + return FSP_ERR_CTSU_DIAG_OVER_CURRENT; + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_load_resistance_scan_start (void) +{ + /* CTSU setting */ + R_CTSU->CTSUCRA_b.PUMPON = 1; + R_CTSU->CTSUCRA_b.CSW = 1; + R_CTSU->CTSUCRA_b.PON = 1; + + R_CTSU->CTSUCRA_b.SDPSEL = 1; + R_CTSU->CTSUCRA_b.PCSEL = 1; + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND; + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCALIB_b.SUCLKEN = 0; + + R_CTSU->CTSUCRA_b.MD0 = 1; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + R_CTSU->CTSUCRA_b.LOAD = 1; + + /* Setting time of measurement */ + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10); + + R_CTSU->CTSUCHACA = 1; + R_CTSU->CTSUCHACB = 0; + R_CTSU->CTSUCHTRC0 = 0; + R_CTSU->CTSUCHTRC1 = 0; + R_CTSU->CTSUCHTRC2 = 0; + R_CTSU->CTSUCHTRC3 = 0; + R_CTSU->CTSUCHTRC4 = 0; + + R_CTSU->CTSUCALIB_b.TSOC = 1; + + switch (g_ctsu_diag_info.loop_count) + { + case 0: + { + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; // 7.5Kohm 160uA + break; + } + + case 1: + { + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; // 15Kohm 80uA + break; + } + + case 2: + { + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; // 30Kohm 40uA + break; + } + + case 3: + { + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 1; // 60Kohm 20uA + break; + } + + default: + { + break; + } + } + + R_CTSU->CTSUCRA_b.LOAD = 3; +} + +static void ctsu_diag_load_resistance_data_get (void) +{ + g_ctsu_diag_info.load_resistance[g_ctsu_diag_info.loop_count] = (uint16_t) g_ctsu_diag_info.ctsuscnt[0]; + + g_ctsu_diag_info.load_resistance[g_ctsu_diag_info.loop_count] = + (uint16_t) ((((uint32_t) g_ctsu_diag_info.load_resistance[g_ctsu_diag_info.loop_count]) * + g_ctsu_diag_info.error_registance[3 - g_ctsu_diag_info.loop_count]) >> (CTSU_SHIFT_AMOUNT)); + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) + ctsu_correction_calc_t calc; + calc.snum = CTSU_SNUM_RECOMMEND; + calc.range = CTSU_RANGE_40UA; + calc.md = CTSU_MODE_DIAGNOSIS_SCAN; + ctsu_correction_calc(&g_ctsu_diag_info.load_resistance[g_ctsu_diag_info.loop_count], + g_ctsu_diag_info.load_resistance[g_ctsu_diag_info.loop_count], + &calc); + #endif + g_ctsu_diag_info.loop_count++; +} + +static fsp_err_t ctsu_diag_load_resistance_result (void) +{ + uint8_t k; + + for (k = 0; k < 4; k++) + { + if ((g_ctsu_diag_info.load_resistance[k] > CTSU_CFG_DIAG_LOAD_REISTER_MIN) && + (g_ctsu_diag_info.load_resistance[k] < CTSU_CFG_DIAG_LOAD_REISTER_MAX)) + { + } + else + { + return FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE; + } + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_current_source_scan_start (void) +{ + /* CTSU setting */ + R_CTSU->CTSUCRA_b.PUMPON = 1; + R_CTSU->CTSUCRA_b.CSW = 1; + R_CTSU->CTSUCRA_b.PON = 1; + + R_CTSU->CTSUCRA_b.SDPSEL = 1; + R_CTSU->CTSUCRA_b.PCSEL = 1; + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND; + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCALIB_b.SUCLKEN = 0; + + R_CTSU->CTSUCRA_b.MD0 = 1; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + + R_CTSU->CTSUCHACA = 1; + R_CTSU->CTSUCHACB = 0; + R_CTSU->CTSUCHTRC0 = 0; + R_CTSU->CTSUCHTRC1 = 0; + R_CTSU->CTSUCHTRC2 = 0; + R_CTSU->CTSUCHTRC3 = 0; + R_CTSU->CTSUCHTRC4 = 0; + + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_0; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + + /* LDO Nch setting (40uAmode) */ + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCALIB_b.TSOC = 1; + R_CTSU->CTSUCRA_b.ATUNE1 = 1; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + R_CTSU->CTSUCRA_b.LOAD = 3; + + /* DAC initial setting */ + R_CTSU->CTSUCALIB_b.DACMSEL = 1; + R_CTSU->CTSUCALIB_b.DACCARRY = 1; + + R_CTSU->CTSUCRA_b.DCMODE = 0; + R_CTSU->CTSUCRA_b.DCBACK = 0; + + if (15 >= g_ctsu_diag_info.loop_count) + { + /* Upper Current source setting (10uA) */ + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_0; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1; + + switch (g_ctsu_diag_info.loop_count) + { + case 0: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2 + CTSU_DIAG_DAC_0BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + + /* Setting time of measurement */ + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + break; + } + + case 1: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2 + CTSU_DIAG_DAC_1BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + break; + } + + case 2: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2 + CTSU_DIAG_DAC_2BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + break; + } + + case 3: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2 + CTSU_DIAG_DAC_3BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + break; + } + + case 4: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2 + CTSU_DIAG_DAC_4BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + break; + } + + case 5: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2 + CTSU_DIAG_DAC_5BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + break; + } + + case 6: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2 + CTSU_DIAG_DAC_6BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + break; + } + + case 7: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2 + CTSU_DIAG_DAC_7BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + break; + } + + case 8: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_0BIT; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | + (CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_0BIT); + break; + } + + case 9: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_1BIT; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | + (CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_1BIT); + break; + } + + case 10: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_2BIT; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | + (CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_2BIT); + break; + } + + case 11: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_3BIT; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | + (CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_3BIT); + break; + } + + case 12: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_4BIT; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | + (CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_4BIT); + break; + } + + case 13: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_5BIT; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | + (CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_5BIT); + break; + } + + case 14: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_6BIT; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | + (CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_6BIT); + break; + } + + case 15: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_7BIT; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | + (CTSU_DIAG_DAC_INIT_3 + CTSU_DIAG_DAC_7BIT); + break; + } + } + } + + if (16 <= g_ctsu_diag_info.loop_count) + { + /* Lower Current source setting (10uA) */ + switch (g_ctsu_diag_info.loop_count) + { + case 16: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1; + break; + } + + case 17: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - CTSU_DIAG_DAC_0BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + CTSU_DIAG_DAC_0BIT; + break; + } + + case 18: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - (CTSU_DIAG_DAC_0BIT + CTSU_DIAG_DAC_1BIT); + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + (CTSU_DIAG_DAC_0BIT + CTSU_DIAG_DAC_1BIT); + break; + } + + case 19: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - (CTSU_DIAG_DAC_1BIT + CTSU_DIAG_DAC_2BIT); + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + (CTSU_DIAG_DAC_0BIT + CTSU_DIAG_DAC_1BIT); + break; + } + + case 20: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - (CTSU_DIAG_DAC_2BIT + CTSU_DIAG_DAC_3BIT); + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + (CTSU_DIAG_DAC_0BIT + CTSU_DIAG_DAC_1BIT); + break; + } + + case 21: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - (CTSU_DIAG_DAC_3BIT + CTSU_DIAG_DAC_4BIT); + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + (CTSU_DIAG_DAC_0BIT + CTSU_DIAG_DAC_1BIT); + break; + } + + case 22: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - (CTSU_DIAG_DAC_4BIT + CTSU_DIAG_DAC_5BIT); + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + (CTSU_DIAG_DAC_0BIT + CTSU_DIAG_DAC_1BIT); + break; + } + + case 23: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - (CTSU_DIAG_DAC_5BIT + CTSU_DIAG_DAC_6BIT); + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + (CTSU_DIAG_DAC_0BIT + CTSU_DIAG_DAC_1BIT); + break; + } + + case 24: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - (CTSU_DIAG_DAC_6BIT + CTSU_DIAG_DAC_7BIT); + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + (CTSU_DIAG_DAC_0BIT + CTSU_DIAG_DAC_1BIT); + break; + } + + case 25: + { + R_CTSU->CTSUSO = CTSU_DIAG_DAC_DATA_MAX_0 - CTSU_DIAG_DAC_7BIT; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_1 + CTSU_DIAG_DAC_1BIT; + break; + } + } + + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_2; + R_CTSU->CTSUSO = CTSU_DIAG_DAC_INIT_3; + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10) | CTSU_DIAG_DAC_INIT_3; + } +} + +static void ctsu_diag_current_source_data_get (void) +{ + g_ctsu_diag_info.current_source[g_ctsu_diag_info.loop_count] = (uint16_t) g_ctsu_diag_info.ctsuscnt[0]; + + g_ctsu_diag_info.current_source[g_ctsu_diag_info.loop_count] = + (uint16_t) ((((uint32_t) g_ctsu_diag_info.current_source[g_ctsu_diag_info.loop_count]) * + g_ctsu_diag_info.error_registance[2]) >> (CTSU_SHIFT_AMOUNT)); + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 0) + ctsu_correction_calc_t calc; + calc.snum = CTSU_SNUM_RECOMMEND; + calc.range = CTSU_RANGE_40UA; + calc.md = CTSU_MODE_DIAGNOSIS_SCAN; + ctsu_correction_calc(&g_ctsu_diag_info.current_source[g_ctsu_diag_info.loop_count], + g_ctsu_diag_info.current_source[g_ctsu_diag_info.loop_count], &calc); + #endif + g_ctsu_diag_info.loop_count++; +} + +static fsp_err_t ctsu_diag_current_source_result (void) +{ + uint8_t k; + uint16_t current_source_diff; + + for (k = 0; k < (CTSU_DIAG_HIGH_CURRENT_SOURCE + CTSU_DIAG_LOW_CURRENT_SOURCE); k++) + { + current_source_diff = (uint16_t) (g_ctsu_diag_info.load_resistance[2] - g_ctsu_diag_info.current_source[k]); + if ((current_source_diff < CTSU_CFG_DIAG_CURRENT_SOURCE_DIFF_MAX) && + (current_source_diff > CTSU_CFG_DIAG_CURRENT_SOURCE_DIFF_MIN)) + { + } + else + { + return FSP_ERR_CTSU_DIAG_CURRENT_SOURCE; + } + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_cco_gain_scan_start (void) +{ + uint16_t read_reg; + + /* CTSU Setting */ + R_CTSU->CTSUCRA_b.MD0 = 0; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.PON = 1; + R_CTSU->CTSUCRA_b.CSW = 1; + R_CTSU->CTSUCRA_b.PUMPON = 1; + + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + + R_CTSU->CTSUCRB_b.SSMOD = 4; + R_CTSU->CTSUCRB_b.SSCNT = 0; + R_CTSU->CTSUCRB_b.SST = CTSU_SST_RECOMMEND; + + R_CTSU->CTSUCRA_b.PCSEL = 1; + R_CTSU->CTSUCRA_b.SDPSEL = 1; + + R_CTSU->CTSUCALIB = 0; + R_CTSU->CTSUCALIB_b.SUCARRY = 0; + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + + /* Sensor counter auto correction enabled */ + R_CTSU->CTSUOPT_b.CCOCFEN = 0; + #endif + + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + R_CTSU->CTSUCALIB_b.CCOCALIB = 1; + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + R_CTSU->CTSUCALIB_b.CCOCALIB = 0; + } + + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + + R_CTSU->CTSUCHACA = 1; + R_CTSU->CTSUCHACB = 0; + R_CTSU->CTSUCHTRC0 = 0; + R_CTSU->CTSUCHTRC1 = 0; + R_CTSU->CTSUCHTRC2 = 0; + R_CTSU->CTSUCHTRC3 = 0; + R_CTSU->CTSUCHTRC4 = 0; + + /* Setting time of measurement */ + g_ctsu_diag_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10); + + R_CTSU->CTSUMCH_b.MCH0 = 0; + + if (g_ctsu_diag_info.loop_count < 8) + { + read_reg = R_CTSU->CTSUSUCLK0; + read_reg = + (uint16_t) ((read_reg & CTSU_DIAG_SUCLK0_REG1) | + (0x1f + (g_ctsu_diag_info.loop_count * CTSU_DIAG_SUCLK0_REG2))); + R_CTSU->CTSUSUCLK0 = read_reg; + } + else if ((8 <= g_ctsu_diag_info.loop_count) && (g_ctsu_diag_info.loop_count < 11)) + { + read_reg = R_CTSU->CTSUSUCLK0; + read_reg = + (uint16_t) ((read_reg & CTSU_DIAG_SUCLK0_REG1) | (0x1f + (7 * CTSU_DIAG_SUCLK0_REG2))); + R_CTSU->CTSUSUCLK0 = read_reg; + + if (8 == g_ctsu_diag_info.loop_count) + { + R_CTSU->CTSUCRB_b.SSCNT = 0; + } + else if (9 == g_ctsu_diag_info.loop_count) + { + R_CTSU->CTSUCRB_b.SSCNT = 1; + } + else if (10 == g_ctsu_diag_info.loop_count) + { + R_CTSU->CTSUCRB_b.SSCNT = 2; + } + else + { + } + + R_CTSU->CTSUCALIB_b.SUCARRY = 0; + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + R_CTSU->CTSUCALIB_b.CCOCALIB = 1; + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + R_CTSU->CTSUCALIB_b.CCOCALIB = 0; + } + + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCRB_b.SSMOD = 1; + R_CTSU->CTSUCRB_b.SST = CTSU_SST_RECOMMEND_CURRENT; + if (8 == g_ctsu_diag_info.loop_count) + { + R_CTSU->CTSUCRB_b.SSCNT = 1; + } + else if (9 == g_ctsu_diag_info.loop_count) + { + R_CTSU->CTSUCRB_b.SSCNT = 2; + } + else if (10 == g_ctsu_diag_info.loop_count) + { + R_CTSU->CTSUCRB_b.SSCNT = 3; + } + else + { + } + } + else if (11 == g_ctsu_diag_info.loop_count) + { + read_reg = R_CTSU->CTSUSUCLK0; + read_reg = + (uint16_t) ((read_reg & CTSU_DIAG_SUCLK0_REG1) | (0x1f + (7 * CTSU_DIAG_SUCLK0_REG2))); + R_CTSU->CTSUSUCLK0 = read_reg; + + R_CTSU->CTSUCRB_b.SSCNT = 2; + R_CTSU->CTSUCALIB_b.SUCARRY = 1; + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + R_CTSU->CTSUCALIB_b.CCOCALIB = 1; + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + R_CTSU->CTSUCALIB_b.CCOCALIB = 0; + } + + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCRB_b.SSMOD = 1; + R_CTSU->CTSUCRB_b.SST = CTSU_SST_RECOMMEND_CURRENT; + R_CTSU->CTSUCRB_b.SSCNT = 3; + } + else + { + } +} + +static void ctsu_diag_cco_gain_data_get (void) +{ + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + g_ctsu_diag_info.sensclk_cnt[g_ctsu_diag_info.loop_count] = (uint16_t) g_ctsu_diag_info.ctsuscnt[0]; + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + g_ctsu_diag_info.suclk_cnt[g_ctsu_diag_info.loop_count] = (uint16_t) (g_ctsu_diag_info.ctsuscnt[0] >> 16); + } + + g_ctsu_diag_info.loop_count++; + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + + /* Sensor counter auto correction enabled */ + R_CTSU->CTSUOPT_b.CCOCFEN = 1; + #endif +} + +static fsp_err_t ctsu_diag_cco_gain_result (void) +{ + uint32_t k; + volatile uint16_t cco_gain_data; + uint16_t cco_gain_data_pre; + uint16_t cco_gain_diff; + uint16_t cco_gain_max; + uint16_t cco_gain_min; + uint16_t cco_gain_diff_max; + uint16_t cco_gain_diff_min; + + /* read counter data */ + for (k = 0; k < CTSU_CORRECTION_POINT_NUM; k++) + { + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + cco_gain_data = g_ctsu_diag_info.sensclk_cnt[k]; + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + cco_gain_data = g_ctsu_diag_info.suclk_cnt[k]; + } + + cco_gain_max = cco_gain_table[k][1]; + cco_gain_min = cco_gain_table[k][0]; + + /* check measurement result */ + if ((cco_gain_data <= cco_gain_max) && (cco_gain_data >= cco_gain_min)) + { + } + else + { + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + return FSP_ERR_CTSU_DIAG_SENSCLK_GAIN; + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + return FSP_ERR_CTSU_DIAG_SUCLK_GAIN; + } + } + + if (0 < k) + { + cco_gain_diff_max = cco_gain_diff_table[k - 1][1]; + cco_gain_diff_min = cco_gain_diff_table[k - 1][0]; + + if (cco_gain_data > cco_gain_data_pre) + { + cco_gain_diff = (uint16_t) (cco_gain_data - cco_gain_data_pre); + } + else + { + cco_gain_diff = (uint16_t) (cco_gain_data_pre - cco_gain_data); + } + + /* check measurement result */ + if ((cco_gain_diff > cco_gain_diff_max) || (cco_gain_diff < cco_gain_diff_min)) + { + if (CTSU_DIAG_SENSCLK == g_ctsu_diag_info.state) + { + return FSP_ERR_CTSU_DIAG_SENSCLK_GAIN; + } + + if (CTSU_DIAG_SUCLK == g_ctsu_diag_info.state) + { + return FSP_ERR_CTSU_DIAG_SUCLK_GAIN; + } + } + } + + cco_gain_data_pre = cco_gain_data; + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + +static void ctsu_diag_clock_recovery_scan_start (void) +{ + R_CTSU->CTSUCRA = g_ctsu_diag_reg.ctsucra; + R_CTSU->CTSUCRA_b.MD0 = 1; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 0; + R_CTSU->CTSUMCH = g_ctsu_diag_reg.ctsumch; + R_CTSU->CTSUCRB = g_ctsu_diag_reg.ctsucrb; + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRB_b.SSCNT = 1; + R_CTSU->CTSUCALIB_b.SUCARRY = 0; + R_CTSU->CTSUCALIB_b.CCOCALIB = 0; + R_CTSU->CTSUCALIB_b.CCOCLK = 1; + R_CTSU->CTSUCALIB_b.TSOC = 0; + R_CTSU->CTSUCALIB_b.SUCLKEN = 1; + + R_CTSU->CTSUCRA_b.SDPSEL = 0; + R_CTSU->CTSUSUCLKA = g_ctsu_diag_reg.ctsusuclka; + R_CTSU->CTSUSUCLKB = g_ctsu_diag_reg.ctsusuclkb; + R_CTSU->CTSUCRA_b.SDPSEL = 1; + + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 1; + R_CTSU->CTSUMCH_b.MCA2 = 1; + R_CTSU->CTSUMCH_b.MCA3 = 0; + + R_CTSU->CTSUCHACA = g_ctsu_diag_info.chaca; + R_CTSU->CTSUCHACB = g_ctsu_diag_info.chacb; + + R_CTSU->CTSUCHTRC0 = 0; + R_CTSU->CTSUCHTRC1 = 0; + R_CTSU->CTSUCHTRC2 = 0; + R_CTSU->CTSUCHTRC3 = 0; + R_CTSU->CTSUCHTRC4 = 0; + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + + /* Sensor counter auto correction enabled */ + R_CTSU->CTSUOPT_b.CCOCFEN = 0; + #endif + + /* Setting time of measurement */ + + g_ctsu_diag_info.ctsuwr.ctsuso = (uint32_t) ((0xf << 24) | (CTSU_SNUM_RECOMMEND << 10)); +} + +static void ctsu_diag_clock_recovery_data_get (void) +{ + uint8_t i; + for (i = 0; i < 3; i++) + { + g_ctsu_diag_info.suclk_count_clk_recv[i] = (uint16_t) (g_ctsu_diag_info.ctsuscnt[i] >> 16); + } + + #if (CTSU_CFG_AUTO_CORRECTION_ENABLE == 1) + + /* Sensor counter auto correction enabled */ + R_CTSU->CTSUOPT_b.CCOCFEN = 1; + #endif +} + +static fsp_err_t ctsu_diag_clock_recovery_result (void) +{ + uint8_t i; + uint32_t suclk[3]; + static uint32_t suclk_cnt[3]; + + suclk[0] = (CTSU_DIAG_STCLK_FREQ * (CTSU_CFG_SUMULTI0 + 1)); + suclk[1] = (CTSU_DIAG_STCLK_FREQ * (CTSU_CFG_SUMULTI1 + 1)); + suclk[2] = (CTSU_DIAG_STCLK_FREQ * (CTSU_CFG_SUMULTI2 + 1)); + + for (i = 0; i < 3; i++) + { + suclk_cnt[i % 3] = ((suclk[i % 3] * (CTSU_SNUM_RECOMMEND + 1)) / CTSU_DIAG_STCLK_FREQ) * 8 * 2; + + /* suclk check */ + if ((suclk_cnt[i % 3] + CTSU_CFG_DIAG_CLOCK_RECOV_RANGE) < g_ctsu_diag_info.suclk_count_clk_recv[i]) + { + return FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY; + } + + if ((suclk_cnt[i % 3] - CTSU_CFG_DIAG_CLOCK_RECOV_RANGE) > g_ctsu_diag_info.suclk_count_clk_recv[i]) + { + return FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY; + } + } + + /* if all checks passed to this point, return success */ + return FSP_SUCCESS; +} + + #if (CTSU_CFG_NUM_CFC != 0) +static void ctsu_diag_cfc_gain_scan_start (void) +{ + /* CTSU Setting */ + R_CTSU->CTSUCRA_b.MD0 = 1; + R_CTSU->CTSUCRA_b.MD1 = 0; + R_CTSU->CTSUCRA_b.MD2 = 1; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRA_b.CFCON = 1; + R_CTSU->CTSUCRA_b.PUMPON = 1; + R_CTSU->CTSUCRA_b.TXVSEL = 1; + + R_CTSU->CTSUCRB_b.SSMOD = 0; + R_CTSU->CTSUCRB_b.SSCNT = 0; + R_CTSU->CTSUCRB_b.SST = 0x1F; + + R_CTSU->CTSUCRA_b.PCSEL = 1; + R_CTSU->CTSUCRA_b.SDPSEL = 1; + + R_CTSU->CTSUCALIB = 0; + R_CTSU->CTSUCALIB_b.SUCARRY = 0; + R_CTSU->CTSUCALIB_b.CCOCALIB = 0; + R_CTSU->CTSUCALIB_b.CCOCLK = 0; + R_CTSU->CTSUCALIB_b.CFCMODE = 1; + R_CTSU->CTSUCALIB_b.CFCRDMD = 1; + + if (CTSU_DIAG_CHACA_TSMAX > g_ctsu_corrcfc_info.ts_table[0]) + { + R_CTSU->CTSUCHACA = (uint32_t) (1 << g_ctsu_corrcfc_info.ts_table[0]); + R_CTSU->CTSUCHACB = 0; + } + else + { + R_CTSU->CTSUCHACA = 0; + R_CTSU->CTSUCHACB = (uint32_t) (1 << (g_ctsu_corrcfc_info.ts_table[0] - CTSU_DIAG_CHACA_TSMAX)); + } + + R_CTSU->CTSUCHTRC0 = 0; + R_CTSU->CTSUCHTRC1 = 0; + R_CTSU->CTSUCHTRC2 = 0; + R_CTSU->CTSUCHTRC3 = 0; + R_CTSU->CTSUCHTRC4 = 0; + + R_CTSU->CTSUMCH_b.MCH0 = 0; + + R_CTSU->CTSUCRA_b.SDPSEL = 0; + R_CTSU->CTSUSUCLK0 = + (uint16_t) (((g_ctsu_diag_info.loop_count + CTSU_CORRCFC_CENTER_POINT) * CTSU_CORRECTION_SUMULTI) - 1); + R_CTSU->CTSUCRA_b.SDPSEL = 1; + + g_ctsu_diag_info.ctsuwr.ctsuso = (uint32_t) (CTSU_SNUM_RECOMMEND << 10); +} + +static void ctsu_diag_cfc_gain_data_get (void) +{ + g_ctsu_diag_info.cfc_cnt[g_ctsu_diag_info.loop_count] = (uint16_t) g_ctsu_diag_info.ctsuscnt[0]; + + g_ctsu_diag_info.loop_count++; +} + +static fsp_err_t ctsu_diag_cfc_gain_result (void) +{ + uint8_t k; + + for (k = 0; k < (CTSU_CORRCFC_POINT_NUM - 1); k++) + { + if (g_ctsu_diag_info.cfc_cnt[k + 1] > g_ctsu_diag_info.cfc_cnt[k]) + { + /* PASS */ + } + else + { + + /* FAIL */ + return FSP_ERR_CTSU_DIAG_CFC_GAIN; + } + } + + return FSP_SUCCESS; +} + + #endif + #endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dac/r_dac.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dac/r_dac.c new file mode 100644 index 0000000000..5c72069a2a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dac/r_dac.c @@ -0,0 +1,435 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_dac.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* D/A Control Register Mask */ +/** Driver ID (DAC in ASCII), used to identify Digital to Analog Converter (DAC) configuration */ +#define DAC_OPEN (0x44414300) +#define DAC_DAADSCR_REG_DAADST_BIT_POS (0x07U) +#define DAC_DAADUSR_REG_MASK BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK +#define DAC_DADPR_REG_DPSEL_BIT_POS (0x07U) +#define DAC_DAAMPCR_AMP_CTRL_BITS (0x06U) /* 6th bit for channel 0; 7th bit for channel 1 */ +#define DAC_DACR_DAOE_BITS (0x06U) /* 6th bit for channel 0; 7th bit for channel 1 */ +#define DAC_DAASWCR_DAASW0_MASK (0x40) +#define DAC_DAASWCR_DAASW1_MASK (0x80) +#if 0x01U == BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK + #define DAC_ADC_UNIT (0) +#elif 0x02U == BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK + #define DAC_ADC_UNIT (1) +#endif + +/* Conversion time with Output Amplifier. See hardware manual (see Table + * "D/A conversion characteristics" in the DAC12 Characteristics section of the relevant hardware manual.) */ +#define DAC_CONVERSION_TIME_WITH_OUTPUT_AMPLIFIER (0x04U) /* Unit: Microseconds. */ + +#define DAC_VREF_DISCHARGING_DELAY_US (10) +#define DAC_INTERNAL_VREF_WAIT_TIME_US (5) +#define DAC12_CHANNEL_COUNT (BSP_FEATURE_DAC12_CHANNELS_PER_UNIT * \ + BSP_FEATURE_DAC12_UNIT_COUNT) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +const dac_api_t g_dac_on_dac = +{ + .open = R_DAC_Open, + .write = R_DAC_Write, + .start = R_DAC_Start, + .stop = R_DAC_Stop, + .close = R_DAC_Close, +}; + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup DAC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Perform required initialization described in hardware manual. Implements @ref dac_api_t::open. + * Configures a single DAC channel, starts the channel, and provides a handle for use with the + * DAC API Write and Close functions. Must be called once prior to calling any other DAC API + * functions. After a channel is opened, Open should not be called again for the same channel + * without calling Close first. + * + * @retval FSP_SUCCESS The channel was successfully opened. + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. One or both of the following parameters may be NULL: p_api_ctrl or p_cfg + * 2. data_format value in p_cfg is out of range. + * 3. Extended configuration structure is set to NULL for + * MCU supporting charge pump. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel ID requested in p_cfg may not available on the devices. + * @retval FSP_ERR_ALREADY_OPEN The control structure is already opened. + * + **********************************************************************************************************************/ +fsp_err_t R_DAC_Open (dac_ctrl_t * p_api_ctrl, dac_cfg_t const * const p_cfg) +{ + dac_instance_ctrl_t * p_ctrl = (dac_instance_ctrl_t *) p_api_ctrl; + + /* Validate the input parameter. */ +#if DAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_cfg->channel < (uint8_t) DAC12_CHANNEL_COUNT, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(false == p_ctrl->channel_opened, FSP_ERR_ALREADY_OPEN); + #if (BSP_FEATURE_DAC_HAS_CHARGEPUMP || BSP_FEATURE_DAC_HAS_DAVREFCR) + FSP_ASSERT(NULL != p_cfg->p_extend) + #endif +#endif + +#if (DAC12_CHANNEL_COUNT > 2U) + uint8_t unit = p_cfg->channel / BSP_FEATURE_DAC12_CHANNELS_PER_UNIT; + p_ctrl->p_reg = (R_DAC_Type *) ((uint32_t) R_DAC0 + (unit * ((uint32_t) R_DAC1 - (uint32_t) R_DAC0))); +#else + p_ctrl->p_reg = R_DAC; +#endif + + p_ctrl->channel_index = p_cfg->channel % BSP_FEATURE_DAC12_CHANNELS_PER_UNIT; + + /* Power on the DAC device. */ + uint8_t dac_unit = p_cfg->channel / BSP_FEATURE_DAC12_CHANNELS_PER_UNIT; + R_BSP_MODULE_START(FSP_IP_DAC, dac_unit); + + /* Added this to a separate block to avoid redeclaration of + * critical section variable under module start macro. */ + { + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Stop the channel. */ + (0U == p_ctrl->channel_index) ? (p_ctrl->p_reg->DACR_b.DAOE0 = 0U) : (p_ctrl->p_reg->DACR_b.DAOE1 = 0U); + + FSP_CRITICAL_SECTION_EXIT; + } + + dac_extended_cfg_t * p_extend = (dac_extended_cfg_t *) p_cfg->p_extend; + + /* Configure data format: left or right justified. */ + p_ctrl->p_reg->DADPR = (uint8_t) ((uint8_t) p_extend->data_format << (uint8_t) DAC_DADPR_REG_DPSEL_BIT_POS); + +#if BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE + #if BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK + + /* DA/AD Synchronization. Described in hardware manual (see + * "D/A A/D Synchronous Unit Select Register (DAADUSR)" and + * "D/A A/D Synchronous Start Control Register (DAADSCR)" descriptions in the DAC section of the relevant hardware manual). + * D/A A/D Synchronous Unit Select Register: Select ADC Unit for synchronization with this DAC channel */ + if ((0U == p_ctrl->p_reg->DAADSCR) && (p_cfg->ad_da_synchronized)) + { + /* For correctly writing to this register: + * 1. ADC module stop bit must be cleared. + * 2. DAADSCR.DAADST must be cleared. + * + * If ADC module is started, this will have no effect. + * + * If ADC module is not started yet, this will start it for enabling write to DAADUSR. + * Since the ad_da_synchronized is set to true in the configuration structure + * the ADC module is believed to be started at a later point in the application. + */ + R_BSP_MODULE_START(FSP_IP_ADC, (uint16_t) DAC_ADC_UNIT); + + p_ctrl->p_reg->DAADUSR = (uint8_t) BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK; + + /* Configure D/A-A/D Synchronous Start Control Register(DAADSCR). */ + p_ctrl->p_reg->DAADSCR = (uint8_t) (1U << (uint8_t) DAC_DAADSCR_REG_DAADST_BIT_POS); + } + #else + + /* Configure D/A-A/D Synchronous Start Control Register(DAADSCR). */ + p_ctrl->p_reg->DAADSCR = (uint8_t) (p_cfg->ad_da_synchronized << (uint8_t) DAC_DAADSCR_REG_DAADST_BIT_POS); + #endif +#endif + +#if BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER + p_ctrl->output_amplifier_enabled = p_extend->output_amplifier_enabled; +#endif + +#if BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL + p_ctrl->internal_output_enabled = p_extend->internal_output_enabled; +#endif + + /* Set the reference voltage. */ +#if BSP_FEATURE_DAC_HAS_DAVREFCR + + /* D/A Reference Voltage Select. Described in hardware manual (see + * "D/A VREF Control Register (DAVREFCR)" description and + * "Notes on Using the Internal Reference Voltage as the Reference Voltage" in the DAC Operation section of + * the relevant hardware manual). *//* Clear REF bits before changing the value of these bits. */ + p_ctrl->p_reg->DAVREFCR = 0x00; + if (DAC_VREF_IVREF_AVSS0 == p_extend->ref_volt_sel) + { + p_ctrl->p_reg->DADR[0] = 0x00U; + + /* Discharge for 10 us. */ + R_BSP_SoftwareDelay(DAC_VREF_DISCHARGING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + p_ctrl->p_reg->DAVREFCR = (uint8_t) p_extend->ref_volt_sel; + p_ctrl->p_reg->DACR_b.DAOE0 = 1U; + + /* Wait 5 us, the stabilization wait time of the internal reference voltage. */ + R_BSP_SoftwareDelay(DAC_INTERNAL_VREF_WAIT_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else + { + p_ctrl->p_reg->DAVREFCR = (uint8_t) p_extend->ref_volt_sel; + } + FSP_REGISTER_READ(p_ctrl->p_reg->DAVREFCR) +#endif + +#if (1U == BSP_FEATURE_DAC_HAS_CHARGEPUMP) + p_ctrl->p_reg->DAPC = (uint8_t) p_extend->enable_charge_pump; +#endif + + /* Initialize the channel state information. */ + p_ctrl->channel = p_cfg->channel; + p_ctrl->channel_opened = DAC_OPEN; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Write data to the D/A converter and enable the output if it has not been enabled. + * + * @retval FSP_SUCCESS Data is successfully written to the D/A Converter. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Channel associated with p_ctrl has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_DAC_Write (dac_ctrl_t * p_api_ctrl, uint16_t value) +{ + dac_instance_ctrl_t * p_ctrl = (dac_instance_ctrl_t *) p_api_ctrl; + +#if DAC_CFG_PARAM_CHECKING_ENABLE + + /* Validate the handle parameter */ + FSP_ASSERT(NULL != p_ctrl); + + /* Validate that the channel is opened. */ + FSP_ERROR_RETURN(p_ctrl->channel_opened, FSP_ERR_NOT_OPEN); +#endif + + /* Write the value to D/A converter. */ + p_ctrl->p_reg->DADR[p_ctrl->channel_index] = value; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Start the D/A conversion output if it has not been started. + * + * @retval FSP_SUCCESS The channel is started successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_IN_USE Attempt to re-start a channel. + * @retval FSP_ERR_NOT_OPEN Channel associated with p_ctrl has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_DAC_Start (dac_ctrl_t * p_api_ctrl) +{ + dac_instance_ctrl_t * p_ctrl = (dac_instance_ctrl_t *) p_api_ctrl; + +#if DAC_CFG_PARAM_CHECKING_ENABLE + + /* Validate the handle parameter */ + FSP_ASSERT(NULL != p_ctrl); + + /* Validate that the channel is opened. */ + FSP_ERROR_RETURN(p_ctrl->channel_opened, FSP_ERR_NOT_OPEN); + + /* Check if the channel is not already started */ + bool channel_started = false; + + channel_started = + ((0U == p_ctrl->channel_index) ? ((bool) p_ctrl->p_reg->DACR_b.DAOE0) : (bool) (p_ctrl->p_reg->DACR_b.DAOE1)); + + FSP_ERROR_RETURN(!channel_started, FSP_ERR_IN_USE); +#endif + +#if BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER + + /* Initialize output amplifier. Described in hardware manual (see + * "Initialization Procedure with the Output Amplifier" in the DAC section of the relevant hardware manual). */ + if (p_ctrl->output_amplifier_enabled) + { + /* Store value intended to be amplified during DAC output */ + uint16_t value = p_ctrl->p_reg->DADR[p_ctrl->channel_index]; + + /* Clear the D/A Data Register for the requested channel. */ + p_ctrl->p_reg->DADR[p_ctrl->channel_index] = 0x00U; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if (0U == p_ctrl->channel_index) + { + p_ctrl->p_reg->DACR_b.DAOE0 = 0U; /* Disable channel 0 */ + p_ctrl->p_reg->DAASWCR_b.DAASW0 = 1U; /* Enable D/A Amplifier Stabilization Wait for channel 0 */ + p_ctrl->p_reg->DAAMPCR_b.DAAMP0 = 1U; /* Enable amplifier control for channel 0 */ + p_ctrl->p_reg->DACR_b.DAOE0 = 1U; /* Enable channel 0 to start D/A conversion of 0x00 */ + } + else + { + p_ctrl->p_reg->DACR_b.DAOE1 = 0U; /* Disable channel 1 */ + p_ctrl->p_reg->DAASWCR_b.DAASW1 = 1U; /* Enable D/A Amplifier Stabilization Wait for channel 1 */ + p_ctrl->p_reg->DAAMPCR_b.DAAMP1 = 1U; /* Enable amplifier control for channel 1 */ + p_ctrl->p_reg->DACR_b.DAOE1 = 1U; /* Enable channel 1 to start D/A conversion of 0x00 */ + } + + FSP_CRITICAL_SECTION_EXIT; + + /* The System clock will be running at this point. It is safe to use this function. */ + R_BSP_SoftwareDelay((uint32_t) DAC_CONVERSION_TIME_WITH_OUTPUT_AMPLIFIER, BSP_DELAY_UNITS_MICROSECONDS); + + FSP_CRITICAL_SECTION_ENTER; + + /* Disable D/A Amplifier Stabilization Wait for channel 0 or 1 */ + (0U == + p_ctrl->channel_index) ? (p_ctrl->p_reg->DAASWCR_b.DAASW0 = 0U) : (p_ctrl->p_reg->DAASWCR_b.DAASW1 = 0U); + + FSP_CRITICAL_SECTION_EXIT; + + /* Revert value intended to be amplified during DAC output. */ + p_ctrl->p_reg->DADR[p_ctrl->channel_index] = value; + } + else +#endif + { + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if (0U == p_ctrl->channel_index) + { +#if BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL + p_ctrl->p_reg->DACR_b.DAOE0 = 0U; /* Disable channel 0 */ + p_ctrl->p_reg->DAASWCR_b.DAASW0 = p_ctrl->internal_output_enabled; /* Disable channel 0 internal output. */ +#endif + + /* Enable channel 0 to start D/A conversion of 0x00 */ + p_ctrl->p_reg->DACR_b.DAOE0 = 1U; + } + else + { +#if BSP_FEATURE_DAC_HAS_DAASWCR_INTERNAL_OUTPUT_CONTROL + p_ctrl->p_reg->DACR_b.DAOE1 = 0U; /* Disable channel 1 */ + p_ctrl->p_reg->DAASWCR_b.DAASW1 = p_ctrl->internal_output_enabled; /* Disable channel 1 internal output. */ +#endif + + /* Enable channel 1 to start D/A conversion of 0x00 */ + p_ctrl->p_reg->DACR_b.DAOE1 = 1U; + } + + FSP_CRITICAL_SECTION_EXIT; + } + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Stop the D/A conversion and disable the output signal. + * + * @retval FSP_SUCCESS The control is successfully stopped. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Channel associated with p_ctrl has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_DAC_Stop (dac_ctrl_t * p_api_ctrl) +{ + dac_instance_ctrl_t * p_ctrl = (dac_instance_ctrl_t *) p_api_ctrl; + +#if DAC_CFG_PARAM_CHECKING_ENABLE + + /* Validate the handle parameter */ + FSP_ASSERT(NULL != p_ctrl); + + /* Validate that the channel is opened. */ + FSP_ERROR_RETURN(p_ctrl->channel_opened, FSP_ERR_NOT_OPEN); +#endif + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Stop the channel */ + (0U == p_ctrl->channel_index) ? (p_ctrl->p_reg->DACR_b.DAOE0 = 0U) : (p_ctrl->p_reg->DACR_b.DAOE1 = 0U); + + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Stop the D/A conversion, stop output, and close the DAC channel. + * + * @retval FSP_SUCCESS The channel is successfully closed. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Channel associated with p_ctrl has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_DAC_Close (dac_ctrl_t * p_api_ctrl) +{ + dac_instance_ctrl_t * p_ctrl = (dac_instance_ctrl_t *) p_api_ctrl; + +#if DAC_CFG_PARAM_CHECKING_ENABLE + + /* Validate the handle parameter */ + FSP_ASSERT(NULL != p_ctrl); + + /* Validate that the channel is opened. */ + FSP_ERROR_RETURN(p_ctrl->channel_opened, FSP_ERR_NOT_OPEN); +#endif + + /* Module Stop is not needed here as this module does not have channel specific Start/Stop control. + * For more than 1 channels used (on selected MCUs), a module stop will disable both the channels. */ + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Stop the channel, clear the amplifier stabilization wait bit and + * clear the output amplifier control register for the associated channel. */ + if (0U == p_ctrl->channel_index) + { + p_ctrl->p_reg->DACR_b.DAOE0 = 0U; /* Disable channel 0 */ + p_ctrl->p_reg->DAAMPCR_b.DAAMP0 = 0U; /* Disable amplifier control for channel 0 */ + } + else + { + p_ctrl->p_reg->DACR_b.DAOE1 = 0U; /* Disable channel 1 */ + p_ctrl->p_reg->DAAMPCR_b.DAAMP1 = 0U; /* Disable amplifier control for channel 1 */ + } + + FSP_CRITICAL_SECTION_EXIT; + + /* Update the channel state information. */ + p_ctrl->channel_opened = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup DAC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dmac/r_dmac.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dmac/r_dmac.c new file mode 100644 index 0000000000..3d807b0844 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dmac/r_dmac.c @@ -0,0 +1,800 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_dmac.h" +#include "r_dmac_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Driver ID (DMAC in ASCII) */ +#define DMAC_ID (0x444d4143) + +/** Length limited to 1024 transfers for repeat and block mode */ +#define DMAC_REPEAT_BLOCK_MAX_LENGTH (0x400) + +#define DMAC_PRV_MASK_ALIGN_2_BYTES (0x1U) +#define DMAC_PRV_MASK_ALIGN_4_BYTES (0x3U) + +/* Calculate the mask bits for byte alignment from the transfer_size_t. */ +#define DMAC_PRV_MASK_ALIGN_N_BYTES(x) ((1U << (x)) - 1U) + +#define DMAC_PRV_REG(ch) ((R_DMAC0_Type *) (((uint32_t) R_DMAC1 - (uint32_t) R_DMAC0) * ch + \ + (uint32_t) R_DMAC0)) + +/* Transfer Count Register A Bit Field Definitions */ +#define DMAC_PRV_DMCRA_LOW_OFFSET (0U) +#define DMAC_PRV_DMCRA_LOW_MASK (0x3FFU << DMAC_PRV_DMCRA_LOW_OFFSET) +#define DMAC_PRV_DMCRA_HIGH_OFFSET (16U) +#define DMAC_PRV_DMCRA_HIGH_MASK (0x3FFU << DMAC_PRV_DMCRA_HIGH_OFFSET) + +/* Transfer Mode Register Bit Field Definitions */ +#define DMAC_PRV_DMTMD_DCTG_OFFSET (0U) +#define DMAC_PRV_DMTMD_DCTG_MASK (3U << DMAC_PRV_DMTMD_DCTG_OFFSET) +#define DMAC_PRV_DMTMD_SZ_OFFSET (8U) +#define DMAC_PRV_DMTMD_SZ_MASK (3U << DMAC_PRV_DMTMD_SZ_OFFSET) +#define DMAC_PRV_DMTMD_DTS_OFFSET (12U) +#define DMAC_PRV_DMTMD_DTS_MASK (3U << DMAC_PRV_DMTMD_DTS_OFFSET) +#define DMAC_PRV_DMTMD_MD_OFFSET (14U) +#define DMAC_PRV_DMTMD_MD_MASK (3U << DMAC_PRV_DMTMD_MD_OFFSET) + +/* Interrupt Setting Register Bit Field Definitions */ +#define DMAC_PRV_DMINT_DARIE_OFFSET (0U) +#define DMAC_PRV_DMINT_DARIE_MASK (1U << DMAC_PRV_DMINT_DARIE_OFFSET) +#define DMAC_PRV_DMINT_SARIE_OFFSET (1U) +#define DMAC_PRV_DMINT_SARIE_MASK (1U << DMAC_PRV_DMINT_SARIE_OFFSET) +#define DMAC_PRV_DMINT_RPTIE_OFFSET (2U) +#define DMAC_PRV_DMINT_RPTIE_MASK (1U << DMAC_PRV_DMINT_RPTIE_OFFSET) +#define DMAC_PRV_DMINT_ESIE_OFFSET (3U) +#define DMAC_PRV_DMINT_ESIE_MASK (1U << DMAC_PRV_DMINT_ESIE_OFFSET) +#define DMAC_PRV_DMINT_DTIE_OFFSET (4U) +#define DMAC_PRV_DMINT_DTIE_MASK (1U << DMAC_PRV_DMINT_DTIE_OFFSET) + +/* Address Mode Register Bit Field Definitions */ +#define DMAC_PRV_DMAMD_DARA_OFFSET (0U) +#define DMAC_PRV_DMAMD_DARA_MASK (0x1FU << DMAC_PRV_DMAMD_DARA_OFFSET) +#define DMAC_PRV_DMAMD_DM_OFFSET (6U) +#define DMAC_PRV_DMAMD_DM_MASK (3U << DMAC_PRV_DMAMD_DM_OFFSET) +#define DMAC_PRV_DMAMD_SARA_OFFSET (8U) +#define DMAC_PRV_DMAMD_SARA_MASK (0x1FU << DMAC_PRV_DMAMD_SARA_OFFSET) +#define DMAC_PRV_DMAMD_SM_OFFSET (14U) +#define DMAC_PRV_DMAMD_SM_MASK (3U << DMAC_PRV_DMAMD_SM_OFFSET) + +/* Software Start Register Bit Field Definitions */ +#define DMAC_PRV_DMREQ_SWREQ_OFFSET (0U) +#define DMAC_PRV_DMREQ_SWREQ_MASK (1U << DMAC_PRV_DMREQ_SWREQ_OFFSET) +#define DMAC_PRV_DMREQ_CLRS_OFFSET (4U) +#define DMAC_PRV_DMREQ_CLRS_MASK (1U << DMAC_PRV_DMREQ_CLRS_OFFSET) + +#ifndef DMAC_CFG_ERROR_CHANNEL_CLEAR + #define DMAC_CFG_ERROR_CHANNEL_CLEAR (0) +#endif + +#ifndef DMAC_CFG_PRIORITY_MODE + #define DMAC_CFG_PRIORITY_MODE (0) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Internal driver storage for p_callback, used by ISRs. */ +typedef struct st_dmac_callback +{ + /** Callback for transfer end interrupt. Set to NULL for no CPU interrupt. */ + void (* p_callback)(dmac_callback_args_t * cb_data); + + /** Placeholder for user data. Passed to the user p_callback in ::transfer_callback_args_t. */ + void * p_context; +} dmac_callback_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void dmac_int_isr(void); + +static fsp_err_t r_dmac_prv_enable(dmac_instance_ctrl_t * p_ctrl); +static void r_dmac_prv_disable(dmac_instance_ctrl_t * p_ctrl); +static void r_dmac_config_transfer_info(dmac_instance_ctrl_t * p_ctrl, transfer_info_t * p_info); + +#if DMAC_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_dma_open_parameter_checking(dmac_instance_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); +static fsp_err_t r_dmac_reconfigure_parameter_checking(transfer_info_t const * const p_info); +static fsp_err_t r_dmac_enable_parameter_checking(dmac_instance_ctrl_t * const p_ctrl); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** DMAC implementation of transfer API. */ +const transfer_api_t g_transfer_on_dmac = +{ + .open = R_DMAC_Open, + .reconfigure = R_DMAC_Reconfigure, + .reset = R_DMAC_Reset, + .infoGet = R_DMAC_InfoGet, + .softwareStart = R_DMAC_SoftwareStart, + .softwareStop = R_DMAC_SoftwareStop, + .enable = R_DMAC_Enable, + .disable = R_DMAC_Disable, + .reload = R_DMAC_Reload, + .callbackSet = R_DMAC_CallbackSet, + .close = R_DMAC_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup DMAC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure a DMAC channel. + * + * @retval FSP_SUCCESS Successful open. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The configured channel is invalid. + * @retval FSP_ERR_IRQ_BSP_DISABLED The IRQ associated with the activation source is not enabled in the BSP. + * @retval FSP_ERR_ALREADY_OPEN The control structure is already opened. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_Open (transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg) +{ +#if DMAC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = FSP_SUCCESS; + err = r_dma_open_parameter_checking(p_api_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; + dmac_extended_cfg_t * p_extend = (dmac_extended_cfg_t *) p_cfg->p_extend; + + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_reg = DMAC_PRV_REG(p_extend->channel); + + /* Set callback and context pointers, if configured */ + p_ctrl->p_callback = p_extend->p_callback; + p_ctrl->p_context = p_extend->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Enable DMAC Operation. */ + R_BSP_MODULE_START(FSP_IP_DMAC, p_extend->channel); + + R_DMA->DMAST = 1; + +#if BSP_FEATURE_DMAC_HAS_DMCTL + R_DMA->DMCTL = (DMAC_CFG_PRIORITY_MODE << R_DMA_DMCTL_PR_Pos) | + (DMAC_CFG_ERROR_CHANNEL_CLEAR << R_DMA_DMCTL_ERCH_Pos); +#endif + + /* Configure the transfer settings. */ + r_dmac_config_transfer_info(p_ctrl, p_cfg->p_info); + + /* Mark driver as open by initializing "DMAC" in its ASCII equivalent.*/ + p_ctrl->open = DMAC_ID; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reconfigure the transfer with new transfer info. + * + * @retval FSP_SUCCESS Transfer is configured and will start when trigger occurs. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_ENABLED DMAC is not enabled. The current configuration must not be valid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DMAC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_Reconfigure (transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info) +{ + fsp_err_t err; + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; + +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); + err = r_dmac_reconfigure_parameter_checking(p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Reconfigure the transfer settings. */ + r_dmac_config_transfer_info(p_ctrl, p_info); + + /* Enable the transfer configuration. */ + err = r_dmac_prv_enable(p_api_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_NOT_ENABLED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reset transfer source, destination, and number of transfers. + * + * @retval FSP_SUCCESS Transfer reset successfully. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_ENABLED DMAC is not enabled. The current configuration must not be valid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DMAC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_Reset (transfer_ctrl_t * const p_api_ctrl, + void const * volatile p_src, + void * volatile p_dest, + uint16_t const num_transfers) +{ + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); +#endif + + /* Disable transfers if they are currently enabled. */ + r_dmac_prv_disable(p_ctrl); + + if (NULL != p_src) + { + /* Configure the DMAC source pointer if it is provided. */ + p_ctrl->p_reg->DMSAR = (uint32_t) p_src; + } + + if (NULL != p_dest) + { + /* Configure the DMAC destination pointer if it is provided. */ + p_ctrl->p_reg->DMDAR = (uint32_t) p_dest; + } + + if ((TRANSFER_MODE_NORMAL != (transfer_mode_t) p_ctrl->p_reg->DMTMD_b.MD)) + { + /* Reset the block/repeat count if it is not normal mode. */ + p_ctrl->p_reg->DMCRB = num_transfers; + } + else + { + /* Reset the transfer count if it is normal mode. */ + p_ctrl->p_reg->DMCRA = num_transfers; + } + + /* Enable the transfer configuration. */ + err = r_dmac_prv_enable(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_NOT_ENABLED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * If the mode is TRANSFER_START_MODE_SINGLE initiate a single transfer with software. If the mode is + * TRANSFER_START_MODE_REPEAT continue triggering transfers until all of the transfers are completed. + * + * @retval FSP_SUCCESS Transfer started written successfully. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DMAC_Open to initialize the control block. + * @retval FSP_ERR_UNSUPPORTED Handle was not configured for software activation. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_SoftwareStart (transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode) +{ + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); + + dmac_extended_cfg_t * p_extend = (dmac_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + FSP_ERROR_RETURN(ELC_EVENT_NONE == p_extend->activation_source, FSP_ERR_UNSUPPORTED); +#endif + + /* Set auto clear bit and software start bit. */ + p_ctrl->p_reg->DMREQ = (uint8_t) (((uint32_t) mode << DMAC_PRV_DMREQ_CLRS_OFFSET) | DMAC_PRV_DMREQ_SWREQ_MASK); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stop software transfers if they were started with TRANSFER_START_MODE_REPEAT. + * + * @retval FSP_SUCCESS Transfer stopped written successfully. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DMAC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_SoftwareStop (transfer_ctrl_t * const p_api_ctrl) +{ + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); +#endif + + /* Reset auto clear bit and clear software start bit. */ + p_ctrl->p_reg->DMREQ = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable transfers for the configured activation source. + * + * @retval FSP_SUCCESS Counter value written successfully. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DMAC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_Enable (transfer_ctrl_t * const p_api_ctrl) +{ + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); +#endif + + return r_dmac_prv_enable(p_ctrl); +} + +/*******************************************************************************************************************//** + * Disable transfers so that they are no longer triggered by the activation source. + * + * @retval FSP_SUCCESS Counter value written successfully. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DMAC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_Disable (transfer_ctrl_t * const p_api_ctrl) +{ + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); +#endif + + r_dmac_prv_disable(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set driver specific information in provided pointer. + * + * @retval FSP_SUCCESS Information has been written to p_info. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DMAC_Open to initialize the control block. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_InfoGet (transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_info) +{ + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_info); +#endif + + p_info->transfer_length_max = DMAC_MAX_BLOCK_TRANSFER_LENGTH; + p_info->block_count_max = DMAC_MAX_BLOCK_COUNT; + + transfer_mode_t mode = (transfer_mode_t) p_ctrl->p_reg->DMTMD_b.MD; + + p_info->block_count_remaining = p_ctrl->p_reg->DMCRB; + p_info->transfer_length_remaining = p_ctrl->p_reg->DMCRA_b.DMCRAL; + + if (TRANSFER_MODE_NORMAL == mode) + { + p_info->transfer_length_max = DMAC_MAX_NORMAL_TRANSFER_LENGTH; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * To update next transfer information without interruption during transfer. + * + * @retval FSP_ERR_UNSUPPORTED This feature is not supported. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_Reload (transfer_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const num_transfers) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(num_transfers); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_CallbackSet (transfer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(dmac_callback_args_t *), + void * const p_context, + dmac_callback_args_t * const p_callback_memory) +{ + FSP_PARAMETER_NOT_USED(p_callback_memory); + + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; + +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable transfer and clean up internal data. Implements @ref transfer_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DMAC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DMAC_Close (transfer_ctrl_t * const p_api_ctrl) +{ + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) p_api_ctrl; +#if DMAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DMAC_ID, FSP_ERR_NOT_OPEN); +#endif + + dmac_extended_cfg_t * p_extend = (dmac_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Disable DMAC transfers on this channel. */ +#if !BSP_FEATURE_DMAC_HAS_DELSR + R_ICU->DELSR[p_extend->channel] = ELC_EVENT_NONE; +#else + R_DMA->DELSR[p_extend->channel] = ELC_EVENT_NONE; +#endif + p_ctrl->p_reg->DMCNT = 0; + + if (NULL != p_extend->p_callback) + { + R_BSP_IrqDisable(p_extend->irq); + R_FSP_IsrContextSet(p_extend->irq, NULL); + } + + /* Clear ID so control block can be reused. */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup DMAC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enable transfers for the channel. + * + * @param[in] p_ctrl Pointer to control structure. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_dmac_prv_enable (dmac_instance_ctrl_t * p_ctrl) +{ +#if DMAC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_dmac_enable_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /** Enable transfer. */ + p_ctrl->p_reg->DMCNT = 1; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable transfers for the channel. + * + * @param p_ctrl Pointer to the control structure + **********************************************************************************************************************/ +static void r_dmac_prv_disable (dmac_instance_ctrl_t * p_ctrl) +{ + dmac_extended_cfg_t * p_extend = (dmac_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Disable the transfers. See table "Register setting procedure" in the DMAC section of the relevant + * hardware manual. */ +#if !BSP_FEATURE_DMAC_HAS_DELSR + R_ICU->DELSR[p_extend->channel] = ELC_EVENT_NONE; +#else + R_DMA->DELSR[p_extend->channel] = ELC_EVENT_NONE; +#endif + + p_ctrl->p_reg->DMCNT = 0; + + /* Configure the activation source. */ +#if !BSP_FEATURE_DMAC_HAS_DELSR + R_ICU->DELSR[p_extend->channel] = p_extend->activation_source; +#else + R_DMA->DELSR[p_extend->channel] = p_extend->activation_source; +#endif + + /* Disable software start. */ + p_ctrl->p_reg->DMREQ = 0; +} + +/*******************************************************************************************************************//** + * Write the transfer info to the hardware registers. + * + * @param[in] p_ctrl Pointer to control structure. + * @param p_info Pointer to transfer info. + **********************************************************************************************************************/ +static void r_dmac_config_transfer_info (dmac_instance_ctrl_t * p_ctrl, transfer_info_t * p_info) +{ + dmac_extended_cfg_t * p_extend = (dmac_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + uint32_t dmcra = 0; + uint32_t dmcrb = 0; + uint32_t dmtmd = 0; + uint32_t dmint = 0; + uint32_t dmamd = 0; + + /* Disable transfers if they are currently enabled. */ + r_dmac_prv_disable(p_ctrl); + + /* Configure the Transfer Data Size (1,2,4) bytes. */ + dmtmd |= (uint32_t) (p_info->transfer_settings_word_b.size << DMAC_PRV_DMTMD_SZ_OFFSET); + + /* Configure source and destination address mode. */ + dmamd |= (uint32_t) (p_info->transfer_settings_word_b.src_addr_mode << DMAC_PRV_DMAMD_SM_OFFSET); + dmamd |= (uint32_t) (p_info->transfer_settings_word_b.dest_addr_mode << DMAC_PRV_DMAMD_DM_OFFSET); + + /* Configure the transfer mode. */ + dmtmd |= (uint32_t) p_info->transfer_settings_word_b.mode << DMAC_PRV_DMTMD_MD_OFFSET; + + /* Configure the transfer count. */ + dmcra = p_info->length; + + if ((TRANSFER_MODE_BLOCK == p_info->transfer_settings_word_b.mode) || + (TRANSFER_MODE_REPEAT == p_info->transfer_settings_word_b.mode) || + (TRANSFER_MODE_REPEAT_BLOCK == p_info->transfer_settings_word_b.mode)) + { + /* Configure the reload count. */ + dmcra |= dmcra << DMAC_PRV_DMCRA_HIGH_OFFSET; + dmcra &= (DMAC_PRV_DMCRA_HIGH_MASK | DMAC_PRV_DMCRA_LOW_MASK); + + /* Configure the block count. */ + dmcrb = p_info->num_blocks; + + if ((TRANSFER_MODE_BLOCK == p_info->transfer_settings_word_b.mode) || + (TRANSFER_MODE_REPEAT == p_info->transfer_settings_word_b.mode)) + { + /* Configure the repeat area */ + dmtmd |= (uint32_t) (p_info->transfer_settings_word_b.repeat_area << DMAC_PRV_DMTMD_DTS_OFFSET); + } + } + else /* TRANSFER_MODE_NORMAL */ + { + /* Configure no repeat area. */ + dmtmd |= 2U << DMAC_PRV_DMTMD_DTS_OFFSET; + } + + if (ELC_EVENT_NONE != p_extend->activation_source) + { + /* DMAC will be triggered by interrupts (ELC Events). */ + dmtmd |= 1U << DMAC_PRV_DMTMD_DCTG_OFFSET; + } + + if (NULL != p_ctrl->p_callback) + { + /* Enable transfer end interrupt requests. */ + dmint |= DMAC_PRV_DMINT_DTIE_MASK; + + /* Enable the transfer end escape interrupt requests. + * Repeat size end and Extended Repeat area overflow requests are not + * used with Repeat-Block mode. Reference section 16.2.9 "DMINT : DMA Interrupt Setting Register" + * description in the DMAC section of the relevant hardware manual. */ + if ((TRANSFER_IRQ_EACH == p_info->transfer_settings_word_b.irq) && + (TRANSFER_MODE_REPEAT_BLOCK != p_info->transfer_settings_word_b.mode)) + { + /* Enable the transfer end escape interrupt requests + * (Repeat size end and Extended Repeat area overflow requests). */ + dmint |= (DMAC_PRV_DMINT_RPTIE_MASK | DMAC_PRV_DMINT_ESIE_MASK); + } + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqCfgEnable(p_extend->irq, p_extend->ipl, p_ctrl); + } + +#if BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE + uint32_t dmsbs = 0; + uint32_t dmdbs = 0; + + if (TRANSFER_MODE_REPEAT_BLOCK == p_info->transfer_settings_word_b.mode) + { + uint16_t num_of_blocks = p_info->num_blocks; + uint16_t size_of_block; + size_of_block = p_info->length; + uint16_t src_buffer_size; + uint16_t dest_buffer_size; + if (TRANSFER_ADDR_MODE_OFFSET == p_info->transfer_settings_word_b.src_addr_mode) + { + src_buffer_size = num_of_blocks; + dmamd |= R_DMAC0_DMAMD_SADR_Msk; + } + else + { + src_buffer_size = p_extend->src_buffer_size; + } + + if (TRANSFER_ADDR_MODE_OFFSET == p_info->transfer_settings_word_b.dest_addr_mode) + { + dest_buffer_size = num_of_blocks; + dmamd |= R_DMAC0_DMAMD_DADR_Msk; + } + else + { + dest_buffer_size = (uint16_t) (num_of_blocks * size_of_block); + } + + dmsbs = src_buffer_size; + dmsbs |= dmsbs << R_DMAC0_DMSBS_DMSBSH_Pos; + + dmdbs = dest_buffer_size; + dmdbs |= dmdbs << R_DMAC0_DMDBS_DMDBSH_Pos; + + p_ctrl->p_reg->DMSRR = (uint32_t) p_info->p_src; + p_ctrl->p_reg->DMDRR = (uint32_t) p_info->p_dest; + } + + p_ctrl->p_reg->DMSBS = dmsbs; + p_ctrl->p_reg->DMDBS = dmdbs; +#endif + + /* Write register settings. */ + p_ctrl->p_reg->DMAMD = (uint16_t) dmamd; + p_ctrl->p_reg->DMTMD = (uint16_t) dmtmd; + p_ctrl->p_reg->DMSAR = (uint32_t) p_info->p_src; + p_ctrl->p_reg->DMDAR = (uint32_t) p_info->p_dest; + p_ctrl->p_reg->DMCRA = dmcra; + p_ctrl->p_reg->DMCRB = (uint16_t) dmcrb; + p_ctrl->p_reg->DMOFR = (uint32_t) p_extend->offset; + p_ctrl->p_reg->DMINT = (uint8_t) dmint; +} + +#if DMAC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking of R_DMAC_Open. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be + * set by user. + * + * @retval FSP_SUCCESS Input Parameters are Valid. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The configured channel is invalid. + * @retval FSP_ERR_IRQ_BSP_DISABLED Callback is NULL and the DMAC IRQ is not enabled. + * @retval FSP_ERR_ALREADY_OPEN The control structure is already opened. + **********************************************************************************************************************/ +static fsp_err_t r_dma_open_parameter_checking (dmac_instance_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open != DMAC_ID, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + dmac_extended_cfg_t * p_extend = (dmac_extended_cfg_t *) p_cfg->p_extend; + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(p_extend->channel < BSP_FEATURE_DMAC_NUM_CHANNELS, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + if (NULL != p_extend->p_callback) + { + FSP_ERROR_RETURN(p_extend->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + fsp_err_t err = r_dmac_reconfigure_parameter_checking(p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Checks for errors in the transfer into structure. + * + * @param[in] p_info Pointer transfer info. + * + * @retval FSP_SUCCESS The transfer info is valid. + * @retval FSP_ERR_ASSERTION A transfer info setting is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_dmac_reconfigure_parameter_checking (transfer_info_t const * const p_info) +{ + FSP_ASSERT(p_info != NULL); + + if (TRANSFER_MODE_NORMAL != p_info->transfer_settings_word_b.mode) + { + FSP_ASSERT(p_info->length <= DMAC_REPEAT_BLOCK_MAX_LENGTH); + } + + FSP_ASSERT((TRANSFER_MODE_REPEAT_BLOCK != p_info->transfer_settings_word_b.mode) || + (TRANSFER_IRQ_EACH != p_info->transfer_settings_word_b.irq)); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Parameter checking for r_dmac_prv_enable. + * + * @param[in] p_ctrl Pointer to control structure. + * + * @retval FSP_SUCCESS Alignment on source and destination pointers is valid. + * @retval FSP_ERR_ASSERTION The current configuration is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_dmac_enable_parameter_checking (dmac_instance_ctrl_t * const p_ctrl) +{ + void const * p_src = (void const *) p_ctrl->p_reg->DMSAR; + void const * p_dest = (void const *) p_ctrl->p_reg->DMDAR; + transfer_size_t size = (transfer_size_t) p_ctrl->p_reg->DMTMD_b.SZ; + transfer_mode_t mode = (transfer_mode_t) p_ctrl->p_reg->DMTMD_b.MD; + + /* The source and destination pointers cannot be NULL. */ + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); + + /* The source and destination pointers must be aligned to the transfer size. */ + FSP_ASSERT(0U == ((uint32_t) p_dest & DMAC_PRV_MASK_ALIGN_N_BYTES(size))); + FSP_ASSERT(0U == ((uint32_t) p_src & DMAC_PRV_MASK_ALIGN_N_BYTES(size))); + + if (TRANSFER_MODE_NORMAL == mode) + { + /* Setting transfer count to 0 in normal mode means transfer forever. This feature is not supported. */ + FSP_ASSERT(0 != p_ctrl->p_reg->DMCRA); + } + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * DMAC ISR + **********************************************************************************************************************/ +void dmac_int_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + dmac_instance_ctrl_t * p_ctrl = (dmac_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Call the callback routine if one is available */ + dmac_callback_args_t args; + args.p_context = p_ctrl->p_context; + + /* Call user callback */ + p_ctrl->p_callback(&args); + + /* Transfers are disabled during the interrupt if an interrupt is requested after each block or after each repeat + * length. If not all transfers are complete, reenable transfer here. See "Transfer End by Repeat + * Size End Interrupt" in the DMAC section of the relevant hardware manual. */ + if (p_ctrl->p_reg->DMCRB > 0U) + { + p_ctrl->p_reg->DMCNT = 1; + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_doc/r_doc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_doc/r_doc.c new file mode 100644 index 0000000000..56503024a0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_doc/r_doc.c @@ -0,0 +1,370 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_doc_api.h" +#include "bsp_api.h" +#include "bsp_cfg.h" +#include "r_doc.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "DOCO" in ASCII, used to identify Data Operation Circuit (DOC) configuration */ +#define DOC_OPEN (0x444F434fU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * doc_prv_ns_callback)(doc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile doc_prv_ns_callback)(doc_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void doc_int_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* DOC implementation of DOC Driver */ + +const doc_api_t g_doc_on_doc = +{ + .open = R_DOC_Open, + .close = R_DOC_Close, + .read = R_DOC_Read, + .write = R_DOC_Write, + .callbackSet = R_DOC_CallbackSet, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup DOC + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens and configures the Data Operation Circuit (DOC) in comparison, addition or subtraction mode and sets + * initial data for addition or subtraction, or reference data for comparison. + * + * Example: + * @snippet r_doc_example.c R_DOC_Open + * + * @retval FSP_SUCCESS DOC successfully configured. + * @retval FSP_ERR_ALREADY_OPEN Module already open. + * @retval FSP_ERR_ASSERTION One or more pointers point to NULL or callback is NULL or the interrupt vector + * is invalid. + * + ***********************************************************************************************************************/ +fsp_err_t R_DOC_Open (doc_ctrl_t * const p_api_ctrl, doc_cfg_t const * const p_cfg) +{ + doc_instance_ctrl_t * p_ctrl = (doc_instance_ctrl_t *) p_api_ctrl; + + /* Validate the parameters and check if the module is initialized */ +#if DOC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + #if !BSP_TZ_SECURE_BUILD + FSP_ASSERT(p_cfg->p_callback != NULL); + #endif + FSP_ASSERT(p_cfg->irq >= (IRQn_Type) 0); + FSP_ERROR_RETURN(DOC_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* save pointers for later use */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Power on the DOC module. */ + R_BSP_MODULE_START(FSP_IP_DOC, 0); + +#if BSP_FEATURE_DOC_VERSION == 1 + + /* Clear the hardware status flag and Configure the DOC using DOCR register. */ + R_DOC->DOCR = (uint8_t) (R_DOC_DOCR_DOPCFCL_Msk | p_cfg->event); + + /* write initial data for comparison/ addition/subtraction to DODSR register */ + R_DOC->DODSR = (uint16_t) (p_ctrl->p_cfg->doc_data & UINT16_MAX); +#else + + /* Configure the DOC using DOCR register. */ + uint32_t docr = R_DOC_B_DOCR_OMS_Msk & p_cfg->event; + docr |= (uint32_t) (p_cfg->event << (R_DOC_B_DOCR_DCSEL_Pos - 2U)) & R_DOC_B_DOCR_DCSEL_Msk; + docr |= (uint32_t) (p_cfg->bit_width << R_DOC_B_DOCR_DOBW_Pos) & R_DOC_B_DOCR_DOBW_Msk; + R_DOC_B->DOCR = (uint8_t) docr & UINT8_MAX; + + /* Clear the hardware status flag. */ + R_DOC_B->DOSCR = 1; + + /* write initial data for comparison/ addition/subtraction to DODSR0/DODSR1 registers. */ + R_DOC_B->DODSR0 = p_ctrl->p_cfg->doc_data; + R_DOC_B->DODSR1 = p_ctrl->p_cfg->doc_data_extra; +#endif + + /* Set valid interrupt contexts and user provided priority. Enable the interrupt at the NVIC */ + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->irq, p_cfg->ipl, p_ctrl); + + /* Mark driver as open by initializing it to "DOCO" in its ASCII equivalent. */ + p_ctrl->open = DOC_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes the module driver. Enables module stop mode. + * + * @retval FSP_SUCCESS Module successfully closed. + * @retval FSP_ERR_NOT_OPEN Driver not open. + * @retval FSP_ERR_ASSERTION Pointer pointing to NULL. + * + * @note This function will disable the DOC interrupt in the NVIC. + **********************************************************************************************************************/ +fsp_err_t R_DOC_Close (doc_ctrl_t * const p_api_ctrl) +{ + doc_instance_ctrl_t * p_ctrl = (doc_instance_ctrl_t *) p_api_ctrl; + + /* Validate the parameter and check if the module is initialized */ +#if DOC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(DOC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disable the IRQ in the NVIC in case it has been left enabled. */ + if (p_ctrl->p_cfg->irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + R_FSP_IsrContextSet(p_ctrl->p_cfg->irq, NULL); + } + + R_BSP_MODULE_STOP(FSP_IP_DOC, 0); + + /* Mark driver as closed. */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Returns the result of addition/subtraction. + * + * Example: + * @snippet r_doc_example.c R_DOC_Read + * + * @retval FSP_SUCCESS Status successfully read. + * @retval FSP_ERR_NOT_OPEN Driver not open. + * @retval FSP_ERR_ASSERTION One or more pointers point to NULL. + * + **********************************************************************************************************************/ +fsp_err_t R_DOC_Read (doc_ctrl_t * const p_api_ctrl, uint32_t * p_result) +{ + doc_instance_ctrl_t * p_ctrl = (doc_instance_ctrl_t *) p_api_ctrl; + + FSP_PARAMETER_NOT_USED(p_ctrl); + + /* Validate the parameters and check if the module is intialized */ +#if DOC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_result); + FSP_ERROR_RETURN(DOC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Read the result of addition or subtraction operation from the register and store in the user supplied location */ +#if BSP_FEATURE_DOC_VERSION == 1 + *p_result = R_DOC->DODSR; +#else + *p_result = R_DOC_B->DODSR0; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes to the DODIR - DOC Input Register. + * + * Example: + * @snippet r_doc_example.c R_DOC_Write + * + * @retval FSP_SUCCESS Values successfully written to the registers. + * @retval FSP_ERR_NOT_OPEN Driver not open. + * @retval FSP_ERR_ASSERTION One or more pointers point to NULL. + * + **********************************************************************************************************************/ +fsp_err_t R_DOC_Write (doc_ctrl_t * const p_api_ctrl, uint32_t data) +{ + doc_instance_ctrl_t * p_ctrl = (doc_instance_ctrl_t *) p_api_ctrl; + + FSP_PARAMETER_NOT_USED(p_ctrl); + + /* Validate the parameters and check if the module is initialized */ +#if DOC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(DOC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Writes the user supplied data to the DODIR register for data operation in Comparison, Addition and subtraction modes */ +#if BSP_FEATURE_DOC_VERSION == 1 + R_DOC->DODIR = (uint16_t) (data & UINT16_MAX); +#else + R_DOC_B->DODIR = data; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements doc_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_DOC_CallbackSet (doc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(doc_callback_args_t *), + void * const p_context, + doc_callback_args_t * const p_callback_memory) +{ + doc_instance_ctrl_t * p_ctrl = (doc_instance_ctrl_t *) p_api_ctrl; + +#if (DOC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(DOC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if DOC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + doc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(doc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup DOC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * DOC ISR. + * + * Saves context if RTOS is used, clears interrupts, calls callback if one was provided in the open function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void doc_int_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + doc_instance_ctrl_t * p_ctrl = (doc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Call callback */ + doc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + doc_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + if (NULL != p_ctrl->p_callback) + { + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + doc_prv_ns_callback p_callback = (doc_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } + + /* clear DOPCF flag */ +#if BSP_FEATURE_DOC_VERSION == 1 + R_DOC->DOCR = (uint8_t) (R_DOC_DOCR_DOPCFCL_Msk | (p_ctrl->p_cfg->event)); +#else + R_DOC_B->DOSCR = 1; +#endif + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_base.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_base.c new file mode 100644 index 0000000000..e60b1e3893 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_base.c @@ -0,0 +1,233 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_drw_base.c + * Description : This file defines the D/AVE D1 low-level driver basic functions. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include + +#include "bsp_api.h" + +#include "r_drw_base.h" +#include "r_drw_cfg.h" + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define DRW_PRV_D2_DLISTSTART 50 /* display list start register index */ + +/*********************************************************************************************************************** + * Extern global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* D1 device handle to be passed up to D2 layer */ +static d1_device_flex device_d2d = {0}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @internal + * @addtogroup DRW_PRV Internal DRW Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This function initializes the D1 device handle, supplies module clock to D/AVE 2D hardware and enables the D/AVE 2D + * interrupt. It is called by the D/AVE 2D driver function d2_inithw() to initialize the D/AVE 2D hardware. + * + * @param[in] flags Reserved. Not used in this function. + * @retval Non-NULL The function returns the pointer to a d1_device object if the D1 device handle was successfully + * initialized. + * @retval NULL The function returns NULL if the interrupt could not be successfully initialized. + **********************************************************************************************************************/ +d1_device * d1_opendevice (d1_long_t flags) +{ + d1_device_flex * handle; + + FSP_PARAMETER_NOT_USED(flags); + + /* Get new device handle. */ + handle = &device_d2d; + + /* Initialize device data. */ + handle->dlist_indirect_enable = DRW_CFG_USE_DLIST_INDIRECT; + + /* Supply clock to the D/AVE 2D hardware. */ + R_BSP_MODULE_START(FSP_IP_DRW, 0); + + /* Enable the D/AVE 2D interrupt. */ + if (d1_initirq_intern(handle) == 0) + { + /* If the IRQ number is invalid return NULL. */ + handle = NULL; + + /* Stop clock supply to the D/AVE 2D hardware. */ + R_BSP_MODULE_STOP(FSP_IP_DRW, 0); + } + + /* Returns the pointer to the d1_device object. */ + return (d1_device *) handle; +} + +/*******************************************************************************************************************//** + * This function is called by the D/AVE 2D driver function d2_deinithw to de-initialize the D/AVE 2D hardware. Disables + * the D/AVE 2D interrupt and stop the module clock supply. + * + * @param[in] handle Pointer to the d1_device object. + * @retval 1 The function returns 1. + **********************************************************************************************************************/ +d1_int_t d1_closedevice (d1_device * handle) +{ + d1_device_flex * dev = (d1_device_flex *) handle; + + /* Disable the D/AVE 2D interrupt. */ + d1_shutdownirq_intern(dev); + + /* Stop clock supply to the D/AVE 2D hardware. */ + R_BSP_MODULE_STOP(FSP_IP_DRW, 0); + + return 1; +} + +/*******************************************************************************************************************//** + * This function is used to write data to a D/AVE 2D hardware register. + * + * @param[in] handle Pointer to a device handle. + * @param[in] deviceid D1_DAVE2D (Rendering core) or D1_DLISTINDIRECT (Lists of dlist support). Others are ignored. + * @param[in] index Register index (word offset from the D/AVE 2D base address). + * @param[in] value 32-bit value to write. + **********************************************************************************************************************/ +void d1_setregister (d1_device * handle, d1_int_t deviceid, d1_int_t index, d1_long_t value) +{ + d1_device_flex * handle_flex = (d1_device_flex *) handle; + + switch (deviceid) + { + case D1_DAVE2D: + { +#if DRW_CFG_USE_DLIST_INDIRECT + + /* If indirect mode is configured start processing the display list list in indirect mode */ + if ((DRW_PRV_D2_DLISTSTART == index) && (handle_flex->dlist_indirect_enable)) + { + /* Set DLISTSTART to the address of the first display list and set pp_dlist_indirect_start to the next dlist ptr */ + uint32_t * p_dlist = (uint32_t *) value; + R_DRW->DLISTSTART = *p_dlist; + handle_flex->pp_dlist_indirect_start = p_dlist + 1U; + } + else +#endif + { + /* Write data to specified D/AVE 2D register. */ + ((uint32_t *) R_DRW)[index] = (uint32_t) value; + } + + break; + } + + case D1_DLISTINDIRECT: + { +#if DRW_CFG_USE_DLIST_INDIRECT + handle_flex->dlist_indirect_enable = value; +#else + handle_flex->dlist_indirect_enable = 0; +#endif + break; + } + + default: + { + /* Not supported or Unknown device, do nothing. */ + break; + } + } +} + +/*******************************************************************************************************************//** + * This function is used to read data from a hardware register. + * Reading a register from an invalid or unsupported device ID will always return 0. + * + * @param[in] handle Pointer to a device handle. + * @param[in] deviceid D1_DAVE2D (Rendering core) or D1_DLISTINDIRECT (Lists of dlist support). Others are ignored. + * @param[in] index Register index (starts with 0). + * @retval Value The function returns the 32-bit value of the register. + **********************************************************************************************************************/ +d1_long_t d1_getregister (d1_device * handle, d1_int_t deviceid, d1_int_t index) +{ +#if DRW_CFG_USE_DLIST_INDIRECT + d1_device_flex * handle_flex = (d1_device_flex *) handle; +#else + FSP_PARAMETER_NOT_USED(handle); +#endif + + int32_t ret = 0; + + if (D1_DAVE2D == deviceid) + { + ret = (int32_t) (((uint32_t *) R_DRW)[index]); + } + +#if DRW_CFG_USE_DLIST_INDIRECT + else if (D1_DLISTINDIRECT == deviceid) + { + ret = handle_flex->dlist_indirect_enable; + } + else + { + } +#endif + + return (d1_long_t) ret; +} + +/*******************************************************************************************************************//** + * Check if the specified device ID is valid for the D/AVE 2D implementation for Flex. + * Use this function to verify that a specific hardware interface is available on the current host system. + * + * @param[in] handle Pointer to a device handle. + * @param[in] deviceid D1_DAVE2D (Rendering core) or D1_DLISTINDIRECT (Lists of dlist support). Others are ignored. + * @retval 0 The function returns 0 if specified device ID not supported. + * @retval 1 The function returns 1 if specified device ID supported. + **********************************************************************************************************************/ +d1_int_t d1_devicesupported (d1_device * handle, d1_int_t deviceid) +{ + d1_int_t ret = 0; + + FSP_PARAMETER_NOT_USED(handle); + + if (deviceid == D1_DAVE2D) + { + ret = 1; + } + +#if DRW_CFG_USE_DLIST_INDIRECT + else if (D1_DLISTINDIRECT == deviceid) + { + ret = 1; + } + else + { + } +#endif + + return ret; +} + +/*******************************************************************************************************************//** + * @} + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_base.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_base.h new file mode 100644 index 0000000000..2fb2244033 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_base.h @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_drw_base.h + * Description : D/AVE D1 low-level driver function header file. + **********************************************************************************************************************/ + +#ifndef DRW_BASE_H +#define DRW_BASE_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "dave_base.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef long d1_long_t; +typedef int d1_int_t; +typedef unsigned int d1_uint_t; + +/** Device handle type definition for FSP implementation. */ +typedef struct _d1_device_flex +{ + volatile uint32_t * pp_dlist_indirect_start; /* Display list start address */ + int32_t dlist_indirect_enable; /* Set to 1 when supporting lists of dlist addresses */ +} d1_device_flex; + +d1_int_t d1_initirq_intern(d1_device_flex * handle); +d1_int_t d1_shutdownirq_intern(d1_device_flex * handle); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_irq.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_irq.c new file mode 100644 index 0000000000..15a8420308 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_irq.c @@ -0,0 +1,270 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_drw_irq.c + * Description : This file defines the D/AVE D1 low-level driver IRQ setting functions. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_drw_base.h" +#include "r_drw_cfg.h" + +#if (BSP_CFG_RTOS == 2) // FreeRTOS + #include "FreeRTOS.h" + #include "semphr.h" +#elif (BSP_CFG_RTOS == 1) // ThreadX + #include "tx_api.h" +#endif + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define DRW_PRV_IRQCTL_DLISTIRQ_ENABLE (1U << 1) +#define DRW_PRV_IRQCTL_ENUMIRQ_CLEAR (1U << 2) +#define DRW_PRV_IRQCTL_DLISTIRQ_CLEAR (1U << 3) +#define DRW_PRV_IRQCTL_BUSIRQ_CLEAR (1U << 5) +#define DRW_PRV_IRQCTL_ALLIRQ_DISABLE_AND_CLEAR (DRW_PRV_IRQCTL_BUSIRQ_CLEAR | DRW_PRV_IRQCTL_DLISTIRQ_CLEAR | \ + DRW_PRV_IRQCTL_ENUMIRQ_CLEAR) +#define DRW_PRV_IRQCTL_ALLIRQ_CLEAR_AND_DLISTIRQ_ENABLE \ + (DRW_PRV_IRQCTL_BUSIRQ_CLEAR | DRW_PRV_IRQCTL_DLISTIRQ_CLEAR | DRW_PRV_IRQCTL_ENUMIRQ_CLEAR | \ + DRW_PRV_IRQCTL_DLISTIRQ_ENABLE) +#define DRW_PRV_STATUS_DLISTIRQ_TRIGGERED (1U << 5) + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +#if (BSP_CFG_RTOS == 0) // No RTOS +static volatile d1_int_t g_dlist_done = 0; +#elif (BSP_CFG_RTOS == 1) // ThreadX +static TX_SEMAPHORE g_d1_queryirq_sem; +#elif (BSP_CFG_RTOS == 2) // FreeRTOS +static SemaphoreHandle_t g_d1_queryirq_sem; +static StaticSemaphore_t g_d1_queryirq_sem_data; +#endif + +/*********************************************************************************************************************** + * Extern variables + **********************************************************************************************************************/ +extern const uint8_t DRW_INT_IPL; + +/*******************************************************************************************************************//** + * @internal + * @addtogroup DRW_PRV Internal DRW Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void drw_int_isr(void); + +/*******************************************************************************************************************//** + * Initializes DRW_INT. + * + * @param[in] handle Pointer to the d1_device object. + * @retval 0 The function returns 0 if the IRQ number is invalid. + * @retval 1 The function returns 1 if DRW_INT is successfully initialized. + **********************************************************************************************************************/ +d1_int_t d1_initirq_intern (d1_device_flex * handle) +{ + d1_int_t ret = 0; + + if (DRW_CFG_INT_IRQ >= 0) + { + /* Clear all the D/AVE 2D IRQs and enable Display list IRQ. */ + R_DRW->IRQCTL = DRW_PRV_IRQCTL_ALLIRQ_CLEAR_AND_DLISTIRQ_ENABLE; + + /* Enable D/AVE 2D interrupt in NVIC. */ + R_BSP_IrqCfgEnable((IRQn_Type) DRW_CFG_INT_IRQ, DRW_INT_IPL, handle); + +#if (BSP_CFG_RTOS == 2) // FreeRTOS + + /* Initialize semaphore for use in d1_queryirq() */ + g_d1_queryirq_sem = xSemaphoreCreateBinaryStatic(&g_d1_queryirq_sem_data); + + ret = 1; +#elif (BSP_CFG_RTOS == 1) // ThreadX + + /* Initialize semaphore for use in d1_queryirq() */ + if (TX_SUCCESS == tx_semaphore_create(&g_d1_queryirq_sem, (CHAR *) "g_d1_isr_semaphore", 0)) + { + ret = 1; + } +#else + ret = 1; +#endif + } + + return ret; +} + +/*******************************************************************************************************************//** + * De-initializes DRW_INT. + * + * @param[in] handle Pointer to the d1_device object. + * @retval 1 The function returns 1. + **********************************************************************************************************************/ +d1_int_t d1_shutdownirq_intern (d1_device_flex * handle) +{ + FSP_PARAMETER_NOT_USED(handle); + + /* Disable D/AVE 2D interrupt in NVIC. */ + NVIC_DisableIRQ((IRQn_Type) DRW_CFG_INT_IRQ); + + /* Clear all the D/AVE 2D IRQs and disable Display list IRQ. */ + R_DRW->IRQCTL = DRW_PRV_IRQCTL_ALLIRQ_DISABLE_AND_CLEAR; + +#if (BSP_CFG_RTOS == 2) // FreeRTOS + + /* Delete semaphore */ + vSemaphoreDelete(g_d1_queryirq_sem); +#elif (BSP_CFG_RTOS == 1) // ThreadX + + /* Delete semaphore */ + tx_semaphore_delete(&g_d1_queryirq_sem); +#endif + + return 1; +} + +/*******************************************************************************************************************//** + * This function waits for DRW_INT with timeout. + * + * @param[in] handle Pointer to the d1_device object (Not used). + * @param[in] irqmask Interrupt ID (Not used. FSP only uses Display list IRQ). + * @param[in] timeout Timeout value. + * @retval 0 The function returns 0 if the wait times out. + * @retval 1 The function returns 1 if DRW_INT was detected. + **********************************************************************************************************************/ +d1_int_t d1_queryirq (d1_device * handle, d1_int_t irqmask, d1_int_t timeout) +{ + d1_int_t ret = 1; + + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(irqmask); + +#if (BSP_CFG_RTOS == 2) // FreeRTOS + BaseType_t err; + + /* Wait for dlist processing to complete. */ + /* d1_to_wait_forever (D2) == -1 == portMAX_DELAY (FreeRTOS), so just pass the raw timeout through. */ + err = xSemaphoreTake(g_d1_queryirq_sem, (uint32_t) timeout); + + /* If the wait timed out return 0. */ + if (pdPASS != err) + { + ret = 0; + } +#elif (BSP_CFG_RTOS == 1) // ThreadX + + /* Wait for dlist processing to complete. */ + /* d1_to_wait_forever (D2) == -1 == TX_WAIT_FOREVER (ThreadX), so just pass the raw timeout through. */ + if (TX_SUCCESS != tx_semaphore_get(&g_d1_queryirq_sem, (ULONG) timeout)) + { + ret = 0; + } +#else + + /* Wait for dlist processing to complete. */ + while (!g_dlist_done && timeout) + { + if (timeout != d1_to_wait_forever) + { + timeout--; + } + } + + /* If the wait timed out return 0. */ + if (!g_dlist_done) + { + ret = 0; + } + g_dlist_done = 0; +#endif + + return ret; +} + +/*******************************************************************************************************************//** + * @} + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Increments the dlist array pointer in indirect mode and indicates dlist completion in both modes. + **********************************************************************************************************************/ +void drw_int_isr (void) +{ + FSP_CONTEXT_SAVE + + uint32_t int_status; + +#if (BSP_CFG_RTOS == 2) // FreeRTOS + BaseType_t context_switch = pdFALSE; +#endif + + /* Get current IRQ number */ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Get D/AVE 2D interrupt status. */ + int_status = R_DRW->STATUS; + + /* Clear all the D/AVE 2D interrupts (keep the Display list interrupt enable). */ + R_DRW->IRQCTL = DRW_PRV_IRQCTL_ALLIRQ_CLEAR_AND_DLISTIRQ_ENABLE; + + /* Display list interrupt? */ + if (int_status & DRW_PRV_STATUS_DLISTIRQ_TRIGGERED) + { +#if DRW_CFG_USE_DLIST_INDIRECT + + /* Get handle from ISR context */ + d1_device_flex * p_context = (d1_device_flex *) R_FSP_IsrContextGet(irq); + + /* If indirect mode is enabled and there are more display lists left then continue with the next list */ + if ((p_context->dlist_indirect_enable) && (NULL != (uint32_t *) *(p_context->pp_dlist_indirect_start))) + { + /* Start D/AVE 2D. */ + R_DRW->DLISTSTART = *(p_context->pp_dlist_indirect_start); + + /* Get next display list start address. */ + p_context->pp_dlist_indirect_start++; + } + else +#endif + { +#if (BSP_CFG_RTOS == 2) // FreeRTOS + + /* Put semaphore */ + xSemaphoreGiveFromISR(g_d1_queryirq_sem, &context_switch); + + /* Pend a context switch at the end of this ISR, if necessary */ + portYIELD_FROM_ISR(context_switch); +#elif (BSP_CFG_RTOS == 1) // ThreadX + + /* Put semaphore */ + tx_semaphore_ceiling_put(&g_d1_queryirq_sem, 1UL); +#else + + /* Increment dlist completion flag. */ + g_dlist_done++; +#endif + } + } + else + { + /* Do nothing. */ + } + + /* Clear IRQ status. */ + R_BSP_IrqStatusClear(irq); + + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_memory.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_memory.c new file mode 100644 index 0000000000..bee6473665 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_drw/r_drw_memory.c @@ -0,0 +1,333 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_drw_memory.c + * Description : This file defines the D/AVE D1 low-level driver memory management functions. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include +#include "r_drw_base.h" +#include "r_drw_cfg.h" + +#if (BSP_CFG_RTOS == 2) // FreeRTOS + #include "FreeRTOS.h" +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Extern functions + **********************************************************************************************************************/ + +/* Optional user-defined memory allocation functions */ +#if DRW_CFG_CUSTOM_MALLOC +extern void * d1_malloc(size_t size); +extern void d1_free(void * ptr); + +#endif + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @internal + * @addtogroup DRW_PRV Internal DRW Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Allocates memory in the driver heap. + * + * @param[in] size Size of the memory to be allocated. + * @retval Non-NULL The function returns a pointer to the allocation if successful. + * @retval NULL The function returns NULL if memory allocation failed. + **********************************************************************************************************************/ +void * d1_allocmem (d1_uint_t size) +{ +#if DRW_CFG_CUSTOM_MALLOC + + /* Use user-defined malloc */ + return d1_malloc((size_t) size); +#elif (BSP_CFG_RTOS == 2) // FreeRTOS + #if configSUPPORT_DYNAMIC_ALLOCATION + + /* Use FreeRTOS heap */ + return pvPortMalloc((size_t) size); + #else + + /* If RTOS dynamic allocation is disabled then allocate d1 heap data in the main heap. */ + return malloc((size_t) size); + #endif +#else + + /* If no RTOS is present then allocate d1 heap data in the main heap. */ + return malloc((size_t) size); +#endif +} + +/*******************************************************************************************************************//** + * Frees the specified memory area in the driver heap. + * + * @param[in] ptr Pointer to the memory area to be freed. + **********************************************************************************************************************/ +void d1_freemem (void * ptr) +{ +#if DRW_CFG_CUSTOM_MALLOC + + /* Use user-defined free */ + d1_free(ptr); +#elif (BSP_CFG_RTOS == 2) // FreeRTOS + #if configSUPPORT_DYNAMIC_ALLOCATION + + /* Use FreeRTOS heap */ + vPortFree(ptr); + #else + + /* If RTOS dynamic allocation is disabled then use free(). */ + free(ptr); + #endif +#else + + /* If no RTOS is present then use free(). */ + free(ptr); +#endif +} + +/*******************************************************************************************************************//** + * This function intends to return the size of the given memory block but we don't return a valid value. + * This function always returns 1. + * + * @param[in] ptr Pointer to a memory block in the heap. + * @retval 1 The function always returns 1. + **********************************************************************************************************************/ +d1_uint_t d1_memsize (void * ptr) +{ + FSP_PARAMETER_NOT_USED(ptr); + + /* Always return 1. */ + return 1U; +} + +/*******************************************************************************************************************//** + * Allocate video memory. + * FSP does not use virtual memory so this function simply calls d1_allocmem. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] memtype Type of memory (not used). + * @param[in] size Number of bytes to allocate. + * @retval Non-NULL The function returns a pointer to the allocation if successful. + * @retval NULL The function returns Null if memory allocation failed. + **********************************************************************************************************************/ +void * d1_allocvidmem (d1_device * handle, d1_int_t memtype, d1_uint_t size) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(memtype); + + return d1_allocmem(size); +} + +/*******************************************************************************************************************//** + * Free video memory. + * FSP does not use virtual memory so this function simply calls d1_freemem. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] memtype Type of memory (not used). + * @param[in] ptr Address returned by d1_allocvidmem. + **********************************************************************************************************************/ +void d1_freevidmem (d1_device * handle, d1_int_t memtype, void * ptr) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(memtype); + + d1_freemem(ptr); +} + +/*******************************************************************************************************************//** + * Get current memory status. This function is not used and always returns 0. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] memtype Type of memory (not used). + * @param[in] query Type of requested information (not used). + * @retval 0 The function always return 0. + **********************************************************************************************************************/ +d1_int_t d1_queryvidmem (d1_device * handle, d1_int_t memtype, d1_int_t query) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(memtype); + FSP_PARAMETER_NOT_USED(query); + + return 0; +} + +/*******************************************************************************************************************//** + * Return information about system memory architecture. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @retval d1_ma_unified The function always return d1_ma_unified (Unified memory architecture). + **********************************************************************************************************************/ +d1_int_t d1_queryarchitecture (d1_device * handle) +{ + FSP_PARAMETER_NOT_USED(handle); + + return d1_ma_unified; +} + +/*******************************************************************************************************************//** + * Map video memory for direct CPU access. + * FSP does not use virtual memory so this function simply returns the passed pointer. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] ptr Video memory address returned by d1_allocvidmem. + * @param[in] flags Memory mapping flags (not used). + * @retval ptr The function just returns ptr back as there is no mapping required for FSP. + **********************************************************************************************************************/ +void * d1_mapvidmem (d1_device * handle, void * ptr, d1_int_t flags) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(flags); + + /* Nothing special necessary for FSP. */ + return ptr; +} + +/*******************************************************************************************************************//** + * Release memory mapping. + * FSP does not use virtual memory so this function always returns 1. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] ptr Mapped video memory address returned by d1_mapvidmem (not used). + * @retval 1 The function always return 1. + **********************************************************************************************************************/ +d1_int_t d1_unmapvidmem (d1_device * handle, void * ptr) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(ptr); + + /* No unmapping necessary for FSP. */ + return 1; +} + +/*******************************************************************************************************************//** + * Map CPU accessible address of a video memory block back to video memory address. + * FSP does not use virtual memory so this function simply returns the passed pointer. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] ptr CPU accessible address pointing to a video memory block originally allocated using d1_allocvidmem. + * @retval ptr The function just returns ptr back as there is no mapping required for FSP. + **********************************************************************************************************************/ +void * d1_maptovidmem (d1_device * handle, void * ptr) +{ + FSP_PARAMETER_NOT_USED(handle); + + /* Nothing special necessary for FSP. */ + return ptr; +} + +/*******************************************************************************************************************//** + * Map already allocated video memory address to a CPU-accessible address. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] ptr Video memory address returned by d1_allocvidmem. + * @retval ptr The function just returns ptr back as there is no mapping required for FSP. + **********************************************************************************************************************/ +void * d1_mapfromvidmem (d1_device * handle, void * ptr) +{ + FSP_PARAMETER_NOT_USED(handle); + + /* Nothing special necessary for FSP. */ + return ptr; +} + +/*******************************************************************************************************************//** + * Copy data to video memory. Destination (video) memory area has to be allocated by d1_allocvidmem. + * As RA devices do not have separate video memory this simply calls memcpy. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] dst pointer into video memory (destination). + * @param[in] src Pointer into system memory (source). + * @param[in] size Number of bytes to copy. + * @param[in] flags Bitfield containing additional information on data to be copied (not used). + * @retval 1 The function always return 1. + **********************************************************************************************************************/ +d1_int_t d1_copytovidmem (d1_device * handle, void * dst, const void * src, d1_uint_t size, d1_int_t flags) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(flags); + + /* Simply use C standard memcpy. */ + memcpy(dst, src, size); + + return 1; +} + +/*******************************************************************************************************************//** + * Copy data from video memory. Source (video) memory area has to be allocated by d1_allocvidmem. + * As RA devices do not have separate video memory this simply calls memcpy. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] dst pointer into system memory (destination). + * @param[in] src Pointer into video memory (source). + * @param[in] size Number of bytes to copy. + * @param[in] flags Reserved for future use. + * @retval 1 The function always return 1. + **********************************************************************************************************************/ +d1_int_t d1_copyfromvidmem (d1_device * handle, void * dst, const void * src, d1_uint_t size, d1_int_t flags) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(flags); + + /* Simply use C standard memcpy. */ + memcpy(dst, src, size); + + return 1; +} + +/*******************************************************************************************************************//** + * Flush CPU data caches. This function may be overridden by the user to perform cache maintenance. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] memtype Memory pools to flush (can be ORed together; not used). + * @retval 1 The function always return 1. + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE d1_int_t d1_cacheflush (d1_device * handle, d1_int_t memtype) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(memtype); + + return 1; +} + +/*******************************************************************************************************************//** + * Flush part of CPU data caches. This function may be overridden by the user to perform cache maintenance. + * + * @param[in] handle Pointer to the d1_device object (not used). + * @param[in] memtype Memory pools to flush (can be ORed together; not used). + * @param[in] ptr Start address of memory to be flushed (not used). + * @param[in] size Size of memory to be flushed (not used). + * @retval 1 The function always return 1. + **********************************************************************************************************************/ +BSP_WEAK_REFERENCE d1_int_t d1_cacheblockflush (d1_device * handle, d1_int_t memtype, const void * ptr, d1_uint_t size) +{ + FSP_PARAMETER_NOT_USED(handle); + FSP_PARAMETER_NOT_USED(memtype); + FSP_PARAMETER_NOT_USED(ptr); + FSP_PARAMETER_NOT_USED(size); + + return 1; +} + +/*******************************************************************************************************************//** + * @} + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dsmif/r_dsmif.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dsmif/r_dsmif.c new file mode 100644 index 0000000000..b9bb55b121 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dsmif/r_dsmif.c @@ -0,0 +1,1139 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "r_dsmif_cfg.h" +#include "r_dsmif.h" + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define DSMIF_OPEN ((uint32_t) ('D' << 24U) | ('S' << 16U) | ('M' << 8U) | ('I' << 0U)) + +#define DSMIF_DATA_CHANNEL_MASK (0x03U) +#define DSMIF_DATA_REGID_MASK (0x0FU) +#define DSMIF_DATA_TYPE_MASK (0x70U) +#define DSMIF_DATA_TYPE_SHIFT (0x4U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* DSMIF data register */ +typedef enum e_dsmif_current_data +{ + DSMIF_CURRENT_DATA = 0, // DSCDRCHn : Current Data Register + DSMIF_CURRENT_DATA_CAPTURE_A = 1, // DSCCDRACHn : Capture Current Data Register A + DSMIF_CURRENT_DATA_CAPTURE_B = 2, // DSCCDRBCHn : Capture Current Data Register B + DSMIF_OVERCURRENT_DATA = 3, // DSOCDRCHn : Overcurrent Data Register + DSMIF_OVERCURRENT0_CAPTURE_DATA = 4, // DSCOCDR0CHn : Overcurrent Capture Data Register 0 + DSMIF_OVERCURRENT1_CAPTURE_DATA = 5, // DSCOCDR1CHn : Overcurrent Capture Data Register 1 + DSMIF_OVERCURRENT2_CAPTURE_DATA = 6, // DSCOCDR2CHn : Overcurrent Capture Data Register 2 + DSMIF_OVERCURRENT_SUM_CAPTURE_DATA = 7, // DSSECDRn : Overcurrent Sum Error Detect Capture Data Register n +} dsmif_current_data_t; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + +static fsp_err_t r_dsmif_open_param_check(dsmif_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg); + +#endif + +static void r_dsmif_start(dsmif_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t r_dsmif_stop(dsmif_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t r_dsmif_read(dsmif_instance_ctrl_t * const p_instance_ctrl, + adc_channel_t const reg_id, + uint16_t * p_data); +static void r_dsmif_irq_enable(dsmif_instance_ctrl_t * const p_instance_ctrl, + dsmif_interrupt_cfg_t const * const p_irq_cfg); +static void r_dsmif_irq_disable(dsmif_interrupt_cfg_t const * const p_irq_cfg); + +static void r_dsmif_call_callback(dsmif_instance_ctrl_t * p_instance_ctrl, adc_event_t event, adc_channel_t channel); + +void dsmif_cdupdn_isr(void); +void dsmif_cdaupdn_isr(void); +void dsmif_cdbupdn_isr(void); +void dsmif_cdupd_com_isr(void); +void dsmif_cdaupd_com_isr(void); +void dsmif_cdbupd_com_isr(void); +void dsmif_err_isr(void); + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** DSMIF Implementation of DSMIF interface. */ +const adc_api_t g_adc_on_dsmif = +{ + .open = R_DSMIF_Open, + .scanCfg = R_DSMIF_ScanCfg, + .scanStart = R_DSMIF_ScanStart, + .scanGroupStart = R_DSMIF_ScanGroupStart, + .scanStop = R_DSMIF_ScanStop, + .scanStatusGet = R_DSMIF_ScanStatusGet, + .read = R_DSMIF_Read, + .read32 = R_DSMIF_Read32, + .calibrate = R_DSMIF_Calibrate, + .offsetSet = R_DSMIF_OffsetSet, + .callbackSet = R_DSMIF_CallbackSet, + .close = R_DSMIF_Close, + .infoGet = R_DSMIF_InfoGet, +}; + +/*******************************************************************************************************************//** + * @addtogroup DSMIF + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Applies power to the DSMIF and initializes the hardware based on the user configuration. + * As part of this initialization, set interrupts, set DSMIF error interrupt registers, etc. + * + * @retval FSP_SUCCESS Configuration successful. + * @retval FSP_ERR_ASSERTION An input pointer is NULL or an input parameter is invalid. + * @retval FSP_ERR_ALREADY_OPEN Control block is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt is disabled + * @retval FSP_ERR_IP_UNIT_NOT_PRESENT The Unit requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_Open (adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg) +{ + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + err = r_dsmif_open_param_check(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Set all p_instance_ctrl fields prior to using it in any functions. */ + p_instance_ctrl->p_cfg = p_cfg; + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + + dsmif_extended_cfg_t const * p_extend = p_cfg->p_extend; + + /* Calculate the register base address. */ + uint32_t address_offset = ((uint32_t) R_DSMIF1 - (uint32_t) R_DSMIF0); + p_instance_ctrl->p_reg = (R_DSMIF0_Type *) ((uint32_t) R_DSMIF0 + address_offset * p_cfg->unit); + + /* Release from the module-stop state */ + R_BSP_MODULE_START(FSP_IP_DSMIF, p_cfg->unit); + + /* Set the DSMIF core clock. */ + p_instance_ctrl->p_reg->DSCCSCR = (uint32_t) p_extend->clock_selection; + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + + /* Set Overcurrent Sum Error Detection Lower Limit. */ + p_instance_ctrl->p_reg->DSSELTR = p_extend->overcurrent_sum_error_lower_limit; + + /* Set Overcurrent Sum Error Detection Upper Limit. */ + p_instance_ctrl->p_reg->DSSEHTR = p_extend->overcurrent_sum_error_upper_limit; + + /* Set Overcurrent Sum Error Channel(s). */ + p_instance_ctrl->p_reg->DSSECSR = p_extend->overcurrent_sum_error_channel; + + /* Set the Overcurrent Sum Error Interrupt. */ + p_instance_ctrl->p_reg->DSSEICR = p_extend->overcurrent_sum_error_enable; +#endif + + /* Set data format for measurement results. */ + p_instance_ctrl->p_reg->DSCMSR = (uint32_t) !p_cfg->alignment | + ((uint32_t) p_extend->synchronization_mode << R_DSMIF0_DSCMSR_CISM_Pos); + + /* Enable common interrupts. */ + p_instance_ctrl->p_reg->DSCICR = R_DSMIF0_DSCICR_IUCE_Msk | R_DSMIF0_DSCICR_IAUCE_Msk | R_DSMIF0_DSCICR_IBUCE_Msk; + + /* Register settings for each channel */ + for (uint32_t ch = 0U; ch < DSMIF_MAX_NUM_CHANNELS; ch++) + { + if (p_extend->p_channel_cfgs[ch] != NULL) + { + /* Get the channel register struct for this channel. */ + __IOM R_DSMIF0_CH_Type * p_channel_reg = &p_instance_ctrl->p_reg->CH[ch]; + + /* Get the channel configuration for this channel. */ + dsmif_channel_cfg_t const * p_channel_cfg = p_extend->p_channel_cfgs[ch]; + dsmif_clock_cfg_t const * p_clock_cfg = &p_channel_cfg->clock_cfg; + dsmif_trigger_cfg_t const * p_trigger_cfg = &p_channel_cfg->trigger_cfg; + dsmif_filter_cfg_t const * p_filter_cfg = &p_channel_cfg->filter_cfg; + dsmif_interrupt_cfg_t const * p_irq_cfg = &p_channel_cfg->irq_cfg; + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + dsmif_error_detection_cfg_t const * p_error_detection_cfg = &p_channel_cfg->error_detection_cfg; + + dsmif_filter_cfg_t const * p_overcurrent_filter_cfg = + &p_error_detection_cfg->overcurrent_filter_cfg; +#endif + + /* Set interrupt settings. */ + uint32_t dsicr = R_DSMIF0_CH_DSICR_IUE_Msk | + R_DSMIF0_CH_DSICR_IAUE_Msk | + R_DSMIF0_CH_DSICR_IBUE_Msk; + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + dsicr |= (uint32_t) p_error_detection_cfg->short_circuit_detection_enable << R_DSMIF0_CH_DSICR_ISE_Pos; + dsicr |= (uint32_t) p_error_detection_cfg->overcurrent_detection_enable << R_DSMIF0_CH_DSICR_IOEL0_Pos; + dsicr |= (uint32_t) p_error_detection_cfg->overcurrent_window_notification_enable << + R_DSMIF0_CH_DSICR_OWNE0_Pos; +#endif + + p_channel_reg->DSICR = dsicr; + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + + /* Set Overcurrent Threshold settings. */ + p_channel_reg->TR[0].DSOCL = p_error_detection_cfg->overcurrent_lower_limit[0]; + p_channel_reg->TR[1].DSOCL = p_error_detection_cfg->overcurrent_lower_limit[1]; + p_channel_reg->TR[2].DSOCL = p_error_detection_cfg->overcurrent_lower_limit[2]; + p_channel_reg->TR[0].DSOCH = p_error_detection_cfg->overcurrent_upper_limit[0]; + p_channel_reg->TR[1].DSOCH = p_error_detection_cfg->overcurrent_upper_limit[1]; + p_channel_reg->TR[2].DSOCH = p_error_detection_cfg->overcurrent_upper_limit[2]; + + /* Set Overcurrent Window Notification mode. */ + p_channel_reg->DSODWCR = (uint32_t) p_error_detection_cfg->overcurrent_window_notification_mode; + + /* Set Short Circuit Detection settings. */ + p_channel_reg->DSSCTSR = + ((p_error_detection_cfg->short_circuit_detection_low_count << R_DSMIF0_CH_DSSCTSR_SCNTL_Pos) | + (p_error_detection_cfg->short_circuit_detection_high_count << R_DSMIF0_CH_DSSCTSR_SCNTH_Pos)); + p_channel_reg->DSEDCR = + ((uint32_t) p_error_detection_cfg->short_circuit_detection_enable << R_DSMIF0_CH_DSEDCR_SDE_Pos); +#endif + + /* Set Measurement Capture Trigger settings. */ + p_channel_reg->DSCMCTCR = + (((uint32_t) p_trigger_cfg->capture_trigger_a << R_DSMIF0_CH_DSCMCTCR_CTSELA_Pos) | + ((uint32_t) p_trigger_cfg->capture_trigger_b << R_DSMIF0_CH_DSCMCTCR_CTSELB_Pos) | + ((uint32_t) p_trigger_cfg->filter_initialization_trigger << R_DSMIF0_CH_DSCMCTCR_DITSEL_Pos) | + ((uint32_t) p_trigger_cfg->filter_initialization_edge << R_DSMIF0_CH_DSCMCTCR_DEDGE_Pos)); + + /* Set channel clock settings. */ + p_channel_reg->DSCMCCR = (((uint32_t) p_clock_cfg->direction << R_DSMIF0_CH_DSCMCCR_CKDIR_Pos) | + ((uint32_t) p_clock_cfg->edge << R_DSMIF0_CH_DSCMCCR_SEDGE_Pos) | + ((uint32_t) p_clock_cfg->divider << R_DSMIF0_CH_DSCMCCR_CKDIV_Pos)); + + /* Set Current Measurement Filter settings. */ + p_channel_reg->DSCMFCR = + (((uint32_t) p_filter_cfg->filter_order << R_DSMIF0_CH_DSCMFCR_CMSINC_Pos) | + ((uint32_t) p_filter_cfg->decimation_count << R_DSMIF0_CH_DSCMFCR_CMDEC_Pos) | + ((uint32_t) p_filter_cfg->data_shift << R_DSMIF0_CH_DSCMFCR_CMSH_Pos)); + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + + /* Set Overcurrent Measurement Filter settings. */ + p_channel_reg->DSOCFCR = + (((uint32_t) p_overcurrent_filter_cfg->filter_order << R_DSMIF0_CH_DSOCFCR_OCSINC_Pos) | + ((uint32_t) p_overcurrent_filter_cfg->decimation_count << R_DSMIF0_CH_DSOCFCR_OCDEC_Pos) | + ((uint32_t) p_overcurrent_filter_cfg->data_shift << R_DSMIF0_CH_DSOCFCR_OCSH_Pos)); +#endif + + /* Enable configured channel interrupts. */ + r_dsmif_irq_enable(p_instance_ctrl, p_irq_cfg); + } + } + + /* Enable the common capture data update interrupt request if it is provided. */ + if (p_extend->common_current_data_irq >= 0) + { + R_BSP_IrqCfgEnable(p_extend->common_current_data_irq, p_extend->common_current_data_ipl, p_instance_ctrl); + } + + /* Enable the common capture data a interrupt request if it is provided. */ + if (p_extend->common_capture_data_a_irq >= 0) + { + R_BSP_IrqCfgEnable(p_extend->common_capture_data_a_irq, p_extend->common_capture_data_a_ipl, p_instance_ctrl); + } + + /* Enable the common capture data b interrupt request if it is provided. */ + if (p_extend->common_capture_data_b_irq >= 0) + { + R_BSP_IrqCfgEnable(p_extend->common_capture_data_b_irq, p_extend->common_capture_data_b_ipl, p_instance_ctrl); + } + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + + /* Enable the error interrupt request if it is provided. */ + if (p_extend->common_error_irq >= 0) + { + R_BSP_IrqCfgEnable(p_extend->common_error_irq, p_extend->common_error_ipl, p_instance_ctrl); + } +#endif + + /* Mark driver as open by initializing it to "DSMI" - its ASCII equivalent. */ + p_instance_ctrl->open = DSMIF_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::scanCfg is not supported on DSMIF. + * + * @retval FSP_ERR_UNSUPPORTED This function is not supported by the DSMIF instance. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_ScanCfg (adc_ctrl_t * p_ctrl, void const * const p_extend) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_extend); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Starts all configured DSMIF channels + * + * @note After executing R_DSMIF_ScanStart, it is necessary to wait until the filter result is output stably. + * + * @retval FSP_SUCCESS Scan started or hardware triggers enabled successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_ScanStart (adc_ctrl_t * p_ctrl) +{ + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are not NULL and ensure the DSMIF unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(DSMIF_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + r_dsmif_start(p_instance_ctrl); + + /* Return the error code */ + return err; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::scanGroupStart is not supported on DSMIF. + * + * @retval FSP_ERR_UNSUPPORTED This function is not supported by the DSMIF instance. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_ScanGroupStart (adc_ctrl_t * p_ctrl, adc_group_mask_t group_mask) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(group_mask); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Stops any in-progress scan started by software. + * + * @retval FSP_SUCCESS Scan stopped or hardware triggers disabled successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + * @retval FSP_ERR_TIMEOUT Timeout error. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_ScanStop (adc_ctrl_t * p_ctrl) +{ + fsp_err_t err; + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are not NULL and ensure the DSMIF unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(DSMIF_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + err = r_dsmif_stop(p_instance_ctrl); + + /* Return the error code */ + return err; +} + +/*******************************************************************************************************************//** + * Returns the status of a scan started by software. + * + * @retval FSP_SUCCESS No software scan is in progress. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_ScanStatusGet (adc_ctrl_t * p_ctrl, adc_status_t * p_status) +{ + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are not NULL and ensure the DSMIF unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(DSMIF_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + if (0U == (p_instance_ctrl->p_reg->DSCSSR & (R_DSMIF0_DSCSSR_CHSTATE_Msk | \ + (R_DSMIF0_DSCSSR_CHSTATE_Msk << 4) | + (R_DSMIF0_DSCSSR_CHSTATE_Msk << 8)))) + { + p_status->state = ADC_STATE_IDLE; + } + else + { + p_status->state = ADC_STATE_SCAN_IN_PROGRESS; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the most recent result from a channel. + * + * @retval FSP_SUCCESS Result in p_data. + * @retval FSP_ERR_ASSERTION An input pointer was NULL or an input parameter was invalid. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_Read (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data) +{ +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_data != NULL); +#endif + + return r_dsmif_read(p_ctrl, reg_id, p_data); +} + +/*******************************************************************************************************************//** + * Reads the most recent conversion result from a single channel into a 32-bit result. + * + * @retval FSP_SUCCESS Result in p_data. + * @retval FSP_ERR_ASSERTION An input pointer was NULL or an input parameter was invalid. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_Read32 (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data) +{ +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_data != NULL); +#endif + uint16_t data16 = 0; + fsp_err_t err = r_dsmif_read(p_ctrl, reg_id, &data16); + if (FSP_SUCCESS == err) + { + dsmif_instance_ctrl_t * const p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + if (ADC_ALIGNMENT_LEFT == p_instance_ctrl->p_cfg->alignment) + { + *p_data = (uint32_t) data16 << 16U; + } + else + { + *p_data = data16; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::calibrate is not supported on DSMIF. + * + * @retval FSP_ERR_UNSUPPORTED This function is not supported by the DSMIF instance. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_Calibrate (adc_ctrl_t * p_ctrl, void const * p_extend) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_extend); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::offsetSet is not supported on DSMIF. + * + * @retval FSP_ERR_UNSUPPORTED This function is not supported by the DSMIF instance. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_OffsetSet (adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t const offset) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(reg_id); + FSP_PARAMETER_NOT_USED(offset); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_CallbackSet (adc_ctrl_t * const p_ctrl, + void ( * p_callback)(adc_callback_args_t *), + void * const p_context, + adc_callback_args_t * const p_callback_memory) +{ + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(DSMIF_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops any scan in progress, disables interrupts, and powers down the DSMIF peripheral. + * + * @note This function is delayed at least until the outage is complete, as required by the DSMIF outage procedure. + * + * @retval FSP_SUCCESS Instance control block closed successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_Close (adc_ctrl_t * p_ctrl) +{ + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking*/ +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are not NULL and ensure the DSMIF unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(DSMIF_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Mark driver as closed */ + p_instance_ctrl->open = 0U; + + dsmif_extended_cfg_t const * const p_extend = (dsmif_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + for (uint32_t ch = 0U; ch < DSMIF_MAX_NUM_CHANNELS; ch++) + { + p_instance_ctrl->p_reg->CH[ch].DSICR = 0x00000000U; + + if (NULL != p_extend->p_channel_cfgs[ch]) + { + /* Disable channel interrupts. */ + r_dsmif_irq_disable(&p_extend->p_channel_cfgs[ch]->irq_cfg); + } + } + + /* Disabled common interrupts. */ + if (p_extend->common_current_data_irq >= 0) + { + R_BSP_IrqDisable(p_extend->common_current_data_irq); + } + + if (p_extend->common_capture_data_a_irq >= 0) + { + R_BSP_IrqDisable(p_extend->common_capture_data_a_irq); + } + + if (p_extend->common_capture_data_b_irq >= 0) + { + R_BSP_IrqDisable(p_extend->common_capture_data_b_irq); + } + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + if (p_extend->common_error_irq >= 0) + { + R_BSP_IrqDisable(p_extend->common_error_irq); + } +#endif + + /* Stop processing(No error is returned because it is forcibly terminated.) */ + r_dsmif_stop(p_instance_ctrl); + + R_BSP_MODULE_STOP(FSP_IP_DSMIF, p_instance_ctrl->p_cfg->unit); + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::infoGet is not supported on DSMIF. + * + * @retval FSP_ERR_UNSUPPORTED This function is not supported by the DSMIF instance. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_InfoGet (adc_ctrl_t * const p_ctrl, adc_info_t * const p_adc_info) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_adc_info); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Enable error detection. + * + * @retval FSP_SUCCESS Configuration setting successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_ErrorDetectionEnable (adc_ctrl_t * p_ctrl) +{ +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + #if DSMIF_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are not NULL and ensure the DSMIF unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(DSMIF_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + adc_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + + dsmif_extended_cfg_t const * p_cfg_extend = (dsmif_extended_cfg_t *) p_cfg->p_extend; + + /* Clear error flags after reading. */ + p_instance_ctrl->p_reg->DSCOCNSCR = p_instance_ctrl->p_reg->DSCOCNSR; + p_instance_ctrl->p_reg->DSCOCESCR = p_instance_ctrl->p_reg->DSCOCESR; + p_instance_ctrl->p_reg->DSCESCR = p_instance_ctrl->p_reg->DSCESR; + + /* Enable Overcurrent Detection and Window Notification for each channel. */ + for (uint32_t ch = 0U; ch < DSMIF_MAX_NUM_CHANNELS; ch++) + { + if (NULL != p_cfg_extend->p_channel_cfgs[ch]) + { + __IOM R_DSMIF0_CH_Type * p_channel_reg = &p_instance_ctrl->p_reg->CH[ch]; + dsmif_error_detection_cfg_t const * p_error_detection_cfg = + &p_cfg_extend->p_channel_cfgs[ch]->error_detection_cfg; + + p_channel_reg->DSODCR = + ((uint32_t) p_error_detection_cfg->overcurrent_detection_enable << R_DSMIF0_CH_DSODCR_ODEL_Pos) | + ((uint32_t) p_error_detection_cfg->overcurrent_window_notification_enable << + R_DSMIF0_CH_DSODCR_OWFE_Pos); + } + } + + /* Enable sum error detection. */ + p_instance_ctrl->p_reg->DSSECR = + (uint32_t) ((p_cfg_extend->overcurrent_sum_error_enable_b.lower_limit_enable << R_DSMIF0_DSSECR_SEEL_Pos) | + (p_cfg_extend->overcurrent_sum_error_enable_b.upper_limit_enable << + R_DSMIF0_DSSECR_SEEH_Pos)); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Returns the error status of a scan started by software. + * + * @retval FSP_SUCCESS No software scan is in progress. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_DSMIF_ErrorStatusGet (adc_ctrl_t * p_ctrl, dsmif_error_status_t * p_error_status) +{ +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) p_ctrl; + + #if DSMIF_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are not NULL and ensure the DSMIF unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_error_status); + FSP_ERROR_RETURN(DSMIF_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + uint32_t dscesr = p_instance_ctrl->p_reg->DSCESR; + + p_error_status->channel_overcurrent_window_status = + (dsmif_overcurrent_window_notification_status_t) (p_instance_ctrl->p_reg->DSCOCNSR); + p_error_status->channel_overcurrent_status = + (dsmif_overcurrent_status_t) (p_instance_ctrl->p_reg->DSCOCESR); + p_error_status->channel_short_circuit_status = (dsmif_short_circuit_status_t) (dscesr & UINT16_MAX); + p_error_status->overcurrent_sum_status = (dsmif_overcurrent_sum_status_t) (dscesr >> 16U); + + /* Clear error flags after reading. */ + p_instance_ctrl->p_reg->DSCOCNSCR = p_error_status->channel_overcurrent_window_status; + p_instance_ctrl->p_reg->DSCOCESCR = p_error_status->channel_overcurrent_status; + p_instance_ctrl->p_reg->DSCESCR = dscesr; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_error_status); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * @} (end addtogroup DSMIF) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Validates the input parameters to open(). + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS No invalid configurations identified. + * @retval FSP_ERR_ALREADY_OPEN Control block is already open. + * @retval FSP_ERR_ASSERTION An input pointer is NULL or an input parameter is invalid. + * @retval FSP_ERR_IRQ_BSP_DISABLED A callback is provided, but the interrupt is not enabled. + * @retval FSP_ERR_IP_UNIT_NOT_PRESENT The Unit requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +static fsp_err_t r_dsmif_open_param_check (dsmif_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg) +{ + /* Verify the pointers are not NULL. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + + /* Verify the control block has not already been initialized. */ + FSP_ERROR_RETURN(DSMIF_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Verify the unit exists on the MCU. */ + FSP_ERROR_RETURN(((1U << p_cfg->unit) & BSP_PERIPHERAL_DSMIF_CHANNEL_MASK), FSP_ERR_IP_UNIT_NOT_PRESENT); + + dsmif_extended_cfg_t const * const p_extend = (dsmif_extended_cfg_t *) p_cfg->p_extend; + + /* If a common interrupt is enabled, then a callback must be provided. */ + if ( + #if DSMIF_CFG_ERROR_DETECTION_SUPPORT + (p_extend->common_error_irq >= 0) || + #endif + (p_extend->common_current_data_irq >= 0) || + (p_extend->common_capture_data_a_irq >= 0) || + (p_extend->common_capture_data_b_irq >= 0)) + { + FSP_ASSERT(p_cfg->p_callback != NULL); + } + + /* If a channel interrupt is enabled, then a callback must be provided. */ + for (uint32_t i = 0; i < DSMIF_MAX_NUM_CHANNELS; i++) + { + if ((NULL != p_extend->p_channel_cfgs[i]) && + ((p_extend->p_channel_cfgs[i]->irq_cfg.capture_data_a_irq >= 0) || + (p_extend->p_channel_cfgs[i]->irq_cfg.capture_data_b_irq >= 0))) + { + FSP_ASSERT(p_cfg->p_callback != NULL); + break; + } + } + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Start DSMIF conversion on all configured channels. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * + **********************************************************************************************************************/ +static void r_dsmif_start (dsmif_instance_ctrl_t * const p_instance_ctrl) +{ + dsmif_extended_cfg_t const * p_extend = (dsmif_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + + /* Write channel mask to DSCSTRTR to start all configured channels at the same time. */ + p_instance_ctrl->p_reg->DSCSTRTR = p_extend->channel_mask; +} + +/*******************************************************************************************************************//** + * Stop DMSIF conversion on all configured channels. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * + * @retval FSP_SUCCESS Stop processing succeeded. + * @retval FSP_ERR_TIMEOUT Timeout error. + **********************************************************************************************************************/ +static fsp_err_t r_dsmif_stop (dsmif_instance_ctrl_t * const p_instance_ctrl) +{ + dsmif_extended_cfg_t const * p_extend = (dsmif_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + + /* Write channel mask to DSCSTPTR to stop all configured channels at the same time. */ + p_instance_ctrl->p_reg->DSCSTPTR = p_extend->channel_mask; + + /* Wait for all DSMIF channels to stop (Refer to "DSMIF / Stop Flow" section in the MCU user manaul). */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->DSCSSR, 0); + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + + /* Disable overcurrent detection of all target channels */ + for (uint32_t ch = 0U; ch < DSMIF_MAX_NUM_CHANNELS; ch++) + { + p_instance_ctrl->p_reg->CH[ch].DSODCR = 0; + } + + /* Disable sum error detection */ + p_instance_ctrl->p_reg->DSSECR = 0; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures interrupts and ensures required interrupts are enabled. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] reg_id Channel to read data from + * @param[out] p_data Pointer to store the conversion result + **********************************************************************************************************************/ +static fsp_err_t r_dsmif_read (dsmif_instance_ctrl_t * const p_instance_ctrl, + adc_channel_t const reg_id, + uint16_t * p_data) +{ +#if DSMIF_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are not NULL and ensure the DSMIF unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(DSMIF_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + dsmif_extended_cfg_t const * p_extend = (dsmif_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + FSP_ASSERT(0U != ((1U << ((uint32_t) reg_id & DSMIF_DATA_REGID_MASK)) & p_extend->channel_mask)); +#elif DSMIF_CFG_ERROR_DETECTION_SUPPORT + dsmif_extended_cfg_t const * p_extend = (dsmif_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; +#endif + + adc_channel_t channel = (adc_channel_t) ((uint32_t) reg_id & DSMIF_DATA_CHANNEL_MASK); + dsmif_current_data_t dsmif_data_type = + (dsmif_current_data_t) (((uint32_t) reg_id & DSMIF_DATA_TYPE_MASK) >> DSMIF_DATA_TYPE_SHIFT); + if (DSMIF_CURRENT_DATA == dsmif_data_type) + { + *p_data = (uint16_t) (p_instance_ctrl->p_reg->CH[channel].DSCDR); + } + else if (DSMIF_CURRENT_DATA_CAPTURE_A == dsmif_data_type) + { + *p_data = (uint16_t) (p_instance_ctrl->p_reg->CH[channel].DSCCDRA); + } + else if (DSMIF_CURRENT_DATA_CAPTURE_B == dsmif_data_type) + { + *p_data = (uint16_t) (p_instance_ctrl->p_reg->CH[channel].DSCCDRB); + } + +#if DSMIF_CFG_ERROR_DETECTION_SUPPORT + else if (DSMIF_OVERCURRENT_DATA == dsmif_data_type) + { + *p_data = (uint16_t) (p_instance_ctrl->p_reg->CH[channel].DSOCDR); + } + else if (DSMIF_OVERCURRENT2_CAPTURE_DATA >= dsmif_data_type) + { + /* There are three different overcurrent capture registers. Calculate the overcurrent capture register + * from the dsmif_data_type field. */ + uint32_t overcurrent_index = dsmif_data_type - DSMIF_OVERCURRENT0_CAPTURE_DATA; + *p_data = (uint16_t) (p_instance_ctrl->p_reg->CH[channel].DSCOCDR[overcurrent_index]); + } + else if (DSMIF_OVERCURRENT_SUM_CAPTURE_DATA == dsmif_data_type) + { + /* There is an overcurrent sum capture register for each channel. + * In the following modes, the channel is used to index the associated overcurrent sum capture data. + * - DSMIF_OVERCURRENT_SUM_ERROR_CHANNEL_0_2 + * - DSMIF_OVERCURRENT_SUM_ERROR_CHANNEL_0_1 + */ + uint32_t overcurrent_sum_index = (uint32_t) channel; + + /* + * If the overcurrent sum data is configured to any of the following modes, the data will be stored in the + * first overcurrent capture register. + * - DSMIF_OVERCURRENT_SUM_ERROR_CHANNEL_0 + * - DSMIF_OVERCURRENT_SUM_ERROR_CHANNEL_1 + * - DSMIF_OVERCURRENT_SUM_ERROR_CHANNEL_2 + */ + if (DSMIF_OVERCURRENT_SUM_ERROR_CHANNEL_0 <= p_extend->overcurrent_sum_error_channel) + { + overcurrent_sum_index = 0; + } + + *p_data = (uint16_t) (p_instance_ctrl->p_reg->DSSECDR[overcurrent_sum_index]); + } +#endif + else + { + return FSP_ERR_UNSUPPORTED; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures channel interrupts. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_irq_cfg Pointer to interrupt configuration structure + * + **********************************************************************************************************************/ +static void r_dsmif_irq_enable (dsmif_instance_ctrl_t * const p_instance_ctrl, + dsmif_interrupt_cfg_t const * const p_irq_cfg) +{ + /* Set the interrupt priorities. */ + if (p_irq_cfg->current_data_update_irq >= 0) + { + R_BSP_IrqCfgEnable(p_irq_cfg->current_data_update_irq, p_irq_cfg->current_data_update_ipl, p_instance_ctrl); + } + + if (p_irq_cfg->capture_data_a_irq >= 0) + { + R_BSP_IrqCfgEnable(p_irq_cfg->capture_data_a_irq, p_irq_cfg->capture_data_a_ipl, p_instance_ctrl); + } + + if (p_irq_cfg->capture_data_b_irq >= 0) + { + R_BSP_IrqCfgEnable(p_irq_cfg->capture_data_b_irq, p_irq_cfg->capture_data_b_ipl, p_instance_ctrl); + } +} + +/*******************************************************************************************************************//** + * Disables channel interrupts. + * + * @param[in] p_irq_cfg Pointer to interrupt configuration structure + **********************************************************************************************************************/ +static void r_dsmif_irq_disable (dsmif_interrupt_cfg_t const * const p_irq_cfg) +{ + if (p_irq_cfg->current_data_update_irq >= 0) + { + R_BSP_IrqDisable(p_irq_cfg->current_data_update_irq); + R_FSP_IsrContextSet(p_irq_cfg->current_data_update_irq, NULL); + } + + if (p_irq_cfg->capture_data_a_irq >= 0) + { + R_BSP_IrqDisable(p_irq_cfg->capture_data_a_irq); + R_FSP_IsrContextSet(p_irq_cfg->capture_data_a_irq, NULL); + } + + if (p_irq_cfg->capture_data_b_irq >= 0) + { + R_BSP_IrqDisable(p_irq_cfg->capture_data_b_irq); + R_FSP_IsrContextSet(p_irq_cfg->capture_data_b_irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Fill in the adc_callback_args_t, then call the user callback. + **********************************************************************************************************************/ +static void r_dsmif_call_callback (dsmif_instance_ctrl_t * p_instance_ctrl, adc_event_t event, adc_channel_t channel) +{ + adc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + adc_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_callback) + { + /* Store the event into the callback argument */ + p_args->event = event; + p_args->unit = p_instance_ctrl->p_cfg->unit; + p_args->channel = channel; + p_args->p_context = p_instance_ctrl->p_context; + p_instance_ctrl->p_callback(p_args); + } + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * DSMIFn Current data update interrupt handler. + **********************************************************************************************************************/ +void dsmif_cdupdn_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Determine the channel associated with this interrupt request. */ + uint32_t ielsr_offset = (uint32_t) ELC_EVENT_DSMIF0_CDUPD0 + + ((ELC_EVENT_DSMIF1_CDUPD0 - ELC_EVENT_DSMIF0_CDUPD0) * p_instance_ctrl->p_cfg->unit); + uint32_t channel = R_ICU->IELSR_b[irq].IELS - ielsr_offset; + + /* Clear the channel status flag. */ + p_instance_ctrl->p_reg->DSCSCR = 1 << channel; + + r_dsmif_call_callback(p_instance_ctrl, ADC_EVENT_CONVERSION_COMPLETE, (adc_channel_t) channel); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * DSMIFn Capture Data A Update interrupt handler. + **********************************************************************************************************************/ +void dsmif_cdaupdn_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Determine the channel associated with this interrupt request. */ + uint32_t ielsr_offset = (uint32_t) ELC_EVENT_DSMIF0_CDAUPD0 + + ((ELC_EVENT_DSMIF1_CDAUPD0 - ELC_EVENT_DSMIF0_CDAUPD0) * p_instance_ctrl->p_cfg->unit); + uint32_t channel = R_ICU->IELSR_b[irq].IELS - ielsr_offset; + + /* Clear the channel status flag. */ + p_instance_ctrl->p_reg->DSCSCR = 1U << (R_DSMIF0_DSCSCR_CLRCAUF_Pos + channel); + + r_dsmif_call_callback(p_instance_ctrl, ADC_EVENT_CAPTURE_A, (adc_channel_t) (ADC_CHANNEL_CAPTURE_A_MASK | channel)); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * DSMIFn Capture Data B Update interrupt handler. + **********************************************************************************************************************/ +void dsmif_cdbupdn_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Determine the channel associated with this interrupt request. */ + uint32_t ielsr_offset = (uint32_t) ELC_EVENT_DSMIF0_CDBUPD0 + + ((ELC_EVENT_DSMIF1_CDBUPD0 - ELC_EVENT_DSMIF0_CDBUPD0) * p_instance_ctrl->p_cfg->unit); + uint32_t channel = R_ICU->IELSR_b[irq].IELS - ielsr_offset; + + /* Clear the channel status flag. */ + p_instance_ctrl->p_reg->DSCSCR = 1U << (R_DSMIF0_DSCSCR_CLRCBUF_Pos + channel); + + r_dsmif_call_callback(p_instance_ctrl, ADC_EVENT_CAPTURE_B, (adc_channel_t) (ADC_CHANNEL_CAPTURE_B_MASK | channel)); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * DSMIFn Common Current data update interrupt handler. + **********************************************************************************************************************/ +void dsmif_cdupd_com_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Clear all data update flags. */ + p_instance_ctrl->p_reg->DSCSCR = (R_DSMIF0_DSCSCR_CLRDUF_Msk << 0) | + (R_DSMIF0_DSCSCR_CLRDUF_Msk << 1) | + (R_DSMIF0_DSCSCR_CLRDUF_Msk << 2); + + r_dsmif_call_callback(p_instance_ctrl, ADC_EVENT_CONVERSION_COMPLETE, (adc_channel_t) 0); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * DSMIFn Common Capture Data A Update interrupt handler. + **********************************************************************************************************************/ +void dsmif_cdaupd_com_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Clear all capture a flags. */ + p_instance_ctrl->p_reg->DSCSCR = (R_DSMIF0_DSCSCR_CLRCAUF_Msk << 0) | + (R_DSMIF0_DSCSCR_CLRCAUF_Msk << 1) | + (R_DSMIF0_DSCSCR_CLRCAUF_Msk << 2); + + r_dsmif_call_callback(p_instance_ctrl, ADC_EVENT_CAPTURE_A, (adc_channel_t) 0); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * DSMIFn Common Capture Data B Update interrupt handler. + **********************************************************************************************************************/ +void dsmif_cdbupd_com_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Clear all capture b flags. */ + p_instance_ctrl->p_reg->DSCSCR = (R_DSMIF0_DSCSCR_CLRCBUF_Msk << 0) | + (R_DSMIF0_DSCSCR_CLRCBUF_Msk << 1) | + (R_DSMIF0_DSCSCR_CLRCBUF_Msk << 2); + + r_dsmif_call_callback(p_instance_ctrl, ADC_EVENT_CAPTURE_B, (adc_channel_t) 0); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * DSMIFn Common Error interrupt handler. + **********************************************************************************************************************/ +void dsmif_err_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + dsmif_instance_ctrl_t * p_instance_ctrl = (dsmif_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + r_dsmif_call_callback(p_instance_ctrl, ADC_EVENT_CONVERSION_ERROR, (adc_channel_t) 0); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dtc/r_dtc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dtc/r_dtc.c new file mode 100644 index 0000000000..65790e3114 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_dtc/r_dtc.c @@ -0,0 +1,691 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_dtc.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Driver ID (DTC in ASCII), used to identify Data Transfer Controller (DTC) configuration */ +#define DTC_OPEN (0x44544300) + +/** Size of vector table is based on number of vectors defined in BSP. */ +#define DTC_VECTOR_TABLE_ENTRIES (BSP_ICU_VECTOR_NUM_ENTRIES) + +/** The size of transfer_info_t is defined in the Hardware Manual therefore it must be 16 bytes. */ +#define DTC_TRANSFER_INFO_SIZE (16U) + +/* Compiler specific macro to specify vector table section. */ +#ifndef DTC_CFG_VECTOR_TABLE_SECTION_NAME + #define DTC_SECTION_ATTRIBUTE + #ifndef SUPPRESS_WARNING_DTC_CFG_VECTOR_TABLE_SECTION_NAME + #warning "DTC vector table is aligned on 1K boundary. Automatic placing could lead to memory holes." + #endif +#else + #define DTC_SECTION_ATTRIBUTE BSP_PLACE_IN_SECTION(DTC_CFG_VECTOR_TABLE_SECTION_NAME) +#endif + +/* Used to generate a compiler error (divided by 0 error) if the assertion fails. This is used in place of "#error" + * for expressions that cannot be evaluated by the preprocessor like sizeof(). */ +#define DTC_COMPILE_TIME_ASSERT(e) ((void) sizeof(char[1 - 2 * !(e)])) + +/* Calculate the mask bits for byte alignment from the transfer_size_t. */ +#define DTC_PRV_MASK_ALIGN_N_BYTES(x) ((1U << (x)) - 1U) + +/* Counter Register A Lower Byte Mask */ +#define DTC_PRV_MASK_CRAL (0xFFU) + +/* Counter Register A Upper Byte Offset */ +#define DTC_PRV_OFFSET_CRAH (8U) + +/* Offset of in_progress bit in R_DTC->DTCSTS. */ +#define DTC_PRV_OFFSET_IN_PROGRESS (15U) + +/* DTC Control Register RRS Enable value. */ +#define DTC_PRV_RRS_ENABLE (0x18) + +/* DTC Control Register RRS Disable value. */ +#define DTC_PRV_RRS_DISABLE (0x08) + +/* DTC security attribution for the core */ +#if (1U == BSP_CFG_CPU_CORE) + #define DTC_PRV_DTCSAR_DTCSTSA (R_CPSCU->DTCSAR_b.DTCSTSA1) +#else + #define DTC_PRV_DTCSAR_DTCSTSA ((R_CPSCU->DTCSAR & R_CPSCU_DTCSAR_DTCSTSA_Msk) >> R_CPSCU_DTCSAR_DTCSTSA_Pos) +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static fsp_err_t r_dtc_prv_enable(dtc_instance_ctrl_t * p_ctrl); +static void r_dtc_state_initialize(void); +static void r_dtc_block_repeat_initialize(transfer_info_t * p_info); +static void r_dtc_set_info(dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_info); + +#if DTC_CFG_PARAM_CHECKING_ENABLE + #if BSP_CFG_ASSERT != 3 +static fsp_err_t r_dtc_length_assert(transfer_info_t * p_info); + + #endif +static fsp_err_t r_dtc_source_destination_parameter_check(transfer_info_t * p_info); + +#endif + +static void r_dtc_wait_for_transfer_complete(dtc_instance_ctrl_t * p_ctrl); +static void r_dtc_disable_transfer(const IRQn_Type irq); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static transfer_info_t * gp_dtc_vector_table[DTC_VECTOR_TABLE_ENTRIES] BSP_ALIGN_VARIABLE(1024) +DTC_SECTION_ATTRIBUTE; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** DTC implementation of transfer API. */ +const transfer_api_t g_transfer_on_dtc = +{ + .open = R_DTC_Open, + .reconfigure = R_DTC_Reconfigure, + .reset = R_DTC_Reset, + .infoGet = R_DTC_InfoGet, + .softwareStart = R_DTC_SoftwareStart, + .softwareStop = R_DTC_SoftwareStop, + .enable = R_DTC_Enable, + .disable = R_DTC_Disable, + .reload = R_DTC_Reload, + .callbackSet = R_DTC_CallbackSet, + .close = R_DTC_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup DTC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure the vector table if it hasn't been configured, enable the Module and copy the pointer to the transfer info + * into the DTC vector table. Implements @ref transfer_api_t::open. + * + * Example: + * @snippet r_dtc_example.c R_DTC_Open + * + * @retval FSP_SUCCESS Successful open. + * Transfer transfer info pointer copied to DTC Vector table. + * Module started. + * DTC vector table configured. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + * @retval FSP_ERR_ALREADY_OPEN The control structure is already opened. + * @retval FSP_ERR_IN_USE The index for this IRQ in the DTC vector table is already configured. + * @retval FSP_ERR_IRQ_BSP_DISABLED The IRQ associated with the activation source is not enabled in the BSP. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Open (transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg) +{ + /* Generate a compiler error if transfer_info_t is modified. */ + DTC_COMPILE_TIME_ASSERT(sizeof(transfer_info_t) == DTC_TRANSFER_INFO_SIZE); + + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open != DTC_OPEN, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); +#endif + + /* One time initialization for all DTC instances. */ + r_dtc_state_initialize(); + + /* Make sure the activation source is mapped in the ICU. */ + dtc_extended_cfg_t * p_dtc_cfg = (dtc_extended_cfg_t *) p_cfg->p_extend; + IRQn_Type irq = p_dtc_cfg->activation_source; + FSP_ERROR_RETURN(irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED); + + /* Make sure the activation source is not already being used by the DTC. */ + FSP_ERROR_RETURN(NULL == gp_dtc_vector_table[irq], FSP_ERR_IN_USE); + + /* irq is used to index the DTC vector table. */ + p_ctrl->irq = irq; + + /* Copy p_info into the DTC vector table. */ + if (p_cfg->p_info) + { +#if DTC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_dtc_length_assert(p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + r_dtc_set_info(p_ctrl, p_cfg->p_info); + } + + /* Mark driver as open by initializing it to "DTC" in its ASCII equivalent. */ + p_ctrl->open = DTC_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Copy pointer to transfer info into the DTC vector table and enable transfer in ICU. + * Implements @ref transfer_api_t::reconfigure. + * + * @retval FSP_SUCCESS Transfer is configured and will start when trigger occurs. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + * @retval FSP_ERR_NOT_ENABLED Transfer source address is NULL or is not aligned correctly. + * Transfer destination address is NULL or is not aligned correctly. + * + * @note p_info must persist until all transfers are completed. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Reconfigure (transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_info); + FSP_ASSERT(FSP_SUCCESS == r_dtc_length_assert(p_info)); +#endif + + /* Disable transfers on this activation source. */ + r_dtc_disable_transfer(p_ctrl->irq); + + /* Wait for current transfer to finish. */ + r_dtc_wait_for_transfer_complete(p_ctrl); + + /* Copy p_info into the DTC vector table. */ + r_dtc_set_info(p_ctrl, p_info); + + /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */ + /* Enable transfers on this activation source. */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_dtc_prv_enable(p_ctrl), FSP_ERR_NOT_ENABLED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reset transfer source, destination, and number of transfers. Implements @ref transfer_api_t::reset. + * + * @retval FSP_SUCCESS Transfer reset successfully (transfers are enabled). + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + * @retval FSP_ERR_NOT_ENABLED Transfer source address is NULL or is not aligned correctly. + * Transfer destination address is NULL or is not aligned correctly. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Reset (transfer_ctrl_t * const p_api_ctrl, + void const * volatile p_src, + void * volatile p_dest, + uint16_t const num_transfers) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); +#endif + + const IRQn_Type irq = p_ctrl->irq; + transfer_info_t * const gp_dtc_vector = gp_dtc_vector_table[irq]; + + /* Disable transfers on this activation source. */ + r_dtc_disable_transfer(irq); + + /* Wait for current transfer to finish. */ + r_dtc_wait_for_transfer_complete(p_ctrl); + + /* Disable read skip prior to modifying settings. It will be enabled later + * (See "Transfer Information Read Skip Function" in the DTC section of the relevant hardware manual). */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE; +#else + R_DTC->DTCCR = DTC_PRV_RRS_DISABLE; +#endif + + /* Reset transfer based on input parameters. */ + if (NULL != p_src) + { + gp_dtc_vector->p_src = p_src; + } + + if (NULL != p_dest) + { + gp_dtc_vector->p_dest = p_dest; + } + + if (TRANSFER_MODE_BLOCK == gp_dtc_vector->transfer_settings_word_b.mode) + { + gp_dtc_vector->num_blocks = num_transfers; + } + else if (TRANSFER_MODE_NORMAL == gp_dtc_vector->transfer_settings_word_b.mode) + { + gp_dtc_vector->length = num_transfers; + } + else /* TRANSFER_MODE_REPEAT */ + { + /* Do nothing. */ + } + + /* Enable read skip after all settings are written. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE; +#else + R_DTC->DTCCR = DTC_PRV_RRS_ENABLE; +#endif + + /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */ + /* Enable transfers on this activation source. */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_dtc_prv_enable(p_ctrl), FSP_ERR_NOT_ENABLED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported softwareStart function. Implements @ref transfer_api_t::softwareStart. + * + * @retval FSP_ERR_UNSUPPORTED DTC software start is not supported. + **********************************************************************************************************************/ +fsp_err_t R_DTC_SoftwareStart (transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode) +{ + /* This function isn't supported. It is defined only to implement a required function of transfer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(mode); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported softwareStop function. Implements @ref transfer_api_t::softwareStop. + * + * @retval FSP_ERR_UNSUPPORTED DTC software stop is not supported. + **********************************************************************************************************************/ +fsp_err_t R_DTC_SoftwareStop (transfer_ctrl_t * const p_api_ctrl) +{ + /* This function isn't supported. It is defined only to implement a required function of transfer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Enable transfers on this activation source. Implements @ref transfer_api_t::enable. + * + * Example: + * @snippet r_dtc_example.c R_DTC_Enable + * + * @retval FSP_SUCCESS Transfers will be triggered by the activation source + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Enable (transfer_ctrl_t * const p_api_ctrl) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); +#endif + + return r_dtc_prv_enable(p_ctrl); +} + +/*******************************************************************************************************************//** + * Disable transfer on this activation source. Implements @ref transfer_api_t::disable. + * + * @retval FSP_SUCCESS Transfers will not occur on activation events. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Disable (transfer_ctrl_t * const p_api_ctrl) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /* Disable transfer. */ + r_dtc_disable_transfer(p_ctrl->irq); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides information about this transfer. Implements @ref transfer_api_t::infoGet. + * + * @retval FSP_SUCCESS p_info updated with current instance information. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +fsp_err_t R_DTC_InfoGet (transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_properties); +#endif + + transfer_info_t * p_info = gp_dtc_vector_table[p_ctrl->irq]; + + p_properties->block_count_max = 0U; + p_properties->block_count_remaining = 0U; + + if (TRANSFER_MODE_NORMAL != p_info->transfer_settings_word_b.mode) + { + /* Repeat and Block Mode */ + + /* transfer_length_max is the same for Block and repeat mode. */ + p_properties->transfer_length_max = DTC_MAX_REPEAT_TRANSFER_LENGTH; + p_properties->transfer_length_remaining = p_info->length & DTC_PRV_MASK_CRAL; + + if (TRANSFER_MODE_BLOCK == p_info->transfer_settings_word_b.mode) + { + p_properties->block_count_max = DTC_MAX_BLOCK_COUNT; + p_properties->block_count_remaining = p_info->num_blocks; + } + } + else + { + p_properties->transfer_length_max = DTC_MAX_NORMAL_TRANSFER_LENGTH; + p_properties->transfer_length_remaining = p_info->length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * To update next transfer information without interruption during transfer. + * + * @retval FSP_ERR_UNSUPPORTED This feature is not supported. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Reload (transfer_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const num_transfers) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(num_transfers); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported callbackset function. Implements @ref transfer_api_t::callbackSet. + * + * @retval FSP_ERR_UNSUPPORTED DTC does not support direct callbacks. + **********************************************************************************************************************/ +fsp_err_t R_DTC_CallbackSet (transfer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(transfer_callback_args_t *), + void * const p_context, + transfer_callback_args_t * const p_callback_memory) +{ + /* This function isn't supported. It is defined only to implement a required function of transfer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_context); + FSP_PARAMETER_NOT_USED(p_callback_memory); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Disables DTC activation in the ICU, then clears transfer data from the DTC vector table. + * Implements @ref transfer_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Close (transfer_ctrl_t * const p_api_ctrl) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); +#endif + + const IRQn_Type irq = p_ctrl->irq; + + /* Clear DTC enable bit in ICU. */ + r_dtc_disable_transfer(irq); + + /* Clear pointer in vector table. */ + gp_dtc_vector_table[irq] = NULL; + + /* Mark instance as closed. */ + p_ctrl->open = 0U; + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup DTC) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Verify that the source and destination pointers are valid then enable the DTC. + * + * @retval FSP_SUCCESS Successfully enabled + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + **********************************************************************************************************************/ +static fsp_err_t r_dtc_prv_enable (dtc_instance_ctrl_t * p_ctrl) +{ +#if DTC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_dtc_source_destination_parameter_check(gp_dtc_vector_table[p_ctrl->irq]); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Enable transfers on this activation source. */ +#if BSP_FEATURE_ICU_HAS_IELSR + R_ICU->IELSR_b[p_ctrl->irq].DTCE = 1U; +#else + R_ICU->DTCENSET[(((uint32_t) p_ctrl->irq) >> 5UL)] = 1UL << ((uint32_t) p_ctrl->irq & (uint32_t) 0x1FUL); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * One time state initialization for all DTC instances. + **********************************************************************************************************************/ +static void r_dtc_state_initialize (void) +{ + /* Stores initialization state to skip initialization in ::R_DTC_Open after the first call. */ + static bool g_dtc_state_initialized = false; + + /* DTC requires a one time initialization. This will be handled only the first time this function + * is called. This initialization: + * -# Stores the register base addresses for DTC and ICU. + * -# Powers on the DTC block. + * -# Initializes the vector table to NULL pointers. + * -# Sets the vector table base address. + * -# Enables DTC transfers. */ + if (!g_dtc_state_initialized) + { + g_dtc_state_initialized = true; + + /** Power on DTC */ + R_BSP_MODULE_START(FSP_IP_DTC, 0); + + /* The DTC vector table must be cleared during initialization because it is located in + * its own section outside of the .BSS section which is cleared during startup. */ + memset(&gp_dtc_vector_table, 0U, DTC_VECTOR_TABLE_ENTRIES * sizeof(transfer_info_t *)); + + /* Set DTC vector table. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + R_DTC->DTCVBR_SEC = (uint32_t) gp_dtc_vector_table; +#else + R_DTC->DTCVBR = (uint32_t) gp_dtc_vector_table; +#endif + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD + if (1 == DTC_PRV_DTCSAR_DTCSTSA) + { + /* Enable the DTC Peripheral */ + R_DTC->DTCST = 1U; + } + +#else + + /* Enable the DTC Peripheral */ + R_DTC->DTCST = 1U; +#endif + } +} + +/*******************************************************************************************************************//** + * Configure the p_info state and write p_info to DTC vector table. + **********************************************************************************************************************/ +static void r_dtc_set_info (dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_info) +{ + /* Update internal variables. */ + r_dtc_block_repeat_initialize(p_info); + + /* Disable read skip prior to modifying settings. It will be enabled later + * (See "Transfer Information Read Skip Function" in the DTC section of the relevant hardware manual). */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE; +#else + R_DTC->DTCCR = DTC_PRV_RRS_DISABLE; +#endif + + /* Update the entry in the DTC Vector table. */ + gp_dtc_vector_table[p_ctrl->irq] = p_info; + + /* Enable read skip after all settings are written. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE; +#else + R_DTC->DTCCR = DTC_PRV_RRS_ENABLE; +#endif +} + +/*******************************************************************************************************************//** + * Configure the length setting for block and repeat mode. + **********************************************************************************************************************/ +static void r_dtc_block_repeat_initialize (transfer_info_t * p_info) +{ + uint32_t i = 0; + do + { + /* Update the CRA register to the desired settings */ + if (TRANSFER_MODE_NORMAL != p_info[i].transfer_settings_word_b.mode) + { + uint8_t CRAL = p_info[i].length & DTC_PRV_MASK_CRAL; + p_info[i].length = (uint16_t) ((CRAL << DTC_PRV_OFFSET_CRAH) | CRAL); + } + } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].transfer_settings_word_b.chain_mode); +} + +#if DTC_CFG_PARAM_CHECKING_ENABLE + + #if BSP_CFG_ASSERT != 3 + +/*******************************************************************************************************************//** + * Check to make sure that the length is valid for block and repeat mode. + * + * @retval FSP_SUCCESS Parameters are valid. + * @retval FSP_ERR_ASSERTION Invalid length for block or repeat mode. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + * + **********************************************************************************************************************/ +static fsp_err_t r_dtc_length_assert (transfer_info_t * p_info) +{ + uint32_t i = 0; + do + { + FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].transfer_settings_word_b.src_addr_mode, + FSP_ERR_UNSUPPORTED); + FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].transfer_settings_word_b.dest_addr_mode, + FSP_ERR_UNSUPPORTED); + + if (TRANSFER_MODE_NORMAL != p_info[i].transfer_settings_word_b.mode) + { + /* transfer_length_max is the same for Block and repeat mode. */ + FSP_ASSERT(p_info[i].length <= DTC_MAX_REPEAT_TRANSFER_LENGTH); + } + } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].transfer_settings_word_b.chain_mode); + + return FSP_SUCCESS; +} + + #endif + +/*******************************************************************************************************************//** + * Check that the source and destination are not NULL and that they are aligned correctly. + * + * @retval FSP_SUCCESS Parameters are valid. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + * + **********************************************************************************************************************/ +static fsp_err_t r_dtc_source_destination_parameter_check (transfer_info_t * p_info) +{ + uint32_t i = 0; + do + { + FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].transfer_settings_word_b.src_addr_mode, + FSP_ERR_UNSUPPORTED); + FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].transfer_settings_word_b.dest_addr_mode, + FSP_ERR_UNSUPPORTED); + FSP_ASSERT(NULL != p_info[i].p_src); + FSP_ASSERT(NULL != p_info[i].p_dest); + FSP_ASSERT(0U == + ((uint32_t) p_info[i].p_dest & DTC_PRV_MASK_ALIGN_N_BYTES(p_info[i].transfer_settings_word_b.size))); + FSP_ASSERT(0U == + ((uint32_t) p_info[i].p_src & DTC_PRV_MASK_ALIGN_N_BYTES(p_info[i].transfer_settings_word_b.size))); + } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].transfer_settings_word_b.chain_mode); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Wait for the current DTC transfer to complete. + **********************************************************************************************************************/ +static void r_dtc_wait_for_transfer_complete (dtc_instance_ctrl_t * p_ctrl) +{ + uint32_t in_progress = (1U << DTC_PRV_OFFSET_IN_PROGRESS) | (uint32_t) p_ctrl->irq; + + /* Wait for the DTCSTS.ACT flag to be clear if the current vector is the activation source.*/ + FSP_HARDWARE_REGISTER_WAIT((FSP_STYPE3_REG16_READ(R_DTC->DTCSTS, !DTC_PRV_DTCSAR_DTCSTSA) == in_progress), 0); +} + +/*******************************************************************************************************************//** + * Disable transfers on activation source. + **********************************************************************************************************************/ +static void r_dtc_disable_transfer (const IRQn_Type irq) +{ +#if BSP_FEATURE_ICU_HAS_IELSR + R_ICU->IELSR_b[((uint32_t) irq)].DTCE = 0U; +#else + R_ICU->DTCENCLR[(((uint32_t) irq) >> 5UL)] = 1UL << (((uint32_t) irq) & (uint32_t) 0x1FUL); +#endif +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_elc/r_elc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_elc/r_elc.c new file mode 100644 index 0000000000..0b7c4e27ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_elc/r_elc.c @@ -0,0 +1,370 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_elc.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "ELC" in ASCII, used to determine if the module is open */ +#define ELC_OPEN (0x00454C43U) +#define ELC_CLOSED (0x00000000U) + +#define ELC_ELCR_ELCON_DISABLE (0x00U) +#define ELC_ELCR_ELCON_ENABLE (0x80U) + +/* Steps necessary to unlock and write software event generation bits */ +#define ELC_ELSEGRN_STEP1 (0x00U) /* WI = 0, WE = 0, SEG = 0 */ +#define ELC_ELSEGRN_STEP2 (0x40U) /* WI = 0, WE = 1, SEG = 0 */ +#define ELC_ELSEGRN_STEP3 (0x41U) /* WI = 0, WE = 1, SEG = 1 */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +#if ELC_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_elc_common_parameter_checking(elc_instance_ctrl_t * p_instance_ctrl); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** ELC API structure. */ +const elc_api_t g_elc_on_elc = +{ + .open = R_ELC_Open, + .close = R_ELC_Close, + .softwareEventGenerate = R_ELC_SoftwareEventGenerate, + .linkSet = R_ELC_LinkSet, + .linkBreak = R_ELC_LinkBreak, + .enable = R_ELC_Enable, + .disable = R_ELC_Disable, +}; + +/*******************************************************************************************************************//** + * @addtogroup ELC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize all the links in the Event Link Controller. Implements @ref elc_api_t::open + * + * The configuration structure passed in to this function includes links for every event source included in the ELC + * and sets them all at once. To set or clear an individual link use R_ELC_LinkSet and R_ELC_LinkBreak respectively. + * + * Example: + * @snippet r_elc_example.c R_ELC_Open + * + * @retval FSP_SUCCESS Initialization was successful + * @retval FSP_ERR_ASSERTION p_ctrl or p_cfg was NULL + * @retval FSP_ERR_ALREADY_OPEN The module is currently open + * + **********************************************************************************************************************/ +fsp_err_t R_ELC_Open (elc_ctrl_t * const p_ctrl, elc_cfg_t const * const p_cfg) +{ + uint32_t i; + uint64_t i_shift = 1; + + elc_instance_ctrl_t * p_instance_ctrl = (elc_instance_ctrl_t *) p_ctrl; + +#if ELC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN(ELC_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Power on ELC */ + R_BSP_MODULE_START(FSP_IP_ELC, 0); + + /* Loop through all links and set or clear them in the ELC block */ + for (i = 0; i < ELC_PERIPHERAL_NUM; i++) + { + /* Check to ensure the MCU we are using actually has this event link option */ + if (BSP_ELC_PERIPHERAL_MASK & i_shift) + { + R_ELC->ELSR[i].HA = (uint16_t) p_cfg->link[i]; + } + + i_shift <<= 1; + } + + /* Set driver status to open */ + p_instance_ctrl->open = ELC_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Globally disable ELC linking. Implements @ref elc_api_t::close + * + * @retval FSP_SUCCESS The ELC was successfully disabled + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_ELC_Close (elc_ctrl_t * const p_ctrl) +{ + elc_instance_ctrl_t * p_instance_ctrl = (elc_instance_ctrl_t *) p_ctrl; + +#if ELC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_elc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Set state to closed */ + p_instance_ctrl->open = ELC_CLOSED; + + uint8_t volatile * p_elcr = &R_ELC->ELCR; + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + if (1 == R_ELC->ELCSARA_b.ELCR) + { + /* Access ELCR using the non-secure alias. */ + p_elcr = (uint8_t volatile *) ((uint32_t) p_elcr | BSP_FEATURE_TZ_NS_OFFSET); + } +#endif + + /* Globally disable the operation of the Event Link Controller */ + *p_elcr = ELC_ELCR_ELCON_DISABLE; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Generate a software event in the Event Link Controller. Implements @ref elc_api_t::softwareEventGenerate + * + * Example: + * @snippet r_elc_example.c R_ELC_SoftwareEventGenerate + * + * @retval FSP_SUCCESS Initialization was successful + * @retval FSP_ERR_ASSERTION Invalid event number or p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + **********************************************************************************************************************/ +fsp_err_t R_ELC_SoftwareEventGenerate (elc_ctrl_t * const p_ctrl, elc_software_event_t event_number) +{ +#if ELC_CFG_PARAM_CHECKING_ENABLE + elc_instance_ctrl_t * p_instance_ctrl = (elc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = r_elc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + FSP_PARAMETER_NOT_USED(p_ctrl); + + uint8_t volatile * p_elsegrn = &R_ELC->ELSEGR[event_number].BY; + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + + /* Access ELSEGR using the non-secure alias. */ + p_elsegrn = (uint8_t volatile *) ((uint32_t) p_elsegrn | BSP_FEATURE_TZ_NS_OFFSET); +#endif + + /* Set the ELSEGR bits in the correct order (see "Event Link Software Event Generation Register n + * (ELSEGRn) (n = 0, 1)" description in the ELC section of the relevant hardware manual). */ + + /* Step 1. enable the ELSEGR0 register for writing */ + *p_elsegrn = ELC_ELSEGRN_STEP1; + + /* Step 2. Enable the SEG bit for writing */ + *p_elsegrn = ELC_ELSEGRN_STEP2; + + /* Step 3. Set the SEG bit which causes the software event generation */ + *p_elsegrn = ELC_ELSEGRN_STEP3; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Create a single event link. Implements @ref elc_api_t::linkSet + * + * Example: + * @snippet r_elc_example.c R_ELC_LinkSet + * + * @retval FSP_SUCCESS Initialization was successful + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_ELC_LinkSet (elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal) +{ +#if ELC_CFG_PARAM_CHECKING_ENABLE + elc_instance_ctrl_t * p_instance_ctrl = (elc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = r_elc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Disable write protection to SAR registers */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Configure security attribution for ELSRn */ + /* Devices that only have ELCSARB */ + #if BSP_FEATURE_ELC_VERSION == 2 + R_ELC->ELCSARB &= (uint32_t) ~(1 << peripheral); + + /* Devices that have ELCSARB and ELCSARC */ + #elif BSP_FEATURE_ELC_VERSION == 1 + if (peripheral < 16) + { + R_ELC->ELCSARB &= (uint16_t) ~(1U << peripheral); + } + else + { + R_ELC->ELCSARC &= (uint16_t) ~(1U << (peripheral - 16U)); + } + #endif + + /* Restore write protection to SAR registers */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + + /* Set the event link register for the corresponding peripheral to the given signal */ + R_ELC->ELSR[(uint32_t) peripheral].HA = (uint16_t) signal; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Break an event link. Implements @ref elc_api_t::linkBreak + * + * @retval FSP_SUCCESS Event link broken + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_ELC_LinkBreak (elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral) +{ +#if ELC_CFG_PARAM_CHECKING_ENABLE + elc_instance_ctrl_t * p_instance_ctrl = (elc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = r_elc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Clear the corresponding peripheral event link register to break the link */ + R_ELC->ELSR[(uint32_t) peripheral].HA = ELC_EVENT_NONE; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable the operation of the Event Link Controller. Implements @ref elc_api_t::enable + * + * @retval FSP_SUCCESS ELC enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_ELC_Enable (elc_ctrl_t * const p_ctrl) +{ +#if ELC_CFG_PARAM_CHECKING_ENABLE + elc_instance_ctrl_t * p_instance_ctrl = (elc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = r_elc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + uint8_t volatile * p_elcr = &R_ELC->ELCR; + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + if (1 == R_ELC->ELCSARA_b.ELCR) + { + /* Access ELCR using the non-secure alias. */ + p_elcr = (uint8_t volatile *) ((uint32_t) p_elcr | BSP_FEATURE_TZ_NS_OFFSET); + } +#endif + + /* Globally enable ELC function */ + *p_elcr = ELC_ELCR_ELCON_ENABLE; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable the operation of the Event Link Controller. Implements @ref elc_api_t::disable + * + * @retval FSP_SUCCESS ELC disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_ELC_Disable (elc_ctrl_t * const p_ctrl) +{ +#if ELC_CFG_PARAM_CHECKING_ENABLE + elc_instance_ctrl_t * p_instance_ctrl = (elc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = r_elc_common_parameter_checking(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + uint8_t volatile * p_elcr = &R_ELC->ELCR; + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + if (1 == R_ELC->ELCSARA_b.ELCR) + { + /* Access ELCR using the non-secure alias. */ + p_elcr = (uint8_t volatile *) ((uint32_t) p_elcr | BSP_FEATURE_TZ_NS_OFFSET); + } +#endif + + /* Globally disable ELC function */ + *p_elcr = ELC_ELCR_ELCON_DISABLE; + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @} (end addtogroup ELC) + **********************************************************************************************************************/ + +#if ELC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Verifies the control structure is not NULL and the module is open. This reduces code size when the error logger is + * used. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * + * @retval FSP_SUCCESS No error detected. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +static fsp_err_t r_elc_common_parameter_checking (elc_instance_ctrl_t * p_instance_ctrl) +{ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ELC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + return FSP_SUCCESS; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether/r_ether.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether/r_ether.c new file mode 100644 index 0000000000..bb30b44a72 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether/r_ether.c @@ -0,0 +1,2078 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ +#include +#include "r_ether.h" +#include "r_ether_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ +#ifndef ETHER_ERROR_RETURN + + #define ETHER_ERROR_RETURN(a, err) FSP_ERROR_RETURN((a), (err)) +#endif + +#define ETHER_ETHERC_REG_SIZE (0x400UL) +#define ETHER_ETHERC_EDMAC_REG_SIZE (0x100UL) + +#define ETHER_ETHERC_INITIALIZATION_WAIT_CYCLE (0x64UL) + +/** "ETHE" in ASCII. Used to determine if the control block is open. */ +#define ETHER_OPEN (0x45544845U) + +/* Definition of the maximum / minimum number of data that can be sent at one time in the Ethernet */ +#define ETHER_MAXIMUM_FRAME_SIZE (1514U) /* Maximum number of transmitted data */ +#define ETHER_MINIMUM_FRAME_SIZE (60U) /* Minimum number of transmitted data */ + +/* Definition of the maximum padding offset */ +#define ETHER_MAXIMUM_PADDING_OFFSET (63U) + +/* Bit definition of Ethernet interrupt factor*/ +#define ETHER_ETHERC_INTERRUPT_FACTOR_ALL (0x00000037UL) + +#define ETHER_ETHERC_INTERRUPT_FACTOR_LCHNG (1UL << 2) +#define ETHER_ETHERC_INTERRUPT_FACTOR_MPD (1UL << 1) + +#define ETHER_EDMAC_INTERRUPT_FACTOR_ALL (0x47FF0F9FUL) + +#define ETHER_EDMAC_INTERRUPT_FACTOR_RFCOF (1UL << 24) +#define ETHER_EDMAC_INTERRUPT_FACTOR_ECI (1UL << 22) +#define ETHER_EDMAC_INTERRUPT_FACTOR_TC (1UL << 21) +#define ETHER_EDMAC_INTERRUPT_FACTOR_FR (1UL << 18) +#define ETHER_EDMAC_INTERRUPT_FACTOR_RDE (1UL << 17) +#define ETHER_EDMAC_INTERRUPT_FACTOR_RFOF (1UL << 16) + +/* Bit definition of Ethernet interrupt enable */ +#define ETHER_ETHERC_INTERRUPT_ENABLE_LCHNG (1UL << 2) +#define ETHER_ETHERC_INTERRUPT_ENABLE_MPD (1UL << 1) + +/* Bit definitions of status member of DescriptorS */ + +#define ETHER_TD0_TACT (0x80000000UL) +#define ETHER_TD0_TDLE (0x40000000UL) +#define ETHER_TD0_TFP1 (0x20000000UL) +#define ETHER_TD0_TFP0 (0x10000000UL) +#define ETHER_TD0_TFE (0x08000000UL) + +#define ETHER_TD0_TWBI (0x04000000UL) +#define ETHER_TD0_TFS8_TAD (0x00000100UL) +#define ETHER_TD0_TFS3_CND (0x00000008UL) +#define ETHER_TD0_TFS2_DLC (0x00000004UL) +#define ETHER_TD0_TFS1_CD (0x00000002UL) +#define ETHER_TD0_TFS0_TRO (0x00000001UL) + +#define ETHER_RD0_RACT (0x80000000UL) +#define ETHER_RD0_RDLE (0x40000000UL) +#define ETHER_RD0_RFP1 (0x20000000UL) +#define ETHER_RD0_RFP0 (0x10000000UL) +#define ETHER_RD0_RFE (0x08000000UL) + +#define ETHER_RD0_RFS9_RFOVER (0x00000200UL) +#define ETHER_RD0_RFS8_RAD (0x00000100UL) +#define ETHER_RD0_RFS7_RMAF (0x00000080UL) +#define ETHER_RD0_RFS4_RRF (0x00000010UL) +#define ETHER_RD0_RFS3_RTLF (0x00000008UL) +#define ETHER_RD0_RFS2_RTSF (0x00000004UL) +#define ETHER_RD0_RFS1_PRE (0x00000002UL) +#define ETHER_RD0_RFS0_CERF (0x00000001UL) + +/* Macro definitions of ETHERC/EDMAC configurations */ +#define ETHER_ETHERC_ECMR_MODE_CLEAR (0x00000000UL) +#define ETHER_ETHERC_RFLR_DEFAULT_VALUE (1518U) +#define ETHER_ETHERC_IPGR_DEFAULT_VALUE (0x00000014UL) +#define ETHER_ETHERC_APR_MAXIMUM_VALUE (0x0000FFFFUL) +#define ETHER_ETHERC_FCFTR_MINIMUM_VALUE (0x00000000UL) + +#define ETHER_EDMAC_TRSCER_MULTICAST_DISABLE (0x00000000UL) +#define ETHER_EDMAC_TRSCER_MULTICAST_ENABLE (0x00000080UL) +#define ETHER_EDMAC_RMCR_MULTIPLE_FRAMES_ENABLE (0x00000001UL) +#define ETHER_EDMAC_TFTR_STORE_AND_FORWARD_MODE (0x00000000UL) + +/* Macro definitions of EDMAC requests */ +#define ETHER_EDMAC_EDRRR_RECEIVE_REQUEST (0x00000001UL) +#define ETHER_EDMAC_EDTRR_TRANSMIT_REQUEST (0x00000001UL) + +/* Number of entries in PAUSE resolution table */ +#define ETHER_PAUSE_TABLE_ENTRIES (8) + +/* Local device and link partner PAUSE settings */ +#define ETHER_PAUSE_XMIT_OFF (0) /* The pause frame transmission is prohibited. */ +#define ETHER_PAUSE_RECV_OFF (0) /* The pause frame reception is prohibited. */ +#define ETHER_PAUSE_XMIT_ON (1) /* The pause frame transmission is permitted. */ +#define ETHER_PAUSE_RECV_ON (1) /* The pause frame reception is permitted. */ + +/* Macro definition for buffer alignment adjustment */ +#define ETHER_BUFFER_32BYTE_ALIGNMENT_MASK (0x1FUL) /* Mask for checking whether or not 32-bit alignment. */ + +/* PAUSE link mask and shift values */ + +/* + * The mask value and shift value which are for that shift the bits form a line and + * for comparing the bit information of PAUSE function which support the local device and + * Link partner with the assorted table(pause_resolution) which enable or disable the PAUSE frame. + */ +#define ETHER_LINK_RESOLUTION_ABILITY_MASK (3) +#define ETHER_LINK_RESOLUTION_LOCAL_ABILITY_BITSHIFT (2) + +/* Etherc mode */ +#define ETHER_NO_USE_MAGIC_PACKET_DETECT (0) +#define ETHER_USE_MAGIC_PACKET_DETECT (1) + +/* ETHER_NO_DATA is the return value that indicates that no received data. */ +#define ETHER_NO_DATA (0) + +/* PAUSE link mask and shift values */ + +#define ETHER_NO_DATA (0) + +/* Event mask for EESR register. */ +#define ETHER_EESR_ERR_GLOBAL_MASK (ETHER_EESR_EVENT_MASK_CERF | ETHER_EESR_EVENT_MASK_PRE | \ + ETHER_EESR_EVENT_MASK_RTSF | ETHER_EESR_EVENT_MASK_RTLF | \ + ETHER_EESR_EVENT_MASK_RRF | ETHER_EESR_EVENT_MASK_RMAF | \ + ETHER_EESR_EVENT_MASK_TRO | ETHER_EESR_EVENT_MASK_CD | \ + ETHER_EESR_EVENT_MASK_DLC | ETHER_EESR_EVENT_MASK_CND | \ + ETHER_EESR_EVENT_MASK_ADE | ETHER_EESR_EVENT_MASK_RFCOF | \ + ETHER_EESR_EVENT_MASK_RABT | ETHER_EESR_EVENT_MASK_TWB) +#define ETHER_EESR_RX_COMPLETE_MASK (ETHER_EESR_EVENT_MASK_FR) +#define ETHER_EESR_RX_MESSAGE_LOST_MASK (ETHER_EESR_EVENT_MASK_RFOF | ETHER_EESR_EVENT_MASK_RDE) +#define ETHER_EESR_TX_ABORTED_MASK (ETHER_EESR_EVENT_MASK_TABT) +#define ETHER_EESR_TX_BUFFER_EMPTY_MASK (ETHER_EESR_EVENT_MASK_TFUF | ETHER_EESR_EVENT_MASK_TDE) +#define ETHER_EESR_TX_COMPLETE_MASK (ETHER_EESR_EVENT_MASK_TC) + +/* Event mask for ECSR register. */ +#define ETHER_ECSR_ERR_GLOBAL_MASK (ETHER_ECSR_EVENT_MASK_ICD) +#define ETHER_ECSR_WAKEON_LAN_MASK (ETHER_ECSR_EVENT_MASK_MPD) + +#define ETHER_EESR_EVENT_NUM (6) +#define ETHER_ECSR_EVENT_NUM (2) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * ether_prv_ns_callback)(ether_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile ether_prv_ns_callback)(ether_callback_args_t * p_args); +#endif + +typedef struct st_ether_event_mask +{ + ether_event_t event; // Event code which is passed to user callback + uint32_t mask; // Mask to determine whether to call callback +} ether_event_mask_t; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + ***********************************************************************************************************************/ +void ether_eint_isr(void); + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) +static fsp_err_t ether_open_param_check(ether_instance_ctrl_t const * const p_instance_ctrl, + ether_cfg_t const * const p_cfg); + +#endif + +static void ether_enable_icu(ether_instance_ctrl_t * const p_instance_ctrl); +static void ether_disable_icu(ether_instance_ctrl_t * const p_instance_ctrl); +static void ether_reset_mac(R_ETHERC_EDMAC_Type * const p_reg); +static void ether_init_descriptors(ether_instance_ctrl_t * const p_instance_ctrl); +static void ether_init_buffers(ether_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ether_buffer_get(ether_instance_ctrl_t * const p_instance_ctrl, + void ** const p_buffer, + uint32_t * p_buffer_size); +static void ether_config_ethernet(ether_instance_ctrl_t const * const p_instance_ctrl, const uint8_t mode); +static void ether_pause_resolution(uint32_t const local_ability, + uint32_t const partner_ability, + uint32_t * ptx_pause, + uint32_t * prx_pause); +static void ether_configure_mac(ether_instance_ctrl_t * const p_instance_ctrl, + const uint8_t mac_addr[], + const uint8_t mode); +static fsp_err_t ether_do_link(ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode); +static fsp_err_t ether_link_status_check(ether_instance_ctrl_t const * const p_instance_ctrl); +static uint8_t ether_check_magic_packet_detection_bit(ether_instance_ctrl_t const * const p_instance_ctrl); +static void ether_configure_padding(ether_instance_ctrl_t * const p_instance_ctrl); +static void ether_call_callback(ether_instance_ctrl_t * p_instance_ctrl, ether_callback_args_t * p_callback_args); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +#if defined(__GNUC__) + +/* This structure is affected by warnings from a GCC compiler bug. This pragma suppresses the warnings in this + * structure only.*/ + + #pragma GCC diagnostic ignored "-Wmissing-field-initializers" +#endif + +/** ETHER HAL API mapping for Ethernet Controller interface. */ +const ether_api_t g_ether_on_ether = +{ + .open = R_ETHER_Open, + .close = R_ETHER_Close, + .read = R_ETHER_Read, + .bufferRelease = R_ETHER_BufferRelease, + .rxBufferUpdate = R_ETHER_RxBufferUpdate, + .write = R_ETHER_Write, + .linkProcess = R_ETHER_LinkProcess, + .wakeOnLANEnable = R_ETHER_WakeOnLANEnable, + .txStatusGet = R_ETHER_TxStatusGet, + .callbackSet = R_ETHER_CallbackSet, +}; + +/* + * PAUSE Resolution as documented in IEEE 802.3-2008_section2 Annex + * 28B, Table 28B-3. The following table codify logic that + * determines how the PAUSE is configured for local transmitter + * and receiver and partner transmitter and receiver. + */ +static const ether_pause_resolution_t pause_resolution[ETHER_PAUSE_TABLE_ENTRIES] = +{ + {ETHER_PAUSE_MASKC, ETHER_PAUSE_VAL0, ETHER_PAUSE_XMIT_OFF, ETHER_PAUSE_RECV_OFF }, + {ETHER_PAUSE_MASKE, ETHER_PAUSE_VAL4, ETHER_PAUSE_XMIT_OFF, ETHER_PAUSE_RECV_OFF }, + {ETHER_PAUSE_MASKF, ETHER_PAUSE_VAL6, ETHER_PAUSE_XMIT_OFF, ETHER_PAUSE_RECV_OFF }, + {ETHER_PAUSE_MASKF, ETHER_PAUSE_VAL7, ETHER_PAUSE_XMIT_ON, ETHER_PAUSE_RECV_OFF }, + {ETHER_PAUSE_MASKE, ETHER_PAUSE_VAL8, ETHER_PAUSE_XMIT_OFF, ETHER_PAUSE_RECV_OFF }, + {ETHER_PAUSE_MASKA, ETHER_PAUSE_VALA, ETHER_PAUSE_XMIT_ON, ETHER_PAUSE_RECV_ON }, + {ETHER_PAUSE_MASKF, ETHER_PAUSE_VALC, ETHER_PAUSE_XMIT_OFF, ETHER_PAUSE_RECV_OFF }, + {ETHER_PAUSE_MASKF, ETHER_PAUSE_VALD, ETHER_PAUSE_XMIT_OFF, ETHER_PAUSE_RECV_ON } +}; +static const ether_event_mask_t ether_eesr_event_mask[ETHER_EESR_EVENT_NUM] = +{ + {.event = ETHER_EVENT_RX_COMPLETE, .mask = ETHER_EESR_RX_COMPLETE_MASK }, + {.event = ETHER_EVENT_RX_MESSAGE_LOST, .mask = ETHER_EESR_RX_MESSAGE_LOST_MASK}, + {.event = ETHER_EVENT_TX_COMPLETE, .mask = ETHER_EESR_TX_COMPLETE_MASK }, + {.event = ETHER_EVENT_TX_BUFFER_EMPTY, .mask = ETHER_EESR_TX_BUFFER_EMPTY_MASK}, + {.event = ETHER_EVENT_TX_ABORTED, .mask = ETHER_EESR_TX_ABORTED_MASK }, + {.event = ETHER_EVENT_ERR_GLOBAL, .mask = ETHER_EESR_ERR_GLOBAL_MASK }, +}; + +static const ether_event_mask_t ether_ecsr_event_mask[ETHER_ECSR_EVENT_NUM] = +{ + {.event = ETHER_EVENT_WAKEON_LAN, .mask = ETHER_ECSR_WAKEON_LAN_MASK}, + {.event = ETHER_EVENT_ERR_GLOBAL, .mask = ETHER_EESR_ERR_GLOBAL_MASK}, +}; + +/*******************************************************************************************************************//** + * @addtogroup ETHER + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/********************************************************************************************************************//** + * @brief After ETHERC, EDMAC and PHY-LSI are reset in software, an auto negotiation of PHY-LSI is begun. + * Afterwards, the link signal change interrupt is permitted. Implements @ref ether_api_t::open. + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block or configuration structure is NULL. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION Initialization of PHY-LSI failed. + * @retval FSP_ERR_INVALID_CHANNEL Invalid channel number is given. + * @retval FSP_ERR_INVALID_POINTER Pointer to extend config structure or MAC address is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Interrupt is not enabled. + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK Initialization of PHY-LSI failed. + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + ether_extended_cfg_t * p_ether_extended_cfg; + R_ETHERC0_Type * p_reg_etherc; + R_ETHERC_EDMAC_Type * p_reg_edmac; + + fsp_err_t phy_ret; + +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + + /** Check parameters. */ + err = ether_open_param_check(p_instance_ctrl, p_cfg); /** check arguments */ + ETHER_ERROR_RETURN((FSP_SUCCESS == err), err); +#endif + ETHER_ERROR_RETURN((ETHER_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN); + + p_ether_extended_cfg = (ether_extended_cfg_t *) p_cfg->p_extend; + + /** Make sure this channel exists. */ + p_instance_ctrl->p_reg_etherc = ((R_ETHERC0_Type *) (R_ETHERC0_BASE + (ETHER_ETHERC_REG_SIZE * p_cfg->channel))); + p_instance_ctrl->p_reg_edmac = + ((R_ETHERC_EDMAC_Type *) (R_ETHERC_EDMAC_BASE + (ETHER_ETHERC_EDMAC_REG_SIZE * p_cfg->channel))); + + p_reg_etherc = p_instance_ctrl->p_reg_etherc; + p_reg_edmac = p_instance_ctrl->p_reg_edmac; + + /* Initialize configuration of Ethernet module. */ + p_instance_ctrl->p_ether_cfg = p_cfg; + + /* Initialize the flags */ + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + p_instance_ctrl->magic_packet = ETHER_MAGIC_PACKET_NOT_DETECTED; + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_DOWN; + + /* Initialize the transmit and receive descriptor */ + memset(p_ether_extended_cfg->p_rx_descriptors, + 0x00, + sizeof(ether_instance_descriptor_t) * + p_instance_ctrl->p_ether_cfg->num_rx_descriptors); + memset(p_ether_extended_cfg->p_tx_descriptors, + 0x00, + sizeof(ether_instance_descriptor_t) * + p_instance_ctrl->p_ether_cfg->num_tx_descriptors); + + /* Initialize the Ethernet buffer */ + ether_init_buffers(p_instance_ctrl); + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + R_BSP_MODULE_START(FSP_IP_ETHER, p_instance_ctrl->p_ether_cfg->channel); + + /* Software reset */ + ether_reset_mac(p_instance_ctrl->p_reg_edmac); + + /* Setting the padding function */ + ether_configure_padding(p_instance_ctrl); + + /* Software reset the PHY */ + phy_ret = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->open( + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl, + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_cfg); + +#if !ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC + + /* Initialize the PHY */ + if (FSP_SUCCESS == phy_ret) + { + phy_ret = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->chipInit( + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl, + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_cfg); + } +#endif + + if (FSP_SUCCESS == phy_ret) + { + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->startAutoNegotiate( + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl); + + /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ + p_reg_etherc->ECSR = ETHER_ETHERC_INTERRUPT_FACTOR_ALL; + + /* Clear all EDMAC status bits */ + p_reg_edmac->EESR = ETHER_EDMAC_INTERRUPT_FACTOR_ALL; + +#if (ETHER_CFG_USE_LINKSTA == 1) + + /* Enable interrupts of interest only. */ + p_reg_etherc->ECSIPR_b.LCHNGIP = 1; +#endif + + p_reg_edmac->EESIPR_b.ECIIP = 1; + + /* Set Ethernet interrupt level and enable */ + ether_enable_icu(p_instance_ctrl); + + p_instance_ctrl->open = ETHER_OPEN; + + err = FSP_SUCCESS; + } + else + { + if (FSP_ERR_ETHER_PHY_ERROR_LINK == phy_ret) + { + err = FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION; + } + else + { + err = phy_ret; + } + } + + return err; +} /* End of function R_ETHER_Open() */ + +/********************************************************************************************************************//** + * @brief Disables interrupts. Removes power and releases hardware lock. Implements @ref ether_api_t::close. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_Close (ether_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + R_ETHERC0_Type * p_reg_etherc; + R_ETHERC_EDMAC_Type * p_reg_edmac; + +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + + /* Disable Ethernet interrupt. */ + ether_disable_icu(p_instance_ctrl); + + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->close( + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl); + + p_reg_etherc->ECSIPR_b.LCHNGIP = 0; + p_reg_edmac->EESIPR_b.ECIIP = 0; + + /* Disable TE and RE */ + p_reg_etherc->ECMR = ETHER_ETHERC_ECMR_MODE_CLEAR; + + /* Initialize the flags */ + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + p_instance_ctrl->magic_packet = ETHER_MAGIC_PACKET_NOT_DETECTED; + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; +#if (ETHER_CFG_USE_LINKSTA == 0) + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_DOWN; +#endif + + /** Remove power to the channel. */ + R_BSP_MODULE_STOP(FSP_IP_ETHER, p_instance_ctrl->p_ether_cfg->channel); + + /** Clear configure block parameters. */ + p_instance_ctrl->p_ether_cfg = NULL; + + /** Mark the channel not open so other APIs cannot use it. */ + p_instance_ctrl->open = 0U; + + return err; +} /* End of function R_ETHER_Close() */ + +/********************************************************************************************************************//** + * @brief Move to the next buffer in the circular receive buffer list. Implements @ref ether_api_t::bufferRelease. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation is not completed, and reception is not enabled. + * @retval FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE As a Magic Packet is being detected, transmission and reception is + * not enabled. + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_BufferRelease (ether_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + R_ETHERC_EDMAC_Type * p_reg_edmac; + + uint32_t status; + + /* Check argument */ +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* When the Link up processing is not completed, return error */ + ETHER_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, + FSP_ERR_ETHER_ERROR_LINK); + + /* In case of detection mode of magic packet, return error. */ + ETHER_ERROR_RETURN(0 == ether_check_magic_packet_detection_bit(p_instance_ctrl), + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE); + + /* When receive data exists */ + if (ETHER_RD0_RACT != (p_instance_ctrl->p_rx_descriptor->status & ETHER_RD0_RACT)) + { + /* Reset current descriptor */ + status = ETHER_RD0_RFP1; + status |= ETHER_RD0_RFP0; + status |= ETHER_RD0_RFE; + status |= ETHER_RD0_RFS9_RFOVER; + status |= ETHER_RD0_RFS8_RAD; + status |= ETHER_RD0_RFS7_RMAF; + status |= ETHER_RD0_RFS4_RRF; + status |= ETHER_RD0_RFS3_RTLF; + status |= ETHER_RD0_RFS2_RTSF; + status |= ETHER_RD0_RFS1_PRE; + status |= ETHER_RD0_RFS0_CERF; + + p_instance_ctrl->p_rx_descriptor->status &= (~status); + + /* Enable current descriptor */ + p_instance_ctrl->p_rx_descriptor->status |= ETHER_RD0_RACT; + + /* Move to next descriptor */ + p_instance_ctrl->p_rx_descriptor = p_instance_ctrl->p_rx_descriptor->p_next; + } + + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + + if (ETHER_EDMAC_EDRRR_RECEIVE_REQUEST != p_reg_edmac->EDRRR) + { + /* Restart if stopped */ + p_reg_edmac->EDRRR = ETHER_EDMAC_EDRRR_RECEIVE_REQUEST; + } + + err = FSP_SUCCESS; + + return err; +} /* End of function R_ETHER_BufferRelease() */ + +/********************************************************************************************************************//** + * @brief Change the buffer pointer of the current rx buffer descriptor. Implements @ref ether_api_t::rxBufferUpdate. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION A pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER The pointer of buffer is NULL or not aligned on a 32-bit boundary. + * @retval FSP_ERR_INVALID_MODE Driver is configured to non zero copy mode. + * @retval FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE All descriptor is active. + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_RxBufferUpdate (ether_ctrl_t * const p_ctrl, void * const p_buffer) +{ + fsp_err_t err = FSP_SUCCESS; + R_ETHERC_EDMAC_Type * p_reg_edmac; + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + uint32_t status; + + /* Check argument */ +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHER_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER); + ETHER_ERROR_RETURN(0 == ((uint32_t) p_buffer & (uint32_t) ETHER_BUFFER_32BYTE_ALIGNMENT_MASK), + FSP_ERR_INVALID_POINTER); + ETHER_ERROR_RETURN(ETHER_ZEROCOPY_ENABLE == p_instance_ctrl->p_ether_cfg->zerocopy, FSP_ERR_INVALID_MODE); +#endif + + if (ETHER_RD0_RACT != (p_instance_ctrl->p_rx_descriptor->status & ETHER_RD0_RACT)) + { + p_instance_ctrl->p_rx_descriptor->p_buffer = p_buffer; + + /* Reset current descriptor */ + status = ETHER_RD0_RFP1; + status |= ETHER_RD0_RFP0; + status |= ETHER_RD0_RFE; + status |= ETHER_RD0_RFS9_RFOVER; + status |= ETHER_RD0_RFS8_RAD; + status |= ETHER_RD0_RFS7_RMAF; + status |= ETHER_RD0_RFS4_RRF; + status |= ETHER_RD0_RFS3_RTLF; + status |= ETHER_RD0_RFS2_RTSF; + status |= ETHER_RD0_RFS1_PRE; + status |= ETHER_RD0_RFS0_CERF; + + p_instance_ctrl->p_rx_descriptor->status &= (~status); + + /* Enable current descriptor */ + p_instance_ctrl->p_rx_descriptor->status |= ETHER_RD0_RACT; + + /* Move to next descriptor */ + p_instance_ctrl->p_rx_descriptor = p_instance_ctrl->p_rx_descriptor->p_next; + + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + + if (ETHER_EDMAC_EDRRR_RECEIVE_REQUEST != p_reg_edmac->EDRRR) + { + /* Restart if stopped */ + p_reg_edmac->EDRRR = ETHER_EDMAC_EDRRR_RECEIVE_REQUEST; + } + } + else + { + err = FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE; + } + + return err; +} + +/********************************************************************************************************************//** + * @brief The Link up processing, the Link down processing, and the magic packet detection processing are executed. + * Implements @ref ether_api_t::linkProcess. + * + * @retval FSP_SUCCESS Link is up. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_LINK Link is down. + * @retval FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION When reopening the PHY interface initialization of the PHY-LSI failed. + * @retval FSP_ERR_ALREADY_OPEN When reopening the PHY interface it was already opened. + * @retval FSP_ERR_INVALID_CHANNEL When reopening the PHY interface an invalid channel was passed. + * @retval FSP_ERR_INVALID_POINTER When reopening the PHY interface the MAC address pointer was NULL. + * @retval FSP_ERR_INVALID_ARGUMENT When reopening the PHY interface the interrupt was not enabled. + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK Initialization of the PHY-LSI failed. + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_LinkProcess (ether_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + R_ETHERC0_Type * p_reg_etherc; + + ether_callback_args_t callback_arg; + ether_cfg_t const * p_ether_cfg; + volatile ether_previous_link_status_t previous_link_status; + ether_extended_cfg_t * p_ether_extended_cfg; + +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + p_ether_extended_cfg = (ether_extended_cfg_t *) p_instance_ctrl->p_ether_cfg->p_extend; + + /* When the magic packet is detected. */ + if (ETHER_MAGIC_PACKET_DETECTED == p_instance_ctrl->magic_packet) + { + p_instance_ctrl->magic_packet = ETHER_MAGIC_PACKET_NOT_DETECTED; + + /* If a callback is provided, then call it with callback argument. */ + if (NULL != p_instance_ctrl->p_callback) + { + callback_arg.channel = p_instance_ctrl->p_ether_cfg->channel; + callback_arg.event = ETHER_EVENT_WAKEON_LAN; + callback_arg.status_ecsr = 0; + callback_arg.status_eesr = 0; + callback_arg.p_context = p_instance_ctrl->p_ether_cfg->p_context; + ether_call_callback(p_instance_ctrl, &callback_arg); + } + + /* + * After the close function is called, the open function is called + * to have to set ETHERC to a usual operational mode + * to usually communicate after magic packet is detected. + *//* back up previous_link_status */ + previous_link_status = p_instance_ctrl->previous_link_status; + + p_ether_cfg = p_instance_ctrl->p_ether_cfg; + + err = R_ETHER_Close((ether_ctrl_t *) p_instance_ctrl); + ETHER_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = R_ETHER_Open((ether_ctrl_t *) p_instance_ctrl, (ether_cfg_t *) p_ether_cfg); + ETHER_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* restore previous_link_status */ + p_instance_ctrl->previous_link_status = previous_link_status; + } + +#if (ETHER_CFG_USE_LINKSTA == 0) + err = ether_link_status_check(p_instance_ctrl); + + /* The state of the link status in PHY-LSI is confirmed and Link Up/Down is judged. */ + if (FSP_SUCCESS == err) + { + /* When becoming Link up */ + if (ETHER_PREVIOUS_LINK_STATUS_DOWN == p_instance_ctrl->previous_link_status) + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_UP; + + /* Update Link status */ + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_UP; + } + } + else + { + /* When becoming Link down */ + if (ETHER_PREVIOUS_LINK_STATUS_UP == p_instance_ctrl->previous_link_status) + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_DOWN; + + /* Update Link status */ + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_DOWN; + } + } +#endif + + /* When the link is up */ + if (ETHER_LINK_CHANGE_LINK_UP == p_instance_ctrl->link_change) + { +#if (ETHER_CFG_USE_LINKSTA == 1) + + /* + * The Link Up/Down is confirmed by the Link Status bit of PHY register1, + * because the LINK signal of PHY-LSI is used for LED indicator, and + * isn't used for notifing the Link Up/Down to external device. + */ + err = ether_link_status_check(p_instance_ctrl); + + if (FSP_SUCCESS == err) + { +#endif + + /* + * The status of the LINK signal became "link-up" even if PHY-LSI did not detect "link-up" + * after a reset. To avoid this wrong detection, processing in R_ETHER_LinkProcess has been modified to + * clear the flag after link-up is confirmed in R_ETHER_CheckLink_ZC. + */ +#if (ETHER_CFG_USE_LINKSTA == 1) + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_DOWN; +#elif (ETHER_CFG_USE_LINKSTA == 0) + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; +#endif + + /* Initialize the transmit and receive descriptor */ + memset(p_ether_extended_cfg->p_rx_descriptors, + 0x00, + sizeof(ether_instance_descriptor_t) * p_instance_ctrl->p_ether_cfg->num_rx_descriptors); + memset(p_ether_extended_cfg->p_tx_descriptors, + 0x00, + sizeof(ether_instance_descriptor_t) * p_instance_ctrl->p_ether_cfg->num_tx_descriptors); + + /* Initialize the Ethernet buffer */ + ether_init_buffers(p_instance_ctrl); + + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_UP; + + /* + * ETHERC and EDMAC are set after ETHERC and EDMAC are reset in software + * and sending and receiving is permitted. + */ + ether_configure_mac(p_instance_ctrl, + p_instance_ctrl->p_ether_cfg->p_mac_address, + ETHER_NO_USE_MAGIC_PACKET_DETECT); + err = ether_do_link(p_instance_ctrl, ETHER_NO_USE_MAGIC_PACKET_DETECT); + + if (FSP_SUCCESS == err) + { + /* If a callback is provided, then call it with callback argument. */ + if (NULL != p_instance_ctrl->p_callback) + { + callback_arg.channel = p_instance_ctrl->p_ether_cfg->channel; + callback_arg.event = ETHER_EVENT_LINK_ON; + callback_arg.status_ecsr = 0; + callback_arg.status_eesr = 0; + callback_arg.p_context = p_instance_ctrl->p_ether_cfg->p_context; + ether_call_callback(p_instance_ctrl, &callback_arg); + } + } + else + { + /* When PHY auto-negotiation is not completed */ + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_UP; + } + +#if (ETHER_CFG_USE_LINKSTA == 1) + } + else + { + /* no process */ + } +#endif + } + /* When the link is down */ + else if (ETHER_LINK_CHANGE_LINK_DOWN == p_instance_ctrl->link_change) + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; + +#if (ETHER_CFG_USE_LINKSTA == 1) + + /* + * The Link Up/Down is confirmed by the Link Status bit of PHY register1, + * because the LINK signal of PHY-LSI is used for LED indicator, and + * isn't used for notifying the Link Up/Down to external device. + */ + err = ether_link_status_check(p_instance_ctrl); + if (FSP_ERR_ETHER_ERROR_LINK == err) + { +#endif + + p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; + + /* Disable receive and transmit. */ + p_reg_etherc->ECMR_b.RE = 0; + p_reg_etherc->ECMR_b.TE = 0; + + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + + /* If a callback is provided, then call it with callback argument. */ + if (NULL != p_instance_ctrl->p_callback) + { + callback_arg.channel = p_instance_ctrl->p_ether_cfg->channel; + callback_arg.event = ETHER_EVENT_LINK_OFF; + callback_arg.status_ecsr = 0; + callback_arg.status_eesr = 0; + callback_arg.p_context = p_instance_ctrl->p_ether_cfg->p_context; + ether_call_callback(p_instance_ctrl, &callback_arg); + } + +#if (ETHER_CFG_USE_LINKSTA == 1) + } + else + { + ; /* no operation */ + } +#endif + } + else + { + ; /* no operation */ + } + + return err; +} /* End of function R_ETHER_LinkProcess() */ + +/********************************************************************************************************************//** + * @brief The setting of ETHERC is changed from normal sending and receiving mode to magic packet detection mode. + * Implements @ref ether_api_t::wakeOnLANEnable. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation is not completed, and reception is not enabled. + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK Initialization of PHY-LSI failed. + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_WakeOnLANEnable (ether_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + +#if (ETHER_CFG_USE_LINKSTA == 1) + R_ETHERC0_Type * p_reg_etherc; +#endif + + /* Check argument */ +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* When the Link up processing is not completed, return error */ + ETHER_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, + FSP_ERR_ETHER_ERROR_LINK); + + /* When the Link up processing is completed */ + /* Change to the magic packet detection mode. */ + ether_configure_mac(p_instance_ctrl, p_instance_ctrl->p_ether_cfg->p_mac_address, ETHER_USE_MAGIC_PACKET_DETECT); + err = ether_do_link(p_instance_ctrl, ETHER_USE_MAGIC_PACKET_DETECT); + if (FSP_SUCCESS == err) + { +#if (ETHER_CFG_USE_LINKSTA == 1) + p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; + + /* It is confirmed not to become Link down while changing the setting. */ + if (ETHER_CFG_LINK_PRESENT == p_reg_etherc->PSR_b.LMON) + { + err = FSP_SUCCESS; + } + else + { + err = FSP_ERR_ETHER_ERROR_LINK; + } + +#else + + /* It is confirmed not to become Link down while changing the setting. */ + err = ether_link_status_check(p_instance_ctrl); +#endif + } + else + { + err = FSP_ERR_ETHER_ERROR_LINK; + } + + return err; +} /* End of function R_ETHER_WakeOnLANEnable() */ + +/********************************************************************************************************************//** + * @brief Receive Ethernet frame. Receives data to the location specified by the pointer to the receive buffer. + * In zero copy mode, the address of the receive buffer is returned. + * In non zero copy mode, the received data in the internal buffer is copied to the pointer passed by the argument. + * Implements @ref ether_api_t::read. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_NO_DATA There is no data in receive buffer. + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation is not completed, and reception is not enabled. + * @retval FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE As a Magic Packet is being detected, transmission and reception + * is not enabled. + * @retval FSP_ERR_ETHER_ERROR_FILTERING Multicast Frame filter is enable, and Multicast Address Frame is + * received. + * @retval FSP_ERR_INVALID_POINTER Value of the pointer is NULL. + * @retval FSP_ERR_INVALID_SIZE The buffer size is smaller than @ref ether_cfg_t::ether_buffer_size. + * + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_Read (ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t * const length_bytes) +{ + fsp_err_t err = FSP_SUCCESS; + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + uint8_t * p_read_buffer = NULL; /* Buffer location controlled by the Ethernet driver */ + uint32_t received_size = ETHER_NO_DATA; + uint8_t ** pp_read_buffer = (uint8_t **) p_buffer; + + /* Check argument */ +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHER_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER); + ETHER_ERROR_RETURN(NULL != length_bytes, FSP_ERR_INVALID_POINTER); + #if (ETHER_CFG_READ_BUFFER_SIZE_CHECK) + ETHER_ERROR_RETURN(p_instance_ctrl->p_ether_cfg->ether_buffer_size <= *length_bytes, FSP_ERR_INVALID_SIZE); + #endif +#endif + + /* (1) Retrieve the receive buffer location controlled by the descriptor. */ + /* When the Link up processing is not completed, return error */ + ETHER_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, + FSP_ERR_ETHER_ERROR_LINK); + + /* In case of detection mode of magic packet, return error. */ + ETHER_ERROR_RETURN(0 == ether_check_magic_packet_detection_bit(p_instance_ctrl), + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE); + + while (FSP_SUCCESS == err) + { + /* When receive data exists. */ + + if (ETHER_RD0_RACT != (p_instance_ctrl->p_rx_descriptor->status & ETHER_RD0_RACT)) + { + /* Check multicast is detected when multicast frame filter is enabled */ + + if (ETHER_MULTICAST_DISABLE == p_instance_ctrl->p_ether_cfg->multicast) + { + if (ETHER_RD0_RFS7_RMAF == (p_instance_ctrl->p_rx_descriptor->status & ETHER_RD0_RFS7_RMAF)) + { + /* The buffer is released at the multicast frame detect. */ + + err = R_ETHER_BufferRelease((ether_ctrl_t *) p_instance_ctrl); + + if (FSP_SUCCESS == err) + { + err = FSP_ERR_ETHER_ERROR_FILTERING; + } + + break; + } + } + + if (ETHER_RD0_RFE == (p_instance_ctrl->p_rx_descriptor->status & ETHER_RD0_RFE)) + { + /* The buffer is released at the error. */ + err = R_ETHER_BufferRelease((ether_ctrl_t *) p_instance_ctrl); + } + else + { + /** + * Pass the pointer to received data to application. This is + * zero-copy operation. + */ + p_read_buffer = p_instance_ctrl->p_rx_descriptor->p_buffer; + + /* Get bytes received */ + received_size = + (uint32_t) (p_instance_ctrl->p_rx_descriptor->size + + (uint16_t) p_instance_ctrl->p_ether_cfg->padding); + break; + } + } + else + { + break; + } + } + + if (FSP_SUCCESS == err) + { + /* When there is data to receive */ + if (received_size > ETHER_NO_DATA) + { + if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_ether_cfg->zerocopy) + { + /* (2) Copy the data read from the receive buffer which is controlled + * by the descriptor to the buffer which is specified by the user (up to 1024 bytes). */ + memcpy(p_buffer, p_read_buffer, received_size); + + /* (3) Read the receive data from the receive buffer controlled by the descriptor, + * and then release the receive buffer. */ + err = R_ETHER_BufferRelease((ether_ctrl_t *) p_instance_ctrl); + } + else + { + *pp_read_buffer = p_read_buffer; + } + + *length_bytes = received_size; + } + /* When there is no data to receive */ + else + { + err = FSP_ERR_ETHER_ERROR_NO_DATA; + } + } + + return err; +} /* End of function R_ETHER_Read() */ + +/********************************************************************************************************************//** + * @brief Transmit Ethernet frame. Transmits data from the location specified by the pointer to the transmit + * buffer, with the data size equal to the specified frame length. + * In the non zero copy mode, transmits data after being copied to the internal buffer. + * Implements @ref ether_api_t::write. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation is not completed, and reception is not enabled. + * @retval FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE As a Magic Packet is being detected, transmission and reception + * is not enabled. + * @retval FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL Transmit buffer is not empty. + * @retval FSP_ERR_INVALID_POINTER Value of the pointer is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Value of the send frame size is out of range. + * + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_Write (ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length) +{ + fsp_err_t err = FSP_SUCCESS; + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + R_ETHERC_EDMAC_Type * p_reg_edmac; + + uint8_t * p_write_buffer; + uint32_t write_buffer_size; + + /* Check argument */ +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHER_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER); + ETHER_ERROR_RETURN((ETHER_MINIMUM_FRAME_SIZE <= frame_length) && (ETHER_MAXIMUM_FRAME_SIZE >= frame_length), + FSP_ERR_INVALID_ARGUMENT); +#endif + + /* When the Link up processing is not completed, return error */ + ETHER_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, + FSP_ERR_ETHER_ERROR_LINK); + + /* In case of detection mode of magic packet, return error. */ + ETHER_ERROR_RETURN(0 == ether_check_magic_packet_detection_bit(p_instance_ctrl), + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE); + + if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_ether_cfg->zerocopy) + { + /* (1) Retrieve the transmit buffer location controlled by the descriptor. */ + err = ether_buffer_get(p_instance_ctrl, (void **) &p_write_buffer, &write_buffer_size); + + /* Writing to the transmit buffer (buf) is enabled. */ + if (FSP_SUCCESS == err) + { + if (write_buffer_size < frame_length) + { + err = FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL; /* Transmit buffer overflow */ + } + else + { + /* Write the transmit data to the transmit buffer. */ + + /* (2) Write the data to the transmit buffer controlled by the descriptor. */ + memcpy(p_write_buffer, p_buffer, frame_length); + } + } + } + + /* Writing to the transmit buffer (buf) is enabled. */ + if (FSP_SUCCESS == err) + { + /* (3) Enable the EDMAC to transmit data in the transmit buffer. */ + /* When the Link up processing is not completed, return error */ + + /* The data of the buffer is made active. */ + if (ETHER_ZEROCOPY_ENABLE == p_instance_ctrl->p_ether_cfg->zerocopy) + { + p_instance_ctrl->p_tx_descriptor->p_buffer = (uint8_t *) p_buffer; + } + + p_instance_ctrl->p_tx_descriptor->buffer_size = (uint16_t) frame_length; + p_instance_ctrl->p_tx_descriptor->status &= (~(ETHER_TD0_TFP1 | ETHER_TD0_TFP0)); + p_instance_ctrl->p_tx_descriptor->status |= ((ETHER_TD0_TFP1 | ETHER_TD0_TFP0) | ETHER_TD0_TACT); + p_instance_ctrl->p_tx_descriptor = p_instance_ctrl->p_tx_descriptor->p_next; + + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + + if (ETHER_EDMAC_EDTRR_TRANSMIT_REQUEST != p_reg_edmac->EDTRR) + { + /* Restart if stopped */ + p_reg_edmac->EDTRR = ETHER_EDMAC_EDTRR_TRANSMIT_REQUEST; + } + } + + return err; +} /* End of function R_ETHER_Write() */ + +/**********************************************************************************************************************//** + * Provides status of Ethernet driver in the user provided pointer. Implements @ref ether_api_t::txStatusGet. + * + * @retval FSP_SUCCESS Transmit buffer address is stored in provided p_buffer_address. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER p_status is NULL. + * @retval FSP_ERR_NOT_FOUND Transmit buffer address has been overwritten in transmit descriptor. + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_TxStatusGet (ether_ctrl_t * const p_ctrl, void * const p_buffer_address) +{ + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) p_ctrl; + ether_extended_cfg_t * p_ether_extended_cfg; + R_ETHERC_EDMAC_Type * p_reg_edmac; + ether_instance_descriptor_t * p_descriptor; + uint8_t ** p_sent_buffer_address = (uint8_t **) p_buffer_address; + fsp_err_t err = FSP_ERR_NOT_FOUND; + +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHER_ERROR_RETURN(NULL != p_buffer_address, FSP_ERR_INVALID_POINTER); +#endif + p_ether_extended_cfg = (ether_extended_cfg_t *) p_instance_ctrl->p_ether_cfg->p_extend; + + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + + p_descriptor = (ether_instance_descriptor_t *) p_reg_edmac->TDFAR; + + /* Descriptor is NULL, when no packet transmitted. */ + if (NULL != p_descriptor) + { + uint32_t num_tx_descriptors = p_instance_ctrl->p_ether_cfg->num_tx_descriptors; + ether_instance_descriptor_t * p_tx_descriptors = p_ether_extended_cfg->p_tx_descriptors; + + p_descriptor = (ether_instance_descriptor_t *) ((uint8_t *) p_descriptor - sizeof(ether_instance_descriptor_t)); + + if (p_descriptor < p_tx_descriptors) + { + p_descriptor = &p_tx_descriptors[num_tx_descriptors - 1]; + } + + /* Check that the descriptor is not overridden. */ + if ((NULL != p_descriptor->p_buffer) && (ETHER_TD0_TACT != (p_descriptor->status & ETHER_TD0_TACT))) + { + *p_sent_buffer_address = p_descriptor->p_buffer; + err = FSP_SUCCESS; + } + else + { + ; + } + } + + return err; +} /* End of function R_ETHER_VersionGet() */ + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref ether_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_ETHER_CallbackSet (ether_ctrl_t * const p_api_ctrl, + void ( * p_callback)(ether_callback_args_t *), + void * const p_context, + ether_callback_args_t * const p_callback_memory) +{ + ether_instance_ctrl_t * p_ctrl = (ether_instance_ctrl_t *) p_api_ctrl; + +#if ETHER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(ETHER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if ETHER_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + ether_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(ether_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup ETHER) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * @brief Parameter error check function for open. + * + * @param[in] p_instance_ctrl Pointer to the control block for the channel + * @param[in] p_cfg Pointer to the configuration structure specific to UART mode + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block or configuration structure is NULL + * @retval FSP_ERR_INVALID_CHANNEL Invalid channel number is given. + * @retval FSP_ERR_INVALID_POINTER Pointer to MAC address is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Irq number lower then 0. + **********************************************************************************************************************/ +static fsp_err_t ether_open_param_check (ether_instance_ctrl_t const * const p_instance_ctrl, + ether_cfg_t const * const p_cfg) +{ + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN((NULL != p_cfg), FSP_ERR_INVALID_POINTER); + ETHER_ERROR_RETURN((NULL != p_cfg->p_mac_address), FSP_ERR_INVALID_POINTER); + ETHER_ERROR_RETURN((NULL != p_cfg->p_extend), FSP_ERR_INVALID_POINTER); + ETHER_ERROR_RETURN((BSP_FEATURE_ETHER_NUM_CHANNELS > p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + ETHER_ERROR_RETURN((0 <= p_cfg->irq), FSP_ERR_INVALID_ARGUMENT); + ETHER_ERROR_RETURN((p_cfg->padding <= ETHER_PADDING_3BYTE), FSP_ERR_INVALID_ARGUMENT); + + if (p_cfg->padding != ETHER_PADDING_DISABLE) + { + ETHER_ERROR_RETURN((p_cfg->padding_offset <= ETHER_MAXIMUM_PADDING_OFFSET), FSP_ERR_INVALID_ARGUMENT); + } + + if (p_cfg->zerocopy == ETHER_ZEROCOPY_DISABLE) + { + ETHER_ERROR_RETURN((p_cfg->pp_ether_buffers != NULL), FSP_ERR_INVALID_ARGUMENT); + } + + return FSP_SUCCESS; +} + +#endif + +/*********************************************************************************************************************** + * Function Name: ether_reset_mac + * Description : The EDMAC and EtherC are reset through the software reset. + * Arguments : channel - + * ETHERC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_reset_mac (R_ETHERC_EDMAC_Type * const p_reg) +{ + p_reg->EDMR_b.SWR = 1; + + /* + * Waiting time until the initialization of ETHERC and EDMAC is completed is 64 cycles + * in the clock conversion of an internal bus of EDMAC. + */ + R_BSP_SoftwareDelay(ETHER_ETHERC_INITIALIZATION_WAIT_CYCLE * BSP_DELAY_UNITS_SECONDS / SystemCoreClock + 1, + BSP_DELAY_UNITS_MICROSECONDS); +} /* End of function ether_reset_mac() */ + +/*********************************************************************************************************************** + * Function Name: ether_init_descriptors + * Description : The EDMAC descriptors and the driver buffers are initialized. + * Arguments : channel - + * ETHERC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_init_descriptors (ether_instance_ctrl_t * const p_instance_ctrl) +{ + ether_instance_descriptor_t * p_descriptor = NULL; + uint32_t i; + ether_extended_cfg_t * p_ether_extended_cfg = (ether_extended_cfg_t *) p_instance_ctrl->p_ether_cfg->p_extend; + + /* Initialize the receive descriptors */ + for (i = 0; i < p_instance_ctrl->p_ether_cfg->num_rx_descriptors; i++) + { + p_descriptor = &p_ether_extended_cfg->p_rx_descriptors[i]; + p_descriptor->buffer_size = (uint16_t) p_instance_ctrl->p_ether_cfg->ether_buffer_size; + p_descriptor->size = 0; + p_descriptor->p_next = &p_ether_extended_cfg->p_rx_descriptors[(i + 1)]; + + if (NULL != p_instance_ctrl->p_ether_cfg->pp_ether_buffers) + { + p_descriptor->p_buffer = p_instance_ctrl->p_ether_cfg->pp_ether_buffers[i]; + p_descriptor->status = ETHER_RD0_RACT; + } + else + { + p_descriptor->p_buffer = NULL; + } + } + + if (NULL != p_descriptor) + { + /* The last descriptor points back to the start */ + p_descriptor->status |= ETHER_RD0_RDLE; + p_descriptor->p_next = &p_ether_extended_cfg->p_rx_descriptors[0]; + + /* Initialize application receive descriptor pointer */ + p_instance_ctrl->p_rx_descriptor = &p_ether_extended_cfg->p_rx_descriptors[0]; + } + + /* Initialize the transmit descriptors */ + for (i = 0; i < p_instance_ctrl->p_ether_cfg->num_tx_descriptors; i++) + { + p_descriptor = &p_ether_extended_cfg->p_tx_descriptors[i]; + p_descriptor->buffer_size = 1; /* Set a value equal to or greater than 1. (reference to UMH) + * When transmitting data, the value of size is set to the function argument + * R_ETHER_Write. */ + p_descriptor->size = 0; /* Reserved : The write value should be 0. (reference to UMH) */ + p_descriptor->status = 0; + p_descriptor->p_next = &p_ether_extended_cfg->p_tx_descriptors[(i + 1)]; + + if ((ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_ether_cfg->zerocopy) && + (NULL != p_instance_ctrl->p_ether_cfg->pp_ether_buffers)) + { + p_descriptor->p_buffer = + p_instance_ctrl->p_ether_cfg->pp_ether_buffers[(p_instance_ctrl->p_ether_cfg->num_rx_descriptors + i)]; + } + else + { + p_descriptor->p_buffer = NULL; + } + } + + if (NULL != p_descriptor) + { + /* The last descriptor points back to the start */ + p_descriptor->status |= ETHER_TD0_TDLE; + p_descriptor->p_next = &p_ether_extended_cfg->p_tx_descriptors[0]; + + /* Initialize application transmit descriptor pointer */ + p_instance_ctrl->p_tx_descriptor = &p_ether_extended_cfg->p_tx_descriptors[0]; + } +} /* End of function ether_init_descriptors() */ + +/*********************************************************************************************************************** + * Function Name: ether_init_buffers + * Description : The driver buffers are initialized. + * Arguments : p_instance_ctrl - + * ETHERC control block. + * Return Value : none + ***********************************************************************************************************************/ +static void ether_init_buffers (ether_instance_ctrl_t * const p_instance_ctrl) +{ + uint32_t i; + uint32_t buffer_num; + + if (NULL != p_instance_ctrl->p_ether_cfg->pp_ether_buffers) + { + if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_ether_cfg->zerocopy) + { + buffer_num = + (uint32_t) (p_instance_ctrl->p_ether_cfg->num_tx_descriptors + + p_instance_ctrl->p_ether_cfg->num_rx_descriptors); + } + else + { + buffer_num = (uint32_t) p_instance_ctrl->p_ether_cfg->num_rx_descriptors; + } + + for (i = 0; i < buffer_num; i++) + { + memset(p_instance_ctrl->p_ether_cfg->pp_ether_buffers[i], + 0x00, + p_instance_ctrl->p_ether_cfg->ether_buffer_size); + } + } +} /* End of function ether_init_buffers() */ + +/********************************************************************************************************************//** + * @brief Get Points to the buffer pointer used by the stack. + * @param[in] p_instance_ctrl Ethernet driver control block. + * @param[out] p_buffer Pointer to location to store the buffer pointer + * @param[out] p_buffer_size Pointer to location to store the buffer size + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL Transmit buffer is not empty. + * + ***********************************************************************************************************************/ +static fsp_err_t ether_buffer_get (ether_instance_ctrl_t * const p_instance_ctrl, + void ** const p_buffer, + uint32_t * p_buffer_size) +{ + fsp_err_t err = FSP_SUCCESS; + + /* When the Link up processing is completed */ + /* All transmit buffers are full */ + if (ETHER_TD0_TACT == (p_instance_ctrl->p_tx_descriptor->status & ETHER_TD0_TACT)) + { + err = FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL; + } + else + { + /* Give application another buffer to work with */ + (*p_buffer) = p_instance_ctrl->p_tx_descriptor->p_buffer; + (*p_buffer_size) = p_instance_ctrl->p_ether_cfg->ether_buffer_size; + err = FSP_SUCCESS; + } + + return err; +} /* End of function ether_buffer_get() */ + +/*********************************************************************************************************************** + * Function Name: ether_config_ethernet + * Description : Configure the Ethernet Controller (EtherC) and the Ethernet + * Direct Memory Access controller (EDMAC). + * Arguments : channel - + * ETHERC channel number + * mode - + * The operational mode is specified. + * NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually + * USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode + * Return Value : none + ***********************************************************************************************************************/ +static void ether_config_ethernet (ether_instance_ctrl_t const * const p_instance_ctrl, const uint8_t mode) +{ + R_ETHERC0_Type * p_reg_etherc; + R_ETHERC_EDMAC_Type * p_reg_edmac; + +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + + /* Check argument */ + if ((NULL == p_instance_ctrl) || (ETHER_OPEN != p_instance_ctrl->open)) + { + return; + } +#endif + + p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + + /* Magic packet detection mode */ + if (ETHER_USE_MAGIC_PACKET_DETECT == mode) + { +#if (ETHER_CFG_USE_LINKSTA == 1) + p_reg_etherc->ECSIPR = (ETHER_ETHERC_INTERRUPT_ENABLE_LCHNG | ETHER_ETHERC_INTERRUPT_ENABLE_MPD); +#elif (ETHER_CFG_USE_LINKSTA == 0) + p_reg_etherc->ECSIPR_b.MPDIP = 1; +#endif + p_reg_edmac->EESIPR_b.ECIIP = 1; + } + /* Normal mode */ + else + { +#if (ETHER_CFG_USE_LINKSTA == 1) + + /* LINK Signal Change Interrupt Enable */ + p_reg_etherc->ECSR_b.LCHNG = 1; + p_reg_etherc->ECSIPR_b.LCHNGIP = 1; +#endif + p_reg_edmac->EESIPR_b.ECIIP = 1; + + /* Frame receive interrupt and frame transmit end interrupt */ + p_reg_edmac->EESIPR_b.FRIP = 1; /* Enable the frame receive interrupt. */ + p_reg_edmac->EESIPR_b.TCIP = 1; /* Enable the frame transmit end interrupt. */ + } + + /* Ethernet length 1514bytes + CRC and intergap is 96-bit time */ + p_reg_etherc->RFLR = ETHER_ETHERC_RFLR_DEFAULT_VALUE; /* Ethernet length (1514bytes) + CRC(4byte) */ + p_reg_etherc->IPGR = ETHER_ETHERC_IPGR_DEFAULT_VALUE; /* Interpacket Gap is 96-bit time */ + + /* Continuous reception number of Broadcast frame */ + p_reg_etherc->BCFRR = p_instance_ctrl->p_ether_cfg->broadcast_filter; + +#if ((defined(__GNUC__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) || (defined(__ARMCC_VERSION) && \ + !defined(__ARM_BIG_ENDIAN)) || (defined(__ICCARM__) && (__LITTLE_ENDIAN__))) + + /* Set little endian mode */ + p_reg_edmac->EDMR_b.DE = 1; +#endif + + /* Initialize Rx descriptor list address */ + /* Casting the pointer to a uint32_t type is valid because the Renesas Compiler uses 4 bytes per pointer. */ + p_reg_edmac->RDLAR = (uint32_t) p_instance_ctrl->p_rx_descriptor; + + /* Initialize Tx descriptor list address */ + /* Casting the pointer to a uint32_t type is valid because the Renesas Compiler uses 4 bytes per pointer. */ + p_reg_edmac->TDLAR = (uint32_t) p_instance_ctrl->p_tx_descriptor; + + if (ETHER_MULTICAST_DISABLE == p_instance_ctrl->p_ether_cfg->multicast) + { + /* Reflect the EESR.RMAF bit status in the RD0.RFS bit in the receive descriptor */ + p_reg_edmac->TRSCER = ETHER_EDMAC_TRSCER_MULTICAST_DISABLE; + } + else + { + /* Don't reflect the EESR.RMAF bit status in the RD0.RFS bit in the receive descriptor */ + p_reg_edmac->TRSCER = ETHER_EDMAC_TRSCER_MULTICAST_ENABLE; + } + + /* Threshold of Tx_FIFO */ + /* To prevent a transmit underflow, setting the initial value (store and forward modes) is recommended. */ + p_reg_edmac->TFTR = ETHER_EDMAC_TFTR_STORE_AND_FORWARD_MODE; + + p_reg_edmac->FDR = BSP_FEATURE_ETHER_FIFO_DEPTH; + + /* Configure receiving method + * b0 RNR - Receive Request Bit Reset - Continuous reception of multiple frames is possible. + * b31:b1 Reserved set to 0 + */ + p_reg_edmac->RMCR = ETHER_EDMAC_RMCR_MULTIPLE_FRAMES_ENABLE; +} /* End of function ether_config_ethernet() */ + +/*********************************************************************************************************************** + * Function Name: ether_pause_resolution + * Description : Determines PAUSE frame generation and handling. Uses + * the resolution Table 28B-3 of IEEE 802.3-2008. + * Arguments : local_ability - + * local PAUSE capability (2 least significant bits) + * partner_ability - + * link partner PAUSE capability (2 least significant bits) + * *ptx_pause - + * pointer to location to store the result of the table lookup for transmit + * PAUSE. 1 is enable, 0 is disable. + * *prx_pause - + * pointer to location to store the result of the table lookup for receive + * PAUSE. 1 is enable, 0 is disable. + * Return Value : none + ***********************************************************************************************************************/ +static void ether_pause_resolution (uint32_t const local_ability, + uint32_t const partner_ability, + uint32_t * ptx_pause, + uint32_t * prx_pause) +{ + uint32_t i; + uint32_t ability_compare; + + /* + * Arrange the bits so that they correspond to the Table 28B-3 + * of the IEEE 802.3 values. + */ + ability_compare = + (uint32_t) (((local_ability & ETHER_LINK_RESOLUTION_ABILITY_MASK) << + ETHER_LINK_RESOLUTION_LOCAL_ABILITY_BITSHIFT) | + (partner_ability & ETHER_LINK_RESOLUTION_ABILITY_MASK)); + + /* Walk through the look up table */ + for (i = 0; i < ETHER_PAUSE_TABLE_ENTRIES; i++) + { + if ((ability_compare & pause_resolution[i].mask) == pause_resolution[i].value) + { + (*ptx_pause) = pause_resolution[i].transmit; + (*prx_pause) = pause_resolution[i].receive; + + return; + } + } +} /* End of function ether_pause_resolution() */ + +/*********************************************************************************************************************** + * Function Name: ether_configure_mac + * Description : Software reset is executed, and ETHERC and EDMAC are configured. + * Arguments : channel - + * ETHERC channel number + * mac_addr - + * The MAC address of ETHERC + * mode - + * The operational mode is specified. + * NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually + * USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode + * Return Value : none + ***********************************************************************************************************************/ +static void ether_configure_mac (ether_instance_ctrl_t * const p_instance_ctrl, + const uint8_t mac_addr[], + const uint8_t mode) +{ + R_ETHERC0_Type * p_reg_etherc; + uint32_t mac_h; + uint32_t mac_l; + +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + + /* Check argument */ + if ((NULL == p_instance_ctrl) || (ETHER_OPEN != p_instance_ctrl->open)) + { + return; + } +#endif + + p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; + + /* Software reset */ + ether_reset_mac(p_instance_ctrl->p_reg_edmac); + + /* Setting the padding function */ + ether_configure_padding(p_instance_ctrl); + + /* Set MAC address */ + mac_h = (((((uint32_t) mac_addr[0] << 24) | ((uint32_t) mac_addr[1] << 16)) | ((uint32_t) mac_addr[2] << 8)) | + (uint32_t) mac_addr[3]); + + mac_l = (((uint32_t) mac_addr[4] << 8) | (uint32_t) mac_addr[5]); + + p_reg_etherc->MAHR = mac_h; + p_reg_etherc->MALR = mac_l; + + /* Initialize receive and transmit descriptors */ + ether_init_descriptors(p_instance_ctrl); + + /* Perform reset of hardware interface configuration */ + ether_config_ethernet(p_instance_ctrl, mode); +} /* End of function ether_configure_mac() */ + +/********************************************************************************************************************//** + * @brief Determines the partner PHY capability through auto-negotiation process. The link abilities + * are handled to determine duplex, speed and flow control (PAUSE frames). + * + * @param[in] p_instance_ctrl Pointer to the control block for the channel + * @param[in] mode The operational mode is specified. + * NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually + * USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block or configuration structure is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation of PHY-LSI is not completed + * or result of Auto-negotiation is abnormal. + * + ***********************************************************************************************************************/ +static fsp_err_t ether_do_link (ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode) +{ + fsp_err_t err; + R_ETHERC0_Type * p_reg_etherc; + R_ETHERC_EDMAC_Type * p_reg_edmac; + + uint32_t link_speed_duplex = 0; + uint32_t local_pause_bits = 0; + uint32_t partner_pause_bits = 0; + uint32_t transmit_pause_set = 0; + uint32_t receive_pause_set = 0; + uint32_t full_duplex = 0; + fsp_err_t link_result; + +#if (ETHER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_ERROR_RETURN(ETHER_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + + /* Set the link status */ + link_result = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->linkPartnerAbilityGet( + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl, + &link_speed_duplex, + &local_pause_bits, + &partner_pause_bits); + + if (FSP_SUCCESS == link_result) + { + switch (link_speed_duplex) + { + /* Half duplex link */ + case ETHER_PHY_LINK_SPEED_100H: + { + p_reg_etherc->ECMR_b.DM = 0; + p_reg_etherc->ECMR_b.RTM = 1; + err = FSP_SUCCESS; + break; + } + + case ETHER_PHY_LINK_SPEED_10H: + { + p_reg_etherc->ECMR_b.DM = 0; + p_reg_etherc->ECMR_b.RTM = 0; + err = FSP_SUCCESS; + break; + } + + /* Full duplex link */ + case ETHER_PHY_LINK_SPEED_100F: + { + p_reg_etherc->ECMR_b.DM = 1; + p_reg_etherc->ECMR_b.RTM = 1; + full_duplex = 1; + err = FSP_SUCCESS; + break; + } + + case ETHER_PHY_LINK_SPEED_10F: + { + p_reg_etherc->ECMR_b.DM = 1; + p_reg_etherc->ECMR_b.RTM = 0; + full_duplex = 1; + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_ETHER_ERROR_LINK; + break; + } + } + + /* At the communicate mode usually */ + if (FSP_SUCCESS == err) + { + if (ETHER_NO_USE_MAGIC_PACKET_DETECT == mode) + { + /* When pause frame is used */ + if ((full_duplex) && (ETHER_FLOW_CONTROL_ENABLE == p_instance_ctrl->p_ether_cfg->flow_control)) + { + /* Set automatic PAUSE for 512 bit-time */ + p_reg_etherc->APR = ETHER_ETHERC_APR_MAXIMUM_VALUE; + + /* Set unlimited retransmit of PAUSE frames */ + p_reg_etherc->TPAUSER = 0; + + /* PAUSE flow control FIFO settings. */ + p_reg_edmac->FCFTR = ETHER_ETHERC_FCFTR_MINIMUM_VALUE; + + /* Control of a PAUSE frame whose TIME parameter value is 0 is enabled. */ + p_reg_etherc->ECMR_b.ZPF = 1; + + /** + * Enable PAUSE for full duplex link depending on + * the pause resolution results + */ + ether_pause_resolution(local_pause_bits, partner_pause_bits, &transmit_pause_set, + &receive_pause_set); + + if (ETHER_PAUSE_XMIT_ON == transmit_pause_set) + { + /* Enable automatic PAUSE frame transmission */ + p_reg_etherc->ECMR_b.TXF = 1; + } + else + { + /* Disable automatic PAUSE frame transmission */ + p_reg_etherc->ECMR_b.TXF = 0; + } + + if (ETHER_PAUSE_RECV_ON == receive_pause_set) + { + /* Enable reception of PAUSE frames */ + p_reg_etherc->ECMR_b.RXF = 1; + } + else + { + /* Disable reception of PAUSE frames */ + p_reg_etherc->ECMR_b.RXF = 0; + } + } + /* When pause frame is not used */ + else + { + /* Disable PAUSE for half duplex link */ + p_reg_etherc->ECMR_b.TXF = 0; + p_reg_etherc->ECMR_b.RXF = 0; + } + + /* Set the promiscuous mode bit */ + p_reg_etherc->ECMR_b.PRM = p_instance_ctrl->p_ether_cfg->promiscuous; + + /* Enable receive and transmit. */ + p_reg_etherc->ECMR_b.RE = 1; + p_reg_etherc->ECMR_b.TE = 1; + + /* Enable EDMAC receive */ + p_reg_edmac->EDRRR = 0x1; + } + /* At the magic packet detection mode */ + else + { + /* The magic packet detection is permitted. */ + p_reg_etherc->ECMR_b.MPDE = 1; + + /* Because data is not transmitted for the magic packet detection waiting, + * only the reception is permitted. */ + p_reg_etherc->ECMR_b.RE = 1; + + /* + * The reception function of EDMAC keep invalidity + * because the receive data don't need to be read when the magic packet detection mode. + */ + } + } + } + else + { + err = FSP_ERR_ETHER_ERROR_LINK; + } + + return err; +} /* End of function ether_do_link() */ + +/*********************************************************************************************************************** + * Function Name: ether_check_magic_packet_detection_bit + * Description : + * Arguments : ether_instance_ctrl_t const * const p_instance_ctrl + * Return Value : 1: Magic Packet detection is enabled. + * 0: Magic Packet detection is disabled. + ***********************************************************************************************************************/ +static uint8_t ether_check_magic_packet_detection_bit (ether_instance_ctrl_t const * const p_instance_ctrl) +{ + R_ETHERC0_Type * p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; + uint8_t ret = 0; + + /* The MPDE bit can be referred to only when ETHERC operates. */ + if ((1 == p_reg_etherc->ECMR_b.MPDE)) + { + ret = 1; + } + else + { + ret = 0; + } + + return ret; +} /* End of function ether_check_magic_packet_detection_bit() */ + +/*******************************************************************************************************************//** + * @brief Verifies the Ethernet link is up or not. + * + * @param[in] p_instance_ctrl Pointer to the control block for the channel + * + * @retval FSP_SUCCESS: Link is up + * @retval FSP_ERR_ETHER_ERROR_LINK: Link is down + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK Initialization of PHY-LSI failed. + **********************************************************************************************************************/ +static fsp_err_t ether_link_status_check (ether_instance_ctrl_t const * const p_instance_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + fsp_err_t link_status; + + link_status = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->linkStatusGet( + p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl); + + if (FSP_ERR_ETHER_PHY_ERROR_LINK == link_status) + { + /* Link is down */ + err = FSP_ERR_ETHER_ERROR_LINK; + } + else + { + /* Link is up */ + err = FSP_SUCCESS; + } + + return err; +} /* End of function ether_link_status_check() */ + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_instance_ctrl Pointer to ether instance control block + * @param[in] p_callback_args Pointer to callback args + **********************************************************************************************************************/ +static void ether_call_callback (ether_instance_ctrl_t * p_instance_ctrl, ether_callback_args_t * p_callback_args) +{ + ether_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + ether_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = p_callback_args->event; + p_args->channel = p_instance_ctrl->p_ether_cfg->channel; + p_args->p_context = p_instance_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + ether_prv_ns_callback p_callback = (ether_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } +} + +/*********************************************************************************************************************** + * Function Name: ether_eint_isr + * Description : Interrupt handler for Ethernet receive and transmit interrupts. + * Arguments : none + * Return Value : none + ***********************************************************************************************************************/ +void ether_eint_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + uint32_t status_ecsr; + uint32_t status_eesr; + + ether_callback_args_t callback_arg; + R_ETHERC0_Type * p_reg_etherc; + R_ETHERC_EDMAC_Type * p_reg_edmac; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ether_instance_ctrl_t * p_instance_ctrl = (ether_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + ether_extended_cfg_t * p_ether_extended_cfg = (ether_extended_cfg_t *) p_instance_ctrl->p_ether_cfg->p_extend; + + p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc; + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + + status_ecsr = p_reg_etherc->ECSR; + status_eesr = p_reg_edmac->EESR; + + /* When the ETHERC status interrupt is generated */ + if (status_eesr & ETHER_EDMAC_INTERRUPT_FACTOR_ECI) + { +#if (ETHER_CFG_USE_LINKSTA == 1) + + /* When the link signal change interrupt is generated */ + if (ETHER_ETHERC_INTERRUPT_FACTOR_LCHNG == (status_ecsr & ETHER_ETHERC_INTERRUPT_FACTOR_LCHNG)) + { + /* The state of the link signal is confirmed and Link Up/Down is judged. */ + /* When becoming Link up */ + if (ETHER_CFG_LINK_PRESENT == p_reg_etherc->PSR_b.LMON) + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_UP; + } + /* When Link becomes down */ + else + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_DOWN; + } + } +#endif + + /* When the Magic Packet detection interrupt is generated */ + if (ETHER_ETHERC_INTERRUPT_FACTOR_MPD == (status_ecsr & ETHER_ETHERC_INTERRUPT_FACTOR_MPD)) + { + p_instance_ctrl->magic_packet = ETHER_MAGIC_PACKET_DETECTED; + } + + /* + * Because each bit of the ECSR register is cleared when one is written, + * the value read from the register is written and the bit is cleared. + */ + p_reg_etherc->ECSR = status_ecsr; /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ + } + + /* + * Because each bit of the EESR register is cleared when one is written, + * the value read from the register is written and the bit is cleared. + */ + p_reg_edmac->EESR = status_eesr; /* Clear EDMAC status bits */ + + /* If a callback is provided, then call it with callback argument. */ + if (NULL != p_instance_ctrl->p_callback) + { + callback_arg.channel = p_instance_ctrl->p_ether_cfg->channel; + callback_arg.p_context = p_instance_ctrl->p_ether_cfg->p_context; + + /* Callbacks for events related to EESR. */ + for (int i = 0; i < ETHER_EESR_EVENT_NUM; i++) + { + if (status_eesr & ether_eesr_event_mask[i].mask & p_ether_extended_cfg->eesr_event_filter) + { + callback_arg.event = ether_eesr_event_mask[i].event; + ether_call_callback(p_instance_ctrl, &callback_arg); + } + } + + /* Callbacks for events related to ECSR. */ + if (status_eesr & ETHER_EDMAC_INTERRUPT_FACTOR_ECI) + { + for (int i = 0; i < ETHER_ECSR_EVENT_NUM; i++) + { + if (status_ecsr & ether_ecsr_event_mask[i].mask & p_ether_extended_cfg->ecsr_event_filter) + { + callback_arg.event = ether_ecsr_event_mask[i].event; + ether_call_callback(p_instance_ctrl, &callback_arg); + } + } + } + } + + /* Clear pending interrupt flag to make sure it doesn't fire again + * after exiting. */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} /* End of function ether_eint_isr() */ + +/*********************************************************************************************************************** + * Function Name: ether_enable_icu + * Description : + * Arguments : channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_enable_icu (ether_instance_ctrl_t * const p_instance_ctrl) +{ + /** Configure the Ethernet interrupt. */ + R_BSP_IrqCfgEnable(p_instance_ctrl->p_ether_cfg->irq, + p_instance_ctrl->p_ether_cfg->interrupt_priority, + p_instance_ctrl); +} /* End of function ether_enable_icu() */ + +/*********************************************************************************************************************** + * Function Name: ether_disable_icu + * Description : + * Arguments : channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_disable_icu (ether_instance_ctrl_t * const p_instance_ctrl) +{ + /* Get IRQ number for EDMAC_EINT interrupt. */ + NVIC_DisableIRQ(p_instance_ctrl->p_ether_cfg->irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_ether_cfg->irq, NULL); +} /* End of function ether_disable_icu() */ + +/*********************************************************************************************************************** + * Function Name: ether_configure_padding + * Description : + * Arguments : channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_configure_padding (ether_instance_ctrl_t * const p_instance_ctrl) +{ + R_ETHERC_EDMAC_Type * p_reg_edmac; + p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac; + p_reg_edmac->RPADIR_b.PADR = (unsigned) p_instance_ctrl->p_ether_cfg->padding_offset & ETHER_MAXIMUM_PADDING_OFFSET; + p_reg_edmac->RPADIR_b.PADS = p_instance_ctrl->p_ether_cfg->padding; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/r_ether_phy.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/r_ether_phy.c new file mode 100644 index 0000000000..3dbed1403c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/r_ether_phy.c @@ -0,0 +1,1120 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_ether_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +#ifndef ETHER_PHY_ERROR_RETURN + + #define ETHER_PHY_ERROR_RETURN(a, err) FSP_ERROR_RETURN((a), (err)) +#endif + +#define ETHERC_REG_SIZE (0x400UL) + +/** "RPHY" in ASCII. Used to determine if the control block is open. */ +#define ETHER_PHY_OPEN (0x52504859U) + +/* Media Independent Interface */ +#define ETHER_PHY_MII_ST (1) +#define ETHER_PHY_MII_READ (2) +#define ETHER_PHY_MII_WRITE (1) + +/* Standard PHY Registers */ +#define ETHER_PHY_REG_CONTROL (0) +#define ETHER_PHY_REG_STATUS (1) +#define ETHER_PHY_REG_IDENTIFIER1 (2) +#define ETHER_PHY_REG_IDENTIFIER2 (3) +#define ETHER_PHY_REG_AN_ADVERTISEMENT (4) +#define ETHER_PHY_REG_AN_LINK_PARTNER (5) +#define ETHER_PHY_REG_AN_EXPANSION (6) + +/* Basic Mode Control Register Bit Definitions */ +#define ETHER_PHY_CONTROL_RESET (1 << 15) +#define ETHER_PHY_CONTROL_LOOPBACK (1 << 14) +#define ETHER_PHY_CONTROL_100_MBPS (1 << 13) +#define ETHER_PHY_CONTROL_AN_ENABLE (1 << 12) +#define ETHER_PHY_CONTROL_POWER_DOWN (1 << 11) +#define ETHER_PHY_CONTROL_ISOLATE (1 << 10) +#define ETHER_PHY_CONTROL_AN_RESTART (1 << 9) +#define ETHER_PHY_CONTROL_FULL_DUPLEX (1 << 8) +#define ETHER_PHY_CONTROL_COLLISION (1 << 7) + +/* Basic Mode Status Register Bit Definitions */ +#define ETHER_PHY_STATUS_100_T4 (1 << 15) +#define ETHER_PHY_STATUS_100F (1 << 14) +#define ETHER_PHY_STATUS_100H (1 << 13) +#define ETHER_PHY_STATUS_10F (1 << 12) +#define ETHER_PHY_STATUS_10H (1 << 11) +#define ETHER_PHY_STATUS_AN_COMPLETE (1 << 5) +#define ETHER_PHY_STATUS_RM_FAULT (1 << 4) +#define ETHER_PHY_STATUS_AN_ABILITY (1 << 3) +#define ETHER_PHY_STATUS_LINK_UP (1 << 2) +#define ETHER_PHY_STATUS_JABBER (1 << 1) +#define ETHER_PHY_STATUS_EX_CAPABILITY (1 << 0) + +/* Auto Negotiation Advertisement Bit Definitions */ +#define ETHER_PHY_AN_ADVERTISEMENT_NEXT_PAGE (1 << 15) +#define ETHER_PHY_AN_ADVERTISEMENT_RM_FAULT (1 << 13) +#define ETHER_PHY_AN_ADVERTISEMENT_ASM_DIR (1 << 11) +#define ETHER_PHY_AN_ADVERTISEMENT_PAUSE (1 << 10) +#define ETHER_PHY_AN_ADVERTISEMENT_100_T4 (1 << 9) +#define ETHER_PHY_AN_ADVERTISEMENT_100F (1 << 8) +#define ETHER_PHY_AN_ADVERTISEMENT_100H (1 << 7) +#define ETHER_PHY_AN_ADVERTISEMENT_10F (1 << 6) +#define ETHER_PHY_AN_ADVERTISEMENT_10H (1 << 5) +#define ETHER_PHY_AN_ADVERTISEMENT_SELECTOR (1 << 0) + +/* Auto Negotiate Link Partner Ability Bit Definitions */ +#define ETHER_PHY_AN_LINK_PARTNER_NEXT_PAGE (1 << 15) +#define ETHER_PHY_AN_LINK_PARTNER_ACK (1 << 14) +#define ETHER_PHY_AN_LINK_PARTNER_RM_FAULT (1 << 13) +#define ETHER_PHY_AN_LINK_PARTNER_ASM_DIR (1 << 11) +#define ETHER_PHY_AN_LINK_PARTNER_PAUSE (1 << 10) +#define ETHER_PHY_AN_LINK_PARTNER_100_T4 (1 << 9) +#define ETHER_PHY_AN_LINK_PARTNER_100F (1 << 8) +#define ETHER_PHY_AN_LINK_PARTNER_100H (1 << 7) +#define ETHER_PHY_AN_LINK_PARTNER_10F (1 << 6) +#define ETHER_PHY_AN_LINK_PARTNER_10H (1 << 5) +#define ETHER_PHY_AN_LINK_PARTNER_SELECTOR (1 << 0) + +#define ETHER_PHY_PIR_MDI_MASK (1 << 3) +#define ETHER_PHY_PIR_MDO_HIGH (0x04) +#define ETHER_PHY_PIR_MDO_LOW (0x00) +#define ETHER_PHY_PIR_MMD_WRITE (0x02) +#define ETHER_PHY_PIR_MMD_READ (0x00) +#define ETHER_PHY_PIR_MDC_HIGH (0x01) +#define ETHER_PHY_PIR_MDC_LOW (0x00) + +#define ETHER_PHY_ADDRESS_SIZE (0x1fU) +#define ETHER_PHY_REGISTER_DATA_SIZE (0xffffU) + +#define ETHER_PHY_PREAMBLE_LENGTH (32U) +#define ETHER_PHY_WRITE_DATA_BIT_MASK (0x8000) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) +extern void ether_phy_target_ksz8091rnb_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +extern bool ether_phy_target_ksz8091rnb_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif +#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) +extern void ether_phy_target_ksz8041_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +extern bool ether_phy_target_ksz8041_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif +#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) +extern void ether_phy_target_dp83620_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +extern bool ether_phy_target_dp83620_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) +extern void ether_phy_target_ics1894_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +extern bool ether_phy_target_ics1894_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ +static void ether_phy_preamble(ether_phy_instance_ctrl_t * p_instance_ctrl); +static void ether_phy_reg_set(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, int32_t option); +static void ether_phy_reg_read(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t * pdata); +static void ether_phy_reg_write(ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t data); +static void ether_phy_trans_zto0(ether_phy_instance_ctrl_t * p_instance_ctrl); +static void ether_phy_trans_1to0(ether_phy_instance_ctrl_t * p_instance_ctrl); +static void ether_phy_trans_idle(ether_phy_instance_ctrl_t * p_instance_ctrl); +static void ether_phy_mii_write1(ether_phy_instance_ctrl_t * p_instance_ctrl); +static void ether_phy_mii_write0(ether_phy_instance_ctrl_t * p_instance_ctrl); +static void ether_phy_mii_writez(ether_phy_instance_ctrl_t * p_instance_ctrl); +static void ether_phy_targets_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +static bool ether_phy_targets_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/** ETHER_PHY HAL API mapping for Ethernet PHY Controller interface */ +/*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */ +const ether_phy_api_t g_ether_phy_on_ether_phy = +{ + .open = R_ETHER_PHY_Open, + .close = R_ETHER_PHY_Close, + .startAutoNegotiate = R_ETHER_PHY_StartAutoNegotiate, + .linkPartnerAbilityGet = R_ETHER_PHY_LinkPartnerAbilityGet, + .linkStatusGet = R_ETHER_PHY_LinkStatusGet, + .chipInit = R_ETHER_PHY_ChipInit, + .read = R_ETHER_PHY_Read, + .write = R_ETHER_PHY_Write +}; + +/*******************************************************************************************************************//** + * @addtogroup ETHER_PHY + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/********************************************************************************************************************//** + * @brief Resets Ethernet PHY device. Implements @ref ether_phy_api_t::open. + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER_PHY control block or configuration structure is NULL. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_CHANNEL Invalid channel number is given. + * @retval FSP_ERR_INVALID_POINTER Pointer to p_cfg is NULL. + * @retval FSP_ERR_TIMEOUT PHY-LSI Reset wait timeout. + * @retval FSP_ERR_INVALID_ARGUMENT Register address is incorrect + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized. + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_PHY_Open (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl; + R_ETHERC0_Type * p_reg_etherc; + +#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE) + ether_phy_extended_cfg_t * p_extend; + + FSP_ASSERT(p_instance_ctrl); + ETHER_PHY_ERROR_RETURN(NULL != p_cfg, FSP_ERR_INVALID_POINTER); + ETHER_PHY_ERROR_RETURN((ETHER_PHY_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN); + ETHER_PHY_ERROR_RETURN((BSP_FEATURE_ETHER_NUM_CHANNELS > p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + p_extend = (ether_phy_extended_cfg_t *) p_cfg->p_extend; + ETHER_PHY_ERROR_RETURN(NULL != p_extend, FSP_ERR_INVALID_POINTER); + ETHER_PHY_ERROR_RETURN(NULL != p_extend->p_phy_lsi_cfg_list[0], FSP_ERR_INVALID_ARGUMENT); +#endif + + /** Make sure this channel exists. */ + p_reg_etherc = ((R_ETHERC0_Type *) (R_ETHERC0_BASE + (ETHERC_REG_SIZE * p_cfg->channel))); + p_instance_ctrl->p_reg_pir = (uint32_t *) &p_reg_etherc->PIR; + p_instance_ctrl->local_advertise = 0; + + /* Initialize configuration of ethernet phy module. */ + p_instance_ctrl->p_ether_phy_cfg = p_cfg; + + /* Configure pins for MII or RMII. Set PHYMODE0 if MII is selected. */ + R_PMISC->PFENET = (uint8_t) ((ETHER_PHY_MII_TYPE_MII == p_cfg->mii_type) << R_PMISC_PFENET_PHYMODE0_Pos); + +#if ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC + uint32_t reg = 0; + uint32_t count = 0; + + p_instance_ctrl->interface_status = ETHER_PHY_INTERFACE_STATUS_INITIALIZED; + + /* Reset PHY */ + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_CONTROL, ETHER_PHY_CONTROL_RESET); + + /* Reset completion waiting */ + do + { + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_CONTROL, ®); + count++; + } while ((reg & ETHER_PHY_CONTROL_RESET) && (count < p_cfg->phy_reset_wait_time)); + + if (count < p_cfg->phy_reset_wait_time) + { + ether_phy_targets_initialize(p_instance_ctrl); + + p_instance_ctrl->open = ETHER_PHY_OPEN; + + err = FSP_SUCCESS; + } + else + { + err = FSP_ERR_TIMEOUT; + } + +#else + p_instance_ctrl->open = ETHER_PHY_OPEN; + + err = FSP_SUCCESS; +#endif + + return err; +} /* End of function R_ETHER_PHY_Open() */ + +/********************************************************************************************************************//** + * @brief Close Ethernet PHY device. Implements @ref ether_phy_api_t::close. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to ETHER_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_PHY_Close (ether_phy_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl; + +#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /** Clear configure block parameters. */ + p_instance_ctrl->p_ether_phy_cfg = NULL; + p_instance_ctrl->local_advertise = 0; + p_instance_ctrl->p_reg_pir = NULL; + + p_instance_ctrl->interface_status = ETHER_PHY_INTERFACE_STATUS_UNINITIALIZED; + p_instance_ctrl->open = 0; + + return err; +} /* End of function R_ETHER_PHY_Close() */ + +/********************************************************************************************************************//** + * @brief Starts auto-negotiate. Implements @ref ether_phy_api_t::startAutoNegotiate. + * + * @retval FSP_SUCCESS ETHER_PHY successfully starts auto-negotiate. + * @retval FSP_ERR_ASSERTION Pointer to ETHER_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Register address is incorrect + * @retval FSP_ERR_INVALID_POINTER Pointer to read buffer is NULL. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_PHY_StartAutoNegotiate (ether_phy_ctrl_t * const p_ctrl) +{ + ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + +#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* Set local ability */ + /* When pause frame is not used */ + if (ETHER_PHY_FLOW_CONTROL_DISABLE == p_instance_ctrl->p_ether_phy_cfg->flow_control) + { + p_instance_ctrl->local_advertise = ((((ETHER_PHY_AN_ADVERTISEMENT_100F | + ETHER_PHY_AN_ADVERTISEMENT_100H) | + ETHER_PHY_AN_ADVERTISEMENT_10F) | + ETHER_PHY_AN_ADVERTISEMENT_10H) | + ETHER_PHY_AN_ADVERTISEMENT_SELECTOR); + } + /* When pause frame is used */ + else + { + p_instance_ctrl->local_advertise = ((((((ETHER_PHY_AN_ADVERTISEMENT_ASM_DIR | + ETHER_PHY_AN_ADVERTISEMENT_PAUSE) | + ETHER_PHY_AN_ADVERTISEMENT_100F) | + ETHER_PHY_AN_ADVERTISEMENT_100H) | + ETHER_PHY_AN_ADVERTISEMENT_10F) | + ETHER_PHY_AN_ADVERTISEMENT_10H) | + ETHER_PHY_AN_ADVERTISEMENT_SELECTOR); + } + + /* Configure what the PHY and the Ethernet controller on this board supports */ + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_AN_ADVERTISEMENT, p_instance_ctrl->local_advertise); + R_ETHER_PHY_Write(p_instance_ctrl, + ETHER_PHY_REG_CONTROL, + (ETHER_PHY_CONTROL_AN_ENABLE | + ETHER_PHY_CONTROL_AN_RESTART)); + + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_AN_ADVERTISEMENT, ®); + + return FSP_SUCCESS; +} /* End of function R_ETHER_PHY_StartAutoNegotiate() */ + +/********************************************************************************************************************//** + * @brief Reports the other side's physical capability. Implements @ref ether_phy_api_t::linkPartnerAbilityGet. + * + * @retval FSP_SUCCESS ETHER_PHY successfully get link partner ability. + * @retval FSP_ERR_ASSERTION Pointer to ETHER_PHY control block is NULL. + * @retval FSP_ERR_INVALID_POINTER Pointer to arguments are NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK PHY-LSI is not link up. + * @retval FSP_ERR_ETHER_PHY_NOT_READY The auto-negotiation isn't completed + * @retval FSP_ERR_INVALID_ARGUMENT Status register address is incorrect + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_PHY_LinkPartnerAbilityGet (ether_phy_ctrl_t * const p_ctrl, + uint32_t * const p_line_speed_duplex, + uint32_t * const p_local_pause, + uint32_t * const p_partner_pause) +{ + fsp_err_t err = FSP_SUCCESS; + ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + uint32_t line_speed_duplex = ETHER_PHY_LINK_SPEED_NO_LINK; + +#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHER_PHY_ERROR_RETURN(NULL != p_line_speed_duplex, FSP_ERR_INVALID_POINTER); + ETHER_PHY_ERROR_RETURN(NULL != p_local_pause, FSP_ERR_INVALID_POINTER); + ETHER_PHY_ERROR_RETURN(NULL != p_partner_pause, FSP_ERR_INVALID_POINTER); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* Because reading the first time shows the previous state, the Link status bit is read twice. */ + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_STATUS, ®); + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_STATUS, ®); + + /* When the link isn't up, return error */ + ETHER_PHY_ERROR_RETURN(ETHER_PHY_STATUS_LINK_UP == (reg & ETHER_PHY_STATUS_LINK_UP), FSP_ERR_ETHER_PHY_ERROR_LINK); + + /* Establish local pause capability */ + if (ETHER_PHY_AN_ADVERTISEMENT_PAUSE == (p_instance_ctrl->local_advertise & ETHER_PHY_AN_ADVERTISEMENT_PAUSE)) + { + (*p_local_pause) |= (1 << 1); + } + + if (ETHER_PHY_AN_ADVERTISEMENT_ASM_DIR == (p_instance_ctrl->local_advertise & ETHER_PHY_AN_ADVERTISEMENT_ASM_DIR)) + { + (*p_local_pause) |= 1; + } + + /* When the auto-negotiation isn't completed, return error */ + ETHER_PHY_ERROR_RETURN(ETHER_PHY_STATUS_AN_COMPLETE == (reg & ETHER_PHY_STATUS_AN_COMPLETE), + FSP_ERR_ETHER_PHY_NOT_READY); + + /* Get the link partner response */ + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_AN_LINK_PARTNER, ®); + + /* Establish partner pause capability */ + if (ETHER_PHY_AN_LINK_PARTNER_PAUSE == (reg & ETHER_PHY_AN_LINK_PARTNER_PAUSE)) + { + (*p_partner_pause) = (1 << 1); + } + + if (ETHER_PHY_AN_LINK_PARTNER_ASM_DIR == (reg & ETHER_PHY_AN_LINK_PARTNER_ASM_DIR)) + { + (*p_partner_pause) |= 1; + } + + /* Establish the line speed and the duplex */ + if ((ETHER_PHY_AN_LINK_PARTNER_10H == (reg & ETHER_PHY_AN_LINK_PARTNER_10H)) && + ether_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_10H)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_10H; + } + + if ((ETHER_PHY_AN_LINK_PARTNER_10F == (reg & ETHER_PHY_AN_LINK_PARTNER_10F)) && + ether_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_10F)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_10F; + } + + if ((ETHER_PHY_AN_LINK_PARTNER_100H == (reg & ETHER_PHY_AN_LINK_PARTNER_100H)) && + ether_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_100H)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_100H; + } + + if ((ETHER_PHY_AN_LINK_PARTNER_100F == (reg & ETHER_PHY_AN_LINK_PARTNER_100F)) && + ether_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_100F)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_100F; + } + + if (ETHER_PHY_LINK_SPEED_NO_LINK == line_speed_duplex) + { + err = FSP_ERR_ETHER_PHY_ERROR_LINK; + } + else + { + (*p_line_speed_duplex) = line_speed_duplex; + } + + return err; +} /* End of function R_ETHER_PHY_LinkPartnerAbilityGet() */ + +/********************************************************************************************************************//** + * @brief Returns the status of the physical link. Implements @ref ether_phy_api_t::linkStatusGet. + * + * @retval FSP_SUCCESS ETHER_PHY successfully get link partner ability. + * @retval FSP_ERR_ASSERTION Pointer to ETHER_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK PHY-LSI is not link up. + * @retval FSP_ERR_INVALID_ARGUMENT Status register address is incorrect + * @retval FSP_ERR_INVALID_POINTER Pointer to read buffer is NULL. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_PHY_LinkStatusGet (ether_phy_ctrl_t * const p_ctrl) +{ + ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg; + fsp_err_t err = FSP_SUCCESS; + +#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* Because reading the first time shows the previous state, the Link status bit is read twice. */ + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_STATUS, ®); + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_STATUS, ®); + + /* When the link isn't up, return error */ + if (ETHER_PHY_STATUS_LINK_UP != (reg & ETHER_PHY_STATUS_LINK_UP)) + { + /* Link is down */ + err = FSP_ERR_ETHER_PHY_ERROR_LINK; + } + else + { + /* Link is up */ + err = FSP_SUCCESS; + } + + return err; +} /* End of function R_ETHER_PHY_LinkStatusGet() */ + +/********************************************************************************************************************//** + * @brief Initialize Ethernet PHY device. Implements @ref ether_phy_api_t::chipInit. + * + * @retval FSP_SUCCESS PHY device initialized successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER_PHY control block or configuration structure is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Address or data is not a valid size. + * @retval FSP_ERR_INVALID_POINTER Pointer to p_cfg is NULL. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_TIMEOUT PHY-LSI Reset wait timeout. + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_PHY_ChipInit (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + uint32_t count = 0; + +#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_PHY_ERROR_RETURN(NULL != p_cfg, FSP_ERR_INVALID_POINTER); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->interface_status = ETHER_PHY_INTERFACE_STATUS_INITIALIZED; + + /* Reset PHY */ + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_CONTROL, ETHER_PHY_CONTROL_RESET); + + /* Reset completion waiting */ + do + { + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_CONTROL, ®); + count++; + } while ((reg & ETHER_PHY_CONTROL_RESET) && (count < p_cfg->phy_reset_wait_time)); + + if (count < p_cfg->phy_reset_wait_time) + { + ether_phy_targets_initialize(p_instance_ctrl); + + err = FSP_SUCCESS; + } + else + { + err = FSP_ERR_TIMEOUT; + } + + return err; +} /* End of function R_ETHER_PHY_ChipInit() */ + +/********************************************************************************************************************//** + * @brief Read data from register of PHY-LSI . Implements @ref ether_phy_api_t::read. + * + * @retval FSP_SUCCESS ETHER_PHY successfully read data. + * @retval FSP_ERR_ASSERTION Pointer to ETHER_PHY control block is NULL. + * @retval FSP_ERR_INVALID_POINTER Pointer to read buffer is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Address is not a valid size + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_PHY_Read (ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data) +{ + ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl; + uint32_t data; +#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_PHY_ERROR_RETURN(NULL != p_data, FSP_ERR_INVALID_POINTER); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_ADDRESS_SIZE >= reg_addr, FSP_ERR_INVALID_ARGUMENT); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* + * The value is read from the PHY register by the frame format of MII Management Interface provided + * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2. + */ + ether_phy_preamble(p_instance_ctrl); + ether_phy_reg_set(p_instance_ctrl, reg_addr, ETHER_PHY_MII_READ); + ether_phy_trans_zto0(p_instance_ctrl); + ether_phy_reg_read(p_instance_ctrl, &data); + ether_phy_trans_idle(p_instance_ctrl); + + (*p_data) = data; + + return FSP_SUCCESS; +} /* End of function R_ETHER_PHY_Read() */ + +/********************************************************************************************************************//** + * @brief Write data to register of PHY-LSI . Implements @ref ether_phy_api_t::write. + * + * @retval FSP_SUCCESS ETHER_PHY successfully write data. + * @retval FSP_ERR_ASSERTION Pointer to ETHER_PHY control block is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Address or data is not a valid size + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHER_PHY_Write (ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data) +{ + ether_phy_instance_ctrl_t * p_instance_ctrl = (ether_phy_instance_ctrl_t *) p_ctrl; + +#if (ETHER_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_ADDRESS_SIZE >= reg_addr, FSP_ERR_INVALID_ARGUMENT); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_REGISTER_DATA_SIZE >= data, FSP_ERR_INVALID_ARGUMENT); + ETHER_PHY_ERROR_RETURN(ETHER_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* + * The value is read from the PHY register by the frame format of MII Management Interface provided + * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2. + */ + ether_phy_preamble(p_instance_ctrl); + ether_phy_reg_set(p_instance_ctrl, reg_addr, ETHER_PHY_MII_WRITE); + ether_phy_trans_1to0(p_instance_ctrl); + ether_phy_reg_write(p_instance_ctrl, data); + ether_phy_trans_idle(p_instance_ctrl); + + return FSP_SUCCESS; +} /* End of function R_ETHER_PHY_Write() */ + +/*******************************************************************************************************************//** + * @} (end addtogroup ETHER_PHY) + **********************************************************************************************************************/ + +/** + * Private functions + */ + +/*********************************************************************************************************************** + * Function Name: phy_preamble + * Description : As preliminary preparation for access to the PHY module register, + * "1" is output via the MII management interface. + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_preamble (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + int16_t i; + + /* + * The processing of PRE (preamble) about the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + i = ETHER_PHY_PREAMBLE_LENGTH; + while (i > 0) + { + ether_phy_mii_write1(p_instance_ctrl); + i--; + } +} /* End of function ether_phy_preamble() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_reg_set + * Description : Sets a PHY device to read or write mode + * Arguments : ether_channel - + * Ethernet channel number + * reg_addr - + * address of the PHY register + * option - + * mode + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_reg_set (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t reg_addr, int32_t option) +{ + int32_t i; + uint32_t data = 0; + ether_phy_extended_cfg_t * p_extend = (ether_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + + /* + * The processing of ST (start of frame),OP (operation code), PHYAD (PHY Address), and + * REGAD (Register Address) about the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + data = (ETHER_PHY_MII_ST << 14); /* ST code */ + + if (ETHER_PHY_MII_READ == option) + { + data |= (ETHER_PHY_MII_READ << 12); /* OP code(RD) */ + } + else + { + data |= (ETHER_PHY_MII_WRITE << 12); /* OP code(WT) */ + } + + data |= (uint32_t) (p_extend->p_phy_lsi_cfg_list[0]->address << 7); /* PHY Address */ + + data |= (reg_addr << 2); /* Reg Address */ + + i = 14; + while (i > 0) + { + if (0 == (data & ETHER_PHY_WRITE_DATA_BIT_MASK)) + { + ether_phy_mii_write0(p_instance_ctrl); + } + else + { + ether_phy_mii_write1(p_instance_ctrl); + } + + data = (data << 1); + i--; + } +} /* End of function ether_phy_reg_set() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_reg_read + * Description : Reads PHY register through MII interface + * Arguments : p_instance_ctrl - + * Ethernet channel number + * pdata - + * pointer to store the data read + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_reg_read (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t * pdata) +{ + int32_t i; + int32_t j; + uint32_t reg_data; + + volatile uint32_t * petherc_pir; + + petherc_pir = p_instance_ctrl->p_reg_pir; + + /* + * The processing of DATA (data) about reading of the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + reg_data = 0; + i = 16; + while (i > 0) + { + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_LOW); + } + + reg_data = (reg_data << 1); + reg_data |= (uint32_t) (((*petherc_pir) & ETHER_PHY_PIR_MDI_MASK) >> 3); /* MDI read */ + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_HIGH); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_HIGH); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_LOW); + } + + i--; + } + + (*pdata) = reg_data; +} /* End of function ether_phy_reg_read() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_reg_write + * Description : Writes to PHY register through MII interface + * Arguments : ether_channel - + * Ethernet channel number + * data - + * value to write + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_reg_write (ether_phy_instance_ctrl_t * p_instance_ctrl, uint32_t data) +{ + int32_t i; + + /* + * The processing of DATA (data) about writing of the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + i = 16; + while (i > 0) + { + if (0 == (data & ETHER_PHY_WRITE_DATA_BIT_MASK)) + { + ether_phy_mii_write0(p_instance_ctrl); + } + else + { + ether_phy_mii_write1(p_instance_ctrl); + } + + i--; + data = (data << 1); + } +} /* End of function ether_phy_reg_write() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_trans_zto0 + * Description : Performs bus release so that PHY can drive data + * : for read operation + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_trans_zto0 (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + /* Release the bus by writing z. */ + ether_phy_mii_writez(p_instance_ctrl); + + /* The PHY will drive the bus to 0. */ + ether_phy_mii_writez(p_instance_ctrl); +} /* End of function ether_phy_trans_zto0() */ + +/*********************************************************************************************************************** + * Function Name: phy_trans_1to0 + * Description : Switches data bus so MII interface can drive data + * : for write operation + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_trans_1to0 (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + /* + * The processing of TA (turnaround) about writing of the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + ether_phy_mii_write1(p_instance_ctrl); + ether_phy_mii_write0(p_instance_ctrl); +} /* End of function ether_phy_trans_1to0() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_trans_idle + * Description : Switches data bus to IDLE state to prepare for the next transfer. + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_trans_idle (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + volatile uint32_t * petherc_pir; + + petherc_pir = p_instance_ctrl->p_reg_pir; + + int64_t count = (int64_t) p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time * 4; + + /* Release the bus for one MDC period. */ + for (int64_t j = count; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_LOW); + } +} + +/*********************************************************************************************************************** + * Function Name: ether_phy_mii_write1 + * Description : Outputs 1 to the MII interface + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_mii_write1 (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + int32_t j; + volatile uint32_t * petherc_pir; + + petherc_pir = p_instance_ctrl->p_reg_pir; + + /* + * The processing of one bit about frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + * The data that 1 is output. + */ + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_HIGH | ETHER_PHY_PIR_MMD_WRITE | ETHER_PHY_PIR_MDC_LOW); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_HIGH | ETHER_PHY_PIR_MMD_WRITE | ETHER_PHY_PIR_MDC_HIGH); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_HIGH | ETHER_PHY_PIR_MMD_WRITE | ETHER_PHY_PIR_MDC_HIGH); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_HIGH | ETHER_PHY_PIR_MMD_WRITE | ETHER_PHY_PIR_MDC_LOW); + } +} /* End of function ether_phy_mii_write1() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_mii_write0 + * Description : Outputs 0 to the MII interface + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_mii_write0 (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + int32_t j; + volatile uint32_t * petherc_pir; + + petherc_pir = p_instance_ctrl->p_reg_pir; + + /* + * The processing of one bit about frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + * The data that 0 is output. + */ + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_WRITE | ETHER_PHY_PIR_MDC_LOW); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_WRITE | ETHER_PHY_PIR_MDC_HIGH); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_WRITE | ETHER_PHY_PIR_MDC_HIGH); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_WRITE | ETHER_PHY_PIR_MDC_LOW); + } +} /* End of function ether_phy_mii_write0() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_mii_writez + * Description : Outputs z to the MII interface + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_mii_writez (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + int32_t j; + + volatile uint32_t * petherc_pir; + + petherc_pir = p_instance_ctrl->p_reg_pir; + + /* + * The processing of one bit about frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + * The data that z is output. + */ + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_LOW); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_HIGH); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_HIGH); + } + + for (j = p_instance_ctrl->p_ether_phy_cfg->mii_bit_access_wait_time; j > 0; j--) + { + (*petherc_pir) = (ETHER_PHY_PIR_MDO_LOW | ETHER_PHY_PIR_MMD_READ | ETHER_PHY_PIR_MDC_LOW); + } +} + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_instance_ctrl - + * Ethernet control block + * Return Value : none + ***********************************************************************************************************************/ +static void ether_phy_targets_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + ether_phy_extended_cfg_t * p_extend = (ether_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + switch (p_extend->p_phy_lsi_cfg_list[0]->type) + { + /* Use KSZ8091RNB */ +#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) + case ETHER_PHY_LSI_TYPE_KSZ8091RNB: + { + ether_phy_target_ksz8091rnb_initialize(p_instance_ctrl); + break; + } +#endif + + /* Use KSZ8041 */ +#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) + case ETHER_PHY_LSI_TYPE_KSZ8041: + { + ether_phy_target_ksz8041_initialize(p_instance_ctrl); + break; + } +#endif + + /* Use DP83620 */ +#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) + case ETHER_PHY_LSI_TYPE_DP83620: + { + ether_phy_target_dp83620_initialize(p_instance_ctrl); + break; + } +#endif + + /* Use ICS1894 */ +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + case ETHER_PHY_LSI_TYPE_ICS1894: + { + ether_phy_target_ics1894_initialize(p_instance_ctrl); + break; + } +#endif + + /* User custom */ +#if (ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE) + case ETHER_PHY_LSI_TYPE_CUSTOM: + { + if (NULL != p_instance_ctrl->p_ether_phy_cfg->p_extend) + { + ether_phy_extended_cfg_t const * p_callback = p_instance_ctrl->p_ether_phy_cfg->p_extend; + if (NULL != p_callback->p_target_init) + { + p_callback->p_target_init(p_instance_ctrl); + } + } + + break; + } +#endif + + /* If module is configured for default LSI */ + default: + { + break; + } + } +} /* End of function ether_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +static bool ether_phy_targets_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + bool result = false; + ether_phy_extended_cfg_t * p_extend = (ether_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + FSP_PARAMETER_NOT_USED(line_speed_duplex); + switch (p_extend->p_phy_lsi_cfg_list[0]->type) + { + /* Use KSZ8091RNB */ +#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) + case ETHER_PHY_LSI_TYPE_KSZ8091RNB: + { + result = ether_phy_target_ksz8091rnb_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* Use KSZ8041 */ +#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) + case ETHER_PHY_LSI_TYPE_KSZ8041: + { + result = ether_phy_target_ksz8041_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* Use DP83620 */ +#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) + case ETHER_PHY_LSI_TYPE_DP83620: + { + result = ether_phy_target_dp83620_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* Use ICS1894 */ +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + case ETHER_PHY_LSI_TYPE_ICS1894: + { + result = ether_phy_target_ics1894_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* User custom */ +#if (ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE) + case ETHER_PHY_LSI_TYPE_CUSTOM: + { + if (NULL != p_instance_ctrl->p_ether_phy_cfg->p_extend) + { + ether_phy_extended_cfg_t const * p_callback = p_instance_ctrl->p_ether_phy_cfg->p_extend; + if (NULL != p_callback->p_target_link_partner_ability_get) + { + result = p_callback->p_target_link_partner_ability_get(p_instance_ctrl, line_speed_duplex); + } + } + + break; + } +#endif + + /* If module is configured for default LSI, always return true */ + default: + { + result = true; + break; + } + } + + return result; +} /* End of function ether_phy_targets_is_support_link_partner_ability() */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c new file mode 100644 index 0000000000..14646bc520 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c @@ -0,0 +1,94 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_ether_phy.h" + +#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define ETHER_PHY_REG_PAGE_SELECT (0x13) + #define ETHER_PHY_REG_14H (0x14) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void ether_phy_target_dp83620_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +bool ether_phy_target_dp83620_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_api_ctrl - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +void ether_phy_target_dp83620_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + if (ETHER_PHY_MII_TYPE_RMII == p_instance_ctrl->p_ether_phy_cfg->mii_type) + { + /* + * The following is the recommended settings for TI to output 50 MHz from CLK_OUT when using Texas Instruments DP83620 + * in RMII master mode. + */ + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PAGE_SELECT, 0x0006); + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_14H, ®); + if (0x800A == reg) + { + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_14H, 0x000A); + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PAGE_SELECT, 0x0000); + } + } +} /* End of function ether_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool ether_phy_target_dp83620_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(line_speed_duplex); + + /* This PHY-LSI supports half and full duplex mode. */ + return true; +} /* End of function ether_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_DP83620_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c new file mode 100644 index 0000000000..d34cb9c697 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_ether_phy.h" + +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define ETHER_PHY_REG_PHY_CONTROL_20 (0x14) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void ether_phy_target_ics1894_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +bool ether_phy_target_ics1894_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_instance_ctrl - + * Ethernet control block + * Return Value : none + ***********************************************************************************************************************/ +void ether_phy_target_ics1894_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + /* + * When ICS1894NL of the the Renesas Electronics Corporation. is used, + * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. + * The setting of the pin is changed so that only the state of LINK is output. + */ + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_20, ®); + reg |= 0x0007U; + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_20, reg); +} /* End of function ether_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool ether_phy_target_ics1894_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + bool ret = false; + + /* This PHY-LSI only supports full duplex mode. */ + switch (line_speed_duplex) + { + /* 10Mbps full duplex */ + case ETHER_PHY_LINK_SPEED_10F: + { + ret = true; + break; + } + + /* 100Mbps full duplex */ + case ETHER_PHY_LINK_SPEED_100F: + { + ret = true; + break; + } + + /* Half duplex is not supported */ + default: + { + break; + } + } + + return ret; +} /* End of function ether_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_ICS1894_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c new file mode 100644 index 0000000000..e7eeafbd75 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c @@ -0,0 +1,91 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_ether_phy.h" + +#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define ETHER_PHY_REG_PHY_CONTROL_1 (0x1E) + + #define ETHER_PHY_LED_MODE_LED0_LINK_LED1_ACTIVITY (0x4000U) + #define ETHER_PHY_LED_MODE_MASK (0xC000U) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void ether_phy_target_ksz8041_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +bool ether_phy_target_ksz8041_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_api_ctrl - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +void ether_phy_target_ksz8041_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + /* + * When KSZ8041NL of the Micrel, Inc. is used, + * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. + * The setting of the pin is changed so that only the state of LINK is output. + */ + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_1, ®); + reg &= ~ETHER_PHY_LED_MODE_MASK; + reg |= ETHER_PHY_LED_MODE_LED0_LINK_LED1_ACTIVITY; + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL_1, reg); +} /* End of function ether_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool ether_phy_target_ksz8041_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(line_speed_duplex); + + /* This PHY-LSI supports half and full duplex mode. */ + return true; +} /* End of function ether_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c new file mode 100644 index 0000000000..4b4253a566 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c @@ -0,0 +1,105 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_ether_phy.h" + +#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define ETHER_PHY_REG_INTERRUPT_CONTROL (0x1B) + #define ETHER_PHY_REG_PHY_CONTROL2 (0x1F) + + #define ETHER_PHY_REG_INTERRUPT_CONTROL_LUIE_OFFSET (0x8) + #define ETHER_PHY_REG_INTERRUPT_CONTROL_LDIE_OFFSET (0xA) + #define ETHER_PHY_REG_PHY_CONTROL2_RMII_RCS_OFFSET (0x7) + #define ETHER_PHY_REG_PHY_CONTROL2_RMII_IL_OFFSET (0x9) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void ether_phy_target_ksz8091rnb_initialize(ether_phy_instance_ctrl_t * p_instance_ctrl); +bool ether_phy_target_ksz8091rnb_is_support_link_partner_ability(ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_api_ctrl - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +void ether_phy_target_ksz8091rnb_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + /* When KSZ8091RNB of the Micrel, Inc. is used. + * This processing is a setting to use Link -up and Link-down as a factor of INTPR. + * b10=1:Enable link-down interrupt + * b8=1 :Enable link-up interrupt + */ + R_ETHER_PHY_Write(p_instance_ctrl, + ETHER_PHY_REG_INTERRUPT_CONTROL, + (0x1 << ETHER_PHY_REG_INTERRUPT_CONTROL_LUIE_OFFSET | 0x1 << + ETHER_PHY_REG_INTERRUPT_CONTROL_LDIE_OFFSET)); + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_INTERRUPT_CONTROL, ®); + R_ETHER_PHY_Read(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL2, ®); + + /* b7=1:RMII 50MHz clock mode; clock input to XI(pin 9) is 50MHz */ + #if (ETHER_PHY_CFG_USE_REF_CLK == 0) + reg |= (0x1 << ETHER_PHY_REG_PHY_CONTROL2_RMII_RCS_OFFSET); + #endif + + /* b9=0:Interrupt pin active low */ + reg &= (uint16_t) ~(0x1 << ETHER_PHY_REG_PHY_CONTROL2_RMII_IL_OFFSET); + R_ETHER_PHY_Write(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL2, reg); +} /* End of function ether_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: ether_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool ether_phy_target_ksz8091rnb_is_support_link_partner_ability (ether_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(line_speed_duplex); + + /* This PHY-LSI supports half and full duplex mode. */ + return true; +} /* End of function ether_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ethercat_phy/r_ethercat_phy.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ethercat_phy/r_ethercat_phy.c new file mode 100644 index 0000000000..32031679bc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ethercat_phy/r_ethercat_phy.c @@ -0,0 +1,744 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_ethercat_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +#ifndef ETHERCAT_PHY_ERROR_RETURN + #define ETHERCAT_PHY_ERROR_RETURN(a, err) FSP_ERROR_RETURN((a), (err)) +#endif + +/** "ECPH" in ASCII. Used to determine if the control block is open. */ +#define ETHERCAT_PHY_OPEN (('C' << 24U) | ('P' << 16U) | ('H' << 8U) | ('Y' << 0U)) + +/* Standard PHY Registers */ +#define ETHERCAT_PHY_REG_CONTROL (0) +#define ETHERCAT_PHY_REG_STATUS (1) +#define ETHERCAT_PHY_REG_IDENTIFIER1 (2) +#define ETHERCAT_PHY_REG_IDENTIFIER2 (3) +#define ETHERCAT_PHY_REG_AN_ADVERTISEMENT (4) +#define ETHERCAT_PHY_REG_AN_LINK_PARTNER (5) +#define ETHERCAT_PHY_REG_AN_EXPANSION (6) +#define ETHERCAT_PHY_REG_GIGABIT_CONTROL (9) + +/* Basic Mode Control Register Bit Definitions */ +#define ETHERCAT_PHY_CONTROL_RESET (1 << 15) +#define ETHERCAT_PHY_CONTROL_LOOPBACK (1 << 14) +#define ETHERCAT_PHY_CONTROL_100_MBPS (1 << 13) +#define ETHERCAT_PHY_CONTROL_AN_ENABLE (1 << 12) +#define ETHERCAT_PHY_CONTROL_POWER_DOWN (1 << 11) +#define ETHERCAT_PHY_CONTROL_ISOLATE (1 << 10) +#define ETHERCAT_PHY_CONTROL_AN_RESTART (1 << 9) +#define ETHERCAT_PHY_CONTROL_FULL_DUPLEX (1 << 8) +#define ETHERCAT_PHY_CONTROL_COLLISION (1 << 7) + +/* Basic Mode Status Register Bit Definitions */ +#define ETHERCAT_PHY_STATUS_100_T4 (1 << 15) +#define ETHERCAT_PHY_STATUS_100F (1 << 14) +#define ETHERCAT_PHY_STATUS_100H (1 << 13) +#define ETHERCAT_PHY_STATUS_10F (1 << 12) +#define ETHERCAT_PHY_STATUS_10H (1 << 11) +#define ETHERCAT_PHY_STATUS_AN_COMPLETE (1 << 5) +#define ETHERCAT_PHY_STATUS_RM_FAULT (1 << 4) +#define ETHERCAT_PHY_STATUS_AN_ABILITY (1 << 3) +#define ETHERCAT_PHY_STATUS_LINK_UP (1 << 2) +#define ETHERCAT_PHY_STATUS_JABBER (1 << 1) +#define ETHERCAT_PHY_STATUS_EX_CAPABILITY (1 << 0) + +/* Auto Negotiation Advertisement Bit Definitions */ +#define ETHERCAT_PHY_AN_ADVERTISEMENT_NEXT_PAGE (1 << 15) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_RM_FAULT (1 << 13) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_ASM_DIR (1 << 11) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_PAUSE (1 << 10) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_100_T4 (1 << 9) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_100F (1 << 8) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_100H (1 << 7) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_10F (1 << 6) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_10H (1 << 5) +#define ETHERCAT_PHY_AN_ADVERTISEMENT_SELECTOR (1 << 0) + +/* Auto Negotiate Link Partner Ability Bit Definitions */ +#define ETHERCAT_PHY_AN_LINK_PARTNER_NEXT_PAGE (1 << 15) +#define ETHERCAT_PHY_AN_LINK_PARTNER_ACK (1 << 14) +#define ETHERCAT_PHY_AN_LINK_PARTNER_RM_FAULT (1 << 13) +#define ETHERCAT_PHY_AN_LINK_PARTNER_ASM_DIR (1 << 11) +#define ETHERCAT_PHY_AN_LINK_PARTNER_PAUSE (1 << 10) +#define ETHERCAT_PHY_AN_LINK_PARTNER_100_T4 (1 << 9) +#define ETHERCAT_PHY_AN_LINK_PARTNER_100F (1 << 8) +#define ETHERCAT_PHY_AN_LINK_PARTNER_100H (1 << 7) +#define ETHERCAT_PHY_AN_LINK_PARTNER_10F (1 << 6) +#define ETHERCAT_PHY_AN_LINK_PARTNER_10H (1 << 5) +#define ETHERCAT_PHY_AN_LINK_PARTNER_SELECTOR (1 << 0) + +#define ETHERCAT_PHY_PIR_MDI_MASK (1 << 3) +#define ETHERCAT_PHY_PIR_MDO_HIGH (0x04) +#define ETHERCAT_PHY_PIR_MDO_LOW (0x00) +#define ETHERCAT_PHY_PIR_MMD_WRITE (0x02) +#define ETHERCAT_PHY_PIR_MMD_READ (0x00) +#define ETHERCAT_PHY_PIR_MDC_HIGH (0x01) +#define ETHERCAT_PHY_PIR_MDC_LOW (0x00) + +/* Gigabit Control Bit Definitions */ +#define ETHERCAT_PHY_GIGABIT_CONTROL_1000F (1 << 9) +#define ETHERCAT_PHY_GIGABIT_CONTROL_1000H (1 << 8) + +#define ETHERCAT_PHY_ADDRESS_SIZE (0x1fU) +#define ETHERCAT_PHY_REGISTER_DATA_SIZE (0xffffU) + +#define ETHERCAT_PHY_MII_CONT_STAT_READ_COMMAND (1) +#define ETHERCAT_PHY_MII_CONT_STAT_WRITE_COMMAND (2) +#define ETHERCAT_PHY_ERROR_DATA (0xffff) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) +extern void ethercat_phy_target_ics1894_initialize(ethercat_phy_instance_ctrl_t * p_instance_ctrl); +extern bool ethercat_phy_target_ics1894_is_support_link_partner_ability(ethercat_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ +static void ethercat_phy_targets_initialize(ethercat_phy_instance_ctrl_t * p_instance_ctrl); +static bool ethercat_phy_targets_is_support_link_partner_ability(ethercat_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/** ETHERCAT_PHY HAL API mapping for Ethercat PHY Controller interface */ +/*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */ +const ether_phy_api_t g_ether_phy_on_ethercat_phy = +{ + .open = R_ETHERCAT_PHY_Open, + .close = R_ETHERCAT_PHY_Close, + .startAutoNegotiate = R_ETHERCAT_PHY_StartAutoNegotiate, + .linkPartnerAbilityGet = R_ETHERCAT_PHY_LinkPartnerAbilityGet, + .linkStatusGet = R_ETHERCAT_PHY_LinkStatusGet, + .chipInit = R_ETHERCAT_PHY_ChipInit, + .read = R_ETHERCAT_PHY_Read, + .write = R_ETHERCAT_PHY_Write +}; + +/*******************************************************************************************************************//** + * @addtogroup ETHERCAT_PHY + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/********************************************************************************************************************//** + * @brief Resets Ethercat PHY device. Implements @ref ether_phy_api_t::open. + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHERCAT_PHY control block or configuration structure is NULL. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_CHANNEL Invalid channel number is given. + * @retval FSP_ERR_INVALID_POINTER Pointer to p_cfg is NULL. + ***********************************************************************************************************************/ +fsp_err_t R_ETHERCAT_PHY_Open (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + ethercat_phy_instance_ctrl_t * p_instance_ctrl = (ethercat_phy_instance_ctrl_t *) p_ctrl; + +#if (ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHERCAT_PHY_ERROR_RETURN(NULL != p_cfg, FSP_ERR_INVALID_POINTER); + ETHERCAT_PHY_ERROR_RETURN((ETHERCAT_PHY_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN); + ETHERCAT_PHY_ERROR_RETURN((BSP_FEATURE_ETHER_NUM_CHANNELS > p_cfg->channel), FSP_ERR_INVALID_CHANNEL); +#endif + + /* Initialize configuration of ethernet phy module. */ + p_instance_ctrl->p_ether_phy_cfg = p_cfg; + + p_instance_ctrl->local_advertise = 0; + + /* Configure pins for MII or RMII. Set PHYMODE0 if MII is selected. */ + R_PMISC->PFENET = + (uint8_t) ((ETHER_PHY_MII_TYPE_MII == p_cfg->mii_type) << (R_PMISC_PFENET_PHYMODE0_Pos + p_cfg->channel)); + + p_instance_ctrl->open = ETHERCAT_PHY_OPEN; + + return err; +} /* End of function R_ETHERCAT_PHY_Open() */ + +/********************************************************************************************************************//** + * @brief Close Ethercat PHY device. Implements @ref ether_phy_api_t::close. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to ETHERCAT_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * + ***********************************************************************************************************************/ +fsp_err_t R_ETHERCAT_PHY_Close (ether_phy_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + ethercat_phy_instance_ctrl_t * p_instance_ctrl = (ethercat_phy_instance_ctrl_t *) p_ctrl; + +#if (ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /** Clear configure block parameters. */ + p_instance_ctrl->p_ether_phy_cfg = NULL; + p_instance_ctrl->local_advertise = 0; + p_instance_ctrl->interface_status = ETHERCAT_PHY_INTERFACE_STATUS_UNINITIALIZED; + p_instance_ctrl->open = 0; + + return err; +} /* End of function R_ETHERCAT_PHY_Close() */ + +/********************************************************************************************************************//** + * @brief Starts auto-negotiate. Implements @ref ether_phy_api_t::startAutoNegotiate. + * + * @retval FSP_SUCCESS ETHERCAT_PHY successfully starts auto-negotiate. + * @retval FSP_ERR_ASSERTION Pointer to ETHERCAT_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Register address is incorrect + * @retval FSP_ERR_INVALID_MODE Command is invalid. + * @retval FSP_ERR_INVALID_POINTER Pointer to read buffer is NULL. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHERCAT_PHY_StartAutoNegotiate (ether_phy_ctrl_t * const p_ctrl) +{ + ethercat_phy_instance_ctrl_t * p_instance_ctrl = (ethercat_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + +#if (ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* Set local ability */ + /* When pause frame is not used */ + if (ETHER_PHY_FLOW_CONTROL_DISABLE == p_instance_ctrl->p_ether_phy_cfg->flow_control) + { + p_instance_ctrl->local_advertise = ((((ETHERCAT_PHY_AN_ADVERTISEMENT_100F | + ETHERCAT_PHY_AN_ADVERTISEMENT_100H) | + ETHERCAT_PHY_AN_ADVERTISEMENT_10F) | + ETHERCAT_PHY_AN_ADVERTISEMENT_10H) | + ETHERCAT_PHY_AN_ADVERTISEMENT_SELECTOR); + } + /* When pause frame is used */ + else + { + p_instance_ctrl->local_advertise = ((((((ETHERCAT_PHY_AN_ADVERTISEMENT_ASM_DIR | + ETHERCAT_PHY_AN_ADVERTISEMENT_PAUSE) | + ETHERCAT_PHY_AN_ADVERTISEMENT_100F) | + ETHERCAT_PHY_AN_ADVERTISEMENT_100H) | + ETHERCAT_PHY_AN_ADVERTISEMENT_10F) | + ETHERCAT_PHY_AN_ADVERTISEMENT_10H) | + ETHERCAT_PHY_AN_ADVERTISEMENT_SELECTOR); + } + + /* Configure what the PHY and the Ethernet controller on this board supports */ + R_ETHERCAT_PHY_Write(p_instance_ctrl, ETHERCAT_PHY_REG_AN_ADVERTISEMENT, p_instance_ctrl->local_advertise); + + /* Advertise Gigabit Ethernet capacity when using RGMII or GMII. */ + if ((ETHER_PHY_MII_TYPE_RGMII == p_instance_ctrl->p_ether_phy_cfg->mii_type) || + (ETHER_PHY_MII_TYPE_GMII == p_instance_ctrl->p_ether_phy_cfg->mii_type)) + { + R_ETHERCAT_PHY_Write(p_instance_ctrl, ETHERCAT_PHY_REG_GIGABIT_CONTROL, + (ETHERCAT_PHY_GIGABIT_CONTROL_1000F | ETHERCAT_PHY_GIGABIT_CONTROL_1000H)); + } + + /* Start auto-negotiation. */ + R_ETHERCAT_PHY_Write(p_instance_ctrl, + ETHERCAT_PHY_REG_CONTROL, + (ETHERCAT_PHY_CONTROL_AN_ENABLE | + ETHERCAT_PHY_CONTROL_AN_RESTART)); + + R_ETHERCAT_PHY_Read(p_instance_ctrl, ETHERCAT_PHY_REG_AN_ADVERTISEMENT, ®); + + return FSP_SUCCESS; +} /* End of function R_ETHERCAT_PHY_StartAutoNegotiate() */ + +/********************************************************************************************************************//** + * @brief Reports the other side's physical capability. Implements @ref ether_phy_api_t::linkPartnerAbilityGet. + * + * @retval FSP_SUCCESS ETHERCAT_PHY successfully get link partner ability. + * @retval FSP_ERR_ASSERTION Pointer to ETHERCAT_PHY control block is NULL. + * @retval FSP_ERR_INVALID_POINTER Pointer to arguments are NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK PHY-LSI is not link up. + * @retval FSP_ERR_ETHER_PHY_NOT_READY The auto-negotiation isn't completed + * @retval FSP_ERR_INVALID_ARGUMENT Status register address is incorrect + * @retval FSP_ERR_INVALID_MODE Command is invalid. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHERCAT_PHY_LinkPartnerAbilityGet (ether_phy_ctrl_t * const p_ctrl, + uint32_t * const p_line_speed_duplex, + uint32_t * const p_local_pause, + uint32_t * const p_partner_pause) +{ + fsp_err_t err = FSP_SUCCESS; + ethercat_phy_instance_ctrl_t * p_instance_ctrl = (ethercat_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + uint32_t line_speed_duplex = ETHER_PHY_LINK_SPEED_NO_LINK; + +#if (ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHERCAT_PHY_ERROR_RETURN(NULL != p_line_speed_duplex, FSP_ERR_INVALID_POINTER); + ETHERCAT_PHY_ERROR_RETURN(NULL != p_local_pause, FSP_ERR_INVALID_POINTER); + ETHERCAT_PHY_ERROR_RETURN(NULL != p_partner_pause, FSP_ERR_INVALID_POINTER); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* Because reading the first time shows the previous state, the Link status bit is read twice. */ + R_ETHERCAT_PHY_Read(p_instance_ctrl, ETHERCAT_PHY_REG_STATUS, ®); + R_ETHERCAT_PHY_Read(p_instance_ctrl, ETHERCAT_PHY_REG_STATUS, ®); + + /* When the link isn't up, return error */ + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_STATUS_LINK_UP == (reg & ETHERCAT_PHY_STATUS_LINK_UP), + FSP_ERR_ETHER_PHY_ERROR_LINK); + + /* Establish local pause capability */ + if (ETHERCAT_PHY_AN_ADVERTISEMENT_PAUSE == (p_instance_ctrl->local_advertise & ETHERCAT_PHY_AN_ADVERTISEMENT_PAUSE)) + { + (*p_local_pause) |= (1 << 1); + } + + if (ETHERCAT_PHY_AN_ADVERTISEMENT_ASM_DIR == + (p_instance_ctrl->local_advertise & ETHERCAT_PHY_AN_ADVERTISEMENT_ASM_DIR)) + { + (*p_local_pause) |= 1; + } + + /* When the auto-negotiation isn't completed, return error */ + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_STATUS_AN_COMPLETE == (reg & ETHERCAT_PHY_STATUS_AN_COMPLETE), + FSP_ERR_ETHER_PHY_NOT_READY); + + /* Get the link partner response */ + R_ETHERCAT_PHY_Read(p_instance_ctrl, ETHERCAT_PHY_REG_AN_LINK_PARTNER, ®); + + /* Establish partner pause capability */ + if (ETHERCAT_PHY_AN_LINK_PARTNER_PAUSE == (reg & ETHERCAT_PHY_AN_LINK_PARTNER_PAUSE)) + { + (*p_partner_pause) = (1 << 1); + } + + if (ETHERCAT_PHY_AN_LINK_PARTNER_ASM_DIR == (reg & ETHERCAT_PHY_AN_LINK_PARTNER_ASM_DIR)) + { + (*p_partner_pause) |= 1; + } + + /* Establish the line speed and the duplex */ + if ((ETHERCAT_PHY_AN_LINK_PARTNER_10H == (reg & ETHERCAT_PHY_AN_LINK_PARTNER_10H)) && + ethercat_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_10H)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_10H; + } + + if ((ETHERCAT_PHY_AN_LINK_PARTNER_10F == (reg & ETHERCAT_PHY_AN_LINK_PARTNER_10F)) && + ethercat_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_10F)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_10F; + } + + if ((ETHERCAT_PHY_AN_LINK_PARTNER_100H == (reg & ETHERCAT_PHY_AN_LINK_PARTNER_100H)) && + ethercat_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_100H)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_100H; + } + + if ((ETHERCAT_PHY_AN_LINK_PARTNER_100F == (reg & ETHERCAT_PHY_AN_LINK_PARTNER_100F)) && + ethercat_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_100F)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_100F; + } + + /* When MII type is RGMII, check also Gigabit Ethernet ability. */ + if ((ETHER_PHY_MII_TYPE_RGMII == p_instance_ctrl->p_ether_phy_cfg->mii_type) || + (ETHER_PHY_MII_TYPE_GMII == p_instance_ctrl->p_ether_phy_cfg->mii_type)) + { + R_ETHERCAT_PHY_Read(p_instance_ctrl, ETHERCAT_PHY_REG_GIGABIT_CONTROL, ®); + + if ((ETHERCAT_PHY_GIGABIT_CONTROL_1000H == (reg & ETHERCAT_PHY_GIGABIT_CONTROL_1000H)) && + ethercat_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_1000H)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_1000H; + } + + if ((ETHERCAT_PHY_GIGABIT_CONTROL_1000F == (reg & ETHERCAT_PHY_GIGABIT_CONTROL_1000F)) && + ethercat_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_1000F)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_1000F; + } + } + + if (ETHER_PHY_LINK_SPEED_NO_LINK == line_speed_duplex) + { + err = FSP_ERR_ETHER_PHY_ERROR_LINK; + } + else + { + (*p_line_speed_duplex) = line_speed_duplex; + } + + return err; +} /* End of function R_ETHERCAT_PHY_LinkPartnerAbilityGet() */ + +/********************************************************************************************************************//** + * @brief Returns the status of the physical link. Implements @ref ether_phy_api_t::linkStatusGet. + * + * @retval FSP_SUCCESS ETHERCAT_PHY successfully get link partner ability. + * @retval FSP_ERR_ASSERTION Pointer to ETHERCAT_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK PHY-LSI is not link up. + * @retval FSP_ERR_INVALID_ARGUMENT Status register address is incorrect + * @retval FSP_ERR_INVALID_MODE Command is invalid. + * @retval FSP_ERR_INVALID_POINTER Pointer to read buffer is NULL. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHERCAT_PHY_LinkStatusGet (ether_phy_ctrl_t * const p_ctrl) +{ + ethercat_phy_instance_ctrl_t * p_instance_ctrl = (ethercat_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + fsp_err_t err = FSP_SUCCESS; + +#if (ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* Because reading the first time shows the previous state, the Link status bit is read twice. */ + R_ETHERCAT_PHY_Read(p_instance_ctrl, ETHERCAT_PHY_REG_STATUS, ®); + R_ETHERCAT_PHY_Read(p_instance_ctrl, ETHERCAT_PHY_REG_STATUS, ®); + + /* When the link isn't up, return error */ + if (ETHERCAT_PHY_STATUS_LINK_UP != (reg & ETHERCAT_PHY_STATUS_LINK_UP)) + { + /* Link is down */ + err = FSP_ERR_ETHER_PHY_ERROR_LINK; + } + else + { + /* Link is up */ + err = FSP_SUCCESS; + } + + return err; +} /* End of function R_ETHERCAT_PHY_LinkStatusGet() */ + +/********************************************************************************************************************//** + * @brief Initialize Ethercat PHY device. Implements @ref ether_phy_api_t::chipInit. + * + * @retval FSP_SUCCESS PHY device initialized successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHERCAT_PHY control block or configuration structure is NULL. + * @retval FSP_ERR_INVALID_POINTER Pointer to p_cfg is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_TIMEOUT PHY-LSI Reset wait timeout. + ***********************************************************************************************************************/ +fsp_err_t R_ETHERCAT_PHY_ChipInit (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + ethercat_phy_instance_ctrl_t * p_instance_ctrl = (ethercat_phy_instance_ctrl_t *) p_ctrl; + uint32_t count = 0; + +#if (ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHERCAT_PHY_ERROR_RETURN(NULL != p_cfg, FSP_ERR_INVALID_POINTER); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->interface_status = ETHERCAT_PHY_INTERFACE_STATUS_INITIALIZED; + + if (count < p_cfg->phy_reset_wait_time) + { + ethercat_phy_targets_initialize(p_instance_ctrl); + } + else + { + err = FSP_ERR_TIMEOUT; + } + + return err; +} /* End of function R_ETHERCAT_PHY_ChipInit() */ + +/********************************************************************************************************************//** + * @brief Read data from register of PHY-LSI . Implements @ref ether_phy_api_t::read. + * + * @retval FSP_SUCCESS ETHERCAT_PHY successfully read data. + * @retval FSP_ERR_ASSERTION Pointer to ETHERCAT_PHY control block is NULL. + * @retval FSP_ERR_INVALID_POINTER Pointer to read buffer is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Address is not a valid size + * @retval FSP_ERR_INVALID_MODE Command is invalid. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHERCAT_PHY_Read (ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data) +{ + ethercat_phy_instance_ctrl_t * p_instance_ctrl = (ethercat_phy_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + R_ESC_Type * p_reg_esc = (R_ESC_Type *) R_ESC_BASE; + +#if (ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHERCAT_PHY_ERROR_RETURN(NULL != p_data, FSP_ERR_INVALID_POINTER); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_ADDRESS_SIZE >= reg_addr, FSP_ERR_INVALID_ARGUMENT); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* If the management interface is busy, wait until it is no longer so. */ + FSP_HARDWARE_REGISTER_WAIT(p_reg_esc->MII_CONT_STAT_b.BUSY, 0U) + + if (FSP_SUCCESS == err) + { + /* Get PDI access right */ + p_reg_esc->MII_PDI_ACS_STAT_b.ACSMII = 1; + + /* Confirm that access rights switch to PDI. */ + FSP_HARDWARE_REGISTER_WAIT(p_reg_esc->MII_ECAT_ACS_STAT_b.ACSMII, 0U) + } + + if (FSP_SUCCESS == err) + { + /* Read PHY register */ + p_reg_esc->PHY_ADR = (uint8_t) R_ESC_PHY_ADR_PHYADDR_Msk & + (p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << R_ESC_PHY_ADR_PHYADDR_Pos); + p_reg_esc->PHY_REG_ADR = (uint8_t) R_ESC_PHY_REG_ADR_PHYREGADDR_Msk & + (reg_addr << R_ESC_PHY_REG_ADR_PHYREGADDR_Pos); + p_reg_esc->MII_CONT_STAT = ETHERCAT_PHY_MII_CONT_STAT_READ_COMMAND << R_ESC_MII_CONT_STAT_COMMAND_Pos; // < Read command + + /* Start read access to the phy register and wait for completion. */ + FSP_HARDWARE_REGISTER_WAIT(p_reg_esc->MII_CONT_STAT_b.BUSY, 0U) + } + + if (FSP_SUCCESS == err) + { + /* Check the error bit */ + if ((p_reg_esc->MII_CONT_STAT & + (R_ESC_MII_CONT_STAT_CMDERR_Msk | R_ESC_MII_CONT_STAT_READERR_Msk))) + { + /* Error operation */ + err = FSP_ERR_INVALID_MODE; + + /* Clear error bit */ + p_reg_esc->MII_CONT_STAT_b.COMMAND = 0x0; + } + } + + if (FSP_SUCCESS == err) + { + /* Get read data */ + *p_data = p_reg_esc->PHY_DATA; + + /* Give the access right to ECAT */ + p_reg_esc->MII_PDI_ACS_STAT_b.ACSMII = 0; + } + else + { + *p_data = ETHERCAT_PHY_ERROR_DATA; + } + + return err; +} /* End of function R_ETHERCAT_PHY_Read() */ + +/********************************************************************************************************************//** + * @brief Write data to register of PHY-LSI . Implements @ref ether_phy_api_t::write. + * + * @retval FSP_SUCCESS ETHERCAT_PHY successfully write data. + * @retval FSP_ERR_ASSERTION Pointer to ETHERCAT_PHY control block is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Address or data is not a valid size + * @retval FSP_ERR_INVALID_MODE Command is invalid. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + ***********************************************************************************************************************/ +fsp_err_t R_ETHERCAT_PHY_Write (ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data) +{ + ethercat_phy_instance_ctrl_t * p_instance_ctrl = (ethercat_phy_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + R_ESC_Type * p_reg_esc = (R_ESC_Type *) R_ESC_BASE; + +#if (ETHERCAT_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_ADDRESS_SIZE >= reg_addr, FSP_ERR_INVALID_ARGUMENT); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_REGISTER_DATA_SIZE >= data, FSP_ERR_INVALID_ARGUMENT); + ETHERCAT_PHY_ERROR_RETURN(ETHERCAT_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* If the management interface is busy, wait until it is no longer so. */ + FSP_HARDWARE_REGISTER_WAIT(p_reg_esc->MII_CONT_STAT_b.BUSY, 0U) + + if (FSP_SUCCESS == err) + { + /* Get PDI access right */ + p_reg_esc->MII_PDI_ACS_STAT_b.ACSMII = 1; + + /* Confirm that access rights switch to PDI. */ + FSP_HARDWARE_REGISTER_WAIT(p_reg_esc->MII_ECAT_ACS_STAT_b.ACSMII, 0U) + } + + if (FSP_SUCCESS == err) + { + /* Write PHY register */ + p_reg_esc->PHY_ADR = (uint8_t) R_ESC_PHY_ADR_PHYADDR_Msk & + (p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << R_ESC_PHY_ADR_PHYADDR_Pos); + p_reg_esc->PHY_REG_ADR = (uint8_t) R_ESC_PHY_REG_ADR_PHYREGADDR_Msk & + (reg_addr << R_ESC_PHY_REG_ADR_PHYREGADDR_Pos); + p_reg_esc->PHY_DATA = (uint16_t) R_ESC_PHY_DATA_PHYREGDATA_Msk & + (data << R_ESC_PHY_DATA_PHYREGDATA_Pos); + p_reg_esc->MII_CONT_STAT = ETHERCAT_PHY_MII_CONT_STAT_WRITE_COMMAND << R_ESC_MII_CONT_STAT_COMMAND_Pos; // < Write command + + /* Start write access to the phy register and wait for completion. */ + FSP_HARDWARE_REGISTER_WAIT(p_reg_esc->MII_CONT_STAT_b.BUSY, 0U) + } + + if (FSP_SUCCESS == err) + { + /* Check the error bit */ + if ((p_reg_esc->MII_CONT_STAT & + R_ESC_MII_CONT_STAT_CMDERR_Msk)) + { + /* Error operation */ + err = FSP_ERR_INVALID_MODE; + + /* Clear error bit */ + p_reg_esc->MII_CONT_STAT_b.COMMAND = 0x0; + } + + /* Give the access right to ECAT */ + p_reg_esc->MII_PDI_ACS_STAT_b.ACSMII = 0; + } + + return err; +} + +/* End of function R_ETHERCAT_PHY_Write() */ + +/*******************************************************************************************************************//** + * @} (end addtogroup ETHERCAT_PHY) + **********************************************************************************************************************/ + +/** + * Private functions + */ + +/*********************************************************************************************************************** + * Function Name: ethercat_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_instance_ctrl - + * Ethercat control block + * Return Value : none + ***********************************************************************************************************************/ +static void ethercat_phy_targets_initialize (ethercat_phy_instance_ctrl_t * p_instance_ctrl) +{ + switch (p_instance_ctrl->p_ether_phy_cfg->phy_lsi_type) + { + /* Use ICS1894 */ +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + case ETHER_PHY_LSI_TYPE_ICS1894: + { + ethercat_phy_target_ics1894_initialize(p_instance_ctrl); + break; + } +#endif + + /* User custom */ +#if (ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE) + case ETHER_PHY_LSI_TYPE_CUSTOM: + { + if (NULL != p_instance_ctrl->p_ether_phy_cfg->p_extend) + { + ether_phy_extended_cfg_t const * p_callback = p_instance_ctrl->p_ether_phy_cfg->p_extend; + if (NULL != p_callback->p_target_init) + { + p_callback->p_target_init(p_instance_ctrl); + } + } + + break; + } +#endif + + /* If module is configured for default LSI */ + default: + { + break; + } + } +} /* End of function ethercat_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: ethercat_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethercat controller supports link ability + * Arguments : p_instance_ctrl - + * Ethercat control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +static bool ethercat_phy_targets_is_support_link_partner_ability (ethercat_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + bool result = false; + FSP_PARAMETER_NOT_USED(line_speed_duplex); + + switch (p_instance_ctrl->p_ether_phy_cfg->phy_lsi_type) + { + /* Use ICS1894 */ +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + case ETHER_PHY_LSI_TYPE_ICS1894: + { + result = ethercat_phy_target_ics1894_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* User custom */ +#if (ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE) + case ETHER_PHY_LSI_TYPE_CUSTOM: + { + if (NULL != p_instance_ctrl->p_ether_phy_cfg->p_extend) + { + ether_phy_extended_cfg_t const * p_callback = p_instance_ctrl->p_ether_phy_cfg->p_extend; + if (NULL != p_callback->p_target_link_partner_ability_get) + { + result = p_callback->p_target_link_partner_ability_get(p_instance_ctrl, line_speed_duplex); + } + } + + break; + } +#endif + + /* If module is configured for default LSI, always return true */ + default: + { + result = true; + break; + } + } + + return result; +} /* End of function ethercat_phy_targets_is_support_link_partner_ability() */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ethercat_phy/targets/ICS1894/r_ethercat_phy_target_ics1894.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ethercat_phy/targets/ICS1894/r_ethercat_phy_target_ics1894.c new file mode 100644 index 0000000000..7b4df1d37c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ethercat_phy/targets/ICS1894/r_ethercat_phy_target_ics1894.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_ethercat_phy.h" + +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define ETHERCAT_PHY_REG_PHY_CONTROL_20 (0x14) + #define ETHERCAT_PHY_CLEAR_LED (0xffc0U) + #define ETHERCAT_PHY_ACTIVATE_LED (0x000dU) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void ethercat_phy_target_ics1894_initialize(ethercat_phy_instance_ctrl_t * p_instance_ctrl); +bool ethercat_phy_target_ics1894_is_support_link_partner_ability(ethercat_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: ethercat_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_instance_ctrl - + * Ethercat control block + * Return Value : none + ***********************************************************************************************************************/ +void ethercat_phy_target_ics1894_initialize (ethercat_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + /* + * When ICS1894NL of the the Renesas Electronics Corporation. is used, + * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. + * The setting of the pin is changed so that only the state of LINK is output. + */ + R_ETHERCAT_PHY_Read(p_instance_ctrl, ETHERCAT_PHY_REG_PHY_CONTROL_20, ®); + reg &= ETHERCAT_PHY_CLEAR_LED; // LED0, LED1 Mode clear + reg |= ETHERCAT_PHY_ACTIVATE_LED; // LED1 Mode = activity/no activity, LED0 Mode = 100/10 mode (speed is used as link) + R_ETHERCAT_PHY_Write(p_instance_ctrl, ETHERCAT_PHY_REG_PHY_CONTROL_20, reg); +} /* End of function ethercat_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: ethercat_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethercat controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool ethercat_phy_target_ics1894_is_support_link_partner_ability (ethercat_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + bool ret = false; + + /* This PHY-LSI only supports full duplex mode. */ + switch (line_speed_duplex) + { + /* 10Mbps full duplex */ + case ETHER_PHY_LINK_SPEED_10F: + { + ret = true; + break; + } + + /* 100Mbps full duplex */ + case ETHER_PHY_LINK_SPEED_100F: + { + ret = true; + break; + } + + /* Half duplex is not supported */ + default: + { + break; + } + } + + return ret; +} /* End of function ethercat_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_ICS1894_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_flash_hp/r_flash_hp.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_flash_hp/r_flash_hp.c new file mode 100644 index 0000000000..2af05f5138 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_flash_hp/r_flash_hp.c @@ -0,0 +1,3420 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include +#include "r_flash_hp.h" + +/* Configuration for this package. */ +#include "r_flash_hp_cfg.h" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * flash_hp_prv_ns_callback)(flash_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile flash_hp_prv_ns_callback)(flash_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define FLASH_HP_FENTRYR_PE_MODE_BITS (0x0081U) +#define FLASH_HP_FSTATR_FLWEERR (1U << 6U) +#define FLASH_HP_FSTATR_PRGERR (1U << 12U) +#define FLASH_HP_FSTATR_ERSERR (1U << 13U) +#define FLASH_HP_FSTATR_ILGLERR (1U << 14U) +#define FLASH_HP_FSTATR_OTERR (1U << 20U) +#define FLASH_HP_FSTATR_SECERR (1U << 21U) +#define FLASH_HP_FSTATR_FESETERR (1U << 22U) +#define FLASH_HP_FSTATR_ILGCOMERR (1U << 23U) + +#define FLASH_HP_FSTATR_ERROR_MASK (FLASH_HP_FSTATR_FLWEERR | FLASH_HP_FSTATR_PRGERR | \ + FLASH_HP_FSTATR_ERSERR | \ + FLASH_HP_FSTATR_ILGLERR | FLASH_HP_FSTATR_OTERR | \ + FLASH_HP_FSTATR_SECERR | \ + FLASH_HP_FSTATR_FESETERR | FLASH_HP_FSTATR_ILGCOMERR) + +/** "OPEN" in ASCII, used to avoid multiple open. */ +#define FLASH_HP_OPEN (0x4f50454eU) +#define FLASH_HP_CLOSE (0U) + +/* Minimum FCLK for Flash Operations in Hz */ +#define FLASH_HP_MINIMUM_SUPPORTED_FCLK_FREQ (4000000U) + +/** The maximum timeout for commands is 100usec when FCLK is 16 MHz i.e. 1600 FCLK cycles. + * Assuming worst case of ICLK at 240 MHz and FCLK at 4 MHz, and optimization set to max such that + * each count decrement loop takes only 5 cycles, then ((240/4)*1600)/5 = 19200 */ +#define FLASH_HP_FRDY_CMD_TIMEOUT (19200) + +/** Time that it would take for the Data Buffer to be empty (DBFULL Flag) is 90 FCLK cycles. + * Assuming worst case of ICLK at 240 MHz and FCLK at 4 MHz, and optimization set to max such that + * each count decrement loop takes only 5 cycles, then ((240/4)*90)/5 = 1080 */ +#define FLASH_HP_DBFULL_TIMEOUT (1080U) + +/** R_FACI Commands */ +#define FLASH_HP_FACI_CMD_PROGRAM (0xE8U) +#define FLASH_HP_FACI_CMD_PROGRAM_CF (0x80U) +#define FLASH_HP_FACI_CMD_PROGRAM_DF (0x02U) +#define FLASH_HP_FACI_CMD_BLOCK_ERASE (0x20U) +#define FLASH_HP_FACI_CMD_PE_SUSPEND (0xB0U) +#define FLASH_HP_FACI_CMD_PE_RESUME (0xD0U) +#define FLASH_HP_FACI_CMD_STATUS_CLEAR (0x50U) +#define FLASH_HP_FACI_CMD_FORCED_STOP (0xB3U) +#define FLASH_HP_FACI_CMD_BLANK_CHECK (0x71U) +#define FLASH_HP_FACI_CMD_CONFIG_SET_1 (0x40U) +#define FLASH_HP_FACI_CMD_CONFIG_SET_2_CF (0x08U) +#define FLASH_HP_FACI_CMD_CONFIG_SET_2_DF (0x02U) +#define FLASH_HP_FACI_CMD_LOCK_BIT_PGM (0x77U) +#define FLASH_HP_FACI_CMD_LOCK_BIT_READ (0x71U) +#define FLASH_HP_FACI_CMD_INCREMENT_COUNTER (0x35U) +#define FLASH_HP_FACI_CMD_REFRESH_COUNTER (0x37U) +#define FLASH_HP_FACI_CMD_READ_COUNTER (0x39U) +#define FLASH_HP_FACI_CMD_FINAL (0xD0U) + +#if (BSP_CFG_MCU_PART_SERIES == 8) + #define FLASH_HP_FCU_CONFIG_SET_DUAL_MODE (0x0300A110U) + #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP (0x0300A130U) + #define FLASH_HP_FCU_CONFIG_SET_BANK_MODE (0x1300A190U) + #define FLASH_HP_FCU_CONFIG_SET_BANK_MODE_SEC (0x0300A210U) + #define FLASH_HP_BANK_MODE_SECURITY_ATTRIBUTION (0x0300A290U) +#else + #if BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW + #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP (0x0000A160U) + #define FLASH_HP_FCU_CONFIG_SET_ID_BYTE (0x0000A150U) + #else + #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP (0x0100A130U) + #define FLASH_HP_FCU_CONFIG_SET_ID_BYTE (0x0000A120U) + #endif + #define FLASH_HP_FCU_CONFIG_SET_DUAL_MODE (0x0100A110U) + #define FLASH_HP_FCU_CONFIG_SET_BANK_MODE (0x0100A190U) + #define FLASH_HP_FCU_CONFIG_SET_BANK_MODE_SEC (0x0100A210U) + #define FLASH_HP_BANK_MODE_SECURITY_ATTRIBUTION (0x0100A290U) +#endif + +/* Zero based offset into g_configuration_area_data[] for FAWS */ +#define FLASH_HP_FCU_CONFIG_SET_FAWS_OFFSET (2U) + +/* Zero based offset into g_configuration_area_data[] for FAWE and BTFLG */ +#define FLASH_HP_FCU_CONFIG_SET_FAWE_BTFLG_OFFSET (3U) + +/* These bits must always be set when writing to the configuration area. */ +#define FLASH_HP_FCU_CONFIG_FAWE_BTFLG_UNUSED_BITS (0x7800U) +#define FLASH_HP_FCU_CONFIG_FAWS_UNUSED_BITS (0xF800U) + +/* 8 words need to be written for code flash */ +#define FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT_CF (8U) + +/* 2 words need to be written for data flash */ +#define FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT_DF (2U) + +#define FLASH_HP_FSUACR_KEY (0x6600U) + +/** Register masks */ +#define FLASH_HP_FPESTAT_NON_LOCK_BIT_PGM_ERROR (0x0002U) // Bits indicating Non Lock Bit related Programming error. +#define FLASH_HP_FPESTAT_NON_LOCK_BIT_ERASE_ERROR (0x0012U) // Bits indicating Non Lock Bit related Erasure error. +#define FLASH_HP_FENTRYR_DF_PE_MODE (0x0080U) // Bits indicating that Data Flash is in P/E mode. +#define FLASH_HP_FENTRYR_CF_PE_MODE (0x0001U) // Bits indicating that CodeFlash is in P/E mode. +#define FLASH_HP_FENTRYR_TRANSITION_TO_CF_PE (0xAA01U) // Key Code to transition to CF P/E mode. +#define FLASH_HP_FENTRYR_TRANSITION_TO_DF_PE (0xAA80U) // Key Code to transition to DF P/E mode. + +#define FLASH_HP_FREQUENCY_IN_HZ (1000000U) + +#define FLASH_HP_FENTRYR_READ_MODE (0xAA00U) + +#define FLASH_HP_FMEPROT_LOCK (0xD901) +#define FLASH_HP_FMEPROT_UNLOCK (0xD900) + +#define FLASH_HP_OFS_SAS_MASK (0x7FFFU) + +#define FLASH_HP_FAEINT_DFAEIE (0x08) +#define FLASH_HP_FAEINT_CMDLKIE (0x10) +#define FLASH_HP_FAEINT_CFAEIE (0x80) +#define FLASH_HP_ERROR_INTERRUPTS_ENABLE (FLASH_HP_FAEINT_DFAEIE | FLASH_HP_FAEINT_CMDLKIE | \ + FLASH_HP_FAEINT_CFAEIE) + +#define FLASH_HP_FPCKAR_KEY (0x1E00U) + +#define FLASH_HP_MAX_WRITE_CF_US (15800) +#define FLASH_HP_MAX_WRITE_DF_US (3800) +#define FLASH_HP_MAX_DBFULL_US (2) +#define FLASH_HP_MAX_BLANK_CHECK_US (84) +#define FLASH_HP_MAX_WRITE_CONFIG_US (512000) +#define FLASH_HP_MAX_ERASE_DF_BLOCK_US (18000) +#define FLASH_HP_MAX_ERASE_CF_LARGE_BLOCK_US (1040000) +#define FLASH_HP_MAX_ERASE_CF_SMALL_BLOCK_US (260000) +#define FLASH_HP_MAX_INCREMENT_REFRESH_COUNTER_US (81000) +#define FLASH_HP_MAX_READ_COUNTER_US (25) + +#define FLASH_HP_FASTAT_DFAE (0x08) +#define FLASH_HP_FASTAT_CFAE (0x80) +#define FLASH_HP_FASTAT_CMDLK (0x10) + +#define FLASH_HP_WAIT_TDSTOP (250U) +#define FLASH_HP_DELAY_LOOP_CYCLES (4U) +#define FLASH_HP_DELAY_NS_PER_US (1000U) + +#if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK + #define FLASH_HP_PRV_DUALSEL_BANKMD_MASK (0x7U) + #define FLASH_HP_PRV_BANKSEL_BANKSWP_MASK (0x7U) + #define FLASH_HP_PRV_BANK1_MASK (~BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START) +#else + #define FLASH_HP_PRV_BANK1_MASK (UINT32_MAX) +#endif + +#define FLASH_HP_PRV_ARCNS_SINGLE (1) // ARCNS setting for single ARC_NSEC counter +#define FLASH_HP_PRV_ARCNS_MULTIPLE (0) // ARCNS setting for multiple ARC_NSEC counters +#define FLASH_HP_PRV_ARC_OEMBL_FCNTSELR (2) +#define FLASH_HP_PRV_ARC_SEC_FCNTSELR (1) +#define FLASH_HP_PRV_ARC_NSEC_0_FCNTSELR (4) +#define FLASH_HP_PRV_64_BITS (64U) + +/* flash_hp_configuration_area_write needs to be in RAM only when code flash programming is enabled */ +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #define FLASH_HP_CONFIG_AREA_WRITE_SECTION PLACE_IN_RAM_SECTION +#else + #define FLASH_HP_CONFIG_AREA_WRITE_SECTION +#endif + +/* The number of CPU cycles per each timeout loop. */ +#ifndef R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP + #if defined(__GNUC__) + #define R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP (6U) + #elif defined(__ICCARM__) + #define R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP (6U) + #endif +#endif + +#define FLASH_HP_REGISTER_WAIT_TIMEOUT(val, reg, timeout, err) \ + while (val != reg) \ + { \ + if (0 == timeout) \ + { \ + return err; \ + } \ + timeout--; \ + } + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) +static uint16_t g_configuration_area_data[FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT_CF] = {UINT16_MAX}; +#endif + +#define FLASH_HP_DF_START_ADDRESS (BSP_FEATURE_FLASH_DATA_FLASH_START) +#define FLASH_HP_DF_NUM_REGIONS ((BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE > 0) ? 2 : 1) + +static const flash_block_info_t g_code_flash_macro_info[] = +{ + { + .block_section_st_addr = 0, + .block_section_end_addr = UINT16_MAX, + .block_size = BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE, + .block_size_write = BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE + }, + { + .block_section_st_addr = BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE, + .block_section_end_addr = BSP_ROM_SIZE_BYTES - 1, + .block_size = BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE, + .block_size_write = BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE + } +}; + +static const flash_regions_t g_flash_code_region = +{ + .num_regions = 2, + .p_block_array = g_code_flash_macro_info +}; + +const flash_block_info_t g_data_flash_macro_info[] = +{ + { + .block_section_st_addr = FLASH_HP_DF_START_ADDRESS, + .block_section_end_addr = FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES - 1, + .block_size = BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE, + .block_size_write = BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE + }, +#if FLASH_HP_DF_NUM_REGIONS > 1 + { + .block_section_st_addr = BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START, + .block_section_end_addr = BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START + + BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE - 1, + .block_size = 1, + .block_size_write = BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE + }, +#endif +}; + +static flash_regions_t g_flash_data_region = +{ + .num_regions = FLASH_HP_DF_NUM_REGIONS, + .p_block_array = g_data_flash_macro_info +}; + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK == 1) && \ + (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) +static volatile uint32_t * const flash_hp_dualsel = (uint32_t *) FLASH_HP_FCU_CONFIG_SET_DUAL_MODE; +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +void fcu_fiferr_isr(void); +void fcu_frdyi_isr(void); + +/* Internal functions. */ +static fsp_err_t flash_hp_init(flash_hp_instance_ctrl_t * p_ctrl); + +#if BSP_FEATURE_FLASH_HP_VERSION == 4 +static void r_flash_hp_delay_ns(uint32_t ns, uint32_t mhz) PLACE_IN_RAM_SECTION __attribute__((noinline)); + +#endif +static fsp_err_t flash_hp_enter_pe_df_mode(flash_hp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t flash_hp_pe_mode_exit() PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_reset(flash_hp_instance_ctrl_t * p_ctrl) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_stop(void) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_status_clear() PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_erase_block(flash_hp_instance_ctrl_t * const p_ctrl, uint32_t block_size, + uint32_t timeout) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_write_data(flash_hp_instance_ctrl_t * const p_ctrl, uint32_t write_size, + uint32_t timeout) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_check_errors(fsp_err_t previous_error, uint32_t error_bits, + fsp_err_t return_error) PLACE_IN_RAM_SECTION; + +static void r_flash_hp_call_callback(flash_hp_instance_ctrl_t * p_ctrl, flash_event_t event); + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +static fsp_err_t flash_hp_df_blank_check(flash_hp_instance_ctrl_t * const p_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * p_blank_check_result); + +static fsp_err_t flash_hp_df_write(flash_hp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t flash_hp_df_erase(flash_hp_instance_ctrl_t * p_ctrl, uint32_t block_address, uint32_t num_blocks); + +#endif + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) || (((FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && \ + (BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE > 0)) == 1) +static fsp_err_t flash_hp_configuration_area_write(flash_hp_instance_ctrl_t * p_ctrl, + uint32_t fsaddr, + uint16_t * src_address) +FLASH_HP_CONFIG_AREA_WRITE_SECTION; + +#endif + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) +static void flash_hp_configuration_area_data_setup(uint32_t btflg_swap, uint32_t start_addr, + uint32_t end_addr) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_cf_write(flash_hp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + + #if (BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK == 1) +static fsp_err_t flash_hp_bank_swap(flash_hp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; +static uint32_t flash_hp_banksel_bankswp_addr_get(void); + + #endif + +static fsp_err_t flash_hp_cf_erase(flash_hp_instance_ctrl_t * p_ctrl, uint32_t block_address, + uint32_t num_blocks) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_enter_pe_cf_mode(flash_hp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_access_window_set(flash_hp_instance_ctrl_t * p_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) PLACE_IN_RAM_SECTION; + +static fsp_err_t flash_hp_set_startup_area_boot(flash_hp_instance_ctrl_t * p_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary) PLACE_IN_RAM_SECTION; + + #if (BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1) +static fsp_err_t flash_hp_set_id_code(flash_hp_instance_ctrl_t * p_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) PLACE_IN_RAM_SECTION; + + #endif + +#endif + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + +static fsp_err_t r_flash_hp_common_parameter_checking(flash_hp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_flash_hp_write_bc_parameter_checking(flash_hp_instance_ctrl_t * const p_ctrl, + uint32_t flash_address, + uint32_t const num_bytes, + bool check_write); + +#endif + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE > 0) +static fsp_err_t flash_hp_user_lockable_area_write(flash_hp_instance_ctrl_t * p_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes); + +#endif + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK == 1) +static uint8_t flash_hp_counter_to_fcntselr_convert(flash_arc_t counter); +static fsp_err_t flash_hp_arc_read(flash_hp_instance_ctrl_t * const p_ctrl, uint8_t fcntselr, uint32_t * const p_count); +static fsp_err_t flash_hp_arc_cmd_execute(flash_hp_instance_ctrl_t * const p_ctrl, + uint8_t fcntselr, + uint8_t cmd, + volatile uint32_t wait_count); + + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) +static fsp_err_t r_flash_hp_arc_common_parameter_checking(flash_hp_instance_ctrl_t * const p_ctrl, + flash_arc_t counter, + uint8_t fcntselr); + + #endif +#endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +const flash_api_t g_flash_on_flash_hp = +{ + .open = R_FLASH_HP_Open, + .close = R_FLASH_HP_Close, + .write = R_FLASH_HP_Write, + .erase = R_FLASH_HP_Erase, + .blankCheck = R_FLASH_HP_BlankCheck, + .statusGet = R_FLASH_HP_StatusGet, + .infoGet = R_FLASH_HP_InfoGet, + .accessWindowSet = R_FLASH_HP_AccessWindowSet, + .accessWindowClear = R_FLASH_HP_AccessWindowClear, + .idCodeSet = R_FLASH_HP_IdCodeSet, + .reset = R_FLASH_HP_Reset, + .startupAreaSelect = R_FLASH_HP_StartUpAreaSelect, + .updateFlashClockFreq = R_FLASH_HP_UpdateFlashClockFreq, + .bankSwap = R_FLASH_HP_BankSwap, + .callbackSet = R_FLASH_HP_CallbackSet, + .antiRollbackCounterIncrement = R_FLASH_HP_AntiRollbackCounterIncrement, + .antiRollbackCounterRefresh = R_FLASH_HP_AntiRollbackCounterRefresh, + .antiRollbackCounterRead = R_FLASH_HP_AntiRollbackCounterRead, + .userLockableAreaWrite = R_FLASH_HP_UserLockableAreaWrite, +}; + +/*******************************************************************************************************************//** + * @addtogroup FLASH_HP + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the high performance flash peripheral. Implements @ref flash_api_t::open. + * + * The Open function initializes the Flash. + * + * Example: + * @snippet r_flash_hp_example.c R_FLASH_HP_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ALREADY_OPEN The flash control block is already open. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_cfg. + * @retval FSP_ERR_IRQ_BSP_DISABLED Caller is requesting BGO but the Flash interrupts are not enabled. + * @retval FSP_ERR_FCLK FCLK must be a minimum of 4 MHz for Flash operations. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_Open (flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) + + /* If null pointers return error. */ + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + + /* If open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN != p_ctrl->opened), FSP_ERR_ALREADY_OPEN); + + /* Background operations for data flash are enabled but the flash interrupt is disabled. */ + if (p_cfg->data_flash_bgo) + { + FSP_ERROR_RETURN(p_cfg->irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ERROR_RETURN(p_cfg->err_irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + /* MF4 devices must have HOCO running and stable in order to program and erase flash. */ + #if BSP_FEATURE_FLASH_HP_VERSION == 4 + + /* If HOCO is not operating, return error */ + FSP_ERROR_RETURN(0U == R_SYSTEM->HOCOCR_b.HCSTP, FSP_ERR_INVALID_STATE); + + /* If HOCO is not stable, return error */ + FSP_ERROR_RETURN(1U == R_SYSTEM->OSCSF_b.HOCOSF, FSP_ERR_INVALID_STATE); + #endif +#endif + + /* Set the parameters struct based on the user supplied settings */ + p_ctrl->p_cfg = p_cfg; + + if (true == p_cfg->data_flash_bgo) + { + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Enable FCU interrupts. */ + R_FACI_HP->FRDYIE = 1U; + R_BSP_IrqCfgEnable(p_cfg->irq, p_cfg->ipl, p_ctrl); + + /* Enable Error interrupts. */ + R_FACI_HP->FAEINT = FLASH_HP_ERROR_INTERRUPTS_ENABLE; + R_BSP_IrqCfgEnable(p_cfg->err_irq, p_cfg->err_ipl, p_ctrl); + } + else + { + /* Disable Flash Rdy interrupt in the FLASH peripheral. */ + R_FACI_HP->FRDYIE = 0U; + + /* Disable Flash Error interrupt in the FLASH peripheral */ + R_FACI_HP->FAEINT = 0U; + } + + /* Calculate timeout values. */ + err = flash_hp_init(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If successful mark the control block as open. Otherwise release the hardware lock. */ + p_ctrl->opened = FLASH_HP_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Writes to the specified Code or Data Flash memory area. Implements @ref flash_api_t::write. + * + * Example: + * @snippet r_flash_hp_example.c R_FLASH_HP_Write + * + * @retval FSP_SUCCESS Operation successful. If BGO is enabled this means the operation was started + * successfully. + * @retval FSP_ERR_IN_USE The Flash peripheral is busy with a prior on-going transaction. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of attempting to Write an area + * that is protected by an Access Window. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. This may + * be returned if the requested Flash area is not blank. + * @retval FSP_ERR_TIMEOUT Timed out waiting for FCU operation to complete. + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was not a multiple of the programming size or exceeded + * the maximum range. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_Write (flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Verify write parameters. If failure return error. */ + err = r_flash_hp_write_bc_parameter_checking(p_ctrl, flash_address & ~BSP_FEATURE_TZ_NS_OFFSET, num_bytes, true); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); +#endif + + p_ctrl->operations_remaining = (num_bytes) >> 1; // Since two bytes will be written at a time + p_ctrl->source_start_address = src_address; + p_ctrl->dest_end_address = flash_address; + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + if ((flash_address & ~BSP_FEATURE_TZ_NS_OFFSET) < BSP_FEATURE_FLASH_DATA_FLASH_START) + { + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Verify the source address is not in code flash. It will not be available in P/E mode. */ + FSP_ASSERT(src_address > BSP_ROM_SIZE_BYTES); + #endif + + /* Initiate the write operation, may return FSP_ERR_IN_USE via setup_for_pe_mode() */ + err = flash_hp_cf_write(p_ctrl); + } + else +#endif + { +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + #if (BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE == 1) + p_ctrl->operations_remaining = num_bytes; // Since one byte will be written at a time + #endif + + /* Initiate the write operation, may return FSP_ERR_IN_USE via setup_for_pe_mode() */ + err = flash_hp_df_write(p_ctrl); +#endif + } + + return err; +} + +/*******************************************************************************************************************//** + * Erases the specified Code or Data Flash blocks. Implements @ref flash_api_t::erase by the block_erase_address. + * + * @note Code flash may contain blocks of different sizes. When erasing code flash it is important to take this + * into consideration to prevent erasing a larger address space than desired. + * + * Example: + * @snippet r_flash_hp_example.c R_FLASH_HP_Erase + * + * @retval FSP_SUCCESS Successful open. + * @retval FSP_ERR_INVALID_BLOCKS Invalid number of blocks specified + * @retval FSP_ERR_INVALID_ADDRESS Invalid address specified. If the address is in code flash then code flash + * programming must be enabled. + * @retval FSP_ERR_IN_USE Other flash operation in progress, or API not initialized + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of attempting to Erase an area + * that is protected by an Access Window. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_ERASE_FAILED Status is indicating a Erase error. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_Erase (flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Verify the control block is not null and is opened. */ + err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + if (true == p_ctrl->p_cfg->data_flash_bgo) + { + FSP_ASSERT(NULL != p_ctrl->p_callback); + } + + /* If invalid number of blocks return error. */ + FSP_ERROR_RETURN(num_blocks != 0U, FSP_ERR_INVALID_BLOCKS); +#endif + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + if ((address & ~BSP_FEATURE_TZ_NS_OFFSET) < BSP_FEATURE_FLASH_DATA_FLASH_START) + { + uint32_t start_address = 0; + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + uint32_t region0_blocks = 0; + #endif + + #if BSP_FEATURE_FLASH_CODE_FLASH_START != 0 + FSP_ERROR_RETURN(BSP_FEATURE_FLASH_CODE_FLASH_START <= (address & ~BSP_FEATURE_TZ_NS_OFFSET), + FSP_ERR_INVALID_ADDRESS); + #endif + + /* Configure the current parameters based on if the operation is for code flash or data flash. */ + if ((((address & ~BSP_FEATURE_TZ_NS_OFFSET)) & FLASH_HP_PRV_BANK1_MASK) < BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE) + { + start_address = address & ~((BSP_FEATURE_TZ_NS_OFFSET | BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE) - 1); + + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + region0_blocks = (BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE - (start_address & FLASH_HP_PRV_BANK1_MASK)) / + BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE; + #endif + } + else + { + start_address = address & ~((BSP_FEATURE_TZ_NS_OFFSET | BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE) - 1); + } + + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + uint32_t num_bytes = (region0_blocks * BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE); + if (num_blocks > region0_blocks) + { + num_bytes += ((num_blocks - region0_blocks) * BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE); + } + + #if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK + uint32_t rom_end = 0; + + if ((FLASH_HP_PRV_DUALSEL_BANKMD_MASK != (*flash_hp_dualsel & FLASH_HP_PRV_DUALSEL_BANKMD_MASK))) + { + /* Start address out of range */ + rom_end = BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START + ((BSP_ROM_SIZE_BYTES & ~UINT16_MAX) / 2); + FSP_ERROR_RETURN(start_address < rom_end, FSP_ERR_INVALID_ADDRESS); + + /* Region to erase must fall within bank */ + rom_end = (BSP_ROM_SIZE_BYTES & ~UINT16_MAX) / 2; + FSP_ERROR_RETURN((start_address & FLASH_HP_PRV_BANK1_MASK) + num_bytes <= rom_end, FSP_ERR_INVALID_BLOCKS); + } + else + { + /* Start address out of range */ + rom_end = BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES; + FSP_ERROR_RETURN(start_address < rom_end, FSP_ERR_INVALID_ADDRESS); + + /* Requested region to erase out of range */ + FSP_ERROR_RETURN(start_address + num_bytes <= rom_end, FSP_ERR_INVALID_BLOCKS); + } + + #else + FSP_ERROR_RETURN(start_address + num_bytes <= (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES), + FSP_ERR_INVALID_BLOCKS); + #endif + #endif + start_address |= (address & BSP_FEATURE_TZ_NS_OFFSET); + err = flash_hp_cf_erase(p_ctrl, start_address, num_blocks); + } + else +#endif + { +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + uint32_t start_address = address & ~((BSP_FEATURE_TZ_NS_OFFSET | BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE) - 1); + + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + uint32_t num_bytes = num_blocks * BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE; + + FSP_ERROR_RETURN((start_address >= (FLASH_HP_DF_START_ADDRESS)) && + (start_address < (FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERR_INVALID_ADDRESS); + + FSP_ERROR_RETURN(start_address + num_bytes <= (FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES), + FSP_ERR_INVALID_BLOCKS); + #endif + + /* Initiate the flash erase. */ + start_address |= (address & BSP_FEATURE_TZ_NS_OFFSET); + err = flash_hp_df_erase(p_ctrl, start_address, num_blocks); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + + return FSP_ERR_INVALID_ADDRESS; +#endif + } + + return err; +} + +/*******************************************************************************************************************//** + * Performs a blank check on the specified address area. Implements @ref flash_api_t::blankCheck. + * + * Example: + * @snippet r_flash_hp_example.c R_FLASH_HP_BlankCheck + * + * @retval FSP_SUCCESS Blank check operation completed with result in p_blank_check_result, or + * blank check started and in-progess (BGO mode). + * @retval FSP_ERR_INVALID_ADDRESS Invalid data flash address was input. + * @retval FSP_ERR_INVALID_SIZE 'num_bytes' was either too large or not aligned for the CF/DF boundary size. + * @retval FSP_ERR_IN_USE Other flash operation in progress or API not initialized. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of attempting to Erase an area + * that is protected by an Access Window. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + * @retval FSP_ERR_BLANK_CHECK_FAILED Blank check operation failed. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_BlankCheck (flash_ctrl_t * const p_api_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * p_blank_check_result) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Check parameters. If failure return error */ + err = r_flash_hp_write_bc_parameter_checking(p_ctrl, address & ~BSP_FEATURE_TZ_NS_OFFSET, num_bytes, false); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + FSP_ASSERT(NULL != p_blank_check_result); +#endif + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + + /* Is this a request to Blank check Code Flash? */ + /* If the address is code flash check if the region is blank. If not blank return error. */ + if ((address & ~BSP_FEATURE_TZ_NS_OFFSET) < BSP_FEATURE_FLASH_DATA_FLASH_START) + { + /* Blank checking for Code Flash does not require any FCU operations. The specified address area + * can simply be checked for non 0xFF. */ + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + *p_blank_check_result = FLASH_RESULT_BLANK; // Assume blank until we know otherwise + uint8_t * p_address = (uint8_t *) address; + for (uint32_t index = 0U; index < num_bytes; index++) + { + if (p_address[index] != UINT8_MAX) + { + *p_blank_check_result = FLASH_RESULT_NOT_BLANK; + break; + } + } + } + /* Otherwise the address is data flash. Put the flash in the blank check state. Return status. */ + else +#endif + { +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + err = flash_hp_df_blank_check(p_ctrl, address, num_bytes, p_blank_check_result); +#endif + } + + return err; +} + +/*******************************************************************************************************************//** + * Query the FLASH peripheral for its status. Implements @ref flash_api_t::statusGet. + * + * Example: + * @snippet r_flash_hp_example.c R_FLASH_HP_StatusGet + * + * @retval FSP_SUCCESS FLASH peripheral is ready to use. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_StatusGet (flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status) +{ +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + /* If null pointer return error. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN(!(FLASH_HP_OPEN != p_ctrl->opened), FSP_ERR_NOT_OPEN); +#else + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* If the flash is currently in program/erase mode notify the caller that the flash is busy. */ + if ((R_FACI_HP->FENTRYR & FLASH_HP_FENTRYR_PE_MODE_BITS) == 0x0000U) + { + *p_status = FLASH_STATUS_IDLE; + } + else + { + *p_status = FLASH_STATUS_BUSY; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Implements @ref flash_api_t::idCodeSet. + * + * @retval FSP_SUCCESS ID Code successfully configured. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal + * command. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_IdCodeSet (flash_ctrl_t * const p_api_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1) + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the id bytes are not in code flash. They will not be available in P/E mode. */ + FSP_ASSERT(((uint32_t) p_id_code) > BSP_ROM_SIZE_BYTES); + + /* Verify the control block is not null and is opened. */ + err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* If successful set the id code. */ + err = flash_hp_set_id_code(p_ctrl, p_id_code, mode); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_id_code); + FSP_PARAMETER_NOT_USED(mode); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + /* Return status. */ + return err; +} + +/*******************************************************************************************************************//** + * Configure an access window for the Code Flash memory using the provided start and end address. An access window + * defines a contiguous area in Code Flash for which programming/erase is enabled. This area is on block boundaries. The + * block containing start_addr is the first block. The block containing end_addr is the last block. The access window + * then becomes first block --> last block inclusive. Anything outside this range of Code Flash is then write protected. + * @note If the start address and end address are set to the same value, then the access window is effectively + * removed. This accomplishes the same functionality as R_FLASH_HP_AccessWindowClear(). + * + * Implements @ref flash_api_t::accessWindowSet. + * + * @retval FSP_SUCCESS Access window successfully configured. + * @retval FSP_ERR_INVALID_ADDRESS Invalid settings for start_addr and/or end_addr. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal + * command. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_AccessWindowSet (flash_ctrl_t * const p_api_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW == 1) + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Note that the end_addr indicates the address up to, but not including the block that contains that address. */ + /* Therefore to allow the very last Block to be included in the access window we must allow for FLASH_CF_BLOCK_END+1 */ + /* If the start or end addresses are invalid return error. */ + FSP_ERROR_RETURN(start_addr <= end_addr, FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(end_addr <= BSP_ROM_SIZE_BYTES, FSP_ERR_INVALID_ADDRESS); + #endif + + /* Set the access window. */ + err = flash_hp_access_window_set(p_ctrl, start_addr, end_addr); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + FSP_PARAMETER_NOT_USED(start_addr); + FSP_PARAMETER_NOT_USED(end_addr); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + /* Return status. */ + return err; +} + +/*******************************************************************************************************************//** + * Remove any access window that is currently configured in the Code Flash. Subsequent to this call all Code Flash is + * writable. Implements @ref flash_api_t::accessWindowClear. + * + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal + * command. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_AccessWindowClear (flash_ctrl_t * const p_api_ctrl) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW == 1) + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* Clear the access window. When the start address and end address are set to the same value, then the access + * window is effectively removed. */ + err = flash_hp_access_window_set(p_ctrl, 0, 0); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Reset the FLASH peripheral. Implements @ref flash_api_t::reset. + * + * No attempt is made to check if the flash is busy before executing the reset since the assumption is that a reset will + * terminate any existing operation. + * + * @retval FSP_SUCCESS Flash circuit successfully reset. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal command. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_Reset (flash_ctrl_t * const p_api_ctrl) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) + + /* If null pointer return error. */ + FSP_ASSERT(NULL != p_ctrl); + + /* If control block not open return error. */ + FSP_ERROR_RETURN(FLASH_HP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Reset the flash. */ + return flash_hp_reset(p_ctrl); +} + +/*******************************************************************************************************************//** + * Selects which block, Default (Block 0) or Alternate (Block 1), is used as the startup area block. The provided + * parameters determine which block will become the active startup block and whether that action will be immediate (but + * temporary), or permanent subsequent to the next reset. Doing a temporary switch might appear to have limited + * usefulness. If there is an access window in place such that Block 0 is write protected, then one could do a temporary + * switch, update the block and switch them back without having to touch the access window. Implements + * @ref flash_api_t::startupAreaSelect. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal + * command. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_StartUpAreaSelect (flash_ctrl_t * const p_api_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If the swap type is BTFLG and the operation is temporary there's nothing to do. */ + FSP_ASSERT(!((swap_type == FLASH_STARTUP_AREA_BTFLG) && (is_temporary == false))); + #endif + + err = flash_hp_set_startup_area_boot(p_ctrl, swap_type, is_temporary); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(swap_type); + FSP_PARAMETER_NOT_USED(is_temporary); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Swaps the flash bank located at address 0x00000000 and address 0x00200000. This can only be done when in dual bank + * mode. Dual bank mode can be enabled in the FSP Configuration Tool under BSP Properties. After a bank swap is done + * the MCU will need to be reset for the changes to take place. + * @ref flash_api_t::bankSwap. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_INVALID_MODE Cannot switch banks while flash is in Linear mode. + * @retval FSP_ERR_WRITE_FAILED Flash write operation failed. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal + * command. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_BankSwap (flash_ctrl_t * const p_api_ctrl) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK == 1) + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + FSP_ERROR_RETURN(0 == (*flash_hp_dualsel & FLASH_HP_PRV_DUALSEL_BANKMD_MASK), FSP_ERR_INVALID_MODE) + #endif + + flash_hp_bank_swap(p_ctrl); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Indicate to the already open Flash API that the FCLK has changed. Implements @ref flash_api_t::updateFlashClockFreq. + * + * This could be the case if the application has changed the system clock, and therefore the FCLK. Failure to call this + * function subsequent to changing the FCLK could result in damage to the flash macro. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE Flash is busy with an on-going operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_FCLK FCLK is not within the acceptable range. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_UpdateFlashClockFreq (flash_ctrl_t * const p_api_ctrl) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + fsp_err_t err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Calculate timeout values */ + return flash_hp_init(p_ctrl); +} + +/*******************************************************************************************************************//** + * Returns the information about the flash regions. Implements @ref flash_api_t::infoGet. + * + * @retval FSP_SUCCESS Successful retrieved the request information. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_info. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_InfoGet (flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info) +{ +#if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + + /* If null pointers return error. */ + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ASSERT(NULL != p_info); + + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + /* If the flash api is not open return an error. */ + FSP_ERROR_RETURN(FLASH_HP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#else + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Copy information about the code and data flash to the user structure. */ + p_info->code_flash = g_flash_code_region; + p_info->data_flash = g_flash_data_region; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Releases any resources that were allocated by the Open() or any subsequent Flash operations. Implements + * @ref flash_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_cfg. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_Close (flash_ctrl_t * const p_api_ctrl) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + fsp_err_t err = FSP_SUCCESS; + +#if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + + /* If null pointer return error. */ + FSP_ASSERT(NULL != p_ctrl); + + /* If the flash api is not open return an error. */ + FSP_ERROR_RETURN(FLASH_HP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Close the API */ + p_ctrl->opened = FLASH_HP_CLOSE; + + if (p_ctrl->p_cfg->irq >= 0) + { + /* Disable interrupt in ICU */ + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + } + + /* Disable Flash Rdy interrupt in the FLASH peripheral */ + R_FACI_HP->FRDYIE = 0x00U; + + if (p_ctrl->p_cfg->err_irq >= 0) + { + /* Disable interrupt in ICU */ + R_BSP_IrqDisable(p_ctrl->p_cfg->err_irq); + } + + /* Disable Flash Error interrupt in the FLASH peripheral */ + R_FACI_HP->FAEINT = 0x00U; + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref flash_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_CallbackSet (flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void * const p_context, + flash_callback_args_t * const p_callback_memory) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + +#if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(FLASH_HP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + flash_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(flash_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Increments the selected anti-rollback counter. + * + * @warning If this function returns an error code other than FSP_SUCCESS, or power loss occurs during a call to this function, + * call @ref R_FLASH_HP_AntiRollbackCounterRefresh to ensure the counter flash is in a valid state following the error. + * + * @note The counter is read internally before increment. + * + * Implements @ref flash_api_t::antiRollbackCounterIncrement + * + * @retval FSP_SUCCESS Counter incremented successfully + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_api_ctrl + * @retval FSP_ERR_NOT_ENABLED The specified counter has not been configured (configuration is only required for ARC_NSEC) + * @retval FSP_ERR_OVERFLOW The counter cannot be incremented because it is already at its max value + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Data Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal command + * @retval FSP_ERR_UNSUPPORTED Data flash programming is not enabled or selected anti-rollback counter is not supported on this MCU + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_AntiRollbackCounterIncrement (flash_ctrl_t * const p_api_ctrl, flash_arc_t counter) +{ + fsp_err_t err; + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK == 1) + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + uint8_t fcntselr = flash_hp_counter_to_fcntselr_convert(counter); + + #if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + err = r_flash_hp_arc_common_parameter_checking(p_ctrl, counter, fcntselr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* Read the current counter value*/ + uint32_t count; + err = flash_hp_arc_read(p_ctrl, fcntselr, &count); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check for overflow. */ + uint32_t max_count; + if (counter >= FLASH_ARC_NSEC_0) + { + uint8_t arcns = R_OFS_DATAFLASH->ARCCS_b.CNF_ARCNS; + max_count = (arcns == FLASH_HP_PRV_ARCNS_MULTIPLE) ? + BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT : BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT; + } + else if (counter == FLASH_ARC_OEMBL) + { + max_count = BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT; + } + else + { + max_count = BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT; + } + + FSP_ERROR_RETURN((count + 1) <= max_count, FSP_ERR_OVERFLOW); + + /* Increment the counter */ + err = flash_hp_arc_cmd_execute(p_ctrl, + fcntselr, + FLASH_HP_FACI_CMD_INCREMENT_COUNTER, + p_ctrl->timeout_arc_increment_refresh); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(counter); + + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Refreshes the selected anti-rollback counter flash area to ensure the flash is in a valid state even if an error + * occurred during counter increment processing. + * + * This function must be called if errors or power failure occurred during counter increment. + * + * Power failure can be detected by the application code by management of user-defined non-voltile flags during + * counter increment. + * + * Until a refresh completes successfully, the value of the anti-rollback counter cannot be guaranteed and should not + * be read. + * + * Implements @ref flash_api_t::antiRollbackCounterRefresh + * + * @retval FSP_SUCCESS Counter refreshed successfully + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_ENABLED The specified counter has not been configured (configuration is only required for ARC_NSEC) + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Data Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal command + * @retval FSP_ERR_UNSUPPORTED Data flash programming is not enabled or Anti-Rollback counter is not supported on this MCU + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_AntiRollbackCounterRefresh (flash_ctrl_t * const p_api_ctrl, flash_arc_t counter) +{ + fsp_err_t err; + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK == 1) + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + uint8_t fcntselr = flash_hp_counter_to_fcntselr_convert(counter); + + #if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + err = r_flash_hp_arc_common_parameter_checking(p_ctrl, counter, fcntselr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* Refresh the counter */ + err = flash_hp_arc_cmd_execute(p_ctrl, + fcntselr, + FLASH_HP_FACI_CMD_REFRESH_COUNTER, + p_ctrl->timeout_arc_increment_refresh); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(counter); + + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Reads the selected anti-rollback counter and returns the number of counter bits set. + * + * Implements @ref flash_api_t::antiRollbackCounterRead + * + * @retval FSP_SUCCESS Counter read successfully into p_count + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_api_ctrl or p_count + * @retval FSP_ERR_NOT_ENABLED The specified counter has not been configured (configuration is only required for ARC_NSEC) + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Data Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal command + * @retval FSP_ERR_UNSUPPORTED Data flash programming is not enabled or Anti-Rollback counter is not supported on this MCU + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_AntiRollbackCounterRead (flash_ctrl_t * const p_api_ctrl, + flash_arc_t counter, + uint32_t * const p_count) +{ + fsp_err_t err; + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK == 1) + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + uint8_t fcntselr = flash_hp_counter_to_fcntselr_convert(counter); + + #if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + err = r_flash_hp_arc_common_parameter_checking(p_ctrl, counter, fcntselr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(p_count); + #endif + + /* Read the counter */ + err = flash_hp_arc_read(p_ctrl, fcntselr, p_count); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(counter); + FSP_PARAMETER_NOT_USED(p_count); + + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Write to the user lockable area in flash + * + * Implements @ref flash_api_t::userLockableAreaWrite + * + * @note BGO is not supported for user lockable area flash operations. + * + * @retval FSP_SUCCESS Operation successful. + * @retval FSP_ERR_IN_USE The Flash peripheral is busy with a prior on-going transaction. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of attempting to Write an area + * that is protected by an Access Window. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for FCU operation to complete. + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was not a multiple of the programming size or exceeded + * the maximum range. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_UserLockableAreaWrite (flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes) +{ + fsp_err_t err; + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE > 0) + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + + #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + err = r_flash_hp_write_bc_parameter_checking(p_ctrl, flash_address, num_bytes, true); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + err = flash_hp_user_lockable_area_write(p_ctrl, src_address, flash_address, num_bytes); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(src_address); + FSP_PARAMETER_NOT_USED(flash_address); + FSP_PARAMETER_NOT_USED(num_bytes); + + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup FLASH_HP) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Write data to the flash. + * + * @param p_ctrl Pointer to the control block + * @param[in] write_size The write size + * @param[in] timeout The timeout + * + * @retval FSP_SUCCESS Write completed successfully + * @retval FSP_ERR_TIMEOUT Flash timed out during write operation. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_write_data (flash_hp_instance_ctrl_t * const p_ctrl, uint32_t write_size, uint32_t timeout) +{ +#if !(BSP_FEATURE_FLASH_HP_VERSION == 4) + volatile uint32_t wait_count; +#endif + + if (0 == timeout) + { + /* Disable flash interrupts until command final is written. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + } + + /* Set block start address */ + R_FACI_HP->FSADDR = p_ctrl->dest_end_address; + + /* Issue two part Write commands */ + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_PROGRAM; + + /* Write 2 bytes at a time */ + uint32_t line_size = write_size / 2U; + uint32_t increment = 2U; + +#if (BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE == 1) || (BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE == 1) + + /* Special case for line size of 1, where only 1 byte is written at a time */ + if (1U == write_size) + { + line_size = 1; + increment = 1; + } +#endif + + R_FACI_HP_CMD->FACI_CMD8 = (uint8_t) line_size; + + /* Write one line. If timeout stop the flash and return error. */ + for (uint32_t i = 0U; i < line_size; i++) + { + /* Copy data from source address to destination area */ + R_FACI_HP_CMD->FACI_CMD16 = *(uint16_t *) p_ctrl->source_start_address; + +#if !(BSP_FEATURE_FLASH_HP_VERSION == 4) + wait_count = p_ctrl->timeout_dbfull; + + while (R_FACI_HP->FSTATR_b.DBFULL == 1U) + { + /* Wait until DBFULL is 0 unless timeout occurs. */ + if (wait_count-- == 0U) + { + + /* If DBFULL is not set to 0 return timeout. */ + return FSP_ERR_TIMEOUT; + } + } +#endif + + p_ctrl->source_start_address += increment; + p_ctrl->dest_end_address += increment; + p_ctrl->operations_remaining--; + } + + /* Issue write end command */ + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_FINAL; + + /* If a timeout has been supplied wait for the flash to become ready. Otherwise return immediately. */ + if (timeout) + { + /* Read FRDY bit until it has been set to 1 indicating that the current operation is complete.*/ + /* Wait until operation has completed or timeout occurs. If timeout stop the module and return error. */ + while (1U != R_FACI_HP->FSTATR_b.FRDY) + { + /* Wait until FRDY is 1 unless timeout occurs. */ + if (timeout == 0U) + { + return FSP_ERR_TIMEOUT; + } + + timeout--; + } + } + else + { + /* Enable flash interrupts following write sequence. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->irq); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Check for errors after a flash operation + * + * @param[in] previous_error The previous error + * @param[in] error_bits The error bits + * @param[in] return_error The return error + * + * @retval FSP_SUCCESS Command completed successfully + * @retval FSP_ERR_CMD_LOCKED Flash entered command locked state + **********************************************************************************************************************/ +static fsp_err_t flash_hp_check_errors (fsp_err_t previous_error, uint32_t error_bits, fsp_err_t return_error) +{ + /* See "Recovery from the Command-Locked State" in the Flash Memory section of the relevant hardware manual. */ + fsp_err_t err = FSP_SUCCESS; + if (1U == R_FACI_HP->FASTAT_b.CMDLK) + { + /* If an illegal error occurred read and clear CFAE and DFAE in FASTAT. */ + if (1U == R_FACI_HP->FSTATR_b.ILGLERR) + { + R_FACI_HP->FASTAT; + R_FACI_HP->FASTAT = 0; + } + + err = FSP_ERR_CMD_LOCKED; + } + + /* Check if status is indicating a Programming error */ + /* If a programming error occurred return error. */ + if (R_FACI_HP->FSTATR & error_bits) + { + err = return_error; + } + + /* Return the first error code that was encountered. */ + if (FSP_SUCCESS != previous_error) + { + err = previous_error; + } + + if (FSP_SUCCESS != err) + { + /* Stop the flash and return the previous error. */ + (void) flash_hp_stop(); + } + + return err; +} + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function initiates the write sequence for the R_FLASH_HP_Write() function. + * @param[in] p_ctrl Flash control block + * @retval FSP_SUCCESS The write started successfully. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + * @retval FSP_ERR_CMD_LOCKED Flash entered command locked state. + * @retval FSP_ERR_TIMEOUT Flash timed out during write operation. + * @retval FSP_ERR_WRITE_FAILED Flash write operation failed. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_cf_write (flash_hp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Update Flash state and enter the respective Code or Data Flash P/E mode. If failure return error */ + err = flash_hp_enter_pe_cf_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Iterate through the number of data bytes */ + while (p_ctrl->operations_remaining && (err == FSP_SUCCESS)) + { + err = flash_hp_write_data(p_ctrl, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE, p_ctrl->timeout_write_cf); + + err = flash_hp_check_errors(err, FLASH_HP_FSTATR_PRGERR | FLASH_HP_FSTATR_ILGLERR, FSP_ERR_WRITE_FAILED); + } + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + /* Return status. */ + return err; +} + + #if (BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK == 1) + +/*******************************************************************************************************************//** + * This function checks the security attribution of the Bank Select Register BANKSWP bits and returns the appropriate + * register address according to the configured attribution: BANKSEL for nonsecure attribution + * and BANKSEL_SEC for secure attribution. + * + * The security attribution of the BANKSWP bits must be read from the BANKSEL_SEL register rather than determined + * from compile time macros in case another program (eg. a bootloader) has modified the configuration area. + * + * @retval uint32_t Address of bank select register bankswap setting + **********************************************************************************************************************/ +static uint32_t flash_hp_banksel_bankswp_addr_get (void) +{ + volatile uint32_t * const flash_hp_banksel_sel = (uint32_t *) FLASH_HP_BANK_MODE_SECURITY_ATTRIBUTION; + + /* Check if non-secure attribution is selected */ + if ((*flash_hp_banksel_sel & FLASH_HP_PRV_BANKSEL_BANKSWP_MASK) == FLASH_HP_PRV_BANKSEL_BANKSWP_MASK) + { + return FLASH_HP_FCU_CONFIG_SET_BANK_MODE; + } + + /* Secure attribution selected, return address of secure register */ + return FLASH_HP_FCU_CONFIG_SET_BANK_MODE_SEC; +} + +/*******************************************************************************************************************//** + * This function swaps which flash bank will be used to boot from after the next reset. + * @param[in] p_ctrl Flash control block + * @retval FSP_SUCCESS The write started successfully. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + * @retval FSP_ERR_CMD_LOCKED Flash entered command locked state. + * @retval FSP_ERR_TIMEOUT Flash timed out during write operation. + * @retval FSP_ERR_WRITE_FAILED Flash write operation failed. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_bank_swap (flash_hp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + uint32_t const flash_hp_banksel = flash_hp_banksel_bankswp_addr_get(); + + /* Unused bits should be written as 1. */ + g_configuration_area_data[0] = + (uint16_t) ((~FLASH_HP_PRV_BANKSEL_BANKSWP_MASK) | + (~(FLASH_HP_PRV_BANKSEL_BANKSWP_MASK & *((volatile uint32_t *) flash_hp_banksel)))); + + memset(&g_configuration_area_data[1], UINT8_MAX, 7 * sizeof(uint16_t)); + + flash_hp_enter_pe_cf_mode(p_ctrl); + + /* Write the configuration area to the access/startup region. */ + err = flash_hp_configuration_area_write(p_ctrl, flash_hp_banksel, g_configuration_area_data); + + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + /* Return status. */ + return err; +} + + #endif +#endif + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function initiates the write sequence for the R_FLASH_HP_Write() function. + * @param[in] p_ctrl Flash control block + * @retval FSP_SUCCESS The write started successfully. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + * @retval FSP_ERR_CMD_LOCKED Flash entered command locked state. + * @retval FSP_ERR_TIMEOUT Flash timed out during write operation. + * @retval FSP_ERR_WRITE_FAILED Flash write operation failed. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_df_write (flash_hp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Update Flash state and enter the respective Code or Data Flash P/E mode. If failure return error */ + err = flash_hp_enter_pe_df_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + uint32_t wait_count; + + /* If in BGO mode, exit here; remaining processing if any will be done in ISR */ + if (p_ctrl->p_cfg->data_flash_bgo == true) + { + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_WRITE; + wait_count = 0; + } + else + { + wait_count = p_ctrl->timeout_write_df; + } + + do + { + err = flash_hp_write_data(p_ctrl, BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE, wait_count); + + if (p_ctrl->p_cfg->data_flash_bgo) + { + + /* Errors will be handled in the error interrupt when using BGO. */ + return err; + } + + err = flash_hp_check_errors(err, FLASH_HP_FSTATR_PRGERR, FSP_ERR_WRITE_FAILED); + } while (p_ctrl->operations_remaining && (err == FSP_SUCCESS)); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +#endif + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the parameter checking required by the write, read and blank check functions. + * + * @param[in] p_ctrl Flash control block + * @param[in] flash_address The flash address to be written to + * @param[in] num_bytes The number bytes + * @param[in] check_write Check that the parameters are valid for a write. + * + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_IN_USE The Flash peripheral is busy with a prior on-going transaction. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was not a multiple of the programming size or exceeded + * the maximum range. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + **********************************************************************************************************************/ +static fsp_err_t r_flash_hp_write_bc_parameter_checking (flash_hp_instance_ctrl_t * const p_ctrl, + uint32_t flash_address, + uint32_t const num_bytes, + bool check_write) +{ + /* Verify the control block is not null and is opened. Verify the flash isn't in use. */ + fsp_err_t err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + uint32_t write_size; + + if (p_ctrl->p_cfg->data_flash_bgo == true) + { + FSP_ASSERT(NULL != p_ctrl->p_callback); + } + + /* If invalid address or number of bytes return error. */ + #if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + if (flash_address < BSP_FEATURE_FLASH_DATA_FLASH_START) + { + #if BSP_FEATURE_FLASH_CODE_FLASH_START != 0 + FSP_ERROR_RETURN(BSP_FEATURE_FLASH_CODE_FLASH_START <= flash_address, FSP_ERR_INVALID_ADDRESS); + #endif + uint32_t rom_end = BSP_ROM_SIZE_BYTES; + #if BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK + if (0 == (FLASH_HP_PRV_DUALSEL_BANKMD_MASK & *flash_hp_dualsel)) + { + flash_address &= ~BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START; + rom_end = BSP_ROM_SIZE_BYTES / 2; + } + #endif + + #if BSP_FEATURE_FLASH_CODE_FLASH_START != 0 + flash_address &= ~BSP_FEATURE_FLASH_CODE_FLASH_START; + #endif + + FSP_ERROR_RETURN(flash_address <= rom_end, FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(flash_address + num_bytes <= rom_end, FSP_ERR_INVALID_SIZE); + write_size = BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; + } + else + #endif + { + #if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + uint32_t start; + uint32_t end; + + #if (BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE > 0) + if (flash_address >= BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START) + { + start = BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START; + end = BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START + BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE; + } + else + #endif + { + start = FLASH_HP_DF_START_ADDRESS; + end = FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES; + } + + write_size = BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE; + + FSP_ERROR_RETURN((flash_address >= start) && (flash_address < end), FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(((flash_address + num_bytes) <= end), FSP_ERR_INVALID_SIZE); + #else + + return FSP_ERR_INVALID_ADDRESS; + #endif + } + + if (check_write) + { + FSP_ERROR_RETURN(!(flash_address & (write_size - 1U)), FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(!(num_bytes & (write_size - 1U)), FSP_ERR_INVALID_SIZE); + } + + /* If invalid number of bytes return error. */ + FSP_ERROR_RETURN((0 != num_bytes), FSP_ERR_INVALID_SIZE); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); + + return FSP_SUCCESS; +} + +#endif + +#if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the common parameter checking required by top level API functions. + * @param p_ctrl Pointer to the control block + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_NOT_OPEN The flash module is not open. + * @retval FSP_ERR_IN_USE The Flash peripheral is busy with a prior on-going transaction. + **********************************************************************************************************************/ +static fsp_err_t r_flash_hp_common_parameter_checking (flash_hp_instance_ctrl_t * const p_ctrl) +{ + /* If null control block return error. */ + FSP_ASSERT(p_ctrl); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); + + /* If the flash is currently in program/erase mode return an error. */ + FSP_ERROR_RETURN((R_FACI_HP->FENTRYR & FLASH_HP_FENTRYR_PE_MODE_BITS) == 0x0000U, FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + + #if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK == 1) +static fsp_err_t r_flash_hp_arc_common_parameter_checking (flash_hp_instance_ctrl_t * const p_ctrl, + flash_arc_t counter, + uint8_t fcntselr) +{ + fsp_err_t err = r_flash_hp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + uint8_t arcns = R_OFS_DATAFLASH->ARCCS_b.CNF_ARCNS; + uint8_t target_counter_is_arc_ns = fcntselr & 0x4; + uint8_t target_counter_is_enabled = (FLASH_HP_PRV_ARCNS_MULTIPLE == arcns) || + ((FLASH_HP_PRV_ARCNS_SINGLE == arcns) && (counter == FLASH_ARC_NSEC_0)); + + /* Ensure that requested counter is supported by hardware. Some MCUs may not support all counter types. */ + #if (0 == BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT) + FSP_ERROR_RETURN(counter != FLASH_ARC_OEMBL, FSP_ERR_UNSUPPORTED); + #endif + + #if (0 == BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT) + FSP_ERROR_RETURN(counter != FLASH_ARC_SEC, FSP_ERR_UNSUPPORTED); + #endif + + #if (0 == BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS) + FSP_ERROR_RETURN(0 == target_counter_is_arc_ns, FSP_ERR_UNSUPPORTED); + #endif + + /* Ensure that requested NSEC counter has been configured when NSEC is the target counter */ + FSP_ERROR_RETURN(!target_counter_is_arc_ns || target_counter_is_enabled, FSP_ERR_NOT_ENABLED); + + return FSP_SUCCESS; +} + + #endif + +#endif + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the Blank check phase required by the R_FLASH_HP_BlankCheck() function. + * + * @param[in] p_ctrl Flash control block + * @param[in] address The start address of the range to blank check + * @param[in] num_bytes The number bytes + * @param[out] p_blank_check_result The blank check result + * + * @retval FSP_SUCCESS Setup completed completed without error. + * @retval FSP_ERR_PE_FAILURE Failed to enter P/E mode + * @retval FSP_ERR_CMD_LOCKED Peripheral in command locked state. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_BLANK_CHECK_FAILED Blank check operation failed. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_df_blank_check (flash_hp_instance_ctrl_t * const p_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * p_blank_check_result) +{ + fsp_err_t err; + + /* This is a request to Blank check Data Flash */ + err = flash_hp_enter_pe_df_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Start the Blank check operation. If BGO is enabled then the result of the Blank check will be + * available when the interrupt occurs and p_blank_check_result will contain FLASH_RESULT_BGO_ACTIVE */ + + /* Call blank check. If successful and not DF BGO operation then enter read mode. */ + /* Set the mode to incremental*/ + R_FACI_HP->FBCCNT = 0x00U; + + /* Set the start address for blank checking*/ + R_FACI_HP->FSADDR = address; + + /* Set the end address for blank checking*/ + R_FACI_HP->FEADDR = (address + num_bytes) - 1U; + + /* Issue two part Blank Check command*/ + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_BLANK_CHECK; + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_FINAL; + + /* If in DF BGO mode, exit here; remaining processing if any will be done in ISR */ + if (p_ctrl->p_cfg->data_flash_bgo == true) + { + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_BLANKCHECK; + *p_blank_check_result = FLASH_RESULT_BGO_ACTIVE; + + return FSP_SUCCESS; + } + + /* timeout_blank_check specifies the wait time for a 4 byte blank check, + * num_bytes is divided by 4 and then multiplied to calculate the wait time for the entire operation*/ + + /* Configure the timeout value. */ + uint32_t wait_count = (p_ctrl->timeout_blank_check * ((num_bytes >> 2) + 1)); + + /* Wait for the operation to complete or timeout. If timeout stop the module and return error. */ + + /* Read FRDY bit until it has been set to 1 indicating that the current + * operation is complete. */ + while (1U != R_FACI_HP->FSTATR_b.FRDY) + { + /* Wait until FRDY is 1 unless timeout occurs. */ + if (wait_count == 0U) + { + err = FSP_ERR_TIMEOUT; + break; + } + + wait_count--; + } + + /* Check the status of the Blank Check operation. */ + err = flash_hp_check_errors(err, 0, FSP_ERR_BLANK_CHECK_FAILED); + + /* Set the result to blank or not blank. */ + if (R_FACI_HP->FBCSTAT == 0x01U) + { + *p_blank_check_result = FLASH_RESULT_NOT_BLANK; + } + else + { + *p_blank_check_result = FLASH_RESULT_BLANK; + } + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + /* Return status. */ + return err; +} + +#endif + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK == 1) + +/*******************************************************************************************************************//** + * This function converts the flash API counter enumeration to the register value for FCNTSELR + * + * @param counter The API counter value + * + * @returns FCNTSELR value + **********************************************************************************************************************/ +static uint8_t flash_hp_counter_to_fcntselr_convert (flash_arc_t counter) +{ + return (uint8_t) ((counter < FLASH_ARC_NSEC_0 ? counter + 1 : counter + 2) & R_FACI_HP_FCNTSELR_CNTSEL_Msk); +} + +/*******************************************************************************************************************//** + * This function reads the anti-rollback counter value + * + * ARC_OEMBL is read by FACI command because it is required to be read before increment to support RSIP-E51A comparison + * by the FACI controller. The other counters are read by memory-mapped read. + * + * @param p_ctrl Flash control block + * @param fcntselr FCNTSELR register value + * @param p_count The counter value + * + * @returns FCNTSELR value + **********************************************************************************************************************/ +static fsp_err_t flash_hp_arc_read (flash_hp_instance_ctrl_t * const p_ctrl, uint8_t fcntselr, uint32_t * const p_count) +{ + fsp_err_t err; + volatile uint32_t * p_src; + uint32_t counter_num_words; + uint32_t arc_oembl[2]; + + switch (fcntselr) + { + case FLASH_HP_PRV_ARC_OEMBL_FCNTSELR: + { + err = flash_hp_arc_cmd_execute(p_ctrl, fcntselr, FLASH_HP_FACI_CMD_READ_COUNTER, p_ctrl->timeout_arc_read); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Read the counter values after successful FACI read command */ + arc_oembl[0] = R_FACI_HP->FCNTDATAR0; + arc_oembl[1] = R_FACI_HP->FCNTDATAR1; + + p_src = arc_oembl; + counter_num_words = 2; + break; + } + + case FLASH_HP_PRV_ARC_SEC_FCNTSELR: + { + p_src = R_OFS_DATAFLASH->ARC_SEC; + counter_num_words = sizeof(R_OFS_DATAFLASH->ARC_SEC) / sizeof(R_OFS_DATAFLASH->ARC_SEC[0]); + break; + } + + default: // ARC_NSEC + { + uint8_t arcns = R_OFS_DATAFLASH->ARCCS_b.CNF_ARCNS; + p_src = R_OFS_DATAFLASH->ARC_NSEC; + + if (FLASH_HP_PRV_ARCNS_MULTIPLE == arcns) + { + counter_num_words = BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT >> 5; // bits to words + uint32_t counter_index = ((uint32_t) fcntselr - FLASH_HP_PRV_ARC_NSEC_0_FCNTSELR) * counter_num_words; + p_src = &R_OFS_DATAFLASH->ARC_NSEC[counter_index]; + } + else if (FLASH_HP_PRV_ARCNS_SINGLE == arcns) + { + counter_num_words = sizeof(R_OFS_DATAFLASH->ARC_NSEC) / sizeof(R_OFS_DATAFLASH->ARC_NSEC[0]); + } + else + { + return FSP_ERR_NOT_ENABLED; + } + + break; + } + } + + /* Determine the number of bits set in the counter data. This is the actual count value. */ + uint32_t count = 0; + for (uint8_t word = 0; word < counter_num_words; word += 2) + { + uint32_t lo = p_src[word]; + uint32_t hi = p_src[1 + word]; + count += FLASH_HP_PRV_64_BITS - (__CLZ(hi) + __CLZ(lo)); + } + + *p_count = count; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function executes an anti-rollback counter FACI operation (read, refresh, or increment) + * + * @param[in] p_ctrl Flash control block + * @param[in] fcntselr Register value to write to FCNTSELR to select the target counter + * @param[in] cmd The FACI command to use + * @param[in] wait_count The command timeout + * + * @returns FCNTSELR value + **********************************************************************************************************************/ +static fsp_err_t flash_hp_arc_cmd_execute (flash_hp_instance_ctrl_t * const p_ctrl, + uint8_t fcntselr, + uint8_t cmd, + volatile uint32_t wait_count) +{ + /* Enter Data Flash P/E mode. If failure, return error */ + fsp_err_t err = flash_hp_enter_pe_df_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Select target counter */ + R_FACI_HP->FCNTSELR = fcntselr; + + /* Issue 2-part command to the FACI command-issuing area */ + R_FACI_HP_CMD->FACI_CMD8 = cmd; + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_FINAL; + + /* Wait for FRDY flag or timeout */ + while (1U != R_FACI_HP->FSTATR_b.FRDY) + { + if (wait_count == 0U) + { + err = FSP_ERR_TIMEOUT; + break; + } + + wait_count--; + } + + /* Check for errors and issue forced stop if error occurred */ + err = flash_hp_check_errors(err, 0, err); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * This function will initialize the FCU and set the FCU Clock based on the current FCLK frequency. + * @param p_ctrl Pointer to the instance control block + * @retval FSP_SUCCESS Clock and timeouts configured successfully. + * @retval FSP_ERR_FCLK FCLK is not within the acceptable range. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_init (flash_hp_instance_ctrl_t * p_ctrl) +{ + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + uint32_t flash_clock_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_FCLK); + uint32_t system_clock_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK); + +#if !(BSP_FEATURE_FLASH_HP_VERSION == 4) + + /* Allow Access to the Flash registers*/ + R_SYSTEM->FWEPROR = 0x01U; +#endif + + FSP_ERROR_RETURN(flash_clock_freq_hz >= FLASH_HP_MINIMUM_SUPPORTED_FCLK_FREQ, FSP_ERR_FCLK); + + /* Round up the frequency to a whole number */ + uint32_t flash_clock_freq_mhz = (flash_clock_freq_hz + (FLASH_HP_FREQUENCY_IN_HZ - 1)) / + FLASH_HP_FREQUENCY_IN_HZ; + + /* Round up the frequency to a whole number */ + uint32_t system_clock_freq_mhz = (system_clock_freq_hz + (FLASH_HP_FREQUENCY_IN_HZ - 1)) / + FLASH_HP_FREQUENCY_IN_HZ; + +#if BSP_FEATURE_FLASH_HP_VERSION == 4 + + /* Enable the DataFlash if not already enabled */ + if (1U != R_FACI_LP->DFLCTL) + { + R_FACI_LP->DFLCTL = 1U; + + /* Wait for (tDSTOP) before reading from data flash. + * Refer to the "Data flash STOP recovery time" in the "Data flash characteristics" table from the relevant hardware manual */ + r_flash_hp_delay_ns(FLASH_HP_WAIT_TDSTOP, system_clock_freq_mhz); + } +#endif + + /* Set the Clock */ + R_FACI_HP->FPCKAR = (uint16_t) (FLASH_HP_FPCKAR_KEY + flash_clock_freq_mhz); + + /* According to HW Manual the Max Programming Time for 256 bytes (ROM) + * is 15.8ms. This is with a FCLK of 4MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_cf = (uint32_t) (FLASH_HP_MAX_WRITE_CF_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Programming Time for 4 bytes + * (Data Flash) is 3.8ms. This is with a FCLK of 4MHz. The calculation + * below calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_df = (uint32_t) (FLASH_HP_MAX_WRITE_DF_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Data Buffer Full time for 2 bytes + * is 2 usec. This is with a FCLK of 4MHz. The calculation + * below calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_dbfull = (uint32_t) (FLASH_HP_MAX_DBFULL_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Blank Check time for 4 bytes + * (Data Flash) is 84 usec. This is with a FCLK of 4MHz. The calculation + * below calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_blank_check = (uint32_t) (FLASH_HP_MAX_BLANK_CHECK_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to the device hardware manual the max timeout value when + * using the configuration set command is 515 ms (DF max timeout). This + * is with a FCLK of 4MHz. The calculation below calculates the number + * of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_config = (uint32_t) (FLASH_HP_MAX_WRITE_CONFIG_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for a 64 byte Data Flash block is + * around 18ms. This is with a FCLK of 4MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_erase_df_block = (uint32_t) (FLASH_HP_MAX_ERASE_DF_BLOCK_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for a 32KB block is + * around 1040ms. This is with a FCLK of 4MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_erase_cf_large_block = + (uint32_t) (FLASH_HP_MAX_ERASE_CF_LARGE_BLOCK_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for a 8KB block is + * around 260ms. This is with a FCLK of 4MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_erase_cf_small_block = + (uint32_t) (FLASH_HP_MAX_ERASE_CF_SMALL_BLOCK_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + +#if (BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK == 1) + + /* According to the device HW manual the max timeout value for + * refreshing or incrementing the anti-rollback counter is around 81 ms. + * This is with a FCLK of 4MHz. The calculation below calculates the + * number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_arc_increment_refresh = + (uint32_t) (FLASH_HP_MAX_INCREMENT_REFRESH_COUNTER_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to the device HW manual the max timeout value for + * reading the anti-rollback counter is around 25 ms. This is with + * a FCLK of 4MHz. The calculation below calculates the number of ICLK + * ticks needed for the timeout delay. + */ + p_ctrl->timeout_arc_read = + (uint32_t) (FLASH_HP_MAX_READ_COUNTER_US * system_clock_freq_mhz) / + R_FLASH_HP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; +#endif + + return FSP_SUCCESS; +} + +#if BSP_FEATURE_FLASH_HP_VERSION == 4 + +/*******************************************************************************************************************//** + * Delay for the given number of nano seconds at the given frequency + * + * @note This is used instead of R_BSP_SoftwareDelay because that may be linked in code flash. + * + * @param[in] ns Number of nanoseconds to delay + * @param[in] mhz The frequency of the system clock + **********************************************************************************************************************/ +static void r_flash_hp_delay_ns (uint32_t ns, uint32_t mhz) +{ + uint32_t loop_cnt; + + /* @80 MHz, one loop is 12.5 ns. A delay of 250 ns would require 20 loops. 20 * 12.5 = 250 ns */ + + /* Calculation of a loop count */ + loop_cnt = ((ns * mhz) / (FLASH_HP_DELAY_LOOP_CYCLES * FLASH_HP_DELAY_NS_PER_US)); + + if (loop_cnt > 0U) + { + __asm volatile ("delay_loop:\n" + #if defined(__ICCARM__) || defined(__ARMCC_VERSION) || (defined(__llvm__) && !defined(__CLANG_TIDY__)) + " subs %[loops_remaining], #1 \n" // 1 cycle + #elif defined(__GNUC__) + " sub %[loops_remaining], %[loops_remaining], #1 \n" // 1 cycle + #endif + "cmp %[loops_remaining], #0\n" // 1 cycle + + " bne.n delay_loop \n" // 2 cycles + : // No outputs + :[loops_remaining] "r" (loop_cnt) + : // No clobbers + ); + } +} + +#endif + +/*******************************************************************************************************************//** + * Erase the block at the start address in the control block. + * + * @param p_ctrl Pointer to the instance control block + * @param[in] block_size The block size + * @param[in] timeout The timeout for the block erase + * + * @retval FSP_SUCCESS The erase completed successfully. + * @retval FSP_ERR_TIMEOUT The erase operation timed out. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_erase_block (flash_hp_instance_ctrl_t * const p_ctrl, uint32_t block_size, uint32_t timeout) +{ + /* Set block start address*/ + R_FACI_HP->FSADDR = p_ctrl->source_start_address; + + /* Issue two part Block Erase commands */ + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_BLOCK_ERASE; + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_FINAL; + + p_ctrl->source_start_address += block_size; + + p_ctrl->operations_remaining--; + + /* Wait until the operation has completed or timeout. If timeout stop the flash and return error. */ + + /* Read FRDY bit until it has been set to 1 indicating that the current + * operation is complete.*/ + if (timeout) + { + while (1U != R_FACI_HP->FSTATR_b.FRDY) + { + /* Wait until FRDY is 1 unless timeout occurs. */ + if (timeout == 0U) + { + return FSP_ERR_TIMEOUT; + } + + timeout--; + } + } + + return FSP_SUCCESS; +} + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function erases a specified number of Code Flash blocks + * + * @param p_ctrl Pointer to the control block + * @param[in] block_address The starting address of the first block to erase. + * @param[in] num_blocks The number of blocks to erase. + * + * @retval FSP_SUCCESS Successfully erased (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_ERASE_FAILED Status is indicating a Erase error. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of attempting to Write or Erase an + * area that is protected by an Access Window. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_cf_erase (flash_hp_instance_ctrl_t * p_ctrl, uint32_t block_address, uint32_t num_blocks) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Set current operation parameters */ + p_ctrl->source_start_address = block_address; + p_ctrl->operations_remaining = num_blocks; + uint32_t wait_count; + uint32_t block_size; + + err = flash_hp_enter_pe_cf_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if !(BSP_FEATURE_FLASH_HP_VERSION == 4) + + /* Set Erasure Priority Mode*/ + R_FACI_HP->FCPSR = 1U; + #endif + + while (p_ctrl->operations_remaining && (FSP_SUCCESS == err)) + { + if ((p_ctrl->source_start_address & FLASH_HP_PRV_BANK1_MASK) < BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE) + { + wait_count = p_ctrl->timeout_erase_cf_small_block; + block_size = BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE; + } + else + { + wait_count = p_ctrl->timeout_erase_cf_large_block; + block_size = BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE; + } + + err = flash_hp_erase_block(p_ctrl, block_size, wait_count); + + /* Check the status of the erase operation. */ + err = flash_hp_check_errors(err, FLASH_HP_FSTATR_ERSERR | FLASH_HP_FSTATR_ILGLERR, FSP_ERR_ERASE_FAILED); + } + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +#endif + +#if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function erases a specified number of Code or Data Flash blocks + * + * @param p_ctrl Pointer to the control block + * @param[in] block_address The starting address of the first block to erase. + * @param[in] num_blocks The number of blocks to erase. + * + * @retval FSP_SUCCESS Successfully erased (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_ERASE_FAILED Status is indicating a Erase error. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of attempting to Write or Erase an + * area that is protected by an Access Window. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_df_erase (flash_hp_instance_ctrl_t * p_ctrl, uint32_t block_address, uint32_t num_blocks) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Set current operation parameters */ + p_ctrl->source_start_address = block_address; + p_ctrl->operations_remaining = num_blocks; + uint32_t wait_count; + + err = flash_hp_enter_pe_df_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_PE_FAILURE); + + /* If in BGO mode, exit here; remaining processing if any will be done in ISR */ + if (p_ctrl->p_cfg->data_flash_bgo) + { + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_ERASE; + wait_count = 0; + } + else + { + wait_count = p_ctrl->timeout_erase_df_block; + } + + #if !(BSP_FEATURE_FLASH_HP_VERSION == 4) + + /* Set Erasure Priority Mode*/ + R_FACI_HP->FCPSR = 1U; + #endif + + do + { + err = flash_hp_erase_block(p_ctrl, BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE, wait_count); + + if (p_ctrl->p_cfg->data_flash_bgo) + { + return err; + } + + err = flash_hp_check_errors(err, FLASH_HP_FSTATR_ERSERR, FSP_ERR_ERASE_FAILED); + } while (p_ctrl->operations_remaining && (err == FSP_SUCCESS)); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * This function switches the peripheral from P/E mode for Code Flash or Data Flash to Read mode. + * + * @retval FSP_SUCCESS Successfully entered P/E mode. + * @retval FSP_ERR_PE_FAILURE Failed to exited P/E mode + * @retval FSP_ERR_CMD_LOCKED Flash entered command locked state. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_pe_mode_exit (void) +{ + /* See "Transition to Read Mode" in the Flash Memory section of the relevant hardware manual. */ + /* FRDY and CMDLK are checked after the previous commands complete and do not need to be checked again. */ + fsp_err_t err = FSP_SUCCESS; + fsp_err_t temp_err = FSP_SUCCESS; + uint32_t pe_mode = R_FACI_HP->FENTRYR; + + uint32_t wait_count = FLASH_HP_FRDY_CMD_TIMEOUT; + + /* Transition to Read mode */ + R_FACI_HP->FENTRYR = FLASH_HP_FENTRYR_READ_MODE; + + /* Wait until the flash is in read mode or timeout. If timeout return error. */ + /* Read FENTRYR until it has been set to 0x0000 indicating that we have successfully exited P/E mode.*/ + while (0U != R_FACI_HP->FENTRYR) + { + /* Wait until FENTRYR is 0x0000 unless timeout occurs. */ + if (wait_count == 0U) + { + /* If FENTRYR is not set after max timeout, FSP_ERR_PE_FAILURE*/ + err = FSP_ERR_PE_FAILURE; + } + + wait_count--; + } + + /* If the device is coming out of code flash p/e mode restore the flash cache state. */ + if (FLASH_HP_FENTRYR_CF_PE_MODE == pe_mode) + { +#if BSP_FEATURE_FLASH_HP_HAS_FMEPROT + R_FACI_HP->FMEPROT = FLASH_HP_FMEPROT_LOCK; +#endif + + R_BSP_FlashCacheEnable(); +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_PREFETCH_BUFFER == 1) + R_FACI_LP->PFBER = 1U; +#endif + +#if defined(RENESAS_CORTEX_M85) + + /* Invalidate I-Cache after programming code flash. */ + SCB_InvalidateICache(); +#endif + } + +#ifdef R_CACHE + else if (FLASH_HP_FENTRYR_DF_PE_MODE == pe_mode) + { + /* Flush the C-CACHE. */ + R_CACHE->CCAFCT = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U); + } + else + { + /* Do nothing. */ + } +#endif + + /* If a command locked state was detected earlier, then return that error. */ + if (FSP_ERR_CMD_LOCKED == temp_err) + { + err = temp_err; + } + + return err; +} + +/*******************************************************************************************************************//** + * This function resets the Flash peripheral. + * @param[in] p_ctrl Pointer to the Flash HP instance control block. + * @retval FSP_SUCCESS Reset completed + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal command. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_reset (flash_hp_instance_ctrl_t * p_ctrl) +{ + /* Disable the FACI interrupts, we don't want the reset itself to generate an interrupt */ + if (p_ctrl->p_cfg->data_flash_bgo) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->err_irq); + } + + /* If not in PE mode enter PE mode. */ + if (R_FACI_HP->FENTRYR == 0x0000U) + { + /* Enter P/E mode so that we can execute some FACI commands. Either Code or Data Flash P/E mode would work + * but Code Flash P/E mode requires FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1, which may not be true */ + flash_hp_enter_pe_df_mode(p_ctrl); + } + + /* Issue a Flash Stop to stop any ongoing operation*/ + fsp_err_t err = flash_hp_stop(); + + /* Issue a status clear to clear the locked-command state*/ + fsp_err_t temp_err = flash_hp_status_clear(); + + /* Keep track of and return the first error encountered. */ + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + /* Transition back to Read mode*/ + temp_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + /* Cancel any in progress background operation. */ + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + return err; +} + +/*******************************************************************************************************************//** + * This function is used to force stop the flash during an ongoing operation. + * + * @retval FSP_SUCCESS Successful stop. + * @retval FSP_ERR_TIMEOUT Timeout executing flash_stop. + * @retval FSP_ERR_CMD_LOCKED Peripheral in command locked state. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_stop (void) +{ + /* See "Forced Stop Command" in the Flash Memory section of the relevant hardware manual. If the CMDLK bit + * is still set after issuing the force stop command return an error. */ + volatile uint32_t wait_count = FLASH_HP_FRDY_CMD_TIMEOUT; + + R_FACI_HP_CMD->FACI_CMD8 = (uint8_t) FLASH_HP_FACI_CMD_FORCED_STOP; + + while (1U != R_FACI_HP->FSTATR_b.FRDY) + { + if (wait_count == 0U) + { + return FSP_ERR_TIMEOUT; + } + + wait_count--; + } + + if (0U != R_FACI_HP->FASTAT_b.CMDLK) + { + return FSP_ERR_CMD_LOCKED; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function is used to clear the command-locked state . + * @retval FSP_SUCCESS Successful stop. + * @retval FSP_ERR_TIMEOUT Timeout executing flash_stop.Failed to exited P/E mode + * @retval FSP_ERR_CMD_LOCKED Peripheral in command locked state + **********************************************************************************************************************/ +static fsp_err_t flash_hp_status_clear (void) +{ + /* See "Status Clear Command" in the Flash Memory section of the relevant hardware manual. */ + /* Timeout counter. */ + volatile uint32_t wait_count = FLASH_HP_FRDY_CMD_TIMEOUT; + + /*Issue stop command to flash command area*/ + R_FACI_HP_CMD->FACI_CMD8 = (uint8_t) FLASH_HP_FACI_CMD_STATUS_CLEAR; + + /* Read FRDY bit until it has been set to 1 indicating that the current + * operation is complete.*/ + while (1U != R_FACI_HP->FSTATR_b.FRDY) + { + /* Wait until FRDY is 1 unless timeout occurs. */ + if (wait_count == 0U) + { + + /* This should not happen normally. + * FRDY should get set in 15-20 ICLK cycles on STOP command*/ + return FSP_ERR_TIMEOUT; + } + + wait_count--; + } + + /*Check that Command Lock bit is cleared*/ + if (0U != R_FACI_HP->FASTAT_b.CMDLK) + { + return FSP_ERR_CMD_LOCKED; + } + + return FSP_SUCCESS; +} + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Set up the g_configuration_area_data for writing to the access/startup region of option setting memory. + * + * @param[in] btflg_swap The btflg swap + * @param[in] start_addr The access window start address + * @param[in] end_addr The access window end address + **********************************************************************************************************************/ +static void flash_hp_configuration_area_data_setup (uint32_t btflg_swap, uint32_t start_addr, uint32_t end_addr) +{ + /* Unused bits should be written as 1. */ + g_configuration_area_data[0] = UINT16_MAX; + g_configuration_area_data[1] = UINT16_MAX; + + /* Prepare the configuration data. */ + + /* Bit 15 is BTFLG(Startup Area Select Flag) */ + /* Bits 10:0 are FAWE(Flash Access Window End Block). */ + /* Unused bits should be written as 1. */ + g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_FAWE_BTFLG_OFFSET] = + (uint16_t) (FLASH_HP_FCU_CONFIG_FAWE_BTFLG_UNUSED_BITS | end_addr | (btflg_swap << 15U)); + + /* Bits 10:0 are FAWS(Flash Access Window Start Block). */ + /* Unused bits should be written as 1. */ + g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_FAWS_OFFSET] = + (uint16_t) (FLASH_HP_FCU_CONFIG_FAWS_UNUSED_BITS | start_addr); + + g_configuration_area_data[4] = UINT16_MAX; + g_configuration_area_data[5] = UINT16_MAX; + g_configuration_area_data[6] = UINT16_MAX; + g_configuration_area_data[7] = UINT16_MAX; +} + +#endif + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Configure an access window for the Code Flash memory using the provided start and end address. An access window + * defines a contiguous area in Code Flash for which programming/erase is enabled. This area is on block boundaries. The + * block containing start_addr is the first block. The block containing end_addr is the last block. The access window + * then becomes first block - last block inclusive. Anything outside this range of Code Flash is then write protected. + * This command DOES modify the configuration via The Configuration Set command to update the FAWS and FAWE. + * + * @param p_ctrl Pointer to the control block + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. + * + * @retval FSP_SUCCESS Access window successfully configured. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal + * command. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_access_window_set (flash_hp_instance_ctrl_t * p_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) +{ + uint32_t btflg = R_FACI_HP->FAWMON_b.BTFLG; + + /* Update Flash state and enter Code Flash P/E mode */ + fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Configure the configuration area to be written. */ + flash_hp_configuration_area_data_setup(btflg, start_addr >> 13U, end_addr >> 13U); + + /* Write the configuration area to the access/startup region. */ + err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP, g_configuration_area_data); + + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +#endif + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Modifies the start-up program swap flag (BTFLG) based on the supplied parameters. These changes will take effect on + * the next reset. This command DOES modify the configuration via The Configuration Set command to update the BTFLG. + * + * @param p_ctrl Pointer to the instance control block. + * @param[in] swap_type The swap type Alternate or Default. + * @param[in] is_temporary Indicates if the swap should be temporary or permanent. + * + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal + * command. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_set_startup_area_boot (flash_hp_instance_ctrl_t * p_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary) +{ + /* Update Flash state and enter Code Flash P/E mode */ + fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + if (is_temporary) + { + R_FACI_HP->FSUACR = (uint16_t) (FLASH_HP_FSUACR_KEY | swap_type); + } + else + { + #if BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW + + /* Do not call functions with multiple volatile parameters. */ + uint32_t faws = R_FACI_HP->FAWMON_b.FAWS; + uint32_t fawe = R_FACI_HP->FAWMON_b.FAWE; + + /* Configure the configuration area to be written. */ + flash_hp_configuration_area_data_setup(~swap_type & 0x1, faws, fawe); + #else + memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); + + g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_FAWE_BTFLG_OFFSET] = + (uint16_t) (((((uint16_t) ~swap_type) & 0x1U) << 15U) | FLASH_HP_OFS_SAS_MASK); + #endif + + /* Write the configuration area to the access/startup region. */ + err = flash_hp_configuration_area_write(p_ctrl, + FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP, + g_configuration_area_data); + + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + } + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +#endif + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1) + +/*******************************************************************************************************************//** + * Set the ID code. + * + * @param p_ctrl Pointer to the control block + * @param p_id_code The identifier code + * @param[in] mode ID code mode + * + * @retval FSP_SUCCESS Set Configuration successful + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit Code Flash P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_CMD_LOCKED FCU is in locked state, typically as a result of having received an illegal + * command. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_set_id_code (flash_hp_instance_ctrl_t * p_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) +{ + uint32_t * temp = (uint32_t *) p_id_code; + uint32_t * temp_area = (uint32_t *) g_configuration_area_data; + + /* Update Flash state and enter the required P/E mode specified by the hardware manual. */ + fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Configure the configuration area to be written. If the mode is unlocked write all 0xFF. */ + for (uint32_t index = 0U; index < 4U; index++) + { + if (FLASH_ID_CODE_MODE_UNLOCKED == mode) + { + temp_area[index] = UINT32_MAX; + } + else + { + temp_area[index] = temp[index]; + } + } + + /* If the mode is not unlocked set bits 126 and 127 accordingly. */ + if (FLASH_ID_CODE_MODE_UNLOCKED != mode) + { + g_configuration_area_data[FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT_CF - 1U] |= (uint16_t) mode; + } + + /* Write the configuration area to the access/startup region. */ + err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_ID_BYTE, g_configuration_area_data); + + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +#endif + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) || ((FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && \ + (BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE > 0)) + +/*******************************************************************************************************************//** + * Execute the Configuration Set Command: sequence + * + * @param p_ctrl Pointer to the control block + * @param[in] fsaddr Flash address to be written to. + * @param[in] src_address Pointer to the data to write to the configuration area. + * + * @retval FSP_SUCCESS Configuration Set successful + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_configuration_area_write (flash_hp_instance_ctrl_t * p_ctrl, + uint32_t fsaddr, + uint16_t * src_address) +{ + volatile uint32_t timeout = p_ctrl->timeout_write_config; + uint8_t faci_config_set_2 = FLASH_HP_FACI_CMD_CONFIG_SET_2_CF; + uint32_t access_word_count = FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT_CF; + + #if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE > 0) + if (fsaddr >= BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START) + { + faci_config_set_2 = FLASH_HP_FACI_CMD_CONFIG_SET_2_DF; + access_word_count = FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT_DF; + } + #endif + + /* See "Configuration Set Command" in the Flash Memory section of the relevant hardware manual. */ + R_FACI_HP->FSADDR = fsaddr; + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_CONFIG_SET_1; + R_FACI_HP_CMD->FACI_CMD8 = faci_config_set_2; + + /* Write the configuration data. */ + for (uint32_t index = 0U; index < access_word_count; index++) + { + /* There are 8 16 bit halfwords that must be written to accomplish a configuration set */ + R_FACI_HP_CMD->FACI_CMD16 = src_address[index]; + } + + R_FACI_HP_CMD->FACI_CMD8 = FLASH_HP_FACI_CMD_FINAL; + + while (1U != R_FACI_HP->FSTATR_b.FRDY) + { + if (timeout <= 0U) + { + return FSP_ERR_TIMEOUT; + } + + timeout--; + } + + return FSP_SUCCESS; +} + +#endif + +#if (((FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE > 0)) == 1) + +/*******************************************************************************************************************//** + * Write user data to the user lockable area + * + * @param p_ctrl Pointer to the control block + * @param src_address Pointer to the data to write to the configuration area. Data length must a multiple of the + * write size. + * @param flash_address Flash address to be written to. + * @param num_bytes Number of bytes to write. Must be a multiple of the write size. + * + * @retval FSP_SUCCESS Configuration Set successful + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_user_lockable_area_write (flash_hp_instance_ctrl_t * p_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes) +{ + fsp_err_t err; + err = flash_hp_enter_pe_df_mode(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + uint32_t operations_remaining = num_bytes / BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE; + uint16_t * p_src = (uint16_t *) src_address; + + do + { + /* Write the minimum write size to the lockable area */ + err = flash_hp_configuration_area_write(p_ctrl, flash_address, p_src); + + /* Check for errors that may have occurred during the write */ + err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED); + + flash_address += BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE; + p_src += BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE / sizeof(p_src[0]); + operations_remaining--; + } while ((operations_remaining) && (err == FSP_SUCCESS)); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = flash_hp_pe_mode_exit(); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +#endif + +/** If BGO is being used then we require both interrupts to be enabled (RDY and ERR). If either one + * is not enabled then don't generate any ISR routines */ + +/*******************************************************************************************************************//** + * FLASH error interrupt routine. + * + * This function implements the FLASH error isr. The function clears the interrupt request source on entry populates the + * callback structure with the FLASH_IRQ_EVENT_ERR_ECC event, and providing a callback routine has been provided, calls + * the callback function with the event. + **********************************************************************************************************************/ +void fcu_fiferr_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + flash_event_t event; + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t fastat = R_FACI_HP->FASTAT; + uint32_t fstatr_errors = R_FACI_HP->FSTATR & FLASH_HP_FSTATR_ERROR_MASK; + + /* The flash access error interrupt register has fired. */ + /* Check for the data flash memory access violation flag. */ + if (fastat & FLASH_HP_FASTAT_DFAE) + { + event = FLASH_EVENT_ERR_DF_ACCESS; + } + /* Check for the code flash memory access violation flag. */ + else if (fastat & FLASH_HP_FASTAT_CFAE) + { + event = FLASH_EVENT_ERR_CF_ACCESS; + } + /* Check if the command Lock bit is set. */ + else if (fastat & FLASH_HP_FASTAT_CMDLK) + { + if (fstatr_errors & (FLASH_HP_FSTATR_PRGERR | FLASH_HP_FSTATR_ERSERR)) + { + event = FLASH_EVENT_ERR_FAILURE; + } + else + { + event = FLASH_EVENT_ERR_CMD_LOCKED; + } + } + else + { + event = FLASH_EVENT_ERR_FAILURE; + } + + /* Reset the FCU: This will stop any existing processes and exit PE mode*/ + flash_hp_reset(p_ctrl); + + /* Clear the Error Interrupt. */ + R_BSP_IrqStatusClear(irq); + + /* Call the user callback. */ + r_flash_hp_call_callback(p_ctrl, event); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * FLASH ready interrupt routine. + * + * This function implements the FLASH ready isr. The function clears the interrupt request source on entry populates the + * callback structure with the relevant event, and providing a callback routine has been provided, calls the callback + * function with the event. + **********************************************************************************************************************/ +void fcu_frdyi_isr (void) +{ + FSP_CONTEXT_SAVE + bool operation_completed = false; + + /*Wait counter used for DBFULL flag*/ + flash_event_t event; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the Interrupt Request*/ + R_BSP_IrqStatusClear(irq); + + /* A reset of the FACI with a BGO operation in progress may still generate a single interrupt + * subsequent to the reset. We want to ignore that */ + + /* Continue the current operation. If unknown operation set callback event to failure. */ + if (FLASH_OPERATION_DF_BGO_WRITE == p_ctrl->current_operation) + { + /* If there are still bytes to write */ + if (p_ctrl->operations_remaining) + { + fsp_err_t err = flash_hp_write_data(p_ctrl, BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE, 0); + + if (FSP_SUCCESS != err) + { + flash_hp_reset(p_ctrl); + event = FLASH_EVENT_ERR_FAILURE; + } + } + /*Done writing all bytes*/ + else + { + event = FLASH_EVENT_WRITE_COMPLETE; + operation_completed = true; + } + } + else if ((FLASH_OPERATION_DF_BGO_ERASE == p_ctrl->current_operation)) + { + if (p_ctrl->operations_remaining) + { + flash_hp_erase_block(p_ctrl, BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE, 0); + } + /* If all blocks are erased*/ + else + { + event = FLASH_EVENT_ERASE_COMPLETE; + operation_completed = true; + } + } + else + { + /* Blank check is a single operation */ + operation_completed = true; + if (R_FACI_HP->FBCSTAT == 0x01U) + { + event = FLASH_EVENT_NOT_BLANK; + } + else + { + event = FLASH_EVENT_BLANK; + } + } + + /* If the current operation has completed exit pe mode, release the software lock and call the user callback if used. */ + if (operation_completed == true) + { + /* finished current operation. Exit P/E mode*/ + flash_hp_pe_mode_exit(); + + /* Release lock and Set current state to Idle*/ + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + /* Set data to identify callback to user, then call user callback. */ + r_flash_hp_call_callback(p_ctrl, event); + } + + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to FLASH_HP instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_flash_hp_call_callback (flash_hp_instance_ctrl_t * p_ctrl, flash_event_t event) +{ + flash_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + flash_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->data = 0U; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + flash_hp_prv_ns_callback p_callback = (flash_hp_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * This function switches the peripheral to P/E mode for Data Flash. + * @param[in] p_ctrl Pointer to the Flash control block. + * @retval FSP_SUCCESS Successfully entered Data Flash P/E mode. + * @retval FSP_ERR_PE_FAILURE Failed to enter Data Flash P/E mode. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_enter_pe_df_mode (flash_hp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + /* See "Transition to Data Flash P/E Mode" in the Flash Memory section of the relevant hardware manual. */ + /* Timeout counter. */ + volatile uint32_t wait_count = FLASH_HP_FRDY_CMD_TIMEOUT; + + /* If BGO mode is enabled and interrupts are being used then enable interrupts. */ + if (p_ctrl->p_cfg->data_flash_bgo == true) + { + /* We are supporting Flash Rdy interrupts for Data Flash operations. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->irq); + + /* We are supporting Flash Err interrupts for Data Flash operations. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->err_irq); + } + + /* Enter Data Flash PE mode. */ + R_FACI_HP->FENTRYR = FLASH_HP_FENTRYR_TRANSITION_TO_DF_PE; + + /* Wait for the operation to complete or timeout. If timeout return error. */ + /* Read FENTRYR until it has been set to 0x0080 indicating that we have successfully entered P/E mode.*/ + while (FLASH_HP_FENTRYR_DF_PE_MODE != R_FACI_HP->FENTRYR) + { + /* Wait until FENTRYR is 0x0080 unless timeout occurs. */ + if (wait_count == 0U) + { + + /* if FENTRYR is not set after max timeout return an error. */ + return FSP_ERR_PE_FAILURE; + } + + wait_count--; + } + + return err; +} + +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function switches the peripheral to P/E mode for Code Flash. + * @param[in] p_ctrl Pointer to the Flash control block. + * @retval FSP_SUCCESS Successfully entered Code Flash P/E mode. + * @retval FSP_ERR_PE_FAILURE Failed to enter Code Flash P/E mode. + **********************************************************************************************************************/ +static fsp_err_t flash_hp_enter_pe_cf_mode (flash_hp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + /* See "Transition to Code Flash P/E Mode" in the Flash Memory section of the relevant hardware manual. */ + /* Timeout counter. */ + volatile uint32_t wait_count = FLASH_HP_FRDY_CMD_TIMEOUT; + + /* While the Flash API is in use we will disable the flash cache. */ + #if BSP_FEATURE_FLASH_HP_FCACHE_DISABLE_BEFORE_PE + + /* Disable the FCACHE, except for Star/RA40MCU devices that have errata. */ + R_FCACHE->FCACHEE = 0U; + #endif + + #if defined(R_CACHE) + + /* Disable the C-Cache. */ + R_CACHE->CCACTL = 0U; + #endif + #if BSP_FEATURE_FLASH_PREFETCH_BUFFER + R_FACI_LP->PFBER = 0U; + #endif + + /* If interrupts are being used then disable interrupts. */ + if (p_ctrl->p_cfg->data_flash_bgo == true) + { + /* We are not supporting Flash Rdy interrupts for Code Flash operations */ + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + + /* We are not supporting Flash Err interrupts for Code Flash operations */ + R_BSP_IrqDisable(p_ctrl->p_cfg->err_irq); + } + + #if BSP_FEATURE_FLASH_HP_HAS_FMEPROT + R_FACI_HP->FMEPROT = FLASH_HP_FMEPROT_UNLOCK; + #endif + + /* Enter code flash PE mode */ + R_FACI_HP->FENTRYR = FLASH_HP_FENTRYR_TRANSITION_TO_CF_PE; + + /* Wait for the operation to complete or timeout. If timeout return error. */ + /* Read FENTRYR until it has been set to 0x0001 indicating that we have successfully entered CF P/E mode.*/ + while (FLASH_HP_FENTRYR_CF_PE_MODE != R_FACI_HP->FENTRYR) + { + /* Wait until FENTRYR is 0x0001UL unless timeout occurs. */ + if (wait_count == 0U) + { + + /* if FENTRYR is not set after max timeout, FSP_ERR_PE_FAILURE*/ + return FSP_ERR_PE_FAILURE; + } + + wait_count--; + } + + return err; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_flash_lp/r_flash_lp.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_flash_lp/r_flash_lp.c new file mode 100644 index 0000000000..348603b3b7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_flash_lp/r_flash_lp.c @@ -0,0 +1,2756 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include + +#include "r_flash_lp.h" + +/* Configuration for this package. */ +#include "r_flash_lp_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "OPEN" in ASCII, used to avoid multiple open. */ +#define FLASH_HP_OPEN (0x4f50454eULL) + +#define FLASH_HP_MINIMUM_SUPPORTED_FCLK_FREQ (4000000U) /// Minimum FCLK for Flash Operations in Hz + +/* The number of CPU cycles per each timeout loop. */ +#ifndef FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP + #if defined(__GNUC__) + #define FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP (6U) + #elif defined(__ICCARM__) + #define FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP (6U) + #endif +#endif + +#define FLASH_LP_HZ_IN_MHZ (1000000U) + +#if defined(__ICCARM__) + #define BSP_ATTRIBUTE_STACKLESS __stackless +#elif defined(__GNUC__) + + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) +#endif + +/* Roughly 4 cycles per loop */ +#define FLASH_LP_DELAY_LOOP_CYCLES 4U + +/* flash mode definition (FENTRYR Register setting)*/ +#define FLASH_LP_FENTRYR_DATAFLASH_PE_MODE (0xAA80U) +#define FLASH_LP_FENTRYR_CODEFLASH_PE_MODE (0xAA01U) +#define FLASH_LP_FENTRYR_READ_MODE (0xAA00U) + +/* flash mode definition (FPMCR Register setting)*/ +#define FLASH_LP_DATAFLASH_PE_MODE (0x10U) +#define FLASH_LP_READ_MODE (0x08U) +#define FLASH_LP_LVPE_MODE (0x40U) +#define FLASH_LP_DISCHARGE_1 (0x12U) +#define FLASH_LP_DISCHARGE_2 (0x92U) +#define FLASH_LP_CODEFLASH_PE_MODE (0x82U) + +/* operation definition (FCR Register setting)*/ +#define FLASH_LP_FCR_WRITE (0x81U) +#define FLASH_LP_FCR_ERASE (0x84U) +#define FLASH_LP_FCR_BLANKCHECK (0x83U) +#define FLASH_LP_FCR_CLEAR (0x00U) + +/* operation definition (FEXCR Register setting)*/ +#define FLASH_LP_FEXCR_STARTUP (0x81U) +#define FLASH_LP_FEXCR_AW (0x82U) +#define FLASH_LP_FEXCR_OCDID1 (0x83U) +#define FLASH_LP_FEXCR_OCDID2 (0x84U) +#define FLASH_LP_FEXCR_OCDID3 (0x85U) +#define FLASH_LP_FEXCR_OCDID4 (0x86U) +#define FLASH_LP_FEXCR_CLEAR (0x00U) +#define FLASH_LP_FEXCR_MF4_CONTROL (0x81U) +#define FLASH_LP_FEXCR_MF4_AW_STARTUP (0x82U) + +/* Wait Process definition */ +#define FLASH_LP_WAIT_TDIS (3U) +#if (BSP_FEATURE_FLASH_LP_VERSION == 4) + #define FLASH_LP_WAIT_TMS_HIGH (16U) // "Flash memory mode transition wait time 2" in the "Code Flash Memory Characteristics" subsection of the hardware manual +#else + #define FLASH_LP_WAIT_TMS_HIGH (6U) // tMS wait time on flash version 3 +#endif +#define FLASH_LP_WAIT_TMS_MID (4U) +#define FLASH_LP_WAIT_TDSTOP (6U) + +/* Flash information */ +/* Used for DataFlash */ +#define FLASH_LP_DATAFLASH_READ_BASE_ADDR (0x40100000U) +#define FLASH_LP_DATAFLASH_WRITE_BASE_ADDR (0xFE000000U) +#define FLASH_LP_DATAFLASH_ADDR_OFFSET (FLASH_LP_DATAFLASH_WRITE_BASE_ADDR - \ + FLASH_LP_DATAFLASH_READ_BASE_ADDR) + +#define FLASH_LP_FENTRYR_DF_PE_MODE (0x0080U) +#define FLASH_LP_FENTRYR_CF_PE_MODE (0x0001U) +#define FLASH_LP_FENTRYR_PE_MODE_BITS (FLASH_LP_FENTRYR_DF_PE_MODE | FLASH_LP_FENTRYR_CF_PE_MODE) + +#if BSP_FEATURE_FLASH_LP_VERSION == 4 + #define FLASH_LP_PRV_FENTRYR R_FACI_LP->FENTRYR_MF4 +#else + #define FLASH_LP_PRV_FENTRYR R_FACI_LP->FENTRYR +#endif + +#define FLASH_LP_FSCMR_FSPR_AND_UNUSED_BITS (0xFEFFU) + +#define FLASH_LP_MF4_FAWEMR_STARTUP_AREA_MASK (0x8000U) + +#define FLASH_LP_FCR_PROCESSING_MASK (0x80U) +#define FLASH_LP_FEXCR_PROCESSING_MASK (0x80U) + +#define FLASH_LP_MAX_WRITE_CF_TIME_US (1411) +#define FLASH_LP_MAX_WRITE_DF_TIME_US (886) +#define FLASH_LP_MAX_BLANK_CHECK_TIME_US (88) +#define FLASH_LP_MAX_ERASE_CF_BLOCK_TIME_US (355000) +#define FLASH_LP_MAX_ERASE_DF_BLOCK_TIME_US (504000) +#define FLASH_LP_MAX_WRITE_EXTRA_AREA_TIME_US (2289000) + +#define FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS (0x10) +#define FLASH_LP_FSTATR2_ERASE_ERROR_BITS (0x11) +#define FLASH_LP_FSTATR2_WRITE_ERROR_BITS 0x12 + +#define FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ (32) + +#define FLASH_LP_3BIT_MASK (0x7U) +#define FLASH_LP_6BIT_MASK (0x3FU) +#define FLASH_LP_5BIT_MASK (0x1FU) + +#define FLASH_LP_DF_START_ADDRESS (0x40100000) + +#define FLASH_LP_FPR_UNLOCK (0xA5U) + +#define FLASH_LP_BANK_PROGRAMMING_EXIT (0x6D00) +#define FLASH_LP_BANK_PROGRAMMING_ENTER (0x6D01) + +#define FLASH_LP_BANK_SWAP_UPDATE_ENABLE (0xC301) +#define FLASH_LP_BANK_SWAP_UPDATE_DISABLE (0xC300) +#define FLASH_LP_EXTRA_AREA_FCTLF_ADDRESS (0x01010008) + +/** The maximum timeout for commands is 100usec when FCLK is 16 MHz i.e. 1600 FCLK cycles. + * Assuming worst case of ICLK at 240 MHz and FCLK at 4 MHz, and optimization set to max such that + * each count decrement loop takes only 5 cycles, then ((240/4)*1600)/5 = 19200 */ +#define FLASH_LP_FRDY_CMD_TIMEOUT (19200) + +#define FLASH_LP_REGISTER_WAIT_TIMEOUT(val, reg, timeout, err) \ + while (val != reg) \ + { \ + if (0 == timeout) \ + { \ + return err; \ + } \ + timeout--; \ + } + +/** Flash P/E related functions are not required to be in RAM when using Bank Programming. */ +#if (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 0) + #define FLASH_PE_PLACE_IN_RAM_SECTION PLACE_IN_RAM_SECTION +#else + #define FLASH_PE_PLACE_IN_RAM_SECTION +#endif + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/** + * @struct r_dataflash_data_t + * DATAFLASH information values + */ +typedef struct r_dataflash_data_t +{ + uint32_t start_addr; /* start address (Erase) or Ram Source for Write, Dest for read */ + uint32_t end_addr; /* end address (Erase), or Flash Start address which will be read/written */ + uint32_t write_cnt; /* bytes remaining to do */ +} r_dataflash_data_t; + +typedef struct r_dataflash_erase_t +{ + uint32_t start_addr; /* start address (Erase) or Ram Source for Write, Dest for read */ + uint32_t end_addr; /* end address (Erase), or Flash Start address which will be read/written */ + uint32_t write_cnt; /* bytes remaining to do */ +} r_dataflash_erase_t; + +/** FLASH operation command values */ +typedef enum e_flash_command +{ + FLASH_COMMAND_ACCESSWINDOW, /**< Flash access window command */ + FLASH_COMMAND_STARTUPAREA /**< Flash change startup area command */ +} r_flash_command_t; + +/****************************************************************************** + * Exported global variables + ******************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_flash_lp_init(flash_lp_instance_ctrl_t * p_ctrl); + +static void r_flash_lp_df_enter_pe_mode(flash_lp_instance_ctrl_t * const p_ctrl); + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +static void r_flash_lp_df_write_operation(flash_lp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_flash_lp_df_blankcheck(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t start_address, + uint32_t num_bytes, + flash_result_t * result); + +static fsp_err_t r_flash_lp_df_erase(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t block_address, + uint32_t num_blocks); + +#endif + +static fsp_err_t r_flash_lp_set_fisr(flash_lp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_flash_lp_setup(flash_lp_instance_ctrl_t * p_ctrl); + +static void r_flash_lp_process_command(const uint32_t start_addr, uint32_t num_bytes, + uint32_t command) FLASH_PE_PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_command_finish(uint32_t timeout) FLASH_PE_PLACE_IN_RAM_SECTION; + +static void r_flash_lp_reset(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_wait_for_ready(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t timeout, + uint32_t error_bits, + fsp_err_t return_code) FLASH_PE_PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_write(flash_lp_instance_ctrl_t * const p_ctrl) FLASH_PE_PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_pe_mode_exit(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + +static void r_flash_lp_delay_us(uint32_t us, uint32_t mhz) PLACE_IN_RAM_SECTION __attribute__((noinline)); + +static void r_flash_lp_write_fpmcr(uint8_t value) PLACE_IN_RAM_SECTION; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) +static void r_flash_lp_memcpy(uint8_t * const dest, uint8_t * const src, uint32_t len) FLASH_PE_PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_extra_command_finish(uint32_t timeout) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_cf_blankcheck(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t start_address, + uint32_t num_bytes, + flash_result_t * result) FLASH_PE_PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_cf_erase(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t block_address, + uint32_t num_blocks, + uint32_t block_size) FLASH_PE_PLACE_IN_RAM_SECTION; + +static void r_flash_lp_cf_write_operation(flash_lp_instance_ctrl_t * const p_ctrl) FLASH_PE_PLACE_IN_RAM_SECTION; + +static void r_flash_lp_cf_enter_pe_mode(flash_lp_instance_ctrl_t * const p_ctrl, bool bank_programming) +PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_extra_check(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_set_startup_area_boot(flash_lp_instance_ctrl_t * const p_ctrl, + flash_startup_area_swap_t swap_type, + bool temporary) +PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_access_window_set(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) PLACE_IN_RAM_SECTION; + +static fsp_err_t r_flash_lp_set_id_code(flash_lp_instance_ctrl_t * const p_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) PLACE_IN_RAM_SECTION; + +static void r_flash_lp_extra_operation(const uint32_t start_addr_startup_value, + const uint32_t end_addr, + r_flash_command_t command) PLACE_IN_RAM_SECTION; + + #if (BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK == 1) +static fsp_err_t r_flash_lp_bank_swap(flash_lp_instance_ctrl_t * const p_ctrl) PLACE_IN_RAM_SECTION; + + #endif + +#endif + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + +static fsp_err_t r_flash_lp_common_parameter_checking(flash_lp_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_flash_lp_write_read_bc_parameter_checking(flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t flash_address, + uint32_t const num_bytes, + bool check_write); + +#endif + +/** FRDY ISR is only used for DataFlash operations and Code flash operations when Bank Programming is supported. + * Other Code flash operations are blocking. Therefore ISR does not need to be located in RAM. + */ +void fcu_frdyi_isr(void); + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +const flash_api_t g_flash_on_flash_lp = +{ + .open = R_FLASH_LP_Open, + .close = R_FLASH_LP_Close, + .write = R_FLASH_LP_Write, + .erase = R_FLASH_LP_Erase, + .blankCheck = R_FLASH_LP_BlankCheck, + .statusGet = R_FLASH_LP_StatusGet, + .infoGet = R_FLASH_LP_InfoGet, + .accessWindowSet = R_FLASH_LP_AccessWindowSet, + .accessWindowClear = R_FLASH_LP_AccessWindowClear, + .idCodeSet = R_FLASH_LP_IdCodeSet, + .reset = R_FLASH_LP_Reset, + .startupAreaSelect = R_FLASH_LP_StartUpAreaSelect, + .bankSwap = R_FLASH_LP_BankSwap, + .updateFlashClockFreq = R_FLASH_LP_UpdateFlashClockFreq, + .callbackSet = R_FLASH_LP_CallbackSet, + .antiRollbackCounterIncrement = R_FLASH_LP_AntiRollbackCounterIncrement, + .antiRollbackCounterRefresh = R_FLASH_LP_AntiRollbackCounterRefresh, + .antiRollbackCounterRead = R_FLASH_LP_AntiRollbackCounterRead, + .userLockableAreaWrite = R_FLASH_LP_UserLockableAreaWrite, +}; + +const flash_block_info_t g_code_flash_macro_info = +{ + .block_section_st_addr = 0, + .block_section_end_addr = BSP_ROM_SIZE_BYTES - 1, + .block_size = BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE, + .block_size_write = BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE +}; + +static flash_regions_t g_flash_code_region = +{ + .num_regions = 1, + .p_block_array = &g_code_flash_macro_info +}; + +const flash_block_info_t g_data_flash_macro_info = +{ + .block_section_st_addr = FLASH_LP_DF_START_ADDRESS, + .block_section_end_addr = FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES - 1, + .block_size = BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE, + .block_size_write = BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE +}; + +static flash_regions_t g_flash_data_region = +{ + .num_regions = 1, + .p_block_array = &g_data_flash_macro_info +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup FLASH_LP + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize the Low Power flash peripheral. Implements @ref flash_api_t::open. + * + * The Open function initializes the Flash. + * + * This function must be called once prior to calling any other FLASH API functions. If a user supplied callback + * function is supplied, then the Flash Ready interrupt will be configured to call the users callback routine with an + * Event type describing the source of the interrupt for Data Flash operations. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_Open + * + * @note Providing a callback function in the supplied p_cfg->callback field automatically configures the Flash + * for Data Flash to operate in non-blocking background operation (BGO) mode. + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl, p_cfg or p_callback if BGO is enabled. + * @retval FSP_ERR_IRQ_BSP_DISABLED Caller is requesting BGO but the Flash interrupts are not enabled. + * @retval FSP_ERR_FCLK FCLK must be a minimum of 4 MHz for Flash operations. + * @retval FSP_ERR_ALREADY_OPEN Flash Open() has already been called. + * @retval FSP_ERR_TIMEOUT Failed to exit P/E mode after configuring flash. + * @retval FSP_ERR_INVALID_STATE The system is not running from the required clock or the required clock is not running and stable. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Open (flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + + /* If null pointers return error. */ +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + + /* If open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN != p_ctrl->opened), FSP_ERR_ALREADY_OPEN); + #if BSP_FEATURE_FLASH_LP_VERSION == 4 + + /* MF4 devices must have HOCO running and stable in order to program and erase flash. */ + #if BSP_FEATURE_CGC_REGISTER_SET_B + + /* HOCO is selected when ICLK source is FMAIN, FMAIN source is FOCO, and FOCO source is HOCO. */ + FSP_ERROR_RETURN((0U == R_SYSTEM->ICLKSCR_b.CKST) && + (0U == R_SYSTEM->FMAINSCR_b.CKST) && + (0U == R_SYSTEM->FOCOSCR_b.CKST), + FSP_ERR_INVALID_STATE); + #else + + /* If HOCO is not operating, return error */ + FSP_ERROR_RETURN(0U == R_SYSTEM->HOCOCR_b.HCSTP, FSP_ERR_INVALID_STATE); + + /* If HOCO is not stable, return error */ + FSP_ERROR_RETURN(1U == R_SYSTEM->OSCSF_b.HOCOSF, FSP_ERR_INVALID_STATE); + #endif + #endif + + #if FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1 || FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1 + + /* Background operations are enabled but the flash interrupt is disabled. */ + if (p_cfg->data_flash_bgo || (1U == FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE)) + { + FSP_ERROR_RETURN(p_cfg->irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ASSERT(NULL != p_cfg->p_callback); + } + #endif +#endif + p_ctrl->p_cfg = p_cfg; + +#if FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1 || FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1 + if (p_cfg->data_flash_bgo || (1U == FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE)) + { + R_BSP_IrqCfg(p_cfg->irq, p_cfg->ipl, p_ctrl); + } +#endif + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + /* Check FCLK, calculate timeout values. */ + err = r_flash_lp_setup(p_ctrl); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + /* Set the FlashIF peripheral clock frequency. */ + err = r_flash_lp_set_fisr(p_ctrl); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + p_ctrl->opened = FLASH_HP_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Write to the specified Code or Data Flash memory area. Implements @ref flash_api_t::write. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_Write + * + * @retval FSP_SUCCESS Operation successful. If BGO is enabled this means the operation was started + * successfully. + * @retval FSP_ERR_IN_USE The Flash peripheral is busy with a prior on-going transaction. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. This may + * be returned if the requested Flash area is not blank. + * @retval FSP_ERR_TIMEOUT Timed out waiting for FCU operation to complete. + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was not a multiple of the programming size or exceeded + * the maximum range. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Write (flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Check parameters. If failure return error */ + err = r_flash_lp_write_read_bc_parameter_checking(p_ctrl, flash_address, num_bytes, true); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); +#endif + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + if (flash_address < BSP_ROM_SIZE_BYTES) + { + #if FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1 + + /* Verify the source address is not in BANK1 of code flash. It will not be available in P/E mode. */ + FSP_ERROR_RETURN((src_address > BSP_ROM_SIZE_BYTES) || ((src_address + num_bytes) < (BSP_ROM_SIZE_BYTES / 2)), + FSP_ERR_INVALID_ADDRESS); + + /* The target flash area must be in Bank1 when using Bank Programming. */ + FSP_ERROR_RETURN(flash_address >= (BSP_FEATURE_FLASH_CODE_FLASH_START + (BSP_ROM_SIZE_BYTES / 2)), + FSP_ERR_INVALID_ADDRESS); + #else + + /* Verify the source address is not in code flash. It will not be available in P/E mode. */ + FSP_ASSERT(src_address > BSP_ROM_SIZE_BYTES); + #endif + } +#endif + + p_ctrl->dest_end_address = flash_address; + p_ctrl->source_start_address = src_address; + p_ctrl->operations_remaining = num_bytes; + + err = r_flash_lp_write(p_ctrl); + + /* Return status. */ + return err; +} + +/*******************************************************************************************************************//** + * Erase the specified Code or Data Flash blocks. Implements @ref flash_api_t::erase. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_Erase + * + * @retval FSP_SUCCESS Successful open. + * @retval FSP_ERR_INVALID_BLOCKS Invalid number of blocks specified + * @retval FSP_ERR_INVALID_ADDRESS Invalid address specified + * @retval FSP_ERR_IN_USE Other flash operation in progress, or API not initialized + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_TIMEOUT Timed out waiting for FCU to be ready. + * @retval FSP_ERR_ERASE_FAILED Status is indicating a Erase error. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Erase (flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If invalid number of blocks return error. */ + FSP_ERROR_RETURN(num_blocks != 0U, FSP_ERR_INVALID_BLOCKS); +#endif + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + + /* Configure the current parameters based on if the operation is for code flash or data flash. */ + if (address < BSP_ROM_SIZE_BYTES) + { + uint32_t start_address = address & ~(BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE - 1); + + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + uint32_t num_bytes = num_blocks * BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE; + + #if FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1 + + /* Verify start address is in BANK1 */ + FSP_ERROR_RETURN(start_address >= (BSP_FEATURE_FLASH_CODE_FLASH_START + (BSP_ROM_SIZE_BYTES / 2)), + FSP_ERR_INVALID_ADDRESS); + #endif + + /* Verify erase will not write past end of code flash */ + FSP_ERROR_RETURN((start_address + num_bytes) <= (BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES), + FSP_ERR_INVALID_BLOCKS); + #endif + + err = r_flash_lp_cf_erase(p_ctrl, start_address, num_blocks, BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE); + } + else +#endif + { +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + uint32_t start_address = address & ~(BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE - 1); + + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + uint32_t num_bytes = num_blocks * BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE; + + FSP_ERROR_RETURN((start_address >= (FLASH_LP_DF_START_ADDRESS)) && + (start_address < (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERR_INVALID_ADDRESS); + + FSP_ERROR_RETURN(start_address + num_bytes <= (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES), + FSP_ERR_INVALID_BLOCKS); + #endif + + /* Initiate the flash erase. */ + err = r_flash_lp_df_erase(p_ctrl, start_address, num_blocks); +#else + + return FSP_ERR_INVALID_ADDRESS; +#endif + } + + return err; +} + +/*******************************************************************************************************************//** + * Perform a blank check on the specified address area. Implements @ref flash_api_t::blankCheck. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_BlankCheck + * + * @retval FSP_SUCCESS Blankcheck operation completed with result in p_blank_check_result, or + * blankcheck started and in-progess (BGO mode). + * @retval FSP_ERR_INVALID_ADDRESS Invalid data flash address was input + * @retval FSP_ERR_INVALID_SIZE 'num_bytes' was either too large or not aligned for the CF/DF boundary size. + * @retval FSP_ERR_IN_USE Flash is busy with an on-going operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_BLANK_CHECK_FAILED An error occurred during blank checking. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_BlankCheck (flash_ctrl_t * const p_api_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * p_blank_check_result) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + + /* Check parameters. If failure return error */ + err = r_flash_lp_write_read_bc_parameter_checking(p_ctrl, address, num_bytes, false); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); +#endif + + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + /* Initiate the Blank Check operation */ + /* Configure the current operation and wait count based on the number of bytes and if it's a data flash or code flash operation. */ + /* Is this a request to Blank check Code Flash? */ +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + if (address < BSP_ROM_SIZE_BYTES) + { + /* This is a request to Blank check Code Flash */ + err = r_flash_lp_cf_blankcheck(p_ctrl, address, num_bytes, p_blank_check_result); + } + else +#endif + { +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + + /* This is a request to Blank check Data Flash */ + err = r_flash_lp_df_blankcheck(p_ctrl, address, num_bytes, p_blank_check_result); +#endif + } + + /* If failure reset the flash. */ + if (FSP_SUCCESS != err) + { + /* This will clear error flags and exit the P/E mode*/ + r_flash_lp_reset(p_ctrl); + } + + return err; +} + +/*******************************************************************************************************************//** + * Query the FLASH for its status. Implements @ref flash_api_t::statusGet. + * + * Example: + * @snippet r_flash_lp_example.c R_FLASH_LP_StatusGet + * + * @retval FSP_SUCCESS Flash is ready and available to accept commands. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_StatusGet (flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status) +{ + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + /* If null control block return error. */ + FSP_ASSERT(NULL != p_ctrl); + + /* If null status pointer return error. */ + FSP_ASSERT(NULL != p_status); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Return flash status */ + if ((FLASH_LP_PRV_FENTRYR & FLASH_LP_FENTRYR_PE_MODE_BITS) == 0x0000U) + { + *p_status = FLASH_STATUS_IDLE; + } + else + { + *p_status = FLASH_STATUS_BUSY; + } + + return err; +} + +/*******************************************************************************************************************//** + * Configure an access window for the Code Flash memory. Implements @ref flash_api_t::accessWindowSet. + * + * An access window defines a contiguous area in Code Flash for which programming/erase is enabled. This area is on + * block boundaries. The block containing start_addr is the first block. The block containing end_addr is the last + * block. The access window then becomes first block (inclusive) --> last block (exclusive). Anything outside this range + * of Code Flash is then write protected. As an example, if you wanted to place an accesswindow on Code Flash Blocks 0 + * and 1, such that only those two blocks were writable, you would need to specify (address in block 0, address in block + * 2) as the respective start and end address. + * @note If the start address and end address are set to the same value, then the access window is effectively + * removed. This accomplishes the same functionality as R_FLASH_LP_AccessWindowClear(). + * + * The invalid address and programming boundaries supported and enforced by this function are dependent on the MCU in + * use as well as the part package size. Please see the User manual and/or requirements document for additional + * information. + * + * @param p_api_ctrl The p api control + * @param[in] start_addr The start address + * @param[in] end_addr The end address + * + * @retval FSP_SUCCESS Access window successfully configured. + * @retval FSP_ERR_INVALID_ADDRESS Invalid settings for start_addr and/or end_addr. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_AccessWindowSet (flash_ctrl_t * const p_api_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Note that the end_addr indicates the address up to, but not including the block that contains that address. */ + /* Therefore to allow the very last Block to be included in the access window we must allow for FLASH_CF_BLOCK_END+1 */ + /* If the start or end addresses are invalid return error. */ + FSP_ERROR_RETURN((start_addr <= end_addr) && (end_addr <= BSP_ROM_SIZE_BYTES), FSP_ERR_INVALID_ADDRESS); + #endif + + /* Set the access window. */ + err = r_flash_lp_access_window_set(p_ctrl, start_addr, end_addr); +#else + + /* Remove warnings generated when Code Flash code is DISABLED. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(start_addr); + FSP_PARAMETER_NOT_USED(end_addr); + + /* If not code flash return error. */ + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Remove any access window that is configured in the Code Flash. Implements @ref flash_api_t::accessWindowClear. On + * successful return from this call all Code Flash is writable. + * + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_AccessWindowClear (flash_ctrl_t * const p_api_ctrl) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* If successful clear the access window. When the start address and end address are set to the same value, + * then the access window is effectively removed. */ + err = r_flash_lp_access_window_set(p_ctrl, 0, 0); +#else + + /* Return error if Code Flash not enabled. */ + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Write the ID code provided to the id code registers. Implements @ref flash_api_t::idCodeSet. + * + * @retval FSP_SUCCESS ID code successfully configured. + * @retval FSP_ERR_IN_USE FLASH peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for completion of extra command. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_IdCodeSet (flash_ctrl_t * const p_api_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify the id bytes are not in code flash. They will not be available in P/E mode. */ + FSP_ASSERT(((uint32_t) p_id_code) > BSP_ROM_SIZE_BYTES); + #endif + + /* Set the id code. */ + err = r_flash_lp_set_id_code(p_ctrl, p_id_code, mode); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_id_code); + FSP_PARAMETER_NOT_USED(mode); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + /* Return status. */ + return err; +} + +/*******************************************************************************************************************//** + * Reset the FLASH peripheral. Implements @ref flash_api_t::reset. + * + * No attempt is made to check if the flash is busy before executing the reset since the assumption is that a reset + * will terminate any existing operation. + * @retval FSP_SUCCESS Flash circuit successfully reset. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Reset (flash_ctrl_t * const p_api_ctrl) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* If null control block return error. */ + FSP_ASSERT(NULL != p_ctrl); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); +#endif + + /* Reset the flash. */ + r_flash_lp_reset(p_ctrl); + + return err; +} + +/*******************************************************************************************************************//** + * Select which block is used as the startup area block. Implements @ref flash_api_t::startupAreaSelect. + * + * Selects which block - Default (Block 0) or Alternate (Block 1) is used as the startup area block. The provided + * parameters determine which block will become the active startup block and whether that action will be immediate (but + * temporary), or permanent subsequent to the next reset. Doing a temporary switch might appear to have limited + * usefulness. If there is an access window in place such that Block 0 is write protected, then one could do a temporary + * switch, update the block and switch them back without having to touch the access window. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE Flash is busy with an on-going operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_UNSUPPORTED Code Flash Programming is not enabled. Cannot set FLASH_STARTUP_AREA_BTFLG + * when the temporary flag is false. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_StartUpAreaSelect (flash_ctrl_t * const p_api_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* If the swap type is BTFLG and the operation is temporary there's nothing to do. */ + FSP_ASSERT(!((swap_type == FLASH_STARTUP_AREA_BTFLG) && (is_temporary == false))); + + err = r_flash_lp_set_startup_area_boot(p_ctrl, swap_type, is_temporary); +#else + + /* Eliminate warning if code flash programming is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(swap_type); + FSP_PARAMETER_NOT_USED(is_temporary); + + err = FSP_ERR_UNSUPPORTED; // For consistency with _LP API we return error if Code Flash not enabled +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Swap the Code Flash bank to update new program. Implement @ref flash_api_t::bankSwap. + * + * Swap the flash bank located at address 0x00000000 and address 0x00040000. After a bank swap is done the MCU will + * need to be reset for the changes to take place unless instant swap is enabled. + * + * To use this API, Code Flash Programming in the FSP Configuration Tool under Stack Properties must be enabled. + * + * @note This function only available on MCUs which support bank swap feature. + * + * @note When active bank is bank 1, startup program protection function is invalid. + * + * @param[in] p_api_ctrl The api control instance. + * + * @retval FSP_SUCCESS Banks were swapped. + * @retval FSP_ERR_UNSUPPORTED Module does not support Bank Swap. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_IN_USE Extra area is being used by other command. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_BankSwap (flash_ctrl_t * const p_api_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK == 1) + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + #if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + err = r_flash_lp_bank_swap(p_ctrl); +#else + + /* Eliminate unused warning. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Indicate to the already open Flash API that the FCLK has changed. Implements flash_api_t::updateFlashClockFreq. + * + * This could be the case if the application has changed the system clock, and therefore the FCLK. Failure to call this + * function subsequent to changing the FCLK could result in damage to the flash macro. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE Flash is busy with an on-going operation. + * @retval FSP_ERR_FCLK Invalid flash clock source frequency. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_UpdateFlashClockFreq (flash_ctrl_t * const p_api_ctrl) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Check FCLK, calculate timeout values. */ + err = r_flash_lp_setup(p_ctrl); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + /* Set the FlashIF peripheral clock frequency. */ + err = r_flash_lp_set_fisr(p_ctrl); + + return err; +} + +/*******************************************************************************************************************//** + * Returns the information about the flash regions. Implements @ref flash_api_t::infoGet. + * + * @retval FSP_SUCCESS Successful retrieved the request information. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_info. + * @retval FSP_ERR_NOT_OPEN The flash is not open. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_InfoGet (flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info) +{ +#if FLASH_LP_CFG_PARAM_CHECKING_ENABLE + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + + /* If null control block return error. */ + FSP_ASSERT(NULL != p_ctrl); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); + + FSP_ASSERT(NULL != p_info); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Copy the region data to the info structure. */ + p_info->code_flash = g_flash_code_region; + p_info->data_flash = g_flash_data_region; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Release any resources that were allocated by the Flash API. Implements @ref flash_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_cfg. + * @retval FSP_ERR_NOT_OPEN Flash API has not yet been opened. + * @retval FSP_ERR_IN_USE The flash is currently in P/E mode. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_Close (flash_ctrl_t * const p_api_ctrl) +{ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) p_api_ctrl; + +#if FLASH_LP_CFG_PARAM_CHECKING_ENABLE + + /* Verify the control block is not null and is opened. */ + fsp_err_t err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Mark the control block as closed. */ + p_ctrl->opened = 0; + +#if FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1 + + /* Disable the flash interrupt. */ + if (FSP_INVALID_VECTOR != p_ctrl->p_cfg->irq) + { + /* Disable interrupt in ICU*/ + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::callbackSet. + * + * @retval FSP_ERR_UNSUPPORTED Function has not been implemented. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_CallbackSet (flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void * const p_context, + flash_callback_args_t * const p_callback_memory) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_callback_memory); + FSP_PARAMETER_NOT_USED(p_context); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::antiRollbackCounterIncrement. + * + * @retval FSP_ERR_UNSUPPORTED Function has not been implemented. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_AntiRollbackCounterIncrement (flash_ctrl_t * const p_api_ctrl, flash_arc_t counter) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(counter); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::antiRollbackCounterRefresh. + * + * @retval FSP_ERR_UNSUPPORTED Function has not been implemented. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_AntiRollbackCounterRefresh (flash_ctrl_t * const p_api_ctrl, flash_arc_t counter) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(counter); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::antiRollbackCounterRead. + * + * @retval FSP_ERR_UNSUPPORTED Function has not been implemented. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_AntiRollbackCounterRead (flash_ctrl_t * const p_api_ctrl, + flash_arc_t counter, + uint32_t * const p_count) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(counter); + FSP_PARAMETER_NOT_USED(p_count); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::userLockableAreaWrite. + * + * @retval FSP_ERR_UNSUPPORTED Function has not been implemented. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_UserLockableAreaWrite (flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(src_address); + FSP_PARAMETER_NOT_USED(flash_address); + FSP_PARAMETER_NOT_USED(num_bytes); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup FLASH_LP) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This function verifies that FCLK falls within the allowable range and calculates the timeout values based on the + * current FCLK frequency. + * @param p_ctrl The p control + * @retval FSP_SUCCESS Success + * @retval FSP_ERR_FCLK FCLK must be 1 MHz, 2 MHz, 3 MHz or a minimum of 4 MHz. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_setup (flash_lp_instance_ctrl_t * p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Get the frequency of the clock driving the flash. */ + p_ctrl->flash_clock_frequency = R_FSP_SystemClockHzGet(BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC); + + /* FCLK must be 1 MHz, 2 MHz, 3 MHz or a minimum of 4 MHz for Flash operations. If not return error. */ + if (p_ctrl->flash_clock_frequency < FLASH_HP_MINIMUM_SUPPORTED_FCLK_FREQ) + { + FSP_ERROR_RETURN((p_ctrl->flash_clock_frequency == (1 * FLASH_LP_HZ_IN_MHZ)) || + (p_ctrl->flash_clock_frequency == (2 * FLASH_LP_HZ_IN_MHZ)) || + (p_ctrl->flash_clock_frequency == (3 * FLASH_LP_HZ_IN_MHZ)), + FSP_ERR_FCLK); + } + + /* Get the frequency of the system clock. */ + p_ctrl->system_clock_frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK); + + /* Initialize the flash timeout calculations and transfer global parameters to code and data flash layers. */ + r_flash_lp_init(p_ctrl); + + /* Enable the DataFlash if not already enabled */ + if (1U != R_FACI_LP->DFLCTL) + { + R_FACI_LP->DFLCTL = 1U; + + /* Wait for (tDSTOP) before reading from data flash. */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TDSTOP, p_ctrl->system_clock_frequency); + } + + return err; +} + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the parameter checking required by Write, Read and BlankCheck functions. + * + * @param p_ctrl Pointer to the control block + * @param[in] flash_address The flash address + * @param[in] num_bytes The number bytes + * @param[in] check_write Check parameters for writing. + * + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_NOT_OPEN The Flash API is not Open. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was not a multiple of the programming size or exceeded + * the maximum range. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + * @retval FSP_ERR_IN_USE The flash is currently in P/E mode. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_write_read_bc_parameter_checking (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t flash_address, + uint32_t const num_bytes, + bool check_write) +{ + /* Verify the control block is not null and is opened. */ + fsp_err_t err = r_flash_lp_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If invalid address or number of bytes return error. */ + #if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 0) + FSP_PARAMETER_NOT_USED(check_write); + #else + if (flash_address < BSP_ROM_SIZE_BYTES) + { + /* If the start address is in code flash verify the end address is in code flash. */ + FSP_ERROR_RETURN(flash_address + num_bytes <= BSP_ROM_SIZE_BYTES, FSP_ERR_INVALID_SIZE); + + if (check_write) + { + FSP_ERROR_RETURN(!(flash_address & (BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE - 1U)), FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(!(num_bytes & (BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE - 1U)), FSP_ERR_INVALID_SIZE); + } + } + else + #endif + { + #if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + FSP_ERROR_RETURN((flash_address >= (FLASH_LP_DF_START_ADDRESS)) && + (flash_address < (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN((flash_address + num_bytes <= (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERR_INVALID_SIZE); + #else + + return FSP_ERR_INVALID_ADDRESS; + #endif + } + + /* If invalid number of bytes return error. */ + FSP_ERROR_RETURN((0 != num_bytes), FSP_ERR_INVALID_SIZE); + + return FSP_SUCCESS; +} + +#endif + +#if (FLASH_LP_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the parameter checking required by the R_FLASH_LP_Write() function. + * @param p_ctrl Pointer to the control block + * + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_NOT_OPEN The flash module is not open. + * @retval FSP_ERR_IN_USE The flash is currently in P/E mode. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_common_parameter_checking (flash_lp_instance_ctrl_t * const p_ctrl) +{ + /* If null control block return error. */ + FSP_ASSERT(NULL != p_ctrl); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((FLASH_HP_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); + + /* If the API is not ready return error. */ + FSP_ERROR_RETURN((FLASH_LP_PRV_FENTRYR & FLASH_LP_FENTRYR_PE_MODE_BITS) == 0x0000U, FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * This function will calculate the timeout values for various operations. + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +void r_flash_lp_init (flash_lp_instance_ctrl_t * p_ctrl) +{ + /* Round up the frequency to a whole number. */ + p_ctrl->flash_clock_frequency = (p_ctrl->flash_clock_frequency + (FLASH_LP_HZ_IN_MHZ - 1)) / + FLASH_LP_HZ_IN_MHZ; + + /* If the frequency is over 32MHz round up to an even number. */ +#if BSP_FEATURE_FLASH_LP_VERSION == 4 + if ((p_ctrl->flash_clock_frequency > FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ) && + (1 == p_ctrl->flash_clock_frequency % 2)) + { + p_ctrl->flash_clock_frequency++; + } +#endif + + p_ctrl->system_clock_frequency = (p_ctrl->system_clock_frequency + (FLASH_LP_HZ_IN_MHZ - 1)) / + FLASH_LP_HZ_IN_MHZ; + + /* According to HW Manual the Max Programming Time for 4 bytes(RA2L1) or 8 bytes(RA2A1/RA4M1)(ROM) + * is 1411us. This is with a FCLK of 1MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_cf = + (uint32_t) (FLASH_LP_MAX_WRITE_CF_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Programming Time for 1 byte + * (Data Flash) is 886us. This is with a FCLK of 4MHz. The calculation + * below calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_df = + (uint32_t) (FLASH_LP_MAX_WRITE_DF_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Blank Check time for 2 bytes (S12*) or 8 bytes (RA2A1/RA4M1) + * (Code Flash) is 87.7 usec. This is with a FCLK of 1MHz. The calculation + * below calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_blank_check = + (uint32_t) (FLASH_LP_MAX_BLANK_CHECK_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for a 1KB block (S12*) or 2KB bytes (RA2A1/RA4M1) is + * around 289ms. This is with a FCLK of 1MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_erase_cf_block = + (uint32_t) (FLASH_LP_MAX_ERASE_CF_BLOCK_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for a 1KB Data Flash block is + * around 299ms. This is with a FCLK of 4MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_erase_df_block = + (uint32_t) (FLASH_LP_MAX_ERASE_DF_BLOCK_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; + + /* According to HW Manual the Max Erasure Time for writing to the extra area is + * around 585ms. This is with a FCLK of 1MHz. The calculation below + * calculates the number of ICLK ticks needed for the timeout delay. + */ + p_ctrl->timeout_write_extra_area = + (uint32_t) (FLASH_LP_MAX_WRITE_EXTRA_AREA_TIME_US * p_ctrl->system_clock_frequency) / + FLASH_LP_CYCLES_MINIMUM_PER_TIMEOUT_LOOP; +} + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function erases a specified number of Code or Data Flash blocks + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] block_address The starting address of the first block to erase. + * @param[in] num_blocks The number of blocks to erase. + * + * @retval FSP_SUCCESS Successfully erased (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_ERASE_FAILED Erase failed. Flash could be locked or address could be under access window + * control. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_df_erase (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t block_address, + uint32_t num_blocks) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Enter data flash P/E mode. */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + + /* Save the current operation parameters. */ + p_ctrl->source_start_address = block_address + FLASH_LP_DATAFLASH_ADDR_OFFSET; + p_ctrl->operations_remaining = num_blocks; + + /* Start the code flash erase operation. */ + r_flash_lp_process_command(p_ctrl->source_start_address, + num_blocks * BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE, + FLASH_LP_FCR_ERASE); + + /* If configured for Blocking mode then don't return until the entire operation is complete */ + #if (FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1) + if (!p_ctrl->p_cfg->data_flash_bgo) + #endif + { + /* Waits for the erase commands to be completed and verifies the result of the command execution. */ + err = r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_erase_df_block * num_blocks, + FLASH_LP_FSTATR2_ERASE_ERROR_BITS, + FSP_ERR_ERASE_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Disable P/E mode for data flash. */ + r_flash_lp_pe_mode_exit(p_ctrl); + } + + #if (FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1) + else + { + p_ctrl->current_operation = FLASH_OPERATION_BGO_ERASE; + p_ctrl->flash_status_mask = FLASH_LP_FSTATR2_ERASE_ERROR_BITS; + p_ctrl->timeout = p_ctrl->timeout_erase_df_block; + } + #endif + + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function erases a specified number of Code Flash blocks + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] block_address The starting address of the first block to erase. + * @param[in] num_blocks The number of blocks to erase. + * @param[in] block_size The Flash block size. + * + * @retval FSP_SUCCESS Successfully erased (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_ERASE_FAILED Status is indicating a Erase error. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_cf_erase (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t block_address, + uint32_t num_blocks, + uint32_t block_size) +{ + fsp_err_t err = FSP_SUCCESS; + + r_flash_lp_cf_enter_pe_mode(p_ctrl, (bool) FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE); + + /* Start the code flash erase operation. */ + r_flash_lp_process_command(block_address, num_blocks * block_size, FLASH_LP_FCR_ERASE); + + #if (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + p_ctrl->current_operation = FLASH_OPERATION_BGO_ERASE; + p_ctrl->flash_status_mask = FLASH_LP_FSTATR2_ERASE_ERROR_BITS; + p_ctrl->timeout = p_ctrl->timeout_erase_cf_block; + + return err; + #else + + /* Wait for the operation to complete. */ + err = r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_erase_cf_block * num_blocks, + FLASH_LP_FSTATR2_ERASE_ERROR_BITS, + FSP_ERR_ERASE_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return r_flash_lp_pe_mode_exit(p_ctrl); + #endif +} + +#endif + +/*******************************************************************************************************************//** + * This function writes a specified number of bytes to Code or Data Flash. + * + * @param[in] p_ctrl Pointer to the Flash control block + * + * @retval FSP_SUCCESS Data successfully written (non-BGO) mode or operation successfully started (BGO). + * @retval FSP_ERR_IN_USE Command still executing. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. This may be + * returned if the requested Flash area is not blank. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the Flash sequencer to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_write (flash_lp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) || (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + bool bgo = false; +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + if (p_ctrl->dest_end_address < BSP_ROM_SIZE_BYTES) + { + #if (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + p_ctrl->current_operation = FLASH_OPERATION_CF_BGO_WRITE; + bgo = true; + #endif + + p_ctrl->timeout = p_ctrl->timeout_write_cf; + p_ctrl->operations_remaining = p_ctrl->operations_remaining / BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE; + r_flash_lp_cf_enter_pe_mode(p_ctrl, (bool) FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE); + } + else +#endif + { +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + if (p_ctrl->p_cfg->data_flash_bgo) + { + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_WRITE; + bgo = true; + } + + p_ctrl->timeout = p_ctrl->timeout_write_df; + + /* Enter data flash P/E mode. */ + r_flash_lp_df_enter_pe_mode(p_ctrl); +#endif + } + + /* Select user area. */ + R_FACI_LP->FASR = 0U; + + while (p_ctrl->operations_remaining && (FSP_SUCCESS == err)) + { +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + if (p_ctrl->dest_end_address < BSP_ROM_SIZE_BYTES) + { + /* Initiate the code flash write operation. */ + r_flash_lp_cf_write_operation(p_ctrl); + } + else +#endif + { +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + + /* Initiate the data flash write operation. */ + r_flash_lp_df_write_operation(p_ctrl); +#endif + } + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) || (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + if (bgo) + { + p_ctrl->flash_status_mask = FLASH_LP_FSTATR2_WRITE_ERROR_BITS; + + return err; + } +#endif + + err = + r_flash_lp_wait_for_ready(p_ctrl, p_ctrl->timeout, FLASH_LP_FSTATR2_WRITE_ERROR_BITS, FSP_ERR_WRITE_FAILED); + } + + /* If successful exit P/E mode. */ + if (FSP_SUCCESS == err) + { + r_flash_lp_pe_mode_exit(p_ctrl); + } + + return err; +} + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Execute a single Write operation on the Low Power Data Flash data. + * See "Flowchart for consecutive programming of the code flash" in the Flash Memory section of the relevant + * hardware manual + * + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +static void r_flash_lp_df_write_operation (flash_lp_instance_ctrl_t * const p_ctrl) +{ + uint32_t dest_addr_idx = p_ctrl->dest_end_address + FLASH_LP_DATAFLASH_ADDR_OFFSET; + + /* Conversion to the P/E address from the read address */ + uint8_t * data8_ptr = (uint8_t *) p_ctrl->source_start_address; + + /* Increment the start/end addresses of the next write before the current write is executed. */ + p_ctrl->source_start_address += BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE; + p_ctrl->dest_end_address += BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE; + p_ctrl->operations_remaining--; + + /* Write flash address setting */ + R_FACI_LP->FSARH = (uint16_t) ((dest_addr_idx >> 16)); + R_FACI_LP->FSARL = (uint16_t) (dest_addr_idx); + + /* Write data address setting */ + R_FACI_LP->FWBL0 = *data8_ptr; // For data flash there are only 8 bits used of the 16 in the reg + + /* Execute Write command */ + R_FACI_LP->FCR = FLASH_LP_FCR_WRITE; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Execute a single Write operation on the Low Power Code Flash data. + * See "Flowchart for programming of the code flash" in the Flash Memory section of the relevant hardware manual + * + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +static void r_flash_lp_cf_write_operation (flash_lp_instance_ctrl_t * const p_ctrl) +{ + uint16_t data[BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE / 2]; + + /* Write flash address setting */ + R_FACI_LP->FSARH = (uint16_t) ((p_ctrl->dest_end_address >> 16)); + R_FACI_LP->FSARL = (uint16_t) (p_ctrl->dest_end_address); + + /* Copy the data and write them to the flash write buffers. CM23 parts to not support unaligned access so this + * must be done using byte access. */ + r_flash_lp_memcpy((uint8_t *) data, (uint8_t *) p_ctrl->source_start_address, BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE); + + /* If there is more data to write then write the next data. */ + p_ctrl->source_start_address += BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE; + p_ctrl->dest_end_address += BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE; + p_ctrl->operations_remaining--; + + R_FACI_LP->FWBL0 = data[0]; + R_FACI_LP->FWBH0 = data[1]; + #if BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE == 8 + R_FACI_LP->FWBL1 = data[2]; + R_FACI_LP->FWBH1 = data[3]; + #endif + + /* Execute Write command */ + R_FACI_LP->FCR = FLASH_LP_FCR_WRITE; +} + +#endif + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function checks if the specified Data Flash address range is blank. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] start_address The starting address of the Flash area to blank check. + * @param[in] num_bytes Specifies the number of bytes that need to be checked. + * @param[out] result Pointer that will be populated by the API with the results of the blank check + * operation in non-BGO (blocking) mode. In this case the blank check operation + * completes here and the result is returned. In Data Flash BGO mode the blank + * check operation is only started here and the result obtained later when the + * supplied callback routine is called. + * + * @retval FSP_SUCCESS Blankcheck operation completed with result in result, or blankcheck started + * and in-progess (BGO mode). + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_BLANK_CHECK_FAILED An error occurred during blank checking. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_df_blankcheck (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t start_address, + uint32_t num_bytes, + flash_result_t * result) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Enter data flash P/E mode. */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + + /* Execute blank check command. */ + r_flash_lp_process_command(start_address + FLASH_LP_DATAFLASH_ADDR_OFFSET, num_bytes, FLASH_LP_FCR_BLANKCHECK); + + #if (FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1) + + /* If in DF BGO mode, exit here; remaining processing if any will be done in ISR */ + if (p_ctrl->p_cfg->data_flash_bgo) + { + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_BLANKCHECK; + *result = FLASH_RESULT_BGO_ACTIVE; + p_ctrl->timeout = p_ctrl->timeout_blank_check; + + return err; + } + #endif + + /* p_ctrl->timeout_blank_check specifies the wait time for a 4 code flash byte blank check. This is the same as + * the wait time for a 1 byte Data Flash blankcheck.*/ + err = + r_flash_lp_wait_for_ready(p_ctrl, + p_ctrl->timeout_blank_check * num_bytes, + FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS, + FSP_ERR_BLANK_CHECK_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check the result of the blank check. */ + if (0U != R_FACI_LP->FSTATR00_b.BCERR0) // Tested Flash Area is not blank + { + *result = FLASH_RESULT_NOT_BLANK; + } + else + { + *result = FLASH_RESULT_BLANK; + } + + /* Return the data flash to P/E mode. */ + r_flash_lp_pe_mode_exit(p_ctrl); + + /* Return status. Blank status is in result. */ + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function checks if the specified Data Flash address range is blank. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] start_address The starting address of the Flash area to blank check. + * @param[in] num_bytes Specifies the number of bytes that need to be checked. + * @param[out] result Pointer that will be populated by the API with the results of the blank check + * operation in non-BGO (blocking) mode. In this case the blank check operation + * completes here and the result is returned. In Data Flash BGO mode the blank + * check operation is only started here and the result obtained later when the + * supplied callback routine is called. + * + * @retval FSP_SUCCESS Blankcheck operation completed with result in result, or blankcheck started + * and in-progess (BGO mode). + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + * @retval FSP_ERR_BLANK_CHECK_FAILED An error occurred during blank checking. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_cf_blankcheck (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t start_address, + uint32_t num_bytes, + flash_result_t * result) +{ + fsp_err_t err = FSP_SUCCESS; + + r_flash_lp_cf_enter_pe_mode(p_ctrl, (bool) FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE); + + /* Give the blank check command to the FACI. */ + r_flash_lp_process_command(start_address, num_bytes, FLASH_LP_FCR_BLANKCHECK); + + #if (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + *result = FLASH_RESULT_BGO_ACTIVE; + + p_ctrl->flash_status_mask = FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS; + p_ctrl->timeout = p_ctrl->timeout_blank_check; + + p_ctrl->current_operation = FLASH_OPERATION_DF_BGO_BLANKCHECK; + + return err; + #else + + /* p_ctrl->timeout_blank_check specifies the wait time for a 4 code flash byte blank check. + * num_bytes is divided by 4 and then multiplied to calculate the wait time for the entire operation */ + uint32_t wait_count = p_ctrl->timeout_blank_check * ((num_bytes + 3) / 4); + + /* Wait for the blank check to complete and return result in control block. */ + err = + r_flash_lp_wait_for_ready(p_ctrl, wait_count, FLASH_LP_FSTATR2_ILLEGAL_ERROR_BITS, FSP_ERR_BLANK_CHECK_FAILED); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + if (0U != R_FACI_LP->FSTATR00_b.BCERR0) // Tested Flash Area is not blank + { + /* If the result is already NOT Blank there is no reason to continue with any subsequent checks, simply return */ + *result = FLASH_RESULT_NOT_BLANK; + } + else + { + *result = FLASH_RESULT_BLANK; + } + + /* Return the flash to P/E mode. */ + err = r_flash_lp_pe_mode_exit(p_ctrl); + + /* Return status. Blank status is in result. */ + return err; + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Initiates a flash command. + * See Figures "Flowchart for the code flash block erase procedure", "Flowchart for the data flash block erase procedure", + * "Flowchart for the data flash chip erase procedure", "Flowchart for the code flash blank check procedure" + * in the Flash Memory section of the relevant hardware manual. + * + * @param[in] start_addr Start address of the operation. + * @param[in] num_bytes Number of bytes beginning at start_addr. + * @param[in] command The flash command + **********************************************************************************************************************/ +static void r_flash_lp_process_command (const uint32_t start_addr, uint32_t num_bytes, uint32_t command) +{ + uint32_t end_addr_idx = start_addr + (num_bytes - 1U); + + /* Select User Area */ + R_FACI_LP->FASR = 0U; + + /* BlankCheck start address setting */ + R_FACI_LP->FSARH = (uint16_t) ((start_addr >> 16)); + R_FACI_LP->FSARL = (uint16_t) (start_addr); + + /* BlankCheck end address setting */ + R_FACI_LP->FEARH = (uint16_t) ((end_addr_idx >> 16)); + R_FACI_LP->FEARL = (uint16_t) (end_addr_idx); + + /* Execute BlankCheck command */ + R_FACI_LP->FCR = (uint8_t) command; +} + +/*******************************************************************************************************************//** + * This function switches the peripheral from P/E mode for Code Flash or Data Flash to Read mode. + * See Figures "Procedure for changing from code flash P/E mode to read mode", "Procedure for changing from data + * flash P/E mode to read mode" in the Flash Memory section of the relevant hardware manual. + * + * + * @param[in] p_ctrl Pointer to the Flash control block + * @retval FSP_SUCCESS Successfully entered P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for confirmation of transition to read mode + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_pe_mode_exit (flash_lp_instance_ctrl_t * const p_ctrl) +{ +#if FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE + uint32_t flash_pe_mode = FLASH_LP_PRV_FENTRYR; +#endif + + /* Timeout counter. */ + volatile uint32_t wait_cnt = FLASH_LP_FRDY_CMD_TIMEOUT; + +#if BSP_FEATURE_FLASH_LP_VERSION == 3 && FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE + if (flash_pe_mode == FLASH_LP_FENTRYR_CF_PE_MODE) + { + r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_2); + + /* Wait for 2us over (tDIS) */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency); + + r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_1); + } +#endif + + r_flash_lp_write_fpmcr(FLASH_LP_READ_MODE); + + /* Wait for flash mode transition complete. The value of tMS will depend on flash version */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TMS_HIGH, p_ctrl->system_clock_frequency); + +#if FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE && (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + if ((flash_pe_mode == FLASH_LP_FENTRYR_CF_PE_MODE) && (0U != R_FACI_LP->FBKPGCR)) + { + R_FACI_LP->FBKPGCR = FLASH_LP_BANK_PROGRAMMING_EXIT; + } +#endif + + /* Clear the P/E mode register */ + FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_READ_MODE; + + /* Loop until the Flash P/E mode entry register is cleared or a timeout occurs. If timeout occurs return error. */ + FLASH_LP_REGISTER_WAIT_TIMEOUT(0, FLASH_LP_PRV_FENTRYR, wait_cnt, FSP_ERR_TIMEOUT); + +#if FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE + if (flash_pe_mode == FLASH_LP_FENTRYR_CF_PE_MODE) + { + #if BSP_FEATURE_FLASH_CACHE + R_BSP_FlashCacheEnable(); + #endif + #if BSP_FEATURE_FLASH_PREFETCH_BUFFER + R_FACI_LP->PFBER = 1; + #endif + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function resets the Flash sequencer. + * See figure "Flowchart for programming of the code flash" in the Flash Memory section of the relevant hardware manual. + * + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +static void r_flash_lp_reset (flash_lp_instance_ctrl_t * const p_ctrl) +{ + /* Cancel any in progress BGO operation. */ + p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; + + /* If not currently in PE mode then enter P/E mode. */ + if (FLASH_LP_PRV_FENTRYR == 0x0000UL) + { + /* Enter P/E mode so that we can execute some FACI commands. Either Code or Data Flash P/E mode would work + * but Code Flash P/E mode requires FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE ==1, which may not be true */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + } + + /* Reset the flash. */ + R_FACI_LP->FRESETR = 1U; + R_FACI_LP->FRESETR = 0U; + + /* Transition to Read mode */ + r_flash_lp_pe_mode_exit(p_ctrl); +} + +/*******************************************************************************************************************//** + * FLASH ready interrupt routine. + * + * This function implements the FLASH ready isr. The function clears the interrupt request source on entry populates the + * callback structure with the relevant event, and providing a callback routine has been provided, calls the callback + * function with the event. + **********************************************************************************************************************/ +void fcu_frdyi_isr (void) +{ +#if (FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1) || (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + FSP_CONTEXT_SAVE + flash_callback_args_t cb_data; + bool operation_completed = true; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + #if BSP_FEATURE_ICU_HAS_IELSR + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + #endif + + /* Recover ISR context saved in open. */ + flash_lp_instance_ctrl_t * p_ctrl = (flash_lp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* If an error occurs reset and return error. */ + if ((FSP_ERR_TIMEOUT == r_flash_lp_command_finish(p_ctrl->timeout)) || + (0U != (R_FACI_LP->FSTATR2 & p_ctrl->flash_status_mask))) + { + r_flash_lp_reset(p_ctrl); + + cb_data.event = FLASH_EVENT_ERR_FAILURE; + } + else + { + /* Continue the current operation. If unknown operation set callback event to failure. */ + if (FLASH_OPERATION_BGO_ERASE == p_ctrl->current_operation) + { + cb_data.event = FLASH_EVENT_ERASE_COMPLETE; + } + + #if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) + else if (FLASH_OPERATION_DF_BGO_WRITE == p_ctrl->current_operation) + { + if (p_ctrl->operations_remaining) + { + operation_completed = false; + r_flash_lp_df_write_operation(p_ctrl); + } + else + { + cb_data.event = FLASH_EVENT_WRITE_COMPLETE; + } + } + #endif + #if (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + else if (FLASH_OPERATION_CF_BGO_WRITE == p_ctrl->current_operation) + { + if (p_ctrl->operations_remaining) + { + operation_completed = false; + r_flash_lp_cf_write_operation(p_ctrl); + } + else + { + cb_data.event = FLASH_EVENT_WRITE_COMPLETE; + } + } + #endif + else + { + /* Check the result and return it */ + if (R_FACI_LP->FSTATR00_b.BCERR0 == 1U) + { + cb_data.event = FLASH_EVENT_NOT_BLANK; + } + else + { + cb_data.event = FLASH_EVENT_BLANK; + } + } + } + + /* If the operation completed exit read mode, release the flash, and call the callback if available. */ + if (operation_completed == true) + { + /* finished current operation. Exit P/E mode*/ + r_flash_lp_pe_mode_exit(p_ctrl); + + if (NULL != p_ctrl->p_cfg->p_callback) + { + cb_data.p_context = p_ctrl->p_cfg->p_context; + cb_data.data = 0U; + + /* Set data to identify callback to user, then call user callback. */ + p_ctrl->p_cfg->p_callback(&cb_data); + } + } + FSP_CONTEXT_RESTORE +#endif +} + +/*******************************************************************************************************************//** + * Delay for the given number of micro seconds at the given frequency + * + * @note This is used instead of R_BSP_SoftwareDelay because that may be linked in code flash. + * + * @param[in] us Number of microseconds to delay + * @param[in] mhz The frequency of the system clock + **********************************************************************************************************************/ +static void r_flash_lp_delay_us (uint32_t us, uint32_t mhz) +{ + uint32_t loop_cnt; + + // @12 MHz, one loop is 332 ns. A delay of 5 us would require 15 loops. 15 * 332 = 4980 ns or ~ 5us + + /* Calculation of a loop count */ + loop_cnt = ((us * mhz) / FLASH_LP_DELAY_LOOP_CYCLES); + + if (loop_cnt > 0U) + { + __asm volatile ("delay_loop:\n" +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || (defined(__llvm__) && !defined(__CLANG_TIDY__)) + " subs %[loops_remaining], #1 \n" ///< 1 cycle +#elif defined(__GNUC__) + " sub %[loops_remaining], %[loops_remaining], #1 \n" ///< 1 cycle +#endif + "cmp %[loops_remaining], #0\n" // 1 cycle + +/* CM0 and CM23 have different instruction sets */ +#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC) + " bne delay_loop \n" ///< 2 cycles +#else + " bne.n delay_loop \n" ///< 2 cycles +#endif + : // No outputs + :[loops_remaining] "r" (loop_cnt) + : // No clobbers + ); + } +} + +/*******************************************************************************************************************//** + * Transition to Data Flash P/E mode. + * @param[in] p_ctrl Pointer to the Flash control block + **********************************************************************************************************************/ +void r_flash_lp_df_enter_pe_mode (flash_lp_instance_ctrl_t * const p_ctrl) +{ + FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_DATAFLASH_PE_MODE; + + r_flash_lp_delay_us(FLASH_LP_WAIT_TDSTOP, p_ctrl->system_clock_frequency); + + /* See figure "Procedure for changing from the read mode to the data flash P/E mode" in the Flash Memory section + * of the relevant hardware manual. */ +#if BSP_FEATURE_FLASH_LP_VERSION == 3 + + /* If the device is not in high speed mode enable LVPE mode as per the flash documentation. */ + if (R_SYSTEM->OPCCR_b.OPCM == 0U) + { + r_flash_lp_write_fpmcr(FLASH_LP_DATAFLASH_PE_MODE); + } + else + { + r_flash_lp_write_fpmcr((uint8_t) FLASH_LP_DATAFLASH_PE_MODE | (uint8_t) FLASH_LP_LVPE_MODE); + } + +#elif BSP_FEATURE_FLASH_LP_VERSION == 4 + r_flash_lp_write_fpmcr(FLASH_LP_DATAFLASH_PE_MODE); + + r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency); +#endif + +#if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1) + + /* If BGO mode is enabled and interrupts are being used then enable interrupts. */ + if (p_ctrl->p_cfg->data_flash_bgo == true) + { + /* We are supporting Flash Rdy interrupts for Data Flash operations. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->irq); + } +#endif +} + +/*******************************************************************************************************************//** + * Sets the FPMCR register, used to place the Flash sequencer in Code Flash P/E mode. + * @param[in] value - 8 bit value to be written to the FPMCR register. + **********************************************************************************************************************/ +static void r_flash_lp_write_fpmcr (uint8_t value) +{ + /* Procedure for writing to FPMCR is documented in "FPR : Protection Unlock Register" description in the Flash Memory section of the relevant hardware manual. */ + R_FACI_LP->FPR = FLASH_LP_FPR_UNLOCK; + + R_FACI_LP->FPMCR = value; + R_FACI_LP->FPMCR = (uint8_t) ~value; + R_FACI_LP->FPMCR = value; + + if (value == R_FACI_LP->FPMCR) + { + __NOP(); + } +} + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Configure an access window for the Code Flash memory using the provided start and end address. An access window + * defines a contiguous area in Code Flash for which programming/erase is enabled. This area is on block boundaries. The + * block containing start_addr is the first block. The block containing end_addr is the last block. The access window + * then becomes first block - last block inclusive. Anything outside this range of Code Flash is then write protected. + * This command DOES modify the configuration via The Configuration Set command to update the FAWS and FAWE. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. + * + * @retval FSP_SUCCESS Access window successfully configured. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_access_window_set (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t const start_addr, + uint32_t const end_addr) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Enter Code Flash P/E mode */ + r_flash_lp_cf_enter_pe_mode(p_ctrl, false); + + /* Select The Extra Area */ + R_FACI_LP->FASR = 1U; + + /* Set the access window. */ + r_flash_lp_extra_operation(start_addr, end_addr, FLASH_COMMAND_ACCESSWINDOW); + + /* Wait for the operation to complete or error. */ + err = r_flash_lp_extra_check(p_ctrl); + + /* Select User Area */ + R_FACI_LP->FASR = 0U; + + /* Return to read mode. */ + fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl); + + /* If the previous commands were successful return the result of P/E exit. */ + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + /* Return status. */ + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Set the id code + * See figure "Simple flowchart for the procedure for Startup Area Information and FSPR Program/Access + * Window Information Program/OCDID information Program" in the Flash Memory section of the relevant hardware manual. + * + * @param p_ctrl Pointer to the instance control block + * @param p_id_code Pointer to the code to be written + * @param[in] mode The id code mode + * + * @retval FSP_SUCCESS The id code have been written. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for completion of extra command. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_set_id_code (flash_lp_instance_ctrl_t * const p_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t fexcr_command = FLASH_LP_FEXCR_OCDID1; + + uint16_t mode_mask = (uint16_t) mode; + + /* Update Flash state and enter Code Flash P/E mode */ + r_flash_lp_cf_enter_pe_mode(p_ctrl, false); + + /* For each ID byte register */ + for (uint32_t i = 0U; i < 16U; i += 4U) + { + /* Select Extra Area */ + R_FACI_LP->FASR = 1U; + + /* Write the ID Bytes. If mode is unlocked write all 0xFF. Write the mode mask to the MSB. */ + if (FLASH_ID_CODE_MODE_UNLOCKED == mode) + { + R_FACI_LP->FWBL0 = UINT16_MAX; + R_FACI_LP->FWBH0 = UINT16_MAX; + } + else + { + /* The id code array may be unaligned. Do not attempt to optimize this code to prevent unaligned access. */ + R_FACI_LP->FWBL0 = (uint16_t) (p_id_code[i] | (p_id_code[i + 1] << 8)); + if (12U == i) + { + R_FACI_LP->FWBH0 = (uint16_t) (p_id_code[i + 2] | (p_id_code[i + 3] << 8)) | mode_mask; + } + else + { + R_FACI_LP->FWBH0 = (uint16_t) (p_id_code[i + 2] | (p_id_code[i + 3] << 8)); + } + } + + /* Execute OCDID command */ + R_FACI_LP->FEXCR = fexcr_command; + + /* Increment the command to write to the next OCDID bytes */ + fexcr_command++; + + /* Wait until the operation is complete or an error. */ + err = r_flash_lp_extra_check(p_ctrl); + + /* Select User Area */ + R_FACI_LP->FASR = 0U; + + /* If failure return error */ + if (FSP_SUCCESS != err) + { + break; + } + } + + /* Return to read mode. */ + fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl); + + /* If the previous commands were successful return the result of P/E exit. */ + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Modifies the start-up program swap flag (BTFLG) based on the supplied parameters. These changes will take effect on + * the next reset. This command DOES modify the configuration via The Configuration Set command to update the BTFLG. + * + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] swap_type Specifies the startup area swap being requested. + * @param[in] temporary Swap blocks temporarily. + * + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the FCU to become ready. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_set_startup_area_boot (flash_lp_instance_ctrl_t * const p_ctrl, + flash_startup_area_swap_t swap_type, + bool temporary) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Update Flash state and enter Code Flash P/E mode */ + r_flash_lp_cf_enter_pe_mode(p_ctrl, false); + + if (temporary) + { + /* Set the Flash initial setting startup area select bit as requested. */ + R_FACI_LP->FISR_b.SAS = swap_type; + } + else + { + /* Sets the BTFLG flag where 1 selects block 0 and 0 selects block 1. */ + #if BSP_FEATURE_FLASH_LP_VERSION == 3 + uint32_t startup_area_mask = ((uint32_t) (~swap_type & 0x1) << 8); // move selection to bit 8 + #elif BSP_FEATURE_FLASH_LP_VERSION == 4 + uint32_t startup_area_mask = ((uint32_t) (~swap_type & 0x1) << 15); // move selection to bit 15 + #endif + + /* Select Extra Area */ + R_FACI_LP->FASR = 1U; + + /* Call extra operation to set the startup area. */ + r_flash_lp_extra_operation(startup_area_mask, 0, FLASH_COMMAND_STARTUPAREA); + + /* Wait until the operation is complete or an error occurs. */ + err = r_flash_lp_extra_check(p_ctrl); + + /* Select User Area */ + R_FACI_LP->FASR = 0U; + } + + /* Return to read mode. */ + fsp_err_t temp_err = r_flash_lp_pe_mode_exit(p_ctrl); + + /* If the previous commands were successful return the result of P/E exit. */ + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + return err; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Command processing for the extra area. + * See figure "Simple flowchart for the procedure for Startup Area Information and FSPR Program/Access + * Window Information Program/OCDID information Program" in the Flash Memory section of the relevant hardware manual. + * + * @param[in] start_addr_startup_value Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. + * @param[in] command Select from R_FLASH_ACCESSWINDOW or R_FLASH_STARTUPAREA. + **********************************************************************************************************************/ +static void r_flash_lp_extra_operation (const uint32_t start_addr_startup_value, + const uint32_t end_addr, + r_flash_command_t command) +{ + /* Per the spec: */ + /* Setting data to the FWBL0 register, this command is allowed to select the start-up area from the */ + /* default area (blocks 0-3) to the alternative area (blocks 4-7) and set the security. */ + /* Bit 8 of the FWBL0 register is 0: the alternative area (blocks 4-7) are selected as the start-up area. */ + /* Bit 8 of the FWBL0 register is 1: the default area (blocks 0-3) are selected as the start-up area. */ + /* Bit 14 of the FWBL0 register MUST be 1! Setting this bit to zero will clear the FSPR register and lock the */ + /* FLASH!!! It is not be possible to unlock it. */ + #if BSP_FEATURE_FLASH_LP_VERSION == 3 + if (FLASH_COMMAND_ACCESSWINDOW == command) + { + /* Set the Access Window start and end addresses. */ + /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */ + /* Convert the addresses to their respective block numbers */ + R_FACI_LP->FWBL0 = (uint16_t) ((start_addr_startup_value >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT)); + R_FACI_LP->FWBH0 = (uint16_t) ((end_addr >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT)); + + /* Execute Access Window command */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_AW; + } + else + { + /* Startup Area Flag value setting */ + R_FACI_LP->FWBH0 = UINT16_MAX; + + /* FSPR must be set. Unused bits write value should be 1. */ + R_FACI_LP->FWBL0 = (start_addr_startup_value | FLASH_LP_FSCMR_FSPR_AND_UNUSED_BITS); + + /* Execute Startup Area Flag command */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_STARTUP; + } + + #elif BSP_FEATURE_FLASH_LP_VERSION == 4 + if (FLASH_COMMAND_ACCESSWINDOW == command) + { + uint32_t fawsmr = R_FACI_LP->FAWSMR & ~BSP_FEATURE_FLASH_LP_AWS_FAW_MASK; + uint32_t fawemr = R_FACI_LP->FAWEMR & ~BSP_FEATURE_FLASH_LP_AWS_FAW_MASK; + + /* Set the Access Window start and end addresses. */ + /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */ + /* Convert the addresses to their respective block numbers */ + R_FACI_LP->FWBL0 = ((start_addr_startup_value >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT) | fawsmr); + R_FACI_LP->FWBH0 = ((end_addr >> BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT) | fawemr); + + /* Execute Access Window command */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_MF4_AW_STARTUP; + } + else + { + uint32_t fawsmr = R_FACI_LP->FAWSMR; + uint32_t fawemr = R_FACI_LP->FAWEMR & ~FLASH_LP_MF4_FAWEMR_STARTUP_AREA_MASK; + + /* Set the Access Window start and end addresses. */ + /* FWBL0 reg sets the Start Block address. FWBH0 reg sets the end address. */ + /* Convert the addresses to their respective block numbers */ + + /* Set the access window start address to what was in FAWSMR. */ + R_FACI_LP->FWBL0 = fawsmr; + + /* Set the access window end address to what was in FAWEMR. Set BTFLG according to user input. */ + R_FACI_LP->FWBH0 = (start_addr_startup_value | fawemr); + + /* Execute Startup Area Flag command */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_MF4_AW_STARTUP; + } + #endif +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Wait for the current command to finish processing and clear the FCR register. If MF4 is used clear the processing + * bit before clearing the rest of FCR. + * See figure "Simple flowchart for the procedure for Startup Area Information and FSPR Program/Access + * Window Information Program/OCDID information Program" in the Flash Memory section of the relevant hardware manual. + * + * @param[in] timeout The timeout + * @retval FSP_SUCCESS The command completed successfully. + * @retval FSP_ERR_TIMEOUT The command timed out. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_extra_command_finish (uint32_t timeout) +{ + /* Timeout counter. */ + volatile uint32_t wait_cnt = timeout; + + /* If the software command of the FEXCR register is not terminated return in use. */ + FLASH_LP_REGISTER_WAIT_TIMEOUT(1, R_FACI_LP->FSTATR1_b.EXRDY, wait_cnt, FSP_ERR_TIMEOUT); + + #if BSP_FEATURE_FLASH_LP_VERSION == 4 + + /* Stop Processing */ + R_FACI_LP->FEXCR = R_FACI_LP->FEXCR & ((uint8_t) ~FLASH_LP_FEXCR_PROCESSING_MASK); + #endif + + /* Clear the Flash Extra Area Control Register. */ + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_CLEAR; + + wait_cnt = timeout; + + /* Wait until the command has completed or a timeout occurs. If timeout return error. */ + FLASH_LP_REGISTER_WAIT_TIMEOUT(0, R_FACI_LP->FSTATR1_b.EXRDY, wait_cnt, FSP_ERR_TIMEOUT); + + return FSP_SUCCESS; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Verifying the execution result for the extra area. + * @param[in] p_ctrl Pointer to the Flash control block + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for completion of extra command. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_extra_check (flash_lp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = r_flash_lp_extra_command_finish(p_ctrl->timeout_write_extra_area); + + /* If a timeout occurs reset the flash and return error. */ + if (FSP_ERR_TIMEOUT == err) + { + r_flash_lp_reset(p_ctrl); + + return err; + } + + /* If Extra Area Illegal Command Error Flag or Error during programming reset the flash and return error. */ + if (0 != (FLASH_LP_FSTATR2_WRITE_ERROR_BITS & R_FACI_LP->FSTATR2)) + { + r_flash_lp_reset(p_ctrl); + + return FSP_ERR_WRITE_FAILED; + } + + /* Return success. */ + return FSP_SUCCESS; +} + +#endif + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Transition to Code Flash P/E mode. + * @param[in] p_ctrl Pointer to the Flash control block + * @param[in] bank_programming Put the flash into bank programming mode + **********************************************************************************************************************/ +void r_flash_lp_cf_enter_pe_mode (flash_lp_instance_ctrl_t * const p_ctrl, bool bank_programming) +{ + /* While the Flash API is in use we will disable the Flash Cache. */ + #if BSP_FEATURE_FLASH_PREFETCH_BUFFER + R_FACI_LP->PFBER = 0; + #endif + #if BSP_FEATURE_FLASH_CACHE + R_BSP_FlashCacheDisable(); + #endif + + #if (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + if (bank_programming) + { + R_BSP_IrqEnable(p_ctrl->p_cfg->irq); + } + else + { + if (FSP_INVALID_VECTOR != p_ctrl->p_cfg->irq) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); // We are not supporting Flash Rdy interrupts for Code Flash operations + } + } + + #else + FSP_PARAMETER_NOT_USED(bank_programming); + #if (FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) && (FLASH_LP_CFG_DATA_FLASH_BGO_SUPPORT_ENABLE == 1) + if (p_ctrl->p_cfg->data_flash_bgo) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + } + #endif + #endif + + FLASH_LP_PRV_FENTRYR = FLASH_LP_FENTRYR_CODEFLASH_PE_MODE; + + /* See figure "Procedure for changing from read mode to code flash P/E mode" + * in the Flash Memory section of the relevant hardware manual. */ + #if BSP_FEATURE_FLASH_LP_VERSION == 3 + r_flash_lp_write_fpmcr(FLASH_LP_DISCHARGE_1); + + /* Wait for 2us over (tDIS) */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency); + + uint32_t fpmcr_command1; + uint32_t fpmcr_command2; + uint32_t fpmcr_mode_setup_time; + + /* If the device is not in high speed mode enable LVPE mode as per the flash documentation. */ + if (R_SYSTEM->OPCCR_b.OPCM == 0U) + { + fpmcr_command1 = FLASH_LP_DISCHARGE_2; + fpmcr_command2 = FLASH_LP_CODEFLASH_PE_MODE; + fpmcr_mode_setup_time = FLASH_LP_WAIT_TMS_HIGH; + } + else + { + fpmcr_command1 = FLASH_LP_DISCHARGE_2 | FLASH_LP_LVPE_MODE; + fpmcr_command2 = FLASH_LP_CODEFLASH_PE_MODE | FLASH_LP_LVPE_MODE; + fpmcr_mode_setup_time = FLASH_LP_WAIT_TMS_MID; + } + + r_flash_lp_write_fpmcr((uint8_t) fpmcr_command1); + r_flash_lp_write_fpmcr((uint8_t) fpmcr_command2); + + /* Wait for 5us or 3us depending on current operating mode. (tMS) */ + r_flash_lp_delay_us(fpmcr_mode_setup_time, p_ctrl->system_clock_frequency); + #elif BSP_FEATURE_FLASH_LP_VERSION == 4 + #if (FLASH_LP_CFG_CODE_FLASH_BANK_PROGRAMMING_ENABLE == 1) + if (bank_programming) + { + R_FACI_LP->FBKPGCR = FLASH_LP_BANK_PROGRAMMING_ENTER; + } + #endif + r_flash_lp_write_fpmcr(0x02); + + /* Wait for 2us over (tDIS) */ + r_flash_lp_delay_us(FLASH_LP_WAIT_TDIS, p_ctrl->system_clock_frequency); + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Wait for the current command to finish processing and clear the FCR register. If MF4 is used clear the processing + * bit before clearing the rest of FCR. + * See figure "Flowchart for programming of the code flash" in the Flash Memory section of the relevant hardware manual. + * + * @param[in] timeout The timeout + * @retval FSP_SUCCESS The command completed successfully. + * @retval FSP_ERR_TIMEOUT The command timed out. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_command_finish (uint32_t timeout) +{ + /* Worst case timeout */ + volatile uint32_t wait = timeout; + + /* Check the Flash Ready Flag bit*/ + FLASH_LP_REGISTER_WAIT_TIMEOUT(1, R_FACI_LP->FSTATR1_b.FRDY, wait, FSP_ERR_TIMEOUT); + +#if BSP_FEATURE_FLASH_LP_VERSION == 4 + + /* Stop Processing */ + R_FACI_LP->FCR = R_FACI_LP->FCR & ((uint8_t) ~FLASH_LP_FCR_PROCESSING_MASK); +#endif + + /* Clear FCR register */ + R_FACI_LP->FCR = FLASH_LP_FCR_CLEAR; + + /* Worst case timeout */ + wait = timeout; + + /* Wait for the Flash Ready Flag bit to indicate ready or a timeout to occur. If timeout return error. */ + FLASH_LP_REGISTER_WAIT_TIMEOUT(0, R_FACI_LP->FSTATR1_b.FRDY, wait, FSP_ERR_TIMEOUT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Wait for the current command to finish processing and check for error. + * + * @param p_ctrl Pointer to the control block + * @param[in] timeout The timeout + * @param[in] error_bits The error bits related to the current command + * @param[in] return_code The operation specific error code + * + * @retval FSP_SUCCESS Erase command successfully completed. + * @retval FSP_ERR_TIMEOUT Timed out waiting for erase command completion. + * @return return_code The operation specific error code. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_wait_for_ready (flash_lp_instance_ctrl_t * const p_ctrl, + uint32_t timeout, + uint32_t error_bits, + fsp_err_t return_code) +{ + fsp_err_t err = r_flash_lp_command_finish(timeout); + + /* If a timeout occurs reset the flash and return error. */ + if (FSP_ERR_TIMEOUT == err) + { + r_flash_lp_reset(p_ctrl); + + return err; + } + + /* If an error occurs reset and return error. */ + if (0U != (R_FACI_LP->FSTATR2 & error_bits)) + { + r_flash_lp_reset(p_ctrl); + + return return_code; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the flash interface peripheral clock frequency + * @param p_ctrl Pointer to the interface control block + * @retval FSP_SUCCESS Flash interface clock frequency successfully configured. + * @retval FSP_ERR_TIMEOUT Setting the flash interface clock frequency timed out. + **********************************************************************************************************************/ +fsp_err_t r_flash_lp_set_fisr (flash_lp_instance_ctrl_t * const p_ctrl) +{ + /* Enter data flash P/E mode to enable writing to FISR. */ + r_flash_lp_df_enter_pe_mode(p_ctrl); + +#if BSP_FEATURE_FLASH_LP_VERSION == 4 + + /* If the flash clock is larger than 32 increment FISR_b.PCKA by 1 for every 2MHZ. (See "Flash + * Internal Setting Register" description in the Flash Memory section of the relevant hardware manual.) */ + if (p_ctrl->flash_clock_frequency >= FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ) + { + R_FACI_LP->FISR_b.PCKA = + (0x1F + ((p_ctrl->flash_clock_frequency - FLASH_LP_FISR_INCREASE_PCKA_EVERY_2MHZ) >> 1)) & + FLASH_LP_6BIT_MASK; + } + else +#endif + { + R_FACI_LP->FISR_b.PCKA = (p_ctrl->flash_clock_frequency - 1U) & FLASH_LP_5BIT_MASK; + } + + return r_flash_lp_pe_mode_exit(p_ctrl); +} + +#if (FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Local memcpy function to prevent from using memcpy linked in code flash + * + * @param dest The destination + * @param src The source + * @param[in] len The length + **********************************************************************************************************************/ +void r_flash_lp_memcpy (uint8_t * const dest, uint8_t * const src, uint32_t len) +{ + for (uint32_t i = 0; i < len; i++) + { + dest[i] = src[i]; + } +} + + #if (BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK == 1) + +/*******************************************************************************************************************//** + * This function swaps which flash bank will be used to boot from after swapped and activated. + * + * @param[in] p_ctrl Flash control block. + * + * @retval FSP_SUCCESS Banks were swapped. + * @retval FSP_ERR_IN_USE Extra area is being used by other command. + * @retval FSP_ERR_WRITE_FAILED Failed to write bank swap command into extra area. + * @retval FSP_ERR_TIMEOUT Timed out waiting for completion of extra command or timed out waiting for + * confirmation of transition to read mode. + **********************************************************************************************************************/ +static fsp_err_t r_flash_lp_bank_swap (flash_lp_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + uint8_t cur_bank; + + /* Refer to the "Example of startup bank selection flow" flowchart in the relevant hardware manual */ + cur_bank = R_FACI_LP->FCTLFR_b.BANKSWP; + + r_flash_lp_cf_enter_pe_mode(p_ctrl, false); + + /* Select The Extra Area. Needed when using FEXCR register. */ + R_FACI_LP->FASR = 1U; + + /* Change the BANKSWP[2:0] of extra area */ + R_FACI_LP->FWBL0_b.WDATA = ((uint8_t) ~cur_bank) & FLASH_LP_3BIT_MASK; + R_FACI_LP->FWBH0_b.WDATA = 0x0000U; + R_FACI_LP->FEXCR = FLASH_LP_FEXCR_MF4_CONTROL; + + err = r_flash_lp_extra_check(p_ctrl); + + /* Select User Area. Need to change back to User Area before return error. */ + R_FACI_LP->FASR = 0U; + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = r_flash_lp_pe_mode_exit(p_ctrl); + + #if FLASH_LP_CFG_DUAL_BANK_INSTANT_SWAP + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* See figure "Example of startup bank selection flow (2/4) (change the startup bank without reset)" + * in the Flash Memory section of the relevant hardware manual. */ + + /* Enable writing to FCTLFR. */ + R_FACI_LP->FBKSWCR = FLASH_LP_BANK_SWAP_UPDATE_ENABLE; + + /* Read BANKSWP[2:0] from the extra area */ + (void) *(uint32_t *) FLASH_LP_EXTRA_AREA_FCTLF_ADDRESS; + + /* Update FCTLFR with the new bank value. */ + R_FACI_LP->FCTLFR = ((uint8_t) ~cur_bank) & FLASH_LP_3BIT_MASK; + + /* Disable writing to FCTLFR. */ + R_FACI_LP->FBKSWCR = FLASH_LP_BANK_SWAP_UPDATE_DISABLE; + #endif + + return err; +} + + #endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_glcdc/r_glcdc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_glcdc/r_glcdc.c new file mode 100644 index 0000000000..23cdea93aa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_glcdc/r_glcdc.c @@ -0,0 +1,2108 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include + +#include "bsp_api.h" + +#include "r_glcdc.h" +#include "r_glcdc_cfg.h" + +#if defined(GLCDC_CFG_USING_DSI) + #include "r_mipi_dsi_api.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The macro to use for 64-byte alignment checking, calculation */ +#define GLCDC_PRV_ADDRESS_ALIGNMENT_64B (64U) + +/* This enables the GLCDC to locate the foreground/background layer image, at the physical start of the left side of + * the display, if the offset of layer start position is a negative value, compared to the active video area. + * Shifting the base address of the layer image can be used in this operation, but it must be aligned to 64 byte + * boundary, so that the layer position adjustment can be made. + */ +#define GLCDC_PRV_OFFSET_MARGIN_MINUS_64PIX (64U) + +#define GLCDC_PRV_OUT_CLKPHASE_ALL_RISING (0x00000000) +#define GLCDC_PRV_OUT_CLKPHASE_ALL_FALLING (0x00000178) + +/* Color look up table entry size */ +#define GLCDC_PRV_CLUT_ENTRY_SIZE (256U) + +/* Panel timing, Maximum threshold */ +#define GLCDC_PRV_BG_PLANE_H_CYC_MAX (2047U) ///< BG_PERI.FH +#define GLCDC_PRV_BG_PLANE_V_CYC_MAX (2047U) ///< BG_PERI.FV +#define GLCDC_PRV_BG_PLANE_H_CYC_ACTIVE_SIZE_MAX (2039U) ///< BG_HSIZE.HW (Max=2039) +#define GLCDC_PRV_BG_PLANE_V_CYC_ACTIVE_SIZE_MAX (2043U) ///< BG_VSIZE.VW (Max=2043) +#define GLCDC_PRV_BG_PLANE_H_CYC_ACTIVE_POS_MAX (2029U) ///< BG_HSIZE.HP (Max=2029, note that this value is 1cycle larger than GRn_AB3.GRCHS) +#define GLCDC_PRV_BG_PLANE_V_CYC_ACTIVE_POS_MAX (2030U) ///< BG_VSIZE.VP (Max=2030, note that this value is 1cycle larger than GRn_AB3.GRCVS) +#define GLCDC_PRV_GR_PLANE_TOTAL_TRANSFER_TIMES_MAX (65536U) ///< GRn_FLM5.DATANUM (Max=65536) +#define GLCDC_PRV_GR_PLANE_V_CYC_ACTIVE_SIZE_MAX (2043U) ///< GRn_AB2.GRCVW (Max=2043) ; Image Area, GRn_AB4.ARCVW (Max=2043); Rectangular Area +#define GLCDC_PRV_GR_PLANE_H_CYC_ACTIVE_POS_MAX (2028U) ///< GRn_AB3.GRCHS (Max=2028) ; Image Area, GRn_AB5.ARCHS (Max=2028); Rectangular Area +#define GLCDC_PRV_GR_PLANE_V_CYC_ACTIVE_POS_MAX (2029U) ///< GRn_AB2.GRCVS (Max=2029) ; Image Area, GRn_AB4.ARCVS (Max=2029); Rectangular Area +#define GLCDC_PRV_TCON_SIGNAL_ASSERT_WIDTH_MAX (2046U) + +/* Panel timing, Minimum threshold */ +#define GLCDC_PRV_BG_PLANE_H_CYC_MIN ((uint16_t) 23) ///< BG_PERI.FH +#define GLCDC_PRV_BG_PLANE_V_CYC_MIN ((uint16_t) 19) ///< BG_PERI.FV +#define GLCDC_PRV_BG_PLANE_HSYNC_POS_MIN ((uint16_t) 1) ///< BG_HSYNC.HP (Min=1) +#define GLCDC_PRV_BG_PLANE_VSYNC_POS_MIN ((uint16_t) 1) ///< BG_HSYNC.VP (Min=1) +#define GLCDC_PRV_BG_PLANE_H_CYC_ACTIVE_SIZE_MIN ((uint16_t) 16) ///< BG_HSIZE.HW (Min=16) +#define GLCDC_PRV_BG_PLANE_V_CYC_ACTIVE_SIZE_MIN ((uint16_t) 16) ///< BG_VSIZE.VW (Min=16) +#define GLCDC_PRV_BG_PLANE_H_CYC_ACTIVE_POS_MIN ((uint16_t) 6) ///< BG_HSIZE.HP (Min= 6) +#define GLCDC_PRV_BG_PLANE_V_CYC_ACTIVE_POS_MIN ((uint16_t) 3) ///< BG_VSIZE.VP (Min= 3) + +/* This driver sets same value to GRn_AB2.GRCVW and GRn_AB4.ARCVW, so the value of this macro + * is defined as the number of GRn_AB2.GRCVW(larger value). + */ +#define GLCDC_PRV_GR_PLANE_H_CYC_ACTIVE_POS_MIN (5U) ///< GRn_AB3.GRCHS (Min= 5) ; Image Area, GRn_AB5.ARCHS (Min= 5); Rectangular Area +#define GLCDC_PRV_GR_PLANE_V_CYC_ACTIVE_POS_MIN (2U) ///< GRn_AB2.GRCVS (Min= 2) ; Image Area, GRn_AB4.ARCVS (Min= 2); Rectangular Area +#define GLCDC_PRV_TCON_SIGNAL_ASSERT_WIDTH_MIN (0U) + +/* Color correction setting threshold */ +#define GLCDC_PRV_BRIGHTNESS_DEFAULT (512U) ///< OUT_BRIGHT1.BRTG, OUT_BRIGHT2.BRTR and .BRTB (Mid=512) +#define GLCDC_PRV_BRIGHTNESS_MIN (0U) ///< OUT_BRIGHT1.BRTG, OUT_BRIGHT2.BRTR and .BRTB (Min=0) +#define GLCDC_PRV_BRIGHTNESS_MAX (1023U) ///< OUT_BRIGHT1.BRTG, OUT_BRIGHT2.BRTR and .BRTB (Max=1023) +#define GLCDC_PRV_CONTRAST_DEFAULT (128U) ///< OUT_CONTRAST.CONTG and .CONTB and .CONTR (Mid=128) +#define GLCDC_PRV_CONTRAST_MIN (0U) ///< OUT_CONTRAST.CONTG and .CONTB and .CONTR (Min=0) +#define GLCDC_PRV_CONTRAST_MAX (255U) ///< OUT_CONTRAST.CONTG and .CONTB and .CONTR (Max=255) +#define GLCDC_PRV_GAMMA_GAIN_MAX (2047U) ///< GAMx_LUTn.GAIN15 - GAIN0 (Max=2047) +#define GLCDC_PRV_GAMMA_THRESHOLD_MAX (1023U) ///< GAMx_AREAn.TH15 - TH0 (Max=1023) + +/* Registers for Background Frame Control Block */ +#define GLCDC_PRV_BG_PERI_FV_MASK (0x7FFU) +#define GLCDC_PRV_BG_PERI_FH_MASK (0x7FFU) +#define GLCDC_PRV_BG_SYNC_VP_MASK (0xFU) +#define GLCDC_PRV_BG_SYNC_HP_MASK (0xFU) +#define GLCDC_PRV_BG_VSIZE_VP_MASK (0x7FFU) +#define GLCDC_PRV_BG_VSIZE_VW_MASK (0x7FFU) +#define GLCDC_PRV_BG_HSIZE_HP_MASK (0x7FFU) +#define GLCDC_PRV_BG_HSIZE_HW_MASK (0x7FFU) + +/* Register bit definition for Graphics Frame Control Block */ +#define GLCDC_PRV_GR_FLM3_LNOFF_MASK (0xFFFFU) +#define GLCDC_PRV_GR_FLM3_FLNUM_MASK (0x3FFU) +#define GLCDC_PRV_GR_FLM4_FLOFF_MASK (0xFFFFFFU) +#define GLCDC_PRV_GR_FLM5_LNNUM_MASK (0x7FFU) +#define GLCDC_PRV_GR_FLM5_DATANUM_MASK (0xFFFFU) +#define GLCDC_PRV_GR_FLM6_FORMAT_MASK (0x7U) + +#define GLCDC_PRV_GR_AB1_DISPSEL_MASK (0x3U) +#define GLCDC_PRV_GR_AB1_ARCON_SET (1 << 12) +#define GLCDC_PRV_GR_AB2_GRCVS_MASK (0x7FFU) +#define GLCDC_PRV_GR_AB2_GRCVW_MASK (0x7FFU) +#define GLCDC_PRV_GR_AB3_GRCHS_MASK (0x7FFU) +#define GLCDC_PRV_GR_AB3_GRCHW_MASK (0x7FFU) +#define GLCDC_PRV_GR_AB4_ARCVS_MASK (0x7FFU) +#define GLCDC_PRV_GR_AB4_ARCVW_MASK (0x7FFU) +#define GLCDC_PRV_GR_AB5_ARCHS_MASK (0x7FFU) +#define GLCDC_PRV_GR_AB5_ARCHW_MASK (0x7FFU) +#define GLCDC_PRV_GR_AB6_ARCCOEF_MASK (0x1FFU) +#define GLCDC_PRV_GR_AB6_ARCRATE_MASK (0xFFU) +#define GLCDC_PRV_GR_AB7_ARCDEF_MASK (0xFFU) +#define GLCDC_PRV_GR_CLUTINT_LINE_MASK (0x7FFU) + +/* Register bit definition for Output Control Block */ +#define GLCDC_PRV_GAMX_LUTX_GAIN_MASK (0x7FFU) +#define GLCDC_PRV_GAMX_AREAX_MASK (0x3FFU) + +#define GLCDC_PRV_OUT_SET_FRQSEL_NO_DIVISION (0U) +#define GLCDC_PRV_OUT_SET_FRQSEL_QUARTER_DIVISION (2U) +#define GLCDC_PRV_OUT_SET_FORMAT_SHIFT (12U) +#define GLCDC_PRV_OUT_SET_ENDIANON_ENABLE (1 << 28) +#define GLCDC_PRV_OUT_SET_SWAPON_ENABLE (1 << 24) + +#define GLCDC_PRV_OUT_PDTHA_SEL_SHIFT (20U) +#define GLCDC_PRV_OUT_PDTHA_FORM_SHIFT (16U) +#define GLCDC_PRV_OUT_PDTHA_PA_SHIFT (12U) +#define GLCDC_PRV_OUT_PDTHA_PB_SHIFT (8U) +#define GLCDC_PRV_OUT_PDTHA_PC_SHIFT (4U) + +#define GLCDC_PRV_OUT_BRIGHT1_BRTG_MASK (0x3FFU) +#define GLCDC_PRV_OUT_BRIGHT2_BRTB_MASK (0x3FFU) +#define GLCDC_PRV_OUT_BRIGHT2_BRTR_MASK (0x3FFU) + +#define GLCDC_PRV_OUT_CONTRAST_CONTG_MASK (0xFFU) +#define GLCDC_PRV_OUT_CONTRAST_CONTB_MASK (0xFFU) +#define GLCDC_PRV_OUT_CONTRAST_CONTR_MASK (0xFFU) + +#define GLCDC_PRV_TCON_STHX1_HS_MASK (0x7FFU) +#define GLCDC_PRV_TCON_STHX1_HW_MASK (0x7FFU) +#define GLCDC_PRV_TCON_STVX1_VS_MASK (0x7FFU) +#define GLCDC_PRV_TCON_STVX1_VW_MASK (0x7FFU) +#define GLCDC_PRV_TCON_STXX2_INV_SET (1 << 4) + +#define GLCDC_PRV_SYSCNT_PANEL_CLK_PIXSEL_SERIALRGB (1 << 12) +#define GLCDC_PRV_SYSCNT_PANEL_CLK_CLKSEL_PLL (1 << 8) +#define GLCDC_PRV_SYSCNT_PANEL_CLK_CLKEN_ENABLE (1 << 6) +#define GLCDC_PRV_SYSCNT_PANEL_CLK_DCDR_MASK (0x3FU) + +#define GLCDC_PRV_SYSCNT_DTCTEN_INIT (6U) +#define GLCDC_PRV_SYSCNT_INTEN_INIT (7U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* RGB color order select */ +typedef enum e_glcdc_plane_blend +{ + GLCDC_PLANE_BLEND_TRANSPARENT = 1, ///< Current graphics layer is transparent and the lower layer is displayed + GLCDC_PLANE_BLEND_NON_TRANSPARENT = 2, ///< Current graphics layer is displayed + GLCDC_PLANE_BLEND_ON_LOWER_LAYER = 3 ///< Current graphics layer is blended with the lower layer +} glcdc_plane_blend_t; + +/* RGB color order select */ +typedef enum e_glcdc_fading_control_initial_alpha +{ + GLCDC_FADING_CONTROL_INITIAL_ALPHA_MIN = 0, ///< Initial alpha value setting for a graphics plane is zero + GLCDC_FADING_CONTROL_INITIAL_ALPHA_MAX = 0xff ///< Initial alpha value setting for a graphics plane is maximum +} glcdc_fading_control_initial_alpha_t; + +/* The structure for the layer parameter recalculation */ +typedef struct st_recalculated_param +{ + uint16_t hpix_size; + uint16_t vpix_size; + int16_t hpix_offset; /* Offset can be signed value */ + int16_t vpix_offset; + uint32_t hread_size; + uint32_t base_address; +} glcdc_recalculated_param_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_stop(glcdc_instance_ctrl_t * const p_ctrl); +static void r_glcdc_sync_signal_set(display_cfg_t const * const p_cfg); + +static void r_glcdc_background_screen_set(display_cfg_t const * const p_cfg); + +static void r_glcdc_graphics_layer_set(display_input_cfg_t const * const p_input, + display_layer_t const * const p_layer, + display_frame_layer_t const layer); + +static void r_glcdc_output_block_set(display_cfg_t const * const p_cfg); + +static void r_glcdc_hsync_set(glcdc_tcon_pin_t tcon, display_timing_t const * timing); + +static void r_glcdc_vsync_set(glcdc_tcon_pin_t tcon, display_timing_t const * const timing); + +static void r_glcdc_data_enable_set(glcdc_tcon_pin_t const tcon, + display_timing_t const * const vtiming, + display_timing_t const * const htiming, + display_signal_polarity_t const polarity); + +static void r_glcdc_clock_set(display_cfg_t const * const p_cfg); + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_glcdc_open_param_check(display_cfg_t const * const p_cfg); + + #if GLCDC_CFG_COLOR_CORRECTION_ENABLE + +static fsp_err_t r_glcdc_param_check_brightness(display_brightness_t const * const p_brightness); + + #endif + +#endif + +static inline uint16_t r_glcdc_get_bit_size(display_in_format_t const format); + +static void r_glcdc_interrupt_enable(glcdc_instance_ctrl_t * p_instance_ctrl); + +static void r_glcdc_pixel_size_recalculate(display_input_cfg_t const * const p_input, + display_layer_t const * const p_layer, + glcdc_recalculated_param_t * p_recalculated, + uint16_t bit_size); + +#if GLCDC_CFG_COLOR_CORRECTION_ENABLE + +static void r_glcdc_brightness_correction(glcdc_instance_ctrl_t const * const p_ctrl, + display_brightness_t const * const p_brightness); + +static void r_glcdc_contrast_correction(glcdc_instance_ctrl_t const * const p_ctrl, + display_contrast_t const * const p_contrast); + +static void r_glcdc_color_correction_order(display_cfg_t const * const p_cfg); + +static void r_glcdc_gamma_correction(display_cfg_t const * const p_cfg); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* GLCDC HAL module API function pointer list */ +const display_api_t g_display_on_glcdc = +{ + .open = R_GLCDC_Open, + .close = R_GLCDC_Close, + .start = R_GLCDC_Start, + .stop = R_GLCDC_Stop, + .layerChange = R_GLCDC_LayerChange, + .bufferChange = R_GLCDC_BufferChange, + .clut = R_GLCDC_ClutUpdate, + .clutEdit = R_GLCDC_ClutEdit, + .correction = R_GLCDC_ColorCorrection, + .colorKeySet = R_GLCDC_ColorKeySet, + .statusGet = R_GLCDC_StatusGet, +}; + +/* GLCDC control block */ +static glcdc_ctrl_t g_ctrl_blk = +{ + .back_porch = {0U, 0U}, + .hsize = 0U, + .vsize = 0U, + .p_context = NULL +}; + +void glcdc_line_detect_isr(void); +void glcdc_underflow_1_isr(void); +void glcdc_underflow_2_isr(void); + +/* Needed to track fade status */ +static uint32_t g_fade_pending[2] = {false, false}; +static volatile uint32_t g_frame_ctr = 0; + +/* Tracks when an edited CLUT has been latched in */ +static volatile bool g_clut_data_latched[2] = {true, true}; + +/* Look-up table for r_glcdc_tcon_set */ +static uint32_t volatile * g_tcon_lut[] = +{ + &(R_GLCDC->TCON.STVA2), &(R_GLCDC->TCON.STVB2), &(R_GLCDC->TCON.STHA2), &(R_GLCDC->TCON.STHB2), +}; + +/* Look-up table for converting display_in_format_t to glcdc_input_interface_format_t */ +static glcdc_input_interface_format_t g_format_lut[] = +{ + GLCDC_INPUT_INTERFACE_FORMAT_ARGB8888, + GLCDC_INPUT_INTERFACE_FORMAT_RGB888, + GLCDC_INPUT_INTERFACE_FORMAT_RGB565, + GLCDC_INPUT_INTERFACE_FORMAT_ARGB1555, + GLCDC_INPUT_INTERFACE_FORMAT_ARGB4444, + GLCDC_INPUT_INTERFACE_FORMAT_CLUT8, + GLCDC_INPUT_INTERFACE_FORMAT_CLUT4, + GLCDC_INPUT_INTERFACE_FORMAT_CLUT1 +}; + +/* Look-up table for r_glcdc_get_bit_size */ +static uint16_t g_pixsize_lut[] = {32, 32, 16, 16, 16, 8, 4, 1}; // NOLINT(readability-magic-numbers) + +/* Look-up tables for use in r_glcdc_output_block_set */ +static glcdc_output_interface_format_t g_outset_lut[] = +{ + GLCDC_OUTPUT_INTERFACE_FORMAT_RGB888, + GLCDC_OUTPUT_INTERFACE_FORMAT_RGB666, + GLCDC_OUTPUT_INTERFACE_FORMAT_RGB565, + GLCDC_OUTPUT_INTERFACE_FORMAT_SERIAL_RGB +}; +static glcdc_dithering_output_format_t g_pdtha_lut[] = +{ + GLCDC_DITHERING_OUTPUT_FORMAT_RGB888, + GLCDC_DITHERING_OUTPUT_FORMAT_RGB666, + GLCDC_DITHERING_OUTPUT_FORMAT_RGB565, + GLCDC_DITHERING_OUTPUT_FORMAT_RGB888 +}; + +/*******************************************************************************************************************//** + * @addtogroup GLCDC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Open GLCDC module. Implements @ref display_api_t::open. + * + * @retval FSP_SUCCESS Device was opened successfully. + * @retval FSP_ERR_ALREADY_OPEN Device was already open. + * @retval FSP_ERR_ASSERTION Pointer to the control block or the configuration structure is NULL. + * @retval FSP_ERR_CLOCK_GENERATION Dot clock cannot be generated from clock source. + * @retval FSP_ERR_INVALID_TIMING_SETTING Invalid panel timing parameter. + * @retval FSP_ERR_INVALID_LAYER_SETTING Invalid layer setting found. + * @retval FSP_ERR_INVALID_ALIGNMENT Input buffer alignment invalid. + * @retval FSP_ERR_INVALID_GAMMA_SETTING Invalid gamma correction setting found + * @retval FSP_ERR_INVALID_BRIGHTNESS_SETTING Invalid brightness correction setting found + * @note PCLKA must be supplied to Graphics LCD Controller (GLCDC) and GLCDC pins must be set in IOPORT before + * calling this API. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_Open (display_ctrl_t * const p_api_ctrl, display_cfg_t const * const p_cfg) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters */ + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(p_ctrl->state <= DISPLAY_STATE_CLOSED, FSP_ERR_ALREADY_OPEN); + err = r_glcdc_open_param_check(p_cfg); + if (FSP_SUCCESS != err) + { + return err; + } +#endif + + p_ctrl->state = DISPLAY_STATE_CLOSED; + + /* Supply the peripheral clock to the GLCDC module */ + R_BSP_MODULE_START(FSP_IP_GLCDC, 0); + + /* Release GLCDC from a SW reset status. */ + R_GLCDC->BG.EN_b.SWRST = 1U; + + /* Set the dot clock frequency */ + r_glcdc_clock_set(p_cfg); + + /* Set the panel signal timing */ + r_glcdc_sync_signal_set(p_cfg); + + /* Configure the background screen */ + r_glcdc_background_screen_set(p_cfg); + + /* Store back porch position to the control block (needed to define the layer blending position later) */ + g_ctrl_blk.back_porch.x = (int16_t) (p_cfg->output.htiming.back_porch); + g_ctrl_blk.back_porch.y = (int16_t) (p_cfg->output.vtiming.back_porch); + g_ctrl_blk.hsize = p_cfg->output.htiming.display_cyc; + g_ctrl_blk.vsize = p_cfg->output.vtiming.display_cyc; + + /* Configure the graphics plane layers */ + for (uint32_t layer = 0U; layer <= DISPLAY_FRAME_LAYER_2; layer++) + { + r_glcdc_graphics_layer_set(&(p_cfg->input[layer]), &(p_cfg->layer[layer]), (display_frame_layer_t) layer); + } + + /* Configure the output control block */ + r_glcdc_output_block_set(p_cfg); + +#if GLCDC_CFG_COLOR_CORRECTION_ENABLE + + /* Configure the color correction setting (brightness, brightness and gamma correction) */ + r_glcdc_brightness_correction(p_ctrl, &p_cfg->output.brightness); + r_glcdc_contrast_correction(p_ctrl, &p_cfg->output.contrast); + if (p_cfg->output.p_gamma_correction) + { + r_glcdc_gamma_correction(p_cfg); + } + + /* Set the color correction order (brightness/contrast or gamma first) */ + r_glcdc_color_correction_order(p_cfg); +#else + + /* Set default brightness and contrast */ + R_GLCDC->OUT.BRIGHT1 = GLCDC_PRV_BRIGHTNESS_DEFAULT & GLCDC_PRV_OUT_BRIGHT1_BRTG_MASK; + R_GLCDC->OUT.BRIGHT2 = ((GLCDC_PRV_BRIGHTNESS_DEFAULT & GLCDC_PRV_OUT_BRIGHT2_BRTB_MASK) << 16) + + (GLCDC_PRV_BRIGHTNESS_DEFAULT & GLCDC_PRV_OUT_BRIGHT2_BRTR_MASK); + R_GLCDC->OUT.CONTRAST = ((GLCDC_PRV_CONTRAST_DEFAULT & GLCDC_PRV_OUT_CONTRAST_CONTG_MASK) << 16) + + ((GLCDC_PRV_CONTRAST_DEFAULT & GLCDC_PRV_OUT_CONTRAST_CONTB_MASK) << 8) + + (GLCDC_PRV_CONTRAST_DEFAULT & GLCDC_PRV_OUT_CONTRAST_CONTR_MASK); +#endif + + p_ctrl->p_callback = p_cfg->p_callback; /// Save callback function + p_ctrl->p_context = p_cfg->p_context; /// Save user defined context + p_ctrl->p_cfg = p_cfg; /// Save user configuration + g_ctrl_blk.p_context = p_ctrl; /// Save the display interface context into GLCDC HAL control block + + /* Set the line number to trigger the line detect interrupt */ + R_GLCDC->GR[1].CLUTINT_b.LINE = (uint16_t) (p_cfg->output.vtiming.back_porch + + p_cfg->output.vtiming.display_cyc + + GLCDC_PRV_BG_PLANE_HSYNC_POS_MIN) & GLCDC_PRV_GR_CLUTINT_LINE_MASK; + +#if defined(GLCDC_CFG_USING_DSI) + + /* DSI must be opened after GLCDC configuration. See "Overall Control" in the GLCDC Operation section of the + * relevant hardware manual */ + glcdc_extended_cfg_t * p_extend = (glcdc_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + mipi_dsi_instance_t * dsi_instance = (mipi_dsi_instance_t *) p_extend->phy_layer; + err = dsi_instance->p_api->open(dsi_instance->p_ctrl, dsi_instance->p_cfg); +#endif + + if (FSP_SUCCESS == err) + { + /* Enable GLCDC interrupts */ + r_glcdc_interrupt_enable(p_api_ctrl); + p_ctrl->state = DISPLAY_STATE_OPENED; /// Change GLCDC driver state + } + else + { + R_BSP_MODULE_STOP(FSP_IP_GLCDC, 0); + } + + return err; +} + +/*******************************************************************************************************************//** + * Close GLCDC module. Implements @ref display_api_t::close. + * + * @retval FSP_SUCCESS Device was closed successfully. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. + * @retval FSP_ERR_NOT_OPEN The function call is performed when the driver state is not equal to + * DISPLAY_STATE_CLOSED. + * @retval FSP_ERR_INVALID_UPDATE_TIMING A function call is performed when the GLCDC is updating register values + * internally. + * @note This API can be called when the driver is not in DISPLAY_STATE_CLOSED state. It returns an error + * if the register update operation for the background screen generation block is being held. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_Close (display_ctrl_t * const p_api_ctrl) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(DISPLAY_STATE_CLOSED != p_ctrl->state, FSP_ERR_NOT_OPEN); +#endif + + /* Stop video if running */ + if (R_GLCDC->BG.EN_b.EN) + { + r_glcdc_stop(p_api_ctrl); + } + +#if defined(GLCDC_CFG_USING_DSI) + + /* DSI must be closed before GLCDC. See "Overall Control" in the GLCDC Operation section of the + * relevant hardware manual */ + glcdc_extended_cfg_t * p_extend = (glcdc_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + mipi_dsi_instance_t * dsi_instance = (mipi_dsi_instance_t *) p_extend->phy_layer; + err = dsi_instance->p_api->close(dsi_instance->p_ctrl); +#endif + + /* Return immediately if the background block register updating is performed. */ + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->BG.MON_b.VEN & 1U), FSP_ERR_INVALID_UPDATE_TIMING); + + /* Disable the GLCDC interrupts in the NVIC */ + if (p_ctrl->p_cfg->line_detect_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->line_detect_irq); + } + + if (p_ctrl->p_cfg->underflow_1_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->underflow_1_irq); + } + + if (p_ctrl->p_cfg->underflow_2_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->underflow_2_irq); + } + + /* Disable the GLCDC interrupts */ + R_GLCDC->SYSCNT.DTCTEN = 0U; + R_GLCDC->SYSCNT.INTEN = 0U; + + /* Disable background plane operation */ + R_GLCDC->BG.EN_b.EN = 0U; + + /* Reset the GLCDC hardware */ + R_GLCDC->BG.EN_b.SWRST = 0U; + + /* Halt the peripheral clock to the GLCDC module */ + R_BSP_MODULE_STOP(FSP_IP_GLCDC, 0); + + p_ctrl->state = DISPLAY_STATE_CLOSED; + + return err; +} + +/*******************************************************************************************************************//** + * Start GLCDC module. Implements @ref display_api_t::start. + * + * @retval FSP_SUCCESS Device was started successfully. + * @retval FSP_ERR_NOT_OPEN GLCDC module has not been opened. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. + * @note This API can be called when the driver is not in DISPLAY_STATE_OPENED status. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_Start (display_ctrl_t * const p_api_ctrl) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(DISPLAY_STATE_OPENED == p_ctrl->state, FSP_ERR_NOT_OPEN); +#endif + +#if defined(GLCDC_CFG_USING_DSI) + + /* DSI must be started before GLCDC. See "Overall Control" in the GLCDC Operation section of the + * relevant hardware manual */ + glcdc_extended_cfg_t * p_extend = (glcdc_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + mipi_dsi_instance_t * dsi_instance = (mipi_dsi_instance_t *) p_extend->phy_layer; + err = dsi_instance->p_api->start(dsi_instance->p_ctrl); +#endif + + /* Start to output the vertical and horizontal synchronization signals and screen data. */ + + /* enables background plane operation and internal register value reflection. */ + R_GLCDC->BG.EN_b.VEN = 1U; + R_GLCDC->BG.EN_b.EN = 1U; + + /* Enable Line detect function */ + R_GLCDC->SYSCNT.DTCTEN_b.VPOSDTC = 1U; + + p_ctrl->state = DISPLAY_STATE_DISPLAYING; + + return err; +} + +/*******************************************************************************************************************//** + * Stop GLCDC module. Implements @ref display_api_t::stop. + * + * @retval FSP_SUCCESS Device was stopped successfully + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL + * @retval FSP_ERR_INVALID_MODE Function call is performed when the driver state is not + * DISPLAY_STATE_DISPLAYING. + * @retval FSP_ERR_INVALID_UPDATE_TIMING The function call is performed while the GLCDC is updating register values + * internally. + * @note This API can be called when the driver is in the DISPLAY_STATE_DISPLAYING state. It returns an + * error if the register update operation for the background screen generation blocks, the graphics data I/F + * blocks, or the output control block is being held. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_Stop (display_ctrl_t * const p_api_ctrl) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN((DISPLAY_STATE_DISPLAYING == p_ctrl->state), FSP_ERR_INVALID_MODE); +#endif + + return r_glcdc_stop(p_ctrl); +} + +/*******************************************************************************************************************//** + * Change layer parameters of GLCDC module at runtime. Implements display_api_t::layerChange. + * + * @retval FSP_SUCCESS Changed layer parameters of GLCDC module successfully. + * @retval FSP_ERR_ASSERTION Pointer to the control block or the configuration structure is NULL. + * @retval FSP_ERR_INVALID_MODE A function call is performed when the driver state is not + * DISPLAY_STATE_DISPLAYING. + * @retval FSP_ERR_INVALID_UPDATE_TIMING A function call is performed while the GLCDC is updating register values + * internally. + * @note This API can be called when the driver is in DISPLAY_STATE_DISPLAYING state. It returns an error if + * the register update operation for the background screen generation blocks or the graphics data I/F block + * is being held. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_LayerChange (display_ctrl_t const * const p_api_ctrl, + display_runtime_cfg_t const * const p_cfg, + display_frame_layer_t layer) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + FSP_PARAMETER_NOT_USED(p_ctrl); + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + FSP_ERROR_RETURN((DISPLAY_STATE_DISPLAYING == p_ctrl->state), FSP_ERR_INVALID_MODE); +#endif + + /* Return immediately if the register updating is in progress */ + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->GR[layer].VEN_b.PVEN), FSP_ERR_INVALID_UPDATE_TIMING); + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->BG.EN_b.VEN), FSP_ERR_INVALID_UPDATE_TIMING); + + /* Configure the graphics plane layers */ + r_glcdc_graphics_layer_set(&p_cfg->input, &p_cfg->layer, layer); + + /* Reflect the graphics module register value to the GLCDC internal operations (at the timing of the next Vsync + * assertion) */ + R_GLCDC->GR[layer].VEN_b.PVEN = 1U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Change the framebuffer pointer for a layer. Implements @ref display_api_t::bufferChange. + * + * @retval FSP_SUCCESS Changed layer parameters of GLCDC module successfully. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. + * @retval FSP_ERR_INVALID_MODE A function call is performed when the driver state is not + * DISPLAY_STATE_DISPLAYING. + * @retval FSP_ERR_INVALID_ALIGNMENT The framebuffer pointer is not 64-byte aligned. + * @retval FSP_ERR_INVALID_UPDATE_TIMING A function call is performed while the GLCDC is updating register values + * internally. + * @note This API can be called when the driver is in DISPLAY_STATE_OPENED state or higher. It returns an error if + * the register update operation for the background screen generation blocks or the graphics data I/F block + * is being held. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_BufferChange (display_ctrl_t const * const p_api_ctrl, + uint8_t * const framebuffer, + display_frame_layer_t layer) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + FSP_PARAMETER_NOT_USED(p_ctrl); + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN((DISPLAY_STATE_DISPLAYING == p_ctrl->state), FSP_ERR_INVALID_MODE); + + /* Buffer address must be aligned to 64-byte boundary */ + FSP_ERROR_RETURN(0U == (((uint32_t) framebuffer) % GLCDC_PRV_ADDRESS_ALIGNMENT_64B), FSP_ERR_INVALID_ALIGNMENT); +#endif + + /* Return immediately if the register updating is in progress */ + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->GR[layer].VEN_b.PVEN), FSP_ERR_INVALID_UPDATE_TIMING); + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->BG.EN_b.VEN), FSP_ERR_INVALID_UPDATE_TIMING); + + uint32_t dispsel; + uint32_t flmrd; + + /* If the base address is NULL set the layer as transparent and disable read memory access */ + if (framebuffer == NULL) + { + dispsel = GLCDC_PLANE_BLEND_TRANSPARENT; + flmrd = 0U; + } + else + { + dispsel = GLCDC_PLANE_BLEND_ON_LOWER_LAYER; + flmrd = 1U; + } + + /* Enable or disable the layer */ + R_GLCDC->GR[layer].AB1_b.DISPSEL = dispsel & GLCDC_PRV_GR_AB1_DISPSEL_MASK; /* Set layer transparent */ + R_GLCDC->GR[layer].FLMRD = flmrd; + + /* Set the buffer address */ + R_GLCDC->GR[layer].FLM2 = (uint32_t) framebuffer; + + /* Reflect the shadow registers on the next Vsync */ + R_GLCDC->GR[layer].VEN_b.PVEN = 1U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Perform color correction through the GLCDC module. Implements display_api_t::correction. + * + * @retval FSP_SUCCESS Color correction by GLCDC module was performed successfully. + * @retval FSP_ERR_ASSERTION Pointer to the control block or the display correction structure is NULL. + * @retval FSP_ERR_INVALID_MODE Function call is performed when the driver state is not + * DISPLAY_STATE_DISPLAYING. + * @retval FSP_ERR_INVALID_UPDATE_TIMING A function call is performed while the GLCDC is updating registers + * internally. + * @retval FSP_ERR_UNSUPPORTED Feature not supported with the current configuration. + * + * @retval FSP_ERR_INVALID_BRIGHTNESS_SETTING Invalid brightness correction setting found + * @note This API can be called when the driver is in the DISPLAY_STATE_DISPLAYING state. It returns an error if + * the register update operation for the background screen generation blocks or the output control block is + * being held. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_ColorCorrection (display_ctrl_t const * const p_api_ctrl, + display_correction_t const * const p_correction) +{ +#if GLCDC_CFG_COLOR_CORRECTION_ENABLE + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + + #if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_correction); + FSP_ERROR_RETURN((DISPLAY_STATE_DISPLAYING == p_ctrl->state), FSP_ERR_INVALID_MODE); + + if (p_correction->brightness.enable) + { + /* Ensure brightness settings are in range */ + FSP_ERROR_RETURN((FSP_SUCCESS == r_glcdc_param_check_brightness(&(p_correction->brightness))), + FSP_ERR_INVALID_BRIGHTNESS_SETTING); + } + #endif + + /* Return immediately if the register updatings are performed */ + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->OUT.VLATCH_b.VEN), FSP_ERR_INVALID_UPDATE_TIMING); + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->BG.EN_b.VEN), FSP_ERR_INVALID_UPDATE_TIMING); + + /* Configure the brightness and contrast correction register setting. */ + r_glcdc_brightness_correction(p_ctrl, &p_correction->brightness); + r_glcdc_contrast_correction(p_ctrl, &p_correction->contrast); + + /* Update the Output block register setting. */ + R_GLCDC->OUT.VLATCH_b.VEN = 1U; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_correction); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Write an entire color look-up table (CLUT) in the GLCDC module. Implements display_api_t::clut. + * + * @retval FSP_SUCCESS CLUT written successfully. + * @retval FSP_ERR_ASSERTION Pointer to the control block or CLUT source data is NULL. + * @retval FSP_ERR_INVALID_UPDATE_TIMING R_GLCDC_ClutEdit was already used to edit the specified CLUT this frame. + * @retval FSP_ERR_INVALID_CLUT_ACCESS Illegal CLUT entry or size is specified. + * @note This API can be called any time. The written data will be used after the next vertical sync event. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_ClutUpdate (display_ctrl_t const * const p_api_ctrl, + display_clut_cfg_t const * const p_clut_cfg, + display_frame_layer_t layer) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + FSP_PARAMETER_NOT_USED(p_ctrl); + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_clut_cfg); + FSP_ERROR_RETURN(g_clut_data_latched[layer], FSP_ERR_INVALID_UPDATE_TIMING); + FSP_ERROR_RETURN((GLCDC_PRV_CLUT_ENTRY_SIZE > p_clut_cfg->start), FSP_ERR_INVALID_CLUT_ACCESS); + FSP_ERROR_RETURN((GLCDC_PRV_CLUT_ENTRY_SIZE >= p_clut_cfg->size), FSP_ERR_INVALID_CLUT_ACCESS); +#endif + + /* Get the index of the CLUT not in use */ + uint32_t target_plane = R_GLCDC->GR[layer].CLUTINT_b.SEL ? 0 : 1; + + /* Get the start address in the destination CLUT hardware array based on the currently selected table and layer */ + uint32_t volatile * clut_hw = R_GLCDC->GR1_CLUT0 + + ((target_plane + (uint32_t) (layer << 1)) * GLCDC_PRV_CLUT_ENTRY_SIZE) + + p_clut_cfg->start; + + /* Copy the new CLUT data from the source memory to the CLUT SRAM in the GLCDC module */ + memcpy((void *) clut_hw, p_clut_cfg->p_base, sizeof(uint32_t) * p_clut_cfg->size); + + /* Swap to the new CLUT table data on the next frame */ + R_GLCDC->GR[layer].CLUTINT_b.SEL = target_plane & 1; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Update an element of a color look-up table (CLUT) in the GLCDC module. Implements display_api_t::clutEdit. + * + * @retval FSP_SUCCESS CLUT element updated successfully. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. + * @note This API can be called any time. The written data will be used after the next vertical sync event. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_ClutEdit (display_ctrl_t const * const p_api_ctrl, + display_frame_layer_t layer, + uint8_t index, + uint32_t color) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + FSP_PARAMETER_NOT_USED(p_ctrl); + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); +#endif + + static uint32_t volatile * clut_hw[2] = {R_GLCDC->GR1_CLUT0, R_GLCDC->GR2_CLUT0}; + + /* If the previously written CLUT has been selected, switch to the unused one */ + if (g_clut_data_latched[layer]) + { + g_clut_data_latched[layer] = false; + + /* Get the index of the CLUT not in use */ + uint32_t target_plane = R_GLCDC->GR[layer].CLUTINT_b.SEL ? 0 : 1; + + /* Get the start address of the destination CLUT hardware array */ + uint32_t volatile * clut_hw_new = R_GLCDC->GR1_CLUT0 + + ((target_plane + (uint32_t) (layer << 1)) * GLCDC_PRV_CLUT_ENTRY_SIZE); + + /* Copy the old data to the new table then save the new table address */ + memcpy((void *) clut_hw_new, (void *) clut_hw[layer], GLCDC_PRV_CLUT_ENTRY_SIZE * 4U); + clut_hw[layer] = clut_hw_new; + + /* Swap to the new CLUT table data on the next frame */ + R_GLCDC->GR[layer].CLUTINT_b.SEL = target_plane & 1; + } + + /* Set the CLUT element */ + clut_hw[layer][index] = color; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configuring color key is not supported for GLCDC. + * + * @retval FSP_ERR_UNSUPPORTED + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_ColorKeySet (display_ctrl_t const * const p_api_ctrl, + display_colorkeying_layer_t key_cfg, + display_frame_layer_t layer) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(key_cfg); + FSP_PARAMETER_NOT_USED(layer); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Get status of GLCDC module. Implements display_api_t::statusGet. + * + * @retval FSP_SUCCESS Got status successfully. + * @retval FSP_ERR_ASSERTION Pointer to the control block or the status structure is NULL. + * @note The GLCDC hardware starts the fading processing at the first Vsync after the previous LayerChange() call is + * held. + * Due to this behavior of the hardware, this API may not return DISPLAY_FADE_STATUS_FADING_UNDERWAY as the fading + * status, if it is called before the first Vsync after LayerChange() is called. In this case, the API returns + * DISPLAY_FADE_STATUS_PENDING, instead of DISPLAY_FADE_STATUS_NOT_UNDERWAY. + **********************************************************************************************************************/ +fsp_err_t R_GLCDC_StatusGet (display_ctrl_t const * const p_api_ctrl, display_status_t * const p_status) +{ + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) p_api_ctrl; + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_status); +#endif + + /* Return the GLCDC HAL driver state */ + p_status->state = p_ctrl->state; + + /* Return the fading status for the layers */ + for (display_frame_layer_t layer = (display_frame_layer_t) 0; layer <= DISPLAY_FRAME_LAYER_2; layer++) + { + if ((bool) (R_GLCDC->GR[layer].VEN & 1U) || (g_fade_pending[layer] > g_frame_ctr)) + { + /* Fading status is uncertain (the reason is described above). */ + p_status->fade_status[layer] = DISPLAY_FADE_STATUS_PENDING; + } + else + { + if (R_GLCDC->GR[layer].MON & 1U) + { + p_status->fade_status[layer] = DISPLAY_FADE_STATUS_FADING_UNDERWAY; + } + else + { + p_status->fade_status[layer] = DISPLAY_FADE_STATUS_NOT_UNDERWAY; + } + } + } + + return FSP_SUCCESS; +} + +/* @} (end addtogroup GLCDC) */ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * The GLCDC stop subroutine for R_GLCDC_Stop API. + * @param[in] p_ctrl Pointer to the configuration structure for display interface + * @retval FSP_SUCCESS Stoped successfully. + * @retval FSP_ERR_INVALID_UPDATE_TIMING The function call is performed while the GLCDC is updating register values + * internally. + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_stop (glcdc_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + +#if defined(GLCDC_CFG_USING_DSI) + + /* DSI must be stopped before GLCDC. See "Overall Control" in the GLCDC Operation section of the + * relevant hardware manual */ + glcdc_extended_cfg_t * p_extend = (glcdc_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + mipi_dsi_instance_t * dsi_instance = (mipi_dsi_instance_t *) p_extend->phy_layer; + err = dsi_instance->p_api->stop(dsi_instance->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Return immediately if the register is being updated */ + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->GR[DISPLAY_FRAME_LAYER_1].VEN_b.PVEN), FSP_ERR_INVALID_UPDATE_TIMING); + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->GR[DISPLAY_FRAME_LAYER_2].VEN_b.PVEN), FSP_ERR_INVALID_UPDATE_TIMING); + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->OUT.VLATCH_b.VEN), FSP_ERR_INVALID_UPDATE_TIMING); + FSP_ERROR_RETURN(false == (bool) (R_GLCDC->BG.EN_b.VEN), FSP_ERR_INVALID_UPDATE_TIMING); + + /* Disable background plane operation */ + R_GLCDC->BG.EN_b.EN = 0U; + + p_ctrl->state = DISPLAY_STATE_OPENED; + + return err; +} + +#if (GLCDC_CFG_PARAM_CHECKING_ENABLE) + #if GLCDC_CFG_COLOR_CORRECTION_ENABLE + +/*******************************************************************************************************************//** + * The parameter checking subroutine for brightness correction. + * @param[in] p_brightness Pointer to a brightness setting struct + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_INVALID_BRIGHTNESS_SETTING Invalid brightness setting found + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_param_check_brightness (display_brightness_t const * const p_brightness) +{ + if ((p_brightness->r > GLCDC_PRV_BRIGHTNESS_MAX) || + (p_brightness->g > GLCDC_PRV_BRIGHTNESS_MAX) || + (p_brightness->b > GLCDC_PRV_BRIGHTNESS_MAX)) + { + return FSP_ERR_INVALID_BRIGHTNESS_SETTING; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The parameter checking subroutine for R_GLCDC_Open API. + * @param[in] p_gamma_correction Pointer to the gamma configuration struct + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_ASSERTION Gain or threshold table pointers are NULL + * @retval FSP_ERR_INVALID_GAMMA_SETTING Invalid gamma correction setting found + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_param_check_gamma_correction (gamma_correction_t const * const p_gamma_correction) +{ + uint16_t previous_threshold = 0; + + /* Verify gain/threshold tables are not NULL */ + FSP_ASSERT(p_gamma_correction->gain); + FSP_ASSERT(p_gamma_correction->threshold); + + for (int32_t i = 0; i < DISPLAY_GAMMA_CURVE_ELEMENT_NUM; i++) + { + /* Each of the gamma correction threshold values must be less than GLCDC_PRV_GAMMA_THRESHOLD_MAX */ + FSP_ERROR_RETURN((GLCDC_PRV_GAMMA_THRESHOLD_MAX >= p_gamma_correction->threshold[i]), + FSP_ERR_INVALID_GAMMA_SETTING); + + /* The Gamma correction threshold[N] must be less than threshold[N+1] */ + FSP_ERROR_RETURN(previous_threshold <= p_gamma_correction->threshold[i], FSP_ERR_INVALID_GAMMA_SETTING); + previous_threshold = p_gamma_correction->threshold[i]; + + /* Each of gamma correction gain values must be less than GLCDC_PRV_GAMMA_GAIN_MAX */ + FSP_ERROR_RETURN((GLCDC_PRV_GAMMA_GAIN_MAX >= p_gamma_correction->gain[i]), FSP_ERR_INVALID_GAMMA_SETTING); + } + + return FSP_SUCCESS; +} + + #endif + +/*******************************************************************************************************************//** + * The parameter checking subroutine for the R_GLCDC_Open API. + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @param[in] layer Layer number to check + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_INVALID_ALIGNMENT Invalid setting for base address and memory stride + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_param_check_layer_setting_alignment (display_cfg_t const * const p_cfg, + display_frame_layer_t layer) +{ + /* Base address and memory stride have to be aligned to 64-byte boundary */ + FSP_ERROR_RETURN(0U == ((uint32_t) (p_cfg->input[layer].p_base) % GLCDC_PRV_ADDRESS_ALIGNMENT_64B), + FSP_ERR_INVALID_ALIGNMENT); + FSP_ERROR_RETURN((uint16_t) 0 == + (((p_cfg->input[layer].hstride * + r_glcdc_get_bit_size(p_cfg->input[layer].format)) >> 3) % GLCDC_PRV_ADDRESS_ALIGNMENT_64B), + FSP_ERR_INVALID_ALIGNMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This is the parameter checking subroutine for the R_GLCDC_Open API. + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_INVALID_TIMING_SETTING Invalid panel timing parameter + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_param_check_display_cycle (display_cfg_t const * const p_cfg) +{ + FSP_ERROR_RETURN((GLCDC_PRV_BG_PLANE_H_CYC_MIN <= p_cfg->output.htiming.total_cyc) && + (GLCDC_PRV_BG_PLANE_H_CYC_MAX >= p_cfg->output.htiming.total_cyc), + FSP_ERR_INVALID_TIMING_SETTING); + FSP_ERROR_RETURN((GLCDC_PRV_BG_PLANE_V_CYC_MIN <= p_cfg->output.vtiming.total_cyc) && + (GLCDC_PRV_BG_PLANE_V_CYC_MAX >= p_cfg->output.vtiming.total_cyc), + FSP_ERR_INVALID_TIMING_SETTING); + FSP_ERROR_RETURN((GLCDC_PRV_BG_PLANE_H_CYC_ACTIVE_SIZE_MIN <= p_cfg->output.htiming.display_cyc) && + (GLCDC_PRV_BG_PLANE_H_CYC_ACTIVE_SIZE_MAX >= p_cfg->output.htiming.display_cyc), + FSP_ERR_INVALID_TIMING_SETTING); + FSP_ERROR_RETURN((GLCDC_PRV_BG_PLANE_V_CYC_ACTIVE_SIZE_MIN <= p_cfg->output.vtiming.display_cyc) && + (GLCDC_PRV_BG_PLANE_V_CYC_ACTIVE_SIZE_MAX >= p_cfg->output.vtiming.display_cyc), + FSP_ERR_INVALID_TIMING_SETTING); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This is the parameter checking subroutine for the R_GLCDC_Open API. + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_INVALID_TIMING_SETTING Invalid panel timing parameter + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_param_check_display_timing (display_cfg_t const * const p_cfg) +{ + /* p_cfg->output.htiming.back_porch / p_cfg->output.vtiming.back_porch + * |_ __________________________________ + * | |______| | + * |1|<---BP---->| + * ^GLCDC_PRV_BG_PLANE_X_CYC_ACTIVE_POS_xxx + */ + FSP_ERROR_RETURN(((GLCDC_PRV_BG_PLANE_H_CYC_ACTIVE_POS_MIN - GLCDC_PRV_BG_PLANE_HSYNC_POS_MIN) <= + p_cfg->output.htiming.back_porch) && + ((GLCDC_PRV_BG_PLANE_H_CYC_ACTIVE_POS_MAX - GLCDC_PRV_BG_PLANE_HSYNC_POS_MIN) >= + p_cfg->output.htiming.back_porch), + FSP_ERR_INVALID_TIMING_SETTING); + FSP_ERROR_RETURN(((GLCDC_PRV_BG_PLANE_V_CYC_ACTIVE_POS_MIN - GLCDC_PRV_BG_PLANE_VSYNC_POS_MIN) <= + p_cfg->output.vtiming.back_porch) && + ((GLCDC_PRV_BG_PLANE_V_CYC_ACTIVE_POS_MAX - GLCDC_PRV_BG_PLANE_VSYNC_POS_MIN) >= + p_cfg->output.vtiming.back_porch), + FSP_ERR_INVALID_TIMING_SETTING); + FSP_ERROR_RETURN((GLCDC_PRV_TCON_SIGNAL_ASSERT_WIDTH_MAX >= p_cfg->output.htiming.sync_width), + FSP_ERR_INVALID_TIMING_SETTING); + FSP_ERROR_RETURN((GLCDC_PRV_TCON_SIGNAL_ASSERT_WIDTH_MAX >= p_cfg->output.vtiming.sync_width), + FSP_ERR_INVALID_TIMING_SETTING); + + /* See "Internal configuration of output control block" in the GLCDC section of the relevant hardware manual about 3cycles */ + FSP_ERROR_RETURN((p_cfg->output.htiming.total_cyc >= + (p_cfg->output.htiming.back_porch + p_cfg->output.htiming.display_cyc + 3)), + FSP_ERR_INVALID_TIMING_SETTING); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This is the parameter checking subroutine for the R_GLCDC_Open API. + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_INVALID_TIMING_SETTING Invalid panel timing parameter + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_open_param_check_sync_signal (display_cfg_t const * const p_cfg) +{ + fsp_err_t error; + + error = r_glcdc_param_check_display_cycle(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + + error = r_glcdc_param_check_display_timing(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + + /* See "Internal definition of background screen" in the GLCDC section of the relevant hardware manual + * for explanation of +2 */ + FSP_ERROR_RETURN((p_cfg->output.vtiming.total_cyc >= + (p_cfg->output.vtiming.back_porch + p_cfg->output.vtiming.display_cyc + 2)), + FSP_ERR_INVALID_TIMING_SETTING); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The parameter checking subroutine for the R_GLCDC_Open API. + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_INVALID_LAYER_SETTING Invalid layer setting found + * @retval FSP_ERR_INVALID_ALIGNMENT Invalid setting for base address and memory stride + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_open_param_check_layer_setting (display_cfg_t const * const p_cfg) +{ + fsp_err_t error; + for (uint32_t i = 0U; i <= DISPLAY_FRAME_LAYER_2; i++) + { + if (p_cfg->input[i].p_base) + { + error = r_glcdc_param_check_layer_setting_alignment(p_cfg, (display_frame_layer_t) i); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + + /* Check horizontal/vertical pixels is less than or equal to maximum value, also horizontal pixel + * must not be an odd value. Horizontal check is intently not performed because of supporting line + * repeating mode.*/ + + uint16_t vline_size = p_cfg->input[i].vsize; + if (p_cfg->input[i].lines_repeat_enable) + { + vline_size = (uint16_t) (vline_size * p_cfg->input[i].lines_repeat_times); + } + + FSP_ERROR_RETURN((GLCDC_PRV_GR_PLANE_V_CYC_ACTIVE_SIZE_MAX >= vline_size), FSP_ERR_INVALID_LAYER_SETTING); + + /* Check horizontal/vertical pixels is less than or equal to the maximum value, also horizontal pixel must + * not be an odd value*/ + FSP_ERROR_RETURN((uint16_t) 0 == ((p_cfg->input[i].hsize) % (uint16_t) 2), FSP_ERR_INVALID_LAYER_SETTING); + + /* Check the number of data transfer times per a line (64bytes/transfer) */ + FSP_ERROR_RETURN((GLCDC_PRV_GR_PLANE_TOTAL_TRANSFER_TIMES_MAX >= + (((p_cfg->input[i].hstride * + r_glcdc_get_bit_size(p_cfg->input[i].format)) / 8) / + GLCDC_PRV_ADDRESS_ALIGNMENT_64B)), + FSP_ERR_INVALID_LAYER_SETTING); + } + } + + return FSP_SUCCESS; +} + + #if GLCDC_CFG_COLOR_CORRECTION_ENABLE + +/*******************************************************************************************************************//** + * The parameter checking subroutine for R_GLCDC_Open API. + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_ASSERTION Gain or threshold table pointers are NULL + * @retval FSP_ERR_INVALID_GAMMA_SETTING Invalid gamma correction setting found + * @retval FSP_ERR_INVALID_BRIGHTNESS_SETTING Invalid brightness correction setting found + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_open_param_check_correction_setting (display_cfg_t const * const p_cfg) +{ + fsp_err_t error; + + if (p_cfg->output.brightness.enable) + { + error = r_glcdc_param_check_brightness(&(p_cfg->output.brightness)); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + } + + if (p_cfg->output.p_gamma_correction) + { + if (p_cfg->output.p_gamma_correction->b.enable) + { + error = r_glcdc_param_check_gamma_correction(&(p_cfg->output.p_gamma_correction->b)); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + } + + if (p_cfg->output.p_gamma_correction->g.enable) + { + error = r_glcdc_param_check_gamma_correction(&(p_cfg->output.p_gamma_correction->g)); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + } + + if (p_cfg->output.p_gamma_correction->r.enable) + { + error = r_glcdc_param_check_gamma_correction(&(p_cfg->output.p_gamma_correction->r)); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + } + } + + return FSP_SUCCESS; +} + + #endif + +/*******************************************************************************************************************//** + * The parameter checking subroutine for R_GLCDC_Open API. + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL + * @retval FSP_ERR_CLOCK_GENERATION Clock ratio setting is invalid + * @retval FSP_ERR_INVALID_TIMING_SETTING Invalid panel timing parameter + * @retval FSP_ERR_INVALID_LAYER_SETTING Invalid layer setting found + * @retval FSP_ERR_INVALID_ALIGNMENT Input data alignment invalid + * @retval FSP_ERR_INVALID_GAMMA_SETTING Invalid gamma correction setting found + * @retval FSP_ERR_INVALID_BRIGHTNESS_SETTING Invalid brightness correction setting found + **********************************************************************************************************************/ +static fsp_err_t r_glcdc_open_param_check (display_cfg_t const * const p_cfg) +{ + fsp_err_t error; + + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_cfg->p_extend); + + glcdc_extended_cfg_t * pextend = (glcdc_extended_cfg_t *) p_cfg->p_extend; + + /* Sync signal parameter check */ + error = r_glcdc_open_param_check_sync_signal(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + + /* Layer setting parameter check */ + error = r_glcdc_open_param_check_layer_setting(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + + #if GLCDC_CFG_COLOR_CORRECTION_ENABLE + + /* Color correction setting parameter check */ + error = r_glcdc_open_param_check_correction_setting(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == error, error); + #endif + + /* Ensure clock division ratio is initialized */ + FSP_ERROR_RETURN(0 != pextend->clock_div_ratio, FSP_ERR_CLOCK_GENERATION); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Subroutine to configure dot clock setting + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_clock_set (display_cfg_t const * const p_cfg) +{ + glcdc_extended_cfg_t * pextend = (glcdc_extended_cfg_t *) p_cfg->p_extend; + + /* Build PANEL_CLK bitfields */ + uint32_t pixsel = + ((DISPLAY_OUT_FORMAT_8BITS_SERIAL != + p_cfg->output.format) ? 0 : GLCDC_PRV_SYSCNT_PANEL_CLK_PIXSEL_SERIALRGB); + uint32_t clksel = ((GLCDC_CLK_SRC_INTERNAL == pextend->clksrc) ? GLCDC_PRV_SYSCNT_PANEL_CLK_CLKSEL_PLL : 0); + uint32_t clken = GLCDC_PRV_SYSCNT_PANEL_CLK_CLKEN_ENABLE; + uint32_t dcdr = (pextend->clock_div_ratio & GLCDC_PRV_SYSCNT_PANEL_CLK_DCDR_MASK); + + /* Set panel clock configuration */ + R_GLCDC->SYSCNT.PANEL_CLK = pixsel | clksel | clken | dcdr; +} + +/*******************************************************************************************************************//** + * Subroutine to configure the sync signal setting (TCON block setting) + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_sync_signal_set (display_cfg_t const * const p_cfg) +{ + glcdc_extended_cfg_t * pextend = (glcdc_extended_cfg_t *) p_cfg->p_extend; + glcdc_tcon_pin_t tcon_hsync; + glcdc_tcon_pin_t tcon_vsync; + glcdc_tcon_pin_t tcon_de; + + /* Because this function is called before gamma correction is enabled we can clobber the CLKPHASE register */ + if (DISPLAY_SIGNAL_SYNC_EDGE_RISING == p_cfg->output.sync_edge) + { + /* Set all phases to rising edge */ + R_GLCDC->OUT.CLKPHASE = GLCDC_PRV_OUT_CLKPHASE_ALL_RISING; + } + else + { + /* Set all phases to falling edge */ + R_GLCDC->OUT.CLKPHASE = GLCDC_PRV_OUT_CLKPHASE_ALL_FALLING; + } + + /* Clear signal reference timing */ + R_GLCDC->TCON.TIM = 0; + + tcon_hsync = pextend->tcon_hsync; + tcon_vsync = pextend->tcon_vsync; + tcon_de = pextend->tcon_de; + + if (GLCDC_TCON_PIN_NONE != tcon_hsync) + { + r_glcdc_hsync_set(tcon_hsync, &p_cfg->output.htiming); + } + + if (GLCDC_TCON_PIN_NONE != tcon_vsync) + { + r_glcdc_vsync_set(tcon_vsync, &p_cfg->output.vtiming); + } + + if (GLCDC_TCON_PIN_NONE != tcon_de) + { + r_glcdc_data_enable_set(tcon_de, + &p_cfg->output.vtiming, + &p_cfg->output.htiming, + p_cfg->output.data_enable_polarity); + } +} + +/*******************************************************************************************************************//** + * Subroutine to configure a TCON signal output + * @param[in] tcon TCON pin select(GLCDC_TCON_PIN_0|GLCDC_TCON_PIN_1|GLCDC_TCON_PIN_2|GLCDC_TCON_PIN_3) + * @param[in] signal Signal to output + * @param[in] polarity Signal polarity + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_tcon_set (glcdc_tcon_pin_t tcon, + glcdc_tcon_signal_select_t signal, + display_signal_polarity_t polarity) +{ + /* Set signal polarity */ + if (DISPLAY_SIGNAL_POLARITY_LOACTIVE == polarity) + { + /* Set INV bit depending on register */ + if (GLCDC_TCON_SIGNAL_SELECT_DE != signal) + { + *g_tcon_lut[signal] |= GLCDC_PRV_TCON_STXX2_INV_SET; + } + else + { + R_GLCDC->TCON.DE = 1; + } + } + + /* Set TCON signal */ + *g_tcon_lut[tcon] |= signal; +} + +/*******************************************************************************************************************//** + * Subroutine to configure the horizontal signal setting + * @param[in] tcon TCON pin select(GLCDC_TCON_PIN_0|GLCDC_TCON_PIN_1|GLCDC_TCON_PIN_2|GLCDC_TCON_PIN_3) + * @param[in] timing Hsync signal timing + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_hsync_set (glcdc_tcon_pin_t tcon, display_timing_t const * timing) +{ + r_glcdc_tcon_set(tcon, GLCDC_TCON_SIGNAL_SELECT_STHA_HS, timing->sync_polarity); + + R_GLCDC->TCON.STHA1 = timing->sync_width & GLCDC_PRV_TCON_STHX1_HW_MASK; +} + +/*******************************************************************************************************************//** + * Subroutine to configure the vertical signal setting + * @param[in] tcon TCON pin select(GLCDC_TCON_PIN_0|GLCDC_TCON_PIN_1|GLCDC_TCON_PIN_2|GLCDC_TCON_PIN_3) + * @param[in] timing Vsync signal timing + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_vsync_set (glcdc_tcon_pin_t tcon, display_timing_t const * const timing) +{ + r_glcdc_tcon_set(tcon, GLCDC_TCON_SIGNAL_SELECT_STVA_VS, timing->sync_polarity); + + R_GLCDC->TCON.STVA1 = timing->sync_width & GLCDC_PRV_TCON_STVX1_VW_MASK; +} + +/*******************************************************************************************************************//** + * Subroutine to configure the data enable(DE) signal setting + * @param[in] tcon TCON pin select(GLCDC_TCON_PIN_0|GLCDC_TCON_PIN_1|GLCDC_TCON_PIN_2|GLCDC_TCON_PIN_3) + * @param[in] vtiming DE signal vertical timing + * @param[in] htiming DE signal horizontal timing + * @param[in] polarity DE signal porarity(DISPLAY_SIGNAL_POLARITY_LOACTIVE|DISPLAY_SIGNAL_POLARITY_HIACTIVE) + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_data_enable_set (glcdc_tcon_pin_t const tcon, + display_timing_t const * const vtiming, + display_timing_t const * const htiming, + display_signal_polarity_t const polarity) +{ + r_glcdc_tcon_set(tcon, GLCDC_TCON_SIGNAL_SELECT_DE, polarity); + + R_GLCDC->TCON.STHB1 = ((htiming->back_porch & GLCDC_PRV_TCON_STHX1_HS_MASK) << 16) + + (htiming->display_cyc & GLCDC_PRV_TCON_STHX1_HW_MASK); + R_GLCDC->TCON.STVB1 = ((vtiming->back_porch & GLCDC_PRV_TCON_STVX1_VS_MASK) << 16) + + (vtiming->display_cyc & GLCDC_PRV_TCON_STVX1_VW_MASK); +} + +/*******************************************************************************************************************//** + * Subroutine to configure the background screen setting + * - Panel timing setting + * - Color setting for the background screen + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_background_screen_set (display_cfg_t const * const p_cfg) +{ + /* Set number of total cycles for a line including sync, back porch and Front porch */ + R_GLCDC->BG.PERI = ((p_cfg->output.vtiming.total_cyc & GLCDC_PRV_BG_PERI_FV_MASK) << 16) + + (p_cfg->output.htiming.total_cyc & GLCDC_PRV_BG_PERI_FH_MASK); + R_GLCDC->BG.SYNC = ((GLCDC_PRV_BG_PLANE_VSYNC_POS_MIN & GLCDC_PRV_BG_SYNC_VP_MASK) << 16) + + (GLCDC_PRV_BG_PLANE_HSYNC_POS_MIN & GLCDC_PRV_BG_SYNC_HP_MASK); + + /* Set the start position and width of the background screen */ + R_GLCDC->BG.HSIZE = ((((uint32_t) (p_cfg->output.htiming.back_porch) + GLCDC_PRV_BG_PLANE_HSYNC_POS_MIN) & + GLCDC_PRV_BG_HSIZE_HP_MASK) << 16) + + (p_cfg->output.htiming.display_cyc & GLCDC_PRV_BG_HSIZE_HW_MASK); + R_GLCDC->BG.VSIZE = ((((uint32_t) (p_cfg->output.vtiming.back_porch) + GLCDC_PRV_BG_PLANE_VSYNC_POS_MIN) & + GLCDC_PRV_BG_VSIZE_VP_MASK) << 16) + + (p_cfg->output.vtiming.display_cyc & GLCDC_PRV_BG_VSIZE_VW_MASK); + + /* Set the background color */ + R_GLCDC->BG.BGC = ((uint32_t) (p_cfg->output.bg_color.byte.r) << 16) + + ((uint32_t) (p_cfg->output.bg_color.byte.g) << 8) + + ((uint32_t) (p_cfg->output.bg_color.byte.b)); +} + +/*******************************************************************************************************************//** + * Subroutine to configure the blending setting for the graphics planes + * @param[in] p_layer The layer configuration + * @param[in] layer Layer number + * @retval void + * @note This function does not perform parameter check and it would be expected to be done in the caller function. + **********************************************************************************************************************/ +static void r_glcdc_graphics_layer_blend_condition_set (display_layer_t const * const p_layer, + display_frame_layer_t const layer) +{ + uint32_t arcon_temp = 0; + uint32_t ab6_temp; + uint32_t ab7_temp; + + if (DISPLAY_FADE_CONTROL_NONE != p_layer->fade_control) + { + /* Enable alpha blending */ + arcon_temp = GLCDC_PRV_GR_AB1_ARCON_SET; + + /* Set AB6 and AB7 for fade in or fade out */ + if (DISPLAY_FADE_CONTROL_FADEIN == p_layer->fade_control) + { + ab7_temp = (GLCDC_FADING_CONTROL_INITIAL_ALPHA_MIN & GLCDC_PRV_GR_AB7_ARCDEF_MASK) << 16; + ab6_temp = ((uint32_t) p_layer->fade_speed & GLCDC_PRV_GR_AB6_ARCCOEF_MASK) << 16; + } + else + { + ab7_temp = (GLCDC_FADING_CONTROL_INITIAL_ALPHA_MAX & GLCDC_PRV_GR_AB7_ARCDEF_MASK) << 16; + ab6_temp = ((uint32_t) (p_layer->fade_speed | (1U << 8)) & GLCDC_PRV_GR_AB6_ARCCOEF_MASK) << 16; + } + + R_GLCDC->GR[layer].AB6 = ab6_temp; + R_GLCDC->GR[layer].AB7 = ab7_temp; + + /* Set g_fade_pending flag to inform R_GLCDC_StatusGet that a fade is scheduled */ + g_fade_pending[layer] = g_frame_ctr + 2; + } + + /* Set blend mode and enable if configured */ + R_GLCDC->GR[layer].AB1 = (GLCDC_PLANE_BLEND_ON_LOWER_LAYER & GLCDC_PRV_GR_AB1_DISPSEL_MASK) + arcon_temp; + + /* Graphics data read enable */ + R_GLCDC->GR[layer].FLMRD = 1U; +} + +/*******************************************************************************************************************//** + * Subroutine to recalculate the configuration for the graphics planes. This routine recalculates the layer + * configuration if the layer is beyond the left/right/top/bottom end of the active video region. + * @param[in] p_input The input frame buffer configuration + * @param[in] p_layer The layer configuration + * @param[in,out] p_recalculated Pointer to store recalculated parameter + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_graphics_layer_param_recalculation (display_input_cfg_t const * const p_input, + display_layer_t const * const p_layer, + glcdc_recalculated_param_t * p_recalculated) +{ + uint16_t bit_size = r_glcdc_get_bit_size(p_input->format); + int32_t line_offset = (int32_t) ((p_input->hstride * bit_size) / 8); + + p_recalculated->hpix_size = 0U; + p_recalculated->vpix_size = 0U; + p_recalculated->hpix_offset = 0; + p_recalculated->vpix_offset = 0; + + r_glcdc_pixel_size_recalculate(p_input, p_layer, p_recalculated, bit_size); + + int16_t coord_y = p_layer->coordinate.y; + + /* Get data size to be read in a line */ + p_recalculated->hread_size = ((uint32_t) p_recalculated->hpix_size * bit_size) / 8; + + /* If line repeat mode is enabled, data number to be read (in a line) is multiplied by line number of image */ + if (p_input->lines_repeat_enable) + { + p_recalculated->hread_size *= p_input->vsize; + } + + /* Calculate data size to be aligned to a 64-byte boundary. This is required by hardware */ + if (p_recalculated->hread_size % GLCDC_PRV_ADDRESS_ALIGNMENT_64B) + { + p_recalculated->hread_size = (p_recalculated->hread_size & (uint32_t) (~0x3F)) + // NOLINT(readability-magic-numbers) + GLCDC_PRV_ADDRESS_ALIGNMENT_64B; + } + + if ((g_ctrl_blk.vsize >= coord_y) && (0 <= coord_y)) + { + /* If graphics layer offset is less than or equal to display window size, calculate the actual pixel size to + * display */ + if ((g_ctrl_blk.vsize - coord_y) < p_input->vsize) + { + /* Actual pixel size to display is less than display window size */ + p_recalculated->vpix_size = (uint16_t) (g_ctrl_blk.vsize - coord_y); + } + else + { + /* Actual pixel size to display is the same as display window size */ + p_recalculated->vpix_size = p_input->vsize; + } + + p_recalculated->vpix_offset = coord_y; + } + else if ((0 > coord_y) && (p_input->vsize + coord_y > 0)) + { + /* If the offset of the graphics layer is less than the top end of display window but some part of the layer + * may still be visible, calculate actual pixel size to display */ + + /* Calculate actual pixel size, the pixels to be displayed is less than the display window size */ + p_recalculated->vpix_size = (uint16_t) (p_input->vsize + coord_y); + p_recalculated->base_address += (uint32_t) (line_offset * ((coord_y) * (-1))); + } + else + { + p_recalculated->vpix_size = 0U; + } +} + +/*******************************************************************************************************************//** + * Subroutine to configure the graphics layer register settings which includes... + * - Blend setting of foreground or background plane on background plane + * - Rectangle area blending settings + * @param[in] p_input The input frame buffer configuration + * @param[in] p_layer The layer configuration + * @param[in] layer Layer number + * @retval void + * @note This function does not perform parameter check and it would be expected to be done in the caller function. + **********************************************************************************************************************/ +static void r_glcdc_graphics_layer_set (display_input_cfg_t const * const p_input, + display_layer_t const * const p_layer, + display_frame_layer_t const layer) +{ + uint32_t bit_size = r_glcdc_get_bit_size(p_input->format); + int32_t line_offset = (int32_t) ((p_input->hstride * bit_size) / 8); + glcdc_recalculated_param_t recalculated; + uint32_t lnnum_temp; + uint32_t grcvw_temp; + uint32_t arcvw_temp; + + /* If the base address is NULL, just set the layer transparent and disable read memory access */ + if (NULL == p_input->p_base) + { + R_GLCDC->GR[layer].AB1 = GLCDC_PLANE_BLEND_TRANSPARENT & GLCDC_PRV_GR_AB1_DISPSEL_MASK; /* Set layer transparent */ + R_GLCDC->GR[layer].FLMRD = 0U; + + return; + } + + /* Set layer pixel color format */ + R_GLCDC->GR[layer].FLM6 = ((uint32_t) g_format_lut[p_input->format]) << 28; + + r_glcdc_graphics_layer_param_recalculation(p_input, p_layer, &recalculated); + + /* Set the base address of graphics plane */ + R_GLCDC->GR[layer].FLM2 = recalculated.base_address; + + /* If line number descending mode is enable, change its sign */ + if (p_input->line_descending_enable) + { + line_offset *= (-1); + } + + /* In line repeat mode, the GLCDC is configured to treat the entire repeated region of the buffer as a single line. + * The number of lines given in the configuration reflects how many times the pattern is repeated. */ + if (p_input->lines_repeat_enable) + { + /* Set the line offset address for accessing the graphics data on graphics plane */ + lnnum_temp = (uint32_t) (p_input->lines_repeat_times); + + /* When line repeating mode, always read data on same line(s) */ + R_GLCDC->GR[layer].FLM3 = 0; + + /* Set the total visible line count based on the size and number of the repeated region */ + grcvw_temp = (uint32_t) (recalculated.vpix_size * p_input->lines_repeat_times); + arcvw_temp = grcvw_temp; + } + else + { + /* Set the line offset address for accessing the graphics data */ + lnnum_temp = (uint32_t) (recalculated.vpix_size); + + /* Set the line offset address for accessing the graphics data on graphics plane */ + R_GLCDC->GR[layer].FLM3 = ((uint32_t) line_offset & GLCDC_PRV_GR_FLM3_LNOFF_MASK) << 16; + + /* Set the total visible line count */ + grcvw_temp = recalculated.vpix_size; + arcvw_temp = grcvw_temp; + } + + /* Set the number of data transfer times per line, 64 bytes are transferred in each transfer */ + /* Set (actual transfer times - 1) */ + R_GLCDC->GR[layer].FLM5 = (((lnnum_temp - 1) & GLCDC_PRV_GR_FLM5_LNNUM_MASK) << 16) + + (((recalculated.hread_size >> 6) - 1) & GLCDC_PRV_GR_FLM5_DATANUM_MASK); + + /* Set the graphics area horizontal dimensions */ + R_GLCDC->GR[layer].AB3 = + (((uint32_t) (g_ctrl_blk.back_porch.x + recalculated.hpix_offset) & GLCDC_PRV_GR_AB3_GRCHS_MASK) << 16) + + (recalculated.hpix_size & GLCDC_PRV_GR_AB3_GRCHW_MASK); + + /* Set the alpha blending area horizontal dimensions */ + R_GLCDC->GR[layer].AB5 = + (((uint32_t) (g_ctrl_blk.back_porch.x + recalculated.hpix_offset) & GLCDC_PRV_GR_AB5_ARCHS_MASK) << 16) + + (recalculated.hpix_size & GLCDC_PRV_GR_AB5_ARCHW_MASK); + + /* Set the graphics area vertical dimensions */ + R_GLCDC->GR[layer].AB2 = + (grcvw_temp & GLCDC_PRV_GR_AB2_GRCVW_MASK) + + (((uint32_t) (g_ctrl_blk.back_porch.y + recalculated.vpix_offset) & GLCDC_PRV_GR_AB2_GRCVS_MASK) << 16); + + /* Set the alpha blending area vertical dimensions */ + R_GLCDC->GR[layer].AB4 = + (arcvw_temp & GLCDC_PRV_GR_AB4_ARCVW_MASK) + + (((uint32_t) (g_ctrl_blk.back_porch.y + recalculated.vpix_offset) & GLCDC_PRV_GR_AB4_ARCVS_MASK) << 16); + + /* Set the alpha blending condition */ + r_glcdc_graphics_layer_blend_condition_set(p_layer, layer); + + /* Reset CLUT table selection */ + R_GLCDC->GR[layer].CLUTINT = 0; + g_clut_data_latched[0] = true; + g_clut_data_latched[1] = true; +} + +/*******************************************************************************************************************//** + * Subroutine to configure the output control block register settings which includes... + * - Bit endian / color order setting + * - Output color setting + * - Color correction setting + * @param[in] p_cfg Pointer to the configuration structure for display interface + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_output_block_set (display_cfg_t const * const p_cfg) +{ + glcdc_extended_cfg_t * pextend = (glcdc_extended_cfg_t *) p_cfg->p_extend; + uint32_t outset_temp = 0; + uint32_t pdtha_temp = 0; + + /* Select the output format */ + outset_temp = ((uint32_t) g_outset_lut[p_cfg->output.format]) << GLCDC_PRV_OUT_SET_FORMAT_SHIFT; + pdtha_temp = ((uint32_t) g_pdtha_lut[p_cfg->output.format]) << GLCDC_PRV_OUT_PDTHA_FORM_SHIFT; + + /* Selects big or little endian for output data */ + if (DISPLAY_ENDIAN_BIG == p_cfg->output.endian) + { + outset_temp |= GLCDC_PRV_OUT_SET_ENDIANON_ENABLE; + } + + /* Selects the output byte order swapping */ + if (DISPLAY_COLOR_ORDER_BGR == p_cfg->output.color_order) + { + outset_temp |= GLCDC_PRV_OUT_SET_SWAPON_ENABLE; + } + + /* Sets the pixel clock (the GLCDC internal signal) frequency in case that the output format is 8-bit serial RGB */ + if (DISPLAY_OUT_FORMAT_8BITS_SERIAL == p_cfg->output.format) + { + outset_temp |= GLCDC_PRV_OUT_SET_FRQSEL_QUARTER_DIVISION << 8; + } + + /* Set the dithering mode */ + if (p_cfg->output.dithering_on) + { + if (GLCDC_DITHERING_MODE_2X2PATTERN == pextend->dithering_mode) + { + pdtha_temp |= (uint32_t) ((GLCDC_DITHERING_MODE_2X2PATTERN << GLCDC_PRV_OUT_PDTHA_SEL_SHIFT) | + (pextend->dithering_pattern_A << GLCDC_PRV_OUT_PDTHA_PA_SHIFT) | + (pextend->dithering_pattern_B << GLCDC_PRV_OUT_PDTHA_PB_SHIFT) | + (pextend->dithering_pattern_C << GLCDC_PRV_OUT_PDTHA_PC_SHIFT) | + (pextend->dithering_pattern_D)); + } + else + { + pdtha_temp |= GLCDC_DITHERING_MODE_ROUND_OFF << GLCDC_PRV_OUT_PDTHA_SEL_SHIFT; + } + } + + /* Set registers */ + R_GLCDC->OUT.SET = outset_temp; + R_GLCDC->OUT.PDTHA = pdtha_temp; +} + +#if GLCDC_CFG_COLOR_CORRECTION_ENABLE + +/*******************************************************************************************************************//** + * Subroutine to configure the brightness register settings. Pixel color output comes to be the value + * shown below processed by the brightness control block. + * - Gout = Gin + p_cfg->output.brightness.g - 512 (output.brightness.g must be 10 bits value; up to 512) + * - Bout = Bin + p_cfg->output.brightness.b - 512 (output.brightness.b must be 10 bits value; up to 512) + * - Rout = Rin + p_cfg->output.brightness.r - 512 (output.brightness.r must be 10 bits value; up to 512) + * @param[in] p_ctrl Pointer to the control block for Display Interface + * @param[in] p_brightness Pointer to brightness configuration structure + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_brightness_correction (glcdc_instance_ctrl_t const * const p_ctrl, + display_brightness_t const * const p_brightness) +{ + uint32_t r; + uint32_t g; + uint32_t b; + + if (p_brightness->enable) + { + g = p_brightness->g; + b = p_brightness->b; + r = p_brightness->r; + } + else + { + if (DISPLAY_STATE_CLOSED == p_ctrl->state) + { + /* If brightness setting in configuration is 'off', apply default value */ + g = GLCDC_PRV_BRIGHTNESS_DEFAULT; + b = GLCDC_PRV_BRIGHTNESS_DEFAULT; + r = GLCDC_PRV_BRIGHTNESS_DEFAULT; + } + else + { + return; + } + } + + /* Sets brightness correction register for each color in a pixel. */ + R_GLCDC->OUT.BRIGHT1 = g & GLCDC_PRV_OUT_BRIGHT1_BRTG_MASK; + R_GLCDC->OUT.BRIGHT2 = ((b & GLCDC_PRV_OUT_BRIGHT2_BRTB_MASK) << 16) + (r & GLCDC_PRV_OUT_BRIGHT2_BRTR_MASK); +} + +/*******************************************************************************************************************//** + * Subroutine to configure the contrast register settings. Pixel color output becomes the value + * shown below, processed by the contrast control block. Contrast can be changed between x0.000 to x1.992 + * (0x0:x0.000 / 0x80:x1.000 / 0xFF:x1.992). + * - Gout = (Gin + p_contrast->g)/128 + * - Bout = (Bin + p_contrast->b)/128 + * - Rout = (Rin + p_contrast->r)/128 + * @param[in] p_ctrl Pointer to the control block for the Display Interface + * @param[in] p_contrast Pointer to the contrast configuration structure + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_contrast_correction (glcdc_instance_ctrl_t const * const p_ctrl, + display_contrast_t const * const p_contrast) +{ + uint32_t r; + uint32_t g; + uint32_t b; + + if (p_contrast->enable) + { + g = p_contrast->g; + b = p_contrast->b; + r = p_contrast->r; + } + else + { + if (DISPLAY_STATE_CLOSED == p_ctrl->state) + { + /* If the contrast setting in the configuration is set to 'off', apply default value */ + g = GLCDC_PRV_CONTRAST_DEFAULT; + b = GLCDC_PRV_CONTRAST_DEFAULT; + r = GLCDC_PRV_CONTRAST_DEFAULT; + } + else + { + return; + } + } + + /* Sets the contrast correction register for each color in a pixel. */ + R_GLCDC->OUT.CONTRAST = ((g & GLCDC_PRV_OUT_CONTRAST_CONTG_MASK) << 16) + + ((b & GLCDC_PRV_OUT_CONTRAST_CONTB_MASK) << 8) + + (r & GLCDC_PRV_OUT_CONTRAST_CONTR_MASK); +} + +/*******************************************************************************************************************//** + * Subroutine to configure the color correction order. + * + * @param[in] p_cfg Pointer to the configuration structure for the display interface + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_color_correction_order (display_cfg_t const * const p_cfg) +{ + glcdc_extended_cfg_t * pextend = (glcdc_extended_cfg_t *) p_cfg->p_extend; + + /* Sets the Brightness/contrast and Gamma Correction processing order */ + if (GLCDC_CORRECTION_PROC_ORDER_BRIGHTNESS_CONTRAST2GAMMA == pextend->correction_proc_order) + { + /* OUT_CLKPHASE (LCDC clock source is PLCKA) + * b12 FRONTGAM = 0(Brightness/contrast correction is followed by gamma correction.) + */ + R_GLCDC->OUT.CLKPHASE_b.FRONTGAM = 0U; + } + else + { + /* OUT_CLKPHASE (LCDC clock source is PLCKA) + * b12 FRONTGAM = 1(Gamma correction is followed by Brightness/contrast correction) + */ + R_GLCDC->OUT.CLKPHASE_b.FRONTGAM = 1U; + } +} + +/*******************************************************************************************************************//** + * Subroutine to configure the gamma correction register setting. + * @param[in] p_cfg Pointer to the configuration structure for the display interface + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_gamma_correction (display_cfg_t const * const p_cfg) +{ + uint8_t i; + uint8_t j; + + gamma_correction_t * LUT_ptr; + + /* Set gamma correction LUTs based on config struct */ + for (j = 0U; j < 3U; j++) + { + /* Get pointer to LUT */ + switch (j) + { + default: + case 0: + { + LUT_ptr = &(p_cfg->output.p_gamma_correction->g); + break; + } + + case 1: + { + LUT_ptr = &(p_cfg->output.p_gamma_correction->b); + break; + } + + case 2: + { + LUT_ptr = &(p_cfg->output.p_gamma_correction->r); + break; + } + } + + if (LUT_ptr->enable) + { + for (i = 0U; i < (uint8_t) (DISPLAY_GAMMA_CURVE_ELEMENT_NUM / 2); i++) + { + R_GLCDC->GAM[j].LUT[i] = ((LUT_ptr->gain[i * 2U] & GLCDC_PRV_GAMX_LUTX_GAIN_MASK) << 16) + + (LUT_ptr->gain[(i * 2U) + 1U] & GLCDC_PRV_GAMX_LUTX_GAIN_MASK); + } + + for (i = 0U; i < (uint8_t) (DISPLAY_GAMMA_CURVE_ELEMENT_NUM / 3); i++) + { + R_GLCDC->GAM[j].AREA[i] = ((LUT_ptr->threshold[(i * 3U) + 1U] & GLCDC_PRV_GAMX_AREAX_MASK) << 20) + + ((LUT_ptr->threshold[(i * 3U) + 2U] & GLCDC_PRV_GAMX_AREAX_MASK) << 10) + + (LUT_ptr->threshold[(i * 3U) + 3U] & GLCDC_PRV_GAMX_AREAX_MASK); + } + + /* Enable LUT */ + R_GLCDC->GAM[j].GAM_SW = 1U; + } + else + { + R_GLCDC->GAM[j].GAM_SW = 0U; + } + + R_GLCDC->GAM[j].LATCH = 1U; + } +} + +#endif + +/*******************************************************************************************************************//** + * Subroutine to get the bit size of the specified format. + * @param[in] format Color format (specify display_in_format_t type enumeration value) + * @retval Bit size + **********************************************************************************************************************/ +static inline uint16_t r_glcdc_get_bit_size (display_in_format_t const format) +{ + return g_pixsize_lut[format]; +} + +/*******************************************************************************************************************//** + * The line detection interrupt service routine. + * This ISR is called when the number of the display line reaches the designated number of lines. If a + * callback function is registered in R_GLCDC_Open(), it is called from this ISR and the + * DISPLAY_EVENT_LINE_DETECTION event code is set as its argument. + * @retval none + **********************************************************************************************************************/ +void glcdc_line_detect_isr (void) +{ + FSP_CONTEXT_SAVE + + display_callback_args_t args; + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) g_ctrl_blk.p_context; + + /* Increment frame counter */ + g_frame_ctr++; + + /* Handle overflow case for g_frame_ctr vs. g_fade_pending + * (at 60FPS this should occur once every 2.25 years of uptime) */ + if (!g_frame_ctr) + { + g_fade_pending[0] = 0; + g_fade_pending[1] = 0; + } + + /* Set CLUT state to latched */ + g_clut_data_latched[0] = true; + g_clut_data_latched[1] = true; + + /* Call back callback function if it is registered */ + if (NULL != p_ctrl->p_callback) + { + args.event = DISPLAY_EVENT_LINE_DETECTION; + args.p_context = p_ctrl->p_context; + p_ctrl->p_callback(&args); + } + + /* Clear interrupt flag in the register of the GLCDC module */ + R_GLCDC->SYSCNT.STCLR_b.VPOSCLR = 1U; + + /* Clear interrupt flag in the register of the NVIC module */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * The graphics plane 1 underflow detection interrupt service routine. + * This ISR is called when the underflow occurs in the graphics plane 1 control block. If a callback function + * is registered in R_GLCDC_Open(), it is called back from this ISR and the DISPLAY_EVENT_GR1_UNDERFLOW event + * code is set as its argument. + * @retval none + **********************************************************************************************************************/ +void glcdc_underflow_1_isr (void) +{ + FSP_CONTEXT_SAVE + + display_callback_args_t args; + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) g_ctrl_blk.p_context; + + /* Call back callback function if it is registered */ + if (NULL != p_ctrl->p_callback) + { + args.event = DISPLAY_EVENT_GR1_UNDERFLOW; + args.p_context = p_ctrl->p_context; + p_ctrl->p_callback(&args); + } + + /* Clear interrupt flag in the register of the GLCDC module */ + R_GLCDC->SYSCNT.STCLR_b.L1UNDFCLR = 1U; + + /* Clear interrupt flag in the register of the NVIC module */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * The graphics plane 2 underflow detection interrupt service routine. + * This ISR is called when the underflow occurs in the graphics plane 2 control block. If a callback function + * is registered in R_GLCDC_Open(), it is called from this ISR and the DISPLAY_EVENT_GR2_UNDERFLOW event + * code is set as its argument. + * @retval none + **********************************************************************************************************************/ +void glcdc_underflow_2_isr (void) +{ + FSP_CONTEXT_SAVE + + display_callback_args_t args; + glcdc_instance_ctrl_t * p_ctrl = (glcdc_instance_ctrl_t *) g_ctrl_blk.p_context; + + /* Call the callback function if it is registered */ + if (NULL != p_ctrl->p_callback) + { + args.event = DISPLAY_EVENT_GR2_UNDERFLOW; + args.p_context = p_ctrl->p_context; + p_ctrl->p_callback(&args); + } + + /* Clear interrupt flag in the register of the GLCDC module */ + R_GLCDC->SYSCNT.STCLR_b.L2UNDFCLR = 1U; + + /* Clear interrupt flag in the register of the NVIC module */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Enable the glcdc interrupt. + * @param[in] p_instance_ctrl Pointer to GLCDC instance struct + * @retval none + **********************************************************************************************************************/ +static void r_glcdc_interrupt_enable (glcdc_instance_ctrl_t * p_instance_ctrl) +{ + /* Enable the GLCDC interrupts */ + R_GLCDC->SYSCNT.DTCTEN = GLCDC_PRV_SYSCNT_DTCTEN_INIT; // VPOS interrupt is enabled in R_GLCDC_Start + R_GLCDC->SYSCNT.INTEN = GLCDC_PRV_SYSCNT_INTEN_INIT; + + if (p_instance_ctrl->p_cfg->line_detect_irq >= 0) + { + R_BSP_IrqCfgEnable(p_instance_ctrl->p_cfg->line_detect_irq, + p_instance_ctrl->p_cfg->line_detect_ipl, + p_instance_ctrl); + } + + if (p_instance_ctrl->p_cfg->underflow_1_irq >= 0) + { + R_BSP_IrqCfgEnable(p_instance_ctrl->p_cfg->underflow_1_irq, + p_instance_ctrl->p_cfg->underflow_1_ipl, + p_instance_ctrl); + } + + if (p_instance_ctrl->p_cfg->underflow_2_irq >= 0) + { + R_BSP_IrqCfgEnable(p_instance_ctrl->p_cfg->underflow_2_irq, + p_instance_ctrl->p_cfg->underflow_2_ipl, + p_instance_ctrl); + } +} + +/*******************************************************************************************************************//** + * Calculate the pixels to be displayed on window based on the offset of the graphic layer. + * @param[in] p_input The input frame buffer configuration + * @param[in] p_layer The layer configuration + * @param[in,out] p_recalculated Pointer to store recalculated parameter + * @param[in] bit_size Pointer to bit size of the color format + * @retval void + **********************************************************************************************************************/ +static void r_glcdc_pixel_size_recalculate (display_input_cfg_t const * const p_input, + display_layer_t const * const p_layer, + glcdc_recalculated_param_t * p_recalculated, + uint16_t bit_size) +{ + uint16_t hpix_size_temp; + int16_t hpix_offset_temp; /* Offset can be signed value */ + uint32_t base_address_temp; + + int16_t coord_x = p_layer->coordinate.x; + + if ((g_ctrl_blk.hsize >= coord_x) && (0 <= coord_x)) + { + /* If the offset of the graphics layer is greater than or equal to zero and it is less than or + * equal to the size of the display window, calculate actual pixel size to display. + */ + if ((g_ctrl_blk.hsize - (uint16_t) coord_x) < p_input->hsize) + { + /* Calculate actual pixel size, the pixels to be displayed is less than the display window size */ + hpix_size_temp = (uint16_t) (g_ctrl_blk.hsize - (uint16_t) coord_x); + } + else + { + /* Actual pixel size to display is same as the display window size */ + hpix_size_temp = p_input->hsize; + } + + p_recalculated->hpix_offset = coord_x; + base_address_temp = (uint32_t) p_input->p_base; + } + else if ((0 > coord_x) && (p_input->hsize + coord_x > 0)) + { + /* If the offset of the graphics layer is less than zero but part of the layer would still be visible, calculate + * the actual pixel size to display. */ + + /* If coordinate.x is a minus value, the layer image position can be adjusted not only by adjusting + * the horizontal offset but also by changing the base address of layer image. Since the base address + * has to be aligned to 64 bytes, we need to adjust the horizontal offset, which is the cycles from + * the 'internal zero' to the start cycle of active video region to achieve 1 pixel unit offset. + * We need to adjust the size of image to display as well. + */ + int16_t adj_cycles = 1; + if (bit_size >= 8) + { + adj_cycles = (int16_t) (GLCDC_PRV_OFFSET_MARGIN_MINUS_64PIX / ((bit_size) / 8)); + } + + if (g_ctrl_blk.back_porch.x < adj_cycles) + { + /* If there is not enough cycles for the offset adjustment, simply do not adjust. */ + hpix_offset_temp = 0; + hpix_size_temp = (uint16_t) (p_input->hsize - (((coord_x * (-1)) / adj_cycles) * adj_cycles)); + } + else + { + /* If there are cycles for the offset adjustment, adjust pixel offset and size */ + hpix_offset_temp = (int16_t) (((coord_x * (-1)) % adj_cycles) * (-1)); + hpix_size_temp = (uint16_t) ((p_input->hsize + coord_x) + ((coord_x * (-1)) % adj_cycles)); + } + + p_recalculated->hpix_offset = hpix_offset_temp; + + /* Base address must be aligned to a 64-bit address */ + uint32_t offset_address = (uint32_t) (((coord_x * (-1)) * (bit_size)) / 8); + base_address_temp = ((uint32_t) p_input->p_base + offset_address) & (uint32_t) (~0x3F); // NOLINT(readability-magic-numbers) + } + else + { + /* If graphics layer offset is beyond the display window size, set the pixel size to display to zero */ + hpix_size_temp = 0U; + base_address_temp = (uint32_t) p_input->p_base; + } + + p_recalculated->hpix_size = hpix_size_temp; + p_recalculated->base_address = base_address_temp; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gpt/r_gpt.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gpt/r_gpt.c new file mode 100644 index 0000000000..c2a62e5982 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gpt/r_gpt.c @@ -0,0 +1,2078 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_gpt.h" +#include "r_gpt_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "GPT" in ASCII, used to determine if channel is open. */ +#define GPT_OPEN (0x00475054ULL) + +/* define in case unsupported */ +#ifndef BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK + #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0) +#endif +#ifndef BSP_FEATURE_GPT_GPTE_CHANNEL_MASK + #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0) +#endif +#ifndef BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK + #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0) +#endif + +#define GPT_PRV_GPTE_OR_GPTEH_SUPPORTED (BSP_FEATURE_GPT_GPTEH_SUPPORTED | \ + BSP_FEATURE_GPT_GPTE_SUPPORTED) +#define GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK (BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK | \ + BSP_FEATURE_GPT_GPTE_CHANNEL_MASK) +#define GPT_PRV_ADC_DIRECT_START_SUPPORTED (BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED) +#define GPT_PRV_ADC_CONVERSION_START_CHANNEL_MASK (BSP_FEATURE_GPT_AD_CONVERSION_START_CHANNEL_MASK) +#define GPT_PRV_ADC_CONVERSION_START_SUPPORTED (GPT_PRV_GPTE_OR_GPTEH_SUPPORTED | \ + GPT_PRV_ADC_DIRECT_START_SUPPORTED) +#define GPT_PRV_ODC_SUPPORTED (BSP_FEATURE_GPT_GPTEH_SUPPORTED) +#define GPT_PRV_ODC_CHANNEL_MASK (BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK) +#define GPT_PRV_GTWP_RESET_VALUE (0xA500U) +#define GPT_PRV_GTWP_WRITE_PROTECT (0xA501U) + +#define GPT_PRV_GTIOR_STOP_LEVEL_BIT (6) +#define GPT_PRV_GTIOR_INITIAL_LEVEL_BIT (4) + +#define GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END (0x6U) +#define GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END (0x9U) + +#define GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH (0x3U) + +#define GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER (0x550000U) +#define GPT_PRV_GTBER_DISABLE_BUFFER_OP_GTCCRA_GTCCRB (0x500000U) + +#define GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE (0x80000000U) + +#define GPT_PRV_GTCCRA (0U) +#define GPT_PRV_GTCCRB (1U) +#define GPT_PRV_GTCCRC (2U) +#define GPT_PRV_GTCCRE (3U) +#define GPT_PRV_GTCCRD (4U) +#define GPT_PRV_GTCCRF (5U) + +#define GPT_PRV_GTCCR_AB_MASK (0x03U) + +/* This macro is used to match the address order of GTCCRk registers and enum timer_compare_match_t. */ +#define GPT_PRV_GTCCR(ch) (TIMER_COMPARE_MATCH_D == \ + (ch) ? GPT_PRV_GTCCRD : (TIMER_COMPARE_MATCH_E == (ch) ? GPT_PRV_GTCCRE : (ch))) + +/* GPT_CFG_OUTPUT_SUPPORT_ENABLE is set to 2 to enable extra features. */ +#define GPT_PRV_EXTRA_FEATURES_ENABLED (2U) + +#define R_GPT0_GTINTAD_ADTRAUEN_Pos (16U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Duty cycle mode. */ +typedef enum e_gpt_duty_cycle_mode +{ + GPT_DUTY_CYCLE_MODE_REGISTER = 0, // Duty cycle depends on compare match + GPT_DUTY_CYCLE_MODE_0_PERCENT = 2, // Output low + GPT_DUTY_CYCLE_MODE_100_PERCENT = 3, // Output high +} gpt_duty_cycle_mode_t; + +/* Count direction */ +typedef enum e_gpt_dir +{ + GPT_DIR_COUNT_DOWN = 0, + GPT_DIR_COUNT_UP = 1 +} gpt_dir_t; + +typedef struct st_gpt_prv_duty_registers +{ + uint32_t gtccr_buffer; + uint32_t omdty; +} gpt_prv_duty_registers_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * gpt_prv_ns_callback)(timer_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile gpt_prv_ns_callback)(timer_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void gpt_hardware_initialize(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg); + +static void gpt_common_open(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg); + +static uint32_t gpt_clock_frequency_get(gpt_instance_ctrl_t * const p_instance_ctrl); + +static void gpt_hardware_events_disable(gpt_instance_ctrl_t * p_instance_ctrl); + +__STATIC_INLINE void r_gpt_disable_irq(IRQn_Type irq); + +static inline void r_gpt_write_protect_enable(gpt_instance_ctrl_t * const p_instance_ctrl, + uint32_t write_protect_setting); +static inline uint32_t r_gpt_write_protect_disable(gpt_instance_ctrl_t * const p_instance_ctrl); + +__STATIC_INLINE void r_gpt_enable_irq(IRQn_Type const irq, uint32_t priority, void * p_context); + +__STATIC_INLINE void r_gpt_clear_pending_irq(IRQn_Type irq); + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + +static void gpt_calculate_duty_cycle(gpt_instance_ctrl_t * const p_instance_ctrl, + uint32_t const duty_cycle_counts, + gpt_prv_duty_registers_t * p_duty_reg, + uint32_t pin); + +static uint32_t gpt_gtior_calculate(timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level); + +#endif + +static void r_gpt_call_callback(gpt_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture); + +static void r_gpt_init_compare_match_channel(gpt_instance_ctrl_t * p_instance_ctrl); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void gpt_counter_overflow_isr(void); +void gpt_counter_underflow_isr(void); +void gpt_capture_compare_a_isr(void); +void gpt_capture_compare_b_isr(void); +void gpt_compare_match_c_isr(void); +void gpt_compare_match_d_isr(void); +void gpt_compare_match_e_isr(void); +void gpt_compare_match_f_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* GPT implementation of timer interface */ +const timer_api_t g_timer_on_gpt = +{ + .open = R_GPT_Open, + .stop = R_GPT_Stop, + .start = R_GPT_Start, + .reset = R_GPT_Reset, + .enable = R_GPT_Enable, + .disable = R_GPT_Disable, + .periodSet = R_GPT_PeriodSet, + .dutyCycleSet = R_GPT_DutyCycleSet, + .compareMatchSet = R_GPT_CompareMatchSet, + .infoGet = R_GPT_InfoGet, + .statusGet = R_GPT_StatusGet, + .callbackSet = R_GPT_CallbackSet, + .close = R_GPT_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup GPT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open. + * + * GPT hardware does not support one-shot functionality natively. When using one-shot mode, the timer will be stopped + * in an ISR after the requested period has elapsed. + * + * The GPT implementation of the general timer can accept a gpt_extended_cfg_t extension parameter. + * + * Example: + * @snippet r_gpt_example.c R_GPT_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the source divider is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED timer_cfg_t::mode is ::TIMER_MODE_ONE_SHOT or timer_cfg_t::p_callback is not + * NULL, but ISR is not enabled. ISR must be enabled to use one-shot mode or + * callback. + * @retval FSP_ERR_INVALID_MODE Triangle wave PWM is only supported if GPT_CFG_OUTPUT_SUPPORT_ENABLE is 2. + * Selected channel does not support external count sources. + * External and event count sources not are available in this mode. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_instance_ctrl); + + #if (2U == BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE) + #if (BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID) + FSP_ASSERT(p_cfg->source_div <= 10U); + #else + FSP_ASSERT((p_cfg->source_div != 7U) && (p_cfg->source_div != 9U) && (p_cfg->source_div <= 10)); + #endif + #else + FSP_ASSERT((0U == (p_cfg->source_div % 2U)) && (p_cfg->source_div <= 10)); + #endif + + #if GPT_PRV_EXTRA_FEATURES_ENABLED != GPT_CFG_OUTPUT_SUPPORT_ENABLE + FSP_ERROR_RETURN(p_cfg->mode <= TIMER_MODE_ONE_SHOT_PULSE, FSP_ERR_INVALID_MODE); + #endif + + FSP_ERROR_RETURN(GPT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + p_instance_ctrl->channel_mask = 1U << p_cfg->channel; + +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN((p_instance_ctrl->channel_mask & BSP_PERIPHERAL_GPT_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + if ((p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode)) + { + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend; + FSP_ERROR_RETURN((!p_extend->count_up_source && !p_extend->count_down_source) || + (BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK & p_instance_ctrl->channel_mask), + FSP_ERR_INVALID_MODE); + + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Alternate count sources cannot be used in triangle PWM modes */ + FSP_ERROR_RETURN(!((p_cfg->mode >= TIMER_MODE_ONE_SHOT_PULSE) && + (p_extend->count_up_source || p_extend->count_down_source)), + FSP_ERR_INVALID_MODE); + + /* Callback is required if underflow interrupt is enabled. */ + gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg; + + if (NULL != p_pwm_cfg) + { + if (p_pwm_cfg->trough_irq >= 0) + { + FSP_ASSERT(NULL != p_cfg->p_callback); + } + } + #endif +#endif + + /* Initialize control structure based on configurations. */ + gpt_common_open(p_instance_ctrl, p_cfg); + + gpt_hardware_initialize(p_instance_ctrl, p_cfg); + + p_instance_ctrl->open = GPT_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops timer. Implements @ref timer_api_t::stop. + * + * Example: + * @snippet r_gpt_example.c R_GPT_Stop + * + * @retval FSP_SUCCESS Timer successfully stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Stop (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Stop timer */ + p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts timer. Implements @ref timer_api_t::start. + * + * Example: + * @snippet r_gpt_example.c R_GPT_Start + * + * @retval FSP_SUCCESS Timer successfully started. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Start (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Start timer */ + p_instance_ctrl->p_reg->GTSTR = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter value to 0. Implements @ref timer_api_t::reset. + * + * @note This function also updates to the new period if no counter overflow has occurred since the last call to + * R_GPT_PeriodSet(). + * + * @retval FSP_SUCCESS Counter value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Reset (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear timer counter. */ + p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable. + * + * Example: + * @snippet r_gpt_example.c R_GPT_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Enable (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint32_t gtssr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + uint32_t gtpsr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + uint32_t gtcsr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + + /* OR with user settings. */ + gtssr |= p_extend->start_source; + gtpsr |= p_extend->stop_source; + gtcsr |= p_extend->clear_source; + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + /* Set the count sources. Ensure stop and clear sources are set before start source, and capture sources are set + * after start source. */ + p_instance_ctrl->p_reg->GTPSR = gtpsr; + p_instance_ctrl->p_reg->GTCSR = gtcsr; + p_instance_ctrl->p_reg->GTSSR = gtssr; + p_instance_ctrl->p_reg->GTICASR = p_extend->capture_a_source; + p_instance_ctrl->p_reg->GTICBSR = p_extend->capture_b_source; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables external event triggers that start, stop, clear, or capture the counter. + * Implements @ref timer_api_t::disable. + * + * @note The timer could be running after R_GPT_Disable(). To ensure it is stopped, call R_GPT_Stop(). + * + * Example: + * @snippet r_gpt_example.c R_GPT_Disable + * + * @retval FSP_SUCCESS External events successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Disable (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + gpt_hardware_events_disable(p_instance_ctrl); + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets period value provided. If the timer is running, the period will be updated after the next counter overflow. + * If the timer is stopped, this function resets the counter and updates the period. + * Implements @ref timer_api_t::periodSet. + * + * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register. + * If this function is called while the timer is running and a GPT overflow occurs during processing, the duty cycle + * will not be the desired 50% duty cycle until the counter overflow after processing completes. + * + * Example: + * @snippet r_gpt_example.c R_GPT_PeriodSet + * + * @retval FSP_SUCCESS Period value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + /* Update period buffer register. The actual period is one cycle longer than the register value for saw waves and + * twice the register value for triangle waves. Reference section "General PWM Timer Cycle Setting Register (GTPR)". + * The setting passed to the configuration is expected to be half the desired period for triangle waves. */ + uint32_t new_gtpr = period_counts - 1U; +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + new_gtpr = period_counts; + } +#endif + + p_instance_ctrl->p_reg->GTPBR = new_gtpr; + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Set a 50% duty cycle so the period of the waveform on the output pin matches the requested period. */ + if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode) + { + /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. See + * figure "Example setting for saw-wave PWM mode" in the GPT section of the relevant hardware manual. + * To get a duty cycle as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */ + uint32_t duty_cycle_50_percent = (period_counts >> 1) - 1U; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_cycle_50_percent; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRE] = duty_cycle_50_percent; + } +#endif + + /* If the counter is not counting, update period register and reset counter. */ + if (0U == p_instance_ctrl->p_reg->GTCR_b.CST) + { + p_instance_ctrl->p_reg->GTPR = new_gtpr; + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER; +#endif + + p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; + } + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets duty cycle on requested pin. Implements @ref timer_api_t::dutyCycleSet. + * + * Duty cycle is updated in the buffer register. The updated duty cycle is reflected after the next cycle end (counter + * overflow). + * + * Example: + * @snippet r_gpt_example.c R_GPT_DutyCycleSet + * + * @param[in] p_ctrl Pointer to instance control block. + * @param[in] duty_cycle_counts Duty cycle to set in counts. + * @param[in] pin Use gpt_io_pin_t to select GPT_IO_PIN_GTIOCA or GPT_IO_PIN_GTIOCB + * + * @retval FSP_SUCCESS Duty cycle updated successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL or the pin is not one of gpt_io_pin_t + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Duty cycle is larger than period. + * @retval FSP_ERR_INVALID_MODE GPT_IO_PIN_TROUGH, and GPT_IO_PIN_CREST settings are invalid in the this mode. + * @retval FSP_ERR_UNSUPPORTED GPT_CFG_OUTPUT_SUPPORT_ENABLE is 0. + **********************************************************************************************************************/ +fsp_err_t R_GPT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + uint32_t tmp_pin = pin & 3U; + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; + #if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(tmp_pin <= GPT_IO_PIN_GTIOCA_AND_GTIOCB); + bool pwm_mode3_pin = 0 != (pin & (GPT_IO_PIN_CREST | GPT_IO_PIN_TROUGH)); + if (TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 == p_instance_ctrl->p_cfg->mode) + { + /* In TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3, the duty cycle must be for either a trough or crest. */ + FSP_ERROR_RETURN(pwm_mode3_pin, FSP_ERR_INVALID_MODE); + } + else + { + FSP_ERROR_RETURN((!pwm_mode3_pin) || (TIMER_MODE_ONE_SHOT_PULSE == p_instance_ctrl->p_cfg->mode), + FSP_ERR_INVALID_MODE); + } + + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(duty_cycle_counts <= (p_instance_ctrl->p_reg->GTPBR + 1), FSP_ERR_INVALID_ARGUMENT); + #endif + + /* Set duty cycle. */ + gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0}; + + gpt_calculate_duty_cycle(p_instance_ctrl, duty_cycle_counts, &duty_regs, pin); + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + /* Read modify write bitfield access is used to update GTUDDTYC to make sure we don't clobber settings for the + * other pin. */ + uint32_t gtuddtyc = p_instance_ctrl->p_reg->GTUDDTYC; + + /* Only update GTCCR if 0% or 100% duty is not requested */ + if (!duty_regs.omdty) + { + uint32_t reg_offset = 2U; + if (0 != (pin & GPT_IO_PIN_CREST)) + { + /* + * In TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3, if this is a crest duty cycle, then update the crest + * duty cycle register. Otherwise, update the trough duty cycle register. + * Or in case of One-Shot pulse mode, buffer registers are either GTCCRC and GTCCRD for pulses on GTIOCnA + * pin or GTCCRE and GTCCRF for pulses on GTIOCnB pin. + * Hence update registers GTCCRD, GTCCRF for trailing edge dutycycle counts on GTIOCnA, GTIOCnB + * respectively, otherwise update registers GTCCRC,GTCCRE for leading edge dutycycle counts on GTIOCnA, + * GTIOCnB respectively. + */ + reg_offset = 4U; + } + + if (0 != (pin & GPT_IO_PIN_GTIOCA_AND_GTIOCB)) + { + p_instance_ctrl->p_reg->GTCCR[reg_offset] = duty_regs.gtccr_buffer; + p_instance_ctrl->p_reg->GTCCR[reg_offset + 1] = duty_regs.gtccr_buffer; + } + else + { + p_instance_ctrl->p_reg->GTCCR[tmp_pin + reg_offset] = duty_regs.gtccr_buffer; + } + } + + if (0 != (pin & GPT_BUFFER_FORCE_PUSH)) + { + /* Enable the compare match buffer. */ + p_instance_ctrl->p_reg->GTBER |= 1U << R_GPT0_GTBER_CCRSWT_Pos; + } + + if (GPT_IO_PIN_GTIOCB != tmp_pin) + { + /* GTIOCA or both GTIOCA and GTIOCB. */ + gtuddtyc &= ~R_GPT0_GTUDDTYC_OADTY_Msk; + gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OADTY_Pos; + } + + if ((GPT_IO_PIN_GTIOCA_AND_GTIOCB == pin) && duty_regs.omdty) + { + /* When setting both pins to 0%/100% duty recalculate OBDTY before setting */ + gpt_calculate_duty_cycle(p_instance_ctrl, duty_cycle_counts, &duty_regs, GPT_IO_PIN_GTIOCB); + } + + if (GPT_IO_PIN_GTIOCA != tmp_pin) + { + /* GTIOCB or both GTIOCA and GTIOCB. */ + gtuddtyc &= ~R_GPT0_GTUDDTYC_OBDTY_Msk; + gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OBDTY_Pos; + } + + p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(duty_cycle_counts); + FSP_PARAMETER_NOT_USED(pin); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Set value for compare match feature. Implements @ref timer_api_t::compareMatchSet. + * + * @note This API should be used when timer is stop counting. And shall not be used along with PWM operation. + * + * Example: + * @snippet r_gpt_example.c R_GPT_CompareMatchSet + * + * @retval FSP_SUCCESS Set the compare match value successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_UNSUPPORTED Requested compare match channel is not supported. + * @retval FSP_ERR_NOT_ENABLED Requested compare match channel is disabled. + **********************************************************************************************************************/ +fsp_err_t R_GPT_CompareMatchSet (timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; + +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* GPT module does not support Compare match channel G, H */ + FSP_ERROR_RETURN(TIMER_COMPARE_MATCH_F >= match_channel, FSP_ERR_UNSUPPORTED); + + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Confirm that requested compare match channel is enabled */ + FSP_ERROR_RETURN(p_extend->compare_match_status & (1U << match_channel), FSP_ERR_NOT_ENABLED); +#endif + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + /* The actual period is one cycle longer than the register value for saw waves. Reference section "General PWM + * Timer Cycle Setting Register (GTPR)" */ + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCR(match_channel)] = compare_match_value - 1U; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_gpt_example.c R_GPT_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, frequency, and ELC event written to caller's + * structure successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_info was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Get and store period */ + uint32_t gtpr = p_instance_ctrl->p_reg->GTPR; + uint32_t period_counts = gtpr + 1; +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + period_counts = gtpr; + } +#endif + p_info->period_counts = period_counts; + + /* Get and store clock frequency */ + p_info->clock_frequency = gpt_clock_frequency_get(p_instance_ctrl); + + /* Get and store clock counting direction. Read count direction setting */ + p_info->count_direction = TIMER_DIRECTION_UP; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get current timer status and store it in provided pointer p_status. Implements @ref timer_api_t::statusGet. + * + * Example: + * @snippet r_gpt_example.c R_GPT_StatusGet + * + * @retval FSP_SUCCESS Current timer state and counter value set successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Get counter state. */ + p_status->state = (timer_state_t) p_instance_ctrl->p_reg->GTCR_b.CST; + + /* Get counter value */ + p_status->counter = p_instance_ctrl->p_reg->GTCNT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set counter value. + * + * @note Do not call this API while the counter is counting. The counter value can only be updated while the counter + * is stopped. + * + * @retval FSP_SUCCESS Counter value updated. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IN_USE The timer is running. Stop the timer before calling this function. + **********************************************************************************************************************/ +fsp_err_t R_GPT_CounterSet (timer_ctrl_t * const p_ctrl, uint32_t counter) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->GTCR_b.CST, FSP_ERR_IN_USE); +#endif + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + /* Set counter value */ + p_instance_ctrl->p_reg->GTCNT = counter; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable output for GTIOCA and/or GTIOCB. + * + * @retval FSP_SUCCESS Output is enabled. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_OutputEnable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + uint32_t gtior = p_instance_ctrl->p_reg->GTIOR; + if (GPT_IO_PIN_GTIOCB != pin) + { + /* GTIOCA or both GTIOCA and GTIOCB. */ + gtior |= R_GPT0_GTIOR_OAE_Msk; + } + + if (GPT_IO_PIN_GTIOCA != pin) + { + /* GTIOCB or both GTIOCA and GTIOCB. */ + gtior |= R_GPT0_GTIOR_OBE_Msk; + } + + p_instance_ctrl->p_reg->GTIOR = gtior; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable output for GTIOCA and/or GTIOCB. + * + * @retval FSP_SUCCESS Output is disabled. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_OutputDisable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + uint32_t gtior = p_instance_ctrl->p_reg->GTIOR; + if (GPT_IO_PIN_GTIOCB != pin) + { + /* GTIOCA or both GTIOCA and GTIOCB. */ + gtior &= ~R_GPT0_GTIOR_OAE_Msk; + } + + if (GPT_IO_PIN_GTIOCA != pin) + { + /* GTIOCB or both GTIOCA and GTIOCB. */ + gtior &= ~R_GPT0_GTIOR_OBE_Msk; + } + + p_instance_ctrl->p_reg->GTIOR = gtior; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set A/D converter start request compare match value. + * + * @retval FSP_SUCCESS Counter value updated. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_AdcTriggerSet (timer_ctrl_t * const p_ctrl, + gpt_adc_compare_match_t which_compare_match, + uint32_t compare_match_value) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + /* Set A/D converter start request compare match value. */ + volatile uint32_t * p_gtadtr = &p_instance_ctrl->p_reg->GTADTRA; + p_gtadtr[which_compare_match] = compare_match_value; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the Output Delay setting for the PWM output pin. + * + * @retval FSP_SUCCESS The output delay was set. + * @retval FSP_ERR_ASSERTION An input parameter was invalid. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_CHANNEL The channel does not support this feature. + * @retval FSP_ERR_NOT_INITIALIZED The PWM Output Delay Circuit has not been initialized. + * @retval FSP_ERR_INVALID_STATE The PWM Output Delay setting cannot be updated in the current state. + * @retval FSP_ERR_UNSUPPORTED This feature is not supported on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_GPT_PwmOutputDelaySet (timer_ctrl_t * const p_ctrl, + gpt_pwm_output_delay_edge_t edge, + gpt_pwm_output_delay_setting_t delay_setting, + uint32_t const pin) +{ +#if 0U != GPT_PRV_ODC_SUPPORTED && GPT_CFG_OUTPUT_SUPPORT_ENABLE + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; + + #if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(0U != (GPT_PRV_ODC_CHANNEL_MASK & p_instance_ctrl->channel_mask), FSP_ERR_INVALID_CHANNEL); + FSP_ERROR_RETURN(0U != (R_GPT_ODC->GTDLYCR1 & R_GPT_ODC_GTDLYCR1_DLLEN_Msk), FSP_ERR_NOT_INITIALIZED); + + if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + /* In Saw-wave mode, do not change the settings for the delay while the compare-match value is greater than or + * equal to GTPR - 2. */ + uint32_t gtpr = p_instance_ctrl->p_reg->GTPR; + uint32_t compare_match = p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC + pin]; + FSP_ERROR_RETURN(gtpr - 2 > compare_match, FSP_ERR_INVALID_STATE); + } + else + { + uint32_t compare_match; + if ((TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 == p_instance_ctrl->p_cfg->mode) || + (TIMER_MODE_ONE_SHOT_PULSE == p_instance_ctrl->p_cfg->mode)) + { + /* In TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3, the trough compare match value is set in + * GTCCRD, and GTCCRF. */ + compare_match = p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRD + pin]; + } + else + { + /* In TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM and TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM, the trough + * compare match value is set in GTCCRC, and GTCCRE. */ + compare_match = p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC + pin]; + } + + timer_direction_t count_direction = (timer_direction_t) p_instance_ctrl->p_reg->GTST_b.TUCF; + + /* In Triangle-wave mode, do not change the settings for the delay while the counter if going down and the + * compare-match value is less than or equal to 2. */ + FSP_ERROR_RETURN(TIMER_DIRECTION_DOWN != count_direction || 2 < compare_match, FSP_ERR_INVALID_STATE); + } + #endif + + FSP_CRITICAL_SECTION_DEFINE; + + if (GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS == delay_setting) + { + /* Enter a critical section in order to ensure that multiple GPT channels don't access the common + * register simultaneously. */ + FSP_CRITICAL_SECTION_ENTER; + + #if GPT_CFG_WRITE_PROTECT_ENABLE + + /* GTDLYCR2 is protected by R_GPT::GTWP. */ + uint32_t wp = R_GPT0->GTWP; + R_GPT0->GTWP = GPT_PRV_GTWP_RESET_VALUE; + R_GPT0->GTWP; + #endif + + /* Enable the Delay Generation Circuit bypass. */ + R_GPT_ODC->GTDLYCR2 &= (uint16_t) (~p_instance_ctrl->channel_mask & UINT16_MAX); + + #if GPT_CFG_WRITE_PROTECT_ENABLE + + /* Restore the previous value of GTWP. */ + R_GPT0->GTWP = wp | GPT_PRV_GTWP_RESET_VALUE; + #endif + + FSP_CRITICAL_SECTION_EXIT; + } + else + { + /* Calculate the offset for the register than needs to be set. */ + uint32_t channel_offset = sizeof(uint32_t) * p_instance_ctrl->p_cfg->channel; + uint32_t pin_offset = + (uint32_t) ((uint32_t) &R_GPT_ODC->GTDLYR[0].B - (uint32_t) &R_GPT_ODC->GTDLYR[0].A) * pin; + uint32_t edge_offset = + (uint32_t) ((uint32_t) &R_GPT_ODC->GTDLYF[0].A - (uint32_t) &R_GPT_ODC->GTDLYR[0].A) * edge; + uint16_t * p_gtdlyfnx = + (uint16_t *) ((uint32_t) &R_GPT_ODC->GTDLYR[0].A + channel_offset + pin_offset + edge_offset); + + #if BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED + + /* Delay count is out of 32, per the API. Convert provided 32-count resolution into 128-count register + * setting. */ + delay_setting *= 4U; + #endif + + /* Unprotect the delay setting register. */ + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + /* Write the delay setting to the register. */ + *p_gtdlyfnx = (uint16_t) delay_setting; + + /* Restore the previous value of GTWP. */ + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + /* Check if the channel has already been enabled. */ + if (0U == (R_GPT_ODC->GTDLYCR2 & p_instance_ctrl->channel_mask)) + { + /* Enter a critical section in order to ensure that multiple GPT channels don't access the common + * register simultaneously. */ + FSP_CRITICAL_SECTION_ENTER; + + #if GPT_CFG_WRITE_PROTECT_ENABLE + + /* GTDLYCR2 is protected by R_GPT::GTWP. */ + wp = R_GPT0->GTWP; + R_GPT0->GTWP = GPT_PRV_GTWP_RESET_VALUE; + R_GPT0->GTWP; + #endif + + /* Disable the Delay Generation Circuit bypass. */ + R_GPT_ODC->GTDLYCR2 |= (uint16_t) p_instance_ctrl->channel_mask; + + #if GPT_CFG_WRITE_PROTECT_ENABLE + + /* Restore the previous value of GTWP. */ + R_GPT0->GTWP = wp | GPT_PRV_GTWP_RESET_VALUE; + #endif + + FSP_CRITICAL_SECTION_EXIT; + } + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(edge); + FSP_PARAMETER_NOT_USED(delay_setting); + FSP_PARAMETER_NOT_USED(pin); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_GPT_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + gpt_instance_ctrl_t * p_ctrl = (gpt_instance_ctrl_t *) p_api_ctrl; + +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(GPT_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if GPT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(timer_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_Close (timer_ctrl_t * const p_ctrl) +{ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disable interrupts. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + r_gpt_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq); + r_gpt_disable_irq(p_extend->capture_a_irq); + r_gpt_disable_irq(p_extend->capture_b_irq); + r_gpt_disable_irq(p_extend->compare_match_c_irq); + r_gpt_disable_irq(p_extend->compare_match_d_irq); + r_gpt_disable_irq(p_extend->compare_match_e_irq); + r_gpt_disable_irq(p_extend->compare_match_f_irq); +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg; + if (NULL != p_pwm_cfg) + { + r_gpt_disable_irq(p_pwm_cfg->trough_irq); + } +#endif + + /* Clear open flag. */ + p_instance_ctrl->open = 0U; + + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + /* Stop counter. */ + p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask; + + /* Disable output. */ + p_instance_ctrl->p_reg->GTIOR = 0U; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + return err; +} + +/*******************************************************************************************************************//** + * Initialize the PWM Delay Generation Circuit (PDG). + * This function must be called before calling @ref R_GPT_PwmOutputDelaySet. + * + * @note This function will delay for 20 microseconds. + * + * @retval FSP_SUCCESS Initialization sequence completed successfully. + * @retval FSP_ERR_INVALID_STATE The source clock frequnecy is out of the required range for the PDG. + * @retval FSP_ERR_UNSUPPORTED This feature is not supported. + **********************************************************************************************************************/ +fsp_err_t R_GPT_PwmOutputDelayInitialize () +{ +#if (BSP_FEATURE_GPT_GPTEH_SUPPORTED && GPT_CFG_OUTPUT_SUPPORT_ENABLE) + #if ((BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN > 0) || GPT_CFG_PARAM_CHECKING_ENABLE) + #if (BSP_PERIPHERAL_GPT_GTCLK_PRESENT && (GPT_CFG_GPTCLK_BYPASS == 0)) + + /* Get the GPTCK Divider. */ + const uint8_t divider = (uint8_t) R_FSP_ClockDividerGet(R_SYSTEM->GPTCKDIVCR_b.GPTCKDIV); + + /* Calculate the GPTCK Frequency. */ + uint32_t gpt_frequency = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) R_SYSTEM->GPTCKCR_b.GPTCKSEL) / divider; + #else + + /* Calculate the PCLKD Frequency. */ + uint32_t gpt_frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD); + #endif + #endif + + #if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(BSP_FEATURE_GPT_ODC_FREQ_MAX >= gpt_frequency, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(BSP_FEATURE_GPT_ODC_FREQ_MIN <= gpt_frequency, FSP_ERR_INVALID_STATE); + #endif + + uint32_t gtdlycr1 = R_GPT_ODC_GTDLYCR1_DLYRST_Msk; + + #if BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN > 0 + gtdlycr1 |= BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency); + #endif + + #if BSP_PERIPHERAL_GPT_GTCLK_PRESENT && GPT_CFG_GPTCLK_BYPASS + + /* Bypass the GPTCLK. GPT instances will use PCLKD as the GPT Core clock. */ + R_GPT_GTCLK->GTCLKCR = 1U; + #endif + + /* Cancel the module-stop state for the PDG. */ + R_BSP_MODULE_START(FSP_IP_GPT_PDG, 0); + + #if GPT_CFG_WRITE_PROTECT_ENABLE + + /* Disable write protection for GPT registers if they are protected. */ + R_GPT0->GTWP = GPT_PRV_GTWP_RESET_VALUE; + R_GPT0->GTWP; + #endif + + /* Reset the PWM Delay Generation Circuit. */ + R_GPT_ODC->GTDLYCR1 = (uint16_t) gtdlycr1; + R_GPT_ODC->GTDLYCR2 = 0; + + /* Enable the DLL. */ + R_GPT_ODC->GTDLYCR1 = (uint16_t) (gtdlycr1 | R_GPT_ODC_GTDLYCR1_DLLEN_Msk); + + /* Wait for the DLL to be enabled. */ + R_BSP_SoftwareDelay(20, BSP_DELAY_UNITS_MICROSECONDS); + + /* Release the PWM Delay Generation Circuit from reset. */ + R_GPT_ODC->GTDLYCR1 &= (uint16_t) ~R_GPT_ODC_GTDLYCR1_DLYRST_Msk; + + #if GPT_CFG_WRITE_PROTECT_ENABLE + + /* Re-enable write protection for GPT registers. */ + R_GPT0->GTWP = GPT_PRV_GTWP_WRITE_PROTECT; + #endif + + return FSP_SUCCESS; +#else + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/** @} (end addtogroup GPT) */ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enables write protection. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] write_protect_setting The value of GTWP prior to being cleared. + **********************************************************************************************************************/ +static inline void r_gpt_write_protect_enable (gpt_instance_ctrl_t * const p_instance_ctrl, + uint32_t write_protect_setting) +{ +#if GPT_CFG_WRITE_PROTECT_ENABLE + p_instance_ctrl->p_reg->GTWP = write_protect_setting; +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(write_protect_setting); +#endif +} + +/*******************************************************************************************************************//** + * Disables write protection. + * + * @param[in] p_instance_ctrl Instance control block. + **********************************************************************************************************************/ +static inline uint32_t r_gpt_write_protect_disable (gpt_instance_ctrl_t * const p_instance_ctrl) +{ +#if GPT_CFG_WRITE_PROTECT_ENABLE + uint32_t write_protect_setting = p_instance_ctrl->p_reg->GTWP; + p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_RESET_VALUE; + + return write_protect_setting; +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + + return 0U; +#endif +} + +/*******************************************************************************************************************//** + * Initializes control structure based on configuration. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void gpt_common_open (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + /* Initialize control structure. */ + p_instance_ctrl->p_cfg = p_cfg; + + /* If callback is not null or timer mode is one shot, make sure the IRQ is enabled and store callback in the + * control block. + * @note The GPT hardware does not support one-shot mode natively. To support one-shot mode, the timer will be + * stopped and cleared using software in the ISR. *//* Determine if this is a 32-bit or a 16-bit timer. */ + p_instance_ctrl->variant = TIMER_VARIANT_16_BIT; + if (0U != (p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_32BIT_CHANNEL_MASK)) + { + p_instance_ctrl->variant = TIMER_VARIANT_32_BIT; + } + + /* Save register base address. */ + uint32_t base_address = (uint32_t) R_GPT0 + (p_cfg->channel * ((uint32_t) R_GPT1 - (uint32_t) R_GPT0)); + p_instance_ctrl->p_reg = (R_GPT0_Type *) base_address; + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; +} + +/*******************************************************************************************************************//** + * Performs hardware initialization of the GPT. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + /* Save pointer to extended configuration structure. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend; + +#if BSP_PERIPHERAL_GPT_GTCLK_PRESENT && GPT_CFG_GPTCLK_BYPASS + + /* Bypass the GPTCLK. GPT instances will use PCLKD as the GPT Core clock. */ + R_GPT_GTCLK->GTCLKCR = 1U; +#endif + + /* Power on GPT before setting any hardware registers. Make sure the counter is stopped before setting mode + * register, PCLK divisor register, and counter register. */ + R_BSP_MODULE_START(FSP_IP_GPT, p_cfg->channel); + +#if (GPT_CFG_OUTPUT_SUPPORT_ENABLE && BSP_FEATURE_GPT_GPTEH_SUPPORTED) + if (0U != (BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK & p_instance_ctrl->channel_mask)) + { + /* Enter a critical section in order to ensure that multiple GPT channels don't access the common + * register simultaneously. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + #if GPT_CFG_WRITE_PROTECT_ENABLE + + /* Disable write protection for GPT registers if they are protected. */ + uint32_t wp = R_GPT0->GTWP; + R_GPT0->GTWP = GPT_PRV_GTWP_RESET_VALUE; + R_GPT0->GTWP; + #endif + + /* Enable the Delay Generation Circuit bypass. */ + R_GPT_ODC->GTDLYCR2 &= (uint16_t) (~p_instance_ctrl->channel_mask & UINT16_MAX); + + #if GPT_CFG_WRITE_PROTECT_ENABLE + R_GPT0->GTWP = wp | GPT_PRV_GTWP_RESET_VALUE; + #endif + + FSP_CRITICAL_SECTION_EXIT; + } +#endif + + /* Initialize all registers that may affect operation of this driver to reset values. Skip these since they + * affect all channels, and are initialized in GTCR and GTCNT: GTSTR, GTSTP, GTCLR. GTCR is set immediately after + * clearing the module stop bit to ensure the timer is stopped before proceeding with configuration. */ + p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_RESET_VALUE; + p_instance_ctrl->p_reg->GTCR = 0U; + p_instance_ctrl->p_reg->GTST = 0U; + p_instance_ctrl->p_reg->GTCNT = 0U; + + /* GTPR, GTCCRn, GTIOR, GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTPBR, and GTUDDTYC are set by this driver. */ + + /* Initialization sets all register required for up counting as described in hardware manual (Figure + * "Example setting for a periodic count operation in up-counting by the count clock" + * in the GPT section of the relevant hardware manual.) */ + + /* Dividers for GPT are half the enum value. */ + uint32_t gtcr_tpcs = p_cfg->source_div >> BSP_FEATURE_GPT_TPCS_SHIFT; + uint32_t gtcr = gtcr_tpcs << R_GPT0_GTCR_TPCS_Pos; + + /* Store period register setting. The actual period and is one cycle longer than the register value for saw waves + * and twice the register value for triangle waves. Reference section "General PWM Timer Cycle Setting Register + * (GTPR)". The setting passed to the configuration is expected to be half the desired period for triangle waves. */ + uint32_t gtpr = p_cfg->period_counts - 1U; + + /* Set GTCR.MD = 0x001 for TIMER_MODE_ONE_SHOT_PULSE mode. */ + if (TIMER_MODE_ONE_SHOT_PULSE == p_cfg->mode) + { + gtcr |= (1U << R_GPT0_GTCR_MD_Pos); + } + +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Saw-wave PWM mode is set in GTCR.MD for all modes except TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM and + * TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM. */ + if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + gtcr |= ((uint32_t) p_cfg->mode << R_GPT0_GTCR_MD_Pos); + gtpr = p_cfg->period_counts; + } +#endif + + /* Counter must be stopped to update TPCS. See "General PWM Timer Control Register (GTCR)" description + * in the GPT section of the relevant hardware manual. */ + p_instance_ctrl->p_reg->GTCR = gtcr; + + gpt_hardware_events_disable(p_instance_ctrl); + + /* Configure the up/down count sources. These are not affected by enable/disable. */ + p_instance_ctrl->p_reg->GTUPSR = p_extend->count_up_source; + p_instance_ctrl->p_reg->GTDNSR = p_extend->count_down_source; + + /* Set period. The actual period is one cycle longer than the register value. Reference section "General PWM Timer + * Cycle Setting Register (GTPR)". */ + p_instance_ctrl->p_reg->GTPBR = gtpr; + p_instance_ctrl->p_reg->GTPR = gtpr; + + uint32_t gtuddtyc = 0U; + uint32_t gtior = p_extend->gtior_setting.gtior; + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* For one shot mode, the compare match buffer register must be loaded with a value that exceeds the timer + * cycle end value so that second compare match event would never occur and hence there will be only a + * single pulse. Writing to the upper bits is ignored for 16-bit timers. */ + gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0}; + + if (TIMER_MODE_PERIODIC == p_cfg->mode) + { + /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. See + * "Example setting for saw-wave PWM mode" in the GPT section of the relevant hardware manual. To get a duty + * cycle as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */ + uint32_t duty_cycle_50_percent = (p_cfg->period_counts >> 1) - 1U; + duty_regs.gtccr_buffer = duty_cycle_50_percent; + } + + if (p_cfg->mode >= TIMER_MODE_PWM) + { + gpt_calculate_duty_cycle(p_instance_ctrl, p_cfg->duty_cycle_counts, &duty_regs, GPT_IO_PIN_GTIOCA); + } + + /* Set the compare match and compare match buffer registers based on previously calculated values. */ + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_regs.gtccr_buffer; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRE] = duty_regs.gtccr_buffer; + + if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + /* Set the double buffer registers for triangle modes. */ + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRD] = duty_regs.gtccr_buffer; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRF] = duty_regs.gtccr_buffer; + } + + /* If the requested duty cycle is 0% or 100%, set this in the registers. */ + gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OADTY_Pos; + gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OBDTY_Pos; + + /* Check if custom GTIOR settings are provided. */ + if (0 == p_extend->gtior_setting.gtior) + { + /* If custom GTIOR settings are not provided, calculate GTIOR. */ + if (p_extend->gtioca.output_enabled) + { + uint32_t gtioca_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtioca.stop_level); + gtior |= gtioca_gtior << R_GPT0_GTIOR_GTIOA_Pos; + } + + if (p_extend->gtiocb.output_enabled) + { + uint32_t gtiocb_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtiocb.stop_level); + gtior |= gtiocb_gtior << R_GPT0_GTIOR_GTIOB_Pos; + } + } +#endif + + r_gpt_init_compare_match_channel(p_instance_ctrl); + +#if GPT_PRV_GPTE_OR_GPTEH_SUPPORTED + if ((1U << p_cfg->channel) & GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK) + { + /* This register is available on GPTE and GPTEH only. It must be cleared before setting. When modifying the + * IVTT[2:0] bits, first set the IVTC[1:0] bits to 00b. See "General PWM Timer Interrupt + * and A/D Converter Start Request Skipping Setting Register (GTITC)" description in the GPT section of the + * relevant hardware manual. */ + p_instance_ctrl->p_reg->GTITC = 0U; + } +#endif + +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg; + if (NULL != p_pwm_cfg) + { + uint32_t gtintad = ((uint32_t) p_pwm_cfg->output_disable << R_GPT0_GTINTAD_GRPDTE_Pos) | + ((uint32_t) p_pwm_cfg->poeg_link << R_GPT0_GTINTAD_GRP_Pos); + + /* Configure PWM Dead-time. + * GTDVU is available on most timers, while GTDVD is only available on a subset of timers (GPTE/GPTEH) */ + #if BSP_FEATURE_GPT_GTDVU_SUPPORTED + if ((1U << p_cfg->channel) & (BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK | GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK)) + { + /* Enable Dead-time nagative-phase waveform + * Set GTDTCR.TDE only if one of the dead time values is non-zero. */ + p_instance_ctrl->p_reg->GTDTCR = + ((p_pwm_cfg->dead_time_count_up > 0) || (p_pwm_cfg->dead_time_count_down > 0)); + + /* Dead time value register GTDVU */ + p_instance_ctrl->p_reg->GTDVU = p_pwm_cfg->dead_time_count_up; + } + #endif + + #if GPT_PRV_ADC_CONVERSION_START_SUPPORTED + if ((1U << p_cfg->channel) & GPT_PRV_ADC_CONVERSION_START_CHANNEL_MASK) + { + #if (GPT_PRV_GPTE_OR_GPTEH_SUPPORTED) + + /* Dead time value register GTDVD */ + p_instance_ctrl->p_reg->GTDVD = p_pwm_cfg->dead_time_count_down; + + /* GTITC is always present for GPTE and GPTEH timers */ + p_instance_ctrl->p_reg->GTITC = ((uint32_t) p_pwm_cfg->interrupt_skip_source << R_GPT0_GTITC_IVTC_Pos) | + ((uint32_t) p_pwm_cfg->interrupt_skip_count << R_GPT0_GTITC_IVTT_Pos) | + ((uint32_t) p_pwm_cfg->interrupt_skip_adc << R_GPT0_GTITC_ADTAL_Pos); + #endif + + /* Configure AD Compare match behavior */ + gtintad |= ((uint32_t) p_pwm_cfg->adc_trigger << R_GPT0_GTINTAD_ADTRAUEN_Pos); + p_instance_ctrl->p_reg->GTADTRA = p_pwm_cfg->adc_a_compare_match; + p_instance_ctrl->p_reg->GTADTRB = p_pwm_cfg->adc_b_compare_match; + } + #endif + + p_instance_ctrl->p_reg->GTINTAD = gtintad; + + /* Check if custom GTIOR (Input/Output) settings are provided. */ + if (0 == p_extend->gtior_setting.gtior) + { + /* If custom GTIOR settings are not provided, set gtioca_disable_settings and gtiocb_disable_settings. */ + gtior |= (uint32_t) (p_pwm_cfg->gtioca_disable_setting << R_GPT0_GTIOR_OADF_Pos); + gtior |= (uint32_t) (p_pwm_cfg->gtiocb_disable_setting << R_GPT0_GTIOR_OBDF_Pos); + } + } + else +#endif + + { + /* GTADTR* registers are unused if GTINTAD is cleared. */ + p_instance_ctrl->p_reg->GTINTAD = 0U; + + /* GTDVU, GTDVD, GTDBU, GTDBD, and GTSOTR are not used if GTDTCR is cleared. */ + p_instance_ctrl->p_reg->GTDTCR = 0U; + } + + /* Check if custom GTIOR settings are provided. */ + if (0 == p_extend->gtior_setting.gtior) + { + /* + * If custom GTIOR settings are not provided, configure the noise filter for + * the GTIOC pins. + */ + gtior |= (uint32_t) (p_extend->capture_filter_gtioca << R_GPT0_GTIOR_NFAEN_Pos); + gtior |= (uint32_t) (p_extend->capture_filter_gtiocb << R_GPT0_GTIOR_NFBEN_Pos); + } + + uint32_t gtber = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER; + + if (p_extend->compare_match_status) + { + /* If compare match is being used, not enable buffer operation for GTCCRA and GTCCRB. */ + gtber = GPT_PRV_GTBER_DISABLE_BUFFER_OP_GTCCRA_GTCCRB; + } + + p_instance_ctrl->p_reg->GTBER = gtber; + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (TIMER_MODE_ONE_SHOT == p_cfg->mode) + { + /* In one shot mode, the output pin toggles when counting starts, then again when the period expires. + * The buffer is enabled to set the compare match to UINT32_MAX after the one shot pulse is output + * so that the pin level will not change if the period expires again before the timer is stopped in + * the interrupt.*/ + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0U; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0U; + } +#endif + + /* Set the I/O control register. */ + p_instance_ctrl->p_reg->GTIOR = gtior; + +#if BSP_FEATURE_GPT_POLARITY_CONTROL_SUPPORTED + + /* Apply polarity inversion control if supported. Needs to happen after GTIOR is set. + * Don't reuse the previous gtcr variable in case it is was updated elsewhere. */ + p_instance_ctrl->p_reg->GTCR |= ((uint32_t) p_extend->gtioca_polarity << R_GPT0_GTCR_AINV_Pos) | + ((uint32_t) p_extend->gtiocb_polarity << R_GPT0_GTCR_BINV_Pos); +#endif + + /* Configure duty cycle and force timer to count up. GTUDDTYC must be set, then cleared to force the count + * direction to be reflected when counting starts. See "General PWM Timer Count Direction + * and Duty Setting Register (GTUDDTYC)" description in the GPT section of the relevant hardware manual. */ + p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 3U; + p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 1U; + + /* Reset counter to 0. */ + p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; + + r_gpt_write_protect_enable(p_instance_ctrl, GPT_PRV_GTWP_WRITE_PROTECT); + + /* Enable CPU interrupts if callback is not null. Also enable interrupts for one shot mode. + * @note The GPT hardware does not support one-shot mode natively. To support one-shot mode, the timer will be + * stopped and cleared using software in the ISR. */ + r_gpt_enable_irq(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + r_gpt_enable_irq(p_extend->capture_a_irq, p_extend->capture_a_ipl, p_instance_ctrl); + r_gpt_enable_irq(p_extend->capture_b_irq, p_extend->capture_b_ipl, p_instance_ctrl); + r_gpt_enable_irq(p_extend->compare_match_c_irq, p_extend->compare_match_c_ipl, p_instance_ctrl); + r_gpt_enable_irq(p_extend->compare_match_d_irq, p_extend->compare_match_d_ipl, p_instance_ctrl); + r_gpt_enable_irq(p_extend->compare_match_e_irq, p_extend->compare_match_e_ipl, p_instance_ctrl); + r_gpt_enable_irq(p_extend->compare_match_f_irq, p_extend->compare_match_f_ipl, p_instance_ctrl); +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (NULL != p_pwm_cfg) + { + r_gpt_enable_irq(p_pwm_cfg->trough_irq, p_pwm_cfg->trough_ipl, p_instance_ctrl); + } +#endif +} + +/*******************************************************************************************************************//** + * Disables hardware events that would cause the timer to start, stop, clear, or capture. + * + * @param[in] p_instance_ctrl Instance control structure + **********************************************************************************************************************/ +static void gpt_hardware_events_disable (gpt_instance_ctrl_t * p_instance_ctrl) +{ + /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */ + p_instance_ctrl->p_reg->GTSSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + p_instance_ctrl->p_reg->GTPSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + p_instance_ctrl->p_reg->GTCSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE; + p_instance_ctrl->p_reg->GTICASR = GPT_SOURCE_NONE; + p_instance_ctrl->p_reg->GTICBSR = GPT_SOURCE_NONE; +} + +/*******************************************************************************************************************//** + * Disables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + **********************************************************************************************************************/ +__STATIC_INLINE void r_gpt_disable_irq (IRQn_Type irq) +{ + /* Disable interrupts. */ + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + R_FSP_IsrContextSet(irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Configures and enables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + **********************************************************************************************************************/ +__STATIC_INLINE void r_gpt_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + if (irq >= 0) + { + R_BSP_IrqCfgEnable(irq, priority, p_context); + } +} + +/*******************************************************************************************************************//** + * Clear a pending interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + **********************************************************************************************************************/ +__STATIC_INLINE void r_gpt_clear_pending_irq (IRQn_Type irq) +{ + if (irq >= 0) + { + R_BSP_IrqClearPending(irq); + } +} + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Calculates duty cycle register values. GTPR must be set before entering this function. + * + * @param[in] p_instance_ctrl Instance control structure + * @param[in] duty_cycle_counts Duty cycle to set + * @param[out] p_duty_reg Duty cycle register values + **********************************************************************************************************************/ +static void gpt_calculate_duty_cycle (gpt_instance_ctrl_t * const p_instance_ctrl, + uint32_t const duty_cycle_counts, + gpt_prv_duty_registers_t * p_duty_reg, + uint32_t pin) +{ + /* Determine the current period. The actual period is one cycle longer than the register value for saw waves and + * twice the register value for triangle waves. Reference section "General PWM Timer Cycle Setting Register + * (GTPBR)". The setting passed to the configuration is expected to be half the desired duty cycle for triangle + * waves. */ + uint32_t current_period = p_instance_ctrl->p_reg->GTPBR; + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (p_instance_ctrl->p_cfg->mode < TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + #endif + { + current_period++; + } + + bool duty_zero = (0U == duty_cycle_counts); + bool duty_high = (duty_cycle_counts >= current_period); + + if (duty_zero || duty_high) + { + uint32_t gtior; + + if (!(GPT_IO_PIN_GTIOCB & pin)) + { + gtior = p_instance_ctrl->p_reg->GTIOR_b.GTIOA; + } + else + { + gtior = p_instance_ctrl->p_reg->GTIOR_b.GTIOB; + } + + bool first_level_low; + + if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + /* In triangle PWM modes use the initial pin level to determine 0%/100% setting. */ + first_level_low = !(gtior & 0x10); + } + else + { + /* In normal PWM mode use the cycle end setting to determine 0%/100% setting */ + first_level_low = (gtior & 0xC) == 0x4; + } + + if ((duty_zero && !first_level_low) || (duty_high && first_level_low)) + { + p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_0_PERCENT; + } + else + { + p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_100_PERCENT; + } + } + else + { + uint32_t temp_duty_cycle = duty_cycle_counts; + + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + p_duty_reg->gtccr_buffer = temp_duty_cycle; + } + else + #endif + { + /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. See + * figure "Example setting for saw-wave PWM mode" in the GPT section of the relevant hardware manual. */ + temp_duty_cycle--; + p_duty_reg->gtccr_buffer = temp_duty_cycle; + } + } +} + +#endif + +/*******************************************************************************************************************//** + * Calculates clock frequency of GPT counter. Divides GPT clock by GPT clock divisor. + * + * @param[in] p_instance_ctrl Instance control block + * + * @return Clock frequency of the GPT counter. + **********************************************************************************************************************/ +static uint32_t gpt_clock_frequency_get (gpt_instance_ctrl_t * const p_instance_ctrl) +{ + timer_source_div_t prescaler_divisor = + (timer_source_div_t) (p_instance_ctrl->p_reg->GTCR_b.TPCS << BSP_FEATURE_GPT_TPCS_SHIFT); + +#if BSP_PERIPHERAL_GPT_GTCLK_PRESENT && !GPT_CFG_GPTCLK_BYPASS + + /* Calculate the GPTCK Divider. */ + const uint8_t divisor = (uint8_t) R_FSP_ClockDividerGet(R_SYSTEM->GPTCKDIVCR_b.GPTCKDIV); + + /* Calculate the GPTCK Frequency. */ + uint32_t source_freq_hz = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) R_SYSTEM->GPTCKCR_b.GPTCKSEL) / divisor; +#else + + /* Look up PCLKD frequency. */ + uint32_t source_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD); +#endif + + return source_freq_hz >> prescaler_divisor; +} + +#if GPT_CFG_OUTPUT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Calculates GTIOR settings for given mode and stop level. + * + * @param[in] p_instance_ctrl Instance control block + * @param[in] p_cfg Timer configuration + * @param[in] level Output level after timer stops + **********************************************************************************************************************/ +static uint32_t gpt_gtior_calculate (timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level) +{ + /* The stop level is used as both the initial level and the stop level. */ + uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t) stop_level << R_GPT0_GTIOR_OADFLT_Pos) | + ((uint32_t) stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT); + + uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END; + + if (TIMER_MODE_PWM == p_cfg->mode) + { + /* Use default: GTIOn is high at cycle end, then low at compare match. */ + } + + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + else if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + { + gtion = GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH; + } + #endif + else if (TIMER_MODE_ONE_SHOT_PULSE == p_cfg->mode) + { + gtion = GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH; + } + else + { + /* In one-shot mode, the output pin goes high after the first compare match (one cycle after the timer starts + * counting). */ + if (GPT_PIN_LEVEL_LOW == stop_level) + { + gtion = GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END; + } + } + + gtior |= gtion; + + return gtior; +} + +#endif + +/*******************************************************************************************************************//** + * Set compare match value from configure instance into corresponding compare match channel. + **********************************************************************************************************************/ +static void r_gpt_init_compare_match_channel (gpt_instance_ctrl_t * p_instance_ctrl) +{ + /* Save pointer to extended configuration structure. */ + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + for (uint32_t channel = 0U; channel <= TIMER_COMPARE_MATCH_F; channel++) + { + /* Set commpare match value for GTCCRk registers. */ + if (p_extend->compare_match_status & (1U << channel)) + { + /* The actual period is one cycle longer than the register value for saw waves. Reference section "General + * PWM Timer Cycle Setting Register (GTPR)" */ + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCR(channel)] = p_extend->compare_match_value[channel] - 1U; + } + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to GPT instance control block + * @param[in] event Event code + * @param[in] capture Event capture counts (if applicable) + **********************************************************************************************************************/ +static void r_gpt_call_callback (gpt_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture) +{ + timer_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + timer_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->capture = capture; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the + * callback. */ + gpt_prv_ns_callback p_callback = (gpt_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the + * callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Common processing for input capture/compare match interrupt. + * + * @param[in] ccmp_event Which input capture/compare match event occurred. + **********************************************************************************************************************/ +static void r_gpt_ccmp_common_isr (timer_event_t ccmp_event) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + uint32_t counter = 0U; + timer_event_t actual_event = ccmp_event; + + /* Identify whether an input capture event have occurred. */ + if (((TIMER_EVENT_COMPARE_A == ccmp_event) || (TIMER_EVENT_COMPARE_B == ccmp_event)) && + !(p_extend->compare_match_status & GPT_PRV_GTCCR_AB_MASK)) + { + /* Get the captured value and actual event. */ + counter = p_instance_ctrl->p_reg->GTCCR[ccmp_event - TIMER_EVENT_COMPARE_A]; + actual_event = (timer_event_t) (TIMER_EVENT_CAPTURE_A + (ccmp_event - TIMER_EVENT_COMPARE_A)); + + /* If we capture a one-shot pulse, then disable future captures. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + /* Disable captures. */ + gpt_hardware_events_disable(p_instance_ctrl); + + /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */ + R_BSP_IrqClearPending(irq); + } + } + + if (NULL != p_instance_ctrl->p_callback) + { + r_gpt_call_callback(p_instance_ctrl, actual_event, counter); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_counter_overflow_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* If one-shot mode is selected, stop the timer since period has expired. */ + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl); + + p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask; + + /* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */ + p_instance_ctrl->p_reg->GTCNT = 0; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0; + p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0; + + r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE); + + /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */ + R_BSP_IrqClearPending(irq); + + /* Compare match pending interrupts are also cleared here. */ + if (p_extend->compare_match_status & (1U << TIMER_COMPARE_MATCH_A)) + { + r_gpt_clear_pending_irq(p_extend->capture_a_irq); + } + + if (p_extend->compare_match_status & (1U << TIMER_COMPARE_MATCH_B)) + { + r_gpt_clear_pending_irq(p_extend->capture_b_irq); + } + + r_gpt_clear_pending_irq(p_extend->compare_match_c_irq); + r_gpt_clear_pending_irq(p_extend->compare_match_d_irq); + r_gpt_clear_pending_irq(p_extend->compare_match_e_irq); + r_gpt_clear_pending_irq(p_extend->compare_match_f_irq); + } + + if (NULL != p_instance_ctrl->p_callback) + { + r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_CYCLE_END, 0); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Only supported for asymmetric triangle-wave PWM. Notifies application of trough event. + **********************************************************************************************************************/ +void gpt_counter_underflow_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Call user callback. */ + r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_TROUGH, 0); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +/*******************************************************************************************************************//** + * Interrupt triggered by a capture/compare match A source. + * + * In case Input Capture A interrupt: Clears interrupt, disables captures if one-shot mode, and calls callback if one + * was provided in the open function. + * In case Compare Match A interrupt: Just call callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_capture_compare_a_isr (void) +{ + r_gpt_ccmp_common_isr(TIMER_EVENT_COMPARE_A); +} + +/*******************************************************************************************************************//** + * Interrupt triggered by a capture/compare match B source. + * + * In case Input Capture B interrupt: Clears interrupt, disables captures if one-shot mode, and calls callback if one + * was provided in the open function. + * In case Compare Match B interrupt: Just call callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_capture_compare_b_isr (void) +{ + r_gpt_ccmp_common_isr(TIMER_EVENT_COMPARE_B); +} + +/*******************************************************************************************************************//** + * Interrupt triggered by a compare match C source. + * + * Call callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_compare_match_c_isr (void) +{ + r_gpt_ccmp_common_isr(TIMER_EVENT_COMPARE_C); +} + +/*******************************************************************************************************************//** + * Interrupt triggered by a compare match D source. + * + * Call callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_compare_match_d_isr (void) +{ + r_gpt_ccmp_common_isr(TIMER_EVENT_COMPARE_D); +} + +/*******************************************************************************************************************//** + * Interrupt triggered by a compare match E source. + * + * Call callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_compare_match_e_isr (void) +{ + r_gpt_ccmp_common_isr(TIMER_EVENT_COMPARE_E); +} + +/*******************************************************************************************************************//** + * Interrupt triggered by a compare match F source. + * + * Call callback if one was provided in the open function. + **********************************************************************************************************************/ +void gpt_compare_match_f_isr (void) +{ + r_gpt_ccmp_common_isr(TIMER_EVENT_COMPARE_F); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c new file mode 100644 index 0000000000..c16f9c62a5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c @@ -0,0 +1,394 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_gpt_three_phase.h" +#include "r_gpt_three_phase_cfg.h" + +#include "r_gpt.h" +#include "r_gpt_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "GPT3" in ASCII, used to determine if channel is open. */ +#define GPT_THREE_PHASE_OPEN (0x47505433ULL) + +#define GPT_THREE_PHASE_PRV_GTWP_RESET_VALUE (0xA500U) +#define GPT_THREE_PHASE_PRV_GTWP_WRITE_PROTECT (0xA501U) + +#define GPT_THREE_PHASE_PRV_GTBER_SINGLE_BUFFER (0x50000U) +#define GPT_THREE_PHASE_PRV_GTBER_DOUBLE_BUFFER (0xA0000U) + +#define GPT_THREE_PHASE_PRV_GTWP_RESET_VALUE (0xA500U) +#define GPT_THREE_PHASE_PRV_GTWP_WRITE_PROTECT (0xA501U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +enum e_gpt_three_phase_prv_gtccr +{ + GPT_THREE_PHASE_PRV_GTCCRA = 0U, + GPT_THREE_PHASE_PRV_GTCCRB, + GPT_THREE_PHASE_PRV_GTCCRC, + GPT_THREE_PHASE_PRV_GTCCRE, + GPT_THREE_PHASE_PRV_GTCCRD, + GPT_THREE_PHASE_PRV_GTCCRF +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static inline void r_gpt_write_protect_enable_all(gpt_three_phase_instance_ctrl_t * const p_instance_ctrl); +static inline void r_gpt_write_protect_disable_all(gpt_three_phase_instance_ctrl_t * const p_instance_ctrl); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* Implementation of GPT_THREE_PHASE interface */ +const three_phase_api_t g_gpt_three_phase_on_gpt_three_phase = +{ + .open = R_GPT_THREE_PHASE_Open, + .stop = R_GPT_THREE_PHASE_Stop, + .start = R_GPT_THREE_PHASE_Start, + .reset = R_GPT_THREE_PHASE_Reset, + .dutyCycleSet = R_GPT_THREE_PHASE_DutyCycleSet, + .callbackSet = R_GPT_THREE_PHASE_CallbackSet, + .close = R_GPT_THREE_PHASE_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup GPT_THREE_PHASE + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the 3-phase timer module (and associated timers) and applies configurations. Implements + * @ref three_phase_api_t::open. + * + * Example: + * @snippet r_gpt_three_phase_example.c R_GPT_THREE_PHASE_Open + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_Open (three_phase_ctrl_t * const p_ctrl, three_phase_cfg_t const * const p_cfg) +{ + gpt_three_phase_instance_ctrl_t * p_instance_ctrl = (gpt_three_phase_instance_ctrl_t *) p_ctrl; +#if GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_THREE_PHASE_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + fsp_err_t err; + + /* Open all three GPT submodules */ + for (three_phase_channel_t ch = THREE_PHASE_CHANNEL_U; ch <= THREE_PHASE_CHANNEL_W; ch++) + { + err = R_GPT_Open(p_cfg->p_timer_instance[ch]->p_ctrl, p_cfg->p_timer_instance[ch]->p_cfg); +#if GPT_CFG_PARAM_CHECKING_ENABLE + if (err) + { + /* In case of an error on GPT open, close all opened instances and return the error */ + for (three_phase_channel_t close_ch = THREE_PHASE_CHANNEL_U; close_ch < ch; close_ch++) + { + R_GPT_Close(p_cfg->p_timer_instance[close_ch]->p_ctrl); + } + + return err; + } + +#else + FSP_PARAMETER_NOT_USED(err); +#endif + + /* Save a pointer to the GPT registers for this channel */ + p_instance_ctrl->p_reg[ch] = ((gpt_instance_ctrl_t *) (p_cfg->p_timer_instance[ch]->p_ctrl))->p_reg; + +#if GPT_CFG_WRITE_PROTECT_ENABLE + + /* Disable write protection on the current GPT channel */ + p_instance_ctrl->p_reg[ch]->GTWP = GPT_THREE_PHASE_PRV_GTWP_RESET_VALUE; +#endif + + /* Set the buffer mode */ + if (THREE_PHASE_BUFFER_MODE_DOUBLE == p_cfg->buffer_mode) + { + p_instance_ctrl->p_reg[ch]->GTBER |= GPT_THREE_PHASE_PRV_GTBER_DOUBLE_BUFFER; + } + +#if GPT_CFG_WRITE_PROTECT_ENABLE + + /* Re-enable write protection */ + p_instance_ctrl->p_reg[ch]->GTWP = GPT_THREE_PHASE_PRV_GTWP_WRITE_PROTECT; +#endif + } + + /* Get copy of GPT channel mask and buffer mode */ + p_instance_ctrl->channel_mask = p_cfg->channel_mask; + p_instance_ctrl->buffer_mode = p_cfg->buffer_mode; + + /* Save pointer to config struct */ + p_instance_ctrl->p_cfg = p_cfg; + + p_instance_ctrl->open = GPT_THREE_PHASE_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops all timers synchronously. Implements @ref three_phase_api_t::stop. + * + * @retval FSP_SUCCESS Timers successfully stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_Stop (three_phase_ctrl_t * const p_ctrl) +{ + gpt_three_phase_instance_ctrl_t * p_instance_ctrl = (gpt_three_phase_instance_ctrl_t *) p_ctrl; +#if GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_THREE_PHASE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Stop timer */ + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_U]->GTSTP = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts all timers synchronously. Implements @ref three_phase_api_t::start. + * + * Example: + * @snippet r_gpt_three_phase_example.c R_GPT_THREE_PHASE_Start + * + * @retval FSP_SUCCESS Timers successfully started. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_Start (three_phase_ctrl_t * const p_ctrl) +{ + gpt_three_phase_instance_ctrl_t * p_instance_ctrl = (gpt_three_phase_instance_ctrl_t *) p_ctrl; +#if GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_THREE_PHASE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Start timer */ + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_U]->GTSTR = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter values to 0. Implements @ref three_phase_api_t::reset. + * + * @retval FSP_SUCCESS Counters were reset successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_Reset (three_phase_ctrl_t * const p_ctrl) +{ + gpt_three_phase_instance_ctrl_t * p_instance_ctrl = (gpt_three_phase_instance_ctrl_t *) p_ctrl; +#if GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_THREE_PHASE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear timer counter. */ + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_U]->GTCLR = p_instance_ctrl->channel_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets duty cycle for all three timers. Implements @ref three_phase_api_t::dutyCycleSet. + * + * In symmetric PWM mode duty cycle values are reflected after the next trough. In asymmetric PWM mode values are + * reflected at the next trough OR crest, whichever comes first. + * + * When double-buffering is enabled the values in @ref three_phase_duty_cycle_t::duty_buffer are set to the + * double-buffer registers. When values are reflected the first time the single buffer values + * (@ref three_phase_duty_cycle_t::duty) are used. On the second reflection the duty_buffer values are used. + * In asymmetric PWM mode this enables both count-up and count-down PWM values to be set at trough (or crest) + * exclusively. + * + * @note It is recommended to call this function in a high-priority callback to ensure that it is not interrupted and + * that no GPT events occur during setting that would result in a duty cycle buffer load operation. + * + * Example: + * @snippet r_gpt_three_phase_example.c R_GPT_THREE_PHASE_DutyCycleSet + * + * @retval FSP_SUCCESS Duty cycle updated successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT One or more duty cycle count values was outside the range 0..(period - 1). + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_DutyCycleSet (three_phase_ctrl_t * const p_ctrl, + three_phase_duty_cycle_t * const p_duty_cycle) +{ + gpt_three_phase_instance_ctrl_t * p_instance_ctrl = (gpt_three_phase_instance_ctrl_t *) p_ctrl; +#if GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_duty_cycle); + FSP_ERROR_RETURN(GPT_THREE_PHASE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Check that duty cycle values are in-range (less than period) */ + for (three_phase_channel_t ch = THREE_PHASE_CHANNEL_U; ch <= THREE_PHASE_CHANNEL_W; ch++) + { + uint32_t gtpr = p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_U]->GTPR; + FSP_ERROR_RETURN((p_duty_cycle->duty[ch] < gtpr) && (p_duty_cycle->duty[ch] > 0), FSP_ERR_INVALID_ARGUMENT); + + /* In double-buffer mode also check double buffer */ + if (THREE_PHASE_BUFFER_MODE_DOUBLE == p_instance_ctrl->buffer_mode) + { + FSP_ERROR_RETURN((p_duty_cycle->duty_buffer[ch] < gtpr) && (p_duty_cycle->duty_buffer[ch] > 0), + FSP_ERR_INVALID_ARGUMENT); + } + } +#endif + + r_gpt_write_protect_disable_all(p_instance_ctrl); + + /* Set all duty cycle registers */ + for (three_phase_channel_t ch = THREE_PHASE_CHANNEL_U; ch <= THREE_PHASE_CHANNEL_W; ch++) + { + p_instance_ctrl->p_reg[ch]->GTCCR[GPT_THREE_PHASE_PRV_GTCCRC] = p_duty_cycle->duty[ch]; + p_instance_ctrl->p_reg[ch]->GTCCR[GPT_THREE_PHASE_PRV_GTCCRE] = p_duty_cycle->duty[ch]; + + /* Set double-buffer registers (if applicable) */ + if ((THREE_PHASE_BUFFER_MODE_DOUBLE == p_instance_ctrl->buffer_mode) || + (TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 == p_instance_ctrl->p_cfg->p_timer_instance[0]->p_cfg->mode)) + { + p_instance_ctrl->p_reg[ch]->GTCCR[GPT_THREE_PHASE_PRV_GTCCRD] = p_duty_cycle->duty_buffer[ch]; + p_instance_ctrl->p_reg[ch]->GTCCR[GPT_THREE_PHASE_PRV_GTCCRF] = p_duty_cycle->duty_buffer[ch]; + } + } + + r_gpt_write_protect_enable_all(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback for the GPT U-channel with the option to provide memory for the callback argument + * structure. + * Implements @ref three_phase_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_CallbackSet (three_phase_ctrl_t * const p_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + gpt_three_phase_instance_ctrl_t * p_instance_ctrl = (gpt_three_phase_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_callback); + FSP_ERROR_RETURN(GPT_THREE_PHASE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + err = R_GPT_CallbackSet(p_instance_ctrl->p_cfg->p_timer_instance[p_instance_ctrl->p_cfg->callback_ch]->p_ctrl, + p_callback, + p_context, + p_callback_memory); + + return err; +} + +/*******************************************************************************************************************//** + * Stops counters, disables output pins, and clears internal driver data. Implements @ref three_phase_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_Close (three_phase_ctrl_t * const p_ctrl) +{ + gpt_three_phase_instance_ctrl_t * p_instance_ctrl = (gpt_three_phase_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(GPT_THREE_PHASE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear open flag. */ + p_instance_ctrl->open = 0U; + + /* Stop counter. */ + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_U]->GTSTP = p_instance_ctrl->channel_mask; + + /* Close all GPT modules */ + for (three_phase_channel_t ch = THREE_PHASE_CHANNEL_U; ch <= THREE_PHASE_CHANNEL_W; ch++) + { + R_GPT_Close(p_instance_ctrl->p_cfg->p_timer_instance[ch]->p_ctrl); + } + + return err; +} + +/** @} (end addtogroup GPT_THREE_PHASE) */ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enables write protection for all relevant GPT registers (if enabled). + * + * @param[in] p_instance_ctrl Instance control block. + **********************************************************************************************************************/ +static inline void r_gpt_write_protect_enable_all (gpt_three_phase_instance_ctrl_t * const p_instance_ctrl) +{ +#if GPT_CFG_WRITE_PROTECT_ENABLE + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_U]->GTWP = GPT_THREE_PHASE_PRV_GTWP_WRITE_PROTECT; + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_V]->GTWP = GPT_THREE_PHASE_PRV_GTWP_WRITE_PROTECT; + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_W]->GTWP = GPT_THREE_PHASE_PRV_GTWP_WRITE_PROTECT; +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif +} + +/*******************************************************************************************************************//** + * Disables write protection for all relevant GPT registers (if enabled). + * + * @param[in] p_instance_ctrl Instance control block. + **********************************************************************************************************************/ +static inline void r_gpt_write_protect_disable_all (gpt_three_phase_instance_ctrl_t * const p_instance_ctrl) +{ +#if GPT_CFG_WRITE_PROTECT_ENABLE + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_U]->GTWP = GPT_THREE_PHASE_PRV_GTWP_RESET_VALUE; + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_V]->GTWP = GPT_THREE_PHASE_PRV_GTWP_RESET_VALUE; + p_instance_ctrl->p_reg[THREE_PHASE_CHANNEL_W]->GTWP = GPT_THREE_PHASE_PRV_GTWP_RESET_VALUE; +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gptp/r_gptp.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gptp/r_gptp.c new file mode 100644 index 0000000000..d90b2e8cb2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_gptp/r_gptp.c @@ -0,0 +1,538 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ +#include "r_gptp.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/** "GPTP" in ASCII. Used to determine if the control block is open. */ +#define GPTP_OPEN (('G' << 24U) | ('P' << 16U) | ('T' << 8U) | ('P' << 0U)) + +#define GPTP_GPTP_TIMER_OFFSET (0x40) +#define GPTP_PULSE_OUTPUT_TIMER_OFFSET (0x30) +#define GPTP_SEC_LOWER_OFFSET (0x100000000L) + +#define GPTP_CLOCK_PERIOD_MASK (0x1F) +#define GPTP_OFFSET_MASK (0xFFFFFFFF) +#define GPTP_OFFSET_NANO_SEC_MASK (0x3FFFFFFF) +#define GPTP_SEC_UPPER_MASK (0xFFFF) + +#define GPTP_NANO_SEC_POSITION (27) +#define GPTP_SEC_UPPER_POSITION (32) + +#define GPTP_NANO_COUNT_FOR_1SEC (1000000000L) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** GPTP API mapping for gptp module. */ +const gptp_api_t g_gptp_on_gptp = +{ + .open = R_GPTP_Open, + .close = R_GPTP_Close, + .timerCfg = R_GPTP_TimerCfg, + .start = R_GPTP_Start, + .stop = R_GPTP_Stop, + .timerValueGet = R_GPTP_TimerValueGet, + .timerOffsetSet = R_GPTP_TimerOffsetSet, + .timerRateSet = R_GPTP_TimerRateSet, + .callbackSet = R_GPTP_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup GPTP + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/********************************************************************************************************************//** + * Initializes the gptp module and applies configurations. + * + * @retval FSP_SUCCESS Module opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to GPTP control block or configuration structure is NULL. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_POINTER Pointer to arguments are NULL. + ***********************************************************************************************************************/ +fsp_err_t R_GPTP_Open (gptp_ctrl_t * const p_ctrl, gptp_cfg_t const * const p_cfg) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN((NULL != p_cfg), FSP_ERR_INVALID_POINTER); + + FSP_ERROR_RETURN((GPTP_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN); +#endif + + /* Initialize configuration of gptp module. */ + p_instance_ctrl->p_reg_gptp = (void *) R_GPTP; + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + p_instance_ctrl->open = GPTP_OPEN; + + return FSP_SUCCESS; +} /* End of function R_GPTP_Open() */ + +/********************************************************************************************************************//** + * Close the gptp module. + * + * @retval FSP_SUCCESS Successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to GPTP control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * + ***********************************************************************************************************************/ +fsp_err_t R_GPTP_Close (gptp_ctrl_t * const p_ctrl) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear configure block parameters. */ + p_instance_ctrl->p_cfg = NULL; + + /* Mark the channel not open so other APIs cannot use it. */ + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} /* End of function R_GPTP_Close() */ + +/*******************************************************************************************************************//** + * Configures the gptp timer parameters. + * + * @retval FSP_SUCCESS Command successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid timer id. + * @retval FSP_ERR_INVALID_POINTER Invalid poiter to the timer cfg. + **********************************************************************************************************************/ +fsp_err_t R_GPTP_TimerCfg (gptp_ctrl_t * const p_ctrl, uint8_t timer, gptp_timer_cfg_t const * const p_timer_cfg) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + volatile uint32_t * p_ptpvic_reg; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((BSP_FEATURE_ESWM_GPTP_TIMER_NUM > timer), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(NULL != p_timer_cfg, FSP_ERR_INVALID_POINTER); +#endif + + p_ptpvic_reg = (volatile uint32_t *) ((uint8_t *) &p_instance_ctrl->p_reg_gptp->PTPTIVC0 + \ + (GPTP_GPTP_TIMER_OFFSET * timer)); + *p_ptpvic_reg = + (uint32_t) ((p_timer_cfg->clock_period & GPTP_CLOCK_PERIOD_MASK) << GPTP_NANO_SEC_POSITION); + + return FSP_SUCCESS; +} /* End of function R_GPTP_TimerCfg() */ + +/*******************************************************************************************************************//** + * Starts gptp timer. + * + * @retval FSP_SUCCESS Timer started.. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid timer id. + **********************************************************************************************************************/ +fsp_err_t R_GPTP_Start (gptp_ctrl_t * const p_ctrl, uint8_t timer) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + R_GPTP_Type * p_gptp_reg; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((BSP_FEATURE_ESWM_GPTP_TIMER_NUM > timer), FSP_ERR_INVALID_ARGUMENT); +#endif + + p_gptp_reg = p_instance_ctrl->p_reg_gptp; + p_gptp_reg->PTPTMEC_b.TE |= (1U << timer); + + return FSP_SUCCESS; +} /* End of function R_GPTP_Start() */ + +/*******************************************************************************************************************//** + * Stops gptp timer. + * + * @retval FSP_SUCCESS Timer stopped. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid timer id. + **********************************************************************************************************************/ +fsp_err_t R_GPTP_Stop (gptp_ctrl_t * const p_ctrl, uint8_t timer) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + R_GPTP_Type * p_gptp_reg; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((BSP_FEATURE_ESWM_GPTP_TIMER_NUM > timer), FSP_ERR_INVALID_ARGUMENT); +#endif + + p_gptp_reg = p_instance_ctrl->p_reg_gptp; + p_gptp_reg->PTPTMDC_b.TD |= (1U << timer); + + return FSP_SUCCESS; +} /* End of function R_GPTP_Stop() */ + +/*******************************************************************************************************************//** + * Gets the current time value to the timer with the specified gptp timer number. + * + * @retval FSP_SUCCESS Sec upper, sec lower, and nano sec srored in p_timestamp. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to arguments are NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid input parameter. + **********************************************************************************************************************/ +fsp_err_t R_GPTP_TimerValueGet (gptp_ctrl_t * const p_ctrl, uint8_t timer, gptp_timer_value_t * const p_timer_value) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + R_GPTP_Type * p_gptp_reg; + volatile uint32_t * p_ptpgptptml_reg; + volatile uint32_t * p_ptpgptptmm_reg; + volatile uint32_t * p_ptpgptptmu_reg; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + FSP_ERROR_RETURN((NULL != p_timer_value), FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(BSP_FEATURE_ESWM_GPTP_TIMER_NUM > timer, FSP_ERR_INVALID_ARGUMENT); +#endif + + p_gptp_reg = p_instance_ctrl->p_reg_gptp; + + p_ptpgptptml_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->PTPGPTPTML0 + \ + (GPTP_GPTP_TIMER_OFFSET * timer)); + p_timer_value->time_nsec = *p_ptpgptptml_reg; + + p_ptpgptptmm_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->PTPGPTPTMM0 + \ + (GPTP_GPTP_TIMER_OFFSET * timer)); + p_timer_value->time_sec_lower = *p_ptpgptptmm_reg; + + p_ptpgptptmu_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->PTPGPTPTMU0 + \ + (GPTP_GPTP_TIMER_OFFSET * timer)); + p_timer_value->time_sec_upper = (uint16_t) (*p_ptpgptptmu_reg); + + return FSP_SUCCESS; +} /* End of R_GPTP_GptpTimeValueGet() */ + +/********************************************************************************************************************//** + * Sets the offset correction for the specified gptp timer number. + * + * @retval FSP_SUCCESS Time offset set successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid input parameter. + ***********************************************************************************************************************/ +fsp_err_t R_GPTP_TimerOffsetSet (gptp_ctrl_t * const p_ctrl, uint8_t timer, int64_t offset) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + R_GPTP_Type * p_gptp_reg; + + int64_t offset_abs; + int64_t offset_nsec; + int64_t offset_sec_lower; + int64_t offset_sec_upper; + + volatile uint32_t * p_ptptovcl_reg; + volatile uint32_t * p_ptptovcm_reg; + volatile uint32_t * p_ptptovcu_reg; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_ESWM_GPTP_TIMER_NUM > timer, FSP_ERR_INVALID_ARGUMENT); +#endif + + p_gptp_reg = p_instance_ctrl->p_reg_gptp; + + /* Obtains the offset value currently applied to the gPTP timer and adds the set offset. */ + p_ptptovcl_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->PTPTOVCL0 + \ + (GPTP_GPTP_TIMER_OFFSET * timer)); + p_ptptovcm_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->PTPTOVCM0 + \ + (GPTP_GPTP_TIMER_OFFSET * timer)); + p_ptptovcu_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->PTPTOVCU0 + \ + (GPTP_GPTP_TIMER_OFFSET * timer)); + + if (0 <= offset) + { + /* When advancing a gPTP timer, add an offset value. */ + offset_abs = offset; + + /* Check for carryover during nanosecond addition. */ + offset_nsec = (int64_t) (*p_ptptovcl_reg) + (offset_abs % GPTP_NANO_COUNT_FOR_1SEC); + if (GPTP_NANO_COUNT_FOR_1SEC <= offset_nsec) + { + offset_nsec -= GPTP_NANO_COUNT_FOR_1SEC; + offset_sec_lower = (int64_t) (*p_ptptovcm_reg) + \ + ((offset_abs / GPTP_NANO_COUNT_FOR_1SEC) & GPTP_OFFSET_MASK) + 1; + } + else + { + offset_sec_lower = (int64_t) (*p_ptptovcm_reg) + \ + ((offset_abs / GPTP_NANO_COUNT_FOR_1SEC) & GPTP_OFFSET_MASK); + } + + /* Check for carryover during lower second addition. */ + if ((int64_t) GPTP_OFFSET_MASK < offset_sec_lower) + { + offset_sec_lower -= (int64_t) GPTP_SEC_LOWER_OFFSET; + offset_sec_upper = (int64_t) (*p_ptptovcu_reg) + \ + ((offset_abs / GPTP_NANO_COUNT_FOR_1SEC) >> GPTP_SEC_UPPER_POSITION) + 1; + } + else + { + offset_sec_upper = (int64_t) (*p_ptptovcu_reg) + \ + ((offset_abs / GPTP_NANO_COUNT_FOR_1SEC) >> GPTP_SEC_UPPER_POSITION); + } + } + else + { + /* To set the gPTP timer back, subtract the offset value. */ + offset_abs = offset * -1; + + /* When subtracting nanoseconds, check for borrowing. */ + offset_nsec = (int64_t) (*p_ptptovcl_reg) - (offset_abs % GPTP_NANO_COUNT_FOR_1SEC); + if (0 > offset_nsec) + { + offset_nsec += GPTP_NANO_COUNT_FOR_1SEC; + offset_sec_lower = (int64_t) (*p_ptptovcm_reg) - \ + ((offset_abs / GPTP_NANO_COUNT_FOR_1SEC) & GPTP_OFFSET_MASK) - 1; + } + else + { + offset_sec_lower = (int64_t) (*p_ptptovcm_reg) - \ + ((offset_abs / GPTP_NANO_COUNT_FOR_1SEC) & GPTP_OFFSET_MASK); + } + + /* When subtracting lower second, check for borrowing. */ + if (0 > offset_sec_lower) + { + offset_sec_lower += (int64_t) GPTP_SEC_LOWER_OFFSET; + offset_sec_upper = (int64_t) (*p_ptptovcu_reg) - \ + ((offset_abs / GPTP_NANO_COUNT_FOR_1SEC) >> GPTP_SEC_UPPER_POSITION) - 1; + } + else + { + offset_sec_upper = (int64_t) (*p_ptptovcu_reg) - \ + ((offset_abs / GPTP_NANO_COUNT_FOR_1SEC) >> GPTP_SEC_UPPER_POSITION); + } + } + + *p_ptptovcu_reg = (uint16_t) offset_sec_upper; + *p_ptptovcm_reg = (uint32_t) offset_sec_lower; + *p_ptptovcl_reg = (uint32_t) offset_nsec & GPTP_OFFSET_NANO_SEC_MASK; + + return FSP_SUCCESS; +} /* End of function R_GPTP_TimeOffsetSet() */ + +/********************************************************************************************************************//** + * Sets clock rate correction for the specified timer. + * + * @retval FSP_SUCCESS Time rate set successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to arguments are NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid input parameter. + ***********************************************************************************************************************/ +fsp_err_t R_GPTP_TimerRateSet (gptp_ctrl_t * const p_ctrl, uint8_t timer, uint32_t rate) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + R_GPTP_Type * p_gptp_reg; + volatile uint32_t * p_ptpvic_reg; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_ESWM_GPTP_TIMER_NUM > timer, FSP_ERR_INVALID_ARGUMENT); +#endif + + p_gptp_reg = p_instance_ctrl->p_reg_gptp; + + p_ptpvic_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->PTPTIVC0 + \ + (GPTP_GPTP_TIMER_OFFSET * timer)); + *p_ptpvic_reg = rate; + + return FSP_SUCCESS; +} /* End of function R_GPTP_TimeRateSet() */ + +/********************************************************************************************************************//** + * Sets pulse generator. + * + * @retval FSP_SUCCESS Pulse generator set successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to arguments are NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid input parameter. + ***********************************************************************************************************************/ +fsp_err_t R_GPTP_PulseGeneratorSet (gptp_ctrl_t * const p_ctrl, uint8_t timer, gptp_pulse_generator_t * p_pulse) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + gptp_pulsed_output_cfg_t * p_pulsed_output_cfg; + R_GPTP_Type * p_gptp_reg; + + volatile uint32_t * p_potcr_reg; + volatile uint32_t * p_potstru_reg; + volatile uint32_t * p_potstrm_reg; + volatile uint32_t * p_potstrl_reg; + volatile uint32_t * p_potperu_reg; + volatile uint32_t * p_potperm_reg; + volatile uint32_t * p_potperl_reg; + volatile uint32_t * p_potpwr_reg; + +#if (GPTP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + FSP_ERROR_RETURN((NULL != p_pulse), FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(BSP_FEATURE_ESWM_GPTP_TIMER_NUM > timer, FSP_ERR_INVALID_ARGUMENT); + + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM; i++) + { + FSP_ERROR_RETURN(BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM > p_pulse->p_pulsed_output_cfg_list[i]->pulse_num, + FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(GPTP_NANO_COUNT_FOR_1SEC > p_pulse->p_pulsed_output_cfg_list[i]->period_ns, + FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(GPTP_NANO_COUNT_FOR_1SEC > p_pulse->p_pulsed_output_cfg_list[i]->start_ns, + FSP_ERR_INVALID_ARGUMENT); + } +#endif + + p_gptp_reg = p_instance_ctrl->p_reg_gptp; + + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_GPTP_PULSE_GENERATOR_NUM; i++) + { + p_pulsed_output_cfg = p_pulse->p_pulsed_output_cfg_list[i]; + p_potcr_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->POTCR0 + + (GPTP_PULSE_OUTPUT_TIMER_OFFSET * p_pulsed_output_cfg->pulse_num)); + + /* Stop pulse output for modification POTCFGR register. */ + *p_potcr_reg = 0U; + + p_gptp_reg->POTCFGR_b.REFSEL = (uint32_t) (timer & 0x1); + + /* Modification Pulse output generation registers. */ + p_potstru_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->POTSTRU0 + \ + (GPTP_PULSE_OUTPUT_TIMER_OFFSET * p_pulsed_output_cfg->pulse_num)); + *p_potstru_reg = (p_pulsed_output_cfg->start_sec_upper & GPTP_SEC_UPPER_MASK); + + p_potstrm_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->POTSTRM0 + \ + (GPTP_PULSE_OUTPUT_TIMER_OFFSET * p_pulsed_output_cfg->pulse_num)); + *p_potstrm_reg = p_pulsed_output_cfg->start_sec_lower; + + p_potstrl_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->POTSTRL0 + \ + (GPTP_PULSE_OUTPUT_TIMER_OFFSET * p_pulsed_output_cfg->pulse_num)); + *p_potstrl_reg = (p_pulsed_output_cfg->start_ns & GPTP_OFFSET_NANO_SEC_MASK); + + p_potperu_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->POTPERU0 + \ + (GPTP_PULSE_OUTPUT_TIMER_OFFSET * p_pulsed_output_cfg->pulse_num)); + *p_potperu_reg = (p_pulsed_output_cfg->period_sec_upper & GPTP_SEC_UPPER_MASK); + + p_potperm_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->POTPERM0 + \ + (GPTP_PULSE_OUTPUT_TIMER_OFFSET * p_pulsed_output_cfg->pulse_num)); + *p_potperm_reg = p_pulsed_output_cfg->period_sec_lower; + + p_potperl_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->POTPERL0 + \ + (GPTP_PULSE_OUTPUT_TIMER_OFFSET * p_pulsed_output_cfg->pulse_num)); + *p_potperl_reg = (p_pulsed_output_cfg->period_ns & GPTP_OFFSET_NANO_SEC_MASK); + + p_potpwr_reg = (volatile uint32_t *) ((uint8_t *) &p_gptp_reg->POTPWR0 + \ + (GPTP_PULSE_OUTPUT_TIMER_OFFSET * p_pulsed_output_cfg->pulse_num)); + *p_potpwr_reg = (p_pulsed_output_cfg->wide & GPTP_SEC_UPPER_MASK); + + /* Apply generate pulse setting. */ + *p_potcr_reg = 1U; + } + + return FSP_SUCCESS; +} /* End of function R_GPTP_PulseGeneratorSet() */ + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref gptp_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_GPTP_CallbackSet (gptp_ctrl_t * const p_ctrl, + void ( * p_callback)(gptp_callback_args_t *), + void * const p_context, + gptp_callback_args_t * const p_callback_memory) +{ + gptp_instance_ctrl_t * p_instance_ctrl = (gptp_instance_ctrl_t *) p_ctrl; + +#if GPTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(GPTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if GPTP_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + gptp_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(gptp_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup GPTP) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_i3c/r_i3c.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_i3c/r_i3c.c new file mode 100644 index 0000000000..bb5cd5a244 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_i3c/r_i3c.c @@ -0,0 +1,2589 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_i3c.h" +#include "r_i3c_cfg.h" + +/* The address of the MCU Version Register on RA2E2 MCUs. Different error recovery procedures are used depending on the + * version of the MCU (This is only used on RA2E2 devices). */ +#define I3C_A2E2_VERSION (*((uint8_t const *) 0x01001C20U)) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef enum e_i3c_internal_state +{ + I3C_INTERNAL_STATE_DISABLED, + I3C_INTERNAL_STATE_MASTER_IDLE, + I3C_INTERNAL_STATE_MASTER_ENTDAA = I3C_EVENT_ADDRESS_ASSIGNMENT_COMPLETE, + I3C_INTERNAL_STATE_MASTER_WRITE = I3C_EVENT_WRITE_COMPLETE, + I3C_INTERNAL_STATE_MASTER_READ = I3C_EVENT_READ_COMPLETE, + I3C_INTERNAL_STATE_MASTER_COMMAND_WRITE = I3C_EVENT_COMMAND_COMPLETE, + I3C_INTERNAL_STATE_MASTER_COMMAND_READ = (I3C_EVENT_COMMAND_COMPLETE | (0x80U)), + I3C_INTERNAL_STATE_SLAVE_IDLE, + I3C_INTERNAL_STATE_SLAVE_IBI = I3C_EVENT_IBI_WRITE_COMPLETE, +} i3c_internal_state_t; + +typedef enum e_i3c_slave_error_recovery_type +{ + I3C_SLAVE_ERROR_RECOVERY_TYPE_WRITE = 0, + I3C_SLAVE_ERROR_RECOVERY_TYPE_READ = 1, + I3C_SLAVE_ERROR_RECOVERY_TYPE_IBI = 2, + I3C_SLAVE_ERROR_RECOVERY_TYPE_OTHER = 2, +} i3c_slave_error_recovery_type_t; + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define I3C_OPEN (('I' << 16U) | ('3' << 8U) | ('C' << 0U)) + +/* Bitfield definitions for Command Descriptor fields. */ +#define I3C_CMD_DESC_CMD_ATTR_Pos (0U) +#define I3C_CMD_DESC_CMD_ATTR_Msk (7U << I3C_CMD_DESC_CMD_ATTR_Pos) +#define I3C_CMD_DESC_CND_ATTR_XFER (0U) +#define I3C_CMD_DESC_CND_ATTR_IMMED_DATA_XFER (1U) +#define I3C_CMD_DESC_CMD_ATTR_ADDR_ASSGN_CMD (2U) +#define I3C_CMD_DESC_TID_Pos (3U) +#define I3C_CMD_DESC_TID_Msk (0x0FU << I3C_CMD_DESC_TID_Pos) +#define I3C_CMD_DESC_CMD_Pos (7U) +#define I3C_CMD_DESC_CMD_Msk (0xFFU << I3C_CMD_DESC_CMD_Pos) +#define I3C_CMD_DESC_DEV_INDEX_Pos (16U) +#define I3C_CMD_DESC_DEV_INDEX_Msk (0x01FFU << I3C_CMD_DESC_DEV_INDEX_Pos) +#define I3C_CMD_DESC_ROC_Pos (30U) +#define I3C_CMD_DESC_ROC_Msk (1U << I3C_CMD_DESC_ROC_Pos) +#define I3C_CMD_DESC_TOC_Pos (31U) +#define I3C_CMD_DESC_TOC_Msk (1U << I3C_CMD_DESC_TOC_Pos) + +/* Command Descriptor definitions for Address Assign Commands. */ +#define I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Pos (26U) +#define I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Msk (0x0FU << I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Pos) + +/* Command Descriptor definitions for Regular Transfer Commands. */ +#define I3C_CMD_DESC_XFER_CP_Pos (15U) +#define I3C_CMD_DESC_XFER_CP_Msk (1U << I3C_CMD_DESC_XFER_CP_Pos) +#define I3C_CMD_DESC_XFER_HJ_Pos (15U) +#define I3C_CMD_DESC_XFER_HJ_Msk (1U << I3C_CMD_DESC_XFER_HJ_Pos) +#define I3C_CMD_DESC_XFER_LENGTH_Pos (16U) +#define I3C_CMD_DESC_XFER_LENGTH_Msk (0xFFFFU << I3C_CMD_DESC_XFER_LENGTH_Pos) +#define I3C_CMD_DESC_XFER_MODE_Pos (26U) +#define I3C_CMD_DESC_XFER_MODE_Msk (0x07U << I3C_CMD_DESC_XFER_MODE_Pos) +#define I3C_CMD_DESC_XFER_RNW_Pos (29U) +#define I3C_CMD_DESC_XFER_RNW_Msk (1U << I3C_CMD_DESC_XFER_RNW_Pos) +#define I3C_CMD_DESC_XFER_MODE_I2C_STDBR (0U) +#define I3C_CMD_DESC_XFER_MODE_I2C_EXDBR (1U) +#define I3C_CMD_DESC_XFER_MODE_I3C_SDR_EXTBR_X2 (3U) +#define I3C_CMD_DESC_XFER_MODE_I3C_SDR_EXTBR_X4 (4U) + +/* Command Descriptor definitions for Immediate Data Transfer Commands. */ +#define I3C_CMD_DESC_IMMED_DATA_XFER_BYTE_CNT_Pos (23U) + +/* Bitfield definitions for the Response Status Descriptor fields. */ +#define I3C_RESP_STATUS_DESC_DATA_LENGTH_Pos (0U) +#define I3C_RESP_STATUS_DESC_DATA_LENGTH_Msk (0xFFFFU << I3C_RESP_STATUS_DESC_DATA_LENGTH_Pos) +#define I3C_RESP_STATUS_DESC_TID_Pos (24U) +#define I3C_RESP_STATUS_DESC_TID_Msk (0x0FU << I3C_RESP_STATUS_DESC_TID_Pos) +#define I3C_RESP_STATUS_DESC_ERR_STATUS_Pos (28U) +#define I3C_RESP_STATUS_DESC_ERR_STATUS_Msk (0x0FU << I3C_RESP_STATUS_DESC_ERR_STATUS_Pos) + +/* Bitfield definitions for Receive Status Descriptor fields. */ +#define I3C_RECV_STATUS_DESC_DATA_LENGTH_Pos (0U) +#define I3C_RECV_STATUS_DESC_DATA_LENGTH_Msk (0xFFFFU << I3C_RECV_STATUS_DESC_DATA_LENGTH_Pos) +#define I3C_RECV_STATUS_DESC_CMD_Pos (16U) +#define I3C_RECV_STATUS_DESC_CMD_Msk (0xFFU << I3C_RECV_STATUS_DESC_CMD_Pos) +#define I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Pos (23U) +#define I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Msk (0x01U << I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Pos) +#define I3C_RECV_STATUS_DESC_ERR_STATUS_Pos (24U) +#define I3C_RECV_STATUS_DESC_ERR_STATUS_Msk (0x07U << I3C_RECV_STATUS_DESC_ERR_STATUS_Pos) +#define I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Pos (27U) +#define I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Msk (0x03U << I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Pos) +#define I3C_RECV_STATUS_DESC_DEV_INDEX_Pos (29U) +#define I3C_RECV_STATUS_DESC_DEV_INDEX_Msk (0x07U << I3C_RECV_STATUS_DESC_DEV_INDEX_Pos) + +/* Bitfield definitions for IBI Status Descriptor fields. */ +#define I3C_IBI_STATUS_DESC_LENGTH_Pos (0U) +#define I3C_IBI_STATUS_DESC_LENGTH_Msk (0xFFU << I3C_IBI_STATUS_DESC_LENGTH_Pos) +#define I3C_IBI_STATUS_DESC_IBI_ID_Pos (8U) +#define I3C_IBI_STATUS_DESC_IBI_ID_Msk (0xFFU << I3C_IBI_STATUS_DESC_IBI_ID_Pos) +#define I3C_IBI_STATUS_DESC_LAST_STATUS_Pos (24U) +#define I3C_IBI_STATUS_DESC_LAST_STATUS_Msk (1U << I3C_IBI_STATUS_DESC_LAST_STATUS_Pos) +#define I3C_IBI_STATUS_DESC_TS_Pos (25U) +#define I3C_IBI_STATUS_DESC_TS_Msk (1U << I3C_IBI_STATUS_DESC_TS_Pos) +#define I3C_IBI_STATUS_DESC_ERR_STATUS_Pos (26U) +#define I3C_IBI_STATUS_DESC_ERR_STATUS_Msk (0x7U << I3C_IBI_STATUS_DESC_ERR_STATUS_Pos) +#define I3C_IBI_STATUS_DESC_IBI_ST_Pos (31U) +#define I3C_IBI_STATUS_DESC_IBI_ST_Msk (1U << I3C_IBI_STATUS_DESC_IBI_ST_Pos) + +/* Address that is written by the slave during a Hot Join request. */ +#define I3C_HOT_JOIN_ADDRESS (2U) + +/* Mask for flushing the Read, Write, and Command FIFO. */ +#define I3C_RSTCTRL_FIFO_FLUSH_Msk (R_I3C0_RSTCTL_CMDQRST_Msk | R_I3C0_RSTCTL_TDBRST_Msk | \ + R_I3C0_RSTCTL_RDBRST_Msk) + +#define I3C_MAX_PUSH_PULL_PERIOD (0x3FU) + +/* Mask for converting the internal state into an I3C event. */ +#define I3C_INTERNAL_EVENT_MASK (0x7FU) + +/*********************************************************************************************************************** + * Function Prototypes + **********************************************************************************************************************/ + +/* ISR function prototypes. */ +void i3c_resp_isr(void); +void i3c_rx_isr(void); +void i3c_tx_isr(void); +void i3c_rcv_isr(void); +void i3c_ibi_isr(void); +void i3c_eei_isr(void); + +static uint8_t i3c_address_parity(uint8_t address); + +#if I3C_CFG_MASTER_SUPPORT +static uint32_t i3c_xfer_command_calculate(uint32_t dev_index, bool rnw, uint32_t bitrate_setting, bool restart); + +#endif +static void i3c_fifo_read(i3c_instance_ctrl_t * p_ctrl, uint32_t bytes); +static void i3c_fifo_write(i3c_instance_ctrl_t * p_ctrl); +static void i3c_read_buffer_store(i3c_instance_ctrl_t * const p_ctrl, + i3c_read_buffer_descriptor_t * p_buffer_descriptor, + uint32_t data_word, + uint32_t num_bytes, + i3c_event_t buffer_full_event); +static uint32_t i3c_read_bytes_remaining_calculate(i3c_instance_ctrl_t * p_ctrl, uint32_t data_length); +static uint32_t i3c_next_data_word_calculate(i3c_write_buffer_descriptor_t * p_buffer_descriptor); +static i3c_ctrl_t * i3c_isr_context_get(void); + +#if I3C_CFG_MASTER_SUPPORT +static void i3c_master_error_recovery(i3c_instance_ctrl_t * p_ctrl, bool error_recovery_case_2); + +#endif +#if I3C_CFG_SLAVE_SUPPORT +static void i3c_slave_error_recovery(i3c_instance_ctrl_t * p_ctrl, i3c_slave_error_recovery_type_t recovery_type); + +#endif + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* I3C implementation of I3C API. */ +const i3c_api_t g_i3c_on_i3c = +{ + .open = R_I3C_Open, + .enable = R_I3C_Enable, + .deviceCfgSet = R_I3C_DeviceCfgSet, + .masterDeviceTableSet = R_I3C_MasterDeviceTableSet, + .slaveStatusSet = R_I3C_SlaveStatusSet, + .deviceSelect = R_I3C_DeviceSelect, + .dynamicAddressAssignmentStart = R_I3C_DynamicAddressAssignmentStart, + .commandSend = R_I3C_CommandSend, + .write = R_I3C_Write, + .read = R_I3C_Read, + .ibiWrite = R_I3C_IbiWrite, + .ibiRead = R_I3C_IbiRead, + .close = R_I3C_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup I3C + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure an I3C instance. Implements @ref i3c_api_t::open. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was invalid. + * @retval FSP_ERR_ALREADY_OPEN Open has already been called for this instance. + * @retval FSP_ERR_UNSUPPORTED A selected feature is not supported with the current configuration. + **********************************************************************************************************************/ +fsp_err_t R_I3C_Open (i3c_ctrl_t * const p_api_ctrl, i3c_cfg_t const * const p_cfg) +{ + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + +#if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(I3C_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + i3c_extended_cfg_t const * p_extend = (i3c_extended_cfg_t const *) p_cfg->p_extend; + FSP_ASSERT(0 <= p_extend->resp_irq); + FSP_ASSERT(0 <= p_extend->rcv_irq); + FSP_ASSERT(0 <= p_extend->tx_irq); + FSP_ASSERT(0 <= p_extend->rx_irq); + FSP_ASSERT(0 <= p_extend->ibi_irq); + FSP_ASSERT(0 <= p_extend->eei_irq); + #if 0U == I3C_CFG_MASTER_SUPPORT + FSP_ERROR_RETURN(I3C_DEVICE_TYPE_MAIN_MASTER != p_cfg->device_type, FSP_ERR_UNSUPPORTED); + #endif + #if 0U == I3C_CFG_SLAVE_SUPPORT + FSP_ERROR_RETURN(I3C_DEVICE_TYPE_SLAVE != p_cfg->device_type, FSP_ERR_UNSUPPORTED); + #endif +#endif + + /* Initialize the internal state of the driver. */ + memset(p_ctrl, 0, sizeof(i3c_instance_ctrl_t)); + + p_ctrl->open = I3C_OPEN; + p_ctrl->p_cfg = p_cfg; + + /* Clear the I3C Module Stop bit. */ + R_BSP_MODULE_START(FSP_IP_I3C, p_cfg->channel); + + /* Get a pointer to the I3C registers for this channel. */ +#if BSP_FEATURE_I3C_NUM_CHANNELS > 1 + p_ctrl->p_reg = (R_I3C0_Type *) ((uint32_t) R_I3C0 + (p_cfg->channel * ((uint32_t) R_I3C1 - (uint32_t) R_I3C0))); +#else + p_ctrl->p_reg = R_I3C0; +#endif + +#if BSP_FEATURE_I3C_HAS_CLOCK + p_ctrl->p_reg->CECTL = 1; +#endif + + /* + * Reset the I3C Peripheral so that it is in a known state during initialization (See Figure "I3C Communication Flow" + * in the I3C section of the relevant hardware manual). + */ + p_ctrl->p_reg->BCTL_b.BUSE = 0; + p_ctrl->p_reg->RSTCTL = 1U; + + /* The field will be cleared automatically upon reset completion (See "RSTCTL : Reset Control Register" description in the I3C section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U); + + /* Set internal reset to one before setting I3C mode. */ + p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_INTLRST_Msk; + + /* Set I3C mode. */ + p_ctrl->p_reg->PRTS = 0U; + + /* Clear internal reset. */ + p_ctrl->p_reg->RSTCTL = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable the I3C device. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_INVALID_MODE This instance is already enabled. + **********************************************************************************************************************/ +fsp_err_t R_I3C_Enable (i3c_ctrl_t * const p_api_ctrl) +{ + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + +#if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_DISABLED == p_ctrl->internal_state, FSP_ERR_INVALID_MODE); +#endif + + i3c_extended_cfg_t const * p_extend = (i3c_extended_cfg_t const *) p_ctrl->p_cfg->p_extend; + + /* + * Write all remaining configuration settings (See Figure "I3C Communication Flow" in the I3C section + * of the relevant hardware manual). + * + * Configure the Normal IBI Data Segment Size used for receiving IBI data. + */ + uint32_t nqthctl = 6U << R_I3C0_NQTHCTL_IBIDSSZ_Pos; + + /* + * Enable Transfer Interrupts. + * - Read Buffer Full Interrupt. + * - Receive Status Queue Full Interrupt + * - Response Queue Full Interrupt + */ + uint32_t ntie = R_I3C0_NTIE_RDBFIE0_Msk | + R_I3C0_NTIE_RSPQFIE_Msk | + R_I3C0_NTIE_RSQFIE_Msk; + +#if I3C_CFG_MASTER_SUPPORT + if (I3C_DEVICE_TYPE_MAIN_MASTER == p_ctrl->p_cfg->device_type) + { + p_ctrl->internal_state = I3C_INTERNAL_STATE_MASTER_IDLE; + + /* Enable the Queue Empty/Full Interrupt. */ + ntie |= R_I3C0_NTIE_IBIQEFIE_Msk; + + /* Write the standard and extended bitrate settings. */ + p_ctrl->p_reg->STDBR = p_extend->bitrate_settings.stdbr; + p_ctrl->p_reg->EXTBR = p_extend->bitrate_settings.extbr; + } + else +#endif + { +#if I3C_CFG_SLAVE_SUPPORT + p_ctrl->internal_state = I3C_INTERNAL_STATE_SLAVE_IDLE; + + /* + * Configure IBI queue threshold so that an IBI IRQ is generated when there is one empty entry in the + * IBI transmit FIFO. + */ + nqthctl |= 1U << R_I3C0_NQTHCTL_IBIQTH_Pos; + + /* Baudrate registers are not used in slave mode. */ + p_ctrl->p_reg->STDBR = 0; + p_ctrl->p_reg->EXTBR = 0; +#endif + } + + /* + * Write settings to the Normal Queue Threshold Control Register. + * - Normal Response Queue Threshold interrupt after one response is received. + * - Normal IBI Queue Threshold interrupt after one IBI status is received. + * - Normal IBI Data Segment Size set to 6 words. + */ + p_ctrl->p_reg->NQTHCTL = nqthctl; + + /* Set the Normal Transfer Data Buffer threshold for transmit and receive (The only supported configuration + * is two entries). */ + p_ctrl->p_reg->NTBTHCTL0 = 0; + + /* Set the Receive Status Queue Threshold to zero (Interrupt when there is one entry in the queue). */ + p_ctrl->p_reg->NRQTHCTL = 0; + + /* Enable the Internal Error Status Flag. */ + p_ctrl->p_reg->INSTE = R_I3C0_INSTE_INEE_Msk; + + /* Enable all Bus Status Flags. */ + p_ctrl->p_reg->BSTE = (R_I3C0_BSTE_STCNDDE_Msk | + R_I3C0_BSTE_SPCNDDE_Msk | + R_I3C0_BSTE_HDREXDE_Msk | + R_I3C0_BSTE_NACKDE_Msk | + R_I3C0_BSTE_TENDE_Msk | + R_I3C0_BSTE_ALE_Msk | + R_I3C0_BSTE_TODE_Msk); + + /* Enable all Transfer Status Flags. */ + p_ctrl->p_reg->NTSTE = (R_I3C0_NTSTE_TDBEE0_Msk | + R_I3C0_NTSTE_RDBFE0_Msk | + R_I3C0_NTSTE_IBIQEFE_Msk | + R_I3C0_NTSTE_CMDQEE_Msk | + R_I3C0_NTSTE_RSPQFE_Msk | + R_I3C0_NTSTE_TABTE_Msk | + R_I3C0_NTSTE_TEE_Msk | + R_I3C0_NTSTE_RSQFE_Msk); + + /* Enable the Internal Error Interrupt Requests. */ + p_ctrl->p_reg->INIE = R_I3C0_INIE_INEIE_Msk; + + /* Enable HDR exit pattern Interrupt Requests. */ + p_ctrl->p_reg->BIE = R_I3C0_BIE_HDREXDIE_Msk | R_I3C0_BIE_TODIE_Msk; + + /* Write settings to the Normal Transfer Interrupt Enable Register. */ + p_ctrl->p_reg->NTIE = ntie; + + /* Write the Hot-Join Ackowlege settings. */ + p_ctrl->p_reg->BCTL_b.HJACKCTL = !p_extend->ibi_control.hot_join_acknowledge; + + /* Calculate the value of the IBI Notify Control Register. */ + uint32_t ibinctl = + (uint32_t) (p_extend->ibi_control.notify_rejected_hot_join_requests << R_I3C0_IBINCTL_NRHJCTL_Pos); + ibinctl |= (uint32_t) (p_extend->ibi_control.notify_rejected_mastership_requests << R_I3C0_IBINCTL_NRMRCTL_Pos); + ibinctl |= (uint32_t) (p_extend->ibi_control.notify_rejected_interrupt_requests << R_I3C0_IBINCTL_NRSIRCTL_Pos); + + /* Write settings to the IBI Notify Control Register. */ + p_ctrl->p_reg->IBINCTL = ibinctl; + + /* Calculate the value of the SCL Clock Stalling Control Register. */ + uint32_t scstlctl = (uint32_t) (p_extend->bitrate_settings.clock_stalling.assigned_address_phase_enable << + R_I3C0_SCSTLCTL_AAPE_Pos); + scstlctl |= (uint32_t) (p_extend->bitrate_settings.clock_stalling.transition_phase_enable << + R_I3C0_SCSTLCTL_TRAPE_Pos); + scstlctl |= (uint32_t) (p_extend->bitrate_settings.clock_stalling.parity_phase_enable << R_I3C0_SCSTLCTL_PARPE_Pos); + scstlctl |= (uint32_t) (p_extend->bitrate_settings.clock_stalling.ack_phase_enable << R_I3C0_SCSTLCTL_ACKPE_Pos); + scstlctl |= + (uint32_t) (p_extend->bitrate_settings.clock_stalling.clock_stalling_time << R_I3C0_SCSTLCTL_STLCYC_Pos); + + /* Write clock stalling settings to the SCL CLock Stalling Control Register. */ + p_ctrl->p_reg->SCSTLCTL = scstlctl; + + /* Write Bus Condition Detection Registers. */ + p_ctrl->p_reg->BFRECDT = p_extend->bus_free_detection_time; + p_ctrl->p_reg->BAVLCDT = p_extend->bus_available_detection_time; + p_ctrl->p_reg->BIDLCDT = p_extend->bus_idle_detection_time; + + if (!p_extend->timeout_detection_enable) + { + /* Disable Timeout Detection. */ + p_ctrl->p_reg->TMOCTL = 0U; + } + +#if I3C_CFG_SLAVE_SUPPORT + + /* Calculate the value of the CCC Slave Events Command Register. */ + uint32_t csecmd = + (uint32_t) (p_extend->slave_command_response_info.inband_interrupt_enable << R_I3C0_CSECMD_SVIRQE_Pos); + csecmd |= (uint32_t) (p_extend->slave_command_response_info.mastership_request_enable << R_I3C0_CSECMD_MSRQE_Pos); + csecmd |= (uint32_t) (p_extend->slave_command_response_info.hotjoin_request_enable << R_I3C0_CSECMD_HJEVE_Pos); + + /* Calculate the value of the CCC Max Data Speed Read Register. */ + uint32_t cmdspr = (uint32_t) p_extend->slave_command_response_info.read_data_rate << R_I3C0_CMDSPR_MSRDR_Pos; + cmdspr |= (uint32_t) p_extend->slave_command_response_info.clock_data_turnaround << R_I3C0_CMDSPR_CDTTIM_Pos; + + /* Calculate the value of the CCC Max Data Speed Rurnaround Register. */ + uint32_t cmdspt = p_extend->slave_command_response_info.read_turnaround_time << R_I3C0_CMDSPT_MRTTIM_Pos; + cmdspt |= (uint32_t) p_extend->slave_command_response_info.read_turnaround_time_enable << R_I3C0_CMDSPT_MRTE_Pos; + + /* Calculate the value of the CCC Exchange Timing Support Information Register. */ + uint32_t cetsm = (uint32_t) (p_extend->slave_command_response_info.oscillator_frequency << R_I3C0_CETSM_FREQ_Pos) & + R_I3C0_CETSM_FREQ_Msk; + cetsm |= (uint32_t) (p_extend->slave_command_response_info.oscillator_inaccuracy << R_I3C0_CETSM_INAC_Pos) & + R_I3C0_CETSM_INAC_Msk; + + uint32_t cmrlg = (uint32_t) p_extend->slave_command_response_info.read_length; + cmrlg |= (uint32_t) p_extend->slave_command_response_info.ibi_payload_length << R_I3C0_CMRLG_IBIPSZ_Pos; + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + uint32_t cghdrcap = (uint32_t) p_extend->slave_command_response_info.hdr_ddr_support; + cghdrcap |= (uint32_t) p_extend->slave_command_response_info.hdr_tsp_support << R_I3C0_CGHDRCAP_TSPEN_Pos; + cghdrcap |= (uint32_t) p_extend->slave_command_response_info.hdr_tsl_support << R_I3C0_CGHDRCAP_TSLEN_Pos; + #endif + + /* Write Slave Command Response Info. */ + p_ctrl->p_reg->CSECMD = csecmd; + p_ctrl->p_reg->CEACTST = (1U << p_extend->slave_command_response_info.activity_state); + p_ctrl->p_reg->CMWLG = (uint32_t) p_extend->slave_command_response_info.write_length; + p_ctrl->p_reg->CMRLG = cmrlg; + p_ctrl->p_reg->CGDVST = + (uint32_t) (p_extend->slave_command_response_info.activity_state << R_I3C0_CGDVST_ACTMD_Pos); + p_ctrl->p_reg->CMDSPW = (uint32_t) p_extend->slave_command_response_info.write_data_rate; + p_ctrl->p_reg->CMDSPR = cmdspr; + p_ctrl->p_reg->CMDSPT = cmdspt; + p_ctrl->p_reg->CETSM = cetsm; + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + p_ctrl->p_reg->CGHDRCAP = cghdrcap; + #endif +#endif + + /* Enable the I3C Bus. */ + p_ctrl->p_reg->BCTL |= R_I3C0_BCTL_BUSE_Msk; + + /* Enable the command response status buffer full IRQ. */ + R_BSP_IrqCfgEnable(p_extend->resp_irq, p_extend->ipl, p_ctrl); + + /* Enable the receive data buffer full IRQ. */ + R_BSP_IrqCfgEnable(p_extend->rx_irq, p_extend->ipl, p_ctrl); + + /* Enable the transmit data buffer empty IRQ. */ + R_BSP_IrqCfgEnable(p_extend->tx_irq, p_extend->ipl, p_ctrl); + +#if I3C_CFG_SLAVE_SUPPORT + + /* Enable the receive status buffer full IRQ. */ + R_BSP_IrqCfgEnable(p_extend->rcv_irq, p_extend->ipl, p_ctrl); +#endif + + /* Enable the IBI IRQ. */ + R_BSP_IrqCfgEnable(p_extend->ibi_irq, p_extend->ipl, p_ctrl); + + /* Enable the Error and Event IRQ. */ + R_BSP_IrqCfgEnable(p_extend->eei_irq, p_extend->eei_ipl, p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the configuration for this device. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_UNSUPPORTED The device cannot be a secondary master if master support is disabled. + **********************************************************************************************************************/ +fsp_err_t R_I3C_DeviceCfgSet (i3c_ctrl_t * const p_api_ctrl, i3c_device_cfg_t const * const p_device_cfg) +{ + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + +#if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_device_cfg); +#endif + +#if I3C_CFG_MASTER_SUPPORT + if (I3C_DEVICE_TYPE_MAIN_MASTER == p_ctrl->p_cfg->device_type) + { + /* + * Configure the master dynamic address and set it to valid (See Figure "I3C Communication Flow" + * in the I3C section of the relevant hardware manual). + */ + uint32_t msdvad = (uint32_t) p_device_cfg->dynamic_address << R_I3C0_MSDVAD_MDYAD_Pos; + msdvad |= R_I3C0_MSDVAD_MDYADV_Msk; + p_ctrl->p_reg->MSDVAD = msdvad; + } + else +#endif + { +#if I3C_CFG_SLAVE_SUPPORT + + /* Secondary master device role is not supported. */ + FSP_ERROR_RETURN(1U != p_device_cfg->slave_info.bcr_b.device_role, FSP_ERR_UNSUPPORTED); + + /* + * Configure slave device address table, Device Characteristics, Bus Characteristics, and + * Provisional ID (See Figure "I3C Communication Flow" in the I3C section of the relevant hardware manual). + * + * Configure the device static address. */ + uint32_t sdatbas0 = (uint32_t) p_device_cfg->static_address & R_I3C0_SDATBAS0_SDSTAD_Msk; + + /* Configure the device dynamic address. */ + sdatbas0 |= (uint32_t) (i3c_address_parity(p_device_cfg->dynamic_address) << R_I3C0_SDATBAS0_SDDYAD_Pos) & + R_I3C0_SDATBAS0_SDDYAD_Msk; + + /* Configure the IBI payload setting based on the BCR register. */ + sdatbas0 |= (uint32_t) (p_device_cfg->slave_info.bcr_b.ibi_payload << R_I3C0_SDATBAS0_SDIBIPL_Pos) & + R_I3C0_SDATBAS0_SDIBIPL_Msk; + + /* Set the slave address to valid. */ + p_ctrl->p_reg->SVCTL_b.SVAEn = 1; + + /* Write settings to the Slave Device Address Table Register. */ + p_ctrl->p_reg->SDATBAS0 = sdatbas0; + + /* Write the BCR and DCR settings to the Slave Device Characteristic Table Register. */ + uint32_t svdct = (uint32_t) p_device_cfg->slave_info.dcr; + svdct |= (uint32_t) p_device_cfg->slave_info.bcr << R_I3C0_SVDCT_TBCR0_Pos; + p_ctrl->p_reg->SVDCT = svdct; + + /* Write the PID setting to the Slave Device Characteristic Table PID Register. */ + uint8_t * pid = (uint8_t *) p_device_cfg->slave_info.pid; + p_ctrl->p_reg->SDCTPIDL = (uint32_t) ((pid[4] << 8U) | (pid[5])); + p_ctrl->p_reg->SDCTPIDH = (uint32_t) ((pid[0] << 24U) | + (pid[1] << 16U) | + (pid[2] << 8U) | + (pid[3] << 0U)); +#endif + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configure an entry in the master device table. This function is called in master mode in order to configure + * the devices on the I3C bus. It may also be called in slave mode when the slave receives the DEFSVLS command. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_UNSUPPORTED Mastership requests must be rejected is slave support is disabled. + **********************************************************************************************************************/ +fsp_err_t R_I3C_MasterDeviceTableSet (i3c_ctrl_t * const p_api_ctrl, + uint32_t device_index, + i3c_device_table_cfg_t const * const p_device_table_cfg) +{ +#if I3C_CFG_MASTER_SUPPORT + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + + #if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_device_table_cfg); + #endif + + /* The driver does not support accepting mastership requests. */ + FSP_ERROR_RETURN(!p_device_table_cfg->master_request_accept, FSP_ERR_UNSUPPORTED); + + uint32_t volatile * p_datbasn_reg = NULL; + uint32_t datbasn = 0; + + if (I3C_DEVICE_INDEX_EXTENDED_DEVICE == device_index) + { + p_datbasn_reg = &p_ctrl->p_reg->EXDATBAS; + } + else + { + /* Compute the address of the DATBASn register. */ + uint32_t address_offset = (uint32_t) (&p_ctrl->p_reg->DATBAS1 - &p_ctrl->p_reg->DATBAS0); + p_datbasn_reg = (uint32_t *) (&p_ctrl->p_reg->DATBAS0 + device_index * address_offset); + + /* Configure the IBI settings for this device. */ + datbasn |= (uint32_t) (p_device_table_cfg->ibi_payload << R_I3C0_DATBAS0_DVIBIPL_Pos) & + R_I3C0_DATBAS0_DVIBIPL_Msk; + datbasn |= (uint32_t) (!p_device_table_cfg->ibi_accept << R_I3C0_DATBAS0_DVSIRRJ_Pos) & + R_I3C0_DATBAS0_DVSIRRJ_Msk; + datbasn |= (uint32_t) (!p_device_table_cfg->master_request_accept << R_I3C0_DATBAS0_DVMRRJ_Pos) & + R_I3C0_DATBAS0_DVMRRJ_Msk; + } + + /* Configure the device static address. */ + datbasn |= (uint32_t) (p_device_table_cfg->static_address << R_I3C0_DATBAS0_DVSTAD_Pos) & R_I3C0_DATBAS0_DVSTAD_Msk; + + /* Configure the device dynamic address. */ + datbasn |= (uint32_t) (i3c_address_parity(p_device_table_cfg->dynamic_address) << R_I3C0_DATBAS0_DVDYAD_Pos) & + R_I3C0_DATBAS0_DVDYAD_Msk; + + if (I3C_DEVICE_PROTOCOL_I2C == p_device_table_cfg->device_protocol) + { + /* Set the device type so that transfers with this device use the legacy I2C protocol. */ + datbasn |= R_I3C0_DATBAS0_DVTYP_Msk; + } + + /* Write to the DATBASn register. */ + *p_datbasn_reg = datbasn; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(device_index); + FSP_PARAMETER_NOT_USED(p_device_table_cfg); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Set the status returned to the master in response to a GETSTATUS command. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_INVALID_MODE The instance is not in slave mode. + * @retval FSP_ERR_UNSUPPORTED Slave support is disabled. + **********************************************************************************************************************/ +fsp_err_t R_I3C_SlaveStatusSet (i3c_ctrl_t * const p_api_ctrl, i3c_device_status_t status) +{ +#if I3C_CFG_SLAVE_SUPPORT + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + + #if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* This function is only called in slave mode. */ + FSP_ERROR_RETURN( + I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state || I3C_INTERNAL_STATE_SLAVE_IBI == p_ctrl->internal_state, + FSP_ERR_INVALID_MODE); + #endif + + /* Clear the Pending Interrupt and Vendor Reserved fields. */ + uint32_t cgdvst = p_ctrl->p_reg->CGDVST; + cgdvst &= ~(R_I3C0_CGDVST_PNDINT_Msk | R_I3C0_CGDVST_VDRSV_Msk); + + /* Write the new Pending Interrupt and Vendor Reserved fields. */ + cgdvst |= (uint32_t) status.pending_interrupt & R_I3C0_CGDVST_PNDINT_Msk; + cgdvst |= (uint32_t) (status.vendor_status << R_I3C0_CGDVST_VDRSV_Pos) & R_I3C0_CGDVST_VDRSV_Msk; + + p_ctrl->p_reg->CGDVST = cgdvst; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(status); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * In master mode, select the device for the next transfer. + * This function is not used in slave mode. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_INVALID_MODE This operation is prohibited in slave mode. + * @retval FSP_ERR_UNSUPPORTED Master support is disabled. + **********************************************************************************************************************/ +fsp_err_t R_I3C_DeviceSelect (i3c_ctrl_t * const p_api_ctrl, uint32_t device_index, uint32_t bitrate_mode) +{ +#if I3C_CFG_MASTER_SUPPORT + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + + #if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #if BSP_FEATURE_I3C_HAS_HDR_MODE + FSP_ASSERT(I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR >= bitrate_mode); + #else + FSP_ASSERT(I3C_BITRATE_MODE_I3C_SDR4_EXTBR_X4 >= bitrate_mode); + #endif + FSP_ERROR_RETURN( + I3C_INTERNAL_STATE_SLAVE_IDLE != p_ctrl->internal_state && I3C_INTERNAL_STATE_DISABLED != p_ctrl->internal_state, + FSP_ERR_INVALID_MODE); + FSP_ASSERT(BSP_FEATURE_I3C_MAX_DEV_COUNT > device_index || + I3C_DEVICE_INDEX_EXTENDED_DEVICE == device_index); + #endif + + p_ctrl->device_index = device_index; + p_ctrl->device_bitrate_mode = (i3c_bitrate_mode_t) bitrate_mode; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(device_index); + FSP_PARAMETER_NOT_USED(bitrate_mode); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Start the Dynamic Address Assignment Process. Implements @ref i3c_api_t::dynamicAddressAssignmentStart. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_INVALID_MODE This operation is prohibited in slave mode. + * @retval FSP_ERR_IN_USE The operation could not be completed because the driver is busy. + * @retval FSP_ERR_UNSUPPORTED Master support is disabled. + **********************************************************************************************************************/ +fsp_err_t R_I3C_DynamicAddressAssignmentStart (i3c_ctrl_t * const p_api_ctrl, + i3c_address_assignment_mode_t address_assignment_mode, + uint32_t starting_device_index, + uint32_t device_count) +{ +#if I3C_CFG_MASTER_SUPPORT + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + + #if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN( + I3C_INTERNAL_STATE_SLAVE_IDLE != p_ctrl->internal_state && I3C_INTERNAL_STATE_DISABLED != p_ctrl->internal_state, + FSP_ERR_INVALID_MODE); + + FSP_ASSERT(BSP_FEATURE_I3C_MAX_DEV_COUNT > starting_device_index || + I3C_DEVICE_INDEX_EXTENDED_DEVICE == starting_device_index); + + if (I3C_ADDRESS_ASSIGNMENT_MODE_ENTDAA == address_assignment_mode) + { + if (I3C_DEVICE_INDEX_EXTENDED_DEVICE == starting_device_index) + { + /* When the extended device index is selected, the device count must be 1. */ + FSP_ASSERT(1U == device_count); + } + else + { + /* The device count must be less than the remaining devices in the device table. */ + FSP_ASSERT(BSP_FEATURE_I3C_MAX_DEV_COUNT > device_count + starting_device_index); + } + } + else + { + /* If the dynamic address is configured with SETDASA then the device count is not used and should be set to 0. */ + FSP_ASSERT(0U == device_count); + } + #endif + + /* Ensure that driver is in the idle state. */ + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state, FSP_ERR_IN_USE); + + p_ctrl->internal_state = I3C_INTERNAL_STATE_MASTER_ENTDAA; + + /* Set the transfer_data pointer to read the PID, DCR, and BCR registers for each device. */ + p_ctrl->read_buffer_descriptor.p_buffer = (uint8_t *) &p_ctrl->current_slave_info; + p_ctrl->read_buffer_descriptor.count = 0; + p_ctrl->read_buffer_descriptor.buffer_size = sizeof(i3c_slave_info_t); + + /* Setup the command descriptor to start the ENTDAA command starting at the selected device index. */ + uint32_t command_descriptor = 0; + command_descriptor |= (I3C_CMD_DESC_CMD_ATTR_ADDR_ASSGN_CMD << I3C_CMD_DESC_CMD_ATTR_Pos); + command_descriptor |= (uint32_t) (I3C_EVENT_ADDRESS_ASSIGNMENT_COMPLETE << I3C_CMD_DESC_TID_Pos); + command_descriptor |= (uint32_t) (address_assignment_mode << I3C_CMD_DESC_CMD_Pos); + command_descriptor |= (starting_device_index << I3C_CMD_DESC_DEV_INDEX_Pos); + command_descriptor |= (device_count << I3C_CMD_DESC_ADDR_ASSGN_DEV_COUNT_Pos); + command_descriptor |= I3C_CMD_DESC_ROC_Msk; + command_descriptor |= I3C_CMD_DESC_TOC_Msk; + + /* + * Write to the descriptor to the command queue. + * Note that the command descriptor is two words. The least significant word must be written first followed by + * the most significant word (See section "Command Descriptor" in the I3C Operation section of the relevant hardware manual). + */ + p_ctrl->p_reg->NCMDQP = command_descriptor; + p_ctrl->p_reg->NCMDQP = 0U; + + /* Clear the command queue empty flag. */ + p_ctrl->p_reg->NTST_b.CMDQEF = 0; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(address_assignment_mode); + FSP_PARAMETER_NOT_USED(starting_device_index); + FSP_PARAMETER_NOT_USED(device_count); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Send a broadcast or direct command to slave devices on the bus. Implements @ref i3c_api_t::commandSend. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_IN_USE The operation could not be completed because the driver is busy. + * @retval FSP_ERR_INVALID_MODE This driver is not in master mode. + * @retval FSP_ERR_INVALID_ALIGNMENT The buffer must be aligned to 4 bytes. If it is a read operation, the length + * also be a multiple of 4 bytes. + * @retval FSP_ERR_UNSUPPORTED Master support must be enabled to call this function. Slave support must be + * enabled when sending the GETACCMST command. + **********************************************************************************************************************/ +fsp_err_t R_I3C_CommandSend (i3c_ctrl_t * const p_api_ctrl, i3c_command_descriptor_t const * const p_command_descriptor) +{ +#if I3C_CFG_MASTER_SUPPORT + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + + #if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_command_descriptor); + if (p_command_descriptor->length > 0) + { + FSP_ASSERT(NULL != p_command_descriptor->p_buffer); + } + + FSP_ERROR_RETURN( + I3C_INTERNAL_STATE_SLAVE_IDLE != p_ctrl->internal_state && I3C_INTERNAL_STATE_DISABLED != p_ctrl->internal_state, + FSP_ERR_INVALID_MODE); + + #if !I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* Verify that the buffer is aligned to 4 bytes. */ + FSP_ERROR_RETURN(0U == ((uint32_t) p_command_descriptor->p_buffer & 0x03U), FSP_ERR_INVALID_ALIGNMENT); + #endif + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + if (I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR == p_ctrl->device_bitrate_mode) + { + /* Verify that length is a multiple of 2 in HDR modes. */ + FSP_ERROR_RETURN(p_command_descriptor->length % 2 == 0, FSP_ERR_INVALID_ALIGNMENT); + } + #endif + #endif + + /* The driver does not currently support relinquishing mastership to secondary masters. */ + FSP_ERROR_RETURN(I3C_CCC_DIRECT_GETACCMST != p_command_descriptor->command_code, FSP_ERR_UNSUPPORTED); + + /* Ensure that driver is in the idle state. */ + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state, FSP_ERR_IN_USE); + + /* Save the current command code. */ + p_ctrl->current_command_code = p_command_descriptor->command_code; + + i3c_read_buffer_descriptor_t * p_transfer_descriptor; + + #if I3C_CFG_SLAVE_SUPPORT + if (I3C_CCC_DIRECT_GETACCMST == p_command_descriptor->command_code) + { + /* Disable the IBI Write Buffer Empty/Full IRQ in case the driver transisitons to slave mode. */ + p_ctrl->p_reg->NTIE_b.IBIQEFIE = 0; + } + #endif + + if (p_command_descriptor->rnw) + { + /* If this is a read transfer, update the read buffer descriptor. */ + p_transfer_descriptor = &p_ctrl->read_buffer_descriptor; + p_transfer_descriptor->read_request_issued = false; + + p_ctrl->internal_state = I3C_INTERNAL_STATE_MASTER_COMMAND_READ; + } + else + { + /* If this is a write transfer, update the write buffer descriptor. */ + p_transfer_descriptor = (i3c_read_buffer_descriptor_t *) &p_ctrl->write_buffer_descriptor; + + p_ctrl->internal_state = I3C_INTERNAL_STATE_MASTER_COMMAND_WRITE; + } + + /* Update the buffer descriptor with the buffer provided in the command descriptor. */ + p_transfer_descriptor->p_buffer = p_command_descriptor->p_buffer; + p_transfer_descriptor->count = 0; + p_transfer_descriptor->buffer_size = p_command_descriptor->length; + + /* Calculate the command descriptor. */ + uint32_t cmd1 = 0; + cmd1 |= (p_ctrl->device_index << I3C_CMD_DESC_DEV_INDEX_Pos) & I3C_CMD_DESC_DEV_INDEX_Msk; + cmd1 |= ((uint32_t) p_ctrl->device_bitrate_mode << I3C_CMD_DESC_XFER_MODE_Pos) & I3C_CMD_DESC_XFER_MODE_Msk; + cmd1 |= (uint32_t) (p_command_descriptor->rnw << I3C_CMD_DESC_XFER_RNW_Pos); + cmd1 |= I3C_CMD_DESC_ROC_Msk; + cmd1 |= (uint32_t) (!p_command_descriptor->restart << I3C_CMD_DESC_TOC_Pos) & I3C_CMD_DESC_TOC_Msk; + cmd1 |= (uint32_t) (p_command_descriptor->command_code << I3C_CMD_DESC_CMD_Pos); + cmd1 |= I3C_CMD_DESC_XFER_CP_Msk; + cmd1 |= (uint32_t) (I3C_EVENT_COMMAND_COMPLETE << I3C_CMD_DESC_TID_Pos); + + uint32_t cmd2; + if ((4 >= p_command_descriptor->length) && !p_command_descriptor->rnw) + { + /* If the transfer length is less than or equal to 4 bytes, then use "Immediate Data Transfer". + * See section "Immediate Transfer Command" in the I3C section of the relevant hardware manual. */ + cmd1 |= I3C_CMD_DESC_CND_ATTR_IMMED_DATA_XFER; + cmd1 |= (p_command_descriptor->length << I3C_CMD_DESC_IMMED_DATA_XFER_BYTE_CNT_Pos); + cmd2 = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor); + p_ctrl->write_buffer_descriptor.count = p_command_descriptor->length; + } + else + { + cmd2 = (p_command_descriptor->length << I3C_CMD_DESC_XFER_LENGTH_Pos) & + I3C_CMD_DESC_XFER_LENGTH_Msk; + } + + /* + * Write the descriptor to the command queue. + * Note that the command descriptor is two words. The least significant word must be written first followed by + * the most significant word (See section "Command Descriptor" in the I3C Operation section of the relevant hardware manual). + */ + p_ctrl->p_reg->NCMDQP = cmd1; + p_ctrl->p_reg->NCMDQP = cmd2; + + /* Clear the command queue empty flag. */ + p_ctrl->p_reg->NTST_b.CMDQEF = 0; + + if (!p_command_descriptor->rnw && (4 < p_command_descriptor->length)) + { + /* Calculate the next data word that will be written to the FIFO. */ + p_ctrl->next_word = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor); + + /* Write data to the FIFO. */ + i3c_fifo_write(p_ctrl); + + /* If there is still data remaining in the transfer then it will be written in the Write Buffer Empty IRQ. */ + if ((BSP_FEATURE_I3C_NTDTBP0_DEPTH * sizeof(uint32_t)) < p_command_descriptor->length) + { + /* Enable the Write Buffer Empty IRQ. */ + p_ctrl->p_reg->NTIE_b.TDBEIE0 = 1; + } + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_command_descriptor); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Set the write buffer for the transfer. In master mode, start the transfer. When the transfer is completed send a + * stop condition or a repeated-start. Implements @ref i3c_api_t::write. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_IN_USE The operation could not be completed because the driver is busy. + * @retval FSP_ERR_INVALID_MODE This driver is disabled, or an invalid bitrate mode is selected. + * @retval FSP_ERR_INVALID_ALIGNMENT The buffer must be aligned to 4 bytes. + **********************************************************************************************************************/ +fsp_err_t R_I3C_Write (i3c_ctrl_t * const p_api_ctrl, uint8_t const * const p_data, uint32_t length, bool restart) +{ + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + +#if 0U == I3C_CFG_MASTER_SUPPORT + FSP_PARAMETER_NOT_USED(restart); +#endif + +#if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_DISABLED != p_ctrl->internal_state, FSP_ERR_INVALID_MODE); + #if !I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* Verify that the buffer is aligned to 4 bytes. */ + FSP_ERROR_RETURN(0U == ((uint32_t) p_data & 0x03U), FSP_ERR_INVALID_ALIGNMENT); + #endif + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + if (I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state) + { + /* In master mode, this function can only be called to start SDR and I2C transfers. */ + FSP_ERROR_RETURN(p_ctrl->device_bitrate_mode < I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR, FSP_ERR_INVALID_MODE); + } + #endif +#endif + +#if I3C_CFG_SLAVE_SUPPORT + if (I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state) + { + /* In slave mode, ensure that a write transfer is not currently in progress. */ + FSP_ERROR_RETURN(0U == (p_ctrl->p_reg->PRSST & R_I3C0_PRSST_TRMD_Msk), FSP_ERR_IN_USE); + } + else +#endif + { +#if I3C_CFG_MASTER_SUPPORT + + /* In master mode, ensure that driver is in the idle state. */ + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state, FSP_ERR_IN_USE); +#endif + } + + /* Set the internal transfer state for a write transfer. */ + p_ctrl->write_buffer_descriptor.count = 0; + p_ctrl->write_buffer_descriptor.buffer_size = length; + p_ctrl->write_buffer_descriptor.p_buffer = (uint8_t *) p_data; + + /* Calculate the next data word that will be written to the FIFO. */ + p_ctrl->next_word = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor); + +#if I3C_CFG_SLAVE_SUPPORT + if (I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state) + { + if (p_ctrl->write_buffer_descriptor.p_buffer != NULL) + { + /* + * If a write buffer has already been configured, then the FIFO needs to be reset before the new data + * can be written. + */ + p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_TDBRST_Msk; + + /* The field will be cleared automatically upon reset completion (See "RSTCTL : Reset Control Register" description in the I3C section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U); + } + + /* Configure the number of bytes that the slave will write before ending the transfer via the T bit. */ + p_ctrl->p_reg->SVTDLG0 = (length << 16U); + } +#endif + + if ((length > 4) || (I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state)) + { + /* Write data to the FIFO. Note that in master mode, if the legnth is less than or equal to 4 bytes, + * the "Immediate Data Transfer" command must be used instead of the "Regular Transfer" command. */ + i3c_fifo_write(p_ctrl); + + /* If there is still data remaining in the transfer then it will be written in the Write Buffer Empty IRQ. */ + if ((BSP_FEATURE_I3C_NTDTBP0_DEPTH * sizeof(uint32_t)) < length) + { + /* Enable the Write Buffer Empty IRQ. */ + p_ctrl->p_reg->NTIE_b.TDBEIE0 = 1; + } + } + +#if I3C_CFG_MASTER_SUPPORT + if (I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state) + { + p_ctrl->internal_state = I3C_INTERNAL_STATE_MASTER_WRITE; + + /* + * Write the descriptor to the command queue. + * Note that the command descriptor is two words. The least significant word must be written first followed by + * the most significant word (See section "Command Descriptor" in the I3C Operation section of the relevant hardware manual). + */ + uint32_t cmd1 = i3c_xfer_command_calculate(p_ctrl->device_index, false, p_ctrl->device_bitrate_mode, restart); + + uint32_t cmd2; + if (length <= 4) + { + /* If the transfer length is less than or equal to 4 bytes, then use "Immediate Data Transfer". + * See section "Immediate Transfer Command" in the I3C section of the relevant hardware manual. */ + cmd1 |= I3C_CMD_DESC_CND_ATTR_IMMED_DATA_XFER; + cmd1 |= (length << I3C_CMD_DESC_IMMED_DATA_XFER_BYTE_CNT_Pos); + cmd2 = p_ctrl->next_word; + p_ctrl->write_buffer_descriptor.count = length; + } + else + { + cmd2 = (length << I3C_CMD_DESC_XFER_LENGTH_Pos) & I3C_CMD_DESC_XFER_LENGTH_Msk; + } + + p_ctrl->p_reg->NCMDQP = cmd1; + p_ctrl->p_reg->NCMDQP = cmd2; + + /* Clear the command queue empty flag. */ + p_ctrl->p_reg->NTST_b.CMDQEF = 0; + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the read buffer for the transfer. In master mode, start the transfer. When the transfer is completed send a + * stop condition or a repeated-start. Implements @ref i3c_api_t::read. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_IN_USE The operation could not be completed because the driver is busy. + * @retval FSP_ERR_INVALID_MODE This driver is disabled, or an invalid bitrate mode is selected. + * @retval FSP_ERR_INVALID_ALIGNMENT The buffer must be aligned to 4 bytes and the length must be a multiple of + * 4 bytes. + **********************************************************************************************************************/ +fsp_err_t R_I3C_Read (i3c_ctrl_t * const p_api_ctrl, uint8_t * const p_data, uint32_t length, bool restart) +{ + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + +#if 0U == I3C_CFG_MASTER_SUPPORT + FSP_PARAMETER_NOT_USED(restart); +#endif + +#if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_DISABLED != p_ctrl->internal_state, FSP_ERR_INVALID_MODE); + #if !I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* The buffer must be 4 byte aligned. */ + FSP_ERROR_RETURN(0U == ((uint32_t) p_data & 0x03U), FSP_ERR_INVALID_ALIGNMENT); + + if (I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state) + { + /* The buffer size must be a multiple of 4 bytes in slave mode. */ + FSP_ERROR_RETURN(0U == ((uint32_t) length & 0x03U), FSP_ERR_INVALID_ALIGNMENT); + } + #endif + + #if BSP_FEATURE_I3C_HAS_HDR_MODE + if (I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state) + { + /* In master mode, this function can only be called to start SDR and I2C transfers. */ + FSP_ERROR_RETURN(p_ctrl->device_bitrate_mode < I3C_BITRATE_MODE_I3C_HDR_DDR_STDBR, FSP_ERR_INVALID_MODE); + } + #endif +#endif + + /* In Master mode, ensure that driver is in the idle state. */ + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state || + I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state, + FSP_ERR_IN_USE); + + i3c_extended_cfg_t const * p_extend = (i3c_extended_cfg_t const *) p_ctrl->p_cfg->p_extend; + + /* Disable the Receive Buffer Full IRQ in order to ensure that updating the read buffer state is not interrupted. */ + R_BSP_IrqDisable(p_extend->rx_irq); + + /* Set the internal transfer state for a read transfer. */ + p_ctrl->read_buffer_descriptor.count = 0; + p_ctrl->read_buffer_descriptor.buffer_size = length; + p_ctrl->read_buffer_descriptor.p_buffer = p_data; + p_ctrl->read_buffer_descriptor.read_request_issued = false; + + R_BSP_IrqEnableNoClear(p_extend->rx_irq); + +#if I3C_CFG_MASTER_SUPPORT + if (I3C_INTERNAL_STATE_MASTER_IDLE == p_ctrl->internal_state) + { + p_ctrl->internal_state = I3C_INTERNAL_STATE_MASTER_READ; + + /* + * Write the descriptor to the command queue. + * Note that the command descriptor is two words. The least significant word must be written first followed by + * the most significant word (See section "Command Descriptor" in the I3C Operation section of the relevant hardware manual). + */ + p_ctrl->p_reg->NCMDQP = i3c_xfer_command_calculate(p_ctrl->device_index, + true, + p_ctrl->device_bitrate_mode, + restart); + p_ctrl->p_reg->NCMDQP = (length << I3C_CMD_DESC_XFER_LENGTH_Pos) & I3C_CMD_DESC_XFER_LENGTH_Msk; + + /* Clear the command queue empty flag. */ + p_ctrl->p_reg->NTST_b.CMDQEF = 0; + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Initiate an IBI write operation (This function is only used in slave mode). + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_IN_USE The operation could not be completed because the driver is busy. + * @retval FSP_ERR_INVALID_MODE This function is only called in slave mode. + * @retval FSP_ERR_INVALID_ALIGNMENT The buffer must be aligned to 4 bytes. + * @retval FSP_ERR_UNSUPPORTED Slave supoprt is disabled. + **********************************************************************************************************************/ +fsp_err_t R_I3C_IbiWrite (i3c_ctrl_t * const p_api_ctrl, + i3c_ibi_type_t ibi_type, + uint8_t const * const p_data, + uint32_t length) +{ +#if I3C_CFG_SLAVE_SUPPORT + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + #if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* If the device has an IBI payload, then a buffer is required. */ + if ((I3C_IBI_TYPE_INTERRUPT == ibi_type) && (0 != (R_I3C0_SDATBAS0_SDIBIPL_Msk & p_ctrl->p_reg->SDATBAS0))) + { + FSP_ASSERT(NULL != p_data); + FSP_ASSERT(0 != length); + } + + /* This function is only called in slave mode. */ + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state, FSP_ERR_INVALID_MODE); + + #if !I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* The buffer must be 4 byte aligned. */ + FSP_ERROR_RETURN(0U == ((uint32_t) p_data & 0x03U), FSP_ERR_INVALID_ALIGNMENT); + #endif + #endif + + /* An IBI can't be started if an IBI is already in progress. */ + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_SLAVE_IBI != p_ctrl->internal_state, FSP_ERR_IN_USE); + + p_ctrl->internal_state = I3C_INTERNAL_STATE_SLAVE_IBI; + + /* Setup the buffer for writing the data portion of the IBI. */ + p_ctrl->ibi_buffer_descriptor.p_buffer = (uint8_t *) p_data; + p_ctrl->ibi_buffer_descriptor.count = 0; + p_ctrl->ibi_buffer_descriptor.buffer_size = length; + + /* Calculate the command descriptor for starting an IBI. */ + uint32_t command_descriptor = 0; + command_descriptor |= I3C_CMD_DESC_ROC_Msk; + command_descriptor |= (I3C_EVENT_IBI_WRITE_COMPLETE << I3C_CMD_DESC_TID_Pos); + + if (I3C_IBI_TYPE_HOT_JOIN == ibi_type) + { + command_descriptor |= I3C_CMD_DESC_XFER_HJ_Msk; + } + else if (I3C_IBI_TYPE_INTERRUPT == ibi_type) + { + command_descriptor |= I3C_CMD_DESC_XFER_RNW_Msk; + } + else + { + /* Mastership request. */ + } + + if (0 < length) + { + /* Write the data to the IBI queue. */ + p_ctrl->p_reg->NIBIQP = i3c_next_data_word_calculate( + (i3c_write_buffer_descriptor_t *) &p_ctrl->ibi_buffer_descriptor); + + if (sizeof(uint32_t) < length) + { + /* If the transfer length is greater than 4 bytes, then prepare the next word to be written to the FIFO. */ + p_ctrl->ibi_next_word = i3c_next_data_word_calculate( + (i3c_write_buffer_descriptor_t *) &p_ctrl->ibi_buffer_descriptor); + + /* Enable the IBI Write Buffer Empty/Full IRQ. */ + p_ctrl->p_reg->NTIE_b.IBIQEFIE = 1; + } + + /* Clear the IBI Queue Empty/Full Flag (This will generate an IBI IRQ). */ + p_ctrl->p_reg->NTST_b.IBIQEFF = 0; + } + + /* + * Write the descriptor to the command queue. + * Note that the command descriptor is two words. The least significant word must be written first followed by + * the most significant word (See section "Command Descriptor" in the I3C Operation section of the relevant hardware manual). + */ + p_ctrl->p_reg->NCMDQP = command_descriptor; + p_ctrl->p_reg->NCMDQP = (length << I3C_CMD_DESC_XFER_LENGTH_Pos) & I3C_CMD_DESC_XFER_LENGTH_Msk; + + /* Clear the command queue empty flag. */ + p_ctrl->p_reg->NTST_b.CMDQEF = 0; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(ibi_type); + FSP_PARAMETER_NOT_USED(p_data); + FSP_PARAMETER_NOT_USED(length); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Set the read buffer for storing received IBI data (This function is only used in master mode). + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + * @retval FSP_ERR_INVALID_MODE This function is only called in master mode. + * @retval FSP_ERR_INVALID_ALIGNMENT The buffer must be aligned to 4 bytes and the length must be a multiple of + * 4 bytes. + * @retval FSP_ERR_UNSUPPORTED Master support is disabled. + **********************************************************************************************************************/ +fsp_err_t R_I3C_IbiRead (i3c_ctrl_t * const p_api_ctrl, uint8_t * const p_data, uint32_t length) +{ +#if I3C_CFG_MASTER_SUPPORT + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + + #if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_data); + FSP_ASSERT(0 != length); + + /* This function is not used in slave mode. */ + FSP_ERROR_RETURN(I3C_INTERNAL_STATE_SLAVE_IDLE != p_ctrl->internal_state && + I3C_INTERNAL_STATE_SLAVE_IBI != p_ctrl->internal_state && + I3C_INTERNAL_STATE_DISABLED != p_ctrl->internal_state, + FSP_ERR_INVALID_MODE); + + #if !I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* The buffer must be 4 byte aligned. */ + FSP_ERROR_RETURN(0U == ((uint32_t) p_data & 0x03U), FSP_ERR_INVALID_ALIGNMENT); + + /* The buffer size must be a multiple of 4 bytes. */ + FSP_ERROR_RETURN(0U == ((uint32_t) length & 0x03U), FSP_ERR_INVALID_ALIGNMENT); + #endif + #endif + + i3c_extended_cfg_t const * p_extend = (i3c_extended_cfg_t const *) p_ctrl->p_cfg->p_extend; + + /* Disable the IBI Buffer Full IRQ in order to ensure that updating the IBI buffer state is not interrupted. */ + R_BSP_IrqDisable(p_extend->ibi_irq); + + p_ctrl->ibi_buffer_descriptor.p_buffer = p_data; + p_ctrl->ibi_buffer_descriptor.count = 0; + p_ctrl->ibi_buffer_descriptor.buffer_size = length; + p_ctrl->ibi_buffer_descriptor.read_request_issued = false; + + R_BSP_IrqEnableNoClear(p_extend->ibi_irq); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_data); + FSP_PARAMETER_NOT_USED(length); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Close the I3C instance. Implements @ref i3c_api_t::close. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_NOT_OPEN This instance has not been opened yet. + **********************************************************************************************************************/ +fsp_err_t R_I3C_Close (i3c_ctrl_t * const p_api_ctrl) +{ + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) p_api_ctrl; + +#if I3C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(I3C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + i3c_extended_cfg_t * p_extend = (i3c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Disable IRQs. */ + R_BSP_IrqDisable(p_extend->resp_irq); + R_BSP_IrqDisable(p_extend->rx_irq); + R_BSP_IrqDisable(p_extend->tx_irq); + R_BSP_IrqDisable(p_extend->rcv_irq); + R_BSP_IrqDisable(p_extend->ibi_irq); + + /* Reset the I3C Peripheral so that it is in a known state. */ + p_ctrl->p_reg->BCTL_b.BUSE = 0; + p_ctrl->p_reg->RSTCTL = 1U; + + /* The field will be cleared automatically upon reset completion (See "RSTCTL : Reset Control Register" description in the I3C section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U); + + /* Set the I3C Module Stop bit. */ + R_BSP_MODULE_STOP(FSP_IP_I3C, p_ctrl->p_cfg->channel); + + p_ctrl->open = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup I3C) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Compute the odd parity of an I3C address and set the parity bit. + * @param[in] address Number of loops to check bit (at least 1 us per loop). + * + * @return The address with the parity bit set. + **********************************************************************************************************************/ +static uint8_t i3c_address_parity (uint8_t address) +{ + /* Compute the parity of the dynamic address. */ + uint32_t parity = address; + + /* XOR the upper 4 bits with the lower 4 bits. */ + parity ^= (parity >> 4); + + /* XOR the upper 2 bits of the result with the lower 2 bits. */ + parity ^= (parity >> 2); + + /* XOR the upper bit of the result with the lower bit. */ + parity ^= (parity >> 1); + + /* The result of XOR of all bits is stored in the LSB. */ + parity &= 1; + + /* The ODD parity will be the inverse of the even parity. */ + parity = !parity; + + return (uint8_t) (address | (parity << 7)); +} + +#if I3C_CFG_MASTER_SUPPORT + +/*******************************************************************************************************************//** + * Setup the command descriptor for a read or write transfer to the selected device. + * + * @param[in] dev_index The selected index for the transfer. + * @param[in] rnw Read not write. + * @param[in] bitrate_setting The bitrate setting (See @ref i3c_bitrate_mode_t). + * @param[in] restart Terminate the transfer with a repeated start condition. + * + * @return The calculated value for the command descriptor. + **********************************************************************************************************************/ +static uint32_t i3c_xfer_command_calculate (uint32_t dev_index, bool rnw, uint32_t bitrate_setting, bool restart) +{ + uint32_t command_descriptor = 0; + if (rnw) + { + command_descriptor |= (I3C_EVENT_READ_COMPLETE << I3C_CMD_DESC_TID_Pos); + } + else + { + command_descriptor |= (I3C_EVENT_WRITE_COMPLETE << I3C_CMD_DESC_TID_Pos); + } + + command_descriptor |= (dev_index << I3C_CMD_DESC_DEV_INDEX_Pos) & I3C_CMD_DESC_DEV_INDEX_Msk; + command_descriptor |= (bitrate_setting << I3C_CMD_DESC_XFER_MODE_Pos) & I3C_CMD_DESC_XFER_MODE_Msk; + command_descriptor |= (uint32_t) (rnw << I3C_CMD_DESC_XFER_RNW_Pos); + command_descriptor |= I3C_CMD_DESC_ROC_Msk; + command_descriptor |= (uint32_t) (!restart << I3C_CMD_DESC_TOC_Pos) & I3C_CMD_DESC_TOC_Msk; + + return command_descriptor; +} + +#endif + +/*******************************************************************************************************************//** + * Read data from the Normal Transfer Data Buffer and write it into the user provided data buffer. + * @param[in] p_ctrl Pointer to an instance's control structure. + * @param[in] bytes The number of bytes to read from the FIFO. + **********************************************************************************************************************/ +static inline void i3c_fifo_read (i3c_instance_ctrl_t * p_ctrl, uint32_t bytes) +{ + int bytes_remaining = (int) bytes; + while (bytes_remaining > 0) + { + /* Each entry in the FIFO is 4 bytes. */ + uint32_t rx_data = p_ctrl->p_reg->NTDTBP0; + + /* Clear the Read Buffer Full status flag. */ + p_ctrl->p_reg->NTST_b.RDBFF0 = 0; + + /* + * Store the next word of data into the read buffer. If there is not enough space, a I3C_EVENT_READ_BUFFER_FULL + * event will be called to notify the application that a new read buffer is required. + */ + i3c_read_buffer_store(p_ctrl, + &p_ctrl->read_buffer_descriptor, + rx_data, + (uint32_t) bytes_remaining, + I3C_EVENT_READ_BUFFER_FULL); + + bytes_remaining -= 4; + + p_ctrl->read_transfer_count_final += 4; + } +} + +/*******************************************************************************************************************//** + * Write a word of data read from a FIFO into the read buffer. + * + * @param[in] p_ctrl Pointer to an instance's control structure. + * @param[in] p_buffer_descriptor Pointer to a read buffer descriptor for storing the word of data. + * @param[in] data_word Word of data read from a FIFO. + * @param[in] num_bytes The number of valid data bytes in the data word. + * @param[in] buffer_full_event The event to notify that application when their is no more space available in the + * buffer descriptor. + **********************************************************************************************************************/ +static inline void i3c_read_buffer_store (i3c_instance_ctrl_t * const p_ctrl, + i3c_read_buffer_descriptor_t * p_buffer_descriptor, + uint32_t data_word, + uint32_t num_bytes, + i3c_event_t buffer_full_event) +{ +#if !I3C_CFG_UNALIGNED_BUFFER_SUPPORT + FSP_PARAMETER_NOT_USED(num_bytes); +#endif + +#if I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* If unaligned buffers are supported, the word must be written one byte at a time. */ + for (uint32_t i = 0; i < sizeof(uint32_t) && i < num_bytes; i++) + { +#endif + + /* Check if the buffer descriptor has space available. */ + if (p_buffer_descriptor->count >= p_buffer_descriptor->buffer_size) + { + /* If there is no more space available, and the driver already notified the application, + * then discard the data. */ + if (p_buffer_descriptor->read_request_issued) + { + return; + } + + i3c_callback_args_t callback_args = + { + .event = buffer_full_event, + .p_context = p_ctrl->p_cfg->p_context, + }; + + /* Update the buffer descriptor state so that it will not notify the application again until a new buffer + * is provided. */ + p_buffer_descriptor->read_request_issued = true; + + /* Notify the application that the read buffer is full. */ + p_ctrl->p_cfg->p_callback(&callback_args); + + /* If the application didn't provide a new read buffer, then discard the data. */ + if (p_buffer_descriptor->read_request_issued) + { + return; + } + } + +#if I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* Write the data to the read buffer one byte at a time. */ + p_buffer_descriptor->p_buffer[p_buffer_descriptor->count++] = (uint8_t) (data_word >> (i * 8U)) & UINT8_MAX; +} +#endif + +#if !I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* Write the data to the read buffer one word at a time. */ + *((uint32_t *) &p_buffer_descriptor->p_buffer[p_buffer_descriptor->count]) = data_word; + p_buffer_descriptor->count += 4; +#endif +} + +/*******************************************************************************************************************//** + * Calculate the number of bytes left in the FIFO at the end of a transfer. If the buffer is aligned, then it is safe + * to assume that the bytes remaining is a multiple of 4 bytes. + * + * @param[in] p_ctrl Pointer to an instance's control structure. + * @param[in] data_length The total transfer length read from a status descriptor. + **********************************************************************************************************************/ +static inline uint32_t i3c_read_bytes_remaining_calculate (i3c_instance_ctrl_t * p_ctrl, uint32_t data_length) +{ + uint32_t bytes_remaining = 0; + if (p_ctrl->p_reg->NDBSTLV0_b.RDBLV > 0) + { + bytes_remaining = data_length - p_ctrl->read_transfer_count_final; + } + + return bytes_remaining; +} + +/*******************************************************************************************************************//** + * Fill the transmit FIFO with data from a write buffer descriptor. If there is no more data in the write buffer, + * then disable the transmit IRQ, and return. + * + * @param[in] p_ctrl Pointer to an instance's control structure. + * + * Note: this function must be inlined to reduce i3c_tx_isr processing time. + **********************************************************************************************************************/ +BSP_FORCE_INLINE static inline void i3c_fifo_write (i3c_instance_ctrl_t * p_ctrl) +{ + do + { + /* Write data to the transmit FIFO. */ + p_ctrl->p_reg->NTDTBP0 = p_ctrl->next_word; + + /* If there is no more data to write, disable the transmit IRQ and return. */ + if (p_ctrl->write_buffer_descriptor.count >= p_ctrl->write_buffer_descriptor.buffer_size) + { + p_ctrl->p_reg->NTIE_b.TDBEIE0 = 0; + i3c_extended_cfg_t * p_extend = (i3c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + R_BSP_IrqClearPending(p_extend->tx_irq); + break; + } + + /* Calculate the next word of data to write to the FIFO. */ + p_ctrl->next_word = i3c_next_data_word_calculate(&p_ctrl->write_buffer_descriptor); + + /* Continue writing data until the transmit FIFO is full. */ + } while ((p_ctrl->p_reg->NDBSTLV0 & UINT8_MAX)); + + /* Clear the Transmit Buffer Empty status flag. */ + p_ctrl->p_reg->NTST_b.TDBEF0 = 0; +} + +/*******************************************************************************************************************//** + * Compute the value of the next data word in a write transfer. + * + * @param[in] p_buffer_descriptor Pointer to a write buffer descriptor. + * + * Note: this function must be inlined to reduce i3c_tx_isr processing time. + **********************************************************************************************************************/ +BSP_FORCE_INLINE static inline uint32_t i3c_next_data_word_calculate ( + i3c_write_buffer_descriptor_t * p_buffer_descriptor) +{ + uint32_t data_word = 0; + + /* Read the current transfer count. */ + uint32_t count = p_buffer_descriptor->count; + uint8_t const * p_transfer_data = p_buffer_descriptor->p_buffer; + +#if I3C_CFG_UNALIGNED_BUFFER_SUPPORT + + /* Compute the value of the next data word that will be written. */ + for (uint32_t i = 0; i < sizeof(uint32_t) && count < p_buffer_descriptor->buffer_size; i++) + { + /* If there is no more data to write, then exit. */ + data_word |= (uint32_t) (p_transfer_data[count++] << (i * 8)); + } + +#else + + /* If the buffer is aligned, then read the data from the buffer using a word access. */ + data_word = *((uint32_t *) (&p_transfer_data[count])); + count += 4; +#endif + + /* Update the transfer count. */ + p_buffer_descriptor->count = count; + + return data_word; +} + +/*******************************************************************************************************************//** + * Get the control instance associated with the active IRQ. + **********************************************************************************************************************/ +static inline i3c_ctrl_t * i3c_isr_context_get (void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + i3c_instance_ctrl_t * p_ctrl = (i3c_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + R_BSP_IrqStatusClear(irq); + + return p_ctrl; +} + +/*******************************************************************************************************************//** + * ISR for handling the Command Response IRQ. The Command Response IRQ occurs on completion of a command and + * provides status information. + **********************************************************************************************************************/ +void i3c_resp_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + i3c_instance_ctrl_t * p_ctrl = i3c_isr_context_get(); + + /* Get the response status from the Response Status Queue. */ + uint32_t response_status_descriptor = p_ctrl->p_reg->NRSPQP; + + /* Clear the Response Queue Full status flag. */ + p_ctrl->p_reg->NTST_b.RSPQFF = 0; + + /* Read the DATA_LENGTH field in the response descriptor. */ + uint32_t data_length = (response_status_descriptor & I3C_RESP_STATUS_DESC_DATA_LENGTH_Msk) >> + I3C_RESP_STATUS_DESC_DATA_LENGTH_Pos; + + /* Read the ERR_STATUS field in the response descriptor. */ + uint32_t err_status = (response_status_descriptor & I3C_RESP_STATUS_DESC_ERR_STATUS_Msk) >> + I3C_RESP_STATUS_DESC_ERR_STATUS_Pos; + + bool error_recovery_case_2 = false; + + uint32_t internal_state = p_ctrl->internal_state; + + i3c_callback_args_t callback_args; + callback_args.event = (i3c_event_t) (internal_state & I3C_INTERNAL_EVENT_MASK); + callback_args.event_status = err_status; + callback_args.p_context = p_ctrl->p_cfg->p_context; + + p_ctrl->internal_state = I3C_INTERNAL_STATE_MASTER_IDLE; + + switch (internal_state) + { +#if I3C_CFG_MASTER_SUPPORT + case I3C_INTERNAL_STATE_MASTER_ENTDAA: + { + /* Reset the read buffer descriptor that was used to read the slave info. */ + p_ctrl->read_buffer_descriptor = (i3c_read_buffer_descriptor_t) { + 0 + }; + + break; + } + + case I3C_INTERNAL_STATE_MASTER_WRITE: + case I3C_INTERNAL_STATE_MASTER_COMMAND_WRITE: + { + /* Calculate the total transfer length. Note that for a write transfer, the DATA_LENGTH field in the response + * descriptor provides the number of bytes remaining. */ + callback_args.transfer_size = p_ctrl->write_buffer_descriptor.buffer_size - data_length; + + /* Reset the write buffer descriptor that was used for the transfer. */ + p_ctrl->write_buffer_descriptor = (i3c_write_buffer_descriptor_t) { + 0 + }; + + /* Disable the transmit IRQ if it hasn't been disabled already. */ + p_ctrl->p_reg->NTIE_b.TDBEIE0 = 0; + i3c_extended_cfg_t * p_extend = (i3c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + R_BSP_IrqClearPending(p_extend->tx_irq); + + break; + } + + case I3C_INTERNAL_STATE_MASTER_READ: + case I3C_INTERNAL_STATE_MASTER_COMMAND_READ: + { + uint32_t bytes_remaining = i3c_read_bytes_remaining_calculate(p_ctrl, data_length); + + /* Read the remaining byte stored in the FIFO. */ + i3c_fifo_read(p_ctrl, bytes_remaining); + + #if I3C_ERROR_RECOVERY_VERSION_1 == I3C_CFG_ERROR_RECOVERY_SUPPORT || \ + I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + if (1U == I3C_A2E2_VERSION) + #endif + { + /* If the transfer length is less than expected, the driver must perform error recovery defined in + * See figure "Example of error recovery operation flowchart for I3C master" in the I3C section of the + * relevant hardware manual. */ + if (data_length != p_ctrl->read_buffer_descriptor.buffer_size) + { + error_recovery_case_2 = true; + } + } + #endif + + /* + * For a read transfer, the DATA_LENGTH field in the response descriptor provides the total number of bytes + * read. + */ + callback_args.transfer_size = data_length; + + /* Reset the read buffer descriptor that was used for the read transfer. */ + p_ctrl->read_buffer_descriptor = (i3c_read_buffer_descriptor_t) { + 0 + }; + #if I3C_CFG_SLAVE_SUPPORT + if (I3C_CCC_DIRECT_GETACCMST == p_ctrl->current_command_code) + { + if (0U == (p_ctrl->p_reg->PRSST & R_I3C0_PRSST_CRMS_Msk)) + { + /* If the GETACCMST command was successful, transition the driver to slave mode. */ + p_ctrl->internal_state = I3C_INTERNAL_STATE_SLAVE_IDLE; + + /* + * Configure IBI queue threshold so that an IBI IRQ is generated when there is one empty entry in the + * IBI transmit FIFO. + */ + p_ctrl->p_reg->NQTHCTL_b.IBIQTH = 1; + } + else + { + /* If the command was not successful, re-enable the IBI Write Buffer Empty/Full IRQ. */ + p_ctrl->p_reg->NTIE_b.IBIQEFIE = 1; + } + } + #endif + + p_ctrl->current_command_code = 0; + break; + } +#endif + +#if I3C_CFG_SLAVE_SUPPORT + case I3C_INTERNAL_STATE_SLAVE_IBI: + { + /* Calculate the total transfer length. Note that for an IBI transfer, the DATA_LENGTH field in the response + * descriptor provides the number of bytes remaining. */ + callback_args.transfer_size = p_ctrl->ibi_buffer_descriptor.buffer_size - data_length; + + /* Reset the buffer descriptor that was used for the IBI transfer. */ + p_ctrl->ibi_buffer_descriptor = (i3c_read_buffer_descriptor_t) { + 0 + }; + + p_ctrl->internal_state = I3C_INTERNAL_STATE_SLAVE_IDLE; + } +#endif + default: + { + break; + } + } + + /* Reset the total bytes read. */ + p_ctrl->read_transfer_count_final = 0; + + uint32_t ntst = p_ctrl->p_reg->NTST; + + /* + * If the transfer was aborted, then the abort flag must be cleared before notifying the application + * that a transfer has completed. + */ + if (0 != (ntst & R_I3C0_NTST_TABTF_Msk)) + { + p_ctrl->p_reg->BCTL_b.ABT = 0; + } + + /* If a transfer error occurs, follow the error recovery operation defined in Figures "Example of error recovery operation flowchart for I3C master" + * and "Example of error recovery operation flowchart for I3C slave" in the I3C section of the relevant hardware manual. */ + if ((0 != (ntst & R_I3C0_NTST_TEF_Msk)) || error_recovery_case_2) + { +#if I3C_CFG_SLAVE_SUPPORT + if (I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state) + { + i3c_slave_error_recovery(p_ctrl, I3C_SLAVE_ERROR_RECOVERY_TYPE_IBI); + } + else +#endif + { +#if I3C_CFG_MASTER_SUPPORT + i3c_master_error_recovery(p_ctrl, error_recovery_case_2); +#endif + } + } + + /* Clear error status flags. */ + p_ctrl->p_reg->NTST &= ~(R_I3C0_NTST_TEF_Msk | R_I3C0_NTST_TABTF_Msk); + + /* Notify the application of the event. */ + p_ctrl->p_cfg->p_callback(&callback_args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR for handling the Receive Buffer Full IRQ. The Receive Buffer Full IRQ is generated when the number of entries + * in the Receive Data Buffer is greater than or equal to the configured threshold. + **********************************************************************************************************************/ +void i3c_rx_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + i3c_instance_ctrl_t * p_ctrl = i3c_isr_context_get(); + + /* + * If the transfer is complete, the remainder of the Read Data FIFO must be read in the Receive Status Queue Full, + * or Response Status Queue Full ISRs. + * + * This is because in order to read the remaining data, the driver must know exactly how many total bytes were read + * during the transfer. + */ + if (0 == (p_ctrl->p_reg->NTST & (R_I3C0_NTST_RSQFF_Msk | R_I3C0_NTSTE_RSPQFE_Msk))) + { + i3c_fifo_read(p_ctrl, p_ctrl->p_reg->NDBSTLV0_b.RDBLV * sizeof(uint32_t)); + } + +#if I3C_CFG_MASTER_SUPPORT + if (I3C_INTERNAL_STATE_MASTER_ENTDAA == p_ctrl->internal_state) + { + /* The address phase during ENTDAA occurs after 8 bytes (PID, BCR, and DCR) are read. */ + if (8U == p_ctrl->read_buffer_descriptor.count) + { + /* Reset the data pointer after reading each device PID, BCR, and DCR. */ + p_ctrl->read_buffer_descriptor.count = 0; + + /* Notify the applciation that the ENTDAA Address Phase has started. */ + i3c_callback_args_t callback_args; + callback_args.event = I3C_EVENT_ENTDAA_ADDRESS_PHASE; + callback_args.p_slave_info = &p_ctrl->current_slave_info; + callback_args.p_context = p_ctrl->p_cfg->p_context; + + p_ctrl->p_cfg->p_callback(&callback_args); + } + } +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR for handling the Transmit Buffer Empty IRQ. The Transmit Buffer Empty IRQ is generated when the number of + * empties in the Transmit Data Buffer is greater than or equal to the threshold. + **********************************************************************************************************************/ +void i3c_tx_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + i3c_instance_ctrl_t * p_ctrl = i3c_isr_context_get(); + + /* Write data to the FIFO. */ + i3c_fifo_write(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR for handling the Receive Status Buffer Full IRQ. The Receive Status Buffer Full IRQ is generated when the + * number of Receive Status Queue entries is greater than the threshold. + **********************************************************************************************************************/ +void i3c_rcv_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + +#if I3C_CFG_SLAVE_SUPPORT + i3c_instance_ctrl_t * p_ctrl = i3c_isr_context_get(); + + /* Get the receive status descriptor for the Receive Status Queue. */ + uint32_t receive_status_descriptor = p_ctrl->p_reg->NRSQP; + + /* Clear the Receive Status Queue Full Flag. */ + p_ctrl->p_reg->NTST_b.RSQFF = 0; + + /* Read the DATA_LENGTH field in the response descriptor. */ + uint32_t data_length = receive_status_descriptor & I3C_RECV_STATUS_DESC_DATA_LENGTH_Msk; + + /* Read the ERR_STATUS field in the response descriptor. */ + uint32_t err_status = (receive_status_descriptor & I3C_RECV_STATUS_DESC_ERR_STATUS_Msk) >> + I3C_RECV_STATUS_DESC_ERR_STATUS_Pos; + + i3c_callback_args_t callback_args; + callback_args.p_context = p_ctrl->p_cfg->p_context; + callback_args.event_status = err_status; + + i3c_slave_error_recovery_type_t error_recovery_type = I3C_SLAVE_ERROR_RECOVERY_TYPE_OTHER; + + /* The transfer type is a normal SDR transfer. */ + if (0U == (receive_status_descriptor & I3C_RECV_STATUS_DESC_TRANSFER_TYPE_Msk)) + { + /* If the transfer is a read transfer. */ + if (0U == (receive_status_descriptor & I3C_RECV_STATUS_DESC_SDR_R_W_TYPE_Msk)) + { + /* Calculate the remaining number of bytes stored in the read FIFO. */ + uint32_t bytes_remaining = i3c_read_bytes_remaining_calculate(p_ctrl, data_length); + + /* Read the remaining bytes stored in the FIFO. */ + i3c_fifo_read(p_ctrl, bytes_remaining); + + /* + * If the last transfer was a read, then the transfer length was stored in + * the receive status descriptor. + */ + callback_args.transfer_size = data_length; + callback_args.event = I3C_EVENT_READ_COMPLETE; + + /* Reset there state for read transfers. */ + p_ctrl->read_buffer_descriptor = (i3c_read_buffer_descriptor_t) { + 0 + }; + + /* Set the error recovery procedure to use if there was a transfer error. */ + error_recovery_type = I3C_SLAVE_ERROR_RECOVERY_TYPE_READ; + } + else + { + /* Calculate the total transfer length. Note that for a write transfer, the DATA_LENGTH field in the receive + * descriptor provides the number of bytes remaining. */ + callback_args.transfer_size = data_length; + callback_args.event = I3C_EVENT_WRITE_COMPLETE; + + /* Reset the state for write transfers. */ + p_ctrl->write_buffer_descriptor = (i3c_write_buffer_descriptor_t) { + 0 + }; + + /* Set the error recovery procedure to use if there was a transfer error. */ + error_recovery_type = I3C_SLAVE_ERROR_RECOVERY_TYPE_WRITE; + + /* Disable the transmit IRQ if it hasn't been disabled already. */ + i3c_extended_cfg_t * p_extend = (i3c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + p_ctrl->p_reg->NTIE_b.TDBEIE0 = 0; + R_BSP_IrqClearPending(p_extend->tx_irq); + } + } + else + { + /* + * The transfer type is a command. + * + * Get the command code from the response status descriptor. + */ + uint8_t command_code = + (uint8_t) ((receive_status_descriptor & I3C_RECV_STATUS_DESC_CMD_Msk) >> I3C_RECV_STATUS_DESC_CMD_Pos); + + if ((I3C_CCC_BROADCAST_ENTDAA == command_code) || + (I3C_CCC_DIRECT_SETDASA == command_code)) + { + uint32_t data_length_w = (data_length + sizeof(uint32_t) - 1) / sizeof(uint32_t); + for (uint32_t i = 0; i < data_length_w; i++) + { + /* + * Perform dummy read. + * See "Dynamic Address Assign Procedure" in the I3C Slave Operation section of the relevant hardware manual. + */ + p_ctrl->p_reg->NTDTBP0; + } + + /* Reset the state for read transfers. */ + p_ctrl->read_buffer_descriptor = (i3c_read_buffer_descriptor_t) { + 0 + }; + + /* Notify the application that the ENTDAA command has completed. */ + callback_args.event = I3C_EVENT_ADDRESS_ASSIGNMENT_COMPLETE; + + /* Verify that the slave address is valid. */ + if (p_ctrl->p_reg->SVDVAD0_b.SDYADV) + { + /* Provide the assigned dynamic address in the callback. */ + uint32_t dynamic_address_w = (p_ctrl->p_reg->SVDVAD0 & R_I3C0_SVDVAD0_SVAD_Msk); + callback_args.dynamic_address = (uint8_t) (dynamic_address_w >> R_I3C0_SVDVAD0_SVAD_Pos) & UINT8_MAX; + } + } + else + { + /* Calculate the remaining number of bytes stored in the read FIFO. */ + uint32_t bytes_remaining = i3c_read_bytes_remaining_calculate(p_ctrl, data_length); + + /* Read the remaining byte stored in the FIFO. */ + i3c_fifo_read(p_ctrl, bytes_remaining); + + if (I3C_CCC_DIRECT_GETACCMST == command_code) + { + if (0 != (p_ctrl->p_reg->PRSST & R_I3C0_PRSST_CRMS_Msk)) + { + /* On success of the GETACCMST command, the driver will transition to master mode. */ + p_ctrl->internal_state = I3C_INTERNAL_STATE_MASTER_IDLE; + + /* + * Configure IBI queue threshold so that an IBI IRQ is generated when there is 1 IBI status descriptor in the FIFO. + */ + p_ctrl->p_reg->NQTHCTL_b.IBIQTH = 0; + + /* + * In slave mode the IBI Queue Empty/Full flag indicates that the queue is empty. After transitioning to + * master mode, this bit indicates if there is status information in the queue. If the IBI queue was empty + * before transitioning to master mode, then it will be set and the status should be cleared. + */ + p_ctrl->p_reg->NTST_b.IBIQEFF = 0; + } + + /* Re-enable the IBI Status Buffer Full IRQ. */ + p_ctrl->p_reg->NTIE_b.IBIQEFIE = 1; + } + + if (p_ctrl->read_buffer_descriptor.count > 0) + { + /* Reset the state for read transfers if data was read. */ + p_ctrl->read_buffer_descriptor = (i3c_read_buffer_descriptor_t) { + 0 + }; + } + + callback_args.event = I3C_EVENT_COMMAND_COMPLETE; + callback_args.command_code = command_code; + callback_args.transfer_size = data_length; + } + } + + /* Reset the total bytes read. */ + p_ctrl->read_transfer_count_final = 0; + + uint32_t ntst = p_ctrl->p_reg->NTST; + + /* If an error occurred during the transfer, perform the error recovery operation defined in Figure "Example of error recovery operation flowchart for I3C slave" + * in the I3C section of the relevant hardware manual. */ + if ((0 != (ntst & (R_I3C0_NTST_TEF_Msk | R_I3C0_NTST_TABTF_Msk))) && (0U == p_ctrl->p_reg->NRSQSTLV_b.RSQLV)) + { + if (I3C_INTERNAL_STATE_SLAVE_IDLE == p_ctrl->internal_state) + { + i3c_slave_error_recovery(p_ctrl, error_recovery_type); + } + } + + /* Clear error status flags. */ + p_ctrl->p_reg->NTST &= ~(R_I3C0_NTST_TEF_Msk | R_I3C0_NTST_TABTF_Msk); + + /* Notify the application of the event. */ + p_ctrl->p_cfg->p_callback(&callback_args); +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR for writing to the IBI Data Queue in slave mode, and reading from the IBI Status Queue in master mode. + **********************************************************************************************************************/ +void i3c_ibi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + i3c_instance_ctrl_t * p_ctrl = i3c_isr_context_get(); +#if I3C_CFG_SLAVE_SUPPORT + if (I3C_INTERNAL_STATE_SLAVE_IBI == p_ctrl->internal_state) + { + /* Write the data to the IBI queue. */ + p_ctrl->p_reg->NIBIQP = p_ctrl->ibi_next_word; + + /* Clear the IBI Queue Empty/Full Flag. */ + p_ctrl->p_reg->NTST_b.IBIQEFF = 0; + + if (p_ctrl->ibi_buffer_descriptor.count >= p_ctrl->ibi_buffer_descriptor.buffer_size) + { + /* If there is no more data to write, then disable the IBI IRQ. */ + p_ctrl->p_reg->NTIE_b.IBIQEFIE = 0; + i3c_extended_cfg_t * p_extend = (i3c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + R_BSP_IrqClearPending(p_extend->ibi_irq); + } + else + { + /* Calcaulate the next word of data that will be written to the IBI FIFO. */ + p_ctrl->ibi_next_word = i3c_next_data_word_calculate( + (i3c_write_buffer_descriptor_t *) &p_ctrl->ibi_buffer_descriptor); + } + } + else +#endif + { +#if I3C_CFG_MASTER_SUPPORT + + /* Read the IBI status descriptor. */ + uint32_t ibi_status = p_ctrl->p_reg->NIBIQP; + + /* Get the number of bytes following the status descriptor. */ + uint32_t ibi_data_length = (ibi_status & I3C_IBI_STATUS_DESC_LENGTH_Msk) >> I3C_IBI_STATUS_DESC_LENGTH_Pos; + + /* Update the total number of bytes read during the IBI transfer. */ + p_ctrl->ibi_transfer_count_final += ibi_data_length; + + /* Calculate the number of words that need to be read from the IBI Queue. */ + uint32_t ibi_data_length_w = (ibi_data_length + sizeof(uint32_t) - 1) / sizeof(uint32_t); + + for (uint32_t i = 0; i < ibi_data_length_w; i++) + { + /* Get the next word of data from the IBI Queue. */ + uint32_t read_data = p_ctrl->p_reg->NIBIQP; + + /* + * Store the next word of data into the read buffer. If there is not enough space, a I3C_EVENT_IBI_READ_BUFFER_FULL + * event will be called to notify the application that a new read buffer is required. + */ + i3c_read_buffer_store(p_ctrl, + &p_ctrl->ibi_buffer_descriptor, + read_data, + ibi_data_length, + I3C_EVENT_IBI_READ_BUFFER_FULL); + ibi_data_length -= 4; + } + + /* Clear the IBI Queue Empty/Full Flag. */ + p_ctrl->p_reg->NTST_b.IBIQEFF = 0; + + /* If this is the last IBI status descriptor, then the IBI transfer is completed. */ + if (0U != (I3C_IBI_STATUS_DESC_LAST_STATUS_Msk & ibi_status)) + { + /* Get the address of the IBI transfer. */ + uint8_t ibi_address = (ibi_status & I3C_IBI_STATUS_DESC_IBI_ID_Msk) >> + (I3C_IBI_STATUS_DESC_IBI_ID_Pos + 1); + + /* Get the RNW bit of the IBI transfer. */ + uint8_t ibi_rnw = (ibi_status >> I3C_IBI_STATUS_DESC_IBI_ID_Pos) & 1U; + + uint32_t err_status = + (ibi_status & (I3C_IBI_STATUS_DESC_IBI_ST_Msk | I3C_IBI_STATUS_DESC_ERR_STATUS_Msk)) >> + I3C_IBI_STATUS_DESC_ERR_STATUS_Pos; + i3c_callback_args_t callback_args = + { + .event = I3C_EVENT_IBI_READ_COMPLETE, + .event_status = err_status, + .ibi_type = I3C_IBI_TYPE_INTERRUPT, + .ibi_address = ibi_address, + .transfer_size = p_ctrl->ibi_transfer_count_final, + .p_context = p_ctrl->p_cfg->p_context + }; + + if (I3C_HOT_JOIN_ADDRESS == ibi_address) + { + callback_args.ibi_type = I3C_IBI_TYPE_HOT_JOIN; + } + else if (0U == ibi_rnw) + { + callback_args.ibi_type = I3C_IBI_TYPE_MASTERSHIP_REQUEST; + } + else + { + /* IBI type is I3C_IBI_TYPE_INTERRUPT. */ + } + + p_ctrl->ibi_buffer_descriptor = (i3c_read_buffer_descriptor_t) { + 0 + }; + p_ctrl->ibi_transfer_count_final = 0; + + /* Notify the application of the event. */ + p_ctrl->p_cfg->p_callback(&callback_args); + } +#endif + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR for providing the following events to the application: + * - I3C_EVENT_INTERNAL_ERROR: An internal error can occur if too many transfers occur sequenctionally and overflow + * the Receive Status Queue (See "INST: Internal Status Register" description in the I3C section + * of the relevant hardware manual). + * - I3C_EVENT_TIMEOUT_DETECTED + * - I3C_EVENT_HDR_EXIT_PATTERN_DETECTED + **********************************************************************************************************************/ +void i3c_eei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + i3c_instance_ctrl_t * p_ctrl = i3c_isr_context_get(); + + i3c_callback_args_t callback_args; + callback_args.p_context = p_ctrl->p_cfg->p_context; + + /* Read the Internal Status Register. */ + uint32_t inst = p_ctrl->p_reg->INST; + uint32_t inst_clear_mask = 0; + + /* Read the Bus Status Register. */ + uint32_t bst = p_ctrl->p_reg->BST; + uint32_t bst_clear_mask = 0; + + if (0U != (inst & R_I3C0_INST_INEF_Msk)) + { + /* Notify the application of the internal error. */ + callback_args.event = I3C_EVENT_INTERNAL_ERROR; + p_ctrl->p_cfg->p_callback(&callback_args); + + inst_clear_mask |= R_I3C0_INST_INEF_Msk; + + /* Resume I3C operation. */ + p_ctrl->p_reg->BCTL_b.RSM = 1; + } + + /* Check if a timeout occurred. */ + if (0U != (bst & R_I3C0_BST_TODF_Msk)) + { + /* Notify that application that the timeout was detected. */ + callback_args.event = I3C_EVENT_TIMEOUT_DETECTED; + p_ctrl->p_cfg->p_callback(&callback_args); + + bst_clear_mask |= R_I3C0_BST_TODF_Msk; + } + + /* Check if the HDR Exit Pattern was detected. */ + if (0U != (bst & R_I3C0_BST_HDREXDF_Msk)) + { + /* Notify that application that the HDR Exit pattern was detected. */ + callback_args.event = I3C_EVENT_HDR_EXIT_PATTERN_DETECTED; + p_ctrl->p_cfg->p_callback(&callback_args); + + bst_clear_mask |= R_I3C0_BST_HDREXDF_Msk; + } + + /* Clear the status flags that have been handled. */ + p_ctrl->p_reg->INST &= ~inst_clear_mask; + p_ctrl->p_reg->BST &= ~bst_clear_mask; + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#if I3C_CFG_MASTER_SUPPORT + +/*******************************************************************************************************************//** + * Perform error recovery according to Figure "Example of error recovery operation flowchart for I3C master" + * in the I3C section of the relevant hardware manual. + **********************************************************************************************************************/ +void i3c_master_error_recovery (i3c_instance_ctrl_t * p_ctrl, bool error_recovery_case_2) +{ + #if I3C_ERROR_RECOVERY_VERSION_1 == I3C_CFG_ERROR_RECOVERY_SUPPORT || \ + I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + + /* For A2E2 version that has not been modified by ECO, the following error recovery procedure must be performed. + * See Figure "Example of error recovery operation flowchart for I3C master" in the I3C section of the relevant + * hardware manual. */ + if (1U == I3C_A2E2_VERSION) + #endif + { + /* Flush the Command, Rx and Tx Buffers. */ + p_ctrl->p_reg->RSTCTL = I3C_RSTCTRL_FIFO_FLUSH_Msk; + + /* The field will be cleared automatically upon reset completion (See "RSTCTL : Reset Control Register" description in the I3C section + * of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->RSTCTL & I3C_RSTCTRL_FIFO_FLUSH_Msk), 0U); + + /* Wait for the bus available condition. */ + while (1) + { + /* If SDA is pulled low, then a slave device started an IBI during error recovery. */ + if (0U == p_ctrl->p_reg->PRSTDBG_b.SDILV) + { + break; + } + + /* Check the bus available condition. */ + if (1 == p_ctrl->p_reg->BCST_b.BAVLF) + { + break; + } + } + + if (error_recovery_case_2) + { + /* Disable the IBI Status Buffer Full IRQ. */ + p_ctrl->p_reg->NTIE_b.IBIQEFIE = 0; + + /* When recovering from a read operation where the transfer length is less than expected, perform internal + * software reset. */ + p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_INTLRST_Msk; + p_ctrl->p_reg->RSTCTL = 0; + + /* Restore the current master setting. */ + p_ctrl->p_reg->PRSST = (uint32_t) (R_I3C0_PRSST_CRMS_Msk | R_I3C0_PRSST_PRSSTWP_Msk); + + /* After an internal reset, the CRMS bit is cleared which causes the IBI Queue Empty/Full Flag to be set indicating the queue is empty. + * Since the driver is in master mode, this status should be discarded and the flag should be cleared. */ + p_ctrl->p_reg->NTST_b.IBIQEFF = 0; + + /* Enable the IBI Status Buffer Full IRQ. */ + p_ctrl->p_reg->NTIE_b.IBIQEFIE = 1; + } + else + { + /* Resume I3C operation. */ + p_ctrl->p_reg->BCTL_b.RSM = 1; + } + + /* If a slave device started an IBI during error recovery, then it must be NACK'd or SDA will be held low indefinitely. */ + if (0U == p_ctrl->p_reg->PRSTDBG_b.SDILV) + { + /* Calculate the frequency of PCLKD. */ + uint32_t pclkd_frequency = (SystemCoreClock << R_SYSTEM->SCKDIVCR_b.ICK); + pclkd_frequency >>= R_SYSTEM->SCKDIVCR_b.PCKD; + + i3c_extended_cfg_t * p_extend = (i3c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Get the low and high period in PCLKD ticks. */ + uint32_t pclkd_low_period = (p_extend->bitrate_settings.stdbr & R_I3C0_STDBR_SBRLO_Msk) >> + R_I3C0_STDBR_SBRLO_Pos; + uint32_t pclkd_high_period = (p_extend->bitrate_settings.stdbr & R_I3C0_STDBR_SBRHO_Msk) >> + R_I3C0_STDBR_SBRHO_Pos; + + /* Calculate the high and low period for SCL. */ + uint32_t high_frequency = pclkd_frequency / pclkd_high_period; + uint32_t low_frequency = pclkd_frequency / pclkd_low_period; + uint32_t high_delay_us = (1000000U + high_frequency - 1) / high_frequency; // NOLINT(readability-magic-numbers) + uint32_t low_delay_us = (1000000U + low_frequency - 1) / low_frequency; // NOLINT(readability-magic-numbers) + + /* Check if BITCNT is working correctly. */ + bool bcnt_zero = true; + for (uint32_t i = 0; i < 4; i++) + { + R_BSP_SoftwareDelay(high_delay_us + low_delay_us, BSP_DELAY_UNITS_MICROSECONDS); + if (0 != p_ctrl->p_reg->BITCNT_b.BCNT) + { + bcnt_zero = false; + } + } + + /* If BITCNT is not incrementing, then the master is not aware of the IBI. */ + if (bcnt_zero) + { + /* Write SCL low in order to complete the start condition. */ + p_ctrl->p_reg->OUTCTL = R_I3C0_OUTCTL_SDOC_Msk | R_I3C0_OUTCTL_SOCWP_Msk; + + R_BSP_SoftwareDelay(low_delay_us, BSP_DELAY_UNITS_MICROSECONDS); + + /* Complete 9 SCL clock cycles while holding SDA high in order to NACK the IBI. */ + for (uint32_t i = 0; i < 9; i++) + { + /* Write SCL high. */ + p_ctrl->p_reg->OUTCTL = R_I3C0_OUTCTL_SDOC_Msk | R_I3C0_OUTCTL_SCOC_Msk | R_I3C0_OUTCTL_SOCWP_Msk; + + R_BSP_SoftwareDelay(high_delay_us, BSP_DELAY_UNITS_MICROSECONDS); + + /* Write SCL low. */ + p_ctrl->p_reg->OUTCTL = R_I3C0_OUTCTL_SDOC_Msk | R_I3C0_OUTCTL_SOCWP_Msk; + + R_BSP_SoftwareDelay(low_delay_us, BSP_DELAY_UNITS_MICROSECONDS); + } + + /* Write SCL and SDA low. */ + p_ctrl->p_reg->OUTCTL = R_I3C0_OUTCTL_SOCWP_Msk; + + R_BSP_SoftwareDelay(low_delay_us, BSP_DELAY_UNITS_MICROSECONDS); + + /* Write SCL high. */ + p_ctrl->p_reg->OUTCTL = R_I3C0_OUTCTL_SCOC_Msk | R_I3C0_OUTCTL_SOCWP_Msk; + + R_BSP_SoftwareDelay(high_delay_us, BSP_DELAY_UNITS_MICROSECONDS); + + /* Write SDA anb SCL high to complete the stop condition. */ + p_ctrl->p_reg->OUTCTL = R_I3C0_OUTCTL_SDOC_Msk | R_I3C0_OUTCTL_SCOC_Msk | R_I3C0_OUTCTL_SOCWP_Msk; + } + } + } + #endif + + #if I3C_ERROR_RECOVERY_VERSION_2 == I3C_CFG_ERROR_RECOVERY_SUPPORT || \ + I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + + /* For A2E2 version that has been modified by ECO, simplified error recovery procedure can be performed. */ + if (2U == I3C_A2E2_VERSION) + #endif + { + FSP_PARAMETER_NOT_USED(error_recovery_case_2); + + /* Flush the Command, Rx and Tx Buffers. */ + p_ctrl->p_reg->RSTCTL = I3C_RSTCTRL_FIFO_FLUSH_Msk; + + /* The field will be cleared automatically upon reset completion (See "RSTCTL : Reset Control Register" description in the I3C section + * of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->RSTCTL & I3C_RSTCTRL_FIFO_FLUSH_Msk), 0U); + + /* Resume I3C operation. */ + p_ctrl->p_reg->BCTL_b.RSM = 1; + } + #endif +} + +#endif + +#if I3C_CFG_SLAVE_SUPPORT + +/*******************************************************************************************************************//** + * Perform error recovery according to Figure "Example of error recovery operation flowchart for I3C slave" + * in the I3C section of the relevant hardware manual. + **********************************************************************************************************************/ +void i3c_slave_error_recovery (i3c_instance_ctrl_t * p_ctrl, i3c_slave_error_recovery_type_t recovery_type) +{ + switch (recovery_type) + { + case I3C_SLAVE_ERROR_RECOVERY_TYPE_WRITE: + { + /* Flush the Command and Tx Data FIFO. */ + p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_TDBRST_Msk; + break; + } + + case I3C_SLAVE_ERROR_RECOVERY_TYPE_READ: + { + /* Flush the Command and Rx Data FIFO. */ + p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_RDBRST_Msk; + break; + } + + case I3C_SLAVE_ERROR_RECOVERY_TYPE_IBI: + { + /* Flush the Command and Rx Data FIFO. */ + p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_CMDQRST_Msk; + break; + } + + default: + { + break; + } + } + + /* The field will be cleared automatically upon reset completion (See "RSTCTL : Reset Control Register" description + * in the I3C section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL, 0U); + + #if I3C_ERROR_RECOVERY_VERSION_1 == I3C_CFG_ERROR_RECOVERY_SUPPORT || \ + I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + + /* For A2E2 version that has not been modified by ECO, the following error recovery procedure must be performed. + * See Figure "Example of error recovery operation flowchart for I3C slave" in the I3C section of the relevant hardware manual. */ + if (1U == I3C_A2E2_VERSION) + #endif + { + /* Wait for Bus Available Condition (See Figure "Example of error recovery operation flowchart for I3C slave" + * in the I3C section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->BCST & R_I3C0_BCST_BAVLF_Msk), R_I3C0_BCST_BAVLF_Msk); + + /* Wait for start condition to be cleared (See Figure "Example of error recovery operation flowchart for I3C slave" + * in the I3C section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->BST & R_I3C0_BST_STCNDDF_Msk), 0); + + /* Read the current value of SDDYAD. */ + uint32_t sdatbas0 = p_ctrl->p_reg->SDATBAS0; + + /* Perform internal software reset. */ + p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_INTLRST_Msk; + p_ctrl->p_reg->RSTCTL = 0; + + /* Calculate the frequency of PCLKD. */ + uint32_t pclkd_frequency = (SystemCoreClock << R_SYSTEM->SCKDIVCR_b.ICK); + pclkd_frequency >>= R_SYSTEM->SCKDIVCR_b.PCKD; + + /* Wait for the expected amount of time for the Bus Available Condition. */ + uint32_t expected_bus_available_time = + (1000000U * p_ctrl->p_reg->BAVLCDT + pclkd_frequency - 1) / pclkd_frequency; // NOLINT(readability-magic-numbers) + + R_BSP_SoftwareDelay(expected_bus_available_time, BSP_DELAY_UNITS_MICROSECONDS); + + /* If the Bus is already available then error recovery is complete. */ + if (0 == (p_ctrl->p_reg->BCST & R_I3C0_BCST_BAVLF_Msk)) + { + while (0 == (p_ctrl->p_reg->BST & R_I3C0_BST_STCNDDF_Msk)) + { + /* Perform internal software reset. */ + p_ctrl->p_reg->RSTCTL = R_I3C0_RSTCTL_INTLRST_Msk; + + /* Wait for Bus Available Condition (See Figure "Example of error recovery operation flowchart for I3C slave" + * in the I3C section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT((p_ctrl->p_reg->BCST & R_I3C0_BCST_BAVLF_Msk), R_I3C0_BCST_BAVLF_Msk); + + p_ctrl->p_reg->RSTCTL = 0; + } + } + + /* Write back value of SDDYAD. */ + p_ctrl->p_reg->SDATBAS0 = sdatbas0; + } + #endif + #if I3C_ERROR_RECOVERY_VERSION_2 == I3C_CFG_ERROR_RECOVERY_SUPPORT || \ + I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + #if I3C_ERROR_RECOVERY_VERSION_BOTH == I3C_CFG_ERROR_RECOVERY_SUPPORT + + /* For A2E2 version that has been modified by ECO, simplified error recovery procedure can be performed. */ + if (2U == I3C_A2E2_VERSION) + #endif + { + /* Resume I3C operation. */ + p_ctrl->p_reg->BCTL_b.RSM = 1; + } + #endif +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_icu/r_icu.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_icu/r_icu.c new file mode 100644 index 0000000000..6750e29154 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_icu/r_icu.c @@ -0,0 +1,439 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_icu.h" +#include "r_icu_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "ICU" in ASCII, used to determine if channel is open. */ +#define ICU_OPEN (0x00494355U) + +#define ICU_IRQMD_OFFSET (0) + +#if BSP_FEATURE_ICU_HAS_FILTER + #define ICU_FCLKSEL_OFFSET (4) + #define ICU_FLTEN_OFFSET (7) + #if BSP_FEATURE_ICU_HAS_LOCO_FILTER + #define LOCO_CLOCK_HZ (R_BSP_SourceClockHzGet(FSP_PRIV_CLOCK_LOCO)) + #define SYSTEM_CLOCK_HZ (SystemCoreClock) + #endif +#endif + +/* If the mask is larger than 0xFFFF, then it requires 32-bit values instead of 16-bit */ +#if BSP_FEATURE_ICU_IRQ_CHANNELS_MASK > 0xFFFFU + +/* When mask is over 16-bit, there are actually two registers - R_ICU->IRQCRa and R_ICU->IRQCRb. Between them in memory + * is R_ICU->NMICR and means there is a 4 byte offset between the end of IRQCRa and beginning of IRQCRb. To save some + * instructions, this arithmetic determines if the 4 byte offset should be added to the indexing of IRQCRa to write to + * channels 16-31 */ + #define ICU_IRQCR_CH(c) ((c) + (uint8_t) (((c) >> 4) << 2)) + #define ICU_IRQCR_REG (R_ICU->IRQCRa) + #define ICU_IRQCR_REG_BITFIELD (R_ICU->IRQCRa_b) +#else + #define ICU_IRQCR_CH(c) (c) + #define ICU_IRQCR_REG (R_ICU->IRQCR) + #define ICU_IRQCR_REG_BITFIELD (R_ICU->IRQCR_b) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * icu_prv_ns_callback)(external_irq_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile icu_prv_ns_callback)(external_irq_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void r_icu_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* ICU implementation of External IRQ API. */ +const external_irq_api_t g_external_irq_on_icu = +{ + .open = R_ICU_ExternalIrqOpen, + .enable = R_ICU_ExternalIrqEnable, + .disable = R_ICU_ExternalIrqDisable, + .callbackSet = R_ICU_ExternalIrqCallbackSet, + .close = R_ICU_ExternalIrqClose, +}; + +/*******************************************************************************************************************//** + * @addtogroup ICU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure an IRQ input pin for use with the external interrupt interface. Implements @ref external_irq_api_t::open. + * + * The Open function is responsible for preparing an external IRQ pin for operation. + * + * @retval FSP_SUCCESS Open successful. + * @retval FSP_ERR_ASSERTION One of the following is invalid: + * - p_ctrl or p_cfg is NULL + * @retval FSP_ERR_ALREADY_OPEN The channel specified has already been opened. No configurations were changed. + * Call the associated Close function to reconfigure the channel. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in p_cfg is not available on the device selected in + * r_bsp_cfg.h. + * @retval FSP_ERR_INVALID_ARGUMENT p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to + * use callback function. + * @retval FSP_ERR_UNSUPPORTED An input argument is not supported by selected mode. + * + * @note This function is reentrant for different channels. It is not reentrant for the same channel. + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg) +{ + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + FSP_ASSERT(NULL != p_cfg); + + #if BSP_FEATURE_ICU_HAS_LOCO_FILTER + FSP_ASSERT(NULL != p_cfg->p_extend); + #endif + + #if !BSP_FEATURE_ICU_HAS_FILTER + + /* Verify the configuration trigger source is correct */ + FSP_ERROR_RETURN((EXTERNAL_IRQ_TRIG_FALLING == p_cfg->trigger) || + (EXTERNAL_IRQ_TRIG_RISING == p_cfg->trigger) || + (EXTERNAL_IRQ_TRIG_BOTH_EDGE == p_cfg->trigger) || + (EXTERNAL_IRQ_TRIG_LEVEL_LOW == p_cfg->trigger), + FSP_ERR_UNSUPPORTED); + #endif + + FSP_ERROR_RETURN(0 != ((1ULL << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Callback must be used with a valid interrupt priority otherwise it will never be called. */ + if (p_cfg->p_callback) + { + FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT); + } +#endif + + p_ctrl->irq = p_cfg->irq; + +#if BSP_FEATURE_ICU_HAS_IELSR + + /* IELSR Must be zero when modifying the IRQCR bits. + * (See "IRQ Control Register i (IRQCRi) (i = 0 to 15)" description in the ICU section of the relevant hardware manual). */ + uint32_t ielsr = R_ICU->IELSR[p_ctrl->irq]; + R_ICU->IELSR[p_ctrl->irq] = 0; +#endif + +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_ctrl->p_callback_memory = NULL; +#endif + + /* Initialize control block. */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->channel = p_cfg->channel; + + uint8_t channel = ICU_IRQCR_CH(p_ctrl->channel); + uint8_t irqcr = 0; + +#if BSP_FEATURE_ICU_HAS_FILTER + + /* Disable digital filter */ + ICU_IRQCR_REG[channel] = 0U; + + #if BSP_FEATURE_ICU_HAS_LOCO_FILTER + icu_extended_cfg_t * p_extend = (icu_extended_cfg_t *) p_cfg->p_extend; + + /* Set the digital filter divider. */ + irqcr = (uint8_t) (p_extend->filter_src << R_ICU_IRQCR_LOCOSEL_Pos); + #endif + + /* Set the digital filter divider. */ + irqcr |= (uint8_t) (p_cfg->clock_source_div << ICU_FCLKSEL_OFFSET); + + /* Enable/Disable digital filter. */ + irqcr |= (uint8_t) (p_cfg->filter_enable << ICU_FLTEN_OFFSET); + + /* Set the IRQ trigger. */ + irqcr |= (uint8_t) (p_cfg->trigger << ICU_IRQMD_OFFSET); +#else + irqcr = (uint8_t) (p_cfg->trigger << ICU_IRQMD_OFFSET); +#endif + + /* Write IRQCR */ + ICU_IRQCR_REG[channel] = irqcr; + +#if BSP_FEATURE_ICU_HAS_IELSR + #if BSP_FEATURE_ICU_HAS_LOCO_FILTER + + /* If LOCO is used as Digital Filtering Sample Clock, delay 4 LOCO clock cycles before restore IELSR */ + if (EXTERNAL_IRQ_DIGITAL_FILTER_LOCO == p_extend->filter_src) + { + /* If LOCO is used as Digital Filtering Sample Clock, delay 4 LOCO clock cycles before restore IELSR. + * Total_cycles = (4 * system_clock_hz) / (loco_clock_hz). + */ + uint32_t total_cycles = (uint32_t) ((4 * SYSTEM_CLOCK_HZ) / LOCO_CLOCK_HZ); + + bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(total_cycles)); + } + #endif + + /* Restore IELSR. */ + R_ICU->IELSR[p_ctrl->irq] = ielsr; +#endif + + /* NOTE: User can have the driver opened when the IRQ is not in the vector table. This is for use cases + * where the external IRQ driver is used to generate ELC events only (without CPU interrupts). + * In such cases we will not set the IRQ priority but will continue with the processing. + */ + if (p_ctrl->irq >= 0) + { + R_BSP_IrqCfg(p_ctrl->irq, p_cfg->ipl, p_ctrl); + } + + /* Mark the control block as open */ + p_ctrl->open = ICU_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::enable. + * + * @retval FSP_SUCCESS Interrupt Enabled successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @retval FSP_ERR_IRQ_BSP_DISABLED Requested IRQ is not defined in this system + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqEnable (external_irq_ctrl_t * const p_api_ctrl) +{ + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); +#endif + + /* Clear the interrupt status and Pending bits, before the interrupt is enabled. */ + R_BSP_IrqEnable(p_ctrl->irq); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::disable. + * + * @retval FSP_SUCCESS Interrupt disabled successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @retval FSP_ERR_IRQ_BSP_DISABLED Requested IRQ is not defined in this system + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl) +{ + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); +#endif + + /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */ + R_BSP_IrqDisable(p_ctrl->irq); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements external_irq_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)( + external_irq_callback_args_t *), + void * const p_context, + external_irq_callback_args_t * const p_callback_memory) +{ + icu_instance_ctrl_t * p_ctrl = p_api_ctrl; + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#else + FSP_PARAMETER_NOT_USED(p_callback_memory); +#endif + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_callback); + + #if BSP_TZ_SECURE_BUILD + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + external_irq_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback_memory = p_callback_memory; + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(external_irq_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Close the external interrupt channel. Implements @ref external_irq_api_t::close. + * + * @retval FSP_SUCCESS Successfully closed. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqClose (external_irq_ctrl_t * const p_api_ctrl) +{ + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Cleanup. Disable interrupt */ + if (p_ctrl->irq >= 0) + { + /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */ + R_BSP_IrqDisable(p_ctrl->irq); + R_FSP_IsrContextSet(p_ctrl->irq, NULL); + } + + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup ICU) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * ICU External Interrupt ISR. + **********************************************************************************************************************/ +void r_icu_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + +#if BSP_FEATURE_ICU_HAS_IELSR + bool level_irq = false; + + uint8_t channel = ICU_IRQCR_CH(p_ctrl->channel); + uint8_t mode = ICU_IRQCR_REG_BITFIELD[channel].IRQMD; + + if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == mode) + { + level_irq = true; + } + else + { + /* Clear the IR bit before calling the user callback so that if an edge is detected while the ISR is active + * it will not be missed. */ + R_BSP_IrqStatusClear(irq); + } +#endif + + if ((NULL != p_ctrl) && (NULL != p_ctrl->p_callback)) + { +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + external_irq_callback_args_t args; + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + args.channel = p_ctrl->channel; + args.p_context = p_ctrl->p_context; + p_ctrl->p_callback(&args); + } + else + { + /* Save current state of p_callback_args so that it can be shared between interrupts. */ + args = *p_ctrl->p_callback_memory; + + /* Set the callback args passed to the Non-secure callback. */ + p_ctrl->p_callback_memory->channel = p_ctrl->channel; + p_ctrl->p_callback_memory->p_context = p_ctrl->p_context; + + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + icu_prv_ns_callback p_callback = (icu_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_ctrl->p_callback_memory); + + /* Restore the state of p_callback_args. */ + *p_ctrl->p_callback_memory = args; + } + +#else + + /* Set data to identify callback to user, then call user callback. */ + external_irq_callback_args_t args; + args.channel = p_ctrl->channel; + args.p_context = p_ctrl->p_context; + p_ctrl->p_callback(&args); +#endif + } + +#if BSP_FEATURE_ICU_HAS_IELSR + if (level_irq) + { + /* Clear the IR bit after calling the user callback so that if the condition is cleared the ISR will not + * be called again. */ + R_BSP_IrqStatusClear(irq); + } +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_b_master/r_iic_b_master.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_b_master/r_iic_b_master.c new file mode 100644 index 0000000000..af3628c9ed --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_b_master/r_iic_b_master.c @@ -0,0 +1,1693 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_iic_b_master.h" +#if IIC_B_MASTER_CFG_DTC_ENABLE + #include "r_dtc.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "IICB" in ASCII, used to determine if channel is open. */ +#define IIC_B_MASTER_OPEN (0x49494342U) +#define I2C_CODE_READ (0x01U) +#define I2C_CODE_10BIT (0xF0U) +#define IIC_B_MASTER_BUS_RATE_REG_RESERVED_BITS (0xE0U) +#define IIC_B_MASTER_INTERNAL_REF_CLOCK_SELECT_MAX (0x07U) + +#define IIC_B_MASTER_SLAVE_10_BIT_ADDR_LEN_ADJUST (2U) + +#define IIC_B_MASTER_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#define IIC_B_MASTER_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define IIC_B_MASTER_PRV_BIE_INIT_MASK (R_I3C0_BIE_NACKDIE_Msk | R_I3C0_BIE_ALIE_Msk | \ + R_I3C0_BIE_TODIE_Msk) +#define IIC_B_MASTER_PRV_BSTE_INIT_MASK (R_I3C0_BSTE_NACKDE_Msk | R_I3C0_BSTE_TENDE_Msk | \ + R_I3C0_BSTE_ALE_Msk | \ + R_I3C0_BSTE_TODE_Msk) +#define IIC_B_MASTER_PRV_NTIE_INIT_MASK (R_I3C0_NTIE_TDBEIE0_Msk | R_I3C0_NTIE_RDBFIE0_Msk) +#define IIC_B_MASTER_PRV_NTSTE_INIT_MASK (R_I3C0_NTSTE_TDBEE0_Msk | R_I3C0_NTSTE_RDBFE0_Msk) + +#define IIC_B_MASTER_PRV_BST_ERR_STATUS_MASK (R_I3C0_BST_STCNDDF_Msk | R_I3C0_BST_SPCNDDF_Msk | \ + R_I3C0_BST_NACKDF_Msk | \ + R_I3C0_BST_ALF_Msk | R_I3C0_BST_TODF_Msk) + +#define IIC_B_MASTER_BFRECDT_FASTPLUS_DELAY_CONST (120U) +#define IIC_B_MASTER_BFRECDT_DELAY_CONST (300U) +#define IIC_B_MASTER_BILLION (1000000000U) +#define IIC_B_MASTER_ROUNDING_OFF_COMP (1U) + +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + #if BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA && IIC_B_MASTER_CFG_DTC_ENABLE + +/* The address of the MCU Version Register on RA2E2 MCUs. Different transmission procedures are used depending on the + * version of the MCU (This is only used on RA2E2 devices). */ + #define I2C_A2E2_VERSION (*((uint8_t const *) 0x01001C20U)) + #endif +#endif + +/* Worst case ratio of ICLK/PCLKB (RA2E2) or ICLK/PCLKA (RA6T2) = 64 approximately. + * 3 PCLKB cycles is the number of cycles to wait for IICn. + * Refer Table "Access cycles for non-GPT modules" in the I/O Registers section of the relevant hardware manual. + */ +#define IIC_B_MASTER_PERIPHERAL_REG_MAX_WAIT (0x40U * 0x03U) + +#define IIC_B_MASTER_HARDWARE_REGISTER_WAIT(reg, required_value, timeout) \ + while ((timeout)) \ + { \ + if ((required_value) == (reg)) \ + { \ + break; \ + } \ + (timeout)--; \ + } + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* IIC read/write enumeration */ +typedef enum e_iic_b_master_transfer_dir_option +{ + IIC_B_MASTER_TRANSFER_DIR_WRITE = 0x0, + IIC_B_MASTER_TRANSFER_DIR_READ = 0x1 +} iic_b_master_transfer_dir_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * iic_b_master_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile iic_b_master_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +void iic_b_master_rxi_isr(void); +void iic_b_master_txi_isr(void); +void iic_b_master_tei_isr(void); +void iic_b_master_eri_isr(void); + +/* Internal helper functions */ +static void iic_b_master_abort_seq_master(iic_b_master_instance_ctrl_t * const p_ctrl, bool iic_reset); +static fsp_err_t iic_b_master_read_write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + iic_b_master_transfer_dir_t direction); +static void iic_b_master_notify(iic_b_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event); + +#if IIC_B_MASTER_CFG_DTC_ENABLE +static fsp_err_t iic_b_master_transfer_open(i2c_master_cfg_t const * const p_cfg); +static fsp_err_t iic_b_master_transfer_configure(transfer_instance_t const * p_transfer, + iic_b_master_transfer_dir_t direction); + +#endif + +/* Interrupt handlers */ +static void iic_b_master_rxi_master(iic_b_master_instance_ctrl_t * p_ctrl); +static void iic_b_master_txi_master(iic_b_master_instance_ctrl_t * p_ctrl); +static void iic_b_master_tei_master(iic_b_master_instance_ctrl_t * p_ctrl); +static void iic_b_master_err_master(iic_b_master_instance_ctrl_t * p_ctrl); + +/* Functions that manipulate hardware */ +static void iic_b_master_open_hw_master(iic_b_master_instance_ctrl_t * const p_ctrl, + i2c_master_cfg_t const * const p_cfg); +static fsp_err_t iic_b_master_run_hw_master(iic_b_master_instance_ctrl_t * const p_ctrl); +static void iic_b_master_rxi_read_data(iic_b_master_instance_ctrl_t * const p_ctrl); +static void iic_b_master_txi_send_address(iic_b_master_instance_ctrl_t * const p_ctrl); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* IIC Implementation of I2C device master interface */ +i2c_master_api_t const g_i2c_master_on_iic_b = +{ + .open = R_IIC_B_MASTER_Open, + .read = R_IIC_B_MASTER_Read, + .write = R_IIC_B_MASTER_Write, + .abort = R_IIC_B_MASTER_Abort, + .slaveAddressSet = R_IIC_B_MASTER_SlaveAddressSet, + .close = R_IIC_B_MASTER_Close, + .statusGet = R_IIC_B_MASTER_StatusGet, + .callbackSet = R_IIC_B_MASTER_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup IIC_B_MASTER + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens the I2C device. + * + * @retval FSP_SUCCESS Requested clock rate was set exactly. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel is not available on this MCU. + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. p_api_ctrl or p_cfg is NULL. + * 2. extended parameter is NULL. + * 3. Callback parameter is NULL. + * 4. Set the rate to fast mode plus on a channel which does not support it. + * 5. Invalid IRQ number assigned + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) p_api_ctrl; +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); + FSP_ASSERT(p_cfg != NULL); + FSP_ASSERT(p_cfg->p_extend != NULL); + FSP_ASSERT(p_cfg->rxi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->eri_irq >= (IRQn_Type) 0); + FSP_ERROR_RETURN(IIC_B_MASTER_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + FSP_ERROR_RETURN(BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK & (1 << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* If rate is configured as Fast mode plus, check whether the channel supports it */ + if (I2C_MASTER_RATE_FASTPLUS == p_cfg->rate) + { + FSP_ASSERT((BSP_FEATURE_IIC_B_FAST_MODE_PLUS_CHANNELS_MASK & (1U << p_cfg->channel))); + } +#endif +#if IIC_B_MASTER_CFG_DTC_ENABLE + fsp_err_t err = FSP_SUCCESS; +#endif + +#if (BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK > 1U) + p_ctrl->p_reg = + (R_I3C0_Type *) ((uint32_t) R_I3C0 + (p_cfg->channel * ((uint32_t) R_I3C1 - (uint32_t) R_I3C0))); +#else + p_ctrl->p_reg = R_I3C0; +#endif + + /* Record the pointer to the configuration structure for later use */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->slave = p_cfg->slave; + p_ctrl->addr_mode = p_cfg->addr_mode; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + p_ctrl->p_buff = NULL; + p_ctrl->total = 0U; + p_ctrl->remain = 0U; + p_ctrl->loaded = 0U; + p_ctrl->read = false; + p_ctrl->restart = false; + p_ctrl->err = false; + p_ctrl->restarted = false; + +#if (1 == BSP_FEATURE_I3C_HAS_CLOCK) + R_BSP_MODULE_START(FSP_IP_I3C, p_cfg->channel); +#else + R_BSP_MODULE_START(FSP_IP_IIC, p_cfg->channel); +#endif + + /* Open the hardware in master mode. Performs IIC initialization as described in hardware manual (see + * "Initial Setting Flow" in the IIC section of the relevant hardware manual). */ + iic_b_master_open_hw_master(p_ctrl, p_cfg); + +#if IIC_B_MASTER_CFG_DTC_ENABLE + + /* Open the IIC transfer interface if available */ + err = iic_b_master_transfer_open(p_cfg); + if (FSP_SUCCESS != err) + { + #if (1 == BSP_FEATURE_I3C_HAS_CLOCK) + R_BSP_MODULE_STOP(FSP_IP_I3C, p_cfg->channel); + #else + R_BSP_MODULE_STOP(FSP_IP_IIC, p_cfg->channel); + #endif + + return err; + } +#endif + + p_ctrl->open = IIC_B_MASTER_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Performs a read from the I2C device. + * The caller will be notified when the operation has completed (successfully) by an + * I2C_MASTER_EVENT_RX_COMPLETE in the callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl, p_dest or bytes is NULL, or DTC is used for data transmission on RA2E2 Ver 1. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than uint16_t size (65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_IN_USE Bus busy condition. Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_B_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_Read (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart) +{ +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); + FSP_ASSERT(bytes != 0U); + #if BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA && IIC_B_MASTER_CFG_DTC_ENABLE + if (1 == I2C_A2E2_VERSION) + { + FSP_ASSERT(NULL == ((iic_b_master_instance_ctrl_t *) p_api_ctrl)->p_cfg->p_transfer_tx); + } + #endif +#endif + fsp_err_t err = FSP_SUCCESS; + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of iic_b_master_read_write to 4. */ + ((iic_b_master_instance_ctrl_t *) p_api_ctrl)->restart = restart; + + /* Call the common helper function to perform I2C Read operation.*/ + err = iic_b_master_read_write(p_api_ctrl, p_dest, bytes, IIC_B_MASTER_TRANSFER_DIR_READ); + + return err; +} + +/*******************************************************************************************************************//** + * Performs a write to the I2C device. + * The caller will be notified when the operation has completed (successfully) by an + * I2C_MASTER_EVENT_TX_COMPLETE in the callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_src is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than uint16_t size (65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_IN_USE Bus busy condition. Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_B_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_Write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart) +{ +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); + #if BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA && IIC_B_MASTER_CFG_DTC_ENABLE + if (1 == I2C_A2E2_VERSION) + { + FSP_ASSERT(NULL == ((iic_b_master_instance_ctrl_t *) p_api_ctrl)->p_cfg->p_transfer_tx); + } + #endif +#endif + fsp_err_t err = FSP_SUCCESS; + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of iic_b_master_read_write to 4. */ + ((iic_b_master_instance_ctrl_t *) p_api_ctrl)->restart = restart; + + /* Call the common helper function to perform I2C Write operation.*/ + err = iic_b_master_read_write(p_api_ctrl, p_src, bytes, IIC_B_MASTER_TRANSFER_DIR_WRITE); + + return err; +} + +/*******************************************************************************************************************//** + * Safely aborts any in-progress transfer and forces the IIC peripheral into ready state. + * + * + * @retval FSP_SUCCESS Channel was reset successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_B_MASTER_Open to initialize the control block. + * + * @note A callback will not be invoked in case an in-progress transfer gets aborted by calling this API. + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_Abort (i2c_master_ctrl_t * const p_api_ctrl) +{ + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) p_api_ctrl; + +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(IIC_B_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Abort any transfer happening on the channel */ + iic_b_master_abort_seq_master(p_ctrl, true); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets address and addressing mode of the slave device. + * This function is used to set the device address and addressing mode of the slave + * without reconfiguring the entire bus. + * + * @retval FSP_SUCCESS Address of the slave is set correctly. + * @retval FSP_ERR_ASSERTION Pointer to control structure is NULL. + * @retval FSP_ERR_IN_USE Another transfer was in-progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_B_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode) +{ + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(IIC_B_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Fail if there is already a transfer in progress */ + FSP_ERROR_RETURN(((0 == p_ctrl->remain) && (false == p_ctrl->restart)), FSP_ERR_IN_USE); +#endif + + /* Sets the address of the slave device */ + p_ctrl->slave = slave; + + /* Sets the mode of addressing */ + p_ctrl->addr_mode = addr_mode; + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2c_master_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory) +{ + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) p_api_ctrl; + +#if (IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(IIC_B_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2c_master_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2c_master_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides driver status. + * + * @retval FSP_SUCCESS Status stored in p_status. + * @retval FSP_ERR_ASSERTION NULL pointer. + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_StatusGet (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status) +{ + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) p_api_ctrl; + +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_status != NULL); +#endif + + p_status->open = (IIC_B_MASTER_OPEN == p_ctrl->open); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes the I2C device. May power down IIC peripheral. + * This function will safely terminate any in-progress I2C transfers. + * + * @retval FSP_SUCCESS Device closed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_B_MASTER_Open to initialize the control block. + * + * @note A callback will not be invoked in case an in-progress transfer gets aborted by calling this API. + **********************************************************************************************************************/ +fsp_err_t R_IIC_B_MASTER_Close (i2c_master_ctrl_t * const p_api_ctrl) +{ + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) p_api_ctrl; + +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(IIC_B_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disable I2C interrupts. */ + p_ctrl->p_reg->BIE = 0x00; + p_ctrl->p_reg->NTIE = 0x00; + + /* Clear BCTL.BUSE to 0: SCL, SDA pins not driven */ + p_ctrl->p_reg->BCTL = 0; + + /* Abort an in-progress transfer with this device only + * Set RSTCTL.RI2CRST to 1: Reset all registers and internal state; RSTCTL.INTLRST is already 0. + */ + p_ctrl->p_reg->RSTCTL = (uint32_t) (R_I3C0_RSTCTL_RI3CRST_Msk); + + /* Waiting for reset completion RSTCTL.RI2CRST = 0; RSTCTL.INTLRST is already 0. */ + FSP_HARDWARE_REGISTER_WAIT(0U, p_ctrl->p_reg->RSTCTL); + + /* The device is now considered closed */ + p_ctrl->open = 0U; + +#if IIC_B_MASTER_CFG_DTC_ENABLE + + /* Close the handles for the transfer interfaces */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + +#if (1 == BSP_FEATURE_I3C_HAS_CLOCK) + R_BSP_MODULE_STOP(FSP_IP_I3C, p_ctrl->p_cfg->channel); +#else + R_BSP_MODULE_STOP(FSP_IP_IIC, p_ctrl->p_cfg->channel); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IIC_B_MASTER) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Helper function for handling I2C Read or Write. + * + * @param p_api_ctrl Pointer to control block + * @param p_buffer Pointer to the buffer to store read/write data. + * @param[in] bytes Number of bytes to be read/written. + * @param[in] direction Read or Write + * + * @retval FSP_SUCCESS Function executed successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_buffer is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than UINT16_MAX(= 65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_IN_USE Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_B_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +static fsp_err_t iic_b_master_read_write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + iic_b_master_transfer_dir_t direction) +{ + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) p_api_ctrl; + +#if IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_buffer != NULL); + FSP_ERROR_RETURN((p_ctrl->open == IIC_B_MASTER_OPEN), FSP_ERR_NOT_OPEN); + FSP_ASSERT(((iic_b_master_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); + #if IIC_B_MASTER_CFG_DTC_ENABLE + + /* DTC on RX could actually receive 65535+3 = 65538 bytes as 3 bytes are handled separately. + * Forcing to 65535 to keep TX and RX uniform with respect to max transaction length via DTC. + */ + FSP_ERROR_RETURN((bytes <= UINT16_MAX), FSP_ERR_INVALID_SIZE); + #endif +#endif + + fsp_err_t err = FSP_SUCCESS; + + p_ctrl->p_buff = p_buffer; + p_ctrl->total = bytes; + + /* Handle the (different) addressing mode(s) */ + if (p_ctrl->addr_mode == I2C_MASTER_ADDR_MODE_7BIT) + { + /* Set the address bytes according to a 7-bit slave read command */ + p_ctrl->addr_high = 0U; + p_ctrl->addr_low = (uint8_t) ((p_ctrl->slave << 1U) | (uint8_t) direction); + p_ctrl->addr_total = 1U; + } + +#if IIC_B_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE + else + { + /* Set the address bytes according to a 10-bit slave read command */ + p_ctrl->addr_high = (uint8_t) (((p_ctrl->slave >> 7U) | I2C_CODE_10BIT) & (uint8_t) ~(I2C_CODE_READ)); + p_ctrl->addr_low = (uint8_t) p_ctrl->slave; + + /* Addr total = 3 for Read and 2 for Write. + * See Section "I2C Communication Data Format" in the IIC section of the relevant hardware manual. + */ + p_ctrl->addr_total = (uint8_t) ((uint8_t) direction + IIC_B_MASTER_SLAVE_10_BIT_ADDR_LEN_ADJUST); + } +#endif + + p_ctrl->read = (bool) direction; + + /* Kickoff the read operation as a master */ + err = iic_b_master_run_hw_master(p_ctrl); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Single point for managing the logic around notifying a transfer has finished. + * + * @param[in] p_ctrl Pointer to transfer that is ending. + * @param[in] event The event code to pass to the callback. + **********************************************************************************************************************/ +static void iic_b_master_notify (iic_b_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event) +{ + i2c_master_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2c_master_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_ctrl->p_context; + p_args->event = event; + +#if IIC_B_MASTER_CFG_DTC_ENABLE + + /* Stop any DTC assisted transfer for tx */ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if ((NULL != p_transfer_tx) && (!p_ctrl->read)) + { + p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + } + + /* Stop any DTC assisted transfer for rx */ + const transfer_instance_t * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if ((NULL != p_transfer_rx) && (p_ctrl->read)) + { + p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); + } +#endif + + /* Now do the callback here */ +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + iic_b_master_prv_ns_callback p_callback = (iic_b_master_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } + + /* Clear the err flags */ + p_ctrl->err = false; +} + +/*******************************************************************************************************************//** + * Single point for managing the logic around aborting a transfer when operating as a master. + * + * @param[in] p_ctrl Pointer to control structure of specific device. + * @param[in] iic_reset Flag to enable IIC reset + **********************************************************************************************************************/ +static void iic_b_master_abort_seq_master (iic_b_master_instance_ctrl_t * const p_ctrl, bool iic_reset) +{ + /* Safely stop the hardware from operating. */ + + /* Reset the peripheral */ + if (true == iic_reset) + { + /* Disable channel interrupts */ + p_ctrl->p_reg->BIE = 0x00; + p_ctrl->p_reg->NTIE = 0x00; + + /* This helper function would do a full IIC reset + * followed by re-initializing the required peripheral registers. */ + iic_b_master_open_hw_master(p_ctrl, p_ctrl->p_cfg); + } + + /* Update the transfer descriptor to show no longer in-progress and an error */ + p_ctrl->remain = 0U; + + /* Update the transfer descriptor to make sure interrupts no longer process */ + p_ctrl->addr_loaded = p_ctrl->addr_total; + p_ctrl->loaded = p_ctrl->total; + p_ctrl->restarted = false; + p_ctrl->restart = false; + + /* Enable Interrupts: TMOIE, ALIE, NAKIE, RIE, TIE. + * Disable Interrupt: TEIE, STIE, SPIE + */ + p_ctrl->p_reg->BIE = IIC_B_MASTER_PRV_BIE_INIT_MASK; + p_ctrl->p_reg->NTIE = IIC_B_MASTER_PRV_NTIE_INIT_MASK; +} + +/*******************************************************************************************************************//** + * Performs the hardware initialization sequence when operating as a master (see + * "Initial Setting Flow" in the IIC section of the relevant hardware manual). + * + * @param[in] p_ctrl Pointer to IIC specific control structure + * @param[in] p_cfg Pointer to IIC specific configuration structure. + **********************************************************************************************************************/ +static void iic_b_master_open_hw_master (iic_b_master_instance_ctrl_t * const p_ctrl, + i2c_master_cfg_t const * const p_cfg) +{ +#if (1 == BSP_FEATURE_I3C_HAS_CLOCK) + + /* Enable I3CCLK. (Not a part of init sequence in the HW manual, but RA8 must enable it to reset the module ) */ + p_ctrl->p_reg->CECTL = (uint32_t) R_I3C0_CECTL_CLKE_Msk; +#endif + + /* Clear BCTL.BUSE to 0: SCL, SDA pins not driven */ + p_ctrl->p_reg->BCTL = 0; + + /* Set RSTCTL.RI2CRST to 1: Reset all registers and internal state; RSTCTL.INTLRST is already 0.*/ + p_ctrl->p_reg->RSTCTL = (uint32_t) (R_I3C0_RSTCTL_RI3CRST_Msk); + + /* Waiting for reset completion RSTCTL.RI2CRST = 0; RSTCTL.INTLRST is already 0. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->RSTCTL_b.RI3CRST, 0U); + + /* In case of RA2E2, PRTS.PRTMD = 1 after the above reset. + * Refer "PRTS : Protocol Selection Register" description in the IIC section of the + * relevant hardware manual. + * + * Default value of SVCTL register is 0. + * Default/Reset value is set after IIC reset above. See table "Register states when issuing each condition" + * in the IIC section of the relevant hardware manual. + * This ensures the HW is in master mode and does not behave as a slave to another master on the same channel. + * Skip setting slave address length and slave address. + */ + iic_b_master_extended_cfg_t * p_extend = (iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend); + + /* Clock settings - Set REFCKCTL, STDBR and EXTBR registers: Set transfer bit rate. + * The values for these are set in the configuration structure by the tooling. + */ + p_ctrl->p_reg->REFCKCTL = (uint32_t) (p_extend->clock_settings.cks_value & R_I3C0_REFCKCTL_IREFCKS_Msk); + p_ctrl->p_reg->STDBR = (uint32_t) ((p_extend->clock_settings.brl_value << R_I3C0_STDBR_SBRLO_Pos) | + (p_extend->clock_settings.brh_value << R_I3C0_STDBR_SBRHO_Pos)); + + /* Set OUTCTL, INCTL, TMOCTL, ACKCTL and SCSTRCTL registers. + * (Default/Reset value is set after IIC reset above. See table "Register states when issuing each condition" + * in the IIC section of the relevant hardware manual.) + * 1. OUTCTL: Keep default settings in Open. + * + * 2. SCSTRCTL: Keep default settings in Open. + * + * 3. ACKCTL: Keep default settings in Open. + * + * 4. INCTL: Keep default settings in Open: + * Digital noise filter circuit is enabled by default after IIC reset. + * Upon IIC reset, 'DNFS[3:0] Digital Noise Filter Stage Selection' will be set to 0x00 + * This would imply 'Noise of up to one IICφ cycle is filtered out (singlestage filter).' + * (see "INCTL : Input Control Register" description in the IIC section of the relevant hardware manual.) + * + * Set TOHCTL to enable timeouts when SCLn is high. (Non configurable) + * Set TOLCTL based on user settings. + * Set TODTS based on user settings. Only 14 (SHORT) and 16 (LONG) bit counters are allowed. + * (see "TMOCTL : Timeout Control Register" description in the IIC section of the relevant hardware manual). + */ + p_ctrl->p_reg->TMOCTL = (uint32_t) ((uint32_t) R_I3C0_TMOCTL_TOHCTL_Msk | + (uint32_t) (IIC_B_MASTER_TIMEOUT_MODE_SHORT == + ((iic_b_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + timeout_mode) | + (uint32_t) (((iic_b_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + timeout_scl_low << R_I3C0_TMOCTL_TOLCTL_Pos)); + + /* 1. Disable FM+ slope circuit + * 2. Set Master Arbitration-Lost Detection Enable + * 3. Set NACK Transmission Arbitration-Lost Detection Enable + * 4. Enable SMBus mode if requested + */ + p_ctrl->p_reg->BFCTL = + (((uint32_t) (((iic_b_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->smbus_operation << + R_I3C0_BFCTL_SMBS_Pos)) | + ((uint32_t) ((I2C_MASTER_RATE_FASTPLUS == p_ctrl->p_cfg->rate) << R_I3C0_BFCTL_FMPE_Pos)) | + R_I3C0_BFCTL_NALE_Msk | R_I3C0_BFCTL_MALE_Msk | R_I3C0_BFCTL_SCSYNE_Msk); + + /* If SMBus is used, update OUTCTL to use SDA delay function */ + p_ctrl->p_reg->OUTCTL = (((uint32_t) (p_extend->clock_settings.sdod_value << R_I3C0_OUTCTL_SDOD_Pos)) | + ((uint32_t) (p_extend->clock_settings.sdodcs_value << R_I3C0_OUTCTL_SDODCS_Pos))); + + /* Enable status for Timeout Detection, Arbitration Loss, NACK Detection, Transmit End + * Disable status for Wake-up Condition Detection (Feature not supported by driver), + * STOP and START condition Detection + */ + p_ctrl->p_reg->BSTE = (uint32_t) IIC_B_MASTER_PRV_BSTE_INIT_MASK; + + /* Enable Interrupts: Timeout Detection, Arbitration Loss, NACK Detection. + * Disable Interrupt: Transmit End, Start, Stop + */ + p_ctrl->p_reg->BIE = (uint32_t) IIC_B_MASTER_PRV_BIE_INIT_MASK; + + /* Enable status for Transmit Data Buffer Empty and Receive Data Buffer Full */ + p_ctrl->p_reg->NTSTE = (uint32_t) IIC_B_MASTER_PRV_NTSTE_INIT_MASK; + + /* Enable Interrupts: Transmit Data Buffer Empty and Receive Data Buffer Full */ + p_ctrl->p_reg->NTIE = (uint32_t) IIC_B_MASTER_PRV_NTIE_INIT_MASK; + + /* Set valid interrupt contexts and user provided priority. Enable the interrupts at the NVIC */ + R_BSP_IrqCfgEnable(p_cfg->eri_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->tei_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->ipl, p_ctrl); + + /* Set BCTL.BUSE to 1: SCL, SDA pins in active state */ + p_ctrl->p_reg->BCTL = (uint32_t) R_I3C0_BCTL_BUSE_Msk; + + /* Set FRECYC based on IIC reference clock. + * (Not a part of init sequence in the HW manual) + * See section "IIC Timing" in the Electrical Characteristics section of the relevant hardware manual: + * 1. tBUF (Standard Mode) = 5 × tIICcyc + 300 ns + * 2. tBUF (Fast Mode) = 5 × tIICcyc + 300 ns + * 3. tBUF (Fast Plus Mode) = 5 × tIICcyc + 120 ns + * + * See "I3C Timing" in the Electrical Characteristics section of the relevant hardware manual: + * 1. tBUF (Standard Mode) = 3 × tIICcyc + 300 ns + * 2. tBUF (Fast Mode) = 3 × tIICcyc + 300 ns + * 3. tBUF (Fast Plus Mode) = 3 × tIICcyc + 120 ns + */ + uint32_t extra_ns = + (I2C_MASTER_RATE_FASTPLUS == + p_ctrl->p_cfg->rate) ? IIC_B_MASTER_BFRECDT_FASTPLUS_DELAY_CONST : IIC_B_MASTER_BFRECDT_DELAY_CONST; + uint32_t iic_clock_ns = (uint32_t) IIC_B_MASTER_BILLION / p_extend->iic_clock_freq; + p_ctrl->p_reg->BFRECDT = (uint32_t) (BSP_FEATURE_IIC_B_BUS_FREE_TIME_MULTIPLIER + IIC_B_MASTER_ROUNDING_OFF_COMP + + extra_ns / iic_clock_ns); +} + +/*******************************************************************************************************************//** + * Performs the data transfer described by the parameters when operating as a master. + * See "Data Write Transfer (Single Buffer transfer)" and "Data Read Transfer (Single Buffer transfer)" + * of 'I2C Master Operation' in the I3C section of the relevant hardware manual. + * + * @param[in] p_ctrl Pointer to control structure of specific device. + * + * @retval FSP_SUCCESS Data transfer success. + * @retval FSP_ERR_IN_USE If data transfer is in progress. + **********************************************************************************************************************/ +static fsp_err_t iic_b_master_run_hw_master (iic_b_master_instance_ctrl_t * const p_ctrl) +{ + /* Check if this is a new transaction or a continuation */ + if (!p_ctrl->restarted) + { + /* If bus is busy, return error */ + FSP_ERROR_RETURN((R_I3C0_BCST_BFREF_Msk == (p_ctrl->p_reg->BCST & R_I3C0_BCST_BFREF_Msk)), FSP_ERR_IN_USE); + + /* This is not a restarted transaction. Enable TXI for the next transfer. + * This had been disabled at the end of TXI interrupt. + */ + p_ctrl->p_reg->NTIE = IIC_B_MASTER_PRV_NTIE_INIT_MASK; + } + + /* Initialize fields used during transfer */ + p_ctrl->addr_loaded = 0U; + p_ctrl->loaded = 0U; + p_ctrl->remain = p_ctrl->total; + p_ctrl->addr_remain = p_ctrl->addr_total; + p_ctrl->err = false; + p_ctrl->dummy_read_completed = false; + p_ctrl->activation_on_rxi = false; + p_ctrl->activation_on_txi = false; + p_ctrl->address_restarted = false; + + /* This gets disabled in case the previous transaction issues a restart. + * Set TOHCTL to enable timeouts when SCLn is high. (Non configurable) + * Set TOLCTL based on user settings. + * Set TODTS based on user settings. Only 14 (SHORT) and 16 (LONG) bit counters are allowed. + * (see Section "TMOCTL : Timeout Control Register" description in the IIC section of the relevant hardware manual). + */ + p_ctrl->p_reg->TMOCTL = (uint32_t) (R_I3C0_TMOCTL_TOHCTL_Msk | + (uint32_t) (IIC_B_MASTER_TIMEOUT_MODE_SHORT == + ((iic_b_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + timeout_mode) | + (uint32_t) (((iic_b_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + timeout_scl_low << R_I3C0_TMOCTL_TOLCTL_Pos)); + + /* Clear error flags in case they are set unexpectedly, e.g stop condition in multil-master use case */ + p_ctrl->p_reg->BST &= (uint32_t) ~(R_I3C0_BST_STCNDDF_Msk | R_I3C0_BST_SPCNDDF_Msk); + + /* Enable START condition and timeout detection + * Enable SPCNDDIE to detect unexpected STOP condition. This is disabled between communication events as it can lead + * to undesired interrupts in multi-master setups. + */ + p_ctrl->p_reg->BSTE = IIC_B_MASTER_PRV_BSTE_INIT_MASK | R_I3C0_BSTE_STCNDDE_Msk | R_I3C0_BSTE_SPCNDDE_Msk | + R_I3C0_BSTE_TODE_Msk; + p_ctrl->p_reg->BIE = IIC_B_MASTER_PRV_BIE_INIT_MASK | R_I3C0_BIE_STCNDDIE_Msk | R_I3C0_BIE_SPCNDDIE_Msk | + R_I3C0_BIE_TODIE_Msk; + + /* If previous transaction did not end with restart, send a start condition */ + if (!p_ctrl->restarted) + { + /* Request IIC to issue the start condition */ + p_ctrl->p_reg->CNDCTL = (uint32_t) R_I3C0_CNDCTL_STCND_Msk; + } + else + { + p_ctrl->restarted = false; + + /* Enable NTSTE.TDBEE0. This is treated differently to support restart functionality. + * The TXI status interrupt logging (NTSTE.TDBEE0) had been disabled + * before setting the RS bit by the previous restart enabled transaction + * (As a part of TEI interrupt handling). + * + * In case the previous IIC master transaction enabled restart, + * PRSST.CRMS = 1 and PRSST.TRMD = 1 at this point. + * With the above condition, Once NTSTE.TDBEE0 is set, NTST.TDBEF0 will get set enabling the + * pulse triggered IICn_TXI interrupt. + * See Section 27.3.1.1.1 'Master Mode Operation', '(1) I2C Master Operation', + * '(a) Data Write Transfer (Single Buffer transfer)' point #2. + * AND + * Table "Interrupt Generation" in the IIC section of the relevant hardware manual. + * + */ + p_ctrl->p_reg->NTSTE = (uint32_t) IIC_B_MASTER_PRV_NTSTE_INIT_MASK; + } + + /* + * The Flowchart "Master Mode Communication Flow" + * in the IIC section of the relevant hardware manual is covered in the interrupts: + * + * 1. NACKF processing is handled in the ERI interrupt. + * For receive, dummy reading NTDTBP0 is not required because the NACK processing in this driver resets the IIC peripheral. + * 2. Data is written to NTDTBP0 in the transmit interrupt (TDRE is set when a transmit interrupt fires). + * 3. For transmit, stop is issued in the transmit end interrupt (TEND is set when a transmit end interrupt fires). + * 4. For transmit, ICSR2 is cleared in the transmit end interrupt. + * 5. For receive, remaining processing including reading NTDTBP0 happens in the receive interrupt (ACKTWE is set when a receive interrupt fires). + */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Handles the receive data full interrupt when operating as a master. + * + * @param[in] p_ctrl The target IIC block's control block. + **********************************************************************************************************************/ +static void iic_b_master_rxi_master (iic_b_master_instance_ctrl_t * p_ctrl) +{ + volatile uint32_t dummy_read; + + /* First receive interrupt: Handle the special case of 1 or 2 byte read here */ + if (false == p_ctrl->dummy_read_completed) + { + /* Enable RWE for 1 or 2 byte read */ + if (2U >= p_ctrl->total) + { + p_ctrl->p_reg->SCSTRCTL = R_I3C0_SCSTRCTL_RWE_Msk; + } + + /* Enable NACK for 1 byte read */ + if (1U == p_ctrl->remain) + { + /* Writes to be done together with write protect bit. + * See "ACKCTL : Acknowledge Control Register" description + * in the IIC section of the relevant hardware manual. + */ + p_ctrl->p_reg->ACKCTL = (uint32_t) (R_I3C0_ACKCTL_ACKTWP_Msk | R_I3C0_ACKCTL_ACKT_Msk); + } + +#if IIC_B_MASTER_CFG_DTC_ENABLE + uint32_t volatile const * p_iic_b_master_rx_buffer = &(p_ctrl->p_reg->NTDTBP0); + + /* Enable transfer support if possible */ + if ((NULL != p_ctrl->p_cfg->p_transfer_rx) && (p_ctrl->read) && (p_ctrl->total > 3U)) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + (uint8_t *) (p_iic_b_master_rx_buffer), + (void *) (p_ctrl->p_buff), + (uint16_t) (p_ctrl->total - 3U)); + + p_ctrl->remain = 3U; + p_ctrl->loaded = p_ctrl->total - 3U; + p_ctrl->activation_on_rxi = true; + } +#endif + + if (((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + + /* Do a dummy read to clock the data into the NTDTBP0. */ + dummy_read = p_ctrl->p_reg->NTDTBP0; + FSP_PARAMETER_NOT_USED(dummy_read); + + p_ctrl->dummy_read_completed = true; + } + +#if IIC_B_MASTER_CFG_DTC_ENABLE + + /* If this is the interrupt that got fired after DTC transfer, + * ignore it as the DTC has already taken care of the data transfer */ + else if (true == p_ctrl->activation_on_rxi) + { + p_ctrl->activation_on_rxi = false; + } +#endif + + /* NTDTBP0 contains valid received data */ + else if (0U < p_ctrl->remain) + { + if (((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + + iic_b_master_rxi_read_data(p_ctrl); + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Handles the transmit data empty interrupt when operating as a master. + * + * @param[in] p_ctrl The target IIC block's control block. + **********************************************************************************************************************/ +static void iic_b_master_txi_master (iic_b_master_instance_ctrl_t * p_ctrl) +{ + uint32_t timeout_count = IIC_B_MASTER_PERIPHERAL_REG_MAX_WAIT; + + /* Check if we are issuing the slave address */ + if (0U < p_ctrl->addr_remain) + { + iic_b_master_txi_send_address(p_ctrl); + } + else if (!p_ctrl->read) + { + /* If previous event is an error event and this TXI is triggered by ERI, do not invoke SMBus callback. Because + * the internal function which used to issue callback will clear the error flag in the control block and cause + * incorrect behavior at ERI event after this TXI. + * + * Number of loaded byte must larger or equal to 1 because it helps to ensure that SMBus callback only be invoked + * after slave addess already transmitted (omit first 2 TDRE raise event). + */ + if ((((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) && + ((!p_ctrl->err) && (0U < p_ctrl->loaded))) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + +#if IIC_B_MASTER_CFG_DTC_ENABLE + + /* If this is the interrupt that got fired after DTC transfer, + * ignore it as the DTC has already taken care of the data transfer */ + if (true == p_ctrl->activation_on_txi) + { + p_ctrl->activation_on_txi = false; + } + else if (p_ctrl->remain > 0U) +#else + if (p_ctrl->remain > 0U) +#endif + { +#if BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA + + /* Confirm that PRSTDBG.SCILV = 0 (check the status of SCL) before writing the transmission data. + * Please refer to "I2C Master Transmission Flow (Single Buffer Transfer)" in the I3C Bus Interface section of the relevant hardware manual for details. + */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->PRSTDBG_b.SCILV, 0); +#endif + + /* Write the data to NTDTBP0 register */ + p_ctrl->p_reg->NTDTBP0 = p_ctrl->p_buff[p_ctrl->loaded]; + + /* Update the number of bytes remaining for next pass */ + p_ctrl->loaded++; + p_ctrl->remain--; + } + else + { + /* Do nothing */ + } + + /* We are done loading NTDTBP0, wait for TEND to send a stop/restart */ + if (0U == p_ctrl->remain) + { + /* Disable Normal Transmit Data Buffer Empty Interrupt keeping other settings unchanged. */ + p_ctrl->p_reg->NTIE = (uint32_t) R_I3C0_NTIE_RDBFIE0_Msk; + + /* Wait for the value to reflect at the peripheral. + * See "Interrupt sources" in the I3C section of the relevant hardware manual + * : I2C I3C unified IP (R-I3C v2) */ + IIC_B_MASTER_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->NTIE_b.TDBEIE0, 0U, timeout_count); + + /* Enable the transmit end IRQ, to issue a STOP or RESTART */ + /* Clear any pending TEND interrupts */ + R_BSP_IrqClearPending(p_ctrl->p_cfg->tei_irq); + + /* Enable the TXEND interrupt */ + p_ctrl->p_reg->BIE_b.TENDIE = 1U; + + /* No need to wait to check TENDIE has actually become 1U; because if that's not the case, + * no other operation can occur at this point */ + } + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Handles the transmit end interrupt when operating as a master. + * @note This interrupt is configured to be generated at the end of last byte of the requested transfer. + * + * @param[in] p_ctrl The target IIC block's control block. + **********************************************************************************************************************/ +static void iic_b_master_tei_master (iic_b_master_instance_ctrl_t * p_ctrl) +{ + uint32_t timeout_count = IIC_B_MASTER_PERIPHERAL_REG_MAX_WAIT; + + if (((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + + /* This is a 10 bit address read, issue a restart prior to the last address byte transmission */ + if ((p_ctrl->read) && (p_ctrl->addr_remain == 1U) && (false == p_ctrl->address_restarted)) + { +#if IIC_B_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE + + /* Disable TXI interrupt logging to fire it from eri after restart is detected on the bus. */ + p_ctrl->p_reg->NTSTE = (uint32_t) R_I3C0_NTSTE_RDBFE0_Msk; + + /* Request IIC to issue the restart condition */ + p_ctrl->p_reg->CNDCTL = (uint32_t) R_I3C0_CNDCTL_SRCND_Msk; + p_ctrl->address_restarted = true; +#endif + } + /* We are done with the transfer, send STOP or RESTART */ + else if (0U == p_ctrl->remain) + { + /* Send RESTART */ + if (p_ctrl->restart) + { + /* NTIE.TDBEIE0 would be disabled at this point from the previous TXI. Enable it */ + p_ctrl->p_reg->NTIE = IIC_B_MASTER_PRV_NTIE_INIT_MASK; + + /* Disable NTSTE.TDBEE0 + * This diables the functionality of NTST.TDBEF0. + * Once 'SR' is detected on the bus, PRSST.CRMS and PRSST.TRMD will get set leaving NTST.TDBEF0 cleared. + * Upon the next Read/Write API call, NTSTE.TDBEE0 will be enabled setting the NTST.TDBEF0 bit. + * This will allow IICn_TXI to fire where the slave address will be sent. + */ + p_ctrl->p_reg->NTSTE = (uint32_t) R_I3C0_NTSTE_RDBFE0_Msk; + + /* Request IIC to issue the restart condition. + * This will only fire ERI interrupt invoking a user callback + * which informs that this transaction is completed. + */ + p_ctrl->p_reg->CNDCTL = (uint32_t) R_I3C0_CNDCTL_SRCND_Msk; + + /* Disable timeout function. This will get re-enabled by the next read/write API */ + p_ctrl->p_reg->BSTE_b.TODE = 0U; + + /* Remember that we issued a restart for the next transfer */ + p_ctrl->restarted = true; + } + /* Send STOP */ + else + { + /* Clear STOP flag and set SP */ + p_ctrl->p_reg->BST_b.SPCNDDF = 0U; + + /* Request IIC to issue the stop condition */ + p_ctrl->p_reg->CNDCTL = (uint32_t) R_I3C0_CNDCTL_SPCND_Msk; + } + } + else + { + /* Do nothing */ + } + + /* Disable the interrupt as we are done with the transfer */ + p_ctrl->p_reg->BST_b.TENDF = 0U; + p_ctrl->p_reg->BIE_b.TENDIE = 0U; + + /* Wait for the value to reflect at the peripheral. + * See "Interrupt sources" in the I3C section of the relevant hardware manual + * : I2C I3C unified IP (R-I3C v2) */ + IIC_B_MASTER_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->BIE_b.TENDIE, 0U, timeout_count); +} + +/*******************************************************************************************************************//** + * Handles the error interrupts when operating as a master. + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void iic_b_master_err_master (iic_b_master_instance_ctrl_t * p_ctrl) +{ + /* Clear all the event flags except the receive data full, transmit end and transmit data empty flags*/ + uint32_t errs_events = IIC_B_MASTER_PRV_BST_ERR_STATUS_MASK & p_ctrl->p_reg->BST; + p_ctrl->p_reg->BST &= (uint32_t) ~IIC_B_MASTER_PRV_BST_ERR_STATUS_MASK; + + /* If the event was an error event, then handle it */ + if ((errs_events & + (uint32_t) ((uint32_t) (R_I3C0_BST_TODF_Msk) | (uint32_t) (R_I3C0_BST_ALF_Msk))) | + ((errs_events & (uint32_t) (R_I3C0_BST_NACKDF_Msk)) && (1U != p_ctrl->p_reg->PRSST_b.CRMS))) + { + /* Set the error flag when an error event occurred: + * Conditions to get here: + * 1. This is Timeout and/or arbitration loss error during an ongoing transaction + * 2. This is a NACK error and this device is no longer the active master on the bus. + * The MST bit here can get cleared: + * a. In case of an arbitration loss error.also occurs. + * b. If the slave timeout is lesser than master timeout and the slave releases + * the bus by performing an internal reset. + * See Clearing conditions for CRMS in "PRSST : Present State Register" description + * in the IIC section of the relevant hardware manual. + * 3. This is a Timeout error after attempting to issue a stop after detecting a NACK previously. + */ + p_ctrl->err = true; + + /* Abort an in-progress transfer with the current device */ + iic_b_master_abort_seq_master(p_ctrl, true); /* This will reset the IIC Master driver */ + /* Notify anyone waiting that the transfer is Aborted due to error. */ + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED); + } + else if ((errs_events & (uint32_t) (R_I3C0_BST_NACKDF_Msk)) && (1U == p_ctrl->p_reg->PRSST_b.CRMS)) + { + /* CRMS bit must be set to issue a stop condition. + * See "Issuing a Stop Condition" in the I3C section of the relevant hardware manual. + * : I2C I3C unified IP (R-I3C v2) + *//* Set the error flag when an error event occurred + * This will be checked after the stop condition is detected from the request below. */ + p_ctrl->err = true; + + /* The sequence below is to handle a NACK received from slave in the middle of a write. + * See item '[4]' under the figure "Example of I2C master transmission flowchart" + * in the IIC section of the relevant hardware manual. */ + + /* Request IIC to issue the stop condition */ + p_ctrl->p_reg->CNDCTL = (uint32_t) R_I3C0_CNDCTL_SPCND_Msk; /* It is safe to write 0's to other bits. */ + /* Allow timeouts to be generated on the low value of SCL using either long or short mode */ + + p_ctrl->p_reg->TMOCTL = (uint32_t) (R_I3C0_TMOCTL_TOHCTL_Msk | + (uint32_t) (IIC_B_MASTER_TIMEOUT_MODE_SHORT == + ((iic_b_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + timeout_mode) + | + (uint32_t) (1U << R_I3C0_TMOCTL_TOLCTL_Pos)); + + p_ctrl->p_reg->BIE_b.TODIE = 1U; + + /* This interrupt will be fired again when wither stop condition is sent + * or the hardware detects the line is stuck low causing a timeout */ + } + /* This is a STOP, START or RESTART event. We need to process these events only at the + * end of the requisite transfers. + * NOTE: Do not use p_transfer->loaded or p_transfer->remain to check whether the transfer is + * completed, since using them would lead to a race condition between txi and eri interrupts in case + * of one byte transfer which will result in BUS arbitration loss error */ + else if ((errs_events & (uint8_t) R_I3C0_BST_SPCNDDF_Msk) || + ((p_ctrl->restarted) && (errs_events & (uint8_t) R_I3C0_BST_STCNDDF_Msk))) + { + i2c_master_event_t event = I2C_MASTER_EVENT_ABORTED; + if ((0 == p_ctrl->remain) && (false == p_ctrl->err)) /* Successful transaction */ + { + /* Get the correct event to notify the user */ + event = (p_ctrl->read) ? I2C_MASTER_EVENT_RX_COMPLETE : I2C_MASTER_EVENT_TX_COMPLETE; + + /* Disable STIE/SPIE to prevent errant interrupts in multi-master scenarios */ + p_ctrl->p_reg->BIE = IIC_B_MASTER_PRV_BIE_INIT_MASK; + } + else if ((errs_events & (uint8_t) R_I3C0_BST_SPCNDDF_Msk)) + { + /* This is the STOP condition requested due to a NACK error earlier. + * Since the stop condition is successfully issued there is no need to reset the driver. + */ + iic_b_master_abort_seq_master(p_ctrl, false); /* Clear the transaction flags only */ + } + else + { + /* Do nothing */ + } + + /* Notify anyone waiting */ + iic_b_master_notify(p_ctrl, event); + } + else if ((p_ctrl->read) && (p_ctrl->addr_remain == 1U) && (true == p_ctrl->address_restarted)) + { + /* NTIE.TDBEIE0 would be disabled at this point from the previous TXI + * (Which happened just before the TEI that caused the restart condition). + * Enable it */ + p_ctrl->p_reg->NTIE = IIC_B_MASTER_PRV_NTIE_INIT_MASK; + + /* Restart has been detected (after first 2 address bytes of 10-bit slave address format are sent). + * This is a request to read, send 3rd byte of 10-bit slave address. */ + p_ctrl->p_reg->NTSTE = (uint32_t) IIC_B_MASTER_PRV_NTSTE_INIT_MASK; + } + else if (errs_events & (uint8_t) R_I3C0_BST_STCNDDF_Msk) + { + if (((iic_b_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_b_master_notify(p_ctrl, I2C_MASTER_EVENT_START); + } + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Check valid receive data and set RWE, NACK and STOP/RESTART bit in RXI handler. + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void iic_b_master_rxi_read_data (iic_b_master_instance_ctrl_t * const p_ctrl) +{ + /* If next data = (final byte - 2), enable RWE */ + if (3U == p_ctrl->remain) + { + p_ctrl->p_reg->SCSTRCTL = R_I3C0_SCSTRCTL_RWE_Msk; + } + /* If next data = (final byte - 1), enable NACK */ + else if (2U == p_ctrl->remain) + { + /* Writes to be done together with write protect bit. + * See "ACKCTL : Acknowledge Control Register" description + * in the IIC section of the relevant hardware manual. + */ + p_ctrl->p_reg->ACKCTL = (uint32_t) (R_I3C0_ACKCTL_ACKTWP_Msk | R_I3C0_ACKCTL_ACKT_Msk); + } + /* If next data = final byte, send STOP or RESTART */ + else if (1U == p_ctrl->remain) + { + if (p_ctrl->restart) + { + /* NOTE: Only disable NTSTE.TDBEE0 (leaving NTIE.TDBEIE0 enabled). + * This will allow the interrupt to fire in the "restarted" (next) + * transaction when NTSTE.TDBEE0 is re-enabled. + * NTIE.TDBEIE0 should be already enabled as this is a read transfer. + */ + p_ctrl->p_reg->NTSTE = (uint32_t) R_I3C0_NTSTE_RDBFE0_Msk; + + /* This bit clears to 0 automatically by issuing stop condition. + * For restart condition, clear bit by software. + */ + p_ctrl->p_reg->ACKCTL = (uint32_t) (R_I3C0_ACKCTL_ACKTWP_Msk); + + /* Request IIC to issue the restart condition */ + p_ctrl->p_reg->CNDCTL = (uint32_t) R_I3C0_CNDCTL_SRCND_Msk; + + /* Disable timeout function */ + p_ctrl->p_reg->BIE_b.TODIE = 0U; + + /* Remember that we issued a restart when doing the next transfer */ + p_ctrl->restarted = true; + } + else + { + /* Clear STOP flag and set SP. + * It is ok to clear other status' as this transaction is over. + */ + p_ctrl->p_reg->BST_b.SPCNDDF = 0U; + + /* Request IIC to issue the stop condition */ + + p_ctrl->p_reg->CNDCTL = (uint32_t) R_I3C0_CNDCTL_SPCND_Msk; /* It is safe to write 0's to other bits. */ + + /* STOP flag will not be set just yet. STOP will be set only after reading the + * last byte from NTDTBP0 and clearing the RWE. + * See Point #7 under "Master Mode Operation, (1) I2C Master Operation, + * (b) Data Read Transfer (Single Buffer transfer)" in the IIC section of the relevant hardware manual. + */ + } + } + else + { + /* Do nothing */ + } + + volatile uint32_t read_data = p_ctrl->p_reg->NTDTBP0; + p_ctrl->p_buff[p_ctrl->loaded] = (uint8_t) read_data; + + /* Update the counter values */ + p_ctrl->loaded++; + p_ctrl->remain--; + + /* If we are done with the reception, clear the RWE bit */ + if (0U == p_ctrl->remain) + { + p_ctrl->p_reg->SCSTRCTL = 0; + + /* If this transaction does not have the restart flag set to true, + * last byte has been read and RWE has been cleared. + * Callback will be issued by the ERI once the stop condition is detected + * In case of restart flag set to true a callback will be issued by the ERI once the start + * (from restart) condition is detected + */ + } +} + +/*******************************************************************************************************************//** + * Write the address byte to the iic bus + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void iic_b_master_txi_send_address (iic_b_master_instance_ctrl_t * const p_ctrl) +{ + /* This is a 10 bit read and we have transmitted the low byte, next is restart */ + if ((3U == p_ctrl->addr_total) && (2U == p_ctrl->addr_loaded) && (false == p_ctrl->address_restarted)) + { +#if IIC_B_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE + uint32_t timeout_count = IIC_B_MASTER_PERIPHERAL_REG_MAX_WAIT; + + /* For Read operation an extra address byte needs to be sent after issuing restart. + * At this point we have sent the first 2 address bytes. Disable TXI. + */ + p_ctrl->p_reg->NTIE = (uint32_t) R_I3C0_NTIE_RDBFIE0_Msk; + + /* Wait for the value to reflect at the peripheral. + * See "Interrupt sources" in the I3C section of the relevant hardware manual. + * : I2C I3C unified IP (R-I3C v2) */ + IIC_B_MASTER_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->NTIE_b.TDBEIE0, 0U, timeout_count); + + /* Enable the transmit end IRQ, so that we can generate a RESTART condition */ + /* Clear any pending TEND interrupts */ + R_BSP_IrqClearPending(p_ctrl->p_cfg->tei_irq); + + /* Enable the TXEND interrupt */ + p_ctrl->p_reg->BIE_b.TENDIE = 1U; + + /* No need to wait to check TEIE has actually become 1U; because if that's not the case, + * no other operation can occur at this point */ +#endif + } + else + { + /* Address low byte, this could either be a 7 bit address or low byte of 10 bit address */ + uint8_t address_byte = p_ctrl->addr_low; +#if IIC_B_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE + + /* 10 bit address, handle accordingly */ + if (p_ctrl->addr_total > 1U) + { + /* MSB transfer, send address high byte with with R/W set to 0 */ + if (0U == p_ctrl->addr_loaded) + { + address_byte = p_ctrl->addr_high; + } + /* MSB transfer after restart of 10 bit read, send high byte with R/W set to 1 */ + else if ((2U == p_ctrl->addr_loaded) && (3U == p_ctrl->addr_total)) + { + address_byte = p_ctrl->addr_high | (uint8_t) I2C_CODE_READ; + } + /* Low byte transfer */ + else + { + address_byte = p_ctrl->addr_low; + } + } +#endif + +#if IIC_B_MASTER_CFG_DTC_ENABLE + uint32_t volatile const * p_iic_b_master_tx_buffer = &(p_ctrl->p_reg->NTDTBP0); + + /* If this is the last address byte, enable transfer */ + if (1U == p_ctrl->addr_remain) + { + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && !(p_ctrl->read) && (p_ctrl->total > 0U)) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->reset(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + (void *) (p_ctrl->p_buff), + (uint8_t *) (p_iic_b_master_tx_buffer), + (uint16_t) (p_ctrl->remain)); + p_ctrl->remain = 0U; + p_ctrl->loaded = p_ctrl->total; + p_ctrl->activation_on_txi = true; + } + } +#endif + +#if BSP_FEATURE_IIC_B_CHECK_SCILV_BEFORE_MASTER_WRITE_TX_DATA + + /* Confirm that PRSTDBG.SCILV = 0 (check the status of SCL) before writing the transmission data. + * Please refer to "I2C Master Transmission Flow (Single Buffer Transfer)" in the I3C Bus Interface section of the relevant hardware manual for details. + */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->PRSTDBG_b.SCILV, 0); +#endif + + /* Write the address byte */ + p_ctrl->p_reg->NTDTBP0 = address_byte; + + /* Update the number of address bytes loaded for next pass */ + p_ctrl->addr_loaded++; + p_ctrl->addr_remain--; + } +} + +#if IIC_B_MASTER_CFG_DTC_ENABLE + +/*******************************************************************************************************************//** + * Configures IIC related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to IIC specific control structure + * @param[in] p_cfg Pointer to IIC specific configuration structure + * + * @retval FSP_SUCCESS Transfer interface initialized successfully. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL. + **********************************************************************************************************************/ +static fsp_err_t iic_b_master_transfer_open (i2c_master_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + if (NULL != p_cfg->p_transfer_rx) + { + err = iic_b_master_transfer_configure(p_cfg->p_transfer_rx, IIC_B_MASTER_TRANSFER_DIR_READ); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (NULL != p_cfg->p_transfer_tx) + { + err = iic_b_master_transfer_configure(p_cfg->p_transfer_tx, IIC_B_MASTER_TRANSFER_DIR_WRITE); + if (FSP_SUCCESS != err) + { + if (NULL != p_cfg->p_transfer_rx) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + + return err; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures IIC RX related transfer. + * @param[in] p_ctrl Pointer to IIC specific control structure + * @param[in] p_cfg Pointer to IIC specific configuration structure + * + * @retval FSP_SUCCESS Transfer interface is configured with valid parameters. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL. + **********************************************************************************************************************/ +static fsp_err_t iic_b_master_transfer_configure (transfer_instance_t const * p_transfer, + iic_b_master_transfer_dir_t direction) +{ + fsp_err_t err; + + /* Set default transfer info and open receive transfer module, if enabled. */ + #if (IIC_B_MASTER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + #endif + transfer_info_t * p_cfg = p_transfer->p_cfg->p_info; + if (IIC_B_MASTER_TRANSFER_DIR_READ == direction) + { + p_cfg->transfer_settings_word = IIC_B_MASTER_DTC_RX_TRANSFER_SETTINGS; + } + else + { + p_cfg->transfer_settings_word = IIC_B_MASTER_DTC_TX_TRANSFER_SETTINGS; + } + + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); + + return FSP_SUCCESS; +} + +#endif + +/*********************************************************************************************************************** + * Interrupt Vectors + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Receive data full interrupt routine. + * + * This function implements the IIC Receive buffer full ISR routine. + * + **********************************************************************************************************************/ +void iic_b_master_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + iic_b_master_rxi_master(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Transmit data empty interrupt routine. + * + * This function implements the Transmit buffer empty ISR routine. + * + **********************************************************************************************************************/ +void iic_b_master_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + iic_b_master_txi_master(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Transmit end interrupt routine. + * + * This function implements the IIC Transmission End ISR routine. + * + **********************************************************************************************************************/ +void iic_b_master_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + iic_b_master_tei_master(p_ctrl); + + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Error and event interrupt routine. + * + * This function implements the IIC Event/Error. + * + **********************************************************************************************************************/ +void iic_b_master_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_b_master_instance_ctrl_t * p_ctrl = (iic_b_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + iic_b_master_err_master(p_ctrl); + + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_master/r_iic_master.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_master/r_iic_master.c new file mode 100644 index 0000000000..3e212bd0f0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_master/r_iic_master.c @@ -0,0 +1,1618 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_iic_master.h" +#if IIC_MASTER_CFG_DTC_ENABLE + #include "r_dtc.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "IIC" in ASCII, used to determine if channel is open. */ +#define IIC_MASTER_OPEN (0x52494943U) + +#define I2C_CODE_READ (0x01U) +#define I2C_CODE_10BIT (0xF0U) + +/* The timeout interrupt enable bit */ +#define IIC_MASTER_TMO_EN_BIT (0x01) + +/* The arbitration loss detection interrupt enable bit */ +#define IIC_MASTER_ALD_EN_BIT (0x02) + +/* The start condition detection interrupt enable bit */ +#define IIC_MASTER_STR_EN_BIT (0x04) + +/* The stop condition detection interrupt enable bit */ +#define IIC_MASTER_STP_EN_BIT (0x08) + +/* The NAK reception interrupt enable bit */ +#define IIC_MASTER_NAK_EN_BIT (0x10) + +/* The receive data full interrupt enable bit */ +#define IIC_MASTER_RXI_EN_BIT (0x20) + +/* The transmit end interrupt enable bit */ +#define IIC_MASTER_TEI_EN_BIT (0x40) + +/* The transmit data empty interrupt enable bit */ +#define IIC_MASTER_TXI_EN_BIT (0x80) + +#define IIC_MASTER_BUS_RATE_REG_RESERVED_BITS (0xE0U) +#define IIC_MASTER_INTERNAL_REF_CLOCK_SELECT_MAX (0x07U) + +#define IIC_MASTER_SLAVE_10_BIT_ADDR_LEN_ADJUST (2U) + +#define IIC_MASTER_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#define IIC_MASTER_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#define IIC_MASTER_FUNCTION_ENABLE_REG_VAL (0x02U) +#define IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK (0xB3U) +#define IIC_MASTER_FUNCTION_ENABLE_INIT_SETTINGS (0x77U) +#define IIC_MASTER_STATUS_REGISTER_2_ERR_MASK (0x1FU) +#define IIC_MASTER_BUS_MODE_REGISTER_1_MASK (0x08U) +#define IIC_MASTER_BUS_MODE_REGISTER_2_MASK (0x04U) +#define IIC_MASTER_SYSDIVCK_ICLK_MASK (0x0F000000U) +#define IIC_MASTER_SYSDIVCK_PCLKB_MASK (0x00000F00U) +#define IIC_MASTER_ICCR1_SCL_SDA_OUTPUT_MASK (0x1FU) +#define IIC_MASTER_ICCR1_ICE_BIT_MASK (0x80) +#define IIC_MASTER_ICCR1_IICRST_BIT_MASK (0x40) +#define IIC_MASTER_ICCR2_SP_BIT_MASK (0x08) +#define IIC_MASTER_ICCR2_RS_BIT_MASK (0x04) +#define IIC_MASTER_ICCR2_ST_BIT_MASK (0x02) + +/* Worst case ratio of (ICLK/PCLKB) = 64 bytes approximately. + * 3 PCLKB cycles is the number of cycles to wait for IICn. + * See Table "Access cycles" in the I/O Registers section of the relevant hardware manual. + */ +#define IIC_MASTER_PERIPHERAL_REG_MAX_WAIT (0x40U * 0x03U) + +#define IIC_MASTER_HARDWARE_REGISTER_WAIT(reg, required_value, timeout) \ + while ((timeout)) \ + { \ + if ((required_value) == (reg)) \ + { \ + break; \ + } \ + (timeout)--; \ + } + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Hardware errors and events that can occur on the IIC */ +typedef enum e_iic_master_err_event +{ + IIC_MASTER_ERR_EVENT_NONE = 0, + IIC_MASTER_ERR_EVENT_TIMEOUT = 1, + IIC_MASTER_ERR_EVENT_ARBITRATION_LOSS = 2, + IIC_MASTER_ERR_EVENT_START = 4, + IIC_MASTER_ERR_EVENT_STOP = 8, + IIC_MASTER_ERR_EVENT_NACK = 16 +} iic_master_err_t; + +/* IIC read/write enumeration */ +typedef enum e_iic_master_transfer_dir_option +{ + IIC_MASTER_TRANSFER_DIR_WRITE = 0x0, + IIC_MASTER_TRANSFER_DIR_READ = 0x1 +} iic_master_transfer_dir_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * iic_master_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile iic_master_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +void iic_master_rxi_isr(void); +void iic_master_txi_isr(void); +void iic_master_tei_isr(void); +void iic_master_eri_isr(void); + +/* Internal helper functions */ +static void iic_master_abort_seq_master(iic_master_instance_ctrl_t * const p_ctrl, bool iic_reset); +static fsp_err_t iic_master_read_write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + iic_master_transfer_dir_t direction); +static void iic_master_notify(iic_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event); + +#if IIC_MASTER_CFG_DTC_ENABLE +static fsp_err_t iic_master_transfer_open(i2c_master_cfg_t const * const p_cfg); +static fsp_err_t iic_master_transfer_configure(transfer_instance_t const * p_transfer, + iic_master_transfer_dir_t direction); + +#endif + +/* Interrupt handlers */ +static void iic_master_rxi_master(iic_master_instance_ctrl_t * p_ctrl); +static void iic_master_txi_master(iic_master_instance_ctrl_t * p_ctrl); +static void iic_master_tei_master(iic_master_instance_ctrl_t * p_ctrl); +static void iic_master_err_master(iic_master_instance_ctrl_t * p_ctrl); + +/* Functions that manipulate hardware */ +static void iic_master_open_hw_master(iic_master_instance_ctrl_t * const p_ctrl, + i2c_master_cfg_t const * const p_cfg); +static fsp_err_t iic_master_run_hw_master(iic_master_instance_ctrl_t * const p_ctrl); +static void iic_master_rxi_read_data(iic_master_instance_ctrl_t * const p_ctrl); +static void iic_master_txi_send_address(iic_master_instance_ctrl_t * const p_ctrl); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* IIC Implementation of I2C device master interface */ +i2c_master_api_t const g_i2c_master_on_iic = +{ + .open = R_IIC_MASTER_Open, + .read = R_IIC_MASTER_Read, + .write = R_IIC_MASTER_Write, + .abort = R_IIC_MASTER_Abort, + .slaveAddressSet = R_IIC_MASTER_SlaveAddressSet, + .close = R_IIC_MASTER_Close, + .statusGet = R_IIC_MASTER_StatusGet, + .callbackSet = R_IIC_MASTER_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup IIC_MASTER + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens the I2C device. + * + * @retval FSP_SUCCESS Requested clock rate was set exactly. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel is not available on this MCU. + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. p_api_ctrl or p_cfg is NULL. + * 2. extended parameter is NULL. + * 3. Callback parameter is NULL. + * 4. Set the rate to fast mode plus on a channel which does not support it. + * 5. Invalid IRQ number assigned + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl; +#if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); + FSP_ASSERT(p_cfg != NULL); + FSP_ASSERT(p_cfg->p_extend != NULL); + FSP_ASSERT(p_cfg->rxi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->eri_irq >= (IRQn_Type) 0); + FSP_ERROR_RETURN(IIC_MASTER_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + FSP_ERROR_RETURN(BSP_FEATURE_IIC_VALID_CHANNEL_MASK & (1 << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* If rate is configured as Fast mode plus, check whether the channel supports it */ + if (I2C_MASTER_RATE_FASTPLUS == p_cfg->rate) + { + FSP_ASSERT((BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK & (1U << p_cfg->channel))); + } +#endif + + p_ctrl->p_reg = (R_IIC0_Type *) ((uint32_t) R_IIC0 + (p_cfg->channel * ((uint32_t) R_IIC1 - (uint32_t) R_IIC0))); + + /* Record the pointer to the configuration structure for later use */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->slave = p_cfg->slave; + p_ctrl->addr_mode = p_cfg->addr_mode; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + p_ctrl->p_buff = NULL; + p_ctrl->total = 0U; + p_ctrl->remain = 0U; + p_ctrl->loaded = 0U; + p_ctrl->read = false; + p_ctrl->restart = false; + p_ctrl->err = false; + p_ctrl->restarted = false; + + R_BSP_MODULE_START(FSP_IP_IIC, p_cfg->channel); + + /* Open the hardware in master mode. Performs IIC initialization as described in hardware manual (see + * "Initial Settings" in the IIC Operation section of the relevant hardware manual). */ + iic_master_open_hw_master(p_ctrl, p_cfg); + +#if IIC_MASTER_CFG_DTC_ENABLE + + /* Open the IIC transfer interface if available */ + fsp_err_t err = iic_master_transfer_open(p_cfg); + if (FSP_SUCCESS != err) + { + R_BSP_MODULE_STOP(FSP_IP_IIC, p_cfg->channel); + + return err; + } +#endif + + p_ctrl->open = IIC_MASTER_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Performs a read from the I2C device. + * The caller will be notified when the operation has completed (successfully) by an + * I2C_MASTER_EVENT_RX_COMPLETE in the callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl, p_dest or bytes is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than uint16_t size (65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_IN_USE Bus busy condition. Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_Read (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart) +{ +#if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); + FSP_ASSERT(bytes != 0U); +#endif + fsp_err_t err = FSP_SUCCESS; + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of iic_master_read_write to 4. */ + ((iic_master_instance_ctrl_t *) p_api_ctrl)->restart = restart; + + /* Call the common helper function to perform I2C Read operation.*/ + err = iic_master_read_write(p_api_ctrl, p_dest, bytes, IIC_MASTER_TRANSFER_DIR_READ); + + return err; +} + +/*******************************************************************************************************************//** + * Performs a write to the I2C device. + * The caller will be notified when the operation has completed (successfully) by an + * I2C_MASTER_EVENT_TX_COMPLETE in the callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_src is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than uint16_t size (65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_IN_USE Bus busy condition. Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_Write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart) +{ +#if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); +#endif + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of iic_master_read_write to 4. */ + ((iic_master_instance_ctrl_t *) p_api_ctrl)->restart = restart; + + /* Call the common helper function to perform I2C Write operation.*/ + return iic_master_read_write(p_api_ctrl, p_src, bytes, IIC_MASTER_TRANSFER_DIR_WRITE); +} + +/*******************************************************************************************************************//** + * Safely aborts any in-progress transfer and forces the IIC peripheral into ready state. + * + * + * @retval FSP_SUCCESS Channel was reset successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_MASTER_Open to initialize the control block. + * + * @note A callback will not be invoked in case an in-progress transfer gets aborted by calling this API. + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_Abort (i2c_master_ctrl_t * const p_api_ctrl) +{ + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl; + +#if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Abort any transfer happening on the channel */ + iic_master_abort_seq_master(p_ctrl, true); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets address and addressing mode of the slave device. + * This function is used to set the device address and addressing mode of the slave + * without reconfiguring the entire bus. + * + * @retval FSP_SUCCESS Address of the slave is set correctly. + * @retval FSP_ERR_ASSERTION Pointer to control structure is NULL. + * @retval FSP_ERR_IN_USE Another transfer was in-progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode) +{ + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Fail if there is already a transfer in progress */ + FSP_ERROR_RETURN(((0 == p_ctrl->remain) && (false == p_ctrl->restart)), FSP_ERR_IN_USE); +#endif + + /* Sets the address of the slave device */ + p_ctrl->slave = slave; + + /* Sets the mode of addressing */ + p_ctrl->addr_mode = addr_mode; + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2c_master_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory) +{ + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl; + +#if (IIC_MASTER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2c_master_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2c_master_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides driver status. + * + * @retval FSP_SUCCESS Status stored in p_status. + * @retval FSP_ERR_ASSERTION NULL pointer. + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_StatusGet (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status) +{ + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl; + +#if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_status != NULL); +#endif + + p_status->open = (IIC_MASTER_OPEN == p_ctrl->open); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes the I2C device. May power down IIC peripheral. + * This function will safely terminate any in-progress I2C transfers. + * + * @retval FSP_SUCCESS Device closed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_MASTER_Open to initialize the control block. + * + * @note A callback will not be invoked in case an in-progress transfer gets aborted by calling this API. + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_Close (i2c_master_ctrl_t * const p_api_ctrl) +{ + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl; + +#if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Abort an in-progress transfer with this device only */ + iic_master_abort_seq_master(p_ctrl, true); + + /* Disable I2C interrupts. Described in hardware manual (see + * "I2C Bus Interrupt Enable Register (ICIER)" description in the IIC section of the relevant hardware manual). */ + p_ctrl->p_reg->ICIER = 0x00; + + /* The device is now considered closed */ + p_ctrl->open = 0U; + +#if IIC_MASTER_CFG_DTC_ENABLE + + /* Close the handles for the transfer interfaces */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + + R_BSP_MODULE_STOP(FSP_IP_IIC, p_ctrl->p_cfg->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IIC_MASTER) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Helper function for handling I2C Read or Write. + * + * @param p_api_ctrl Pointer to control block + * @param p_buffer Pointer to the buffer to store read/write data. + * @param[in] bytes Number of bytes to be read/written. + * @param[in] direction Read or Write + * + * @retval FSP_SUCCESS Function executed successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_buffer is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than UINT16_MAX(= 65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_IN_USE Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +static fsp_err_t iic_master_read_write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + iic_master_transfer_dir_t direction) +{ + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl; + +#if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_buffer != NULL); + FSP_ERROR_RETURN((p_ctrl->open == IIC_MASTER_OPEN), FSP_ERR_NOT_OPEN); + FSP_ASSERT(((iic_master_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); + #if IIC_MASTER_CFG_DTC_ENABLE + + /* DTC on RX could actually receive 65535+3 = 65538 bytes as 3 bytes are handled separately. + * Forcing to 65535 to keep TX and RX uniform with respect to max transaction length via DTC. + */ + FSP_ERROR_RETURN((bytes <= UINT16_MAX), FSP_ERR_INVALID_SIZE); + #endif +#endif + + p_ctrl->p_buff = p_buffer; + p_ctrl->total = bytes; + + /* Handle the (different) addressing mode(s) */ + if (p_ctrl->addr_mode == I2C_MASTER_ADDR_MODE_7BIT) + { + /* Set the address bytes according to a 7-bit slave read command */ + p_ctrl->addr_high = 0U; + p_ctrl->addr_low = (uint8_t) ((p_ctrl->slave << 1U) | (uint8_t) direction); + p_ctrl->addr_total = 1U; + } + +#if IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE + else + { + /* Set the address bytes according to a 10-bit slave read command */ + p_ctrl->addr_high = (uint8_t) (((p_ctrl->slave >> 7U) | I2C_CODE_10BIT) & (uint8_t) ~(I2C_CODE_READ)); + p_ctrl->addr_low = (uint8_t) p_ctrl->slave; + + /* Addr total = 3 for Read and 2 for Write. + * See "Communication Data Format" in the IIC section of the relevant hardware manual. + */ + p_ctrl->addr_total = (uint8_t) ((uint8_t) direction + IIC_MASTER_SLAVE_10_BIT_ADDR_LEN_ADJUST); + } +#endif + + p_ctrl->read = (bool) direction; + + /* Kickoff the read operation as a master */ + return iic_master_run_hw_master(p_ctrl); +} + +/*******************************************************************************************************************//** + * Single point for managing the logic around notifying a transfer has finished. + * + * @param[in] p_ctrl Pointer to transfer that is ending. + * @param[in] event The event code to pass to the callback. + **********************************************************************************************************************/ +static void iic_master_notify (iic_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event) +{ + i2c_master_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2c_master_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_ctrl->p_context; + p_args->event = event; + +#if IIC_MASTER_CFG_DTC_ENABLE + + /* Stop any DTC assisted transfer for tx */ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if ((NULL != p_transfer_tx) && (!p_ctrl->read)) + { + p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + } + + /* Stop any DTC assisted transfer for rx */ + const transfer_instance_t * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if ((NULL != p_transfer_rx) && (p_ctrl->read)) + { + p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); + } +#endif + + /* Now do the callback here */ +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + iic_master_prv_ns_callback p_callback = (iic_master_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } + + /* Clear the err flags */ + p_ctrl->err = false; +} + +/*******************************************************************************************************************//** + * Single point for managing the logic around aborting a transfer when operating as a master. + * + * @param[in] p_ctrl Pointer to control structure of specific device. + * @param[in] iic_reset Flag to enable IIC reset + **********************************************************************************************************************/ +static void iic_master_abort_seq_master (iic_master_instance_ctrl_t * const p_ctrl, bool iic_reset) +{ + /* Safely stop the hardware from operating. */ + + /* Reset the peripheral */ + if (true == iic_reset) + { + /* Disable channel interrupts */ + p_ctrl->p_reg->ICIER = 0x00; + + /* This helper function would do a full IIC reset + * followed by re-initializing the required peripheral registers. */ + iic_master_open_hw_master(p_ctrl, p_ctrl->p_cfg); + } + + /* Update the transfer descriptor to show no longer in-progress and an error */ + p_ctrl->remain = 0U; + + /* Update the transfer descriptor to make sure interrupts no longer process */ + p_ctrl->addr_loaded = p_ctrl->addr_total; + p_ctrl->loaded = p_ctrl->total; + p_ctrl->restarted = false; + p_ctrl->restart = false; + + /* Enable Interrupts: TMOIE, ALIE, NAKIE, RIE, TIE. + * Disable Interrupt: TEIE, STIE, SPIE + * (see "I2C Bus Interrupt Enable Register (ICIER)" description in the IIC section of the relevant hardware manual). + */ + p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK; +} + +/*******************************************************************************************************************//** + * Performs the hardware initialization sequence when operating as a master (see + * "Initial Settings" in the IIC Operation section of the relevant hardware manual). + * + * @param[in] p_ctrl Pointer to IIC specific control structure + * @param[in] p_cfg Pointer to IIC specific configuration structure. + **********************************************************************************************************************/ +static void iic_master_open_hw_master (iic_master_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + /* Perform IIC reset */ + /* S1. Set the ICCR1.ICE bit to 0 to set the SCLn and SDAn pins to the inactive state. */ + p_ctrl->p_reg->ICCR1 = 0; + + /* S2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset. */ + p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_MASTER_ICCR1_IICRST_BIT_MASK); + + /* Wait for IICRST to be set. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->ICCR1_b.IICRST, 1U); + + /* S3. Set the ICCR1.ICE bit to 1 to initiate internal reset. */ + p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_MASTER_ICCR1_ICE_BIT_MASK | IIC_MASTER_ICCR1_IICRST_BIT_MASK); + + /* S4. Set other registers as required. */ + + /* Configure the clock settings. This is set in the configuration structure by the tooling. */ + /* Set the number of counts that the clock remains low, bit 7 to 5 should be written as 1 */ + p_ctrl->p_reg->ICBRL = + (uint8_t) (IIC_MASTER_BUS_RATE_REG_RESERVED_BITS | + ((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->clock_settings.brl_value); + + /* Set the number of counts that the clock remains high, bit 7 to 5 should be written as 1 */ + p_ctrl->p_reg->ICBRH = (uint8_t) (IIC_MASTER_BUS_RATE_REG_RESERVED_BITS | + ((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->clock_settings.brh_value); + + /* Set the internal reference clock source for generating IIC clock */ + p_ctrl->p_reg->ICMR1 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_1_MASK | + (uint8_t) ((((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + clock_settings. + cks_value & + IIC_MASTER_INTERNAL_REF_CLOCK_SELECT_MAX) << 4U)); + + /* Allow timeouts to be generated on the low value of SCL using either long or short mode */ + + /* TMOL 'Timeout L Count Control' and TMOH 'Timeout H Count Control' will be set at the time of I2C reset. + * This will enable time out detection for both SCLn high and low. + * Only Set/Clear TMOS here to select long or short mode. + * (see "I2C Bus Mode Register 2 (ICMR2)" description in the IIC section of the relevant hardware manual). + */ + p_ctrl->p_reg->ICMR2 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_2_MASK | + (uint8_t) (IIC_MASTER_TIMEOUT_MODE_SHORT == + ((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->timeout_mode) + | + (uint8_t) (((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + timeout_scl_low << R_IIC0_ICMR2_TMOL_Pos)); + + /* ICFER Register Settings: + * 1. Enable timeout function. + * 2. Enable master arbitration loss detection. + * 3. Enable NACK arbitration loss detection. + * 4. Disable Slave arbitration loss detection. + * 5. Enable NACK reception transfer suspension. + * 6. Use the digital noise filter circuit. Upon I2C reset, 'NF[1:0] Noise Filter Stage Select' will be set to 0x00 + * This would imply 'Filter out noise of up to 1 IIC cycle (single-stage filter)' + * (see "I2C Bus Mode Register 3 (ICMR3)" description in the IIC section of the relevant hardware manual). + * 7. Do not use the SCL synchronous circuit. + * 8. Enable FM+ slope circuit if fast mode plus is enabled. + * (see "I2C Bus Function Enable Register" description in the IIC section of the relevant hardware manual). + */ + p_ctrl->p_reg->ICFER = + (uint8_t) ((uint8_t) (I2C_MASTER_RATE_FASTPLUS == + p_ctrl->p_cfg->rate) << 7U) | IIC_MASTER_FUNCTION_ENABLE_INIT_SETTINGS; + + /* Ensure the HW is in master mode and does not behave as a slave to another master on the same channel. */ + p_ctrl->p_reg->ICSER = 0x00; + + /* Enable Interrupts: TMOIE, ALIE, NAKIE, RIE, TIE. + * Disable Interrupt: TEIE, STIE, SPIE + * (see "I2C Bus Interrupt Enable Register (ICIER)" description in the IIC section of the relevant hardware manual). + */ + p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK; + + /* Set valid interrupt contexts and user provided priority. Enable the interrupts at the NVIC */ + R_BSP_IrqCfgEnable(p_cfg->eri_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->tei_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->ipl, p_ctrl); + + /* S5. Set the ICCR1.IICRST bit to 0 to release the IIC reset. */ + p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_MASTER_ICCR1_ICE_BIT_MASK | IIC_MASTER_ICCR1_SCL_SDA_OUTPUT_MASK); +} + +/*******************************************************************************************************************//** + * Performs the data transfer described by the parameters when operating as a master. + * See "Master Transmit Operation" and "Master Receive Operation" + * in the IIC section of the relevant hardware manual. + * + * @param[in] p_ctrl Pointer to control structure of specific device. + * + * @retval FSP_SUCCESS Data transfer success. + * @retval FSP_ERR_IN_USE If data transfer is in progress. + **********************************************************************************************************************/ +static fsp_err_t iic_master_run_hw_master (iic_master_instance_ctrl_t * const p_ctrl) +{ + /* IICn operates using PCLKB. The ratio ICLK (System Clock)/PCLKB gives the CPU cycles for 1 ICBRL count. + * (ICLK/PCLKB)*ICBRL gives the CPU cycles for entire ICBRL count. + * Since each time we loop the timeout count will be decremented by 1 this would require at least 4 CPU clocks, + * making the final timeout count as: + * Timeout = ((ICLK/PCLKB)*ICBRL)/4. + */ + volatile uint32_t sysdiccr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); + sysdiccr &= (IIC_MASTER_SYSDIVCK_ICLK_MASK | IIC_MASTER_SYSDIVCK_PCLKB_MASK); + uint32_t pclkb = (IIC_MASTER_SYSDIVCK_PCLKB_MASK & sysdiccr) >> 8U; + uint32_t iclk = sysdiccr >> 24U; + uint32_t timeout_count = ((1U << (pclkb - iclk)) * p_ctrl->p_reg->ICBRL) >> 2U; + + /* Check if this is a new transaction or a continuation */ + if (!p_ctrl->restarted) + { + /* As per BBSY clearing conditions in "I2C Bus Control Register 2" description in the IIC section of the relevant hardware manual, + * the BBSY bit is 0 after the bus free time (ICBRL setting) + * if a start condition is not detected after a stop condition detection. + */ + IIC_MASTER_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->ICCR2_b.BBSY, 0U, timeout_count); + + /* If bus is busy, return error */ + FSP_ERROR_RETURN((0U != timeout_count), FSP_ERR_IN_USE); + + /* This is not a restarted transaction. + * Interrupt requests are not expected while control struct is being reinitialized, + * especially for multi-master use case, so they need to be disabled. + */ + p_ctrl->p_reg->ICIER = 0; + } + + /* Initialize fields used during transfer */ + p_ctrl->addr_loaded = 0U; + p_ctrl->loaded = 0U; + p_ctrl->remain = p_ctrl->total; + p_ctrl->addr_remain = p_ctrl->addr_total; + p_ctrl->err = false; + p_ctrl->dummy_read_completed = false; + p_ctrl->activation_on_rxi = false; + p_ctrl->activation_on_txi = false; + p_ctrl->address_restarted = false; + + /* Allow timeouts to be generated on the low value of SCL using either short or long mode. + * This gets disabled in case the previous transaction issues a restart. + */ + + /* TMOL 'Timeout L Count Control' and TMOH 'Timeout H Count Control' will be set at the time of I2C reset. + * This will enable time out detection for both SCLn high and low. + * + * Register configuration: + * - Set/Clear TMOS here to select long or short mode. + * (see "I2C Bus Mode Register 2 (ICMR2)" description in the IIC section of the relevant hardware manual). + * - Set SDDL and DLCS. If SMBus is disabled, assign default value. + */ + iic_master_extended_cfg_t * p_extend = (iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + p_ctrl->p_reg->ICMR2 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_2_MASK | + (uint8_t) (IIC_MASTER_TIMEOUT_MODE_SHORT == (p_extend->timeout_mode)) + | + (uint8_t) (p_extend->timeout_scl_low << R_IIC0_ICMR2_TMOL_Pos) + | + (uint8_t) (p_extend->clock_settings.sddl_value << R_IIC0_ICMR2_SDDL_Pos) + | + (uint8_t) (p_extend->clock_settings.dlcs_value << R_IIC0_ICMR2_DLCS_Pos)); + + /* Set the response as ACK */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; /* Write Enable */ + p_ctrl->p_reg->ICMR3_b.ACKBT = 0; /* Write */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + + /* Enable SMBus communication for I2C module if requested */ + p_ctrl->p_reg->ICMR3_b.SMBS = p_extend->smbus_operation; + + /* Enable timeout function */ + p_ctrl->p_reg->ICFER_b.TMOE = 1U; + + /* Enable TXI. This is treated differently to support restart functionality. + * In case the previous IIC master transaction enabled restart, the queued TXI will fire a this point. + * + * The TXI had been NVIC-disabled (but Peripheral enabled) before setting the + * RS bit by the previous restart enabled transaction. + * The RS bit mimics a "stop" followed by a "start" and keeps the bus busy. + * As a part of the previous transaction, TXI fires at the peripheral level and is queued at the CPU. + * + * If the previous transaction was not restart enabled - + * NVIC-enable TXI which will fire after the start condition below. + */ + NVIC_EnableIRQ(p_ctrl->p_cfg->txi_irq); + + /* Clear error flags in case they are set unexpectedly, e.g stop condition in multil-master use case */ + p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(R_IIC0_ICSR2_STOP_Msk | R_IIC0_ICSR2_START_Msk); + + /* Enable SPIE to detect unexpected STOP condition. This is disabled between communication events as it can lead + * to undesired interrupts in multi-master setups. */ + p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK | R_IIC0_ICIER_STIE_Msk | R_IIC0_ICIER_SPIE_Msk; + + /* If previous transaction did not end with restart, send a start condition */ + if (!p_ctrl->restarted) + { + /* Request IIC to issue the start condition */ + p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_ST_BIT_MASK; + } + else + { + p_ctrl->restarted = false; + } + + /* + * The Flowchart under "Master Transmit Operation" and "Master Receive Operation" + * in the IIC section of the relevant hardware manual is covered in the interrupts: + * + * 1. NACKF processing is handled in the ERI interrupt. + * For receive, dummy reading ICDRR is not required because the NACK processing in this driver resets the IIC peripheral. + * 2. Data is written to ICDRT in the transmit interrupt (TDRE is set when a transmit interrupt fires). + * 3. For transmit, stop is issued in the transmit end interrupt (TEND is set when a transmit end interrupt fires). + * 4. For transmit, ICSR2 is cleared in the transmit end interrupt. + * 5. For receive, remaining processing including reading ICDRR happens in the receive interrupt (RDRF is set when a receive interrupt fires). + */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Handles the receive data full interrupt when operating as a master. + * + * @param[in] p_ctrl The target IIC block's control block. + **********************************************************************************************************************/ +static void iic_master_rxi_master (iic_master_instance_ctrl_t * p_ctrl) +{ + volatile uint8_t dummy_read; + + /* First receive interrupt: Handle the special case of 1 or 2 byte read here */ + if (false == p_ctrl->dummy_read_completed) + { + /* Enable WAIT for 1 or 2 byte read */ + if (2U >= p_ctrl->total) + { + p_ctrl->p_reg->ICMR3_b.WAIT = 1; + } + + /* Enable NACK for 1 byte read */ + if (1U == p_ctrl->remain) + { + /* Writes to be done separately. + * See Note 1 of "I2C Bus Mode Register 3 (ICMR3)" description in the IIC section of the relevant + * hardware manual. + */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; /* Write enable ACKBT */ + p_ctrl->p_reg->ICMR3_b.ACKBT = 1; + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + } + +#if IIC_MASTER_CFG_DTC_ENABLE + uint8_t volatile const * p_iic_master_rx_buffer = &(p_ctrl->p_reg->ICDRR); + + /* Enable transfer support if possible */ + if ((NULL != p_ctrl->p_cfg->p_transfer_rx) && (p_ctrl->read) && (p_ctrl->total > 3U)) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + (uint8_t *) (p_iic_master_rx_buffer), + (void *) (p_ctrl->p_buff), + (uint16_t) (p_ctrl->total - 3U)); + + p_ctrl->remain = 3U; + p_ctrl->loaded = p_ctrl->total - 3U; + p_ctrl->activation_on_rxi = true; + } +#endif + if (((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + + /* Do a dummy read to clock the data into the ICDRR. */ + dummy_read = p_ctrl->p_reg->ICDRR; + FSP_PARAMETER_NOT_USED(dummy_read); + + /* Update the counter */ + p_ctrl->dummy_read_completed = true; + } + +#if IIC_MASTER_CFG_DTC_ENABLE + + /* If this is the interrupt that got fired after DTC transfer, + * ignore it as the DTC has already taken care of the data transfer */ + else if (true == p_ctrl->activation_on_rxi) + { + p_ctrl->activation_on_rxi = false; + } +#endif + + /* ICDRR contain valid received data */ + else if (0U < p_ctrl->remain) + { + if (((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + + iic_master_rxi_read_data(p_ctrl); + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Handles the transmit data empty interrupt when operating as a master. + * + * @param[in] p_ctrl The target IIC block's control block. + **********************************************************************************************************************/ +static void iic_master_txi_master (iic_master_instance_ctrl_t * p_ctrl) +{ + uint32_t timeout_count = IIC_MASTER_PERIPHERAL_REG_MAX_WAIT; + + /* Check if we are issuing the slave address */ + if (0U < p_ctrl->addr_remain) + { + iic_master_txi_send_address(p_ctrl); + } + else if (!p_ctrl->read) + { + /* If previous event is an error event and this TXI is triggered by ERI, do not invoke SMBus callback. Because + * the internal function which used to issue callback will clear the error flag in the control block and cause + * incorrect behavior at ERI event after this TXI. + * + * Number of loaded byte must larger or equal to 1 because it helps to ensure that SMBus callback only be invoked + * after slave addess already transmitted (omit first 2 TDRE raise event). + */ + if ((((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) && + ((!p_ctrl->err) && (0U < p_ctrl->loaded))) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + +#if IIC_MASTER_CFG_DTC_ENABLE + + /* If this is the interrupt that got fired after DTC transfer, + * ignore it as the DTC has already taken care of the data transfer */ + if (true == p_ctrl->activation_on_txi) + { + p_ctrl->activation_on_txi = false; + } + else if (p_ctrl->remain > 0U) +#else + if (p_ctrl->remain > 0U) +#endif + { + /* Write the data to ICDRT register */ + p_ctrl->p_reg->ICDRT = p_ctrl->p_buff[p_ctrl->loaded]; + + /* Update the number of bytes remaining for next pass */ + p_ctrl->loaded++; + p_ctrl->remain--; + } + else + { + /* Do nothing */ + } + + /* We are done loading ICDRT, wait for TEND to send a stop/restart */ + if (0U == p_ctrl->remain) + { + /* Disable the Transmit Data Empty Interrupt. */ + p_ctrl->p_reg->ICIER_b.TIE = 0U; + + /* Wait for the value to reflect at the peripheral. + * See 'Note' under Table "Interrupt sources" in the IIC section of the relevant hardware manual. */ + IIC_MASTER_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->ICIER_b.TIE, 0U, timeout_count); + + /* Enable the transmit end IRQ, to issue a STOP or RESTART */ + /* Clear any pending TEND interrupts */ + R_BSP_IrqStatusClear(p_ctrl->p_cfg->tei_irq); + NVIC_ClearPendingIRQ(p_ctrl->p_cfg->tei_irq); + + /* Enable the TXEND interrupt */ + p_ctrl->p_reg->ICIER_b.TEIE = 1U; + + /* No need to wait to check TEIE has actually become 1U; because if that's not the case, + * no other operation can occur at this point */ + } + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Handles the transmit end interrupt when operating as a master. + * @note This interrupt is configured to be generated at the end of last byte of the requested transfer. + * + * @param[in] p_ctrl The target IIC block's control block. + **********************************************************************************************************************/ +static void iic_master_tei_master (iic_master_instance_ctrl_t * p_ctrl) +{ + uint32_t timeout_count = IIC_MASTER_PERIPHERAL_REG_MAX_WAIT; + + if (((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_BYTE_ACK); + } + + /* This is a 10 bit address read, issue a restart prior to the last address byte transmission */ + if ((p_ctrl->read) && (p_ctrl->addr_remain == 1U) && (false == p_ctrl->address_restarted)) + { +#if IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE + + /* Enable TXI so that it fires after restart condition. */ + p_ctrl->p_reg->ICIER_b.TIE = 1U; + + /* Request IIC to issue the restart condition */ + p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_RS_BIT_MASK; + p_ctrl->address_restarted = true; +#endif + } + /* We are done with the transfer, send STOP or RESTART */ + else if (0U == p_ctrl->remain) + { + /* Send RESTART */ + if (p_ctrl->restart) + { + /* NOTE:Only disable in NVIC, disabling in I2C would cause the + * restart condition to fail because we are using the buffered + * interrupt to start the next sequence */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + p_ctrl->p_reg->ICIER_b.TIE = 1U; + + /* Request IIC to issue the restart condition. At this point we will queue a TXI at the NVIC level. */ + p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_RS_BIT_MASK; + + /* Disable timeout function */ + p_ctrl->p_reg->ICFER_b.TMOE = 0; + + /* Remember that we issued a restart for the next transfer */ + p_ctrl->restarted = true; + } + /* Send STOP */ + else + { + /* Clear STOP flag and set SP. + * It is ok to clear other status' as this transaction is over. + */ + p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(R_IIC0_ICSR2_STOP_Msk); + + /* Request IIC to issue the stop condition */ + p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */ + } + } + else + { + /* Do nothing */ + } + + /* Disable the interrupt as we are done with the transfer */ + p_ctrl->p_reg->ICIER_b.TEIE = 0U; + + /* Wait for the value to reflect at the peripheral. + * See 'Note' under the table "Interrupt sources" in the IIC section of the relevant hardware manual. */ + IIC_MASTER_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->ICIER_b.TEIE, 0U, timeout_count); +} + +/*******************************************************************************************************************//** + * Handles the error interrupts when operating as a master. + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void iic_master_err_master (iic_master_instance_ctrl_t * p_ctrl) +{ + /* Clear all the event flags except the receive data full, transmit end and transmit data empty flags*/ + uint8_t errs_events = IIC_MASTER_STATUS_REGISTER_2_ERR_MASK & p_ctrl->p_reg->ICSR2; + p_ctrl->p_reg->ICSR2 &= (uint8_t) ~IIC_MASTER_STATUS_REGISTER_2_ERR_MASK; + + /* If the event was an error event, then handle it */ + if ((errs_events & + (uint8_t) ((uint8_t) (IIC_MASTER_ERR_EVENT_TIMEOUT) | (uint8_t) (IIC_MASTER_ERR_EVENT_ARBITRATION_LOSS))) | + ((errs_events & (uint8_t) (IIC_MASTER_ERR_EVENT_NACK)) && (1U != p_ctrl->p_reg->ICCR2_b.MST))) + { + /* Conditions to get here: + * 1. This is Timeout and/or arbitration loss error during an ongoing transaction + * 2. This is a NACK error and this device is no longer the active master on the bus. + * The MST bit here can get cleared: + * a. In case of an arbitration loss error.also occurs. + * b. If the slave timeout is lesser than master timeout and the slave releases + * the bus by performing an internal reset. + * See clearing conditions of MST in "I2C Bus Control Register 2 (ICCR2)" description + * in the IIC section of the relevant hardware manual. + * 3. This is a Timeout error after attempting to issue a stop after detecting a NACK previously. + *//* Set the error flag when an error event occurred */ + p_ctrl->err = true; + + /* Abort an in-progress transfer with the current device */ + iic_master_abort_seq_master(p_ctrl, true); /* This will reset the IIC Master driver */ + /* Notify anyone waiting that the transfer is Aborted due to error. */ + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED); + } + else if ((errs_events & (uint8_t) (IIC_MASTER_ERR_EVENT_NACK)) && (1U == p_ctrl->p_reg->ICCR2_b.MST)) + { + /* MST bit must be set to issue a stop condition. + * See "Issuing a Stop Condition" in the IIC section of the relevant hardware manual. + */ + + /* Set the error flag when an error event occurred + * This will be checked after the stop condition is detected from the request below. */ + p_ctrl->err = true; + + /* The sequence below is to handle a NACK received from slave in the middle of a write. + * See item '[4]' under the figure "Example master transmission flow" in the IIC section of the relevant hardware manual. */ + + /* Request IIC to issue the stop condition */ + p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */ + + /* Allow timeouts to be generated on the low value of SCL using either long or short mode and re-assign value + * of SDDL and DLCS. */ + p_ctrl->p_reg->ICMR2 = (uint8_t) 0x02U | + (uint8_t) (((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->timeout_mode) | + (uint8_t) (((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + clock_settings.sddl_value << R_IIC0_ICMR2_SDDL_Pos) + | + (uint8_t) (((iic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + clock_settings.dlcs_value << R_IIC0_ICMR2_DLCS_Pos); + p_ctrl->p_reg->ICFER_b.TMOE = 1; + + /* This interrupt will be fired again when wither stop condition is sent + * or the hardware detects the line is stuck low causing a timeout */ + } + /* This is a STOP or RESTART event. Please note there may be expected start/stop condition in multi-master use case. + * NOTE: Do not use p_transfer->loaded or p_transfer->remain to check whether the transfer is + * completed, since using them would lead to a race condition between txi and eri interrupts in case + * of one byte transfer which will result in BUS arbitration loss error. + */ + else if ((errs_events & (uint8_t) IIC_MASTER_ERR_EVENT_STOP) || + ((p_ctrl->restarted) && (errs_events & (uint8_t) IIC_MASTER_ERR_EVENT_START))) + { + i2c_master_event_t event = I2C_MASTER_EVENT_ABORTED; + if ((0 == p_ctrl->remain) && (false == p_ctrl->err)) /* Successful transaction */ + { + /* Get the correct event to notify the user */ + event = (p_ctrl->read) ? I2C_MASTER_EVENT_RX_COMPLETE : I2C_MASTER_EVENT_TX_COMPLETE; + + /* Disable STIE/SPIE to prevent errant interrupts in multi-master scenarios */ + p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK; + } + else if ((errs_events & (uint8_t) IIC_MASTER_ERR_EVENT_STOP)) + { + /* This is the STOP condition requested due to a NACK error earlier. + * Since the stop condition is successfully issued there is no need to reset the driver. + */ + iic_master_abort_seq_master(p_ctrl, false); /* Clear the transaction flags only */ + } + else + { + /* Do nothing */ + } + + /* Notify anyone waiting */ + iic_master_notify(p_ctrl, event); + } + else if (errs_events & (uint8_t) IIC_MASTER_ERR_EVENT_START) + { + if (((iic_master_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->smbus_operation) + { + iic_master_notify(p_ctrl, I2C_MASTER_EVENT_START); + } + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Check valid receive data and set WAIT, NACK and STOP/RESTART bit in RXI handler. + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void iic_master_rxi_read_data (iic_master_instance_ctrl_t * const p_ctrl) +{ + /* If next data = (final byte - 2), enable WAIT */ + if (3U == p_ctrl->remain) + { + p_ctrl->p_reg->ICMR3_b.WAIT = 1; + } + /* If next data = (final byte - 1), enable NACK */ + else if (2U == p_ctrl->remain) + { + /* Writes to be done separately. + * See Note 1 in "I2C Bus Mode Register 3 (ICMR3)" in the IIC section of the relevant hardware manual. + */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; /* Write enable ACKBT */ + p_ctrl->p_reg->ICMR3_b.ACKBT = 1; + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + } + /* If next data = final byte, send STOP or RESTART */ + else if (1U == p_ctrl->remain) + { + if (p_ctrl->restart) + { + /* NOTE:Only disable in NVIC, disabling in I2C would cause the + * restart condition to fail because we are using the buffered + * interrupt to start the next sequence */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + p_ctrl->p_reg->ICIER_b.TIE = 1U; + + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; /* Write enable ACKBT */ + + /* This bit clears to 0 automatically by issuing stop condition. + * For restart condition, clear bit by software. + */ + p_ctrl->p_reg->ICMR3_b.ACKBT = 0; + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + + /* Request IIC to issue the restart condition */ + p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_RS_BIT_MASK; + + /* Disable timeout function */ + p_ctrl->p_reg->ICFER_b.TMOE = 0; + + /* Remember that we issued a restart when doing the next transfer */ + p_ctrl->restarted = true; + } + else + { + /* Clear STOP flag and set SP. + * It is ok to clear other status' as this transaction is over. + */ + p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(R_IIC0_ICSR2_STOP_Msk); + + /* Request IIC to issue the stop condition */ + p_ctrl->p_reg->ICCR2 = (uint8_t) IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */ + + /* STOP flag will not be set just yet. STOP will be set only after reading the last byte from ICDRR and clearing the WAIT. + * See Point #7 under "Master Receive Operation" in the IIC section of the relevant hardware manual. + */ + } + } + else + { + /* Do nothing */ + } + + p_ctrl->p_buff[p_ctrl->loaded] = p_ctrl->p_reg->ICDRR; + + /* Update the counter values */ + p_ctrl->loaded++; + p_ctrl->remain--; + + /* If we are done with the reception, clear the WAIT bit */ + if (0U == p_ctrl->remain) + { + p_ctrl->p_reg->ICMR3_b.WAIT = 0; + + /* If this transaction does not have the restart flag set to true, + * last byte has been read and WAIT has been cleared. + * Callback will be issued by the ERI once the stop condition is detected + * In case of restart flag set to true a callback will be issued by the ERI once the start + * (from restart) condition is detected + */ + } +} + +/*******************************************************************************************************************//** + * Write the address byte to the iic bus + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void iic_master_txi_send_address (iic_master_instance_ctrl_t * const p_ctrl) +{ + /* This is a 10 bit read and we have transmitted the low byte, next is restart */ + if ((3U == p_ctrl->addr_total) && (2U == p_ctrl->addr_loaded) && (false == p_ctrl->address_restarted)) + { +#if IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE + uint32_t timeout_count = IIC_MASTER_PERIPHERAL_REG_MAX_WAIT; + + /* For Read operation an extra address byte needs to be sent after issuing restart. + * At this point we have sent the first 2 address bytes. Disable TXI. + */ + p_ctrl->p_reg->ICIER_b.TIE = 0U; + + /* Wait for the value to reflect at the peripheral. + * See 'Note' under table "Interrupt sources" in the IIC section of the relevant hardware manual. */ + IIC_MASTER_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->ICIER_b.TIE, 0U, timeout_count); + + /* Enable the transmit end IRQ, so that we can generate a RESTART condition */ + /* Clear any pending TEND interrupts */ + R_BSP_IrqStatusClear(p_ctrl->p_cfg->tei_irq); + NVIC_ClearPendingIRQ(p_ctrl->p_cfg->tei_irq); + + /* Enable the TXEND interrupt */ + p_ctrl->p_reg->ICIER_b.TEIE = 1U; + + /* No need to wait to check TEIE has actually become 1U; because if that's not the case, + * no other operation can occur at this point */ +#endif + } + else + { + /* Address low byte, this could either be a 7 bit address or low byte of 10 bit address */ + uint8_t address_byte = p_ctrl->addr_low; +#if IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE + + /* 10 bit address, handle accordingly */ + if (p_ctrl->addr_total > 1U) + { + /* MSB transfer, send address high byte with with R/W set to 0 */ + if (0U == p_ctrl->addr_loaded) + { + address_byte = p_ctrl->addr_high; + } + /* MSB transfer after restart of 10 bit read, send high byte with R/W set to 1 */ + else if ((2U == p_ctrl->addr_loaded) && (3U == p_ctrl->addr_total)) + { + address_byte = p_ctrl->addr_high | (uint8_t) I2C_CODE_READ; + } + /* Low byte transfer */ + else + { + address_byte = p_ctrl->addr_low; + } + } +#endif + +#if IIC_MASTER_CFG_DTC_ENABLE + uint8_t volatile const * p_iic_master_tx_buffer = &(p_ctrl->p_reg->ICDRT); + + /* If this is the last address byte, enable transfer */ + if (1U == p_ctrl->addr_remain) + { + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && !(p_ctrl->read) && (p_ctrl->total > 0U)) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->reset(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + (void *) (p_ctrl->p_buff), + (uint8_t *) (p_iic_master_tx_buffer), + (uint16_t) (p_ctrl->remain)); + p_ctrl->remain = 0U; + p_ctrl->loaded = p_ctrl->total; + p_ctrl->activation_on_txi = true; + } + } +#endif + + /* Write the address byte */ + p_ctrl->p_reg->ICDRT = address_byte; + + /* Update the number of address bytes loaded for next pass */ + p_ctrl->addr_loaded++; + p_ctrl->addr_remain--; + } +} + +#if IIC_MASTER_CFG_DTC_ENABLE + +/*******************************************************************************************************************//** + * Configures IIC related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to IIC specific control structure + * @param[in] p_cfg Pointer to IIC specific configuration structure + * + * @retval FSP_SUCCESS Transfer interface initialized successfully. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL. + **********************************************************************************************************************/ +static fsp_err_t iic_master_transfer_open (i2c_master_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + if (NULL != p_cfg->p_transfer_rx) + { + err = iic_master_transfer_configure(p_cfg->p_transfer_rx, IIC_MASTER_TRANSFER_DIR_READ); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (NULL != p_cfg->p_transfer_tx) + { + err = iic_master_transfer_configure(p_cfg->p_transfer_tx, IIC_MASTER_TRANSFER_DIR_WRITE); + if (FSP_SUCCESS != err) + { + if (NULL != p_cfg->p_transfer_rx) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + + return err; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures IIC RX related transfer. + * @param[in] p_ctrl Pointer to IIC specific control structure + * @param[in] p_cfg Pointer to IIC specific configuration structure + * + * @retval FSP_SUCCESS Transfer interface is configured with valid parameters. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL. + **********************************************************************************************************************/ +static fsp_err_t iic_master_transfer_configure (transfer_instance_t const * p_transfer, + iic_master_transfer_dir_t direction) +{ + fsp_err_t err; + + /* Set default transfer info and open receive transfer module, if enabled. */ + #if (IIC_MASTER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + #endif + transfer_info_t * p_cfg = p_transfer->p_cfg->p_info; + if (IIC_MASTER_TRANSFER_DIR_READ == direction) + { + p_cfg->transfer_settings_word = IIC_MASTER_DTC_RX_TRANSFER_SETTINGS; + } + else + { + p_cfg->transfer_settings_word = IIC_MASTER_DTC_TX_TRANSFER_SETTINGS; + } + + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); + + return FSP_SUCCESS; +} + +#endif + +/*********************************************************************************************************************** + * Interrupt Vectors + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Receive data full interrupt routine. + * + * This function implements the IIC Receive buffer full ISR routine. + * + **********************************************************************************************************************/ +void iic_master_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + iic_master_rxi_master(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Transmit data empty interrupt routine. + * + * This function implements the Transmit buffer empty ISR routine. + * + **********************************************************************************************************************/ +void iic_master_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + iic_master_txi_master(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Transmit end interrupt routine. + * + * This function implements the IIC Transmission End ISR routine. + * + **********************************************************************************************************************/ +void iic_master_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + iic_master_tei_master(p_ctrl); + + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Error and event interrupt routine. + * + * This function implements the IIC Event/Error. + * + **********************************************************************************************************************/ +void iic_master_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + iic_master_err_master(p_ctrl); + + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_slave/r_iic_slave.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_slave/r_iic_slave.c new file mode 100644 index 0000000000..00f50eb47e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iic_slave/r_iic_slave.c @@ -0,0 +1,1421 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes + *********************************************************************************************************************/ +#include "r_iic_slave.h" +#if IIC_SLAVE_CFG_DTC_ENABLE + #include "r_dtc.h" +#endif + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/* "I2CS" in ASCII, used to determine if channel is open. */ +#define IIC_SLAVE_OPEN (0x49324353ULL) + +/* The timeout interrupt enable bit */ +#define IIC_TMO_EN_BIT (0x01U) + +/* The arbitration loss detection interrupt enable bit */ +#define IIC_ALD_EN_BIT (0x02U) + +/* The start condition detection interrupt enable bit */ +#define IIC_STR_EN_BIT (0x04U) + +/* The stop condition detection interrupt enable bit */ +#define IIC_STP_EN_BIT (0x08U) + +/* The NAK reception interrupt enable bit */ +#define IIC_NAK_EN_BIT (0x10U) + +/* The receive data full interrupt enable bit */ +#define IIC_RXI_EN_BIT (0x20U) + +/* The transmit end interrupt enable bit */ +#define IIC_TEI_EN_BIT (0x40U) + +/* The transmit data empty interrupt enable bit */ +#define IIC_TXI_EN_BIT (0x80U) + +/* Bit position for Timeout function (TMOF) detection flag in ICSR2 */ +#define ICSR2_TMOF_BIT (0x01U) + +/* Bit position for Arbitration loss (AL) detection flag in ICSR2 */ +#define ICSR2_AL_BIT (0x02U) + +/* Bit position for the START condition detection flag in ICSR2 */ +#define ICSR2_START_BIT (0x04U) + +/* Bit position for STOP condition flag in ICSR2 */ +#define ICSR2_STOP_BIT (0x08U) + +/* Bit position for No Acknowledgment (NACKF) flag in ICSR2 */ +#define ICSR2_NACKF_BIT (0x10U) + +/* I2C Bus Control Register 1 Masks */ +#define IIC_SLAVE_ICCR1_SCL_SDA_OUTPUT_MASK (0x1FU) +#define IIC_SLAVE_ICCR1_ICE_BIT_MASK (0x80) +#define IIC_SLAVE_ICCR1_IICRST_BIT_MASK (0x40) + +/* I2C Bus Status Enable Register Mask */ +#define IIC_SLAVE_ICSER_SLAVE_ADDRESS_ENABLE_REGISTER_0 (0x01U) + +/* I2C Bus Function Enable Register Mask */ +#define IIC_SLAVE_FUNCTION_ENABLE_INIT_SETTINGS (0x5DU) + +/* I2C Bus Bit Rate Low-Level Register Mask */ +#define IIC_SLAVE_BUS_RATE_REG_RESERVED_BITS (0xE0U) + +/* I2C Bus Mode Register 1 Mask */ +#define IIC_SLAVE_BUS_MODE_REGISTER_1_MASK (0x08U) + +/* I2C Bus Mode Register 2 Masks */ +#define IIC_SLAVE_BUS_MODE_REGISTER_2_MASK (0x06U) +#define IIC_SLAVE_INTERNAL_REF_CLOCK_SELECT_MAX (0x07U) + +/* I2C Bus Status Register 2 Mask */ +#define IIC_SLAVE_STATUS_REGISTER_2_ERR_MASK (0x1FU) + +#if IIC_SLAVE_CFG_DTC_ENABLE + #define IIC_SLAVE_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + #define IIC_SLAVE_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#endif + +/* Register Wait Time */ + +/* Worst case ratio of (ICLK/PCLKB) = 64 bytes approximately. + * 3 PCLKB cycles is the number of cycles to wait for IICn. + * See Table "Access cycles" in the I/O Registers section of the relevant hardware manual. + */ +#define IIC_SLAVE_PERIPHERAL_REG_MAX_WAIT (0x40U * 0x03U) + +#define IIC_SLAVE_HARDWARE_REGISTER_WAIT(reg, required_value, timeout) \ + while ((timeout)) \ + { \ + if ((required_value) == (reg)) \ + { \ + break; \ + } \ + (timeout)--; \ + } + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * iic_slave_prv_ns_callback)(i2c_slave_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile iic_slave_prv_ns_callback)(i2c_slave_callback_args_t * p_args); +#endif + +/********************************************************************************************************************** + * Private function prototypes + *********************************************************************************************************************/ + +/* Internal helper functions */ +static void iic_slave_notify(iic_slave_instance_ctrl_t * const p_ctrl, i2c_slave_event_t const slave_event); +static void iic_slave_callback_request(iic_slave_instance_ctrl_t * const p_ctrl, i2c_slave_event_t slave_event); +static void iic_slave_initiate_transaction(iic_slave_instance_ctrl_t * p_ctrl, i2c_slave_event_t slave_event); +static fsp_err_t iic_slave_read_write(i2c_slave_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + iic_slave_transfer_dir_t direction); +static void r_iic_slave_call_callback(iic_slave_instance_ctrl_t * p_ctrl, + i2c_slave_event_t event, + uint32_t transaction_count); + +#if IIC_SLAVE_CFG_DTC_ENABLE +static fsp_err_t iic_slave_transfer_open(i2c_slave_cfg_t const * const p_cfg); +static fsp_err_t iic_slave_transfer_configure(transfer_instance_t const * p_transfer, + iic_slave_transfer_dir_t direction); + +#endif + +/* Functions that manipulate hardware */ +static void iic_open_hw_slave(iic_slave_instance_ctrl_t * const p_ctrl); + +/* Interrupt handlers */ +static void iic_rxi_slave(iic_slave_instance_ctrl_t * p_ctrl); +static void iic_txi_slave(iic_slave_instance_ctrl_t * p_ctrl); +static void iic_tei_slave(iic_slave_instance_ctrl_t * p_ctrl); +static void iic_err_slave(iic_slave_instance_ctrl_t * p_ctrl); + +/********************************************************************************************************************** + * Private global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Global variables + *********************************************************************************************************************/ + +/* IIC Implementation of I2C device slave interface */ +i2c_slave_api_t const g_i2c_slave_on_iic = +{ + .open = R_IIC_SLAVE_Open, + .read = R_IIC_SLAVE_Read, + .write = R_IIC_SLAVE_Write, + .close = R_IIC_SLAVE_Close, + .callbackSet = R_IIC_SLAVE_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup IIC_SLAVE + * @{ + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Functions + *********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Opens the I2C slave device. + * + * @retval FSP_SUCCESS I2C slave device opened successfully. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel is not available on this MCU. + * @retval FSP_ERR_INVALID_ARGUMENT Error interrupt priority is lower than + * Transmit, Receive and Transmit End interrupt priority + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. p_api_ctrl or p_cfg is NULL. + * 2. extended parameter is NULL. + * 3. Callback parameter is NULL. + * 4. Set the rate to fast mode plus on a channel which does not support it. + * 5. Invalid IRQ number assigned + * 6. transfer instance in p_cfg is NULL when DTC support enabled + *********************************************************************************************************************/ +fsp_err_t R_IIC_SLAVE_Open (i2c_slave_ctrl_t * const p_api_ctrl, i2c_slave_cfg_t const * const p_cfg) +{ + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) p_api_ctrl; + +#if IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_cfg != NULL); + FSP_ASSERT(p_cfg->p_extend != NULL); + FSP_ASSERT(p_cfg->rxi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->eri_irq >= (IRQn_Type) 0); + + FSP_ERROR_RETURN(BSP_FEATURE_IIC_VALID_CHANNEL_MASK & (1 << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + FSP_ERROR_RETURN(IIC_SLAVE_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(p_cfg->eri_ipl <= p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT); + + /* If rate is configured as Fast mode plus, check whether the channel supports it */ + if (I2C_SLAVE_RATE_FASTPLUS == p_cfg->rate) + { + FSP_ASSERT((BSP_FEATURE_IIC_FAST_MODE_PLUS_CHANNELS_MASK & (1U << p_cfg->channel))); + } +#endif + +#if IIC_SLAVE_CFG_DTC_ENABLE + fsp_err_t err = FSP_SUCCESS; +#endif + + p_ctrl->p_reg = (R_IIC0_Type *) ((uint32_t) R_IIC0 + (p_cfg->channel * ((uint32_t) R_IIC1 - (uint32_t) R_IIC0))); + + /* Record the configuration on the device for use later */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + R_BSP_MODULE_START(FSP_IP_IIC, p_cfg->channel); + + /* Indicate that restart and stop condition detection yet to be enabled */ + p_ctrl->start_interrupt_enabled = false; + + /* Open the hardware in slave mode. Performs IIC initialization as described in hardware manual (see + * "Initial Settings" in the IIC Operation section of the relevant hardware manual). */ + iic_open_hw_slave(p_ctrl); + +#if IIC_SLAVE_CFG_DTC_ENABLE + + /* Open the IIC transfer interface if available */ + err = iic_slave_transfer_open(p_cfg); + if (FSP_SUCCESS != err) + { + R_BSP_MODULE_STOP(FSP_IP_IIC, p_cfg->channel); + + return err; + } +#endif + + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->eri_irq, p_ctrl->p_cfg->eri_ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->txi_irq, p_ctrl->p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->tei_irq, p_ctrl->p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->rxi_irq, p_ctrl->p_cfg->ipl, p_ctrl); + + /* Finally, we can consider the device opened */ + p_ctrl->p_buff = NULL; + p_ctrl->total = 0U; + p_ctrl->remain = 0U; + p_ctrl->loaded = 0U; + p_ctrl->transaction_completed = false; + p_ctrl->open = IIC_SLAVE_OPEN; + p_ctrl->direction = IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED; + p_ctrl->do_dummy_read = false; + p_ctrl->notify_request = false; + p_ctrl->transaction_count = 0U; +#if (IIC_SLAVE_CFG_DTC_ENABLE) + p_ctrl->activation_on_rxi = false; + p_ctrl->activation_on_txi = false; +#endif + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Performs a read from the I2C Master device. + * + * This function will fail if there is already an in-progress I2C transfer on the associated channel. Otherwise, the + * I2C slave read operation will begin. The caller will be notified when the operation has finished by an + * I2C_SLAVE_EVENT_RX_COMPLETE in the callback. + * In case the master continues to write more data, an I2C_SLAVE_EVENT_RX_MORE_REQUEST will be issued via callback. + * In case of errors, an I2C_SLAVE_EVENT_ABORTED will be issued via callback. + * + * @retval FSP_SUCCESS Function executed without issue + * @retval FSP_ERR_ASSERTION p_api_ctrl, bytes or p_dest is NULL. + * @retval FSP_ERR_IN_USE Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Device is not open. + * @retval FSP_ERR_INVALID_SIZE Invalid size when reading data via DTC. + *********************************************************************************************************************/ +fsp_err_t R_IIC_SLAVE_Read (i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ + fsp_err_t err = FSP_SUCCESS; + + err = iic_slave_read_write(p_api_ctrl, p_dest, bytes, IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ); + + return err; +} + +/******************************************************************************************************************//** + * Performs a write to the I2C Master device. + * + * This function will fail if there is already an in-progress I2C transfer on the associated channel. Otherwise, the + * I2C slave write operation will begin. The caller will be notified when the operation has finished by an + * I2C_SLAVE_EVENT_TX_COMPLETE in the callback. + * In case the master continues to read more data, an I2C_SLAVE_EVENT_TX_MORE_REQUEST will be issued via callback. + * In case of errors, an I2C_SLAVE_EVENT_ABORTED will be issued via callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_src is NULL. + * @retval FSP_ERR_IN_USE Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Device is not open. + * @retval FSP_ERR_INVALID_SIZE Invalid size when writing data via DTC. + *********************************************************************************************************************/ +fsp_err_t R_IIC_SLAVE_Write (i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const p_src, uint32_t const bytes) +{ + fsp_err_t err = FSP_SUCCESS; + + err = iic_slave_read_write(p_api_ctrl, p_src, bytes, IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE); + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2c_slave_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_IIC_SLAVE_CallbackSet (i2c_slave_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_slave_callback_args_t *), + void * const p_context, + i2c_slave_callback_args_t * const p_callback_memory) +{ + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) p_api_ctrl; + +#if (IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(IIC_SLAVE_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2c_slave_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2c_slave_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Closes the I2C device. + * + * @retval FSP_SUCCESS Device closed successfully. + * @retval FSP_ERR_NOT_OPEN Device not opened. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + *********************************************************************************************************************/ +fsp_err_t R_IIC_SLAVE_Close (i2c_slave_ctrl_t * const p_api_ctrl) +{ + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) p_api_ctrl; + +#if IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + + /* Check if the device is even open, return an error if not */ + FSP_ERROR_RETURN(IIC_SLAVE_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* The device is now considered closed */ + p_ctrl->open = 0U; + + /* Clear all interrupt bits */ + p_ctrl->p_reg->ICIER = 0U; + +#if IIC_SLAVE_CFG_DTC_ENABLE + + /* Close the handles for the transfer interfaces */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + /* Disable all interrupts in NVIC */ + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + + R_BSP_MODULE_STOP(FSP_IP_IIC, p_ctrl->p_cfg->channel); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * @} (end addtogroup IIC_SLAVE) + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Private Functions + *********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Helper function for handling I2C Slave Read or Write. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_buffer Pointer to the buffer to store read/write data. + * @param[in] bytes Number of bytes to be read/written. + * @param[in] direction Slave Read or Slave Write + * + * @retval FSP_SUCCESS Function executed successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_buffer is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than UINT16_MAX(= 65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_IN_USE Another transfer was in progress. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_SLAVE_Open to initialize the control block. + **********************************************************************************************************************/ +static fsp_err_t iic_slave_read_write (i2c_slave_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + iic_slave_transfer_dir_t direction) +{ + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) p_api_ctrl; + +#if IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_buffer != NULL); + + /* Check if the device is even open, return an error if not */ + FSP_ERROR_RETURN(IIC_SLAVE_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Fail if there is already a transfer in progress */ + FSP_ERROR_RETURN(IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED == p_ctrl->direction, FSP_ERR_IN_USE); + + FSP_ASSERT(((iic_slave_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); + #if IIC_SLAVE_CFG_DTC_ENABLE + + /* DTC on RX could actually receive 65535+1 = 65536 bytes as 1 bytes are handled separately. + * DTC on TX could actually receive 65535+2 = 65537 bytes as 2 bytes are handled separately. + * Forcing to 65535 to keep TX and RX uniform with respect to max transaction length via DTC. + */ + FSP_ERROR_RETURN((bytes <= UINT16_MAX), FSP_ERR_INVALID_SIZE); + #endif +#endif + + /* Record the new information about this transfer */ + p_ctrl->p_buff = p_buffer; + p_ctrl->total = bytes; + p_ctrl->remain = bytes; + p_ctrl->direction = direction; + + /* Initialize fields used during transfer */ + p_ctrl->loaded = 0U; + +#if (IIC_SLAVE_CFG_DTC_ENABLE) + + /* Reset activation for DTC */ + p_ctrl->activation_on_txi = false; + p_ctrl->activation_on_rxi = false; +#endif + + /* Indicate that restart and stop condition detection yet to be enabled */ + p_ctrl->start_interrupt_enabled = false; + + /* Set the response as ACK */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; /* Write Enable */ + p_ctrl->p_reg->ICMR3_b.ACKBT = 0; /* Write */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + + /* Timeouts are enabled by the driver code at the end of an IIC Slave callback. + * Do not enable them here to prevent time restricting the application code. + */ + + p_ctrl->transaction_completed = false; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Single point for managing the logic around notifying a transfer has finished. + * + * @param[in] p_ctrl Pointer to the control structure. + * @param[in] slave_event The slave event code to pass to the callback. + *********************************************************************************************************************/ +static void iic_slave_notify (iic_slave_instance_ctrl_t * const p_ctrl, i2c_slave_event_t const slave_event) +{ + /* Clear all interrupt bits, Only enable TXI and RXI interrupts for the next transaction. */ + p_ctrl->p_reg->ICIER = (uint8_t) ((uint8_t) IIC_RXI_EN_BIT | (uint8_t) IIC_TXI_EN_BIT); + + /* Reset the status flags */ + p_ctrl->notify_request = false; + p_ctrl->do_dummy_read = false; + + /* Disable timeout function */ + p_ctrl->p_reg->ICFER_b.TMOE = 0; + +#if IIC_SLAVE_CFG_DTC_ENABLE + + /* Stop any DTC assisted transfer for tx */ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if ((NULL != p_transfer_tx) && (IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE == p_ctrl->direction)) + { + p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + } + + /* Stop any DTC assisted transfer for rx */ + const transfer_instance_t * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if ((NULL != p_transfer_rx) && (IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ == p_ctrl->direction)) + { + p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); + } +#endif + + /* Check if the transaction ended with a stop (or restart) */ + if (p_ctrl->transaction_completed) + { + /* Clear all status flags */ + p_ctrl->p_reg->ICSR2 = 0x00; + } + /* + * Since the transaction resulted in an error or is not completed at the master (this is a bus hang situation) + * the slave must do an internal reset to release the bus. + * See note "I2C Bus Control Register 1 (ICCR1)" under + * "IICRST bit (IIC-Bus Interface Internal Reset)" description + * in the IIC section of the relevant hardware manual. + */ + else + { + /* Internal reset */ + p_ctrl->p_reg->ICCR1 = + (uint8_t) (IIC_SLAVE_ICCR1_ICE_BIT_MASK | IIC_SLAVE_ICCR1_IICRST_BIT_MASK); + + /* Release IIC from internal reset */ + p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_SLAVE_ICCR1_ICE_BIT_MASK | IIC_SLAVE_ICCR1_SCL_SDA_OUTPUT_MASK); + } + + /* Save transaction count */ + uint32_t transaction_count = p_ctrl->transaction_count; + + /* Reset the transaction count here */ + p_ctrl->transaction_count = 0U; + + p_ctrl->direction = IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED; + + /* Invoke the callback */ + r_iic_slave_call_callback(p_ctrl, slave_event, transaction_count); +} + +/*******************************************************************************************************************//** + * Deliver callback. Timeouts are disabled causing clock to stretch. + * + * @param p_ctrl Pointer to the control structure. + * @param[in] slave_event Slave event to be reported via callback. + **********************************************************************************************************************/ +static void iic_slave_callback_request (iic_slave_instance_ctrl_t * const p_ctrl, i2c_slave_event_t slave_event) +{ + p_ctrl->direction = IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED; + + /* Disable timeout function */ + p_ctrl->p_reg->ICFER_b.TMOE = 0; + + /* Invoke the callback to notify the read request. + * The application must call MasterWriteSlaveRead API in the callback.*/ + r_iic_slave_call_callback(p_ctrl, slave_event, p_ctrl->transaction_count); + + /* Allow timeouts to be generated on both high and low value of SCL using long count mode */ + p_ctrl->p_reg->ICMR2 = IIC_SLAVE_BUS_MODE_REGISTER_2_MASK; + + /* Enable timeout function */ + p_ctrl->p_reg->ICFER_b.TMOE = 1; +} + +/******************************************************************************************************************//** + * Performs the hardware initialization sequence when operating as a slave (see + * "Initial Settings" in the IIC Operation section of the relevant hardware manual). + * + * @param[in] p_ctrl Pointer to the control structure. + *********************************************************************************************************************/ +static void iic_open_hw_slave (iic_slave_instance_ctrl_t * const p_ctrl) +{ + uint8_t digital_filter_stages = + (((iic_slave_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->clock_settings.digital_filter_stages); + + /* Perform IIC reset */ + /* S1. Set the ICCR1.ICE bit to 0 to set the SCLn and SDAn pins to the inactive state. */ + p_ctrl->p_reg->ICCR1 = 0; + + /* S2. Set the ICCR1.IICRST bit to 1 to initiate IIC reset. */ + p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_SLAVE_ICCR1_IICRST_BIT_MASK); + + /* Wait for IICRST to be set. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->ICCR1_b.IICRST, 1U); + + /* S3. Set the ICCR1.ICE bit to 1 to initiate internal reset. */ + p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_SLAVE_ICCR1_ICE_BIT_MASK | IIC_SLAVE_ICCR1_IICRST_BIT_MASK); + + /* S4. Set other registers as required. */ + + /* Set Slave address in SARLx and SARUx. and Set ICSER */ + /*7 bit mode selected, clear SARU and set SARL */ + if (I2C_SLAVE_ADDR_MODE_7BIT == p_ctrl->p_cfg->addr_mode) + { + p_ctrl->p_reg->SAR[0].U = 0U; + p_ctrl->p_reg->SAR[0].L = (uint8_t) (p_ctrl->p_cfg->slave << 1U); + } + /* 10 bit mode selected, set SARU and SARL */ + else + { + p_ctrl->p_reg->SAR[0].U = (((p_ctrl->p_cfg->slave >> 7U) | 0x01U) & 0x07U); + p_ctrl->p_reg->SAR[0].L = (uint8_t) p_ctrl->p_cfg->slave; + } + + /* Enable the slave address */ + p_ctrl->p_reg->ICSER = (uint8_t) ((uint8_t) IIC_SLAVE_ICSER_SLAVE_ADDRESS_ENABLE_REGISTER_0 | + ((uint8_t) p_ctrl->p_cfg->general_call_enable << R_IIC0_ICSER_GCAE_Pos)); + + /* Allow timeouts to be generated on the low value of SCL using long count mode */ + p_ctrl->p_reg->ICMR2 = IIC_SLAVE_BUS_MODE_REGISTER_2_MASK; + + /* ICFER Register Settings: + * 1. Enable timeout function. + * 2. Disable master arbitration loss detection. + * 3. Enable NACK arbitration loss detection. + * 4. Enable Slave arbitration loss detection. + * 5. Enable NACK reception transfer suspension. + * 6. Do not use the digital noise filter circuit. + * 7. Use the SCL synchronous circuit. + * 8. Enable FM+ slope circuit if fast mode plus is enabled. + * (see "I2C Bus Function Enable Register" in the IIC section of the relevant hardware manual). + */ + p_ctrl->p_reg->ICFER = + (uint8_t) (((uint8_t) (I2C_SLAVE_RATE_FASTPLUS == p_ctrl->p_cfg->rate) << 7U) | + ((uint8_t) (0 < digital_filter_stages) << 5U) | + (uint8_t) IIC_SLAVE_FUNCTION_ENABLE_INIT_SETTINGS); + + /* Set the clock and slope circuits to match the data setup time specified by the I2C standard */ + /* This is set in the configuration structure by the tooling. */ + + /* Set the number of counts that the clock remains low, bit 7 to 5 should be written as 1 */ + p_ctrl->p_reg->ICBRL = + (uint8_t) (IIC_SLAVE_BUS_RATE_REG_RESERVED_BITS | + ((iic_slave_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->clock_settings.brl_value); + + /* ICBRH need not be updated. */ + /* Set the internal reference clock source for generating IIC clock */ + p_ctrl->p_reg->ICMR1 = (uint8_t) (IIC_SLAVE_BUS_MODE_REGISTER_1_MASK | + (uint8_t) ((((iic_slave_extended_cfg_t *) p_ctrl->p_cfg->p_extend)-> + clock_settings. + cks_value & + IIC_SLAVE_INTERNAL_REF_CLOCK_SELECT_MAX) << 4U)); + + /* 1. Set the digital filter. + * 2. ACKBT should be set to 0 after reset to send out an ACK upon slave address match. + * 3. Set WAIT bit based on user config. + * See "ICMR3 : I2C Bus Mode Register 3" : + * 'WAIT bit (WAIT)' and 'RDRFS bit (RDRF Flag Set Timing Select)' + * in the IIC section of the relevant hardware manual. + * Since RDRFS = 0: + * - SCLn line will *not* be held low at the falling edge of the 8th clock cycle. + * - RDRF flag will be set at the rising edge of the 9th clock cycle. (Cause of iic_rxi_slave) + * This means that iic_rxi_slave will be invoked during the 9th clock cycle (High) if there is no preemption. + * Set the WAIT = 1 so that the SCLn line is held low from the falling edge of the 9th clock cycle. + * This is done to support clock stretching during the 'iic_slave_initiate_transaction'/user event callback (more often) + * and if iic_rxi_slave can get preempted. + * + * Note 1: If the preemption happens after the Read API is called in the user event callback, + * WAIT = 1 will be able to handle that scenario, + * however if the preemption happens before, the slave will timeout if the Read API + * is not called within 'Long Timeout Mode' duration. + * + * Note 2: When WAIT = 1, this driver no longer supports data reception utilizing the double buffer HW setup. + * + * Note 3: WAIT bit is dont-care during transmission. + * */ + p_ctrl->p_reg->ICMR3 = (uint8_t) ((uint8_t) (digital_filter_stages > 0U ? (digital_filter_stages - 1U) : 0U) | + (uint8_t) (p_ctrl->p_cfg->clock_stretching_enable << R_IIC0_ICMR3_WAIT_Pos)); + + p_ctrl->p_reg->ICIER = (uint8_t) ((uint8_t) IIC_RXI_EN_BIT | (uint8_t) IIC_TXI_EN_BIT); + + /* Release IIC from internal reset */ + p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_SLAVE_ICCR1_ICE_BIT_MASK | IIC_SLAVE_ICCR1_SCL_SDA_OUTPUT_MASK); +} + +/*******************************************************************************************************************//** + * Setup the Slave Read/Write transaction by issuing RX Request or TX request to the application via callback. + * + * @param p_ctrl Pointer to the control structure. + * @param[in] slave_event Slave event to be reported via callback. + **********************************************************************************************************************/ +static void iic_slave_initiate_transaction (iic_slave_instance_ctrl_t * p_ctrl, i2c_slave_event_t slave_event) +{ + /* Set the status flag to ensure this conditional clause execution only once */ + p_ctrl->notify_request = true; + + /* Enable the Error ISR for servicing timeout,arbitration loss and a NACK detection conditions. */ + p_ctrl->p_reg->ICIER = (uint8_t) ((uint8_t) IIC_TMO_EN_BIT | + (uint8_t) IIC_ALD_EN_BIT | + (uint8_t) IIC_NAK_EN_BIT | + (uint8_t) IIC_RXI_EN_BIT | + (uint8_t) IIC_TXI_EN_BIT); + + /* Invoke callback for the user to call a valid API. */ + iic_slave_callback_request(p_ctrl, slave_event); + + /* Check if correct API is called here Check direction (API called) against slave event requested (ISR invoked) */ + if (!(((IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ == + p_ctrl->direction) && + ((I2C_SLAVE_EVENT_RX_REQUEST == slave_event) || (I2C_SLAVE_EVENT_GENERAL_CALL == slave_event))) || + ((IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE == + p_ctrl->direction) && (I2C_SLAVE_EVENT_TX_REQUEST == slave_event)))) + { + /* In case MasterWriteSlaveRead API is NOT called to service Master write operation a NACK is + * issued from the RXI ISR (which is fired once) and the bus is released. + * + * In case MasterWriteSlaveRead API is NOT called to service Master General Call operation a NACK is + * issued from the RXI ISR (which is fired once) and the bus is released. + * + * In case MasterReadSlaveWrite API is NOT called to service Master read operation the TXI will fire once, + * no data will be written to ICDRT and the master will read oxFF for every byte it tries to read. + * + * For both the cases above the slave callback is invoked with I2C_SLAVE_EVENT_ABORTED + * event to notify the user application. + * + */ + } + else + { + /* Enable start interrupt to detect restart condition t the end of the current transaction. */ + if (!p_ctrl->start_interrupt_enabled) + { + /* Enable the Start condition detection to trigger ERI ISR */ + + /* Since address match is detected, enable STOP and RESTART detection for Master Read Slave Write. + * This must be done conditionally only for Master Read Slave Write to prevent clearing the start bit + * in case a restart occurred (and got captured) while we were in the user callback. + * This capturing is made possible in the 'iic_rxi_slave' after the dummy read. + */ + if (IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE == p_ctrl->direction) + { + /* Clear the Start and Stop condition flag for Slave Read/Write operation */ + p_ctrl->p_reg->ICSR2 &= ((uint8_t) ~((uint8_t) ICSR2_STOP_BIT | (uint8_t) ICSR2_START_BIT)); + } + + /* Enable the Start and Stop condition detection interrupt */ + p_ctrl->p_reg->ICIER = (uint8_t) ((uint8_t) IIC_STP_EN_BIT | + (uint8_t) IIC_STR_EN_BIT | + (uint8_t) IIC_TMO_EN_BIT | + (uint8_t) IIC_ALD_EN_BIT | + (uint8_t) IIC_NAK_EN_BIT | + (uint8_t) IIC_RXI_EN_BIT | + (uint8_t) IIC_TXI_EN_BIT); + + p_ctrl->start_interrupt_enabled = true; + } + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to iic slave instance control block + * @param[in] event Event code + * @param[in] transaction_count Transaction count for iic slave + **********************************************************************************************************************/ +static void r_iic_slave_call_callback (iic_slave_instance_ctrl_t * p_ctrl, + i2c_slave_event_t event, + uint32_t transaction_count) +{ + i2c_slave_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2c_slave_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->bytes = transaction_count; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + iic_slave_prv_ns_callback p_callback = (iic_slave_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/******************************************************************************************************************//** + * Handles the receive data full interrupt when operating as a slave. + * + * @param[in] p_ctrl The target IIC block's control block. + *********************************************************************************************************************/ +static void iic_rxi_slave (iic_slave_instance_ctrl_t * p_ctrl) +{ + /* Perform dummy read after an address match detection. */ + if (!p_ctrl->do_dummy_read) + { + p_ctrl->do_dummy_read = true; + + volatile uint8_t address_and_intent = p_ctrl->p_reg->ICDRR; + + /* The below code enables/services 0 byte writes from Master.*/ + + /* For 7-bit address: slave addr | R/W + data + * For 10-bit addresss: + * read: slave high addr | W + slave low addr + data + stop + * write: slave high addr | W + slave low addr + restart + slave high addr | R + data + stop + */ + if ((p_ctrl->p_cfg->addr_mode == I2C_SLAVE_ADDR_MODE_7BIT) && (address_and_intent & 1U)) + { + p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(ICSR2_STOP_BIT); + } + else + { + p_ctrl->p_reg->ICSR2 &= ((uint8_t) ~((uint8_t) ICSR2_STOP_BIT | (uint8_t) ICSR2_START_BIT)); + } + + /* Enable the Stop condition detection interrupt. + * In case this is a greater than 0 byte write from Master and MasterWriteSlaveRead API is called + * in the callback with valid parameters, this flag will be appropriately updated by helper function - + * iic_slave_initiate_transaction. + * Start condition is enabled here for Master Write Slave Read case to trigger an interrupt on detecting + * a restart on the bus when slave is processing a long user callback. + * This enablement is harmless for Master Read Slave Write operation as its Start bit is not cleared + * (set during this address match). + * */ + p_ctrl->p_reg->ICIER = (uint8_t) ((uint8_t) IIC_RXI_EN_BIT | + (uint8_t) IIC_TXI_EN_BIT | + (uint8_t) IIC_STR_EN_BIT | + (uint8_t) IIC_STP_EN_BIT); + } + else + { + /* Check if the read request event has been notified through callback, if not provide the callback */ + if (!p_ctrl->notify_request) + { + /* Check if this is a General Call by Master */ + i2c_slave_event_t receive_callback_event = + (R_IIC0_ICSR1_GCA_Msk == + (p_ctrl->p_reg->ICSR1 & + R_IIC0_ICSR1_GCA_Msk)) ? I2C_SLAVE_EVENT_GENERAL_CALL : I2C_SLAVE_EVENT_RX_REQUEST; + iic_slave_initiate_transaction(p_ctrl, receive_callback_event); + } + +#if IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE + + /* Proceed reading data */ + if (IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ != p_ctrl->direction) + { + /* If the user application incorrectly handles Master Write, send a NACK to exit the transaction. */ + /* Do not dummy read here to allow slave to timeout */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; + p_ctrl->p_reg->ICMR3_b.ACKBT = 1; + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + } + else +#endif + { + if (0U == p_ctrl->total) /* Send NACK */ + { + /* Slave is sending a NACK. */ + /* Do dummy read to release SCL */ + volatile uint8_t dummy_read = p_ctrl->p_reg->ICDRR; + FSP_PARAMETER_NOT_USED(dummy_read); + + /* Set the response as NACK, since slave is not setup for reading any data from master at this time. + * This is an intentional way to let master know that the slave receiver cannot + * accept any data and hence should eventually result in I2C_SLAVE_EVENT_RX_COMPLETE. + */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; + p_ctrl->p_reg->ICMR3_b.ACKBT = 1; + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + } + +#if (IIC_SLAVE_CFG_DTC_ENABLE) + + /* If this is the interrupt that got fired after DTC transfer, + * ignore it as the DTC has already taken care of the data transfer */ + else if (true == p_ctrl->activation_on_rxi) + { + p_ctrl->activation_on_rxi = false; + } +#endif + + /* If master is requesting still more data than configured to be read, notify + * with a read more event in callback */ + else if (p_ctrl->total == p_ctrl->loaded) + { + iic_slave_callback_request(p_ctrl, I2C_SLAVE_EVENT_RX_MORE_REQUEST); + +#if IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE + if (IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ != p_ctrl->direction) + { + /* If the user application incorrectly handles Master Write, send a NACK to exit the transaction. */ + /* Do not dummy read here to allow slave to timeout */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; + p_ctrl->p_reg->ICMR3_b.ACKBT = 1; + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + } + else +#endif + { + if (0 == p_ctrl->total) /* Send NACK */ + { + /* Do dummy read to release SCL */ + volatile uint8_t dummy_read = p_ctrl->p_reg->ICDRR; + FSP_PARAMETER_NOT_USED(dummy_read); + + /* Set the response as NACK, since slave is not setup for reading more data from master at this time. + * This is an intentional way to let master know that the slave receiver cannot + * accept any more data and hence should eventually result in I2C_SLAVE_EVENT_RX_COMPLETE. + */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; + p_ctrl->p_reg->ICMR3_b.ACKBT = 1; + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + } + else + { + /* Read data */ + p_ctrl->p_buff[p_ctrl->loaded++] = p_ctrl->p_reg->ICDRR; + + /* Keep track of the the actual number of transactions */ + p_ctrl->transaction_count++; + +#if (IIC_SLAVE_CFG_DTC_ENABLE) + + /* Enable DTC if possible */ + if ((NULL != p_ctrl->p_cfg->p_transfer_rx) && (false == p_ctrl->activation_on_rxi) && + (p_ctrl->total > 1U)) + { + uint8_t volatile const * p_iic_slave_rx_buffer = &(p_ctrl->p_reg->ICDRR); + p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + (uint8_t *) (p_iic_slave_rx_buffer), + (void *) (p_ctrl->p_buff + 1U), + (uint16_t) (p_ctrl->total - 1U)); + p_ctrl->activation_on_rxi = true; + p_ctrl->transaction_count += p_ctrl->total - 1U; + p_ctrl->loaded = p_ctrl->total; + } +#endif + } + } + } + else + { + /* Read data */ + p_ctrl->p_buff[p_ctrl->loaded++] = p_ctrl->p_reg->ICDRR; + + /* Keep track of the the actual number of transactions */ + p_ctrl->transaction_count++; + +#if (IIC_SLAVE_CFG_DTC_ENABLE) + + /* Enable DTC to operate from 2nd data byte */ + if ((NULL != p_ctrl->p_cfg->p_transfer_rx) && (p_ctrl->total > 1U) && + (false == p_ctrl->activation_on_rxi)) + { + uint8_t volatile const * p_iic_slave_rx_buffer = &(p_ctrl->p_reg->ICDRR); + p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + (uint8_t *) (p_iic_slave_rx_buffer), + (void *) (p_ctrl->p_buff + 1U), + (uint16_t) (p_ctrl->total - 1U)); + p_ctrl->activation_on_rxi = true; + p_ctrl->transaction_count += p_ctrl->total - 1U; + p_ctrl->loaded = p_ctrl->total; + } +#endif + } + } + } +} + +/******************************************************************************************************************//** + * Handles the transmit data empty interrupt when operating as a slave. + * + * @param[in] p_ctrl The target IIC block's control block. + *********************************************************************************************************************/ +static void iic_txi_slave (iic_slave_instance_ctrl_t * p_ctrl) +{ + /* Check if the read request event has been notified through callback, if not provide the callback */ + if (!p_ctrl->notify_request) + { + iic_slave_initiate_transaction(p_ctrl, I2C_SLAVE_EVENT_TX_REQUEST); + } + + /* If MasterReadSlaveWrite API is invoked, proceed writing data */ + if (IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE != p_ctrl->direction) + { + /* MasterReadSlaveWrite API was not called in the callback. + * Master will read 0xFF for all the byte(s) for this transaction. + */ + } + else + { + /* If slave has exhausted the buffer length from application, wait for slave to transmit last byte on the bus + * and check for master is sending ACK or NACK. If master ACKs this last byte, it is expecting more data + * from slave. Slave has to notify this event to application via callback */ + if (p_ctrl->total == p_ctrl->loaded) + { + /* Clear the pending interrupts for TEI */ + R_BSP_IrqStatusClear(p_ctrl->p_cfg->tei_irq); + NVIC_ClearPendingIRQ(p_ctrl->p_cfg->tei_irq); + + /* Enable the TEI interrupt source */ + p_ctrl->p_reg->ICIER_b.TEIE = 1U; + } + else + { + /* Write the data byte, this will also release SCL */ + p_ctrl->p_reg->ICDRT = p_ctrl->p_buff[p_ctrl->loaded]; + p_ctrl->loaded++; + + /* Keep track of the the actual number of transactions */ + p_ctrl->transaction_count++; + +#if (IIC_SLAVE_CFG_DTC_ENABLE) + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && (p_ctrl->total > 2U) && + (false == p_ctrl->activation_on_txi) && (p_ctrl->loaded == 2U)) + { + uint8_t volatile const * p_iic_slave_tx_buffer = &(p_ctrl->p_reg->ICDRT); + p_ctrl->p_cfg->p_transfer_tx->p_api->reset(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + (void *) (p_ctrl->p_buff + 2U), + (uint8_t *) (p_iic_slave_tx_buffer), + (uint16_t) (p_ctrl->total - 2U)); + p_ctrl->transaction_count += p_ctrl->total - 2U; + p_ctrl->loaded = p_ctrl->total; + p_ctrl->activation_on_txi = true; + } +#endif + } + } +} + +/******************************************************************************************************************//** + * Handles the transmission end interrupt when operating as a slave. + * + * @param[in] p_ctrl The target IIC block's control block. + *********************************************************************************************************************/ +static void iic_tei_slave (iic_slave_instance_ctrl_t * p_ctrl) +{ + uint32_t timeout_count = IIC_SLAVE_PERIPHERAL_REG_MAX_WAIT; + + /* Check if ACK has been detected from master expecting further data */ + if (0 == p_ctrl->p_reg->ICMR3_b.ACKBR) + { + iic_slave_callback_request(p_ctrl, I2C_SLAVE_EVENT_TX_MORE_REQUEST); + + if (IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE != p_ctrl->direction) + { + /* MasterReadSlaveWrite API was not called in the callback. + * Master will read 0xFF for the remaining byte(s) for this transaction. + */ + } + else + { + p_ctrl->p_reg->ICDRT = p_ctrl->p_buff[p_ctrl->loaded]; + p_ctrl->loaded++; + p_ctrl->transaction_count++; + } + } + + /* Disable the interrupt as we are done with the transfer */ + p_ctrl->p_reg->ICIER_b.TEIE = 0U; + + /* Wait for the value to reflect at the peripheral. + * See 'Note' under table "Interrupt sources" in the IIC section of the relevant hardware manual. */ + IIC_SLAVE_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->ICIER_b.TEIE, 0U, timeout_count); +} + +/******************************************************************************************************************//** + * Handles the error interrupts when operating as a slave. + * + * @param[in] p_ctrl The target IIC block's control block. + *********************************************************************************************************************/ +static void iic_err_slave (iic_slave_instance_ctrl_t * p_ctrl) +{ + uint8_t error_events = IIC_SLAVE_STATUS_REGISTER_2_ERR_MASK & p_ctrl->p_reg->ICSR2; + + /* Timeout or Arbitration loss detected */ + if ((error_events & ICSR2_TMOF_BIT) || (error_events & ICSR2_AL_BIT)) + { + /* Clear the stop flag. This indicates an error. */ + p_ctrl->transaction_completed = false; + + iic_slave_notify(p_ctrl, I2C_SLAVE_EVENT_ABORTED); + } + /* Stop or restart condition detected, a valid end of transaction */ + else if ((error_events & ICSR2_START_BIT) || (error_events & ICSR2_STOP_BIT)) + { + i2c_slave_event_t i2c_event = I2C_SLAVE_EVENT_ABORTED; + + /* In case of stop (or restart), set the transaction_completed flag */ + p_ctrl->transaction_completed = true; + + /* Set the I2C event */ + if (IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ == p_ctrl->direction) + { + i2c_event = I2C_SLAVE_EVENT_RX_COMPLETE; + + /* + * This is to fix the issue that after sending NACK, slave application won't be able to get any events until call read API again. + * It is preferred to clear NACK bit in the driver to allow more granular ACK control from the slave side. + */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 1; /* Write Enable */ + p_ctrl->p_reg->ICMR3_b.ACKBT = 0; /* Write */ + p_ctrl->p_reg->ICMR3_b.ACKWP = 0; + +#if (IIC_SLAVE_CFG_DTC_ENABLE) + if ((NULL != p_ctrl->p_cfg->p_transfer_rx) && (true == p_ctrl->activation_on_rxi)) + { + transfer_properties_t transaction_property; + p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + &transaction_property); + p_ctrl->transaction_count -= transaction_property.transfer_length_remaining; + } +#endif + } + else + { + i2c_event = I2C_SLAVE_EVENT_TX_COMPLETE; + + /* Decrement the transaction count when slave configured to write more data than master requested. + * Addresses the exception raised from double buffer hardware implementation */ + if (p_ctrl->total > p_ctrl->loaded) + { + p_ctrl->transaction_count -= 1U; + } + +#if (IIC_SLAVE_CFG_DTC_ENABLE) + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && (true == p_ctrl->activation_on_txi)) + { + transfer_properties_t transaction_property; + p_ctrl->p_cfg->p_transfer_tx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + &transaction_property); + + /* Decrement the transaction count when slave configured to write more data than master requested. + * Addresses the exception raised from double buffer hardware implementation */ + if (transaction_property.transfer_length_remaining > 0) + { + p_ctrl->transaction_count -= 1U; + p_ctrl->transaction_count -= transaction_property.transfer_length_remaining; + } + } +#endif + } + + /* Notify the user */ + iic_slave_notify(p_ctrl, i2c_event); + } + /* NACK detected */ + else if (error_events & ICSR2_NACKF_BIT) + { + /* NACK interrupt will be triggered on MasterReadSlaveWrite operation. + * Do dummy read to release SCL + * Refer point #5 under Section "Slave Transmit Operation" in the IIC section of the relevant hardware manual. + */ + volatile uint8_t dummy_read = p_ctrl->p_reg->ICDRR; + FSP_PARAMETER_NOT_USED(dummy_read); + + /* Disable NACK interrupt, this is required since we will clear NACK flag only on detection of STOP bit or + * when a timeout occurs. Not clearing the flag will cause error interrupt to get triggered again. + */ + p_ctrl->p_reg->ICIER &= (uint8_t) ~(uint8_t) IIC_NAK_EN_BIT; +#if IIC_SLAVE_CFG_DTC_ENABLE + + /* Stop any DTC assisted transfer for tx */ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if (NULL != p_transfer_tx) + { + p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + } +#endif + } + else + { + /* No processing, should not come here */ + } +} + +#if IIC_SLAVE_CFG_DTC_ENABLE + +/*******************************************************************************************************************//** + * Enable the transfer driver to configure for IIC. + * + * @param[in] p_cfg Pointer to IIC specific configuration structure + * + * @retval FSP_SUCCESS Transfer interface initialized successfully. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL. + **********************************************************************************************************************/ +static fsp_err_t iic_slave_transfer_open (i2c_slave_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + if (NULL != p_cfg->p_transfer_rx) + { + err = iic_slave_transfer_configure(p_cfg->p_transfer_rx, IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (NULL != p_cfg->p_transfer_tx) + { + err = iic_slave_transfer_configure(p_cfg->p_transfer_tx, IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE); + if (FSP_SUCCESS != err) + { + if (NULL != p_cfg->p_transfer_rx) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + + return err; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures IIC related transfer drivers (if enabled) + * @param[in] p_transfer Pointer to IIC specific control structure + * @param[in] direction Pointer to IIC specific configuration structure + * + * @retval FSP_SUCCESS Transfer interface is configured with valid parameters. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL. + **********************************************************************************************************************/ +static fsp_err_t iic_slave_transfer_configure (transfer_instance_t const * p_transfer, + iic_slave_transfer_dir_t direction) +{ + fsp_err_t err; + + /* Set default transfer info and open receive transfer module, if enabled. */ + #if (IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + #endif + transfer_info_t * p_cfg = p_transfer->p_cfg->p_info; + if (IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ == direction) + { + p_cfg->transfer_settings_word = IIC_SLAVE_DTC_RX_TRANSFER_SETTINGS; + } + else + { + p_cfg->transfer_settings_word = IIC_SLAVE_DTC_TX_TRANSFER_SETTINGS; + } + + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); + + return FSP_SUCCESS; +} + +#endif + +/********************************************************************************************************************** + * Interrupt Vectors + *********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Receive data full interrupt routine. + * + * This function implements the IIC Receive buffer full ISR routine. + * + *********************************************************************************************************************/ +void iic_slave_rxi_isr(void); + +void iic_slave_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + iic_rxi_slave(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * Transmit data empty interrupt routine. + * + * This function implements the Transmit buffer empty ISR routine. + * + *********************************************************************************************************************/ +void iic_slave_txi_isr(void); + +void iic_slave_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + iic_txi_slave(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Transmit end interrupt routine. + * + * This function implements the IIC Transmission End ISR routine. + * + ***********************************************************************************************************************/ +void iic_slave_tei_isr(void); + +void iic_slave_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + iic_tei_slave(p_ctrl); + + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * Error and event interrupt routine. + * + * This function implements the IIC Event/Error. + * + *********************************************************************************************************************/ +void iic_slave_eri_isr(void); + +void iic_slave_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + iic_err_slave(p_ctrl); + + /* Clear the IR flag */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iirfa/r_iirfa.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iirfa/r_iirfa.c new file mode 100644 index 0000000000..71d0d542a4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iirfa/r_iirfa.c @@ -0,0 +1,388 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_iirfa.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define IIRFA_OPEN (0x52494952) +#define IIRFA_PRV_NUM_CHANNELS (16) + +#define IIRFA_FILTER_STAGES(stage_base, stage_num) \ + (UINT32_MAX << (32 - (stage_num))) >> (32 - (stage_num) - (stage_base)) + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* Filter stages in use */ +static uint32_t g_iirfa_filter_stages = 0U; + +const iir_api_t g_iir_on_iirfa = +{ + .open = R_IIRFA_Open, + .close = R_IIRFA_Close, + .configure = R_IIRFA_Configure, + .filter = R_IIRFA_Filter, + .statusGet = R_IIRFA_StatusGet, +}; + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IIRFA + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Prepare an IIR channel for filtering. + * + * @retval FSP_SUCCESS The channel was successfully opened. + * @retval FSP_ERR_ASSERTION One or both of the parameters was NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT An invalid channel was selected. + * @retval FSP_ERR_ALREADY_OPEN The instance is already opened. + **********************************************************************************************************************/ +fsp_err_t R_IIRFA_Open (iir_ctrl_t * const p_api_ctrl, iir_cfg_t const * const p_cfg) +{ + iirfa_instance_ctrl_t * p_ctrl = (iirfa_instance_ctrl_t *) p_api_ctrl; + +#if IIRFA_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_cfg->channel < IIRFA_PRV_NUM_CHANNELS, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(!p_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Start clocks to IIRFA */ + R_BSP_MODULE_START(FSP_IP_IIRFA, 0); + +#if (IIRFA_CFG_ECC_SUPPORT > 0) + + /* Set global ECC setting */ + R_IIRFA->IIRECCCNT = IIRFA_CFG_ECC_SUPPORT; +#endif + +#if (IIRFA_CFG_ROUNDING_MODE > 0) + + /* Set global rounding setting */ + R_IIRFA->IIROPCNT = IIRFA_CFG_ROUNDING_MODE; +#endif + + /* Set channel in control struct */ + p_ctrl->channel = p_cfg->channel; + + /* Initialize filter_stages */ + p_ctrl->filter_stages = 0; + + /* Mark control block as opened */ + p_ctrl->open = IIRFA_OPEN; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Start a filter operation on the specified data. + * + * @retval FSP_SUCCESS Data has been successfully filtered. + * @retval FSP_ERR_ASSERTION One of the provided pointers is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_INVALID_ARGUMENT num_samples is zero. + * @retval FSP_ERR_INVALID_RESULT The result of one or more calculations was +/- infinity. + * @retval FSP_ERR_NOT_INITIALIZED The filter is not configured. + * @retval FSP_ERR_IIRFA_ECC_1BIT A 1-bit ECC error was detected. + * @retval FSP_ERR_IIRFA_ECC_2BIT A 2-bit ECC error was detected. + **********************************************************************************************************************/ +fsp_err_t R_IIRFA_Filter (iir_ctrl_t * const p_api_ctrl, + float const * p_data_in, + float * p_data_out, + uint16_t const num_samples) +{ + iirfa_instance_ctrl_t * p_ctrl = (iirfa_instance_ctrl_t *) p_api_ctrl; + +#if IIRFA_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_data_in); + FSP_ASSERT(p_data_out); + FSP_ERROR_RETURN(IIRFA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(num_samples > 0, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_ctrl->filter_stages != 0, FSP_ERR_NOT_INITIALIZED); +#endif + + /* Get pointers for data and registers */ + volatile float * const p_reg_in = (volatile float *) &R_IIRFA->IIRCH[p_ctrl->channel].INP; + volatile float * const p_reg_out = (volatile float *) &R_IIRFA->IIRCH[p_ctrl->channel].OUT; + + /* Define temporary macro to clean up loop unrolling */ +#if IIRFA_CFG_LOOP_USE_POLLING + volatile uint8_t * const p_reg_status = (volatile uint8_t *) &R_IIRFA->IIRCH[p_ctrl->channel].STS; + #define IIRFA_PRV_PROCESS_SAMPLE \ + * p_reg_in = *p_data_in++; \ + while (!(*p_reg_status & R_IIRFA_IIRCH_STS_CPRCFF_Msk)) {;} \ + *p_data_out++ = *p_reg_out; +#else + #define IIRFA_PRV_PROCESS_SAMPLE \ + * p_reg_in = *p_data_in++; \ + *p_data_out++ = *p_reg_out; +#endif + + /* Perform filter operation */ + for (uint32_t sample = 0; sample < num_samples / IIRFA_CFG_LOOP_UNROLL_DEPTH; sample++) + { + /* Reading an IIRCHnOUT register will cause the bus to wait until data is ready. While the bus is waiting + * no interrupts will be handled. For this reason, the IIRCHnSTS register is polled for the CPRCFF flag first. + * See "Procedure for Channel Processing Execution" in the IIRFA section of the relevant hardware manual for + * further details. */ + IIRFA_PRV_PROCESS_SAMPLE; +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 2) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 3) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 4) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 5) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 6) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 7) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 8) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 9) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 10) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 11) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 12) + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 16) + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 20) + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 24) + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; +#endif +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH >= 32) + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; + IIRFA_PRV_PROCESS_SAMPLE; +#endif + } + +#if (IIRFA_CFG_LOOP_UNROLL_DEPTH > 1) + + /* Handle any remaining samples that don't fit into a multiple of the unroll depth */ + for (uint32_t sample = 0; sample < (num_samples % IIRFA_CFG_LOOP_UNROLL_DEPTH); sample++) + { + IIRFA_PRV_PROCESS_SAMPLE; + } +#endif + + /* Undefine temporary macro */ +#undef IIRFA_PRV_PROCESS_SAMPLE + + /* Check to ensure there were no errors in processing */ +#if IIRFA_CFG_ECC_SUPPORT + uint32_t iireccef = R_IIRFA->IIRECCEF; + if ((R_IIRFA->IIRCERRF & (1 << p_ctrl->channel)) || (iireccef > 0)) + { + /* Clear channel error status bits */ + R_IIRFA->IIRCH[p_ctrl->channel].FCLR_b.CERRFCLR = 1; + R_IIRFA->IIRECCEFCLR = iireccef; + + /* Determine if a 1- or 2-bit ECC error has occurred */ + fsp_err_t err = FSP_ERR_INVALID_RESULT; + if (iireccef > 0) + { + err = (iireccef & R_IIRFA_IIRECCEF_EDEF_Msk) ? FSP_ERR_IIRFA_ECC_2BIT : FSP_ERR_IIRFA_ECC_1BIT; + } + + return err; + } + +#else + + /* Check to ensure there were no errors in processing */ + if (R_IIRFA->IIRCERRF & (1 << p_ctrl->channel)) + { + /* Clear channel error status bit */ + R_IIRFA->IIRCH[p_ctrl->channel].FCLR_b.CERRFCLR = 1; + + return FSP_ERR_INVALID_RESULT; + } +#endif + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Configure filter coefficients and state values. + * + * @retval FSP_SUCCESS Configuration successful. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid filter stage selection. + * @retval FSP_ERR_IN_USE One or more requested filter stages are currently in use. + **********************************************************************************************************************/ +fsp_err_t R_IIRFA_Configure (iir_ctrl_t * const p_api_ctrl, iir_filter_cfg_t const * const p_filter_cfg) +{ + iirfa_instance_ctrl_t * p_ctrl = (iirfa_instance_ctrl_t *) p_api_ctrl; + +#if IIRFA_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_filter_cfg); + FSP_ERROR_RETURN(IIRFA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_filter_cfg->stage_base < 32, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_filter_cfg->stage_num && (p_filter_cfg->stage_num <= (32 - p_filter_cfg->stage_base)), + FSP_ERR_INVALID_ARGUMENT); +#endif + + /* Calculate requested filter stage mask by shifting all 1s left then right */ + uint32_t filter_stages = IIRFA_FILTER_STAGES(p_filter_cfg->stage_base, p_filter_cfg->stage_num); +#if IIRFA_CFG_PARAM_CHECKING_ENABLE + + /* Ensure the requested stages are not in use */ + FSP_ERROR_RETURN(!(filter_stages & (g_iirfa_filter_stages & ~p_ctrl->filter_stages)), FSP_ERR_IN_USE); +#endif + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Keep track of what stages are used globally */ + g_iirfa_filter_stages = (g_iirfa_filter_stages & ~p_ctrl->filter_stages) | filter_stages; + + FSP_CRITICAL_SECTION_EXIT; + + p_ctrl->filter_stages = filter_stages; + + /* Set selected stages */ + R_IIRFA->IIRCH[p_ctrl->channel].CNT = filter_stages; + + uint32_t stage_base = p_filter_cfg->stage_base; + uint32_t stage_num = p_filter_cfg->stage_num; + + for (uint32_t stage = stage_base; stage < (stage_base + stage_num); stage++) + { + *(iir_filter_coeffs_t *) &R_IIRFA->IIRSTG[stage].B0 = p_filter_cfg->p_filter_coeffs[stage - stage_base]; + *(iir_filter_state_t *) &R_IIRFA->IIRSTG[stage].D0 = p_filter_cfg->p_filter_state[stage - stage_base]; + } + + p_ctrl->stage_base = (uint8_t) stage_base; + p_ctrl->stage_num = (uint8_t) stage_num; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Read the current filter state variables. + * + * @retval FSP_SUCCESS Information read successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + **********************************************************************************************************************/ +fsp_err_t R_IIRFA_StatusGet (iir_ctrl_t * const p_api_ctrl, iir_status_t * const p_status) +{ + iirfa_instance_ctrl_t * p_ctrl = (iirfa_instance_ctrl_t *) p_api_ctrl; + +#if IIRFA_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(IIRFA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Only fill in state array if present */ + iir_filter_state_t * p_filter_state = p_status->p_filter_state; + if (p_filter_state != NULL) + { + uint32_t stage_base = p_ctrl->stage_base; + uint32_t stage_num = p_ctrl->stage_num; + + /* Write current state variables to provided filter config */ + for (uint32_t stage = stage_base; stage < (stage_base + stage_num); stage++) + { + p_filter_state[stage - stage_base].d0 = *((float *) &R_IIRFA->IIRSTG[stage].D0); + p_filter_state[stage - stage_base].d1 = *((float *) &R_IIRFA->IIRSTG[stage].D1); + } + } + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Stop filter operations and close the channel instance. + * + * @retval FSP_SUCCESS The channel is successfully closed. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + **********************************************************************************************************************/ +fsp_err_t R_IIRFA_Close (iir_ctrl_t * const p_api_ctrl) +{ + iirfa_instance_ctrl_t * p_ctrl = (iirfa_instance_ctrl_t *) p_api_ctrl; + +#if IIRFA_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(IIRFA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear channel stages in case another channel needs to use them */ + R_IIRFA->IIRCH[p_ctrl->channel].CNT = 0U; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Release stages in g_iirfa_filter_stages */ + g_iirfa_filter_stages &= ~p_ctrl->filter_stages; + + FSP_CRITICAL_SECTION_EXIT; + + /* Set control block to closed */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IIRFA) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ioport/r_ioport.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ioport/r_ioport.c new file mode 100644 index 0000000000..f747af1aad --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ioport/r_ioport.c @@ -0,0 +1,1034 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "r_ioport_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "PORT" in ASCII, used to determine if the module is open */ +#define IOPORT_OPEN (0x504F5254U) +#define IOPORT_CLOSED (0x00000000U) + +/* Mask to get PSEL bitfield from PFS register. */ +#define BSP_PRV_PFS_PSEL_MASK (R_PFS_PORT_PIN_PmnPFS_PSEL_Msk) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define IOPORT_PRV_PORT_OFFSET (8U) + +#define IOPORT_PRV_PORT_BITS (0xFF00U) +#define IOPORT_PRV_PIN_BITS (0x00FFU) + +#define IOPORT_PRV_PERIPHERAL_FUNCTION (1U << 16) + +#define IOPORT_PRV_8BIT_MASK (0xFFU) +#define IOPORT_PRV_16BIT_MASK (0xFFFFU) + +#define IOPORT_PRV_PORT_ADDRESS(port_number) ((uint32_t) (R_PORT1 - R_PORT0) * (port_number) + R_PORT0) + +/* Stabilization time when output current control is enabled */ +#define IOPORT_PRV_CCDE_STABILIZATION_DELAY_US (10U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_ioport_pins_config(const ioport_cfg_t * p_cfg); + +#if BSP_FEATURE_ELC_VERSION +static void r_ioport_hw_pin_event_output_data_write(bsp_io_port_t port, ioport_size_t pin, bsp_io_level_t pin_level); + +#endif + +static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value); + +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN +static void bsp_vbatt_init(ioport_cfg_t const * const p_pin_cfg); // Used internally by BSP + +#endif + +#if IOPORT_CFG_CCD_SUPPORT_ENABLE +static fsp_err_t r_ioport_ccd_pins_config(const ioport_extended_cfg_t * p_cfg_extend); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* IOPort Implementation of IOPort Driver */ +const ioport_api_t g_ioport_on_ioport = +{ + .open = R_IOPORT_Open, + .close = R_IOPORT_Close, + .pinsCfg = R_IOPORT_PinsCfg, + .pinCfg = R_IOPORT_PinCfg, + .pinEventInputRead = R_IOPORT_PinEventInputRead, + .pinEventOutputWrite = R_IOPORT_PinEventOutputWrite, + .pinRead = R_IOPORT_PinRead, + .pinWrite = R_IOPORT_PinWrite, + .portDirectionSet = R_IOPORT_PortDirectionSet, + .portEventInputRead = R_IOPORT_PortEventInputRead, + .portEventOutputWrite = R_IOPORT_PortEventOutputWrite, + .portRead = R_IOPORT_PortRead, + .portWrite = R_IOPORT_PortWrite, +}; + +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN +static const bsp_io_port_pin_t g_vbatt_pins_input[] = +{ + BSP_IO_PORT_04_PIN_02, ///< Associated with VBTICTLR->VCH0INEN + BSP_IO_PORT_04_PIN_03, ///< Associated with VBTICTLR->VCH1INEN + BSP_IO_PORT_04_PIN_04 ///< Associated with VBTICTLR->VCH2INEN +}; +#endif + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes internal driver data, then calls pin configuration function to configure pins. + * + * @retval FSP_SUCCESS Pin configuration data written to PFS register(s) + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_INVALID_ARGUMENT Pin configurations is invalid. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data || 0 == p_cfg->number_of_pins); + FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set driver status to open */ + p_instance_ctrl->open = IOPORT_OPEN; + +#if IOPORT_CFG_CCD_SUPPORT_ENABLE + if (NULL != p_cfg->p_extend) + { + FSP_ERROR_RETURN(FSP_SUCCESS == r_ioport_ccd_pins_config((ioport_extended_cfg_t *) p_cfg->p_extend), + FSP_ERR_INVALID_ARGUMENT); + } +#endif + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets IOPORT registers. Implements @ref ioport_api_t::close + * + * @retval FSP_SUCCESS The IOPORT was successfully uninitialized + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set state to closed */ + p_instance_ctrl->open = IOPORT_CLOSED; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the functions of multiple pins by loading configuration data into pin PFS registers. + * Implements @ref ioport_api_t::pinsCfg. + * + * This function initializes the supplied list of PmnPFS registers with the supplied values. This data can be generated + * by the Pins tab of the RA Configuration editor or manually by the developer. Different pin configurations can be + * loaded for different situations such as low power modes and testing. + * + * @retval FSP_SUCCESS Pin configuration data written to PFS register(s) + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg. + * + * @retval FSP_SUCCESS Pin configured + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. + * This function will change the configuration of the pin with the new configuration. For example it is not possible + * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To + * achieve this the original settings with the required change will need to be written using this function. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN + + /* Create temporary structure for handling VBATT pins. */ + ioport_cfg_t temp_cfg; + ioport_pin_cfg_t temp_pin_cfg; + + temp_pin_cfg.pin = pin; + temp_pin_cfg.pin_cfg = cfg; + + temp_cfg.number_of_pins = 1U; + temp_cfg.p_pin_cfg_data = &temp_pin_cfg; + + /* Handle any VBATT domain pin configuration. */ + bsp_vbatt_init(&temp_cfg); +#endif + + R_BSP_PinAccessEnable(); + + r_ioport_pfs_write(pin, cfg); + + R_BSP_PinAccessDisable(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the level on a pin. Implements @ref ioport_api_t::pinRead. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different pins. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_pin_value = (bsp_io_level_t) R_BSP_PinRead(pin); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value on an IO port. Implements @ref ioport_api_t::portRead. + * + * The specified port will be read, and the levels for all the pins will be returned. + * Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds + * to pin 7, bit 6 to pin 6, and so on. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_port_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); +#if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Read current value of PIDR for the specified port */ + *p_port_value = p_ioport_regs->PIDR; +#else + + /* Read current value of PCNTR2 register for the specified port */ + *p_port_value = p_ioport_regs->PCNTR2 & IOPORT_PRV_16BIT_MASK; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite. + * + * The input value will be written to the specified port. Each bit in the value parameter corresponds to a bit + * on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * Each bit in the mask parameter corresponds to a pin on the port. + * + * Only the bits with the corresponding bit in the mask value set will be updated. + * For example, value = 0xFFFF, mask = 0x0003 results in only bits 0 and 1 being updated. + * + * @retval FSP_SUCCESS Port written to + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. This function makes use of the PCNTR3 register to atomically + * modify the levels on the specified pins on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + ioport_size_t setbits; + ioport_size_t clrbits; + + /* High bits */ + setbits = value & mask; + + /* Low bits */ + /* Cast to ensure size */ + clrbits = (ioport_size_t) ((~value) & mask); + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + +#if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Reset data in PORR, set data in POSR register */ + p_ioport_regs->PORR = (uint16_t) clrbits; + p_ioport_regs->POSR = (uint16_t) setbits; +#else + + /* PCNTR3 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite. + * + * @retval FSP_SUCCESS Pin written to + * @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. This function makes use of the PCNTR3 register to atomically + * modify the level on the specified pin on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + ioport_size_t setbits = 0U; + ioport_size_t clrbits = 0U; + bsp_io_port_t port = (bsp_io_port_t) (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin); + + ioport_size_t shift = IOPORT_PRV_PIN_BITS & (ioport_size_t) pin; + ioport_size_t pin_mask = (ioport_size_t) (1U << shift); + + if (BSP_IO_LEVEL_LOW == level) + { + clrbits = pin_mask; + } + else + { + setbits = pin_mask; + } + + /* PCNTR register is updated instead of using PFS as access is atomic and PFS requires separate enable/disable + * using PWPR register */ + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); +#if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Reset data in PORR, set data in POSR register */ + p_ioport_regs->PORR = (uint16_t) clrbits; + p_ioport_regs->POSR = (uint16_t) setbits; +#else + + /* PCNTR3 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet(). + * + * Multiple pins on a port can be set to inputs or outputs at once. + * Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to + * pin 7, bit 6 to pin 6, and so on. If a bit is set to 1 then the corresponding pin will be changed to + * an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of + * the pin will not be changed. + * + * @retval FSP_SUCCESS Port direction updated + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask) +{ + uint32_t orig_value; + uint32_t set_bits; + uint32_t clr_bits; + uint32_t write_value; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); +#if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Read current value of PDR register for the specified port */ + orig_value = p_ioport_regs->PDR; +#else + + /* Read current value of PCNTR1 register for the specified port */ + orig_value = p_ioport_regs->PCNTR1; +#endif + + /* High bits */ + set_bits = direction_values & mask; + + /* Low bits */ + /* Cast to ensure size */ + clr_bits = (uint32_t) ((~direction_values) & mask); + + /* New value to write to port direction register */ + write_value = orig_value; + write_value |= set_bits; + + /* Clear bits as needed */ + write_value &= ~clr_bits; +#if (3U == BSP_FEATURE_IOPORT_VERSION) + p_ioport_regs->PDR = (uint16_t) write_value; +#else + p_ioport_regs->PCNTR1 = write_value; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead(). + * + * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port. + * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * + * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_UNSUPPORTED Function not supported. + * + * @note This function is re-entrant for different ports. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data) +{ +#if (3U != BSP_FEATURE_IOPORT_VERSION) + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_event_data); + uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS_MASK & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(port >> IOPORT_PRV_PORT_OFFSET & IOPORT_PRV_8BIT_MASK); + + /* Read current value of EIDR value from PCNTR2 register for the specified port */ + *p_event_data = p_ioport_regs->PCNTR2_b.EIDR; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(p_event_data); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead. + * + * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT. + * @retval FSP_ERR_UNSUPPORTED Function not supported. + * + * @note This function is re-entrant. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event) +{ +#if (3U != BSP_FEATURE_IOPORT_VERSION) + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_event); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS_MASK & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + ioport_size_t portvalue; + ioport_size_t mask; + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((pin >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + + /* Read current value of EIDR value from PCNTR2 register for the specified port */ + portvalue = p_ioport_regs->PCNTR2_b.EIDR; + mask = (ioport_size_t) (1U << (IOPORT_PRV_PIN_BITS & (bsp_io_port_t) pin)); + + if ((portvalue & mask) == mask) + { + *p_pin_event = BSP_IO_LEVEL_HIGH; + } + else + { + *p_pin_event = BSP_IO_LEVEL_LOW; + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(pin); + FSP_PARAMETER_NOT_USED(p_pin_event); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * This function writes the set and reset event output data for a port. Implements + * @ref ioport_api_t::portEventOutputWrite. + * + * Using the event system enables a port state to be stored by this function in advance of being output on the port. + * The output to the port will occur when the ELC event occurs. + * + * The input value will be written to the specified port when an ELC event configured for that port occurs. + * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7, + * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port. + * + * @retval FSP_SUCCESS Port event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_UNSUPPORTED Function not supported + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value) +{ +#if BSP_FEATURE_ELC_VERSION + ioport_size_t set_bits; + ioport_size_t reset_bits; + + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS_MASK & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + set_bits = event_data & mask_value; + + /* Cast to ensure size */ + reset_bits = (ioport_size_t) ((~event_data) & mask_value); + + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + #if (3U == BSP_FEATURE_IOPORT_VERSION) + + /* Reset data in EORR, set data in EOSR register */ + p_ioport_regs->EOSR = (uint16_t) set_bits; + p_ioport_regs->EORR = (uint16_t) reset_bits; + #else + + /* PCNTR4 register: lower word = set data, upper word = reset_data */ + p_ioport_regs->PCNTR4 = (uint32_t) (((uint32_t) reset_bits << 16) | set_bits); + #endif + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(event_data); + FSP_PARAMETER_NOT_USED(mask_value); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/**********************************************************************************************************************//** + * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite. + * + * Using the event system enables a pin state to be stored by this function in advance of being output on the pin. + * The output to the pin will occur when the ELC event occurs. + * + * @retval FSP_SUCCESS Pin event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_UNSUPPORTED Function not supported + * + * @note This function is re-entrant for different ports. + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value) +{ +#if BSP_FEATURE_ELC_VERSION + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((BSP_FEATURE_IOPORT_ELC_PORTS_MASK & (1 << port_number)), FSP_ERR_INVALID_ARGUMENT); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + r_ioport_hw_pin_event_output_data_write((bsp_io_port_t) (pin & IOPORT_PRV_PORT_BITS), + (ioport_size_t) (pin & IOPORT_PRV_PIN_BITS), pin_value); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(pin); + FSP_PARAMETER_NOT_USED(pin_value); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IOPORT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures pins. + * + * @param[in] p_cfg Pin configuration data + **********************************************************************************************************************/ +void r_ioport_pins_config (const ioport_cfg_t * p_cfg) +{ +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN + + /* Handle any VBATT domain pin configuration. */ + bsp_vbatt_init(p_cfg); +#endif + + uint16_t pin_count; + ioport_cfg_t * p_pin_data; + + p_pin_data = (ioport_cfg_t *) p_cfg; + + R_BSP_PinAccessEnable(); // Protect PWPR from re-entrancy + + for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++) + { + r_ioport_pfs_write(p_pin_data->p_pin_cfg_data[pin_count].pin, p_pin_data->p_pin_cfg_data[pin_count].pin_cfg); + } + + R_BSP_PinAccessDisable(); +} + +#if BSP_FEATURE_ELC_VERSION + +/*******************************************************************************************************************//** + * Writes the set and clear values on a pin of the port when an ELC event occurs. This allows accurate timing of + * pin output level. + * + * @param[in] port Port to read event data + * @param[in] pin Bit in the EORR/EOSR to be set + * @param[in] pin_level Event data for pin + **********************************************************************************************************************/ +static void r_ioport_hw_pin_event_output_data_write (bsp_io_port_t port, ioport_size_t pin, bsp_io_level_t pin_level) +{ + /* Get the port address */ + R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK); + #if (3U == BSP_FEATURE_IOPORT_VERSION) + uint16_t set_value_high = (uint16_t) (pin_level << pin); + uint16_t set_value_low = (uint16_t) ((!pin_level) << pin); + + /* Ensure the same bits are not set in both registers */ + p_ioport_regs->EORR &= ~set_value_high; + p_ioport_regs->EOSR = (p_ioport_regs->EOSR & ~set_value_low) | set_value_high; + p_ioport_regs->EORR |= set_value_low; + #else + uint32_t set_value = (uint32_t) (1 << pin); + + /* Read current value of PCNTR4 register */ + uint32_t port_value = p_ioport_regs->PCNTR4; + + if (BSP_IO_LEVEL_HIGH == pin_level) + { + /* To avoid setting bit high in both EOSR and EORR */ + port_value &= ~(set_value << 16); + + /* Set output high */ + port_value |= set_value; + } + else + { + /* To avoid setting bit high in both EOSR and EORR */ + port_value &= ~set_value; + + /* Set output low */ + port_value |= set_value << 16; + } + p_ioport_regs->PCNTR4 = port_value; + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Writes to the specified pin's PFS register + * + * @param[in] pin Pin to write PFS data for + * @param[in] value Value to be written to the PFS register + * + **********************************************************************************************************************/ +static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value) +{ +#if (3U != BSP_FEATURE_IOPORT_VERSION) + + /* PMR bits should be cleared before specifying PSEL. See "Notes on the PmnPFS Register Setting" + * in the I/O Ports section of the relevant hardware manual. */ + if ((value & IOPORT_PRV_PERIPHERAL_FUNCTION) > 0) + { + /* Clear PMR */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PMR = 0; + + /* New config with PMR = 0 */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & + BSP_IO_PRV_8BIT_MASK].PmnPFS = + (value & ~((uint32_t) IOPORT_PRV_PERIPHERAL_FUNCTION)); + } + + /* Write configuration */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = value; +#else + + /* Write configuration */ + R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (uint16_t) value; +#endif +} + +#if BSP_FEATURE_RTC_HAS_VBTICTLR || BSP_FEATURE_RTC_HAS_TCEN + +/*******************************************************************************************************************//** + * @brief Initializes VBTICTLR register based on pin configuration. + * + * The VBTICTLR register may need to be modified based on the project's pin configuration. There is a set of pins that + * needs to be checked. If one of these pins is found in the pin configuration table then it will be tested to see if + * the appropriate VBTICTLR bit needs to be set or cleared. If one of the pins that is being searched for is not found + * then the accompanying VBTICTLR bit is left as-is. + **********************************************************************************************************************/ +static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg) +{ + uint32_t pin_index; + uint32_t vbatt_index; + + #if BSP_FEATURE_RTC_HAS_VBTICTLR + R_SYSTEM_Type * p_system = R_SYSTEM; + #endif + #if BSP_FEATURE_RTC_HAS_TCEN + R_RTC_Type * p_rtc = R_RTC; + #endif + + #if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_NS_OFFSET > 0 + #if BSP_FEATURE_RTC_HAS_VBTICTLR + if (1 == R_SYSTEM->BBFSAR_b.NONSEC2) + { + /* If security attribution of VBTICTLR is set to non-secure, then use the non-secure alias. */ + p_system = (R_SYSTEM_Type *) ((uint32_t) p_system | BSP_FEATURE_TZ_NS_OFFSET); + } + #endif + + #if BSP_FEATURE_RTC_HAS_TCEN + #if (BSP_FEATURE_TZ_NS_OFFSET == 0) + if (1 == R_PSCU->PSARE_b.PSARE2) + #else + if (1 == R_PSCU->PSARE_b.PSARE3) + #endif + { + /* If security attribution of RTC is set to non-secure, then use the non-secure alias. */ + p_rtc = (R_RTC_Type *) ((uint32_t) p_rtc | BSP_FEATURE_TZ_NS_OFFSET); + } + #endif + #endif + + /* Must loop over all pins as pin configuration table is unordered. */ + for (pin_index = 0U; pin_index < p_pin_cfg->number_of_pins; pin_index++) + { + /* Loop over VBATT input pins. */ + for (vbatt_index = 0U; + vbatt_index < (sizeof(g_vbatt_pins_input) / sizeof(g_vbatt_pins_input[0])); + vbatt_index++) + { + if (p_pin_cfg->p_pin_cfg_data[pin_index].pin == g_vbatt_pins_input[vbatt_index]) + { + /* Get PSEL value for pin. */ + uint32_t pfs_psel_value = p_pin_cfg->p_pin_cfg_data[pin_index].pin_cfg & BSP_PRV_PFS_PSEL_MASK; + + /* Check if pin is being used for RTC or AGT use. */ + if ((IOPORT_PERIPHERAL_AGT == pfs_psel_value) || (IOPORT_PERIPHERAL_CLKOUT_COMP_RTC == pfs_psel_value)) + { + /* Bit should be set to 1. */ + #if BSP_FEATURE_RTC_HAS_VBTICTLR + #if BSP_TZ_NONSECURE_BUILD + if (0 == R_SYSTEM->BBFSAR_b.NONSEC2) + { + /* Do nothing: non secure build can't configure secure VBTICTLR register. */ + } + else + #endif + if (0 == (p_system->VBTICTLR & (uint8_t) (1U << vbatt_index))) + { + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + p_system->VBTICTLR |= (uint8_t) (1U << vbatt_index); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } + else + { + /* Do nothing: it is already enabled. */ + } + #endif + #if BSP_FEATURE_RTC_HAS_TCEN + #if BSP_TZ_NONSECURE_BUILD + #if (BSP_FEATURE_TZ_NS_OFFSET == 0) + if (0 == R_PSCU->PSARE_b.PSARE2) + #else + if (0 == R_PSCU->PSARE_b.PSARE3) + #endif + { + /* Do nothing: non secure build can't configure secure RTC registers. */ + } + else + #endif + { + if (0 == p_rtc->RTCCR[vbatt_index].RTCCR_b.TCEN) + { + p_rtc->RTCCR[vbatt_index].RTCCR_b.TCEN = 1; + R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else + { + /* Do nothing: it is already enabled. */ + } + } + #endif + } + else + { + /* Bit should be cleared to 0. */ + #if BSP_FEATURE_RTC_HAS_VBTICTLR + #if BSP_TZ_NONSECURE_BUILD + if (0 == R_SYSTEM->BBFSAR_b.NONSEC2) + { + /* Do nothing: non secure build can't configure secure VBTICTLR register. */ + } + else + #endif + if ((p_system->VBTICTLR & (uint8_t) (1U << vbatt_index)) > 0) + { + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + p_system->VBTICTLR &= (uint8_t) ~(1U << vbatt_index); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + } + else + { + /* Do nothing: it is already disabled. */ + } + #endif + #if BSP_FEATURE_RTC_HAS_TCEN + #if BSP_TZ_NONSECURE_BUILD + #if (BSP_FEATURE_TZ_NS_OFFSET == 0) + if (0 == R_PSCU->PSARE_b.PSARE2) + #else + if (0 == R_PSCU->PSARE_b.PSARE3) + #endif + { + /* Do nothing: non secure build can't configure secure RTC registers. */ + } + else + #endif + { + if (p_rtc->RTCCR[vbatt_index].RTCCR_b.TCEN > 0) + { + p_rtc->RTCCR[vbatt_index].RTCCR_b.TCEN = 0; + R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else + { + /* Do nothing: it is already disabled. */ + } + } + #endif + } + } + } + } +} + +#endif + +#if IOPORT_CFG_CCD_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * @brief Initializes the low-level output current control settings for CCD pins. + * + * This internal function configures the low-level output current values for CCD pins based on the provided extended + * configuration. It updates the CCS registers with the specified current levels, modifies the CCDE register to enable + * the required CCD pins, and waits for stabilization. + * + * @retval FSP_SUCCESS CCD pins configured. + * @retval FSP_ERR_INVALID_ARGUMENT CCD pin configurations are invalid. + * + **********************************************************************************************************************/ +static fsp_err_t r_ioport_ccd_pins_config (const ioport_extended_cfg_t * p_cfg_extend) +{ + uint8_t ccde_value = 0U; + + for (uint8_t index = 0; index < IOPORT_PRV_CCD_PIN_COUNT; index++) + { + ioport_output_current_t ccd_cfg = p_cfg_extend->ccd_pin_cfg_data[index]; + #if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + + /* 15 mA is only for CCD4 to CCD7 */ + FSP_ERROR_RETURN(((IOPORT_OUTPUT_CURRENT_15_MA != ccd_cfg) || (index > 3)), FSP_ERR_INVALID_ARGUMENT); + #endif + if ((BSP_FEATURE_IOPORT_CCD_PINS_MASK & (1U << index)) && (IOPORT_OUTPUT_CURRENT_DISABLE != ccd_cfg)) + { + R_PORGA->CCS[index] = (uint8_t) ccd_cfg; + ccde_value |= (1U << index); + } + } + + R_PORGA->CCDE = ccde_value; + + /* Wait for the stable time (10 us). See in hardware manual: IOPORT > Register Descriptions > CCDE */ + R_BSP_SoftwareDelay(IOPORT_PRV_CCDE_STABILIZATION_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + return FSP_SUCCESS; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ipc/r_ipc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ipc/r_ipc.c new file mode 100644 index 0000000000..eee80cdbbc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ipc/r_ipc.c @@ -0,0 +1,429 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_ipc.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "RIPC" in ASCII. Used to determine if the control block is open. */ +#define IPC_OPEN (0x52495043U) + +/* IPC0 is Core1 -> Core0, IPC1 is Core0 -> Core1 */ +#if (BSP_CFG_CPU_CORE == 0) + #define IPC_PRV_SEND_UNIT IPC1 + #define IPC_PRV_RECEIVE_UNIT IPC0 +#else + #define IPC_PRV_SEND_UNIT IPC0 + #define IPC_PRV_RECEIVE_UNIT IPC1 +#endif + +/* Mask for IPC event bits to pass into callback */ +#define IPC_PRV_EVENT_MASK (~(R_IPC_IPC_CH_STA_RDY_Msk | R_IPC_IPC_CH_STA_FULL_Msk)) + +#define IPC_PRV_VALID_CHANNEL_MASK (3U) // Mask is per IPC unit + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * ipc_prv_ns_callback)(ipc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile ipc_prv_ns_callback)(ipc_callback_args_t * p_args); +#endif + +/********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +const ipc_api_t g_ipc_on_ipc = +{ + .open = R_IPC_Open, + .messageSend = R_IPC_MessageSend, + .eventGenerate = R_IPC_EventGenerate, + .callbackSet = R_IPC_CallbackSet, + .close = R_IPC_Close, +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/* Interrupt service routines */ +void ipc_isr(void); + +#if (IPC_CFG_PARAM_CHECKING_ENABLE) +static fsp_err_t r_ipc_common_parameter_checking(ipc_instance_ctrl_t const * const p_ctrl); + +#endif + +static void r_ipc_call_callback(ipc_instance_ctrl_t * p_ctrl, ipc_event_t event); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IPC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the IPC driver channel based on the input configuration. + * + * Implements @ref ipc_api_t::open. + * + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to IPC control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for + * other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_IPC_Open (ipc_ctrl_t * const p_api_ctrl, ipc_cfg_t const * const p_cfg) +{ + ipc_instance_ctrl_t * p_ctrl = (ipc_instance_ctrl_t *) p_api_ctrl; + +#if IPC_CFG_PARAM_CHECKING_ENABLE + + /* Check for null parameters */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + + /* Check control block isn't already open */ + FSP_ERROR_RETURN(p_ctrl->open != IPC_OPEN, FSP_ERR_ALREADY_OPEN); + + FSP_ERROR_RETURN(IPC_PRV_VALID_CHANNEL_MASK & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Callback should not be NULL when interrupt is configured */ + if (p_cfg->irq >= 0) + { + FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT); + FSP_ASSERT(NULL != p_cfg->p_callback); + } +#endif + + /* Initialize control block */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Set instance IPC registers based on channel and current core */ + p_ctrl->p_send_reg = (R_IPC_IPC_CH_Type *) &(R_IPC->IPC_PRV_SEND_UNIT.CH[p_cfg->channel]); + p_ctrl->p_recv_reg = (R_IPC_IPC_CH_Type *) &(R_IPC->IPC_PRV_RECEIVE_UNIT.CH[p_cfg->channel]); + + /* Enable IRQ if it is set */ + if (p_cfg->irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->irq, p_cfg->ipl, p_ctrl); + } + + /* Mark the control block as open */ + p_ctrl->open = IPC_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sends a message over the configured IPC channel. + * + * Implements @ref ipc_api_t::messageSend. + * + * + * @retval FSP_SUCCESS Message written to FIFO successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INSUFFICIENT_SPACE IPC channel FIFO is full + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for + * other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_IPC_MessageSend (ipc_ctrl_t * const p_api_ctrl, uint32_t message) +{ + ipc_instance_ctrl_t * p_ctrl = (ipc_instance_ctrl_t *) p_api_ctrl; + +#if IPC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_ipc_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Return an error if the FIFO is full */ + FSP_ERROR_RETURN(0 == p_ctrl->p_send_reg->STA_b.FULL, FSP_ERR_OVERFLOW); + + /* Write message to FIFO */ + p_ctrl->p_send_reg->TXD = message; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Triggers an interrupt with the specified event bit set over the configured IPC channel. + * + * Implements @ref ipc_api_t::eventGenerate. + * + * @retval FSP_SUCCESS Event request set successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for + * other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_IPC_EventGenerate (ipc_ctrl_t * const p_api_ctrl, ipc_generate_event_t event) +{ + ipc_instance_ctrl_t * p_ctrl = (ipc_instance_ctrl_t *) p_api_ctrl; + +#if IPC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_ipc_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Write to IRQ Request Set Register to generate event */ + p_ctrl->p_send_reg->SET = event; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * + * Implements @ref ipc_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION Pointer to IPC control block or callback is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for + * other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_IPC_CallbackSet (ipc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(ipc_callback_args_t *), + void * const p_context, + ipc_callback_args_t * const p_callback_memory) +{ + ipc_instance_ctrl_t * p_ctrl = (ipc_instance_ctrl_t *) p_api_ctrl; + +#if IPC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_ipc_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check for null parameters */ + FSP_ASSERT(NULL != p_callback); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if IPC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + ipc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(ipc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes the IPC driver. + * + * Implements @ref ipc_api_t::close. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to IPC control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_IPC_Close (ipc_ctrl_t * const p_api_ctrl) +{ + ipc_instance_ctrl_t * p_ctrl = (ipc_instance_ctrl_t *) p_api_ctrl; + +#if IPC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_ipc_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + if (p_ctrl->p_cfg->irq >= 0) + { + /* Disable interrupt if configured */ + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + } + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IPC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (IPC_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Verifies the control structure is not NULL and the module is open. This reduces code size when parameter checking is + * enabled. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * + * @retval FSP_SUCCESS No error detected. + * @retval FSP_ERR_ASSERTION NULL input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +static fsp_err_t r_ipc_common_parameter_checking (ipc_instance_ctrl_t const * const p_ctrl) +{ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(IPC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to IPC instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_ipc_call_callback (ipc_instance_ctrl_t * p_ctrl, ipc_event_t event) +{ + ipc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + ipc_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + + if (IPC_EVENT_MESSAGE_RECEIVED == event) + { + /* Pull message from FIFO */ + p_args->message = p_ctrl->p_recv_reg->RXD; + } + else + { + p_args->message = 0; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + ipc_prv_ns_callback p_callback = (ipc_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * IPC general ISR. + * + * @retval none + **********************************************************************************************************************/ +void ipc_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + ipc_instance_ctrl_t * p_ctrl = (ipc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t ipc_status_temp = p_ctrl->p_recv_reg->STA; + + /* Handle Received Messages */ + if (ipc_status_temp & R_IPC_IPC_CH_STA_RDY_Msk) + { + /* Ready bit is set which means FIFO isn't empty read message and call callback */ + r_ipc_call_callback(p_ctrl, IPC_EVENT_MESSAGE_RECEIVED); + } + + /* Check for other errors and generated events */ + ipc_event_t event = (ipc_event_t) (ipc_status_temp & IPC_PRV_EVENT_MASK); + + /* Handle events */ + if (event) + { + /* Call callback */ + r_ipc_call_callback(p_ctrl, event); + + /* Clear out set events */ + p_ctrl->p_recv_reg->CLR = (uint32_t) event; + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iwdt/r_iwdt.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iwdt/r_iwdt.c new file mode 100644 index 0000000000..baa816756d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_iwdt/r_iwdt.c @@ -0,0 +1,670 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_iwdt.h" +#include "bsp_api.h" +#include "bsp_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "IWDT" in ASCII. Used to determine if the control block is open. */ +#define IWDT_OPEN (0X49574454ULL) + +/* Lookup functions for IWDT settings. Using function like macro for stringification. */ +#define IWDT_PRV_OFS0_SETTING_GET(setting) (((uint32_t) BSP_CFG_OPTION_SETTING_OFS0 >> \ + IWDT_PRV_OFS0_ ## setting ## _BIT) & \ + IWDT_PRV_OFS0_ ## setting ## _MASK); +#define IWDT_PRV_IWDTCR_SETTING_GET(setting, \ + iwdtcr) (((iwdtcr >> IWDT_PRV_IWDTCR_ ## setting ## _BIT) & \ + IWDT_PRV_IWDTCR_ ## setting ## _MASK)); +#define IWDT_PRV_IWDTCR_SETTING_SET(setting, \ + value) ((value & IWDT_PRV_IWDTCR_ ## setting ## _MASK) << \ + IWDT_PRV_IWDTCR_ ## setting ## _BIT); + +/* OFS0 register settings. */ +#define IWDT_PRV_OFS0_AUTO_START_MASK (0x00000002U) +#define IWDT_PRV_OFS0_TIMEOUT_BIT (2U) +#define IWDT_PRV_OFS0_TIMEOUT_MASK (0x00000003U) +#define IWDT_PRV_OFS0_NMI_REQUEST_MASK (0x00001000U) +#define IWDT_PRV_OFS0_CLOCK_DIVISION_BIT (4U) +#define IWDT_PRV_OFS0_CLOCK_DIVISION_MASK (0x0000000FU) + +/* Status register settings. */ +#define IWDT_PRV_STATUS_START_BIT (14U) /*Bit 14 and Bit 15*/ + +/* Reset Control register settings. */ +#define IWDT_PRV_IWDTRCR_RESET_CONTROL_BIT (7U) + +/* Count Stop Count Control register settings. */ +#define IWDT_PRV_IWDTCSTPR_STOP_CONTROL_BIT (7U) + +/* Status register settings. */ +#define IWDT_PRV_IWDTSR_COUNTER_MASK (0x3FFFU) + +/* Control register settings. */ +#define IWDT_PRV_IWDTCR_TIMEOUT_BIT (0) // Bits 0-1 +#define IWDT_PRV_IWDTCR_TIMEOUT_MASK (0x3U) +#define IWDT_PRV_IWDTCR_CLOCK_DIVISION_BIT (4) // Bits 4-7 +#define IWDT_PRV_IWDTCR_CLOCK_DIVISION_MASK (0xFU) +#define IWDT_PRV_IWDTCR_WINDOW_END_BIT (8) // Bits 8-9 +#define IWDT_PRV_IWDTCR_WINDOW_END_MASK (0x3U) +#define IWDT_PRV_IWDTCR_WINDOW_START_BIT (12) // Bits 12-13 +#define IWDT_PRV_IWDTCR_WINDOW_START_MASK (0x3U) + +/* Refresh register values */ +#define IWDT_PRV_REFRESH_STEP_1 (0U) +#define IWDT_PRV_REFRESH_STEP_2 (0xFFU) + +/* Macros for start mode and NMI support. */ +#if (BSP_CFG_OPTION_SETTING_OFS0 & IWDT_PRV_OFS0_AUTO_START_MASK) + #if (BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE) + +/* Register start mode */ + #define IWDT_PRV_REGISTER_START_MODE (1U) + #define IWDT_PRV_NMI_SUPPORTED (IWDT_CFG_REGISTER_START_NMI_SUPPORTED) + #else + #define IWDT_PRV_REGISTER_START_MODE (0U) + #define IWDT_PRV_NMI_SUPPORTED (0U) + #endif + #define IWDT_PRV_AUTO_START_MODE (0U) +#else + +/* Auto start mode */ + #define IWDT_PRV_AUTO_START_MODE (1) + #define IWDT_PRV_REGISTER_START_MODE (0) + #if (BSP_CFG_OPTION_SETTING_OFS0 & IWDT_PRV_OFS0_NMI_REQUEST_MASK) + #define IWDT_PRV_NMI_SUPPORTED (0) + #else + #define IWDT_PRV_NMI_SUPPORTED (1) + #endif +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * iwdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile iwdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static uint32_t iwdt_clock_divider_get(wdt_clock_division_t division); + +#if IWDT_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t iwdt_parameter_checking(iwdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg); + +#endif + +#if IWDT_PRV_NMI_SUPPORTED +static void iwdt_nmi_internal_callback(bsp_grp_irq_t irq); +static void iwdt_nmi_initialize(iwdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Convert IWDT timeout value to an integer */ +static const uint16_t g_iwdt_timeout[] = +{ + 128U, ///< OFS0[3:0] value for WDT_TIMEOUT_128 + 512U, ///< OFS0[3:0] value for WDT_TIMEOUT_512 + 1024U, ///< OFS0[3:0] value for WDT_TIMEOUT_1024 + 2048U, ///< OFS0[3:0] value for WDT_TIMEOUT_2048 +}; + +/* Converts IWDT division enum to log base 2 of the division value, used to shift the PCLKB frequency. */ +static const uint8_t g_iwdt_division_lookup[] = +{ + 0U, // log base 2(1) = 0 + 2U, // log base 2(4) = 2 + 4U, // log base 2(16) = 4 + 5U, // log base 2(32) = 5 + 6U, // log base 2(64) = 6 + 8U, // log base 2(256) = 8 + 9U, // log base 2(512) = 9 + 11U, // log base 2(2048) = 11 + 13U, // log base 2(8192) = 13 +}; + +/* Global pointer to control structure for use by the NMI callback. */ +#if IWDT_PRV_NMI_SUPPORTED +static volatile iwdt_instance_ctrl_t * gp_iwdt_ctrl = NULL; +#endif + +/* Watchdog implementation of IWDT Driver. */ +const wdt_api_t g_wdt_on_iwdt = +{ + .open = R_IWDT_Open, + .refresh = R_IWDT_Refresh, + .statusGet = R_IWDT_StatusGet, + .statusClear = R_IWDT_StatusClear, + .counterGet = R_IWDT_CounterGet, + .timeoutGet = R_IWDT_TimeoutGet, + .callbackSet = R_IWDT_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup IWDT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Register the IWDT NMI callback. + * + * Example: + * @snippet r_iwdt_example.c R_IWDT_Open + * + * @retval FSP_SUCCESS IWDT successfully configured. + * @retval FSP_ERR_ASSERTION Null Pointer. + * @retval FSP_ERR_NOT_ENABLED An attempt to open the IWDT when the OFS0 register is not + * configured for auto-start mode. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. + **********************************************************************************************************************/ +fsp_err_t R_IWDT_Open (wdt_ctrl_t * const p_api_ctrl, wdt_cfg_t const * const p_cfg) +{ + iwdt_instance_ctrl_t * p_ctrl = (iwdt_instance_ctrl_t *) p_api_ctrl; + +#if IWDT_CFG_PARAM_CHECKING_ENABLE + + /* Check validity of the parameters */ + fsp_err_t err = iwdt_parameter_checking(p_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Configuration only valid when IWDT operating in register-start mode. */ +#if IWDT_PRV_REGISTER_START_MODE + + /* Register-start mode. */ + #if IWDT_PRV_NMI_SUPPORTED + if (p_cfg->reset_control == WDT_RESET_CONTROL_NMI) + { + /* Register callback with BSP NMI ISR. */ + iwdt_nmi_initialize(p_ctrl, p_cfg); + } + #endif + + /* Set the configuration registers in register start mode. */ + R_IWDT->IWDTRCR_b.RSTIRQS = p_cfg->reset_control == WDT_RESET_CONTROL_RESET; + + uint32_t iwdtcr = IWDT_PRV_IWDTCR_SETTING_SET(TIMEOUT, (uint16_t) p_cfg->timeout); + iwdtcr |= IWDT_PRV_IWDTCR_SETTING_SET(CLOCK_DIVISION, (uint16_t) p_cfg->clock_division); + iwdtcr |= IWDT_PRV_IWDTCR_SETTING_SET(WINDOW_START, (uint16_t) p_cfg->window_start); + iwdtcr |= IWDT_PRV_IWDTCR_SETTING_SET(WINDOW_END, (uint16_t) p_cfg->window_end); + + R_IWDT->IWDTCR = (uint16_t) iwdtcr; + R_IWDT->IWDTCSTPR_b.SLCSTP = p_cfg->stop_control == WDT_STOP_CONTROL_ENABLE; +#else + + /* Auto start mode. */ + /* Check for NMI output mode. */ + #if IWDT_PRV_NMI_SUPPORTED + + /* Register callback with BSP NMI ISR. */ + iwdt_nmi_initialize(p_ctrl, p_cfg); + #else + FSP_PARAMETER_NOT_USED(p_cfg); + #endif +#endif + + p_ctrl->wdt_open = IWDT_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Refresh the Independent Watchdog Timer. + * If the refresh fails due to being performed outside of the + * permitted refresh period the device will either reset or trigger an NMI ISR to run. + * + * Example: + * @snippet r_iwdt_example.c R_IWDT_Refresh + * + * @retval FSP_SUCCESS IWDT successfully refreshed. + * @retval FSP_ERR_ASSERTION One or more parameters are NULL pointers. + * @retval FSP_ERR_NOT_OPEN The driver has not been opened. Perform R_IWDT_Open() first. + **********************************************************************************************************************/ +fsp_err_t R_IWDT_Refresh (wdt_ctrl_t * const p_api_ctrl) +{ +#if (1 == IWDT_CFG_PARAM_CHECKING_ENABLE) + iwdt_instance_ctrl_t * p_ctrl = (iwdt_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN((IWDT_OPEN == p_ctrl->wdt_open), FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Described in hardware manual (see + * "Refresh Operation" in the IWDT section of the relevant hardware manual). */ + R_IWDT->IWDTRR = IWDT_PRV_REFRESH_STEP_1; + R_IWDT->IWDTRR = IWDT_PRV_REFRESH_STEP_2; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read the IWDT status flags. + * + * Indicates both status and error conditions. + * + * Example: + * @snippet r_iwdt_example.c R_IWDT_StatusGet + * + * @retval FSP_SUCCESS IWDT status successfully read. + * @retval FSP_ERR_ASSERTION Null pointer as a parameter. + * @retval FSP_ERR_NOT_OPEN The driver has not been opened. Perform R_IWDT_Open() first. + * @retval FSP_ERR_UNSUPPORTED This function is only valid if the IWDT generates an NMI when an error occurs. + * + * @note When the IWDT is configured to output a reset on underflow or refresh error reading the status and error flags + * serves no purpose as they will always indicate that no underflow has occurred and there is no refresh error. + * Reading the status and error flags is only valid when interrupt request output is enabled. + **********************************************************************************************************************/ +fsp_err_t R_IWDT_StatusGet (wdt_ctrl_t * const p_api_ctrl, wdt_status_t * const p_status) +{ +#if IWDT_PRV_NMI_SUPPORTED + #if (1 == IWDT_CFG_PARAM_CHECKING_ENABLE) + iwdt_instance_ctrl_t * p_ctrl = (iwdt_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_status != NULL); + FSP_ERROR_RETURN((IWDT_OPEN == p_ctrl->wdt_open), FSP_ERR_NOT_OPEN); + #else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + #endif + + *p_status = (wdt_status_t) (R_IWDT->IWDTSR >> (uint32_t) IWDT_PRV_STATUS_START_BIT); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_status); + + /* This function is only supported when the NMI is used. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Clear the IWDT status and error flags. Implements @ref wdt_api_t::statusClear. + * + * Example: + * @snippet r_iwdt_example.c R_IWDT_StatusClear + * + * @retval FSP_SUCCESS IWDT flag(s) successfully cleared. + * @retval FSP_ERR_ASSERTION Null pointer as a parameter. + * @retval FSP_ERR_NOT_OPEN The driver has not been opened. Perform R_IWDT_Open() first. + * @retval FSP_ERR_UNSUPPORTED This function is only valid if the IWDT generates an NMI when an error occurs. + * + * @note When the IWDT is configured to output a reset on underflow or refresh error reading the status and error flags + * serves no purpose as they will always indicate that no underflow has occurred and there is no refresh error. + * Reading the status and error flags is only valid when interrupt request output is enabled. + **********************************************************************************************************************/ +fsp_err_t R_IWDT_StatusClear (wdt_ctrl_t * const p_api_ctrl, const wdt_status_t status) +{ +#if IWDT_PRV_NMI_SUPPORTED + uint16_t value; + uint16_t read_value; + + #if (1 == IWDT_CFG_PARAM_CHECKING_ENABLE) + iwdt_instance_ctrl_t * p_ctrl = (iwdt_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN((IWDT_OPEN == p_ctrl->wdt_open), FSP_ERR_NOT_OPEN); + #else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + #endif + + /* Casts to uint16_t to ensure value is handled as unsigned. */ + value = (uint16_t) status; + + /* Write zero to clear flags */ + value = (uint16_t) ((uint16_t) (~value) << (uint32_t) IWDT_PRV_STATUS_START_BIT); + + /* Read back status flags until required flag(s) cleared. + * Flags cannot be cleared until after the clock cycle after they are set. + * Described in hardware manual (see + * "IWDT Status Register (IWDTSR)" description in the relevant hardware manual). + */ + do + { + R_IWDT->IWDTSR = value; + read_value = R_IWDT->IWDTSR; + read_value &= (uint16_t) ((uint16_t) status << (uint32_t) IWDT_PRV_STATUS_START_BIT); + } while (read_value); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(status); + + /* This function is only supported when the NMI is used. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Read the current count value of the IWDT. Implements @ref wdt_api_t::counterGet. + * + * Example: + * @snippet r_iwdt_example.c R_IWDT_CounterGet + * + * @retval FSP_SUCCESS IWDT current count successfully read. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN The driver has not been opened. Perform R_IWDT_Open() first. + **********************************************************************************************************************/ +fsp_err_t R_IWDT_CounterGet (wdt_ctrl_t * const p_api_ctrl, uint32_t * const p_count) +{ +#if (1 == IWDT_CFG_PARAM_CHECKING_ENABLE) + iwdt_instance_ctrl_t * p_ctrl = (iwdt_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_count != NULL); + FSP_ERROR_RETURN((IWDT_OPEN == p_ctrl->wdt_open), FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + (*p_count) = (uint32_t) R_IWDT->IWDTSR & (uint32_t) IWDT_PRV_IWDTSR_COUNTER_MASK; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read timeout information for the watchdog timer. Implements @ref wdt_api_t::timeoutGet. + * + * @retval FSP_SUCCESS IWDT timeout information retrieved successfully. + * @retval FSP_ERR_ASSERTION One or more parameters are NULL pointers. + * @retval FSP_ERR_NOT_OPEN The driver has not been opened. Perform R_IWDT_Open() first. + **********************************************************************************************************************/ +fsp_err_t R_IWDT_TimeoutGet (wdt_ctrl_t * const p_api_ctrl, wdt_timeout_values_t * const p_timeout) +{ +#if (1 == IWDT_CFG_PARAM_CHECKING_ENABLE) + iwdt_instance_ctrl_t * p_ctrl = (iwdt_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_timeout != NULL); + FSP_ERROR_RETURN((IWDT_OPEN == p_ctrl->wdt_open), FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + uint32_t frequency; + uint32_t shift; + uint32_t timeout = 0; + wdt_clock_division_t clock_division; + +#if IWDT_PRV_REGISTER_START_MODE + + /* Read the configuration of the watchdog */ + uint32_t iwdtcr = R_IWDT->IWDTCR; + clock_division = (wdt_clock_division_t) IWDT_PRV_IWDTCR_SETTING_GET(CLOCK_DIVISION, iwdtcr); + timeout = IWDT_PRV_IWDTCR_SETTING_GET(TIMEOUT, iwdtcr); +#else /* Auto start mode */ + clock_division = (wdt_clock_division_t) IWDT_PRV_OFS0_SETTING_GET(CLOCK_DIVISION); + timeout = IWDT_PRV_OFS0_SETTING_GET(TIMEOUT); +#endif + + p_timeout->timeout_clocks = (uint32_t) g_iwdt_timeout[timeout]; + + /* Get the frequency of the clock supplying the watchdog */ + frequency = (uint32_t) BSP_FEATURE_IWDT_CLOCK_FREQUENCY; + + shift = iwdt_clock_divider_get(clock_division); + + p_timeout->clock_frequency_hz = frequency >> shift; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements wdt_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_IWDT_CallbackSet (wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void * const p_context, + wdt_callback_args_t * const p_callback_memory) +{ + iwdt_instance_ctrl_t * p_instance_ctrl = (iwdt_instance_ctrl_t *) p_ctrl; + +#if IWDT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(IWDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if IWDT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + wdt_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(wdt_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IWDT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Internal NMI ISR callback which calls the user provided callback passing the context provided by the user. + * + * @param[in] irq IRQ which has triggered the NMI interrupt. + * + **********************************************************************************************************************/ +#if IWDT_PRV_NMI_SUPPORTED +static void iwdt_nmi_internal_callback (bsp_grp_irq_t irq) +{ + FSP_PARAMETER_NOT_USED(irq); + + wdt_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + wdt_callback_args_t * p_args = gp_iwdt_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = gp_iwdt_ctrl->p_context; + + #if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(gp_iwdt_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + gp_iwdt_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + iwdt_prv_ns_callback p_callback = (iwdt_prv_ns_callback) (gp_iwdt_ctrl->p_callback); + p_callback(p_args); + } + + #else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + gp_iwdt_ctrl->p_callback(p_args); + #endif + if (NULL != gp_iwdt_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *gp_iwdt_ctrl->p_callback_memory = args; + } +} + +#endif + +/*******************************************************************************************************************//** + * Internal function to return timeout in terms of watchdog clocks from provided timeout setting. + * + * @param[in] division Watchdog division setting. + * + **********************************************************************************************************************/ +static uint32_t iwdt_clock_divider_get (wdt_clock_division_t division) +{ + uint32_t shift; + + if (WDT_CLOCK_DIVISION_128 == division) + { + shift = 7U; /* log base 2(128) = 7 */ + } + else + { + shift = g_iwdt_division_lookup[division]; + } + + return shift; +} + +/*******************************************************************************************************************//** + * Initialize the NMI. + * + * @param[in] p_instance_ctrl Pointer to instance control structure + * @param[in] p_cfg Pointer to configuration structure + **********************************************************************************************************************/ +#if IWDT_PRV_NMI_SUPPORTED +static void iwdt_nmi_initialize (iwdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg) +{ + /* Initialize global pointer to WDT for NMI callback use. */ + gp_iwdt_ctrl = p_instance_ctrl; + + /* NMI output mode. */ + R_BSP_GroupIrqWrite(BSP_GRP_IRQ_IWDT_ERROR, iwdt_nmi_internal_callback); + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + + /* Enable the IWDT underflow/refresh error interrupt to generate an NMI. NMIER bits cannot be cleared after reset, + * so no need to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_IWDTEN_Msk; +} + +#endif + +/*******************************************************************************************************************//** + * Parameter checking function for IWDT Open + * + * @param[in] p_instance_ctrl Pointer to instance control structure + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS IWDT successfully configured. + * @retval FSP_ERR_NOT_ENABLED An attempt to open the IWDT when the OFS0 register is not + * configured for auto-start mode. + * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. + **********************************************************************************************************************/ +#if IWDT_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t iwdt_parameter_checking (iwdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg) +{ + /* Check that control and config structure pointers are valid. */ + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IWDT_OPEN != p_instance_ctrl->wdt_open, FSP_ERR_ALREADY_OPEN); + + /* Ensure this module is in the same security state as the NMI */ + #if defined(BSP_TZ_NONSECURE_BUILD) && BSP_TZ_NONSECURE_BUILD + FSP_ERROR_RETURN(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk, FSP_ERR_INVALID_STATE); + #elif defined(BSP_TZ_SECURE_BUILD) && BSP_TZ_SECURE_BUILD + FSP_ERROR_RETURN(!(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk), FSP_ERR_INVALID_STATE); + #endif + + /* Check timeout parameter is supported by IWDT. */ + + /* Enum checking is done here because some enums in wdt_timeout_t are not supported by the IWDT peripheral (they are + * included for other implementations of the watchdog interface). */ + FSP_ASSERT((p_cfg->timeout == WDT_TIMEOUT_128) || (p_cfg->timeout == WDT_TIMEOUT_512) || \ + (p_cfg->timeout == WDT_TIMEOUT_1024) || (p_cfg->timeout == WDT_TIMEOUT_2048)); + + #if IWDT_PRV_REGISTER_START_MODE + + /* Register-start mode. */ + + #if IWDT_PRV_NMI_SUPPORTED + + /* Register callback with BSP NMI ISR. */ + if (p_cfg->reset_control == WDT_RESET_CONTROL_NMI) + { + FSP_ASSERT(NULL != p_cfg->p_callback); + } + else + { + FSP_ASSERT(NULL == p_cfg->p_callback); + } + + #else + FSP_ASSERT(p_cfg->reset_control == WDT_RESET_CONTROL_RESET); + #endif + #else + + /* Auto start mode. */ + + /* Check the IWDT is enabled in auto start mode. */ + FSP_ERROR_RETURN((0U != (uint32_t) IWDT_PRV_AUTO_START_MODE), FSP_ERR_NOT_ENABLED); + + #if IWDT_PRV_NMI_SUPPORTED + + /* NMI output mode. */ + FSP_ASSERT(NULL != p_cfg->p_callback); + #else + FSP_ASSERT(NULL == p_cfg->p_callback); + #endif + #endif + + return FSP_SUCCESS; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_jpeg/r_jpeg.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_jpeg/r_jpeg.c new file mode 100644 index 0000000000..82ad2db63c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_jpeg/r_jpeg.c @@ -0,0 +1,1638 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_jpeg_decode.c + * Description : JPEG device low level functions used to implement JPEG_DECODE interface driver. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_jpeg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "JPEG" in ASCII, used to determine if the module is open */ +#define JPEG_OPEN (0x4A504547) +#define JPEG_CLOSED (0x00000000) + +#define JPEG_PRV_ALIGNMENT_8 (0x07U) +#define JPEG_PRV_ALIGNMENT_16 (0x0FU) +#define JPEG_PRV_ALIGNMENT_32 (0x1FU) + +#define JPEG_PRV_BUFFER_MAX_SIZE (0xfff8U) + +/* Table 0 is used for Luminance (Y) and Table 1 is used for Chrominance (Cb, Cr) */ +#define JPEG_PRV_QUANTIZATION_TABLE_SETTING (0x14U) + +/* AC and DC table for Luminance and Chrominance */ +#define JPEG_PRV_HUFFMAN_TABLE_SETTING (0x3cU) + +/* Y'CbCr 4:2:2 settings */ +#define JPEG_PRV_YCBCR_BYTES_PER_PIXEL (2U) +#define JPEG_PRV_YCBCR422 (0x1U) + +/* Huffman and Quantization table address/dimensions */ +#define JPEG_PRV_QUANT_TABLE_SIZE (64) +#define JPEG_PRV_HUFFM_DC_TABLE_SIZE (28) +#define JPEG_PRV_HUFFM_AC_TABLE_SIZE (178) + +/* End-of-Image (EOI) marker */ +#define JPEG_PRV_EOI_B0 (0xFFU) +#define JPEG_PRV_EOI_B1 (0xD9U) + +#define JPEG_PRV_OPERATION_ENCODE (0x00U) +#define JPEG_PRV_OPERATION_DECODE (0x08U) + +/*********************************************************************************************************************** + * Constant data + **********************************************************************************************************************/ +#if JPEG_CFG_ENCODE_ENABLE +static const uint8_t g_initial_data[6] = +{ + 0xFFU, + 0xD8U, + 0xFFU, + 0xDBU, + 0x00U, + 0x84U +}; +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +#if (1 == JPEG_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_jpeg_bufferset_param_check(jpeg_instance_ctrl_t const * const p_ctrl, + void * p_buffer, + uint32_t buffer_size); + +#endif + +#if JPEG_CFG_DECODE_ENABLE + +static void r_jpeg_decode_init(jpeg_instance_ctrl_t * p_ctrl); +static void r_jpeg_decode_image_size_get(uint16_t * p_horizontal, uint16_t * p_vertical); +static fsp_err_t r_jpeg_decode_line_number_get(jpeg_instance_ctrl_t * const p_ctrl, uint16_t * p_lines_to_decode); +static void r_jpeg_decode_output_start(jpeg_instance_ctrl_t * const p_ctrl, const uint16_t lines_to_decode); + +__STATIC_INLINE void r_jpeg_status_change(jpeg_instance_ctrl_t * const p_ctrl, uint8_t clear, uint8_t set); + +#endif + +#if JPEG_CFG_ENCODE_ENABLE + + #if JPEG_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_jpeg_encode_image_size_param_check(uint16_t horizontal, uint16_t vertical, uint16_t stride); +static fsp_err_t r_jpeg_encode_init_param_check(jpeg_cfg_t const * const p_cfg); + + #endif + +static void r_jpeg_encode_init(jpeg_instance_ctrl_t * p_ctrl); +static void r_jpeg_data_correction(jpeg_instance_ctrl_t * p_ctrl, uint8_t final_output); +static void r_jpeg_encode_image_size_set(uint16_t horizontal, uint16_t vertical, uint16_t stride); + +#endif + +#if JPEG_CFG_DECODE_ENABLE && JPEG_CFG_ENCODE_ENABLE + +static void r_jpeg_mode_init(jpeg_instance_ctrl_t * p_ctrl, jpeg_mode_t mode); + +#endif + +static void r_jpeg_mode_deinit(jpeg_mode_t mode); + +void jpeg_jdti_isr(); +void jpeg_jedi_isr(); + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* Implementation of General JPEG Codec Driver */ +const jpeg_api_t g_jpeg_on_jpeg = +{ + .open = R_JPEG_Open, + .outputBufferSet = R_JPEG_OutputBufferSet, + .inputBufferSet = R_JPEG_InputBufferSet, +#if JPEG_CFG_DECODE_ENABLE + .linesDecodedGet = R_JPEG_DecodeLinesDecodedGet, + .horizontalStrideSet = R_JPEG_DecodeHorizontalStrideSet, + .imageSubsampleSet = R_JPEG_DecodeImageSubsampleSet, + .imageSizeGet = R_JPEG_DecodeImageSizeGet, + .pixelFormatGet = R_JPEG_DecodePixelFormatGet, +#endif +#if JPEG_CFG_ENCODE_ENABLE + .imageSizeSet = R_JPEG_EncodeImageSizeSet, +#endif +#if JPEG_CFG_ENCODE_ENABLE && JPEG_CFG_DECODE_ENABLE + .modeSet = R_JPEG_ModeSet, +#endif + .statusGet = R_JPEG_StatusGet, + .close = R_JPEG_Close, +}; + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup JPEG + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize the JPEG Codec module. + * @note This function configures the JPEG Codec for operation and sets up the registers for data format and + * pixel format based on user-supplied configuration parameters. Interrupts are enabled to support callbacks. + * + * @retval FSP_SUCCESS JPEG Codec module is properly configured and is ready to take input data. + * @retval FSP_ERR_ALREADY_OPEN JPEG Codec is already open. + * @retval FSP_ERR_ASSERTION Pointer to the control block or the configuration structure is NULL. + * @retval FSP_ERR_IRQ_BSP_DISABLED JEDI interrupt does not have an IRQ number. + * @retval FSP_ERR_INVALID_ARGUMENT (Encode only) Quality factor, horizontal resolution and/or vertical resolution are invalid. + * @retval FSP_ERR_INVALID_ALIGNMENT (Encode only) The horizontal resolution (at 16bpp) is not divisible by 8 bytes. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_Open (jpeg_ctrl_t * const p_api_ctrl, jpeg_cfg_t const * const p_cfg) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + +#if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_cfg->jdti_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + #if JPEG_CFG_DECODE_ENABLE + FSP_ERROR_RETURN(p_cfg->jedi_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + #endif + + FSP_ERROR_RETURN((JPEG_OPEN != p_ctrl->open), FSP_ERR_ALREADY_OPEN); + + #if JPEG_CFG_ENCODE_ENABLE + #if JPEG_CFG_DECODE_ENABLE + if (p_cfg->default_mode == JPEG_MODE_ENCODE) + #endif + { + fsp_err_t err = r_jpeg_encode_init_param_check(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif +#endif + + /* Provide clock to the JPEG module */ + R_BSP_MODULE_START(FSP_IP_JPEG, 0U); + + /* Set pointer to control block in configuration */ + p_ctrl->p_cfg = p_cfg; + +#if JPEG_CFG_DECODE_ENABLE && JPEG_CFG_ENCODE_ENABLE + + /* Initialize based on the default mode */ + r_jpeg_mode_init(p_ctrl, p_cfg->default_mode); +#elif JPEG_CFG_DECODE_ENABLE + + /* Set mode to decode */ + p_ctrl->mode = JPEG_MODE_DECODE; + + r_jpeg_decode_init(p_ctrl); +#else + + /* Set mode to encode */ + p_ctrl->mode = JPEG_MODE_ENCODE; + + r_jpeg_encode_init(p_ctrl); +#endif + + /* Enable interrupts in NVIC */ + R_BSP_IrqCfgEnable(p_cfg->jdti_irq, p_cfg->jdti_ipl, p_ctrl); + +#if JPEG_CFG_DECODE_ENABLE + R_BSP_IrqCfgEnable(p_cfg->jedi_irq, p_cfg->jedi_ipl, p_ctrl); +#endif + + /* Set the status to idle */ + p_ctrl->status = JPEG_STATUS_IDLE; + + /* Set driver status to open */ + p_ctrl->open = JPEG_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Assign a buffer to the JPEG Codec for storing output data. + * @note In Decode mode, the number of image lines to be decoded depends on the size of the buffer and the horizontal stride + * settings. Once the output buffer size is known, the horizontal stride value is known, and the input + * pixel format is known (the input pixel format is obtained by the JPEG decoder from the JPEG headers), + * the driver automatically computes the number of lines that can be decoded into the output buffer. + * After these lines are decoded, the JPEG engine pauses and a callback function is triggered, so the application + * is able to provide the next buffer for the JPEG module to resume the operation. + * + * The JPEG decoding operation automatically starts after both the input buffer and the output buffer are set + * and the output buffer is big enough to hold at least eight lines of decoded image data. + * + * @retval FSP_SUCCESS The output buffer is properly assigned to JPEG codec device. + * @retval FSP_ERR_ASSERTION Pointer to the control block or output_buffer + * is NULL or output_buffer_size is 0. + * @retval FSP_ERR_INVALID_ALIGNMENT Buffer starting address is not 8-byte aligned. + * @retval FSP_ERR_NOT_OPEN JPEG not opened. + * @retval FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE The number of horizontal pixels exceeds horizontal memory stride. + * @retval FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH Invalid buffer size. + * @retval FSP_ERR_IN_USE The output buffer cannot be changed during codec operation. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_OutputBufferSet (jpeg_ctrl_t * p_api_ctrl, void * p_output_buffer, uint32_t output_buffer_size) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if JPEG_CFG_PARAM_CHECKING_ENABLE + err = r_jpeg_bufferset_param_check(p_ctrl, p_output_buffer, output_buffer_size); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN((0 != output_buffer_size) || (p_ctrl->mode == JPEG_MODE_ENCODE), + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH); +#endif + +#if JPEG_CFG_ENCODE_ENABLE + #if JPEG_CFG_DECODE_ENABLE + if (p_ctrl->mode == JPEG_MODE_ENCODE) + #endif + { + /* These parameters are only used during decode operations */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(output_buffer_size); + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + + /* Output buffer cannot be changed during codec operation */ + FSP_ERROR_RETURN(!((uint32_t) (JPEG_STATUS_RUNNING | JPEG_STATUS_INPUT_PAUSE) & (uint32_t) p_ctrl->status), + FSP_ERR_IN_USE); + #endif + + /* Set the encoding destination address. */ + R_JPEG->JIFEDA = (uint32_t) p_output_buffer; + } +#endif +#if JPEG_CFG_DECODE_ENABLE + #if JPEG_CFG_ENCODE_ENABLE + else + #endif + { + /* Return error code if any errors were detected */ + if ((uint32_t) (JPEG_STATUS_ERROR) &p_ctrl->status) + { + return p_ctrl->error_code; + } + + /* Set the decoding destination address */ + R_JPEG->JIFDDA = (uint32_t) p_output_buffer; + + /* Record the size of the output buffer */ + p_ctrl->output_buffer_size = output_buffer_size; + + /* If the image size is not ready yet, the driver does not know the input pixel format. + * Without that information, the driver is unable to compute the number of lines of image + * to decode. In this case, the driver would record the output buffer size. Once all the + * information is ready, the driver would attempt to start the decoding process. */ + if (((uint32_t) JPEG_STATUS_IMAGE_SIZE_READY & (uint32_t) p_ctrl->status) && (p_ctrl->horizontal_stride_bytes)) + { + uint16_t lines_to_decode = 0; + + /* Determine number of lines to decode */ + err = r_jpeg_decode_line_number_get(p_ctrl, &lines_to_decode); + if (FSP_SUCCESS == err) + { + /* If the driver status is IMAGE_SIZE_READY with no other flags, + * that means the driver just received IMAGE_SIZE. It has not started + * the decoding process yet */ + if (JPEG_STATUS_IMAGE_SIZE_READY == p_ctrl->status) + { + /* If Input buffer is set, output buffer is set, and horizontal stride is set, the driver is + * able to determine the number of lines to decode, and start the decoding operation */ + if (R_JPEG->JIFDSA) + { + r_jpeg_decode_output_start(p_ctrl, lines_to_decode); + } + } + /* If the current status is OUTPUT_PAUSE, the driver + * needs to resume the operation */ + else if ((uint32_t) (JPEG_STATUS_OUTPUT_PAUSE) &(uint32_t) p_ctrl->status) + { + /* Set status to running */ + r_jpeg_status_change(p_ctrl, JPEG_STATUS_OUTPUT_PAUSE, JPEG_STATUS_RUNNING); + + /* Set number of lines */ + R_JPEG->JIFDDLC = lines_to_decode; + + /* Resume the JPEG core (set DOUTRINI and DOUTRCMD) */ + R_JPEG->JIFDCNT |= (R_JPEG_JIFDCNT_DOUTRINI_Msk | R_JPEG_JIFDCNT_DOUTRCMD_Msk); + } + else + { + /* Do nothing */ + } + } + } + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Assign an input data buffer to the JPEG codec for processing. + * @note After the amount of data is processed, the JPEG driver triggers a callback function with the flag + * JPEG_PRV_OPERATION_INPUT_PAUSE set. + * The application supplies the next chunk of data to the driver so processing can resume. + * + * @note The JPEG decoding operation automatically starts after both the input buffer and the output buffer are set, + * and the output buffer is big enough to hold at least one line of decoded image data. + * + * If zero is provided for the decode data buffer size the JPEG Codec will never pause for more input data and will + * continue to read until either an image has been fully decoded or an error condition occurs. + * + * @note When encoding images the minimum data buffer size is 8 lines by 16 Y'CbCr 4:2:2 pixels (256 bytes). This + * corresponds to one minimum coded unit (MCU) of the resulting JPEG output. + * + * @retval FSP_SUCCESS The input data buffer is properly assigned to JPEG Codec device. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL, or the pointer to the input_buffer is + * NULL, or the input_buffer_size is 0. + * @retval FSP_ERR_INVALID_ALIGNMENT Buffer starting address is not 8-byte aligned. + * @retval FSP_ERR_NOT_OPEN JPEG not opened. + * @retval FSP_ERR_IN_USE The input buffer cannot be changed while the codec is running. + * @retval FSP_ERR_INVALID_CALL In encode mode the output buffer must be set first. + * @retval FSP_ERR_JPEG_IMAGE_SIZE_ERROR The buffer size is smaller than the minimum coded unit (MCU). + **********************************************************************************************************************/ +fsp_err_t R_JPEG_InputBufferSet (jpeg_ctrl_t * const p_api_ctrl, void * p_data_buffer, uint32_t data_buffer_size) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if JPEG_CFG_PARAM_CHECKING_ENABLE + err = r_jpeg_bufferset_param_check(p_ctrl, p_data_buffer, data_buffer_size); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + +#if JPEG_CFG_ENCODE_ENABLE + #if JPEG_CFG_DECODE_ENABLE + if (p_ctrl->mode == JPEG_MODE_ENCODE) + #endif + { + /* Calculate the number of lines to encode */ + p_ctrl->lines_to_encode = (uint16_t) (data_buffer_size / p_ctrl->horizontal_stride_bytes); + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + + /* The JPEG Codec can process a minimum of 8 lines by 16 YCbCr422 pixels (8x16x2 = 256) */ + FSP_ERROR_RETURN((!(data_buffer_size < 256U)), FSP_ERR_JPEG_IMAGE_SIZE_ERROR); + + /* The JPEG Codec requires lines to be 8-byte aligned */ + FSP_ERROR_RETURN(!((uint32_t) p_ctrl->lines_to_encode & JPEG_PRV_ALIGNMENT_8), FSP_ERR_INVALID_ALIGNMENT); + + /* Check if output image buffer is set or not */ + FSP_ERROR_RETURN(0U != R_JPEG->JIFEDA, FSP_ERR_INVALID_CALL); + #endif + + /* Configure the input buffer address. */ + R_JPEG->JIFESA = (uint32_t) p_data_buffer; + + /* Set the line count */ + R_JPEG->JIFESLC = p_ctrl->lines_to_encode; + + /* Get the status */ + uint32_t status = p_ctrl->status; + + /* If JPEG was just opened or has completed one image, start encoding the new image */ + if (JPEG_STATUS_IDLE & status) + { + /* Set the status to running */ + p_ctrl->status = JPEG_STATUS_RUNNING; + + /* Clear lines encoded */ + p_ctrl->total_lines_encoded = 0U; + + /* Start the encoder */ + + /* If the vertical resolution is greater than or equal to the number of lines to encode the encoder does not + * need to stop. In this case input count mode does not need to be enabled. */ + if (p_ctrl->lines_to_encode < p_ctrl->vertical_resolution) + { + /* Enable count mode */ + R_JPEG->JIFECNT_b.DINLC = 1; + } + else + { + /* Disable count mode */ + R_JPEG->JIFECNT_b.DINLC = 0; + } + + R_JPEG->JCCMD = R_JPEG_JCCMD_JSRT_Msk; + } + /* Codec is paused for next chunk of image */ + else if ((uint32_t) JPEG_STATUS_INPUT_PAUSE & status) + { + /* Set the status to running */ + p_ctrl->status = JPEG_STATUS_RUNNING; + + /* Resume count mode + * (See "Compression process" in the JPEG section of the relevant hardware manual). */ + R_JPEG->JIFECNT_b.DINRCMD = 1; + } + else + { + /* Codec is running, so return error */ + err = FSP_ERR_IN_USE; + } + } +#endif +#if JPEG_CFG_DECODE_ENABLE + #if JPEG_CFG_ENCODE_ENABLE + else + #endif + { + /* Return error code if any errors were detected */ + if ((uint32_t) JPEG_STATUS_ERROR & p_ctrl->status) + { + return p_ctrl->error_code; + } + + /* Configure the input buffer address */ + R_JPEG->JIFDSA = (uint32_t) p_data_buffer; + + /* If the system is idle, start the JPEG engine. This allows the + * system to obtain image information (image size and input pixel format). This + * information is needed to drive the decode process later on */ + if (JPEG_STATUS_IDLE & p_ctrl->status) + { + uint32_t jifdcnt = R_JPEG->JIFDCNT; + + /* Based on buffer size, detect the in count mode setting. + * The driver is able to read input data in chunks. However the size of each chunk + * is limited to JPEG_PRV_BUFFER_MAX_SIZE. Therefore, if the input data size is larger than + * JPEG_PRV_BUFFER_MAX_SIZE, the driver assumes the entire input data is present, and can be decoded + * without additional input data. Otherwise, the driver enables input stream feature. + * This works even if the entire input size is smaller than JPEG_PRV_BUFFER_MAX_SIZE + */ + if ((0 != data_buffer_size) && (data_buffer_size <= JPEG_PRV_BUFFER_MAX_SIZE)) + { + /* Enable input data count interrupt */ + R_JPEG->JINTE1 |= R_JPEG_JINTE1_JINEN_Msk; + + /* Start reading input data */ + jifdcnt |= (R_JPEG_JIFDCNT_JINC_Msk | R_JPEG_JIFDCNT_JINRINI_Msk); + + /* Set number of input bytes to read */ + R_JPEG->JIFDSDC = data_buffer_size; // Number of data is transfer when count-mode is on (in 8-bytes uint); + } + else + { + /* Start reading input data (JINRINI not needed when not in count mode) */ + jifdcnt &= (uint32_t) ~(R_JPEG_JIFDCNT_JINC_Msk); + } + + R_JPEG->JIFDCNT = jifdcnt; + + /* Set the internal status */ + p_ctrl->status = JPEG_STATUS_HEADER_PROCESSING; + + /* Start the core */ + R_JPEG->JCCMD = R_JPEG_JCCMD_JSRT_Msk; + } + /* If the JPEG driver is paused for input data, the driver needs to resume the + * operation */ + else if ((uint32_t) JPEG_STATUS_INPUT_PAUSE & p_ctrl->status) + { + /* Set status to running */ + r_jpeg_status_change(p_ctrl, JPEG_STATUS_INPUT_PAUSE, JPEG_STATUS_RUNNING); + + /* Set number of transfers (in 8-byte increments) */ + R_JPEG->JIFDSDC = data_buffer_size; + + /* Resume the JPEG core (set JINRINI and JINRCMD) */ + R_JPEG->JIFDCNT |= (R_JPEG_JIFDCNT_JINRINI_Msk | R_JPEG_JIFDCNT_JINRCMD_Msk); + } + else + { + /* Do nothing */ + } + } +#endif + + return err; +} + +#if JPEG_CFG_DECODE_ENABLE + +/*******************************************************************************************************************//** + * Returns the number of lines decoded into the output buffer. + * @note Use this function to retrieve the number of image lines written to the output buffer after a partial decode + * operation. Combined with the horizontal stride settings and the output pixel format the application + * can compute the amount of data to read from the output buffer. + * + * @retval FSP_SUCCESS Line count successfully returned. + * @retval FSP_ERR_ASSERTION Pointer to the control block or p_lines is NULL. + * @retval FSP_ERR_NOT_OPEN JPEG not opened. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_DecodeLinesDecodedGet (jpeg_ctrl_t * p_api_ctrl, uint32_t * p_lines) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_lines); + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + #endif + + /* Return error code if any errors were detected */ + if ((uint32_t) (JPEG_STATUS_ERROR) &(uint32_t) p_ctrl->status) + { + return p_ctrl->error_code; + } + + /* Get decoded line count */ + uint32_t lines = R_JPEG->JIFDDLC & UINT16_MAX; + + /* In 4:2:0 subsampling mode the decoded line count is doubled */ + if (((uint32_t) JPEG_COLOR_SPACE_YCBCR420 | R_JPEG_JCMOD_DSP_Msk) == R_JPEG->JCMOD) + { + lines *= 2U; + } + + *p_lines = lines; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configure horizontal and vertical subsampling. + * @note This function can be used to scale the output of decoded image data. + * + * @retval FSP_SUCCESS Horizontal subsample value is properly configured. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. + * @retval FSP_ERR_NOT_OPEN JPEG not opened. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_DecodeImageSubsampleSet (jpeg_ctrl_t * const p_api_ctrl, + jpeg_decode_subsample_t horizontal_subsample, + jpeg_decode_subsample_t vertical_subsample) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + #endif + + /* Return error code if any errors were detected */ + if ((uint32_t) JPEG_STATUS_ERROR & p_ctrl->status) + { + return p_ctrl->error_code; + } + + /* Update horizontal sub-sample setting */ + p_ctrl->horizontal_subsample = horizontal_subsample; + + /* Set vertical and horizontal rescaling factors */ + R_JPEG->JIFDCNT_b.VINTER = vertical_subsample; + R_JPEG->JIFDCNT_b.HINTER = horizontal_subsample; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configure horizontal stride setting for decode operations. + * @note If the image size is known prior to the open call and/or the output buffer stride is constant, pass the + * horizontal stride value in the jpeg_cfg_t structure. Otherwise, after the image size becomes available use + * this function to set the output buffer horizontal stride value. + * + * @retval FSP_SUCCESS Horizontal stride value is properly configured. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. + * @retval FSP_ERR_INVALID_ALIGNMENT Horizontal stride is zero or is not 8-byte aligned. + * @retval FSP_ERR_NOT_OPEN JPEG not opened. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_DecodeHorizontalStrideSet (jpeg_ctrl_t * p_api_ctrl, uint32_t horizontal_stride) +{ + fsp_err_t err = FSP_SUCCESS; + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN((0U != horizontal_stride), FSP_ERR_INVALID_ALIGNMENT); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + #endif + + /* Return error code if any errors were detected */ + if ((uint32_t) JPEG_STATUS_ERROR & p_ctrl->status) + { + return p_ctrl->error_code; + } + + if (JPEG_DECODE_PIXEL_FORMAT_ARGB8888 == R_JPEG->JIFDCNT_b.OPF) + { + horizontal_stride *= 4U; + } + else + { + horizontal_stride *= 2U; + } + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(!(horizontal_stride & JPEG_PRV_ALIGNMENT_8), FSP_ERR_INVALID_ALIGNMENT); + #endif + + /* Record the horizontal stride value in the control block */ + p_ctrl->horizontal_stride_bytes = horizontal_stride; + + /* Set the horizontal stride */ + R_JPEG->JIFDDOFST = horizontal_stride; + + return err; +} + +/*******************************************************************************************************************//** + * Obtain the size of an image being decoded. + * + * @retval FSP_SUCCESS The image size is available and the horizontal and vertical values are + * stored in the memory pointed to by p_horizontal_size and p_vertical_size. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL and/or size is not ready. + * @retval FSP_ERR_NOT_OPEN JPEG is not opened. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_DecodeImageSizeGet (jpeg_ctrl_t * p_api_ctrl, uint16_t * p_horizontal_size, uint16_t * p_vertical_size) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_horizontal_size); + FSP_ASSERT(NULL != p_vertical_size); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Get the image horizontal and vertical size */ + r_jpeg_decode_image_size_get(p_horizontal_size, p_vertical_size); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get the color format of the JPEG being decoded. + * + * @retval FSP_SUCCESS The color format was successfully retrieved. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. + * @retval FSP_ERR_NOT_OPEN JPEG is not opened. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_DecodePixelFormatGet (jpeg_ctrl_t * p_api_ctrl, jpeg_color_space_t * p_color_space) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_color_space); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Return color format as reported by the JPEG Codec */ + *p_color_space = (jpeg_color_space_t) (R_JPEG->JCMOD_b.REDU); + + return FSP_SUCCESS; +} + +#endif + +#if JPEG_CFG_ENCODE_ENABLE + +/*******************************************************************************************************************//** + * Set the image dimensions for an encode operation. + * @note Image dimensions must be set before setting the input buffer. + * + * @retval FSP_SUCCESS Image size was successfully written to the JPEG Codec. + * @retval FSP_ERR_ASSERTION Pointer to the control block or p_image_size is NULL. + * @retval FSP_ERR_INVALID_ALIGNMENT Horizontal stride is not 8-byte aligned. + * @retval FSP_ERR_INVALID_ARGUMENT Horizontal or vertical resolution is invalid or zero. + * @retval FSP_ERR_NOT_OPEN JPEG not opened. + * @retval FSP_ERR_IN_USE Image parameters cannot be changed while the codec is running. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_EncodeImageSizeSet (jpeg_ctrl_t * const p_api_ctrl, jpeg_encode_image_size_t * p_image_size) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + + #if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_image_size); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + + /* Do not change the JPEG Codec image setting while an operation is in progress */ + FSP_ERROR_RETURN(!((uint32_t) (JPEG_STATUS_RUNNING | JPEG_STATUS_INPUT_PAUSE) & (uint32_t) p_ctrl->status), + FSP_ERR_IN_USE); + + fsp_err_t err = r_jpeg_encode_image_size_param_check(p_image_size->horizontal_resolution, + p_image_size->vertical_resolution, + p_image_size->horizontal_stride_pixels); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + /* Record the horizontal stride and vertical size value in the control block */ + p_ctrl->horizontal_stride_bytes = p_image_size->horizontal_stride_pixels * JPEG_PRV_YCBCR_BYTES_PER_PIXEL; + p_ctrl->vertical_resolution = p_image_size->vertical_resolution; + + /* Set the image horizontal and vertical size.*/ + r_jpeg_encode_image_size_set(p_image_size->horizontal_resolution, + p_image_size->vertical_resolution, + (uint16_t) p_ctrl->horizontal_stride_bytes); + + return FSP_SUCCESS; +} + + #if JPEG_CFG_DECODE_ENABLE + +/*******************************************************************************************************************//** + * Switch between encode and decode mode (or vice-versa). + * @note The codec must not be idle in order to switch modes. + * + * @retval FSP_SUCCESS Mode changed successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_IN_USE JPEG Codec is currently in use. + * @retval FSP_ERR_INVALID_ARGUMENT (Encode only) Quality factor, horizontal resolution and/or vertical resolution are invalid. + * @retval FSP_ERR_INVALID_ALIGNMENT (Encode only) The horizontal resolution (at 16bpp) is not divisible by 8 bytes. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_ModeSet (jpeg_ctrl_t * const p_api_ctrl, jpeg_mode_t mode) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + + #if JPEG_CFG_ENCODE_ENABLE && JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + + /* Don't allow changing mode while JPEG unit is in use */ + FSP_ERROR_RETURN(p_ctrl->status & JPEG_STATUS_IDLE, FSP_ERR_IN_USE); + + if (mode == JPEG_MODE_ENCODE) + { + fsp_err_t err = r_jpeg_encode_init_param_check(p_ctrl->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Deinitialize previous mode */ + r_jpeg_mode_deinit(p_ctrl->mode); + + /* Set and initialize the new mode */ + r_jpeg_mode_init(p_ctrl, mode); + + return FSP_SUCCESS; +} + + #endif + +#endif + +/*******************************************************************************************************************//** + * Cancel an outstanding JPEG codec operation and close the device. + * + * @retval FSP_SUCCESS The JPEG unit is stopped and the driver is closed. + * @retval FSP_ERR_ASSERTION Pointer to the control block is NULL. + * @retval FSP_ERR_NOT_OPEN JPEG not opened. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_Close (jpeg_ctrl_t * p_api_ctrl) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + +#if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); +#endif + + /* Set JPEG driver status to CLOSED */ + p_ctrl->open = JPEG_CLOSED; + + /* Disable and clear all interrupts */ + R_BSP_IrqDisable(p_ctrl->p_cfg->jdti_irq); + R_JPEG->JINTE1 = 0; +#if JPEG_CFG_DECODE_ENABLE + R_BSP_IrqDisable(p_ctrl->p_cfg->jedi_irq); + R_JPEG->JINTE0 = 0; +#endif + + /* Flush input and output data */ +#if JPEG_CFG_DECODE_ENABLE && JPEG_CFG_ENCODE_ENABLE + r_jpeg_mode_deinit(p_ctrl->mode); +#elif JPEG_CFG_DECODE_ENABLE + r_jpeg_mode_deinit(JPEG_MODE_DECODE); +#else + r_jpeg_mode_deinit(JPEG_MODE_ENCODE); +#endif + + /* Power off the JPEG unit */ + R_BSP_MODULE_STOP(FSP_IP_JPEG, 0); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get the status of the JPEG codec. This function can also be used to poll the device. + * + * @retval FSP_SUCCESS The status information is successfully retrieved. + * @retval FSP_ERR_ASSERTION Pointer to the control block or p_status is NULL. + * @retval FSP_ERR_NOT_OPEN JPEG is not opened. + **********************************************************************************************************************/ +fsp_err_t R_JPEG_StatusGet (jpeg_ctrl_t * p_api_ctrl, jpeg_status_t * p_status) +{ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) p_api_ctrl; + +#if JPEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); +#endif + + /* HW does not report error. Return internal status information */ + *p_status = p_ctrl->status; + + if ((uint32_t) JPEG_STATUS_ERROR & p_ctrl->status) + { + return p_ctrl->error_code; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup JPEG_DECODE) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (JPEG_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter checking for buffer setting functions. + * + * @param[in] p_ctrl Pointer to control block structure. + * @param[in] p_buffer Pointer to the output buffer. + * @param[in] buffer_size Size of the output buffer. + * @retval FSP_SUCCESS All the parameter are valid. + * @retval FSP_ERR_NOT_OPEN JPEG module is closed or in use. + * @retval FSP_ERR_ASSERTION p_ctrl or p_buffer is NULL. + * @retval FSP_ERR_INVALID_ALIGNMENT p_output_buffer is not on 8-byte memory boundary, or output_buffer_size is not a + * multiple of eight. + **********************************************************************************************************************/ +static fsp_err_t r_jpeg_bufferset_param_check (jpeg_instance_ctrl_t const * const p_ctrl, + void * p_buffer, + uint32_t buffer_size) +{ + FSP_ASSERT(NULL != p_buffer); + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN((JPEG_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(!((uint32_t) p_buffer & JPEG_PRV_ALIGNMENT_8), FSP_ERR_INVALID_ALIGNMENT); + + #if JPEG_CFG_DECODE_ENABLE + #if JPEG_CFG_ENCODE_ENABLE + if (p_ctrl->mode == JPEG_MODE_DECODE) + #endif + { + FSP_ERROR_RETURN(!(buffer_size & JPEG_PRV_ALIGNMENT_8), FSP_ERR_INVALID_ALIGNMENT); + } + + #else + FSP_PARAMETER_NOT_USED(buffer_size); + #endif + + return FSP_SUCCESS; +} + + #if JPEG_CFG_ENCODE_ENABLE + +/*******************************************************************************************************************//** + * Parameter check function for JPEG Encode image size parameters. + * + * @param[in] horizontal Horizontal size (in pixels) + * @param[in] vertical Vertical size (in pixels) + * @param[in] stride Horizontal stride (in pixels) + * @retval FSP_SUCCESS All parameters are valid. + * @retval FSP_ERR_INVALID_ARGUMENT Horizontal resolution and/or vertical resolution are invalid. + * @retval FSP_ERR_INVALID_ALIGNMENT The resolution is not compatible with the minimum coded unit (MCU) size + * (16x8 pixels) and/or the horizontal stride is not divisible by 8. + **********************************************************************************************************************/ +static fsp_err_t r_jpeg_encode_image_size_param_check (uint16_t horizontal, uint16_t vertical, uint16_t stride) +{ + FSP_ERROR_RETURN(0U != horizontal, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(0U != vertical, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(0U == (horizontal & 0x07), FSP_ERR_INVALID_ALIGNMENT); + FSP_ERROR_RETURN(0U == (vertical & 0x03), FSP_ERR_INVALID_ALIGNMENT); + FSP_ERROR_RETURN(stride >= horizontal, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(!(stride & JPEG_PRV_ALIGNMENT_8), FSP_ERR_INVALID_ALIGNMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Parameter check function for JPEG Encode initialization. + * + * @param[in] p_cfg Pointer to config block structure. + * @retval FSP_SUCCESS All parameters are valid. + * @retval FSP_ERR_INVALID_ARGUMENT Quality factor, horizontal resolution and/or vertical resolution are invalid. + * @retval FSP_ERR_INVALID_ALIGNMENT The horizontal resolution (at 16bpp) is not divisible by 8 bytes. + **********************************************************************************************************************/ +static fsp_err_t r_jpeg_encode_init_param_check (jpeg_cfg_t const * const p_cfg) +{ + fsp_err_t err = r_jpeg_encode_image_size_param_check(p_cfg->horizontal_resolution, + p_cfg->vertical_resolution, + p_cfg->horizontal_stride_pixels); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + + #endif + +#endif + +#if JPEG_CFG_DECODE_ENABLE + +/*******************************************************************************************************************//** + * Decode initialization function. + * + * @param[in,out] p_ctrl Pointer to control structure. + * @retval None + **********************************************************************************************************************/ +static void r_jpeg_decode_init (jpeg_instance_ctrl_t * p_ctrl) +{ + jpeg_cfg_t const * p_cfg = p_ctrl->p_cfg; + + /* Set control block */ + p_ctrl->pixel_format = p_cfg->pixel_format; + p_ctrl->horizontal_stride_bytes = 0U; + p_ctrl->output_buffer_size = 0U; + p_ctrl->total_lines_decoded = 0U; + p_ctrl->horizontal_subsample = JPEG_DECODE_OUTPUT_NO_SUBSAMPLE; + + /* Perform bus reset */ + R_JPEG->JCCMD = R_JPEG_JCCMD_BRST_Msk; + + /* Reset the JPEG unit buffer addresses and horizontal stride setting */ + R_JPEG->JIFDDA = 0U; + R_JPEG->JIFDSA = 0U; + R_JPEG->JIFDDOFST = 0U; + + /* Reset encode size registers in case they were in use */ + R_JPEG->JCVSZU = 0; + R_JPEG->JCVSZD = 0; + R_JPEG->JCHSZU = 0; + R_JPEG->JCHSZD = 0; + + /* Configure the JPEG module for decode operation */ + R_JPEG->JCMOD = JPEG_PRV_OPERATION_DECODE; + + /* Set data order (byte swapping) and output format */ + R_JPEG->JIFDCNT = (uint32_t) (p_cfg->decode_output_data_order + (p_cfg->decode_input_data_order << 8) + + (p_cfg->pixel_format << 24)); + + /* If the output pixel format is ARGB8888, also configure the alpha value */ + if (JPEG_DECODE_PIXEL_FORMAT_ARGB8888 == p_cfg->pixel_format) + { + R_JPEG->JIFDADT = p_cfg->alpha_value; + } + + /* Clear interrupt status */ + R_JPEG->JINTS0 = 0; + R_JPEG->JINTS1 = 0; + + /* Clear interrupt request in JCCMD + * (See Note 1 of "JPEG Interrupt Status Register 0 (JINTS0)" description in the relevant hardware manual). */ + R_JPEG->JCCMD = R_JPEG_JCCMD_JEND_Msk; + + /* The following interrupts are enabled: + * Interrupt on all errors + * Interrupt on Image Size + */ + R_JPEG->JINTE0 = R_JPEG_JINTE0_INT3_Msk | R_JPEG_JINTE0_INT5_Msk | R_JPEG_JINTE0_INT6_Msk | R_JPEG_JINTE0_INT7_Msk; + R_JPEG->JINTE1 = R_JPEG_JINTE1_DBTEN_Msk; +} + +/*******************************************************************************************************************//** + * Get JPEG image size (horizontal and vertical) from JCU registers. + * + * @param p_horizontal Pointer to the storage space for the horizontal value + * @param p_vertical Pointer to the storage space for the vertical value + ***********************************************************************************************************************/ +static void r_jpeg_decode_image_size_get (uint16_t * p_horizontal, uint16_t * p_vertical) +{ + uint16_t upper; + uint16_t lower; + + /* The upper and lower bytes of the JPEG size are in separate 8-bit registers and are not 16-bit aligned. */ + + upper = (uint16_t) (R_JPEG->JCHSZU << 8); + lower = (uint16_t) (R_JPEG->JCHSZD); + *p_horizontal = (uint16_t) (upper | lower); + + upper = (uint16_t) (R_JPEG->JCVSZU << 8); + lower = (uint16_t) (R_JPEG->JCVSZD); + *p_vertical = (uint16_t) (upper | lower); +} + +/*******************************************************************************************************************//** + * Get the number of lines to decode and check that the image size is valid against the output buffer. + * + * @param[in] p_ctrl Pointer to control block structure. + * @param[out] p_lines_to_decode Pointer to number of Output data lines. + * + * @retval FSP_SUCCESS Line count returned successfully. + * @retval FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH The output buffer is too small. + * @retval FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE The number of horizontal pixels exceeds horizontal memory stride. + **********************************************************************************************************s************/ +static fsp_err_t r_jpeg_decode_line_number_get (jpeg_instance_ctrl_t * const p_ctrl, uint16_t * p_lines_to_decode) +{ + fsp_err_t err = FSP_SUCCESS; + uint16_t horizontal; + uint16_t vertical; + uint16_t horizontal_bytes; + uint16_t lines_to_decode; + + lines_to_decode = (uint16_t) (p_ctrl->output_buffer_size / p_ctrl->horizontal_stride_bytes); + + r_jpeg_decode_image_size_get(&horizontal, &vertical); + + /* If the decode has been partially completed set lines_to_decode appropriately */ + uint16_t remaining_lines = (uint16_t) (vertical - p_ctrl->total_lines_decoded); + if (lines_to_decode > remaining_lines) + { + lines_to_decode = remaining_lines; + } + + /* With 4:2:0 subsampling there are half the lines and in any mode the decode line count must be a multiple of 8 + * (see "JPEG Interface Decompression Destination Line Count Register (JIFDDLC)" description in the relevant hardware manual) */ + if (JPEG_COLOR_SPACE_YCBCR420 == (jpeg_color_space_t) (R_JPEG->JCMOD_b.REDU)) + { + lines_to_decode = lines_to_decode / 2U; + } + + lines_to_decode &= (uint16_t) (~7U); + + if (0U != lines_to_decode) + { + if (JPEG_DECODE_PIXEL_FORMAT_ARGB8888 == p_ctrl->pixel_format) + { + horizontal_bytes = (uint16_t) (horizontal * 4U); + } + else + { + horizontal_bytes = (uint16_t) (horizontal * 2U); + } + + /* If the decoded image will be wider than the destination framebuffer return an error */ + if ((uint32_t) (horizontal_bytes >> p_ctrl->horizontal_subsample) > p_ctrl->horizontal_stride_bytes) + { + p_ctrl->status = (jpeg_status_t) (p_ctrl->status | JPEG_STATUS_ERROR); + p_ctrl->error_code = FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE; + + err = FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE; + } + } + else + { + err = FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH; + } + + *p_lines_to_decode = lines_to_decode; + + return err; +} + +/*******************************************************************************************************************//** + * Set the JPEG hardware to run in the Output Count mode and start JPEG decompression. + * + * @param[in] p_ctrl Pointer to control block structure. + * @param[in] lines_to_decode Number of Output data lines. + * @note This is a private function in the driver module so not check the input parameter. + **********************************************************************************************************************/ +static void r_jpeg_decode_output_start (jpeg_instance_ctrl_t * const p_ctrl, const uint16_t lines_to_decode) +{ + /* Enable the data transfer interrupt */ + R_JPEG->JINTE1 |= R_JPEG_JINTE1_DOUTLEN_Msk; + + /* Enable data output */ + R_JPEG->JIFDCNT |= (R_JPEG_JIFDCNT_DOUTLC_Msk | R_JPEG_JIFDCNT_DOUTRINI_Msk); + + /* Set number of lines to decode */ + R_JPEG->JIFDDLC = lines_to_decode; + + /* Set the driver status to JPEG_STATUS_RUNNING */ + p_ctrl->status = (jpeg_status_t) ((uint32_t) p_ctrl->status | (uint32_t) JPEG_STATUS_RUNNING); + + /* Clear JPEG stop */ + R_JPEG->JCCMD = R_JPEG_JCCMD_JRST_Msk; +} + +/*******************************************************************************************************************//** + * Check if number of pixels is valid against JPEG hardware constraints (the number must be a multiple of the MCU). + * + * @param[in] p_ctrl Pointer to control block structure. + * @param[in] horizontal Number of horizontal pixels. + * @param[in] vertical Number of vertical pixels. + **********************************************************************************************************************/ +static void r_jpeg_decode_pixel_number_check (jpeg_instance_ctrl_t * const p_ctrl, + const uint16_t horizontal, + const uint16_t vertical) +{ + jpeg_color_space_t color_format; + + /* Look-up table for horizontal alignment versus color space */ + uint16_t alignment_lut_h[] = + { + [JPEG_COLOR_SPACE_YCBCR444] = JPEG_PRV_ALIGNMENT_8, + [JPEG_COLOR_SPACE_YCBCR422] = JPEG_PRV_ALIGNMENT_8, + [JPEG_COLOR_SPACE_YCBCR420] = JPEG_PRV_ALIGNMENT_16, + [JPEG_COLOR_SPACE_YCBCR411] = JPEG_PRV_ALIGNMENT_8, + }; + + /* Look-up table for vertical alignment versus color space */ + uint16_t alignment_lut_v[] = + { + [JPEG_COLOR_SPACE_YCBCR444] = JPEG_PRV_ALIGNMENT_8, + [JPEG_COLOR_SPACE_YCBCR422] = JPEG_PRV_ALIGNMENT_16, + [JPEG_COLOR_SPACE_YCBCR420] = JPEG_PRV_ALIGNMENT_16, + [JPEG_COLOR_SPACE_YCBCR411] = JPEG_PRV_ALIGNMENT_32, + }; + + color_format = (jpeg_color_space_t) (R_JPEG->JCMOD_b.REDU); + + /* Check the number of pixels for individual YCbCr color space formats: + * - All formats must be 8-byte aligned + * - 4:2:2 horizontal size must be 16-byte aligned + * - 4:1:1 horizontal size must be 32-byte aligned + * - 4:2:2 horizontal and vertical size must be 16-byte aligned + */ + if ((horizontal & alignment_lut_h[color_format]) || (vertical & alignment_lut_v[color_format])) + { + p_ctrl->status = (jpeg_status_t) ((uint32_t) p_ctrl->status | (uint32_t) JPEG_STATUS_ERROR); + p_ctrl->error_code = FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE; + } +} + +/*******************************************************************************************************************//** + * Inline function to change status bits. + * + * @param[in] p_ctrl Pointer to control block structure. + * @param[in] clear Bitmask to clear + * @param[in] set Bitmask to set + * @retval None + **********************************************************************************************************************/ +__STATIC_INLINE void r_jpeg_status_change (jpeg_instance_ctrl_t * const p_ctrl, uint8_t clear, uint8_t set) +{ + p_ctrl->status = (jpeg_status_t) ((p_ctrl->status & ~clear) | set); +} + +#endif + +#if JPEG_CFG_ENCODE_ENABLE + +/*******************************************************************************************************************//** + * Encode initialization function. + * + * @param[in,out] p_ctrl Pointer to control structure. + * @retval None + **********************************************************************************************************************/ +static void r_jpeg_encode_init (jpeg_instance_ctrl_t * p_ctrl) +{ + jpeg_cfg_t const * p_cfg = p_ctrl->p_cfg; + + /* Perform bus reset */ + R_JPEG->JCCMD = R_JPEG_JCCMD_BRST_Msk; + + /* Configure the JPEG module for encode operation and set input pixel format (YCbCr 4:2:2 only) */ + /* (This must be done first as many registers/bitfields are read-only depending on the mode) */ + R_JPEG->JCMOD = JPEG_PRV_OPERATION_ENCODE | (JPEG_PRV_YCBCR422 << R_JPEG_JCMOD_REDU_Pos); + + /* Reset the destination buffer address so the driver knows it has not been set */ + R_JPEG->JIFEDA = 0; + + /* Set the image horizontal and vertical size.*/ + r_jpeg_encode_image_size_set(p_cfg->horizontal_resolution, + p_cfg->vertical_resolution, + p_cfg->horizontal_stride_pixels); + + /* Set the output data format. */ + R_JPEG->JIFECNT = (uint32_t) (p_cfg->encode_input_data_order + (uint32_t) (p_cfg->encode_output_data_order << 8) + + R_JPEG_JIFECNT_DINRINI_Msk); + + /* Quantization table setting + * NOTE: Table 0 is used for Luminance (Y) and Table 1 is used for Chrominance (Cr and Cb) */ + R_JPEG->JCQTN = JPEG_PRV_QUANTIZATION_TABLE_SETTING; + + /* Huffman table setting */ + R_JPEG->JCHTN = JPEG_PRV_HUFFMAN_TABLE_SETTING; + + /* Upload Huffman and quantization tables to JPEG Codec */ + for (uint8_t i = 0; i < JPEG_PRV_HUFFM_AC_TABLE_SIZE; i++) + { + if (i < JPEG_PRV_HUFFM_DC_TABLE_SIZE) + { + R_JPEG->JCHTBD0[i] = p_cfg->p_huffman_luma_dc_table[i]; + R_JPEG->JCHTBD1[i] = p_cfg->p_huffman_chroma_dc_table[i]; + } + + if (i < JPEG_PRV_QUANT_TABLE_SIZE) + { + R_JPEG->JCQTBL0[i] = p_cfg->p_quant_luma_table[i]; + R_JPEG->JCQTBL1[i] = p_cfg->p_quant_chroma_table[i]; + } + + R_JPEG->JCHTBA0[i] = p_cfg->p_huffman_luma_ac_table[i]; + R_JPEG->JCHTBA1[i] = p_cfg->p_huffman_chroma_ac_table[i]; + } + + /* Reset interval setting */ + R_JPEG->JCDRIU = (uint8_t) (p_cfg->dri_marker >> 8); + R_JPEG->JCDRID = (uint8_t) (p_cfg->dri_marker & UINT8_MAX); + + /* Record image parameters to ctrl */ + p_ctrl->vertical_resolution = p_cfg->vertical_resolution; + p_ctrl->horizontal_stride_bytes = p_cfg->horizontal_stride_pixels * JPEG_PRV_YCBCR_BYTES_PER_PIXEL; + + /* Enabled JPEG Compression data transfer complete interrupt and Count mode Interrupt */ + R_JPEG->JINTE0 = 0; + R_JPEG->JINTE1 = R_JPEG_JINTE1_CBTEN_Msk | R_JPEG_JINTE1_DINLEN_Msk; +} + +/*******************************************************************************************************************//** + * Function to correct output data when needed. (See "Data correction" + * in the JPEG section of the relevant hardware manual) + * + * @param[in] p_ctrl Pointer to control block structure. + * @param[in] final_output Number of bytes that may need to be corrected. + * @retval None + **********************************************************************************************************************/ +static void r_jpeg_data_correction (jpeg_instance_ctrl_t * p_ctrl, uint8_t final_output) +{ + uint8_t * p_end_data = NULL; + uint8_t * p_start_data = NULL; + + /* Get pointer to start and end of JPEG */ + p_start_data = (uint8_t *) R_JPEG->JIFEDA; + p_end_data = (uint8_t *) (R_JPEG->JIFEDA + p_ctrl->output_buffer_size) - 2; + + /* Is the final coded data EOI (0xFFD9)? */ + if ((JPEG_PRV_EOI_B1 != p_end_data[1]) && (JPEG_PRV_EOI_B0 != p_end_data[0])) + { + /* Correct final data */ + memcpy((p_end_data - (final_output - 1U)), p_start_data, final_output); + } + + /* Correct data at JIFEDA address */ + memcpy(p_start_data, g_initial_data, 6); +} + +/*******************************************************************************************************************//** + * Set JPEG image size (horizontal and vertical). + * + * @param[in] horizontal Horizontal size of image (in pixels). + * @param[in] vertical Vertical size of image (in pixels). + * @param[in] stride Horizontal stride of image (in pixels). + * @retval None + **********************************************************************************************************************/ +static void r_jpeg_encode_image_size_set (uint16_t horizontal, uint16_t vertical, uint16_t stride) +{ + /* Set the horizontal stride. */ + R_JPEG->JIFESOFST = stride & R_JPEG_JIFESOFST_ESMW_Msk; + + /* Vertical image size */ + R_JPEG->JCVSZU = (uint8_t) (vertical >> 8); + R_JPEG->JCVSZD = (uint8_t) vertical; + + /* Horizontal image size */ + R_JPEG->JCHSZU = (uint8_t) (horizontal >> 8); + R_JPEG->JCHSZD = (uint8_t) horizontal; +} + +#endif + +#if JPEG_CFG_DECODE_ENABLE && JPEG_CFG_ENCODE_ENABLE + +/*******************************************************************************************************************//** + * Initialize the JPEG unit for a specific mode. + * + * @param[in] p_ctrl Pointer to control block structure. + * @param[in] mode Mode to initialize. + * @retval None + **********************************************************************************************************************/ +static void r_jpeg_mode_init (jpeg_instance_ctrl_t * p_ctrl, jpeg_mode_t mode) +{ + /* Set the startup mode */ + p_ctrl->mode = mode; + + if (mode == JPEG_MODE_DECODE) + { + r_jpeg_decode_init(p_ctrl); + } + else + { + r_jpeg_encode_init(p_ctrl); + } +} + +#endif + +/*******************************************************************************************************************//** + * Deinitialize the current mode. + * + * @param[in] mode Mode to deinitialize + * @retval None + **********************************************************************************************************************/ +static void r_jpeg_mode_deinit (jpeg_mode_t mode) +{ +#if !(JPEG_CFG_DECODE_ENABLE && JPEG_CFG_ENCODE_ENABLE) + FSP_PARAMETER_NOT_USED(mode); +#endif + +#if JPEG_CFG_DECODE_ENABLE + #if JPEG_CFG_ENCODE_ENABLE + if (mode == JPEG_MODE_DECODE) + #endif + { + /* JINRCMD and DOUTRCMD must be set for the JPEG Codec to stop cleanly in Decode mode */ + R_JPEG->JIFDCNT |= (R_JPEG_JIFDCNT_JINRCMD_Msk | R_JPEG_JIFDCNT_DOUTRCMD_Msk); + } +#endif + + /* Perform bus reset to stop any ongoing operation + * Note: Verified with design team that setting BRST during codec operation is okay. */ + R_JPEG->JCCMD = R_JPEG_JCCMD_BRST_Msk; +} + +/*******************************************************************************************************************//** + * Data Transfer Interrupt (JDTI) Interrupt Service Routine (ISR). + * @retval None + **********************************************************************************************************************/ +void jpeg_jdti_isr () +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + /* Obtain the control block. */ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) R_FSP_IsrContextGet(R_FSP_CurrentIrqGet()); + + uint32_t intertype; + jpeg_callback_args_t args; + + /* Get the interrupt type */ + intertype = R_JPEG->JINTS1; + + /* Clear the interrupt flag */ + R_JPEG->JINTS1 = 0x0; + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + +#if JPEG_CFG_DECODE_ENABLE + + /* Return if there are errors */ + if ((uint32_t) JPEG_STATUS_ERROR & p_ctrl->status) + { + + /* If error is detected, no need to further process this interrupt. Simply return */ + return; + } + + /* Check for input pause, output pause and decompression output complete statuses */ + if (intertype & (R_JPEG_JINTS1_JINF_Msk | R_JPEG_JINTS1_DOUTLF_Msk | R_JPEG_JINTS1_DBTF_Msk)) + { + uint32_t status = p_ctrl->status; + + /* Clear internal status information */ + status &= ~((uint32_t) JPEG_STATUS_RUNNING); + + /* Input data pause (specified number of bytes read) */ + if (intertype & R_JPEG_JINTS1_JINF_Msk) + { + /* Set the ctrl status */ + status |= (uint32_t) JPEG_STATUS_INPUT_PAUSE; + + /* Clear the source address */ + R_JPEG->JIFDSA = (uint32_t) 0; + } + + /* Output data pause (specified number of lines written) */ + if (intertype & R_JPEG_JINTS1_DOUTLF_Msk) + { + uint32_t lines_decoded = 0; + + /* Set the ctrl status */ + status |= (uint32_t) JPEG_STATUS_OUTPUT_PAUSE; + + /* Clear the destination address */ + R_JPEG->JIFDDA = 0; + + /* Obtain the number of lines decoded in this operation */ + if (FSP_SUCCESS != R_JPEG_DecodeLinesDecodedGet(p_ctrl, &lines_decoded)) + { + + /* If error is detected, no need to further process this interrupt. Simply return */ + return; + } + + /* Increment the number of lines decoded */ + p_ctrl->total_lines_decoded = (uint16_t) (p_ctrl->total_lines_decoded + (uint16_t) lines_decoded); + } + + uint16_t horizontal; + uint16_t vertical; + + r_jpeg_decode_image_size_get(&horizontal, &vertical); + + /* Data output complete */ + if ((intertype & R_JPEG_JINTS1_DBTF_Msk) || ((p_ctrl->total_lines_decoded >= vertical) && vertical)) + { + /* Set the ctrl status to done */ + status = (uint32_t) (JPEG_STATUS_IDLE | JPEG_STATUS_OPERATION_COMPLETE); + } + + /* Write updated status back to control block */ + p_ctrl->status = (jpeg_status_t) status; + + /* Invoke user-supplied callback function if it is set */ + if (NULL != p_ctrl->p_cfg->p_decode_callback) + { + args.status = p_ctrl->status; + args.p_context = p_ctrl->p_cfg->p_decode_context; + p_ctrl->p_cfg->p_decode_callback(&args); + } + } +#endif + +#if JPEG_CFG_ENCODE_ENABLE + if (intertype & (R_JPEG_JINTS1_CBTF_Msk | R_JPEG_JINTS1_DINLF_Msk)) + { + /* Record the output buffer size */ + int32_t output_buffer_size = R_JPEG->JCDTCD; + output_buffer_size += (R_JPEG->JCDTCM << 8); + p_ctrl->output_buffer_size = (uint32_t) ((R_JPEG->JCDTCU << 16) + output_buffer_size); + + /* Do not call the callback unless one of the two following events has occurred */ + bool valid = false; + + /* Encode complete */ + if (intertype & R_JPEG_JINTS1_CBTF_Msk) + { + /* Data correction */ + uint8_t remainder = (p_ctrl->output_buffer_size % 8); + + /* Data correction decision, if remainder is 1 to 6 bytes */ + if (remainder && (remainder < 7U)) + { + r_jpeg_data_correction(p_ctrl, remainder); + } + + p_ctrl->status = (jpeg_status_t) (JPEG_STATUS_IDLE | JPEG_STATUS_OPERATION_COMPLETE); + + valid = true; + } + /* Input pause (and not yet complete) */ + else if ((p_ctrl->total_lines_encoded) <= (p_ctrl->vertical_resolution - p_ctrl->lines_to_encode)) + { + p_ctrl->status = JPEG_STATUS_INPUT_PAUSE; + + valid = true; + } + else + { + /* Do nothing */ + } + + if (valid) + { + /* Update number of lines encoded */ + p_ctrl->total_lines_encoded = (uint16_t) (p_ctrl->total_lines_encoded + p_ctrl->lines_to_encode); + + /* Invoke the callback (if available and requested) */ + if (NULL != p_ctrl->p_cfg->p_encode_callback) + { + args.image_size = p_ctrl->output_buffer_size; + args.status = p_ctrl->status; + args.p_context = p_ctrl->p_cfg->p_encode_context; + p_ctrl->p_cfg->p_encode_callback(&args); + } + } + } +#endif + + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * JPEG Compression/Decompression Process Interrupt (JEDI) Interrupt Service Routine (ISR). + * + * @note The INS6 interrupt (JPEG Process End) is not used as it does not indicate when the data transfer from the JPEG + * codec has completed. CBTF and DBTF are used to ensure an operation is only deemed complete when data is ready + * for use. + * + * @retval None + **********************************************************************************************************************/ +void jpeg_jedi_isr () +{ +#if JPEG_CFG_DECODE_ENABLE + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + /* Obtain the control block. */ + jpeg_instance_ctrl_t * p_ctrl = (jpeg_instance_ctrl_t *) R_FSP_IsrContextGet(R_FSP_CurrentIrqGet()); + + uint8_t intertype; + + /* Get the interrupt type */ + intertype = R_JPEG->JINTS0; + + /* Clear the interrupt status */ + R_JPEG->JINTS0 = 0; + + /* Clear the request */ + R_JPEG->JCCMD = R_JPEG_JCCMD_JEND_Msk; + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + uint16_t horizontal = 0; + uint16_t vertical = 0; + jpeg_callback_args_t args; + + /* Decompression error */ + if (intertype & R_JPEG_JINTS0_INS5_Msk) + { + /* Set the internal status and error code */ + p_ctrl->status = JPEG_STATUS_ERROR; + p_ctrl->error_code = (fsp_err_t) (R_JPEG->JCDERR + (uint32_t) FSP_ERR_JPEG_ERR); + + /* Invoke user-supplied callback function if it is set */ + if (NULL != p_ctrl->p_cfg->p_decode_callback) + { + args.status = p_ctrl->status; + args.p_context = p_ctrl->p_cfg->p_decode_context; + p_ctrl->p_cfg->p_decode_callback(&args); + } + + /* If error is detected, no need to further process this interrupt. Simply return */ + return; + } + + /* Image size acquired */ + if (intertype & R_JPEG_JINTS0_INS3_Msk) + { + /* Set status to image size ready */ + + r_jpeg_status_change(p_ctrl, (JPEG_STATUS_HEADER_PROCESSING | JPEG_STATUS_RUNNING), + JPEG_STATUS_IMAGE_SIZE_READY); + + /* JPEG header is decoded. Obtain image size, and input pixel format. Verify that image size (width and height) + * is aligned to the Minimum Coded Unit */ + r_jpeg_decode_image_size_get(&horizontal, &vertical); + r_jpeg_decode_pixel_number_check(p_ctrl, horizontal, vertical); + + /* Invoke user-supplied callback function if it is set */ + if (NULL != p_ctrl->p_cfg->p_decode_callback) + { + args.status = p_ctrl->status; + args.p_context = p_ctrl->p_cfg->p_decode_context; + p_ctrl->p_cfg->p_decode_callback(&args); + } + + /* If both Input buffer and output buffer are set, and horizontal stride is set, the driver is available + * to determine the number of lines to decode, and start the decoding operation */ + if ((R_JPEG->JIFDSA) && (p_ctrl->output_buffer_size) && (p_ctrl->horizontal_stride_bytes)) + { + uint16_t lines_to_decode = 0; + + /* Get number of lines that can be decoded at once based on the output buffer size */ + if (FSP_SUCCESS != r_jpeg_decode_line_number_get(p_ctrl, &lines_to_decode)) + { + + /* If error was detected in pixel_number_check there is no need to further process this interrupt */ + return; + } + + /* Set the ctrl status */ + p_ctrl->status |= (uint32_t) JPEG_STATUS_RUNNING; + + /* Detect the output count mode setting based on buffer size */ + r_jpeg_decode_output_start(p_ctrl, lines_to_decode); + } + else + { + /* Otherwise clear running status */ + p_ctrl->status &= ~((uint32_t) JPEG_STATUS_RUNNING); + } + } + FSP_CONTEXT_RESTORE +#endif +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_kint/r_kint.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_kint/r_kint.c new file mode 100644 index 0000000000..1b5133697f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_kint/r_kint.c @@ -0,0 +1,248 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_kint_cfg.h" +#include "r_kint.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define KINT_OPEN (0x4B494E54) + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +void key_int_isr(void); + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* KeyMatrix Implementation of Key Interrupt */ +const keymatrix_api_t g_keymatrix_on_kint = +{ + .open = R_KINT_Open, + .enable = R_KINT_Enable, + .disable = R_KINT_Disable, + .close = R_KINT_Close, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup KINT + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure all the Key Input (KINT) channels and provides a handle for use with the rest of the KINT API functions. + * Implements @ref keymatrix_api_t::open. + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION One of the following parameters may be NULL: p_cfg, or p_ctrl or the + * callback. + * @retval FSP_ERR_ALREADY_OPEN The module has already been opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel mask is invalid. + **********************************************************************************************************************/ +fsp_err_t R_KINT_Open (keymatrix_ctrl_t * const p_api_ctrl, keymatrix_cfg_t const * const p_cfg) +{ + kint_instance_ctrl_t * p_ctrl = (kint_instance_ctrl_t *) p_api_ctrl; + + /* Check to see that the arguments passed are not null pointers */ +#if KINT_CFG_PARAM_CHECKING_ENABLE + + /* Check NULL pointers */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_callback); + + /* Check that the interrupt is valid. */ + FSP_ASSERT(p_cfg->irq >= 0); + + /* Check that the Open function has been called else return FSP_ERR_NOT_OPEN */ + FSP_ERROR_RETURN(0 == p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Check that the selected channels are valid. */ + FSP_ERROR_RETURN(p_cfg->channel_mask <= UINT8_MAX, FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + +#if BSP_FEATURE_KINT_HAS_MSTP + + /* Clear the Module Stop bit. */ + R_BSP_MODULE_START(FSP_IP_KEY, 0); +#endif + + p_ctrl->p_cfg = p_cfg; + + /* Configure the trigger edge. */ + R_KINT->KRCTL = (uint8_t) p_cfg->trigger | R_KINT_KRCTL_KRMD_Msk; + + /* Enable interrupt for the selected channels after casting since KRM is an 8 bit register */ + R_KINT->KRM = 0; + + /* Configure the interrupt priority. */ + R_BSP_IrqCfg(p_cfg->irq, p_cfg->ipl, p_ctrl); + + /* Mark KINT as initialized */ + p_ctrl->open = KINT_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Clear the KINT configuration and disable the KINT IRQ. Implements @ref keymatrix_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The module is not opened. + **********************************************************************************************************************/ +fsp_err_t R_KINT_Close (keymatrix_ctrl_t * const p_api_ctrl) +{ + kint_instance_ctrl_t * p_ctrl = (kint_instance_ctrl_t *) p_api_ctrl; + +#if KINT_CFG_PARAM_CHECKING_ENABLE + + /* Check for null pointers */ + FSP_ASSERT(NULL != p_ctrl); + + /* Check that the Open function has been called else return FSP_ERR_NOT_OPEN */ + FSP_ERROR_RETURN(p_ctrl->open == KINT_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /** Disable interrupt in NVIC. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + + /** Disable interrupts in the KINT peripheral*/ + R_KINT->KRM = 0U; + +#if BSP_FEATURE_KINT_HAS_MSTP + + /* Set the Module Stop bit. */ + R_BSP_MODULE_STOP(FSP_IP_KEY, 0); +#endif + + /* Mark KINT as un-initialized */ + p_ctrl->open = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function enables interrupts for the KINT peripheral after clearing any pending requests. + * Implements @ref keymatrix_api_t::enable. + * + * @retval FSP_SUCCESS Interrupt enabled successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. + * @retval FSP_ERR_NOT_OPEN The peripheral is not opened. + **********************************************************************************************************************/ +fsp_err_t R_KINT_Enable (keymatrix_ctrl_t * const p_api_ctrl) +{ + kint_instance_ctrl_t * p_ctrl = (kint_instance_ctrl_t *) p_api_ctrl; + +#if KINT_CFG_PARAM_CHECKING_ENABLE + + /* Check for null pointer. */ + FSP_ASSERT(NULL != p_ctrl); + + /* Check that the Open function has been called else return FSP_ERR_NOT_OPEN */ + FSP_ERROR_RETURN(p_ctrl->open == KINT_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /* Enable interrupt for the selected channels after casting since KRM is an 8 bit register */ + R_KINT->KRM = (uint8_t) p_ctrl->p_cfg->channel_mask; + + /* Clear any pending interrupt requests in the KINT peripheral */ + R_KINT->KRF = 0; + + /* Enable interrupt */ + R_BSP_IrqEnable(p_ctrl->p_cfg->irq); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function disables interrupts for the KINT peripheral. Implements @ref keymatrix_api_t::disable. + * + * @retval FSP_SUCCESS Interrupt disabled successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_KINT_Disable (keymatrix_ctrl_t * const p_api_ctrl) +{ + kint_instance_ctrl_t * p_ctrl = (kint_instance_ctrl_t *) p_api_ctrl; + +#if KINT_CFG_PARAM_CHECKING_ENABLE + + /* Check for null pointers */ + FSP_ASSERT(NULL != p_ctrl); + + /* Check that the Open function has been called else return FSP_ERR_NOT_OPEN */ + FSP_ERROR_RETURN(p_ctrl->open == KINT_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /* Disable interrupt in the ICU */ + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + + /* Disable interrupts in the KINT peripheral */ + R_KINT->KRM = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup KINT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * ISR for handling key interrupts. It calls p_callback with a mask of channels that caused the interrupt. + **********************************************************************************************************************/ +void key_int_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + kint_instance_ctrl_t * p_ctrl = (kint_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Read the state of the Key Input pins/ */ + uint8_t status = R_KINT->KRF; + + /* The IRQ status must be cleared after reading the KRF register and before writing to the KRF register. + * If the IRQ status is cleared and an edge is detected before KRF is read, then a second interrupt will be + * generated with KRF equal to 0. If the IRQ status is cleared after writing to KRF, then an interrupt could be + * missed. */ + R_BSP_IrqStatusClear(irq); + + /* Only clear the serviced channels in the KINT peripheral. + * Note: + * - Writing 0 to a KRF register bit clears the KRF bit. Writing 1 has no effect on a KRF register bit value. + * - Clearing a subset of KRFn bits has the effect of generating an additional interrupt request (See + * "Operation when using the key interrupt flags" in the KINT section of the relevant hardware manual). */ + R_KINT->KRF = (uint8_t) ~status; + + /* Set data to identify callback to user. */ + keymatrix_callback_args_t cb_data = + { + .channel_mask = status, + .p_context = p_ctrl->p_cfg->p_context + }; + + /* Call the callback function. */ + p_ctrl->p_cfg->p_callback(&cb_data); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_layer3_switch/r_layer3_switch.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_layer3_switch/r_layer3_switch.c new file mode 100644 index 0000000000..38f033742f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_layer3_switch/r_layer3_switch.c @@ -0,0 +1,4041 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ +#include "r_layer3_switch.h" +#include "r_rmac_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/** "ESWM" in ASCII. Used to determine if the control block is open. */ +#define LAYER3_SWITCH_OPEN (('E' << 24U) | ('S' << 16U) | ('W' << 8U) | \ + ('M' << 0U)) + +#define LAYER3_SWITCH_ETHA_REG_SIZE (R_ETHA1_BASE - R_ETHA0_BASE) +#define LAYER3_SWITCH_RMAC_REG_SIZE (R_RMAC1_BASE - R_RMAC0_BASE) +#define LAYER3_SWITCH_REGISTER_SIZE (32) +#define LAYER3_SWITCH_QUEUE_ADDRESS_UPPER_MASK (0xFF00000000) +#define LAYER3_SWITCH_QUEUE_ADDRESS_UPPER_POSITION (32) +#define LAYER3_SWITCH_QUEUE_ADDRESS_LOWER_MASK (0xFFFFFFFF) + +#define LAYER3_SWITCH_FWPBFC_REGISTER_OFFSET (0x10) +#define LAYER3_SWITCH_FWPBFCSDC0_REGISTER_OFFSET (0x10) +#define LAYER3_SWITCH_INTERRUPT_REGISTER_OFFSET (0x10) +#define LAYER3_SWITCH_FWPC_REGISTER_OFFSET (0x10) +#define LAYER3_SWITCH_PORT_CONFIG_REGISTER_OFFSET (0x10) +#define LAYER3_SWITCH_TS_DESCRIPTOR_QUEUE_REGISTOR_OFFSET (0x08) +#define LAYER3_SWITCH_TS_DESCRIPTOR_TIMER_REGISTOR_OFFSET (0x04) + +/* VLAN tag bit position. */ +#define LAYER3_SWITCH_VLAN_TAG_DEI_POSITION (12UL) +#define LAYER3_SWITCH_VLAN_TAG_PCP_POSITION (13UL) + +/* Definitions for forwarding feature. */ +#define LAYER3_SWITCH_MAC_ENTRY_MAX_NUM (0x7FFU) +#define LAYER3_SWITCH_VLAN_ENTRY_MAX_NUM (0xFFFU) +#define LAYER3_SWITCH_L3_ENTRY_MAX_NUM (0xFFU) +#define LAYER3_SWITCH_L3_UPDATE_REMAPPING_MAX_NUM (0x1FU) +#define LAYER3_SWITCH_CLOCK_100MHZ (100U) + +/* MFWD Register bitmask and position. */ +#define R_MFWD_FWIP6OC_IP6IPOM1_Pos (16UL) +#define R_MFWD_FWIP6OC_IP6IPOM1_Msk (0x10000UL) +#define R_MFWD_FWIP6OC_IP6IPO1_Pos (20UL) +#define R_MFWD_FWIP6OC_IP6IPO1_Msk (0xf00000UL) +#define R_MFWD_FWRFVC0_RFSV0_Pos (0UL) +#define R_MFWD_FWRFVC0_RFSV0_Msk (0xffUL) +#define R_MFWD_FWRFVC0_RFSV1_Pos (8UL) +#define R_MFWD_FWRFVC0_RFSV1_Msk (0xff00UL) + +/* Bitmask for the CPU port (GWCA). */ +#define LAYER3_SWITCH_PORT_CPU_BITMASK (1 << BSP_FEATURE_ESWM_GWCA_PORT) +#define LAYER3_SWITCH_EATASIGSC_MASK (R_ETHA0_EATASIGSC_TASIGS0_Msk | \ + R_ETHA0_EATASIGSC_TASIGS1_Msk | \ + R_ETHA0_EATASIGSC_TASIGS2_Msk | \ + R_ETHA0_EATASIGSC_TASIGS3_Msk | \ + R_ETHA0_EATASIGSC_TASIGS4_Msk | \ + R_ETHA0_EATASIGSC_TASIGS5_Msk | \ + R_ETHA0_EATASIGSC_TASIGS6_Msk | \ + R_ETHA0_EATASIGSC_TASIGS7_Msk) + +/* Bitmask for unique number of timestamp. */ +#define LAYER3_SWITCH_TS_UNIQUE_NUMBER_BITMASK (0xFF) + +/* For CBS feature. */ +#define LAYER3_SWITCH_CBS_REQUEST_DELAY (50) +#define LAYER3_SWITCH_CBS_INTERFERENCE_SIZE_OFFSET (20) +#define LAYER3_SWITCH_CBS_BITS_PER_BYTE (8) +#define LAYER3_SWITCH_LINK_SPEED_100M (100000000) +#define LAYER3_SWITCH_LINK_SPEED_1G (1000000000) +#define LAYER3_SWITCH_MAXIMUM_FRAME_SIZE (1514U) + +/* PSFP feature. Offset from FWPMFGC0 to FWPMFGC15. */ +#define LAYER3_SWITCH_PSFP_METER_FILTER_REG_OFFSET (0x20) +#define LAYER3_SWITCH_PSFP_MSDU_FILTER_REGISTER_OFFSET (0x04) + +#define LAYER3_SWITCH_METER_FILTER_PCP_MAX_NUM (8) +#define LAYER3_SWITCH_METER_FILTER_DEI_HANDLING_POLICY_BITMASK (0xAAAAU) + +/* FRER feature. */ +#define LAYER3_SWITCH_FWSEQNGC_REGISTER_OFFSET (0x08) +#define LAYER3_SWITCH_FRER_CHECK_PERIOD_BITMASK (0xFFFFUL) +#define LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK (0x7FUL) +#define LAYER3_SWITCH_FRER_SEQ_GENERATOR_NUM_BITMASK (0x1FUL) +#define LAYER3_SWITCH_FRER_SYSTEM_CLOCK_BITMASK (0x3FFUL) +#define LAYER3_SWITCH_SEQ_REG_MAX_NUM (32) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * layer3_switch_prv_ns_callback)(ether_switch_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile layer3_switch_prv_ns_callback)(ether_switch_callback_args_t * p_args); +#endif + +/* Operation mode of ETHA and GWCA. */ +typedef enum e_layer3_switch_agent_mode +{ + LAYER3_SWITCH_AGENT_MODE_RESET = (0), + LAYER3_SWITCH_AGENT_MODE_DISABLE = (1), + LAYER3_SWITCH_AGENT_MODE_CONFIG = (2), + LAYER3_SWITCH_AGENT_MODE_OPERATION = (3), +} layer3_switch_agent_mode_t; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + ***********************************************************************************************************************/ +void layer3_switch_gwdi_isr(void); +void layer3_switch_eaei_isr(void); + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_layer3_switch_module_start(void); +static void r_layer3_switch_update_gwca_operation_mode( + layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_agent_mode_t mode); +static void r_layer3_switch_update_etha_operation_mode(uint8_t port, + layer3_switch_agent_mode_t mode); +static void r_layer3_switch_reset_coma(void); +static void r_layer3_switch_close_etha_ports(layer3_switch_instance_ctrl_t * p_instance_ctrl); +static void r_layer3_switch_initialize_linkfix_table( + layer3_switch_instance_ctrl_t * p_instance_ctrl); +static layer3_switch_descriptor_t * r_layer3_switch_get_descriptor(layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t queue_index, + uint32_t descriptor_index); +static layer3_switch_descriptor_t * r_layer3_switch_get_current_descriptor( + layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t queue_index); +static bool r_layer3_switch_is_descriptor_queue_active( + layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t queue_index); +static void r_layer3_switch_configure_mac_address(uint8_t * p_mac_address, uint8_t port); +static void r_layer3_switch_configure_port( + layer3_switch_instance_ctrl_t * const p_instance_ctrl, + uint8_t port, + layer3_switch_port_cfg_t const * const p_port_cfg); + +/* Forwarding features. */ +static void r_layer3_switch_configure_forwarding_port(layer3_switch_forwarding_port_cfg_t const * const port_cfg, + uint8_t port); +static void r_layer3_switch_reset_table(layer3_switch_instance_ctrl_t * p_instance_ctrl); +static fsp_err_t r_layer3_switch_learn_mac_entry(layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t const * const p_entry_cfg); +static fsp_err_t r_layer3_switch_search_mac_entry(layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t * const p_entry_cfg); +static fsp_err_t r_layer3_switch_read_mac_entry(uint16_t offset, layer3_switch_table_entry_t * p_entry); +static fsp_err_t r_layer3_switch_learn_vlan_entry(layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t const * const p_entry_cfg); +static fsp_err_t r_layer3_switch_search_vlan_entry(layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t * const p_entry_cfg); +static fsp_err_t r_layer3_switch_read_vlan_entry(uint16_t offset, layer3_switch_table_entry_t * p_entry); +static fsp_err_t r_layer3_switch_learn_l3_entry(layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t const * const p_entry_cfg); +static fsp_err_t r_layer3_switch_search_l3_entry(layer3_switch_frame_filter_t const * p_target_frame, + layer3_switch_table_entry_cfg_t * const p_entry_cfg); +static fsp_err_t r_layer3_switch_learn_l3_update(layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_l3_update_config_t * const p_config); +static fsp_err_t r_layer3_switch_search_l3_update(uint8_t routing_number, layer3_switch_l3_update_config_t * p_config); + +/* MAC/VLAN forwarding. */ +static fsp_err_t r_layer3_switch_enable_mac_table_aging(uint32_t aging_time); +static fsp_err_t r_layer3_switch_extract_vlan_id(layer3_switch_frame_filter_t const * const p_target_frame, + uint16_t * p_vlan_id); +static void r_layer3_switch_initialize_vlan_port(layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_forwarding_port_cfg_t const * const p_port_cfg, + uint8_t port); + +/* L3 forwarding. */ +static fsp_err_t r_layer3_switch_configure_stream_filter(layer3_switch_l3_stream_filter_cfg_t const * p_filter_cfg); +static uint16_t r_layer3_switch_calculate_l3_hash(layer3_switch_frame_filter_t const * p_frame); +static uint8_t r_layer3_switch_calculate_l3_format_code(layer3_switch_frame_filter_t const * p_frame); +static fsp_err_t r_layer3_switch_calculate_l3_stream_id(layer3_switch_frame_filter_t const * p_frame, + layer3_switch_stream_id_t * p_stream_id); +static uint32_t r_layer3_switch_convert_vlan_tag_to_int(layer3_switch_frame_vlan_tag_t const * p_vlan_s_tag, + layer3_switch_frame_vlan_tag_t const * p_vlan_c_tag); +static fsp_err_t r_layer3_switch_remapping_l3_update(layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t routing_number, + layer3_switch_l3_update_config_t * p_update_cfg); +static uint32_t r_layer3_switch_convert_array_to_int(uint8_t * array, uint8_t length); + +/* TSN feature. */ +static void r_layer3_switch_configure_cbs(layer3_switch_instance_ctrl_t const * const p_instance_ctrl, + uint8_t port, + layer3_switch_cbs_cfg_t const * const p_cbs_cfg); +static uint32_t r_layer3_switch_calculate_max_interference_size(uint8_t queue_number, + uint8_t const * const p_max_burst_num_list); + +/* PSFP feature. */ +static fsp_err_t r_layer3_switch_psfp_select_msdu_filter_id(layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t * p_msdu_filter_id, + layer3_switch_psfp_msdu_filter_cfg_t * p_psfp_msdu_filter_cfg); + +static fsp_err_t r_layer3_switch_psfp_select_meter_filter_id(layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t * p_meter_filter_id, + layer3_switch_psfp_meter_filter_cfg_t * p_psfp_meter_filter_cfg); +static fsp_err_t r_layer3_switch_psfp_msdu_filter_init(layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t msdu_filter_id, + layer3_switch_table_entry_cfg_t const * const p_table_entry_cfg); +static fsp_err_t r_layer3_switch_psfp_meter_filter_init(layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t meter_filter_id, + layer3_switch_table_entry_cfg_t const * const p_table_entry_cfg); + +/* FRER feature. */ +static fsp_err_t r_layer3_switch_frer_init(layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_frer_cfg_t const * p_frer_cfg); +static void r_layer3_switch_frer_table_reset(void); +static void r_layer3_switch_configure_sequence_number_generation(layer3_switch_instance_ctrl_t * p_instance_ctrl); +static fsp_err_t r_layer3_switch_learn_frer_entry(layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_frer_entry_t * const p_frer_entry, + layer3_switch_frer_entry_t * const p_sequence_recovery, + uint32_t sequence_recovery_id); +static fsp_err_t r_layer3_switch_learn_frer_individual_recovery(layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_frer_entry_cfg_t * const p_frer_entry_cfg); + +static void r_layer3_switch_call_callback_for_ports(layer3_switch_instance_ctrl_t * p_instance_ctrl, + ether_switch_callback_args_t * p_callback_args, + uint32_t ports); +static void r_layer3_switch_call_callback(void (* p_callback)( + ether_switch_callback_args_t *), + ether_switch_callback_args_t * p_callback_args, + ether_switch_callback_args_t * const p_callback_memory); + +/* Timestamp feature. */ +static fsp_err_t r_layer3_switch_create_tx_timestamp_queue(ether_switch_ctrl_t * const p_ctrl, + const layer3_switch_descriptor_queue_cfg_t * const p_queue_cfg, + uint32_t * const p_ts_descriptor_queue_index); + +static void r_layer3_switch_enable_frame_preemption_feature(layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint8_t port, + bool preemption_enable); +static void r_layer3_switch_rmac_phy_interrupts_callback(ether_phy_callback_args_t * p_args); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** ETHER SWITCH API mapping for layer3 switch module. */ +const ether_switch_api_t g_ether_switch_on_layer3_switch = +{ + .open = R_LAYER3_SWITCH_Open, + .close = R_LAYER3_SWITCH_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup LAYER3_SWITCH + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/********************************************************************************************************************//** + * Initializes the switch module and applies configurations. Implements @ref ether_switch_api_t::open. + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block, config structure or extended config structure is NULL. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION Initialization of PHY-LSI failed. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid configuration value. + ************************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_Open (ether_switch_ctrl_t * const p_ctrl, ether_switch_cfg_t const * const p_cfg) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + layer3_switch_extended_cfg_t * p_extend; + ether_phy_instance_t const * p_ether_phy; + volatile uint32_t * p_mfwd_fwpbfc_reg; + volatile uint32_t * p_etha_eatdqdcn_reg; + R_ETHA0_Type * p_reg_etha; + R_RMAC0_Type * p_reg_rmac; + + fsp_err_t phy_err = FSP_SUCCESS; + +#if (LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE) + + /** Check parameters. */ + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_cfg); + + p_extend = (layer3_switch_extended_cfg_t *) p_cfg->p_extend; + FSP_ASSERT(p_cfg->p_extend); + FSP_ERROR_RETURN((0 <= p_cfg->irq), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM <= BSP_FEATURE_ESWM_MAX_QUEUE_NUM), + FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(LAYER3_SWITCH_L3_ENTRY_MAX_NUM > p_extend->l3_filter_list_length, FSP_ERR_INVALID_ARGUMENT); +#else + p_extend = (layer3_switch_extended_cfg_t *) p_cfg->p_extend; +#endif + + FSP_ERROR_RETURN((LAYER3_SWITCH_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN); + + /* Initialize parameters. */ + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_gwca_reg = R_GWCA0; + p_instance_ctrl->table_status = LAYER3_SWITCH_TABLE_STATUS_UNINITIALIZED; + p_instance_ctrl->l3_entry_count = 0; + p_instance_ctrl->l3_routing_number = 0; + p_instance_ctrl->frame_preemption_available[0] = false; + p_instance_ctrl->frame_preemption_available[1] = false; + + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM; i++) + { + p_instance_ctrl->ts_descriptor_queue_status_list[i] = LAYER3_SWITCH_TS_DESCRIPTOR_QUEUE_STATUS_UNUSED; + } + + /* Initialize PSFP parameters. */ + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM; i++) + { + p_instance_ctrl->psfp_msdu_filter_info_list[i].msdu_filter_hw_id = 0; + p_instance_ctrl->psfp_msdu_filter_info_list[i].status = LAYER3_SWITCH_PSFP_FILTER_STATUS_UNUSED; + p_instance_ctrl->psfp_msdu_filter_info_list[i].p_psfp_msdu_filter_cfg = NULL; + } + + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM; i++) + { + p_instance_ctrl->psfp_meter_filter_info_list[i].meter_filter_hw_id = 0; + p_instance_ctrl->psfp_meter_filter_info_list[i].status = + LAYER3_SWITCH_PSFP_FILTER_STATUS_UNUSED; + p_instance_ctrl->psfp_meter_filter_info_list[i].p_psfp_meter_filter_cfg = NULL; + } + + /* Clear module stops. */ + r_layer3_switch_module_start(); + + /* Reset COMA IP. */ + r_layer3_switch_reset_coma(); + + /* When a r_gptp instance is set, initialize it. */ + if (NULL != p_extend->p_gptp_instance) + { + p_extend->p_gptp_instance->p_api->open(p_extend->p_gptp_instance->p_ctrl, p_extend->p_gptp_instance->p_cfg); + } + + /* Configure destination ports of forwarding feature. */ + for (uint32_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + p_mfwd_fwpbfc_reg = + (uint32_t *) ((uintptr_t) &(R_MFWD->FWPBFC0) + (i * LAYER3_SWITCH_FWPBFC_REGISTER_OFFSET)); + *p_mfwd_fwpbfc_reg |= (R_MFWD_FWPBFC0_PBDV_Msk & p_extend->fowarding_target_port_masks[i]); + } + + /* Enable extended descriptor for each agents. */ + R_MFWD->FWPC10_b.DDE = 0x1; + R_MFWD->FWPC11_b.DDE = 0x1; + R_MFWD->FWPC12_b.DDE = 0x1; + + /* Set GWCA to CONFIG mode. */ + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_CONFIG); + + /* Reset AXI RAM. */ + p_instance_ctrl->p_gwca_reg->GWARIRM_b.ARIOG = 1; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_gwca_reg->GWARIRM_b.ARR, 1); + + /* Initialize LINKFIX table. */ + r_layer3_switch_initialize_linkfix_table(p_instance_ctrl); + + /* Set GWCA to OPERATION mode. */ + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_OPERATION); + + /* ETHA ports initialization. */ + for (uint8_t channel = 0; (channel < BSP_FEATURE_ETHER_NUM_CHANNELS) && (FSP_SUCCESS == phy_err); channel++) + { + if (NULL != p_extend->p_ether_phy_instances[channel]) + { + /* Change ETHA to CONFIG mode. */ + r_layer3_switch_update_etha_operation_mode(channel, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_etha_operation_mode(channel, LAYER3_SWITCH_AGENT_MODE_CONFIG); + + /* Configure the port specific feature. */ + if (NULL != p_extend->p_port_cfg_list[channel]) + { + r_layer3_switch_configure_port(p_instance_ctrl, channel, p_extend->p_port_cfg_list[channel]); + } + + /* Configure queue depth for each transmission IPV queue. */ + p_reg_etha = (R_ETHA0_Type *) (R_ETHA0_BASE + (LAYER3_SWITCH_ETHA_REG_SIZE * channel)); + p_etha_eatdqdcn_reg = &p_reg_etha->EATDQDC0; + for (uint8_t j = 0; j < BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM; j++) + { + *p_etha_eatdqdcn_reg = p_extend->ipv_queue_depth_list[channel][j] & R_ETHA0_EATDQDC0_DQD_Msk; + p_etha_eatdqdcn_reg += 1; + } + + /* Disable sending preemptable frames until verification is complete. */ + r_layer3_switch_enable_frame_preemption_feature(p_instance_ctrl, channel, false); + + /* Enable Magic packet detection. */ + p_reg_rmac = + (R_RMAC0_Type *) (R_RMAC0_BASE + (channel * LAYER3_SWITCH_RMAC_REG_SIZE)); + p_reg_rmac->MRGC_b.MPDE = 1; + + if (NULL != p_extend->p_gptp_instance) + { + p_reg_rmac->MTRC_b.DTN = (uint8_t) (p_extend->gptp_timer_numbers[channel] & 0x1); + } + } + } + + /* Open all ETHER_PHY instances. */ + for (uint8_t channel = 0; + (channel < BSP_FEATURE_ETHER_NUM_CHANNELS) && ((FSP_SUCCESS == phy_err) | (FSP_ERR_ALREADY_OPEN == phy_err)); + channel++) + { + p_ether_phy = p_extend->p_ether_phy_instances[channel]; + if (NULL != p_ether_phy) + { + p_ether_phy->p_api->open(p_ether_phy->p_ctrl, p_ether_phy->p_cfg); + + /* Add callback for PHY interrupts. */ + R_RMAC_PHY_CallbackSet(p_ether_phy->p_ctrl, + r_layer3_switch_rmac_phy_interrupts_callback, + p_instance_ctrl, + NULL); + } + } + + /* Start operation on ETHA ports. */ + for (uint8_t channel = 0; (channel < BSP_FEATURE_ETHER_NUM_CHANNELS) && (FSP_SUCCESS == phy_err); channel++) + { + p_ether_phy = p_extend->p_ether_phy_instances[channel]; + if (NULL != p_ether_phy) + { + /* Change ETHA to OPERATION mode. */ + r_layer3_switch_update_etha_operation_mode(channel, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_etha_operation_mode(channel, LAYER3_SWITCH_AGENT_MODE_OPERATION); + + /* Initialize each PHY LSI. */ + R_RMAC_PHY_ChipSelect(p_ether_phy->p_ctrl, channel); + phy_err = p_ether_phy->p_api->chipInit(p_ether_phy->p_ctrl, p_ether_phy->p_cfg); + if (phy_err != FSP_SUCCESS) + { + break; + } + + phy_err = p_ether_phy->p_api->startAutoNegotiate(p_ether_phy->p_ctrl); + } + } + + /* If failed to open a PHY instance, revert all configurations and return error. */ + if (FSP_SUCCESS != phy_err) + { + /* Close ETHA IP and other PHY instances. */ + r_layer3_switch_close_etha_ports(p_instance_ctrl); + + /* Disable GWCA. */ + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_DISABLE); + + /* Reset destination ports of forwarding feature. */ + for (uint32_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + p_mfwd_fwpbfc_reg = + (uint32_t *) ((uintptr_t) &(R_MFWD->FWPBFC0) + (i * LAYER3_SWITCH_FWPBFC_REGISTER_OFFSET)); + *p_mfwd_fwpbfc_reg = 0; + } + + /* Disable extended descriptor for each agents. */ + R_MFWD->FWPC10_b.DDE = 0; + R_MFWD->FWPC11_b.DDE = 0; + R_MFWD->FWPC12_b.DDE = 0; + + FSP_RETURN(FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION); + } + + /* Enable GWCA Data Interrupt IRQ. It occurs when a descriptor completes RX/TX or receive frame for a full queue. */ + R_BSP_IrqCfgEnable(p_instance_ctrl->p_cfg->irq, p_instance_ctrl->p_cfg->ipl, p_instance_ctrl); + if (p_extend->etha_error_irq_port_0 >= 0) + { + R_BSP_IrqCfgEnable(p_extend->etha_error_irq_port_0, p_extend->etha_error_ipl_port_0, p_instance_ctrl); + } + + if (p_extend->etha_error_irq_port_1 >= 0) + { + R_BSP_IrqCfgEnable(p_extend->etha_error_irq_port_1, p_extend->etha_error_ipl_port_1, p_instance_ctrl); + } + + p_instance_ctrl->open = LAYER3_SWITCH_OPEN; + + return FSP_SUCCESS; +} /* End of function R_LAYER3_SWITCH_Open() */ + +/********************************************************************************************************************//** + * @brief Disables interrupts and stop module. Implements @ref ether_switch_api_t::close. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN Control block is not open. + ***********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_Close (ether_switch_ctrl_t * const p_ctrl) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + layer3_switch_extended_cfg_t * p_extend; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_extend = (layer3_switch_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Disable GWCA Data Interrupt IRQ. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->irq, NULL); + + if (p_extend->etha_error_irq_port_0 >= 0) + { + R_BSP_IrqDisable(p_extend->etha_error_irq_port_0); + R_FSP_IsrContextSet(p_extend->etha_error_irq_port_0, NULL); + } + + if (p_extend->etha_error_irq_port_1 >= 0) + { + R_BSP_IrqDisable(p_extend->etha_error_irq_port_1); + R_FSP_IsrContextSet(p_extend->etha_error_irq_port_1, NULL); + } + + /* Close ETHA ports and PHY instances. */ + r_layer3_switch_close_etha_ports(p_instance_ctrl); + + /* When a r_gptp instance is set, close it. */ + if (NULL != p_extend->p_gptp_instance) + { + p_extend->p_gptp_instance->p_api->close(p_extend->p_gptp_instance->p_ctrl); + } + + /* Set GWCA to DISABLE mode. */ + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_DISABLE); + + /* Waiting for all pointers to be released. */ + FSP_HARDWARE_REGISTER_WAIT(R_COMA->CABPPCM_b.RPC, R_COMA->CABPPCM_b.TPC) + + /* Not set ESWM module stop feature because it shared with EtherCAT.*/ + + /* Reset instance ctrl members. */ + p_instance_ctrl->p_cfg = NULL; + memset(p_instance_ctrl->p_queues_status, 0, sizeof(p_instance_ctrl->p_queues_status)); + p_instance_ctrl->table_status = LAYER3_SWITCH_TABLE_STATUS_UNINITIALIZED; + + /* Mark the driver as closed. */ + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} /* End of function R_LAYER3_SWITCH_Close() */ + +/********************************************************************************************************************//** + * @brief Create a new descriptor queue and set it to LINKFIX table. + * This function must be called before calling @ref R_LAYER3_SWITCH_SetDescriptor and @ref R_LAYER3_SWITCH_GetDescriptor. + * + * @retval FSP_SUCCESS Descriptor created successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN Control block is not open. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_OUT_OF_MEMORY Descriptor queue list is depleted. + * @retval FSP_ERR_OVERFLOW TS descriptor queue is used. + ***********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_CreateDescriptorQueue (ether_switch_ctrl_t * const p_ctrl, + uint32_t * const p_queue_index, + const layer3_switch_descriptor_queue_cfg_t * const p_queue_cfg) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + uint32_t queue_index; + fsp_err_t err = FSP_SUCCESS; + + volatile uint32_t * p_gwca_gwdcc_reg; + volatile uint32_t * p_gwca_gwdie_reg; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_queue_index, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(NULL != p_queue_cfg, FSP_ERR_INVALID_POINTER); + if (LAYER3_SWITCH_DISCRIPTOR_FORMTAT_TX_TIMESTAMP == p_queue_cfg->descriptor_format) + { + FSP_ERROR_RETURN(NULL != p_queue_cfg->p_ts_descriptor_array, FSP_ERR_INVALID_POINTER); + } + else + { + FSP_ERROR_RETURN(NULL != p_queue_cfg->p_descriptor_array, FSP_ERR_INVALID_POINTER); + } +#endif + + if (LAYER3_SWITCH_DISCRIPTOR_FORMTAT_TX_TIMESTAMP == p_queue_cfg->descriptor_format) + { + err = r_layer3_switch_create_tx_timestamp_queue(p_instance_ctrl, p_queue_cfg, p_queue_index); + } + else + { + queue_index = p_instance_ctrl->allocated_descriptor_queue_index; + FSP_ERROR_RETURN(LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM > queue_index, FSP_ERR_OUT_OF_MEMORY); + + /* Set all descriptors of new queue as disable. */ + for (uint32_t i = 0; i < p_queue_cfg->array_length; i++) + { + p_queue_cfg->p_descriptor_array[i].basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY; + } + + /* Set the new queue to LINKFIX table. */ + p_instance_ctrl->p_descriptor_queue_list[queue_index].ptr_h = + (LAYER3_SWITCH_QUEUE_ADDRESS_UPPER_MASK & (uint64_t) (uintptr_t) p_queue_cfg->p_descriptor_array) >> + LAYER3_SWITCH_QUEUE_ADDRESS_UPPER_POSITION; + p_instance_ctrl->p_descriptor_queue_list[queue_index].ptr_l = + LAYER3_SWITCH_QUEUE_ADDRESS_LOWER_MASK & (uintptr_t) p_queue_cfg->p_descriptor_array; + p_instance_ctrl->p_descriptor_queue_list[queue_index].dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_LINKFIX; + + /* Configure the new queue.*/ + p_gwca_gwdcc_reg = &(p_instance_ctrl->p_gwca_reg->GWDCC0) + queue_index; + *p_gwca_gwdcc_reg = + (uint32_t) ((p_queue_cfg->write_back_mode << R_GWCA0_GWDCC0_SM_Pos) | + (p_queue_cfg->descriptor_format << R_GWCA0_GWDCC0_EDE_Pos) | + (p_queue_cfg->rx_timestamp_storage << R_GWCA0_GWDCC0_ETS_Pos) | + (p_queue_cfg->type << R_GWCA0_GWDCC0_DQT_Pos)); + + /* Enable GWCA Data Interrupt of this queue. */ + /* Get register address. Use GWDIE0 for queue 0-31, GWDIE1 for queue 32-63. */ + p_gwca_gwdie_reg = (uint32_t *) ((uintptr_t) &(p_instance_ctrl->p_gwca_reg->GWDIE0) + + ((queue_index / LAYER3_SWITCH_REGISTER_SIZE) * + LAYER3_SWITCH_INTERRUPT_REGISTER_OFFSET)); + + /* Set bit field of this queue. */ + *p_gwca_gwdie_reg = (*p_gwca_gwdie_reg) | (1 << (queue_index % LAYER3_SWITCH_REGISTER_SIZE)); + + /* Enable also Descriptor Full Error Interrupt. */ + p_gwca_gwdie_reg = (uint32_t *) ((uintptr_t) &(p_instance_ctrl->p_gwca_reg->GWEIE20) + + ((queue_index / LAYER3_SWITCH_REGISTER_SIZE) * + LAYER3_SWITCH_INTERRUPT_REGISTER_OFFSET)); + *p_gwca_gwdie_reg = (*p_gwca_gwdie_reg) | (1 << (queue_index % LAYER3_SWITCH_REGISTER_SIZE)); + + /* Initialize software queue status. */ + p_instance_ctrl->p_queues_status[queue_index].created = true; + p_instance_ctrl->p_queues_status[queue_index].head = 0; + p_instance_ctrl->p_queues_status[queue_index].tail = 0; + p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg = p_queue_cfg; + + /* Store queue index. */ + *p_queue_index = queue_index; + p_instance_ctrl->allocated_descriptor_queue_index += 1; + } + + return err; +} /* End of function R_LAYER3_SWITCH_CreateDescriptorQueue() */ + +/********************************************************************************************************************//** + * @brief Set descriptor data to a target descriptor. + * + * @retval FSP_SUCCESS Descriptor set successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN Control block is not open. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Queue index is invalid. + * @retval FSP_ERR_NOT_INITIALIZED This descriptor queue is not created. + * @retval FSP_ERR_IN_USE Target descriptor is now running. + * @retval FSP_ERR_OVERFLOW Descriptor queue is full. + ***********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_SetDescriptor (ether_switch_ctrl_t * const p_ctrl, + uint32_t queue_index, + layer3_switch_descriptor_t const * const p_descriptor) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + layer3_switch_descriptor_t * p_target_descriptor; + layer3_switch_descriptor_type_t active_descriptor_type; + fsp_err_t err = FSP_SUCCESS; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_descriptor, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM > queue_index, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_instance_ctrl->p_queues_status[queue_index].created, FSP_ERR_NOT_INITIALIZED); +#endif + + /* The last descriptor of the queue cannot be rewritten. */ + FSP_ERROR_RETURN(p_instance_ctrl->p_queues_status[queue_index].tail < + p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg->array_length - 1, + FSP_ERR_OVERFLOW); + + /* Get pointer to the target descriptor. */ + p_target_descriptor = + r_layer3_switch_get_descriptor(p_instance_ctrl, queue_index, + p_instance_ctrl->p_queues_status[queue_index].tail); + + /* Check the descriptor queue is in TX queue or RX queue. */ + if (LAYER3_SWITCH_QUEUE_TYPE_TX == p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg->type) + { + /* In TX queue, FSINGLE descriptor is active. */ + active_descriptor_type = LAYER3_SWITCH_DESCRIPTOR_TYPE_FSINGLE; + } + else /* When RX descriptor queue. */ + { + /* In RX queue, FEMPTY descriptor is active. */ + active_descriptor_type = LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY; + } + + /* Check if the target descriptor is active. Set is only permitted to a stopped descriptor. */ + if ((active_descriptor_type == p_target_descriptor->basic.dt) && + (LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY != p_descriptor->basic.dt)) + { + err = FSP_ERR_IN_USE; + } + else + { + /* Copy all fields in the descriptor. */ + memcpy(p_target_descriptor, p_descriptor, sizeof(layer3_switch_descriptor_t)); + p_instance_ctrl->p_queues_status[queue_index].tail += 1; + + /* RX queue become available. */ + if (LAYER3_SWITCH_QUEUE_TYPE_RX == p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg->type) + { + p_instance_ctrl->p_queues_status[queue_index].rx_available = true; + } + } + + return err; +} /* End of function R_LAYER3_SWITCH_SetDescriptor() */ + +/********************************************************************************************************************//** + * @brief Get descriptor data from a target descriptor. + * + * @retval FSP_SUCCESS Descriptor got successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN Control block is not open. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Queue index is invalid. + * @retval FSP_ERR_NOT_INITIALIZED This descriptor queue is not created or target descriptor is not set. + * @retval FSP_ERR_IN_USE Target descriptor is now running. + ***********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_GetDescriptor (ether_switch_ctrl_t * const p_ctrl, + uint32_t queue_index, + layer3_switch_descriptor_t * const p_descriptor) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + layer3_switch_descriptor_t * p_target_descriptor; + layer3_switch_descriptor_type_t active_descriptor_type; + fsp_err_t err = FSP_SUCCESS; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_descriptor, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM > queue_index, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_instance_ctrl->p_queues_status[queue_index].created, FSP_ERR_NOT_INITIALIZED); +#endif + + /* Get pointer to the target descriptor. */ + p_target_descriptor = + r_layer3_switch_get_descriptor(p_instance_ctrl, queue_index, + p_instance_ctrl->p_queues_status[queue_index].head); + + /* Check the descriptor queue is in TX queue or RX queue. */ + if (LAYER3_SWITCH_QUEUE_TYPE_TX == p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg->type) + { + /* In TX queue, FSINGLE descriptor is active. */ + active_descriptor_type = LAYER3_SWITCH_DESCRIPTOR_TYPE_FSINGLE; + } + else /* When RX descriptor queue. */ + { + /* In RX queue, FEMPTY descriptor is active. */ + active_descriptor_type = LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY; + } + + /* Check if the target descriptor is active. Get is only permitted to a stopped descriptor. */ + if (active_descriptor_type == p_target_descriptor->basic.dt) + { + err = FSP_ERR_IN_USE; + } + else if (LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY == p_target_descriptor->basic.dt) + { + err = FSP_ERR_NOT_INITIALIZED; + } + else + { + /* Copy the all descriptor fields to a argument.*/ + memcpy(p_descriptor, p_target_descriptor, sizeof(layer3_switch_descriptor_t)); + + p_instance_ctrl->p_queues_status[queue_index].head += 1; + } + + return err; +} /* End of function R_LAYER3_SWITCH_GetDescriptor() */ + +/********************************************************************************************************************//** + * @brief Reload and enable a descriptor queue. + * In a TX descriptor queue, the queue start transmission. In a RX descriptor queue, the queue start reception. + * + * @retval FSP_SUCCESS Descriptor queue started successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN Control block is not open. + * @retval FSP_ERR_INVALID_ARGUMENT Queue index is invalid. + * @retval FSP_ERR_NOT_INITIALIZED Target descriptor queue is not created. + * @retval FSP_ERR_IN_USE Target descriptor queue is already running. + * @retval FSP_ERR_INVALID_DATA Target TX queue have no data. + ***********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_StartDescriptorQueue (ether_switch_ctrl_t * const p_ctrl, uint32_t queue_index) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + + volatile uint32_t * p_gwca_gwdcc_reg; + volatile uint32_t * p_gwca_gwtrc_reg; + volatile uint32_t * p_mfwd_fwpbfcsdc0_reg; + layer3_switch_descriptor_t * p_descriptor; + fsp_err_t err = FSP_SUCCESS; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM > queue_index, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_instance_ctrl->p_queues_status[queue_index].created, FSP_ERR_NOT_INITIALIZED); +#endif + + /* The target descriptor queue should be stopped. */ + if (LAYER3_SWITCH_QUEUE_TYPE_RX == p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg->type) + { + /* RX queue should have been set a new buffer. */ + FSP_ERROR_RETURN(p_instance_ctrl->p_queues_status[queue_index].rx_available, FSP_ERR_IN_USE); + p_instance_ctrl->p_queues_status[queue_index].rx_available = false; + } + else + { + /* TX queue should have completed previous transmission. */ + FSP_ERROR_RETURN(!r_layer3_switch_is_descriptor_queue_active(p_instance_ctrl, queue_index), FSP_ERR_IN_USE); + + /* Reset descriptor index of this queue. */ + p_instance_ctrl->p_queues_status[queue_index].head = 0; + p_instance_ctrl->p_queues_status[queue_index].tail = 0; + + /* When the head of the queue has no data, do not start transmission. */ + p_descriptor = r_layer3_switch_get_descriptor(p_instance_ctrl, queue_index, 0); + FSP_ERROR_RETURN(LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY != p_descriptor->basic.dt, FSP_ERR_INVALID_DATA); + } + + /* Reload the queue. */ + p_gwca_gwdcc_reg = &(p_instance_ctrl->p_gwca_reg->GWDCC0) + queue_index; + *p_gwca_gwdcc_reg |= R_GWCA0_GWDCC0_BALR_Msk; + FSP_HARDWARE_REGISTER_WAIT((*p_gwca_gwdcc_reg & R_GWCA0_GWDCC0_BALR_Msk), 0); + + /* Check if target descriptor queue type is TX or RX. */ + if (LAYER3_SWITCH_QUEUE_TYPE_TX == p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg->type) + { + /* Get a pointer to GWTRCi register. Use GWTRC0 register for queue 0-31, GWTRC1 register for queue 32-63. */ + p_gwca_gwtrc_reg = &(p_instance_ctrl->p_gwca_reg->GWTRC0) + (queue_index / LAYER3_SWITCH_REGISTER_SIZE); + + /* Request to start transmission. */ + *p_gwca_gwtrc_reg = (*p_gwca_gwtrc_reg) | (1 << (queue_index % LAYER3_SWITCH_REGISTER_SIZE)); + } + else + { + /* When RX queue. */ + for (uint32_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + /* Get register address that depend on port number. */ + if (1 & (p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg->ports >> i)) + { + p_mfwd_fwpbfcsdc0_reg = (uint32_t *) ((uintptr_t) &(R_MFWD->FWPBFCSDC00) + + (LAYER3_SWITCH_FWPBFCSDC0_REGISTER_OFFSET * i)); + + /* Configure reception frame forwarding to the queue. */ + *p_mfwd_fwpbfcsdc0_reg = R_MFWD_FWPBFCSDC00_PBCSD_Msk & queue_index; + } + } + } + + /* Reset descriptor index of this queue. */ + p_instance_ctrl->p_queues_status[queue_index].head = 0; + p_instance_ctrl->p_queues_status[queue_index].tail = 0; + + return err; +} /* End of function R_LAYER3_SWITCH_StartDescriptorQueue() */ + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_CallbackSet (ether_switch_ctrl_t * const p_ctrl, + void ( * p_callback)(ether_switch_callback_args_t *), + void * const p_context, + ether_switch_callback_args_t * const p_callback_memory) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + + /* Get security state of p_callback. */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure. */ + ether_switch_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context. */ +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(ether_switch_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} /* End of function R_LAYER3_SWITCH_CallbackSet() */ + +/*******************************************************************************************************************//** + * Configure Ethernet port features, including callback function for each port. + * + * @retval FSP_SUCCESS Port configured successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Port number is invalid. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_ConfigurePort (ether_switch_ctrl_t * const p_ctrl, + uint8_t port, + layer3_switch_port_cfg_t * p_port_cfg) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(port < BSP_FEATURE_ETHER_NUM_CHANNELS, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_port_cfg, FSP_ERR_INVALID_POINTER); +#endif + + /* Change ETHA to CONFIG mode. */ + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_CONFIG); + + r_layer3_switch_configure_port(p_instance_ctrl, port, p_port_cfg); + + /* Change ETHA to OPERATION mode. */ + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_OPERATION); + + return FSP_SUCCESS; +} /* End of function R_LAYER3_SWITCH_ConfigurePort() */ + +/*******************************************************************************************************************//** + * Add or update an entry of the forwarding table. + * + * @retval FSP_SUCCESS Successfully add/updated an entry into the table. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_OVERFLOW The number of unsecure entries exceeded the configured value. + * @retval FSP_ERR_WRITE_FAILED A hardware error occurred while learning the entry. + * @retval FSP_ERR_INVALID_ARGUMENT Target frame or entry type is invalid. + * @retval FSP_ERR_INVALID_MODE VLAN feature is disabled and a VLAN entry is passed. + * @retval FSP_ERR_BUFFER_EMPTY PSFP MSDU or Meter filter ID is invalid. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_AddTableEntry (ether_switch_ctrl_t * const p_ctrl, + layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t const * const p_entry_cfg) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_target_frame, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(p_entry_cfg, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(LAYER3_SWITCH_TABLE_STATUS_INITIALIZED == p_instance_ctrl->table_status, FSP_ERR_NOT_INITIALIZED); + FSP_ERROR_RETURN(LAYER3_SWITCH_TABLE_ENTRY_TYPE_EMPTY != p_target_frame->entry_type, FSP_ERR_INVALID_ARGUMENT); +#endif + + switch (p_target_frame->entry_type) + { + case LAYER3_SWITCH_TABLE_ENTRY_TYPE_MAC: + { + err = r_layer3_switch_learn_mac_entry(p_target_frame, p_entry_cfg); + break; + } + + case LAYER3_SWITCH_TABLE_ENTRY_TYPE_VLAN: + { + err = r_layer3_switch_learn_vlan_entry(p_target_frame, p_entry_cfg); + break; + } + + case LAYER3_SWITCH_TABLE_ENTRY_TYPE_LAYER3: + { + err = r_layer3_switch_learn_l3_entry(p_instance_ctrl, p_target_frame, p_entry_cfg); + break; + } + + default: + { + break; + } + } + + return err; +} /* End of function R_LAYER3_SWITCH_AddTableEntry() */ + +/*******************************************************************************************************************//** + * Search an entry from the forwarding table. + * + * @retval FSP_SUCCESS The entry is found successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_NOT_FOUND The entry is not found in the table. + * @retval FSP_ERR_INVALID_ARGUMENT Target frame or entry type is invalid. + * @retval FSP_ERR_INVALID_MODE VLAN feature is disabled and a VLAN entry is passed. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_SearchTableEntry (ether_switch_ctrl_t * const p_ctrl, + layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t * const p_entry_cfg) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_target_frame, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(p_entry_cfg, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(LAYER3_SWITCH_TABLE_STATUS_INITIALIZED == p_instance_ctrl->table_status, FSP_ERR_NOT_INITIALIZED); + FSP_ERROR_RETURN(LAYER3_SWITCH_TABLE_ENTRY_TYPE_EMPTY != p_target_frame->entry_type, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + switch (p_target_frame->entry_type) + { + case LAYER3_SWITCH_TABLE_ENTRY_TYPE_MAC: + { + err = r_layer3_switch_search_mac_entry(p_target_frame, p_entry_cfg); + break; + } + + case LAYER3_SWITCH_TABLE_ENTRY_TYPE_VLAN: + { + err = r_layer3_switch_search_vlan_entry(p_target_frame, p_entry_cfg); + break; + } + + case LAYER3_SWITCH_TABLE_ENTRY_TYPE_LAYER3: + { + err = r_layer3_switch_search_l3_entry(p_target_frame, p_entry_cfg); + break; + } + + default: + { + break; + } + } + + return err; +} /* End of function R_LAYER3_SWITCH_SearchTableEntry() */ + +/*******************************************************************************************************************//** + * Configure and initialize an forwarding table. + * + * @retval FSP_SUCCESS Table configured successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_WRITE_FAILED Failed to add entries. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_ConfigureTable (ether_switch_ctrl_t * const p_ctrl, + layer3_switch_table_cfg_t const * const p_table_cfg) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_table_cfg, FSP_ERR_INVALID_POINTER); +#endif + + /* Set VLAN mode. */ + R_MFWD->FWGC_b.SVM = p_table_cfg->vlan_mode; + + /* Reset table. */ + r_layer3_switch_reset_table(p_instance_ctrl); + p_instance_ctrl->table_status = LAYER3_SWITCH_TABLE_STATUS_INITIALIZED; + + /* Set maximum number of unsecure entries. */ + R_MFWD->FWMACHEC = (uint32_t) (R_MFWD_FWMACHEC_MACHMC_Msk & (7) << R_MFWD_FWMACHEC_MACHMC_Pos) | + (uint32_t) (R_MFWD_FWMACHEC_MACHMUE_Msk & + (p_table_cfg->unsecure_entry_maximum_num) << + R_MFWD_FWMACHEC_MACHMUE_Pos); + R_MFWD->FWVLANTEC = (p_table_cfg->unsecure_entry_maximum_num << R_MFWD_FWVLANTEC_VLANTMUE_Pos) & + (R_MFWD_FWVLANTEC_VLANTMUE_Msk); + R_MFWD->FWLTHHEC = (p_table_cfg->unsecure_entry_maximum_num << R_MFWD_FWLTHHEC_LTHHMUE_Pos) & + (R_MFWD_FWLTHHEC_LTHHMUE_Msk); + + /* Initialize FRER parameters. */ + err = r_layer3_switch_frer_init(p_instance_ctrl, &p_table_cfg->frer_cfg); + FSP_ASSERT(FSP_SUCCESS == err); + + /* Configure each port. */ + for (uint8_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS + 1; i++) + { + r_layer3_switch_configure_forwarding_port(&p_table_cfg->port_cfg_list[i], i); + + /* Configure VLAN ingress/egress mode. */ + r_layer3_switch_initialize_vlan_port(p_instance_ctrl, &p_table_cfg->port_cfg_list[i], i); + } + + /* Configure MAC table aging. */ + if (p_table_cfg->mac_entry_aging_enable) + { + r_layer3_switch_enable_mac_table_aging((uint16_t) p_table_cfg->mac_entry_aging_time_sec); + } + + /* Configure Layer3 table stream filter. */ + r_layer3_switch_configure_stream_filter(&p_table_cfg->l3_stream_filter_cfg); + + /* When an table is passed, learn all entries. */ + if (NULL != p_table_cfg->p_table) + { + /* Learn MAC entries. */ + for (uint32_t i = 0; (i < p_table_cfg->p_table->mac_list_length) & (FSP_SUCCESS == err); i++) + { + err = R_LAYER3_SWITCH_AddTableEntry(p_instance_ctrl, + &p_table_cfg->p_table->p_mac_entry_list[i].target_frame, + &p_table_cfg->p_table->p_mac_entry_list[i].entry_cfg); + } + + /* Learn VLAN entries. */ + for (uint32_t i = 0; (i < p_table_cfg->p_table->vlan_list_length) & (FSP_SUCCESS == err); i++) + { + err = R_LAYER3_SWITCH_AddTableEntry(p_instance_ctrl, + &p_table_cfg->p_table->p_vlan_entry_list[i].target_frame, + &p_table_cfg->p_table->p_vlan_entry_list[i].entry_cfg); + } + + /* Learn Layer3 entries. */ + for (uint32_t i = 0; (i < p_table_cfg->p_table->l3_list_length) & (FSP_SUCCESS == err); i++) + { + err = R_LAYER3_SWITCH_AddTableEntry(p_instance_ctrl, + &p_table_cfg->p_table->p_vlan_entry_list[i].target_frame, + &p_table_cfg->p_table->p_l3_entry_list[i].entry_cfg); + } + } + + if (FSP_SUCCESS != err) + { + /* When an error occurs, remove entries and return the error. */ + r_layer3_switch_reset_table(p_instance_ctrl); + err = FSP_ERR_WRITE_FAILED; + } + + return err; +} /* End of function R_LAYER3_SWITCH_ConfigureTable() */ + +/*******************************************************************************************************************//** + * Get a pointer to the forwarding table. + * + * @retval FSP_SUCCESS Table got successfully. + * @retval FSP_ERR_ASSERTION Pointer to control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_INVALID_MODE VLAN feature is disabled and a VLAN entry list is passed. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_GetTable (ether_switch_ctrl_t * const p_ctrl, layer3_switch_table_t * const p_table) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + layer3_switch_extended_cfg_t * p_extend; + fsp_err_t err = FSP_SUCCESS; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_table, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(LAYER3_SWITCH_TABLE_STATUS_INITIALIZED == p_instance_ctrl->table_status, FSP_ERR_NOT_INITIALIZED); +#endif + + /* Initialize lengths. */ + p_table->mac_list_length = 0; + p_table->vlan_list_length = 0; + p_table->l3_list_length = 0; + + /* Read all MAC entries. */ + if (NULL != p_table->p_mac_entry_list) + { + for (uint16_t i = 0; + (i < LAYER3_SWITCH_MAC_ENTRY_MAX_NUM) && ((FSP_SUCCESS == err) || (FSP_ERR_NOT_FOUND == err)); + i++) + { + err = r_layer3_switch_read_mac_entry(i, &p_table->p_mac_entry_list[p_table->mac_list_length]); + if (FSP_SUCCESS == err) + { + p_table->mac_list_length += 1; + } + } + } + + /* Read all VLAN entries. */ + if ((NULL != p_table->p_vlan_entry_list) && ((FSP_SUCCESS == err) || (FSP_ERR_NOT_FOUND == err))) + { + for (uint16_t i = 1; + (i < LAYER3_SWITCH_VLAN_ENTRY_MAX_NUM) && ((FSP_SUCCESS == err) || (FSP_ERR_NOT_FOUND == err)); + i++) + { + err = r_layer3_switch_read_vlan_entry(i, &p_table->p_vlan_entry_list[p_table->vlan_list_length]); + if (FSP_SUCCESS == err) + { + p_table->vlan_list_length += 1; + } + } + } + + /* Read all L3 entries. */ + if ((NULL != p_table->p_l3_entry_list) && ((FSP_SUCCESS == err) || (FSP_ERR_NOT_FOUND == err))) + { + p_extend = (layer3_switch_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + for (uint16_t i = 0; + (i < p_extend->l3_filter_list_length) && ((FSP_SUCCESS == err) || (FSP_ERR_NOT_FOUND == err)); + i++) + { + err = + r_layer3_switch_search_l3_entry(&p_extend->l3_filter_list[i].frame, + &p_table->p_l3_entry_list[p_table->l3_list_length].entry_cfg); + if (FSP_SUCCESS == err) + { + p_table->p_l3_entry_list[p_table->l3_list_length].target_frame = p_extend->l3_filter_list[i].frame; + p_table->l3_list_length += 1; + } + } + } + + if (FSP_ERR_NOT_FOUND == err) + { + /* When entries are not found, it is acceptable. */ + err = FSP_SUCCESS; + } + + return err; +} /* End of function R_LAYER3_SWITCH_GetTable() */ + +/*******************************************************************************************************************//** + * Configure Time Aware Shaper feature. + * + * @retval FSP_SUCCESS TAS configure successfully. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER Pointer to a argument is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Port number is invalid. + * @retval FSP_ERR_UNSUPPORTED TAS feature is not enabled in the configuration. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_ConfigureTAS (ether_switch_ctrl_t * const p_ctrl, + uint8_t port, + layer3_switch_tas_cfg_t * p_tas_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + +#if LAYER3_SWITCH_CFG_TAS_ENABLE + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + uint8_t tas_entry_addr; + uint8_t learn_count = 0; + R_ETHA0_Type * p_etha_reg; + volatile uint32_t * p_eatasenc_reg; + uint32_t initial_gate_state_bitmask = 0; + + #if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(port < BSP_FEATURE_ETHER_NUM_CHANNELS, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(NULL != p_tas_cfg, FSP_ERR_INVALID_POINTER); + #else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #endif + + p_etha_reg = (R_ETHA0_Type *) (R_ETHA0_BASE + (LAYER3_SWITCH_ETHA_REG_SIZE * port)); + + /* Enable TAS gate error interrupt. */ + p_etha_reg->EAEIE1 |= (R_ETHA0_EAEIE1_TASGEE0_Msk | R_ETHA0_EAEIE1_TASGEE1_Msk | + R_ETHA0_EAEIE1_TASGEE2_Msk | R_ETHA0_EAEIE1_TASGEE3_Msk | R_ETHA0_EAEIE1_TASGEE4_Msk | + R_ETHA0_EAEIE1_TASGEE5_Msk | R_ETHA0_EAEIE1_TASGEE6_Msk | R_ETHA0_EAEIE1_TASGEE7_Msk); + + /* Initialize TAS RAM. */ + p_etha_reg->EATASRIRM_b.TASRIOG = 1U; + FSP_HARDWARE_REGISTER_WAIT(p_etha_reg->EATASRIRM_b.TASRR, 1); + + /* Wait until TAS Configuration becomes available. */ + FSP_HARDWARE_REGISTER_WAIT(p_etha_reg->EATASC_b.TASCI, 0); + + /* Set entry count and the initial state of each gate. */ + tas_entry_addr = p_etha_reg->EATASC_b.TASCA; + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM; i++) + { + p_eatasenc_reg = &p_etha_reg->EATASENC0 + i; + *p_eatasenc_reg = ((p_tas_cfg->gate_cfg_list[i].tas_entry_num - 1) & R_ETHA0_EATASCTENC_TASCTAEN_Msk); + + initial_gate_state_bitmask |= (uint8_t) (p_tas_cfg->gate_cfg_list[i].initial_gate_state << i); + } + + p_etha_reg->EATASIGSC = initial_gate_state_bitmask & LAYER3_SWITCH_EATASIGSC_MASK; + + /* Set cycle start time and span. */ + p_etha_reg->EATASCSTC0_b.TASACSTP0 = (p_tas_cfg->cycle_time_start_low); + p_etha_reg->EATASCSTC1_b.TASACSTP1 = (p_tas_cfg->cycle_time_start_high); + p_etha_reg->EATASCTC_b.TASACT = (p_tas_cfg->cycle_time); + + /* Learning TAS gate entries. */ + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM; i++) + { + for (uint8_t learn_port_cnt = 0; + learn_port_cnt < p_tas_cfg->gate_cfg_list[i].tas_entry_num; + learn_port_cnt++) + { + layer3_switch_tas_entry_t * p_learn_entry = + (p_tas_cfg->gate_cfg_list[i].p_tas_entry_list + learn_port_cnt); + + p_etha_reg->EATASGL0_b.TASGAL = (tas_entry_addr + learn_count); + p_etha_reg->EATASGL1 = + ((p_learn_entry->time << R_ETHA0_EATASGL1_TASGTL_Pos) & R_ETHA0_EATASGL1_TASGTL_Msk) | + ((uint32_t) (p_learn_entry->state << R_ETHA0_EATASGL1_TASGSL_Pos) & + R_ETHA0_EATASGL1_TASGSL_Msk); + FSP_HARDWARE_REGISTER_WAIT(p_etha_reg->EATASGLR_b.GL, 0); + + learn_count++; + } + } + + /* Set gPTP timer number. */ + p_etha_reg->EATASC_b.TASTS = (uint32_t) (p_tas_cfg->gptp_timer_number & 0x01); + + /* When the TAS operation is already enabled, apply the configuration. */ + if (p_etha_reg->EATASC_b.TASE == 1) + { + p_etha_reg->EATASC |= R_ETHA0_EATASC_TASE_Msk | R_ETHA0_EATASC_TASCC_Msk; + } + +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + FSP_PARAMETER_NOT_USED(p_tas_cfg); + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} /* End of function R_LAYER3_SWITCH_ConfigureTAS() */ + +/*******************************************************************************************************************//** + * Enable Time Aware Shaper feature. + * + * @retval FSP_SUCCESS TAS enabled successfully. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT Port number is invalid. + * @retval FSP_ERR_UNSUPPORTED TAS feature is not enabled in the configuration. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_EnableTAS (ether_switch_ctrl_t * const p_ctrl, uint8_t port) +{ + fsp_err_t err = FSP_SUCCESS; +#if LAYER3_SWITCH_CFG_TAS_ENABLE + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + #if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(port < BSP_FEATURE_ETHER_NUM_CHANNELS, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(LAYER3_SWITCH_CFG_TAS_ENABLE, FSP_ERR_UNSUPPORTED); + #else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #endif + R_ETHA0_Type * p_etha_reg = (R_ETHA0_Type *) (R_ETHA0_BASE + (LAYER3_SWITCH_ETHA_REG_SIZE * port)); + + /* Enable TAS feature if it is disabled. */ + p_etha_reg->EATASC |= R_ETHA0_EATASC_TASE_Msk; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(port); + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} /* End of function R_LAYER3_SWITCH_EnableTAS() */ + +/*******************************************************************************************************************//** + * Clear error status bit of throttle mode. + * + * @retval FSP_SUCCESS Status bit cleared successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_LAYER3_SWITCH_PsfpClearErrorStatus (ether_switch_ctrl_t * const p_ctrl, + layer3_switch_psfp_error_status_bitmask_t bitmasks) +{ + uint32_t target_bit_value = 0; + uint32_t write_value = 0; + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(LAYER3_SWITCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear PSFP MSDU filter status. */ + if (0 != bitmasks.msdu_filter_bitmask) + { + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM; i++) + { + target_bit_value = (1UL & (bitmasks.msdu_filter_bitmask >> i)); + write_value |= (target_bit_value << p_instance_ctrl->psfp_msdu_filter_info_list[i].msdu_filter_hw_id); + } + + R_MFWD->FWEIS2_b.PMFS = (uint16_t) write_value; + } + + /* Clear PSFP Meter filter status. */ + write_value = 0; + + if (0 != bitmasks.meter_filter_bitmask) + { + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM; i++) + { + target_bit_value = (1UL & (bitmasks.meter_filter_bitmask >> i)); + write_value |= (target_bit_value << p_instance_ctrl->psfp_meter_filter_info_list[i].meter_filter_hw_id); + } + + R_MFWD->FWEIS5_b.PMRFS = write_value; + } + + return FSP_SUCCESS; +} /* End of function R_LAYER3_SWITCH_PsfpClearErrorStatus() */ + +/*******************************************************************************************************************//** + * @} (end addtogroup LAYER3_SWITCH) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Clear module stop and turn on the domain power of the ESWM IP. + ***********************************************************************************************************************/ +static void r_layer3_switch_module_start (void) +{ + /* Disable protect of the power domain control. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Turn on the domain power. */ + if ((0 == R_SYSTEM->PDCTRESWM_b.PDCSF) && (1 == R_SYSTEM->PDCTRESWM_b.PDPGSF)) + { + R_SYSTEM->PDCTRESWM_b.PDDE = 0; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->PDCTRESWM_b.PDCSF, 0); + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->PDCTRESWM_b.PDPGSF, 0); + } + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Clear Ether-PHY clock Module Stop. */ + R_MSTP->MSTPCRC_b.MSTPC28 = 0; + + /* Clear Layer 3 Ethernet Switch Module Module Stop. */ + R_MSTP->MSTPCRC_b.MSTPC30 = 0; + + /* Waiting for module start. */ + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS); +} /* End of function r_layer3_switch_module_start() */ + +/*********************************************************************************************************************** + * Reset COMA IP. + ***********************************************************************************************************************/ +static void r_layer3_switch_reset_coma (void) +{ + /* Reset ESWM IP. */ + R_COMA->RRC_b.RR = 1; + R_COMA->RRC_b.RR = 0; + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS); + + /* Enable switch clock. */ + R_COMA->RCEC_b.RCE = 1; + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS); + + /* Reset COMA buffer pool. */ + R_COMA->CABPIRM_b.BPIOG = 1; + FSP_HARDWARE_REGISTER_WAIT(R_COMA->CABPIRM_b.BPR, 1); + + /* Waiting for COMA reset. */ + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS); + + /* Enable all agent clock. */ + R_COMA->RCEC = R_COMA_RCEC_RCE_Msk | R_COMA_RCEC_ACE_Msk; +} /* End of function r_layer3_switch_reset_coma() */ + +/*********************************************************************************************************************** + * Close ETHA ports with PHY instance. + * + * @param[in] p_instance_ctrl Pointer to a instance ctrl + ***********************************************************************************************************************/ +static void r_layer3_switch_close_etha_ports (layer3_switch_instance_ctrl_t * p_instance_ctrl) +{ + layer3_switch_extended_cfg_t * p_extend = (layer3_switch_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + ether_phy_instance_t const * p_ether_phy; + + /* Disable ETHA ports. */ + for (uint8_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + p_ether_phy = p_extend->p_ether_phy_instances[i]; + if (NULL != p_ether_phy) + { + /* Change ETHA to DISABLE mode. */ + r_layer3_switch_update_etha_operation_mode(i, LAYER3_SWITCH_AGENT_MODE_DISABLE); + + /* Close a ETHER_PHY instance. */ + p_ether_phy->p_api->close(p_ether_phy->p_ctrl); + } + } +} /* End of function r_layer3_switch_close_etha_ports() */ + +/*********************************************************************************************************************** + * Initialize LINKFIX table as queue disabled. + * + * @param[in] p_instance_ctrl Pointer to a instance control + ***********************************************************************************************************************/ +static void r_layer3_switch_initialize_linkfix_table (layer3_switch_instance_ctrl_t * p_instance_ctrl) +{ + layer3_switch_basic_descriptor_t * p_linkfix_descriptor; + + /* Initialize descriptor queue index. */ + p_instance_ctrl->allocated_descriptor_queue_index = 0; + + /* Initialize all LINKFIX descriptors in the LINKFIX table. */ + for (uint32_t i = 0; i < LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM; i++) + { + p_linkfix_descriptor = &p_instance_ctrl->p_descriptor_queue_list[i]; + + /* Initialize descriptor by 0. */ + memset(p_linkfix_descriptor, 0, sizeof(layer3_switch_basic_descriptor_t)); + + /* Set descriptor type as LEMPTY that mean disable queue. */ + p_linkfix_descriptor->dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY; + } + + /* Set link fix table address. */ + p_instance_ctrl->p_gwca_reg->GWDCBAC0 = + (LAYER3_SWITCH_QUEUE_ADDRESS_UPPER_MASK & (uint64_t) (uintptr_t) p_instance_ctrl->p_descriptor_queue_list) >> + LAYER3_SWITCH_QUEUE_ADDRESS_UPPER_POSITION; + p_instance_ctrl->p_gwca_reg->GWDCBAC1 = R_GWCA0_GWDCBAC1_DCBADP_Msk & + (uintptr_t) p_instance_ctrl->p_descriptor_queue_list; +} /* End of function r_layer3_switch_initialize_linkfix_table() */ + +/*********************************************************************************************************************** + * Return a descriptor at descriptor_index in the queue. + * + * @param[in] p_instance_ctrl Pointer to a instance control + * @param[in] queue_index Index of the queue + * @param[in] descriptor_index Index of the descriptor + ***********************************************************************************************************************/ +static layer3_switch_descriptor_t * r_layer3_switch_get_descriptor (layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t queue_index, + uint32_t descriptor_index) +{ + layer3_switch_basic_descriptor_t * p_linkfix_descriptor; + layer3_switch_descriptor_t * p_queue_head_descriptor; + + p_linkfix_descriptor = &p_instance_ctrl->p_descriptor_queue_list[queue_index]; + p_queue_head_descriptor = (layer3_switch_descriptor_t *) p_linkfix_descriptor->ptr_l; + + return &p_queue_head_descriptor[descriptor_index]; +} /* End of function r_layer3_switch_get_descriptor() */ + +/*********************************************************************************************************************** + * Return a descriptor that now processed by hardware in the queue. + * + * @param[in] p_instance_ctrl Pointer to a instance control + * @param[in] queue_index Index of the queue + ***********************************************************************************************************************/ +static layer3_switch_descriptor_t * r_layer3_switch_get_current_descriptor ( + layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t queue_index) +{ + /* Set dummy value to clear AXI searching address. */ + p_instance_ctrl->p_gwca_reg->GWAARSS_b.AARA = R_GWCA0_GWAARSS_AARA_Msk & (queue_index + 1); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_gwca_reg->GWAARSR0_b.AARS, 0); + + /* Get descriptor address that hardware use now. */ + p_instance_ctrl->p_gwca_reg->GWAARSS_b.AARA = R_GWCA0_GWAARSS_AARA_Msk & queue_index; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_gwca_reg->GWAARSR0_b.AARS, 0); + + return (layer3_switch_descriptor_t *) p_instance_ctrl->p_gwca_reg->GWAARSR1; +} /* End of function r_layer3_switch_get_current_descriptor() */ + +/*********************************************************************************************************************** + * Check if the descriptor queue is active. If active, return true. + * + * @param[in] p_instance_ctrl Pointer to a instance control + * @param[in] queue_index Index of the queue + ***********************************************************************************************************************/ +static bool r_layer3_switch_is_descriptor_queue_active (layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t queue_index) +{ + volatile layer3_switch_descriptor_t * p_current_descriptor; + bool active = false; + + /* Check the target descriptor queue type is TX or RX.*/ + if (LAYER3_SWITCH_QUEUE_TYPE_TX == p_instance_ctrl->p_queues_status[queue_index].p_queue_cfg->type) + { + /* In TX queue, the GWTRCi register indicates whether the queue is active. Use GWTRC0 for queue 0-31, GWTRC1 for queue 32-63. */ + if (*(&(p_instance_ctrl->p_gwca_reg->GWTRC0) + (queue_index / LAYER3_SWITCH_REGISTER_SIZE)) & + (1 << (queue_index % LAYER3_SWITCH_REGISTER_SIZE))) + { + active = true; + } + } + else /* When RX descriptor queue. */ + { + p_current_descriptor = r_layer3_switch_get_current_descriptor(p_instance_ctrl, queue_index); + + if (NULL == p_current_descriptor) + { + /* When the pointer is NULL, this queue is not started. */ + active = false; + } + else if (&p_instance_ctrl->p_descriptor_queue_list[queue_index] == (void *) p_current_descriptor) + { + active = false; + } + else + { + /* When the current descriptor is LINKFIX, checking the next descriptor. */ + while (LAYER3_SWITCH_DESCRIPTOR_TYPE_LINKFIX == p_current_descriptor->basic.dt) + { + p_current_descriptor = (layer3_switch_descriptor_t *) p_current_descriptor->basic.ptr_l; + } + + if ((LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY == p_current_descriptor->basic.dt) || + (LAYER3_SWITCH_DESCRIPTOR_TYPE_FSINGLE == p_current_descriptor->basic.dt)) + { + /* When the current descriptor is LEMPTY or FSINGLE, this queue has reached its end. */ + active = false; + } + else + { + active = true; + } + } + } + + return active; +} /* End of function r_layer3_switch_is_descriptor_queue_active() */ + +/*********************************************************************************************************************** + * Change operation mode of GWCA. + * + * @param[in] p_instance_ctrl Pointer to a instance control + * @param[in] mode New operation mode + ***********************************************************************************************************************/ +static void r_layer3_switch_update_gwca_operation_mode (layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_agent_mode_t mode) +{ + if (NULL != p_instance_ctrl) + { + /* Mode transition. */ + p_instance_ctrl->p_gwca_reg->GWMC_b.OPC = R_GWCA0_GWMC_OPC_Msk & mode; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_gwca_reg->GWMS_b.OPS, mode); + } +} /* End of function r_layer3_switch_update_gwca_operation_mode() */ + +/*********************************************************************************************************************** + * Change operation mode of ETHA. + * + * @param[in] mode New operation mode + ***********************************************************************************************************************/ +static void r_layer3_switch_update_etha_operation_mode (uint8_t port, layer3_switch_agent_mode_t mode) +{ + R_ETHA0_Type * p_etha_reg = (R_ETHA0_Type *) (R_ETHA0_BASE + (LAYER3_SWITCH_ETHA_REG_SIZE * port)); + + /* Mode transition. */ + p_etha_reg->EAMC_b.OPC = R_ETHA0_EAMC_OPC_Msk & mode; + FSP_HARDWARE_REGISTER_WAIT(p_etha_reg->EAMS_b.OPS, mode); +} /* End of function r_layer3_switch_update_etha_operation_mode() */ + +/******************************************************************************************************************* + * Configure MAC address of a ETHA port. + * + * @param[in] p_mac_address Pointer to a MAC address + * @param[in] port The target port + **********************************************************************************************************************/ +static void r_layer3_switch_configure_mac_address (uint8_t * p_mac_address, uint8_t port) +{ + R_RMAC0_Type * p_reg_rmac = (R_RMAC0_Type *) (R_RMAC0_BASE + port * LAYER3_SWITCH_RMAC_REG_SIZE); + uint32_t mac_h; + uint32_t mac_l; + + if (NULL != p_mac_address) + { + mac_h = + ((((uint32_t) p_mac_address[0] << 8)) | (uint32_t) p_mac_address[1]); + + mac_l = (((uint32_t) p_mac_address[2] << 24) | ((uint32_t) p_mac_address[3] << 16) | + ((uint32_t) p_mac_address[4] << 8) | (uint32_t) p_mac_address[5]); + + p_reg_rmac->MRMAC0 = mac_h; + p_reg_rmac->MRMAC1 = mac_l; + } +} /* End of function r_layer3_switch_configure_mac_address() */ + +/******************************************************************************************************************* + * Configure the port specific features. + **********************************************************************************************************************/ +static void r_layer3_switch_configure_port (layer3_switch_instance_ctrl_t * const p_instance_ctrl, + uint8_t port, + layer3_switch_port_cfg_t const * const p_port_cfg) +{ + volatile uint32_t * p_mfwd_fwpbfc_reg; + + /* Copy callback settings to the control member. */ + p_instance_ctrl->p_port_cfg_list[port].p_callback = p_port_cfg->p_callback; + p_instance_ctrl->p_port_cfg_list[port].p_context = p_port_cfg->p_context; + p_instance_ctrl->p_port_cfg_list[port].p_callback_memory = p_port_cfg->p_callback_memory; + + /* Configure MAC address. */ + r_layer3_switch_configure_mac_address(p_port_cfg->p_mac_address, port); + + p_mfwd_fwpbfc_reg = + (uint32_t *) ((uintptr_t) &(R_MFWD->FWPBFC0) + (port * LAYER3_SWITCH_FWPBFC_REGISTER_OFFSET)); + if (p_port_cfg->forwarding_to_cpu_enable) + { + *p_mfwd_fwpbfc_reg |= (R_MFWD_FWPBFC0_PBDV_Msk & (uint32_t) (LAYER3_SWITCH_PORT_CPU_BITMASK)); + } + else + { + /* Disable forwarding to CPU. But forwarding from the LAN port to the LAN port is still enabled. */ + *p_mfwd_fwpbfc_reg &= (R_MFWD_FWPBFC0_PBDV_Msk & (uint32_t) (~LAYER3_SWITCH_PORT_CPU_BITMASK)); + } + + if (NULL != p_port_cfg->p_cbs_cfg) + { + r_layer3_switch_configure_cbs(p_instance_ctrl, port, p_port_cfg->p_cbs_cfg); + } +} /* End of function r_layer3_switch_configure_port() */ + +/******************************************************************************************************************* + * Set forwarding configuration of the target port. This configuration includes enable forwarding and reject unknown frame. + * + * @param[in] p_port_cfg Pointer to a port dependent configuration + * @param[in] port The target port + **********************************************************************************************************************/ +static void r_layer3_switch_configure_forwarding_port (layer3_switch_forwarding_port_cfg_t const * const p_port_cfg, + uint8_t port) +{ + uint32_t * p_mfwd_fwpc0_reg = + (uint32_t *) ((uintptr_t) (&R_MFWD->FWPC00) + (port * LAYER3_SWITCH_PORT_CONFIG_REGISTER_OFFSET)); + uint32_t fwpc0_value = *p_mfwd_fwpc0_reg; + + /* Set VLAN configuration. */ + if (p_port_cfg->vlan_table_enable) + { + fwpc0_value |= R_MFWD_FWPC00_VLANSA_Msk; + } + + if (p_port_cfg->vlan_reject_unknown) + { + fwpc0_value |= (R_MFWD_FWPC00_VLANRU_Msk | R_MFWD_FWPC00_VLANRUS_Msk); + } + + /* Set MAC configuration. */ + if (p_port_cfg->mac_table_enable) + { + fwpc0_value |= (R_MFWD_FWPC00_MACDSA_Msk | R_MFWD_FWPC00_MACSSA_Msk); + } + + if (p_port_cfg->mac_reject_unknown) + { + fwpc0_value |= + (R_MFWD_FWPC00_MACRUDA_Pos | R_MFWD_FWPC00_MACRUDSA_Pos | R_MFWD_FWPC00_MACRUSA_Pos | + R_MFWD_FWPC00_MACRUSSA_Pos); + } + + if (p_port_cfg->mac_hardware_learning_enable) + { + fwpc0_value |= (R_MFWD_FWPC00_MACHLA_Msk | R_MFWD_FWPC00_MACHMA_Msk); + } + + /* Set layer3 configuration. */ + if (p_port_cfg->layer3_table_enable) + { + fwpc0_value |= R_MFWD_FWPC00_LTHTA_Msk; + } + + if (p_port_cfg->layer3_ipv4_filter_enable) + { + fwpc0_value |= R_MFWD_FWPC00_IP4UE_Msk | R_MFWD_FWPC00_IP4TE_Msk | R_MFWD_FWPC00_IP4OE_Msk; + } + + if (p_port_cfg->layer3_ipv6_filter_enable) + { + fwpc0_value |= R_MFWD_FWPC00_IP6UE_Msk | R_MFWD_FWPC00_IP6TE_Msk | R_MFWD_FWPC00_IP6OE_Msk; + } + + if (p_port_cfg->layer3_l2_filter_enable) + { + fwpc0_value |= R_MFWD_FWPC00_L2SE_Msk; + } + + if (p_port_cfg->layer3_reject_unknown) + { + fwpc0_value |= (R_MFWD_FWPC00_VLANRU_Msk | R_MFWD_FWPC00_VLANRUS_Msk); + } + + /* Write to port configuration register. */ + *p_mfwd_fwpc0_reg = fwpc0_value; +} /* End of function r_layer3_switch_configure_forwarding_port() */ + +/******************************************************************************************************************* + * Reset each forwarding table. + **********************************************************************************************************************/ +static void r_layer3_switch_reset_table (layer3_switch_instance_ctrl_t * p_instance_ctrl) +{ + /* Reset MAC table. */ + R_MFWD->FWMACTIM_b.MACTIOG = 1; + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWMACTIM_b.MACTR, 1); + + /* Reset VLAN table. */ + R_MFWD->FWVLANTIM_b.VLANTIOG = 1; + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWVLANTIM_b.VLANTR, 1); + + /* Reset layer3 table. */ + R_MFWD->FWLTHTIM_b.LTHTIOG = 1; + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWLTHTIM_b.LTHTR, 1); + + /* Reset layer3 Update feature. */ + R_MFWD->FWL23UTIM_b.L23UTIOG = 1; + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWL23UTIM_b.L23UTR, 1); + + /* Initialize entry counts. */ + p_instance_ctrl->l3_entry_count = 0; + p_instance_ctrl->l3_routing_number = 0; + p_instance_ctrl->l3_remapping_number = 0; +} /* End of function r_layer3_switch_reset_table() */ + +/******************************************************************************************************************* + * Learning an entry of MAC table. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_learn_mac_entry (layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t const * const p_entry_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + uint32_t mac_address_high; + uint32_t mac_address_low; + uint32_t fwmactl3_value = 0; + + /* Destination or source MAC address should be set. */ + FSP_ERROR_RETURN((NULL != p_target_frame->p_destination_mac_address) || + (NULL != p_target_frame->p_source_mac_address), + FSP_ERR_INVALID_ARGUMENT); + + if (NULL != p_target_frame->p_destination_mac_address) + { + /* Enable forwarding when destination MAC of a incoming frame is matched. */ + fwmactl3_value |= R_MFWD_FWMACTL3_MACDSLVL_Msk & (p_entry_cfg->source_ports << R_MFWD_FWMACTL3_MACDSLVL_Pos); + mac_address_high = r_layer3_switch_convert_array_to_int(&p_target_frame->p_destination_mac_address[0], 2); + mac_address_low = r_layer3_switch_convert_array_to_int(&p_target_frame->p_destination_mac_address[2], 4); + } + else + { + /* Enable forwarding when source MAC address of a incoming frame is matched. */ + fwmactl3_value |= R_MFWD_FWMACTL3_MACSSLVL_Msk & (p_entry_cfg->source_ports << R_MFWD_FWMACTL3_MACSSLVL_Pos); + mac_address_high = r_layer3_switch_convert_array_to_int(&p_target_frame->p_source_mac_address[0], 2); + mac_address_low = r_layer3_switch_convert_array_to_int(&p_target_frame->p_source_mac_address[2], 4); + } + + if (p_entry_cfg->entry_enable) + { + /* Set security and dynamic entry feature. */ + R_MFWD->FWMACTL0 = (uint32_t) (p_entry_cfg->mac.dinamic_entry << R_MFWD_FWMACTL0_MACDEL_Pos) | + (uint32_t) (p_entry_cfg->security_enable << R_MFWD_FWMACTL0_MACSLL_Pos); + + /* Set MAC address. */ + R_MFWD->FWMACTL1 = mac_address_high; + R_MFWD->FWMACTL2 = mac_address_low; + + /* Set enabled source port. */ + R_MFWD->FWMACTL3 = fwmactl3_value; + + /* Set destination queue index when forward to CPU. */ + R_MFWD->FWMACTL40 = R_MFWD_FWMACTL40_MACCSDL_Msk & p_entry_cfg->destination_queue_index; + + /* Set destination ports and internal priority. */ + R_MFWD->FWMACTL5 = (p_entry_cfg->internal_priority_update_enable << R_MFWD_FWMACTL5_MACIPUL_Pos) | + (R_MFWD_FWMACTL5_MACIPVL_Msk & p_entry_cfg->internal_priority_update_value << + R_MFWD_FWMACTL5_MACIPVL_Pos) | + (R_MFWD_FWMACTL5_MACDVL_Msk & p_entry_cfg->destination_ports); + } + else + { + /* If entry is disabled, delete the target entry. */ + /* Set to delete mode. */ + R_MFWD->FWMACTL0 = R_MFWD_FWMACTL0_MACED_Msk; + + /* Set MAC address. */ + R_MFWD->FWMACTL1 = R_MFWD_FWMACTL1_MACMALP0_Msk & mac_address_high; + R_MFWD->FWMACTL2 = mac_address_low; + + /* Write to FWMACTL5 register. It is need to start deleting process. */ + R_MFWD->FWMACTL5 = 0; + } + + /* Wait to complete learning. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWMACTLR_b.MACTL, 0); + + /* Check learning result. */ + if (0 != (R_MFWD->FWMACTLR & R_MFWD_FWMACTLR_MACLSF_Msk)) + { + /* Unsecure entry overflow. */ + err = FSP_ERR_OVERFLOW; + } + else if (0 != (R_MFWD->FWMACTLR & (R_MFWD_FWMACTLR_MACLF_Msk | R_MFWD_FWMACTLR_MACLEF_Msk))) + { + err = FSP_ERR_WRITE_FAILED; + } + else + { + /* Do nothing. */ + } + + return err; +} /* End of function r_layer3_switch_learn_mac_entry() */ + +/******************************************************************************************************************* + * Search an entry of MAC table. + * + * @param[in] p_port_cfg Pointer to a target frame + * @param[in] port Pointer to an entry + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_search_mac_entry (layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t * const p_entry_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mac_address_high; + uint32_t mac_address_low; + + /* Destination or source MAC address should be set. */ + FSP_ERROR_RETURN((NULL != p_target_frame->p_destination_mac_address) || + (NULL != p_target_frame->p_source_mac_address), + FSP_ERR_INVALID_POINTER); + + if (NULL != p_target_frame->p_destination_mac_address) + { + /* Use destination MAC address to search. */ + mac_address_high = r_layer3_switch_convert_array_to_int(&p_target_frame->p_destination_mac_address[0], 2); + mac_address_low = r_layer3_switch_convert_array_to_int(&p_target_frame->p_destination_mac_address[2], 4); + } + else + { + /* If destination is not passed, use source MAC address to search. */ + mac_address_high = r_layer3_switch_convert_array_to_int(&p_target_frame->p_source_mac_address[0], 2); + mac_address_low = r_layer3_switch_convert_array_to_int(&p_target_frame->p_source_mac_address[2], 4); + } + + /* Set MAC address and start searching. */ + R_MFWD->FWMACTS0 = mac_address_high; + R_MFWD->FWMACTS1 = mac_address_low; + + /* Wait to complete searching. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWMACTSR0_b.MACTS, 0); + + if (0 == R_MFWD->FWMACTSR0_b.MACSNF) + { + /* If an entry is found successfully, copy the entry fields. */ + p_entry_cfg->security_enable = R_MFWD->FWMACTSR0_b.MACSLS; + p_entry_cfg->mac.dinamic_entry = R_MFWD->FWMACTSR0_b.MACDES; + p_entry_cfg->source_ports = R_MFWD->FWMACTSR1_b.MACDSLVS | R_MFWD->FWMACTSR1_b.MACSSLVS; + p_entry_cfg->destination_queue_index = R_MFWD->FWMACTSR20_b.MACCSDS; + p_entry_cfg->destination_ports = R_MFWD->FWMACTSR3_b.MACDVS; + p_entry_cfg->internal_priority_update_enable = R_MFWD->FWMACTSR3_b.MACIPUS; + p_entry_cfg->internal_priority_update_value = R_MFWD->FWMACTSR3_b.MACIPVS; + } + else + { + /* Any entry is not found. */ + err = FSP_ERR_NOT_FOUND; + } + + return err; +} /* End of function r_layer3_switch_search_mac_entry() */ + +/******************************************************************************************************************* + * Read an entry of MAC table. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_read_mac_entry (uint16_t offset, layer3_switch_table_entry_t * p_entry) +{ + fsp_err_t err = FSP_SUCCESS; + uint8_t * p_mac_address; + + R_MFWD->FWMACTR = LAYER3_SWITCH_MAC_ENTRY_MAX_NUM & offset; + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWMACTRR0_b.MACTR, 0); + + if (R_MFWD->FWMACTRR0_b.MACEVR) + { + p_entry->entry_cfg.security_enable = R_MFWD->FWMACTRR1_b.MACSLR; + p_entry->entry_cfg.mac.dinamic_entry = R_MFWD->FWMACTRR1_b.MACDER; + p_entry->entry_cfg.source_ports = R_MFWD->FWMACTRR4_b.MACDSLVR | + R_MFWD->FWMACTRR4_b.MACSSLVR; + p_entry->entry_cfg.destination_queue_index = R_MFWD->FWMACTRR50_b.MACCSDR; + p_entry->entry_cfg.destination_ports = R_MFWD->FWMACTRR6_b.MACDVR; + p_entry->entry_cfg.internal_priority_update_enable = R_MFWD->FWMACTRR6_b.MACIPUR; + p_entry->entry_cfg.internal_priority_update_value = R_MFWD->FWMACTRR6_b.MACIPVR; + + if (R_MFWD->FWMACTRR4_b.MACDSLVR) + { + /* When destination MAC address matching is enabled. */ + p_mac_address = p_entry->target_frame.p_destination_mac_address; + } + else if (R_MFWD->FWMACTRR4_b.MACSSLVR) + { + /* When source MAC address matching is enabled. */ + p_mac_address = p_entry->target_frame.p_source_mac_address; + } + else + { + p_mac_address = NULL; + } + + if (NULL != p_mac_address) + { + p_mac_address[0] = (uint8_t) (R_MFWD->FWMACTRR2_b.MACMARP0 >> 8); + p_mac_address[1] = (uint8_t) (R_MFWD->FWMACTRR2_b.MACMARP0); + p_mac_address[2] = (uint8_t) (R_MFWD->FWMACTRR3_b.MACMARP1 >> 24); + p_mac_address[3] = (uint8_t) (R_MFWD->FWMACTRR3_b.MACMARP1 >> 16); + p_mac_address[4] = (uint8_t) (R_MFWD->FWMACTRR3_b.MACMARP1 >> 8); + p_mac_address[5] = (uint8_t) (R_MFWD->FWMACTRR3_b.MACMARP1); + } + else + { + /* An array for MAC address should be given by the argument. */ + err = FSP_ERR_INVALID_ARGUMENT; + } + } + else + { + err = FSP_ERR_NOT_FOUND; + } + + return err; +} /* End of function r_layer3_switch_read_mac_entry() */ + +/******************************************************************************************************************* + * Learning an entry of VLAN table. + * + * @param[in] p_entry Pointer to an entry + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_learn_vlan_entry (layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t const * const p_entry_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + uint16_t vlan_id; + + /* Extract VLAN ID. */ + err = r_layer3_switch_extract_vlan_id(p_target_frame, &vlan_id); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + if (p_entry_cfg->entry_enable) + { + /* Set entry is secure or not. */ + R_MFWD->FWVLANTL0 = (uint32_t) (p_entry_cfg->security_enable << R_MFWD_FWVLANTL0_VLANSLL_Pos); + + /* Set VLAN ID. */ + R_MFWD->FWVLANTL1 = vlan_id; + + /* Set forwarding ports. */ + R_MFWD->FWVLANTL2 = p_entry_cfg->source_ports; + R_MFWD->FWVLANTL30 = p_entry_cfg->destination_queue_index; + R_MFWD->FWVLANTL4 = (p_entry_cfg->destination_ports); + } + else + { + /* Set to delete mode. */ + R_MFWD->FWVLANTL0 = R_MFWD_FWVLANTL0_VLANED_Msk; + R_MFWD->FWVLANTL1 = vlan_id; + + /* Write to following register to start learning process. */ + R_MFWD->FWVLANTL4 = 0x0; + } + + /* Wait to complete learning */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWVLANTLR_b.VLANTL, 0); + + if (0 != (R_MFWD->FWVLANTLR & R_MFWD_FWVLANTLR_VLANLSF_Msk)) + { + /* Unsecure entry overflow. */ + err = FSP_ERR_OVERFLOW; + } + else if (0 != (R_MFWD->FWVLANTLR & (R_MFWD_FWVLANTLR_VLANLF_Msk | R_MFWD_FWVLANTLR_VLANLEF_Msk))) + { + err = FSP_ERR_WRITE_FAILED; + } + else + { + err = FSP_SUCCESS; + + /* Do nothing. */ + } + + return err; +} /* End of function r_layer3_switch_learn_vlan_entry() */ + +/******************************************************************************************************************* + * Search an entry of VLAN table. + * + * @param[in] p_port_cfg Pointer to a target frame + * @param[in] port Pointer to an entry + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_search_vlan_entry (layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t * const p_entry_cfg) +{ + uint16_t vlan_id; + fsp_err_t err; + + /* Extract VLAN ID from the target frame. */ + err = r_layer3_switch_extract_vlan_id(p_target_frame, &vlan_id); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Start searching. */ + R_MFWD->FWVLANTS = vlan_id; + + /* Wait to complete searching. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWVLANTSR0_b.VLANTS, 0); + + if (0 == R_MFWD->FWVLANTSR0_b.VLANSNF) + { + /* An entry with the VLAN ID is found. Copy entry fields. */ + p_entry_cfg->security_enable = R_MFWD->FWVLANTSR0_b.VLANSLS; + p_entry_cfg->source_ports = R_MFWD->FWVLANTSR1_b.VLANSLVS; + p_entry_cfg->destination_queue_index = R_MFWD->FWVLANTSR20_b.VLANCSDS; + p_entry_cfg->destination_ports = R_MFWD->FWVLANTSR3_b.VLANDVS; + } + else + { + /* Any entry is not found. */ + err = FSP_ERR_NOT_FOUND; + } + + return err; +} /* End of function r_layer3_switch_search_vlan_entry() */ + +/******************************************************************************************************************* + * Read an entry of VLAN table. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_read_vlan_entry (uint16_t offset, layer3_switch_table_entry_t * p_entry) +{ + fsp_err_t err; + FSP_ERROR_RETURN(LAYER3_SWITCH_VLAN_MODE_NO_VLAN != R_MFWD->FWGC_b.SVM, FSP_ERR_INVALID_MODE); + + /* Set offset as VLAN ID. */ + p_entry->target_frame.vlan_c_tag.id = LAYER3_SWITCH_VLAN_ENTRY_MAX_NUM & offset; + + /* Search an entry with this VLAN ID. */ + err = r_layer3_switch_search_vlan_entry(&p_entry->target_frame, &p_entry->entry_cfg); + + return err; +} /* End of function r_layer3_switch_read_vlan_entry() */ + +/******************************************************************************************************************* + * Learn an entry of layer3 forwarding table. + * + * @param[in] p_entry Pointer to an entry + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_learn_l3_entry (layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t const * const p_entry_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + layer3_switch_extended_cfg_t * p_extend = (layer3_switch_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + layer3_switch_stream_id_t stream_id = {0}; + uint32_t filter_id = 0; + uint32_t frer_number = 0; + uint32_t routing_number; + + FSP_ERROR_RETURN(p_extend->l3_filter_list_length > p_instance_ctrl->l3_entry_count, FSP_ERR_OVERFLOW); + + /* Calculate new stream ID. */ + r_layer3_switch_calculate_l3_stream_id(p_target_frame, &stream_id); + + /* Set stream ID. */ + R_MFWD->FWLTHTL1 = stream_id.words[0]; + R_MFWD->FWLTHTL2 = stream_id.words[1]; + R_MFWD->FWLTHTL3 = stream_id.words[2]; + R_MFWD->FWLTHTL4 = stream_id.words[3]; + + /* Calculate FRER number. */ + if (NULL != p_entry_cfg->p_frer_entry_cfg) + { + /* If sequence recovery is passed and has not been learned, two FRER entries will be learned. */ + if ((NULL != p_entry_cfg->p_frer_entry_cfg->p_sequence_recovery) && + (false == + p_instance_ctrl->frer_sequence_recovery_status[p_entry_cfg->p_frer_entry_cfg->sequence_recovery_id & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK].learned)) + { + frer_number = (p_instance_ctrl->valid_frer_entry_num + 1) & LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK; + } + else + { + /* In other case, one FRER entry will be learned. */ + frer_number = p_instance_ctrl->valid_frer_entry_num & LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK; + } + } + + if (p_entry_cfg->entry_enable) + { + /* Set stream ID and security level. */ + R_MFWD->FWLTHTL0 = + (uint32_t) ((R_MFWD_FWLTHTL0_LTHSLP0_Msk & + (uint32_t) (stream_id.frame_format_code << R_MFWD_FWLTHTL0_LTHSLP0_Pos)) | + (uint32_t) (p_entry_cfg->security_enable << R_MFWD_FWLTHTL0_LTHSLL_Pos)); + + if (NULL != p_entry_cfg->p_psfp_msdu_filter_cfg) + { + err = r_layer3_switch_psfp_select_msdu_filter_id(p_instance_ctrl, + &filter_id, + p_entry_cfg->p_psfp_msdu_filter_cfg); + + if (err == FSP_SUCCESS) + { + /* Initialize PSFP MSDU filter. */ + err = r_layer3_switch_psfp_msdu_filter_init(p_instance_ctrl, filter_id, p_entry_cfg); + + if (err == FSP_SUCCESS) + { + /* Configure PSFP MDSU filter feature. */ + R_MFWD->FWLTHTL5 = + (uint32_t) ((R_MFWD_FWLTHTL5_LTHMSDUNL_Msk & + (filter_id << R_MFWD_FWLTHTL5_LTHMSDUNL_Pos)) | + (R_MFWD_FWLTHTL5_LTHMSDUVL_Msk & + (uint32_t) ((NULL != + p_entry_cfg->p_psfp_msdu_filter_cfg) << + R_MFWD_FWLTHTL5_LTHMSDUVL_Pos))); + } + } + } + + if (NULL != p_entry_cfg->p_psfp_meter_filter_cfg) + { + err = r_layer3_switch_psfp_select_meter_filter_id(p_instance_ctrl, + &filter_id, + p_entry_cfg->p_psfp_meter_filter_cfg); + + if (err == FSP_SUCCESS) + { + /* Initialize PSFP Meter filter. */ + err = r_layer3_switch_psfp_meter_filter_init(p_instance_ctrl, filter_id, p_entry_cfg); + + if (err == FSP_SUCCESS) + { + /* Configure FRER and PSFP Meter filter feature. */ + R_MFWD->FWLTHTL6 = ((R_MFWD_FWLTHTL6_LTHFRERVL_Msk & + (uint32_t) ((NULL != + p_entry_cfg->p_frer_entry_cfg) << + R_MFWD_FWLTHTL6_LTHFRERVL_Pos)) | + (R_MFWD_FWLTHTL6_LTHMTRNL_Msk & + (filter_id << R_MFWD_FWLTHTL6_LTHMTRNL_Pos)) | + (R_MFWD_FWLTHTL6_LTHMTRVL_Msk & + (uint32_t) ((NULL != + p_entry_cfg->p_psfp_meter_filter_cfg) << + R_MFWD_FWLTHTL6_LTHMTRVL_Pos)) | + (R_MFWD_FWLTHTL6_LTHFRERNL_Msk & + (frer_number << R_MFWD_FWLTHTL6_LTHFRERNL_Pos))); + } + } + } + else + { + /* Configure FRER feature. */ + R_MFWD->FWLTHTL6 = ((R_MFWD_FWLTHTL6_LTHFRERVL_Msk & + (uint32_t) ((NULL != + p_entry_cfg->p_frer_entry_cfg) << R_MFWD_FWLTHTL6_LTHFRERVL_Pos)) | + (R_MFWD_FWLTHTL6_LTHFRERNL_Msk & + (frer_number << R_MFWD_FWLTHTL6_LTHFRERNL_Pos))); + } + + /* Configure routing number and source ports. */ + R_MFWD->FWLTHTL7 = + (uint32_t) ((uint32_t) ((NULL != p_entry_cfg->layer3.p_update_configs) << R_MFWD_FWLTHTL7_LTHRVL_Pos) | + (R_MFWD_FWLTHTL7_LTHRNL_Msk & + (uint32_t) (p_instance_ctrl->l3_routing_number << + R_MFWD_FWLTHTL7_LTHRNL_Pos)) | + (R_MFWD_FWLTHTL7_LTHSLVL_Msk & + (p_entry_cfg->source_ports << R_MFWD_FWLTHTL7_LTHSLVL_Pos))); + + /* Configure queue index that frame forwarding to. */ + R_MFWD->FWLTHTL80 = + (uint32_t) (R_MFWD_FWLTHTL80_LTHCSDL_Msk & + (p_entry_cfg->destination_queue_index << R_MFWD_FWLTHTL80_LTHCSDL_Pos)); + + /* Configure destination ports, mirroring and internal priority. After writing this register, hardware start learning. */ + R_MFWD->FWLTHTL9 = + (p_entry_cfg->destination_ports << R_MFWD_FWLTHTL9_LTHDVL_Pos); + } + else + { + /* Set to delete mode. */ + R_MFWD->FWLTHTL0 = + (uint32_t) ((R_MFWD_FWLTHTL0_LTHSLP0_Msk & + (uint32_t) (stream_id.frame_format_code << R_MFWD_FWLTHTL0_LTHSLP0_Pos)) | + (1 << R_MFWD_FWLTHTL0_LTHED_Pos)); + + /* Start removing entry. */ + R_MFWD->FWLTHTL9 = 0; + } + + if (err == FSP_SUCCESS) + { + /* Wait reset. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWLTHTLR_b.LTHTL, 0); + + /* Check learning result. */ + if (0 == + (R_MFWD->FWLTHTLR & (R_MFWD_FWLTHTLR_LTHLF_Msk | R_MFWD_FWLTHTLR_LTHLSF_Msk | R_MFWD_FWLTHTLR_LTHLEF_Msk))) + { + err = FSP_SUCCESS; + } + else + { + err = FSP_ERR_WRITE_FAILED; + } + } + + if (err == FSP_SUCCESS) + { + /* Configure L3 update feature. */ + if (NULL != p_entry_cfg->layer3.p_update_configs) + { + if (0 < p_entry_cfg->layer3.number_of_configs) + { + err = + r_layer3_switch_learn_l3_update(p_instance_ctrl, &p_entry_cfg->layer3.p_update_configs[0]); + routing_number = p_instance_ctrl->l3_routing_number - 1; + } + + /* When two or more config are passed, set it using remapping feature. */ + for (uint32_t i = 1; (i < p_entry_cfg->layer3.number_of_configs) && (FSP_SUCCESS == err); i++) + { + err = r_layer3_switch_remapping_l3_update(p_instance_ctrl, + routing_number, + &p_entry_cfg->layer3.p_update_configs[i]); + } + } + + /* When the FRER individual recovery is passed, learn the FRER entry. */ + if ((FSP_SUCCESS == err) && (NULL != p_entry_cfg->p_frer_entry_cfg)) + { + err = r_layer3_switch_learn_frer_individual_recovery(p_instance_ctrl, p_entry_cfg->p_frer_entry_cfg); + } + + if ((FSP_SUCCESS == err) && p_entry_cfg->entry_enable) + { + /* Save routing number. */ + if (0 != stream_id.frame_format_code) + { + /* This stream ID is generated by stream filter. Save frame with routing number.*/ + p_extend->l3_filter_list[p_instance_ctrl->l3_entry_count].frame = *p_target_frame; + } + + /* Count the valid Layer 3 entry. */ + p_instance_ctrl->l3_entry_count += 1; + } + } + + return err; +} /* End of function r_layer3_switch_learn_l3_entry() */ + +/******************************************************************************************************************* + * Search an entry of layer3 forwarding table. + * + * @param[in] p_port_cfg Pointer to a target frame + * @param[in] port Pointer to an entry + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_search_l3_entry (layer3_switch_frame_filter_t const * const p_target_frame, + layer3_switch_table_entry_cfg_t * const p_entry_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + layer3_switch_stream_id_t stream_id; + uint8_t routing_number; + bool l3_update_enable; + + r_layer3_switch_calculate_l3_stream_id(p_target_frame, &stream_id); + + /* Set stream ID of a entry. */ + R_MFWD->FWLTHTS0_b.LTHSSP0 = R_MFWD_FWLTHTS0_LTHSSP0_Msk & stream_id.frame_format_code; + R_MFWD->FWLTHTS1_b.LTHSSP1 = stream_id.words[0]; + R_MFWD->FWLTHTS2_b.LTHSSP2 = stream_id.words[1]; + R_MFWD->FWLTHTS3_b.LTHSSP3 = stream_id.words[2]; + R_MFWD->FWLTHTS4_b.LTHSSP4 = stream_id.words[3]; + + /* Wait completing search. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWLTHTSR0_b.LTHTS, 0); + + if (0 == R_MFWD->FWLTHTSR0_b.LTHSNF) + { + /* Copy entry values. */ + routing_number = R_MFWD->FWLTHTSR3_b.LTHRNS; + p_entry_cfg->source_ports = R_MFWD->FWLTHTSR3_b.LTHSLVS; + p_entry_cfg->destination_ports = R_MFWD->FWLTHTSR5_b.LTHDVS; + + /* Copy enable/disable setting bits. */ + p_entry_cfg->security_enable = R_MFWD->FWLTHTSR0_b.LTHSLS; + l3_update_enable = R_MFWD->FWLTHTSR3_b.LTHRVS; + } + else + { + /* Any entry for the stream ID is not found. */ + err = FSP_ERR_NOT_FOUND; + } + + if (err == FSP_SUCCESS) + { + /* Search and get update config. */ + if (l3_update_enable && (NULL != p_entry_cfg->layer3.p_update_configs)) + { + err = r_layer3_switch_search_l3_update(routing_number, &p_entry_cfg->layer3.p_update_configs[0]); + } + } + + return err; +} /* End of function r_layer3_switch_search_l3_entry() */ + +/******************************************************************************************************************* + * Learn an entry of layer3 update table. + * + * @param[in] routing_number Index of a target layer3 entry. + * @param[in] p_config Pointer to an configuration of update entry. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_learn_l3_update (layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_l3_update_config_t * const p_config) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Set the target routing number. */ + R_MFWD->FWL23URL0 = + (R_MFWD_FWL23URL0_L23URNL_Msk & + ((uint32_t) (p_instance_ctrl->l3_routing_number << R_MFWD_FWL23URL0_L23URNL_Pos))) | + (R_MFWD_FWL23URL0_L23URPVL_Msk & + (p_config->enable_destination_ports << R_MFWD_FWL23URL0_L23URPVL_Pos)); + + R_MFWD->FWL23URL1 = + (R_MFWD_FWL23URL1_L23UMDALP0_Msk & + (r_layer3_switch_convert_array_to_int(&p_config->p_mac_destination_address[0], + 2) << R_MFWD_FWL23URL1_L23UMDALP0_Pos)) | + (p_config->update_field_bitmask << R_MFWD_FWL23URL1_L23UTTLUL_Pos) | + (R_MFWD_FWL23URL1_L23URTUL_Msk & ((uint32_t) (p_config->r_tag_update_mode << R_MFWD_FWL23URL1_L23URTUL_Pos))); + + R_MFWD->FWL23URL2 = + (R_MFWD_FWL23URL2_L23UMDALP1_Msk & + (r_layer3_switch_convert_array_to_int(&p_config->p_mac_destination_address[2], + 4) << R_MFWD_FWL23URL2_L23UMDALP1_Pos)); + + R_MFWD->FWL23URL3 = + (R_MFWD_FWL23URL3_L23UCVIDL_Msk & ((uint32_t) (p_config->vlan_c_tag.id << R_MFWD_FWL23URL3_L23UCVIDL_Pos))) | + (R_MFWD_FWL23URL3_L23UCPCPL_Msk & ((uint32_t) (p_config->vlan_c_tag.pcp << R_MFWD_FWL23URL3_L23UCPCPL_Pos))) | + (R_MFWD_FWL23URL3_L23UCDEIL_Msk & ((uint32_t) (p_config->vlan_c_tag.dei << R_MFWD_FWL23URL3_L23UCDEIL_Pos))) | + (R_MFWD_FWL23URL3_L23USVIDL_Msk & ((uint32_t) (p_config->vlan_s_tag.id << R_MFWD_FWL23URL3_L23USVIDL_Pos))) | + (R_MFWD_FWL23URL3_L23USPCPL_Msk & ((uint32_t) (p_config->vlan_s_tag.pcp << R_MFWD_FWL23URL3_L23USPCPL_Pos))) | + (R_MFWD_FWL23URL3_L23USDEIL_Msk & ((uint32_t) (p_config->vlan_s_tag.dei << R_MFWD_FWL23URL3_L23USDEIL_Pos))); + + /* Wait reset. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWL23URLR_b.L23URL, 0); + + if (0 != R_MFWD->FWL23URLR_b.L23ULF) + { + /* Layer3 update learning fail. */ + err = FSP_ERR_WRITE_FAILED; + } + else + { + if (true == p_config->sequence_number_generation_enable) + { + /* Enable sequence_number_generation for this L23U entry. */ + if (LAYER3_SWITCH_SEQ_REG_MAX_NUM > + (p_instance_ctrl->used_frer_sequence_generator_num & LAYER3_SWITCH_FRER_SEQ_GENERATOR_NUM_BITMASK)) + { + r_layer3_switch_configure_sequence_number_generation(p_instance_ctrl); + + p_instance_ctrl->used_frer_sequence_generator_num = + (p_instance_ctrl->used_frer_sequence_generator_num + 1) & + LAYER3_SWITCH_FRER_SEQ_GENERATOR_NUM_BITMASK; + } + } + + p_instance_ctrl->l3_routing_number += 1; + } + + return err; +} /* End of function r_layer3_switch_learn_l3_update() */ + +/******************************************************************************************************************* + * Search an entry of layer3 update table. + * + * @param[in] routing_number Index of a target layer3 entry. + * @param[out] p_config Pointer to an configuration of update entry. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_search_l3_update (uint8_t routing_number, layer3_switch_l3_update_config_t * p_config) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Search for entries that match the routing number. */ + R_MFWD->FWL23URR_b.L23RNR = routing_number; + + /* Wait reset. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWL23URRR0_b.L23URR, 0); + + if (0 == R_MFWD->FWL23URRR0_b.L23UREF) + { + /* Layer3 update entry searching success. Copy fields.*/ + p_config->enable_destination_ports = R_MFWD->FWL23URRR0_b.L23URPVR; + p_config->update_field_bitmask = + ((R_MFWD_FWL23URRR1_L23UTTLUR_Msk | R_MFWD_FWL23URRR1_L23UMDAUR_Msk | R_MFWD_FWL23URRR1_L23UMSAUR_Msk | + R_MFWD_FWL23URRR1_L23UCVIDUR_Msk | R_MFWD_FWL23URRR1_L23UCPCPUR_Msk | R_MFWD_FWL23URRR1_L23UCDEIUR_Msk | + R_MFWD_FWL23URRR1_L23USVIDUR_Msk | R_MFWD_FWL23URRR1_L23USPCPUR_Msk | R_MFWD_FWL23URRR1_L23USDEIUR_Msk) & + R_MFWD->FWL23URRR1) >> R_MFWD_FWL23URRR1_L23UTTLUR_Pos; + p_config->r_tag_update_mode = (layer3_switch_forwarding_r_tag_t) R_MFWD->FWL23URRR1_b.L23URTUR; + p_config->vlan_c_tag.id = R_MFWD->FWL23URRR3_b.L23UCVIDR; + p_config->vlan_c_tag.pcp = R_MFWD->FWL23URRR3_b.L23UCPCPR; + p_config->vlan_c_tag.dei = R_MFWD->FWL23URRR3_b.L23UCDEIR; + p_config->vlan_s_tag.id = R_MFWD->FWL23URRR3_b.L23USVIDR; + p_config->vlan_s_tag.pcp = R_MFWD->FWL23URRR3_b.L23USPCPR; + p_config->vlan_s_tag.dei = R_MFWD->FWL23URRR3_b.L23USDEIR; + if (NULL != p_config->p_mac_destination_address) + { + /* Copy MAC address. */ + p_config->p_mac_destination_address[0] = (uint8_t) (R_MFWD->FWL23URRR1_b.L23UMDARP0 >> 8); + p_config->p_mac_destination_address[1] = (uint8_t) R_MFWD->FWL23URRR1_b.L23UMDARP0; + p_config->p_mac_destination_address[2] = (uint8_t) (R_MFWD->FWL23URRR2_b.L23UMDARP1 >> 24); + p_config->p_mac_destination_address[3] = (uint8_t) (R_MFWD->FWL23URRR2_b.L23UMDARP1 >> 16); + p_config->p_mac_destination_address[4] = (uint8_t) (R_MFWD->FWL23URRR2_b.L23UMDARP1 >> 8); + p_config->p_mac_destination_address[5] = (uint8_t) R_MFWD->FWL23URRR2_b.L23UMDARP1; + } + } + else + { + /* Layer3 update entry is not found. */ + err = FSP_ERR_NOT_FOUND; + } + + return err; +} /* End of function r_layer3_switch_search_l3_update() */ + +/******************************************************************************************************************* + * Enable and configure MAC aging feature. + * + * @param[in] aging_time Aging cycle time + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_enable_mac_table_aging (uint32_t aging_time) +{ + /* Configure aging clock prescaler. */ + R_MFWD->FWMACAGUSPC = R_MFWD_FWMACAGUSPC_MACAGUSP_Msk & LAYER3_SWITCH_CLOCK_100MHZ; + + /* Enable aging and set aging time. */ + R_MFWD->FWMACAGC = R_MFWD_FWMACAGC_MACAGE_Msk | (R_MFWD_FWMACAGC_MACAGT_Msk & aging_time); + + return FSP_SUCCESS; +} /* End of function r_layer3_switch_enable_mac_table_aging() */ + +/******************************************************************************************************************* + * Extract VLAN ID from a target frame based on hardware VLAN mode. + * + * @param[in] p_target_frame Pointer to a target frame + * @param[out] p_vlan_id Extracted VLAN ID + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_extract_vlan_id (layer3_switch_frame_filter_t const * const p_target_frame, + uint16_t * p_vlan_id) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Check VLAN mode of this switch. */ + if (R_MFWD->FWGC_b.SVM == LAYER3_SWITCH_VLAN_MODE_NO_VLAN) + { + /* When No VLAN mode, can't use VLAN feature. */ + err = FSP_ERR_INVALID_MODE; + } + else if ((R_MFWD->FWGC_b.SVM == LAYER3_SWITCH_VLAN_MODE_SC_TAG) && (0 < p_target_frame->vlan_s_tag.id)) + { + /* When the switch is SC-TAG mode and passed S-TAG is valid, use S-TAG. */ + *p_vlan_id = p_target_frame->vlan_s_tag.id; + } + else if (0 < p_target_frame->vlan_c_tag.id) + { + /* If passed C-TAG is valid, use C-TAG. */ + *p_vlan_id = p_target_frame->vlan_c_tag.id; + } + else + { + /* If S-TAG and C-TAG is invalid, return error. */ + err = FSP_ERR_INVALID_ARGUMENT; + } + + return err; +} /* End of function r_layer3_switch_extract_vlan_id() */ + +/******************************************************************************************************************* + * Configure VLAN ingress and egress mode of the target port. + * + * @param[in] p_instance_ctrl Pointer to a instance control + * @param[in] p_port_cfg Pointer to a port dependent configuration + * @param[in] port The target port + **********************************************************************************************************************/ +static void r_layer3_switch_initialize_vlan_port (layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_forwarding_port_cfg_t const * const p_port_cfg, + uint8_t port) +{ + R_ETHA0_Type * p_reg_etha; + uint32_t vcc_reg_value; + uint32_t vtc_reg_value; + + /* Set ingress/egress mode. */ + vcc_reg_value = (uint32_t) ((p_port_cfg->vlan_ingress_mode << R_ETHA0_EAVCC_VIM_Pos) | + (p_port_cfg->vlan_egress_mode << R_ETHA0_EAVCC_VEM_Pos)); + + /* Set VLAN ID, PCP, DEI of the port. */ + vtc_reg_value = (uint32_t) ((p_port_cfg->vlan_c_tag.id << R_ETHA0_EAVTC_CTV_Pos) | + (p_port_cfg->vlan_c_tag.pcp << R_ETHA0_EAVTC_CTP_Pos) | + (p_port_cfg->vlan_c_tag.dei << R_ETHA0_EAVTC_CTD_Pos) | + (p_port_cfg->vlan_s_tag.id << R_ETHA0_EAVTC_STV_Pos) | + (p_port_cfg->vlan_s_tag.pcp << R_ETHA0_EAVTC_STP_Pos) | + (p_port_cfg->vlan_s_tag.dei << R_ETHA0_EAVTC_STD_Pos)); + + if (port < BSP_FEATURE_ETHER_NUM_CHANNELS) + { + /* When port is external(ETHA). */ + /* Change ETHA to CONFIG mode. */ + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_CONFIG); + + /* Write register to configuration value. */ + p_reg_etha = (R_ETHA0_Type *) (R_ETHA0_BASE + (LAYER3_SWITCH_ETHA_REG_SIZE * port)); + p_reg_etha->EAVCC = vcc_reg_value; + p_reg_etha->EAVTC = vtc_reg_value; + + /* Change ETHA to OPERATION mode. */ + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_OPERATION); + } + else + { + /* When port is the CPU (GWCA). */ + /* Set GWCA to CONFIG mode. */ + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_CONFIG); + + /* Write register to configuration value. */ + p_instance_ctrl->p_gwca_reg->GWVCC = vcc_reg_value; + p_instance_ctrl->p_gwca_reg->GWVTC = vtc_reg_value; + + /* Set GWCA to OPERATION mode. */ + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_OPERATION); + } +} /* End of function r_layer3_switch_initialize_vlan_port() */ + +/******************************************************************************************************************* + * Configure IPv4/IPv6/L2 stream filter to which frame fields used to stream ID creation. + * + * @param[in] p_filter_cfg Pointer to a stream filter configuration + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_configure_stream_filter (layer3_switch_l3_stream_filter_cfg_t const * p_filter_cfg) +{ + FSP_ERROR_RETURN(NULL != p_filter_cfg, FSP_ERR_INVALID_POINTER); + uint32_t filter_reg_value = 0; + + /* Configure IPv4 filter. */ + /* Set fields included to hash calculation. */ + filter_reg_value = p_filter_cfg->filter_field_bitmask; + + /* Set fields included to stream ID creation. */ + filter_reg_value |= + ((R_MFWD_FWIP4SC_IP4ISVS_Msk | R_MFWD_FWIP4SC_IP4ISPS_Msk | R_MFWD_FWIP4SC_IP4ISDS_Msk | + R_MFWD_FWIP4SC_IP4ICVS_Msk | R_MFWD_FWIP4SC_IP4ICPS_Msk | R_MFWD_FWIP4SC_IP4ICDS_Msk | + R_MFWD_FWIP4SC_IP4IISS_Msk | + R_MFWD_FWIP4SC_IP4IIDS_Msk) & + (uint32_t) (p_filter_cfg->filter_field_bitmask << (R_MFWD_FWIP4SC_IP4ISVS_Pos - 2))) | + ((uint32_t) ((p_filter_cfg->filter_field_bitmask & + LAYER3_SWITCH_L3_FILTER_BITMASK_IP_DESTINATION_PORT) != 0) << R_MFWD_FWIP4SC_IP4IDPTS_Pos); + + R_MFWD->FWIP4SC = filter_reg_value; + + /* Configure IPv6 filter. */ + /* Set fields included to hash calculation. */ + filter_reg_value = p_filter_cfg->filter_field_bitmask; + + /* Set fields included to stream ID creation. */ + filter_reg_value |= + ((R_MFWD_FWIP6SC_IP6ISVS_Msk | R_MFWD_FWIP6SC_IP6ISPS_Msk | R_MFWD_FWIP6SC_IP6ISDS_Msk | + R_MFWD_FWIP6SC_IP6ICVS_Msk | R_MFWD_FWIP6SC_IP6ICPS_Msk | R_MFWD_FWIP6SC_IP6ICDS_Msk | + R_MFWD_FWIP6SC_IP6II0S_Msk | + R_MFWD_FWIP6SC_IP6II1S_Msk) & + (uint32_t) (p_filter_cfg->filter_field_bitmask << (R_MFWD_FWIP6SC_IP6ISVS_Pos - 2))) | + ((uint32_t) ((p_filter_cfg->filter_field_bitmask & + LAYER3_SWITCH_L3_FILTER_BITMASK_IP_DESTINATION_PORT) != 0) << R_MFWD_FWIP6SC_IP6IDPTS_Pos); + + R_MFWD->FWIP6SC = filter_reg_value; + + /* Configure L2 filter. */ + /* Set fields included to stream ID creation. */ + filter_reg_value = + ((R_MFWD_FWL2SC_L2ISVS_Msk | R_MFWD_FWL2SC_L2ISPS_Msk | R_MFWD_FWL2SC_L2ISDS_Msk | R_MFWD_FWL2SC_L2ICVS_Msk | + R_MFWD_FWL2SC_L2ICPS_Msk | R_MFWD_FWL2SC_L2ICDS_Msk | R_MFWD_FWL2SC_L2IMDS_Msk | R_MFWD_FWL2SC_L2IMSS_Msk) & + p_filter_cfg->filter_field_bitmask); + R_MFWD->FWL2SC = filter_reg_value; + + /* Set IPv6 address offset. */ + R_MFWD->FWIP6OC = + (uint32_t) ((R_MFWD_FWIP6OC_IP6IPO1_Msk & + (uint32_t) (p_filter_cfg->ipv6_address1.offset << R_MFWD_FWIP6OC_IP6IPO1_Pos)) | + (R_MFWD_FWIP6OC_IP6IPOM1_Msk & + (uint32_t) (p_filter_cfg->ipv6_address1.direction << R_MFWD_FWIP6OC_IP6IPOM1_Pos)) | + (R_MFWD_FWIP6OC_IP6IPO_Msk & + (uint32_t) (p_filter_cfg->ipv6_address0.offset << R_MFWD_FWIP6OC_IP6IPO_Pos)) | + (R_MFWD_FWIP6OC_IP6IPOM_Msk & + (uint32_t) (p_filter_cfg->ipv6_address0.direction << R_MFWD_FWIP6OC_IP6IPOM_Pos))); + + /* Set IPv4/IPv6 hash equation. */ + R_MFWD->FWSFHEC = (uint32_t) ((1 << R_MFWD_FWSFHEC_IP4HE_Pos) | (1 << R_MFWD_FWSFHEC_IP6HE_Pos)); + + return FSP_SUCCESS; +} /* End of function r_layer3_switch_configure_stream_filter() */ + +/******************************************************************************************************************* + * Calculate a layer3 hash value of the target frame. + * + * @param[in] p_frame Pointer to the target frame. + **********************************************************************************************************************/ +uint16_t r_layer3_switch_calculate_l3_hash (layer3_switch_frame_filter_t const * p_frame) +{ + uint16_t hash_value; + + /* If target is not IP packet, hash value is 0. */ + if (LAYER3_SWITCH_IP_VERSION_NONE == p_frame->ip_version) + { + hash_value = 0; + } + else + { + /* Set destination MAC address. */ + if (NULL != p_frame->p_destination_mac_address) + { + R_MFWD->FWSHCR0 = r_layer3_switch_convert_array_to_int(&p_frame->p_destination_mac_address[0], 4); + R_MFWD->FWSHCR1_b.SHCMDP1 = (uint16_t) r_layer3_switch_convert_array_to_int( + &p_frame->p_destination_mac_address[4], + 2); + } + else + { + R_MFWD->FWSHCR0 = 0; + R_MFWD->FWSHCR1_b.SHCMDP1 = 0; + } + + if (NULL != p_frame->p_source_mac_address) + { + /* Source address should be input as 2 byte higher part and 4 byte lower part. */ + R_MFWD->FWSHCR1_b.SHCMSP0 = (uint16_t) r_layer3_switch_convert_array_to_int( + &p_frame->p_source_mac_address[0], + 2); + R_MFWD->FWSHCR2 = r_layer3_switch_convert_array_to_int(&p_frame->p_source_mac_address[2], 4); + } + else + { + R_MFWD->FWSHCR1_b.SHCMSP0 = 0; + R_MFWD->FWSHCR2 = 0; + } + + /* Set VLANs. */ + R_MFWD->FWSHCR3 = r_layer3_switch_convert_vlan_tag_to_int(&p_frame->vlan_s_tag, &p_frame->vlan_c_tag); + + /* Set IP addresses. */ + if (LAYER3_SWITCH_IP_VERSION_IPV4 == p_frame->ip_version) + { + /* Set IP protocol. */ + R_MFWD->FWSHCR4 = p_frame->protocol; + + /* IPv4 source. */ + R_MFWD->FWSHCR5 = 0; + R_MFWD->FWSHCR6 = 0; + R_MFWD->FWSHCR7 = 0; + R_MFWD->FWSHCR8 = r_layer3_switch_convert_array_to_int(p_frame->p_source_ip_address, 4); + + /* IPv4 destination. */ + R_MFWD->FWSHCR9 = 0; + R_MFWD->FWSHCR10 = 0; + R_MFWD->FWSHCR11 = 0; + R_MFWD->FWSHCR12 = r_layer3_switch_convert_array_to_int(p_frame->p_destination_ip_address, 4); + } + else + { + /* Set IP protocol and IPv6 bit. */ + R_MFWD->FWSHCR4 = (1 << R_MFWD_FWSHCR4_SHCFF_Pos) | p_frame->protocol; + + /* IPv6 source. */ + if (NULL != p_frame->p_source_ip_address) + { + R_MFWD->FWSHCR5 = r_layer3_switch_convert_array_to_int(&p_frame->p_source_ip_address[0], 4); + R_MFWD->FWSHCR6 = r_layer3_switch_convert_array_to_int(&p_frame->p_source_ip_address[4], 4); + R_MFWD->FWSHCR7 = r_layer3_switch_convert_array_to_int(&p_frame->p_source_ip_address[8], 4); + R_MFWD->FWSHCR8 = r_layer3_switch_convert_array_to_int(&p_frame->p_source_ip_address[12], 4); + } + else + { + R_MFWD->FWSHCR5 = 0; + R_MFWD->FWSHCR6 = 0; + R_MFWD->FWSHCR7 = 0; + R_MFWD->FWSHCR8 = 0; + } + + /* IPv6 destination. */ + if (NULL != p_frame->p_destination_ip_address) + { + R_MFWD->FWSHCR9 = r_layer3_switch_convert_array_to_int(&p_frame->p_destination_ip_address[0], 4); + R_MFWD->FWSHCR10 = r_layer3_switch_convert_array_to_int(&p_frame->p_destination_ip_address[4], 4); + R_MFWD->FWSHCR11 = r_layer3_switch_convert_array_to_int(&p_frame->p_destination_ip_address[8], 4); + R_MFWD->FWSHCR12 = r_layer3_switch_convert_array_to_int(&p_frame->p_destination_ip_address[12], 4); + } + else + { + R_MFWD->FWSHCR9 = 0; + R_MFWD->FWSHCR10 = 0; + R_MFWD->FWSHCR11 = 0; + R_MFWD->FWSHCR12 = 0; + } + } + + /* Set layer4 destination/source ports. That used for TCP and UDP. */ + R_MFWD->FWSHCR13 = + (R_MFWD_FWSHCR13_SHCDP_Msk & + (uint32_t) (p_frame->layer4_destination_port << R_MFWD_FWSHCR13_SHCDP_Pos)) | + (R_MFWD_FWSHCR13_SHCSP_Msk & + (uint32_t) (p_frame->layer4_source_port << R_MFWD_FWSHCR13_SHCSP_Pos)); + + /* After writing FWSHCR13 register, IP start calculation. */ + /* Wait for completing calculation. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWSHCRR_b.SHC, 0); + + /* Read hash value. */ + hash_value = R_MFWD->FWSHCRR_b.SHCR; + } + + return hash_value; +} /* End of function r_layer3_switch_calculate_l3_hash() */ + +/******************************************************************************************************************* + * Calculate a layer3 format code of the target frame. + * + * @param[in] p_frame Pointer to the target frame. + **********************************************************************************************************************/ +uint8_t r_layer3_switch_calculate_l3_format_code (layer3_switch_frame_filter_t const * p_frame) +{ + uint8_t ip_version_offset = 0; + uint8_t ip_protocol_offset = 0; + + /* Get the offset value of format code based on the IP version. */ + switch (p_frame->ip_version) + { + case LAYER3_SWITCH_IP_VERSION_IPV4: + { + ip_version_offset = 1; + break; + } + + case LAYER3_SWITCH_IP_VERSION_IPV6: + { + ip_version_offset = 4; + break; + } + + case LAYER3_SWITCH_IP_VERSION_NONE: + { + /* When not IP packet. */ + ip_version_offset = 7; + break; + } + + default: + { + /* Not reach here. */ + break; + } + } + + if (LAYER3_SWITCH_IP_VERSION_NONE != p_frame->ip_version) + { + switch (p_frame->protocol) + { + case LAYER3_SWITCH_IP_PROTOCOL_UDP: + { + ip_protocol_offset = 1; + break; + } + + case LAYER3_SWITCH_IP_PROTOCOL_TCP: + { + ip_protocol_offset = 2; + break; + } + + default: + { + ip_protocol_offset = 0; + break; + } + } + } + + /* Return frame format code. */ + return ip_version_offset + ip_protocol_offset; +} /* End of function r_layer3_switch_calculate_l3_format_code() */ + +/******************************************************************************************************************* + * Calculate a layer3 stream ID of the target frame. + * + * @param[in] p_frame Pointer to the target frame. + * @param[out] p_stream_id Pointer to the stream ID. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_calculate_l3_stream_id (layer3_switch_frame_filter_t const * p_frame, + layer3_switch_stream_id_t * p_stream_id) +{ + uint32_t ip_address0 = 0; + uint32_t ip_address1 = 0; + uint32_t ipv6_offset; + + switch (p_frame->ip_version) + { + case LAYER3_SWITCH_IP_VERSION_IPV4: + { + ip_address0 = r_layer3_switch_convert_array_to_int(p_frame->p_source_ip_address, 4); + ip_address1 = r_layer3_switch_convert_array_to_int(p_frame->p_destination_ip_address, 4); + + break; + } + + case LAYER3_SWITCH_IP_VERSION_IPV6: + { + /* Extract 4 bytes from the IPv6 address according to the offset configuration. */ + ipv6_offset = R_MFWD->FWIP6OC_b.IP6IPO0; + if ((0 == R_MFWD->FWIP6OC_b.IP6IPOM0) && (NULL != p_frame->p_source_ip_address)) + { + /* Use source IP address. */ + ip_address0 = r_layer3_switch_convert_array_to_int(&p_frame->p_source_ip_address[ipv6_offset], 4); + } + else if ((1 == R_MFWD->FWIP6OC_b.IP6IPOM0) && (NULL != p_frame->p_destination_ip_address)) + { + /* Use destination IP address. */ + ip_address0 = r_layer3_switch_convert_array_to_int(&p_frame->p_destination_ip_address[ipv6_offset], 4); + } + else + { + ip_address0 = 0; + } + + /* Extract additional 4 bytes according to another offset configuration. */ + ipv6_offset = R_MFWD->FWIP6OC_b.IP6IPO1; + if ((0 == R_MFWD->FWIP6OC_b.IP6IPOM1) && (NULL != p_frame->p_source_ip_address)) + { + ip_address1 = r_layer3_switch_convert_array_to_int(&p_frame->p_source_ip_address[ipv6_offset], 4); + } + else if ((1 == R_MFWD->FWIP6OC_b.IP6IPOM1) && (NULL != p_frame->p_destination_ip_address)) + { + ip_address1 = r_layer3_switch_convert_array_to_int(&p_frame->p_destination_ip_address[ipv6_offset], 4); + } + else + { + ip_address1 = 0; + } + + break; + } + + default: + { + break; + } + } + + /* Common for stream filters. */ + p_stream_id->frame_format_code = + r_layer3_switch_calculate_l3_format_code(p_frame); + p_stream_id->words[0] = r_layer3_switch_convert_vlan_tag_to_int(&p_frame->vlan_s_tag, &p_frame->vlan_c_tag); + + if (LAYER3_SWITCH_IP_VERSION_NONE == p_frame->ip_version) + { + /* When Layer2 stream filter. */ + + /* Set destination MAC address. */ + if (NULL != p_frame->p_destination_mac_address) + { + p_stream_id->words[1] = r_layer3_switch_convert_array_to_int(&p_frame->p_destination_mac_address[0], 4); + p_stream_id->words[2] = + r_layer3_switch_convert_array_to_int(&p_frame->p_destination_mac_address[4], 2) << 16; + } + + /* Source address should be input as 2 byte higher part and 4 byte lower part. */ + if (NULL != p_frame->p_source_mac_address) + { + p_stream_id->words[2] |= r_layer3_switch_convert_array_to_int(&p_frame->p_source_mac_address[0], 2); + p_stream_id->words[3] = r_layer3_switch_convert_array_to_int(&p_frame->p_source_mac_address[2], 4); + } + } + else + { + /* When IPv4/IPv6 stream filter. */ + p_stream_id->words[1] = (uint32_t) ((p_frame->layer4_destination_port << 16) | + r_layer3_switch_calculate_l3_hash(p_frame)); + p_stream_id->words[2] = ip_address0; + p_stream_id->words[3] = ip_address1; + } + + return FSP_SUCCESS; +} /* End of function r_layer3_switch_calculate_l3_stream_id() */ + +/******************************************************************************************************************* + * Configure remapping feature for L3 update. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_remapping_l3_update (layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t routing_number, + layer3_switch_l3_update_config_t * p_update_cfg) +{ + uint8_t dest_port = (uint8_t) (31 - __CLZ(p_update_cfg->enable_destination_ports)); + volatile uint32_t * p_mfwd_fwl23urmc_reg = &R_MFWD->FWL23URMC0 + p_instance_ctrl->l3_remapping_number; + fsp_err_t err; + + FSP_ERROR_RETURN(LAYER3_SWITCH_L3_UPDATE_REMAPPING_MAX_NUM >= p_instance_ctrl->l3_remapping_number, + FSP_ERR_WRITE_FAILED); + + /* Learn new l3 update rule. */ + err = r_layer3_switch_learn_l3_update(p_instance_ctrl, p_update_cfg); + + if (FSP_SUCCESS == err) + { + /* Set remapping feature. */ + *p_mfwd_fwl23urmc_reg = (routing_number << R_MFWD_FWL23URMC0_RMRN_Pos) | + (uint32_t) (dest_port << R_MFWD_FWL23URMC0_RMDPN_Pos) | + (uint32_t) ((p_instance_ctrl->l3_routing_number - 1) << R_MFWD_FWL23URMC0_RMNRN_Pos) | + R_MFWD_FWL23URMC0_RME_Msk; + + /* Increment indexes. */ + p_instance_ctrl->l3_routing_number += 1; + p_instance_ctrl->l3_remapping_number += 1; + } + + return err; +} /* End of function r_layer3_switch_remapping_l3_update() */ + +/******************************************************************************************************************* + * Convert VLAN SC-TAG to uint32_t. + * + * @param[in] p_vlan_s_tag Pointer to a VLAN S-TAG. + * @param[in] p_vlan_c_tag Pointer to a VLAN C-TAG. + **********************************************************************************************************************/ +static uint32_t r_layer3_switch_convert_vlan_tag_to_int (layer3_switch_frame_vlan_tag_t const * p_vlan_s_tag, + layer3_switch_frame_vlan_tag_t const * p_vlan_c_tag) +{ + return (uint32_t) ( + (((p_vlan_s_tag->pcp << LAYER3_SWITCH_VLAN_TAG_PCP_POSITION) | + (p_vlan_s_tag->dei << LAYER3_SWITCH_VLAN_TAG_DEI_POSITION) | p_vlan_s_tag->id) << 16) | + ((p_vlan_c_tag->pcp << LAYER3_SWITCH_VLAN_TAG_PCP_POSITION) | + (p_vlan_c_tag->dei << LAYER3_SWITCH_VLAN_TAG_DEI_POSITION) | p_vlan_c_tag->id)); +} /* End of function r_layer3_switch_convert_vlan_tag_to_int() */ + +/******************************************************************************************************************* + * Convert a uint8_t array to int32_t. + * + * @param[in] array Pointer to a array. + **********************************************************************************************************************/ +static uint32_t r_layer3_switch_convert_array_to_int (uint8_t * array, uint8_t length) +{ + uint32_t result = 0; + if (NULL != array) + { + for (int i = 0; i < length; i++) + { + result |= (uint32_t) (array[i] << (8 * (length - 1 - i))); + } + } + + return result; +} /* End of function r_layer3_switch_convert_array_to_int() */ + +/******************************************************************************************************************* + * Configure CBS feature for a port. + **********************************************************************************************************************/ +static void r_layer3_switch_configure_cbs (layer3_switch_instance_ctrl_t const * p_instance_ctrl, + uint8_t port, + layer3_switch_cbs_cfg_t const * p_cbs_cfg) +{ + R_ETHA0_Type * p_etha_reg = + (R_ETHA0_Type *) (R_ETHA0_BASE + (LAYER3_SWITCH_ETHA_REG_SIZE * port)); + + /* CBS registers for the target queue. */ + volatile uint32_t * p_eacaivc_reg; + volatile uint32_t * p_eacaulc_reg; + + double bandwidth_fraction; + double civ_raw_value; + uint32_t civ_int_value; + uint32_t max_interference_size; + uint8_t enable_cbs_bitmask = 0; + uint32_t eswclk_frequency; + uint32_t link_speed = 0; + ether_phy_instance_t const * p_phy_instance = + ((layer3_switch_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->p_ether_phy_instances[port]; + + /*Get frequency of ESWCLK. */ + eswclk_frequency = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) (R_SYSTEM->ESWCKCR_b.CKSEL)) / + R_FSP_ClockDividerGet(R_SYSTEM->ESWCKDIVCR_b.CKDIV); + + /* Get link speed. */ + switch (p_phy_instance->p_cfg->mii_type) + { + /* 100 Mbps. */ + case ETHER_PHY_MII_TYPE_MII: + case ETHER_PHY_MII_TYPE_RMII: + { + link_speed = LAYER3_SWITCH_LINK_SPEED_100M; + break; + } + + /* 1000 Mbps. */ + case ETHER_PHY_MII_TYPE_GMII: + case ETHER_PHY_MII_TYPE_RGMII: + { + link_speed = LAYER3_SWITCH_LINK_SPEED_1G; + break; + } + + default: + { + break; + } + } + + for (uint8_t i = 0; i < BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM; i++) + { + if (0 != p_cbs_cfg->band_width_list[i]) + { + p_eacaivc_reg = (volatile uint32_t *) ((uint8_t *) &p_etha_reg->EACAIVC0 + (4 * i)); + p_eacaulc_reg = (volatile uint32_t *) ((uint8_t *) &p_etha_reg->EACAULC0 + (4 * i)); + + /* Calculate CIV (Credit Increment Value). */ + bandwidth_fraction = p_cbs_cfg->band_width_list[i] / 100.0; + civ_raw_value = (link_speed / LAYER3_SWITCH_CBS_BITS_PER_BYTE) * bandwidth_fraction / eswclk_frequency; + civ_int_value = + (uint32_t) (((uint8_t) civ_raw_value << 16) | (uint16_t) (civ_raw_value * (UINT16_MAX + 1))); + + /* Set CIV value to the register. */ + *p_eacaivc_reg = civ_int_value; + + /* Calculate credit upper limit. */ + max_interference_size = r_layer3_switch_calculate_max_interference_size(i, p_cbs_cfg->max_burst_num_list); + *p_eacaulc_reg = 0 * + max_interference_size * + (eswclk_frequency / (link_speed + LAYER3_SWITCH_CBS_REQUEST_DELAY)) * civ_int_value; + enable_cbs_bitmask |= (1 << i); + } + } + + /* Enable and apply CBS configuration. */ + p_etha_reg->EACAEC = enable_cbs_bitmask; + p_etha_reg->EACC = enable_cbs_bitmask; +} /* End of function r_layer3_switch_configure_cbs() */ + +/******************************************************************************************************************* + * Calculate max interference size which used to configure CBS. + **********************************************************************************************************************/ +static uint32_t r_layer3_switch_calculate_max_interference_size (uint8_t queue_number, + uint8_t const * p_max_burst_num_list) +{ + uint32_t queue_interference_size = (LAYER3_SWITCH_MAXIMUM_FRAME_SIZE + LAYER3_SWITCH_CBS_INTERFERENCE_SIZE_OFFSET) * + LAYER3_SWITCH_CBS_BITS_PER_BYTE; + uint32_t queue_interference_size_low = 0; + uint32_t queue_interference_size_high = 0; + + /* Get the interference size of the queues with lower priority than the target queue. */ + if (queue_number > 0) + { + queue_interference_size_low = (LAYER3_SWITCH_MAXIMUM_FRAME_SIZE + LAYER3_SWITCH_CBS_INTERFERENCE_SIZE_OFFSET) * + LAYER3_SWITCH_CBS_BITS_PER_BYTE; + } + + /* Get the interference size of the queues with higher priority than the target queue. */ + for (uint8_t i = queue_number + 1; i < BSP_FEATURE_ESWM_ETHA_IPV_QUEUE_NUM; i++) + { + if (0 != p_max_burst_num_list[i]) + { + queue_interference_size_high += + (LAYER3_SWITCH_MAXIMUM_FRAME_SIZE * 2 + LAYER3_SWITCH_CBS_INTERFERENCE_SIZE_OFFSET * 2) * + LAYER3_SWITCH_CBS_BITS_PER_BYTE; + } + else + { + queue_interference_size_high += + ((p_max_burst_num_list[i] + 1) * LAYER3_SWITCH_MAXIMUM_FRAME_SIZE + + LAYER3_SWITCH_CBS_INTERFERENCE_SIZE_OFFSET * 2) * LAYER3_SWITCH_CBS_BITS_PER_BYTE; + } + } + + return queue_interference_size_low + queue_interference_size + queue_interference_size_high; +} /* End of function r_layer3_switch_calculate_max_interference_size() */ + +/*********************************************************************************************************************** + * Create queue of transmission timestamp. + ***********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_create_tx_timestamp_queue (ether_switch_ctrl_t * const p_ctrl, + const layer3_switch_descriptor_queue_cfg_t * const p_queue_cfg, + uint32_t * const p_ts_descriptor_queue_index) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_ctrl; + layer3_switch_extended_cfg_t * p_extend; + layer3_switch_ts_reception_process_descriptor_t * p_ts_descriptor; + + volatile uint32_t * p_gwtsdcc_reg; /* Timestamp Descriptor Chain Configuration */ + volatile uint32_t * p_gwtdcac0_reg; /* Timestamp Descriptor Chain Address Configuration 0 */ + volatile uint32_t * p_gwtdcac1_reg; /* Timestamp Descriptor Chain Address Configuration 1 */ + + uint8_t port = (uint8_t) (1 & (p_queue_cfg->ports >> 1)); + + p_extend = (layer3_switch_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Search TS descriptor queue can use. */ + uint32_t ts_descriptor_queue_index = 0; + for (ts_descriptor_queue_index = 0; + ts_descriptor_queue_index < BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM; + ts_descriptor_queue_index++) + { + if (port == ts_descriptor_queue_index) + { + if (LAYER3_SWITCH_TS_DESCRIPTOR_QUEUE_STATUS_UNUSED == + p_instance_ctrl->ts_descriptor_queue_status_list[ts_descriptor_queue_index]) + { + break; + } + } + } + + FSP_ERROR_RETURN(BSP_FEATURE_ESWM_TS_DESCRIPTOR_QUEUE_MAX_NUM > ts_descriptor_queue_index, FSP_ERR_OVERFLOW); + + p_ts_descriptor = p_queue_cfg->p_ts_descriptor_array; + + /* Initialize TS descriptor in queue. */ + for (uint8_t i = 0; i < (p_queue_cfg->array_length - 1); i++) + { + p_ts_descriptor[i].ts_reception_descriptor_basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_ND; + p_ts_descriptor[i].ts_reception_descriptor_basic.die = 1; + } + + p_ts_descriptor[(p_queue_cfg->array_length - + 1)].ts_reception_descriptor_basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_LINKFIX; + p_ts_descriptor[(p_queue_cfg->array_length - + 1)].ts_reception_descriptor_basic.ptr_l = (uintptr_t) p_ts_descriptor; + + /* Set GWCA to CONFIG mode. */ + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_CONFIG); + + p_gwtdcac0_reg = (volatile uint32_t *) ((uint8_t *) &p_instance_ctrl->p_gwca_reg->GWTDCAC00 + + (LAYER3_SWITCH_TS_DESCRIPTOR_QUEUE_REGISTOR_OFFSET * + ts_descriptor_queue_index)); + + p_gwtdcac1_reg = (volatile uint32_t *) ((uint8_t *) &p_instance_ctrl->p_gwca_reg->GWTDCAC10 + + (LAYER3_SWITCH_TS_DESCRIPTOR_QUEUE_REGISTOR_OFFSET * + ts_descriptor_queue_index)); + + *p_gwtdcac1_reg = (uintptr_t) p_ts_descriptor; + *p_gwtdcac0_reg = 0; + + p_gwtsdcc_reg = (volatile uint32_t *) ((uint8_t *) &p_instance_ctrl->p_gwca_reg->GWTSDCC0 + + (LAYER3_SWITCH_TS_DESCRIPTOR_TIMER_REGISTOR_OFFSET * + p_extend->gptp_timer_numbers[port])); + + *p_gwtsdcc_reg = ((1U << R_GWCA0_GWTSDCC0_TE_Pos) | + (ts_descriptor_queue_index << R_GWCA0_GWTSDCC0_DCS_Pos)); + + /* Set GWCA to OPERATION mode. */ + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_gwca_operation_mode(p_instance_ctrl, LAYER3_SWITCH_AGENT_MODE_OPERATION); + + /* Output TS Descriptor queue index and change state used. */ + *p_ts_descriptor_queue_index = ts_descriptor_queue_index; + p_instance_ctrl->ts_descriptor_queue_status_list[ts_descriptor_queue_index] = + LAYER3_SWITCH_TS_DESCRIPTOR_QUEUE_STATUS_USED; + + return FSP_SUCCESS; +} /* End of function r_layer3_switch_create_tx_timestamp_queue() */ + +/******************************************************************************************************************* + * FRER initialization. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_frer_init (layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_frer_cfg_t const * p_frer_cfg) +{ + volatile uint32_t * p_fwseqngc_reg; + +#if LAYER3_SWITCH_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(p_frer_cfg, FSP_ERR_INVALID_POINTER); +#endif + + r_layer3_switch_frer_table_reset(); + + /* Set FRER timeout us prescaler 1 MHz to derive the timeout 1 kHz clock. */ + R_MFWD->FWFTOPC_b.USP = p_frer_cfg->sys_clock & LAYER3_SWITCH_FRER_SYSTEM_CLOCK_BITMASK; + R_MFWD->FWFTOC_b.TOCE = p_frer_cfg->timeout_enable & 0x1U; + R_MFWD->FWFTOC_b.TOT = p_frer_cfg->check_period & LAYER3_SWITCH_FRER_CHECK_PERIOD_BITMASK; + + /* Sequence number generation reset n (n = 0 to 31). */ + R_MFWD->FWSEQNRC_b.SEQNR |= R_MFWD_FWSEQNRC_SEQNR_Msk; + + /* FWSEQNGCi(i = 0~31) 0 write. */ + for (uint32_t i = 0; i < LAYER3_SWITCH_SEQ_REG_MAX_NUM; i++) + { + p_fwseqngc_reg = + (uint32_t *) ((uintptr_t) (&R_MFWD->FWSEQNGC0) + (i * LAYER3_SWITCH_FWSEQNGC_REGISTER_OFFSET)); + *p_fwseqngc_reg = 0; + } + + /*SEQNR 0 write. */ + R_MFWD->FWSEQNRC_b.SEQNR &= ~R_MFWD_FWSEQNRC_SEQNR_Msk; + + /* Reset current register index. */ + p_instance_ctrl->valid_frer_entry_num = 0; + + R_MFWD->FWSEQNRC |= R_MFWD_FWSEQNRC_SEQNR_Msk; + for (uint32_t i = 0; i < LAYER3_SWITCH_SEQ_REG_MAX_NUM; i++) + { + p_fwseqngc_reg = + (uint32_t *) ((uintptr_t) (&R_MFWD->FWSEQNGC0) + (i * LAYER3_SWITCH_FWSEQNGC_REGISTER_OFFSET)); + *p_fwseqngc_reg = 0; + } + + R_MFWD->FWSEQNRC &= ~R_MFWD_FWSEQNRC_SEQNR_Msk; + + p_instance_ctrl->used_frer_sequence_generator_num = 0; + + return FSP_SUCCESS; +} /* End of function r_layer3_switch_frer_init() */ + +/******************************************************************************************************************* + * Reset FRER table. + **********************************************************************************************************************/ +static void r_layer3_switch_frer_table_reset (void) +{ + R_MFWD->FWFTIM_b.FTIOG = R_MFWD_FWFTIM_FTIOG_Msk; /* FRER Table Initialization Ongoing */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWFTIM_b.FTR, 1); /* FRER Table Ready */ +} /* End of function r_layer3_switch_frer_table_reset() */ + +/******************************************************************************************************************* + * Configure sequence number generate. + **********************************************************************************************************************/ +static void r_layer3_switch_configure_sequence_number_generation (layer3_switch_instance_ctrl_t * p_instance_ctrl) +{ + volatile uint32_t * p_fwseqngc_reg; + uint32_t fwseqngc_reg_value; + + /* Get FWSEQNGCi register address. */ + p_fwseqngc_reg = + (uint32_t *) ((uintptr_t) (&R_MFWD->FWSEQNGC0) + + ((p_instance_ctrl->used_frer_sequence_generator_num & + LAYER3_SWITCH_FRER_SEQ_GENERATOR_NUM_BITMASK) * + LAYER3_SWITCH_FWSEQNGC_REGISTER_OFFSET)); + fwseqngc_reg_value = *p_fwseqngc_reg; + + /* Sequence generation enable. Routing number set. Sequence number generate valid. */ + fwseqngc_reg_value |= (p_instance_ctrl->l3_routing_number & R_MFWD_FWSEQNGC0_SEQNGRN_Msk) | + (1U << R_MFWD_FWSEQNGC0_SEQNGE_Pos); + *p_fwseqngc_reg = fwseqngc_reg_value; +} /* End of function r_layer3_switch_configure_sequence_number_generation() */ + +/******************************************************************************************************************* + * Learn an entry of FRER table. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_learn_frer_entry (layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_frer_entry_t * const p_frer_entry, + layer3_switch_frer_entry_t * const p_sequence_recovery, + uint32_t sequence_recovery_id) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t sequence_recovery_addr = 0; + + if (NULL != p_sequence_recovery) + { + sequence_recovery_addr = + p_instance_ctrl->frer_sequence_recovery_status[sequence_recovery_id & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK].frer_entry_index & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK; + } + + /* Set entry address and sequence recovery pointer. */ + R_MFWD->FWFTL0 = (R_MFWD_FWFTL0_FSRPL_Msk & (sequence_recovery_addr << R_MFWD_FWFTL0_FSRPL_Pos)) | + (R_MFWD_FWFTL0_FEAL_Msk & (p_instance_ctrl->valid_frer_entry_num << R_MFWD_FWFTL0_FEAL_Pos)); + + /* Set sequence recovery settings. */ + R_MFWD->FWFTL1 = + (R_MFWD_FWFTL1_FSHLL_Msk & (p_frer_entry->sequence_history_len << R_MFWD_FWFTL1_FSHLL_Pos)) | + (R_MFWD_FWFTL1_FTNSL_Msk & (p_frer_entry->take_no_sequence << R_MFWD_FWFTL1_FTNSL_Pos)) | + (R_MFWD_FWFTL1_FSRPVL_Msk & + (uint32_t) ((NULL != p_sequence_recovery) << R_MFWD_FWFTL1_FSRPVL_Pos)) | + (R_MFWD_FWFTL1_FSRRTL_Msk & (p_frer_entry->set_recovery_remaining_tick << R_MFWD_FWFTL1_FSRRTL_Pos)); + + /* Wait for learning complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_MFWD->FWFTLR_b.FTL, 0); + + /* Check learning error. */ + if (1 == R_MFWD->FWFTLR_b.FLF) + { + err = FSP_ERR_WRITE_FAILED; + } + else + { + /* Store the entry information to sequence recovery table. */ + if (NULL == p_sequence_recovery) + { + p_instance_ctrl->frer_sequence_recovery_status[sequence_recovery_id & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK].learned = + true; + p_instance_ctrl->frer_sequence_recovery_status[sequence_recovery_id & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK].frer_entry_index = + p_instance_ctrl->valid_frer_entry_num & LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK; + } + + /* Update the current index of the FRER table. */ + p_instance_ctrl->valid_frer_entry_num = (p_instance_ctrl->valid_frer_entry_num + 1) & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK; + } + + return err; +} /* End of function r_layer3_switch_learn_frer_entry() */ + +/******************************************************************************************************************* + * Learn a individual recovery entry of FRER entry. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_learn_frer_individual_recovery (layer3_switch_instance_ctrl_t * p_instance_ctrl, + layer3_switch_frer_entry_cfg_t * const p_frer_entry_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + /* When the target sequence recovery has not been learned, first learn the sequence recovery entry. */ + if ((NULL != p_frer_entry_cfg->p_sequence_recovery) && + (false == + p_instance_ctrl->frer_sequence_recovery_status[p_frer_entry_cfg->sequence_recovery_id & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK].learned)) + { + r_layer3_switch_learn_frer_entry(p_instance_ctrl, + p_frer_entry_cfg->p_sequence_recovery, + NULL, + p_frer_entry_cfg->sequence_recovery_id & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK); + } + + /* Add the FRER individual recovery entry. */ + err = r_layer3_switch_learn_frer_entry(p_instance_ctrl, + &p_frer_entry_cfg->individual_recovery, + p_frer_entry_cfg->p_sequence_recovery, + p_frer_entry_cfg->sequence_recovery_id & + LAYER3_SWITCH_FRER_ENTRY_NUM_BITMASK); + + return err; +} /* End of function r_layer3_switch_learn_frer_individual_recovery() */ + +/*******************************************************************************************************************//** + * Select MSDU filter ID to use. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_psfp_select_msdu_filter_id (layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t * p_msdu_filter_id, + layer3_switch_psfp_msdu_filter_cfg_t * p_psfp_msdu_filter_cfg) +{ + fsp_err_t err = FSP_ERR_BUFFER_EMPTY; + + /* Set new PSFP MSDU filter. */ + if (LAYER3_SWITCH_PSFP_FILTER_STATUS_UNUSED == + p_instance_ctrl->psfp_msdu_filter_info_list[p_psfp_msdu_filter_cfg->msdu_filter_id].status) + { + /* Decide which internal PSFP MSDU filter ID to use. */ + for (uint8_t unused_id = 0; + unused_id < BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM; + unused_id++) + { + /* Use an unused PSFP MSDU filter ID. */ + if (LAYER3_SWITCH_PSFP_FILTER_STATUS_UNUSED == + p_instance_ctrl->psfp_msdu_filter_info_list[unused_id].status) + { + *p_msdu_filter_id = unused_id; + err = FSP_SUCCESS; + break; + } + } + } + + return err; +} /* End of function r_layer3_switch_psfp_select_msdu_filter_id() */ + +/*******************************************************************************************************************//** + * Select Meter filter ID to use. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_psfp_select_meter_filter_id (layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t * p_meter_filter_id, + layer3_switch_psfp_meter_filter_cfg_t * p_psfp_meter_filter_cfg) +{ + fsp_err_t err = FSP_ERR_BUFFER_EMPTY; + + uint32_t minimum_id = 0; + uint32_t maximum_id = 0; + + /* Set new PSFP Meter filter. */ + if (LAYER3_SWITCH_PSFP_FILTER_STATUS_UNUSED == + p_instance_ctrl->psfp_meter_filter_info_list[p_psfp_meter_filter_cfg->meter_filter_id].status) + { + /* Use single (green) bucket. */ + if (0 == p_psfp_meter_filter_cfg->eir) + { + minimum_id = BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM; + maximum_id = BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM; + } + /* Use double (green and yellow) bucket. */ + else + { + minimum_id = 0; + maximum_id = BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM; + } + + /* Decide which internal PSFP Meter filter ID to use. */ + for (uint32_t unused_id = minimum_id; + unused_id < maximum_id; + unused_id++) + { + /* Use an unused PSFP Meter filter ID. */ + if (LAYER3_SWITCH_PSFP_FILTER_STATUS_UNUSED == + p_instance_ctrl->psfp_meter_filter_info_list[unused_id].status) + { + *p_meter_filter_id = unused_id; + err = FSP_SUCCESS; + break; + } + } + } + + return err; +} /* End of function r_layer3_switch_psfp_select_meter_filter_id() */ + +/*******************************************************************************************************************//** + * Initialize PSFP MSDU filter. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_psfp_msdu_filter_init (layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t msdu_filter_id, + layer3_switch_table_entry_cfg_t const * const p_table_entry_cfg) +{ + volatile uint32_t * p_fwpmfgc_reg; + + layer3_switch_psfp_msdu_filter_cfg_t * p_psfp_msdu_filter_cfg = p_table_entry_cfg->p_psfp_msdu_filter_cfg; + + FSP_ERROR_RETURN(BSP_FEATURE_ESWM_PSFP_MSDU_FILTER_MAX_NUM > msdu_filter_id, FSP_ERR_BUFFER_EMPTY); + + /* Select which FWPMFGC0 to FWPMFGC15 register to use. */ + p_fwpmfgc_reg = (volatile uint32_t *) ((uint8_t *) &R_MFWD->FWPMFGC0 + \ + (LAYER3_SWITCH_PSFP_MSDU_FILTER_REGISTER_OFFSET * msdu_filter_id)); + + /* Enable or disable the MSDU filter. */ + R_MFWD->FWEIE2_b.PMFE = (1U << msdu_filter_id); + + /* Configure the MSDU filter mode and maximum frame size. */ + *p_fwpmfgc_reg = ((p_psfp_msdu_filter_cfg->maximum_frame_size << R_MFWD_FWPMFGC0_MSDUV_Pos) | + ((uint32_t) p_psfp_msdu_filter_cfg->mode << R_MFWD_FWPMFGC0_MFM_Pos)); + + /* Allow first packet, then keep dropping. */ + if ((LAYER3_SWITCH_MSDU_FILTER_THROTTLE_MODE == p_psfp_msdu_filter_cfg->mode) && + ((R_MFWD->FWEIS2_b.PMFS & (1U << msdu_filter_id)) != 0)) + { + /* Initialize FWEIS2_b.PMFS. */ + R_MFWD->FWEIS2_b.PMFS |= (1U << msdu_filter_id); + } + /* Allow first packet, then stop dropping (default behavior). */ + else + { + /* Do nothing */ + } + + /* Store internal MSDU filter ID. */ + p_instance_ctrl->psfp_msdu_filter_info_list[p_psfp_msdu_filter_cfg->msdu_filter_id].msdu_filter_hw_id = + msdu_filter_id; + p_instance_ctrl->psfp_msdu_filter_info_list[p_psfp_msdu_filter_cfg->msdu_filter_id].status = + LAYER3_SWITCH_PSFP_FILTER_STATUS_USED; + + /* Set configuration MSDU filter. */ + p_instance_ctrl->psfp_msdu_filter_info_list[p_psfp_msdu_filter_cfg->msdu_filter_id].p_psfp_msdu_filter_cfg = + p_psfp_msdu_filter_cfg; + + return FSP_SUCCESS; +} /* End of function r_layer3_switch_psfp_msdu_filter_init() */ + +/*******************************************************************************************************************//** + * Initialize PSFP Meter filter setting. + **********************************************************************************************************************/ +static fsp_err_t r_layer3_switch_psfp_meter_filter_init (layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint32_t meter_filter_id, + layer3_switch_table_entry_cfg_t const * const p_table_entry_cfg) +{ + uint16_t yellow_only_bitmask = 0; + + volatile uint32_t * p_mfwd_fwpmtrfc_reg; + volatile uint32_t * p_mfwd_fwpmtrfm_reg; + volatile uint32_t * p_mfwd_fwpmtrcbsc_reg; + volatile uint32_t * p_mfwd_fwpmtrcirc_reg; + volatile uint32_t * p_mfwd_fwpmtrebsc_reg; + volatile uint32_t * p_mfwd_fwpmtreirc_reg; + + layer3_switch_psfp_meter_filter_cfg_t * p_psfp_meter_filter_cfg = p_table_entry_cfg->p_psfp_meter_filter_cfg; + + FSP_ERROR_RETURN(BSP_FEATURE_ESWM_PSFP_METER_FILTER_SINGLE_BUCKET_METERS_MAX_NUM > meter_filter_id, + FSP_ERR_BUFFER_EMPTY); + FSP_ERROR_RETURN(LAYER3_SWITCH_METER_FILTER_PCP_MAX_NUM >= p_psfp_meter_filter_cfg->pcp_handling_policy, + FSP_ERR_INVALID_ARGUMENT); + + p_mfwd_fwpmtrfc_reg = (uint32_t *) ((uintptr_t) &R_MFWD->FWPMTRFC0 + + (meter_filter_id * LAYER3_SWITCH_PSFP_METER_FILTER_REG_OFFSET)); + + p_mfwd_fwpmtrfm_reg = (uint32_t *) ((uintptr_t) &R_MFWD->FWPMTRFM0 + + (meter_filter_id * LAYER3_SWITCH_PSFP_METER_FILTER_REG_OFFSET)); + + /* Disable Meter filter. */ + *p_mfwd_fwpmtrfc_reg = 0; + FSP_HARDWARE_REGISTER_WAIT((*p_mfwd_fwpmtrfm_reg & R_MFWD_FWPMTRFM0_MTRARDN_Msk), 0); + + /* Reset Meter status. If (ATS) throttle mode, stop rejecting frame. */ + R_MFWD->FWEIS5_b.PMRFS |= (1U << meter_filter_id); + + p_mfwd_fwpmtrcbsc_reg = (uint32_t *) ((uintptr_t) &R_MFWD->FWPMTRCBSC0 + + (meter_filter_id * LAYER3_SWITCH_PSFP_METER_FILTER_REG_OFFSET)); + + p_mfwd_fwpmtrcirc_reg = (uint32_t *) ((uintptr_t) &R_MFWD->FWPMTRCIRC0 + + (meter_filter_id * LAYER3_SWITCH_PSFP_METER_FILTER_REG_OFFSET)); + + *p_mfwd_fwpmtrcbsc_reg = R_MFWD_FWPMTRCBSC0_CBS_Msk & (p_psfp_meter_filter_cfg->cbs << R_MFWD_FWPMTRCBSC0_CBS_Pos); + *p_mfwd_fwpmtrcirc_reg = R_MFWD_FWPMTRCIRC0_CIR_Msk & (p_psfp_meter_filter_cfg->cir << R_MFWD_FWPMTRCIRC0_CIR_Pos); + + if (BSP_FEATURE_ESWM_PSFP_METER_FILTER_DOUBLE_BUCKET_METERS_MAX_NUM > meter_filter_id) + { + p_mfwd_fwpmtrebsc_reg = (uint32_t *) ((uintptr_t) &R_MFWD->FWPMTREBSC0 + + (meter_filter_id * LAYER3_SWITCH_PSFP_METER_FILTER_REG_OFFSET)); + + p_mfwd_fwpmtreirc_reg = (uint32_t *) ((uintptr_t) &R_MFWD->FWPMTREIRC0 + + (meter_filter_id * LAYER3_SWITCH_PSFP_METER_FILTER_REG_OFFSET)); + + *p_mfwd_fwpmtrebsc_reg = R_MFWD_FWPMTREBSC0_EBS_Msk & + (p_psfp_meter_filter_cfg->ebs << R_MFWD_FWPMTREBSC0_EBS_Pos); + *p_mfwd_fwpmtreirc_reg = R_MFWD_FWPMTREIRC0_EIR_Msk & + (p_psfp_meter_filter_cfg->eir << R_MFWD_FWPMTREIRC0_EIR_Pos); + + *p_mfwd_fwpmtrfc_reg |= (R_MFWD_FWPMTRFC0_MTRCF_Msk & + ((uint32_t) p_psfp_meter_filter_cfg->coupling_enable << R_MFWD_FWPMTRFC0_MTRCF_Pos)); + + /* Treat a frame as yellow when the PCP value is less than the upper limit. */ + yellow_only_bitmask = (uint16_t) ((1 << ((p_psfp_meter_filter_cfg->pcp_handling_policy) * 2)) - 1); + + if (LAYER3_SWITCH_METER_FILTER_DEI_HANDLING_POLICY_YELLOW == p_psfp_meter_filter_cfg->dei_handling_policy) + { + /* Treat a frame as yellow when the DEI is 1. */ + yellow_only_bitmask |= LAYER3_SWITCH_METER_FILTER_DEI_HANDLING_POLICY_BITMASK; + } + + *p_mfwd_fwpmtrfc_reg |= + (R_MFWD_FWPMTRFC0_MTRCM_Msk & + ((uint32_t) yellow_only_bitmask << R_MFWD_FWPMTRFC0_MTRCM_Pos)); + } + + *p_mfwd_fwpmtrfc_reg |= ((R_MFWD_FWPMTRFC0_MTRFE_Msk & + (1U << R_MFWD_FWPMTRFC0_MTRFE_Pos)) | + (R_MFWD_FWPMTRFC0_MTRFM_Msk & + ((uint32_t) p_psfp_meter_filter_cfg->mode << R_MFWD_FWPMTRFC0_MTRFM_Pos)) | + (R_MFWD_FWPMTRFC0_MTRFRFD_Msk & + ((uint32_t) p_psfp_meter_filter_cfg->drop_red_frame << R_MFWD_FWPMTRFC0_MTRFRFD_Pos))); + R_MFWD->FWEIE5_b.PMRFE |= (1 << meter_filter_id); + + /* Store internal Meter filter ID. */ + p_instance_ctrl->psfp_meter_filter_info_list[p_psfp_meter_filter_cfg->meter_filter_id].meter_filter_hw_id = + meter_filter_id; + p_instance_ctrl->psfp_meter_filter_info_list[p_psfp_meter_filter_cfg->meter_filter_id].status = + LAYER3_SWITCH_PSFP_FILTER_STATUS_USED; + + /* Set configuration Meter filter. */ + p_instance_ctrl->psfp_meter_filter_info_list[p_psfp_meter_filter_cfg->meter_filter_id].p_psfp_meter_filter_cfg = + p_psfp_meter_filter_cfg; + + return FSP_SUCCESS; +} /* End of function r_layer3_switch_psfp_meter_filter_init() */ + +/******************************************************************************************************************* + * Calls user callback for each ports. + * + * @param[in] p_instance_ctrl Pointer to a instance control. + * @param[in] p_callback_args Pointer to callback args. + * @param[in] ports Ports that should call user callback. + **********************************************************************************************************************/ +static void r_layer3_switch_call_callback_for_ports (layer3_switch_instance_ctrl_t * p_instance_ctrl, + ether_switch_callback_args_t * p_callback_args, + uint32_t ports) +{ + /* Call port-specific callback for each port. */ + for (uint8_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + /* Check if event occurred on this port. */ + if (0 != (ports & (1 << i))) + { + if (NULL != p_instance_ctrl->p_port_cfg_list[i].p_callback) + { + p_callback_args->p_context = p_instance_ctrl->p_port_cfg_list[i].p_context; + r_layer3_switch_call_callback(p_instance_ctrl->p_port_cfg_list[i].p_callback, + p_callback_args, + p_instance_ctrl->p_port_cfg_list[i].p_callback_memory); + } + } + } +} /* End of function r_layer3_switch_call_callback_for_ports() */ + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_callback Function pointer to target callback + * @param[in] p_callback_args Pointer to callback args + * @param[in] p_callback_memory Pointer to memory allocated for callback arguments + **********************************************************************************************************************/ +static void r_layer3_switch_call_callback (void (* p_callback)( + ether_switch_callback_args_t *), + ether_switch_callback_args_t * p_callback_args, + ether_switch_callback_args_t * const p_callback_memory) +{ + ether_switch_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + ether_switch_callback_args_t * p_args = p_callback_memory; + + if (NULL == p_args) + { + /* Store on stack. */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + memcpy(p_args, p_callback_args, sizeof(ether_switch_callback_args_t)); + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + layer3_switch_prv_ns_callback p_ns_callback = (layer3_switch_prv_ns_callback) (p_callback); + p_ns_callback(p_args); + } + +#else + + /* If the project is not TrustZone Secure, then it will never need to change security state in order to call the callback. */ + p_callback(p_args); +#endif + + if (NULL != p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_callback_memory = args; + } +} /* End of function r_layer3_switch_call_callback() */ + +/*******************************************************************************************************************//** + * Enables or disables frame preemption feature based on the preemption_enable parameter. + **********************************************************************************************************************/ +static void r_layer3_switch_enable_frame_preemption_feature (layer3_switch_instance_ctrl_t * p_instance_ctrl, + uint8_t port, + bool preemption_enable) +{ + layer3_switch_extended_cfg_t * p_extend = (layer3_switch_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + R_ETHA0_Type * p_etha_reg = + (R_ETHA0_Type *) (R_ETHA0_BASE + (LAYER3_SWITCH_ETHA_REG_SIZE * port)); + layer3_switch_agent_mode_t previous_mode = (layer3_switch_agent_mode_t) p_etha_reg->EAMS_b.OPS; + + /* Change ETHA to CONFIG mode. */ + if (LAYER3_SWITCH_AGENT_MODE_CONFIG != previous_mode) + { + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_CONFIG); + } + + if (preemption_enable) + { + /* Enable sending preemptable frames. */ + p_etha_reg->EATPEC = (p_extend->ipv_queue_preemptable_bitmask[port] << R_ETHA0_EATPEC_TTQ0_Pos) | + (R_ETHA0_EATPEC_AFS_Msk & + (uint32_t) (p_extend->frame_preemption_fragment_size[port] << + R_ETHA0_EATPEC_AFS_Pos)); + } + else + { + /* Disable sending preemptable frames. All TX queues will send express frames. */ + p_etha_reg->EATPEC = 0; + } + + /* Change ETHA to the previous mode. */ + if (LAYER3_SWITCH_AGENT_MODE_CONFIG != previous_mode) + { + r_layer3_switch_update_etha_operation_mode(port, LAYER3_SWITCH_AGENT_MODE_DISABLE); + r_layer3_switch_update_etha_operation_mode(port, previous_mode); + } + + p_instance_ctrl->frame_preemption_available[port] = preemption_enable; +} + +/*******************************************************************************************************************//** + * Callback for r_rmac_phy interrupts. + **********************************************************************************************************************/ +static void r_layer3_switch_rmac_phy_interrupts_callback (ether_phy_callback_args_t * p_args) +{ + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) p_args->p_context; + + switch (p_args->event) + { + /* Frame preemption is available. */ + case ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_SUCCESS: + case ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_RECEIVE: + { + if (!p_instance_ctrl->frame_preemption_available[p_args->port]) + { + r_layer3_switch_enable_frame_preemption_feature(p_instance_ctrl, (uint8_t) p_args->port, true); + } + + break; + } + + /* Frame preemption is not available. */ + case ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_FAIL: + { + if (p_instance_ctrl->frame_preemption_available[p_args->port]) + { + r_layer3_switch_enable_frame_preemption_feature(p_instance_ctrl, (uint8_t) p_args->port, false); + } + + break; + } + + default: + { + break; + } + } +} + +/*********************************************************************************************************************** + * Function Name: layer3_switch_gwdi_isr + * Description : Interrupt handler for GWCA data interrupts that includes RX/TX complete and buffer full error events. + * Arguments : none + * Return Value : none + ***********************************************************************************************************************/ +void layer3_switch_gwdi_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + ether_switch_callback_args_t callback_arg = {}; + bool port_callback_exists = false; + + uint32_t gwdi_status; + uint32_t gwei2_status; + volatile uint32_t * p_gwca_gwdi_reg; + volatile uint32_t * p_gwca_gwei2_reg; + + /* Check if port-specific callbacks are set. */ + for (uint8_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + if (NULL != p_instance_ctrl->p_port_cfg_list[i].p_callback) + { + port_callback_exists = true; + break; + } + } + + /* Get queue ISR happened. */ + for (uint32_t i = 0; i < (LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM / LAYER3_SWITCH_REGISTER_SIZE) + 1; i++) + { + /* Get status register address. */ + p_gwca_gwdi_reg = + (uint32_t *) ((uintptr_t) &(p_instance_ctrl->p_gwca_reg->GWDIS0) + + (i * LAYER3_SWITCH_INTERRUPT_REGISTER_OFFSET)); + p_gwca_gwei2_reg = + (uint32_t *) ((uintptr_t) &(p_instance_ctrl->p_gwca_reg->GWEIS20) + + (i * LAYER3_SWITCH_INTERRUPT_REGISTER_OFFSET)); + + /* Copy status bits. GWDI occur when a descriptor complete RX/TX. GWEI2 occur when receive frame for full RX queue. */ + gwdi_status = *p_gwca_gwdi_reg; + gwei2_status = *p_gwca_gwei2_reg; + + /* Clear status bits. */ + *p_gwca_gwdi_reg = gwdi_status; + *p_gwca_gwei2_reg = gwei2_status; + + /* If a callback is provided, then call it with callback argument. */ + if ((NULL != p_instance_ctrl->p_callback) || port_callback_exists) + { + callback_arg.channel = p_instance_ctrl->p_cfg->channel; + + for (uint32_t j = 0; j < (LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM % LAYER3_SWITCH_REGISTER_SIZE); j++) + { + /* Check RX/TX complete event. */ + if (gwdi_status & (1 << j)) + { + /* Store index of queue. */ + callback_arg.queue_index = j + (i * LAYER3_SWITCH_REGISTER_SIZE); + callback_arg.ports = + p_instance_ctrl->p_queues_status[callback_arg.queue_index].p_queue_cfg->ports; + + /* Store that the event is RX or TX. */ + if (LAYER3_SWITCH_QUEUE_TYPE_RX == + p_instance_ctrl->p_queues_status[callback_arg.queue_index].p_queue_cfg->type) + { + /* Check if queue is active. */ + if (r_layer3_switch_is_descriptor_queue_active(p_instance_ctrl, callback_arg.queue_index)) + { + callback_arg.event = ETHER_SWITCH_EVENT_RX_COMPLETE; + } + else + { + callback_arg.event = ETHER_SWITCH_EVENT_RX_QUEUE_FULL; + + /* Clear the status bit. */ + *p_gwca_gwdi_reg = (1 << j); + } + } + else + { + callback_arg.event = ETHER_SWITCH_EVENT_TX_COMPLETE; + } + + r_layer3_switch_call_callback_for_ports(p_instance_ctrl, &callback_arg, callback_arg.ports); + + /* Do not callback other event for the same queue. */ + continue; + } + + /* Check RX descriptor queue full error event. */ + if (gwei2_status & (1 << j)) + { + /* Store index of queue. */ + callback_arg.queue_index = j + (i * LAYER3_SWITCH_REGISTER_SIZE); + callback_arg.ports = + p_instance_ctrl->p_queues_status[callback_arg.queue_index].p_queue_cfg->ports; + callback_arg.event = ETHER_SWITCH_EVENT_RX_MESSAGE_LOST; + + r_layer3_switch_call_callback_for_ports(p_instance_ctrl, &callback_arg, callback_arg.ports); + } + } + } + } + + /* Clear pending interrupt flag to make sure it doesn't fire again after exiting. */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} /* End of function layer3_switch_gwdi_isr() */ + +/*********************************************************************************************************************** + * Interrupt handler for ETHA error interrupts that includes TAS error events. + ***********************************************************************************************************************/ +void layer3_switch_eaei_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + layer3_switch_instance_ctrl_t * p_instance_ctrl = (layer3_switch_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + ether_switch_callback_args_t callback_arg = {0}; + + R_ETHA0_Type * p_etha_reg; + uint32_t eaei_status; + + callback_arg.channel = p_instance_ctrl->p_cfg->channel; + callback_arg.p_context = p_instance_ctrl->p_context; + + for (uint32_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + /* Get status register address. */ + p_etha_reg = (R_ETHA0_Type *) (R_ETHA0_BASE + (LAYER3_SWITCH_ETHA_REG_SIZE * i)); + eaei_status = p_etha_reg->EAEIS1; + + /* Clear status register. */ + p_etha_reg->EAEIS1 = eaei_status; + + /* Check TAS gate error events. */ + if (eaei_status & (R_ETHA0_EAEIS1_TASGES0_Msk | R_ETHA0_EAEIS1_TASGES1_Msk | + R_ETHA0_EAEIS1_TASGES2_Msk | R_ETHA0_EAEIS1_TASGES3_Msk | R_ETHA0_EAEIS1_TASGES4_Msk | + R_ETHA0_EAEIS1_TASGES5_Msk | R_ETHA0_EAEIS1_TASGES6_Msk | R_ETHA0_EAEIS1_TASGES7_Msk)) + { + /* Call callback function for the port. */ + callback_arg.ports |= (1 << i); + callback_arg.event = ETHER_SWITCH_EVENT_TAS_ERROR; + } + } + + /* Call callback of the switch. */ + if (0 != callback_arg.ports) + { + r_layer3_switch_call_callback(p_instance_ctrl->p_callback, &callback_arg, p_instance_ctrl->p_callback_memory); + } + + /* Clear pending interrupt flag to make sure it doesn't fire again after exiting. */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} /* End of function layer3_switch_eaei_isr() */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_lpm/r_lpm.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_lpm/r_lpm.c new file mode 100644 index 0000000000..e7e4e59154 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_lpm/r_lpm.c @@ -0,0 +1,1187 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_lpm.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define LPM_LPSCR_SYSTEM_ACTIVE (0x0U) +#if BSP_MCU_GROUP_RA8_GEN2 + #define LPM_LPSCR_SOFTWARE_STANDBY_MODE (0x5U) +#else + #define LPM_LPSCR_SOFTWARE_STANDBY_MODE (0x4U) +#endif +#define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE1 (0x8U) +#define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE2 (0x9U) +#define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE3 (0xAU) + +/* Clock control register addresses */ +#define LPM_CLOCK_HOCOCR (&R_SYSTEM->HOCOCR) +#define LPM_CLOCK_MOCOCR (&R_SYSTEM->MOCOCR) +#define LPM_CLOCK_LOCOCR (&R_SYSTEM->LOCOCR) +#define LPM_CLOCK_MOSCCR (&R_SYSTEM->MOSCCR) +#define LPM_CLOCK_SOSCCR (&R_SYSTEM->SOSCCR) +#define LPM_CLOCK_PLLCR (&R_SYSTEM->PLLCR) +#define LPM_CLOCK_PLL2CR (&R_SYSTEM->PLL2CR) +#define LPM_CLOCK_HOCO 0 // The high speed on chip oscillator. +#define LPM_CLOCK_MOCO 1 // The middle speed on chip oscillator. +#define LPM_CLOCK_LOCO 2 // The low speed on chip oscillator. +#define LPM_CLOCK_MAIN_OSC 3 // The main oscillator. +#define LPM_CLOCK_SUBCLOCK 4 // The subclock oscillator. +#define LPM_CLOCK_PLL 5 // The PLL oscillator. +#define LPM_CLOCK_PLL2 6 // The PLL2 oscillator. + +/* From user's manual and discussions with hardware group, + * using the maximum is safe for all MCUs, will be updated and restored in LPM when entering + * low power mode on RA6 MCUs (lowPowerModeEnter()) + */ + +#define LPM_SW_STANDBY_STCONR (0x0U) +#define LPM_SW_STANDBY_WAKE_STCONR (0x3U) + +#define LPM_SNZREQCR1_OFFSET (32ULL) +#define LPM_WUPEN1_OFFSET (32ULL) +#define LPM_SBYEDCR1_OFFSET (32ULL) + +#define LPM_OPEN (0x524c504d) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +#ifdef R_SYSTEM_SNZCR_SNZE_Msk + +/* This array stores the address of the register containing the stop bit for each clock. All of these registers are + * 8-bit registers and only bit 0 is valid. All other bits are read as 0 and should be written to 0. Bit 0 of each + * of these registers indicates that the corresponding clock is stopped when set, or that the corresponding clock + * is operating when cleared. */ +static uint8_t volatile * const gp_lpm_clock_stp_registers[] = +{ + [LPM_CLOCK_HOCO] = LPM_CLOCK_HOCOCR, + [LPM_CLOCK_MOCO] = LPM_CLOCK_MOCOCR, + [LPM_CLOCK_LOCO] = LPM_CLOCK_LOCOCR, + [LPM_CLOCK_MAIN_OSC] = LPM_CLOCK_MOSCCR, + [LPM_CLOCK_SUBCLOCK] = LPM_CLOCK_SOSCCR, + #if BSP_FEATURE_CGC_HAS_PLL + [LPM_CLOCK_PLL] = LPM_CLOCK_PLLCR, + #endif + #if BSP_FEATURE_CGC_HAS_PLL2 + [LPM_CLOCK_PLL2] = LPM_CLOCK_PLL2CR, + #endif +}; +#endif + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ +const lpm_api_t g_lpm_on_lpm = +{ + .open = R_LPM_Open, + .close = R_LPM_Close, + .lowPowerReconfigure = R_LPM_LowPowerReconfigure, + .lowPowerModeEnter = R_LPM_LowPowerModeEnter, + .ioKeepClear = R_LPM_IoKeepClear, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ +static fsp_err_t r_lpm_configure(lpm_cfg_t const * const p_cfg); +static fsp_err_t r_lpm_low_power_enter(lpm_instance_ctrl_t * const p_instance_ctrl); + +#ifdef R_SYSTEM_SNZCR_SNZE_Msk +static fsp_err_t r_lpm_check_clocks(uint32_t clock_source); + +#endif +static void r_lpm_wait_for_operating_mode_flags(void); + +#if BSP_FEATURE_LPM_HAS_LPSCR +static uint8_t r_lpm_lpscr_calculate(lpm_cfg_t const * p_cfg); + +#endif +#if LPM_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_lpm_mcu_specific_low_power_check(lpm_cfg_t const * const p_cfg); + +#endif + +/*******************************************************************************************************************//** + * @addtogroup LPM + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Perform any necessary initialization + * + * @retval FSP_SUCCESS LPM instance opened + * @retval FSP_ERR_ASSERTION Null Pointer + * @retval FSP_ERR_ALREADY_OPEN LPM instance is already open + * @retval FSP_ERR_UNSUPPORTED This MCU does not support Deep Software Standby + * @retval FSP_ERR_INVALID_ARGUMENT One of the following: + * - Invalid snooze entry source + * - Invalid snooze end sources + * @retval FSP_ERR_INVALID_MODE One of the following: + * - Invalid low power mode + * - Invalid DTC option for snooze mode + * - Invalid deep standby end sources + * - Invalid deep standby end sources edges + * - Invalid power supply option for deep standby + * - Invalid IO port option for deep standby + * - Invalid output port state setting for standby or deep standby + * - Invalid sources for wake from standby mode + * - Invalid power supply option for standby + * - Invalid IO port option for standby + * - Invalid standby end sources + * - Invalid standby end sources edges + **********************************************************************************************************************/ +fsp_err_t R_LPM_Open (lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg) +{ + lpm_instance_ctrl_t * p_ctrl = (lpm_instance_ctrl_t *) p_api_ctrl; +#if LPM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(LPM_OPEN != p_ctrl->lpm_open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Save the configuration */ + p_ctrl->p_cfg = p_cfg; + + fsp_err_t err = r_lpm_configure(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_ctrl->lpm_open = LPM_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configure a low power mode + * + * NOTE: This function does not enter the low power mode, it only configures parameters of the mode. Execution of the + * WFI instruction is what causes the low power mode to be entered. + * + * @retval FSP_SUCCESS Low power mode successfully applied + * @retval FSP_ERR_ASSERTION Null Pointer + * @retval FSP_ERR_NOT_OPEN LPM instance is not open + * @retval FSP_ERR_UNSUPPORTED This MCU does not support Deep Software Standby + * @retval FSP_ERR_INVALID_ARGUMENT One of the following: + * - Invalid snooze entry source + * - Invalid snooze end sources + * @retval FSP_ERR_INVALID_MODE One of the following: + * - Invalid low power mode + * - Invalid DTC option for snooze mode + * - Invalid deep standby end sources + * - Invalid deep standby end sources edges + * - Invalid power supply option for deep standby + * - Invalid IO port option for deep standby + * - Invalid output port state setting for standby or deep standby + * - Invalid sources for wake from standby mode + * - Invalid power supply option for standby + * - Invalid IO port option for standby + * - Invalid standby end sources + * - Invalid standby end sources edges + **********************************************************************************************************************/ +fsp_err_t R_LPM_LowPowerReconfigure (lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg) +{ + lpm_instance_ctrl_t * p_ctrl = (lpm_instance_ctrl_t *) p_api_ctrl; + +#if LPM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(LPM_OPEN == p_ctrl->lpm_open, FSP_ERR_NOT_OPEN); +#endif + + /* Save the configuration */ + p_ctrl->p_cfg = p_cfg; + + return r_lpm_configure(p_cfg); +} + +/*******************************************************************************************************************//** + * Enter low power mode (sleep/deep sleep/standby/deep standby) using WFI macro. + * + * Function will return after waking from low power mode. + * + * @retval FSP_SUCCESS Successful. + * @retval FSP_ERR_ASSERTION Null pointer. + * @retval FSP_ERR_NOT_OPEN LPM instance is not open + * @retval FSP_ERR_INVALID_MODE One of the following: + * - HOCO was not system clock when using snooze mode with SCI0/RXD0. + * - HOCO was not stable when using snooze mode with SCI0/RXD0. + * - MOCO was running when using snooze mode with SCI0/RXD0. + * - MAIN OSCILLATOR was running when using snooze mode with SCI0/RXD0. + * - PLL was running when using snooze mode with SCI0/RXD0. + * - Unable to disable ocillator stop detect when using standby or deep standby. + **********************************************************************************************************************/ +fsp_err_t R_LPM_LowPowerModeEnter (lpm_ctrl_t * const p_api_ctrl) +{ + lpm_instance_ctrl_t * p_ctrl = (lpm_instance_ctrl_t *) p_api_ctrl; +#if LPM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(LPM_OPEN == p_ctrl->lpm_open, FSP_ERR_NOT_OPEN); + + #if BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED + + /* The MOCO must be running when entering standby mode. */ + if (LPM_MODE_STANDBY <= p_ctrl->p_cfg->low_power_mode) + { + FSP_ERROR_RETURN(0 == FSP_STYPE3_REG8_READ(R_SYSTEM->MOCOCR, !R_SYSTEM->CGFSAR_b.NONSEC03), + FSP_ERR_INVALID_MODE); + } + #endif +#endif +#if BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST == 1 + uint8_t saved_dtcst = 0; +#endif + + /* Wait for ongoing operating mode transition (OPCMTSF, SOPCMTSF) */ + r_lpm_wait_for_operating_mode_flags(); + + /* Must enable writing to Low Power Mode register prior to entering Low Power Mode. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); +#if LPM_CFG_STANDBY_LIMIT + #if BSP_FEATURE_LPM_HAS_LPSCR + R_SYSTEM->LPSCR = r_lpm_lpscr_calculate(p_ctrl->p_cfg); + #endif + + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + if (LPM_MODE_SLEEP != p_ctrl->p_cfg->low_power_mode) + { + R_SYSTEM->SBYCR |= (1U << R_SYSTEM_SBYCR_SSBY_Pos); + } + #endif +#endif + +#if BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST == 1 + if (((LPM_MODE_STANDBY == p_ctrl->p_cfg->low_power_mode) || + ((LPM_MODE_STANDBY_SNOOZE == p_ctrl->p_cfg->low_power_mode) && !p_ctrl->p_cfg->dtc_state_in_snooze)) && + (0 == R_MSTP->MSTPCRA_b.MSTPA22)) + { + /* Store the previous state of DTCST. */ + saved_dtcst = R_DTC->DTCST; + + /* If DTC is not used for requesting snooze mode, it should be stopped before entering standby or snooze mode. */ + R_DTC->DTCST = 0U; + } +#endif + fsp_err_t err = r_lpm_low_power_enter(p_ctrl); + +#if LPM_CFG_STANDBY_LIMIT + #if BSP_FEATURE_LPM_HAS_LPSCR + if ((LPM_MODE_SLEEP != p_ctrl->p_cfg->low_power_mode) && (LPM_MODE_DEEP_SLEEP != p_ctrl->p_cfg->low_power_mode)) + { + R_SYSTEM->LPSCR = 0; + } + #endif + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + if (LPM_MODE_SLEEP != p_ctrl->p_cfg->low_power_mode) + { + R_SYSTEM->SBYCR &= (uint16_t) (~(1U << R_SYSTEM_SBYCR_SSBY_Pos)); + } + #endif +#endif +#if BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST == 1 + if (((LPM_MODE_STANDBY == p_ctrl->p_cfg->low_power_mode) || + ((LPM_MODE_STANDBY_SNOOZE == p_ctrl->p_cfg->low_power_mode) && !p_ctrl->p_cfg->dtc_state_in_snooze)) && + (0 == R_MSTP->MSTPCRA_b.MSTPA22)) + { + /* If DTC was stopped prior to entering standby or snooze mode, then start it again. */ + R_DTC->DTCST = saved_dtcst; + } +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + + return err; +} + +/*******************************************************************************************************************//** + * Clear the IOKEEP bit after deep software standby + * + * @retval FSP_SUCCESS DPSBYCR_b.IOKEEP bit cleared Successfully. + * @retval FSP_ERR_UNSUPPORTED Deep standby mode not supported on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_LPM_IoKeepClear (lpm_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + R_SYSTEM->DPSBYCR_b.IOKEEP = 0U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + + return FSP_SUCCESS; +#else + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Close the LPM Instance + * + * @retval FSP_SUCCESS LPM driver closed + * @retval FSP_ERR_NOT_OPEN LPM instance is not open + * @retval FSP_ERR_ASSERTION Null Pointer + **********************************************************************************************************************/ +fsp_err_t R_LPM_Close (lpm_ctrl_t * const p_api_ctrl) +{ + lpm_instance_ctrl_t * p_ctrl = (lpm_instance_ctrl_t *) p_api_ctrl; +#if LPM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ERROR_RETURN(LPM_OPEN == p_ctrl->lpm_open, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->lpm_open = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup LPM) + **********************************************************************************************************************/ + +#if LPM_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Verifies all MCU specific settings related to low power modes + * @param p_cfg the MCU specific configuration + * + * @retval FSP_SUCCESS Configuration is valid + * @retval FSP_ERR_UNSUPPORTED This MCU does not support Deep Software Standby + * @retval FSP_ERR_INVALID_ARGUMENT One of the following: + * - Invalid snooze entry source + * - Invalid snooze end sources + * @retval FSP_ERR_INVALID_MODE One of the following: + * - Invalid low power mode + * - Invalid DTC option for snooze mode + * - Invalid deep standby end sources + * - Invalid deep standby end sources edges + * - Invalid power supply option for deep standby + * - Invalid IO port option for deep standby + * - Invalid output port state setting for standby or deep standby + * - Invalid sources for wake from standby mode + * - Invalid power supply option for standby + * - Invalid IO port option for standby + * - Invalid standby end sources + * - Invalid standby end sources edges + * + * @note This function assumes the register has been unlocked by the calling application + **********************************************************************************************************************/ +fsp_err_t r_lpm_mcu_specific_low_power_check (lpm_cfg_t const * const p_cfg) +{ + #if !BSP_FEATURE_LPM_HAS_DEEP_SLEEP + FSP_ERROR_RETURN(LPM_MODE_DEEP_SLEEP != p_cfg->low_power_mode, FSP_ERR_UNSUPPORTED) + #endif + #if !BSP_FEATURE_LPM_HAS_SNOOZE + FSP_ERROR_RETURN(LPM_MODE_STANDBY_SNOOZE != p_cfg->low_power_mode, FSP_ERR_UNSUPPORTED) + #endif + + #if BSP_FEATURE_LPM_HAS_DEEP_SLEEP + if ((LPM_MODE_SLEEP != p_cfg->low_power_mode) && (LPM_MODE_DEEP_SLEEP != p_cfg->low_power_mode)) + #else + if (LPM_MODE_SLEEP != p_cfg->low_power_mode) + #endif + { + if (LPM_MODE_STANDBY_SNOOZE == p_cfg->low_power_mode) + { + #if BSP_FEATURE_LPM_HAS_SNOOZE + #if BSP_FEATURE_LPM_SNZREQCR_MASK > 0 + FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->snooze_request_source & (~BSP_FEATURE_LPM_SNZREQCR_MASK)), + FSP_ERR_INVALID_ARGUMENT); + #endif + #if BSP_FEATURE_LPM_SNZEDCR_MASK > 0 + FSP_ERROR_RETURN(0U == ((uint32_t) p_cfg->snooze_end_sources & (~BSP_FEATURE_LPM_SNZEDCR_MASK)), + FSP_ERR_INVALID_ARGUMENT); + #endif + #endif + } + else if (LPM_MODE_DEEP == p_cfg->low_power_mode) + { + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + + /* Verify the deep software standby interrupt source is valid. */ + FSP_ERROR_RETURN(0U == (uint32_t) (~BSP_FEATURE_LPM_DPSIER_MASK & p_cfg->deep_standby_cancel_source), + FSP_ERR_INVALID_MODE); + + /* Verify the deep software standby interrupt edge is valid. */ + FSP_ERROR_RETURN(0U == (uint32_t) (~BSP_FEATURE_LPM_DPSIEGR_MASK & p_cfg->deep_standby_cancel_edge), + FSP_ERR_INVALID_MODE); + + /* Verify all configured edges have a source configured. */ + FSP_ERROR_RETURN(0U == + (~p_cfg->deep_standby_cancel_source & + (lpm_deep_standby_cancel_source_t) p_cfg->deep_standby_cancel_edge), + FSP_ERR_INVALID_MODE); + #else + + return FSP_ERR_UNSUPPORTED; + #endif + } + else + { + /* Do nothing. */ + } + + #if BSP_FEATURE_ICU_WUPEN_MASK > 0 + FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->standby_wake_sources & ~BSP_FEATURE_ICU_WUPEN_MASK), + FSP_ERR_INVALID_MODE); + #endif + #if BSP_FEATURE_ICU_SBYEDCR_MASK > 0 + FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->standby_wake_sources & ~BSP_FEATURE_ICU_SBYEDCR_MASK), + FSP_ERR_INVALID_MODE); + #endif + } + + #if BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE + FSP_ERROR_RETURN(((R_SYSTEM->FOCOSCR_b.CKSEL == 0) && (R_SYSTEM->FMAINSCR_b.CKSEL == 0) && + (R_SYSTEM->ICLKSCR_b.CKSEL == 0) && (R_SYSTEM->HOCODIV == 0)), + FSP_ERR_INVALID_MODE); + #endif + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Configures all MCU specific settings related to low power modes + * @param p_cfg the MCU specific configuration + * + * @note This function assumes the register has been unlocked by the calling application + * + * @retval FSP_SUCCESS Configuration is valid + * @retval FSP_ERR_UNSUPPORTED This MCU does not support Deep Software Standby + * @retval FSP_ERR_ASSERTION NULL p_extend when low power mode is not Sleep + * @retval FSP_ERR_INVALID_ARGUMENT One of the following: + * - Invalid snooze entry source + * - Invalid snooze end sources + * @retval FSP_ERR_INVALID_MODE One of the following: + * - Invalid low power mode + * - Invalid DTC option for snooze mode + * - Invalid deep standby end sources + * - Invalid deep standby end sources edges + * - Invalid power supply option for deep standby + * - Invalid IO port option for deep standby + * - Invalid output port state setting for standby or deep standby + * - Invalid sources for wake from standby mode + * - Invalid power supply option for standby + * - Invalid IO port option for standby + * - Invalid standby end sources + * - Invalid standby end sources edges + **********************************************************************************************************************/ +fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) +{ +#if LPM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + fsp_err_t err = r_lpm_mcu_specific_low_power_check(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif +#if BSP_FEATURE_ICU_SBYEDCR_MASK > 0 + uint32_t sbyedcr0 = 0; + uint32_t sbyedcr1 = 0; +#endif +#ifdef R_SYSTEM_SNZCR_SNZE_Msk + uint32_t snzcr = 0; +#endif + uint32_t sbycr = 0; +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + uint32_t dpsbycr = 0; +#endif + +#if BSP_FEATURE_LPM_HAS_LDO_SKEEP + if ((R_SYSTEM->PLL1LDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.pll1_ldo) || + (R_SYSTEM->PLL2LDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.pll2_ldo) || + (R_SYSTEM->HOCOLDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.hoco_ldo)) + { + /* Writing to PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers is only allowed in High Speed Mode. */ + FSP_ERROR_RETURN(R_SYSTEM->OPCCR_b.OPCM == 0, FSP_ERR_INVALID_MODE); + } +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + + /* Wait for ongoing operating mode transition (OPCMTSF, SOPCMTSF) */ + r_lpm_wait_for_operating_mode_flags(); + + /* Configure registers for modes other than Sleep */ + if (LPM_MODE_SLEEP != p_cfg->low_power_mode) + { +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + + /* Configure Deep Software Standby registers. */ + if (LPM_MODE_DEEP == p_cfg->low_power_mode) + { + R_SYSTEM->DPSIER0 = (uint8_t) (p_cfg->deep_standby_cancel_source); + R_SYSTEM->DPSIER1 = (uint8_t) (p_cfg->deep_standby_cancel_source >> 8U); + R_SYSTEM->DPSIER2 = (uint8_t) (p_cfg->deep_standby_cancel_source >> 16U); + R_SYSTEM->DPSIER3 = (uint8_t) (p_cfg->deep_standby_cancel_source >> 24U); + + #if BSP_FEATURE_LPM_HAS_DPSIER4 + R_SYSTEM->DPSIER4 = (uint8_t) (p_cfg->deep_standby_cancel_source >> 32U); // NOLINT(readability-magic-numbers) + #endif + #if BSP_FEATURE_LPM_HAS_DPSIER5 + R_SYSTEM->DPSIER5 = (uint8_t) (p_cfg->deep_standby_cancel_source >> 40U); // NOLINT(readability-magic-numbers) + #endif + + R_SYSTEM->DPSIEGR0 = (uint8_t) (p_cfg->deep_standby_cancel_edge); + R_SYSTEM->DPSIEGR1 = (uint8_t) (p_cfg->deep_standby_cancel_edge >> 8U); + R_SYSTEM->DPSIEGR2 = (uint8_t) (p_cfg->deep_standby_cancel_edge >> 16U); + + #if BSP_FEATURE_LPM_HAS_DPSIEGR3 + R_SYSTEM->DPSIEGR3 = (uint8_t) (p_cfg->deep_standby_cancel_edge >> 24U); + #endif + #if BSP_FEATURE_LPM_HAS_DPSIEGR4 + R_SYSTEM->DPSIEGR4 = (uint8_t) (p_cfg->deep_standby_cancel_edge >> 32U); // NOLINT(readability-magic-numbers) + #endif + + #if BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY + dpsbycr |= R_SYSTEM_DPSBYCR_DPSBY_Msk; + #endif + #if BSP_FEATURE_LPM_HAS_DPSBYCR_DCSSMODE + dpsbycr |= (uint8_t) (p_cfg->deep_standby_soft_start_mode << R_SYSTEM_DPSBYCR_DCSSMODE_Pos); + #endif + #if BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT + dpsbycr |= ((uint32_t) p_cfg->power_supply_state << R_SYSTEM_DPSBYCR_DEEPCUT_Pos) & + R_SYSTEM_DPSBYCR_DEEPCUT_Msk; + #endif + dpsbycr |= ((uint32_t) p_cfg->io_port_state << R_SYSTEM_DPSBYCR_IOKEEP_Pos) & R_SYSTEM_DPSBYCR_IOKEEP_Msk; + } +#endif + +#if BSP_FEATURE_LPM_HAS_SNOOZE + + /* Configure Snooze registers */ + if (LPM_MODE_STANDBY_SNOOZE == p_cfg->low_power_mode) + { + #if BSP_FEATURE_LPM_SNZREQCR_MASK > 0 + + /* Configure RXD0 falling edge detect */ + if (LPM_SNOOZE_REQUEST_RXD0_FALLING == p_cfg->snooze_request_source) + { + snzcr = 1U << R_SYSTEM_SNZCR_RXDREQEN_Pos; + } + + /* Set the request condition that can trigger entry in to snooze mode */ + R_SYSTEM->SNZREQCR = (uint32_t) p_cfg->snooze_request_source & UINT32_MAX; + #endif + #if BSP_FEATURE_LPM_HAS_SNZREQCR1 == 1 + R_SYSTEM->SNZREQCR1 = (uint32_t) (p_cfg->snooze_request_source >> LPM_SNZREQCR1_OFFSET) & UINT32_MAX; + #endif + #if BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE + + /* Set the startup speed of the HOCO when entering snooze mode. */ + sbycr |= (uint32_t) (p_cfg->lpm_hoco_startup_speed << R_SYSTEM_SBYCR_FWKUP_Pos); + #endif + #if BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT + + /* Set the SOSC state in snooze mode. */ + sbycr |= (uint32_t) (p_cfg->lpm_standby_sosc << R_SYSTEM_SBYCR_RTCLPC_Pos); + #endif + #ifdef R_SYSTEM_SNZCR_SNZE_Msk + + /* Enable/disable DTC operation */ + snzcr |= (uint32_t) (p_cfg->dtc_state_in_snooze << R_SYSTEM_SNZCR_SNZDTCEN_Pos); + + /* Set the source that can cause an exit from snooze to normal mode */ + R_ICU->SELSR0_b.SELS = R_ICU_SELSR0_SELS_Msk & p_cfg->snooze_cancel_sources; + #endif + #if BSP_FEATURE_ICU_SBYEDCR_MASK > 0 + + /* Set the source that can cause an exit from snooze to normal mode */ + sbyedcr0 |= (uint32_t) p_cfg->snooze_cancel_sources & UINT32_MAX; + sbyedcr1 |= (uint32_t) (p_cfg->snooze_cancel_sources >> LPM_SBYEDCR1_OFFSET) & UINT32_MAX; + #endif + #if BSP_FEATURE_LPM_SNZREQCR_MASK > 0 + + /* Set all sources that can cause an exit from snooze mode to software standby. */ + R_SYSTEM->SNZEDCR = (uint8_t) p_cfg->snooze_end_sources & UINT8_MAX; + #endif + #if BSP_FEATURE_LPM_HAS_SNZEDCR1 == 1 + R_SYSTEM->SNZEDCR1 = (uint8_t) (p_cfg->snooze_end_sources >> 8U) & UINT8_MAX; + #endif + } +#endif + +#if BSP_FEATURE_LPM_HAS_DEEP_SLEEP + if (LPM_MODE_DEEP_SLEEP != p_cfg->low_power_mode) +#endif + { + /* Set SBYCR to Standby/Deep Standby. */ +#if BSP_FEATURE_LPM_HAS_SBYCR_OPE + sbycr = ((uint32_t) p_cfg->output_port_enable) << R_SYSTEM_SBYCR_OPE_Pos; +#elif BSP_FEATURE_LPM_SBYCR_WRITE1_B14 + sbycr = R_SYSTEM_SBYCR_OPE_Msk; +#endif + +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + sbycr |= R_SYSTEM_SBYCR_SSBY_Msk; +#endif + +#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + + /* Configure Standby RAM retention in software standby and deep software standby modes. */ + dpsbycr |= (uint8_t) (p_cfg->ram_retention_cfg.standby_ram_retention << R_SYSTEM_DPSBYCR_SRKEEP_Pos); +#endif + } + + if ((LPM_MODE_SLEEP == p_cfg->low_power_mode) || (LPM_MODE_STANDBY_SNOOZE == p_cfg->low_power_mode)) + { +#if BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT + + /* Flash mode in sleep mode or in snooze mode. */ + sbycr |= (uint32_t) (p_cfg->lpm_flash_mode_select << R_SYSTEM_SBYCR_FLSTP_Pos); +#endif + } + + if ((LPM_MODE_DEEP_SLEEP == p_cfg->low_power_mode) || (LPM_MODE_STANDBY == p_cfg->low_power_mode)) + { +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + + /* Configure TCM retention settings in deep sleep or standby mode. */ + R_SYSTEM->PDRAMSCR1 = p_cfg->ram_retention_cfg.tcm_retention; +#endif + } + + if (LPM_MODE_STANDBY == p_cfg->low_power_mode) + { +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + + /* Configure RAM retention settings in standby mode. */ + R_SYSTEM->PDRAMSCR0 = p_cfg->ram_retention_cfg.ram_retention; +#endif + +#if BSP_FEATURE_LPM_HAS_LDO_SKEEP + + /* PLL1LDOCR may only be written in High Speed Mode. If PLL1DOCR setting is not changed, then skip + * writing to it. */ + if (R_SYSTEM->PLL1LDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.pll1_ldo) + { + R_SYSTEM->PLL1LDOCR_b.SKEEP = (uint8_t) (p_cfg->ldo_standby_cfg.pll1_ldo & 0x01); + } + + /* PLL2LDOCR may only be written in High Speed Mode. If PLL2DOCR setting is not changed, then skip + * writing to it. */ + if (R_SYSTEM->PLL2LDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.pll2_ldo) + { + R_SYSTEM->PLL2LDOCR_b.SKEEP = (uint8_t) (p_cfg->ldo_standby_cfg.pll2_ldo & 0x01); + } + + /* HOCOLDOCR may only be written in High Speed Mode. If HOCOLDOCR setting is not changed, then skip + * writing to it. */ + if (R_SYSTEM->HOCOLDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.hoco_ldo) + { + R_SYSTEM->HOCOLDOCR_b.SKEEP = (uint8_t) (p_cfg->ldo_standby_cfg.hoco_ldo & 0x01); + } +#endif +#if BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT + + /* Set the SOSC state in standby Mode. */ + sbycr |= (uint32_t) (p_cfg->lpm_standby_sosc << R_SYSTEM_SBYCR_RTCLPC_Pos); +#endif + } + +#if BSP_FEATURE_ICU_WUPEN_MASK > 0 + R_ICU->WUPEN = (uint32_t) p_cfg->standby_wake_sources & UINT32_MAX; +#endif +#if BSP_FEATURE_ICU_HAS_WUPEN1 + R_ICU->WUPEN1 = (uint32_t) (p_cfg->standby_wake_sources >> LPM_WUPEN1_OFFSET) & UINT32_MAX; +#endif +#if BSP_FEATURE_ICU_HAS_WUPEN2 + R_ICU->WUPEN2 = (uint32_t) p_cfg->standby_wake_sources_2 & UINT32_MAX; +#endif +#if BSP_FEATURE_ICU_SBYEDCR_MASK > 0 + sbyedcr0 |= (uint32_t) p_cfg->standby_wake_sources & UINT32_MAX; + sbyedcr1 |= (uint32_t) (p_cfg->standby_wake_sources >> LPM_SBYEDCR1_OFFSET) & UINT32_MAX; +#endif + } + else + { + /* Set SBYCR to Sleep mode. */ +#if BSP_FEATURE_LPM_SBYCR_WRITE1_B14 + sbycr = 1U << R_SYSTEM_SBYCR_OPE_Pos; +#elif BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT + + /* Flash mode in sleep mode or in snooze mode. */ + sbycr |= (uint32_t) (p_cfg->lpm_flash_mode_select << R_SYSTEM_SBYCR_FLSTP_Pos); +#else + sbycr = 0; +#endif + } + +#if BSP_FEATURE_ICU_SBYEDCR_MASK > 0 + R_ICU->SBYEDCR0 = sbyedcr0; + R_ICU->SBYEDCR1 = sbyedcr1; +#endif +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + #if LPM_CFG_STANDBY_LIMIT + R_SYSTEM->SBYCR = (uint16_t) (sbycr & ~(1U << R_SYSTEM_SBYCR_SSBY_Pos)); + #else + R_SYSTEM->SBYCR = (uint16_t) sbycr; + #endif +#else + R_SYSTEM->SBYCR = (uint8_t) sbycr; +#endif + +#if BSP_FEATURE_LPM_HAS_LPSCR + #if !LPM_CFG_STANDBY_LIMIT + R_SYSTEM->LPSCR = r_lpm_lpscr_calculate(p_cfg); + #else + R_SYSTEM->LPSCR = 0; + #endif +#endif + +#ifdef R_SYSTEM_SNZCR_SNZE_Msk + R_SYSTEM->SNZCR = (uint8_t) snzcr; +#endif + +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + R_SYSTEM->DPSBYCR = (uint8_t) dpsbycr; +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); + + return FSP_SUCCESS; +} + +#ifdef R_SYSTEM_SNZCR_SNZE_Msk + +/*******************************************************************************************************************//** + * Check the clock settings + * + * @param[in] clock_source The clock source + * + * @retval FSP_SUCCESS Clock settings are valid. + * @retval FSP_ERR_INVALID_MODE One of the following: + * - HOCO was not system clock when using snooze mode with SCI0/RXD0. + * - HOCO was not stable when using snooze mode with SCI0/RXD0. + * - MOCO was running when using snooze mode with SCI0/RXD0. + * - MAIN OSCILLATOR was running when using snooze mode with SCI0/RXD0. + * - PLL was running when using snooze mode with SCI0/RXD0. + * - PLL2 was running when using snooze mode with SCI0/RXD0. + **********************************************************************************************************************/ +fsp_err_t r_lpm_check_clocks (uint32_t clock_source) +{ + /* Verify the clock source is HOCO */ + FSP_ERROR_RETURN(LPM_CLOCK_HOCO == clock_source, FSP_ERR_INVALID_MODE); + + /* Verify Moco, Main Osc and PLL are stopped. */ + FSP_ERROR_RETURN(1U == (*gp_lpm_clock_stp_registers[LPM_CLOCK_MOCO]), FSP_ERR_INVALID_MODE); + FSP_ERROR_RETURN(1U == (*gp_lpm_clock_stp_registers[LPM_CLOCK_MAIN_OSC]), FSP_ERR_INVALID_MODE); + #if BSP_FEATURE_CGC_HAS_PLL + FSP_ERROR_RETURN(1U == (*gp_lpm_clock_stp_registers[LPM_CLOCK_PLL]), FSP_ERR_INVALID_MODE); + #endif + #if BSP_FEATURE_CGC_HAS_PLL2 + FSP_ERROR_RETURN(1U == (*gp_lpm_clock_stp_registers[LPM_CLOCK_PLL2]), FSP_ERR_INVALID_MODE); + #endif + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Perform pre-WFI execution tasks, enter low power mode, Perform post-WFI execution tasks + * + * @note This function will unlock and lock registers as needed + * + * @retval FSP_SUCCESS Successfully entered and woke from low power mode. + * @retval FSP_ERR_INVALID_MODE One of the following: + * - FLL function is enabled when requesting Software Standby. + * - HOCO was not system clock when using snooze mode with SCI0/RXD0. + * - HOCO was not stable when using snooze mode with SCI0/RXD0. + * - MOCO was running when using snooze mode with SCI0/RXD0. + * - MAIN OSCILLATOR was running when using snooze mode with SCI0/RXD0. + * - PLL was running when using snooze mode with SCI0/RXD0. + * - Unable to disable ocillator stop detect when using standby or deep standby. + **********************************************************************************************************************/ +fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) +{ +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + uint32_t saved_opccr = 0U; + uint8_t volatile * p_opccr = &R_SYSTEM->OPCCR; + #if BSP_FEATURE_CGC_HAS_SOPCCR + uint32_t saved_sopccr = 0U; + #endif + uint32_t saved_ostdcr_ostde = 0U; + uint8_t volatile * p_ostde = &R_SYSTEM->OSTDCR; + #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 + uint32_t saved_hocowtcr = 0U; + uint32_t new_hocowtcr = 0U; + #endif + #if BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED + uint32_t stopped_modules = 0; + #endif +#endif + +#if BSP_PRV_POWER_USE_DCDC + bsp_power_mode_t power_mode = BSP_POWER_MODE_LDO; +#endif + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2 + if (1 == R_SYSTEM->LPMSAR_b.NONSEC0) + { + /* If security attribution of OPCCR is set to non-secure, then use the non-secure alias. */ + p_opccr = (uint8_t volatile *) ((uint32_t) p_opccr | BSP_FEATURE_TZ_NS_OFFSET); + } + + if (1 == R_SYSTEM->CGFSAR_b.NONSEC06) + { + /* If security attribution of OSTDCR is set to non-secure, then use the non-secure alias. */ + p_ostde = (uint8_t volatile *) ((uint32_t) p_ostde | BSP_FEATURE_TZ_NS_OFFSET); + } +#endif +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + if (1U == R_SYSTEM->SBYCR_b.SSBY) +#else + if (LPM_LPSCR_SOFTWARE_STANDBY_MODE <= R_SYSTEM->LPSCR) +#endif + { + /* Execute pre-wfi standby tasks */ + +#if BSP_PRV_HOCO_USE_FLL + + /* If FLL is available it must not be active when entering Software Standby. */ + FSP_ERROR_RETURN(0U == R_SYSTEM->FLLCR1, FSP_ERR_INVALID_MODE); +#endif + +#if BSP_FEATURE_LPM_HAS_SNOOZE + + /* Get system clock */ + #if BSP_FEATURE_CGC_STARTUP_SCKSCR + uint32_t clock_source = R_SYSTEM->SCKSCR; + #endif +#endif + +#if !BSP_FEATURE_LPM_HAS_DEEP_STANDBY + #ifdef R_SYSTEM_SNZCR_SNZE_Msk + if (1U == R_SYSTEM->SNZCR_b.RXDREQEN) + { + /* Verify clock settings. */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_lpm_check_clocks(clock_source), FSP_ERR_INVALID_MODE); + } + #endif +#else + + /* Save the OPCCR and SOPCCR registers. When transitioning from Software Standby mode to Normal or Snooze mode + * these registers are overwritten. See "Operating Power Control Register" description + * in the LPM section of the relevant hardware manual. */ + saved_opccr = (*p_opccr & R_SYSTEM_OPCCR_OPCM_Msk) >> R_SYSTEM_OPCCR_OPCM_Pos; + #if BSP_FEATURE_CGC_HAS_SOPCCR + saved_sopccr = R_SYSTEM->SOPCCR_b.SOPCM; + #endif + + #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 + + /* Save HOCOWTCR_b.HSTS */ + saved_hocowtcr = R_SYSTEM->HOCOWTCR_b.HSTS; + #endif + + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + if (0U == R_SYSTEM->DPSBYCR_b.DPSBY) + #else + if (LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE1 > R_SYSTEM->LPSCR) + #endif + { + #if BSP_FEATURE_LPM_HAS_SNOOZE + + /* Check Snooze configuration settings. Set HOCOWTCR based on current configuration. See + * "Standby Control Register" description in the LPM section of the relevant hardware manual. */ + if (1U == R_SYSTEM->SNZCR_b.RXDREQEN) + { + /* Verify clock settings. */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_lpm_check_clocks(clock_source), FSP_ERR_INVALID_MODE); + #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 + new_hocowtcr = BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE; + } + else + { + new_hocowtcr = BSP_FEATURE_CGC_HOCOWTCR_VALUE; + #endif + } + + #else + #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 + new_hocowtcr = LPM_SW_STANDBY_HOCOWTCR_HSTS; + #endif + #endif + + /* Enable writing to CGC register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + + #if BSP_FEATURE_LPM_HAS_STCONR == 1 + + /* Set STCONR based on the current system clock. */ + if (LPM_CLOCK_HOCO == clock_source) + { + #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 + + /* Set HOCOWTCR_b.HSTS when using HOCO as the system clock */ + R_SYSTEM->HOCOWTCR_b.HSTS = R_SYSTEM_HOCOWTCR_HSTS_Msk & (new_hocowtcr << R_SYSTEM_HOCOWTCR_HSTS_Pos); + #endif + + R_SYSTEM->STCONR = LPM_SW_STANDBY_STCONR; + } + else + { + R_SYSTEM->STCONR = LPM_SW_STANDBY_WAKE_STCONR; + } + #endif + } + else + { + /* Enable writing to CGC register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + + /* Execute pre-wfi deep standby tasks */ + /* Clear the DOCDF flag to 0 before entering Deep Software Standby mode. */ + R_SYSTEM->SYOCDCR_b.DOCDF = 0U; + + /* Clear Deep Software Standby Interrupt Flag Registers. A dummy read is required before writing to DPSIFR. + * See "Deep Software Standby Interrupt Flag Register 0" description in the + * LPM section of the relevant hardware manual */ + R_SYSTEM->DPSIFR0; + R_SYSTEM->DPSIFR0 = 0U; + + R_SYSTEM->DPSIFR1; + R_SYSTEM->DPSIFR1 = 0U; + + R_SYSTEM->DPSIFR2; + R_SYSTEM->DPSIFR2 = 0U; + + R_SYSTEM->DPSIFR3; + R_SYSTEM->DPSIFR3 = 0U; + + #if BSP_FEATURE_LPM_HAS_DPSIER4 + R_SYSTEM->DPSIFR4; + R_SYSTEM->DPSIFR4 = 0U; + #endif + + #if BSP_FEATURE_LPM_HAS_DPSIER5 + R_SYSTEM->DPSIFR5; + R_SYSTEM->DPSIFR5 = 0U; + #endif + } + + /* Save oscillator stop detect state. */ + saved_ostdcr_ostde = (*p_ostde & R_SYSTEM_OSTDCR_OSTDE_Msk) >> R_SYSTEM_OSTDCR_OSTDE_Pos; + *p_ostde &= (uint8_t) ~R_SYSTEM_OSTDCR_OSTDE_Msk; + + #if BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED + stopped_modules = bsp_prv_power_change_mstp_set(); + + /* Delay for >750 ns if any modules changed state */ + if (0 != stopped_modules) + { + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); + } + #endif +#endif +#if BSP_PRV_POWER_USE_DCDC + + /* DCDC cannot be used in Software Standby, so switch back to LDO if needed (see Usage Notes + * in the LPM section of the relevant hardware manual). */ + if (R_SYSTEM->DCDCCTL & R_SYSTEM_DCDCCTL_DCDCON_Msk) + { + power_mode = R_BSP_PowerModeSet(BSP_POWER_MODE_LDO_BOOST); + } +#endif + } + +#if BSP_FEATURE_LPM_HAS_SNOOZE + if (LPM_MODE_STANDBY_SNOOZE == p_instance_ctrl->p_cfg->low_power_mode) + { + #ifdef R_SYSTEM_SNZCR_SNZE_Msk + + /* Enable Snooze mode (SNZCR.SNZE = 1) immediately before entering to Software Standby mode. + * See "Canceling Snooze Mode" in the LPM section of the relevant hardware manual. */ + R_SYSTEM->SNZCR_b.SNZE = 1; + + /* Dummy read required. + * infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHICBGB.html */ + R_SYSTEM->SNZCR; + #endif + } +#endif + +#if BSP_FEATURE_LPM_HAS_DEEP_SLEEP + if (LPM_MODE_SLEEP != p_instance_ctrl->p_cfg->low_power_mode) + { + /* Set the SLEEPDEEP bit. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + } +#endif + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Disable RTC Register Read/Write Clock to reduce power consumption. */ + bool rtc_register_clock_state = bsp_prv_rtc_register_clock_set(false); +#endif + +#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE + + /* Enable writing to CGC register. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + + bool clock_slowed = bsp_prv_clock_prepare_pre_sleep(); +#endif + + /* DSB should be last instruction executed before WFI + * infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHICBGB.html */ + __DSB(); + + __WFI(); + +#if BSP_CFG_SLEEP_MODE_DELAY_ENABLE + bsp_prv_clock_prepare_post_sleep(clock_slowed); + + /* Disable writing to CGC register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); +#endif + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable the RTC Register Read/Write clock if it was disabled prior to entering LPM. */ + bsp_prv_rtc_register_clock_set(rtc_register_clock_state); +#endif + +#if BSP_FEATURE_LPM_HAS_DEEP_SLEEP + if (LPM_MODE_SLEEP != p_instance_ctrl->p_cfg->low_power_mode) + { + /* Clear the SLEEPDEEP bit. */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + } +#endif + +#ifdef R_SYSTEM_SNZCR_SNZE_Msk + + /* Disable Snooze mode (SNZCR.SNZE = 0) immediately after canceling Snooze mode. + * See "Canceling Snooze Mode" in the LPM section of the relevant hardware manual. */ + R_SYSTEM->SNZCR_b.SNZE = 0; +#endif +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY || (BSP_PRV_POWER_USE_DCDC) + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + if (1U == R_SYSTEM->SBYCR_b.SSBY) + #else + if (LPM_LPSCR_SOFTWARE_STANDBY_MODE <= R_SYSTEM->LPSCR) + #endif + { + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + + /* Wait for ongoing operating mode transition (OPCMTSF, SOPCMTSF) */ + r_lpm_wait_for_operating_mode_flags(); + + /* Restore system registers to the values prior to entering standby. */ + *p_opccr = saved_opccr & R_SYSTEM_OPCCR_OPCM_Msk; + + #if BSP_FEATURE_CGC_HAS_SOPCCR + R_SYSTEM->SOPCCR = saved_sopccr & R_SYSTEM_SOPCCR_SOPCM_Msk; + #endif + + *p_ostde |= (uint8_t) saved_ostdcr_ostde; + #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 + R_SYSTEM->HOCOWTCR_b.HSTS = R_SYSTEM_HOCOWTCR_HSTS_Msk & (saved_hocowtcr << R_SYSTEM_HOCOWTCR_HSTS_Pos); + #endif + + /* Disable writing to CGC register. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + #if BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED + bsp_prv_power_change_mstp_clear(stopped_modules); + #endif + #endif + #if BSP_PRV_POWER_USE_DCDC + if (power_mode < BSP_POWER_MODE_LDO) + { + /* Switch back to DCDC if it was enabled before. */ + R_BSP_PowerModeSet(power_mode); + } + #endif + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Wait for opccr and sopccr transition flags to clear. + **********************************************************************************************************************/ +void r_lpm_wait_for_operating_mode_flags (void) +{ +#if BSP_FEATURE_CGC_HAS_OPCCR + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT((FSP_STYPE3_REG8_READ(R_SYSTEM->OPCCR, + !R_SYSTEM->LPMSAR_b.NONSEC0) & R_SYSTEM_OPCCR_OPCMTSF_Msk), + 0U); +#endif + +#if BSP_FEATURE_CGC_HAS_SOPCCR + + /* Wait for transition to complete. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); +#endif +} + +#if BSP_FEATURE_LPM_HAS_LPSCR + +/*******************************************************************************************************************//** + * Calculate the correct value of LPSCR based on the mode. + **********************************************************************************************************************/ +static uint8_t r_lpm_lpscr_calculate (lpm_cfg_t const * p_cfg) +{ + uint8_t lpscr = 0; + + switch (p_cfg->low_power_mode) + { + case LPM_MODE_SLEEP: + { + lpscr = LPM_LPSCR_SYSTEM_ACTIVE; + break; + } + + case LPM_MODE_DEEP_SLEEP: + { + lpscr = LPM_LPSCR_SYSTEM_ACTIVE; + break; + } + + case LPM_MODE_STANDBY: + { + lpscr = LPM_LPSCR_SOFTWARE_STANDBY_MODE; + break; + } + + case LPM_MODE_DEEP: + { + lpscr = LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE1; + lpscr |= p_cfg->power_supply_state; + break; + } + + default: + { + break; + } + } + + return lpscr; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_lvd/r_lvd.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_lvd/r_lvd.c new file mode 100644 index 0000000000..aba14282c6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_lvd/r_lvd.c @@ -0,0 +1,1292 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_lvd.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define LVD_OPENED (0x4C5644U) + +#define LVD_MONITOR_LVD1 (1U) +#define LVD_MONITOR_LVD2 (2U) +#define LVD_MONITOR_LVD_VBAT (3U) +#define LVD_MONITOR_LVD_VRTC (4U) +#define LVD_MONITOR_EXLVD (5U) + +#define LVD_PRV_FIRST_MONITOR_NUMBER (1U) + +#if (1U == BSP_FEATURE_LVD_VERSION) + #define LVD_PRV_NUMBER_OF_NMI (2U) + #define LVD_PRV_NUMBER_OF_VCC_MONITOR (2U) +#elif (2U == BSP_FEATURE_LVD_VERSION) + #define LVD_PRV_NUMBER_OF_NMI (1U) + #define LVD_PRV_NUMBER_OF_VCC_MONITOR (1U) +#elif (3U == BSP_FEATURE_LVD_VERSION) + #define LVD_PRV_NUMBER_OF_NMI (2U) + #define LVD_PRV_NUMBER_OF_VCC_MONITOR (5U) +#endif + +#define LVD_PRV_EXT_LVDICR_IE_ENABLE (1U << R_SYSTEM_VBTLVDICR_IE_Pos) + +#define LVD_PRV_EXT_LVDCR_LVDE_ENABLE (1 << R_SYSTEM_VBTLVDCR_LVDE_Pos) + +#define LVD_PRV_LVD1MKR_MK_ENABLE (1U) +#define LVD_PRV_LVD1MKR_MK_DISABLE (0U) +#define LVD_PRV_LVDCR0_BIT3_MASK (0x8U) + +#define LVD_PRV_LVD1CR_IRQSEL_NON_MASKABLE (0U) +#define LVD_PRV_LVD1CR_IRQSEL_MASKABLE (1U) +#define LVD_PRV_LVD1CR_LVD1SEL_INTERRUPT (0U) +#define LVD_PRV_LVD1CR_LVD1SEL_RESET (1U) +#define LVD_PRV_LVD1CR_LVD1EN_DISABLE (0U) +#define LVD_PRV_LVD1CR_LVD1EN_ENABLE (1U) + +#define LVD_PRV_SECONDS_TO_MICROSECONDS (1000000U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * lvd_prv_ns_callback)(lvd_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile lvd_prv_ns_callback)(lvd_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_lvd_hw_configure(lvd_instance_ctrl_t * p_ctrl); + +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 +static void r_lvd_ext_hw_configure(lvd_instance_ctrl_t * p_ctrl); + +#endif + +#if BSP_FEATURE_LVD_HAS_DIGITAL_FILTER == 1 +static uint32_t r_lvd_filter_delay(lvd_sample_clock_t sample_clock_divisor); + +#endif +#if (LVD_CFG_PARAM_CHECKING_ENABLE == 1) +static fsp_err_t lvd_open_parameter_check(lvd_instance_ctrl_t * p_ctrl, lvd_cfg_t const * const p_cfg); + +#endif + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +static void lvd_common_isr_handler(lvd_instance_ctrl_t * p_ctrl); +static void lvd_nmi_handler(bsp_grp_irq_t irq); +void lvd_lvd_isr(void); + +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 +static void lvd_ext_common_isr_handler(lvd_instance_ctrl_t * p_ctrl); +void lvd_ext_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Stored context for NMI handler. */ +static lvd_instance_ctrl_t * gp_ctrls[LVD_PRV_NUMBER_OF_VCC_MONITOR] = {NULL}; + +#if (1U == BSP_FEATURE_LVD_VERSION) + +/* Look-up tables for writing to monitor 1 and monitor 2 registers. */ +static uint8_t volatile * const g_lvdncr0_lut[] = {&(R_SYSTEM->LVD1CR0), &(R_SYSTEM->LVD2CR0)}; +static uint8_t volatile * const g_lvdncr1_lut[] = {&(R_SYSTEM->LVD1CR1), &(R_SYSTEM->LVD2CR1)}; +static uint8_t volatile * const g_lvdnsr_lut[] = {&(R_SYSTEM->LVD1SR), &(R_SYSTEM->LVD2SR)}; + +#elif (2U == BSP_FEATURE_LVD_VERSION) +static uint8_t volatile * const g_lvdnsr_lut[] = {&(R_SYSTEM->LVD1SR)}; + +#elif (3U == BSP_FEATURE_LVD_VERSION) + +/* Look-up tables for writing to monitor 1, monitor 2, monitor 4, monitor 5, registers. monitor 3 registers are dummy variables. */ +static uint8_t volatile * const g_lvdncr0_lut[] = +{ + &(R_SYSTEM->LVD1CR0), &(R_SYSTEM->LVD2CR0), &(R_SYSTEM->LVD3CR0), &(R_SYSTEM->LVD4CR0), &(R_SYSTEM->LVD5CR0) +}; +static uint8_t volatile * const g_lvdncr1_lut[] = +{ + &(R_SYSTEM->LVD1CR1), &(R_SYSTEM->LVD2CR1), &(R_SYSTEM->LVD3CR1), &(R_SYSTEM->LVD4CR1), &(R_SYSTEM->LVD5CR1) +}; +static uint8_t volatile * const g_lvdnsr_lut[] = {&(R_SYSTEM->LVD1SR), &(R_SYSTEM->LVD2SR)}; +#endif + +#if BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE + #if (3U == BSP_FEATURE_LVD_VERSION) +static uint8_t volatile * const g_lvdnfcr_lut[] = +{ + &(R_SYSTEM->LVD1FCR), &(R_SYSTEM->LVD2FCR), &(R_SYSTEM->LVD3FCR), &(R_SYSTEM->LVD4FCR), &(R_SYSTEM->LVD5FCR) +}; + #else +static uint8_t volatile * const g_lvdnfcr_lut[] = {&(R_SYSTEM->LVD1FCR), &(R_SYSTEM->LVD2FCR)}; + #endif +#endif + +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 + +/* Look-up table for writing to VBAT, RTC, EX register. */ +/* Index: VBAT - 0, RTC - 1, EX - 2. */ +static uint8_t volatile * const g_ext_lvdcr_lut[] = +{&(R_SYSTEM->VBTLVDCR), &(R_SYSTEM->VRTLVDCR), &(R_SYSTEM->EXLVDCR)}; + +static uint8_t volatile * const g_ext_lvdsr_lut[] = +{&(R_SYSTEM->VBTLVDSR), &(R_SYSTEM->VRTSR), &(R_SYSTEM->EXLVDSR)}; + +static uint8_t volatile * const g_ext_lvdicr_lut[] = +{&(R_SYSTEM->VBTLVDICR), &(R_SYSTEM->VRTLVDICR), &(R_SYSTEM->EXLVDICR)}; + +static uint8_t volatile * const g_ext_lvdcmpcr_lut[] = +{&(R_SYSTEM->VBTCMPCR), &(R_SYSTEM->VRTCMPCR), &(R_SYSTEM->EXLVDCMPCR)}; +#endif + +#if (BSP_FEATURE_LVD_HAS_LVDLVLR == 1) +static uint32_t const g_lvdlvlr_offset_lut[] = +{ + R_SYSTEM_LVDLVLR_LVD1LVL_Pos, R_SYSTEM_LVDLVLR_LVD2LVL_Pos +}; +static uint32_t const g_lvdlvlr_mask_lut[] = {R_SYSTEM_LVDLVLR_LVD1LVL_Msk, R_SYSTEM_LVDLVLR_LVD2LVL_Msk}; +#elif (1U == BSP_FEATURE_LVD_VERSION) +static uint8_t volatile * const g_lvdncmpcr_lut[] = {&(R_SYSTEM->LVD1CMPCR), &(R_SYSTEM->LVD2CMPCR)}; +static uint32_t const g_lvdnlvl_mask_lut[] = {R_SYSTEM_LVD1CMPCR_LVDLVL_Msk, R_SYSTEM_LVD2CMPCR_LVDLVL_Msk}; +#elif (3U == BSP_FEATURE_LVD_VERSION) +static uint8_t volatile * const g_lvdncmpcr_lut[] = +{ + &(R_SYSTEM->LVD1CMPCR), &(R_SYSTEM->LVD2CMPCR), &(R_SYSTEM->LVD3CMPCR), &(R_SYSTEM->LVD4CMPCR), + &(R_SYSTEM->LVD5CMPCR) +}; +static uint32_t const g_lvdnlvl_mask_lut[] = +{ + R_SYSTEM_LVD1CMPCR_LVDLVL_Msk, R_SYSTEM_LVD2CMPCR_LVDLVL_Msk, R_SYSTEM_LVD3CMPCR_LVDLVL_Msk, + R_SYSTEM_LVD4CMPCR_LVDLVL_Msk, R_SYSTEM_LVD5CMPCR_LVDLVL_Msk +}; +#endif + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* Instance of low voltage detection peripheral driver interface. */ +const lvd_api_t g_lvd_on_lvd = +{ + .open = R_LVD_Open, + .statusGet = R_LVD_StatusGet, + .statusClear = R_LVD_StatusClear, + .close = R_LVD_Close, + .callbackSet = R_LVD_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup LVD-PVD + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes a voltage monitor and detector according to the passed-in configuration structure. + * + * @param[in] p_api_ctrl Pointer to the control structure for the driver instance + * @param[in] p_cfg Pointer to the configuration structure for the driver instance + * + * @note Digital filter is not to be used with standby modes. + * @note Startup time can take on the order of milliseconds for some configurations. + * + * Example: + * @snippet r_lvd_example.c R_LVD_Open + * + * @retval FSP_SUCCESS Successful + * @retval FSP_ERR_ASSERTION Requested configuration was invalid + * @retval FSP_ERR_ALREADY_OPEN The instance was already opened + * @retval FSP_ERR_IN_USE Another instance is already using the desired monitor + * @retval FSP_ERR_UNSUPPORTED Digital filter was enabled on a device that does not support it + **********************************************************************************************************************/ +fsp_err_t R_LVD_Open (lvd_ctrl_t * const p_api_ctrl, lvd_cfg_t const * const p_cfg) +{ + lvd_instance_ctrl_t * p_ctrl = (lvd_instance_ctrl_t *) p_api_ctrl; + +#if (LVD_CFG_PARAM_CHECKING_ENABLE == 1) + fsp_err_t err = FSP_SUCCESS; + err = lvd_open_parameter_check(p_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err) +#endif + + /* Store the user configuration. */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + if (p_ctrl->p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_VCC_MONITOR) + { + /* Store control structure so it can be accessed from NMI handler. */ + gp_ctrls[p_ctrl->p_cfg->monitor_number - 1] = p_ctrl; + + /* Configure the hardware based on the user settings. */ + r_lvd_hw_configure(p_ctrl); + } + +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 + else + { + /* Configure the hardware based on the user settings. */ + r_lvd_ext_hw_configure(p_ctrl); + } +#endif + + /* Mark driver as opened by initializing it to "LVD" in its ASCII equivalent. */ + p_ctrl->open = LVD_OPENED; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get the current state of the monitor (threshold crossing detected, voltage currently above or below threshold). + * + * @param[in] p_api_ctrl Pointer to the control structure for the driver instance + * @param[out] p_lvd_status Pointer to status structure + * + * Example: + * @snippet r_lvd_example.c R_LVD_StatusGet + * + * @retval FSP_SUCCESS Successful + * @retval FSP_ERR_ASSERTION An argument was NULL + * @retval FSP_ERR_NOT_OPEN Driver is not open + * @retval FSP_ERR_UNSUPPORTED This monitor does not support status feature + * + **********************************************************************************************************************/ +fsp_err_t R_LVD_StatusGet (lvd_ctrl_t * const p_api_ctrl, lvd_status_t * p_lvd_status) +{ + lvd_instance_ctrl_t * p_ctrl = (lvd_instance_ctrl_t *) p_api_ctrl; + +#if (0 != LVD_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_lvd_status); + #if (3U == BSP_FEATURE_LVD_VERSION) + FSP_ERROR_RETURN(!((4 == p_ctrl->p_cfg->monitor_number) || (5 == p_ctrl->p_cfg->monitor_number)), + FSP_ERR_UNSUPPORTED); + #endif + FSP_ERROR_RETURN((LVD_OPENED == p_ctrl->open), FSP_ERR_NOT_OPEN); +#endif + + uint8_t lvdnsr = 0; + + if (p_ctrl->p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_NMI) + { + lvdnsr = *(g_lvdnsr_lut[p_ctrl->p_cfg->monitor_number - 1]); + p_lvd_status->crossing_detected = (lvd_threshold_crossing_t) ((lvdnsr & R_SYSTEM_LVD1SR_DET_Msk) != 0); + p_lvd_status->current_state = (lvd_current_state_t) ((lvdnsr & R_SYSTEM_LVD1SR_MON_Msk) != 0); + } + +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 + else + { + lvdnsr = *(g_ext_lvdsr_lut[p_ctrl->p_cfg->monitor_number - 3]); + p_lvd_status->crossing_detected = (lvd_threshold_crossing_t) ((lvdnsr & R_SYSTEM_VBTLVDSR_DET_Msk) != 0); + p_lvd_status->current_state = (lvd_current_state_t) ((lvdnsr & R_SYSTEM_VBTLVDSR_MON_Msk) != 0); + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Clears the latched status of the monitor. + * + * @param[in] p_api_ctrl Pointer to the control structure for the driver instance + * + * @retval FSP_SUCCESS Successful + * @retval FSP_ERR_ASSERTION An argument was NULL + * @retval FSP_ERR_NOT_OPEN Driver is not open + * @retval FSP_ERR_UNSUPPORTED This monitor does not support status feature + * + **********************************************************************************************************************/ +fsp_err_t R_LVD_StatusClear (lvd_ctrl_t * const p_api_ctrl) +{ + lvd_instance_ctrl_t * p_ctrl = (lvd_instance_ctrl_t *) p_api_ctrl; + +#if (0 != LVD_CFG_PARAM_CHECKING_ENABLE) + FSP_ERROR_RETURN((NULL != p_ctrl), FSP_ERR_ASSERTION); + #if (3U == BSP_FEATURE_LVD_VERSION) + FSP_ERROR_RETURN(!((4 == p_ctrl->p_cfg->monitor_number) || (5 == p_ctrl->p_cfg->monitor_number)), + FSP_ERR_UNSUPPORTED); + #endif + FSP_ERROR_RETURN((LVD_OPENED == p_ctrl->open), FSP_ERR_NOT_OPEN); +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); + + /* Clear the status register. */ + if (p_ctrl->p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_NMI) + { + *(g_lvdnsr_lut[p_ctrl->p_cfg->monitor_number - 1]) = 0; + } + +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 + else + { + *(g_ext_lvdsr_lut[p_ctrl->p_cfg->monitor_number - 3]) = 0; + } +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LVD); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements lvd_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_LVD_CallbackSet (lvd_ctrl_t * const p_api_ctrl, + void ( * p_callback)(lvd_callback_args_t *), + void * const p_context, + lvd_callback_args_t * const p_callback_memory) +{ + lvd_instance_ctrl_t * p_ctrl = (lvd_instance_ctrl_t *) p_api_ctrl; + +#if (LVD_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(LVD_OPENED == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback. */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if LVD_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure. */ + lvd_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context. */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(lvd_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables the LVD peripheral. Closes the driver instance. + * + * @param[in] p_api_ctrl Pointer to the control block structure for the driver instance + * + * @retval FSP_SUCCESS Successful + * @retval FSP_ERR_ASSERTION An argument was NULL + * @retval FSP_ERR_NOT_OPEN Driver is not open + * + **********************************************************************************************************************/ +fsp_err_t R_LVD_Close (lvd_ctrl_t * const p_api_ctrl) +{ + lvd_instance_ctrl_t * p_ctrl = (lvd_instance_ctrl_t *) p_api_ctrl; + +#if (0 != LVD_CFG_PARAM_CHECKING_ENABLE) + FSP_ERROR_RETURN((NULL != p_ctrl), FSP_ERR_ASSERTION); + FSP_ERROR_RETURN(LVD_OPENED == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_FEATURE_LVD_HAS_LVDLVLR == 1 + FSP_CRITICAL_SECTION_DEFINE; +#endif + + if (FSP_INVALID_VECTOR != p_ctrl->p_cfg->irq) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->irq); + } + + if (p_ctrl->p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_VCC_MONITOR) + { + uint32_t monitor_index = p_ctrl->p_cfg->monitor_number - 1; + + if (p_ctrl->p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_NMI) + { + /* Setting for NMI. */ + R_BSP_GroupIrqWrite((bsp_grp_irq_t) (BSP_GRP_IRQ_LVD1 + monitor_index), NULL); + } + + /* See Shutdown procedure from Table "Procedure for setting bits related to the voltage monitor 1 + * interrupt and voltage monitor 1 reset so that voltage monitoring stops" in the LVD section of + * the relevant hardware manual. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); + +#if 2U == BSP_FEATURE_LVD_VERSION + + /* Enable writing to the LVD1CR register. */ + R_SYSTEM->LVD1MKR_b.MK = LVD_PRV_LVD1MKR_MK_ENABLE; + + /* Disable LVD1 operation. */ + R_SYSTEM->LVD1CR_b.LVD1EN = LVD_PRV_LVD1CR_LVD1EN_DISABLE; + + /* Disable writing to the LVD1CR register. */ + R_SYSTEM->LVD1MKR_b.MK = LVD_PRV_LVD1MKR_MK_DISABLE; +#else + + /* Disable output of comparison results by voltage monitor. Write value to lvdncr0.bit3 should be 1. */ + *(g_lvdncr0_lut[monitor_index]) = (*(g_lvdncr0_lut[monitor_index]) | (uint8_t) LVD_PRV_LVDCR0_BIT3_MASK) & + ((uint8_t) ~(R_SYSTEM_LVD1CR0_CMPE_Msk)); + + #if BSP_FEATURE_LVD_HAS_DIGITAL_FILTER == 1 + if (LVD_SAMPLE_CLOCK_DISABLED != p_ctrl->p_cfg->sample_clock_divisor) + { + /* Wait for at least 2n + 3 LOCO cycles, where n = [2,4,8,16]. */ + R_BSP_SoftwareDelay(r_lvd_filter_delay(p_ctrl->p_cfg->sample_clock_divisor), BSP_DELAY_UNITS_MICROSECONDS); + } + #endif + uint8_t lvdncr0 = *(g_lvdncr0_lut[monitor_index]); + + /* Disable voltage monitor interrupt or reset. */ + lvdncr0 &= (uint8_t) ~R_SYSTEM_LVD1CR0_RIE_Msk; + + #if BSP_FEATURE_LVD_HAS_DIGITAL_FILTER == 1 + + /* Disable digital filter. */ + lvdncr0 |= (uint8_t) R_SYSTEM_LVD1CR0_DFDIS_Msk; + #endif + + /* Write value to lvdncr0.bit3 should be 1. */ + *(g_lvdncr0_lut[monitor_index]) = (lvdncr0 | (uint8_t) LVD_PRV_LVDCR0_BIT3_MASK); + #if BSP_FEATURE_LVD_HAS_LVDLVLR == 1 + + /* Critical section required because LVCMPCR register is shared with other instances. */ + FSP_CRITICAL_SECTION_ENTER; + + /* Disable voltage detection circuit. */ + R_SYSTEM->LVCMPCR &= (uint8_t) ~(p_ctrl->p_cfg->monitor_number << R_SYSTEM_LVCMPCR_LVD1E_Pos); + + FSP_CRITICAL_SECTION_EXIT; + #else + *(g_lvdncmpcr_lut[monitor_index]) &= (uint8_t) ~R_SYSTEM_LVD1CMPCR_LVDE_Msk; + #endif +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LVD); + gp_ctrls[monitor_index] = NULL; + } + +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 + else + { + uint32_t monitor_index = p_ctrl->p_cfg->monitor_number - 3; + + /* Enable access to LVD registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); + + /* Disable voltage monitor interrupt. */ + *g_ext_lvdicr_lut[monitor_index] &= (uint8_t) ~(LVD_PRV_EXT_LVDICR_IE_ENABLE); + + /* Disable voltage detection circuit. */ + *g_ext_lvdcmpcr_lut[monitor_index] &= (uint8_t) ~(R_SYSTEM_VBTCMPCR_CMPE_Msk); + + /* Disable pin LVD output. */ + *g_ext_lvdcr_lut[monitor_index] &= (uint8_t) ~(LVD_PRV_EXT_LVDCR_LVDE_ENABLE); + + /* Disable access to LVD registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LVD); + } +#endif + + p_ctrl->open = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup LVD-PVD) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the hardware based on the user defined configuration settings. + * + * @param[in] p_ctrl Pointer to the control structure for the driver instance + * + **********************************************************************************************************************/ +static void r_lvd_hw_configure (lvd_instance_ctrl_t * p_ctrl) +{ +#if 2U == BSP_FEATURE_LVD_VERSION + uint32_t lvd1cr = 0; + + /* Configure the voltage threshold setting. */ + lvd1cr &= (uint8_t) ~(R_SYSTEM_LVD1CR_LVD1V_Msk); + lvd1cr |= (uint32_t) (p_ctrl->p_cfg->voltage_threshold << R_SYSTEM_LVD1CR_LVD1V_Pos); + + if (LVD_RESPONSE_NONE != p_ctrl->p_cfg->detection_response) + { + if (LVD_RESPONSE_INTERRUPT == p_ctrl->p_cfg->detection_response) + { + /* Configure the voltage monitor as interrupt mode. */ + lvd1cr |= LVD_PRV_LVD1CR_LVD1SEL_INTERRUPT << R_SYSTEM_LVD1CR_LVD1SEL_Pos; + + /* Configure the voltage monitor interrupt type as maskable. */ + lvd1cr |= LVD_PRV_LVD1CR_IRQSEL_MASKABLE << R_SYSTEM_LVD1CR_IRQSEL_Pos; + + /* Enable interrupt in NVIC. */ + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->irq, p_ctrl->p_cfg->monitor_ipl, p_ctrl); + } + else if (LVD_RESPONSE_NMI == p_ctrl->p_cfg->detection_response) + { + /* Enable the NMI handler. */ + R_BSP_GroupIrqWrite((bsp_grp_irq_t) (BSP_GRP_IRQ_LVD1), lvd_nmi_handler); + + /* Configure the voltage monitor as interrupt mode. */ + lvd1cr |= LVD_PRV_LVD1CR_LVD1SEL_INTERRUPT << R_SYSTEM_LVD1CR_LVD1SEL_Pos; + + /* Configure the voltage monitor interrupt type as non-maskable. */ + lvd1cr |= LVD_PRV_LVD1CR_IRQSEL_NON_MASKABLE << R_SYSTEM_LVD1CR_IRQSEL_Pos; + + /* Enable NMI for this LVD monitor. NMIER bits can only be set. They cannot be cleared. */ + R_ICU->NMIER = (uint16_t) (R_ICU_NMIER_LVD1EN_Msk); + } + else /* LVD_RESPONSE_RESET */ + { + /* Enable voltage monitor reset when the voltage falls to below threshold. */ + lvd1cr |= LVD_PRV_LVD1CR_LVD1SEL_RESET << R_SYSTEM_LVD1CR_LVD1SEL_Pos; + } + } + + /* Enable LVD1 operation. */ + lvd1cr |= LVD_PRV_LVD1CR_LVD1EN_ENABLE << R_SYSTEM_LVD1CR_LVD1EN_Pos; + + /* Enable access to LVD registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); + + /* Enable writing to the LVD1CR register. */ + R_SYSTEM->LVD1MKR_b.MK = LVD_PRV_LVD1MKR_MK_ENABLE; + + /* Writing to the LVD1CR register. */ + R_SYSTEM->LVD1CR = (uint8_t) lvd1cr; + + /* Disable writing to the LVD1CR register. */ + R_SYSTEM->LVD1MKR_b.MK = LVD_PRV_LVD1MKR_MK_DISABLE; + + /* Wait for LVD1 stabilization. */ + R_BSP_SoftwareDelay(BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); +#else + FSP_CRITICAL_SECTION_DEFINE; + + uint32_t lvdncr0 = 0; + uint32_t lvdncr1 = 0; + + /* Calculate index used to get monitor registers from look-up tables and perform other calculations. */ + uint32_t monitor_index = p_ctrl->p_cfg->monitor_number - 1; + + if (p_ctrl->p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_NMI) + { + /* Configure the voltage monitor interrupt condition. */ + lvdncr1 |= (uint32_t) (p_ctrl->p_cfg->voltage_slope << R_SYSTEM_LVD1CR1_IDTSEL_Pos); + + if (LVD_RESPONSE_NONE != p_ctrl->p_cfg->detection_response) + { + if (LVD_RESPONSE_INTERRUPT == p_ctrl->p_cfg->detection_response) + { + /* Configure the voltage monitor interrupt type as maskable. */ + lvdncr1 |= R_SYSTEM_LVD1CR1_IRQSEL_Msk; + + /* Enable interrupt in NVIC. */ + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->irq, p_ctrl->p_cfg->monitor_ipl, p_ctrl); + } + else if (LVD_RESPONSE_NMI == p_ctrl->p_cfg->detection_response) + { + /* Enable the NMI handler. */ + R_BSP_GroupIrqWrite((bsp_grp_irq_t) (BSP_GRP_IRQ_LVD1 + monitor_index), lvd_nmi_handler); + + /* Enable NMI for this LVD monitor. NMIER bits can only be set. They cannot be cleared. */ + R_ICU->NMIER = (uint16_t) (1U << (2U + monitor_index)); + } + else + { + /* LVD_RESPONSE_RESET or LVD_RESPONSE_RESET_ON_RISING. */ + + /* Voltage monitor reset enabled. */ + lvdncr0 |= R_SYSTEM_LVD1CR0_RI_Msk; + + /* Configure the voltage monitor reset negation mode. */ + lvdncr0 |= (uint32_t) (p_ctrl->p_cfg->negation_delay << R_SYSTEM_LVD1CR0_RN_Pos); + } + } + } + + /* Amount of time to wait before enabling output of voltage monitor comparison results. */ + uint32_t delay; + if (LVD_MONITOR_LVD1 == p_ctrl->p_cfg->monitor_number) + { + /* LVD monitor is LVD1. */ + delay = BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US; + } + else + { + /* LVD monitor is LVD2. */ + delay = BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US; + } + + #if BSP_FEATURE_LVD_HAS_DIGITAL_FILTER == 1 + if (LVD_SAMPLE_CLOCK_DISABLED != p_ctrl->p_cfg->sample_clock_divisor) + { + /* Configure the digital filter clock divider. */ + lvdncr0 |= (uint32_t) (p_ctrl->p_cfg->sample_clock_divisor << R_SYSTEM_LVD1CR0_FSAMP_Pos); + + /* Wait for at least 2n + 3 LOCO cycles, where n = [2,4,8,16]. */ + uint32_t filter_delay = r_lvd_filter_delay(p_ctrl->p_cfg->sample_clock_divisor); + + /* If filter delay is greater than the stabilization delay, wait for filter delay. */ + if (filter_delay > delay) + { + delay = filter_delay; + } + } + else + { + /* Disable the digital filter. */ + lvdncr0 |= R_SYSTEM_LVD1CR0_DFDIS_Msk; + } + #endif + + /* See Setup procedure from Table "Procedure for setting bits related to the voltage monitor 1 + * interrupt and voltage monitor 1 reset so that voltage monitoring operates" + * in the LVD section of the relevant hardware manual. */ + + /* Enable access to LVD registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); + + #if (BSP_FEATURE_LVD_HAS_LVDLVLR == 1) + uint32_t lvdne_mask = p_ctrl->p_cfg->monitor_number << R_SYSTEM_LVCMPCR_LVD1E_Pos; + uint32_t lvdlvr_offset = g_lvdlvlr_offset_lut[monitor_index]; + + /* Critical section required because LVCMPCR and LVDLVLR registers are shared with other instances. */ + FSP_CRITICAL_SECTION_ENTER; + + /* Disable the voltage detection circuit before writing the LVDLVLR register. */ + R_SYSTEM->LVCMPCR &= (uint8_t) ~lvdne_mask; + + /* Configure the voltage threshold setting. */ + uint32_t lvdlvlr = R_SYSTEM->LVDLVLR; + lvdlvlr &= ~(g_lvdlvlr_mask_lut[monitor_index]); + lvdlvlr |= (uint32_t) (p_ctrl->p_cfg->voltage_threshold << lvdlvr_offset); + + /* Write the voltage level setting. */ + R_SYSTEM->LVDLVLR = (uint8_t) lvdlvlr; + + /* Enable the voltage detection circuit. */ + R_SYSTEM->LVCMPCR |= (uint8_t) lvdne_mask; + + FSP_CRITICAL_SECTION_EXIT; + #else + + /* Unlock control registers for PVD4 and PVD5. + * Any additional write to PVDLR will lock it to 1 until the next POR, Reset pin toggle, or PVD0 reset. */ + #if (3U == BSP_FEATURE_LVD_VERSION) + if (R_SYSTEM->PVDLR != 0) + { + R_SYSTEM->PVDLR = 0; + } + + /* Write value to bit 6 in LVD4CR0 and LVD5CR0 should be 1. */ + if ((p_ctrl->p_cfg->monitor_number == 4) || (p_ctrl->p_cfg->monitor_number == 5)) + { + lvdncr0 |= (uint8_t) (1 << R_SYSTEM_LVD4CR0_RI_Pos); + } + #endif + uint8_t lvdne[LVD_PRV_NUMBER_OF_VCC_MONITOR]; + uint8_t i; + + /* Critical section required because LVCMPCR and LVDLVLR registers are shared with other instances. */ + FSP_CRITICAL_SECTION_ENTER; + + /* To change a LVDNLVL register both voltage detection circuits must be disabled. + * Disable the voltage detection circuit for all monitors before writing the LVDLVLR register. + * See "LVD1CMPCR : Voltage Monitoring 1 Comparator Control Register" description in the + * relevant hardware manual. */ + for (i = 0; i < LVD_PRV_NUMBER_OF_VCC_MONITOR; i++) + { + if (0 != ((1 << i) & BSP_FEATURE_LVD_MONITOR_MASK)) + { + /* Preserve enable values for other monitors. */ + lvdne[i] = *(g_lvdncmpcr_lut[i]) & R_SYSTEM_LVD1CMPCR_LVDE_Msk; + + /* Disable the monitor. */ + *(g_lvdncmpcr_lut[i]) &= (uint8_t) ~R_SYSTEM_LVD1CMPCR_LVDE_Msk; + } + } + + /* Configure the voltage threshold setting. */ + uint8_t lvdncmpcr = *(g_lvdncmpcr_lut[monitor_index]); + lvdncmpcr &= (uint8_t) ~(g_lvdnlvl_mask_lut[monitor_index]); + lvdncmpcr |= p_ctrl->p_cfg->voltage_threshold; + + /* Write the voltage level setting. */ + *(g_lvdncmpcr_lut[monitor_index]) = lvdncmpcr; + + #if BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE + if (LVD_RESPONSE_RESET_ON_RISING == p_ctrl->p_cfg->detection_response) + { + /* When LVD reset generated by the VCC-rise detection is required, RHSEL must be set to 1. */ + *(g_lvdnfcr_lut[monitor_index]) = 1; + } + else + { + *(g_lvdnfcr_lut[monitor_index]) = 0; + } + #endif + + /* Enable the voltage detection circuits. */ + for (i = 0; i < LVD_PRV_NUMBER_OF_VCC_MONITOR; i++) + { + if (0 != ((1 << i) & BSP_FEATURE_LVD_MONITOR_MASK)) + { + if (monitor_index == i) + { + *(g_lvdncmpcr_lut[monitor_index]) |= R_SYSTEM_LVD1CMPCR_LVDE_Msk; + } + else + { + *(g_lvdncmpcr_lut[i]) |= lvdne[i]; + } + } + } + FSP_CRITICAL_SECTION_EXIT; + #endif + + /* Write settings to control registers. Write value to lvdncr0.bit3 should be 1. */ + *(g_lvdncr0_lut[monitor_index]) = (uint8_t) (lvdncr0 | LVD_PRV_LVDCR0_BIT3_MASK); + *(g_lvdncr1_lut[monitor_index]) = (uint8_t) lvdncr1; + + if (p_ctrl->p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_NMI) + { + /* Clear DET before setting RIE. */ + *(g_lvdnsr_lut[monitor_index]) = 0; + } + + if (LVD_RESPONSE_NONE != p_ctrl->p_cfg->detection_response) + { + /* Reset/Interrupt enable bit set after clearing DET bit. Write value to lvdncr0.bit3 should be 1. */ + *(g_lvdncr0_lut[monitor_index]) |= (R_SYSTEM_LVD1CR0_RIE_Msk | LVD_PRV_LVDCR0_BIT3_MASK); + } + + /* Wait for LVD and filter stabilization. */ + R_BSP_SoftwareDelay(delay, BSP_DELAY_UNITS_MICROSECONDS); + + /* Enable output of comparison results by voltage monitor. Write value to lvdncr0.bit3 should be 1. */ + *(g_lvdncr0_lut[monitor_index]) |= (R_SYSTEM_LVD1CR0_CMPE_Msk | LVD_PRV_LVDCR0_BIT3_MASK); +#endif + + /* Disable access to LVD registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LVD); +} + +#if BSP_FEATURE_LVD_HAS_DIGITAL_FILTER == 1 + +/*******************************************************************************************************************//** + * Calculates the microseconds to delay after enabling the digital filter. + * + * @param[in] sample_clock_divisor The configured sample clock divisor for the digital filter + * + * @retval microseconds Number of microseconds to delay + **********************************************************************************************************************/ +static uint32_t r_lvd_filter_delay (lvd_sample_clock_t sample_clock_divisor) +{ + uint32_t loco_cycles = (uint32_t) (1 << (sample_clock_divisor + 1)) * 2 + 3; + + return (loco_cycles * LVD_PRV_SECONDS_TO_MICROSECONDS) / BSP_LOCO_HZ + 1U; +} + +#endif + +#if (LVD_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * Helper function to do parameter checking for R_LVD_Open. + * + * @param[in] p_ctrl Pointer to the control block structure for the driver instance + * @param[in] p_cfg Pointer to the configuration structure for the driver instance + * + * @retval FSP_SUCCESS Successful + * @retval FSP_ERR_ASSERTION Requested configuration was invalid + * @retval FSP_ERR_ALREADY_OPEN The instance was already opened + * @retval FSP_ERR_IN_USE Another instance is already using the desired monitor + * @retval FSP_ERR_UNSUPPORTED Digital filter was enabled on a device that does not support it + **********************************************************************************************************************/ +static fsp_err_t lvd_open_parameter_check (lvd_instance_ctrl_t * p_ctrl, lvd_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(LVD_OPENED != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN(LVD_THRESHOLD_NOT_AVAILABLE != p_cfg->voltage_threshold, FSP_ERR_INVALID_ARGUMENT); + #if (BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1) + FSP_ASSERT(1U <= p_cfg->monitor_number && 5U >= p_cfg->monitor_number); + #else + FSP_ASSERT(0 != ((1 << (p_cfg->monitor_number - 1)) & BSP_FEATURE_LVD_MONITOR_MASK)); + #endif + #if (3U == BSP_FEATURE_LVD_VERSION) + if (p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_VCC_MONITOR) + { + FSP_ERROR_RETURN(NULL == gp_ctrls[p_cfg->monitor_number - 1], FSP_ERR_IN_USE); + } + + #else + if (p_cfg->monitor_number <= LVD_PRV_NUMBER_OF_NMI) + { + FSP_ERROR_RETURN(NULL == gp_ctrls[p_cfg->monitor_number - 1], FSP_ERR_IN_USE); + } + #endif + + int32_t threshold = (int32_t) p_cfg->voltage_threshold; + + /* Verify that the threshold is valid for voltage monitor. */ + switch (p_cfg->monitor_number) + { + case 1: + { + /* High voltage thresholds correspond to low register settings. */ + FSP_ASSERT(threshold >= (int32_t) BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD && + threshold <= (int32_t) BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD); + break; + } + + case 2: + #if (3U == BSP_FEATURE_LVD_VERSION) + case 4: + case 5: + #endif + { + /* High voltage thresholds correspond to low register settings. */ + FSP_ASSERT(threshold >= (int32_t) BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD && + threshold <= (int32_t) BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD); + break; + } + + /* If the device does not support an external monitor, the check below will be skipped. */ + #if (BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1) + case 3: + { + /* High voltage thresholds correspond to low register settings. */ + FSP_ASSERT(threshold <= (int32_t) BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD && + threshold >= (int32_t) BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD); + break; + } + + case 4: + { + /* High voltage thresholds correspond to low register settings. */ + FSP_ASSERT(threshold <= (int32_t) BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD && + threshold >= (int32_t) BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD); + break; + } + + case 5: + { + /* Checking for EXLVD will be skipped because it doesn't have threshold configuration. */ + break; + } + #endif + default: + { + break; + } + } + + /* If the response is an interrupt then IRQ setting must be a valid interrupt number. */ + if (LVD_RESPONSE_INTERRUPT == p_cfg->detection_response) + { + FSP_ASSERT(p_cfg->irq >= 0); + } + + /* If the response is a maskable or non-maskable interrupt then a callback must be provided. */ + if ((LVD_RESPONSE_INTERRUPT == p_cfg->detection_response) || (LVD_RESPONSE_NMI == p_cfg->detection_response)) + { + FSP_ASSERT(NULL != p_cfg->p_callback); + } + + #if 3U == BSP_FEATURE_LVD_VERSION + if ((p_cfg->monitor_number == 4) || (p_cfg->monitor_number == 5)) + { + if (LVD_RESPONSE_RESET == p_cfg->detection_response) + { + /* Negation shall only follow a stabilization time (tPVDm) after VCC > Vdetm is detected on VCC-falling reset and VCC-rising reset. */ + FSP_ASSERT(LVD_NEGATION_DELAY_FROM_VOLTAGE == p_cfg->negation_delay); + } + } + #endif + if (LVD_RESPONSE_RESET_ON_RISING == p_cfg->detection_response) + { + /* Negation shall only follow a stabilization time (tPVDm) after VCC < Vdetm is detected on VCC-rising reset. */ + FSP_ASSERT(LVD_NEGATION_DELAY_FROM_VOLTAGE == p_cfg->negation_delay); + } + + #if BSP_FEATURE_LVD_HAS_DIGITAL_FILTER == 0 + FSP_ERROR_RETURN(LVD_SAMPLE_CLOCK_DISABLED == p_cfg->sample_clock_divisor, FSP_ERR_UNSUPPORTED); + #endif + + return FSP_SUCCESS; +} + +#endif + +/*********************************************************************************************************************** + * Private funtions configure LVD of VBAT, RTC, EX + * + * @param[in] p_ctrl Pointer to the control block structure for the driver instance + * + **********************************************************************************************************************/ +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 +static void r_lvd_ext_hw_configure (lvd_instance_ctrl_t * p_ctrl) +{ + /* Calculate index used to get monitor registers from look-up tables and perform other calculations. */ + uint32_t monitor_index = p_ctrl->p_cfg->monitor_number - 3; + #if (0UL != BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US) + uint8_t current_rtclvl = 0; + uint8_t new_rtclvl = 0; + #endif + + /* Enable access to LVD registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); + + /* Specify the detection voltage by setting the nLVDCR.LVL bits */ + switch (monitor_index) + { + case 0: + { + /* Configure voltage threshold for LVD of VBAT */ + *g_ext_lvdcr_lut[monitor_index] = + (uint8_t) (p_ctrl->p_cfg->voltage_threshold << R_SYSTEM_VBTLVDCR_LVL_Pos); + break; + } + + case 1: + { + #if (0UL == BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US) + + /* Configure voltage threshold for LVD of VRTC. */ + *g_ext_lvdcr_lut[monitor_index] = + (uint8_t) (p_ctrl->p_cfg->voltage_threshold << R_SYSTEM_VRTLVDCR_LVL_Pos); + break; + #elif (0UL != BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US) + + /* Check the current state and new desire state of LVL field. */ + new_rtclvl = (uint8_t) (p_ctrl->p_cfg->voltage_threshold) < LVD_THRESHOLD_LVDVRTC_LEVEL_1_99V ? 0 : 1; + + current_rtclvl = (uint8_t) (*g_ext_lvdcr_lut[monitor_index] >> R_SYSTEM_VRTLVDCR_LVL_Pos) <= + LVD_THRESHOLD_LVDVRTC_LEVEL_1_99V ? 0 : 1; + + /* If change from voltage_threshold > 2 back to voltage_threshold < 2 a intermediate stage and 300us is required. */ + if (new_rtclvl >= current_rtclvl) + { + /* Direct change */ + *g_ext_lvdcr_lut[monitor_index] = + (uint8_t) (p_ctrl->p_cfg->voltage_threshold << R_SYSTEM_VRTLVDCR_LVL_Pos); + } + else + { + /* Change to (intermediate stage) and wait 300us before change to desired voltage_threshold */ + *g_ext_lvdcr_lut[monitor_index] = + (uint8_t) (LVD_THRESHOLD_LVDVRTC_LEVEL_1_99V << R_SYSTEM_VRTLVDCR_LVL_Pos); + R_BSP_SoftwareDelay((uint32_t) BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US, + BSP_DELAY_UNITS_MICROSECONDS); + *g_ext_lvdcr_lut[monitor_index] = + (uint8_t) (p_ctrl->p_cfg->voltage_threshold << R_SYSTEM_VRTLVDCR_LVL_Pos); + } + break; + #endif + } + + case 2: + { + /* EXLVD doesn't have threshold configuration */ + break; + } + + default: + { + break; + } + } + + /* Select the interrupt request timing in the nLVDICR.IDTSEL bits */ + *g_ext_lvdicr_lut[monitor_index] = (uint8_t) (p_ctrl->p_cfg->voltage_slope << R_SYSTEM_VBTLVDICR_IDTSEL_Pos); + + /* Set the nLVDCR.LVDE bit to 1 to enable pin low voltage detection */ + *g_ext_lvdcr_lut[monitor_index] |= (uint8_t) LVD_PRV_EXT_LVDCR_LVDE_ENABLE; + + /* Waiting for the comparator operation stabilization time */ + if (LVD_MONITOR_LVD_VBAT == p_ctrl->p_cfg->monitor_number) + { + /* LVD monitor is LVD VBAT. */ + R_BSP_SoftwareDelay((uint32_t) BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else if (LVD_MONITOR_LVD_VRTC == p_ctrl->p_cfg->monitor_number) + { + /* LVD monitor is LVD VRTC. */ + R_BSP_SoftwareDelay((uint32_t) BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + } + else + { + /* LVD monitor is EXLVD. */ + R_BSP_SoftwareDelay((uint32_t) BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US, BSP_DELAY_UNITS_MICROSECONDS); + } + + /* Set the nCMPCR.CMPE bit to 1 to enable pin voltage detect circuit. */ + *g_ext_lvdcmpcr_lut[monitor_index] = (uint8_t) R_SYSTEM_VBTCMPCR_CMPE_Msk; + + if (LVD_RESPONSE_NONE != p_ctrl->p_cfg->detection_response) + { + /* Make sure that the nSR.DET flag is 0. */ + *g_ext_lvdsr_lut[monitor_index] &= (uint8_t) (~R_SYSTEM_VBTLVDSR_DET_Msk); + + /* Set the nLVDICR.IE bit to 1 to enable pin low voltage detection interrupt output. */ + *g_ext_lvdicr_lut[monitor_index] |= (uint8_t) (LVD_PRV_EXT_LVDICR_IE_ENABLE); + + /* Enable interrupt in NVIC. */ + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->irq, p_ctrl->p_cfg->monitor_ipl, p_ctrl); + } + else + { + /* Disable interrupt. */ + *g_ext_lvdicr_lut[monitor_index] &= (uint8_t) (~LVD_PRV_EXT_LVDICR_IE_ENABLE); + } + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LVD); +} + +#endif + +/*******************************************************************************************************************//** + * Common code needed for all LVD ISRs. + * + * @param[in] p_ctrl Pointer to the control block structure for the driver instance + * + **********************************************************************************************************************/ +static void lvd_common_isr_handler (lvd_instance_ctrl_t * p_ctrl) +{ + /* Calculate index used to get monitor registers from look-up tables and perform other calculations. */ + uint32_t monitor_index = p_ctrl->p_cfg->monitor_number - 1; + + lvd_callback_args_t callback_args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + lvd_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack. */ + p_args = &callback_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + callback_args = *p_args; + } + + p_args->current_state = + (lvd_current_state_t) ((*(g_lvdnsr_lut[monitor_index]) & R_SYSTEM_LVD1SR_MON_Msk) > 0); + p_args->monitor_number = p_ctrl->p_cfg->monitor_number; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + lvd_prv_ns_callback p_callback = (lvd_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = callback_args; + } + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); + + /* Clear the status register. */ + *(g_lvdnsr_lut[monitor_index]) = 0; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LVD); +} + +/*******************************************************************************************************************//** + * ISR for maskable LVD interrupts + * + **********************************************************************************************************************/ +void lvd_lvd_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + +#if BSP_FEATURE_ICU_HAS_IELSR + + /* Clear the Interrupt Request. */ + R_BSP_IrqStatusClear(irq); +#endif + + /* Call common isr handler. */ + lvd_common_isr_handler((lvd_instance_ctrl_t *) R_FSP_IsrContextGet(irq)); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR handler for non-maskable interrupts + * + * @param[in] irq BSP group IRQ identifier + * + **********************************************************************************************************************/ +static void lvd_nmi_handler (bsp_grp_irq_t irq) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + /* Call common isr handler. */ + lvd_common_isr_handler(gp_ctrls[irq - BSP_GRP_IRQ_LVD1]); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR for maskable interrupts LVD of VBAT, RTC, EX + * + **********************************************************************************************************************/ +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 +void lvd_ext_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear the Interrupt Request. */ + R_BSP_IrqStatusClear(irq); + + /* Call common isr handler. */ + lvd_ext_common_isr_handler((lvd_instance_ctrl_t *) R_FSP_IsrContextGet(irq)); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} + +#endif + +/*********************************************************************************************************************** + * ISR handle for LVD interrupts of VBAT, RTC, EX + * + * @param[in] irq BSP group IRQ indenttifier + * + **********************************************************************************************************************/ +#if BSP_FEATURE_LVD_HAS_EXT_MONITOR == 1 +static void lvd_ext_common_isr_handler (lvd_instance_ctrl_t * p_ctrl) +{ + /* Calculate index used to get monitor registers from look-up tables and perform other calculations. */ + uint32_t monitor_index = p_ctrl->p_cfg->monitor_number - 3; + + lvd_callback_args_t callback_args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be stored in + * non-secure memory so they can be accessed by a non-secure callback function. */ + lvd_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack. */ + p_args = &callback_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + callback_args = *p_args; + } + + p_args->current_state = + (lvd_current_state_t) ((*(g_ext_lvdsr_lut[monitor_index]) & R_SYSTEM_VBTLVDSR_MON_Msk) > 0); + p_args->monitor_number = p_ctrl->p_cfg->monitor_number; + p_args->p_context = p_ctrl->p_context; + + uint8_t det_flag = *g_ext_lvdsr_lut[monitor_index] & (uint8_t) (R_SYSTEM_VBTLVDSR_DET_Msk); + + #if BSP_TZ_SECURE_BUILD + + /* Make sure if nLVDSR.DET bit is 1. */ + if (det_flag != 0) + { + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + lvd_prv_ns_callback p_callback = (lvd_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + } + + #else + + /* Make sure if nLVDSR.DET bit is 1. */ + if (det_flag != 0) + { + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call + * the callback. */ + p_ctrl->p_callback(p_args); + } + #endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = callback_args; + } + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); + + /* Clear the status register. */ + *g_ext_lvdsr_lut[monitor_index] = 0; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LVD); +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi.c new file mode 100644 index 0000000000..04db3c0541 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi.c @@ -0,0 +1,495 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_mipi_csi.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define MIPI_CSI_OPEN (0x4D504943) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * mipi_csi_prv_ns_callback)(mipi_csi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile mipi_csi_prv_ns_callback)(mipi_csi_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +const mipi_csi_api_t g_mipi_csi = +{ + .open = R_MIPI_CSI_Open, + .close = R_MIPI_CSI_Close, + .start = R_MIPI_CSI_Start, + .stop = R_MIPI_CSI_Stop, + .read = R_MIPI_CSI_Read, + .statusGet = R_MIPI_CSI_StatusGet, +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void mipi_csi_rx_isr(void); +void mipi_csi_dl_isr(void); +void mipi_csi_vc_isr(void); +void mipi_csi_pm_isr(void); +void mipi_csi_gst_isr(void); + +static void csi_isr_enable(mipi_csi_irq_cfg_t const * irq_cfg, void * p_context); +static void csi_isr_disable(mipi_csi_irq_cfg_t const * irq_cfg); + +static void csi_call_callback(mipi_csi_instance_ctrl_t * p_ctrl, mipi_csi_callback_args_t * p_args); + +/*******************************************************************************************************************//** + * @addtogroup MIPI_CSI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Initialize the MIPI CSI peripheral. + * + * @retval FSP_SUCCESS The channel was successfully opened. + * @retval FSP_ERR_ASSERTION One or both of the parameters was NULL. + * @retval FSP_ERR_ALREADY_OPEN The instance is already opened. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_CSI_Open (mipi_csi_ctrl_t * const p_api_ctrl, mipi_csi_cfg_t const * const p_cfg) +{ + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) p_api_ctrl; + +#if MIPI_CSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(MIPI_CSI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + p_ctrl->p_cfg = p_cfg; + + /* Start clocks to the MIPI CSI peripheral */ + R_BSP_MODULE_START(FSP_IP_MIPI_CSI, 0); + + /* Open MIPI Phy */ + mipi_phy_api_t const * p_phy_api = p_cfg->p_mipi_phy_instance->p_api; + mipi_phy_cfg_t const * p_phy_cfg = p_cfg->p_mipi_phy_instance->p_cfg; + mipi_phy_ctrl_t * p_phy_ctrl = p_cfg->p_mipi_phy_instance->p_ctrl; + fsp_err_t err = p_phy_api->open(p_phy_ctrl, p_phy_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Open MIPI CSI */ + R_MIPI_CSI->MCT3_b.RXEN = 0; // Ensure reception is disabled before configuration + FSP_HARDWARE_REGISTER_WAIT(R_MIPI_CSI->RTST_b.VSRSTS, 0x0); // Ensure reset not currently in progress - This covers re-opening after stopping reception + + R_MIPI_CSI->MCT0 = p_cfg->ctrl_data.control_0_mask; // Module Control Register 0 + R_MIPI_CSI->MCT2 = p_cfg->ctrl_data.control_2_mask; // Module Control Register 2 + R_MIPI_CSI->EPCT = p_cfg->option_data.epd_option_0_mask; // Efficient Packet Delimter (EPD) settings + R_MIPI_CSI->EMCT = p_cfg->option_data.epd_option_1_mask; // EPD Option settings + *((uint64_t *) &R_MIPI_CSI->DTEL) = p_cfg->option_data.data_type_enable; // Receive Data Type Enable + R_MIPI_CSI->GSCT = p_cfg->ctrl_data.short_packet_control_mask; // Short Data Packet Control + + R_MIPI_CSI->RXIE = p_cfg->interrupt_cfg.receive_enable_mask; + R_MIPI_CSI->DLIE0 = p_cfg->interrupt_cfg.data_lane_enable_mask[0]; + R_MIPI_CSI->DLIE1 = p_cfg->interrupt_cfg.data_lane_enable_mask[1]; + uint32_t volatile * base_addr = (uint32_t volatile *) &R_MIPI_CSI->VCIE0; + for (uint32_t i = 0; i < 16; i++) + { + base_addr[0x10 / 4 * i] = (p_cfg->interrupt_cfg.virtual_channel_enable_mask)[i]; + } + + R_MIPI_CSI->PMIE = p_cfg->interrupt_cfg.power_management_enable_mask; + R_MIPI_CSI->GSIE = p_cfg->interrupt_cfg.short_packet_enable_mask; + + p_ctrl->p_callback_memory = NULL; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + csi_isr_enable(&p_cfg->interrupt_cfg.receive_cfg, (void *) p_ctrl); + csi_isr_enable(&p_cfg->interrupt_cfg.data_lane_cfg, (void *) p_ctrl); + csi_isr_enable(&p_cfg->interrupt_cfg.virtual_channel_cfg, (void *) p_ctrl); + csi_isr_enable(&p_cfg->interrupt_cfg.power_management_cfg, (void *) p_ctrl); + csi_isr_enable(&p_cfg->interrupt_cfg.short_packet_cfg, (void *) p_ctrl); + + /* Mark control block as opened */ + p_ctrl->open = MIPI_CSI_OPEN; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Close MIPI CSI and display data instances, disable interrupts, and power-off the module. + * + * @retval FSP_SUCCESS The channel is successfully closed. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_CSI_Close (mipi_csi_ctrl_t * const p_api_ctrl) +{ + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) p_api_ctrl; + +#if MIPI_CSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(MIPI_CSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + mipi_csi_cfg_t const * const p_cfg = p_ctrl->p_cfg; + csi_isr_disable(&p_cfg->interrupt_cfg.receive_cfg); + csi_isr_disable(&p_cfg->interrupt_cfg.data_lane_cfg); + csi_isr_disable(&p_cfg->interrupt_cfg.virtual_channel_cfg); + csi_isr_disable(&p_cfg->interrupt_cfg.power_management_cfg); + csi_isr_disable(&p_cfg->interrupt_cfg.short_packet_cfg); + + /* Close MIPI Phy */ + mipi_phy_api_t const * p_phy_api = p_cfg->p_mipi_phy_instance->p_api; + mipi_phy_ctrl_t * p_phy_ctrl = p_cfg->p_mipi_phy_instance->p_ctrl; + fsp_err_t err = p_phy_api->close(p_phy_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set control block to closed */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Start video output. + * Initialize Video Output Registers + * Perform sequence steps 3 to 5 from "Start of Video Mode Operation" in the MIPI DSI section of the relevant hardware manual". + * + * @retval FSP_SUCCESS Data is successfully written to the D/A Converter. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_INVALID_STATE CSI is already in video mode. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_CSI_Start (mipi_csi_ctrl_t * const p_api_ctrl) +{ +#if MIPI_CSI_CFG_PARAM_CHECKING_ENABLE + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(MIPI_CSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(!R_MIPI_CSI->MCT3_b.RXEN, FSP_ERR_INVALID_STATE); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Enable CSI Reception */ + R_MIPI_CSI->MCT3_b.RXEN = 1; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Stop video capture. + * - NOTE: Application shall issue stop command to the peripheral and wait at least one full frame before calling + * CSI_Stop, after ensuring MIPI CSI reception is no longer active by checking data returned by GetStatus() + * + * @retval FSP_SUCCESS Data is successfully written to the D/A Converter. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_CSI_Stop (mipi_csi_ctrl_t * const p_api_ctrl) +{ +#if MIPI_CSI_CFG_PARAM_CHECKING_ENABLE + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(MIPI_CSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /*---------------------------------------------------------------------------------------------------- + * Follow procedure identified in Figure "Receiving operation stopped" in the MIPI CSI section of the + * relevant hardware manual + * - NOTE: Application shal stop transmission fromperipheral before calling MIPI_CSI Stop function. + *----------------------------------------------------------------------------------------------------*/ + FSP_ASSERT(R_MIPI_CSI->RXSC_b.RACTDETC); // Reception must not be active when calling Stop(). See note above. + R_MIPI_CSI->MCT3_b.RXEN = 0; + R_MIPI_CSI->RTCT_b.VSRST = 1; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Provide information about current MIPI CSI status. + * + * @retval FSP_SUCCESS Information read successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_CSI_StatusGet (mipi_csi_ctrl_t * const p_api_ctrl, mipi_csi_status_t * p_status) +{ +#if MIPI_CSI_CFG_PARAM_CHECKING_ENABLE + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_status); + FSP_ERROR_RETURN(MIPI_CSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + p_status->state = R_MIPI_CSI->RXST_b.RACTDET ? MIPI_CSI_STATE_RECEIVING : MIPI_CSI_STATE_IDLE; + R_MIPI_CSI->RXSC_b.RACTDETC = 1; // Clear RX active flag + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Read Short Packet Data From FIFO. + * + * @retval FSP_SUCCESS Information read successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_UNDERFLOW Packet FIFO empty. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_CSI_Read (mipi_csi_ctrl_t * const p_api_ctrl, mipi_csi_short_packet_t * p_data) +{ +#if MIPI_CSI_CFG_PARAM_CHECKING_ENABLE + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_data); + FSP_ERROR_RETURN(MIPI_CSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + fsp_err_t err = FSP_ERR_UNDERFLOW; + if (R_MIPI_CSI->GSST_b.PNUM) + { + R_MIPI_CSI->GSIU_b.FINC = 1; + p_data->mask = R_MIPI_CSI->GSHT; + err = FSP_SUCCESS; + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup MIPI_CSI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Calls user callback + **********************************************************************************************************************/ +static void csi_call_callback (mipi_csi_instance_ctrl_t * p_ctrl, mipi_csi_callback_args_t * p_args) +{ + mipi_csi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + mipi_csi_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + mipi_csi_prv_ns_callback p_callback = (mipi_csi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Private helper functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Enable the specified ISR and add the control structure to the ISR context lookup table. + * + * @param[in] irq_cfg Pointer to interrupt configuration structure + * @param[in] p_ctrl Pointer to MIPI CSI instance control block + **********************************************************************************************************************/ +static void csi_isr_enable (mipi_csi_irq_cfg_t const * irq_cfg, void * p_context) +{ + R_BSP_IrqCfgEnable(irq_cfg->irq, irq_cfg->ipl, p_context); +} + +/*********************************************************************************************************************** + * Disable the specified ISR + * + * @param[in] irq_cfg Pointer to interrupt configuration structure + **********************************************************************************************************************/ +static void csi_isr_disable (mipi_csi_irq_cfg_t const * irq_cfg) +{ + R_BSP_IrqDisable(irq_cfg->irq); + R_FSP_IsrContextSet(irq_cfg->irq, NULL); +} + +/*********************************************************************************************************************** + * Interrupt Service Routines + **********************************************************************************************************************/ + +/*---------------------------------------------------------------------------------------------------- + * Receive Interrupt Service Routine + *--------------------------------------------------------------------------------------------------*/ +void mipi_csi_rx_isr (void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + mipi_csi_callback_args_t args; + args.event = MIPI_CSI_EVENT_FRAME_DATA; + args.event_idx = 0xFF; + args.event_data.receive_status.mask = R_MIPI_CSI->RXST; + args.p_context = p_ctrl->p_context; + + R_MIPI_CSI->RXSC = (args.event_data.receive_status.mask & R_MIPI_CSI_RXSC_RACTDETC_Msk); // Only clear RACTDETC (receive active detect) + R_BSP_IrqStatusClear(irq); + + csi_call_callback(p_ctrl, &args); +} + +/*---------------------------------------------------------------------------------------------------- + * Data Lane Interrupt Service Routine + *--------------------------------------------------------------------------------------------------*/ +void mipi_csi_dl_isr (void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + mipi_csi_interrupt_status_t interrupt_status = {.mask = R_MIPI_CSI->MIST}; + uint32_t lane0_status = R_MIPI_CSI->DLST0; + uint32_t lane1_status = R_MIPI_CSI->DLST1; + R_MIPI_CSI->DLSC0 = (lane0_status & ~R_MIPI_CSI_DLST0_ULP_Msk); // ULPS Escape has no clear bit + R_MIPI_CSI->DLSC1 = (lane1_status & ~R_MIPI_CSI_DLST0_ULP_Msk); // ULPS Escape has no clear bit + R_BSP_IrqStatusClear(irq); + + mipi_csi_callback_args_t args; + args.p_context = p_ctrl->p_context; + args.event = MIPI_CSI_EVENT_DATA_LANE; + if (interrupt_status.bits.data_lane_0) + { + args.event_idx = 0; + args.event_data.data_lane_status.mask = lane0_status; + csi_call_callback(p_ctrl, &args); + } + + if (interrupt_status.bits.data_lane_1) + { + args.event_idx = 1; + args.event_data.data_lane_status.mask = lane1_status; + csi_call_callback(p_ctrl, &args); + } +} + +/*---------------------------------------------------------------------------------------------------- + * Virtual Channel Interrupt Service Routine + *--------------------------------------------------------------------------------------------------*/ +void mipi_csi_vc_isr (void) +{ +#define MIPI_CSI_VC_GENERIC_ERRORS (R_MIPI_CSI_VCST0_MLF_Msk | R_MIPI_CSI_VCST0_ECD_Msk) + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + mipi_csi_interrupt_status_t interrupt_status = {.mask = R_MIPI_CSI->MIST}; + uint32_t generic_errors_u32 = 0; + mipi_csi_callback_args_t args; + args.event = MIPI_CSI_EVENT_VIRTUAL_CHANNEL; + args.p_context = p_ctrl->p_context; + for (uint8_t i = 0; i < 16; i++) + { + if (interrupt_status.bits.virtual_channel.mask & (1 << i)) + { + uint32_t volatile * p_vc_status = (uint32_t volatile *) ((&R_MIPI_CSI->VCST0) + 0x10 / 4 * i); + uint32_t volatile * p_vc_clear = (uint32_t volatile *) ((&R_MIPI_CSI->VCSC0) + 0x10 / 4 * i); + uint32_t vc_status_u32 = *p_vc_status; + *p_vc_clear = vc_status_u32; // Clear error flags for this channel + + /* Malformed packet and 2-Bit ECC errors are applied to all virtual channels */ + generic_errors_u32 |= vc_status_u32 & MIPI_CSI_VC_GENERIC_ERRORS; + vc_status_u32 &= ~MIPI_CSI_VC_GENERIC_ERRORS; + + args.event_idx = i; + args.event_data.virtual_channel_status.mask = vc_status_u32; + csi_call_callback(p_ctrl, &args); + } + } + + R_BSP_IrqStatusClear(irq); + args.event_idx = 0xFF; + args.event_data.virtual_channel_status.mask = generic_errors_u32; + csi_call_callback(p_ctrl, &args); + +#undef MIPI_CSI_VC_GENERIC_ERRORS +} + +/*---------------------------------------------------------------------------------------------------- + * Power Management Interrupt Service Routine + *--------------------------------------------------------------------------------------------------*/ +void mipi_csi_pm_isr (void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + mipi_csi_callback_args_t args; + args.event = MIPI_CSI_EVENT_POWER; + args.event_idx = 0xFF; + args.event_data.power_status.mask = R_MIPI_CSI->PMST; + args.p_context = p_ctrl->p_context; + R_MIPI_CSI->PMSC = args.event_data.power_status.mask & 0xFF; // Only lower 8 bits have status to clear + + R_BSP_IrqStatusClear(irq); + + csi_call_callback(p_ctrl, &args); +} + +/*---------------------------------------------------------------------------------------------------- + * Generic Short Packet Interrupt Service Routine + *--------------------------------------------------------------------------------------------------*/ +void mipi_csi_gst_isr (void) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + mipi_csi_instance_ctrl_t * p_ctrl = (mipi_csi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + mipi_csi_callback_args_t args; + args.event = MIPI_CSI_EVENT_SHORT_PACKET_FIFO; + args.event_idx = 0xFF; + args.event_data.fifo_status.mask = R_MIPI_CSI->GSST; + args.p_context = p_ctrl->p_context; + + R_MIPI_CSI->GSSC = (args.event_data.fifo_status.mask & R_MIPI_CSI_GSST_GOV_Msk); // Only clear GOVC (overflow status) + + R_BSP_IrqStatusClear(irq); + + csi_call_callback(p_ctrl, &args); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi_contract_types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi_contract_types.h new file mode 100644 index 0000000000..d8f21f8575 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi_contract_types.h @@ -0,0 +1,49 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup MIPI_CSI + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_MIPI_CSI_CONTRACT_TYPES_H +#define R_MIPI_CSI_CONTRACT_TYPES_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "r_mipi_csi_device_types.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Type definitions + **********************************************************************************************************************/ + +typedef struct st_mipi_csi_event_data +{ + union + { + mipi_csi_receive_status_t receive_status; + mipi_csi_data_lane_status_t data_lane_status; + mipi_csi_virtual_channel_status_t virtual_channel_status; + mipi_csi_power_status_t power_status; + mipi_csi_short_packet_fifo_status_t fifo_status; + }; +} mipi_csi_event_data_t; + +/* @} (end addtogroup MIPI_CSI) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi_device_types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi_device_types.h new file mode 100644 index 0000000000..41c6fa1eea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_csi/r_mipi_csi_device_types.h @@ -0,0 +1,405 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup MIPI_CSI + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_MIPI_CSI_DEVICE_TYPES_H +#define R_MIPI_CSI_DEVICE_TYPES_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Type definitions + **********************************************************************************************************************/ + +/* MIPI CSI Variable Length Spacer Type */ +typedef enum e_mipi_csi_variable_length_spacer +{ + MIPI_CSI_VARIABLE_LENGTH_SPACER_NONE = 0, ///< Variable length spacer invalid (spacer number is fixed length) + MIPI_CSI_VARIABLE_LENGTH_SPACER_1 = 1, ///< Variable length spacer valid (spacer number is 1 * n/lane) + MIPI_CSI_VARIABLE_LENGTH_SPACER_2 = 2, ///< Variable length spacer valid (spacer number is 2 * n/lane) + MIPI_CSI_VARIABLE_LENGTH_SPACER_4 = 3, ///< Variable length spacer valid (spacer number is 4 * n/lane) +} mipi_csi_variable_length_spacer_t; + +/* MIPI CSI Receive Data Enable Type */ +typedef enum e_mipi_csi_rx_data_enable +{ + MIPI_CSI_RX_DATA_ENABLE_EOT = 1ULL << 4, ///< MIPI CSI Data Type Enable EoT Reception + MIPI_CSI_RX_DATA_ENABLE_SHORT_PACKET_1 = 1ULL << 8, ///< MIPI CSI Data Type Enable Generic Short Packet 1 Reception + MIPI_CSI_RX_DATA_ENABLE_SHORT_PACKET_2 = 1ULL << 9, ///< MIPI CSI Data Type Enable Generic Short Packet 2 Reception + MIPI_CSI_RX_DATA_ENABLE_SHORT_PACKET_3 = 1ULL << 10, ///< MIPI CSI Data Type Enable Generic Short Packet 3 Reception + MIPI_CSI_RX_DATA_ENABLE_SHORT_PACKET_4 = 1ULL << 11, ///< MIPI CSI Data Type Enable Generic Short Packet 4 Reception + MIPI_CSI_RX_DATA_ENABLE_SHORT_PACKET_5 = 1ULL << 12, ///< MIPI CSI Data Type Enable Generic Short Packet 5 Reception + MIPI_CSI_RX_DATA_ENABLE_SHORT_PACKET_6 = 1ULL << 13, ///< MIPI CSI Data Type Enable Generic Short Packet 6 Reception + MIPI_CSI_RX_DATA_ENABLE_SHORT_PACKET_7 = 1ULL << 14, ///< MIPI CSI Data Type Enable Generic Short Packet 7 Reception + MIPI_CSI_RX_DATA_ENABLE_SHORT_PACKET_8 = 1ULL << 15, ///< MIPI CSI Data Type Enable Generic Short Packet 8 Reception + MIPI_CSI_RX_DATA_ENABLE_YUV422_8_BIT = 1ULL << 30, ///< MIPI CSI Data Type Enable YUV 422 8-bit Streaming Data Reception + MIPI_CSI_RX_DATA_ENABLE_YUV422_10_BIT = 1ULL << 31, ///< MIPI CSI Data Type Enable YUV 422 10-bit Streaming Data Reception + MIPI_CSI_RX_DATA_ENABLE_RGB888 = 1ULL << 35, ///< MIPI CSI Data Type Enable RAW8 Streaming Data Reception + MIPI_CSI_RX_DATA_ENABLE_RAW8 = 1ULL << 41, ///< MIPI CSI Data Type Enable RGB888 Streaming Data Reception +} mipi_csi_rx_data_enable_t; + +/** MIPI CSI Interrupt Status Type (MIST) */ +typedef union st_mipi_csi_interrupt_status +{ + struct + { + uint32_t data_lane_0 : 1; ///< MIPI CSI Data Lane 0 Interrupt Status + uint32_t data_lane_1 : 1; ///< MIPI CSI Data Lane 1 Interrupt Status + uint32_t : 6; + uint32_t power_management : 1; ///< MIPI CSI Power Management Interrupt Status + uint32_t short_packet : 1; ///< MIPI CSI Generic Short Packet Interrupt Status + uint32_t receive : 1; ///< MIPI CSI Receive Interrupt Status + uint32_t : 5; + union + { + struct + { + uint32_t vc_00 : 1; ///< MIPI CSI Virtual Channel 00 Interrupt Status + uint32_t vc_01 : 1; ///< MIPI CSI Virtual Channel 01 Interrupt Status + uint32_t vc_02 : 1; ///< MIPI CSI Virtual Channel 02 Interrupt Status + uint32_t vc_03 : 1; ///< MIPI CSI Virtual Channel 03 Interrupt Status + uint32_t vc_04 : 1; ///< MIPI CSI Virtual Channel 04 Interrupt Status + uint32_t vc_05 : 1; ///< MIPI CSI Virtual Channel 05 Interrupt Status + uint32_t vc_06 : 1; ///< MIPI CSI Virtual Channel 06 Interrupt Status + uint32_t vc_07 : 1; ///< MIPI CSI Virtual Channel 07 Interrupt Status + uint32_t vc_08 : 1; ///< MIPI CSI Virtual Channel 08 Interrupt Status + uint32_t vc_09 : 1; ///< MIPI CSI Virtual Channel 09 Interrupt Status + uint32_t vc_10 : 1; ///< MIPI CSI Virtual Channel 10 Interrupt Status + uint32_t vc_11 : 1; ///< MIPI CSI Virtual Channel 11 Interrupt Status + uint32_t vc_12 : 1; ///< MIPI CSI Virtual Channel 12 Interrupt Status + uint32_t vc_13 : 1; ///< MIPI CSI Virtual Channel 13 Interrupt Status + uint32_t vc_14 : 1; ///< MIPI CSI Virtual Channel 14 Interrupt Status + uint32_t vc_15 : 1; ///< MIPI CSI Virtual Channel 15 Interrupt Status + } bits; + uint16_t mask; ///< MIPI CSI Virtual Channel Interrupt Status Bit-Mask + } virtual_channel; + } bits; + uint32_t mask; +} mipi_csi_interrupt_status_t; + +/** MIPI CSI Receive Status Type (RXST) */ +typedef union st_mipi_csi_receive_status +{ + struct + { + union + { + struct + { + uint32_t vc_00 : 1; ///< MIPI CSI Virtual Channel 00 Frame Active Receive Status + uint32_t vc_01 : 1; ///< MIPI CSI Virtual Channel 01 Frame Active Receive Status + uint32_t vc_02 : 1; ///< MIPI CSI Virtual Channel 02 Frame Active Receive Status + uint32_t vc_03 : 1; ///< MIPI CSI Virtual Channel 03 Frame Active Receive Status + uint32_t vc_04 : 1; ///< MIPI CSI Virtual Channel 04 Frame Active Receive Status + uint32_t vc_05 : 1; ///< MIPI CSI Virtual Channel 05 Frame Active Receive Status + uint32_t vc_06 : 1; ///< MIPI CSI Virtual Channel 06 Frame Active Receive Status + uint32_t vc_07 : 1; ///< MIPI CSI Virtual Channel 07 Frame Active Receive Status + uint32_t vc_08 : 1; ///< MIPI CSI Virtual Channel 08 Frame Active Receive Status + uint32_t vc_09 : 1; ///< MIPI CSI Virtual Channel 09 Frame Active Receive Status + uint32_t vc_10 : 1; ///< MIPI CSI Virtual Channel 10 Frame Active Receive Status + uint32_t vc_11 : 1; ///< MIPI CSI Virtual Channel 11 Frame Active Receive Status + uint32_t vc_12 : 1; ///< MIPI CSI Virtual Channel 12 Frame Active Receive Status + uint32_t vc_13 : 1; ///< MIPI CSI Virtual Channel 13 Frame Active Receive Status + uint32_t vc_14 : 1; ///< MIPI CSI Virtual Channel 14 Frame Active Receive Status + uint32_t vc_15 : 1; ///< MIPI CSI Virtual Channel 15 Frame Active Receive Status + } bits; + uint16_t mask; ///< MIPI CSI Virtual Channel Interrupt Status Bit-Mask + } virtual_channel; + uint32_t receive_active : 1; ///< MIPI CSI Receive Active Status + uint32_t receive_detect : 1; ///< MIPI CSI Receive Start Detect Status + } bits; + uint32_t mask; +} mipi_csi_receive_status_t; + +/** MIPI CSI Data Lane Status Type (DSLTn) */ +typedef union st_mipi_csi_data_lane_status +{ + struct + { + uint32_t err_sot_hs : 1; ///< MIPI CSI Data Lane Start of Transmission (SoT) High Speed Error Detected + uint32_t err_sot_sync : 1; ///< MIPI CSI Data Lane Start of Transmission (SoT) Synchronization High Speed Error Detected + uint32_t err_control : 1; ///< MIPI CSI Data Lane Control Error Detected + uint32_t err_escape : 1; ///< MIPI CSI Data Lane Escape Sequence Error Detected + uint32_t : 12; + uint32_t ulps_exit : 1; ///< MIPI CSI Data Lane Exit From Ultra Low-Power State (ULPS) Detect + uint32_t ulps_enter : 1; ///< MIPI CSI Data Lane Entry To Ultra Low-Power State (ULPS) Detect + uint32_t : 6; + uint32_t escape_detect : 1; ///< MIPI CSI Data Lane Ultra Low-Power State Escape Detect + uint32_t : 7; + } bits; + uint32_t mask; +} mipi_csi_data_lane_status_t; + +/** MIPI CSI Virtual Channel Status Type (VCSTm) */ +typedef union st_mipi_csi_virtual_channel_status +{ + struct + { + uint32_t malformed : 1; ///< MIPI CSI Virtual Channel Error Malformed Packet + uint32_t err_ecc_2_bit : 1; ///< MIPI CSI Virtual Channel Error ECC 2-bit (Double) + uint32_t err_crc : 1; ///< MIPI CSI Virtual Channel Error CRC + uint32_t err_id : 1; ///< MIPI CSI Virtual Channel Error ID + uint32_t err_word_count : 1; ///< MIPI CSI Virtual Channel Error Word Count + uint32_t err_ecc_1_bit : 1; ///< MIPI CSI Virtual Channel Error ECC 1-bit (Corrected) + uint32_t ecc_no_error : 1; ///< MIPI CSI Virtual Channel ECC No-Error + uint32_t : 1; + uint32_t err_frame_sync : 1; ///< MIPI CSI Virtual Channel Error Frame Sync + uint32_t err_frame_data : 1; ///< MIPI CSI Virtual Channel Error Frame Data + uint32_t : 6; + uint32_t short_packet_overflow : 1; ///< MIPI CSI Virtual Channel Error Generic Short Packet FIFO Overflow + uint32_t : 7; + uint32_t frame_start : 1; ///< MIPI CSI Virtual Channel Detect Frame Start + uint32_t frame_end : 1; ///< MIPI CSI Virtual Channel Detect Frame End + uint32_t line_start : 1; ///< MIPI CSI Virtual Channel Detect Line Start + uint32_t line_end : 1; ///< MIPI CSI Virtual Channel Detect Line End + uint32_t eotp : 1; ///< MIPI CSI Virtual Channel Detect End of Transmission Short Packet (EoTp) + } bits; + uint32_t mask; +} mipi_csi_virtual_channel_status_t; + +/** MIPI CSI Power Status Type (PMST) */ +typedef union st_mipi_csi_power_status +{ + struct + { + uint32_t stop_state_data_exit : 1; ///< MIPI CSI Power Status Data Lane Stop State Exit Detect + uint32_t stop_state_data_enter : 1; ///< MIPI CSI Power Status Data Lane Stop State Entry Detect + uint32_t stop_clock_state_exit : 1; ///< MIPI CSI Power Status Clock Lane Stop State Exit Detect + uint32_t stop_clock_state_enter : 1; ///< MIPI CSI Power Status Clock Lane Stop State Entry Detect + uint32_t ulps_data_exit : 1; ///< MIPI CSI Power Status Ultra Low-Power State (ULPS) Data Exit + uint32_t ulps_data_enter : 1; ///< MIPI CSI Power Status Ultra Low-Power State (ULPS) Data Enter + uint32_t ulps_clock_exit : 1; ///< MIPI CSI Power Status Ultra Low-Power State (ULPS) Clock Exit + uint32_t ulps_clock_enter : 1; ///< MIPI CSI Power Status Ultra Low-Power State (ULPS) Clock Enter + uint32_t : 6; + uint32_t clock_stop_state : 1; ///< MIPI CSI Power Status Clock Stop State + uint32_t clock_interted : 1; ///< MIPI CSI Power Status Clock Inverted + uint32_t data_lane_0_stop : 1; ///< MIPI CSI Power Status Data Lane 0 Stop State + uint32_t data_lane_1_stop : 1; ///< MIPI CSI Power Status Data Lane 1 Stop State + uint32_t : 6; + uint32_t data_lane_0_ulps_state : 1; ///< MIPI CSI Power Status Ultra Low-Power State (ULPS) Data Lane 0 Escape State + uint32_t data_lane_1_ulps_state : 1; ///< MIPI CSI Power Status Ultra Low-Power State (ULPS) Data Lane 0 Escape State + } bits; + uint32_t mask; +} mipi_csi_power_status_t; + +/** MIPI CSI Short Packet FIFO Type (GSST) */ +typedef union st_mipi_csi_short_packet_fifo_status +{ + struct + { + uint32_t not_empty : 1; ///< MIPI CSI Generic Short Packet FIFO Not Empty Status + uint32_t threshold_met : 1; ///< MIPI CSI Generic Short Packet FIFO Contains Number of Packets Exceeds Threshold + uint32_t : 2; + uint32_t overflow : 1; ///< MIPI CSI Generic Short Packet FIFO Overflow Status + uint32_t : 3; + uint32_t packet_count : 8; ///< MIPI CSI Generic Short Packet FIFO Packet Count + uint32_t clear : 1; ///< MIPI CSI Generic Short Packet FIFO Not Empty Status + uint32_t disable : 1; ///< MIPI CSI Generic Short Packet FIFO Not Empty Status + } bits; + uint32_t mask; +} mipi_csi_short_packet_fifo_status_t; + +/** MIPI CSI Control Data */ +typedef struct st_mipi_csi_ctrl_data +{ + /* (MCT0) */ + union + { + struct + { + uint32_t lane_count : 4; ///< Number of lanes for operation + uint32_t : 12; + uint32_t zero_length_packet_output : 1; ///< Output Long Packet With Word-Count of Zero to VIN + uint32_t err_frame_notify : 1; ///< Notifies ErrFrameData when an ECC 2-bit error or a packet of less than 4 bytes is received between FS and FE + uint32_t : 1; + uint32_t reserved_packet_reception : 1; ///< Receive packets with a data type 0x39 to 0x3E, which are reserved in CSI-2 standard “Table 10 Data Type Classes”. + uint32_t generic_rule_mode : 1; ///< Output all data to VIN according to Generic CSI-2 Rule + uint32_t : 3; + uint32_t ecc_check_24_bits : 1; ///< CSI-2 specification-compliant mode of ECC checking (0: 26-bit ECC Check, 1: 24-bit ECC Check) + uint32_t descramble_enable : 1; ///< Enable Descrambling + } control_0_bits; + uint32_t control_0_mask; + }; + + /* (MCT2) */ + union + { + struct + { + uint32_t frrclk : 9; ///< Frequency clock rate to determine packet reception end + uint32_t : 7; + uint32_t frrskw : 9; ///< Frequency clock rate to adjust data lane skew + } control_2_bits; + uint32_t control_2_mask; + }; + + /* (GSCT) */ + union + { + struct + { + uint32_t threshold : 7; ///< Frequency clock rate to determine packet reception end + uint32_t : 9; + uint32_t fifo_enable : 1; ///< Frequency clock rate to adjust data lane skew + uint32_t : 15; + } short_packet_control_bits; + uint32_t short_packet_control_mask; + }; +} mipi_csi_ctrl_data_t; + +/** MIPI CSI IRQ Configuration structure */ +typedef struct st_mipi_csi_irq_cfg +{ + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< Interrupt vector number +} mipi_csi_irq_cfg_t; + +/** MIPI CSI Interrupt control configuration */ +typedef struct st_mipi_csi_interrupt_cfg +{ + mipi_csi_irq_cfg_t receive_cfg; ///< Video Input Operation interrupt + mipi_csi_irq_cfg_t data_lane_cfg; ///< Data Lane interrupt + mipi_csi_irq_cfg_t virtual_channel_cfg; ///< Virtual Channel interrupt + mipi_csi_irq_cfg_t power_management_cfg; ///< Power Management interrupt + mipi_csi_irq_cfg_t short_packet_cfg; ///< Short Packet interrupt + + /* (RXIE) */ + union + { + struct + { + uint32_t : 17; + uint32_t rx_detect : 1; ///< Receive Detect Interrupt Enable + } receive_enable_bits; + uint32_t receive_enable_mask; + }; + + /* (DLIE) */ + union + { + struct + { + uint32_t err_sot_hs_detect : 1; ///< Start of Transmission Error Detect Interrupt + uint32_t err_sot_sync_hs_detect : 1; ///< Start of Transmission Synchronization Error Detect Interrupt + uint32_t err_control_detect : 1; ///< Control Error Detect Interrupt + uint32_t err_escape_detect : 1; ///< Escape Sequence Error Detect Interrupt + uint32_t : 12; + uint32_t ulps_exit_detect : 1; ///< ULPS Exit Detect Interrupt Enable Interrupt + uint32_t ulps_enter_detect : 1; ///< ULPS Enter Detect Interrupt Enable Interrupt + } data_lane_enable_bits[2]; + uint32_t data_lane_enable_mask[2]; + }; + + /* (VCIE) */ + union + { + struct + { + uint32_t malformed_packet_detect : 1; ///< Error Malformed Packet Detect Interrupt + uint32_t error_ecc_2_bit_detect : 1; ///< Error ECC 2-bit Detect Interrupt + uint32_t error_crc_detect : 1; ///< Error CRC Packet Detect Interrupt + uint32_t error_id_detect : 1; ///< Error ID Packet Detect Interrupt + uint32_t error_word_count_detect : 1; ///< Error Word Count Packet Detect Interrupt + uint32_t error_ecc_1_bit_detect : 1; ///< Error ECC 1-bit (corrected) Packet Detect Interrupt + uint32_t ecc_no_error_detect : 1; ///< ECC No-Error Packet Detect Interrupt + uint32_t : 1; + uint32_t error_frame_sync_detect : 1; ///< Error Frame Sync Detect Interrupt + uint32_t error_frame_data_detect : 1; ///< Error Frame Data Detect Interrupt + uint32_t : 6; + uint32_t short_packet_fifo_overflow_detect : 1; ///< Generic Short Packet FIFO Overflow Detect Interrupt + uint32_t : 7; + uint32_t frame_start_detect : 1; ///< Frame Start Packet Detect Interrupt + uint32_t frame_end_detect : 1; ///< Frame End Packet Detect Interrupt + uint32_t line_start_detect : 1; ///< Line Start Packet Detect Interrupt + uint32_t line_end_detect : 1; ///< Line End Packet Detect Interrupt + uint32_t eotp_detect : 1; ///< End of Transmission Packet (EoTp) Detect Interrupt + } virtual_channel_enable_bits[16]; + uint32_t virtual_channel_enable_mask[16]; + }; + + /* (PMIE) */ + union + { + struct + { + uint32_t data_stop_state_exit : 1; ///< Power Management Data Lane Stop State Exit Detect Interrupt + uint32_t data_stop_state_enter : 1; ///< Power Management Data Lane Stop State Enter Detect Interrupt + uint32_t clock_stop_state_exit : 1; ///< Power Management Clock Lane Stop State Exit Detect Interrupt + uint32_t clock_stop_state_enter : 1; ///< Power Management Clock Lane Stop State Enter Detect Interrupt + uint32_t data_ulps_exit : 1; ///< Power Management Data Lane ULPS Exit Detect Interrupt + uint32_t data_ulps_enter : 1; ///< Power Management Data Lane ULPS Enter Detect Interrupt + uint32_t clock_ulps_exit : 1; ///< Power Management Clock Lane ULPS Exit Detect Interrupt + uint32_t clock_ulps_enter : 1; ///< Power Management Clock Lane ULPS Enter Detect Interrupt + uint32_t : 24; + } power_management_enable_bits; + uint32_t power_management_enable_mask; + }; + + /* (GSIE) */ + union + { + struct + { + uint32_t fifo_not_empty : 1; ///< Generic Short Packet FIFO Not Empty Detect + uint32_t fifo_threshold_exceeded : 1; ///< Generic Short Packet FIFO Threshold Exceeded Detect + uint32_t : 2; + uint32_t fifo_overflow : 1; ///< Generic Short Packet FIFO Overflow Detect + uint32_t : 27; + } short_packet_enable_bits; + uint32_t short_packet_enable_mask; + }; +} mipi_csi_interrupt_cfg_t; + +typedef struct st_mipi_csi_option_data +{ + /* (EPCT) */ + union + { + struct + { + uint32_t long_packet_spacers : 15; ///< Specify the number of spacers/lanes inserted after a long packet. + uint32_t epd_option : 1; ///< Efficient Packet Delimiter (EPD) Option Select (Must be 1 when EPDEN is 1) + uint32_t epd_short_spacers : 15; ///< EPD Short Packet Spacers + uint32_t epd_enable : 1; ///< Enable Efficient Packet Delimiter (EPD) Operation + } epd_option_0_bits; + uint32_t epd_option_0_mask; + }; + + /* (EMCT) */ + union + { + struct + { + uint32_t : 4; + mipi_csi_variable_length_spacer_t variable_spacer_insertion : 2; ///< Enable Variable length spacer insertion when EPD Option 2 is enabled. + uint32_t eotpen : 1; ///< Enables (EOTP) when EPD Option 2 is enabled + uint32_t : 25; + } epd_option_1_bits; + uint32_t epd_option_1_mask; + }; + + mipi_csi_rx_data_enable_t data_type_enable : 64; ///< MIPI CSI Data Type Enable +} mipi_csi_option_data_t; + +/* @} (end addtogroup MIPI_CSI) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_dsi/r_mipi_dsi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_dsi/r_mipi_dsi.c new file mode 100644 index 0000000000..ce65bda7c8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_dsi/r_mipi_dsi.c @@ -0,0 +1,1094 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_mipi_dsi.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define MIPI_DSI_OPEN (0x4D504944) +#define MIPI_MAX_CH0_CMD (128) +#define MIPI_MAX_CH1_CMD (1024) +#define MIPI_DSI_RSRST_RESET_BITS (R_MIPI_DSI_RSTSR_RSTHS_Msk | \ + R_MIPI_DSI_RSTSR_RSTLP_Msk | \ + R_MIPI_DSI_RSTSR_RSTAPB_Msk | \ + R_MIPI_DSI_RSTSR_RSTAXI_Msk | \ + R_MIPI_DSI_RSTSR_RSTV_Msk) + +#define DSI_PACKET_FORMAT_IS_SHORT(cmd_id) ((cmd_id & 0x0F) <= 0x08) +#define DSI_PACKET_FORMAT_IS_LONG(cmd_id) ((cmd_id & 0x0F) > 0x08) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * mipi_dsi_prv_ns_callback)(mipi_dsi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile mipi_dsi_prv_ns_callback)(mipi_dsi_callback_args_t * p_args); +#endif + +typedef enum e_mipi_dsi_clock_state +{ + MIPI_DSI_CLOCK_STATE_IDLE, ///< MIPI DSI Clock is off + MIPI_DSI_CLOCK_STATE_STARTING, ///< MIPI DSI Clock starting + MIPI_DSI_CLOCK_STATE_STARTED, ///< MIPI DSI Clock is started + MIPI_DSI_CLOCK_STATE_STOPPING, ///< MIPI DSI Clock is stopping +} mipi_dsi_clock_state_t; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +static volatile mipi_dsi_clock_state_t g_clock_state; +static volatile bool g_video_started; + +const mipi_dsi_api_t g_mipi_dsi = +{ + .open = R_MIPI_DSI_Open, + .close = R_MIPI_DSI_Close, + .start = R_MIPI_DSI_Start, + .stop = R_MIPI_DSI_Stop, + .ulpsEnter = R_MIPI_DSI_UlpsEnter, + .ulpsExit = R_MIPI_DSI_UlpsExit, + .command = R_MIPI_DSI_Command, + .statusGet = R_MIPI_DSI_StatusGet, +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void mipi_dsi_seq0_isr(void); +void mipi_dsi_seq1_isr(void); +void mipi_dsi_vin1_isr(void); +void mipi_dsi_rcv_isr(void); +void mipi_dsi_ferr_isr(void); +void mipi_dsi_ppi_isr(void); + +static void dsi_isr_enable(mipi_dsi_irq_cfg_t const * irq_cfg, mipi_dsi_instance_ctrl_t * p_ctrl); +static void dsi_isr_disable(mipi_dsi_irq_cfg_t const * irq_cfg); + +static void dsi_enter_reset(void); +static void dsi_init_timing(mipi_dsi_cfg_t const * const p_cfg); +static void dsi_exit_reset(mipi_dsi_cfg_t const * const p_cfg); +static void dsi_hs_clock_start(mipi_dsi_instance_ctrl_t * p_ctrl); +static void dsi_hs_clock_stop(mipi_dsi_instance_ctrl_t * p_ctrl); + +static void dsi_init_video(mipi_dsi_cfg_t const * p_cfg); + +static void dsi_call_callback(mipi_dsi_instance_ctrl_t * p_ctrl, mipi_dsi_callback_args_t * p_args); + +static fsp_err_t dsi_stop(mipi_dsi_instance_ctrl_t * p_ctrl); +static uint32_t dsi_cmd_sequence_register_a(mipi_dsi_cmd_t * p_cmd); +static uint32_t dsi_cmd_sequence_register_b(mipi_dsi_cmd_t * p_cmd); +static uint32_t dsi_cmd_sequence_register_c(mipi_dsi_cmd_t * p_cmd); +static uint32_t dsi_cmd_sequence_register_d(mipi_dsi_cmd_t * p_cmd); + +/*******************************************************************************************************************//** + * @addtogroup MIPI_DSI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Initialize the MIPI DSI peripheral. + * + * @retval FSP_SUCCESS The channel was successfully opened. + * @retval FSP_ERR_ASSERTION One or both of the parameters was NULL. + * @retval FSP_ERR_ALREADY_OPEN The instance is already opened. + * @retval FSP_ERR_INVALID_STATE Display module must be opened before DSI. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_Open (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cfg_t const * const p_cfg) +{ + fsp_err_t err; + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; + +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(MIPI_DSI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + FSP_ERROR_RETURN(R_GLCDC->SYSCNT.PANEL_CLK_b.CLKEN, FSP_ERR_INVALID_STATE); + + /* Initialize internal state */ + g_clock_state = MIPI_DSI_CLOCK_STATE_IDLE; + g_video_started = false; + p_ctrl->p_cfg = p_cfg; + + /* Start clocks to the MIPI DSI peripheral */ + R_BSP_MODULE_START(FSP_IP_MIPI_DSI, 0); + + err = r_mipi_phy_open(p_cfg->p_mipi_phy_instance->p_ctrl, p_cfg->p_mipi_phy_instance->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Perform sequence steps 4 to 8 from "Software Reset" in MIPI DSI section of the + * relevant hardware hardware manual. */ + dsi_enter_reset(); + dsi_init_timing(p_cfg); + dsi_exit_reset(p_cfg); + + /* Configure interrupt sources */ + mipi_dsi_extended_cfg_t * p_extend = (mipi_dsi_extended_cfg_t *) p_cfg->p_extend; + R_MIPI_DSI->RXIER = p_extend->dsi_rxie; + R_MIPI_DSI->FERRIER = p_extend->dsi_ferrie; + R_MIPI_DSI->PLIER = p_extend->dsi_plie; + R_MIPI_DSI->VMIER = p_extend->dsi_vmie; + R_MIPI_DSI->SQCH0IER = p_extend->dsi_sqch0ie; + R_MIPI_DSI->SQCH1IER = p_extend->dsi_sqch1ie; + + /* Clear any active status bits */ + R_MIPI_DSI->SQCH0SCR = R_MIPI_DSI_SQCH0SCR_AACTFIN_Msk | + R_MIPI_DSI_SQCH0SCR_ADESFIN_Msk | + R_MIPI_DSI_SQCH0SCR_DABORT_Msk | + R_MIPI_DSI_SQCH0SCR_SIZEERR_Msk | + R_MIPI_DSI_SQCH0SCR_TXIBERR_Msk | + R_MIPI_DSI_SQCH0SCR_RXFERR_Msk | + R_MIPI_DSI_SQCH0SCR_RXFAIL_Msk | + R_MIPI_DSI_SQCH0SCR_RXPFAIL_Msk | + R_MIPI_DSI_SQCH0SCR_RXCORERR_Msk | + R_MIPI_DSI_SQCH0SCR_RXAKE_Msk; + R_MIPI_DSI->SQCH1SCR = R_MIPI_DSI_SQCH1SCR_AACTFIN_Msk | + R_MIPI_DSI_SQCH1SCR_ADESFIN_Msk | + R_MIPI_DSI_SQCH1SCR_DABORT_Msk | + R_MIPI_DSI_SQCH1SCR_SIZEERR_Msk | + R_MIPI_DSI_SQCH1SCR_TXIBERR_Msk | + R_MIPI_DSI_SQCH1SCR_RXFERR_Msk | + R_MIPI_DSI_SQCH1SCR_RXFAIL_Msk | + R_MIPI_DSI_SQCH1SCR_RXPFAIL_Msk | + R_MIPI_DSI_SQCH1SCR_RXCORERR_Msk | + R_MIPI_DSI_SQCH1SCR_RXAKE_Msk; + R_MIPI_DSI->VMSCR = R_MIPI_DSI_VMSCR_START_Msk | + R_MIPI_DSI_VMSCR_STOP_Msk | + R_MIPI_DSI_VMSCR_VIRDY_Msk | + R_MIPI_DSI_VMSCR_TIMERR_Msk | + R_MIPI_DSI_VMSCR_VBUFUDF_Msk | + R_MIPI_DSI_VMSCR_VBUFOVF_Msk; + R_MIPI_DSI->RXSCR = R_MIPI_DSI_RXSCR_BTAREND_Msk | + R_MIPI_DSI_RXSCR_LRXHTO_Msk | + R_MIPI_DSI_RXSCR_TATO_Msk | + R_MIPI_DSI_RXSCR_RXRESP_Msk | + R_MIPI_DSI_RXSCR_RXEOTP_Msk | + R_MIPI_DSI_RXSCR_RXTE_Msk | + R_MIPI_DSI_RXSCR_RXACK_Msk | + R_MIPI_DSI_RXSCR_EXTEDET_Msk | + R_MIPI_DSI_RXSCR_MLFERR_Msk | + R_MIPI_DSI_RXSCR_ECCERRM_Msk | + R_MIPI_DSI_RXSCR_UNEXERR_Msk | + R_MIPI_DSI_RXSCR_WCERR_Msk | + R_MIPI_DSI_RXSCR_CRCERR_Msk | + R_MIPI_DSI_RXSCR_IBERR_Msk | + R_MIPI_DSI_RXSCR_RXOVFERR_Msk | + R_MIPI_DSI_RXSCR_PRTOERR_Msk | + R_MIPI_DSI_RXSCR_NORESERR_Msk | + R_MIPI_DSI_RXSCR_RSIZEERR_Msk | + R_MIPI_DSI_RXSCR_ECCERRS_Msk | + R_MIPI_DSI_RXSCR_RXAKE_Msk; + + p_ctrl->p_callback_memory = NULL; + p_ctrl->p_callback = p_cfg->p_callback; + + /* Enable interrupts */ + p_ctrl->p_context = p_cfg->p_context; + dsi_isr_enable(&p_extend->dsi_seq0, p_ctrl); + dsi_isr_enable(&p_extend->dsi_seq1, p_ctrl); + dsi_isr_enable(&p_extend->dsi_ferr, p_ctrl); + dsi_isr_enable(&p_extend->dsi_ppi, p_ctrl); + dsi_isr_enable(&p_extend->dsi_rcv, p_ctrl); + dsi_isr_enable(&p_extend->dsi_vin1, p_ctrl); + + /* Mark control block as opened */ + p_ctrl->open = MIPI_DSI_OPEN; + + /* Start high-speed clock and init video */ + dsi_hs_clock_start(p_ctrl); + dsi_init_video(p_cfg); + + /* Notify application that DSI is now open */ + mipi_dsi_callback_args_t callback_args; + callback_args.event = MIPI_DSI_EVENT_POST_OPEN; + callback_args.p_context = p_ctrl->p_context; + dsi_call_callback(p_ctrl, &callback_args); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Close MIPI DSI and display data instances, disable interrupts, and power-off the module. + * + * @retval FSP_SUCCESS The channel is successfully closed. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_IN_USE Operation in progress and must be stopped before closing. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_Close (mipi_dsi_ctrl_t * const p_api_ctrl) +{ + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; + +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(MIPI_DSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Ensure video has stopped first */ + fsp_err_t err = dsi_stop(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + dsi_hs_clock_stop(p_ctrl); + + mipi_dsi_cfg_t const * p_cfg = p_ctrl->p_cfg; + mipi_dsi_extended_cfg_t * p_extend = (mipi_dsi_extended_cfg_t *) p_cfg->p_extend; + dsi_isr_disable(&p_extend->dsi_seq0); + dsi_isr_disable(&p_extend->dsi_seq1); + dsi_isr_disable(&p_extend->dsi_ferr); + dsi_isr_disable(&p_extend->dsi_ppi); + dsi_isr_disable(&p_extend->dsi_rcv); + dsi_isr_disable(&p_extend->dsi_vin1); + + /* Close MIPI PHY */ + r_mipi_phy_close(p_cfg->p_mipi_phy_instance->p_ctrl); + + /* Set control block to closed */ + p_ctrl->open = 0U; + + /* Stop clocks to the MIPI DSI peripheral */ + R_BSP_MODULE_STOP(FSP_IP_MIPI_DSI, 0); + + return err; +} + +/******************************************************************************************************************//** + * Start video output. + * Initialize Video Output Registers + * Perform sequence steps 3 to 5 from "Start of Video Mode Operation" in the MIPI DSI section of the relevant + * hardware manual. + * + * @retval FSP_SUCCESS Data is successfully written to the D/A Converter. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_IN_USE The physical interface is currently in use. + * @retval FSP_ERR_INVALID_STATE DSI is already in video mode. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_Start (mipi_dsi_ctrl_t * const p_api_ctrl) +{ + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; + +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(MIPI_DSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(!g_video_started, FSP_ERR_INVALID_STATE); +#endif + + /* Notify application that DSI is now open */ + mipi_dsi_callback_args_t callback_args; + callback_args.event = MIPI_DSI_EVENT_PRE_START; + callback_args.p_context = p_ctrl->p_context; + dsi_call_callback(p_ctrl, &callback_args); + + /* Do not start video if sequence operation is in progress */ + FSP_ERROR_RETURN(!(R_MIPI_DSI->LINKSR_b.SQ0RUN) && !(R_MIPI_DSI->LINKSR_b.SQ1RUN), FSP_ERR_IN_USE); + + mipi_dsi_cfg_t const * p_cfg = p_ctrl->p_cfg; + R_MIPI_DSI->VMSET0R = + (((uint32_t) p_cfg->hsa_no_lp << R_MIPI_DSI_VMSET0R_HSANOLP_Pos) & R_MIPI_DSI_VMSET0R_HSANOLP_Msk) | + (((uint32_t) p_cfg->hbp_no_lp << R_MIPI_DSI_VMSET0R_HBPNOLP_Pos) & R_MIPI_DSI_VMSET0R_HBPNOLP_Msk) | + (((uint32_t) p_cfg->hfp_no_lp << R_MIPI_DSI_VMSET0R_HFPNOLP_Pos) & R_MIPI_DSI_VMSET0R_HFPNOLP_Msk) | + R_MIPI_DSI_VMSET0R_VSTART_Msk; + + while ((R_MIPI_DSI->VMSR_b.VIRDY != 1) && !g_video_started) + { + /* Wait for video mode ready status + * NOTE: VMSR may be modified in isr */ + } + + g_video_started = true; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Stop video output. + * + * @retval FSP_SUCCESS Data is successfully written to the D/A Converter. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_IN_USE DSI cannot be closed while ULPS is active. + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_Stop (mipi_dsi_ctrl_t * const p_api_ctrl) +{ + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; + +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(MIPI_DSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + return dsi_stop(p_ctrl); +} + +/******************************************************************************************************************//** + * Enter Ultra-low Power State (ULPS). + * + * @retval FSP_SUCCESS Information read successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_INVALID_MODE Invalid mode for transition. + * + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_UlpsEnter (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_lane_t lane) +{ + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; + +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(MIPI_DSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Clock lane cannot enter ULPS when Continuous CLock mode is active */ + FSP_ERROR_RETURN(!((MIPI_DSI_LANE_CLOCK & lane) && R_MIPI_DSI->HSCLKSETR_b.HSCLMD), FSP_ERR_INVALID_MODE); +#endif + + /* Do not set 'enter ULPS' bit if lane is already in ULPS */ + uint32_t ulpscr = ((MIPI_DSI_LANE_DATA_ALL & lane) && !p_ctrl->data_ulps_active) ? R_MIPI_DSI_ULPSCR_DLENT_Msk : 0; + ulpscr |= + ((MIPI_DSI_LANE_CLOCK & lane) && !p_ctrl->clock_ulps_active) ? R_MIPI_DSI_ULPSCR_CLENT_Msk : 0; + p_ctrl->ulps_status |= lane; + + p_ctrl->clock_ulps_active = p_ctrl->clock_ulps_active || (MIPI_DSI_LANE_CLOCK & lane); + p_ctrl->data_ulps_active = p_ctrl->data_ulps_active || (MIPI_DSI_LANE_DATA_ALL & lane); + + R_MIPI_DSI->ULPSCR = ulpscr; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Exit Ultra-low Power State (ULPS). + * + * @retval FSP_SUCCESS Information read successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_UlpsExit (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_lane_t lane) +{ + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(MIPI_DSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Do not set 'exit ULPS' bit if lane is not in ULPS */ + uint32_t ulpscr = ((MIPI_DSI_LANE_DATA_ALL & lane) && p_ctrl->data_ulps_active) ? R_MIPI_DSI_ULPSCR_DLEXIT_Msk : 0; + ulpscr |= + ((MIPI_DSI_LANE_CLOCK & lane) && p_ctrl->clock_ulps_active) ? R_MIPI_DSI_ULPSCR_CLEXIT_Msk : 0; + + p_ctrl->clock_ulps_active = p_ctrl->clock_ulps_active && !(MIPI_DSI_LANE_CLOCK & lane); + p_ctrl->data_ulps_active = p_ctrl->data_ulps_active && !(MIPI_DSI_LANE_DATA_ALL & lane); + + R_MIPI_DSI->ULPSCR = ulpscr; + p_ctrl->ulps_status &= ~lane; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Send a command to the peripheral device. + * + * @note p_data will be used as either write data or a read buffer depending on the data id. + * @note p_data memory must not be updated until sequence operation is complete if byte_count is greater than 16. + * + * @retval FSP_SUCCESS Command(s) queued successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * cmd_id specifies a long packet but p_data is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_IN_USE The physical interface is currently in use or video mode is in operation. + * @retval FSP_ERR_INVALID_POINTER Invalid pointer provided + * @retval FSP_ERR_INVALID_ARGUMENT Invalid message configuration + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_Command (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cmd_t * p_cmd) +{ +#define SQCHnSET0R_BIT_23 (0x800000) +#define SEQUENCE_REGISTERS_SIZE (offsetof(R_MIPI_DSI_Type, SQCH1DSC0AR) - offsetof(R_MIPI_DSI_Type, SQCH0DSC0AR)) // 0x80 + +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; + + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_cmd, FSP_ERR_INVALID_POINTER); +#endif + + bool lp = (0 != (p_cmd->flags & MIPI_DSI_CMD_FLAG_LOW_POWER)); + uint8_t sequence_channel = (lp ? 0 : 1); // Sequence Channel (distinct from Virtual Channel) + +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(MIPI_DSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_cmd->p_tx_buffer || (p_cmd->tx_len == 0), FSP_ERR_INVALID_ARGUMENT); // Tx buffer must be supplied for non-zero Tx length + + FSP_ERROR_RETURN(!((sequence_channel == 0) && (p_cmd->tx_len > MIPI_MAX_CH0_CMD)), FSP_ERR_INVALID_ARGUMENT); // Max Tx size is 128 for channel 0 (LP Mode) + FSP_ERROR_RETURN(!((sequence_channel == 1) && (p_cmd->tx_len > MIPI_MAX_CH1_CMD)), FSP_ERR_INVALID_ARGUMENT); // Max Tx size is 1k for channel 1 (HS Mode) + + /* AUX Operation */ + bool aux = (p_cmd->flags & MIPI_DSI_CMD_FLAG_AUX_OPERATION); + if (aux) + { + bool bta = p_cmd->flags & + (MIPI_DSI_CMD_FLAG_BTA | MIPI_DSI_CMD_FLAG_BTA_READ | MIPI_DSI_CMD_FLAG_BTA_NO_WRITE); + bool initial_skew = (p_cmd->flags & MIPI_DSI_CMD_FLAG_ACT_CODE_INITIAL_SKEW_CAL); + bool periodic_skew = (p_cmd->flags & MIPI_DSI_CMD_FLAG_ACT_CODE_PERIODIC_SKEW_CAL); + FSP_ERROR_RETURN(!bta && !p_cmd->tx_len, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(!R_MIPI_DSI->LINKSR_b.VRUN, FSP_ERR_INVALID_ARGUMENT); // Aux operation is prohibited when video mode is running + FSP_ERROR_RETURN(!(initial_skew || periodic_skew) || (sequence_channel == 1), FSP_ERR_INVALID_ARGUMENT); // Periodic and Initial skew must be HS + } + + FSP_ERROR_RETURN(!(lp && R_MIPI_DSI->LINKSR_b.VRUN), FSP_ERR_IN_USE); // LP not allowed during video mode operation. See "Video mode Operation" in MIPI DSI section of the relevant hardware manual +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Do not modify registers if sequence operation is currently in progress */ + FSP_ERROR_RETURN(!(R_MIPI_DSI->LINKSR_b.SQ0RUN) && !(R_MIPI_DSI->LINKSR_b.SQ1RUN), FSP_ERR_IN_USE); + + uint32_t * p_sequence_reg = (uint32_t *) (&R_MIPI_DSI->SQCH0DSC0AR); + p_sequence_reg += (sequence_channel * SEQUENCE_REGISTERS_SIZE) / sizeof(uint32_t); // Offset into Sequence register 'n' + *p_sequence_reg++ = dsi_cmd_sequence_register_a(p_cmd); + *p_sequence_reg++ = dsi_cmd_sequence_register_b(p_cmd); + *p_sequence_reg++ = dsi_cmd_sequence_register_c(p_cmd); + *p_sequence_reg++ = dsi_cmd_sequence_register_d(p_cmd); + + /* Start sequence operation */ + R_MIPI_DSI->SQCH0SET0R = SQCHnSET0R_BIT_23 | (0 == sequence_channel); + R_MIPI_DSI->SQCH1SET0R = SQCHnSET0R_BIT_23 | (1 == sequence_channel); + + return FSP_SUCCESS; +#undef SQCHnSET0R_BIT_23 +#undef SEQUENCE_REGISTERS_SIZE +} + +/******************************************************************************************************************//** + * Provide information about current MIPI DSI status. + * + * Note: Accumulated Acknowledge and Error (AwER) Status is cleared by calling this function. Latest AwER status is + * only set upon reception from peripheral. + * + * @retval FSP_SUCCESS Information read successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * + **********************************************************************************************************************/ +fsp_err_t R_MIPI_DSI_StatusGet (mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_status_t * p_status) +{ +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(MIPI_DSI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + p_status->link_status = (mipi_dsi_link_status_t) R_MIPI_DSI->LINKSR; + p_status->ack_err_latest.bits = R_MIPI_DSI->AKEPLATIR; + p_status->ack_err_accumulated.bits = R_MIPI_DSI->AKEPACMSR; + + /* Clear accumulated error bits after reading */ + R_MIPI_DSI->AKEPSCR = p_status->ack_err_accumulated.bits; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup MIPI_DSI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Stop DSI operation. Basic parameter checking to be performed by caller. + * + * @param[in] p_ctrl Pointer to instance control structure + * + * @retval FSP_SUCCESS DSI stopped successfully. + * @retval FSP_ERR_IN_USE DSI cannot be stopped in ULPS. + **********************************************************************************************************************/ +static fsp_err_t dsi_stop (mipi_dsi_instance_ctrl_t * p_ctrl) +{ +#if MIPI_DSI_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(!p_ctrl->ulps_status, FSP_ERR_IN_USE); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Check if running first else the stop operation may stall indefinitely */ + if (R_MIPI_DSI->VMSR_b.RUNNING) + { + /* Initiate stop video output and wait */ + R_MIPI_DSI->VMSET0R_b.VSTOP = 1U; + + while ((R_MIPI_DSI->VMSR_b.STOP != 1) && g_video_started) + { + /* Wait for video mode stop + * - VMSR.STOP must be zero before proceeding to stop GLCDC + * NOTE: VMSR may be modified in isr */ + } + + g_video_started = false; + + /* Clear any stale VMSR status */ + R_MIPI_DSI->VMSCR = R_MIPI_DSI->VMSR; + } + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * Returns configuration values for Sequence Register A + * + * @param[in] p_cmd Pointer to formatted message structure + **********************************************************************************************************************/ +static uint32_t dsi_cmd_sequence_register_a (mipi_dsi_cmd_t * p_cmd) +{ + /* + * Long write packets contain the word count in header bytes 1 and 2. + * The payload follows the header and is word count bytes long. + * + * Short write packets encode up to two parameters in header bytes 1 + * and 2. + */ + uint8_t short_data[2]; + bool long_packet = DSI_PACKET_FORMAT_IS_LONG(p_cmd->cmd_id); + if (long_packet) + { + short_data[0] = (p_cmd->tx_len >> 0) & 0xFFU; // NOLINT(readability-magic-numbers) + short_data[1] = (p_cmd->tx_len >> 8) & 0xFFU; // NOLINT(readability-magic-numbers) + } + else + { + short_data[0] = (p_cmd->tx_len > 0) ? p_cmd->p_tx_buffer[0] : 0U; + short_data[1] = (p_cmd->tx_len > 1) ? p_cmd->p_tx_buffer[1] : 0U; + } + + uint8_t bta = + (p_cmd->flags & (MIPI_DSI_CMD_FLAG_BTA | MIPI_DSI_CMD_FLAG_BTA_READ | MIPI_DSI_CMD_FLAG_BTA_NO_WRITE)); + + uint8_t lp = (0 != (p_cmd->flags & MIPI_DSI_CMD_FLAG_LOW_POWER)); + uint32_t sequence_register_a = + (((uint32_t) short_data[0] << R_MIPI_DSI_SQCH0DSC0AR_DATA0_Pos) & R_MIPI_DSI_SQCH0DSC0AR_DATA0_Msk) | + (((uint32_t) short_data[1] << R_MIPI_DSI_SQCH0DSC0AR_DATA1_Pos) & R_MIPI_DSI_SQCH0DSC0AR_DATA1_Msk) | + (((uint32_t) p_cmd->cmd_id << R_MIPI_DSI_SQCH0DSC0AR_DT_Pos) & R_MIPI_DSI_SQCH0DSC0AR_DT_Msk) | + (((uint32_t) p_cmd->channel << R_MIPI_DSI_SQCH0DSC0AR_VC_Pos) & R_MIPI_DSI_SQCH0DSC0AR_VC_Msk) | + (((uint32_t) long_packet << R_MIPI_DSI_SQCH0DSC0AR_FMT_Pos) & R_MIPI_DSI_SQCH0DSC0AR_FMT_Msk) | + (((uint32_t) lp << R_MIPI_DSI_SQCH0DSC0AR_SPD_Pos) & R_MIPI_DSI_SQCH0DSC0AR_SPD_Msk) | + (((uint32_t) bta << R_MIPI_DSI_SQCH0DSC0AR_BTA_Pos) & R_MIPI_DSI_SQCH0DSC0AR_BTA_Msk) | + (((uint32_t) 0 << R_MIPI_DSI_SQCH0DSC0AR_NXACT_Pos) & R_MIPI_DSI_SQCH0DSC0AR_NXACT_Msk); + + return sequence_register_a; +} + +/*********************************************************************************************************************** + * Returns configuration values for Sequence Register B + * + * @param[in] p_cmd Pointer to formatted message structure + **********************************************************************************************************************/ +static uint32_t dsi_cmd_sequence_register_b (mipi_dsi_cmd_t * p_cmd) +{ + FSP_PARAMETER_NOT_USED(p_cmd); + + /* Use sequence RAM */ + return (1 << R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Pos) & R_MIPI_DSI_SQCH0DSC0BR_DTSEL_Msk; +} + +/*********************************************************************************************************************** + * Returns configuration values for Sequence Register C + * + * @param[in] p_cmd Pointer to formatted message structure + **********************************************************************************************************************/ +static uint32_t dsi_cmd_sequence_register_c (mipi_dsi_cmd_t * p_cmd) +{ + bool aux_operation = (p_cmd->flags & MIPI_DSI_CMD_FLAG_AUX_OPERATION); + bool actcode = aux_operation ? (p_cmd->flags & 0xF) : 0; // Always store Rx result in slot 0 + uint32_t sequence_register_c = + (((uint32_t) 0 << R_MIPI_DSI_SQCH0DSC0CR_FINACT_Pos) & R_MIPI_DSI_SQCH0DSC0CR_FINACT_Msk) | + (((uint32_t) aux_operation << R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Pos) & R_MIPI_DSI_SQCH0DSC0CR_AUXOP_Msk) | + (((uint32_t) actcode << R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Pos) & R_MIPI_DSI_SQCH0DSC0CR_ACTCODE_Msk); + + return sequence_register_c; +} + +/*********************************************************************************************************************** + * Returns configuration values for Sequence Register D + * + * @param[in] p_cmd Pointer to formatted message structure + **********************************************************************************************************************/ +uint32_t dsi_cmd_sequence_register_d (mipi_dsi_cmd_t * p_cmd) +{ + uint8_t bta = + (p_cmd->flags & (MIPI_DSI_CMD_FLAG_BTA | MIPI_DSI_CMD_FLAG_BTA_READ | MIPI_DSI_CMD_FLAG_BTA_NO_WRITE)); + + return (uint32_t) (bta ? p_cmd->p_rx_buffer : p_cmd->p_tx_buffer); // This buffer address is used for both Tx and Rx. +} + +/*******************************************************************************************************************//** + * Calls user callback + * + * @param[in] p_ctrl Pointer to MIPI DSI instance control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void dsi_call_callback (mipi_dsi_instance_ctrl_t * p_ctrl, mipi_dsi_callback_args_t * p_args) +{ + mipi_dsi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + mipi_dsi_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + mipi_dsi_prv_ns_callback p_callback = (mipi_dsi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Private helper functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enter Reset + * Perform sequence steps 1 and 2 from "Software Reset" in the MIPI DSI section of the relevant hardware manual. + **********************************************************************************************************************/ +static void dsi_enter_reset () +{ + /* Enable clock lane */ + R_MIPI_DSI->TXSETR_b.CLEN = 1U; + + /* Enter the DSI Host software reset state */ + R_MIPI_DSI->RSTCR_b.SWRST = 1; + + /* Wait for reset process to start - Polling RSTSR is okay since it's not updated in interrupt.*/ + FSP_HARDWARE_REGISTER_WAIT((R_MIPI_DSI->RSTSR & MIPI_DSI_RSRST_RESET_BITS), MIPI_DSI_RSRST_RESET_BITS); +} + +/*******************************************************************************************************************//** + * Initialize timing registers from configuration data + * - Perform sequence step 3 from "Software Reset" in the MIPI DSI section of the relevant hardware manual. + * + * @param[in] p_cfg Pointer to MIPI DSI configuration structure + **********************************************************************************************************************/ +static void dsi_init_timing (mipi_dsi_cfg_t const * const p_cfg) +{ + /* Enable clock and data lanes and set number of lanes to use */ + R_MIPI_DSI->TXSETR = R_MIPI_DSI_TXSETR_DLEN_Msk | R_MIPI_DSI_TXSETR_CLEN_Msk | (p_cfg->num_lanes - 1); + + /* Set ULPS wakeup period */ + R_MIPI_DSI->ULPSSETR_b.WKUP = p_cfg->ulps_wakeup_period; + + /* Set data scrambling and/or EoTp transmission */ +#define MIPI_DSI_DSISETR_VCCRCEN_Msk (R_MIPI_DSI_DSISETR_VC0CRCEN_Msk | \ + R_MIPI_DSI_DSISETR_VC1CRCEN_Msk | \ + R_MIPI_DSI_DSISETR_VC2CRCEN_Msk | \ + R_MIPI_DSI_DSISETR_VC3CRCEN_Msk) + R_MIPI_DSI->DSISETR = + ((p_cfg->max_return_packet_size << R_MIPI_DSI_DSISETR_MRPSZ_Pos) & R_MIPI_DSI_DSISETR_MRPSZ_Msk) | + (((uint32_t) p_cfg->ecc_enable << R_MIPI_DSI_DSISETR_ECCEN_Pos) & R_MIPI_DSI_DSISETR_ECCEN_Msk) | + (((uint32_t) p_cfg->crc_check_mask << R_MIPI_DSI_DSISETR_VC0CRCEN_Pos) & MIPI_DSI_DSISETR_VCCRCEN_Msk) | + (((uint32_t) p_cfg->scramble_enable << R_MIPI_DSI_DSISETR_SCREN_Pos) & R_MIPI_DSI_DSISETR_SCREN_Msk) | + (((uint32_t) p_cfg->tearing_detect << R_MIPI_DSI_DSISETR_EXTEMD_Pos) & R_MIPI_DSI_DSISETR_EXTEMD_Msk) | + (((uint32_t) p_cfg->eotp_enable << R_MIPI_DSI_DSISETR_EOTPEN_Pos) & R_MIPI_DSI_DSISETR_EOTPEN_Msk); + + /* Set LP lane transition timing */ + R_MIPI_DSI->CLSTPTSETR = + ((p_cfg->p_timing->clock_stop_time << R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Pos) & + R_MIPI_DSI_CLSTPTSETR_CLKSTPT_Msk) | + ((p_cfg->p_timing->clock_beforehand_time << R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Pos) & + R_MIPI_DSI_CLSTPTSETR_CLKBFHT_Msk) | + ((p_cfg->p_timing->clock_keep_time << R_MIPI_DSI_CLSTPTSETR_CLKKPT_Pos) & + R_MIPI_DSI_CLSTPTSETR_CLKKPT_Msk); + R_MIPI_DSI->LPTRNSTSETR = p_cfg->p_timing->go_lp_and_back & R_MIPI_DSI_LPTRNSTSETR_GOLPBKT_Msk; + + /* Set timeout values */ + R_MIPI_DSI->PRESPTOBTASETR = p_cfg->bta_timeout; + R_MIPI_DSI->PRESPTOLPSETR = p_cfg->lprw_timeout; + R_MIPI_DSI->PRESPTOHSSETR = p_cfg->hsrw_timeout; + R_MIPI_DSI->HSTXTOSETR = p_cfg->hs_tx_timeout; + R_MIPI_DSI->LRXHTOSETR = p_cfg->lp_rx_timeout; + R_MIPI_DSI->TATOSETR = p_cfg->turnaround_timeout; +} + +/*******************************************************************************************************************//** + * Exit Reset + * Perform sequence steps 4 to 8 from "Software Reset" in the MIPI DSI section of the relevant hardware manual. + * + * NOTE: Calling this function is prohibited without first calling dsi_enter_reset(), which sets RSTCR.SWRST to 1 + * + * @param[in] p_cfg Pointer to MIPI DSI configuration structure + **********************************************************************************************************************/ +static void dsi_exit_reset (mipi_dsi_cfg_t const * const p_cfg) +{ + /* Transition data lanes to stop state */ + R_MIPI_DSI->RSTCR_b.FTXSTP = 1U; + + /* Wait for data lanes transition to stop state */ + FSP_HARDWARE_REGISTER_WAIT((R_MIPI_DSI->RSTSR & + (R_MIPI_DSI_RSTSR_DL0DIR_Msk | R_MIPI_DSI_RSTSR_DL0STP_Msk | + R_MIPI_DSI_RSTSR_DL1STP_Msk)), + (((p_cfg->num_lanes * 2U) - 1U) << R_MIPI_DSI_RSTSR_DL0STP_Pos)); + + /* Clear the Force Tx Stop and Software Reset bits */ + R_MIPI_DSI->RSTCR_b.FTXSTP = 0U; + R_MIPI_DSI->RSTCR_b.SWRST = 0U; + + /* Wait for software reset to complete */ + FSP_HARDWARE_REGISTER_WAIT((R_MIPI_DSI->RSTSR & MIPI_DSI_RSRST_RESET_BITS), 0); +} + +/*******************************************************************************************************************//** + * Initialize High Speed Clock + * Perform sequence steps from "Start of HS Clock" in the MIPI DSI section of the relevant hardware manual. + * + * @param[in] p_ctrl Pointer to MIPI DSI instance control block + **********************************************************************************************************************/ +static void dsi_hs_clock_start (mipi_dsi_instance_ctrl_t * p_ctrl) +{ + mipi_dsi_cfg_t const * p_cfg = p_ctrl->p_cfg; + + /* Enable clock lane */ + R_MIPI_DSI->TXSETR_b.CLEN = 1U; + g_clock_state = MIPI_DSI_CLOCK_STATE_STARTING; + + /* Enable HS clock and set running mode */ + R_MIPI_DSI->HSCLKSETR = R_MIPI_DSI_HSCLKSETR_HSCLST_Msk | + (p_cfg->continuous_clock ? R_MIPI_DSI_HSCLKSETR_HSCLMD_Msk : 0U); + + while ((R_MIPI_DSI->PLSR_b.CLLP2HS != p_cfg->continuous_clock) && + (g_clock_state != MIPI_DSI_CLOCK_STATE_STARTED)) + { + /* Wait for HS clock notification bit set to 1. (only in the continuous clock mode) + * NOTE: PLSR may be modified in ISR */ + } + + g_clock_state = MIPI_DSI_CLOCK_STATE_STARTED; +} + +/*********************************************************************************************************************** + * De-initialize High Speed Clock + * Perform sequence steps from "Stop of HS Clock" in the MIPI DSI section of the relevant hardware manual. + * + * @param[in] p_ctrl Pointer to MIPI DSI instance control block + **********************************************************************************************************************/ +static void dsi_hs_clock_stop (mipi_dsi_instance_ctrl_t * p_ctrl) +{ + mipi_dsi_cfg_t const * p_cfg = p_ctrl->p_cfg; + + R_MIPI_DSI->HSCLKSETR_b.HSCLST = 0; + g_clock_state = MIPI_DSI_CLOCK_STATE_STOPPING; + + while ((R_MIPI_DSI->PLSR_b.CLHS2LP != p_cfg->continuous_clock) && (g_clock_state != MIPI_DSI_CLOCK_STATE_IDLE)) + { + /* Wait for clock lane transition LP state. + * NOTE: PLSR may be modified in ISR */ + } + + g_clock_state = MIPI_DSI_CLOCK_STATE_IDLE; +} + +/*********************************************************************************************************************** + * Initialize Video Output Registers + * Perform sequence steps 1 and 2 from "Start of Video Mode Operation" in the MIPI DSI section of the relevant + * hardware manual. + * + * @param[in] p_cfg Pointer to MIPI DSI configuration structure + **********************************************************************************************************************/ +static void dsi_init_video (mipi_dsi_cfg_t const * p_cfg) +{ + R_MIPI_DSI->VMPPSETR = + (((uint32_t) p_cfg->sync_pulse << R_MIPI_DSI_VMPPSETR_TXESYNC_Pos) & R_MIPI_DSI_VMPPSETR_TXESYNC_Msk) | + (((uint32_t) p_cfg->data_type << R_MIPI_DSI_VMPPSETR_DT_Pos) & R_MIPI_DSI_VMPPSETR_DT_Msk) | + (((uint32_t) p_cfg->virtual_channel_id << R_MIPI_DSI_VMPPSETR_VC_Pos) & + R_MIPI_DSI_VMPPSETR_VC_Msk); + R_MIPI_DSI->VMVSSETR = + ((p_cfg->vertical_sync_lines << R_MIPI_DSI_VMVSSETR_VSA_Pos) & R_MIPI_DSI_VMVSSETR_VSA_Msk) | + (((uint32_t) p_cfg->vertical_sync_polarity << R_MIPI_DSI_VMVSSETR_VSPOL_Pos) & + R_MIPI_DSI_VMVSSETR_VSPOL_Msk) | + ((p_cfg->vertical_active_lines << R_MIPI_DSI_VMVSSETR_VACT_Pos) & + R_MIPI_DSI_VMVSSETR_VACT_Msk); + R_MIPI_DSI->VMVPSETR = + ((p_cfg->vertical_back_porch << R_MIPI_DSI_VMVPSETR_VBP_Pos) & R_MIPI_DSI_VMVPSETR_VBP_Msk) | + ((p_cfg->vertical_front_porch << R_MIPI_DSI_VMVPSETR_VFP_Pos) & + R_MIPI_DSI_VMVPSETR_VFP_Msk); + R_MIPI_DSI->VMHSSETR = + ((p_cfg->horizontal_sync_lines << R_MIPI_DSI_VMHSSETR_HSA_Pos) & R_MIPI_DSI_VMHSSETR_HSA_Msk) | + (((uint32_t) p_cfg->horizontal_sync_polarity << R_MIPI_DSI_VMHSSETR_HSPOL_Pos) & + R_MIPI_DSI_VMHSSETR_HSPOL_Msk) | + ((p_cfg->horizontal_active_lines << R_MIPI_DSI_VMHSSETR_HACT_Pos) & + R_MIPI_DSI_VMHSSETR_HACT_Msk); + R_MIPI_DSI->VMHPSETR = + ((p_cfg->horizontal_back_porch << R_MIPI_DSI_VMHPSETR_HBP_Pos) & R_MIPI_DSI_VMHPSETR_HBP_Msk) | + ((p_cfg->horizontal_front_porch << R_MIPI_DSI_VMHPSETR_HFP_Pos) & + R_MIPI_DSI_VMHPSETR_HFP_Msk); + R_MIPI_DSI->VMSET1R = + ((p_cfg->video_mode_delay << R_MIPI_DSI_VMSET1R_DLY_Pos) & R_MIPI_DSI_VMSET1R_DLY_Msk); +} + +/*********************************************************************************************************************** + * Enable the specified ISR and add the control structure to the ISR context lookup table. + * + * @param[in] irq_cfg Pointer to interrupt configuration structure + * @param[in] p_ctrl Pointer to MIPI DSI instance control block + **********************************************************************************************************************/ +static void dsi_isr_enable (mipi_dsi_irq_cfg_t const * irq_cfg, mipi_dsi_instance_ctrl_t * p_ctrl) +{ + R_BSP_IrqCfgEnable(irq_cfg->irq, irq_cfg->ipl, p_ctrl); +} + +/*********************************************************************************************************************** + * Disable the specified ISR + * + * @param[in] irq_cfg Pointer to interrupt configuration structure + **********************************************************************************************************************/ +static void dsi_isr_disable (mipi_dsi_irq_cfg_t const * irq_cfg) +{ + R_BSP_IrqDisable(irq_cfg->irq); + R_FSP_IsrContextSet(irq_cfg->irq, NULL); +} + +/*********************************************************************************************************************** + * Interrupt Service Routines + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Sequence 0 ISR + * - Process LP sequence command events and forward them to the user callback + **********************************************************************************************************************/ +void mipi_dsi_seq0_isr (void) { + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + /* Clear sequence channel 0 status register bits */ + uint32_t sqch0sr_bits = R_MIPI_DSI->SQCH0SR; + R_MIPI_DSI->SQCH0SCR = sqch0sr_bits; // SIZEERR is reserved for SQCH0SCR and should be read and written as zero + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + mipi_dsi_callback_args_t args; + args.event = MIPI_DSI_EVENT_SEQUENCE_0; + args.tx_status = (mipi_dsi_sequence_status_t) sqch0sr_bits; + args.p_context = p_ctrl->p_context; + dsi_call_callback(p_ctrl, &args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*********************************************************************************************************************** + * Sequence 1 ISR + * - Process HS sequence command events and forward them to the user callback + **********************************************************************************************************************/ +void mipi_dsi_seq1_isr (void) { + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + /* Clear sequence channel 1 status register bits */ + uint32_t sqch1sr_bits = R_MIPI_DSI->SQCH1SR; + R_MIPI_DSI->SQCH1SCR = sqch1sr_bits; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + mipi_dsi_callback_args_t args; + args.event = MIPI_DSI_EVENT_SEQUENCE_1; + args.tx_status = (mipi_dsi_sequence_status_t) sqch1sr_bits; + args.p_context = p_ctrl->p_context; + dsi_call_callback(p_ctrl, &args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*********************************************************************************************************************** + * Video Input ISR + * - Process DSI Video Input Events and forward them to the user callback + **********************************************************************************************************************/ +void mipi_dsi_vin1_isr (void) { + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + /* Clear video mode status register bits */ + uint32_t vmsr_bits = R_MIPI_DSI->VMSR; + R_MIPI_DSI->VMSCR = vmsr_bits; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + /* Update internal state */ + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + if (vmsr_bits & R_MIPI_DSI_VMSR_VIRDY_Msk) + { + g_video_started = true; + } + else if (vmsr_bits & R_MIPI_DSI_VMSR_STOP_Msk) + { + g_video_started = false; + } + else + { + // Nothing + } + + /* Pass data to user */ + mipi_dsi_callback_args_t args; + args.event = MIPI_DSI_EVENT_VIDEO; + args.video_status = (mipi_dsi_video_status_t) vmsr_bits; + args.p_context = p_ctrl->p_context; + dsi_call_callback(p_ctrl, &args); + + /* Perform reset according to "Software Reset" in the MIPI DSI section of the relevant hardware manual */ + if (vmsr_bits & (R_MIPI_DSI_VMSR_VBUFUDF_Msk | R_MIPI_DSI_VMSR_VBUFOVF_Msk)) + { + dsi_enter_reset(); + dsi_exit_reset(p_ctrl->p_cfg); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*********************************************************************************************************************** + * Receive ISR + * - Process Receive Events and forward them to the user callback + **********************************************************************************************************************/ +void mipi_dsi_rcv_isr (void) { + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + /* Clear receive status register bits */ + uint32_t rxsr_bits = R_MIPI_DSI->RXSR; + R_MIPI_DSI->RXSCR = rxsr_bits; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + mipi_dsi_callback_args_t args; + args.event = MIPI_DSI_EVENT_RECEIVE; + args.rx_status = (mipi_dsi_receive_status_t) rxsr_bits; + args.p_result = (mipi_dsi_receive_result_t *) &R_MIPI_DSI->RXRSS0R; + args.p_context = p_ctrl->p_context; + dsi_call_callback(p_ctrl, &args); + + R_MIPI_DSI->RXRINFOOWSCR = R_MIPI_DSI_RXRINFOOWSCR_SL0OW_Msk; // Clear slot 0 after reading + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*********************************************************************************************************************** + * Fatal Error ISR + * - Process Fatal Error Events and forward them to the user callback + **********************************************************************************************************************/ +void mipi_dsi_ferr_isr (void) { + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + /* Clear receive status register bits */ + uint32_t ferrsr_bits = R_MIPI_DSI->FERRSR; + R_MIPI_DSI->FERRSCR = ferrsr_bits; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + mipi_dsi_callback_args_t args; + args.event = MIPI_DSI_EVENT_FATAL; + args.fatal_status = (mipi_dsi_fatal_status_t) ferrsr_bits; + args.p_context = p_ctrl->p_context; + dsi_call_callback(p_ctrl, &args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*********************************************************************************************************************** + * PHY-Protocol Interface ISR + * - Process Phy-Protocol Events and forward them to the user callback + **********************************************************************************************************************/ +void mipi_dsi_ppi_isr (void) { + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + /* Clear PLSR */ + uint32_t plsr_bits = R_MIPI_DSI->PLSR; + R_MIPI_DSI->PLSCR = plsr_bits; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + /* Update internal state */ + mipi_dsi_instance_ctrl_t * p_ctrl = (mipi_dsi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + if ((g_clock_state == MIPI_DSI_CLOCK_STATE_STARTING) && + (plsr_bits & R_MIPI_DSI_PLSR_CLLP2HS_Msk)) + { + g_clock_state = MIPI_DSI_CLOCK_STATE_STARTED; + } + else if ((g_clock_state == MIPI_DSI_CLOCK_STATE_STOPPING) && + (plsr_bits & R_MIPI_DSI_PLSR_CLHS2LP_Msk)) + { + g_clock_state = MIPI_DSI_CLOCK_STATE_IDLE; + } + else + { + // Nothing + } + + /* Pass data to user */ + mipi_dsi_callback_args_t args; + args.event = MIPI_DSI_EVENT_PHY; + args.phy_status = (mipi_dsi_phy_status_t) plsr_bits; + args.p_context = p_ctrl->p_context; + dsi_call_callback(p_ctrl, &args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_phy/r_mipi_phy.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_phy/r_mipi_phy.c new file mode 100644 index 0000000000..7484f9888e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mipi_phy/r_mipi_phy.c @@ -0,0 +1,138 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_mipi_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define MIPI_PHY_OPEN (0x4D504950) + +#define MIPI_DSI_PRV_1MHZ (1000000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +const mipi_phy_api_t g_mipi_phy = +{ + .open = r_mipi_phy_open, + .close = r_mipi_phy_close, +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup MIPI_PHY + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Initialize the MIPI PHY peripheral according to "D-PHY Start-up Procedure" in the MIPI PHY section of the relevant + * hardware manual + * + * @retval FSP_SUCCESS The channel was successfully opened. + * @retval FSP_ERR_ASSERTION One or both of the parameters was NULL. + * @retval FSP_ERR_ALREADY_OPEN The instance is already opened. + * @retval FSP_ERR_INVALID_MODE Power control mode must be high-speed-mode. + **********************************************************************************************************************/ +fsp_err_t r_mipi_phy_open (mipi_phy_ctrl_t * const p_api_ctrl, mipi_phy_cfg_t const * const p_cfg) +{ + mipi_phy_ctrl_t * p_ctrl = p_api_ctrl; + + /* Set DSI/CSI Mode setting */ +#if BSP_FEATURE_MIPI_CSI_IS_AVAILABLE + R_MIPI_PHY->DPHYMDC_b.MASTEREN = p_cfg->dsi_mode; +#endif + + /* Set DPHYREFCR to match PCLKA */ + uint32_t pclka_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKA); + R_MIPI_PHY->DPHYREFCR_b.RFREQ = (uint8_t) ((pclka_hz / MIPI_DSI_PRV_1MHZ) - 1); + + /* Start D-PHY LDO and wait for startup */ + R_MIPI_PHY->DPHYPWRCR_b.PWRSEN = 1; + FSP_HARDWARE_REGISTER_WAIT((R_MIPI_PHY->DPHYSFR & R_MIPI_PHY_DPHYSFR_PWRSF_Msk), R_MIPI_PHY_DPHYSFR_PWRSF_Msk); + + /* Do not enable PLL for MIPI CSI */ +#if BSP_FEATURE_MIPI_CSI_IS_AVAILABLE + if (p_cfg->dsi_mode) +#endif + { + /* Configure D-PHY PLL and LP frequency divider */ + R_MIPI_PHY->DPHYPLFCR = p_cfg->pll_settings.raw; + R_MIPI_PHY->DPHYESCCR_b.ESCDIV = p_cfg->lp_divisor; + + /* Start D-PHY PLL and wait for startup */ + R_MIPI_PHY->DPHYPLOCR_b.PLLSTP = 0; + FSP_HARDWARE_REGISTER_WAIT((R_MIPI_PHY->DPHYSFR & R_MIPI_PHY_DPHYSFR_PLLSF_Msk), R_MIPI_PHY_DPHYSFR_PLLSF_Msk); + } + + /* Set D-PHY timing parameters */ + mipi_phy_timing_t const * p_timing = p_cfg->p_timing; + R_MIPI_PHY->DPHYTIM1 = p_timing->t_init; + R_MIPI_PHY->DPHYTIM2 = p_timing->dphytim2; + R_MIPI_PHY->DPHYTIM3 = p_timing->dphytim3; + R_MIPI_PHY->DPHYTIM4 = p_timing->dphytim4; + R_MIPI_PHY->DPHYTIM5 = p_timing->dphytim5; + R_MIPI_PHY->DPHYTIM6 = p_timing->t_lp_exit; + + /* Enable D-PHY */ + R_MIPI_PHY->DPHYOCR_b.DPHYEN = 1U; + + /* Keep track of p_cfg struct */ + p_ctrl->p_cfg = p_cfg; + + /* Mark control block as opened */ + p_ctrl->open = MIPI_PHY_OPEN; + + return FSP_SUCCESS; +} + +/********************************************************************************************************************** + * Stop filter operations and close the channel instance. + * + * NOTE: D_PHY must be stopped and LDO disabled before entering standby mode. See "D-PHY Stop Procedure" in the MIPI PHY + * section of the relevant hardware manual. + * + * @retval FSP_SUCCESS The channel is successfully closed. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + **********************************************************************************************************************/ +fsp_err_t r_mipi_phy_close (mipi_phy_ctrl_t * const p_api_ctrl) +{ + mipi_phy_ctrl_t * p_ctrl = p_api_ctrl; + + /* Disable D-PHY */ + R_MIPI_PHY->DPHYOCR_b.DPHYEN = 0; + + /* Disable D-PHY PLL */ + R_MIPI_PHY->DPHYPLOCR_b.PLLSTP = 1; + + /* Disable MIPI LDO */ + R_MIPI_PHY->DPHYPWRCR_b.PWRSEN = 0; + + /* Set control block to closed */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup MIPI_PHY) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mram/r_mram.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mram/r_mram.c new file mode 100644 index 0000000000..0bbd6d2c62 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_mram/r_mram.c @@ -0,0 +1,1650 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_mram.h" + +/* Configuration for this package. */ +#include "r_mram_cfg.h" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * mram_prv_ns_callback)(flash_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile mram_prv_ns_callback)(flash_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "MRAM" in ASCII, used to avoid multiple open. */ +#define MRAM_PRV_OPEN (0X4D52414DU) + +#define MRAM_PRV_CMD_BASE (0x40120000) + +/** R_MRMS Commands */ +#define MRAM_PRV_MACI_CMD_STATUS_CLEAR (0x50U) +#define MRAM_PRV_MACI_CMD_FORCED_STOP (0xB3U) +#define MRAM_PRV_MACI_CMD_CONFIG_SET_1 (0x40U) +#define MRAM_PRV_MACI_CMD_CONFIG_SET_2 (0x08U) +#define MRAM_PRV_MACI_CMD_INCREMENT_COUNTER (0x35U) +#define MRAM_PRV_MACI_CMD_READ_COUNTER (0x39U) +#define MRAM_PRV_MACI_CMD_FINAL (0xD0U) +#define MRAM_PRV_MACI_CONFIG_SET_STARTUP (0x02C9F070U) + +#ifndef MRAM_PRV_OFS_ARCCS_ADDR + #define MRAM_PRV_OFS_ARCCS_ADDR (0x02E17932) +#endif +#ifndef MRAM_PRV_OFS_ARC_SEC_ADDR + #define MRAM_PRV_OFS_ARC_SEC_ADDR (0x02F27E00) +#endif +#ifndef MRAM_PRV_OFS_ARC_NSEC_ADDR + #define MRAM_PRV_OFS_ARC_NSEC_ADDR (0x02F27E08) +#endif +#define MRAM_PRV_OFS_ARCCS_ARCNS_Msk (0x3) + +/* Zero based offset into g_configuration_area_data[] for BTFLG */ +#define MRAM_PRV_CONFIG_SET_BTFLG_OFFSET (3U) + +/* 8 words need to be written for code MRAM */ +#define MRAM_PRV_CONFIG_SET_ACCESS_WORD_CNT (8U) + +#define MRAM_PRV_MSUACR_KEY (0x6600U) + +/** Register masks */ +#define MRAM_PRV_MENTRYR_PE_MODE (0x0080U) // Bits indicating that MRAM is in P/E mode. +#define MRAM_PRV_MENTRYR_TRANSITION_TO_PE (0xAA80U) // Key Code to transition to P/E mode. +#define MRAM_PRV_MENTRYR_PE_MODE_BITS (0x0080U) +#define MRAM_PRV_MENTRYR_READ_MODE (0xAA00U) + +#define MRAM_PRV_FREQUENCY_IN_HZ (1000000U) + +#define MRAM_PRV_OFS_SAS_MASK (0x1FFFU) + +#define MRAM_PRV_MAX_MRAM_WRITE_US (100) +#define MRAM_PRV_MAX_ARC_INCREMENT_US (2000) +#define MRAM_PRV_MAX_ARC_READ_US (1) +#define MRAM_PRV_MAX_CONFIGURATION_SET_US (10000) +#define MRAM_PRV_MAX_MACI_COMMAND_US (4) + +#define MRAM_PRV_ARCNS_SINGLE (1) // ARCNS setting for single ARC_NSEC counter +#define MRAM_PRV_ARCNS_MULTIPLE (0) // ARCNS setting for multiple ARC_NSEC counters +#define MRAM_PRV_ARC_MCNTSELR_OEMBL (2) +#define MRAM_PRV_ARC_MCNTSELR_SEC (1) +#define MRAM_PRV_ARC_MCNTSELR_NSEC_0 (4) +#define MRAM_PRV_64_BITS (64U) + +#define MRAM_PRV_MRCPC0_KEY (0x8600) +#define MRAM_PRV_MRCPC1_KEY (0x6800) +#define MRAM_PRV_MRCFLR_FLUSH (0xC301) +#define MRAM_PRV_OFS_SAS_ADDRESS (0x02C9F074) +#define MRAM_PRV_OFS_SAS_BTSIZE_MASK (0x60000000) + +/* The number of CPU cycles per each timeout loop. */ +#ifndef MRAM_PRV_MINIMUM_CYCLES_PER_TIMEOUT_LOOP + #define MRAM_PRV_MINIMUM_CYCLES_PER_TIMEOUT_LOOP (1U) +#endif + +/* =========================================================================================================================== */ +/* ================ MRAM_PRV_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (MRAM_PRV_CMD) + */ + +#define MRAM_PRV_CMD ((R_MRAM_CMD_Type *) MRAM_PRV_CMD_BASE) + +typedef struct /*!< (@ 0x407E0000) MRAM_PRV_CMD Structure */ +{ + union + { + __IOM uint16_t MACI_CMD16; /*!< (@ 0x00000000) MACI Command Issuing Area (halfword access) */ + __IOM uint8_t MACI_CMD8; /*!< (@ 0x00000000) MACI Command Issuing Area (byte access) */ + }; +} R_MRAM_CMD_Type; + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +static uint16_t g_configuration_area_data[MRAM_PRV_CONFIG_SET_ACCESS_WORD_CNT] = {UINT16_MAX}; + +static const flash_block_info_t g_code_mram_macro_info[] = +{ + { + .block_section_st_addr = BSP_FEATURE_FLASH_CODE_FLASH_START, + .block_section_end_addr = BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES, + .block_size = BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES, + .block_size_write = 1 + } +}; + +static const flash_regions_t g_mram_code_region = +{ + .num_regions = 1, + .p_block_array = g_code_mram_macro_info +}; + +static const flash_regions_t g_mram_data_region = +{ + .num_regions = 0, + .p_block_array = NULL +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/* Internal functions. */ +static void mram_init(mram_instance_ctrl_t * p_ctrl); + +static fsp_err_t mram_transition_to_read_mode(mram_instance_ctrl_t * p_ctrl); + +static fsp_err_t mram_reset(mram_instance_ctrl_t * p_ctrl); + +static fsp_err_t mram_stop(mram_instance_ctrl_t * p_ctrl); + +static fsp_err_t mram_erase_blocks(uint32_t address, uint32_t num_blocks) PLACE_IN_RAM_SECTION; + +static fsp_err_t mram_write_data(uint32_t src_address, uint32_t mram_address, uint32_t num_bytes) PLACE_IN_RAM_SECTION; + +static void mram_program_control(uint32_t address, bool enable); + +static fsp_err_t mram_check_errors(mram_instance_ctrl_t * const p_ctrl, fsp_err_t previous_error); + +static fsp_err_t mram_configuration_area_write(mram_instance_ctrl_t * p_ctrl, + uint32_t mram_address, + uint16_t * src_address); + +static void mram_enter_pe_mode(void); + +static fsp_err_t mram_set_startup_area_boot(mram_instance_ctrl_t * p_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary); + +#if (MRAM_CFG_PARAM_CHECKING_ENABLE == 1) + +static fsp_err_t r_mram_common_parameter_checking(mram_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_mram_write_erase_parameter_checking(mram_instance_ctrl_t * const p_ctrl, + uint32_t mram_address, + uint32_t const num_bytes, + fsp_err_t size_err); + +#endif + +static uint8_t mram_counter_to_mcntselr_convert(flash_arc_t counter); +static fsp_err_t mram_arc_read(mram_instance_ctrl_t * const p_ctrl, uint8_t mcntselr, uint32_t * const p_count); +static fsp_err_t mram_arc_cmd_execute(mram_instance_ctrl_t * const p_ctrl, + uint8_t mcntselr, + uint8_t cmd, + volatile uint32_t wait_count); + +#if (MRAM_CFG_PARAM_CHECKING_ENABLE == 1) +static fsp_err_t r_mram_arc_common_parameter_checking(mram_instance_ctrl_t * const p_ctrl, + flash_arc_t counter, + uint8_t mcntselr); + +#endif + +void mram_err_isr(void); + +static void mram_call_callback(mram_instance_ctrl_t * p_ctrl, flash_event_t event, uint32_t address); + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +const flash_api_t g_flash_on_mram = +{ + .open = R_MRAM_Open, + .close = R_MRAM_Close, + .write = R_MRAM_Write, + .erase = R_MRAM_Erase, + .blankCheck = R_MRAM_BlankCheck, + .statusGet = R_MRAM_StatusGet, + .infoGet = R_MRAM_InfoGet, + .accessWindowSet = R_MRAM_AccessWindowSet, + .accessWindowClear = R_MRAM_AccessWindowClear, + .idCodeSet = R_MRAM_IdCodeSet, + .reset = R_MRAM_Reset, + .startupAreaSelect = R_MRAM_StartUpAreaSelect, + .updateFlashClockFreq = R_MRAM_UpdateFlashClockFreq, + .bankSwap = R_MRAM_BankSwap, + .callbackSet = R_MRAM_CallbackSet, + .antiRollbackCounterIncrement = R_MRAM_AntiRollbackCounterIncrement, + .antiRollbackCounterRefresh = R_MRAM_AntiRollbackCounterRefresh, + .antiRollbackCounterRead = R_MRAM_AntiRollbackCounterRead, + .userLockableAreaWrite = R_MRAM_UserLockableAreaWrite, +}; + +/*******************************************************************************************************************//** + * @addtogroup MRAM + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the MRAM peripheral. Implements @ref flash_api_t::open. + * + * The Open function initializes the MRAM. + * + * Example: + * @snippet r_mram_example.c R_MRAM_Open + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ALREADY_OPEN The MRAM control block is already open. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_cfg. + * @retval FSP_ERR_IRQ_BSP_DISABLED Caller is requesting BGO but the MRAM interrupts are not supported. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_Open (flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg) +{ + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (MRAM_CFG_PARAM_CHECKING_ENABLE) + + /* If null pointers return error. */ + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + + /* If open return error. */ + FSP_ERROR_RETURN((MRAM_PRV_OPEN != p_ctrl->opened), FSP_ERR_ALREADY_OPEN); + + FSP_ERROR_RETURN(false == p_cfg->data_flash_bgo, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ERROR_RETURN(FSP_INVALID_VECTOR == p_cfg->irq, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ERROR_RETURN(BSP_IRQ_DISABLED == p_cfg->ipl, FSP_ERR_IRQ_BSP_DISABLED); +#endif + + if (0 <= p_cfg->err_irq) + { +#if (MRAM_CFG_PARAM_CHECKING_ENABLE) + FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->err_ipl, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ASSERT(p_cfg->p_callback); +#endif + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + + /* Enable MRAM Error interrupts. */ + R_MRMS->MRCRAEINT = 0x3; + R_BSP_IrqCfgEnable(p_cfg->err_irq, p_cfg->err_ipl, p_ctrl); + } + else + { +#if (MRAM_CFG_PARAM_CHECKING_ENABLE) + FSP_ERROR_RETURN(FSP_INVALID_VECTOR == p_cfg->err_irq, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ERROR_RETURN(BSP_IRQ_DISABLED == p_cfg->err_ipl, FSP_ERR_IRQ_BSP_DISABLED); + FSP_ERROR_RETURN(NULL == p_cfg->p_callback, FSP_ERR_IRQ_BSP_DISABLED); +#endif + } + + /* Calculate timeout values */ + mram_init(p_ctrl); + + p_ctrl->p_cfg = p_cfg; + + /* If successful mark the control block as open. */ + p_ctrl->opened = MRAM_PRV_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Writes to the specified MRAM memory area. Implements @ref flash_api_t::write. + * + * Example: + * @snippet r_mram_example.c R_MRAM_Write + * + * @retval FSP_SUCCESS Operation successful. + * @retval FSP_ERR_IN_USE The MRAM peripheral is busy with a prior on-going transaction. + * @retval FSP_ERR_NOT_OPEN The MRAM API is not Open. + * @retval FSP_ERR_CMD_LOCKED MRAM Application Command Interface is in locked state + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. This may + * be returned if the requested MRAM area is not blank. + * @retval FSP_ERR_TIMEOUT Timed out waiting for write operation to complete. + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was invalid + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_Write (flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t mram_address, + uint32_t const num_bytes) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + fsp_err_t err = FSP_SUCCESS; +#if (MRAM_CFG_PARAM_CHECKING_ENABLE == 1) + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + + /* Verify write parameters. If failure return error. */ + err = r_mram_write_erase_parameter_checking(p_ctrl, + mram_address & ~BSP_FEATURE_TZ_NS_OFFSET, + num_bytes, + FSP_ERR_INVALID_SIZE); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + FSP_ERROR_RETURN((0 == R_MRMS->MRCPC0) && (0 == R_MRMS->MRCPC1), FSP_ERR_IN_USE); +#endif + + err = mram_write_data(src_address, mram_address, num_bytes); + + return err; +} + +/*******************************************************************************************************************//** + * Erases the specified MRAM blocks. Implements @ref flash_api_t::erase by the block_erase_address. + * + * Example: + * @snippet r_mram_example.c R_MRAM_Erase + * + * @retval FSP_SUCCESS Successful open. + * @retval FSP_ERR_INVALID_BLOCKS Invalid number of blocks specified + * @retval FSP_ERR_INVALID_ADDRESS Invalid address specified. + * @retval FSP_ERR_IN_USE Other MRAM operation in progress, or API not initialized + * @retval FSP_ERR_CMD_LOCKED MRAM Application Command Interface is in locked state + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN The MRAM API is not Open. + * @retval FSP_ERR_ERASE_FAILED Status is indicating a Erase error. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the MACI to become ready. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_Erase (flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + fsp_err_t err = FSP_SUCCESS; +#if (MRAM_CFG_PARAM_CHECKING_ENABLE == 1) + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + + /* Verify parameters. */ + err = r_mram_write_erase_parameter_checking(p_ctrl, + address & ~BSP_FEATURE_TZ_NS_OFFSET, + num_blocks * BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES, + FSP_ERR_INVALID_BLOCKS); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + FSP_ERROR_RETURN(0 == address % BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES, FSP_ERR_INVALID_ADDRESS); + + FSP_ERROR_RETURN((0 == R_MRMS->MRCPC0) && (0 == R_MRMS->MRCPC1), FSP_ERR_IN_USE); +#endif + + err = mram_erase_blocks(address, num_blocks); + + return err; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::blankCheck. + * + * @retval FSP_ERR_UNSUPPORTED Blank Check is not supported on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_BlankCheck (flash_ctrl_t * const p_api_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * p_blank_check_result) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(address); + FSP_PARAMETER_NOT_USED(num_bytes); + FSP_PARAMETER_NOT_USED(p_blank_check_result); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Query the MRAM peripheral for its status. Implements @ref flash_api_t::statusGet. + * + * @retval FSP_SUCCESS MRAM peripheral is ready to use. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_NOT_OPEN The MRAM API is not Open. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_StatusGet (flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status) +{ +#if (MRAM_CFG_PARAM_CHECKING_ENABLE == 1) + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + + /* If null pointer return error. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN(!(MRAM_PRV_OPEN != p_ctrl->opened), FSP_ERR_NOT_OPEN); +#else + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* If the MRAM is currently in program/erase mode notify the caller that the MRAM is busy. */ + if (((R_MRMS->MENTRYR & MRAM_PRV_MENTRYR_PE_MODE_BITS) == 0x0000U) && (0 == R_MRMS->MRCPC0) && + (0 == R_MRMS->MRCPC1)) + { + *p_status = FLASH_STATUS_IDLE; + } + else + { + *p_status = FLASH_STATUS_BUSY; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::idCodeSet. + * + * @retval FSP_ERR_UNSUPPORTED ID Code is not supported on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_IdCodeSet (flash_ctrl_t * const p_api_ctrl, uint8_t const * const p_id_code, flash_id_code_mode_t mode) +{ + /* Eliminate warning. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_id_code); + FSP_PARAMETER_NOT_USED(mode); + + /* Return status. */ + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::accessWindowSet. + * + * @retval FSP_ERR_UNSUPPORTED Access window is not supported on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_AccessWindowSet (flash_ctrl_t * const p_api_ctrl, uint32_t const start_addr, uint32_t const end_addr) +{ + /* Eliminate warning. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(start_addr); + FSP_PARAMETER_NOT_USED(end_addr); + + /* Return status. */ + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::accessWindowClear. + * + * @retval FSP_ERR_UNSUPPORTED Access window is not supported on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_AccessWindowClear (flash_ctrl_t * const p_api_ctrl) +{ + /* Eliminate warning. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Reset the MRAM peripheral. Implements @ref flash_api_t::reset. + * + * No attempt is made to check if the MRAM is busy before executing the reset since the assumption is that a reset will + * terminate any existing operation. + * + * @retval FSP_SUCCESS MRAM circuit successfully reset. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the MACI to become ready. + * @retval FSP_ERR_CMD_LOCKED MRAM Application Command Interface is in locked state + **********************************************************************************************************************/ +fsp_err_t R_MRAM_Reset (flash_ctrl_t * const p_api_ctrl) +{ + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + +#if (MRAM_CFG_PARAM_CHECKING_ENABLE) + + /* If null pointer return error. */ + FSP_ASSERT(NULL != p_ctrl); + + /* If control block not open return error. */ + FSP_ERROR_RETURN(MRAM_PRV_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Reset the MRAM. */ + return mram_reset(p_ctrl); +} + +/*******************************************************************************************************************//** + * Selects which block, Default (Block 0) or Alternate (Block 1), is used as the startup area block. The provided + * parameters determine which block will become the active startup block and whether that action will be immediate (but + * temporary), or permanent subsequent to the next reset. Implements + * @ref flash_api_t::startupAreaSelect. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE MRAM peripheral is busy with a prior operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit MRAM P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the MACI to become ready. + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_CMD_LOCKED MRAM Application Command Interface is in locked state + **********************************************************************************************************************/ +fsp_err_t R_MRAM_StartUpAreaSelect (flash_ctrl_t * const p_api_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary) +{ + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if (MRAM_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + err = r_mram_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If the swap type is BTFLG and the operation is temporary there's nothing to do. */ + FSP_ASSERT(!((swap_type == FLASH_STARTUP_AREA_BTFLG) && (is_temporary == false))); +#endif + + err = mram_set_startup_area_boot(p_ctrl, swap_type, is_temporary); + + return err; +} + +/*******************************************************************************************************************//** + * Stub function + * @ref flash_api_t::bankSwap. + * + * @retval FSP_ERR_UNSUPPORTED Bank Swap is not supported on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_BankSwap (flash_ctrl_t * const p_api_ctrl) +{ + /* Eliminate warning. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Indicate to the MRAM module that the system clock has changed. Implements @ref flash_api_t::updateFlashClockFreq. + * + * This should be the case if the application has changed the system clock. + * + * @retval FSP_SUCCESS Start-up area successfully toggled. + * @retval FSP_ERR_IN_USE MRAM is busy with an on-going operation. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl + * @retval FSP_ERR_NOT_OPEN MRAM API has not yet been opened. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_UpdateFlashClockFreq (flash_ctrl_t * const p_api_ctrl) +{ + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + +#if (MRAM_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the control block is not null and is opened. */ + fsp_err_t err = r_mram_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Calculate timeout values */ + mram_init(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Returns the information about the MRAM regions. Implements @ref flash_api_t::infoGet. + * + * @retval FSP_SUCCESS Successful retrieved the request information. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_info. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_InfoGet (flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info) +{ +#if MRAM_CFG_PARAM_CHECKING_ENABLE + + /* If null pointers return error. */ + FSP_ASSERT(NULL != p_api_ctrl); + FSP_ASSERT(NULL != p_info); + + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + + /* If the MRAM api is not open return an error. */ + FSP_ERROR_RETURN(MRAM_PRV_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#else + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + /* Copy information about the MRAM to the user structure. */ + p_info->code_flash = g_mram_code_region; + p_info->data_flash = g_mram_data_region; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Releases any resources that were allocated by the Open() or any subsequent MRAM operations. Implements + * @ref flash_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_ctrl or p_cfg. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_Close (flash_ctrl_t * const p_api_ctrl) +{ + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + +#if MRAM_CFG_PARAM_CHECKING_ENABLE + + /* If null pointer return error. */ + FSP_ASSERT(NULL != p_ctrl); + + /* If the MRAM api is not open return an error. */ + FSP_ERROR_RETURN(MRAM_PRV_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#else + + /* Eliminate warning if parameter checking is disabled. */ + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Close the API */ + p_ctrl->opened = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref flash_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_MRAM_CallbackSet (flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void * const p_context, + flash_callback_args_t * const p_callback_memory) +{ + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + +#if MRAM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(MRAM_PRV_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_ctrl->p_cfg->err_ipl, FSP_ERR_IRQ_BSP_DISABLED); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if MRAM_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + flash_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(flash_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Increments the selected anti-rollback counter. + * + * @note The counter is read internally before increment. + * + * Implements @ref flash_api_t::antiRollbackCounterIncrement + * + * @retval FSP_SUCCESS Counter incremented successfully + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_api_ctrl + * @retval FSP_ERR_NOT_ENABLED The specified counter has not been configured (configuration is only required for ARC_NSEC) + * @retval FSP_ERR_OVERFLOW The counter cannot be incremented because it is already at its max value + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit MRAM P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the MACI to become ready. + * @retval FSP_ERR_CMD_LOCKED MRAM Application Command Interface is in locked state + * @retval FSP_ERR_UNSUPPORTED Selected anti-rollback counter is not supported on this MCU + **********************************************************************************************************************/ +fsp_err_t R_MRAM_AntiRollbackCounterIncrement (flash_ctrl_t * const p_api_ctrl, flash_arc_t counter) +{ + fsp_err_t err; + + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + uint8_t mcntselr = mram_counter_to_mcntselr_convert(counter); + +#if MRAM_CFG_PARAM_CHECKING_ENABLE + err = r_mram_arc_common_parameter_checking(p_ctrl, counter, mcntselr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Read the current counter value*/ + uint32_t count; + err = mram_arc_read(p_ctrl, mcntselr, &count); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check for overflow. */ + uint32_t max_count; + if (counter >= FLASH_ARC_NSEC_0) + { + uint8_t arcns = *((uint16_t *) MRAM_PRV_OFS_ARCCS_ADDR) & MRAM_PRV_OFS_ARCCS_ARCNS_Msk; + max_count = (arcns == MRAM_PRV_ARCNS_MULTIPLE) ? + BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT : BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT; + } + else if (counter == FLASH_ARC_OEMBL) + { + max_count = BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT; + } + else + { + max_count = BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT; + } + + FSP_ERROR_RETURN((count + 1) <= max_count, FSP_ERR_OVERFLOW); + + /* Increment the counter */ + err = + mram_arc_cmd_execute(p_ctrl, mcntselr, MRAM_PRV_MACI_CMD_INCREMENT_COUNTER, p_ctrl->timeout_arc_increment); + + return err; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::antiRollbackCounterRefresh + * + * @retval FSP_ERR_UNSUPPORTED Anti-Rollback counter refresh is not supported on this MCU + **********************************************************************************************************************/ +fsp_err_t R_MRAM_AntiRollbackCounterRefresh (flash_ctrl_t * const p_api_ctrl, flash_arc_t counter) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(counter); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Reads the selected anti-rollback counter and returns the number of counter bits set. + * + * Implements @ref flash_api_t::antiRollbackCounterRead + * + * @retval FSP_SUCCESS Counter read successfully into p_count + * @retval FSP_ERR_NOT_OPEN The control block is not open. + * @retval FSP_ERR_ASSERTION NULL provided for p_api_ctrl or p_count + * @retval FSP_ERR_NOT_ENABLED The specified counter has not been configured (configuration is only required for ARC_NSEC) + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit MRAM P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the MACI to become ready. + * @retval FSP_ERR_CMD_LOCKED MRAM Application Command Interface is in locked state + **********************************************************************************************************************/ +fsp_err_t R_MRAM_AntiRollbackCounterRead (flash_ctrl_t * const p_api_ctrl, flash_arc_t counter, + uint32_t * const p_count) +{ + fsp_err_t err; + + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) p_api_ctrl; + uint8_t mcntselr = mram_counter_to_mcntselr_convert(counter); + +#if MRAM_CFG_PARAM_CHECKING_ENABLE + err = r_mram_arc_common_parameter_checking(p_ctrl, counter, mcntselr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(p_count); +#endif + + /* Read the counter */ + err = mram_arc_read(p_ctrl, mcntselr, p_count); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return err; +} + +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::userLockableAreaWrite + * + * @retval FSP_ERR_UNSUPPORTED User Lockable Area is not supported on this MCU + **********************************************************************************************************************/ +fsp_err_t R_MRAM_UserLockableAreaWrite (flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t mram_address, + uint32_t const num_bytes) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(src_address); + FSP_PARAMETER_NOT_USED(mram_address); + FSP_PARAMETER_NOT_USED(num_bytes); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup MRAM) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Write data to the MRAM. + * + * @param[in] src_address Address of the data to be written + * @param[in] mram_address Address of the MRAM to write + * @param[in] num_bytes Number of bytes to write + * + * @retval FSP_SUCCESS Write completed successfully + * @retval FSP_ERR_TIMEOUT MRAM timed out during write operation. + **********************************************************************************************************************/ +static fsp_err_t mram_write_data (uint32_t src_address, uint32_t mram_address, uint32_t num_bytes) +{ + fsp_err_t err = FSP_SUCCESS; + + uint8_t * p_dest_address = (uint8_t *) mram_address; + uint8_t * p_src_address = (uint8_t *) src_address; + uint32_t operations_remaining = num_bytes; + + mram_program_control(mram_address, true); + + /* Follow the figure "Code MRAM programming procedure (smaller than 32-bytes programming)" in the MRAM section + * of the relevant hardware manual. */ + while (operations_remaining > 0 && FSP_SUCCESS == err) + { + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MRCPS_b.PRGBSYC, 0); + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MRCPS_b.ABUFFULL, 0); + uint32_t write_count = + (operations_remaining < + BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES) ? operations_remaining : + BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES - + ((uint32_t) p_dest_address % BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES); + for (uint32_t i = 0; i < write_count; i++) + { + *p_dest_address = *p_src_address; + p_dest_address += 1; + p_src_address += 1; + } + + operations_remaining -= write_count; + + if (BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES != write_count) + { + __DMB(); + __DSB(); + __ISB(); + R_MRMS->MRCFLR = MRAM_PRV_MRCFLR_FLUSH; + } + + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MRCPS_b.ABUFEMP, 1); + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MRCPS_b.PRGBSYC, 0); + } + + mram_program_control(mram_address, false); + + return err; +} + +/*******************************************************************************************************************//** + * Erase the block at the start address in the control block. + * + * @param[in] address Address of the simulated block to start erasing + * @param[in] num_blocks Number of simulated blocks to erase + * + * @retval FSP_SUCCESS The erase completed successfully. + * @retval FSP_ERR_TIMEOUT The erase operation timed out. + **********************************************************************************************************************/ +static fsp_err_t mram_erase_blocks (uint32_t address, uint32_t num_blocks) +{ + fsp_err_t err = FSP_SUCCESS; + + uint8_t * dest_address = (uint8_t *) address; + uint32_t operations_remaining = num_blocks * + (BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES / + BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES); + + mram_program_control(address, true); + + /* Follow the figure "Code MRAM programming procedure (32-bytes programming)" in the MRAM section of the + * relevant hardware manual. */ + while (0 < operations_remaining && FSP_SUCCESS == err) + { + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MRCPS_b.PRGBSYC, 0); + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MRCPS_b.ABUFFULL, 0); + + for (uint32_t j = 0; j < BSP_FEATURE_MRAM_PROGRAMMING_SIZE_BYTES; j++) + { + *dest_address = UINT8_MAX; + dest_address += 1; + } + + operations_remaining--; + __DMB(); + __DSB(); + __ISB(); + R_MRMS->MRCFLR = MRAM_PRV_MRCFLR_FLUSH; + + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MRCPS_b.ABUFEMP, 1); + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MRCPS_b.PRGBSYC, 0); + } + + mram_program_control(address, false); + + return err; +} + +/*******************************************************************************************************************//** + * Enable/Disable writing to MRAM + * + * @param[in] address Target address + * @param[in] enable Enable/Disable flag + **********************************************************************************************************************/ +static void mram_program_control (uint32_t address, bool enable) +{ + if (enable) + { + bsp_prv_clear_pfb(); + + /* Enable highs-speed program mode. */ + R_MRMS->MRPSC = 1; + } + else + { + /* Disable high-speed program mode. */ + R_MRMS->MRPSC = 0; + (void) R_MRMS->MRPSC; + + bsp_prv_set_pfb(); + } + + /* Check secure/non-secure */ + if (BSP_FEATURE_TZ_NS_OFFSET == (address & BSP_FEATURE_TZ_NS_OFFSET)) + { + /* Enable or Disable writing to Non-Secure MRAM */ + R_MRMS->MRCPC0 = MRAM_PRV_MRCPC0_KEY | enable; + } + else + { + /* Enable or Disable writing to Secure MRAM */ + R_MRMS->MRCPC1 = MRAM_PRV_MRCPC1_KEY | enable; + } +} + +/*******************************************************************************************************************//** + * Check for errors after a MRAM operation + * + * @param[in] p_ctrl MRAM control block + * @param[in] previous_error The previous error + * + * @retval FSP_SUCCESS Command completed successfully + * @retval FSP_ERR_CMD_LOCKED MRAM entered command locked state + **********************************************************************************************************************/ +static fsp_err_t mram_check_errors (mram_instance_ctrl_t * const p_ctrl, fsp_err_t previous_error) +{ + /* See "Recovery from the Command-Locked State" in the MRAM section of the relevant hardware manual. */ + fsp_err_t err = FSP_SUCCESS; + + if (1U == R_MRMS->MASTAT_b.CMDLK) + { + err = FSP_ERR_CMD_LOCKED; + } + + if (1U == R_MRMS->MREZS_b.WHUKEXE) + { + err = FSP_ERR_HUK_ZEROIZATION; + } + + /* Return the first error code that was encountered. */ + if (FSP_SUCCESS != previous_error) + { + err = previous_error; + } + + if (FSP_SUCCESS != err) + { + /* Stop the MRAM and return the previous error. */ + (void) mram_stop(p_ctrl); + } + + return err; +} + +#if (MRAM_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the parameter checking required by the write, read and blank check functions. + * + * @param[in] p_ctrl MRAM control block + * @param[in] mram_address The MRAM address to be written to + * @param[in] num_bytes The number bytes + * @param[in] size_err Error to report when the size is invalid. + * + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_IN_USE The MRAM peripheral is busy with a prior on-going transaction. + * @retval FSP_ERR_NOT_OPEN The MRAM API is not Open. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_SIZE Number of bytes provided was not a multiple of the programming size or exceeded + * the maximum range. + * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. + **********************************************************************************************************************/ +static fsp_err_t r_mram_write_erase_parameter_checking (mram_instance_ctrl_t * const p_ctrl, + uint32_t mram_address, + uint32_t const num_bytes, + fsp_err_t size_err) +{ + /* Verify the control block is not null and is opened. Verify the MRAM isn't in use. */ + fsp_err_t err = r_mram_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + // uint32_t write_size; + + FSP_ERROR_RETURN(BSP_FEATURE_FLASH_CODE_FLASH_START <= mram_address, FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(mram_address < BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES, FSP_ERR_INVALID_ADDRESS); + FSP_ERROR_RETURN(mram_address + num_bytes <= BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES, size_err); + + /* If invalid number of bytes return error. */ + FSP_ERROR_RETURN((0 != num_bytes), size_err); + + return FSP_SUCCESS; +} + +#endif + +#if (MRAM_CFG_PARAM_CHECKING_ENABLE == 1) + +/*******************************************************************************************************************//** + * This function performs the common parameter checking required by top level API functions. + * + * @param p_ctrl Pointer to the control block + * + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_NOT_OPEN The MRAM module is not open. + * @retval FSP_ERR_IN_USE The MRAM peripheral is busy with a prior on-going transaction. + **********************************************************************************************************************/ +static fsp_err_t r_mram_common_parameter_checking (mram_instance_ctrl_t * const p_ctrl) +{ + /* If null control block return error. */ + FSP_ASSERT(p_ctrl); + + /* If control block is not open return error. */ + FSP_ERROR_RETURN((MRAM_PRV_OPEN == p_ctrl->opened), FSP_ERR_NOT_OPEN); + + /* If the MRAM is currently in program/erase mode return an error. */ + FSP_ERROR_RETURN((R_MRMS->MENTRYR & MRAM_PRV_MENTRYR_PE_MODE_BITS) == 0x0000U, FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function performs the common parameter checking required by top level Anti Rollback Counter API functions. + * + * @param p_ctrl Pointer to the control block + * @param counter The counter to be incremented or read + * @param mcntselr The current setting of the MCNTSELR : MRAM Counter Select Register + * + * @retval FSP_SUCCESS Parameter checking completed without error. + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_NOT_OPEN The MRAM module is not open. + * @retval FSP_ERR_IN_USE The MRAM peripheral is busy with a prior on-going transaction. + * @retval FSP_ERR_NOT_ENABLED The Anti Rollback Counter requested is not enabled. + * @retval FSP_ERR_UNSUPPORTED The Anti Rollback Counter requested is unsupported on this MCU. + **********************************************************************************************************************/ +static fsp_err_t r_mram_arc_common_parameter_checking (mram_instance_ctrl_t * const p_ctrl, + flash_arc_t counter, + uint8_t mcntselr) +{ + fsp_err_t err = r_mram_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + uint8_t arcns = *((uint16_t *) MRAM_PRV_OFS_ARCCS_ADDR) & MRAM_PRV_OFS_ARCCS_ARCNS_Msk; + uint8_t target_counter_is_arc_ns = mcntselr & 0x4; + uint8_t target_counter_is_enabled = (MRAM_PRV_ARCNS_MULTIPLE == arcns) || + ((MRAM_PRV_ARCNS_SINGLE == arcns) && (counter == FLASH_ARC_NSEC_0)); + + /* Ensure that requested counter is supported by hardware. Some MCUs may not support all counter types. */ + #if (0 == BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT) + FSP_ERROR_RETURN(counter != FLASH_ARC_OEMBL, FSP_ERR_UNSUPPORTED); + #endif + + #if (0 == BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT) + FSP_ERROR_RETURN(counter != FLASH_ARC_SEC, FSP_ERR_UNSUPPORTED); + #endif + + #if (0 == BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS) + FSP_ERROR_RETURN(0 == target_counter_is_arc_ns, FSP_ERR_UNSUPPORTED); + #endif + + /* Ensure that requested NSEC counter has been configured when NSEC is the target counter */ + FSP_ERROR_RETURN(!target_counter_is_arc_ns || target_counter_is_enabled, FSP_ERR_NOT_ENABLED); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * This function converts the MRAM API counter enumeration to the register value for mCNTSELR + * + * @param counter The API counter value + * + * @returns mCNTSELR value + **********************************************************************************************************************/ +static uint8_t mram_counter_to_mcntselr_convert (flash_arc_t counter) +{ + return (uint8_t) ((counter < FLASH_ARC_NSEC_0 ? counter + 1 : counter + 2) & R_MRMS_MCNTSELR_CNTSEL_Msk); +} + +/*******************************************************************************************************************//** + * This function reads the anti-rollback counter value + * + * ARC_OEMBL is read by MACI command because it is required to be read before increment to support RSIP-E50D comparison + * by the MACI controller. The other counters are read by memory-mapped read. + * + * @param p_ctrl MRAM control block + * @param mcntselr mCNTSELR register value + * @param p_count The counter value + * + * @returns mCNTSELR value + **********************************************************************************************************************/ +static fsp_err_t mram_arc_read (mram_instance_ctrl_t * const p_ctrl, uint8_t mcntselr, uint32_t * const p_count) +{ + fsp_err_t err; + volatile uint32_t * p_src; + uint32_t counter_num_words; + uint32_t arc_oembl[2]; + + switch (mcntselr) + { + case MRAM_PRV_ARC_MCNTSELR_OEMBL: + { + err = mram_arc_cmd_execute(p_ctrl, mcntselr, MRAM_PRV_MACI_CMD_READ_COUNTER, p_ctrl->timeout_arc_read); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Read the counter values after successful MACI read command */ + arc_oembl[0] = R_MRMS->MCNTDTR0; + arc_oembl[1] = R_MRMS->MCNTDTR1; + + p_src = arc_oembl; + counter_num_words = BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT >> 5; + break; + } + + case MRAM_PRV_ARC_MCNTSELR_SEC: + { + p_src = (uint32_t *) MRAM_PRV_OFS_ARC_SEC_ADDR; + counter_num_words = BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT >> 5; + break; + } + + default: // ARC_NSEC + { + uint8_t arcns = *((uint16_t *) MRAM_PRV_OFS_ARCCS_ADDR) & MRAM_PRV_OFS_ARCCS_ARCNS_Msk; + p_src = (uint32_t *) MRAM_PRV_OFS_ARC_NSEC_ADDR; + + if (MRAM_PRV_ARCNS_MULTIPLE == arcns) + { + counter_num_words = BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT >> 5; // bits to words + uint32_t counter_index = ((uint32_t) mcntselr - MRAM_PRV_ARC_MCNTSELR_NSEC_0) * counter_num_words; + p_src = &p_src[counter_index]; + } + else if (MRAM_PRV_ARCNS_SINGLE == arcns) + { + counter_num_words = BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT >> 5; + } + else + { + return FSP_ERR_NOT_ENABLED; + } + + break; + } + } + + /* Determine the number of bits set in the counter data. This is the actual count value. */ + uint32_t count = 0; + + for (uint8_t word = 0; word < counter_num_words; word += 2) + { + uint32_t lo = p_src[word]; + uint32_t hi = p_src[1 + word]; + count += MRAM_PRV_64_BITS - (__CLZ(hi) + __CLZ(lo)); + } + + *p_count = count; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function executes an anti-rollback counter MACI operation (read and increment) + * + * @param[in] p_ctrl MRAM control block + * @param[in] mcntselr Register value to write to mCNTSELR to select the target counter + * @param[in] cmd The MACI command to use + * @param[in] wait_count The command timeout + * + * @returns mCNTSELR value + **********************************************************************************************************************/ +static fsp_err_t mram_arc_cmd_execute (mram_instance_ctrl_t * const p_ctrl, + uint8_t mcntselr, + uint8_t cmd, + volatile uint32_t wait_count) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Enter MRAM P/E mode. */ + mram_enter_pe_mode(); + + /* Select target counter */ + R_MRMS->MCNTSELR = mcntselr; + + /* Issue 2-part command to the MACI command-issuing area */ + MRAM_PRV_CMD->MACI_CMD8 = cmd; + MRAM_PRV_CMD->MACI_CMD8 = MRAM_PRV_MACI_CMD_FINAL; + + /* Wait for MRDY flag or timeout */ + while (1U != R_MRMS->MSTATR_b.MRDY) + { + if (wait_count == 0U) + { + err = FSP_ERR_TIMEOUT; + break; + } + + wait_count--; + } + + /* Check for errors and issue forced stop if error occurred */ + err = mram_check_errors(p_ctrl, err); + + /* Return to read mode*/ + fsp_err_t pe_exit_err = mram_transition_to_read_mode(p_ctrl); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +/*******************************************************************************************************************//** + * This function will initialize the internal timeout values based on the system clock frequency. + * + * @param p_ctrl Pointer to the instance control block + * @retval FSP_SUCCESS Clock and timeouts configured successfully. + **********************************************************************************************************************/ +static void mram_init (mram_instance_ctrl_t * p_ctrl) +{ + uint32_t system_clock_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_CPUCLK); + + /* Round up the frequency to a whole number */ + uint32_t system_clock_freq_mhz = (system_clock_freq_hz + (MRAM_PRV_FREQUENCY_IN_HZ - 1)) / + MRAM_PRV_FREQUENCY_IN_HZ; + + /* The calculation below calculates the number of ICLK ticks needed for the timeout delay. */ + + /* According to "Code MRAM Characteristics" in the Electrical Characteristics section of the relevant hardware manual the Max Programming Time for 32 bytes is 87.3us. */ + p_ctrl->timeout_mram_write = (uint32_t) (MRAM_PRV_MAX_MRAM_WRITE_US * system_clock_freq_mhz) / + MRAM_PRV_MINIMUM_CYCLES_PER_TIMEOUT_LOOP; + + /* According to table "MACI command Characteristics" in the Electrical Characteristics section of the relevant hardware manual max time for a MACI command is 3.7us. */ + p_ctrl->timeout_maci_command = + (uint32_t) (MRAM_PRV_MAX_MACI_COMMAND_US * system_clock_freq_mhz) / + MRAM_PRV_MINIMUM_CYCLES_PER_TIMEOUT_LOOP; + + /* According to table "MACI command Characteristics" in the Electrical Characteristics section of the relevant hardware manual the max time for a configuration set command is 9.42ms. */ + p_ctrl->timeout_configuration_set = (uint32_t) (MRAM_PRV_MAX_CONFIGURATION_SET_US * system_clock_freq_mhz) / + MRAM_PRV_MINIMUM_CYCLES_PER_TIMEOUT_LOOP; + + /* According to table "MACI command Characteristics" in the Electrical Characteristics section of the relevant hardware manual the max time for ARC increment command is 1.61ms. */ + p_ctrl->timeout_arc_increment = + (uint32_t) (MRAM_PRV_MAX_ARC_INCREMENT_US * system_clock_freq_mhz) / + MRAM_PRV_MINIMUM_CYCLES_PER_TIMEOUT_LOOP; + + /* According to table "MACI command Characteristics" in the Electrical Characteristics section of the relevant hardware manual the max time for ARC read command is 0.27us. */ + p_ctrl->timeout_arc_read = + (uint32_t) (MRAM_PRV_MAX_ARC_READ_US * system_clock_freq_mhz) / + MRAM_PRV_MINIMUM_CYCLES_PER_TIMEOUT_LOOP; +} + +/*******************************************************************************************************************//** + * This function switches the peripheral from P/E mode for Extra MRAM to Read mode. + * + * @retval FSP_SUCCESS Successfully entered P/E mode. + * @retval FSP_ERR_PE_FAILURE Failed to exited P/E mode + * @retval FSP_ERR_CMD_LOCKED MRAM entered command locked state. + **********************************************************************************************************************/ +static fsp_err_t mram_transition_to_read_mode (mram_instance_ctrl_t * p_ctrl) +{ + /* See "Transition to Read Mode" in the MRAM section of the relevant hardware manual. */ + /* MRDY and CMDLK are checked after the previous commands complete and do not need to be checked again. */ + fsp_err_t err = FSP_SUCCESS; + + uint32_t wait_count = p_ctrl->timeout_maci_command; + + /* Wait for MRDY flag or timeout */ + while (1U != R_MRMS->MSTATR_b.MRDY) + { + if (wait_count == 0U) + { + err = FSP_ERR_TIMEOUT; + break; + } + + wait_count--; + } + + err = mram_check_errors(p_ctrl, err); + + /* Transition to Read mode */ + R_MRMS->MENTRYR = MRAM_PRV_MENTRYR_READ_MODE; + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MENTRYR, 0); + + bsp_prv_set_pfb(); + + return err; +} + +/*******************************************************************************************************************//** + * This function resets the MRAM peripheral. + * @param[in] p_ctrl Pointer to the MRAM instance control block. + * @retval FSP_SUCCESS Reset completed + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit P/E mode. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the MACI to become ready. + * @retval FSP_ERR_CMD_LOCKED MRAM Application Command Interface is in locked state + **********************************************************************************************************************/ +static fsp_err_t mram_reset (mram_instance_ctrl_t * p_ctrl) +{ + /* Enter P/E mode to execute MACI commands. */ + mram_enter_pe_mode(); + + /* Issue a MRAM Stop to stop any ongoing operation*/ + fsp_err_t err = mram_stop(p_ctrl); + + /*Issue stop command to MRAM command area*/ + MRAM_PRV_CMD->MACI_CMD8 = (uint8_t) MRAM_PRV_MACI_CMD_STATUS_CLEAR; + + /* Transition back to Read mode */ + fsp_err_t temp_err = mram_transition_to_read_mode(p_ctrl); + + if (FSP_SUCCESS == err) + { + err = temp_err; + } + + return err; +} + +/*******************************************************************************************************************//** + * This function is used to force stop the MRAM during an ongoing operation. + * + * @retval FSP_SUCCESS Successful stop. + * @retval FSP_ERR_TIMEOUT Timeout executing the Forced Stop Command. + * @retval FSP_ERR_CMD_LOCKED Peripheral in command locked state. + **********************************************************************************************************************/ +static fsp_err_t mram_stop (mram_instance_ctrl_t * p_ctrl) +{ + /* See "Forced Stop Command" in the MRAM section of the relevant hardware manual. If the CMDLK bit + * is still set after issuing the force stop command return an error. */ + volatile uint32_t wait_count = p_ctrl->timeout_maci_command; + + MRAM_PRV_CMD->MACI_CMD8 = (uint8_t) MRAM_PRV_MACI_CMD_FORCED_STOP; + + while (1U != R_MRMS->MSTATR_b.MRDY) + { + if (wait_count == 0U) + { + return FSP_ERR_TIMEOUT; + } + + wait_count--; + } + + if (0U != R_MRMS->MASTAT_b.CMDLK) + { + return FSP_ERR_CMD_LOCKED; + } + + if (1U == R_MRMS->MREZS_b.WHUKEXE) + { + return FSP_ERR_HUK_ZEROIZATION; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Modifies the start-up program swap flag (BTFLG) based on the supplied parameters. These changes will take effect on + * the next reset. This command DOES modify the configuration via The Configuration Set command to update the BTFLG. + * + * @param p_ctrl Pointer to the instance control block. + * @param[in] swap_type The swap type Alternate or Default. + * @param[in] is_temporary Indicates if the swap should be temporary or permanent. + * + * @retval FSP_SUCCESS Access window successfully removed. + * @retval FSP_ERR_CMD_LOCKED MRAM Application Command Interface is in locked state + * @retval FSP_ERR_WRITE_FAILED Status is indicating a Programming error for the requested operation. + * @retval FSP_ERR_TIMEOUT Timed out waiting for the MACI to become ready. + * @retval FSP_ERR_PE_FAILURE Failed to enter or exit MRAM P/E mode. + **********************************************************************************************************************/ +static fsp_err_t mram_set_startup_area_boot (mram_instance_ctrl_t * p_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary) +{ + fsp_err_t err = FSP_SUCCESS; + + /* Enter MRAM P/E mode */ + mram_enter_pe_mode(); + + if (is_temporary) + { + R_MRMS->MSUACR = (uint16_t) (MRAM_PRV_MSUACR_KEY | swap_type); + } + else + { + uint32_t * ofs_sas = (uint32_t *) MRAM_PRV_OFS_SAS_ADDRESS; + memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); + + g_configuration_area_data[MRAM_PRV_CONFIG_SET_BTFLG_OFFSET] = + (uint16_t) (((((uint16_t) ~swap_type) & 0x1U) << 15U) | MRAM_PRV_OFS_SAS_MASK | + ((*ofs_sas & MRAM_PRV_OFS_SAS_BTSIZE_MASK) >> 16)); + + /* Write the configuration area to the startup region. */ + err = mram_configuration_area_write(p_ctrl, MRAM_PRV_MACI_CONFIG_SET_STARTUP, g_configuration_area_data); + + err = mram_check_errors(p_ctrl, err); + } + + /* Return to read mode */ + fsp_err_t pe_exit_err = mram_transition_to_read_mode(p_ctrl); + + if (FSP_SUCCESS == err) + { + err = pe_exit_err; + } + + return err; +} + +/*******************************************************************************************************************//** + * Execute the Configuration Set Command: sequence + * + * @param p_ctrl Pointer to the control block + * @param[in] mram_address MRAM address to be written to. + * @param[in] src_address Pointer to the data to write to the configuration area. + * + * @retval FSP_SUCCESS Configuration Set successful + * @retval FSP_ERR_TIMEOUT Timed out waiting for the MACI to become ready. + **********************************************************************************************************************/ +static fsp_err_t mram_configuration_area_write (mram_instance_ctrl_t * p_ctrl, + uint32_t mram_address, + uint16_t * src_address) +{ + volatile uint32_t timeout = p_ctrl->timeout_configuration_set; + + /* See "Configuration Set Command" in the MRAM section of the relevant hardware manual. */ + + R_MRMS->MSADDR = mram_address; + + MRAM_PRV_CMD->MACI_CMD8 = MRAM_PRV_MACI_CMD_CONFIG_SET_1; + MRAM_PRV_CMD->MACI_CMD8 = MRAM_PRV_MACI_CMD_CONFIG_SET_2; + + /* Write the configuration data. */ + for (uint32_t index = 0U; index < MRAM_PRV_CONFIG_SET_ACCESS_WORD_CNT; index++) + { + /* There are 8 16 bit halfwords that must be written to accomplish a configuration set */ + MRAM_PRV_CMD->MACI_CMD16 = src_address[index]; + } + + MRAM_PRV_CMD->MACI_CMD8 = MRAM_PRV_MACI_CMD_FINAL; + + while (1U != R_MRMS->MSTATR_b.MRDY) + { + if (timeout <= 0U) + { + return FSP_ERR_TIMEOUT; + } + + timeout--; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function switches the peripheral to P/E mode for Extra MRAM. + * See "Transition to Extra MRAM Program Mode" in the MRAM section of the relevant hardware manual. + **********************************************************************************************************************/ +static void mram_enter_pe_mode (void) +{ + /* While the MRAM API is in use we will disable the MRAM PFB. */ + bsp_prv_clear_pfb(); + + /* Enter Extra MRAM PE mode */ + R_MRMS->MENTRYR = MRAM_PRV_MENTRYR_TRANSITION_TO_PE; + + /* Wait until MENTRYR has entered P/E mode. */ + FSP_HARDWARE_REGISTER_WAIT(R_MRMS->MENTRYR, MRAM_PRV_MENTRYR_PE_MODE); +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to MRAM instance control block + * @param[in] event Event code + * @param[in] address Address of the ECC error + **********************************************************************************************************************/ +static void mram_call_callback (mram_instance_ctrl_t * p_ctrl, flash_event_t event, uint32_t address) +{ + flash_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + flash_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->data = address; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + mram_prv_ns_callback p_callback = (mram_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * MRAM error interrupt routine. + * + * This function implements the MRAM error isr. The function clears the interrupt request source on entry, populates the + * callback structure with the FLASH_IRQ_EVENT_ERR_ECC event, and providing a callback routine has been provided, calls + * the callback function with the event. + **********************************************************************************************************************/ +void mram_err_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + flash_event_t event; + uint32_t address = 0; + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + mram_instance_ctrl_t * p_ctrl = (mram_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if (1 == R_MRMS->MRCRAES_b.TEDERRC) + { + event = FLASH_EVENT_ERR_ECC; + address = R_MRMS->MRCRTEA; + } + else if (1 == R_MRMS->MRCRAES_b.DECERRC) + { + event = FLASH_EVENT_ERR_TWO_BIT; + address = R_MRMS->MRCRDEA; + } + else + { + event = FLASH_EVENT_ERR_FAILURE; + } + + /* Call the user callback. */ + mram_call_callback(p_ctrl, event, address); + + R_MRMS->MRCRAES = 0; + + /* Clear the Error Interrupt. */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_opamp/r_opamp.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_opamp/r_opamp.c new file mode 100644 index 0000000000..e01eb60d7a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_opamp/r_opamp.c @@ -0,0 +1,521 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_opamp_api.h" +#include "bsp_cfg.h" + +/* Configuration for this package. */ +#include "r_opamp_cfg.h" + +/* Private header file for this package. */ +#include "r_opamp.h" + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup OPAMP + * @{ + **********************************************************************************************************************/ +#define OPAMP_OPEN (0x4f414d50U) + +#define OPAMP_PRIV_AMPMC_LOW_POWER (0U) +#define OPAMP_PRIV_AMPMC_MIDDLE_SPEED (0x40U) +#if 2U == BSP_FEATURE_OPAMP_BASE_ADDRESS + #define OPAMP_PRIV_AMPMC_HIGH_SPEED (0xC0U) +#else + #define OPAMP_PRIV_AMPMC_HIGH_SPEED (0x80U) +#endif +#define OPAMP_CHARGE_PUMP_DELAY_US (100U) +#define OPAMP_MAX_SWITCH_CHANNELS (2) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +static void r_opamp_hardware_init(opamp_instance_ctrl_t * const p_instance_ctrl); + +/** Lookup table to select the minimum stabilization wait time for respective power mode based on OPAMP Characteristics + * See Chapter "Electrical Characteristics" in the relevant hardware manual + */ + +static const uint32_t g_opamp_stabilization_lookup[] = +{ + [OPAMP_PRIV_AMPMC_LOW_POWER] = BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US, + [OPAMP_PRIV_AMPMC_MIDDLE_SPEED] = BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US, + [OPAMP_PRIV_AMPMC_HIGH_SPEED] = BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US, +}; + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** OPAMP Implementation of OPAMP interface. */ +const opamp_api_t g_opamp_on_opamp = +{ + .open = R_OPAMP_Open, + .start = R_OPAMP_Start, + .stop = R_OPAMP_Stop, + .trim = R_OPAMP_Trim, + .infoGet = R_OPAMP_InfoGet, + .statusGet = R_OPAMP_StatusGet, + .close = R_OPAMP_Close, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Applies power to the OPAMP and initializes the hardware based on the user configuration. Implements + * @ref opamp_api_t::open. + * + * The op-amp is not operational until the @ref opamp_api_t::start is called. If the op-amp is configured to start after + * AGT compare match, the op-amp is not operational until @ref opamp_api_t::start and the associated AGT compare match + * event occurs. + * + * Some MCUs have switches that must be set before starting the op-amp. These switches must be set in the application + * code after @ref opamp_api_t::open and before @ref opamp_api_t::start. + * + * Example: + * @snippet r_opamp_example.c R_OPAMP_Open + * + * @retval FSP_SUCCESS Configuration successful. + * @retval FSP_ERR_ASSERTION An input pointer is NULL. + * @retval FSP_ERR_ALREADY_OPEN Control block is already opened. + * @retval FSP_ERR_INVALID_ARGUMENT An attempt to configure OPAMP in middle speed mode on MCU that does not + * support middle speed mode. + **********************************************************************************************************************/ +fsp_err_t R_OPAMP_Open (opamp_ctrl_t * const p_api_ctrl, opamp_cfg_t const * const p_cfg) +{ + opamp_instance_ctrl_t * p_ctrl = (opamp_instance_ctrl_t *) p_api_ctrl; + +#if OPAMP_CFG_PARAM_CHECKING_ENABLE + + /* Verify the pointers are not NULL. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + + /* Verify the control block has not already been initialized. */ + FSP_ERROR_RETURN(OPAMP_OPEN != p_ctrl->opened, FSP_ERR_ALREADY_OPEN); + +/* If the MCU does not have middle speed */ + #if (!BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED) + + /* This variant does not support middle speed mode. */ + FSP_ERROR_RETURN(OPAMP_MODE_MIDDLE_SPEED != ((opamp_extended_cfg_t *) p_cfg->p_extend)->mode, + FSP_ERR_INVALID_ARGUMENT); + #endif +#endif + + /* Save pointers for later use */ + p_ctrl->p_cfg = p_cfg; + opamp_extended_cfg_t * p_cfg_extend = (opamp_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + uint8_t amptrm_val = 0U; + uint8_t ampmc_val = 0U; + + /* Appropriately set the available channel based on the MCU */ + amptrm_val |= (uint8_t) p_cfg_extend->trigger_channel_0; + amptrm_val |= (uint8_t) (p_cfg_extend->trigger_channel_1 << 2U); + amptrm_val |= (uint8_t) (p_cfg_extend->trigger_channel_2 << 4U); + amptrm_val |= (uint8_t) (p_cfg_extend->trigger_channel_3 << 6U); + +#if (BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED) + ampmc_val = (uint8_t) (p_cfg_extend->mode << 6U); +#else + + /* This variant only uses bit 7 for power mode. Clear 6th bit. */ + ampmc_val = (uint8_t) (p_cfg_extend->mode << 6U) & R_OPAMP_AMPMC_AMPSP_Msk; +#endif + + p_ctrl->trim_state = OPAMP_PRIV_TRIM_STATE_INVALID; + + /* Initialize the hardware based on the configuration. */ + + R_BSP_MODULE_START(FSP_IP_OPAMP, 0); + + /* Stop operation of all op-amps. */ + R_OPAMP->AMPC = 0U; + + /* Initialize trim registers to factory trim values. */ +#if (BSP_FEATURE_OPAMP_TRIM_CAPABLE) + R_OPAMP->AMPUOTE = 0U; +#endif + R_OPAMP->AMPMC = ampmc_val; + R_OPAMP->AMPTRS = (uint8_t) (p_cfg_extend->agt_link); + R_OPAMP->AMPTRM = amptrm_val; + + /* Initialize to user defined switches and connection settings if the OPAMP as switches */ + + r_opamp_hardware_init(p_ctrl); + + p_ctrl->opened = OPAMP_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the minimum stabilization wait time in microseconds. Implements @ref opamp_api_t::infoGet. + * + * * Example: + * @snippet r_opamp_example.c R_OPAMP_InfoGet + * + * @retval FSP_SUCCESS information on opamp_power_mode stored in p_info. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_OPAMP_InfoGet (opamp_ctrl_t * const p_api_ctrl, opamp_info_t * const p_info) +{ + opamp_instance_ctrl_t * p_ctrl = (opamp_instance_ctrl_t *) p_api_ctrl; + FSP_PARAMETER_NOT_USED(p_ctrl); + + /* Perform parameter checking */ +#if (1 == OPAMP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the OPAMP is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(OPAMP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + uint8_t power_mode = R_OPAMP->AMPMC; + + p_info->min_stabilization_wait_us = g_opamp_stabilization_lookup[power_mode]; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * If the OPAMP is configured for hardware triggers, enables hardware triggers. Otherwise, starts the op-amp. + * Implements @ref opamp_api_t::start. + * + * Some MCUs have switches that must be set before starting the op-amp. These switches must be set in the application + * code after @ref opamp_api_t::open and before @ref opamp_api_t::start. + * + * Example: + * @snippet r_opamp_example.c R_OPAMP_Start + * + * @retval FSP_SUCCESS Op-amp started or hardware triggers enabled successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + * @retval FSP_ERR_INVALID_ARGUMENT channel_mask includes a channel that does not exist on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_OPAMP_Start (opamp_ctrl_t * const p_api_ctrl, uint32_t const channel_mask) +{ + opamp_instance_ctrl_t * p_ctrl = (opamp_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + FSP_PARAMETER_NOT_USED(p_ctrl); +#if (1 == OPAMP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the OPAMP is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(OPAMP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); + + /* Make sure all channels in the mask exist. */ + FSP_ERROR_RETURN(BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK == (BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK | channel_mask), + FSP_ERR_INVALID_ARGUMENT); +#endif + + /* Enable AGT start and ADC conversion end triggers or start the op-amp channel(s). */ + + R_OPAMP->AMPC |= (uint8_t) channel_mask; + + /* Return the error code */ + return err; +} + +/*******************************************************************************************************************//** + * Stops the op-amp. If the OPAMP is configured for hardware triggers, disables hardware triggers. Implements + * @ref opamp_api_t::stop. + * + * + * @retval FSP_SUCCESS Op-amp stopped or hardware triggers disabled successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + * @retval FSP_ERR_INVALID_ARGUMENT channel_mask includes a channel that does not exist on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_OPAMP_Stop (opamp_ctrl_t * const p_api_ctrl, uint32_t const channel_mask) +{ + opamp_instance_ctrl_t * p_ctrl = (opamp_instance_ctrl_t *) p_api_ctrl; + FSP_PARAMETER_NOT_USED(p_ctrl); +#if (1 == OPAMP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the OPAMP is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(OPAMP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); + + /* Make sure all channels in the mask exist. */ + FSP_ERROR_RETURN(BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK == (BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK | channel_mask), + FSP_ERR_INVALID_ARGUMENT); +#endif + + /* Disable AGT start and ADC conversion end triggers and stop the op-amp channel(s). */ + + R_OPAMP->AMPC &= (uint8_t) (~channel_mask); + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the operating status for each op-amp in a bitmask. This bit is set when operation begins, before the + * stabilization wait time has elapsed. Implements @ref opamp_api_t::statusGet. + * + * + * @retval FSP_SUCCESS Operating status of each op-amp provided in p_status. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_OPAMP_StatusGet (opamp_ctrl_t * const p_api_ctrl, opamp_status_t * const p_status) +{ + opamp_instance_ctrl_t * p_ctrl = (opamp_instance_ctrl_t *) p_api_ctrl; + FSP_PARAMETER_NOT_USED(p_ctrl); +#if (1 == OPAMP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the OPAMP is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(OPAMP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Read the operating status of the op-amps. */ + p_status->operating_channel_mask = R_OPAMP->AMPMON; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * On MCUs that support trimming, the op-amp trim register is set to the factory default after open(). This function + * allows the application to trim the operational amplifier to a user setting, which overwrites the factory default + * factory trim values. + * + * Not supported on all MCUs. See hardware manual for details. Not supported if configured for low power mode + * (OPAMP_MODE_LOW_POWER). + * + * This function is not reentrant. Only one side of one op-amp can be trimmed at a time. Complete the procedure for + * one side of one channel before calling trim() with command OPAMP_TRIM_CMD_START again. + * + * Implements @ref opamp_api_t::trim. + * + * See "User Offset Trimming" in the OPAMP section of the relevant hardware manual. + * The trim procedure works as follows: + * - Call trim() for the Pch (+) side input with command OPAMP_TRIM_CMD_START. + * - Connect a fixed voltage to the Pch (+) input. + * - Connect the Nch (-) input to the op-amp output to create a voltage follower. + * - Ensure the op-amp is operating and stabilized. + * - Call trim() for the Pch (+) side input with command OPAMP_TRIM_CMD_START. + * - Measure the fixed voltage connected to the Pch (+) input using the SAR ADC and save the value (referred to as A + * later in this procedure). + * - Iterate over the following loop 5 times: + * - Call trim() for the Pch (+) side input with command OPAMP_TRIM_CMD_NEXT_STEP. + * - Measure the op-amp output using the SAR ADC (referred to as B in the next step). + * - If A <= B, call trim() for the Pch (+) side input with command OPAMP_TRIM_CMD_CLEAR_BIT. + * - Call trim() for the Nch (-) side input with command OPAMP_TRIM_CMD_START. + * - Measure the fixed voltage connected to the Pch (+) input using the SAR ADC and save the value (referred to as A + * later in this procedure). + * - Iterate over the following loop 5 times: + * - Call trim() for the Nch (-) side input with command OPAMP_TRIM_CMD_NEXT_STEP. + * - Measure the op-amp output using the SAR ADC (referred to as B in the next step). + * - If A <= B, call trim() for the Nch (-) side input with command OPAMP_TRIM_CMD_CLEAR_BIT. + * + * @retval FSP_SUCCESS Conversion result in p_data. + * @retval FSP_ERR_UNSUPPORTED Trimming is not supported on this MCU. + * @retval FSP_ERR_INVALID_STATE The command is not valid in the current state of the trim state machine. + * @retval FSP_ERR_INVALID_ARGUMENT The requested channel is not operating or the trim procedure is not in progress + * for this channel/input combination. + * @retval FSP_ERR_INVALID_MODE Trim is not allowed in low power mode. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_OPAMP_Trim (opamp_ctrl_t * const p_api_ctrl, + opamp_trim_cmd_t const cmd, + opamp_trim_args_t const * const p_args) +{ + opamp_instance_ctrl_t * p_ctrl = (opamp_instance_ctrl_t *) p_api_ctrl; + +#if (1 == OPAMP_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_args); + + /* Verify the pointers are not NULL and ensure the OPAMP is already open. */ + FSP_ERROR_RETURN(OPAMP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_OPAMP_TRIM_CAPABLE, FSP_ERR_UNSUPPORTED); + + /* Trim not supported in low power mode. */ + FSP_ERROR_RETURN(OPAMP_PRIV_AMPMC_LOW_POWER != R_OPAMP->AMPMC, FSP_ERR_INVALID_MODE); + + /* Make sure the channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK == + (BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK | (1U << p_args->channel)), + FSP_ERR_INVALID_ARGUMENT); + if (OPAMP_TRIM_CMD_START != cmd) + { + /* Make sure the channel is operating. */ + uint8_t operating_channels = R_OPAMP->AMPMON; + FSP_ERROR_RETURN(operating_channels == (operating_channels | (1U << (uint8_t) p_args->channel)), + FSP_ERR_INVALID_ARGUMENT); + + /* Make sure the trim procedure was most recently started for this channel and input. */ + FSP_ERROR_RETURN(p_ctrl->trim_channel == p_args->channel, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_ctrl->trim_input == p_args->input, FSP_ERR_INVALID_ARGUMENT); + } +#endif + + /* Enable trimming. */ + + R_OPAMP->AMPUOTE |= (uint8_t) (1U << p_args->channel); + + /* Get the trim register for the requested channel and input. */ + uint8_t volatile * p_trim_reg = (uint8_t *) &R_OPAMP->AMPOT + (2 * p_args->channel); + p_trim_reg += p_args->input; + + if (OPAMP_TRIM_CMD_START == cmd) + { + /* OPAMP_PRIV_TRIM_STATE_BEGIN resets the trim procedure and can be called at any time. */ + p_ctrl->trim_state = OPAMP_PRIV_TRIM_STATE_BEGIN; + p_ctrl->trim_channel = p_args->channel; + p_ctrl->trim_input = p_args->input; + + /* Initialize the trim register to 0 during OPAMP_TRIM_CMD_START. */ + *p_trim_reg = 0U; + } + else + { + FSP_ERROR_RETURN(OPAMP_PRIV_TRIM_STATE_INVALID != p_ctrl->trim_state, FSP_ERR_INVALID_STATE); + if (OPAMP_TRIM_CMD_NEXT_STEP == cmd) + { + /* OPAMP_TRIM_CMD_NEXT_STEP can only be called 5 times (one for each trim bit). */ + FSP_ERROR_RETURN(OPAMP_PRIV_TRIM_STATE_END != p_ctrl->trim_state, FSP_ERR_INVALID_STATE); + p_ctrl->trim_state--; + + /* Set the next trim bit during OPAMP_TRIM_CMD_NEXT_STEP. */ + uint8_t mask = (uint8_t) (1U << p_ctrl->trim_state); + *p_trim_reg |= mask; + } + else /* (OPAMP_TRIM_CMD_CLEAR_BIT == cmd) */ + { + /* OPAMP_TRIM_CMD_CLEAR_BIT cannot be used until OPAMP_TRIM_CMD_NEXT_STEP is used at least once. */ + FSP_ERROR_RETURN(OPAMP_PRIV_TRIM_STATE_BEGIN != p_ctrl->trim_state, FSP_ERR_INVALID_STATE); + + /* If the current trim bit is already cleared, return an error. */ + uint8_t mask = (uint8_t) (1U << p_ctrl->trim_state); + FSP_ERROR_RETURN(0U != (*p_trim_reg & mask), FSP_ERR_INVALID_STATE); + + /* Clear the current trim bit during OPAMP_TRIM_CMD_CLEAR_BIT. */ + *p_trim_reg &= (uint8_t) (~mask); + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops the op-amps. Implements @ref opamp_api_t::close. + * + * + * @retval FSP_SUCCESS Instance control block closed successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_OPAMP_Close (opamp_ctrl_t * const p_api_ctrl) +{ + opamp_instance_ctrl_t * p_ctrl = (opamp_instance_ctrl_t *) p_api_ctrl; + + /* Perform parameter checking*/ +#if (1 == OPAMP_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the OPAMP is already open. */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(OPAMP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Set all OPAMP units and the reference current generator to be stopped. */ + R_OPAMP->AMPC = 0U; + + /* Mark driver as closed */ + p_ctrl->opened = 0U; + + /* Enter the module-stop state. */ + + R_BSP_MODULE_STOP(FSP_IP_OPAMP, 0); + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup OPAMP) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +static void r_opamp_hardware_init (opamp_instance_ctrl_t * const p_instance_ctrl) +{ +#if BSP_FEATURE_OPAMP_HAS_SWITCHES + + /* Switches and pin connections are supported through user configurations, configure the respective OPAMP channel,pin and charge pump with respect to configuration settings selected */ + opamp_extended_cfg_t * p_extend = ((opamp_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend); + + /* Clear AMPnMS, AMPnPS, and AMP0OS before setting AMPCPC */ + for (int i = 0; i <= OPAMP_MAX_SWITCH_CHANNELS; i++) + { + R_OPAMP->AMP[i].MS = 0x00; + R_OPAMP->AMP[i].PS = 0x00; + } + + R_OPAMP->AMP[0].OS = 0x00; + + /* Set PUMPnEN bit while the AMPnMS and AMPnPS registers are 00h (no connection). + * Additionally, set the PUMP0EN bit when the AMP0OS register is 00h (no connection). + * See "Operational Amplifier Switch Charge Pump Control Register (AMPCPC)" description + * in the relevant hardware manual. *//* AVCC0 = VCC, enable charge pump for respective channel if AVCC0 < 2.7 V + * Reference: Section "Operational Amplifier Switch Charge Pump Control Register (AMPCPC)" and + * "Electrical characteristics" in the relevant hardware manual */ + + #if BSP_CFG_MCU_VCC_MV < 2700 + uint8_t pump0_enable = 0U; + uint8_t pump1_enable = 0U; + uint8_t pump2_enable = 0U; + + (0U == p_extend->minus_input_select_opamp0 && 0U == p_extend->plus_input_select_opamp0 && + 0U == p_extend->output_select_opamp0) ? (pump0_enable = 0U) : (pump0_enable = 1U); + + (0U == p_extend->minus_input_select_opamp1 && + 0U == p_extend->plus_input_select_opamp1) ? (pump1_enable = 0U) : (pump1_enable = 1U); + + (0U == p_extend->minus_input_select_opamp2 && + 0U == p_extend->plus_input_select_opamp2) ? (pump2_enable = 0U) : (pump2_enable = 1U); + + R_OPAMP->AMPCPC = (uint8_t) (pump0_enable | (pump1_enable << 1U) | (pump2_enable << 2U)); + + R_BSP_SoftwareDelay(OPAMP_CHARGE_PUMP_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + #endif + + R_OPAMP->AMP[0].MS = (uint8_t) (p_extend->minus_input_select_opamp0); + R_OPAMP->AMP[0].PS = (uint8_t) (p_extend->plus_input_select_opamp0); + R_OPAMP->AMP[0].OS = (uint8_t) (p_extend->output_select_opamp0); + R_OPAMP->AMP[1].MS = (uint8_t) (p_extend->minus_input_select_opamp1); + R_OPAMP->AMP[1].PS = (uint8_t) (p_extend->plus_input_select_opamp1); + R_OPAMP->AMP[2].MS = (uint8_t) (p_extend->minus_input_select_opamp2); + R_OPAMP->AMP[2].PS = (uint8_t) (p_extend->plus_input_select_opamp2); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ospi/r_ospi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ospi/r_ospi.c new file mode 100644 index 0000000000..41fb82358d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ospi/r_ospi.c @@ -0,0 +1,989 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_ospi.h" + +#if OSPI_CFG_DMAC_SUPPORT_ENABLE + #include "r_transfer_api.h" + #include "r_dmac.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define OSPI_PRV_OPEN (0x4F535049U) +#define OSPI_PRV_SHIFT(device_0_settings, device) \ + (device_0_settings << (device * 16U)) +#define OSPI_PRV_RMW(reg, device_0_settings, device) \ + ((reg & ~(uint32_t) OSPI_PRV_SHIFT(UINT16_MAX, device)) | (OSPI_PRV_SHIFT(device_0_settings, device))) +#define OSPI_PRV_RMW_MASKED(reg, mask, device_0_settings, device) \ + ((reg & ~(uint32_t) OSPI_PRV_SHIFT(mask, device)) | (OSPI_PRV_SHIFT(device_0_settings, device))) +#define OSPI_PRV_AUTOMATIC_CALIBRATION_NORMAL_END (3U) +#define OSPI_PRV_DIRECT_COMMAND_MASK (3U) +#define OSPI_PRV_DIRECT_ADDR_AND_DATA_MASK (7U) +#define OSPI_PRV_PAGE_SIZE_BYTES (256U) + +#ifndef OSPI_MAX_WRITE_ENABLE_LOOPS + #define OSPI_MAX_WRITE_ENABLE_LOOPS (5) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static fsp_err_t r_ospi_automatic_calibration_seq(ospi_instance_ctrl_t * p_instance_ctrl); +static bool r_ospi_status_sub(ospi_instance_ctrl_t * p_instance_ctrl, uint8_t bit_pos); +static fsp_err_t r_ospi_spi_protocol_specific_settings(ospi_instance_ctrl_t * p_instance_ctrl, + spi_flash_protocol_t spi_protocol); +static fsp_err_t r_ospi_wen(ospi_instance_ctrl_t * p_instance_ctrl); +static void r_ospi_direct_transfer(ospi_instance_ctrl_t * p_instance_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup OSPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +const spi_flash_api_t g_ospi_on_spi_flash = +{ + .open = R_OSPI_Open, + .directWrite = R_OSPI_DirectWrite, + .directRead = R_OSPI_DirectRead, + .directTransfer = R_OSPI_DirectTransfer, + .spiProtocolSet = R_OSPI_SpiProtocolSet, + .write = R_OSPI_Write, + .erase = R_OSPI_Erase, + .statusGet = R_OSPI_StatusGet, + .xipEnter = R_OSPI_XipEnter, + .xipExit = R_OSPI_XipExit, + .bankSet = R_OSPI_BankSet, + .autoCalibrate = R_OSPI_AutoCalibrate, + .close = R_OSPI_Close, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Open the OSPI driver module. After the driver is open, the OSPI can be accessed like internal flash memory. + * + * Implements @ref spi_flash_api_t::open. + * + * Example: + * @snippet r_ospi_example.c R_OSPI_Open + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl or p_cfg is NULL. + * @retval FSP_ERR_ALREADY_OPEN Driver has already been opened with the same p_ctrl. + * @retval FSP_ERR_CALIBRATE_FAILED Failed to perform auto-calibrate. + * @retval FSP_ERR_INVALID_ARGUMENT Attempting to open the driver with an invalid SPI protocol for OctaRAM. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_Open (spi_flash_ctrl_t * const p_ctrl, spi_flash_cfg_t const * const p_cfg) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(OSPI_PRV_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + if (((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->memory_type == OSPI_DEVICE_RAM) + { + FSP_ERROR_RETURN(SPI_FLASH_PROTOCOL_DOPI == p_cfg->spi_protocol, FSP_ERR_INVALID_ARGUMENT); + } +#endif + + /* Enable clock to the OSPI block */ + R_BSP_MODULE_START(FSP_IP_OSPI, 0U); + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_cfg->p_extend; + + /* Initialize control block. */ + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->spi_protocol = p_cfg->spi_protocol; + p_instance_ctrl->channel = p_cfg_extend->channel; + +#if OSPI_CFG_DMAC_SUPPORT_ENABLE + if (p_cfg_extend->memory_type == OSPI_DEVICE_FLASH) + { + transfer_instance_t const * p_transfer = p_cfg_extend->p_lower_lvl_transfer; + #if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_transfer); + #endif + + /* Initialize transfer instance */ + p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + } +#endif + + /* Perform OSPI initial setup as described in hardware manual (see + * "Initial Settings" in the OSPI section of the relevant hardware manual). */ + + /* Set the device type as OctaFlash or OctaRAM and its corresponding storage capacity */ + R_OSPI->DSR[p_instance_ctrl->channel] = (p_cfg_extend->memory_size & R_OSPI_DSR_DVSZ_Msk) | + ((uint32_t) (p_cfg_extend->memory_type << R_OSPI_DSR_DVTYP_Pos) & + R_OSPI_DSR_DVTYP_Msk); + + /* DCSTR and DRCSTR values are designed to not change at the time of changing the SPI protocol. + * Minimum latencies are same for SPI and SOPI. + * In case the SPI protocol is intended to be changed to DOPI, these should be configured with latencies required for DOPI. + */ + ospi_timing_setting_t const * p_timing = p_cfg_extend->p_timing_settings; + R_OSPI->DCSTR = (uint32_t) (p_timing->cs_pulldown_lead << R_OSPI_DCSTR_DVSELLO_Pos) | + (uint32_t) (p_timing->cs_pullup_lag << R_OSPI_DCSTR_DVSELHI_Pos) | + (uint32_t) (p_timing->command_to_command_interval << + R_OSPI_DCSTR_DVSELCMD_Pos); + p_timing = p_cfg_extend->p_mem_mapped_read_timing_settings; + R_OSPI->DRCSTR = OSPI_PRV_RMW(R_OSPI->DRCSTR, + ((uint32_t) (p_cfg_extend->single_continuous_mode_read_idle_time << + R_OSPI_DRCSTR_CTRW0_Pos) | + (uint32_t) (p_timing->cs_pullup_lag << R_OSPI_DRCSTR_DVRDHI0_Pos) | + (uint32_t) (p_timing->cs_pulldown_lead << R_OSPI_DRCSTR_DVRDLO0_Pos) | + (uint32_t) (p_timing->command_to_command_interval << R_OSPI_DRCSTR_DVRDCMD0_Pos)), + p_instance_ctrl->channel); + + p_timing = p_cfg_extend->p_mem_mapped_write_timing_settings; + + /* Always keep single continuous write mode enabled with appropriate settings */ + R_OSPI->DWCSTR = OSPI_PRV_RMW(R_OSPI->DWCSTR, + ((uint32_t) (1U << R_OSPI_DWCSTR_CTW0_Pos) | + (uint32_t) (p_cfg_extend->single_continuous_mode_write_idle_time << + R_OSPI_DWCSTR_CTWW0_Pos) | + (uint32_t) (p_timing->cs_pullup_lag << R_OSPI_DWCSTR_DVWHI0_Pos) | + (uint32_t) (p_timing->cs_pulldown_lead << R_OSPI_DWCSTR_DVWLO0_Pos) | + (uint32_t) (p_timing->command_to_command_interval << R_OSPI_DWCSTR_DVWCMD0_Pos)), + p_instance_ctrl->channel); + + /* Max = 256 bytes, i.e., Page size */ + R_OSPI->DWSCTSR = OSPI_PRV_SHIFT(p_instance_ctrl->p_cfg->page_size_bytes << R_OSPI_DWSCTSR_CTSN0_Pos, + p_instance_ctrl->channel); + + /* Read back to ensure value has been written */ + FSP_HARDWARE_REGISTER_WAIT(R_OSPI->DWSCTSR, + OSPI_PRV_SHIFT(p_instance_ctrl->p_cfg->page_size_bytes << R_OSPI_DWSCTSR_CTSN0_Pos, + p_instance_ctrl->channel)); + + /* OctaRAM specific, Ignored by OctaFlash. */ + R_OSPI->DCSMXR = + OSPI_PRV_RMW_MASKED(R_OSPI->DCSMXR, + R_OSPI_DCSMXR_CTWMX0_Msk, + ((uint32_t) (p_cfg_extend->ram_chip_select_max_period_setting << R_OSPI_DCSMXR_CTWMX0_Pos)), + p_instance_ctrl->channel); + + /* Setup SPI protocol specific registers */ + fsp_err_t ret = r_ospi_spi_protocol_specific_settings(p_instance_ctrl, p_cfg->spi_protocol); + if (FSP_SUCCESS == ret) + { + p_instance_ctrl->open = OSPI_PRV_OPEN; + } + + return ret; +} + +/*******************************************************************************************************************//** + * Writes raw data directly to the OctaFlash. API not supported. Use R_OSPI_DirectTransfer + * + * Implements @ref spi_flash_api_t::directWrite. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_DirectWrite (spi_flash_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + FSP_PARAMETER_NOT_USED(read_after_write); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Reads raw data directly from the OctaFlash. API not supported. Use R_OSPI_DirectTransfer. + * + * Implements @ref spi_flash_api_t::directRead. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_DirectRead (spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Read/Write raw data directly with the OctaFlash/OctaRAM device. + * + * Implements @ref spi_flash_api_t::directTransfer. + * + * Example: + * @snippet r_ospi_example.c R_OSPI_DirectTransfer + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_DirectTransfer (spi_flash_ctrl_t * const p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_transfer); + FSP_ASSERT(0 != p_transfer->command_length); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + r_ospi_direct_transfer(p_instance_ctrl, p_transfer, direction); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enters Single Continuous Read/Write mode. + * + * Implements @ref spi_flash_api_t::xipEnter. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI - OctaRAM. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_XipEnter (spi_flash_ctrl_t * const p_ctrl) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + if (((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->memory_type == OSPI_DEVICE_RAM) + { + return FSP_ERR_UNSUPPORTED; + } +#endif + + /* Single continuous read mode (CTR0/1) is enabled. Other values are set during Open */ + R_OSPI->DRCSTR = + OSPI_PRV_RMW_MASKED(R_OSPI->DRCSTR, + R_OSPI_DRCSTR_CTR0_Msk, + ((uint32_t) (1U << R_OSPI_DRCSTR_CTR0_Pos)), + p_instance_ctrl->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Exits XIP (execute in place) mode. + * + * Implements @ref spi_flash_api_t::xipExit. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI - OctaRAM. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_XipExit (spi_flash_ctrl_t * const p_ctrl) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + if (((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->memory_type == OSPI_DEVICE_RAM) + { + return FSP_ERR_UNSUPPORTED; + } +#endif + + /* Single continuous read mode (CTR0/1) is disabled. Other values are set during Open */ + R_OSPI->DRCSTR = OSPI_PRV_RMW_MASKED(R_OSPI->DRCSTR, R_OSPI_DRCSTR_CTR0_Msk, 0U, p_instance_ctrl->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Program a page of data to the flash. + * + * Implements @ref spi_flash_api_t::write. + * + * Example: + * @snippet r_ospi_example.c R_OSPI_Write + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_DEVICE_BUSY Another Write/Erase transaction is in progress. + * @retval FSP_ERR_INVALID_SIZE Write operation crosses page-boundary. + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI - OctaRAM. + * @retval FSP_ERR_WRITE_FAILED The write enable bit was not set. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_Write (spi_flash_ctrl_t * const p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); + FSP_ASSERT(0 != byte_count); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Check that space remaining in page is sufficient for requested write size */ + uint32_t page_size = p_instance_ctrl->p_cfg->page_size_bytes; + uint32_t page_offset = (uint32_t) p_dest & (page_size - 1); + FSP_ERROR_RETURN((page_size - page_offset) >= byte_count, FSP_ERR_INVALID_SIZE); + if (((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->memory_type == OSPI_DEVICE_RAM) + { + return FSP_ERR_UNSUPPORTED; + } +#endif + + FSP_ERROR_RETURN(false == r_ospi_status_sub(p_instance_ctrl, p_instance_ctrl->p_cfg->write_status_bit), + FSP_ERR_DEVICE_BUSY); + + fsp_err_t err = r_ospi_wen(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + +#if OSPI_CFG_DMAC_SUPPORT_ENABLE + if (((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->memory_type == OSPI_DEVICE_FLASH) + { + /* Setup and start DMAC transfer. */ + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + transfer_instance_t const * p_transfer = p_cfg_extend->p_lower_lvl_transfer; + + /* Enable Octa-SPI DMA Bufferable Write */ + dmac_extended_cfg_t const * p_dmac_extend = p_transfer->p_cfg->p_extend; + R_DMAC0_Type * p_dma_reg = R_DMAC0 + (sizeof(R_DMAC0_Type) * p_dmac_extend->channel); + p_dma_reg->DMBWR = R_DMAC0_DMBWR_BWE_Msk; + + /* Update the block-mode transfer settings */ + p_transfer->p_cfg->p_info->p_src = p_src; + p_transfer->p_cfg->p_info->p_dest = p_dest; + p_transfer->p_cfg->p_info->num_blocks = 1U; + p_transfer->p_cfg->p_info->length = (uint16_t) byte_count; + err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_transfer->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Start DMA */ + err = p_transfer->p_api->softwareStart(p_transfer->p_ctrl, TRANSFER_START_MODE_SINGLE); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Wait for DMAC to complete to maintain deterministic processing and backward compatibility */ + transfer_properties_t transfer_properties = {0U}; + err = p_transfer->p_api->infoGet(p_transfer->p_ctrl, &transfer_properties); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + while (FSP_SUCCESS == err && transfer_properties.block_count_remaining > 0) + { + err = p_transfer->p_api->infoGet(p_transfer->p_ctrl, &transfer_properties); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + /* Disable Octa-SPI DMA Bufferable Write */ + p_dma_reg->DMBWR = 0U; + } + +#else + uint32_t i = 0; + + /* Perform entire write opetation keeping the same access width to remain in single continuous write mode (see point#3 of + * "Single continuous write operation" in the OSPI section of the relevant hardware manual). + * + * A change in access width will reissue the write command only when the access width change happens at a 128-bit boundary. + * This is not handled by the code code below. + * Moreover, a blocking wait (until WIP = 0) needs to be introduced in order to change the access width within this API. + * Below is a conservative approach to perform the entire transfer with a fixed access width. + * Also, memcpy should not be used here to take advantage of larger access widths. + * + * *//* Word access */ + if (0 == byte_count % 4U) + { + uint32_t * p_word_aligned_dest = (uint32_t *) p_dest; + uint32_t * p_word_aligned_src = (uint32_t *) p_src; + for (i = 0; i < byte_count / 4U; i++) + { + *p_word_aligned_dest = *p_word_aligned_src; + p_word_aligned_dest++; + p_word_aligned_src++; + } + } + /* Half Word access */ + else if (0 == byte_count % 2U) + { + uint16_t * p_half_word_aligned_dest = (uint16_t *) p_dest; + uint16_t * p_half_word_aligned_src = (uint16_t *) p_src; + for (i = 0; i < byte_count / 2U; i++) + { + *p_half_word_aligned_dest = *p_half_word_aligned_src; + p_half_word_aligned_dest++; + p_half_word_aligned_src++; + } + } + /* Byte access */ + else + { + for (i = 0; i < byte_count; i++) + { + p_dest[i] = p_src[i]; + } + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. + * For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE. + * + * Implements @ref spi_flash_api_t::erase. + * + * @retval FSP_SUCCESS The command to erase the flash was executed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_device_address is NULL, byte_count doesn't match an erase + * size defined in spi_flash_cfg_t, or byte_count is set to 0. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI - OctaRAM. + * @retval FSP_ERR_WRITE_FAILED The write enable bit was not set. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_Erase (spi_flash_ctrl_t * const p_ctrl, uint8_t * const p_device_address, uint32_t byte_count) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_device_address); + FSP_ASSERT(0 != byte_count); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + if (((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->memory_type == OSPI_DEVICE_RAM) + { + return FSP_ERR_UNSUPPORTED; + } +#endif + spi_flash_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + uint16_t erase_command = 0; + uint32_t chip_address_base = + p_instance_ctrl->channel ? BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS : BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS; + uint32_t chip_address = (uint32_t) p_device_address - chip_address_base; + bool send_address = true; + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_cfg->p_extend; + FSP_ERROR_RETURN(false == r_ospi_status_sub(p_instance_ctrl, p_cfg->write_status_bit), FSP_ERR_DEVICE_BUSY); + + for (uint32_t index = 0; index < p_cfg->erase_command_list_length; index++) + { + /* If requested byte_count is supported by underlying flash, store the command. */ + if (byte_count == p_cfg->p_erase_command_list[index].size) + { + if (SPI_FLASH_ERASE_SIZE_CHIP_ERASE == byte_count) + { + /* Don't send address for chip erase. */ + send_address = false; + } + + erase_command = p_cfg->p_erase_command_list[index].command; + break; + } + } + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U != erase_command); +#endif + + fsp_err_t err = r_ospi_wen(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + spi_flash_direct_transfer_t direct_command = {0}; + direct_command.command = erase_command; + direct_command.address = chip_address; + direct_command.address_length = (true == send_address) ? + (OSPI_PRV_DIRECT_ADDR_AND_DATA_MASK & (p_cfg->address_bytes + 1U)) : 0U; + direct_command.command_length = (SPI_FLASH_PROTOCOL_EXTENDED_SPI == p_instance_ctrl->spi_protocol) ? + 1U : (p_cfg_extend->p_opi_commands->command_bytes & OSPI_PRV_DIRECT_COMMAND_MASK); + + r_ospi_direct_transfer(p_instance_ctrl, &direct_command, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Gets the write or erase status of the flash. + * + * Implements @ref spi_flash_api_t::statusGet. + * + * Example: + * @snippet r_ospi_example.c R_OSPI_StatusGet + * + * @retval FSP_SUCCESS The write status is in p_status. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_status is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI - OctaRAM. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_StatusGet (spi_flash_ctrl_t * const p_ctrl, spi_flash_status_t * const p_status) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + if (((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->memory_type == OSPI_DEVICE_RAM) + { + return FSP_ERR_UNSUPPORTED; + } +#endif + + /* Read device status. */ + p_status->write_in_progress = r_ospi_status_sub(p_instance_ctrl, p_instance_ctrl->p_cfg->write_status_bit); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Selects the bank to access. + * + * Implements @ref spi_flash_api_t::bankSet. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_BankSet (spi_flash_ctrl_t * const p_ctrl, uint32_t bank) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(bank); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Sets the SPI protocol. + * + * Implements @ref spi_flash_api_t::spiProtocolSet. + * + * @retval FSP_SUCCESS SPI protocol updated on MCU peripheral. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_CALIBRATE_FAILED Failed to perform auto-calibrate. + * @retval FSP_ERR_INVALID_ARGUMENT Attempting to set an invalid SPI protocol for OctaRAM. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_SpiProtocolSet (spi_flash_ctrl_t * const p_ctrl, spi_flash_protocol_t spi_protocol) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + if (p_cfg_extend->memory_type == OSPI_DEVICE_RAM) + { + FSP_ERROR_RETURN(SPI_FLASH_PROTOCOL_DOPI == spi_protocol, FSP_ERR_INVALID_ARGUMENT); + } +#endif + p_instance_ctrl->spi_protocol = spi_protocol; + + /* Update the SPI protocol and its associated registers. */ + return r_ospi_spi_protocol_specific_settings(p_instance_ctrl, spi_protocol); +} + +/*******************************************************************************************************************//** + * Auto-calibrate the OctaRAM device using the preamble pattern. + * @note The preamble pattern must be written to the configured address before calling this API. + * Implements @ref spi_flash_api_t::autoCalibrate. + * + * @retval FSP_SUCCESS SPI protocol updated on MCU peripheral. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_CALIBRATE_FAILED Failed to perform auto-calibrate. + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI - OctaFlash. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_AutoCalibrate (spi_flash_ctrl_t * const p_ctrl) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + if (p_cfg_extend->memory_type == OSPI_DEVICE_FLASH) + { + return FSP_ERR_UNSUPPORTED; + } +#endif + + /* Update the SPI protocol and its associated registers. */ + return r_ospi_automatic_calibration_seq(p_instance_ctrl); +} + +/*******************************************************************************************************************//** + * Close the OSPI driver module. + * + * Implements @ref spi_flash_api_t::close. + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_Close (spi_flash_ctrl_t * const p_ctrl) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if OSPI_CFG_DMAC_SUPPORT_ENABLE + + /* Initialize transfer instance */ + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + transfer_instance_t const * p_transfer = p_cfg_extend->p_lower_lvl_transfer; + if (p_cfg_extend->memory_type == OSPI_DEVICE_FLASH) + { + p_transfer->p_api->close(p_transfer->p_ctrl); + } +#endif + + p_instance_ctrl->open = 0U; + + /* Disable clock to the OSPI block */ + R_BSP_MODULE_STOP(FSP_IP_OSPI, 0U); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup OSPI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Perform initialization based on SPI/OPI protocol + * + * @param[in] p_instance_ctrl Pointer to OSPI specific control structure + * @param[in] spi_protocol SPI/OPI protocol request + * + * @retval FSP_SUCCESS Protocol based settings completed successfully. + * @retval FSP_ERR_CALIBRATE_FAILED Auto-Calibration failed. + **********************************************************************************************************************/ +static fsp_err_t r_ospi_spi_protocol_specific_settings (ospi_instance_ctrl_t * p_instance_ctrl, + spi_flash_protocol_t spi_protocol) +{ + spi_flash_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_cfg->p_extend; + fsp_err_t ret = FSP_SUCCESS; + ospi_device_number_t channel = p_instance_ctrl->channel; + + /* In case of SOPI mode enable pre-cycle as described in hardware manual (see Note 1 of + * "CDSR : Controller and Device Setting Register" description in the OSPI section of the relevant hardware manual). */ + uint32_t cdsr = R_OSPI->CDSR; + cdsr &= ~((uint32_t) (R_OSPI_CDSR_DV0TTYP_Msk << (channel * R_OSPI_CDSR_DV1TTYP_Pos)) | + (uint32_t) (R_OSPI_CDSR_DV0PC_Msk << channel)); + + /* Right shifted to match enum to register value */ + cdsr |= ((((uint32_t) spi_protocol) >> 1U) << (channel * R_OSPI_CDSR_DV1TTYP_Pos)); + + /* Enable pre-cycle setting in case of SOPI. ANDed to filter out SOPI enum from other mode enums. */ + cdsr |= ((((uint32_t) spi_protocol) & 1U) << (R_OSPI_CDSR_DV0PC_Pos + channel)); + + /* Keep DLFT disabled. No easy recovery from deadlock */ + cdsr |= 1U << R_OSPI_CDSR_DLFT_Pos; + R_OSPI->CDSR = cdsr; + + /* OPI mode */ + if (SPI_FLASH_PROTOCOL_EXTENDED_SPI != spi_protocol) + { + ospi_opi_command_set_t const * p_opi_commands = p_cfg_extend->p_opi_commands; + + /* In case of DOPI mode the order of data storage (Macronix IP) is byte1, byte0, byte3, byte2. + * Setting MROx and MWOx swaps the byte order between the internal and external bus at the time of read and write respectively. + * With MROx = 1 and MWOx = 1, at the time of write, + * byte0, byte1, byte2, byte3 will be presented as byte1, byte0, byte3, byte2 on the external bus and + * the Macronix flash will store this as byte0, byte1, byte2, byte3. + * Similarly, at the time of read, + * byte0, byte1, byte2, byte3 from Macronix flash will be presented as byte1, byte0, byte3, byte2 on the external bus and + * the internal bus (and CPU) will read this as byte0, byte1, byte2, byte3. + * Keeping this setting matches the written and read data as with SPI and SOPI protocol. + * + * MROx and MWOx setting is ignored for SPI and SOPI modes. + * See Note 1 of "MRWCSR : Memory Map Read/Write Setting Register" description + * in the OSPI section of the relevant hardware manual + */ + R_OSPI->MRWCSR = OSPI_PRV_RMW(R_OSPI->MRWCSR, + ((uint32_t) (((uint32_t) p_cfg->address_bytes + 1U) << R_OSPI_MRWCSR_MRAL0_Pos) | + (uint32_t) (p_opi_commands->command_bytes << R_OSPI_MRWCSR_MRCL0_Pos) | + (uint32_t) (((uint32_t) p_cfg->address_bytes + 1U) << R_OSPI_MRWCSR_MWAL0_Pos) | + (uint32_t) (p_opi_commands->command_bytes << R_OSPI_MRWCSR_MWCL0_Pos) | + (uint32_t) (p_cfg_extend->dopi_byte_order << R_OSPI_MRWCSR_MRO0_Pos) | + (uint32_t) (p_cfg_extend->dopi_byte_order << R_OSPI_MRWCSR_MWO0_Pos)), + channel); + + /* Set MDLR (Memory Map Dummy Length Reg) with Read and Write dummy length setting */ + R_OSPI->MDLR = + OSPI_PRV_RMW(R_OSPI->MDLR, + ((uint32_t) (p_cfg_extend->opi_mem_read_dummy_cycles << R_OSPI_MDLR_DV0RDL_Pos) | + (uint32_t) (p_cfg_extend->opi_mem_write_dummy_cycles << R_OSPI_MDLR_DV0WDL_Pos)), + channel); + + /* Specifies the read and write commands for Device */ + uint32_t read_command = (uint32_t) ((SPI_FLASH_PROTOCOL_SOPI == spi_protocol) ? + p_opi_commands->read_command : p_opi_commands->dual_read_command); + R_OSPI->MRWCR[channel] = (uint32_t) p_opi_commands->page_program_command << R_OSPI_MRWCR_DMWCMD0_Pos | + read_command; + uint32_t mdtr = R_OSPI->MDTR; + if (p_cfg_extend->memory_type == OSPI_DEVICE_FLASH) + { + mdtr &= ~R_OSPI_MDTR_DQSEDOPI_Msk; + mdtr |= (uint32_t) (p_cfg_extend->om_dqs_enable_counter_dopi << R_OSPI_MDTR_DQSEDOPI_Pos); + mdtr &= ~R_OSPI_MDTR_DQSESOPI_Msk; + mdtr |= (uint32_t) (p_cfg_extend->om_dqs_enable_counter_sopi << R_OSPI_MDTR_DQSESOPI_Pos); + } + else + { + mdtr &= ~R_OSPI_MDTR_DQSERAM_Msk; + mdtr |= (uint32_t) (p_cfg_extend->om_dqs_enable_counter_dopi << R_OSPI_MDTR_DQSERAM_Pos); + } + + /* If data_latch_delay_clocks is non-zero the DVnDEL bitfield is appropriately populated and auto-calibration is skipped. */ + mdtr = OSPI_PRV_RMW_MASKED(mdtr, + R_OSPI_MDTR_DV0DEL_Msk, + (uint32_t) p_cfg_extend->data_latch_delay_clocks, + channel); + + R_OSPI->MDTR = mdtr; + + /* Perform auto-calibration to appropriately update MDTR DVnDEL field */ + if ((0 == p_cfg_extend->data_latch_delay_clocks) && (p_cfg_extend->memory_type == OSPI_DEVICE_FLASH)) + { + ret = r_ospi_automatic_calibration_seq(p_instance_ctrl); + } + } + else + { + /* Command length is forced to 1 byte for SPI mode */ + R_OSPI->MRWCSR = OSPI_PRV_RMW(R_OSPI->MRWCSR, + ((uint32_t) (((uint32_t) p_cfg->address_bytes + 1U) << R_OSPI_MRWCSR_MRAL0_Pos) | + (uint32_t) (1U << R_OSPI_MRWCSR_MRCL0_Pos) | + (uint32_t) (((uint32_t) p_cfg->address_bytes + 1U) << R_OSPI_MRWCSR_MWAL0_Pos) | + (uint32_t) (1U << R_OSPI_MRWCSR_MWCL0_Pos)), + channel); + + /* Specifies the read and write commands for Device 0 */ + R_OSPI->MRWCR[channel] = (uint32_t) p_cfg->page_program_command << R_OSPI_MRWCR_DMWCMD0_Pos | + (uint32_t) p_cfg->read_command << R_OSPI_MRWCR_DMRCMD0_Pos; + + /* Single continuous read mode (CTR) must be disabled for SPI mode */ + R_OSPI->DRCSTR = OSPI_PRV_RMW_MASKED(R_OSPI->DRCSTR, R_OSPI_DRCSTR_CTR0_Msk, 0U, channel); + + /* Clear auto-calibration value */ + R_OSPI->MDTR = OSPI_PRV_RMW_MASKED(R_OSPI->MDTR, R_OSPI_MDTR_DV0DEL_Msk, 0U, channel); + + /* Set read/write dummy clocks to 0 in SPI mode. */ + R_OSPI->MDLR = OSPI_PRV_RMW_MASKED(R_OSPI->MDLR, R_OSPI_MDLR_DV0RDL_Msk, 0U, channel); + } + + return ret; +} + +/*******************************************************************************************************************//** + * Gets device status. + * + * @param[in] p_instance_ctrl Pointer to a driver handle + * @param[in] bit_pos Write-in-progress bit position + * + * @return True if busy, false if not. + **********************************************************************************************************************/ +static bool r_ospi_status_sub (ospi_instance_ctrl_t * p_instance_ctrl, uint8_t bit_pos) +{ + spi_flash_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + ospi_extended_cfg_t const * p_extend = (ospi_extended_cfg_t *) p_cfg->p_extend; + spi_flash_direct_transfer_t direct_command = {0}; + if (SPI_FLASH_PROTOCOL_EXTENDED_SPI == p_instance_ctrl->spi_protocol) + { + direct_command.command = p_cfg->status_command; + direct_command.command_length = 1U; + } + else + { + ospi_opi_command_set_t const * p_opi_commands = ((ospi_extended_cfg_t *) p_cfg->p_extend)->p_opi_commands; + direct_command.command = p_opi_commands->status_command; + direct_command.command_length = p_opi_commands->command_bytes & OSPI_PRV_DIRECT_COMMAND_MASK; + direct_command.address_length = (p_cfg->address_bytes + 1U) & + OSPI_PRV_DIRECT_ADDR_AND_DATA_MASK; + direct_command.dummy_cycles = p_extend->opi_status_read_dummy_cycles; + } + + direct_command.data_length = 1U; + r_ospi_direct_transfer(p_instance_ctrl, &direct_command, SPI_FLASH_DIRECT_TRANSFER_DIR_READ); + + return (direct_command.data >> bit_pos) & 1U; +} + +/*******************************************************************************************************************//** + * Send Write enable command to the OctaFlash + * + * @param[in] p_instance_ctrl Pointer to OSPI specific control structure + * + * @retval FSP_SUCCESS The write enable bit is set. + * @retval FSP_ERR_WRITE_FAILED The write enable bit was not set. + **********************************************************************************************************************/ +static fsp_err_t r_ospi_wen (ospi_instance_ctrl_t * p_instance_ctrl) +{ + spi_flash_direct_transfer_t direct_command = {0}; + spi_flash_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + if (SPI_FLASH_PROTOCOL_EXTENDED_SPI == p_instance_ctrl->spi_protocol) + { + direct_command.command = p_cfg->write_enable_command; + direct_command.command_length = 1U; + } + else + { + ospi_opi_command_set_t const * p_opi_commands = ((ospi_extended_cfg_t *) p_cfg->p_extend)->p_opi_commands; + direct_command.command = p_opi_commands->write_enable_command; + direct_command.command_length = p_opi_commands->command_bytes & OSPI_PRV_DIRECT_COMMAND_MASK; + } + + r_ospi_direct_transfer(p_instance_ctrl, &direct_command, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE); + + /* In case write enable is not checked, assume write is enabled. */ + bool write_enabled = true; + +#if OSPI_MAX_WRITE_ENABLE_LOOPS > 0U + + /* Verify write is enabled. */ + for (uint32_t i = 0U; i < OSPI_MAX_WRITE_ENABLE_LOOPS; i++) + { + write_enabled = r_ospi_status_sub(p_instance_ctrl, p_instance_ctrl->p_cfg->write_enable_bit); + if (write_enabled) + { + break; + } + } +#endif + + FSP_ERROR_RETURN(write_enabled, FSP_ERR_WRITE_FAILED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Perform Automatic Calibration + * + * @param[in] p_instance_ctrl Pointer to OSPI specific control structure + * + * @retval FSP_SUCCESS Auto-Calibration completed successfully. + * @retval FSP_ERR_CALIBRATE_FAILED Auto-Calibration failed. + **********************************************************************************************************************/ +static fsp_err_t r_ospi_automatic_calibration_seq (ospi_instance_ctrl_t * p_instance_ctrl) +{ + fsp_err_t ret = FSP_SUCCESS; + ospi_device_number_t channel = p_instance_ctrl->channel; + + /* Default ACTR value is long enough for stable environment */ + R_OSPI->ACAR[channel] = + (uint32_t) ((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->p_autocalibration_preamble_pattern_addr; + uint32_t cdsr = R_OSPI->CDSR; + + /* Enable auto-calibration and allow MDTR update */ + R_OSPI->CDSR = cdsr | (uint32_t) ((1U << (R_OSPI_CDSR_ACMEME0_Pos + channel))) | + (uint32_t) (1U << R_OSPI_CDSR_ACMODE_Pos); + + /* Using configured values for DQSSOPI nad DQSDOPI counter */ + /* MDTR.DVnDEL: Typical value(VCC=3.3, 25 degree C, typical sample) is around 0x80 */ + while (0 == (R_OSPI->ACSR & (uint32_t) (R_OSPI_ACSR_ACSR0_Msk << (channel * R_OSPI_ACSR_ACSR1_Pos)))) + { + /* Worst case delay is set by default ACTR value */ + } + + /* Disable automatic calibration */ + R_OSPI->CDSR = cdsr; + if ((OSPI_PRV_AUTOMATIC_CALIBRATION_NORMAL_END << (channel * R_OSPI_ACSR_ACSR1_Pos)) != + (R_OSPI->ACSR & (uint32_t) (R_OSPI_ACSR_ACSR0_Msk << (channel * R_OSPI_ACSR_ACSR1_Pos)))) + { + ret = FSP_ERR_CALIBRATE_FAILED; + } + + /* Clear automatic calibration status */ + R_OSPI->ACSR = + (uint32_t) (R_OSPI->ACSR & + ~(uint32_t) (R_OSPI_ACSR_ACSR0_Msk << (channel * R_OSPI_ACSR_ACSR1_Pos))); + + return ret; +} + +/*******************************************************************************************************************//** + * Performs direct data transfer with the OctaFlash/OctaRAM device + * + * @param[in] p_instance_ctrl Pointer to OSPI specific control structure + * @param[in] p_transfer Pointer to transfer parameters + * @param[in] direction Read/Write + **********************************************************************************************************************/ +static void r_ospi_direct_transfer (ospi_instance_ctrl_t * p_instance_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction) +{ + ospi_extended_cfg_t * p_extend = (ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + R_OSPI->DCR = p_transfer->command; /* Write OSPI command. */ + R_OSPI->DAR = p_transfer->address; /* Write OSPI address */ + + /* Build the read/write settings. */ + uint32_t dcsr = (uint32_t) (p_transfer->command_length << R_OSPI_DCSR_CMDLEN_Pos) | + (uint32_t) (p_transfer->address_length << R_OSPI_DCSR_ADLEN_Pos) | + (uint32_t) (p_transfer->dummy_cycles << R_OSPI_DCSR_DMLEN_Pos) | + + /* OctaFlash: DOPI = 0, SOPI = 1; OctaRAM: DOPI = 0. */ + (uint32_t) (((uint8_t) (p_instance_ctrl->spi_protocol & 2U) >> 1U) << R_OSPI_DCSR_DOPI_Pos) | + (uint32_t) (p_instance_ctrl->channel << R_OSPI_DCSR_ACDV_Pos) | + (uint32_t) (1U << R_OSPI_DCSR_DAOR_Pos) | + (uint32_t) (p_transfer->data_length << R_OSPI_DCSR_DALEN_Pos); + + /* Change the byte order as needed. */ + if ((SPI_FLASH_PROTOCOL_DOPI == p_instance_ctrl->spi_protocol) && + (OSPI_DOPI_BYTE_ORDER_0123 == p_extend->dopi_byte_order)) + { + dcsr &= ~R_OSPI_DCSR_DAOR_Msk; + } + + /* Apply Direct Read/Write settings */ + R_OSPI->DCSR = dcsr; + + if (SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE == direction) + { + if (0 == p_transfer->data_length) + { + /* Write any data. This will only send out command or command & address based on the settings above */ + R_OSPI->CWNDR = (uint32_t) OSPI_PRV_OPEN; + } + else + { + R_OSPI->CWDR = p_transfer->data; + } + } + else + { + p_transfer->data = R_OSPI->CRR; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_pdc/r_pdc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_pdc/r_pdc.c new file mode 100644 index 0000000000..bb5bdc70cb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_pdc/r_pdc.c @@ -0,0 +1,571 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_pdc_cfg.h" +#include "r_pdc.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "PDC" in ASCII, used to determine if driver is open. */ +#define PDC_PRV_OPEN (0x00504443ULL) + +/* Performs 8 32bit/4byte transfers per PDC data ready interrupt as described in hardware manual (see + * "Reception Operation" in the PDC section of the relevant hardware manual). + * */ +#define PDC_PRV_TRANSFER_SIZE 4U /* 32 bit transfer size from PCDR register */ +#define PDC_PRV_TRANSFERS_PER_BLOCK 8U + +#define PDC_PRV_MAX_PIXEL_RESOLUTION 0x1000U /* Max resolution: 4095 */ + +#define PDC_PRV_PCSR_MASK (R_PDC_PCSR_HERF_Msk | R_PDC_PCSR_VERF_Msk | R_PDC_PCSR_UDRF_Msk | \ + R_PDC_PCSR_OVRF_Msk | R_PDC_PCSR_FEF_Msk | R_PDC_PCSR_FEMPF_Msk | \ + R_PDC_PCSR_FBSY_Msk) // Mask of PCSR flag bits +#define PDC_PRV_INTERRUPT_DISABLE_MASK (~(R_PDC_PCCR0_HERIE_Msk | R_PDC_PCCR0_VERIE_Msk | R_PDC_PCCR0_UDRIE_Msk | \ + R_PDC_PCCR0_OVIE_Msk | R_PDC_PCCR0_FEIE_Msk | R_PDC_PCCR0_DFIE_Msk)) + +#define PDC_PRV_TIMEOUT 0xFFFFU + +/* Worst case ratio of (ICLK/PCLKB) = 64 approximately. + * 3 PCLKB cycles is the number of cycles to wait for IICn. + * See table "Access cycles" in the I/O Registers section of the relevant hardware manual + */ +#define PDC_PERIPHERAL_REG_MAX_WAIT (0x40U * 0x03U) + +#define PDC_HARDWARE_REGISTER_WAIT(reg, required_value, timeout) \ + while ((timeout)) \ + { \ + if ((required_value) == (reg)) \ + { \ + break; \ + } \ + (timeout)--; \ + } + +void pdc_transfer_req_isr(void); +void pdc_int_isr(void); + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void r_pdc_transfer_callback(pdc_instance_ctrl_t * p_ctrl); +static void r_pdc_error_handler(pdc_instance_ctrl_t * p_ctrl); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* Capture API */ +const capture_api_t g_pdc_on_capture = +{ + .open = R_PDC_Open, + .close = R_PDC_Close, + .captureStart = R_PDC_CaptureStart, + .statusGet = R_PDC_StatusGet, + .callbackSet = R_PDC_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup PDC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Powers on PDC, handles required initialization described in the hardware manual. + * + * Implements @ref capture_api_t::open. + * + * The Open function provides initial configuration for the PDC module. It powers on the module and enables the PCLKO + * output and the PIXCLK input. Further initialization requires the PIXCLK input to be running in order to be able to + * reset the PDC as part of its initialization. This clock is input from a camera module and so the reset and further + * initialization is performed in @ref capture_api_t::captureStart. This function should be called once prior to calling any + * other PDC API functions. After the PDC is opened the Open function should not be called again without first + * calling the Close function. + * + * Example: + * @snippet r_pdc_example.c R_PDC_Open + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION One or more of the following parameters is NULL + * 1. p_cfg is NULL + * 2. p_api_ctrl is NULL + * 3. The pointer to the transfer interface in the p_cfg parameter is NULL + * 4. Callback parameter is NULL. + * 5. Invalid IRQ number assigned + * @retval FSP_ERR_INVALID_ARGUMENT One or more of the following parameters is incorrect + * 1. bytes_per_pixel is zero + * 2. x_capture_pixels is zero + * 3. y_capture_pixels is zero + * 4. x_capture_start_pixel + x_capture_pixels is greater than 4095, OR + * 5. y_capture_start_pixel + y_capture_pixels is greater than 4095 + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **********************************************************************************************************************/ +fsp_err_t R_PDC_Open (capture_ctrl_t * const p_ctrl, capture_cfg_t const * const p_cfg) +{ + fsp_err_t err; + pdc_instance_ctrl_t * p_instance_ctrl = (pdc_instance_ctrl_t *) p_ctrl; + +#if (PDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != ((pdc_extended_cfg_t *) p_cfg->p_extend)->p_lower_lvl_transfer); + FSP_ASSERT(p_cfg->p_callback != NULL); + FSP_ASSERT(((pdc_extended_cfg_t *) p_cfg->p_extend)->pdc_irq >= (IRQn_Type) 0); + FSP_ERROR_RETURN((p_cfg->bytes_per_pixel != 0UL), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((p_cfg->x_capture_pixels != (uint16_t) 0UL), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((p_cfg->y_capture_pixels != (uint16_t) 0UL), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN( + ((p_cfg->y_capture_start_pixel + p_cfg->y_capture_pixels) < (uint16_t) PDC_PRV_MAX_PIXEL_RESOLUTION), + FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN( + ((p_cfg->x_capture_start_pixel + p_cfg->x_capture_pixels) < (uint16_t) PDC_PRV_MAX_PIXEL_RESOLUTION), + FSP_ERR_INVALID_ARGUMENT); +#endif + p_instance_ctrl->p_cfg = p_cfg; + +#if (PDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ERROR_RETURN(PDC_PRV_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + pdc_extended_cfg_t * p_extend = (pdc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + R_BSP_IrqCfgEnable(p_extend->pdc_irq, p_extend->pdc_ipl, p_ctrl); + + /* If DTC is used */ + if (p_extend->transfer_req_irq >= 0) + { + R_BSP_IrqCfgEnable(p_extend->transfer_req_irq, p_extend->transfer_req_ipl, p_ctrl); + } + + p_instance_ctrl->transfer_in_progress = false; + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + + /** Disable module stop mode for PDC */ + R_BSP_MODULE_START(FSP_IP_PDC, 0); + + /* Performs PDC initialization as described in hardware manual (see + * "Initial Settings" in the PDC section of the relevant hardware manual). + * Disable PDC + * Set PCLKB divider + * Enable PCLKO output + * Enable the PIXCLK input + */ + R_PDC->PCCR1 = (uint32_t) 0UL; + R_PDC->PCCR0 = ((uint32_t) (p_extend->clock_division << R_PDC_PCCR0_PCKDIV_Pos) & R_PDC_PCCR0_PCKDIV_Msk) | + (1U << R_PDC_PCCR0_PCKOE_Pos) | + (1U << R_PDC_PCCR0_PCKE_Pos); + + /* Open the transfer driver. Clear the transfer length in case the transfer_info_t structure is reused and the + * length was copied to the upper 8 bits for block mode. Configurations are updated before it is used. */ + + transfer_info_t * p_info = p_extend->p_lower_lvl_transfer->p_cfg->p_info; + uint32_t transfer_settings = (uint32_t) TRANSFER_MODE_BLOCK << TRANSFER_SETTINGS_MODE_BITS | + (uint32_t) TRANSFER_ADDR_MODE_INCREMENTED << + TRANSFER_SETTINGS_DEST_ADDR_BITS | + (uint32_t) TRANSFER_SIZE_4_BYTE << TRANSFER_SETTINGS_SIZE_BITS | + (uint32_t) TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS | + (uint32_t) TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS; + + /** Set up transfer interface */ + p_info->length = PDC_PRV_TRANSFERS_PER_BLOCK; + + /** Configure the transfer interface */ + + p_info->p_src = (void const *) &R_PDC->PCDR; + uint32_t num_blocks = + (uint32_t) (p_cfg->x_capture_pixels * p_cfg->bytes_per_pixel * + p_cfg->y_capture_pixels) / + (uint32_t) (PDC_PRV_TRANSFER_SIZE * PDC_PRV_TRANSFERS_PER_BLOCK); + p_info->num_blocks = (uint16_t) num_blocks; + p_instance_ctrl->num_blocks = p_info->num_blocks; + p_info->transfer_settings_word = transfer_settings; + + err = p_extend->p_lower_lvl_transfer->p_api->open(p_extend->p_lower_lvl_transfer->p_ctrl, + p_extend->p_lower_lvl_transfer->p_cfg); + + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + p_instance_ctrl->open = PDC_PRV_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Stops and closes the transfer interface, disables and powers off the PDC, clears internal driver data + * and disables interrupts. + * + * Implements @ref capture_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL + * @retval FSP_ERR_NOT_OPEN Open has not been successfully called. + **********************************************************************************************************************/ +fsp_err_t R_PDC_Close (capture_ctrl_t * const p_ctrl) +{ + pdc_instance_ctrl_t * p_instance_ctrl = (pdc_instance_ctrl_t *) p_ctrl; + +#if (PDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PDC_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + pdc_extended_cfg_t * p_extend = (pdc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Disable all interrupts. */ + R_PDC->PCCR0 &= PDC_PRV_INTERRUPT_DISABLE_MASK; + + /* Close the transfer driver. */ + p_extend->p_lower_lvl_transfer->p_api->close(p_extend->p_lower_lvl_transfer->p_ctrl); + + /* Disable PDC */ + R_PDC->PCCR1 = (uint32_t) 0UL; + + R_BSP_IrqDisable(p_extend->pdc_irq); + + if (p_extend->transfer_req_irq >= 0) + { + R_BSP_IrqDisable(p_extend->transfer_req_irq); + } + + R_BSP_MODULE_STOP(FSP_IP_PDC, 0); + + /* Mark driver as closed */ + p_instance_ctrl->open = 0U; + + /* Mark transfer as not in progress */ + p_instance_ctrl->transfer_in_progress = false; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @brief Starts a capture. Enables interrupts. + * + * Implements @ref capture_api_t::captureStart. + * + * Sets up the transfer interface to transfer data from the PDC into the specified buffer. Configures the PDC settings + * as previously set by the @ref capture_api_t::open API. These settings are configured here as the PIXCLK input must be active + * for the PDC reset operation. + * When a capture is complete the callback registered during @ref capture_api_t::open API call will be called. + * + * Example: + * @snippet r_pdc_example.c R_PDC_CaptureStart + * + * @retval FSP_SUCCESS Capture start successful. + * @retval FSP_ERR_ASSERTION One or more of the following parameters is NULL + * 1. p_api_ctrl is NULL + * 2. p_buffer is NULL + * @retval FSP_ERR_NOT_OPEN Open has not been successfully called. + * @retval FSP_ERR_IN_USE PDC transfer is already in progress. + * @retval FSP_ERR_TIMEOUT Reset operation timed out. + * @retval FSP_ERR_NOT_INITIALIZED Callback function has not been set + **********************************************************************************************************************/ +fsp_err_t R_PDC_CaptureStart (capture_ctrl_t * const p_ctrl, uint8_t * const p_buffer) +{ + pdc_instance_ctrl_t * p_instance_ctrl = (pdc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if PDC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + + FSP_ASSERT(p_buffer); + + /* Check driver is open */ + FSP_ERROR_RETURN((PDC_PRV_OPEN == p_instance_ctrl->open), FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_instance_ctrl->p_callback, FSP_ERR_NOT_INITIALIZED); + + /* Check if a transfer is already in progress */ + FSP_ERROR_RETURN((p_instance_ctrl->transfer_in_progress == false), FSP_ERR_IN_USE); +#endif + + pdc_extended_cfg_t * p_extend = (pdc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + uint32_t pccr0_initial_setting = + ((uint32_t) ((uint32_t) (p_extend->clock_division << R_PDC_PCCR0_PCKDIV_Pos) & R_PDC_PCCR0_PCKDIV_Msk)) | + (1U << R_PDC_PCCR0_PCKOE_Pos) | + (1U << R_PDC_PCCR0_PCKE_Pos); + + if (NULL != p_buffer) + { + p_instance_ctrl->p_current_buffer = p_buffer; + } + + /* Reset PDC */ + /* Retain old settings and apply reset */ + R_PDC->PCCR0 = pccr0_initial_setting | (1U << R_PDC_PCCR0_PRST_Pos); + + /* Wait for PDC reset bit (PRST) to clear as described in hardware manual (see + * "PDC Control Register 0 (PCCR0): PRST" description in the relevant hardware manual). + */ + uint32_t timeout = PDC_PERIPHERAL_REG_MAX_WAIT; + PDC_HARDWARE_REGISTER_WAIT(R_PDC->PCCR0, pccr0_initial_setting, timeout); + if (!timeout) + { + return FSP_ERR_TIMEOUT; + } + + /** Set horizontal capture range */ + R_PDC->HCR = + (uint32_t) ((uint32_t) (p_instance_ctrl->p_cfg->x_capture_start_pixel * + p_instance_ctrl->p_cfg->bytes_per_pixel) & + R_PDC_HCR_HST_Msk) | + (uint32_t) ((uint32_t) ((p_instance_ctrl->p_cfg->x_capture_pixels * p_instance_ctrl->p_cfg->bytes_per_pixel) << + 16) & + R_PDC_HCR_HSZ_Msk); + + /** Set vertical capture range */ + R_PDC->VCR = (uint32_t) ((p_instance_ctrl->p_cfg->y_capture_start_pixel) & R_PDC_VCR_VST_Msk) | + (uint32_t) ((uint32_t) ((p_instance_ctrl->p_cfg->y_capture_pixels) << 16) & R_PDC_VCR_VSZ_Msk); + + /** + * Set VSYNC polarity + * Set HSYNC polarity + * Set endianess of capture data + * Enable interrupts + * Receive data ready interrupt, + * Underrun interrupt, + * Overrun interrupt, + * Frame end interrupt, + * Vertical line number setting error interrupt, + * Horizontal byte number setting error interrupt */ + R_PDC->PCCR0 = pccr0_initial_setting | + (uint32_t) (((uint32_t) p_extend->vsync_polarity << R_PDC_PCCR0_VPS_Pos) | + ((uint32_t) p_extend->hsync_polarity << R_PDC_PCCR0_HPS_Pos) | + ((uint32_t) p_extend->endian << R_PDC_PCCR0_EDS_Pos) | + (R_PDC_PCCR0_DFIE_Msk | R_PDC_PCCR0_UDRIE_Msk | R_PDC_PCCR0_OVIE_Msk | + R_PDC_PCCR0_FEIE_Msk | R_PDC_PCCR0_VERIE_Msk | R_PDC_PCCR0_HERIE_Msk)); + + /* Set destination buffer and enable transfer */ + err = p_extend->p_lower_lvl_transfer->p_api->reset(p_extend->p_lower_lvl_transfer->p_ctrl, + p_extend->p_lower_lvl_transfer->p_cfg->p_info->p_src, + p_instance_ctrl->p_current_buffer, + p_instance_ctrl->num_blocks); + FSP_ERROR_RETURN((err == FSP_SUCCESS), err); + + /* Mark transfer as in progress */ + p_instance_ctrl->transfer_in_progress = true; + + /* Set PCCR1.PCE as 1 */ + R_PDC->PCCR1 = 1; + + return FSP_SUCCESS; +} + +/***********************************************************************************************************************//** + * Provides the pdc operating status. + * + * Implements @ref capture_api_t::statusGet. + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION One or more parameters is NULL. + * @retval FSP_ERR_NOT_OPEN Open has not been successfully called. + **************************************************************************************************************************/ +fsp_err_t R_PDC_StatusGet (capture_ctrl_t * const p_ctrl, capture_status_t * p_status) +{ + pdc_instance_ctrl_t * p_instance_ctrl = (pdc_instance_ctrl_t *) p_ctrl; + +#if (PDC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_status); + FSP_ERROR_RETURN(PDC_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + if (p_instance_ctrl->transfer_in_progress) + { + p_status->state = CAPTURE_STATE_IN_PROGRESS; + } + else + { + p_status->state = CAPTURE_STATE_IDLE; + } + + p_status->p_buffer = (uint32_t *) p_instance_ctrl->p_current_buffer; + + p_status->data_size = ((uint32_t) ((p_instance_ctrl->p_cfg->x_capture_pixels - + p_instance_ctrl->p_cfg->x_capture_start_pixel) * + p_instance_ctrl->p_cfg->bytes_per_pixel) + + (uint32_t) ((p_instance_ctrl->p_cfg->y_capture_pixels - + p_instance_ctrl->p_cfg->y_capture_start_pixel) * + p_instance_ctrl->p_cfg->bytes_per_pixel)); + + return FSP_SUCCESS; +} /* End of function R_PDC_StatusGet() */ + +/***********************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * + * Implements @ref capture_api_t::callbackSet. + * + * @retval FSP_ERR_UNSUPPORTED This is just a stub at present + **************************************************************************************************************************/ +fsp_err_t R_PDC_CallbackSet (capture_ctrl_t * const p_ctrl, + void ( * p_callback)(capture_callback_args_t *), + void * const p_context, + capture_callback_args_t * const p_callback_memory) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_context); + FSP_PARAMETER_NOT_USED(p_callback_memory); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup PDC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Internal transfer complete callback for PDC driver. + * + * This is invoked every time a frame has been captured and hence also performs PDC operation flow + * as described in hardware manual (see Figure "Example operation flow" in the PDC section of the + * relevant hardware manual). + * Thus eliminating the need of a separate frame end interrupt and its ISR. + * + * + * @param[in] p_ctrl Pointer to the instance control block. + **********************************************************************************************************************/ +void r_pdc_transfer_callback (pdc_instance_ctrl_t * p_ctrl) +{ + capture_callback_args_t pdc_args; + uint16_t timeout = PDC_PERIPHERAL_REG_MAX_WAIT; + + /* Performs PDC operation flow as described in hardware manual (see + * "Example operation flow" in the PDC section of the relevant hardware manual). + * */ + while ((0UL == (R_PDC_PCSR_FEMPF_Msk & R_PDC->PCSR)) && (0UL != timeout) && + (0UL == (R_PDC_PCSR_UDRF_Msk & R_PDC->PCSR))) + { + /* Wait for FIFO empty flag to be set and DTC/DMAC to transfer last data block.*/ + timeout--; + } + + /* As per the above hardware manual reference the sequence for PDC stop and + * FEF flag clear is reversed for error case but has no impact on the functionality. + */ + + /* Stop the PDC */ + R_PDC->PCCR1 = (uint32_t) 0UL; + + /* Clear FEF frame end flag */ + R_PDC->PCSR &= ~R_PDC_PCSR_FEF_Msk; + + if (0UL != (R_PDC_PCSR_UDRF_Msk & R_PDC->PCSR)) + { + /* Underrun error has occurred */ + + /* Clear FEF frame end flag */ + R_PDC->PCSR &= ~R_PDC_PCSR_FEF_Msk; + + /* Call the error handler */ + r_pdc_error_handler(p_ctrl); + } + + p_ctrl->transfer_in_progress = false; + pdc_args.p_context = p_ctrl; + pdc_args.event = PDC_EVENT_TRANSFER_COMPLETE; + pdc_args.event_status = 0; + pdc_args.interrupt_status = 0; + pdc_args.p_buffer = p_ctrl->p_current_buffer; + p_ctrl->p_callback(&pdc_args); +} + +/*******************************************************************************************************************//** + * Called when a DTC transfer completes. Not used for DMAC. + **********************************************************************************************************************/ +void pdc_transfer_req_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + pdc_instance_ctrl_t * p_ctrl = (pdc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + r_pdc_transfer_callback(p_ctrl); + + /* Clear the IR flag in the ICU. + * This must be after the callback because the next DTC transfer will begin when this bit is cleared. */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * @brief PDC error ISR + **********************************************************************************************************************/ +void pdc_int_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + pdc_instance_ctrl_t * p_ctrl = (pdc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Call the error handler */ + r_pdc_error_handler(p_ctrl); + + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * @brief PDC error handler + * @param[in] p_ctrl Pointer to PDC Specific Control Structure + **********************************************************************************************************************/ +static void r_pdc_error_handler (pdc_instance_ctrl_t * p_ctrl) +{ + capture_callback_args_t pdc_args; + + /* Performs PDC error processing flow as described in hardware manual (see Figure + * "Example error processing flow" in the PDC section of the relevant hardware manual). + * All the errors are consolidated and reported through the callback and the status register + * is cleared in a single write. + * *//* Stop the PDC */ + R_PDC->PCCR1 = (uint32_t) 0UL; + + /* Disable the transfer */ + + ((pdc_extended_cfg_t *) (p_ctrl->p_cfg->p_extend))->p_lower_lvl_transfer->p_api->disable(((pdc_extended_cfg_t *) ( + p_ctrl->p_cfg-> + p_extend))->p_lower_lvl_transfer->p_ctrl); + + /* Report all the errors at once */ + uint32_t event = R_PDC->PCSR; + R_PDC->PCSR = ~event & PDC_PRV_PCSR_MASK; + pdc_args.event = (pdc_event_t) event; + pdc_args.event_status = 0; + pdc_args.interrupt_status = 0; + pdc_args.p_context = p_ctrl->p_context; + p_ctrl->p_callback(&pdc_args); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_pdm/r_pdm.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_pdm/r_pdm.c new file mode 100644 index 0000000000..575f14daf0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_pdm/r_pdm.c @@ -0,0 +1,958 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_pdm.h" +#include "r_pdm_cfg.h" +#if PDM_CFG_DMAC_ENABLE + #include "r_dmac.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define PDM_PRV_PDSCR_CLEAR_MASK (R_PDM_CH_PDSCR_SDFC_Msk | R_PDM_CH_PDSCR_SCDFC_Msk | \ + R_PDM_CH_PDSCR_OVLDFC_Msk | R_PDM_CH_PDSCR_OVUDFC_Msk | \ + R_PDM_CH_PDSCR_BFOWDFC_Msk) +#define PDM_PRV_PDSR_ERROR_MASK (R_PDM_CH_PDSR_SCDF_Msk | R_PDM_CH_PDSR_OVLDF_Msk | \ + R_PDM_CH_PDSR_OVUDF_Msk | \ + R_PDM_CH_PDSR_BFOWDF_Msk) + +#define PDM_PRV_FIFO_SAMPLE_SIZE sizeof(uint32_t) +#define PDM_PRV_FIFO_DEPTH 32 +#define PDM_PRV_FIFO_INITIAL_READ_LENGTH (PDM_PRV_FIFO_DEPTH - 2) + +/* "PDM" in ASCII, used to determine if driver is open. */ +#define PDM_PRV_OPEN (0x50444DU) + +#define PDM_PRV_LOOP_MAX (1000) + +#define PDM_PRV_UNITS (1) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * pdm_prv_ns_callback)(pdm_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile pdm_prv_ns_callback)(pdm_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/* ISRs */ +void pdm_sdet_isr(void); +void pdm_dat_isr(void); +void pdm_err_isr(void); + +static void r_pdm_call_callback(pdm_instance_ctrl_t * p_ctrl, pdm_event_t event, pdm_error_t error); + +/* FIFO subroutines */ +static uint32_t r_pdm_fifo_read(pdm_instance_ctrl_t * p_instance_ctrl); + +#if PDM_CFG_DMAC_ENABLE +static fsp_err_t r_pdm_dependent_drivers_configure(pdm_instance_ctrl_t * p_instance_ctrl); +void pdm_rxi_dmac_isr(dmac_callback_args_t * args); + +#endif + +/* Subroutines */ +static void r_pdm_stop_sub(pdm_instance_ctrl_t * const p_instance_ctrl); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** PDM Implementation of PDM interface. */ +const pdm_api_t g_pdm_on_pdm = +{ + .open = R_PDM_Open, + .start = R_PDM_Start, + .stop = R_PDM_Stop, + .soundDetectionEnable = R_PDM_SoundDetectionEnable, + .soundDetectionDisable = R_PDM_SoundDetectionDisable, + .read = R_PDM_Read, + .statusGet = R_PDM_StatusGet, + .close = R_PDM_Close, + .callbackSet = R_PDM_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup PDM + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens the PDM. Implements @ref pdm_api_t::open. + * + * This function sets this clock divisor and the configurations specified in pdm_cfg_t. + * + * @retval FSP_SUCCESS Ready for PDM communication. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl or p_cfg is null. + * @retval FSP_ERR_ALREADY_OPEN The control block has already been opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel number is not available on this device. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_PDM_Open (pdm_ctrl_t * const p_ctrl, pdm_cfg_t const * const p_cfg) +{ + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) p_ctrl; + +#if PDM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + + FSP_ERROR_RETURN(BSP_PERIPHERAL_PDM_CHANNEL_MASK & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(PDM_PRV_UNITS > p_cfg->unit, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + FSP_ERROR_RETURN(PDM_PRV_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Calculate base address for registers on this channel. */ + R_PDM_CH_Type * p_reg = (R_PDM_CH_Type *) &R_PDM->CH[p_cfg->channel]; + pdm_extended_cfg_t * p_extend = (pdm_extended_cfg_t *) p_cfg->p_extend; + + /* Enable PDM module */ + R_BSP_MODULE_START(FSP_IP_PDM, p_cfg->unit); + + /* Initialize PDM IP according to Figure "PDM-IF Start Flow" in + * in the PDM-IF section of the relevant hardware manual. */ + + /* Set PCM Width */ + uint32_t pdmdsr = (uint32_t) p_cfg->pcm_width << R_PDM_CH_PDMDSR_DBIS_Pos; + + /* Set sinc and moving average order */ + pdmdsr |= (uint32_t) p_extend->sinc_filter_mode << R_PDM_CH_PDMDSR_SFMD_Pos; + pdmdsr |= (uint32_t) p_extend->moving_average_mode << R_PDM_CH_PDMDSR_SDMAMD_Pos; + + /* Set filter shifts */ + pdmdsr |= (uint32_t) p_extend->low_pass_filter_shift << R_PDM_CH_PDMDSR_LFIS_Pos; + pdmdsr |= (uint32_t) p_extend->compensation_filter_shift << R_PDM_CH_PDMDSR_CFIS_Pos; + pdmdsr |= (uint32_t) p_extend->high_pass_filter_shift << R_PDM_CH_PDMDSR_HFIS_Pos; + + /* Set edge detection */ + pdmdsr |= (uint32_t) p_cfg->pcm_edge << R_PDM_CH_PDMDSR_INPSEL_Pos; + + /* Write to PDMDSRCHn */ + p_reg->PDMDSR = pdmdsr; + + /* Set sinc output range */ + uint32_t pdsfcr = (uint32_t) p_extend->sincrng << R_PDM_CH_PDSFCR_SINCRNG_Pos; + + /* Set sinc decimation ratio */ + pdsfcr |= (uint32_t) p_extend->sincdec << R_PDM_CH_PDSFCR_SINCDEC_Pos; + + /* Set PDM_CLK divider */ + pdsfcr |= (uint32_t) p_extend->clock_div << R_PDM_CH_PDSFCR_CKDIV_Pos; + + /* Write to PDSFCRCHn */ + p_reg->PDSFCR = pdsfcr; + + uint8_t i; + + /* Set high pass filter coefficients */ + p_reg->PDHFCS0R = (uint32_t) p_extend->hpf_coefficient_s0; + p_reg->PDHFCK1R = (uint32_t) p_extend->hpf_coefficient_k1; + for (i = 0; i < PDM_NUM_HPF_COEFFICIENT_H; i++) + { + p_reg->PDHFCHR[i] = (uint32_t) p_extend->hpf_coefficient_h[i]; + } + + /* Set compensation filter coefficients */ + for (i = 0; i < PDM_NUM_COMPENSATION_FILTER_COEFFICIENT_H; i++) + { + p_reg->PDCFCHR[i] = (uint32_t) p_extend->compensation_filter_coefficient_h[i]; + } + + /* Set low pass filter coefficients */ + p_reg->PDLFCH010R = (uint32_t) p_extend->lpf_coefficient_h0; + for (i = 0; i < PDM_NUM_LPF_FILTER_COEFFICIENT_H1; i++) + { + p_reg->PDLFCH1R[i] = (uint32_t) p_extend->lpf_coefficient_h1[i]; + } + + /* Set Channel's Data Buffer Control */ + p_reg->PDDBCR = (uint32_t) p_extend->interrupt_threshold; + + /* Set Channel's Error Detection Control */ + p_reg->PDSCTSR = (uint32_t) (p_extend->short_circuit_count_h << R_PDM_CH_PDSCTSR_SCDH_Pos) | + (uint32_t) (p_extend->short_circuit_count_l << R_PDM_CH_PDSCTSR_SCDL_Pos); + p_reg->PDOVLTR = p_extend->overvoltage_detection_lower_limit; + p_reg->PDOVUTR = p_extend->overvoltage_detection_upper_limit; + + /* Activate target channel's filtering */ + p_reg->PDSTRTR = R_PDM_CH_PDSTRTR_STRTRG_Msk; + + /* Clear Channel's Status */ + p_reg->PDSCR = PDM_PRV_PDSCR_CLEAR_MASK; + + /* Set Channel's Status Detection Control (for Error Detection) */ + uint32_t pdsdcr = p_extend->short_circuit_detection_enable; + pdsdcr |= p_extend->over_voltage_lower_limit_detection_enable; + pdsdcr |= p_extend->over_voltage_upper_limit_detection_enable; + pdsdcr |= p_extend->buffer_overwrite_detection_enable; + + p_reg->PDSDCR = pdsdcr; + + /* Initialize the control structure. */ + p_instance_ctrl->p_reg = p_reg; + p_instance_ctrl->p_cfg = p_cfg; + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + /* Initialization complete. */ + p_instance_ctrl->open = PDM_PRV_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts PDM. Implements @ref pdm_api_t::start. + * + * This function enables reception, and enables any transfer instances used. + * + * The PDM will start on the next frame boundary. + * + * @retval FSP_SUCCESS PDM communication stop request issued. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl was null. + * @retval FSP_ERR_INVALID_SIZE The size of buffer is not a multiple of pdm_interrupt_threshold_t. + * @retval FSP_ERR_INVALID_ALIGNMENT The alignment of argument buffer_size is not matched with hardware specification. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @return See @ref RENESAS_ERROR_CODES or lower level drivers for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_PDM_Start (pdm_ctrl_t * const p_ctrl, + void * const p_buffer, + size_t const buffer_size, + uint32_t const number_of_data_to_callback) +{ + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) p_ctrl; + +#if PDM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(NULL != p_buffer, FSP_ERR_ASSERTION); + FSP_ERROR_RETURN(PDM_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(buffer_size > 0U); + FSP_ASSERT(number_of_data_to_callback > 0U); +#endif + pdm_extended_cfg_t * p_extend = (pdm_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; +#if PDM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_extend); +#endif + + R_PDM_CH_Type * p_reg = p_instance_ctrl->p_reg; + pdm_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + uint32_t stages_per_interrupt = 1U << p_extend->interrupt_threshold; + + /* Verify that the buffer is aligned to 4 bytes. */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buffer & 0x03U)), FSP_ERR_INVALID_ALIGNMENT); + + /* Verify that number_of_data_to_callback is a multiple of configured interrupt threshold which determines the + * number of stages per interrupt */ + FSP_ERROR_RETURN((0 == (number_of_data_to_callback % stages_per_interrupt)), FSP_ERR_INVALID_SIZE); + + /* Verify that buffer size is a multiple of 4 bytes */ + FSP_ERROR_RETURN((0 == buffer_size % PDM_PRV_FIFO_SAMPLE_SIZE), FSP_ERR_INVALID_SIZE); + + /* Verify that number of samples in buffer is a multiple of the number of data to callback */ + uint32_t number_of_samples_in_buffer = buffer_size / PDM_PRV_FIFO_SAMPLE_SIZE; + FSP_ERROR_RETURN((0 == (number_of_samples_in_buffer % number_of_data_to_callback)), FSP_ERR_INVALID_SIZE); + + p_instance_ctrl->p_rx_dest = p_buffer; + p_instance_ctrl->p_read = p_buffer; + p_instance_ctrl->rx_dest_samples = number_of_samples_in_buffer; + p_instance_ctrl->rx_int_count = 0; + p_instance_ctrl->rx_int_count_max = number_of_data_to_callback; + + /* Start communication according to Figure "PDM-IF normal processing flow" in + * "Normal Processing Flow" of the relevant hardware manual. */ + + /* Set Channel's Data Read Enable */ + p_reg->PDDRCR = R_PDM_CH_PDDRCR_DATRE_Msk; + + /* Read PDDRR x (P_FD - 2) before starting interrupts/DMA + * P_FD: FIFO Depth + * Note: this data discarded and not stored anywhere + */ + for (int i = 0; i < PDM_PRV_FIFO_INITIAL_READ_LENGTH; i++) + { + FSP_REGISTER_READ(p_reg->PDDRR); + } + +#if PDM_CFG_DMAC_ENABLE + + /* Configure dependent timer and transfer drivers. */ + fsp_err_t err = r_pdm_dependent_drivers_configure(p_instance_ctrl); + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); +#endif + + /* Enable error interrupt if allocated and not already enabled */ + if ((p_cfg->err_irq >= 0) && (0 == p_reg->PDICR_b.IEDE)) + { + p_reg->PDICR_b.IEDE = 1; + R_BSP_IrqCfgEnable(p_cfg->err_irq, p_cfg->err_ipl, p_instance_ctrl); + } + + /* Enable data interrupt */ + p_reg->PDICR |= R_PDM_CH_PDICR_IDRE_Msk; + + if (p_cfg->dat_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->dat_irq, p_cfg->dat_ipl, p_instance_ctrl); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops PDM. Implements @ref pdm_api_t::stop. + * + * This function disables reception, and disables any transfer instances used. + * + * The PDM will stop on the next frame boundary. + * + * @retval FSP_SUCCESS PDM communication stop request issued. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @return See @ref RENESAS_ERROR_CODES or lower level drivers for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_PDM_Stop (pdm_ctrl_t * const p_ctrl) +{ + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) p_ctrl; + +#if PDM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(PDM_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + r_pdm_stop_sub(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures and enables sound detection. Implements @ref pdm_api_t::soundDetectionEnable. + * + * This function configures sound detection based on the passed in settings. It then enables sound detection. + * + * @retval FSP_SUCCESS Sound detection configured and enabled. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @return See @ref RENESAS_ERROR_CODES or lower level drivers for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_PDM_SoundDetectionEnable (pdm_ctrl_t * const p_ctrl, pdm_sound_detection_setting_t sound_detection_setting) +{ + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) p_ctrl; + +#if PDM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(PDM_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + pdm_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + R_PDM_CH_Type * p_reg = p_instance_ctrl->p_reg; + + /* Enable error interrupt if allocated and not already enabled */ + if ((p_cfg->err_irq >= 0) && (0 == p_reg->PDICR_b.IEDE)) + { + p_reg->PDICR_b.IEDE = 1; + R_BSP_IrqCfgEnable(p_cfg->err_irq, p_cfg->err_ipl, p_instance_ctrl); + } + + /* Clear sound detection status */ + p_reg->PDSCR_b.SDFC = 1; + + /* Set Channel's Sound Detection Control */ + p_reg->PDSDLTR = sound_detection_setting.sound_detection_lower_limit; + p_reg->PDSDUTR = sound_detection_setting.sound_detection_upper_limit; + + /* Set sound detection enable */ + p_reg->PDSDCR_b.SDE = 1; + + /* Enable sound detection interrupt if used */ + if (p_cfg->sdet_irq >= 0) + { + p_reg->PDICR_b.ISDE = 1; + R_BSP_IrqCfgEnable(p_cfg->sdet_irq, p_cfg->sdet_ipl, p_instance_ctrl); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables sound detection. Implements @ref pdm_api_t::soundDetectionDisable. + * + * This function disables sound detection. + * + * @retval FSP_SUCCESS Sound detection disabled. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @return See @ref RENESAS_ERROR_CODES or lower level drivers for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_PDM_SoundDetectionDisable (pdm_ctrl_t * const p_ctrl) +{ + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) p_ctrl; + +#if PDM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(PDM_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + pdm_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + R_PDM_CH_Type * p_reg = p_instance_ctrl->p_reg; + + /* Clear sound detection enable */ + p_reg->PDSDCR_b.SDE = 0; + + /* Disable sound detection interrupt if used */ + if (p_cfg->sdet_irq >= 0) + { + p_reg->PDICR_b.ISDE = 0; + } + + /* Clear sound detection status */ + p_reg->PDSCR_b.SDFC = 1; + + /* Disable error interrupt if allocated and if data read isn't enabled */ + if ((p_cfg->err_irq >= 0) && (0 == p_reg->PDDRCR)) + { + p_reg->PDICR_b.IEDE = 0; + R_BSP_IrqDisable(p_cfg->err_irq); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function is not supported. Implements @ref pdm_api_t::read. + * + * @retval FSP_ERR_UNSUPPORTED This function is not supported. + **********************************************************************************************************************/ +fsp_err_t R_PDM_Read (pdm_ctrl_t * const p_ctrl, void * const p_dest, uint32_t const bytes) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Gets PDM status and stores it in provided pointer p_status. Implements @ref pdm_api_t::statusGet. + * + * Calling this function will clear any set error flags in the hardware. + * + * @retval FSP_SUCCESS Information stored successfully. + * @retval FSP_ERR_ASSERTION The p_ctrl or p_status parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_PDM_StatusGet (pdm_ctrl_t * const p_ctrl, pdm_status_t * const p_status) +{ + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) p_ctrl; + +#if PDM_CFG_PARAM_CHECKING_ENABLE + + /* Make sure parameters are valid. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(PDM_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + R_PDM_CH_Type * p_reg = p_instance_ctrl->p_reg; + + /* Set state based on if data read is enabled */ + p_status->state = p_reg->PDDRCR ? PDM_STATE_IN_USE : PDM_STATE_STOPPED; + + /* Set sound detection state */ + p_status->sound_detection_enabled = (0 != p_reg->PDICR_b.ISDE); + + /* Get status, mask out non-error statuses */ + uint32_t pdsr = p_instance_ctrl->p_reg->PDSR & PDM_PRV_PDSR_ERROR_MASK; + + /* Set errors, shift so that error statuses match the error enum*/ + p_status->error = (pdm_error_t) (pdsr >> R_PDM_CH_PDSCR_SCDFC_Pos); + + /* Clear set error flags */ + p_instance_ctrl->p_reg->PDSCR = pdsr; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes PDM. Implements @ref pdm_api_t::close. + * + * This function powers down the PDM and closes the lower level timer and transfer drivers if they are used. + * + * @retval FSP_SUCCESS Device closed successfully. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_PDM_Close (pdm_ctrl_t * const p_ctrl) +{ + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) p_ctrl; + +#if PDM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(PDM_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + pdm_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + R_PDM_CH_Type * p_reg = p_instance_ctrl->p_reg; + + r_pdm_stop_sub(p_instance_ctrl); + + /* Stop PDM according to Figure "PDM-IF Stop Flow" in + * "Stop Flow" of the relevant hardware manual. */ + + /* Stop target channel's filtering */ + p_reg->PDSTPTR = R_PDM_CH_PDSTPTR_STPTRG_Msk; + + /* Target channel is stopped? */ + for (uint32_t loop = 0; loop < PDM_PRV_LOOP_MAX; loop++) + { + if (!(p_reg->PDSR & R_PDM_CH_PDSR_STATE_Msk)) + { + break; + } + } + + /* Disable Channel's Interrupt */ + p_reg->PDICR &= ~(R_PDM_CH_PDICR_ISDE_Msk | R_PDM_CH_PDICR_IEDE_Msk); + + /* Disable Channel's Status Detection */ + p_reg->PDSDCR = 0; + + /* Clear Channel's Status */ + p_reg->PDSCR = PDM_PRV_PDSCR_CLEAR_MASK; + + p_instance_ctrl->open = 0U; + + /* Disable interrupts. */ + if (p_cfg->dat_irq >= 0) + { + R_BSP_IrqDisable(p_cfg->dat_irq); + } + + if (p_cfg->sdet_irq >= 0) + { + R_BSP_IrqDisable(p_cfg->sdet_irq); + } + + if (p_cfg->err_irq >= 0) + { + R_BSP_IrqDisable(p_cfg->err_irq); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements pdm_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_PDM_CallbackSet (pdm_ctrl_t * const p_ctrl, + void ( * p_callback)(pdm_callback_args_t *), + void * const p_context, + pdm_callback_args_t * const p_callback_memory) +{ + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) p_ctrl; + +#if (PDM_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(PDM_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if PDM_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + pdm_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(pdm_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup R_PDM) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if PDM_CFG_DMAC_ENABLE + +/*********************************************************************************************************************** + * Configures any dependent drivers selected by the user, including transfer and timer drivers. + * + * @param[in] p_instance_ctrl Pointer to the p_instance_ctrl structure. + * + * @retval FSP_SUCCESS Dependent drivers configured successfully. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +static fsp_err_t r_pdm_dependent_drivers_configure (pdm_instance_ctrl_t * p_instance_ctrl) +{ + /* Prepare transfer configuration. */ + fsp_err_t err_transfer_rx = FSP_SUCCESS; + pdm_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + R_PDM_CH_Type * p_reg = p_instance_ctrl->p_reg; + pdm_extended_cfg_t * p_extend = (pdm_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + transfer_instance_t * p_transfer_rx = (transfer_instance_t *) p_cfg->p_transfer_rx; + + /* If a transfer instance is provided for read, open the transfer instance. */ + if (NULL != p_transfer_rx) + { + transfer_info_t * p_transfer_info = p_transfer_rx->p_cfg->p_info; + uint32_t * p_data_end = p_instance_ctrl->p_rx_dest; + p_data_end += p_instance_ctrl->rx_dest_samples; + + /* Configure transfer src, dest, and length */ + p_transfer_info->p_src = (void *) &p_reg->PDDRR; + p_transfer_info->p_dest = p_instance_ctrl->p_rx_dest; + p_transfer_info->transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + p_transfer_info->transfer_settings_word_b.mode = TRANSFER_MODE_BLOCK; + p_transfer_info->transfer_settings_word_b.irq = TRANSFER_IRQ_END; + p_transfer_info->length = (uint16_t) (1U << p_extend->interrupt_threshold); + p_transfer_info->num_blocks = (uint16_t) p_instance_ctrl->rx_int_count_max / + (1U << p_extend->interrupt_threshold); + + /* Calculate next transfer destination, if the next transfer will go past + * the end of the buffer then start the next transfer at the beginning of the buffer */ + p_instance_ctrl->p_read = + (void *) ((uint32_t *) p_instance_ctrl->p_read + p_instance_ctrl->rx_int_count_max); + + if (p_instance_ctrl->p_read >= (void *) p_data_end) + { + p_instance_ctrl->p_read = p_instance_ctrl->p_rx_dest; + } + + err_transfer_rx = p_transfer_rx->p_api->open(p_cfg->p_transfer_rx->p_ctrl, p_cfg->p_transfer_rx->p_cfg); + FSP_ERROR_RETURN((FSP_SUCCESS == err_transfer_rx), err_transfer_rx); + + err_transfer_rx = p_transfer_rx->p_api->enable(p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN((FSP_SUCCESS == err_transfer_rx), err_transfer_rx); + } + + return FSP_SUCCESS; +} + +#endif + +/*********************************************************************************************************************** + * Disables PDM reception. + * + * @param[in] p_instance_ctrl Pointer to the control block. + **********************************************************************************************************************/ +static void r_pdm_stop_sub (pdm_instance_ctrl_t * const p_instance_ctrl) +{ + /* Stop communication according to Figure "PDM-IF normal processing flow" in + * "Normal Processing Flow" of the relevant hardware manual. */ + R_PDM_CH_Type * p_reg = p_instance_ctrl->p_reg; + pdm_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + + /* Only stop if data read is currently enabled */ + if (p_reg->PDDRCR) + { + /* Disable channel data interrupt. */ + p_reg->PDICR_b.IDRE = 0; + + /* Disable Channel's Data Read. */ + p_reg->PDDRCR = 0; + +#if PDM_CFG_DMAC_ENABLE + transfer_instance_t * p_transfer_rx = (transfer_instance_t *) p_instance_ctrl->p_cfg->p_transfer_rx; + + /* If transfer is used, disable transfer when stop is requested. */ + if (NULL != p_transfer_rx) + { + fsp_err_t err = p_transfer_rx->p_api->close(p_transfer_rx->p_ctrl); + + /* Return from close is only used for error log */ + FSP_PARAMETER_NOT_USED(err); + FSP_ERROR_LOG(err); + } +#endif + + /* Disable error interrupt if allocated and if sound detection isn't enabled */ + if ((p_cfg->err_irq >= 0) && (0 == p_reg->PDSDCR_b.SDE)) + { + p_reg->PDICR_b.IEDE = 0; + R_BSP_IrqDisable(p_cfg->err_irq); + } + } +} + +/*********************************************************************************************************************** + * Reads data from FIFO. + * + * @param[in] p_instance_ctrl Pointer to the control block. + * @return The number of received data. + **********************************************************************************************************************/ +static uint32_t r_pdm_fifo_read (pdm_instance_ctrl_t * p_instance_ctrl) +{ + /* Calculate the number of available bytes of data in receive FIFO. */ + uint32_t count; + + uint32_t * p_data_end = p_instance_ctrl->p_rx_dest; + p_data_end += p_instance_ctrl->rx_dest_samples; + uint32_t * p_data = p_instance_ctrl->p_read; + uint32_t fifo_number = p_instance_ctrl->p_reg->PDDSR; + for (count = 0; count < fifo_number; count++) + { + *p_data++ = p_instance_ctrl->p_reg->PDDRR; + if (p_data >= p_data_end) + { + p_data = p_instance_ctrl->p_rx_dest; + count++; + break; + } + } + + p_instance_ctrl->p_read = p_data; + + return count; +} + +/*********************************************************************************************************************** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to PDM instance control block + * @param[in] event Event code + * @param[in] error Error code + **********************************************************************************************************************/ +static void r_pdm_call_callback (pdm_instance_ctrl_t * p_ctrl, pdm_event_t event, pdm_error_t error) +{ + pdm_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + pdm_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + p_args->error = error; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + pdm_prv_ns_callback p_callback = (pdm_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*********************************************************************************************************************** + * Sound detection ISR. Calls callback and disables Sound detection interrupt. + **********************************************************************************************************************/ +void pdm_sdet_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Disable Sound detection */ + p_instance_ctrl->p_reg->PDSDCR &= ~R_PDM_CH_PDSDCR_SDE_Msk; + + /* Clear Sound detection flag */ + p_instance_ctrl->p_reg->PDSCR = R_PDM_CH_PDSCR_SDFC_Msk; + + /* Call callback if provided with sound detection event */ + if (p_instance_ctrl->p_callback) + { + r_pdm_call_callback(p_instance_ctrl, PDM_EVENT_SOUND_DETECTION, PDM_ERROR_NONE); + } + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + /* Enable Sound detection */ + p_instance_ctrl->p_reg->PDSDCR |= R_PDM_CH_PDSDCR_SDE_Msk; + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*********************************************************************************************************************** + * Receive ISR. Calls callback when reception is complete. Empties FIFO if transfer interface is not used. + **********************************************************************************************************************/ +void pdm_dat_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + if (NULL != p_instance_ctrl->p_rx_dest) + { + uint32_t received; + + /* If transfer is not used, read data into the destination buffer. */ + received = r_pdm_fifo_read(p_instance_ctrl); + p_instance_ctrl->rx_int_count += received; + while (p_instance_ctrl->rx_int_count >= p_instance_ctrl->rx_int_count_max) + { + p_instance_ctrl->rx_int_count -= p_instance_ctrl->rx_int_count_max; + if (p_instance_ctrl->p_callback) + { + r_pdm_call_callback(p_instance_ctrl, PDM_EVENT_DATA, PDM_ERROR_NONE); + } + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*********************************************************************************************************************** + * Error ISR. + * + * Handles errors and calls callback. + **********************************************************************************************************************/ +void pdm_err_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + pdm_error_t error = PDM_ERROR_NONE; + + /* Get status, mask out non-error statuses */ + uint32_t pdsr = p_instance_ctrl->p_reg->PDSR & PDM_PRV_PDSR_ERROR_MASK; + + /* Set error for callback, shift so that error statuses match the error enum*/ + error = (pdm_error_t) (pdsr >> R_PDM_CH_PDSCR_SCDFC_Pos); + + /* Clear set error flags */ + p_instance_ctrl->p_reg->PDSCR = pdsr; + + if (p_instance_ctrl->p_callback) + { + /* Call callback if provided. */ + r_pdm_call_callback(p_instance_ctrl, PDM_EVENT_ERROR, error); + } + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#if PDM_CFG_DMAC_ENABLE + +/*********************************************************************************************************************** + * Dedicated function for DMAC linkage at the time of reception. + **********************************************************************************************************************/ +void pdm_rxi_dmac_isr (dmac_callback_args_t * args) +{ + if (NULL != args) + { + pdm_instance_ctrl_t * p_instance_ctrl = (pdm_instance_ctrl_t *) args->p_context; + + if ((NULL != p_instance_ctrl) && (p_instance_ctrl->p_callback)) + { + pdm_extended_cfg_t * p_extend = (pdm_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + transfer_instance_t * p_transfer_rx = (transfer_instance_t *) p_instance_ctrl->p_cfg->p_transfer_rx; + + /* Set new destination for next transfer, reset block count */ + p_transfer_rx->p_api->reset(p_transfer_rx->p_ctrl, + (void *) &p_instance_ctrl->p_reg->PDDRR, + p_instance_ctrl->p_read, + (uint16_t) p_instance_ctrl->rx_int_count_max / + (1U << p_extend->interrupt_threshold)); + + /* Calculate the next destination */ + p_instance_ctrl->p_read = + (void *) ((uint32_t *) p_instance_ctrl->p_read + p_instance_ctrl->rx_int_count_max); + + uint32_t * p_data_end = p_instance_ctrl->p_rx_dest; + p_data_end += p_instance_ctrl->rx_dest_samples; + + if (p_instance_ctrl->p_read >= (void *) p_data_end) + { + p_instance_ctrl->p_read = p_instance_ctrl->p_rx_dest; + } + + /* Call callback function */ + r_pdm_call_callback(p_instance_ctrl, PDM_EVENT_DATA, PDM_ERROR_NONE); + } + } +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_poeg/r_poeg.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_poeg/r_poeg.c new file mode 100644 index 0000000000..5ff0e46468 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_poeg/r_poeg.c @@ -0,0 +1,367 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_poeg.h" +#include "r_poeg_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "POEG" in ASCII, used to determine if channel is open. */ +#define POEG_OPEN (0x00475054ULL) + +#if BSP_FEATURE_POEG_HAS_POEGG_DERRST + #define POEG_PRV_STATUS_FLAGS (R_GPT_POEG0_POEGG_ST_Msk | R_GPT_POEG0_POEGG_SSF_Msk | \ + R_GPT_POEG0_POEGG_OSTPF_Msk | R_GPT_POEG0_POEGG_IOCF_Msk | \ + R_GPT_POEG0_POEGG_PIDF_Msk | R_GPT_POEG0_POEGG_DERR0ST_Msk | \ + R_GPT_POEG0_POEGG_DERR1ST_Msk) +#else + #define POEG_PRV_STATUS_FLAGS (R_GPT_POEG0_POEGG_ST_Msk | R_GPT_POEG0_POEGG_SSF_Msk | \ + R_GPT_POEG0_POEGG_OSTPF_Msk | R_GPT_POEG0_POEGG_IOCF_Msk | \ + R_GPT_POEG0_POEGG_PIDF_Msk) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * poeg_prv_ns_callback)(poeg_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile poeg_prv_ns_callback)(poeg_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void poeg_event_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* POEG implementation of POEG interface */ +const poeg_api_t g_poeg_on_poeg = +{ + .open = R_POEG_Open, + .reset = R_POEG_Reset, + .outputDisable = R_POEG_OutputDisable, + .statusGet = R_POEG_StatusGet, + .callbackSet = R_POEG_CallbackSet, + .close = R_POEG_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup POEG + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the POEG module and applies configurations. Implements @ref poeg_api_t::open. + * + * @note The @ref poeg_cfg_t::trigger setting can only be configured once after reset. Reopening with a different trigger + * configuration is not possible. + * + * Example: + * @snippet r_poeg_example.c R_POEG_Open + * + * @retval FSP_SUCCESS Initialization was successful. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the source divider is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED poeg_cfg_t::p_callback is not NULL, but ISR is not enabled. ISR must be + * enabled to use callback. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_POEG_Open (poeg_ctrl_t * const p_ctrl, poeg_cfg_t const * const p_cfg) +{ + poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) p_ctrl; +#if POEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(POEG_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(((1U << p_cfg->channel) & BSP_FEATURE_POEG_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + if (p_cfg->p_callback) + { + FSP_ERROR_RETURN(p_cfg->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + if (p_cfg->irq >= 0) + { + FSP_ASSERT(NULL != p_cfg->p_callback); + } +#endif + + /* Save register base address. */ + uint32_t base_address = (uint32_t) R_GPT_POEG0 + + (p_cfg->channel * ((uint32_t) R_GPT_POEG1 - (uint32_t) R_GPT_POEG0)); + p_instance_ctrl->p_reg = (R_GPT_POEG0_Type *) base_address; + p_instance_ctrl->p_cfg = p_cfg; + + /* Power on POEG before setting any hardware registers. */ + R_BSP_MODULE_START(FSP_IP_POEG, p_cfg->channel); + + /* Configure the POEGG register. */ + p_instance_ctrl->p_reg->POEGG = ((uint32_t) p_cfg->trigger << R_GPT_POEG0_POEGG_PIDE_Pos) | + ((uint32_t) p_cfg->polarity << R_GPT_POEG0_POEGG_INV_Pos) | + ((uint32_t) p_cfg->noise_filter << R_GPT_POEG0_POEGG_NFEN_Pos); + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + /* Make sure the module is marked open before enabling the interrupt since the interrupt could fire immediately. */ + p_instance_ctrl->open = POEG_OPEN; + + /* Configure interrupt. */ + if (p_cfg->irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->irq, p_cfg->ipl, p_instance_ctrl); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables GPT output pins. Implements @ref poeg_api_t::outputDisable. + * + * @retval FSP_SUCCESS GPT output pins successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_POEG_OutputDisable (poeg_ctrl_t * const p_ctrl) +{ + poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) p_ctrl; +#if POEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(POEG_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disable GPT output pins. */ + p_instance_ctrl->p_reg->POEGG_b.SSF = 1U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets status flags. Implements @ref poeg_api_t::reset. + * + * @note Status flags are only reset if the original POEG trigger is resolved. Check the status using + * @ref R_POEG_StatusGet after calling this function to verify the status is cleared. + * + * Example: + * @snippet r_poeg_example.c R_POEG_Reset + * + * @retval FSP_SUCCESS Function attempted to clear status flags. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_POEG_Reset (poeg_ctrl_t * const p_ctrl) +{ + poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) p_ctrl; +#if POEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(POEG_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Reset POEG status flags. */ + p_instance_ctrl->p_reg->POEGG &= ~POEG_PRV_STATUS_FLAGS; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get current POEG status and store it in provided pointer p_status. Implements @ref poeg_api_t::statusGet. + * + * Example: + * @snippet r_poeg_example.c R_POEG_StatusGet + * + * @retval FSP_SUCCESS Current POEG state stored successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_POEG_StatusGet (poeg_ctrl_t * const p_ctrl, poeg_status_t * const p_status) +{ + poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) p_ctrl; +#if POEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(POEG_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Get POEG state. */ + p_status->state = (poeg_state_t) (p_instance_ctrl->p_reg->POEGG & POEG_PRV_STATUS_FLAGS); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref poeg_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_POEG_CallbackSet (poeg_ctrl_t * const p_ctrl, + void ( * p_callback)(poeg_callback_args_t *), + void * const p_context, + poeg_callback_args_t * const p_callback_memory) +{ + poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) p_ctrl; + +#if POEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(POEG_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if POEG_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + poeg_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(poeg_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables POEG interrupt. Implements @ref poeg_api_t::close. + * + * @note This function does not disable the POEG. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_POEG_Close (poeg_ctrl_t * const p_ctrl) +{ + poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) p_ctrl; + +#if POEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(POEG_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disable interrupts. */ + if (p_instance_ctrl->p_cfg->irq >= 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->irq, NULL); + } + + /* Clear open flag. */ + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/** @} (end addtogroup POEG) */ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Notifies user of POEG event. + **********************************************************************************************************************/ +void poeg_event_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + poeg_callback_args_t args; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + volatile poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + poeg_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_instance_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + poeg_prv_ns_callback p_callback = (poeg_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting. This is a level interrupt, so it must be + * cleared at the end of the ISR. */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_edmac/r_edmac.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_edmac/r_edmac.c new file mode 100644 index 0000000000..c042515fef --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_edmac/r_edmac.c @@ -0,0 +1,293 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "r_edmac.h" +#include "r_ptp_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define EDMAC_OPEN (0x45444D41U) +#define EDMAC_PCLKA_RESET_CYCLES (64U) +#define EDMAC_FDR_VALUE (0x0000070FU) +#define EDMAC_DESC_STATUS_ACTIVE (1U << 31U) +#define EDMAC_TDLE (1U << 30U) +#define EDMAC_TD0_TFP0 (1U << 28U) +#define EDMAC_TD0_TFP1 (1U << 29U) + +/*********************************************************************************************************************** + * Private function declarations + **********************************************************************************************************************/ +void r_edmac_hw_reset(edmac_instance_ctrl_t * p_ctrl); + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This function initializes the EDMAC instance. + * + * This function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Initialize the buffer descriptor lists to a known state. + * - Write EDMAC configuration settings to registers. + * - Initialize the control structure for use in other. + * + * @retval FSP_SUCCESS The instance has been successfully configured. + * @retval FSP_ERR_ASSERTION An invalid argument was given in the configuration structure. + * @retval FSP_ERR_ALREADY_OPEN The EDMAC instance is already opened. + **********************************************************************************************************************/ +fsp_err_t R_EDMAC_Open (edmac_instance_ctrl_t * const p_ctrl, edmac_cfg_t const * const p_cfg) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(EDMAC_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(p_cfg->edmac_irq >= 0); + FSP_ASSERT(0 < p_cfg->num_rx_desc); + FSP_ASSERT(0 < p_cfg->num_tx_desc); + FSP_ASSERT(NULL != p_cfg->p_rx_descriptors); + FSP_ASSERT(NULL != p_cfg->p_tx_descriptors); +#endif + + p_ctrl->p_reg = NULL; + if (PTPC_EDMAC_CHANNEL == p_cfg->channel) + { + p_ctrl->p_reg = R_PTP_EDMAC; + } + else if (ETHERC_EDMAC_CHANNEL == p_cfg->channel) + { + p_ctrl->p_reg = R_ETHERC_EDMAC; + } + else + { + return FSP_ERR_ASSERTION; + } + + /* Mark the driver as open. */ + p_ctrl->open = EDMAC_OPEN; + + /* Save the configuration structure. */ + p_ctrl->p_cfg = p_cfg; + + /* Clear the rx an tx descriptor lists. */ + memset(p_cfg->p_rx_descriptors, 0U, p_cfg->num_rx_desc * sizeof(edmac_desc_t)); + memset(p_cfg->p_tx_descriptors, 0U, p_cfg->num_tx_desc * sizeof(edmac_desc_t)); + + /* + * TBL must be set to a value greater than or equal to 1 + * (See "Transmit descriptor" in the EDMAC section of the relevant hardware manual). + */ + for (uint32_t i = 0; i < p_cfg->num_tx_desc; i++) + { + p_cfg->p_tx_descriptors[i].buffer_size = 1; + } + + /* Mark the last descriptor in the tx and rx descriptor lists. */ + p_cfg->p_rx_descriptors[p_cfg->num_rx_desc - 1U].status.raw = EDMAC_TDLE; + p_cfg->p_tx_descriptors[p_cfg->num_tx_desc - 1U].status.raw = EDMAC_TDLE; + + /* Reset the EDMAC peripheral. */ + r_edmac_hw_reset(p_ctrl); + + /* Set little endian mode. */ + p_ctrl->p_reg->EDMR = R_ETHERC_EDMAC_EDMR_DE_Msk; + + /* Set pointer to transmit descriptor list. */ + p_ctrl->p_reg->TDLAR = (uint32_t) p_cfg->p_tx_descriptors; + + /* Set pointer to receive descriptor list. */ + p_ctrl->p_reg->RDLAR = (uint32_t) p_cfg->p_rx_descriptors; + + /* + * Set the fifo depth register according to the hardware manual + * (Reference "FIFO Depth Register (FDR)" in the EDMAC section of the relevant hardware manual). + */ + p_ctrl->p_reg->FDR = EDMAC_FDR_VALUE; + + /* Set RNR so that the EDRRR.RR is not cleared after receiving a single ethernet frame. */ + p_ctrl->p_reg->RMCR = 1U; + + /* Enable the frame receive interrupt request and frame transfer complete interrupt request. */ + p_ctrl->p_reg->EESIPR = R_ETHERC_EDMAC_EESIPR_FRIP_Msk | R_ETHERC_EDMAC_EESIPR_TCIP_Msk; + + /* Enable the EDMAC interrupt. */ + R_BSP_IrqCfgEnable(p_cfg->edmac_irq, p_cfg->edmac_ipl, p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the buffer address of a descriptor. + * If it is a reveive descriptor, re-enable receive requests. + * If it is a transmit descriptor, re-enable transmit requests. + * + * @retval FSP_SUCCESS The buffer descriptor has been updated. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument is invalid or NULL. + **********************************************************************************************************************/ +fsp_err_t R_EDMAC_DescriptorUpdate (edmac_instance_ctrl_t * const p_ctrl, + edmac_desc_type_t type, + uint32_t index, + uint8_t * const p_buffer, + uint16_t length) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(EDMAC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_buffer); + FSP_ASSERT(0 < length); + + if (EDMAC_DESC_RECEIVE == type) + { + FSP_ASSERT(index < p_ctrl->p_cfg->num_rx_desc); + } + else + { + FSP_ASSERT(index < p_ctrl->p_cfg->num_tx_desc); + } +#endif + + if (EDMAC_DESC_RECEIVE == type) + { + p_ctrl->p_cfg->p_rx_descriptors[index].p_buffer = p_buffer; + p_ctrl->p_cfg->p_rx_descriptors[index].buffer_size = length; + p_ctrl->p_cfg->p_rx_descriptors[index].status.raw &= EDMAC_TDLE; + p_ctrl->p_cfg->p_rx_descriptors[index].status.raw_b.active = 1U; + + /* Re-enable the receive request register in case it was cleared. */ + if (0U == p_ctrl->p_reg->EDRRR) + { + p_ctrl->p_reg->EDRRR = 1U; + } + } + else + { + p_ctrl->p_cfg->p_tx_descriptors[index].p_buffer = p_buffer; + p_ctrl->p_cfg->p_tx_descriptors[index].buffer_size = length; + p_ctrl->p_cfg->p_tx_descriptors[index].status.raw &= EDMAC_TDLE; + p_ctrl->p_cfg->p_tx_descriptors[index].status.raw |= EDMAC_DESC_STATUS_ACTIVE | EDMAC_TD0_TFP1 | EDMAC_TD0_TFP0; + + /* Re-enable the transmit request register in case it was cleared. */ + if (0U == p_ctrl->p_reg->EDTRR) + { + p_ctrl->p_reg->EDTRR = 1U; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get a pointer to a descriptor. + * + * @retval FSP_SUCCESS The address of the descriptor at the index has been written to p_desc. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument is invalid or NULL. + **********************************************************************************************************************/ +fsp_err_t R_EDMAC_DescriptorGet (edmac_instance_ctrl_t * const p_ctrl, + edmac_desc_type_t type, + uint32_t index, + edmac_desc_t ** const p_desc) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(EDMAC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_desc); + if (EDMAC_DESC_RECEIVE == type) + { + FSP_ASSERT(index < p_ctrl->p_cfg->num_rx_desc); + } + else + { + FSP_ASSERT(index < p_ctrl->p_cfg->num_tx_desc); + } +#endif + + if (EDMAC_DESC_RECEIVE == type) + { + *p_desc = &p_ctrl->p_cfg->p_rx_descriptors[index]; + } + else + { + *p_desc = &p_ctrl->p_cfg->p_tx_descriptors[index]; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable an EDMAC instance and mark it as closed. + * + * @retval FSP_SUCCESS The instance has been closed. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument is invalid or NULL. + **********************************************************************************************************************/ +fsp_err_t R_EDMAC_Close (edmac_instance_ctrl_t * const p_ctrl) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(EDMAC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Reset the EDMAC peripheral. */ + r_edmac_hw_reset(p_ctrl); + + /* Disable the EDMAC interrupt. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->edmac_irq); + + /* Mark the driver as close. */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +void r_edmac_hw_reset (edmac_instance_ctrl_t * p_ctrl) +{ + /* Reset the EDMAC peripheral. */ + p_ctrl->p_reg->EDMR = 1U; + + uint32_t pclka_freq = SystemCoreClock << R_SYSTEM->SCKDIVCR_b.ICK; + pclka_freq >>= R_SYSTEM->SCKDIVCR_b.PCKA; + + uint32_t delay_microseconds = EDMAC_PCLKA_RESET_CYCLES * BSP_DELAY_UNITS_SECONDS / pclka_freq + 1U; + + /* Wait 64 cycles of PCLKA for the EDMAC peripheral to reset + * (See section "EDMAC Mode Register (EDMR)" description of the relevant hardware manual). */ + R_BSP_SoftwareDelay(delay_microseconds, BSP_DELAY_UNITS_MICROSECONDS); +} + +void edmac_eint_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + edmac_instance_ctrl_t * p_instance_ctrl = (edmac_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + edmac_callback_args_t callback_args; + + /* Read the status flags. */ + callback_args.status = p_instance_ctrl->p_reg->EESR; + + /* Clear all status flags. */ + p_instance_ctrl->p_reg->EESR = callback_args.status; + + callback_args.p_context = p_instance_ctrl->p_cfg->p_context; + + /* Call user callback. */ + p_instance_ctrl->p_cfg->p_callback(&callback_args); + + /* Clear interrupt request. */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_edmac/r_edmac.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_edmac/r_edmac.h new file mode 100644 index 0000000000..37ea40c9ce --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_edmac/r_edmac.h @@ -0,0 +1,129 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +#ifndef R_EDMAC_H + #define R_EDMAC_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************* + * Macro definitions + ********************************************************************************************************************/ + +/* EDMAC Channels available. */ + #define ETHERC_EDMAC_CHANNEL (0U) + #define PTPC_EDMAC_CHANNEL (1U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* EDMAC Descriptor Type. */ +typedef enum +{ + EDMAC_DESC_RECEIVE, + EDMAC_DESC_TRANSMIT +} edmac_desc_type_t; + +/* Number of bytes to insert into a received Ethernet packet. */ +typedef enum +{ + EDMAC_PADDING_DISABLE, + EDMAC_PADDING_1BYTE, + EDMAC_PADDING_2BYTE, + EDMAC_PADDING_3BYTE, +} edmac_padding_t; + +/* The status of a descriptor. */ +typedef struct __PACKED +{ + union + { + uint32_t raw; + + struct + { + uint32_t : 31U; + uint32_t active : 1U; + } raw_b; + }; +} edmac_desc_status_t; + +/* Buffer descriptor. */ +typedef struct +{ + volatile edmac_desc_status_t status; // The status of the descriptor. + volatile uint16_t size; // The number of bytes received or the number of bytes to transmit. + uint16_t buffer_size; // The total size of the buffer (Receive descriptor only). + uint8_t * p_buffer; // Pointer to a buffer to transmit or receive. + uint32_t resv; +} edmac_desc_t; + +typedef struct +{ + uint32_t status; // Current EDMAC status (EESR). + void * p_context; +} edmac_callback_args_t; + +typedef struct +{ + uint32_t channel; // The channel of the EDMAC instance. + edmac_padding_t padding; // Number of bytes to insert into a received buffer. + uint32_t padding_offset; // The offset into the received buffer to insert padding bytes. + uint32_t num_tx_desc; // Number of descriptors in the transmit descriptor list. + uint32_t num_rx_desc; // Number of descriptors in the receive descriptor list. + edmac_desc_t * p_tx_descriptors; // Transmit descriptor list. + edmac_desc_t * p_rx_descriptors; // Receive descriptor list. + IRQn_Type edmac_irq; // IRQ number for the EDMAC instance. + uint8_t edmac_ipl; // Interrupt priority for the EDMAC IRQ. + + /* Callback called when a buffer is transmitted or received, or if an error occurred during transmission. */ + void (* p_callback)(edmac_callback_args_t * p_args); + + void * p_context; + void * p_extend; +} edmac_cfg_t; + +typedef struct +{ + uint32_t open; // Mark if the instance has been opened. + R_ETHERC_EDMAC_Type * p_reg; // Pointer to the EDMAC registers for this instance. + edmac_cfg_t const * p_cfg; // Pointer to the configuration structure. +} edmac_instance_ctrl_t; + +typedef struct +{ + edmac_instance_ctrl_t * const p_ctrl; + edmac_cfg_t const * const p_cfg; +} edmac_instance_t; + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_EDMAC_Open(edmac_instance_ctrl_t * const p_ctrl, edmac_cfg_t const * const p_cfg); + +fsp_err_t R_EDMAC_DescriptorUpdate(edmac_instance_ctrl_t * const p_ctrl, + edmac_desc_type_t type, + uint32_t index, + uint8_t * const p_buffer, + uint16_t length); + +fsp_err_t R_EDMAC_DescriptorGet(edmac_instance_ctrl_t * const p_ctrl, + edmac_desc_type_t type, + uint32_t index, + edmac_desc_t ** const p_desc); + +fsp_err_t R_EDMAC_Close(edmac_instance_ctrl_t * const p_ctrl); + +void edmac_eint_isr(void); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_ptp.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_ptp.c new file mode 100644 index 0000000000..4d0017fe7b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ptp/r_ptp.c @@ -0,0 +1,2261 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ptp.h" +#include "r_ptp_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define PTP_OPEN (('P' << 16U) | ('T' << 8U) | ('P' << 0U)) + +#ifndef PTP_SYNFP_SYCONFR_TCYC + #define PTP_SYNFP_SYCONFR_TCYC (0x28U) +#endif + +#ifndef PTP_VERSION + #define PTP_VERSION (2U) +#endif + +#define PTP_SHIFT_32 (32U) + +#define PTP_NUM_PULSE_TIMER (5U) + +#define PTP_MILLISECONDS_IN_SECOND (1000U) +#define PTP_MICROSECONDS_IN_SECOND (PTP_MILLISECONDS_IN_SECOND * 1000U) +#define PTP_NANOSECONDS_IN_SECOND (PTP_MICROSECONDS_IN_SECOND * 1000U) +#define PTP_TIMEOUT_DIVIDER (1024U) +#define PTP_PCLKA_RESET_CYCLES (64U) + +#define PTP_BYTES_TO_UINT32(ary) ((uint32_t) (((ary)[0] << 24U) | ((ary)[1] << 16U) | ((ary)[2] << 8U) | \ + ((ary)[3] << 0U))) + +#define PTP_CMP_RETURN(p_result, a, ret) \ + { \ + if ((a)) \ + { \ + *p_result = ret; \ + return FSP_SUCCESS; \ + } \ + } + +#define PTP_ETHER_HEADER_SIZE (14U) +#define PTP_ETHER_MAX_PACKET_SIZE (1514U) +#define PTP_ETHER_MIN_PACKET_SIZE (60U) +#define PTP_ETHER_TYPE_IPV4 (0x0800U) +#define PTP_ETHER_TYPE_PTP (0x88F7U) + +#define PTP_LLC_HEADER_SIZE (0x03U) +#define PTP_LLC_MAX_LEN (1500U) +#define PTP_LLC_SAP_DSAP_OFFSET (0x00U) +#define PTP_LLC_SAP_SSAP_OFFSET (0x01U) +#define PTP_LLC_SAP_SNAP (0xAAU) +#define PTP_LLC_SAP_MASK (0xFEU) +#define PTP_LLC_CTRL_OFFSET (0x02U) +#define PTP_LLC_CTRL_FORMAT_U (0x03U) + +#define PTP_SNAP_HEADER_SIZE (5U) +#define PTP_SNAP_OID_OFFSET (0x00U) +#define PTP_SNAP_PID_OFFSET (0x03U) + +#define PTP_IPV4_HEADER_SIZE (20U) +#define PTP_IP_VERSION (4U) +#define PTP_IP_PROTOCOL_UDP (17U) +#define PTP_IP_MULTICAST_ADDRESS_MASK (0x007FFFFFU) +#define PTP_IP_MULTICAST_MAC_ADDRESS_PREFIX (0x0001005EU) + +#define PTP_UDP_HEADER_SIZE (8U) + +#define PTP_ETHER_PHY_MII (0U) +#define PTP_ETHER_PHY_RMII (1U) + +#define PTP_ETHER_PHY_10MHZ (0U) +#define PTP_ETHER_PHY_100MHZ (1U) + +#define PTP_SYRFL1R_MASK (R_ETHERC_EPTPC_SYRFL1R_ANCE0_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_SYNC0_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_SYNC2_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_FUP0_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_FUP2_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_DRQ0_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_DRQ2_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_DRP0_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_DRP2_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_PDRP0_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_PDRP2_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Msk \ + | R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Msk) + +#define PTP_SYRFL2R_MASK (R_ETHERC_EPTPC_SYRFL2R_MAN0_Msk \ + | R_ETHERC_EPTPC_SYRFL2R_SIG0_Msk) + +#define PTP_SYTRENR_MASK (R_ETHERC_EPTPC_SYTRENR_ANCE_Msk \ + | R_ETHERC_EPTPC_SYTRENR_SYNC_Msk \ + | R_ETHERC_EPTPC_SYTRENR_DRQ_Msk \ + | R_ETHERC_EPTPC_SYTRENR_PDRQ_Msk) + +#define PTP_STIPR_MASK (R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Msk \ + | R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Msk \ + | R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Msk \ + | R_ETHERC_EPTPC_COMMON_STIPR_W10D_Msk) + +#define PTP_SYIPR_MASK (R_ETHERC_EPTPC_SYIPR_OFMUD_Msk \ + | R_ETHERC_EPTPC_SYIPR_INTCHG_Msk \ + | R_ETHERC_EPTPC_SYIPR_MPDUD_Msk \ + | R_ETHERC_EPTPC_SYIPR_DRPTO_Msk \ + | R_ETHERC_EPTPC_SYIPR_INTDEV_Msk \ + | R_ETHERC_EPTPC_SYIPR_DRQOVR_Msk \ + | R_ETHERC_EPTPC_SYIPR_RECLP_Msk \ + | R_ETHERC_EPTPC_SYIPR_INFABT_Msk \ + | R_ETHERC_EPTPC_SYIPR_RESDN_Msk \ + | R_ETHERC_EPTPC_SYIPR_GENDN_Msk) + +/* Valid flags for annonuce messages. */ +#define PTP_ANNOUNCE_FLAGS_MASK (R_ETHERC_EPTPC_ANFR_FLAG0_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG1_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG2_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG3_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG4_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG5_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG8_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG10_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG13_Msk \ + | R_ETHERC_EPTPC_ANFR_FLAG14_Msk) + +/* Valid flags for sync messages. */ +#define PTP_SYNC_FLAGS_MASK (R_ETHERC_EPTPC_SYNFR_FLAG8_Msk \ + | R_ETHERC_EPTPC_SYNFR_FLAG9_Msk \ + | R_ETHERC_EPTPC_SYNFR_FLAG10_Msk \ + | R_ETHERC_EPTPC_SYNFR_FLAG13_Msk \ + | R_ETHERC_EPTPC_SYNFR_FLAG14_Msk) + +/* Valid flags for delay_req and pdelay_req messages. */ +#define PTP_P_DELAY_REQ_FLAGS_MASK (R_ETHERC_EPTPC_DYRQFR_FLAG10_Msk \ + | R_ETHERC_EPTPC_DYRQFR_FLAG13_Msk \ + | R_ETHERC_EPTPC_DYRQFR_FLAG14_Msk) + +/* Valid flags for delay_resp and pdelay_resp messages. */ +#define PTP_P_DELAY_RESP_FLAGS_MASK (R_ETHERC_EPTPC_DYRPFR_FLAG8_Msk \ + | R_ETHERC_EPTPC_DYRPFR_FLAG9_Msk \ + | R_ETHERC_EPTPC_DYRPFR_FLAG10_Msk \ + | R_ETHERC_EPTPC_DYRPFR_FLAG13_Msk \ + | R_ETHERC_EPTPC_DYRPFR_FLAG14_Msk) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Structure of an Ethernet packet. */ +typedef struct PTP_PACKED +{ + uint8_t destination_mac_address[6]; + uint8_t source_mac_address[6]; + uint16_t ether_type; +} ptp_ether_header_t; + +/* Structure of an IP packet header. */ +typedef struct PTP_PACKED +{ + uint8_t ihl : 4; + uint8_t version : 4; + uint8_t tos; + uint16_t total_length; + uint16_t id; + uint16_t fragment_offset : 14; + uint16_t flags : 2; + uint8_t ttl; + uint8_t protocol; + uint16_t checksum; + uint32_t source_address; + uint32_t destination_address; +} ptp_ip_header_t; + +/* Structure of a UDP packet header. */ +typedef struct PTP_PACKED +{ + uint16_t source_port; + uint16_t destination_port; + uint16_t length; + uint16_t checksum; +} ptp_udp_header_t; + +/* Configuration values for the Timestamp Latency Setting Register. */ +typedef struct +{ + uint32_t egp; + uint32_t ingp; +} ptp_tslatr_setting_t; + +/*********************************************************************************************************************** + * Private function declarations + **********************************************************************************************************************/ +static void r_ptp_hw_reset(void); + +static void r_ptp_hw_config(ptp_instance_ctrl_t * p_instance_ctrl); + +static uint32_t r_ptp_calculate_timeout(ptp_instance_ctrl_t * p_instance_ctrl, int8_t log_interval); + +void r_ptp_local_clock_value_get(ptp_time_t * const p_time); + +static void r_ptp_message_endian_swap(ptp_message_t * p_message); + +static fsp_err_t r_ptp_process_llc_snap_packet(uint8_t const * const p_llc_snap_packet, + uint16_t llc_snap_packet_length, + uint16_t * p_ether_type, + uint8_t ** const p_payload, + uint16_t * const payload_length); +static void r_ptp_append_ether_header(ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t * p_packet, + uint16_t packet_length); +static void r_ptp_append_ieee802_3_llc_snap_header(ptp_instance_ctrl_t * p_instance_ctrl, uint8_t * p_packet); +uint16_t r_ptp_ip_checksum(uint8_t * p_ip_header); +static void r_ptp_append_ipv4_udp_header(ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t * p_packet, + uint16_t packet_length); + +static fsp_err_t r_ptp_process_ipv4_udp_packet(ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_ip_packet, + uint16_t ip_packet_length, + uint8_t ** const p_payload, + uint16_t * const payload_length); + +static fsp_err_t r_ptp_process_ptp_packet(ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_ptp_packet, + uint16_t ptp_packet_length); + +static fsp_err_t r_ptp_process_ether_packet(ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_ether_packet, + uint16_t ether_packet_length); + +void r_ptp_edmac_callback(edmac_callback_args_t * p_args); +void r_ptp_mint_isr(void); +void r_ptp_ipls_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Lookup table for calculating TSLATR. */ +static const ptp_tslatr_setting_t g_tslatr_lut[2][2][4] = +{ + /* MMI */ + { + /* PHY Speed 10Mbs */ + { + /* STCA Input Clock Frequency 20Mhz */ + { + 9230U /* EGP */, 8980U /* INGP */ + }, + + /* STCA Input Clock Frequency 25Mhz */ + { + 9265U /* EGP */, 8945U /* INGP */ + }, + + /* STCA Input Clock Frequency 50Mhz */ + { + 9335U /* EGP */, 8875U /* INGP */ + }, + + /* STCA Input Clock Frequency 100Mhz */ + { + 9370U /* EGP */, 8815U /* INGP */ + }, + }, + + /* PHY Speed 100Mbs */ + { + /* STCA Input Clock Frequency 20Mhz */ + { + 7430U /* EGP */, 8180U /* INGP */ + }, + + /* STCA Input Clock Frequency 25Mhz */ + { + 7465U /* EGP */, 8145U /* INGP */ + }, + + /* STCA Input Clock Frequency 50Mhz */ + { + 7535U /* EGP */, 8075U /* INGP */ + }, + + /* STCA Input Clock Frequency 100Mhz */ + { + 7570U /* EGP */, 8015U /* INGP */ + }, + } + }, + + /* RMMI */ + { + /* PHY Speed 10Mbs */ + { + /* STCA Input Clock Frequency 20Mhz */ + { + 9230U /* EGP */, 8980U /* INGP */ + }, + + /* STCA Input Clock Frequency 25Mhz */ + { + 9265U /* EGP */, 8945U /* INGP */ + }, + + /* STCA Input Clock Frequency 50Mhz */ + { + 9335U /* EGP */, 8875U /* INGP */ + }, + + /* STCA Input Clock Frequency 100Mhz */ + { + 9370U /* EGP */, 8815U /* INGP */ + }, + }, + + /* PHY Speed 100Mbs */ + { + /* STCA Input Clock Frequency 20Mhz */ + { + 770U /* EGP */, 1060U /* INGP */ + }, + + /* STCA Input Clock Frequency 25Mhz */ + { + 805U /* EGP */, 1025U /* INGP */ + }, + + /* STCA Input Clock Frequency 50Mhz */ + { + 875U /* EGP */, 955U /* INGP */ + }, + + /* STCA Input Clock Frequency 100Mhz */ + { + 910U /* EGP */, 920U /* INGP */ + }, + } + } +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +const ptp_api_t g_ptp_api = +{ + .open = R_PTP_Open, + .macAddrSet = R_PTP_MacAddrSet, + .ipAddrSet = R_PTP_IpAddrSet, + .localClockIdSet = R_PTP_LocalClockIdSet, + .masterClockIdSet = R_PTP_MasterClockIdSet, + .messageFlagsSet = R_PTP_MessageFlagsSet, + .currentUtcOffsetSet = R_PTP_CurrentUtcOffsetSet, + .portStateSet = R_PTP_PortStateSet, + .messageSend = R_PTP_MessageSend, + .localClockValueSet = R_PTP_LocalClockValueSet, + .localClockValueGet = R_PTP_LocalClockValueGet, + .pulseTimerCommonConfig = R_PTP_PulseTimerCommonConfig, + .pulseTimerEnable = R_PTP_PulseTimerEnable, + .pulseTimerDisable = R_PTP_PulseTimerDisable, + .close = R_PTP_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup PTP + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This function initializes PTP. Implements @ref ptp_api_t::open. + * + * This function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Configures the peripheral registers according to the configuration. + * - Initialize the control structure for use in other @ref PTP_API functions. + * + * @retval FSP_SUCCESS The instance has been successfully configured. + * @retval FSP_ERR_ALREADY_OPEN Instance was already initialized. + * @retval FSP_ERR_NOT_OPEN The EDMAC instance was not opened correctly. + * @retval FSP_ERR_ASSERTION An invalid argument was given in the configuration structure. + **********************************************************************************************************************/ +fsp_err_t R_PTP_Open (ptp_ctrl_t * const p_ctrl, ptp_cfg_t const * const p_cfg) +{ + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(PTP_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_edmac_instance); + if (PTP_CLOCK_CORRECTION_MODE2 == p_cfg->stca.clock_correction_mode) + { + FSP_ASSERT(0U != p_cfg->stca.gradient_worst10_interval); + } + + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(p_cfg->mint_irq >= 0); + FSP_ASSERT(p_cfg->ipls_irq >= 0); +#endif + + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->tslatr = 0U; + + r_ptp_hw_config(p_instance_ctrl); + + p_instance_ctrl->rx_buffer_index = 0U; + p_instance_ctrl->tx_buffer_write_index = 0U; + p_instance_ctrl->tx_buffer_complete_index = 0U; + edmac_instance_t * p_edmac_instance = p_instance_ctrl->p_cfg->p_edmac_instance; + fsp_err_t err = R_EDMAC_Open(p_edmac_instance->p_ctrl, p_edmac_instance->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + for (uint32_t i = 0; i < p_edmac_instance->p_cfg->num_rx_desc; i++) + { + err = R_EDMAC_DescriptorUpdate(p_edmac_instance->p_ctrl, + EDMAC_DESC_RECEIVE, + i, + &p_instance_ctrl->p_cfg->p_rx_buffers[i][0], + p_instance_ctrl->p_cfg->buffer_size); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + R_BSP_IrqCfgEnable(p_instance_ctrl->p_cfg->mint_irq, p_instance_ctrl->p_cfg->mint_ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_instance_ctrl->p_cfg->ipls_irq, p_instance_ctrl->p_cfg->ipls_ipl, p_ctrl); + + p_instance_ctrl->open = PTP_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sets the MAC address for the PTP instance. Implements @ref ptp_api_t::macAddrSet. + * @note This function may only be called while the PTP instance is in @ref ptp_port_state_t::PTP_PORT_STATE_DISABLE. + * + * @retval FSP_SUCCESS The MAC address has been set. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL + * @retval FSP_ERR_INVALID_MODE The instance is not in the correct state. + **********************************************************************************************************************/ +fsp_err_t R_PTP_MacAddrSet (ptp_ctrl_t * const p_ctrl, uint8_t const * const p_mac_addr) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_mac_addr); + FSP_ERROR_RETURN(0U == R_ETHERC_EPTPC->SYRFL1R && + 0U == R_ETHERC_EPTPC->SYRFL2R && + 0U == R_ETHERC_EPTPC->SYTRENR, + FSP_ERR_INVALID_MODE); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + uint32_t symacru = 0U; + uint32_t symacrl = 0U; + + symacru |= (uint32_t) p_mac_addr[0] << 16U; + symacru |= (uint32_t) p_mac_addr[1] << 8U; + symacru |= (uint32_t) p_mac_addr[2] << 0U; + symacrl |= (uint32_t) p_mac_addr[3] << 16U; + symacrl |= (uint32_t) p_mac_addr[4] << 8U; + symacrl |= (uint32_t) p_mac_addr[5] << 0U; + + R_ETHERC_EPTPC->SYMACRU = symacru; + R_ETHERC_EPTPC->SYMACRL = symacrl; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sets the IP address for the PTP instance. Implements @ref ptp_api_t::ipAddrSet. + * @note This function may only be called while the PTP instance is in @ref ptp_port_state_t::PTP_PORT_STATE_DISABLE. + * + * @retval FSP_SUCCESS The IP address has been set. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL. + * @retval FSP_ERR_INVALID_MODE The configured ptp_synfp_cfg_t::frame_format is not configured to + * use IP packets, or the instance is not in the correct state. + **********************************************************************************************************************/ +fsp_err_t R_PTP_IpAddrSet (ptp_ctrl_t * const p_ctrl, uint32_t ip_addr) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(PTP_FRAME_FORMAT_ETHERII != p_instance_ctrl->p_cfg->synfp.frame_format && + PTP_FRAME_FORMAT_IEEE802_3 != p_instance_ctrl->p_cfg->synfp.frame_format, + FSP_ERR_INVALID_MODE); + FSP_ERROR_RETURN(0U == R_ETHERC_EPTPC->SYRFL1R && + 0U == R_ETHERC_EPTPC->SYRFL2R && + 0U == R_ETHERC_EPTPC->SYTRENR, + FSP_ERR_INVALID_MODE); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set SYNFP Local IP Address Register. */ + R_ETHERC_EPTPC->SYIPADDRR = ip_addr; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sets the local clock ID for the PTP instance. Implements @ref ptp_api_t::localClockIdSet. + * @note This function may only be called while the PTP instance is in @ref ptp_port_state_t::PTP_PORT_STATE_DISABLE. + * @note Typically the clock ID is derived from the MAC address (E.g. {b1,b2,b3,0xFF,0xFE,b4,b5,b6}). + * + * @retval FSP_SUCCESS The local clock ID has been set. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL + * @retval FSP_ERR_INVALID_MODE The instance is not in the correct state. + **********************************************************************************************************************/ +fsp_err_t R_PTP_LocalClockIdSet (ptp_ctrl_t * const p_ctrl, uint8_t const * const p_clock_id) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_clock_id); + FSP_ERROR_RETURN(0U == R_ETHERC_EPTPC->SYRFL1R && + 0U == R_ETHERC_EPTPC->SYRFL2R && + 0U == R_ETHERC_EPTPC->SYTRENR, + FSP_ERR_INVALID_MODE); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + uint32_t sycidru = PTP_BYTES_TO_UINT32(p_clock_id); + uint32_t sycidrl = PTP_BYTES_TO_UINT32(p_clock_id + 4U); + + /* SYNFP Local Clock ID Register (SYCIDRU, SYCIDRL). */ + R_ETHERC_EPTPC->SYCIDRU = sycidru; + R_ETHERC_EPTPC->SYCIDRL = sycidrl; + + /* grandmasterIdentity Field Setting Register. */ + R_ETHERC_EPTPC->GMIDRU = sycidru; + R_ETHERC_EPTPC->GMIDRL = sycidrl; + + /* Load GMIDRU and GMIDRL into the internal registers. */ + R_ETHERC_EPTPC->SYRVLDR = R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sets the master clock ID and port ID that the local clock will synchronize with. + * Implements @ref ptp_api_t::masterClockIdSet. + * + * @retval FSP_SUCCESS The master clock ID and port ID have been set. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL + **********************************************************************************************************************/ +fsp_err_t R_PTP_MasterClockIdSet (ptp_ctrl_t * const p_ctrl, uint8_t const * const p_clock_id, uint16_t port_id) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_clock_id); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + uint32_t mtcidu = PTP_BYTES_TO_UINT32(p_clock_id); + uint32_t mtcidl = PTP_BYTES_TO_UINT32(p_clock_id + 4U); + + /* Update master clock ID. */ + R_ETHERC_EPTPC->MTCIDU = mtcidu; + R_ETHERC_EPTPC->MTCIDL = mtcidl; + R_ETHERC_EPTPC->MTPID = port_id; + R_ETHERC_EPTPC->SYRVLDR = R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sets the flags field for the given message type. + * Implements @ref ptp_api_t::messageFlagsSet. + * + * @retval FSP_SUCCESS The master clock ID and port ID have been set. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + **********************************************************************************************************************/ +fsp_err_t R_PTP_MessageFlagsSet (ptp_ctrl_t * const p_ctrl, ptp_message_type_t message_type, ptp_message_flags_t flags) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + switch (message_type) + { + case PTP_MESSAGE_TYPE_ANNOUNCE: + { +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U == ((~PTP_ANNOUNCE_FLAGS_MASK) & flags.value)); +#endif + R_ETHERC_EPTPC->ANFR = flags.value; + break; + } + + case PTP_MESSAGE_TYPE_SYNC: + { +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U == ((~PTP_SYNC_FLAGS_MASK) & flags.value)); +#endif + R_ETHERC_EPTPC->SYNFR = flags.value; + break; + } + + case PTP_MESSAGE_TYPE_DELAY_REQ: + case PTP_MESSAGE_TYPE_PDELAY_REQ: + { +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U == ((~PTP_P_DELAY_REQ_FLAGS_MASK) & flags.value)); +#endif + R_ETHERC_EPTPC->DYRQFR = flags.value; + break; + } + + case PTP_MESSAGE_TYPE_DELAY_RESP: + case PTP_MESSAGE_TYPE_PDELAY_RESP: + { +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U == ((~PTP_P_DELAY_RESP_FLAGS_MASK) & flags.value)); +#endif + R_ETHERC_EPTPC->DYRPFR = flags.value; + break; + } + + default: + { + return FSP_ERR_ASSERTION; + } + } + + /* Load settings into internal registers. */ + R_ETHERC_EPTPC->SYRVLDR = R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk | R_ETHERC_EPTPC_SYRVLDR_STUP_Msk; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sets the currentUtcOffset value in announce messages. @ref ptp_api_t::currentUtcOffsetSet. + * + * @retval FSP_SUCCESS The currentUtcOffset has been updated. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + **********************************************************************************************************************/ +fsp_err_t R_PTP_CurrentUtcOffsetSet (ptp_ctrl_t * const p_ctrl, uint16_t offset) +{ + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + R_ETHERC_EPTPC->CUOTSR = + (uint32_t) (p_instance_ctrl->p_cfg->synfp.timesource | (offset << R_ETHERC_EPTPC_CUOTSR_CUTO_Pos)); + + /* Load settings into internal registers. */ + R_ETHERC_EPTPC->SYRVLDR = R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function changes the current state of the PTP instance. Implements @ref ptp_api_t::portStateSet. + * + * @retval FSP_SUCCESS The instance will transition to the new state. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL + **********************************************************************************************************************/ +fsp_err_t R_PTP_PortStateSet (ptp_ctrl_t * const p_ctrl, uint32_t state) +{ + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Set TSLATR if it has not already be set. */ + if (0U == p_instance_ctrl->tslatr) + { + /* Read ECMR in order to determine the PHY bitrate. */ + uint32_t ecmr = R_ETHERC0->ECMR; + uint32_t rtm = (ecmr & R_ETHERC0_ECMR_RTM_Msk) >> R_ETHERC0_ECMR_RTM_Pos; + + /* Get the value of tslatr from lookup table. */ + ptp_tslatr_setting_t tsaltr_setting = + g_tslatr_lut[p_instance_ctrl->p_cfg->synfp.ethernet_phy_interface][rtm][p_instance_ctrl->p_cfg->stca. + clock_freq]; + + p_instance_ctrl->tslatr = tsaltr_setting.egp | (tsaltr_setting.ingp << R_ETHERC_EPTPC_TSLATR_INGP_Pos); + R_ETHERC_EPTPC->TSLATR = p_instance_ctrl->tslatr; + } + + /* + * A critical section is required in order to clear the delay request timeout status + * without generating an IRQ. + */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Disable clock synchronization when changing port state. */ + R_ETHERC_EPTPC_COMMON->SYNSTARTR = 0U; + + /* Enum values defined in ptp_port_state_t related to SYRFL1R map directly to the bitfields. */ + R_ETHERC_EPTPC->SYRFL1R = state & PTP_SYRFL1R_MASK; + + /* + * Enum values defined in ptp_port_state_t related to SYRFL2R map directly to the bitfields but are shifted by 1 so that + * all port state settings can fit in a 32 bit integer. + */ + R_ETHERC_EPTPC->SYRFL2R = (state >> 1U) & PTP_SYRFL2R_MASK; + + /* + * Enum values defined in ptp_port_state_t related to SYTRENR map directly to the bitfields but are shifted by 3 so that + * all port state settings can fit in a 32 bit integer. + */ + R_ETHERC_EPTPC->SYTRENR = (state >> 3U) & PTP_SYTRENR_MASK; + + /* Load settings into internal registers. */ + R_ETHERC_EPTPC->SYRVLDR = R_ETHERC_EPTPC_SYRVLDR_STUP_Msk; + + /* Suppress delay_req timeout IRQ when entering slave mode. */ + R_ETHERC_EPTPC->SYSR = R_ETHERC_EPTPC_SYSR_DRPTO_Msk; + + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sends a PTP message. @ref ptp_api_t::messageSend. + * + * @retval FSP_SUCCESS The packet has been written to the transmit descriptor. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + * @retval FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL There is no space for the packet in the transmit queue. + **********************************************************************************************************************/ +fsp_err_t R_PTP_MessageSend (ptp_ctrl_t * const p_ctrl, + ptp_message_t const * const p_message, + uint8_t const * const p_tlv_data, + uint16_t tlv_data_size) +{ + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_message); + FSP_ASSERT(sizeof(ptp_message_header_t) < p_message->header.message_length); + if (NULL == p_tlv_data) + { + FSP_ASSERT(0 == tlv_data_size); + } +#endif + + /* Calculate the total size of the ethernet packet. */ + uint16_t packet_size = (uint16_t) (p_message->header.message_length + PTP_ETHER_HEADER_SIZE); + + if ((PTP_FRAME_FORMAT_IEEE802_3 == p_instance_ctrl->p_cfg->synfp.frame_format) || + (PTP_FRAME_FORMAT_IEEE802_3_IPV4_UDP == p_instance_ctrl->p_cfg->synfp.frame_format)) + { + packet_size = (uint16_t) (packet_size + PTP_LLC_HEADER_SIZE + PTP_SNAP_HEADER_SIZE); + } + + if ((PTP_FRAME_FORMAT_ETHERII_IPV4_UDP == p_instance_ctrl->p_cfg->synfp.frame_format) || + (PTP_FRAME_FORMAT_IEEE802_3_IPV4_UDP == p_instance_ctrl->p_cfg->synfp.frame_format)) + { + packet_size = (uint16_t) (packet_size + PTP_IPV4_HEADER_SIZE + PTP_UDP_HEADER_SIZE); + } + +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl->p_cfg->buffer_size >= packet_size); + FSP_ASSERT(PTP_ETHER_MAX_PACKET_SIZE >= packet_size); +#endif + + uint8_t * p_packet = p_instance_ctrl->p_cfg->p_tx_buffers[p_instance_ctrl->tx_buffer_write_index]; + edmac_instance_t * p_edmac_instance = p_instance_ctrl->p_cfg->p_edmac_instance; + + edmac_desc_t * p_desc; + fsp_err_t err = R_EDMAC_DescriptorGet(p_edmac_instance->p_ctrl, + EDMAC_DESC_TRANSMIT, + p_instance_ctrl->tx_buffer_write_index, + &p_desc); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If the current buffer descriptor is active, then there is no more space in the transmit queue. */ + if (1U == p_desc->status.raw_b.active) + { + return FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL; + } + + /* Add the Ethernet header. */ + r_ptp_append_ether_header(p_instance_ctrl, p_packet, packet_size); + uint8_t * p_packet_append = p_packet + PTP_ETHER_HEADER_SIZE; + uint16_t packet_size_remaining = (uint16_t) (packet_size - PTP_ETHER_HEADER_SIZE); + + if ((PTP_FRAME_FORMAT_IEEE802_3 == p_instance_ctrl->p_cfg->synfp.frame_format) || + (PTP_FRAME_FORMAT_IEEE802_3_IPV4_UDP == p_instance_ctrl->p_cfg->synfp.frame_format)) + { + /* Add LLC and SNAP headers. */ + r_ptp_append_ieee802_3_llc_snap_header(p_instance_ctrl, p_packet_append); + + p_packet_append += PTP_LLC_HEADER_SIZE + PTP_SNAP_HEADER_SIZE; + packet_size_remaining = (uint16_t) (packet_size_remaining - PTP_LLC_HEADER_SIZE - PTP_SNAP_HEADER_SIZE); + } + + if ((PTP_FRAME_FORMAT_ETHERII_IPV4_UDP == p_instance_ctrl->p_cfg->synfp.frame_format) || + (PTP_FRAME_FORMAT_IEEE802_3_IPV4_UDP == p_instance_ctrl->p_cfg->synfp.frame_format)) + { + /* Add IP and UDP header. */ + r_ptp_append_ipv4_udp_header(p_instance_ctrl, p_packet_append, packet_size_remaining); + p_packet_append += PTP_IPV4_HEADER_SIZE + PTP_UDP_HEADER_SIZE; + } + + uint32_t message_length = p_message->header.message_length; + + /* Copy the PTP message into the packet. */ + memcpy(p_packet_append, p_message, message_length - tlv_data_size); + + /* Convert PTP message fields to big endian. */ + r_ptp_message_endian_swap((ptp_message_t *) p_packet_append); + + p_packet_append += message_length - tlv_data_size; + + if (NULL != p_tlv_data) + { + /* Copy TLV data into the packet. */ + memcpy(p_packet_append, p_tlv_data, tlv_data_size); + p_packet_append += tlv_data_size; + } + + if (PTP_ETHER_MIN_PACKET_SIZE > packet_size) + { + /* Zero pad if the packet is smaller than the minimum Ethernet packet. */ + memset(p_packet_append, 0, PTP_ETHER_MIN_PACKET_SIZE - packet_size); + packet_size = PTP_ETHER_MIN_PACKET_SIZE; + } + + /* Disable the PTP EDMAC IRQ so that a transmit complete interrupt does not occur + * before tx_buffer_write_index is incremented. */ + R_BSP_IrqDisable(p_edmac_instance->p_cfg->edmac_irq); + + /* Write the buffer into the buffer descriptor and set the status to active. */ + err = R_EDMAC_DescriptorUpdate(p_edmac_instance->p_ctrl, + EDMAC_DESC_TRANSMIT, + p_instance_ctrl->tx_buffer_write_index, + p_packet, + packet_size); + + if (FSP_SUCCESS != err) + { + R_BSP_IrqEnable(p_edmac_instance->p_cfg->edmac_irq); + + return err; + } + + /* Go to the next space in the queue. */ + p_instance_ctrl->tx_buffer_write_index++; + if (p_instance_ctrl->tx_buffer_write_index == p_edmac_instance->p_cfg->num_tx_desc) + { + p_instance_ctrl->tx_buffer_write_index = 0U; + } + + R_BSP_IrqEnable(p_edmac_instance->p_cfg->edmac_irq); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sets the local clock value. Implements @ref ptp_api_t::localClockValueSet. + * + * @retval FSP_SUCCESS The local clock value has been set. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + **********************************************************************************************************************/ +fsp_err_t R_PTP_LocalClockValueSet (ptp_ctrl_t * const p_ctrl, ptp_time_t const * const p_time) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_time); + FSP_ASSERT(1000000000U > p_time->nanoseconds); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /** IRQs disabled because LCIVRn registers must be set in consecutive operations + * (See "Local Clock Counter Initial Value Register (LCIVRU, LCIVRM, LCIVRL)" description in the + * EPTPC section of the relevant hardware manual). */ + __disable_irq(); + + /* Set an initial value in the local clock counter. */ + R_ETHERC_EPTPC_COMMON->LCIVRU = (uint32_t) p_time->seconds_upper; + R_ETHERC_EPTPC_COMMON->LCIVRM = p_time->seconds_lower; + R_ETHERC_EPTPC_COMMON->LCIVRL = p_time->nanoseconds; + + /* Load the initial value into the local clock counter. */ + R_ETHERC_EPTPC_COMMON->LCIVLDR = 1; + + __enable_irq(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function gets the local clock value. Implements @ref ptp_api_t::localClockValueGet. + * + * @retval FSP_SUCCESS The local clock value has been written in p_time. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL + **********************************************************************************************************************/ +fsp_err_t R_PTP_LocalClockValueGet (ptp_ctrl_t * const p_ctrl, ptp_time_t * const p_time) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_time); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + r_ptp_local_clock_value_get(p_time); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function configures IPLS IRQ settings that are common to all pulse timer channels. + * Implements @ref ptp_api_t::pulseTimerCommonConfig. + * + * @retval FSP_SUCCESS The pulse timer has been enabled. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + **********************************************************************************************************************/ +fsp_err_t R_PTP_PulseTimerCommonConfig (ptp_ctrl_t * const p_ctrl, ptp_pulse_timer_common_cfg_t * const p_timer_cfg) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_timer_cfg); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* + * A critical section is required because timer functions cannot be re-entered while accessing common registers. + */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Configure the IPLS IRQ for rising and falling edge for all channels. */ + uint32_t elippr = R_ETHERC_EPTPC_COMMON->ELIPPR; + elippr &= ~(R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Msk | R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Msk); + elippr |= (uint32_t) (p_timer_cfg->ipls_rising_irq << R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Pos); + elippr |= (uint32_t) (p_timer_cfg->ipls_falling_irq << R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Pos); + + /* Configure auto clearing of the IPLS IRQ enable bits for rising and falling edges. */ + uint32_t elipacr = R_ETHERC_EPTPC_COMMON->ELIPACR; + elipacr &= ~(R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Msk | R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Msk); + elipacr |= (uint32_t) (p_timer_cfg->ipls_rising_irq_auto_clear << R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Pos); + elipacr |= (uint32_t) (p_timer_cfg->ipls_falling_irq_auto_clear << R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Pos); + + /* Write settings to registers. */ + R_ETHERC_EPTPC_COMMON->ELIPPR = elippr; + R_ETHERC_EPTPC_COMMON->ELIPACR = elipacr; + + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function enables a pulse timer channel. Implements @ref ptp_api_t::pulseTimerEnable. + * + * @retval FSP_SUCCESS The pulse timer has been enabled. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + * @retval FSP_ERR_INVALID_ARGUMENT The start time must be set to a value that is later than current time. + **********************************************************************************************************************/ +fsp_err_t R_PTP_PulseTimerEnable (ptp_ctrl_t * const p_ctrl, uint32_t channel, + ptp_pulse_timer_cfg_t * const p_timer_cfg) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_timer_cfg); + FSP_ASSERT(PTP_NUM_PULSE_TIMER >= channel); + FSP_ASSERT(1000000000U > p_timer_cfg->start_time.nanoseconds); + FSP_ASSERT(p_timer_cfg->period > p_timer_cfg->pulse); + + /* Verify that the start time is after the current time. */ + ptp_time_t current_time; + r_ptp_local_clock_value_get(¤t_time); + + FSP_ERROR_RETURN(p_timer_cfg->start_time.seconds_upper >= current_time.seconds_upper, FSP_ERR_INVALID_ARGUMENT); + + if (p_timer_cfg->start_time.seconds_upper == current_time.seconds_upper) + { + FSP_ERROR_RETURN(p_timer_cfg->start_time.seconds_lower >= current_time.seconds_lower, FSP_ERR_INVALID_ARGUMENT); + + if (p_timer_cfg->start_time.seconds_lower == current_time.seconds_lower) + { + FSP_ERROR_RETURN(p_timer_cfg->start_time.nanoseconds >= current_time.nanoseconds, FSP_ERR_INVALID_ARGUMENT); + } + } + +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Convert the time to nanoseconds. */ + uint64_t start_time = ((uint64_t) p_timer_cfg->start_time.seconds_upper << PTP_SHIFT_32) | + (uint64_t) p_timer_cfg->start_time.seconds_lower; + start_time *= PTP_NANOSECONDS_IN_SECOND; + start_time += p_timer_cfg->start_time.nanoseconds; + + /* Get pointer to the registers for this channel. */ + R_ETHERC_EPTPC_COMMON_TM_Type volatile * p_tm = &R_ETHERC_EPTPC_COMMON->TM[channel]; + + p_tm->STTRU = (uint32_t) (start_time >> PTP_SHIFT_32); + p_tm->STTRL = (uint32_t) (start_time & UINT32_MAX); + p_tm->CYCR = p_timer_cfg->period; + p_tm->PLSR = p_timer_cfg->pulse; + + /* + * A critical section is required because timer functions cannot be re-entered while accessing common registers. + */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Configure MINT IRQ for this channel. */ + uint32_t mieipr = R_ETHERC_EPTPC_COMMON->MIEIPR; + mieipr &= ~(1U << (R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos + channel)); + mieipr |= (uint32_t) p_timer_cfg->mint_rising_irq << (R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos + channel); + uint32_t mitselr = R_ETHERC_EPTPC_COMMON->MITSELR; + mitselr &= ~(1U << channel); + mitselr |= (uint32_t) p_timer_cfg->mint_rising_irq << channel; + + /* Configure rising and falling edge ELC events for this channel. */ + uint32_t elippr = R_ETHERC_EPTPC_COMMON->ELIPPR; + elippr &= ~(1U << channel); + elippr &= ~(1U << (R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos + channel)); + elippr |= (uint32_t) (p_timer_cfg->ipls_rising_event << channel); + elippr |= (uint32_t) (p_timer_cfg->ipls_falling_event << (R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos + channel)); + + /* Configure auto clearing of ELC event enable bits for rising and falling edge. */ + uint32_t elipacr = R_ETHERC_EPTPC_COMMON->ELIPACR; + elipacr &= ~(1U << channel); + elipacr &= ~(1U << (R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos + channel)); + elipacr |= (uint32_t) (p_timer_cfg->ipls_rising_event_auto_clear << channel); + elipacr |= + (uint32_t) (p_timer_cfg->ipls_falling_event_auto_clear << (R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos + channel)); + + /* Configure IPLS IRQ for this channel. */ + uint32_t iptselr = R_ETHERC_EPTPC_COMMON->IPTSELR; + iptselr &= ~(1U << channel); + iptselr |= (uint32_t) (p_timer_cfg->ipls_irq_source << channel); + + /* Write settings to registers. */ + R_ETHERC_EPTPC_COMMON->MIEIPR = mieipr; + R_ETHERC_EPTPC_COMMON->ELIPPR = elippr; + R_ETHERC_EPTPC_COMMON->ELIPACR = elipacr; + R_ETHERC_EPTPC_COMMON->IPTSELR = iptselr; + R_ETHERC_EPTPC_COMMON->MITSELR = mitselr; + + /* Start the pulse timer. */ + R_ETHERC_EPTPC_COMMON->TMSTARTR |= (1U << channel); + + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function disables a pulse timer channel. Implements @ref ptp_api_t::pulseTimerDisable. + * + * @retval FSP_SUCCESS The pulse timer has been disabled. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + **********************************************************************************************************************/ +fsp_err_t R_PTP_PulseTimerDisable (ptp_ctrl_t * const p_ctrl, uint32_t channel) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(PTP_NUM_PULSE_TIMER >= channel); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* + * A critical section is required because timer functions cannot be re-entered while accessing common registers. + */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Disable the pulse timer. */ + R_ETHERC_EPTPC_COMMON->TMSTARTR &= ~(1U << channel); + + FSP_CRITICAL_SECTION_EXIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable the PTP instance. Implements @ref ptp_api_t::close. + * + * @retval FSP_SUCCESS The pulse timer has been disabled. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION An argument was NULL or invalid. + **********************************************************************************************************************/ +fsp_err_t R_PTP_Close (ptp_ctrl_t * const p_ctrl) +{ + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ctrl; +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(PTP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + edmac_instance_t * p_edmac_instance = p_instance_ctrl->p_cfg->p_edmac_instance; + + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->mint_irq); + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->ipls_irq); + + R_EDMAC_Close(p_edmac_instance->p_ctrl); + + r_ptp_hw_reset(); + + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function compares two clocks to determine which one is the better master clock. + * + * p_comparison: + * - Set to -1 if p_announce1 defines the best master clock. + * - Set to 1 if p_announce2 defines the best master clock. + * - Set to 0 if p_announce1 and p_announce2 define the same clock. + * + * @retval FSP_SUCCESS The valid result has been written to p_use_announce_clock. + * @retval FSP_ERR_ASSERTION An argument was NULL. + **********************************************************************************************************************/ +fsp_err_t R_PTP_BestMasterClock (ptp_message_t const * const p_announce1, + ptp_message_t const * const p_announce2, + int8_t * const p_comparison) +{ +#if PTP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_announce1); + FSP_ASSERT(NULL != p_announce2); + FSP_ASSERT(NULL != p_comparison); + FSP_ASSERT(PTP_MESSAGE_TYPE_ANNOUNCE == p_announce1->header.message_type); + FSP_ASSERT(PTP_MESSAGE_TYPE_ANNOUNCE == p_announce2->header.message_type); +#endif + + int parent_id_comparison = memcmp(p_announce1->header.clock_id, p_announce2->header.clock_id, 8); + int grandmaster_id_comparison = memcmp(p_announce1->announce.clock_id, p_announce2->announce.clock_id, 8); + + /** If the parent ID is identical than these messages originate from the same clock. */ + PTP_CMP_RETURN(p_comparison, 0 == parent_id_comparison, 0); + + if (0 != grandmaster_id_comparison) + { + /* Compare clock properties to determine which grandmaster clock is the best. */ + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.priority1 < p_announce2->announce.clock_properties.priority1, + -1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.priority1 > p_announce2->announce.clock_properties.priority1, + 1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.cclass < p_announce2->announce.clock_properties.cclass, + -1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.cclass > p_announce2->announce.clock_properties.cclass, + 1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.accuracy < p_announce2->announce.clock_properties.accuracy, + -1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.accuracy > p_announce2->announce.clock_properties.accuracy, + 1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.variance < p_announce2->announce.clock_properties.variance, + -1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.variance > p_announce2->announce.clock_properties.variance, + 1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.priority2 < p_announce2->announce.clock_properties.priority2, + -1); + PTP_CMP_RETURN(p_comparison, + p_announce1->announce.clock_properties.priority2 > p_announce2->announce.clock_properties.priority2, + 1); + + /* If all of the clock properties are equal, then the smallest grandmaster clock ID is best. */ + *p_comparison = (int8_t) grandmaster_id_comparison; + + return FSP_SUCCESS; + } + + /* If the grandmaster clock ID is identical then determine which parent clock is best. */ + + PTP_CMP_RETURN(p_comparison, p_announce1->announce.steps_removed < p_announce2->announce.steps_removed, -1); + PTP_CMP_RETURN(p_comparison, p_announce1->announce.steps_removed > p_announce2->announce.steps_removed, 1); + + *p_comparison = (int8_t) parent_id_comparison; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup PTP) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Reset the PTP peripheral using PTRSTR. + **********************************************************************************************************************/ +static void r_ptp_hw_reset (void) +{ + uint32_t pclka_freq = SystemCoreClock << R_SYSTEM->SCKDIVCR_b.ICK; + pclka_freq >>= R_SYSTEM->SCKDIVCR_b.PCKA; + + uint32_t delay_microseconds = PTP_PCLKA_RESET_CYCLES * BSP_DELAY_UNITS_SECONDS / pclka_freq + 1U; + + /* Reset the PTP module. */ + R_ETHERC_EPTPC_CFG->PTRSTR = 1; + + /* Wait 64 cycles of PCLKA for the PTP peripheral to reset + * (See "PTP Reset Register (PTRSTR)" description in the EPTPC section of the relevant hardware manual). */ + R_BSP_SoftwareDelay(delay_microseconds, BSP_DELAY_UNITS_MICROSECONDS); + + R_ETHERC_EPTPC_CFG->PTRSTR = 0; + + /* Wait 2 access cycles to ensure that the write has completed. */ + R_ETHERC_EPTPC_CFG->PTRSTR; +} + +/*******************************************************************************************************************//** + * Writes the configuration settings into the PTP registers. + * + * @param[in] p_instance_ctrl Instance control block + **********************************************************************************************************************/ +static void r_ptp_hw_config (ptp_instance_ctrl_t * p_instance_ctrl) +{ + ptp_cfg_t const * const p_cfg = p_instance_ctrl->p_cfg; + + /* Set the number of times the offsetFromMaster must be above the threshold for sync to be lost. */ + uint32_t stmr = (uint32_t) (p_cfg->stca.sync_threshold.count << R_ETHERC_EPTPC_COMMON_STMR_DVTH_Pos); + + /* Set the number of times the offsetFromMaster must be below the threshold for sync to be acquired. */ + stmr |= (uint32_t) (p_cfg->stca.sync_loss_threshold.count << R_ETHERC_EPTPC_COMMON_STMR_SYTH_Pos); + + /* Enable the SYNCOUT and SYNTOUT flags in STSR. */ + stmr |= R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Msk | R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Msk; + + /* Configure gradient worst10 acquisition. */ + if (PTP_CLOCK_CORRECTION_MODE2 == p_cfg->stca.clock_correction_mode) + { + /* Enable clock correction mode 2. */ + stmr |= R_ETHERC_EPTPC_COMMON_STMR_CMOD_Msk; + + /* Set the interval for calculating worst10 gradients. */ + stmr |= (uint32_t) (p_cfg->stca.gradient_worst10_interval << R_ETHERC_EPTPC_COMMON_STMR_WINT_Pos); + + /* Set worst10 aquistion mode to software start. */ + stmr |= R_ETHERC_EPTPC_COMMON_STMR_W10S_Msk; + } + + /* Set the value of Synchronization Loss Detection Threshold Register. */ + uint32_t syntdaru = (uint32_t) (p_cfg->stca.sync_loss_threshold.threshold >> PTP_SHIFT_32); + uint32_t syntdarl = + (uint32_t) (p_cfg->stca.sync_loss_threshold.threshold & R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Msk); + + /* Set the value of Synchronization Detection Threshold Register. */ + uint32_t syntdbru = (uint32_t) (p_cfg->stca.sync_threshold.threshold >> PTP_SHIFT_32); + uint32_t syntdbrl = (uint32_t) (p_cfg->stca.sync_threshold.threshold & R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Msk); + + /* SYNFP Transmission Interval Setting Register. */ + uint32_t sytlir = (uint32_t) p_cfg->synfp.announce_interval << R_ETHERC_EPTPC_SYTLIR_ANCE_Pos; + sytlir |= (uint32_t) p_cfg->synfp.sync_interval << R_ETHERC_EPTPC_SYTLIR_SYNC_Pos; + sytlir |= (uint32_t) p_cfg->synfp.delay_req_interval << R_ETHERC_EPTPC_SYTLIR_DREQ_Pos; + + /* grandmasterClockQuality Field Setting Register. */ + uint32_t gmcqr = 0; + gmcqr |= (uint32_t) (p_cfg->synfp.clock_properties.cclass << 24U); + gmcqr |= (uint32_t) (p_cfg->synfp.clock_properties.accuracy << 16U); + gmcqr |= (uint32_t) (p_cfg->synfp.clock_properties.variance << 0U); + + uint64_t delay_resp_timeout = (uint64_t) p_cfg->synfp.message_timeout * + (PTP_NANOSECONDS_IN_SECOND / PTP_MILLISECONDS_IN_SECOND / PTP_TIMEOUT_DIVIDER); + if (delay_resp_timeout > UINT32_MAX) + { + delay_resp_timeout = UINT32_MAX; + } + + R_BSP_MODULE_START(FSP_IP_EPTPC, 0); + + r_ptp_hw_reset(); + + /* Set the value of STCA Clock Select Register. */ + R_ETHERC_EPTPC_CFG->STCSELR = (uint32_t) p_cfg->stca.clock_sel; + + /* Ensure that there are at least 2 access cycles between writing STCSELR and STCFR. */ + R_ETHERC_EPTPC_CFG->STCSELR; + + /* Set the value of the STCA Clock Frequency Setting Register. */ + R_ETHERC_EPTPC_COMMON->STCFR = (uint32_t) p_cfg->stca.clock_freq; + + if (PTP_FRAME_FILTER_MODE_UNICAST_MULTICAST_FILTERED == p_cfg->synfp.frame_filter) + { + /* Set the value of Frame Reception Filter MAC Address 0 Setting Register */ + uint32_t fmac0ru = (uint32_t) (p_cfg->synfp.p_multicast_addr_filter[0] << 16U); + fmac0ru |= (uint32_t) (p_cfg->synfp.p_multicast_addr_filter[1] << 8U); + fmac0ru |= (uint32_t) (p_cfg->synfp.p_multicast_addr_filter[2] << 0U); + uint32_t fmac0rl = (uint32_t) (p_cfg->synfp.p_multicast_addr_filter[3] << 16U); + fmac0rl |= (uint32_t) (p_cfg->synfp.p_multicast_addr_filter[4] << 8U); + fmac0rl |= (uint32_t) (p_cfg->synfp.p_multicast_addr_filter[5] << 0U); + + R_ETHERC_EPTPC->FMAC0RU = fmac0ru; + R_ETHERC_EPTPC->FMAC0RL = fmac0rl; + } + + if ((PTP_FRAME_FORMAT_ETHERII == p_cfg->synfp.frame_format) || + (PTP_FRAME_FORMAT_IEEE802_3 == p_cfg->synfp.frame_format)) + { + /* Set the value of PTP-primary Message Destination MAC Address Setting Register. */ + uint32_t ppmacru = (uint32_t) (p_cfg->synfp.ether.p_primary_mac_addr[0] << 16U); + ppmacru |= (uint32_t) (p_cfg->synfp.ether.p_primary_mac_addr[1] << 8U); + ppmacru |= (uint32_t) (p_cfg->synfp.ether.p_primary_mac_addr[2] << 0U); + uint32_t ppmacrl = (uint32_t) (p_cfg->synfp.ether.p_primary_mac_addr[3] << 16U); + ppmacrl |= (uint32_t) (p_cfg->synfp.ether.p_primary_mac_addr[4] << 8U); + ppmacrl |= (uint32_t) (p_cfg->synfp.ether.p_primary_mac_addr[5] << 0U); + + /* Set the value of PTP-pdelay Message MAC Address Setting Register. */ + uint32_t pdmacru = (uint32_t) (p_cfg->synfp.ether.p_pdelay_mac_addr[0] << 16U); + pdmacru |= (uint32_t) (p_cfg->synfp.ether.p_pdelay_mac_addr[1] << 8U); + pdmacru |= (uint32_t) (p_cfg->synfp.ether.p_pdelay_mac_addr[2] << 0U); + uint32_t pdmacrl = (uint32_t) (p_cfg->synfp.ether.p_pdelay_mac_addr[3] << 16U); + pdmacrl |= (uint32_t) (p_cfg->synfp.ether.p_pdelay_mac_addr[4] << 8U); + pdmacrl |= (uint32_t) (p_cfg->synfp.ether.p_pdelay_mac_addr[5] << 0U); + + R_ETHERC_EPTPC->PPMACRU = ppmacru; + R_ETHERC_EPTPC->PPMACRL = ppmacrl; + R_ETHERC_EPTPC->PDMACRU = pdmacru; + R_ETHERC_EPTPC->PDMACRL = pdmacrl; + } + else + { + /* Set the value of the PTP-primary Message Destination IP Address Setting Register. */ + R_ETHERC_EPTPC->PPIPR = p_cfg->synfp.ipv4.primary_ip_addr; + + /* Set the value of the PTP-pdelay Message Destination IP Address Setting Register. */ + R_ETHERC_EPTPC->PDIPR = p_cfg->synfp.ipv4.pdelay_ip_addr; + + /* Set the value of the PTP Event Message TOS Register. */ + R_ETHERC_EPTPC->PETOSR = p_cfg->synfp.ipv4.event_tos; + + /* Set the value of the PTP General Message TOS Register. */ + R_ETHERC_EPTPC->PGTOSR = p_cfg->synfp.ipv4.general_tos; + + /* Set the value of the PTP-primary Message TTL Settig Register. */ + R_ETHERC_EPTPC->PPTTLR = p_cfg->synfp.ipv4.primary_ttl; + + /* Set the value of the PTP-pdelay Message TTL Settig Register. */ + R_ETHERC_EPTPC->PDTTLR = p_cfg->synfp.ipv4.pdelay_ttl; + + /* Set the value of the PTP Event Message UDP Destination Port Number Setting Register. */ + R_ETHERC_EPTPC->PEUDPR = p_cfg->synfp.ipv4.event_udp_port; + + /* Set the value of the PTP General Message UDP Destination Port Number Setting Register. */ + R_ETHERC_EPTPC->PGUDPR = p_cfg->synfp.ipv4.general_udp_port; + } + + /* Write to PTP registers. */ + R_ETHERC_EPTPC_COMMON->MIEIPR = R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Msk | R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Msk; + R_ETHERC_EPTPC_COMMON->STIPR = PTP_STIPR_MASK; + R_ETHERC_EPTPC_COMMON->STMR = stmr; + R_ETHERC_EPTPC_COMMON->SYNTOR = p_cfg->synfp.message_timeout / PTP_TIMEOUT_DIVIDER; + R_ETHERC_EPTPC_COMMON->SYNTDARU = syntdaru; + R_ETHERC_EPTPC_COMMON->SYNTDARL = syntdarl; + R_ETHERC_EPTPC_COMMON->SYNTDBRU = syntdbru; + R_ETHERC_EPTPC_COMMON->SYNTDBRL = syntdbrl; + R_ETHERC_EPTPC->SYIPR = PTP_SYIPR_MASK; + R_ETHERC_EPTPC->SYSPVRR = (PTP_VERSION << R_ETHERC_EPTPC_SYSPVRR_VER_Pos); + R_ETHERC_EPTPC->SYDOMR = p_cfg->synfp.clock_domain; + R_ETHERC_EPTPC->SYPNUMR = 1U; + R_ETHERC_EPTPC->GMPR = (uint32_t) (p_cfg->synfp.clock_properties.priority2 | + (p_cfg->synfp.clock_properties.priority1 << + R_ETHERC_EPTPC_GMPR_GMPR1_Pos)); + R_ETHERC_EPTPC->GMCQR = gmcqr; + R_ETHERC_EPTPC->CUOTSR = (uint32_t) p_cfg->synfp.timesource; + R_ETHERC_EPTPC->SYTLIR = sytlir; + R_ETHERC_EPTPC->PETYPER = PTP_ETHER_TYPE_PTP; + R_ETHERC_EPTPC->FFLTR = (uint32_t) p_cfg->synfp.frame_filter; + R_ETHERC_EPTPC->SYCONFR = (uint32_t) (p_cfg->synfp.clock_domain_filter << R_ETHERC_EPTPC_SYCONFR_FILDIS_Pos) | + PTP_SYNFP_SYCONFR_TCYC; + R_ETHERC_EPTPC->SYFORMR = (uint32_t) p_cfg->synfp.frame_format; + R_ETHERC_EPTPC->RSTOUTR = (uint32_t) delay_resp_timeout; + + /* Load settings into internal registers. */ + R_ETHERC_EPTPC->SYRVLDR = R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk | + R_ETHERC_EPTPC_SYRVLDR_STUP_Msk | + R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk; +} + +/*******************************************************************************************************************//** + * Calcualtes the appropriate timeout value based off of the given log_interval. + * + * @param[in] p_instance_ctrl Instance control block + * @param[in] log_interval log_interval + * + * @return Timeout value + **********************************************************************************************************************/ +static uint32_t r_ptp_calculate_timeout (ptp_instance_ctrl_t * p_instance_ctrl, int8_t log_interval) +{ + /* If the inteval is less then (1 / 128) seconds, assume interval is (1 / 128) seconds. */ + if (PTP_MESSAGE_INTERVAL_1_128 > log_interval) + { + log_interval = PTP_MESSAGE_INTERVAL_1_128; + } + /* If the interval is greater than 64 seconds, assume interval is 64 seconds. */ + else if (PTP_MESSAGE_INTERVAL_64 < log_interval) + { + log_interval = PTP_MESSAGE_INTERVAL_64; + } + else + { + } + + uint64_t timeout = 0; + + /** Convert the message timeout to nanoseconds. */ + uint64_t message_timeout_ns = (uint64_t) p_instance_ctrl->p_cfg->synfp.message_timeout * + (PTP_NANOSECONDS_IN_SECOND / PTP_MILLISECONDS_IN_SECOND / PTP_TIMEOUT_DIVIDER); + + /* Set the timeout to (message period + message_timeout). */ + if (log_interval < 0) + { + log_interval = (int8_t) (log_interval * -1); + timeout = (PTP_NANOSECONDS_IN_SECOND / PTP_TIMEOUT_DIVIDER) >> log_interval; + } + else + { + timeout = (PTP_NANOSECONDS_IN_SECOND / PTP_TIMEOUT_DIVIDER) << log_interval; + } + + timeout += message_timeout_ns; + + /* If the timeout is to large to fit in a 32bit int, clamp the value at UINT32_MAX. */ + if (timeout > UINT32_MAX) + { + timeout = UINT32_MAX; + } + + return (uint32_t) (timeout & UINT32_MAX); +} + +/*******************************************************************************************************************//** + * Get the current value of the local clock. + * + * @param[in] p_time Pointer to a structure for storing the clock value. + **********************************************************************************************************************/ +void r_ptp_local_clock_value_get (ptp_time_t * const p_time) +{ + /* Issue a directive to capture information. */ + R_ETHERC_EPTPC_COMMON->GETINFOR = 1U; + + /* Waiting for information capturing to complete. + * (See Figure "Procedure for reading the time kept by the local clock counter" + * in the EPTPC section of the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT(R_ETHERC_EPTPC_COMMON->GETINFOR, 0U); + + /* Read the value of the local clock counter from the LCCVR register. */ + p_time->seconds_upper = (uint16_t) R_ETHERC_EPTPC_COMMON->LCCVRU; + p_time->seconds_lower = R_ETHERC_EPTPC_COMMON->LCCVRM; + p_time->nanoseconds = R_ETHERC_EPTPC_COMMON->LCCVRL; +} + +/*******************************************************************************************************************//** + * Performs endian swap on PTP message fields. + * + * @param[in] p_message Pointer to message to endian swap. + **********************************************************************************************************************/ +static void r_ptp_message_endian_swap (ptp_message_t * p_message) +{ + p_message->header.message_length = (uint16_t) __REV16(p_message->header.message_length); + p_message->header.flags.value = (uint16_t) __REV16(p_message->header.flags.value); + p_message->header.source_port_id = (uint16_t) __REV16(p_message->header.source_port_id); + p_message->header.sequence_id = (uint16_t) __REV16(p_message->header.sequence_id); + + uint32_t correction_upper = (uint32_t) (p_message->header.correction_field >> PTP_SHIFT_32); + uint32_t correction_lower = (uint32_t) (p_message->header.correction_field & UINT32_MAX); + p_message->header.correction_field = ((uint64_t) __REV(correction_lower) << PTP_SHIFT_32) | __REV(correction_upper); + + if (PTP_MESSAGE_TYPE_ANNOUNCE == p_message->header.message_type) + { + p_message->announce.current_utc_offset = (uint16_t) __REV16(p_message->announce.current_utc_offset); + p_message->announce.clock_properties.variance = + (uint16_t) __REV16(p_message->announce.clock_properties.variance); + p_message->announce.steps_removed = (uint16_t) __REV16(p_message->announce.steps_removed); + } + + if ((PTP_MESSAGE_TYPE_MANAGEMENT == p_message->header.message_type) || + (PTP_MESSAGE_TYPE_SIGNALING == p_message->header.message_type)) + { + /* Target Port ID is common to both management and signaling messages. */ + p_message->management.target_port_id = (uint16_t) __REV16(p_message->management.target_port_id); + } + else + { + /* Origin timestamp is common to all other message types. */ + p_message->sync.origin_timestamp.seconds_upper = (uint16_t) __REV16( + p_message->sync.origin_timestamp.seconds_upper); + p_message->sync.origin_timestamp.seconds_lower = __REV(p_message->sync.origin_timestamp.seconds_lower); + p_message->sync.origin_timestamp.nanoseconds = __REV(p_message->sync.origin_timestamp.nanoseconds); + } +} + +/*******************************************************************************************************************//** + * Add an Ethernet header to a packet. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_packet packet to add an Ethernet header to. + * @param[in] packet_length size of the packet in bytes. + **********************************************************************************************************************/ +static void r_ptp_append_ether_header (ptp_instance_ctrl_t * p_instance_ctrl, uint8_t * p_packet, + uint16_t packet_length) +{ + ptp_ether_header_t * p_ether_header = (ptp_ether_header_t *) p_packet; + + /* Write the source MAC address. */ + uint32_t symacru = R_ETHERC_EPTPC->SYMACRU; + uint32_t symacrl = R_ETHERC_EPTPC->SYMACRL; + p_ether_header->source_mac_address[0U] = (uint8_t) (symacru >> 16U) & UINT8_MAX; + p_ether_header->source_mac_address[1U] = (uint8_t) (symacru >> 8U) & UINT8_MAX; + p_ether_header->source_mac_address[2U] = (uint8_t) (symacru >> 0U) & UINT8_MAX; + p_ether_header->source_mac_address[3U] = (uint8_t) (symacrl >> 16U) & UINT8_MAX; + p_ether_header->source_mac_address[4U] = (uint8_t) (symacrl >> 8U) & UINT8_MAX; + p_ether_header->source_mac_address[5U] = (uint8_t) (symacrl >> 0U) & UINT8_MAX; + + if ((PTP_FRAME_FORMAT_ETHERII == p_instance_ctrl->p_cfg->synfp.frame_format) || + (PTP_FRAME_FORMAT_IEEE802_3 == p_instance_ctrl->p_cfg->synfp.frame_format)) + { + /* Write the destination MAC address. */ + memcpy(p_ether_header->destination_mac_address, p_instance_ctrl->p_cfg->synfp.ether.p_primary_mac_addr, + sizeof(p_ether_header->destination_mac_address)); + } + else + { + uint32_t dest_ip_addr = p_instance_ctrl->p_cfg->synfp.ipv4.primary_ip_addr; + dest_ip_addr &= PTP_IP_MULTICAST_ADDRESS_MASK; + + /* Compute the multicast MAC address from the IP address. */ + p_ether_header->destination_mac_address[0U] = (PTP_IP_MULTICAST_MAC_ADDRESS_PREFIX >> 16U) & UINT8_MAX; + p_ether_header->destination_mac_address[1U] = (PTP_IP_MULTICAST_MAC_ADDRESS_PREFIX >> 8U) & UINT8_MAX; + p_ether_header->destination_mac_address[2U] = (PTP_IP_MULTICAST_MAC_ADDRESS_PREFIX >> 0U) & UINT8_MAX; + p_ether_header->destination_mac_address[3U] = (dest_ip_addr >> 16U) & UINT8_MAX; + p_ether_header->destination_mac_address[4U] = (dest_ip_addr >> 8U) & UINT8_MAX; + p_ether_header->destination_mac_address[5U] = (dest_ip_addr >> 0U) & UINT8_MAX; + } + + /* Write the EtherType field. */ + switch (p_instance_ctrl->p_cfg->synfp.frame_format) + { + case PTP_FRAME_FORMAT_ETHERII: + { + p_ether_header->ether_type = (uint16_t) __REV16(PTP_ETHER_TYPE_PTP); + break; + } + + case PTP_FRAME_FORMAT_ETHERII_IPV4_UDP: + { + p_ether_header->ether_type = (uint16_t) __REV16(PTP_ETHER_TYPE_IPV4); + break; + } + + case PTP_FRAME_FORMAT_IEEE802_3: + case PTP_FRAME_FORMAT_IEEE802_3_IPV4_UDP: + { + uint16_t size = (uint16_t) (packet_length - PTP_ETHER_HEADER_SIZE); + p_ether_header->ether_type = (uint16_t) __REV16(size); + break; + } + + default: + { + break; + } + } +} + +/*******************************************************************************************************************//** + * Add the LLC and SNAP headers to the ieee802_3 header. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_packet Packet to add an LLC and SNAP header to. + **********************************************************************************************************************/ +static void r_ptp_append_ieee802_3_llc_snap_header (ptp_instance_ctrl_t * p_instance_ctrl, uint8_t * p_packet) +{ + uint8_t * p_llc_header = p_packet; + uint8_t * p_snap_header = p_packet + PTP_LLC_HEADER_SIZE; + + p_llc_header[PTP_LLC_SAP_SSAP_OFFSET] = PTP_LLC_SAP_SNAP; + p_llc_header[PTP_LLC_SAP_DSAP_OFFSET] = PTP_LLC_SAP_SNAP; + p_llc_header[PTP_LLC_CTRL_OFFSET] = PTP_LLC_CTRL_FORMAT_U; + + uint32_t symacru = R_ETHERC_EPTPC->SYMACRU; + p_snap_header[PTP_SNAP_OID_OFFSET + 0] = (uint8_t) (symacru >> 16U) & UINT8_MAX; + p_snap_header[PTP_SNAP_OID_OFFSET + 1] = (uint8_t) (symacru >> 8U) & UINT8_MAX; + p_snap_header[PTP_SNAP_OID_OFFSET + 2] = (uint8_t) (symacru >> 0U) & UINT8_MAX; + + if ((PTP_FRAME_FORMAT_ETHERII_IPV4_UDP == p_instance_ctrl->p_cfg->synfp.frame_format) || + (PTP_FRAME_FORMAT_IEEE802_3_IPV4_UDP == p_instance_ctrl->p_cfg->synfp.frame_format)) + { + p_snap_header[PTP_SNAP_PID_OFFSET + 0] = PTP_ETHER_TYPE_IPV4 >> 8; + p_snap_header[PTP_SNAP_PID_OFFSET + 1] = PTP_ETHER_TYPE_IPV4 & UINT8_MAX; + } + else + { + p_snap_header[PTP_SNAP_PID_OFFSET + 0] = PTP_ETHER_TYPE_PTP >> 8; + p_snap_header[PTP_SNAP_PID_OFFSET + 1] = PTP_ETHER_TYPE_PTP & UINT8_MAX; + } +} + +/*******************************************************************************************************************//** + * Compute the checksum of an IP header. + * + * @param[in] p_ip_header Pointer to an IP header. + **********************************************************************************************************************/ +uint16_t r_ptp_ip_checksum (uint8_t * p_ip_header) +{ + uint16_t * p_ip_header16 = (uint16_t *) p_ip_header; + + /* Get the IP header length in words. */ + uint32_t ihl = p_ip_header16[0] & 0x0FU; + + /* Compunte checksum. */ + uint32_t sum = 0; + for (uint32_t i = 0; i < ihl * 2; i++) + { + sum += p_ip_header16[i]; + } + + /* Add the carry bits to the sum and clear them. */ + uint32_t carry = sum >> 16U; + sum &= UINT16_MAX; + sum += carry; + + /* Do it again in case a carry occurred when adding carry bits. */ + carry = sum >> 16U; + sum &= UINT16_MAX; + sum += carry; + + /* One's complement the result. */ + uint16_t sum16 = sum & UINT16_MAX; + sum16 = (uint16_t) ~sum16 & UINT16_MAX; + + return sum16; +} + +/*******************************************************************************************************************//** + * Add an IP and UDP header to a packet. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_packet Packet to add an IP and UDP header to. + * @param[in] packet_length Size of the packet in bytes. + **********************************************************************************************************************/ +static void r_ptp_append_ipv4_udp_header (ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t * p_packet, + uint16_t packet_length) +{ + ptp_ip_header_t * p_ip_header = (ptp_ip_header_t *) p_packet; + ptp_udp_header_t * p_udp_header = (ptp_udp_header_t *) (p_packet + sizeof(ptp_ip_header_t)); + + p_ip_header->version = PTP_IP_VERSION; + p_ip_header->ihl = 5; + p_ip_header->tos = p_instance_ctrl->p_cfg->synfp.ipv4.general_tos; + p_ip_header->total_length = (uint16_t) __REV16(packet_length); + p_ip_header->id = 0; + p_ip_header->flags = 0; + p_ip_header->fragment_offset = 0; + p_ip_header->ttl = p_instance_ctrl->p_cfg->synfp.ipv4.primary_ttl; + p_ip_header->protocol = PTP_IP_PROTOCOL_UDP; + p_ip_header->checksum = 0; + p_ip_header->source_address = __REV(R_ETHERC_EPTPC->SYIPADDRR); + p_ip_header->destination_address = __REV(p_instance_ctrl->p_cfg->synfp.ipv4.primary_ip_addr); + p_udp_header->source_port = (uint16_t) __REV16(p_instance_ctrl->p_cfg->synfp.ipv4.general_udp_port); + p_udp_header->destination_port = (uint16_t) __REV16(p_instance_ctrl->p_cfg->synfp.ipv4.general_udp_port); + p_udp_header->length = (uint16_t) __REV16((packet_length - sizeof(ptp_ip_header_t))); + p_udp_header->checksum = 0; + + p_ip_header->checksum = r_ptp_ip_checksum(p_packet); +} + +/*******************************************************************************************************************//** + * Removes the IEEE802.3 + LLC + SNAP header from a packet. + * + * @param[in] p_llc_snap_packet Pointer to an IEEE802.3 + LLC + SNAP frame. + * @param[in] llc_snap_packet_length Length of the packet. + * @param[out] p_ether_type EtherType field defined in the SNAP header. + * @param[out] p_payload Pointer to a pointer to store the payload of the packet. + * @param[out] payload_length Pointer to store the payload length. + * + * @retval FSP_SUCCESS The frame was successfully processed. + * @retval FSP_ERR_ASSERTION There was an error parsing the frame. + **********************************************************************************************************************/ +static fsp_err_t r_ptp_process_llc_snap_packet (uint8_t const * const p_llc_snap_packet, + uint16_t llc_snap_packet_length, + uint16_t * p_ether_type, + uint8_t ** const p_payload, + uint16_t * const payload_length) +{ + /* Extract LLC header information. */ + uint8_t dsap = p_llc_snap_packet[PTP_LLC_SAP_DSAP_OFFSET] & PTP_LLC_SAP_MASK; + uint8_t ssap = p_llc_snap_packet[PTP_LLC_SAP_SSAP_OFFSET] & PTP_LLC_SAP_MASK; + uint8_t ctrl = p_llc_snap_packet[PTP_LLC_CTRL_OFFSET]; + + if ((PTP_LLC_SAP_SNAP != dsap) || (PTP_LLC_SAP_SNAP != ssap) || (PTP_LLC_CTRL_FORMAT_U != ctrl)) + { + + /* Packet does not have snap header. */ + return FSP_ERR_ASSERTION; + } + + *p_ether_type = (uint16_t) ((p_llc_snap_packet[PTP_LLC_HEADER_SIZE + PTP_SNAP_PID_OFFSET + 0U] << 8U) | + (p_llc_snap_packet[PTP_LLC_HEADER_SIZE + PTP_SNAP_PID_OFFSET + 1U] << 0U)); + + *p_payload = (uint8_t *) &p_llc_snap_packet[PTP_LLC_HEADER_SIZE + PTP_SNAP_HEADER_SIZE]; + *payload_length = (uint16_t) (llc_snap_packet_length - 8U); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Removes IP header from a packet. + * + * @param[in] p_instance_ctrl Instance control block + * @param[in] p_ip_packet Pointer to an IP packet. + * @param[in] ip_packet_length Length of the packet. + * @param[out] p_payload Pointer to a pointer to store the payload of the packet. + * @param[out] payload_length Pointer to store the payload length. + * + * @retval FSP_SUCCESS The frame was successfully processed. + * @retval FSP_ERR_ASSERTION There was an error parsing the frame. + **********************************************************************************************************************/ +static fsp_err_t r_ptp_process_ipv4_udp_packet (ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_ip_packet, + uint16_t ip_packet_length, + uint8_t ** const p_payload, + uint16_t * const payload_length) +{ + ptp_ip_header_t * p_ip_header = (ptp_ip_header_t *) p_ip_packet; + p_ip_header->total_length = (uint16_t) __REV16(p_ip_header->total_length); + p_ip_header->destination_address = __REV(p_ip_header->destination_address); + uint32_t header_size = p_ip_header->ihl * 4U; + + ptp_udp_header_t * p_udp_header = (ptp_udp_header_t *) (p_ip_packet + header_size); + p_udp_header->destination_port = (uint16_t) __REV16(p_udp_header->destination_port); + p_udp_header->source_port = (uint16_t) __REV16(p_udp_header->source_port); + p_udp_header->length = (uint16_t) __REV16(p_udp_header->length); + + /* Verify that the packet is a valid IPv4 + UDP packet. */ + if ((PTP_IP_VERSION != p_ip_header->version) || + (p_ip_header->total_length != ip_packet_length) || + (PTP_IP_PROTOCOL_UDP != p_ip_header->protocol)) + { + return FSP_ERR_ASSERTION; + } + + /* Check to make sure the destination ip address matches the configured ptp message IPv4 address. */ + if ((p_instance_ctrl->p_cfg->synfp.ipv4.primary_ip_addr != p_ip_header->destination_address) && + (p_instance_ctrl->p_cfg->synfp.ipv4.pdelay_ip_addr != p_ip_header->destination_address)) + { + return FSP_ERR_ASSERTION; + } + + /* Check to make sure the destination port matches the configured ptp message UDP port. */ + if ((p_instance_ctrl->p_cfg->synfp.ipv4.general_udp_port != p_udp_header->destination_port) && + (p_instance_ctrl->p_cfg->synfp.ipv4.event_udp_port != p_udp_header->destination_port)) + { + return FSP_ERR_ASSERTION; + } + + *p_payload = (uint8_t *) (p_ip_packet + header_size + PTP_UDP_HEADER_SIZE); + *payload_length = (uint16_t) (p_udp_header->length - PTP_UDP_HEADER_SIZE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Processes PTP messages and then calls a user callback. + * + * @param[in] p_instance_ctrl Instance control block + * @param[in] p_ptp_packet Pointer to an IP packet. + * @param[in] ptp_packet_length Length of the packet. + * + * @retval FSP_SUCCESS The frame was successfully processed. + **********************************************************************************************************************/ +static fsp_err_t r_ptp_process_ptp_packet (ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_ptp_packet, + uint16_t ptp_packet_length) +{ + FSP_PARAMETER_NOT_USED(ptp_packet_length); + + ptp_message_t * p_ptp_message = (ptp_message_t *) p_ptp_packet; + + /* Convert message fields to little endian. */ + r_ptp_message_endian_swap(p_ptp_message); + + uint16_t message_type_size; + + /* Calculate the size of the PTP message excluding TLV data. */ + switch (p_ptp_message->header.message_type) + { + case PTP_MESSAGE_TYPE_ANNOUNCE: + { + message_type_size = sizeof(ptp_message_header_t) + sizeof(ptp_message_announce_t); + break; + } + + case PTP_MESSAGE_TYPE_MANAGEMENT: + { + message_type_size = sizeof(ptp_message_header_t) + sizeof(ptp_message_management_t); + break; + } + + case PTP_MESSAGE_TYPE_SIGNALING: + { + message_type_size = sizeof(ptp_message_header_t) + sizeof(ptp_message_signaling_t); + break; + } + + default: + { + /* Other PTP messages do not have TLV data. */ + message_type_size = p_ptp_message->header.message_length; + break; + } + } + + /* Calculate the start of TLV data. */ + uint8_t const * p_tlv_data = NULL; + uint16_t tlv_data_size = (uint16_t) (p_ptp_message->header.message_length - message_type_size); + + if (0 < tlv_data_size) + { + p_tlv_data = p_ptp_packet + message_type_size; + } + + ptp_callback_args_t callback_args = + { + .event = PTP_EVENT_MESSAGE_RECEIVED, + .p_message = p_ptp_message, + .p_tlv_data = p_tlv_data, + .tlv_data_size = tlv_data_size, + .p_context = p_instance_ctrl->p_cfg->p_context + }; + + /* Send the application the processed PTP message. */ + p_instance_ctrl->p_cfg->p_callback(&callback_args); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Processes incoming ethernet packet. Notify the user if the packet contiains a PTP message. + * + * @param[in] p_instance_ctrl Instance control block + * @param[in] p_ether_packet Pointer to an IP packet. + * @param[in] ether_packet_length Length of the packet. + * + * @retval FSP_SUCCESS The frame was successfully processed. + * @retval FSP_ERR_ASSERTION There was an error parsing the frame. + **********************************************************************************************************************/ +static fsp_err_t r_ptp_process_ether_packet (ptp_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_ether_packet, + uint16_t ether_packet_length) +{ + fsp_err_t err; + + ptp_ether_header_t * p_ether_header = (ptp_ether_header_t *) p_ether_packet; + + uint16_t ether_type = (uint16_t) __REV16(p_ether_header->ether_type); + + uint16_t ether_header_length = + (uint16_t) (PTP_ETHER_HEADER_SIZE + p_instance_ctrl->p_cfg->p_edmac_instance->p_cfg->padding); + uint8_t * p_payload = (uint8_t *) p_ether_packet + ether_header_length; + uint16_t payload_length = (uint16_t) (ether_packet_length - ether_header_length); + + /* + * If length is less than the max frame length then the ethertype field contains the length of the packet. + * This means that this frame is an IEEE802.3 packet. + */ + if (PTP_LLC_MAX_LEN >= ether_type) + { + /* Remove the IEEE802.3 + LLC + SNAP headers. */ + err = r_ptp_process_llc_snap_packet(p_payload, payload_length, ðer_type, &p_payload, &payload_length); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (PTP_ETHER_TYPE_IPV4 == ether_type) + { + /* Remove the IP + UDP headers. */ + err = r_ptp_process_ipv4_udp_packet(p_instance_ctrl, p_payload, payload_length, &p_payload, &payload_length); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + else if (PTP_ETHER_TYPE_PTP != ether_type) + { + + /* Unsupported Ethernet packet type. */ + return FSP_ERR_ASSERTION; + } + else + { + } + + err = r_ptp_process_ptp_packet(p_instance_ctrl, p_payload, payload_length); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Callback from internal EDMAC module. + * + * Notifies the user of all transmitted and received ptp messages using ptp_cfg_t::p_callback. + * + * @param[in] p_args Pointer to callback args. + **********************************************************************************************************************/ +void r_ptp_edmac_callback (edmac_callback_args_t * p_args) +{ + ptp_instance_t * p_ptp_instance = (ptp_instance_t *) p_args->p_context; + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) p_ptp_instance->p_ctrl; + edmac_instance_t * p_edmac_instance = p_ptp_instance->p_cfg->p_edmac_instance; + + /* Handle frame receive IRQ. */ + if (0 != (p_args->status & R_ETHERC_EDMAC_EESR_FR_Msk)) + { + edmac_desc_t * p_desc = NULL; + + uint32_t desc_status = 0; + do + { + /* Get the next receive buffer descriptor. */ + fsp_err_t err = R_EDMAC_DescriptorGet(p_edmac_instance->p_ctrl, + EDMAC_DESC_RECEIVE, + p_instance_ctrl->rx_buffer_index, + &p_desc); + if (FSP_SUCCESS != err) + { + FSP_LOG_PRINT("Failed to get receive buffer descriptor."); + } + + desc_status = p_desc->status.raw_b.active; + + /* Check if the buffer descriptor is active. */ + if (0U == desc_status) + { + /* Process the received Ethernet packet and notify the user if it contains a PTP message. */ + err = + r_ptp_process_ether_packet(p_instance_ctrl, + p_desc->p_buffer, + (uint16_t) (p_desc->size + + p_instance_ctrl->p_cfg->p_edmac_instance->p_cfg->padding)); + if (FSP_SUCCESS != err) + { + FSP_LOG_PRINT("Failed to parse packet because the format was invalid."); + } + + /* Set the buffer descriptor to active so that it receive future Ethernet packets. */ + err = R_EDMAC_DescriptorUpdate(p_edmac_instance->p_ctrl, + EDMAC_DESC_RECEIVE, + p_instance_ctrl->rx_buffer_index, + p_desc->p_buffer, + p_desc->buffer_size); + if (FSP_SUCCESS != err) + { + FSP_LOG_PRINT("Failed to re-activate the processed packet."); + } + + /* Move to the next buffer descriptor. */ + p_instance_ctrl->rx_buffer_index++; + if (p_instance_ctrl->rx_buffer_index == p_edmac_instance->p_cfg->num_rx_desc) + { + p_instance_ctrl->rx_buffer_index = 0; + } + } + + /* + * Continue reading packets until an active descriptor is found. This indicates there are + * no more inactive buffers to process. + */ + } while (0 == desc_status); + } + + /* Handle transmit Complete IRQ. */ + if (0U != (p_args->status & R_ETHERC_EDMAC_EESR_TC_Msk)) + { + edmac_desc_status_t status; + uint32_t tx_buffer_write_index = p_instance_ctrl->tx_buffer_write_index; + uint32_t tx_buffer_complete_index = p_instance_ctrl->tx_buffer_complete_index; + do + { + edmac_desc_t * p_desc; + + /* Get the next transmit buffer descriptor. */ + fsp_err_t err = R_EDMAC_DescriptorGet(p_edmac_instance->p_ctrl, + EDMAC_DESC_TRANSMIT, + tx_buffer_complete_index, + &p_desc); + if (FSP_SUCCESS != err) + { + FSP_LOG_PRINT("Failed to get transmit buffer descriptor."); + } + + status = p_desc->status; + + /* If the status is no longer active, then the buffer has been transmitted. */ + if (0U == status.raw_b.active) + { + ptp_callback_args_t callback_args; + callback_args.event = PTP_EVENT_MESSAGE_TRANSMIT_COMPLETE; + p_instance_ctrl->p_cfg->p_callback(&callback_args); + } + + tx_buffer_complete_index++; + if (tx_buffer_complete_index == p_edmac_instance->p_cfg->num_tx_desc) + { + tx_buffer_complete_index = 0U; + } + } while (tx_buffer_complete_index != tx_buffer_write_index && 0U == status.raw_b.active); + + p_instance_ctrl->tx_buffer_complete_index = tx_buffer_complete_index; + } +} + +/*******************************************************************************************************************//** + * PTP MINT interrupt handler + * + * Notifies the user of all ptp events using ptp_cfg_t::p_callback. + **********************************************************************************************************************/ +void r_ptp_mint_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + ptp_callback_args_t callback_args = + { + .p_message = NULL + }; + + /* ETHER_MINT Interrupt Source Status Register. */ + uint32_t miesr = R_ETHERC_EPTPC_COMMON->MIESR; + + /* STCA Status Register. */ + uint32_t stsr = R_ETHERC_EPTPC_COMMON->STSR; + + /* SYNFP Status Register. */ + uint32_t sysr = R_ETHERC_EPTPC->SYSR; + + /* Notify user of STCA events. */ + uint32_t stsr_tmp = stsr; + while (stsr_tmp) + { + /* Get the offset of the next status bit that is set to one. */ + uint32_t event = 31U - __CLZ(stsr_tmp); + + /* Convert the status offset to its corresponding enum value. */ + callback_args.event = (ptp_event_t) (event + PTP_EVENT_SYNC_ACQUIRED); + + /* Notify the application of the event. */ + p_instance_ctrl->p_cfg->p_callback(&callback_args); + + /* Clear the status bit so the next event can be processed. */ + stsr_tmp &= ~(1U << event); + } + + /* Notify user of SYNFP events. */ + uint32_t sysr_tmp = sysr; + while (sysr_tmp) + { + /* Get the offset of the next status bit that is set to one. */ + uint32_t event = 31U - __CLZ(sysr_tmp); + + /* Convert the status offset to its corresponding enum value. */ + callback_args.event = (ptp_event_t) event; + + /* Notify the application of the event. */ + p_instance_ctrl->p_cfg->p_callback(&callback_args); + + /* Clear the status bit so the next event can be processed. */ + sysr_tmp &= ~(1U << event); + } + + /* Notify user of Pulse Timer rising edge events. */ + uint32_t miesr_tmp = miesr >> R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Pos; + while (miesr_tmp) + { + /* Get the offset of the next status bit that is set to one. */ + uint32_t event = 31U - __CLZ(miesr_tmp); + + /* Convert the status offset to its corresponding enum value. */ + callback_args.pulse_timer_channel = event; + callback_args.event = PTP_EVENT_PULSE_TIMER_MINT_RISING_EDGE; + + /* Notify the application of the event. */ + p_instance_ctrl->p_cfg->p_callback(&callback_args); + + /* Clear the status bit so the next event can be processed. */ + miesr_tmp &= ~(1U << event); + } + + /* Handle STCA events. */ + + if ((stsr & R_ETHERC_EPTPC_COMMON_STSR_W10D_Msk) != 0) + { + /* Issue a directive to capture information. */ + R_ETHERC_EPTPC_COMMON->GETINFOR = 1U; + + /* Waiting for information capturing to complete + * (See figure "Example procedure for software-triggered acquisition of the worst 10 values" + * in the EPTPC section of the relevant hardware manual). */ + FSP_HARDWARE_REGISTER_WAIT(R_ETHERC_EPTPC_COMMON->GETINFOR, 0U); + + /** Disable IRQs because PW10VRn, and MW10Rn registers must be set in consecutive operations + * (See "Positive Gradient Limit Register (PLIMITRU, PLIMITRM, PLIMITRL)" description + * in the EPTPC section of the relevant hardware manual). */ + __disable_irq(); + + /* Read the gradient worst 10 values. */ + uint32_t pw10vru = R_ETHERC_EPTPC_COMMON->PW10VRU; + uint32_t pw10vrm = R_ETHERC_EPTPC_COMMON->PW10VRM; + uint32_t pw10vrl = R_ETHERC_EPTPC_COMMON->PW10VRL; + uint32_t mw10ru = R_ETHERC_EPTPC_COMMON->MW10RU; + uint32_t mw10rm = R_ETHERC_EPTPC_COMMON->MW10RM; + uint32_t mw10rl = R_ETHERC_EPTPC_COMMON->MW10RL; + + /* Write the gradient worst 10 values to the gradient limit registers. */ + R_ETHERC_EPTPC_COMMON->PLIMITRU = pw10vru & R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Msk; + R_ETHERC_EPTPC_COMMON->PLIMITRM = pw10vrm; + R_ETHERC_EPTPC_COMMON->PLIMITRL = pw10vrl; + R_ETHERC_EPTPC_COMMON->MLIMITRU = mw10ru & R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Msk; + R_ETHERC_EPTPC_COMMON->MLIMITRM = mw10rm; + R_ETHERC_EPTPC_COMMON->MLIMITRL = mw10rl; + + __enable_irq(); + } + + /* Handle SYNFP events. */ + + if ((sysr & R_ETHERC_EPTPC_SYSR_OFMUD_Msk) != 0) + { + /* offsetFromMaster value updated. */ + if (0U == R_ETHERC_EPTPC_COMMON->SYNSTARTR) + { + /* Clear SYNTOUT and SYNCOUT flags immediately after starting synchronization + * (See "STCA Status Register (STSR)" description + * in the EPTPC section of the relevant hardware manual). */ + stsr |= R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Msk | R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Msk; + + /* Start synchronization. */ + R_ETHERC_EPTPC_COMMON->SYNSTARTR = 1U; + + if (PTP_CLOCK_CORRECTION_MODE2 == p_instance_ctrl->p_cfg->stca.clock_correction_mode) + { + /* Start acquiring gradient worst 10 values. */ + R_ETHERC_EPTPC_COMMON->GETW10R = 1U; + } + } + } + + if ((sysr & R_ETHERC_EPTPC_SYSR_INTCHG_Msk) != 0) + { + /* Receive LogMessageInterval value changed. */ + + /* Read the SYNFP Received Log Interval register. */ + uint32_t syrlir = R_ETHERC_EPTPC->SYRLIR; + + /* Get the delay_resp log interval. */ + int8_t sync_log_int = (int8_t) ((syrlir & R_ETHERC_EPTPC_SYRLIR_SYNC_Msk) >> R_ETHERC_EPTPC_SYRLIR_SYNC_Pos); + + /* Recalculate Sync message timeout based on the new Sync message interval. */ + R_ETHERC_EPTPC_COMMON->SYNTOR = r_ptp_calculate_timeout(p_instance_ctrl, sync_log_int); + R_ETHERC_EPTPC->SYRVLDR = R_ETHERC_EPTPC_SYRVLDR_STUP_Msk; + } + + /* Clear interrupt status flags. */ + + R_ETHERC_EPTPC_COMMON->MIESR = miesr; + R_ETHERC_EPTPC_COMMON->STSR = stsr; + R_ETHERC_EPTPC->SYSR = sysr; + + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * PTP IPLS interrupt handler + * + * Notifies the user of all ptp pulse timer events using ptp_cfg_t::p_pulse_timer_callback. + **********************************************************************************************************************/ +void r_ptp_ipls_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ptp_instance_ctrl_t * p_instance_ctrl = (ptp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + R_BSP_IrqStatusClear(irq); + + ptp_callback_args_t callback_args = + { + .p_message = NULL + }; + + callback_args.event = PTP_EVENT_PULSE_TIMER_IPLS_COMMON; + + /* Notify the application of the event. */ + p_instance_ctrl->p_cfg->p_callback(&callback_args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_qspi/r_qspi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_qspi/r_qspi.c new file mode 100644 index 0000000000..ebf8f794f3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_qspi/r_qspi.c @@ -0,0 +1,888 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_qspi.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define QSPI_PRV_OPEN (0x51535049) + +#define QSPI_PRV_MASK_UPPER_4_BITS_OF_BYTE (0xF0U) +#define QSPI_PRV_MASK_LOWER_4_BITS_OF_BYTE (0x0FU) + +#define QSPI_PRV_LSB_NIBBLE_CLEARED (0xEEEEEEEE) +#define QSPI_PRV_EVEN_BITS_CLEARED (0xAAAA) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Number of address bytes in 4 byte address mode. */ +#define QSPI_4_BYTE_ADDRESS (4U) + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM + +static void qspi_d0_byte_write_quad_mode(uint8_t byte); + +static void qspi_d0_byte_write_dual_mode(uint8_t byte); + +#endif + +static void qspi_d0_byte_write_standard(uint8_t byte); + +static void r_qspi_direct_write_sub(uint8_t const * const p_src, uint32_t const bytes, bool const read_after_write); + +static void r_qspi_direct_read_sub(uint8_t * const p_dest, uint32_t const bytes); +static bool r_qspi_status_sub(qspi_instance_ctrl_t * p_instance_ctrl); + +static fsp_err_t r_qspi_xip(qspi_instance_ctrl_t * p_instance_ctrl, uint8_t code, bool enter_mode); + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + +static fsp_err_t r_qspi_param_checking_dcom(qspi_instance_ctrl_t * p_instance_ctrl); + +static fsp_err_t qspi_program_param_check(qspi_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +#if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM + +/* Page program command. Index by [data_lines]. data_lines is 0 for 1 data line, 1 for 2 data lines, or + * 2 for 4 data lines. */ +static void(*const gp_qspi_prv_byte_write[3]) (uint8_t byte) = +{ + qspi_d0_byte_write_standard, + qspi_d0_byte_write_dual_mode, + qspi_d0_byte_write_quad_mode +}; +#endif + +/*******************************************************************************************************************//** + * @addtogroup QSPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +const spi_flash_api_t g_qspi_on_spi_flash = +{ + .open = R_QSPI_Open, + .directWrite = R_QSPI_DirectWrite, + .directRead = R_QSPI_DirectRead, + .directTransfer = R_QSPI_DirectTransfer, + .spiProtocolSet = R_QSPI_SpiProtocolSet, + .write = R_QSPI_Write, + .erase = R_QSPI_Erase, + .statusGet = R_QSPI_StatusGet, + .xipEnter = R_QSPI_XipEnter, + .xipExit = R_QSPI_XipExit, + .bankSet = R_QSPI_BankSet, + .autoCalibrate = R_QSPI_AutoCalibrate, + .close = R_QSPI_Close, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Open the QSPI driver module. After the driver is open, the QSPI can be accessed like internal flash memory starting + * at address 0x60000000. + * + * Implements @ref spi_flash_api_t::open. + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl or p_cfg is NULL. + * @retval FSP_ERR_ALREADY_OPEN Driver has already been opened with the same p_instance_ctrl. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_Open (spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN(QSPI_PRV_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT((p_cfg->dummy_clocks >= SPI_FLASH_DUMMY_CLOCKS_3 && p_cfg->dummy_clocks <= SPI_FLASH_DUMMY_CLOCKS_17) || + p_cfg->dummy_clocks == SPI_FLASH_DUMMY_CLOCKS_DEFAULT); +#endif + + /* Enable clock to the QSPI block */ + R_BSP_MODULE_START(FSP_IP_QSPI, 0U); + + qspi_extended_cfg_t * p_cfg_extend = (qspi_extended_cfg_t *) p_cfg->p_extend; + + /* Initialized unused registers. */ + R_QSPI->SFMCST = 0U; + R_QSPI->SFMSIC = 0U; + R_QSPI->SFMPMD = 0U; + R_QSPI->SFMCNT1 = 0U; + + /* Set the initial SPI protocol. */ + R_QSPI->SFMSPC = R_QSPI_SFMSPC_SFMSDE_Msk | p_cfg->spi_protocol; + + /* Set the SPI clock rate */ + R_QSPI->SFMSKC = p_cfg_extend->qspclk_div; + + /* Set the address mode. */ + R_QSPI->SFMSAC = p_cfg->address_bytes; + + uint32_t dummy_clocks = 0; + if (SPI_FLASH_DUMMY_CLOCKS_DEFAULT != p_cfg->dummy_clocks) + { + /* Convert dummy cycles setting to the register value. */ + dummy_clocks = (uint32_t) p_cfg->dummy_clocks - 2U; + } + + /* Set the number of dummy cycles in QSPI peripheral */ + R_QSPI->SFMSDC = dummy_clocks | R_QSPI_SFMSDC_SFMXD_Msk; + + /* Set configured minimum high level width for QSSL signal. */ + R_QSPI->SFMSSC = p_cfg_extend->min_qssl_deselect_cycles | R_QSPI_SFMSSC_SFMSLD_Msk | R_QSPI_SFMSSC_SFMSHD_Msk; + + /* Set the read mode based on user configuration. */ + R_QSPI->SFMSMD = R_QSPI_SFMSMD_SFMPFE_Msk | p_cfg->read_mode; + + /* Initialize control block. */ + p_instance_ctrl->p_cfg = p_cfg; + + /* This is the index into g_qspi_prv_program_command. The index should be 0 for data on one line, 1 for data on + * 2 lines, and 2 for data on 4 lines. */ + if (SPI_FLASH_READ_MODE_STANDARD == p_cfg->read_mode) + { + p_instance_ctrl->data_lines = SPI_FLASH_DATA_LINES_1; + } + else + { + p_instance_ctrl->data_lines = (spi_flash_data_lines_t) (31 - __CLZ(p_cfg->read_mode)); + } + + /* The memory size is read from the device if needed. */ + p_instance_ctrl->total_size_bytes = 0U; + + p_instance_ctrl->open = QSPI_PRV_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes raw data directly to the QSPI. + * + * Implements @ref spi_flash_api_t::directWrite. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_DirectWrite (spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_qspi_param_checking_dcom(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(bytes > 0); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Write data to QSPI. */ + r_qspi_direct_write_sub(p_src, bytes, read_after_write); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads raw data directly from the QSPI. This API can only be called after R_QSPI_DirectWrite with read_after_write + * set to true. + * + * Implements @ref spi_flash_api_t::directRead. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function must be called after R_QSPI_DirectWrite with read_after_write set + * to true. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_DirectRead (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + + FSP_ASSERT(NULL != p_dest); + FSP_ASSERT(bytes > 0); + FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* This API can only be called after R_QSPI_DirectWrite with the read_after_write parameter set to true. The QSPI + * peripheral must already be in direct communications mode. */ + FSP_ERROR_RETURN(1U == R_QSPI->SFMCMD, FSP_ERR_INVALID_MODE); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Read data from QSPI. */ + r_qspi_direct_read_sub(p_dest, bytes); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read/Write raw data directly with the OctaFlash/OctaRAM device. Unsupported by QSPI. + * + * Implements @ref spi_flash_api_t::directTransfer. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by QSPI. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_DirectTransfer (spi_flash_ctrl_t * p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_transfer); + FSP_PARAMETER_NOT_USED(direction); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Enters XIP (execute in place) mode. + * + * Implements @ref spi_flash_api_t::xipEnter. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_XipEnter (spi_flash_ctrl_t * p_ctrl) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + fsp_err_t err; + err = r_qspi_xip(p_instance_ctrl, p_instance_ctrl->p_cfg->xip_enter_command, true); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Exits XIP (execute in place) mode. + * + * Implements @ref spi_flash_api_t::xipExit. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_XipExit (spi_flash_ctrl_t * p_ctrl) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + fsp_err_t err; + err = r_qspi_xip(p_instance_ctrl, p_instance_ctrl->p_cfg->xip_exit_command, false); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Program a page of data to the flash. + * + * Implements @ref spi_flash_api_t::write. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_Write (spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = qspi_program_param_check(p_instance_ctrl, p_src, p_dest, byte_count); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + uint32_t chip_address = (uint32_t) p_dest - (uint32_t) QSPI_DEVICE_START_ADDRESS + R_QSPI->SFMCNT1; + + bool restore_spi_mode = false; + void (* write_command)(uint8_t byte) = qspi_d0_byte_write_standard; + void (* write_address)(uint8_t byte) = qspi_d0_byte_write_standard; + +#if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM + + /* If the peripheral is in extended SPI mode, and the configuration provided in the BSP allows for programming on + * multiple data lines, and a unique command is provided for the required mode, update the SPI protocol to send + * data on multiple lines. */ + if ((SPI_FLASH_DATA_LINES_1 != p_instance_ctrl->data_lines) && + (SPI_FLASH_PROTOCOL_EXTENDED_SPI == R_QSPI->SFMSPC_b.SFMSPI)) + { + R_QSPI->SFMSPC_b.SFMSPI = p_instance_ctrl->data_lines; + + restore_spi_mode = true; + + /* Write command in extended SPI mode on one line. */ + write_command = gp_qspi_prv_byte_write[p_instance_ctrl->data_lines]; + + if (SPI_FLASH_DATA_LINES_1 == p_instance_ctrl->p_cfg->page_program_address_lines) + { + /* Write address in extended SPI mode on one line. */ + write_address = gp_qspi_prv_byte_write[p_instance_ctrl->data_lines]; + } + } +#endif + + /* Enter Direct Communication mode */ + R_QSPI->SFMCMD = 1; + + /* Send command to enable writing */ + write_command(p_instance_ctrl->p_cfg->write_enable_command); + + /* Close the SPI bus cycle. See "Generating the SPI Bus Cycle during Direct Communication" + * in the QSPI section of the relevant hardware manual. */ + R_QSPI->SFMCMD = 1; + + /* Send command to write data */ + write_command(p_instance_ctrl->p_cfg->page_program_command); + + /* Write the address. */ + if ((p_instance_ctrl->p_cfg->address_bytes & R_QSPI_SFMSAC_SFMAS_Msk) == SPI_FLASH_ADDRESS_BYTES_4) + { + /* Send the most significant byte of the address */ + write_address((uint8_t) (chip_address >> 24)); + } + + /* Send the remaining bytes of the address */ + write_address((uint8_t) (chip_address >> 16)); + write_address((uint8_t) (chip_address >> 8)); + write_address((uint8_t) (chip_address)); + + /* Write the data. */ + uint32_t index = 0; + while (index < byte_count) + { + /* Read the device memory into the passed in buffer */ + R_QSPI->SFMCOM = p_src[index]; + index++; + } + + /* Close the SPI bus cycle. See "Generating the SPI Bus Cycle during Direct Communication" + * in the QSPI section of the relevant hardware manual. */ + R_QSPI->SFMCMD = 1; + + /* If the SPI protocol was modified in this function, restore it. */ + if (restore_spi_mode) + { + /* Restore SPI mode to extended SPI mode. */ + R_QSPI->SFMSPC_b.SFMSPI = SPI_FLASH_PROTOCOL_EXTENDED_SPI; + } + + /* Return to ROM access mode */ + R_QSPI->SFMCMD = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. + * For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE. + * + * Implements @ref spi_flash_api_t::erase. + * + * @retval FSP_SUCCESS The command to erase the flash was executed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_device_address is NULL, or byte_count doesn't match an erase + * size defined in spi_flash_cfg_t, or device is in XIP mode. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_Erase (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_qspi_param_checking_dcom(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_device_address); +#endif + + uint16_t erase_command = 0; + uint32_t chip_address = (uint32_t) p_device_address - QSPI_DEVICE_START_ADDRESS + R_QSPI->SFMCNT1; + bool send_address = true; + + for (uint32_t index = 0; index < p_instance_ctrl->p_cfg->erase_command_list_length; index++) + { + /* If requested byte_count is supported by underlying flash, store the command. */ + if (byte_count == p_instance_ctrl->p_cfg->p_erase_command_list[index].size) + { + if (SPI_FLASH_ERASE_SIZE_CHIP_ERASE == byte_count) + { + /* Don't send address for chip erase. */ + send_address = false; + } + + erase_command = p_instance_ctrl->p_cfg->p_erase_command_list[index].command; + break; + } + } + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U != erase_command); +#endif + + /* Enter direct communication mode */ + R_QSPI->SFMCMD = 1U; + + /* Enable write. */ + R_QSPI->SFMCOM = p_instance_ctrl->p_cfg->write_enable_command; + + /* Close the SPI bus cycle. See "Generating the SPI Bus Cycle during Direct Communication" + * in the QSPI section of the relevant hardware manual. */ + R_QSPI->SFMCMD = 1U; + + /* Send erase command. */ + R_QSPI->SFMCOM = erase_command; + + /* Send address if this is not a chip erase command. */ + if (send_address) + { + if ((p_instance_ctrl->p_cfg->address_bytes & R_QSPI_SFMSAC_SFMAS_Msk) == SPI_FLASH_ADDRESS_BYTES_4) + { + R_QSPI->SFMCOM = (uint8_t) (chip_address >> 24); + } + + R_QSPI->SFMCOM = (uint8_t) (chip_address >> 16); + R_QSPI->SFMCOM = (uint8_t) (chip_address >> 8); + R_QSPI->SFMCOM = (uint8_t) (chip_address); + } + + /* Close the SPI bus cycle. See "Generating the SPI Bus Cycle during Direct Communication" + * in the QSPI section of the relevant hardware manual. */ + R_QSPI->SFMCMD = 1U; + + /* Exit direct communication mode */ + R_QSPI->SFMCMD = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Gets the write or erase status of the flash. + * + * Implements @ref spi_flash_api_t::statusGet. + * + * @retval FSP_SUCCESS The write status is in p_status. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_status is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_StatusGet (spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Do not enter direct communication mode from XIP mode. See reference note in "Using Direct + * Communication Mode" in the QSPI section of the relevant hardware manual. */ + FSP_ERROR_RETURN(0U == R_QSPI->SFMSDC_b.SFMXST, FSP_ERR_INVALID_MODE); +#endif + + /* Read device status. */ + p_status->write_in_progress = r_qspi_status_sub(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Selects the bank to access. A bank is a 64MB sliding access window into the QSPI device flash memory space. To access + * chip address 0x4000000, select bank 1, then read from internal flash address 0x60000000. To access chip address + * 0x8001000, select bank 2, then read from internal flash address 0x60001000. + * + * This function is not required for memory devices less than or equal to 512 Mb (64MB). + * + * Implements @ref spi_flash_api_t::bankSet. + * + * @retval FSP_SUCCESS Bank successfully selected. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_BankSet (spi_flash_ctrl_t * p_ctrl, uint32_t bank) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Select the requested bank. */ + R_QSPI->SFMCNT1 = bank << R_QSPI_SFMCNT1_QSPI_EXT_Pos; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the SPI protocol. + * + * Implements @ref spi_flash_api_t::spiProtocolSet. + * + * @retval FSP_SUCCESS SPI protocol updated on MCU peripheral. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid SPI protocol requested. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_SpiProtocolSet (spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(SPI_FLASH_PROTOCOL_QPI >= spi_protocol, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Update the SPI protocol. */ + + /* The cast is used to prevent a warning that not all values of spi_flash_protocol_t fit in SFMSPI. spi_protocol is + * verified to fit in SFMSPI in parameter checking above. */ + R_QSPI->SFMSPC_b.SFMSPI = (uint32_t) spi_protocol & 3U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Auto-calibrate the OctaRAM device using the preamble pattern. Unsupported by QSPI. + * Implements @ref spi_flash_api_t::autoCalibrate. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by QSPI + **********************************************************************************************************************/ +fsp_err_t R_QSPI_AutoCalibrate (spi_flash_ctrl_t * p_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Close the QSPI driver module. + * + * Implements @ref spi_flash_api_t::close. + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_QSPI_Close (spi_flash_ctrl_t * p_ctrl) +{ + qspi_instance_ctrl_t * p_instance_ctrl = (qspi_instance_ctrl_t *) p_ctrl; + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->open = 0U; + + /* Disable clock to the QSPI block */ + R_BSP_MODULE_STOP(FSP_IP_QSPI, 0U); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup QSPI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enters or exits XIP (execute in place) mode. + * + * @param[in] p_instance_ctrl Pointer to a driver handle + * @param[in] code Code to place in M7-M0 + * @param[in] enter_mode True to enter, false to exit + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_xip (qspi_instance_ctrl_t * p_instance_ctrl, uint8_t code, bool enter_mode) +{ +#if QSPI_CFG_PARAM_CHECKING_ENABLE + + /* FSP_ASSERT(NULL != p_instance_ctrl) is optimized out when it shouldn't be. It appears to be affected by GCC bug + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90949. */ + qspi_instance_ctrl_t * volatile p_volatile_ctrl = p_instance_ctrl; + FSP_ASSERT(NULL != p_volatile_ctrl); + FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + volatile uint8_t i = 0; + + FSP_PARAMETER_NOT_USED(i); + + uint32_t dummy_clocks = 0; + if (SPI_FLASH_DUMMY_CLOCKS_DEFAULT != p_instance_ctrl->p_cfg->dummy_clocks) + { + /* Convert dummy cycles setting to the register value. */ + dummy_clocks = (uint32_t) p_instance_ctrl->p_cfg->dummy_clocks - 2U; + } + + R_QSPI->SFMSDC = (uint32_t) (code << R_QSPI_SFMSDC_SFMXD_Pos) | + (uint32_t) (enter_mode << R_QSPI_SFMSDC_SFMXEN_Pos) | + dummy_clocks; + + /* Read from QSPI to send the XIP entry request. */ + i = *(volatile uint8_t *) QSPI_DEVICE_START_ADDRESS; + + /* Wait for the controller to XIP mode status to update. To confirm completion of the XIP mode enter/exit procedure, + * read 1/0 from the SFMXST bit in the SFMSDC register. See "Selecting the XIP Mode" and + * "Releasing the XIP Mode" in the QSPI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(R_QSPI->SFMSDC_b.SFMXST, (uint32_t) enter_mode); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Gets device status. + * + * @param[in] p_instance_ctrl Pointer to a driver handle + * + * @return True if busy, false if not. + **********************************************************************************************************************/ +static bool r_qspi_status_sub (qspi_instance_ctrl_t * p_instance_ctrl) +{ + /* Enter direct communication mode */ + R_QSPI->SFMCMD = 1U; + + R_QSPI->SFMCOM = p_instance_ctrl->p_cfg->status_command; + bool status = (R_QSPI->SFMCOM >> p_instance_ctrl->p_cfg->write_status_bit) & 1; + + /* Close the SPI bus cycle. See "Generating the SPI Bus Cycle during Direct Communication" + * in the QSPI section of the relevant hardware manual. */ + R_QSPI->SFMCMD = 1U; + + /* Exit direct communication mode */ + R_QSPI->SFMCMD = 0U; + + return status; +} + +/*******************************************************************************************************************//** + * Writes raw data to QSPI. + * + * @param[in] p_src Pointer to data to write + * @param[in] bytes Number of bytes to write + * @param[in] read_after_write Whether or not to close SPI bus cycle + **********************************************************************************************************************/ +static void r_qspi_direct_write_sub (uint8_t const * const p_src, uint32_t const bytes, bool const read_after_write) +{ + /* Enter direct communication mode */ + R_QSPI->SFMCMD = 1U; + + /* Write data to QSPI. */ + for (uint32_t i = 0; i < bytes; i++) + { + R_QSPI->SFMCOM = p_src[i]; + } + + if (!read_after_write) + { + /* Close the SPI bus cycle. See "Generating the SPI Bus Cycle during Direct + * Communication" in the QSPI section of the relevant hardware manual. */ + R_QSPI->SFMCMD = 1U; + + /* Return to ROM access mode */ + R_QSPI->SFMCMD = 0U; + } +} + +/*******************************************************************************************************************//** + * Reads raw data from QSPI. + * + * @param[in] p_dest Pointer to store data + * @param[in] bytes Number of bytes to read + **********************************************************************************************************************/ +static void r_qspi_direct_read_sub (uint8_t * const p_dest, uint32_t const bytes) +{ + /* Read data from QSPI. */ + for (uint32_t i = 0; i < bytes; i++) + { + p_dest[i] = (uint8_t) R_QSPI->SFMCOM; + } + + /* Close the SPI bus cycle. See "Generating the SPI Bus Cycle during Direct + * Communication" in the QSPI section of the relevant hardware manual. */ + R_QSPI->SFMCMD = 1U; + + /* Return to ROM access mode */ + R_QSPI->SFMCMD = 0U; +} + +#if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM + +/*******************************************************************************************************************//** + * Writes a byte in extended SPI mode when the QSPI peripheral is configured for quad mode. + * + * @param[in] byte Byte to write + **********************************************************************************************************************/ +static void qspi_d0_byte_write_quad_mode (uint8_t byte) +{ + /* The LSB of each nibble ends up on D0. */ + uint32_t value = QSPI_PRV_LSB_NIBBLE_CLEARED; + for (uint32_t i = 0U; i < 8U; i++) + { + uint32_t bit = ((uint32_t) (byte >> i) & 1U); + + /* Place bits in every 4th bit (bit 0, 4, 8, ... 28). */ + uint32_t bit_mask = bit << (i * 4U); + + value |= bit_mask; + } + + R_QSPI->SFMCOM = (uint8_t) (value >> 24U); + R_QSPI->SFMCOM = (uint8_t) (value >> 16U); + R_QSPI->SFMCOM = (uint8_t) (value >> 8U); + R_QSPI->SFMCOM = (uint8_t) value; +} + +#endif + +#if QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM + +/*******************************************************************************************************************//** + * Writes a byte in extended SPI mode when the QSPI peripheral is configured for dual mode. + * + * @param[in] byte Byte to write + **********************************************************************************************************************/ +static void qspi_d0_byte_write_dual_mode (uint8_t byte) +{ + /* Every other bit ends up on D0. Unused bits are set. */ + uint16_t value = QSPI_PRV_EVEN_BITS_CLEARED; + for (uint32_t i = 0U; i < 8U; i++) + { + uint16_t bit = ((uint16_t) (byte >> i) & 1U); + + /* Place bits in every other bit (bit 0, 2, 4 ... 14). */ + uint16_t bit_mask = (uint16_t) (bit << (i * 2U)); + + value |= bit_mask; + } + + R_QSPI->SFMCOM = (uint8_t) (value >> 8U); + R_QSPI->SFMCOM = (uint8_t) value; +} + +#endif + +/*******************************************************************************************************************//** + * Writes a byte in the SPI mode configured in the QSPI peripheral. + * + * @param[in] byte Byte to write + **********************************************************************************************************************/ +static void qspi_d0_byte_write_standard (uint8_t byte) +{ + R_QSPI->SFMCOM = byte; +} + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking. + * + * @param[in] p_instance_ctrl Pointer to a driver handle + * + * @retval FSP_SUCCESS Device size stored in p_device_size_bytes + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled. + **********************************************************************************************************************/ +static fsp_err_t r_qspi_param_checking_dcom (qspi_instance_ctrl_t * p_instance_ctrl) +{ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Do not enter direct communication mode from XIP mode. See note in "Using Direct + * Communication Mode" in the QSPI section of the relevant hardware manual. */ + FSP_ERROR_RETURN(0U == R_QSPI->SFMSDC_b.SFMXST, FSP_ERR_INVALID_MODE); + + /* Verify device is not busy. */ + FSP_ERROR_RETURN(!r_qspi_status_sub(p_instance_ctrl), FSP_ERR_DEVICE_BUSY); + + return FSP_SUCCESS; +} + +#endif + +#if QSPI_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking for R_QSPI_Write. + * + * @param[in] p_instance_ctrl Pointer to a driver handle + * @param[in] p_src The source of the data to write to QSPI + * @param[in] p_dest The address in QSPI to write to + * @param[in] byte_count The number of bytes to write + * + * @retval FSP_SUCCESS Parameters are valid. + * @retval FSP_ERR_ASSERTION p_instance_ctrl,p_device_address or p_memory_address is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_MODE This function can't be called when XIP mode is enabled. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + **********************************************************************************************************************/ +static fsp_err_t qspi_program_param_check (qspi_instance_ctrl_t * p_instance_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count) +{ + fsp_err_t err = r_qspi_param_checking_dcom(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); + + /* Check if byte_count is valid */ + uint32_t page_size_bytes = p_instance_ctrl->p_cfg->page_size_bytes; + uint32_t bytes_left_in_page = page_size_bytes - ((uint32_t) p_dest % page_size_bytes); + FSP_ASSERT(byte_count <= bytes_left_in_page); + + return FSP_SUCCESS; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac/r_rmac.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac/r_rmac.c new file mode 100644 index 0000000000..89f9d5117a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac/r_rmac.c @@ -0,0 +1,2175 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rmac_cfg.h" +#include "r_rmac.h" +#include "r_layer3_switch.h" +#include "r_rmac_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define RMAC_OPEN (('R' << 24U) | ('M' << 16U) | ('A' << 8U) | ('C' << 0U)) + +#define RMAC_ETHA_REG_SIZE (R_ETHA1_BASE - R_ETHA0_BASE) +#define RMAC_RMAC_REG_SIZE (R_RMAC1_BASE - R_RMAC0_BASE) + +/* Register values */ +#define RMAC_REG_MRAFC_PROMISCUOUS_VALUE (R_RMAC0_MRAFC_UCENE_Msk | R_RMAC0_MRAFC_MCENE_Msk | \ + R_RMAC0_MRAFC_BCENE_Msk | R_RMAC0_MRAFC_BCACE_Msk | \ + R_RMAC0_MRAFC_NDAREE_Msk | R_RMAC0_MRAFC_SDSFREE_Msk | \ + R_RMAC0_MRAFC_NSAREE_Msk | R_RMAC0_MRAFC_UCENP_Msk | \ + R_RMAC0_MRAFC_MCENP_Msk | R_RMAC0_MRAFC_BCENP_Msk | \ + R_RMAC0_MRAFC_BCACP_Msk | R_RMAC0_MRAFC_NDAREP_Msk | \ + R_RMAC0_MRAFC_SDSFREP_Msk | R_RMAC0_MRAFC_NSAREP_Msk) + +/* For descriptor fields */ +#define RMAC_DESCRIPTOR_FIELD_DS_UPPER_MASK (0xF00) +#define RMAC_DESCRIPTOR_FIELD_DS_LOWER_MASK (0x00FF) +#define RMAC_DESCRIPTOR_FIELD_DS_UPPER_POSITION (0x8) +#define RMAC_DESCRIPTOR_FIELD_DV_MASK (0x7F) +#define RMAC_DESCRIPTOR_FIELD_PTR_UPPER_MASK (0xFF00000000) +#define RMAC_DESCRIPTOR_FIELD_PTR_LOWER_MASK (0xFFFFFFFF) +#define RMAC_DESCRIPTOR_FIELD_PTR_UPPER_POSITION (32) + +/* Definition of the maximum / minimum number of data that can be sent at one time in the Ethernet */ +#define RMAC_MAXIMUM_FRAME_SIZE (1514U) /* Maximum number of transmitted data */ +#define RMAC_MINIMUM_FRAME_SIZE (60U) /* Minimum number of transmitted data */ +#define RMAC_NO_DATA (0) + +/* Invalid value that mean all queue is not running or not available. */ +#define RMAC_INVALID_QUEUE_INDEX (0xFFFFFFFF) + +/* Increments a index and wraps around to 0 if it exceeds the maximum value */ +#define RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(x, max) (x = (x + 1) % max) + +/* TX Timestamp feature. */ +#define RMAC_WRITE_CFG_TX_TIMESTAMP_ENABLE (1) +#define RMAC_GET_TX_TIMESTAMP_WAIT_TIME (10000) + +/* Timestamp sequence number mask. */ +#define RMAC_TS_SEQUENCE_NUMBER_MASK (0x7F) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * ether_prv_ns_callback)(ether_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile ether_prv_ns_callback)(ether_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) +static fsp_err_t rmac_open_param_check(rmac_instance_ctrl_t const * const p_instance_ctrl, + ether_cfg_t const * const p_cfg); + +#endif + +static void rmac_init_descriptors(rmac_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t rmac_init_descriptor_queues(rmac_instance_ctrl_t * const p_instance_ctrl); +static void rmac_init_buffers(rmac_instance_ctrl_t * const p_instance_ctrl); + +static void rmac_configure_reception_filter(rmac_instance_ctrl_t const * const p_instance_ctrl); +static fsp_err_t rmac_do_link(rmac_instance_ctrl_t * const p_instance_ctrl, + const layer3_switch_magic_packet_detection_t mode); +static fsp_err_t rmac_link_status_check(rmac_instance_ctrl_t const * const p_instance_ctrl); + +static void rmac_call_callback(rmac_instance_ctrl_t * p_instance_ctrl, + ether_callback_args_t * p_callback_args); +static void r_rmac_switch_interrupt_callback(ether_switch_callback_args_t * p_args); +static fsp_err_t r_rmac_set_rx_buffer(rmac_instance_ctrl_t * p_instance_ctrl, + rmac_buffer_node_t * p_buffer_node); +static fsp_err_t r_rmac_set_tx_buffer(rmac_instance_ctrl_t * p_instance_ctrl, + void * p_write_buffer, + uint32_t frame_length, + uint32_t queue_index); +static fsp_err_t r_rmac_start_tx_queue(rmac_instance_ctrl_t * p_instance_ctrl, uint32_t queue_index); +static void r_rmac_disable_reception(rmac_instance_ctrl_t * p_instance_ctrl); +static rmac_buffer_node_t * r_rmac_buffer_dequeue(rmac_buffer_queue_t * p_queue); +static void r_rmac_buffer_enqueue(rmac_buffer_queue_t * p_queue, rmac_buffer_node_t * p_node); +static fsp_err_t r_rmac_get_rx_queue(rmac_instance_ctrl_t * p_instance_ctrl, uint32_t queue_index); +static fsp_err_t r_rmac_set_rx_queue(rmac_instance_ctrl_t * p_instance_ctrl, uint32_t queue_index); +static fsp_err_t r_rmac_get_tx_timestamp(rmac_instance_ctrl_t * p_instance_ctrl); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void rmac_rmpi_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* RMAC implementation of ether interface */ +const ether_api_t g_ether_on_rmac = +{ + .open = R_RMAC_Open, + .close = R_RMAC_Close, + .bufferRelease = R_RMAC_BufferRelease, + .rxBufferUpdate = R_RMAC_RxBufferUpdate, + .linkProcess = R_RMAC_LinkProcess, + .wakeOnLANEnable = R_RMAC_WakeOnLANEnable, + .read = R_RMAC_Read, + .write = R_RMAC_Write, + .txStatusGet = R_RMAC_TxStatusGet, + .callbackSet = R_RMAC_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup RMAC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the ether module and applies configurations. Implements @ref ether_api_t::open. + * + * @brief After RMAC, Switch and PHY-LSI are reset in software, an auto negotiation of PHY-LSI is begun. + * Afterwards, the link signal change interrupt is permitted. Implements @ref ether_api_t::open. + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block or configuration structure is NULL. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION Initialization of PHY-LSI failed. + * @retval FSP_ERR_INVALID_CHANNEL Invalid channel number is given. + * @retval FSP_ERR_INVALID_POINTER Pointer to extend config structure or MAC address is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Interrupt is not enabled. + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK Initialization of PHY-LSI failed. + **********************************************************************************************************************/ +fsp_err_t R_RMAC_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + rmac_extended_cfg_t * p_rmac_extended_cfg; + const ether_switch_instance_t * p_ether_switch; + +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + + /** Check parameters. */ + err = rmac_open_param_check(p_instance_ctrl, p_cfg); /** check arguments */ + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); +#endif + FSP_ERROR_RETURN((RMAC_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN); + + p_rmac_extended_cfg = (rmac_extended_cfg_t *) p_cfg->p_extend; + p_ether_switch = p_rmac_extended_cfg->p_ether_switch; + + /* Store register addresses. */ + p_instance_ctrl->p_reg_rmac = (R_RMAC0_Type *) (R_RMAC0_BASE + (RMAC_RMAC_REG_SIZE * p_cfg->channel)); + p_instance_ctrl->p_reg_etha = + (R_ETHA0_Type *) (R_ETHA0_BASE + (RMAC_ETHA_REG_SIZE * p_cfg->channel)); + + /* Initialize the flags */ + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_DOWN; + p_instance_ctrl->wake_on_lan = ETHER_WAKE_ON_LAN_DISABLE; + p_instance_ctrl->p_last_sent_buffer = NULL; + + /* Initialize configuration of Ethernet module. */ + p_instance_ctrl->p_cfg = p_cfg; + + /* Initialize configuration of timestamp. */ + p_instance_ctrl->p_rx_timestamp = NULL; + p_instance_ctrl->tx_timestamp.ns = 0; + p_instance_ctrl->tx_timestamp.sec_lower = 0; + p_instance_ctrl->tx_timestamp.sec_upper = 0; + p_instance_ctrl->tx_timestamp_seq_num = 0; + p_instance_ctrl->write_cfg.tx_timestamp_enable = 0; + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + /* Open ethernet switch module. */ + err = p_ether_switch->p_api->open(p_ether_switch->p_ctrl, p_ether_switch->p_cfg); + + /* Already open is acceptable because switch module is common for each RMAC port. */ + if ((FSP_SUCCESS == err) || (FSP_ERR_ALREADY_OPEN == err)) + { + /* Initialize the Ethernet buffer */ + rmac_init_buffers(p_instance_ctrl); + + /* Create descriptor queues. */ + err = rmac_init_descriptor_queues(p_instance_ctrl); + } + + if (FSP_SUCCESS == err) + { + p_instance_ctrl->open = RMAC_OPEN; + } + + return err; +} + +/********************************************************************************************************************//** + * @brief Disables interrupts. Removes power and releases hardware lock. Implements @ref ether_api_t::close. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_Close (ether_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + rmac_extended_cfg_t * p_extend; + layer3_switch_port_cfg_t port_cfg = {0}; + +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Reset port configuration to disable IRQ on the switch. */ + port_cfg.p_callback = NULL; + R_LAYER3_SWITCH_ConfigurePort(p_extend->p_ether_switch->p_ctrl, p_instance_ctrl->p_cfg->channel, &port_cfg); + + /* Disable IRQ. */ + p_instance_ctrl->p_reg_rmac->MMID2_b.MPDID = 1; + NVIC_DisableIRQ(p_extend->rmpi_irq); + R_FSP_IsrContextSet(p_extend->rmpi_irq, NULL); + + /* Initialize the flags */ + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_DOWN; + + /** Clear configure block parameters. */ + p_instance_ctrl->p_cfg = NULL; + + /** Mark the channel not open so other APIs cannot use it. */ + p_instance_ctrl->open = 0U; + + return err; +} /* End of function R_RMAC_Close() */ + +/********************************************************************************************************************//** + * @brief Move to the next buffer in the receive buffer list. Implements @ref ether_api_t::bufferRelease. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block or internal buffers is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation is not completed, and reception is not enabled. + * @retval FSP_ERR_BUFFER_EMPTY There is no available internal RX buffer. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_BufferRelease (ether_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + + rmac_buffer_node_t * p_read_buffer_node; /* Buffer location controlled by the Ethernet driver */ + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_instance_ctrl->p_cfg->pp_ether_buffers != NULL, FSP_ERR_ASSERTION) +#endif + + /* When the Link up processing is not completed, return error */ + FSP_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, + FSP_ERR_ETHER_ERROR_LINK); + + /* When the zerocopy mode, dequeue a unreleased buffer. */ + p_read_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->rx_unreleased_buffer_queue); + + if (NULL != p_read_buffer_node) + { + /* Try to set to the buffer */ + r_rmac_set_rx_buffer(p_instance_ctrl, p_read_buffer_node); + } + else + { + err = FSP_ERR_BUFFER_EMPTY; + } + + return err; +} /* End of function R_RMAC_BufferRelease() */ + +/********************************************************************************************************************//** + * @brief Change the buffer pointer of the current rx buffer descriptor. Implements @ref ether_api_t::rxBufferUpdate. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION A pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER The pointer of buffer is NULL or not aligned on a 32-bit boundary. + * @retval FSP_ERR_INVALID_MODE Driver is configured to non zero copy mode. + * @retval FSP_ERR_BUFFER_EMPTY There is no available internal RX buffer. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_RxBufferUpdate (ether_ctrl_t * const p_ctrl, void * const p_buffer) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + rmac_buffer_node_t * p_read_buffer_node; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(ETHER_ZEROCOPY_ENABLE == p_instance_ctrl->p_cfg->zerocopy, FSP_ERR_INVALID_MODE); +#endif + + if (p_instance_ctrl->rx_initialized_buffer_num < p_instance_ctrl->p_cfg->num_rx_descriptors) + { + p_instance_ctrl->rx_initialized_buffer_num++; + } + + /* Discard unreleased buffer and set the passed new buffer. */ + p_read_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->rx_unreleased_buffer_queue); + + /* When the unreleased buffer queue is empty, use the buffer node pool. */ + if (NULL == p_read_buffer_node) + { + p_read_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->buffer_node_pool); + } + + if (NULL != p_read_buffer_node) + { + p_read_buffer_node->p_buffer = p_buffer; + r_rmac_set_rx_buffer(p_instance_ctrl, p_read_buffer_node); + } + else + { + err = FSP_ERR_BUFFER_EMPTY; + } + + return err; +} + +/********************************************************************************************************************//** + * @brief The Link up processing, the Link down processing, and the magic packet detection processing are executed. + * Implements @ref ether_api_t::linkProcess. + * + * @retval FSP_SUCCESS Link is up. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_LINK Link is down. + * @retval FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION When reopening the PHY interface initialization of the PHY-LSI failed. + * @retval FSP_ERR_ALREADY_OPEN When reopening the PHY interface it was already opened. + * @retval FSP_ERR_INVALID_CHANNEL When reopening the PHY interface an invalid channel was passed. + * @retval FSP_ERR_INVALID_POINTER When reopening the PHY interface the MAC address pointer was NULL. + * @retval FSP_ERR_INVALID_ARGUMENT When reopening the PHY interface the interrupt was not enabled. + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK Initialization of the PHY-LSI failed. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_LinkProcess (ether_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + ether_callback_args_t callback_arg; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + err = rmac_link_status_check(p_instance_ctrl); + + /* The state of the link status in PHY-LSI is confirmed and Link Up/Down is judged. */ + if (FSP_SUCCESS == err) + { + /* When becoming Link up */ + if (ETHER_PREVIOUS_LINK_STATUS_DOWN == p_instance_ctrl->previous_link_status) + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_UP; + + /* Update Link status */ + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_UP; + } + } + else + { + /* When becoming Link down */ + if (ETHER_PREVIOUS_LINK_STATUS_UP == p_instance_ctrl->previous_link_status) + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_DOWN; + + /* Update Link status */ + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_DOWN; + } + } + + /* When the link is up */ + if (ETHER_LINK_CHANGE_LINK_UP == p_instance_ctrl->link_change) + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_UP; + + /* Initialize the Ethernet buffer */ + rmac_init_buffers(p_instance_ctrl); + + /* Initialize receive and transmit descriptors */ + rmac_init_descriptors(p_instance_ctrl); + + /* Configure reception filters. */ + rmac_configure_reception_filter(p_instance_ctrl); + + err = rmac_do_link(p_instance_ctrl, LAYER3_SWITCH_MAGIC_PACKET_DETECTION_DISABLE); + + if (FSP_SUCCESS == err) + { + /* If a callback is provided, then call it with callback argument. */ + if (NULL != p_instance_ctrl->p_callback) + { + callback_arg.channel = p_instance_ctrl->p_cfg->channel; + callback_arg.event = ETHER_EVENT_LINK_ON; + callback_arg.p_context = p_instance_ctrl->p_cfg->p_context; + rmac_call_callback(p_instance_ctrl, &callback_arg); + } + } + else + { + /* When PHY auto-negotiation is not completed */ + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_LINK_UP; + } + } + /* When the link is down */ + else if (ETHER_LINK_CHANGE_LINK_DOWN == p_instance_ctrl->link_change) + { + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + + /* Disable reception. */ + r_rmac_disable_reception(p_instance_ctrl); + + /* If a callback is provided, then call it with callback argument. */ + if (NULL != p_instance_ctrl->p_callback) + { + callback_arg.channel = p_instance_ctrl->p_cfg->channel; + callback_arg.event = ETHER_EVENT_LINK_OFF; + callback_arg.p_context = p_instance_ctrl->p_cfg->p_context; + rmac_call_callback(p_instance_ctrl, &callback_arg); + } + } + else + { + /* no operation */ + } + + return err; +} /* End of function R_RMAC_LinkProcess() */ + +/********************************************************************************************************************//** + * @brief The setting of RMAC is changed from normal sending and receiving mode to magic packet detection mode. + * Implements @ref ether_api_t::wakeOnLANEnable. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation is not completed, and reception is not enabled. + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK Initialization of PHY-LSI failed. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_WakeOnLANEnable (ether_ctrl_t * const p_ctrl) +{ + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* When the Link up processing is not completed, return error */ + FSP_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, + FSP_ERR_ETHER_ERROR_LINK); + + /* When the Link up processing is completed */ + /* Change to the magic packet detection mode. */ + rmac_do_link(p_instance_ctrl, LAYER3_SWITCH_MAGIC_PACKET_DETECTION_ENABLE); + + /* It is confirmed not to become Link down while changing the setting. */ + err = rmac_link_status_check(p_instance_ctrl); + + if (FSP_SUCCESS == err) + { + p_instance_ctrl->wake_on_lan = ETHER_WAKE_ON_LAN_ENABLE; + } + else + { + err = FSP_ERR_ETHER_ERROR_LINK; + } + + return err; +} /* End of function R_RMAC_WakeOnLANEnable() */ + +/********************************************************************************************************************//** + * @brief Receive Ethernet frame. Receives data to the location specified by the pointer to the receive buffer. + * In zero copy mode, the address of the receive buffer is returned. + * In non zero copy mode, the received data in the internal buffer is copied to the pointer passed by the argument. + * Implements @ref ether_api_t::read. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_NO_DATA There is no data in receive buffer. + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation is not completed, and reception is not enabled. + * @retval FSP_ERR_ETHER_ERROR_FILTERING Multicast Frame filter is enable, and Multicast Address Frame is + * received. + * @retval FSP_ERR_INVALID_POINTER Value of the pointer is NULL. + * @retval FSP_ERR_BUFFER_EMPTY There is no available internal RX buffer. + * @retval FSP_ERR_INVALID_SIZE The buffer size is smaller than @ref ether_cfg_t::ether_buffer_size. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_Read (ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t * const length_bytes) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + rmac_buffer_node_t * p_read_buffer_node = NULL; /* Buffer location controlled by the Ethernet driver */ + uint32_t received_size = RMAC_NO_DATA; + uint8_t * p_read_buffer = NULL; + uint8_t ** pp_read_buffer = (uint8_t **) p_buffer; + rmac_extended_cfg_t * p_extend; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(NULL != length_bytes, FSP_ERR_INVALID_POINTER); + #if (RMAC_CFG_READ_BUFFER_SIZE_CHECK) + FSP_ERROR_RETURN(p_instance_ctrl->p_cfg->ether_buffer_size <= *length_bytes, FSP_ERR_INVALID_SIZE); + #endif +#endif + + /* (1) Retrieve the receive buffer location controlled by the descriptor. */ + /* When the Link up processing is not completed, return error */ + FSP_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, + FSP_ERR_ETHER_ERROR_LINK); + + p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + p_read_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->rx_completed_buffer_queue); + if (NULL != p_read_buffer_node) + { + p_read_buffer = p_read_buffer_node->p_buffer; + received_size = p_read_buffer_node->size; + } + + /* When there is data to receive */ + if (received_size > RMAC_NO_DATA) + { +#if LAYER3_SWITCH_CFG_GPTP_ENABLE + + /* Get timestamp. */ + if (NULL != p_instance_ctrl->p_rx_timestamp) + { + p_instance_ctrl->p_rx_timestamp->ns = p_read_buffer_node->timestamp.ns; + p_instance_ctrl->p_rx_timestamp->sec_lower = p_read_buffer_node->timestamp.sec_lower; + + /* Clear for next read. */ + p_instance_ctrl->p_rx_timestamp = NULL; + } +#endif + + if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_cfg->zerocopy) + { + /* (2) Copy the data read from the receive buffer which is controlled + * by the descriptor to the buffer which is specified by the user (up to 1024 bytes). */ + memcpy(p_buffer, p_read_buffer, received_size); + + /* (3) Read the receive data from the receive buffer controlled by the descriptor, + * and then release the receive buffer. */ + + /* Read a pending buffer, try to set this buffer to the descriptor queue. If failed, it will be enqueued to the buffer pool. */ + r_rmac_set_rx_buffer(p_instance_ctrl, p_read_buffer_node); + } + else + { + *pp_read_buffer = p_read_buffer; + + /* Add this buffer to the buffer pool. It becomes reusable after being released via the BufferRelease API. */ + r_rmac_buffer_enqueue(&p_instance_ctrl->rx_unreleased_buffer_queue, p_read_buffer_node); + } + + *length_bytes = received_size; + } + /* When there is no data to receive */ + else + { + err = FSP_ERR_ETHER_ERROR_NO_DATA; + + if (RMAC_INVALID_QUEUE_INDEX == p_instance_ctrl->rx_running_queue_index) + { + /*Try to set a new empty buffer and restart reception. */ + fsp_err_t serr = R_LAYER3_SWITCH_StartDescriptorQueue(p_extend->p_ether_switch->p_ctrl, + p_extend->p_rx_queue_list[p_instance_ctrl-> + read_queue_index].index); + if (FSP_SUCCESS == serr) + { + p_instance_ctrl->rx_running_queue_index = p_instance_ctrl->read_queue_index; + } + + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(p_instance_ctrl->read_queue_index, p_extend->rx_queue_num); + } + } + + FSP_CRITICAL_SECTION_EXIT; + + return err; +} /* End of function R_RMAC_Read() */ + +/********************************************************************************************************************//** + * @brief Transmit Ethernet frame. Transmits data from the location specified by the pointer to the transmit + * buffer, with the data size equal to the specified frame length. + * In the non zero copy mode, transmits data after being copied to the internal buffer. + * Implements @ref ether_api_t::write. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation is not completed, and reception is not enabled. + * @retval FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL Transmit buffer is not empty. + * @retval FSP_ERR_INVALID_POINTER Value of the pointer is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Value of the send frame size is out of range. + * @retval FSP_ERR_BUFFER_EMPTY There is no available internal TX buffer. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_Write (ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + rmac_extended_cfg_t * p_extend; + + void * p_write_buffer; + rmac_buffer_node_t * p_write_buffer_node = NULL; + uint32_t next_write_queue; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_buffer, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN((RMAC_MINIMUM_FRAME_SIZE <= frame_length) && (RMAC_MAXIMUM_FRAME_SIZE >= frame_length), + FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_instance_ctrl->p_cfg->ether_buffer_size >= frame_length, FSP_ERR_OVERFLOW); +#endif + + p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + next_write_queue = p_instance_ctrl->write_queue_index; + + /* When the Link up processing is not completed, return error */ + FSP_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, + FSP_ERR_ETHER_ERROR_LINK); + + /* Get TX buffer. */ + if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_cfg->zerocopy) + { + p_write_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->tx_empty_buffer_queue); + FSP_ERROR_RETURN(NULL != p_write_buffer_node, FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL); + p_write_buffer_node->size = frame_length; + + /* Get a buffer from internal buffers. */ + p_write_buffer = p_write_buffer_node->p_buffer; + + /* Copy data to the transmit buffer. */ + memcpy(p_write_buffer, p_buffer, frame_length); + } + else + { + /* In zerocopy mode, use a passed buffer. */ + p_write_buffer = p_buffer; + } + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* If a pending buffer exists, this buffer will be also pending. */ + if (NULL != p_instance_ctrl->tx_pending_buffer_queue.p_head) + { + err = FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL; + } + else + { + /* If the write target is the running queue, don't write to the descriptor queue. */ + if (RMAC_INVALID_QUEUE_INDEX != p_instance_ctrl->tx_running_queue_index) + { + next_write_queue = p_instance_ctrl->tx_running_queue_index; + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(next_write_queue, p_extend->tx_queue_num); + } + else + { + next_write_queue = p_instance_ctrl->write_queue_index; + } + + err = + r_rmac_set_tx_buffer(p_instance_ctrl, p_write_buffer, frame_length, + p_extend->p_tx_queue_list[next_write_queue].index); + + /* Try to write to the next queue. */ + if (FSP_ERR_OVERFLOW == err) + { + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(next_write_queue, p_extend->tx_queue_num); + if (p_instance_ctrl->tx_running_queue_index != next_write_queue) + { + err = + r_rmac_set_tx_buffer(p_instance_ctrl, p_write_buffer, frame_length, + p_extend->p_tx_queue_list[next_write_queue].index); + } + } + } + + FSP_CRITICAL_SECTION_EXIT; + + if (FSP_SUCCESS == err) + { + /* If non-zerocoy mode, move the internal buffer node to the pool. */ + if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_cfg->zerocopy) + { + r_rmac_buffer_enqueue(&p_instance_ctrl->buffer_node_pool, p_write_buffer_node); + } + } + else + { + /* Copy the zerocopy buffer to a new buffer node. */ + if (NULL == p_write_buffer_node) + { + p_write_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->buffer_node_pool); + FSP_ERROR_RETURN(NULL != p_write_buffer_node, FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL); + p_write_buffer_node->p_buffer = p_write_buffer; + p_write_buffer_node->size = frame_length; + } + + /* If write process fails, add the buffer to the pending queue. */ + r_rmac_buffer_enqueue(&p_instance_ctrl->tx_pending_buffer_queue, p_write_buffer_node); + err = FSP_SUCCESS; + } + + /* Check if all TX queues are stopped. */ + if (p_instance_ctrl->tx_running_queue_index == RMAC_INVALID_QUEUE_INDEX) + { + FSP_CRITICAL_SECTION_ENTER; + + /* When all TX queues are stopped, start transmission */ + if (FSP_SUCCESS == + r_rmac_start_tx_queue(p_instance_ctrl, p_extend->p_tx_queue_list[next_write_queue].index)) + { + p_instance_ctrl->tx_running_queue_index = next_write_queue; + } + else + { + p_instance_ctrl->tx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + } + + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(next_write_queue, p_extend->tx_queue_num); + + FSP_CRITICAL_SECTION_EXIT; + } + + p_instance_ctrl->write_queue_index = next_write_queue; + + return err; +} /* End of function R_RMAC_Write() */ + +/**********************************************************************************************************************//** + * Provides status of Ethernet driver in the user provided pointer. Implements @ref ether_api_t::txStatusGet. + * + * @retval FSP_SUCCESS Transmit buffer address is stored in provided p_buffer_address. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_POINTER p_status is NULL. + * @retval FSP_ERR_NOT_FOUND Transmit buffer address has been overwritten in transmit descriptor. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_TxStatusGet (ether_ctrl_t * const p_ctrl, void * const p_buffer_address) +{ + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + uint8_t ** p_sent_buffer_address = (uint8_t **) p_buffer_address; + fsp_err_t err; + +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(NULL != p_buffer_address, FSP_ERR_INVALID_POINTER); +#endif + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + if (NULL != p_instance_ctrl->p_last_sent_buffer) + { + *p_sent_buffer_address = p_instance_ctrl->p_last_sent_buffer; + p_instance_ctrl->p_last_sent_buffer = NULL; + err = FSP_SUCCESS; + } + else + { + /* No descriptors have been sent. */ + err = FSP_ERR_NOT_FOUND; + } + + FSP_CRITICAL_SECTION_EXIT; + + return err; +} /* End of function R_RMAC_VersionGet() */ + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref ether_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_RMAC_CallbackSet (ether_ctrl_t * const p_api_ctrl, + void ( * p_callback)(ether_callback_args_t *), + void * const p_context, + ether_callback_args_t * const p_callback_memory) +{ + rmac_instance_ctrl_t * p_ctrl = (rmac_instance_ctrl_t *) p_api_ctrl; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(RMAC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if RMAC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + ether_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(ether_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/********************************************************************************************************************//** + * @brief Set configuration for tx frame. This API must call before @ref ether_api_t::write. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION A pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_SetWriteConfig (ether_ctrl_t * const p_ctrl, rmac_write_cfg_t * const p_write_cfg) +{ + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(NULL != p_write_cfg, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->write_cfg.tx_timestamp_enable = p_write_cfg->tx_timestamp_enable; + + return FSP_SUCCESS; +} + +/********************************************************************************************************************//** + * @brief Get timestamp of transmitted frame. This API must call after @ref ether_api_t::write. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION A pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_GetTxTimestamp (ether_ctrl_t * const p_ctrl, rmac_timestamp_t * const p_timestamp) +{ + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(NULL != p_timestamp, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_timestamp->ns = p_instance_ctrl->tx_timestamp.ns; + p_timestamp->sec_lower = p_instance_ctrl->tx_timestamp.sec_lower; + + /* Clear timestamp */ + p_instance_ctrl->tx_timestamp.ns = 0; + p_instance_ctrl->tx_timestamp.sec_lower = 0; + + return FSP_SUCCESS; +} + +/********************************************************************************************************************//** + * @brief Get timestamp of received frame. This API must call before @ref ether_api_t::read. + * + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION A pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_GetRxTimestamp (ether_ctrl_t * const p_ctrl, rmac_timestamp_t * const p_timestamp) +{ + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_ctrl; + + /* Check argument */ +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(NULL != p_timestamp, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->p_rx_timestamp = p_timestamp; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RMAC) + **********************************************************************************************************************/ + +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * @brief Parameter error check function for open. + * + * @param[in] p_instance_ctrl Pointer to the control block for the channel + * @param[in] p_cfg Pointer to the configuration structure specific to UART mode + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_ASSERTION Pointer to RMAC control block or configuration structure is NULL + * @retval FSP_ERR_INVALID_CHANNEL Invalid channel number is given. + * @retval FSP_ERR_INVALID_POINTER Pointer to MAC address is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Irq number lower then 0. + **********************************************************************************************************************/ +static fsp_err_t rmac_open_param_check (rmac_instance_ctrl_t const * const p_instance_ctrl, + ether_cfg_t const * const p_cfg) +{ + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(NULL != p_cfg, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(NULL != p_cfg->p_mac_address, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(NULL != p_cfg->p_extend, FSP_ERR_INVALID_POINTER); + FSP_ERROR_RETURN(BSP_FEATURE_ETHER_NUM_CHANNELS > p_cfg->channel, FSP_ERR_INVALID_CHANNEL); + + if (p_cfg->zerocopy == ETHER_ZEROCOPY_DISABLE) + { + FSP_ERROR_RETURN((p_cfg->pp_ether_buffers != NULL), FSP_ERR_INVALID_ARGUMENT); + } + + /* RMAC does not support padding feature. */ + FSP_ERROR_RETURN(p_cfg->padding == ETHER_PADDING_DISABLE, FSP_ERR_UNSUPPORTED); + + return FSP_SUCCESS; +} + +#endif + +/*********************************************************************************************************************** + * Function Name: rmac_configure_reception_filter + * Description : Configure the ETHA and RMAC feature. + * Arguments : channel - + * RMAC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void rmac_configure_reception_filter (rmac_instance_ctrl_t const * const p_instance_ctrl) +{ + uint32_t mrafc = p_instance_ctrl->p_reg_rmac->MRAFC; + + if (ETHER_PROMISCUOUS_ENABLE == p_instance_ctrl->p_cfg->promiscuous) + { + /* Enable promiscuous reception. */ + mrafc = RMAC_REG_MRAFC_PROMISCUOUS_VALUE; + } + else + { + /* Configure multicast reception features. */ + if (ETHER_MULTICAST_ENABLE == p_instance_ctrl->p_cfg->multicast) + { + /* Enable multicast reception. */ + mrafc |= R_RMAC0_MRAFC_MCENE_Msk | R_RMAC0_MRAFC_MCENP_Msk; + } + else + { + mrafc &= ~(R_RMAC0_MRAFC_MCENE_Msk | R_RMAC0_MRAFC_MCENP_Msk); + } + + /* Enable broadcast reception. */ + mrafc |= R_RMAC0_MRAFC_BCENE_Msk | R_RMAC0_MRAFC_BCENP_Msk; + } + + /* Set the broadcast storm filter regardless of the promiscuous mode configuration. */ + if (0 < p_instance_ctrl->p_cfg->broadcast_filter) + { + /* Enable the broadcast storm filter */ + mrafc |= R_RMAC0_MRAFC_BCACE_Msk | R_RMAC0_MRAFC_BSTENE_Msk | + R_RMAC0_MRAFC_BSTENP_Msk | R_RMAC0_MRAFC_BCACP_Msk; + + /* Configure how many broadcast frames can be received consecutively. */ + p_instance_ctrl->p_reg_rmac->MRSCE_b.CBFE = (R_RMAC0_MRSCE_CBFE_Msk >> R_RMAC0_MRSCE_CBFE_Pos) & + (p_instance_ctrl->p_cfg->broadcast_filter - 1); + } + else + { + mrafc &= ~(R_RMAC0_MRAFC_BSTENE_Msk | R_RMAC0_MRAFC_BSTENP_Msk); + } + + p_instance_ctrl->p_reg_rmac->MRAFC = mrafc; +} /* End of function rmac_configure_reception_filter() */ + +/********************************************************************************************************************//** + * @brief Determines the partner PHY capability through auto-negotiation process. The link abilities + * are handled to determine duplex, speed and flow control (PAUSE frames). + * + * @param[in] p_instance_ctrl Pointer to the control block for the channel + * @param[in] mode The operational mode is specified. + * NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually + * USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode + * @retval FSP_SUCCESS Processing completed successfully. + * @retval FSP_ERR_ASSERTION Pointer to ETHER control block or configuration structure is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ETHER_ERROR_LINK Auto-negotiation of PHY-LSI is not completed + * or result of Auto-negotiation is abnormal. + * + ***********************************************************************************************************************/ +static fsp_err_t rmac_do_link (rmac_instance_ctrl_t * const p_instance_ctrl, + const layer3_switch_magic_packet_detection_t mode) +{ + fsp_err_t err = FSP_SUCCESS; + + rmac_extended_cfg_t * p_rmac_extended_cfg; + layer3_switch_extended_cfg_t * p_switch_extended_cfg; + const ether_phy_instance_t * p_phy_instance; + + layer3_switch_port_cfg_t port_cfg = {0}; + uint32_t link_speed_duplex = 0; + uint32_t local_pause_bits = 0; + uint32_t partner_pause_bits = 0; + fsp_err_t link_result; + +#if (RMAC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RMAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_rmac_extended_cfg = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + p_switch_extended_cfg = (layer3_switch_extended_cfg_t *) p_rmac_extended_cfg->p_ether_switch->p_cfg->p_extend; + p_phy_instance = + (ether_phy_instance_t *) p_switch_extended_cfg->p_ether_phy_instances[p_instance_ctrl->p_cfg->channel]; + + /* Set the link status */ + R_RMAC_PHY_ChipSelect(p_phy_instance->p_ctrl, p_instance_ctrl->p_cfg->channel); + link_result = p_phy_instance->p_api->linkPartnerAbilityGet(p_phy_instance->p_ctrl, + &link_speed_duplex, + &local_pause_bits, + &partner_pause_bits); + + if (FSP_SUCCESS == link_result) + { + /* Set MAC address. */ + port_cfg.p_mac_address = p_instance_ctrl->p_cfg->p_mac_address; + + if (LAYER3_SWITCH_MAGIC_PACKET_DETECTION_DISABLE == mode) + { + /* + * To prevent reception from starting at an invalid descriptor, the queue must be reloaded first. + * Until then, reception is kept disabled. + */ + port_cfg.forwarding_to_cpu_enable = false; + R_LAYER3_SWITCH_ConfigurePort(p_rmac_extended_cfg->p_ether_switch->p_ctrl, + p_instance_ctrl->p_cfg->channel, + &port_cfg); + + /* Reload RX queue. */ + if (NULL != p_instance_ctrl->p_cfg->pp_ether_buffers) + { + p_instance_ctrl->rx_running_queue_index = 0; + err = R_LAYER3_SWITCH_StartDescriptorQueue(p_rmac_extended_cfg->p_ether_switch->p_ctrl, + p_rmac_extended_cfg->p_rx_queue_list[0].index); + } + + /* Set callback for switch data interrupt. */ + port_cfg.p_callback = r_rmac_switch_interrupt_callback; + port_cfg.p_context = p_instance_ctrl; + port_cfg.p_callback_memory = NULL; + + /* Enable reception. */ + port_cfg.forwarding_to_cpu_enable = true; + R_LAYER3_SWITCH_ConfigurePort(p_rmac_extended_cfg->p_ether_switch->p_ctrl, + p_instance_ctrl->p_cfg->channel, + &port_cfg); + } + else + { + /* Disable reception. */ + r_rmac_disable_reception(p_instance_ctrl); + + /* Enable a magic packet interrupt. */ + R_BSP_IrqCfgEnable(p_rmac_extended_cfg->rmpi_irq, p_rmac_extended_cfg->rmpi_ipl, p_instance_ctrl); + p_instance_ctrl->p_reg_rmac->MMIE2_b.MPDIE = 1; + } + } + else + { + err = FSP_ERR_ETHER_ERROR_LINK; + } + + return err; +} /* End of function rmac_do_link() */ + +/*******************************************************************************************************************//** + * @brief Verifies the Ethernet link is up or not. + * + * @param[in] p_instance_ctrl Pointer to the control block for the channel + * + * @retval FSP_SUCCESS: Link is up + * @retval FSP_ERR_ETHER_ERROR_LINK: Link is down + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK Initialization of PHY-LSI failed. + **********************************************************************************************************************/ +static fsp_err_t rmac_link_status_check (rmac_instance_ctrl_t const * const p_instance_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + fsp_err_t link_status; + + rmac_extended_cfg_t * p_rmac_extended_cfg; + layer3_switch_extended_cfg_t * p_switch_extended_cfg; + const ether_phy_instance_t * p_phy_instance; + uint32_t line_speed_duplex; + uint32_t local_pause; + uint32_t partner_pause; + + p_rmac_extended_cfg = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + p_switch_extended_cfg = (layer3_switch_extended_cfg_t *) p_rmac_extended_cfg->p_ether_switch->p_cfg->p_extend; + p_phy_instance = + (ether_phy_instance_t *) p_switch_extended_cfg->p_ether_phy_instances[p_instance_ctrl->p_cfg->channel]; + + /* Update PHY LSI information */ + R_RMAC_PHY_ChipSelect(p_phy_instance->p_ctrl, p_instance_ctrl->p_cfg->channel); + + /* Get link status */ + link_status = p_phy_instance->p_api->linkStatusGet(p_phy_instance->p_ctrl); + + if (FSP_ERR_ETHER_PHY_ERROR_LINK == link_status) + { + /* Link is down */ + err = FSP_ERR_ETHER_ERROR_LINK; + } + else + { + /* Link is up */ + err = FSP_SUCCESS; + + /* Call LinkPartnerAbilityGet to configure link speed. */ + p_phy_instance->p_api->linkPartnerAbilityGet(p_phy_instance->p_ctrl, + &line_speed_duplex, + &local_pause, + &partner_pause); + } + + return err; +} /* End of function rmac_link_status_check() */ + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_instance_ctrl Pointer to ether instance control block + * @param[in] p_callback_args Pointer to callback args + **********************************************************************************************************************/ +static void rmac_call_callback (rmac_instance_ctrl_t * p_instance_ctrl, ether_callback_args_t * p_callback_args) +{ + ether_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + ether_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = p_callback_args->event; + p_args->channel = p_instance_ctrl->p_cfg->channel; + p_args->p_context = p_instance_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + ether_prv_ns_callback p_callback = (ether_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } +} + +/*********************************************************************************************************************** + * Function Name: rmac_init_descriptors + * Description : Initialize descriptors and set buffers to these. + * Arguments : channel - + * RMAC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void rmac_init_descriptors (rmac_instance_ctrl_t * const p_instance_ctrl) +{ + layer3_switch_descriptor_t descriptor = {0}; + + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + uint32_t buffers_index = 0; + uint32_t nodes_index = 0; + rmac_buffer_node_t * p_buffer_node; + + /* Initialize common buffer pool. */ + p_instance_ctrl->buffer_node_pool.p_head = NULL; + p_instance_ctrl->buffer_node_pool.p_tail = NULL; + p_instance_ctrl->tx_empty_buffer_queue.p_head = NULL; + p_instance_ctrl->tx_empty_buffer_queue.p_tail = NULL; + p_instance_ctrl->rx_empty_buffer_queue.p_head = NULL; + p_instance_ctrl->rx_empty_buffer_queue.p_tail = NULL; + + /* Enable Data interrupt for RX descriptor. */ + descriptor.basic.die = 1; + + /* Initialize variables that used for RX. */ + p_instance_ctrl->read_queue_index = 0; + p_instance_ctrl->rx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + p_instance_ctrl->rx_completed_buffer_queue.p_head = NULL; + p_instance_ctrl->rx_completed_buffer_queue.p_tail = NULL; + p_instance_ctrl->rx_unreleased_buffer_queue.p_head = NULL; + p_instance_ctrl->rx_unreleased_buffer_queue.p_tail = NULL; + + if (NULL != p_instance_ctrl->p_cfg->pp_ether_buffers) + { + p_instance_ctrl->rx_initialized_buffer_num = p_instance_ctrl->p_cfg->num_rx_descriptors; + + /* Settings for RX descriptors */ + descriptor.basic.ds_h = (RMAC_DESCRIPTOR_FIELD_DS_UPPER_MASK & RMAC_MAXIMUM_FRAME_SIZE) >> + RMAC_DESCRIPTOR_FIELD_DS_UPPER_POSITION; + descriptor.basic.ds_l = RMAC_DESCRIPTOR_FIELD_DS_LOWER_MASK & RMAC_MAXIMUM_FRAME_SIZE; + descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY; + } + else + { + p_instance_ctrl->rx_initialized_buffer_num = 0; + } + + /* Initialize descriptors of each RX queue if buffers are allocated by configuration. */ + for (uint32_t i = 0; i < p_extend->rx_queue_num; i++) + { + /* For each RX descriptor exclude the last. */ + for (uint32_t j = 0; j < p_extend->p_rx_queue_list[0].queue_cfg.array_length - 1; j++) + { + /* Get a node without buffer. */ + p_buffer_node = &p_extend->p_buffer_node_list[nodes_index]; + p_buffer_node->p_buffer = NULL; + nodes_index++; + + if (NULL != p_instance_ctrl->p_cfg->pp_ether_buffers) + { + descriptor.basic.ptr_h = + (RMAC_DESCRIPTOR_FIELD_PTR_UPPER_MASK & + (uint64_t) (uintptr_t) p_instance_ctrl->p_cfg->pp_ether_buffers[buffers_index]) >> + RMAC_DESCRIPTOR_FIELD_PTR_UPPER_POSITION; + descriptor.basic.ptr_l = RMAC_DESCRIPTOR_FIELD_PTR_LOWER_MASK & + (uintptr_t) p_instance_ctrl->p_cfg->pp_ether_buffers[buffers_index]; + + /* Set data to descriptor. */ + R_LAYER3_SWITCH_SetDescriptor(p_extend->p_ether_switch->p_ctrl, + p_extend->p_rx_queue_list[i].index, + &descriptor); + + /* Add to RX buffer pool without a buffer. */ + r_rmac_buffer_enqueue(&p_instance_ctrl->buffer_node_pool, p_buffer_node); + buffers_index++; + } + else + { + /* Add to unreleased buffer queue without a buffer. */ + r_rmac_buffer_enqueue(&p_instance_ctrl->rx_unreleased_buffer_queue, p_buffer_node); + } + } + } + + /* Save the remaining reception buffers as reserves. */ + if (NULL != p_instance_ctrl->p_cfg->pp_ether_buffers) + { + while (nodes_index < p_instance_ctrl->p_cfg->num_rx_descriptors) + { + p_buffer_node = &p_extend->p_buffer_node_list[nodes_index]; + p_buffer_node->p_buffer = p_instance_ctrl->p_cfg->pp_ether_buffers[buffers_index]; + r_rmac_buffer_enqueue(&p_instance_ctrl->rx_empty_buffer_queue, p_buffer_node); + nodes_index++; + buffers_index++; + } + } + + /* Settings for TX descriptors.*/ + /* Initialize variables that used for TX. */ + p_instance_ctrl->write_queue_index = 0; + p_instance_ctrl->tx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + + p_instance_ctrl->tx_pending_buffer_queue.p_head = NULL; + p_instance_ctrl->tx_pending_buffer_queue.p_tail = NULL; + + /* Set descriptor type as terminate descriptor. TX descriptors will be set actual buffer in Write() API. */ + descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY; + descriptor.basic.ptr_h = 0; + descriptor.basic.ptr_l = (uintptr_t) NULL; + descriptor.basic.ds_h = 0; + descriptor.basic.ds_l = 0; + descriptor.basic.die = 0; + descriptor.basic.ds_l = 0; + + /* Initialize descriptors of each TX queue */ + for (uint32_t i = 0; i < p_extend->tx_queue_num; i++) + { + /* For each TX descriptor exclude the last. */ + for (uint32_t j = 0; j < p_extend->p_tx_queue_list[0].queue_cfg.array_length - 1; j++) + { + /* Set data to descriptor. */ + R_LAYER3_SWITCH_SetDescriptor(p_extend->p_ether_switch->p_ctrl, + p_extend->p_tx_queue_list[i].index, + &descriptor); + } + + /* Performing a null transmission to initialize the TX queue. */ + R_LAYER3_SWITCH_StartDescriptorQueue(p_extend->p_ether_switch->p_ctrl, p_extend->p_tx_queue_list[i].index); + } + + /* Save the remaining transmit buffers as reserves. */ + while (nodes_index < p_extend->buffer_node_num) + { + p_buffer_node = &p_extend->p_buffer_node_list[nodes_index]; + nodes_index++; + if ((ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_cfg->zerocopy) && + (buffers_index < (p_instance_ctrl->p_cfg->num_tx_descriptors + p_instance_ctrl->p_cfg->num_rx_descriptors))) + { + p_buffer_node->p_buffer = p_instance_ctrl->p_cfg->pp_ether_buffers[buffers_index]; + r_rmac_buffer_enqueue(&p_instance_ctrl->tx_empty_buffer_queue, p_buffer_node); + buffers_index++; + } + else + { + r_rmac_buffer_enqueue(&p_instance_ctrl->buffer_node_pool, p_buffer_node); + } + } +} /* End of function ether_init_descriptors() */ + +/*********************************************************************************************************************** + * Function Name: rmac_init_buffers + * Description : The driver buffers are initialized. + * Arguments : p_instance_ctrl - + * RMAC control block. + * Return Value : none + ***********************************************************************************************************************/ +static void rmac_init_buffers (rmac_instance_ctrl_t * const p_instance_ctrl) +{ + uint32_t i; + uint32_t buffer_num; + + if (NULL != p_instance_ctrl->p_cfg->pp_ether_buffers) + { + if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_cfg->zerocopy) + { + buffer_num = + (uint32_t) (p_instance_ctrl->p_cfg->num_tx_descriptors + + p_instance_ctrl->p_cfg->num_rx_descriptors); + } + else + { + buffer_num = (uint32_t) p_instance_ctrl->p_cfg->num_rx_descriptors; + } + + for (i = 0; i < buffer_num; i++) + { + memset(p_instance_ctrl->p_cfg->pp_ether_buffers[i], 0x00, p_instance_ctrl->p_cfg->ether_buffer_size); + } + } +} /* End of function rmac_init_buffers() */ + +static fsp_err_t rmac_init_descriptor_queues (rmac_instance_ctrl_t * const p_instance_ctrl) +{ + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + fsp_err_t err = FSP_SUCCESS; + + /* Initialize TX queues. */ + for (uint32_t i = 0; i < p_extend->tx_queue_num; i++) + { + err = R_LAYER3_SWITCH_CreateDescriptorQueue(p_extend->p_ether_switch->p_ctrl, + &p_extend->p_tx_queue_list[i].index, + &p_extend->p_tx_queue_list[i].queue_cfg); + if (FSP_SUCCESS != err) + { + break; + } + } + +#if LAYER3_SWITCH_CFG_GPTP_ENABLE + if (FSP_SUCCESS == err) + { + /* Initialize TS queues. */ + err = R_LAYER3_SWITCH_CreateDescriptorQueue(p_extend->p_ether_switch->p_ctrl, + &p_extend->p_ts_queue->index, + &p_extend->p_ts_queue->queue_cfg); + } +#endif + + if (FSP_SUCCESS == err) + { + /* Initialize RX queues. */ + for (uint32_t i = 0; i < p_extend->rx_queue_num; i++) + { + err = R_LAYER3_SWITCH_CreateDescriptorQueue(p_extend->p_ether_switch->p_ctrl, + &p_extend->p_rx_queue_list[i].index, + &p_extend->p_rx_queue_list[i].queue_cfg); + if (FSP_SUCCESS != err) + { + break; + } + } + } + + return err; +} + +/*********************************************************************************************************************** + * Reset RX descriptor. If a buffer is passed, set it to descriptor. + * When all descriptors in the queue are reset, increment index of the queue and restart next queue. + ***********************************************************************************************************************/ +static fsp_err_t r_rmac_set_rx_buffer (rmac_instance_ctrl_t * p_instance_ctrl, rmac_buffer_node_t * p_buffer_node) +{ + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + layer3_switch_descriptor_t descriptor = {0}; + fsp_err_t err; + + FSP_ERROR_RETURN(NULL != p_buffer_node, FSP_ERR_BUFFER_EMPTY); + + /* Reset descriptor as waiting for reception. */ + descriptor.basic.err = 0; + descriptor.basic.ds_h = (RMAC_DESCRIPTOR_FIELD_DS_UPPER_MASK & RMAC_MAXIMUM_FRAME_SIZE) >> + RMAC_DESCRIPTOR_FIELD_DS_UPPER_POSITION; + descriptor.basic.ds_l = RMAC_DESCRIPTOR_FIELD_DS_LOWER_MASK & RMAC_MAXIMUM_FRAME_SIZE; + descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY; + descriptor.basic.die = 1; + + /* Update the buffer when a new buffer is passed. */ + descriptor.basic.ptr_h = + (RMAC_DESCRIPTOR_FIELD_PTR_UPPER_MASK & (uint64_t) (uintptr_t) p_buffer_node->p_buffer) >> + RMAC_DESCRIPTOR_FIELD_PTR_UPPER_POSITION; + descriptor.basic.ptr_l = RMAC_DESCRIPTOR_FIELD_PTR_LOWER_MASK & (uintptr_t) p_buffer_node->p_buffer; + + /* Set new buffer to the descriptor. */ + if (RMAC_INVALID_QUEUE_INDEX != p_instance_ctrl->rx_running_queue_index) + { + p_instance_ctrl->read_queue_index = p_instance_ctrl->rx_running_queue_index; + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(p_instance_ctrl->read_queue_index, p_extend->rx_queue_num); + } + + err = + R_LAYER3_SWITCH_SetDescriptor(p_extend->p_ether_switch->p_ctrl, + p_extend->p_rx_queue_list[p_instance_ctrl->read_queue_index].index, &descriptor); + + if (FSP_SUCCESS == err) + { + r_rmac_buffer_enqueue(&p_instance_ctrl->buffer_node_pool, p_buffer_node); + } + else + { + /* Failed to set to the descriptor, store the buffer. */ + r_rmac_buffer_enqueue(&p_instance_ctrl->rx_empty_buffer_queue, p_buffer_node); + if (FSP_ERR_OVERFLOW == err) + { + /* If any RX queue is not running, restart this queue. */ + if ((RMAC_INVALID_QUEUE_INDEX == p_instance_ctrl->rx_running_queue_index) && + (p_instance_ctrl->rx_initialized_buffer_num == p_instance_ctrl->p_cfg->num_rx_descriptors)) + { + fsp_err_t serr = R_LAYER3_SWITCH_StartDescriptorQueue(p_extend->p_ether_switch->p_ctrl, + p_extend->p_rx_queue_list[p_instance_ctrl-> + read_queue_index].index); + if (FSP_SUCCESS == serr) + { + p_instance_ctrl->rx_running_queue_index = p_instance_ctrl->read_queue_index; + } + else + { + p_instance_ctrl->rx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + } + } + + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(p_instance_ctrl->read_queue_index, p_extend->rx_queue_num); + } + } + + return err; +} + +/*********************************************************************************************************************** + * Set a buffer to the TX descriptor queue. + ***********************************************************************************************************************/ +static fsp_err_t r_rmac_set_tx_buffer (rmac_instance_ctrl_t * p_instance_ctrl, + void * p_write_buffer, + uint32_t frame_length, + uint32_t queue_index) +{ + layer3_switch_descriptor_t descriptor = {0}; + fsp_err_t err; + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + layer3_switch_extended_cfg_t * p_layer3_switch_extend = + (layer3_switch_extended_cfg_t *) p_extend->p_ether_switch->p_cfg->p_extend; + + /* Set the buffer address to the descriptor. */ + descriptor.basic.ptr_h = (RMAC_DESCRIPTOR_FIELD_PTR_UPPER_MASK & (uint64_t) (uintptr_t) p_write_buffer) >> + RMAC_DESCRIPTOR_FIELD_PTR_UPPER_POSITION; + descriptor.basic.ptr_l = RMAC_DESCRIPTOR_FIELD_PTR_LOWER_MASK & (uintptr_t) p_write_buffer; + + /* Configure transmission descriptor. */ + descriptor.basic.ds_h = (RMAC_DESCRIPTOR_FIELD_DS_UPPER_MASK & frame_length) >> + RMAC_DESCRIPTOR_FIELD_DS_UPPER_POSITION; + descriptor.basic.ds_l = RMAC_DESCRIPTOR_FIELD_DS_LOWER_MASK & frame_length; + descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_FSINGLE; + descriptor.basic.die = 1; + descriptor.info1_tx.dv = RMAC_DESCRIPTOR_FIELD_DV_MASK & (1 << p_instance_ctrl->p_cfg->channel); + descriptor.info1_tx.fmt = 1; + + if (RMAC_WRITE_CFG_TX_TIMESTAMP_ENABLE == p_instance_ctrl->write_cfg.tx_timestamp_enable) + { + descriptor.info1_tx.txc = 1; + descriptor.info1_tx.tn = + (uint8_t) (p_layer3_switch_extend->gptp_timer_numbers[p_instance_ctrl->p_cfg->channel] & 0x1); + descriptor.info1_tx.tsun = + (p_instance_ctrl->tx_timestamp_seq_num & RMAC_TS_SEQUENCE_NUMBER_MASK); + p_instance_ctrl->tx_timestamp_seq_num = (p_instance_ctrl->tx_timestamp_seq_num + 1) & + RMAC_TS_SEQUENCE_NUMBER_MASK; + } + else + { + descriptor.info1_tx.txc = 0; + descriptor.info1_tx.tn = 0; + descriptor.info1_tx.tsun = 0; + } + + err = + R_LAYER3_SWITCH_SetDescriptor(p_extend->p_ether_switch->p_ctrl, queue_index, &descriptor); + + return err; +} + +/*********************************************************************************************************************** + * Start a TX descriptor queue. + ***********************************************************************************************************************/ +static fsp_err_t r_rmac_start_tx_queue (rmac_instance_ctrl_t * p_instance_ctrl, uint32_t queue_index) +{ + layer3_switch_descriptor_t descriptor = {0}; + fsp_err_t err = FSP_SUCCESS; + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + /* Try to set a terminate descriptor to imply the end of the queue. */ + descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY; + + while (FSP_SUCCESS == err) + { + err = R_LAYER3_SWITCH_SetDescriptor(p_extend->p_ether_switch->p_ctrl, queue_index, &descriptor); + } + + /* Start transmission. */ + err = R_LAYER3_SWITCH_StartDescriptorQueue(p_extend->p_ether_switch->p_ctrl, queue_index); + + if (RMAC_WRITE_CFG_TX_TIMESTAMP_ENABLE == p_instance_ctrl->write_cfg.tx_timestamp_enable) + { + for (uint32_t i = 0; i < RMAC_GET_TX_TIMESTAMP_WAIT_TIME; i++) + { + /* If found tx timestamp, break from wait time. */ + if (FSP_SUCCESS == r_rmac_get_tx_timestamp(p_instance_ctrl)) + { + break; + } + } + + /* Clear write configuration for next write */ + p_instance_ctrl->write_cfg.tx_timestamp_enable = 0; + } + + return err; +} + +/******************************************************************************************************************* + * Disable reception on this port. + **********************************************************************************************************************/ +static void r_rmac_disable_reception (rmac_instance_ctrl_t * p_instance_ctrl) +{ + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + layer3_switch_port_cfg_t port_cfg = {0}; + layer3_switch_descriptor_t descriptor = {0}; + + /* When magic packet detection is enabled, disable data interrupt. */ + port_cfg.p_callback = NULL; + + /* Disable CPU reception from this port. */ + port_cfg.forwarding_to_cpu_enable = false; + R_LAYER3_SWITCH_ConfigurePort(p_extend->p_ether_switch->p_ctrl, p_instance_ctrl->p_cfg->channel, &port_cfg); + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Set the all RX descriptors to stop state. */ + descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY; + for (uint32_t j = 0; j < p_extend->rx_queue_num; ++j) + { + /* Perform starting reception to initialize queue status. */ + R_LAYER3_SWITCH_StartDescriptorQueue(p_extend->p_ether_switch->p_ctrl, p_extend->p_rx_queue_list[j].index); + + for (uint32_t i = 0; i < p_extend->p_rx_queue_list[j].queue_cfg.array_length; i++) + { + R_LAYER3_SWITCH_SetDescriptor(p_extend->p_ether_switch->p_ctrl, + p_extend->p_rx_queue_list[j].index, + &descriptor); + } + + /* Perform starting reception to initialize queue status. */ + R_LAYER3_SWITCH_StartDescriptorQueue(p_extend->p_ether_switch->p_ctrl, p_extend->p_rx_queue_list[j].index); + } + + p_instance_ctrl->rx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + + FSP_CRITICAL_SECTION_EXIT; +} + +/** Get the node from head of the queue and remove it. */ +static rmac_buffer_node_t * r_rmac_buffer_dequeue (rmac_buffer_queue_t * p_queue) +{ + /* Use critical section to prevent concurrent access to the queue. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + rmac_buffer_node_t * p_node = p_queue->p_head; + if (NULL != p_node) + { + p_queue->p_head = p_node->p_next; + if (NULL == p_queue->p_head) + { + /* If the queue become empty, set the tail to the empty. */ + p_queue->p_tail = NULL; + } + + p_node->p_next = NULL; + } + + FSP_CRITICAL_SECTION_EXIT; + + return p_node; +} + +/** Add the node to tail of the queue. */ +static void r_rmac_buffer_enqueue (rmac_buffer_queue_t * p_queue, rmac_buffer_node_t * p_node) +{ + /* Use critical section to prevent concurrent access to the queue. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* To add as a terminal node, set the next node to NULL. */ + if (NULL != p_node) + { + p_node->p_next = NULL; + + if (NULL != p_queue->p_tail) + { + p_queue->p_tail->p_next = p_node; + } + else + { + /* If the queue is empty, set the node also to the head. */ + p_queue->p_head = p_node; + } + + p_queue->p_tail = p_node; + } + + FSP_CRITICAL_SECTION_EXIT; +} + +static fsp_err_t r_rmac_get_rx_queue (rmac_instance_ctrl_t * p_instance_ctrl, uint32_t queue_index) +{ + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + layer3_switch_descriptor_t descriptor; + rmac_buffer_node_t * p_buffer_node = NULL; + fsp_err_t get_err; + + /* Read all descriptors in the queue. */ + get_err = R_LAYER3_SWITCH_GetDescriptor(p_extend->p_ether_switch->p_ctrl, queue_index, &descriptor); + while (FSP_SUCCESS == get_err) + { + /* Store the read buffer as the RX completed buffer. */ + p_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->buffer_node_pool); + if (NULL != p_buffer_node) + { + if ((RMAC_INVALID_QUEUE_INDEX != p_instance_ctrl->rx_running_queue_index) && + (queue_index != p_extend->p_rx_queue_list[p_instance_ctrl->rx_running_queue_index].index)) + { + /* When the queue raising this interrupt is not the same as the currently running queue, discard data. */ + p_buffer_node->p_buffer = (void *) (uintptr_t) descriptor.basic.ptr_l; + r_rmac_buffer_enqueue(&p_instance_ctrl->rx_empty_buffer_queue, p_buffer_node); + } + else + { + /* Store the received buffer. */ + p_buffer_node->p_buffer = (void *) (uintptr_t) descriptor.basic.ptr_l; + p_buffer_node->size = + (uint32_t) ((descriptor.basic.ds_h << RMAC_DESCRIPTOR_FIELD_DS_UPPER_POSITION) + + descriptor.basic.ds_l); + r_rmac_buffer_enqueue(&p_instance_ctrl->rx_completed_buffer_queue, p_buffer_node); + +#if LAYER3_SWITCH_CFG_GPTP_ENABLE + + /* Get timestamp. */ + if (1 == descriptor.reception_ethernet_descriptor.tsv) + { + p_buffer_node->timestamp.ns = descriptor.reception_ethernet_descriptor.tsns; + p_buffer_node->timestamp.sec_lower = descriptor.reception_ethernet_descriptor.tss; + } + else + { + p_buffer_node->timestamp.ns = 0; + p_buffer_node->timestamp.sec_lower = 0; + } +#endif + } + } + + get_err = R_LAYER3_SWITCH_GetDescriptor(p_extend->p_ether_switch->p_ctrl, queue_index, &descriptor); + } + + return get_err; +} + +static fsp_err_t r_rmac_set_rx_queue (rmac_instance_ctrl_t * p_instance_ctrl, uint32_t queue_index) +{ + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + layer3_switch_descriptor_t descriptor; + rmac_buffer_node_t * p_new_buffer_node = NULL; + fsp_err_t set_err = FSP_SUCCESS; + + /* When get the all descriptors in the queue, set new descriptors. */ + while (FSP_SUCCESS == set_err) + { + p_new_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->rx_empty_buffer_queue); + if (NULL != p_new_buffer_node) + { + descriptor.basic.err = 0; + descriptor.basic.ds_h = (RMAC_DESCRIPTOR_FIELD_DS_UPPER_MASK & RMAC_MAXIMUM_FRAME_SIZE) >> + RMAC_DESCRIPTOR_FIELD_DS_UPPER_POSITION; + descriptor.basic.ds_l = RMAC_DESCRIPTOR_FIELD_DS_LOWER_MASK & RMAC_MAXIMUM_FRAME_SIZE; + descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY; + descriptor.basic.die = 1; + descriptor.basic.ptr_h = + (RMAC_DESCRIPTOR_FIELD_PTR_UPPER_MASK & (uint64_t) (uintptr_t) p_new_buffer_node->p_buffer) >> + RMAC_DESCRIPTOR_FIELD_PTR_UPPER_POSITION; + descriptor.basic.ptr_l = RMAC_DESCRIPTOR_FIELD_PTR_LOWER_MASK & + (uintptr_t) p_new_buffer_node->p_buffer; + } + else + { + /* If no buffer is available, set LEMPTY. */ + descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY; + descriptor.basic.ptr_l = 0; + } + + set_err = R_LAYER3_SWITCH_SetDescriptor(p_extend->p_ether_switch->p_ctrl, queue_index, &descriptor); + if (NULL != p_new_buffer_node) + { + if (FSP_SUCCESS == set_err) + { + /* Store the buffer node. */ + r_rmac_buffer_enqueue(&p_instance_ctrl->buffer_node_pool, p_new_buffer_node); + } + else + { + /* Back the buffer node to the pool. */ + r_rmac_buffer_enqueue(&p_instance_ctrl->rx_empty_buffer_queue, p_new_buffer_node); + } + } + } + + return set_err; +} + +static fsp_err_t r_rmac_get_tx_timestamp (rmac_instance_ctrl_t * p_instance_ctrl) +{ + fsp_err_t err = FSP_ERR_NOT_FOUND; + rmac_extended_cfg_t * p_rmac_extended_cfg = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + layer3_switch_descriptor_queue_cfg_t queue_cfg = p_rmac_extended_cfg->p_ts_queue->queue_cfg; + + /* Search tx timestamp from ts reception descriptor that has same timestamp id and not empty. */ + for (uint8_t i = 0; i < (queue_cfg.array_length - 1); i++) + { + if ((LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_ND != + queue_cfg.p_ts_descriptor_array[i].ts_reception_descriptor_result.dt) && + (((p_instance_ctrl->tx_timestamp_seq_num - 1) & RMAC_TS_SEQUENCE_NUMBER_MASK) == + queue_cfg.p_ts_descriptor_array[i].ts_reception_descriptor_result.tsun)) + { + p_instance_ctrl->tx_timestamp.sec_lower = + queue_cfg.p_ts_descriptor_array[i].ts_reception_descriptor_result.tss; + p_instance_ctrl->tx_timestamp.ns = + queue_cfg.p_ts_descriptor_array[i].ts_reception_descriptor_result.tsns; + + queue_cfg.p_ts_descriptor_array[i].ts_reception_descriptor_result.dt = + LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_ND; + + err = FSP_SUCCESS; + break; + } + } + + return err; +} + +/*********************************************************************************************************************** + * Function Name: r_rmac_switch_interrupt_callback + * Description : Callback for RX/TX data interrupts. This function set to switch module callback. + ***********************************************************************************************************************/ +static void r_rmac_switch_interrupt_callback (ether_switch_callback_args_t * p_args) +{ + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) p_args->p_context; + rmac_extended_cfg_t * p_extend = (rmac_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + ether_callback_args_t callback_args = {0}; + uint32_t next_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + layer3_switch_descriptor_t descriptor; + rmac_buffer_node_t * p_buffer_node = NULL; + fsp_err_t get_err = FSP_SUCCESS; + fsp_err_t err = FSP_SUCCESS; + + switch (p_args->event) + { + case ETHER_SWITCH_EVENT_TX_COMPLETE: + { + callback_args.event = ETHER_EVENT_TX_COMPLETE; + get_err = R_LAYER3_SWITCH_GetDescriptor(p_extend->p_ether_switch->p_ctrl, + p_args->queue_index, + &descriptor); + while (FSP_SUCCESS == get_err) + { + /* If zerocopy is enabled, save the last sent buffer. */ + if (ETHER_ZEROCOPY_ENABLE == p_instance_ctrl->p_cfg->zerocopy) + { + if (LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY == descriptor.basic.dt) + { + p_instance_ctrl->p_last_sent_buffer = (void *) (uintptr_t) descriptor.basic.ptr_l; + } + } + else + { + /* Store the buffer to the buffer pool. */ + p_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->buffer_node_pool); + if (NULL != p_buffer_node) + { + p_buffer_node->p_buffer = (void *) (uintptr_t) descriptor.basic.ptr_l; + r_rmac_buffer_enqueue(&p_instance_ctrl->tx_empty_buffer_queue, p_buffer_node); + } + } + + get_err = R_LAYER3_SWITCH_GetDescriptor(p_extend->p_ether_switch->p_ctrl, + p_args->queue_index, + &descriptor); + } + + /* When finish transmission on the queue. */ + if (get_err == FSP_ERR_NOT_INITIALIZED) + { + p_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->tx_pending_buffer_queue); + while (NULL != p_buffer_node) + { + err = r_rmac_set_tx_buffer(p_instance_ctrl, + p_buffer_node->p_buffer, + p_buffer_node->size, + p_args->queue_index); + + if (FSP_SUCCESS == err) + { + r_rmac_buffer_enqueue(&p_instance_ctrl->buffer_node_pool, p_buffer_node); + + /* Dequeue the next pending buffer. */ + p_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->tx_pending_buffer_queue); + } + else + { + if (ETHER_ZEROCOPY_DISABLE == p_instance_ctrl->p_cfg->zerocopy) + { + r_rmac_buffer_enqueue(&p_instance_ctrl->tx_empty_buffer_queue, p_buffer_node); + } + else + { + r_rmac_buffer_enqueue(&p_instance_ctrl->buffer_node_pool, p_buffer_node); + } + + p_buffer_node = NULL; + } + } + + /* When pending TX data exits, start the next queue. */ + next_running_queue_index = p_instance_ctrl->tx_running_queue_index; + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(next_running_queue_index, p_extend->tx_queue_num); + err = + r_rmac_start_tx_queue(p_instance_ctrl, p_extend->p_tx_queue_list[next_running_queue_index].index); + + if (err == FSP_SUCCESS) + { + p_instance_ctrl->tx_running_queue_index = next_running_queue_index; + } + else + { + p_instance_ctrl->tx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + } + } + + break; + } + + case ETHER_SWITCH_EVENT_RX_COMPLETE: + { + p_instance_ctrl->is_lost_rx_packet = false; + + /* When the link is down, ignore this event. */ + FSP_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, ); + + /* Read all descriptors in the queue. */ + err = r_rmac_get_rx_queue(p_instance_ctrl, p_args->queue_index); + if (FSP_ERR_NOT_INITIALIZED == err) + { + err = r_rmac_set_rx_queue(p_instance_ctrl, p_args->queue_index); + } + + if (FSP_ERR_OVERFLOW == err) + { + /* Start reception on next queue. */ + next_running_queue_index = p_instance_ctrl->rx_running_queue_index; + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(next_running_queue_index, p_extend->rx_queue_num); + err = + R_LAYER3_SWITCH_StartDescriptorQueue(p_extend->p_ether_switch->p_ctrl, + p_extend->p_rx_queue_list[next_running_queue_index].index); + + if (FSP_SUCCESS == err) + { + p_instance_ctrl->rx_running_queue_index = next_running_queue_index; + } + else + { + p_instance_ctrl->rx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + } + } + + callback_args.event = ETHER_EVENT_RX_COMPLETE; + break; + } + + case ETHER_SWITCH_EVENT_RX_QUEUE_FULL: + { + p_instance_ctrl->is_lost_rx_packet = false; + + /* When the link is down, ignore this event. */ + FSP_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, ); + + if ((RMAC_INVALID_QUEUE_INDEX != p_instance_ctrl->rx_running_queue_index) && + (p_args->queue_index == p_extend->p_rx_queue_list[p_instance_ctrl->rx_running_queue_index].index)) + { + get_err = R_LAYER3_SWITCH_GetDescriptor(p_extend->p_ether_switch->p_ctrl, + p_args->queue_index, + &descriptor); + if (FSP_SUCCESS == get_err) + { + /* Start reception on next queue. */ + next_running_queue_index = p_instance_ctrl->rx_running_queue_index; + RMAC_INCREMENT_DESCRIPTOR_QUEUE_INDEX(next_running_queue_index, p_extend->rx_queue_num); + err = + R_LAYER3_SWITCH_StartDescriptorQueue(p_extend->p_ether_switch->p_ctrl, + p_extend->p_rx_queue_list[next_running_queue_index].index); + + /* Store the read buffer as the RX completed buffer. */ + p_buffer_node = r_rmac_buffer_dequeue(&p_instance_ctrl->buffer_node_pool); + if (NULL != p_buffer_node) + { + /* Store the received buffer. */ + p_buffer_node->p_buffer = (void *) (uintptr_t) descriptor.basic.ptr_l; + p_buffer_node->size = + (uint32_t) ((descriptor.basic.ds_h << RMAC_DESCRIPTOR_FIELD_DS_UPPER_POSITION) + + descriptor.basic.ds_l); + r_rmac_buffer_enqueue(&p_instance_ctrl->rx_completed_buffer_queue, p_buffer_node); + +#if LAYER3_SWITCH_CFG_GPTP_ENABLE + + /* Get timestamp. */ + if (1 == descriptor.reception_ethernet_descriptor.tsv) + { + p_buffer_node->timestamp.ns = descriptor.reception_ethernet_descriptor.tsns; + p_buffer_node->timestamp.sec_lower = descriptor.reception_ethernet_descriptor.tss; + } + else + { + p_buffer_node->timestamp.ns = 0; + p_buffer_node->timestamp.sec_lower = 0; + } +#endif + } + + if (FSP_SUCCESS == err) + { + p_instance_ctrl->rx_running_queue_index = next_running_queue_index; + } + else + { + p_instance_ctrl->rx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + } + + r_rmac_get_rx_queue(p_instance_ctrl, p_args->queue_index); + r_rmac_set_rx_queue(p_instance_ctrl, p_args->queue_index); + } + } + + callback_args.event = ETHER_EVENT_RX_COMPLETE; + break; + } + + case ETHER_SWITCH_EVENT_RX_MESSAGE_LOST: + { + /* When the link is down, ignore this event. */ + FSP_ERROR_RETURN(ETHER_LINK_ESTABLISH_STATUS_UP == p_instance_ctrl->link_establish_status, ); + + callback_args.event = ETHER_EVENT_RX_MESSAGE_LOST; + + /* When the lost error occurs repeatedly, treat the queue as stopped. */ + if (p_instance_ctrl->is_lost_rx_packet) + { + r_rmac_get_rx_queue(p_instance_ctrl, p_args->queue_index); + r_rmac_set_rx_queue(p_instance_ctrl, p_args->queue_index); + p_instance_ctrl->rx_running_queue_index = RMAC_INVALID_QUEUE_INDEX; + p_instance_ctrl->is_lost_rx_packet = false; + } + + if ((RMAC_INVALID_QUEUE_INDEX != p_instance_ctrl->rx_running_queue_index) && + (p_args->queue_index == p_extend->p_rx_queue_list[p_instance_ctrl->rx_running_queue_index].index)) + { + p_instance_ctrl->is_lost_rx_packet = true; + } + + break; + } + + default: + { + break; + } + } + + if (NULL != p_instance_ctrl->p_callback) + { + rmac_call_callback(p_instance_ctrl, &callback_args); + } +} + +/*********************************************************************************************************************** + * Function Name: rmac_rmpi_isr + * Description : Interrupt handler for RMPI interrupts. + * Arguments : none + * Return Value : none + ***********************************************************************************************************************/ +void rmac_rmpi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + ether_callback_args_t callback_arg; + uint32_t status_rmpi; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + rmac_instance_ctrl_t * p_instance_ctrl = (rmac_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + status_rmpi = p_instance_ctrl->p_reg_rmac->MMIS2; + + /* When the Magic Packet detection interrupt is generated */ + if (status_rmpi & R_RMAC0_MMIS2_MPDIS_Msk) + { + /* Disable the interrupt of Magic packet detection. */ + p_instance_ctrl->p_reg_rmac->MMID2_b.MPDID = 1; + + /* If a callback is provided, then call it with callback argument. */ + if (NULL != p_instance_ctrl->p_callback) + { + callback_arg.channel = p_instance_ctrl->p_cfg->channel; + callback_arg.event = ETHER_EVENT_WAKEON_LAN; + callback_arg.p_context = p_instance_ctrl->p_cfg->p_context; + rmac_call_callback(p_instance_ctrl, &callback_arg); + } + + if (ETHER_WAKE_ON_LAN_ENABLE == p_instance_ctrl->wake_on_lan) + { + /* Initialize the link status. */ + p_instance_ctrl->link_establish_status = ETHER_LINK_ESTABLISH_STATUS_DOWN; + p_instance_ctrl->link_change = ETHER_LINK_CHANGE_NO_CHANGE; + p_instance_ctrl->previous_link_status = ETHER_PREVIOUS_LINK_STATUS_DOWN; + + /* + * Call LinkProcess to initialize descriptors and resume reception. + * If the link is down, it need to call LinkProcess again after this interrput. + */ + R_RMAC_LinkProcess(p_instance_ctrl); + } + } + + /* Clear RMPI status bit. */ + p_instance_ctrl->p_reg_rmac->MMIS2 = status_rmpi; /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ + + /* Clear pending interrupt flag to make sure it doesn't fire again + * after exiting. */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} /* End of function rmac_rmpi_isr() */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/r_rmac_phy.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/r_rmac_phy.c new file mode 100644 index 0000000000..2f2f874939 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/r_rmac_phy.c @@ -0,0 +1,1217 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_rmac_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ +#ifndef RMAC_PHY_ERROR_RETURN + #define RMAC_PHY_ERROR_RETURN(a, err) FSP_ERROR_RETURN((a), (err)) +#endif + +#define RMAC_REG_SIZE (R_RMAC1_BASE - R_RMAC0_BASE) +#define ETHA_REG_SIZE (R_ETHA1_BASE - R_ETHA0_BASE) + +/** "RPHY" in ASCII. Used to determine if the control block is open. */ +#define RMAC_PHY_OPEN (('R' << 24U) | ('P' << 16U) | ('H' << 8U) | ('Y' << 0U)) + +/* Standard PHY Registers */ +#define RMAC_PHY_REG_CONTROL (0) +#define RMAC_PHY_REG_STATUS (1) +#define RMAC_PHY_REG_IDENTIFIER1 (2) +#define RMAC_PHY_REG_IDENTIFIER2 (3) +#define RMAC_PHY_REG_AN_ADVERTISEMENT (4) +#define RMAC_PHY_REG_AN_LINK_PARTNER (5) +#define RMAC_PHY_REG_AN_EXPANSION (6) +#define RMAC_PHY_REG_GIGABIT_CONTROL (9) +#define RMAC_PHY_REG_GIGABIT_STATUS (10) + +/* Basic Mode Control Register Bit Definitions */ +#define RMAC_PHY_CONTROL_RESET (1 << 15) +#define RMAC_PHY_CONTROL_LOOPBACK (1 << 14) +#define RMAC_PHY_CONTROL_100_MBPS (1 << 13) +#define RMAC_PHY_CONTROL_AN_ENABLE (1 << 12) +#define RMAC_PHY_CONTROL_POWER_DOWN (1 << 11) +#define RMAC_PHY_CONTROL_ISOLATE (1 << 10) +#define RMAC_PHY_CONTROL_AN_RESTART (1 << 9) +#define RMAC_PHY_CONTROL_FULL_DUPLEX (1 << 8) +#define RMAC_PHY_CONTROL_COLLISION (1 << 7) + +/* Basic Mode Status Register Bit Definitions */ +#define RMAC_PHY_STATUS_100_T4 (1 << 15) +#define RMAC_PHY_STATUS_100F (1 << 14) +#define RMAC_PHY_STATUS_100H (1 << 13) +#define RMAC_PHY_STATUS_10F (1 << 12) +#define RMAC_PHY_STATUS_10H (1 << 11) +#define RMAC_PHY_STATUS_AN_COMPLETE (1 << 5) +#define RMAC_PHY_STATUS_RM_FAULT (1 << 4) +#define RMAC_PHY_STATUS_AN_ABILITY (1 << 3) +#define RMAC_PHY_STATUS_LINK_UP (1 << 2) +#define RMAC_PHY_STATUS_JABBER (1 << 1) +#define RMAC_PHY_STATUS_EX_CAPABILITY (1 << 0) + +/* Auto Negotiation Advertisement Bit Definitions */ +#define RMAC_PHY_AN_ADVERTISEMENT_NEXT_PAGE (1 << 15) +#define RMAC_PHY_AN_ADVERTISEMENT_RM_FAULT (1 << 13) +#define RMAC_PHY_AN_ADVERTISEMENT_ASM_DIR (1 << 11) +#define RMAC_PHY_AN_ADVERTISEMENT_PAUSE (1 << 10) +#define RMAC_PHY_AN_ADVERTISEMENT_100_T4 (1 << 9) +#define RMAC_PHY_AN_ADVERTISEMENT_100F (1 << 8) +#define RMAC_PHY_AN_ADVERTISEMENT_100H (1 << 7) +#define RMAC_PHY_AN_ADVERTISEMENT_10F (1 << 6) +#define RMAC_PHY_AN_ADVERTISEMENT_10H (1 << 5) +#define RMAC_PHY_AN_ADVERTISEMENT_SELECTOR (1 << 0) + +/* Auto Negotiate Link Partner Ability Bit Definitions */ +#define RMAC_PHY_AN_LINK_PARTNER_NEXT_PAGE (1 << 15) +#define RMAC_PHY_AN_LINK_PARTNER_ACK (1 << 14) +#define RMAC_PHY_AN_LINK_PARTNER_RM_FAULT (1 << 13) +#define RMAC_PHY_AN_LINK_PARTNER_ASM_DIR (1 << 11) +#define RMAC_PHY_AN_LINK_PARTNER_PAUSE (1 << 10) +#define RMAC_PHY_AN_LINK_PARTNER_100_T4 (1 << 9) +#define RMAC_PHY_AN_LINK_PARTNER_100F (1 << 8) +#define RMAC_PHY_AN_LINK_PARTNER_100H (1 << 7) +#define RMAC_PHY_AN_LINK_PARTNER_10F (1 << 6) +#define RMAC_PHY_AN_LINK_PARTNER_10H (1 << 5) +#define RMAC_PHY_AN_LINK_PARTNER_SELECTOR (1 << 0) + +/* Gigabit Control Bit Definitions */ +#define RMAC_PHY_GIGABIT_CONTROL_1000F (1 << 9) +#define RMAC_PHY_GIGABIT_CONTROL_1000H (1 << 8) + +/* Gigabit Status Bit Definitions. LP stands for Link Partner. */ +#define RMAC_PHY_GIGABIT_STATUS_LP_1000H (1 << 10) +#define RMAC_PHY_GIGABIT_STATUS_LP_1000F (1 << 11) + +#define RMAC_PHY_ADDRESS_SIZE (0x1fU) +#define RMAC_PHY_REGISTER_DATA_SIZE (0xffffU) + +/* MDIO frame OP code */ +#define RMAC_PHY_MDIO_OPCODE_WRITE (0x1) +#define RMAC_PHY_MDIO_OPCODE_READ (0x2) + +/* eMDIO frame OP code */ +#define RMAC_PHY_EMDIO_OPCODE_ADDRESS (0x0) +#define RMAC_PHY_EMDIO_OPCODE_WRITE (0x1) +#define RMAC_PHY_EMDIO_OPCODE_READ (0x3) +#define RMAC_PHY_EMDIO_OPCODE_POST_READ (0x2) + +/* Operation mode of ETHA*/ +#define RMAC_PHY_ETHA_CONFIG_MODE (0b10) +#define RMAC_PHY_ETHA_OPERATION_MODE (0b11) +#define RMAC_PHY_ETHA_DISABLE_MODE (0b01) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) +extern void rmac_phy_target_ksz8091rnb_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +extern bool rmac_phy_target_ksz8091rnb_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif +#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) +extern void rmac_phy_target_ksz8041_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +extern bool rmac_phy_target_ksz8041_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif +#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) +extern void rmac_phy_target_dp83620_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +extern bool rmac_phy_target_dp83620_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) +extern void rmac_phy_target_ics1894_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +extern bool rmac_phy_target_ics1894_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif + +#if (ETHER_PHY_CFG_TARGET_GPY111_ENABLE) +extern void rmac_phy_target_gpy111_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +extern bool rmac_phy_target_gpy111_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +#endif + +void rmac_phy_easi_isr(void); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ +static void rmac_phy_targets_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +static bool rmac_phy_targets_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); +static uint32_t r_rmac_phy_calculate_mpic(rmac_phy_instance_ctrl_t * p_instance_ctrl, uint32_t line_speed_duplex); +static uint8_t r_rmac_phy_get_operation_mode(rmac_phy_instance_ctrl_t * p_instance_ctrl); +static void r_rmac_phy_set_operation_mode(uint32_t channel, uint8_t mode); +static void r_rmac_phy_set_mii_type_configuration(rmac_phy_instance_ctrl_t * p_instance_ctrl, uint8_t port); + +/** RMAC_PHY HAL API mapping for Ethernet PHY Controller interface */ +/*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */ +const ether_phy_api_t g_ether_phy_on_rmac_phy = +{ + .open = R_RMAC_PHY_Open, + .close = R_RMAC_PHY_Close, + .startAutoNegotiate = R_RMAC_PHY_StartAutoNegotiate, + .linkPartnerAbilityGet = R_RMAC_PHY_LinkPartnerAbilityGet, + .linkStatusGet = R_RMAC_PHY_LinkStatusGet, + .chipInit = R_RMAC_PHY_ChipInit, + .read = R_RMAC_PHY_Read, + .write = R_RMAC_PHY_Write +}; + +/*******************************************************************************************************************//** + * @addtogroup RMAC_PHY + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/********************************************************************************************************************//** + * @brief Resets Ethernet PHY device. Implements @ref ether_phy_api_t::open. + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block is NULL. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_CHANNEL Invalid channel number is given. + * @retval FSP_ERR_INVALID_POINTER Pointer to p_cfg is NULL. + * @retval FSP_ERR_INVALID_MODE Function is called when not in CONFIG mode. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_Open (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + rmac_phy_extended_cfg_t * p_extend; + uint32_t link_speed = ETHER_PHY_LINK_SPEED_10F; + R_RMAC0_Type * p_reg_rmac; + +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + RMAC_PHY_ERROR_RETURN(NULL != p_cfg, FSP_ERR_INVALID_POINTER); + RMAC_PHY_ERROR_RETURN((RMAC_PHY_OPEN != p_instance_ctrl->open), FSP_ERR_ALREADY_OPEN); + RMAC_PHY_ERROR_RETURN((BSP_FEATURE_ETHER_NUM_CHANNELS > p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + p_extend = (rmac_phy_extended_cfg_t *) p_cfg->p_extend; + RMAC_PHY_ERROR_RETURN(NULL != p_extend, FSP_ERR_INVALID_POINTER); + RMAC_PHY_ERROR_RETURN(NULL != p_extend->p_phy_lsi_cfg_list[p_extend->default_phy_lsi_cfg_index], + FSP_ERR_INVALID_ARGUMENT); +#else + p_extend = (rmac_phy_extended_cfg_t *) p_cfg->p_extend; +#endif + + /* Initialize configuration of ethernet phy module. */ + p_instance_ctrl->p_ether_phy_cfg = p_cfg; + p_instance_ctrl->p_callback = p_extend->p_callback; + p_instance_ctrl->p_context = p_extend->p_context; + + /* ETHA IP should be CONFIG mode */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ETHA_CONFIG_MODE == r_rmac_phy_get_operation_mode(p_instance_ctrl), + FSP_ERR_INVALID_MODE); + + /* Set the RMAC register address of this channel. */ + p_instance_ctrl->p_reg_rmac = (R_RMAC0_Type *) (R_RMAC0_BASE + (RMAC_REG_SIZE * p_cfg->channel)); + p_instance_ctrl->local_advertise = 0; + + /* Copy default PHY LSI settings. */ + p_instance_ctrl->phy_lsi_cfg_index = p_extend->default_phy_lsi_cfg_index; + + /* Configure maximum link speed for each interface. */ + if ((ETHER_PHY_MII_TYPE_MII == p_instance_ctrl->p_ether_phy_cfg->mii_type) || + (ETHER_PHY_MII_TYPE_RMII == p_instance_ctrl->p_ether_phy_cfg->mii_type)) + { + link_speed = ETHER_PHY_LINK_SPEED_100F; + } + else if ((ETHER_PHY_MII_TYPE_GMII == p_instance_ctrl->p_ether_phy_cfg->mii_type) || + (ETHER_PHY_MII_TYPE_RGMII == p_instance_ctrl->p_ether_phy_cfg->mii_type)) + { + link_speed = ETHER_PHY_LINK_SPEED_1000F; + } + else + { + ; + } + + /* Configure PHY interface for each available channels. */ + for (uint32_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + if (NULL != p_extend->p_phy_lsi_cfg_list[i]) + { + p_reg_rmac = (R_RMAC0_Type *) (R_RMAC0_BASE + (RMAC_REG_SIZE * i)); + p_reg_rmac->MPIC = r_rmac_phy_calculate_mpic(p_instance_ctrl, link_speed); + + /* Enable frame preemption feature. */ + if (p_extend->frame_preemption_enable) + { + r_rmac_phy_set_operation_mode(i, RMAC_PHY_ETHA_DISABLE_MODE); + r_rmac_phy_set_operation_mode(i, RMAC_PHY_ETHA_OPERATION_MODE); + + p_reg_rmac->MLVC = R_RMAC0_MLVC_PASE_Msk; + if (p_extend->easi_irq[i] >= 0) + { + p_reg_rmac->MMIE0 = R_RMAC0_MMIE0_LVSE_Msk | R_RMAC0_MMIE0_LVFE_Msk | R_RMAC0_MMIE0_VFRE_Msk; + R_BSP_IrqCfgEnable(p_extend->easi_irq[i], p_extend->easi_ipl[i], p_instance_ctrl); + } + + r_rmac_phy_set_operation_mode(i, RMAC_PHY_ETHA_DISABLE_MODE); + r_rmac_phy_set_operation_mode(i, RMAC_PHY_ETHA_CONFIG_MODE); + } + } + } + + p_instance_ctrl->open = RMAC_PHY_OPEN; + + return err; +} /* End of function R_RMAC_PHY_Open() */ + +/********************************************************************************************************************//** + * @brief Close Ethernet PHY device. Implements @ref ether_phy_api_t::close. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_INVALID_MODE Function is called when not in DISABLE mode. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_Close (ether_phy_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* ETHA IP should be DISABLE mode */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ETHA_DISABLE_MODE == r_rmac_phy_get_operation_mode(p_instance_ctrl), + FSP_ERR_INVALID_MODE); + + /** Clear configure block parameters. */ + p_instance_ctrl->p_ether_phy_cfg = NULL; + p_instance_ctrl->local_advertise = 0; + p_instance_ctrl->p_reg_rmac = NULL; + + p_instance_ctrl->interface_status = RMAC_PHY_INTERFACE_STATUS_UNINITIALIZED; + p_instance_ctrl->open = 0; + + return err; +} /* End of function R_RMAC_PHY_Close() */ + +/********************************************************************************************************************//** + * @brief Starts auto-negotiate. Implements @ref ether_phy_api_t::startAutoNegotiate. + * + * @retval FSP_SUCCESS RMAC_PHY successfully starts auto-negotiate. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + * @retval FSP_ERR_INVALID_MODE Function is called when not in OPERATION mode. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_StartAutoNegotiate (ether_phy_ctrl_t * const p_ctrl) +{ + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* ETHA IP should be OPERATION mode */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ETHA_OPERATION_MODE == r_rmac_phy_get_operation_mode(p_instance_ctrl), + FSP_ERR_INVALID_MODE); + + /* Set local ability */ + /* When pause frame is not used */ + if (ETHER_PHY_FLOW_CONTROL_DISABLE == p_instance_ctrl->p_ether_phy_cfg->flow_control) + { + p_instance_ctrl->local_advertise = ((((RMAC_PHY_AN_ADVERTISEMENT_100F | + RMAC_PHY_AN_ADVERTISEMENT_100H) | + RMAC_PHY_AN_ADVERTISEMENT_10F) | + RMAC_PHY_AN_ADVERTISEMENT_10H) | + RMAC_PHY_AN_ADVERTISEMENT_SELECTOR); + } + /* When pause frame is used */ + else + { + p_instance_ctrl->local_advertise = ((((((RMAC_PHY_AN_ADVERTISEMENT_ASM_DIR | + RMAC_PHY_AN_ADVERTISEMENT_PAUSE) | + RMAC_PHY_AN_ADVERTISEMENT_100F) | + RMAC_PHY_AN_ADVERTISEMENT_100H) | + RMAC_PHY_AN_ADVERTISEMENT_10F) | + RMAC_PHY_AN_ADVERTISEMENT_10H) | + RMAC_PHY_AN_ADVERTISEMENT_SELECTOR); + } + + /* Configure what the PHY and the Ethernet controller on this board supports */ + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_AN_ADVERTISEMENT, p_instance_ctrl->local_advertise); + + /* Advertise Gigabit Ethernet capacity when using RGMII or GMII. */ + if ((ETHER_PHY_MII_TYPE_RGMII == p_instance_ctrl->p_ether_phy_cfg->mii_type) || + (ETHER_PHY_MII_TYPE_GMII == p_instance_ctrl->p_ether_phy_cfg->mii_type)) + { + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_GIGABIT_CONTROL, + (RMAC_PHY_GIGABIT_CONTROL_1000F | RMAC_PHY_GIGABIT_CONTROL_1000H)); + } + + /* Start auto-negotiation. */ + R_RMAC_PHY_Write(p_instance_ctrl, + RMAC_PHY_REG_CONTROL, + (RMAC_PHY_CONTROL_AN_ENABLE | + RMAC_PHY_CONTROL_AN_RESTART)); + + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_AN_ADVERTISEMENT, ®); + + return FSP_SUCCESS; +} /* End of function R_RMAC_PHY_StartAutoNegotiate() */ + +/********************************************************************************************************************//** + * @brief Reports the other side's physical capability. Implements @ref ether_phy_api_t::linkPartnerAbilityGet. + * + * @retval FSP_SUCCESS RMAC_PHY successfully get link partner ability. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block is NULL. + * @retval FSP_ERR_INVALID_POINTER Pointer to arguments are NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK PHY-LSI is not link up. + * @retval FSP_ERR_ETHER_PHY_NOT_READY The auto-negotiation isn't completed + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + * @retval FSP_ERR_INVALID_MODE Function is called when not in OPERATION mode. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_LinkPartnerAbilityGet (ether_phy_ctrl_t * const p_ctrl, + uint32_t * const p_line_speed_duplex, + uint32_t * const p_local_pause, + uint32_t * const p_partner_pause) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + uint32_t line_speed_duplex = ETHER_PHY_LINK_SPEED_NO_LINK; + uint32_t mpic; + R_RMAC0_Type * p_reg_rmac; + +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + RMAC_PHY_ERROR_RETURN(NULL != p_line_speed_duplex, FSP_ERR_INVALID_POINTER); + RMAC_PHY_ERROR_RETURN(NULL != p_local_pause, FSP_ERR_INVALID_POINTER); + RMAC_PHY_ERROR_RETURN(NULL != p_partner_pause, FSP_ERR_INVALID_POINTER); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + + /* ETHA IP should be OPERATION mode */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ETHA_OPERATION_MODE == r_rmac_phy_get_operation_mode(p_instance_ctrl), + FSP_ERR_INVALID_MODE); + + /* Because reading the first time shows the previous state, the Link status bit is read twice. */ + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_STATUS, ®); + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_STATUS, ®); + + /* When the link isn't up, return error */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_STATUS_LINK_UP == (reg & RMAC_PHY_STATUS_LINK_UP), FSP_ERR_ETHER_PHY_ERROR_LINK); + + /* Establish local pause capability */ + if (RMAC_PHY_AN_ADVERTISEMENT_PAUSE == (p_instance_ctrl->local_advertise & RMAC_PHY_AN_ADVERTISEMENT_PAUSE)) + { + (*p_local_pause) |= (1 << 1); + } + + if (RMAC_PHY_AN_ADVERTISEMENT_ASM_DIR == (p_instance_ctrl->local_advertise & RMAC_PHY_AN_ADVERTISEMENT_ASM_DIR)) + { + (*p_local_pause) |= 1; + } + + /* When the auto-negotiation isn't completed, return error */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_STATUS_AN_COMPLETE == (reg & RMAC_PHY_STATUS_AN_COMPLETE), + FSP_ERR_ETHER_PHY_NOT_READY); + + /* Get the link partner response */ + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_AN_LINK_PARTNER, ®); + + /* Establish partner pause capability */ + if (RMAC_PHY_AN_LINK_PARTNER_PAUSE == (reg & RMAC_PHY_AN_LINK_PARTNER_PAUSE)) + { + (*p_partner_pause) = (1 << 1); + } + + if (RMAC_PHY_AN_LINK_PARTNER_ASM_DIR == (reg & RMAC_PHY_AN_LINK_PARTNER_ASM_DIR)) + { + (*p_partner_pause) |= 1; + } + + /* Establish the line speed and the duplex */ + if ((RMAC_PHY_AN_LINK_PARTNER_10H == (reg & RMAC_PHY_AN_LINK_PARTNER_10H)) && + rmac_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_10H)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_10H; + } + + if ((RMAC_PHY_AN_LINK_PARTNER_10F == (reg & RMAC_PHY_AN_LINK_PARTNER_10F)) && + rmac_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_10F)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_10F; + } + + if ((RMAC_PHY_AN_LINK_PARTNER_100H == (reg & RMAC_PHY_AN_LINK_PARTNER_100H)) && + rmac_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_100H)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_100H; + } + + if ((RMAC_PHY_AN_LINK_PARTNER_100F == (reg & RMAC_PHY_AN_LINK_PARTNER_100F)) && + rmac_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_100F)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_100F; + } + + /* When MII type is RGMII, check also Gigabit Ethernet ability. */ + if ((ETHER_PHY_MII_TYPE_RGMII == p_instance_ctrl->p_ether_phy_cfg->mii_type) || + (ETHER_PHY_MII_TYPE_GMII == p_instance_ctrl->p_ether_phy_cfg->mii_type)) + { + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_GIGABIT_STATUS, ®); + + if ((RMAC_PHY_GIGABIT_STATUS_LP_1000H == (reg & RMAC_PHY_GIGABIT_STATUS_LP_1000H)) && + rmac_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_1000H)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_1000H; + } + + if ((RMAC_PHY_GIGABIT_STATUS_LP_1000F == (reg & RMAC_PHY_GIGABIT_STATUS_LP_1000F)) && + rmac_phy_targets_is_support_link_partner_ability(p_instance_ctrl, ETHER_PHY_LINK_SPEED_1000F)) + { + line_speed_duplex = ETHER_PHY_LINK_SPEED_1000F; + } + } + + if (ETHER_PHY_LINK_SPEED_NO_LINK == line_speed_duplex) + { + err = FSP_ERR_ETHER_PHY_ERROR_LINK; + } + else + { + (*p_line_speed_duplex) = line_speed_duplex; + } + + mpic = r_rmac_phy_calculate_mpic(p_instance_ctrl, line_speed_duplex); + p_reg_rmac = (R_RMAC0_Type *) (R_RMAC0_BASE + (RMAC_REG_SIZE * p_instance_ctrl->phy_lsi_cfg_index)); + if (mpic != p_reg_rmac->MPIC) + { + /* Set ETHA to CONFIG mode */ + r_rmac_phy_set_operation_mode(p_instance_ctrl->phy_lsi_cfg_index, RMAC_PHY_ETHA_DISABLE_MODE); + r_rmac_phy_set_operation_mode(p_instance_ctrl->phy_lsi_cfg_index, RMAC_PHY_ETHA_CONFIG_MODE); + + p_reg_rmac->MPIC = mpic; + + /* Set ETHA to OPERATION mode */ + r_rmac_phy_set_operation_mode(p_instance_ctrl->phy_lsi_cfg_index, RMAC_PHY_ETHA_DISABLE_MODE); + r_rmac_phy_set_operation_mode(p_instance_ctrl->phy_lsi_cfg_index, RMAC_PHY_ETHA_OPERATION_MODE); + } + + return err; +} /* End of function R_RMAC_PHY_LinkPartnerAbilityGet() */ + +/********************************************************************************************************************//** + * @brief Returns the status of the physical link. Implements @ref ether_phy_api_t::linkStatusGet. + * + * @retval FSP_SUCCESS RMAC_PHY successfully get link partner ability. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ETHER_PHY_ERROR_LINK PHY-LSI is not link up. + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + * @retval FSP_ERR_INVALID_MODE Function is called when not in OPERATION mode. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_LinkStatusGet (ether_phy_ctrl_t * const p_ctrl) +{ + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + fsp_err_t err = FSP_SUCCESS; + rmac_phy_extended_cfg_t * p_extend; + R_RMAC0_Type * p_reg_rmac = NULL; + +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_instance_ctrl->p_ether_phy_cfg->p_extend); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + p_extend = (rmac_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + + /* ETHA IP should be OPERATION mode */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ETHA_OPERATION_MODE == r_rmac_phy_get_operation_mode(p_instance_ctrl), + FSP_ERR_INVALID_MODE); + + /* Because reading the first time shows the previous state, the Link status bit is read twice. */ + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_STATUS, ®); + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_STATUS, ®); + + /* When the link isn't up, return error */ + if (RMAC_PHY_STATUS_LINK_UP != (reg & RMAC_PHY_STATUS_LINK_UP)) + { + /* Link is down */ + err = FSP_ERR_ETHER_PHY_ERROR_LINK; + } + else + { + /* Link is up */ + err = FSP_SUCCESS; + + /* Start verification for frame preemption. Send verify frame 3 times at the configured interval. */ + if (p_extend->frame_preemption_enable) + { + p_reg_rmac = (R_RMAC0_Type *) (R_RMAC0_BASE + (RMAC_REG_SIZE * p_instance_ctrl->phy_lsi_cfg_index)); + p_reg_rmac->MLVC |= + ((R_RMAC0_MLVC_LVT_Msk & ((uint32_t) ((p_extend->frame_preemption_verification_interval - 1) << + R_RMAC0_MLVC_LVT_Pos))) | + R_RMAC0_MLVC_PLV_Msk); + } + } + + return err; +} /* End of function R_RMAC_PHY_LinkStatusGet() */ + +/********************************************************************************************************************//** + * @brief Initialize Ethernet PHY device. Implements @ref ether_phy_api_t::chipInit. + * + * @retval FSP_SUCCESS PHY device initialized successfully. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block or configuration structure is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_TIMEOUT PHY-LSI Reset wait timeout. + * @retval FSP_ERR_INVALID_MODE Function is called when not in OPERATION mode. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_ChipInit (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + uint32_t reg = 0; + uint32_t count = 0; + +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + RMAC_PHY_ERROR_RETURN(NULL != p_cfg, FSP_ERR_INVALID_POINTER); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* ETHA IP should be OPERATION mode */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ETHA_OPERATION_MODE == r_rmac_phy_get_operation_mode(p_instance_ctrl), + FSP_ERR_INVALID_MODE); + + /* Set MII type configuration for this PHY LSI port. */ + r_rmac_phy_set_mii_type_configuration(p_instance_ctrl, p_instance_ctrl->phy_lsi_cfg_index); + + p_instance_ctrl->interface_status = RMAC_PHY_INTERFACE_STATUS_INITIALIZED; + + /* Reset PHY */ + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_CONTROL, RMAC_PHY_CONTROL_RESET); + + /* Reset completion waiting */ + do + { + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_CONTROL, ®); + count++; + } while ((reg & RMAC_PHY_CONTROL_RESET) && (count < p_cfg->phy_reset_wait_time)); + + if (count < p_cfg->phy_reset_wait_time) + { + rmac_phy_targets_initialize(p_instance_ctrl); + } + else + { + err = FSP_ERR_TIMEOUT; + } + + return err; +} /* End of function R_RMAC_PHY_ChipInit() */ + +/********************************************************************************************************************//** + * @brief Read data from register of PHY-LSI . Implements @ref ether_phy_api_t::read. + * + * @retval FSP_SUCCESS RMAC_PHY successfully read data. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block is NULL. + * @retval FSP_ERR_INVALID_POINTER Pointer to read buffer is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Address is not a valid size + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + * @retval FSP_ERR_INVALID_MODE Function is called when not in OPERATION mode. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_Read (ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data) +{ + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + uint32_t mpsm = 0; + rmac_phy_extended_cfg_t * p_extend; + +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + RMAC_PHY_ERROR_RETURN(NULL != p_data, FSP_ERR_INVALID_POINTER); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ADDRESS_SIZE >= reg_addr, FSP_ERR_INVALID_ARGUMENT); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + p_extend = (rmac_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + + /* Create configuration value to read phy register. */ + mpsm |= R_RMAC0_MPSM_POP_Msk & (RMAC_PHY_MDIO_OPCODE_READ << R_RMAC0_MPSM_POP_Pos); + mpsm |= R_RMAC0_MPSM_PDA_Msk & + ((uint32_t) p_extend->p_phy_lsi_cfg_list[p_instance_ctrl->phy_lsi_cfg_index]->address << + R_RMAC0_MPSM_PDA_Pos); + mpsm |= R_RMAC0_MPSM_PRA_Msk & (reg_addr << R_RMAC0_MPSM_PRA_Pos); + + /* Set configuration value. */ + p_instance_ctrl->p_reg_rmac->MPSM = mpsm; + + /* Start read access to the phy register and wait for completion. */ + p_instance_ctrl->p_reg_rmac->MPSM_b.PSME = 1; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg_rmac->MPSM_b.PSME, 0); + + /* Copy register value. */ + *p_data = p_instance_ctrl->p_reg_rmac->MPSM_b.PRD; + + return FSP_SUCCESS; +} /* End of function R_RMAC_PHY_Read() */ + +/********************************************************************************************************************//** + * @brief Write data to register of PHY-LSI . Implements @ref ether_phy_api_t::write. + * + * @retval FSP_SUCCESS RMAC_PHY successfully write data. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Address or data is not a valid size + * @retval FSP_ERR_NOT_INITIALIZED The control block has not been initialized + * @retval FSP_ERR_INVALID_MODE Function is called when not in OPERATION mode. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_Write (ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data) +{ + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + uint32_t mpsm = 0; + rmac_phy_extended_cfg_t * p_extend; + +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ADDRESS_SIZE >= reg_addr, FSP_ERR_INVALID_ARGUMENT); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_REGISTER_DATA_SIZE >= data, FSP_ERR_INVALID_ARGUMENT); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_INTERFACE_STATUS_INITIALIZED == p_instance_ctrl->interface_status, + FSP_ERR_NOT_INITIALIZED); +#endif + p_extend = (rmac_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + + /* ETHA IP should be OPERATION mode */ + RMAC_PHY_ERROR_RETURN(RMAC_PHY_ETHA_OPERATION_MODE == r_rmac_phy_get_operation_mode(p_instance_ctrl), + FSP_ERR_INVALID_MODE); + + /* Create configuration value to write phy register. */ + mpsm |= R_RMAC0_MPSM_POP_Msk & (RMAC_PHY_MDIO_OPCODE_WRITE << R_RMAC0_MPSM_POP_Pos); + mpsm |= R_RMAC0_MPSM_PDA_Msk & + ((uint32_t) p_extend->p_phy_lsi_cfg_list[p_instance_ctrl->phy_lsi_cfg_index]->address << + R_RMAC0_MPSM_PDA_Pos); + mpsm |= R_RMAC0_MPSM_PRA_Msk & (reg_addr << R_RMAC0_MPSM_PRA_Pos); + mpsm |= R_RMAC0_MPSM_PRD_Msk & (data << R_RMAC0_MPSM_PRD_Pos); + + /* Set configuration value. */ + p_instance_ctrl->p_reg_rmac->MPSM = mpsm; + + /* Start write access to the phy register and wait for completion. */ + p_instance_ctrl->p_reg_rmac->MPSM_b.PSME = 1; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg_rmac->MPSM_b.PSME, 0); + + return FSP_SUCCESS; +} /* End of function R_RMAC_PHY_Write() */ + +/********************************************************************************************************************//** + * @brief Update the target PHY LSI of this driver. + * + * @retval FSP_SUCCESS PHY device initialized successfully. + * @retval FSP_ERR_ASSERTION Pointer to RMAC_PHY control block or configuration structure is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid PHY LSI is selected. + ***********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_ChipSelect (ether_phy_ctrl_t * const p_ctrl, uint8_t port) +{ + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + rmac_phy_extended_cfg_t * p_extend; +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + RMAC_PHY_ERROR_RETURN(RMAC_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + RMAC_PHY_ERROR_RETURN(BSP_FEATURE_ETHER_NUM_CHANNELS > port, FSP_ERR_INVALID_ARGUMENT); +#endif + p_extend = (rmac_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + FSP_ERROR_RETURN(NULL != p_extend->p_phy_lsi_cfg_list[port], FSP_ERR_INVALID_ARGUMENT); + + /* Update the target PHY lSI. */ + p_instance_ctrl->phy_lsi_cfg_index = port; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref ether_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_RMAC_PHY_CallbackSet (ether_phy_ctrl_t * const p_ctrl, + void ( * p_callback)(ether_phy_callback_args_t *), + void * const p_context, + ether_phy_callback_args_t * const p_callback_memory) +{ + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) p_ctrl; + + /* Check argument */ +#if (RMAC_PHY_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(RMAC_PHY_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if RMAC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + ether_phy_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD && BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(ether_phy_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RMAC_PHY) + **********************************************************************************************************************/ + +/** + * Private functions + */ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_instance_ctrl - + * Ethernet control block + * Return Value : none + ***********************************************************************************************************************/ +static void rmac_phy_targets_initialize (rmac_phy_instance_ctrl_t * p_instance_ctrl) +{ + rmac_phy_extended_cfg_t * p_extend = (rmac_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + + switch (p_extend->p_phy_lsi_cfg_list[p_instance_ctrl->phy_lsi_cfg_index]->type) + { + /* Use KSZ8091RNB */ +#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) + case ETHER_PHY_LSI_TYPE_KSZ8091RNB: + { + rmac_phy_target_ksz8091rnb_initialize(p_instance_ctrl); + break; + } +#endif + + /* Use KSZ8041 */ +#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) + case ETHER_PHY_LSI_TYPE_KSZ8041: + { + rmac_phy_target_ksz8041_initialize(p_instance_ctrl); + break; + } +#endif + + /* Use DP83620 */ +#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) + case ETHER_PHY_LSI_TYPE_DP83620: + { + rmac_phy_target_dp83620_initialize(p_instance_ctrl); + break; + } +#endif + + /* Use ICS1894 */ +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + case ETHER_PHY_LSI_TYPE_ICS1894: + { + rmac_phy_target_ics1894_initialize(p_instance_ctrl); + break; + } +#endif + + /* Use GPY111 */ +#if (ETHER_PHY_CFG_TARGET_GPY111_ENABLE) + case ETHER_PHY_LSI_TYPE_GPY111: + { + rmac_phy_target_gpy111_initialize(p_instance_ctrl); + break; + } +#endif + + /* User custom */ +#if (ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE) + case ETHER_PHY_LSI_TYPE_CUSTOM: + { + if (NULL != p_instance_ctrl->p_ether_phy_cfg->p_extend) + { + rmac_phy_extended_cfg_t const * p_callback = p_instance_ctrl->p_ether_phy_cfg->p_extend; + if (NULL != p_callback->p_port_custom_init) + { + p_callback->p_port_custom_init(p_instance_ctrl); + } + } + + break; + } +#endif + + /* If module is configured for default LSI */ + default: + { + break; + } + } +} /* End of function rmac_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +static bool rmac_phy_targets_is_support_link_partner_ability (rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + rmac_phy_extended_cfg_t * p_extend = (rmac_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + bool result = false; + switch (p_extend->p_phy_lsi_cfg_list[p_instance_ctrl->phy_lsi_cfg_index]->type) + { + /* Use KSZ8091RNB */ +#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) + case ETHER_PHY_LSI_TYPE_KSZ8091RNB: + { + result = rmac_phy_target_ksz8091rnb_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* Use KSZ8041 */ +#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) + case ETHER_PHY_LSI_TYPE_KSZ8041: + { + result = rmac_phy_target_ksz8041_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* Use DP83620 */ +#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) + case ETHER_PHY_LSI_TYPE_DP83620: + { + result = rmac_phy_target_dp83620_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* Use ICS1894 */ +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + case ETHER_PHY_LSI_TYPE_ICS1894: + { + result = rmac_phy_target_ics1894_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* Use ICS1894 */ +#if (ETHER_PHY_CFG_TARGET_GPY111_ENABLE) + case ETHER_PHY_LSI_TYPE_GPY111: + { + result = rmac_phy_target_gpy111_is_support_link_partner_ability(p_instance_ctrl, line_speed_duplex); + break; + } +#endif + + /* User custom */ +#if (ETHER_PHY_CFG_USE_CUSTOM_PHY_LSI_ENABLE) + case ETHER_PHY_LSI_TYPE_CUSTOM: + { + if (NULL != p_instance_ctrl->p_ether_phy_cfg->p_extend) + { + rmac_phy_extended_cfg_t const * p_callback = p_instance_ctrl->p_ether_phy_cfg->p_extend; + if (NULL != p_callback->p_port_custom_link_partner_ability_get) + { + result = p_callback->p_port_custom_link_partner_ability_get(p_instance_ctrl, line_speed_duplex); + } + } + + break; + } +#endif + + /* If module is configured for default LSI, always return true */ + default: + { + result = true; + break; + } + } + + return result; +} /* End of function rmac_phy_targets_is_support_link_partner_ability() */ + +/*********************************************************************************************************************** + * Function Name: r_rmac_phy_calculate_mpic + * Description : Calculate MPIC register value. + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : uint32_t + ***********************************************************************************************************************/ +static uint32_t r_rmac_phy_calculate_mpic (rmac_phy_instance_ctrl_t * p_instance_ctrl, uint32_t line_speed_duplex) +{ + rmac_phy_extended_cfg_t * p_extend = (rmac_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + uint32_t mpic; + uint32_t mpic_psmcs; + uint32_t mpic_pis; + uint32_t mpic_lsc; + uint32_t eswclk_frequency; + + /*Get frequency of ESWCLK. */ + eswclk_frequency = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) (R_SYSTEM->ESWCKCR_b.CKSEL)) / + R_FSP_ClockDividerGet(R_SYSTEM->ESWCKDIVCR_b.CKDIV); + + /* Calculate cycle of MDC clock. */ + mpic_psmcs = ((eswclk_frequency / p_extend->mdc_clock_rate) / 2) - 1; + + /* Configure interface. */ + if ((ETHER_PHY_MII_TYPE_MII == p_instance_ctrl->p_ether_phy_cfg->mii_type) || + (ETHER_PHY_MII_TYPE_RMII == p_instance_ctrl->p_ether_phy_cfg->mii_type)) + { + /* MII, 100Mbps */ + mpic_pis = 0; + } + else + { + /* GMII, 1000Mbps */ + mpic_pis = 2; + } + + /* Configure link speed. */ + switch (line_speed_duplex) + { + case ETHER_PHY_LINK_SPEED_10H: + case ETHER_PHY_LINK_SPEED_10F: + { + mpic_lsc = 0; + break; + } + + case ETHER_PHY_LINK_SPEED_100H: + case ETHER_PHY_LINK_SPEED_100F: + { + mpic_lsc = 1; + break; + } + + case ETHER_PHY_LINK_SPEED_1000H: + case ETHER_PHY_LINK_SPEED_1000F: + { + mpic_lsc = 2; + break; + } + + default: + { + mpic_lsc = 0; + break; + } + } + + mpic = (R_RMAC0_MPIC_PSMCS_Msk & (mpic_psmcs << R_RMAC0_MPIC_PSMCS_Pos)) | + (R_RMAC0_MPIC_PIS_Msk & (mpic_pis << R_RMAC0_MPIC_PIS_Pos)) | + (R_RMAC0_MPIC_LSC_Msk & (mpic_lsc << R_RMAC0_MPIC_LSC_Pos)) | + (R_RMAC0_MPIC_PSMCT_Msk & ((uint32_t) p_extend->mdio_capture_time << R_RMAC0_MPIC_PSMCT_Pos)) | + (R_RMAC0_MPIC_PSMHT_Msk & ((uint32_t) p_extend->mdio_hold_time << R_RMAC0_MPIC_PSMHT_Pos)); + + return mpic; +} + +/*********************************************************************************************************************** + * Function Name: r_rmac_phy_get_operation_mode + * Description : Get operation mode of ETHA. + * Arguments : p_instance_ctrl - + * Ethernet control block + * Return Value : uint8_t + ***********************************************************************************************************************/ +static uint8_t r_rmac_phy_get_operation_mode (rmac_phy_instance_ctrl_t * p_instance_ctrl) +{ + R_ETHA0_Type * p_etha_reg = + (R_ETHA0_Type *) (R_ETHA0_BASE + (ETHA_REG_SIZE * p_instance_ctrl->p_ether_phy_cfg->channel)); + + /* Return operation mode of ETHA IP. */ + return p_etha_reg->EAMS_b.OPS; +} + +/*********************************************************************************************************************** + * Change operation mode of ETHA. + * + * @param[in] mode New operation mode + ***********************************************************************************************************************/ +static void r_rmac_phy_set_operation_mode (uint32_t channel, uint8_t mode) +{ + R_ETHA0_Type * p_etha_reg = + (R_ETHA0_Type *) (R_ETHA0_BASE + (ETHA_REG_SIZE * channel)); + + /* Mode transition */ + p_etha_reg->EAMC_b.OPC = R_ETHA0_EAMC_OPC_Msk & mode; + FSP_HARDWARE_REGISTER_WAIT(p_etha_reg->EAMS_b.OPS, mode); +} + +/*********************************************************************************************************************** + * Function Name: r_rmac_phy_set_mii_type_configuration + * Description : Set MII type configuration for the port. + * Arguments : p_instance_ctrl - + * Ethernet control block + * Return Value : uint32_t + ***********************************************************************************************************************/ +static void r_rmac_phy_set_mii_type_configuration (rmac_phy_instance_ctrl_t * p_instance_ctrl, uint8_t port) +{ + volatile uint32_t * p_miicr_register; + + /* Configure pins for MII or RMII. Set PHYMODE0 if MII is selected. */ + R_PMISC->PFENET = + (uint8_t) ((ETHER_PHY_MII_TYPE_MII == + p_instance_ctrl->p_ether_phy_cfg->mii_type) << (R_PMISC_PFENET_PHYMODE0_Pos + port)); + + /* Get pointer to a MIICRn register. */ + p_miicr_register = &(R_ESWM->MIICR0) + port; + + /* Configure ESWM as MII, RMII, or RGMII. */ + switch (p_instance_ctrl->p_ether_phy_cfg->mii_type) + { + case ETHER_PHY_MII_TYPE_RMII: + { + *p_miicr_register = 2; + break; + } + + case ETHER_PHY_MII_TYPE_RGMII: + { + *p_miicr_register = (R_ESWM_MIICR0_TXCIDE_Msk | 1); + + /* Enable TXC generation. */ + R_ESWM->MIIRR = R_ESWM->MIIRR | (1 << (R_ESWM_MIIRR_RGRST_Pos + port)); + break; + } + + default: + { + /* MII or GMII. */ + *p_miicr_register = 0; + break; + } + } +} + +/*********************************************************************************************************************** + * Interrupt handler for ETHA status interrupts that include frame preemption events. + ***********************************************************************************************************************/ +void rmac_phy_easi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + ether_phy_callback_args_t callback_arg; + uint8_t port = 0; + R_RMAC0_Type * p_reg_rmac; + uint32_t status_mmis0; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + rmac_phy_instance_ctrl_t * p_instance_ctrl = (rmac_phy_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + rmac_phy_extended_cfg_t * p_extend = (rmac_phy_extended_cfg_t *) p_instance_ctrl->p_ether_phy_cfg->p_extend; + + /* Find the port that this interrupt occurred. */ + for (uint8_t i = 0; i < BSP_FEATURE_ETHER_NUM_CHANNELS; i++) + { + if (p_extend->easi_irq[i] == irq) + { + port = i; + } + } + + p_reg_rmac = (R_RMAC0_Type *) (R_RMAC0_BASE + (RMAC_REG_SIZE * port)); + + /* Get the monitoring status register value, which contains the link verification status. */ + status_mmis0 = p_reg_rmac->MMIS0; + p_reg_rmac->MMIS0 = status_mmis0; + + /* Clear pending interrupt flag. */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + if (NULL != p_instance_ctrl->p_callback) + { + callback_arg.channel = p_instance_ctrl->p_ether_phy_cfg->channel; + callback_arg.port = port; + callback_arg.p_context = p_instance_ctrl->p_context; + + /* Timeout occurred while waiting for respond frame. */ + if (status_mmis0 & R_RMAC0_MMIS0_LVFS_Msk) + { + callback_arg.event = ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_FAIL; + p_instance_ctrl->p_callback(&callback_arg); + } + + /* Received verify frame. */ + if (status_mmis0 & R_RMAC0_MMIS0_VFRS_Msk) + { + callback_arg.event = ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_RECEIVE; + p_instance_ctrl->p_callback(&callback_arg); + } + + /* Received respond frame. Frame preemption verification is succeeded. */ + if (status_mmis0 & R_RMAC0_MMIS0_LVSS_Msk) + { + callback_arg.event = ETHER_PHY_EVENT_PREEMPTION_LINK_VERIFY_SUCCESS; + p_instance_ctrl->p_callback(&callback_arg); + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} /* End of function ether_eint_isr() */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/DP83620/r_rmac_phy_target_dp83620.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/DP83620/r_rmac_phy_target_dp83620.c new file mode 100644 index 0000000000..6e5e7295af --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/DP83620/r_rmac_phy_target_dp83620.c @@ -0,0 +1,94 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_rmac_phy.h" + +#if (ETHER_PHY_CFG_TARGET_DP83620_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define RMAC_PHY_REG_PAGE_SELECT (0x13) + #define RMAC_PHY_REG_14H (0x14) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void rmac_phy_target_dp83620_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +bool rmac_phy_target_dp83620_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_api_ctrl - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +void rmac_phy_target_dp83620_initialize (rmac_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + if (ETHER_PHY_MII_TYPE_RMII == p_instance_ctrl->p_ether_phy_cfg->mii_type) + { + /* + * The following is the recommended settings for TI to output 50 MHz from CLK_OUT when using Texas Instruments DP83620 + * in RMII master mode. + */ + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_PAGE_SELECT, 0x0006); + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_14H, ®); + if (0x800A == reg) + { + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_14H, 0x000A); + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_PAGE_SELECT, 0x0000); + } + } +} /* End of function rmac_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool rmac_phy_target_dp83620_is_support_link_partner_ability (rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(line_speed_duplex); + + /* This PHY-LSI supports half and full duplex mode. */ + return true; +} /* End of function rmac_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_DP83620_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/GPY111/r_rmac_phy_target_gpy111.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/GPY111/r_rmac_phy_target_gpy111.c new file mode 100644 index 0000000000..38c5e6ce12 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/GPY111/r_rmac_phy_target_gpy111.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_rmac_phy.h" + +#if (ETHER_PHY_CFG_TARGET_GPY111_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + #define RMAC_PHY_REG_MIICTRL (0x17U) + #define RMAC_PHY_REG_MIICTRL_RXSKEW_MASK (0x7000U) + #define RMAC_PHY_REG_MIICTRL_RXSKEW_VALUE_1NS (0x2000U) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void rmac_phy_target_gpy111_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +bool rmac_phy_target_gpy111_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_api_ctrl - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +void rmac_phy_target_gpy111_initialize (rmac_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + /* Set RGMII receive timing skew to 1.0 ns. */ + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_MIICTRL, ®); + reg = (reg & ~RMAC_PHY_REG_MIICTRL_RXSKEW_MASK) | RMAC_PHY_REG_MIICTRL_RXSKEW_VALUE_1NS; + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_MIICTRL, reg); +} /* End of function rmac_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool rmac_phy_target_gpy111_is_support_link_partner_ability (rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(line_speed_duplex); + + /* This PHY-LSI supports half and full duplex mode. */ + return true; +} /* End of function rmac_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_GPY111_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/ICS1894/r_rmac_phy_target_ics1894.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/ICS1894/r_rmac_phy_target_ics1894.c new file mode 100644 index 0000000000..d9b6c4447c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/ICS1894/r_rmac_phy_target_ics1894.c @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_rmac_phy.h" + +#if (ETHER_PHY_CFG_TARGET_ICS1894_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define RMAC_PHY_REG_PHY_CONTROL_20 (0x14) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void rmac_phy_target_ics1894_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +bool rmac_phy_target_ics1894_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_instance_ctrl - + * Ethernet control block + * Return Value : none + ***********************************************************************************************************************/ +void rmac_phy_target_ics1894_initialize (rmac_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + /* + * When ICS1894NL of the the Renesas Electronics Corporation. is used, + * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. + * The setting of the pin is changed so that only the state of LINK is output. + */ + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_PHY_CONTROL_20, ®); + reg |= 0x0007U; + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_PHY_CONTROL_20, reg); +} /* End of function rmac_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool rmac_phy_target_ics1894_is_support_link_partner_ability (rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + bool ret = false; + + /* This PHY-LSI only supports full duplex mode. */ + switch (line_speed_duplex) + { + /* 10Mbps full duplex */ + case ETHER_PHY_LINK_SPEED_10F: + { + ret = true; + break; + } + + /* 100Mbps full duplex */ + case ETHER_PHY_LINK_SPEED_100F: + { + ret = true; + break; + } + + /* Half duplex is not supported */ + default: + { + break; + } + } + + return ret; +} /* End of function rmac_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_ICS1894_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/KSZ8041/r_rmac_phy_target_ksz8041.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/KSZ8041/r_rmac_phy_target_ksz8041.c new file mode 100644 index 0000000000..6af8edaab7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/KSZ8041/r_rmac_phy_target_ksz8041.c @@ -0,0 +1,91 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_rmac_phy.h" + +#if (ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define RMAC_PHY_REG_PHY_CONTROL_1 (0x1E) + + #define ETHER_PHY_LED_MODE_LED0_LINK_LED1_ACTIVITY (0x4000U) + #define ETHER_PHY_LED_MODE_MASK (0xC000U) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void rmac_phy_target_ksz8041_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +bool rmac_phy_target_ksz8041_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_api_ctrl - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +void rmac_phy_target_ksz8041_initialize (rmac_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + /* + * When KSZ8041NL of the Micrel, Inc. is used, + * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. + * The setting of the pin is changed so that only the state of LINK is output. + */ + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_PHY_CONTROL_1, ®); + reg &= ~ETHER_PHY_LED_MODE_MASK; + reg |= ETHER_PHY_LED_MODE_LED0_LINK_LED1_ACTIVITY; + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_PHY_CONTROL_1, reg); +} /* End of function rmac_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool rmac_phy_target_ksz8041_is_support_link_partner_ability (rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(line_speed_duplex); + + /* This PHY-LSI supports half and full duplex mode. */ + return true; +} /* End of function rmac_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_KSZ8041_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c new file mode 100644 index 0000000000..810c4b831e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rmac_phy/targets/KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c @@ -0,0 +1,105 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ + +/* Access to peripherals and board defines. */ +#include "bsp_api.h" +#include "r_rmac_phy.h" + +#if (ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE) + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* Vendor Specific PHY Registers */ + #define RMAC_PHY_REG_INTERRUPT_CONTROL (0x1B) + #define RMAC_PHY_REG_PHY_CONTROL2 (0x1F) + + #define RMAC_PHY_REG_INTERRUPT_CONTROL_LUIE_OFFSET (0x8) + #define RMAC_PHY_REG_INTERRUPT_CONTROL_LDIE_OFFSET (0xA) + #define RMAC_PHY_REG_PHY_CONTROL2_RMII_RCS_OFFSET (0x7) + #define RMAC_PHY_REG_PHY_CONTROL2_RMII_IL_OFFSET (0x9) + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global function + ***********************************************************************************************************************/ +void rmac_phy_target_ksz8091rnb_initialize(rmac_phy_instance_ctrl_t * p_instance_ctrl); +bool rmac_phy_target_ksz8091rnb_is_support_link_partner_ability(rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex); + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_initialize + * Description : PHY-LSI specific initialization processing + * Arguments : p_api_ctrl - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +void rmac_phy_target_ksz8091rnb_initialize (rmac_phy_instance_ctrl_t * p_instance_ctrl) +{ + uint32_t reg; + + /* When KSZ8091RNB of the Micrel, Inc. is used. + * This processing is a setting to use Link -up and Link-down as a factor of INTPR. + * b10=1:Enable link-down interrupt + * b8=1 :Enable link-up interrupt + */ + R_RMAC_PHY_Write(p_instance_ctrl, + RMAC_PHY_REG_INTERRUPT_CONTROL, + (0x1 << RMAC_PHY_REG_INTERRUPT_CONTROL_LUIE_OFFSET | 0x1 << + RMAC_PHY_REG_INTERRUPT_CONTROL_LDIE_OFFSET)); + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_INTERRUPT_CONTROL, ®); + R_RMAC_PHY_Read(p_instance_ctrl, RMAC_PHY_REG_PHY_CONTROL2, ®); + + /* b7=1:RMII 50MHz clock mode; clock input to XI(pin 9) is 50MHz */ + #if (ETHER_PHY_CFG_USE_REF_CLK == 0) + reg |= (0x1 << RMAC_PHY_REG_PHY_CONTROL2_RMII_RCS_OFFSET); + #endif + + /* b9=0:Interrupt pin active low */ + reg &= (uint16_t) ~(0x1 << RMAC_PHY_REG_PHY_CONTROL2_RMII_IL_OFFSET); + R_RMAC_PHY_Write(p_instance_ctrl, RMAC_PHY_REG_PHY_CONTROL2, reg); +} /* End of function rmac_phy_targets_initialize() */ + +/*********************************************************************************************************************** + * Function Name: rmac_phy_targets_is_support_link_partner_ability + * Description : Check if the PHY-LSI connected Ethernet controller supports link ability + * Arguments : p_instance_ctrl - + * Ethernet control block + * line_speed_duplex - + * Line speed duplex of link partner PHY-LSI + * Return Value : bool + ***********************************************************************************************************************/ +bool rmac_phy_target_ksz8091rnb_is_support_link_partner_ability (rmac_phy_instance_ctrl_t * p_instance_ctrl, + uint32_t line_speed_duplex) +{ + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(line_speed_duplex); + + /* This PHY-LSI supports half and full duplex mode. */ + return true; +} /* End of function rmac_phy_targets_is_support_link_partner_ability() */ + +#endif /* ETHER_PHY_CFG_TARGET_KSZ8091RNB_ENABLE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/inc/api/r_rsip_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/inc/api/r_rsip_api.h new file mode 100644 index 0000000000..f3a26a38ad --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/inc/api/r_rsip_api.h @@ -0,0 +1,1296 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SECURITY_INTERFACES + * @defgroup RSIP_PROTECTED_API RSIP Interface + * @brief Interface for Renesas Secure IP (RSIP) functions. + * + * @section RSIP_PROTECTED_API_Summary Summary + * The RSIP interface provides RSIP functionality. + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_RSIP_API_H +#define R_RSIP_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Internal macro (calculation of key type values) */ +#define RSIP_PRV_KEY_TYPE_VAL(plain_words, alg, subtype) (((alg) << 24) | ((subtype) << 16) | (plain_words)) +#define RSIP_PRV_KEY_TYPE_VAL_ALG(key_type_val) ((uint8_t) \ + (((uint32_t) (key_type_val) & 0xff000000U) >> 24)) +#define RSIP_PRV_KEY_TYPE_VAL_SUBTYPE(key_type_val) ((uint8_t) \ + (((uint32_t) (key_type_val) & 0x00ff0000U) >> 16)) +#define RSIP_PRV_KEY_TYPE_VAL_PLAIN_WORDS(key_type_val) (((uint32_t) (key_type_val) & 0x0000ffffU) >> 0) + +/* Internal algorithm ID */ +#define RSIP_PRV_ALG_INVALID (0x00) +#define RSIP_PRV_ALG_AES (0x01) +#define RSIP_PRV_ALG_XTS_AES (0x02) +#define RSIP_PRV_ALG_CHACHA (0x03) +#define RSIP_PRV_ALG_ECC_PUBLIC (0x04) +#define RSIP_PRV_ALG_ECC_PRIVATE (0x05) +#define RSIP_PRV_ALG_RSA_PUBLIC (0x06) +#define RSIP_PRV_ALG_RSA_PRIVATE (0x07) +#define RSIP_PRV_ALG_HMAC (0x08) +#define RSIP_PRV_ALG_KDF_HMAC (0x09) +#define RSIP_PRV_ALG_MISC (0xff) + +/* Internal key subtype ID */ +#define RSIP_PRV_KEY_SUBTYPE_INVALID (0x0) +#define RSIP_PRV_KEY_SUBTYPE_AES_128 (0x0) +#define RSIP_PRV_KEY_SUBTYPE_AES_192 (0x1) +#define RSIP_PRV_KEY_SUBTYPE_AES_256 (0x2) +#define RSIP_PRV_KEY_SUBTYPE_AES_NUM (0x3) +#define RSIP_PRV_KEY_SUBTYPE_CHACHA_CHACHA20 (0x0) +#define RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM (0x1) +#define RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1 (0x0) +#define RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1 (0x1) +#define RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1 (0x2) +#define RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1 (0x3) +#define RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1 (0x4) +#define RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1 (0x5) +#define RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1 (0x6) +#define RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519 (0x7) +#define RSIP_PRV_KEY_SUBTYPE_ECC_NUM (0x8) +#define RSIP_PRV_KEY_SUBTYPE_RSA_1024 (0x0) +#define RSIP_PRV_KEY_SUBTYPE_RSA_2048 (0x1) +#define RSIP_PRV_KEY_SUBTYPE_RSA_3072 (0x2) +#define RSIP_PRV_KEY_SUBTYPE_RSA_4096 (0x3) +#define RSIP_PRV_KEY_SUBTYPE_RSA_NUM (0x4) +#define RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1 (0x0) +#define RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 (0x1) +#define RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 (0x2) +#define RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384 (0x3) +#define RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512 (0x4) +#define RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_224 (0x5) +#define RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_256 (0x6) +#define RSIP_PRV_KEY_SUBTYPE_HMAC_NUM (0x7) +#define RSIP_PRV_KEY_SUBTYPE_MISC_KUK (0x0) +#define RSIP_PRV_KEY_SUBTYPE_MISC_NUM (0x1) + +/* Internal DKM algorithm ID */ +#define RSIP_PRV_DKM_ALG_INVALID (0x0) +#define RSIP_PRV_DKM_ALG_SHA (0x1) +#define RSIP_PRV_DKM_ALG_HMAC (0x2) + +/* Internal DKM subtype ID */ +#define RSIP_PRV_DKM_SUBTYPE_INVALID (0x0) +#define RSIP_PRV_DKM_SUBTYPE_SHA_256 (0x0) +#define RSIP_PRV_DKM_SUBTYPE_SHA_384 (0x1) +#define RSIP_PRV_DKM_SUBTYPE_SHA_NUM (0x2) +#define RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256 (0x0) +#define RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384 (0x1) +#define RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512 (0x2) +#define RSIP_PRV_DKM_SUBTYPE_HMAC_NUM (0x3) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Key types */ +typedef enum e_rsip_key_type +{ + RSIP_KEY_TYPE_INVALID = + RSIP_PRV_KEY_TYPE_VAL(0, RSIP_PRV_ALG_INVALID, RSIP_PRV_KEY_SUBTYPE_INVALID), ///< Invalid key + RSIP_KEY_TYPE_AES_128 = + RSIP_PRV_KEY_TYPE_VAL(4, RSIP_PRV_ALG_AES, RSIP_PRV_KEY_SUBTYPE_AES_128), ///< AES-128 + RSIP_KEY_TYPE_AES_192 = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_AES, RSIP_PRV_KEY_SUBTYPE_AES_192), ///< AES-192 + RSIP_KEY_TYPE_AES_256 = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_AES, RSIP_PRV_KEY_SUBTYPE_AES_256), ///< AES-256 + RSIP_KEY_TYPE_XTS_AES_128 = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_XTS_AES, RSIP_PRV_KEY_SUBTYPE_AES_128), ///< XTS-AES-128 + RSIP_KEY_TYPE_XTS_AES_256 = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_XTS_AES, RSIP_PRV_KEY_SUBTYPE_AES_256), ///< XTS-AES-256 + RSIP_KEY_TYPE_CHACHA20 = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_CHACHA, RSIP_PRV_KEY_SUBTYPE_CHACHA_CHACHA20), ///< ChaCha20 + RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_ECC_PUBLIC, RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1), ///< secp256r1 public key (also known as NIST P-256, prime256v1) + RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(24, RSIP_PRV_ALG_ECC_PUBLIC, RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1), ///< secp384r1 public key (also known as NIST P-384) + RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(40, RSIP_PRV_ALG_ECC_PUBLIC, RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1), ///< secp521r1 public key (also known as NIST P-521) + RSIP_KEY_TYPE_ECC_SECP256K1_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_ECC_PUBLIC, RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1), ///< secp256k1 public key + RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_ECC_PUBLIC, RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1), ///< brainpoolP256r1 public key + RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(24, RSIP_PRV_ALG_ECC_PUBLIC, RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1), ///< brainpoolP384r1 public key + RSIP_KEY_TYPE_ECC_BRAINPOOLP512R1_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(32, RSIP_PRV_ALG_ECC_PUBLIC, RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1), ///< brainpoolP512r1 public key + RSIP_KEY_TYPE_ECC_EDWARDS25519_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_ECC_PUBLIC, RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519), ///< edwards25519 public key + RSIP_KEY_TYPE_ECC_SECP256R1_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_ECC_PRIVATE, RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1), ///< secp256r1 private key (also known as NIST P-256, prime256v1) + RSIP_KEY_TYPE_ECC_SECP384R1_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(12, RSIP_PRV_ALG_ECC_PRIVATE, RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1), ///< secp384r1 private key (also known as NIST P-384) + RSIP_KEY_TYPE_ECC_SECP521R1_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(20, RSIP_PRV_ALG_ECC_PRIVATE, RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1), ///< secp521r1 private key (also known as NIST P-521) + RSIP_KEY_TYPE_ECC_SECP256K1_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_ECC_PRIVATE, RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1), ///< secp256k1 private key + RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_ECC_PRIVATE, RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1), ///< brainpoolP256r1 private key + RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(12, RSIP_PRV_ALG_ECC_PRIVATE, RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1), ///< brainpoolP384r1 private key + RSIP_KEY_TYPE_ECC_BRAINPOOLP512R1_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_ECC_PRIVATE, RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1), ///< brainpoolP512r1 private key + RSIP_KEY_TYPE_ECC_EDWARDS25519_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_ECC_PRIVATE, RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519), ///< edwards25519 private key + RSIP_KEY_TYPE_RSA_1024_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(36, RSIP_PRV_ALG_RSA_PUBLIC, RSIP_PRV_KEY_SUBTYPE_RSA_1024), ///< RSA-1024 public key + RSIP_KEY_TYPE_RSA_2048_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(68, RSIP_PRV_ALG_RSA_PUBLIC, RSIP_PRV_KEY_SUBTYPE_RSA_2048), ///< RSA-2048 public key + RSIP_KEY_TYPE_RSA_3072_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(100, RSIP_PRV_ALG_RSA_PUBLIC, RSIP_PRV_KEY_SUBTYPE_RSA_3072), ///< RSA-3072 public key + RSIP_KEY_TYPE_RSA_4096_PUBLIC = + RSIP_PRV_KEY_TYPE_VAL(132, RSIP_PRV_ALG_RSA_PUBLIC, RSIP_PRV_KEY_SUBTYPE_RSA_4096), ///< RSA-4096 public key + RSIP_KEY_TYPE_RSA_1024_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(64, RSIP_PRV_ALG_RSA_PRIVATE, RSIP_PRV_KEY_SUBTYPE_RSA_1024), ///< RSA-1024 private key + RSIP_KEY_TYPE_RSA_2048_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(128, RSIP_PRV_ALG_RSA_PRIVATE, RSIP_PRV_KEY_SUBTYPE_RSA_2048), ///< RSA-2048 private key + RSIP_KEY_TYPE_RSA_3072_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(192, RSIP_PRV_ALG_RSA_PRIVATE, RSIP_PRV_KEY_SUBTYPE_RSA_3072), ///< RSA-3072 private key + RSIP_KEY_TYPE_RSA_4096_PRIVATE = + RSIP_PRV_KEY_TYPE_VAL(256, RSIP_PRV_ALG_RSA_PRIVATE, RSIP_PRV_KEY_SUBTYPE_RSA_4096), ///< RSA-4096 private key + RSIP_KEY_TYPE_HMAC_SHA1 = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1), ///< HMAC-SHA1 + RSIP_KEY_TYPE_HMAC_SHA224 = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224), ///< HMAC-SHA224 + RSIP_KEY_TYPE_HMAC_SHA256 = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256), ///< HMAC-SHA256 + RSIP_KEY_TYPE_HMAC_SHA384 = + RSIP_PRV_KEY_TYPE_VAL(12, RSIP_PRV_ALG_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384), ///< HMAC-SHA384 + RSIP_KEY_TYPE_HMAC_SHA512 = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512), ///< HMAC-SHA512 + RSIP_KEY_TYPE_HMAC_SHA512_224 = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_224), ///< HMAC-SHA512/224 + RSIP_KEY_TYPE_HMAC_SHA512_256 = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_256), ///< HMAC-SHA512/256 + RSIP_KEY_TYPE_KDF_HMAC_SHA256 = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_KDF_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256), ///< HMAC-SHA256 + RSIP_KEY_TYPE_KDF_HMAC_SHA384 = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_KDF_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384), ///< HMAC-SHA384 + RSIP_KEY_TYPE_KDF_HMAC_SHA512 = + RSIP_PRV_KEY_TYPE_VAL(16, RSIP_PRV_ALG_KDF_HMAC, RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512), ///< HMAC-SHA512 + RSIP_KEY_TYPE_KUK = + RSIP_PRV_KEY_TYPE_VAL(8, RSIP_PRV_ALG_MISC, RSIP_PRV_KEY_SUBTYPE_MISC_KUK), ///< Key Update Key (KUK) +} rsip_key_type_t; + +/** Block cipher modes of operation for AES */ +typedef enum e_rsip_aes_cipher_mode +{ + RSIP_AES_CIPHER_MODE_ECB_ENC, ///< Electronic Codebook (ECB) mode encryption + RSIP_AES_CIPHER_MODE_ECB_DEC, ///< Electronic Codebook (ECB) mode decryption + RSIP_AES_CIPHER_MODE_CBC_ENC, ///< Cipher Block Chaining (CBC) mode encryption + RSIP_AES_CIPHER_MODE_CBC_DEC, ///< Cipher Block Chaining (CBC) mode decryption + RSIP_AES_CIPHER_MODE_CTR, ///< Counter (CTR) mode encryption or decryption + RSIP_AES_CIPHER_MODE_XTS_ENC, ///< XEX-based tweaked-codebook mode with ciphertext stealing (XTS) encryption + RSIP_AES_CIPHER_MODE_XTS_DEC, ///< XEX-based tweaked-codebook mode with ciphertext stealing (XTS) decryption + + RSIP_AES_CIPHER_MODE_CBC_ENC_WRAPPED_IV, ///< Cipher Block Chaining (CBC) mode encryption with wrapped IV + RSIP_AES_CIPHER_MODE_CBC_DEC_WRAPPED_IV, ///< Cipher Block Chaining (CBC) mode decryption with wrapped IV +} rsip_aes_cipher_mode_t; + +/** AEAD modes of operation for AES */ +typedef enum e_rsip_aes_aead_mode +{ + RSIP_AES_AEAD_MODE_GCM_ENC, ///< Galois/Counter Mode (GCM) encryption + RSIP_AES_AEAD_MODE_GCM_DEC, ///< Galois/Counter Mode (GCM) decryption + RSIP_AES_AEAD_MODE_CCM_ENC, ///< Counter with CBC-MAC (CCM) encryption + RSIP_AES_AEAD_MODE_CCM_DEC, ///< Counter with CBC-MAC (CCM) decryption + + RSIP_AES_AEAD_MODE_GCM_ENC_WRAPPED_IV, ///< Galois/Counter Mode (GCM) encryption with wrapped IV + RSIP_AES_AEAD_MODE_GCM_DEC_WRAPPED_IV, ///< Galois/Counter Mode (GCM) decryption with wrapped IV +} rsip_aes_aead_mode_t; + +/** ChaCha20-Poly1305 mode */ +typedef enum e_rsip_chacha_poly_mode +{ + RSIP_CHACHA20_POLY1305_MODE_ENC, ///< ChaCha20-Poly1305 encryption + RSIP_CHACHA20_POLY1305_MODE_DEC, ///< ChaCha20-Poly1305 decryption +} rsip_chacha_poly_mode_t; + +/** MAC modes of operation for AES */ +typedef enum e_rsip_aes_mac_mode +{ + RSIP_AES_MAC_MODE_CMAC, ///< Cipher-based MAC (CMAC) +} rsip_aes_mac_mode_t; + +/** Hash type */ +typedef enum e_rsip_hash_type +{ + RSIP_HASH_TYPE_SHA1, ///< SHA-1 + RSIP_HASH_TYPE_SHA224, ///< SHA-224 + RSIP_HASH_TYPE_SHA256, ///< SHA-256 + RSIP_HASH_TYPE_SHA384, ///< SHA-384 + RSIP_HASH_TYPE_SHA512, ///< SHA-512 + RSIP_HASH_TYPE_SHA512_224, ///< SHA-512/224 + RSIP_HASH_TYPE_SHA512_256, ///< SHA-512/256 + RSIP_HASH_TYPE_SHA3_224, ///< SHA3-224 + RSIP_HASH_TYPE_SHA3_256, ///< SHA3-256 + RSIP_HASH_TYPE_SHA3_384, ///< SHA3-384 + RSIP_HASH_TYPE_SHA3_512, ///< SHA3-512 + + RSIP_HASH_TYPE_NUM // Number of hash types +} rsip_hash_type_t; + +/** MGF type */ +typedef enum e_rsip_mgf_type +{ + RSIP_MGF_TYPE_MGF1_SHA1 = RSIP_HASH_TYPE_SHA1, ///< MGF1 with SHA-1 + RSIP_MGF_TYPE_MGF1_SHA224 = RSIP_HASH_TYPE_SHA224, ///< MGF1 with SHA-224 + RSIP_MGF_TYPE_MGF1_SHA256 = RSIP_HASH_TYPE_SHA256, ///< MGF1 with SHA-256 + RSIP_MGF_TYPE_MGF1_SHA384 = RSIP_HASH_TYPE_SHA384, ///< MGF1 with SHA-384 + RSIP_MGF_TYPE_MGF1_SHA512 = RSIP_HASH_TYPE_SHA512, ///< MGF1 with SHA-512 + RSIP_MGF_TYPE_MGF1_SHA512_224 = RSIP_HASH_TYPE_SHA512_224, ///< MGF1 with SHA-512/224 + RSIP_MGF_TYPE_MGF1_SHA512_256 = RSIP_HASH_TYPE_SHA512_256 ///< MGF1 with SHA-512/256 +} rsip_mgf_type_t; + +/** RSA salt length */ +typedef enum e_rsip_rsa_salt_length +{ + RSIP_RSA_SALT_LENGTH_AUTO = 0xFFFFFFFFU, ///< When signing, the salt length is set to @ref RSIP_RSA_SALT_LENGTH_MAX or @ref RSIP_RSA_SALT_LENGTH_HASH, whichever is shorter. When verifying, the salt length is detected automatically. + RSIP_RSA_SALT_LENGTH_HASH = 0xFFFFFFFEU, ///< The salt length is set to the hash length. + RSIP_RSA_SALT_LENGTH_MAX = 0xFFFFFFFDU, ///< The salt length is set to emLen - hLen - 2, where emLen is the same as the key length and hLen is the hash length. +} rsip_rsa_salt_length_t; + +/* State that specifies functions that can be called next. This enum is private. */ +typedef enum e_rsip_user_handle_state +{ + RSIP_USER_HANDLE_STATE_INIT, // Init function can be called. + RSIP_USER_HANDLE_STATE_RESUME, // Resume + RSIP_USER_HANDLE_STATE_UPDATE // Update +} rsip_user_handle_state_t; + +/** IV data types */ +typedef enum e_rsip_initial_vector_type +{ + RSIP_INITIAL_VECTOR_TYPE_AES_16_BYTE, ///< Wrapped AES initial vector (unprocessed) + RSIP_INITIAL_VECTOR_TYPE_AES_TLS12_AEAD, ///< Wrapped AES nonce (TLS1.2 AES AEAD) + RSIP_INITIAL_VECTOR_TYPE_AES_TLS13_AEAD, ///< Wrapped AES nonce (TLS1.3 AES AEAD) +} rsip_initial_vector_type_t; + +/** Channel number of on-the-fly decryption/encryption module. */ +typedef enum e_rsip_otf_channel +{ + RSIP_OTF_CHANNEL_0, ///< Channel 0 + RSIP_OTF_CHANNEL_1, ///< Channel 1 + RSIP_OTF_CHANNEL_2, ///< Channel 2 + RSIP_OTF_CHANNEL_NUM // Number of channels +} rsip_otf_channel_t; + +/** Wrapped key structure for all supported algorithms. */ +typedef struct st_rsip_wrapped_key +{ + rsip_key_type_t type; ///< Key type + void * p_value; ///< Key value +} rsip_wrapped_key_t; + +/** Wrapped Derived Keying Material (DKM) structure for KDF APIs. */ +typedef struct st_rsip_wrapped_dkm +{ + uint8_t alg; // Internal algorithm ID + uint8_t subtype; // Internal key type ID + uint8_t info[2]; // Reserved area + uint32_t block_length; // DKM block length + uint32_t blocks; // Number of DKM blocks + + uint8_t value[]; // Variable length array to store the data value +} rsip_wrapped_dkm_t; + +/** Allocate an instance specific handle to pass into the API calls. */ +typedef void rsip_sha_handle_abstractor_t; + +/** Allocate an instance specific handle to pass into the API calls. */ +typedef void rsip_hmac_handle_abstractor_t; + +/** Allocate an instance specific handle to pass into the API calls. */ +typedef void rsip_kdf_sha_handle_abstractor_t; + +/** Allocate an instance specific handle to pass into the API calls. */ +typedef void rsip_kdf_hmac_handle_abstractor_t; + +/** Allocate an instance specific handle to pass into the API calls. */ +typedef void rsip_wrapped_secret_abstractor_t; + +/** Allocate an instance specific handle to pass into the API calls. */ +typedef void rsip_verified_cert_info_abstractor_t; + +/** RSIP Control block. Allocate an instance specific control block to pass into the API calls. */ +typedef void rsip_ctrl_t; + +/** User configuration structure, used in open function */ +typedef struct st_rsip_cfg +{ + void const * p_extend; ///< Hardware-dependent configuration +} rsip_cfg_t; + +/** RSIP driver structure. General RSIP functions implemented at the HAL layer follow this API. */ +typedef struct st_rsip_api +{ + /** + * Enables use of Renesas Secure IP functionality. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(rsip_ctrl_t * const p_ctrl, rsip_cfg_t const * const p_cfg); + + /** + * Disables use of Renesas Secure IP functionality. + * + * @param[in,out] p_ctrl Pointer to control block. + */ + fsp_err_t (* close)(rsip_ctrl_t * const p_ctrl); + + /** + * Generates a 128-bit random number. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_random 128bit random numbers. + */ + fsp_err_t (* randomNumberGenerate)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_random); + + /** + * Generate a wrapped symmetric key from a random number. + * In this API, user key input is unnecessary. + * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in,out] p_wrapped_key Pointer to destination of wrapped key. The length depends on key type. Refer "Key Size Table". + */ + fsp_err_t (* keyGenerate)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t * const p_wrapped_key); + + /** + * Generate a wrapped asymmetric key pair from a random number. In this API, user key input is unnecessary. + * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in,out] p_wrapped_public_key Key index for Public Key. The length depends on the key type. Refer "Key Size Table". + * @param[in,out] p_wrapped_private_key Key index for Private Key. The length depends on the key type. Refer "Key Size Table". + */ + fsp_err_t (* keyPairGenerate)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t * const p_wrapped_public_key, + rsip_wrapped_key_t * const p_wrapped_private_key); + + /** + * Decrypt the encrypted user key with Key Update Key (KUK) and wrap it with the Hardware Unique Key (HUK). + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_key_update_key Pointer to Key Update Key. + * @param[in] p_initial_vector Initialization vector when generating encrypted_key. + * The length is 16 bytes. + * @param[in] p_encrypted_key Encrypted user key. The length depends on the key type. Refer "Key Size Table". + * @param[in,out] p_wrapped_key Pointer to destination of wrapped key. The length depends on key type. Refer "Key Size Table". + */ + fsp_err_t (* encryptedKeyWrap)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_key_update_key, + void const * const p_initial_vector, void const * const p_encrypted_key, + rsip_wrapped_key_t * const p_wrapped_key); + + /** + * This function provides Key Wrap algorithm compliant with RFC3394. + * Using p_wrapped_kek to wrap p_wrapped_target_key, and output the result to p_rfc3394_wrapped_target_key. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_kek Pointer to wrapped key-encryption-key used to RFC3394-wrap the target key. + * @param[in] p_wrapped_target_key Pointer to wrapped target key to be RFC3394-wrapped. + * @param[out] p_rfc3394_wrapped_target_key Pointer to destination of RFC3394-wrapped target key. + */ + fsp_err_t (* rfc3394_KeyWrap)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_kek, + rsip_wrapped_key_t const * const p_wrapped_target_key, + uint8_t * const p_rfc3394_wrapped_target_key); + + /** + * This function provides Key Unwrap algorithm compliant with RFC3394. + * Using p_wrapped_kek to unwrap p_rfc3394_wrapped_target_key, and output the result to p_wrapped_target_key. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_kek Pointer to wrapped key-encryption-key used to RFC3394-unwrap the target key. + * @param[in] p_rfc3394_wrapped_target_key Pointer to AES-wrapped target key to be RFC3394-unwrapped. + * @param[in,out] p_wrapped_target_key Pointer to destination of RFC3394-unwrapped target key. + */ + fsp_err_t (* rfc3394_KeyUnwrap)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_kek, + uint8_t const * const p_rfc3394_wrapped_target_key, + rsip_wrapped_key_t * const p_wrapped_target_key); + + /** + * Exports public key parameters from a wrapped key. + * + * @param[in] p_wrapped_public_key Key index for Public Key. The length depends on the key type. Refer "Key Size Table". + * @param[out] p_raw_public_key Pointer to destination of raw public key. The length depends on the key length. + */ + fsp_err_t (* publicKeyExport)(rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t * const p_raw_public_key); + + /** + * Set parameters of AES cipher. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] mode Block cipher modes of operation for AES. + * @param[in] p_wrapped_key Pointer to wrapped key of AES or XTS-AES key. + * @param[in] p_initial_vector Pointer to initialization vector (IV) or nonce. The length is 16 bytes. + * @arg [ECB] Not required + * @arg [CBC][XTS] IV + * @arg [CTR] Nonce + */ + fsp_err_t (* aesCipherInit)(rsip_ctrl_t * const p_ctrl, rsip_aes_cipher_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key, uint8_t const * const p_initial_vector); + + /** + * Encrypt plaintext. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_input Pointer to input text. The length is given as the argument. + * @param[out] p_output Pointer to destination of output text. The length is given as the argument. + * @param[in] length Byte length of input and output. + * @arg [ECB][CBC][CTR] Must be 0 or a multiple of 16. + * @arg [XTS] Must be 0 or greater than or equal to 16. + * After an integer not divisible by 16 is input, update can no longer be executed. + */ + fsp_err_t (* aesCipherUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_input, uint8_t * const p_output, + uint32_t const length); + + /** + * Finalize AES operation. + * + * @param[in,out] p_ctrl Pointer to control block. + */ + fsp_err_t (* aesCipherFinish)(rsip_ctrl_t * const p_ctrl); + + /** + * Prepares an AES-AEAD function. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] mode AEAD mode of operation. + * @param[in] p_wrapped_key Pointer to wrapped key of AES key. + * @param[in] p_nonce Pointer to nonce. The length is nonce_length. + * @param[in] nonce_length Byte length of nonce. Input 1 or more. + */ + fsp_err_t (* aesAeadInit)(rsip_ctrl_t * const p_ctrl, rsip_aes_aead_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key, uint8_t const * const p_nonce, + uint32_t const nonce_length); + + /** + * Set text and tag lengths for specific mode. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] total_aad_length Total AAD length. + * @param[in] total_text_length Total input and output text length. + * @param[in] tag_length Input or output tag length. + */ + fsp_err_t (* aesAeadLengthsSet)(rsip_ctrl_t * const p_ctrl, uint32_t const total_aad_length, + uint32_t const total_text_length, uint32_t const tag_length); + + /** + * Inputs additional authentication data. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_aad Additional authentication data. The length depends on aad_length. + * @param[in] aad_length Byte length of additional authentication data (0 or more bytes). + * After starting input of plaintext, this value must always be 0. + */ + fsp_err_t (* aesAeadAadUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_aad, uint32_t const aad_length); + + /** + * Inputs test and executes encryption and decryption. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_input Pointer to input text. The length is input_length. + * @param[in] input_length Byte length of input text (0 or more bytes). + * @param[out] p_output Pointer to destination of output text. The length is p_output_length. + * @param[out] p_output_length Pointer to destination of output text length. + */ + fsp_err_t (* aesAeadUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_input, uint32_t const input_length, + uint8_t * const p_output, uint32_t * const p_output_length); + + /** + * Finalizes an AES-GCM encryption. + * + * If there is 16-byte fractional data indicated by the total data length of the value of p_plain that was input by + * R_RSIP_AES_GCM_EncryptUpdate(), this API will output the result of encrypting that fractional data to p_cipher. + * Here, the portion that does not reach 16 bytes will be padded with zeros. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of output text. The fractional block is output. + * @param[out] p_output_length Pointer to destination of output text length. + * @param[out] p_tag Pointer to destination of tag for authentication. + * GCM : The length is 16 bytes. + * *If a different tag length is required, truncate the 16-byte tag + * to the required tag length (NIST SP800-38D 7.1). + * CCM : The length is the value set by the API R_RSIP_AES_AEAD_LengthsSet(). + */ + fsp_err_t (* aesAeadFinish)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_output, uint32_t * const p_output_length, + uint8_t * const p_tag); + + /** + * Finalizes an AES-GCM decryption. + * + * If there is 16-byte fractional data indicated by the total data length of the value of p_cipher that was input by + * R_RSIP_AES_GCM_DecryptUpdate(), this API will output the result of decrypting that fractional data to p_cipher. + * Here, the portion that does not reach 16 bytes will be padded with zeros. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of decrypted data. + * @param[out] p_output_length Pointer to destination of decrypted data length. + * @param[in] p_tag Pointer to destination of tag for authentication. The length depends on tag_length. + * @param[in] tag_length Byte length of tag. Must be 1 to 16. + */ + fsp_err_t (* aesAeadVerify)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_output, uint32_t * const p_output_length, + uint8_t const * const p_tag, uint32_t const tag_length); + + /** + * Prepares an AES-MAC generation and verification. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] mode MAC mode of operation + * @param[in] p_wrapped_key Pointer to wrapped key of AES key. + */ + fsp_err_t (* aesMacInit)(rsip_ctrl_t * const p_ctrl, rsip_aes_mac_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key); + + /** + * Input message. + * Inside this function, the data that is input by the user is buffered until the input value of p_message exceeds 16 bytes. + * If the input value, p_message, is not a multiple of 16 bytes, it will be padded within the function. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + */ + fsp_err_t (* aesMacUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, + uint32_t const message_length); + + /** + * Finalizes an AES-CMAC generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_mac Pointer to destination of MAC. The length is 16 bytes. + */ + fsp_err_t (* aesMacSignFinish)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_mac); + + /** Finalizes an AES-CMAC verification. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. Must be 2 to 16. + */ + fsp_err_t (* aesMacVerifyFinish)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_mac, + uint32_t const mac_length); + + /** + * Prepares a ChaCha20 function. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_key Pointer to wrapped key of ChaCha20 key. + * @param[in] p_nonce Pointer to nonce. The length is 12 bytes. + * @param[in] counter 32-bit initial counter. This is usually zero. + */ + fsp_err_t (* chacha20Init)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_nonce, uint32_t const counter); + + /** + * Encrypts plaintext or decrypts ciphertext. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_input Pointer to input text. The length is input_length. + * @param[in] input_length Byte length of input text (0 or more bytes). + * @param[out] p_output Pointer to destination of output text. The length is p_output_length. + * @param[out] p_output_length Pointer to destination of output text length. + */ + fsp_err_t (* chacha20Update)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_input, uint32_t const input_length, + uint8_t * const p_output, uint32_t * const p_output_length); + + /** + * Finalize ChaCha20 operation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of output text. The fractional block is output. + * @param[out] p_output_length Pointer to destination of output text length. + */ + fsp_err_t (* chacha20Finish)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_output, + uint32_t * const p_output_length); + + /** + * Prepares a ChaCha20-Poly1305 function. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] mode AEAD mode of operation. + * @param[in] p_wrapped_key Pointer to wrapped key of AES key. + * @param[in] p_nonce Pointer to nonce. The length is nonce_length. + * @param[in] nonce_length Byte length of nonce. Input 1 or more. + */ + fsp_err_t (* chacha20Poly1305Init)(rsip_ctrl_t * const p_ctrl, rsip_chacha_poly_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key, uint8_t const * const p_nonce, + uint32_t const nonce_length); + + /** + * Inputs Additional Authentication Data (AAD). + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_aad Additional authentication data. The length depends on aad_length. + * @param[in] aad_length Byte length of additional authentication data (0 or more bytes). + * After starting input of plaintext, this value must always be 0. + */ + fsp_err_t (* chacha20Poly1305AadUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_aad, + uint32_t const aad_length); + + /** + * Encrypts plaintext or decrypts ciphertext. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_input Pointer to input text. The length is input_length. + * @param[in] input_length Byte length of input text (0 or more bytes). + * @param[out] p_output Pointer to destination of output text. The length is p_output_length. + * @param[out] p_output_length Pointer to destination of output text length. + */ + fsp_err_t (* chacha20Poly1305Update)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_input, + uint32_t const input_length, uint8_t * const p_output, + uint32_t * const p_output_length); + + /** + * Finalizes a ChaCha20-Poly1305 encryption. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of output text. The fractional block is output. + * @param[out] p_output_length Pointer to destination of output text length. + * @param[out] p_tag Pointer to destination of tag for authentication. The length is 16 bytes. + */ + fsp_err_t (* chacha20Poly1305Finish)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_output, + uint32_t * const p_output_length, uint8_t * const p_tag); + + /** + * Finalizes a ChaCha20-Poly1305 decryption. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of decrypted data. + * @param[out] p_output_length Pointer to destination of decrypted data length. + * @param[in] p_tag Pointer to destination of tag for authentication. The length depends on tag_length. + * @param[in] tag_length Byte length of tag. Must be 16. + */ + fsp_err_t (* chacha20Poly1305Verify)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_output, + uint32_t * const p_output_length, uint8_t const * const p_tag, + uint32_t const tag_length); + + /** + * Signs a hashed message. The message hash should be generated in advance. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Pointer to wrapped key of ECC private key. + * @param[in] p_hash Pointer to hash value. The length is as same as the key length. + * @param[out] p_signature Pointer to destination of signature (r, s). + * The length is twice as long as the key length. + */ + fsp_err_t (* ecdsaSign)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_hash, uint8_t * const p_signature); + + /** + * Verifies a hashed message. The message hash should be generated in advance. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of ECC public key. + * @param[in] p_hash Pointer to hash value. The length is as same as the key length. + * @param[in] p_signature Pointer to signature (r, s). The length is twice as long as the key length. + */ + fsp_err_t (* ecdsaVerify)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_hash, uint8_t const * const p_signature); + + /** + * Sign the message using EdDSA. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Pointer to wrapped key of ECC private key. + * @param[in] p_wrapped_public_key Pointer to wrapped key of ECC public key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[out] p_signature Pointer to destination of signature (r, s). + * The length is twice as long as the key length. + */ + fsp_err_t (* eddsaSign)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_wrapped_key_t const * const p_wrapped_public_key, uint8_t const * const p_message, + uint64_t const message_length, uint8_t * const p_signature); + + /** + * Verifies the message using EdDSA. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of ECC public key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] p_signature Pointer to signature (r, s). The length is twice as long as the key length. + */ + fsp_err_t (* eddsaVerify)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_message, uint64_t const message_length, + uint8_t const * const p_signature); + + /** + * Computes ECDH secret with wrapped private key and wrapped public key. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Wrapped secp256r1 private key. + * @param[in] p_wrapped_public_key Wrapped secp256r1 public key. + * @param[out] p_wrapped_secret Pointer to destination of wrapped secret + */ + fsp_err_t (* ecdhKeyAgree)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_wrapped_secret_abstractor_t * const p_wrapped_secret); + + /** + * Computes ECDH secret with wrapped private key and plain public key. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Wrapped secp256r1 private key. + * @param[in] p_plain_public_key Plain secp256r1 public key. + * @param[out] p_wrapped_secret Pointer to destination of wrapped secret. + */ + fsp_err_t (* ecdhPlainKeyAgree)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_plain_public_key, + rsip_wrapped_secret_abstractor_t * const p_wrapped_secret); + + /** + * Encrypts plaintext with raw RSA. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] p_plain Pointer to plaintext. The length is as same as the key length. + * @param[out] p_cipher Pointer to destination of ciphertext. The length is as same as the key length. + */ + fsp_err_t (* rsaEncrypt)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, uint8_t * const p_cipher); + + /** + * Decrypts ciphertext with raw RSA. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Pointer to wrapped key of RSA private key. + * @param[in] p_cipher Pointer to ciphertext. The length is as same as the key length. + * @param[out] p_plain Pointer to destination of plaintext. The length is as same as the key length. + */ + fsp_err_t (* rsaDecrypt)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_cipher, uint8_t * const p_plain); + + /** + * Encrypts plaintext with RSAES-PKCS1-v1_5. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] p_plain Pointer to plaintext. + * @param[in] plain_length Length of plaintext. + * @param[out] p_cipher Pointer to destination of ciphertext. The length is as same as the key length. + */ + fsp_err_t (* rsaesPkcs1V15Encrypt)(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, uint32_t const plain_length, + uint8_t * const p_cipher); + + /** + * Decrypts with RSAES-PKCS1-v1_5. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Pointer to wrapped key of RSA private key. + * @param[in] p_cipher Pointer to ciphertext. The length is as same as the key length. + * @param[out] p_plain Pointer to destination of plaintext. + * @param[out] p_plain_length Pointer to destination of actual plaintext length. + * @param[in] plain_buffer_length Length of plaintext destination. It must be equal to or greater than *p_plain_length. + */ + fsp_err_t (* rsaesPkcs1V15Decrypt)(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_cipher, uint8_t * const p_plain, + uint32_t * const p_plain_length, uint32_t const plain_buffer_length); + + /** + * Encrypts plaintext with RSAES-OAEP. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] hash_function Hash function for label. + * @param[in] mask_generation_function Mask generation function in EME-OAEP encoding. + * @param[in] p_label Pointer to label. If label_length != 0, p_label must not be NULL. + * @param[in] label_length Length of label. Please set 0 or more. + * @param[in] p_plain Pointer to plaintext. + * @param[in] plain_length Length of plaintext. + * @param[out] p_cipher Pointer to destination of ciphertext. The length is as same as the key length. + */ + fsp_err_t (* rsaesOaepEncrypt)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, + uint8_t const * const p_label, + uint32_t const label_length, uint8_t const * const p_plain, + uint32_t const plain_length, uint8_t * const p_cipher); + + /** + * Decrypts ciphertext with RSAES-OAEP. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Pointer to wrapped key of RSA private key. + * @param[in] hash_function Hash function for label. + * @param[in] mask_generation_function Mask generation function in EME-OAEP encoding. + * @param[in] p_label Pointer to label. If label_length != 0, p_label must not be NULL. + * @param[in] label_length Length of label. Please set 0 or more. + * @param[in] p_cipher Pointer to ciphertext. The length is as same as the key length. + * @param[out] p_plain Pointer to destination of plaintext. + * @param[out] p_plain_length Pointer to destination of actual plaintext length. + * @param[in] plain_buffer_length Length of plaintext destination. It must be equal to or greater than + * *p_plain_length. + */ + fsp_err_t (* rsaesOaepDecrypt)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, + uint8_t const * const p_label, + uint32_t const label_length, uint8_t const * const p_cipher, uint8_t * const p_plain, + uint32_t * const p_plain_length, uint32_t const plain_buffer_length); + + /** + * Signs message with RSASSA-PKCS1-v1_5. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Pointer to wrapped key of RSA private key. + * @param[in] hash_function Hash function in EMSA-PKCS1-v1_5. + * @param[in] p_hash Pointer to input hash. + * @param[out] p_signature Pointer to destination of signature. + */ + fsp_err_t (* rsassaPkcs1V15Sign)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, uint8_t const * const p_hash, + uint8_t * const p_signature); + + /** + * Verifies signature with RSASSA-PKCS1-v1_5. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] hash_function Hash function in EMSA-PKCS1-v1_5. + * @param[in] p_hash Pointer to input hash. + * @param[in] p_signature Pointer to input signature. + */ + fsp_err_t (* rsassaPkcs1V15Verify)(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, uint8_t const * const p_signature); + + /** + * Signs message with RSASSA-PSS. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_private_key Pointer to wrapped key of RSA private key. + * @param[in] hash_function Hash function in EMSA-PSS-ENCODE. + * @param[in] mask_generation_function Mask generation function in EMSA-PSS-ENCODE. + * @param[in] salt_length Salt length. + * @param[in] p_hash Pointer to input hash. + * @param[out] p_signature Pointer to destination of signature. + */ + fsp_err_t (* rsassaPssSign)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_hash, uint8_t * const p_signature); + + /** + * Verifies signature with RSASSA-PSS. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] hash_function Hash function in EMSA-PSS-VERIFY. + * @param[in] mask_generation_function Mask generation function in EMSA-PSS-VERIFY. + * @param[in] salt_length Salt length. + * @param[in] p_hash Pointer to input hash. + * @param[in] p_signature Pointer to input signature. + */ + fsp_err_t (* rsassaPssVerify)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_hash, uint8_t const * const p_signature); + + /** + * Generates SHA message digest. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] hash_type Generating hash type. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + */ + fsp_err_t (* shaCompute)(rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type, + uint8_t const * const p_message, uint32_t const message_length, uint8_t * const p_digest); + + /** + * Prepares a SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] hash_type Generating hash type. + */ + fsp_err_t (* shaInit)(rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type); + + /** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + */ + fsp_err_t (* shaUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, uint32_t const message_length); + + /** + * Finalizes a SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + */ + fsp_err_t (* shaFinish)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_digest); + + /** + * Suspend SHA generation. + * This API allows you to suspend processing, for example, if you are in the middle of computing digest value for successive chunks of the message and need to perform another process. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_handle Pointer to destination of SHA control block. + */ + fsp_err_t (* shaSuspend)(rsip_ctrl_t * const p_ctrl, rsip_sha_handle_abstractor_t * const p_handle); + + /** + * Resume SHA generation. + * This API allows you to resume a process that has been suspended by R_RSIP_SHA_Suspend() API. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_handle Pointer to SHA control block. + */ + fsp_err_t (* shaResume)(rsip_ctrl_t * const p_ctrl, rsip_sha_handle_abstractor_t const * const p_handle); + + /** + * Generates HMAC. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + */ + fsp_err_t (* hmacCompute)(rsip_ctrl_t * const p_ctrl, const rsip_wrapped_key_t * p_wrapped_key, + uint8_t const * const p_message, uint32_t const message_length, uint8_t * const p_mac); + + /** + * Verifies HMAC. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + */ + fsp_err_t (* hmacVerify)(rsip_ctrl_t * const p_ctrl, const rsip_wrapped_key_t * p_wrapped_key, + uint8_t const * const p_message, uint32_t const message_length, + uint8_t const * const p_mac, + uint32_t const mac_length); + + /** + * Prepares a HMAC generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + */ + fsp_err_t (* hmacInit)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_key); + + /** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + */ + fsp_err_t (* hmacUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, + uint32_t const message_length); + + /** + * Finalizes a HMAC generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + */ + fsp_err_t (* hmacSignFinish)(rsip_ctrl_t * const p_ctrl, uint8_t * const p_mac); + + /** + * Finalizes a HMAC verification. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + */ + fsp_err_t (* hmacVerifyFinish)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_mac, uint32_t const mac_length); + + /** + * Suspend HMAC generation. + * This API allows you to suspend processing, for example, if you are in the middle of computing HMAC for successive chunks of the message and need to perform another process. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_handle Pointer to destination of HMAC control block. + */ + fsp_err_t (* hmacSuspend)(rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_abstractor_t * const p_handle); + + /** + * Resume HMAC generation. + * This API allows you to resume a process that has been suspended by R_RSIP_HMAC_Suspend() API. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_handle Pointer to HMAC control block. + */ + fsp_err_t (* hmacResume)(rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_abstractor_t const * const p_handle); + + /** + * Verifies a public key certificate with ECDSA. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of ECC public key. + * @param[in] p_hash Pointer to hash value. The length is as same as the key length. + * @param[in] p_signature Pointer to signature (r, s). The length is twice as long as the key length. + */ + fsp_err_t (* pkiEcdsaCertVerify)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_hash, uint8_t const * const p_signature); + + /** + * Exports verified certificate information stored in this driver. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_verified_cert_info Pointer to certificate to be signed + */ + fsp_err_t (* pkiVerifiedCertInfoExport)(rsip_ctrl_t * const p_ctrl, + rsip_verified_cert_info_abstractor_t * const p_verified_cert_info); + + /** + * Imports verified certificate information. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_verified_cert_info Pointer to certificate to be signed + */ + fsp_err_t (* pkiVerifiedCertInfoImport)(rsip_ctrl_t * const p_ctrl, + rsip_verified_cert_info_abstractor_t const * const p_verified_cert_info); + + /** + * Wraps the public key in the verified public key certificate. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_cert Pointer to certificate. + * @param[in] cert_length Certificate length. + * @param[in] p_key_param1 Pointer to start address of the public key parameter in certificate. + * - [ECC] Qx + * @param[in] key_param1_length Length of key_param1 stored in the certificate. + * @param[in] p_key_param2 Pointer to start address of the public key parameter in certificate. + * - [ECC] Qy + * @param[in] key_param2_length Length of key_param2 stored in the certificate. + * @param[in] hash_function The hash function used when verifying certificate signature. + * @param[in,out] p_wrapped_public_key Pointer to wrapped key of public key in the certificate. + */ + fsp_err_t (* pkiCertKeyImport)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_cert, uint32_t const cert_length, + uint8_t const * const p_key_param1, uint32_t const key_param1_length, + uint8_t const * const p_key_param2, + uint32_t const key_param2_length, rsip_hash_type_t const hash_function, + rsip_wrapped_key_t * const p_wrapped_public_key); + + /** + * Prepares a SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] hash_type Generating hash type. + */ + fsp_err_t (* kdfShaInit)(rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type); + + /** + * Inputs wrapped ECDH secret as a message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_secret Pointer to wrapped secret. + */ + fsp_err_t (* kdfShaEcdhSecretUpdate)(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_abstractor_t const * const p_wrapped_secret); + + /** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + */ + fsp_err_t (* kdfShaUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, + uint32_t const message_length); + + /** + * Finalizes a SHA operation and generate DKM (Derived Keying Material). + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_wrapped_dkm Pointer to destination of wrapped DKM. + */ + fsp_err_t (* kdfShaFinish)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t * const p_wrapped_dkm); + + /** + * Suspend SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_handle Pointer to destination of KDF SHA control block. + */ + fsp_err_t (* kdfShaSuspend)(rsip_ctrl_t * const p_ctrl, rsip_kdf_sha_handle_abstractor_t * const p_handle); + + /** + * Resume SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_handle Pointer to KDF SHA control block. + */ + fsp_err_t (* kdfShaResume)(rsip_ctrl_t * const p_ctrl, rsip_kdf_sha_handle_abstractor_t const * const p_handle); + + /** + * Converts wrapped Derived Keying Material (DKM) to HMAC key for KDF. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_dkm Pointer to wrapped DKM. + * @param[in] key_length Length of HMAC key to be extracted from DKM. + * @param[in,out] p_wrapped_key Pointer to destination wrapped HMAC key for KDF. + */ + fsp_err_t (* kdfHmacDkmKeyImport)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t const * const p_wrapped_dkm, + uint32_t const key_length, rsip_wrapped_key_t * const p_wrapped_key); + + /** + * Converts wrapped ECDH secret to wrapped HMAC key for KDF. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_secret Pointer to wrapped secret. + * @param[in,out] p_wrapped_key Pointer to destination wrapped HMAC key for KDF. + */ + fsp_err_t (* kdfHmacEcdhSecretKeyImport)(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_abstractor_t const * const p_wrapped_secret, + rsip_wrapped_key_t * const p_wrapped_key); + + /** + * Prepares a HMAC generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + */ + fsp_err_t (* kdfHmacInit)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_key); + + /** + * Inputs wrapped Derived Keying Material (DKM) as a message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_dkm Pointer to wrapped DKM. + */ + fsp_err_t (* kdfHmacDkmUpdate)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t const * const p_wrapped_dkm); + + /** + * Inputs wrapped ECDH secret as a message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_secret Pointer to wrapped secret. + */ + fsp_err_t (* kdfHmacEcdhSecretUpdate)(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_abstractor_t const * const p_wrapped_secret); + + /** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + */ + fsp_err_t (* kdfHmacUpdate)(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, + uint32_t const message_length); + + /** + * Finalizes a HMAC generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_wrapped_dkm Pointer to destination of wrapped Derived Keying Material (DKM). + */ + fsp_err_t (* kdfHmacSignFinish)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t * const p_wrapped_dkm); + + /** + * Suspends HMAC operation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_handle Pointer to destination of KDF HMAC control block. + */ + fsp_err_t (* kdfHmacSuspend)(rsip_ctrl_t * const p_ctrl, rsip_kdf_hmac_handle_abstractor_t * const p_handle); + + /** + * Resumes HMAC operation suspended by R_RSIP_KDF_HMAC_Suspend(). + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_handle Pointer to KDF HMAC control block. + */ + fsp_err_t (* kdfHmacResume)(rsip_ctrl_t * const p_ctrl, rsip_kdf_hmac_handle_abstractor_t const * const p_handle); + + /** + * Concatenates two wrapped derived keying materials (DKMs). + * + * @param[in,out] p_wrapped_dkm1 Pointer to first DKM (DKM1). + * @param[in] p_wrapped_dkm2 Pointer to second DKM (DKM2). + * @param[in] wrapped_dkm1_buffer_length Length of wrapped_dkm1 buffer. + * It must be equal to or greater than DKM1 || DKM2. + */ + fsp_err_t (* kdfDkmConcatenate)(rsip_wrapped_dkm_t * const p_wrapped_dkm1, + rsip_wrapped_dkm_t const * const p_wrapped_dkm2, + uint32_t const wrapped_dkm1_buffer_length); + + /** + * Outputs a wrapped key from Derived Keying Material (DKM). + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_dkm Pointer to wrapped DKM. + * @param[in] position Start position of output key value in the DKM. + * @param[in,out] p_wrapped_key Pointer to destination of wrapped key. + */ + fsp_err_t (* kdfDerivedKeyImport)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t const * const p_wrapped_dkm, + uint32_t const position, rsip_wrapped_key_t * const p_wrapped_key); + + /** + * Outputs a initial vector from Derived Keying Material (DKM). + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_dkm Pointer to wrapped DKM. + * @param[in] initial_vector_type Initial vector type. + * @param[in] position Start position of output data value in the DKM. + * @param[in] p_tls_sequence_num TLS sequence number. This argument is valid only for TLS-related data type. + * @param[out] p_wrapped_initial_vector Pointer to destination of wrapped initial vector. + */ + fsp_err_t (* kdfDerivedIvWrap)(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t const * const p_wrapped_dkm, + rsip_initial_vector_type_t const initial_vector_type, uint32_t const position, + uint8_t const * const p_tls_sequence_num, uint8_t * const p_wrapped_initial_vector); + + /** + * Initialize on-the-fly decryption on RSIP. + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] channel Channel number. + * @param[in] p_wrapped_key Pointer to wrapped AES key. + * @param[in] p_seed Pointer to seed. + */ + fsp_err_t (* otfInit)(rsip_ctrl_t * const p_ctrl, rsip_otf_channel_t const channel, + rsip_wrapped_key_t * const p_wrapped_key, uint8_t const * const p_seed); +} rsip_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_rsip_instance +{ + rsip_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + rsip_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + rsip_api_t const * p_api; ///< Pointer to the API structure for this instance +} rsip_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_RSIP_API_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_err.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_err.h new file mode 100644 index 0000000000..a9571be212 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_err.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_ERR_H +#define R_RSIP_ERR_H + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Return code of internal function */ +typedef enum e_rsip_ret +{ + /* Success */ + RSIP_RET_PASS, + + /* Branching */ + RSIP_RET_PASS_0, + RSIP_RET_PASS_1, + RSIP_RET_PASS_2, + + /* Error */ + RSIP_RET_RESOURCE_CONFLICT, + RSIP_RET_RETRY, + RSIP_RET_FAIL, + RSIP_RET_KEY_FAIL, + RSIP_RET_PARAM_FAIL, + RSIP_RET_VERIFICATION_FAIL, + RSIP_RET_AUTH_FAIL, + RSIP_RET_VERSION_MATCH, + RSIP_RET_UNKNOWN +} rsip_ret_t; + +#endif /* R_RSIP_ERR_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.c new file mode 100644 index 0000000000..756edde3a8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_reg.h" + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +#if defined(__ARM_ARCH) && defined(__GNUC__) +uintptr_t const g_rsip_addr_0000h = RSIP_PRV_ADDR_VAL_0000H; +#endif + +#if defined(__ARM_ARCH) && defined(__GNUC__) && (5U == RSIP_PRV_ADDR_TYPE) +uintptr_t const g_rsip_addr_1000h = RSIP_PRV_ADDR_VAL_1000H; +uintptr_t const g_rsip_addr_2000h = RSIP_PRV_ADDR_VAL_2000H; +uintptr_t const g_rsip_addr_1420h = RSIP_PRV_ADDR_VAL_1420H; +uintptr_t const g_rsip_addr_1440h = RSIP_PRV_ADDR_VAL_1440H; +uintptr_t const g_rsip_addr_1600h = RSIP_PRV_ADDR_VAL_1600H; + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.h new file mode 100644 index 0000000000..e978bed1dc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_reg.h @@ -0,0 +1,2668 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_REG_H +#define R_RSIP_REG_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_rsip_addr.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* RSIP register access macro */ +#define RD1_MASK(reg, value) ((reg) & (value)) +#define CHCK_STS(reg, bitPos, value) ((value) == ((reg >> bitPos) & 1)) +#define WAIT_STS(reg, bitPos, value) while (!CHCK_STS((reg), (bitPos), (value))) {;} +#define WR1_ADDR(reg, addr) (reg) = *(addr) +#define WR2_ADDR(reg, addr) \ + { \ + WR1_ADDR((reg), (&(addr)[0])); \ + WR1_ADDR((reg), (&(addr)[1])); \ + } +#define WR4_ADDR(reg, addr) \ + { \ + WR1_ADDR((reg), (&(addr)[0])); \ + WR1_ADDR((reg), (&(addr)[1])); \ + WR1_ADDR((reg), (&(addr)[2])); \ + WR1_ADDR((reg), (&(addr)[3])); \ + } +#define WR3_ADDR(reg, addr) \ + { \ + WR1_ADDR((reg), (&(addr)[0])); \ + WR1_ADDR((reg), (&(addr)[1])); \ + WR1_ADDR((reg), (&(addr)[2])); \ + } +#define WR8_ADDR(reg, addr) \ + { \ + WR1_ADDR((reg), (&(addr)[0])); \ + WR1_ADDR((reg), (&(addr)[1])); \ + WR1_ADDR((reg), (&(addr)[2])); \ + WR1_ADDR((reg), (&(addr)[3])); \ + WR1_ADDR((reg), (&(addr)[4])); \ + WR1_ADDR((reg), (&(addr)[5])); \ + WR1_ADDR((reg), (&(addr)[6])); \ + WR1_ADDR((reg), (&(addr)[7])); \ + } +#define WR12_ADDR(reg, addr) \ + { \ + WR1_ADDR((reg), (&(addr)[0])); \ + WR1_ADDR((reg), (&(addr)[1])); \ + WR1_ADDR((reg), (&(addr)[2])); \ + WR1_ADDR((reg), (&(addr)[3])); \ + WR1_ADDR((reg), (&(addr)[4])); \ + WR1_ADDR((reg), (&(addr)[5])); \ + WR1_ADDR((reg), (&(addr)[6])); \ + WR1_ADDR((reg), (&(addr)[7])); \ + WR1_ADDR((reg), (&(addr)[8])); \ + WR1_ADDR((reg), (&(addr)[9])); \ + WR1_ADDR((reg), (&(addr)[10])); \ + WR1_ADDR((reg), (&(addr)[11])); \ + } +#define WR16_ADDR(reg, addr) \ + { \ + WR1_ADDR((reg), (&(addr)[0])); \ + WR1_ADDR((reg), (&(addr)[1])); \ + WR1_ADDR((reg), (&(addr)[2])); \ + WR1_ADDR((reg), (&(addr)[3])); \ + WR1_ADDR((reg), (&(addr)[4])); \ + WR1_ADDR((reg), (&(addr)[5])); \ + WR1_ADDR((reg), (&(addr)[6])); \ + WR1_ADDR((reg), (&(addr)[7])); \ + WR1_ADDR((reg), (&(addr)[8])); \ + WR1_ADDR((reg), (&(addr)[9])); \ + WR1_ADDR((reg), (&(addr)[10])); \ + WR1_ADDR((reg), (&(addr)[11])); \ + WR1_ADDR((reg), (&(addr)[12])); \ + WR1_ADDR((reg), (&(addr)[13])); \ + WR1_ADDR((reg), (&(addr)[14])); \ + WR1_ADDR((reg), (&(addr)[15])); \ + } +#define WR1_PROG(reg, value) (reg) = (value) +#define WR2_PROG(reg, value0, value1) \ + { \ + WR1_PROG((reg), (value0)); \ + WR1_PROG((reg), (value1)); \ + } +#define WR4_PROG(reg, value0, value1, value2, value3) \ + { \ + WR1_PROG((reg), (value0)); \ + WR1_PROG((reg), (value1)); \ + WR1_PROG((reg), (value2)); \ + WR1_PROG((reg), (value3)); \ + } +#define WR8_PROG(reg, value0, value1, value2, value3, value4, value5, value6, value7) \ + { \ + WR1_PROG((reg), (value0)); \ + WR1_PROG((reg), (value1)); \ + WR1_PROG((reg), (value2)); \ + WR1_PROG((reg), (value3)); \ + WR1_PROG((reg), (value4)); \ + WR1_PROG((reg), (value5)); \ + WR1_PROG((reg), (value6)); \ + WR1_PROG((reg), (value7)); \ + } +#define RD1_ADDR(reg, addr) *(addr) = (reg) +#define RD4_ADDR(reg, addr) \ + { \ + RD1_ADDR((reg), (&(addr)[0])); \ + RD1_ADDR((reg), (&(addr)[1])); \ + RD1_ADDR((reg), (&(addr)[2])); \ + RD1_ADDR((reg), (&(addr)[3])); \ + } +#define RD7_ADDR(reg, addr) \ + { \ + RD1_ADDR((reg), (&(addr)[0])); \ + RD1_ADDR((reg), (&(addr)[1])); \ + RD1_ADDR((reg), (&(addr)[2])); \ + RD1_ADDR((reg), (&(addr)[3])); \ + RD1_ADDR((reg), (&(addr)[4])); \ + RD1_ADDR((reg), (&(addr)[5])); \ + RD1_ADDR((reg), (&(addr)[6])); \ + } +#define RD8_ADDR(reg, addr) \ + { \ + RD1_ADDR((reg), (&(addr)[0])); \ + RD1_ADDR((reg), (&(addr)[1])); \ + RD1_ADDR((reg), (&(addr)[2])); \ + RD1_ADDR((reg), (&(addr)[3])); \ + RD1_ADDR((reg), (&(addr)[4])); \ + RD1_ADDR((reg), (&(addr)[5])); \ + RD1_ADDR((reg), (&(addr)[6])); \ + RD1_ADDR((reg), (&(addr)[7])); \ + } +#define RD12_ADDR(reg, addr) \ + { \ + RD1_ADDR((reg), (&(addr)[0])); \ + RD1_ADDR((reg), (&(addr)[1])); \ + RD1_ADDR((reg), (&(addr)[2])); \ + RD1_ADDR((reg), (&(addr)[3])); \ + RD1_ADDR((reg), (&(addr)[4])); \ + RD1_ADDR((reg), (&(addr)[5])); \ + RD1_ADDR((reg), (&(addr)[6])); \ + RD1_ADDR((reg), (&(addr)[7])); \ + RD1_ADDR((reg), (&(addr)[8])); \ + RD1_ADDR((reg), (&(addr)[9])); \ + RD1_ADDR((reg), (&(addr)[10])); \ + RD1_ADDR((reg), (&(addr)[11])); \ + } +#define RD16_ADDR(reg, addr) \ + { \ + RD1_ADDR((reg), (&(addr)[0])); \ + RD1_ADDR((reg), (&(addr)[1])); \ + RD1_ADDR((reg), (&(addr)[2])); \ + RD1_ADDR((reg), (&(addr)[3])); \ + RD1_ADDR((reg), (&(addr)[4])); \ + RD1_ADDR((reg), (&(addr)[5])); \ + RD1_ADDR((reg), (&(addr)[6])); \ + RD1_ADDR((reg), (&(addr)[7])); \ + RD1_ADDR((reg), (&(addr)[8])); \ + RD1_ADDR((reg), (&(addr)[9])); \ + RD1_ADDR((reg), (&(addr)[10])); \ + RD1_ADDR((reg), (&(addr)[11])); \ + RD1_ADDR((reg), (&(addr)[12])); \ + RD1_ADDR((reg), (&(addr)[13])); \ + RD1_ADDR((reg), (&(addr)[14])); \ + RD1_ADDR((reg), (&(addr)[15])); \ + } + +/* register address */ +#define REG_0000H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x000U)) +#define REG_0004H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x004U)) +#define REG_0008H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x008U)) +#define REG_000CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x00CU)) +#define REG_0010H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x010U)) +#define REG_0014H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x014U)) +#define REG_0018H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x018U)) +#define REG_001CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x01CU)) +#define REG_0020H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x020U)) +#define REG_0024H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x024U)) +#define REG_0028H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x028U)) +#define REG_002CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x02CU)) +#define REG_0030H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x030U)) +#define REG_0034H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x034U)) +#define REG_0038H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x038U)) +#define REG_003CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x03CU)) +#define REG_0040H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x040U)) +#define REG_0044H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x044U)) +#define REG_0048H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x048U)) +#define REG_004CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x04CU)) +#define REG_0050H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x050U)) +#define REG_0054H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x054U)) +#define REG_0058H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x058U)) +#define REG_005CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x05CU)) +#define REG_0060H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x060U)) +#define REG_0064H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x064U)) +#define REG_0068H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x068U)) +#define REG_006CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x06CU)) +#define REG_0070H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x070U)) +#define REG_0074H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x074U)) +#define REG_0078H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x078U)) +#define REG_007CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x07CU)) +#define REG_0080H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x080U)) +#define REG_0084H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x084U)) +#define REG_0088H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x088U)) +#define REG_008CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x08CU)) +#define REG_0090H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x090U)) +#define REG_0094H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x094U)) +#define REG_0098H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x098U)) +#define REG_009CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x09CU)) +#define REG_00A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0A0U)) +#define REG_00A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0A4U)) +#define REG_00A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0A8U)) +#define REG_00ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0ACU)) +#define REG_00B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0B0U)) +#define REG_00B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0B4U)) +#define REG_00B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0B8U)) +#define REG_00BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0BCU)) +#define REG_00C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0C0U)) +#define REG_00C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0C4U)) +#define REG_00C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0C8U)) +#define REG_00CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0CCU)) +#define REG_00D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0D0U)) +#define REG_00D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0D4U)) +#define REG_00D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0D8U)) +#define REG_00DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0DCU)) +#define REG_00E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0E0U)) +#define REG_00E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0E4U)) +#define REG_00E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0E8U)) +#define REG_00ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0ECU)) +#define REG_00F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0F0U)) +#define REG_00F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0F4U)) +#define REG_00F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0F8U)) +#define REG_00FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x0FCU)) +#define REG_0100H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x100U)) +#define REG_0104H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x104U)) +#define REG_0108H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x108U)) +#define REG_010CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x10CU)) +#define REG_0110H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x110U)) +#define REG_0114H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x114U)) +#define REG_0118H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x118U)) +#define REG_011CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x11CU)) +#define REG_0120H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x120U)) +#define REG_0124H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x124U)) +#define REG_0128H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x128U)) +#define REG_012CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x12CU)) +#define REG_0130H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x130U)) +#define REG_0134H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x134U)) +#define REG_0138H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x138U)) +#define REG_013CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x13CU)) +#define REG_0140H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x140U)) +#define REG_0144H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x144U)) +#define REG_0148H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x148U)) +#define REG_014CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x14CU)) +#define REG_0150H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x150U)) +#define REG_0154H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x154U)) +#define REG_0158H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x158U)) +#define REG_015CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x15CU)) +#define REG_0160H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x160U)) +#define REG_0164H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x164U)) +#define REG_0168H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x168U)) +#define REG_016CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x16CU)) +#define REG_0170H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x170U)) +#define REG_0174H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x174U)) +#define REG_0178H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x178U)) +#define REG_017CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x17CU)) +#define REG_0180H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x180U)) +#define REG_0184H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x184U)) +#define REG_0188H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x188U)) +#define REG_018CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x18CU)) +#define REG_0190H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x190U)) +#define REG_0194H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x194U)) +#define REG_0198H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x198U)) +#define REG_019CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x19CU)) +#define REG_01A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1A0U)) +#define REG_01A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1A4U)) +#define REG_01A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1A8U)) +#define REG_01ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1ACU)) +#define REG_01B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1B0U)) +#define REG_01B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1B4U)) +#define REG_01B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1B8U)) +#define REG_01BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1BCU)) +#define REG_01C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1C0U)) +#define REG_01C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1C4U)) +#define REG_01C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1C8U)) +#define REG_01CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1CCU)) +#define REG_01D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1D0U)) +#define REG_01D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1D4U)) +#define REG_01D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1D8U)) +#define REG_01DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1DCU)) +#define REG_01E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1E0U)) +#define REG_01E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1E4U)) +#define REG_01E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1E8U)) +#define REG_01ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1ECU)) +#define REG_01F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1F0U)) +#define REG_01F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1F4U)) +#define REG_01F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1F8U)) +#define REG_01FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x1FCU)) +#define REG_0200H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x200U)) +#define REG_0204H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x204U)) +#define REG_0208H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x208U)) +#define REG_020CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x20CU)) +#define REG_0210H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x210U)) +#define REG_0214H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x214U)) +#define REG_0218H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x218U)) +#define REG_021CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x21CU)) +#define REG_0220H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x220U)) +#define REG_0224H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x224U)) +#define REG_0228H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x228U)) +#define REG_022CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x22CU)) +#define REG_0230H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x230U)) +#define REG_0234H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x234U)) +#define REG_0238H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x238U)) +#define REG_023CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x23CU)) +#define REG_0240H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x240U)) +#define REG_0244H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x244U)) +#define REG_0248H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x248U)) +#define REG_024CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x24CU)) +#define REG_0250H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x250U)) +#define REG_0254H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x254U)) +#define REG_0258H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x258U)) +#define REG_025CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x25CU)) +#define REG_0260H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x260U)) +#define REG_0264H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x264U)) +#define REG_0268H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x268U)) +#define REG_026CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x26CU)) +#define REG_0270H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x270U)) +#define REG_0274H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x274U)) +#define REG_0278H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x278U)) +#define REG_027CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x27CU)) +#define REG_0280H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x280U)) +#define REG_0284H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x284U)) +#define REG_0288H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x288U)) +#define REG_028CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x28CU)) +#define REG_0290H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x290U)) +#define REG_0294H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x294U)) +#define REG_0298H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x298U)) +#define REG_029CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x29CU)) +#define REG_02A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2A0U)) +#define REG_02A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2A4U)) +#define REG_02A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2A8U)) +#define REG_02ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2ACU)) +#define REG_02B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2B0U)) +#define REG_02B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2B4U)) +#define REG_02B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2B8U)) +#define REG_02BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2BCU)) +#define REG_02C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2C0U)) +#define REG_02C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2C4U)) +#define REG_02C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2C8U)) +#define REG_02CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2CCU)) +#define REG_02D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2D0U)) +#define REG_02D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2D4U)) +#define REG_02D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2D8U)) +#define REG_02DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2DCU)) +#define REG_02E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2E0U)) +#define REG_02E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2E4U)) +#define REG_02E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2E8U)) +#define REG_02ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2ECU)) +#define REG_02F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2F0U)) +#define REG_02F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2F4U)) +#define REG_02F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2F8U)) +#define REG_02FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x2FCU)) +#define REG_0300H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x300U)) +#define REG_0304H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x304U)) +#define REG_0308H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x308U)) +#define REG_030CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x30CU)) +#define REG_0310H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x310U)) +#define REG_0314H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x314U)) +#define REG_0318H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x318U)) +#define REG_031CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x31CU)) +#define REG_0320H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x320U)) +#define REG_0324H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x324U)) +#define REG_0328H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x328U)) +#define REG_032CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x32CU)) +#define REG_0330H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x330U)) +#define REG_0334H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x334U)) +#define REG_0338H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x338U)) +#define REG_033CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x33CU)) +#define REG_0340H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x340U)) +#define REG_0344H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x344U)) +#define REG_0348H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x348U)) +#define REG_034CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x34CU)) +#define REG_0350H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x350U)) +#define REG_0354H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x354U)) +#define REG_0358H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x358U)) +#define REG_035CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x35CU)) +#define REG_0360H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x360U)) +#define REG_0364H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x364U)) +#define REG_0368H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x368U)) +#define REG_036CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x36CU)) +#define REG_0370H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x370U)) +#define REG_0374H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x374U)) +#define REG_0378H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x378U)) +#define REG_037CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x37CU)) +#define REG_0380H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x380U)) +#define REG_0384H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x384U)) +#define REG_0388H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x388U)) +#define REG_038CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x38CU)) +#define REG_0390H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x390U)) +#define REG_0394H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x394U)) +#define REG_0398H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x398U)) +#define REG_039CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x39CU)) +#define REG_03A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3A0U)) +#define REG_03A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3A4U)) +#define REG_03A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3A8U)) +#define REG_03ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3ACU)) +#define REG_03B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3B0U)) +#define REG_03B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3B4U)) +#define REG_03B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3B8U)) +#define REG_03BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3BCU)) +#define REG_03C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3C0U)) +#define REG_03C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3C4U)) +#define REG_03C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3C8U)) +#define REG_03CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3CCU)) +#define REG_03D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3D0U)) +#define REG_03D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3D4U)) +#define REG_03D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3D8U)) +#define REG_03DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3DCU)) +#define REG_03E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3E0U)) +#define REG_03E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3E4U)) +#define REG_03E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3E8U)) +#define REG_03ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3ECU)) +#define REG_03F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3F0U)) +#define REG_03F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3F4U)) +#define REG_03F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3F8U)) +#define REG_03FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x3FCU)) +#define REG_0400H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x400U)) +#define REG_0404H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x404U)) +#define REG_0408H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x408U)) +#define REG_040CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x40CU)) +#define REG_0410H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x410U)) +#define REG_0414H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x414U)) +#define REG_0418H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x418U)) +#define REG_041CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x41CU)) +#define REG_0420H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x420U)) +#define REG_0424H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x424U)) +#define REG_0428H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x428U)) +#define REG_042CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x42CU)) +#define REG_0430H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x430U)) +#define REG_0434H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x434U)) +#define REG_0438H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x438U)) +#define REG_043CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x43CU)) +#define REG_0440H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x440U)) +#define REG_0444H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x444U)) +#define REG_0448H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x448U)) +#define REG_044CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x44CU)) +#define REG_0450H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x450U)) +#define REG_0454H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x454U)) +#define REG_0458H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x458U)) +#define REG_045CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x45CU)) +#define REG_0460H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x460U)) +#define REG_0464H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x464U)) +#define REG_0468H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x468U)) +#define REG_046CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x46CU)) +#define REG_0470H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x470U)) +#define REG_0474H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x474U)) +#define REG_0478H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x478U)) +#define REG_047CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x47CU)) +#define REG_0480H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x480U)) +#define REG_0484H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x484U)) +#define REG_0488H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x488U)) +#define REG_048CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x48CU)) +#define REG_0490H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x490U)) +#define REG_0494H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x494U)) +#define REG_0498H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x498U)) +#define REG_049CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x49CU)) +#define REG_04A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4A0U)) +#define REG_04A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4A4U)) +#define REG_04A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4A8U)) +#define REG_04ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4ACU)) +#define REG_04B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4B0U)) +#define REG_04B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4B4U)) +#define REG_04B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4B8U)) +#define REG_04BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4BCU)) +#define REG_04C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4C0U)) +#define REG_04C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4C4U)) +#define REG_04C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4C8U)) +#define REG_04CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4CCU)) +#define REG_04D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4D0U)) +#define REG_04D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4D4U)) +#define REG_04D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4D8U)) +#define REG_04DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4DCU)) +#define REG_04E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4E0U)) +#define REG_04E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4E4U)) +#define REG_04E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4E8U)) +#define REG_04ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4ECU)) +#define REG_04F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4F0U)) +#define REG_04F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4F4U)) +#define REG_04F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4F8U)) +#define REG_04FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x4FCU)) +#define REG_0500H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x500U)) +#define REG_0504H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x504U)) +#define REG_0508H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x508U)) +#define REG_050CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x50CU)) +#define REG_0510H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x510U)) +#define REG_0514H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x514U)) +#define REG_0518H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x518U)) +#define REG_051CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x51CU)) +#define REG_0520H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x520U)) +#define REG_0524H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x524U)) +#define REG_0528H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x528U)) +#define REG_052CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x52CU)) +#define REG_0530H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x530U)) +#define REG_0534H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x534U)) +#define REG_0538H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x538U)) +#define REG_053CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x53CU)) +#define REG_0540H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x540U)) +#define REG_0544H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x544U)) +#define REG_0548H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x548U)) +#define REG_054CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x54CU)) +#define REG_0550H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x550U)) +#define REG_0554H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x554U)) +#define REG_0558H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x558U)) +#define REG_055CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x55CU)) +#define REG_0560H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x560U)) +#define REG_0564H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x564U)) +#define REG_0568H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x568U)) +#define REG_056CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x56CU)) +#define REG_0570H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x570U)) +#define REG_0574H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x574U)) +#define REG_0578H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x578U)) +#define REG_057CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x57CU)) +#define REG_0580H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x580U)) +#define REG_0584H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x584U)) +#define REG_0588H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x588U)) +#define REG_058CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x58CU)) +#define REG_0590H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x590U)) +#define REG_0594H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x594U)) +#define REG_0598H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x598U)) +#define REG_059CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x59CU)) +#define REG_05A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5A0U)) +#define REG_05A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5A4U)) +#define REG_05A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5A8U)) +#define REG_05ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5ACU)) +#define REG_05B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5B0U)) +#define REG_05B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5B4U)) +#define REG_05B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5B8U)) +#define REG_05BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5BCU)) +#define REG_05C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5C0U)) +#define REG_05C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5C4U)) +#define REG_05C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5C8U)) +#define REG_05CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5CCU)) +#define REG_05D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5D0U)) +#define REG_05D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5D4U)) +#define REG_05D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5D8U)) +#define REG_05DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5DCU)) +#define REG_05E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5E0U)) +#define REG_05E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5E4U)) +#define REG_05E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5E8U)) +#define REG_05ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5ECU)) +#define REG_05F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5F0U)) +#define REG_05F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5F4U)) +#define REG_05F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5F8U)) +#define REG_05FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x5FCU)) +#define REG_0600H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x600U)) +#define REG_0604H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x604U)) +#define REG_0608H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x608U)) +#define REG_060CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x60CU)) +#define REG_0610H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x610U)) +#define REG_0614H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x614U)) +#define REG_0618H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x618U)) +#define REG_061CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x61CU)) +#define REG_0620H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x620U)) +#define REG_0624H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x624U)) +#define REG_0628H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x628U)) +#define REG_062CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x62CU)) +#define REG_0630H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x630U)) +#define REG_0634H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x634U)) +#define REG_0638H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x638U)) +#define REG_063CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x63CU)) +#define REG_0640H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x640U)) +#define REG_0644H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x644U)) +#define REG_0648H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x648U)) +#define REG_064CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x64CU)) +#define REG_0650H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x650U)) +#define REG_0654H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x654U)) +#define REG_0658H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x658U)) +#define REG_065CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x65CU)) +#define REG_0660H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x660U)) +#define REG_0664H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x664U)) +#define REG_0668H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x668U)) +#define REG_066CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x66CU)) +#define REG_0670H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x670U)) +#define REG_0674H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x674U)) +#define REG_0678H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x678U)) +#define REG_067CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x67CU)) +#define REG_0680H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x680U)) +#define REG_0684H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x684U)) +#define REG_0688H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x688U)) +#define REG_068CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x68CU)) +#define REG_0690H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x690U)) +#define REG_0694H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x694U)) +#define REG_0698H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x698U)) +#define REG_069CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x69CU)) +#define REG_06A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6A0U)) +#define REG_06A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6A4U)) +#define REG_06A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6A8U)) +#define REG_06ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6ACU)) +#define REG_06B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6B0U)) +#define REG_06B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6B4U)) +#define REG_06B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6B8U)) +#define REG_06BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6BCU)) +#define REG_06C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6C0U)) +#define REG_06C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6C4U)) +#define REG_06C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6C8U)) +#define REG_06CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6CCU)) +#define REG_06D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6D0U)) +#define REG_06D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6D4U)) +#define REG_06D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6D8U)) +#define REG_06DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6DCU)) +#define REG_06E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6E0U)) +#define REG_06E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6E4U)) +#define REG_06E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6E8U)) +#define REG_06ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6ECU)) +#define REG_06F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6F0U)) +#define REG_06F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6F4U)) +#define REG_06F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6F8U)) +#define REG_06FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x6FCU)) +#define REG_0700H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x700U)) +#define REG_0704H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x704U)) +#define REG_0708H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x708U)) +#define REG_070CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x70CU)) +#define REG_0710H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x710U)) +#define REG_0714H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x714U)) +#define REG_0718H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x718U)) +#define REG_071CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x71CU)) +#define REG_0720H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x720U)) +#define REG_0724H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x724U)) +#define REG_0728H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x728U)) +#define REG_072CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x72CU)) +#define REG_0730H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x730U)) +#define REG_0734H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x734U)) +#define REG_0738H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x738U)) +#define REG_073CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x73CU)) +#define REG_0740H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x740U)) +#define REG_0744H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x744U)) +#define REG_0748H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x748U)) +#define REG_074CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x74CU)) +#define REG_0750H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x750U)) +#define REG_0754H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x754U)) +#define REG_0758H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x758U)) +#define REG_075CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x75CU)) +#define REG_0760H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x760U)) +#define REG_0764H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x764U)) +#define REG_0768H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x768U)) +#define REG_076CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x76CU)) +#define REG_0770H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x770U)) +#define REG_0774H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x774U)) +#define REG_0778H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x778U)) +#define REG_077CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x77CU)) +#define REG_0780H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x780U)) +#define REG_0784H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x784U)) +#define REG_0788H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x788U)) +#define REG_078CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x78CU)) +#define REG_0790H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x790U)) +#define REG_0794H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x794U)) +#define REG_0798H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x798U)) +#define REG_079CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x79CU)) +#define REG_07A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7A0U)) +#define REG_07A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7A4U)) +#define REG_07A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7A8U)) +#define REG_07ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7ACU)) +#define REG_07B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7B0U)) +#define REG_07B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7B4U)) +#define REG_07B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7B8U)) +#define REG_07BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7BCU)) +#define REG_07C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7C0U)) +#define REG_07C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7C4U)) +#define REG_07C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7C8U)) +#define REG_07CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7CCU)) +#define REG_07D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7D0U)) +#define REG_07D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7D4U)) +#define REG_07D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7D8U)) +#define REG_07DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7DCU)) +#define REG_07E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7E0U)) +#define REG_07E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7E4U)) +#define REG_07E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7E8U)) +#define REG_07ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7ECU)) +#define REG_07F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7F0U)) +#define REG_07F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7F4U)) +#define REG_07F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7F8U)) +#define REG_07FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x7FCU)) +#define REG_0800H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x800U)) +#define REG_0804H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x804U)) +#define REG_0808H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x808U)) +#define REG_080CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x80CU)) +#define REG_0810H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x810U)) +#define REG_0814H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x814U)) +#define REG_0818H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x818U)) +#define REG_081CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x81CU)) +#define REG_0820H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x820U)) +#define REG_0824H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x824U)) +#define REG_0828H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x828U)) +#define REG_082CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x82CU)) +#define REG_0830H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x830U)) +#define REG_0834H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x834U)) +#define REG_0838H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x838U)) +#define REG_083CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x83CU)) +#define REG_0840H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x840U)) +#define REG_0844H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x844U)) +#define REG_0848H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x848U)) +#define REG_084CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x84CU)) +#define REG_0850H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x850U)) +#define REG_0854H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x854U)) +#define REG_0858H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x858U)) +#define REG_085CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x85CU)) +#define REG_0860H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x860U)) +#define REG_0864H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x864U)) +#define REG_0868H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x868U)) +#define REG_086CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x86CU)) +#define REG_0870H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x870U)) +#define REG_0874H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x874U)) +#define REG_0878H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x878U)) +#define REG_087CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x87CU)) +#define REG_0880H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x880U)) +#define REG_0884H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x884U)) +#define REG_0888H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x888U)) +#define REG_088CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x88CU)) +#define REG_0890H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x890U)) +#define REG_0894H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x894U)) +#define REG_0898H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x898U)) +#define REG_089CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x89CU)) +#define REG_08A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8A0U)) +#define REG_08A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8A4U)) +#define REG_08A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8A8U)) +#define REG_08ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8ACU)) +#define REG_08B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8B0U)) +#define REG_08B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8B4U)) +#define REG_08B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8B8U)) +#define REG_08BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8BCU)) +#define REG_08C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8C0U)) +#define REG_08C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8C4U)) +#define REG_08C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8C8U)) +#define REG_08CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8CCU)) +#define REG_08D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8D0U)) +#define REG_08D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8D4U)) +#define REG_08D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8D8U)) +#define REG_08DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8DCU)) +#define REG_08E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8E0U)) +#define REG_08E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8E4U)) +#define REG_08E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8E8U)) +#define REG_08ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8ECU)) +#define REG_08F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8F0U)) +#define REG_08F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8F4U)) +#define REG_08F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8F8U)) +#define REG_08FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x8FCU)) +#define REG_0900H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x900U)) +#define REG_0904H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x904U)) +#define REG_0908H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x908U)) +#define REG_090CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x90CU)) +#define REG_0910H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x910U)) +#define REG_0914H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x914U)) +#define REG_0918H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x918U)) +#define REG_091CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x91CU)) +#define REG_0920H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x920U)) +#define REG_0924H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x924U)) +#define REG_0928H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x928U)) +#define REG_092CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x92CU)) +#define REG_0930H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x930U)) +#define REG_0934H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x934U)) +#define REG_0938H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x938U)) +#define REG_093CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x93CU)) +#define REG_0940H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x940U)) +#define REG_0944H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x944U)) +#define REG_0948H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x948U)) +#define REG_094CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x94CU)) +#define REG_0950H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x950U)) +#define REG_0954H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x954U)) +#define REG_0958H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x958U)) +#define REG_095CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x95CU)) +#define REG_0960H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x960U)) +#define REG_0964H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x964U)) +#define REG_0968H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x968U)) +#define REG_096CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x96CU)) +#define REG_0970H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x970U)) +#define REG_0974H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x974U)) +#define REG_0978H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x978U)) +#define REG_097CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x97CU)) +#define REG_0980H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x980U)) +#define REG_0984H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x984U)) +#define REG_0988H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x988U)) +#define REG_098CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x98CU)) +#define REG_0990H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x990U)) +#define REG_0994H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x994U)) +#define REG_0998H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x998U)) +#define REG_099CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x99CU)) +#define REG_09A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9A0U)) +#define REG_09A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9A4U)) +#define REG_09A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9A8U)) +#define REG_09ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9ACU)) +#define REG_09B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9B0U)) +#define REG_09B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9B4U)) +#define REG_09B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9B8U)) +#define REG_09BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9BCU)) +#define REG_09C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9C0U)) +#define REG_09C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9C4U)) +#define REG_09C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9C8U)) +#define REG_09CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9CCU)) +#define REG_09D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9D0U)) +#define REG_09D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9D4U)) +#define REG_09D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9D8U)) +#define REG_09DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9DCU)) +#define REG_09E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9E0U)) +#define REG_09E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9E4U)) +#define REG_09E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9E8U)) +#define REG_09ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9ECU)) +#define REG_09F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9F0U)) +#define REG_09F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9F4U)) +#define REG_09F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9F8U)) +#define REG_09FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0x9FCU)) +#define REG_0A00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA00U)) +#define REG_0A04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA04U)) +#define REG_0A08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA08U)) +#define REG_0A0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA0CU)) +#define REG_0A10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA10U)) +#define REG_0A14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA14U)) +#define REG_0A18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA18U)) +#define REG_0A1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA1CU)) +#define REG_0A20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA20U)) +#define REG_0A24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA24U)) +#define REG_0A28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA28U)) +#define REG_0A2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA2CU)) +#define REG_0A30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA30U)) +#define REG_0A34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA34U)) +#define REG_0A38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA38U)) +#define REG_0A3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA3CU)) +#define REG_0A40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA40U)) +#define REG_0A44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA44U)) +#define REG_0A48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA48U)) +#define REG_0A4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA4CU)) +#define REG_0A50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA50U)) +#define REG_0A54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA54U)) +#define REG_0A58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA58U)) +#define REG_0A5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA5CU)) +#define REG_0A60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA60U)) +#define REG_0A64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA64U)) +#define REG_0A68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA68U)) +#define REG_0A6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA6CU)) +#define REG_0A70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA70U)) +#define REG_0A74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA74U)) +#define REG_0A78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA78U)) +#define REG_0A7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA7CU)) +#define REG_0A80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA80U)) +#define REG_0A84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA84U)) +#define REG_0A88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA88U)) +#define REG_0A8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA8CU)) +#define REG_0A90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA90U)) +#define REG_0A94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA94U)) +#define REG_0A98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA98U)) +#define REG_0A9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xA9CU)) +#define REG_0AA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAA0U)) +#define REG_0AA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAA4U)) +#define REG_0AA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAA8U)) +#define REG_0AACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAACU)) +#define REG_0AB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAB0U)) +#define REG_0AB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAB4U)) +#define REG_0AB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAB8U)) +#define REG_0ABCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xABCU)) +#define REG_0AC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAC0U)) +#define REG_0AC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAC4U)) +#define REG_0AC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAC8U)) +#define REG_0ACCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xACCU)) +#define REG_0AD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAD0U)) +#define REG_0AD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAD4U)) +#define REG_0AD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAD8U)) +#define REG_0ADCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xADCU)) +#define REG_0AE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAE0U)) +#define REG_0AE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAE4U)) +#define REG_0AE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAE8U)) +#define REG_0AECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAECU)) +#define REG_0AF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAF0U)) +#define REG_0AF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAF4U)) +#define REG_0AF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAF8U)) +#define REG_0AFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xAFCU)) +#define REG_0B00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB00U)) +#define REG_0B04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB04U)) +#define REG_0B08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB08U)) +#define REG_0B0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB0CU)) +#define REG_0B10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB10U)) +#define REG_0B14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB14U)) +#define REG_0B18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB18U)) +#define REG_0B1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB1CU)) +#define REG_0B20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB20U)) +#define REG_0B24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB24U)) +#define REG_0B28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB28U)) +#define REG_0B2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB2CU)) +#define REG_0B30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB30U)) +#define REG_0B34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB34U)) +#define REG_0B38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB38U)) +#define REG_0B3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB3CU)) +#define REG_0B40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB40U)) +#define REG_0B44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB44U)) +#define REG_0B48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB48U)) +#define REG_0B4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB4CU)) +#define REG_0B50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB50U)) +#define REG_0B54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB54U)) +#define REG_0B58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB58U)) +#define REG_0B5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB5CU)) +#define REG_0B60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB60U)) +#define REG_0B64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB64U)) +#define REG_0B68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB68U)) +#define REG_0B6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB6CU)) +#define REG_0B70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB70U)) +#define REG_0B74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB74U)) +#define REG_0B78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB78U)) +#define REG_0B7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB7CU)) +#define REG_0B80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB80U)) +#define REG_0B84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB84U)) +#define REG_0B88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB88U)) +#define REG_0B8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB8CU)) +#define REG_0B90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB90U)) +#define REG_0B94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB94U)) +#define REG_0B98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB98U)) +#define REG_0B9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xB9CU)) +#define REG_0BA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBA0U)) +#define REG_0BA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBA4U)) +#define REG_0BA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBA8U)) +#define REG_0BACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBACU)) +#define REG_0BB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBB0U)) +#define REG_0BB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBB4U)) +#define REG_0BB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBB8U)) +#define REG_0BBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBBCU)) +#define REG_0BC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBC0U)) +#define REG_0BC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBC4U)) +#define REG_0BC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBC8U)) +#define REG_0BCCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBCCU)) +#define REG_0BD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBD0U)) +#define REG_0BD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBD4U)) +#define REG_0BD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBD8U)) +#define REG_0BDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBDCU)) +#define REG_0BE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBE0U)) +#define REG_0BE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBE4U)) +#define REG_0BE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBE8U)) +#define REG_0BECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBECU)) +#define REG_0BF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBF0U)) +#define REG_0BF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBF4U)) +#define REG_0BF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBF8U)) +#define REG_0BFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xBFCU)) +#define REG_0C00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC00U)) +#define REG_0C04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC04U)) +#define REG_0C08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC08U)) +#define REG_0C0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC0CU)) +#define REG_0C10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC10U)) +#define REG_0C14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC14U)) +#define REG_0C18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC18U)) +#define REG_0C1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC1CU)) +#define REG_0C20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC20U)) +#define REG_0C24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC24U)) +#define REG_0C28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC28U)) +#define REG_0C2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC2CU)) +#define REG_0C30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC30U)) +#define REG_0C34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC34U)) +#define REG_0C38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC38U)) +#define REG_0C3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC3CU)) +#define REG_0C40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC40U)) +#define REG_0C44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC44U)) +#define REG_0C48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC48U)) +#define REG_0C4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC4CU)) +#define REG_0C50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC50U)) +#define REG_0C54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC54U)) +#define REG_0C58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC58U)) +#define REG_0C5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC5CU)) +#define REG_0C60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC60U)) +#define REG_0C64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC64U)) +#define REG_0C68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC68U)) +#define REG_0C6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC6CU)) +#define REG_0C70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC70U)) +#define REG_0C74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC74U)) +#define REG_0C78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC78U)) +#define REG_0C7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC7CU)) +#define REG_0C80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC80U)) +#define REG_0C84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC84U)) +#define REG_0C88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC88U)) +#define REG_0C8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC8CU)) +#define REG_0C90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC90U)) +#define REG_0C94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC94U)) +#define REG_0C98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC98U)) +#define REG_0C9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xC9CU)) +#define REG_0CA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCA0U)) +#define REG_0CA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCA4U)) +#define REG_0CA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCA8U)) +#define REG_0CACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCACU)) +#define REG_0CB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCB0U)) +#define REG_0CB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCB4U)) +#define REG_0CB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCB8U)) +#define REG_0CBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCBCU)) +#define REG_0CC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCC0U)) +#define REG_0CC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCC4U)) +#define REG_0CC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCC8U)) +#define REG_0CCCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCCCU)) +#define REG_0CD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCD0U)) +#define REG_0CD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCD4U)) +#define REG_0CD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCD8U)) +#define REG_0CDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCDCU)) +#define REG_0CE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCE0U)) +#define REG_0CE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCE4U)) +#define REG_0CE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCE8U)) +#define REG_0CECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCECU)) +#define REG_0CF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCF0U)) +#define REG_0CF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCF4U)) +#define REG_0CF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCF8U)) +#define REG_0CFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xCFCU)) +#define REG_0D00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD00U)) +#define REG_0D04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD04U)) +#define REG_0D08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD08U)) +#define REG_0D0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD0CU)) +#define REG_0D10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD10U)) +#define REG_0D14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD14U)) +#define REG_0D18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD18U)) +#define REG_0D1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD1CU)) +#define REG_0D20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD20U)) +#define REG_0D24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD24U)) +#define REG_0D28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD28U)) +#define REG_0D2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD2CU)) +#define REG_0D30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD30U)) +#define REG_0D34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD34U)) +#define REG_0D38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD38U)) +#define REG_0D3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD3CU)) +#define REG_0D40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD40U)) +#define REG_0D44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD44U)) +#define REG_0D48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD48U)) +#define REG_0D4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD4CU)) +#define REG_0D50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD50U)) +#define REG_0D54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD54U)) +#define REG_0D58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD58U)) +#define REG_0D5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD5CU)) +#define REG_0D60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD60U)) +#define REG_0D64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD64U)) +#define REG_0D68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD68U)) +#define REG_0D6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD6CU)) +#define REG_0D70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD70U)) +#define REG_0D74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD74U)) +#define REG_0D78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD78U)) +#define REG_0D7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD7CU)) +#define REG_0D80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD80U)) +#define REG_0D84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD84U)) +#define REG_0D88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD88U)) +#define REG_0D8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD8CU)) +#define REG_0D90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD90U)) +#define REG_0D94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD94U)) +#define REG_0D98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD98U)) +#define REG_0D9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xD9CU)) +#define REG_0DA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDA0U)) +#define REG_0DA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDA4U)) +#define REG_0DA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDA8U)) +#define REG_0DACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDACU)) +#define REG_0DB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDB0U)) +#define REG_0DB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDB4U)) +#define REG_0DB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDB8U)) +#define REG_0DBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDBCU)) +#define REG_0DC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDC0U)) +#define REG_0DC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDC4U)) +#define REG_0DC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDC8U)) +#define REG_0DCCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDCCU)) +#define REG_0DD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDD0U)) +#define REG_0DD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDD4U)) +#define REG_0DD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDD8U)) +#define REG_0DDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDDCU)) +#define REG_0DE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDE0U)) +#define REG_0DE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDE4U)) +#define REG_0DE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDE8U)) +#define REG_0DECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDECU)) +#define REG_0DF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDF0U)) +#define REG_0DF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDF4U)) +#define REG_0DF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDF8U)) +#define REG_0DFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xDFCU)) +#define REG_0E00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE00U)) +#define REG_0E04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE04U)) +#define REG_0E08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE08U)) +#define REG_0E0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE0CU)) +#define REG_0E10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE10U)) +#define REG_0E14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE14U)) +#define REG_0E18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE18U)) +#define REG_0E1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE1CU)) +#define REG_0E20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE20U)) +#define REG_0E24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE24U)) +#define REG_0E28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE28U)) +#define REG_0E2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE2CU)) +#define REG_0E30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE30U)) +#define REG_0E34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE34U)) +#define REG_0E38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE38U)) +#define REG_0E3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE3CU)) +#define REG_0E40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE40U)) +#define REG_0E44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE44U)) +#define REG_0E48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE48U)) +#define REG_0E4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE4CU)) +#define REG_0E50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE50U)) +#define REG_0E54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE54U)) +#define REG_0E58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE58U)) +#define REG_0E5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE5CU)) +#define REG_0E60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE60U)) +#define REG_0E64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE64U)) +#define REG_0E68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE68U)) +#define REG_0E6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE6CU)) +#define REG_0E70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE70U)) +#define REG_0E74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE74U)) +#define REG_0E78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE78U)) +#define REG_0E7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE7CU)) +#define REG_0E80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE80U)) +#define REG_0E84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE84U)) +#define REG_0E88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE88U)) +#define REG_0E8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE8CU)) +#define REG_0E90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE90U)) +#define REG_0E94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE94U)) +#define REG_0E98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE98U)) +#define REG_0E9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xE9CU)) +#define REG_0EA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEA0U)) +#define REG_0EA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEA4U)) +#define REG_0EA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEA8U)) +#define REG_0EACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEACU)) +#define REG_0EB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEB0U)) +#define REG_0EB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEB4U)) +#define REG_0EB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEB8U)) +#define REG_0EBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEBCU)) +#define REG_0EC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEC0U)) +#define REG_0EC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEC4U)) +#define REG_0EC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEC8U)) +#define REG_0ECCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xECCU)) +#define REG_0ED0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xED0U)) +#define REG_0ED4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xED4U)) +#define REG_0ED8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xED8U)) +#define REG_0EDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEDCU)) +#define REG_0EE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEE0U)) +#define REG_0EE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEE4U)) +#define REG_0EE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEE8U)) +#define REG_0EECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEECU)) +#define REG_0EF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEF0U)) +#define REG_0EF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEF4U)) +#define REG_0EF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEF8U)) +#define REG_0EFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xEFCU)) +#define REG_0F00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF00U)) +#define REG_0F04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF04U)) +#define REG_0F08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF08U)) +#define REG_0F0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF0CU)) +#define REG_0F10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF10U)) +#define REG_0F14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF14U)) +#define REG_0F18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF18U)) +#define REG_0F1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF1CU)) +#define REG_0F20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF20U)) +#define REG_0F24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF24U)) +#define REG_0F28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF28U)) +#define REG_0F2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF2CU)) +#define REG_0F30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF30U)) +#define REG_0F34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF34U)) +#define REG_0F38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF38U)) +#define REG_0F3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF3CU)) +#define REG_0F40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF40U)) +#define REG_0F44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF44U)) +#define REG_0F48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF48U)) +#define REG_0F4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF4CU)) +#define REG_0F50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF50U)) +#define REG_0F54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF54U)) +#define REG_0F58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF58U)) +#define REG_0F5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF5CU)) +#define REG_0F60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF60U)) +#define REG_0F64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF64U)) +#define REG_0F68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF68U)) +#define REG_0F6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF6CU)) +#define REG_0F70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF70U)) +#define REG_0F74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF74U)) +#define REG_0F78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF78U)) +#define REG_0F7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF7CU)) +#define REG_0F80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF80U)) +#define REG_0F84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF84U)) +#define REG_0F88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF88U)) +#define REG_0F8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF8CU)) +#define REG_0F90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF90U)) +#define REG_0F94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF94U)) +#define REG_0F98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF98U)) +#define REG_0F9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xF9CU)) +#define REG_0FA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFA0U)) +#define REG_0FA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFA4U)) +#define REG_0FA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFA8U)) +#define REG_0FACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFACU)) +#define REG_0FB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFB0U)) +#define REG_0FB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFB4U)) +#define REG_0FB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFB8U)) +#define REG_0FBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFBCU)) +#define REG_0FC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFC0U)) +#define REG_0FC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFC4U)) +#define REG_0FC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFC8U)) +#define REG_0FCCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFCCU)) +#define REG_0FD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFD0U)) +#define REG_0FD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFD4U)) +#define REG_0FD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFD8U)) +#define REG_0FDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFDCU)) +#define REG_0FE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFE0U)) +#define REG_0FE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFE4U)) +#define REG_0FE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFE8U)) +#define REG_0FECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFECU)) +#define REG_0FF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFF0U)) +#define REG_0FF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFF4U)) +#define REG_0FF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFF8U)) +#define REG_0FFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_0000H + 0xFFCU)) +#define REG_1000H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x000U)) +#define REG_1004H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x004U)) +#define REG_1008H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x008U)) +#define REG_100CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x00CU)) +#define REG_1010H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x010U)) +#define REG_1014H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x014U)) +#define REG_1018H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x018U)) +#define REG_101CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x01CU)) +#define REG_1020H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x020U)) +#define REG_1024H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x024U)) +#define REG_1028H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x028U)) +#define REG_102CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x02CU)) +#define REG_1030H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x030U)) +#define REG_1034H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x034U)) +#define REG_1038H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x038U)) +#define REG_103CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x03CU)) +#define REG_1040H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x040U)) +#define REG_1044H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x044U)) +#define REG_1048H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x048U)) +#define REG_104CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x04CU)) +#define REG_1050H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x050U)) +#define REG_1054H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x054U)) +#define REG_1058H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x058U)) +#define REG_105CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x05CU)) +#define REG_1060H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x060U)) +#define REG_1064H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x064U)) +#define REG_1068H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x068U)) +#define REG_106CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x06CU)) +#define REG_1070H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x070U)) +#define REG_1074H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x074U)) +#define REG_1078H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x078U)) +#define REG_107CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x07CU)) +#define REG_1080H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x080U)) +#define REG_1084H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x084U)) +#define REG_1088H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x088U)) +#define REG_108CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x08CU)) +#define REG_1090H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x090U)) +#define REG_1094H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x094U)) +#define REG_1098H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x098U)) +#define REG_109CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x09CU)) +#define REG_10A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0A0U)) +#define REG_10A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0A4U)) +#define REG_10A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0A8U)) +#define REG_10ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0ACU)) +#define REG_10B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0B0U)) +#define REG_10B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0B4U)) +#define REG_10B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0B8U)) +#define REG_10BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0BCU)) +#define REG_10C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0C0U)) +#define REG_10C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0C4U)) +#define REG_10C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0C8U)) +#define REG_10CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0CCU)) +#define REG_10D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0D0U)) +#define REG_10D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0D4U)) +#define REG_10D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0D8U)) +#define REG_10DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0DCU)) +#define REG_10E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0E0U)) +#define REG_10E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0E4U)) +#define REG_10E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0E8U)) +#define REG_10ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0ECU)) +#define REG_10F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0F0U)) +#define REG_10F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0F4U)) +#define REG_10F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0F8U)) +#define REG_10FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x0FCU)) +#define REG_1100H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x100U)) +#define REG_1104H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x104U)) +#define REG_1108H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x108U)) +#define REG_110CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x10CU)) +#define REG_1110H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x110U)) +#define REG_1114H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x114U)) +#define REG_1118H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x118U)) +#define REG_111CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x11CU)) +#define REG_1120H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x120U)) +#define REG_1124H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x124U)) +#define REG_1128H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x128U)) +#define REG_112CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x12CU)) +#define REG_1130H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x130U)) +#define REG_1134H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x134U)) +#define REG_1138H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x138U)) +#define REG_113CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x13CU)) +#define REG_1140H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x140U)) +#define REG_1144H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x144U)) +#define REG_1148H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x148U)) +#define REG_114CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x14CU)) +#define REG_1150H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x150U)) +#define REG_1154H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x154U)) +#define REG_1158H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x158U)) +#define REG_115CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x15CU)) +#define REG_1160H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x160U)) +#define REG_1164H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x164U)) +#define REG_1168H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x168U)) +#define REG_116CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x16CU)) +#define REG_1170H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x170U)) +#define REG_1174H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x174U)) +#define REG_1178H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x178U)) +#define REG_117CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x17CU)) +#define REG_1180H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x180U)) +#define REG_1184H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x184U)) +#define REG_1188H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x188U)) +#define REG_118CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x18CU)) +#define REG_1190H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x190U)) +#define REG_1194H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x194U)) +#define REG_1198H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x198U)) +#define REG_119CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x19CU)) +#define REG_11A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1A0U)) +#define REG_11A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1A4U)) +#define REG_11A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1A8U)) +#define REG_11ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1ACU)) +#define REG_11B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1B0U)) +#define REG_11B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1B4U)) +#define REG_11B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1B8U)) +#define REG_11BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1BCU)) +#define REG_11C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1C0U)) +#define REG_11C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1C4U)) +#define REG_11C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1C8U)) +#define REG_11CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1CCU)) +#define REG_11D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1D0U)) +#define REG_11D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1D4U)) +#define REG_11D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1D8U)) +#define REG_11DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1DCU)) +#define REG_11E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1E0U)) +#define REG_11E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1E4U)) +#define REG_11E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1E8U)) +#define REG_11ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1ECU)) +#define REG_11F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1F0U)) +#define REG_11F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1F4U)) +#define REG_11F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1F8U)) +#define REG_11FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x1FCU)) +#define REG_1200H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x200U)) +#define REG_1204H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x204U)) +#define REG_1208H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x208U)) +#define REG_120CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x20CU)) +#define REG_1210H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x210U)) +#define REG_1214H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x214U)) +#define REG_1218H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x218U)) +#define REG_121CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x21CU)) +#define REG_1220H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x220U)) +#define REG_1224H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x224U)) +#define REG_1228H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x228U)) +#define REG_122CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x22CU)) +#define REG_1230H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x230U)) +#define REG_1234H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x234U)) +#define REG_1238H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x238U)) +#define REG_123CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x23CU)) +#define REG_1240H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x240U)) +#define REG_1244H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x244U)) +#define REG_1248H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x248U)) +#define REG_124CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x24CU)) +#define REG_1250H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x250U)) +#define REG_1254H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x254U)) +#define REG_1258H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x258U)) +#define REG_125CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x25CU)) +#define REG_1260H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x260U)) +#define REG_1264H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x264U)) +#define REG_1268H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x268U)) +#define REG_126CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x26CU)) +#define REG_1270H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x270U)) +#define REG_1274H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x274U)) +#define REG_1278H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x278U)) +#define REG_127CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x27CU)) +#define REG_1280H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x280U)) +#define REG_1284H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x284U)) +#define REG_1288H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x288U)) +#define REG_128CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x28CU)) +#define REG_1290H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x290U)) +#define REG_1294H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x294U)) +#define REG_1298H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x298U)) +#define REG_129CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x29CU)) +#define REG_12A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2A0U)) +#define REG_12A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2A4U)) +#define REG_12A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2A8U)) +#define REG_12ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2ACU)) +#define REG_12B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2B0U)) +#define REG_12B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2B4U)) +#define REG_12B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2B8U)) +#define REG_12BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2BCU)) +#define REG_12C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2C0U)) +#define REG_12C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2C4U)) +#define REG_12C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2C8U)) +#define REG_12CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2CCU)) +#define REG_12D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2D0U)) +#define REG_12D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2D4U)) +#define REG_12D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2D8U)) +#define REG_12DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2DCU)) +#define REG_12E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2E0U)) +#define REG_12E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2E4U)) +#define REG_12E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2E8U)) +#define REG_12ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2ECU)) +#define REG_12F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2F0U)) +#define REG_12F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2F4U)) +#define REG_12F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2F8U)) +#define REG_12FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x2FCU)) +#define REG_1300H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x300U)) +#define REG_1304H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x304U)) +#define REG_1308H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x308U)) +#define REG_130CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x30CU)) +#define REG_1310H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x310U)) +#define REG_1314H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x314U)) +#define REG_1318H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x318U)) +#define REG_131CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x31CU)) +#define REG_1320H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x320U)) +#define REG_1324H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x324U)) +#define REG_1328H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x328U)) +#define REG_132CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x32CU)) +#define REG_1330H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x330U)) +#define REG_1334H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x334U)) +#define REG_1338H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x338U)) +#define REG_133CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x33CU)) +#define REG_1340H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x340U)) +#define REG_1344H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x344U)) +#define REG_1348H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x348U)) +#define REG_134CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x34CU)) +#define REG_1350H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x350U)) +#define REG_1354H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x354U)) +#define REG_1358H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x358U)) +#define REG_135CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x35CU)) +#define REG_1360H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x360U)) +#define REG_1364H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x364U)) +#define REG_1368H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x368U)) +#define REG_136CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x36CU)) +#define REG_1370H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x370U)) +#define REG_1374H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x374U)) +#define REG_1378H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x378U)) +#define REG_137CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x37CU)) +#define REG_1380H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x380U)) +#define REG_1384H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x384U)) +#define REG_1388H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x388U)) +#define REG_138CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x38CU)) +#define REG_1390H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x390U)) +#define REG_1394H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x394U)) +#define REG_1398H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x398U)) +#define REG_139CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x39CU)) +#define REG_13A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3A0U)) +#define REG_13A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3A4U)) +#define REG_13A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3A8U)) +#define REG_13ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3ACU)) +#define REG_13B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3B0U)) +#define REG_13B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3B4U)) +#define REG_13B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3B8U)) +#define REG_13BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3BCU)) +#define REG_13C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3C0U)) +#define REG_13C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3C4U)) +#define REG_13C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3C8U)) +#define REG_13CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3CCU)) +#define REG_13D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3D0U)) +#define REG_13D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3D4U)) +#define REG_13D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3D8U)) +#define REG_13DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3DCU)) +#define REG_13E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3E0U)) +#define REG_13E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3E4U)) +#define REG_13E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3E8U)) +#define REG_13ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3ECU)) +#define REG_13F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3F0U)) +#define REG_13F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3F4U)) +#define REG_13F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3F8U)) +#define REG_13FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x3FCU)) +#define REG_1400H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x400U)) +#define REG_1404H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x404U)) +#define REG_1408H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x408U)) +#define REG_140CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x40CU)) +#define REG_1410H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x410U)) +#define REG_1414H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x414U)) +#define REG_1418H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x418U)) +#define REG_141CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x41CU)) +#define REG_1420H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x420U)) +#define REG_1424H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x424U)) +#define REG_1428H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x428U)) +#define REG_142CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x42CU)) +#define REG_1430H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x430U)) +#define REG_1434H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x434U)) +#define REG_1438H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x438U)) +#define REG_143CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x43CU)) +#define REG_1440H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x440U)) +#define REG_1444H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x444U)) +#define REG_1448H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x448U)) +#define REG_144CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x44CU)) +#define REG_1450H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x450U)) +#define REG_1454H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x454U)) +#define REG_1458H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x458U)) +#define REG_145CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x45CU)) +#define REG_1460H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x460U)) +#define REG_1464H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x464U)) +#define REG_1468H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x468U)) +#define REG_146CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x46CU)) +#define REG_1470H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x470U)) +#define REG_1474H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x474U)) +#define REG_1478H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x478U)) +#define REG_147CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x47CU)) +#define REG_1480H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x480U)) +#define REG_1484H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x484U)) +#define REG_1488H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x488U)) +#define REG_148CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x48CU)) +#define REG_1490H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x490U)) +#define REG_1494H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x494U)) +#define REG_1498H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x498U)) +#define REG_149CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x49CU)) +#define REG_14A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4A0U)) +#define REG_14A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4A4U)) +#define REG_14A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4A8U)) +#define REG_14ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4ACU)) +#define REG_14B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4B0U)) +#define REG_14B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4B4U)) +#define REG_14B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4B8U)) +#define REG_14BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4BCU)) +#define REG_14C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4C0U)) +#define REG_14C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4C4U)) +#define REG_14C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4C8U)) +#define REG_14CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4CCU)) +#define REG_14D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4D0U)) +#define REG_14D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4D4U)) +#define REG_14D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4D8U)) +#define REG_14DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4DCU)) +#define REG_14E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4E0U)) +#define REG_14E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4E4U)) +#define REG_14E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4E8U)) +#define REG_14ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4ECU)) +#define REG_14F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4F0U)) +#define REG_14F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4F4U)) +#define REG_14F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4F8U)) +#define REG_14FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x4FCU)) +#define REG_1500H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x500U)) +#define REG_1504H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x504U)) +#define REG_1508H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x508U)) +#define REG_150CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x50CU)) +#define REG_1510H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x510U)) +#define REG_1514H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x514U)) +#define REG_1518H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x518U)) +#define REG_151CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x51CU)) +#define REG_1520H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x520U)) +#define REG_1524H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x524U)) +#define REG_1528H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x528U)) +#define REG_152CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x52CU)) +#define REG_1530H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x530U)) +#define REG_1534H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x534U)) +#define REG_1538H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x538U)) +#define REG_153CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x53CU)) +#define REG_1540H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x540U)) +#define REG_1544H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x544U)) +#define REG_1548H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x548U)) +#define REG_154CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x54CU)) +#define REG_1550H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x550U)) +#define REG_1554H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x554U)) +#define REG_1558H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x558U)) +#define REG_155CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x55CU)) +#define REG_1560H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x560U)) +#define REG_1564H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x564U)) +#define REG_1568H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x568U)) +#define REG_156CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x56CU)) +#define REG_1570H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x570U)) +#define REG_1574H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x574U)) +#define REG_1578H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x578U)) +#define REG_157CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x57CU)) +#define REG_1580H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x580U)) +#define REG_1584H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x584U)) +#define REG_1588H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x588U)) +#define REG_158CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x58CU)) +#define REG_1590H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x590U)) +#define REG_1594H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x594U)) +#define REG_1598H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x598U)) +#define REG_159CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x59CU)) +#define REG_15A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5A0U)) +#define REG_15A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5A4U)) +#define REG_15A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5A8U)) +#define REG_15ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5ACU)) +#define REG_15B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5B0U)) +#define REG_15B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5B4U)) +#define REG_15B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5B8U)) +#define REG_15BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5BCU)) +#define REG_15C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5C0U)) +#define REG_15C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5C4U)) +#define REG_15C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5C8U)) +#define REG_15CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5CCU)) +#define REG_15D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5D0U)) +#define REG_15D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5D4U)) +#define REG_15D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5D8U)) +#define REG_15DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5DCU)) +#define REG_15E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5E0U)) +#define REG_15E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5E4U)) +#define REG_15E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5E8U)) +#define REG_15ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5ECU)) +#define REG_15F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5F0U)) +#define REG_15F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5F4U)) +#define REG_15F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5F8U)) +#define REG_15FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x5FCU)) +#define REG_1600H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x600U)) +#define REG_1604H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x604U)) +#define REG_1608H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x608U)) +#define REG_160CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x60CU)) +#define REG_1610H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x610U)) +#define REG_1614H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x614U)) +#define REG_1618H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x618U)) +#define REG_161CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x61CU)) +#define REG_1620H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x620U)) +#define REG_1624H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x624U)) +#define REG_1628H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x628U)) +#define REG_162CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x62CU)) +#define REG_1630H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x630U)) +#define REG_1634H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x634U)) +#define REG_1638H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x638U)) +#define REG_163CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x63CU)) +#define REG_1640H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x640U)) +#define REG_1644H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x644U)) +#define REG_1648H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x648U)) +#define REG_164CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x64CU)) +#define REG_1650H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x650U)) +#define REG_1654H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x654U)) +#define REG_1658H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x658U)) +#define REG_165CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x65CU)) +#define REG_1660H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x660U)) +#define REG_1664H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x664U)) +#define REG_1668H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x668U)) +#define REG_166CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x66CU)) +#define REG_1670H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x670U)) +#define REG_1674H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x674U)) +#define REG_1678H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x678U)) +#define REG_167CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x67CU)) +#define REG_1680H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x680U)) +#define REG_1684H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x684U)) +#define REG_1688H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x688U)) +#define REG_168CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x68CU)) +#define REG_1690H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x690U)) +#define REG_1694H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x694U)) +#define REG_1698H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x698U)) +#define REG_169CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x69CU)) +#define REG_16A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6A0U)) +#define REG_16A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6A4U)) +#define REG_16A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6A8U)) +#define REG_16ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6ACU)) +#define REG_16B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6B0U)) +#define REG_16B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6B4U)) +#define REG_16B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6B8U)) +#define REG_16BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6BCU)) +#define REG_16C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6C0U)) +#define REG_16C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6C4U)) +#define REG_16C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6C8U)) +#define REG_16CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6CCU)) +#define REG_16D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6D0U)) +#define REG_16D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6D4U)) +#define REG_16D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6D8U)) +#define REG_16DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6DCU)) +#define REG_16E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6E0U)) +#define REG_16E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6E4U)) +#define REG_16E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6E8U)) +#define REG_16ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6ECU)) +#define REG_16F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6F0U)) +#define REG_16F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6F4U)) +#define REG_16F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6F8U)) +#define REG_16FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x6FCU)) +#define REG_1700H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x700U)) +#define REG_1704H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x704U)) +#define REG_1708H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x708U)) +#define REG_170CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x70CU)) +#define REG_1710H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x710U)) +#define REG_1714H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x714U)) +#define REG_1718H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x718U)) +#define REG_171CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x71CU)) +#define REG_1720H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x720U)) +#define REG_1724H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x724U)) +#define REG_1728H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x728U)) +#define REG_172CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x72CU)) +#define REG_1730H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x730U)) +#define REG_1734H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x734U)) +#define REG_1738H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x738U)) +#define REG_173CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x73CU)) +#define REG_1740H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x740U)) +#define REG_1744H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x744U)) +#define REG_1748H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x748U)) +#define REG_174CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x74CU)) +#define REG_1750H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x750U)) +#define REG_1754H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x754U)) +#define REG_1758H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x758U)) +#define REG_175CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x75CU)) +#define REG_1760H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x760U)) +#define REG_1764H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x764U)) +#define REG_1768H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x768U)) +#define REG_176CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x76CU)) +#define REG_1770H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x770U)) +#define REG_1774H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x774U)) +#define REG_1778H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x778U)) +#define REG_177CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x77CU)) +#define REG_1780H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x780U)) +#define REG_1784H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x784U)) +#define REG_1788H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x788U)) +#define REG_178CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x78CU)) +#define REG_1790H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x790U)) +#define REG_1794H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x794U)) +#define REG_1798H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x798U)) +#define REG_179CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x79CU)) +#define REG_17A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7A0U)) +#define REG_17A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7A4U)) +#define REG_17A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7A8U)) +#define REG_17ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7ACU)) +#define REG_17B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7B0U)) +#define REG_17B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7B4U)) +#define REG_17B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7B8U)) +#define REG_17BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7BCU)) +#define REG_17C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7C0U)) +#define REG_17C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7C4U)) +#define REG_17C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7C8U)) +#define REG_17CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7CCU)) +#define REG_17D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7D0U)) +#define REG_17D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7D4U)) +#define REG_17D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7D8U)) +#define REG_17DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7DCU)) +#define REG_17E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7E0U)) +#define REG_17E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7E4U)) +#define REG_17E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7E8U)) +#define REG_17ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7ECU)) +#define REG_17F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7F0U)) +#define REG_17F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7F4U)) +#define REG_17F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7F8U)) +#define REG_17FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x7FCU)) +#define REG_1800H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x800U)) +#define REG_1804H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x804U)) +#define REG_1808H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x808U)) +#define REG_180CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x80CU)) +#define REG_1810H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x810U)) +#define REG_1814H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x814U)) +#define REG_1818H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x818U)) +#define REG_181CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x81CU)) +#define REG_1820H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x820U)) +#define REG_1824H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x824U)) +#define REG_1828H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x828U)) +#define REG_182CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x82CU)) +#define REG_1830H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x830U)) +#define REG_1834H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x834U)) +#define REG_1838H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x838U)) +#define REG_183CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x83CU)) +#define REG_1840H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x840U)) +#define REG_1844H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x844U)) +#define REG_1848H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x848U)) +#define REG_184CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x84CU)) +#define REG_1850H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x850U)) +#define REG_1854H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x854U)) +#define REG_1858H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x858U)) +#define REG_185CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x85CU)) +#define REG_1860H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x860U)) +#define REG_1864H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x864U)) +#define REG_1868H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x868U)) +#define REG_186CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x86CU)) +#define REG_1870H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x870U)) +#define REG_1874H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x874U)) +#define REG_1878H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x878U)) +#define REG_187CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x87CU)) +#define REG_1880H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x880U)) +#define REG_1884H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x884U)) +#define REG_1888H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x888U)) +#define REG_188CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x88CU)) +#define REG_1890H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x890U)) +#define REG_1894H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x894U)) +#define REG_1898H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x898U)) +#define REG_189CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x89CU)) +#define REG_18A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8A0U)) +#define REG_18A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8A4U)) +#define REG_18A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8A8U)) +#define REG_18ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8ACU)) +#define REG_18B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8B0U)) +#define REG_18B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8B4U)) +#define REG_18B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8B8U)) +#define REG_18BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8BCU)) +#define REG_18C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8C0U)) +#define REG_18C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8C4U)) +#define REG_18C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8C8U)) +#define REG_18CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8CCU)) +#define REG_18D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8D0U)) +#define REG_18D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8D4U)) +#define REG_18D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8D8U)) +#define REG_18DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8DCU)) +#define REG_18E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8E0U)) +#define REG_18E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8E4U)) +#define REG_18E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8E8U)) +#define REG_18ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8ECU)) +#define REG_18F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8F0U)) +#define REG_18F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8F4U)) +#define REG_18F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8F8U)) +#define REG_18FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x8FCU)) +#define REG_1900H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x900U)) +#define REG_1904H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x904U)) +#define REG_1908H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x908U)) +#define REG_190CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x90CU)) +#define REG_1910H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x910U)) +#define REG_1914H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x914U)) +#define REG_1918H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x918U)) +#define REG_191CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x91CU)) +#define REG_1920H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x920U)) +#define REG_1924H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x924U)) +#define REG_1928H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x928U)) +#define REG_192CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x92CU)) +#define REG_1930H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x930U)) +#define REG_1934H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x934U)) +#define REG_1938H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x938U)) +#define REG_193CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x93CU)) +#define REG_1940H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x940U)) +#define REG_1944H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x944U)) +#define REG_1948H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x948U)) +#define REG_194CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x94CU)) +#define REG_1950H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x950U)) +#define REG_1954H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x954U)) +#define REG_1958H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x958U)) +#define REG_195CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x95CU)) +#define REG_1960H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x960U)) +#define REG_1964H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x964U)) +#define REG_1968H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x968U)) +#define REG_196CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x96CU)) +#define REG_1970H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x970U)) +#define REG_1974H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x974U)) +#define REG_1978H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x978U)) +#define REG_197CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x97CU)) +#define REG_1980H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x980U)) +#define REG_1984H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x984U)) +#define REG_1988H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x988U)) +#define REG_198CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x98CU)) +#define REG_1990H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x990U)) +#define REG_1994H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x994U)) +#define REG_1998H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x998U)) +#define REG_199CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x99CU)) +#define REG_19A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9A0U)) +#define REG_19A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9A4U)) +#define REG_19A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9A8U)) +#define REG_19ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9ACU)) +#define REG_19B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9B0U)) +#define REG_19B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9B4U)) +#define REG_19B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9B8U)) +#define REG_19BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9BCU)) +#define REG_19C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9C0U)) +#define REG_19C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9C4U)) +#define REG_19C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9C8U)) +#define REG_19CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9CCU)) +#define REG_19D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9D0U)) +#define REG_19D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9D4U)) +#define REG_19D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9D8U)) +#define REG_19DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9DCU)) +#define REG_19E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9E0U)) +#define REG_19E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9E4U)) +#define REG_19E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9E8U)) +#define REG_19ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9ECU)) +#define REG_19F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9F0U)) +#define REG_19F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9F4U)) +#define REG_19F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9F8U)) +#define REG_19FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0x9FCU)) +#define REG_1A00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA00U)) +#define REG_1A04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA04U)) +#define REG_1A08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA08U)) +#define REG_1A0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA0CU)) +#define REG_1A10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA10U)) +#define REG_1A14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA14U)) +#define REG_1A18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA18U)) +#define REG_1A1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA1CU)) +#define REG_1A20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA20U)) +#define REG_1A24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA24U)) +#define REG_1A28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA28U)) +#define REG_1A2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA2CU)) +#define REG_1A30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA30U)) +#define REG_1A34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA34U)) +#define REG_1A38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA38U)) +#define REG_1A3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA3CU)) +#define REG_1A40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA40U)) +#define REG_1A44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA44U)) +#define REG_1A48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA48U)) +#define REG_1A4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA4CU)) +#define REG_1A50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA50U)) +#define REG_1A54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA54U)) +#define REG_1A58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA58U)) +#define REG_1A5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA5CU)) +#define REG_1A60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA60U)) +#define REG_1A64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA64U)) +#define REG_1A68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA68U)) +#define REG_1A6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA6CU)) +#define REG_1A70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA70U)) +#define REG_1A74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA74U)) +#define REG_1A78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA78U)) +#define REG_1A7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA7CU)) +#define REG_1A80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA80U)) +#define REG_1A84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA84U)) +#define REG_1A88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA88U)) +#define REG_1A8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA8CU)) +#define REG_1A90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA90U)) +#define REG_1A94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA94U)) +#define REG_1A98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA98U)) +#define REG_1A9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xA9CU)) +#define REG_1AA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAA0U)) +#define REG_1AA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAA4U)) +#define REG_1AA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAA8U)) +#define REG_1AACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAACU)) +#define REG_1AB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAB0U)) +#define REG_1AB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAB4U)) +#define REG_1AB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAB8U)) +#define REG_1ABCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xABCU)) +#define REG_1AC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAC0U)) +#define REG_1AC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAC4U)) +#define REG_1AC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAC8U)) +#define REG_1ACCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xACCU)) +#define REG_1AD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAD0U)) +#define REG_1AD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAD4U)) +#define REG_1AD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAD8U)) +#define REG_1ADCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xADCU)) +#define REG_1AE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAE0U)) +#define REG_1AE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAE4U)) +#define REG_1AE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAE8U)) +#define REG_1AECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAECU)) +#define REG_1AF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAF0U)) +#define REG_1AF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAF4U)) +#define REG_1AF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAF8U)) +#define REG_1AFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xAFCU)) +#define REG_1B00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB00U)) +#define REG_1B04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB04U)) +#define REG_1B08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB08U)) +#define REG_1B0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB0CU)) +#define REG_1B10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB10U)) +#define REG_1B14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB14U)) +#define REG_1B18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB18U)) +#define REG_1B1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB1CU)) +#define REG_1B20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB20U)) +#define REG_1B24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB24U)) +#define REG_1B28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB28U)) +#define REG_1B2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB2CU)) +#define REG_1B30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB30U)) +#define REG_1B34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB34U)) +#define REG_1B38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB38U)) +#define REG_1B3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB3CU)) +#define REG_1B40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB40U)) +#define REG_1B44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB44U)) +#define REG_1B48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB48U)) +#define REG_1B4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB4CU)) +#define REG_1B50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB50U)) +#define REG_1B54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB54U)) +#define REG_1B58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB58U)) +#define REG_1B5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB5CU)) +#define REG_1B60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB60U)) +#define REG_1B64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB64U)) +#define REG_1B68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB68U)) +#define REG_1B6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB6CU)) +#define REG_1B70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB70U)) +#define REG_1B74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB74U)) +#define REG_1B78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB78U)) +#define REG_1B7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB7CU)) +#define REG_1B80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB80U)) +#define REG_1B84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB84U)) +#define REG_1B88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB88U)) +#define REG_1B8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB8CU)) +#define REG_1B90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB90U)) +#define REG_1B94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB94U)) +#define REG_1B98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB98U)) +#define REG_1B9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xB9CU)) +#define REG_1BA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBA0U)) +#define REG_1BA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBA4U)) +#define REG_1BA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBA8U)) +#define REG_1BACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBACU)) +#define REG_1BB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBB0U)) +#define REG_1BB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBB4U)) +#define REG_1BB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBB8U)) +#define REG_1BBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBBCU)) +#define REG_1BC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBC0U)) +#define REG_1BC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBC4U)) +#define REG_1BC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBC8U)) +#define REG_1BCCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBCCU)) +#define REG_1BD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBD0U)) +#define REG_1BD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBD4U)) +#define REG_1BD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBD8U)) +#define REG_1BDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBDCU)) +#define REG_1BE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBE0U)) +#define REG_1BE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBE4U)) +#define REG_1BE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBE8U)) +#define REG_1BECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBECU)) +#define REG_1BF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBF0U)) +#define REG_1BF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBF4U)) +#define REG_1BF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBF8U)) +#define REG_1BFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xBFCU)) +#define REG_1C00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC00U)) +#define REG_1C04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC04U)) +#define REG_1C08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC08U)) +#define REG_1C0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC0CU)) +#define REG_1C10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC10U)) +#define REG_1C14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC14U)) +#define REG_1C18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC18U)) +#define REG_1C1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC1CU)) +#define REG_1C20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC20U)) +#define REG_1C24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC24U)) +#define REG_1C28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC28U)) +#define REG_1C2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC2CU)) +#define REG_1C30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC30U)) +#define REG_1C34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC34U)) +#define REG_1C38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC38U)) +#define REG_1C3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC3CU)) +#define REG_1C40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC40U)) +#define REG_1C44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC44U)) +#define REG_1C48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC48U)) +#define REG_1C4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC4CU)) +#define REG_1C50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC50U)) +#define REG_1C54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC54U)) +#define REG_1C58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC58U)) +#define REG_1C5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC5CU)) +#define REG_1C60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC60U)) +#define REG_1C64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC64U)) +#define REG_1C68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC68U)) +#define REG_1C6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC6CU)) +#define REG_1C70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC70U)) +#define REG_1C74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC74U)) +#define REG_1C78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC78U)) +#define REG_1C7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC7CU)) +#define REG_1C80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC80U)) +#define REG_1C84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC84U)) +#define REG_1C88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC88U)) +#define REG_1C8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC8CU)) +#define REG_1C90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC90U)) +#define REG_1C94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC94U)) +#define REG_1C98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC98U)) +#define REG_1C9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xC9CU)) +#define REG_1CA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCA0U)) +#define REG_1CA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCA4U)) +#define REG_1CA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCA8U)) +#define REG_1CACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCACU)) +#define REG_1CB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCB0U)) +#define REG_1CB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCB4U)) +#define REG_1CB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCB8U)) +#define REG_1CBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCBCU)) +#define REG_1CC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCC0U)) +#define REG_1CC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCC4U)) +#define REG_1CC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCC8U)) +#define REG_1CCCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCCCU)) +#define REG_1CD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCD0U)) +#define REG_1CD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCD4U)) +#define REG_1CD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCD8U)) +#define REG_1CDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCDCU)) +#define REG_1CE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCE0U)) +#define REG_1CE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCE4U)) +#define REG_1CE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCE8U)) +#define REG_1CECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCECU)) +#define REG_1CF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCF0U)) +#define REG_1CF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCF4U)) +#define REG_1CF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCF8U)) +#define REG_1CFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xCFCU)) +#define REG_1D00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD00U)) +#define REG_1D04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD04U)) +#define REG_1D08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD08U)) +#define REG_1D0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD0CU)) +#define REG_1D10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD10U)) +#define REG_1D14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD14U)) +#define REG_1D18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD18U)) +#define REG_1D1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD1CU)) +#define REG_1D20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD20U)) +#define REG_1D24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD24U)) +#define REG_1D28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD28U)) +#define REG_1D2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD2CU)) +#define REG_1D30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD30U)) +#define REG_1D34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD34U)) +#define REG_1D38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD38U)) +#define REG_1D3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD3CU)) +#define REG_1D40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD40U)) +#define REG_1D44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD44U)) +#define REG_1D48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD48U)) +#define REG_1D4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD4CU)) +#define REG_1D50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD50U)) +#define REG_1D54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD54U)) +#define REG_1D58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD58U)) +#define REG_1D5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD5CU)) +#define REG_1D60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD60U)) +#define REG_1D64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD64U)) +#define REG_1D68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD68U)) +#define REG_1D6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD6CU)) +#define REG_1D70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD70U)) +#define REG_1D74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD74U)) +#define REG_1D78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD78U)) +#define REG_1D7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD7CU)) +#define REG_1D80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD80U)) +#define REG_1D84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD84U)) +#define REG_1D88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD88U)) +#define REG_1D8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD8CU)) +#define REG_1D90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD90U)) +#define REG_1D94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD94U)) +#define REG_1D98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD98U)) +#define REG_1D9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xD9CU)) +#define REG_1DA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDA0U)) +#define REG_1DA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDA4U)) +#define REG_1DA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDA8U)) +#define REG_1DACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDACU)) +#define REG_1DB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDB0U)) +#define REG_1DB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDB4U)) +#define REG_1DB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDB8U)) +#define REG_1DBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDBCU)) +#define REG_1DC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDC0U)) +#define REG_1DC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDC4U)) +#define REG_1DC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDC8U)) +#define REG_1DCCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDCCU)) +#define REG_1DD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDD0U)) +#define REG_1DD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDD4U)) +#define REG_1DD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDD8U)) +#define REG_1DDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDDCU)) +#define REG_1DE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDE0U)) +#define REG_1DE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDE4U)) +#define REG_1DE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDE8U)) +#define REG_1DECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDECU)) +#define REG_1DF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDF0U)) +#define REG_1DF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDF4U)) +#define REG_1DF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDF8U)) +#define REG_1DFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xDFCU)) +#define REG_1E00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE00U)) +#define REG_1E04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE04U)) +#define REG_1E08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE08U)) +#define REG_1E0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE0CU)) +#define REG_1E10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE10U)) +#define REG_1E14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE14U)) +#define REG_1E18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE18U)) +#define REG_1E1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE1CU)) +#define REG_1E20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE20U)) +#define REG_1E24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE24U)) +#define REG_1E28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE28U)) +#define REG_1E2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE2CU)) +#define REG_1E30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE30U)) +#define REG_1E34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE34U)) +#define REG_1E38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE38U)) +#define REG_1E3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE3CU)) +#define REG_1E40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE40U)) +#define REG_1E44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE44U)) +#define REG_1E48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE48U)) +#define REG_1E4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE4CU)) +#define REG_1E50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE50U)) +#define REG_1E54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE54U)) +#define REG_1E58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE58U)) +#define REG_1E5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE5CU)) +#define REG_1E60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE60U)) +#define REG_1E64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE64U)) +#define REG_1E68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE68U)) +#define REG_1E6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE6CU)) +#define REG_1E70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE70U)) +#define REG_1E74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE74U)) +#define REG_1E78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE78U)) +#define REG_1E7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE7CU)) +#define REG_1E80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE80U)) +#define REG_1E84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE84U)) +#define REG_1E88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE88U)) +#define REG_1E8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE8CU)) +#define REG_1E90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE90U)) +#define REG_1E94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE94U)) +#define REG_1E98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE98U)) +#define REG_1E9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xE9CU)) +#define REG_1EA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEA0U)) +#define REG_1EA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEA4U)) +#define REG_1EA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEA8U)) +#define REG_1EACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEACU)) +#define REG_1EB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEB0U)) +#define REG_1EB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEB4U)) +#define REG_1EB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEB8U)) +#define REG_1EBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEBCU)) +#define REG_1EC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEC0U)) +#define REG_1EC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEC4U)) +#define REG_1EC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEC8U)) +#define REG_1ECCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xECCU)) +#define REG_1ED0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xED0U)) +#define REG_1ED4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xED4U)) +#define REG_1ED8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xED8U)) +#define REG_1EDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEDCU)) +#define REG_1EE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEE0U)) +#define REG_1EE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEE4U)) +#define REG_1EE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEE8U)) +#define REG_1EECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEECU)) +#define REG_1EF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEF0U)) +#define REG_1EF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEF4U)) +#define REG_1EF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEF8U)) +#define REG_1EFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xEFCU)) +#define REG_1F00H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF00U)) +#define REG_1F04H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF04U)) +#define REG_1F08H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF08U)) +#define REG_1F0CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF0CU)) +#define REG_1F10H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF10U)) +#define REG_1F14H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF14U)) +#define REG_1F18H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF18U)) +#define REG_1F1CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF1CU)) +#define REG_1F20H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF20U)) +#define REG_1F24H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF24U)) +#define REG_1F28H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF28U)) +#define REG_1F2CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF2CU)) +#define REG_1F30H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF30U)) +#define REG_1F34H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF34U)) +#define REG_1F38H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF38U)) +#define REG_1F3CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF3CU)) +#define REG_1F40H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF40U)) +#define REG_1F44H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF44U)) +#define REG_1F48H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF48U)) +#define REG_1F4CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF4CU)) +#define REG_1F50H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF50U)) +#define REG_1F54H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF54U)) +#define REG_1F58H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF58U)) +#define REG_1F5CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF5CU)) +#define REG_1F60H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF60U)) +#define REG_1F64H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF64U)) +#define REG_1F68H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF68U)) +#define REG_1F6CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF6CU)) +#define REG_1F70H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF70U)) +#define REG_1F74H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF74U)) +#define REG_1F78H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF78U)) +#define REG_1F7CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF7CU)) +#define REG_1F80H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF80U)) +#define REG_1F84H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF84U)) +#define REG_1F88H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF88U)) +#define REG_1F8CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF8CU)) +#define REG_1F90H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF90U)) +#define REG_1F94H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF94U)) +#define REG_1F98H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF98U)) +#define REG_1F9CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xF9CU)) +#define REG_1FA0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFA0U)) +#define REG_1FA4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFA4U)) +#define REG_1FA8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFA8U)) +#define REG_1FACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFACU)) +#define REG_1FB0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFB0U)) +#define REG_1FB4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFB4U)) +#define REG_1FB8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFB8U)) +#define REG_1FBCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFBCU)) +#define REG_1FC0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFC0U)) +#define REG_1FC4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFC4U)) +#define REG_1FC8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFC8U)) +#define REG_1FCCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFCCU)) +#define REG_1FD0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFD0U)) +#define REG_1FD4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFD4U)) +#define REG_1FD8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFD8U)) +#define REG_1FDCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFDCU)) +#define REG_1FE0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFE0U)) +#define REG_1FE4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFE4U)) +#define REG_1FE8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFE8U)) +#define REG_1FECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFECU)) +#define REG_1FF0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFF0U)) +#define REG_1FF4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFF4U)) +#define REG_1FF8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFF8U)) +#define REG_1FFCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1000H + 0xFFCU)) +#define REG_2000H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x000U)) +#define REG_2004H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x004U)) +#define REG_2008H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x008U)) +#define REG_200CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x00CU)) +#define REG_2010H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x010U)) +#define REG_2014H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x014U)) +#define REG_2018H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x018U)) +#define REG_201CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x01CU)) +#define REG_2020H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x020U)) +#define REG_2024H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x024U)) +#define REG_2028H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x028U)) +#define REG_202CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x02CU)) +#define REG_2030H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x030U)) +#define REG_2034H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x034U)) +#define REG_2038H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x038U)) +#define REG_203CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x03CU)) +#define REG_2040H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x040U)) +#define REG_2044H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x044U)) +#define REG_2048H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x048U)) +#define REG_204CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x04CU)) +#define REG_2050H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x050U)) +#define REG_2054H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x054U)) +#define REG_2058H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x058U)) +#define REG_205CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x05CU)) +#define REG_2060H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x060U)) +#define REG_2064H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x064U)) +#define REG_2068H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x068U)) +#define REG_206CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x06CU)) +#define REG_2070H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x070U)) +#define REG_2074H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x074U)) +#define REG_2078H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x078U)) +#define REG_207CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x07CU)) +#define REG_2080H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x080U)) +#define REG_2084H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x084U)) +#define REG_2088H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x088U)) +#define REG_208CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x08CU)) +#define REG_2090H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x090U)) +#define REG_2094H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x094U)) +#define REG_2098H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x098U)) +#define REG_209CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x09CU)) +#define REG_20A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0A0U)) +#define REG_20A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0A4U)) +#define REG_20A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0A8U)) +#define REG_20ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0ACU)) +#define REG_20B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0B0U)) +#define REG_20B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0B4U)) +#define REG_20B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0B8U)) +#define REG_20BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0BCU)) +#define REG_20C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0C0U)) +#define REG_20C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0C4U)) +#define REG_20C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0C8U)) +#define REG_20CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0CCU)) +#define REG_20D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0D0U)) +#define REG_20D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0D4U)) +#define REG_20D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0D8U)) +#define REG_20DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0DCU)) +#define REG_20E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0E0U)) +#define REG_20E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0E4U)) +#define REG_20E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0E8U)) +#define REG_20ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0ECU)) +#define REG_20F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0F0U)) +#define REG_20F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0F4U)) +#define REG_20F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0F8U)) +#define REG_20FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x0FCU)) +#define REG_2100H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x100U)) +#define REG_2104H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x104U)) +#define REG_2108H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x108U)) +#define REG_210CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x10CU)) +#define REG_2110H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x110U)) +#define REG_2114H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x114U)) +#define REG_2118H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x118U)) +#define REG_211CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x11CU)) +#define REG_2120H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x120U)) +#define REG_2124H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x124U)) +#define REG_2128H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x128U)) +#define REG_212CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x12CU)) +#define REG_2130H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x130U)) +#define REG_2134H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x134U)) +#define REG_2138H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x138U)) +#define REG_213CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x13CU)) +#define REG_2140H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x140U)) +#define REG_2144H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x144U)) +#define REG_2148H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x148U)) +#define REG_214CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x14CU)) +#define REG_2150H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x150U)) +#define REG_2154H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x154U)) +#define REG_2158H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x158U)) +#define REG_215CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x15CU)) +#define REG_2160H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x160U)) +#define REG_2164H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x164U)) +#define REG_2168H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x168U)) +#define REG_216CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x16CU)) +#define REG_2170H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x170U)) +#define REG_2174H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x174U)) +#define REG_2178H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x178U)) +#define REG_217CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x17CU)) +#define REG_2180H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x180U)) +#define REG_2184H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x184U)) +#define REG_2188H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x188U)) +#define REG_218CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x18CU)) +#define REG_2190H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x190U)) +#define REG_2194H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x194U)) +#define REG_2198H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x198U)) +#define REG_219CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x19CU)) +#define REG_21A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1A0U)) +#define REG_21A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1A4U)) +#define REG_21A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1A8U)) +#define REG_21ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1ACU)) +#define REG_21B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1B0U)) +#define REG_21B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1B4U)) +#define REG_21B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1B8U)) +#define REG_21BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1BCU)) +#define REG_21C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1C0U)) +#define REG_21C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1C4U)) +#define REG_21C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1C8U)) +#define REG_21CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1CCU)) +#define REG_21D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1D0U)) +#define REG_21D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1D4U)) +#define REG_21D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1D8U)) +#define REG_21DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1DCU)) +#define REG_21E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1E0U)) +#define REG_21E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1E4U)) +#define REG_21E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1E8U)) +#define REG_21ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1ECU)) +#define REG_21F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1F0U)) +#define REG_21F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1F4U)) +#define REG_21F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1F8U)) +#define REG_21FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x1FCU)) +#define REG_2200H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x200U)) +#define REG_2204H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x204U)) +#define REG_2208H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x208U)) +#define REG_220CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x20CU)) +#define REG_2210H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x210U)) +#define REG_2214H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x214U)) +#define REG_2218H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x218U)) +#define REG_221CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x21CU)) +#define REG_2220H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x220U)) +#define REG_2224H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x224U)) +#define REG_2228H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x228U)) +#define REG_222CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x22CU)) +#define REG_2230H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x230U)) +#define REG_2234H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x234U)) +#define REG_2238H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x238U)) +#define REG_223CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x23CU)) +#define REG_2240H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x240U)) +#define REG_2244H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x244U)) +#define REG_2248H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x248U)) +#define REG_224CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x24CU)) +#define REG_2250H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x250U)) +#define REG_2254H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x254U)) +#define REG_2258H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x258U)) +#define REG_225CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x25CU)) +#define REG_2260H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x260U)) +#define REG_2264H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x264U)) +#define REG_2268H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x268U)) +#define REG_226CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x26CU)) +#define REG_2270H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x270U)) +#define REG_2274H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x274U)) +#define REG_2278H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x278U)) +#define REG_227CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x27CU)) +#define REG_2280H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x280U)) +#define REG_2284H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x284U)) +#define REG_2288H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x288U)) +#define REG_228CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x28CU)) +#define REG_2290H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x290U)) +#define REG_2294H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x294U)) +#define REG_2298H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x298U)) +#define REG_229CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x29CU)) +#define REG_22A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2A0U)) +#define REG_22A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2A4U)) +#define REG_22A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2A8U)) +#define REG_22ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2ACU)) +#define REG_22B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2B0U)) +#define REG_22B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2B4U)) +#define REG_22B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2B8U)) +#define REG_22BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2BCU)) +#define REG_22C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2C0U)) +#define REG_22C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2C4U)) +#define REG_22C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2C8U)) +#define REG_22CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2CCU)) +#define REG_22D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2D0U)) +#define REG_22D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2D4U)) +#define REG_22D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2D8U)) +#define REG_22DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2DCU)) +#define REG_22E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2E0U)) +#define REG_22E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2E4U)) +#define REG_22E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2E8U)) +#define REG_22ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2ECU)) +#define REG_22F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2F0U)) +#define REG_22F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2F4U)) +#define REG_22F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2F8U)) +#define REG_22FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x2FCU)) +#define REG_2300H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x300U)) +#define REG_2304H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x304U)) +#define REG_2308H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x308U)) +#define REG_230CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x30CU)) +#define REG_2310H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x310U)) +#define REG_2314H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x314U)) +#define REG_2318H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x318U)) +#define REG_231CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x31CU)) +#define REG_2320H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x320U)) +#define REG_2324H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x324U)) +#define REG_2328H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x328U)) +#define REG_232CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x32CU)) +#define REG_2330H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x330U)) +#define REG_2334H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x334U)) +#define REG_2338H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x338U)) +#define REG_233CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x33CU)) +#define REG_2340H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x340U)) +#define REG_2344H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x344U)) +#define REG_2348H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x348U)) +#define REG_234CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x34CU)) +#define REG_2350H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x350U)) +#define REG_2354H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x354U)) +#define REG_2358H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x358U)) +#define REG_235CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x35CU)) +#define REG_2360H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x360U)) +#define REG_2364H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x364U)) +#define REG_2368H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x368U)) +#define REG_236CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x36CU)) +#define REG_2370H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x370U)) +#define REG_2374H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x374U)) +#define REG_2378H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x378U)) +#define REG_237CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x37CU)) +#define REG_2380H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x380U)) +#define REG_2384H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x384U)) +#define REG_2388H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x388U)) +#define REG_238CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x38CU)) +#define REG_2390H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x390U)) +#define REG_2394H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x394U)) +#define REG_2398H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x398U)) +#define REG_239CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x39CU)) +#define REG_23A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3A0U)) +#define REG_23A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3A4U)) +#define REG_23A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3A8U)) +#define REG_23ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3ACU)) +#define REG_23B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3B0U)) +#define REG_23B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3B4U)) +#define REG_23B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3B8U)) +#define REG_23BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3BCU)) +#define REG_23C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3C0U)) +#define REG_23C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3C4U)) +#define REG_23C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3C8U)) +#define REG_23CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3CCU)) +#define REG_23D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3D0U)) +#define REG_23D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3D4U)) +#define REG_23D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3D8U)) +#define REG_23DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3DCU)) +#define REG_23E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3E0U)) +#define REG_23E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3E4U)) +#define REG_23E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3E8U)) +#define REG_23ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3ECU)) +#define REG_23F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3F0U)) +#define REG_23F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3F4U)) +#define REG_23F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3F8U)) +#define REG_23FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x3FCU)) +#define REG_2400H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x400U)) +#define REG_2404H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x404U)) +#define REG_2408H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x408U)) +#define REG_240CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x40CU)) +#define REG_2410H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x410U)) +#define REG_2414H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x414U)) +#define REG_2418H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x418U)) +#define REG_241CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x41CU)) +#define REG_2420H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x420U)) +#define REG_2424H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x424U)) +#define REG_2428H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x428U)) +#define REG_242CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x42CU)) +#define REG_2430H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x430U)) +#define REG_2434H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x434U)) +#define REG_2438H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x438U)) +#define REG_243CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x43CU)) +#define REG_2440H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x440U)) +#define REG_2444H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x444U)) +#define REG_2448H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x448U)) +#define REG_244CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x44CU)) +#define REG_2450H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x450U)) +#define REG_2454H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x454U)) +#define REG_2458H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x458U)) +#define REG_245CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x45CU)) +#define REG_2460H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x460U)) +#define REG_2464H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x464U)) +#define REG_2468H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x468U)) +#define REG_246CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x46CU)) +#define REG_2470H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x470U)) +#define REG_2474H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x474U)) +#define REG_2478H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x478U)) +#define REG_247CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x47CU)) +#define REG_2480H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x480U)) +#define REG_2484H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x484U)) +#define REG_2488H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x488U)) +#define REG_248CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x48CU)) +#define REG_2490H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x490U)) +#define REG_2494H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x494U)) +#define REG_2498H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x498U)) +#define REG_249CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x49CU)) +#define REG_24A0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4A0U)) +#define REG_24A4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4A4U)) +#define REG_24A8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4A8U)) +#define REG_24ACH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4ACU)) +#define REG_24B0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4B0U)) +#define REG_24B4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4B4U)) +#define REG_24B8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4B8U)) +#define REG_24BCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4BCU)) +#define REG_24C0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4C0U)) +#define REG_24C4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4C4U)) +#define REG_24C8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4C8U)) +#define REG_24CCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4CCU)) +#define REG_24D0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4D0U)) +#define REG_24D4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4D4U)) +#define REG_24D8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4D8U)) +#define REG_24DCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4DCU)) +#define REG_24E0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4E0U)) +#define REG_24E4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4E4U)) +#define REG_24E8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4E8U)) +#define REG_24ECH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4ECU)) +#define REG_24F0H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4F0U)) +#define REG_24F4H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4F4U)) +#define REG_24F8H (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4F8U)) +#define REG_24FCH (*(volatile uint32_t *) (RSIP_PRV_ADDR_2000H + 0x4FCU)) + +#define RSIP_PRV_ADDR_VAL_0000H (RSIP_PRV_ADDR_BASE + 0x0000U) +#define RSIP_PRV_ADDR_VAL_1000H (RSIP_PRV_ADDR_BASE + 0x1000U) +#define RSIP_PRV_ADDR_VAL_2000H (RSIP_PRV_ADDR_BASE + 0x2000U) +#define RSIP_PRV_ADDR_VAL_1420H (RSIP_PRV_ADDR_BASE + 0x1420U) +#define RSIP_PRV_ADDR_VAL_1440H (RSIP_PRV_ADDR_BASE + 0x1440U) +#define RSIP_PRV_ADDR_VAL_1600H (RSIP_PRV_ADDR_BASE + 0x1600U) + +/* + * Address definition depends on the toolchain for optimization. + * + * GNU Toolchain: variable with const keyword + * - Common + * - REG_0000H-REG_0FFCH: g_rsip_addr_0000h + offset (imm12) + * - if (5U == RSIP_PRV_ADDR_TYPE) + * - REG_1420H-REG_143CH: g_rsip_addr_1420h + offset (imm5) + * - REG_1440H-REG_145CH: g_rsip_addr_1440h + offset (imm5) + * - REG_1600H-REG_161CH: g_rsip_addr_1600h + offset (imm5) + * - REG_1000H-REG_1FFCH: g_rsip_addr_1000h + offset (imm12) (except the above) + * - REG_2000H-REG_24FCH: g_rsip_addr_2000h + offset (imm12) + * + * Other toolchains: #define preprocessor + */ +#if defined(__ARM_ARCH) && defined(__GNUC__) + #define RSIP_PRV_ADDR_0000H g_rsip_addr_0000h +#else + #define RSIP_PRV_ADDR_0000H RSIP_PRV_ADDR_VAL_0000H +#endif + +#if defined(__ARM_ARCH) && defined(__GNUC__) && (5U == RSIP_PRV_ADDR_TYPE) + #define RSIP_PRV_ADDR_1000H g_rsip_addr_1000h + #define RSIP_PRV_ADDR_2000H g_rsip_addr_2000h + #define RSIP_PRV_ADDR_1420H g_rsip_addr_1420h + #define RSIP_PRV_ADDR_1440H g_rsip_addr_1440h + #define RSIP_PRV_ADDR_1600H g_rsip_addr_1600h + + #undef REG_1420H + #undef REG_1424H + #undef REG_1428H + #undef REG_142CH + #undef REG_1430H + #undef REG_1434H + #undef REG_1438H + #undef REG_143CH + #define REG_1420H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1420H + 0x00U)) + #define REG_1424H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1420H + 0x04U)) + #define REG_1428H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1420H + 0x08U)) + #define REG_142CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1420H + 0x0CU)) + #define REG_1430H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1420H + 0x10U)) + #define REG_1434H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1420H + 0x14U)) + #define REG_1438H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1420H + 0x18U)) + #define REG_143CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1420H + 0x1CU)) + + #undef REG_1440H + #undef REG_1444H + #undef REG_1448H + #undef REG_144CH + #undef REG_1450H + #undef REG_1454H + #undef REG_1458H + #undef REG_145CH + #define REG_1440H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1440H + 0x00U)) + #define REG_1444H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1440H + 0x04U)) + #define REG_1448H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1440H + 0x08U)) + #define REG_144CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1440H + 0x0CU)) + #define REG_1450H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1440H + 0x10U)) + #define REG_1454H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1440H + 0x14U)) + #define REG_1458H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1440H + 0x18U)) + #define REG_145CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1440H + 0x1CU)) + + #undef REG_1600H + #undef REG_1604H + #undef REG_1608H + #undef REG_160CH + #undef REG_1610H + #undef REG_1614H + #undef REG_1618H + #undef REG_161CH + #define REG_1600H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1600H + 0x00U)) + #define REG_1604H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1600H + 0x04U)) + #define REG_1608H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1600H + 0x08U)) + #define REG_160CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1600H + 0x0CU)) + #define REG_1610H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1600H + 0x10U)) + #define REG_1614H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1600H + 0x14U)) + #define REG_1618H (*(volatile uint32_t *) (RSIP_PRV_ADDR_1600H + 0x18U)) + #define REG_161CH (*(volatile uint32_t *) (RSIP_PRV_ADDR_1600H + 0x1CU)) + +#else + #define RSIP_PRV_ADDR_1000H RSIP_PRV_ADDR_VAL_1000H + #define RSIP_PRV_ADDR_2000H RSIP_PRV_ADDR_VAL_2000H +#endif /* defined(__ARM_ARCH) && defined(__GNUC__) && (5U == RSIP_PRV_ADDR_TYPE) */ + +/* Register value */ +#define RSIP_PRV_CMD_REG_0018H (0x00CB00CBU) +#define RSIP_PRV_CMD_REG_001CH (0x00CB00CBU) +#define RSIP_PRV_CMD_REG_1424H (0x00CF00CFU) +#define RSIP_PRV_CMD_REG_1428H (0x00CF00CFU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +#if defined(__ARM_ARCH) && defined(__GNUC__) +extern uintptr_t const g_rsip_addr_0000h; +#endif + +#if defined(__ARM_ARCH) && defined(__GNUC__) && (5U == RSIP_PRV_ADDR_TYPE) +extern uintptr_t const g_rsip_addr_1000h; +extern uintptr_t const g_rsip_addr_2000h; + +extern uintptr_t const g_rsip_addr_1420h; +extern uintptr_t const g_rsip_addr_1440h; +extern uintptr_t const g_rsip_addr_1600h; +#endif /* defined(__ARM_ARCH) && defined(__GNUC__) && (5U == RSIP_PRV_ADDR_TYPE) */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +#endif /* R_RSIP_REG_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h new file mode 100644 index 0000000000..6be91534f2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/primitive/r_rsip_util.h @@ -0,0 +1,87 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_UTIL_H +#define R_RSIP_UTIL_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include + +#if defined(__ARM_ARCH) + #include "cmsis_compiler.h" +#else + #error Unsupported architecture. +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* + * Set compiler optimization option for primitive functions. + * GNU Toolchain: "Os" + * IAR Embedded Workbench: "size" (enabled only if default optimization level is "high") + * Other toolchains: no change + */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) && !defined(__llvm__) + #define RSIP_PRV_PRIMITIVE_FUNC __attribute__((optimize("Os"))) +#elif defined(__ICCARM__) + #define RSIP_PRV_PRIMITIVE_FUNC _Pragma("optimize = size") +#else + #define RSIP_PRV_PRIMITIVE_FUNC +#endif + +/* CPU Architecture and endianness */ +#if defined(__ARM_ARCH) + #define RSIP_PRV_ARCH_ARM + #define RSIP_PRV_STATIC_INLINE __STATIC_FORCEINLINE + #define RSIP_PRV_LITTLE_ENDIAN !__ARM_BIG_ENDIAN +#else + #error Unsupported architecture. +#endif + +#if RSIP_PRV_LITTLE_ENDIAN + #define BSWAP_32BIG_C(data) ((((data) & 0xff000000U) >> 24) | (((data) & 0x00ff0000U) >> 8) | \ + (((data) & 0x0000ff00U) << 8) | (((data) & 0x000000ffU) << 24)) +#else + #define BSWAP_32BIG_C(data) (data) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Changes data endianness to big-endian. + * + * bswap_32big(): For other than const variable. This inline function directly uses ISA. + * + * BSWAP_32BIG_C(): For const variable. This macro uses bit shift operation. + * + * @param[in] data 32-bit data + * + * @return big-endian data + **********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint32_t bswap_32big (uint32_t data) +{ +#if RSIP_PRV_LITTLE_ENDIAN && defined(RSIP_PRV_ARCH_ARM) + return __REV(data); +#else + return data; +#endif +} + +#endif /* R_RSIP_UTIL_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c new file mode 100644 index 0000000000..5f51e4ff64 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.c @@ -0,0 +1,1901 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_private.h" +#include "r_rsip_wrapper.h" +#include "r_rsip_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#define RSIP_PRV_FUNC_RANDOM_NUMBER_GENERATE RSIP_PRV_FUNC_NAME_RANDOM_NUMBER_GENERATE + +#if RSIP_CFG_AES_128_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_128 RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_128 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_128 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_128 + #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_128_KEY_WRAP + #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_128_KEY_UNWRAP + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128 RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_128 + #define RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_128 RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_128 + #define RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_128 NULL +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_128 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_128 NULL + #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP NULL + #define RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128 NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_128 NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_128 NULL +#endif + +#if RSIP_CFG_AES_128_ENABLE && RSIP_CFG_AES_ECB_CBC_CTR_ENABLE + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_128 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_128 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_128 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_128 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128_WRAPPED_IV \ + RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_128_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128_WRAPPED_IV \ + RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_128_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_128 + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_128 + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_128 +#else + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_128 NULL +#endif + +#if RSIP_CFG_AES_128_ENABLE && RSIP_CFG_AES_GCM_ENABLE + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_128 + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128_WRAPPED_IV RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_128_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_128 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_128 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128_WRAPPED_IV RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_128_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_128 +#else + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 NULL +#endif + +#if RSIP_CFG_AES_128_ENABLE && RSIP_CFG_AES_CCM_ENABLE + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_128 + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_128 + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_128 + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_128 +#else + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 NULL +#endif + +#if RSIP_CFG_AES_128_ENABLE && RSIP_CFG_AES_CMAC_ENABLE + #define RSIP_PRV_FUNC_AES_CMAC_INIT_128 RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_128 + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_128 RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_128 + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_128 + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_128 RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_128 +#else + #define RSIP_PRV_FUNC_AES_CMAC_INIT_128 NULL + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_128 NULL + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_128 NULL +#endif + +#if RSIP_CFG_AES_192_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_192 RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_192 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_192 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_192 + #define RSIP_PRV_FUNC_RFC3394_AES_192_KEY_WRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_192_KEY_WRAP + #define RSIP_PRV_FUNC_RFC3394_AES_192_KEY_UNWRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_192_KEY_UNWRAP + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_192 RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_192 + #define RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_192 RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_192 + #define RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_192 NULL +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_192 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_192 NULL + #define RSIP_PRV_FUNC_RFC3394_AES_192_KEY_WRAP NULL + #define RSIP_PRV_FUNC_RFC3394_AES_192_KEY_UNWRAP NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_192 NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_192 NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_192 NULL +#endif + +#if RSIP_CFG_AES_192_ENABLE && RSIP_CFG_AES_ECB_CBC_CTR_ENABLE + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_192 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_192 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_192 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_192 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_192 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_192 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_192 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_192 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_192_WRAPPED_IV \ + RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_192_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_192_WRAPPED_IV \ + RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_192_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_192 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_192 + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_192 RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_192 + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_192 RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_192 +#else + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_192 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_192 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_192 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_192 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_192_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_192_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_192 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_192 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_192 NULL +#endif + +#if RSIP_CFG_AES_192_ENABLE && RSIP_CFG_AES_GCM_ENABLE + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_192 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_192 + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_192_WRAPPED_IV RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_192_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_192 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_192 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_192 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_192 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_192 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_192 + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_192 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_192 + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_192 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_192 + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_192_WRAPPED_IV RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_192_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_192 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_192 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_192 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_192 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_192 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_192 + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_192 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_192 +#else + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_192_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_192_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_192 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_192 NULL +#endif + +#if RSIP_CFG_AES_192_ENABLE && RSIP_CFG_AES_CCM_ENABLE + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_192 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_192 + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_192 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_192 + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_192 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_192 + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_192 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_192 + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_192 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_192 + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_192 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_192 +#else + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_192 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_192 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_192 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_192 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_192 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_192 NULL +#endif + +#if RSIP_CFG_AES_192_ENABLE && RSIP_CFG_AES_CMAC_ENABLE + #define RSIP_PRV_FUNC_AES_CMAC_INIT_192 RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_192 + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_192 RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_192 + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_192 RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_192 + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_192 RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_192 +#else + #define RSIP_PRV_FUNC_AES_CMAC_INIT_192 NULL + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_192 NULL + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_192 NULL + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_192 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_256 RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_256 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_256 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_256 + #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_256_KEY_WRAP + #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP RSIP_PRV_FUNC_NAME_RFC3394_AES_256_KEY_UNWRAP + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_256 + #define RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_256 RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_256 + #define RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_256 NULL +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_AES_256 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_256 NULL + #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP NULL + #define RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_256 NULL + #define RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_256 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE && RSIP_CFG_AES_ECB_CBC_CTR_ENABLE + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_256 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_256 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_256 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_256 + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256_WRAPPED_IV \ + RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_256_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256_WRAPPED_IV \ + RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_256_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_256 + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_256 + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_256 +#else + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_CIPHER_FINAL_256 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE && RSIP_CFG_AES_GCM_ENABLE + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_256 + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256_WRAPPED_IV RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_256_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_256 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_256 + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256_WRAPPED_IV RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_256_WRAPPED_IV + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_256 +#else + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256_WRAPPED_IV NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE && RSIP_CFG_AES_CCM_ENABLE + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_256 + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_256 + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_256 + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_256 +#else + #define RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 NULL +#endif + +#if RSIP_CFG_AES_256_ENABLE && RSIP_CFG_AES_CMAC_ENABLE + #define RSIP_PRV_FUNC_AES_CMAC_INIT_256 RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_256 + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_256 RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_256 + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_256 + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_256 RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_256 +#else + #define RSIP_PRV_FUNC_AES_CMAC_INIT_256 NULL + #define RSIP_PRV_FUNC_AES_CMAC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_256 NULL + #define RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_256 NULL +#endif + +#if RSIP_CFG_AES_GCM_ENABLE + #define RSIP_PRV_FUNC_GHASH_COMPUTE RSIP_PRV_FUNC_NAME_GHASH_COMPUTE +#else + #define RSIP_PRV_FUNC_GHASH_COMPUTE NULL +#endif + +#if RSIP_CFG_XTS_AES_128_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128 RSIP_PRV_FUNC_NAME_KEY_GENERATE_XTS_AES_128 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_128 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_XTS_AES_128 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_128 NULL +#endif + +#if RSIP_CFG_XTS_AES_128_ENABLE && RSIP_CFG_AES_XTS_ENABLE + #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_INIT_128 + #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_UPDATE_128 + #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_FINAL_128 + #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_INIT_128 + #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_UPDATE_128 + #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_FINAL_128 +#else + #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 NULL +#endif + +#if RSIP_CFG_XTS_AES_256_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 RSIP_PRV_FUNC_NAME_KEY_GENERATE_XTS_AES_256 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_256 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_XTS_AES_256 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_256 NULL +#endif + +#if RSIP_CFG_XTS_AES_256_ENABLE && RSIP_CFG_AES_XTS_ENABLE + #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_INIT_256 + #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_UPDATE_256 + #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 RSIP_PRV_FUNC_NAME_XTS_AES_ENC_FINAL_256 + #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_INIT_256 + #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_UPDATE_256 + #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 RSIP_PRV_FUNC_NAME_XTS_AES_DEC_FINAL_256 +#else + #define RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256 NULL + #define RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 NULL +#endif + +#if RSIP_CFG_CHACHA20_ENABLE || RSIP_CFG_CHACHA20_POLY1305_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_CHACHA20 RSIP_PRV_FUNC_NAME_KEY_GENERATE_CHACHA20 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_CHACHA20 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_CHACHA20 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_CHACHA20 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_CHACHA20 NULL +#endif + +#if RSIP_CFG_CHACHA20_ENABLE + #define RSIP_PRV_FUNC_CHACHA20_INIT RSIP_PRV_FUNC_NAME_CHACHA20_INIT + #define RSIP_PRV_FUNC_CHACHA20_UPDATE RSIP_PRV_FUNC_NAME_CHACHA20_UPDATE + #define RSIP_PRV_FUNC_CHACHA20_FINAL RSIP_PRV_FUNC_NAME_CHACHA20_FINAL + #define RSIP_PRV_FUNC_CHACHA20_SUSPEND RSIP_PRV_FUNC_NAME_CHACHA20_SUSPEND + #define RSIP_PRV_FUNC_CHACHA20_RESUME RSIP_PRV_FUNC_NAME_CHACHA20_RESUME +#else + #define RSIP_PRV_FUNC_CHACHA20_INIT NULL + #define RSIP_PRV_FUNC_CHACHA20_UPDATE NULL + #define RSIP_PRV_FUNC_CHACHA20_FINAL NULL + #define RSIP_PRV_FUNC_CHACHA20_SUSPEND NULL + #define RSIP_PRV_FUNC_CHACHA20_RESUME NULL +#endif + +#if RSIP_CFG_CHACHA20_POLY1305_ENABLE + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_ENC_INIT RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_ENC_INIT + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_DEC_INIT RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_DEC_INIT + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE_AAD RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE_AAD + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE_TRANSITION RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE_TRANSITION + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_FINAL RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_FINAL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_SUSPEND RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_SUSPEND + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_ENC_RESUME RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_ENC_RESUME + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_DEC_RESUME RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_DEC_RESUME +#else + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_ENC_INIT NULL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_DEC_INIT NULL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE_AAD NULL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE_TRANSITION NULL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE NULL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_FINAL NULL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_SUSPEND NULL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_ENC_RESUME NULL + #define RSIP_PRV_FUNC_CHACHA20_POLY1305_DEC_RESUME NULL +#endif + +#if RSIP_CFG_ECC_SECP256R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP256R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP256R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP256R1 + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_SECP256R1 RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_SECP256R1 + #define RSIP_PRV_FUNC_ECDH_PLAIN_SECP256R1 RSIP_PRV_FUNC_NAME_ECDH_PLAIN_SECP256R1 + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP256R1 RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_SECP256R1 + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP256R1 RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_SECP256R1 + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP256R1 RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_SECP256R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1 NULL + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_SECP256R1 NULL + #define RSIP_PRV_FUNC_ECDH_PLAIN_SECP256R1 NULL + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP256R1 NULL + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP256R1 NULL + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP256R1 NULL +#endif + +#if RSIP_CFG_ECC_SECP384R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP384R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP384R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP384R1 + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_SECP384R1 RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_SECP384R1 + #define RSIP_PRV_FUNC_ECDH_PLAIN_SECP384R1 RSIP_PRV_FUNC_NAME_ECDH_PLAIN_SECP384R1 + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP384R1 RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_SECP384R1 + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP384R1 RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_SECP384R1 + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP384R1 RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_SECP384R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1 NULL + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_SECP384R1 NULL + #define RSIP_PRV_FUNC_ECDH_PLAIN_SECP384R1 NULL + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP384R1 NULL + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP384R1 NULL + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP384R1 NULL +#endif + +#if RSIP_CFG_ECC_SECP521R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP521R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PUBLIC RSIP_PRV_FUNC_NAME_KEY_WRAP_ECC_SECP521R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PRIVATE RSIP_PRV_FUNC_NAME_KEY_WRAP_ECC_SECP521R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP521R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP521R1 + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_SECP521R1 RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_SECP521R1 + #define RSIP_PRV_FUNC_ECDH_PLAIN_SECP521R1 RSIP_PRV_FUNC_NAME_ECDH_PLAIN_SECP521R1 + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP521R1 RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_SECP521R1 + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP521R1 RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_SECP521R1 + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP521R1 RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_SECP521R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1 NULL + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_SECP521R1 NULL + #define RSIP_PRV_FUNC_ECDH_PLAIN_SECP521R1 NULL + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP521R1 NULL + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP521R1 NULL + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP521R1 NULL +#endif + +#if RSIP_CFG_ECC_SECP256K1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256K1 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP256K1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256K1_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256K1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256K1_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256K1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP256K1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP256K1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256K1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP256K1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256K1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256K1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256K1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_SECP256K1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256K1 NULL +#endif + +#if RSIP_CFG_ECC_BRAINPOOLP256R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP256R1 \ + RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_BRAINPOOLP256R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PUBLIC \ + RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PRIVATE \ + RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP256R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_BRAINPOOLP256R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP256R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_BRAINPOOLP256R1 + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP256R1 RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_BRAINPOOLP256R1 + #define RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP256R1 RSIP_PRV_FUNC_NAME_ECDH_PLAIN_BRAINPOOLP256R1 + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP256R1 \ + RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP256R1 + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP256R1 \ + RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP256R1 + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP256R1 \ + RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP256R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP256R1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP256R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP256R1 NULL + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP256R1 NULL + #define RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP256R1 NULL + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP256R1 NULL + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP256R1 NULL + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP256R1 NULL +#endif + +#if RSIP_CFG_ECC_BRAINPOOLP384R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP384R1 \ + RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_BRAINPOOLP384R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PUBLIC \ + RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PRIVATE \ + RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP384R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_BRAINPOOLP384R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP384R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_BRAINPOOLP384R1 + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP384R1 RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_BRAINPOOLP384R1 + #define RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP384R1 RSIP_PRV_FUNC_NAME_ECDH_PLAIN_BRAINPOOLP384R1 + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP384R1 \ + RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP384R1 + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP384R1 \ + RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP384R1 + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP384R1 \ + RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP384R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP384R1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP384R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP384R1 NULL + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP384R1 NULL + #define RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP384R1 NULL + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP384R1 NULL + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP384R1 NULL + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP384R1 NULL +#endif + +#if RSIP_CFG_ECC_BRAINPOOLP512R1_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP512R1 \ + RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_BRAINPOOLP512R1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PUBLIC \ + RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PRIVATE \ + RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PRIVATE + + #define RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP512R1 RSIP_PRV_FUNC_NAME_ECDSA_SIGN_BRAINPOOLP512R1 + #define RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP512R1 RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_BRAINPOOLP512R1 + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP512R1 RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_BRAINPOOLP512R1 + #define RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP512R1 RSIP_PRV_FUNC_NAME_ECDH_PLAIN_BRAINPOOLP512R1 + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP512R1 \ + RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP512R1 + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP512R1 \ + RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP512R1 + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP512R1 \ + RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP512R1 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP512R1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PRIVATE NULL + + #define RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP512R1 NULL + #define RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP512R1 NULL + + #define RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP512R1 NULL + #define RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP512R1 NULL + + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP512R1 NULL + #define RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP512R1 NULL + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP512R1 NULL +#endif + +#if RSIP_CFG_ECC_EDWARDS25519_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_EDWARDS25519 \ + RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_EDWARDS25519 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_EDWARDS25519_PUBLIC \ + RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_EDWARDS25519_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_EDWARDS25519_PRIVATE \ + RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_EDWARDS25519_PRIVATE + + #define RSIP_PRV_FUNC_EDDSA_SIGN_EDWARDS25519 RSIP_PRV_FUNC_NAME_EDDSA_SIGN_EDWARDS25519 + #define RSIP_PRV_FUNC_EDDSA_VERIFY_EDWARDS25519 RSIP_PRV_FUNC_NAME_EDDSA_VERIFY_EDWARDS25519 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_EDWARDS25519 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_EDWARDS25519_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_EDWARDS25519_PRIVATE NULL + + #define RSIP_PRV_FUNC_EDDSA_SIGN_EDWARDS25519 NULL + #define RSIP_PRV_FUNC_EDDSA_VERIFY_EDWARDS25519 NULL +#endif + +#if RSIP_CFG_RSA_1024_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_1024 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_1024 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_1024_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_1024_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_1024_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_1024_PRIVATE + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_1024 RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_1024 + #define RSIP_PRV_FUNC_RSA_DECRYPT_1024 RSIP_PRV_FUNC_NAME_RSA_DECRYPT_1024 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_1024 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_1024_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_1024_PRIVATE NULL + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_1024 NULL + #define RSIP_PRV_FUNC_RSA_DECRYPT_1024 NULL +#endif + +#if RSIP_CFG_RSA_2048_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_2048 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_2048_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_2048_PRIVATE + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_2048 RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_2048 + #define RSIP_PRV_FUNC_RSA_DECRYPT_2048 RSIP_PRV_FUNC_NAME_RSA_DECRYPT_2048 + + #define RSIP_PRV_FUNC_PKI_RSA_VERIFY_INIT_2048 RSIP_PRV_FUNC_NAME_PKI_RSA_VERIFY_INIT_2048 + #define RSIP_PRV_FUNC_PKI_RSA_VERIFY_FINAL_2048 RSIP_PRV_FUNC_NAME_PKI_RSA_VERIFY_FINAL_2048 + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_RSA_2048 RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_RSA_2048 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PRIVATE NULL + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_2048 NULL + #define RSIP_PRV_FUNC_RSA_DECRYPT_2048 NULL + + #define RSIP_PRV_FUNC_PKI_RSA_VERIFY_INIT_2048 NULL + #define RSIP_PRV_FUNC_PKI_RSA_VERIFY_FINAL_2048 NULL + #define RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_RSA_2048 NULL +#endif + +#if RSIP_CFG_RSA_3072_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_3072 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_3072_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_3072_PRIVATE + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_3072 RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_3072 + #define RSIP_PRV_FUNC_RSA_DECRYPT_3072 RSIP_PRV_FUNC_NAME_RSA_DECRYPT_3072 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PRIVATE NULL + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_3072 NULL + #define RSIP_PRV_FUNC_RSA_DECRYPT_3072 NULL +#endif + +#if RSIP_CFG_RSA_4096_ENABLE + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_4096 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PUBLIC RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_4096_PUBLIC + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PRIVATE RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_4096_PRIVATE + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_4096 RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_4096 + #define RSIP_PRV_FUNC_RSA_DECRYPT_4096 RSIP_PRV_FUNC_NAME_RSA_DECRYPT_4096 +#else + #define RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PUBLIC NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PRIVATE NULL + + #define RSIP_PRV_FUNC_RSA_ENCRYPT_4096 NULL + #define RSIP_PRV_FUNC_RSA_DECRYPT_4096 NULL +#endif + +#if 1U == RSIP_PRV_HASH_IP_TYPE + #if RSIP_CFG_SHA224_ENABLE || RSIP_CFG_SHA256_ENABLE + #define RSIP_PRV_FUNC_SHA1SHA2 RSIP_PRV_FUNC_NAME_SHA1SHA2 + #else + #define RSIP_PRV_FUNC_SHA1SHA2 NULL + #endif + + #if RSIP_CFG_HMAC_SHA224_ENABLE + #define RSIP_PRV_FUNC_HMAC_SHA224_INIT RSIP_PRV_FUNC_NAME_HMAC_SHA224_INIT + #define RSIP_PRV_FUNC_HMAC_SHA224_RESUME RSIP_PRV_FUNC_NAME_HMAC_SHA224_RESUME + #define RSIP_PRV_FUNC_HMAC_SHA224_UPDATE RSIP_PRV_FUNC_NAME_HMAC_SHA224_UPDATE + #define RSIP_PRV_FUNC_HMAC_SHA224_SUSPEND RSIP_PRV_FUNC_NAME_HMAC_SHA224_SUSPEND + #define RSIP_PRV_FUNC_HMAC_SHA224_FINAL RSIP_PRV_FUNC_NAME_HMAC_SHA224_FINAL + #else + #define RSIP_PRV_FUNC_HMAC_SHA224_INIT NULL + #define RSIP_PRV_FUNC_HMAC_SHA224_RESUME NULL + #define RSIP_PRV_FUNC_HMAC_SHA224_UPDATE NULL + #define RSIP_PRV_FUNC_HMAC_SHA224_SUSPEND NULL + #define RSIP_PRV_FUNC_HMAC_SHA224_FINAL NULL + #endif + + #if RSIP_CFG_HMAC_SHA256_ENABLE + #define RSIP_PRV_FUNC_HMAC_SHA256_INIT RSIP_PRV_FUNC_NAME_HMAC_SHA256_INIT + #define RSIP_PRV_FUNC_HMAC_SHA256_RESUME RSIP_PRV_FUNC_NAME_HMAC_SHA256_RESUME + #define RSIP_PRV_FUNC_HMAC_SHA256_UPDATE RSIP_PRV_FUNC_NAME_HMAC_SHA256_UPDATE + #define RSIP_PRV_FUNC_HMAC_SHA256_SUSPEND RSIP_PRV_FUNC_NAME_HMAC_SHA256_SUSPEND + #define RSIP_PRV_FUNC_HMAC_SHA256_FINAL RSIP_PRV_FUNC_NAME_HMAC_SHA256_FINAL + #else + #define RSIP_PRV_FUNC_HMAC_SHA256_INIT NULL + #define RSIP_PRV_FUNC_HMAC_SHA256_RESUME NULL + #define RSIP_PRV_FUNC_HMAC_SHA256_UPDATE NULL + #define RSIP_PRV_FUNC_HMAC_SHA256_SUSPEND NULL + #define RSIP_PRV_FUNC_HMAC_SHA256_FINAL NULL + #endif + + #if RSIP_CFG_KDF_SHA256_ENABLE + #define RSIP_PRV_FUNC_KDF_SHA1SHA2 RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2 + #else + #define RSIP_PRV_FUNC_KDF_SHA1SHA2 NULL + #endif + + #if RSIP_CFG_KDF_HMAC_SHA256_ENABLE || RSIP_CFG_KDF_HMAC_SHA384_ENABLE || RSIP_CFG_KDF_HMAC_SHA512_ENABLE + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_INIT RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_INIT + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_RESUME RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_RESUME + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_ENC_UPDATE RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_ENC_UPDATE + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_UPDATE RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_UPDATE + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_SUSPEND RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_SUSPEND + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_FINAL RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_FINAL + #else + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_INIT NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_RESUME NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_UPDATE NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_ENC_UPDATE NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_SUSPEND NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_FINAL NULL + #endif + +#elif (3U == RSIP_PRV_HASH_IP_TYPE) || (5U == RSIP_PRV_HASH_IP_TYPE) + #if RSIP_CFG_SHA1_ENABLE || RSIP_CFG_SHA224_ENABLE || RSIP_CFG_SHA256_ENABLE || RSIP_CFG_SHA384_ENABLE || \ + RSIP_CFG_SHA512_ENABLE || RSIP_CFG_SHA512_224_ENABLE || RSIP_CFG_SHA512_256_ENABLE + #define RSIP_PRV_FUNC_SHA1SHA2_INIT RSIP_PRV_FUNC_NAME_SHA1SHA2_INIT + #define RSIP_PRV_FUNC_SHA1SHA2_RESUME RSIP_PRV_FUNC_NAME_SHA1SHA2_RESUME + #define RSIP_PRV_FUNC_SHA1SHA2_UPDATE RSIP_PRV_FUNC_NAME_SHA1SHA2_UPDATE + #define RSIP_PRV_FUNC_SHA1SHA2_SUSPEND RSIP_PRV_FUNC_NAME_SHA1SHA2_SUSPEND + #define RSIP_PRV_FUNC_SHA1SHA2_FINAL RSIP_PRV_FUNC_NAME_SHA1SHA2_FINAL + #else + #define RSIP_PRV_FUNC_SHA1SHA2_INIT NULL + #define RSIP_PRV_FUNC_SHA1SHA2_RESUME NULL + #define RSIP_PRV_FUNC_SHA1SHA2_UPDATE NULL + #define RSIP_PRV_FUNC_SHA1SHA2_SUSPEND NULL + #define RSIP_PRV_FUNC_SHA1SHA2_FINAL NULL + #endif + + #if RSIP_CFG_SHA3_224_ENABLE || RSIP_CFG_SHA3_256_ENABLE || RSIP_CFG_SHA3_384_ENABLE || RSIP_CFG_SHA3_512_ENABLE + #define RSIP_PRV_FUNC_SHA3_INIT RSIP_PRV_FUNC_NAME_SHA3_INIT + #define RSIP_PRV_FUNC_SHA3_RESUME RSIP_PRV_FUNC_NAME_SHA3_RESUME + #define RSIP_PRV_FUNC_SHA3_UPDATE RSIP_PRV_FUNC_NAME_SHA3_UPDATE + #define RSIP_PRV_FUNC_SHA3_SUSPEND RSIP_PRV_FUNC_NAME_SHA3_SUSPEND + #define RSIP_PRV_FUNC_SHA3_FINAL RSIP_PRV_FUNC_NAME_SHA3_FINAL + #else + #define RSIP_PRV_FUNC_SHA3_INIT NULL + #define RSIP_PRV_FUNC_SHA3_RESUME NULL + #define RSIP_PRV_FUNC_SHA3_UPDATE NULL + #define RSIP_PRV_FUNC_SHA3_SUSPEND NULL + #define RSIP_PRV_FUNC_SHA3_FINAL NULL + #endif + + #if RSIP_CFG_HMAC_SHA1_ENABLE || RSIP_CFG_HMAC_SHA224_ENABLE || RSIP_CFG_HMAC_SHA256_ENABLE || \ + RSIP_CFG_HMAC_SHA384_ENABLE || RSIP_CFG_HMAC_SHA512_ENABLE + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_INIT RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_INIT + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_RESUME RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_RESUME + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_UPDATE RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_UPDATE + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_SUSPEND RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_SUSPEND + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_FINAL RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_FINAL + #else + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_INIT NULL + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_RESUME NULL + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_UPDATE NULL + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_SUSPEND NULL + #define RSIP_PRV_FUNC_HMAC_SHA1SHA2_FINAL NULL + #endif + + #if RSIP_CFG_HMAC_SHA3_224_ENABLE || RSIP_CFG_HMAC_SHA3_256_ENABLE || RSIP_CFG_HMAC_SHA3_384_ENABLE || \ + RSIP_CFG_HMAC_SHA53_512_ENABLE + #define RSIP_PRV_FUNC_HMAC_SHA3_INIT RSIP_PRV_FUNC_NAME_HMAC_SHA3_INIT + #define RSIP_PRV_FUNC_HMAC_SHA3_RESUME RSIP_PRV_FUNC_NAME_HMAC_SHA3_RESUME + #define RSIP_PRV_FUNC_HMAC_SHA3_UPDATE RSIP_PRV_FUNC_NAME_HMAC_SHA3_UPDATE + #define RSIP_PRV_FUNC_HMAC_SHA3_SUSPEND RSIP_PRV_FUNC_NAME_HMAC_SHA3_SUSPEND + #define RSIP_PRV_FUNC_HMAC_SHA3_FINAL RSIP_PRV_FUNC_NAME_HMAC_SHA3_FINAL + #else + #define RSIP_PRV_FUNC_HMAC_SHA3_INIT NULL + #define RSIP_PRV_FUNC_HMAC_SHA3_RESUME NULL + #define RSIP_PRV_FUNC_HMAC_SHA3_UPDATE NULL + #define RSIP_PRV_FUNC_HMAC_SHA3_SUSPEND NULL + #define RSIP_PRV_FUNC_HMAC_SHA3_FINAL NULL + #endif + + #if RSIP_CFG_KDF_SHA256_ENABLE || RSIP_CFG_KDF_SHA384_ENABLE + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_INIT RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_INIT + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_RESUME RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_RESUME + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_UPDATE RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_UPDATE + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_SUSPEND RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_SUSPEND + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_FINAL RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_FINAL + #else + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_INIT NULL + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_RESUME NULL + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_UPDATE NULL + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_SUSPEND NULL + #define RSIP_PRV_FUNC_KDF_SHA1SHA2_FINAL NULL + #endif + + #if RSIP_CFG_KDF_HMAC_SHA256_ENABLE || RSIP_CFG_KDF_HMAC_SHA384_ENABLE || RSIP_CFG_KDF_HMAC_SHA512_ENABLE + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_INIT RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_INIT + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_RESUME RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_RESUME + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_ENC_UPDATE RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_ENC_UPDATE + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_UPDATE RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_UPDATE + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_SUSPEND RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_SUSPEND + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_FINAL RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_FINAL + #else + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_INIT NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_RESUME NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_UPDATE NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_ENC_UPDATE NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_SUSPEND NULL + #define RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_FINAL NULL + #endif +#endif + +#if RSIP_CFG_HMAC_SHA1_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA1 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA1 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA1 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA1 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA1 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA1 NULL +#endif + +#if RSIP_CFG_HMAC_SHA224_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA224 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA224 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA224 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA224 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA224 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA224 NULL +#endif + +#if RSIP_CFG_HMAC_SHA256_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA256 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA256 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA256 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA256 NULL +#endif + +#if RSIP_CFG_HMAC_SHA384_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA384 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA384 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA384 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA384 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA384 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA384 NULL +#endif + +#if RSIP_CFG_HMAC_SHA512_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA512 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA512 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512 NULL +#endif + +#if RSIP_CFG_HMAC_SHA512_224_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512_224 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA512_224 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512_224 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA512_224 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512_224 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512_224 NULL +#endif + +#if RSIP_CFG_HMAC_SHA512_256_ENABLE + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512_256 RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA512_256 + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512_256 RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA512_256 +#else + #define RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512_256 NULL + #define RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512_256 NULL +#endif + +#if RSIP_CFG_KDF_SHA256_ENABLE + #define RSIP_PRV_FUNC_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA256 \ + RSIP_PRV_FUNC_NAME_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA256 + + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_128 \ + RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_128 + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_256 \ + RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_256 + + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_IV_WRAP_SHA256_AES \ + RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_IV_WRAP_SHA256_AES +#else + #define RSIP_PRV_FUNC_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA256 NULL + + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_128 NULL + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_256 NULL + + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_IV_WRAP_SHA256_AES NULL +#endif + +#if RSIP_CFG_KDF_SHA384_ENABLE + #define RSIP_PRV_FUNC_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA384 \ + RSIP_PRV_FUNC_NAME_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA384 + + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_128 \ + RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_128 + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_256 \ + RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_256 + + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_IV_WRAP_SHA384_AES \ + RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_IV_WRAP_SHA384_AES +#else + #define RSIP_PRV_FUNC_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA384 NULL + + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_128 NULL + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_256 NULL + + #define RSIP_PRV_FUNC_KDF_SHA_DERIVED_IV_WRAP_SHA384_AES NULL +#endif + +#if RSIP_CFG_KDF_HMAC_SHA256_ENABLE + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA256 RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_KEY_IMPORT_SHA256 + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA256 RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_MSG_WRAP_SHA256 + #define RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA256 RSIP_PRV_FUNC_NAME_KDF_MAC_KEY_IMPORT_SHA256 + + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_AES_128 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_AES_128 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_AES_256 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_AES_256 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA1 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA1 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA256 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA256 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA384 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA384 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA512 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA512 + + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_AES RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA256_AES + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_TLS12 RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA256_TLS12 + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_TLS13 RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA256_TLS13 +#else + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA256 NULL + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA256 NULL + #define RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA256 NULL + + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_AES_128 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_AES_256 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA1 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA256 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA384 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA512 NULL + + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_AES NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_TLS12 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_TLS13 NULL +#endif + +#if RSIP_CFG_KDF_HMAC_SHA384_ENABLE + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA384 RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_KEY_IMPORT_SHA384 + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA384 RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_MSG_WRAP_SHA384 + #define RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA384 RSIP_PRV_FUNC_NAME_KDF_MAC_KEY_IMPORT_SHA384 + + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_AES_128 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_AES_128 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_AES_256 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_AES_256 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA1 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA1 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA256 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA256 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA384 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA384 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA512 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA512 + + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_AES RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA384_AES + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_TLS12 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA384_TLS12 + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_TLS13 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA384_TLS13 +#else + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA384 NULL + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA384 NULL + #define RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA384 NULL + + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_AES_128 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_AES_256 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA1 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA256 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA384 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA512 NULL + + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_AES NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_TLS12 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_TLS13 NULL +#endif + +#if RSIP_CFG_KDF_HMAC_SHA512_ENABLE + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_SECP521R1 \ + RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_SECP521R1 + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_BRAINPOOLP512R1 \ + RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_BRAINPOOLP512R1 + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA512_SECP521R1 \ + RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_MSG_WRAP_SHA512_SECP521R1 + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA512_BRAINPOOLP512R1 \ + RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_MSG_WRAP_SHA512_BRAINPOOLP512R1 + #define RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA512 RSIP_PRV_FUNC_NAME_KDF_MAC_KEY_IMPORT_SHA512 + + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_AES_128 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_AES_128 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_AES_256 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_AES_256 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA1 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA1 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA256 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA256 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA384 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA384 + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA512 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA512 + + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_AES \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA512_AES + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_TLS12 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA512_TLS12 + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_TLS13 \ + RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA512_TLS13 +#else + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_SECP521R1 NULL + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_BRAINPOOLP512R1 NULL + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA512_SECP521R1 NULL + #define RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA512_BRAINPOOLP512R1 NULL + #define RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA512 NULL + + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_AES_128 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_AES_256 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA1 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA256 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA384 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA512 NULL + + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_AES NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_TLS12 NULL + #define RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_TLS13 NULL +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +const bool g_sha_enabled[RSIP_HASH_TYPE_NUM] = +{ + [RSIP_HASH_TYPE_SHA1] = RSIP_CFG_SHA1_ENABLE, + [RSIP_HASH_TYPE_SHA224] = RSIP_CFG_SHA224_ENABLE, + [RSIP_HASH_TYPE_SHA256] = RSIP_CFG_SHA256_ENABLE, + [RSIP_HASH_TYPE_SHA384] = RSIP_CFG_SHA384_ENABLE, + [RSIP_HASH_TYPE_SHA512] = RSIP_CFG_SHA512_ENABLE, + [RSIP_HASH_TYPE_SHA512_224] = RSIP_CFG_SHA512_224_ENABLE, + [RSIP_HASH_TYPE_SHA512_256] = RSIP_CFG_SHA512_256_ENABLE, + [RSIP_HASH_TYPE_SHA3_224] = RSIP_CFG_SHA3_224_ENABLE, + [RSIP_HASH_TYPE_SHA3_256] = RSIP_CFG_SHA3_256_ENABLE, + [RSIP_HASH_TYPE_SHA3_384] = RSIP_CFG_SHA3_384_ENABLE, + [RSIP_HASH_TYPE_SHA3_512] = RSIP_CFG_SHA3_512_ENABLE, +}; + +const bool g_hmac_enabled[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1] = RSIP_CFG_HMAC_SHA1_ENABLE, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224] = RSIP_CFG_HMAC_SHA224_ENABLE, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = RSIP_CFG_HMAC_SHA256_ENABLE, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = RSIP_CFG_HMAC_SHA384_ENABLE, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = RSIP_CFG_HMAC_SHA512_ENABLE, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_224] = RSIP_CFG_HMAC_SHA512_224_ENABLE, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_256] = RSIP_CFG_HMAC_SHA512_256_ENABLE, +}; + +const bool g_kdf_sha_enabled[RSIP_HASH_TYPE_NUM] = +{ + [RSIP_HASH_TYPE_SHA256] = RSIP_CFG_KDF_SHA256_ENABLE, + [RSIP_HASH_TYPE_SHA384] = RSIP_CFG_KDF_SHA384_ENABLE, +}; + +const bool g_kdf_hmac_enabled[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = RSIP_CFG_KDF_HMAC_SHA256_ENABLE, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = RSIP_CFG_KDF_HMAC_SHA384_ENABLE, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = RSIP_CFG_KDF_HMAC_SHA512_ENABLE, +}; + +const uint32_t g_pki_hash_type[RSIP_HASH_TYPE_NUM] = +{ + [RSIP_HASH_TYPE_SHA1] = RSIP_PRV_PKI_HASH_TYPE_SHA1, + [RSIP_HASH_TYPE_SHA224] = RSIP_PRV_PKI_HASH_TYPE_SHA224, + [RSIP_HASH_TYPE_SHA256] = RSIP_PRV_PKI_HASH_TYPE_SHA256, + [RSIP_HASH_TYPE_SHA384] = RSIP_PRV_PKI_HASH_TYPE_SHA384, + [RSIP_HASH_TYPE_SHA512] = RSIP_PRV_PKI_HASH_TYPE_SHA512, + [RSIP_HASH_TYPE_SHA512_224] = RSIP_PRV_PKI_HASH_TYPE_SHA512_224, + [RSIP_HASH_TYPE_SHA512_256] = RSIP_PRV_PKI_HASH_TYPE_SHA512_256, +}; + +const rsip_func_rng_t gp_func_rng = RSIP_PRV_FUNC_RANDOM_NUMBER_GENERATE; +const rsip_func_ghash_t gp_func_ghash_compute = RSIP_PRV_FUNC_GHASH_COMPUTE; + +const rsip_func_key_generate_t gp_func_key_generate_aes[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_KEY_GENERATE_AES_128, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = RSIP_PRV_FUNC_KEY_GENERATE_AES_192, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_KEY_GENERATE_AES_256 +}; + +const rsip_func_key_generate_t gp_func_key_generate_xts_aes[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_128, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_KEY_GENERATE_XTS_AES_256 +}; + +const rsip_func_key_generate_t gp_func_key_generate_chacha[RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_CHACHA_CHACHA20] = RSIP_PRV_FUNC_KEY_GENERATE_CHACHA20 +}; + +const rsip_func_key_generate_t gp_func_key_generate_hmac[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA1, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA224, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA256, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA384, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_224] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512_224, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_256] = RSIP_PRV_FUNC_KEY_GENERATE_HMAC_SHA512_256 +}; + +const rsip_func_key_pair_generate_t gp_func_key_pair_generate_ecc[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP521R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_SECP256K1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_BRAINPOOLP512R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_ECC_EDWARDS25519 +}; + +const rsip_func_key_pair_generate_t gp_func_key_pair_generate_rsa[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_1024] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_1024, + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_2048, + [RSIP_PRV_KEY_SUBTYPE_RSA_3072] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_3072, + [RSIP_PRV_KEY_SUBTYPE_RSA_4096] = RSIP_PRV_FUNC_KEY_PAIR_GENERATE_RSA_4096 +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_aes[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_128, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_192, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_ENC_KEY_WRAP_AES_256 +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_xts_aes[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_128, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_ENC_KEY_WRAP_XTS_AES_256 +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_chacha[RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_CHACHA_CHACHA20] = RSIP_PRV_FUNC_ENC_KEY_WRAP_CHACHA20 +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_ecc_pub[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256K1_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_EDWARDS25519_PUBLIC +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_ecc_priv[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP521R1_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_SECP256K1_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = RSIP_PRV_FUNC_ENC_KEY_WRAP_ECC_EDWARDS25519_PRIVATE +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_rsa_pub[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_1024] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_1024_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_RSA_3072] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PUBLIC, + [RSIP_PRV_KEY_SUBTYPE_RSA_4096] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PUBLIC +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_rsa_priv[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_1024] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_1024_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_2048_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_RSA_3072] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_3072_PRIVATE, + [RSIP_PRV_KEY_SUBTYPE_RSA_4096] = RSIP_PRV_FUNC_ENC_KEY_WRAP_RSA_4096_PRIVATE +}; + +const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_hmac[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA1, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA224, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA256, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA384, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_224] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512_224, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_256] = RSIP_PRV_FUNC_ENC_KEY_WRAP_HMAC_SHA512_256 +}; + +const rsip_func_rfc3394_key_wrap_t gp_func_rfc3394_key_wrap[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_RFC3394_AES_128_KEY_WRAP, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = NULL, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_RFC3394_AES_256_KEY_WRAP +}; + +const rsip_func_rfc3394_key_unwrap_t gp_func_rfc3394_key_unwrap[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_RFC3394_AES_128_KEY_UNWRAP, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = NULL, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_RFC3394_AES_256_KEY_UNWRAP +}; + +const rsip_func_subset_aes_cipher_t gp_func_aes_cipher[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = + { + .p_init_ecb_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_128, + .p_init_ecb_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_128, + .p_init_cbc_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128, + .p_init_cbc_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128, + .p_init_cbc_enc_wrapped_iv = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_128_WRAPPED_IV, + .p_init_cbc_dec_wrapped_iv = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_128_WRAPPED_IV, + .p_init_ctr = RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_128, + .p_update = RSIP_PRV_FUNC_AES_CIPHER_UPDATE_128, + .p_final = RSIP_PRV_FUNC_AES_CIPHER_FINAL_128, + }, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = + { + .p_init_ecb_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_192, + .p_init_ecb_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_192, + .p_init_cbc_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_192, + .p_init_cbc_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_192, + .p_init_cbc_enc_wrapped_iv = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_192_WRAPPED_IV, + .p_init_cbc_dec_wrapped_iv = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_192_WRAPPED_IV, + .p_init_ctr = RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_192, + .p_update = RSIP_PRV_FUNC_AES_CIPHER_UPDATE_192, + .p_final = RSIP_PRV_FUNC_AES_CIPHER_FINAL_192, + }, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = + { + .p_init_ecb_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_ENC_256, + .p_init_ecb_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_ECB_DEC_256, + .p_init_cbc_enc = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256, + .p_init_cbc_dec = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256, + .p_init_cbc_enc_wrapped_iv = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_ENC_256_WRAPPED_IV, + .p_init_cbc_dec_wrapped_iv = RSIP_PRV_FUNC_AES_CIPHER_INIT_CBC_DEC_256_WRAPPED_IV, + .p_init_ctr = RSIP_PRV_FUNC_AES_CIPHER_INIT_CTR_256, + .p_update = RSIP_PRV_FUNC_AES_CIPHER_UPDATE_256, + .p_final = RSIP_PRV_FUNC_AES_CIPHER_FINAL_256, + } +}; + +const rsip_func_subset_aes_xts_t gp_func_aes_xts_enc[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = + { + .p_init = RSIP_PRV_FUNC_XTS_AES_ENC_INIT_128, + .p_update = RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_128, + .p_final = RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_128 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = + { + .p_init = RSIP_PRV_FUNC_XTS_AES_ENC_INIT_256, + .p_update = RSIP_PRV_FUNC_XTS_AES_ENC_UPDATE_256, + .p_final = RSIP_PRV_FUNC_XTS_AES_ENC_FINAL_256 + } +}; + +const rsip_func_subset_aes_xts_t gp_func_aes_xts_dec[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = + { + .p_init = RSIP_PRV_FUNC_XTS_AES_DEC_INIT_128, + .p_update = RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_128, + .p_final = RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_128 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = + { + .p_init = RSIP_PRV_FUNC_XTS_AES_DEC_INIT_256, + .p_update = RSIP_PRV_FUNC_XTS_AES_DEC_UPDATE_256, + .p_final = RSIP_PRV_FUNC_XTS_AES_DEC_FINAL_256 + } +}; + +const rsip_func_subset_aes_gcm_t gp_func_aes_gcm_enc[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128, + .p_init_wrapped_iv = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_128_WRAPPED_IV, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_128, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_128, + .p_update = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_128, + .p_encryptFinal = RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_128 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_192, + .p_init_wrapped_iv = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_192_WRAPPED_IV, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_192, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_192, + .p_update = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_192, + .p_encryptFinal = RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_192 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256, + .p_init_wrapped_iv = RSIP_PRV_FUNC_AES_GCM_ENC_INIT_256_WRAPPED_IV, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_AAD_256, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_TRANSITION_256, + .p_update = RSIP_PRV_FUNC_AES_GCM_ENC_UPDATE_256, + .p_encryptFinal = RSIP_PRV_FUNC_AES_GCM_ENC_FINAL_256 + } +}; + +const rsip_func_subset_aes_gcm_t gp_func_aes_gcm_dec[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128, + .p_init_wrapped_iv = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_128_WRAPPED_IV, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_128, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_128, + .p_update = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_128, + .p_decryptFinal = RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_128 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_192, + .p_init_wrapped_iv = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_192_WRAPPED_IV, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_192, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_192, + .p_update = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_192, + .p_decryptFinal = RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_192 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = + { + .p_init = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256, + .p_init_wrapped_iv = RSIP_PRV_FUNC_AES_GCM_DEC_INIT_256_WRAPPED_IV, + .p_updateAad = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_AAD_256, + .p_updateTransition = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_TRANSITION_256, + .p_update = RSIP_PRV_FUNC_AES_GCM_DEC_UPDATE_256, + .p_decryptFinal = RSIP_PRV_FUNC_AES_GCM_DEC_FINAL_256 + } +}; + +const rsip_func_subset_aes_ccm_t gp_func_aes_ccm_enc[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = + { + .p_encryptInit = RSIP_PRV_FUNC_AES_CCM_ENC_INIT_128, + .p_update = RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_128, + .p_encryptFinal = RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_128 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = + { + .p_encryptInit = RSIP_PRV_FUNC_AES_CCM_ENC_INIT_192, + .p_update = RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_192, + .p_encryptFinal = RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_192 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = + { + .p_encryptInit = RSIP_PRV_FUNC_AES_CCM_ENC_INIT_256, + .p_update = RSIP_PRV_FUNC_AES_CCM_ENC_UPDATE_256, + .p_encryptFinal = RSIP_PRV_FUNC_AES_CCM_ENC_FINAL_256 + } +}; + +const rsip_func_subset_aes_ccm_t gp_func_aes_ccm_dec[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = + { + .p_decryptInit = RSIP_PRV_FUNC_AES_CCM_DEC_INIT_128, + .p_update = RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_128, + .p_decryptFinal = RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_128 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = + { + .p_decryptInit = RSIP_PRV_FUNC_AES_CCM_DEC_INIT_192, + .p_update = RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_192, + .p_decryptFinal = RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_192 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = + { + .p_decryptInit = RSIP_PRV_FUNC_AES_CCM_DEC_INIT_256, + .p_update = RSIP_PRV_FUNC_AES_CCM_DEC_UPDATE_256, + .p_decryptFinal = RSIP_PRV_FUNC_AES_CCM_DEC_FINAL_256 + } +}; + +const rsip_func_subset_aes_cmac_t gp_func_aes_cmac[RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_AES_128] = + { + .p_init = RSIP_PRV_FUNC_AES_CMAC_INIT_128, + .p_update = RSIP_PRV_FUNC_AES_CMAC_UPDATE_128, + .p_generateFinal = RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_128, + .p_verifyFinal = RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_128 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = + { + .p_init = RSIP_PRV_FUNC_AES_CMAC_INIT_192, + .p_update = RSIP_PRV_FUNC_AES_CMAC_UPDATE_192, + .p_generateFinal = RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_192, + .p_verifyFinal = RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_192 + }, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = + { + .p_init = RSIP_PRV_FUNC_AES_CMAC_INIT_256, + .p_update = RSIP_PRV_FUNC_AES_CMAC_UPDATE_256, + .p_generateFinal = RSIP_PRV_FUNC_AES_CMAC_GENERATE_FINAL_256, + .p_verifyFinal = RSIP_PRV_FUNC_AES_CMAC_VERIFY_FINAL_256 + } +}; + +const rsip_func_subset_chacha20_t gp_func_chacha20[RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_CHACHA_CHACHA20] = + { + .p_init = RSIP_PRV_FUNC_CHACHA20_INIT, + .p_update = RSIP_PRV_FUNC_CHACHA20_UPDATE, + .p_final = RSIP_PRV_FUNC_CHACHA20_FINAL, + .p_suspend = RSIP_PRV_FUNC_CHACHA20_SUSPEND, + .p_resume = RSIP_PRV_FUNC_CHACHA20_RESUME + } +}; + +const rsip_func_subset_chacha20_poly1305_t gp_func_chacha20_poly1305[RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_CHACHA_CHACHA20] = + { + .p_init_enc = RSIP_PRV_FUNC_CHACHA20_POLY1305_ENC_INIT, + .p_init_dec = RSIP_PRV_FUNC_CHACHA20_POLY1305_DEC_INIT, + .p_updateAad = RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE_AAD, + .p_updateTransition = RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE_TRANSITION, + .p_update = RSIP_PRV_FUNC_CHACHA20_POLY1305_UPDATE, + .p_final = RSIP_PRV_FUNC_CHACHA20_POLY1305_FINAL, + .p_suspend = RSIP_PRV_FUNC_CHACHA20_POLY1305_SUSPEND, + .p_resume_enc = RSIP_PRV_FUNC_CHACHA20_POLY1305_ENC_RESUME, + .p_resume_dec = RSIP_PRV_FUNC_CHACHA20_POLY1305_DEC_RESUME + } +}; + +const rsip_func_ecdsa_sign_t gp_func_ecdsa_sign[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP521R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_FUNC_ECDSA_SIGN_SECP256K1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_FUNC_ECDSA_SIGN_BRAINPOOLP512R1 +}; + +const rsip_func_ecdsa_verify_t gp_func_ecdsa_verify[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP521R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_FUNC_ECDSA_VERIFY_SECP256K1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_FUNC_ECDSA_VERIFY_BRAINPOOLP512R1 +}; + +const rsip_func_eddsa_sign_t gp_func_eddsa_sign[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = RSIP_PRV_FUNC_EDDSA_SIGN_EDWARDS25519, +}; + +const rsip_func_eddsa_verify_t gp_func_eddsa_verify[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = RSIP_PRV_FUNC_EDDSA_VERIFY_EDWARDS25519, +}; + +const rsip_func_ecdh_t gp_func_ecdh_wrapped[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_FUNC_ECDH_WRAPPED_SECP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_FUNC_ECDH_WRAPPED_SECP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_FUNC_ECDH_WRAPPED_SECP521R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_FUNC_ECDH_WRAPPED_BRAINPOOLP512R1 +}; + +const rsip_func_ecdh_t gp_func_ecdh_plain[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_FUNC_ECDH_PLAIN_SECP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_FUNC_ECDH_PLAIN_SECP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_FUNC_ECDH_PLAIN_SECP521R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_FUNC_ECDH_PLAIN_BRAINPOOLP512R1 +}; + +const rsip_func_rsa_t gp_func_rsa_public[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_1024] = RSIP_PRV_FUNC_RSA_ENCRYPT_1024, + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_FUNC_RSA_ENCRYPT_2048, + [RSIP_PRV_KEY_SUBTYPE_RSA_3072] = RSIP_PRV_FUNC_RSA_ENCRYPT_3072, + [RSIP_PRV_KEY_SUBTYPE_RSA_4096] = RSIP_PRV_FUNC_RSA_ENCRYPT_4096 +}; + +const rsip_func_rsa_t gp_func_rsa_private[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_1024] = RSIP_PRV_FUNC_RSA_DECRYPT_1024, + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_FUNC_RSA_DECRYPT_2048, + [RSIP_PRV_KEY_SUBTYPE_RSA_3072] = RSIP_PRV_FUNC_RSA_DECRYPT_3072, + [RSIP_PRV_KEY_SUBTYPE_RSA_4096] = RSIP_PRV_FUNC_RSA_DECRYPT_4096 +}; + +#if 1U == RSIP_PRV_HASH_IP_TYPE +const rsip_func_subset_sha_t gp_func_sha1sha2 = RSIP_PRV_FUNC_SHA1SHA2; + +const rsip_func_subset_hmac_t gp_func_hmac_sha1sha2 = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224] = + { + .p_init = RSIP_PRV_FUNC_HMAC_SHA224_INIT, + .p_resume = RSIP_PRV_FUNC_HMAC_SHA224_RESUME, + .p_update = RSIP_PRV_FUNC_HMAC_SHA224_UPDATE, + .p_suspend = RSIP_PRV_FUNC_HMAC_SHA224_SUSPEND, + .p_final = RSIP_PRV_FUNC_HMAC_SHA224_FINAL, + }, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = + { + .p_init = RSIP_PRV_FUNC_HMAC_SHA256_INIT, + .p_resume = RSIP_PRV_FUNC_HMAC_SHA256_RESUME, + .p_update = RSIP_PRV_FUNC_HMAC_SHA256_UPDATE, + .p_suspend = RSIP_PRV_FUNC_HMAC_SHA256_SUSPEND, + .p_final = RSIP_PRV_FUNC_HMAC_SHA256_FINAL, + }, +}; + +const rsip_func_subset_kdf_sha_t gp_func_kdf_sha1sha2 = RSIP_PRV_FUNC_KDF_SHA1SHA2; + +const rsip_func_subset_kdf_hmac_t gp_func_kdf_hmac_sha1sha2 = +{ + .p_init = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_INIT, + .p_resume = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_RESUME, + .p_enc_update = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_ENC_UPDATE, + .p_update = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_UPDATE, + .p_suspend = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_SUSPEND, + .p_final = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_FINAL, +}; + +#elif (3U == RSIP_PRV_HASH_IP_TYPE) || (5U == RSIP_PRV_HASH_IP_TYPE) +const rsip_func_subset_sha_t gp_func_sha1sha2 = +{ + .p_init = RSIP_PRV_FUNC_SHA1SHA2_INIT, + .p_resume = RSIP_PRV_FUNC_SHA1SHA2_RESUME, + .p_update = RSIP_PRV_FUNC_SHA1SHA2_UPDATE, + .p_suspend = RSIP_PRV_FUNC_SHA1SHA2_SUSPEND, + .p_final = RSIP_PRV_FUNC_SHA1SHA2_FINAL, +}; + +const rsip_func_subset_sha_t gp_func_sha3 = +{ + .p_init = RSIP_PRV_FUNC_SHA3_INIT, + .p_resume = RSIP_PRV_FUNC_SHA3_RESUME, + .p_update = RSIP_PRV_FUNC_SHA3_UPDATE, + .p_suspend = RSIP_PRV_FUNC_SHA3_SUSPEND, + .p_final = RSIP_PRV_FUNC_SHA3_FINAL, +}; + +const rsip_func_subset_hmac_t gp_func_hmac_sha1sha2 = +{ + .p_init = RSIP_PRV_FUNC_HMAC_SHA1SHA2_INIT, + .p_resume = RSIP_PRV_FUNC_HMAC_SHA1SHA2_RESUME, + .p_update = RSIP_PRV_FUNC_HMAC_SHA1SHA2_UPDATE, + .p_suspend = RSIP_PRV_FUNC_HMAC_SHA1SHA2_SUSPEND, + .p_final = RSIP_PRV_FUNC_HMAC_SHA1SHA2_FINAL, +}; + +const rsip_func_subset_hmac_t gp_func_hmac_sha3 = +{ + .p_init = RSIP_PRV_FUNC_HMAC_SHA3_INIT, + .p_resume = RSIP_PRV_FUNC_HMAC_SHA3_RESUME, + .p_update = RSIP_PRV_FUNC_HMAC_SHA3_UPDATE, + .p_suspend = RSIP_PRV_FUNC_HMAC_SHA3_SUSPEND, + .p_final = RSIP_PRV_FUNC_HMAC_SHA3_FINAL, +}; + +const rsip_func_subset_kdf_sha_t gp_func_kdf_sha1sha2 = +{ + .p_init = RSIP_PRV_FUNC_KDF_SHA1SHA2_INIT, + .p_resume = RSIP_PRV_FUNC_KDF_SHA1SHA2_RESUME, + .p_update = RSIP_PRV_FUNC_KDF_SHA1SHA2_UPDATE, + .p_suspend = RSIP_PRV_FUNC_KDF_SHA1SHA2_SUSPEND, + .p_final = RSIP_PRV_FUNC_KDF_SHA1SHA2_FINAL, +}; + +const rsip_func_subset_kdf_hmac_t gp_func_kdf_hmac_sha1sha2 = +{ + .p_init = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_INIT, + .p_resume = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_RESUME, + .p_enc_update = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_ENC_UPDATE, + .p_update = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_UPDATE, + .p_suspend = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_SUSPEND, + .p_final = RSIP_PRV_FUNC_KDF_HMAC_SHA1SHA2_FINAL, +}; +#endif /* RSIP_PRV_HASH_IP_TYPE */ + +const rsip_func_subset_pki_ecdsa_verify_t gp_func_pki_ecdsa_verify[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = + { + .p_init = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP256R1, + .p_final = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP256R1 + }, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = + { + .p_init = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP384R1, + .p_final = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP384R1 + }, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = + { + .p_init = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_SECP521R1, + .p_final = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_SECP521R1 + }, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = + { + .p_init = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP256R1, + .p_final = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP256R1 + }, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = + { + .p_init = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP384R1, + .p_final = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP384R1 + }, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = + { + .p_init = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP512R1, + .p_final = RSIP_PRV_FUNC_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP512R1 + }, +}; + +const rsip_func_subset_pki_rsa_verify_t gp_func_pki_rsa_verify[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = + { + .p_init = RSIP_PRV_FUNC_PKI_RSA_VERIFY_INIT_2048, + .p_final = RSIP_PRV_FUNC_PKI_RSA_VERIFY_FINAL_2048 + } +}; + +const rsip_func_pki_cert_key_import_t gp_func_pki_cert_key_import_ecc[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_SECP521R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP256R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP384R1, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP512R1 +}; + +const rsip_func_pki_cert_key_import_t gp_func_pki_cert_key_import_rsa[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_FUNC_PKI_CERT_KEY_IMPORT_RSA_2048 +}; + +const rsip_func_kdf_ecdh_secret_msg_wrap_t gp_func_kdf_sha_ecdh_secret_msg_wrap[RSIP_PRV_DKM_SUBTYPE_SHA_NUM] = +{ + [RSIP_PRV_DKM_SUBTYPE_SHA_256] = RSIP_PRV_FUNC_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA256, + [RSIP_PRV_DKM_SUBTYPE_SHA_384] = RSIP_PRV_FUNC_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA384, +}; + +const rsip_func_kdf_derived_key_import_t gp_func_kdf_sha_derived_key_import_aes[RSIP_PRV_DKM_SUBTYPE_SHA_NUM][ + RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_DKM_SUBTYPE_SHA_256][RSIP_PRV_KEY_SUBTYPE_AES_128] = + RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_128, + [RSIP_PRV_DKM_SUBTYPE_SHA_256][RSIP_PRV_KEY_SUBTYPE_AES_256] = + RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_256, + [RSIP_PRV_DKM_SUBTYPE_SHA_384][RSIP_PRV_KEY_SUBTYPE_AES_128] = + RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_128, + [RSIP_PRV_DKM_SUBTYPE_SHA_384][RSIP_PRV_KEY_SUBTYPE_AES_256] = + RSIP_PRV_FUNC_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_256, +}; + +const rsip_func_kdf_derived_iv_wrap_t gp_func_kdf_sha_derived_iv_wrap[RSIP_PRV_DKM_SUBTYPE_SHA_NUM][2] = +{ + [RSIP_PRV_DKM_SUBTYPE_SHA_256][RSIP_INITIAL_VECTOR_TYPE_AES_16_BYTE] = + RSIP_PRV_FUNC_KDF_SHA_DERIVED_IV_WRAP_SHA256_AES, + [RSIP_PRV_DKM_SUBTYPE_SHA_384][RSIP_INITIAL_VECTOR_TYPE_AES_16_BYTE] = + RSIP_PRV_FUNC_KDF_SHA_DERIVED_IV_WRAP_SHA384_AES, +}; + +const rsip_func_kdf_ecdh_secret_key_import_t gp_func_kdf_hmac_ecdh_secret_key_import[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM][ + RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA256, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA256, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA384, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA384, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_SECP521R1, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_BRAINPOOLP512R1 +}; + +const rsip_func_kdf_ecdh_secret_msg_wrap_t gp_func_kdf_hmac_ecdh_secret_msg_wrap[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM][ + RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA256, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA256, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA384, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA384, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA512_SECP521R1, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = + RSIP_PRV_FUNC_KDF_ECDH_SECRET_MSG_WRAP_SHA512_BRAINPOOLP512R1 +}; +const rsip_func_kdf_dkm_key_import_t gp_func_kdf_hmac_dkm_key_import[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA256, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA384, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = RSIP_PRV_FUNC_KDF_MAC_KEY_IMPORT_SHA512 +}; + +const rsip_func_kdf_derived_key_import_t gp_func_kdf_hmac_derived_key_import_aes[RSIP_PRV_DKM_SUBTYPE_HMAC_NUM][ + RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_AES_128] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_AES_128, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_AES_256] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_AES_256, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_AES_128] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_AES_128, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_AES_256] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_AES_256, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_AES_128] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_AES_128, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_AES_256] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_AES_256 +}; + +const rsip_func_kdf_derived_key_import_t gp_func_kdf_hmac_derived_key_import_hmac[RSIP_PRV_DKM_SUBTYPE_HMAC_NUM][ + RSIP_PRV_KEY_SUBTYPE_HMAC_NUM] = +{ + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA1, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA256, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA384, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA512, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA1, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA256, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA384, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA512, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA1, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA256, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA384, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = + RSIP_PRV_FUNC_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA512, +}; + +const rsip_func_kdf_derived_iv_wrap_t gp_func_kdf_hmac_derived_iv_wrap[RSIP_PRV_DKM_SUBTYPE_HMAC_NUM][3] = +{ + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_INITIAL_VECTOR_TYPE_AES_16_BYTE] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_AES, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_INITIAL_VECTOR_TYPE_AES_TLS12_AEAD] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_TLS12, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256][RSIP_INITIAL_VECTOR_TYPE_AES_TLS13_AEAD] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA256_TLS13, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_INITIAL_VECTOR_TYPE_AES_16_BYTE] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_AES, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_INITIAL_VECTOR_TYPE_AES_TLS12_AEAD] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_TLS12, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384][RSIP_INITIAL_VECTOR_TYPE_AES_TLS13_AEAD] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA384_TLS13, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_INITIAL_VECTOR_TYPE_AES_16_BYTE] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_AES, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_INITIAL_VECTOR_TYPE_AES_TLS12_AEAD] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_TLS12, + [RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512][RSIP_INITIAL_VECTOR_TYPE_AES_TLS13_AEAD] = + RSIP_PRV_FUNC_KDF_DERIVED_IV_WRAP_SHA512_TLS13 +}; + +const rsip_func_otf_t gp_func_otf[RSIP_OTF_CHANNEL_NUM][RSIP_PRV_KEY_SUBTYPE_AES_NUM] = +{ + [RSIP_OTF_CHANNEL_0] = + { + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_128, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_192, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_OTF_CHANNEL_0_AES_256 + }, + [RSIP_OTF_CHANNEL_1] = + { + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_128, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_192, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_OTF_CHANNEL_1_AES_256, + }, + [RSIP_OTF_CHANNEL_2] = + { + [RSIP_PRV_KEY_SUBTYPE_AES_128] = RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_128, + [RSIP_PRV_KEY_SUBTYPE_AES_192] = RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_192, + [RSIP_PRV_KEY_SUBTYPE_AES_256] = RSIP_PRV_FUNC_OTF_CHANNEL_2_AES_256, + } +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.h new file mode 100644 index 0000000000..68b76833d1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private.h @@ -0,0 +1,961 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_PRIVATE_H +#define R_RSIP_PRIVATE_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip.h" +#include "r_rsip_err.h" +#include "r_rsip_util.h" +#include "r_rsip_addr.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* + * Private/Primitive functions + */ + +/* Random number generation */ +typedef rsip_ret_t (* rsip_func_rng_t)(uint32_t OutData_Text[]); + +/* Key generation */ +typedef rsip_ret_t (* rsip_func_key_generate_t)(uint32_t OutData_KeyIndex[]); + +/* Key pair generation */ +typedef rsip_ret_t (* rsip_func_key_pair_generate_t)(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); + +/* Encrypted key wrap */ +typedef rsip_ret_t (* rsip_func_encrypted_key_wrap_t)(const uint32_t InData_IV[], const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); + +/* RFC3394 Key Wrap */ +typedef rsip_ret_t (* rsip_func_rfc3394_key_wrap_t)(const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_WrappedKeyIndex[], uint32_t OutData_Text[], + uint32_t KEY_INDEX_SIZE, uint32_t WRAPPED_KEY_SIZE); + +/* RFC3394 Key Unwrap */ +typedef rsip_ret_t (* rsip_func_rfc3394_key_unwrap_t)(const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_Text[], uint32_t OutData_KeyIndex[], + uint32_t WRAPPED_KEY_SIZE, uint32_t KEY_INDEX_SIZE); + +/* AES-ECB/CBC/CTR */ +typedef rsip_ret_t (* rsip_func_aes_cipher_init_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); + +/* AES-GCM */ +typedef rsip_ret_t (* rsip_func_aes_gcm_init_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +typedef rsip_ret_t (* rsip_func_ghash_t)(const uint32_t InData_HV[], const uint32_t InData_IV[], + const uint32_t InData_Text[], uint32_t OutData_DataT[], uint32_t MAX_CNT); + +/* ChaCha20-Poly1305 */ +typedef rsip_ret_t (* rsip_func_chacha_poly_init_t)(const uint32_t * InData_KeyIndex, const uint32_t * InData_Nonce, + const uint32_t * InData_TextLen, const uint32_t * InData_DataALen); +typedef rsip_ret_t (* rsip_func_chacha_poly_resume_t)(const uint32_t * InData_KeyIndex, const uint32_t * InData_Nonce, + const uint32_t * InData_State); + +/* ECDSA */ +typedef rsip_ret_t (* rsip_func_ecdsa_sign_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]); +typedef rsip_ret_t (* rsip_func_ecdsa_verify_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); + +/* EdDSA */ +typedef rsip_ret_t (* rsip_func_eddsa_sign_t)(const uint32_t InData_PrivKeyIndex[], const uint32_t InData_PubKeyIndex[], + const uint32_t InData_Msg[], const uint64_t InData_MsgLen, + uint32_t OutData_Signature[]); + +typedef rsip_ret_t (* rsip_func_eddsa_verify_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_Msg[], + const uint64_t InData_MsgLen, const uint32_t InData_Signature[]); + +/* ECDH */ +typedef rsip_ret_t (* rsip_func_ecdh_t)(const uint32_t InData_PubKey[], const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +/* RSA */ +typedef rsip_ret_t (* rsip_func_rsa_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], + uint32_t OutData_Text[]); + +/* PKI */ +typedef rsip_ret_t (* rsip_func_pki_cert_key_import_t)(const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]); + +/* KDF */ +typedef rsip_ret_t (* rsip_func_kdf_ecdh_secret_key_import_t)(const uint32_t InData_EncSecret[], + uint32_t OutData_KeyIndex[]); +typedef rsip_ret_t (* rsip_func_kdf_ecdh_secret_msg_wrap_t)(const uint32_t InData_EncSecret[], + uint32_t OutData_EncMsg[]); +typedef rsip_ret_t (* rsip_func_kdf_dkm_key_import_t)(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]); +typedef rsip_ret_t (* rsip_func_kdf_derived_key_import_t)(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]); +typedef rsip_ret_t (* rsip_func_kdf_derived_iv_wrap_t)(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_EncIV[]); + +/* OTF */ +typedef rsip_ret_t (* rsip_func_otf_t)(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); + +/* + * Private/Primitive function subsets + */ + +/* AES-ECB/CBC/CTR */ +typedef struct st_rsip_func_subset_aes_cipher +{ + rsip_func_aes_cipher_init_t p_init_ecb_enc; + rsip_func_aes_cipher_init_t p_init_ecb_dec; + rsip_func_aes_cipher_init_t p_init_cbc_enc; + rsip_func_aes_cipher_init_t p_init_cbc_dec; + rsip_func_aes_cipher_init_t p_init_cbc_enc_wrapped_iv; + rsip_func_aes_cipher_init_t p_init_cbc_dec_wrapped_iv; + rsip_func_aes_cipher_init_t p_init_ctr; + void (* p_update)(const uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + rsip_ret_t (* p_final)(); +} rsip_func_subset_aes_cipher_t; + +/* AES-XTS */ +typedef struct st_rsip_func_subset_aes_xts +{ + rsip_ret_t (* p_init)(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); + void (* p_update)(const uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + rsip_ret_t (* p_final)(const uint32_t * InData_TextBitLen, const uint32_t * InData_Text, uint32_t * OutData_Text); +} rsip_func_subset_aes_xts_t; + +/* AES-GCM */ +typedef struct st_rsip_func_subset_aes_gcm +{ + rsip_func_aes_gcm_init_t p_init; + rsip_func_aes_gcm_init_t p_init_wrapped_iv; + void (* p_updateAad)(const uint32_t * InData_DataA, uint32_t MAX_CNT); + void (* p_updateTransition)(); + void (* p_update)(const uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + rsip_ret_t (* p_encryptFinal)(const uint32_t * InData_Text, const uint32_t * InData_DataALen, + const uint32_t * InData_TextLen, uint32_t * OutData_Text, uint32_t * OutData_DataT); + rsip_ret_t (* p_decryptFinal)(const uint32_t * InData_Text, const uint32_t * InData_DataT, + const uint32_t * InData_DataALen, const uint32_t * InData_TextLen, + const uint32_t * InData_DataTLen, + uint32_t * OutData_Text); +} rsip_func_subset_aes_gcm_t; + +/* AES-CCM */ +typedef struct st_rsip_func_subset_aes_ccm +{ + rsip_ret_t (* p_encryptInit)(const uint32_t * InData_KeyIndex, const uint32_t * InData_TextLen, + const uint32_t * InData_IV, const uint32_t * InData_Header, uint32_t Header_Len); + rsip_ret_t (* p_decryptInit)(const uint32_t * InData_KeyIndex, const uint32_t * InData_TextLen, + const uint32_t * InData_MACLength, const uint32_t * InData_IV, + const uint32_t * InData_Header, uint32_t Header_Len); + void (* p_update)(const uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + rsip_ret_t (* p_encryptFinal)(const uint32_t * InData_Text, const uint32_t * InData_TextLen, + uint32_t * OutData_Text, uint32_t * OutData_MAC); + rsip_ret_t (* p_decryptFinal)(const uint32_t * InData_Text, const uint32_t * InData_TextLen, + const uint32_t * InData_MAC, const uint32_t * InData_MACLength, + uint32_t * OutData_Text); +} rsip_func_subset_aes_ccm_t; + +/* AES-CMAC */ +typedef struct st_rsip_func_subset_aes_cmac +{ + rsip_ret_t (* p_init)(const uint32_t * InData_KeyIndex); + void (* p_update)(const uint32_t * InData_Text, uint32_t MAX_CNT); + rsip_ret_t (* p_generateFinal)(const uint32_t * InData_Text, uint32_t * OutData_DataT, const uint32_t all_msg_len); + rsip_ret_t (* p_verifyFinal)(const uint32_t * InData_Text, const uint32_t * InData_DataT, + const uint32_t * InData_DataTLen, const uint32_t all_msg_len); +} rsip_func_subset_aes_cmac_t; + +/* ChaCha20 */ +typedef struct st_rsip_func_subset_chacha20 +{ + rsip_ret_t (* p_init)(const uint32_t * InData_KeyIndex, const uint32_t * InData_Ctr, const uint32_t * InData_Nonce, + const uint32_t * InData_TextLen); + void (* p_update)(const uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + rsip_ret_t (* p_final)(const uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + rsip_ret_t (* p_suspend)(uint32_t * OutData_State); + rsip_ret_t (* p_resume)(const uint32_t * InData_KeyIndex, const uint32_t * InData_Nonce, + const uint32_t * InData_State); +} rsip_func_subset_chacha20_t; + +/* ChaCha20-Poly1305 */ +typedef struct st_rsip_func_subset_chacha20_poly1305 +{ + rsip_func_chacha_poly_init_t p_init_enc; + rsip_func_chacha_poly_init_t p_init_dec; + void (* p_updateAad)(const uint32_t * InData_DataA, uint32_t MAX_CNT); + void (* p_updateTransition)(); + void (* p_update)(const uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + rsip_ret_t (* p_final)(const uint32_t * InData_Text, const uint32_t * InData_DataT, uint32_t * OutData_Text, + uint32_t * OutData_DataT, uint32_t MAX_CNT); + rsip_ret_t (* p_suspend)(uint32_t * OutData_State); + rsip_func_chacha_poly_resume_t p_resume_enc; + rsip_func_chacha_poly_resume_t p_resume_dec; +} rsip_func_subset_chacha20_poly1305_t; + +/* SHA */ +#if 1U == RSIP_PRV_HASH_IP_TYPE +typedef rsip_ret_t (* rsip_func_subset_sha_t)(const uint32_t InData_InitVal[], const uint32_t InData_PaddedMsg[], + uint32_t MAX_CNT, uint32_t OutData_MsgDigest[]); +#elif (3U == RSIP_PRV_HASH_IP_TYPE) || (5U == RSIP_PRV_HASH_IP_TYPE) +typedef struct st_rsip_func_subset_sha +{ + rsip_ret_t (* p_init)(const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]); + rsip_ret_t (* p_resume)(const uint32_t InData_HashType[], const uint32_t InData_State[]); + rsip_ret_t (* p_update)(const uint32_t InData_Msg[], uint32_t MAX_CNT); + rsip_ret_t (* p_suspend)(uint32_t OutData_State[]); + rsip_ret_t (* p_final)(const uint32_t InData_Msg[], uint32_t MAX_CNT, uint32_t OutData_MsgDigest[]); +} rsip_func_subset_sha_t; +#endif + +/* HMAC */ +#if 1U == RSIP_PRV_HASH_IP_TYPE +typedef struct st_rsip_func_subset_hmac +{ + rsip_ret_t (* p_init)(const uint32_t InData_KeyIndex[]); + rsip_ret_t (* p_resume)(const uint32_t InData_KeyIndex[], const uint32_t InData_State[]); + void (* p_update)(const uint32_t InData_PaddedMsg[], uint32_t MAX_CNT); + rsip_ret_t (* p_suspend)(uint32_t OutData_State[]); + rsip_ret_t (* p_final)(const uint32_t InData_Cmd[], const uint32_t InData_MAC[], const uint32_t InData_length[], + uint32_t OutData_MAC[]); +} rsip_func_subset_hmac_t[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 + 1]; +#elif (3U == RSIP_PRV_HASH_IP_TYPE) || (5U == RSIP_PRV_HASH_IP_TYPE) +typedef struct st_rsip_func_subset_hmac +{ + rsip_ret_t (* p_init)(const uint32_t InData_KeyIndex[], const uint32_t InData_HashType[], + const uint32_t InData_MsgLen[], uint32_t KEY_INDEX_SIZE); + rsip_ret_t (* p_resume)(const uint32_t InData_KeyIndex[], const uint32_t InData_HashType[], + const uint32_t InData_State[], uint32_t KEY_INDEX_SIZE); + rsip_ret_t (* p_update)(const uint32_t InData_Msg[], uint32_t MAX_CNT); + rsip_ret_t (* p_suspend)(uint32_t OutData_State[]); + rsip_ret_t (* p_final)(const uint32_t InData_Cmd[], const uint32_t InData_Msg[], const uint32_t InData_MAC[], + const uint32_t InData_length[], uint32_t MAX_CNT, uint32_t OutData_MAC[]); +} rsip_func_subset_hmac_t; +#endif + +/* KDF SHA */ +#if 1U == RSIP_PRV_HASH_IP_TYPE +typedef rsip_ret_t (* rsip_func_subset_kdf_sha_t)(const uint32_t InData_InitVal[], const uint32_t InData_Msg1[], + const uint32_t InData_Msg1Length[], const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], + const uint32_t InData_Msg2[], const uint32_t InData_Msg2Length[], + const uint32_t InData_OutDataType[], + uint32_t OutData_MsgDigest[], uint32_t OutData_KDFInfo[]); +#elif (3U == RSIP_PRV_HASH_IP_TYPE) || (5U == RSIP_PRV_HASH_IP_TYPE) +typedef struct st_rsip_func_subset_kdf_sha +{ + rsip_ret_t (* p_init)(const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]); + rsip_ret_t (* p_resume)(const uint32_t InData_HashType[], const uint32_t InData_State[]); + rsip_ret_t (* p_update)(const uint32_t InData_Msg1[], const uint32_t InData_Msg1Length[], + const uint32_t InData_EncMsg[], const uint32_t InData_EncMsgLength[], + const uint32_t InData_Msg2[], + const uint32_t InData_Msg2Length[]); + rsip_ret_t (* p_suspend)(uint32_t OutData_State[]); + rsip_ret_t (* p_final)(const uint32_t InData_Msg1[], const uint32_t InData_Msg1Length[], + const uint32_t InData_EncMsg[], const uint32_t InData_EncMsgLength[], + const uint32_t InData_Msg2[], + const uint32_t InData_Msg2Length[], uint32_t OutData_KDFInfo[]); +} rsip_func_subset_kdf_sha_t; +#endif + +/* KDF HMAC */ +#if 1U == RSIP_PRV_HASH_IP_TYPE +typedef struct st_rsip_func_subset_kdf_hmac +{ + rsip_ret_t (* p_init)(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); + rsip_ret_t (* p_resume)(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], + const uint32_t InData_State[]); + rsip_ret_t (* p_enc_update)(const uint32_t InData_EncMsg[], const uint32_t InData_EncMsgLength[]); + rsip_ret_t (* p_update)(const uint32_t InData_Msg[], uint32_t MAX_CNT); + rsip_ret_t (* p_suspend)(uint32_t OutData_State[]); + rsip_ret_t (* p_final)(const uint32_t InData_Msg[], const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], uint32_t OutData_KDFInfo[], uint32_t MAX_CNT); +} rsip_func_subset_kdf_hmac_t; +#elif (3U == RSIP_PRV_HASH_IP_TYPE) || (5U == RSIP_PRV_HASH_IP_TYPE) +typedef struct st_rsip_func_subset_kdf_hmac +{ + rsip_ret_t (* p_init)(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]); + rsip_ret_t (* p_resume)(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], const uint32_t InData_State[]); + rsip_ret_t (* p_enc_update)(const uint32_t InData_EncMsg[], const uint32_t InData_EncMsgLength[]); + rsip_ret_t (* p_update)(const uint32_t InData_Msg[], uint32_t MAX_CNT); + rsip_ret_t (* p_suspend)(uint32_t OutData_State[]); + rsip_ret_t (* p_final)(const uint32_t InData_Msg[], const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], uint32_t OutData_KDFInfo[], uint32_t MAX_CNT); +} rsip_func_subset_kdf_hmac_t; +#endif + +/* PKI */ +typedef struct st_rsip_func_subset_pki_ecdsa_verify +{ + rsip_ret_t (* p_init)(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); + rsip_ret_t (* p_final)(uint32_t OutData_EncCertificateInfo[]); +} rsip_func_subset_pki_ecdsa_verify_t; + +typedef struct st_rsip_func_subsetpki_rsa_verify +{ + rsip_ret_t (* p_init)(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); + rsip_ret_t (* p_final)(const uint32_t InData_SignatureType[], const uint32_t InData_HashType[], + const uint32_t InData_MsgDgst[], const uint32_t InData_Salt[], + const uint32_t InData_SaltLength[], + uint32_t OutData_EncCertificateInfo[]); +} rsip_func_subset_pki_rsa_verify_t; + +/** Parsed key type */ +typedef struct st_rsip_key_type_extend +{ + uint8_t alg; ///< Key algorithm + uint8_t subtype; ///< Key subtype +} rsip_key_type_extend_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern const bool g_sha_enabled[RSIP_HASH_TYPE_NUM]; +extern const bool g_hmac_enabled[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM]; +extern const bool g_kdf_sha_enabled[RSIP_HASH_TYPE_NUM]; +extern const bool g_kdf_hmac_enabled[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM]; + +extern const uint32_t g_pki_hash_type[RSIP_HASH_TYPE_NUM]; + +extern const rsip_func_key_generate_t gp_func_key_generate_aes[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_key_generate_t gp_func_key_generate_xts_aes[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_key_generate_t gp_func_key_generate_chacha[RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM]; +extern const rsip_func_key_generate_t gp_func_key_generate_hmac[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM]; + +extern const rsip_func_key_pair_generate_t gp_func_key_pair_generate_ecc[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_key_pair_generate_t gp_func_key_pair_generate_rsa[RSIP_PRV_KEY_SUBTYPE_RSA_NUM]; + +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_aes[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_xts_aes[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_chacha[RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_ecc_pub[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_ecc_priv[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_rsa_pub[RSIP_PRV_KEY_SUBTYPE_RSA_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_rsa_priv[RSIP_PRV_KEY_SUBTYPE_RSA_NUM]; +extern const rsip_func_encrypted_key_wrap_t gp_func_encrypted_key_wrap_hmac[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM]; + +extern const rsip_func_rfc3394_key_wrap_t gp_func_rfc3394_key_wrap[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_rfc3394_key_unwrap_t gp_func_rfc3394_key_unwrap[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; + +extern const rsip_func_subset_aes_cipher_t gp_func_aes_cipher[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_subset_aes_xts_t gp_func_aes_xts_enc[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_subset_aes_xts_t gp_func_aes_xts_dec[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_subset_aes_gcm_t gp_func_aes_gcm_enc[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_subset_aes_gcm_t gp_func_aes_gcm_dec[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_subset_aes_ccm_t gp_func_aes_ccm_enc[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_subset_aes_ccm_t gp_func_aes_ccm_dec[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_subset_aes_cmac_t gp_func_aes_cmac[RSIP_PRV_KEY_SUBTYPE_AES_NUM]; + +extern const rsip_func_subset_chacha20_t gp_func_chacha20[RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM]; +extern const rsip_func_subset_chacha20_poly1305_t gp_func_chacha20_poly1305[RSIP_PRV_KEY_SUBTYPE_CHACHA_NUM]; + +extern const rsip_func_ecdsa_sign_t gp_func_ecdsa_sign[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_ecdsa_verify_t gp_func_ecdsa_verify[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; + +extern const rsip_func_eddsa_sign_t gp_func_eddsa_sign[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_eddsa_verify_t gp_func_eddsa_verify[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; + +extern const rsip_func_ecdh_t gp_func_ecdh_wrapped[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_ecdh_t gp_func_ecdh_plain[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; + +extern const rsip_func_rsa_t gp_func_rsa_public[RSIP_PRV_KEY_SUBTYPE_RSA_NUM]; +extern const rsip_func_rsa_t gp_func_rsa_private[RSIP_PRV_KEY_SUBTYPE_RSA_NUM]; + +extern const rsip_func_subset_sha_t gp_func_sha1sha2; +extern const rsip_func_subset_sha_t gp_func_sha3; +extern const rsip_func_subset_hmac_t gp_func_hmac_sha1sha2; +extern const rsip_func_subset_hmac_t gp_func_hmac_sha3; +extern const rsip_func_subset_kdf_sha_t gp_func_kdf_sha1sha2; +extern const rsip_func_subset_kdf_hmac_t gp_func_kdf_hmac_sha1sha2; + +extern const rsip_func_subset_pki_ecdsa_verify_t gp_func_pki_ecdsa_verify[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_subset_pki_rsa_verify_t gp_func_pki_rsa_verify[RSIP_PRV_KEY_SUBTYPE_RSA_NUM]; +extern const rsip_func_pki_cert_key_import_t gp_func_pki_cert_key_import_ecc[RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_pki_cert_key_import_t gp_func_pki_cert_key_import_rsa[RSIP_PRV_KEY_SUBTYPE_RSA_NUM]; + +extern const rsip_func_rng_t gp_func_rng; +extern const rsip_func_ghash_t gp_func_ghash_compute; + +extern const rsip_func_kdf_ecdh_secret_msg_wrap_t gp_func_kdf_sha_ecdh_secret_msg_wrap[RSIP_PRV_DKM_SUBTYPE_SHA_NUM]; + +extern const rsip_func_kdf_derived_key_import_t gp_func_kdf_sha_derived_key_import_aes +[RSIP_PRV_DKM_SUBTYPE_SHA_NUM][RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_kdf_derived_iv_wrap_t gp_func_kdf_sha_derived_iv_wrap[RSIP_PRV_DKM_SUBTYPE_SHA_NUM][2]; + +extern const rsip_func_kdf_ecdh_secret_key_import_t gp_func_kdf_hmac_ecdh_secret_key_import[ + RSIP_PRV_KEY_SUBTYPE_HMAC_NUM +][RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_kdf_ecdh_secret_msg_wrap_t gp_func_kdf_hmac_ecdh_secret_msg_wrap[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM][ + RSIP_PRV_KEY_SUBTYPE_ECC_NUM]; +extern const rsip_func_kdf_dkm_key_import_t gp_func_kdf_hmac_dkm_key_import[RSIP_PRV_KEY_SUBTYPE_HMAC_NUM]; + +extern const rsip_func_kdf_derived_key_import_t gp_func_kdf_hmac_derived_key_import_aes +[RSIP_PRV_DKM_SUBTYPE_HMAC_NUM][RSIP_PRV_KEY_SUBTYPE_AES_NUM]; +extern const rsip_func_kdf_derived_key_import_t gp_func_kdf_hmac_derived_key_import_hmac +[RSIP_PRV_DKM_SUBTYPE_HMAC_NUM][RSIP_PRV_KEY_SUBTYPE_HMAC_NUM]; +extern const rsip_func_kdf_derived_iv_wrap_t gp_func_kdf_hmac_derived_iv_wrap[RSIP_PRV_DKM_SUBTYPE_HMAC_NUM +][3]; + +extern const rsip_func_otf_t gp_func_otf[RSIP_OTF_CHANNEL_NUM][RSIP_PRV_KEY_SUBTYPE_AES_NUM]; + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the RSIP engine. + * + * @return The return value of the internally called primitive functions. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_open(void); + +/*******************************************************************************************************************//** + * Finalizes the RSIP engine. + * + * @return The return value of the internally called primitive functions. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_close(void); + +/*******************************************************************************************************************//** + * Sets Key Update Key (KUK). + * + * @param[in] p_key_update_key KUK. + **********************************************************************************************************************/ +void r_rsip_kuk_set(const void * p_key_update_key); + +/*******************************************************************************************************************//** + * Gets parameters for RFC3394 AES Key Wrap from target key type. + * + * @param[in] key_type Key type of target key. + * @param[out] wrapped_key_type Key type number used for primitives. + * @param[out] key_index_size Word size of key index. + * @param[out] wrapped_key_size Word size of AES-wrapped key. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid key type. + **********************************************************************************************************************/ +fsp_err_t get_rfc3394_key_wrap_param(rsip_key_type_t key_type, + uint32_t * wrapped_key_type, + uint32_t * key_index_size, + uint32_t * wrapped_key_size); + +/*******************************************************************************************************************//** + * 1. Initialize hash operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_sha_hash_init_update(rsip_sha_handle_t * p_handle, const uint8_t * p_message, + uint64_t message_length); + +/*******************************************************************************************************************//** + * 1. Resume hash operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_sha_hash_resume_update(rsip_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length); + +/*******************************************************************************************************************//** + * Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_sha_hash_update(rsip_sha_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length); + +/*******************************************************************************************************************//** + * Suspend hash operation. + * + * @param[in,out] p_handle Pointer to handle. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_sha_hash_suspend(rsip_sha_handle_t * p_handle); + +/*******************************************************************************************************************//** + * 1. Initialize hash operation. + * 2. Input the remaining message and finalize hash operation. + * + * @note This function allows empty message. + * + * @param[in] hash_type Generating hash type. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_sha_hash_init_final(rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint8_t * p_digest); + +/*******************************************************************************************************************//** + * 1. Resume hash operation. + * 2. Input the remaining message and finalize hash operation. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_sha_hash_resume_final(rsip_sha_handle_t * p_handle, uint8_t * p_digest); + +/*******************************************************************************************************************//** + * Input the remaining message and finalize hash operation. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_sha_hash_final(rsip_sha_handle_t * p_handle, uint8_t * p_digest); + +/*******************************************************************************************************************//** + * 1. Initialize HMAC operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_init_update(rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length); + +/*******************************************************************************************************************//** + * 1. Resume HMAC operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_resume_update(rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length); + +/*******************************************************************************************************************//** + * Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_update(rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length); + +/*******************************************************************************************************************//** + * Suspend HMAC operation. + * + * @param[in,out] p_handle Pointer to handle. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_suspend(rsip_hmac_handle_t * p_handle); + +/*******************************************************************************************************************//** + * 1. Initialize HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Output MAC. + * + * @note This function allows empty message. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_init_final(const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint8_t * p_mac); + +/*******************************************************************************************************************//** + * 1. Resume HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Output MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_resume_final(rsip_hmac_handle_t * p_handle, uint8_t * p_mac); + +/*******************************************************************************************************************//** + * 1. Input the remaining message and finalize HMAC operation. + * 2. Output MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_final(rsip_hmac_handle_t * p_handle, uint8_t * p_mac); + +/*******************************************************************************************************************//** + * 1. Initialize HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Verify MAC. + * + * @note This function allows empty message. + * + * @param[in] p_wrapped_key Pointer to wrapped key of HMAC key. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_init_verify(const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + const uint8_t * p_mac, + uint32_t mac_length); + +/*******************************************************************************************************************//** + * 1. Resume HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Verify MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_resume_verify(rsip_hmac_handle_t * p_handle, const uint8_t * p_mac, uint32_t mac_length); + +/*******************************************************************************************************************//** + * 1. Input the remaining message and finalize HMAC operation. + * 2. Verify MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_hmac_verify(rsip_hmac_handle_t * p_handle, const uint8_t * p_mac, uint32_t mac_length); + +/*******************************************************************************************************************//** + * 1. Initialize hash operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_sha_init_update(rsip_kdf_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length); + +/*******************************************************************************************************************//** + * 1. Resume hash operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_sha_resume_update(rsip_kdf_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length); + +/*******************************************************************************************************************//** + * Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_sha_update(rsip_kdf_sha_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length); + +/*******************************************************************************************************************//** + * Suspend hash operation. + * + * @param[in,out] p_handle Pointer to handle. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_sha_suspend(rsip_kdf_sha_handle_t * p_handle); + +/*******************************************************************************************************************//** + * 1. Initialize hash operation. + * 2. Input the remaining message and finalize hash operation. + * + * @note This function allows empty message. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_sha_init_final(rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest); + +/*******************************************************************************************************************//** + * 1. Resume hash operation. + * 2. Input the remaining message and finalize hash operation. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_sha_resume_final(rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest); + +/*******************************************************************************************************************//** + * Input the remaining message and finalize hash operation. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_sha_final(rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest); + +/*******************************************************************************************************************//** + * 1. Initialize HMAC operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_hmac_init_update(rsip_kdf_hmac_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length); + +/*******************************************************************************************************************//** + * 1. Resume HMAC operation. + * 2. Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_hmac_resume_update(rsip_kdf_hmac_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length); + +/*******************************************************************************************************************//** + * Input block message in block length. + * + * @note Message length must be at least 1 block. + * + * @param[in,out] p_handle Pointer to handle. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_hmac_update(rsip_kdf_hmac_handle_t * p_handle, const uint8_t * p_message, + uint64_t message_length); + +/*******************************************************************************************************************//** + * Suspend HMAC operation. + * + * @param[in,out] p_handle Pointer to handle. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_hmac_suspend(rsip_kdf_hmac_handle_t * p_handle); + +/*******************************************************************************************************************//** + * 1. Initialize HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Output MAC. + * + * @note This function allows empty message. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_hmac_init_final(rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac); + +/*******************************************************************************************************************//** + * 1. Resume HMAC operation. + * 2. Input the remaining message and finalize HMAC operation. + * 3. Output MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_hmac_resume_final(rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac); + +/*******************************************************************************************************************//** + * 1. Input the remaining message and finalize HMAC operation. + * 2. Output MAC. + * + * @note Message length must be at least 1 byte. + * + * @param[in,out] p_handle Pointer to handle. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +rsip_ret_t r_rsip_kdf_hmac_final(rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac); + +/*******************************************************************************************************************//** + * Parses key type. + * + * @param[in] key_type Key type. + * + * @return Parsed key type. + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE rsip_key_type_extend_t r_rsip_key_type_parse (rsip_key_type_t key_type) +{ + rsip_key_type_extend_t ret = + { + .alg = RSIP_PRV_KEY_TYPE_VAL_ALG(key_type), .subtype = RSIP_PRV_KEY_TYPE_VAL_SUBTYPE(key_type) + }; + + return ret; +} + +/*******************************************************************************************************************//** + * Converts byte length to word (4-byte) length and rounds up it. + * + * @param[in] bytes Byte length + * + * @return Word length + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint32_t r_rsip_byte_to_word_convert (const uint32_t bytes) +{ + return (bytes + 3) >> 2; +} + +/*******************************************************************************************************************//** + * Converts word (4-byte) length to byte length. + * + * @param[in] words Word length + * + * @return Byte length + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint32_t r_rsip_word_to_byte_convert (const uint32_t words) +{ + return words << 2; +} + +/*******************************************************************************************************************//** + * Converts byte data to bit data. This function returns upper 3 digits. + * + * @param[in] bytes Byte length + * + * @return Bit length (upper 3 digits) + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint32_t r_rsip_byte_to_bit_convert_upper (const uint64_t bytes) +{ + return (uint32_t) (bytes >> 29); +} + +/*******************************************************************************************************************//** + * Converts byte data to bit data. This function returns lower 32 digits. + * + * @param[in] bytes Byte length + * + * @return Bit length (lower 32 digits) + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint32_t r_rsip_byte_to_bit_convert_lower (const uint64_t bytes) +{ + return (uint32_t) (bytes << 3); +} + +#endif /* R_RSIP_PRIVATE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private_sub1.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private_sub1.c new file mode 100644 index 0000000000..994fe7cde7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private_sub1.c @@ -0,0 +1,1261 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_private.h" + +#if 1U == RSIP_PRV_HASH_IP_TYPE + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* For SHA, HMAC-SHA */ + #define RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER (16U) + #define RSIP_PRV_WORD_SIZE_SHA_MESSAGE_DIGEST_BUFFER (8U) + +/* Block length (in bytes) of SHA */ + #define SHA_BLOCK8_LEN (64U) + #define HMAC_LAST_BLOCK_ADD_LEN (64U) + #define SHA_STOP_BIT (0x80) + #define SHA_PADDING_DATA_LEN (9U) + #define SHA2_FINAL_BLOCK_MAX_MESSAGE_LEN (SHA_BLOCK8_LEN * 2 - SHA_PADDING_DATA_LEN) + #define HMAC_SHA256_MESSAGE_ADD_LEN (512U) + +/* Initial values for SHA operation */ + #define RSIP_PRV_SHA224_INIT_VALUE1 (0xc1059ed8) + #define RSIP_PRV_SHA224_INIT_VALUE2 (0x367cd507) + #define RSIP_PRV_SHA224_INIT_VALUE3 (0x3070dd17) + #define RSIP_PRV_SHA224_INIT_VALUE4 (0xf70e5939) + #define RSIP_PRV_SHA224_INIT_VALUE5 (0xffc00b31) + #define RSIP_PRV_SHA224_INIT_VALUE6 (0x68581511) + #define RSIP_PRV_SHA224_INIT_VALUE7 (0x64f98fa7) + #define RSIP_PRV_SHA224_INIT_VALUE8 (0xbefa4fa4) + + #define RSIP_PRV_SHA256_INIT_VALUE1 (0x6a09e667) + #define RSIP_PRV_SHA256_INIT_VALUE2 (0xbb67ae85) + #define RSIP_PRV_SHA256_INIT_VALUE3 (0x3c6ef372) + #define RSIP_PRV_SHA256_INIT_VALUE4 (0xa54ff53a) + #define RSIP_PRV_SHA256_INIT_VALUE5 (0x510e527f) + #define RSIP_PRV_SHA256_INIT_VALUE6 (0x9b05688c) + #define RSIP_PRV_SHA256_INIT_VALUE7 (0x1f83d9ab) + #define RSIP_PRV_SHA256_INIT_VALUE8 (0x5be0cd19) + + #define RSIP_PRV_KDF_SHA256_INIT_VALUE1 (0x6a09e667) + #define RSIP_PRV_KDF_SHA256_INIT_VALUE2 (0xbb67ae85) + #define RSIP_PRV_KDF_SHA256_INIT_VALUE3 (0x3c6ef372) + #define RSIP_PRV_KDF_SHA256_INIT_VALUE4 (0xa54ff53a) + #define RSIP_PRV_KDF_SHA256_INIT_VALUE5 (0x510e527f) + #define RSIP_PRV_KDF_SHA256_INIT_VALUE6 (0x9b05688c) + #define RSIP_PRV_KDF_SHA256_INIT_VALUE7 (0x1f83d9ab) + #define RSIP_PRV_KDF_SHA256_INIT_VALUE8 (0x5be0cd19) + + #define RSIP_PRV_KDF_SHA_DATA_TYPE_MESSAGE_DIGEST (0U) + #define RSIP_PRV_KDF_SHA_DATA_TYPE_KDF_INFORMATION (1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum e_rsip_hmac_cmd +{ + RSIP_HMAC_CMD_SIGN = 0U, + RSIP_HMAC_CMD_VERIFY = 1U, +} rsip_hmac_cmd_t; + +typedef union u_rsip_dword_data +{ + uint64_t dword; + struct + { + uint8_t pos_1st; + uint8_t pos_2nd; + uint8_t pos_3rd; + uint8_t pos_4th; + uint8_t pos_5th; + uint8_t pos_6th; + uint8_t pos_7th; + uint8_t pos_8th; + } byte; +} rsip_dword_data_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void set_sha2_final_block(const uint8_t * p_message, + uint64_t message_length, + uint64_t total_message_length, + uint8_t * p_last_block, + uint32_t * p_last_block_length); +RSIP_PRV_STATIC_INLINE uint32_t get_cmd_kdf_hmac_alg(uint8_t alg); +RSIP_PRV_STATIC_INLINE const rsip_func_subset_kdf_hmac_t * get_kdf_hmac_func(rsip_key_type_extend_t key_type_ext); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +static const uint32_t gs_hmac_cmd[] = +{ + [RSIP_HMAC_CMD_SIGN] = BSWAP_32BIG_C(0U), + [RSIP_HMAC_CMD_VERIFY] = BSWAP_32BIG_C(1U), +}; + +static const uint32_t gs_sha224_init_value[8] = +{ + BSWAP_32BIG_C(RSIP_PRV_SHA224_INIT_VALUE1), + BSWAP_32BIG_C(RSIP_PRV_SHA224_INIT_VALUE2), + BSWAP_32BIG_C(RSIP_PRV_SHA224_INIT_VALUE3), + BSWAP_32BIG_C(RSIP_PRV_SHA224_INIT_VALUE4), + BSWAP_32BIG_C(RSIP_PRV_SHA224_INIT_VALUE5), + BSWAP_32BIG_C(RSIP_PRV_SHA224_INIT_VALUE6), + BSWAP_32BIG_C(RSIP_PRV_SHA224_INIT_VALUE7), + BSWAP_32BIG_C(RSIP_PRV_SHA224_INIT_VALUE8), +}; + +static const uint32_t gs_sha256_init_value[8] = +{ + BSWAP_32BIG_C(RSIP_PRV_SHA256_INIT_VALUE1), + BSWAP_32BIG_C(RSIP_PRV_SHA256_INIT_VALUE2), + BSWAP_32BIG_C(RSIP_PRV_SHA256_INIT_VALUE3), + BSWAP_32BIG_C(RSIP_PRV_SHA256_INIT_VALUE4), + BSWAP_32BIG_C(RSIP_PRV_SHA256_INIT_VALUE5), + BSWAP_32BIG_C(RSIP_PRV_SHA256_INIT_VALUE6), + BSWAP_32BIG_C(RSIP_PRV_SHA256_INIT_VALUE7), + BSWAP_32BIG_C(RSIP_PRV_SHA256_INIT_VALUE8), +}; + +static const uint32_t gs_kdf_sha256_init_value[8] = +{ + BSWAP_32BIG_C(RSIP_PRV_KDF_SHA256_INIT_VALUE1), + BSWAP_32BIG_C(RSIP_PRV_KDF_SHA256_INIT_VALUE2), + BSWAP_32BIG_C(RSIP_PRV_KDF_SHA256_INIT_VALUE3), + BSWAP_32BIG_C(RSIP_PRV_KDF_SHA256_INIT_VALUE4), + BSWAP_32BIG_C(RSIP_PRV_KDF_SHA256_INIT_VALUE5), + BSWAP_32BIG_C(RSIP_PRV_KDF_SHA256_INIT_VALUE6), + BSWAP_32BIG_C(RSIP_PRV_KDF_SHA256_INIT_VALUE7), + BSWAP_32BIG_C(RSIP_PRV_KDF_SHA256_INIT_VALUE8), +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_sha_hash_init_update (rsip_sha_handle_t * p_handle, const uint8_t * p_message, + uint64_t message_length) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + + switch (p_handle->type) + { + /* SHA-224 */ + case RSIP_HASH_TYPE_SHA224: + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = + gp_func_sha1sha2(gs_sha224_init_value, (const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) message_length), p_handle->internal_state); + break; + } + + /* SHA-256 */ + case RSIP_HASH_TYPE_SHA256: + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = + gp_func_sha1sha2(gs_sha256_init_value, (const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) message_length), p_handle->internal_state); + break; + } + + default: + { + break; + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha_hash_resume_update (rsip_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + return r_rsip_sha_hash_update(p_handle, p_message, message_length); +} + +rsip_ret_t r_rsip_sha_hash_update (rsip_sha_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + + /* Call function (cast to match the argument type with the primitive function) */ + return gp_func_sha1sha2(p_handle->internal_state, (const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) message_length), p_handle->internal_state); +} + +rsip_ret_t r_rsip_sha_hash_suspend (rsip_sha_handle_t * p_handle) +{ + FSP_PARAMETER_NOT_USED(p_handle); + + return RSIP_RET_PASS; +} + +rsip_ret_t r_rsip_sha_hash_init_final (rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint8_t * p_digest) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + uint8_t padded_msg[SHA_BLOCK8_LEN * 2] = {0}; + uint32_t set_prc_byte_size = 0; + uint64_t tmp_message_length = message_length; + const uint8_t * p_tmp_message = p_message; + const uint32_t * p_tmp_digest; + uint32_t digest_buffer[RSIP_PRV_WORD_SIZE_SHA_MESSAGE_DIGEST_BUFFER] = {0}; + + switch (hash_type) + { + /* SHA-224 */ + case RSIP_HASH_TYPE_SHA224: + { + p_tmp_digest = gs_sha224_init_value; + rsip_ret = RSIP_RET_PASS; + break; + } + + /* SHA-256 */ + case RSIP_HASH_TYPE_SHA256: + { + p_tmp_digest = gs_sha256_init_value; + rsip_ret = RSIP_RET_PASS; + break; + } + + default: + { + break; + } + } + + if (RSIP_RET_PASS == rsip_ret) + { + if (SHA2_FINAL_BLOCK_MAX_MESSAGE_LEN <= message_length) + { + tmp_message_length = message_length & (SHA_BLOCK8_LEN - 1); + p_tmp_message = p_message + (message_length - tmp_message_length); + rsip_ret = + gp_func_sha1sha2(p_tmp_digest, + (const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) (message_length - tmp_message_length)), + digest_buffer); + p_tmp_digest = digest_buffer; + } + + if (RSIP_RET_PASS == rsip_ret) + { + set_sha2_final_block(p_tmp_message, tmp_message_length, message_length, padded_msg, &set_prc_byte_size); + + rsip_ret = + gp_func_sha1sha2(p_tmp_digest, (const uint32_t *) padded_msg, + r_rsip_byte_to_word_convert(set_prc_byte_size), (uint32_t *) p_digest); + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha_hash_resume_final (rsip_sha_handle_t * p_handle, uint8_t * p_digest) +{ + return r_rsip_sha_hash_final(p_handle, p_digest); +} + +rsip_ret_t r_rsip_sha_hash_final (rsip_sha_handle_t * p_handle, uint8_t * p_digest) +{ + uint32_t set_prc_byte_size = 0; + + set_sha2_final_block(p_handle->buffer, + p_handle->buffered_length, + p_handle->total_length + p_handle->buffered_length, + p_handle->buffer, + &set_prc_byte_size); + + /* Call function (cast to match the argument type with the primitive function) */ + return gp_func_sha1sha2(p_handle->internal_state, (const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert(set_prc_byte_size), (uint32_t *) p_digest); +} + +rsip_ret_t r_rsip_hmac_init_update (rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_init( + (uint32_t *) p_handle->wrapped_key.p_value); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_init( + (uint32_t *) p_handle->wrapped_key.p_value); + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + + if (RSIP_RET_PASS == rsip_ret) + { + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) + message_length)); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) + message_length)); + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_update (rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + FSP_PARAMETER_NOT_USED(p_handle); + + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + + /* Call function (cast to match the argument type with the primitive function) */ + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_resume( + (uint32_t *) p_handle->wrapped_key.p_value, + p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) + message_length)); + } + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_resume( + (uint32_t *) p_handle->wrapped_key.p_value, + p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) + message_length)); + } + } + else + { + /* Do nothing */ + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_update (rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) + message_length)); + rsip_ret = RSIP_RET_PASS; + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) + message_length)); + rsip_ret = RSIP_RET_PASS; + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_suspend (rsip_hmac_handle_t * p_handle) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_suspend(p_handle->internal_state); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_suspend(p_handle->internal_state); + } + else + { + /* Do nothing */ + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_init_final (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint8_t * p_mac) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); + + uint8_t padded_msg[SHA_BLOCK8_LEN * 2] = {0}; + uint32_t set_prc_byte_size = 0; + uint64_t tmp_message_length = message_length; + const uint8_t * p_tmp_message = p_message; + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_init((uint32_t *) p_wrapped_key->p_value); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_init((uint32_t *) p_wrapped_key->p_value); + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + + if (RSIP_RET_PASS == rsip_ret) + { + if (SHA2_FINAL_BLOCK_MAX_MESSAGE_LEN <= message_length) + { + tmp_message_length = message_length & (SHA_BLOCK8_LEN - 1); + p_tmp_message = p_message + (message_length - tmp_message_length); + } + + set_sha2_final_block(p_tmp_message, + tmp_message_length, + message_length + HMAC_LAST_BLOCK_ADD_LEN, + padded_msg, + &set_prc_byte_size); + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + if (SHA2_FINAL_BLOCK_MAX_MESSAGE_LEN <= message_length) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) ( + message_length + - + tmp_message_length))); + } + + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) padded_msg, + r_rsip_byte_to_word_convert( + set_prc_byte_size)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + NULL, + NULL, + (uint32_t *) p_mac); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + if (SHA2_FINAL_BLOCK_MAX_MESSAGE_LEN <= message_length) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) ( + message_length + - + tmp_message_length))); + } + + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) padded_msg, + r_rsip_byte_to_word_convert( + set_prc_byte_size)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + NULL, + NULL, + (uint32_t *) p_mac); + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_final (rsip_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + uint32_t set_prc_byte_size = 0; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + + set_sha2_final_block(p_handle->buffer, + p_handle->buffered_length, + p_handle->total_length + p_handle->buffered_length + HMAC_LAST_BLOCK_ADD_LEN, + (uint8_t *) p_handle->buffer, + &set_prc_byte_size); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_resume( + (uint32_t *) p_handle->wrapped_key.p_value, + p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert( + set_prc_byte_size)); + rsip_ret = + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + NULL, + NULL, + (uint32_t *) p_mac); + } + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_resume( + (uint32_t *) p_handle->wrapped_key.p_value, + p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert( + set_prc_byte_size)); + rsip_ret = + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + NULL, + NULL, + (uint32_t *) p_mac); + } + } + else + { + /* Do nothing */ + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_final (rsip_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t set_prc_byte_size = 0; + + set_sha2_final_block(p_handle->buffer, + p_handle->buffered_length, + p_handle->total_length + p_handle->buffered_length + HMAC_LAST_BLOCK_ADD_LEN, + p_handle->buffer, + &set_prc_byte_size); + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert(set_prc_byte_size)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + NULL, + NULL, + (uint32_t *) p_mac); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert(set_prc_byte_size)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + NULL, + NULL, + (uint32_t *) p_mac); + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_init_verify (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + const uint8_t * p_mac, + uint32_t mac_length) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); + + uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = {0}; + uint8_t padded_msg[SHA_BLOCK8_LEN * 2] = {0}; + uint32_t set_prc_byte_size = 0; + uint64_t tmp_message_length = message_length; + const uint8_t * p_tmp_message = p_message; + memcpy(InData_MAC, p_mac, mac_length); + uint32_t mac_len[1] = {bswap_32big(mac_length)}; + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_init((uint32_t *) p_wrapped_key->p_value); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_init((uint32_t *) p_wrapped_key->p_value); + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + + if (RSIP_RET_PASS == rsip_ret) + { + if (SHA2_FINAL_BLOCK_MAX_MESSAGE_LEN <= message_length) + { + tmp_message_length = message_length & (SHA_BLOCK8_LEN - 1); + p_tmp_message = p_message + (message_length - tmp_message_length); + } + + set_sha2_final_block(p_tmp_message, + tmp_message_length, + message_length + HMAC_LAST_BLOCK_ADD_LEN, + padded_msg, + &set_prc_byte_size); + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + if (SHA2_FINAL_BLOCK_MAX_MESSAGE_LEN <= message_length) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) ( + message_length + - + tmp_message_length))); + } + + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) padded_msg, + r_rsip_byte_to_word_convert( + set_prc_byte_size)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_final( + &gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + InData_MAC, + mac_len, + NULL); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + if (SHA2_FINAL_BLOCK_MAX_MESSAGE_LEN <= message_length) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_message, + r_rsip_byte_to_word_convert((uint32_t) ( + message_length + - + tmp_message_length))); + } + + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) padded_msg, + r_rsip_byte_to_word_convert( + set_prc_byte_size)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_final( + &gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + InData_MAC, + mac_len, + NULL); + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_verify (rsip_hmac_handle_t * p_handle, const uint8_t * p_mac, uint32_t mac_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t set_prc_byte_size = 0; + uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = + { + 0 + }; + + set_sha2_final_block(p_handle->buffer, + p_handle->buffered_length, + p_handle->total_length + p_handle->buffered_length + HMAC_LAST_BLOCK_ADD_LEN, + (uint8_t *) p_handle->buffer, + &set_prc_byte_size); + + memcpy(InData_MAC, p_mac, mac_length); + uint32_t mac_len[1] = + { + bswap_32big(mac_length) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_resume( + (uint32_t *) p_handle->wrapped_key.p_value, + p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert( + set_prc_byte_size)); + rsip_ret = + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + InData_MAC, + mac_len, + (uint32_t *) NULL); + } + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_resume( + (uint32_t *) p_handle->wrapped_key.p_value, + p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert( + set_prc_byte_size)); + rsip_ret = + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + InData_MAC, + mac_len, + (uint32_t *) NULL); + } + } + else + { + /* Do nothing */ + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_verify (rsip_hmac_handle_t * p_handle, const uint8_t * p_mac, uint32_t mac_length) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + + uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = {0}; + uint32_t mac_len[1] = {bswap_32big(mac_length)}; + uint32_t set_prc_byte_size = 0; + + set_sha2_final_block(p_handle->buffer, + p_handle->buffered_length, + p_handle->total_length + p_handle->buffered_length + HMAC_LAST_BLOCK_ADD_LEN, + p_handle->buffer, + &set_prc_byte_size); + + memcpy(InData_MAC, p_mac, mac_length); + + if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224 == key_type_ext.subtype) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_update((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert(set_prc_byte_size)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + InData_MAC, + mac_len, + NULL); + } + else if (RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256 == key_type_ext.subtype) + { + gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_update((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert(set_prc_byte_size)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_hmac_sha1sha2[RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256].p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + InData_MAC, + mac_len, + NULL); + } + else + { + rsip_ret = RSIP_RET_FAIL; + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_init_update (rsip_kdf_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + + uint32_t msg1_len[1] = {bswap_32big(p_handle->buffered_length1)}; + uint32_t enc_msg_len[1] = {bswap_32big(p_handle->actual_wrapped_msg_length)}; + uint32_t msg2_len[1] = {bswap_32big((uint32_t) message_length)}; + uint32_t out_data_type[1] = {bswap_32big(RSIP_PRV_KDF_SHA_DATA_TYPE_MESSAGE_DIGEST)}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = + gp_func_kdf_sha1sha2(gs_kdf_sha256_init_value, + (const uint32_t *) p_handle->buffer1, + msg1_len, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (const uint32_t *) p_message, + msg2_len, + (const uint32_t *) out_data_type, + p_handle->internal_state, + NULL); + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_resume_update (rsip_kdf_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + return r_rsip_kdf_sha_update(p_handle, p_message, message_length); +} + +rsip_ret_t r_rsip_kdf_sha_update (rsip_kdf_sha_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + + uint32_t msg1_len[1] = {0}; + uint32_t enc_msg_len[1] = {0}; + uint32_t msg2_len[1] = {bswap_32big((uint32_t) message_length)}; + uint32_t out_data_type[1] = {bswap_32big(RSIP_PRV_KDF_SHA_DATA_TYPE_MESSAGE_DIGEST)}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = + gp_func_kdf_sha1sha2(p_handle->internal_state, + NULL, + msg1_len, + NULL, + enc_msg_len, + (const uint32_t *) p_message, + msg2_len, + (const uint32_t *) out_data_type, + p_handle->internal_state, + NULL); + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_suspend (rsip_kdf_sha_handle_t * p_handle) +{ + FSP_PARAMETER_NOT_USED(p_handle); + + return RSIP_RET_PASS; +} + +rsip_ret_t r_rsip_kdf_sha_init_final (rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest) +{ + uint32_t total_length = p_handle->buffered_length1 + p_handle->actual_wrapped_msg_length + + p_handle->buffered_length2; + rsip_dword_data_t total_bit_length = {.dword = total_length << 3}; + uint8_t padded_buffer2[SHA_BLOCK8_LEN * 2] = {0}; + uint32_t zero_padding_len = 0; + uint32_t tmp_len = (total_length + SHA_PADDING_DATA_LEN) & (SHA_BLOCK8_LEN - 1); + + if (0 != tmp_len) + { + zero_padding_len = SHA_BLOCK8_LEN - tmp_len; + } + + memcpy(padded_buffer2, p_handle->buffer2, p_handle->buffered_length2); + + padded_buffer2[p_handle->buffered_length2] = SHA_STOP_BIT; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 1] = total_bit_length.byte.pos_8th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 2] = total_bit_length.byte.pos_7th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 3] = total_bit_length.byte.pos_6th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 4] = total_bit_length.byte.pos_5th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 5] = total_bit_length.byte.pos_4th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 6] = total_bit_length.byte.pos_3rd; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 7] = total_bit_length.byte.pos_2nd; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 8] = total_bit_length.byte.pos_1st; + + uint32_t padded_buffer2_len = p_handle->buffered_length2 + zero_padding_len + SHA_PADDING_DATA_LEN; + uint32_t msg1_len[1] = {bswap_32big(p_handle->buffered_length1)}; + uint32_t enc_msg_len[1] = {bswap_32big(p_handle->actual_wrapped_msg_length)}; + uint32_t msg2_len[1] = {bswap_32big(padded_buffer2_len)}; + uint32_t out_data_type[1] = {bswap_32big(RSIP_PRV_KDF_SHA_DATA_TYPE_KDF_INFORMATION)}; + + /* Call function (cast to match the argument type with the primitive function) */ + return gp_func_kdf_sha1sha2(gs_kdf_sha256_init_value, + (const uint32_t *) p_handle->buffer1, + msg1_len, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (const uint32_t *) padded_buffer2, + msg2_len, + (const uint32_t *) out_data_type, + NULL, + (uint32_t *) p_digest); +} + +rsip_ret_t r_rsip_kdf_sha_resume_final (rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest) +{ + return r_rsip_kdf_sha_final(p_handle, p_digest); +} + +rsip_ret_t r_rsip_kdf_sha_final (rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest) +{ + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + uint32_t total_length = p_handle->total_length + p_handle->buffered_length2; + rsip_dword_data_t total_bit_length = {.dword = (total_length << 3)}; + uint8_t padded_buffer2[SHA_BLOCK8_LEN * 2] = {0}; + uint32_t zero_padding_len = 0; + uint32_t tmp_len = (total_length + SHA_PADDING_DATA_LEN) & (SHA_BLOCK8_LEN - 1); + + if (0 != tmp_len) + { + zero_padding_len = SHA_BLOCK8_LEN - tmp_len; + } + + memcpy(padded_buffer2, p_handle->buffer2, p_handle->buffered_length2); + + padded_buffer2[p_handle->buffered_length2] = SHA_STOP_BIT; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 1] = total_bit_length.byte.pos_8th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 2] = total_bit_length.byte.pos_7th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 3] = total_bit_length.byte.pos_6th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 4] = total_bit_length.byte.pos_5th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 5] = total_bit_length.byte.pos_4th; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 6] = total_bit_length.byte.pos_3rd; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 7] = total_bit_length.byte.pos_2nd; + padded_buffer2[p_handle->buffered_length2 + zero_padding_len + 8] = total_bit_length.byte.pos_1st; + + uint32_t msg1_len[1] = {0}; + uint32_t enc_msg_len[1] = {0}; + uint32_t padded_buffer2_len = p_handle->buffered_length2 + zero_padding_len + SHA_PADDING_DATA_LEN; + uint32_t msg2_len[1] = {bswap_32big(padded_buffer2_len)}; + uint32_t out_data_type[1] = {bswap_32big(RSIP_PRV_KDF_SHA_DATA_TYPE_KDF_INFORMATION)}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = + gp_func_kdf_sha1sha2(p_handle->internal_state, + NULL, + msg1_len, + NULL, + enc_msg_len, + (const uint32_t *) padded_buffer2, + msg2_len, + (const uint32_t *) out_data_type, + NULL, + (uint32_t *) p_digest); + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_init_update (rsip_kdf_hmac_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t cmd_key_type = get_cmd_kdf_hmac_alg(key_type_ext.alg); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_init(&cmd_key_type, p_handle->wrapped_key.p_value); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->wrapped_msg_length))}; + rsip_ret = + p_func->p_enc_update((const uint32_t *) p_handle->wrapped_msg, enc_msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_resume_update (rsip_kdf_hmac_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t cmd_key_type = get_cmd_kdf_hmac_alg(key_type_ext.alg); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call funcion (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_resume(&cmd_key_type, p_handle->wrapped_key.p_value, p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->wrapped_msg_length))}; + rsip_ret = + p_func->p_enc_update((const uint32_t *) p_handle->wrapped_msg, enc_msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_update (rsip_kdf_hmac_handle_t * p_handle, const uint8_t * p_message, + uint64_t message_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + uint32_t enc_msg_len[1] = {0}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_enc_update(NULL, enc_msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_suspend (rsip_kdf_hmac_handle_t * p_handle) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + return p_func->p_suspend(p_handle->internal_state); +} + +rsip_ret_t r_rsip_kdf_hmac_init_final (rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t cmd_key_type = get_cmd_kdf_hmac_alg(key_type_ext.alg); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_init(&cmd_key_type, (const uint32_t *) p_handle->wrapped_key.p_value); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t enc_msg_len[1] = + { + bswap_32big(r_rsip_byte_to_word_convert(p_handle->wrapped_msg_length)) + }; + uint8_t padded_buffer2[SHA_BLOCK8_LEN * 2] = {0}; + uint32_t zero_padding_len = 0; + uint32_t total_length = p_handle->buffered_length + p_handle->actual_wrapped_msg_length; + uint32_t tmp_len = (total_length + SHA_PADDING_DATA_LEN) & (SHA_BLOCK8_LEN - 1); + rsip_dword_data_t total_bit_length = {.dword = (total_length << 3) + HMAC_SHA256_MESSAGE_ADD_LEN}; + + if (0 != tmp_len) + { + zero_padding_len = SHA_BLOCK8_LEN - tmp_len; + } + + memcpy(padded_buffer2, p_handle->buffer, p_handle->buffered_length); + + padded_buffer2[p_handle->buffered_length] = SHA_STOP_BIT; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 1] = total_bit_length.byte.pos_8th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 2] = total_bit_length.byte.pos_7th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 3] = total_bit_length.byte.pos_6th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 4] = total_bit_length.byte.pos_5th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 5] = total_bit_length.byte.pos_4th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 6] = total_bit_length.byte.pos_3rd; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 7] = total_bit_length.byte.pos_2nd; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 8] = total_bit_length.byte.pos_1st; + + rsip_ret = + p_func->p_final((const uint32_t *) padded_buffer2, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (uint32_t *) p_mac, + r_rsip_byte_to_word_convert(p_handle->buffered_length + zero_padding_len + + SHA_PADDING_DATA_LEN)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_resume_final (rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t cmd_key_type = get_cmd_kdf_hmac_alg(key_type_ext.alg); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_resume(&cmd_key_type, + (uint32_t *) p_handle->wrapped_key.p_value, + p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t enc_msg_len[1] = {0U}; + uint8_t padded_buffer2[SHA_BLOCK8_LEN * 2] = {0}; + uint32_t total_length = p_handle->total_length + p_handle->buffered_length; + uint32_t zero_padding_len = 0; + uint32_t tmp_len = (p_handle->buffered_length + SHA_PADDING_DATA_LEN) & (SHA_BLOCK8_LEN - 1); + rsip_dword_data_t total_bit_length = {.dword = (total_length << 3) + HMAC_SHA256_MESSAGE_ADD_LEN}; + + if (0 != tmp_len) + { + zero_padding_len = SHA_BLOCK8_LEN - tmp_len; + } + + memcpy(padded_buffer2, p_handle->buffer, p_handle->buffered_length); + + padded_buffer2[p_handle->buffered_length] = SHA_STOP_BIT; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 1] = total_bit_length.byte.pos_8th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 2] = total_bit_length.byte.pos_7th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 3] = total_bit_length.byte.pos_6th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 4] = total_bit_length.byte.pos_5th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 5] = total_bit_length.byte.pos_4th; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 6] = total_bit_length.byte.pos_3rd; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 7] = total_bit_length.byte.pos_2nd; + padded_buffer2[p_handle->buffered_length + zero_padding_len + 8] = total_bit_length.byte.pos_1st; + + rsip_ret = + p_func->p_final((const uint32_t *) padded_buffer2, + NULL, + enc_msg_len, + (uint32_t *) p_mac, + r_rsip_byte_to_word_convert(p_handle->buffered_length + zero_padding_len + + SHA_PADDING_DATA_LEN)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_final (rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_suspend(p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_kdf_hmac_resume_final(p_handle, p_mac); + } + + return rsip_ret; +} + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Set sha final block. + * + * @param[in] p_message Last block_message. + * @param[in] message_length Byte length of message.(Must be (128 - 9)byte or less) + * @param[in] total_message_length Total message length. + * @param[out] p_last_block Last block data (This area is need 128byte). + * @param[out] p_last_block_length Last block length. + * + * @return void. + **********************************************************************************************************************/ +static void set_sha2_final_block (const uint8_t * p_message, + uint64_t message_length, + uint64_t total_message_length, + uint8_t * p_last_block, + uint32_t * p_last_block_length) +{ + rsip_dword_data_t total_bit_length = {.dword = total_message_length << 3}; + + memset(&p_last_block[message_length], 0, (size_t) (SHA_BLOCK8_LEN * 2 - message_length)); + memcpy(p_last_block, p_message, (size_t) message_length); + p_last_block[message_length] = SHA_STOP_BIT; + + if (SHA_BLOCK8_LEN >= (SHA_PADDING_DATA_LEN + message_length)) /* another block unnecessary */ + { + /* Casting uint64_t data to uint8_t data array. */ + p_last_block[SHA_BLOCK8_LEN - 8] = total_bit_length.byte.pos_8th; + p_last_block[SHA_BLOCK8_LEN - 7] = total_bit_length.byte.pos_7th; + p_last_block[SHA_BLOCK8_LEN - 6] = total_bit_length.byte.pos_6th; + p_last_block[SHA_BLOCK8_LEN - 5] = total_bit_length.byte.pos_5th; + p_last_block[SHA_BLOCK8_LEN - 4] = total_bit_length.byte.pos_4th; + p_last_block[SHA_BLOCK8_LEN - 3] = total_bit_length.byte.pos_3rd; + p_last_block[SHA_BLOCK8_LEN - 2] = total_bit_length.byte.pos_2nd; + p_last_block[SHA_BLOCK8_LEN - 1] = total_bit_length.byte.pos_1st; + p_last_block_length[0] = SHA_BLOCK8_LEN; + } + else + { + /* another block necessary */ + /* Casting uint64_t data to uint8_t data array. */ + p_last_block[(2 * SHA_BLOCK8_LEN) - 8] = total_bit_length.byte.pos_8th; + p_last_block[(2 * SHA_BLOCK8_LEN) - 7] = total_bit_length.byte.pos_7th; + p_last_block[(2 * SHA_BLOCK8_LEN) - 6] = total_bit_length.byte.pos_6th; + p_last_block[(2 * SHA_BLOCK8_LEN) - 5] = total_bit_length.byte.pos_5th; + p_last_block[(2 * SHA_BLOCK8_LEN) - 4] = total_bit_length.byte.pos_4th; + p_last_block[(2 * SHA_BLOCK8_LEN) - 3] = total_bit_length.byte.pos_3rd; + p_last_block[(2 * SHA_BLOCK8_LEN) - 2] = total_bit_length.byte.pos_2nd; + p_last_block[(2 * SHA_BLOCK8_LEN) - 1] = total_bit_length.byte.pos_1st; + p_last_block_length[0] = 2 * SHA_BLOCK8_LEN; + } +} + +RSIP_PRV_STATIC_INLINE uint32_t get_cmd_kdf_hmac_alg (uint8_t alg) +{ + uint32_t ret = bswap_32big(0); + + if (RSIP_PRV_ALG_HMAC != alg) + { + ret = bswap_32big(1); + } + + return ret; +} + +RSIP_PRV_STATIC_INLINE const rsip_func_subset_kdf_hmac_t * get_kdf_hmac_func (rsip_key_type_extend_t key_type_ext) +{ + FSP_PARAMETER_NOT_USED(key_type_ext); + + return &gp_func_kdf_hmac_sha1sha2; +} + +#endif /* 1U == RSIP_PRV_HASH_IP_TYPE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private_sub2.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private_sub2.c new file mode 100644 index 0000000000..c996b234c2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/private/r_rsip_private_sub2.c @@ -0,0 +1,911 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_private.h" + +#if (3U == RSIP_PRV_HASH_IP_TYPE) || (5U == RSIP_PRV_HASH_IP_TYPE) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + + #define RSIP_PRV_SHA_INIT_VAL1 (0xffffffffU) + #define RSIP_PRV_SHA_INIT_VAL2 (0xfffffc00U) + #define RSIP_PRV_INTERNAL_STATE_OVERWRITE_BASE_SHA1SHA2 (16U) + #define RSIP_PRV_INTERNAL_STATE_OVERWRITE_BASE_SHA3 (50U) + + #define RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER (16U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum e_rsip_hmac_cmd +{ + RSIP_HMAC_CMD_SIGN = 0U, + RSIP_HMAC_CMD_VERIFY = 1U, +} rsip_hmac_cmd_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static bool hash_type_is_sha3(rsip_hash_type_t hash_type); +static bool hmac_type_is_sha3(rsip_key_type_extend_t key_type_ext); + +static void overwrite_internal_state_sha1sha2(uint32_t * internal_state, uint64_t buffered_length, + uint64_t input_length); +static void overwrite_internal_state_sha3(uint32_t * internal_state, uint64_t buffered_length); + +static void overwrite_internal_state_sha(rsip_sha_handle_t * p_handle); +static void overwrite_internal_state_hmac(rsip_hmac_handle_t * p_handle); +static void overwrite_internal_state_kdf_sha(rsip_kdf_sha_handle_t * p_handle); +static void overwrite_internal_state_kdf_hmac(rsip_kdf_hmac_handle_t * p_handle); + +RSIP_PRV_STATIC_INLINE const rsip_func_subset_sha_t * get_hash_func(rsip_hash_type_t hash_type); +RSIP_PRV_STATIC_INLINE const rsip_func_subset_hmac_t * get_hmac_func(rsip_key_type_extend_t key_type_ext); +RSIP_PRV_STATIC_INLINE const rsip_func_subset_kdf_sha_t * get_kdf_hash_func(rsip_hash_type_t hash_type); +RSIP_PRV_STATIC_INLINE const rsip_func_subset_kdf_hmac_t * get_kdf_hmac_func(rsip_key_type_extend_t key_type_ext); +RSIP_PRV_STATIC_INLINE uint32_t get_cmd_kdf_hmac_alg(uint8_t alg); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static const uint32_t gs_sha_hash_type[] = +{ + [RSIP_HASH_TYPE_SHA1] = BSWAP_32BIG_C(0U), + [RSIP_HASH_TYPE_SHA224] = BSWAP_32BIG_C(1U), + [RSIP_HASH_TYPE_SHA256] = BSWAP_32BIG_C(2U), + [RSIP_HASH_TYPE_SHA384] = BSWAP_32BIG_C(5U), + [RSIP_HASH_TYPE_SHA512] = BSWAP_32BIG_C(6U), + [RSIP_HASH_TYPE_SHA512_224] = BSWAP_32BIG_C(3U), + [RSIP_HASH_TYPE_SHA512_256] = BSWAP_32BIG_C(4U), + [RSIP_HASH_TYPE_SHA3_224] = BSWAP_32BIG_C(0U), + [RSIP_HASH_TYPE_SHA3_256] = BSWAP_32BIG_C(1U), + [RSIP_HASH_TYPE_SHA3_384] = BSWAP_32BIG_C(2U), + [RSIP_HASH_TYPE_SHA3_512] = BSWAP_32BIG_C(3U), +}; + +static const uint32_t gs_hmac_hash_type[] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1] = BSWAP_32BIG_C(0U), + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224] = BSWAP_32BIG_C(1U), + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = BSWAP_32BIG_C(2U), + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = BSWAP_32BIG_C(5U), + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = BSWAP_32BIG_C(6U), + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_224] = BSWAP_32BIG_C(3U), + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_256] = BSWAP_32BIG_C(4U), +}; + +static const uint32_t gs_hmac_cmd[] = +{ + [RSIP_HMAC_CMD_SIGN] = BSWAP_32BIG_C(0U), + [RSIP_HMAC_CMD_VERIFY] = BSWAP_32BIG_C(1U), +}; + +static const uint32_t gs_kdf_sha_hash_type[] = +{ + [RSIP_HASH_TYPE_SHA256] = BSWAP_32BIG_C(0U), + [RSIP_HASH_TYPE_SHA384] = BSWAP_32BIG_C(1U), +}; + +static const uint32_t gs_kdf_hmac_hash_type[] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = BSWAP_32BIG_C(0U), + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = BSWAP_32BIG_C(1U), + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = BSWAP_32BIG_C(2U), +}; + +static const uint32_t gs_sha_msg_len_multi[2] = +{ + RSIP_PRV_SHA_INIT_VAL1, RSIP_PRV_SHA_INIT_VAL2 +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_sha_hash_init_update (rsip_sha_handle_t * p_handle, const uint8_t * p_message, + uint64_t message_length) +{ + const rsip_func_subset_sha_t * p_func = get_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_init(&gs_sha_hash_type[p_handle->type], gs_sha_msg_len_multi); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha_hash_resume_update (rsip_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + const rsip_func_subset_sha_t * p_func = get_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_resume(&gs_sha_hash_type[p_handle->type], p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha_hash_update (rsip_sha_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + const rsip_func_subset_sha_t * p_func = get_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + return p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); +} + +rsip_ret_t r_rsip_sha_hash_suspend (rsip_sha_handle_t * p_handle) +{ + const rsip_func_subset_sha_t * p_func = get_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + return p_func->p_suspend(p_handle->internal_state); +} + +rsip_ret_t r_rsip_sha_hash_init_final (rsip_hash_type_t hash_type, + const uint8_t * p_message, + uint64_t message_length, + uint8_t * p_digest) +{ + const rsip_func_subset_sha_t * p_func = get_hash_func(hash_type); + + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(message_length), + r_rsip_byte_to_bit_convert_lower(message_length) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_init(&gs_sha_hash_type[hash_type], msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_final((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) p_digest); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha_hash_resume_final (rsip_sha_handle_t * p_handle, uint8_t * p_digest) +{ + const rsip_func_subset_sha_t * p_func = get_hash_func(p_handle->type); + + overwrite_internal_state_sha(p_handle); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_resume(&gs_sha_hash_type[p_handle->type], p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_final((const uint32_t *) p_handle->buffer, + r_rsip_byte_to_word_convert(p_handle->buffered_length), + (uint32_t *) p_digest); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_sha_hash_final (rsip_sha_handle_t * p_handle, uint8_t * p_digest) +{ + const rsip_func_subset_sha_t * p_func = get_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_suspend(p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_sha_hash_resume_final(p_handle, p_digest); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_init_update (rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + rsip_wrapped_key_t * p_wrapped_key = &p_handle->wrapped_key; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_init((uint32_t *) p_wrapped_key->p_value, + &gs_hmac_hash_type[key_type_ext.subtype], + gs_sha_msg_len_multi, + r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type))); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_update (rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + rsip_wrapped_key_t * p_wrapped_key = &p_handle->wrapped_key; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_resume((uint32_t *) p_wrapped_key->p_value, + &gs_hmac_hash_type[key_type_ext.subtype], + p_handle->internal_state, + r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type))); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_update (rsip_hmac_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + return p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); +} + +rsip_ret_t r_rsip_hmac_suspend (rsip_hmac_handle_t * p_handle) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + return p_func->p_suspend(p_handle->internal_state); +} + +rsip_ret_t r_rsip_hmac_init_final (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + uint8_t * p_mac) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(message_length), + r_rsip_byte_to_bit_convert_lower(message_length) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_init((uint32_t *) p_wrapped_key->p_value, + &gs_hmac_hash_type[key_type_ext.subtype], + msg_len, + r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type))); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + (const uint32_t *) p_message, + NULL, + NULL, + r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) p_mac); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_final (rsip_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + rsip_wrapped_key_t * p_wrapped_key = &p_handle->wrapped_key; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + overwrite_internal_state_hmac(p_handle); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_resume((uint32_t *) p_wrapped_key->p_value, + &gs_hmac_hash_type[key_type_ext.subtype], + p_handle->internal_state, + r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type))); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_SIGN], + (const uint32_t *) p_handle->buffer, + NULL, + NULL, + r_rsip_byte_to_word_convert(p_handle->buffered_length), + (uint32_t *) p_mac); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_final (rsip_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_suspend(p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_hmac_resume_final(p_handle, p_mac); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_init_verify (const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_message, + uint64_t message_length, + const uint8_t * p_mac, + uint32_t mac_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(message_length), + r_rsip_byte_to_bit_convert_lower(message_length) + }; + uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = + { + 0 + }; + memcpy(InData_MAC, p_mac, mac_length); + uint32_t mac_len[1] = + { + bswap_32big(mac_length) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_init((uint32_t *) p_wrapped_key->p_value, + &gs_hmac_hash_type[key_type_ext.subtype], + msg_len, + r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type))); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + (const uint32_t *) p_message, + InData_MAC, + mac_len, + r_rsip_byte_to_word_convert((uint32_t) message_length), + (uint32_t *) NULL); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_resume_verify (rsip_hmac_handle_t * p_handle, const uint8_t * p_mac, uint32_t mac_length) +{ + rsip_wrapped_key_t * p_wrapped_key = &p_handle->wrapped_key; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + overwrite_internal_state_hmac(p_handle); + + uint32_t InData_MAC[RSIP_PRV_WORD_SIZE_HMAC_MAC_BUFFER] = + { + 0 + }; + memcpy(InData_MAC, p_mac, mac_length); + uint32_t mac_len[1] = + { + bswap_32big(mac_length) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_resume((uint32_t *) p_wrapped_key->p_value, + &gs_hmac_hash_type[key_type_ext.subtype], + p_handle->internal_state, + r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type))); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_final(&gs_hmac_cmd[RSIP_HMAC_CMD_VERIFY], + (const uint32_t *) p_handle->buffer, + InData_MAC, + mac_len, + r_rsip_byte_to_word_convert(p_handle->buffered_length), + (uint32_t *) NULL); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_hmac_verify (rsip_hmac_handle_t * p_handle, const uint8_t * p_mac, uint32_t mac_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_hmac_t * p_func = get_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_suspend(p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_hmac_resume_verify(p_handle, p_mac, mac_length); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_init_update (rsip_kdf_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + const rsip_func_subset_kdf_sha_t * p_func = get_kdf_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_init(&gs_kdf_sha_hash_type[p_handle->type], gs_sha_msg_len_multi); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t msg1_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length1))}; + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->actual_wrapped_msg_length))}; + uint32_t msg2_len[1] = {bswap_32big(r_rsip_byte_to_word_convert((uint32_t) message_length))}; + + rsip_ret = p_func->p_update((const uint32_t *) p_handle->buffer1, + msg1_len, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (const uint32_t *) p_message, + msg2_len); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_resume_update (rsip_kdf_sha_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + const rsip_func_subset_kdf_sha_t * p_func = get_kdf_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_resume(&gs_kdf_sha_hash_type[p_handle->type], p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t msg1_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length1))}; + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->actual_wrapped_msg_length))}; + uint32_t msg2_len[1] = {bswap_32big(r_rsip_byte_to_word_convert((uint32_t) message_length))}; + + rsip_ret = p_func->p_update((const uint32_t *) p_handle->buffer1, + msg1_len, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (const uint32_t *) p_message, + msg2_len); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_update (rsip_kdf_sha_handle_t * p_handle, const uint8_t * p_message, uint64_t message_length) +{ + const rsip_func_subset_kdf_sha_t * p_func = get_kdf_hash_func(p_handle->type); + uint32_t msg1_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length1))}; + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->actual_wrapped_msg_length))}; + uint32_t msg2_len[1] = {bswap_32big(r_rsip_byte_to_word_convert((uint32_t) message_length))}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_update((const uint32_t *) p_handle->buffer1, + msg1_len, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (const uint32_t *) p_message, + msg2_len); + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_suspend (rsip_kdf_sha_handle_t * p_handle) +{ + const rsip_func_subset_kdf_sha_t * p_func = get_kdf_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + return p_func->p_suspend(p_handle->internal_state); +} + +rsip_ret_t r_rsip_kdf_sha_init_final (rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest) +{ + const rsip_func_subset_kdf_sha_t * p_func = get_kdf_hash_func(p_handle->type); + uint64_t total_length = p_handle->buffered_length1 + p_handle->actual_wrapped_msg_length + + p_handle->buffered_length2; + + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(total_length), + r_rsip_byte_to_bit_convert_lower(total_length) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_init(&gs_kdf_sha_hash_type[p_handle->type], msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t msg1_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length1))}; + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->actual_wrapped_msg_length))}; + uint32_t msg2_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length2))}; + + rsip_ret = p_func->p_final((const uint32_t *) p_handle->buffer1, + msg1_len, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (const uint32_t *) p_handle->buffer2, + msg2_len, + (uint32_t *) p_digest); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_resume_final (rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest) +{ + const rsip_func_subset_kdf_sha_t * p_func = get_kdf_hash_func(p_handle->type); + + overwrite_internal_state_kdf_sha(p_handle); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_resume(&gs_kdf_sha_hash_type[p_handle->type], p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t msg1_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length1))}; + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->actual_wrapped_msg_length))}; + uint32_t msg2_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length2))}; + + rsip_ret = p_func->p_final((const uint32_t *) p_handle->buffer1, + msg1_len, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (const uint32_t *) p_handle->buffer2, + msg2_len, + (uint32_t *) p_digest); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_sha_final (rsip_kdf_sha_handle_t * p_handle, uint8_t * p_digest) +{ + const rsip_func_subset_kdf_sha_t * p_func = get_kdf_hash_func(p_handle->type); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_suspend(p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_kdf_sha_resume_final(p_handle, p_digest); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_init_update (rsip_kdf_hmac_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t cmd_key_type = get_cmd_kdf_hmac_alg(key_type_ext.alg); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_init(&cmd_key_type, (const uint32_t *) p_handle->wrapped_key.p_value, + &gs_kdf_hmac_hash_type[key_type_ext.subtype], gs_sha_msg_len_multi); + + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->wrapped_msg_length))}; + rsip_ret = + p_func->p_enc_update((const uint32_t *) p_handle->wrapped_msg, enc_msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_resume_update (rsip_kdf_hmac_handle_t * p_handle, + const uint8_t * p_message, + uint64_t message_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t cmd_key_type = get_cmd_kdf_hmac_alg(key_type_ext.alg); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_resume(&cmd_key_type, (uint32_t *) p_handle->wrapped_key.p_value, + &gs_kdf_hmac_hash_type[key_type_ext.subtype], p_handle->internal_state); + + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->wrapped_msg_length))}; + rsip_ret = + p_func->p_enc_update((const uint32_t *) p_handle->wrapped_msg, enc_msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_update (rsip_kdf_hmac_handle_t * p_handle, const uint8_t * p_message, + uint64_t message_length) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + uint32_t enc_msg_len[1] = {0}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_enc_update(NULL, enc_msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_update((const uint32_t *) p_message, r_rsip_byte_to_word_convert((uint32_t) message_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_suspend (rsip_kdf_hmac_handle_t * p_handle) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + return p_func->p_suspend(p_handle->internal_state); +} + +rsip_ret_t r_rsip_kdf_hmac_init_final (rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + uint64_t total_length = p_handle->buffered_length + p_handle->actual_wrapped_msg_length; + + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(total_length), + r_rsip_byte_to_bit_convert_lower(total_length) + }; + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t cmd_key_type = get_cmd_kdf_hmac_alg(key_type_ext.alg); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_init(&cmd_key_type, (const uint32_t *) p_handle->wrapped_key.p_value, + &gs_kdf_hmac_hash_type[key_type_ext.subtype], msg_len); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t enc_msg_len[1] = {bswap_32big(r_rsip_byte_to_word_convert(p_handle->wrapped_msg_length))}; + rsip_ret = + p_func->p_final((const uint32_t *) p_handle->buffer, + (const uint32_t *) p_handle->wrapped_msg, + enc_msg_len, + (uint32_t *) p_mac, + r_rsip_byte_to_word_convert(p_handle->buffered_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_resume_final (rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + overwrite_internal_state_kdf_hmac(p_handle); + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + uint32_t cmd_key_type = get_cmd_kdf_hmac_alg(key_type_ext.alg); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_resume(&cmd_key_type, (uint32_t *) p_handle->wrapped_key.p_value, + &gs_kdf_hmac_hash_type[key_type_ext.subtype], p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + uint32_t enc_msg_len[1] = {0}; + rsip_ret = + p_func->p_final((const uint32_t *) p_handle->buffer, + NULL, + enc_msg_len, + (uint32_t *) p_mac, + r_rsip_byte_to_word_convert(p_handle->buffered_length)); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_kdf_hmac_final (rsip_kdf_hmac_handle_t * p_handle, uint8_t * p_mac) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + const rsip_func_subset_kdf_hmac_t * p_func = get_kdf_hmac_func(key_type_ext); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_suspend(p_handle->internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = r_rsip_kdf_hmac_resume_final(p_handle, p_mac); + } + + return rsip_ret; +} + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +bool hash_type_is_sha3 (rsip_hash_type_t hash_type) +{ + bool ret = false; + + switch (hash_type) + { + case RSIP_HASH_TYPE_SHA1: + case RSIP_HASH_TYPE_SHA224: + case RSIP_HASH_TYPE_SHA256: + case RSIP_HASH_TYPE_SHA384: + case RSIP_HASH_TYPE_SHA512: + case RSIP_HASH_TYPE_SHA512_224: + case RSIP_HASH_TYPE_SHA512_256: + { + ret = false; + break; + } + + default: + { + ret = true; + } + } + + return ret; +} + +bool hmac_type_is_sha3 (rsip_key_type_extend_t key_type_ext) +{ + bool ret = false; + + switch (key_type_ext.subtype) + { + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1: + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224: + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256: + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384: + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512: + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_224: + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_256: + { + ret = false; + break; + } + + default: + { + ret = true; + } + } + + return ret; +} + +static void overwrite_internal_state_sha1sha2 (uint32_t * internal_state, + uint64_t buffered_length, + uint64_t input_length) +{ + #if 5U == RSIP_PRV_HASH_IP_TYPE + uint64_t total_length = buffered_length + input_length; + internal_state[RSIP_PRV_INTERNAL_STATE_OVERWRITE_BASE_SHA1SHA2] = + r_rsip_byte_to_bit_convert_lower(total_length); + internal_state[RSIP_PRV_INTERNAL_STATE_OVERWRITE_BASE_SHA1SHA2 + + 1] = r_rsip_byte_to_bit_convert_upper(total_length); + #else + FSP_PARAMETER_NOT_USED(input_length); + #endif + internal_state[RSIP_PRV_INTERNAL_STATE_OVERWRITE_BASE_SHA1SHA2 + 2] = r_rsip_byte_to_bit_convert_upper( + buffered_length); + internal_state[RSIP_PRV_INTERNAL_STATE_OVERWRITE_BASE_SHA1SHA2 + 3] = r_rsip_byte_to_bit_convert_lower( + buffered_length); +} + +static void overwrite_internal_state_sha3 (uint32_t * internal_state, uint64_t buffered_length) +{ + internal_state[RSIP_PRV_INTERNAL_STATE_OVERWRITE_BASE_SHA3] = r_rsip_byte_to_bit_convert_upper(buffered_length); + internal_state[RSIP_PRV_INTERNAL_STATE_OVERWRITE_BASE_SHA3 + 1] = r_rsip_byte_to_bit_convert_lower(buffered_length); +} + +void overwrite_internal_state_sha (rsip_sha_handle_t * p_handle) +{ + if (hash_type_is_sha3(p_handle->type)) + { + overwrite_internal_state_sha3(p_handle->internal_state, p_handle->buffered_length); + } + else + { + overwrite_internal_state_sha1sha2(p_handle->internal_state, p_handle->buffered_length, p_handle->total_length); + } +} + +void overwrite_internal_state_hmac (rsip_hmac_handle_t * p_handle) +{ + if (hmac_type_is_sha3(r_rsip_key_type_parse(p_handle->wrapped_key.type))) + { + overwrite_internal_state_sha3(p_handle->internal_state, p_handle->buffered_length); + } + else + { + overwrite_internal_state_sha1sha2(p_handle->internal_state, p_handle->buffered_length, p_handle->total_length); + } +} + +void overwrite_internal_state_kdf_sha (rsip_kdf_sha_handle_t * p_handle) +{ + overwrite_internal_state_sha1sha2(p_handle->internal_state, p_handle->buffered_length2, p_handle->total_length); +} + +void overwrite_internal_state_kdf_hmac (rsip_kdf_hmac_handle_t * p_handle) +{ + overwrite_internal_state_sha1sha2(p_handle->internal_state, p_handle->buffered_length, p_handle->total_length); +} + +RSIP_PRV_STATIC_INLINE const rsip_func_subset_sha_t * get_hash_func (rsip_hash_type_t hash_type) +{ + return hash_type_is_sha3(hash_type) ? &gp_func_sha3 : &gp_func_sha1sha2; +} + +RSIP_PRV_STATIC_INLINE const rsip_func_subset_hmac_t * get_hmac_func (rsip_key_type_extend_t key_type_ext) +{ + return hmac_type_is_sha3(key_type_ext) ? &gp_func_hmac_sha3 : &gp_func_hmac_sha1sha2; +} + +RSIP_PRV_STATIC_INLINE const rsip_func_subset_kdf_sha_t * get_kdf_hash_func (rsip_hash_type_t hash_type) +{ + FSP_PARAMETER_NOT_USED(hash_type); + + return &gp_func_kdf_sha1sha2; +} + +RSIP_PRV_STATIC_INLINE const rsip_func_subset_kdf_hmac_t * get_kdf_hmac_func (rsip_key_type_extend_t key_type_ext) +{ + FSP_PARAMETER_NOT_USED(key_type_ext); + + return &gp_func_kdf_hmac_sha1sha2; +} + +RSIP_PRV_STATIC_INLINE uint32_t get_cmd_kdf_hmac_alg (uint8_t alg) +{ + return (RSIP_PRV_ALG_HMAC == alg) ? bswap_32big(0) : bswap_32big(1); +} + +#endif /* (3U == RSIP_PRV_HASH_IP_TYPE) || (5U == RSIP_PRV_HASH_IP_TYPE) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip.c new file mode 100644 index 0000000000..544c50822a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip.c @@ -0,0 +1,1194 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Function pointers for initializing g_rsip_on_rsip */ +typedef fsp_err_t (* rsip_api_ecdh_key_agree_t)(rsip_ctrl_t * const, rsip_wrapped_key_t const * const, + rsip_wrapped_key_t const * const, + rsip_wrapped_secret_abstractor_t * const); +typedef fsp_err_t (* rsip_api_ecdh_plain_key_agree_t)(rsip_ctrl_t * const, rsip_wrapped_key_t const * const, + uint8_t const * const, rsip_wrapped_secret_abstractor_t * const); +typedef fsp_err_t (* rsip_api_sha_suspend_t)(rsip_ctrl_t * const, rsip_sha_handle_abstractor_t * const); +typedef fsp_err_t (* rsip_api_sha_resume_t)(rsip_ctrl_t * const, rsip_sha_handle_abstractor_t const * const); +typedef fsp_err_t (* rsip_api_hmac_suspend_t)(rsip_ctrl_t * const, rsip_hmac_handle_abstractor_t * const); +typedef fsp_err_t (* rsip_api_hmac_resume_t)(rsip_ctrl_t * const, rsip_hmac_handle_abstractor_t const * const); +typedef fsp_err_t (* rsip_api_pki_verified_cert_info_export_t)(rsip_ctrl_t * const, + rsip_verified_cert_info_abstractor_t * const); +typedef fsp_err_t (* rsip_api_pki_verified_cert_info_import_t)(rsip_ctrl_t * const, + rsip_verified_cert_info_abstractor_t const * const); +typedef fsp_err_t (* rsip_api_kdf_sha_ecdh_secret_update_t)(rsip_ctrl_t * const, + rsip_wrapped_secret_abstractor_t const * const); +typedef fsp_err_t (* rsip_api_kdf_sha_suspend_t)(rsip_ctrl_t * const, rsip_kdf_sha_handle_abstractor_t * const); +typedef fsp_err_t (* rsip_api_kdf_sha_resume_t)(rsip_ctrl_t * const, rsip_kdf_sha_handle_abstractor_t const * const); +typedef fsp_err_t (* rsip_api_kdf_hmac_ecdh_secret_key_import_t)(rsip_ctrl_t * const, + rsip_wrapped_secret_abstractor_t const * const, + rsip_wrapped_key_t * const); +typedef fsp_err_t (* rsip_api_kdf_hmac_ecdh_secret_update_t)(rsip_ctrl_t * const, + rsip_wrapped_secret_abstractor_t const * const); +typedef fsp_err_t (* rsip_api_kdf_hmac_suspend_t)(rsip_ctrl_t * const, rsip_kdf_hmac_handle_abstractor_t * const); +typedef fsp_err_t (* rsip_api_kdf_hmac_resume_t)(rsip_ctrl_t * const, rsip_kdf_hmac_handle_abstractor_t const * const); + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static rsip_func_key_generate_t select_func_key_generate(rsip_key_type_extend_t key_type_ext); +static rsip_func_key_pair_generate_t select_func_key_pair_generate(rsip_key_type_extend_t key_type_ext); +static rsip_func_encrypted_key_wrap_t select_func_encrypted_key_wrap(rsip_key_type_extend_t key_type_ext); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static const uint32_t gs_ecc_param1_pos[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_256_QX, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_384_QX, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_521_QX, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_256_QX, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_256_QX, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_384_QX, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_512_QX, + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_EDWARDS25519_Q +}; + +static const uint32_t gs_ecc_param1_len[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_BYTE_SIZE_ECC_384_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_BYTE_SIZE_ECC_521_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_BYTE_SIZE_ECC_384_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_BYTE_SIZE_ECC_512_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM +}; + +static const uint32_t gs_ecc_param2_pos[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_256_QY, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_384_QY, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_521_QY, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_256_QY, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_256_QY, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_384_QY, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_512_QY, + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = 0 +}; + +static const uint32_t gs_ecc_param2_len[RSIP_PRV_KEY_SUBTYPE_ECC_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1] = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1] = RSIP_PRV_BYTE_SIZE_ECC_384_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP521R1] = RSIP_PRV_BYTE_SIZE_ECC_521_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_SECP256K1] = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1] = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1] = RSIP_PRV_BYTE_SIZE_ECC_384_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1] = RSIP_PRV_BYTE_SIZE_ECC_512_PARAM, + [RSIP_PRV_KEY_SUBTYPE_ECC_EDWARDS25519] = 0 +}; + +static const uint32_t gs_rsa_n_pos = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_N; + +static const uint32_t gs_rsa_n_len[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_1024] = RSIP_PRV_BYTE_SIZE_RSA_1024_N, + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_BYTE_SIZE_RSA_2048_N, + [RSIP_PRV_KEY_SUBTYPE_RSA_3072] = RSIP_PRV_BYTE_SIZE_RSA_3072_N, + [RSIP_PRV_KEY_SUBTYPE_RSA_4096] = RSIP_PRV_BYTE_SIZE_RSA_4096_N +}; + +static const uint32_t gs_rsa_e_pos[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_1024] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_1024_E, + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_2048_E, + [RSIP_PRV_KEY_SUBTYPE_RSA_3072] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_3072_E, + [RSIP_PRV_KEY_SUBTYPE_RSA_4096] = RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_4096_E +}; + +static const uint32_t gs_rsa_e_len = RSIP_PRV_BYTE_SIZE_RSA_E; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +const rsip_api_t g_rsip_on_rsip = +{ + .open = R_RSIP_Open, + .close = R_RSIP_Close, + .randomNumberGenerate = R_RSIP_RandomNumberGenerate, + .keyGenerate = R_RSIP_KeyGenerate, + .keyPairGenerate = R_RSIP_KeyPairGenerate, + .encryptedKeyWrap = R_RSIP_EncryptedKeyWrap, + .rfc3394_KeyWrap = R_RSIP_RFC3394_KeyWrap, + .rfc3394_KeyUnwrap = R_RSIP_RFC3394_KeyUnwrap, + .publicKeyExport = R_RSIP_PublicKeyExport, + .aesCipherInit = R_RSIP_AES_Cipher_Init, + .aesCipherUpdate = R_RSIP_AES_Cipher_Update, + .aesCipherFinish = R_RSIP_AES_Cipher_Finish, + .aesAeadInit = R_RSIP_AES_AEAD_Init, + .aesAeadLengthsSet = R_RSIP_AES_AEAD_LengthsSet, + .aesAeadAadUpdate = R_RSIP_AES_AEAD_AADUpdate, + .aesAeadUpdate = R_RSIP_AES_AEAD_Update, + .aesAeadFinish = R_RSIP_AES_AEAD_Finish, + .aesAeadVerify = R_RSIP_AES_AEAD_Verify, + .aesMacInit = R_RSIP_AES_MAC_Init, + .aesMacUpdate = R_RSIP_AES_MAC_Update, + .aesMacSignFinish = R_RSIP_AES_MAC_SignFinish, + .aesMacVerifyFinish = R_RSIP_AES_MAC_VerifyFinish, + .chacha20Init = R_RSIP_ChaCha20_Init, + .chacha20Update = R_RSIP_ChaCha20_Update, + .chacha20Finish = R_RSIP_ChaCha20_Finish, + .chacha20Poly1305Init = R_RSIP_ChaCha20_Poly1305_Init, + .chacha20Poly1305AadUpdate = R_RSIP_ChaCha20_Poly1305_AADUpdate, + .chacha20Poly1305Update = R_RSIP_ChaCha20_Poly1305_Update, + .chacha20Poly1305Finish = R_RSIP_ChaCha20_Poly1305_Finish, + .chacha20Poly1305Verify = R_RSIP_ChaCha20_Poly1305_Verify, + .ecdsaSign = R_RSIP_ECDSA_Sign, + .ecdsaVerify = R_RSIP_ECDSA_Verify, + .eddsaSign = R_RSIP_PureEdDSA_Sign, + .eddsaVerify = R_RSIP_PureEdDSA_Verify, + .ecdhKeyAgree = (rsip_api_ecdh_key_agree_t) R_RSIP_ECDH_KeyAgree, + .ecdhPlainKeyAgree = (rsip_api_ecdh_plain_key_agree_t) R_RSIP_ECDH_PlainKeyAgree, + .rsaEncrypt = R_RSIP_RSA_Encrypt, + .rsaDecrypt = R_RSIP_RSA_Decrypt, + .rsaesPkcs1V15Encrypt = R_RSIP_RSAES_PKCS1_V1_5_Encrypt, + .rsaesPkcs1V15Decrypt = R_RSIP_RSAES_PKCS1_V1_5_Decrypt, + .rsaesOaepEncrypt = R_RSIP_RSAES_OAEP_Encrypt, + .rsaesOaepDecrypt = R_RSIP_RSAES_OAEP_Decrypt, + .rsassaPkcs1V15Sign = R_RSIP_RSASSA_PKCS1_V1_5_Sign, + .rsassaPkcs1V15Verify = R_RSIP_RSASSA_PKCS1_V1_5_Verify, + .rsassaPssSign = R_RSIP_RSASSA_PSS_Sign, + .rsassaPssVerify = R_RSIP_RSASSA_PSS_Verify, + .shaCompute = R_RSIP_SHA_Compute, + .shaInit = R_RSIP_SHA_Init, + .shaUpdate = R_RSIP_SHA_Update, + .shaFinish = R_RSIP_SHA_Finish, + .shaSuspend = (rsip_api_sha_suspend_t) R_RSIP_SHA_Suspend, + .shaResume = (rsip_api_sha_resume_t) R_RSIP_SHA_Resume, + .hmacCompute = R_RSIP_HMAC_Compute, + .hmacVerify = R_RSIP_HMAC_Verify, + .hmacInit = R_RSIP_HMAC_Init, + .hmacUpdate = R_RSIP_HMAC_Update, + .hmacSignFinish = R_RSIP_HMAC_SignFinish, + .hmacVerifyFinish = R_RSIP_HMAC_VerifyFinish, + .hmacSuspend = (rsip_api_hmac_suspend_t) R_RSIP_HMAC_Suspend, + .hmacResume = (rsip_api_hmac_resume_t) R_RSIP_HMAC_Resume, + .pkiEcdsaCertVerify = R_RSIP_PKI_ECDSA_CertVerify, + .pkiVerifiedCertInfoExport = (rsip_api_pki_verified_cert_info_export_t) R_RSIP_PKI_VerifiedCertInfoExport, + .pkiVerifiedCertInfoImport = (rsip_api_pki_verified_cert_info_import_t) R_RSIP_PKI_VerifiedCertInfoImport, + .pkiCertKeyImport = R_RSIP_PKI_CertKeyImport, + .kdfShaInit = R_RSIP_KDF_SHA_Init, + .kdfShaEcdhSecretUpdate = (rsip_api_kdf_sha_ecdh_secret_update_t) R_RSIP_KDF_SHA_ECDHSecretUpdate, + .kdfShaUpdate = R_RSIP_KDF_SHA_Update, + .kdfShaFinish = R_RSIP_KDF_SHA_Finish, + .kdfShaSuspend = (rsip_api_kdf_sha_suspend_t) R_RSIP_KDF_SHA_Suspend, + .kdfShaResume = (rsip_api_kdf_sha_resume_t) R_RSIP_KDF_SHA_Resume, + .kdfHmacDkmKeyImport = R_RSIP_KDF_HMAC_DKMKeyImport, + .kdfHmacEcdhSecretKeyImport = (rsip_api_kdf_hmac_ecdh_secret_key_import_t) R_RSIP_KDF_HMAC_ECDHSecretKeyImport, + .kdfHmacInit = R_RSIP_KDF_HMAC_Init, + .kdfHmacDkmUpdate = R_RSIP_KDF_HMAC_DKMUpdate, + .kdfHmacEcdhSecretUpdate = (rsip_api_kdf_hmac_ecdh_secret_update_t) R_RSIP_KDF_HMAC_ECDHSecretUpdate, + .kdfHmacUpdate = R_RSIP_KDF_HMAC_Update, + .kdfHmacSignFinish = R_RSIP_KDF_HMAC_SignFinish, + .kdfHmacSuspend = (rsip_api_kdf_hmac_suspend_t) R_RSIP_KDF_HMAC_Suspend, + .kdfHmacResume = (rsip_api_kdf_hmac_resume_t) R_RSIP_KDF_HMAC_Resume, + .kdfDkmConcatenate = R_RSIP_KDF_DKMConcatenate, + .kdfDerivedKeyImport = R_RSIP_KDF_DerivedKeyImport, + .kdfDerivedIvWrap = R_RSIP_KDF_DerivedIVWrap, + .otfInit = R_RSIP_OTF_Init, +}; + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enables use of Renesas Secure IP functionality. + * + * Implements @ref rsip_api_t::open. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_INITIAL**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Internal key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Hardware initialization is failed. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption or hardware fault is detected. + * + * @note This version does not have an optional feature to disable TRNG initialization. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_Open (rsip_ctrl_t * const p_ctrl, rsip_cfg_t const * const p_cfg) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_cfg); + FSP_ERROR_RETURN(RSIP_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Set configuration */ + p_instance_ctrl->p_cfg = p_cfg; + + /* Device-specific sequence */ + rsip_ret_t rsip_ret = r_rsip_open(); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Set driver status to open */ + p_instance_ctrl->open = RSIP_OPEN; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + /* Treat PASS_1 as FAIL */ + case RSIP_RET_FAIL: + case RSIP_RET_PASS_1: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + /* Treat RETRY as FATAL */ + case RSIP_RET_RETRY: + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Disables use of Renesas Secure IP functionality. + * + * Implements @ref rsip_api_t::close. + * + * @par State transition + * @parblock + * This API can be executed in **except STATE_INITIAL**, and causes state transition. + * + * |Return value|Next state | + * |------------|-------------| + * |FSP_SUCCESS |STATE_INITIAL| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_Close (rsip_ctrl_t * const p_ctrl) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Device-specific sequence */ + rsip_ret_t rsip_ret = r_rsip_close(); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* Set driver status to close */ + p_instance_ctrl->open = 0U; + + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Generates a 128-bit random number. + * + * Implements @ref rsip_api_t::randomNumberGenerate. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RandomNumberGenerate (rsip_ctrl_t * const p_ctrl, uint8_t * const p_random) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_random); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + return r_rsip_random_number_generate(p_ctrl, p_random); +} + +/*******************************************************************************************************************//** + * Generates a wrapped symmetric key from a random number. + * In this API, user key input is unnecessary. + * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented. + * + * Implements @ref rsip_api_t::keyGenerate. + * + * @par Conditions + * Argument key_type must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128, @ref RSIP_KEY_TYPE_AES_256 + * - @ref RSIP_KEY_TYPE_XTS_AES_128, @ref RSIP_KEY_TYPE_XTS_AES_256 + * - @ref RSIP_KEY_TYPE_HMAC_SHA224, @ref RSIP_KEY_TYPE_HMAC_SHA256, @ref RSIP_KEY_TYPE_HMAC_SHA384, @ref RSIP_KEY_TYPE_HMAC_SHA512 + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL A generated AES-XTS key is illegal.(Data Key == Tweak Key) + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KeyGenerate (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t * const p_wrapped_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + rsip_func_key_generate_t p_func = select_func_key_generate(key_type_ext); // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((uint32_t *) p_wrapped_key->p_value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Generates a wrapped asymmetric key pair from a random number. In this API, user key input is unnecessary. + * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented. + * + * Implements @ref rsip_api_t::keyPairGenerate. + * + * @par Conditions + * Argument p_wrapped_public_key->type must be one of the following: + * - RSIP_KEY_TYPE_ECC_*_PUBLIC + * - RSIP_KEY_TYPE_RSA_*_PUBLIC + * Argument p_wrapped_private_key->type must be one of the following: + * - RSIP_KEY_TYPE_ECC_*_PRIVATE + * - RSIP_KEY_TYPE_RSA_*_PRIVATE + * Here, p_wrapped_public_key->type and p_wrapped_private_key->type must match. + * For example, if p_wrapped_public_key->type is @ref RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC, + * then p_wrapped_public_key->type must be @ref RSIP_KEY_TYPE_ECC_SECP256R1_PRIVATE. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KeyPairGenerate (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t * const p_wrapped_public_key, + rsip_wrapped_key_t * const p_wrapped_private_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t public_key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_key_pair_generate_t p_func = select_func_key_pair_generate(public_key_type_ext); // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_key_type_extend_t private_key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + FSP_ERROR_RETURN(((RSIP_PRV_ALG_ECC_PUBLIC == public_key_type_ext.alg) && + (RSIP_PRV_ALG_ECC_PRIVATE == private_key_type_ext.alg)) || + ((RSIP_PRV_ALG_RSA_PUBLIC == public_key_type_ext.alg) && + (RSIP_PRV_ALG_RSA_PRIVATE == private_key_type_ext.alg)) + , + FSP_ERR_NOT_ENABLED); // Check key type + FSP_ERROR_RETURN(private_key_type_ext.subtype == public_key_type_ext.subtype, FSP_ERR_NOT_ENABLED); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func((uint32_t *) p_wrapped_public_key->p_value, (uint32_t *) p_wrapped_private_key->p_value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Decrypts an encrypted user key with Key Update Key (KUK) and wrap it with the Hardware Unique Key (HUK). + * + * Implements @ref rsip_api_t::encryptedKeyWrap. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input KUK is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms" + **********************************************************************************************************************/ +fsp_err_t R_RSIP_EncryptedKeyWrap (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_key_update_key, + void const * const p_initial_vector, + void const * const p_encrypted_key, + rsip_wrapped_key_t * const p_wrapped_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_key_update_key); + FSP_ASSERT(p_key_update_key->p_value); + FSP_ASSERT(p_initial_vector); + FSP_ASSERT(p_encrypted_key); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + rsip_func_encrypted_key_wrap_t p_func = select_func_encrypted_key_wrap(key_type_ext); // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_KEY_TYPE_KUK == p_key_update_key->type, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Set KUK */ + r_rsip_kuk_set(p_key_update_key->p_value); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func((uint32_t const *) p_initial_vector, + (uint32_t const *) p_encrypted_key, + (uint32_t *) p_wrapped_key->p_value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * This function provides Key Wrap algorithm compliant with RFC3394. + * Using p_wrapped_kek to wrap p_wrapped_target_key, and output the result to p_rfc3394_wrapped_target_key. + * + * Implements @ref rsip_api_t::rfc3394_KeyWrap. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @par Conditions + * - Key type of p_wrapped_kek must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_256 + * - Key type of p_wrapped_target_key must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_256 + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RFC3394_KeyWrap (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_kek, + rsip_wrapped_key_t const * const p_wrapped_target_key, + uint8_t * const p_rfc3394_wrapped_target_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_kek); + FSP_ASSERT(p_wrapped_kek->p_value); + FSP_ASSERT(p_wrapped_target_key); + FSP_ASSERT(p_wrapped_target_key->p_value); + FSP_ASSERT(p_rfc3394_wrapped_target_key); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_kek->type); // Parse key type + rsip_func_rfc3394_key_wrap_t p_func = gp_func_rfc3394_key_wrap[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_AES == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Check key type and get parameters */ + uint32_t wrapped_key_type[1] = {0}; + uint32_t key_index_size = 0; + uint32_t wrapped_key_size = 0; + + FSP_ERROR_RETURN(FSP_SUCCESS == + get_rfc3394_key_wrap_param(p_wrapped_target_key->type, wrapped_key_type, &key_index_size, + &wrapped_key_size), + FSP_ERR_INVALID_ARGUMENT); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_wrapped_kek->p_value, + wrapped_key_type, + (const uint32_t *) p_wrapped_target_key->p_value, + (uint32_t *) p_rfc3394_wrapped_target_key, + key_index_size, + wrapped_key_size); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * This function provides Key Unwrap algorithm compliant with RFC3394. + * Using p_wrapped_kek to unwrap p_rfc3394_wrapped_target_key, and output the result to p_wrapped_target_key. + * + * Implements @ref rsip_api_t::rfc3394_KeyUnwrap. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @par Conditions + * - Key type of p_wrapped_kek must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_256 + * - The third argument key_type represents the key type of p_rfc3394_wrapped_target_key must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_256 + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RFC3394_KeyUnwrap (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_kek, + uint8_t const * const p_rfc3394_wrapped_target_key, + rsip_wrapped_key_t * const p_wrapped_target_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_kek); + FSP_ASSERT(p_wrapped_kek->p_value); + FSP_ASSERT(p_rfc3394_wrapped_target_key); + FSP_ASSERT(p_wrapped_target_key); + FSP_ASSERT(p_wrapped_target_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_kek->type); // Parse key type + rsip_func_rfc3394_key_unwrap_t p_func = gp_func_rfc3394_key_unwrap[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_AES == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Check key type and get parameters */ + uint32_t wrapped_key_type[1] = {0}; + uint32_t key_index_size = 0; + uint32_t wrapped_key_size = 0; + FSP_ERROR_RETURN(FSP_SUCCESS == + get_rfc3394_key_wrap_param(p_wrapped_target_key->type, wrapped_key_type, &key_index_size, + &wrapped_key_size), + FSP_ERR_INVALID_ARGUMENT); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_wrapped_kek->p_value, + wrapped_key_type, + (const uint32_t *) p_rfc3394_wrapped_target_key, + (uint32_t *) p_wrapped_target_key->p_value, + wrapped_key_size, + key_index_size); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Exports public key parameters from a wrapped key. + * + * Implements @ref rsip_api_t::publicKeyExport. + * + * Relative position of each elements in p_raw_public_key is shown in below: + * - ECC (RSIP_KEY_TYPE_ECC_*) : + * Qx placed first and Qy placed after that. + * |bit length|Qx|Qy| + * |----------|--|--| + * |256 |0 |32| + * |384 |0 |48| + * |512 |0 |64| + * |521 |0 |66| + * + * - RSA (RSIP_KEY_TYPE_RSA_*) : n placed first and e placed after that. + * |modulus|n|e | + * |-------|-|---| + * |1024 |0|128| + * |2048 |0|256| + * |3072 |0|384| + * |4096 |0|512| + * + * @par State transition + * This API can be executed in **any state** including STATE_INITIAL, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PublicKeyExport (rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t * const p_raw_public_key) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_raw_public_key); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + uint8_t * base = (uint8_t *) p_wrapped_public_key->p_value + r_rsip_word_to_byte_convert( + RSIP_CFG_WORD_SIZE_WRAPPED_PUBLIC_KEY_PREFIX); + uint32_t param1_pos; + uint32_t param1_len; + uint32_t param2_pos; + uint32_t param2_len; + + switch (key_type_ext.alg) + { + case RSIP_PRV_ALG_ECC_PUBLIC: + { + param1_pos = gs_ecc_param1_pos[key_type_ext.subtype]; + param1_len = gs_ecc_param1_len[key_type_ext.subtype]; + param2_pos = gs_ecc_param2_pos[key_type_ext.subtype]; + param2_len = gs_ecc_param2_len[key_type_ext.subtype]; + err = FSP_SUCCESS; + break; + } + + case RSIP_PRV_ALG_RSA_PUBLIC: + { + param1_pos = gs_rsa_n_pos; + param1_len = gs_rsa_n_len[key_type_ext.subtype]; + param2_pos = gs_rsa_e_pos[key_type_ext.subtype]; + param2_len = gs_rsa_e_len; + err = FSP_SUCCESS; + break; + } + + default: + { + /* Do nothing */ + } + } + + if (FSP_SUCCESS == err) + { + memcpy(p_raw_public_key, base + param1_pos, param1_len); + memcpy(p_raw_public_key + param1_len, base + param2_pos, param2_len); + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Generates a 128-bit random number. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_random Pointer to destination of random number. The length is 16 bytes. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t r_rsip_random_number_generate (rsip_ctrl_t * const p_ctrl, uint8_t * const p_random) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = gp_func_rng((uint32_t *) p_random); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Select primitive function of key generation from key type. + * + * @param[in] key_type_ext Extended key type. + * + * @return Pointer to function. + ***********************************************************************************************************************/ +static rsip_func_key_generate_t select_func_key_generate (rsip_key_type_extend_t key_type_ext) +{ + rsip_func_key_generate_t ret = NULL; + + switch (key_type_ext.alg) + { + case RSIP_PRV_ALG_AES: + { + ret = gp_func_key_generate_aes[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_XTS_AES: + { + ret = gp_func_key_generate_xts_aes[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_CHACHA: + { + ret = gp_func_key_generate_chacha[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_HMAC: + { + ret = gp_func_key_generate_hmac[key_type_ext.subtype]; + break; + } + + default: + { + /* Do nothing */ + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Select primitive function of key pair generation from public key type. + * + * @param[in] key_type_ext Extended key type. + * + * @return Pointer to function. + ***********************************************************************************************************************/ +static rsip_func_key_pair_generate_t select_func_key_pair_generate (rsip_key_type_extend_t key_type_ext) +{ + rsip_func_key_pair_generate_t ret = NULL; + + switch (key_type_ext.alg) + { + case RSIP_PRV_ALG_ECC_PUBLIC: + { + ret = gp_func_key_pair_generate_ecc[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_RSA_PUBLIC: + { + ret = gp_func_key_pair_generate_rsa[key_type_ext.subtype]; + break; + } + + default: + { + /* Do nothing */ + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Select primitive function of encrypted key wrapping from key type. + * + * @param[in] key_type_ext Extended key type. + * + * @return Pointer to function. + ***********************************************************************************************************************/ +static rsip_func_encrypted_key_wrap_t select_func_encrypted_key_wrap (rsip_key_type_extend_t key_type_ext) +{ + rsip_func_encrypted_key_wrap_t ret = NULL; + + switch (key_type_ext.alg) + { + case RSIP_PRV_ALG_AES: + { + ret = gp_func_encrypted_key_wrap_aes[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_XTS_AES: + { + ret = gp_func_encrypted_key_wrap_xts_aes[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_CHACHA: + { + ret = gp_func_encrypted_key_wrap_chacha[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_ECC_PUBLIC: + { + ret = gp_func_encrypted_key_wrap_ecc_pub[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_ECC_PRIVATE: + { + ret = gp_func_encrypted_key_wrap_ecc_priv[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_RSA_PUBLIC: + { + ret = gp_func_encrypted_key_wrap_rsa_pub[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_RSA_PRIVATE: + { + ret = gp_func_encrypted_key_wrap_rsa_priv[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_HMAC: + { + ret = gp_func_encrypted_key_wrap_hmac[key_type_ext.subtype]; + break; + } + + default: + { + /* Do nothing */ + } + } + + return ret; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_aes.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_aes.c new file mode 100644 index 0000000000..6287293eef --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_aes.c @@ -0,0 +1,2862 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define RSIP_PRV_BYTE_AES_CCM_B (128U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static fsp_err_t aes_init(rsip_ctrl_t * p_ctrl, + rsip_aes_cipher_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_initial_vector); +static fsp_err_t aes_update(rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint8_t * p_output, uint32_t input_length); +static fsp_err_t aes_finish(rsip_ctrl_t * p_ctrl); + +static fsp_err_t xts_init(rsip_ctrl_t * p_ctrl, + rsip_aes_cipher_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_initial_vector); +static fsp_err_t xts_update(rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint8_t * p_output, uint32_t input_length); +static fsp_err_t xts_finish(rsip_ctrl_t * p_ctrl); +static fsp_err_t xts_finish_primitive(rsip_func_subset_aes_xts_t * p_func, + const uint8_t * p_input, + uint8_t * p_output, + uint32_t input_length); + +static fsp_err_t gcm_init(rsip_ctrl_t * p_ctrl, + rsip_aes_aead_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_nonce, + uint32_t nonce_length); +static fsp_err_t gcm_aad_update(rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, uint32_t aad_length); +static fsp_err_t gcm_update(rsip_ctrl_t * p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length); +static fsp_err_t gcm_finish(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag); +static fsp_err_t gcm_verify(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length); +static fsp_err_t gcm_iv_prepare(const rsip_func_subset_aes_cipher_t * p_func_aes_cipher, + const uint8_t * p_initial_vector, + uint32_t initial_vector_length, + const rsip_wrapped_key_t * p_wrapped_key, + uint32_t * p_hashed_ivec); +static void gcm_aad_input_terminate(rsip_instance_ctrl_t * p_instance_ctrl); + +static fsp_err_t ccm_init(rsip_ctrl_t * p_ctrl, + rsip_aes_aead_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_nonce, + uint32_t nonce_length); +static fsp_err_t ccm_length_set(rsip_ctrl_t * const p_ctrl, + uint32_t const total_aad_length, + uint32_t const total_text_length, + uint32_t const tag_length); +static fsp_err_t ccm_aad_update(rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, uint32_t aad_length); +static fsp_err_t ccm_update(rsip_ctrl_t * p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length); +static fsp_err_t ccm_finish(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag); +static fsp_err_t ccm_verify(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length); +static void ccm_format(const uint8_t * nonce, + uint32_t nonce_len, + const uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len, + uint8_t * counter, + uint8_t * formatted_data, + uint32_t * formatted_length); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Starts AES cipher operation in confidentiality mode (ECB/CBC/CTR) or XTS mode. + * + * Implements @ref rsip_api_t::aesCipherInit. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_key must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128, @ref RSIP_KEY_TYPE_AES_192, @ref RSIP_KEY_TYPE_AES_256 + * - @ref RSIP_KEY_TYPE_XTS_AES_128, @ref RSIP_KEY_TYPE_XTS_AES_256 + * + * Argument mode must be the following: + * - AES key + * - @ref RSIP_AES_CIPHER_MODE_ECB_ENC, @ref RSIP_AES_CIPHER_MODE_ECB_DEC + * - @ref RSIP_AES_CIPHER_MODE_CBC_ENC, @ref RSIP_AES_CIPHER_MODE_CBC_DEC + * - @ref RSIP_AES_CIPHER_MODE_CTR + * - XTS-AES key + * - @ref RSIP_AES_CIPHER_MODE_XTS_ENC, @ref RSIP_AES_CIPHER_MODE_XTS_DEC + * + * Argument p_initial_vector must be the following: + * - [ECB] Not used + * - [CBC] Raw initial vector + * - [CTR] Raw nonce + * - [XTS] Raw initial vector + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_AES | + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_INVALID_ARGUMENT Input key type or mode is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input AES-XTS key value is illegal.(Data Key == Tweak Key) + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_Cipher_Init (rsip_ctrl_t * const p_ctrl, + rsip_aes_cipher_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_initial_vector) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ASSERT(p_initial_vector || (RSIP_AES_CIPHER_MODE_ECB_ENC == mode) || + (RSIP_AES_CIPHER_MODE_ECB_DEC == mode)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + + FSP_ERROR_RETURN((RSIP_PRV_ALG_AES == key_type_ext.alg) || (RSIP_PRV_ALG_XTS_AES == key_type_ext.alg), + FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type +#endif + + /* Check argument */ + fsp_err_t err = FSP_ERR_INVALID_ARGUMENT; + switch (mode) + { + /* AES-ECB, AES-CBC, AES-CTR */ + case RSIP_AES_CIPHER_MODE_ECB_ENC: + case RSIP_AES_CIPHER_MODE_ECB_DEC: + case RSIP_AES_CIPHER_MODE_CBC_ENC: + case RSIP_AES_CIPHER_MODE_CBC_DEC: + case RSIP_AES_CIPHER_MODE_CBC_ENC_WRAPPED_IV: + case RSIP_AES_CIPHER_MODE_CBC_DEC_WRAPPED_IV: + case RSIP_AES_CIPHER_MODE_CTR: + { + err = aes_init(p_ctrl, mode, p_wrapped_key, p_initial_vector); + break; + } + + /* AES-XTS */ + case RSIP_AES_CIPHER_MODE_XTS_ENC: + case RSIP_AES_CIPHER_MODE_XTS_DEC: + { + err = xts_init(p_ctrl, mode, p_wrapped_key, p_initial_vector); + break; + } + + default: + { + /* Invalid argument */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Encrypts plaintext or decrypts ciphertext. + * + * Implements @ref rsip_api_t::aesCipherUpdate. + * + * @par Conditions + * Argument length must be the following: + * - [ECB][CBC][CTR] 0 or a multiple of 16. + * - [XTS] 0 or greater than or equal to 16. + * + * @par Output length + * Output length to p_output is `length`. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES**, and does not cause any state transitions. + * + * In XTS mode, if once an integer other than 0 or a multiple of 16 is input, this API can no longer be called. + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE Input length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_Cipher_Update (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_input, + uint8_t * const p_output, + uint32_t const length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_input || (0 == length)); + FSP_ASSERT(p_output || (0 == length)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* AES-ECB, AES-CBC, AES-CTR */ + case RSIP_STATE_AES_CIPHER: + { + err = aes_update(p_ctrl, p_input, p_output, length); + break; + } + + /* AES-XTS (update) */ + case RSIP_STATE_AES_XTS_UPDATE: + { + err = xts_update(p_ctrl, p_input, p_output, length); + break; + } + + /* AES-XTS (finish) */ + case RSIP_STATE_AES_XTS_FINISH: + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finishes AES operation. + * + * Implements @ref rsip_api_t::aesCipherFinish. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_Cipher_Finish (rsip_ctrl_t * const p_ctrl) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* AES-ECB, AES-CBC, AES-CTR */ + case RSIP_STATE_AES_CIPHER: + { + err = aes_finish(p_ctrl); + break; + } + + /* AES-XTS (update, finish) */ + case RSIP_STATE_AES_XTS_UPDATE: + case RSIP_STATE_AES_XTS_FINISH: + { + err = xts_finish(p_ctrl); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Starts AES AEAD function. + * + * Implements @ref rsip_api_t::aesAeadInit. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_key must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_192 + * - @ref RSIP_KEY_TYPE_AES_256 + * + * Argument mode accepts any member of enumeration @ref rsip_aes_aead_mode_t. + * + * Argument nonce_length must be the following: + * - [GCM] Any length is accepted, but 12 bytes is generally recommended. + * - [CCM] 7 to 13 bytes. + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|--------------| + * |FSP_SUCCESS |STATE_AES_AEAD| + * |Others |No change | + * + * The next callable API functions in STATE_AES_AEAD are as below. + * - [GCM] R_RSIP_AES_AEAD_AADUpdate(), R_RSIP_AES_AEAD_Update(), R_RSIP_AES_AEAD_Finish() (encryption), + * R_RSIP_AES_AEAD_Verify() (decryption) + * - [CCM] R_RSIP_AES_AEAD_LengthsSet() + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_INVALID_ARGUMENT Input key type is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_AEAD_Init (rsip_ctrl_t * const p_ctrl, + rsip_aes_aead_mode_t mode, + rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_nonce, + uint32_t const nonce_length) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ASSERT(p_nonce); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + + FSP_ERROR_RETURN(RSIP_PRV_ALG_AES == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type +#endif + + /* Check argument */ + fsp_err_t err = FSP_ERR_INVALID_ARGUMENT; + switch (mode) + { + /* AES-GCM */ + case RSIP_AES_AEAD_MODE_GCM_ENC: + case RSIP_AES_AEAD_MODE_GCM_DEC: + case RSIP_AES_AEAD_MODE_GCM_ENC_WRAPPED_IV: + case RSIP_AES_AEAD_MODE_GCM_DEC_WRAPPED_IV: + { + err = gcm_init(p_ctrl, mode, p_wrapped_key, p_nonce, nonce_length); + break; + } + + /* AES-CCM */ + case RSIP_AES_AEAD_MODE_CCM_ENC: + case RSIP_AES_AEAD_MODE_CCM_DEC: + { + err = ccm_init(p_ctrl, mode, p_wrapped_key, p_nonce, nonce_length); + break; + } + + default: + { + /* Invalid argument */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Sets text and tag lengths for CCM mode. + * + * Implements @ref rsip_api_t::aesAeadLengthsSet. + * + * @par Conditions + * @parblock + * Argument total_aad_length must be equal to the length of AAD and must be 110 or less. + * + * Argument total_test_length must be equal to the length of the plaintext or ciphertext. + * + * Argument tag_length must be 4, 6, 8, 10, 12, 14, or 16. + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and does not cause any state transitions. + * + * The next callable API functions in STATE_AES_AEAD are as below. + * - [CCM] R_RSIP_AES_AEAD_AADUpdate() + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_SIZE Input length is illegal. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @note In GCM mode, this API must NOT be called. If called, FSP_ERR_INVALID_STATE will be returned. + * AAD length and text length are indeterminate and output tag length is fixed to 16 bytes. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_AEAD_LengthsSet (rsip_ctrl_t * const p_ctrl, + uint32_t const total_aad_length, + uint32_t const total_text_length, + uint32_t const tag_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + case RSIP_STATE_AES_CCM_ENC_SET_LENGTH: + case RSIP_STATE_AES_CCM_DEC_SET_LENGTH: + { + err = ccm_length_set(p_ctrl, total_aad_length, total_text_length, tag_length); + break; + } + + default: + { + /* Invalid argument */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Inputs Additional Authentication Data (AAD). + * + * Implements @ref rsip_api_t::aesAeadAadUpdate. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and does not cause any state transitions. + * + * - [GCM] R_RSIP_AES_AEAD_AADUpdate(), R_RSIP_AES_AEAD_Update(), R_RSIP_AES_AEAD_Finish() (encryption), + * R_RSIP_AES_AEAD_Verify() (decryption) + * - [CCM] R_RSIP_AES_AEAD_AADUpdate() (AAD input is not completed), + * R_RSIP_AES_AEAD_Update() (AAD input is completed) + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE aad_length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_AEAD_AADUpdate (rsip_ctrl_t * const p_ctrl, uint8_t const * const p_aad, uint32_t const aad_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_aad || (0 == aad_length)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* AES-GCM (AAD update) */ + case RSIP_STATE_AES_GCM_ENC_UPDATE_AAD: + case RSIP_STATE_AES_GCM_DEC_UPDATE_AAD: + { + err = gcm_aad_update(p_ctrl, p_aad, aad_length); + break; + } + + /* AES-CCM (AAD update) */ + case RSIP_STATE_AES_CCM_ENC_UPDATE_AAD: + case RSIP_STATE_AES_CCM_DEC_UPDATE_AAD: + { + err = ccm_aad_update(p_ctrl, p_aad, aad_length); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Encrypts plaintext or decrypts ciphertext. + * + * Implements @ref rsip_api_t::aesAeadUpdate. + * + * @par Output length + * Output length to p_output (p_output_length) is calculated text that has not yet been output in multiple of 16 bytes. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and does not cause any state transitions. + * + * - [GCM] R_RSIP_AES_AEAD_Update(), R_RSIP_AES_AEAD_Finish() (encryption), R_RSIP_AES_AEAD_Verify() (decryption) + * - [CCM] R_RSIP_AES_AEAD_Update() (text input is not completed), + * R_RSIP_AES_AEAD_Finish() (text input is completed, encryption), + * R_RSIP_AES_AEAD_Verify() (text input is completed, decryption) + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_SIZE Input length is illegal. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @note In GCM mode, if this API is skipped, GMAC will be calculated. For detailed usage, refer to example code. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_AEAD_Update (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_input || (0 == input_length)); + FSP_ASSERT(p_output || (0 == input_length)); + FSP_ASSERT(p_output_length); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* AES-GCM (AAD update, text update) */ + case RSIP_STATE_AES_GCM_ENC_UPDATE_AAD: + case RSIP_STATE_AES_GCM_DEC_UPDATE_AAD: + case RSIP_STATE_AES_GCM_ENC_UPDATE_TEXT: + case RSIP_STATE_AES_GCM_DEC_UPDATE_TEXT: + { + err = gcm_update(p_ctrl, p_input, input_length, p_output, p_output_length); + break; + } + + /* AES-CCM (text update) */ + case RSIP_STATE_AES_CCM_ENC_UPDATE_TEXT: + case RSIP_STATE_AES_CCM_DEC_UPDATE_TEXT: + { + err = ccm_update(p_ctrl, p_input, input_length, p_output, p_output_length); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes an AES AEAD encryption. + * + * Implements @ref rsip_api_t::aesAeadFinish. + * + * @par Output length + * @parblock + * Output length to p_output (p_output_length) is the remaining calculated text length. + * + * Output length to p_tag as below. + * - [GCM] 16 bytes. + * - [CCM] Input value as tag_length in R_RSIP_AES_AEAD_LengthsSet(). + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_AEAD_Finish (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_output); + FSP_ASSERT(p_output_length); + FSP_ASSERT(p_tag); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* AES-GCM encryption (AAD update, text update) */ + case RSIP_STATE_AES_GCM_ENC_UPDATE_AAD: + case RSIP_STATE_AES_GCM_ENC_UPDATE_TEXT: + { + err = gcm_finish(p_ctrl, p_output, p_output_length, p_tag); + break; + } + + /* AES-CCM (finish) */ + case RSIP_STATE_AES_CCM_ENC_FINISH: + { + err = ccm_finish(p_ctrl, p_output, p_output_length, p_tag); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes an AES AEAD decryption. + * + * If there is 16-byte fractional data indicated by the total data length of the value of p_cipher that was input by + * R_RSIP_AES_GCM_DecryptUpdate(), this API will output the result of decrypting that fractional data to p_cipher. + * Here, the portion that does not reach 16 bytes will be padded with zeros. + * + * Implements @ref rsip_api_t::aesAeadVerify. + * + * @par Conditions + * Argument tag_length must be as below. + * - [GCM] 1 to 16 bytes. + * - [CCM] Input value as tag_length in R_RSIP_AES_AEAD_LengthsSet(). + * + * @par Output length + * Output length to p_output (p_output_length) is the remaining calculated text length. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_AEAD**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE tag_length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * @retval FSP_ERR_CRYPTO_RSIP_AUTHENTICATION Authentication is failed. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_AEAD_Verify (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_output); + FSP_ASSERT(p_output_length); + FSP_ASSERT(p_tag); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* AES-GCM decryption (AAD update, text update) */ + case RSIP_STATE_AES_GCM_DEC_UPDATE_AAD: + case RSIP_STATE_AES_GCM_DEC_UPDATE_TEXT: + { + err = gcm_verify(p_ctrl, p_output, p_output_length, p_tag, tag_length); + break; + } + + /* AES-CCM decryption (finish) */ + case RSIP_STATE_AES_CCM_DEC_VERI: + { + err = ccm_verify(p_ctrl, p_output, p_output_length, p_tag, tag_length); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Starts an AES MAC operation. + * + * Implements @ref rsip_api_t::aesMacInit. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_key must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_192 + * - @ref RSIP_KEY_TYPE_AES_256 + * + * Argument mode accepts any member of enumeration @ref rsip_aes_aead_mode_t. + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|--------------| + * |FSP_SUCCESS |STATE_AES_MAC | + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @note To calculate AES-GMAC, please use not R_RSIP_MAC_*() but R_RSIP_AEAD_*(). + * For detailed usage, refer to example code. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_MAC_Init (rsip_ctrl_t * const p_ctrl, + rsip_aes_mac_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key) +{ + FSP_PARAMETER_NOT_USED(mode); // Always select AES-CMAC + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + const rsip_func_subset_aes_cmac_t * p_func = &gp_func_aes_cmac[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_AES == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func->p_init, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Initialize handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* Set function to handle */ + p_handle->p_func = p_func; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_init((const uint32_t *) p_wrapped_key->p_value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_AES_CMAC; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Inputs message. + * + * Implements @ref rsip_api_t::aesMacUpdate. + * + * Inside this function, the data that is input by the user is buffered until the input value of p_message exceeds 16 bytes. + * If the input value, p_message, is not a multiple of 16 bytes, it will be padded within the function. + * + * @par State transition + * This API can only be executed in **STATE_AES_MAC**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_MAC_Update (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_message, + uint32_t const message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_message || (0 == message_length)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; + rsip_func_subset_aes_cmac_t * p_func = (rsip_func_subset_aes_cmac_t *) p_handle->p_func; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_AES_CMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t length_rest = 0; + + p_handle->total_length += message_length; + if ((p_handle->buffered_length + message_length) > RSIP_PRV_BYTE_SIZE_AES_BLOCK) + { + /* Input remaining data in buffer */ + memcpy((&p_handle->buffer[0] + p_handle->buffered_length), + p_message, + RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((const uint32_t *) (p_handle->buffer), + r_rsip_byte_to_word_convert(RSIP_PRV_BYTE_SIZE_AES_BLOCK)); + length_rest = message_length - + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + + /* Input block data */ + if (length_rest > RSIP_PRV_BYTE_SIZE_AES_BLOCK) + { + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((const uint32_t *) (p_message + + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - + p_handle->buffered_length)), + r_rsip_byte_to_word_convert(((length_rest - 1) / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * + RSIP_PRV_BYTE_SIZE_AES_BLOCK)); + length_rest -= (((length_rest - 1) / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * RSIP_PRV_BYTE_SIZE_AES_BLOCK); + } + + p_handle->buffered_length = 0; + + /* Store remaining data to buffer */ + memcpy(p_handle->buffer, p_message + (message_length - length_rest), length_rest); + p_handle->buffered_length = length_rest; + } + else + { + /* Store remaining data to buffer */ + memcpy(&p_handle->buffer[0] + p_handle->buffered_length, p_message, message_length); + p_handle->buffered_length += message_length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Outputs AES MAC. + * + * Implements @ref rsip_api_t::aesMacSignFinish. + * + * @par Output length + * Output length to p_mac is 16 bytes. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_MAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_MAC_SignFinish (rsip_ctrl_t * const p_ctrl, uint8_t * const p_mac) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_mac); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; + rsip_func_subset_aes_cmac_t * p_func = (rsip_func_subset_aes_cmac_t *) p_handle->p_func; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_AES_CMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* + * Check buffered data + * If the buffered data is not a complete block, fill the blank with 10/ (NIST SP 800-38B 6.2 Step4). + */ + if ((0 != (p_handle->buffered_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK)) || + (0 == p_handle->total_length)) + { + p_handle->buffer[p_handle->buffered_length] = 1 << 7; + memset(p_handle->buffer + (p_handle->buffered_length + 1), 0, + RSIP_PRV_BYTE_SIZE_AES_BLOCK - (p_handle->buffered_length + 1)); + } + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_generateFinal((const uint32_t *) p_handle->buffer, (uint32_t *) p_mac, p_handle->total_length); + + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies AES MAC. + * + * Implements @ref rsip_api_t::aesMacVerifyFinish. + * + * @par Conditions + * Argument mac_length must be as below. + * - [CMAC] 2 to 16 bytes. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_AES_MAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE mac_length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * @retval FSP_ERR_CRYPTO_RSIP_AUTHENTICATION Authentication is failed. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_AES_MAC_VerifyFinish (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_mac, + uint32_t const mac_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_mac); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_aes_cmac_handle_t * p_handle = &p_instance_ctrl->handle.aes_cmac; + rsip_func_subset_aes_cmac_t * p_func = (rsip_func_subset_aes_cmac_t *) p_handle->p_func; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_AES_CMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* mac_length must be 2 to 16 */ + FSP_ERROR_RETURN((2 <= mac_length) && (mac_length <= RSIP_PRV_BYTE_SIZE_AES_BLOCK), FSP_ERR_INVALID_SIZE); + + /* Set parameters */ + uint32_t mac_length_bit[1] = + { + bswap_32big(mac_length * 8) + }; + uint32_t mac_tmp[RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)] = + { + 0 + }; + memcpy(mac_tmp, p_mac, mac_length); + + /* + * Check buffered data + * If the buffered data is not a complete block, fill the blank with 10/ (NIST SP 800-38B 6.2 Step4). + */ + if ((0 != (p_handle->buffered_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK)) || + (0 == p_handle->total_length)) + { + p_handle->buffer[p_handle->buffered_length] = 1 << 7; + memset(p_handle->buffer + (p_handle->buffered_length + 1), 0, + RSIP_PRV_BYTE_SIZE_AES_BLOCK - (p_handle->buffered_length + 1)); + } + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_verifyFinal((const uint32_t *) p_handle->buffer, + (const uint32_t *) mac_tmp, + mac_length_bit, + p_handle->total_length); + + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_AUTH_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_AUTHENTICATION; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Prepares an AES-ECB/CBC/CTR. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t aes_init (rsip_ctrl_t * p_ctrl, + rsip_aes_cipher_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_initial_vector) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + const rsip_func_subset_aes_cipher_t * p_func = &gp_func_aes_cipher[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(p_func->p_init_ecb_enc, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Initialize handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* Set function */ + p_handle->p_func = p_func; + + /* Select init function */ + rsip_func_aes_cipher_init_t p_func_init; + switch (mode) + { + case RSIP_AES_CIPHER_MODE_ECB_ENC: + { + p_func_init = p_func->p_init_ecb_enc; + break; + } + + case RSIP_AES_CIPHER_MODE_ECB_DEC: + { + p_func_init = p_func->p_init_ecb_dec; + break; + } + + case RSIP_AES_CIPHER_MODE_CBC_ENC: + { + p_func_init = p_func->p_init_cbc_enc; + break; + } + + case RSIP_AES_CIPHER_MODE_CBC_DEC: + { + p_func_init = p_func->p_init_cbc_dec; + break; + } + + case RSIP_AES_CIPHER_MODE_CBC_ENC_WRAPPED_IV: + { + p_func_init = p_func->p_init_cbc_enc_wrapped_iv; + break; + } + + case RSIP_AES_CIPHER_MODE_CBC_DEC_WRAPPED_IV: + { + p_func_init = p_func->p_init_cbc_dec_wrapped_iv; + break; + } + + default: // RSIP_AES_CIPHER_MODE_CTR + { + p_func_init = p_func->p_init_ctr; + } + } + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func_init((const uint32_t *) p_wrapped_key->p_value, (const uint32_t *) p_initial_vector); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_AES_CIPHER; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Executes AES-ECB/CBC/CTR encryption and decryption. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE Input length is illegal. + **********************************************************************************************************************/ +static fsp_err_t aes_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint8_t * p_output, uint32_t input_length) + +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; + rsip_func_subset_aes_cipher_t * p_func = (rsip_func_subset_aes_cipher_t *) p_handle->p_func; + + /* input_length must be a multiple of AES block length */ + FSP_ERROR_RETURN(0 == (input_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK), FSP_ERR_INVALID_SIZE); + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_AES_CIPHER == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + if (0 != input_length) + { + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((const uint32_t *) p_input, (uint32_t *) p_output, r_rsip_byte_to_word_convert(input_length)); + } + else + { + /* Do nothing */ + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Finalizes an AES-ECB/CBC/CTR. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t aes_finish (rsip_ctrl_t * p_ctrl) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; + rsip_func_subset_aes_cipher_t * p_func = (rsip_func_subset_aes_cipher_t *) p_handle->p_func; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_AES_CIPHER == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_final(); + + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Prepares an AES-XTS. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input AES-XTS key value is illegal.(Data Key == Tweak Key) + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t xts_init (rsip_ctrl_t * p_ctrl, + rsip_aes_cipher_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_initial_vector) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + const rsip_func_subset_aes_xts_t * p_func = (RSIP_AES_CIPHER_MODE_XTS_ENC == mode) ? + &gp_func_aes_xts_enc[key_type_ext.subtype] : + &gp_func_aes_xts_dec[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(p_func->p_init, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Initialize handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* Set function */ + p_handle->p_func = p_func; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_init((const uint32_t *) p_wrapped_key->p_value, (const uint32_t *) p_initial_vector); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_AES_XTS_UPDATE; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Executes AES-XTS encryption and decryption. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE Input length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t xts_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_input, uint8_t * p_output, uint32_t input_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; + rsip_func_subset_aes_xts_t * p_func = (rsip_func_subset_aes_xts_t *) p_handle->p_func; + + /* Input_length must be 0 or >= 16 */ + FSP_ERROR_RETURN((0 == input_length) || (RSIP_PRV_BYTE_SIZE_AES_BLOCK <= input_length), FSP_ERR_INVALID_SIZE); + + /* Set length */ + uint32_t remaining_length = (0 == (input_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK)) ? 0 : + input_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK + RSIP_PRV_BYTE_SIZE_AES_BLOCK; + uint32_t block_length = input_length - remaining_length; + + fsp_err_t err = FSP_SUCCESS; + if (0 != input_length) + { + if (0 != block_length) + { + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((const uint32_t *) p_input, + (uint32_t *) p_output, + r_rsip_byte_to_word_convert(block_length)); + } + + /* Input remaining blocks */ + if (0 != (input_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK)) + { + uint8_t buffer[RSIP_PRV_BYTE_SIZE_AES_BLOCK * 2] = {0}; + memcpy(buffer, p_input + block_length, remaining_length); + + err = xts_finish_primitive(p_func, buffer, p_output + block_length, remaining_length); + + /* After input remaining blocks, final function must be called */ + p_instance_ctrl->state = RSIP_STATE_AES_XTS_FINISH; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes an AES-XTS. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t xts_finish (rsip_ctrl_t * p_ctrl) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_cipher_handle_t * p_handle = &p_instance_ctrl->handle.aes_cipher; + rsip_func_subset_aes_xts_t * p_func = (rsip_func_subset_aes_xts_t *) p_handle->p_func; + + fsp_err_t err = FSP_SUCCESS; + if (RSIP_STATE_AES_XTS_UPDATE == p_instance_ctrl->state) + { + /* If final function have not called (remaining blocks have not been input), Call function for empty message */ + err = xts_finish_primitive(p_func, NULL, NULL, 0); + } + + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes an AES-XTS. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t xts_finish_primitive (rsip_func_subset_aes_xts_t * p_func, + const uint8_t * p_input, + uint8_t * p_output, + uint32_t input_length) +{ + uint32_t output_length_bit[1] = + { + bswap_32big(r_rsip_byte_to_bit_convert_lower(input_length)) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_final(output_length_bit, (uint32_t *) p_input, (uint32_t *) (p_output)); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* After this function returns, final function must be called */ + err = FSP_SUCCESS; + + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Prepares an AES-GCM. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t gcm_init (rsip_ctrl_t * p_ctrl, + rsip_aes_aead_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_nonce, + uint32_t nonce_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_gcm_handle_t * p_handle = &p_instance_ctrl->handle.aes_gcm; + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + const rsip_func_subset_aes_gcm_t * p_func = + ((RSIP_AES_AEAD_MODE_GCM_ENC == mode) || (RSIP_AES_AEAD_MODE_GCM_ENC_WRAPPED_IV == mode)) ? + &gp_func_aes_gcm_enc[key_type_ext.subtype] : &gp_func_aes_gcm_dec[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(p_func->p_init, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Initialize handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* Set function */ + p_handle->p_func = p_func; + + /* Call function (cast to match the argument type with the primitive function) */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + rsip_ret_t rsip_ret = RSIP_RET_UNKNOWN; + switch (mode) + { + /* Plain IV */ + case RSIP_AES_AEAD_MODE_GCM_ENC: + case RSIP_AES_AEAD_MODE_GCM_DEC: + { + /* Generate IV */ + uint32_t hashed_ivec[4] = + { + 0 + }; + + err = gcm_iv_prepare(&gp_func_aes_cipher[key_type_ext.subtype], + p_nonce, + nonce_length, + p_wrapped_key, + hashed_ivec); + + if (FSP_SUCCESS == err) + { + rsip_ret = p_func->p_init((const uint32_t *) p_wrapped_key->p_value, hashed_ivec); + } + + break; + } + + /* Wrapped IV */ + case RSIP_AES_AEAD_MODE_GCM_ENC_WRAPPED_IV: + case RSIP_AES_AEAD_MODE_GCM_DEC_WRAPPED_IV: + { + err = FSP_SUCCESS; + rsip_ret = p_func->p_init_wrapped_iv((const uint32_t *) p_wrapped_key->p_value, (const uint32_t *) p_nonce); + + break; + } + + default: + { + /* Invalid mode */ + } + } + + if (FSP_SUCCESS == err) + { + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* + * State transition + * RSIP_AES_AEAD_MODE_GCM_ENC -> RSIP_STATE_AES_GCM_ENC_UPDATE_AAD + * RSIP_AES_AEAD_MODE_GCM_DEC -> RSIP_STATE_AES_GCM_DEC_UPDATE_AAD + */ + p_instance_ctrl->state = + ((RSIP_AES_AEAD_MODE_GCM_ENC == mode) || (RSIP_AES_AEAD_MODE_GCM_ENC_WRAPPED_IV == mode)) ? + RSIP_STATE_AES_GCM_ENC_UPDATE_AAD : RSIP_STATE_AES_GCM_DEC_UPDATE_AAD; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + } + else + { + /* Do nothing */ + } + + return err; +} + +/*******************************************************************************************************************//** + * Inputs aad and executes encryption and decryption. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +static fsp_err_t gcm_aad_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, uint32_t aad_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_gcm_handle_t * p_handle = &p_instance_ctrl->handle.aes_gcm; + rsip_func_subset_aes_gcm_t * p_func = (rsip_func_subset_aes_gcm_t *) p_handle->p_func; + + uint32_t length_rest = 0; + + /* Input AAD */ + if (0 != aad_length) + { + p_handle->total_aad_length += aad_length; + + if ((p_handle->buffered_length + aad_length) >= RSIP_PRV_BYTE_SIZE_AES_BLOCK) + { + /* Input remaining data in buffer */ + memcpy((&p_handle->buffer[0] + p_handle->buffered_length), + p_aad, + RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_updateAad((uint32_t *) (p_handle->buffer), + r_rsip_byte_to_word_convert((RSIP_PRV_BYTE_SIZE_AES_BLOCK))); + length_rest = aad_length - + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + + /* Input block data */ + if (length_rest >= RSIP_PRV_BYTE_SIZE_AES_BLOCK) + { + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_updateAad((const uint32_t *) (p_aad + + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - + p_handle->buffered_length)), + r_rsip_byte_to_word_convert((length_rest / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * + RSIP_PRV_BYTE_SIZE_AES_BLOCK)); + length_rest -= ((length_rest / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * RSIP_PRV_BYTE_SIZE_AES_BLOCK); + } + + p_handle->buffered_length = 0; + + /* Store remaining data to buffer */ + memcpy(p_handle->buffer, p_aad + (aad_length - length_rest), length_rest); + p_handle->buffered_length = length_rest; + } + else + { + /* Store remaining data to buffer */ + memcpy(&p_handle->buffer[0] + p_handle->buffered_length, p_aad, aad_length); + p_handle->buffered_length += aad_length; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Inputs aad and executes encryption and decryption. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +static fsp_err_t gcm_update (rsip_ctrl_t * p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_gcm_handle_t * p_handle = &p_instance_ctrl->handle.aes_gcm; + rsip_func_subset_aes_gcm_t * p_func = (rsip_func_subset_aes_gcm_t *) p_handle->p_func; + + uint32_t length_rest = 0; + *p_output_length = 0; + + /* If plaintext/ciphertext is input for the first time, input remaining AAD and prohibit new AAD input */ + switch (p_instance_ctrl->state) + { + case RSIP_STATE_AES_GCM_ENC_UPDATE_AAD: + case RSIP_STATE_AES_GCM_DEC_UPDATE_AAD: + { + gcm_aad_input_terminate(p_instance_ctrl); + break; + } + + default: + { + /* Do nothing */ + } + } + + /* Input plaintext/ciphertext */ + if (0 != input_length) + { + p_handle->total_length += input_length; + if ((p_handle->buffered_length + input_length) >= RSIP_PRV_BYTE_SIZE_AES_BLOCK) + { + /* Input remaining data in buffer */ + memcpy((&p_handle->buffer[0] + p_handle->buffered_length), + p_input, + RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((uint32_t *) (p_handle->buffer), (uint32_t *) (p_output), + r_rsip_byte_to_word_convert(RSIP_PRV_BYTE_SIZE_AES_BLOCK)); + length_rest = input_length - + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + *p_output_length += RSIP_PRV_BYTE_SIZE_AES_BLOCK; + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + + /* Input block data */ + if (length_rest >= RSIP_PRV_BYTE_SIZE_AES_BLOCK) + { + uint32_t block_data_length = (length_rest / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * + RSIP_PRV_BYTE_SIZE_AES_BLOCK; + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((const uint32_t *) (p_input + + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - + p_handle->buffered_length)), + (uint32_t *) (p_output + RSIP_PRV_BYTE_SIZE_AES_BLOCK), + r_rsip_byte_to_word_convert(block_data_length)); + length_rest -= block_data_length; + *p_output_length += block_data_length; + } + + p_handle->buffered_length = 0; + + /* Store remaining data to buffer */ + memcpy(p_handle->buffer, p_input + (input_length - length_rest), length_rest); + p_handle->buffered_length = length_rest; + } + else + { + /* Store remaining data to buffer */ + memcpy(&p_handle->buffer[0] + p_handle->buffered_length, p_input, input_length); + p_handle->buffered_length += input_length; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Finalizes an AES-GCM encryption. + * + * If there is 16-byte fractional data indicated by the total data length of the value of p_plain that was input by + * R_RSIP_AES_GCM_EncryptUpdate(), this API will output the result of encrypting that fractional data to p_cipher. + * Here, the portion that does not reach 16 bytes will be padded with zeros. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of ciphertext. The fractional block is output. + * @param[out] p_output_length Pointer to destination of ciphertext length. + * @param[out] p_tag Pointer to destination of tag for authentication. The length is 16 bytes. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t gcm_finish (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_gcm_handle_t * p_handle = &p_instance_ctrl->handle.aes_gcm; + rsip_func_subset_aes_gcm_t * p_func = (rsip_func_subset_aes_gcm_t *) p_handle->p_func; + + uint32_t aad_bit_size[2] = + { + 0 + }; + uint32_t data_bit_size[2] = + { + 0 + }; + + /* If unprocessed AAD still exists in buffer, input it */ + if (RSIP_STATE_AES_GCM_ENC_UPDATE_AAD == p_instance_ctrl->state) + { + gcm_aad_input_terminate(p_instance_ctrl); + } + + /* Set remaining data */ + if ((0 != (p_handle->total_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK)) || + (0 == p_handle->total_length)) + { + memset(p_handle->buffer + p_handle->buffered_length, 0, + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length)); + } + + /* Set parameters */ + aad_bit_size[0] = bswap_32big(r_rsip_byte_to_bit_convert_upper(p_handle->total_aad_length)); + aad_bit_size[1] = bswap_32big(r_rsip_byte_to_bit_convert_lower(p_handle->total_aad_length)); + data_bit_size[0] = bswap_32big((r_rsip_byte_to_bit_convert_upper(p_handle->total_length))); + data_bit_size[1] = bswap_32big(r_rsip_byte_to_bit_convert_lower(p_handle->total_length)); + *p_output_length = p_handle->buffered_length; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_encryptFinal((uint32_t *) (p_handle->buffer), aad_bit_size, data_bit_size, (uint32_t *) p_output, + (uint32_t *) p_tag); + + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes an AES-GCM decryption. + * + * If there is 16-byte fractional data indicated by the total data length of the value of p_cipher that was input by + * R_RSIP_AES_GCM_DecryptUpdate(), this API will output the result of decrypting that fractional data to p_cipher. + * Here, the portion that does not reach 16 bytes will be padded with zeros. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of plaintext. The fractional block is output. + * @param[out] p_output_length Pointer to destination of plaintext length. + * @param[in] p_tag Pointer to tag for authentication. The length depends on tag_length. + * @param[in] tag_length Byte length of tag. Must be 1 to 16. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE tag_length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * @retval FSP_ERR_CRYPTO_RSIP_AUTHENTICATION Authentication is failed. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t gcm_verify (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_gcm_handle_t * p_handle = &p_instance_ctrl->handle.aes_gcm; + rsip_func_subset_aes_gcm_t * p_func = (rsip_func_subset_aes_gcm_t *) p_handle->p_func; + + /* tag_length must be from 1 to 16 */ + FSP_ERROR_RETURN((0 < tag_length) && (tag_length <= 16), FSP_ERR_INVALID_SIZE); + + uint32_t aad_bit_size[2] = + { + 0 + }; + uint32_t data_bit_size[2] = + { + 0 + }; + uint32_t tag_length_tmp[1] = + { + 0 + }; + uint32_t tag_tmp[RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)] = + { + 0 + }; + + /* If unprocessed AAD still exists in buffer, input it */ + if (RSIP_STATE_AES_GCM_DEC_UPDATE_AAD == p_instance_ctrl->state) + { + gcm_aad_input_terminate(p_instance_ctrl); + } + + /* Set remaining data */ + if ((0 != (p_handle->total_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK)) || + (0 == p_handle->total_length)) + { + memset(p_handle->buffer + p_handle->buffered_length, 0, + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length)); + } + + /* Copy tag */ + memcpy(tag_tmp, p_tag, tag_length); + + /* Set parameters */ + aad_bit_size[0] = bswap_32big(r_rsip_byte_to_bit_convert_upper(p_handle->total_aad_length)); + aad_bit_size[1] = bswap_32big(r_rsip_byte_to_bit_convert_lower(p_handle->total_aad_length)); + data_bit_size[0] = bswap_32big(r_rsip_byte_to_bit_convert_upper(p_handle->total_length)); + data_bit_size[1] = bswap_32big(r_rsip_byte_to_bit_convert_lower(p_handle->total_length)); + tag_length_tmp[0] = bswap_32big(tag_length); + *p_output_length = p_handle->buffered_length; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func->p_decryptFinal((uint32_t *) (p_handle->buffer), + (uint32_t *) tag_tmp, + aad_bit_size, + data_bit_size, + (uint32_t *) tag_length_tmp, + (uint32_t *) p_output); + + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_AUTH_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_AUTHENTICATION; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Generates of input parameter for AES-GCM functions. + * + * @param[in] p_func_aes_cipher Pointer to function subset of AES cipher (AES-ECB) + * @param[in] p_initial_vector Pointer to initialization vector. + * @param[in] initial_vector_length Initial vector byte size. + * @param[in] p_wrapped_key Wrapped key area. + * @param[out] p_hashed_ivec Pointer to destination of initialization vector + * (using length of initial_vector_length as a condition) + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + *********************************************************************************************************************/ +static fsp_err_t gcm_iv_prepare (const rsip_func_subset_aes_cipher_t * p_func_aes_cipher, + const uint8_t * p_initial_vector, + uint32_t initial_vector_length, + const rsip_wrapped_key_t * p_wrapped_key, + uint32_t * p_hashed_ivec) +{ + uint32_t hash_subkey[4] = + { + 0 + }; + uint32_t hashed_ivec_tmp[4] = + { + 0 + }; + uint32_t zero[4] = + { + 0 + }; + uint32_t ivec_length_rest = 0; + uint32_t ivec_bit_len[4] = + { + 0 + }; + uint32_t ivec_tmp[4] = + { + 0 + }; + + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + + /* If initial_vector_length is 12 (96 bit), hashed_ivec is (initial_vector || 0^{31} || 1) */ + if (12U == initial_vector_length) + { + memcpy(p_hashed_ivec, p_initial_vector, 12U); + p_hashed_ivec[3] = bswap_32big(0x00000001U); + err = FSP_SUCCESS; + } + /* If iv_len is not 12 (96 bit), calculate GHASH */ + else + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = p_func_aes_cipher->p_init_ecb_enc((const uint32_t *) p_wrapped_key->p_value, zero); + if (RSIP_RET_PASS == rsip_ret) + { + p_func_aes_cipher->p_update(zero, hash_subkey, RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); + rsip_ret = p_func_aes_cipher->p_final(); + } + + if (RSIP_RET_PASS == rsip_ret) + { + if (RSIP_PRV_BYTE_SIZE_AES_BLOCK <= initial_vector_length) + { + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = + gp_func_ghash_compute(hash_subkey, zero, (const uint32_t *) p_initial_vector, hashed_ivec_tmp, + (initial_vector_length / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * sizeof(uint32_t)); + if (RSIP_RET_PASS == rsip_ret) + { + ivec_length_rest = initial_vector_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK; + if (0 != ivec_length_rest) + { + memcpy(ivec_tmp, p_initial_vector + (initial_vector_length - ivec_length_rest), + ivec_length_rest); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_ghash_compute(hash_subkey, + hashed_ivec_tmp, + ivec_tmp, + hashed_ivec_tmp, + RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); + } + } + } + else + { + memcpy(ivec_tmp, p_initial_vector, initial_vector_length); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_ghash_compute(hash_subkey, + zero, + ivec_tmp, + hashed_ivec_tmp, + RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); + } + + if (RSIP_RET_PASS == rsip_ret) + { + /* Calculate ivec bit length */ + ivec_bit_len[0] = 0U; + ivec_bit_len[1] = 0U; + ivec_bit_len[2] = bswap_32big(r_rsip_byte_to_bit_convert_upper(initial_vector_length)); + ivec_bit_len[3] = bswap_32big(r_rsip_byte_to_bit_convert_lower(initial_vector_length)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret = gp_func_ghash_compute(hash_subkey, + hashed_ivec_tmp, + ivec_bit_len, + p_hashed_ivec, + RSIP_PRV_BYTE_SIZE_AES_BLOCK / sizeof(uint32_t)); + } + } + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + } + + return err; +} + +static void gcm_aad_input_terminate (rsip_instance_ctrl_t * p_instance_ctrl) +{ + rsip_aes_gcm_handle_t * p_handle = &p_instance_ctrl->handle.aes_gcm; + rsip_func_subset_aes_gcm_t * p_func = (rsip_func_subset_aes_gcm_t *) p_handle->p_func; + + if (0 != (p_handle->buffered_length % RSIP_PRV_BYTE_SIZE_AES_BLOCK)) + { + /* Input remaining AAD */ + memset(&p_handle->buffer[0] + p_handle->buffered_length, + 0, + RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_updateAad((uint32_t *) (p_handle-> + buffer), + r_rsip_byte_to_word_convert(RSIP_PRV_BYTE_SIZE_AES_BLOCK)); + } + + /* Reset buffer */ + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + p_handle->buffered_length = 0; + + /* Prohibit AAD input and start plaintext/ciphertext input */ + p_func->p_updateTransition(); + + /* + * State transition + * RSIP_STATE_AES_GCM_ENC_UPDATE_AAD -> RSIP_STATE_AES_GCM_ENC_UPDATE_TEXT + * RSIP_STATE_AES_GCM_DEC_UPDATE_AAD -> RSIP_STATE_AES_GCM_DEC_UPDATE_TEXT + */ + p_instance_ctrl->state = (p_instance_ctrl->state == RSIP_STATE_AES_GCM_ENC_UPDATE_AAD) ? + RSIP_STATE_AES_GCM_ENC_UPDATE_TEXT : RSIP_STATE_AES_GCM_DEC_UPDATE_TEXT; +} + +/*******************************************************************************************************************//** + * Prepares an AES-CCM. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + **********************************************************************************************************************/ +static fsp_err_t ccm_init (rsip_ctrl_t * p_ctrl, + rsip_aes_aead_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_nonce, + uint32_t nonce_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_ccm_handle_t * p_handle = &p_instance_ctrl->handle.aes_ccm; + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + const rsip_func_subset_aes_ccm_t * p_func = + (RSIP_AES_AEAD_MODE_CCM_ENC == mode) ? + &gp_func_aes_ccm_enc[key_type_ext.subtype] : &gp_func_aes_ccm_dec[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + + /* Check if the key type is enabled on configuration */ + FSP_ERROR_RETURN((p_func->p_encryptInit || p_func->p_decryptInit), FSP_ERR_NOT_ENABLED); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Check length */ + FSP_ERROR_RETURN((7 <= nonce_length) && (nonce_length <= 13), FSP_ERR_INVALID_SIZE); + + /* Initialize handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* Set function */ + p_handle->p_func = p_func; + + /* Copy wrapped key */ + p_handle->wrapped_key.type = p_wrapped_key->type; + p_handle->wrapped_key.p_value = p_handle->wrapped_key_value; + memcpy(p_handle->wrapped_key_value, p_wrapped_key->p_value, RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type)); + + /* Copy nonce */ + memcpy(p_handle->nonce_buffer, p_nonce, nonce_length); + p_handle->nonce_length = nonce_length; + + /* + * State transition + * RSIP_AES_AEAD_MODE_CCM_ENC -> RSIP_STATE_AES_CCM_ENC_SET_LENGTH + * RSIP_AES_AEAD_MODE_CCM_DEC -> RSIP_STATE_AES_CCM_DEC_SET_LENGTH + */ + p_instance_ctrl->state = (RSIP_AES_AEAD_MODE_CCM_ENC == mode) ? + RSIP_STATE_AES_CCM_ENC_SET_LENGTH : RSIP_STATE_AES_CCM_DEC_SET_LENGTH; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set lengths of AES-CCM. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. + **********************************************************************************************************************/ +static fsp_err_t ccm_length_set (rsip_ctrl_t * const p_ctrl, + uint32_t const total_aad_length, + uint32_t const total_text_length, + uint32_t const tag_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_ccm_handle_t * p_handle = &p_instance_ctrl->handle.aes_ccm; + + /* Check length */ + FSP_ERROR_RETURN(total_aad_length <= RSIP_PRV_BYTE_SIZE_CCM_AAD_MAX, FSP_ERR_INVALID_SIZE); + FSP_ERROR_RETURN((tag_length % 2 == 0) && + (4 <= tag_length) && + (tag_length <= 16), + FSP_ERR_INVALID_SIZE); // 4, 6, 8, 10, 12, 14, or 16 + + /* Set lengths */ + p_handle->total_aad_length = total_aad_length; + p_handle->total_length = total_text_length; + p_handle->tag_length = tag_length; + + /* + * State transition + * RSIP_STATE_AES_CCM_ENC_SET_LENGTH -> RSIP_STATE_AES_CCM_ENC_UPDATE_AAD + * RSIP_STATE_AES_CCM_DEC_SET_LENGTH -> RSIP_STATE_AES_CCM_DEC_UPDATE_AAD + */ + p_instance_ctrl->state = (p_instance_ctrl->state == RSIP_STATE_AES_CCM_ENC_SET_LENGTH) ? + RSIP_STATE_AES_CCM_ENC_UPDATE_AAD : RSIP_STATE_AES_CCM_DEC_UPDATE_AAD; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Inputs aad and executes encryption and decryption. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE aad_length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t ccm_aad_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, uint32_t aad_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_ccm_handle_t * p_handle = &p_instance_ctrl->handle.aes_ccm; + rsip_func_subset_aes_ccm_t * p_func = (rsip_func_subset_aes_ccm_t *) p_handle->p_func; + rsip_wrapped_key_t * p_wrapped_key = &p_handle->wrapped_key; + + /* Check length */ + FSP_ERROR_RETURN((p_handle->input_aad_length + aad_length) <= p_handle->total_aad_length, FSP_ERR_INVALID_SIZE); + + /* Copy AAD to buffer */ + memcpy(p_handle->buffer + p_handle->input_aad_length, p_aad, aad_length); + p_handle->input_aad_length += aad_length; + + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + if (p_handle->input_aad_length == p_handle->total_aad_length) + { + /* format B and generate counter */ + uint8_t counter[RSIP_PRV_BYTE_SIZE_AES_BLOCK]; + uint8_t formatted_data[RSIP_PRV_BYTE_AES_CCM_B]; + uint32_t formatted_length = 0; + memset(counter, 0, sizeof(counter)); + memset(formatted_data, 0, sizeof(formatted_data)); + ccm_format(p_handle->nonce_buffer, + p_handle->nonce_length, + p_handle->buffer, // AAD + (uint8_t) p_handle->total_aad_length, + p_handle->total_length, // payload length + p_handle->tag_length, + counter, + formatted_data, + &formatted_length); + + /* Clear buffer for ccm_update */ + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = RSIP_RET_UNKNOWN; + uint32_t length_tmp = bswap_32big(p_handle->total_length); + uint32_t tag_length_tmp = bswap_32big(p_handle->tag_length); + if (RSIP_STATE_AES_CCM_ENC_UPDATE_AAD == p_instance_ctrl->state) + { + rsip_ret = + p_func->p_encryptInit((const uint32_t *) p_wrapped_key->p_value, + &length_tmp, + (const uint32_t *) counter, + (const uint32_t *) formatted_data, + formatted_length); + } + else // RSIP_STATE_AES_CCM_DEC_UPDATE_AAD == p_instance_ctrl->state + { + rsip_ret = + p_func->p_decryptInit((const uint32_t *) p_wrapped_key->p_value, &length_tmp, &tag_length_tmp, + (const uint32_t *) counter, (const uint32_t *) formatted_data, formatted_length); + } + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* + * State transition + * RSIP_AES_AEAD_MODE_CCM_ENC -> RSIP_STATE_AES_CCM_ENC_UPDATE_AAD + * RSIP_AES_AEAD_MODE_CCM_DEC -> RSIP_STATE_AES_CCM_DEC_UPDATE_AAD + */ + p_instance_ctrl->state = (RSIP_STATE_AES_CCM_ENC_UPDATE_AAD == p_instance_ctrl->state) ? + RSIP_STATE_AES_CCM_ENC_UPDATE_TEXT : RSIP_STATE_AES_CCM_DEC_UPDATE_TEXT; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + } + else + { + err = FSP_SUCCESS; + } + + return err; +} + +/*******************************************************************************************************************//** + * Inputs aad and executes encryption and decryption. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE input_length is illegal. + **********************************************************************************************************************/ +static fsp_err_t ccm_update (rsip_ctrl_t * p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_ccm_handle_t * p_handle = &p_instance_ctrl->handle.aes_ccm; + rsip_func_subset_aes_ccm_t * p_func = (rsip_func_subset_aes_ccm_t *) p_handle->p_func; + + /* Check length */ + FSP_ERROR_RETURN((p_handle->input_length + input_length) <= p_handle->total_length, FSP_ERR_INVALID_SIZE); + + uint32_t length_rest = 0; + *p_output_length = 0; + + p_handle->input_length += input_length; + + /* Input plaintext/ciphertext */ + if ((p_handle->buffered_length + input_length) >= RSIP_PRV_BYTE_SIZE_AES_BLOCK) + { + /* Input remaining data in buffer */ + memcpy(p_handle->buffer + p_handle->buffered_length, + p_input, + RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((uint32_t *) p_handle->buffer, (uint32_t *) p_output, + r_rsip_byte_to_word_convert(RSIP_PRV_BYTE_SIZE_AES_BLOCK)); + length_rest = input_length - + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - p_handle->buffered_length); + *p_output_length += RSIP_PRV_BYTE_SIZE_AES_BLOCK; + + /* Input block data */ + if (length_rest >= RSIP_PRV_BYTE_SIZE_AES_BLOCK) + { + uint32_t block_data_length = (length_rest / RSIP_PRV_BYTE_SIZE_AES_BLOCK) * + RSIP_PRV_BYTE_SIZE_AES_BLOCK; + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((uint32_t *) (p_input + + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - + p_handle->buffered_length)), + (uint32_t *) (p_output + RSIP_PRV_BYTE_SIZE_AES_BLOCK), + r_rsip_byte_to_word_convert(block_data_length)); + length_rest -= block_data_length; + *p_output_length += block_data_length; + } + + p_handle->buffered_length = 0; + + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + + /* Store remaining data to buffer */ + memcpy(p_handle->buffer, p_input + (input_length - length_rest), length_rest); + p_handle->buffered_length = length_rest; + } + else + { + /* Store remaining data to buffer */ + memcpy(p_handle->buffer + p_handle->buffered_length, p_input, input_length); + p_handle->buffered_length += input_length; + } + + if (p_handle->total_length == p_handle->input_length) + { + /* + * State transition + * RSIP_STATE_AES_CCM_ENC_UPDATE_TEXT -> RSIP_STATE_AES_CCM_ENC_FINISH + * RSIP_STATE_AES_CCM_DEC_UPDATE_TEXT -> RSIP_STATE_AES_CCM_DEC_VERI + */ + p_instance_ctrl->state = (p_instance_ctrl->state == RSIP_STATE_AES_CCM_ENC_UPDATE_TEXT) ? + RSIP_STATE_AES_CCM_ENC_FINISH : RSIP_STATE_AES_CCM_DEC_VERI; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Finalizes an AES-CCM encryption. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of ciphertext. The fractional block is output. + * @param[out] p_output_length Pointer to destination of ciphertext length. + * @param[out] p_tag Pointer to destination of tag for authentication. The length is 16 bytes. + * + * @retval FSP_SUCCESS Normal termination. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t ccm_finish (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_ccm_handle_t * p_handle = &p_instance_ctrl->handle.aes_ccm; + rsip_func_subset_aes_ccm_t * p_func = (rsip_func_subset_aes_ccm_t *) p_handle->p_func; + + uint32_t length_tmp = bswap_32big(p_handle->total_length); + uint8_t tag_tmp[RSIP_PRV_BYTE_SIZE_AES_BLOCK] = + { + 0 + }; + uint32_t output_tmp[RSIP_PRV_BYTE_SIZE_AES_BLOCK] = + { + 0 + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_encryptFinal((uint32_t *) p_handle->buffer, &length_tmp, (uint32_t *) output_tmp, + (uint32_t *) tag_tmp); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + memcpy(p_output, output_tmp, p_handle->buffered_length); + *p_output_length = p_handle->buffered_length; + memcpy(p_tag, tag_tmp, p_handle->tag_length); + + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes an AES-CCM decryption. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of plaintext. The fractional block is output. + * @param[out] p_output_length Pointer to destination of plaintext length. + * @param[in] p_tag Pointer to tag for authentication. The length depends on tag_length. + * @param[in] tag_length Byte length of tag. Must be 1 to 16. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE tag_length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Internal error. + * @retval FSP_ERR_CRYPTO_RSIP_AUTHENTICATION Authentication is failed. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t ccm_verify (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_aes_ccm_handle_t * p_handle = &p_instance_ctrl->handle.aes_ccm; + rsip_func_subset_aes_ccm_t * p_func = (rsip_func_subset_aes_ccm_t *) p_handle->p_func; + + /* Check length */ + FSP_ERROR_RETURN(p_handle->tag_length == tag_length, FSP_ERR_INVALID_SIZE); + + uint32_t length_tmp = bswap_32big(p_handle->total_length); + uint32_t tag_length_tmp = bswap_32big(tag_length); + uint8_t tag_tmp[RSIP_PRV_BYTE_SIZE_AES_BLOCK] = + { + 0 + }; + uint32_t output_tmp[RSIP_PRV_BYTE_SIZE_AES_BLOCK] = + { + 0 + }; + + /* Copy tag */ + memcpy(tag_tmp, p_tag, tag_length); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func->p_decryptFinal((uint32_t *) p_handle->buffer, &length_tmp, (uint32_t *) tag_tmp, &tag_length_tmp, + (uint32_t *) output_tmp); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + memcpy(p_output, output_tmp, p_handle->buffered_length); + *p_output_length = p_handle->buffered_length; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_AUTH_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_AUTHENTICATION; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + /* Reset handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return err; +} + +/*******************************************************************************************************************//** + * Format B and generate counter (SP 800-38C 5.4) + * + * @param[in] nonce Nonce. + * @param[in] nonce_len Nonce data length (byte). + * @param[in] adata Associated data. + * @param[in] a_len Associated data length (byte). + * @param[in] payload_len Payload length (byte). + * @param[in] mac_len MAC data length (byte). + * @param[out] counter Counter blocks area. + * @param[out] formatted_data Formatted data area. + * @param[out] formatted_length Formatted data length. + *********************************************************************************************************************/ +static void ccm_format (const uint8_t * nonce, + uint32_t nonce_len, + const uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len, + uint8_t * counter, + uint8_t * formatted_data, + uint32_t * formatted_length) +{ + uint8_t flag = 0; + uint8_t mac_len_tmp = 0; + uint8_t q_len = 0; + uint32_t formatted_length_tmp = 0; + + /* Out of range check */ + if (((7 > nonce_len) || (13 < nonce_len)) || + (((4 > mac_len) || (16 < mac_len)) || ((0 != (mac_len % 2)) || (RSIP_PRV_BYTE_SIZE_CCM_AAD_MAX < a_len)))) + { + return; + } + + /* formatting flag section in formatted data B */ + if (0 < a_len) + { + flag = 1 << 6; + } + + mac_len_tmp = (uint8_t) ((mac_len - 2) / 2); + mac_len_tmp = (uint8_t) (mac_len_tmp << 3); + flag |= mac_len_tmp; + q_len = (uint8_t) (15 - nonce_len); + flag |= (uint8_t) (q_len - 1); + formatted_data[formatted_length_tmp] = flag; + formatted_length_tmp++; + + /* adding nonce to formatted data B */ + memcpy(formatted_data + formatted_length_tmp, nonce, nonce_len); + formatted_length_tmp += 11; + if (12 <= nonce_len) + { + formatted_length_tmp++; + } + + if (13 <= nonce_len) + { + formatted_length_tmp++; + } + + /* adding Q to formatted data B */ + do + { + /* Casting uint32_t data to uint8_t data array. */ + formatted_data[formatted_length_tmp] = (uint8_t) (payload_len >> (8 * (15 - formatted_length_tmp))); + formatted_length_tmp++; + } while (16 != formatted_length_tmp); + + /* adding Adata to formatted data B */ + if (0 < a_len) + { + formatted_length_tmp++; + formatted_data[formatted_length_tmp] = a_len; + formatted_length_tmp++; + memcpy(formatted_data + formatted_length_tmp, adata, a_len); + formatted_length_tmp += a_len; + if (0 != (formatted_length_tmp % RSIP_PRV_BYTE_SIZE_AES_BLOCK)) + { + formatted_length_tmp += + (RSIP_PRV_BYTE_SIZE_AES_BLOCK - (formatted_length_tmp % RSIP_PRV_BYTE_SIZE_AES_BLOCK)); + } + } + + *formatted_length = formatted_length_tmp >> 2; + + /* formatting flag section in counter0 */ + flag = (uint8_t) (q_len - 1); + counter[0] = flag; + + /* adding nonce to counter0 */ + memcpy(counter + 1, nonce, nonce_len); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_chacha.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_chacha.c new file mode 100644 index 0000000000..a401a3f58a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_chacha.c @@ -0,0 +1,1195 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define RSIP_PRV_CHACHA_INIT_LEN (0xFFFFFFFFU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static fsp_err_t chacha_poly_init(rsip_ctrl_t * p_ctrl, + rsip_chacha_poly_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_nonce, + uint32_t nonce_length); +static fsp_err_t chacha_poly_aad_update(rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, uint32_t aad_length); +static fsp_err_t chacha_poly_update(rsip_ctrl_t * p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length); +static fsp_err_t chacha_poly_finish(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag); +static fsp_err_t chacha_poly_verify(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Prepares a ChaCha20 function. + * + * Implements @ref rsip_api_t::chacha20Init. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_key must be RSIP_KEY_TYPE_CHACHA20. + * + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|-------------| + * |FSP_SUCCESS |STATE_CHACHA | + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ChaCha20_Init (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_nonce, + uint32_t const counter) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_chacha20_handle_t * p_handle = &p_instance_ctrl->handle.chacha20; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ASSERT(p_nonce); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + const rsip_func_subset_chacha20_t * p_func = &gp_func_chacha20[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_CHACHA == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func->p_init, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Set function */ + p_handle->p_func = p_func; + + /* Copy wrapped key */ + p_handle->wrapped_key.type = p_wrapped_key->type; + p_handle->wrapped_key.p_value = p_handle->wrapped_key_value; + memcpy(p_handle->wrapped_key_value, p_wrapped_key->p_value, RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type)); + + /* Copy nonce */ + p_handle->nonce_buffer[0] = bswap_32big(((uint32_t *) p_nonce)[0]); + p_handle->nonce_buffer[1] = bswap_32big(((uint32_t *) p_nonce)[1]); + p_handle->nonce_buffer[2] = bswap_32big(((uint32_t *) p_nonce)[2]); + + /* Reset handle */ + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + p_handle->buffered_length = 0; + p_handle->total_length = 0; + + /* Call function (cast to match the argument type with the primitive function) */ + uint32_t init_length[1] = {RSIP_PRV_CHACHA_INIT_LEN}; + rsip_ret_t rsip_ret = p_func->p_init((const uint32_t *) p_handle->wrapped_key_value, + &counter, + p_handle->nonce_buffer, + init_length); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_CHACHA; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Encrypts plaintext or decrypts ciphertext. + * + * Implements @ref rsip_api_t::chacha20Update. + * + * @par Output length + * Output length to p_output (p_output_length) is calculated text that has not yet been output in multiple of 64 bytes. + * + * @par State transition + * @parblock + * This API can only be executed in **RSIP_STATE_CHACHA**, and does not cause any state transitions. + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ChaCha20_Update (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_input || (0 == input_length)); + FSP_ASSERT(p_output || (0 == input_length)); + FSP_ASSERT(p_output_length); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_chacha20_handle_t * p_handle = &p_instance_ctrl->handle.chacha20; + rsip_func_subset_chacha20_t * p_func = (rsip_func_subset_chacha20_t *) p_handle->p_func; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_CHACHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t length_rest = 0; + *p_output_length = 0; + + /* Input plaintext/ciphertext */ + if (0 != input_length) + { + p_handle->total_length += input_length; + if ((p_handle->buffered_length + input_length) >= RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) + { + /* Input remaining data in buffer */ + memcpy((&p_handle->buffer[0] + p_handle->buffered_length), + p_input, + RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - p_handle->buffered_length); + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((uint32_t *) (p_handle->buffer), (uint32_t *) (p_output), + r_rsip_byte_to_word_convert(RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK)); + length_rest = input_length - + (RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - p_handle->buffered_length); + *p_output_length += RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK; + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + + /* Input block data */ + if (length_rest >= RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) + { + uint32_t block_data_length = (length_rest / RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) * + RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK; + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((const uint32_t *) (p_input + + (RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - + p_handle->buffered_length)), + (uint32_t *) (p_output + RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK), + r_rsip_byte_to_word_convert(block_data_length)); + length_rest -= block_data_length; + *p_output_length += block_data_length; + } + + p_handle->buffered_length = 0; + + /* Store remaining data to buffer */ + memcpy(p_handle->buffer, p_input + (input_length - length_rest), length_rest); + p_handle->buffered_length = length_rest; + } + else + { + /* Store remaining data to buffer */ + memcpy(&p_handle->buffer[0] + p_handle->buffered_length, p_input, input_length); + p_handle->buffered_length += input_length; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Finalize ChaCha20 operation. + * + * Implements @ref rsip_api_t::chacha20Finish. + * + * @par Output length + * @parblock + * Output length to p_output (p_output_length) is the remaining calculated text length. + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **RSIP_STATE_CHACHA**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ChaCha20_Finish (rsip_ctrl_t * const p_ctrl, uint8_t * const p_output, + uint32_t * const p_output_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_output); + FSP_ASSERT(p_output_length); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_chacha20_handle_t * p_handle = &p_instance_ctrl->handle.chacha20; + rsip_func_subset_chacha20_t * p_func = (rsip_func_subset_chacha20_t *) p_handle->p_func; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_CHACHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Set remaining data */ + if ((0 != (p_handle->total_length % RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK)) || + (0 == p_handle->total_length)) + { + memset(p_handle->buffer + p_handle->buffered_length, 0, + (RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - p_handle->buffered_length)); + } + + /* Set parameters */ + *p_output_length = p_handle->buffered_length; + + /* Call function (cast to match the argument type with the primitive function) */ + uint32_t internal_state[2]; + + /* The suspend function always returns RSIP_RET_PASS, so the return value is not checked */ + p_func->p_suspend(internal_state); + + /* Reflect remaining text length in the internal state */ + internal_state[1] = p_handle->buffered_length; + rsip_ret_t rsip_ret = p_func->p_resume((const uint32_t *) p_handle->wrapped_key_value, + (const uint32_t *) p_handle->nonce_buffer, + internal_state); + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = + p_func->p_final((uint32_t *) (p_handle->buffer), (uint32_t *) p_output, + r_rsip_byte_to_word_convert(p_handle->buffered_length)); + } + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Prepares a ChaCha20-Poly1305 function. + * + * Implements @ref rsip_api_t::chacha20Poly1305Init. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_key must be RSIP_KEY_TYPE_CHACHA20. + * + * Argument mode accepts any member of enumeration @ref rsip_chacha_poly_mode_t. + * + * Argument nonce_length must be 12 bytes. + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|------------------| + * |FSP_SUCCESS |STATE_CHACHA_POLY | + * |Others |No change | + * + * The next callable API functions in STATE_CHACHA_POLY are as below. + * - R_RSIP_ChaCha20_Poly1305_AADUpdate(), R_RSIP_ChaCha20_Poly1305_Update(), R_RSIP_ChaCha20_Poly1305_Finish() (encryption), + * R_RSIP_ChaCha20_Poly1305_Verify() (decryption) + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_INVALID_ARGUMENT Input mode is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ChaCha20_Poly1305_Init (rsip_ctrl_t * const p_ctrl, + rsip_chacha_poly_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_nonce, + uint32_t const nonce_length) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ASSERT(p_nonce); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + + FSP_ERROR_RETURN(RSIP_PRV_ALG_CHACHA == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type +#endif + + /* Check argument */ + fsp_err_t err = FSP_ERR_INVALID_ARGUMENT; + switch (mode) + { + /* ChaCha20-Poly1305 */ + case RSIP_CHACHA20_POLY1305_MODE_ENC: + case RSIP_CHACHA20_POLY1305_MODE_DEC: + { + err = chacha_poly_init(p_ctrl, mode, p_wrapped_key, p_nonce, nonce_length); + break; + } + + default: + { + /* Invalid argument */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Inputs Additional Authentication Data (AAD). + * + * Implements @ref rsip_api_t::chacha20Poly1305AadUpdate. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_CHACHA_POLY**, and does not cause any state transitions. + * + * - R_RSIP_ChaCha20_Poly1305_AADUpdate(), R_RSIP_ChaCha20_Poly1305_Update(), R_RSIP_ChaCha20_Poly1305_Finish() (encryption), + * R_RSIP_ChaCha20_Poly1305_Verify() (decryption) + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ChaCha20_Poly1305_AADUpdate (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_aad, + uint32_t const aad_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_aad || (0 == aad_length)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* ChaCha20-Poly1305 (AAD update) */ + case RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD: + case RSIP_STATE_CHACHA_POLY_DEC_UPDATE_AAD: + { + err = chacha_poly_aad_update(p_ctrl, p_aad, aad_length); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Encrypts plaintext or decrypts ciphertext. + * + * Implements @ref rsip_api_t::chacha20Poly1305Update. + * + * @par Conditions + * At least one byte of data must be input with this API before calling R_RSIP_ChaCha20_Poly1305_Finish() or R_RSIP_ChaCha20_Poly1305_Verify(). + * + * @par Output length + * Output length to p_output (p_output_length) is calculated text that has not yet been output in multiple of 64 bytes. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_CHACHA_POLY**, and does not cause any state transitions. + * + * - R_RSIP_ChaCha20_Poly1305_Update(), R_RSIP_ChaCha20_Poly1305_Finish() (encryption), R_RSIP_ChaCha20_Poly1305_Verify() (decryption) + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ChaCha20_Poly1305_Update (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_input || (0 == input_length)); + FSP_ASSERT(p_output || (0 == input_length)); + FSP_ASSERT(p_output_length); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* ChaCha20-Poly1305 (AAD update, text update) */ + case RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD: + case RSIP_STATE_CHACHA_POLY_DEC_UPDATE_AAD: + case RSIP_STATE_CHACHA_POLY_ENC_UPDATE_TEXT: + case RSIP_STATE_CHACHA_POLY_DEC_UPDATE_TEXT: + { + err = chacha_poly_update(p_ctrl, p_input, input_length, p_output, p_output_length); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes a ChaCha20-Poly1305 encryption. + * + * Implements @ref rsip_api_t::chacha20Poly1305Finish. + * + * @par Output length + * @parblock + * Output length to p_output (p_output_length) is the remaining calculated text length. + * + * Output length to p_tag is 16 bytes. + * @endparblock + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_CHACHA_POLY**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |FSP_ERR_INVALID_SIZE |No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE Input text length is illegal. (zero byte) + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ChaCha20_Poly1305_Finish (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_output); + FSP_ASSERT(p_output_length); + FSP_ASSERT(p_tag); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* ChaCha20-Poly1305 encryption (text update) */ + case RSIP_STATE_CHACHA_POLY_ENC_UPDATE_TEXT: + { + err = chacha_poly_finish(p_ctrl, p_output, p_output_length, p_tag); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes a ChaCha20-Poly1305 decryption. + * + * Implements @ref rsip_api_t::chacha20Poly1305Verify. + * + * @par Conditions + * Argument tag_length must be 16 bytes. + * + * @par Output length + * Output length to p_output (p_output_length) is the remaining calculated text length. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_CHACHA_POLY**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE tag_length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_AUTHENTICATION Authentication is failed. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ChaCha20_Poly1305_Verify (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_output); + FSP_ASSERT(p_output_length); + FSP_ASSERT(p_tag); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + fsp_err_t err = FSP_ERR_INVALID_STATE; + switch (p_instance_ctrl->state) + { + /* ChaCha20-Poly1305 decryption (text update) */ + case RSIP_STATE_CHACHA_POLY_DEC_UPDATE_TEXT: + { + err = chacha_poly_verify(p_ctrl, p_output, p_output_length, p_tag, tag_length); + break; + } + + default: + { + /* Invalid state */ + } + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Prepares a ChaCha20-Poly1305. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE nonce_length is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t chacha_poly_init (rsip_ctrl_t * p_ctrl, + rsip_chacha_poly_mode_t mode, + const rsip_wrapped_key_t * p_wrapped_key, + const uint8_t * p_nonce, + uint32_t nonce_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_chacha20_poly1305_handle_t * p_handle = &p_instance_ctrl->handle.chacha20_poly1305; + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + const rsip_func_subset_chacha20_poly1305_t * p_func = &gp_func_chacha20_poly1305[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(p_func->p_init_enc, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Check size */ + FSP_ERROR_RETURN(nonce_length == 12, FSP_ERR_INVALID_SIZE); + + /* Initialize handle */ + r_rsip_handle_reset(&p_instance_ctrl->handle); + + /* Set function */ + p_handle->p_func = p_func; + + /* Copy wrapped key */ + p_handle->wrapped_key.type = p_wrapped_key->type; + p_handle->wrapped_key.p_value = p_handle->wrapped_key_value; + memcpy(p_handle->wrapped_key_value, p_wrapped_key->p_value, RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type)); + + /* Copy nonce */ + p_handle->nonce_buffer[0] = bswap_32big(((uint32_t *) p_nonce)[0]); + p_handle->nonce_buffer[1] = bswap_32big(((uint32_t *) p_nonce)[1]); + p_handle->nonce_buffer[2] = bswap_32big(((uint32_t *) p_nonce)[2]); + + /* Select init function */ + rsip_func_chacha_poly_init_t p_func_init = (RSIP_CHACHA20_POLY1305_MODE_ENC == mode) ? + p_func->p_init_enc : p_func->p_init_dec; + + /* Call function (cast to match the argument type with the primitive function) */ + uint32_t init_length[1] = {RSIP_PRV_CHACHA_INIT_LEN}; + uint32_t init_aad_length[1] = {RSIP_PRV_CHACHA_INIT_LEN}; + rsip_ret_t rsip_ret = p_func_init((const uint32_t *) p_handle->wrapped_key_value, + p_handle->nonce_buffer, + init_length, + init_aad_length); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* + * State transition + * RSIP_CHACHA20_POLY1305_MODE_ENC -> RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD + * RSIP_CHACHA20_POLY1305_MODE_DEC -> RSIP_STATE_CHACHA_POLY_DEC_UPDATE_AAD + */ + p_instance_ctrl->state = + (RSIP_CHACHA20_POLY1305_MODE_ENC == mode) ? + RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD : RSIP_STATE_CHACHA_POLY_DEC_UPDATE_AAD; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Inputs aad and executes encryption and decryption. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +static fsp_err_t chacha_poly_aad_update (rsip_ctrl_t * p_ctrl, const uint8_t * p_aad, uint32_t aad_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_chacha20_poly1305_handle_t * p_handle = &p_instance_ctrl->handle.chacha20_poly1305; + rsip_func_subset_chacha20_poly1305_t * p_func = (rsip_func_subset_chacha20_poly1305_t *) p_handle->p_func; + + uint32_t length_rest = 0; + + /* Input AAD */ + if (0 != aad_length) + { + p_handle->total_aad_length += aad_length; + + if ((p_handle->buffered_length + aad_length) >= RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) + { + /* Input remaining data in buffer */ + memcpy((&p_handle->buffer[0] + p_handle->buffered_length), + p_aad, + RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - p_handle->buffered_length); + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_updateAad((uint32_t *) (p_handle->buffer), + r_rsip_byte_to_word_convert((RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK))); + length_rest = aad_length - + (RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - p_handle->buffered_length); + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + + /* Input block data */ + if (length_rest >= RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) + { + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_updateAad((const uint32_t *) (p_aad + + (RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - + p_handle->buffered_length)), + r_rsip_byte_to_word_convert((length_rest / RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) * + RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK)); + length_rest -= ((length_rest / RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) * RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK); + } + + p_handle->buffered_length = 0; + + /* Store remaining data to buffer */ + memcpy(p_handle->buffer, p_aad + (aad_length - length_rest), length_rest); + p_handle->buffered_length = length_rest; + } + else + { + /* Store remaining data to buffer */ + memcpy(&p_handle->buffer[0] + p_handle->buffered_length, p_aad, aad_length); + p_handle->buffered_length += aad_length; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Inputs aad and executes encryption and decryption. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t chacha_poly_update (rsip_ctrl_t * p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_chacha20_poly1305_handle_t * p_handle = &p_instance_ctrl->handle.chacha20_poly1305; + rsip_func_subset_chacha20_poly1305_t * p_func = (rsip_func_subset_chacha20_poly1305_t *) p_handle->p_func; + + uint32_t length_rest = 0; + *p_output_length = 0; + + /* If plaintext/ciphertext is input for the first time, input remaining AAD and prohibit new AAD input */ + rsip_ret_t rsip_ret = RSIP_RET_UNKNOWN; + switch (p_instance_ctrl->state) + { + case RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD: + case RSIP_STATE_CHACHA_POLY_DEC_UPDATE_AAD: + { + /* The suspend function always returns RSIP_RET_PASS, so the return value is not checked */ + uint32_t internal_state[16]; + p_func->p_suspend(internal_state); + + /* Select resume function */ + rsip_func_chacha_poly_resume_t p_func_resume = + (RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD == p_instance_ctrl->state) ? + p_func->p_resume_enc : p_func->p_resume_dec; + + /* Reflect remaining AAD length and total AAD length in the internal state */ + internal_state[2] = p_handle->buffered_length; // Set remaining AAD length + internal_state[9] = p_handle->total_aad_length; // Set total AAD length + rsip_ret = p_func_resume((uint32_t *) p_handle->wrapped_key_value, + p_handle->nonce_buffer, + internal_state); + + if (RSIP_RET_PASS_1 == rsip_ret) + { + /* Update remaining AAD */ + p_func->p_updateAad((uint32_t *) (p_handle-> + buffer), + r_rsip_byte_to_word_convert(p_handle->buffered_length)); + + /* Reset buffer */ + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + p_handle->buffered_length = 0; + + /* Prohibit AAD input and start plaintext/ciphertext input */ + p_func->p_updateTransition(); + + /* + * State transition + * RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD -> RSIP_STATE_CHACHA_POLY_ENC_UPDATE_TEXT + * RSIP_STATE_CHACHA_POLY_DEC_UPDATE_AAD -> RSIP_STATE_CHACHA_POLY_DEC_UPDATE_TEXT + */ + p_instance_ctrl->state = (p_instance_ctrl->state == RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD) ? + RSIP_STATE_CHACHA_POLY_ENC_UPDATE_TEXT : RSIP_STATE_CHACHA_POLY_DEC_UPDATE_TEXT; + } + + break; + } + + default: + { + rsip_ret = RSIP_RET_PASS_1; + } + } + + /* Input plaintext/ciphertext */ + if (RSIP_RET_PASS_1 == rsip_ret) + { + if (0 != input_length) + { + p_handle->total_length += input_length; + if ((p_handle->buffered_length + input_length) >= RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) + { + /* Input remaining data in buffer */ + memcpy((&p_handle->buffer[0] + p_handle->buffered_length), + p_input, + RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - p_handle->buffered_length); + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((uint32_t *) (p_handle->buffer), (uint32_t *) (p_output), + r_rsip_byte_to_word_convert(RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK)); + length_rest = input_length - + (RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - p_handle->buffered_length); + *p_output_length += RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK; + memset(p_handle->buffer, 0, sizeof(p_handle->buffer)); + + /* Input block data */ + if (length_rest >= RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) + { + uint32_t block_data_length = (length_rest / RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK) * + RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK; + + /* Call function (cast to match the argument type with the primitive function) */ + p_func->p_update((const uint32_t *) (p_input + + (RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK - + p_handle->buffered_length)), + (uint32_t *) (p_output + RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK), + r_rsip_byte_to_word_convert(block_data_length)); + length_rest -= block_data_length; + *p_output_length += block_data_length; + } + + p_handle->buffered_length = 0; + + /* Store remaining data to buffer */ + memcpy(p_handle->buffer, p_input + (input_length - length_rest), length_rest); + p_handle->buffered_length = length_rest; + } + else + { + /* Store remaining data to buffer */ + memcpy(&p_handle->buffer[0] + p_handle->buffered_length, p_input, input_length); + p_handle->buffered_length += input_length; + } + } + } + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS_1: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + + /* RSIP_RET_KEY_FAIL does not occur unless the key value in the handle structure is destroyed, + * so it is returned as FSP_ERR_CRYPTO_RSIP_FATAL */ + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes a ChaCha20-Poly1305 encryption. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of ciphertext. The fractional block is output. + * @param[out] p_output_length Pointer to destination of ciphertext length. + * @param[out] p_tag Pointer to destination of tag for authentication. The length is 16 bytes. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE Input data length is invalid. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t chacha_poly_finish (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_chacha20_poly1305_handle_t * p_handle = &p_instance_ctrl->handle.chacha20_poly1305; + rsip_func_subset_chacha20_poly1305_t * p_func = (rsip_func_subset_chacha20_poly1305_t *) p_handle->p_func; + + *p_output_length = p_handle->buffered_length; + + /* Check total input length */ + FSP_ERROR_RETURN(p_handle->total_length >= 1, FSP_ERR_INVALID_SIZE); + + /* The suspend function always returns RSIP_RET_PASS, so the return value is not checked */ + uint32_t internal_state[16]; + p_func->p_suspend(internal_state); + + /* Reflect remaining Text length and total Text length in the internal state */ + internal_state[1] = p_handle->buffered_length; // Set remaining Text length + internal_state[8] = p_handle->total_length; // Set total Text length + rsip_ret_t rsip_ret = p_func->p_resume_enc((uint32_t *) p_handle->wrapped_key_value, + p_handle->nonce_buffer, + internal_state); + + if (RSIP_RET_PASS_2 == rsip_ret) + { + rsip_ret = p_func->p_final((uint32_t *) (p_handle->buffer), + NULL, + (uint32_t *) p_output, + (uint32_t *) p_tag, + bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length))); + } + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes a ChaCha20-Poly1305 decryption. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_output Pointer to destination of plaintext. The fractional block is output. + * @param[out] p_output_length Pointer to destination of plaintext length. + * @param[in] p_tag Pointer to tag for authentication. The length depends on tag_length. + * @param[in] tag_length Byte length of tag. Must be 16. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE Input data length or tag_length is invalid. + * @retval FSP_ERR_CRYPTO_RSIP_AUTHENTICATION Authentication is failed. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t chacha_poly_verify (rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_chacha20_poly1305_handle_t * p_handle = &p_instance_ctrl->handle.chacha20_poly1305; + rsip_func_subset_chacha20_poly1305_t * p_func = (rsip_func_subset_chacha20_poly1305_t *) p_handle->p_func; + + *p_output_length = p_handle->buffered_length; + + /* Check total input length and tag_length */ + FSP_ERROR_RETURN((p_handle->total_length >= 1) && (tag_length == 16), FSP_ERR_INVALID_SIZE); + + /* The suspend function always returns RSIP_RET_PASS, so the return value is not checked */ + uint32_t internal_state[16]; + p_func->p_suspend(internal_state); + + /* Reflect remaining Text length and total Text length in the internal state */ + internal_state[1] = p_handle->buffered_length; // Set remaining Text length + internal_state[8] = p_handle->total_length; // Set total Text length + rsip_ret_t rsip_ret = p_func->p_resume_dec((uint32_t *) p_handle->wrapped_key_value, + p_handle->nonce_buffer, + internal_state); + + if (RSIP_RET_PASS_2 == rsip_ret) + { + rsip_ret = p_func->p_final((uint32_t *) (p_handle->buffer), + (uint32_t *) p_tag, + (uint32_t *) p_output, + NULL, + bswap_32big(r_rsip_byte_to_word_convert(p_handle->buffered_length))); + } + + /* State transition*/ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_AUTH_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_AUTHENTICATION; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_ecc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_ecc.c new file mode 100644 index 0000000000..a8b5a760c9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_ecc.c @@ -0,0 +1,859 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define RSIP_PRV_BYTE_SIZE_EDWARDS25519_MESSAGE_MAX (uint64_t) (0x1FFFFFFFFFFFFFBFU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Generates an ECDSA signature. + * + * Implements @ref rsip_api_t::ecdsaSign. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_SECP256R1_PRIVATE + * - @ref RSIP_KEY_TYPE_ECC_SECP384R1_PRIVATE + * - @ref RSIP_KEY_TYPE_ECC_SECP521R1_PRIVATE + * - @ref RSIP_KEY_TYPE_ECC_SECP256K1_PRIVATE + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PRIVATE + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PRIVATE + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP512R1_PRIVATE + * + * Message hash p_hash should be computed in advance. + * In the case of hash length is less than the key length, padding is required to make it the same as the key length. + * + * For secp521r1 operation, the length of p_hash must be set to 64 bytes. + * + * For secp521r1 operation, the length of the argument p_signature must be set as 132 byte. + * Since 521 bit is not a 8-bit multiple, zero padding is required and the data format is as follows: + * + * + * + * + * + * + * + * + * + * + *
Data Format for secp521r1 (132 byte)
zero padding (7 bit)signature r (521 bit)zero padding (7 bit)signature s (521 bit)
+ * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL @arg Input parameter is illegal. + * @arg Signature generation is failed. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ECDSA_Sign (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_hash, + uint8_t * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + rsip_func_ecdsa_sign_t p_func = gp_func_ecdsa_sign[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PRIVATE == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func((const uint32_t *) p_wrapped_private_key->p_value, (const uint32_t *) p_hash, (uint32_t *) p_signature); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies an ECDSA signature. + * + * Implements @ref rsip_api_t::ecdsaVerify. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP256K1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP512R1_PUBLIC + * + * Message hash p_hash should be computed in advance. + * In the case of hash length is less than the key length, padding is required to make it the same as the key length. + * + * For secp521r1 operation, the length of p_hash must be set to 64 bytes. + * + * For secp521r1 operation, the length of the argument p_signature must be set as 132 byte. + * Since 521 bit is not a 8-bit multiple, zero padding is required and the data format is as follows: + * + * + * + * + * + * + * + * + * + * + *
Data Format for secp521r1 (132 byte)
zero padding (7 bit)signature r (521 bit)zero padding (7 bit)signature s (521 bit)
+ * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL @arg Input parameter is illegal. + * @arg Signature verification is failed. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ECDSA_Verify (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_hash, + uint8_t const * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_ecdsa_verify_t p_func = gp_func_ecdsa_verify[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func((const uint32_t *) p_wrapped_public_key->p_value, + (const uint32_t *) p_hash, + (const uint32_t *) p_signature); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies a public key certificate with ECDSA. + * + * Implements @ref rsip_api_t::pkiEcdsaCertVerify. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PUBLIC + * + * Message hash p_hash should be computed in advance. + * In the case of hash length is less than the key length, padding is required to make it the same as the key length. + * + * For secp521r1 operation, the length of p_hash must be set to 64 bytes. + * + * For secp521r1 operation, the length of the argument p_signature must be set as 132 byte. + * Since 521 bit is not a 8-bit multiple, zero padding is required and the data format is as follows: + * + * + * + * + * + * + * + * + * + * + *
Data Format for secp521r1 (132 byte)
zero padding (7 bit)signature r (521 bit)zero padding (7 bit)signature s (521 bit)
+ * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL @arg Input parameter is illegal. + * @arg Signature verification is failed. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PKI_ECDSA_CertVerify (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_hash, + uint8_t const * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_subset_pki_ecdsa_verify_t p_func = gp_func_pki_ecdsa_verify[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func.p_init, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func.p_init((const uint32_t *) p_wrapped_public_key->p_value, + (const uint32_t *) p_hash, + (const uint32_t *) p_signature); + + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = p_func.p_final((uint32_t *) &p_instance_ctrl->pki_verified_cert_info); + } + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Generates an EdDSA signature. + * + * Implements @ref rsip_api_t::eddsaSign. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_EDWARDS25519_PRIVATE + * + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_EDWARDS25519_PUBLIC + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_INVALID_SIZE Input length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PureEdDSA_Sign (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_message, + uint64_t const message_length, + uint8_t * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_message); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t private_key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + rsip_func_eddsa_sign_t p_func = gp_func_eddsa_sign[private_key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_key_type_extend_t public_key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PRIVATE == private_key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PUBLIC == public_key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(private_key_type_ext.subtype == public_key_type_ext.subtype, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Check length */ + FSP_ERROR_RETURN(RSIP_PRV_BYTE_SIZE_EDWARDS25519_MESSAGE_MAX >= message_length, FSP_ERR_INVALID_SIZE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_wrapped_private_key->p_value, + (const uint32_t *) p_wrapped_public_key->p_value, + (const uint32_t *) p_message, + message_length, + (uint32_t *) p_signature); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies an EdDSA signature. + * + * Implements @ref rsip_api_t::eddsaVerify. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_EDWARDS25519_PUBLIC + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_INVALID_SIZE Input length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PureEdDSA_Verify (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_message, + uint64_t const message_length, + uint8_t const * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_message); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_eddsa_verify_t p_func = gp_func_eddsa_verify[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Check length */ + FSP_ERROR_RETURN(RSIP_PRV_BYTE_SIZE_EDWARDS25519_MESSAGE_MAX >= message_length, FSP_ERR_INVALID_SIZE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_wrapped_public_key->p_value, + (const uint32_t *) p_message, + message_length, + (uint32_t *) p_signature); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Computes ECDH secret with wrapped private key and wrapped public key. + * + * Implements @ref rsip_api_t::ecdhKeyAgree. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key and p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PUBLIC + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ECDH_KeyAgree (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_wrapped_secret_t * const p_wrapped_secret) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_wrapped_secret); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t private_key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + rsip_func_ecdh_t p_func = gp_func_ecdh_wrapped[private_key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_key_type_extend_t public_key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PRIVATE == private_key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PUBLIC == public_key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(private_key_type_ext.subtype == public_key_type_ext.subtype, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_wrapped_public_key->p_value, + (const uint32_t *) p_wrapped_private_key->p_value, + (uint32_t *) p_wrapped_secret->value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + p_wrapped_secret->type = private_key_type_ext.subtype; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Computes ECDH secret with wrapped private key and plain public key. + * + * Implements @ref rsip_api_t::ecdhPlainKeyAgree. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PUBLIC + * + * For secp521r1 operation, the length of the argument p_plain_public_key must be set as 132 byte. + * Since 521 bit is not a 8-bit multiple, zero padding is required and the data format is as follows: + * + * + * + * + * + * + * + * + * + * + *
Data Format for secp521r1 (132 byte)
zero padding (7 bit)public_key Qx (521 bit)zero padding (7 bit)public_key Qy (521 bit)
+ * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @attention Unauthenticated public key of Diffie–Hellman key exchange generally carry the risk of man-in-the-middle + * (MITM) attack. Please use R_RSIP_ECDH_KeyAgree() or implement signature verification whenever possible. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_ECDH_PlainKeyAgree (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_plain_public_key, + rsip_wrapped_secret_t * const p_wrapped_secret) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_plain_public_key); + FSP_ASSERT(p_wrapped_secret); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + rsip_func_ecdh_t p_func = gp_func_ecdh_plain[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_ECC_PRIVATE == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_plain_public_key, + (const uint32_t *) p_wrapped_private_key->p_value, + (uint32_t *) p_wrapped_secret->value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + p_wrapped_secret->type = key_type_ext.subtype; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_kdf.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_kdf.c new file mode 100644 index 0000000000..56b8971134 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_kdf.c @@ -0,0 +1,2075 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA256_MIN (32U) +#define RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA256_MAX (64U) +#define RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA384_MIN (48U) +#define RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA384_MAX (64U) +#define RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA512_MIN (64U) +#define RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA512_MAX (64U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static rsip_func_kdf_derived_key_import_t select_func_derived_key_import(uint8_t dkm_alg, + uint8_t dkm_subtype, + rsip_key_type_t key_type); +static rsip_func_kdf_derived_iv_wrap_t select_func_derived_iv_wrap(uint8_t dkm_alg, + uint8_t dkm_subtype, + rsip_initial_vector_type_t iv_type); +static rsip_ret_t kdf_sha_update(rsip_ctrl_t * const p_ctrl, + const uint8_t * p_message, + uint32_t message_length); +static rsip_ret_t kdf_sha_finish(rsip_ctrl_t * const p_ctrl, uint8_t * p_digest); +static rsip_ret_t kdf_hmac_update(rsip_ctrl_t * const p_ctrl, + const uint8_t * p_message, + uint32_t message_length); +static rsip_ret_t kdf_hmac_sign_finish(rsip_ctrl_t * const p_ctrl, uint8_t * p_mac); + +static const uint8_t gs_kdf_hmac_byte_length_min[] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA256_MIN, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA384_MIN, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA512_MIN, +}; + +static const uint8_t gs_kdf_hmac_byte_length_max[] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA256_MAX, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA384_MAX, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = RSIP_PRV_BYTE_SIZE_KDF_HMAC_SHA512_MAX, +}; + +static const uint8_t gs_convert_to_kdf_sha_subtype[RSIP_HASH_TYPE_NUM] = +{ + [RSIP_HASH_TYPE_SHA256] = RSIP_PRV_DKM_SUBTYPE_SHA_256, + [RSIP_HASH_TYPE_SHA384] = RSIP_PRV_DKM_SUBTYPE_SHA_384, +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Prepares a SHA generation. + * + * Implements @ref rsip_api_t::kdfShaInit. + * + * @par Conditions + * Argument hash_type must be one of the following: + * - @ref RSIP_HASH_TYPE_SHA256 + * - @ref RSIP_HASH_TYPE_SHA384 + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|-------------| + * |FSP_SUCCESS |STATE_KDF_SHA| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_SHA_Init (rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Check configuration */ + FSP_ERROR_RETURN(g_kdf_sha_enabled[hash_type], FSP_ERR_NOT_ENABLED); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_kdf_sha_handle_t * p_handle = &p_instance_ctrl->handle.kdf_sha; + + /* Reset handle */ + memset(p_handle->buffer1, 0, 4); + memset(p_handle->buffer2, 0, RSIP_PRV_BYTE_SIZE_KDF_SHA_BLOCK_BUF); + p_handle->buffered_length1 = 0; + p_handle->buffered_length2 = 0; + p_handle->total_length = 0; + p_handle->wrapped_msg_length = 0; + p_handle->actual_wrapped_msg_length = 0; + + /* Set hash type */ + p_handle->type = hash_type; + + /* Set block size */ + switch (hash_type) + { + /* SHA-256 */ + case RSIP_HASH_TYPE_SHA256: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA1_SHA224_SHA256; + break; + } + + /* SHA-384 */ + default: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA384_SHA512; + break; + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_KDF_SHA; + p_handle->handle_state = RSIP_USER_HANDLE_STATE_INIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Inputs wrapped ECDH secret as a message. + * Input the messages required to perform the SHA operation using this API and R_RSIP_KDF_SHA_Update() in the desired order. + * + * Implements @ref rsip_api_t::kdfShaEcdhSecretUpdate. + * + * @par Conditions + * The argument p_wrapped_secret must be input the result of R_RSIP_ECDH_KeyAgree() or R_RSIP_ECDH_PlainKeyAgree(). + * This API can only be called if there is no previous message input, or if a 4-byte message has been input using R_RSIP_KDF_SHA_Update(). + * This API cannot be called multiple times in a process of performing SHA operation. + * + * @par State transition + * This API can only be executed in **STATE_KDF_SHA**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_SHA_ECDHSecretUpdate (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_t const * const p_wrapped_secret) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_kdf_sha_handle_t * p_handle = &p_instance_ctrl->handle.kdf_sha; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_secret); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Set function */ + uint8_t subtype = gs_convert_to_kdf_sha_subtype[p_handle->type]; + FSP_ERROR_RETURN(subtype < RSIP_PRV_DKM_SUBTYPE_SHA_NUM, FSP_ERR_CRYPTO_RSIP_FATAL); + rsip_func_kdf_ecdh_secret_msg_wrap_t p_func = gp_func_kdf_sha_ecdh_secret_msg_wrap[subtype]; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + + /* Check configuration */ + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_SHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN((0 == p_handle->buffered_length1) || + (4 == p_handle->buffered_length1), + FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->buffered_length2, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->total_length, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->wrapped_msg_length, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) (p_wrapped_secret->value), (uint32_t *) (p_handle->wrapped_msg)); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* Set length */ + switch (p_wrapped_secret->type) + { + /* ECC secp256r1, brainpoolP256r1 */ + case RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1: + case RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1: + { + p_handle->wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_256; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM; + break; + } + + /* ECC secp384r1, brainpoolP384r1 */ + default: + { + p_handle->wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_384; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECC_384_PARAM; + } + } + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Inputs message. + * Input the messages required to perform the SHA operation using this API and R_RSIP_KDF_SHA_ECDHSecretUpdate() in the desired order. + * + * Implements @ref rsip_api_t::kdfShaUpdate. + * + * @par State transition + * This API can only be executed in **STATE_KDF_SHA**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_SHA_Update (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_message, + uint32_t const message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_message || (0 == message_length)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_SHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_kdf_sha_handle_t * p_handle = &p_instance_ctrl->handle.kdf_sha; + + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + if (0 == message_length) + { + err = FSP_SUCCESS; + } + else + { + /* Check if the message only exists in buffer1 */ + if ((0 == p_handle->actual_wrapped_msg_length) && (0 == p_handle->buffered_length2)) + { + if (p_handle->buffered_length1 + message_length <= 4) + { + /* Copy head of new message to buffer1 */ + memcpy(p_handle->buffer1 + p_handle->buffered_length1, p_message, message_length); + p_handle->buffered_length1 += message_length; + + err = FSP_SUCCESS; + } + else + { + /* Copy buffer1 to buffer2 */ + memcpy(p_handle->buffer2, p_handle->buffer1, p_handle->buffered_length1); + p_handle->buffered_length2 = p_handle->buffered_length1; + p_handle->buffered_length1 = 0; + } + } + + if (FSP_SUCCESS != err) + { + rsip_ret_t rsip_ret = RSIP_RET_PASS; + uint32_t processed_len = 0; + + const uint8_t * p_msg_pos = p_message; + + /* (0) Remaining message in buffer and head of new input message (wrapped) */ + if ((0 != p_handle->actual_wrapped_msg_length) && + (p_handle->block_size < + (p_handle->buffered_length1 + p_handle->actual_wrapped_msg_length + p_handle->buffered_length2 + + message_length))) + { + uint32_t len = p_handle->block_size - p_handle->buffered_length1 - p_handle->actual_wrapped_msg_length - + p_handle->buffered_length2; + + /* Copy head of new message to buffer */ + memcpy(p_handle->buffer2 + p_handle->buffered_length2, p_msg_pos, len); + + /* Call function */ + rsip_ret = kdf_sha_update(p_ctrl, p_handle->buffer2, p_handle->block_size); + + p_handle->wrapped_msg_length = 0; + p_handle->actual_wrapped_msg_length = 0; + p_handle->buffered_length1 = 0; + p_handle->buffered_length2 = 0; + p_handle->total_length += p_handle->block_size; + processed_len += len; + } + + /* (1) Remaining message in buffer and head of new input message */ + if ((0 != p_handle->buffered_length2) && + (p_handle->block_size < (p_handle->buffered_length2 + message_length))) + { + uint32_t len = p_handle->block_size - p_handle->buffered_length2; + + /* Copy head of new message to buffer */ + memcpy(p_handle->buffer2 + p_handle->buffered_length2, p_msg_pos, len); + + /* Call function */ + rsip_ret = kdf_sha_update(p_ctrl, p_handle->buffer2, p_handle->block_size); + + p_handle->buffered_length2 = 0; + p_handle->total_length += p_handle->block_size; + processed_len += len; + } + + /* (2) New input message except last block */ + if ((p_handle->block_size < message_length - processed_len) && (RSIP_RET_PASS == rsip_ret)) + { + uint32_t len = ((message_length - processed_len - 1) / p_handle->block_size) * + p_handle->block_size; + + /* Call function */ + rsip_ret = kdf_sha_update(p_ctrl, p_message + processed_len, len); + + p_handle->total_length += len; + processed_len += len; + } + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* (3) Last block */ + memcpy(p_handle->buffer2 + p_handle->buffered_length2, + p_message + processed_len, + message_length - processed_len); + p_handle->buffered_length2 += message_length - processed_len; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes a SHA operation and generate DKM (Derived Keying Material). + * + * Implements @ref rsip_api_t::kdfShaFinish. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_KDF_SHA**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_SHA_Finish (rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t * const p_wrapped_dkm) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_kdf_sha_handle_t * p_handle = &p_instance_ctrl->handle.kdf_sha; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_dkm); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_SHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Check if the message only exists in buffer1 */ + if ((0 == p_handle->wrapped_msg_length) && (0 == p_handle->buffered_length2)) + { + /* Copy buffer1 to buffer2 */ + memcpy(p_handle->buffer2, p_handle->buffer1, p_handle->buffered_length1); + p_handle->buffered_length2 = p_handle->buffered_length1; + p_handle->buffered_length1 = 0; + } + + /* Call function */ + rsip_ret_t rsip_ret = kdf_sha_finish(p_ctrl, p_wrapped_dkm->value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + p_wrapped_dkm->alg = RSIP_PRV_DKM_ALG_SHA; + p_wrapped_dkm->blocks = 1; + switch (p_handle->type) + { + /* SHA-256 */ + case RSIP_HASH_TYPE_SHA256: + { + p_wrapped_dkm->subtype = RSIP_PRV_DKM_SUBTYPE_SHA_256; + p_wrapped_dkm->block_length = RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA256; + break; + } + + /* SHA-384 */ + default: + { + p_wrapped_dkm->subtype = RSIP_PRV_DKM_SUBTYPE_SHA_384; + p_wrapped_dkm->block_length = RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA384; + } + } + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Suspends SHA operation. + * + * This API releases RSIP resource and outputs intermediate results. Therefore, it can be used in the following cases: + * - Execute another cryptographic operations during inputting successive chunks of the message. + * - Reuse intermediate results. + * + * Implements @ref rsip_api_t::kdfShaSuspend. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_KDF_SHA**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_SHA_Suspend (rsip_ctrl_t * const p_ctrl, rsip_kdf_sha_handle_t * const p_handle) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_handle); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_SHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_ret_t rsip_ret; + switch (p_instance_ctrl->handle.kdf_sha.handle_state) + { + /* If the state is update, call suspension function */ + case RSIP_USER_HANDLE_STATE_UPDATE: + { + /* Read internal state */ + rsip_ret = r_rsip_kdf_sha_suspend(&p_instance_ctrl->handle.kdf_sha); + + /* Handle state transition */ + p_instance_ctrl->handle.kdf_sha.handle_state = RSIP_USER_HANDLE_STATE_RESUME; + break; + } + + default: + { + rsip_ret = RSIP_RET_PASS; + } + } + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* Copy handle */ + *p_handle = p_instance_ctrl->handle.kdf_sha; + + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return err; +} + +/*******************************************************************************************************************//** + * Resumes SHA operation suspended by R_RSIP_KDF_SHA_Suspend(). + * + * Implements @ref rsip_api_t::kdfShaResume. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|-------------| + * |FSP_SUCCESS |STATE_KDF_SHA| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_SHA_Resume (rsip_ctrl_t * const p_ctrl, rsip_kdf_sha_handle_t const * const p_handle) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_handle); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Copy handle */ + p_instance_ctrl->handle.kdf_sha = *p_handle; + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_KDF_SHA; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Converts wrapped MAC to wrapped HMAC key for KDF. + * + * Implements @ref rsip_api_t::kdfHmacDkmKeyImport. + * + * @par Conditions + * @parblock + * Argument key_type must be one of the following: + * - @ref RSIP_KEY_TYPE_KDF_HMAC_SHA256 + * - @ref RSIP_KEY_TYPE_KDF_HMAC_SHA384 + * - @ref RSIP_KEY_TYPE_KDF_HMAC_SHA512 + * + * The argument p_wrapped_dkm must be input the result of R_RSIP_KDF_HMAC_SignFinish(). + * @endparblock + * + * Argument kdf_data_length depends on key type. + * - 32 to 64 ( @ref RSIP_KEY_TYPE_KDF_HMAC_SHA256) + * - 48 to 64 ( @ref RSIP_KEY_TYPE_KDF_HMAC_SHA384) + * - 64 ( @ref RSIP_KEY_TYPE_KDF_HMAC_SHA512) + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_DKMKeyImport (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_dkm_t const * const p_wrapped_dkm, + uint32_t const key_length, + rsip_wrapped_key_t * const p_wrapped_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_dkm); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + rsip_func_kdf_dkm_key_import_t p_func = gp_func_kdf_hmac_dkm_key_import[key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_KDF_HMAC == key_type_ext.alg, FSP_ERR_NOT_ENABLED); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Check length */ + FSP_ERROR_RETURN(gs_kdf_hmac_byte_length_min[key_type_ext.subtype] <= key_length, FSP_ERR_INVALID_SIZE); + FSP_ERROR_RETURN(gs_kdf_hmac_byte_length_max[key_type_ext.subtype] >= key_length, FSP_ERR_INVALID_SIZE); + + uint32_t blocks[1] = {bswap_32big((gs_kdf_hmac_byte_length_min[key_type_ext.subtype] == key_length) ? 1 : 2)}; + uint32_t len[1] = {bswap_32big(key_length)}; + + /* Call function */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_wrapped_dkm->value, + (const uint32_t *) blocks, + (const uint32_t *) len, + (uint32_t *) p_wrapped_key->p_value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Converts wrapped ECDH secret to wrapped HMAC key for KDF. + * + * Implements @ref rsip_api_t::kdfHmacEcdhSecretKeyImport. + * + * @par Conditions + * @parblock + * Argument key_type must be one of the following: + * - @ref RSIP_KEY_TYPE_KDF_HMAC_SHA256 + * - @ref RSIP_KEY_TYPE_KDF_HMAC_SHA384 + * - @ref RSIP_KEY_TYPE_KDF_HMAC_SHA512 + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_ECDHSecretKeyImport (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_t const * const p_wrapped_secret, + rsip_wrapped_key_t * const p_wrapped_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_secret); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + rsip_func_kdf_ecdh_secret_key_import_t p_func = + gp_func_kdf_hmac_ecdh_secret_key_import[key_type_ext.subtype][p_wrapped_secret->type]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_KDF_HMAC == key_type_ext.alg, FSP_ERR_NOT_ENABLED); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_wrapped_secret->value, (uint32_t *) p_wrapped_key->p_value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Prepares a HMAC generation. + * + * Implements @ref rsip_api_t::kdfHmacInit. + * + * @par Conditions + * Argument p_wrapped_key must be one of the following: + * - Output data p_wrapped_key from R_RSIP_KDF_ECDHSecretKeyImport(). + * - Key type of p_wrapped_key is RSIP_KEY_TYPE_HMAC_*. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|--------------| + * |FSP_SUCCESS |STATE_KDF_HMAC| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_Init (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN((RSIP_PRV_ALG_HMAC == key_type_ext.alg) || (RSIP_PRV_ALG_KDF_HMAC == key_type_ext.alg), + FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(g_kdf_hmac_enabled[key_type_ext.subtype], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_kdf_hmac_handle_t * p_handle = &p_instance_ctrl->handle.kdf_hmac; + + /* Reset handle */ + p_handle->buffered_length = 0; + p_handle->total_length = 0; + p_handle->wrapped_msg_length = 0; + p_handle->actual_wrapped_msg_length = 0; + + /* Copy wrapped key */ + p_handle->wrapped_key.type = p_wrapped_key->type; + p_handle->wrapped_key.p_value = p_handle->wrapped_key_value; + memcpy(p_handle->wrapped_key_value, p_wrapped_key->p_value, RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type)); + + /* Set block size */ + switch (key_type_ext.subtype) + { + /* SHA-256 */ + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA1_SHA224_SHA256; + break; + } + + /* SHA-384, SHA-512 */ + default: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA384_SHA512; + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_KDF_HMAC; + p_handle->handle_state = RSIP_USER_HANDLE_STATE_INIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Inputs wrapped Derived Keying Material (DKM) as a message. + * + * Implements @ref rsip_api_t::kdfHmacDkmUpdate. + * + * @par Conditions + * The argument p_wrapped_dkm must be input the result of R_RSIP_KDF_HMAC_SignFinish(). + * + * @par State transition + * This API can only be executed in **STATE_KDF_HMAC**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_DKMUpdate (rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t const * const p_wrapped_dkm) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_kdf_hmac_handle_t * p_handle = &p_instance_ctrl->handle.kdf_hmac; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_dkm); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->buffered_length, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->total_length, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->wrapped_msg_length, FSP_ERR_INVALID_STATE); + + /* Copy wrapped DKM */ + memcpy(p_handle->wrapped_msg, p_wrapped_dkm->value, RSIP_PRV_BYTE_SIZE_KDF_WRAPPED_MSG_BUF); + + /* Set length */ + switch (p_wrapped_dkm->subtype) + { + /* SHA-256 */ + case RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256: + { + p_handle->wrapped_msg_length = RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA256; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_DIGEST_SHA256; + break; + } + + /* SHA-384 */ + case RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384: + { + p_handle->wrapped_msg_length = RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA384; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_DIGEST_SHA384; + break; + } + + /* SHA-512 */ + default: + { + p_handle->wrapped_msg_length = RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA512; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_DIGEST_SHA512; + break; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Inputs wrapped ECDH secret as a message. + * + * Implements @ref rsip_api_t::kdfHmacEcdhSecretUpdate. + * + * @par Conditions + * The argument p_wrapped_secret must be input the result of R_RSIP_ECDH_KeyAgree() or R_RSIP_ECDH_PlainKeyAgree(). + * + * @par State transition + * This API can only be executed in **STATE_KDF_HMAC**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_ECDHSecretUpdate (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_t const * const p_wrapped_secret) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_kdf_hmac_handle_t * p_handle = &p_instance_ctrl->handle.kdf_hmac; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_secret); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); // Parse key type + + /* Set function */ + rsip_func_kdf_ecdh_secret_msg_wrap_t p_func = + gp_func_kdf_hmac_ecdh_secret_msg_wrap[key_type_ext.subtype][p_wrapped_secret->type]; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + + /* Check configuration */ + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->buffered_length, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->total_length, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(0 == p_handle->wrapped_msg_length, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) (p_wrapped_secret->value), (uint32_t *) (p_handle->wrapped_msg)); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* Set length */ + switch (p_wrapped_secret->type) + { + /* ECC secp256r1, brainpoolP256r1 */ + case RSIP_PRV_KEY_SUBTYPE_ECC_SECP256R1: + case RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP256R1: + { + p_handle->wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_256; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECC_256_PARAM; + break; + } + + /* ECC secp384r1, brainpoolP384r1 */ + case RSIP_PRV_KEY_SUBTYPE_ECC_SECP384R1: + case RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP384R1: + { + p_handle->wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_384; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECC_384_PARAM; + break; + } + + /* ECC brainpoolP512r1 */ + case RSIP_PRV_KEY_SUBTYPE_ECC_BRAINPOOLP512R1: + { + p_handle->wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_512; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECC_512_PARAM; + break; + } + + /* ECC secp521r1 */ + default: + { + p_handle->wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_521; + p_handle->actual_wrapped_msg_length = RSIP_PRV_BYTE_SIZE_ECC_521_PARAM; + break; + } + } + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Inputs message. + * + * Implements @ref rsip_api_t::kdfHmacUpdate. + * + * @par State transition + * This API can only be executed in **STATE_KDF_HMAC**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_Update (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_message, + uint32_t const message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_message || (0 == message_length)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_kdf_hmac_handle_t * p_handle = &p_instance_ctrl->handle.kdf_hmac; + + if (0 == message_length) + { + err = FSP_SUCCESS; + } + else + { + rsip_ret_t rsip_ret = RSIP_RET_PASS; + const uint8_t * p_msg_pos = p_message; + uint32_t processed_len = 0; + + /* (0) Remaining message in buffer and head of new input message (wrapped) */ + if ((0 != p_handle->actual_wrapped_msg_length) && + (p_handle->block_size < (p_handle->actual_wrapped_msg_length + p_handle->buffered_length + message_length))) + { + uint32_t len = p_handle->block_size - p_handle->buffered_length - p_handle->actual_wrapped_msg_length; + + /* Copy head of new message to buffer */ + memcpy(p_handle->buffer + p_handle->buffered_length, p_msg_pos, len); + + /* Call function */ + rsip_ret = kdf_hmac_update(p_ctrl, p_handle->buffer, p_handle->block_size); + + p_handle->wrapped_msg_length = 0; + p_handle->actual_wrapped_msg_length = 0; + p_handle->buffered_length = 0; + p_handle->total_length += p_handle->block_size; + processed_len += len; + } + + /* (1) Remaining message in buffer and head of new input message */ + if ((0 != p_handle->buffered_length) && + (p_handle->block_size < (p_handle->buffered_length + message_length))) + { + uint32_t len = p_handle->block_size - p_handle->buffered_length; + + /* Copy head of new message to buffer */ + memcpy(p_handle->buffer + p_handle->buffered_length, p_msg_pos, len); + + /* Call function */ + rsip_ret = kdf_hmac_update(p_ctrl, p_handle->buffer, p_handle->block_size); + + p_handle->buffered_length = 0; + p_handle->total_length += p_handle->block_size; + processed_len += len; + } + + /* (2) New input message except last block */ + if ((p_handle->block_size < message_length - processed_len) && (RSIP_RET_PASS == rsip_ret)) + { + uint32_t len = ((message_length - processed_len - 1) / p_handle->block_size) * + p_handle->block_size; + + /* Call function */ + rsip_ret = kdf_hmac_update(p_ctrl, p_message + processed_len, len); + + p_handle->total_length += len; + processed_len += len; + } + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* (3) Last block */ + memcpy(p_handle->buffer + p_handle->buffered_length, + p_message + processed_len, + message_length - processed_len); + p_handle->buffered_length += message_length - processed_len; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes a HMAC generation. + * + * Implements @ref rsip_api_t::kdfHmacSignFinish. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_KDF_HMAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_SignFinish (rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t * const p_wrapped_dkm) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + + rsip_kdf_hmac_handle_t * p_handle = &p_instance_ctrl->handle.kdf_hmac; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_dkm); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); // Parse key type + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function */ + rsip_ret_t rsip_ret = kdf_hmac_sign_finish(p_ctrl, p_wrapped_dkm->value); + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + p_wrapped_dkm->alg = RSIP_PRV_DKM_ALG_HMAC; + p_wrapped_dkm->blocks = 1; + switch (key_type_ext.subtype) + { + /* SHA-256 */ + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256: + { + p_wrapped_dkm->subtype = RSIP_PRV_DKM_SUBTYPE_HMAC_SHA256; + p_wrapped_dkm->block_length = RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA256; + break; + } + + /* SHA-384 */ + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384: + { + p_wrapped_dkm->subtype = RSIP_PRV_DKM_SUBTYPE_HMAC_SHA384; + p_wrapped_dkm->block_length = RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA384; + break; + } + + /* SHA-512 */ + default: + { + p_wrapped_dkm->subtype = RSIP_PRV_DKM_SUBTYPE_HMAC_SHA512; + p_wrapped_dkm->block_length = RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA512; + break; + } + } + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Suspends HMAC operation. + * + * This API releases RSIP resource and outputs intermediate results. Therefore, it can be used in the following cases: + * - Execute another cryptographic operations during inputting successive chunks of the message. + * - Reuse intermediate results. + * + * Implements @ref rsip_api_t::kdfHmacSuspend. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_KDF_HMAC**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_Suspend (rsip_ctrl_t * const p_ctrl, rsip_kdf_hmac_handle_t * const p_handle) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_handle); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_KDF_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_ret_t rsip_ret; + switch (p_instance_ctrl->handle.kdf_hmac.handle_state) + { + /* If the state is update, call suspension function */ + case RSIP_USER_HANDLE_STATE_UPDATE: + { + /* Read internal state */ + rsip_ret = r_rsip_kdf_hmac_suspend(&p_instance_ctrl->handle.kdf_hmac); + + /* Handle state transition */ + p_instance_ctrl->handle.kdf_hmac.handle_state = RSIP_USER_HANDLE_STATE_RESUME; + break; + } + + default: + { + rsip_ret = RSIP_RET_PASS; + } + } + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* Copy handle */ + *p_handle = p_instance_ctrl->handle.kdf_hmac; + + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return err; +} + +/*******************************************************************************************************************//** + * Resumes HMAC operation suspended by R_RSIP_KDF_HMAC_Suspend(). + * + * Implements @ref rsip_api_t::kdfHmacResume. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state | + * |------------|--------------| + * |FSP_SUCCESS |STATE_KDF_HMAC| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_HMAC_Resume (rsip_ctrl_t * const p_ctrl, rsip_kdf_hmac_handle_t const * const p_handle) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_handle); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Copy handle */ + p_instance_ctrl->handle.kdf_hmac = *p_handle; + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_KDF_HMAC; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Concatenates two wrapped derived keying materials (DKMs). + * + * DKM1 || DKM2 is output to p_wrapped_dkm1. + * + * Implements @ref rsip_api_t::kdfDkmConcatenate. + * + * @par State transition + * This API can be executed in **any state** including STATE_INITIAL, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_DKMConcatenate (rsip_wrapped_dkm_t * const p_wrapped_dkm1, + rsip_wrapped_dkm_t const * const p_wrapped_dkm2, + uint32_t const wrapped_dkm1_buffer_length) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_wrapped_dkm1); + FSP_ASSERT(p_wrapped_dkm2); + + /* Check mac type */ + FSP_ERROR_RETURN(RSIP_PRV_DKM_ALG_INVALID != p_wrapped_dkm1->alg, FSP_ERR_CRYPTO_RSIP_FAIL); + FSP_ERROR_RETURN(p_wrapped_dkm1->alg == p_wrapped_dkm2->alg, FSP_ERR_CRYPTO_RSIP_FAIL); + FSP_ERROR_RETURN(p_wrapped_dkm1->subtype == p_wrapped_dkm2->subtype, FSP_ERR_CRYPTO_RSIP_FAIL); +#endif + + uint32_t len1 = p_wrapped_dkm1->block_length * p_wrapped_dkm1->blocks; + uint32_t len2 = p_wrapped_dkm2->block_length * p_wrapped_dkm2->blocks; + + /* Check length */ + FSP_ERROR_RETURN(wrapped_dkm1_buffer_length >= (sizeof(rsip_wrapped_dkm_t) + len1 + len2), FSP_ERR_INVALID_SIZE); + + /* Copy DKM */ + memcpy(p_wrapped_dkm1->value + len1, p_wrapped_dkm2->value, len2); + p_wrapped_dkm1->blocks += p_wrapped_dkm2->blocks; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Outputs a wrapped key from KDF output. + * + * Implements @ref rsip_api_t::kdfDerivedKeyImport. + * + * @par Conditions + * @parblock + * Argument p_wrapped_dkm must be input the result of R_RSIP_KDF_SHA_Finish(), R_RSIP_KDF_HMAC_SignFinish() + * or R_RSIP_KDF_DKMConcatenate(). + * Argument key_type must be one of the following: + * - @ref RSIP_KEY_TYPE_AES_128 + * - @ref RSIP_KEY_TYPE_AES_256 + * - @ref RSIP_KEY_TYPE_HMAC_SHA256 + * - @ref RSIP_KEY_TYPE_HMAC_SHA384 + * - @ref RSIP_KEY_TYPE_HMAC_SHA512 + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_DerivedKeyImport (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_dkm_t const * const p_wrapped_dkm, + uint32_t const position, + rsip_wrapped_key_t * const p_wrapped_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ASSERT(p_wrapped_dkm); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Set function */ + rsip_func_kdf_derived_key_import_t p_func = select_func_derived_key_import(p_wrapped_dkm->alg, + p_wrapped_dkm->subtype, + p_wrapped_key->type); + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + + /* Check configuration */ + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t blocks[1] = {bswap_32big(p_wrapped_dkm->blocks)}; + uint32_t pos[1] = {bswap_32big(position)}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func((const uint32_t *) p_wrapped_dkm->value, blocks, pos, (uint32_t *) p_wrapped_key->p_value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Outputs a initial vector from KDF output. + * + * Implements @ref rsip_api_t::kdfDerivedIvWrap + * + * @par Conditions + * @parblock + * Argument p_wrapped_dkm must be input the result of R_RSIP_KDF_SHA_Finish(), R_RSIP_KDF_HMAC_SignFinish() + * or R_RSIP_KDF_DKMConcatenate(). + * + * Argument initial_vector_type must be one of the following: + * - @ref RSIP_INITIAL_VECTOR_TYPE_AES_16_BYTE + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_KDF_DerivedIVWrap (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_dkm_t const * const p_wrapped_dkm, + rsip_initial_vector_type_t const initial_vector_type, + uint32_t const position, + uint8_t const * const p_tls_sequence_num, + uint8_t * const p_wrapped_initial_vector) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_tls_sequence_num || (RSIP_INITIAL_VECTOR_TYPE_AES_16_BYTE == initial_vector_type)); + FSP_ASSERT(p_wrapped_initial_vector); + FSP_ASSERT(p_wrapped_dkm); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Check mac type */ + FSP_ERROR_RETURN((RSIP_PRV_DKM_ALG_SHA == p_wrapped_dkm->alg) || (RSIP_PRV_DKM_ALG_HMAC == p_wrapped_dkm->alg), + FSP_ERR_CRYPTO_RSIP_FAIL); +#endif + + /* Set function */ + rsip_func_kdf_derived_iv_wrap_t p_func = select_func_derived_iv_wrap(p_wrapped_dkm->alg, + p_wrapped_dkm->subtype, + initial_vector_type); + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + + /* Check configuration */ + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t blocks[1] = {bswap_32big(p_wrapped_dkm->blocks)}; + uint32_t pos[1] = {bswap_32big(position)}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func((const uint32_t *) p_wrapped_dkm->value, + blocks, + pos, + (const uint32_t *) p_tls_sequence_num, + (uint32_t *) p_wrapped_initial_vector); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t kdf_sha_update (rsip_ctrl_t * const p_ctrl, const uint8_t * p_message, uint32_t message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_kdf_sha_handle_t * p_handle = &p_instance_ctrl->handle.kdf_sha; + + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = r_rsip_kdf_sha_init_update(p_handle, + p_message, + message_length - p_handle->buffered_length1 - + p_handle->actual_wrapped_msg_length); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = r_rsip_kdf_sha_resume_update(p_handle, p_message, message_length); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_kdf_sha_update(p_handle, p_message, message_length); + } + } + + /* Check error */ + switch (ret) + { + case RSIP_RET_PASS: + { + /* State transition */ + p_handle->handle_state = RSIP_USER_HANDLE_STATE_UPDATE; + break; + } + + default: + { + /* State transition (abort) */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Finalizes a SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t kdf_sha_finish (rsip_ctrl_t * const p_ctrl, uint8_t * p_digest) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_kdf_sha_handle_t * p_handle = &p_instance_ctrl->handle.kdf_sha; + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = r_rsip_kdf_sha_init_final(p_handle, p_digest); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = r_rsip_kdf_sha_resume_final(p_handle, p_digest); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_kdf_sha_final(p_handle, p_digest); + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return ret; +} + +/*******************************************************************************************************************//** + * Select primitive function of key import from DKM and key type. + * + * @param[in] dkm_alg DKM alg. + * @param[in] dkm_subtype DKM subtype. + * @param[in] key_type Key type. + * + * @return Pointer to function. + ***********************************************************************************************************************/ +static rsip_func_kdf_derived_key_import_t select_func_derived_key_import (uint8_t dkm_alg, + uint8_t dkm_subtype, + rsip_key_type_t key_type) +{ + rsip_func_kdf_derived_key_import_t ret = NULL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(key_type); // Parse key type + + switch (dkm_alg) + { + case RSIP_PRV_DKM_ALG_SHA: + { + switch (key_type_ext.alg) + { + case RSIP_PRV_ALG_AES: + { + ret = gp_func_kdf_sha_derived_key_import_aes[dkm_subtype][key_type_ext.subtype]; + break; + } + + default: + { + /* Do nothing */ + } + } + + break; + } + + case RSIP_PRV_DKM_ALG_HMAC: + { + switch (key_type_ext.alg) + { + case RSIP_PRV_ALG_AES: + { + ret = gp_func_kdf_hmac_derived_key_import_aes[dkm_subtype][key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_HMAC: + { + ret = gp_func_kdf_hmac_derived_key_import_hmac[dkm_subtype][key_type_ext.subtype]; + break; + } + + default: + { + /* Do nothing */ + } + } + + break; + } + + default: + { + /* Do nothing */ + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Select primitive function of IV wrap from DKM and IV type. + * + * @param[in] dkm_alg DKM alg. + * @param[in] dkm_subtype DKM subtype. + * @param[in] iv_type IV type. + * + * @return Pointer to function. + ***********************************************************************************************************************/ +static rsip_func_kdf_derived_iv_wrap_t select_func_derived_iv_wrap (uint8_t dkm_alg, + uint8_t dkm_subtype, + rsip_initial_vector_type_t iv_type) +{ + rsip_func_kdf_derived_iv_wrap_t ret = NULL; + + switch (dkm_alg) + { + case RSIP_PRV_DKM_ALG_SHA: + { + ret = gp_func_kdf_sha_derived_iv_wrap[dkm_subtype][iv_type]; + break; + } + + case RSIP_PRV_DKM_ALG_HMAC: + { + ret = gp_func_kdf_hmac_derived_iv_wrap[dkm_subtype][iv_type]; + break; + } + + default: + { + /* Do nothing */ + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t kdf_hmac_update (rsip_ctrl_t * const p_ctrl, const uint8_t * p_message, uint32_t message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_kdf_hmac_handle_t * p_handle = &p_instance_ctrl->handle.kdf_hmac; + + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = + r_rsip_kdf_hmac_init_update(p_handle, p_message, message_length - p_handle->actual_wrapped_msg_length); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = r_rsip_kdf_hmac_resume_update(p_handle, p_message, message_length); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_kdf_hmac_update(p_handle, p_message, message_length); + } + } + + /* Check error */ + switch (ret) + { + case RSIP_RET_PASS: + { + /* State transition */ + p_handle->handle_state = RSIP_USER_HANDLE_STATE_UPDATE; + break; + } + + default: + { + /* State transition (abort) */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Finalizes a HMAC generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t kdf_hmac_sign_finish (rsip_ctrl_t * const p_ctrl, uint8_t * p_mac) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_kdf_hmac_handle_t * p_handle = &p_instance_ctrl->handle.kdf_hmac; + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = + r_rsip_kdf_hmac_init_final(p_handle, p_mac); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = r_rsip_kdf_hmac_resume_final(p_handle, p_mac); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_kdf_hmac_final(p_handle, p_mac); + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return ret; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_otf.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_otf.c new file mode 100644 index 0000000000..95e61287cf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_otf.c @@ -0,0 +1,130 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize on-the-fly decryption on RSIP. + * Implements @ref rsip_api_t::otfInit. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled or selected channel is invalid. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms" + * + * @attention This function is only part of on-the-fly decryption activation process and intended to be called from + * a higher level FSP module. Even if a user calls this function directly, the feature will not be enabled. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_OTF_Init (rsip_ctrl_t * const p_ctrl, + rsip_otf_channel_t const channel, + rsip_wrapped_key_t * const p_wrapped_key, + uint8_t const * const p_seed) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ASSERT(p_seed); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + rsip_func_otf_t p_func = gp_func_otf[channel][key_type_ext.subtype]; // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_AES == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) p_wrapped_key->p_value, (const uint32_t *) p_seed); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_pki.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_pki.c new file mode 100644 index 0000000000..e290c9e75e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_pki.c @@ -0,0 +1,262 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static rsip_func_pki_cert_key_import_t select_func_cert_key_import(rsip_key_type_t key_type); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Exports verified certificate information stored in this driver. + * + * The certificate is last called function R_RSIP_PKI_ECDSA_CertVerify(), R_RSIP_PKI_RSASSA_PKCS1_V1_5_CertVerify(), + * R_RSIP_PKI_RSASSA_PSS_CertVerify(), or R_RSIP_PKI_VerifiedCertInfoImport(). + * + * Implements @ref rsip_api_t::pkiVerifiedCertInfoExport. + * + * @par State transition + * This API can be executed in **any state** including STATE_INITIAL, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PKI_VerifiedCertInfoExport (rsip_ctrl_t * const p_ctrl, + rsip_verified_cert_info_t * const p_verified_cert_info) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_verified_cert_info); +#endif + + memcpy(p_verified_cert_info, &p_instance_ctrl->pki_verified_cert_info, sizeof(rsip_verified_cert_info_t)); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Imports verified certificate information. + * + * Implements @ref rsip_api_t::pkiVerifiedCertInfoImport. + * + * @par State transition + * This API can be executed in **any state** including STATE_INITIAL, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PKI_VerifiedCertInfoImport (rsip_ctrl_t * const p_ctrl, + rsip_verified_cert_info_t const * const p_verified_cert_info) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_verified_cert_info); +#endif + + memcpy(&p_instance_ctrl->pki_verified_cert_info, p_verified_cert_info, sizeof(rsip_verified_cert_info_t)); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Wraps the public key in the verified public key certificate. + * + * Implements @ref rsip_api_t::pkiCertKeyImport. + * + * @par Conditions + * @parblock + * Argument key_type must be one of the following: + * - @ref RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PUBLIC + * - @ref RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PUBLIC + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @note + * - Argument p_cert must correspond to the signature of the last called function R_RSIP_PKI_ECDSA_CertVerify(), + * R_RSIP_PKI_RSASSA_PKCS1_V1_5_CertVerify(), or R_RSIP_PKI_RSASSA_PSS_CertVerify(). + * - For arguments p_key_param1 and p_key_param2, specify an address inside the certificate. + * Addresses outside the certificate are invalid. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms" + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PKI_CertKeyImport (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_cert, + uint32_t const cert_length, + uint8_t const * const p_key_param1, + uint32_t const key_param1_length, + uint8_t const * const p_key_param2, + uint32_t const key_param2_length, + rsip_hash_type_t const hash_function, + rsip_wrapped_key_t * const p_wrapped_public_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_cert); + FSP_ASSERT(p_key_param1); + FSP_ASSERT(p_key_param2); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_func_pki_cert_key_import_t p_func = select_func_cert_key_import(p_wrapped_public_key->type); // Set function + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t certificate_length[1] = + { + bswap_32big(cert_length) + }; + + uint32_t certificate_pubkey[4] = + { + bswap_32big((uint32_t) ((uintptr_t) p_key_param1 - (uintptr_t) p_cert)), // Start position of param1 + bswap_32big((uint32_t) ((uintptr_t) p_key_param1 - (uintptr_t) p_cert + key_param1_length - 1)), // End position of param1 + bswap_32big((uint32_t) ((uintptr_t) p_key_param2 - (uintptr_t) p_cert)), // Start position of param2 + bswap_32big((uint32_t) ((uintptr_t) p_key_param2 - (uintptr_t) p_cert + key_param2_length - 1)), // End position of param2 + }; + + uint32_t hash_type[1] = + { + bswap_32big(g_pki_hash_type[hash_function]) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func(hash_type, + (uint32_t const *) p_cert, + certificate_length, + (uint32_t const *) certificate_pubkey, + (uint32_t *) &p_instance_ctrl->pki_verified_cert_info, + (uint32_t *) p_wrapped_public_key->p_value); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get parameter length from key type. + * + * @param[in] key_type Key type. + ***********************************************************************************************************************/ +static rsip_func_pki_cert_key_import_t select_func_cert_key_import (rsip_key_type_t key_type) +{ + rsip_func_pki_cert_key_import_t ret = NULL; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(key_type); + + switch (key_type_ext.alg) + { + case RSIP_PRV_ALG_ECC_PUBLIC: + { + ret = gp_func_pki_cert_key_import_ecc[key_type_ext.subtype]; + break; + } + + case RSIP_PRV_ALG_RSA_PUBLIC: + { + ret = gp_func_pki_cert_key_import_rsa[key_type_ext.subtype]; + break; + } + + default: + { + /* Do nothing */ + } + } + + return ret; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_public.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_public.h new file mode 100644 index 0000000000..7b7601a7be --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_public.h @@ -0,0 +1,106 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_COMMON_H +#define R_RSIP_COMMON_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip.h" +#include "r_rsip_private.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "RSIP" in ASCII, used to determine if channel is open. */ +#define RSIP_OPEN (0x52534950U) + +/* Various lengths */ + +/* RSIP_PRV_BYTE_SIZE_AES_BLOCK is defined in r_rsip.h */ + +/* ECC */ +#define RSIP_PRV_BYTE_SIZE_ECC_256_PARAM (32U) +#define RSIP_PRV_BYTE_SIZE_ECC_384_PARAM (48U) +#define RSIP_PRV_BYTE_SIZE_ECC_512_PARAM (64U) +#define RSIP_PRV_BYTE_SIZE_ECC_521_PARAM (66U) + +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_256_QX (0U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_256_QY (32U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_384_QX (0U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_384_QY (48U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_512_QX (0U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_512_QY (64U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_521_QX (14U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_521_QY (94U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_ECC_EDWARDS25519_Q (0U) + +/* RSA */ +#define RSIP_PRV_BYTE_SIZE_RSA_1024_N (128U) +#define RSIP_PRV_BYTE_SIZE_RSA_2048_N (256U) +#define RSIP_PRV_BYTE_SIZE_RSA_3072_N (384U) +#define RSIP_PRV_BYTE_SIZE_RSA_4096_N (512U) +#define RSIP_PRV_BYTE_SIZE_RSA_E (4U) + +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_N (0U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_1024_E (128U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_2048_E (256U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_3072_E (384U) +#define RSIP_PRV_BYTE_POS_WRAPPED_PUBLIC_KEY_RSA_4096_E (512U) + +/* SHA */ +#define RSIP_PRV_BYTE_SIZE_DIGEST_SHA1 (20U) +#define RSIP_PRV_BYTE_SIZE_DIGEST_SHA224 (28U) +#define RSIP_PRV_BYTE_SIZE_DIGEST_SHA256 (32U) +#define RSIP_PRV_BYTE_SIZE_DIGEST_SHA384 (48U) +#define RSIP_PRV_BYTE_SIZE_DIGEST_SHA512 (64U) +#define RSIP_PRV_BYTE_SIZE_DIGEST_SHA512_224 (28U) +#define RSIP_PRV_BYTE_SIZE_DIGEST_SHA512_256 (32U) + +#define RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA1_SHA224_SHA256 (64U) +#define RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA384_SHA512 (128U) +#define RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA3_224 (144U) +#define RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA3_256 (136U) +#define RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA3_384 (104U) +#define RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA3_512 (72U) + +/* RNG */ +#define RSIP_PRV_BYTE_SIZE_RNG (16U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +/* r_rsip.c */ +fsp_err_t r_rsip_random_number_generate(rsip_ctrl_t * const p_ctrl, uint8_t * const p_random); + +/* r_rsip_sha.c */ +fsp_err_t r_rsip_sha_init(rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type); +fsp_err_t r_rsip_sha_update(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, uint32_t const message_length); +fsp_err_t r_rsip_sha_finish(rsip_ctrl_t * const p_ctrl, uint8_t * const p_digest); + +/*******************************************************************************************************************//** + * Resets handle. + * + * @param[in] handle Pointer to handle. + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE void r_rsip_handle_reset (rsip_handle_t * handle) +{ + memset(handle, 0, sizeof(rsip_handle_t)); +} + +#endif /* R_RSIP_COMMON_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_rsa.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_rsa.c new file mode 100644 index 0000000000..645a038cb6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_rsa.c @@ -0,0 +1,2625 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Buffer size of EM */ +#if RSIP_CFG_RSA_4096_ENABLE + #define RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER (RSIP_PRV_BYTE_SIZE_RSA_4096_N) +#elif RSIP_CFG_RSA_3072_ENABLE + #define RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER (RSIP_PRV_BYTE_SIZE_RSA_3072_N) +#elif RSIP_CFG_RSA_2048_ENABLE + #define RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER (RSIP_PRV_BYTE_SIZE_RSA_2048_N) +#else + #define RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER (RSIP_PRV_BYTE_SIZE_RSA_1024_N) +#endif + +/* Buffer size of hash function */ +#if RSIP_CFG_SHA512_ENABLE + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA512) +#elif RSIP_CFG_SHA384_ENABLE + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA384) +#elif RSIP_CFG_SHA256_ENABLE || RSIP_CFG_SHA512_256_ENABLE + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA256) +#elif RSIP_CFG_SHA224_ENABLE || RSIP_CFG_SHA512_224_ENABLE + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA224) +#else + #define RSIP_PRV_BYTE_SIZE_HASH_BUFFER (RSIP_PRV_BYTE_SIZE_DIGEST_SHA1) +#endif + +/* PS (padding string) of EMSA-PKCS1-v1_5 */ +#define RSIP_PRV_EMSA_PKCS1_V1_5_PS (0xFF) + +/* Mask for EMSA-PSS */ +#define RSIP_PRV_EMSA_PSS_MASK (0xFF) + +/* Trailer field of EMSA-PSS (constant) */ +#define RSIP_PRV_EMSA_PSS_TRAILER_FIELD (0xBC) + +/* Command */ +#define RSIP_PRV_PKI_SIGNATURE_TYPE_PKCS1_V1_5 (0U) +#define RSIP_PRV_PKI_SIGNATURE_TYPE_PSS (1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static fsp_err_t r_rsip_rsa_encrypt(rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, + uint8_t * const p_cipher); +static fsp_err_t r_rsip_rsa_decrypt(rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_cipher, + uint8_t * const p_plain); +static fsp_err_t eme_pkcs1_v1_5_ps_generate(rsip_ctrl_t * const p_ctrl, uint8_t * p_ps, uint32_t ps_length); +static fsp_err_t emsa_pkcs1_v1_5_encode(rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t * const p_em, + uint32_t const em_length); +static fsp_err_t emsa_pss_encode(rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_mhash, + uint8_t * const p_em, + uint32_t const em_bit_length); +static fsp_err_t emsa_pss_verify(rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_mhash, + uint8_t * const p_em, + uint32_t const em_bit_length); +static fsp_err_t emsa_pss_h_generate(rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_function, + uint8_t const * const p_mhash, + uint32_t const hlen, + uint8_t const * const p_salt, + uint32_t const slen, + uint8_t * const p_h); +static fsp_err_t emsa_pss_salt_generate(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_salt, + uint32_t const salt_length); +static fsp_err_t emsa_pss_ps_check(uint8_t const * const p_db, + uint32_t const dblen, + uint8_t const ** const pp_salt, + uint32_t * const p_slen, + bool const salt_auto_detection); +static fsp_err_t mgf1_mask(rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_function, + uint8_t const * const p_mgf_seed, + uint32_t const mgf_seed_len, + uint8_t * const p_mask, + uint32_t const mask_len); +static uint32_t secure_memcmp(const void * buf1, const void * buf2, uint32_t num); +static void * memxor(void * buf1, void * buf2, uint32_t num); +RSIP_PRV_STATIC_INLINE void buffer_clear(void * p_buf, const uint32_t num); + +static fsp_err_t pki_rsa_encrypt(rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, + uint8_t * const p_cipher); +static fsp_err_t pki_rsassa_pkcs1_v1_5_info_output(rsip_instance_ctrl_t * p_instance_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t const * const p_signature); +static fsp_err_t pki_rsassa_pss_info_output(rsip_instance_ctrl_t * p_instance_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t const * const p_signature, + uint8_t const * const p_salt, + uint32_t const slen); +static void pki_rsassa_pss_salt_get(uint8_t const * const p_em, + uint32_t const emlen, + uint32_t const hlen, + uint8_t * const p_salt, + uintptr_t * const p_slen); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static const uint32_t gs_hash_length[] = +{ + [RSIP_HASH_TYPE_SHA1] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA1, + [RSIP_HASH_TYPE_SHA224] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA224, + [RSIP_HASH_TYPE_SHA256] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA256, + [RSIP_HASH_TYPE_SHA384] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA384, + [RSIP_HASH_TYPE_SHA512] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA512, + [RSIP_HASH_TYPE_SHA512_224] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA224, + [RSIP_HASH_TYPE_SHA512_256] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA256 +}; + +static const uint32_t gs_key_length[RSIP_PRV_KEY_SUBTYPE_RSA_NUM] = +{ + [RSIP_PRV_KEY_SUBTYPE_RSA_1024] = RSIP_PRV_BYTE_SIZE_RSA_1024_N, + [RSIP_PRV_KEY_SUBTYPE_RSA_2048] = RSIP_PRV_BYTE_SIZE_RSA_2048_N, + [RSIP_PRV_KEY_SUBTYPE_RSA_3072] = RSIP_PRV_BYTE_SIZE_RSA_3072_N, + [RSIP_PRV_KEY_SUBTYPE_RSA_4096] = RSIP_PRV_BYTE_SIZE_RSA_4096_N, +}; + +/* Because the buffer sizes are large, allocate memory in the static area instead of the stack area. */ +static uint8_t em_buffer[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER]; +static uint8_t em_buffer2[RSIP_PRV_BYTE_SIZE_RSA_EM_BUFFER]; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Encrypts plaintext with raw RSA. + * + * Implements @ref rsip_api_t::rsaEncrypt. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @note This API provides RSA low-level primitives (RSAEP/RSAVP1). + * It should be used in conjunction with any padding scheme. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSA_Encrypt (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, + uint8_t * const p_cipher) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_plain); + FSP_ASSERT(p_cipher); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_rsa_t p_func = gp_func_rsa_public[key_type_ext.subtype]; // Set function + + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + return r_rsip_rsa_encrypt(p_wrapped_public_key, p_plain, p_cipher); +} + +/*******************************************************************************************************************//** + * Decrypts ciphertext with raw RSA. + * + * Implements @ref rsip_api_t::rsaDecrypt. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @note This API provides RSA low-level primitives (RSADP/RSASP1). + * It should be used in conjunction with any padding scheme. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSA_Decrypt (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_cipher, + uint8_t * const p_plain) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_cipher); + FSP_ASSERT(p_plain); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + rsip_func_rsa_t p_func = gp_func_rsa_private[key_type_ext.subtype]; // Set function + + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PRIVATE == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + return r_rsip_rsa_decrypt(p_wrapped_private_key, p_cipher, p_plain); +} + +/*******************************************************************************************************************//** + * Encrypts plaintext with RSAES-PKCS1-v1_5. + * + * Implements @ref rsip_api_t::rsaesPkcs1V15Encrypt. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * + * mLen (plain_length) and k (modulus length) must meet the following condition. + * - mLen <= k - 11 + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Encrypt (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, + uint32_t const plain_length, + uint8_t * const p_cipher) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_plain); + FSP_ASSERT(p_cipher); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_rsa_t p_func = gp_func_rsa_public[key_type_ext.subtype]; // Set function + + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name on RFC8017 is "k" + uint32_t mlen = plain_length; + + /* Check length */ + FSP_ERROR_RETURN(mlen <= (klen - 11), FSP_ERR_INVALID_SIZE); + + uint8_t * p_em = &p_cipher[0]; + + /* + * EME-PKCS1-v1_5 encoding + * EM = 0x00 || 0x02 || PS || 0x00 || M + * + * cipher = EM + */ + p_em[0] = 0x00; + p_em[1] = 0x02; + fsp_err_t err = eme_pkcs1_v1_5_ps_generate(p_ctrl, &p_em[2], klen - mlen - 3); + p_em[klen - mlen - 1] = 0x00; + memcpy(&p_em[klen - mlen], p_plain, mlen); + + if (FSP_SUCCESS == err) + { + /* + * c = RSAEP ((n, e), m) + * + * cipher = c + */ + err = r_rsip_rsa_encrypt(p_wrapped_public_key, p_em, p_em); + } + + /* Clear plaintext if the operation fails */ + if (FSP_SUCCESS != err) + { + memset(p_em, 0, klen); + } + + return err; +} + +/*******************************************************************************************************************//** + * Decrypts with RSAES-PKCS1-v1_5. + * + * Implements @ref rsip_api_t::rsaesPkcs1V15Decrypt. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * + * plain_buffer_length must be greater than or equal to mLen(plaintext length). + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @note This API skips the ciphertext length checking at RFC8017 (PKCS#1 v2.2) Section 7.2.2 Step 1. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Decrypt (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_cipher, + uint8_t * const p_plain, + uint32_t * const p_plain_length, + uint32_t const plain_buffer_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_cipher); + FSP_ASSERT(p_plain); + FSP_ASSERT(p_plain_length); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_rsa_t p_func = gp_func_rsa_private[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PRIVATE == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name in RFC 8107 is "k" + uint32_t mlen = 0; + + /* + * Prepare EME-PKCS1-v1_5 decoding input + * EM = 0x00 || 0x02 || PS || 0x00 || M + * + * buffer = EM + */ + uint8_t * p_em = &em_buffer[0]; + + /* m = RSADP (K, c) */ + fsp_err_t err = r_rsip_rsa_decrypt(p_wrapped_private_key, p_cipher, p_em); + + /* + * Verification + * In accordance with PKCS #1 v2.2 7.2.2., error code and timing is unified. + */ + if (FSP_SUCCESS == err) + { + uint32_t ptr = 0; + volatile uint32_t error_detection = 0; + + /* Error: The first octet of EM does not have hexadecimal value 0x00 */ + error_detection |= p_em[ptr]; + ptr++; + + /* Error: The second octet of EM does not have hexadecimal value 0x02 */ + error_detection |= p_em[ptr] ^ 0x02; + ptr++; + + /* Error: The length of PS is less than 8 octets */ + for (uint32_t i = 0; i < 8; i++) + { + error_detection |= !p_em[ptr]; + ptr++; + } + + /* Error: There is no octet with hexadecimal value 0x00 to separate PS from M */ + uint32_t zero_detection = 0; + mlen = klen - ptr; + while (klen > ptr) + { + mlen -= !zero_detection; + + zero_detection |= !p_em[ptr]; + ptr++; + } + + error_detection |= !zero_detection; + + if (error_detection) + { + /* Wipe error_detection */ + error_detection = 0; + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + } + + /* Output the message M */ + if (FSP_SUCCESS == err) + { + *p_plain_length = mlen; + + /* Buffer length must be equal or grater than actual plaintext length */ + if (*p_plain_length > plain_buffer_length) + { + err = FSP_ERR_INVALID_SIZE; + } + else + { + memcpy(p_plain, &p_em[klen - mlen], mlen); + } + } + + /* Clear plaintext in buffer */ + buffer_clear(p_em, klen); + + return err; +} + +/*******************************************************************************************************************//** + * Encrypts plaintext with RSAES-OAEP. + * + * Implements @ref rsip_api_t::rsaesOaepEncrypt. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * + * mLen (plain_length), hLen (hash length of hash_function), and k (modulus length) + * must meet the following condition. + * - mLen <= k - 2 hLen - 2 + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Argument mask_generation_function accepts any member of enumeration @ref rsip_mgf_type_t. + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSAES_OAEP_Encrypt (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint8_t const * const p_label, + uint32_t const label_length, + uint8_t const * const p_plain, + uint32_t const plain_length, + uint8_t * const p_cipher) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_label || (0 == label_length)); + FSP_ASSERT(p_plain); + FSP_ASSERT(p_cipher); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_rsa_t p_func = gp_func_rsa_public[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name on RFC8017 is "k" + uint32_t hlen = gs_hash_length[hash_function]; + uint32_t mlen = plain_length; + uint32_t dblen = klen - hlen - 1; + + /* Check length */ + FSP_ERROR_RETURN((mlen + 2 * hlen + 2) <= klen, FSP_ERR_INVALID_SIZE); + + /* + * Prepare EME-OAEP encoding input + * 0x00 || seed || DB + * DB = lHash || PS || 0x01 || M + * + * cipher = 0x00 || seed || DB + */ + uint8_t * p_em = &p_cipher[0]; + uint8_t * p_seed = &p_em[1]; + uint8_t * p_db = &p_em[1 + hlen]; + uint8_t * p_lhash = &p_em[1 + hlen]; + uint8_t * p_sentinel = &p_em[klen - mlen - 1]; // Position of 0x01 + uint8_t * p_message = &p_em[klen - mlen]; + + /* Zero filling */ + memset(p_em, 0, klen); + + /* Generate seed (length: hlen) */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + + for (uint32_t i = 0; i * RSIP_PRV_BYTE_SIZE_RNG < hlen; i++) + { + uint8_t seed_buffer[RSIP_PRV_BYTE_SIZE_RNG]; + err = r_rsip_random_number_generate(p_ctrl, seed_buffer); + + if (FSP_SUCCESS == err) + { + memcpy(&p_seed[i * RSIP_PRV_BYTE_SIZE_RNG], + seed_buffer, + ((hlen / RSIP_PRV_BYTE_SIZE_RNG) > i) ? RSIP_PRV_BYTE_SIZE_RNG : (hlen % RSIP_PRV_BYTE_SIZE_RNG)); + } + } + + if (FSP_SUCCESS == err) + { + /* Generate lHash (length: hlen) */ + err = r_rsip_sha_init(p_ctrl, hash_function); + + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_update(p_ctrl, p_label, label_length); + + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_finish(p_ctrl, p_lhash); + } + } + + /* Insert 0x01 */ + *p_sentinel = 0x01; + + /* Copy message */ + memcpy(p_message, p_plain, mlen); + } + + /* + * EME-OAEP encoding + * EM = 0x00 || maskedSeed || maskedDB + * + * cipher = EM + */ + rsip_hash_type_t mgf1_hash = (rsip_hash_type_t) mask_generation_function; + + if (FSP_SUCCESS == err) + { + /* + * dbMask = MGF(seed, k - hLen - 1) + * maskedDB = DB \xor dbMask + */ + err = mgf1_mask(p_ctrl, mgf1_hash, p_seed, hlen, p_db, dblen); + } + + if (FSP_SUCCESS == err) + { + /* + * seedMask = MGF(maskedDB, hLen) + * maskedSeed = seed \xor seedMask + */ + err = mgf1_mask(p_ctrl, mgf1_hash, p_db, dblen, p_seed, hlen); + } + + if (FSP_SUCCESS == err) + { + /* + * c = RSAEP ((n, e), m) + * + * cipher = c + */ + err = r_rsip_rsa_encrypt(p_wrapped_public_key, p_em, p_cipher); + } + + /* Clear plaintext if the operation fails */ + if (FSP_SUCCESS != err) + { + memset(p_em, 0, klen); + } + + return err; +} + +/*******************************************************************************************************************//** + * Decrypts ciphertext with RSAES-OAEP. + * + * Implements @ref rsip_api_t::rsaesOaepDecrypt. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * + * hLen (hash length of hash_function) and k (modulus length) must meet the following condition. + * - k >= 2 hLen + 2 + * + * plain_buffer_length must be greater than or equal to mLen(plaintext length). + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Argument mask_generation_function accepts any member of enumeration @ref rsip_mgf_type_t. + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @note This API skips the ciphertext length checking at RFC8017 (PKCS#1 v2.2) Section 7.1.2 Step 1. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSAES_OAEP_Decrypt (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint8_t const * const p_label, + uint32_t const label_length, + uint8_t const * const p_cipher, + uint8_t * const p_plain, + uint32_t * const p_plain_length, + uint32_t const plain_buffer_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_label || (0 == label_length)); + FSP_ASSERT(p_cipher); + FSP_ASSERT(p_plain); + FSP_ASSERT(p_plain_length); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_rsa_t p_func = gp_func_rsa_private[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PRIVATE == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name in RFC 8107 is "k" + uint32_t hlen = gs_hash_length[hash_function]; + uint32_t mlen = 0; + uint32_t dblen = klen - hlen - 1; + + /* Check length */ + FSP_ERROR_RETURN(klen >= (2 * hlen + 2), FSP_ERR_INVALID_SIZE); + + /* + * Prepare EME-OAEP decoding input + * EM = Y || maskedSeed || maskedDB + * + * buffer = EM + */ + uint8_t hash_buffer[RSIP_PRV_BYTE_SIZE_HASH_BUFFER]; + uint8_t * p_em = &em_buffer[0]; + uint8_t * p_seed = &p_em[1]; + uint8_t * p_db = &p_em[1 + hlen]; + uint8_t * p_lhash = &p_em[1 + hlen]; + uint8_t * p_sentinel = NULL; // Position of 0x01 + uint8_t * p_message = NULL; + + /* m = RSADP (K, c) */ + fsp_err_t err = r_rsip_rsa_decrypt(p_wrapped_private_key, p_cipher, p_em); + + /* + * EME-OAEP decoding + * Y || seed || DB + * DB = lHash' || PS || 0x01 || M + * + * buffer = Y || seed || DB + */ + rsip_hash_type_t mgf1_hash = (rsip_hash_type_t) mask_generation_function; + + if (FSP_SUCCESS == err) + { + /* + * seedMask = MGF(maskedDB, hLen) + * seed = maskedSeed \xor seedMask + */ + err = mgf1_mask(p_ctrl, mgf1_hash, p_db, dblen, p_seed, hlen); + } + + if (FSP_SUCCESS == err) + { + /* + * dbMask = MGF(seed, k - hLen - 1) + * DB = maskedDB \xor dbMask + */ + err = mgf1_mask(p_ctrl, mgf1_hash, p_seed, hlen, p_db, dblen); + } + + if (FSP_SUCCESS == err) + { + /* Generate lHash' (output to p_mask) */ + err = r_rsip_sha_init(p_ctrl, hash_function); + + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_update(p_ctrl, p_label, label_length); + + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_finish(p_ctrl, hash_buffer); + } + } + } + + /* + * Verification + * In accordance with PKCS #1 v2.2 7.1.2., error code and timing is unified. + */ + if (FSP_SUCCESS == err) + { + volatile uint32_t error_detection = 0; + + /* Error: There is no octet with hexadecimal value 0x01 to separate PS from M */ + uint32_t nonzero_detection = 0; + mlen = klen - 2 * hlen - 2; // Maximum length + + for (uint32_t i = mlen; i > 0; i--) + { + nonzero_detection |= p_em[klen - i - 1]; + mlen -= !nonzero_detection; + } + + p_sentinel = &p_em[klen - mlen - 1]; + p_message = &p_em[klen - mlen]; + error_detection |= *p_sentinel ^ 0x01; + + /* Error: lHash does not equal lHash' */ + error_detection |= secure_memcmp(p_lhash, hash_buffer, hlen); + + /* Error: Y is nonzero */ + error_detection |= p_em[0]; + + if (error_detection) + { + /* Wipe error_detection */ + error_detection = 0; + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + } + + /* Output the message M */ + if (FSP_SUCCESS == err) + { + *p_plain_length = mlen; + + /* Buffer length must be equal or grater than actual plaintext length */ + if (*p_plain_length > plain_buffer_length) + { + err = FSP_ERR_INVALID_SIZE; + } + else + { + memcpy(p_plain, p_message, mlen); + } + } + + /* Clear buffer data */ + buffer_clear(p_em, klen); + buffer_clear(hash_buffer, hlen); + + return err; +} + +/*******************************************************************************************************************//** + * Signs message with RSASSA-PKCS1-v1_5. + * + * Implements @ref rsip_api_t::rsassaPkcs1V15Sign. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Message hash p_hash should be computed in advance with hash_function. + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Sign (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_rsa_t p_func = gp_func_rsa_private[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PRIVATE == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name in RFC 8107 is "k" + + /* + * EMSA-PKCS1-v1_5 encoding + * EM = EMSA-PKCS1-V1_5-ENCODE (M, k) + * + * signature = EM + */ + fsp_err_t err = emsa_pkcs1_v1_5_encode(hash_function, p_hash, p_signature, klen); + + /* + * s = RSASP1 (K, m) + * + * signature = s + */ + if (FSP_SUCCESS == err) + { + err = r_rsip_rsa_decrypt(p_wrapped_private_key, p_signature, p_signature); + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies signature with RSASSA-PKCS1-v1_5. + * + * Implements @ref rsip_api_t::rsassaPkcs1V15Verify. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Message hash p_hash should be computed in advance with hash_function. + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t const * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_rsa_t p_func = gp_func_rsa_public[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name in RFC 8107 is "k" + + /* + * s = OS2IP (S) + * m = RSAVP1 ((n, e), s) + * EM = I2OSP (m, k) + * + * em_buffer = EM + */ + fsp_err_t err = r_rsip_rsa_encrypt(p_wrapped_public_key, p_signature, em_buffer); + + if (FSP_SUCCESS == err) + { + /* + * EMSA-PKCS1-v1_5 encoding + * EM' = EMSA-PKCS1-V1_5-ENCODE (M, k) + * + * em_buffer2 = EM' + */ + err = emsa_pkcs1_v1_5_encode(hash_function, p_hash, em_buffer2, klen); + } + + if (FSP_SUCCESS == err) + { + /* Compare the encoded message EM and the second encoded message EM' */ + if (0 != memcmp(em_buffer, em_buffer2, klen)) + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Signs message with RSASSA-PSS. + * + * Implements @ref rsip_api_t::rsassaPssSign. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_private_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_3072_PRIVATE + * - @ref RSIP_KEY_TYPE_RSA_4096_PRIVATE + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Argument mask_generation_function accepts any member of enumeration @ref rsip_mgf_type_t. + * + * Message hash p_hash should be computed in advance with hash_function. + * + * Salt length salt_length must be one of the following: + * - Any member of enumeration @ref rsip_rsa_salt_length_t + * - @ref RSIP_RSA_SALT_LENGTH_AUTO + * - @ref RSIP_RSA_SALT_LENGTH_HASH + * - @ref RSIP_RSA_SALT_LENGTH_MAX + * - Integers that satisfies the formula: sLen <= emLen - hLen - 2 + * - sLen is salt_length + * - emLen is the same as modulus length + * - hLen is the hash length + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSASSA_PSS_Sign (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_hash, + uint8_t * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_private_key); + FSP_ASSERT(p_wrapped_private_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_rsa_t p_func = gp_func_rsa_private[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PRIVATE == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name in RFC 8107 is "k" + + fsp_err_t err = emsa_pss_encode(p_ctrl, + hash_function, + mask_generation_function, + salt_length, + p_hash, + p_signature, + klen * 8 - 1); + + /* + * s = RSASP1 (K, m) + * + * signature = s + */ + if (FSP_SUCCESS == err) + { + /* + * EMSA-PSS encoding + * EM = EMSA-PSS-ENCODE (M, modBits - 1) + * + * signature = EM + */ + err = r_rsip_rsa_decrypt(p_wrapped_private_key, p_signature, p_signature); + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies signature with RSASSA-PSS. + * Implements @ref rsip_api_t::rsassaPssVerify. + * + * @par Conditions + * @parblock + * Key type of p_wrapped_public_key must be one of the following: + * - @ref RSIP_KEY_TYPE_RSA_2048_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_3072_PUBLIC + * - @ref RSIP_KEY_TYPE_RSA_4096_PUBLIC + * + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * Argument mask_generation_function accepts any member of enumeration @ref rsip_mgf_type_t. + * + * Message hash p_hash should be computed in advance with hash_function. + * + * Salt length salt_length must be one of the following: + * - Any member of enumeration @ref rsip_rsa_salt_length_t + * - @ref RSIP_RSA_SALT_LENGTH_AUTO + * - @ref RSIP_RSA_SALT_LENGTH_HASH + * - @ref RSIP_RSA_SALT_LENGTH_MAX + * - Integers that satisfies the formula: sLen <= emLen - hLen - 2 + * - sLen is salt_length + * - emLen is the same as modulus length + * - hLen is the hash length + * @endparblock + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_RSASSA_PSS_Verify (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_hash, + uint8_t const * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_rsa_t p_func = gp_func_rsa_public[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func, FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name in RFC 8107 is "k" + + /* + * s = OS2IP (S) + * m = RSAVP1 ((n, e), s) + * EM = I2OSP (m, emLen) + * + * em_buffer = EM + */ + fsp_err_t err = r_rsip_rsa_encrypt(p_wrapped_public_key, p_signature, em_buffer); + + if (FSP_SUCCESS == err) + { + /* + * EMSA-PSS verification + * Result = EMSA-PSS-VERIFY (M, EM, modBits - 1) + */ + err = emsa_pss_verify(p_ctrl, + hash_function, + mask_generation_function, + salt_length, + p_hash, + em_buffer, + klen * 8 - 1); + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies a certificate with RSASSA-PKCS1-v1_5. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] hash_function Hash function in EMSA-PKCS1-v1_5. + * @param[in] p_hash Pointer to input hash. + * @param[in] p_signature Pointer to input signature. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PKI_RSASSA_PKCS1_V1_5_CertVerify (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t const * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_subset_pki_rsa_verify_t p_func = gp_func_pki_rsa_verify[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func.p_init, FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name in RFC 8107 is "k" + + /* + * s = OS2IP (S) + * m = RSAVP1 ((n, e), s) + * EM = I2OSP (m, k) + * + * em_buffer = EM + */ + fsp_err_t err = pki_rsa_encrypt(p_wrapped_public_key, p_signature, em_buffer); + + if (FSP_SUCCESS == err) + { + /* + * EMSA-PKCS1-v1_5 encoding + * EM' = EMSA-PKCS1-V1_5-ENCODE (M, k) + * + * em_buffer2 = EM' + */ + err = emsa_pkcs1_v1_5_encode(hash_function, p_hash, em_buffer2, klen); + } + + if (FSP_SUCCESS == err) + { + /* Compare the encoded message EM and the second encoded message EM' */ + if (0 != memcmp(em_buffer, em_buffer2, klen)) + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + } + + /* Output encrypted certificate info */ + if (FSP_SUCCESS == err) + { + err = pki_rsassa_pkcs1_v1_5_info_output(p_instance_ctrl, + p_wrapped_public_key, + hash_function, + p_hash, + p_signature); + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies a certificate with RSASSA-PSS. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] hash_function Hash function in EMSA-PSS-VERIFY. + * @param[in] mask_generation_function Mask generation function in EMSA-PSS-VERIFY. + * @param[in] salt_length Salt length. @ref RSIP_RSA_SALT_LENGTH_AUTO, @ref RSIP_RSA_SALT_LENGTH_HASH, + * @ref RSIP_RSA_SALT_LENGTH_MAX, 0, or positive integers can be set, + * where salt_length <= emLen - hLen - 2 (emLen is the same as the key length + * and hLen is the hash length). + * @param[in] p_hash Pointer to input hash. + * @param[in] p_signature Pointer to input signature. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_INVALID_SIZE Any length is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_PKI_RSASSA_PSS_CertVerify (rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_hash, + uint8_t const * const p_signature) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_public_key); + FSP_ASSERT(p_wrapped_public_key->p_value); + FSP_ASSERT(p_hash); + FSP_ASSERT(p_signature); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_func_subset_pki_rsa_verify_t p_func = gp_func_pki_rsa_verify[key_type_ext.subtype]; // Set function + FSP_ERROR_RETURN(RSIP_PRV_ALG_RSA_PUBLIC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(p_func.p_init, FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[hash_function], FSP_ERR_NOT_ENABLED); // Check configuration + FSP_ERROR_RETURN(g_sha_enabled[mask_generation_function], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + uint32_t klen = gs_key_length[key_type_ext.subtype]; // Actual name in RFC 8107 is "k" + + /* + * s = OS2IP (S) + * m = RSAVP1 ((n, e), s) + * EM = I2OSP (m, emLen) + * + * em_buffer = EM + */ + fsp_err_t err = pki_rsa_encrypt(p_wrapped_public_key, p_signature, em_buffer); + + if (FSP_SUCCESS == err) + { + /* + * EMSA-PSS verification + * Result = EMSA-PSS-VERIFY (M, EM, modBits - 1) + */ + err = emsa_pss_verify(p_ctrl, + hash_function, + mask_generation_function, + salt_length, + p_hash, + em_buffer, + klen * 8 - 1); + } + + /* Get salt and salt length */ + uintptr_t slen = 0; + pki_rsassa_pss_salt_get(em_buffer, klen, gs_hash_length[hash_function], em_buffer2, &slen); + + /* Output encrypted certificate info */ + if (FSP_SUCCESS == err) + { + err = pki_rsassa_pss_info_output(p_instance_ctrl, + p_wrapped_public_key, + hash_function, + p_hash, + p_signature, + em_buffer2, + (uint32_t) slen); + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Encrypts plaintext with raw RSA. + * + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] p_plain Pointer to plaintext. The length is as same as the key length. + * @param[out] p_cipher Pointer to destination of ciphertext. The length is as same as the key length. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t r_rsip_rsa_encrypt (rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, + uint8_t * const p_cipher) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_rsa_t p_func = gp_func_rsa_public[key_type_ext.subtype]; // Set function + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = p_func((const uint32_t *) + p_wrapped_public_key-> + p_value, + (const uint32_t *) p_plain, + (uint32_t *) p_cipher); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Decrypts ciphertext with raw RSA. + * + * @param[in] p_wrapped_private_key Pointer to wrapped key of RSA private key. + * @param[in] p_cipher Pointer to ciphertext. The length is as same as the key length. + * @param[out] p_plain Pointer to destination of plaintext. The length is as same as the key length. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t r_rsip_rsa_decrypt (rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_cipher, + uint8_t * const p_plain) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_private_key->type); // Parse key type + rsip_func_rsa_t p_func = gp_func_rsa_private[key_type_ext.subtype]; // Set function + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func((const uint32_t *) p_wrapped_private_key->p_value, (const uint32_t *) p_cipher, (uint32_t *) p_plain); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Generates PS (Padding String) for EME-PKCS1-v1_5 + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_ps Pointer to PS. + * @param[in] ps_length Length of PS. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + ***********************************************************************************************************************/ +static fsp_err_t eme_pkcs1_v1_5_ps_generate (rsip_ctrl_t * const p_ctrl, uint8_t * const p_ps, uint32_t const ps_length) +{ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + uint32_t rand_ptr = 0; + uint8_t rand_tmp[RSIP_PRV_BYTE_SIZE_RNG]; + + while (ps_length > rand_ptr) + { + err = r_rsip_random_number_generate(p_ctrl, rand_tmp); + if (FSP_SUCCESS != err) + { + break; + } + + for (uint32_t i = 0; i < RSIP_PRV_BYTE_SIZE_RNG; i++) + { + if (0 != rand_tmp[i]) + { + p_ps[rand_ptr] = rand_tmp[i]; + rand_ptr++; + } + + if (ps_length == rand_ptr) + { + break; + } + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Computes EMSA-PKCS1-v1_5-ENCODE. + * + * @param[in] hash_function Hash function in EMSA-PKCS1-v1_5. + * @param[in] p_hash Pointer to input hash. + * @param[out] p_em Pointer to destination of EM (Encoded Message). + * @param[in] em_length Length of EM. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_SIZE Key length is too short. + **********************************************************************************************************************/ +static fsp_err_t emsa_pkcs1_v1_5_encode (rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t * const p_em, + uint32_t const em_length) +{ + static const uint8_t digest_info_prefix[][19] = + { + [RSIP_HASH_TYPE_SHA1] = + { + 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14 + }, + [RSIP_HASH_TYPE_SHA224] = + { + 0x30, 0x2d, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x04, 0x05, + 0x00, 0x04, 0x1c + }, + [RSIP_HASH_TYPE_SHA256] = + { + 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, + 0x00, 0x04, 0x20 + }, + [RSIP_HASH_TYPE_SHA384] = + { + 0x30, 0x41, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05, + 0x00, 0x04, 0x30 + }, + [RSIP_HASH_TYPE_SHA512] = + { + 0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05, + 0x00, 0x04, 0x40 + }, + [RSIP_HASH_TYPE_SHA512_224] = + { + 0x30, 0x2d, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x05, 0x05, + 0x00, 0x04, 0x1c + }, + [RSIP_HASH_TYPE_SHA512_256] = + { + 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x06, 0x05, + 0x00, 0x04, 0x20 + }, + }; + static const uint32_t digest_info_prefix_len[] = + { + [RSIP_HASH_TYPE_SHA1] = 15, + [RSIP_HASH_TYPE_SHA224] = 19, + [RSIP_HASH_TYPE_SHA256] = 19, + [RSIP_HASH_TYPE_SHA384] = 19, + [RSIP_HASH_TYPE_SHA512] = 19, + [RSIP_HASH_TYPE_SHA512_224] = 19, + [RSIP_HASH_TYPE_SHA512_256] = 19 + }; + + uint8_t const * t_prefix = digest_info_prefix[hash_function]; + uint32_t t_prefix_len = digest_info_prefix_len[hash_function]; + uint32_t t_hash_len = gs_hash_length[hash_function]; + + /* Check length */ + FSP_ERROR_RETURN((t_prefix_len + t_hash_len + 11) <= em_length, FSP_ERR_INVALID_SIZE); + + /* Padding */ + p_em[0] = 0x00; + p_em[1] = 0x01; + memset(&p_em[2], RSIP_PRV_EMSA_PKCS1_V1_5_PS, em_length - t_prefix_len - t_hash_len - 3); + p_em[em_length - t_prefix_len - t_hash_len - 1] = 0x00; + + /* Copy the prefix of DER encoding T */ + memcpy(&p_em[em_length - t_prefix_len - t_hash_len], t_prefix, t_prefix_len); + + /* Copy hash */ + memcpy(&p_em[em_length - t_hash_len], p_hash, t_hash_len); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Computes EMSA-PSS-ENCODE. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] hash_function Hash function in EMSA-PSS-ENCODE. + * @param[in] mask_generation_function Mask generation function in EMSA-PSS-ENCODE. + * @param[in] salt_length Salt length. + * @param[in] p_mhash Pointer to mHash. + * @param[out] p_em Pointer to destination of EM (Encoded Message). + * @param[in] em_bit_length Bit length of EM. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_INVALID_SIZE Key length is too short. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t emsa_pss_encode (rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_mhash, + uint8_t * const p_em, + uint32_t const em_bit_length) +{ + uint32_t slen; + uint32_t hlen = gs_hash_length[hash_function]; + uint32_t emlen = (em_bit_length + 7) / 8; // round up + + /* Set salt length */ + uint32_t slen_max = emlen - hlen - 2; + switch (salt_length) + { + case RSIP_RSA_SALT_LENGTH_AUTO: + { + slen = (slen_max >= hlen) ? hlen : slen_max; + break; + } + + case RSIP_RSA_SALT_LENGTH_HASH: + { + slen = hlen; + break; + } + + case RSIP_RSA_SALT_LENGTH_MAX: + { + slen = slen_max; + break; + } + + default: + { + slen = salt_length; + } + } + + uint8_t * p_db = &p_em[0]; + uint8_t * p_salt = &p_em[emlen - slen - hlen - 1]; + uint8_t * p_hash = &p_em[emlen - hlen - 1]; + + /* Check length */ + FSP_ERROR_RETURN(emlen >= hlen + slen + 2, FSP_ERR_INVALID_SIZE); + + /* + * DB = PS ((0x)00 00 ...) || 0x01 || salt + * + * em = DB + */ + memset(p_db, 0x00, emlen - hlen - slen - 2); + p_em[emlen - hlen - slen - 2] = 0x01; + fsp_err_t err = emsa_pss_salt_generate(p_ctrl, p_salt, slen); + + if (FSP_SUCCESS == err) + { + /* + * mHash = Hash(M) + * M' = Padding1 ((0x)00 00 00 00 00 00 00 00) || mHash || salt + * H = Hash(M') + * Set trailer field (0xbc) + * + * em = DB || H || 0xbc + */ + err = emsa_pss_h_generate(p_ctrl, hash_function, p_mhash, hlen, p_salt, slen, p_hash); + p_em[emlen - 1] = RSIP_PRV_EMSA_PSS_TRAILER_FIELD; + } + + if (FSP_SUCCESS == err) + { + /* + * dbMask = MGF(H, emLen - hLen - 1) + * maskedDB = DB \xor dbMask + * + * em = maskedDB || H || 0xbc + */ + rsip_hash_type_t mgf1_hash = (rsip_hash_type_t) mask_generation_function; + err = mgf1_mask(p_ctrl, mgf1_hash, p_hash, hlen, p_db, emlen - hlen - 1); + } + + if (FSP_SUCCESS == err) + { + /* Set the leftmost 8emLen - emBits bits of the leftmost octet in maskedDB to zero */ + p_em[0] &= (uint8_t) (RSIP_PRV_EMSA_PSS_MASK >> (8 * emlen - em_bit_length)); + } + + return err; +} + +/*******************************************************************************************************************//** + * Computes EMSA-PSS-VERIFY. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] hash_function Hash function in EMSA-PSS-VERIFY. + * @param[in] mask_generation_function Mask generation function in EMSA-PSS-VERIFY. + * @param[in] salt_length Salt length. + * @param[in] p_mhash Pointer to mHash. + * @param[in,out] p_em Pointer to EM (Encoded Message). After execution, DB is unmasked. + * @param[in] em_bit_length Bit length of EM. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_INVALID_SIZE Key length is too short. + * + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Verification failed. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t emsa_pss_verify (rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_mhash, + uint8_t * const p_em, + uint32_t const em_bit_length) +{ + uint32_t slen = 0; + uint32_t hlen = gs_hash_length[hash_function]; + uint32_t emlen = (em_bit_length + 7) / 8; // round up + bool salt_auto_detection = false; + + /* Set salt length*/ + uint32_t slen_max = emlen - hlen - 2; + switch (salt_length) + { + case RSIP_RSA_SALT_LENGTH_AUTO: + { + salt_auto_detection = true; + break; + } + + case RSIP_RSA_SALT_LENGTH_HASH: + { + slen = hlen; + break; + } + + case RSIP_RSA_SALT_LENGTH_MAX: + { + slen = slen_max; + break; + } + + default: + { + slen = salt_length; + } + } + + uint8_t hash_buffer[RSIP_PRV_BYTE_SIZE_HASH_BUFFER]; + uint8_t * p_db = &p_em[0]; + uint8_t * p_salt = &p_em[emlen - slen - hlen - 1]; + uint8_t * p_hash = &p_em[emlen - hlen - 1]; + + /* Check length */ + FSP_ERROR_RETURN(emlen >= hlen + slen + 2, FSP_ERR_INVALID_SIZE); + + /* Error: the rightmost octet of EM does not have hexadecimal value 0xbc */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + + if (p_em[emlen - 1] != RSIP_PRV_EMSA_PSS_TRAILER_FIELD) + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + else + { + err = FSP_SUCCESS; + } + + /* the leftmost 8emLen - emBits bits of the leftmost octet in maskedDB are not all equal to zero */ + if (FSP_SUCCESS == err) + { + if (0x00 != (p_em[0] & ~(RSIP_PRV_EMSA_PSS_MASK >> (8 * emlen - em_bit_length)))) + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + } + + /* + * dbMask = MGF(H, emLen - hLen - 1) + * DB = maskedDB \xor dbMask + * + * em = DB || H || 0xbc + */ + if (FSP_SUCCESS == err) + { + rsip_hash_type_t mgf1_hash = (rsip_hash_type_t) mask_generation_function; + err = mgf1_mask(p_ctrl, mgf1_hash, p_hash, hlen, p_db, emlen - hlen - 1); + } + + if (FSP_SUCCESS == err) + { + /* Set the leftmost 8emLen - emBits bits of the leftmost octet in DB to zero */ + p_em[0] &= (uint8_t) (RSIP_PRV_EMSA_PSS_MASK >> (8 * emlen - em_bit_length)); + + /* + * Error: the emLen - hLen - sLen - 2 leftmost octets of DB are not zero or the octet at position + * emLen - hLen - sLen - 1 (the leftmost position is "position 1") does not have hexadecimal value 0x01 + */ + err = emsa_pss_ps_check(p_db, emlen - hlen - 1, (uint8_t const **) &p_salt, &slen, salt_auto_detection); + } + + /* + * mHash = Hash(M) + * M' = Padding1 ((0x)00 00 00 00 00 00 00 00) || mHash || salt + * H' = Hash(M') + * + * hash_buffer = H' + */ + if (FSP_SUCCESS == err) + { + err = emsa_pss_h_generate(p_ctrl, hash_function, p_mhash, hlen, p_salt, slen, hash_buffer); + } + + /* Compare H and H' */ + if (FSP_SUCCESS == err) + { + if (0 != memcmp(p_hash, hash_buffer, hlen)) + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Computes H or H' in EMSA-PSS. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] hash_function Hash function in EMSA-PSS. + * @param[in] p_mhash Pointer to mHash. + * @param[in] hlen hLen. + * @param[in] p_salt Pointer to salt. + * @param[in] slen sLen. + * @param[out] p_h Pointer to destination of H or H'. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t emsa_pss_h_generate (rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_function, + uint8_t const * const p_mhash, + uint32_t const hlen, + uint8_t const * const p_salt, + uint32_t const slen, + uint8_t * const p_h) +{ + /* "Padding1" in EMSA-PSS */ + static const uint8_t padding1[8] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + + fsp_err_t err = r_rsip_sha_init(p_ctrl, hash_function); + + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_update(p_ctrl, padding1, sizeof(padding1)); + + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_update(p_ctrl, p_mhash, hlen); + + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_update(p_ctrl, p_salt, slen); + + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_finish(p_ctrl, p_h); + } + } + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Generates salt for EMSA-PSS-ENCODE + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_salt Pointer to salt. + * @param[in] salt_length Length of salt. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + ***********************************************************************************************************************/ +static fsp_err_t emsa_pss_salt_generate (rsip_ctrl_t * const p_ctrl, uint8_t * const p_salt, uint32_t const salt_length) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t rand_ptr = 0; + uint8_t rand_tmp[RSIP_PRV_BYTE_SIZE_RNG]; + + for (uint32_t i = 0; i < salt_length / 16; i++) + { + err = r_rsip_random_number_generate(p_ctrl, &p_salt[rand_ptr]); + rand_ptr += 16; + } + + if (rand_ptr < salt_length) + { + err = r_rsip_random_number_generate(p_ctrl, rand_tmp); + memcpy(&p_salt[rand_ptr], rand_tmp, salt_length - rand_ptr); + } + + return err; +} + +/*******************************************************************************************************************//** + * Check PS for EMSA-PSS-VERIFY + * + * @param[in] p_db Pointer to DB (Data Block). + * @param[in] dblen DB length. + * @param[out] pp_salt Pointer to start address of salt. If salt_auto_detection is true, + * the address is updated in this function. + * @param[in,out] p_slen Pointer to salt length. If salt_auto_detection is true, + * detected salt length is output. Otherwise, the known salt length should be input. + * @param[in] salt_auto_detection If true, salt length is detected automatically. + * Otherwise, this function use input salt length. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL PS is invalid. + **********************************************************************************************************************/ +static fsp_err_t emsa_pss_ps_check (uint8_t const * const p_db, + uint32_t const dblen, + uint8_t const ** const pp_salt, + uint32_t * const p_slen, + bool const salt_auto_detection) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t ps_ptr = 0; + + if (salt_auto_detection) + { + /* Detect salt */ + while ((ps_ptr < dblen) && (0x00 == p_db[ps_ptr])) + { + ps_ptr++; + } + + if (0x01 != p_db[ps_ptr]) + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + else + { + *p_slen = dblen - ps_ptr - 1; + *pp_salt = &p_db[dblen - *p_slen]; + } + } + else + { + /* Verify sLen */ + for (ps_ptr = 0; ps_ptr < dblen - *p_slen - 1; ps_ptr++) + { + if (0x00 != p_db[ps_ptr]) + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + } + + if (0x01 != p_db[ps_ptr]) + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Computes MGF1 and outputs (input XOR MGF1). + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] hash_function Hash function used in MGF1. + * @param[in] p_mgf_seed Seed used in MGF1. + * @param[in] mgf_seed_len Length of seed. + * @param[in,out] p_mask Pointer to input data and destination of output data. + * @param[in] mask_len Length of mask. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + ***********************************************************************************************************************/ +static fsp_err_t mgf1_mask (rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_function, + uint8_t const * const p_mgf_seed, + uint32_t const mgf_seed_len, + uint8_t * const p_mask, + uint32_t const mask_len) +{ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + uint32_t hlen = gs_hash_length[hash_function]; + uint8_t buffer[RSIP_PRV_BYTE_SIZE_HASH_BUFFER]; + + for (uint32_t counter = 0; counter * hlen < mask_len; counter++) + { + /* Generate mask */ + err = r_rsip_sha_init(p_ctrl, hash_function); + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_update(p_ctrl, p_mgf_seed, mgf_seed_len); + if (FSP_SUCCESS == err) + { + uint32_t counter_big[1] = {bswap_32big(counter)}; + err = r_rsip_sha_update(p_ctrl, (uint8_t *) counter_big, 4); + if (FSP_SUCCESS == err) + { + err = r_rsip_sha_finish(p_ctrl, buffer); + } + } + } + + /* Output masked data */ + if (FSP_SUCCESS == err) + { + memxor(&p_mask[counter * hlen], buffer, ((mask_len / hlen) > counter) ? hlen : (mask_len % hlen)); + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Compares buf1 and buf2 while protecting against timing attack. + * + * @param[in] buf1 Pointer to buf1. + * @param[in] buf2 Pointer to buf2. + * @param[in] num Byte size of buf1 and buf2. + * + * @retval 0 buf1 and buf2 are equal. + * @retval 1 buf1 and buf2 are not equal. + **********************************************************************************************************************/ +static uint32_t secure_memcmp (const void * buf1, const void * buf2, uint32_t num) +{ + uint8_t * p_buf1 = (uint8_t *) buf1; + uint8_t * p_buf2 = (uint8_t *) buf2; + uint32_t tmp = 0; + + for (uint32_t i = 0; i < num; i++) + { + tmp |= p_buf1[i] ^ p_buf2[i]; + } + + return tmp > 0; +} + +/*******************************************************************************************************************//** + * Computes buf1 XOR buf2. + * + * @param[in,out] buf1 Pointer to buf1. buf1 XOR buf2 is output. + * @param[in] buf2 Pointer to buf2. + * @param[in] num Byte size of buf1 and buf2. + * + * @return Pointer to buf1. + **********************************************************************************************************************/ +static void * memxor (void * buf1, void * buf2, uint32_t num) +{ + uint8_t * p_buf1 = (uint8_t *) buf1; + uint8_t * p_buf2 = (uint8_t *) buf2; + + for (uint32_t i = 0; i < num; i++) + { + p_buf1[i] ^= p_buf2[i]; + } + + return buf1; +} + +/*******************************************************************************************************************//** + * Clears buffer. + * + * If memset_s is supported, it is guaranteed that this function will not be optimized. + * + * @param[in,out] p_buf Buffer data to be cleared. + * @param[in] num Buffer data size. + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE void buffer_clear (void * p_buf, const uint32_t num) +{ +#if __STDC_WANT_LIB_EXT1__ + memset_s(p_buf, num, 0, num); +#else + void * (* volatile p_memset)(void *, int, size_t) = memset; + p_memset(p_buf, 0, num); +#endif +} + +/*******************************************************************************************************************//** + * Encrypts plaintext with raw RSA. + * + * @param[in] p_wrapped_public_key Pointer to wrapped key of RSA public key. + * @param[in] p_plain Pointer to plaintext. The length is as same as the key length. + * @param[out] p_cipher Pointer to destination of ciphertext. The length is as same as the key length. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t pki_rsa_encrypt (rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, + uint8_t * const p_cipher) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_subset_pki_rsa_verify_t p_func = gp_func_pki_rsa_verify[key_type_ext.subtype]; // Set function + + rsip_verified_cert_info_t pki_enc_cert_info; + uint32_t cmd[1] = {bswap_32big(0U)}; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func.p_init((const uint32_t *) p_wrapped_public_key->p_value, + (const uint32_t *) p_plain, + (uint32_t *) p_cipher); + + if (RSIP_RET_PASS == rsip_ret) + { + /* Dummy call */ + p_func.p_final(cmd, cmd, (const uint32_t *) p_plain, NULL, NULL, (uint32_t *) &pki_enc_cert_info); + } + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies a certificate with RSASSA-PKCS1-v1_5. + * + * @param[in,out] p_instance_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped public key. + * @param[in] hash_function Hash function in EMSA-PKCS1-v1_5. + * @param[in] p_hash Pointer to input hash. + * @param[in] p_signature Pointer to input signature. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t pki_rsassa_pkcs1_v1_5_info_output (rsip_instance_ctrl_t * p_instance_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t const * const p_signature) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_subset_pki_rsa_verify_t p_func = gp_func_pki_rsa_verify[key_type_ext.subtype]; // Set function + + uint32_t signature_type[1] = + { + bswap_32big(RSIP_PRV_PKI_SIGNATURE_TYPE_PKCS1_V1_5) + }; + + uint32_t hash_type[1] = + { + bswap_32big(g_pki_hash_type[hash_function]) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func.p_init((const uint32_t *) p_wrapped_public_key->p_value, + (const uint32_t *) p_signature, + (uint32_t *) em_buffer); + + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = p_func.p_final(signature_type, + hash_type, + (const uint32_t *) p_hash, + NULL, + NULL, + (uint32_t *) &p_instance_ctrl->pki_verified_cert_info); + } + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies a certificate with RSASSA-PSS. + * + * @param[in,out] p_instance_ctrl Pointer to control block. + * @param[in] p_wrapped_public_key Pointer to wrapped public key. + * @param[in] hash_function Hash function in EMSA-PKCS1-v1_5. + * @param[in] p_hash Pointer to input hash. + * @param[in] p_signature Pointer to input signature. + * @param[in] p_salt Pointer to salt. + * @param[in] slen Salt length + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL Input parameter is invalid. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +static fsp_err_t pki_rsassa_pss_info_output (rsip_instance_ctrl_t * p_instance_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t const * const p_signature, + uint8_t const * const p_salt, + uint32_t const slen) +{ + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_public_key->type); // Parse key type + rsip_func_subset_pki_rsa_verify_t p_func = gp_func_pki_rsa_verify[key_type_ext.subtype]; // Set function + + uint32_t signature_type[1] = + { + bswap_32big(RSIP_PRV_PKI_SIGNATURE_TYPE_PSS) + }; + + uint32_t hash_type[1] = + { + bswap_32big(g_pki_hash_type[hash_function]) + }; + uint32_t salt_length[1] = + { + bswap_32big(slen) + }; + + /* Call function (cast to match the argument type with the primitive function) */ + rsip_ret_t rsip_ret = + p_func.p_init((const uint32_t *) p_wrapped_public_key->p_value, + (const uint32_t *) p_signature, + (uint32_t *) em_buffer); + + if (RSIP_RET_PASS == rsip_ret) + { + rsip_ret = p_func.p_final(signature_type, + hash_type, + (const uint32_t *) p_hash, + (const uint32_t *) p_salt, + salt_length, + (uint32_t *) &p_instance_ctrl->pki_verified_cert_info); + } + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Gets RSASSA-PSS salt. + * + * @param[in] p_em Pointer to unmasked encoded message (EM). + * @param[in] emlen EM length. + * @param[in] hlen Hash length. + * @param[out] p_salt Pointer to destination salt. + * @param[out] p_slen Pointer to destination of salt length. + **********************************************************************************************************************/ +static void pki_rsassa_pss_salt_get (uint8_t const * const p_em, + uint32_t const emlen, + uint32_t const hlen, + uint8_t * const p_salt, + uintptr_t * const p_slen) +{ + uint8_t const * p_ps_end = memchr(p_em, 0x01, emlen); + + if (NULL == p_ps_end) + { + /* Dummy position */ + p_ps_end = p_em; + } + + /* + * EM = PS ((0x)00 00 ...) || 0x01 || salt || H || 0xbc + */ + uintptr_t ps_len = (uintptr_t) p_ps_end - (uintptr_t) p_em + 1; + *p_slen = emlen - (hlen + 1) - ps_len; + + memcpy(p_salt, &p_em[ps_len], *p_slen); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_sha.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_sha.c new file mode 100644 index 0000000000..c05eb80e8d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/common/public/r_rsip_sha.c @@ -0,0 +1,1549 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static rsip_ret_t sha_update(rsip_ctrl_t * const p_ctrl, const uint8_t * p_message, uint32_t message_length); +static rsip_ret_t sha_finish(rsip_ctrl_t * const p_ctrl, uint8_t * p_digest); +static rsip_ret_t hmac_update(rsip_ctrl_t * const p_ctrl, const uint8_t * p_message, uint32_t message_length); +static rsip_ret_t hmac_sign_finish(rsip_ctrl_t * const p_ctrl, uint8_t * p_mac); +static rsip_ret_t hmac_verify_finish(rsip_ctrl_t * const p_ctrl, const uint8_t * p_mac, const uint32_t mac_length); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static const uint32_t gs_hmac_length[] = +{ + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA1, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA224, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA256, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA384] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA384, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA512, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_224] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA512_224, + [RSIP_PRV_KEY_SUBTYPE_HMAC_SHA512_256] = RSIP_PRV_BYTE_SIZE_DIGEST_SHA512_256, +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Generates SHA message digest. (Total input message must be less than 2^64 bits.) + * + * Implements @ref rsip_api_t::shaCompute. + * + * @par Conditions + * See R_RSIP_SHA_Init(). + * + * @par Output length + * See R_RSIP_SHA_Finish(). + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_SHA_Compute (rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_type, + uint8_t const * const p_message, + uint32_t const message_length, + uint8_t * const p_digest) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_message || (0 == message_length)); + FSP_ASSERT(p_digest); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Check configuration */ + FSP_ERROR_RETURN(g_sha_enabled[hash_type], FSP_ERR_NOT_ENABLED); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the function) */ + rsip_ret_t rsip_ret = r_rsip_sha_hash_init_final(hash_type, p_message, message_length, p_digest); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Starts SHA operation. + * + * Implements @ref rsip_api_t::shaInit. + * + * @par Conditions + * Argument hash_function accepts any member of enumeration @ref rsip_hash_type_t. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_SHA | + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_SHA_Init (rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Check configuration */ + FSP_ERROR_RETURN(g_sha_enabled[hash_type], FSP_ERR_NOT_ENABLED); +#endif + + return r_rsip_sha_init(p_ctrl, hash_type); +} + +/*******************************************************************************************************************//** + * Inputs SHA message. (Total input message must be less than 2^64 bits.) + * + * Implements @ref rsip_api_t::shaUpdate. + * + * @par State transition + * This API can only be executed in **STATE_SHA**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_SHA_Update (rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, uint32_t const message_length) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_message || (0 == message_length)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + return r_rsip_sha_update(p_ctrl, p_message, message_length); +} + +/*******************************************************************************************************************//** + * Outputs SHA message digest. + * + * Implements @ref rsip_api_t::shaFinish. + * + * @par Output length + * Output length to p_digest depends on hash_function. + * - 28 ( @ref RSIP_HASH_TYPE_SHA224, @ref RSIP_HASH_TYPE_SHA512_224, @ref RSIP_HASH_TYPE_SHA3_224) + * - 32 ( @ref RSIP_HASH_TYPE_SHA256, @ref RSIP_HASH_TYPE_SHA512_256, @ref RSIP_HASH_TYPE_SHA3_256) + * - 48 ( @ref RSIP_HASH_TYPE_SHA384, @ref RSIP_HASH_TYPE_SHA3_384) + * - 64 ( @ref RSIP_HASH_TYPE_SHA512, @ref RSIP_HASH_TYPE_SHA3_512) + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_SHA**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_SHA_Finish (rsip_ctrl_t * const p_ctrl, uint8_t * const p_digest) +{ +#if RSIP_CFG_PARAM_CHECKING_ENABLE + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_digest); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + return r_rsip_sha_finish(p_ctrl, p_digest); +} + +/*******************************************************************************************************************//** + * Suspends SHA operation. + * + * This API releases RSIP resource and outputs intermediate results. Therefore, it can be used in the following cases: + * - Execute another cryptographic operations during inputting successive chunks of the message. + * - Reuse intermediate results. + * + * Implements @ref rsip_api_t::shaSuspend. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_SHA**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_SHA_Suspend (rsip_ctrl_t * const p_ctrl, rsip_sha_handle_t * const p_handle) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_handle); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_SHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_ret_t rsip_ret; + switch (p_instance_ctrl->handle.sha.handle_state) + { + /* If the state is update, call suspension function */ + case RSIP_USER_HANDLE_STATE_UPDATE: + { + /* Read internal state */ + rsip_ret = r_rsip_sha_hash_suspend(&p_instance_ctrl->handle.sha); + + /* Handle state transition */ + p_instance_ctrl->handle.sha.handle_state = RSIP_USER_HANDLE_STATE_RESUME; + break; + } + + default: + { + rsip_ret = RSIP_RET_PASS; + } + } + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* Copy handle */ + *p_handle = p_instance_ctrl->handle.sha; + + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return err; +} + +/*******************************************************************************************************************//** + * Resumes SHA operation suspended by R_RSIP_SHA_Suspend(). + * + * Implements @ref rsip_api_t::shaResume. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_SHA | + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_SHA_Resume (rsip_ctrl_t * const p_ctrl, rsip_sha_handle_t const * const p_handle) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_handle); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Copy handle */ + p_instance_ctrl->handle.sha = *p_handle; + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_SHA; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Generates HMAC. (Total input message must be less than 2^64 bits.) + * + * Implements @ref rsip_api_t::hmacCompute. + * + * @par Conditions + * See R_RSIP_HMAC_Init(). + * + * @par Output length + * See R_RSIP_HMAC_SignFinish(). + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_HMAC_Compute (rsip_ctrl_t * const p_ctrl, + const rsip_wrapped_key_t * p_wrapped_key, + uint8_t const * const p_message, + uint32_t const message_length, + uint8_t * const p_mac) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ASSERT(p_message || (0 == message_length)); + FSP_ASSERT(p_mac); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + + FSP_ERROR_RETURN(RSIP_PRV_ALG_HMAC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(g_hmac_enabled[key_type_ext.subtype], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the function) */ + rsip_ret_t rsip_ret = r_rsip_hmac_init_final(p_wrapped_key, p_message, message_length, p_mac); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + /* RSIP_RET_FAIL is not used in this function */ + case RSIP_RET_FAIL: + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies HMAC. (Total input message must be less than 2^64 bits.) + * + * Implements @ref rsip_api_t::hmacVerify. + * + * @par Conditions + * See R_RSIP_HMAC_Init() and R_RSIP_HMAC_VerifyFinish(). + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE mac_length is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key value is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL MAC verification is failed. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_HMAC_Verify (rsip_ctrl_t * const p_ctrl, + const rsip_wrapped_key_t * p_wrapped_key, + uint8_t const * const p_message, + uint32_t const message_length, + uint8_t const * const p_mac, + uint32_t const mac_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ASSERT(p_message || (0 == message_length)); + FSP_ASSERT(p_mac); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_HMAC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(g_hmac_enabled[key_type_ext.subtype], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* mac_length must be 4 or greater (common) */ + FSP_ERROR_RETURN(4 <= mac_length, FSP_ERR_INVALID_SIZE); + + /* mac_length must be MAC size or less */ + FSP_ERROR_RETURN(mac_length <= gs_hmac_length[key_type_ext.subtype], FSP_ERR_INVALID_SIZE); + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function (cast to match the argument type with the function) */ + rsip_ret_t rsip_ret = r_rsip_hmac_init_verify(p_wrapped_key, p_message, message_length, p_mac, mac_length); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Starts HMAC operation. + * + * Implements @ref rsip_api_t::hmacInit. + * + * @par Conditions + * Key type of p_wrapped_key must be one of the following: + * - @ref RSIP_KEY_TYPE_HMAC_SHA224 + * - @ref RSIP_KEY_TYPE_HMAC_SHA256 + * - @ref RSIP_KEY_TYPE_HMAC_SHA384 + * - @ref RSIP_KEY_TYPE_HMAC_SHA512 + * - @ref RSIP_KEY_TYPE_HMAC_SHA512_224 + * - @ref RSIP_KEY_TYPE_HMAC_SHA512_256 + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_HMAC| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_NOT_ENABLED Input key type is disabled in this function by configuration. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * + * @sa Section @ref r-rsip-protected-supported-algorithms "Supported Algorithms". + **********************************************************************************************************************/ +fsp_err_t R_RSIP_HMAC_Init (rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_key) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_wrapped_key); + FSP_ASSERT(p_wrapped_key->p_value); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_wrapped_key->type); // Parse key type + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(RSIP_PRV_ALG_HMAC == key_type_ext.alg, FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL); // Check key type + FSP_ERROR_RETURN(g_hmac_enabled[key_type_ext.subtype], FSP_ERR_NOT_ENABLED); // Check configuration +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_hmac_handle_t * p_handle = &p_instance_ctrl->handle.hmac; + + /* Reset handle */ + p_handle->buffered_length = 0; + p_handle->total_length = 0; + + /* Copy wrapped key */ + p_handle->wrapped_key.type = p_wrapped_key->type; + p_handle->wrapped_key.p_value = p_handle->wrapped_key_value; + memcpy(p_handle->wrapped_key_value, p_wrapped_key->p_value, RSIP_BYTE_SIZE_WRAPPED_KEY(p_wrapped_key->type)); + + /* Set block size */ + switch (key_type_ext.subtype) + { + /* SHA-1, SHA-224, SHA-256 */ + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA1: + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA224: + case RSIP_PRV_KEY_SUBTYPE_HMAC_SHA256: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA1_SHA224_SHA256; + break; + } + + /* SHA-384, SHA-512 */ + default: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA384_SHA512; + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_HMAC; + p_handle->handle_state = RSIP_USER_HANDLE_STATE_INIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Inputs HMAC message. (Total input message must be less than 2^64 bits.) + * + * Implements @ref rsip_api_t::hmacUpdate. + * + * @par State transition + * This API can only be executed in **STATE_HMAC**, and does not cause any state transitions. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_HMAC_Update (rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, + uint32_t const message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_message || (0 == message_length)); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + if (0 == message_length) + { + err = FSP_SUCCESS; + } + else + { + rsip_ret_t rsip_ret = RSIP_RET_PASS; + rsip_hmac_handle_t * p_handle = &p_instance_ctrl->handle.hmac; + const uint8_t * p_msg_pos = p_message; + uint32_t processed_len = 0; + + /* (1) Remaining message in buffer and head of new input message */ + if ((0 != p_handle->buffered_length) && + (p_handle->block_size < (p_handle->buffered_length + message_length))) + { + uint32_t len = p_handle->block_size - p_handle->buffered_length; + + /* Copy head of new message to buffer */ + memcpy(p_handle->buffer + p_handle->buffered_length, p_msg_pos, len); + + /* Call function */ + rsip_ret = hmac_update(p_ctrl, p_handle->buffer, p_handle->block_size); + + p_handle->buffered_length = 0; + p_handle->total_length += p_handle->block_size; + processed_len += len; + } + + /* (2) New input message except last block */ + if ((p_handle->block_size < message_length) && (RSIP_RET_PASS == rsip_ret)) + { + uint32_t len = ((message_length - processed_len - 1) / p_handle->block_size) * + p_handle->block_size; + + /* Call function */ + rsip_ret = hmac_update(p_ctrl, p_message + processed_len, len); + + p_handle->total_length += len; + processed_len += len; + } + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* (3) Last block */ + memcpy(p_handle->buffer + p_handle->buffered_length, + p_message + processed_len, + message_length - processed_len); + p_handle->buffered_length += message_length - processed_len; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + /* RSIP_RET_FAIL is not used in this function */ + case RSIP_RET_FAIL: + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Outputs HMAC. + * + * Implements @ref rsip_api_t::hmacSignFinish. + * + * @par Output length + * Output length to p_mac depends on key type of p_wrapped_key. + * - 28 ( @ref RSIP_KEY_TYPE_HMAC_SHA224, @ref RSIP_KEY_TYPE_HMAC_SHA512_224) + * - 32 ( @ref RSIP_KEY_TYPE_HMAC_SHA256, @ref RSIP_KEY_TYPE_HMAC_SHA512_256) + * - 48 ( @ref RSIP_KEY_TYPE_HMAC_SHA384) + * - 64 ( @ref RSIP_KEY_TYPE_HMAC_SHA512) + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_HMAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_HMAC_SignFinish (rsip_ctrl_t * const p_ctrl, uint8_t * const p_mac) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_mac); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function */ + rsip_ret_t rsip_ret = hmac_sign_finish(p_ctrl, p_mac); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + /* RSIP_RET_FAIL is not used in this function */ + case RSIP_RET_FAIL: + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Verifies HMAC. + * + * Implements @ref rsip_api_t::hmacVerifyFinish. + * + * @par Conditions + * Argument mac_length depends on key type of p_wrapped_key. Usually the longest length is recommended. + * - 4 to 28 ( @ref RSIP_KEY_TYPE_HMAC_SHA224, @ref RSIP_KEY_TYPE_HMAC_SHA512_224) + * - 4 to 32 ( @ref RSIP_KEY_TYPE_HMAC_SHA256, @ref RSIP_KEY_TYPE_HMAC_SHA512_256) + * - 4 to 48 ( @ref RSIP_KEY_TYPE_HMAC_SHA384) + * - 4 to 64 ( @ref RSIP_KEY_TYPE_HMAC_SHA512) + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_HMAC**, and causes state transition. + * + * |Return value |Next state| + * |---------------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |FSP_ERR_ASSERTION |No change | + * |FSP_ERR_NOT_OPEN |No change | + * |FSP_ERR_INVALID_STATE|No change | + * |FSP_ERR_INVALID_SIZE |No change | + * |Others |STATE_MAIN| + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_INVALID_SIZE mac_length is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL Input key is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FAIL MAC verification is failed. + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_HMAC_VerifyFinish (rsip_ctrl_t * const p_ctrl, uint8_t const * const p_mac, uint32_t const mac_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_mac); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_hmac_handle_t * p_handle = &p_instance_ctrl->handle.hmac; + rsip_key_type_extend_t key_type_ext = r_rsip_key_type_parse(p_handle->wrapped_key.type); + + /* mac_length must be 4 or greater (common) */ + FSP_ERROR_RETURN(4 <= mac_length, FSP_ERR_INVALID_SIZE); + + /* mac_length must be MAC size or less */ + FSP_ERROR_RETURN(mac_length <= gs_hmac_length[key_type_ext.subtype], FSP_ERR_INVALID_SIZE); + + /* Call function (cast to match the argument type with the function) */ + rsip_ret_t rsip_ret = hmac_verify_finish(p_ctrl, p_mac, mac_length); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_KEY_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL; + break; + } + + case RSIP_RET_FAIL: + { + err = FSP_ERR_CRYPTO_RSIP_FAIL; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Suspends HMAC operation. + * + * This API releases RSIP resource and outputs intermediate results. Therefore, it can be used in the following cases: + * - Execute another cryptographic operations during inputting successive chunks of the message. + * - Reuse intermediate results. + * + * Implements @ref rsip_api_t::hmacSuspend. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_HMAC**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_MAIN| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_HMAC_Suspend (rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_t * const p_handle) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_handle); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_HMAC == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + rsip_ret_t rsip_ret; + switch (p_instance_ctrl->handle.hmac.handle_state) + { + /* If the state is update, call suspension function */ + case RSIP_USER_HANDLE_STATE_UPDATE: + { + /* Read internal state */ + rsip_ret = r_rsip_hmac_suspend(&p_instance_ctrl->handle.hmac); + + /* Handle state transition */ + p_instance_ctrl->handle.hmac.handle_state = RSIP_USER_HANDLE_STATE_RESUME; + break; + } + + default: + { + rsip_ret = RSIP_RET_PASS; + } + } + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* Copy handle */ + *p_handle = p_instance_ctrl->handle.hmac; + + err = FSP_SUCCESS; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return err; +} + +/*******************************************************************************************************************//** + * Resumes HMAC operation suspended by R_RSIP_HMAC_Suspend(). + * + * Implements @ref rsip_api_t::hmacResume. + * + * @par State transition + * @parblock + * This API can only be executed in **STATE_MAIN**, and causes state transition. + * + * |Return value|Next state| + * |------------|----------| + * |FSP_SUCCESS |STATE_HMAC| + * |Others |No change | + * @endparblock + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_HMAC_Resume (rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_t const * const p_handle) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + +#if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_handle); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Copy handle */ + p_instance_ctrl->handle.hmac = *p_handle; + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_HMAC; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Prepares a SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] hash_type Generating hash type. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + **********************************************************************************************************************/ +fsp_err_t r_rsip_sha_init (rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_sha_handle_t * p_handle = &p_instance_ctrl->handle.sha; + + /* Reset handle */ + p_handle->buffered_length = 0; + p_handle->total_length = 0; + + /* Set hash type */ + p_handle->type = hash_type; + + /* Set block size */ + switch (hash_type) + { + /* SHA-1, SHA-224, SHA-256 */ + case RSIP_HASH_TYPE_SHA1: + case RSIP_HASH_TYPE_SHA224: + case RSIP_HASH_TYPE_SHA256: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA1_SHA224_SHA256; + break; + } + + /* SHA-384, SHA-512, SHA-512/224, SHA-512/256 */ + case RSIP_HASH_TYPE_SHA384: + case RSIP_HASH_TYPE_SHA512: + case RSIP_HASH_TYPE_SHA512_224: + case RSIP_HASH_TYPE_SHA512_256: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA384_SHA512; + break; + } + + /* SHA3-224 */ + case RSIP_HASH_TYPE_SHA3_224: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA3_224; + break; + } + + /* SHA3-256 */ + case RSIP_HASH_TYPE_SHA3_256: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA3_256; + break; + } + + /* SHA3-384 */ + case RSIP_HASH_TYPE_SHA3_384: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA3_384; + break; + } + + /* SHA3-512 */ + default: + { + p_handle->block_size = RSIP_PRV_BYTE_SIZE_HASH_BLOCK_SHA3_512; + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_SHA; + p_handle->handle_state = RSIP_USER_HANDLE_STATE_INIT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t r_rsip_sha_update (rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, uint32_t const message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_SHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + rsip_sha_handle_t * p_handle = &p_instance_ctrl->handle.sha; + + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + if (0 == message_length) + { + err = FSP_SUCCESS; + } + else + { + rsip_ret_t rsip_ret = RSIP_RET_PASS; + const uint8_t * p_msg_pos = p_message; + uint32_t processed_len = 0; + + /* (1) Remaining message in buffer and head of new input message */ + if ((0 != p_handle->buffered_length) && + (p_handle->block_size < (p_handle->buffered_length + message_length))) + { + uint32_t len = p_handle->block_size - p_handle->buffered_length; + + /* Copy head of new message to buffer */ + memcpy(p_handle->buffer + p_handle->buffered_length, p_msg_pos, len); + + /* Call function */ + rsip_ret = sha_update(p_ctrl, p_handle->buffer, p_handle->block_size); + + p_handle->buffered_length = 0; + p_handle->total_length += p_handle->block_size; + processed_len += len; + } + + /* (2) New input message except last block */ + if ((p_handle->block_size < message_length) && (RSIP_RET_PASS == rsip_ret)) + { + uint32_t len = ((message_length - processed_len - 1) / p_handle->block_size) * + p_handle->block_size; + + /* Call function */ + rsip_ret = sha_update(p_ctrl, p_message + processed_len, len); + + p_handle->total_length += len; + processed_len += len; + } + + /* Check error */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + /* (3) Last block */ + memcpy(p_handle->buffer + p_handle->buffered_length, + p_message + processed_len, + message_length - processed_len); + p_handle->buffered_length += message_length - processed_len; + + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Finalizes a SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_RSIP_FATAL Software corruption is detected. + **********************************************************************************************************************/ +fsp_err_t r_rsip_sha_finish (rsip_ctrl_t * const p_ctrl, uint8_t * const p_digest) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_SHA == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call function */ + rsip_ret_t rsip_ret = sha_finish(p_ctrl, p_digest); + + /* Check error */ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + err = FSP_SUCCESS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + err = FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT; + break; + } + + default: + { + err = FSP_ERR_CRYPTO_RSIP_FATAL; + } + } + + return err; +} + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t sha_update (rsip_ctrl_t * const p_ctrl, const uint8_t * p_message, uint32_t message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_sha_handle_t * p_handle = &p_instance_ctrl->handle.sha; + + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = r_rsip_sha_hash_init_update(p_handle, p_message, message_length); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = r_rsip_sha_hash_resume_update(p_handle, p_message, message_length); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_sha_hash_update(p_handle, p_message, message_length); + } + } + + /* Check error */ + switch (ret) + { + case RSIP_RET_PASS: + { + /* State transition */ + p_handle->handle_state = RSIP_USER_HANDLE_STATE_UPDATE; + break; + } + + default: + { + /* State transition (abort) */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Finalizes a SHA generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_digest Pointer to destination of message digest. The length depends on hash type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t sha_finish (rsip_ctrl_t * const p_ctrl, uint8_t * p_digest) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_sha_handle_t * p_handle = &p_instance_ctrl->handle.sha; + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = r_rsip_sha_hash_init_final(p_handle->type, p_handle->buffer, p_handle->buffered_length, p_digest); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = r_rsip_sha_hash_resume_final(p_handle, p_digest); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_sha_hash_final(p_handle, p_digest); + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return ret; +} + +/*******************************************************************************************************************//** + * Inputs message. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_message Pointer to message. The length is message_length. + * @param[in] message_length Byte length of message (0 or more bytes). + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t hmac_update (rsip_ctrl_t * const p_ctrl, const uint8_t * p_message, uint32_t message_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_hmac_handle_t * p_handle = &p_instance_ctrl->handle.hmac; + + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = r_rsip_hmac_init_update(p_handle, p_message, message_length); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = + r_rsip_hmac_resume_update(p_handle, p_message, message_length); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_hmac_update(p_handle, p_message, message_length); + } + } + + /* Check error */ + switch (ret) + { + case RSIP_RET_PASS: + { + /* State transition */ + p_handle->handle_state = RSIP_USER_HANDLE_STATE_UPDATE; + break; + } + + default: + { + /* State transition (abort) */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Finalizes a HMAC generation. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[out] p_mac Pointer to destination of message digest. The length depends on MAC type. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t hmac_sign_finish (rsip_ctrl_t * const p_ctrl, uint8_t * p_mac) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_hmac_handle_t * p_handle = &p_instance_ctrl->handle.hmac; + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = + r_rsip_hmac_init_final(&p_handle->wrapped_key, p_handle->buffer, p_handle->buffered_length, p_mac); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = r_rsip_hmac_resume_final(p_handle, p_mac); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_hmac_final(p_handle, p_mac); + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return ret; +} + +/*******************************************************************************************************************//** + * Finalizes a HMAC verification. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_mac Pointer to MAC. The length depends on mac_length. + * @param[in] mac_length Byte length of MAC. + * + * @return The return value of the internally called primitive function. + **********************************************************************************************************************/ +static rsip_ret_t hmac_verify_finish (rsip_ctrl_t * const p_ctrl, const uint8_t * p_mac, const uint32_t mac_length) +{ + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + rsip_hmac_handle_t * p_handle = &p_instance_ctrl->handle.hmac; + rsip_ret_t ret; + switch (p_handle->handle_state) + { + case RSIP_USER_HANDLE_STATE_INIT: + { + ret = + r_rsip_hmac_init_verify(&p_handle->wrapped_key, + p_handle->buffer, + p_handle->buffered_length, + p_mac, + mac_length); + break; + } + + case RSIP_USER_HANDLE_STATE_RESUME: + { + ret = r_rsip_hmac_resume_verify(p_handle, p_mac, mac_length); + break; + } + + case RSIP_USER_HANDLE_STATE_UPDATE: + default: + { + ret = r_rsip_hmac_verify(p_handle, p_mac, mac_length); + } + } + + /* State transition */ + p_instance_ctrl->state = RSIP_STATE_MAIN; + + return ret; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/inc/instances/r_rsip.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/inc/instances/r_rsip.h new file mode 100644 index 0000000000..b9471490ba --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/inc/instances/r_rsip.h @@ -0,0 +1,889 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +#ifndef R_RSIP_H +#define R_RSIP_H + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_rsip_api.h" +#include "r_rsip_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Version Number of Module. */ +#define FSP_R_RSIP_PROTECTED_VERSION_MAJOR (2U) +#define FSP_R_RSIP_PROTECTED_VERSION_MINOR (3U) +#define FSP_R_RSIP_PROTECTED_VERSION_PATCH (0U) + +/** Returns the plain key size formatted for RSIP driver of the key type. */ +#define RSIP_BYTE_SIZE_PLAIN_KEY(key_type) (RSIP_PRV_KEY_TYPE_VAL_PLAIN_WORDS(key_type) << 2) + +/** Returns the encrypted key size of the key type. */ +#define RSIP_BYTE_SIZE_ENCRYPTED_KEY(key_type) (RSIP_PRV_BYTE_SIZE_ENCRYPTED_DATA(RSIP_PRV_KEY_TYPE_VAL_PLAIN_WORDS( \ + key_type))) + +/** Returns the wrapped key size of the key type. */ +#define RSIP_BYTE_SIZE_WRAPPED_KEY(key_type) (RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(RSIP_PRV_KEY_TYPE_VAL_PLAIN_WORDS( \ + key_type))) + +/* data size */ +#define RSIP_PRV_BYTE_SIZE_ENCRYPTED_DATA(words) (((words) + RSIP_CFG_WORD_SIZE_ENCRYPTED_KEY_OVERHEAD) << 2) +#define RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(words) (((words) + RSIP_CFG_WORD_SIZE_WRAPPED_KEY_OVERHEAD) << 2) + +/* Wrapped ECDH secret size */ +#define RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_256 RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(8) +#define RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_384 RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(12) +#define RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_512 RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(16) +#define RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_521 RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(20) + +/* Internal state buffer size for SHA */ +#if RSIP_CFG_SHA3_224_ENABLE || RSIP_CFG_SHA3_256_ENABLE || RSIP_CFG_SHA3_384_ENABLE || RSIP_CFG_SHA3_512_ENABLE + #define RSIP_PRV_WORD_SIZE_SHA_INTERNAL_STATE_BUF (52U) +#else + #define RSIP_PRV_WORD_SIZE_SHA_INTERNAL_STATE_BUF (20U) +#endif + +/* Internal state buffer size for HMAC */ +#define RSIP_PRV_WORD_SIZE_HMAC_INTERNAL_STATE_BUF (20U) + +/* Buffer size for SHA */ +#if RSIP_CFG_SHA3_224_ENABLE + #define RSIP_PRV_BYTE_SIZE_SHA_BLOCK_BUF (144U * RSIP_CFG_SHA_BUF_BLOCKS) +#elif RSIP_CFG_SHA3_256_ENABLE + #define RSIP_PRV_BYTE_SIZE_SHA_BLOCK_BUF (136U * RSIP_CFG_SHA_BUF_BLOCKS) +#elif RSIP_CFG_SHA512_ENABLE || RSIP_CFG_SHA512_224_ENABLE || RSIP_CFG_SHA512_256_ENABLE || RSIP_CFG_SHA384_ENABLE + #define RSIP_PRV_BYTE_SIZE_SHA_BLOCK_BUF (128U * RSIP_CFG_SHA_BUF_BLOCKS) +#elif RSIP_CFG_SHA3_384_ENABLE + #define RSIP_PRV_BYTE_SIZE_SHA_BLOCK_BUF (104U * RSIP_CFG_SHA_BUF_BLOCKS) +#elif RSIP_CFG_SHA3_512_ENABLE + #define RSIP_PRV_BYTE_SIZE_SHA_BLOCK_BUF (72U * RSIP_CFG_SHA_BUF_BLOCKS) +#else + #define RSIP_PRV_BYTE_SIZE_SHA_BLOCK_BUF (64U * RSIP_CFG_SHA_BUF_BLOCKS) +#endif + +/* Buffer size for KDF SHA */ +#if RSIP_CFG_KDF_SHA384_ENABLE + #define RSIP_PRV_BYTE_SIZE_KDF_SHA_BLOCK_BUF (128U) +#else + #define RSIP_PRV_BYTE_SIZE_KDF_SHA_BLOCK_BUF (64U) +#endif + +/* Buffer sizes for HMAC */ +#if RSIP_CFG_HMAC_SHA512_ENABLE + #define RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_HMAC_BUF RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA512) + #define RSIP_PRV_BYTE_SIZE_HMAC_BLOCK_BUF (128U * RSIP_CFG_SHA_BUF_BLOCKS) +#elif RSIP_CFG_HMAC_SHA384_ENABLE + #define RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_HMAC_BUF RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA384) + #define RSIP_PRV_BYTE_SIZE_HMAC_BLOCK_BUF (128U * RSIP_CFG_SHA_BUF_BLOCKS) +#elif RSIP_CFG_HMAC_SHA256_ENABLE + #define RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_HMAC_BUF RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA256) + #define RSIP_PRV_BYTE_SIZE_HMAC_BLOCK_BUF (64U * RSIP_CFG_HMAC_BUF_BLOCKS) +#elif RSIP_CFG_HMAC_SHA224_ENABLE + #define RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_HMAC_BUF RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA224) + #define RSIP_PRV_BYTE_SIZE_HMAC_BLOCK_BUF (64U * RSIP_CFG_HMAC_BUF_BLOCKS) +#else + #define RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_HMAC_BUF RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA1) + #define RSIP_PRV_BYTE_SIZE_HMAC_BLOCK_BUF (64U * RSIP_CFG_HMAC_BUF_BLOCKS) +#endif + +/* Buffer size for ECDH */ +#if RSIP_CFG_ECC_SECP521R1_ENABLE + #define RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_BUF RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_521 +#elif RSIP_CFG_ECC_SECP384R1_ENABLE + #define RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_BUF RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_384 +#else + #define RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_BUF RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_256 +#endif + +/* Buffer size for KDF */ +#if RSIP_CFG_ECC_SECP521R1_ENABLE + #define RSIP_PRV_BYTE_SIZE_KDF_WRAPPED_MSG_BUF RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_521 +#elif RSIP_CFG_KDF_HMAC_SHA512_ENABLE + #define RSIP_PRV_BYTE_SIZE_KDF_WRAPPED_MSG_BUF RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA512 +#elif RSIP_CFG_ECC_SECP384R1_ENABLE + #define RSIP_PRV_BYTE_SIZE_KDF_WRAPPED_MSG_BUF RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_384 +#elif RSIP_CFG_KDF_HMAC_SHA384_ENABLE + #define RSIP_PRV_BYTE_SIZE_KDF_WRAPPED_MSG_BUF RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA384 +#else + #define RSIP_PRV_BYTE_SIZE_KDF_WRAPPED_MSG_BUF RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA256 +#endif + +/* Buffer sizes for KDF HMAC */ +#if RSIP_CFG_KDF_HMAC_SHA512_ENABLE + #define RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_KDF_HMAC_BUF RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA512) + #define RSIP_PRV_BYTE_SIZE_KDF_HMAC_BLOCK_BUF (128U) +#elif RSIP_CFG_KDF_HMAC_SHA384_ENABLE + #define RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_KDF_HMAC_BUF RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA384) + #define RSIP_PRV_BYTE_SIZE_KDF_HMAC_BLOCK_BUF (128U) +#else + #define RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_KDF_HMAC_BUF RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA256) + #define RSIP_PRV_BYTE_SIZE_KDF_HMAC_BLOCK_BUF (64U) +#endif + +/* Buffer sizes for PKI */ +#if RSIP_CFG_ECC_SECP521R1_ENABLE + #define RSIP_PRV_BYTE_SIZE_PKI_ENC_CERT_INFO RSIP_BYTE_SIZE_WRAPPED_KEY(16) +#elif RSIP_CFG_ECC_SECP384R1_ENABLE + #define RSIP_PRV_BYTE_SIZE_PKI_ENC_CERT_INFO RSIP_BYTE_SIZE_WRAPPED_KEY(12) +#else + #define RSIP_PRV_BYTE_SIZE_PKI_ENC_CERT_INFO RSIP_BYTE_SIZE_WRAPPED_KEY(8) +#endif + +/* Constants */ +#define RSIP_PRV_BYTE_SIZE_AES_BLOCK (16U) +#define RSIP_PRV_BYTE_SIZE_CCM_NONCE_MAX (13U) +#define RSIP_PRV_BYTE_SIZE_CCM_AAD_MAX (110U) +#define RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK (64U) +#define RSIP_PRV_WORD_SIZE_CHACHA20_NONCE (3U) + +/* Return code for SB-Lib */ +#define FSP_ERR_SB_INTERNAL_FAIL (0x00030000UL) ///< An internal failure +#define FSP_ERR_SB_INVALID_ARG (0x00030001UL) ///< An invalid argument was entered +#define FSP_ERR_SB_UNSUPPORTED_FUNCTION (0x00030002UL) ///< Unsupported function executed +#define FSP_ERR_SB_INVALID_ALIGNMENT (0x00030003UL) ///< Data entered with incorrect alignment +#define FSP_ERR_SB_SAME_IMAGE_VERSION (0x00030004UL) ///< Same image version +#define FSP_ERR_SB_LOWER_IMAGE_VERSION (0x00030005UL) ///< Lower image version +#define FSP_ERR_SB_MANI_INVALID_MAGIC (0x00031000UL) ///< An invalid magic number is set +#define FSP_ERR_SB_MANI_UNSUPPORTED_VERSION (0x00031001UL) ///< Unsupported version is set +#define FSP_ERR_SB_MANI_OUT_OF_RANGE_LEN (0x00031002UL) ///< Out of range TLV Length is set +#define FSP_ERR_SB_MANI_TLV_FIELD_ERR (0x00031003UL) ///< Missing required TLV field +#define FSP_ERR_SB_MANI_TLV_INVALID_LEN (0x00031004UL) ///< The length exceeding the end of the manifest is specified in length of the TLV field +#define FSP_ERR_SB_MANI_INVALID_IMAGE_LEN (0x00031005UL) ///< An invalid image length is set +#define FSP_ERR_SB_MANI_MISMATCH_SIGN_ALGORITHM (0x00031006UL) ///< There is a wrong combination of signature algorithms +#define FSP_ERR_SB_MANI_UNSUPPORTED_ALGORITHM (0x00031007UL) ///< An algorithm was specified that the manifest does not support +#define FSP_ERR_SB_CRYPTO_FAIL (0x00032000UL) ///< Cryptographic processing failure +#define FSP_ERR_SB_CRYPTO_AUTH_FAIL (0x00032001UL) ///< Verification failed +#define FSP_ERR_SB_CRYPTO_UNSUPPORTED_ALGORITHM (0x00032002UL) ///< Unsupported algorithm +#define FSP_ERR_SB_CRYPTO_RESOURCE_CONFLICT (0x00032003UL) ///< CryptoIP is in use. +#define FSP_ERR_SB_CRYPTO_PARAM_ERR (0x00032004UL) ///< Parameter error + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * Byte size of wrapped key + */ +typedef enum e_rsip_byte_size_wrapped_key +{ + RSIP_BYTE_SIZE_WRAPPED_KEY_AES_128 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_AES_128), ///< AES-128 + RSIP_BYTE_SIZE_WRAPPED_KEY_AES_192 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_AES_192), ///< AES-192 + RSIP_BYTE_SIZE_WRAPPED_KEY_AES_256 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_AES_256), ///< AES-256 + RSIP_BYTE_SIZE_WRAPPED_KEY_XTS_AES_128 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_XTS_AES_128), ///< XTS-AES-128 + RSIP_BYTE_SIZE_WRAPPED_KEY_XTS_AES_256 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_XTS_AES_256), ///< XTS-AES-256 + RSIP_BYTE_SIZE_WRAPPED_KEY_CHACHA20 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_CHACHA20), ///< ChaCha20 + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_SECP256R1_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC), ///< secp256r1 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_SECP384R1_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC), ///< secp384r1 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_SECP521R1_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC), ///< secp521r1 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_SECP256K1_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_SECP256K1_PUBLIC), ///< secp256k1 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_BRAINPOOLP256R1_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PUBLIC), ///< brainpoolP256r1 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_BRAINPOOLP384R1_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PUBLIC), ///< brainpoolP384r1 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_BRAINPOOLP512R1_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP512R1_PUBLIC), ///< brainpoolP512r1 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_EDWARDS25519_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_EDWARDS25519_PUBLIC), ///< edwards25519 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_SECP256R1_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_SECP256R1_PRIVATE), ///< secp256r1 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_SECP384R1_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_SECP384R1_PRIVATE), ///< secp384r1 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_SECP521R1_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_SECP521R1_PRIVATE), ///< secp521r1 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_SECP256K1_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_SECP256K1_PRIVATE), ///< secp256k1 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_BRAINPOOLP256R1_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PRIVATE), ///< brainpoolP256r1 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_BRAINPOOLP384R1_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PRIVATE), ///< brainpoolP384r1 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_BRAINPOOLP512R1_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP512R1_PRIVATE), ///< brainpoolP512r1 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_ECC_EDWARDS25519_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_ECC_EDWARDS25519_PRIVATE), ///< edwards25519 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_1024_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_RSA_1024_PUBLIC), ///< RSA-1024 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_2048_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_RSA_2048_PUBLIC), ///< RSA-2048 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_3072_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_RSA_3072_PUBLIC), ///< RSA-3072 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_4096_PUBLIC = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_RSA_4096_PUBLIC), ///< RSA-4096 public key + RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_1024_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_RSA_1024_PRIVATE), ///< RSA-1024 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_2048_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_RSA_2048_PRIVATE), ///< RSA-2048 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_3072_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_RSA_3072_PRIVATE), ///< RSA-3072 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_RSA_4096_PRIVATE = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_RSA_4096_PRIVATE), ///< RSA-4096 private key + RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA1 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA1), ///< HMAC-SHA1 + RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA224 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA224), ///< HMAC-SHA224 + RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA256 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA256), ///< HMAC-SHA256 + RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA384 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA384), ///< HMAC-SHA384 + RSIP_BYTE_SIZE_WRAPPED_KEY_HMAC_SHA512 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_HMAC_SHA512), ///< HMAC-SHA512 + RSIP_BYTE_SIZE_WRAPPED_KEY_KDF_HMAC_SHA256 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA256), ///< KDF HMAC-SHA256 + RSIP_BYTE_SIZE_WRAPPED_KEY_KDF_HMAC_SHA384 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA384), ///< KDF HMAC-SHA384 + RSIP_BYTE_SIZE_WRAPPED_KEY_KDF_HMAC_SHA512 = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA512), ///< KDF HMAC-SHA512 + RSIP_BYTE_SIZE_WRAPPED_KEY_KUK = + RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_KUK), ///< Key Update Key (KUK) +} rsip_byte_size_wrapped_key_t; + +/** + * Byte size of encrypted key + */ +typedef enum e_rsip_byte_size_encrypted_key +{ + RSIP_BYTE_SIZE_ENCRYPTED_KEY_AES_128 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_AES_128), ///< AES-128 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_AES_192 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_AES_192), ///< AES-192 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_AES_256 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_AES_256), ///< AES-256 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_XTS_AES_128 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_XTS_AES_128), ///< XTS-AES-128 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_XTS_AES_256 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_XTS_AES_256), ///< XTS-AES-256 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_CHACHA20 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_CHACHA20), ///< ChaCha20 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_SECP256R1_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_SECP256R1_PUBLIC), ///< secp256r1 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_SECP384R1_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_SECP384R1_PUBLIC), ///< secp384r1 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_SECP521R1_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_SECP521R1_PUBLIC), ///< secp521r1 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_SECP256K1_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_SECP256K1_PUBLIC), ///< secp256k1 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_BRAINPOOLP256R1_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PUBLIC), ///< brainpoolP256r1 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_BRAINPOOLP384R1_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PUBLIC), ///< brainpoolP384r1 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_BRAINPOOLP512R1_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP512R1_PUBLIC), ///< brainpoolP512r1 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_EDWARDS25519_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_EDWARDS25519_PUBLIC), ///< edwards25519 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_SECP256R1_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_SECP256R1_PRIVATE), ///< secp256r1 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_SECP384R1_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_SECP384R1_PRIVATE), ///< secp384r1 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_SECP521R1_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_SECP521R1_PRIVATE), ///< secp521r1 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_SECP256K1_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_SECP256K1_PRIVATE), ///< secp256k1 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_BRAINPOOLP256R1_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP256R1_PRIVATE), ///< brainpoolP256r1 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_BRAINPOOLP384R1_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP384R1_PRIVATE), ///< brainpoolP384r1 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_BRAINPOOLP512R1_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_BRAINPOOLP512R1_PRIVATE), ///< brainpoolP512r1 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_ECC_EDWARDS25519_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_ECC_EDWARDS25519_PRIVATE), ///< edwards25519 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_RSA_1024_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_RSA_1024_PUBLIC), ///< RSA-1024 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_RSA_2048_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_RSA_2048_PUBLIC), ///< RSA-2048 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_RSA_3072_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_RSA_3072_PUBLIC), ///< RSA-3072 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_RSA_4096_PUBLIC = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_RSA_4096_PUBLIC), ///< RSA-4096 public key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_RSA_1024_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_RSA_1024_PRIVATE), ///< RSA-1024 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_RSA_2048_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_RSA_2048_PRIVATE), ///< RSA-2048 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_RSA_3072_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_RSA_3072_PRIVATE), ///< RSA-3072 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_RSA_4096_PRIVATE = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_RSA_4096_PRIVATE), ///< RSA-4096 private key + RSIP_BYTE_SIZE_ENCRYPTED_KEY_HMAC_SHA1 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_HMAC_SHA1), ///< HMAC-SHA1 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_HMAC_SHA224 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_HMAC_SHA224), ///< HMAC-SHA224 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_HMAC_SHA256 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_HMAC_SHA256), ///< HMAC-SHA256 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_HMAC_SHA384 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_HMAC_SHA384), ///< HMAC-SHA384 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_HMAC_SHA512 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_HMAC_SHA512), ///< HMAC-SHA512 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_KDF_HMAC_SHA256 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA256), ///< KDF HMAC-SHA256 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_KDF_HMAC_SHA384 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA384), ///< KDF HMAC-SHA384 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_KDF_HMAC_SHA512 = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_KDF_HMAC_SHA512), ///< KDF HMAC-SHA512 + RSIP_BYTE_SIZE_ENCRYPTED_KEY_KUK = + RSIP_BYTE_SIZE_ENCRYPTED_KEY(RSIP_KEY_TYPE_KUK), ///< Key Update Key (KUK) +} rsip_byte_size_encrypted_key_t; + +/** Byte size of wrapped key */ +typedef enum e_rsip_byte_size_wrapped_dkm +{ + RSIP_BYTE_SIZE_WRAPPED_DKM_HEADER = 12, ///< Header + RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA256 = RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(8), ///< A block of SHA-256 + RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA384 = RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(12), ///< A block of SHA-384 + RSIP_BYTE_SIZE_WRAPPED_DKM_BLOCK_SHA512 = RSIP_PRV_BYTE_SIZE_WRAPPED_DATA(16), ///< A block of SHA-384 +} rsip_byte_size_wrapped_dkm_t; + +/* Working area for AES block cipher */ +typedef struct st_rsip_aes_cihper_handle +{ + const void * p_func; // Pointer to primitive functions +} rsip_aes_cipher_handle_t; + +/* Working area for AES-GCM */ +typedef struct st_rsip_aes_gcm_handle +{ + const void * p_func; // Pointer to primitive functions + uint8_t buffer[RSIP_PRV_BYTE_SIZE_AES_BLOCK]; // Buffer for AAD and plaintext/ciphertext + uint32_t buffered_length; // Buffered AAD and plaintext/ciphertext length + uint32_t total_length; // Total plaintext/ciphertext length + uint32_t total_aad_length; // Total AAD length +} rsip_aes_gcm_handle_t; + +/* Working area for AES-CCM */ +typedef struct st_rsip_aes_ccm_handle +{ + const void * p_func; // Pointer to primitive functions + rsip_wrapped_key_t wrapped_key; // Wrapped key + uint8_t wrapped_key_value[RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_AES_256)]; // Wrapped key value + uint8_t nonce_buffer[RSIP_PRV_BYTE_SIZE_CCM_NONCE_MAX]; // Buffer for nonce + uint32_t nonce_length; // Nonce length + uint8_t buffer[RSIP_PRV_BYTE_SIZE_CCM_AAD_MAX]; // Buffer for AAD and plaintext/ciphertext + uint32_t buffered_length; // Buffered AAD and plaintext/ciphertext length + uint32_t input_aad_length; // Input AAD length + uint32_t total_aad_length; // Total AAD length + uint32_t input_length; // Input plaintext/ciphertext length + uint32_t total_length; // Total plaintext/ciphertext length + uint32_t tag_length; // Tag length +} rsip_aes_ccm_handle_t; + +/* Working area for AES-CMAC */ +typedef struct st_rsip_aes_cmac_handle +{ + const void * p_func; // Pointer to primitive functions + uint8_t buffer[RSIP_PRV_BYTE_SIZE_AES_BLOCK]; // Buffer for message + uint32_t buffered_length; // Buffered message length + uint32_t total_length; // Total message length +} rsip_aes_cmac_handle_t; + +/* Working area for ChaCha20 */ +typedef struct st_rsip_chacha20_handle +{ + const void * p_func; // Pointer to primitive functions + rsip_wrapped_key_t wrapped_key; // Wrapped key + uint8_t wrapped_key_value[RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_CHACHA20)]; // Wrapped key value + uint32_t nonce_buffer[RSIP_PRV_WORD_SIZE_CHACHA20_NONCE]; // Buffer for nonce + uint8_t buffer[RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK]; // Buffer for plaintext/ciphertext + uint32_t buffered_length; // Buffered plaintext/ciphertext length + uint32_t total_length; // Total plaintext/ciphertext length +} rsip_chacha20_handle_t; + +/* Working area for ChaCha20-Poly1305 */ +typedef struct st_rsip_chacha20_poly1305_handle +{ + const void * p_func; // Pointer to primitive functions + rsip_wrapped_key_t wrapped_key; // Wrapped key + uint8_t wrapped_key_value[RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_CHACHA20)]; // Wrapped key value + uint32_t nonce_buffer[RSIP_PRV_WORD_SIZE_CHACHA20_NONCE]; // Buffer for nonce + uint8_t buffer[RSIP_PRV_BYTE_SIZE_CHACHA20_BLOCK]; // Buffer for plaintext/ciphertext + uint32_t buffered_length; // Buffered plaintext/ciphertext length + uint32_t total_length; // Total plaintext/ciphertext length + uint32_t total_aad_length; // Total AAD length +} rsip_chacha20_poly1305_handle_t; + +/** Working area for SHA functions. DO NOT MODIFY. */ +typedef struct st_rsip_sha_handle +{ + rsip_hash_type_t type; // Hash type + uint8_t buffer[RSIP_PRV_BYTE_SIZE_SHA_BLOCK_BUF]; // Stored message + uint32_t buffered_length; // Buffered message length + uint32_t total_length; // Total message length input to primitive + uint32_t block_size; // Block size + uint32_t internal_state[RSIP_PRV_WORD_SIZE_SHA_INTERNAL_STATE_BUF]; // Internal state + rsip_user_handle_state_t handle_state; // Handle state +} rsip_sha_handle_t; + +/** Working area for HMAC functions. DO NOT MODIFY. */ +typedef struct st_rsip_hmac_handle +{ + rsip_wrapped_key_t wrapped_key; // Wrapped key + uint8_t wrapped_key_value[RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_HMAC_BUF]; // Wrapped key value + uint8_t buffer[RSIP_PRV_BYTE_SIZE_HMAC_BLOCK_BUF]; // Stored message + uint32_t buffered_length; // Buffered message length + uint32_t total_length; // Total message length input to primitive + uint32_t block_size; // Block size + uint32_t internal_state[RSIP_PRV_WORD_SIZE_HMAC_INTERNAL_STATE_BUF]; // Internal state + rsip_user_handle_state_t handle_state; // Handle state +} rsip_hmac_handle_t; + +/** Working area for KDF SHA functions. DO NOT MODIFY. */ +typedef struct st_rsip_kdf_sha_handle +{ + rsip_hash_type_t type; // Hash type + uint8_t buffer1[4]; // Stored message1 + uint32_t buffered_length1; // Buffered message length1 + uint8_t buffer2[RSIP_PRV_BYTE_SIZE_KDF_SHA_BLOCK_BUF]; // Stored message2 + uint32_t buffered_length2; // Buffered message length2 + uint32_t total_length; // Total message length input to primitive + uint32_t block_size; // Block size + uint32_t internal_state[RSIP_PRV_WORD_SIZE_SHA_INTERNAL_STATE_BUF]; // Internal state + rsip_user_handle_state_t handle_state; // Handle state + + uint8_t wrapped_msg[RSIP_PRV_BYTE_SIZE_KDF_WRAPPED_MSG_BUF]; // Wrapped message + uint32_t wrapped_msg_length; // Wrapped message length + uint32_t actual_wrapped_msg_length; // Actual wrapped message length +} rsip_kdf_sha_handle_t; + +/** Working area for KDF HMAC functions. DO NOT MODIFY. */ +typedef struct st_rsip_kdf_hmac_handle +{ + rsip_wrapped_key_t wrapped_key; // Wrapped key + uint8_t wrapped_key_value[RSIP_PRV_BYTE_SIZE_WRAPPED_KEY_KDF_HMAC_BUF]; // Wrapped key value + uint8_t buffer[RSIP_PRV_BYTE_SIZE_KDF_HMAC_BLOCK_BUF]; // Stored message + uint32_t buffered_length; // Buffered message length + uint32_t total_length; // Total message length input to primitive + uint32_t block_size; // Block size + uint32_t internal_state[RSIP_PRV_WORD_SIZE_HMAC_INTERNAL_STATE_BUF]; // Internal state + rsip_user_handle_state_t handle_state; // Handle state + + uint8_t wrapped_msg[RSIP_PRV_BYTE_SIZE_KDF_WRAPPED_MSG_BUF]; // Wrapped message + uint32_t wrapped_msg_length; // Wrapped message length + uint32_t actual_wrapped_msg_length; // Actual wrapped message length +} rsip_kdf_hmac_handle_t; + +/** Verified certificate information */ +typedef struct st_rsip_verified_cert_info +{ + uint8_t value[RSIP_PRV_BYTE_SIZE_PKI_ENC_CERT_INFO]; +} rsip_verified_cert_info_t; + +/** Wrapped ECDH secret structure for ECDH and KDF APIs. */ +typedef struct st_rsip_wrapped_secret +{ + uint8_t type; // Internal key type ID + uint8_t info[3]; // Reserved area + uint8_t value[RSIP_PRV_BYTE_SIZE_ECDH_WRAPPED_SECRET_BUF]; // Wrapped secret +} rsip_wrapped_secret_t; + +/* Working area for RSIP cryptographic algorithms. This union is included in private control block. */ +typedef union u_rsip_handle +{ + rsip_aes_cipher_handle_t aes_cipher; // AES block cipher + rsip_aes_gcm_handle_t aes_gcm; // AES-GCM + rsip_aes_ccm_handle_t aes_ccm; // AES-CCM + rsip_aes_cmac_handle_t aes_cmac; // AES-CMAC + rsip_chacha20_handle_t chacha20; // ChaCha20 + rsip_chacha20_poly1305_handle_t chacha20_poly1305; // ChaCha20-Poly1305 + rsip_sha_handle_t sha; // SHA + rsip_hmac_handle_t hmac; // HMAC + rsip_kdf_sha_handle_t kdf_sha; // KDF SHA + rsip_kdf_hmac_handle_t kdf_hmac; // KDF HMAC +} rsip_handle_t; + +/* State that specifies functions that can be called next */ +typedef enum e_rsip_state +{ + RSIP_STATE_MAIN, // Main + RSIP_STATE_AES_CIPHER, // AES-ECB, AES-CBC, AES-CTR + RSIP_STATE_AES_XTS_UPDATE, // XTS-AES update + RSIP_STATE_AES_XTS_FINISH, // XTS-AES finalization + RSIP_STATE_AES_GCM_ENC_UPDATE_AAD, // AES-GCM encryption, AAD input + RSIP_STATE_AES_GCM_ENC_UPDATE_TEXT, // AES-GCM encryption, plaintext/ciphertext input + RSIP_STATE_AES_GCM_DEC_UPDATE_AAD, // AES-GCM decryption, AAD input + RSIP_STATE_AES_GCM_DEC_UPDATE_TEXT, // AES-GCM decryption, plaintext/ciphertext input + RSIP_STATE_AES_CCM_ENC_SET_LENGTH, // AES-CCM encryption, length setting + RSIP_STATE_AES_CCM_ENC_UPDATE_AAD, // AES-CCM encryption, AAD input + RSIP_STATE_AES_CCM_ENC_UPDATE_TEXT, // AES-CCM encryption, plaintext/ciphertext input + RSIP_STATE_AES_CCM_ENC_FINISH, // AES-CCM encryption, finish + RSIP_STATE_AES_CCM_DEC_SET_LENGTH, // AES-CCM decryption, length setting + RSIP_STATE_AES_CCM_DEC_UPDATE_AAD, // AES-CCM decryption, AAD input + RSIP_STATE_AES_CCM_DEC_UPDATE_TEXT, // AES-CCM decryption, plaintext/ciphertext input + RSIP_STATE_AES_CCM_DEC_VERI, // AES-CCM encryption, verification + RSIP_STATE_AES_CMAC, // AES-CMAC + RSIP_STATE_CHACHA, // ChaCha20 + RSIP_STATE_CHACHA_POLY_ENC_UPDATE_AAD, // ChaCha20-Poly1305 encryption, AAD input + RSIP_STATE_CHACHA_POLY_ENC_UPDATE_TEXT, // ChaCha20-Poly1305 encryption, plaintext/ciphertext input + RSIP_STATE_CHACHA_POLY_DEC_UPDATE_AAD, // ChaCha20-Poly1305 decryption, AAD input + RSIP_STATE_CHACHA_POLY_DEC_UPDATE_TEXT, // ChaCha20-Poly1305 decryption, plaintext/ciphertext input + RSIP_STATE_SHA, // SHA + RSIP_STATE_HMAC, // HMAC + RSIP_STATE_KDF_SHA, // KDF SHA + RSIP_STATE_KDF_HMAC, // KDF HMAC +} rsip_state_t; + +/** RSIP private control block. DO NOT MODIFY. Initialization occurs when R_RSIP_Open() is called. */ +typedef struct st_rsip_instance_ctrl +{ + uint32_t open; // Indicates whether the open() API has been successfully + rsip_cfg_t const * p_cfg; // Pointer to the configuration block + rsip_handle_t handle; // Handle of algorithms that cannot be suspended + rsip_state_t state; // Flags to limit the next API to call + + rsip_verified_cert_info_t pki_verified_cert_info; // Verified certificate info +} rsip_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const rsip_api_t g_rsip_on_rsip; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +/* r_rsip.c */ +fsp_err_t R_RSIP_Open(rsip_ctrl_t * const p_ctrl, rsip_cfg_t const * const p_cfg); +fsp_err_t R_RSIP_Close(rsip_ctrl_t * const p_ctrl); +fsp_err_t R_RSIP_RandomNumberGenerate(rsip_ctrl_t * const p_ctrl, uint8_t * const p_random); +fsp_err_t R_RSIP_KeyGenerate(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t * const p_wrapped_key); +fsp_err_t R_RSIP_KeyPairGenerate(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t * const p_wrapped_public_key, + rsip_wrapped_key_t * const p_wrapped_private_key); +fsp_err_t R_RSIP_EncryptedKeyWrap(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_key_update_key, + void const * const p_initial_vector, + void const * const p_encrypted_key, + rsip_wrapped_key_t * const p_wrapped_key); +fsp_err_t R_RSIP_RFC3394_KeyWrap(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_kek, + rsip_wrapped_key_t const * const p_wrapped_target_key, + uint8_t * const p_rfc3394_wrapped_target_key); +fsp_err_t R_RSIP_RFC3394_KeyUnwrap(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_kek, + uint8_t const * const p_rfc3394_wrapped_target_key, + rsip_wrapped_key_t * const p_wrapped_target_key); +fsp_err_t R_RSIP_PublicKeyExport(rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t * const p_raw_public_key); + +/* r_rsip_aes.c */ +fsp_err_t R_RSIP_AES_Cipher_Init(rsip_ctrl_t * const p_ctrl, + rsip_aes_cipher_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_initial_vector); +fsp_err_t R_RSIP_AES_Cipher_Update(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_input, + uint8_t * const p_output, + uint32_t const length); +fsp_err_t R_RSIP_AES_Cipher_Finish(rsip_ctrl_t * const p_ctrl); +fsp_err_t R_RSIP_AES_AEAD_Init(rsip_ctrl_t * const p_ctrl, + rsip_aes_aead_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_nonce, + uint32_t const nonce_length); +fsp_err_t R_RSIP_AES_AEAD_LengthsSet(rsip_ctrl_t * const p_ctrl, + uint32_t const total_aad_length, + uint32_t const total_text_length, + uint32_t const tag_length); +fsp_err_t R_RSIP_AES_AEAD_AADUpdate(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_aad, uint32_t const aad_length); +fsp_err_t R_RSIP_AES_AEAD_Update(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length); +fsp_err_t R_RSIP_AES_AEAD_Finish(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag); +fsp_err_t R_RSIP_AES_AEAD_Verify(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length); + +fsp_err_t R_RSIP_AES_MAC_Init(rsip_ctrl_t * const p_ctrl, + rsip_aes_mac_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key); +fsp_err_t R_RSIP_AES_MAC_Update(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_message, + uint32_t const message_length); +fsp_err_t R_RSIP_AES_MAC_SignFinish(rsip_ctrl_t * const p_ctrl, uint8_t * const p_mac); +fsp_err_t R_RSIP_AES_MAC_VerifyFinish(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_mac, + uint32_t const mac_length); + +/* r_rsip_chacha.c */ +fsp_err_t R_RSIP_ChaCha20_Init(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_nonce, + uint32_t const counter); +fsp_err_t R_RSIP_ChaCha20_Update(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length); +fsp_err_t R_RSIP_ChaCha20_Finish(rsip_ctrl_t * const p_ctrl, uint8_t * const p_output, + uint32_t * const p_output_length); +fsp_err_t R_RSIP_ChaCha20_Poly1305_Init(rsip_ctrl_t * const p_ctrl, + rsip_chacha_poly_mode_t const mode, + rsip_wrapped_key_t const * const p_wrapped_key, + uint8_t const * const p_nonce, + uint32_t const nonce_length); +fsp_err_t R_RSIP_ChaCha20_Poly1305_AADUpdate(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_aad, + uint32_t const aad_length); +fsp_err_t R_RSIP_ChaCha20_Poly1305_Update(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_input, + uint32_t const input_length, + uint8_t * const p_output, + uint32_t * const p_output_length); +fsp_err_t R_RSIP_ChaCha20_Poly1305_Finish(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t * const p_tag); +fsp_err_t R_RSIP_ChaCha20_Poly1305_Verify(rsip_ctrl_t * const p_ctrl, + uint8_t * const p_output, + uint32_t * const p_output_length, + uint8_t const * const p_tag, + uint32_t const tag_length); + +/* r_rsip_ecc.c */ +fsp_err_t R_RSIP_ECDSA_Sign(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_hash, + uint8_t * const p_signature); +fsp_err_t R_RSIP_ECDSA_Verify(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_hash, + uint8_t const * const p_signature); +fsp_err_t R_RSIP_PureEdDSA_Sign(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_message, + uint64_t const message_length, + uint8_t * const p_signature); +fsp_err_t R_RSIP_PureEdDSA_Verify(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_message, + uint64_t const message_length, + uint8_t const * const p_signature); +fsp_err_t R_RSIP_ECDH_KeyAgree(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_wrapped_secret_t * const p_wrapped_secret); +fsp_err_t R_RSIP_ECDH_PlainKeyAgree(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_plain_public_key, + rsip_wrapped_secret_t * const p_wrapped_secret); + +/* r_rsip_rsa.c */ +fsp_err_t R_RSIP_RSA_Encrypt(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, + uint8_t * const p_cipher); +fsp_err_t R_RSIP_RSA_Decrypt(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_cipher, + uint8_t * const p_plain); +fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Encrypt(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_plain, + uint32_t const plain_length, + uint8_t * const p_cipher); +fsp_err_t R_RSIP_RSAES_PKCS1_V1_5_Decrypt(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + uint8_t const * const p_cipher, + uint8_t * const p_plain, + uint32_t * const p_plain_length, + uint32_t const plain_buffer_length); +fsp_err_t R_RSIP_RSAES_OAEP_Encrypt(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint8_t const * const p_label, + uint32_t const label_length, + uint8_t const * const p_plain, + uint32_t const plain_length, + uint8_t * const p_cipher); +fsp_err_t R_RSIP_RSAES_OAEP_Decrypt(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint8_t const * const p_label, + uint32_t const label_length, + uint8_t const * const p_cipher, + uint8_t * const p_plain, + uint32_t * const p_plain_length, + uint32_t const plain_buffer_length); +fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Sign(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t * const p_signature); +fsp_err_t R_RSIP_RSASSA_PKCS1_V1_5_Verify(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t const * const p_signature); +fsp_err_t R_RSIP_RSASSA_PSS_Sign(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_private_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_hash, + uint8_t * const p_signature); +fsp_err_t R_RSIP_RSASSA_PSS_Verify(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_hash, + uint8_t const * const p_signature); + +/* r_rsip_sha.c */ +fsp_err_t R_RSIP_SHA_Compute(rsip_ctrl_t * const p_ctrl, + rsip_hash_type_t const hash_type, + uint8_t const * const p_message, + uint32_t const message_length, + uint8_t * const p_digest); +fsp_err_t R_RSIP_SHA_Init(rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type); +fsp_err_t R_RSIP_SHA_Update(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, uint32_t const message_length); +fsp_err_t R_RSIP_SHA_Finish(rsip_ctrl_t * const p_ctrl, uint8_t * const p_digest); +fsp_err_t R_RSIP_SHA_Suspend(rsip_ctrl_t * const p_ctrl, rsip_sha_handle_t * const p_handle); +fsp_err_t R_RSIP_SHA_Resume(rsip_ctrl_t * const p_ctrl, rsip_sha_handle_t const * const p_handle); +fsp_err_t R_RSIP_HMAC_Compute(rsip_ctrl_t * const p_ctrl, + const rsip_wrapped_key_t * p_wrapped_key, + uint8_t const * const p_message, + uint32_t const message_length, + uint8_t * const p_mac); +fsp_err_t R_RSIP_HMAC_Verify(rsip_ctrl_t * const p_ctrl, + const rsip_wrapped_key_t * p_wrapped_key, + uint8_t const * const p_message, + uint32_t const message_length, + uint8_t const * const p_mac, + uint32_t const mac_length); +fsp_err_t R_RSIP_HMAC_Init(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_key); +fsp_err_t R_RSIP_HMAC_Update(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_message, + uint32_t const message_length); +fsp_err_t R_RSIP_HMAC_SignFinish(rsip_ctrl_t * const p_ctrl, uint8_t * const p_mac); +fsp_err_t R_RSIP_HMAC_VerifyFinish(rsip_ctrl_t * const p_ctrl, uint8_t const * const p_mac, uint32_t const mac_length); +fsp_err_t R_RSIP_HMAC_Suspend(rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_t * const p_handle); +fsp_err_t R_RSIP_HMAC_Resume(rsip_ctrl_t * const p_ctrl, rsip_hmac_handle_t const * const p_handle); + +/* r_rsip_pki.c */ +fsp_err_t R_RSIP_PKI_ECDSA_CertVerify(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + uint8_t const * const p_hash, + uint8_t const * const p_signature); +fsp_err_t R_RSIP_PKI_RSASSA_PKCS1_V1_5_CertVerify(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + uint8_t const * const p_hash, + uint8_t const * const p_signature); +fsp_err_t R_RSIP_PKI_RSASSA_PSS_CertVerify(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_key_t const * const p_wrapped_public_key, + rsip_hash_type_t const hash_function, + rsip_mgf_type_t const mask_generation_function, + uint32_t const salt_length, + uint8_t const * const p_hash, + uint8_t const * const p_signature); +fsp_err_t R_RSIP_PKI_VerifiedCertInfoExport(rsip_ctrl_t * const p_ctrl, + rsip_verified_cert_info_t * const p_verified_cert_info); +fsp_err_t R_RSIP_PKI_VerifiedCertInfoImport(rsip_ctrl_t * const p_ctrl, + rsip_verified_cert_info_t const * const p_verified_cert_info); +fsp_err_t R_RSIP_PKI_CertKeyImport(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_cert, + uint32_t const cert_length, + uint8_t const * const p_key_param1, + uint32_t const key_param1_length, + uint8_t const * const p_key_param2, + uint32_t const key_param2_length, + rsip_hash_type_t const hash_function, + rsip_wrapped_key_t * const p_wrapped_public_key); + +/* r_rsip_kdf.c */ +fsp_err_t R_RSIP_KDF_SHA_Init(rsip_ctrl_t * const p_ctrl, rsip_hash_type_t const hash_type); +fsp_err_t R_RSIP_KDF_SHA_ECDHSecretUpdate(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_t const * const p_wrapped_secret); +fsp_err_t R_RSIP_KDF_SHA_Update(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_message, + uint32_t const message_length); +fsp_err_t R_RSIP_KDF_SHA_Finish(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t * const p_wrapped_dkm); +fsp_err_t R_RSIP_KDF_SHA_Suspend(rsip_ctrl_t * const p_ctrl, rsip_kdf_sha_handle_t * const p_handle); +fsp_err_t R_RSIP_KDF_SHA_Resume(rsip_ctrl_t * const p_ctrl, rsip_kdf_sha_handle_t const * const p_handle); +fsp_err_t R_RSIP_KDF_HMAC_DKMKeyImport(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_dkm_t const * const p_wrapped_dkm, + uint32_t const key_length, + rsip_wrapped_key_t * const p_wrapped_key); +fsp_err_t R_RSIP_KDF_HMAC_ECDHSecretKeyImport(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_t const * const p_wrapped_secret, + rsip_wrapped_key_t * const p_wrapped_key); +fsp_err_t R_RSIP_KDF_HMAC_Init(rsip_ctrl_t * const p_ctrl, rsip_wrapped_key_t const * const p_wrapped_key); +fsp_err_t R_RSIP_KDF_HMAC_DKMUpdate(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t const * const p_wrapped_dkm); +fsp_err_t R_RSIP_KDF_HMAC_ECDHSecretUpdate(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_secret_t const * const p_wrapped_secret); +fsp_err_t R_RSIP_KDF_HMAC_Update(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_message, + uint32_t const message_length); +fsp_err_t R_RSIP_KDF_HMAC_SignFinish(rsip_ctrl_t * const p_ctrl, rsip_wrapped_dkm_t * const p_wrapped_dkm); +fsp_err_t R_RSIP_KDF_HMAC_Suspend(rsip_ctrl_t * const p_ctrl, rsip_kdf_hmac_handle_t * const p_handle); +fsp_err_t R_RSIP_KDF_HMAC_Resume(rsip_ctrl_t * const p_ctrl, rsip_kdf_hmac_handle_t const * const p_handle); +fsp_err_t R_RSIP_KDF_DKMConcatenate(rsip_wrapped_dkm_t * const p_wrapped_dkm1, + rsip_wrapped_dkm_t const * const p_wrapped_dkm2, + uint32_t const wrapped_dkm1_buffer_length); +fsp_err_t R_RSIP_KDF_DerivedKeyImport(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_dkm_t const * const p_wrapped_dkm, + uint32_t const position, + rsip_wrapped_key_t * const p_wrapped_key); +fsp_err_t R_RSIP_KDF_DerivedIVWrap(rsip_ctrl_t * const p_ctrl, + rsip_wrapped_dkm_t const * const p_wrapped_dkm, + rsip_initial_vector_type_t const initial_vector_type, + uint32_t const position, + uint8_t const * const p_tls_sequence_num, + uint8_t * const p_wrapped_initial_vector); + +/* r_rsip_otf.c */ +fsp_err_t R_RSIP_OTF_Init(rsip_ctrl_t * const p_ctrl, + rsip_otf_channel_t const channel, + rsip_wrapped_key_t * const p_wrapped_key, + uint8_t const * const p_seed); + +/* r_rsip_ra.c */ +fsp_err_t R_RSIP_FSBL_OEM_BL_Digest_Generate(rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_key_cert, + uint32_t const key_cert_max_length, + uint8_t const * const p_code_cert, + uint32_t const code_cert_max_length, + uint32_t * const p_mac); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_RSIP_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_addr.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_addr.h new file mode 100644 index 0000000000..de30760ed8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_addr.h @@ -0,0 +1,17 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_ADDR_H +#define R_RSIP_ADDR_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define RSIP_PRV_ADDR_BASE (0x403B0000UL) +#define RSIP_PRV_ADDR_TYPE (5U) +#define RSIP_PRV_HASH_IP_TYPE (5U) + +#endif /* R_RSIP_ADDR_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.c new file mode 100644 index 0000000000..438e81c122 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.c @@ -0,0 +1,297 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +uint32_t S_RAM[RSIP_PRV_WORD_SIZE_S_RAM]; +uint32_t S_HEAP[RSIP_PRV_WORD_SIZE_S_HEAP]; +uint32_t const * S_INST2; +uint32_t INST_DATA_SIZE; + +uint32_t const DomainParam_NIST_P192[] = +{ + BSWAP_32BIG_C(0x8d739360U), BSWAP_32BIG_C(0xfd7ede3fU), BSWAP_32BIG_C(0x669521c5U), BSWAP_32BIG_C(0xb8341cbbU), + BSWAP_32BIG_C(0x140deb42U), BSWAP_32BIG_C(0x0c0a1fb4U), BSWAP_32BIG_C(0x531044d2U), BSWAP_32BIG_C(0xfacc28dcU), + BSWAP_32BIG_C(0x85a2aafeU), BSWAP_32BIG_C(0x37eb9074U), BSWAP_32BIG_C(0xf7b22873U), BSWAP_32BIG_C(0xfbcc9317U), + BSWAP_32BIG_C(0x863ef860U), BSWAP_32BIG_C(0xdeb83a05U), BSWAP_32BIG_C(0x81e89b95U), BSWAP_32BIG_C(0xe65a8fe9U), + BSWAP_32BIG_C(0x62d5e768U), BSWAP_32BIG_C(0x7cda9337U), BSWAP_32BIG_C(0x5c94f169U), BSWAP_32BIG_C(0x45cb7864U), + BSWAP_32BIG_C(0x36b0623bU), BSWAP_32BIG_C(0x2d4ef58aU), BSWAP_32BIG_C(0x224f19cdU), BSWAP_32BIG_C(0xe90c73a1U), + BSWAP_32BIG_C(0xc45844d2U), BSWAP_32BIG_C(0xe82fa9b6U), BSWAP_32BIG_C(0xc58fbdebU), BSWAP_32BIG_C(0xce874ce4U), + BSWAP_32BIG_C(0x3f5df995U), BSWAP_32BIG_C(0x362c67aeU), BSWAP_32BIG_C(0xf6d1af40U), BSWAP_32BIG_C(0xc722846eU), + BSWAP_32BIG_C(0xae2b5b3cU), BSWAP_32BIG_C(0x09f8875cU), BSWAP_32BIG_C(0x7dae67c6U), BSWAP_32BIG_C(0x1d336db2U), + BSWAP_32BIG_C(0x9a172c90U), BSWAP_32BIG_C(0x1b4eb189U), BSWAP_32BIG_C(0xedf86918U), BSWAP_32BIG_C(0xa9efc2f9U), + BSWAP_32BIG_C(0x31f5f50eU), BSWAP_32BIG_C(0x717e7940U), BSWAP_32BIG_C(0x63fc2af0U), BSWAP_32BIG_C(0x98ecb038U), + BSWAP_32BIG_C(0x1bcce632U), BSWAP_32BIG_C(0x5632930eU), BSWAP_32BIG_C(0xd42e731cU), BSWAP_32BIG_C(0x533b5c2dU), + BSWAP_32BIG_C(0x3074d94dU), BSWAP_32BIG_C(0xb791dba2U), BSWAP_32BIG_C(0x5fe03498U), BSWAP_32BIG_C(0x884e5088U), + BSWAP_32BIG_C(0x2eec4a56U), BSWAP_32BIG_C(0xc1fe2fa5U), BSWAP_32BIG_C(0x8a336c66U), BSWAP_32BIG_C(0xef926760U), + BSWAP_32BIG_C(0xff460d6fU), BSWAP_32BIG_C(0x5c39ce75U), BSWAP_32BIG_C(0x33b99bdbU), BSWAP_32BIG_C(0x68d187d0U), + BSWAP_32BIG_C(0x4a888212U), BSWAP_32BIG_C(0xfbdd931dU), BSWAP_32BIG_C(0x31f200deU), BSWAP_32BIG_C(0x2d0a66b6U), + BSWAP_32BIG_C(0x05df0ad8U), BSWAP_32BIG_C(0xa865368fU), BSWAP_32BIG_C(0x65351baaU), BSWAP_32BIG_C(0x7c5aea69U), + BSWAP_32BIG_C(0x0f3c5f06U), BSWAP_32BIG_C(0x62e498a1U), BSWAP_32BIG_C(0xa2d9d94dU), BSWAP_32BIG_C(0x58194cdaU), +}; + +uint32_t const DomainParam_NIST_P224[] = +{ + BSWAP_32BIG_C(0x0a1c9774U), BSWAP_32BIG_C(0x7dda462cU), BSWAP_32BIG_C(0x98395868U), BSWAP_32BIG_C(0x28cbc3c3U), + BSWAP_32BIG_C(0x0a8df02aU), BSWAP_32BIG_C(0x9c8abdb0U), BSWAP_32BIG_C(0x6bee83a7U), BSWAP_32BIG_C(0xdde17559U), + BSWAP_32BIG_C(0x94cfcb10U), BSWAP_32BIG_C(0xd926d09bU), BSWAP_32BIG_C(0x61eb5b97U), BSWAP_32BIG_C(0x9c2dad08U), + BSWAP_32BIG_C(0xd232f14aU), BSWAP_32BIG_C(0x8fb72c2cU), BSWAP_32BIG_C(0xfc44051cU), BSWAP_32BIG_C(0x93280bf0U), + BSWAP_32BIG_C(0x5463afe9U), BSWAP_32BIG_C(0x94b751dbU), BSWAP_32BIG_C(0xb7d5024aU), BSWAP_32BIG_C(0x177ce72aU), + BSWAP_32BIG_C(0x18e951a6U), BSWAP_32BIG_C(0xb46fb71cU), BSWAP_32BIG_C(0x2186414bU), BSWAP_32BIG_C(0x19eb64b0U), + BSWAP_32BIG_C(0x5ee1ee19U), BSWAP_32BIG_C(0x1ae0d537U), BSWAP_32BIG_C(0x2b2e6443U), BSWAP_32BIG_C(0x55613a15U), + BSWAP_32BIG_C(0xbc092520U), BSWAP_32BIG_C(0xc70f8f5bU), BSWAP_32BIG_C(0xd1ef9455U), BSWAP_32BIG_C(0x26fb4e18U), + BSWAP_32BIG_C(0x5bf0c079U), BSWAP_32BIG_C(0x080ca300U), BSWAP_32BIG_C(0x8ccece0bU), BSWAP_32BIG_C(0xa6886a21U), + BSWAP_32BIG_C(0xb2c207f2U), BSWAP_32BIG_C(0xe323f8b7U), BSWAP_32BIG_C(0xfbd9e54aU), BSWAP_32BIG_C(0x43f5eaafU), + BSWAP_32BIG_C(0xab94a327U), BSWAP_32BIG_C(0xcbdaf526U), BSWAP_32BIG_C(0xf3eaefd5U), BSWAP_32BIG_C(0x6647c5dbU), + BSWAP_32BIG_C(0xf5f0dc46U), BSWAP_32BIG_C(0x859b555bU), BSWAP_32BIG_C(0x059b78b3U), BSWAP_32BIG_C(0x7d0219eaU), + BSWAP_32BIG_C(0xab7735b5U), BSWAP_32BIG_C(0x957cfa54U), BSWAP_32BIG_C(0x8b6d9baeU), BSWAP_32BIG_C(0xc0b21767U), + BSWAP_32BIG_C(0x859449acU), BSWAP_32BIG_C(0x8fc06db5U), BSWAP_32BIG_C(0x192a96dbU), BSWAP_32BIG_C(0xed6dcbadU), + BSWAP_32BIG_C(0x110af69cU), BSWAP_32BIG_C(0x68d615d6U), BSWAP_32BIG_C(0x7c9c5436U), BSWAP_32BIG_C(0xc0ac8afeU), + BSWAP_32BIG_C(0x28780209U), BSWAP_32BIG_C(0x9fc5d609U), BSWAP_32BIG_C(0x7eee921dU), BSWAP_32BIG_C(0xa984f93eU), + BSWAP_32BIG_C(0x28f2539fU), BSWAP_32BIG_C(0x23d5c67eU), BSWAP_32BIG_C(0x62bba4abU), BSWAP_32BIG_C(0x75339f7bU), + BSWAP_32BIG_C(0x801a6bdfU), BSWAP_32BIG_C(0xc59fd5eeU), BSWAP_32BIG_C(0x00e4ab2cU), BSWAP_32BIG_C(0xebbe5dbcU), +}; + +uint32_t const DomainParam_NIST_P256[] = +{ + BSWAP_32BIG_C(0x035ed43bU), BSWAP_32BIG_C(0x398dbc01U), BSWAP_32BIG_C(0x9109272cU), BSWAP_32BIG_C(0x3f7d6b72U), + BSWAP_32BIG_C(0x28606f3cU), BSWAP_32BIG_C(0xdb667ff2U), BSWAP_32BIG_C(0x0d5aee59U), BSWAP_32BIG_C(0x2ae099c7U), + BSWAP_32BIG_C(0xf7a3fb8eU), BSWAP_32BIG_C(0x9c6f1282U), BSWAP_32BIG_C(0x0c1cac92U), BSWAP_32BIG_C(0x85281624U), + BSWAP_32BIG_C(0x46126296U), BSWAP_32BIG_C(0x8638b754U), BSWAP_32BIG_C(0x6c5bffc3U), BSWAP_32BIG_C(0x1c6f0d31U), + BSWAP_32BIG_C(0x6f6e4db7U), BSWAP_32BIG_C(0x70c024c1U), BSWAP_32BIG_C(0x4c3f1aa2U), BSWAP_32BIG_C(0x075d1a79U), + BSWAP_32BIG_C(0x2770976fU), BSWAP_32BIG_C(0x921ca8d1U), BSWAP_32BIG_C(0x5a912313U), BSWAP_32BIG_C(0x44814876U), + BSWAP_32BIG_C(0x1adc96d6U), BSWAP_32BIG_C(0x3c969ec2U), BSWAP_32BIG_C(0x0dcdb2ddU), BSWAP_32BIG_C(0x212cc108U), + BSWAP_32BIG_C(0xe82419d5U), BSWAP_32BIG_C(0x8342e6c2U), BSWAP_32BIG_C(0x6076dbe3U), BSWAP_32BIG_C(0xaedeeb8eU), + BSWAP_32BIG_C(0x8d2c9fddU), BSWAP_32BIG_C(0x028d7dadU), BSWAP_32BIG_C(0xe9b5b8e5U), BSWAP_32BIG_C(0xd1e13e7bU), + BSWAP_32BIG_C(0x723e3beaU), BSWAP_32BIG_C(0x9d2939c5U), BSWAP_32BIG_C(0x02a42453U), BSWAP_32BIG_C(0x17c7bc07U), + BSWAP_32BIG_C(0x9027e99fU), BSWAP_32BIG_C(0x65352bd6U), BSWAP_32BIG_C(0x1bba4a2dU), BSWAP_32BIG_C(0xb31fe39cU), + BSWAP_32BIG_C(0x2cbc4542U), BSWAP_32BIG_C(0xe9d4ce5fU), BSWAP_32BIG_C(0xfef4af1cU), BSWAP_32BIG_C(0x44bdf683U), + BSWAP_32BIG_C(0xe1affc99U), BSWAP_32BIG_C(0x4fe934cfU), BSWAP_32BIG_C(0x77544cbcU), BSWAP_32BIG_C(0x9ff7d5efU), + BSWAP_32BIG_C(0xe3604ebbU), BSWAP_32BIG_C(0x45f03e92U), BSWAP_32BIG_C(0xd258582dU), BSWAP_32BIG_C(0x9c807d86U), + BSWAP_32BIG_C(0xbdc6a8d5U), BSWAP_32BIG_C(0xa3b21009U), BSWAP_32BIG_C(0x23725fbcU), BSWAP_32BIG_C(0x1d067998U), + BSWAP_32BIG_C(0xda886eb9U), BSWAP_32BIG_C(0xb53796dbU), BSWAP_32BIG_C(0x2caba848U), BSWAP_32BIG_C(0xb371ebb0U), + BSWAP_32BIG_C(0x607f2890U), BSWAP_32BIG_C(0x2c9f8d55U), BSWAP_32BIG_C(0x990ac425U), BSWAP_32BIG_C(0xebfadd24U), + BSWAP_32BIG_C(0x2504fdaaU), BSWAP_32BIG_C(0xbad6b4b2U), BSWAP_32BIG_C(0x00f5cc25U), BSWAP_32BIG_C(0x45acaf5cU), +}; + +uint32_t const DomainParam_NIST_P384[] = +{ + BSWAP_32BIG_C(0x454baa1bU), BSWAP_32BIG_C(0x0e821ac1U), BSWAP_32BIG_C(0xdc20feeeU), BSWAP_32BIG_C(0xb83f8abdU), + BSWAP_32BIG_C(0x0b450ba5U), BSWAP_32BIG_C(0xee2ad4efU), BSWAP_32BIG_C(0xcec80fc9U), BSWAP_32BIG_C(0x0672b50bU), + BSWAP_32BIG_C(0x8c2f5f5fU), BSWAP_32BIG_C(0x17c1f268U), BSWAP_32BIG_C(0xe721d5dcU), BSWAP_32BIG_C(0x2af26798U), + BSWAP_32BIG_C(0x090c3649U), BSWAP_32BIG_C(0xcefa2599U), BSWAP_32BIG_C(0xd05c3e1cU), BSWAP_32BIG_C(0x098ec55bU), + BSWAP_32BIG_C(0x099e306bU), BSWAP_32BIG_C(0xc8862365U), BSWAP_32BIG_C(0x489507e8U), BSWAP_32BIG_C(0xc56d8e56U), + BSWAP_32BIG_C(0x9f80068dU), BSWAP_32BIG_C(0xb04512acU), BSWAP_32BIG_C(0x6aaeb283U), BSWAP_32BIG_C(0x7a16d53eU), + BSWAP_32BIG_C(0x0db27194U), BSWAP_32BIG_C(0x86260d17U), BSWAP_32BIG_C(0xab0da504U), BSWAP_32BIG_C(0x04048f61U), + BSWAP_32BIG_C(0x0982635dU), BSWAP_32BIG_C(0x6bafe52aU), BSWAP_32BIG_C(0xc726ae28U), BSWAP_32BIG_C(0x7f6c25a4U), + BSWAP_32BIG_C(0xe0d754b2U), BSWAP_32BIG_C(0xf926ceabU), BSWAP_32BIG_C(0x221eab95U), BSWAP_32BIG_C(0x0b094488U), + BSWAP_32BIG_C(0x71b2ea1fU), BSWAP_32BIG_C(0xa1f96200U), BSWAP_32BIG_C(0x6eb6e3b1U), BSWAP_32BIG_C(0xa5139a61U), + BSWAP_32BIG_C(0x57426fc5U), BSWAP_32BIG_C(0x2a7abbe7U), BSWAP_32BIG_C(0x5159a15aU), BSWAP_32BIG_C(0xd52fa7a4U), + BSWAP_32BIG_C(0xfbb72d4aU), BSWAP_32BIG_C(0x3d55ee79U), BSWAP_32BIG_C(0xd1c56bbaU), BSWAP_32BIG_C(0xfef0ef1bU), + BSWAP_32BIG_C(0x0debba5fU), BSWAP_32BIG_C(0x97177c11U), BSWAP_32BIG_C(0xe55fcc77U), BSWAP_32BIG_C(0xf4618e33U), + BSWAP_32BIG_C(0x3d0f68e9U), BSWAP_32BIG_C(0x05c30c1bU), BSWAP_32BIG_C(0xabaae2d3U), BSWAP_32BIG_C(0x1615d192U), + BSWAP_32BIG_C(0x0e4acc65U), BSWAP_32BIG_C(0x22a4ffc5U), BSWAP_32BIG_C(0xd5b03676U), BSWAP_32BIG_C(0x40946677U), + BSWAP_32BIG_C(0xfacdc777U), BSWAP_32BIG_C(0x4a67f35cU), BSWAP_32BIG_C(0x80963009U), BSWAP_32BIG_C(0xe848cc42U), + BSWAP_32BIG_C(0xe0d42183U), BSWAP_32BIG_C(0xaab1100cU), BSWAP_32BIG_C(0x4f4f5956U), BSWAP_32BIG_C(0x05528ef9U), + BSWAP_32BIG_C(0x1e70a8d1U), BSWAP_32BIG_C(0x24d90221U), BSWAP_32BIG_C(0xe7789138U), BSWAP_32BIG_C(0xb4a227eaU), + BSWAP_32BIG_C(0xfbdd2a0fU), BSWAP_32BIG_C(0x402cbab5U), BSWAP_32BIG_C(0x3b7f01a3U), BSWAP_32BIG_C(0x82f7e985U), + BSWAP_32BIG_C(0x6e5ffffeU), BSWAP_32BIG_C(0x2c53055fU), BSWAP_32BIG_C(0xd0395451U), BSWAP_32BIG_C(0x4895233bU), + BSWAP_32BIG_C(0xbb0ccecbU), BSWAP_32BIG_C(0x03f7d032U), BSWAP_32BIG_C(0x8fbc60fbU), BSWAP_32BIG_C(0x64f74639U), + BSWAP_32BIG_C(0x4a7b85ffU), BSWAP_32BIG_C(0x06c0c155U), BSWAP_32BIG_C(0x882880f8U), BSWAP_32BIG_C(0x86ba7841U), + BSWAP_32BIG_C(0xd8eed2a9U), BSWAP_32BIG_C(0xa70227daU), BSWAP_32BIG_C(0x58d9db68U), BSWAP_32BIG_C(0xd3400847U), + BSWAP_32BIG_C(0xe906f73bU), BSWAP_32BIG_C(0x3e16537fU), BSWAP_32BIG_C(0x93e84a9fU), BSWAP_32BIG_C(0x24efbb5eU), + BSWAP_32BIG_C(0xabde9092U), BSWAP_32BIG_C(0xfcab1f48U), BSWAP_32BIG_C(0x15b003f8U), BSWAP_32BIG_C(0xa3ffd73dU), + BSWAP_32BIG_C(0x659cbeb7U), BSWAP_32BIG_C(0x5df7929aU), BSWAP_32BIG_C(0x08200ae3U), BSWAP_32BIG_C(0xece2c7ccU), +}; + +uint32_t const DomainParam_NIST_P521[] = +{ + BSWAP_32BIG_C(0x7a249f9aU), BSWAP_32BIG_C(0xa02b4d76U), BSWAP_32BIG_C(0x45ae598eU), BSWAP_32BIG_C(0xea6bad10U), + BSWAP_32BIG_C(0x5796477cU), BSWAP_32BIG_C(0x2e42c734U), BSWAP_32BIG_C(0x46071abfU), BSWAP_32BIG_C(0x5dec4559U), + BSWAP_32BIG_C(0xa25e4aa4U), BSWAP_32BIG_C(0xb1f05f07U), BSWAP_32BIG_C(0x9fa87f1cU), BSWAP_32BIG_C(0x81e7d466U), + BSWAP_32BIG_C(0xb8ed9524U), BSWAP_32BIG_C(0x82de7b9cU), BSWAP_32BIG_C(0x93e73a2fU), BSWAP_32BIG_C(0xf52f0247U), + BSWAP_32BIG_C(0xa76e9d6eU), BSWAP_32BIG_C(0x5e5deb97U), BSWAP_32BIG_C(0xe345ae73U), BSWAP_32BIG_C(0x12975194U), + BSWAP_32BIG_C(0xe4be8c4eU), BSWAP_32BIG_C(0x99691e35U), BSWAP_32BIG_C(0xf1557973U), BSWAP_32BIG_C(0x829bd421U), + BSWAP_32BIG_C(0xda47480bU), BSWAP_32BIG_C(0xb049a32eU), BSWAP_32BIG_C(0xd1de53a1U), BSWAP_32BIG_C(0xcb6ca7fcU), + BSWAP_32BIG_C(0x32a5777dU), BSWAP_32BIG_C(0x268a501dU), BSWAP_32BIG_C(0x1bb6b947U), BSWAP_32BIG_C(0x9e56b5f2U), + BSWAP_32BIG_C(0xff561b0cU), BSWAP_32BIG_C(0x47efd961U), BSWAP_32BIG_C(0x9c63770dU), BSWAP_32BIG_C(0xf5c4b79bU), + BSWAP_32BIG_C(0x5eb8417cU), BSWAP_32BIG_C(0xbc7dd1dcU), BSWAP_32BIG_C(0xc06c8bc2U), BSWAP_32BIG_C(0x388f1042U), + BSWAP_32BIG_C(0x93703d42U), BSWAP_32BIG_C(0x2ad272ecU), BSWAP_32BIG_C(0x50ecccd3U), BSWAP_32BIG_C(0x0443f647U), + BSWAP_32BIG_C(0xcecf72aaU), BSWAP_32BIG_C(0xa98babd3U), BSWAP_32BIG_C(0x7cc05c6bU), BSWAP_32BIG_C(0x23c861b6U), + BSWAP_32BIG_C(0x227cc559U), BSWAP_32BIG_C(0xe6288893U), BSWAP_32BIG_C(0x7806f2dbU), BSWAP_32BIG_C(0xcac45daeU), + BSWAP_32BIG_C(0xdca55dd8U), BSWAP_32BIG_C(0x612fbc24U), BSWAP_32BIG_C(0xc0bb05cdU), BSWAP_32BIG_C(0xb95465c5U), + BSWAP_32BIG_C(0x3817299cU), BSWAP_32BIG_C(0x3981162eU), BSWAP_32BIG_C(0x28baff24U), BSWAP_32BIG_C(0xc0e2e107U), + BSWAP_32BIG_C(0x72e29fdfU), BSWAP_32BIG_C(0x90371d50U), BSWAP_32BIG_C(0x6d28466eU), BSWAP_32BIG_C(0xd3429dfaU), + BSWAP_32BIG_C(0xf455e0faU), BSWAP_32BIG_C(0xec8eac53U), BSWAP_32BIG_C(0x59bf3157U), BSWAP_32BIG_C(0x56487a6dU), + BSWAP_32BIG_C(0xcfa45250U), BSWAP_32BIG_C(0x4b3a84e9U), BSWAP_32BIG_C(0x761813e0U), BSWAP_32BIG_C(0x0b2dd569U), + BSWAP_32BIG_C(0x113b79dfU), BSWAP_32BIG_C(0x966c60b7U), BSWAP_32BIG_C(0x0be5ccb7U), BSWAP_32BIG_C(0xd1d63f28U), + BSWAP_32BIG_C(0xae0bd280U), BSWAP_32BIG_C(0x72306332U), BSWAP_32BIG_C(0x92b3f2d0U), BSWAP_32BIG_C(0xee95a228U), + BSWAP_32BIG_C(0x55181fbaU), BSWAP_32BIG_C(0xdecd4077U), BSWAP_32BIG_C(0xeae51cecU), BSWAP_32BIG_C(0x9508c693U), + BSWAP_32BIG_C(0xde21165dU), BSWAP_32BIG_C(0x11ce5305U), BSWAP_32BIG_C(0x4f3e737dU), BSWAP_32BIG_C(0x98190e93U), + BSWAP_32BIG_C(0xf6598bbdU), BSWAP_32BIG_C(0x047fbd98U), BSWAP_32BIG_C(0xf3a5a7c6U), BSWAP_32BIG_C(0x20e5fce1U), + BSWAP_32BIG_C(0x7c3d5ba0U), BSWAP_32BIG_C(0xd2dcedbdU), BSWAP_32BIG_C(0xa95c7e00U), BSWAP_32BIG_C(0xdea51b22U), + BSWAP_32BIG_C(0x5cff2ce2U), BSWAP_32BIG_C(0x7861e523U), BSWAP_32BIG_C(0xbb035506U), BSWAP_32BIG_C(0xf39b017aU), + BSWAP_32BIG_C(0x85ffef06U), BSWAP_32BIG_C(0x8c8c9328U), BSWAP_32BIG_C(0x5e19a690U), BSWAP_32BIG_C(0x679030dbU), + BSWAP_32BIG_C(0x49c5ed6dU), BSWAP_32BIG_C(0x7aa56b79U), BSWAP_32BIG_C(0x808728b0U), BSWAP_32BIG_C(0x3d0dabf3U), + BSWAP_32BIG_C(0xa9c12a00U), BSWAP_32BIG_C(0xd67ea366U), BSWAP_32BIG_C(0x528ad6a6U), BSWAP_32BIG_C(0x0a509f7fU), + BSWAP_32BIG_C(0x01ad0d7cU), BSWAP_32BIG_C(0x9269f954U), BSWAP_32BIG_C(0xf9201d43U), BSWAP_32BIG_C(0xb2a7e5e4U), + BSWAP_32BIG_C(0x93c9a417U), BSWAP_32BIG_C(0x7950d8f6U), BSWAP_32BIG_C(0x2794418aU), BSWAP_32BIG_C(0xa30be44bU), + BSWAP_32BIG_C(0x13a96875U), BSWAP_32BIG_C(0xac0c45b3U), BSWAP_32BIG_C(0x689ed97dU), BSWAP_32BIG_C(0xeba560cdU), + BSWAP_32BIG_C(0x9724a053U), BSWAP_32BIG_C(0xfd078f3dU), BSWAP_32BIG_C(0xe36865c0U), BSWAP_32BIG_C(0x590ad323U), + BSWAP_32BIG_C(0xb808c41bU), BSWAP_32BIG_C(0x1af855adU), BSWAP_32BIG_C(0x7c409673U), BSWAP_32BIG_C(0x8ad48e1eU), + BSWAP_32BIG_C(0x68a3678fU), BSWAP_32BIG_C(0xca2137a3U), BSWAP_32BIG_C(0x738d062cU), BSWAP_32BIG_C(0xd0ac4d97U), + BSWAP_32BIG_C(0xbeacf4baU), BSWAP_32BIG_C(0xa61c18ecU), BSWAP_32BIG_C(0xf0362fe1U), BSWAP_32BIG_C(0x18a61560U), + BSWAP_32BIG_C(0x40bc68afU), BSWAP_32BIG_C(0x5c2a7a03U), BSWAP_32BIG_C(0x2e183427U), BSWAP_32BIG_C(0x36eff8b9U), + BSWAP_32BIG_C(0xa5960827U), BSWAP_32BIG_C(0x9606d41bU), BSWAP_32BIG_C(0x4afb9a29U), BSWAP_32BIG_C(0x20b13d24U), + BSWAP_32BIG_C(0xbb41fd40U), BSWAP_32BIG_C(0x03482936U), BSWAP_32BIG_C(0x3e6e7557U), BSWAP_32BIG_C(0x0868bbc9U), + BSWAP_32BIG_C(0x1c886e71U), BSWAP_32BIG_C(0x39ecdb78U), BSWAP_32BIG_C(0xc6b983b6U), BSWAP_32BIG_C(0x560a12e3U), + BSWAP_32BIG_C(0xeca618ccU), BSWAP_32BIG_C(0x79ca754dU), BSWAP_32BIG_C(0x1a5b2c93U), BSWAP_32BIG_C(0x9c616568U), + BSWAP_32BIG_C(0xe8fb45a9U), BSWAP_32BIG_C(0x5e59a88aU), BSWAP_32BIG_C(0xe96c246aU), BSWAP_32BIG_C(0xd65aa43aU), + BSWAP_32BIG_C(0x8c1a5b55U), BSWAP_32BIG_C(0xbc379280U), BSWAP_32BIG_C(0xb9a30278U), BSWAP_32BIG_C(0xef0dba99U), +}; + +uint32_t const DomainParam_Ed25519[] = +{ + BSWAP_32BIG_C(0x7e954da9U), BSWAP_32BIG_C(0xa5a8035eU), BSWAP_32BIG_C(0x292f36b3U), BSWAP_32BIG_C(0xd86e2375U), + BSWAP_32BIG_C(0x7d7d7f8eU), BSWAP_32BIG_C(0x63969f29U), BSWAP_32BIG_C(0x44419852U), BSWAP_32BIG_C(0x3530be90U), + BSWAP_32BIG_C(0x4e22ac6aU), BSWAP_32BIG_C(0xc4ffd911U), BSWAP_32BIG_C(0x1c93b71eU), BSWAP_32BIG_C(0x626a2d7aU), + BSWAP_32BIG_C(0xdb5f29b6U), BSWAP_32BIG_C(0xa0ba4edaU), BSWAP_32BIG_C(0x26f76cccU), BSWAP_32BIG_C(0xbd8a5732U), + BSWAP_32BIG_C(0x892d6d53U), BSWAP_32BIG_C(0x730e15e5U), BSWAP_32BIG_C(0x9fb7daacU), BSWAP_32BIG_C(0x1b8837a6U), + BSWAP_32BIG_C(0x3da0e439U), BSWAP_32BIG_C(0xda7d1fd9U), BSWAP_32BIG_C(0xc576bf1fU), BSWAP_32BIG_C(0x01e2e938U), + BSWAP_32BIG_C(0xb25a5ce1U), BSWAP_32BIG_C(0xe21f906bU), BSWAP_32BIG_C(0xe12c5bdfU), BSWAP_32BIG_C(0xa8c47883U), + BSWAP_32BIG_C(0x17ff1a8dU), BSWAP_32BIG_C(0xf5af50c1U), BSWAP_32BIG_C(0x638fbc6eU), BSWAP_32BIG_C(0xaa75bec2U), + BSWAP_32BIG_C(0x32b84b8fU), BSWAP_32BIG_C(0xec076e46U), BSWAP_32BIG_C(0xb55dd881U), BSWAP_32BIG_C(0x1a9a8ba6U), + BSWAP_32BIG_C(0x3a71f8e0U), BSWAP_32BIG_C(0xb374a5ecU), BSWAP_32BIG_C(0x5ff7db04U), BSWAP_32BIG_C(0xd0752e14U), + BSWAP_32BIG_C(0x66e95c0dU), BSWAP_32BIG_C(0x833c6a12U), BSWAP_32BIG_C(0xd2b953d5U), BSWAP_32BIG_C(0x5e5651fbU), + BSWAP_32BIG_C(0xf9439fa0U), BSWAP_32BIG_C(0x253b7ad6U), BSWAP_32BIG_C(0x398b9033U), BSWAP_32BIG_C(0x1fa058b9U), + BSWAP_32BIG_C(0x05b0e08bU), BSWAP_32BIG_C(0x3f81f154U), BSWAP_32BIG_C(0xb4f6aa56U), BSWAP_32BIG_C(0x8d9c165dU), + BSWAP_32BIG_C(0xead6c0eaU), BSWAP_32BIG_C(0x671b37ebU), BSWAP_32BIG_C(0x96cce9a1U), BSWAP_32BIG_C(0x4d645c6fU), + BSWAP_32BIG_C(0xdfdbec79U), BSWAP_32BIG_C(0x29a1132eU), BSWAP_32BIG_C(0x7f17293bU), BSWAP_32BIG_C(0x95f3eeb6U), + BSWAP_32BIG_C(0x52f48b56U), BSWAP_32BIG_C(0x69f1c841U), BSWAP_32BIG_C(0xccc8bf93U), BSWAP_32BIG_C(0x7f64543dU), + BSWAP_32BIG_C(0xe82eea75U), BSWAP_32BIG_C(0x7e38faa3U), BSWAP_32BIG_C(0xad2ad1b5U), BSWAP_32BIG_C(0x17c1ed15U), + BSWAP_32BIG_C(0xd4f861beU), BSWAP_32BIG_C(0xfb198636U), BSWAP_32BIG_C(0x05a90426U), BSWAP_32BIG_C(0x6c87647cU), + BSWAP_32BIG_C(0x83b9b954U), BSWAP_32BIG_C(0x471059e9U), BSWAP_32BIG_C(0x98c34a13U), BSWAP_32BIG_C(0x8a117171U), +}; + +uint32_t const DomainParam_Brainpool_256r1[] = +{ + BSWAP_32BIG_C(0xedfe3eaaU), BSWAP_32BIG_C(0x60cca332U), BSWAP_32BIG_C(0xc40ba65cU), BSWAP_32BIG_C(0x5b15ca42U), + BSWAP_32BIG_C(0x08394b93U), BSWAP_32BIG_C(0x8779b3ecU), BSWAP_32BIG_C(0xfc081496U), BSWAP_32BIG_C(0x60434e99U), + BSWAP_32BIG_C(0x4552fa44U), BSWAP_32BIG_C(0x66e57d63U), BSWAP_32BIG_C(0x015876d6U), BSWAP_32BIG_C(0x3757ad69U), + BSWAP_32BIG_C(0x3261babdU), BSWAP_32BIG_C(0xd8ecfa94U), BSWAP_32BIG_C(0x17f85400U), BSWAP_32BIG_C(0x234f150eU), + BSWAP_32BIG_C(0x5ea911e5U), BSWAP_32BIG_C(0x3f2ceb6cU), BSWAP_32BIG_C(0x6c2897d7U), BSWAP_32BIG_C(0x3bf2d8ecU), + BSWAP_32BIG_C(0x18514cf3U), BSWAP_32BIG_C(0x44c9e543U), BSWAP_32BIG_C(0x8997fd59U), BSWAP_32BIG_C(0x8b40bc41U), + BSWAP_32BIG_C(0xb17782eeU), BSWAP_32BIG_C(0xef4fd5c8U), BSWAP_32BIG_C(0x97540d29U), BSWAP_32BIG_C(0xc161589bU), + BSWAP_32BIG_C(0x74f8160cU), BSWAP_32BIG_C(0x8d51c2f3U), BSWAP_32BIG_C(0x81c87ef2U), BSWAP_32BIG_C(0x0a41096cU), + BSWAP_32BIG_C(0xad8d3cb0U), BSWAP_32BIG_C(0xadf0c76cU), BSWAP_32BIG_C(0xa40e5103U), BSWAP_32BIG_C(0xb2c5af11U), + BSWAP_32BIG_C(0x9365af9aU), BSWAP_32BIG_C(0xebfe4c00U), BSWAP_32BIG_C(0xb14dfb71U), BSWAP_32BIG_C(0x477c31cdU), + BSWAP_32BIG_C(0x0e11171eU), BSWAP_32BIG_C(0x9d536a58U), BSWAP_32BIG_C(0x152c5afdU), BSWAP_32BIG_C(0xe29fcc17U), + BSWAP_32BIG_C(0x437a6cf9U), BSWAP_32BIG_C(0x71b57bdeU), BSWAP_32BIG_C(0x425e0698U), BSWAP_32BIG_C(0x6e12427aU), + BSWAP_32BIG_C(0xc73460b9U), BSWAP_32BIG_C(0x42b6bfc5U), BSWAP_32BIG_C(0x53f33de0U), BSWAP_32BIG_C(0x0537d279U), + BSWAP_32BIG_C(0x1d4a9a68U), BSWAP_32BIG_C(0x35c39c6bU), BSWAP_32BIG_C(0x70fc32e7U), BSWAP_32BIG_C(0x7b81fb79U), + BSWAP_32BIG_C(0x144ef689U), BSWAP_32BIG_C(0x6fe757c8U), BSWAP_32BIG_C(0x8b1ce932U), BSWAP_32BIG_C(0x39e47c27U), + BSWAP_32BIG_C(0xb3880125U), BSWAP_32BIG_C(0xa5be4d73U), BSWAP_32BIG_C(0xf7fabd06U), BSWAP_32BIG_C(0x0f58ca9aU), + BSWAP_32BIG_C(0x0af7048dU), BSWAP_32BIG_C(0x6f6fa32dU), BSWAP_32BIG_C(0xfea15cafU), BSWAP_32BIG_C(0x4dac41f8U), + BSWAP_32BIG_C(0xadd1269fU), BSWAP_32BIG_C(0x253e68a0U), BSWAP_32BIG_C(0xf34017cfU), BSWAP_32BIG_C(0x31111c43U), +}; + +uint32_t const DomainParam_Brainpool_384r1[] = +{ + BSWAP_32BIG_C(0x5af47deaU), BSWAP_32BIG_C(0x63f28e9dU), BSWAP_32BIG_C(0x2d8fe31fU), BSWAP_32BIG_C(0x0bce7626U), + BSWAP_32BIG_C(0x4f351c2eU), BSWAP_32BIG_C(0x8082d50bU), BSWAP_32BIG_C(0xb4783637U), BSWAP_32BIG_C(0xb9d1d672U), + BSWAP_32BIG_C(0x2f6a9b6fU), BSWAP_32BIG_C(0x7b0a0847U), BSWAP_32BIG_C(0x9e8e9e53U), BSWAP_32BIG_C(0xd1fd8c14U), + BSWAP_32BIG_C(0xf844d19cU), BSWAP_32BIG_C(0x22e2ed6cU), BSWAP_32BIG_C(0x40fcdc97U), BSWAP_32BIG_C(0x451a8443U), + BSWAP_32BIG_C(0x0c8c4cf0U), BSWAP_32BIG_C(0x7a43c7faU), BSWAP_32BIG_C(0xc749bf0bU), BSWAP_32BIG_C(0x49bb87ebU), + BSWAP_32BIG_C(0x1f15d9fbU), BSWAP_32BIG_C(0x6cb4945cU), BSWAP_32BIG_C(0x432cd564U), BSWAP_32BIG_C(0xf00f6f79U), + BSWAP_32BIG_C(0xcf87a42cU), BSWAP_32BIG_C(0x531ccc07U), BSWAP_32BIG_C(0xe9cb004cU), BSWAP_32BIG_C(0x49d0798dU), + BSWAP_32BIG_C(0xb1669415U), BSWAP_32BIG_C(0xad54e498U), BSWAP_32BIG_C(0x6c648847U), BSWAP_32BIG_C(0x07c6a03aU), + BSWAP_32BIG_C(0xe5cb3975U), BSWAP_32BIG_C(0x9c1ae0ebU), BSWAP_32BIG_C(0xfcca95e3U), BSWAP_32BIG_C(0xf319072dU), + BSWAP_32BIG_C(0x73951576U), BSWAP_32BIG_C(0x74721ee4U), BSWAP_32BIG_C(0x418fa196U), BSWAP_32BIG_C(0x02172560U), + BSWAP_32BIG_C(0x0e58541cU), BSWAP_32BIG_C(0xad5c599aU), BSWAP_32BIG_C(0xa3e311cfU), BSWAP_32BIG_C(0xdad89377U), + BSWAP_32BIG_C(0x9f321ae9U), BSWAP_32BIG_C(0x37fdbb5bU), BSWAP_32BIG_C(0x7c4b86c4U), BSWAP_32BIG_C(0x4c3686ebU), + BSWAP_32BIG_C(0x9ef342e6U), BSWAP_32BIG_C(0x5889a02bU), BSWAP_32BIG_C(0x4184b209U), BSWAP_32BIG_C(0xff7277e0U), + BSWAP_32BIG_C(0x44239909U), BSWAP_32BIG_C(0xbb4381e6U), BSWAP_32BIG_C(0x97a43546U), BSWAP_32BIG_C(0xa538ab8eU), + BSWAP_32BIG_C(0xf8b9182cU), BSWAP_32BIG_C(0xdbe5e2a7U), BSWAP_32BIG_C(0x9d51fbb0U), BSWAP_32BIG_C(0x04262d8dU), + BSWAP_32BIG_C(0xf1e65d86U), BSWAP_32BIG_C(0x58139700U), BSWAP_32BIG_C(0x01a721a5U), BSWAP_32BIG_C(0x8ae61429U), + BSWAP_32BIG_C(0xf0e8dff6U), BSWAP_32BIG_C(0xd263d9adU), BSWAP_32BIG_C(0x08defbf6U), BSWAP_32BIG_C(0xb59c41c8U), + BSWAP_32BIG_C(0x9ff5666fU), BSWAP_32BIG_C(0x496f64fdU), BSWAP_32BIG_C(0x1892bd1fU), BSWAP_32BIG_C(0x0f442820U), + BSWAP_32BIG_C(0x273fca54U), BSWAP_32BIG_C(0xa7c2fdb6U), BSWAP_32BIG_C(0x231a20a4U), BSWAP_32BIG_C(0x0aa0b20fU), + BSWAP_32BIG_C(0xa8418d13U), BSWAP_32BIG_C(0x8a5b7ae0U), BSWAP_32BIG_C(0x332ae50dU), BSWAP_32BIG_C(0x41af6d76U), + BSWAP_32BIG_C(0xe0dbaa9cU), BSWAP_32BIG_C(0x0aaf44bcU), BSWAP_32BIG_C(0xfbb63eafU), BSWAP_32BIG_C(0xa45aad20U), + BSWAP_32BIG_C(0x0f247da5U), BSWAP_32BIG_C(0x16ff80abU), BSWAP_32BIG_C(0x6928e857U), BSWAP_32BIG_C(0x77931c49U), + BSWAP_32BIG_C(0x0a513afeU), BSWAP_32BIG_C(0xdf82aef2U), BSWAP_32BIG_C(0xc7ec95c4U), BSWAP_32BIG_C(0x5932731aU), + BSWAP_32BIG_C(0xc3ff6021U), BSWAP_32BIG_C(0x5fe1b0f4U), BSWAP_32BIG_C(0xdb67f487U), BSWAP_32BIG_C(0x72531f68U), + BSWAP_32BIG_C(0xc3737a8dU), BSWAP_32BIG_C(0xa0273e95U), BSWAP_32BIG_C(0xae241acbU), BSWAP_32BIG_C(0xa0ce40ddU), + BSWAP_32BIG_C(0x6e6bb314U), BSWAP_32BIG_C(0x68582a5dU), BSWAP_32BIG_C(0xf1653edeU), BSWAP_32BIG_C(0xc62e358fU), +}; + +uint32_t const DomainParam_Brainpool_512r1[] = +{ + BSWAP_32BIG_C(0xf1cb294dU), BSWAP_32BIG_C(0x1cf2464eU), BSWAP_32BIG_C(0x528afd58U), BSWAP_32BIG_C(0x14d85df8U), + BSWAP_32BIG_C(0x615d0538U), BSWAP_32BIG_C(0x6db75452U), BSWAP_32BIG_C(0xdfe9cbb8U), BSWAP_32BIG_C(0x64b7bb7aU), + BSWAP_32BIG_C(0x51e3f2ecU), BSWAP_32BIG_C(0x5db1eee5U), BSWAP_32BIG_C(0xf9bca9d3U), BSWAP_32BIG_C(0x174a369eU), + BSWAP_32BIG_C(0x3f1bcf73U), BSWAP_32BIG_C(0x63675a89U), BSWAP_32BIG_C(0x22ea0c31U), BSWAP_32BIG_C(0x5a0160f7U), + BSWAP_32BIG_C(0x3e44084cU), BSWAP_32BIG_C(0x1aebae8dU), BSWAP_32BIG_C(0x81df8311U), BSWAP_32BIG_C(0x1821be87U), + BSWAP_32BIG_C(0x724afba7U), BSWAP_32BIG_C(0xb42583e2U), BSWAP_32BIG_C(0x09e263a4U), BSWAP_32BIG_C(0x6a561a71U), + BSWAP_32BIG_C(0xdbbfc13aU), BSWAP_32BIG_C(0x0b6fbfd0U), BSWAP_32BIG_C(0x41ecd1a6U), BSWAP_32BIG_C(0xed04a5d1U), + BSWAP_32BIG_C(0x5029bc29U), BSWAP_32BIG_C(0xe847c63aU), BSWAP_32BIG_C(0x8ab05f1fU), BSWAP_32BIG_C(0xec1fd565U), + BSWAP_32BIG_C(0xcf3fed7eU), BSWAP_32BIG_C(0x435d74baU), BSWAP_32BIG_C(0x09581bc4U), BSWAP_32BIG_C(0x06fae2bdU), + BSWAP_32BIG_C(0x497b903aU), BSWAP_32BIG_C(0x20d53be2U), BSWAP_32BIG_C(0xfbd7b193U), BSWAP_32BIG_C(0x523f76c8U), + BSWAP_32BIG_C(0x6c60616fU), BSWAP_32BIG_C(0x784206bbU), BSWAP_32BIG_C(0x522c144eU), BSWAP_32BIG_C(0x23490627U), + BSWAP_32BIG_C(0xf093a77cU), BSWAP_32BIG_C(0x5ce92c6dU), BSWAP_32BIG_C(0xc8a461e6U), BSWAP_32BIG_C(0x064e0521U), + BSWAP_32BIG_C(0x7fd8077eU), BSWAP_32BIG_C(0x1b29332dU), BSWAP_32BIG_C(0x8bdb778eU), BSWAP_32BIG_C(0x71031464U), + BSWAP_32BIG_C(0x644d626eU), BSWAP_32BIG_C(0x5be163fcU), BSWAP_32BIG_C(0x93eb8853U), BSWAP_32BIG_C(0xa3f5743bU), + BSWAP_32BIG_C(0xd1255f8dU), BSWAP_32BIG_C(0x943461ddU), BSWAP_32BIG_C(0x0b98989aU), BSWAP_32BIG_C(0x762a3af2U), + BSWAP_32BIG_C(0x1ce4b678U), BSWAP_32BIG_C(0x51bb714bU), BSWAP_32BIG_C(0x724d46b5U), BSWAP_32BIG_C(0x80ffe8ceU), + BSWAP_32BIG_C(0xb881f838U), BSWAP_32BIG_C(0xc7741d40U), BSWAP_32BIG_C(0x4c2b7842U), BSWAP_32BIG_C(0xa7f02d54U), + BSWAP_32BIG_C(0x3bc74902U), BSWAP_32BIG_C(0x151306d9U), BSWAP_32BIG_C(0x29908baeU), BSWAP_32BIG_C(0xc8c0fc70U), + BSWAP_32BIG_C(0x012edd8aU), BSWAP_32BIG_C(0x3a427b1cU), BSWAP_32BIG_C(0x044416c7U), BSWAP_32BIG_C(0x94662783U), + BSWAP_32BIG_C(0xfe747d98U), BSWAP_32BIG_C(0x167632c3U), BSWAP_32BIG_C(0xa268c188U), BSWAP_32BIG_C(0x86b6a6e5U), + BSWAP_32BIG_C(0x2beee4a4U), BSWAP_32BIG_C(0xa8f4a8f0U), BSWAP_32BIG_C(0xf8ee7b3eU), BSWAP_32BIG_C(0x3c6eb6a9U), + BSWAP_32BIG_C(0xe5f5605cU), BSWAP_32BIG_C(0x624aed62U), BSWAP_32BIG_C(0x1dcd888aU), BSWAP_32BIG_C(0xe16555dfU), + BSWAP_32BIG_C(0xefe68310U), BSWAP_32BIG_C(0xe8978c8fU), BSWAP_32BIG_C(0xaa088d92U), BSWAP_32BIG_C(0x78cb8467U), + BSWAP_32BIG_C(0xafd20ac1U), BSWAP_32BIG_C(0xa0909bc2U), BSWAP_32BIG_C(0xa72f5c8dU), BSWAP_32BIG_C(0xec517a8fU), + BSWAP_32BIG_C(0x68b454eeU), BSWAP_32BIG_C(0x4c8b4bfcU), BSWAP_32BIG_C(0xb25d217cU), BSWAP_32BIG_C(0x267ebc1dU), + BSWAP_32BIG_C(0xd64b5feaU), BSWAP_32BIG_C(0xd49c40e7U), BSWAP_32BIG_C(0x0805c3e6U), BSWAP_32BIG_C(0x13fb307bU), + BSWAP_32BIG_C(0x236769c9U), BSWAP_32BIG_C(0x43d1c632U), BSWAP_32BIG_C(0x7bbc60beU), BSWAP_32BIG_C(0x344e74bfU), + BSWAP_32BIG_C(0x7a3c8a43U), BSWAP_32BIG_C(0xcb212038U), BSWAP_32BIG_C(0x57d450ebU), BSWAP_32BIG_C(0xaa23e1ceU), + BSWAP_32BIG_C(0xa2e61d0eU), BSWAP_32BIG_C(0x125f0312U), BSWAP_32BIG_C(0x4444b76fU), BSWAP_32BIG_C(0xd4eff35cU), + BSWAP_32BIG_C(0xec26cee7U), BSWAP_32BIG_C(0x92673fa8U), BSWAP_32BIG_C(0x4ca68a96U), BSWAP_32BIG_C(0xbf7b9fa2U), + BSWAP_32BIG_C(0xaa259ea7U), BSWAP_32BIG_C(0xe7c08bf8U), BSWAP_32BIG_C(0x99a17e25U), BSWAP_32BIG_C(0x2bd426f4U), + BSWAP_32BIG_C(0xd0af6e60U), BSWAP_32BIG_C(0xc0753e74U), BSWAP_32BIG_C(0x12ae5b37U), BSWAP_32BIG_C(0xbd95728eU), + BSWAP_32BIG_C(0x98090a9fU), BSWAP_32BIG_C(0x04fc6f93U), BSWAP_32BIG_C(0x8271d0f9U), BSWAP_32BIG_C(0x3d018521U), + BSWAP_32BIG_C(0xd0ae694dU), BSWAP_32BIG_C(0xc9d098a6U), BSWAP_32BIG_C(0x5025087bU), BSWAP_32BIG_C(0xc522683bU), +}; + +uint32_t const DomainParam_Koblitz_secp256k1[] = +{ + BSWAP_32BIG_C(0x8ab7bc7eU), BSWAP_32BIG_C(0x60c4601aU), BSWAP_32BIG_C(0x1090109eU), BSWAP_32BIG_C(0x10816c9eU), + BSWAP_32BIG_C(0xf889c01cU), BSWAP_32BIG_C(0xac9e6736U), BSWAP_32BIG_C(0xdf536181U), BSWAP_32BIG_C(0x9a5cf89eU), + BSWAP_32BIG_C(0xc1063010U), BSWAP_32BIG_C(0x8e9c99b6U), BSWAP_32BIG_C(0xdf01bac0U), BSWAP_32BIG_C(0x2787ae77U), + BSWAP_32BIG_C(0x911ef89bU), BSWAP_32BIG_C(0xaba8d56dU), BSWAP_32BIG_C(0xe3d76f91U), BSWAP_32BIG_C(0x4a25c671U), + BSWAP_32BIG_C(0x70d6d2cdU), BSWAP_32BIG_C(0x4859e1e1U), BSWAP_32BIG_C(0x132f9128U), BSWAP_32BIG_C(0x83d56b42U), + BSWAP_32BIG_C(0x6a4f5a16U), BSWAP_32BIG_C(0x91cc0fb6U), BSWAP_32BIG_C(0x54fd12adU), BSWAP_32BIG_C(0x4878c7e7U), + BSWAP_32BIG_C(0x7c727a8fU), BSWAP_32BIG_C(0xc174a90eU), BSWAP_32BIG_C(0x2aaae7d1U), BSWAP_32BIG_C(0x68dd6db6U), + BSWAP_32BIG_C(0xbdbcfd2dU), BSWAP_32BIG_C(0xed095eecU), BSWAP_32BIG_C(0x5423f3feU), BSWAP_32BIG_C(0xaa49fb61U), + BSWAP_32BIG_C(0x98d6fc5dU), BSWAP_32BIG_C(0xed01f5c8U), BSWAP_32BIG_C(0x48b7e964U), BSWAP_32BIG_C(0x593d27d1U), + BSWAP_32BIG_C(0xada4442dU), BSWAP_32BIG_C(0xe7ba1636U), BSWAP_32BIG_C(0xe334019dU), BSWAP_32BIG_C(0x45b442e6U), + BSWAP_32BIG_C(0x7761876eU), BSWAP_32BIG_C(0x8923a8b9U), BSWAP_32BIG_C(0x9f9f242bU), BSWAP_32BIG_C(0xefda4b9dU), + BSWAP_32BIG_C(0x1dc4a72eU), BSWAP_32BIG_C(0xff1e9c9dU), BSWAP_32BIG_C(0x7d94a0e6U), BSWAP_32BIG_C(0xc68919b3U), + BSWAP_32BIG_C(0x1f090536U), BSWAP_32BIG_C(0xffeae12bU), BSWAP_32BIG_C(0x7217f173U), BSWAP_32BIG_C(0x030c960fU), + BSWAP_32BIG_C(0x8703845eU), BSWAP_32BIG_C(0x5f43e097U), BSWAP_32BIG_C(0x494d2673U), BSWAP_32BIG_C(0x492109d2U), + BSWAP_32BIG_C(0x25e53c51U), BSWAP_32BIG_C(0x6f2aaca2U), BSWAP_32BIG_C(0xb9923498U), BSWAP_32BIG_C(0x36c6f390U), + BSWAP_32BIG_C(0xc5250c3cU), BSWAP_32BIG_C(0xa486353aU), BSWAP_32BIG_C(0x2d23d677U), BSWAP_32BIG_C(0x18bef955U), + BSWAP_32BIG_C(0x2b33ac23U), BSWAP_32BIG_C(0x91ac4a3bU), BSWAP_32BIG_C(0x4ed4a36bU), BSWAP_32BIG_C(0xe273eac4U), + BSWAP_32BIG_C(0xb480b510U), BSWAP_32BIG_C(0x5978645cU), BSWAP_32BIG_C(0x76491482U), BSWAP_32BIG_C(0xba9bf7afU), +}; diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.h new file mode 100644 index 0000000000..a70f32a261 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_data.h @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_DATA_H +#define R_RSIP_DATA_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern uint32_t INST_DATA_SIZE; + +#endif /* R_RSIP_DATA_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func008.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func008.c new file mode 100644 index 0000000000..6a13e89b11 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func008.c @@ -0,0 +1,100 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func008 (void) +{ + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000890U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000008e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func016.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func016.c new file mode 100644 index 0000000000..20d9781f54 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func016.c @@ -0,0 +1,101 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func016 (uint32_t ARG1) +{ + uint32_t oLoop = 0U; + + r_rsip_func100(bswap_32big(0x6f1ac5a9U), + bswap_32big(0xa623b33bU), + bswap_32big(0xbe75b461U), + bswap_32big(0x5cd3d5ccU)); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 2]); + S_RAM[0 + 2] = bswap_32big(S_RAM[0 + 2]); + + for (oLoop = 0U; oLoop < S_RAM[0 + 2]; ) + { + WR1_PROG(REG_1600H, 0x34202820U); + WR1_PROG(REG_1600H, 0x2000d060U); + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x9c2e3e2aU), bswap_32big(0x7ee70e3bU), bswap_32big(0x22c4ad1fU), + bswap_32big(0xe2233620U)); + WR1_PROG(REG_1A24H, 0xe70c0d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &S_HEAP[ARG1 + oLoop]); + + WR1_PROG(REG_1600H, 0x00002422U); + + r_rsip_func101(bswap_32big(0x33a34c03U), bswap_32big(0x2465cc63U), bswap_32big(0x760883d2U), + bswap_32big(0x69a0de7dU)); + oLoop = oLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000801U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x0199b139U), + bswap_32big(0x136515d9U), + bswap_32big(0xef3162ccU), + bswap_32big(0xe347a6faU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x091c0105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &S_HEAP[ARG1 + oLoop]); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func017.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func017.c new file mode 100644 index 0000000000..bb26bb5e98 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func017.c @@ -0,0 +1,91 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func017 (uint32_t ARG1) +{ + uint32_t oLoop = 0U; + + r_rsip_func100(bswap_32big(0x368c755dU), + bswap_32big(0xe3f727f8U), + bswap_32big(0x2361620cU), + bswap_32big(0x20de4a39U)); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 2]); + S_RAM[0 + 2] = bswap_32big(S_RAM[0 + 2]); + + for (oLoop = 0U; oLoop < S_RAM[0 + 2]; ) + { + WR1_PROG(REG_1600H, 0x34202820U); + WR1_PROG(REG_1600H, 0x2000d060U); + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A24H, 0xf70c0d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_HEAP[ARG1 + oLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002422U); + + r_rsip_func101(bswap_32big(0x425441daU), bswap_32big(0x03608447U), bswap_32big(0xd051e2d4U), + bswap_32big(0x998c7c69U)); + oLoop = oLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000801U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A24H, 0x070c0d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_HEAP[ARG1 + oLoop]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func027.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func027.c new file mode 100644 index 0000000000..6ee05c798f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func027.c @@ -0,0 +1,118 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func027 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x01305c44U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0142859dU); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1404H, 0x10400000U); + WR1_PROG(REG_1444H, 0x000047c2U); + WR1_PROG(REG_1A2CH, 0x00001100U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[28]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[32]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[36]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x13600000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[40]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[44]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[48]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18600000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[52]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[56]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[60]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18b00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[64]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[68]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[72]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10900000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[76]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[80]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[84]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18100000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[88]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[92]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[96]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[100]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func028.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func028.c new file mode 100644 index 0000000000..6f718faafd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func028.c @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func028 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x01166403U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x013659ffU); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1404H, 0x11b00000U); + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x00000500U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[8]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11e80000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[12]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[16]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[20]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[24]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func030.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func030.c new file mode 100644 index 0000000000..0ed5cf90a9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func030.c @@ -0,0 +1,46 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func030 (void) +{ + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b4a0U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x1000b4c0U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1600H, 0x1000b4e0U); + WR1_PROG(REG_1600H, 0x00000009U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1600H, 0x1000b4a0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x1000b4c0U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1600H, 0x1000b4e0U); + WR1_PROG(REG_1600H, 0x0000000dU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x1000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x1000b4c0U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x1000b4e0U); + WR1_PROG(REG_1600H, 0x0000000dU); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func031.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func031.c new file mode 100644 index 0000000000..e289ee070e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func031.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func031 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1600H, 0x0000356aU); + WR1_PROG(REG_1600H, 0x0420a960U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x0001696bU); + WR1_PROG(REG_1600H, 0x00036d6bU); + + WR1_PROG(REG_1600H, 0x00009160U); + WR1_PROG(REG_1600H, 0x00000042U); + WR1_PROG(REG_1600H, 0x00186d6bU); + + WR1_PROG(REG_1600H, 0x00008c60U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x0000106bU); + WR1_PROG(REG_1600H, 0x000010c9U); + + WR1_PROG(REG_1824H, 0x08000105U); + WR1_PROG(REG_1608H, 0x81040060U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + WR1_PROG(REG_1608H, 0x80040180U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b560U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1600H, 0x01906d6cU); + WR1_PROG(REG_1600H, 0x01906d8dU); + WR1_PROG(REG_1600H, 0x000009adU); + WR1_PROG(REG_1600H, 0x000009ceU); + + WR1_PROG(REG_1824H, 0x08000105U); + WR1_PROG(REG_1608H, 0x81040160U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00000100U); + WR1_PROG(REG_1824H, 0xf8008007U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00490021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func040.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func040.c new file mode 100644 index 0000000000..33ea6a6e76 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func040.c @@ -0,0 +1,47 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func040 (void) +{ + r_rsip_func100(bswap_32big(0xe960a74fU), + bswap_32big(0x4d3fc9fbU), + bswap_32big(0x5d4eb718U), + bswap_32big(0xffb5a7a7U)); + WR1_PROG(REG_1A24H, 0x4a470044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e470484U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x01ea725dU)); + + r_rsip_func100(bswap_32big(0xb2141d54U), + bswap_32big(0x49dba92cU), + bswap_32big(0x92aa10b5U), + bswap_32big(0x6f4942dfU)); + WR1_PROG(REG_1A24H, 0x4a470044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e470494U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x02ea725dU)); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func043.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func043.c new file mode 100644 index 0000000000..0cd74b0a0c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func043.c @@ -0,0 +1,122 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func043 (void) +{ + r_rsip_func100(bswap_32big(0x6ab71710U), + bswap_32big(0xb914c763U), + bswap_32big(0x60a8d359U), + bswap_32big(0xb76d5418U)); + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x000001d0U); + WR1_PROG(REG_1608H, 0x8188000aU); + + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x6a1baa91U), + bswap_32big(0x0f3acd3dU), + bswap_32big(0x401977b6U), + bswap_32big(0xb1b408a5U)); + WR1_PROG(REG_1A24H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xcbbf314bU), + bswap_32big(0x8579611fU), + bswap_32big(0x5e2a7cf5U), + bswap_32big(0x3cff2581U)); + + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x000001c0U); + WR1_PROG(REG_1608H, 0x8184000aU); + + WR1_PROG(REG_1A24H, 0x080000c5U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x0b040104U); + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x01000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009105U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x02000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009045U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0xb63c4bacU), + bswap_32big(0x458abb86U), + bswap_32big(0xb9a13e61U), + bswap_32big(0xb132cd47U)); + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x915d9137U), + bswap_32big(0x7df2d248U), + bswap_32big(0xcc59b369U), + bswap_32big(0x184be643U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func044.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func044.c new file mode 100644 index 0000000000..ca90bb3d3a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func044.c @@ -0,0 +1,75 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func044 (void) +{ + WR1_PROG(REG_1600H, 0x00008ce0U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x000090e0U); + WR1_PROG(REG_1600H, 0x01000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009104U); + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008ce0U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x000090e0U); + WR1_PROG(REG_1600H, 0x02000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009044U); + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0xdaec2193U), + bswap_32big(0x8c4491baU), + bswap_32big(0x6b93d7e7U), + bswap_32big(0xd3218709U)); + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x0c55093fU), + bswap_32big(0xb6622226U), + bswap_32big(0xf54987cfU), + bswap_32big(0x34435aafU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func048.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func048.c new file mode 100644 index 0000000000..9b1c82d455 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func048.c @@ -0,0 +1,25 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func048 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(ARG1[0])); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func049.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func049.c new file mode 100644 index 0000000000..422bd3ed4d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func049.c @@ -0,0 +1,25 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func049 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[0]); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func052.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func052.c new file mode 100644 index 0000000000..ca80c389d1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func052.c @@ -0,0 +1,1095 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func052 (void) +{ + uint32_t OFS_ADR = 0U; + + WR1_PROG(REG_1600H, 0x0000373dU); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + while (1) + { + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x7c6ac214U), bswap_32big(0xf6d38923U), bswap_32big(0x6edc917dU), + bswap_32big(0x74e45fe0U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1010000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00002fc0U); + + r_rsip_func101(bswap_32big(0xf2100eb9U), bswap_32big(0x1644cec2U), bswap_32big(0x570218c9U), + bswap_32big(0x11ddbd6bU)); + } + else + { + r_rsip_func101(bswap_32big(0x9d6a3a32U), bswap_32big(0x8c74a943U), bswap_32big(0xbb46c6b9U), + bswap_32big(0xb2bd77ccU)); + + break; + } + } + + WR1_PROG(REG_1404H, 0x19b00000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xf22994b8U)); + + OFS_ADR = 40; + + WR1_PROG(REG_1404H, 0x19b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000521U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x63fc75a1U), + bswap_32big(0x06db7dffU), + bswap_32big(0x6d74b834U), + bswap_32big(0xfc307f0dU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x725c8882U)); + + OFS_ADR = 80; + + WR1_PROG(REG_1404H, 0x19b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000522U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc6f978b9U), + bswap_32big(0x45118571U), + bswap_32big(0x7dcef9beU), + bswap_32big(0xe733a32fU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x68d2ac6fU)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x19b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000523U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xea1e641eU), + bswap_32big(0xbe352ddeU), + bswap_32big(0x74455cbeU), + bswap_32big(0x23449c19U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x6afa85bfU)); + + OFS_ADR = 120; + + WR1_PROG(REG_1404H, 0x19b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000524U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x38228f9eU), + bswap_32big(0xa1a5aeddU), + bswap_32big(0x68dcc687U), + bswap_32big(0x093f17e7U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x093b7d04U)); + + OFS_ADR = 160; + + WR1_PROG(REG_1404H, 0x11a00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000525U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf85ae6afU), + bswap_32big(0x50c047b8U), + bswap_32big(0x89dc3e3eU), + bswap_32big(0x9fc541d7U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x15b00000U); + WR1_PROG(REG_1600H, 0x00000b7bU); + WR1_PROG(REG_1608H, 0x80a0001bU); + WR1_PROG(REG_1400H, 0x03430081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + while (1) + { + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xaa04c482U), bswap_32big(0x55e286acU), bswap_32big(0xb54fbc75U), + bswap_32big(0x4229209fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xbd2f4512U), bswap_32big(0x1cdcd45aU), bswap_32big(0xdb0a530dU), + bswap_32big(0x48eff268U)); + + break; + } + else + { + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x68d2ac6fU)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x13980000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000521U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5973b3f4U), bswap_32big(0x7debd89eU), bswap_32big(0x9766ef56U), + bswap_32big(0x3934cdd6U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xf22994b8U)); + + OFS_ADR = 40; + + WR1_PROG(REG_1404H, 0x19b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000522U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0d381f08U), bswap_32big(0xab42f3fbU), bswap_32big(0x0a5f0f5aU), + bswap_32big(0xcd3cffd5U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000521U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc01d0439U), bswap_32big(0xdf87e860U), bswap_32big(0x000c1558U), + bswap_32big(0x30368515U)); + r_rsip_func053(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x68d2ac6fU)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x13980000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000526U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa19eeb87U), bswap_32big(0x1a1bb519U), bswap_32big(0x02210472U), + bswap_32big(0xf5271bbcU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xf22994b8U)); + + OFS_ADR = 40; + + WR1_PROG(REG_1404H, 0x19b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000527U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe0adcff3U), bswap_32big(0x1e6dbcb2U), bswap_32big(0xa6cb099fU), + bswap_32big(0xaa6c3cabU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x725c8882U)); + + OFS_ADR = 80; + + WR1_PROG(REG_1404H, 0x13980000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000523U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x51e31ad8U), bswap_32big(0x91d3d0e1U), bswap_32big(0xf72c4cccU), + bswap_32big(0x349f7125U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x6afa85bfU)); + + OFS_ADR = 120; + + WR1_PROG(REG_1404H, 0x19b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000524U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x498c84d1U), bswap_32big(0x5c07b8e5U), bswap_32big(0x4320ac62U), + bswap_32big(0xeb4e90e0U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1404H, 0x1f580000U); + WR1_PROG(REG_1400H, 0x00c00081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000522U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x64088ec8U), bswap_32big(0xa1137ecfU), bswap_32big(0x8f6f5227U), + bswap_32big(0x876abcd4U)); + r_rsip_func053(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x725c8882U)); + + OFS_ADR = 80; + + WR1_PROG(REG_1404H, 0x13980000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000528U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x44666c98U), bswap_32big(0x19a3f9d4U), bswap_32big(0x71ae2cfeU), + bswap_32big(0x9674e24fU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x6afa85bfU)); + + OFS_ADR = 120; + + WR1_PROG(REG_1404H, 0x19b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000529U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x60b25cb8U), bswap_32big(0x09849cd5U), bswap_32big(0x72e20d92U), + bswap_32big(0x88459d59U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x1f580000U); + WR1_PROG(REG_1400H, 0x00c00081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x858a157fU), bswap_32big(0xaadc81d1U), bswap_32big(0xc1e4a9f2U), + bswap_32big(0x59616e49U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x68d2ac6fU)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000525U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc2c0f3d9U), + bswap_32big(0x1c868867U), + bswap_32big(0x76f4064aU), + bswap_32big(0xc35092daU)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x725c8882U)); + + OFS_ADR = 80; + + WR1_PROG(REG_1404H, 0x1f480000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000526U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcf049895U), + bswap_32big(0x4391b176U), + bswap_32big(0xbe70aa70U), + bswap_32big(0xe15033d1U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000521U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbd5601a5U), + bswap_32big(0x559a2ac9U), + bswap_32big(0x1520a56eU), + bswap_32big(0x8f7fd2b9U)); + r_rsip_func303(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x68d2ac6fU)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcee7a7b1U), + bswap_32big(0xff7ce462U), + bswap_32big(0x8efd19d1U), + bswap_32big(0x3a4a2ee9U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xf22994b8U)); + + OFS_ADR = 40; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000527U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf0f362e9U), + bswap_32big(0x375ab0bcU), + bswap_32big(0xd7124398U), + bswap_32big(0x36391239U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x6afa85bfU)); + + OFS_ADR = 120; + + WR1_PROG(REG_1404H, 0x1f480000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000528U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3f4c1c10U), + bswap_32big(0x976d4db7U), + bswap_32big(0x56e10896U), + bswap_32big(0xe57c1968U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000522U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x123d43e9U), + bswap_32big(0x19223b04U), + bswap_32big(0x8ddc8b02U), + bswap_32big(0xf4a282f6U)); + r_rsip_func303(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xf22994b8U)); + + OFS_ADR = 40; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc50acd4eU), + bswap_32big(0x34c71d00U), + bswap_32big(0xb6835d2eU), + bswap_32big(0x8412ad76U)); + r_rsip_func016(OFS_ADR); + + r_rsip_func101(bswap_32big(0x077d5b77U), + bswap_32big(0x97a81921U), + bswap_32big(0x755c34a2U), + bswap_32big(0xc5a2dbd4U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x725c8882U)); + + OFS_ADR = 80; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa92bb347U), + bswap_32big(0x296c1816U), + bswap_32big(0x46dc743cU), + bswap_32big(0x76f69540U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x68d2ac6fU)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x1f480000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x34b30840U), + bswap_32big(0xeab7f3e9U), + bswap_32big(0x374e6fb3U), + bswap_32big(0x50ae3b0fU)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000523U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc4c524a3U), + bswap_32big(0x41cdb506U), + bswap_32big(0xa8963a09U), + bswap_32big(0x84c8adfdU)); + r_rsip_func303(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x725c8882U)); + + OFS_ADR = 80; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7af55f9eU), + bswap_32big(0xc2ba9459U), + bswap_32big(0x8844a4aeU), + bswap_32big(0xd98ca9f6U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x6afa85bfU)); + + OFS_ADR = 120; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe26f2c4eU), + bswap_32big(0x9aa932d9U), + bswap_32big(0x7f937af4U), + bswap_32big(0x544c70b1U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xf22994b8U)); + + OFS_ADR = 40; + + WR1_PROG(REG_1404H, 0x1f480000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3755ac8eU), + bswap_32big(0x2e702383U), + bswap_32big(0x6d8cd9dfU), + bswap_32big(0x3307a73eU)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000524U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3f4279feU), + bswap_32big(0x302d87e8U), + bswap_32big(0xc375784cU), + bswap_32big(0x78d50328U)); + r_rsip_func303(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x6afa85bfU)); + + OFS_ADR = 120; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x58aa89a5U), + bswap_32big(0xe1b53846U), + bswap_32big(0x3147e93cU), + bswap_32big(0xe67d7176U)); + r_rsip_func016(OFS_ADR); + + r_rsip_func101(bswap_32big(0xd9ac97bcU), + bswap_32big(0x96100312U), + bswap_32big(0x00cf8024U), + bswap_32big(0xea34fff2U)); + } + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x093b7d04U)); + + OFS_ADR = 160; + + WR1_PROG(REG_1404H, 0x11a00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd65d8e4bU), + bswap_32big(0xf1c6fe15U), + bswap_32big(0x57a651e4U), + bswap_32big(0x4593a27dU)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + while (1) + { + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x0ba2029bU), bswap_32big(0xa858a58dU), bswap_32big(0x3fa4efa3U), + bswap_32big(0xfe4f1928U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x10100008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x000033c0U); + + r_rsip_func101(bswap_32big(0xb5bee57fU), bswap_32big(0x9813f1c8U), bswap_32big(0x38a6508bU), + bswap_32big(0x7e2aafebU)); + } + else + { + r_rsip_func101(bswap_32big(0x6416321fU), bswap_32big(0xd47d43d3U), bswap_32big(0xe8c186daU), + bswap_32big(0xb5082f64U)); + + break; + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x6afa85bfU)); + + OFS_ADR = 120; + + WR1_PROG(REG_1404H, 0x17a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000052fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x200159efU), + bswap_32big(0xf4bb8116U), + bswap_32big(0x83bde300U), + bswap_32big(0xf9e96ca4U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + while (1) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x6ee67558U), bswap_32big(0x9cfb72dbU), bswap_32big(0x0d380054U), + bswap_32big(0x6f274a77U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x70d389b5U), bswap_32big(0x7b31e8e3U), bswap_32big(0x8236f7e4U), + bswap_32big(0x3b05898aU)); + } + else + { + r_rsip_func101(bswap_32big(0x81ffdc83U), bswap_32big(0xeaaddd29U), bswap_32big(0xe5b82c09U), + bswap_32big(0x6ee4df22U)); + + break; + } + } + + WR1_PROG(REG_1600H, 0x3800db60U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x1f3cb9b7U), + bswap_32big(0x568953fcU), + bswap_32big(0xf895cad8U), + bswap_32big(0x96fa5640U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x3c2344c0U), bswap_32big(0xa2c19d38U), bswap_32big(0xb05c4bd0U), + bswap_32big(0x1ecc5658U)); + } + else + { + r_rsip_func101(bswap_32big(0x04923d9eU), bswap_32big(0xba90c94cU), bswap_32big(0xe0d69265U), + bswap_32big(0xbfbe2be2U)); + } + + WR1_PROG(REG_1600H, 0x000037b9U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func053.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func053.c new file mode 100644 index 0000000000..7ced56ffb9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func053.c @@ -0,0 +1,314 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func053 (void) +{ + uint32_t OFS_ADR = 0U; + + WR1_PROG(REG_1600H, 0x0000379dU); + + while (1) + { + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xe6bfc659U), bswap_32big(0xaf9aa26cU), bswap_32big(0xc8e73f5cU), + bswap_32big(0x199a1c3dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14200000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1a380000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x12dd95b0U), bswap_32big(0xbe6c58beU), bswap_32big(0x9bdf49fcU), + bswap_32big(0x221d17fcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1404H, 0x13980000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19b00000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x13980000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x19b00000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x1111000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x1111000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13980000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19b00000U); + WR1_PROG(REG_1608H, 0x81010300U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xc13881d8U), + bswap_32big(0x8f55227dU), + bswap_32big(0xb9d32959U), + bswap_32big(0xce03406eU)); + } + else + { + WR1_PROG(REG_1404H, 0x1f480000U); + WR1_PROG(REG_1600H, 0x00000b7bU); + WR1_PROG(REG_1608H, 0x81a0001bU); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x12120009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f053U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xccf9c189U), + bswap_32big(0x98d77cf7U), + bswap_32big(0xad66dba6U), + bswap_32big(0x1f2c9932U)); + r_rsip_func302(); + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x1111000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13980000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1f480000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x093b7d04U)); + + OFS_ADR = 160; + + WR1_PROG(REG_1404H, 0x1f580000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f053U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x508b97d6U), + bswap_32big(0x0506d2e3U), + bswap_32big(0x539b32c2U), + bswap_32big(0x86244960U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x12120009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f053U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9662b54eU), + bswap_32big(0x60ac207aU), + bswap_32big(0x8ef02d9dU), + bswap_32big(0x9a705dceU)); + r_rsip_func303(); + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x1111000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19b00000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xffc80b1aU), + bswap_32big(0x97eae19fU), + bswap_32big(0xf22d352bU), + bswap_32big(0xd442eedbU)); + } + } + else + { + r_rsip_func101(bswap_32big(0x15aec9a0U), bswap_32big(0xa660fc1aU), bswap_32big(0x3b76b919U), + bswap_32big(0x2f5393d5U)); + + break; + } + } + + WR1_PROG(REG_1600H, 0x000037bcU); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func054.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func054.c new file mode 100644 index 0000000000..644312dd95 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func054.c @@ -0,0 +1,1095 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func054 (void) +{ + uint32_t OFS_ADR = 0U; + + WR1_PROG(REG_1600H, 0x0000373dU); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + while (1) + { + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x0114d52cU), bswap_32big(0x386b9764U), bswap_32big(0x73ca42daU), + bswap_32big(0xa7c4294bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x2020000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x2020000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00002fc0U); + + r_rsip_func101(bswap_32big(0xa9471521U), bswap_32big(0x774cdc21U), bswap_32big(0x387f848dU), + bswap_32big(0xccb62111U)); + } + else + { + r_rsip_func101(bswap_32big(0xdde6385cU), bswap_32big(0xdcb41b2dU), bswap_32big(0x328ee887U), + bswap_32big(0x76f88bdeU)); + + break; + } + } + + WR1_PROG(REG_1404H, 0x19300000U); + WR1_PROG(REG_1400H, 0x00c00111U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xd9634da2U)); + + OFS_ADR = 72; + + WR1_PROG(REG_1404H, 0x19300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000541U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfea630f6U), + bswap_32big(0x45c2ae0bU), + bswap_32big(0xb385cb86U), + bswap_32big(0x2057b232U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x94174653U)); + + OFS_ADR = 144; + + WR1_PROG(REG_1404H, 0x19300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000542U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7d561fc3U), + bswap_32big(0xa4c40e9cU), + bswap_32big(0xa1356e42U), + bswap_32big(0xf5ec4fa8U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x933f58e2U)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x19300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000543U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x51ff7c06U), + bswap_32big(0x558bed30U), + bswap_32big(0x3216d2d2U), + bswap_32big(0x0fb78763U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xe14d5c93U)); + + OFS_ADR = 216; + + WR1_PROG(REG_1404H, 0x19300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000544U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x23599527U), + bswap_32big(0xc8d76b11U), + bswap_32big(0x82635f52U), + bswap_32big(0xb3c2a4c2U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x9bee78e8U)); + + OFS_ADR = 288; + + WR1_PROG(REG_1404H, 0x11200000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000545U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x53bb93fdU), + bswap_32big(0xec245d90U), + bswap_32big(0x5d7c9b28U), + bswap_32big(0x3d0918c3U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x15300000U); + WR1_PROG(REG_1600H, 0x00000b7bU); + WR1_PROG(REG_1608H, 0x80c0001bU); + WR1_PROG(REG_1400H, 0x03430101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + while (1) + { + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xcf4cf38eU), bswap_32big(0x020afd29U), bswap_32big(0x00af941cU), + bswap_32big(0x39507714U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x02527f2eU), bswap_32big(0x403184f7U), bswap_32big(0x14fb28d3U), + bswap_32big(0xe40e6853U)); + + break; + } + else + { + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x933f58e2U)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x13180000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000541U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x00b488f5U), bswap_32big(0xe2077677U), bswap_32big(0x366e26d8U), + bswap_32big(0x7b4a6c90U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xd9634da2U)); + + OFS_ADR = 72; + + WR1_PROG(REG_1404H, 0x19300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000542U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf4ea50e3U), bswap_32big(0x930aa438U), bswap_32big(0x7584d8edU), + bswap_32big(0x73f29ed5U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000541U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x56648348U), bswap_32big(0xc321bc63U), bswap_32big(0x613cda0dU), + bswap_32big(0x424f0251U)); + r_rsip_func055(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x933f58e2U)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x13180000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000546U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x53481bb8U), bswap_32big(0xf096fde8U), bswap_32big(0xfdd55b91U), + bswap_32big(0x1aeb10f0U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xd9634da2U)); + + OFS_ADR = 72; + + WR1_PROG(REG_1404H, 0x19300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000547U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb7ec2b76U), bswap_32big(0x48622633U), bswap_32big(0xca5d036bU), + bswap_32big(0xfe7befefU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x94174653U)); + + OFS_ADR = 144; + + WR1_PROG(REG_1404H, 0x13180000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000543U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe0d9cb00U), bswap_32big(0x2f5ad688U), bswap_32big(0xb8e47143U), + bswap_32big(0xe3a1e7c1U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xe14d5c93U)); + + OFS_ADR = 216; + + WR1_PROG(REG_1404H, 0x19300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000544U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4331cb5bU), bswap_32big(0xe7fb1f5bU), bswap_32big(0xefa89eb3U), + bswap_32big(0x87271464U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1404H, 0x1ed80000U); + WR1_PROG(REG_1400H, 0x00c00101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000542U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3e28f773U), bswap_32big(0x8a9fecfeU), bswap_32big(0xaa4ee8dcU), + bswap_32big(0xae7a96cdU)); + r_rsip_func055(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x94174653U)); + + OFS_ADR = 144; + + WR1_PROG(REG_1404H, 0x13180000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000548U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe61ff5a3U), bswap_32big(0x2cb247f8U), bswap_32big(0xdd9b76abU), + bswap_32big(0x939cc005U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xe14d5c93U)); + + OFS_ADR = 216; + + WR1_PROG(REG_1404H, 0x19300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000549U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5da03a5cU), bswap_32big(0x24313715U), bswap_32big(0x614cee89U), + bswap_32big(0xf88315f2U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x1ed80000U); + WR1_PROG(REG_1400H, 0x00c00101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x14c820feU), bswap_32big(0x0cdfecd2U), bswap_32big(0xc71b247aU), + bswap_32big(0x425b56e8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x933f58e2U)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000545U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xebde67d8U), + bswap_32big(0x03ea280fU), + bswap_32big(0x3c1b26b6U), + bswap_32big(0xf8a7875dU)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x94174653U)); + + OFS_ADR = 144; + + WR1_PROG(REG_1404H, 0x1ec80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000546U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xac0aa1b4U), + bswap_32big(0x366aec0bU), + bswap_32big(0x8dba3c05U), + bswap_32big(0x2b922f80U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000541U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x31357296U), + bswap_32big(0x94317cc8U), + bswap_32big(0x252ad271U), + bswap_32big(0xe2b365e0U)); + r_rsip_func305(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x933f58e2U)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x920740a0U), + bswap_32big(0xf3e5109fU), + bswap_32big(0x7761f4e8U), + bswap_32big(0x07e7ff7bU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xd9634da2U)); + + OFS_ADR = 72; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000547U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x59046d9eU), + bswap_32big(0xf7e4fe60U), + bswap_32big(0xd76cd256U), + bswap_32big(0xb4e19c85U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xe14d5c93U)); + + OFS_ADR = 216; + + WR1_PROG(REG_1404H, 0x1ec80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000548U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6600b9bcU), + bswap_32big(0xb7cecfaaU), + bswap_32big(0x98d343e6U), + bswap_32big(0xb4f76ad9U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000542U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd2b499c6U), + bswap_32big(0xead45d6eU), + bswap_32big(0x2334d23fU), + bswap_32big(0x1621bc29U)); + r_rsip_func305(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xd9634da2U)); + + OFS_ADR = 72; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9464d078U), + bswap_32big(0xfc4e2801U), + bswap_32big(0xe52614d7U), + bswap_32big(0x7462fbadU)); + r_rsip_func016(OFS_ADR); + + r_rsip_func101(bswap_32big(0x2f398a84U), + bswap_32big(0x63398ec9U), + bswap_32big(0xfc51de95U), + bswap_32big(0x0ccf339bU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x94174653U)); + + OFS_ADR = 144; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0971b9b3U), + bswap_32big(0x3f9b66a3U), + bswap_32big(0x62640cafU), + bswap_32big(0x76a3dee8U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x933f58e2U)); + + OFS_ADR = 0; + + WR1_PROG(REG_1404H, 0x1ec80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x951f6a87U), + bswap_32big(0x8aa15a51U), + bswap_32big(0x306075b4U), + bswap_32big(0xd866f2c1U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000543U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8005f1c6U), + bswap_32big(0xfb1a9aa8U), + bswap_32big(0x558990c3U), + bswap_32big(0x3b40bdceU)); + r_rsip_func305(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x94174653U)); + + OFS_ADR = 144; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd803fb33U), + bswap_32big(0xebb58422U), + bswap_32big(0xabec795bU), + bswap_32big(0x30cb057dU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xe14d5c93U)); + + OFS_ADR = 216; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x060f9514U), + bswap_32big(0x83b7ef9cU), + bswap_32big(0x241c8b07U), + bswap_32big(0x6a605418U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xd9634da2U)); + + OFS_ADR = 72; + + WR1_PROG(REG_1404H, 0x1ec80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6f0d7e7cU), + bswap_32big(0x0f1e7902U), + bswap_32big(0x319ec8e5U), + bswap_32big(0x711ad429U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000544U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6a021b57U), + bswap_32big(0x57df69b1U), + bswap_32big(0x8e97125fU), + bswap_32big(0xc62627eeU)); + r_rsip_func305(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xe14d5c93U)); + + OFS_ADR = 216; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbb449c76U), + bswap_32big(0x713a34d1U), + bswap_32big(0xa400470bU), + bswap_32big(0xf3996329U)); + r_rsip_func016(OFS_ADR); + + r_rsip_func101(bswap_32big(0xcb6b16efU), + bswap_32big(0xace48422U), + bswap_32big(0x3452d5faU), + bswap_32big(0x179cd397U)); + } + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x9bee78e8U)); + + OFS_ADR = 288; + + WR1_PROG(REG_1404H, 0x11200000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x420d5ea7U), + bswap_32big(0x1a3099dbU), + bswap_32big(0x2e8c381dU), + bswap_32big(0xe72732c0U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + while (1) + { + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x151fbae3U), bswap_32big(0xfb8adb0fU), bswap_32big(0x3b042ad5U), + bswap_32big(0x979221a5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x20200008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x000033c0U); + + r_rsip_func101(bswap_32big(0x253ade5eU), bswap_32big(0x190e4edfU), bswap_32big(0x2c010649U), + bswap_32big(0x92300968U)); + } + else + { + r_rsip_func101(bswap_32big(0xd87ee3f0U), bswap_32big(0x49cf04a7U), bswap_32big(0xb2fad346U), + bswap_32big(0xbc9540dfU)); + + break; + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xe14d5c93U)); + + OFS_ADR = 216; + + WR1_PROG(REG_1404H, 0x17280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000044U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000054fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2e3a9051U), + bswap_32big(0x740ee11aU), + bswap_32big(0xbe37186dU), + bswap_32big(0xb125ae82U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + while (1) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x7ab81e38U), bswap_32big(0xd06568e8U), bswap_32big(0x36bb363aU), + bswap_32big(0xb5757ff9U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x90380ef4U), bswap_32big(0xae544b11U), bswap_32big(0x3f15c1c9U), + bswap_32big(0x798cd3c9U)); + } + else + { + r_rsip_func101(bswap_32big(0x6d3852e3U), bswap_32big(0x8fdf0541U), bswap_32big(0x65cf6941U), + bswap_32big(0xa6b3936aU)); + + break; + } + } + + WR1_PROG(REG_1600H, 0x3800db60U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xeb6141e3U), + bswap_32big(0xe9eb3966U), + bswap_32big(0x2bd55db2U), + bswap_32big(0x226fe2f1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x88397779U), bswap_32big(0xe6268741U), bswap_32big(0x0e32048aU), + bswap_32big(0x9601bf37U)); + } + else + { + r_rsip_func101(bswap_32big(0x8c20d2c2U), bswap_32big(0x589cc6e2U), bswap_32big(0x87e2f6fdU), + bswap_32big(0x6f5aca9cU)); + } + + WR1_PROG(REG_1600H, 0x000037b9U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func055.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func055.c new file mode 100644 index 0000000000..c21f842d6a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func055.c @@ -0,0 +1,314 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func055 (void) +{ + uint32_t OFS_ADR = 0U; + + WR1_PROG(REG_1600H, 0x0000379dU); + + while (1) + { + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xb2afc141U), bswap_32big(0x44b89cc5U), bswap_32big(0x55a5e2a1U), + bswap_32big(0x99dffeefU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x2020000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14200000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1a380000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x516afcbcU), bswap_32big(0x4d21b6b3U), bswap_32big(0x069ab47cU), + bswap_32big(0x2bb97c4aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1404H, 0x13180000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19300000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x13180000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x19300000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x2121000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x2121000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13180000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19300000U); + WR1_PROG(REG_1608H, 0x81010300U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xbcf1ede3U), + bswap_32big(0xd770d388U), + bswap_32big(0x1af6933fU), + bswap_32big(0xaba770ceU)); + } + else + { + WR1_PROG(REG_1404H, 0x1ec80000U); + WR1_PROG(REG_1600H, 0x00000b7bU); + WR1_PROG(REG_1608H, 0x81c0001bU); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1400H, 0x00c00111U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x22220009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000f55U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x781dd1b0U), + bswap_32big(0xc76bd809U), + bswap_32big(0xb6f78051U), + bswap_32big(0x6e5f424dU)); + r_rsip_func304(); + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x2121000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13180000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1ec80000U); + WR1_PROG(REG_1400H, 0x00c00111U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x9bee78e8U)); + + OFS_ADR = 288; + + WR1_PROG(REG_1404H, 0x1ed80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000f55U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3c082c29U), + bswap_32big(0x11235aaaU), + bswap_32big(0xf16e22e3U), + bswap_32big(0x646ef9d1U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1400H, 0x00c00111U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x22220009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000f55U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf1508e66U), + bswap_32big(0x129727f9U), + bswap_32big(0x3a5e5508U), + bswap_32big(0x9408e4d3U)); + r_rsip_func305(); + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x2121000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19300000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x6ba2e5a3U), + bswap_32big(0xee1adb9bU), + bswap_32big(0x5cc8fa16U), + bswap_32big(0x85250fc8U)); + } + } + else + { + r_rsip_func101(bswap_32big(0xcdb5da5eU), bswap_32big(0x081350ddU), bswap_32big(0xd48cfd0aU), + bswap_32big(0xbc08f52aU)); + + break; + } + } + + WR1_PROG(REG_1600H, 0x000037bcU); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func057.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func057.c new file mode 100644 index 0000000000..8d0232227b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func057.c @@ -0,0 +1,415 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func057 (const uint32_t ARG1[], const uint32_t ARG2[], uint32_t ARG3[]) +{ + uint32_t iLoop = 0U; + uint32_t oLoop = 0U; + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f057U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1d9c643fU), + bswap_32big(0x51f05ae0U), + bswap_32big(0x1a2fbd89U), + bswap_32big(0x4a9f277eU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000ffU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x91115787U), + bswap_32big(0x3dc4b55cU), + bswap_32big(0xcce4258fU), + bswap_32big(0x98a1bd5aU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e4U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000feU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7a34a588U), + bswap_32big(0x9f19faddU), + bswap_32big(0x105d4e65U), + bswap_32big(0x2c6b9c61U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xb45d6191U), + bswap_32big(0x69f02425U), + bswap_32big(0xcdcf3ff3U), + bswap_32big(0xfcd2661cU)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1000H, 0x00010000U); + + r_rsip_func081(); + + WR1_PROG(REG_1600H, 0x00007c01U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + oLoop = 0U; + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + for (iLoop = 0U; iLoop < (INST_DATA_SIZE - 4); ) + { + r_rsip_func100(bswap_32big(0xf78b7c3bU), bswap_32big(0x5bf2abb1U), bswap_32big(0x2dd45823U), + bswap_32big(0x8b9bebacU)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xd900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + iLoop]); + + r_rsip_func101(bswap_32big(0x8c67d4baU), bswap_32big(0x5dbb6346U), bswap_32big(0x36314530U), + bswap_32big(0xe22570ceU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + oLoop = iLoop; + + r_rsip_func101(bswap_32big(0x3c8e1e9eU), bswap_32big(0x8b587a19U), bswap_32big(0x22480e81U), + bswap_32big(0x604ecefeU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000aU) + { + r_rsip_func100(bswap_32big(0xd9e45ba4U), bswap_32big(0x3ee3425fU), bswap_32big(0xda42dcd5U), + bswap_32big(0xaa35d3a6U)); + WR1_PROG(REG_1404H, 0x10000000U); + r_rsip_func061(0, ARG2); + iLoop = 0 + 32; + + WR1_PROG(REG_1404H, 0x10000000U); + r_rsip_func065(0, ARG3); + r_rsip_func100(bswap_32big(0xb747c814U), bswap_32big(0x21e78d2aU), bswap_32big(0x570dc412U), + bswap_32big(0x5b2ccc31U)); + r_rsip_func065(8, ARG3); + r_rsip_func100(bswap_32big(0xfff15fe9U), bswap_32big(0x4730eb1cU), bswap_32big(0xac182b22U), + bswap_32big(0xf6f9539bU)); + r_rsip_func065(16, ARG3); + r_rsip_func100(bswap_32big(0x63681694U), bswap_32big(0x2cd6435cU), bswap_32big(0x26d97b23U), + bswap_32big(0x73d8a97aU)); + r_rsip_func065(24, ARG3); + oLoop = oLoop + 32; + + r_rsip_func100(bswap_32big(0x405e106eU), bswap_32big(0x287e9cefU), bswap_32big(0x1189f507U), + bswap_32big(0x9e9ff40aU)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xd900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + iLoop = iLoop + 4; + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + oLoop]); + oLoop = oLoop + 4; + + WAIT_STS(REG_1A28H, 6, 0); + + r_rsip_func101(bswap_32big(0x36b59a3bU), bswap_32big(0x55dcbb6eU), bswap_32big(0x39143f0dU), + bswap_32big(0x171df73cU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000bU) + { + r_rsip_func100(bswap_32big(0x9690cf2cU), bswap_32big(0x7bce5c8fU), bswap_32big(0xccb52088U), + bswap_32big(0x835c8d5eU)); + WR1_PROG(REG_1404H, 0x10000000U); + r_rsip_func061(0, ARG2); + iLoop = 0 + 32; + + WR1_PROG(REG_1404H, 0x10000000U); + r_rsip_func062(0, ARG3); + r_rsip_func100(bswap_32big(0xf83aee04U), bswap_32big(0x2b223e4dU), bswap_32big(0x5848680cU), + bswap_32big(0x1b78422cU)); + r_rsip_func062(8, ARG3); + r_rsip_func100(bswap_32big(0x124534cfU), bswap_32big(0xe443f2aeU), bswap_32big(0xc81ffa4cU), + bswap_32big(0xfcf24872U)); + r_rsip_func062(16, ARG3); + r_rsip_func100(bswap_32big(0xa2ef1772U), bswap_32big(0xe524a4eaU), bswap_32big(0x7d43abf8U), + bswap_32big(0x92f2280fU)); + r_rsip_func062(24, ARG3); + oLoop = oLoop + 32; + + r_rsip_func100(bswap_32big(0xc44d7458U), bswap_32big(0xc3c8b89eU), bswap_32big(0xf6edcc85U), + bswap_32big(0x87a1a2ffU)); + WR1_PROG(REG_1404H, 0x11100000U); + r_rsip_func061(32, ARG2); + iLoop = 32 + 32; + + WR1_PROG(REG_1404H, 0x11100000U); + r_rsip_func062(32, ARG3); + r_rsip_func100(bswap_32big(0xb03f6da5U), bswap_32big(0x2f58fba3U), bswap_32big(0x9422647eU), + bswap_32big(0x1efb85c2U)); + r_rsip_func062(40, ARG3); + r_rsip_func100(bswap_32big(0x2acb4987U), bswap_32big(0xf5fbd999U), bswap_32big(0x54b43cdeU), + bswap_32big(0x495aef0aU)); + r_rsip_func062(48, ARG3); + r_rsip_func100(bswap_32big(0xcd3086c4U), bswap_32big(0x82afd5cdU), bswap_32big(0xd99519e1U), + bswap_32big(0x4afbc043U)); + r_rsip_func062(56, ARG3); + oLoop = oLoop + 32; + + r_rsip_func101(bswap_32big(0xf0420fadU), bswap_32big(0xd2e744eaU), bswap_32big(0xf7e14ea2U), + bswap_32big(0xd5f37807U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000cU) + { + r_rsip_func100(bswap_32big(0x28e8224fU), bswap_32big(0x63d20dfdU), bswap_32big(0x5bdef589U), + bswap_32big(0xf86b2b83U)); + WR1_PROG(REG_1404H, 0x10000000U); + r_rsip_func063(0, ARG2); + iLoop = 0 + 64; + + WR1_PROG(REG_1404H, 0x10000000U); + r_rsip_func065(0, ARG3); + r_rsip_func100(bswap_32big(0x97c2b947U), bswap_32big(0x484f0b12U), bswap_32big(0x97a74178U), + bswap_32big(0x22faac60U)); + r_rsip_func065(8, ARG3); + r_rsip_func100(bswap_32big(0x5a8bcdd1U), bswap_32big(0x8a0e585dU), bswap_32big(0xaf0c9d37U), + bswap_32big(0x6365655cU)); + r_rsip_func065(16, ARG3); + r_rsip_func100(bswap_32big(0x186833fbU), bswap_32big(0xa8bf2705U), bswap_32big(0x813b7c1aU), + bswap_32big(0x60a1ee73U)); + r_rsip_func065(24, ARG3); + r_rsip_func100(bswap_32big(0xf315072aU), bswap_32big(0x8300d795U), bswap_32big(0xe9258088U), + bswap_32big(0x05c8fb87U)); + r_rsip_func065(32, ARG3); + r_rsip_func100(bswap_32big(0x6c359d20U), bswap_32big(0x92180d08U), bswap_32big(0x560dc733U), + bswap_32big(0x793a44f6U)); + r_rsip_func065(40, ARG3); + r_rsip_func100(bswap_32big(0xd5fcd702U), bswap_32big(0x79e33f9aU), bswap_32big(0xbc282de2U), + bswap_32big(0x90183566U)); + r_rsip_func065(48, ARG3); + r_rsip_func100(bswap_32big(0x7a92f74aU), bswap_32big(0x52470de2U), bswap_32big(0x50d493bbU), + bswap_32big(0x03e04151U)); + r_rsip_func065(56, ARG3); + oLoop = oLoop + 64; + + r_rsip_func100(bswap_32big(0xd11d182bU), bswap_32big(0xb071b621U), bswap_32big(0xa8f29e62U), + bswap_32big(0x7ab7d5e2U)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xd900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + iLoop = iLoop + 4; + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + oLoop]); + oLoop = oLoop + 4; + + WAIT_STS(REG_1A28H, 6, 0); + + r_rsip_func101(bswap_32big(0xac19009bU), bswap_32big(0xf87b8294U), bswap_32big(0x50d45fe1U), + bswap_32big(0xec9f2329U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000dU) + { + r_rsip_func100(bswap_32big(0xad6e80b8U), bswap_32big(0x0fa2d1bfU), bswap_32big(0xe445bb5aU), + bswap_32big(0xb1c7d229U)); + WR1_PROG(REG_1404H, 0x10000000U); + r_rsip_func063(0, ARG2); + iLoop = 0 + 64; + + WR1_PROG(REG_1404H, 0x10000000U); + r_rsip_func062(0, ARG3); + r_rsip_func100(bswap_32big(0xdab49857U), bswap_32big(0x7718798fU), bswap_32big(0xe14af5e9U), + bswap_32big(0x8a3d02e9U)); + r_rsip_func062(8, ARG3); + r_rsip_func100(bswap_32big(0x027d9eb3U), bswap_32big(0xb4bfad26U), bswap_32big(0xa58cff45U), + bswap_32big(0x939ac84cU)); + r_rsip_func062(16, ARG3); + r_rsip_func100(bswap_32big(0xbbfaf311U), bswap_32big(0x92ee6a2fU), bswap_32big(0xe3d82256U), + bswap_32big(0x8ecfbaa9U)); + r_rsip_func062(24, ARG3); + r_rsip_func100(bswap_32big(0x2021b03cU), bswap_32big(0x195766e1U), bswap_32big(0x88c6535dU), + bswap_32big(0x5ec43fd9U)); + r_rsip_func062(32, ARG3); + r_rsip_func100(bswap_32big(0x4788bc1aU), bswap_32big(0x580f048dU), bswap_32big(0x7f3d5b5fU), + bswap_32big(0xaebe64c4U)); + r_rsip_func062(40, ARG3); + r_rsip_func100(bswap_32big(0x97959b92U), bswap_32big(0x2f308f5aU), bswap_32big(0x4b48d814U), + bswap_32big(0xda49080aU)); + r_rsip_func062(48, ARG3); + r_rsip_func100(bswap_32big(0x790137f4U), bswap_32big(0xdf8fdb4aU), bswap_32big(0x72d57a72U), + bswap_32big(0x6f3a69c8U)); + r_rsip_func062(56, ARG3); + oLoop = oLoop + 64; + + r_rsip_func100(bswap_32big(0x01dc96e0U), bswap_32big(0x063094d5U), bswap_32big(0x28d2a8a9U), + bswap_32big(0xf82bf24aU)); + WR1_PROG(REG_1404H, 0x11100000U); + r_rsip_func063(64, ARG2); + iLoop = 64 + 64; + + WR1_PROG(REG_1404H, 0x11100000U); + r_rsip_func062(64, ARG3); + r_rsip_func100(bswap_32big(0x8ea0e088U), bswap_32big(0x90b980c7U), bswap_32big(0x1a00697fU), + bswap_32big(0x04d70a97U)); + r_rsip_func062(72, ARG3); + r_rsip_func100(bswap_32big(0x0b7474afU), bswap_32big(0x6bd14713U), bswap_32big(0x1bc8ba7eU), + bswap_32big(0xb140ac37U)); + r_rsip_func062(80, ARG3); + r_rsip_func100(bswap_32big(0xb5482b2cU), bswap_32big(0x684ae3bdU), bswap_32big(0xb09e4fdcU), + bswap_32big(0xb24eb9ebU)); + r_rsip_func062(88, ARG3); + r_rsip_func100(bswap_32big(0x78d066eaU), bswap_32big(0xe71d7d67U), bswap_32big(0xd8af340eU), + bswap_32big(0xf32bb617U)); + r_rsip_func062(96, ARG3); + r_rsip_func100(bswap_32big(0xa8de069cU), bswap_32big(0x4e9fc512U), bswap_32big(0x541b99fbU), + bswap_32big(0x38eb7b59U)); + r_rsip_func062(104, ARG3); + r_rsip_func100(bswap_32big(0x27dc1b25U), bswap_32big(0xb4705dd3U), bswap_32big(0x29f7e483U), + bswap_32big(0x144a2fb5U)); + r_rsip_func062(112, ARG3); + r_rsip_func100(bswap_32big(0x2496bcafU), bswap_32big(0xab036e21U), bswap_32big(0xd3b37848U), + bswap_32big(0x05d61913U)); + r_rsip_func062(120, ARG3); + oLoop = oLoop + 64; + + r_rsip_func101(bswap_32big(0x8ecd93f9U), bswap_32big(0x41535173U), bswap_32big(0xc416675cU), + bswap_32big(0xa0b1103fU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000012U) + { + for (iLoop = 0U; iLoop < (INST_DATA_SIZE - 4); ) + { + r_rsip_func100(bswap_32big(0x23f19a7dU), bswap_32big(0x9609f129U), bswap_32big(0x6313ecacU), + bswap_32big(0xc36ca68eU)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xd900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + iLoop]); + + r_rsip_func101(bswap_32big(0x2fbfac41U), bswap_32big(0xb085fcd4U), bswap_32big(0xdac79525U), + bswap_32big(0x3ef0d443U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + oLoop = iLoop; + + r_rsip_func101(bswap_32big(0xf9029aadU), bswap_32big(0xdb469de3U), bswap_32big(0x5ade0f46U), + bswap_32big(0x6ba8e912U)); + } + + r_rsip_func100(bswap_32big(0x1f9e302aU), + bswap_32big(0x1d48214dU), + bswap_32big(0xb463381dU), + bswap_32big(0x32afbb34U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + oLoop]); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1cU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func059.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func059.c new file mode 100644 index 0000000000..5fd78db40e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func059.c @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func059 (void) +{ + r_rsip_func100(bswap_32big(0xadc0c725U), + bswap_32big(0xc7568f8dU), + bswap_32big(0x63cda326U), + bswap_32big(0x25d47cfaU)); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x01000000U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x4a060044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e060085U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x78e24cbaU), + bswap_32big(0x50bf9103U), + bswap_32big(0x4eb6c97eU), + bswap_32big(0x65a4b108U)); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x02000000U); + + WR1_PROG(REG_1A24H, 0x0e060095U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func061.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func061.c new file mode 100644 index 0000000000..0afea3a01b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func061.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func061 (const uint32_t ARG1, const uint32_t ARG2[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00001fc1U); + WR1_PROG(REG_182CH, 0x00000700U); + WR1_PROG(REG_1824H, 0xd900890fU); + + for (iLoop = ARG1; iLoop < ARG1 + 32; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func062.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func062.c new file mode 100644 index 0000000000..d8a99ea3fd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func062.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func062 (const uint32_t ARG1, uint32_t ARG2[]) +{ + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7008d07U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[ARG1 + 1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[ARG1 + 5]); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func063.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func063.c new file mode 100644 index 0000000000..2a6fa12e6e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func063.c @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func063 (const uint32_t ARG1, const uint32_t ARG2[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00003fc1U); + WR1_PROG(REG_182CH, 0x00000f00U); + WR1_PROG(REG_1824H, 0xd900890fU); + + for (iLoop = ARG1; iLoop < ARG1 + 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func065.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func065.c new file mode 100644 index 0000000000..4282afa9ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func065.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func065 (const uint32_t ARG1, uint32_t ARG2[]) +{ + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[ARG1 + 1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[ARG1 + 5]); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func068.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func068.c new file mode 100644 index 0000000000..3c2e0c5357 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func068.c @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func068 (void) +{ + r_rsip_func100(bswap_32big(0x89a4702aU), + bswap_32big(0x860ade94U), + bswap_32big(0xcfb8875fU), + bswap_32big(0x57ea3022U)); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x01000000U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x4a060044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e060084U); + WR1_PROG(REG_1608H, 0x81010140U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x3cabdf26U), + bswap_32big(0xb8c6a487U), + bswap_32big(0x7c30475fU), + bswap_32big(0x1864f5d9U)); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x02000000U); + + WR1_PROG(REG_1A24H, 0x0e060094U); + WR1_PROG(REG_1608H, 0x81010140U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func070.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func070.c new file mode 100644 index 0000000000..af49edf13f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func070.c @@ -0,0 +1,118 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func070 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0131ec45U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x014bb610U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x01542614U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x01ba24feU); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x01bb59d6U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1404H, 0x10500000U); + WR1_PROG(REG_1444H, 0x00002fc2U); + WR1_PROG(REG_1A2CH, 0x00000b00U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[24]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x13700000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[28]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[32]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18700000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[36]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[40]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[44]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[48]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10a00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[52]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[56]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18200000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[60]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[64]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[68]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func071.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func071.c new file mode 100644 index 0000000000..f72ebd8dd6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func071.c @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func071 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x017d423aU); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0163c737U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x017c67d8U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0126ddb5U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x01bcfa36U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[4]); + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[8]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[12]); + WR1_PROG(REG_1404H, 0x12080000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[16]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func073.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func073.c new file mode 100644 index 0000000000..2f67907cff --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func073.c @@ -0,0 +1,610 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" +#include "r_rsip_sub_func.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func073 (const uint32_t ARG1[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0x1a17116dU), + bswap_32big(0x1534088dU), + bswap_32big(0x822d9d3aU), + bswap_32big(0x86cf5164U)); + r_rsip_func070(ARG1); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0001dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000000c0U, 0x00000200U, 0x00000160U, 0x0404000aU); + + r_rsip_func_sub001(0x00000160U, 0x00000930U, 0x000001b0U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000930U, 0x00000200U, 0x000001b0U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000160U, 0x00000980U, 0x000001b0U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000980U, 0x00000200U, 0x000001b0U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x4bcdf189U), + bswap_32big(0xaf66475bU), + bswap_32big(0xb52b2d2dU), + bswap_32big(0x3e0f065cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x95486067U), bswap_32big(0xf45456e8U), bswap_32big(0xa5b526f0U), + bswap_32big(0x798882b6U)); + } + else + { + r_rsip_func100(bswap_32big(0xdaaf0924U), bswap_32big(0xf21f9d17U), bswap_32big(0x95199256U), + bswap_32big(0xb2dd032bU)); + + r_rsip_func_sub001(0x00000160U, 0x00000200U, 0x000001b0U, 0x0404000aU); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + r_rsip_func_sub003(0x000000c0U, 0x00000160U, 0x04040002U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8188001fU); + r_rsip_func_sub002(0x00c90021U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x000000c0U, 0x00000480U, 0x04040002U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x000000c0U, 0x00000340U, 0x04040002U); + + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11400000U); + r_rsip_func_sub002(0x00c00021U); + + WR1_PROG(REG_1404H, 0x19800000U); + r_rsip_func_sub002(0x00c002d1U); + + WR1_PROG(REG_1014H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a70U, 0x04040004U); + + r_rsip_func_sub001(0x00000890U, 0x00000160U, 0x000002c8U, 0x04040009U); + + r_rsip_func_sub001(0x00000070U, 0x00000160U, 0x000002f0U, 0x04040009U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1608H, 0x81880001U); + r_rsip_func_sub002(0x00c90021U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a20U, 0x04040002U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x8188001fU); + r_rsip_func_sub002(0x00c90021U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a48U, 0x04040002U); + + r_rsip_func100(bswap_32big(0x95ce33b6U), bswap_32big(0x0caec020U), bswap_32big(0x3d68910fU), + bswap_32big(0x726ba7bdU)); + r_rsip_func071(ARG1); + + r_rsip_func_sub001(0x00000200U, 0x00000160U, 0x00000b10U, 0x04040009U); + + r_rsip_func_sub001(0x00000228U, 0x00000160U, 0x00000b38U, 0x04040009U); + + r_rsip_func_sub001(0x00000a70U, 0x00000160U, 0x00000b60U, 0x04040009U); + + r_rsip_func_sub001(0x00000b10U, 0x00000a20U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000a20U, 0x00000b10U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000b38U, 0x00000a48U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000a48U, 0x00000b38U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xf2c73929U), bswap_32big(0x543811e5U), bswap_32big(0x274e655eU), + bswap_32big(0xcb1a2177U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000a70U); + r_rsip_func_sub003(0x00000070U, 0x00000c50U, 0x04040013U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x7bc13891U), bswap_32big(0x2d588ab0U), bswap_32big(0xaba1ee5aU), + bswap_32big(0x1f0e61fcU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000b60U); + r_rsip_func_sub003(0x000002f0U, 0x00000c50U, 0x04040014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xa796a82aU), bswap_32big(0x0b15b4d8U), bswap_32big(0x144272e1U), + bswap_32big(0xc1f8f6ecU)); + } + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1404H, 0x14600000U); + WR1_PROG(REG_1608H, 0x80880001U); + r_rsip_func_sub002(0x03430021U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1404H, 0x13200000U); + WR1_PROG(REG_1608H, 0x80880001U); + r_rsip_func_sub002(0x03430021U); + + WR1_PROG(REG_1404H, 0x11600000U); + r_rsip_func_sub002(0x00c000f1U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000034a1U); + + WR1_PROG(REG_1600H, 0x00026ca5U); + + WR1_PROG(REG_1600H, 0x00003865U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x00003885U); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x01816ca3U); + WR1_PROG(REG_1600H, 0x01816ca4U); + WR1_PROG(REG_1600H, 0x00016c63U); + WR1_PROG(REG_1600H, 0x00016c84U); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0001dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000200U, 0x00000160U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000250U, 0x00000160U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x191767f0U), + bswap_32big(0xabc6db42U), + bswap_32big(0x9992ee17U), + bswap_32big(0x44d567baU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x000002f0U, 0x00000250U, 0x04040014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x0bf72d59U), + bswap_32big(0x410c46e2U), + bswap_32big(0xf26de175U), + bswap_32big(0x5aa05d25U)); + } + else + { + r_rsip_func101(bswap_32big(0x8cec993eU), + bswap_32big(0xa3e7c7c2U), + bswap_32big(0x39305501U), + bswap_32big(0xbed293bfU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xbdc2f467U), + bswap_32big(0x6e7526a0U), + bswap_32big(0x242438bfU), + bswap_32big(0x5047ecc5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x3b8dc878U), + bswap_32big(0x344a8884U), + bswap_32big(0x9a078a77U), + bswap_32big(0xefdd58cfU)); + + WR1_PROG(REG_1404H, 0x11400000U); + r_rsip_func_sub002(0x00c00021U); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func_sub001(0x00000a20U, 0x00000160U, 0x00000430U, 0x04040009U); + + r_rsip_func_sub001(0x00000a48U, 0x00000160U, 0x00000458U, 0x04040009U); + + r_rsip_func_sub001(0x00000a70U, 0x00000160U, 0x00000480U, 0x04040009U); + + r_rsip_func101(bswap_32big(0x30231137U), + bswap_32big(0xfd6f9e09U), + bswap_32big(0xdfe25bfdU), + bswap_32big(0x6df51643U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func_sub001(0x00000b10U, 0x00000160U, 0x00000430U, 0x04040009U); + + r_rsip_func_sub001(0x00000b38U, 0x00000160U, 0x00000458U, 0x04040009U); + + r_rsip_func_sub001(0x00000b60U, 0x00000160U, 0x00000480U, 0x04040009U); + + r_rsip_func101(bswap_32big(0xa8fe4a11U), + bswap_32big(0x10661ad1U), + bswap_32big(0xc7063800U), + bswap_32big(0xd95f9173U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func_sub001(0x00000c00U, 0x00000160U, 0x00000430U, 0x04040009U); + + r_rsip_func_sub001(0x00000c28U, 0x00000160U, 0x00000458U, 0x04040009U); + + r_rsip_func_sub001(0x00000c50U, 0x00000160U, 0x00000480U, 0x04040009U); + + r_rsip_func101(bswap_32big(0xd4201b8dU), + bswap_32big(0xb71b39cdU), + bswap_32big(0x6aaa4ad1U), + bswap_32big(0x9684b655U)); + } + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0001dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000200U, 0x00000160U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000250U, 0x00000160U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x815d4972U), + bswap_32big(0x35424cf3U), + bswap_32big(0x32df663cU), + bswap_32big(0xf3b8ee50U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func_sub001(0x00000430U, 0x00000160U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000480U, 0x00000160U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x4ba41fffU), + bswap_32big(0xf81310a6U), + bswap_32big(0xf8796bdfU), + bswap_32big(0xaab20d7fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func_sub001(0x00000200U, 0x00000430U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000430U, 0x00000200U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000228U, 0x00000458U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000458U, 0x00000228U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000250U, 0x00000480U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000480U, 0x00000250U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x2635d046U), + bswap_32big(0x20b329a4U), + bswap_32big(0xde498607U), + bswap_32big(0x5f44fecaU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + r_rsip_func_sub003(0x00000070U, 0x00000250U, 0x04040013U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xcbfc8dfbU), bswap_32big(0x5c1f6da9U), + bswap_32big(0x5eb382a7U), bswap_32big(0xcb77f9e4U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x000002f0U, 0x00000250U, 0x04040014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x121ad6a0U), bswap_32big(0x4abdaa1dU), + bswap_32big(0x87efc800U), bswap_32big(0xc9b59ee2U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x4437f798U), + bswap_32big(0xc2603db6U), + bswap_32big(0xdb097d26U), + bswap_32big(0x6e736af2U)); + } + } + else + { + WR1_PROG(REG_1404H, 0x11400000U); + r_rsip_func_sub002(0x00c00021U); + + r_rsip_func_sub001(0x00000430U, 0x00000160U, 0x00000200U, 0x04040009U); + + r_rsip_func_sub001(0x00000458U, 0x00000160U, 0x00000228U, 0x04040009U); + + r_rsip_func_sub001(0x00000480U, 0x00000160U, 0x00000250U, 0x04040009U); + + r_rsip_func101(bswap_32big(0x3de3f17dU), + bswap_32big(0x87271290U), + bswap_32big(0x9c1a9c8fU), + bswap_32big(0x9e585bafU)); + } + } + else + { + r_rsip_func101(bswap_32big(0x8b0ae415U), + bswap_32big(0x7b46fb70U), + bswap_32big(0xeb25ac6eU), + bswap_32big(0xd4382c1dU)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + r_rsip_func101(bswap_32big(0xf4655730U), + bswap_32big(0xf928fbbeU), + bswap_32big(0x4abbd73fU), + bswap_32big(0xf874d7deU)); + } + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002c20U); + + r_rsip_func101(bswap_32big(0xa2384d69U), bswap_32big(0xf9a4974cU), bswap_32big(0x779a3b1cU), + bswap_32big(0xda9e0812U)); + } + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0001dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000250U, 0x000002a0U, 0x000002f0U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x96e6a243U), bswap_32big(0xc9efea35U), bswap_32big(0xea881343U), + bswap_32big(0x77955462U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xfa7deb28U), bswap_32big(0x7d91d2abU), bswap_32big(0x884549b3U), + bswap_32big(0x87d6ca43U)); + } + else + { + r_rsip_func100(bswap_32big(0xcc82ccacU), bswap_32big(0xd1cdc457U), bswap_32big(0x32e6b3e2U), + bswap_32big(0xa5d19c08U)); + + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x00000070U, 0x000002a0U, 0x04040004U); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + r_rsip_func_sub002(0x00c0001dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000070U, 0x00000160U, 0x00000110U, 0x0404000aU); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x00000070U, 0x000002a0U, 0x04040002U); + + r_rsip_func_sub001(0x000002a0U, 0x00000930U, 0x000001b0U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000930U, 0x000002a0U, 0x000001b0U, 0x0404000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x785aa023U), bswap_32big(0x28d92742U), bswap_32big(0x352febc3U), + bswap_32big(0xced84b2eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x14c1a0a2U), + bswap_32big(0x99dcd412U), + bswap_32big(0x0f5bf522U), + bswap_32big(0xb0da0764U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x797935bbU); + + r_rsip_func101(bswap_32big(0x925a047dU), + bswap_32big(0x795335c8U), + bswap_32big(0x389791f7U), + bswap_32big(0x58dee35dU)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func074.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func074.c new file mode 100644 index 0000000000..b012a82b80 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func074.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func074 (void) +{ + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000023U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001dU); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000017U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000015U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000013U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00000080U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func075.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func075.c new file mode 100644 index 0000000000..6dcc67ccd7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func075.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func075 (void) +{ + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000022U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001cU); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000016U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000014U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000012U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00000080U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func076.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func076.c new file mode 100644 index 0000000000..a02c157612 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func076.c @@ -0,0 +1,28 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func076 (void) +{ + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000019U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x00000080U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func077.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func077.c new file mode 100644 index 0000000000..cca223e821 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func077.c @@ -0,0 +1,28 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func077 (void) +{ + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000018U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001eU); + WR1_PROG(REG_1600H, 0x00000080U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func078.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func078.c new file mode 100644 index 0000000000..d5cd47110e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func078.c @@ -0,0 +1,132 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func078 (const uint32_t ARG1[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x018d3a5eU)); + + WR1_PROG(REG_1444H, 0x00005fc2U); + WR1_PROG(REG_1A2CH, 0x00001700U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + + WR1_PROG(REG_1404H, 0x10300000U); + for (iLoop = 36U; iLoop < 52U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x13500000U); + for (iLoop = 52U; iLoop < 68U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x18500000U); + for (iLoop = 68U; iLoop < 84U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x18a00000U); + for (iLoop = 84U; iLoop < 100U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10800000U); + for (iLoop = 100U; iLoop < 116U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x18000000U); + for (iLoop = 116U; iLoop < 132U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[132]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func079.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func079.c new file mode 100644 index 0000000000..ea1b6b76ca --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func079.c @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func079 (const uint32_t ARG1[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x01a9d8a8U)); + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x00000700U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + + WR1_PROG(REG_1404H, 0x11800000U); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x11c80000U); + for (iLoop = 16U; iLoop < 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[32]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func081.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func081.c new file mode 100644 index 0000000000..ae92d02875 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func081.c @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func081 (void) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x00003424U); + + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1600H, 0x0000000aU); + WR1_PROG(REG_1600H, 0x10000821U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1600H, 0x342028e4U); + WR1_PROG(REG_1600H, 0x10000821U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1600H, 0x1000b420U); + WR1_PROG(REG_1600H, 0x0000000cU); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000012U); + + WR1_PROG(REG_1600H, 0x0000b7a0U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1444H, 0x00000ba7U); + WR1_PROG(REG_1608H, 0x808c001fU); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000012U)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000014U)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000016U)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000018U)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000001cU)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000001eU)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000020U)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000eU)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000010U)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000022U)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000024U)); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 12U; iLoop++) + { + WR1_PROG(REG_1600H, 0x00003bdfU); + + WR1_PROG(REG_1600H, 0x3800089eU); + WR1_PROG(REG_1600H, 0x10003427U); + + WR1_PROG(REG_1600H, 0x000027fdU); + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func082.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func082.c new file mode 100644 index 0000000000..a7c55390c1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func082.c @@ -0,0 +1,110 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func082 (void) +{ + r_rsip_func100(bswap_32big(0x85e2aebeU), + bswap_32big(0x98480a19U), + bswap_32big(0xffcf0a19U), + bswap_32big(0x4eb8c805U)); + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x000001d0U); + WR1_PROG(REG_1608H, 0x8188000aU); + + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x24fa535aU), + bswap_32big(0x33c4841dU), + bswap_32big(0x567dacccU), + bswap_32big(0x475ab5a9U)); + WR1_PROG(REG_1A24H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x9cef12b2U), + bswap_32big(0x31d8c68fU), + bswap_32big(0x94279a36U), + bswap_32big(0xbda605daU)); + + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x000001c0U); + WR1_PROG(REG_1608H, 0x8184000aU); + + WR1_PROG(REG_1A24H, 0x080000c5U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x0b040104U); + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x01000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009105U); + + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x02000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009105U); + + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x01420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func083.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func083.c new file mode 100644 index 0000000000..53da2143fa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func083.c @@ -0,0 +1,210 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func083 (const uint32_t ARG1[]) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x0568b4e1U), + bswap_32big(0xbf0433caU), + bswap_32big(0x66adef04U), + bswap_32big(0xde527ecdU)); + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00002840U); + + WR1_PROG(REG_1608H, 0x81010040U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x00003466U); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1400H, 0x12490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00086c63U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0x821546c5U), bswap_32big(0xe5cbedc8U), bswap_32big(0x3782e44eU), + bswap_32big(0x6a9ecf45U)); + } + + WR1_PROG(REG_1600H, 0x38000845U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x5a1e4294U), + bswap_32big(0xb7b2d990U), + bswap_32big(0x6074e52eU), + bswap_32big(0x73069a3cU)); + + WR1_PROG(REG_1600H, 0x000034e6U); + + WR1_PROG(REG_1600H, 0x00036c00U); + WR1_PROG(REG_1600H, 0x00004400U); + + WR1_PROG(REG_1608H, 0x81010160U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000001U); + + for (iLoop = 1; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003506U); + WR1_PROG(REG_1600H, 0x01807507U); + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1400H, 0x02490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e6U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0x20482510U), bswap_32big(0x05a4e180U), bswap_32big(0xa3667c53U), + bswap_32big(0xe8d7b0fbU)); + } + + WR1_PROG(REG_1600H, 0x38000965U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008ec0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x84d3852eU), + bswap_32big(0xe3377619U), + bswap_32big(0x415df6ebU), + bswap_32big(0x364c220bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x01807507U); + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1400H, 0x02490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x645141fcU), bswap_32big(0x6939e82aU), bswap_32big(0xe9f488bbU), + bswap_32big(0x4a7740b8U)); + } + + r_rsip_func100(bswap_32big(0xf5fcea36U), + bswap_32big(0xd41ed011U), + bswap_32big(0x386435cbU), + bswap_32big(0x3a0dbf36U)); + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x00026800U); + WR1_PROG(REG_1600H, 0x0000240bU); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00002840U); + + WR1_PROG(REG_1600H, 0x00008c40U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1608H, 0x81010040U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x000008a5U); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1400H, 0x00400005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0x007ba068U), bswap_32big(0xf1369610U), bswap_32big(0x1b6cbcc6U), + bswap_32big(0xa9a88bbeU)); + } + + WR1_PROG(REG_1600H, 0x38000845U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_2030H, 4, 1); + + WAIT_STS(REG_1828H, 6, 0); + WR1_PROG(REG_143CH, 0x00000400U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x8084001eU); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func086.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func086.c new file mode 100644 index 0000000000..b8d988a78d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func086.c @@ -0,0 +1,120 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func086 (const uint32_t ARG1[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0123ba68U)); + + WR1_PROG(REG_1444H, 0x000077c2U); + WR1_PROG(REG_1A2CH, 0x00001d00U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + + WR1_PROG(REG_1404H, 0x10200000U); + for (iLoop = 44U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x13400000U); + for (iLoop = 64U; iLoop < 84U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x18400000U); + for (iLoop = 84U; iLoop < 104U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x18900000U); + for (iLoop = 104U; iLoop < 124U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10700000U); + for (iLoop = 124U; iLoop < 144U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x17f00000U); + for (iLoop = 144U; iLoop < 164U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func087.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func087.c new file mode 100644 index 0000000000..50a749c31e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func087.c @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func087 (const uint32_t ARG1[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x01783e10U)); + + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x00000900U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + + WR1_PROG(REG_1404H, 0x11600000U); + for (iLoop = 0U; iLoop < 20U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x11b00000U); + for (iLoop = 20U; iLoop < 40U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[40]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func088.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func088.c new file mode 100644 index 0000000000..0c236acefc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func088.c @@ -0,0 +1,546 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func088 (void) +{ + WR1_PROG(REG_1600H, 0x0000373dU); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000430U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000430U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f08801U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6ea23088U), + bswap_32big(0xfa6e2d6eU), + bswap_32big(0xcfe32205U), + bswap_32big(0x0337730bU)); + r_rsip_func113(); + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f08802U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9771bb05U), + bswap_32big(0x8694b075U), + bswap_32big(0x21f1dcd5U), + bswap_32big(0x6b27adc1U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000430U); + WR1_PROG(REG_1020H, 0x00000480U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1404H, 0x14380000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000458U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000458U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x93d63f27U), + bswap_32big(0x90d501adU), + bswap_32big(0xbf374952U), + bswap_32big(0x268844abU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x45c2a524U), bswap_32big(0x4558eb0cU), bswap_32big(0x635216f0U), + bswap_32big(0x89d6656cU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14100000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_1020H, 0x000002c8U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x9f5015daU), bswap_32big(0xc9c28d47U), bswap_32big(0x483086fbU), + bswap_32big(0x05835c4fU)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x04040015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000520U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xd52827ccU), bswap_32big(0xeebd3a80U), bswap_32big(0x52d2ce51U), + bswap_32big(0xf9880cfaU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xd64913e3U), bswap_32big(0xffd323e0U), bswap_32big(0x03064f94U), + bswap_32big(0xb6005c6fU)); + } + else + { + r_rsip_func100(bswap_32big(0xd8c562b6U), bswap_32big(0xd6a0f25aU), bswap_32big(0x3675fe30U), + bswap_32big(0x42c6059dU)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x04040015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x4d765037U), bswap_32big(0x54f029f0U), bswap_32big(0x0f041113U), + bswap_32big(0xd92038f8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xf8c0f17dU), + bswap_32big(0xc73c1358U), + bswap_32big(0xaa3c8c76U), + bswap_32big(0x8cae2191U)); + } + else + { + r_rsip_func100(bswap_32big(0x1b1aed91U), + bswap_32big(0xf1a3373aU), + bswap_32big(0x55dd78ffU), + bswap_32big(0xf8b1c848U)); + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000520U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000548U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000548U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000520U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x12d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x78c59514U), + bswap_32big(0xcdfbbaecU), + bswap_32big(0x2e5f93fdU), + bswap_32big(0x8c9c33efU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xe26e6ebdU), + bswap_32big(0xc9e4ad34U), + bswap_32big(0x8fbcdaddU), + bswap_32big(0x825b0dc8U)); + } + else + { + r_rsip_func100(bswap_32big(0x475a1149U), + bswap_32big(0xc6e70b17U), + bswap_32big(0xbe287bacU), + bswap_32big(0x1354735aU)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000228U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x618c5618U); + + r_rsip_func101(bswap_32big(0x4e32590dU), + bswap_32big(0x770fd1cfU), + bswap_32big(0xb2366702U), + bswap_32big(0xfa9976d7U)); + } + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x618c5618U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x000037b9U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func089.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func089.c new file mode 100644 index 0000000000..c8f878b535 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func089.c @@ -0,0 +1,565 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func089 (void) +{ + WR1_PROG(REG_1600H, 0x0000373dU); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000410U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000410U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f08901U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x05afaf4bU), + bswap_32big(0xc3bc3dfdU), + bswap_32big(0x378d79e6U), + bswap_32big(0xddde4921U)); + r_rsip_func113(); + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f08902U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa82abe92U), + bswap_32big(0x3f1650e8U), + bswap_32big(0x9ab4a03eU), + bswap_32big(0x6d11d681U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f08903U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x04e4a640U), + bswap_32big(0x7bd374e5U), + bswap_32big(0x94394412U), + bswap_32big(0x97c5ea8bU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000410U); + WR1_PROG(REG_1020H, 0x00000480U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1404H, 0x14180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000448U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000448U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xa76beb69U), + bswap_32big(0x9fe28779U), + bswap_32big(0x3e63d088U), + bswap_32big(0xcd78798eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x29664332U), bswap_32big(0x8657bc14U), bswap_32big(0x7f3293fdU), + bswap_32big(0x2ebe2411U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13e00000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000410U); + WR1_PROG(REG_1020H, 0x000002b8U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000410U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x9fb33d55U), bswap_32big(0xc23d707aU), bswap_32big(0x57dc6480U), + bswap_32big(0xd95a6cdaU)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x06060015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000500U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xfb7a7279U), bswap_32big(0x9624a144U), bswap_32big(0x317f0d97U), + bswap_32big(0x241129a5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x930559e7U), bswap_32big(0x13f5f143U), bswap_32big(0x7679ca93U), + bswap_32big(0xd4e80e74U)); + } + else + { + r_rsip_func100(bswap_32big(0xe698df73U), bswap_32big(0xdcf7e59eU), bswap_32big(0xbb782fedU), + bswap_32big(0x0e29313dU)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x06060015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x189e6a5aU), bswap_32big(0x94ba0e4cU), bswap_32big(0xf67fffceU), + bswap_32big(0x6c0fd67fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x1aa895a0U), + bswap_32big(0x0544f462U), + bswap_32big(0xa6be4254U), + bswap_32big(0xcbfbbbc7U)); + } + else + { + r_rsip_func100(bswap_32big(0x580e8169U), + bswap_32big(0x50fc721dU), + bswap_32big(0x860df3c6U), + bswap_32big(0x11440969U)); + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000500U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000538U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000538U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000500U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x12c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xd9ca762bU), + bswap_32big(0x8f48a563U), + bswap_32big(0xad4403bdU), + bswap_32big(0xc03cb2f7U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xae5114fdU), + bswap_32big(0xbdadc080U), + bswap_32big(0x8f7cc9a8U), + bswap_32big(0xf26a5a07U)); + } + else + { + r_rsip_func100(bswap_32big(0x9ce9521bU), + bswap_32big(0xdf15202eU), + bswap_32big(0xa1ca1753U), + bswap_32big(0x4f9c27b5U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000218U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x1714dcbaU); + + r_rsip_func101(bswap_32big(0x96fac04fU), + bswap_32big(0xb489a640U), + bswap_32big(0x06b3a826U), + bswap_32big(0x58a07fd3U)); + } + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x1714dcbaU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x000037b9U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func090.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func090.c new file mode 100644 index 0000000000..47c73cbf8c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func090.c @@ -0,0 +1,584 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func090 (void) +{ + WR1_PROG(REG_1600H, 0x0000373dU); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003f0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000003f0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09001U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x146efdfaU), + bswap_32big(0xfd2f475aU), + bswap_32big(0x6477acd1U), + bswap_32big(0x8b500af8U)); + r_rsip_func113(); + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09002U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x522c8c7bU), + bswap_32big(0x680bbfc5U), + bswap_32big(0x7593b7e9U), + bswap_32big(0x0f87ff5dU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09003U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x000b6d47U), + bswap_32big(0xe24b3cefU), + bswap_32big(0x3c991f7aU), + bswap_32big(0x8fa72b7cU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09004U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4a77a2ebU), + bswap_32big(0xcf0adf66U), + bswap_32big(0x0f6b1e2bU), + bswap_32big(0x13cdf571U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000003f0U); + WR1_PROG(REG_1020H, 0x00000480U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1404H, 0x13f80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000438U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000438U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x7b9ab5a1U), + bswap_32big(0xc9e75f70U), + bswap_32big(0xd0d198deU), + bswap_32big(0x72f479afU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xa120cc82U), bswap_32big(0x6dc2dee0U), bswap_32big(0xd7da71cfU), + bswap_32big(0x7b065620U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13b00000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x000003f0U); + WR1_PROG(REG_1020H, 0x000002a8U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000003f0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x9f659b48U), bswap_32big(0x3f1f3f6bU), bswap_32big(0x1836eeebU), + bswap_32big(0x75bcf669U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x08080015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000004e0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xa78fb95eU), bswap_32big(0x939c3302U), bswap_32big(0x82e97960U), + bswap_32big(0xbed0aa1bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x847e2179U), bswap_32big(0x8fe44a08U), bswap_32big(0xaa6c1ebcU), + bswap_32big(0x0cc1882aU)); + } + else + { + r_rsip_func100(bswap_32big(0xabcb0a0fU), bswap_32big(0x7c251845U), bswap_32big(0xee97c110U), + bswap_32big(0xdc3d1906U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x08080015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xd9f79d72U), bswap_32big(0xe905c49eU), bswap_32big(0xe962554dU), + bswap_32big(0x599d7a7dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xed590de9U), + bswap_32big(0x3b4d5a05U), + bswap_32big(0x5abc4d98U), + bswap_32big(0x2df5cc3eU)); + } + else + { + r_rsip_func100(bswap_32big(0x139f3739U), + bswap_32big(0x4049c13eU), + bswap_32big(0x495a2bcdU), + bswap_32big(0x2df01342U)); + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000004e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000528U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000528U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000004e0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x12b00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xeb8d1d62U), + bswap_32big(0xa755d3cfU), + bswap_32big(0x195f4c82U), + bswap_32big(0xfd7a9716U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x720de485U), + bswap_32big(0x07e1bcafU), + bswap_32big(0xabc24dedU), + bswap_32big(0x06ae438cU)); + } + else + { + r_rsip_func100(bswap_32big(0x345bc152U), + bswap_32big(0x256d9aa7U), + bswap_32big(0x9562dbfaU), + bswap_32big(0xb61b9073U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000208U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x1b8be139U); + + r_rsip_func101(bswap_32big(0x5c6be6c6U), + bswap_32big(0xd96bdaaaU), + bswap_32big(0xd6ecd6ebU), + bswap_32big(0xe05c243cU)); + } + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x1b8be139U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x000037b9U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func091.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func091.c new file mode 100644 index 0000000000..7d06794ccb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func091.c @@ -0,0 +1,603 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func091 (void) +{ + WR1_PROG(REG_1600H, 0x0000373dU); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09101U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3de075e8U), + bswap_32big(0x1a41184cU), + bswap_32big(0xd065c5c7U), + bswap_32big(0x03a784e6U)); + r_rsip_func113(); + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09102U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x42e9f698U), + bswap_32big(0xa79a4ec6U), + bswap_32big(0x77e3b250U), + bswap_32big(0x37b7205eU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09103U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfd1c7dd9U), + bswap_32big(0x9edb7d40U), + bswap_32big(0x1b143160U), + bswap_32big(0x30361622U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09104U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbeb89ebdU), + bswap_32big(0xf930ebd1U), + bswap_32big(0x96788c89U), + bswap_32big(0xda7aff3eU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00f09105U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xafad0640U), + bswap_32big(0x3515d4cbU), + bswap_32big(0x5d57d18cU), + bswap_32big(0xc5de0bd7U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000003e0U); + WR1_PROG(REG_1020H, 0x00000480U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1404H, 0x13e80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x45038653U), + bswap_32big(0x97f8962cU), + bswap_32big(0x9b6b2223U), + bswap_32big(0x3893c652U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x0d682d78U), bswap_32big(0xa24969e3U), bswap_32big(0x62f979f8U), + bswap_32big(0xac30c52cU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13980000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xbef74487U), bswap_32big(0x3ecd92e4U), bswap_32big(0x829a5c2dU), + bswap_32big(0x0f6931f4U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x09090015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000004d0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x3791dc9bU), bswap_32big(0x610720b5U), bswap_32big(0xabc3a633U), + bswap_32big(0xc07cba9aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xe70b82fbU), bswap_32big(0xabf095caU), bswap_32big(0x49486f9cU), + bswap_32big(0xd6566215U)); + } + else + { + r_rsip_func100(bswap_32big(0xe7729f5cU), bswap_32big(0x26178a74U), bswap_32big(0xe18b5794U), + bswap_32big(0x09e90530U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x09090015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x38c5b2eaU), bswap_32big(0x0e5a6c1bU), bswap_32big(0xd1089241U), + bswap_32big(0x2860aa6dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x61164a14U), + bswap_32big(0x67e2b504U), + bswap_32big(0xb49689b2U), + bswap_32big(0x974b8da1U)); + } + else + { + r_rsip_func100(bswap_32big(0x50e8870cU), + bswap_32big(0x724b086bU), + bswap_32big(0xf21fa813U), + bswap_32big(0xe3e7157cU)); + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000004d0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000520U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000520U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000004d0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x12a80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x6a964e25U), + bswap_32big(0xc775c3a2U), + bswap_32big(0xe504b19eU), + bswap_32big(0x57b3bfb0U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x4bad2f29U), + bswap_32big(0xa0d6cf16U), + bswap_32big(0x02d82627U), + bswap_32big(0xbb1abb25U)); + } + else + { + r_rsip_func100(bswap_32big(0xfd18a6f6U), + bswap_32big(0x4d152486U), + bswap_32big(0x8006344eU), + bswap_32big(0x71cfccd3U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x313622d7U); + + r_rsip_func101(bswap_32big(0x9bce78ceU), + bswap_32big(0xe8f9b531U), + bswap_32big(0x769390ddU), + bswap_32big(0xefa73291U)); + } + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x313622d7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x000037b9U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func092.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func092.c new file mode 100644 index 0000000000..8a5fcd4431 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func092.c @@ -0,0 +1,174 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func092 (void) +{ + r_rsip_func100(bswap_32big(0xd4026ab7U), + bswap_32big(0x4cb770aaU), + bswap_32big(0x13d66d1dU), + bswap_32big(0x475c04ffU)); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x01000000U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x4a060044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e060084U); + WR1_PROG(REG_1608H, 0x81010140U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xda78a32dU), + bswap_32big(0x8e38a4c3U), + bswap_32big(0x0a6c4ff5U), + bswap_32big(0x1be859eaU)); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1600H, 0x02000000U); + + WR1_PROG(REG_1A24H, 0x0e060094U); + WR1_PROG(REG_1608H, 0x81010140U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x300032a0U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b6e0U); + WR1_PROG(REG_1600H, 0x1204c99cU); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b6e0U); + WR1_PROG(REG_1600H, 0xa9ed4879U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b6e0U); + WR1_PROG(REG_1600H, 0x7c182e99U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x00008ee0U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x000092e0U); + WR1_PROG(REG_1600H, 0x01000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009104U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008ee0U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x000092e0U); + WR1_PROG(REG_1600H, 0x02000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009044U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0x6aca5809U), + bswap_32big(0x331407fbU), + bswap_32big(0x0de35e2cU), + bswap_32big(0x40b6223eU)); + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x34a533c2U), + bswap_32big(0x58750b30U), + bswap_32big(0x1133044cU), + bswap_32big(0x6f64466fU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008ec0U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x000092c0U); + WR1_PROG(REG_1600H, 0x01000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009104U); + WR1_PROG(REG_1608H, 0x810102c0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008ec0U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1600H, 0x000092c0U); + WR1_PROG(REG_1600H, 0x02000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009044U); + WR1_PROG(REG_1608H, 0x810102c0U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0xd151f813U), + bswap_32big(0x3dd3ca1cU), + bswap_32big(0xf9386f7bU), + bswap_32big(0xfd4765d4U)); + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x87ae7eedU), + bswap_32big(0x9dc63c83U), + bswap_32big(0x34600170U), + bswap_32big(0x7a232d88U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func100.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func100.c new file mode 100644 index 0000000000..5e0b04dc11 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func100.c @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func100 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_1A24H, 0x0a0701f5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, ARG1, ARG2, ARG3, ARG4); + WAIT_STS(REG_1A28H, 16, 0); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func101.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func101.c new file mode 100644 index 0000000000..86840e3dda --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func101.c @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func101 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_1A24H, 0x0a0701e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, ARG1, ARG2, ARG3, ARG4); + WAIT_STS(REG_1A28H, 17, 0); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func102.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func102.c new file mode 100644 index 0000000000..43b8c7e960 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func102.c @@ -0,0 +1,23 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func102 (uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_1A24H, 0x0a0701d5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, ARG1, ARG2, ARG3, ARG4); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func103.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func103.c new file mode 100644 index 0000000000..ddbe5900d8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func103.c @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func103 (void) +{ + r_rsip_func100(bswap_32big(0xa65e93d4U), + bswap_32big(0x3be84215U), + bswap_32big(0x521e4cafU), + bswap_32big(0xf50c43a4U)); + WR1_PROG(REG_1444H, 0x000004a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07328c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07328d04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07328d04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1404H, 0x1fd80000U); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07328d04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x06328074U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1404H, 0x1fd80000U); + WR1_PROG(REG_1A24H, 0x080000a5U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xc504ca52U), + bswap_32big(0x2669871fU), + bswap_32big(0x4e1f35b8U), + bswap_32big(0x14c73cb2U)); + WR1_PROG(REG_1A24H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func113.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func113.c new file mode 100644 index 0000000000..62ffb1017d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func113.c @@ -0,0 +1,78 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func113 (void) +{ + r_rsip_func100(bswap_32big(0xb29f684eU), + bswap_32big(0x9ba210dcU), + bswap_32big(0x359e4e1eU), + bswap_32big(0x45b83b3fU)); + WR1_PROG(REG_1444H, 0x000004a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07328c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07328d04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07328d04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x800402a0U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07328d04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x06328074U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x080000a5U); + WR1_PROG(REG_1608H, 0x810402a0U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x76b4812fU), + bswap_32big(0x526299e0U), + bswap_32big(0x3c83c807U), + bswap_32big(0x76eee210U)); + WR1_PROG(REG_1A24H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func202.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func202.c new file mode 100644 index 0000000000..6a684fb43b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func202.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func202 (void) +{ + WR1_PROG(REG_1408H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00000000U); + WR1_PROG(REG_1A24H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00000900U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func214.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func214.c new file mode 100644 index 0000000000..321f67d794 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func214.c @@ -0,0 +1,26 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func214 (void) +{ + WR1_PROG(REG_1408H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00000400U); + WR1_PROG(REG_143CH, 0x00000600U); + WR1_PROG(REG_143CH, 0x00000500U); + WR1_PROG(REG_1824H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func215.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func215.c new file mode 100644 index 0000000000..985ba1c19e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func215.c @@ -0,0 +1,28 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func215 (void) +{ + WR1_PROG(REG_1408H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_1828H, 6, 0); + + WR1_PROG(REG_143CH, 0x00000400U); + WR1_PROG(REG_143CH, 0x00000600U); + WR1_PROG(REG_143CH, 0x00000500U); + WR1_PROG(REG_1824H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func216.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func216.c new file mode 100644 index 0000000000..7afdd70e9e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func216.c @@ -0,0 +1,26 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func216 (void) +{ + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_1828H, 6, 0); + WR1_PROG(REG_143CH, 0x00000400U); + WR1_PROG(REG_143CH, 0x00000600U); + WR1_PROG(REG_143CH, 0x00000500U); + WR1_PROG(REG_1824H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func220.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func220.c new file mode 100644 index 0000000000..dbba61f190 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func220.c @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func220 (const uint32_t ARG1[], uint32_t ARG2, uint32_t ARG3[]) +{ + uint32_t iLoop = 0U; + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + for (iLoop = 4; iLoop < ARG2; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[iLoop - 4]); + + r_rsip_func214(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func302.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func302.c new file mode 100644 index 0000000000..db09cabc07 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func302.c @@ -0,0 +1,143 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func302 (void) +{ + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1f480000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000e50U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0xebc3fc05U), + bswap_32big(0xefb97619U), + bswap_32big(0xda871071U), + bswap_32big(0x8eb49b2cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x0ab13913U), bswap_32big(0x05882ea2U), bswap_32big(0xab583e8dU), + bswap_32big(0x1d4aa3a6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x11110009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x4b8b270dU), bswap_32big(0xe9d63591U), bswap_32big(0x07745a36U), + bswap_32big(0x019222b7U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x1ec17fc5U), bswap_32big(0xb1ecda41U), bswap_32big(0xaa2a1fa2U), + bswap_32big(0x18fa8b15U)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xc74ebd23U), bswap_32big(0xfb81e80cU), bswap_32big(0x562336d5U), + bswap_32big(0x9af6e6e8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x11110009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x8028c0c0U), bswap_32big(0xa5e74618U), bswap_32big(0xd75bec94U), + bswap_32big(0x142e61dbU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000dee0U); + + r_rsip_func101(bswap_32big(0xe3a4de3dU), bswap_32big(0x43aa5b5aU), bswap_32big(0x99f59db7U), + bswap_32big(0x90eae4a5U)); + } + } + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func303.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func303.c new file mode 100644 index 0000000000..e1f4e60303 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func303.c @@ -0,0 +1,143 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func303 (void) +{ + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1f480000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000e50U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x06368669U), + bswap_32big(0xe7ed91a1U), + bswap_32big(0x590b36c5U), + bswap_32big(0xa0c5c203U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x9da54cb3U), bswap_32big(0xdeedb109U), bswap_32big(0x22753694U), + bswap_32big(0x6b6ad934U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x04a37645U), bswap_32big(0x7d2edf7eU), bswap_32big(0x4487b211U), + bswap_32big(0x7b39e3a1U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x11110009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x99405635U), bswap_32big(0x768baf33U), bswap_32big(0xa4446829U), + bswap_32big(0x6cbd7a02U)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xafd07230U), bswap_32big(0x73b5db2aU), bswap_32big(0xe2d32420U), + bswap_32big(0x3a76baf9U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000dee0U); + + r_rsip_func101(bswap_32big(0xd6eae33cU), bswap_32big(0x4a5c8723U), bswap_32big(0x951ebb62U), + bswap_32big(0x5b62ac2cU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x11110009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x828ea0e5U), bswap_32big(0xa318b3ddU), bswap_32big(0xd7565856U), + bswap_32big(0x34b30d6dU)); + } + } + + WR1_PROG(REG_1404H, 0x17a80000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func304.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func304.c new file mode 100644 index 0000000000..877de7ff42 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func304.c @@ -0,0 +1,143 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func304 (void) +{ + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1ec80000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000e50U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x0482f1deU), + bswap_32big(0x0425cc0bU), + bswap_32big(0x93b904a2U), + bswap_32big(0xcfaa5e61U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x55f43070U), bswap_32big(0xec726d02U), bswap_32big(0xafb82f2dU), + bswap_32big(0x8f73c757U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x21210009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xae16cbb2U), bswap_32big(0xad07c43bU), bswap_32big(0x088441dcU), + bswap_32big(0xdbe4ed5eU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x31c18744U), bswap_32big(0x68a5083dU), bswap_32big(0x8eb1d357U), + bswap_32big(0x51111556U)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd83e5f80U), bswap_32big(0xbb23c5a8U), bswap_32big(0x4d2c4620U), + bswap_32big(0x9b1d9097U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x21210009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x80987b8dU), bswap_32big(0x940c8e41U), bswap_32big(0xceb045d6U), + bswap_32big(0x853d9255U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000dee0U); + + r_rsip_func101(bswap_32big(0x14a4003eU), bswap_32big(0x5e5c72d8U), bswap_32big(0x99d46613U), + bswap_32big(0x3b5b4673U)); + } + } + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func305.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func305.c new file mode 100644 index 0000000000..0315affa39 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func305.c @@ -0,0 +1,143 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func305 (void) +{ + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1ec80000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000e50U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0xbe680dbdU), + bswap_32big(0xceabf173U), + bswap_32big(0x05e7bbdaU), + bswap_32big(0x6fef9e92U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x15949ac5U), bswap_32big(0x8f936c29U), bswap_32big(0x447b111eU), + bswap_32big(0x45265351U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xecadebbcU), bswap_32big(0x24d0f771U), bswap_32big(0xa27202bbU), + bswap_32big(0x92b49c90U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x21210009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x19969077U), bswap_32big(0xebe6d931U), bswap_32big(0xf1a6782aU), + bswap_32big(0x25ed47b8U)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x2fcb44c9U), bswap_32big(0xe7e96fe6U), bswap_32big(0xe8f6a90fU), + bswap_32big(0x3183efb5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000dee0U); + + r_rsip_func101(bswap_32big(0xff78d412U), bswap_32big(0xe685424aU), bswap_32big(0x4f3ce470U), + bswap_32big(0x7b6272f5U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x21210009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xb71b9f81U), bswap_32big(0x9296d29bU), bswap_32big(0xeeb6a69eU), + bswap_32big(0xb8309f65U)); + } + } + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func310.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func310.c new file mode 100644 index 0000000000..3c90650280 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func310.c @@ -0,0 +1,156 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func310 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1400H, 0x00c00089U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x19d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00085U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000948U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1bf00000U); + WR1_PROG(REG_1400H, 0x00c00089U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000400U); + WR1_PROG(REG_1600H, 0x00000bffU); + for (oLoop = 0; oLoop < 1024; oLoop++) + { + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x2eece453U), bswap_32big(0x6125f4d8U), bswap_32big(0xb74b814cU), + bswap_32big(0xa399c4f3U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000948U); + WR1_PROG(REG_1018H, 0x00000b68U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x11110009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000c78U); + WR1_PROG(REG_1018H, 0x00000a58U); + WR1_PROG(REG_1020H, 0x00000c78U); + WR1_PROG(REG_1004H, 0x11110009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x688c7b7aU), bswap_32big(0xf70cba72U), bswap_32big(0x6a0fc07bU), + bswap_32big(0x23469096U)); + } + else + { + r_rsip_func101(bswap_32big(0x8655e943U), bswap_32big(0x2c1ad69bU), bswap_32big(0x272a1d76U), + bswap_32big(0xabb40233U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1014H, 0x00000948U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x1111000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a58U); + WR1_PROG(REG_1018H, 0x00000a58U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x11110009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x00002c00U); + r_rsip_func101(bswap_32big(0x5c64a44bU), bswap_32big(0xa3ec9fb2U), bswap_32big(0x6ced5b8dU), + bswap_32big(0xf6e113e5U)); + } + + WR1_PROG(REG_1600H, 0x38000801U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1608H, 0x80a00000U); + WR1_PROG(REG_1404H, 0x1bf80000U); + WR1_PROG(REG_1400H, 0x03430081U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func311.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func311.c new file mode 100644 index 0000000000..d235fc9508 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func311.c @@ -0,0 +1,367 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func311 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1404H, 0x1b680000U); + WR1_PROG(REG_1400H, 0x00c00331U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000530U); + WR1_PROG(REG_1018H, 0x00000c78U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000c78U); + WR1_PROG(REG_1020H, 0x00000e98U); + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + while (1) + { + WR1_PROG(REG_1404H, 0x1ae00000U); + WR1_PROG(REG_1608H, 0x80010080U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0x6c3f5059U), bswap_32big(0xc0742058U), bswap_32big(0x72caad39U), + bswap_32big(0xcf4dc557U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000b68U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x11110009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000948U); + WR1_PROG(REG_1018H, 0x00000e98U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x21210009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xf065cebbU), bswap_32big(0xb4a2e3ceU), bswap_32big(0x22713327U), + bswap_32big(0x0a5a29a7U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000b68U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19d00000U); + WR1_PROG(REG_1608H, 0x800100a0U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000d88U); + WR1_PROG(REG_1018H, 0x00000b68U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19d00000U); + WR1_PROG(REG_1608H, 0x800100c0U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x38000cc6U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x9233eb27U), bswap_32big(0xb080aa8aU), bswap_32big(0x4f2e9fbeU), + bswap_32big(0x62b0be4fU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x38000ce7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0x41cb113bU), + bswap_32big(0xc311954fU), + bswap_32big(0x2411cb1aU), + bswap_32big(0xcce1c8a9U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000c78U); + WR1_PROG(REG_1018H, 0x00000948U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19500000U); + WR1_PROG(REG_1608H, 0x80010100U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00002d00U); + WR1_PROG(REG_1404H, 0x19d00000U); + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1400H, 0x00c00085U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000b68U); + WR1_PROG(REG_1018H, 0x00000a58U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19500000U); + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00101U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000948U); + WR1_PROG(REG_1018H, 0x00000a58U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x21210009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xd97d7079U), + bswap_32big(0xece70de5U), + bswap_32big(0x88c3762eU), + bswap_32big(0xe1ed94fdU)); + } + else + { + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x28f035e2U), + bswap_32big(0x2acfbfc5U), + bswap_32big(0x82581072U), + bswap_32big(0xc4691dd6U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000948U); + WR1_PROG(REG_1018H, 0x00000e98U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19500000U); + WR1_PROG(REG_1608H, 0x80010100U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0x61607ae2U), + bswap_32big(0xcac66caeU), + bswap_32big(0x15336fe6U), + bswap_32big(0x125a931bU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + r_rsip_func101(bswap_32big(0x612561b1U), + bswap_32big(0x69a6b19aU), + bswap_32big(0xb89806e3U), + bswap_32big(0xecaba86aU)); + break; + } + else + { + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1400H, 0x00c00109U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000b68U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a58U); + WR1_PROG(REG_1018H, 0x00000948U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x21210009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xcdeaef1eU), + bswap_32big(0xc960fb74U), + bswap_32big(0x69ae4e67U), + bswap_32big(0xfd8d1626U)); + } + } + else + { + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1608H, 0x80010120U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x38000d29U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x2b1a9745U), + bswap_32big(0xd5150c15U), + bswap_32big(0xcd8ab433U), + bswap_32big(0x432e8cd7U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + r_rsip_func101(bswap_32big(0x0684953fU), + bswap_32big(0x4ff4772aU), + bswap_32big(0xdb4046e8U), + bswap_32big(0xeed45ea7U)); + break; + } + else + { + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x19d00000U); + WR1_PROG(REG_1608H, 0x81010120U); + WR1_PROG(REG_1400H, 0x00c00085U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000b68U); + WR1_PROG(REG_1018H, 0x00000a58U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x21210009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xd03bebfaU), + bswap_32big(0x248a6525U), + bswap_32big(0x5de0f709U), + bswap_32big(0x6183dfe7U)); + } + } + } + } + else + { + WR1_PROG(REG_1014H, 0x00000b68U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x1111000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000948U); + WR1_PROG(REG_1018H, 0x00000e98U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x2121000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x2d4d6fecU), + bswap_32big(0x5332f872U), + bswap_32big(0xeb3db6dcU), + bswap_32big(0x2099468eU)); + } + } + } + + WR1_PROG(REG_1014H, 0x00000948U); + WR1_PROG(REG_1018H, 0x00000c78U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000b68U); + WR1_PROG(REG_1018H, 0x00000c78U); + WR1_PROG(REG_1020H, 0x00000738U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func312.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func312.c new file mode 100644 index 0000000000..b67eb7d908 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func312.c @@ -0,0 +1,404 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func312 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1600H, 0x0000379dU); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1404H, 0x18380000U); + WR1_PROG(REG_1400H, 0x00c00661U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80a00004U); + WR1_PROG(REG_1400H, 0x03400081U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + for (oLoop = 0; oLoop < 3; oLoop++) + { + WR1_PROG(REG_1404H, 0x18380000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func100(bswap_32big(0x1a696e5fU), bswap_32big(0xc828001cU), bswap_32big(0xec6dd6caU), + bswap_32big(0xe8f80945U)); + WR1_PROG(REG_1600H, 0x00007c02U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + if (0x00000000U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x000008c0U); + WR1_PROG(REG_1020H, 0x00000e98U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x540e146cU), bswap_32big(0xfad7dd2dU), bswap_32big(0xa0cae7b4U), + bswap_32big(0x4898d8d3U)); + } + else if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_1014H, 0x000001a0U); + WR1_PROG(REG_1018H, 0x000008c0U); + WR1_PROG(REG_1020H, 0x00000e98U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x078b9536U), bswap_32big(0xea684953U), bswap_32big(0x794ecce8U), + bswap_32big(0xa6855652U)); + } + else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_1014H, 0x00000120U); + WR1_PROG(REG_1018H, 0x000008c0U); + WR1_PROG(REG_1020H, 0x00000e98U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xbc588686U), bswap_32big(0xf6ac8a2aU), bswap_32big(0xc88d5d35U), + bswap_32big(0x56e4a25aU)); + } + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x000008c0U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000e98U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_101CH, 0x00000948U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x1010000dU); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1d080000U); + WR1_PROG(REG_1400H, 0x00c00081U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x000008c8U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000ae8U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x18380000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1d080000U); + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1608H, 0x81a00004U); + WR1_PROG(REG_1400H, 0x00c90081U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000948U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000d88U); + WR1_PROG(REG_1018H, 0x000008c0U); + WR1_PROG(REG_1020H, 0x00000e10U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x000008c0U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000e10U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_101CH, 0x00000948U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x1010000dU); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19480000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x000007b8U); + WR1_PROG(REG_1018H, 0x000009d0U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000e98U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_101CH, 0x00000a58U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x1010000dU); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1c780000U); + WR1_PROG(REG_1400H, 0x00c00111U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000ae8U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a58U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x000009d8U); + WR1_PROG(REG_1018H, 0x00000d00U); + WR1_PROG(REG_1020H, 0x00000bf8U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19480000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x000005b0U); + WR1_PROG(REG_1018H, 0x000009d0U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000e10U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_101CH, 0x00000a58U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x1010000dU); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x000008c8U); + WR1_PROG(REG_1018H, 0x000009d0U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x18380000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000d88U); + WR1_PROG(REG_1018H, 0x00000948U); + WR1_PROG(REG_1020H, 0x00000948U); + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x000008c8U); + WR1_PROG(REG_1018H, 0x000009d0U); + WR1_PROG(REG_1020H, 0x000009d8U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1a580000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000738U); + WR1_PROG(REG_1018H, 0x00000ae0U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000e98U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_101CH, 0x00000b68U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x1010000dU); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1c780000U); + WR1_PROG(REG_1400H, 0x00c00111U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000bf8U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000b68U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000ae8U); + WR1_PROG(REG_1018H, 0x00000d00U); + WR1_PROG(REG_1020H, 0x000008c8U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1a580000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000530U); + WR1_PROG(REG_1018H, 0x00000ae0U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000e10U); + WR1_PROG(REG_1018H, 0x00000d88U); + WR1_PROG(REG_101CH, 0x00000b68U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x1010000dU); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x000009d8U); + WR1_PROG(REG_1018H, 0x00000ae0U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19480000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000d88U); + WR1_PROG(REG_1018H, 0x00000a58U); + WR1_PROG(REG_1020H, 0x00000a58U); + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x000009d8U); + WR1_PROG(REG_1018H, 0x00000ae0U); + WR1_PROG(REG_1020H, 0x00000ae8U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1c780000U); + WR1_PROG(REG_1400H, 0x00c00111U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x000008c8U); + WR1_PROG(REG_1018H, 0x00000d00U); + WR1_PROG(REG_1020H, 0x00000d88U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000ae8U); + WR1_PROG(REG_1018H, 0x00000d00U); + WR1_PROG(REG_1020H, 0x00000c78U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1b680000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000d88U); + WR1_PROG(REG_1018H, 0x00000c78U); + WR1_PROG(REG_1020H, 0x00000e98U); + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x1d080000U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81a00004U); + WR1_PROG(REG_1400H, 0x00c90081U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000d88U); + WR1_PROG(REG_1018H, 0x00000e98U); + WR1_PROG(REG_1020H, 0x00000b68U); + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80a00004U); + WR1_PROG(REG_1404H, 0x1a680000U); + WR1_PROG(REG_1400H, 0x03430081U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00002c40U); + r_rsip_func101(bswap_32big(0xa3821c57U), bswap_32big(0x1f2d8810U), bswap_32big(0x2b32ccfbU), + bswap_32big(0xe9c5b595U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000843U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1014H, 0x00000a58U); + WR1_PROG(REG_1018H, 0x00000d00U); + WR1_PROG(REG_1020H, 0x000008c8U); + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f312U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xa02039fdU), + bswap_32big(0x7a3bd2e7U), + bswap_32big(0xa4e1b28bU), + bswap_32big(0x4cc8e0dbU)); + r_rsip_func311(); + WR1_PROG(REG_1600H, 0x000037bcU); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func313.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func313.c new file mode 100644 index 0000000000..038163af9a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func313.c @@ -0,0 +1,888 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func313 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1600H, 0x0000373dU); + WR1_PROG(REG_1600H, 0x00000bdeU); + while (1) + { + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x601736b6U), bswap_32big(0x19fb0987U), bswap_32big(0x68ead324U), + bswap_32big(0x0bafc5cfU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x1818000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x1818000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x00002fc0U); + r_rsip_func101(bswap_32big(0x6b757ba9U), bswap_32big(0x333b00b6U), bswap_32big(0x0926d849U), + bswap_32big(0xdea75fecU)); + } + else + { + r_rsip_func101(bswap_32big(0xc2fd8664U), bswap_32big(0x1607d0a7U), bswap_32big(0xce650d98U), + bswap_32big(0x44c5103cU)); + break; + } + } + + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1400H, 0x00c000d1U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xa277852fU)); + OFS_ADR = 56; + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003131U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x9f7b69d4U), + bswap_32big(0xda3ba583U), + bswap_32big(0xfb075510U), + bswap_32big(0xaa01f531U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x4db9e5b0U)); + OFS_ADR = 112; + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003132U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x6a87e9d0U), + bswap_32big(0x17c15a85U), + bswap_32big(0x751d056dU), + bswap_32big(0x2d96f3fcU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xab580788U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003133U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xf30204aeU), + bswap_32big(0xe707b24cU), + bswap_32big(0x60e62817U), + bswap_32big(0xfc5cdffaU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xc447d111U)); + OFS_ADR = 168; + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003134U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xe847ce29U), + bswap_32big(0xc7ff1346U), + bswap_32big(0xb3798ac0U), + bswap_32big(0x66179da1U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf6428095U)); + OFS_ADR = 224; + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003135U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x60439d51U), + bswap_32big(0x6c02fbeaU), + bswap_32big(0xac8cd97dU), + bswap_32big(0xe3062ea0U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1404H, 0x15700000U); + WR1_PROG(REG_1600H, 0x00000b7bU); + WR1_PROG(REG_1608H, 0x80b0001bU); + WR1_PROG(REG_1400H, 0x034300c1U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + while (1) + { + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00210000U); + r_rsip_func100(bswap_32big(0xa4928d99U), bswap_32big(0x8ccb6d81U), bswap_32big(0xb273c1cdU), + bswap_32big(0xdb626188U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + r_rsip_func101(bswap_32big(0xe052148bU), bswap_32big(0xf0ecd87bU), bswap_32big(0x5f593ca7U), + bswap_32big(0xac34cd3bU)); + break; + } + else + { + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xab580788U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x13580000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003131U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x36c1d3aeU), bswap_32big(0xb1fd7c31U), bswap_32big(0x866d0b43U), + bswap_32big(0x8ae28132U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xa277852fU)); + OFS_ADR = 56; + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003132U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x93695a66U), bswap_32big(0x1b406f63U), bswap_32big(0x49196257U), + bswap_32big(0x671b5c6bU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003131U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x9271668aU), bswap_32big(0xef4f78ddU), bswap_32big(0xcada7454U), + bswap_32big(0xd8a8648fU)); + r_rsip_func314(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xab580788U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x13580000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003136U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x11c23b1fU), bswap_32big(0x462a935fU), bswap_32big(0xf30a0e6fU), + bswap_32big(0x7df428dfU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xa277852fU)); + OFS_ADR = 56; + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003137U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x9cefca6dU), bswap_32big(0x956fd979U), bswap_32big(0xf07c01d0U), + bswap_32big(0xa1542807U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x4db9e5b0U)); + OFS_ADR = 112; + WR1_PROG(REG_1404H, 0x13580000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003133U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x3b4efc9fU), bswap_32big(0x66f98bd7U), bswap_32big(0x2ce42495U), + bswap_32big(0xc0d2a9f1U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xc447d111U)); + OFS_ADR = 168; + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003134U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xe7013b3eU), bswap_32big(0xa2c5ad8aU), bswap_32big(0x6d827c74U), + bswap_32big(0xf0770fa0U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x1f180000U); + WR1_PROG(REG_1400H, 0x00c000c1U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003132U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x186cc5b7U), bswap_32big(0x7420d5a4U), bswap_32big(0xcfc756e2U), + bswap_32big(0xf9183b48U)); + r_rsip_func314(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x4db9e5b0U)); + OFS_ADR = 112; + WR1_PROG(REG_1404H, 0x13580000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003138U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x29ce0bd2U), bswap_32big(0x4cdbcf3cU), bswap_32big(0x77ab84c0U), + bswap_32big(0x878595a7U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xc447d111U)); + OFS_ADR = 168; + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003139U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xf75fd450U), bswap_32big(0x6079636fU), bswap_32big(0x8abd4af0U), + bswap_32big(0x8973d947U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1404H, 0x1f180000U); + WR1_PROG(REG_1400H, 0x00c000c1U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0xe300f11fU), bswap_32big(0x8b2e4275U), bswap_32big(0x0323bde9U), + bswap_32big(0xb705bcd9U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xab580788U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003135U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x72449468U), + bswap_32big(0x97696a0aU), + bswap_32big(0x0e1e6703U), + bswap_32big(0x5f6d0728U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x4db9e5b0U)); + OFS_ADR = 112; + WR1_PROG(REG_1404H, 0x1f080000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003136U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x41182fa3U), + bswap_32big(0xc99bbdb0U), + bswap_32big(0x334b6958U), + bswap_32big(0x644f9a03U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003131U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xbe82515aU), + bswap_32big(0x55489f24U), + bswap_32big(0x528e969bU), + bswap_32big(0x03f8f718U)); + r_rsip_func318(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xab580788U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313aU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x2b135aa0U), + bswap_32big(0x2e45d35eU), + bswap_32big(0x3c4e2ff2U), + bswap_32big(0x559e8e9aU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xa277852fU)); + OFS_ADR = 56; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003137U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xfac50d60U), + bswap_32big(0x0576dd30U), + bswap_32big(0xc16c18a9U), + bswap_32big(0xd6a8f7c3U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xc447d111U)); + OFS_ADR = 168; + WR1_PROG(REG_1404H, 0x1f080000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003138U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xebaec341U), + bswap_32big(0xb6b145e3U), + bswap_32big(0x1a6814e4U), + bswap_32big(0x8f20f3aaU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003132U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xac0accfbU), + bswap_32big(0xb717f228U), + bswap_32big(0xeaee71b3U), + bswap_32big(0x0f24f3cfU)); + r_rsip_func318(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xa277852fU)); + OFS_ADR = 56; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313bU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xdad3dae3U), + bswap_32big(0x0c8e7e1bU), + bswap_32big(0x6e1a0d23U), + bswap_32big(0xbf77ba47U)); + r_rsip_func016(OFS_ADR); + r_rsip_func101(bswap_32big(0x7df2e2d1U), + bswap_32big(0x72ae1bb1U), + bswap_32big(0xd8ca81e6U), + bswap_32big(0x189cf641U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x4db9e5b0U)); + OFS_ADR = 112; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313aU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xa0c300c3U), + bswap_32big(0x289d5f26U), + bswap_32big(0x83278ddcU), + bswap_32big(0xde65c683U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xab580788U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x1f080000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313bU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xb1a5c137U), + bswap_32big(0x4d82510aU), + bswap_32big(0x2afbd7f9U), + bswap_32big(0x7b036221U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003133U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xcf433d64U), + bswap_32big(0xdd50045cU), + bswap_32big(0x5e6b31f3U), + bswap_32big(0x44001b9fU)); + r_rsip_func318(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x4db9e5b0U)); + OFS_ADR = 112; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313cU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xb9d83081U), + bswap_32big(0xcc17117aU), + bswap_32big(0x179ce4d6U), + bswap_32big(0xb0984394U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xc447d111U)); + OFS_ADR = 168; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313cU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xf4a60cb1U), + bswap_32big(0x1071ad70U), + bswap_32big(0x494fb89cU), + bswap_32big(0xd25acd29U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xa277852fU)); + OFS_ADR = 56; + WR1_PROG(REG_1404H, 0x1f080000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313dU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xb6d74ebfU), + bswap_32big(0x70ee8bd8U), + bswap_32big(0x824af075U), + bswap_32big(0xc190dff2U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003134U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xb89562cfU), + bswap_32big(0x1d4c335aU), + bswap_32big(0x4acb6936U), + bswap_32big(0x1bd9ee01U)); + r_rsip_func318(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xc447d111U)); + OFS_ADR = 168; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313dU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xea0750fcU), + bswap_32big(0xec110227U), + bswap_32big(0xce067e1dU), + bswap_32big(0x2bfb6617U)); + r_rsip_func016(OFS_ADR); + r_rsip_func101(bswap_32big(0x1f0d3f81U), + bswap_32big(0x126b48aaU), + bswap_32big(0x87efc409U), + bswap_32big(0x229c44bfU)); + } + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf6428095U)); + OFS_ADR = 224; + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313eU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xd6b7e1abU), + bswap_32big(0x3019af4aU), + bswap_32big(0xc68d9fd0U), + bswap_32big(0x053798a8U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + while (1) + { + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0x699e3e0dU), bswap_32big(0x3bf794f4U), bswap_32big(0xad74dc44U), + bswap_32big(0x04223bf8U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x18180008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x18180008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x000033c0U); + r_rsip_func101(bswap_32big(0x2206fab3U), bswap_32big(0x44f06b9bU), bswap_32big(0xa8e9eb51U), + bswap_32big(0x06e705cdU)); + } + else + { + r_rsip_func101(bswap_32big(0x71e9a522U), bswap_32big(0x75f83d15U), bswap_32big(0x805eac24U), + bswap_32big(0x73853ef7U)); + break; + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xc447d111U)); + OFS_ADR = 168; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000034U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000313fU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x2f926c08U), + bswap_32big(0xa43d848aU), + bswap_32big(0x7b7f81aaU), + bswap_32big(0xd98a8350U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + while (1) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00210000U); + r_rsip_func100(bswap_32big(0xa621e6aaU), bswap_32big(0x3fc6b52eU), bswap_32big(0x18bfb9a5U), + bswap_32big(0x76e5cecaU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x4c0ddd5aU), bswap_32big(0xbba73c23U), bswap_32big(0x72898d56U), + bswap_32big(0xc55e31d6U)); + } + else + { + r_rsip_func101(bswap_32big(0xeca9afafU), bswap_32big(0xeda04ec6U), bswap_32big(0xd7d96c40U), + bswap_32big(0x4b48a5b3U)); + break; + } + } + + WR1_PROG(REG_1600H, 0x3800db60U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0xa60bfb3aU), + bswap_32big(0x8d4bd31cU), + bswap_32big(0xdf36912eU), + bswap_32big(0x07c6f6d5U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x997b6084U), bswap_32big(0x4a9f74b8U), bswap_32big(0x68ef78b0U), + bswap_32big(0x7407aeafU)); + } + else + { + r_rsip_func101(bswap_32big(0x9db08274U), bswap_32big(0x56fcc2dfU), bswap_32big(0xa05cdb0cU), + bswap_32big(0x60fd4729U)); + } + + WR1_PROG(REG_1600H, 0x000037b9U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func314.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func314.c new file mode 100644 index 0000000000..24f10667ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func314.c @@ -0,0 +1,299 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func314 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1600H, 0x0000379dU); + while (1) + { + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x5dc4167fU), bswap_32big(0xdfa0e3b1U), bswap_32big(0x3d212490U), + bswap_32big(0xb10bdaaeU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x1818000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x14200000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1a380000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x500a3648U), bswap_32big(0x385aed6bU), bswap_32big(0x17e3088cU), + bswap_32big(0xc61537c4U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1404H, 0x13580000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x13580000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000428U); + WR1_PROG(REG_1004H, 0x1919000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000a40U); + WR1_PROG(REG_1004H, 0x1919000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x13580000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1608H, 0x81010300U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func101(bswap_32big(0xa0c648b5U), + bswap_32big(0x1f9a33f2U), + bswap_32big(0x13985f0cU), + bswap_32big(0x50f12c36U)); + } + else + { + WR1_PROG(REG_1404H, 0x1f080000U); + WR1_PROG(REG_1600H, 0x00000b7bU); + WR1_PROG(REG_1608H, 0x81b0001bU); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c900c1U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1400H, 0x00c000d1U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1a1a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f314U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x06210c5dU), + bswap_32big(0x8d0c5b27U), + bswap_32big(0x4c1a9e53U), + bswap_32big(0x604435feU)); + r_rsip_func317(); + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000428U); + WR1_PROG(REG_1004H, 0x1919000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x13580000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1f080000U); + WR1_PROG(REG_1400H, 0x00c000d1U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf6428095U)); + OFS_ADR = 224; + WR1_PROG(REG_1404H, 0x1f180000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f314U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xf2711aa0U), + bswap_32big(0x5dffa914U), + bswap_32big(0x619fc2a3U), + bswap_32big(0x17082dcbU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1400H, 0x00c000d1U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1a1a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f314U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x578e3a3bU), + bswap_32big(0x1149611eU), + bswap_32big(0x817ba55fU), + bswap_32big(0x43d449d0U)); + r_rsip_func318(); + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + WR1_PROG(REG_1004H, 0x1919000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x19700000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func101(bswap_32big(0x50ba135fU), + bswap_32big(0x781953f9U), + bswap_32big(0xf05b8d42U), + bswap_32big(0xbc2c9d9dU)); + } + } + else + { + r_rsip_func101(bswap_32big(0xb4a0384fU), bswap_32big(0xcd3cd70fU), bswap_32big(0xad73a83cU), + bswap_32big(0xd9e13823U)); + break; + } + } + + WR1_PROG(REG_1600H, 0x000037bcU); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func315.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func315.c new file mode 100644 index 0000000000..914b1ca5b9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func315.c @@ -0,0 +1,888 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func315 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1600H, 0x0000373dU); + WR1_PROG(REG_1600H, 0x00000bdeU); + while (1) + { + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x4975fa91U), bswap_32big(0x1532f1f9U), bswap_32big(0xec5cacc2U), + bswap_32big(0xfd81d448U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x3030000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x3030000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x00002fc0U); + r_rsip_func101(bswap_32big(0xd97da2beU), bswap_32big(0xa977bedcU), bswap_32big(0x4ebc2ac9U), + bswap_32big(0xc9d90b10U)); + } + else + { + r_rsip_func101(bswap_32big(0x6206722fU), bswap_32big(0xf409b6c4U), bswap_32big(0x30ff1809U), + bswap_32big(0xe78d678bU)); + break; + } + } + + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1400H, 0x00c00191U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x2517e7b7U)); + OFS_ADR = 104; + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003151U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x93fec043U), + bswap_32big(0x5adb0d4aU), + bswap_32big(0xb4f6ae87U), + bswap_32big(0x5ae18a3dU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x3cc10901U)); + OFS_ADR = 208; + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003152U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x7226f94cU), + bswap_32big(0x9b145f5cU), + bswap_32big(0x10d888d4U), + bswap_32big(0x52f0316bU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xabf7a97eU)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003153U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x76f63cefU), + bswap_32big(0x0855a73eU), + bswap_32big(0xd1b447ddU), + bswap_32big(0xa233885dU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0b097e1fU)); + OFS_ADR = 312; + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003154U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xb94af777U), + bswap_32big(0x2504aebcU), + bswap_32big(0x5ea20de5U), + bswap_32big(0xc952f41dU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xe4f152fdU)); + OFS_ADR = 416; + WR1_PROG(REG_1404H, 0x10a00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003155U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x39d49654U), + bswap_32big(0xb6cc376fU), + bswap_32big(0xf7494985U), + bswap_32big(0xc4d5ed5dU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1404H, 0x14b00000U); + WR1_PROG(REG_1600H, 0x00000b7bU); + WR1_PROG(REG_1608H, 0x80e0001bU); + WR1_PROG(REG_1400H, 0x03430181U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + while (1) + { + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00210000U); + r_rsip_func100(bswap_32big(0x4dd93322U), bswap_32big(0xe5482d5fU), bswap_32big(0xe2b64e20U), + bswap_32big(0x0c82572dU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + r_rsip_func101(bswap_32big(0x15594be0U), bswap_32big(0x7d6eb3ccU), bswap_32big(0x7e43c1d1U), + bswap_32big(0xdf472f20U)); + break; + } + else + { + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xabf7a97eU)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x12980000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003151U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x9fb9f627U), bswap_32big(0xcaa1618cU), bswap_32big(0x90ab3e22U), + bswap_32big(0x3c11754aU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x2517e7b7U)); + OFS_ADR = 104; + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003152U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xb8f64342U), bswap_32big(0xb76f531fU), bswap_32big(0x43170ecbU), + bswap_32big(0xb50be53eU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003151U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x8259f7eaU), bswap_32big(0x4ab12ff4U), bswap_32big(0xcc6ad8cdU), + bswap_32big(0x65133952U)); + r_rsip_func316(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xabf7a97eU)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x12980000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003156U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x66f2156cU), bswap_32big(0xd1dc279fU), bswap_32big(0xc0faa6b7U), + bswap_32big(0xedbbaec1U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x2517e7b7U)); + OFS_ADR = 104; + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003157U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xc4626285U), bswap_32big(0x5b72c90bU), bswap_32big(0x3d917904U), + bswap_32big(0x5cabc377U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x3cc10901U)); + OFS_ADR = 208; + WR1_PROG(REG_1404H, 0x12980000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003153U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x33383fa2U), bswap_32big(0x991d6706U), bswap_32big(0x27c05051U), + bswap_32big(0x28d2d4d4U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0b097e1fU)); + OFS_ADR = 312; + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003154U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x4bc0a8d6U), bswap_32big(0x435ddfdcU), bswap_32big(0x0b105d9aU), + bswap_32big(0x1ad9f12dU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x1e580000U); + WR1_PROG(REG_1400H, 0x00c00181U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x30300009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x30300009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x30300009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003152U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x5c85df00U), bswap_32big(0x60dfd3d0U), bswap_32big(0x7fb65d8cU), + bswap_32big(0x390b3fc8U)); + r_rsip_func316(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x3cc10901U)); + OFS_ADR = 208; + WR1_PROG(REG_1404H, 0x12980000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003158U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x75f1c2baU), bswap_32big(0x985d1b64U), bswap_32big(0x0fee9c8bU), + bswap_32big(0xacb45ce0U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0b097e1fU)); + OFS_ADR = 312; + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003159U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x39e85691U), bswap_32big(0xc6fbfb49U), bswap_32big(0x31ddf6efU), + bswap_32big(0xe09b5090U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1404H, 0x1e580000U); + WR1_PROG(REG_1400H, 0x00c00181U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x30300009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x30300009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x30300009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0xa41658b7U), bswap_32big(0xafd3eb25U), bswap_32big(0x62211efaU), + bswap_32big(0x87ffc091U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x30300009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xabf7a97eU)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003155U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x09c1bfd2U), + bswap_32big(0x6ade80c9U), + bswap_32big(0x01779f89U), + bswap_32big(0x290dd163U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x3cc10901U)); + OFS_ADR = 208; + WR1_PROG(REG_1404H, 0x1e480000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003156U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xe0f52561U), + bswap_32big(0x579cf0b3U), + bswap_32big(0xf1a29ad4U), + bswap_32big(0x82616033U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003151U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x675f4223U), + bswap_32big(0x90c24f48U), + bswap_32big(0xa74d8581U), + bswap_32big(0x0599ecd5U)); + r_rsip_func320(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xabf7a97eU)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315aU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xbe0a9565U), + bswap_32big(0x673a64b5U), + bswap_32big(0x289ee459U), + bswap_32big(0x648c3a3dU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x2517e7b7U)); + OFS_ADR = 104; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003157U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x960ea839U), + bswap_32big(0x5988481dU), + bswap_32big(0x1e8730d5U), + bswap_32big(0xaa684d13U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0b097e1fU)); + OFS_ADR = 312; + WR1_PROG(REG_1404H, 0x1e480000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003158U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x5f59d61eU), + bswap_32big(0xaa12525cU), + bswap_32big(0xcddb3b02U), + bswap_32big(0xb41d0da0U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003152U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x9f74a68cU), + bswap_32big(0x45d0a134U), + bswap_32big(0xc4fd10feU), + bswap_32big(0x8b1faa17U)); + r_rsip_func320(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x2517e7b7U)); + OFS_ADR = 104; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315bU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xebe34980U), + bswap_32big(0xbdb23805U), + bswap_32big(0xd9ce5f71U), + bswap_32big(0xb7fe7da3U)); + r_rsip_func016(OFS_ADR); + r_rsip_func101(bswap_32big(0xec5b3909U), + bswap_32big(0xdba91c42U), + bswap_32big(0x89fd4a71U), + bswap_32big(0x7f13ba31U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x3cc10901U)); + OFS_ADR = 208; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315aU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x326a6804U), + bswap_32big(0x38aa7513U), + bswap_32big(0xf967864fU), + bswap_32big(0x5d22c1a3U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xabf7a97eU)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x1e480000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315bU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x31fae08dU), + bswap_32big(0x5136bb91U), + bswap_32big(0x5018b59bU), + bswap_32big(0xd650926bU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003153U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x192f36d5U), + bswap_32big(0x8690953eU), + bswap_32big(0x247a9bb1U), + bswap_32big(0x4a95df0dU)); + r_rsip_func320(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x3cc10901U)); + OFS_ADR = 208; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315cU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x700b56aeU), + bswap_32big(0xe3fdf1beU), + bswap_32big(0xc3968460U), + bswap_32big(0xa74b7513U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0b097e1fU)); + OFS_ADR = 312; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315cU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xc37fcc6aU), + bswap_32big(0xcc8514b8U), + bswap_32big(0x648cbc46U), + bswap_32big(0xec3a3488U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x2517e7b7U)); + OFS_ADR = 104; + WR1_PROG(REG_1404H, 0x1e480000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315dU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x26a16ea6U), + bswap_32big(0x43f32d5bU), + bswap_32big(0xacfcde43U), + bswap_32big(0xc234ce39U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003154U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x224d18daU), + bswap_32big(0xf22ba6a6U), + bswap_32big(0x117f799cU), + bswap_32big(0x54cd0da0U)); + r_rsip_func320(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0b097e1fU)); + OFS_ADR = 312; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315dU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xa5b026bfU), + bswap_32big(0x14eb53b0U), + bswap_32big(0xc62c7015U), + bswap_32big(0xf9e4c051U)); + r_rsip_func016(OFS_ADR); + r_rsip_func101(bswap_32big(0xcb6e050cU), + bswap_32big(0x07651356U), + bswap_32big(0xeb1cf7d4U), + bswap_32big(0xc17a4b41U)); + } + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xe4f152fdU)); + OFS_ADR = 416; + WR1_PROG(REG_1404H, 0x10a00000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315eU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x2c98b618U), + bswap_32big(0xe752d6abU), + bswap_32big(0xa64e6560U), + bswap_32big(0xb763b5caU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + while (1) + { + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0xf8e45450U), bswap_32big(0xa979e463U), bswap_32big(0xd2e64d4bU), + bswap_32big(0xc4c3be64U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000630U); + WR1_PROG(REG_1004H, 0x30300008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x30300008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x000033c0U); + r_rsip_func101(bswap_32big(0x76f2d52fU), bswap_32big(0x790f8ec8U), bswap_32big(0x6b38ba89U), + bswap_32big(0x1929685bU)); + } + else + { + r_rsip_func101(bswap_32big(0xd21a70c8U), bswap_32big(0xd7e466e1U), bswap_32big(0x850cd447U), + bswap_32big(0xa3913442U)); + break; + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0b097e1fU)); + OFS_ADR = 312; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000064U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000315fU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x94ddae8cU), + bswap_32big(0x15253fc2U), + bswap_32big(0xdfe1bcc6U), + bswap_32big(0xa1c3de06U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + while (1) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00210000U); + r_rsip_func100(bswap_32big(0x517e289dU), bswap_32big(0x0e29cb98U), bswap_32big(0x45c614ddU), + bswap_32big(0x6af9f19aU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x3791207eU), bswap_32big(0xcacea114U), bswap_32big(0xb686dbc6U), + bswap_32big(0xdb2c506aU)); + } + else + { + r_rsip_func101(bswap_32big(0x6d8e3bd2U), bswap_32big(0xb95d84e3U), bswap_32big(0x8e7bd357U), + bswap_32big(0x4d8511feU)); + break; + } + } + + WR1_PROG(REG_1600H, 0x3800db60U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0xc6360c41U), + bswap_32big(0x003108c9U), + bswap_32big(0xea2d9fc8U), + bswap_32big(0x99dde586U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xd18f913cU), bswap_32big(0x94e33e81U), bswap_32big(0xe2efb21fU), + bswap_32big(0x9d415515U)); + } + else + { + r_rsip_func101(bswap_32big(0x6c4f55f2U), bswap_32big(0x2e9cceb3U), bswap_32big(0x052b4f15U), + bswap_32big(0x364ab236U)); + } + + WR1_PROG(REG_1600H, 0x000037b9U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func316.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func316.c new file mode 100644 index 0000000000..6bd1ad04e4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func316.c @@ -0,0 +1,299 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func316 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1600H, 0x0000379dU); + while (1) + { + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x1cf2d2c5U), bswap_32big(0x1e04183bU), bswap_32big(0xb85d79d0U), + bswap_32big(0xa0744604U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000220U); + WR1_PROG(REG_1004H, 0x3030000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x14200000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1a380000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0xe5c3df4dU), bswap_32big(0x4ab9b448U), bswap_32big(0x00b32810U), + bswap_32big(0xe4571e3bU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1404H, 0x12980000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x12980000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000428U); + WR1_PROG(REG_1004H, 0x3131000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000a40U); + WR1_PROG(REG_1004H, 0x3131000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x12980000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1608H, 0x81010300U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func101(bswap_32big(0x809dbebcU), + bswap_32big(0x014593feU), + bswap_32big(0x455020beU), + bswap_32big(0x88ef5ffaU)); + } + else + { + WR1_PROG(REG_1404H, 0x1e480000U); + WR1_PROG(REG_1600H, 0x00000b7bU); + WR1_PROG(REG_1608H, 0x81e0001bU); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90181U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1400H, 0x00c00191U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x32320009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f316U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x6e536df5U), + bswap_32big(0x7bee537eU), + bswap_32big(0x1f0db5deU), + bswap_32big(0x16040ccaU)); + r_rsip_func319(); + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000428U); + WR1_PROG(REG_1004H, 0x3131000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x12980000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1e480000U); + WR1_PROG(REG_1400H, 0x00c00191U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xe4f152fdU)); + OFS_ADR = 416; + WR1_PROG(REG_1404H, 0x1e580000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f316U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x8ae55f12U), + bswap_32big(0xad1a89feU), + bswap_32big(0xa24cb84eU), + bswap_32big(0x53ee4b8dU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1400H, 0x00c00191U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x32320009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f316U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x4c9ccbf9U), + bswap_32big(0x42c0bc08U), + bswap_32big(0xb4a217c6U), + bswap_32big(0x7f31f200U)); + r_rsip_func320(); + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + WR1_PROG(REG_1004H, 0x3131000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x18b00000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func101(bswap_32big(0xf2d18d6eU), + bswap_32big(0x05c4f242U), + bswap_32big(0x22e28684U), + bswap_32big(0x46678bbfU)); + } + } + else + { + r_rsip_func101(bswap_32big(0x9ffe1754U), bswap_32big(0xaf65feabU), bswap_32big(0x9b77854fU), + bswap_32big(0x38a1efa7U)); + break; + } + } + + WR1_PROG(REG_1600H, 0x000037bcU); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func317.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func317.c new file mode 100644 index 0000000000..0427029c19 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func317.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func317 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1f080000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000e40U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0xf8e56780U), + bswap_32big(0x3a4fdfc3U), + bswap_32big(0x6e457e11U), + bswap_32big(0x9fa6f941U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0xa4fe85bfU), bswap_32big(0xff262367U), bswap_32big(0xd5bb1200U), + bswap_32big(0xfd0dc3e3U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x19190009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x08b452a4U), bswap_32big(0xd8df04f6U), bswap_32big(0xc00fdc23U), + bswap_32big(0x0abc3e5fU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xf2f2891eU), bswap_32big(0xd3f679d5U), bswap_32big(0xd16af82eU), + bswap_32big(0xff68bb0cU)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0xf7e82dc0U), bswap_32big(0x531eddacU), bswap_32big(0x9c9094cfU), + bswap_32big(0xa5e8a2d3U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x19190009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x21b9808cU), bswap_32big(0x0f0f51f2U), bswap_32big(0x15e955c8U), + bswap_32big(0xd6165721U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x0000dee0U); + r_rsip_func101(bswap_32big(0xebe6b879U), bswap_32big(0xd20a4ba3U), bswap_32big(0x309915fbU), + bswap_32big(0x58c816eeU)); + } + } + + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func318.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func318.c new file mode 100644 index 0000000000..7df20cbcc1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func318.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func318 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1f080000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000e40U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0x030bb516U), + bswap_32big(0xa9363583U), + bswap_32big(0xc6b220d9U), + bswap_32big(0x84195d60U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x157f6cebU), bswap_32big(0x0d0ea321U), bswap_32big(0x2d4eba59U), + bswap_32big(0xb3073413U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x312282acU), bswap_32big(0xc49f1e0aU), bswap_32big(0x990e458eU), + bswap_32big(0x320fc040U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x19190009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x8a6da6a6U), bswap_32big(0xca2f50cdU), bswap_32big(0x185a481fU), + bswap_32big(0x6b6d11b2U)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x848b466bU), bswap_32big(0xf1b2db4fU), bswap_32big(0x5d4f5aecU), + bswap_32big(0x35f9ab17U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x1919000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x0000dee0U); + r_rsip_func101(bswap_32big(0xf4ec94fcU), bswap_32big(0xf09fb31eU), bswap_32big(0x52b4cf42U), + bswap_32big(0x444b5c93U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x19190009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xed48e28cU), bswap_32big(0x82424e00U), bswap_32big(0x6ab07c7fU), + bswap_32big(0xa6c9792bU)); + } + } + + WR1_PROG(REG_1404H, 0x17680000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func319.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func319.c new file mode 100644 index 0000000000..085005cc04 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func319.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func319 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1e480000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000e40U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0x2b18a501U), + bswap_32big(0x6b9f9bf3U), + bswap_32big(0x10db1661U), + bswap_32big(0x070c2bb6U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x8c104e84U), bswap_32big(0x3f065813U), bswap_32big(0x2fe38abaU), + bswap_32big(0xdba122edU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x31310009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x44352d4fU), bswap_32big(0xc5abe092U), bswap_32big(0xd7d518d4U), + bswap_32big(0x0fb7c4b3U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x502b4635U), bswap_32big(0x883c5953U), bswap_32big(0x5c2122c6U), + bswap_32big(0x495ea657U)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x961ec9e4U), bswap_32big(0xd6027f90U), bswap_32big(0xa6205a40U), + bswap_32big(0x64a8132aU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x31310009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x15b42ad3U), bswap_32big(0xfeb82206U), bswap_32big(0xa3ebfadaU), + bswap_32big(0xd1298d6bU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x0000dee0U); + r_rsip_func101(bswap_32big(0x85e8786bU), bswap_32big(0x2e80211bU), bswap_32big(0xb617e995U), + bswap_32big(0x40f7463dU)); + } + } + + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func320.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func320.c new file mode 100644 index 0000000000..b06bd4aaf4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func320.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func320 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1e480000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000e40U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0x1090030aU), + bswap_32big(0xb655c524U), + bswap_32big(0x8f602d83U), + bswap_32big(0x927ddf08U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x21863f6eU), bswap_32big(0xe351692dU), bswap_32big(0x5a641927U), + bswap_32big(0x64ef9e4aU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x3f4079dfU), bswap_32big(0x16a85b73U), bswap_32big(0x2d11d1e2U), + bswap_32big(0x4be73c6dU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x31310009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x67946269U), bswap_32big(0x342cae79U), bswap_32big(0x565c3bc3U), + bswap_32big(0x1fac9469U)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0xbd69cb85U), bswap_32big(0x404bf2e6U), bswap_32big(0x04d129baU), + bswap_32big(0xf9b01860U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x3131000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x0000dee0U); + r_rsip_func101(bswap_32big(0x70a32d22U), bswap_32big(0xea0cc3ecU), bswap_32big(0xb7108a92U), + bswap_32big(0xcf414bdeU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000838U); + WR1_PROG(REG_1004H, 0x31310009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x3359a07fU), bswap_32big(0xb2d8fd5fU), bswap_32big(0x2e09da47U), + bswap_32big(0x07543678U)); + } + } + + WR1_PROG(REG_1404H, 0x16a80000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func321.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func321.c new file mode 100644 index 0000000000..6bb3520504 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func321.c @@ -0,0 +1,900 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func321 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1600H, 0x0000373dU); + WR1_PROG(REG_1600H, 0x00000bdeU); + while (1) + { + WR1_PROG(REG_1404H, 0x12280000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x16580000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x9fbf56b4U), bswap_32big(0x8223cb62U), bswap_32big(0x962e59e4U), + bswap_32big(0xfb25eb44U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000230U); + WR1_PROG(REG_1020H, 0x00000230U); + WR1_PROG(REG_1004H, 0x4040000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1020H, 0x00000660U); + WR1_PROG(REG_1004H, 0x4040000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x00002fc0U); + r_rsip_func101(bswap_32big(0x44f55146U), bswap_32big(0x39157059U), bswap_32big(0x47eedb79U), + bswap_32big(0x9717cabdU)); + } + else + { + r_rsip_func101(bswap_32big(0xac380e98U), bswap_32big(0xcc7999acU), bswap_32big(0xac1ad7a5U), + bswap_32big(0x1afbca7aU)); + break; + } + } + + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1400H, 0x00c00211U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf9bf3112U)); + OFS_ADR = 136; + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003211U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x7b3532fcU), + bswap_32big(0xeb1bf883U), + bswap_32big(0x00fed6bcU), + bswap_32big(0x26e8635fU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x5bfa91b0U)); + OFS_ADR = 272; + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003212U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xcf2862b1U), + bswap_32big(0x50f66644U), + bswap_32big(0xdd1e69e6U), + bswap_32big(0x3bd0702eU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1404H, 0x18900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x9fd531f0U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003213U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x6d1e6169U), + bswap_32big(0x2d1ef853U), + bswap_32big(0x2db10e1dU), + bswap_32big(0xb6a93b58U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0c0ab7c4U)); + OFS_ADR = 408; + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003214U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x8080e075U), + bswap_32big(0x0c4533caU), + bswap_32big(0xebc35eddU), + bswap_32big(0xf08cf298U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x7edfb1abU)); + OFS_ADR = 544; + WR1_PROG(REG_1404H, 0x10300000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003215U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x53d2dd71U), + bswap_32big(0x3d8ee4fbU), + bswap_32big(0x79175aa7U), + bswap_32big(0xd2b4ab6dU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x8162b38bU)); + OFS_ADR = 676; + WR1_PROG(REG_1404H, 0x14600000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003216U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x9568d133U), + bswap_32big(0x58f5dcefU), + bswap_32big(0x236add2fU), + bswap_32big(0xf5ef8219U)); + r_rsip_func016(OFS_ADR); + while (1) + { + WR1_PROG(REG_1404H, 0x18900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000230U); + WR1_PROG(REG_1018H, 0x00000a90U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00210000U); + r_rsip_func100(bswap_32big(0x1d8ba92cU), bswap_32big(0x17411a79U), bswap_32big(0x47417322U), + bswap_32big(0x9e584798U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + r_rsip_func101(bswap_32big(0x89796701U), bswap_32big(0x8341c97cU), bswap_32big(0xa6b336d9U), + bswap_32big(0x6c55c63bU)); + break; + } + else + { + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x9fd531f0U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x12380000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003211U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x1dd9dd9cU), bswap_32big(0x9de4554bU), bswap_32big(0x77f1fb6dU), + bswap_32big(0xabe6bbfdU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf9bf3112U)); + OFS_ADR = 136; + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003212U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x3d46da21U), bswap_32big(0xff05b75aU), bswap_32big(0x4d87c0dbU), + bswap_32big(0x03fcd064U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003211U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x6acb1c01U), bswap_32big(0xa1c06746U), bswap_32big(0x7ac8e8abU), + bswap_32big(0xd1b9c376U)); + r_rsip_func322(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x9fd531f0U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x12380000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003217U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xb4e80901U), bswap_32big(0xfc24583eU), bswap_32big(0x49b69976U), + bswap_32big(0x46b50d3aU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf9bf3112U)); + OFS_ADR = 136; + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003218U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xa1bd20ffU), bswap_32big(0x92bf4ff4U), bswap_32big(0x8e6a924cU), + bswap_32big(0x0dc79eb9U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x5bfa91b0U)); + OFS_ADR = 272; + WR1_PROG(REG_1404H, 0x12380000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003213U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x3632c743U), bswap_32big(0x65913f6eU), bswap_32big(0xf2168e91U), + bswap_32big(0x9ea6d521U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0c0ab7c4U)); + OFS_ADR = 408; + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003214U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x63d18077U), bswap_32big(0x4b97bc8aU), bswap_32big(0x5deb77e4U), + bswap_32big(0xe02632e3U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x1dd80000U); + WR1_PROG(REG_1400H, 0x00c00201U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000230U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x40400009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000230U); + WR1_PROG(REG_1004H, 0x40400009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000660U); + WR1_PROG(REG_1004H, 0x40400009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003212U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xa156624aU), bswap_32big(0x2c2cba01U), bswap_32big(0x93144528U), + bswap_32big(0xab329f07U)); + r_rsip_func322(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x5bfa91b0U)); + OFS_ADR = 272; + WR1_PROG(REG_1404H, 0x12380000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003219U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x5f356242U), bswap_32big(0x72a86cefU), bswap_32big(0xff3dffbaU), + bswap_32big(0x918a69beU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0c0ab7c4U)); + OFS_ADR = 408; + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321aU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x596679b2U), bswap_32big(0xcacd9491U), bswap_32big(0xdbb55f84U), + bswap_32big(0x7d68411fU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1404H, 0x1dd80000U); + WR1_PROG(REG_1400H, 0x00c00201U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000230U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x40400009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000230U); + WR1_PROG(REG_1004H, 0x40400009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000660U); + WR1_PROG(REG_1004H, 0x40400009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000230U); + WR1_PROG(REG_1018H, 0x00000660U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0x00231b00U), bswap_32big(0xdc997757U), bswap_32big(0xa4740cafU), + bswap_32big(0xed0f13c3U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000230U); + WR1_PROG(REG_1004H, 0x40400009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x9fd531f0U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003215U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xd84ca561U), + bswap_32big(0xad70c105U), + bswap_32big(0x28e4027aU), + bswap_32big(0xb0d884ecU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x5bfa91b0U)); + OFS_ADR = 272; + WR1_PROG(REG_1404H, 0x1dc80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003216U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x16c60115U), + bswap_32big(0x93561bb6U), + bswap_32big(0x7d2e750dU), + bswap_32big(0xbb9ed60aU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003211U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xef0708cbU), + bswap_32big(0x8628fe83U), + bswap_32big(0x9a49d347U), + bswap_32big(0x036db239U)); + r_rsip_func324(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x9fd531f0U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321bU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x6be35146U), + bswap_32big(0x567ad338U), + bswap_32big(0x5ae17855U), + bswap_32big(0x3a670e7aU)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf9bf3112U)); + OFS_ADR = 136; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003217U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x2f0648d1U), + bswap_32big(0xc68a8d27U), + bswap_32big(0x022c552cU), + bswap_32big(0xc58aa259U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0c0ab7c4U)); + OFS_ADR = 408; + WR1_PROG(REG_1404H, 0x1dc80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003218U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x2672f28cU), + bswap_32big(0x1c4ac3e7U), + bswap_32big(0x6052c13fU), + bswap_32big(0x46adbb60U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003212U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x183e9ef2U), + bswap_32big(0x42bf1d42U), + bswap_32big(0x47e15dbfU), + bswap_32big(0x7fbfbccbU)); + r_rsip_func324(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf9bf3112U)); + OFS_ADR = 136; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321cU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x3479179fU), + bswap_32big(0x448b4373U), + bswap_32big(0xfd09bf8fU), + bswap_32big(0xcf754ed6U)); + r_rsip_func016(OFS_ADR); + r_rsip_func101(bswap_32big(0x03b2d372U), + bswap_32big(0x93e05cd4U), + bswap_32big(0xb1b6b0e0U), + bswap_32big(0x9ee92f95U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000230U); + WR1_PROG(REG_1020H, 0x00000660U); + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x5bfa91b0U)); + OFS_ADR = 272; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321aU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x10325768U), + bswap_32big(0xd6697732U), + bswap_32big(0x18b0f0fdU), + bswap_32big(0x25c358f1U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x9fd531f0U)); + OFS_ADR = 0; + WR1_PROG(REG_1404H, 0x1dc80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321bU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x0baf3cf6U), + bswap_32big(0x48984e2cU), + bswap_32big(0x6ee7cc5aU), + bswap_32big(0x32d455d9U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003213U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xc4f1c16bU), + bswap_32big(0x8fbeb87aU), + bswap_32big(0xe76928e2U), + bswap_32big(0xfce7e9d3U)); + r_rsip_func324(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x5bfa91b0U)); + OFS_ADR = 272; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321dU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x9e0262e1U), + bswap_32big(0x1fdca22bU), + bswap_32big(0x52b05ef2U), + bswap_32big(0xf38b5633U)); + r_rsip_func016(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0c0ab7c4U)); + OFS_ADR = 408; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321cU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xe3088868U), + bswap_32big(0x45bb0fe8U), + bswap_32big(0x01ffcd20U), + bswap_32big(0x14ed4107U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0xf9bf3112U)); + OFS_ADR = 136; + WR1_PROG(REG_1404H, 0x1dc80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321dU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xff98eea3U), + bswap_32big(0xdc4178efU), + bswap_32big(0xa49dcb8bU), + bswap_32big(0x1c05f1c9U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003214U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xd6bb27deU), + bswap_32big(0xc8df4617U), + bswap_32big(0x877446b0U), + bswap_32big(0xdb743a5cU)); + r_rsip_func324(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0c0ab7c4U)); + OFS_ADR = 408; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321eU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x19273b21U), + bswap_32big(0xe89208a1U), + bswap_32big(0x19abbf79U), + bswap_32big(0x3682d180U)); + r_rsip_func016(OFS_ADR); + r_rsip_func101(bswap_32big(0xd9eab1c7U), + bswap_32big(0xe8cf11d7U), + bswap_32big(0xad23639aU), + bswap_32big(0xb3f7e648U)); + } + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x7edfb1abU)); + OFS_ADR = 544; + WR1_PROG(REG_1404H, 0x10300000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321eU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x39d7cce0U), + bswap_32big(0x85759887U), + bswap_32big(0x7e2ec732U), + bswap_32big(0xf985c637U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x18900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + while (1) + { + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0x4e7eea18U), bswap_32big(0xccbf3c25U), bswap_32big(0x9e149799U), + bswap_32big(0x3321db56U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000a90U); + WR1_PROG(REG_1018H, 0x00000660U); + WR1_PROG(REG_1020H, 0x00000660U); + WR1_PROG(REG_1004H, 0x40400008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a90U); + WR1_PROG(REG_1018H, 0x00000230U); + WR1_PROG(REG_1020H, 0x00000230U); + WR1_PROG(REG_1004H, 0x40400008U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x000033c0U); + r_rsip_func101(bswap_32big(0x70e12068U), bswap_32big(0x17e56877U), bswap_32big(0xcf9b1f9dU), + bswap_32big(0xd91eb19eU)); + } + else + { + r_rsip_func101(bswap_32big(0xd30c0b7dU), bswap_32big(0x047d3c99U), bswap_32big(0xa4408661U), + bswap_32big(0x3b91b033U)); + break; + } + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0c0ab7c4U)); + OFS_ADR = 408; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000084U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000321fU)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x27c3d09dU), + bswap_32big(0x2b99a4acU), + bswap_32big(0x12d082ceU), + bswap_32big(0x2972f09eU)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + while (1) + { + WR1_PROG(REG_1014H, 0x00000230U); + WR1_PROG(REG_1018H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000a90U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00210000U); + r_rsip_func100(bswap_32big(0xd8bf9319U), bswap_32big(0xcdbf5f8aU), bswap_32big(0x6f4bbb0cU), + bswap_32big(0x60062f0eU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000230U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x61ff77fdU), bswap_32big(0x7f775e7fU), bswap_32big(0x795224a5U), + bswap_32big(0x380c81faU)); + } + else + { + r_rsip_func101(bswap_32big(0x1fa2bf08U), bswap_32big(0xc0a9a249U), bswap_32big(0xac2d290dU), + bswap_32big(0x60d67742U)); + break; + } + } + + WR1_PROG(REG_1600H, 0x3800db60U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0xf3d04496U), + bswap_32big(0x656599b8U), + bswap_32big(0x0c44dc80U), + bswap_32big(0x37ef4bccU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000230U); + WR1_PROG(REG_1018H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x254702a9U), bswap_32big(0xe88e33ceU), bswap_32big(0x9fb2e846U), + bswap_32big(0x37706fffU)); + } + else + { + r_rsip_func101(bswap_32big(0x3aa5f4c0U), bswap_32big(0x1b50bf80U), bswap_32big(0x055b0e62U), + bswap_32big(0xb1e1b0efU)); + } + + WR1_PROG(REG_1600H, 0x000037b9U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func322.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func322.c new file mode 100644 index 0000000000..b7faa91673 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func322.c @@ -0,0 +1,312 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func322 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1600H, 0x0000379dU); + while (1) + { + WR1_PROG(REG_1404H, 0x12280000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0xb1dd5988U), bswap_32big(0x6724050aU), bswap_32big(0x1fb6da00U), + bswap_32big(0xcb12386dU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000230U); + WR1_PROG(REG_1020H, 0x00000230U); + WR1_PROG(REG_1004H, 0x4040000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x14400000U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1a880000U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000135bU); + WR1_PROG(REG_1600H, 0x3800db40U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x70785f8eU), bswap_32big(0xf531bb18U), bswap_32big(0xd3f02cd6U), + bswap_32big(0xabcc7de7U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1404H, 0x12380000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x12380000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000448U); + WR1_PROG(REG_1020H, 0x00000448U); + WR1_PROG(REG_1004H, 0x4141000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1014H, 0x00000a90U); + WR1_PROG(REG_1020H, 0x00000a90U); + WR1_PROG(REG_1004H, 0x4141000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x12380000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1608H, 0x81010300U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func101(bswap_32big(0xb4b65d12U), + bswap_32big(0x0b0077e7U), + bswap_32big(0xb41fa2b3U), + bswap_32big(0x65c2a4c8U)); + } + else + { + WR1_PROG(REG_1404H, 0x1dc80000U); + WR1_PROG(REG_1400H, 0x00c00211U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x8162b38bU)); + OFS_ADR = 676; + WR1_PROG(REG_1404H, 0x1dd80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003221U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xacf207f3U), + bswap_32big(0x152726d7U), + bswap_32big(0x7e0bcc84U), + bswap_32big(0x4f5dc8e5U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1400H, 0x00c00211U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000448U); + WR1_PROG(REG_1018H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x42420009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f322U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xa2fa752eU), + bswap_32big(0x67b01aafU), + bswap_32big(0x7fa73a51U), + bswap_32big(0x78169ab1U)); + r_rsip_func323(); + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000448U); + WR1_PROG(REG_1004H, 0x4141000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x12380000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1dc80000U); + WR1_PROG(REG_1400H, 0x00c00211U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x7edfb1abU)); + OFS_ADR = 544; + WR1_PROG(REG_1404H, 0x1dd80000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x00003222U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xf66ac87eU), + bswap_32big(0xa61626cdU), + bswap_32big(0xc7b198c4U), + bswap_32big(0x17f1dfe4U)); + r_rsip_func017(OFS_ADR); + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1400H, 0x00c00211U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000a90U); + WR1_PROG(REG_1018H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x42420009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_PROG(REG_1420H, bswap_32big(0x0000f322U)); + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0x600e5cf9U), + bswap_32big(0xa890991eU), + bswap_32big(0xb69ce047U), + bswap_32big(0x336790b2U)); + r_rsip_func324(); + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000a90U); + WR1_PROG(REG_1004H, 0x4141000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1404H, 0x18800000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func101(bswap_32big(0x0e7039f5U), + bswap_32big(0x30767f49U), + bswap_32big(0x0ef2e8fbU), + bswap_32big(0x29d1f692U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x7e9a673eU), bswap_32big(0x90a84e5fU), bswap_32big(0xfdf8ac6dU), + bswap_32big(0xa0987c1fU)); + break; + } + } + + WR1_PROG(REG_1600H, 0x000037bcU); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func323.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func323.c new file mode 100644 index 0000000000..30dd4021e9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func323.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func323 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1dc80000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000dc0U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0x945462eeU), + bswap_32big(0xa59c720eU), + bswap_32big(0x18768e73U), + bswap_32big(0xf844a00bU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0xeadc10a8U), bswap_32big(0x04cc18bcU), bswap_32big(0xe8bf6fbaU), + bswap_32big(0x9df19199U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x41410009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xcd0914feU), bswap_32big(0x2ac84f0cU), bswap_32big(0x9c6493a8U), + bswap_32big(0x090c5e0dU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xeb6b2e3aU), bswap_32big(0x4f31f872U), bswap_32big(0x655c3e6aU), + bswap_32big(0xc2a68a7cU)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x7d255405U), bswap_32big(0xf9d0f42cU), bswap_32big(0x8c5c4764U), + bswap_32big(0x9908b252U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x41410009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x6ac26427U), bswap_32big(0x7f7a4df2U), bswap_32big(0x6062a048U), + bswap_32big(0x89ecfeffU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x0000dee0U); + r_rsip_func101(bswap_32big(0x3e061fc7U), bswap_32big(0x1e6904fbU), bswap_32big(0x1723f88aU), + bswap_32big(0x9e02fea2U)); + } + } + + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func324.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func324.c new file mode 100644 index 0000000000..6f212220ad --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func324.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +void r_rsip_func324 (void) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1608H, 0x800102e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x1dc80000U); + WR1_PROG(REG_1608H, 0x80010300U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000dc0U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_143CH, 0x00a10000U); + r_rsip_func100(bswap_32big(0xf69c273aU), + bswap_32big(0x13d0dc4dU), + bswap_32big(0xef687aceU), + bswap_32big(0xccb6d252U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x406125cdU), bswap_32big(0xd12ca7cbU), bswap_32big(0x25017b67U), + bswap_32big(0x526a9fefU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x969cc120U), bswap_32big(0x822333ffU), bswap_32big(0xdbf5ec45U), + bswap_32big(0x8dd3c9a4U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x41410009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0x1a9be375U), bswap_32big(0xfdeef395U), bswap_32big(0x16e7995aU), + bswap_32big(0xf1e06273U)); + } + } + else + { + WR1_PROG(REG_1600H, 0x38000af8U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + r_rsip_func100(bswap_32big(0x124150baU), bswap_32big(0x81090e58U), bswap_32big(0x5a3038f5U), + bswap_32big(0x45812fc7U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22U, 1U)) + { + WR1_PROG(REG_1014H, 0x00000fd8U); + WR1_PROG(REG_1018H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x4141000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + WR1_PROG(REG_1600H, 0x0000dee0U); + r_rsip_func101(bswap_32big(0x92f2b483U), bswap_32big(0x76827772U), bswap_32big(0x72c80721U), + bswap_32big(0x8ae46f4bU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000fd8U); + WR1_PROG(REG_1020H, 0x00000878U); + WR1_PROG(REG_1004H, 0x41410009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0U, 0U); + r_rsip_func101(bswap_32big(0xecbd178dU), bswap_32big(0xa4583182U), bswap_32big(0x104893bdU), + bswap_32big(0x8b6b5a49U)); + } + } + + WR1_PROG(REG_1404H, 0x16680000U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30U, 0U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func401.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func401.c new file mode 100644 index 0000000000..909402cfee --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func401.c @@ -0,0 +1,57 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func401 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x6212e267U)); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[4]); + WR1_PROG(REG_1404H, 0x14600000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[8]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[12]); + WR1_PROG(REG_1404H, 0x14b00000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[16]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func402.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func402.c new file mode 100644 index 0000000000..49ea3e8516 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func402.c @@ -0,0 +1,92 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func402 (void) +{ + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xe7c7a388U), + bswap_32big(0x6405c604U), + bswap_32big(0xa473c22aU), + bswap_32big(0xa487fa46U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000750U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000bb0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000007a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000c00U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000007f0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x872cd0c2U), bswap_32big(0x3971cf55U), bswap_32big(0x47df5790U), + bswap_32big(0x98c9a2f9U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000750U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000004d0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000007a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000520U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000007f0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xdfcff10dU), bswap_32big(0xdd0d6da3U), bswap_32big(0x80135499U), + bswap_32big(0xc7b3463aU)); + } + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func403.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func403.c new file mode 100644 index 0000000000..4eea6fa522 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func403.c @@ -0,0 +1,199 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func403 (void) +{ + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x000006b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000ac0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000ac0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000ac0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000ac0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000006b0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x000006b0U); + WR1_PROG(REG_1018H, 0x00000ac0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000340U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000390U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x00000ac0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000570U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000005c0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x000005c0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000610U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000005c0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000570U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000005c0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func404.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func404.c new file mode 100644 index 0000000000..ec5f005abe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func404.c @@ -0,0 +1,226 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func404 (void) +{ + WR1_PROG(REG_1014H, 0x00000610U); + WR1_PROG(REG_1018H, 0x000007f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000ac0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000700U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000750U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000005c0U); + WR1_PROG(REG_1018H, 0x000007a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000340U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000390U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000390U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000700U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000660U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000006b0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x000005c0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000750U); + WR1_PROG(REG_1018H, 0x000007a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000390U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000390U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000660U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func405.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func405.c new file mode 100644 index 0000000000..da8bcc6c64 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func405.c @@ -0,0 +1,32 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func405 (void) +{ + WR1_PROG(REG_1600H, 0x000037e8U); + WR1_PROG(REG_1600H, 0x00056bffU); + WR1_PROG(REG_1600H, 0x00026fffU); + WR1_PROG(REG_1600H, 0x0000381fU); + + WR1_PROG(REG_1600H, 0x000037e8U); + WR1_PROG(REG_1600H, 0x000037c1U); + WR1_PROG(REG_1600H, 0x00000fe1U); + WR1_PROG(REG_1600H, 0x00002bdfU); + WR1_PROG(REG_1600H, 0x0000441eU); + WR1_PROG(REG_1600H, 0x00007400U); + WR1_PROG(REG_1600H, 0x00000c13U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func406.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func406.c new file mode 100644 index 0000000000..e55dee1946 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func406.c @@ -0,0 +1,112 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func406 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x785d648dU)); + + WR1_PROG(REG_1404H, 0x10500000U); + WR1_PROG(REG_1444H, 0x000033c2U); + WR1_PROG(REG_1A2CH, 0x00000c00U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[24]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10a00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[28]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[32]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11e00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[36]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[40]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10000000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[44]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11900000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[48]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[52]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[56]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[60]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11400000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[64]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[68]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[72]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1af00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func407.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func407.c new file mode 100644 index 0000000000..2c614b5644 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func407.c @@ -0,0 +1,128 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func407 (const uint32_t ARG1[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x0000379dU); + + r_rsip_func100(bswap_32big(0x697fdaaeU), + bswap_32big(0xce07b0a7U), + bswap_32big(0x2a561da2U), + bswap_32big(0x3540d86fU)); + WR1_PROG(REG_1608H, 0x810100c0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f407U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdddf44b0U), + bswap_32big(0x196546c3U), + bswap_32big(0xb36e0473U), + bswap_32big(0x17543918U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e5U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f407U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1481edd1U), + bswap_32big(0x7c777a33U), + bswap_32big(0x6c537039U), + bswap_32big(0xa8853563U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1600H, 0x000008a5U); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[1 + iLoop]); + + WR1_PROG(REG_1608H, 0x80840005U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x638e4599U), bswap_32big(0xcaff2167U), bswap_32big(0xe247c414U), + bswap_32big(0x16dfb792U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x380008c7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000037bcU); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func408.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func408.c new file mode 100644 index 0000000000..fbc17212d1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func408.c @@ -0,0 +1,48 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func408 (void) +{ + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000000cU); + + WR1_PROG(REG_1404H, 0x10000000U); + + WR1_PROG(REG_1608H, 0x81910005U); + WR1_PROG(REG_1400H, 0x00c90045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1404H, 0x10000000U); + + WR1_PROG(REG_1608H, 0x80940005U); + WR1_PROG(REG_1400H, 0x10030009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x13430109U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1400H, 0x13400039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x10000009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func420.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func420.c new file mode 100644 index 0000000000..32bcd56e2a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func420.c @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func420 (void) +{ + WR1_PROG(REG_1600H, 0x000037c0U); + WR1_PROG(REG_1600H, 0x00076bdeU); + WR1_PROG(REG_1600H, 0x00026fdeU); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1600H, 0x00020020U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1600H, 0x2000abc0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func421.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func421.c new file mode 100644 index 0000000000..da4ac0cca3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func421.c @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func421 (void) +{ + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func422.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func422.c new file mode 100644 index 0000000000..e419bd7b53 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func422.c @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func422 (const uint32_t ARG1[], uint32_t ARG2) +{ + uint32_t jLoop = 0U; + + r_rsip_func100(bswap_32big(0xa5963577U), + bswap_32big(0xac8d53eeU), + bswap_32big(0xb4eb4162U), + bswap_32big(0x3865a5e3U)); + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80840007U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[ARG2 + 4]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[ARG2 + 5]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[ARG2 + 6]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[ARG2 + 7]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x00003500U); + WR1_PROG(REG_1600H, 0x00036908U); + WR1_PROG(REG_1600H, 0x00008d00U); + WR1_PROG(REG_1600H, 0x0000000cU); + + WR1_PROG(REG_1600H, 0x000024c8U); + + WR1_PROG(REG_1600H, 0x000024e8U); + + WR1_PROG(REG_1600H, 0x00003826U); + + WR1_PROG(REG_1600H, 0x00003847U); + + WR1_PROG(REG_1600H, 0x00003460U); + WR1_PROG(REG_1600H, 0x00008c60U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0xffffffffU); + WR1_PROG(REG_1600H, 0x00004403U); + WR1_PROG(REG_1600H, 0x00007484U); + + WR1_PROG(REG_1600H, 0x00000c24U); + + WR1_PROG(REG_1600H, 0x00001484U); + + WR1_PROG(REG_1600H, 0x00000c44U); + + WR1_PROG(REG_1600H, 0x00001041U); + + WR1_PROG(REG_1600H, 0x00003c47U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1600H, 0x0000007fU); + + WR1_PROG(REG_1600H, 0x38008fe0U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x1000a7e0U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00002bdfU); + WR1_PROG(REG_1600H, 0x00056bdeU); + WR1_PROG(REG_1600H, 0x0000353eU); + + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1600H, 0x000024e5U); + + WR1_PROG(REG_1600H, 0x00003b86U); + WR1_PROG(REG_1600H, 0x00003f87U); + + WR1_PROG(REG_1600H, 0x000033c0U); + r_rsip_func101(bswap_32big(0xb77f8759U), bswap_32big(0xdaf38eccU), bswap_32big(0x122d89bdU), + bswap_32big(0xc1f0ee34U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func423.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func423.c new file mode 100644 index 0000000000..30cca8b35a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func423.c @@ -0,0 +1,73 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func423 (uint32_t ARG1[], uint32_t ARG2) +{ + uint32_t jLoop = 0U; + + WR1_PROG(REG_1600H, 0x000008c6U); + + WR1_PROG(REG_1600H, 0x000024c8U); + + WR1_PROG(REG_1600H, 0x00003826U); + + WR1_PROG(REG_1600H, 0x00000c24U); + + WR1_PROG(REG_1600H, 0x00003c26U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + + WR1_PROG(REG_1600H, 0x00003fe6U); + + WR1_PROG(REG_1600H, 0x00003120U); + r_rsip_func101(bswap_32big(0x3cd11efeU), bswap_32big(0x247c55d2U), bswap_32big(0x73a3eb4cU), + bswap_32big(0xf970f89dU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x552f951bU), + bswap_32big(0x58204dc9U), + bswap_32big(0xfe1ab997U), + bswap_32big(0x8e59d6bdU)); + WR1_PROG(REG_1600H, 0x38000d29U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1608H, 0x81840006U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &ARG1[ARG2 + 4]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &ARG1[ARG2 + 5]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &ARG1[ARG2 + 6]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &ARG1[ARG2 + 7]); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func424.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func424.c new file mode 100644 index 0000000000..ce4c449096 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func424.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func424 (void) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x00000bffU); + + for (iLoop = 0U; iLoop < 4; iLoop++) + { + WR1_PROG(REG_1600H, 0x00003840U); + WR1_PROG(REG_1600H, 0x00003861U); + + WR1_PROG(REG_1600H, 0x38000843U); + WR1_PROG(REG_1600H, 0x2000b7e0U); + WR1_PROG(REG_1600H, 0x1ae211e9U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func501.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func501.c new file mode 100644 index 0000000000..81c2665718 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_func501.c @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func501 (uint32_t ARG1[], uint32_t ARG2) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0e108406U); + + for (iLoop = 0U; iLoop < ARG2; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p00.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p00.c new file mode 100644 index 0000000000..5ccaf06536 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p00.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_reg.h" +#include "r_rsip_primitive.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p00 (void) +{ + WR1_PROG(REG_140CH, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + +/*********************************************************************************************************************** + ***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p07.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p07.c new file mode 100644 index 0000000000..c211d1b9fc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p07.c @@ -0,0 +1,142 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p07 (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00070001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000701U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2b8cfa4fU), + bswap_32big(0xe4bb921bU), + bswap_32big(0xd62d0dfbU), + bswap_32big(0xfb3cc0ebU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000007U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x14c74b78U), + bswap_32big(0xae7a894eU), + bswap_32big(0xc29ad69dU), + bswap_32big(0x44ee96c9U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000007U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd630f09aU), + bswap_32big(0x6b56d023U), + bswap_32big(0x5f2a04b0U), + bswap_32big(0xd40d019eU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xac328280U), + bswap_32big(0x7295a54fU), + bswap_32big(0x8639b49fU), + bswap_32big(0xecaccbdcU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000702U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xaa75e6fdU), + bswap_32big(0xd192de85U), + bswap_32big(0x4fee36ffU), + bswap_32big(0x3fd63c90U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7009d45U); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xfa424195U), + bswap_32big(0xa02ad773U), + bswap_32big(0x24948af7U), + bswap_32big(0x7fc9654cU)); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000001U)); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + + r_rsip_func102(bswap_32big(0xa34d52c8U), + bswap_32big(0x2b63eb59U), + bswap_32big(0xd03daa87U), + bswap_32big(0x871e8f7cU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p08.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p08.c new file mode 100644 index 0000000000..55d9b60e68 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p08.c @@ -0,0 +1,163 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p08 (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00080001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000801U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5f589dfbU), + bswap_32big(0x150a25beU), + bswap_32big(0x6d98128fU), + bswap_32big(0xa71a463fU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000008U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x45693b6bU), + bswap_32big(0x68cbd215U), + bswap_32big(0xcd24384aU), + bswap_32big(0x31dc4e9cU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000008U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5be22900U), + bswap_32big(0xf07394d9U), + bswap_32big(0x8dbad761U), + bswap_32big(0x00246267U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xda537d01U), + bswap_32big(0xf707e590U), + bswap_32big(0x50229f5dU), + bswap_32big(0x7738a7b5U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000802U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd9b62a99U), + bswap_32big(0x3a3600a7U), + bswap_32big(0x4a6881b3U), + bswap_32big(0x2eb0bfeeU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000803U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x10881f30U), + bswap_32big(0x3829e559U), + bswap_32big(0x5f41533aU), + bswap_32big(0xe5ba4884U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func100(bswap_32big(0x346078a8U), + bswap_32big(0x76f267b6U), + bswap_32big(0x3385d467U), + bswap_32big(0x60836a5aU)); + + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81080000U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000002U)); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + r_rsip_func102(bswap_32big(0x8412a131U), + bswap_32big(0xd88c9644U), + bswap_32big(0x39eba840U), + bswap_32big(0x8bc5ab71U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0a.c new file mode 100644 index 0000000000..7eed24f05a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0a.c @@ -0,0 +1,166 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p0a (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x000a0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa8f23ddcU), + bswap_32big(0x03d3f5b3U), + bswap_32big(0x6cfe5115U), + bswap_32big(0xce886a44U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfe6103c2U), + bswap_32big(0xaff19ce7U), + bswap_32big(0x8afd270eU), + bswap_32big(0x000e36d0U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000001aU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1efeae3cU), + bswap_32big(0x01f0f7dcU), + bswap_32big(0x215f8d58U), + bswap_32big(0x807b3d17U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x57ee6a4bU), + bswap_32big(0xf23b2c01U), + bswap_32big(0xb6225974U), + bswap_32big(0x78482520U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xedc15dbcU), + bswap_32big(0x663d6080U), + bswap_32big(0xacefa043U), + bswap_32big(0xcd90f8b1U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000a03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8971c83aU), + bswap_32big(0x8632248fU), + bswap_32big(0xb94afa61U), + bswap_32big(0xb961ee63U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x90f50d97U), + bswap_32big(0x8952ecb2U), + bswap_32big(0x0e27f81dU), + bswap_32big(0xef979cdcU)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81070000U); + WR1_PROG(REG_1400H, 0x0089001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00800005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000002U)); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + r_rsip_func102(bswap_32big(0x96e46d58U), + bswap_32big(0x8d4cb3fcU), + bswap_32big(0x98f78456U), + bswap_32big(0x844c6b6bU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0b.c new file mode 100644 index 0000000000..30df17c992 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0b.c @@ -0,0 +1,163 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p0b (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x000b0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4842f6a2U), + bswap_32big(0xa209ce9bU), + bswap_32big(0x303c5d3cU), + bswap_32big(0x9523ece0U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4c2a99e5U), + bswap_32big(0x8aee295dU), + bswap_32big(0xd11e90afU), + bswap_32big(0x1ba3160dU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000001bU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x62c1f37bU), + bswap_32big(0x1d97b516U), + bswap_32big(0x27192504U), + bswap_32big(0xbdad33bfU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x451fcb42U), + bswap_32big(0x93430809U), + bswap_32big(0xb2d13a62U), + bswap_32big(0x5f6a085fU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x12bbca56U), + bswap_32big(0xf21d3cadU), + bswap_32big(0x4c17f2cbU), + bswap_32big(0xc3ad1732U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000b03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x653c699eU), + bswap_32big(0xca77f89cU), + bswap_32big(0xc3c67a93U), + bswap_32big(0xb605724aU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + r_rsip_func100(bswap_32big(0xdba1f209U), + bswap_32big(0xac9e20a4U), + bswap_32big(0x563dbe64U), + bswap_32big(0xb9efa32eU)); + + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81080000U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000002U)); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + r_rsip_func102(bswap_32big(0xc8ef061fU), + bswap_32big(0x50a96df1U), + bswap_32big(0xf06cd8fbU), + bswap_32big(0x260bd72cU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0c.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0c.c new file mode 100644 index 0000000000..16404a2172 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0c.c @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p0c (const uint32_t InData_CurrentVer[], const uint32_t InData_NextVer[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x000c0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + r_rsip_func048(InData_CurrentVer); + + r_rsip_func049(InData_NextVer); + + WR1_PROG(REG_1600H, 0x34202880U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xa006fff8U), + bswap_32big(0xd93cd0bbU), + bswap_32big(0xcdb66f1eU), + bswap_32big(0x184dd992U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_14BCH, 0x00000020U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_VERIFICATION_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38002880U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x3983300cU), bswap_32big(0xf424286cU), bswap_32big(0x74c57a20U), + bswap_32big(0x880d5960U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1B08H, 0x00000215U); + + r_rsip_func102(bswap_32big(0x937ec401U), bswap_32big(0x67c174b4U), bswap_32big(0xc32d39c1U), + bswap_32big(0x80bc13f3U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_VERSION_MATCH; + } + else + { + WR1_PROG(REG_1B08H, 0x00000215U); + + r_rsip_func102(bswap_32big(0x3adff011U), bswap_32big(0xf98f1382U), bswap_32big(0xcc6f21a7U), + bswap_32big(0x9774e299U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0d.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0d.c new file mode 100644 index 0000000000..2cddbe1f2f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0d.c @@ -0,0 +1,1385 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p0d (const uint32_t InData_KeyCertificate[], + const uint32_t InData_KeyCertificateLength[], + const uint32_t InData_KeyCertificateSignature[], + const uint32_t InData_KeyCertificatePubKey[], + const uint32_t InData_ImgPkHash[], + const uint32_t InData_OemRootPkHashIndex[], + const uint32_t InData_CodeCertificate[], + const uint32_t InData_CodeCertificateLength[], + const uint32_t InData_CodeCertificateSignature[], + const uint32_t InData_CodeCertificatePubKey[], + const uint32_t InData_Image[], + const uint32_t InData_DomainParam[], + uint32_t MAX_CNT, + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + uint32_t iTemp = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x000d0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000004c7U); + WR1_PROG(REG_1608H, 0x800501e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CodeCertificateLength[0]); + for (iLoop = 0U; iLoop < 4; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CodeCertificatePubKey[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000006c7U); + WR1_PROG(REG_1608H, 0x800702c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyCertificateLength[0]); + for (iLoop = 0U; iLoop < 4; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyCertificatePubKey[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 2U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_ImgPkHash[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x34202af8U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202b19U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202b3aU); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202b5bU); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202b7cU); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202b96U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x00003417U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x08000818U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x00003419U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x0800081aU); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x0000341bU); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x0800081cU); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x34202bd0U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202a11U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202a32U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202a53U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x34202a6fU); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x00003410U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x08000811U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x00003412U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x08000813U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x5a19a28aU), + bswap_32big(0xc3fce2b4U), + bswap_32big(0x0a45ed75U), + bswap_32big(0xbf0e93e6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_14BCH, 0x00000020U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PARAM_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x3d321d68U), bswap_32big(0x7b98f83cU), bswap_32big(0xe3d49b91U), + bswap_32big(0x3c8ef22dU)); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00003436U); + + WR1_PROG(REG_1600H, 0x01836c01U); + WR1_PROG(REG_1600H, 0x00036c21U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1408H, 0x0000500aU); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + + r_rsip_func100(bswap_32big(0xcf472b35U), bswap_32big(0x51d463b2U), bswap_32big(0x683122a4U), + bswap_32big(0xef03e8e6U)); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, S_RAM[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, S_RAM[0 + 1]); + + WR1_PROG(REG_1600H, 0x00003417U); + WR1_PROG(REG_1600H, 0x00046800U); + WR1_PROG(REG_1600H, 0x00026c00U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x000008a5U); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1444H, 0x000003c4U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyCertificate[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x5081cf2aU), bswap_32big(0xb75c1a81U), bswap_32big(0xdfd26d14U), + bswap_32big(0x22a59465U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xf7f01f28U), bswap_32big(0x22a79eddU), bswap_32big(0xbd0db958U), + bswap_32big(0x62431676U)); + + WR1_PROG(REG_1600H, 0x38000805U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1404H, 0x10000000U); + + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x00026800U); + WR1_PROG(REG_1600H, 0x38008ec0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x20002c00U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x00003445U); + WR1_PROG(REG_1600H, 0x00026c42U); + + WR1_PROG(REG_1600H, 0x000034d6U); + WR1_PROG(REG_1600H, 0x000030c0U); + + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000180U); + + iTemp = iLoop; + for (iLoop = iTemp; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyCertificate[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000004U); + + for (jLoop = 0U; jLoop < 4; jLoop++) + { + WR1_PROG(REG_1600H, 0x00003020U); + + WR1_PROG(REG_1600H, 0x01886ce8U); + WR1_PROG(REG_1600H, 0x00086d08U); + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c002859U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x3c002b42U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xebe2ac0eU), + bswap_32big(0x78ec0a6cU), + bswap_32big(0x70feb889U), + bswap_32big(0x78e0d136U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x10c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x89721c48U), + bswap_32big(0x99e823a3U), + bswap_32big(0xd38c74f1U), + bswap_32big(0xe470a45dU)); + } + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c002857U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x3c002b02U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xc43af23bU), + bswap_32big(0xe09d4306U), + bswap_32big(0xb6ffe941U), + bswap_32big(0x84ff5436U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x10c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xe9471574U), + bswap_32big(0x4340cc57U), + bswap_32big(0xcdb1caa3U), + bswap_32big(0x37a86996U)); + } + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c00285bU); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x3c002b82U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xa9784474U), + bswap_32big(0x615bc6edU), + bswap_32big(0xd250cc05U), + bswap_32big(0xe48f0defU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x02003ce9U); + WR1_PROG(REG_1600H, 0x00002d20U); + r_rsip_func101(bswap_32big(0xe2108c5cU), + bswap_32big(0x69bf3cd0U), + bswap_32big(0x69f2cd61U), + bswap_32big(0xcd0cb441U)); + } + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c0028c2U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x0fcb4f5aU), + bswap_32big(0x3fb69779U), + bswap_32big(0xc8405c5dU), + bswap_32big(0x2c245611U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x11490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xa17f657bU), + bswap_32big(0xa2c98cdfU), + bswap_32big(0xfa206f23U), + bswap_32big(0x6b449d7fU)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + + r_rsip_func101(bswap_32big(0x0f39f874U), + bswap_32big(0x115e6b00U), + bswap_32big(0x7e87ceebU), + bswap_32big(0x0187cd32U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08000c21U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0x5f998a3bU), bswap_32big(0x45335dd5U), bswap_32big(0x8922604aU), + bswap_32big(0xc8e4775fU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000805U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x0d2466fbU), bswap_32big(0xde474549U), bswap_32big(0xb5a9eca5U), + bswap_32big(0x3095153fU)); + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00002840U); + + WR1_PROG(REG_1600H, 0x00008c40U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1608H, 0x81010040U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000000U); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1400H, 0x11490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00086c63U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0xd2e2a759U), bswap_32big(0xfff888c7U), bswap_32big(0x29f1d2d0U), + bswap_32big(0xc0c1e4ebU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000845U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x00000929U); + WR1_PROG(REG_1608H, 0x80880009U); + WR1_PROG(REG_1400H, 0x03450021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_2010H, 0x00000200U); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x01430041U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x000000fdU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdb3052a8U), bswap_32big(0xb7f1af97U), bswap_32big(0xdf35612aU), + bswap_32big(0xc22fb133U)); + r_rsip_func043(); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x37b96c17U), bswap_32big(0xf6bb586aU), bswap_32big(0x4c781037U), + bswap_32big(0x17ba4317U)); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0x0900890fU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_OemRootPkHashIndex[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_OemRootPkHashIndex[4]); + + WR1_PROG(REG_1A24H, 0x08000055U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00850011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x08000055U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00850011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xf18ea06fU), bswap_32big(0x273dad0dU), bswap_32big(0x3dde803eU), + bswap_32big(0xa801896eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_14BCH, 0x00000020U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_VERIFICATION_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1400H, 0x03430041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1444H, 0x00000fc1U); + WR1_PROG(REG_182CH, 0x00000300U); + WR1_PROG(REG_1824H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyCertificateSignature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyCertificateSignature[4]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19600000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyCertificateSignature[8]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyCertificateSignature[12]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000b5aU); + WR1_PROG(REG_1600H, 0x00000b9cU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000d01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1cbf9403U), bswap_32big(0xff5237f6U), bswap_32big(0x1aea544cU), + bswap_32big(0xdb30e1bdU)); + r_rsip_func073(InData_DomainParam); + + r_rsip_func100(bswap_32big(0xda978056U), bswap_32big(0x812e105dU), bswap_32big(0x3d36d693U), + bswap_32big(0xe9f42218U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_14BCH, 0x00000020U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_VERIFICATION_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x4506db4aU), + bswap_32big(0x401df0a0U), + bswap_32big(0xf695b240U), + bswap_32big(0x20b6de78U)); + + WR1_PROG(REG_1600H, 0x000036cfU); + WR1_PROG(REG_1600H, 0x000036f0U); + WR1_PROG(REG_1600H, 0x00003711U); + WR1_PROG(REG_1600H, 0x00003732U); + WR1_PROG(REG_1600H, 0x00003753U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010160U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, MAX_CNT); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000342bU); + + WR1_PROG(REG_1600H, 0x01826c01U); + WR1_PROG(REG_1600H, 0x00026c21U); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1600H, 0x0c002436U); + WR1_PROG(REG_1600H, 0x00802406U); + + WR1_PROG(REG_1600H, 0x01836c01U); + WR1_PROG(REG_1600H, 0x00036c21U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1408H, 0x0000500aU); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + + r_rsip_func100(bswap_32big(0x4fe5e312U), + bswap_32big(0xb57c2757U), + bswap_32big(0xb4663336U), + bswap_32big(0x744515d8U)); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, S_RAM[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, S_RAM[0 + 1]); + + WR1_PROG(REG_1600H, 0x00003417U); + WR1_PROG(REG_1600H, 0x00046800U); + WR1_PROG(REG_1600H, 0x00026c00U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x501f45b0U), + bswap_32big(0xcf4c42d9U), + bswap_32big(0xf3329b50U), + bswap_32big(0xc52a8eebU)); + r_rsip_func103(); + + r_rsip_func100(bswap_32big(0x0601662cU), + bswap_32big(0x07d78a49U), + bswap_32big(0xd0710447U), + bswap_32big(0x796ca9e2U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000003a1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x8ab22685U), + bswap_32big(0xbfab115bU), + bswap_32big(0x841c0f17U), + bswap_32big(0xa1af8aa1U)); + + WR1_PROG(REG_1824H, 0x0e0c0446U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000090U); + + WR1_PROG(REG_1444H, 0x000007c7U); + WR1_PROG(REG_1608H, 0x8088001fU); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CodeCertificate[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x8188001fU); + WR1_PROG(REG_1400H, 0x02490021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000008U); + + for (iLoop = 8; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1444H, 0x000003caU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_CodeCertificate[iLoop]); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x505bd04aU), + bswap_32big(0x6f02fbc4U), + bswap_32big(0xa1cf524aU), + bswap_32big(0xe64025b6U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x83bff524U), + bswap_32big(0xed503092U), + bswap_32big(0x9ffd14dfU), + bswap_32big(0x9d981f0eU)); + + WR1_PROG(REG_1600H, 0x38000805U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10000000U); + + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x00026800U); + WR1_PROG(REG_1600H, 0x38008ec0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x20002c00U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x00003445U); + WR1_PROG(REG_1600H, 0x00026c42U); + + WR1_PROG(REG_1600H, 0x000034d6U); + WR1_PROG(REG_1600H, 0x000030c0U); + + iTemp = iLoop; + for (iLoop = iTemp; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CodeCertificate[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000004U); + + for (jLoop = 0U; jLoop < 4; jLoop++) + { + WR1_PROG(REG_1600H, 0x00003020U); + + WR1_PROG(REG_1600H, 0x01886ce8U); + WR1_PROG(REG_1600H, 0x00086d08U); + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c002859U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x3c002b42U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x8c164b95U), + bswap_32big(0x3c32fd0fU), + bswap_32big(0x0a516bb1U), + bswap_32big(0xddf95c50U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x10c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xec0fc5c8U), + bswap_32big(0x6144c68aU), + bswap_32big(0xb7e7bcbeU), + bswap_32big(0xb7ede7f5U)); + } + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c002857U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x3c002b02U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x0af6d1f2U), + bswap_32big(0x8665d3c5U), + bswap_32big(0x50d1dd0eU), + bswap_32big(0x3ef364c4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x10c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xb1432e78U), + bswap_32big(0x0995a7b7U), + bswap_32big(0x66d6bf47U), + bswap_32big(0xd08fde38U)); + } + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c0028c2U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x65ccdc79U), + bswap_32big(0xaf4bfebfU), + bswap_32big(0x673edc84U), + bswap_32big(0x009b678cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x12490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x5ad8157eU), + bswap_32big(0x08efb79bU), + bswap_32big(0x8435a772U), + bswap_32big(0x9a2b12d9U)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + + r_rsip_func101(bswap_32big(0xd3d39bcaU), + bswap_32big(0x465e7014U), + bswap_32big(0x83a9b1c2U), + bswap_32big(0x44ddb393U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08000c21U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0xace4cca9U), + bswap_32big(0xb4da0198U), + bswap_32big(0x44496754U), + bswap_32big(0x94724b21U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000805U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000030U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000d01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7dda89d5U), + bswap_32big(0x7fe11744U), + bswap_32big(0x2b9e0094U), + bswap_32big(0xc98f0645U)); + r_rsip_func083(InData_Image); + + WR1_PROG(REG_1600H, 0x00000929U); + WR1_PROG(REG_1608H, 0x80880009U); + WR1_PROG(REG_1400H, 0x03450021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_2010H, 0x00000200U); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x01430041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000180U); + WR1_PROG(REG_1A24H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81840009U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x9c000005U); + WR1_PROG(REG_1400H, 0x00850011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a520U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1A24H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81840009U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x9c000005U); + WR1_PROG(REG_1400H, 0x00850011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x7e6c155eU), + bswap_32big(0xe34ab487U), + bswap_32big(0xdb30c0afU), + bswap_32big(0x42fa0182U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_14BCH, 0x00000020U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_VERIFICATION_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1400H, 0x03430041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1444H, 0x00000fc1U); + WR1_PROG(REG_182CH, 0x00000300U); + WR1_PROG(REG_1824H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_CodeCertificateSignature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_CodeCertificateSignature[4]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19600000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_CodeCertificateSignature[8]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_CodeCertificateSignature[12]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000b5aU); + WR1_PROG(REG_1600H, 0x00000b9cU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000d02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x032af6f9U), + bswap_32big(0x1566cf9aU), + bswap_32big(0x17afdde4U), + bswap_32big(0xa92c3c12U)); + r_rsip_func073(InData_DomainParam); + + r_rsip_func100(bswap_32big(0x1f6c4198U), + bswap_32big(0x9c46fd47U), + bswap_32big(0xa53c2456U), + bswap_32big(0x3c2e5212U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_14BCH, 0x00000020U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_VERIFICATION_FAIL; + } + else + { + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_2008H, 0x00000013U); + + WR1_PROG(REG_1600H, 0x000037ebU); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01522594U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x810d03cbU), + bswap_32big(0x3b5ba7afU), + bswap_32big(0xfceb03bbU), + bswap_32big(0x128b21b9U)); + r_rsip_func082(); + + WR1_PROG(REG_1600H, 0x0000357fU); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00003436U); + WR1_PROG(REG_1600H, 0x01836c01U); + WR1_PROG(REG_1600H, 0x00036c21U); + + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000346bU); + WR1_PROG(REG_1600H, 0x01856c43U); + WR1_PROG(REG_1600H, 0x00056c63U); + + WR1_PROG(REG_1600H, 0x0c002423U); + WR1_PROG(REG_1600H, 0x00802402U); + + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0c00a420U); + WR1_PROG(REG_1600H, 0x00000200U); + WR1_PROG(REG_1600H, 0x00802402U); + + WR1_PROG(REG_1600H, 0x38001001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x28a09012U), + bswap_32big(0x32c1bbe5U), + bswap_32big(0x75350176U), + bswap_32big(0x07ea20f0U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000080U); + + WR1_PROG(REG_200CH, 0x00000001U); + + WAIT_STS(REG_2030H, 8, 0); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000000U); + + WR1_PROG(REG_200CH, 0x00000100U); + + WAIT_STS(REG_2030H, 4, 1); + + r_rsip_func100(bswap_32big(0x3470fe60U), + bswap_32big(0x6038d875U), + bswap_32big(0x5c49920cU), + bswap_32big(0x1466ad29U)); + WR1_PROG(REG_1408H, 0x00004022U); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MAC[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1B08H, 0x00000216U); + + r_rsip_func102(bswap_32big(0x23089c47U), + bswap_32big(0xbacad5d2U), + bswap_32big(0x1aaf3f13U), + bswap_32big(0xd09fa1e1U)); + WR1_PROG(REG_149CH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + else + { + r_rsip_func100(bswap_32big(0xd4c123c7U), + bswap_32big(0x1a9ed1c9U), + bswap_32big(0x8e8a5ab1U), + bswap_32big(0xf78792fdU)); + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1408H, 0x0000500aU); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, S_RAM[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, S_RAM[0 + 1]); + + WR1_PROG(REG_200CH, 0x00000001U); + + r_rsip_func100(bswap_32big(0x1a9d11bfU), + bswap_32big(0x62cf9404U), + bswap_32big(0x6962b083U), + bswap_32big(0xf19a64d2U)); + WR1_PROG(REG_1444H, 0x000003a1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x8ab22685U), bswap_32big(0xbfab115bU), + bswap_32big(0x841c0f17U), bswap_32big(0xa1af8aa1U)); + + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x00026800U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0xfffffffcU); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1824H, 0x0e0c0446U); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1444H, 0x000003caU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_CodeCertificate[iLoop]); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x5c292978U), bswap_32big(0x60c7bff0U), + bswap_32big(0x3ef9b0a2U), bswap_32big(0x96ff5accU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func100(bswap_32big(0x807d1fd1U), + bswap_32big(0xafdd4ee9U), + bswap_32big(0x6121e6b6U), + bswap_32big(0x4fc0714bU)); + + WR1_PROG(REG_1600H, 0x38000805U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x00026800U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x00003445U); + WR1_PROG(REG_1600H, 0x00026c42U); + + WR1_PROG(REG_1600H, 0x000034d6U); + WR1_PROG(REG_1600H, 0x000030c0U); + + iTemp = iLoop; + for (iLoop = iTemp; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CodeCertificate[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000004U); + + for (jLoop = 0U; jLoop < 4; jLoop++) + { + WR1_PROG(REG_1600H, 0x00003020U); + + WR1_PROG(REG_1600H, 0x01886ce8U); + WR1_PROG(REG_1600H, 0x00086d08U); + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c0028c2U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x94552a48U), bswap_32big(0xe58be834U), + bswap_32big(0x9ff2f743U), bswap_32big(0xb0673975U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x12490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x81c74b5cU), bswap_32big(0x4453b1cdU), + bswap_32big(0x3ce7e6f4U), bswap_32big(0xcdd3e4a0U)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + + r_rsip_func101(bswap_32big(0x3260293cU), bswap_32big(0xcff54e13U), + bswap_32big(0x2b81adb4U), bswap_32big(0xcac1a2daU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x08000c21U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0x4af10ec7U), bswap_32big(0x81f4dd98U), + bswap_32big(0x067aea8cU), bswap_32big(0xd733d0a5U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000805U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1400H, 0x11430081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x19600000U); + WR1_PROG(REG_1400H, 0x11430081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000d02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0ea2b246U), + bswap_32big(0x20949da3U), + bswap_32big(0xb7b4fd6fU), + bswap_32big(0x1f73d099U)); + r_rsip_func083(InData_Image); + + WR1_PROG(REG_1824H, 0x9c000005U); + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1608H, 0x8184001fU); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x34d0cf7cU), + bswap_32big(0xa8cff4e4U), + bswap_32big(0x82ae773bU), + bswap_32big(0x3893daa4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x651d6ce0U), bswap_32big(0xeb3ef632U), + bswap_32big(0x6ff722e0U), bswap_32big(0xfb5aa02bU)); + WR1_PROG(REG_14BCH, 0x00000020U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xdb69aebfU), bswap_32big(0x07da4621U), + bswap_32big(0x6540a723U), bswap_32big(0xe2d99dddU)); + + WR1_PROG(REG_1408H, 0x00004022U); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MAC[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1B08H, 0x00000216U); + + r_rsip_func102(bswap_32big(0x0a5197c9U), bswap_32big(0xa558050dU), + bswap_32big(0x79626149U), bswap_32big(0x69be5213U)); + WR1_PROG(REG_149CH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0e.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0e.c new file mode 100644 index 0000000000..b4e66af02b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p0e.c @@ -0,0 +1,52 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p0e (void) +{ + if (RD1_MASK(REG_149CH, 0x00000017U) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x000e0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + r_rsip_func100(bswap_32big(0x3f546405U), + bswap_32big(0x64da2a5aU), + bswap_32big(0xfa00eed4U), + bswap_32big(0xdf669c15U)); + WR1_PROG(REG_1438H, 0x400000c0U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x000000a8U); + + WR1_PROG(REG_1608H, 0x8181001fU); + WR1_PROG(REG_1400H, 0x02090005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1B08H, 0x00000202U); + + r_rsip_func102(bswap_32big(0xbd061a08U), + bswap_32big(0xa06898b4U), + bswap_32big(0x52c08ccbU), + bswap_32big(0x2a4d4c67U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p11.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p11.c new file mode 100644 index 0000000000..03fb7919b9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p11.c @@ -0,0 +1,614 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p11 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00110001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0xb103b486U), + bswap_32big(0x83ed4464U), + bswap_32big(0x6344798cU), + bswap_32big(0xeecedabbU)); + r_rsip_func086(InData_DomainParam); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001101U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x42fc2300U), + bswap_32big(0x8a8dfa7eU), + bswap_32big(0x2671a38bU), + bswap_32big(0xd7b72925U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001102U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x24d983c0U), + bswap_32big(0xcdf28ca5U), + bswap_32big(0x1300bc10U), + bswap_32big(0x3f36b533U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001103U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x15ea59efU), + bswap_32big(0x53c69a43U), + bswap_32big(0x344ea90eU), + bswap_32big(0x0ae5614fU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001104U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x52f46d82U), + bswap_32big(0x57636582U), + bswap_32big(0x31cc6848U), + bswap_32big(0x75e8451aU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001105U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xde428e4dU), + bswap_32big(0x43b44a95U), + bswap_32big(0xdf56afd9U), + bswap_32big(0x3060bfeaU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000003e0U); + WR1_PROG(REG_1020H, 0x00000160U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13e80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xc101ac12U), + bswap_32big(0x69b6c30aU), + bswap_32big(0x27c865f4U), + bswap_32big(0xf6e95160U)); + r_rsip_func087(InData_DomainParam); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000011U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1bd661f0U), + bswap_32big(0x8c2ea8ebU), + bswap_32big(0x9ef92135U), + bswap_32big(0xf793329cU)); + r_rsip_func091(); + + r_rsip_func100(bswap_32big(0xcb316579U), + bswap_32big(0x8e24b11eU), + bswap_32big(0xc7cdb982U), + bswap_32big(0xd52b2c15U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8a0e868aU), bswap_32big(0x1d90cae9U), bswap_32big(0xf07330ddU), + bswap_32big(0x2424ba66U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x962887e7U), bswap_32big(0xedcfd914U), bswap_32big(0x4c0fa660U), + bswap_32big(0x9e04e476U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x5831f58eU), bswap_32big(0xe2da9811U), bswap_32big(0x50965d66U), + bswap_32big(0xc8d85f47U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x92e20826U), bswap_32big(0xc3e144edU), bswap_32big(0xad7f1485U), + bswap_32big(0x52a08b6fU)); + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11100000U); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MsgDgst[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000011U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc8721aa1U), bswap_32big(0x7cb308ceU), bswap_32big(0xa75121a2U), + bswap_32big(0x20685becU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000025U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000011U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd7699770U), bswap_32big(0x38505c18U), bswap_32big(0x469b0415U), + bswap_32big(0xc32bb772U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000013c2U); + WR1_PROG(REG_1A2CH, 0x40000400U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x11b00000U); + + for (iLoop = 0U; iLoop < 20; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x6313fcadU), bswap_32big(0x361a2ec1U), bswap_32big(0x41eb99eeU), + bswap_32big(0xc65d7adbU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x62673a05U), + bswap_32big(0x359b65a2U), + bswap_32big(0xef997146U), + bswap_32big(0x5c9a3cadU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xf770b793U), + bswap_32big(0x31fb5339U), + bswap_32big(0x7f5d8d88U), + bswap_32big(0xee20a21fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x1497597cU), + bswap_32big(0xd6b9bef5U), + bswap_32big(0x2f9fed19U), + bswap_32big(0xdf871c5dU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xf9fdfb4dU), + bswap_32big(0xcd33b420U), + bswap_32big(0x5b336872U), + bswap_32big(0x81db458aU)); + WR1_PROG(REG_1404H, 0x12500000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[8]); + + r_rsip_func100(bswap_32big(0x119159c1U), + bswap_32big(0xe83d5cadU), + bswap_32big(0x6e55ccb7U), + bswap_32big(0xdd621891U)); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[12]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[16]); + + r_rsip_func100(bswap_32big(0x91db8be3U), + bswap_32big(0x71d53c35U), + bswap_32big(0xc2397199U), + bswap_32big(0x31f93c1bU)); + WR1_PROG(REG_1404H, 0x11b00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[20]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[24]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[28]); + + r_rsip_func100(bswap_32big(0x97a391d0U), + bswap_32big(0x15d994f3U), + bswap_32big(0x749950c5U), + bswap_32big(0x5a7f0a52U)); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[32]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[36]); + + r_rsip_func102(bswap_32big(0xd8e1d01eU), + bswap_32big(0x8ccd7af7U), + bswap_32big(0xa1fae8e2U), + bswap_32big(0x1d29b55eU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p12.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p12.c new file mode 100644 index 0000000000..7308556afe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p12.c @@ -0,0 +1,802 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" +#include "r_rsip_sub_func.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p12 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00120001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000012U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe4e6f231U), + bswap_32big(0x94c64e63U), + bswap_32big(0x7c2c5fcfU), + bswap_32big(0x7d4f0af8U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000012U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd0b6038fU), + bswap_32big(0xb27eeb53U), + bswap_32big(0x2077b27eU), + bswap_32big(0x361d9115U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x40000900U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80a80001U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + r_rsip_func_sub002(0x03420031U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + r_rsip_func_sub002(0x03420021U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[21]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[25]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[29]); + r_rsip_func_sub002(0x03420031U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[33]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[37]); + r_rsip_func_sub002(0x03420021U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[41]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + r_rsip_func_sub002(0x00820011U); + + r_rsip_func100(bswap_32big(0x1abeb8e6U), + bswap_32big(0xfd779813U), + bswap_32big(0x97c75e33U), + bswap_32big(0x4a4f39c8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x5171e3e2U), bswap_32big(0xa5776a6bU), bswap_32big(0x72687beeU), + bswap_32big(0xbb81f80bU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000fc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8090001fU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000012U)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0x7d7553e9U), bswap_32big(0x3bfdbf71U), bswap_32big(0x4b17eeb1U), + bswap_32big(0x1cf147f6U)); + r_rsip_func086(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x18e00000U); + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x00000900U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + r_rsip_func_sub002(0x00c20031U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + r_rsip_func_sub002(0x00c20021U); + + WR1_PROG(REG_1404H, 0x19300000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[24]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[28]); + r_rsip_func_sub002(0x00c20031U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[32]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[36]); + r_rsip_func_sub002(0x00c20021U); + + WR1_PROG(REG_1404H, 0x11b80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c00045U); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000000c0U, 0x00000200U, 0x00000160U, 0x0909000aU); + + r_rsip_func_sub001(0x00000160U, 0x00000930U, 0x000001b0U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000930U, 0x00000200U, 0x000001b0U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000160U, 0x00000980U, 0x000001b0U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000980U, 0x00000200U, 0x000001b0U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x59cc1cccU), bswap_32big(0xee735e5bU), bswap_32big(0x5b29c997U), + bswap_32big(0x95f91d04U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x84ddcda9U), bswap_32big(0x0cd1d327U), bswap_32big(0x70f044eeU), + bswap_32big(0x8f8b0aecU)); + } + else + { + r_rsip_func100(bswap_32big(0x4ebcf058U), bswap_32big(0x0cd163e8U), bswap_32big(0x56fe6533U), + bswap_32big(0x801c7524U)); + + r_rsip_func_sub001(0x00000160U, 0x00000200U, 0x000001b0U, 0x0909000aU); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + r_rsip_func_sub003(0x000000c0U, 0x00000160U, 0x09090002U); + + WR1_PROG(REG_1404H, 0x10c00000U); + r_rsip_func_sub002(0x00c00011U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8190001fU); + r_rsip_func_sub002(0x00c90041U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x000000c0U, 0x00000480U, 0x09090002U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x000000c0U, 0x00000340U, 0x09090002U); + + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11180000U); + r_rsip_func_sub002(0x00c00049U); + + WR1_PROG(REG_1404H, 0x19800000U); + r_rsip_func_sub002(0x00c002d1U); + + WR1_PROG(REG_1014H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a70U, 0x09090004U); + + r_rsip_func_sub001(0x00000890U, 0x00000160U, 0x000002a0U, 0x09090009U); + + r_rsip_func_sub001(0x00000070U, 0x00000160U, 0x000002f0U, 0x09090009U); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1608H, 0x81940001U); + r_rsip_func_sub002(0x00c90051U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x000009d0U, 0x09090002U); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000050U); + WR1_PROG(REG_1608H, 0x8194001fU); + r_rsip_func_sub002(0x00c90051U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a20U, 0x09090002U); + + r_rsip_func100(bswap_32big(0x7b3ee435U), bswap_32big(0x55c880dfU), bswap_32big(0x0f1dc185U), + bswap_32big(0x1405fd8aU)); + r_rsip_func087(InData_DomainParam); + + r_rsip_func_sub001(0x000001b0U, 0x00000160U, 0x00000ac0U, 0x09090009U); + + r_rsip_func_sub001(0x00000200U, 0x00000160U, 0x00000b10U, 0x09090009U); + + r_rsip_func_sub001(0x00000a70U, 0x00000160U, 0x00000b60U, 0x09090009U); + + r_rsip_func_sub001(0x00000ac0U, 0x000009d0U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x000009d0U, 0x00000ac0U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000b10U, 0x00000a20U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000a20U, 0x00000b10U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x3ceaf008U), bswap_32big(0xa9e8b676U), bswap_32big(0x0ba171c1U), + bswap_32big(0x0942acfdU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000a70U); + r_rsip_func_sub003(0x00000070U, 0x00000c50U, 0x09090013U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xab6fc217U), + bswap_32big(0x3b5bbeebU), + bswap_32big(0x0f8f2cc4U), + bswap_32big(0xc0e8e2acU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000b60U); + r_rsip_func_sub003(0x000002f0U, 0x00000c50U, 0x09090014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x322ab825U), + bswap_32big(0xa7480ae3U), + bswap_32big(0x0e2e0c65U), + bswap_32big(0x4e51f04eU)); + } + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1404H, 0x14380000U); + WR1_PROG(REG_1608H, 0x80920001U); + r_rsip_func_sub002(0x03430049U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1404H, 0x12f80000U); + WR1_PROG(REG_1608H, 0x80920001U); + r_rsip_func_sub002(0x03430049U); + + WR1_PROG(REG_1404H, 0x11600000U); + r_rsip_func_sub002(0x00c000f1U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000034a1U); + + WR1_PROG(REG_1600H, 0x00026ca5U); + + WR1_PROG(REG_1600H, 0x00003865U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x00003885U); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x01816ca3U); + WR1_PROG(REG_1600H, 0x01816ca4U); + WR1_PROG(REG_1600H, 0x00016c63U); + WR1_PROG(REG_1600H, 0x00016c84U); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c00045U); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000001b0U, 0x00000160U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000250U, 0x00000160U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x05c86752U), + bswap_32big(0xf3b94837U), + bswap_32big(0x20890582U), + bswap_32big(0x452d3f20U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x000002f0U, 0x00000250U, 0x09090014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xe4e6a977U), + bswap_32big(0x35784319U), + bswap_32big(0xbd76059fU), + bswap_32big(0x0320b22fU)); + } + else + { + r_rsip_func101(bswap_32big(0xb620a53aU), + bswap_32big(0xb2b89a42U), + bswap_32big(0xf93cc3c5U), + bswap_32big(0x29489552U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xc1678e6dU), + bswap_32big(0x260e24e3U), + bswap_32big(0xd8aef2dfU), + bswap_32big(0xdf404a02U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x08ff7922U), + bswap_32big(0x39b9d7e2U), + bswap_32big(0x8d291d06U), + bswap_32big(0x8bb98510U)); + + WR1_PROG(REG_1404H, 0x11180000U); + r_rsip_func_sub002(0x00c00049U); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func_sub001(0x000009d0U, 0x00000160U, 0x000003e0U, 0x09090009U); + + r_rsip_func_sub001(0x00000a20U, 0x00000160U, 0x00000430U, 0x09090009U); + + r_rsip_func_sub001(0x00000a70U, 0x00000160U, 0x00000480U, 0x09090009U); + + r_rsip_func101(bswap_32big(0x220bbd69U), + bswap_32big(0xe1061fbbU), + bswap_32big(0x78272fa5U), + bswap_32big(0x8acafd4aU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func_sub001(0x00000ac0U, 0x00000160U, 0x000003e0U, 0x09090009U); + + r_rsip_func_sub001(0x00000b10U, 0x00000160U, 0x00000430U, 0x09090009U); + + r_rsip_func_sub001(0x00000b60U, 0x00000160U, 0x00000480U, 0x09090009U); + + r_rsip_func101(bswap_32big(0x94e021a6U), + bswap_32big(0x3f69a9eaU), + bswap_32big(0x98458254U), + bswap_32big(0x9d5500e9U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func_sub001(0x00000bb0U, 0x00000160U, 0x000003e0U, 0x09090009U); + + r_rsip_func_sub001(0x00000c00U, 0x00000160U, 0x00000430U, 0x09090009U); + + r_rsip_func_sub001(0x00000c50U, 0x00000160U, 0x00000480U, 0x09090009U); + + r_rsip_func101(bswap_32big(0x5388c928U), + bswap_32big(0x470d4f32U), + bswap_32big(0x455a67c5U), + bswap_32big(0xd873818fU)); + } + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c00045U); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000001b0U, 0x00000160U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000250U, 0x00000160U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0xe6e64432U), + bswap_32big(0xaeb5b8b6U), + bswap_32big(0x0ce3b61eU), + bswap_32big(0x3f6b7f24U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func_sub001(0x000003e0U, 0x00000160U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000480U, 0x00000160U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x9e90facdU), + bswap_32big(0xe7c503d6U), + bswap_32big(0x9dd18390U), + bswap_32big(0x70d19cadU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func_sub001(0x000001b0U, 0x000003e0U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x000003e0U, 0x000001b0U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000200U, 0x00000430U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000430U, 0x00000200U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000250U, 0x00000480U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000480U, 0x00000250U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xf0289b69U), bswap_32big(0x57318414U), + bswap_32big(0xb170ae0bU), bswap_32big(0xdf2ef331U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + r_rsip_func_sub003(0x00000070U, 0x00000250U, 0x09090013U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x3411a5e4U), bswap_32big(0x4a6d4f01U), + bswap_32big(0x0b14a29cU), bswap_32big(0x080456e1U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x000002f0U, 0x00000250U, 0x09090014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xdde60c76U), bswap_32big(0xf2017836U), + bswap_32big(0x011a6ed8U), bswap_32big(0x7447746eU)); + } + } + else + { + r_rsip_func101(bswap_32big(0x1c003eb7U), bswap_32big(0x21ff4999U), + bswap_32big(0xbbe3f19aU), bswap_32big(0x56a52d85U)); + } + } + else + { + WR1_PROG(REG_1404H, 0x11180000U); + r_rsip_func_sub002(0x00c00049U); + + r_rsip_func_sub001(0x000003e0U, 0x00000160U, 0x000001b0U, 0x09090009U); + + r_rsip_func_sub001(0x00000430U, 0x00000160U, 0x00000200U, 0x09090009U); + + r_rsip_func_sub001(0x00000480U, 0x00000160U, 0x00000250U, 0x09090009U); + + r_rsip_func101(bswap_32big(0x5974953dU), + bswap_32big(0x0451234dU), + bswap_32big(0x8c13ab0fU), + bswap_32big(0x2e39e063U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x4f712ed6U), + bswap_32big(0x2e299e13U), + bswap_32big(0xfecaf5b9U), + bswap_32big(0x831785c2U)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + r_rsip_func101(bswap_32big(0xb7673bffU), + bswap_32big(0xf57300acU), + bswap_32big(0xcd18562aU), + bswap_32big(0x9d6455d2U)); + } + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002c20U); + + r_rsip_func101(bswap_32big(0x14b0be08U), + bswap_32big(0xe1a8a3feU), + bswap_32big(0xbcfb5bf2U), + bswap_32big(0x94a19ef2U)); + } + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0x00000012U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12580000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c00045U); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000250U, 0x000002a0U, 0x000002f0U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x433743e9U), bswap_32big(0x86be0732U), bswap_32big(0x02ccdc65U), + bswap_32big(0x0a3986a4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x75ad8378U), + bswap_32big(0x788f0be7U), + bswap_32big(0x596a5c5fU), + bswap_32big(0xd6ef8398U)); + } + else + { + r_rsip_func100(bswap_32big(0x1e956984U), + bswap_32big(0x0f59ae25U), + bswap_32big(0xabe5ea18U), + bswap_32big(0xb823b68dU)); + + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x00000070U, 0x000002a0U, 0x09090004U); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + r_rsip_func_sub002(0x00c00045U); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000070U, 0x00000160U, 0x00000110U, 0x0909000aU); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x00000070U, 0x000002a0U, 0x09090002U); + + r_rsip_func_sub001(0x000002a0U, 0x00000930U, 0x000001b0U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000930U, 0x000002a0U, 0x000001b0U, 0x0909000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x2ae41089U), + bswap_32big(0x97da58c1U), + bswap_32big(0x457b097aU), + bswap_32big(0xef2b8cb5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xdc972363U), + bswap_32big(0xc30a36d0U), + bswap_32big(0xa11998b0U), + bswap_32big(0x3656289aU)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x797935bbU); + + r_rsip_func101(bswap_32big(0xfd99d8f4U), + bswap_32big(0x82ec05c6U), + bswap_32big(0xf5c27e69U), + bswap_32big(0x797c3cfdU)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xf1ebfcbdU), bswap_32big(0x6290c228U), bswap_32big(0xe1c40b54U), + bswap_32big(0x2085c6cdU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x5c5ef3b1U), bswap_32big(0x6d324abeU), bswap_32big(0xbf1df9f2U), + bswap_32big(0x8ac0b838U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x9dd89bb0U), bswap_32big(0x49925296U), bswap_32big(0x9f276718U), + bswap_32big(0x35eabe42U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p13.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p13.c new file mode 100644 index 0000000000..91f6214524 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p13.c @@ -0,0 +1,711 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p13 (const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00130001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0xb6ac2fc2U), + bswap_32big(0x821a6020U), + bswap_32big(0x62c94bcaU), + bswap_32big(0x94794e29U)); + r_rsip_func086(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12a00000U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001301U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x35838fe1U), + bswap_32big(0x103cef5eU), + bswap_32big(0x7375246bU), + bswap_32big(0x60ece265U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80020000U); + WR1_PROG(REG_1400H, 0x03420009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00008c20U); + WR1_PROG(REG_1600H, 0x000001ffU); + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1400H, 0x00c90009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001302U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x41fe8407U), + bswap_32big(0xa459806eU), + bswap_32big(0x48dbc8e8U), + bswap_32big(0xb91bc9daU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001303U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x995b2ec8U), + bswap_32big(0x118783e6U), + bswap_32big(0xb05c8347U), + bswap_32big(0xb29aee6fU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001304U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x841181daU), + bswap_32big(0x2c2a5c53U), + bswap_32big(0x14653399U), + bswap_32big(0xfeca4ad2U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001305U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x14baa3d6U), + bswap_32big(0x38dcf89eU), + bswap_32big(0x938d41b4U), + bswap_32big(0x66ac5ae6U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xabf54acfU), + bswap_32big(0x46abdd67U), + bswap_32big(0x0f372209U), + bswap_32big(0x07ab1c62U)); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1404H, 0x12000000U); + WR1_PROG(REG_1608H, 0x80940001U); + WR1_PROG(REG_1400H, 0x03430051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 20; iLoop++) + { + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1600H, 0x20000842U); + WR1_PROG(REG_1600H, 0x10003841U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3800585eU); + WR1_PROG(REG_1600H, 0x20003460U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1600H, 0x100033c0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x14300000U); + WR1_PROG(REG_1400H, 0x00c00051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0a0a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0004dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003403U); + + WR1_PROG(REG_1600H, 0x00003060U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0a0a0007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0a0a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00003060U); + + r_rsip_func101(bswap_32big(0xd635d65cU), bswap_32big(0x67532c5eU), bswap_32big(0x3b7bd1b9U), + bswap_32big(0xdaf75c54U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1400H, 0x00c00051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x3eea1a57U), + bswap_32big(0xfe2ed5e6U), + bswap_32big(0x03ef4f3aU), + bswap_32big(0x765e56f6U)); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0a0a000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0xfe09dc90U), bswap_32big(0x0d330977U), bswap_32big(0x9a652222U), + bswap_32big(0x5bd1dacfU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0a0a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x2651107fU), bswap_32big(0x9538ee48U), bswap_32big(0xb8d0f034U), + bswap_32big(0xa86f7909U)); + } + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0a0a000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0a0a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1600H, 0x00003000U); + + r_rsip_func101(bswap_32big(0x29a50128U), bswap_32big(0xf92aa3daU), bswap_32big(0xaca38e16U), + bswap_32big(0x0370bef8U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x54979f37U), + bswap_32big(0x59294fc2U), + bswap_32big(0x17426697U), + bswap_32big(0xefff9c9bU)); + + r_rsip_func087(InData_DomainParam); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000013U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x08482350U), + bswap_32big(0x8d75130aU), + bswap_32big(0xebca15b4U), + bswap_32big(0xd0977999U)); + r_rsip_func091(); + + r_rsip_func100(bswap_32big(0x3efec19eU), + bswap_32big(0x738bd53cU), + bswap_32big(0xb6a78e5eU), + bswap_32big(0xeadd4494U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8d8dfec1U), bswap_32big(0x1a915238U), bswap_32big(0x5d452ea3U), + bswap_32big(0xfbcacb5cU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001306U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcc7c27bbU), bswap_32big(0xb67aaef3U), bswap_32big(0xcc9ea67aU), + bswap_32big(0x1b725192U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000013U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdaa8deeeU), bswap_32big(0xead064cfU), bswap_32big(0x376e15d4U), + bswap_32big(0x1844d095U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000025U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000013U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9873b624U), bswap_32big(0x24e56d0aU), bswap_32big(0x1b00b720U), + bswap_32big(0x87ad72adU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x1820a720U), bswap_32big(0x7d084caeU), bswap_32big(0x4d2bf6b9U), + bswap_32big(0x4e126983U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x12f80000U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00830029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x6152a981U), bswap_32big(0x95a8146bU), bswap_32big(0xecfa4a95U), + bswap_32big(0x4d14cbcfU)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7008d07U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 5]); + + r_rsip_func100(bswap_32big(0x52a7bd0aU), bswap_32big(0x2be5b62bU), bswap_32big(0x7f821862U), + bswap_32big(0x4e23fd78U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 9]); + + r_rsip_func100(bswap_32big(0x03e61202U), bswap_32big(0x0e47778fU), bswap_32big(0xc76af654U), + bswap_32big(0xf4e0d488U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001307U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc265a524U), bswap_32big(0xdceed181U), bswap_32big(0xf1fca866U), + bswap_32big(0x92a0ab4eU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000113U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa8515017U), bswap_32big(0x594e2992U), bswap_32big(0xd0b04b99U), + bswap_32big(0x3489de20U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000113U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcb172c2fU), bswap_32big(0x21e50dddU), bswap_32big(0xc9948a94U), + bswap_32big(0xc3dfba9aU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xc68a5edfU), bswap_32big(0x759be082U), bswap_32big(0x26cd6a97U), + bswap_32big(0x047cf198U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1404H, 0x12580000U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00830029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x0a82ed80U), bswap_32big(0x88455583U), bswap_32big(0x2d3d92a0U), + bswap_32big(0x3642aa28U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x12a80000U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00830009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 12; iLoop < 24U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x9aaf09beU), bswap_32big(0x6238ebbeU), bswap_32big(0x0d008d72U), + bswap_32big(0x34bed910U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 24; iLoop < 36; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x39ee005fU), bswap_32big(0x627a4c10U), bswap_32big(0x51524826U), + bswap_32big(0xffdedcc6U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + + r_rsip_func100(bswap_32big(0xc9564f47U), bswap_32big(0xdc24f36fU), bswap_32big(0x90007a7fU), + bswap_32big(0xff0e895fU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 5]); + + r_rsip_func100(bswap_32big(0x824d504aU), bswap_32big(0x092c0620U), bswap_32big(0xbd3afb05U), + bswap_32big(0x9645ca6dU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + r_rsip_func102(bswap_32big(0x8f74ea7dU), bswap_32big(0xbf758be2U), bswap_32big(0x3829a63cU), + bswap_32big(0x3eea288dU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p15.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p15.c new file mode 100644 index 0000000000..c323b275c1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p15.c @@ -0,0 +1,166 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p15 (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00150001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8659d07eU), + bswap_32big(0x92b87690U), + bswap_32big(0xed77f7efU), + bswap_32big(0xb3a1fe61U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000015U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x92c80c6cU), + bswap_32big(0x0edc24d9U), + bswap_32big(0xdb8b5e34U), + bswap_32big(0x90d97832U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000015U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7e207f82U), + bswap_32big(0x45359812U), + bswap_32big(0xf45bf106U), + bswap_32big(0x6598f771U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x57eb27d5U), + bswap_32big(0x50413466U), + bswap_32big(0x7c06927aU), + bswap_32big(0xd4e6c891U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xabe56aa8U), + bswap_32big(0xaa66f03fU), + bswap_32big(0xa16caba6U), + bswap_32big(0x6d8b950cU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001503U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1c52b274U), + bswap_32big(0x5f247437U), + bswap_32big(0x3ab9ef3fU), + bswap_32big(0xf5242788U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x5ef994b2U), + bswap_32big(0xf734a9f8U), + bswap_32big(0x60ce0433U), + bswap_32big(0xd670760dU)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81060000U); + WR1_PROG(REG_1400H, 0x00890019U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000002U)); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + r_rsip_func102(bswap_32big(0x19e03380U), + bswap_32big(0x6b5c6406U), + bswap_32big(0x3b9b013aU), + bswap_32big(0xcd3b6df7U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p16.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p16.c new file mode 100644 index 0000000000..0e0109cc89 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p16.c @@ -0,0 +1,191 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p16 (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00160001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001601U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xccec78feU), + bswap_32big(0x71a49ea2U), + bswap_32big(0xe7f02cc8U), + bswap_32big(0x7425ffbaU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010080U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e4U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000016U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x664653eeU), + bswap_32big(0x7d099655U), + bswap_32big(0xfb8881f8U), + bswap_32big(0xe684e8b0U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000016U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa4b38418U), + bswap_32big(0xc019998cU), + bswap_32big(0xe88e49d4U), + bswap_32big(0x17b28f5eU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001602U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdc413898U), + bswap_32big(0xa3d9b7b8U), + bswap_32big(0x166aec8aU), + bswap_32big(0x5a944b33U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001603U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe1565636U), + bswap_32big(0x67d25116U), + bswap_32big(0xd47a0e94U), + bswap_32big(0xc3aeeda3U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x1ae211e9U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x3fb09c52U), + bswap_32big(0xf4ad40f7U), + bswap_32big(0x2031c436U), + bswap_32big(0x42e2665cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd93fb26bU), bswap_32big(0x02d104f7U), bswap_32big(0x2245df9cU), + bswap_32big(0xc6545e89U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x8d19f931U), bswap_32big(0x5fc78a7eU), bswap_32big(0x5879765dU), + bswap_32big(0x39d3f0ceU)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8188001fU); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000002U)); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + r_rsip_func100(bswap_32big(0xc010a668U), bswap_32big(0x48133b28U), bswap_32big(0x602a9f2cU), + bswap_32big(0xb18eda2fU)); + WR1_PROG(REG_1608H, 0x81010080U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func102(bswap_32big(0x7a131d71U), bswap_32big(0x792b5edbU), bswap_32big(0x672c8d6dU), + bswap_32big(0x27b12dcaU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p17.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p17.c new file mode 100644 index 0000000000..2b149682cd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p17.c @@ -0,0 +1,273 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p17 (uint32_t OutData_KeyIndex[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00170001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001701U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcf8c8a27U), + bswap_32big(0x28848b77U), + bswap_32big(0xadf202d8U), + bswap_32big(0x647626fbU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010080U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e4U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000017U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x21f862e7U), + bswap_32big(0x481f83e3U), + bswap_32big(0xc30db4b5U), + bswap_32big(0x8bad2b97U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000009U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000017U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe1d69d56U), + bswap_32big(0x1be35341U), + bswap_32big(0x59973756U), + bswap_32big(0x10541ca2U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001702U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb83cd1a8U), + bswap_32big(0x027febf0U), + bswap_32big(0xefaf15e6U), + bswap_32big(0xa33f968cU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001703U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8dfb4c22U), + bswap_32big(0xa1339bacU), + bswap_32big(0x2349adfeU), + bswap_32big(0x1e5e62c5U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001704U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x764130fbU), + bswap_32big(0xa1caf8b7U), + bswap_32big(0x7397dbdaU), + bswap_32big(0xbb44fe42U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001705U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe985771dU), + bswap_32big(0x7cc1f0c6U), + bswap_32big(0xcf1501fbU), + bswap_32big(0x9abfeca5U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xc58be4e5U), + bswap_32big(0x3665fd3fU), + bswap_32big(0x0812489bU), + bswap_32big(0xc511c547U)); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000020U); + + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x000037dfU); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000030U); + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x000013feU); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x1ae211e9U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xf9dedee6U), + bswap_32big(0x2932b2f1U), + bswap_32big(0xf21e5c1dU), + bswap_32big(0xce6c4f7fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x4240baecU), bswap_32big(0xf3433138U), bswap_32big(0x6ed8e4c8U), + bswap_32big(0x8038d4c1U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x32f7427eU), bswap_32big(0x512efebeU), bswap_32big(0x16d76bdfU), + bswap_32big(0xad0cd42bU)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x818c001fU); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x6d703f7cU), bswap_32big(0x0f3ffcd8U), bswap_32big(0xf687ee03U), + bswap_32big(0x7fdef46cU)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d47U); + WR1_PROG(REG_1608H, 0x81040180U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[iLoop + 1]); + + r_rsip_func100(bswap_32big(0x14f3700dU), bswap_32big(0xcd0a474eU), bswap_32big(0x800d10eeU), + bswap_32big(0xe60fdf20U)); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000004U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[iLoop + 5]); + + r_rsip_func100(bswap_32big(0x4d0a6be0U), bswap_32big(0x4687b6ebU), bswap_32big(0xea50581cU), + bswap_32big(0xebd9602eU)); + WR1_PROG(REG_1608H, 0x81010080U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func102(bswap_32big(0xe1ad7e5dU), bswap_32big(0xecd79ba3U), bswap_32big(0x74e142bcU), + bswap_32big(0x38c93b59U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p18.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p18.c new file mode 100644 index 0000000000..d744c648cc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p18.c @@ -0,0 +1,1036 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p18 (const uint32_t InData_PrivKeyIndex[], + const uint32_t InData_PubKeyIndex[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[], + uint64_t MAX_CNT) +{ + uint64_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00180001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000008c8U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PrivKeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000018U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x94f522baU), + bswap_32big(0x0eea8e03U), + bswap_32big(0x4595497aU), + bswap_32big(0x5cc50199U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000027U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000018U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x33f4fda5U), + bswap_32big(0x0368fe5eU), + bswap_32big(0x8879fbf7U), + bswap_32big(0x10a0d100U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 8U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PrivKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1608H, 0x80880000U); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PrivKeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x7bb45a99U), + bswap_32big(0x4ccccec5U), + bswap_32big(0x8ffa3a9aU), + bswap_32big(0x4eda35fcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x36aa8486U), bswap_32big(0x7b06a90eU), bswap_32big(0x1d6624ecU), + bswap_32big(0xdd6da797U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000118U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x55ebe36dU), bswap_32big(0x4018b866U), bswap_32big(0x7d3035d5U), + bswap_32big(0xd9016dd0U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000026U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000118U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5ac59946U), bswap_32big(0x12bad022U), bswap_32big(0x377b00deU), + bswap_32big(0xfa177bf3U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + for (iLoop = 0U; iLoop < 8U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x554f1971U), bswap_32big(0x7e628bbdU), bswap_32big(0x2669b605U), + bswap_32big(0xb23c74cfU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xf0563577U), bswap_32big(0x04be4d92U), bswap_32big(0xe8b24446U), + bswap_32big(0x7f2633ccU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020000U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_MsgLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x30008800U); + WR1_PROG(REG_1600H, 0xffffffffU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x3000a820U); + WR1_PROG(REG_1600H, 0xfffffdffU); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xcfb57323U), bswap_32big(0xb367d1cdU), bswap_32big(0x162ed74fU), + bswap_32big(0x10adf402U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x3548e285U), + bswap_32big(0x04f27027U), + bswap_32big(0x194fe286U), + bswap_32big(0x6ae1e54eU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xc19f4c21U), + bswap_32big(0xaab90c0eU), + bswap_32big(0xdc09dc9eU), + bswap_32big(0x08c9bc19U)); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0c00a420U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1600H, 0x00802402U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1408H, 0x0000500aU); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + + r_rsip_func100(bswap_32big(0x5e5c29f8U), + bswap_32big(0xe938cb33U), + bswap_32big(0x84df03d6U), + bswap_32big(0xec2d6d15U)); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0c00a420U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1600H, 0x00802402U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1408H, 0x0000500aU); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 2]); + S_RAM[0 + 2] = bswap_32big(S_RAM[0 + 2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 3]); + S_RAM[0 + 3] = bswap_32big(S_RAM[0 + 3]); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000100U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x8188001eU); + WR1_PROG(REG_1400H, 0x01490021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1400H, 0x03450041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003841U); + WR1_PROG(REG_1600H, 0x00008c40U); + WR1_PROG(REG_1600H, 0xf8ffffffU); + WR1_PROG(REG_1600H, 0x00003c41U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000001cU); + WR1_PROG(REG_1600H, 0x00003841U); + + WR1_PROG(REG_1600H, 0x00008c40U); + WR1_PROG(REG_1600H, 0xffffff3fU); + + WR1_PROG(REG_1600H, 0x00009040U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1600H, 0x00003c41U); + + WR1_PROG(REG_1404H, 0x19600000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, S_RAM[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, S_RAM[0 + 1]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x01490021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffffffffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR8_ADDR(REG_1420H, &InData_Msg[iLoop]); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (MAX_CNT & 0xfffffffffffffff0U); iLoop < MAX_CNT; iLoop++) + { + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1400H, 0x03450041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000003fU); + + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1004H, 0x00000000U); + WR1_PROG(REG_1004H, 0x04040000U); + + r_rsip_func100(bswap_32big(0xc00166d4U), + bswap_32big(0x377facbaU), + bswap_32big(0x9d4b46a8U), + bswap_32big(0x73897090U)); + r_rsip_func401(InData_DomainParam); + + r_rsip_func100(bswap_32big(0xca31355fU), + bswap_32big(0xe31e3c3bU), + bswap_32big(0x77c985ccU), + bswap_32big(0xedb1fdfeU)); + r_rsip_func406(InData_DomainParam); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0EEC73D2U), + bswap_32big(0x17F5BE65U), + bswap_32big(0xCB5C63AAU), + bswap_32big(0x97A331B5U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0665E1DBU), + bswap_32big(0x6EABA043U), + bswap_32big(0xF98B4BAAU), + bswap_32big(0x9C78F954U)); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000010U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000009d0U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x15000000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1b400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1b900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1be00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19b00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8088001fU); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b660U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000100U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000018U)); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 256U; iLoop++) + { + r_rsip_func405(); + + r_rsip_func403(); + + r_rsip_func101(bswap_32big(0xf277a28bU), + bswap_32big(0x801c2c7fU), + bswap_32big(0x86b03079U), + bswap_32big(0x73c1961aU)); + r_rsip_func402(); + + r_rsip_func404(); + + WR1_PROG(REG_1600H, 0x00002d00U); + + r_rsip_func101(bswap_32big(0x9ae1bb93U), + bswap_32big(0x02131eedU), + bswap_32big(0x40407ec4U), + bswap_32big(0xcfeda0dcU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000006b0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000005c0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000610U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000610U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x037807b7U), + bswap_32big(0x36742391U), + bswap_32big(0x3960ff58U), + bswap_32big(0x2884a15aU)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000005c0U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003801U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x7fffffffU); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000003cU); + WR1_PROG(REG_1600H, 0x00003841U); + + WR1_PROG(REG_1600H, 0x001f6c42U); + WR1_PROG(REG_1600H, 0x00001002U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00003c01U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x1c300000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, S_RAM[0 + 2]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, S_RAM[0 + 3]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x01490021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1400H, 0x01430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffffffffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR16_ADDR(REG_1420H, &InData_Msg[iLoop]); + iLoop = iLoop + 16U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (MAX_CNT & 0xfffffffffffffff0U); iLoop < MAX_CNT; iLoop++) + { + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1400H, 0x03450041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000003fU); + + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81900001U); + + WR1_PROG(REG_1404H, 0x1a000000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1a500000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19600000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x19600000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0EEC73D2U), + bswap_32big(0x17F5BE65U), + bswap_32big(0xCB5C63AAU), + bswap_32big(0x97A331B5U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0665E1DBU), + bswap_32big(0x6EABA043U), + bswap_32big(0xF98B4BAAU), + bswap_32big(0x9C78F954U)); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000a20U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + WR1_PROG(REG_1010H, 0x00000010U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a70U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000430U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000390U); + WR1_PROG(REG_1010H, 0x00000010U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000009d0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func100(bswap_32big(0xacb6bdf2U), + bswap_32big(0x0c21cf38U), + bswap_32big(0x9d4d21b3U), + bswap_32big(0x121b1e56U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x1c300000U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + + r_rsip_func100(bswap_32big(0xd714cbb8U), + bswap_32big(0xb4c37a98U), + bswap_32big(0xea20def9U), + bswap_32big(0x7e46ecefU)); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1408H, 0x00005022U); + for (iLoop = 8; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Signature[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func102(bswap_32big(0x111f4c92U), + bswap_32big(0xb9d8b869U), + bswap_32big(0x17016699U), + bswap_32big(0x1c3a0990U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p19.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p19.c new file mode 100644 index 0000000000..670a7945b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p19.c @@ -0,0 +1,1473 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p19 (const uint32_t InData_KeyIndex[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[], + uint64_t MAX_CNT) +{ + uint64_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00190001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000008c8U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000019U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x001b32f4U), + bswap_32big(0x9fc51ec7U), + bswap_32big(0xd029cc80U), + bswap_32big(0x9b6cde81U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000026U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000019U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x55d624e3U), + bswap_32big(0x998d1936U), + bswap_32big(0x455d5e96U), + bswap_32big(0x8ecec968U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + for (iLoop = 0U; iLoop < 8U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xf2556ae3U), + bswap_32big(0x604d314dU), + bswap_32big(0xd9e9efecU), + bswap_32big(0xf4683450U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x52956e58U), bswap_32big(0x8090efbfU), bswap_32big(0x195701c3U), + bswap_32big(0x6eec9c70U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020000U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_MsgLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x30008800U); + WR1_PROG(REG_1600H, 0xffffffffU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x3000a820U); + WR1_PROG(REG_1600H, 0xfffffdffU); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xb9bbea0aU), bswap_32big(0x09e927b6U), bswap_32big(0x32b3f4d2U), + bswap_32big(0xd5cccf8fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd5bd341bU), bswap_32big(0xec484dc2U), bswap_32big(0xecc5a082U), + bswap_32big(0x7b17aa94U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1404H, 0x1c300000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x31890f62U), bswap_32big(0x2a971356U), bswap_32big(0x70a996cbU), + bswap_32big(0x4c52d809U)); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0c00a420U); + WR1_PROG(REG_1600H, 0x00000200U); + WR1_PROG(REG_1600H, 0x00802402U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1408H, 0x0000500aU); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, S_RAM[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, S_RAM[0 + 1]); + + WR1_PROG(REG_1404H, 0x1c300000U); + WR1_PROG(REG_1400H, 0x01430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1400H, 0x01430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffffffffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR16_ADDR(REG_1420H, &InData_Msg[iLoop]); + iLoop = iLoop + 16U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (MAX_CNT & 0xfffffffffffffff0U); iLoop < MAX_CNT; iLoop++) + { + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1400H, 0x03450041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000003fU); + + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81900001U); + + WR1_PROG(REG_1404H, 0x1a000000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1a500000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1004H, 0x00000000U); + WR1_PROG(REG_1004H, 0x04040000U); + + r_rsip_func100(bswap_32big(0x6b42fd6bU), bswap_32big(0x3449d7dcU), bswap_32big(0x50dd60e8U), + bswap_32big(0xbf8a8cecU)); + r_rsip_func406(InData_DomainParam); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0EEC73D2U), + bswap_32big(0x17F5BE65U), + bswap_32big(0xCB5C63AAU), + bswap_32big(0x97A331B5U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0665E1DBU), + bswap_32big(0x6EABA043U), + bswap_32big(0xF98B4BAAU), + bswap_32big(0x9C78F954U)); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000a20U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + WR1_PROG(REG_1010H, 0x00000010U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a70U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000009d0U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14300000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x00003440U); + WR1_PROG(REG_1600H, 0x00076800U); + WR1_PROG(REG_1600H, 0x000037e0U); + + WR1_PROG(REG_1600H, 0x00008c40U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1600H, 0x02003c41U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1608H, 0x81880000U); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000004d0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000004d0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000004d0U); + WR1_PROG(REG_1018H, 0x00000ac0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000390U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000340U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x1f89d167U), bswap_32big(0x0d317a0cU), bswap_32big(0x7810843aU), + bswap_32big(0x3ba8dc3bU)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000390U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0FFFFFFFU), + bswap_32big(0xFFFFFFFFU), + bswap_32big(0xFFFFFFFFU), + bswap_32big(0xFFFFFFFFU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0xFFFFFFFFU), + bswap_32big(0xFFFFFFFFU), + bswap_32big(0xFFFFFFFFU), + bswap_32big(0xFFFFFFFEU)); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x7c70b179U), bswap_32big(0x97c68724U), bswap_32big(0x4c3e1871U), + bswap_32big(0x9c461616U)); + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000ac0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000340U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14100000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x1edc2a2eU), bswap_32big(0x32ac9153U), bswap_32big(0x494bdf4dU), + bswap_32big(0xe86b6955U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000250U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x58d7f675U), + bswap_32big(0x969077d2U), + bswap_32big(0xe5de2d28U), + bswap_32big(0x986e9ea8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0xd4cfa273U); + + r_rsip_func101(bswap_32big(0x6c687933U), + bswap_32big(0x5ee2fa1aU), + bswap_32big(0x56161375U), + bswap_32big(0xdd82d05bU)); + } + else + { + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x2B832480U), + bswap_32big(0x4FC1DF0BU), + bswap_32big(0x2B4D0099U), + bswap_32big(0x3DFBD7A7U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x2F431806U), + bswap_32big(0xAD2FE478U), + bswap_32big(0xC4EE1B27U), + bswap_32big(0x4A0EA0B0U)); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000003e0U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xca9e321cU), + bswap_32big(0x1a0300daU), + bswap_32big(0x296652d1U), + bswap_32big(0x90e95f26U)); + } + + r_rsip_func101(bswap_32big(0x3f231481U), + bswap_32big(0xf7e00a43U), + bswap_32big(0x95a6f5dfU), + bswap_32big(0x050706d1U)); + } + else + { + r_rsip_func101(bswap_32big(0xe69b1d96U), + bswap_32big(0xd1b1cb00U), + bswap_32big(0x8c45f536U), + bswap_32big(0xebd571d9U)); + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0xd4cfa273U); + + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x5709d7afU), bswap_32big(0x10de8807U), bswap_32big(0xda6649f8U), + bswap_32big(0x52b49393U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x57170f45U), + bswap_32big(0x7492f626U), + bswap_32big(0x059e71bdU), + bswap_32big(0x6430cdbfU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x1b100000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x13c00000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x02003841U); + + WR1_PROG(REG_1600H, 0x00008c40U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x3800085fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x04f96973U), + bswap_32big(0x83047dbbU), + bswap_32big(0x0be2a2e1U), + bswap_32big(0x6bc4218dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000480U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x59ff83e6U), + bswap_32big(0x17ef5b9dU), + bswap_32big(0x0d474589U), + bswap_32big(0xde9739dcU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000480U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x2a7ee098U), + bswap_32big(0x9ad03f87U), + bswap_32big(0x376ae2bfU), + bswap_32big(0x9c6e6722U)); + } + + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1404H, 0x15000000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1b400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1b900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1be00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19b00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8088001fU); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b660U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000100U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000019U)); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 256U; iLoop++) + { + r_rsip_func405(); + + r_rsip_func403(); + + r_rsip_func101(bswap_32big(0x3bb4f2c7U), + bswap_32big(0x23226412U), + bswap_32big(0x6e28ca8fU), + bswap_32big(0xc137cf42U)); + r_rsip_func402(); + + r_rsip_func404(); + + WR1_PROG(REG_1600H, 0x00002d00U); + + r_rsip_func101(bswap_32big(0xfddab528U), + bswap_32big(0x6c368f90U), + bswap_32big(0x4e21ada5U), + bswap_32big(0x20d84629U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000ca0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000006b0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000cf0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000d40U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000007c7U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80880001U); + for (iLoop = 8; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Signature[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x19600000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0EEC73D2U), + bswap_32big(0x17F5BE65U), + bswap_32big(0xCB5C63AAU), + bswap_32big(0x97A331B5U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x0665E1DBU), + bswap_32big(0x6EABA043U), + bswap_32big(0xF98B4BAAU), + bswap_32big(0x9C78F954U)); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000010U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000980U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000008U); + + r_rsip_func100(bswap_32big(0x13529bdaU), + bswap_32big(0x3c2e69deU), + bswap_32big(0x3b0eb06fU), + bswap_32big(0x2b7717cbU)); + r_rsip_func401(InData_DomainParam); + + WR1_PROG(REG_1404H, 0x15000000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19600000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8088001fU); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b660U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000100U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000119U)); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 256U; iLoop++) + { + r_rsip_func405(); + + r_rsip_func403(); + + r_rsip_func101(bswap_32big(0x9cef4dc9U), + bswap_32big(0x7f44facbU), + bswap_32big(0xd2f07f98U), + bswap_32big(0xad11a491U)); + r_rsip_func402(); + + r_rsip_func404(); + + WR1_PROG(REG_1600H, 0x00002d00U); + + r_rsip_func101(bswap_32big(0x60e155d5U), + bswap_32big(0x5eb44f02U), + bswap_32big(0x7ffe0b1cU), + bswap_32big(0xa94f3bfcU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000750U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000006b0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000007a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000007f0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000ca0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000ca0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000ca0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000cf0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000005c0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000d40U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000610U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func404(); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000006b0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000005c0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000610U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000610U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040006U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x56edf6ccU), + bswap_32big(0xab944d61U), + bswap_32big(0xa448d41dU), + bswap_32big(0x99e63537U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000005c0U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003801U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x7fffffffU); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000003cU); + WR1_PROG(REG_1600H, 0x00003841U); + + WR1_PROG(REG_1600H, 0x001f6c42U); + WR1_PROG(REG_1600H, 0x00001002U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00003c01U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x14100000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000c50U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000c50U); + WR1_PROG(REG_1018H, 0x00000250U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x02bf6fcfU), + bswap_32big(0x99992eccU), + bswap_32big(0x99e8e91bU), + bswap_32big(0x56fa2ce1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x97247c18U), + bswap_32big(0xdead177fU), + bswap_32big(0x1aa0050bU), + bswap_32big(0x95597667U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0xac87ba00U), + bswap_32big(0x30ca0b6eU), + bswap_32big(0xa225e1bcU), + bswap_32big(0x37fd9dcfU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p1a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p1a.c new file mode 100644 index 0000000000..5be69ed242 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p1a.c @@ -0,0 +1,621 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p1a (const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x0001a001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000008c8U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd554bd5dU), + bswap_32big(0xc8ce8c28U), + bswap_32big(0x3f23c0f6U), + bswap_32big(0x21d5d25aU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000050U); + WR1_PROG(REG_1608H, 0x80840000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc591e0cdU), + bswap_32big(0xb821a25fU), + bswap_32big(0x7da1151cU), + bswap_32big(0xfd90c1bbU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1608H, 0x80840000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_2000H, 0x00000001U); + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000100U); + + WR1_PROG(REG_1608H, 0x81880000U); + WR1_PROG(REG_1400H, 0x01490021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1608H, 0x80880000U); + WR1_PROG(REG_1400H, 0x03450021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00050021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003820U); + WR1_PROG(REG_1600H, 0x00008c20U); + WR1_PROG(REG_1600H, 0xf8ffffffU); + WR1_PROG(REG_1600H, 0x00003c20U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x0000001cU); + + WR1_PROG(REG_1600H, 0x00003820U); + WR1_PROG(REG_1600H, 0x00008c20U); + WR1_PROG(REG_1600H, 0xffffff3fU); + WR1_PROG(REG_1600H, 0x00009020U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1600H, 0x00003c20U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1004H, 0x00000000U); + WR1_PROG(REG_1004H, 0x04040000U); + + r_rsip_func100(bswap_32big(0x7f914ae6U), + bswap_32big(0x5cb3110dU), + bswap_32big(0x6e09a0a2U), + bswap_32big(0xa0c9863eU)); + r_rsip_func401(InData_DomainParam); + + r_rsip_func100(bswap_32big(0x102c581fU), + bswap_32big(0x63de2631U), + bswap_32big(0x332030d7U), + bswap_32big(0x6e1d3e98U)); + r_rsip_func406(InData_DomainParam); + + WR1_PROG(REG_1404H, 0x15000000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x16e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1b400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1b900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x1be00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000026U)); + WR1_PROG(REG_1400H, 0x00c00015U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c2000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b660U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000100U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000001aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 256U; iLoop++) + { + r_rsip_func405(); + + r_rsip_func403(); + + r_rsip_func101(bswap_32big(0xec1b2ce2U), bswap_32big(0x09d227bfU), bswap_32big(0xd1ed09e3U), + bswap_32big(0x090c4fecU)); + r_rsip_func402(); + + r_rsip_func404(); + + WR1_PROG(REG_1600H, 0x00002d00U); + + r_rsip_func101(bswap_32big(0xe554e47eU), bswap_32big(0x3296aebcU), bswap_32big(0x412a548aU), + bswap_32big(0x9eeec0cfU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000006b0U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x000005c0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000700U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000610U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000610U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000008U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x0c9982c0U), + bswap_32big(0xcbb05197U), + bswap_32big(0x583cce74U), + bswap_32big(0x22f03686U)); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000005c0U); + WR1_PROG(REG_1018H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003801U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x7fffffffU); + + WR1_PROG(REG_1404H, 0x12300000U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000003cU); + WR1_PROG(REG_1600H, 0x00003841U); + + WR1_PROG(REG_1600H, 0x001f6c42U); + WR1_PROG(REG_1600H, 0x00001002U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00003c01U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003801U); + WR1_PROG(REG_1600H, 0x02003843U); + WR1_PROG(REG_1600H, 0x02003c41U); + WR1_PROG(REG_1600H, 0x02003c03U); + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1600H, 0x00003060U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001a03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7b72a8abU), + bswap_32big(0x8a09952eU), + bswap_32big(0x3e852eacU), + bswap_32big(0x3808d940U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x09b991b9U), + bswap_32big(0xc0a78c03U), + bswap_32big(0x9295e8c3U), + bswap_32big(0x37b6e1a5U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000027U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8e8f190bU), + bswap_32big(0x18f82bb9U), + bswap_32big(0x551416bfU), + bswap_32big(0xbfe9a918U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x32ed748dU), + bswap_32big(0x7931b41fU), + bswap_32big(0xb590287aU), + bswap_32big(0x6f4df683U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[5]); + + r_rsip_func100(bswap_32big(0x93ecbffbU), + bswap_32big(0xb67331d4U), + bswap_32big(0x8b2eb2a4U), + bswap_32big(0x91dab59bU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[9]); + + r_rsip_func100(bswap_32big(0xce3b75bbU), + bswap_32big(0xd25eccfeU), + bswap_32big(0x220f01a3U), + bswap_32big(0xfbce9766U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001a04U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc6606eceU), + bswap_32big(0x66f719e9U), + bswap_32big(0xa978cb01U), + bswap_32big(0x4b4415ceU)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9f07471dU), + bswap_32big(0xb8fc4dcbU), + bswap_32big(0xf9562fe2U), + bswap_32big(0x954692e7U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000026U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00001a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xda7399faU), + bswap_32big(0xef82f87cU), + bswap_32big(0xa46328b2U), + bswap_32big(0xbb4bbc13U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x4a15e963U), + bswap_32big(0x5fc230e4U), + bswap_32big(0x48ffe099U), + bswap_32big(0xdecc5d81U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[5]); + + r_rsip_func100(bswap_32big(0xa5557d94U), + bswap_32big(0x07c7160eU), + bswap_32big(0xbde5e463U), + bswap_32big(0xc038adcfU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[9]); + + r_rsip_func100(bswap_32big(0x53dc76eaU), + bswap_32big(0xa52ec353U), + bswap_32big(0x06f66599U), + bswap_32big(0xf6502fdaU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + r_rsip_func102(bswap_32big(0xf08d02c7U), + bswap_32big(0x51e1a254U), + bswap_32big(0x5de71d48U), + bswap_32big(0x681da887U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p20.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p20.c new file mode 100644 index 0000000000..38a20bc580 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p20.c @@ -0,0 +1,61 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p20 (uint32_t OutData_Text[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00200002U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000020U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7b4e80d3U), + bswap_32big(0x50ed03c3U), + bswap_32big(0x157cda39U), + bswap_32big(0x7532ea8aU)); + r_rsip_func103(); + r_rsip_func100(bswap_32big(0x18dcbb76U), + bswap_32big(0x1bd8115cU), + bswap_32big(0x841c0ee2U), + bswap_32big(0x56401949U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + + r_rsip_func102(bswap_32big(0xca23625aU), + bswap_32big(0xd1fb2144U), + bswap_32big(0x617496c6U), + bswap_32big(0xb60241acU)); + + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p21.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p21.c new file mode 100644 index 0000000000..6b1307002a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p21.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p21 (const uint32_t InData_HV[], + const uint32_t InData_IV[], + const uint32_t InData_Text[], + uint32_t OutData_DataT[], + uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00210001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00070000U); + WR1_PROG(REG_1824H, 0x08008005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_HV[0]); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000025U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a058006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func100(bswap_32big(0x40fd80caU), + bswap_32big(0x761f756dU), + bswap_32big(0x093dea59U), + bswap_32big(0x44147e59U)); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + r_rsip_func102(bswap_32big(0xf8e6bff9U), + bswap_32big(0x14e1b117U), + bswap_32big(0xbef78ffbU), + bswap_32big(0xbd75db0fU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29a.c new file mode 100644 index 0000000000..5435632a7a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29a.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p29a (const uint32_t InData_DataA[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0x92a9fb5aU), + bswap_32big(0xff4b06bbU), + bswap_32big(0xb47f9594U), + bswap_32big(0x1656f183U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29f.c new file mode 100644 index 0000000000..592889f897 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29f.c @@ -0,0 +1,165 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p29f (const uint32_t InData_Text[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd4a17b10U), + bswap_32big(0x4ecbec3bU), + bswap_32big(0x820a466bU), + bswap_32big(0x789adaa1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xc6ef1a28U), bswap_32big(0xa355cc9cU), bswap_32big(0x5954a90eU), + bswap_32big(0xc59abbfaU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1600H, 0x00036800U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x3b8bb95aU), bswap_32big(0x4a8a0a2cU), bswap_32big(0x2d44e567U), + bswap_32big(0x4b9f6edcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0xb07c0555U), bswap_32big(0x3ae5ca4fU), bswap_32big(0x6850b92fU), + bswap_32big(0xe504509cU)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x81840001U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0xbd4cfcdaU), bswap_32big(0x7db55c97U), bswap_32big(0xbed50176U), + bswap_32big(0x10acc0b6U)); + } + + r_rsip_func100(bswap_32big(0x9bf82443U), bswap_32big(0xf8947307U), bswap_32big(0x0277f4d4U), + bswap_32big(0x7828440fU)); + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + r_rsip_func102(bswap_32big(0x02006361U), bswap_32big(0x6672981eU), bswap_32big(0xdfb201bfU), + bswap_32big(0x7f8f1770U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29i.c new file mode 100644 index 0000000000..684fe207b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29i.c @@ -0,0 +1,227 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p29i (const uint32_t InData_KeyIndex[], const uint32_t InData_IVType[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00290001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002901U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2b6a4acdU), + bswap_32big(0x02cba8e3U), + bswap_32big(0x2eb4f871U), + bswap_32big(0x2bc2784cU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002901U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa9ee3ff9U), + bswap_32big(0x52f26700U), + bswap_32big(0x57449ca3U), + bswap_32big(0xb68f9428U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xd00240e7U), + bswap_32big(0x19a18630U), + bswap_32big(0xa72fdc5fU), + bswap_32big(0x9a132d2aU)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x34c3c143U), + bswap_32big(0xcb7c04ceU), + bswap_32big(0x7866458aU), + bswap_32big(0xf5945c1bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x24fe20f9U), bswap_32big(0x9b321bdaU), bswap_32big(0xb46544ffU), + bswap_32big(0xe8f863b7U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IVType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x1f490ff0U), bswap_32big(0xa9f1737dU), bswap_32big(0xf58841f8U), + bswap_32big(0x0559489fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcce45f9fU), bswap_32big(0x36169ddeU), bswap_32big(0x2f35bb2eU), + bswap_32big(0x5508eea2U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002902U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x36b5a34cU), bswap_32big(0x70d34ebcU), bswap_32big(0xee7c05d5U), + bswap_32big(0x3338caf1U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002902U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfa9ffe2eU), bswap_32big(0xaf89c27aU), bswap_32big(0x4467d6a9U), + bswap_32big(0x145063a7U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[1]); + + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xf3ff431cU), bswap_32big(0x6740ebecU), bswap_32big(0xaefe585aU), + bswap_32big(0xaa178c3bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x9418c0daU), + bswap_32big(0x1a4574ccU), + bswap_32big(0x93a8543cU), + bswap_32big(0x872d515aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x8f482b1dU), + bswap_32big(0xcdfd805eU), + bswap_32big(0x9e0366b3U), + bswap_32big(0xaad810d0U)); + } + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00070000U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x3fe58398U), bswap_32big(0x0211fff5U), bswap_32big(0xefe96923U), + bswap_32big(0xda2e6edbU)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29t.c new file mode 100644 index 0000000000..0c2115b9f6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29t.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p29t (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29u.c new file mode 100644 index 0000000000..620b9d3f09 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p29u.c @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p29u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0xf2431294U), + bswap_32big(0xfb1a26e7U), + bswap_32big(0xb06136c0U), + bswap_32big(0x21339089U)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00020020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + + r_rsip_func100(bswap_32big(0x4af240afU), + bswap_32big(0xa35a52a4U), + bswap_32big(0x7b434b76U), + bswap_32big(0xbd78bafbU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00028020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + if (MAX_CNT >= 8) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[4]); + for (iLoop = 8; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + r_rsip_func215(); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00028000U); + WR1_PROG(REG_1824H, 0x08008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x5e69d607U), + bswap_32big(0x5239347cU), + bswap_32big(0x9fe2d624U), + bswap_32big(0x0b3162e9U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2b.c new file mode 100644 index 0000000000..33f57a957a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2b.c @@ -0,0 +1,1932 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p2b (const uint32_t MAX_CNT, uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + uint32_t kLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x002b0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1600H, 0x00000a31U); + for (kLoop = 0U; kLoop < MAX_CNT; kLoop++) + { + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1444H, 0x00002fa2U); + WR1_PROG(REG_1A2CH, 0x00000b00U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00030005U), bswap_32big(0x0007000bU), bswap_32big(0x000d0011U), + bswap_32big(0x00130017U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x001d001fU), bswap_32big(0x00250029U), bswap_32big(0x002b002fU), + bswap_32big(0x003b003dU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00430047U), bswap_32big(0x0049004fU), bswap_32big(0x00530059U), + bswap_32big(0x00610065U)); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x0067006bU), bswap_32big(0x006d0071U), bswap_32big(0x007f0083U), + bswap_32big(0x0089008bU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00950097U), bswap_32big(0x009d00a3U), bswap_32big(0x00a700adU), + bswap_32big(0x00b300b5U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00bf00c1U), bswap_32big(0x00c500c7U), bswap_32big(0x00d300dfU), + bswap_32big(0x00e300e5U)); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00e900efU), bswap_32big(0x00f100fbU), bswap_32big(0x01010107U), + bswap_32big(0x010d010fU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x01150119U), bswap_32big(0x011b0125U), bswap_32big(0x01330137U), + bswap_32big(0x0139013dU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x014b0151U), bswap_32big(0x015b015dU), bswap_32big(0x01610167U), + bswap_32big(0x016f0175U)); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x017b017fU), bswap_32big(0x0185018dU), bswap_32big(0x01910199U), + bswap_32big(0x01a301a5U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x01af01b1U), bswap_32big(0x01b701bbU), bswap_32big(0x01c101c9U), + bswap_32big(0x01cd01cfU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x01d301dfU), bswap_32big(0x01e701ebU), bswap_32big(0x01f301f7U), + bswap_32big(0x01fd0000U)); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80b00006U); + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x034300c1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10180000U); + WR1_PROG(REG_1400H, 0x00c00209U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbb530268U), bswap_32big(0x86be24bdU), bswap_32big(0x31100f57U), + bswap_32big(0x2e89b1ccU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000d01fU); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1404H, 0x11a00000U); + WR1_PROG(REG_1400H, 0x00c90011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000018U); + WR1_PROG(REG_1600H, 0x000008e7U); + + for (iLoop = 0U; iLoop < 24U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc36ab3dfU), bswap_32big(0xe8556e28U), bswap_32big(0x20fa6b9cU), + bswap_32big(0xea48406aU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0xb252d49aU), bswap_32big(0x6b5f12c9U), bswap_32big(0xd96b0aedU), + bswap_32big(0x5808c2e4U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x637b82fbU), bswap_32big(0xf5506346U), bswap_32big(0x825ed69bU), + bswap_32big(0xf8143d90U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000d060U); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1400H, 0x00c90011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x00001fa2U); + WR1_PROG(REG_1A2CH, 0x00000700U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0xB51EB851U), bswap_32big(0xEB851EB8U), bswap_32big(0x51EB851EU), + bswap_32big(0xB851EB85U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x1EB851EBU), bswap_32big(0x851EB851U), bswap_32big(0xEB851EB8U), + bswap_32big(0x51EB851EU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0xB851EB85U), bswap_32big(0x1EB851EBU), bswap_32big(0x851EB851U), + bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x51EB851EU), bswap_32big(0xB851EB85U), bswap_32big(0x1EB851EBU), + bswap_32big(0x851EB851U)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0xEB851EB8U), bswap_32big(0x51EB851EU), bswap_32big(0xB851EB85U), + bswap_32big(0x1EB851EBU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x851EB851U), bswap_32big(0xEB851EB8U), bswap_32big(0x51EB851EU), + bswap_32big(0xB851EB85U)); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x1EB851EBU), bswap_32big(0x851EB851U), bswap_32big(0xEB851EB8U), + bswap_32big(0x51EB851EU)); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0xB851EB85U), bswap_32big(0x1EB851EBU), bswap_32big(0x851EB851U), + bswap_32big(0xEB851B5CU)); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x8e46c456U), bswap_32big(0xb0ad90cfU), bswap_32big(0x432af280U), + bswap_32big(0xc6361c70U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xbb3f0232U), bswap_32big(0x4a30784bU), bswap_32big(0x087a4415U), + bswap_32big(0x255bb714U)); + continue; + } + else + { + r_rsip_func101(bswap_32big(0xd8d31c1eU), bswap_32big(0xe481e37bU), bswap_32big(0x4a2fdbcbU), + bswap_32big(0xdba2085eU)); + } + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x82623a48U), bswap_32big(0x360943b0U), bswap_32big(0x86cb9003U), + bswap_32big(0x90c5e7f1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xebfc321dU), bswap_32big(0x69e6ac74U), bswap_32big(0xcfc75ad5U), + bswap_32big(0xa973618fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000320U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x4753c441U), + bswap_32big(0x2a4a0092U), + bswap_32big(0x7e7c91f6U), + bswap_32big(0x4e613a52U)); + } + else + { + r_rsip_func101(bswap_32big(0x24564178U), + bswap_32big(0xf395bcddU), + bswap_32big(0xf97bd94fU), + bswap_32big(0x8adef143U)); + } + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x00000000U), + bswap_32big(0x00000000U), + bswap_32big(0x00000000U), + bswap_32big(0x10000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00071U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xc9b40780U), bswap_32big(0x95b7d3d5U), bswap_32big(0x1d099d15U), + bswap_32big(0xfa56ecfcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xa6c844bbU), + bswap_32big(0x8f8eb81dU), + bswap_32big(0xf26cd015U), + bswap_32big(0x42cc6109U)); + continue; + } + else + { + r_rsip_func101(bswap_32big(0x2128cd0bU), + bswap_32big(0x3c41b095U), + bswap_32big(0x9e32b1aaU), + bswap_32big(0x8ff9c54cU)); + } + } + else + { + r_rsip_func101(bswap_32big(0x7602a5e2U), bswap_32big(0xc8a1ffe8U), bswap_32big(0xa23756c8U), + bswap_32big(0x9b19fd78U)); + } + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x0000094aU); + + for (iLoop = 0U; iLoop < 95U; iLoop++) + { + WR1_PROG(REG_1600H, 0x01003906U); + WR1_PROG(REG_1600H, 0x00002cc0U); + WR1_PROG(REG_1600H, 0x00002cc0U); + WR1_PROG(REG_1608H, 0x81010100U); + + WR1_PROG(REG_1404H, 0x14280000U); + WR1_PROG(REG_1400H, 0x00c00209U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x15b00000U); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100004U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x63524f27U), bswap_32big(0xfa1597c1U), bswap_32big(0x0720b17dU), + bswap_32big(0x53c6accbU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000d140U); + + r_rsip_func101(bswap_32big(0xbecf55d1U), + bswap_32big(0xec6f66cbU), + bswap_32big(0x3a6d3108U), + bswap_32big(0x4e537c0eU)); + break; + } + else + { + r_rsip_func101(bswap_32big(0xfe55d5e2U), + bswap_32big(0x5d4a9194U), + bswap_32big(0x470d9229U), + bswap_32big(0xfb1c905cU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xcdcd1581U), bswap_32big(0x009054c9U), bswap_32big(0xbe572e37U), + bswap_32big(0x9d8069deU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xe5940a94U), bswap_32big(0xf443718dU), bswap_32big(0xfe1a3622U), + bswap_32big(0xe4ebb2eaU)); + continue; + } + + WR1_PROG(REG_1404H, 0x18b80000U); + WR1_PROG(REG_1400H, 0x00c00081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14280000U); + WR1_PROG(REG_1400H, 0x00c00209U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x15b00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00010001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100004U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xe9c26dffU), bswap_32big(0x3d99b9fdU), bswap_32big(0xae2d1c34U), + bswap_32big(0x5407874aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x63f068f5U), bswap_32big(0x8611299cU), bswap_32big(0x792ec17dU), + bswap_32big(0x5641808bU)); + } + else + { + WR1_PROG(REG_1404H, 0x16300000U); + WR1_PROG(REG_1400H, 0x00c00209U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x4d9468cbU), bswap_32big(0xea66de8cU), bswap_32big(0x2b851535U), + bswap_32big(0x6b721743U)); + WR1_PROG(REG_1404H, 0x17b80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000428U); + + WR1_PROG(REG_1004H, 0x10100010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x0d9f8f2bU), bswap_32big(0x094d13f2U), bswap_32big(0xb7594226U), + bswap_32big(0x4eae1821U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x899c588aU), + bswap_32big(0x1bcf9d61U), + bswap_32big(0x7dc52458U), + bswap_32big(0xea61c5f0U)); + continue; + } + + r_rsip_func100(bswap_32big(0xb39e2c0dU), bswap_32big(0x62b67a14U), bswap_32big(0xb17917cdU), + bswap_32big(0x1128f2fcU)); + + WR1_PROG(REG_1600H, 0x0000b560U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x0000094aU); + WR1_PROG(REG_1608H, 0x80a0000aU); + WR1_PROG(REG_1404H, 0x11a00000U); + WR1_PROG(REG_1400H, 0x03430081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000929U); + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x0000007cU); + + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000038e6U); + WR1_PROG(REG_1600H, 0x0000a8c0U); + WR1_PROG(REG_1600H, 0x00000004U); + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1600H, 0x11816907U); + + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10002d20U); + + WR1_PROG(REG_1600H, 0x000168e7U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010120U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WR1_PROG(REG_1600H, 0x000037e9U); + + WR1_PROG(REG_1404H, 0x15b00000U); + WR1_PROG(REG_1600H, 0x0000094aU); + WR1_PROG(REG_1608H, 0x81a0000aU); + WR1_PROG(REG_1400H, 0x00c90081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x000033e0U); + + r_rsip_func101(bswap_32big(0xebe483f9U), + bswap_32big(0x7f993974U), + bswap_32big(0x03fc5bd1U), + bswap_32big(0xd3bbe7d8U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007c1fU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xdd4e4379U), bswap_32big(0x97e1d8b7U), bswap_32big(0xe6d16aa9U), + bswap_32big(0x41b25071U)); + WR1_PROG(REG_1600H, 0x00000a52U); + + WR1_PROG(REG_1608H, 0x81010160U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1404H, 0x10180000U); + WR1_PROG(REG_1400H, 0x00c00209U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x11a00000U); + for (jLoop = 0U; jLoop < 32U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b04U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe58d33a0U), + bswap_32big(0x7c69bf69U), + bswap_32big(0x48559794U), + bswap_32big(0xb7f000bbU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x3ba33a78U), + bswap_32big(0xc2b5450bU), + bswap_32big(0x4346d088U), + bswap_32big(0x26d422bbU)); + jLoop = jLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xe2bdd415U), + bswap_32big(0xb005ac7dU), + bswap_32big(0x9686839fU), + bswap_32big(0x6a3391feU)); + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000004U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x10100004U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x17b80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000428U); + + WR1_PROG(REG_1004H, 0x10100010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xad7b5a4aU), + bswap_32big(0x4251f0ecU), + bswap_32big(0xd704ec98U), + bswap_32big(0x3fc74685U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 0)) + { + WR1_PROG(REG_1600H, 0x00002e40U); + + r_rsip_func101(bswap_32big(0x7951c756U), + bswap_32big(0x1ba6a758U), + bswap_32big(0xc07ee7b5U), + bswap_32big(0xfbe04689U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000094aU); + + r_rsip_func100(bswap_32big(0x3b2ec828U), + bswap_32big(0x96ebf625U), + bswap_32big(0x2bcadd21U), + bswap_32big(0x4e03f99cU)); + WR1_PROG(REG_1608H, 0x81010120U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + WR1_PROG(REG_1600H, 0x000037e9U); + + for (jLoop = 0U; jLoop < S_RAM[0 + 1]; jLoop++) + { + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1608H, 0x81a0000aU); + WR1_PROG(REG_1400H, 0x00c90081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xfb37f76aU), + bswap_32big(0xd59daafeU), + bswap_32big(0x626e174dU), + bswap_32big(0x3e14ba40U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 0)) + { + WR1_PROG(REG_1600H, 0x00002e40U); + + r_rsip_func101(bswap_32big(0x67c4c84eU), + bswap_32big(0x41b857d5U), + bswap_32big(0xf51dd4ceU), + bswap_32big(0xe391a6feU)); + break; + } + else + { + WR1_PROG(REG_1404H, 0x18380000U); + WR1_PROG(REG_1400H, 0x00c00209U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x6684158aU), + bswap_32big(0xc9376f6dU), + bswap_32big(0x7f62e650U), + bswap_32big(0x1acdaa27U)); + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x10100000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xa4ed964fU), + bswap_32big(0xabdfb25cU), + bswap_32big(0x0c148259U), + bswap_32big(0x88080bbcU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008a40U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd11aadcdU), + bswap_32big(0xc24162c2U), + bswap_32big(0xe3d87713U), + bswap_32big(0xa3763f14U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x590b9213U), + bswap_32big(0xed101946U), + bswap_32big(0xed0fee9cU), + bswap_32big(0x21767261U)); + break; + } + else + { + r_rsip_func101(bswap_32big(0x1d5a9314U), + bswap_32big(0x58137212U), + bswap_32big(0xcfcc2771U), + bswap_32big(0x8c483a24U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38000a4bU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x8c869ae5U), bswap_32big(0x10ea9640U), bswap_32big(0xa82e46d7U), + bswap_32big(0xc382c209U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00002e20U); + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x258a1fd0U), + bswap_32big(0x68c2cd28U), + bswap_32big(0x03a73d82U), + bswap_32big(0x2c2a1a30U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xa97af9e4U), + bswap_32big(0x01e9e11fU), + bswap_32big(0xadc04141U), + bswap_32big(0x723a5cacU)); + break; + } + else + { + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000320U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x8802cba2U), + bswap_32big(0xc021b2ffU), + bswap_32big(0xf1d4f4a0U), + bswap_32big(0xe2ea6b63U)); + } + } + else + { + r_rsip_func101(bswap_32big(0xacf17654U), + bswap_32big(0x5f1bb542U), + bswap_32big(0xd5350120U), + bswap_32big(0x84f2f020U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xa87ea8beU), + bswap_32big(0xf939b193U), + bswap_32big(0x3854dfbcU), + bswap_32big(0xbf42173dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x07725832U), bswap_32big(0x40764facU), bswap_32big(0x57588b7fU), + bswap_32big(0x6b18e449U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1400H, 0x00c00081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x000007b8U); + + WR1_PROG(REG_1004H, 0x10100009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b05U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5e585107U), + bswap_32big(0x21c740b5U), + bswap_32big(0xcbed30efU), + bswap_32big(0x99ff6045U)); + r_rsip_func113(); + r_rsip_func100(bswap_32big(0x990e2718U), + bswap_32big(0x268d6f56U), + bswap_32big(0x97d0fd7fU), + bswap_32big(0xd35f02dfU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c2000c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x820edca6U)); + + OFS_ADR = 356; + + WR1_PROG(REG_1404H, 0x17380000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0a0cbac9U), + bswap_32big(0xc597808dU), + bswap_32big(0x1498d75dU), + bswap_32big(0xd3bb1225U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000002bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7429725fU), + bswap_32big(0xd7677e50U), + bswap_32big(0xa55acd14U), + bswap_32big(0xedee8c08U)); + r_rsip_func052(); + + WR1_PROG(REG_1404H, 0x15200000U); + WR1_PROG(REG_1400H, 0x00c00091U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x820edca6U)); + + OFS_ADR = 356; + + WR1_PROG(REG_1404H, 0x17380000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x825ffb2bU), + bswap_32big(0x0cc8e2b7U), + bswap_32big(0x49549332U), + bswap_32big(0x56069029U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1014H, 0x000007b8U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x10100007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xadf847acU), + bswap_32big(0x2836ad74U), + bswap_32big(0xf0d0f352U), + bswap_32big(0x6280e7d5U)); + r_rsip_func054(); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xa55dff21U), + bswap_32big(0x94ad7ebaU), + bswap_32big(0x6aab3825U), + bswap_32big(0x012bd1f6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x68fd14daU), bswap_32big(0x728b9501U), bswap_32big(0xaca5d927U), + bswap_32big(0x3873d145U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x820edca6U)); + + OFS_ADR = 356; + + WR1_PROG(REG_1404H, 0x13280000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xeb36ad34U), + bswap_32big(0x3fc0caf7U), + bswap_32big(0xdbf5fca9U), + bswap_32big(0x023786ccU)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1014H, 0x000003a8U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x820edca6U)); + + OFS_ADR = 356; + + WR1_PROG(REG_1404H, 0x15300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc55e11b8U), + bswap_32big(0xb8ccdc46U), + bswap_32big(0x02f87d20U), + bswap_32big(0x04e7b0d2U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x17280000U); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000003a8U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x000001a0U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001a0U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x10100007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x20200002U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x20200003U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x20200002U); + WR1_PROG(REG_1000H, 0x00010201U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x15300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00010001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdc89b916U), + bswap_32big(0x589e71e2U), + bswap_32big(0x0ca1e88dU), + bswap_32big(0x5277c589U)); + r_rsip_func054(); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xa5f6927cU), + bswap_32big(0xc62797c1U), + bswap_32big(0x292a7c7eU), + bswap_32big(0xc1cf2ddcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe3bdb8f7U), bswap_32big(0xfd76c5aeU), bswap_32big(0x38779653U), + bswap_32big(0x95252ecfU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1400H, 0x00c00101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x820edca6U)); + + OFS_ADR = 356; + + WR1_PROG(REG_1404H, 0x15300000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9f1aa4e4U), + bswap_32big(0xed5f8d05U), + bswap_32big(0x5a6b230aU), + bswap_32big(0x0852a232U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x00010001U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b06U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x996c9594U), + bswap_32big(0x90cc5f3aU), + bswap_32big(0x524b6560U), + bswap_32big(0x9d153078U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000012bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xed1cda30U), + bswap_32big(0x334686bdU), + bswap_32big(0x816bf3b7U), + bswap_32big(0x43377c39U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000dU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000012bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x664d989aU), + bswap_32big(0x52909cefU), + bswap_32big(0x21909a2cU), + bswap_32big(0x7ce84d7fU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x15300000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xf2ca3e59U), bswap_32big(0x09038dc1U), bswap_32big(0x0307f2bfU), + bswap_32big(0x7096f49bU)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[1 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x34f180e5U), bswap_32big(0xbc03ad81U), bswap_32big(0x0a00fc87U), + bswap_32big(0xd6f824e2U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x13280000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x6e87a8b3U), bswap_32big(0x5cdcdc0aU), bswap_32big(0xad4f55bfU), + bswap_32big(0x55501825U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[65 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x20dd5579U), bswap_32big(0x76f98691U), bswap_32big(0xa4d56a56U), + bswap_32big(0x83d6edacU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x730a33f4U), + bswap_32big(0x5283eb94U), + bswap_32big(0x6003d614U), + bswap_32big(0xfb79f788U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[129]); + + r_rsip_func100(bswap_32big(0xed1995c9U), + bswap_32big(0x6e05e204U), + bswap_32big(0x7afa7656U), + bswap_32big(0xe7b8a4ebU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00002b07U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x146fc0a2U), + bswap_32big(0x634c8bffU), + bswap_32big(0xf043c233U), + bswap_32big(0x395030f0U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000022bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xff1f14f1U), + bswap_32big(0xc7af1d18U), + bswap_32big(0xeffa7b2eU), + bswap_32big(0xd652d31aU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000cU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000022bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xee9ad686U), + bswap_32big(0x09917a25U), + bswap_32big(0x9e5053b6U), + bswap_32big(0xa7057d3fU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x15300000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x257419b0U), bswap_32big(0x6ad86520U), bswap_32big(0xbed94152U), + bswap_32big(0x2d4ade36U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[1 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0xaed61b5fU), bswap_32big(0x1ee228e0U), bswap_32big(0x1b842116U), + bswap_32big(0x650a2e84U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xdd6e990fU), + bswap_32big(0x94f91542U), + bswap_32big(0x82e17b98U), + bswap_32big(0x8c7188e6U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008104U); + WR1_PROG(REG_1608H, 0x81010280U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[65]); + + r_rsip_func100(bswap_32big(0x42b59108U), + bswap_32big(0xbad484dbU), + bswap_32big(0xcf686ff8U), + bswap_32big(0x39bf0675U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[69]); + + r_rsip_func100(bswap_32big(0xb6897939U), + bswap_32big(0x090f1ff0U), + bswap_32big(0x30137ca0U), + bswap_32big(0xfb423244U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + r_rsip_func102(bswap_32big(0xe31b4f49U), + bswap_32big(0x4ce5b5cfU), + bswap_32big(0x6d32d151U), + bswap_32big(0x787b8d98U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c new file mode 100644 index 0000000000..cf6c1120fd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2c.c @@ -0,0 +1,153 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p2c (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x002c0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000002cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe4550b41U), + bswap_32big(0x816b27d7U), + bswap_32big(0xa6f03cf4U), + bswap_32big(0x1b2b8f33U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000002cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x739f6269U), + bswap_32big(0xed55ff32U), + bswap_32big(0xe94789c6U), + bswap_32big(0x0b4d7a23U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xf3c4df08U), + bswap_32big(0xde01e9caU), + bswap_32big(0x5029ab3eU), + bswap_32big(0xeb6fb089U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd050af91U), bswap_32big(0x30204a38U), bswap_32big(0xfc8aff57U), + bswap_32big(0x74abc66fU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xca38b20eU), bswap_32big(0x620da7e5U), bswap_32big(0x11048e7fU), + bswap_32big(0x60a81deaU)); + WR1_PROG(REG_1438H, 0x40000100U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1400H, 0x02090005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xd6446ed6U), bswap_32big(0x844d807dU), bswap_32big(0x4701e6a3U), + bswap_32big(0xd90b30deU)); + WR1_PROG(REG_1438H, 0x40000110U); + + WR1_PROG(REG_1400H, 0x02000011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xea310309U), bswap_32big(0xcdea15b9U), bswap_32big(0x4b530004U), + bswap_32big(0xacca6c86U)); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x02090011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DOTFSEED[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DOTFSEED[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x4b09bad8U), bswap_32big(0x7cf5ec6fU), bswap_32big(0xd91a3e0aU), + bswap_32big(0xab56dd86U)); + WR1_PROG(REG_1438H, 0x40000140U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1400H, 0x02090009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func102(bswap_32big(0xe53bf0f4U), bswap_32big(0x1d2adf54U), bswap_32big(0x1556405bU), + bswap_32big(0x7ce73748U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2d.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2d.c new file mode 100644 index 0000000000..f70d94d2db --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2d.c @@ -0,0 +1,155 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p2d (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x002d0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000002dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4e8a0d28U), + bswap_32big(0x7df86047U), + bswap_32big(0x39378e07U), + bswap_32big(0x0f668eceU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000002dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xea2a7360U), + bswap_32big(0xb832644aU), + bswap_32big(0x8bd3e735U), + bswap_32big(0x71bd1c17U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x5c371d6bU), + bswap_32big(0x598f7b65U), + bswap_32big(0x954f2c91U), + bswap_32big(0xcf76d7e1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x27a9c796U), bswap_32big(0xdd07dc91U), bswap_32big(0x146091d3U), + bswap_32big(0xe0189051U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x82bd954dU), bswap_32big(0xbc85b76fU), bswap_32big(0xbccc8fd9U), + bswap_32big(0x54f187edU)); + WR1_PROG(REG_1438H, 0x40000100U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1400H, 0x02090005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xc75c0d1dU), bswap_32big(0x44eb94ddU), bswap_32big(0x376cee07U), + bswap_32big(0x30ef5860U)); + WR1_PROG(REG_1438H, 0x40000110U); + + WR1_PROG(REG_1400H, 0x02000009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x107f17fdU), bswap_32big(0x71037facU), bswap_32big(0x2f457a30U), + bswap_32big(0x1534de24U)); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81860001U); + WR1_PROG(REG_1400H, 0x02090019U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DOTFSEED[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DOTFSEED[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xd47ef471U), bswap_32big(0x8b4a5e6eU), bswap_32big(0xe21d68e5U), + bswap_32big(0x4dbd369aU)); + WR1_PROG(REG_1438H, 0x40000140U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1400H, 0x02090009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func102(bswap_32big(0xc7398015U), bswap_32big(0xd0763bc5U), bswap_32big(0xa42bcf4fU), + bswap_32big(0xc68025deU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2e.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2e.c new file mode 100644 index 0000000000..523ac5c89c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p2e.c @@ -0,0 +1,153 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p2e (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x002e0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000002eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x064b8eacU), + bswap_32big(0x46aa6347U), + bswap_32big(0x0e7c5c90U), + bswap_32big(0xa2b91c93U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000002eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x530d294cU), + bswap_32big(0xf64cf311U), + bswap_32big(0x50d60570U), + bswap_32big(0xff20f891U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xa93f975bU), + bswap_32big(0x158d0472U), + bswap_32big(0x90f5ec2fU), + bswap_32big(0xc28a9489U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x800f3032U), bswap_32big(0x17c60138U), bswap_32big(0xdd5f4ad9U), + bswap_32big(0x950eef2bU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x87697706U), bswap_32big(0x53972684U), bswap_32big(0x85dd8526U), + bswap_32big(0xf67f8015U)); + WR1_PROG(REG_1438H, 0x40000100U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1400H, 0x02090005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x40c39521U), bswap_32big(0xd8d9e045U), bswap_32big(0x99fa81a1U), + bswap_32big(0xe705c507U)); + WR1_PROG(REG_1438H, 0x40000110U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1400H, 0x02090021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DOTFSEED[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DOTFSEED[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x4ec71b94U), bswap_32big(0x826f31d2U), bswap_32big(0x8693bce3U), + bswap_32big(0x11f4d7d9U)); + WR1_PROG(REG_1438H, 0x40000140U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1400H, 0x02090009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func102(bswap_32big(0xc8dc4820U), bswap_32big(0xfaa9262fU), bswap_32big(0xb74c44eeU), + bswap_32big(0x7e7b4261U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p31.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p31.c new file mode 100644 index 0000000000..0488b96672 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p31.c @@ -0,0 +1,261 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p31 (const uint32_t InData_HashType[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + uint32_t OutData_MsgDigest[], + uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00310001U); + WR1_PROG(REG_144CH, 0x00000000U); + + r_rsip_func100(bswap_32big(0x62385557U), + bswap_32big(0x7a5628aeU), + bswap_32big(0x9a99514fU), + bswap_32big(0xdda38601U)); + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b400U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_2004H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x22109c28U), bswap_32big(0xba4ec560U), bswap_32big(0x3e908923U), + bswap_32big(0xba558af6U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_2004H, 0x00000040U); + + r_rsip_func101(bswap_32big(0x503d0fa1U), bswap_32big(0x25eec85eU), bswap_32big(0x24ca0eb6U), + bswap_32big(0xff93da2bU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_2004H, 0x00000050U); + + r_rsip_func101(bswap_32big(0xed233fc0U), bswap_32big(0x04ac4f07U), bswap_32big(0xaf05aa05U), + bswap_32big(0x11f1cd93U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_2004H, 0x00000080U); + + r_rsip_func101(bswap_32big(0x4e55f287U), bswap_32big(0x7706d006U), bswap_32big(0x9fe1d6d2U), + bswap_32big(0x52d55e94U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_2004H, 0x00000090U); + + r_rsip_func101(bswap_32big(0xdd6fcefbU), bswap_32big(0x37de5497U), bswap_32big(0xcb784168U), + bswap_32big(0xc229c60eU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_2004H, 0x000000a0U); + + r_rsip_func101(bswap_32big(0xa38edc66U), bswap_32big(0x349759a9U), bswap_32big(0x0c42227eU), + bswap_32big(0x1308c0dfU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_2004H, 0x000000b0U); + + r_rsip_func101(bswap_32big(0xfa515800U), bswap_32big(0x88647384U), bswap_32big(0xedd52300U), + bswap_32big(0xa8324a51U)); + } + + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_200CH, 0x00000100U); + + r_rsip_func101(bswap_32big(0x3ec2055bU), bswap_32big(0x723c11deU), bswap_32big(0xfe0ad62fU), + bswap_32big(0x8aa8325eU)); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_MsgLen[1]); + + r_rsip_func101(bswap_32big(0x619997b2U), bswap_32big(0x57979dc8U), bswap_32big(0xfeec98aeU), + bswap_32big(0x7d85637cU)); + } + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR16_ADDR(REG_1420H, &InData_Msg[iLoop]); + + iLoop = iLoop + 16U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop++) + { + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + + WAIT_STS(REG_2030H, 4, 1); + + r_rsip_func100(bswap_32big(0x11df1a6fU), + bswap_32big(0x4c46acd1U), + bswap_32big(0xafc5fc80U), + bswap_32big(0x180ad28dU)); + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x1000b400U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x1000b400U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func100(bswap_32big(0x6904b628U), bswap_32big(0x35695477U), bswap_32big(0xf951a736U), + bswap_32big(0x8337e951U)); + WR1_PROG(REG_1408H, 0x00004016U); + for (iLoop = 0U; iLoop < 5U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func102(bswap_32big(0x31ffd17cU), bswap_32big(0xa28ec340U), bswap_32big(0x1d00b5bbU), + bswap_32big(0x82c82642U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func100(bswap_32big(0xc5895cf7U), bswap_32big(0x8acc4e2bU), bswap_32big(0x3d0a0b09U), + bswap_32big(0x1a62561bU)); + WR1_PROG(REG_1408H, 0x0000401eU); + for (iLoop = 0U; iLoop < 7U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func102(bswap_32big(0xd82a2cc0U), bswap_32big(0xed085186U), bswap_32big(0xd7832099U), + bswap_32big(0x6db679cdU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func100(bswap_32big(0x5a0e307dU), bswap_32big(0xbf037881U), bswap_32big(0xe53a0ed6U), + bswap_32big(0x981ed136U)); + WR1_PROG(REG_1408H, 0x00004022U); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func102(bswap_32big(0xa836b017U), bswap_32big(0x4bd4cd31U), bswap_32big(0xfe9e745dU), + bswap_32big(0xd3f256f2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + r_rsip_func100(bswap_32big(0x8e5b2e04U), bswap_32big(0x8ee752c5U), bswap_32big(0x57ca9f51U), + bswap_32big(0x44a7024dU)); + WR1_PROG(REG_1408H, 0x00004032U); + for (iLoop = 0U; iLoop < 12U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func102(bswap_32big(0x00266d6eU), bswap_32big(0x072e737aU), bswap_32big(0xacfb1600U), + bswap_32big(0x052ca8e4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + r_rsip_func100(bswap_32big(0xa012e3ecU), bswap_32big(0x015b0f14U), bswap_32big(0xe15eb65fU), + bswap_32big(0xe65ff9f0U)); + WR1_PROG(REG_1408H, 0x00004042U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func102(bswap_32big(0x0d4bc92fU), bswap_32big(0x8be7f79cU), bswap_32big(0x9a678cfbU), + bswap_32big(0x9ac5dd79U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32a.c new file mode 100644 index 0000000000..710e10c6ed --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32a.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p32a (const uint32_t InData_DataA[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0x1f290cfaU), + bswap_32big(0xc291cb2eU), + bswap_32big(0x58e82591U), + bswap_32big(0x93c29883U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32f.c new file mode 100644 index 0000000000..cab52b16fe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32f.c @@ -0,0 +1,215 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p32f (const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x9eb1adc1U), + bswap_32big(0x85492440U), + bswap_32big(0xfe5c56f5U), + bswap_32big(0xd6cff67bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x3c9fd1ceU), bswap_32big(0x1e139381U), bswap_32big(0xae3162ffU), + bswap_32big(0x39eb8ff1U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1600H, 0x00036800U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x14bc2e45U), bswap_32big(0x20397e7bU), bswap_32big(0x8ae1d485U), + bswap_32big(0x8b01c163U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0xc8ce96d4U), bswap_32big(0x2cfd0a01U), bswap_32big(0x3f8b749eU), + bswap_32big(0x363cb380U)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00018020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0x7699ef48U), bswap_32big(0x03aa298cU), bswap_32big(0x98b27a55U), + bswap_32big(0x10e17ebbU)); + } + + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x2f376d24U), bswap_32big(0x7f7f0dd9U), bswap_32big(0x2dd061d9U), + bswap_32big(0x7a8d8760U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd8841126U), bswap_32big(0x39011d57U), bswap_32big(0x29f8af5dU), + bswap_32big(0xbeb8c8f2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x2b59075aU), bswap_32big(0x86d11b58U), bswap_32big(0xc7530eb4U), + bswap_32big(0x9b15655fU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32i.c new file mode 100644 index 0000000000..8415fde378 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32i.c @@ -0,0 +1,227 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p32i (const uint32_t InData_KeyIndex[], const uint32_t InData_IVType[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00320001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003201U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0dfc12a4U), + bswap_32big(0xfa8880ccU), + bswap_32big(0x5bd5afcfU), + bswap_32big(0x3c95f918U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003201U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfe886365U), + bswap_32big(0xf6aeb45aU), + bswap_32big(0x95d59963U), + bswap_32big(0x41bc194cU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x338ff82bU), + bswap_32big(0x84c1bf79U), + bswap_32big(0x3d6e030dU), + bswap_32big(0xf99ba861U)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x5278f9adU), + bswap_32big(0x5a5a03c0U), + bswap_32big(0x22c9ab0aU), + bswap_32big(0xd417ae7bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x06d299d8U), bswap_32big(0xbfe159b0U), bswap_32big(0xbababe5aU), + bswap_32big(0xaf8cd8f8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IVType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x3499228bU), bswap_32big(0x05527b55U), bswap_32big(0x32646751U), + bswap_32big(0xd9ad9186U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf72820acU), bswap_32big(0xa3354f78U), bswap_32big(0x0f25691fU), + bswap_32big(0x5c8e9215U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003202U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf054384fU), bswap_32big(0xd1c7cde3U), bswap_32big(0xb04510c2U), + bswap_32big(0x046e95dcU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003202U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3e7472c8U), bswap_32big(0x018d19d2U), bswap_32big(0x989946edU), + bswap_32big(0xb7bbe33fU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[1]); + + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xed02afb6U), bswap_32big(0x6145cbc0U), bswap_32big(0x47a21e84U), + bswap_32big(0x4919a996U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xa3fbd9a2U), + bswap_32big(0x6092c04dU), + bswap_32big(0x1062edf4U), + bswap_32big(0x1cf9acc4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x545b605aU), + bswap_32big(0x558e1182U), + bswap_32big(0xeb72a294U), + bswap_32big(0xd12eabf6U)); + } + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00070000U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x0b0cc55bU), bswap_32big(0x1e6a90e5U), bswap_32big(0x4dbfb921U), + bswap_32big(0xaa982470U)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32t.c new file mode 100644 index 0000000000..21397a9d2c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32t.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p32t (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32u.c new file mode 100644 index 0000000000..6c7fbc6fb1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p32u.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p32u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x82e17accU), + bswap_32big(0x0ac22052U), + bswap_32big(0x3fbbfbbaU), + bswap_32big(0xcd39b6e3U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + r_rsip_func215(); + + r_rsip_func101(bswap_32big(0x3e87a72eU), + bswap_32big(0x0c8d27edU), + bswap_32big(0x84a3c38eU), + bswap_32big(0x753b1d60U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34a.c new file mode 100644 index 0000000000..3086859ce9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34a.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p34a (const uint32_t InData_DataA[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0x6cd19482U), + bswap_32big(0xfd431017U), + bswap_32big(0x9a3bb037U), + bswap_32big(0x5573f17eU)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34f.c new file mode 100644 index 0000000000..2032cae803 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34f.c @@ -0,0 +1,166 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p34f (const uint32_t InData_Text[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x52312e79U), + bswap_32big(0x93ad8205U), + bswap_32big(0xba1e5c4cU), + bswap_32big(0x1ffaec0bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x402a09dbU), bswap_32big(0x16de41a8U), bswap_32big(0x1c594089U), + bswap_32big(0xcc799c65U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1600H, 0x00036800U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x6320c519U), bswap_32big(0x2f49b2fcU), bswap_32big(0x8336d0f5U), + bswap_32big(0x6ab029d4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x77fa94b3U), bswap_32big(0x497edf59U), bswap_32big(0xf5eeabdeU), + bswap_32big(0x6d5553ceU)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x81840001U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0x1adf3a75U), bswap_32big(0x6d45afddU), bswap_32big(0xf50f6b77U), + bswap_32big(0xa04525b6U)); + } + + r_rsip_func100(bswap_32big(0x476b9d2cU), bswap_32big(0x3982f253U), bswap_32big(0x975a427eU), + bswap_32big(0xdd47b8e9U)); + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + r_rsip_func102(bswap_32big(0x40c85ddeU), bswap_32big(0xb6a48aecU), bswap_32big(0x9d88af0bU), + bswap_32big(0x79aa503aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34i.c new file mode 100644 index 0000000000..7062636cb2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34i.c @@ -0,0 +1,238 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p34i (const uint32_t InData_KeyIndex[], const uint32_t InData_IVType[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00340001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003401U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa1a89503U), + bswap_32big(0x98dfdbf1U), + bswap_32big(0xd71361c0U), + bswap_32big(0xaebce691U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003401U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x94fbe1e1U), + bswap_32big(0xca324aa5U), + bswap_32big(0x39de5889U), + bswap_32big(0x16b0301eU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x7ace34eaU), + bswap_32big(0xa39c2112U), + bswap_32big(0xe3ea362cU), + bswap_32big(0xe0596bccU)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xce1d2959U), + bswap_32big(0x55e309beU), + bswap_32big(0x43ab1748U), + bswap_32big(0x92a2ae85U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x13694d05U), + bswap_32big(0x98ce3f05U), + bswap_32big(0x267eaa94U), + bswap_32big(0x7ff85210U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xdc58ab87U), bswap_32big(0x471eadfaU), bswap_32big(0x67aa937fU), + bswap_32big(0xfb369f3dU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IVType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x0128c57dU), bswap_32big(0xb87a8064U), bswap_32big(0xebe67e81U), + bswap_32big(0x8a621a01U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9290d273U), bswap_32big(0x7deced29U), bswap_32big(0x541e1cdcU), + bswap_32big(0x7779ac75U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003402U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6e5cbcacU), bswap_32big(0xf02ca8e0U), bswap_32big(0x95158d15U), + bswap_32big(0x8668f112U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003402U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa41063f0U), bswap_32big(0x6b151900U), bswap_32big(0x4adf5d73U), + bswap_32big(0x0aebc649U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[1]); + + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xc2885833U), bswap_32big(0x0bb2499bU), bswap_32big(0x7a2f07e3U), + bswap_32big(0xc6fdb699U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd572aed5U), + bswap_32big(0xfcce968fU), + bswap_32big(0xd5b39a14U), + bswap_32big(0x9a65dbb5U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x724e4e1cU), + bswap_32big(0xbbee6407U), + bswap_32big(0xb4819a97U), + bswap_32big(0xf479b8abU)); + } + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40070000U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0xe21815faU), bswap_32big(0xf2a388efU), bswap_32big(0x2d448464U), + bswap_32big(0xaa05ef6fU)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34t.c new file mode 100644 index 0000000000..85c08b3db1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34t.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p34t (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34u.c new file mode 100644 index 0000000000..5d05c6d735 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p34u.c @@ -0,0 +1,75 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p34u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x96d9bcbdU), + bswap_32big(0x8aadca48U), + bswap_32big(0x82cea6adU), + bswap_32big(0xb7b62c80U)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40020020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + + r_rsip_func100(bswap_32big(0x98e71896U), + bswap_32big(0x50db210fU), + bswap_32big(0xf4825ac2U), + bswap_32big(0x48da729fU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40028020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + if (MAX_CNT >= 8) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[4]); + for (iLoop = 8; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + r_rsip_func215(); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00028000U); + WR1_PROG(REG_1824H, 0x08008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x3909db02U), + bswap_32big(0x2fdfa9f5U), + bswap_32big(0x004b6dedU), + bswap_32big(0xbf673aa5U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36a.c new file mode 100644 index 0000000000..be10e48ac4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36a.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p36a (const uint32_t InData_DataA[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0xa4d1dcafU), + bswap_32big(0x3cf63677U), + bswap_32big(0xd75d7628U), + bswap_32big(0xeddfb1dfU)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36f.c new file mode 100644 index 0000000000..2c20651b53 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36f.c @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p36f (const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x38644529U), + bswap_32big(0x7cb3ad21U), + bswap_32big(0xef228c44U), + bswap_32big(0xec61df57U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0d2837b9U), bswap_32big(0x3b0b7349U), bswap_32big(0x1d2ba0cdU), + bswap_32big(0x62c5958aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1600H, 0x00036800U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xbcc461b2U), bswap_32big(0x19b725bbU), bswap_32big(0x37dbffe7U), + bswap_32big(0xb038451aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x3e19b863U), bswap_32big(0xacf5d5d0U), bswap_32big(0x53f2cea6U), + bswap_32big(0x953ba9c4U)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40018020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0x7fd3f4f6U), bswap_32big(0x84bceb66U), bswap_32big(0x955f048dU), + bswap_32big(0xc45ad97bU)); + } + else + { + } + + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xdd7b6d7bU), bswap_32big(0xf463fa83U), bswap_32big(0x3aef73b0U), + bswap_32big(0x0dd15a67U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x91fe3861U), bswap_32big(0xada191d1U), bswap_32big(0xfd5d3d81U), + bswap_32big(0x939a04e4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x05ac305bU), bswap_32big(0xe13a1aaeU), bswap_32big(0x5611f1eaU), + bswap_32big(0x00b7bafdU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36i.c new file mode 100644 index 0000000000..e72e866985 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36i.c @@ -0,0 +1,238 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p36i (const uint32_t InData_KeyIndex[], const uint32_t InData_IVType[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00360001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003601U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5e46e6a2U), + bswap_32big(0xb573fa8dU), + bswap_32big(0xddbf8d7aU), + bswap_32big(0xe29b97afU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003601U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7fb9bf71U), + bswap_32big(0x7c9ec2a4U), + bswap_32big(0x232dabf5U), + bswap_32big(0x507c260dU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x98a261a1U), + bswap_32big(0x569860e7U), + bswap_32big(0xbdad963bU), + bswap_32big(0x79207655U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xd7a02c4aU), + bswap_32big(0x8c0a14f9U), + bswap_32big(0xa6a78147U), + bswap_32big(0xc007bd64U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x7ba98e87U), + bswap_32big(0xd790c6feU), + bswap_32big(0x99d9f082U), + bswap_32big(0x3d2c3f81U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x17126d8eU), bswap_32big(0x8b4621d0U), bswap_32big(0x138216e8U), + bswap_32big(0xfe8f9660U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IVType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x5cf1e457U), bswap_32big(0x8d33b519U), bswap_32big(0x7de4522fU), + bswap_32big(0x45353d7eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9d1ad23aU), bswap_32big(0x5bd45281U), bswap_32big(0xe2e79f42U), + bswap_32big(0x1d0193aeU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003602U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd2ba1284U), bswap_32big(0x3e478d59U), bswap_32big(0x9f18a2c6U), + bswap_32big(0x9604b21aU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003602U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbd0a818cU), bswap_32big(0xb5b178d4U), bswap_32big(0x932f66f8U), + bswap_32big(0x73554ae6U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[1]); + + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x3d56954cU), bswap_32big(0xa627e3cfU), bswap_32big(0x9795015aU), + bswap_32big(0x5d8be3a3U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8b674233U), + bswap_32big(0xd828c49cU), + bswap_32big(0x98607ee5U), + bswap_32big(0x9865f9cfU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x288b9083U), + bswap_32big(0x04cc2ab1U), + bswap_32big(0x3d6f4019U), + bswap_32big(0xa5730b65U)); + } + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40070000U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x980d814cU), bswap_32big(0xfbc29d85U), bswap_32big(0x67765da3U), + bswap_32big(0xe414d83eU)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36t.c new file mode 100644 index 0000000000..42417a73bf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36t.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p36t (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36u.c new file mode 100644 index 0000000000..a9164e88f8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p36u.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p36u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x3e4a5b0aU), + bswap_32big(0x86e515b8U), + bswap_32big(0x6e2da0b9U), + bswap_32big(0xdb0ab66fU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40018020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + r_rsip_func215(); + + r_rsip_func101(bswap_32big(0x89fd046eU), + bswap_32big(0x3d3a5343U), + bswap_32big(0xb32c2678U), + bswap_32big(0x64ef6a51U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3a.c new file mode 100644 index 0000000000..66ac902717 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3a.c @@ -0,0 +1,1913 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p3a (const uint32_t MAX_CNT, uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + uint32_t kLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x003a0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1600H, 0x00000a31U); + for (kLoop = 0U; kLoop < MAX_CNT; kLoop++) + { + WR1_PROG(REG_1444H, 0x00002fb0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_0160H, bswap_32big(0x00030005U)); + WR1_PROG(REG_0164H, bswap_32big(0x0007000bU)); + WR1_PROG(REG_0168H, bswap_32big(0x000d0011U)); + WR1_PROG(REG_016CH, bswap_32big(0x00130017U)); + WR1_PROG(REG_0170H, bswap_32big(0x001d001fU)); + WR1_PROG(REG_0174H, bswap_32big(0x00250029U)); + WR1_PROG(REG_0178H, bswap_32big(0x002b002fU)); + WR1_PROG(REG_017CH, bswap_32big(0x003b003dU)); + WR1_PROG(REG_0180H, bswap_32big(0x00430047U)); + WR1_PROG(REG_0184H, bswap_32big(0x0049004fU)); + WR1_PROG(REG_0188H, bswap_32big(0x00530059U)); + WR1_PROG(REG_018CH, bswap_32big(0x00610065U)); + WR1_PROG(REG_0190H, bswap_32big(0x0067006bU)); + WR1_PROG(REG_0194H, bswap_32big(0x006d0071U)); + WR1_PROG(REG_0198H, bswap_32big(0x007f0083U)); + WR1_PROG(REG_019CH, bswap_32big(0x0089008bU)); + WR1_PROG(REG_01A0H, bswap_32big(0x00950097U)); + WR1_PROG(REG_01A4H, bswap_32big(0x009d00a3U)); + WR1_PROG(REG_01A8H, bswap_32big(0x00a700adU)); + WR1_PROG(REG_01ACH, bswap_32big(0x00b300b5U)); + WR1_PROG(REG_01B0H, bswap_32big(0x00bf00c1U)); + WR1_PROG(REG_01B4H, bswap_32big(0x00c500c7U)); + WR1_PROG(REG_01B8H, bswap_32big(0x00d300dfU)); + WR1_PROG(REG_01BCH, bswap_32big(0x00e300e5U)); + WR1_PROG(REG_01C0H, bswap_32big(0x00e900efU)); + WR1_PROG(REG_01C4H, bswap_32big(0x00f100fbU)); + WR1_PROG(REG_01C8H, bswap_32big(0x01010107U)); + WR1_PROG(REG_01CCH, bswap_32big(0x010d010fU)); + WR1_PROG(REG_01D0H, bswap_32big(0x01150119U)); + WR1_PROG(REG_01D4H, bswap_32big(0x011b0125U)); + WR1_PROG(REG_01D8H, bswap_32big(0x01330137U)); + WR1_PROG(REG_01DCH, bswap_32big(0x0139013dU)); + WR1_PROG(REG_01E0H, bswap_32big(0x014b0151U)); + WR1_PROG(REG_01E4H, bswap_32big(0x015b015dU)); + WR1_PROG(REG_01E8H, bswap_32big(0x01610167U)); + WR1_PROG(REG_01ECH, bswap_32big(0x016f0175U)); + WR1_PROG(REG_01F0H, bswap_32big(0x017b017fU)); + WR1_PROG(REG_01F4H, bswap_32big(0x0185018dU)); + WR1_PROG(REG_01F8H, bswap_32big(0x01910199U)); + WR1_PROG(REG_01FCH, bswap_32big(0x01a301a5U)); + WR1_PROG(REG_0200H, bswap_32big(0x01af01b1U)); + WR1_PROG(REG_0204H, bswap_32big(0x01b701bbU)); + WR1_PROG(REG_0208H, bswap_32big(0x01c101c9U)); + WR1_PROG(REG_020CH, bswap_32big(0x01cd01cfU)); + WR1_PROG(REG_0210H, bswap_32big(0x01d301dfU)); + WR1_PROG(REG_0214H, bswap_32big(0x01e701ebU)); + WR1_PROG(REG_0218H, bswap_32big(0x01f301f7U)); + WR1_PROG(REG_021CH, bswap_32big(0x01fd0000U)); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x000000c0U); + WR1_PROG(REG_1608H, 0x80b00006U); + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x034300c1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x059b108aU), bswap_32big(0x33cf2d7aU), bswap_32big(0xb0dfe72aU), + bswap_32big(0x3c2a6079U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000d01fU); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x00c90011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000028U); + WR1_PROG(REG_1600H, 0x000008e7U); + + for (iLoop = 0U; iLoop < 40U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x25a8a496U), bswap_32big(0x3315ed01U), bswap_32big(0x15e94de1U), + bswap_32big(0xb3f2277eU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x76645b97U), bswap_32big(0x50783d97U), bswap_32big(0xb60f25a0U), + bswap_32big(0xa04303e0U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x354e8599U), bswap_32big(0x95a30707U), bswap_32big(0x5b026884U), + bswap_32big(0xcec81672U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000d060U); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1400H, 0x00c90011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x00002fb0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_0980H, bswap_32big(0xB51EB851U)); + WR1_PROG(REG_0984H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0988H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_098CH, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0990H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0994H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0998H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_099CH, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09A0H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09A4H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09A8H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09ACH, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09B0H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09B4H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09B8H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09BCH, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09C0H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09C4H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09C8H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09CCH, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09D0H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09D4H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09D8H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09DCH, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09E0H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09E4H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09E8H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09ECH, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09F0H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09F4H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09F8H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09FCH, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0A00H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0A04H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0A08H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0A0CH, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0A10H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0A14H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0A18H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0A1CH, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0A20H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0A24H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0A28H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0A2CH, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0A30H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0A34H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0A38H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0A3CH, bswap_32big(0x51EB851EU)); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xe27795b3U), bswap_32big(0x24fd2d0aU), bswap_32big(0xba146712U), + bswap_32big(0xad37a529U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x68dae7acU), bswap_32big(0xc7ea0e80U), bswap_32big(0x6044ec52U), + bswap_32big(0x2fcec170U)); + continue; + } + else + { + r_rsip_func101(bswap_32big(0x2f7de89cU), bswap_32big(0x72744d2bU), bswap_32big(0x1163d3d8U), + bswap_32big(0x1fa026f4U)); + } + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xb88ad10eU), bswap_32big(0x6313044cU), bswap_32big(0xa325bbe7U), + bswap_32big(0x390bc221U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xe18e6709U), bswap_32big(0x6ff7d55cU), bswap_32big(0x6619c490U), + bswap_32big(0x50b5cdb7U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000320U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x58fb63d4U), + bswap_32big(0x41f867aaU), + bswap_32big(0x6bf41c65U), + bswap_32big(0xae1d756cU)); + } + else + { + r_rsip_func101(bswap_32big(0x8032ee5cU), + bswap_32big(0xfcb2f2efU), + bswap_32big(0x572ea8ffU), + bswap_32big(0xd7a91f9aU)); + } + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x00000000U), + bswap_32big(0x00000000U), + bswap_32big(0x00000000U), + bswap_32big(0x10000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c000b1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x4294f345U), bswap_32big(0xecd8fbeeU), bswap_32big(0x4a0d9c49U), + bswap_32big(0xa59a600dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xb77a0070U), + bswap_32big(0xbcbb75acU), + bswap_32big(0xcef06570U), + bswap_32big(0x47776768U)); + continue; + } + else + { + r_rsip_func101(bswap_32big(0x1189a973U), + bswap_32big(0xe16006c4U), + bswap_32big(0x7729730cU), + bswap_32big(0xcfb61435U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x991ecbb5U), bswap_32big(0xce763731U), bswap_32big(0x421f3cdfU), + bswap_32big(0x02ff26ffU)); + } + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x000000c0U); + WR1_PROG(REG_1600H, 0x0000094aU); + + for (iLoop = 0U; iLoop < 95U; iLoop++) + { + WR1_PROG(REG_1600H, 0x01003906U); + WR1_PROG(REG_1600H, 0x00002cc0U); + WR1_PROG(REG_1600H, 0x00002cc0U); + WR1_PROG(REG_1608H, 0x81010100U); + + WR1_PROG(REG_1404H, 0x15700000U); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x18180010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x18180004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xabcfc090U), bswap_32big(0xe795b5b0U), bswap_32big(0x1cedefb2U), + bswap_32big(0x06863ad4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000d140U); + + r_rsip_func101(bswap_32big(0xf9b28b9eU), + bswap_32big(0xc3707843U), + bswap_32big(0xca2e9380U), + bswap_32big(0xf731c7a9U)); + break; + } + else + { + r_rsip_func101(bswap_32big(0xadab0528U), + bswap_32big(0x92420ba3U), + bswap_32big(0xb95376b8U), + bswap_32big(0xfb595eeaU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xea9e2b61U), bswap_32big(0x2353eae0U), bswap_32big(0x188169dfU), + bswap_32big(0x95b764a5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x58579309U), bswap_32big(0xe1975acfU), bswap_32big(0x18127cbcU), + bswap_32big(0x5ddc6536U)); + continue; + } + + WR1_PROG(REG_1404H, 0x18780000U); + WR1_PROG(REG_1400H, 0x00c000c1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x15700000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00010001U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x18180010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x18180004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xecd29870U), bswap_32big(0x567079e5U), bswap_32big(0xe422e128U), + bswap_32big(0x9eb22d32U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x4d35366fU), bswap_32big(0x4a73afd6U), bswap_32big(0x1b8d0bf5U), + bswap_32big(0xd09d4423U)); + } + else + { + r_rsip_func100(bswap_32big(0xbb09a539U), bswap_32big(0x8a0b7a57U), bswap_32big(0x4a96229fU), + bswap_32big(0x581de666U)); + WR1_PROG(REG_1404H, 0x17780000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000428U); + + WR1_PROG(REG_1004H, 0x18180010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x18180000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x119fc6caU), bswap_32big(0x886abd9eU), bswap_32big(0x6c0b8187U), + bswap_32big(0x30252fa7U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xb371d3b4U), + bswap_32big(0x7ffc3d0fU), + bswap_32big(0x50b47a84U), + bswap_32big(0x9e308558U)); + continue; + } + + r_rsip_func100(bswap_32big(0x64000d05U), bswap_32big(0x2d83b1bcU), bswap_32big(0x8d4ab7d4U), + bswap_32big(0x4697f269U)); + + WR1_PROG(REG_1600H, 0x0000b560U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x0000094aU); + WR1_PROG(REG_1608H, 0x80b0000aU); + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x034300c1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000929U); + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x000000bcU); + + for (iLoop = 0U; iLoop < 48U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000038e6U); + WR1_PROG(REG_1600H, 0x0000a8c0U); + WR1_PROG(REG_1600H, 0x00000004U); + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1600H, 0x11816907U); + + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10002d20U); + + WR1_PROG(REG_1600H, 0x000168e7U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010120U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WR1_PROG(REG_1600H, 0x000037e9U); + + WR1_PROG(REG_1404H, 0x15700000U); + WR1_PROG(REG_1600H, 0x0000094aU); + WR1_PROG(REG_1608H, 0x81b0000aU); + WR1_PROG(REG_1400H, 0x00c900c1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1818000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x000033e0U); + + r_rsip_func101(bswap_32big(0xff8824bbU), + bswap_32big(0x938a0094U), + bswap_32big(0x98793950U), + bswap_32big(0x31af1027U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007c1fU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xc2613d0cU), bswap_32big(0x63ff1dffU), bswap_32big(0x40a844bdU), + bswap_32big(0x578c7455U)); + WR1_PROG(REG_1600H, 0x00000a52U); + + WR1_PROG(REG_1608H, 0x81010160U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x11600000U); + for (jLoop = 0U; jLoop < 48U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a04U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3d58d2fcU), + bswap_32big(0xe20a94eaU), + bswap_32big(0xac4625b4U), + bswap_32big(0xae567f62U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x645566d4U), + bswap_32big(0x489f6c01U), + bswap_32big(0x6a20dea6U), + bswap_32big(0xdc691831U)); + jLoop = jLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x2861afb2U), + bswap_32big(0xd011d257U), + bswap_32big(0xc75fd5c9U), + bswap_32big(0x93e9f032U)); + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000004U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000838U); + + WR1_PROG(REG_1004H, 0x18180010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x18180004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x17780000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000428U); + + WR1_PROG(REG_1004H, 0x18180010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x18180000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x1f157361U), + bswap_32big(0xf409a574U), + bswap_32big(0x26408614U), + bswap_32big(0xf8822277U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 0)) + { + WR1_PROG(REG_1600H, 0x00002e40U); + + r_rsip_func101(bswap_32big(0x1d43f9b3U), + bswap_32big(0xc1e4e0b8U), + bswap_32big(0xb8b8ceaeU), + bswap_32big(0xfc2ff268U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000094aU); + + r_rsip_func100(bswap_32big(0x03591a67U), + bswap_32big(0x992c8e0fU), + bswap_32big(0x682f6cc0U), + bswap_32big(0xf54e0af5U)); + WR1_PROG(REG_1608H, 0x81010120U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + WR1_PROG(REG_1600H, 0x000037e9U); + + for (jLoop = 0U; jLoop < S_RAM[0 + 1]; jLoop++) + { + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1608H, 0x81b0000aU); + WR1_PROG(REG_1400H, 0x00c900c1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x37f3161bU), + bswap_32big(0xf0026a71U), + bswap_32big(0xfe04bf66U), + bswap_32big(0xa1955ae4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 0)) + { + WR1_PROG(REG_1600H, 0x00002e40U); + + r_rsip_func101(bswap_32big(0x5fcd951fU), + bswap_32big(0x60b609aeU), + bswap_32big(0xbc6949ebU), + bswap_32big(0xb2112e26U)); + break; + } + else + { + r_rsip_func100(bswap_32big(0x00511a68U), + bswap_32big(0x8e080e33U), + bswap_32big(0x38626ffdU), + bswap_32big(0xccb16717U)); + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x18180000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x04aeebc1U), + bswap_32big(0x8d30a29aU), + bswap_32big(0xd5aad5a6U), + bswap_32big(0x17bd7135U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008a40U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x73fbb88dU), + bswap_32big(0xdf3efe15U), + bswap_32big(0x03068327U), + bswap_32big(0x2e0a569cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xb58f1b0aU), + bswap_32big(0x033a71ecU), + bswap_32big(0xe5927baaU), + bswap_32big(0xdaf40ecdU)); + break; + } + else + { + r_rsip_func101(bswap_32big(0xb8dfbbacU), + bswap_32big(0x15bf38e5U), + bswap_32big(0x966e0c86U), + bswap_32big(0x123f036fU)); + } + } + } + + WR1_PROG(REG_1600H, 0x38000a4bU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x367e74f9U), bswap_32big(0xb080ecf7U), bswap_32big(0xf7565210U), + bswap_32big(0x1fcea309U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00002e20U); + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x6a335ea5U), + bswap_32big(0xe60fea76U), + bswap_32big(0x379fa5beU), + bswap_32big(0x9e430b5dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xe295a76dU), + bswap_32big(0x06a57f61U), + bswap_32big(0x533a3207U), + bswap_32big(0x66a705c1U)); + break; + } + else + { + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000320U); + + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x78308bb4U), + bswap_32big(0x03da16f3U), + bswap_32big(0xf77ee47aU), + bswap_32big(0x5f42157bU)); + } + } + else + { + r_rsip_func101(bswap_32big(0x0e03bb03U), + bswap_32big(0xec40616bU), + bswap_32big(0xa00da835U), + bswap_32big(0xb585c421U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x0b36589dU), + bswap_32big(0x16c7d192U), + bswap_32big(0x1451d3c4U), + bswap_32big(0xed17dec2U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x55375e52U), bswap_32big(0xb650783cU), bswap_32big(0xa9abff0dU), + bswap_32big(0x484622a4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1400H, 0x00c000c1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000778U); + + WR1_PROG(REG_1004H, 0x18180009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a05U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x30676847U), + bswap_32big(0x0efa16b1U), + bswap_32big(0x5676ffebU), + bswap_32big(0x0a762bf7U)); + r_rsip_func113(); + + r_rsip_func100(bswap_32big(0xfd2b8c80U), + bswap_32big(0x7e644763U), + bswap_32big(0xd1bf98efU), + bswap_32big(0xdbf9b4b8U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c2000c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xc9690989U)); + + OFS_ADR = 516; + + WR1_PROG(REG_1404H, 0x16b80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0e77e8bbU), + bswap_32big(0x874d8e30U), + bswap_32big(0x5e1951dbU), + bswap_32big(0x07f8bbb8U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8260270cU), + bswap_32big(0x90e434d5U), + bswap_32big(0xf947b5e6U), + bswap_32big(0x02e88732U)); + r_rsip_func313(); + + WR1_PROG(REG_1404H, 0x14a00000U); + WR1_PROG(REG_1400H, 0x00c000d1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xc9690989U)); + + OFS_ADR = 516; + + WR1_PROG(REG_1404H, 0x16b80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8d078eeaU), + bswap_32big(0xf26917adU), + bswap_32big(0x5b288572U), + bswap_32big(0xc9e03745U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1014H, 0x00000778U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x18180007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x36b45b14U), + bswap_32big(0x87ffe652U), + bswap_32big(0xb1807ea7U), + bswap_32big(0x380ce692U)); + r_rsip_func315(); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xa5cd5aaaU), + bswap_32big(0x14c9cb10U), + bswap_32big(0x8a0cc2bbU), + bswap_32big(0x5bf4a219U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x15080d2bU), bswap_32big(0xe2fadddfU), bswap_32big(0x252e6cc5U), + bswap_32big(0xc06338e0U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xc9690989U)); + + OFS_ADR = 516; + + WR1_PROG(REG_1404H, 0x12a80000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x89105415U), + bswap_32big(0xf94dc8e1U), + bswap_32big(0xd0141a2aU), + bswap_32big(0x22b3c270U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1014H, 0x00000368U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x18180007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xc9690989U)); + + OFS_ADR = 516; + + WR1_PROG(REG_1404H, 0x14b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8f8c5983U), + bswap_32big(0xd54250fcU), + bswap_32big(0x65533cfaU), + bswap_32big(0x299284dfU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000bdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000368U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x1818000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x18180007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x30300010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x30300002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x30300003U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x30300002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14b00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00010001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc067acddU), + bswap_32big(0x56056f00U), + bswap_32big(0x483179feU), + bswap_32big(0x508e8eefU)); + r_rsip_func315(); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x88a339c7U), + bswap_32big(0x70f930fbU), + bswap_32big(0x95ff6462U), + bswap_32big(0x1b3c2de9U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x19debb06U), bswap_32big(0x17f8916aU), bswap_32big(0xd5d4e917U), + bswap_32big(0x5808c9a1U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1400H, 0x00c00181U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x30300009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0xc9690989U)); + + OFS_ADR = 516; + + WR1_PROG(REG_1404H, 0x14b00000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a0fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x316af1c2U), + bswap_32big(0x9e922c9aU), + bswap_32big(0x27e9da7aU), + bswap_32big(0xb58403d6U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x00010001U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a06U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3d199572U), + bswap_32big(0x44312b67U), + bswap_32big(0x05f7868dU), + bswap_32big(0x61fa46ddU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xad23284dU), + bswap_32big(0xae5cab69U), + bswap_32big(0xe02a6297U), + bswap_32big(0xe46b854bU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000fU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc2326d5eU), + bswap_32big(0x6a1b2be0U), + bswap_32big(0x404b33e3U), + bswap_32big(0x413f750dU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x14b00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xe08debdcU), bswap_32big(0xb04a7508U), bswap_32big(0x211b9fa9U), + bswap_32big(0x65fc1ceeU)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[1 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x95b1e6a0U), bswap_32big(0x44aebdbeU), bswap_32big(0xa1a24bb9U), + bswap_32big(0x9962a590U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x12a80000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xba0c3c8aU), bswap_32big(0xeb1a4571U), bswap_32big(0xc9fd36b5U), + bswap_32big(0xbcc17725U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[97 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x83e4efd3U), bswap_32big(0x4ece69baU), bswap_32big(0x233b2912U), + bswap_32big(0xbcbbda92U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x9f7950e9U), + bswap_32big(0x3d3eaa6cU), + bswap_32big(0xbaa42762U), + bswap_32big(0x433b3ac5U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[193]); + + r_rsip_func100(bswap_32big(0x2f36ed17U), + bswap_32big(0x6aff61d7U), + bswap_32big(0xc76cf2feU), + bswap_32big(0x8a210309U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a07U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0bdd40ccU), + bswap_32big(0xff6b7a40U), + bswap_32big(0x9a911737U), + bswap_32big(0x941f54daU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xda7cf8c4U), + bswap_32big(0x8556b916U), + bswap_32big(0xeac9be31U), + bswap_32big(0x99e5c625U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000eU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003a02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7367caf9U), + bswap_32big(0x9ed8f8c3U), + bswap_32big(0x24fb0e8fU), + bswap_32big(0xbb47aa94U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x14b00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xeb27ee72U), bswap_32big(0x965385ffU), bswap_32big(0x61eeb388U), + bswap_32big(0x7896e9b6U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[1 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0xe3c918dfU), bswap_32big(0x6fa2b2e8U), bswap_32big(0x394cdc83U), + bswap_32big(0xd1aa66b4U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x472b0262U), + bswap_32big(0x1b762b22U), + bswap_32big(0xcda17f80U), + bswap_32big(0x61826dccU)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008104U); + WR1_PROG(REG_1608H, 0x81010280U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[97]); + + r_rsip_func100(bswap_32big(0x5dc61d38U), + bswap_32big(0xc47387c5U), + bswap_32big(0xe719331fU), + bswap_32big(0xcf28cb5aU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[101]); + + r_rsip_func100(bswap_32big(0x900ba014U), + bswap_32big(0x7f8b85fbU), + bswap_32big(0x888a1d71U), + bswap_32big(0x0bdf52e6U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + r_rsip_func102(bswap_32big(0x5a4d3c3eU), + bswap_32big(0x87a7ed15U), + bswap_32big(0xd502b61aU), + bswap_32big(0x06c13f95U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3b.c new file mode 100644 index 0000000000..20acdcfcf8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3b.c @@ -0,0 +1,1945 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p3b (const uint32_t MAX_CNT, uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + uint32_t kLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x003b0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1600H, 0x00000a31U); + for (kLoop = 0U; kLoop < MAX_CNT; kLoop++) + { + WR1_PROG(REG_1444H, 0x00002fb0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_0160H, bswap_32big(0x00030005U)); + WR1_PROG(REG_0164H, bswap_32big(0x0007000bU)); + WR1_PROG(REG_0168H, bswap_32big(0x000d0011U)); + WR1_PROG(REG_016CH, bswap_32big(0x00130017U)); + WR1_PROG(REG_0170H, bswap_32big(0x001d001fU)); + WR1_PROG(REG_0174H, bswap_32big(0x00250029U)); + WR1_PROG(REG_0178H, bswap_32big(0x002b002fU)); + WR1_PROG(REG_017CH, bswap_32big(0x003b003dU)); + WR1_PROG(REG_0180H, bswap_32big(0x00430047U)); + WR1_PROG(REG_0184H, bswap_32big(0x0049004fU)); + WR1_PROG(REG_0188H, bswap_32big(0x00530059U)); + WR1_PROG(REG_018CH, bswap_32big(0x00610065U)); + WR1_PROG(REG_0190H, bswap_32big(0x0067006bU)); + WR1_PROG(REG_0194H, bswap_32big(0x006d0071U)); + WR1_PROG(REG_0198H, bswap_32big(0x007f0083U)); + WR1_PROG(REG_019CH, bswap_32big(0x0089008bU)); + WR1_PROG(REG_01A0H, bswap_32big(0x00950097U)); + WR1_PROG(REG_01A4H, bswap_32big(0x009d00a3U)); + WR1_PROG(REG_01A8H, bswap_32big(0x00a700adU)); + WR1_PROG(REG_01ACH, bswap_32big(0x00b300b5U)); + WR1_PROG(REG_01B0H, bswap_32big(0x00bf00c1U)); + WR1_PROG(REG_01B4H, bswap_32big(0x00c500c7U)); + WR1_PROG(REG_01B8H, bswap_32big(0x00d300dfU)); + WR1_PROG(REG_01BCH, bswap_32big(0x00e300e5U)); + WR1_PROG(REG_01C0H, bswap_32big(0x00e900efU)); + WR1_PROG(REG_01C4H, bswap_32big(0x00f100fbU)); + WR1_PROG(REG_01C8H, bswap_32big(0x01010107U)); + WR1_PROG(REG_01CCH, bswap_32big(0x010d010fU)); + WR1_PROG(REG_01D0H, bswap_32big(0x01150119U)); + WR1_PROG(REG_01D4H, bswap_32big(0x011b0125U)); + WR1_PROG(REG_01D8H, bswap_32big(0x01330137U)); + WR1_PROG(REG_01DCH, bswap_32big(0x0139013dU)); + WR1_PROG(REG_01E0H, bswap_32big(0x014b0151U)); + WR1_PROG(REG_01E4H, bswap_32big(0x015b015dU)); + WR1_PROG(REG_01E8H, bswap_32big(0x01610167U)); + WR1_PROG(REG_01ECH, bswap_32big(0x016f0175U)); + WR1_PROG(REG_01F0H, bswap_32big(0x017b017fU)); + WR1_PROG(REG_01F4H, bswap_32big(0x0185018dU)); + WR1_PROG(REG_01F8H, bswap_32big(0x01910199U)); + WR1_PROG(REG_01FCH, bswap_32big(0x01a301a5U)); + WR1_PROG(REG_0200H, bswap_32big(0x01af01b1U)); + WR1_PROG(REG_0204H, bswap_32big(0x01b701bbU)); + WR1_PROG(REG_0208H, bswap_32big(0x01c101c9U)); + WR1_PROG(REG_020CH, bswap_32big(0x01cd01cfU)); + WR1_PROG(REG_0210H, bswap_32big(0x01d301dfU)); + WR1_PROG(REG_0214H, bswap_32big(0x01e701ebU)); + WR1_PROG(REG_0218H, bswap_32big(0x01f301f7U)); + WR1_PROG(REG_021CH, bswap_32big(0x01fd0000U)); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x000000c0U); + WR1_PROG(REG_1608H, 0x80b00006U); + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x034300c1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2fc1e1cfU), bswap_32big(0x23797578U), bswap_32big(0x8e47bcedU), + bswap_32big(0x846b3dbaU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000d01fU); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1400H, 0x00c90011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000038U); + WR1_PROG(REG_1600H, 0x000008e7U); + + for (iLoop = 0U; iLoop < 56U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x60b27d92U), bswap_32big(0xbe9d23abU), bswap_32big(0x897293e6U), + bswap_32big(0xa7b4b582U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x05101202U), bswap_32big(0x27fe0d14U), bswap_32big(0x7f440cbcU), + bswap_32big(0xaf4c7cc2U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x74df1227U), bswap_32big(0x5d58d46fU), bswap_32big(0xdfdfeedfU), + bswap_32big(0x24a350adU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x0000d060U); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1400H, 0x00c90011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x00003fb0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_0940H, bswap_32big(0xB51EB851U)); + WR1_PROG(REG_0944H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0948H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_094CH, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0950H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0954H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0958H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_095CH, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0960H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0964H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0968H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_096CH, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0970H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0974H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0978H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_097CH, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0980H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0984H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0988H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_098CH, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0990H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0994H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0998H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_099CH, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09A0H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09A4H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09A8H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09ACH, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09B0H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09B4H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09B8H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09BCH, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09C0H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09C4H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09C8H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09CCH, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09D0H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09D4H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09D8H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09DCH, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09E0H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09E4H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09E8H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_09ECH, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_09F0H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_09F4H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_09F8H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_09FCH, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0A00H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0A04H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0A08H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0A0CH, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0A10H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0A14H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0A18H, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0A1CH, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0A20H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0A24H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0A28H, bswap_32big(0xB851EB85U)); + WR1_PROG(REG_0A2CH, bswap_32big(0x1EB851EBU)); + WR1_PROG(REG_0A30H, bswap_32big(0x851EB851U)); + WR1_PROG(REG_0A34H, bswap_32big(0xEB851EB8U)); + WR1_PROG(REG_0A38H, bswap_32big(0x51EB851EU)); + WR1_PROG(REG_0A3CH, bswap_32big(0xB851EB85U)); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xc97748faU), bswap_32big(0xab884819U), bswap_32big(0x9b85f9acU), + bswap_32big(0x38955739U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xdf9a48a5U), bswap_32big(0xe6e71d7bU), bswap_32big(0x3505f1e3U), + bswap_32big(0x5c861a45U)); + continue; + } + else + { + r_rsip_func101(bswap_32big(0x0813b602U), bswap_32big(0xc87e6c80U), bswap_32big(0xe094433bU), + bswap_32big(0x9cf2adffU)); + } + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x3ba6e686U), bswap_32big(0x626c44f4U), bswap_32big(0x9bf1beecU), + bswap_32big(0x77a633c8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x74f3a65dU), bswap_32big(0x1848676eU), bswap_32big(0x8a28c37aU), + bswap_32big(0x9a274586U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000320U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xbbb1a687U), + bswap_32big(0x82e66be3U), + bswap_32big(0x7d8b5f5cU), + bswap_32big(0x457c201eU)); + } + else + { + r_rsip_func101(bswap_32big(0x732839fdU), + bswap_32big(0xe4c1b727U), + bswap_32big(0xaa9b81e6U), + bswap_32big(0x4de5d5b9U)); + } + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, + bswap_32big(0x00000000U), + bswap_32big(0x00000000U), + bswap_32big(0x00000000U), + bswap_32big(0x10000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x79334c80U), bswap_32big(0x0b4dee97U), bswap_32big(0x8129b330U), + bswap_32big(0x04176892U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x9b4cb7fcU), + bswap_32big(0x384a7416U), + bswap_32big(0x221b74fcU), + bswap_32big(0x16621e18U)); + continue; + } + else + { + r_rsip_func101(bswap_32big(0xbb9be7b4U), + bswap_32big(0xbe40177dU), + bswap_32big(0x6e845b37U), + bswap_32big(0x1fc001baU)); + } + } + else + { + r_rsip_func101(bswap_32big(0xe1c7b987U), bswap_32big(0x5d733990U), bswap_32big(0x6b3226b0U), + bswap_32big(0xe6645d86U)); + } + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x000000c0U); + WR1_PROG(REG_1600H, 0x0000094aU); + + for (iLoop = 0U; iLoop < 95U; iLoop++) + { + WR1_PROG(REG_1600H, 0x01003906U); + WR1_PROG(REG_1600H, 0x00002cc0U); + WR1_PROG(REG_1600H, 0x00002cc0U); + WR1_PROG(REG_1608H, 0x81010100U); + + WR1_PROG(REG_1404H, 0x15300000U); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x0f6a6285U), bswap_32big(0x0ab5fc1bU), bswap_32big(0x5ccbaf23U), + bswap_32big(0xa9d5db6eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000d140U); + + r_rsip_func101(bswap_32big(0xb8394cf3U), + bswap_32big(0x7d8048d4U), + bswap_32big(0x7781eb32U), + bswap_32big(0x719c9025U)); + break; + } + else + { + r_rsip_func101(bswap_32big(0xcfb15a84U), + bswap_32big(0x8f5b0ef6U), + bswap_32big(0x0a648675U), + bswap_32big(0x018207ebU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x339aee89U), bswap_32big(0x8f9281f7U), bswap_32big(0xc1ae3ffaU), + bswap_32big(0x8a2a8345U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xad24540eU), bswap_32big(0x34c5cc9bU), bswap_32big(0x312d5413U), + bswap_32big(0x1a09a2bcU)); + continue; + } + + WR1_PROG(REG_1404H, 0x18380000U); + WR1_PROG(REG_1400H, 0x00c00101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000428U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x15300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00010001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xcbe3691cU), bswap_32big(0x3d37eecdU), bswap_32big(0x2cbf8f32U), + bswap_32big(0xb6558f40U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x7c285b39U), bswap_32big(0xd94fe5fcU), bswap_32big(0x2ced59f3U), + bswap_32big(0x9d597440U)); + } + else + { + r_rsip_func100(bswap_32big(0xddacf41fU), bswap_32big(0x8dd867daU), bswap_32big(0xa5bcb447U), + bswap_32big(0xa1a3368cU)); + WR1_PROG(REG_1404H, 0x17380000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000428U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xbefabb5cU), bswap_32big(0x56de6de1U), bswap_32big(0x3172e3c0U), + bswap_32big(0x7ba2c65cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xa24b7be6U), + bswap_32big(0x7339b2c7U), + bswap_32big(0x5b215e79U), + bswap_32big(0x54ebc466U)); + continue; + } + + r_rsip_func100(bswap_32big(0x440ad503U), bswap_32big(0xb865ceafU), bswap_32big(0x9cf41037U), + bswap_32big(0x7dfedf87U)); + + WR1_PROG(REG_1600H, 0x0000b560U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x0000094aU); + WR1_PROG(REG_1608H, 0x80c0000aU); + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1400H, 0x03430101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000929U); + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x000000fcU); + + for (iLoop = 0U; iLoop < 64U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000038e6U); + WR1_PROG(REG_1600H, 0x0000a8c0U); + WR1_PROG(REG_1600H, 0x00000004U); + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1600H, 0x11816907U); + + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10002d20U); + + WR1_PROG(REG_1600H, 0x000168e7U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010120U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WR1_PROG(REG_1600H, 0x000037e9U); + + WR1_PROG(REG_1404H, 0x15300000U); + WR1_PROG(REG_1600H, 0x0000094aU); + WR1_PROG(REG_1608H, 0x81c0000aU); + WR1_PROG(REG_1400H, 0x00c90101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x000033e0U); + + r_rsip_func101(bswap_32big(0xf4c051cdU), + bswap_32big(0x85faeffdU), + bswap_32big(0x11f39e9cU), + bswap_32big(0x68ca93caU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007c1fU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xaa2f3502U), bswap_32big(0x2e7d6e14U), bswap_32big(0xf5d25804U), + bswap_32big(0x637fb462U)); + WR1_PROG(REG_1600H, 0x00000a52U); + + WR1_PROG(REG_1608H, 0x81010160U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (jLoop = 0U; jLoop < 64U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b04U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8974bbd1U), + bswap_32big(0x456aeee3U), + bswap_32big(0xfefddb03U), + bswap_32big(0xf7ee3065U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0xd23841ccU), + bswap_32big(0x0b85fcb8U), + bswap_32big(0x5900c61cU), + bswap_32big(0x2013006eU)); + jLoop = jLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xc7fd0ed7U), + bswap_32big(0xccd04254U), + bswap_32big(0x5caa8a30U), + bswap_32big(0xc87ab93fU)); + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000004U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_101CH, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x20200004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x17380000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000428U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000630U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x7af3ef3dU), + bswap_32big(0x501e059eU), + bswap_32big(0xbd913ac0U), + bswap_32big(0xf6206e97U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 0)) + { + WR1_PROG(REG_1600H, 0x00002e40U); + + r_rsip_func101(bswap_32big(0xb81f3c12U), + bswap_32big(0xfabc508fU), + bswap_32big(0x2ebd007eU), + bswap_32big(0xe9279829U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000094aU); + + r_rsip_func100(bswap_32big(0xda07bc27U), + bswap_32big(0xaa7b7215U), + bswap_32big(0x5a56c5cbU), + bswap_32big(0x39a236cdU)); + WR1_PROG(REG_1608H, 0x81010120U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + WR1_PROG(REG_1600H, 0x000037e9U); + + for (jLoop = 0U; jLoop < S_RAM[0 + 1]; jLoop++) + { + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1608H, 0x81c0000aU); + WR1_PROG(REG_1400H, 0x00c90101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000838U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x4a92d88fU), + bswap_32big(0x71beda31U), + bswap_32big(0x675a2e4dU), + bswap_32big(0x2cbb75d8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 0)) + { + WR1_PROG(REG_1600H, 0x00002e40U); + + r_rsip_func101(bswap_32big(0xf05b995fU), + bswap_32big(0xef88e2d4U), + bswap_32big(0x7eb27f3aU), + bswap_32big(0xaa63d751U)); + break; + } + else + { + r_rsip_func100(bswap_32big(0xe8e2cf85U), + bswap_32big(0x528ef2f8U), + bswap_32big(0x1761cd5cU), + bswap_32big(0x3c4bd2e8U)); + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_101CH, 0x00000428U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x20200000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xdecb8abeU), + bswap_32big(0x1cb92eabU), + bswap_32big(0x79853ce1U), + bswap_32big(0xbc388166U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008a40U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd9ecd517U), + bswap_32big(0xf99dbecbU), + bswap_32big(0xc2dbd955U), + bswap_32big(0x9ccc3bceU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xdf36d6a6U), + bswap_32big(0x880a7c8eU), + bswap_32big(0xc6657bdeU), + bswap_32big(0xf65aee7cU)); + break; + } + else + { + r_rsip_func101(bswap_32big(0x7acff248U), + bswap_32big(0x8366309bU), + bswap_32big(0x0c1b9eb5U), + bswap_32big(0x8dd52387U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38000a4bU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x765635b4U), bswap_32big(0xd2820434U), bswap_32big(0x7fc0b664U), + bswap_32big(0x90cf302eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00002e20U); + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd5601d34U), + bswap_32big(0xe1de9099U), + bswap_32big(0x04392bb1U), + bswap_32big(0xdaa4151bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0x069e5338U), + bswap_32big(0x02450d07U), + bswap_32big(0x7d3f34a8U), + bswap_32big(0x32d9fd1fU)); + break; + } + else + { + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000938U); + WR1_PROG(REG_1020H, 0x00000320U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xab33dde8U), + bswap_32big(0x9e2bf4f3U), + bswap_32big(0x7784a8ffU), + bswap_32big(0x88a39058U)); + } + } + else + { + r_rsip_func101(bswap_32big(0xaf8b4143U), + bswap_32big(0xc2a4d2faU), + bswap_32big(0x47126475U), + bswap_32big(0x3ce7f66bU)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008a20U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xaf77d897U), + bswap_32big(0x35892c72U), + bswap_32big(0x426f53abU), + bswap_32big(0xac579fd0U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd043e820U), bswap_32big(0x89c7fb14U), bswap_32big(0xe944a3b5U), + bswap_32big(0xa7a4b951U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1400H, 0x00c00101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000738U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b05U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfe9e64e4U), + bswap_32big(0x722b100dU), + bswap_32big(0x6e831b5cU), + bswap_32big(0xab76c28dU)); + r_rsip_func113(); + + r_rsip_func100(bswap_32big(0xfac3916eU), + bswap_32big(0x007aeb65U), + bswap_32big(0x2d3a8d6eU), + bswap_32big(0xe04a7c35U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c2000c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x360905f3U)); + + OFS_ADR = 808; + + WR1_PROG(REG_1404H, 0x16380000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6c59c3e9U), + bswap_32big(0xff39b0a1U), + bswap_32big(0x80ce95aaU), + bswap_32big(0xbb628179U)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000320U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000220U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000428U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000630U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4cb5bf94U), + bswap_32big(0xc862ac8aU), + bswap_32big(0x688ce218U), + bswap_32big(0xa438740dU)); + r_rsip_func054(); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1400H, 0x00c00101U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000660U); + + WR1_PROG(REG_1004H, 0x20200009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000dc0U); + + WR1_PROG(REG_1404H, 0x14500000U); + WR1_PROG(REG_1400H, 0x00c00111U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x360905f3U)); + + OFS_ADR = 808; + + WR1_PROG(REG_1404H, 0x16780000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xba7ce631U), + bswap_32big(0x2f615e20U), + bswap_32big(0x0c448cb2U), + bswap_32big(0x57c85c63U)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1014H, 0x00000778U); + WR1_PROG(REG_1018H, 0x00000878U); + WR1_PROG(REG_1020H, 0x00000230U); + + WR1_PROG(REG_1004H, 0x20200007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xede19902U), + bswap_32big(0x622636f0U), + bswap_32big(0x12ae68b1U), + bswap_32big(0x6a701ecaU)); + r_rsip_func321(); + + WR1_PROG(REG_1404H, 0x18900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000a90U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a90U); + WR1_PROG(REG_1018H, 0x00000660U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x92dcf757U), + bswap_32big(0xf576443fU), + bswap_32big(0xb35cef75U), + bswap_32big(0xdec1ecaaU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x57fca3a9U), bswap_32big(0x6469b8afU), bswap_32big(0x1c921ed4U), + bswap_32big(0xd58983ceU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x360905f3U)); + + OFS_ADR = 808; + + WR1_PROG(REG_1404H, 0x12480000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0ba82be5U), + bswap_32big(0x4c795556U), + bswap_32big(0x51bc5ebfU), + bswap_32big(0xc947aa3dU)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1014H, 0x00000348U); + WR1_PROG(REG_1018H, 0x00000448U); + WR1_PROG(REG_1020H, 0x00000660U); + + WR1_PROG(REG_1004H, 0x20200007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x360905f3U)); + + OFS_ADR = 808; + + WR1_PROG(REG_1404H, 0x14600000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa15ef1f3U), + bswap_32big(0xce8ed8ceU), + bswap_32big(0x4f4c7bd0U), + bswap_32big(0xa0a1cd2eU)); + r_rsip_func016(OFS_ADR); + + WR1_PROG(REG_1404H, 0x19900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000448U); + WR1_PROG(REG_1018H, 0x00000a90U); + WR1_PROG(REG_1020H, 0x00000230U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000348U); + WR1_PROG(REG_1018H, 0x00000a90U); + WR1_PROG(REG_1020H, 0x00000130U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000130U); + WR1_PROG(REG_1018H, 0x00000230U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x20200007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000660U); + + WR1_PROG(REG_1004H, 0x40400010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000448U); + WR1_PROG(REG_1018H, 0x00000878U); + WR1_PROG(REG_101CH, 0x00000660U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x40400002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_101CH, 0x00000660U); + WR1_PROG(REG_1020H, 0x00000230U); + + WR1_PROG(REG_1004H, 0x40400003U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000448U); + WR1_PROG(REG_1018H, 0x00000230U); + WR1_PROG(REG_101CH, 0x00000660U); + WR1_PROG(REG_1020H, 0x00000230U); + + WR1_PROG(REG_1004H, 0x40400002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14600000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00010001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x75f6ae8aU), + bswap_32big(0x62d61efdU), + bswap_32big(0x6002bbccU), + bswap_32big(0x0fd08483U)); + r_rsip_func321(); + + WR1_PROG(REG_1404H, 0x18900000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000660U); + WR1_PROG(REG_1018H, 0x00000a90U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a90U); + WR1_PROG(REG_1018H, 0x00000660U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x509f3ab6U), + bswap_32big(0x67fdc39eU), + bswap_32big(0xa206f2ccU), + bswap_32big(0x9537d209U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd78663c1U), bswap_32big(0x8dec69ffU), bswap_32big(0xbb663cb7U), + bswap_32big(0xf6ce8835U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + + WR1_PROG(REG_1404H, 0x18900000U); + WR1_PROG(REG_1400H, 0x00c00201U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000878U); + WR1_PROG(REG_1018H, 0x00000a90U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x40400009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b040184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x360905f3U)); + + OFS_ADR = 808; + + WR1_PROG(REG_1404H, 0x14600000U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x460b701bU), + bswap_32big(0xf27a8b01U), + bswap_32big(0x86637c6eU), + bswap_32big(0x15a10f2fU)); + r_rsip_func017(OFS_ADR); + + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x00010001U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b06U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8bb0aa17U), + bswap_32big(0xc52cf8a7U), + bswap_32big(0x236250abU), + bswap_32big(0x3ab6186bU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x32ed4c3fU), + bswap_32big(0xfc9853daU), + bswap_32big(0x69a8e333U), + bswap_32big(0x8f2c6ae9U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000011U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbab165dfU), + bswap_32big(0xea5f053fU), + bswap_32big(0x9cc97e5fU), + bswap_32big(0xa3ab25eeU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x14600000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x417b502eU), bswap_32big(0xabbdaf08U), bswap_32big(0xab0e9843U), + bswap_32big(0x4489b2b7U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[1 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x476fdeb3U), bswap_32big(0xc68ebad2U), bswap_32big(0x30fd0d92U), + bswap_32big(0xa00cd93eU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x12480000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x763f5e48U), bswap_32big(0x72927fdaU), bswap_32big(0x820bdc09U), + bswap_32big(0xc44ae84fU)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[129 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0x459ba85bU), bswap_32big(0x899a5235U), bswap_32big(0x20383419U), + bswap_32big(0x29a83e03U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x1e2a72bdU), + bswap_32big(0x5db0e968U), + bswap_32big(0xc34f2212U), + bswap_32big(0x022b33cdU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[257]); + + r_rsip_func100(bswap_32big(0x1676c8baU), + bswap_32big(0x97e09d5dU), + bswap_32big(0x1212dd81U), + bswap_32big(0x9fe7c745U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b07U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbc6b2673U), + bswap_32big(0x04551e73U), + bswap_32big(0xf0cef891U), + bswap_32big(0x6677ccfdU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x19538ee2U), + bswap_32big(0x8bd76535U), + bswap_32big(0x8b3362a6U), + bswap_32big(0x0698f638U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003b02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdfe0280dU), + bswap_32big(0xa02a7c45U), + bswap_32big(0x115f778dU), + bswap_32big(0xdcd304fdU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1404H, 0x14600000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WR1_PROG(REG_1600H, 0x34202886U); + WR1_PROG(REG_1600H, 0x2000d0e0U); + WR1_PROG(REG_1600H, 0x00007c07U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x51749134U), bswap_32big(0xee71497eU), bswap_32big(0x9d76c078U), + bswap_32big(0xa8af4895U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[1 + iLoop]); + + WR1_PROG(REG_1600H, 0x00002485U); + + r_rsip_func101(bswap_32big(0xf5cc0599U), bswap_32big(0x207d18a2U), bswap_32big(0xdaf0184bU), + bswap_32big(0x32b8b67dU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000886U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xea7c6de5U), + bswap_32big(0x52aac35eU), + bswap_32big(0xeada5e0dU), + bswap_32big(0x3bb4b6d5U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008104U); + WR1_PROG(REG_1608H, 0x81010280U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[129]); + + r_rsip_func100(bswap_32big(0x86877c2bU), + bswap_32big(0xc8186f67U), + bswap_32big(0xf68c387aU), + bswap_32big(0x75a031d5U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[133]); + + r_rsip_func100(bswap_32big(0xd2936377U), + bswap_32big(0x5a5d7e76U), + bswap_32big(0xc7a4e8eaU), + bswap_32big(0xc56946d9U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + r_rsip_func102(bswap_32big(0x4c252cefU), + bswap_32big(0x7702e86bU), + bswap_32big(0x01808324U), + bswap_32big(0x5967d15fU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3c.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3c.c new file mode 100644 index 0000000000..c4067e6da7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3c.c @@ -0,0 +1,193 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p3c (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x003c0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003c01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6623dcbbU), + bswap_32big(0x360a321dU), + bswap_32big(0xbd4932c2U), + bswap_32big(0x59d38244U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9e4ad544U), + bswap_32big(0xba9f60aeU), + bswap_32big(0xe3bd45ebU), + bswap_32big(0xf9d1ab6bU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3005eeb3U), + bswap_32big(0xc5c575ceU), + bswap_32big(0x0b9279efU), + bswap_32big(0xa4611eb6U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x7b221004U), + bswap_32big(0x0b91fa37U), + bswap_32big(0xdc1bb9aaU), + bswap_32big(0xd4288633U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003c02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x72585eefU), + bswap_32big(0x48bda3b3U), + bswap_32big(0x88935e97U), + bswap_32big(0x81b51219U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003c03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5cd843eeU), + bswap_32big(0xd80d9223U), + bswap_32big(0x433ad1a8U), + bswap_32big(0x6f73a940U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003c04U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc5da015fU), + bswap_32big(0xea0f73d4U), + bswap_32big(0x64ed7786U), + bswap_32big(0xc79cfec7U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040100U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xb473dd6fU), + bswap_32big(0x3267c347U), + bswap_32big(0x390eecdbU), + bswap_32big(0xc91011bcU)); + + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x810c0000U); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + r_rsip_func100(bswap_32big(0x74bde7cfU), + bswap_32big(0xc89e185cU), + bswap_32big(0xc37dfdf6U), + bswap_32big(0x05d7f055U)); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000003U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[13]); + + r_rsip_func102(bswap_32big(0x72347da7U), + bswap_32big(0x4e3ce7cdU), + bswap_32big(0x38082f42U), + bswap_32big(0xaf58d31fU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3d.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3d.c new file mode 100644 index 0000000000..928c4ac558 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p3d.c @@ -0,0 +1,219 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p3d (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x003d0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003d01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x066ff0b6U), + bswap_32big(0x3b14888eU), + bswap_32big(0x9c244157U), + bswap_32big(0x3b3ba104U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2575e602U), + bswap_32big(0x65f2a6dcU), + bswap_32big(0xae416820U), + bswap_32big(0x4635e180U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5c8c5894U), + bswap_32big(0x8eddff6fU), + bswap_32big(0x5c9a9cdeU), + bswap_32big(0x81c99ba5U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xdfb6d899U), + bswap_32big(0x22212bb7U), + bswap_32big(0x1e6ea182U), + bswap_32big(0x9e6d4806U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003d02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0dc20bedU), + bswap_32big(0x7e9851beU), + bswap_32big(0x3c802831U), + bswap_32big(0xda07ecc8U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003d03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe89c2f71U), + bswap_32big(0x0b4a55eeU), + bswap_32big(0x516028b9U), + bswap_32big(0x5be0c39cU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003d04U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x522d3d4dU), + bswap_32big(0x8c1d7115U), + bswap_32big(0x951b94c2U), + bswap_32big(0x20899e6fU)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040100U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00003d05U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbc2e6c16U), + bswap_32big(0xf92d940aU), + bswap_32big(0xf9a9c7faU), + bswap_32big(0x4ed9e745U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040180U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x5cecdcbaU), + bswap_32big(0x9d0d8db6U), + bswap_32big(0x76678695U), + bswap_32big(0x25e81edcU)); + + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81100000U); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x2ba3a988U), + bswap_32big(0x1d9a5f9aU), + bswap_32big(0xe3875b36U), + bswap_32big(0x9d179dffU)); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000004U)); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[13]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[17]); + + r_rsip_func102(bswap_32big(0x65e3a887U), + bswap_32big(0x888bccbcU), + bswap_32big(0x6c1ae7e9U), + bswap_32big(0x65405585U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p40.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p40.c new file mode 100644 index 0000000000..76f04beca3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p40.c @@ -0,0 +1,212 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p40 (const uint32_t InData_LC[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00400001U); + WR1_PROG(REG_144CH, 0x00000000U); + + r_rsip_func048(InData_LC); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000000aU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x10003401U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x10003401U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1600H, 0x10003401U); + + WR1_PROG(REG_1600H, 0x34202801U); + WR1_PROG(REG_1600H, 0x20003401U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (InData_LC[0] == 0x00000000U) + { + WR1_PROG(REG_143CH, 0x00b80000U); + + r_rsip_func101(bswap_32big(0x87d73112U), bswap_32big(0x99489c5eU), bswap_32big(0xf20e6c89U), + bswap_32big(0x032ed21cU)); + } + else if (InData_LC[0] == 0x00000001U) + { + WR1_PROG(REG_143CH, 0x00b00000U); + + r_rsip_func101(bswap_32big(0xec9bfc30U), bswap_32big(0xfb4affb3U), bswap_32big(0x6bb08ff3U), + bswap_32big(0x62202101U)); + } + else if (InData_LC[0] == 0x00000004U) + { + WR1_PROG(REG_143CH, 0x00b30000U); + + r_rsip_func101(bswap_32big(0x86402685U), bswap_32big(0x1b8cfb91U), bswap_32big(0x6abda81cU), + bswap_32big(0x62d9c55fU)); + } + else if (InData_LC[0] == 0x00000006U) + { + WR1_PROG(REG_143CH, 0x00b50000U); + + r_rsip_func101(bswap_32big(0x3e0f61a3U), bswap_32big(0xb24c4426U), bswap_32big(0x9999b1daU), + bswap_32big(0x6facaf71U)); + } + else if (InData_LC[0] == 0x00000007U) + { + WR1_PROG(REG_143CH, 0x00b60000U); + + r_rsip_func101(bswap_32big(0x7895e3f6U), bswap_32big(0x5ff712f1U), bswap_32big(0x7ff1876fU), + bswap_32big(0x5cdceddcU)); + } + else if (InData_LC[0] == 0x00000008U) + { + WR1_PROG(REG_143CH, 0x00b70000U); + + r_rsip_func101(bswap_32big(0x3a062cc7U), bswap_32big(0x70fe1d0cU), bswap_32big(0x75bc5cdcU), + bswap_32big(0xbc4ea24fU)); + } + else if (InData_LC[0] == 0x00000009U) + { + WR1_PROG(REG_143CH, 0x00b90000U); + + r_rsip_func101(bswap_32big(0x2d92e5ebU), bswap_32big(0xa26ef03dU), bswap_32big(0x08914987U), + bswap_32big(0x5f530e60U)); + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func101(bswap_32big(0x5de847ccU), bswap_32big(0x6e822bb4U), bswap_32big(0x1d247d2fU), + bswap_32big(0xf1d42455U)); + } + + r_rsip_func100(bswap_32big(0xccdbfba4U), + bswap_32big(0x31d111c4U), + bswap_32big(0x885a0cd4U), + bswap_32big(0xe3b36ac9U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x415a6dceU), bswap_32big(0x7a2bb17bU), bswap_32big(0x784354ccU), + bswap_32big(0xfda5486eU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000040U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x193e2eddU), bswap_32big(0x8264c7ccU), bswap_32big(0x702c0503U), + bswap_32big(0x7a200f8bU)); + r_rsip_func040(); + + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WR1_PROG(REG_1438H, 0x20000000U); + WR1_PROG(REG_1400H, 0x00880011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WR1_PROG(REG_1438H, 0x20000010U); + WR1_PROG(REG_1400H, 0x00880011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x000001d0U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x000001b0U); + WR1_PROG(REG_1600H, 0x00003c01U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WR1_PROG(REG_1438H, 0x20000020U); + WR1_PROG(REG_1400H, 0x00880011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x8f0ea4ceU), bswap_32big(0xdebcbecfU), bswap_32big(0x253b5caaU), + bswap_32big(0x8407d742U)); + WR1_PROG(REG_1A24H, 0x4a470044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e4704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0152db38U)); + + WR1_PROG(REG_1A24H, 0x4a040044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e040504U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x01f7370eU)); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x000001c0U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1B08H, 0x00000202U); + + r_rsip_func102(bswap_32big(0x14440fd8U), bswap_32big(0x7bc5db83U), bswap_32big(0x360b67c8U), + bswap_32big(0xeb01427aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41f.c new file mode 100644 index 0000000000..a976a0adc0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41f.c @@ -0,0 +1,200 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p41f (const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x4a000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0xd6118a6cU), bswap_32big(0xc28daa0eU), bswap_32big(0xe9bbcfa9U), + bswap_32big(0x1b84397cU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x5a000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x181a0deaU), bswap_32big(0xcfcfb706U), bswap_32big(0xc41434c6U), + bswap_32big(0xed9b60baU)); + } + + WR1_PROG(REG_1824H, 0x0c000045U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + r_rsip_func100(bswap_32big(0xbff2d496U), bswap_32big(0x1d097928U), bswap_32big(0x37f77fa6U), + bswap_32big(0x698f7f19U)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0e000505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + r_rsip_func102(bswap_32big(0x8fd23867U), bswap_32big(0x1868bff9U), bswap_32big(0xcef01686U), + bswap_32big(0x972da3d4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010040U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a840U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x34202862U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xa63e5f17U), bswap_32big(0xe3de58b0U), bswap_32big(0xf57087d4U), + bswap_32big(0x4b2048e7U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x99f25e2fU), bswap_32big(0xdcbb3b70U), bswap_32big(0x0b00381dU), + bswap_32big(0x1733a148U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0e000505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e2U); + WR1_PROG(REG_1600H, 0x000568e7U); + WR1_PROG(REG_1600H, 0x00026ce7U); + + WR1_PROG(REG_1600H, 0x00003827U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1600H, 0x00003402U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x000028c0U); + WR1_PROG(REG_1600H, 0x00008cc0U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x00004406U); + + WR1_PROG(REG_1600H, 0x00007421U); + WR1_PROG(REG_1600H, 0x00007821U); + + WR1_PROG(REG_1600H, 0x00003c27U); + + WR1_PROG(REG_1600H, 0x000034c2U); + WR1_PROG(REG_1600H, 0x0000a4c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x000568c6U); + + WR1_PROG(REG_1600H, 0x000034e6U); + WR1_PROG(REG_1600H, 0x00026ce7U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 4U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3420a8e0U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1600H, 0x10003c27U); + + WR1_PROG(REG_1600H, 0x1000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + r_rsip_func100(bswap_32big(0x8c41fff8U), bswap_32big(0x9c2c6192U), bswap_32big(0xfb507cb9U), + bswap_32big(0x9724068bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x886a58a0U), + bswap_32big(0x6210ec96U), + bswap_32big(0xae928243U), + bswap_32big(0x029ba73eU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x0a02398cU), + bswap_32big(0x2098c3b3U), + bswap_32big(0x45511380U), + bswap_32big(0xa43cdd13U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41i.c new file mode 100644 index 0000000000..7762927187 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41i.c @@ -0,0 +1,111 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p41i (const uint32_t InData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00410001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000041U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x317a7b1bU), + bswap_32big(0x2a238f0bU), + bswap_32big(0x4ec2f0c7U), + bswap_32big(0x66a7a7c4U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000041U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6df6df62U), + bswap_32big(0x6b3af2c6U), + bswap_32big(0x20e1b15dU), + bswap_32big(0x8810bd10U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x80a2dd99U), + bswap_32big(0xa59b2d4aU), + bswap_32big(0x79e2fa9dU), + bswap_32big(0x05faf18fU)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x4728e30cU), + bswap_32big(0x8d4073b4U), + bswap_32big(0x1f868135U), + bswap_32big(0xdb8d3db3U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xc4787ffdU), bswap_32big(0x724bc43bU), bswap_32big(0x2f2a4234U), + bswap_32big(0x7cd2042dU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41u.c new file mode 100644 index 0000000000..d59eb82174 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p41u.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p41u (const uint32_t InData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0e000406U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0x10e58614U), + bswap_32big(0xb95e4c93U), + bswap_32big(0x43a7aa78U), + bswap_32big(0xe082522eU)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44f.c new file mode 100644 index 0000000000..c69632069d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44f.c @@ -0,0 +1,204 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p44f (const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x4a008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x113a7aa4U), bswap_32big(0xa2a042f8U), bswap_32big(0xf49fd5a9U), + bswap_32big(0x9288ad77U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x5a008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x987246faU), bswap_32big(0x5e4c9e7eU), bswap_32big(0xb76e4cfdU), + bswap_32big(0x0396ac5aU)); + } + + WR1_PROG(REG_1824H, 0x0c000045U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + r_rsip_func100(bswap_32big(0x1b2c8827U), bswap_32big(0x43f78b12U), bswap_32big(0x1f267e0aU), + bswap_32big(0x80bce919U)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + r_rsip_func102(bswap_32big(0xc239f9daU), bswap_32big(0x3e59d635U), bswap_32big(0xb2eb9f3bU), + bswap_32big(0xe067516aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010040U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a840U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x34202862U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xb00ad243U), bswap_32big(0xa3abf242U), bswap_32big(0x572d859cU), + bswap_32big(0x7b9e5f54U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x7e9ac66eU), bswap_32big(0xe56d4d0bU), bswap_32big(0x26566ac9U), + bswap_32big(0xcb790c98U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e2U); + WR1_PROG(REG_1600H, 0x000568e7U); + WR1_PROG(REG_1600H, 0x00026ce7U); + + WR1_PROG(REG_1600H, 0x00003827U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1600H, 0x00003402U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x000028c0U); + WR1_PROG(REG_1600H, 0x00008cc0U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x00004406U); + + WR1_PROG(REG_1600H, 0x00007421U); + WR1_PROG(REG_1600H, 0x00007821U); + + WR1_PROG(REG_1600H, 0x00003c27U); + + WR1_PROG(REG_1600H, 0x000034c2U); + WR1_PROG(REG_1600H, 0x0000a4c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x000568c6U); + + WR1_PROG(REG_1600H, 0x000034e6U); + WR1_PROG(REG_1600H, 0x00026ce7U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 4U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3420a8e0U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1600H, 0x10003c27U); + + WR1_PROG(REG_1600H, 0x1000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + r_rsip_func100(bswap_32big(0x2a41951aU), bswap_32big(0x8ce2fa9dU), bswap_32big(0x1cadbefbU), + bswap_32big(0xdef11839U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x910189b1U), + bswap_32big(0x5b2dce1eU), + bswap_32big(0xeaada42cU), + bswap_32big(0xc0d95f0bU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x6b83036cU), + bswap_32big(0xe702a8afU), + bswap_32big(0x597e6f5eU), + bswap_32big(0x4ba8a982U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44i.c new file mode 100644 index 0000000000..2b48904dae --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44i.c @@ -0,0 +1,122 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p44i (const uint32_t InData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00440001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000044U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0016cdbbU), + bswap_32big(0xfadbbf30U), + bswap_32big(0x68feffbcU), + bswap_32big(0xdc3d84acU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000044U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1f80c1b8U), + bswap_32big(0x00d55f14U), + bswap_32big(0xf7b6feffU), + bswap_32big(0x82d89836U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x9665d5f6U), + bswap_32big(0xf62fd705U), + bswap_32big(0x346e74b8U), + bswap_32big(0x4e2ed0d9U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xb9837ad1U), + bswap_32big(0x4ff8f69aU), + bswap_32big(0x088aec37U), + bswap_32big(0x21123929U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x965f901eU), + bswap_32big(0x198bd30fU), + bswap_32big(0x79d4c13cU), + bswap_32big(0x5496bae5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xeb453b85U), bswap_32big(0x519547acU), bswap_32big(0x440af007U), + bswap_32big(0x1aae4ba9U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44u.c new file mode 100644 index 0000000000..81c567b044 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p44u.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p44u (const uint32_t InData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008406U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0x3cddb3deU), + bswap_32big(0x8125705dU), + bswap_32big(0xc0db339fU), + bswap_32big(0x10b3d262U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47f.c new file mode 100644 index 0000000000..139c638332 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47f.c @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p47f (void) +{ + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func101(bswap_32big(0x7c1839bbU), bswap_32big(0xdb1964afU), bswap_32big(0x3b18725cU), + bswap_32big(0x0c30bfc8U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func101(bswap_32big(0x15622c79U), bswap_32big(0xad7a4026U), bswap_32big(0x6da71cb7U), + bswap_32big(0xdbfc6783U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func101(bswap_32big(0xa2326a27U), bswap_32big(0x0864d1d2U), bswap_32big(0x700d8ad2U), + bswap_32big(0xcef8c280U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func101(bswap_32big(0x386d4cfeU), bswap_32big(0xac6fd53aU), bswap_32big(0xd3eaf72fU), + bswap_32big(0xacbbbb20U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + r_rsip_func101(bswap_32big(0xc1cfad39U), bswap_32big(0x54191ceeU), bswap_32big(0xb8d68cc6U), + bswap_32big(0x77a0a3ceU)); + } + else + { + ; + } + + r_rsip_func102(bswap_32big(0xf9c7aeceU), + bswap_32big(0xf05b2fb2U), + bswap_32big(0x46ea5307U), + bswap_32big(0x72377664U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47i.c new file mode 100644 index 0000000000..0408964c4c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47i.c @@ -0,0 +1,372 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p47i (const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IVType[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00470001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1608H, 0x80010080U); + WR1_PROG(REG_1444H, 0x000000c7U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004701U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb9bcb3c4U), + bswap_32big(0x6cb3d81dU), + bswap_32big(0x9bb85f89U), + bswap_32big(0x08237be6U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004701U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcb83f1e8U), + bswap_32big(0xb4f2c99eU), + bswap_32big(0xbfda355aU), + bswap_32big(0x7ce0213eU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x8032119eU), + bswap_32big(0x30108072U), + bswap_32big(0xc7cc37fbU), + bswap_32big(0x057cc8a1U)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xa6d18dccU), + bswap_32big(0xfd16a4f3U), + bswap_32big(0x80d6c565U), + bswap_32big(0x4d75e0d7U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xf0d55e55U), bswap_32big(0x923fe84fU), bswap_32big(0x999fba4eU), + bswap_32big(0xa60d7687U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xcb5741cfU), bswap_32big(0x4cd2d194U), bswap_32big(0xb3ac9123U), + bswap_32big(0x9784b967U)); + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func101(bswap_32big(0x56cecea4U), bswap_32big(0x47013527U), bswap_32big(0x67043742U), + bswap_32big(0xbf699041U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func101(bswap_32big(0x341a9cabU), bswap_32big(0x0c02b2d2U), bswap_32big(0x2c2ded9cU), + bswap_32big(0x98b3b5b1U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IVType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x89692601U), bswap_32big(0x9bb1b334U), bswap_32big(0xe03e41eeU), + bswap_32big(0xed931863U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0x9f76eb48U), + bswap_32big(0xc5cf0284U), + bswap_32big(0x5bc40a5eU), + bswap_32big(0xf18894b3U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004702U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcfbd5020U), + bswap_32big(0xe2f50848U), + bswap_32big(0x369abb25U), + bswap_32big(0x8ca4bde3U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004702U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x994df9f9U), + bswap_32big(0xcbab2babU), + bswap_32big(0xfeea75c2U), + bswap_32big(0xcafe8272U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[1]); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x60e95fddU), + bswap_32big(0xd75c4ac2U), + bswap_32big(0x31bceebaU), + bswap_32big(0xe062eb33U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8f336eeeU), + bswap_32big(0xb8b12e91U), + bswap_32big(0xd26a0aa8U), + bswap_32big(0x4b7256b3U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x670937bfU), + bswap_32big(0x7d1d1629U), + bswap_32big(0xc7bba2d3U), + bswap_32big(0xbb2f23c8U)); + } + } + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IVType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x034c5cd1U), bswap_32big(0x69fb51c6U), bswap_32big(0x1f3e4060U), + bswap_32big(0x1ea59594U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0xde100001U), + bswap_32big(0x97b13960U), + bswap_32big(0x2e1e4b2aU), + bswap_32big(0x30aef1baU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004703U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3e260afaU), + bswap_32big(0xc6bdeed9U), + bswap_32big(0x044fb040U), + bswap_32big(0x93d2e350U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004703U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2f2f51edU), + bswap_32big(0x1d4c1a06U), + bswap_32big(0x2c73bff7U), + bswap_32big(0x3ad3f7d3U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[1]); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x64b4ee4aU), + bswap_32big(0x8aa717beU), + bswap_32big(0x39f54073U), + bswap_32big(0x797106dfU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe95b4b1bU), + bswap_32big(0x745fc20dU), + bswap_32big(0xdb42cac6U), + bswap_32big(0x919073b9U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x6a50ea03U), + bswap_32big(0xa5ebc98bU), + bswap_32big(0x92ca60a3U), + bswap_32big(0x1dfac49bU)); + } + } + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0x14c0f2b9U), bswap_32big(0xfce4e9c3U), bswap_32big(0x0788c085U), + bswap_32big(0x79d3b46dU)); + } + else + { + } + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47u.c new file mode 100644 index 0000000000..d55a9f1bc7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p47u.c @@ -0,0 +1,131 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p47u (uint32_t const InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x3a2354a1U), bswap_32big(0x54199b04U), bswap_32big(0xc4156b93U), + bswap_32big(0xd55f6ebaU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0a000106U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x99ba8cefU), bswap_32big(0x63f5414cU), bswap_32big(0x8cdcd890U), + bswap_32big(0x24d210d7U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0a00010eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x993f883fU), bswap_32big(0x7920a7f7U), bswap_32big(0x9e2488a7U), + bswap_32big(0x7db23ae7U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0e000506U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x395149eaU), bswap_32big(0x82cecc13U), bswap_32big(0xc38d8759U), + bswap_32big(0x077fa6dbU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0900090eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0xdbb0efd9U), bswap_32big(0xecf2f4e6U), bswap_32big(0x7084cfb6U), + bswap_32big(0x5b481e64U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x07000d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else + { + ; + } + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0xe0ab8198U), bswap_32big(0x89323c6bU), bswap_32big(0xecfdb396U), + bswap_32big(0x2b843bcaU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0x7d057555U), bswap_32big(0x69c1a7ecU), bswap_32big(0x590253c9U), + bswap_32big(0xcccd5b37U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0x8d3652b1U), bswap_32big(0x1b846e72U), bswap_32big(0xdeb48362U), + bswap_32big(0x2b00c63fU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0x9f659e29U), bswap_32big(0x934675e9U), bswap_32big(0xa9b54b7bU), + bswap_32big(0xb93e085dU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0x2c71731eU), bswap_32big(0x60d7f514U), bswap_32big(0x169e094eU), + bswap_32big(0xfa9f7109U)); + } + else + { + ; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p4e.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p4e.c new file mode 100644 index 0000000000..eb0a192848 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p4e.c @@ -0,0 +1,527 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p4e (const uint32_t InData_CurveType[], + const uint32_t InData_PubKeyType[], + const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_DomainParam[], + uint32_t OutData_EncSecret[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x004e0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x92296edbU), + bswap_32big(0x82fe4ec3U), + bswap_32big(0x7f25e598U), + bswap_32big(0xd1a8505cU)); + r_rsip_func027(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004e01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x59fec05dU), + bswap_32big(0xc4fde013U), + bswap_32big(0xbb760ba8U), + bswap_32big(0x60226a6eU)); + r_rsip_func043(); + + r_rsip_func076(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004e01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x918051e2U), + bswap_32big(0x334979ebU), + bswap_32big(0xc0472a49U), + bswap_32big(0x0861b75dU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x00000bc2U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x13100000U); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x0be593a8U), + bswap_32big(0x500b6a6dU), + bswap_32big(0xff1f84c2U), + bswap_32big(0x8baf91efU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0b62cc05U), bswap_32big(0x1c2b1961U), bswap_32big(0x54aff6d7U), + bswap_32big(0xc5184907U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000f7bU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xbb0132e6U), bswap_32big(0x1216121fU), bswap_32big(0x89234a08U), + bswap_32big(0x0d4acd26U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x00000bd0U); + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = 0U; iLoop < 48U; ) + { + WR1_ADDR((&(REG_00E0H))[iLoop / 4], &InData_PubKey[0 + (iLoop / 4)]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x00000bd0U); + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = 0U; iLoop < 48U; ) + { + WR1_ADDR((&(REG_0130H))[iLoop / 4], &InData_PubKey[12 + (iLoop / 4)]); + iLoop = iLoop + 4U; + } + + r_rsip_func101(bswap_32big(0x76f7defaU), bswap_32big(0x5e75b5bcU), bswap_32big(0x015b79fdU), + bswap_32big(0x44e0c7b1U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004e02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc918e5beU), bswap_32big(0xe21eb167U), bswap_32big(0x6ba23afbU), + bswap_32big(0x1fcd0500U)); + r_rsip_func043(); + + r_rsip_func077(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004e02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xddc80570U), bswap_32big(0xb19fffb2U), bswap_32big(0x97d1fb16U), + bswap_32big(0xbe483218U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x40000500U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[5]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[9]); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[13]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[17]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[21]); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[25]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x7e52aadeU), bswap_32big(0x6912e633U), bswap_32big(0xf66e0c03U), + bswap_32big(0xc7a6848bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xfb5859a3U), + bswap_32big(0xeba553e0U), + bswap_32big(0xd3d2ec06U), + bswap_32big(0xc0d42f02U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x2036775cU), + bswap_32big(0x5d9dbc00U), + bswap_32big(0xb856a4baU), + bswap_32big(0x7285db5dU)); + } + } + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000890U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x06060005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000008e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x06060005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x7f5e80ebU), bswap_32big(0x43844727U), bswap_32big(0x671124a3U), + bswap_32big(0xd235a938U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x50aa0ecbU), bswap_32big(0x5e0e722eU), bswap_32big(0x19cf7584U), + bswap_32big(0xf290aac4U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000218U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001e0U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000004eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3920b5d9U), bswap_32big(0xfc89f8e0U), bswap_32big(0x368a44c1U), + bswap_32big(0xe7ebe725U)); + r_rsip_func089(); + + r_rsip_func100(bswap_32big(0x24e802e4U), bswap_32big(0x46c59e47U), bswap_32big(0xec6f0f3dU), + bswap_32big(0xce7ec315U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x059283b7U), + bswap_32big(0x7257859dU), + bswap_32big(0x4d1ec816U), + bswap_32big(0x1e1a9ff1U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000004eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x356d0231U), + bswap_32big(0x2eaf5637U), + bswap_32big(0xe84305baU), + bswap_32big(0xaab18240U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004e03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x61c9609bU), + bswap_32big(0xeb6dca41U), + bswap_32big(0x3cd54576U), + bswap_32big(0xe0611bedU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0165e3d8U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004e03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x52e64e8fU), + bswap_32big(0xe0dce3b3U), + bswap_32big(0x6cf3cc6cU), + bswap_32big(0x17f0b426U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x22165956U), + bswap_32big(0xfbe944d3U), + bswap_32big(0xcb145b27U), + bswap_32big(0x27cd3048U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[9]); + + r_rsip_func100(bswap_32big(0x0d69d9c3U), + bswap_32big(0xb4e23fe0U), + bswap_32big(0x008934f2U), + bswap_32big(0x2c7c0947U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[13]); + + r_rsip_func100(bswap_32big(0xdbd8131cU), + bswap_32big(0xa957f1dbU), + bswap_32big(0x3141af23U), + bswap_32big(0xc1bcb082U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncSecret[0]); + + r_rsip_func102(bswap_32big(0x192f519eU), + bswap_32big(0x650ab23aU), + bswap_32big(0x0a036f4dU), + bswap_32big(0x50c3595fU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p4f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p4f.c new file mode 100644 index 0000000000..49848f927a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p4f.c @@ -0,0 +1,618 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p4f (const uint32_t InData_PubKeyType[], + const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_DomainParam[], + uint32_t OutData_EncSecret[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x004f0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0x2fbe0dd5U), + bswap_32big(0xda443bd5U), + bswap_32big(0x795891d9U), + bswap_32big(0xc94c2b9bU)); + r_rsip_func086(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004f01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf28e80d5U), + bswap_32big(0x315cc5ebU), + bswap_32big(0xcd897c8cU), + bswap_32big(0xd19ed2b7U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000025U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004f01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6dbf0933U), + bswap_32big(0x32549d85U), + bswap_32big(0x6b34aa8fU), + bswap_32big(0xbea09385U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000013c2U); + WR1_PROG(REG_1A2CH, 0x40000400U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x12f00000U); + + for (iLoop = 0U; iLoop < 20; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xd1f859c7U), + bswap_32big(0x86170122U), + bswap_32big(0x89e49f17U), + bswap_32big(0x2813c39aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x50e46e85U), bswap_32big(0x0f5300e9U), bswap_32big(0x62d21955U), + bswap_32big(0x94b83cc8U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000f7bU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xbfe67ddeU), bswap_32big(0x20521f01U), bswap_32big(0x90b66147U), + bswap_32big(0x47237516U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + + WR1_PROG(REG_1444H, 0x000027c7U); + WR1_PROG(REG_1608H, 0x80a8001eU); + for (iLoop = 0U; iLoop < 40U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x00000bbdU); + + for (iLoop = 0U; iLoop < 2U; iLoop++) + { + for (jLoop = 0U; jLoop < 3U; jLoop++) + { + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1600H, 0x100053fdU); + + WR1_PROG(REG_1600H, 0x00002fa0U); + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1600H, 0xfffffe00U); + WR1_PROG(REG_1600H, 0x100053fdU); + + WR1_PROG(REG_1600H, 0x00002fa0U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000050U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x000000ffU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xecb11aacU), bswap_32big(0xda2ad50aU), bswap_32big(0xd627203cU), + bswap_32big(0xf389f55fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x78a6982eU), + bswap_32big(0xa6e21406U), + bswap_32big(0x377d293dU), + bswap_32big(0xe64d5881U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x756ddd9cU), + bswap_32big(0xd4c58ca1U), + bswap_32big(0xfaab4ce0U), + bswap_32big(0x959e4bd7U)); + } + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004f02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3f9fca82U), bswap_32big(0x69efa2fdU), bswap_32big(0x138a963eU), + bswap_32big(0x6052d13eU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004f02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa5eb2c5fU), bswap_32big(0x97ef0327U), bswap_32big(0xf309ccf8U), + bswap_32big(0xfddb84e6U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x40000900U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x80a8001eU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[5]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[9]); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[13]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[17]); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[21]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[25]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[29]); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[33]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[37]); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[41]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xea4e2544U), bswap_32big(0x112ab0daU), bswap_32big(0xc55034b6U), + bswap_32big(0x58e8bc20U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x9508cee5U), + bswap_32big(0x64357f83U), + bswap_32big(0x2564cf34U), + bswap_32big(0x84adc095U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x35e076bbU), + bswap_32big(0xae3ecdedU), + bswap_32big(0xa32be00fU), + bswap_32big(0xb4bd9a5bU)); + } + } + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x81a8001eU); + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1400H, 0x00c90051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11100000U); + WR1_PROG(REG_1400H, 0x00c90051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000890U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x09090005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000008e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x09090005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x6ca0d89cU), bswap_32big(0x0721cd88U), bswap_32big(0xa199c26fU), + bswap_32big(0x682d5e28U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x2c44d0caU), bswap_32big(0x6a189af6U), bswap_32big(0x6fc45e3aU), + bswap_32big(0x9ed4e39eU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000004fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf166da1fU), bswap_32big(0x19b64510U), bswap_32big(0xcabe011bU), + bswap_32big(0x671a73fcU)); + r_rsip_func091(); + + r_rsip_func100(bswap_32big(0x0da6054fU), bswap_32big(0x457456b9U), bswap_32big(0x29c3775eU), + bswap_32big(0xd6bde236U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x2c76bdd7U), + bswap_32big(0x037f2397U), + bswap_32big(0x6750b1e3U), + bswap_32big(0xde740239U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000004fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb3777504U), + bswap_32big(0x05c822b0U), + bswap_32big(0xd14d3841U), + bswap_32big(0x48286b73U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004f03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6cb39292U), + bswap_32big(0x26590065U), + bswap_32big(0x66cdd0ceU), + bswap_32big(0x585463abU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01ea2366U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00004f03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2c37a5d9U), + bswap_32big(0x6cf3c189U), + bswap_32big(0x5dc7ad3cU), + bswap_32big(0xfb7d033bU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x72da56e2U), + bswap_32big(0x771acd6bU), + bswap_32big(0x15f67c9aU), + bswap_32big(0x7d9ba59fU)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x12580000U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00830029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xb9eddd84U), + bswap_32big(0x163dabacU), + bswap_32big(0xe4de49ffU), + bswap_32big(0xcdcb02b1U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7008d07U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[iLoop + 1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[iLoop + 5]); + r_rsip_func100(bswap_32big(0x222b2b9cU), + bswap_32big(0x35a66401U), + bswap_32big(0xb47dcac4U), + bswap_32big(0xd618e601U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[iLoop + 9]); + + r_rsip_func100(bswap_32big(0x82f304ceU), + bswap_32big(0x47e842c8U), + bswap_32big(0xaf286571U), + bswap_32big(0x0e5c267cU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncSecret[0]); + + r_rsip_func102(bswap_32big(0xa77dc41fU), + bswap_32big(0x04cfb7fdU), + bswap_32big(0xd4496b51U), + bswap_32big(0x2254abc1U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50f.c new file mode 100644 index 0000000000..c13fc714ce --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50f.c @@ -0,0 +1,54 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p50f (void) +{ + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func101(bswap_32big(0x51918b25U), bswap_32big(0x21cb2e29U), bswap_32big(0x5e8bb2eaU), + bswap_32big(0xa9e46fccU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func101(bswap_32big(0x514cac3bU), bswap_32big(0x8d94dd1fU), bswap_32big(0x0fe693a1U), + bswap_32big(0xce7152ceU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func101(bswap_32big(0xa25522a4U), bswap_32big(0x803beb1fU), bswap_32big(0xbf2c1e3bU), + bswap_32big(0xe7efe428U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func101(bswap_32big(0xaef7b372U), bswap_32big(0x944d935bU), bswap_32big(0xed52892bU), + bswap_32big(0xe0d2eb96U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + r_rsip_func101(bswap_32big(0xa8e06244U), bswap_32big(0x868e7c5fU), bswap_32big(0x9888fdedU), + bswap_32big(0x25ab8c6eU)); + } + + r_rsip_func102(bswap_32big(0x4380f41aU), + bswap_32big(0x6029e898U), + bswap_32big(0x61ae0705U), + bswap_32big(0xe7be0026U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50i.c new file mode 100644 index 0000000000..5b78074b5c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50i.c @@ -0,0 +1,380 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p50i (const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IVType[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00500001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1608H, 0x80010080U); + WR1_PROG(REG_1444H, 0x000000c7U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005001U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x07d48aa4U), + bswap_32big(0xfce58dc0U), + bswap_32big(0xe6eb1757U), + bswap_32big(0x7af98fe1U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005001U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x09ef5af8U), + bswap_32big(0x33632767U), + bswap_32big(0x0037a094U), + bswap_32big(0x2bc79f18U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x2893cb10U), + bswap_32big(0xa00b4d81U), + bswap_32big(0xce253840U), + bswap_32big(0xa539a52cU)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x5daf2d71U), + bswap_32big(0x82aeec58U), + bswap_32big(0x90161142U), + bswap_32big(0x712ec473U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xeac6d05aU), + bswap_32big(0x9194b36cU), + bswap_32big(0x2326e45bU), + bswap_32big(0x409dd77bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd3eb92e7U), bswap_32big(0x35113d8aU), bswap_32big(0xe3a20c4eU), + bswap_32big(0xfcd563aaU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xd088896bU), bswap_32big(0x2a0ec2b9U), bswap_32big(0x2b6c0529U), + bswap_32big(0xeca5cbcbU)); + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func101(bswap_32big(0xe8554663U), bswap_32big(0x8ba5263cU), bswap_32big(0xd5fa24acU), + bswap_32big(0x3f225584U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func101(bswap_32big(0xaf0dcb42U), bswap_32big(0x4360d11eU), bswap_32big(0xcb02ae2bU), + bswap_32big(0x1a49073aU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IVType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x7006b5ddU), bswap_32big(0x9c1a1bc3U), bswap_32big(0xb542f271U), + bswap_32big(0xd83ae465U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0x41086f0eU), + bswap_32big(0xf7d4349aU), + bswap_32big(0x11af1146U), + bswap_32big(0x1b6f3745U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005002U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6f20a273U), + bswap_32big(0x0c425446U), + bswap_32big(0x3de3e6ddU), + bswap_32big(0x89c113fdU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005002U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xba8fb78eU), + bswap_32big(0x9a191ccaU), + bswap_32big(0x9bcb575fU), + bswap_32big(0xfd5e6bfeU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[1]); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x4923ba69U), + bswap_32big(0x5185aa2fU), + bswap_32big(0x934832f8U), + bswap_32big(0x4c8bfdc0U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x1b883993U), + bswap_32big(0x53f0c711U), + bswap_32big(0x4c536dc7U), + bswap_32big(0xfa4c45fcU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x38b5a76fU), + bswap_32big(0xda0f55b9U), + bswap_32big(0xfa38a034U), + bswap_32big(0x35e70887U)); + } + } + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IVType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x9e03769bU), bswap_32big(0x140508ccU), bswap_32big(0x5da32492U), + bswap_32big(0x91ff19f5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0xd438e58aU), + bswap_32big(0x0dfa4c1bU), + bswap_32big(0x6a0b1a48U), + bswap_32big(0x9f6f52a5U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005003U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4183ec0fU), + bswap_32big(0x0a5bbf3cU), + bswap_32big(0xfbc03641U), + bswap_32big(0x65053724U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005003U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7f194fd5U), + bswap_32big(0x0628b6d0U), + bswap_32big(0x3e117e33U), + bswap_32big(0xfddbf996U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[1]); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xca98a177U), + bswap_32big(0x14b87173U), + bswap_32big(0xe9362257U), + bswap_32big(0xf2079ac5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xa4f0386bU), + bswap_32big(0x2a2ede76U), + bswap_32big(0xe546fa79U), + bswap_32big(0x6b0525bdU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x4ec19d1fU), + bswap_32big(0xba63fed0U), + bswap_32big(0xd4c011d2U), + bswap_32big(0x503718a8U)); + } + } + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0x294146cbU), bswap_32big(0x23e8a782U), bswap_32big(0x1b1bc745U), + bswap_32big(0x690a50f5U)); + } + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50u.c new file mode 100644 index 0000000000..848ed2c987 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p50u.c @@ -0,0 +1,136 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p50u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x02e2bebbU), bswap_32big(0x197f36b2U), bswap_32big(0x2dab0db6U), + bswap_32big(0x8a6edbf4U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0a008106U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x8e117143U), bswap_32big(0xf50e82bbU), bswap_32big(0x24d387a5U), + bswap_32big(0x08be162cU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0a00810eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x8f5136ceU), bswap_32big(0xcc92a0bfU), bswap_32big(0xae1d5aa4U), + bswap_32big(0x4c80ddc3U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008506U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0xc5831880U), bswap_32big(0x638beea0U), bswap_32big(0xef27fe4fU), + bswap_32big(0x39eb4be1U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0900890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x7c9a6a45U), bswap_32big(0x1458c047U), bswap_32big(0xbe0431e0U), + bswap_32big(0x4f94615bU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else + { + ; + } + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0x08d83b3aU), bswap_32big(0xf809bf2eU), bswap_32big(0x078e4610U), + bswap_32big(0x221efdd8U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0xe5187f09U), bswap_32big(0xac474836U), bswap_32big(0x1afc0432U), + bswap_32big(0x958fd8faU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0xf3dc0990U), bswap_32big(0x5239d741U), bswap_32big(0xe177e8caU), + bswap_32big(0xaedd1c19U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0x6c296703U), bswap_32big(0x3ab077efU), bswap_32big(0xc39ef4e1U), + bswap_32big(0x8d60bf8fU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0x27bd620fU), bswap_32big(0xbf71e04aU), bswap_32big(0xf2b0b401U), + bswap_32big(0x39d52466U)); + } + else + { + ; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p51f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p51f.c new file mode 100644 index 0000000000..891592d6a1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p51f.c @@ -0,0 +1,131 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p51f (uint32_t OutData_EncCertificateInfo[]) +{ + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000051U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xafa76023U), + bswap_32big(0xcfdf6e31U), + bswap_32big(0x876c7ed3U), + bswap_32big(0xbfa852b2U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005102U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa611414cU), + bswap_32big(0x212a3d6eU), + bswap_32big(0x545cefcdU), + bswap_32big(0xefeeaf16U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01f6c222U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005102U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x85bd883bU), + bswap_32big(0x1c3401a1U), + bswap_32big(0x8fdef9e4U), + bswap_32big(0x598bd571U)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x00000884U); + + r_rsip_func100(bswap_32big(0xab50bbd0U), + bswap_32big(0xa12e668bU), + bswap_32big(0x0420f303U), + bswap_32big(0x164e0e02U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + + WR1_PROG(REG_1608H, 0x818c0004U); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[9]); + + r_rsip_func100(bswap_32big(0x1f0dc008U), + bswap_32big(0xa2fe4924U), + bswap_32big(0x1a91cc83U), + bswap_32big(0x54fefb0fU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[13]); + + r_rsip_func100(bswap_32big(0xed0db4e4U), + bswap_32big(0x9050c163U), + bswap_32big(0xe2842e16U), + bswap_32big(0x725e127dU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncCertificateInfo[0]); + + r_rsip_func102(bswap_32big(0x52b0d8eaU), + bswap_32big(0x6b6cad27U), + bswap_32big(0x63cba73aU), + bswap_32big(0xad25ccddU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p51i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p51i.c new file mode 100644 index 0000000000..74aa29540b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p51i.c @@ -0,0 +1,1197 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p51i (const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00510001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005101U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcf827ef0U), + bswap_32big(0x46dcbf26U), + bswap_32big(0xaf886714U), + bswap_32big(0xb3927569U)); + r_rsip_func043(); + + r_rsip_func077(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005101U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9f904d75U), + bswap_32big(0x39e120e8U), + bswap_32big(0x1257ce9aU), + bswap_32big(0xa8e5867bU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x40000500U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80980001U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[21]); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[25]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x81ce3c2fU), + bswap_32big(0x00d63520U), + bswap_32big(0x4bc21c04U), + bswap_32big(0x14e139f0U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xc7808741U), bswap_32big(0x231cfb41U), bswap_32big(0x1738c005U), + bswap_32big(0x15018108U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000bc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x808c001fU); + for (iLoop = 0U; iLoop < 12U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x818c001eU); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1608H, 0x808c001eU); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000051U)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0xd54e8d33U), bswap_32big(0xb7d72cceU), bswap_32big(0x032bdae4U), + bswap_32big(0x7c7953d1U)); + r_rsip_func027(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19000000U); + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x00000500U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19500000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000980U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xf0351567U), bswap_32big(0x84420d00U), bswap_32big(0xa3fbe4efU), + bswap_32big(0xe10ce2a3U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x6e784953U), bswap_32big(0x76d334f5U), bswap_32big(0x00a92279U), + bswap_32big(0x64f24229U)); + } + else + { + r_rsip_func100(bswap_32big(0x52eb7ad5U), bswap_32big(0x9dd2115fU), bswap_32big(0xb9d376bcU), + bswap_32big(0xe34ccd2dU)); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x818c001fU); + WR1_PROG(REG_1400H, 0x00c90031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1400H, 0x00c002d1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000a70U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002b8U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1608H, 0x818c0001U); + WR1_PROG(REG_1400H, 0x00c90031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000a00U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1608H, 0x818c001fU); + WR1_PROG(REG_1400H, 0x00c90031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000a38U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xa2ca9bceU), bswap_32big(0x1987f549U), bswap_32big(0xbd6efaeaU), + bswap_32big(0xedddf264U)); + r_rsip_func028(InData_DomainParam); + + WR1_PROG(REG_1014H, 0x000001e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000af0U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000218U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000b28U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a70U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000b60U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000af0U); + WR1_PROG(REG_1018H, 0x00000a00U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a00U); + WR1_PROG(REG_1018H, 0x00000af0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000b28U); + WR1_PROG(REG_1018H, 0x00000a38U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a38U); + WR1_PROG(REG_1018H, 0x00000b28U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xa0b17a17U), bswap_32big(0xc65d53a0U), bswap_32big(0xef22760fU), + bswap_32big(0x859e8c99U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000a70U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000c50U); + + WR1_PROG(REG_1004H, 0x06060013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xb88dd5a4U), + bswap_32big(0x4aea1022U), + bswap_32big(0x18eb4832U), + bswap_32big(0xde5a957fU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000c50U); + + WR1_PROG(REG_1004H, 0x06060014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x06d81f9dU), + bswap_32big(0x3320787dU), + bswap_32big(0x456ba820U), + bswap_32big(0xa91bf37dU)); + } + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1404H, 0x14500000U); + WR1_PROG(REG_1608H, 0x808c0001U); + WR1_PROG(REG_1400H, 0x03430031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1404H, 0x13100000U); + WR1_PROG(REG_1608H, 0x808c0001U); + WR1_PROG(REG_1400H, 0x03430031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 12U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000034a1U); + + WR1_PROG(REG_1600H, 0x00026ca5U); + + WR1_PROG(REG_1600H, 0x00003865U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x00003885U); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x01816ca3U); + WR1_PROG(REG_1600H, 0x01816ca4U); + WR1_PROG(REG_1600H, 0x00016c63U); + WR1_PROG(REG_1600H, 0x00016c84U); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x67744cbeU), + bswap_32big(0x2480d621U), + bswap_32big(0x50803b7aU), + bswap_32big(0xfb8deaffU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xca659dccU), + bswap_32big(0xf0b5f902U), + bswap_32big(0x570c61dfU), + bswap_32big(0x530022fdU)); + } + else + { + r_rsip_func101(bswap_32big(0xe40b84d4U), + bswap_32big(0xf78d7831U), + bswap_32big(0x1f32312bU), + bswap_32big(0xf2882d86U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xcbe3662dU), + bswap_32big(0xaf1273ebU), + bswap_32big(0xa9318fbaU), + bswap_32big(0x4546aafcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x821a8dd5U), + bswap_32big(0x417994dbU), + bswap_32big(0x3f18f054U), + bswap_32big(0x0b397a78U)); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1014H, 0x00000a00U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000410U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a38U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a70U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xb0b12ad4U), + bswap_32big(0x36b007a3U), + bswap_32big(0x6942a78aU), + bswap_32big(0x77f1f042U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1014H, 0x00000af0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000410U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000b28U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x7c03f7f5U), + bswap_32big(0x59b6ad56U), + bswap_32big(0x4b55cb17U), + bswap_32big(0xc6b6ec8cU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1014H, 0x00000be0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000410U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000c18U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000448U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000c50U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xc473bf2aU), + bswap_32big(0x46a42e51U), + bswap_32big(0xa4d217daU), + bswap_32big(0xbfb671d1U)); + } + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x0355abfbU), + bswap_32big(0x18e483aaU), + bswap_32big(0x161a8e9fU), + bswap_32big(0xf5967a10U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000410U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x23376590U), + bswap_32big(0xcd87c03dU), + bswap_32big(0x1a528762U), + bswap_32big(0x4acd41e8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x000001e0U); + WR1_PROG(REG_1018H, 0x00000410U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000410U); + WR1_PROG(REG_1018H, 0x000001e0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000218U); + WR1_PROG(REG_1018H, 0x00000448U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000448U); + WR1_PROG(REG_1018H, 0x00000218U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000250U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xff680518U), bswap_32big(0x150684b3U), + bswap_32big(0x66b68592U), bswap_32big(0x11e68d29U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x1ab4a112U), bswap_32big(0xac4ff13aU), + bswap_32big(0x73d9c968U), bswap_32big(0xbccf389eU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x08207576U), bswap_32big(0xb0876031U), + bswap_32big(0xbe02366aU), bswap_32big(0x98d40b69U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x494d6ab3U), bswap_32big(0x2b0419b8U), + bswap_32big(0xb6413d30U), bswap_32big(0x85fb4c3dU)); + } + } + else + { + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000410U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000001e0U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000448U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000218U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x43db0358U), + bswap_32big(0x2421207aU), + bswap_32big(0x538c2a41U), + bswap_32big(0xd23b7161U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x85a97f2cU), + bswap_32big(0x98542558U), + bswap_32big(0x87dc8542U), + bswap_32big(0xadfdcfe9U)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + r_rsip_func101(bswap_32big(0xda515a95U), + bswap_32big(0x0ae54391U), + bswap_32big(0xf971d725U), + bswap_32big(0x12effeadU)); + } + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002c20U); + + r_rsip_func101(bswap_32big(0xcf82e310U), + bswap_32big(0x80400a11U), + bswap_32big(0xf626f417U), + bswap_32big(0x41ddf4b9U)); + } + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xa9c2f93bU), bswap_32big(0xa56e6923U), bswap_32big(0xf246bba2U), + bswap_32big(0x901afc75U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xef29384aU), + bswap_32big(0x0700f5eaU), + bswap_32big(0xd0de216aU), + bswap_32big(0x9d78b6ddU)); + } + else + { + r_rsip_func100(bswap_32big(0x6d519652U), + bswap_32big(0x80fee761U), + bswap_32big(0xc5185804U), + bswap_32big(0x22eb277fU)); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x7c89e1c7U), + bswap_32big(0x3d2e5e0bU), + bswap_32big(0x379e89ddU), + bswap_32big(0xabea5a9dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x6d627810U), + bswap_32big(0x35e43526U), + bswap_32big(0x40c4f31aU), + bswap_32big(0xa2d2783dU)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x797935bbU); + + r_rsip_func101(bswap_32big(0x7e0febccU), + bswap_32big(0x8ecc0d2cU), + bswap_32big(0x0866f419U), + bswap_32big(0x5cc06743U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xb3399aa0U), bswap_32big(0x0acd36d6U), bswap_32big(0x91809d58U), + bswap_32big(0x950b891bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xf8895b73U), bswap_32big(0x9bbefb9aU), bswap_32big(0x3d118738U), + bswap_32big(0xae1b1a1aU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1608H, 0x818c001eU); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x808c001eU); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x89d8d21fU), bswap_32big(0x25ab1dccU), bswap_32big(0x818dc7ceU), + bswap_32big(0x44dea2f9U)); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p52f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p52f.c new file mode 100644 index 0000000000..58066f6fa0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p52f.c @@ -0,0 +1,144 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p52f (uint32_t OutData_EncCertificateInfo[]) +{ + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000052U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7837c402U), + bswap_32big(0x7f93686aU), + bswap_32big(0x1794922aU), + bswap_32big(0x646f50fdU)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005202U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4d06f5eaU), + bswap_32big(0xb0564afdU), + bswap_32big(0xb6e2f911U), + bswap_32big(0x69d8d027U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x013a8e02U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005202U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x556c74cdU), + bswap_32big(0x8f7abcefU), + bswap_32big(0x27a3d91aU), + bswap_32big(0xe12e0bc5U)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x00000884U); + + r_rsip_func100(bswap_32big(0xbef22b11U), + bswap_32big(0xbecfa02cU), + bswap_32big(0x030631f7U), + bswap_32big(0x83206983U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + + WR1_PROG(REG_1608H, 0x81900004U); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[9]); + + r_rsip_func100(bswap_32big(0xe81f6f37U), + bswap_32big(0xc62167beU), + bswap_32big(0xe9f99abaU), + bswap_32big(0x03f64998U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[13]); + + r_rsip_func100(bswap_32big(0x7902fa73U), + bswap_32big(0x4b70644dU), + bswap_32big(0xa5d8617bU), + bswap_32big(0x9faa2747U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[17]); + + r_rsip_func100(bswap_32big(0x544f39f7U), + bswap_32big(0x9d970e29U), + bswap_32big(0xbe204d09U), + bswap_32big(0x563157b0U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncCertificateInfo[0]); + + r_rsip_func102(bswap_32big(0x94263f9aU), + bswap_32big(0x6d606824U), + bswap_32big(0x4d748050U), + bswap_32big(0x37f46c6cU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p52i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p52i.c new file mode 100644 index 0000000000..843f0a946d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p52i.c @@ -0,0 +1,1221 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p52i (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00520001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005201U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x824797a5U), + bswap_32big(0x57f03067U), + bswap_32big(0xfd436db2U), + bswap_32big(0x5ad5c06dU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005201U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6d9f385aU), + bswap_32big(0x4c62006eU), + bswap_32big(0xb062d09dU), + bswap_32big(0x99601c4aU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x40000900U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80a80001U); + for (iLoop = 0U; iLoop < 40U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[41]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xb6478413U), + bswap_32big(0xd608b3e9U), + bswap_32big(0x3fa0458eU), + bswap_32big(0xd3ef200aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x5df08693U), bswap_32big(0x23dca38aU), bswap_32big(0x4fa252f5U), + bswap_32big(0x71e40057U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000fc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8090001fU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000100U); + + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0x08008107U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WR1_PROG(REG_1608H, 0x8184001eU); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000052U)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0x51e95866U), bswap_32big(0x4b4b88d8U), bswap_32big(0x940769e3U), + bswap_32big(0x97ded03bU)); + r_rsip_func086(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x18e00000U); + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x00000900U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19300000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[24]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[28]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[32]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[36]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11b80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000980U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x671645acU), bswap_32big(0xbcb0f4eaU), bswap_32big(0xf5670500U), + bswap_32big(0xf6cf6767U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x3e87889dU), bswap_32big(0xb685bb8fU), bswap_32big(0xb7379a85U), + bswap_32big(0x35cac746U)); + } + else + { + r_rsip_func100(bswap_32big(0x7dee736eU), bswap_32big(0x97b785e8U), bswap_32big(0xff3026ebU), + bswap_32big(0x08c724a4U)); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8190001fU); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1400H, 0x00c002d1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000a70U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1608H, 0x81940001U); + WR1_PROG(REG_1400H, 0x00c90051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000009d0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000050U); + WR1_PROG(REG_1608H, 0x8194001fU); + WR1_PROG(REG_1400H, 0x00c90051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000a20U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xf26d12b0U), bswap_32big(0x890fd41cU), bswap_32big(0x90f155b5U), + bswap_32big(0x40a7d1a6U)); + r_rsip_func087(InData_DomainParam); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000ac0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000b10U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a70U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000b60U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000ac0U); + WR1_PROG(REG_1018H, 0x000009d0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x000009d0U); + WR1_PROG(REG_1018H, 0x00000ac0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000b10U); + WR1_PROG(REG_1018H, 0x00000a20U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a20U); + WR1_PROG(REG_1018H, 0x00000b10U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x90b11d19U), bswap_32big(0x65d28bc0U), bswap_32big(0xae735e97U), + bswap_32big(0xf8af19c7U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000a70U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000c50U); + + WR1_PROG(REG_1004H, 0x09090013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x0285fb79U), + bswap_32big(0x354a5edaU), + bswap_32big(0xffdde4b0U), + bswap_32big(0x30decf2cU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000c50U); + + WR1_PROG(REG_1004H, 0x09090014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x67099a2cU), + bswap_32big(0x2a99e0bbU), + bswap_32big(0x3945d716U), + bswap_32big(0x96730fd7U)); + } + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1404H, 0x14380000U); + WR1_PROG(REG_1608H, 0x80920001U); + WR1_PROG(REG_1400H, 0x03430049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1404H, 0x12f80000U); + WR1_PROG(REG_1608H, 0x80920001U); + WR1_PROG(REG_1400H, 0x03430049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000034a1U); + + WR1_PROG(REG_1600H, 0x00026ca5U); + + WR1_PROG(REG_1600H, 0x00003865U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x00003885U); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x01816ca3U); + WR1_PROG(REG_1600H, 0x01816ca4U); + WR1_PROG(REG_1600H, 0x00016c63U); + WR1_PROG(REG_1600H, 0x00016c84U); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x4070a5ecU), + bswap_32big(0xdd122245U), + bswap_32big(0xfeaccb35U), + bswap_32big(0x4158107cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x6917eb4cU), + bswap_32big(0xd573edf6U), + bswap_32big(0x75ef757dU), + bswap_32big(0x44550d26U)); + } + else + { + r_rsip_func101(bswap_32big(0x3efacb03U), + bswap_32big(0x1f428bb3U), + bswap_32big(0x976e22d4U), + bswap_32big(0x6ba8fa12U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x6f33f103U), + bswap_32big(0x3c2c321fU), + bswap_32big(0x67169cdcU), + bswap_32big(0xed19607fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x38bada99U), + bswap_32big(0xd983abb7U), + bswap_32big(0x31b5111fU), + bswap_32big(0x01d5fdffU)); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1014H, 0x000009d0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a20U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000430U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a70U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x53135a18U), + bswap_32big(0x477a48f6U), + bswap_32big(0x0700cfeeU), + bswap_32big(0x6b20099eU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1014H, 0x00000ac0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000b10U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000430U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x29d6e969U), + bswap_32big(0xa615a87cU), + bswap_32big(0x879aadbeU), + bswap_32big(0x58244593U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1014H, 0x00000bb0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003e0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000c00U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000430U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000c50U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x2c987b91U), + bswap_32big(0xb435fac6U), + bswap_32big(0x2a36dcbeU), + bswap_32big(0xccc77745U)); + } + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x85def7abU), + bswap_32big(0x3df249c1U), + bswap_32big(0x0d379028U), + bswap_32big(0xe731bc9dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x0205d824U), + bswap_32big(0x1b807af9U), + bswap_32big(0xa64a8f6aU), + bswap_32big(0xbc2aae1dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000430U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000250U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x43e4ac35U), bswap_32big(0x051b1a08U), + bswap_32big(0x3e8adc2cU), bswap_32big(0xffd4833eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x03ccfeacU), bswap_32big(0xe7b3d540U), + bswap_32big(0x7a4530aaU), bswap_32big(0x8e0b06f7U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x43805500U), bswap_32big(0x0b91a7abU), + bswap_32big(0xe823e2edU), bswap_32big(0x6e4268ffU)); + } + } + else + { + r_rsip_func101(bswap_32big(0xdca35d74U), bswap_32big(0x4f9525beU), + bswap_32big(0xbbfce4cfU), bswap_32big(0x636d76efU)); + } + } + else + { + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000003e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000430U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xffc56736U), + bswap_32big(0x8f2b3023U), + bswap_32big(0x5e20acedU), + bswap_32big(0x63480805U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x6c158e45U), + bswap_32big(0xeb388015U), + bswap_32big(0x67cd94ecU), + bswap_32big(0x37239cfbU)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + r_rsip_func101(bswap_32big(0x19b24f84U), + bswap_32big(0xa8049242U), + bswap_32big(0x0bb04848U), + bswap_32big(0xb146b9a1U)); + } + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002c20U); + + r_rsip_func101(bswap_32big(0x1359c46bU), + bswap_32big(0xc4d3cb87U), + bswap_32big(0x5849afd5U), + bswap_32big(0x6757139aU)); + } + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0x00000012U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12580000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xab19cb2cU), bswap_32big(0xb8b9136dU), bswap_32big(0x7ab537f4U), + bswap_32big(0x989708dcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x0be21a3dU), + bswap_32big(0x49787983U), + bswap_32big(0xfc759863U), + bswap_32big(0xe10cff0cU)); + } + else + { + r_rsip_func100(bswap_32big(0xb9df1864U), + bswap_32big(0x63892907U), + bswap_32big(0x393daf28U), + bswap_32big(0xc0c2e403U)); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x2aad7b9aU), + bswap_32big(0x7805b595U), + bswap_32big(0xcc9ee34aU), + bswap_32big(0xcdd3fadeU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x1383a66dU), + bswap_32big(0x58ee3130U), + bswap_32big(0x9642ad83U), + bswap_32big(0x0bf0d658U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x797935bbU); + + r_rsip_func101(bswap_32big(0x6d6e38e9U), + bswap_32big(0x9cf5cc55U), + bswap_32big(0x05a3fb49U), + bswap_32big(0xe9df2eb8U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x7f3cc6fdU), bswap_32big(0xcbc5ff8aU), bswap_32big(0x4e40b518U), + bswap_32big(0x7ee4bd1aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x44b00eacU), bswap_32big(0x8ca4259bU), bswap_32big(0x023f9e55U), + bswap_32big(0xb10c9afaU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0x08008107U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WR1_PROG(REG_1608H, 0x8184001eU); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc7e2b884U), bswap_32big(0xbcc4794aU), bswap_32big(0x4936fa9fU), + bswap_32big(0x9a9fd61cU)); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p56.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p56.c new file mode 100644 index 0000000000..e5458212b6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p56.c @@ -0,0 +1,320 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p56 (const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00560001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000056U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x358d49b5U), + bswap_32big(0x24c3c5faU), + bswap_32big(0x32ae44ffU), + bswap_32big(0xb5b58203U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000cU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000056U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5fa5e15aU), + bswap_32big(0x9dd80535U), + bswap_32big(0x8d1aee98U), + bswap_32big(0x5bf7e78aU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000043c2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1404H, 0x15300000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[65]); + + WR1_PROG(REG_1404H, 0x12200000U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[69]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xdee42f8aU), + bswap_32big(0x7f520b5cU), + bswap_32big(0xbf2dbce6U), + bswap_32big(0x9bff0ed0U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xbf753718U), bswap_32big(0x0ff970a8U), bswap_32big(0x2e4f34c4U), + bswap_32big(0xa6a72cc5U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00003fc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x30d1998fU), bswap_32big(0x14f67a76U), bswap_32big(0xf3889521U), + bswap_32big(0xf666aa14U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe9435e61U), bswap_32big(0xc0eee543U), bswap_32big(0x22263b46U), + bswap_32big(0x1f68ffdeU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x248f6731U), bswap_32big(0x319c5754U), bswap_32big(0x42be7eb0U), + bswap_32big(0x26590ab8U)); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000228U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x0120000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1404H, 0x17380000U); + + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_143CH, 0x00602000U); + + r_rsip_func100(bswap_32big(0x1416a069U), + bswap_32big(0x56f09d24U), + bswap_32big(0x00590724U), + bswap_32big(0x79b9079aU)); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x50357cc7U), + bswap_32big(0x82528c27U), + bswap_32big(0xc5eef684U), + bswap_32big(0xef8c7759U)); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + + r_rsip_func100(bswap_32big(0x49f29defU), bswap_32big(0x50a7faa2U), bswap_32big(0x75437eb1U), + bswap_32big(0x3e1ea0bbU)); + WR1_PROG(REG_1408H, 0x00020000U); + + r_rsip_func102(bswap_32big(0x41d7454aU), bswap_32big(0x8eeed798U), bswap_32big(0xeb6467aaU), + bswap_32big(0x7cd849a8U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p57.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p57.c new file mode 100644 index 0000000000..6b855c1a94 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p57.c @@ -0,0 +1,321 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p57 (const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00570001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000057U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe15a983dU), + bswap_32big(0x25e4dbb2U), + bswap_32big(0xe2cb762dU), + bswap_32big(0x5e6f04c0U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000dU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000057U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf4191e9bU), + bswap_32big(0x041bc057U), + bswap_32big(0x3ab4533dU), + bswap_32big(0x6216fc62U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00007fc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x15300000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + + WR1_PROG(REG_1404H, 0x13280000U); + for (iLoop = 64U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[129]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x6aee409aU), + bswap_32big(0x3321046bU), + bswap_32big(0x152f14cfU), + bswap_32big(0x99f21627U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0c5b5bf2U), bswap_32big(0x3c3a9775U), bswap_32big(0xc7dbf5d5U), + bswap_32big(0x11bac0e2U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00003fc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x2ec44c3dU), bswap_32big(0xcbf25f29U), bswap_32big(0x5348411fU), + bswap_32big(0xf1f61fe5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe2d44466U), bswap_32big(0x3a8d162aU), bswap_32big(0xb56eca9fU), + bswap_32big(0x6ca90f50U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x9b3c92c6U), bswap_32big(0x4f694f8fU), bswap_32big(0xed239c4bU), + bswap_32big(0xd74e8cfcU)); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1404H, 0x17380000U); + + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_143CH, 0x00602000U); + + r_rsip_func100(bswap_32big(0x014ba15aU), + bswap_32big(0x7f4c137eU), + bswap_32big(0x3bbe1a5cU), + bswap_32big(0xe79546b3U)); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x4aec129dU), + bswap_32big(0xe4bad574U), + bswap_32big(0x6c904ba2U), + bswap_32big(0xbd7c9ff8U)); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + + r_rsip_func100(bswap_32big(0x7ac71450U), bswap_32big(0xe6c53a4eU), bswap_32big(0xb051db8cU), + bswap_32big(0xdf66788eU)); + WR1_PROG(REG_1408H, 0x00020000U); + + r_rsip_func102(bswap_32big(0xb1cb1895U), bswap_32big(0xf9bf12ecU), bswap_32big(0x52b3c1b8U), + bswap_32big(0xde7fb8f0U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5e.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5e.c new file mode 100644 index 0000000000..b34a1df5ab --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5e.c @@ -0,0 +1,538 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p5e (const uint32_t InData_PubKeyType[], + const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_DomainParam[], + uint32_t OutData_EncSecret[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x005e0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0x9ec81dc5U), + bswap_32big(0x86a5f7bfU), + bswap_32big(0xfc961526U), + bswap_32big(0x5ecad9e4U)); + r_rsip_func078(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005e01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x22707a71U), + bswap_32big(0x31419731U), + bswap_32big(0x9631ab58U), + bswap_32big(0x8e3b21f2U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000021U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005e01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa2f406b9U), + bswap_32big(0xc6ff63bfU), + bswap_32big(0x0f3ba4dfU), + bswap_32big(0x186d194dU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x13000000U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xb534c47cU), + bswap_32big(0x460553cfU), + bswap_32big(0xffd9ab01U), + bswap_32big(0xf1496075U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xc3187250U), bswap_32big(0x643e388cU), bswap_32big(0x59b298e7U), + bswap_32big(0x404437b6U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000f7bU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x21f4316cU), bswap_32big(0x6812877bU), bswap_32big(0xb6353afeU), + bswap_32big(0xdb4ffc30U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x00000fd0U); + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_ADDR((&(REG_00D0H))[iLoop / 4], &InData_PubKey[0 + (iLoop / 4)]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x00000fd0U); + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_ADDR((&(REG_0120H))[iLoop / 4], &InData_PubKey[16 + (iLoop / 4)]); + iLoop = iLoop + 4U; + } + + r_rsip_func101(bswap_32big(0x720ea1c9U), bswap_32big(0x509767cbU), bswap_32big(0xd4b5ad8cU), + bswap_32big(0xf606a66dU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005e02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x750dba55U), bswap_32big(0xf32bcd6cU), bswap_32big(0x8ef2d430U), + bswap_32big(0x94eb9988U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005e02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xace84df0U), bswap_32big(0x78a593eaU), bswap_32big(0x65d2b1c6U), + bswap_32big(0x50c53192U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1404H, 0x10d00000U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[1 + iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x11200000U); + + for (iLoop = 16; iLoop < 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[1 + iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x665ae25fU), bswap_32big(0xca1b48c7U), bswap_32big(0x65e2d8f3U), + bswap_32big(0x4c74b596U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe03e2e65U), + bswap_32big(0x2a928c08U), + bswap_32big(0x9bc7a7dbU), + bswap_32big(0xccd11a61U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x6df9e95cU), + bswap_32big(0xff4b6e67U), + bswap_32big(0x286c4209U), + bswap_32big(0x29649bc4U)); + } + } + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000890U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x08080005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000008e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x08080005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xf9261bc1U), bswap_32big(0xd6eaa74eU), bswap_32big(0xe3fae5a7U), + bswap_32big(0xe8b40460U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0658321aU), bswap_32big(0x3e292b30U), bswap_32big(0x88c93ec2U), + bswap_32big(0xef3abf45U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000208U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001c0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000005eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0a0b6ae8U), bswap_32big(0xb114e1eeU), bswap_32big(0xe370d62eU), + bswap_32big(0xce8d26f0U)); + r_rsip_func090(); + + r_rsip_func100(bswap_32big(0x49c88b2bU), bswap_32big(0xdc0090b7U), bswap_32big(0x34344d74U), + bswap_32big(0xa064f96aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x27b9a001U), + bswap_32big(0x37c6afa0U), + bswap_32big(0xede4928fU), + bswap_32big(0x297f3a72U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000005eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x702bd440U), + bswap_32big(0x5b3ea5b1U), + bswap_32big(0x9bd39d87U), + bswap_32big(0xb2a75b85U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005e03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x92330e87U), + bswap_32big(0x643389e0U), + bswap_32big(0xf25824c8U), + bswap_32big(0x7421bb3eU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x015d7825U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005e03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x174d22bcU), + bswap_32big(0xf26e30bfU), + bswap_32big(0x5407034eU), + bswap_32big(0xa17ba109U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x7e29937dU), + bswap_32big(0x61bc20caU), + bswap_32big(0xaef4813bU), + bswap_32big(0x632b9baaU)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x93d49611U), + bswap_32big(0x929805f6U), + bswap_32big(0x31345036U), + bswap_32big(0xb9a57ec4U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[1 + iLoop]); + r_rsip_func100(bswap_32big(0x62ef240fU), + bswap_32big(0x0b0221caU), + bswap_32big(0xb85408d3U), + bswap_32big(0x69196231U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[5 + iLoop]); + + r_rsip_func100(bswap_32big(0x7f39e817U), + bswap_32big(0x646ce88eU), + bswap_32big(0x24272f19U), + bswap_32big(0x4ed2645fU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncSecret[0]); + + r_rsip_func102(bswap_32big(0x8e7c47bcU), + bswap_32big(0xed24f5d3U), + bswap_32big(0x39f9ef60U), + bswap_32big(0x70f95a1cU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5ff.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5ff.c new file mode 100644 index 0000000000..e7644ff8ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5ff.c @@ -0,0 +1,144 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p5ff (uint32_t OutData_EncCertificateInfo[]) +{ + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000005fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc580920dU), + bswap_32big(0x4062ba0fU), + bswap_32big(0xf609c187U), + bswap_32big(0xd3278b49U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005f02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4b0c1dbbU), + bswap_32big(0xf1e969feU), + bswap_32big(0x19f48baaU), + bswap_32big(0xb48034aaU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x013a8e02U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005f02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x18d94c6cU), + bswap_32big(0xa15d68edU), + bswap_32big(0x6d03a83fU), + bswap_32big(0x94c4a260U)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x00000884U); + + r_rsip_func100(bswap_32big(0x944ef033U), + bswap_32big(0x78b9cf50U), + bswap_32big(0x8a33f2e8U), + bswap_32big(0x6469c773U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + + WR1_PROG(REG_1608H, 0x81900004U); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[9]); + + r_rsip_func100(bswap_32big(0x626704dbU), + bswap_32big(0x76badd87U), + bswap_32big(0xab4d1df8U), + bswap_32big(0x8dd6627bU)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[13]); + + r_rsip_func100(bswap_32big(0xb04f5418U), + bswap_32big(0x5bc09678U), + bswap_32big(0x9e776ebeU), + bswap_32big(0xdede2f15U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[17]); + + r_rsip_func100(bswap_32big(0xf4ca1fffU), + bswap_32big(0xc38def93U), + bswap_32big(0xa1cb42a0U), + bswap_32big(0xdb5d4967U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncCertificateInfo[0]); + + r_rsip_func102(bswap_32big(0xc4647677U), + bswap_32big(0xff9b81a5U), + bswap_32big(0x84436d5bU), + bswap_32big(0xeea12833U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5fi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5fi.c new file mode 100644 index 0000000000..4c83fd8f88 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p5fi.c @@ -0,0 +1,1222 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p5fi (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x005f0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005f01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x14f5ff4aU), + bswap_32big(0xd670bef1U), + bswap_32big(0xf2d71c66U), + bswap_32big(0xa02338c3U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00005f01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x852a94f6U), + bswap_32big(0x0df68518U), + bswap_32big(0x3ba54f3dU), + bswap_32big(0x2dba871bU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80a00001U); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17 + iLoop]); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[33]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x86cc11c5U), + bswap_32big(0x4c37c1cfU), + bswap_32big(0x239e84a6U), + bswap_32big(0x960edb12U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd42abd63U), bswap_32big(0x281b47d9U), bswap_32big(0xb8e26af4U), + bswap_32big(0x8763ce98U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000fc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8090001fU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000100U); + + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0x08008107U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WR1_PROG(REG_1608H, 0x8184001eU); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000005fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0xe8131870U), bswap_32big(0xff52cbcdU), bswap_32big(0xcb537efbU), + bswap_32big(0xdaf09b0aU)); + r_rsip_func078(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x18f00000U); + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x00000700U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19400000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[24]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[28]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000980U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xd1fbc162U), bswap_32big(0xe20f739fU), bswap_32big(0xc0602066U), + bswap_32big(0x215f30eaU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xd5838959U), bswap_32big(0x19bb59c6U), bswap_32big(0x59985b7aU), + bswap_32big(0x203e0838U)); + } + else + { + r_rsip_func100(bswap_32big(0xb3995d73U), bswap_32big(0x8d9031e9U), bswap_32big(0x9e6491c6U), + bswap_32big(0xa5e779b0U)); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8190001fU); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19800000U); + WR1_PROG(REG_1400H, 0x00c002d1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000a70U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002a8U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1608H, 0x81900001U); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000009e0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1608H, 0x8190001fU); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000a28U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xe09be6d1U), bswap_32big(0x2242d919U), bswap_32big(0xe7b16682U), + bswap_32big(0x8fc18a8eU)); + r_rsip_func079(InData_DomainParam); + + WR1_PROG(REG_1014H, 0x000001c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000ad0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000208U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000b18U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a70U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000b60U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000ad0U); + WR1_PROG(REG_1018H, 0x000009e0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x000009e0U); + WR1_PROG(REG_1018H, 0x00000ad0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000b18U); + WR1_PROG(REG_1018H, 0x00000a28U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000a28U); + WR1_PROG(REG_1018H, 0x00000b18U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x9711a114U), bswap_32big(0x442e5613U), bswap_32big(0xd2104118U), + bswap_32big(0x802c1395U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000a70U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000c50U); + + WR1_PROG(REG_1004H, 0x08080013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x11b79db5U), + bswap_32big(0x1aba9207U), + bswap_32big(0x0efe17bfU), + bswap_32big(0x369da93eU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000c50U); + + WR1_PROG(REG_1004H, 0x08080014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x8b485f09U), + bswap_32big(0xce2bcdacU), + bswap_32big(0xd1480dbeU), + bswap_32big(0x69c108a1U)); + } + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1404H, 0x14400000U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1400H, 0x03430041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1404H, 0x13000000U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1400H, 0x03430041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000034a1U); + + WR1_PROG(REG_1600H, 0x00026ca5U); + + WR1_PROG(REG_1600H, 0x00003865U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x00003885U); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x01816ca3U); + WR1_PROG(REG_1600H, 0x01816ca4U); + WR1_PROG(REG_1600H, 0x00016c63U); + WR1_PROG(REG_1600H, 0x00016c84U); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x4304b1c3U), + bswap_32big(0x8043e874U), + bswap_32big(0x766162beU), + bswap_32big(0x9579dacbU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x79341e0eU), + bswap_32big(0x4fc54342U), + bswap_32big(0x83f41afdU), + bswap_32big(0x9b47de33U)); + } + else + { + r_rsip_func101(bswap_32big(0x14a478c2U), + bswap_32big(0xf427bcb2U), + bswap_32big(0x92afb93aU), + bswap_32big(0xb0971002U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x30885ff3U), + bswap_32big(0x26d5a0adU), + bswap_32big(0xe40b1f32U), + bswap_32big(0x33a46184U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x97c381c6U), + bswap_32big(0x72d6f91eU), + bswap_32big(0xb191e2edU), + bswap_32big(0x9b79b148U)); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1014H, 0x000009e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003f0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a28U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000438U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000a70U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x37c03066U), + bswap_32big(0xc58756deU), + bswap_32big(0x6ef8bee4U), + bswap_32big(0xeb9d65aaU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1014H, 0x00000ad0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003f0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000b18U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000438U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xe60eb951U), + bswap_32big(0xeaa1cddaU), + bswap_32big(0x5abcda3eU), + bswap_32big(0x3a8315adU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1014H, 0x00000bc0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003f0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000c08U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000438U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000c50U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xc1f6e268U), + bswap_32big(0x81135f76U), + bswap_32big(0x7e8c2439U), + bswap_32big(0xd53a4128U)); + } + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x42e0b694U), + bswap_32big(0xb92dbe55U), + bswap_32big(0x85958a49U), + bswap_32big(0xd84a8177U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x000003f0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x284ed7baU), + bswap_32big(0x84998a8fU), + bswap_32big(0xb41ad3d5U), + bswap_32big(0x9dfcbbf1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x000001c0U); + WR1_PROG(REG_1018H, 0x000003f0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x000003f0U); + WR1_PROG(REG_1018H, 0x000001c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000208U); + WR1_PROG(REG_1018H, 0x00000438U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000438U); + WR1_PROG(REG_1018H, 0x00000208U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000250U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xfd2a4a4dU), bswap_32big(0xdbd7f245U), + bswap_32big(0xb221a381U), bswap_32big(0x3e3239eaU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xb302f2c4U), bswap_32big(0x27371218U), + bswap_32big(0x6aad2245U), bswap_32big(0xd0ab66dfU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080014U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x9bf656f8U), bswap_32big(0x5bb23bd5U), + bswap_32big(0x45135387U), bswap_32big(0xb6d43e03U)); + } + } + else + { + r_rsip_func101(bswap_32big(0xe7ccefeaU), bswap_32big(0xc19ee188U), + bswap_32big(0x98b43ed0U), bswap_32big(0x8fa5ac12U)); + } + } + else + { + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000003f0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000001c0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000438U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000208U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x82d351a8U), + bswap_32big(0x71068ad1U), + bswap_32big(0x5d88792fU), + bswap_32big(0xe21262fcU)); + } + } + else + { + r_rsip_func101(bswap_32big(0xd899b2e0U), + bswap_32big(0x2f4a67ebU), + bswap_32big(0x92de9931U), + bswap_32big(0x9658b8e4U)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + r_rsip_func101(bswap_32big(0xe3f9fb58U), + bswap_32big(0x992b70fcU), + bswap_32big(0x2ae296b7U), + bswap_32big(0x6704c5e6U)); + } + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002c20U); + + r_rsip_func101(bswap_32big(0x2074f063U), + bswap_32big(0x1a6ec197U), + bswap_32big(0x3d14eedcU), + bswap_32big(0x2a71438bU)); + } + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xcc7d3a82U), bswap_32big(0xfa8f1b52U), bswap_32big(0xc4377cfaU), + bswap_32big(0x4bbc4600U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x63e9b9feU), + bswap_32big(0xfcf0f282U), + bswap_32big(0xc7c86e4eU), + bswap_32big(0x235cf277U)); + } + else + { + r_rsip_func100(bswap_32big(0xe24de367U), + bswap_32big(0x198b18f1U), + bswap_32big(0x394368d8U), + bswap_32big(0x96bce89aU)); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x282a5db5U), + bswap_32big(0xaa96282dU), + bswap_32big(0xd9c6bb6dU), + bswap_32big(0x142f971bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x850ee47cU), + bswap_32big(0xc5203495U), + bswap_32big(0xdf3995c0U), + bswap_32big(0xbdaef5c9U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x797935bbU); + + r_rsip_func101(bswap_32big(0xd4c8e979U), + bswap_32big(0x97f1c61aU), + bswap_32big(0x9b73d8cbU), + bswap_32big(0x5143ff61U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x4b66efe5U), bswap_32big(0xb3cffb0bU), bswap_32big(0xd277b0eaU), + bswap_32big(0xd1a18e8dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xfa34f86bU), bswap_32big(0x78d78ecbU), bswap_32big(0x0b94a562U), + bswap_32big(0xaae0540eU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0x08008107U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WR1_PROG(REG_1608H, 0x8184001eU); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p6f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p6f.c new file mode 100644 index 0000000000..0936384df2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p6f.c @@ -0,0 +1,193 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p6f (const uint32_t InData_LC[], + const uint32_t InData_Cmd[], + const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x006f0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + r_rsip_func048(InData_LC); + + r_rsip_func049(InData_Cmd); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x0000000aU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1600H, 0x0000002cU); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1600H, 0x200053e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x2192d7bdU), + bswap_32big(0x98aa65abU), + bswap_32big(0x824b40c0U), + bswap_32big(0x33867febU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x4035902bU), bswap_32big(0x80fd57c8U), bswap_32big(0x945202cdU), + bswap_32big(0x876b606eU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, S_INST2[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000006fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2ccf4d29U), bswap_32big(0x4ba91dd9U), bswap_32big(0x7e94d7a2U), + bswap_32big(0x51efeb9dU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x000000ffU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000006fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x36afbad5U), bswap_32big(0xf81d945aU), bswap_32big(0x2561308aU), + bswap_32big(0x4f6f5627U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x37f30ac5U), bswap_32big(0x75212a82U), bswap_32big(0x056a8b10U), + bswap_32big(0xb78017bbU)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_INST2[0 + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_INST2[0 + 5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x71a6d22bU), bswap_32big(0x9f32e2beU), bswap_32big(0xa66fbb19U), + bswap_32big(0xdd1ef0d8U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_INST2[0 + 9]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010380U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000006fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0fa9e1feU), bswap_32big(0xf0353ffeU), bswap_32big(0xf4f4e510U), + bswap_32big(0xa0ceb99eU)); + r_rsip_func057(InData_IV, InData_InstData, OutData_KeyIndex); + + r_rsip_func100(bswap_32big(0x2e898236U), bswap_32big(0xd993d819U), bswap_32big(0x49a8ad1aU), + bswap_32big(0xbc07b103U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8afc09e1U), bswap_32big(0x5f1090b1U), bswap_32big(0x3385d77fU), + bswap_32big(0x076fa3acU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x3e2e5db3U), bswap_32big(0xb28ee6a4U), bswap_32big(0x905c2b63U), + bswap_32big(0xcd5d0ebaU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func102(bswap_32big(0xdfbd6955U), bswap_32big(0xc823e0f0U), bswap_32big(0x5693cf2cU), + bswap_32big(0x1a339200U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73f.c new file mode 100644 index 0000000000..43ed22b31f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73f.c @@ -0,0 +1,209 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +rsip_ret_t r_rsip_p73f (const uint32_t InData_Msg[], uint32_t MAX_CNT, uint32_t OutData_MsgDigest[]) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WAIT_STS(REG_2030H, 0U, 1U); + WR1_PROG(REG_1444H, 0x00020064U); + for (iLoop = 0; iLoop < (MAX_CNT & 0xfffffff0U); iLoop = iLoop + 16) + { + WAIT_STS(REG_1444H, 31U, 1U); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 0]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 1]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 2]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 3]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 4]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 5]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 6]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 7]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 8]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 9]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 10]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 11]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 12]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 13]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 14]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 15]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31U, 1U); + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop = iLoop + 1) + { + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 0]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8U, 0U); + WR1_PROG(REG_143CH, 0x00001600U); + WAIT_STS(REG_2030H, 4U, 1U); + r_rsip_func100(bswap_32big(0x613b57a1U), + bswap_32big(0x38d28e4fU), + bswap_32big(0x4b09cd77U), + bswap_32big(0x8bfdc1d0U)); + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x1000b400U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x1000b400U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + if (0x00000000U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0xc75eca98U), bswap_32big(0x1508e263U), bswap_32big(0x8f4ec345U), + bswap_32big(0x120a26f4U)); + WR1_PROG(REG_1408H, 0x00004016U); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + r_rsip_func102(bswap_32big(0x69817aadU), bswap_32big(0x2fb02a70U), bswap_32big(0x66054079U), + bswap_32big(0xef752c92U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + else if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0x847fb73eU), bswap_32big(0xb646991bU), bswap_32big(0x14997e83U), + bswap_32big(0x4395df73U)); + WR1_PROG(REG_1408H, 0x0000401eU); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[5]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[6]); + r_rsip_func102(bswap_32big(0xf1554fc6U), bswap_32big(0x172cf756U), bswap_32big(0xc99402ccU), + bswap_32big(0x1f826902U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0xcffad43aU), bswap_32big(0x6a8ffd50U), bswap_32big(0xf5113be8U), + bswap_32big(0x74dcf42aU)); + WR1_PROG(REG_1408H, 0x00004022U); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[5]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[6]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[7]); + r_rsip_func102(bswap_32big(0x7333795fU), bswap_32big(0x1b3df1e3U), bswap_32big(0xfbad3912U), + bswap_32big(0x873b50f8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + else if (0x00000005U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0xeccf52aaU), bswap_32big(0xcfe6d35aU), bswap_32big(0xab729384U), + bswap_32big(0x91f8352fU)); + WR1_PROG(REG_1408H, 0x00004032U); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[5]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[6]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[7]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[8]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[9]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[10]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[11]); + r_rsip_func102(bswap_32big(0x02b2d092U), bswap_32big(0xa0f3ae9eU), bswap_32big(0xbf85d244U), + bswap_32big(0xd2000f8cU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + else if (0x00000006U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + r_rsip_func100(bswap_32big(0xa5cbf736U), bswap_32big(0x790cf329U), bswap_32big(0xb2d617c5U), + bswap_32big(0xfdd5d816U)); + WR1_PROG(REG_1408H, 0x00004042U); + WAIT_STS(REG_1408H, 30U, 1U); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[0]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[1]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[2]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[3]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[4]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[5]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[6]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[7]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[8]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[9]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[10]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[11]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[12]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[13]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[14]); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[15]); + r_rsip_func102(bswap_32big(0x857b2da2U), bswap_32big(0x1c05c7d2U), bswap_32big(0xc96239a2U), + bswap_32big(0xc51438b2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + } + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73i.c new file mode 100644 index 0000000000..8b02404b42 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73i.c @@ -0,0 +1,138 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +rsip_ret_t r_rsip_p73i (const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + if (0x0U != RD1_MASK(REG_14BCH, 0x1fU)) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00730001U); + WR1_PROG(REG_144CH, 0x00000000U); + r_rsip_func100(bswap_32big(0x10536e75U), + bswap_32big(0x331466a8U), + bswap_32big(0x7eefde91U), + bswap_32big(0xe28e803fU)); + WR1_PROG(REG_2000H, 0x00000001U); + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_ADDR(REG_1420H, &InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b400U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + if (0x00000000U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000000U); + r_rsip_func101(bswap_32big(0xd96bfc9eU), bswap_32big(0x487c02b2U), bswap_32big(0xfc75625fU), + bswap_32big(0x6053b6c3U)); + } + else if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000040U); + r_rsip_func101(bswap_32big(0xd82c8e37U), bswap_32big(0x57edf2f6U), bswap_32big(0x44321c10U), + bswap_32big(0x9549981fU)); + } + else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000050U); + r_rsip_func101(bswap_32big(0x3aa12cabU), bswap_32big(0x7b307f76U), bswap_32big(0x8d4e154cU), + bswap_32big(0x61e17003U)); + } + else if (0x00000003U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000080U); + r_rsip_func101(bswap_32big(0xf197febfU), bswap_32big(0x0acf8d75U), bswap_32big(0x65ffcf05U), + bswap_32big(0xca09fd44U)); + } + else if (0x00000004U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00000090U); + r_rsip_func101(bswap_32big(0xf34ef58fU), bswap_32big(0x907ea3cfU), bswap_32big(0xa313eeecU), + bswap_32big(0x2445166eU)); + } + else if (0x00000005U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x000000a0U); + r_rsip_func101(bswap_32big(0x98d7fc97U), bswap_32big(0xa91c8662U), bswap_32big(0xb76231c5U), + bswap_32big(0xff218a00U)); + } + else if (0x00000006U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x000000b0U); + r_rsip_func101(bswap_32big(0xd91630c6U), bswap_32big(0x254dddb8U), bswap_32big(0x87ef4539U), + bswap_32big(0x831051b2U)); + } + + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_200CH, 0x00000100U); + r_rsip_func101(bswap_32big(0xd7e4dd58U), bswap_32big(0x6deb38e7U), bswap_32big(0x38547147U), + bswap_32big(0xcea045caU)); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2014H, &InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2010H, &InData_MsgLen[1]); + r_rsip_func101(bswap_32big(0xe64467f0U), bswap_32big(0x1ec38968U), bswap_32big(0xace088cfU), + bswap_32big(0xa6ae0529U)); + } + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73r.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73r.c new file mode 100644 index 0000000000..edc573b10d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73r.c @@ -0,0 +1,138 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +rsip_ret_t r_rsip_p73r (const uint32_t InData_HashType[], const uint32_t InData_State[]) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + if (0x0U != RD1_MASK(REG_14BCH, 0x1fU)) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00730001U); + WR1_PROG(REG_144CH, 0x00000000U); + r_rsip_func100(bswap_32big(0x10536e75U), + bswap_32big(0x331466a8U), + bswap_32big(0x7eefde91U), + bswap_32big(0xe28e803fU)); + WR1_PROG(REG_2000H, 0x00000001U); + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31U, 1U); + WR1_ADDR(REG_1420H, &InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b400U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + if (0x00000000U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001000U); + r_rsip_func101(bswap_32big(0x2e718b88U), bswap_32big(0xdb4b75c2U), bswap_32big(0xb3a8b0acU), + bswap_32big(0xf3e09da0U)); + } + else if (0x00000001U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001040U); + r_rsip_func101(bswap_32big(0xe379ab73U), bswap_32big(0x404c8b84U), bswap_32big(0xe6897dedU), + bswap_32big(0xf7ab42c5U)); + } + else if (0x00000002U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001050U); + r_rsip_func101(bswap_32big(0x2316ff0eU), bswap_32big(0xc5fde60dU), bswap_32big(0x863172d9U), + bswap_32big(0xf9cc187eU)); + } + else if (0x00000003U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001080U); + r_rsip_func101(bswap_32big(0x11f65666U), bswap_32big(0x499bd4a0U), bswap_32big(0xd344b1f9U), + bswap_32big(0xf2a866a5U)); + } + else if (0x00000004U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x00001090U); + r_rsip_func101(bswap_32big(0xac484580U), bswap_32big(0xdefd0225U), bswap_32big(0x8430b2c6U), + bswap_32big(0xfbf4d22fU)); + } + else if (0x00000005U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x000010a0U); + r_rsip_func101(bswap_32big(0xf2ac21deU), bswap_32big(0xa6584e00U), bswap_32big(0xd0dcec5cU), + bswap_32big(0xac5f5b57U)); + } + else if (0x00000006U == RD1_MASK(REG_1440H, 0xffffffffU)) + { + WR1_PROG(REG_2004H, 0x000010b0U); + r_rsip_func101(bswap_32big(0x20311c6cU), bswap_32big(0xfaa52075U), bswap_32big(0x4cabf318U), + bswap_32big(0xecbb34e5U)); + } + + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2014H, &InData_State[18]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2010H, &InData_State[19]); + for (iLoop = 0; iLoop < 18; iLoop = iLoop + 1) + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_ADDR(REG_2028H, &InData_State[iLoop + 0]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + r_rsip_func101(bswap_32big(0xafa17b39U), + bswap_32big(0x8c4f9b53U), + bswap_32big(0x049691c3U), + bswap_32big(0x4a78e698U)); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73s.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73s.c new file mode 100644 index 0000000000..c4ddd4be2c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73s.c @@ -0,0 +1,70 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +rsip_ret_t r_rsip_p73s (uint32_t OutData_State[]) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + for (iLoop = 0; iLoop < 18; iLoop = iLoop + 1) + { + RD1_ADDR(REG_202CH, &OutData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + RD1_ADDR(REG_2014H, &OutData_State[18]); + RD1_ADDR(REG_2010H, &OutData_State[19]); + r_rsip_func102(bswap_32big(0x1727bd13U), + bswap_32big(0x4857d99eU), + bswap_32big(0xe40b45a8U), + bswap_32big(0x2f3fe937U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12U, 0U); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73u.c new file mode 100644 index 0000000000..652a97f068 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p73u.c @@ -0,0 +1,87 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +RSIP_PRV_PRIMITIVE_FUNC + +rsip_ret_t r_rsip_p73u (const uint32_t InData_Msg[], uint32_t MAX_CNT) +{ + uint32_t iLoop; + uint32_t jLoop; + uint32_t kLoop; + uint32_t oLoop; + uint32_t oLoop1; + uint32_t OFS_ADR; + (void) iLoop; + (void) jLoop; + (void) kLoop; + (void) oLoop; + (void) oLoop1; + (void) OFS_ADR; + WAIT_STS(REG_2030H, 0U, 1U); + WR1_PROG(REG_1444H, 0x00020064U); + for (iLoop = 0; iLoop < (MAX_CNT & 0xfffffff0U); iLoop = iLoop + 16) + { + WAIT_STS(REG_1444H, 31U, 1U); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 0]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 1]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 2]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 3]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 4]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 5]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 6]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 7]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 8]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 9]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 10]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 11]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 12]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 13]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 14]); + WR1_ADDR(REG_1420H, &InData_Msg[iLoop + 15]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8U, 0U); + WR1_PROG(REG_143CH, 0x00001600U); + r_rsip_func101(bswap_32big(0x80c0ee56U), + bswap_32big(0xc2fa20dcU), + bswap_32big(0x8bb2b171U), + bswap_32big(0xecb4fa8dU)); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75f.c new file mode 100644 index 0000000000..690ede3751 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75f.c @@ -0,0 +1,352 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75f (const uint32_t InData_Cmd[], + const uint32_t InData_Msg[], + const uint32_t InData_MAC[], + const uint32_t InData_length[], + uint32_t MAX_CNT, + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR16_ADDR(REG_1420H, &InData_Msg[iLoop]); + iLoop = iLoop + 16U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop++) + { + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xc44e575fU), + bswap_32big(0xb39d73feU), + bswap_32big(0x3129abb9U), + bswap_32big(0xefe727d9U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0xc47987c4U), bswap_32big(0x77e43a73U), bswap_32big(0xfb0db761U), + bswap_32big(0x37e78ca7U)); + + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func100(bswap_32big(0x4387084cU), bswap_32big(0x039b42dcU), bswap_32big(0x91e98272U), + bswap_32big(0x64ff31d4U)); + WR1_PROG(REG_1408H, 0x0000401eU); + WAIT_STS(REG_1408H, 30, 1); + RD7_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0xfaa1e43fU), bswap_32big(0x7c268b13U), bswap_32big(0x2e363126U), + bswap_32big(0x3bfa9bd2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func100(bswap_32big(0x22dc5cd1U), bswap_32big(0x3346fef7U), bswap_32big(0x3a0fbc41U), + bswap_32big(0x7009ed0fU)); + WR1_PROG(REG_1408H, 0x00004022U); + WAIT_STS(REG_1408H, 30, 1); + RD8_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0x0960b3c3U), bswap_32big(0xacd09037U), bswap_32big(0x3c995204U), + bswap_32big(0xb984ea7aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + r_rsip_func100(bswap_32big(0x90ed49e7U), bswap_32big(0x098bd813U), bswap_32big(0xa6d6f145U), + bswap_32big(0x235ebf98U)); + WR1_PROG(REG_1408H, 0x00004032U); + WAIT_STS(REG_1408H, 30, 1); + RD12_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0x352f38c8U), bswap_32big(0xee4e235fU), bswap_32big(0xd2dbdcb1U), + bswap_32big(0xc84455c8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + r_rsip_func100(bswap_32big(0x4a510798U), bswap_32big(0xfc029359U), bswap_32big(0x290d7027U), + bswap_32big(0xf32f787aU)); + WR1_PROG(REG_1408H, 0x00004042U); + WAIT_STS(REG_1408H, 30, 1); + RD16_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0xc15fdafaU), bswap_32big(0x628a9928U), bswap_32big(0x29f19258U), + bswap_32big(0x4e26e728U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + + return RSIP_RET_PASS; + } + else + { + r_rsip_func100(bswap_32big(0x935beb89U), bswap_32big(0x093d4062U), bswap_32big(0xf3193d07U), + bswap_32big(0x377e81c4U)); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_length[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x0000001cU); + + r_rsip_func101(bswap_32big(0x39248654U), bswap_32big(0x2b2ead69U), bswap_32big(0x51bf0030U), + bswap_32big(0x0af1a03cU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000020U); + + r_rsip_func101(bswap_32big(0x015e4f5eU), bswap_32big(0x93ac7d35U), bswap_32big(0x505b42c2U), + bswap_32big(0xe78a74abU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000030U); + + r_rsip_func101(bswap_32big(0x0f420d9cU), bswap_32big(0x67696037U), bswap_32big(0xa556cea6U), + bswap_32big(0xf938003dU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000040U); + + r_rsip_func101(bswap_32big(0x445b7f11U), bswap_32big(0x7dfda686U), bswap_32big(0xd59d7715U), + bswap_32big(0x0c6b8496U)); + } + + WR1_PROG(REG_1600H, 0x3420a820U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x34202841U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x288cc714U), bswap_32big(0xb2576d89U), bswap_32big(0x51b3dbd5U), + bswap_32big(0x74dda411U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xa591d5d6U), bswap_32big(0x0db6ba0aU), bswap_32big(0xc58cd089U), + bswap_32big(0xe475a057U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x8baea9e4U), bswap_32big(0x7d429282U), bswap_32big(0x074aeb80U), + bswap_32big(0xbe27aba0U)); + + WR1_PROG(REG_1600H, 0x000008c6U); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x0000a440U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1600H, 0x00046842U); + WR1_PROG(REG_1600H, 0x00026c42U); + + WR1_PROG(REG_1608H, 0x81010040U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + r_rsip_func100(bswap_32big(0xda719471U), + bswap_32big(0x7b6e23daU), + bswap_32big(0x84d9cf3bU), + bswap_32big(0x9e8619abU)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1600H, 0x380088c0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x2000d060U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1600H, 0x2000d060U); + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1608H, 0x80830007U); + WR1_PROG(REG_1400H, 0x0345000dU); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000002c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR3_ADDR(REG_1420H, &InData_MAC[iLoop]); + WR1_PROG(REG_1444H, 0x000000a1U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x29f7ab0aU), + bswap_32big(0xad41feb8U), + bswap_32big(0x65713280U), + bswap_32big(0xfd39715eU)); + } + else + { + WR1_PROG(REG_1608H, 0x80840007U); + WR1_PROG(REG_1400H, 0x03450011U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[iLoop]); + + r_rsip_func101(bswap_32big(0x771de06aU), + bswap_32big(0x427323c3U), + bswap_32big(0x5f6f85f0U), + bswap_32big(0x57bd697cU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000800U); + for (jLoop = 0U; jLoop < 16U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3c0028a1U); + WR1_PROG(REG_1600H, 0x12003c07U); + WR1_PROG(REG_1600H, 0x00002ce0U); + WR1_PROG(REG_1600H, 0x00002ca0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x9c000005U); + WR1_PROG(REG_1600H, 0x000008e7U); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a4c0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x298e2ab0U), + bswap_32big(0x9a2d1b27U), + bswap_32big(0xec3c2ceaU), + bswap_32big(0xd524cbf6U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1600H, 0x000008c2U); + + WR1_PROG(REG_1600H, 0x00007c06U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xaf6f5e67U), bswap_32big(0x773f2216U), bswap_32big(0x094b1d18U), + bswap_32big(0x8548d3f2U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x252b31a1U), + bswap_32big(0x91cc3fbfU), + bswap_32big(0x7447417eU), + bswap_32big(0x435514d4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x5b1ad2ecU), + bswap_32big(0x7e0c8e9cU), + bswap_32big(0x85adf7f4U), + bswap_32big(0xe831d6deU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75i.c new file mode 100644 index 0000000000..e16cbfda1e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75i.c @@ -0,0 +1,273 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75i (const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], + const uint32_t InData_MsgLen[], + uint32_t KEY_INDEX_SIZE) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00750001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x3d9c6768U), + bswap_32big(0xeed11688U), + bswap_32big(0xb81e4821U), + bswap_32big(0x13e0f0b1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe043b90dU), bswap_32big(0xa2048907U), bswap_32big(0xfdb526a5U), + bswap_32big(0x557b06cdU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x40809cadU), bswap_32big(0x8fb81e4fU), bswap_32big(0xf3fa3df5U), + bswap_32big(0x51b4fc88U)); + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b480U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001aU); + + WR1_PROG(REG_2004H, 0x00000040U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0xbf9e5542U), bswap_32big(0x7d579b0dU), bswap_32big(0xc6aed1dfU), + bswap_32big(0x589be1dbU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001bU); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x4623c1f6U), bswap_32big(0x6d8f740fU), bswap_32big(0x2c3b2f07U), + bswap_32big(0x22da1d59U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_2004H, 0x000000a0U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000000cU); + + r_rsip_func101(bswap_32big(0x66326bfbU), bswap_32big(0x0f5f9954U), bswap_32big(0xdb3700c1U), + bswap_32big(0xd5ac02daU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func101(bswap_32big(0xd8fc71b8U), bswap_32big(0x5c272856U), bswap_32big(0x9e4ae5d9U), + bswap_32big(0x5e5c3df8U)); + } + + WR1_PROG(REG_2008H, 0x00000003U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3526cf5cU), bswap_32big(0x5cd9659cU), bswap_32big(0xa7a6c9e7U), + bswap_32big(0xd54caea0U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e5U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcf3bb4bdU), bswap_32big(0x5f4b1c1eU), bswap_32big(0x2015072bU), + bswap_32big(0xadd68673U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + for (iLoop = 0U; iLoop < KEY_INDEX_SIZE - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1400H, 0x01420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x8f90b383U), bswap_32big(0x5eb9a5a9U), bswap_32big(0x9d5d27cfU), + bswap_32big(0x58810b56U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x380008e3U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x3df2ca0dU), bswap_32big(0x9f76b229U), bswap_32big(0x321840daU), + bswap_32big(0x929577afU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xb02910c8U), bswap_32big(0x3c497f61U), bswap_32big(0x29dfba2dU), + bswap_32big(0x69d830ccU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000080U); + + WR1_PROG(REG_200CH, 0x00000001U); + + WAIT_STS(REG_2030H, 8, 0); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000000U); + + WR1_PROG(REG_200CH, 0x00000100U); + + r_rsip_func101(bswap_32big(0x35007ef2U), + bswap_32big(0xeae17f70U), + bswap_32big(0x5941fe37U), + bswap_32big(0x02799ba3U)); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_MsgLen[1]); + + WR1_PROG(REG_200CH, 0x00000001U); + + r_rsip_func101(bswap_32big(0xee738e30U), + bswap_32big(0x088a20d8U), + bswap_32big(0x78bb2b09U), + bswap_32big(0x7a2eb843U)); + } + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75r.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75r.c new file mode 100644 index 0000000000..97d1294865 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75r.c @@ -0,0 +1,251 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75r (const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], + const uint32_t InData_State[], + uint32_t KEY_INDEX_SIZE) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00750001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x3d9c6768U), + bswap_32big(0xeed11688U), + bswap_32big(0xb81e4821U), + bswap_32big(0x13e0f0b1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe043b90dU), bswap_32big(0xa2048907U), bswap_32big(0xfdb526a5U), + bswap_32big(0x557b06cdU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x40809cadU), bswap_32big(0x8fb81e4fU), bswap_32big(0xf3fa3df5U), + bswap_32big(0x51b4fc88U)); + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x2000b480U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001aU); + + WR1_PROG(REG_2004H, 0x00001040U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0xe8603735U), bswap_32big(0x475b57ccU), bswap_32big(0xba493135U), + bswap_32big(0x4dff4c43U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001bU); + + WR1_PROG(REG_2004H, 0x00001050U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x491797b0U), bswap_32big(0x16ebb4fbU), bswap_32big(0xe3618953U), + bswap_32big(0x43e5f95eU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_2004H, 0x000010a0U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000000cU); + + r_rsip_func101(bswap_32big(0x5bd7bc8aU), bswap_32big(0x2697558cU), bswap_32big(0x2ae29db1U), + bswap_32big(0x63c89718U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_2004H, 0x000010b0U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func101(bswap_32big(0xd1fb1242U), bswap_32big(0xa76bb5f3U), bswap_32big(0x49db6405U), + bswap_32big(0xef8046b3U)); + } + + WR1_PROG(REG_2008H, 0x00000003U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x881a15b7U), bswap_32big(0x04c57eddU), bswap_32big(0x9ca1bc1aU), + bswap_32big(0xb7f036dcU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e5U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xff774896U), bswap_32big(0x5f32303dU), bswap_32big(0x6ccc1b06U), + bswap_32big(0x6c1e1a70U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + for (iLoop = 0U; iLoop < KEY_INDEX_SIZE - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1400H, 0x01420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0xa39a5550U), bswap_32big(0xec37e9e5U), bswap_32big(0x17b1b88dU), + bswap_32big(0x421e19a0U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x380008e3U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x42c7d303U), bswap_32big(0x269e96a5U), bswap_32big(0xfd7d36f3U), + bswap_32big(0x71865308U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd87d9593U), bswap_32big(0x990073e2U), bswap_32big(0x77b02d52U), + bswap_32big(0xaefa97d8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_State[18]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_State[19]); + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2028H, InData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf843ec47U), bswap_32big(0x58697af4U), bswap_32big(0x62f1f47cU), + bswap_32big(0xb7f44d3cU)); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75s.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75s.c new file mode 100644 index 0000000000..18eb837fea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75s.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75s (uint32_t OutData_State[]) +{ + uint32_t iLoop = 0U; + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + RD1_ADDR(REG_202CH, &OutData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + RD1_ADDR(REG_2014H, &OutData_State[18]); + RD1_ADDR(REG_2010H, &OutData_State[19]); + + r_rsip_func102(bswap_32big(0x28daed97U), + bswap_32big(0x1af21c2aU), + bswap_32big(0x8392cfe7U), + bswap_32big(0x895daae5U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75u.c new file mode 100644 index 0000000000..3e632ff2c0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p75u.c @@ -0,0 +1,45 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p75u (const uint32_t InData_Msg[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR16_ADDR(REG_1420H, &InData_Msg[iLoop]); + iLoop = iLoop + 16U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + r_rsip_func101(bswap_32big(0x255d49a9U), + bswap_32big(0xbbbf843fU), + bswap_32big(0xd81296bfU), + bswap_32big(0x827440e9U)); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p79.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p79.c new file mode 100644 index 0000000000..0b68c5efb6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p79.c @@ -0,0 +1,326 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p79 (const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00790001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000079U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x35160691U), + bswap_32big(0x38418c60U), + bswap_32big(0x7e6cfa0dU), + bswap_32big(0xec18ff7aU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000eU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000079U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd31c5bdbU), + bswap_32big(0x47594aafU), + bswap_32big(0xa9caa1f7U), + bswap_32big(0x3f455a1eU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000063c2U); + WR1_PROG(REG_1A2CH, 0x40001800U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1404H, 0x14b00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1404H, 0x12200000U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x4cad6ab8U), + bswap_32big(0x603bda8eU), + bswap_32big(0x070a98f1U), + bswap_32big(0xf02cb629U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xb9a5f222U), bswap_32big(0xff18cecfU), bswap_32big(0xa6c6ac21U), + bswap_32big(0x93983646U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x30300010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00005fc2U); + WR1_PROG(REG_1A2CH, 0x40001700U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x10a00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x693235d6U), bswap_32big(0xc550fe1dU), bswap_32big(0xdc3f43c5U), + bswap_32big(0x893492b5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xcd1ce42dU), bswap_32big(0xa7978febU), bswap_32big(0x5150f85cU), + bswap_32big(0x0f5837a2U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x239f5ff8U), bswap_32big(0x253d6bb0U), bswap_32big(0x7ab8ba0cU), + bswap_32big(0x53c49c5dU)); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000228U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x0130000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + + WR1_PROG(REG_1404H, 0x16b80000U); + + for (iLoop = 0U; iLoop < 96U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x4136fe87U), + bswap_32big(0x2615ac89U), + bswap_32big(0xcda38031U), + bswap_32big(0xbc6dd77cU)); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x804a3cd7U), + bswap_32big(0xbb2f7ad7U), + bswap_32big(0xd5cc7693U), + bswap_32big(0x8327cc64U)); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x3d6f6420U), bswap_32big(0x59837082U), bswap_32big(0x999074eaU), + bswap_32big(0x496388f4U)); + WR1_PROG(REG_1408H, 0x00020000U); + + r_rsip_func102(bswap_32big(0xf7fe1c1eU), bswap_32big(0x936a500bU), bswap_32big(0x2d25498bU), + bswap_32big(0x84148d0aU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7a.c new file mode 100644 index 0000000000..fc222ee00b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7a.c @@ -0,0 +1,331 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p7a (const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007a0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1041a559U), + bswap_32big(0x001550c2U), + bswap_32big(0x561de6a0U), + bswap_32big(0xd3f0da52U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000000fU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8b2e6dd2U), + bswap_32big(0x65094f88U), + bswap_32big(0x7a17a94dU), + bswap_32big(0xb0dc0a02U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x0000bfc2U); + WR1_PROG(REG_1A2CH, 0x40001700U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x14b00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40001700U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + + WR1_PROG(REG_1404H, 0x12a80000U); + for (iLoop = 96U; iLoop < 192U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x6531aedaU), + bswap_32big(0x18385a06U), + bswap_32big(0x1be81a92U), + bswap_32big(0x75b087f3U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x11a972caU), bswap_32big(0x69b98d84U), bswap_32big(0x87f03242U), + bswap_32big(0xaaa3befeU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x30300010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00005fc2U); + WR1_PROG(REG_1A2CH, 0x40001700U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x10a00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x6bc74da0U), bswap_32big(0xd569db2fU), bswap_32big(0xe399af50U), + bswap_32big(0x480e4427U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0c497a63U), bswap_32big(0xad71243cU), bswap_32big(0x07d99793U), + bswap_32big(0x2b77c7c2U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xbb8a9004U), bswap_32big(0x90145d93U), bswap_32big(0x7b85bd65U), + bswap_32big(0x46994f37U)); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x30300000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000060U); + + WR1_PROG(REG_1404H, 0x16b80000U); + + for (iLoop = 0U; iLoop < 96U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x337a3220U), + bswap_32big(0xdeeed72aU), + bswap_32big(0xe100271cU), + bswap_32big(0xe9a9a698U)); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0xb49e12c7U), + bswap_32big(0x5d3ba4aaU), + bswap_32big(0x563d32d1U), + bswap_32big(0xc838de88U)); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xfeee56e5U), bswap_32big(0xa84dd085U), bswap_32big(0x1a7573f9U), + bswap_32big(0xbfd26526U)); + WR1_PROG(REG_1408H, 0x00020000U); + + r_rsip_func102(bswap_32big(0x4f8a2893U), bswap_32big(0x59f837d4U), bswap_32big(0xa451f922U), + bswap_32big(0xb6162953U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7b.c new file mode 100644 index 0000000000..6d821a35ab --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7b.c @@ -0,0 +1,329 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p7b (const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007b0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd88a9323U), + bswap_32big(0xac15817dU), + bswap_32big(0x7a8dccb2U), + bswap_32big(0xedac177eU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xeab30cfcU), + bswap_32big(0x094e41c8U), + bswap_32big(0x5dac815cU), + bswap_32big(0xa908940aU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00007fc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1404H, 0x14300000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1404H, 0x12200000U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xd100ac3aU), + bswap_32big(0x88a81617U), + bswap_32big(0x75349f37U), + bswap_32big(0x4ff20412U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x5322588bU), bswap_32big(0x53bc4fc4U), bswap_32big(0x22380c7fU), + bswap_32big(0x13e9d41fU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x40400010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00007fc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x10200000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x61a5d5e2U), bswap_32big(0x72779226U), bswap_32big(0xa0a7a89aU), + bswap_32big(0x3f3d1e28U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x3ccd64f4U), bswap_32big(0x5a5623c6U), bswap_32big(0x62ac7954U), + bswap_32big(0xdd3cbd7fU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xcb5da913U), bswap_32big(0xd9e7aa19U), bswap_32big(0x33798421U), + bswap_32big(0x45de0871U)); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000228U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x0140000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1404H, 0x16380000U); + + for (iLoop = 0U; iLoop < 128U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xa2d27122U), + bswap_32big(0xd4723a57U), + bswap_32big(0x40200df9U), + bswap_32big(0x80db7edeU)); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0xf2a03be0U), + bswap_32big(0xc7af3169U), + bswap_32big(0xf561cfc8U), + bswap_32big(0x1d07ae52U)); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x3d736dd2U), bswap_32big(0xf6727c7eU), bswap_32big(0xa24ad1a4U), + bswap_32big(0xfe5f6378U)); + WR1_PROG(REG_1408H, 0x00020000U); + + r_rsip_func102(bswap_32big(0x722fef77U), bswap_32big(0x0557ff47U), bswap_32big(0xfbe9c2a1U), + bswap_32big(0x0b2e641eU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7c.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7c.c new file mode 100644 index 0000000000..d34f0e7c49 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7c.c @@ -0,0 +1,331 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p7c (const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007c0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x362e9ad8U), + bswap_32big(0x04a83840U), + bswap_32big(0x4f7f1e2fU), + bswap_32big(0xd6b96791U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000011U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfce9d75eU), + bswap_32big(0x21347283U), + bswap_32big(0x46ea3918U), + bswap_32big(0x07a3bfa2U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x0000ffc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x14300000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + + WR1_PROG(REG_1404H, 0x12280000U); + for (iLoop = 128U; iLoop < 256U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xe5f4a65dU), + bswap_32big(0x31889f37U), + bswap_32big(0x3b190fecU), + bswap_32big(0x3be25c17U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xc1b673d3U), bswap_32big(0xb8978998U), bswap_32big(0xd635a110U), + bswap_32big(0x854b8e4cU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x40400010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00007fc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x10200000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x89399558U), bswap_32big(0x15cc5ee4U), bswap_32big(0xad83de04U), + bswap_32big(0x5c82fb11U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x1057cb7bU), bswap_32big(0x12345758U), bswap_32big(0x66c4e385U), + bswap_32big(0xc45ec2bfU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x0a4dc214U), bswap_32big(0x6c3f140fU), bswap_32big(0xa3ecde91U), + bswap_32big(0x87ac39d9U)); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x40400000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1404H, 0x16380000U); + + for (iLoop = 0U; iLoop < 128U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xcc4cef5bU), + bswap_32big(0x5261e04aU), + bswap_32big(0x2ca4a0e5U), + bswap_32big(0x7ab37fa7U)); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x481d6c36U), + bswap_32big(0xd7d44a2cU), + bswap_32big(0xdb5658c6U), + bswap_32big(0xc565db94U)); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x7dec56faU), bswap_32big(0xf4139241U), bswap_32big(0x79efc7b8U), + bswap_32big(0x41cb3d1bU)); + WR1_PROG(REG_1408H, 0x00020000U); + + r_rsip_func102(bswap_32big(0xfcf441cfU), bswap_32big(0xe0243144U), bswap_32big(0x3a8e946aU), + bswap_32big(0x7e6fc8a2U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7d.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7d.c new file mode 100644 index 0000000000..10c5520700 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7d.c @@ -0,0 +1,581 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p7d (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x007d0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0x226b7ec9U), + bswap_32big(0xc49622b5U), + bswap_32big(0x165d3ba3U), + bswap_32big(0x9e56d2d9U)); + r_rsip_func078(InData_DomainParam); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000003f0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000003f0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007d01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe3d2d535U), + bswap_32big(0x11118722U), + bswap_32big(0xb24c0c16U), + bswap_32big(0xd9546668U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007d02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8468b6fbU), + bswap_32big(0x018c392fU), + bswap_32big(0xe75778c1U), + bswap_32big(0x21690b73U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007d03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc200a7abU), + bswap_32big(0x931934fcU), + bswap_32big(0x0853b8bcU), + bswap_32big(0xbe6224baU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007d04U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x96f9dedbU), + bswap_32big(0xb2c47447U), + bswap_32big(0x63c3bfdeU), + bswap_32big(0xaca23388U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000003f0U); + WR1_PROG(REG_1020H, 0x00000160U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13f80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000438U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x3645d6a4U), + bswap_32big(0xb7ad9bc2U), + bswap_32big(0xd5f982d7U), + bswap_32big(0x3162cdacU)); + r_rsip_func079(InData_DomainParam); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbd7f9e39U), + bswap_32big(0x8f084548U), + bswap_32big(0x53e5d5f2U), + bswap_32big(0x6e94da99U)); + r_rsip_func090(); + + r_rsip_func100(bswap_32big(0x59efd58bU), + bswap_32big(0x973f6461U), + bswap_32big(0x90a0639eU), + bswap_32big(0x4953eff5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x6bb54e2aU), bswap_32big(0x8c52fe07U), bswap_32big(0x8591f226U), + bswap_32big(0x331baa83U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x20899469U), bswap_32big(0xa18871b2U), bswap_32big(0x8fa9bac4U), + bswap_32big(0x8bbf9040U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8793dc46U), bswap_32big(0x7b64c9f9U), bswap_32big(0x2171944dU), + bswap_32big(0xcca22c83U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xf20b1d30U), bswap_32big(0xaf1b7d1aU), bswap_32big(0xdc5fa6deU), + bswap_32big(0xca2c4a42U)); + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MsgDgst[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9a4665bdU), bswap_32big(0xd6f4f875U), bswap_32big(0x9bed833fU), + bswap_32big(0xeb2c17d4U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000021U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5eda6f34U), bswap_32big(0xdc9d6819U), bswap_32big(0x57e49badU), + bswap_32big(0x87faa64dU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x11c00000U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x28fca00eU), bswap_32big(0x1f226297U), bswap_32big(0xd639908aU), + bswap_32big(0x8d0a3ee6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xab6da78eU), + bswap_32big(0x51d793eaU), + bswap_32big(0xcc2d9c0eU), + bswap_32big(0x6dd6493bU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x08080005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x88d5e3a6U), + bswap_32big(0x2efe7c9bU), + bswap_32big(0xc65cccacU), + bswap_32big(0x9ac2435bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8f9f5fb2U), + bswap_32big(0xe1f3dadeU), + bswap_32big(0x7b2b6e9eU), + bswap_32big(0x07aed491U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x6a794c71U), + bswap_32big(0x38f53e3eU), + bswap_32big(0x2481daf2U), + bswap_32big(0xdb759557U)); + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[8]); + + r_rsip_func100(bswap_32big(0x787e5833U), + bswap_32big(0x63e79074U), + bswap_32big(0x894b8dacU), + bswap_32big(0x1461fe21U)); + WR1_PROG(REG_1A24H, 0x08000105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[12]); + + r_rsip_func100(bswap_32big(0x51bc7897U), + bswap_32big(0x8db48b4dU), + bswap_32big(0x7069a5a5U), + bswap_32big(0xb9892961U)); + WR1_PROG(REG_1404H, 0x11c00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[16]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[20]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[24]); + + r_rsip_func100(bswap_32big(0xd22d841bU), + bswap_32big(0x4e939954U), + bswap_32big(0x6c2b270eU), + bswap_32big(0xf4d33c72U)); + WR1_PROG(REG_1A24H, 0x08000105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[28]); + + r_rsip_func102(bswap_32big(0x30aec445U), + bswap_32big(0x7dd64da5U), + bswap_32big(0xfd7aa994U), + bswap_32big(0x25d892caU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7e.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7e.c new file mode 100644 index 0000000000..67074bb1c1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7e.c @@ -0,0 +1,787 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" +#include "r_rsip_sub_func.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p7e (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x007e0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x331e84e0U), + bswap_32big(0x1c477d9dU), + bswap_32big(0x82b9edf0U), + bswap_32big(0xa085474dU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc46018cdU), + bswap_32big(0x0ee89f0fU), + bswap_32big(0x23b0b717U), + bswap_32big(0x7265f191U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80a00001U); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + r_rsip_func_sub002(0x03420011U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 17]); + r_rsip_func_sub002(0x03420011U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[33]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + r_rsip_func_sub002(0x00820011U); + + r_rsip_func100(bswap_32big(0xbcdf1297U), + bswap_32big(0x4567f627U), + bswap_32big(0xb9c56121U), + bswap_32big(0x664d75a1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x9929fc88U), bswap_32big(0xc7c941c3U), bswap_32big(0x91ac1fd1U), + bswap_32big(0xc969ab27U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000fc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8090001fU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0xcd01c7f7U), bswap_32big(0x4c737b82U), bswap_32big(0x44ef9d55U), + bswap_32big(0xf41b0bb2U)); + r_rsip_func078(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x18f00000U); + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x00000700U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + r_rsip_func_sub002(0x00c20031U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + r_rsip_func_sub002(0x00c20011U); + + WR1_PROG(REG_1404H, 0x19400000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[24]); + r_rsip_func_sub002(0x00c20031U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[28]); + r_rsip_func_sub002(0x00c20011U); + + WR1_PROG(REG_1404H, 0x11c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0003dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000000c0U, 0x00000200U, 0x00000160U, 0x0808000aU); + + r_rsip_func_sub001(0x00000160U, 0x00000930U, 0x000001b0U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000930U, 0x00000200U, 0x000001b0U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000160U, 0x00000980U, 0x000001b0U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000980U, 0x00000200U, 0x000001b0U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x306c7cd5U), bswap_32big(0x4aaa36cdU), bswap_32big(0x3289d560U), + bswap_32big(0xb95da083U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x0c1053fcU), bswap_32big(0xf8f0d08aU), bswap_32big(0x12645fc6U), + bswap_32big(0xf82ba89aU)); + } + else + { + r_rsip_func100(bswap_32big(0xc9efe878U), bswap_32big(0x3dd98d4eU), bswap_32big(0x61cc304aU), + bswap_32big(0x61717222U)); + + r_rsip_func_sub001(0x00000160U, 0x00000200U, 0x000001b0U, 0x0808000aU); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + r_rsip_func_sub003(0x000000c0U, 0x00000160U, 0x08080002U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8190001fU); + r_rsip_func_sub002(0x00c90041U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x000000c0U, 0x00000480U, 0x08080002U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x000000c0U, 0x00000340U, 0x08080002U); + + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11200000U); + r_rsip_func_sub002(0x00c00041U); + + WR1_PROG(REG_1404H, 0x19800000U); + r_rsip_func_sub002(0x00c002d1U); + + WR1_PROG(REG_1014H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a70U, 0x08080004U); + + r_rsip_func_sub001(0x00000890U, 0x00000160U, 0x000002a8U, 0x08080009U); + + r_rsip_func_sub001(0x00000070U, 0x00000160U, 0x000002f0U, 0x08080009U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1608H, 0x81900001U); + r_rsip_func_sub002(0x00c90041U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x000009e0U, 0x08080002U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1608H, 0x8190001fU); + r_rsip_func_sub002(0x00c90041U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a28U, 0x08080002U); + + r_rsip_func100(bswap_32big(0x1d8d6d5bU), bswap_32big(0xeca4b656U), bswap_32big(0x8a4c8630U), + bswap_32big(0x13afe170U)); + r_rsip_func079(InData_DomainParam); + + r_rsip_func_sub001(0x000001c0U, 0x00000160U, 0x00000ad0U, 0x08080009U); + + r_rsip_func_sub001(0x00000208U, 0x00000160U, 0x00000b18U, 0x08080009U); + + r_rsip_func_sub001(0x00000a70U, 0x00000160U, 0x00000b60U, 0x08080009U); + + r_rsip_func_sub001(0x00000ad0U, 0x000009e0U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x000009e0U, 0x00000ad0U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000b18U, 0x00000a28U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000a28U, 0x00000b18U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xbad88468U), bswap_32big(0x73fa70f6U), bswap_32big(0xd82f664aU), + bswap_32big(0x031fffcdU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000a70U); + r_rsip_func_sub003(0x00000070U, 0x00000c50U, 0x08080013U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x954d3910U), + bswap_32big(0xda1b4896U), + bswap_32big(0xee693040U), + bswap_32big(0xe2fe7ae8U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000b60U); + r_rsip_func_sub003(0x000002f0U, 0x00000c50U, 0x08080014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xfeae9548U), + bswap_32big(0xf2a06da1U), + bswap_32big(0x4fc0b425U), + bswap_32big(0x26a58024U)); + } + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1404H, 0x14400000U); + WR1_PROG(REG_1608H, 0x80900001U); + r_rsip_func_sub002(0x03430041U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1404H, 0x13000000U); + WR1_PROG(REG_1608H, 0x80900001U); + r_rsip_func_sub002(0x03430041U); + + WR1_PROG(REG_1404H, 0x11600000U); + r_rsip_func_sub002(0x00c000f1U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000034a1U); + + WR1_PROG(REG_1600H, 0x00026ca5U); + + WR1_PROG(REG_1600H, 0x00003865U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x00003885U); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x01816ca3U); + WR1_PROG(REG_1600H, 0x01816ca4U); + WR1_PROG(REG_1600H, 0x00016c63U); + WR1_PROG(REG_1600H, 0x00016c84U); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0003dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000001c0U, 0x00000160U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000250U, 0x00000160U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x249e5836U), + bswap_32big(0xabc66244U), + bswap_32big(0x606c531bU), + bswap_32big(0x6f42e26bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x000002f0U, 0x00000250U, 0x08080014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x6d92a778U), + bswap_32big(0x4ecf7844U), + bswap_32big(0xdd9eac9bU), + bswap_32big(0x0b94263dU)); + } + else + { + r_rsip_func101(bswap_32big(0xc3729894U), + bswap_32big(0xd7341b7aU), + bswap_32big(0x2f1dad42U), + bswap_32big(0x5747a9f8U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xe0e5fe6aU), + bswap_32big(0x7620493dU), + bswap_32big(0x6c406e36U), + bswap_32big(0x48da7dc0U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x678b676bU), + bswap_32big(0x2cc7db67U), + bswap_32big(0x28119041U), + bswap_32big(0x94720d30U)); + + WR1_PROG(REG_1404H, 0x11200000U); + r_rsip_func_sub002(0x00c00041U); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func_sub001(0x000009e0U, 0x00000160U, 0x000003f0U, 0x08080009U); + + r_rsip_func_sub001(0x00000a28U, 0x00000160U, 0x00000438U, 0x08080009U); + + r_rsip_func_sub001(0x00000a70U, 0x00000160U, 0x00000480U, 0x08080009U); + + r_rsip_func101(bswap_32big(0xad9b81c4U), + bswap_32big(0xd43a7e36U), + bswap_32big(0xe706826bU), + bswap_32big(0xfe24ed6bU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func_sub001(0x00000ad0U, 0x00000160U, 0x000003f0U, 0x08080009U); + + r_rsip_func_sub001(0x00000b18U, 0x00000160U, 0x00000438U, 0x08080009U); + + r_rsip_func_sub001(0x00000b60U, 0x00000160U, 0x00000480U, 0x08080009U); + + r_rsip_func101(bswap_32big(0xbf5e7a10U), + bswap_32big(0x0a76436dU), + bswap_32big(0xc9222b4dU), + bswap_32big(0x518ba3d2U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func_sub001(0x00000bc0U, 0x00000160U, 0x000003f0U, 0x08080009U); + + r_rsip_func_sub001(0x00000c08U, 0x00000160U, 0x00000438U, 0x08080009U); + + r_rsip_func_sub001(0x00000c50U, 0x00000160U, 0x00000480U, 0x08080009U); + + r_rsip_func101(bswap_32big(0x232ff655U), + bswap_32big(0x0a4322c0U), + bswap_32big(0xa1100469U), + bswap_32big(0xfba69e68U)); + } + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0003dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000001c0U, 0x00000160U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000250U, 0x00000160U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x5a4e7440U), + bswap_32big(0x1927f2daU), + bswap_32big(0x0017b154U), + bswap_32big(0xe4fc2e98U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func_sub001(0x000003f0U, 0x00000160U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000480U, 0x00000160U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0xcac34c3cU), + bswap_32big(0xce416f3cU), + bswap_32big(0xb5c842f7U), + bswap_32big(0x51b7f912U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func_sub001(0x000001c0U, 0x000003f0U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x000003f0U, 0x000001c0U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000208U, 0x00000438U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000438U, 0x00000208U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000250U, 0x00000480U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000480U, 0x00000250U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x6a098fd1U), bswap_32big(0xd427204eU), + bswap_32big(0x3478b127U), bswap_32big(0xc1b858e2U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + r_rsip_func_sub003(0x00000070U, 0x00000250U, 0x08080013U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xbf3994ddU), bswap_32big(0xc56d6cfdU), + bswap_32big(0x6f60de55U), bswap_32big(0x6f86e857U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x000002f0U, 0x00000250U, 0x08080014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xb9352a35U), bswap_32big(0xb62d53edU), + bswap_32big(0xda436f56U), bswap_32big(0xbb8e52bbU)); + } + } + else + { + r_rsip_func101(bswap_32big(0x33a8cb47U), bswap_32big(0x7b4b128cU), + bswap_32big(0xe2b6754eU), bswap_32big(0x59b74136U)); + } + } + else + { + WR1_PROG(REG_1404H, 0x11200000U); + r_rsip_func_sub002(0x00c00041U); + + r_rsip_func_sub001(0x000003f0U, 0x00000160U, 0x000001c0U, 0x08080009U); + + r_rsip_func_sub001(0x00000438U, 0x00000160U, 0x00000208U, 0x08080009U); + + r_rsip_func_sub001(0x00000480U, 0x00000160U, 0x00000250U, 0x08080009U); + + r_rsip_func101(bswap_32big(0x51c8bd08U), + bswap_32big(0xb72c9019U), + bswap_32big(0x0900f0e4U), + bswap_32big(0x8e8e6167U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x0812f1b1U), + bswap_32big(0x9bdfdbe5U), + bswap_32big(0x78583637U), + bswap_32big(0x871aad66U)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + r_rsip_func101(bswap_32big(0x20fc2467U), + bswap_32big(0x30515322U), + bswap_32big(0x7095c208U), + bswap_32big(0x3e19c9c8U)); + } + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002c20U); + + r_rsip_func101(bswap_32big(0x5d175a92U), + bswap_32big(0x831a1017U), + bswap_32big(0x4c26afb9U), + bswap_32big(0x7d9b3e5bU)); + } + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0003dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000250U, 0x000002a0U, 0x000002f0U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xe46c269aU), bswap_32big(0x87f26ee9U), bswap_32big(0x1b358840U), + bswap_32big(0x408e8353U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xbf9819a4U), + bswap_32big(0x676eda8fU), + bswap_32big(0xcaf21897U), + bswap_32big(0xd750ef71U)); + } + else + { + r_rsip_func100(bswap_32big(0x00be8870U), + bswap_32big(0x4202d626U), + bswap_32big(0xcabd94ebU), + bswap_32big(0xb340c0cfU)); + + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x00000070U, 0x000002a0U, 0x08080004U); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + r_rsip_func_sub002(0x00c0003dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000070U, 0x00000160U, 0x00000110U, 0x0808000aU); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001c0U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x00000070U, 0x000002a0U, 0x08080002U); + + r_rsip_func_sub001(0x000002a0U, 0x00000930U, 0x000001b0U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000930U, 0x000002a0U, 0x000001b0U, 0x0808000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xa3b6a580U), + bswap_32big(0x991cc0b4U), + bswap_32big(0xd5c121dcU), + bswap_32big(0xa3324b95U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xcca0c364U), + bswap_32big(0x2eddf876U), + bswap_32big(0x7d738bd8U), + bswap_32big(0xfbbc069eU)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x797935bbU); + + r_rsip_func101(bswap_32big(0x3edf04c6U), + bswap_32big(0x8f9bd110U), + bswap_32big(0x765237d2U), + bswap_32big(0xe27a29e3U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x00f9ba66U), bswap_32big(0xf8179214U), bswap_32big(0x9f758430U), + bswap_32big(0x5c5e453fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x56870795U), bswap_32big(0xbf6a8b0dU), bswap_32big(0xdff875d5U), + bswap_32big(0x0a9df613U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0xcd2ca957U), bswap_32big(0x7d0c2da1U), bswap_32big(0x996cbe10U), + bswap_32big(0x25014c80U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7f.c new file mode 100644 index 0000000000..c815951e3c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p7f.c @@ -0,0 +1,681 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p7f (const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x007f0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0xfe66784eU), + bswap_32big(0x63730ef1U), + bswap_32big(0x032320bbU), + bswap_32big(0xd8a433dfU)); + r_rsip_func078(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12a80000U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007f01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1e449e63U), + bswap_32big(0x76572aa1U), + bswap_32big(0xef022fd7U), + bswap_32big(0x28ea8f5dU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007f02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x18144922U), + bswap_32big(0xbcc3b5e3U), + bswap_32big(0x34a0b1a5U), + bswap_32big(0xdcba0ed8U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007f03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x75953895U), + bswap_32big(0x3c8fdc07U), + bswap_32big(0x6fb72b01U), + bswap_32big(0x5d45af39U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007f04U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5ccfe545U), + bswap_32big(0xb3366274U), + bswap_32big(0x15e4ece5U), + bswap_32big(0xfe09e606U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007f05U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x26c7ecfaU), + bswap_32big(0x6ee3e568U), + bswap_32big(0x67932456U), + bswap_32big(0x2e309189U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xe16eed57U), + bswap_32big(0x62b7998fU), + bswap_32big(0xbde7205aU), + bswap_32big(0xd06a7542U)); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1404H, 0x12080000U); + WR1_PROG(REG_1608H, 0x80920001U); + WR1_PROG(REG_1400H, 0x03430049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1600H, 0x20000842U); + WR1_PROG(REG_1600H, 0x10003841U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3800585eU); + WR1_PROG(REG_1600H, 0x20003460U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1600H, 0x100033c0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x14380000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003403U); + + WR1_PROG(REG_1600H, 0x00003060U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00003060U); + + r_rsip_func101(bswap_32big(0x30ee8d88U), bswap_32big(0x16979f3fU), bswap_32big(0x57d0d490U), + bswap_32big(0xb2bcbf6cU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x4b897e49U), + bswap_32big(0x7d1831e2U), + bswap_32big(0x46692325U), + bswap_32big(0x2e9c902dU)); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x52f593edU), bswap_32big(0xa2e355e5U), bswap_32big(0x7afc8d29U), + bswap_32big(0xfbfb25b6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xccce46b0U), bswap_32big(0x50c4511aU), bswap_32big(0x2f62b421U), + bswap_32big(0x07fd240bU)); + } + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0909000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1600H, 0x00003000U); + + r_rsip_func101(bswap_32big(0x17412c72U), bswap_32big(0x53c62442U), bswap_32big(0xad9b9736U), + bswap_32big(0xc7bac056U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xd6d26e4dU), + bswap_32big(0x39464ad5U), + bswap_32big(0x607ca214U), + bswap_32big(0x9733f380U)); + + r_rsip_func079(InData_DomainParam); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x07a2297aU), + bswap_32big(0x7c43aabbU), + bswap_32big(0x04ff8982U), + bswap_32big(0x4e7fce0bU)); + r_rsip_func090(); + + r_rsip_func100(bswap_32big(0xf1be6d53U), + bswap_32big(0x589febacU), + bswap_32big(0x0bbcb3feU), + bswap_32big(0x8f71aa98U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x6be6d185U), bswap_32big(0xc538f1ecU), bswap_32big(0xe40e2c30U), + bswap_32big(0x1843e07dU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007f06U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x88d0eb42U), bswap_32big(0xb8d6de00U), bswap_32big(0x9f28fbffU), + bswap_32big(0xdc5e5d9cU)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x303476ecU), bswap_32big(0x0155afe6U), bswap_32big(0xc4d91facU), + bswap_32big(0xdf52308eU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000021U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000007fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x70e1c7feU), bswap_32big(0x0138322dU), bswap_32big(0xf398475cU), + bswap_32big(0xc3fb3069U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x91c80ab5U), bswap_32big(0x5263068aU), bswap_32big(0xbaddce64U), + bswap_32big(0x8900e6e5U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x13000000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x4109408aU), bswap_32big(0x587f99d3U), bswap_32big(0xf762c3e1U), + bswap_32big(0xf7e5d027U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 1]); + + r_rsip_func100(bswap_32big(0x43ba6491U), bswap_32big(0x60811b77U), bswap_32big(0xadb9473bU), + bswap_32big(0xb1f770efU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 5]); + + r_rsip_func100(bswap_32big(0x4e0fcbeeU), bswap_32big(0x42cba817U), bswap_32big(0xbd5b5bf4U), + bswap_32big(0xb8332224U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00007f07U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb69a104cU), bswap_32big(0x95c21417U), bswap_32big(0x33b94211U), + bswap_32big(0x5e95bba6U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000009U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd20f65c9U), bswap_32big(0x68553b5fU), bswap_32big(0x694b33b9U), + bswap_32big(0x1d1c6b58U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000009U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9934de7eU), bswap_32big(0x02c70f36U), bswap_32big(0xc2b390c6U), + bswap_32big(0x8a13a94bU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xdf078b1dU), bswap_32big(0x716b8744U), bswap_32big(0x78b30b6dU), + bswap_32big(0x6b613ab9U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xd0473553U), bswap_32big(0x7c9a3d42U), bswap_32big(0x2e717892U), + bswap_32big(0xa6b4ba99U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x12b00000U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 12; iLoop < 24U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xa60ac965U), bswap_32big(0x7a6d796eU), bswap_32big(0x104b36d2U), + bswap_32big(0x55097464U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + for (iLoop = 24; iLoop < 32U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x3b815981U), bswap_32big(0x5e445616U), bswap_32big(0x8b00d3a0U), + bswap_32big(0x8bdd02efU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + + r_rsip_func100(bswap_32big(0xc53fe2abU), bswap_32big(0x13d03f6fU), bswap_32big(0xc7427f28U), + bswap_32big(0xf08bc4a5U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + r_rsip_func102(bswap_32big(0x900dbd47U), bswap_32big(0x130a8bd6U), bswap_32big(0x19e789d9U), + bswap_32big(0xb99d95e8U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p81.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p81.c new file mode 100644 index 0000000000..2e4d933a65 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p81.c @@ -0,0 +1,92 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p81 (void) +{ + WR1_PROG(REG_1D04H, 0x000dec05U); + WR1_PROG(REG_1D08H, 0x000f3c90U); + + WR1_PROG(REG_1D00H, 0x00000001U); + + WAIT_STS(REG_1D00H, 1, 0); + + if (RD1_MASK(REG_1D00H, 0x00030000U) != 0x00000000U) + { + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_140CH, 0x38c60eedU); + WR1_PROG(REG_1448H, 0x00000000U); + + WR1_PROG(REG_1408H, 0x00000001U); + WR1_PROG(REG_1414H, 0x00001401U); + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1800H, 0x00000001U); + WR1_PROG(REG_1700H, 0x00000001U); + + WR1_PROG(REG_1B00H, 0x00818001U); + WR1_PROG(REG_1B08H, 0x00000d00U); + + WR1_PROG(REG_1804H, 0x00008003U); + + WR1_PROG(REG_1444H, 0x000003a2U); + r_rsip_func101(0x7b32b49dU, 0x44008805U, 0xcbcc8015U, 0x30853d95U); + WR1_PROG(REG_1804H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x0a0700f5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, 0x31c26c53U, 0x8cb55749U, 0x1b2b5a7eU, 0x29d04c85U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + r_rsip_func101(0x6e510296U, 0x70dce478U, 0x104cad17U, 0xbe691952U); + + r_rsip_func100(0x2f59c033U, 0x2f1fbbc4U, 0xc208c759U, 0xc9b1a43aU); + + WR1_PROG(REG_1408H, 0x00020000U); + + if (CHCK_STS(REG_142CH, 13, 0)) + { + WR1_PROG(REG_14BCH, 0x00000020U); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1430H, 0x0000FFFFU); + + WR1_PROG(REG_1B08H, 0x00000220U); + + r_rsip_func102(0x157dae9eU, 0x6db19678U, 0x334d88c1U, 0xe66cddc8U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p82.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p82.c new file mode 100644 index 0000000000..4fd07fd6f1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p82.c @@ -0,0 +1,378 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p82 (void) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00820001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b070194U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x01c7ba56U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b070184U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x01fd9cb7U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000074U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x3000a820U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000080U); + + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_143CH, 0x00001200U); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x00000028U); + + for (jLoop = 0U; jLoop < 3U; jLoop++) + { + r_rsip_func100(bswap_32big(0xa77e3c75U), bswap_32big(0xe488ce93U), bswap_32big(0x8404d3f7U), + bswap_32big(0xa49c7658U)); + WR1_PROG(REG_1600H, 0x00000884U); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000013U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000355U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x000000aaU); + + WR1_PROG(REG_1600H, 0x00007c01U); + WR1_PROG(REG_143CH, 0x00600000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00200007U); + + r_rsip_func101(bswap_32big(0x2ea36172U), bswap_32big(0xb612e170U), bswap_32big(0x1384ad46U), + bswap_32big(0x7be9d812U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00200005U); + + r_rsip_func101(bswap_32big(0x39d1acebU), bswap_32big(0xd3094a50U), bswap_32big(0x21dc54ccU), + bswap_32big(0xced222ceU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00200006U); + + r_rsip_func101(bswap_32big(0xcec77843U), bswap_32big(0xae9def84U), bswap_32big(0x35eab8f1U), + bswap_32big(0x1e65445dU)); + } + + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0x0e3c8407U); + WR1_PROG(REG_1400H, 0x00840081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1708H, 2, 1); + WR1_PROG(REG_143CH, 0x00001200U); + + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000a00U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1608H, 0x808a0000U); + WR1_PROG(REG_1400H, 0x03440029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000038a0U); + WR1_PROG(REG_1600H, 0x00003405U); + WR1_PROG(REG_1600H, 0x00002804U); + + WR1_PROG(REG_1600H, 0x342028e0U); + WR1_PROG(REG_1600H, 0x10005066U); + + WR1_PROG(REG_1600H, 0x34202808U); + WR1_PROG(REG_1600H, 0x10005066U); + + WR1_PROG(REG_1600H, 0x00003485U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x0000005AU); + + WR1_PROG(REG_1600H, 0x00000842U); + + WR1_PROG(REG_1600H, 0x000008c6U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000002U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x01003804U); + + WR1_PROG(REG_1600H, 0x342028e0U); + WR1_PROG(REG_1600H, 0x10005066U); + + WR1_PROG(REG_1600H, 0x00002440U); + + WR1_PROG(REG_1600H, 0x00002cc0U); + + WR1_PROG(REG_1600H, 0x00002485U); + } + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000037U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000024U); + + WR1_PROG(REG_1600H, 0x01003804U); + + WR1_PROG(REG_1600H, 0x342028e0U); + WR1_PROG(REG_1600H, 0x10005066U); + + WR1_PROG(REG_1600H, 0x00002cc0U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000026U); + + WR1_PROG(REG_1600H, 0x01003804U); + + WR1_PROG(REG_1600H, 0x342028e0U); + WR1_PROG(REG_1600H, 0x10005066U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c300104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x8084000aU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a540U); + WR1_PROG(REG_1600H, 0x00000010U); + + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_143CH, 0x00001200U); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00000080U); + + r_rsip_func101(bswap_32big(0xbab72790U), bswap_32big(0xfb0c6732U), bswap_32big(0x811e0c23U), + bswap_32big(0xd0bff33eU)); + } + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000058U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + + WR1_PROG(REG_1600H, 0x00002c20U); + + WR1_PROG(REG_1600H, 0x38008860U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xd5280305U), + bswap_32big(0x5ec838a5U), + bswap_32big(0x90bea9beU), + bswap_32big(0x256d53e4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xf507c391U), bswap_32big(0x78d1eee7U), bswap_32big(0xfd5e3a3eU), + bswap_32big(0x1da36422U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_RETRY; + } + else + { + r_rsip_func100(bswap_32big(0xfe11703cU), bswap_32big(0xa74f70e6U), bswap_32big(0xd54d9ce6U), + bswap_32big(0xbc64834cU)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x080000a4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0x78d85999U), bswap_32big(0x9b1eb53aU), bswap_32big(0xa6c5fb76U), + bswap_32big(0xba500f61U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x080000b4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0x6a6d91c8U), bswap_32big(0xd200e279U), bswap_32big(0x37bf43beU), + bswap_32big(0x7e2b3a4bU)); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x08000075U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, bswap_32big(0x00000000U), bswap_32big(0x00000000U), bswap_32big(0x00000000U), + bswap_32big(0x00000001U)); + + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0x07328d07U); + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x00000028U); + WR1_PROG(REG_1608H, 0x818c000aU); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x02cabe3fU), bswap_32big(0xb73fe20fU), bswap_32big(0xfefa233cU), + bswap_32big(0x2cd272b2U)); + WR1_PROG(REG_1A24H, 0x08000075U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x080000a5U); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00008201U)); + + r_rsip_func101(bswap_32big(0xdb1ca3daU), bswap_32big(0x0d8bc17dU), bswap_32big(0x6dd1eae6U), + bswap_32big(0x05e952ecU)); + r_rsip_func103(); + r_rsip_func100(bswap_32big(0xaf8c71bbU), bswap_32big(0x15be5a17U), bswap_32big(0x48e8cf97U), + bswap_32big(0xc3e545cdU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c2000d4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00008202U)); + + r_rsip_func101(bswap_32big(0xe6492cc9U), bswap_32big(0xc153eb3aU), bswap_32big(0x09045a7aU), + bswap_32big(0xd7677e44U)); + r_rsip_func103(); + r_rsip_func100(bswap_32big(0x001d4e5aU), bswap_32big(0x4cd977afU), bswap_32big(0xb6bff34dU), + bswap_32big(0x3df768d8U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &S_RAM[16]); + S_RAM[16] = bswap_32big(S_RAM[16]); + S_RAM[17] = bswap_32big(S_RAM[17]); + S_RAM[18] = bswap_32big(S_RAM[18]); + S_RAM[19] = bswap_32big(S_RAM[19]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00008203U)); + + r_rsip_func101(bswap_32big(0xe1921c22U), bswap_32big(0x8f2f5ccfU), bswap_32big(0xc40c04f3U), + bswap_32big(0x160998c8U)); + r_rsip_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1404H, 0x20000000U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x00c01001U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1B00H, 0x00008002U); + WR1_PROG(REG_1B08H, 0x00000d01U); + + WR1_PROG(REG_1B00H, 0x00008001U); + + WR1_PROG(REG_1B08H, 0x00000214U); + + r_rsip_func102(bswap_32big(0x2aee58bcU), bswap_32big(0xa1214cddU), bswap_32big(0x30944b8bU), + bswap_32big(0x64f0fc69U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83a.c new file mode 100644 index 0000000000..a1140293a3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83a.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p83a (const uint32_t InData_DataA[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0xa57b0396U), + bswap_32big(0x41b7d5bcU), + bswap_32big(0x40a30832U), + bswap_32big(0x0fc29d05U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83f.c new file mode 100644 index 0000000000..30f7b955fa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83f.c @@ -0,0 +1,165 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p83f (const uint32_t InData_Text[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x83cccf84U), + bswap_32big(0x2cb52154U), + bswap_32big(0xfb871811U), + bswap_32big(0x8d713e02U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x11007451U), bswap_32big(0x8f74262cU), bswap_32big(0xb9870bc3U), + bswap_32big(0x14e6900bU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1600H, 0x00036800U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x34f4c116U), bswap_32big(0x56bafdc7U), bswap_32big(0x1338e325U), + bswap_32big(0x31fd0246U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xc9fea7b8U), bswap_32big(0x2d22d20fU), bswap_32big(0xc0292c40U), + bswap_32big(0x3ddc5227U)); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x81840001U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0x71ab7c92U), bswap_32big(0xc68db878U), bswap_32big(0xb60ddf6cU), + bswap_32big(0x0f18ccf0U)); + } + + r_rsip_func100(bswap_32big(0x368be93eU), bswap_32big(0x691d5361U), bswap_32big(0x39485ac7U), + bswap_32big(0x712c2a54U)); + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + r_rsip_func102(bswap_32big(0x229bf9c1U), bswap_32big(0x2f0ce0e9U), bswap_32big(0xcefd76f6U), + bswap_32big(0x258cffe8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83i.c new file mode 100644 index 0000000000..ae5bf76dc9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83i.c @@ -0,0 +1,144 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p83i (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00830001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000083U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x17250ef1U), + bswap_32big(0xfc7a10e9U), + bswap_32big(0x6fcab1baU), + bswap_32big(0xbf6cb56bU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000083U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6324fd46U), + bswap_32big(0xe08fdf8eU), + bswap_32big(0x54425e42U), + bswap_32big(0xeb7112caU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xcc6939e1U), + bswap_32big(0xd2eaa3a4U), + bswap_32big(0x8267fdbdU), + bswap_32big(0xc9b40791U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xb00d66d0U), + bswap_32big(0x3da1b337U), + bswap_32big(0x8856edafU), + bswap_32big(0x946e2812U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xb953ebc0U), + bswap_32big(0x2b41cea0U), + bswap_32big(0x7eb929b5U), + bswap_32big(0xff3e8522U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x99f57749U), bswap_32big(0x86c0f335U), bswap_32big(0xd95a44d8U), + bswap_32big(0x3ea4daa0U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40070010U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83t.c new file mode 100644 index 0000000000..76cf94b5ed --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83t.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p83t (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83u.c new file mode 100644 index 0000000000..b31badb17f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p83u.c @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p83u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x980dd63bU), + bswap_32big(0xe9852166U), + bswap_32big(0xeb5354caU), + bswap_32big(0x50f39f3dU)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40020030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + + r_rsip_func100(bswap_32big(0xe5d11834U), + bswap_32big(0x2e120a1dU), + bswap_32big(0xaf566faeU), + bswap_32big(0x9cf9361aU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40028030U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + if (MAX_CNT >= 8) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[4]); + for (iLoop = 8; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + r_rsip_func202(); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00028000U); + WR1_PROG(REG_1824H, 0x08008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0xce840c6eU), + bswap_32big(0x45fed9a6U), + bswap_32big(0x0c7c1a5dU), + bswap_32big(0x9d165ed6U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85a.c new file mode 100644 index 0000000000..c6388ed11f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85a.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p85a (const uint32_t InData_DataA[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0x70e58445U), + bswap_32big(0xeba06533U), + bswap_32big(0x5e5b2aefU), + bswap_32big(0x24f38be9U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85f.c new file mode 100644 index 0000000000..3f1cd45c6e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85f.c @@ -0,0 +1,215 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p85f (const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd331410bU), + bswap_32big(0x39356383U), + bswap_32big(0xb01491c0U), + bswap_32big(0x302e251bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x5a88dd71U), bswap_32big(0x79c6abc0U), bswap_32big(0x4e8b14ebU), + bswap_32big(0xf209dbd0U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1600H, 0x00036800U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x31be1474U), bswap_32big(0x80872d31U), bswap_32big(0xbc341acaU), + bswap_32big(0xbacf5ecdU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0xa46c092fU), bswap_32big(0x2fc24ac3U), bswap_32big(0x1502df4fU), + bswap_32big(0xea58f74bU)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40018030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0x5e254350U), bswap_32big(0x90fbb951U), bswap_32big(0x48bc276aU), + bswap_32big(0x1da25806U)); + } + + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xd3a0fba9U), bswap_32big(0xca26fc8bU), bswap_32big(0x52930063U), + bswap_32big(0xdd4b5772U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xf7ff436bU), bswap_32big(0x5a977b00U), bswap_32big(0xfbe20adfU), + bswap_32big(0x45b1ddf4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x3b4142d3U), bswap_32big(0x65a0e952U), bswap_32big(0x365f471cU), + bswap_32big(0xc7a28269U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85i.c new file mode 100644 index 0000000000..8c83726b49 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85i.c @@ -0,0 +1,146 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p85i (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00850001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000085U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x243a156aU), + bswap_32big(0x894ca1e8U), + bswap_32big(0xe596a6d3U), + bswap_32big(0xf0afd434U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000085U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8e272b42U), + bswap_32big(0x02ce40d2U), + bswap_32big(0x4d61a756U), + bswap_32big(0x68487d82U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1608H, 0x80080000U); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x57d79764U), + bswap_32big(0xb07a2f75U), + bswap_32big(0x36d874f2U), + bswap_32big(0xf9d93391U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd192a26eU), bswap_32big(0x29055116U), bswap_32big(0x242b41f4U), + bswap_32big(0x58a01c4dU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x454f8e0eU), bswap_32big(0x706533e3U), bswap_32big(0x671b3e15U), + bswap_32big(0x709d59caU)); + WR1_PROG(REG_1608H, 0x81080000U); + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xb11f90e1U), bswap_32big(0x5edf4330U), bswap_32big(0xbc32b417U), + bswap_32big(0x6de6da83U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40070010U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85t.c new file mode 100644 index 0000000000..3b51e6d4a3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85t.c @@ -0,0 +1,31 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p85t (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85u.c new file mode 100644 index 0000000000..452ab97109 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p85u.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p85u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x7edc1d0fU), + bswap_32big(0xeaa7807aU), + bswap_32big(0x218a3cabU), + bswap_32big(0x960e0fbaU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40018030U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + r_rsip_func202(); + + r_rsip_func101(bswap_32big(0xd814f5beU), + bswap_32big(0x01165e16U), + bswap_32big(0x0c0dab4fU), + bswap_32big(0xd118ce4aU)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87f.c new file mode 100644 index 0000000000..75342fd78c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87f.c @@ -0,0 +1,226 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p87f (const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x87eb6ebaU), + bswap_32big(0x3509b223U), + bswap_32big(0xc0a4899fU), + bswap_32big(0x59153b58U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8f708f63U), bswap_32big(0x47c93bb7U), bswap_32big(0x7515dcbbU), + bswap_32big(0xaf6e04ecU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x4a008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x3817102aU), bswap_32big(0xddc1c982U), bswap_32big(0xa6063cdcU), + bswap_32big(0x3de637faU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x5a008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func101(bswap_32big(0x72dfc1e7U), bswap_32big(0x06620d71U), bswap_32big(0xe1b44debU), + bswap_32big(0x01a9f1c1U)); + } + + WR1_PROG(REG_1824H, 0x0c000045U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + r_rsip_func100(bswap_32big(0x49c21239U), bswap_32big(0x56a4ce69U), bswap_32big(0x1cf0f8b5U), + bswap_32big(0xcca99c3bU)); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e008505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + r_rsip_func102(bswap_32big(0x0cf911a1U), bswap_32big(0x72d726a6U), bswap_32big(0x72dd7dd0U), + bswap_32big(0x6848c90dU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010040U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a840U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x34202862U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x4c70d0d0U), bswap_32big(0x717f8565U), bswap_32big(0x709e9899U), + bswap_32big(0xe00dd203U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x46cf0a01U), + bswap_32big(0xa1cc7b23U), + bswap_32big(0x14f1edd1U), + bswap_32big(0x76787cd4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e008505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e2U); + WR1_PROG(REG_1600H, 0x000568e7U); + WR1_PROG(REG_1600H, 0x00026ce7U); + + WR1_PROG(REG_1600H, 0x00003827U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1600H, 0x00003402U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x000028c0U); + WR1_PROG(REG_1600H, 0x00008cc0U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x00004406U); + + WR1_PROG(REG_1600H, 0x00007421U); + WR1_PROG(REG_1600H, 0x00007821U); + + WR1_PROG(REG_1600H, 0x00003c27U); + + WR1_PROG(REG_1600H, 0x000034c2U); + WR1_PROG(REG_1600H, 0x0000a4c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1600H, 0x000568c6U); + + WR1_PROG(REG_1600H, 0x000034e6U); + WR1_PROG(REG_1600H, 0x00026ce7U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 4U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3420a8e0U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1600H, 0x10003c27U); + + WR1_PROG(REG_1600H, 0x1000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + r_rsip_func100(bswap_32big(0x03990d4fU), + bswap_32big(0x4fe64d63U), + bswap_32big(0x6f990fe0U), + bswap_32big(0x0aaf01a5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd291cd60U), + bswap_32big(0xb5cb891cU), + bswap_32big(0xd7819e89U), + bswap_32big(0x94a13e4aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x5ba60e6eU), + bswap_32big(0xcb91a9c0U), + bswap_32big(0x5ae38b39U), + bswap_32big(0x2dd9e11cU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87i.c new file mode 100644 index 0000000000..5ecfb8d804 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87i.c @@ -0,0 +1,126 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p87i (const uint32_t InData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00870001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000087U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x28fb9a1aU), + bswap_32big(0x0600a389U), + bswap_32big(0xa81b7bf6U), + bswap_32big(0x9e345121U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000087U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x11c6f508U), + bswap_32big(0xcdaff931U), + bswap_32big(0x96e49066U), + bswap_32big(0xccdabd97U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x0eb72256U), + bswap_32big(0xf0a3d3feU), + bswap_32big(0xd319bf69U), + bswap_32big(0x508e8893U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xc94487c0U), + bswap_32big(0x1dff9ba1U), + bswap_32big(0x0c96cb67U), + bswap_32big(0x9084e48eU)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x9451e5bdU), + bswap_32big(0xfa1ef548U), + bswap_32big(0x78f671abU), + bswap_32big(0xb2497414U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x65b77918U), bswap_32big(0xe8d2b2cdU), bswap_32big(0x52f69716U), + bswap_32big(0xc09f9faaU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87u.c new file mode 100644 index 0000000000..3353aa9660 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p87u.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p87u (const uint32_t InData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e008406U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0xefed5cedU), + bswap_32big(0xef4cf1aaU), + bswap_32big(0x77d571f4U), + bswap_32big(0xaa99cea3U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89f.c new file mode 100644 index 0000000000..cd941f7a8e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89f.c @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p89f (void) +{ + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func101(bswap_32big(0xf351fd8fU), bswap_32big(0x5df42a44U), bswap_32big(0x2093f6bdU), + bswap_32big(0xd54e3977U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func101(bswap_32big(0x23d0f905U), bswap_32big(0xec060a28U), bswap_32big(0xba8e4acfU), + bswap_32big(0xe5aad16cU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func101(bswap_32big(0xc0dddca4U), bswap_32big(0xd8384309U), bswap_32big(0x0718c944U), + bswap_32big(0x53e5c656U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func101(bswap_32big(0x7410d6eeU), bswap_32big(0xb7e6a471U), bswap_32big(0x6a718631U), + bswap_32big(0xb48c248dU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + r_rsip_func101(bswap_32big(0x8290ca26U), bswap_32big(0x1dbdd9aaU), bswap_32big(0x9388548dU), + bswap_32big(0x3532f2a8U)); + } + else + { + ; + } + + r_rsip_func102(bswap_32big(0xd97f89a3U), + bswap_32big(0xaa23577eU), + bswap_32big(0xd6bf1091U), + bswap_32big(0xbee3efcaU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89i.c new file mode 100644 index 0000000000..c3fe4f33c9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89i.c @@ -0,0 +1,185 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p89i (const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00890001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000089U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf8b3ad50U), + bswap_32big(0xaae92652U), + bswap_32big(0x92a4d7bfU), + bswap_32big(0x4738924cU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000089U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7797b6acU), + bswap_32big(0xeb7d5ae5U), + bswap_32big(0x877c27f5U), + bswap_32big(0x6a4ddb2eU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x33d0ca40U), + bswap_32big(0xf22a1ef8U), + bswap_32big(0xe2bd9e9bU), + bswap_32big(0xb2b7f41dU)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x65791523U), + bswap_32big(0x68594a89U), + bswap_32big(0x25b88bbeU), + bswap_32big(0xdc9e028cU)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x407cc6fdU), + bswap_32big(0xf424a300U), + bswap_32big(0x2604c437U), + bswap_32big(0xc6e20074U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x851d8212U), bswap_32big(0xb502ddb3U), bswap_32big(0x8e1696f6U), + bswap_32big(0x9a2bccddU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1444H, 0x000000c7U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00000080U); + + r_rsip_func100(bswap_32big(0xad284ee0U), bswap_32big(0x72780197U), bswap_32big(0x90692935U), + bswap_32big(0xdc6473ceU)); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func101(bswap_32big(0x82815d8eU), bswap_32big(0x61338f74U), bswap_32big(0x5d1b531aU), + bswap_32big(0x94408b0fU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func101(bswap_32big(0xb1c69c16U), bswap_32big(0x9517a426U), bswap_32big(0x2211c437U), + bswap_32big(0x187a2584U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0xb1127db0U), bswap_32big(0xb0c739f0U), bswap_32big(0x6939a0d4U), + bswap_32big(0x8ee7d7edU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0x972cfb65U), bswap_32big(0x40f1dff4U), bswap_32big(0x1ce6c7dfU), + bswap_32big(0xee17ecddU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + r_rsip_func101(bswap_32big(0x5e044856U), bswap_32big(0x7c62990fU), bswap_32big(0x2425c353U), + bswap_32big(0x0121188dU)); + } + else + { + ; + } + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89u.c new file mode 100644 index 0000000000..bc97e19902 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p89u.c @@ -0,0 +1,141 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p89u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0xf303b8e1U), bswap_32big(0x1af85895U), bswap_32big(0xd5b03a02U), + bswap_32big(0x6e44dc9dU)); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0a008106U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x5edc1b03U), bswap_32big(0xd9391454U), bswap_32big(0xe3126acdU), + bswap_32big(0x3ea084ddU)); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0a00810eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0xe455a433U), bswap_32big(0xe1a0e21aU), bswap_32big(0x4c3ca482U), + bswap_32big(0x8168c8a7U)); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e008506U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0xe41e0443U), bswap_32big(0x1f8369b5U), bswap_32big(0x188c6164U), + bswap_32big(0xf34dee1eU)); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0900890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + r_rsip_func100(bswap_32big(0x7ad2412cU), bswap_32big(0x32e3ba10U), bswap_32big(0x81728959U), + bswap_32big(0x3e431a0dU)); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else + { + ; + } + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0xe314fed8U), bswap_32big(0x2f1b277fU), bswap_32big(0x5ee0601eU), + bswap_32big(0x20dc8d93U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0xac21296cU), bswap_32big(0x74c982d6U), bswap_32big(0x9c2cd4b5U), + bswap_32big(0x228a3134U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0xd04cf276U), bswap_32big(0x0f2de17eU), bswap_32big(0x4b5d93f7U), + bswap_32big(0x7b7feebaU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0xb99d2cb7U), bswap_32big(0xd1c91f22U), bswap_32big(0xb66687b5U), + bswap_32big(0x3ce6f5dbU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + r_rsip_func214(); + + r_rsip_func101(bswap_32big(0x9654977aU), bswap_32big(0xd9dab7afU), bswap_32big(0x60d4b208U), + bswap_32big(0xda074296U)); + } + else + { + ; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p8f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p8f.c new file mode 100644 index 0000000000..b2dacefeb0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p8f.c @@ -0,0 +1,471 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p8f (const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_WrappedKeyIndex[], + uint32_t OutData_Text[], + uint32_t KEY_INDEX_SIZE, + uint32_t WRAPPED_KEY_SIZE) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B4H, 0x0000001dU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x008f0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_WrappedKeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003409U); + + WR1_PROG(REG_1600H, 0x3420a900U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x028a0cbbU), + bswap_32big(0x40697bf1U), + bswap_32big(0x1816f508U), + bswap_32big(0x6c044d0eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x48e2ca3cU), bswap_32big(0xba015e40U), bswap_32big(0xeece954bU), + bswap_32big(0x09e53f29U)); + WR1_PROG(REG_14B4H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00008f01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe2c5515dU), bswap_32big(0x629ac68bU), bswap_32big(0x9b8282ccU), + bswap_32big(0x3fd2c138U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x0e2189e0U), bswap_32big(0x1e75781cU), bswap_32big(0x6def5d24U), + bswap_32big(0x87f14c42U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00008f01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x053bef49U), bswap_32big(0x8641d4b2U), bswap_32big(0xb6e32ec2U), + bswap_32big(0x58ef0673U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x761b584cU), bswap_32big(0x0539381bU), bswap_32big(0x7adc43e3U), + bswap_32big(0x0b25fb8eU)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_182CH, 0x00000000U); + + r_rsip_func101(bswap_32big(0x195a4dc1U), bswap_32big(0x7b015d19U), bswap_32big(0xa7b9599fU), + bswap_32big(0x683928c1U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00008f02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x47736210U), bswap_32big(0x3e1ae5bcU), bswap_32big(0xdc81757aU), + bswap_32big(0xfdd99ba4U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xc2c71bf6U), bswap_32big(0x795d20c4U), bswap_32big(0x18121a7cU), + bswap_32big(0xec06ff95U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x58e3d241U), bswap_32big(0x312e4e4eU), bswap_32big(0x40f10a05U), + bswap_32big(0xf21f15feU)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_182CH, 0x40000000U); + + r_rsip_func101(bswap_32big(0x49aedde1U), bswap_32big(0x8b816fdaU), bswap_32big(0xcae25c76U), + bswap_32big(0x70a88ae5U)); + } + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xfdb7088dU), bswap_32big(0x93fc06b3U), bswap_32big(0x07fc0f7eU), + bswap_32big(0x5eb38b57U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8d4ff5f1U), bswap_32big(0xd2545684U), bswap_32big(0x6b56ebe0U), + bswap_32big(0x221d6b1aU)); + WR1_PROG(REG_14B4H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func030(); + + WR1_PROG(REG_1600H, 0x000035c7U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_WrappedKeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00008f02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb62b748dU), bswap_32big(0x8fbd6610U), bswap_32big(0xa9c91c45U), + bswap_32big(0xc9240f9eU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e6U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00008f03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x395b3e5bU), bswap_32big(0x1d52f6f8U), bswap_32big(0x5f34bef1U), + bswap_32big(0x40236ddfU)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x000034eeU); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1600H, 0x0000b780U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x0000a8e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + for (iLoop = 0U; iLoop < KEY_INDEX_SIZE - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_WrappedKeyIndex[iLoop + 1]); + + WR1_PROG(REG_1608H, 0x8084001fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000027fcU); + + WR1_PROG(REG_1600H, 0x000027dbU); + + r_rsip_func101(bswap_32big(0x7f5cec79U), + bswap_32big(0x2be2151fU), + bswap_32big(0xabf0c984U), + bswap_32big(0x7f58aef6U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000bc7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_WrappedKeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xc7a1ed92U), bswap_32big(0xcfddade1U), bswap_32big(0x3a9c19e4U), + bswap_32big(0x42d6de77U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x329b5189U), + bswap_32big(0x9431dac3U), + bswap_32big(0x6235cc44U), + bswap_32big(0x234f64deU)); + WR1_PROG(REG_14B4H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0xa6a6a6a6U); + WR1_PROG(REG_1600H, 0x00003420U); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1600H, 0x0000b780U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + for (jLoop = 0U; jLoop <= 5; jLoop++) + { + WR1_PROG(REG_1600H, 0x000037fbU); + + WR1_PROG(REG_1600H, 0x00000bbdU); + + for (iLoop = 1; iLoop <= (WRAPPED_KEY_SIZE - 2) / 2; iLoop++) + { + WR1_PROG(REG_1824H, 0x0a008105U); + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1608H, 0x8182001fU); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000824U); + + WR1_PROG(REG_1600H, 0x00003c5fU); + WR1_PROG(REG_1600H, 0x000027fcU); + WR1_PROG(REG_1600H, 0x00003c7fU); + WR1_PROG(REG_1600H, 0x000027fcU); + + WR1_PROG(REG_1600H, 0x00002c80U); + + WR1_PROG(REG_1600H, 0x00002fa0U); + + r_rsip_func101(bswap_32big(0xfd5a860dU), + bswap_32big(0x8c14061eU), + bswap_32big(0xcfc1d543U), + bswap_32big(0x2ab0b6a3U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ba5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002fc0U); + + r_rsip_func101(bswap_32big(0x23d9c946U), + bswap_32big(0x854c9920U), + bswap_32big(0xfb74a4cfU), + bswap_32big(0x49bd84c7U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008bc0U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1600H, 0x00003c1fU); + WR1_PROG(REG_1600H, 0x000027fcU); + WR1_PROG(REG_1600H, 0x00003c3fU); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + WR1_PROG(REG_1600H, 0x000037a5U); + WR1_PROG(REG_1600H, 0x00002fa0U); + + WR1_PROG(REG_1600H, 0x0000b780U); + WR1_PROG(REG_1600H, 0x00000008U); + + for (iLoop = 0U; iLoop < WRAPPED_KEY_SIZE; ) + { + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1600H, 0x34202bddU); + WR1_PROG(REG_1600H, 0x2000d0c0U); + + WR1_PROG(REG_1600H, 0x00007c06U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xfb11b1c0U), + bswap_32big(0xcc3434caU), + bswap_32big(0xea166ad2U), + bswap_32big(0x88637393U)); + WR1_PROG(REG_1608H, 0x8182001fU); + WR1_PROG(REG_1408H, 0x0000500aU); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 1]); + + WR1_PROG(REG_1600H, 0x000027fcU); + + WR1_PROG(REG_1600H, 0x00002fc0U); + + r_rsip_func101(bswap_32big(0xf345f53dU), + bswap_32big(0xf58ec480U), + bswap_32big(0xea093b02U), + bswap_32big(0xf5387c5fU)); + iLoop = iLoop + 2; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000bddU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func102(bswap_32big(0xb7614d87U), + bswap_32big(0x36498aadU), + bswap_32big(0x66753f20U), + bswap_32big(0xf279371dU)); + WR1_PROG(REG_14B4H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p90.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p90.c new file mode 100644 index 0000000000..a544396eca --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p90.c @@ -0,0 +1,551 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p90 (const uint32_t InData_KeyType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_Text[], + uint32_t OutData_KeyIndex[], + uint32_t WRAPPED_KEY_SIZE, + uint32_t KEY_INDEX_SIZE) +{ + uint32_t iLoop = 0U; + int32_t jLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00900001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000002c7U); + WR1_PROG(REG_1608H, 0x80030100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_WrappedKeyType[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x00003409U); + + WR1_PROG(REG_1600H, 0x3420a900U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x1000d3e1U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xad66c77fU), + bswap_32big(0x3d58a044U), + bswap_32big(0x7177f584U), + bswap_32big(0xaaaca63aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x53dd04acU), bswap_32big(0x2687190cU), bswap_32big(0x19117b61U), + bswap_32big(0x2450fea0U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00009001U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6df902f9U), bswap_32big(0x8fdd71f6U), bswap_32big(0xc334a2a2U), + bswap_32big(0x98fd07f4U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xc67dcc4fU), bswap_32big(0xbf0b42d2U), bswap_32big(0x1ba21cb8U), + bswap_32big(0xd0848d2bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00009001U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x71a4d79dU), bswap_32big(0x19fd9f09U), bswap_32big(0x8a323c35U), + bswap_32big(0x16e814dfU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x97a9554eU), bswap_32big(0xb7ed34d5U), bswap_32big(0x63433838U), + bswap_32big(0xded20c05U)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_182CH, 0x00000000U); + + r_rsip_func101(bswap_32big(0x88a11ba8U), bswap_32big(0x25d2dd49U), bswap_32big(0xc54547e5U), + bswap_32big(0xb5e51761U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00009002U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x976d8b53U), bswap_32big(0x4cdebaeeU), bswap_32big(0x2117aa2eU), + bswap_32big(0x6bfeccceU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x2c4b16b2U), bswap_32big(0xc212d40aU), bswap_32big(0xde528630U), + bswap_32big(0xe71e6ac1U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xcd4d0f80U), bswap_32big(0x1ee104bcU), bswap_32big(0x8c7c1df8U), + bswap_32big(0xdcce2de5U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_182CH, 0x40000000U); + + r_rsip_func101(bswap_32big(0x6954764aU), bswap_32big(0x1e9645f4U), bswap_32big(0x2fa7f32cU), + bswap_32big(0x4a62ae8cU)); + } + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xd662c849U), bswap_32big(0xe7917962U), bswap_32big(0xe9c510afU), + bswap_32big(0xdb7207c6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x7e8b4a58U), bswap_32big(0x3b9b4932U), bswap_32big(0xa71d5890U), + bswap_32big(0x220057e4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func030(); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + WR1_PROG(REG_1600H, 0x000035c7U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1600H, 0x00002fc0U); + + WR1_PROG(REG_1600H, 0x0000b780U); + WR1_PROG(REG_1600H, 0x00000008U); + + for (iLoop = 2; iLoop < WRAPPED_KEY_SIZE; ) + { + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x8082001fU); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000027fcU); + + WR1_PROG(REG_1600H, 0x00002fc0U); + + r_rsip_func101(bswap_32big(0xe32ea363U), + bswap_32big(0x7ef18789U), + bswap_32big(0xfeeb6aaaU), + bswap_32big(0x415870dfU)); + iLoop = iLoop + 2; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000bc5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000377fU); + WR1_PROG(REG_1600H, 0x0000ab60U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1600H, 0x00003785U); + WR1_PROG(REG_1600H, 0x00003380U); + + WR1_PROG(REG_1600H, 0x0000349cU); + WR1_PROG(REG_1600H, 0x00026c84U); + WR1_PROG(REG_1600H, 0x00016f9cU); + WR1_PROG(REG_1600H, 0x0000249cU); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + WR1_PROG(REG_1600H, 0x0000b720U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x0000b740U); + WR1_PROG(REG_1600H, 0x0000000cU); + + WR1_PROG(REG_1600H, 0x00003785U); + WR1_PROG(REG_1600H, 0x00003380U); + + for (jLoop = 5; jLoop >= 0; jLoop = jLoop - 1) + { + WR1_PROG(REG_1600H, 0x000037fbU); + + WR1_PROG(REG_1600H, 0x00000bbdU); + + for (iLoop = (WRAPPED_KEY_SIZE / 2) - 1; iLoop >= 1; iLoop = iLoop - 1) + { + WR1_PROG(REG_1600H, 0x00000824U); + + WR1_PROG(REG_1824H, 0x0a00810dU); + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1608H, 0x8182001fU); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003c5fU); + WR1_PROG(REG_1600H, 0x000027f9U); + WR1_PROG(REG_1600H, 0x00003c7fU); + WR1_PROG(REG_1600H, 0x00002bfaU); + + WR1_PROG(REG_1600H, 0x00003080U); + + WR1_PROG(REG_1600H, 0x00002fa0U); + + r_rsip_func101(bswap_32big(0xcb6a02e1U), + bswap_32big(0xf88fab4fU), + bswap_32big(0x1fe350eeU), + bswap_32big(0x32a572beU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000bbcU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002fc0U); + + r_rsip_func101(bswap_32big(0xa540fd47U), + bswap_32big(0x45625612U), + bswap_32big(0x80525ae6U), + bswap_32big(0xc9c79756U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008bc0U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0xa6a6a6a6U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0xa6a6a6a6U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xeedf8f42U), bswap_32big(0x3e20cbb6U), bswap_32big(0x83827a1dU), + bswap_32big(0x013c7fbcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0a3b2562U), + bswap_32big(0x888edb8cU), + bswap_32big(0x08a8aae0U), + bswap_32big(0x84120fb9U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000090U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfeb36c48U), + bswap_32big(0xac56c762U), + bswap_32big(0xb8f9255dU), + bswap_32big(0xe9b4b8e6U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00009002U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf32a56abU), + bswap_32big(0x1995610bU), + bswap_32big(0xb14ed73aU), + bswap_32big(0x405ebba5U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e6U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00009003U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd231b630U), + bswap_32big(0xaab41079U), + bswap_32big(0xd7808171U), + bswap_32big(0xca2e20a9U)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x000034eeU); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x0000b780U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000a8e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + for (iLoop = 0U; iLoop < KEY_INDEX_SIZE - 5; ) + { + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1600H, 0x34202bc7U); + WR1_PROG(REG_1600H, 0x2000d0c0U); + + WR1_PROG(REG_1600H, 0x00007c06U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xb16f7bf8U), + bswap_32big(0xa92cda17U), + bswap_32big(0xebb4c7e2U), + bswap_32big(0x6918513aU)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + + WR1_PROG(REG_1608H, 0x8184001fU); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1600H, 0x000027fcU); + + WR1_PROG(REG_1600H, 0x000027dbU); + + r_rsip_func101(bswap_32big(0x5e610fafU), + bswap_32big(0x48fe9b73U), + bswap_32big(0xf4a55d6cU), + bswap_32big(0xd8840f81U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000bc7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xf2af22c3U), + bswap_32big(0x971f99baU), + bswap_32big(0x6e689b1aU), + bswap_32big(0x2b1cbfbbU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[iLoop + 1]); + + r_rsip_func100(bswap_32big(0x905de4baU), + bswap_32big(0xd744a462U), + bswap_32big(0xf7df0b72U), + bswap_32big(0x09349832U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func102(bswap_32big(0xa33f3031U), + bswap_32big(0xc68a2934U), + bswap_32big(0x3bfc0b83U), + bswap_32big(0x78b48cbfU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95f.c new file mode 100644 index 0000000000..82716d941a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95f.c @@ -0,0 +1,119 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p95f (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x00003409U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xa11068c4U), + bswap_32big(0xb7f332a7U), + bswap_32big(0x03f43030U), + bswap_32big(0xea88e86bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xe7000d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x148f2f03U), bswap_32big(0xdc09a971U), bswap_32big(0xc435d56cU), + bswap_32big(0x68310accU)); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0xd7c1f698U), bswap_32big(0x6eaca583U), bswap_32big(0xd7e2bf25U), + bswap_32big(0x3406b295U)); + } + else + { + r_rsip_func101(bswap_32big(0x38cd3bbbU), bswap_32big(0xb23c38edU), bswap_32big(0x471a3732U), + bswap_32big(0xc71c9a20U)); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0x2f193d6dU), + bswap_32big(0x226cd42cU), + bswap_32big(0x6d345a31U), + bswap_32big(0x8bfec233U)); + WR1_PROG(REG_1824H, 0x09100105U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0x8e0070bbU), + bswap_32big(0x5db79a38U), + bswap_32big(0x8a809e10U), + bswap_32big(0x1b8591a0U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95i.c new file mode 100644 index 0000000000..49538b90c2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95i.c @@ -0,0 +1,470 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p95i (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00950001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003640U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010120U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x28fe8c10U), + bswap_32big(0x351c0eadU), + bswap_32big(0x802ce382U), + bswap_32big(0xbf51357eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x3420a920U); + WR1_PROG(REG_1600H, 0x00004101U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func101(bswap_32big(0x42640d0bU), bswap_32big(0xee27a885U), bswap_32big(0x330402edU), + bswap_32big(0x54459ca6U)); + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x6c3c524fU), + bswap_32big(0x31422a56U), + bswap_32big(0x61f0cf00U), + bswap_32big(0x53c27a42U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe8526d3aU), bswap_32big(0x2922e025U), bswap_32big(0xe8c8ffd0U), + bswap_32big(0x09be2a1bU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x6db572deU), bswap_32big(0x87930f61U), bswap_32big(0x5d49264cU), + bswap_32big(0xb83417eeU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xe4dc1b19U), bswap_32big(0x00bc5646U), bswap_32big(0xbe08c9f4U), + bswap_32big(0x55c74592U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000095U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe43624e0U), + bswap_32big(0xe4b1a9c2U), + bswap_32big(0xb8468791U), + bswap_32big(0x1f1e7a18U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + r_rsip_func101(bswap_32big(0xfa9d7930U), + bswap_32big(0xaa0bf54bU), + bswap_32big(0x681d26f1U), + bswap_32big(0x8f9da5eeU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000095U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbda29cb3U), + bswap_32big(0x3eb81b4fU), + bswap_32big(0x3851b8bcU), + bswap_32big(0x2730facdU)); + r_rsip_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + + r_rsip_func101(bswap_32big(0xa3fbc8bcU), + bswap_32big(0x9e3acd2fU), + bswap_32big(0xba61703aU), + bswap_32big(0xbdeaebb7U)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000095U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2da82aaaU), bswap_32big(0xba91ffe4U), bswap_32big(0xb15309d1U), + bswap_32big(0x82b077b6U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xd89a5596U), bswap_32big(0x79932fb5U), bswap_32big(0xce04f76bU), + bswap_32big(0x52970cf7U)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x4272e8daU), bswap_32big(0xf35091c0U), bswap_32big(0x8eecf4cdU), + bswap_32big(0xb3c1a270U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x04b09d73U), bswap_32big(0xf03a84ccU), bswap_32big(0x99c99ec4U), + bswap_32big(0x2cd0aab4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000036a0U); + + WR1_PROG(REG_1600H, 0x0000b6c0U); + WR1_PROG(REG_1600H, 0x4cc18a1aU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000095U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4bb3c619U), + bswap_32big(0x3cf25d1bU), + bswap_32big(0x53cf2426U), + bswap_32big(0x323544fdU)); + r_rsip_func092(); + + r_rsip_func101(bswap_32big(0xad03e763U), + bswap_32big(0xf463fa26U), + bswap_32big(0x4023d4e6U), + bswap_32big(0x6dd2bee7U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000dfU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb16f26f4U), + bswap_32big(0x38f5e084U), + bswap_32big(0x529da794U), + bswap_32big(0xd4b85e49U)); + r_rsip_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x6ad6575eU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000ebU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x91435511U), + bswap_32big(0x21b8a36fU), + bswap_32big(0x3e71e1d9U), + bswap_32big(0x6cc7ecf8U)); + r_rsip_func044(); + + r_rsip_func101(bswap_32big(0x21b0e26aU), + bswap_32big(0x7f26f817U), + bswap_32big(0x433805deU), + bswap_32big(0x61c4c017U)); + } + + r_rsip_func100(bswap_32big(0xffb15aefU), bswap_32big(0xb1a0c5cdU), bswap_32big(0x3a281150U), + bswap_32big(0x3b326628U)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x5c27ea77U), bswap_32big(0x451a92afU), bswap_32big(0x0e946632U), + bswap_32big(0x71657b58U)); + } + + r_rsip_func100(bswap_32big(0x18e89b1bU), bswap_32big(0x24ad6f3bU), bswap_32big(0x9714058aU), + bswap_32big(0xa6e54852U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x863a2e91U), bswap_32big(0x291c0f32U), bswap_32big(0x94f4fb73U), + bswap_32big(0xadd64ef2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003412U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x295088a0U), bswap_32big(0x2144fe6eU), bswap_32big(0x9457b560U), + bswap_32big(0x204b5d40U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0xf8000006U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0x6a10897eU), + bswap_32big(0xc1e73e37U), + bswap_32big(0x1cd4acceU), + bswap_32big(0x5c2c8f55U)); + } + else + { + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x800201c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008aeU); + WR1_PROG(REG_1600H, 0x000008cfU); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x01986c64U); + WR1_PROG(REG_1600H, 0x01986c85U); + WR1_PROG(REG_1600H, 0x01986ca6U); + WR1_PROG(REG_1600H, 0x00186cc6U); + + WR1_PROG(REG_1824H, 0x08000145U); + WR1_PROG(REG_1608H, 0x81040060U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x00000010U); + r_rsip_func031(InData_Header); + + r_rsip_func101(bswap_32big(0x0934175bU), + bswap_32big(0x6529f37bU), + bswap_32big(0x7d0c1e5cU), + bswap_32big(0xb987c71fU)); + } + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95u.c new file mode 100644 index 0000000000..fc4803b453 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p95u.c @@ -0,0 +1,52 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p95u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x46f4be2bU), + bswap_32big(0x4f4daf78U), + bswap_32big(0x1df04261U), + bswap_32big(0x2704085aU)); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_1824H, 0xe7000d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + r_rsip_func215(); + + r_rsip_func101(bswap_32big(0x32c11cdfU), + bswap_32big(0x6a2a7e8dU), + bswap_32big(0x53668c30U), + bswap_32big(0x2afae318U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98f.c new file mode 100644 index 0000000000..ce66fe10c6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98f.c @@ -0,0 +1,197 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p98f (const uint32_t InData_Text[], const uint32_t InData_MAC[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x5a7ec03cU), + bswap_32big(0xa68a74c7U), + bswap_32big(0xca681fc6U), + bswap_32big(0x7f414f09U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x54dfa407U), bswap_32big(0x3a426fbfU), bswap_32big(0x36c7d35fU), + bswap_32big(0xac86215eU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x27a12520U), bswap_32big(0x1906db13U), bswap_32big(0xe4b3dd48U), + bswap_32big(0x3f254163U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x07000d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x52fc845cU), bswap_32big(0xd6c324efU), bswap_32big(0x0796c6e2U), + bswap_32big(0x0e235bffU)); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + WR1_PROG(REG_1824H, 0x0e100405U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xa66ccc5cU), bswap_32big(0x0b2f7bf8U), bswap_32big(0xe25f41ebU), + bswap_32big(0xda2e36fdU)); + } + else + { + r_rsip_func101(bswap_32big(0xf67e7fcaU), bswap_32big(0x518271e5U), bswap_32big(0x23438b3dU), + bswap_32big(0x18214108U)); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c100104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1824H, 0x07200d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a540U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xe766706dU), bswap_32big(0x37ee4d54U), bswap_32big(0xfef96882U), + bswap_32big(0x486534f4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x7220e070U), bswap_32big(0x61f2d5d5U), bswap_32big(0x3b9c3699U), + bswap_32big(0x2de01c9dU)); + + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0xe508df83U), bswap_32big(0x3f703852U), bswap_32big(0xbf858488U), + bswap_32big(0x030d79bdU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98i.c new file mode 100644 index 0000000000..677e31e70b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98i.c @@ -0,0 +1,491 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_p98i (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00980001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003640U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010120U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003689U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x07f7d3adU), + bswap_32big(0xe7e18e46U), + bswap_32big(0x0c7c9777U), + bswap_32big(0x08fcd417U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MACLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd2d21e10U), bswap_32big(0x38dc7f8cU), bswap_32big(0x571b1409U), + bswap_32big(0x03814f66U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x3420a920U); + WR1_PROG(REG_1600H, 0x00004101U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func101(bswap_32big(0xb80412b3U), bswap_32big(0x6a869691U), bswap_32big(0xc5f6796aU), + bswap_32big(0x08883696U)); + } + + WR1_PROG(REG_1600H, 0x0000366aU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x780f33baU), + bswap_32big(0xe21013f8U), + bswap_32big(0xbd489679U), + bswap_32big(0x21a911e8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xc08b2bd8U), bswap_32big(0x2650909dU), bswap_32big(0x0be12f4eU), + bswap_32big(0x33e8bbb0U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x1377180bU), bswap_32big(0xd0efb08bU), bswap_32big(0xa4dd7d8eU), + bswap_32big(0xf599f9b8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xeb3e68bdU), bswap_32big(0x1624ece4U), bswap_32big(0xaef68fe4U), + bswap_32big(0x8295253aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000098U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2a6743e3U), + bswap_32big(0xc5f99062U), + bswap_32big(0xc0036048U), + bswap_32big(0xcd77e7beU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000005U); + + r_rsip_func101(bswap_32big(0xfb66bbdeU), + bswap_32big(0x0dc61ec7U), + bswap_32big(0x01c0c80bU), + bswap_32big(0xfe5079ffU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000098U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf326e5f9U), + bswap_32big(0x3b4f3a4dU), + bswap_32big(0x85f9f081U), + bswap_32big(0xeeb7a449U)); + r_rsip_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + + r_rsip_func101(bswap_32big(0xad61608bU), + bswap_32big(0xb4f1990aU), + bswap_32big(0xbccbb331U), + bswap_32big(0xb2ec6be9U)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000098U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd7b6888bU), bswap_32big(0x53b1ffbbU), bswap_32big(0xf528690eU), + bswap_32big(0xf634547dU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xdfb9e6fdU), bswap_32big(0x038dc6bcU), bswap_32big(0x3baba902U), + bswap_32big(0xdc91ad82U)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x0dd4724eU), bswap_32big(0x002c51f3U), bswap_32big(0xa7562e3fU), + bswap_32big(0xb0530559U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xb1483cf3U), bswap_32big(0x9395000fU), bswap_32big(0xbf42cfbdU), + bswap_32big(0x47e0d856U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000036a0U); + + WR1_PROG(REG_1600H, 0x0000b6c0U); + WR1_PROG(REG_1600H, 0x8026ee7fU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000098U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7c0fea46U), + bswap_32big(0x86f3c34aU), + bswap_32big(0x85bc3dffU), + bswap_32big(0xee522f80U)); + r_rsip_func092(); + + r_rsip_func101(bswap_32big(0xee21bc6fU), + bswap_32big(0x78c6b471U), + bswap_32big(0x2f5d5cb8U), + bswap_32big(0x0baa76d7U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000003U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbd535448U), + bswap_32big(0x23995423U), + bswap_32big(0x703ed7f2U), + bswap_32big(0x28c7c4daU)); + r_rsip_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x98bae316U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000ccU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x311549fdU), + bswap_32big(0x4178cdfdU), + bswap_32big(0x85f2e598U), + bswap_32big(0xdefc168fU)); + r_rsip_func044(); + + r_rsip_func101(bswap_32big(0x03fc24f6U), + bswap_32big(0xb2214770U), + bswap_32big(0x5f764c4dU), + bswap_32big(0xe34f086eU)); + } + + r_rsip_func100(bswap_32big(0x2800bbc9U), bswap_32big(0x8f5414aeU), bswap_32big(0x937101efU), + bswap_32big(0x349a0e0aU)); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x48f2ab55U), bswap_32big(0xec4d6b94U), bswap_32big(0x821c67e2U), + bswap_32big(0xf5e5b8c6U)); + } + + r_rsip_func100(bswap_32big(0x1e044adeU), bswap_32big(0x56e26d1cU), bswap_32big(0xfa4cf9b6U), + bswap_32big(0x24ff0d46U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x58130d85U), bswap_32big(0x1f1691b3U), bswap_32big(0x8234a9b0U), + bswap_32big(0xd8aba884U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003534U); + + WR1_PROG(REG_1600H, 0x00003553U); + + WR1_PROG(REG_1600H, 0x00003412U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xfee8981dU), bswap_32big(0xd8fd762aU), bswap_32big(0x780dde0aU), + bswap_32big(0x7c586fe9U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0xf8000006U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + r_rsip_func101(bswap_32big(0xedd9569fU), + bswap_32big(0x05dccab3U), + bswap_32big(0x413b5813U), + bswap_32big(0xb1f5ea28U)); + } + else + { + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x800201c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008aeU); + WR1_PROG(REG_1600H, 0x000008cfU); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x01986c64U); + WR1_PROG(REG_1600H, 0x01986c85U); + WR1_PROG(REG_1600H, 0x01986ca6U); + WR1_PROG(REG_1600H, 0x00186cc6U); + + WR1_PROG(REG_1824H, 0x08000145U); + WR1_PROG(REG_1608H, 0x81040060U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func031(InData_Header); + + r_rsip_func101(bswap_32big(0x3e8ee2feU), + bswap_32big(0xbcf98c4eU), + bswap_32big(0x5adc5e56U), + bswap_32big(0xc1ae4c8bU)); + } + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98u.c new file mode 100644 index 0000000000..1ff19ada11 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_p98u.c @@ -0,0 +1,52 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_p98u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x7c990721U), + bswap_32big(0x564f8465U), + bswap_32big(0xc6d4dbe8U), + bswap_32big(0xb5229b1fU)); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_1824H, 0xf7000d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + r_rsip_func215(); + + r_rsip_func101(bswap_32big(0x6ba5d6e9U), + bswap_32big(0x4dfeaedeU), + bswap_32big(0x616ff98cU), + bswap_32big(0x7e8c045cU)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1f.c new file mode 100644 index 0000000000..22e57ca762 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1f.c @@ -0,0 +1,128 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pa1f (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x359d8875U), + bswap_32big(0xb4d028b9U), + bswap_32big(0x8b65e2deU), + bswap_32big(0xa8764758U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0xe7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xa61cb9caU), bswap_32big(0xdadd00a8U), bswap_32big(0x2fc0736fU), + bswap_32big(0xeba7b8e3U)); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0x3079c684U), bswap_32big(0x8f09d05bU), bswap_32big(0x88440006U), + bswap_32big(0x2adfbd17U)); + } + else + { + r_rsip_func101(bswap_32big(0x57d1b79eU), bswap_32big(0xa4ce084fU), bswap_32big(0xd27985a0U), + bswap_32big(0x80c506fbU)); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0xe614456eU), + bswap_32big(0x2bc72697U), + bswap_32big(0x7985d797U), + bswap_32big(0x0d6e0886U)); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0xfb511ef2U), + bswap_32big(0x200868c2U), + bswap_32big(0x1a5956a1U), + bswap_32big(0xbcad812aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1i.c new file mode 100644 index 0000000000..3fbd3561ca --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1i.c @@ -0,0 +1,223 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pa1i (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00a10001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x2180f8a5U), + bswap_32big(0x5f517e8aU), + bswap_32big(0x3888aba0U), + bswap_32big(0x1822a59bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x5cd308eaU), bswap_32big(0x25a53a91U), bswap_32big(0x8d0e273aU), + bswap_32big(0xf25800a2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xafec45fdU), bswap_32big(0x2f687662U), bswap_32big(0xa5851f2aU), + bswap_32big(0x5df143e8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000a1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x357eb2ecU), bswap_32big(0x53f0d1fbU), bswap_32big(0xf36ed08aU), + bswap_32big(0xe997ad4fU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + r_rsip_func101(bswap_32big(0x6a968522U), bswap_32big(0x9e379da3U), bswap_32big(0xe47daad6U), + bswap_32big(0x9bf9c2faU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000a1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x88b3c802U), bswap_32big(0x43021533U), bswap_32big(0x5dae71e6U), + bswap_32big(0xc11f739eU)); + r_rsip_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x85d04999U); + + r_rsip_func101(bswap_32big(0x03bf4f95U), bswap_32big(0x7d1f7b6aU), bswap_32big(0x4ba55fb1U), + bswap_32big(0x5fb2fbfcU)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000a1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfdd9e5baU), bswap_32big(0x88bd16f5U), bswap_32big(0x40135118U), + bswap_32big(0xc8ffd98dU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x0600a1acU), bswap_32big(0xceb3af36U), bswap_32big(0x526a98ccU), + bswap_32big(0x455d0559U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x6ea94097U), bswap_32big(0xc75f42d5U), bswap_32big(0x00f1e439U), + bswap_32big(0x0c0190bdU)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x8cbbdc09U), bswap_32big(0x08bc0974U), bswap_32big(0x49e41958U), + bswap_32big(0x5d2f6346U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x3da7e49dU), bswap_32big(0x7ecc2848U), bswap_32big(0x910953efU), + bswap_32big(0x46427edfU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e108406U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1u.c new file mode 100644 index 0000000000..7269a75f54 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa1u.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_pa1u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0xc5933819U), + bswap_32big(0xc7dbf726U), + bswap_32big(0x9aa827ecU), + bswap_32big(0x19a40762U)); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0xe7008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + r_rsip_func215(); + + r_rsip_func101(bswap_32big(0x21768843U), + bswap_32big(0x13221602U), + bswap_32big(0xe9ba65aaU), + bswap_32big(0xc499426cU)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4f.c new file mode 100644 index 0000000000..5ef27e0470 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4f.c @@ -0,0 +1,214 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pa4f (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MACLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xf2a7c1bcU), + bswap_32big(0xe0d14548U), + bswap_32big(0xd6cf6b5bU), + bswap_32big(0xc434af82U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x33906ca7U), bswap_32big(0xf17e621eU), bswap_32big(0x138b58b5U), + bswap_32big(0x0380b926U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x5090e5d6U), bswap_32big(0x41b5819eU), bswap_32big(0x88cb7391U), + bswap_32big(0xefe03502U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xafb6e12fU), bswap_32big(0xc3d15fd1U), bswap_32big(0xb6962350U), + bswap_32big(0x8f7ce851U)); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e108405U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x6189f45eU), bswap_32big(0xed4656f7U), bswap_32big(0x7cfacebaU), + bswap_32big(0xbe8927acU)); + } + else + { + r_rsip_func101(bswap_32big(0x6872d4baU), bswap_32big(0xcc4ef1a3U), bswap_32big(0xd8ea0851U), + bswap_32big(0xfe2fdad3U)); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c100104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x07208d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a540U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xddabf2dbU), bswap_32big(0x5ab8904bU), bswap_32big(0xcb540cb9U), + bswap_32big(0x1bb97480U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x7a3cbe9dU), bswap_32big(0x17f6c9c0U), bswap_32big(0x193c1265U), + bswap_32big(0x0ae91024U)); + + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x44457413U), bswap_32big(0x5f9f11a3U), bswap_32big(0x0d141b1cU), + bswap_32big(0xcf9cefa3U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4i.c new file mode 100644 index 0000000000..581481bdd1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4i.c @@ -0,0 +1,223 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pa4i (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00a40001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xff3f702aU), + bswap_32big(0x1ae8edc4U), + bswap_32big(0xc128b4f6U), + bswap_32big(0x951ef814U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x06b37adaU), bswap_32big(0xc91ee093U), bswap_32big(0xb4fd0ccbU), + bswap_32big(0xb112cce2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x94c2109cU), bswap_32big(0xd1a6f9c0U), bswap_32big(0x475e625bU), + bswap_32big(0x95ebb36bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000a4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xae9cb379U), bswap_32big(0x4c67c054U), bswap_32big(0x31d6662dU), + bswap_32big(0x232457efU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000007U); + + r_rsip_func101(bswap_32big(0x7905e5e8U), bswap_32big(0xd3ee20b1U), bswap_32big(0xd8fb193bU), + bswap_32big(0x69d82933U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000a4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xec0b0fafU), bswap_32big(0x047cf2ceU), bswap_32big(0xc66b14a9U), + bswap_32big(0x965c7ba2U)); + r_rsip_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x85d04999U); + + r_rsip_func101(bswap_32big(0x1af9d5f2U), bswap_32big(0x9f40d4a3U), bswap_32big(0x40a045cfU), + bswap_32big(0x41000653U)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000a4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x606013b5U), bswap_32big(0x8581da59U), bswap_32big(0x99728532U), + bswap_32big(0x6bd20243U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x30c1e35bU), bswap_32big(0x4bb00969U), bswap_32big(0xb170457cU), + bswap_32big(0x16683880U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x37509494U), bswap_32big(0x27745a5aU), bswap_32big(0xef2512b3U), + bswap_32big(0x846cb5ffU)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xaece102dU), bswap_32big(0xc926df6bU), bswap_32big(0x2513dc0eU), + bswap_32big(0xf4e44517U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x20dd73d6U), bswap_32big(0x66252f67U), bswap_32big(0x5e1ed339U), + bswap_32big(0x55124a1aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e108406U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4u.c new file mode 100644 index 0000000000..8fe87ce80b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa4u.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_pa4u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x9eb16f83U), + bswap_32big(0x07489ad8U), + bswap_32big(0x2567e07fU), + bswap_32big(0xf6f72cbcU)); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0xf7008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + r_rsip_func215(); + + r_rsip_func101(bswap_32big(0x63dd8ff7U), + bswap_32big(0xa4b35995U), + bswap_32big(0x23f6f556U), + bswap_32big(0xce59c450U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7f.c new file mode 100644 index 0000000000..e930480fbe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7f.c @@ -0,0 +1,128 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pa7f (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x906b641fU), + bswap_32big(0x6aa6d3caU), + bswap_32big(0x58a04858U), + bswap_32big(0x1687648dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0xe7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x86664c46U), bswap_32big(0x0513b405U), bswap_32big(0x96d7d4acU), + bswap_32big(0x869c421cU)); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + r_rsip_func101(bswap_32big(0x7e7610d9U), bswap_32big(0xa263c2b8U), bswap_32big(0x6a5b6fd8U), + bswap_32big(0x90a218f4U)); + } + else + { + r_rsip_func101(bswap_32big(0x3bc47236U), bswap_32big(0x12c54170U), bswap_32big(0xddb1e9e3U), + bswap_32big(0xdd4de3ceU)); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0x20407f2fU), + bswap_32big(0x03dd53adU), + bswap_32big(0x166677feU), + bswap_32big(0x1390c519U)); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_MAC[0]); + + r_rsip_func102(bswap_32big(0x48e196aeU), + bswap_32big(0x684415a6U), + bswap_32big(0x67fd5d48U), + bswap_32big(0x2eb89ab9U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7i.c new file mode 100644 index 0000000000..8315b8a291 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7i.c @@ -0,0 +1,161 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pa7i (const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00a70001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000a7U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x88dfa970U), + bswap_32big(0xa8943563U), + bswap_32big(0x24571bdbU), + bswap_32big(0xc482f366U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000a7U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x893beed3U), + bswap_32big(0xea49cd50U), + bswap_32big(0x26ed1a30U), + bswap_32big(0x8de57d47U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xb4fd0ed9U), + bswap_32big(0xca24cf2dU), + bswap_32big(0x6284d46cU), + bswap_32big(0x1d7f394eU)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x38f1d1d5U), + bswap_32big(0x6d1e76a3U), + bswap_32big(0x09fe240cU), + bswap_32big(0x27098b75U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x6512547dU), + bswap_32big(0x1641a52eU), + bswap_32big(0x71f6a284U), + bswap_32big(0x18a020adU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0ee340daU), bswap_32big(0x6aa1f5deU), bswap_32big(0x02559e76U), + bswap_32big(0xd48807b8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e108456U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7u.c new file mode 100644 index 0000000000..8c73d1365b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pa7u.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_pa7u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x4d716914U), + bswap_32big(0x2050f446U), + bswap_32big(0x1fd8b94fU), + bswap_32big(0x9818a913U)); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0xe7008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + r_rsip_func215(); + + r_rsip_func101(bswap_32big(0xef60146dU), + bswap_32big(0xd4e37121U), + bswap_32big(0x11a5ad1dU), + bswap_32big(0x3dde9d47U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0f.c new file mode 100644 index 0000000000..0939e108e5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0f.c @@ -0,0 +1,214 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pb0f (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MACLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x3c982798U), + bswap_32big(0xab01bcbbU), + bswap_32big(0xc5affd93U), + bswap_32big(0xa8a63719U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xa7d47fdaU), bswap_32big(0xd2924d8dU), bswap_32big(0x31fa2a26U), + bswap_32big(0x016be777U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x0000000fU); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x202211d0U), bswap_32big(0xe32b68b9U), bswap_32big(0xb9949c55U), + bswap_32big(0x95c9213dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xf508b21aU), bswap_32big(0x86c4541bU), bswap_32big(0x10b4dddfU), + bswap_32big(0x07ab6870U)); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e108405U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xd775f6efU), bswap_32big(0xb3c23273U), bswap_32big(0xbf1f8414U), + bswap_32big(0x725f2999U)); + } + else + { + r_rsip_func101(bswap_32big(0xe4620497U), bswap_32big(0xc5b8543dU), bswap_32big(0x6e3e5170U), + bswap_32big(0x7d18de2cU)); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c100104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x07208d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a540U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1600H, 0x00002fe0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x84389ea9U), bswap_32big(0x4fe08abdU), bswap_32big(0x24f4f524U), + bswap_32big(0xc224dc91U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x392d9b21U), bswap_32big(0xaf8cd266U), bswap_32big(0xca162ec9U), + bswap_32big(0x95e952bdU)); + + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_AUTH_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0xe528a1d6U), bswap_32big(0x352b028fU), bswap_32big(0x8e1828c4U), + bswap_32big(0xdf2bddc8U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0i.c new file mode 100644 index 0000000000..046abf04b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0i.c @@ -0,0 +1,161 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pb0i (const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00b00001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x76ca7abdU), + bswap_32big(0xfbd732abU), + bswap_32big(0x025ad2a8U), + bswap_32big(0x8523dd4aU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000006U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbf594a4cU), + bswap_32big(0x70a5177eU), + bswap_32big(0xcad7ddffU), + bswap_32big(0x28104d46U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x38b1a9e2U), + bswap_32big(0xdfaa2cb5U), + bswap_32big(0xf599039dU), + bswap_32big(0x2eb9cd41U)); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x01b95625U), + bswap_32big(0x3fd7dc15U), + bswap_32big(0xd0bab388U), + bswap_32big(0xf8409483U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x1f6186e8U), + bswap_32big(0xa10e77acU), + bswap_32big(0x43dd6396U), + bswap_32big(0x4e55e96fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xc819606bU), bswap_32big(0x9a23f3faU), bswap_32big(0x20a6098aU), + bswap_32big(0x18815050U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e108406U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func216(); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0u.c new file mode 100644 index 0000000000..ca21f70a8f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb0u.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_pb0u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + r_rsip_func100(bswap_32big(0x5b80c98aU), + bswap_32big(0x877bfe2dU), + bswap_32big(0xf23341c7U), + bswap_32big(0x341cd6deU)); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0xf7008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + r_rsip_func215(); + + r_rsip_func101(bswap_32big(0x2c585ac3U), + bswap_32big(0x09e97e31U), + bswap_32big(0x65fcb5c9U), + bswap_32big(0xa86a73a7U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3f.c new file mode 100644 index 0000000000..1430ecda12 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3f.c @@ -0,0 +1,150 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pb3f (const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextBitLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func420(); + + r_rsip_func100(bswap_32big(0xa2b329ebU), + bswap_32big(0x631fbbc4U), + bswap_32big(0x3e5601bdU), + bswap_32big(0x4923be50U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xc624de30U), bswap_32big(0x11850024U), bswap_32big(0xcb45900bU), + bswap_32big(0xf67dbfa0U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x9e4d72d9U), bswap_32big(0x9d3b5addU), bswap_32big(0x39d9dda4U), + bswap_32big(0x4e3323efU)); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + r_rsip_func100(bswap_32big(0xd6eebc9eU), bswap_32big(0x3873f55cU), bswap_32big(0xd13a7613U), + bswap_32big(0xe00fe575U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d008906U); + WR1_PROG(REG_1408H, 0x000c1000U); + + iLoop = 0U; + if (S_RAM[0] >= 4) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4; iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + r_rsip_func214(); + + r_rsip_func421(); + + r_rsip_func100(bswap_32big(0x5c4a9214U), bswap_32big(0xb45b8579U), bswap_32big(0x87506f29U), + bswap_32big(0xb429c63fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d008905U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1608H, 0x80840006U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4803c617U), bswap_32big(0xf08fb4caU), bswap_32big(0x755f1b83U), + bswap_32big(0xc88eb0a8U)); + r_rsip_func422(InData_Text, iLoop); + + r_rsip_func100(bswap_32big(0xea499061U), bswap_32big(0x2b90e310U), bswap_32big(0x696d9aa1U), + bswap_32big(0x9274c340U)); + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d008905U); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xde3eab7eU), bswap_32big(0x79f979a2U), bswap_32big(0x2dead3fcU), + bswap_32big(0x95e5a368U)); + r_rsip_func423(OutData_Text, iLoop); + + r_rsip_func101(bswap_32big(0x43ed870dU), bswap_32big(0x7e283c7fU), bswap_32big(0xc056fbaaU), + bswap_32big(0xb1a22f90U)); + } + + r_rsip_func102(bswap_32big(0x1ccc8f5bU), bswap_32big(0xe70f7b76U), bswap_32big(0x2946320dU), + bswap_32big(0x53287152U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3i.c new file mode 100644 index 0000000000..8b9886d0f9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3i.c @@ -0,0 +1,153 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pb3i (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00b30001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6c24788cU), + bswap_32big(0x948505f9U), + bswap_32big(0xc127e67dU), + bswap_32big(0x1cb2c1f5U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x96059cfcU), + bswap_32big(0x23f8d351U), + bswap_32big(0xef861811U), + bswap_32big(0x8d923b27U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8088001fU); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x14ce11ebU), + bswap_32big(0x6eff92c0U), + bswap_32big(0x5a68f1a7U), + bswap_32big(0x33109b2cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x80f3ec65U), bswap_32big(0xc0674d52U), bswap_32big(0xd381deb4U), + bswap_32big(0xbd498eddU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x1ae211e9U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x6b034cb1U), bswap_32big(0x7194c79cU), bswap_32big(0xe3017edeU), + bswap_32big(0x51c0a62dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x267a3b43U), bswap_32big(0x15137165U), bswap_32big(0x348fd9e2U), + bswap_32big(0xd511d2ddU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x80a5f771U), bswap_32big(0xcca0ebedU), bswap_32big(0x6f482d6fU), + bswap_32big(0xc57f373aU)); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8188001fU); + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xcc7efcf6U), bswap_32big(0xd7fe8deeU), bswap_32big(0xf9676a2cU), + bswap_32big(0x7e07738fU)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0a010045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3u.c new file mode 100644 index 0000000000..a948861cd1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb3u.c @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_pb3u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + r_rsip_func100(bswap_32big(0x02fa6705U), + bswap_32big(0x5ab474d0U), + bswap_32big(0xe09d1923U), + bswap_32big(0x618d45f9U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d008906U); + WR1_PROG(REG_1408H, 0x000c1000U); + + r_rsip_func220(InData_Text, MAX_CNT, OutData_Text); + + r_rsip_func101(bswap_32big(0x22ae9ffcU), + bswap_32big(0x3b8baaedU), + bswap_32big(0x46803757U), + bswap_32big(0x837ed581U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6f.c new file mode 100644 index 0000000000..35eabedbbb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6f.c @@ -0,0 +1,171 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pb6f (const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextBitLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func420(); + + r_rsip_func100(bswap_32big(0x7c01aacbU), + bswap_32big(0x864e8f23U), + bswap_32big(0x248d218cU), + bswap_32big(0x6ec8fa97U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd8028364U), bswap_32big(0x65c84b4eU), bswap_32big(0x2e9aa15dU), + bswap_32big(0xa14d758cU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x67f0ac96U), bswap_32big(0xcd985bacU), bswap_32big(0x2ce6ff2aU), + bswap_32big(0xf15178dcU)); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + r_rsip_func100(bswap_32big(0x30b4b4a4U), bswap_32big(0x3563885fU), bswap_32big(0x55f7b03bU), + bswap_32big(0xb4d0cc23U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + + iLoop = 0U; + if (S_RAM[0] >= 4) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4; iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + r_rsip_func214(); + + r_rsip_func421(); + + r_rsip_func100(bswap_32big(0xe484c135U), bswap_32big(0x0b6e0f08U), bswap_32big(0x90a54cffU), + bswap_32big(0xb9a10744U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00880cU); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00890dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1608H, 0x80840006U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xca64a427U), bswap_32big(0xd5c808dbU), bswap_32big(0xfd1b57a0U), + bswap_32big(0xeb9f472aU)); + r_rsip_func422(InData_Text, iLoop); + + r_rsip_func100(bswap_32big(0xd5d42889U), bswap_32big(0xee004097U), bswap_32big(0x5b3a2005U), + bswap_32big(0x608bbddbU)); + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00890dU); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2ced1ab9U), bswap_32big(0xadd5c001U), bswap_32big(0x33dd57fdU), + bswap_32big(0xa3dfbc27U)); + r_rsip_func423(OutData_Text, iLoop); + + r_rsip_func101(bswap_32big(0xade353e8U), bswap_32big(0xb026af43U), bswap_32big(0x7399fd23U), + bswap_32big(0x5a0a2916U)); + } + + r_rsip_func102(bswap_32big(0x24589d04U), bswap_32big(0x03fdbb58U), bswap_32big(0xd42e458aU), + bswap_32big(0x13eaa7beU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6i.c new file mode 100644 index 0000000000..4c24f19d62 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6i.c @@ -0,0 +1,153 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pb6i (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00b60001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3758f0d5U), + bswap_32big(0x7624b886U), + bswap_32big(0x4acd213cU), + bswap_32big(0x02441220U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe61b375eU), + bswap_32big(0x44edba96U), + bswap_32big(0xcf8a3bc3U), + bswap_32big(0xafac43beU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8088001fU); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xccd28d8eU), + bswap_32big(0x480361f7U), + bswap_32big(0x0d692003U), + bswap_32big(0xb57c6a67U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0990e9feU), bswap_32big(0xfe7517e1U), bswap_32big(0xc0bf2176U), + bswap_32big(0xb477bcebU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x1ae211e9U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x01363f60U), bswap_32big(0xbb72682cU), bswap_32big(0x88037031U), + bswap_32big(0x09861a08U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xf6da9b1eU), bswap_32big(0x6582bf3bU), bswap_32big(0x7fe6fcbdU), + bswap_32big(0x0bf177e9U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x94f77138U), bswap_32big(0x7e50db79U), bswap_32big(0x8f101b2cU), + bswap_32big(0xcc75592cU)); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8188001fU); + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x2465c08bU), bswap_32big(0xe0f88521U), bswap_32big(0x330448a8U), + bswap_32big(0x143f1511U)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0a010045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6u.c new file mode 100644 index 0000000000..15386972f7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb6u.c @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_pb6u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + r_rsip_func100(bswap_32big(0x8b28d618U), + bswap_32big(0xca3e7296U), + bswap_32big(0x8b02a1cfU), + bswap_32big(0x48458921U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + + r_rsip_func220(InData_Text, MAX_CNT, OutData_Text); + + r_rsip_func101(bswap_32big(0x58211f97U), + bswap_32big(0x044b49b0U), + bswap_32big(0x4c29ece3U), + bswap_32big(0x2ecf9546U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9f.c new file mode 100644 index 0000000000..1cac5207ed --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9f.c @@ -0,0 +1,150 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pb9f (const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextBitLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func420(); + + r_rsip_func100(bswap_32big(0xcaa40270U), + bswap_32big(0x7da17216U), + bswap_32big(0x238f142dU), + bswap_32big(0x50d3d8beU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xbb0b0d7cU), bswap_32big(0x1ff1722eU), bswap_32big(0x88300f3eU), + bswap_32big(0xcfa81d52U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xb3cda820U), bswap_32big(0x0e5740e9U), bswap_32big(0x16a78d29U), + bswap_32big(0x2076db4fU)); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + r_rsip_func100(bswap_32big(0x4aa02ed9U), bswap_32big(0xf90cbfb5U), bswap_32big(0x96581b6eU), + bswap_32big(0x376132d8U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d008906U); + WR1_PROG(REG_1408H, 0x000c1000U); + + iLoop = 0U; + if (S_RAM[0] >= 4) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4; iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + r_rsip_func214(); + + r_rsip_func421(); + + r_rsip_func100(bswap_32big(0x1e330196U), bswap_32big(0x55d1b27eU), bswap_32big(0x18afca81U), + bswap_32big(0x793f6f0fU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d008905U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1608H, 0x80840006U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8c17f287U), bswap_32big(0x48a92d97U), bswap_32big(0x13a872d1U), + bswap_32big(0x012792ceU)); + r_rsip_func422(InData_Text, iLoop); + + r_rsip_func100(bswap_32big(0x3db01d75U), bswap_32big(0x87517df7U), bswap_32big(0xd4d775b5U), + bswap_32big(0xb8a52900U)); + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d008905U); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4df2d62aU), bswap_32big(0xba2e6df6U), bswap_32big(0x3f408632U), + bswap_32big(0xe43d421bU)); + r_rsip_func423(OutData_Text, iLoop); + + r_rsip_func101(bswap_32big(0x2772d859U), bswap_32big(0x2292abdaU), bswap_32big(0x306ca261U), + bswap_32big(0x87c613fbU)); + } + + r_rsip_func102(bswap_32big(0x85e21266U), bswap_32big(0x0d8a895bU), bswap_32big(0x38aedaefU), + bswap_32big(0x07600079U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9i.c new file mode 100644 index 0000000000..672834f7de --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9i.c @@ -0,0 +1,184 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pb9i (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00b90001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3c6a7b24U), + bswap_32big(0xfafd0275U), + bswap_32big(0x5685dc46U), + bswap_32big(0xa2e1d631U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000009U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000b9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4cdf0856U), + bswap_32big(0x39200853U), + bswap_32big(0x72b50e1fU), + bswap_32big(0xcf019744U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8090001fU); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x649edaf1U), + bswap_32big(0x7ab8c172U), + bswap_32big(0x4e912b68U), + bswap_32big(0x14d63d2aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x2fc4b034U), bswap_32big(0x5b5080a2U), bswap_32big(0x7b64e572U), + bswap_32big(0xf98e413dU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000020U); + + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x000037dfU); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000030U); + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x000013feU); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x1ae211e9U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x731f185fU), bswap_32big(0x8fb554f0U), bswap_32big(0x0da2437cU), + bswap_32big(0xe0ac1fbeU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xcf7335edU), bswap_32big(0x237ae70fU), bswap_32big(0x8ff314edU), + bswap_32big(0x179fe33aU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xe4aa5c6eU), bswap_32big(0x785cf1a6U), bswap_32big(0x9728dd8eU), + bswap_32big(0xcfbbe768U)); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8190001fU); + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x462c4ccdU), bswap_32big(0xdec74a9aU), bswap_32big(0x8f930f5bU), + bswap_32big(0x269549efU)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x1f3fe180U), bswap_32big(0x11eaa27eU), bswap_32big(0x70143472U), + bswap_32big(0xc99edb1bU)); + WR1_PROG(REG_1824H, 0x080000a5U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x5ae1daa4U), bswap_32big(0x541117d7U), bswap_32big(0x704bf8f1U), + bswap_32big(0xc945e7feU)); + WR1_PROG(REG_1824H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0a028045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9u.c new file mode 100644 index 0000000000..a5598c5e10 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pb9u.c @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_pb9u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + r_rsip_func100(bswap_32big(0xa8510faeU), + bswap_32big(0x1729f824U), + bswap_32big(0xa921e87dU), + bswap_32big(0x8dcf578aU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d008906U); + WR1_PROG(REG_1408H, 0x000c1000U); + + r_rsip_func220(InData_Text, MAX_CNT, OutData_Text); + + r_rsip_func101(bswap_32big(0x5d82b68fU), + bswap_32big(0x50c018a8U), + bswap_32big(0xc8af3e4bU), + bswap_32big(0x7397fee7U)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2f.c new file mode 100644 index 0000000000..955db3b950 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2f.c @@ -0,0 +1,171 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pc2f (const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextBitLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func420(); + + r_rsip_func100(bswap_32big(0xbf1c7addU), + bswap_32big(0xededf14dU), + bswap_32big(0xac838c61U), + bswap_32big(0x3d35fda6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xf8e17c5bU), bswap_32big(0xeb3f055fU), bswap_32big(0xd4d20c47U), + bswap_32big(0x9763c0d2U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xb2b1b68bU), bswap_32big(0xe5eeb010U), bswap_32big(0x0669c80cU), + bswap_32big(0x02935b69U)); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + r_rsip_func100(bswap_32big(0x1e5442f7U), bswap_32big(0x57477c26U), bswap_32big(0xdffdd3f3U), + bswap_32big(0x5cf6e44dU)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + + iLoop = 0U; + if (S_RAM[0] >= 4) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4; iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + r_rsip_func214(); + + r_rsip_func421(); + + r_rsip_func100(bswap_32big(0x2fca3410U), bswap_32big(0xa091cbdcU), bswap_32big(0x2e8d4dd9U), + bswap_32big(0xaff73664U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00880cU); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00890dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1608H, 0x80840006U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000c2U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x86849b58U), bswap_32big(0x217a910eU), bswap_32big(0xf97aac2aU), + bswap_32big(0x7eea2488U)); + r_rsip_func422(InData_Text, iLoop); + + r_rsip_func100(bswap_32big(0xfa07c7d4U), bswap_32big(0x4724d180U), bswap_32big(0x9253a8e2U), + bswap_32big(0x765ccfcaU)); + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00890dU); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000c2U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf8e7e138U), bswap_32big(0xf6492db4U), bswap_32big(0x4ac79170U), + bswap_32big(0x128c38e2U)); + r_rsip_func423(OutData_Text, iLoop); + + r_rsip_func101(bswap_32big(0x829d5553U), bswap_32big(0xc2cf0baeU), bswap_32big(0xe303b324U), + bswap_32big(0xb737b6f8U)); + } + + r_rsip_func102(bswap_32big(0x9d25dfb7U), bswap_32big(0x5a17938fU), bswap_32big(0x0ea6cda6U), + bswap_32big(0xc571ca1fU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2i.c new file mode 100644 index 0000000000..122c29778c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2i.c @@ -0,0 +1,184 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pc2i (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00c20001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000c2U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdbf87770U), + bswap_32big(0x23969f27U), + bswap_32big(0x07f4766bU), + bswap_32big(0x900237c4U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000009U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000c2U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9899acd7U), + bswap_32big(0x879509e6U), + bswap_32big(0x1de0802aU), + bswap_32big(0xc970f17aU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8090001fU); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xd0d1b508U), + bswap_32big(0xc32db85bU), + bswap_32big(0x67e557bbU), + bswap_32big(0x5b56c3d1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd67830ffU), bswap_32big(0x0685ca1aU), bswap_32big(0x8a07f9b6U), + bswap_32big(0xcfcf54e5U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000020U); + + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x000037dfU); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000030U); + r_rsip_func424(); + + WR1_PROG(REG_1600H, 0x000013feU); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x1ae211e9U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xb06bcb48U), bswap_32big(0x6f20a511U), bswap_32big(0xd0e7d8d6U), + bswap_32big(0x38400df5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x88bf30e0U), bswap_32big(0xc671274eU), bswap_32big(0x065d7fd0U), + bswap_32big(0x93801418U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xae374bddU), bswap_32big(0x858abf78U), bswap_32big(0x34d80af8U), + bswap_32big(0x383372a7U)); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x8190001fU); + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xa84e762aU), bswap_32big(0x4789ec01U), bswap_32big(0xe3db4667U), + bswap_32big(0x26ee98fdU)); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x3dc48dddU), bswap_32big(0xfaeb3ef8U), bswap_32big(0x62010ca8U), + bswap_32big(0xce824b86U)); + WR1_PROG(REG_1824H, 0x080000a5U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x8c5aa4a4U), bswap_32big(0xca881903U), bswap_32big(0x97250029U), + bswap_32big(0xe1c9453eU)); + WR1_PROG(REG_1824H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0a028045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2u.c new file mode 100644 index 0000000000..628508b423 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pc2u.c @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_pc2u (const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT) +{ + r_rsip_func100(bswap_32big(0xf47101f4U), + bswap_32big(0x0ff7ba4fU), + bswap_32big(0xefcd3648U), + bswap_32big(0x83117d31U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + + r_rsip_func220(InData_Text, MAX_CNT, OutData_Text); + + r_rsip_func101(bswap_32big(0x9e894a56U), + bswap_32big(0x31fcbe81U), + bswap_32big(0xab8a8887U), + bswap_32big(0x40634befU)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe1.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe1.c new file mode 100644 index 0000000000..40a4d95744 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe1.c @@ -0,0 +1,982 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe1 (const uint32_t InData_Sel_KeyType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + uint32_t iTemp = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00e10001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800101e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Sel_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a9e0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xe5f859edU), + bswap_32big(0x53931fd1U), + bswap_32big(0x637e9996U), + bswap_32big(0xd1d925beU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x16dedb43U), bswap_32big(0x20dd646eU), bswap_32big(0x00a1a904U), + bswap_32big(0x958fcf49U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x3420a9e0U); + WR1_PROG(REG_1600H, 0x00000009U); + WR1_PROG(REG_1600H, 0x2000b5e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1600H, 0x3000a9e0U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x3000a9e0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x010f6caaU); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x01f6c222U); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x013a8e02U); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x3000a9e0U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x010f6caaU); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x01f6c222U); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x013a8e02U); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x00000080U); + + r_rsip_func100(bswap_32big(0x9def13f0U), bswap_32big(0x5e237cd1U), bswap_32big(0x98d1e5eeU), + bswap_32big(0xa77d0c11U)); + WR1_PROG(REG_1608H, 0x81010200U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncCertificateInfo[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e101U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb72caf76U), bswap_32big(0x1c2ab585U), bswap_32big(0x543b28b5U), + bswap_32big(0x6f1ffac4U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034eeU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e101U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc9540137U), bswap_32big(0xd995ff31U), bswap_32big(0xb0a7cf4eU), + bswap_32big(0xc2e287a6U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x00000800U); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncCertificateInfo[1 + iLoop]); + + WR1_PROG(REG_1608H, 0x80840000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0xe6724a0dU), bswap_32big(0x45c62eb2U), bswap_32big(0x2c607da4U), + bswap_32big(0x92de6debU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000a05U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncCertificateInfo[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xbf71ef6cU), bswap_32big(0xff5c0fdbU), bswap_32big(0xc76f6c8bU), + bswap_32big(0x4a4ebcfcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xab87a1a5U), bswap_32big(0xf5e9b4b2U), bswap_32big(0x4265aa06U), + bswap_32big(0x0db6f774U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x436c46d0U), bswap_32big(0x2232724dU), bswap_32big(0xc21ccbedU), + bswap_32big(0x98124919U)); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800102c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CertificateLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x800402e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CertificatePubKey[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CertificatePubKey[1]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CertificatePubKey[2]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CertificatePubKey[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x00007c0fU); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x00000016U); + + r_rsip_func101(bswap_32big(0xda4b6533U), + bswap_32big(0x1c025110U), + bswap_32big(0x71e2cbd4U), + bswap_32big(0x2c58a25cU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_2004H, 0x000000a0U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x0000002fU); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000002fU); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000018U); + + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x00000018U); + + r_rsip_func101(bswap_32big(0xda5e9b43U), + bswap_32big(0x4e68d3b0U), + bswap_32big(0x057fdaf4U), + bswap_32big(0xcc9075e4U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000041U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000041U); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x00000024U); + + r_rsip_func101(bswap_32big(0x4ed62bbbU), + bswap_32big(0x688da3d5U), + bswap_32big(0x69411f6eU), + bswap_32big(0x8fcb96adU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x0000001cU); + + r_rsip_func101(bswap_32big(0x9fdaf948U), + bswap_32big(0xd3f58cc1U), + bswap_32big(0xf286a4fbU), + bswap_32big(0xa30a3932U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000007U) + { + WR1_PROG(REG_2004H, 0x000000a0U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x0000002fU); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000002fU); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000018U); + + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x0000001eU); + + r_rsip_func101(bswap_32big(0x958437e3U), + bswap_32big(0xa7db11e6U), + bswap_32big(0x1817c8fdU), + bswap_32big(0xb7ad1224U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000008U) + { + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x0000003fU); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x0000003fU); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1600H, 0x0000b5c0U); + WR1_PROG(REG_1600H, 0x00000020U); + + r_rsip_func101(bswap_32big(0x59a042bdU), + bswap_32big(0x88aff809U), + bswap_32big(0x834b066fU), + bswap_32big(0x65d12099U)); + } + + WR1_PROG(REG_1600H, 0x3c002b3aU); + WR1_PROG(REG_1600H, 0x1000d3e0U); + + WR1_PROG(REG_1600H, 0x00002439U); + WR1_PROG(REG_1600H, 0x0800283aU); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x3c002af8U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + + WR1_PROG(REG_1600H, 0x3c002b19U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + + WR1_PROG(REG_1600H, 0x00002417U); + WR1_PROG(REG_1600H, 0x08002818U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x3c002b56U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x210dd939U), bswap_32big(0xa6fa5d65U), bswap_32big(0xf8e493c7U), + bswap_32big(0x7ce6069dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd6b295b5U), + bswap_32big(0x3ad60ee7U), + bswap_32big(0xdbcd1aa8U), + bswap_32big(0xd614eb62U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x73486254U), + bswap_32big(0xbbf45fa9U), + bswap_32big(0xc0f6e844U), + bswap_32big(0xb505eb78U)); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00003436U); + + WR1_PROG(REG_1600H, 0x01836c01U); + WR1_PROG(REG_1600H, 0x00036c21U); + + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1408H, 0x0000500aU); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + + r_rsip_func100(bswap_32big(0xf6fb9f58U), + bswap_32big(0x27c206bdU), + bswap_32big(0x80d37382U), + bswap_32big(0x2a4bb405U)); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, S_RAM[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, S_RAM[0 + 1]); + + WR1_PROG(REG_1600H, 0x00003417U); + WR1_PROG(REG_1600H, 0x00046800U); + WR1_PROG(REG_1600H, 0x00026c00U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x000008a5U); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1444H, 0x000003c4U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Certificate[iLoop]); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x4ca9e6c5U), + bswap_32big(0xe7815412U), + bswap_32big(0xfaa581e6U), + bswap_32big(0x7bdc5bb4U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xa3a2237bU), + bswap_32big(0x0255990cU), + bswap_32big(0x5c95da1cU), + bswap_32big(0x89730260U)); + + WR1_PROG(REG_1600H, 0x38000805U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1404H, 0x10000000U); + + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x00026800U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x00003445U); + WR1_PROG(REG_1600H, 0x00026c42U); + + WR1_PROG(REG_1600H, 0x000034d6U); + WR1_PROG(REG_1600H, 0x000030c0U); + + iTemp = iLoop; + for (iLoop = iTemp; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010120U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Certificate[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (jLoop = 0U; jLoop < 4; jLoop++) + { + WR1_PROG(REG_1600H, 0x00002c20U); + + WR1_PROG(REG_1600H, 0x01886d09U); + WR1_PROG(REG_1600H, 0x00086d29U); + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c002859U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x3c002b42U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd7cd7b1bU), + bswap_32big(0xc193483eU), + bswap_32big(0xf9aa9cf8U), + bswap_32big(0xb860ae74U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x10c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x2de13bf2U), + bswap_32big(0x2301380bU), + bswap_32big(0xdeef4966U), + bswap_32big(0x6ea2cf50U)); + } + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c002857U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x3c002b02U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd35ad9b2U), + bswap_32big(0xb83f554dU), + bswap_32big(0xcd8096b0U), + bswap_32big(0x680eb5afU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x10c90005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x89cf42a5U), + bswap_32big(0x1db03debU), + bswap_32big(0x70d34219U), + bswap_32big(0x7f6514d1U)); + } + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1600H, 0x3c0028c2U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x23a8a71dU), + bswap_32big(0xa33043d8U), + bswap_32big(0x942d1c09U), + bswap_32big(0x38fc3a44U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x11490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x106a1855U), + bswap_32big(0x2c84008fU), + bswap_32big(0x2f7114bcU), + bswap_32big(0xa3aa0502U)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + + r_rsip_func101(bswap_32big(0xdd5098a9U), + bswap_32big(0xcdf89368U), + bswap_32big(0x5c8beeb2U), + bswap_32big(0x5ec4ecc9U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0xe304a236U), + bswap_32big(0xcfc87fbdU), + bswap_32big(0x1c697c4cU), + bswap_32big(0x7f2d6214U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000805U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x4b3a5963U), + bswap_32big(0xade90730U), + bswap_32big(0xf3f2200cU), + bswap_32big(0xf0f4cd82U)); + WR1_PROG(REG_1600H, 0x00003416U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x0000b440U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x00002840U); + WR1_PROG(REG_1600H, 0x00008c40U); + WR1_PROG(REG_1600H, 0x00000003U); + + WR1_PROG(REG_1608H, 0x81010040U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x00000863U); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1400H, 0x11490005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x1009000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00086c63U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0xd9c8773eU), + bswap_32big(0x715d13dcU), + bswap_32big(0xa3718a88U), + bswap_32big(0x72d67ac0U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000845U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func100(bswap_32big(0x877f9088U), + bswap_32big(0x72e44acbU), + bswap_32big(0xfe563c0dU), + bswap_32big(0xddc1d601U)); + WR1_PROG(REG_1608H, 0x81010200U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1400H, 0x03450005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003840U); + + WR1_PROG(REG_1600H, 0x08002822U); + WR1_PROG(REG_1600H, 0x2000d3e0U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x00002ca0U); + + r_rsip_func101(bswap_32big(0xaab0dd0bU), + bswap_32big(0x47b20ff5U), + bswap_32big(0x426b7c2eU), + bswap_32big(0xba5ed4cbU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000a05U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x67e4d98eU), + bswap_32big(0x61f29891U), + bswap_32big(0x212764d3U), + bswap_32big(0x5c7d3fcbU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xac65695fU), + bswap_32big(0x4744d87dU), + bswap_32big(0x312610d1U), + bswap_32big(0x0bf34fefU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x380089e0U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x9c9ae4eeU), + bswap_32big(0xe9a63f5bU), + bswap_32big(0x1635412aU), + bswap_32big(0x1f00e4f2U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + WR1_PROG(REG_1608H, 0x80a80000U); + + WR1_PROG(REG_1400H, 0x13400039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x13430109U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1400H, 0x13400039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1400H, 0x13430109U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1608H, 0x81a80000U); + WR1_PROG(REG_1400H, 0x00c900a1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xd76b2013U), + bswap_32big(0x3ff4463cU), + bswap_32big(0x336f2d0aU), + bswap_32big(0x89661fc2U)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdd63be91U), + bswap_32big(0xcfc27455U), + bswap_32big(0xdb0855b9U), + bswap_32big(0xf226fedcU)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e102U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xeb6f5947U), + bswap_32big(0x151c1644U), + bswap_32big(0x81c8cb11U), + bswap_32big(0x86206473U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034eeU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e102U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa77ef16fU), + bswap_32big(0xea9e995fU), + bswap_32big(0x91934b4aU), + bswap_32big(0x84159788U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xabe3b7a4U), + bswap_32big(0x9c77a9a4U), + bswap_32big(0xc8e6bf51U), + bswap_32big(0xbd315ed7U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x81010360U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1404H, 0x10000000U); + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1600H, 0x342028bbU); + WR1_PROG(REG_1600H, 0x2000d080U); + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x016b8e8cU), + bswap_32big(0x05e9e3e6U), + bswap_32big(0x7009f85dU), + bswap_32big(0x4f281387U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1 + iLoop]); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0xff204b58U), + bswap_32big(0x42605f17U), + bswap_32big(0x5c4fc156U), + bswap_32big(0xf2a74e8fU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x380008bbU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x2f52cb5dU), + bswap_32big(0xd4c47d2dU), + bswap_32big(0xff999268U), + bswap_32big(0xac060899U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1 + iLoop]); + + r_rsip_func100(bswap_32big(0x0503370eU), + bswap_32big(0x610cd23bU), + bswap_32big(0x30c1277dU), + bswap_32big(0xe9173370U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func102(bswap_32big(0x3a337037U), + bswap_32big(0x63115e8dU), + bswap_32big(0x3854e7acU), + bswap_32big(0xe5c72bf7U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe2.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe2.c new file mode 100644 index 0000000000..8aae5a2078 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe2.c @@ -0,0 +1,450 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe2 (const uint32_t InData_CurveType[], + const uint32_t InData_PubKeyType[], + const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_DomainParam[], + uint32_t OutData_EncSecret[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00e20001U); + WR1_PROG(REG_144CH, 0x00000000U); + + r_rsip_func100(bswap_32big(0xa841da9cU), + bswap_32big(0xb38412f4U), + bswap_32big(0x45131c51U), + bswap_32big(0x1cf94ccaU)); + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420ab40U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x2000b740U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x00000b9cU); + + r_rsip_func070(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e201U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xda96c451U), + bswap_32big(0xf08821f6U), + bswap_32big(0x7dfd9980U), + bswap_32big(0x6ba79275U)); + r_rsip_func043(); + + r_rsip_func074(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e201U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xde554be3U), + bswap_32big(0x835b52e4U), + bswap_32big(0xa5c19a65U), + bswap_32big(0x0ff5e70eU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 8U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x13200000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x63938360U), + bswap_32big(0xdf7b7f55U), + bswap_32big(0x3b1a44a4U), + bswap_32big(0x8e6efdbcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x2f393c7cU), bswap_32big(0x8c5e46b7U), bswap_32big(0xffe3e7e5U), + bswap_32big(0x50c0fe61U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000f7bU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x28acf91aU), bswap_32big(0x3d0b2c86U), bswap_32big(0x3d8d9d07U), + bswap_32big(0xe170dc69U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000007d0U); + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = 0U; iLoop < 32U; ) + { + WR1_ADDR((&(REG_00F0H))[iLoop / 4], &InData_PubKey[0 + (iLoop / 4)]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000007d0U); + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = 0U; iLoop < 32U; ) + { + WR1_ADDR((&(REG_0140H))[iLoop / 4], &InData_PubKey[8 + (iLoop / 4)]); + iLoop = iLoop + 4U; + } + + r_rsip_func101(bswap_32big(0x0760abfbU), bswap_32big(0x6d259365U), bswap_32big(0x92002191U), + bswap_32big(0x19fa1835U)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e202U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf8451663U), bswap_32big(0x0d90a12dU), bswap_32big(0xabf0cbe6U), + bswap_32big(0xe645e16bU)); + r_rsip_func043(); + + r_rsip_func075(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e202U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8e4c4dfbU), bswap_32big(0x01025140U), bswap_32big(0x55937e47U), + bswap_32big(0x1dc2433aU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[5]); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[9]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[13]); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_PubKey[17]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x74c3157dU), bswap_32big(0x2dcea5d2U), bswap_32big(0x459809c9U), + bswap_32big(0xe0c6936dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x26949b41U), + bswap_32big(0x8f92608cU), + bswap_32big(0x762fbd89U), + bswap_32big(0xe14f434aU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0xb65fc77cU), + bswap_32big(0x1d9908beU), + bswap_32big(0xaf7473a5U), + bswap_32big(0xb78d6075U)); + } + } + + r_rsip_func008(); + + r_rsip_func100(bswap_32big(0x5e180cffU), bswap_32big(0x7c600a29U), bswap_32big(0xa2e7e0d9U), + bswap_32big(0xc5bf4914U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xfd64a6a4U), bswap_32big(0x549a39d2U), bswap_32big(0xd6d1554aU), + bswap_32big(0xce100a75U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000228U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e2U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1120aea2U), bswap_32big(0x5bcb3616U), bswap_32big(0x7f221ad0U), + bswap_32big(0x2df5afbcU)); + r_rsip_func088(); + + r_rsip_func100(bswap_32big(0x271e41a4U), bswap_32big(0xca9878b3U), bswap_32big(0x989433c5U), + bswap_32big(0x26bc7f8cU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xa2087fa5U), + bswap_32big(0xd41c5b4aU), + bswap_32big(0x5febcdadU), + bswap_32big(0x7bf70f4fU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e2U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x22e02587U), + bswap_32big(0xecce12b9U), + bswap_32big(0x7e546bc9U), + bswap_32big(0x94873ae2U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e203U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x88fcce3dU), + bswap_32big(0x54172488U), + bswap_32big(0x29beac92U), + bswap_32big(0xe32e0968U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x015c5d71U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e203U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x79d167f3U), + bswap_32big(0x8a1752e6U), + bswap_32big(0x847c11d8U), + bswap_32big(0x1c158e46U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x9f24ee28U), + bswap_32big(0xd0e30f82U), + bswap_32big(0xad3713b7U), + bswap_32big(0xf389361aU)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[5]); + + r_rsip_func100(bswap_32big(0x339850beU), + bswap_32big(0x2cae0b73U), + bswap_32big(0x1f03dbfdU), + bswap_32big(0x9916c85cU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncSecret[9]); + + r_rsip_func100(bswap_32big(0x593f37c3U), + bswap_32big(0x3c220bd5U), + bswap_32big(0x140748abU), + bswap_32big(0xf426bf49U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncSecret[0]); + + r_rsip_func102(bswap_32big(0xb566a837U), + bswap_32big(0x07ccbe98U), + bswap_32big(0x23fd0bfaU), + bswap_32big(0x8cdd7025U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe3.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe3.c new file mode 100644 index 0000000000..0d9af0a696 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe3.c @@ -0,0 +1,290 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe3 (const uint32_t InData_HashType[], + const uint32_t InData_CurveType[], + const uint32_t InData_EncSecret[], + uint32_t OutData_EncMsg[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00e30001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x2000b480U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x000009ceU); + + r_rsip_func100(bswap_32big(0xf21ced96U), + bswap_32big(0x2209af79U), + bswap_32big(0x88c43d63U), + bswap_32big(0x10c70cd9U)); + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x015c5d71U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800100c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000008U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa32f8fc2U), bswap_32big(0xf350b842U), bswap_32big(0x12aa11b5U), + bswap_32big(0x44c2a6e7U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0165e3d8U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800100c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x252d1d91U), bswap_32big(0x1b08e080U), bswap_32big(0xe433575bU), + bswap_32big(0xab04af85U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30000dceU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x01ea2366U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000014U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x015d7825U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x00000080U); + + r_rsip_func101(bswap_32big(0xa77ef864U), bswap_32big(0x757f1c86U), bswap_32big(0xce660a05U), + bswap_32big(0xa1eb575eU)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0550f34eU), + bswap_32big(0xde7e5fbeU), + bswap_32big(0x01c1ea86U), + bswap_32big(0x7a2df0f5U)); + r_rsip_func407(InData_EncSecret); + + r_rsip_func100(bswap_32big(0xfb0c75c1U), + bswap_32big(0xdae08bd5U), + bswap_32big(0xc48096e1U), + bswap_32big(0x2c7c7242U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd17ba5a2U), bswap_32big(0xa727a069U), bswap_32big(0xf0bc4b3aU), + bswap_32big(0xc7eeb797U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x30008880U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x38000dceU); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x48171020U), bswap_32big(0x7e81b5edU), bswap_32big(0xc3a46c45U), + bswap_32big(0xd66485ccU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func408(); + + r_rsip_func101(bswap_32big(0x5b471199U), bswap_32big(0x4c515d7dU), bswap_32big(0xd9cbe831U), + bswap_32big(0x32072ad0U)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe6ce8517U), bswap_32big(0x04e273dcU), bswap_32big(0x2292fc76U), + bswap_32big(0x534a162eU)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4cf2df9bU), bswap_32big(0x940f65b0U), bswap_32big(0xd0e669faU), + bswap_32big(0x5852a67bU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x326fc89eU), bswap_32big(0xe057a14eU), bswap_32big(0x06940d24U), + bswap_32big(0x9b9c4bfcU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + WR1_PROG(REG_1600H, 0x000008a5U); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + r_rsip_func100(bswap_32big(0x6393feb6U), bswap_32big(0xc2f2d86dU), bswap_32big(0xfac11f66U), + bswap_32big(0x173607f8U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1608H, 0x81840005U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncMsg[1 + iLoop]); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x7c97ad8fU), bswap_32big(0x35987e49U), bswap_32big(0x2e3707edU), + bswap_32big(0x34872db6U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x380008c7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xb060c049U), bswap_32big(0xa32490c7U), bswap_32big(0x565f4714U), + bswap_32big(0xb9637c90U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncMsg[1 + iLoop]); + + r_rsip_func100(bswap_32big(0x9f1e770bU), bswap_32big(0x09bde06fU), bswap_32big(0x27db0297U), + bswap_32big(0xdff480acU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncMsg[0]); + + r_rsip_func102(bswap_32big(0xaa28efb0U), bswap_32big(0x392d3709U), bswap_32big(0xde45a6d2U), + bswap_32big(0xa37cf0e3U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe4.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe4.c new file mode 100644 index 0000000000..a968425763 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe4.c @@ -0,0 +1,366 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe4 (const uint32_t InData_HashType[], + const uint32_t InData_CurveType[], + const uint32_t InData_EncSecret[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00e40001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x2000b480U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x000009ceU); + + r_rsip_func100(bswap_32big(0x44f75652U), + bswap_32big(0x911e1e9eU), + bswap_32big(0x9aadcceaU), + bswap_32big(0x960d23a4U)); + WR1_PROG(REG_1600H, 0x00007c04U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x015c5d71U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800100c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000008U)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x01b41ce9U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010120U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000008U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3c270202U), bswap_32big(0xdfdb6142U), bswap_32big(0x3aa0cf77U), + bswap_32big(0x37e6976dU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0165e3d8U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800100c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x0199f119U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010120U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8ea958a9U), bswap_32big(0x1bc55f60U), bswap_32big(0x3fc668afU), + bswap_32big(0x131203f3U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30000dceU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x01ea2366U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000014U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x015d7825U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x01b4cab0U); + + r_rsip_func101(bswap_32big(0xd387ed79U), bswap_32big(0x1f303a0aU), bswap_32big(0x8ed72cf8U), + bswap_32big(0xff15f104U)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3fc5e441U), + bswap_32big(0xb5c7d2fcU), + bswap_32big(0x04706163U), + bswap_32big(0x7b3250a3U)); + r_rsip_func407(InData_EncSecret); + + r_rsip_func100(bswap_32big(0x931c5b02U), + bswap_32big(0xf9413ac0U), + bswap_32big(0x87526a56U), + bswap_32big(0x2a2c4c57U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x0426806bU), bswap_32big(0x87c13f95U), bswap_32big(0xc597726aU), + bswap_32big(0xe2e2252dU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x52c1c885U), bswap_32big(0x74c0903aU), bswap_32big(0xd3b54501U), + bswap_32big(0x91ddcbffU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000dceU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xe3839f24U), bswap_32big(0x71393db6U), bswap_32big(0xbf77f0f8U), + bswap_32big(0x8c5ea1beU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_2010H, 0x00000210U); + + r_rsip_func408(); + + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1608H, 0x81910005U); + WR1_PROG(REG_1400H, 0x01490045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + WR1_PROG(REG_1608H, 0x80900005U); + WR1_PROG(REG_1400H, 0x03450041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xdcd38b42U), + bswap_32big(0xaaff8b32U), + bswap_32big(0x2dfec636U), + bswap_32big(0xa4ecf99bU)); + } + else + { + r_rsip_func101(bswap_32big(0x77110b06U), + bswap_32big(0xcf64708aU), + bswap_32big(0x8c4310c7U), + bswap_32big(0xe20443a1U)); + } + } + else + { + r_rsip_func100(bswap_32big(0x6223ae3eU), bswap_32big(0xc7588bb3U), bswap_32big(0xedeab21cU), + bswap_32big(0x9f2bcfe0U)); + WR1_PROG(REG_1608H, 0x81010120U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = S_RAM[0]; iLoop < 16U; ) + { + WR1_PROG(REG_1608H, 0x80840005U); + WR1_PROG(REG_1400H, 0x03400011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func101(bswap_32big(0x22c46f05U), + bswap_32big(0xeabd6d34U), + bswap_32big(0xe06a5f4fU), + bswap_32big(0x75117038U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x380088e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xff08fe16U), bswap_32big(0xff16525cU), bswap_32big(0x36078c43U), + bswap_32big(0x09a58395U)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdcc62c05U), bswap_32big(0xee9ca8f6U), bswap_32big(0x1b41e61dU), + bswap_32big(0xb59bcc06U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6c1d6fb2U), bswap_32big(0x5f449d72U), bswap_32big(0xda70c5a5U), + bswap_32big(0x911509b0U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e8U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6b3ab4beU), bswap_32big(0xd886991aU), bswap_32big(0xc245b521U), + bswap_32big(0xc8e2b593U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x4e85b904U), bswap_32big(0xc3dfba74U), bswap_32big(0x17571f6cU), + bswap_32big(0x92d82d0aU)); + WR1_PROG(REG_1600H, 0x000008a5U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1608H, 0x81900005U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + + r_rsip_func100(bswap_32big(0x25d9af11U), bswap_32big(0x2741f014U), bswap_32big(0x441910dcU), + bswap_32big(0x2087bd83U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7008d07U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[13]); + + r_rsip_func100(bswap_32big(0xacc36738U), bswap_32big(0x12ede9c3U), bswap_32big(0x3715382fU), + bswap_32big(0xf837907aU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[17]); + + r_rsip_func100(bswap_32big(0x4ad190fdU), bswap_32big(0x0c4229d9U), bswap_32big(0xbc068aa0U), + bswap_32big(0xeb4c7341U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func102(bswap_32big(0x6e22f4d9U), bswap_32big(0x9584fd4bU), bswap_32big(0x46c38572U), + bswap_32big(0xb34526ecU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5e.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5e.c new file mode 100644 index 0000000000..4b32b4f431 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5e.c @@ -0,0 +1,331 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe5e (const uint32_t InData_EncMsg[], const uint32_t InData_EncMsgLength[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncMsgLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xb1896bd9U), + bswap_32big(0xa91c0f26U), + bswap_32big(0xaeb0a8bfU), + bswap_32big(0x94a1395aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncMsg[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e503U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc12bffadU), bswap_32big(0xefa1a2b5U), bswap_32big(0x993f55fcU), + bswap_32big(0x4613e8deU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e503U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xfbda1c8aU), bswap_32big(0x5b3a2b82U), bswap_32big(0x0231fbb2U), + bswap_32big(0x1df93cb9U)); + r_rsip_func044(); + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa258d38fU), bswap_32big(0x94adbc0dU), bswap_32big(0x74a32a5fU), + bswap_32big(0x143659e2U)); + r_rsip_func103(); + + r_rsip_func100(bswap_32big(0xab76a25eU), bswap_32big(0xc89af2bfU), bswap_32big(0xc2c770ecU), + bswap_32big(0x6a6ca66aU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c2000c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + r_rsip_func100(bswap_32big(0x3027a54bU), bswap_32big(0xb93d2d09U), bswap_32big(0x4a9c61ccU), + bswap_32big(0xd3a79ac9U)); + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + WR1_PROG(REG_1600H, 0x0000a900U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00026908U); + + WR1_PROG(REG_1600H, 0x00000929U); + + for (iLoop = 0U; iLoop < S_RAM[0] - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[1 + iLoop]); + + r_rsip_func100(bswap_32big(0x0804c50cU), bswap_32big(0x1336dbb5U), bswap_32big(0xa981bc60U), + bswap_32big(0xbe7903a7U)); + WR1_PROG(REG_1824H, 0xe7040d05U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &S_HEAP[iLoop]); + + WR1_PROG(REG_1600H, 0x00002d20U); + + r_rsip_func101(bswap_32big(0x3ac3c074U), bswap_32big(0x51e374b3U), bswap_32big(0xb929cf87U), + bswap_32big(0x26464566U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x11f013b6U), bswap_32big(0xd6573539U), bswap_32big(0xbe2315baU), + bswap_32big(0x2ceaac82U)); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1824H, 0x09140105U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &S_HEAP[iLoop]); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[OFS_ADR - 4]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x0c8ea856U), bswap_32big(0x41a67e36U), bswap_32big(0xb14d5042U), + bswap_32big(0xcadf5d71U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xd025a147U), bswap_32big(0xc746a03dU), bswap_32big(0xbefde3feU), + bswap_32big(0x758aaa01U)); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x3800a900U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xd72edd61U), bswap_32big(0x0a711c0fU), bswap_32big(0x19cb9fd1U), + bswap_32big(0xb25bddbcU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000929U); + + for (iLoop = 0U; iLoop < S_RAM[0] - 9; ) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xf7040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_HEAP[iLoop]); + WR1_PROG(REG_1400H, 0x01410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002d20U); + + r_rsip_func101(bswap_32big(0x0dab4927U), + bswap_32big(0xd02d1833U), + bswap_32big(0x518a5a85U), + bswap_32big(0x4cdc3d6aU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e8U); + WR1_PROG(REG_1600H, 0x000033e0U); + WR1_PROG(REG_1600H, 0x38000be9U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xf7040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_HEAP[iLoop]); + WR1_PROG(REG_1400H, 0x01410005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0001000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + iLoop = iLoop + 4; + + r_rsip_func101(bswap_32big(0x57043d22U), + bswap_32big(0xa0d5491aU), + bswap_32big(0x66f0e4bfU), + bswap_32big(0x168a271eU)); + } + else + { + WR1_PROG(REG_1600H, 0x00000929U); + + for (iLoop = 0U; iLoop < S_RAM[0] - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xf7040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_HEAP[iLoop]); + WR1_PROG(REG_1400H, 0x01410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002d20U); + + r_rsip_func101(bswap_32big(0x942bfd40U), + bswap_32big(0x6607090aU), + bswap_32big(0x9dd1a346U), + bswap_32big(0x128d6cb2U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5df4da92U), + bswap_32big(0x093b4a45U), + bswap_32big(0x6148ead7U), + bswap_32big(0x6a6ad0c5U)); + } + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_HEAP[iLoop]); + + WR1_PROG(REG_1824H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xfd9d845cU), bswap_32big(0xc4400d41U), bswap_32big(0x0b42e199U), + bswap_32big(0x77133469U)); + + WR1_PROG(REG_1408H, 0x00020000U); + + r_rsip_func101(bswap_32big(0x5510ea78U), bswap_32big(0x12d5fdceU), bswap_32big(0x30e3f9a1U), + bswap_32big(0xdd405250U)); + + return RSIP_RET_PASS; + } + } + else + { + r_rsip_func101(bswap_32big(0x7be6d59aU), bswap_32big(0x660960d3U), bswap_32big(0x1385e7fdU), + bswap_32big(0x1f28b2a5U)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5f.c new file mode 100644 index 0000000000..d5a98c93b8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5f.c @@ -0,0 +1,394 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe5f (const uint32_t InData_Msg[], + const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], + uint32_t OutData_KDFInfo[], + uint32_t MAX_CNT) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncMsgLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xb1896bd9U), + bswap_32big(0xa91c0f26U), + bswap_32big(0xaeb0a8bfU), + bswap_32big(0x94a1395aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncMsg[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e504U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xec72c040U), bswap_32big(0x6c2c86d4U), bswap_32big(0xbbb97d59U), + bswap_32big(0x1023c135U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e504U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xded0afd4U), bswap_32big(0xa2c280a4U), bswap_32big(0x87f4dbe4U), + bswap_32big(0x9e31e8a9U)); + r_rsip_func044(); + + WAIT_STS(REG_2030H, 0, 1); + + r_rsip_func100(bswap_32big(0x7bf28682U), bswap_32big(0xe7ae7329U), bswap_32big(0x50df69c9U), + bswap_32big(0xcd440b78U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + WR1_PROG(REG_1600H, 0x0000a900U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00026908U); + + WR1_PROG(REG_1600H, 0x3800a900U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x12a3c29aU), bswap_32big(0x810222eeU), bswap_32big(0xe789a2f0U), + bswap_32big(0x21232183U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000929U); + + for (iLoop = 0U; iLoop < S_RAM[0] - 9; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[1 + iLoop]); + + WR1_PROG(REG_1400H, 0x01420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002d20U); + + r_rsip_func101(bswap_32big(0xd2773096U), + bswap_32big(0xbaf68399U), + bswap_32big(0xe5a2c4cbU), + bswap_32big(0x17010487U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e8U); + WR1_PROG(REG_1600H, 0x000033e0U); + WR1_PROG(REG_1600H, 0x38000be9U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[1 + iLoop]); + + WR1_PROG(REG_1400H, 0x01420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + iLoop = iLoop + 4; + + r_rsip_func101(bswap_32big(0xf85ba35aU), bswap_32big(0x06a0faf9U), bswap_32big(0x6802de4fU), + bswap_32big(0x89462668U)); + } + else + { + WR1_PROG(REG_1600H, 0x00000929U); + + for (iLoop = 0U; iLoop < S_RAM[0] - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[1 + iLoop]); + + WR1_PROG(REG_1400H, 0x01420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002d20U); + + r_rsip_func101(bswap_32big(0xe150ba60U), + bswap_32big(0xb1270c63U), + bswap_32big(0x43b6791cU), + bswap_32big(0x622f74e7U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe25c20e9U), bswap_32big(0x58f11451U), bswap_32big(0xabc26729U), + bswap_32big(0xfcc3e350U)); + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[OFS_ADR - 4]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xeaa14ebfU), bswap_32big(0x24acec4cU), bswap_32big(0xa3eb01c5U), + bswap_32big(0x8333f327U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x83a8b714U), bswap_32big(0xddd80255U), bswap_32big(0x25219c4dU), + bswap_32big(0x4457c6e4U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func101(bswap_32big(0x3e8a4746U), bswap_32big(0x8e173806U), bswap_32big(0xe176550eU), + bswap_32big(0x962dd445U)); + } + } + else + { + r_rsip_func101(bswap_32big(0xbd4c386cU), bswap_32big(0xb9e0fd63U), bswap_32big(0xe405a54aU), + bswap_32big(0x3dd9a9dfU)); + } + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < MAX_CNT; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3d3c1ad9U), + bswap_32big(0xcbc4c635U), + bswap_32big(0xd3808280U), + bswap_32big(0x93334145U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e505U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7f05e88fU), + bswap_32big(0xa83b2a5aU), + bswap_32big(0x270d4df1U), + bswap_32big(0xbbe68252U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e505U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x735cc6e3U), + bswap_32big(0xf70c4002U), + bswap_32big(0x36840f1aU), + bswap_32big(0xc61fe8e5U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x000008e7U); + + r_rsip_func100(bswap_32big(0x984a8143U), + bswap_32big(0x2e1c593eU), + bswap_32big(0x4e2be20eU), + bswap_32big(0x852e3962U)); + WR1_PROG(REG_1608H, 0x810101e0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + r_rsip_func100(bswap_32big(0x6c0dcf65U), bswap_32big(0x7b61b86cU), bswap_32big(0x20df57daU), + bswap_32big(0xa3591191U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00850011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[iLoop + 1]); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0xc3f481c8U), bswap_32big(0xa5e9d05bU), bswap_32big(0x60d06abcU), + bswap_32big(0x8d829611U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x380008efU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x549ed717U), + bswap_32big(0x869ed820U), + bswap_32big(0xbe78d0ecU), + bswap_32big(0xd92fb865U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[iLoop + 1]); + + r_rsip_func100(bswap_32big(0x4e724bf8U), + bswap_32big(0xee974c4cU), + bswap_32big(0x98d4dc10U), + bswap_32big(0x0be67138U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KDFInfo[0]); + + r_rsip_func102(bswap_32big(0xcd88c46fU), + bswap_32big(0x72fb7e60U), + bswap_32big(0x97072eafU), + bswap_32big(0x84477f7cU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5i.c new file mode 100644 index 0000000000..6f6d0bd0b3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5i.c @@ -0,0 +1,299 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe5i (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], + const uint32_t InData_MsgLen[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00e50001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x800200a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + r_rsip_func100(bswap_32big(0x0cbb78cdU), + bswap_32big(0x4aa20986U), + bswap_32big(0x1f395d0bU), + bswap_32big(0x9964ccc5U)); + WR1_PROG(REG_1600H, 0x3420a8c0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x2000b4c0U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x00007c06U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0xfe3ecd34U), bswap_32big(0x33737111U), bswap_32big(0xbd751474U), + bswap_32big(0x4dea6e5dU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_2004H, 0x000000a0U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x0000000cU); + + r_rsip_func101(bswap_32big(0x96614930U), bswap_32big(0x0d7e985dU), bswap_32big(0xc165abc0U), + bswap_32big(0x88546956U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_2004H, 0x000000b0U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func101(bswap_32big(0xe4e8284dU), bswap_32big(0xe0eb7cf5U), bswap_32big(0xb2c9e2d9U), + bswap_32big(0xcf184edaU)); + } + + WR1_PROG(REG_2008H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x6c3b9d72U), + bswap_32big(0xc33928c6U), + bswap_32big(0xde2c9bceU), + bswap_32big(0x04c3e575U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x300030c0U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001bU); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x0000000cU); + + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00000080U); + r_rsip_func101(bswap_32big(0x91825c5aU), bswap_32big(0x6ce3a2b5U), bswap_32big(0xe4f579aaU), + bswap_32big(0x1ad7037fU)); + } + else + { + WR1_PROG(REG_1600H, 0x300030c0U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x01b41ce9U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0199f119U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x01b4cab0U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00000080U); + r_rsip_func101(bswap_32big(0x91927292U), bswap_32big(0x3c1a7908U), bswap_32big(0x33c017d8U), + bswap_32big(0x263aa7a1U)); + } + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7aac6cefU), + bswap_32big(0xd2d33543U), + bswap_32big(0x7a29cc7eU), + bswap_32big(0x95eaea5aU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e5U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5ba5844cU), + bswap_32big(0x721d7f04U), + bswap_32big(0x1d57dac6U), + bswap_32big(0x0c2df8b8U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x710840adU), + bswap_32big(0xeacfebffU), + bswap_32big(0x84b86d05U), + bswap_32big(0x2e05a482U)); + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x00000929U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + WR1_PROG(REG_1400H, 0x01420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a520U); + WR1_PROG(REG_1600H, 0x00000004U); + r_rsip_func101(bswap_32big(0xe592ddabU), bswap_32big(0x88eb6311U), bswap_32big(0x5fa8d0a0U), + bswap_32big(0x09fd2a62U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0xabe6dfcdU), + bswap_32big(0xf5ac1900U), + bswap_32big(0x15a859dbU), + bswap_32big(0x3186e75dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe2c3950dU), bswap_32big(0xc8b2db48U), bswap_32big(0x0a9a1ba1U), + bswap_32big(0x56287b76U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000080U); + + WR1_PROG(REG_200CH, 0x00000001U); + + WAIT_STS(REG_2030H, 8, 0); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000000U); + + WR1_PROG(REG_200CH, 0x00000100U); + + r_rsip_func101(bswap_32big(0x2c7c2ac4U), bswap_32big(0x7f4b33dfU), bswap_32big(0xcb61ad34U), + bswap_32big(0xae0c057cU)); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_MsgLen[1]); + + WR1_PROG(REG_200CH, 0x00000001U); + + r_rsip_func101(bswap_32big(0xc9b6e2c3U), bswap_32big(0x31d41c34U), bswap_32big(0x22f8cb2fU), + bswap_32big(0x16f0834bU)); + } + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5r.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5r.c new file mode 100644 index 0000000000..904b1ed22a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5r.c @@ -0,0 +1,281 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe5r (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], + const uint32_t InData_State[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00e50001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x800200a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + r_rsip_func100(bswap_32big(0x0cbb78cdU), + bswap_32big(0x4aa20986U), + bswap_32big(0x1f395d0bU), + bswap_32big(0x9964ccc5U)); + WR1_PROG(REG_1600H, 0x3420a8c0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x2000b4c0U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x00007c06U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_2004H, 0x00001050U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x00000008U); + + r_rsip_func101(bswap_32big(0x89854a1bU), bswap_32big(0xd04bf489U), bswap_32big(0x23ccfa80U), + bswap_32big(0x857432a6U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_2004H, 0x000010a0U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x0000000cU); + + r_rsip_func101(bswap_32big(0xa64a6421U), bswap_32big(0xa9dcbe9dU), bswap_32big(0xf3322753U), + bswap_32big(0xd399663aU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_2004H, 0x000010b0U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x00000010U); + + r_rsip_func101(bswap_32big(0xd45f974aU), bswap_32big(0x66cbeca0U), bswap_32big(0xf75b9c3fU), + bswap_32big(0x4476bb9aU)); + } + + WR1_PROG(REG_2008H, 0x00000003U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x9c13dff9U), + bswap_32big(0xe0b2faadU), + bswap_32big(0x5cde3eb5U), + bswap_32big(0xa189e097U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x300030c0U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0000001bU); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000008U); + + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x0000000cU); + + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00000080U); + r_rsip_func101(bswap_32big(0x222a0b9aU), bswap_32big(0xe324feaaU), bswap_32big(0x30a2a070U), + bswap_32big(0x3d362e21U)); + } + else + { + WR1_PROG(REG_1600H, 0x300030c0U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x01b41ce9U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x0199f119U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1600H, 0x01b4cab0U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x00000080U); + r_rsip_func101(bswap_32big(0x5f88ea82U), bswap_32big(0xa3ed2f14U), bswap_32big(0x8255cf9bU), + bswap_32big(0x4f27e946U)); + } + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcec7b850U), + bswap_32big(0x709c9182U), + bswap_32big(0x21f1a1a8U), + bswap_32big(0x20838db3U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e5U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4389585eU), + bswap_32big(0xbd0f1b8cU), + bswap_32big(0x97d773c4U), + bswap_32big(0x42246fbcU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xa39fd439U), + bswap_32big(0x68871382U), + bswap_32big(0xca8af331U), + bswap_32big(0x5d89f6b0U)); + WR1_PROG(REG_1608H, 0x81010100U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x00000929U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + WR1_PROG(REG_1400H, 0x01420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a520U); + WR1_PROG(REG_1600H, 0x00000004U); + r_rsip_func101(bswap_32big(0x2f58d9b8U), bswap_32big(0xc77bcc0eU), bswap_32big(0xcea1b11bU), + bswap_32big(0x3125e5cbU)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000909U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x84887498U), + bswap_32big(0x81cde991U), + bswap_32big(0xf9e94a91U), + bswap_32big(0x565e3767U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x98af6c21U), bswap_32big(0xeef21691U), bswap_32big(0x5aba8ebfU), + bswap_32big(0x4e04cd03U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_State[18]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_State[19]); + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2028H, InData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7b647f3dU), bswap_32big(0xb5488a44U), bswap_32big(0x808092f0U), + bswap_32big(0x81a2ae84U)); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5s.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5s.c new file mode 100644 index 0000000000..32848d0692 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5s.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe5s (uint32_t OutData_State[]) +{ + uint32_t iLoop = 0U; + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + RD1_ADDR(REG_202CH, &OutData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + RD1_ADDR(REG_2014H, &OutData_State[18]); + RD1_ADDR(REG_2010H, &OutData_State[19]); + + r_rsip_func102(bswap_32big(0xe8a321b2U), + bswap_32big(0x4de7f4ceU), + bswap_32big(0xea212ae8U), + bswap_32big(0x02414209U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5u.c new file mode 100644 index 0000000000..23b459cdb6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe5u.c @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe5u (const uint32_t InData_Msg[], uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < MAX_CNT; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + r_rsip_func101(bswap_32big(0xe967c726U), + bswap_32big(0x8fae8567U), + bswap_32big(0x3860b8e8U), + bswap_32big(0x6b4975bdU)); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe6.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe6.c new file mode 100644 index 0000000000..e3c6afdc29 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe6.c @@ -0,0 +1,499 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe6 (const uint32_t InData_HashType[], + const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00e60001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x30003080U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000020U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000000dU); + + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x01b41ce9U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000002U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000030U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000011U); + + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x0199f119U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000015U); + + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x01b4cab0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KDFInfo_Count[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x342028c5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x86fc6261U), + bswap_32big(0x73413f58U), + bswap_32big(0x024cd898U), + bswap_32big(0x9da756c8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x74346ae0U), bswap_32big(0x2823702fU), bswap_32big(0x5196d508U), + bswap_32big(0x6cd6abc2U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_OutDataLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x300030a0U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x00003547U); + + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x342028c7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x34202946U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x4be3e91fU), bswap_32big(0x3ca3b0f1U), bswap_32big(0x4ccae43cU), + bswap_32big(0xc7db144eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x09b0f5b5U), bswap_32big(0x5bb2b55dU), bswap_32big(0x61eb8d8bU), + bswap_32big(0x902b2564U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x71ac79acU), bswap_32big(0xd98054ffU), bswap_32big(0x755acf41U), + bswap_32big(0x5fa060e1U)); + WR1_PROG(REG_1608H, 0x810100a0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + r_rsip_func100(bswap_32big(0xaed15345U), bswap_32big(0xe647ff87U), bswap_32big(0xfe9d70d4U), + bswap_32big(0x159524a7U)); + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0 + 1]); + S_RAM[0 + 1] = bswap_32big(S_RAM[0 + 1]); + OFS_ADR = S_RAM[0 + 1]; + + WR1_PROG(REG_1600H, 0x00000908U); + + WR1_PROG(REG_1600H, 0x00000929U); + + WR1_PROG(REG_1600H, 0x000009ceU); + + WR1_PROG(REG_1600H, 0x000009efU); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1600H, 0x34202905U); + WR1_PROG(REG_1600H, 0x2000d1e0U); + WR1_PROG(REG_1600H, 0x00007c0fU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KDFInfo[iLoop * OFS_ADR]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e601U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2600618eU), + bswap_32big(0xfd61db2cU), + bswap_32big(0xf31ea1c0U), + bswap_32big(0x05799483U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e601U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x5d60f3faU), + bswap_32big(0x2db9487aU), + bswap_32big(0xe10967efU), + bswap_32big(0xfa6b512eU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < OFS_ADR - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KDFInfo[1 + jLoop + iLoop * OFS_ADR]); + + WR1_PROG(REG_1608H, 0x80840009U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a520U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000a440U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x60b34839U), + bswap_32big(0xf4f4d07cU), + bswap_32big(0x5dbcf28bU), + bswap_32big(0x3e5f6892U)); + jLoop = jLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e3U); + WR1_PROG(REG_1600H, 0x0000abe0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1600H, 0x38000be2U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KDFInfo[1 + jLoop + iLoop * OFS_ADR]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00002d00U); + + r_rsip_func100(bswap_32big(0x0afd354dU), + bswap_32big(0xc30bbd44U), + bswap_32big(0xf1ce9ac0U), + bswap_32big(0x1b2b7350U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000d1c0U); + r_rsip_func101(bswap_32big(0xd23de98cU), + bswap_32big(0xdc9fde27U), + bswap_32big(0x5561a79eU), + bswap_32big(0xf911f5eeU)); + } + else + { + r_rsip_func101(bswap_32big(0xbe0b111cU), + bswap_32big(0x9774077dU), + bswap_32big(0xe1b9ba3fU), + bswap_32big(0x2f1f9d4fU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x38000905U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000dceU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0xe53c68e9U), bswap_32big(0x190addaeU), bswap_32big(0x292144a6U), + bswap_32big(0x5242f435U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xb8d7f1c4U), + bswap_32big(0x471e9524U), + bswap_32big(0x2e5f6656U), + bswap_32big(0x1066d94dU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x745c3c70U), + bswap_32big(0x1988cc90U), + bswap_32big(0x7a9fbd1fU), + bswap_32big(0x6d6dec98U)); + WR1_PROG(REG_1608H, 0x810100c0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1600H, 0x0000094aU); + + WR1_PROG(REG_1600H, 0x0000b560U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1600H, 0x00002966U); + + WR1_PROG(REG_1600H, 0x00000908U); + WR1_PROG(REG_1600H, 0x00003526U); + + for (iLoop = S_RAM[0]; iLoop < 64U; iLoop++) + { + WR1_PROG(REG_1600H, 0x02003d49U); + WR1_PROG(REG_1600H, 0x00002d00U); + WR1_PROG(REG_1600H, 0x00002d20U); + r_rsip_func101(bswap_32big(0x8598ab1aU), + bswap_32big(0xa1d4fab4U), + bswap_32big(0x31fe2d86U), + bswap_32big(0x29c272dbU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3800090bU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf9f9cfd4U), + bswap_32big(0x3681b8b3U), + bswap_32big(0xe81449d0U), + bswap_32big(0x599f8951U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e602U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd7a83816U), + bswap_32big(0xc165a7bdU), + bswap_32big(0x6b34c42cU), + bswap_32big(0x33ef8033U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034f4U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e602U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9ec70516U), + bswap_32big(0x279ab210U), + bswap_32big(0x4afd0185U), + bswap_32big(0x971c06bdU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x5b824665U), + bswap_32big(0x31202ed1U), + bswap_32big(0x929e7270U), + bswap_32big(0x17a91801U)); + WR1_PROG(REG_1600H, 0x00000929U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + + WR1_PROG(REG_1608H, 0x81900009U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + + r_rsip_func100(bswap_32big(0x03e2f623U), + bswap_32big(0x9931a480U), + bswap_32big(0xdd19d07aU), + bswap_32big(0xb96ead96U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7008d07U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[13]); + + r_rsip_func100(bswap_32big(0x05855d7aU), + bswap_32big(0x59e3f930U), + bswap_32big(0xa1cc8cd3U), + bswap_32big(0xe596233bU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[17]); + + r_rsip_func100(bswap_32big(0x0c3a9da3U), + bswap_32big(0xce12cd51U), + bswap_32big(0x40140142U), + bswap_32big(0x2d298f8eU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func102(bswap_32big(0x7b06b4eeU), + bswap_32big(0xfd66a282U), + bswap_32big(0xbb25d0ffU), + bswap_32big(0xe5dd99f1U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe7.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe7.c new file mode 100644 index 0000000000..e6810a137f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pe7.c @@ -0,0 +1,1016 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pe7 (const uint32_t InData_HashType[], + const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataType[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_HMACKeyIndex[], + uint32_t OutData_KeyIndex[], + uint32_t OutData_EncIV[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00e70001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000002c7U); + WR1_PROG(REG_1608H, 0x80030080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KDFInfo_Count[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_OutDataType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x30003080U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x08000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x05555555U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000b680U); + WR1_PROG(REG_1600H, 0x04000000U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x3000a8c0U); + WR1_PROG(REG_1600H, 0x00000009U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x34202a85U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x380088c0U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x66e78dc6U), + bswap_32big(0x82f80f9cU), + bswap_32big(0xea743073U), + bswap_32big(0x06cba152U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x2f151912U), bswap_32big(0x65d514e8U), bswap_32big(0x8617efe7U), + bswap_32big(0xb7f69aa0U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xbbc82708U), bswap_32big(0xd2269029U), bswap_32big(0xc7c7e100U), + bswap_32big(0xe7b8f696U)); + WR1_PROG(REG_1600H, 0x00007c06U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf2f5a516U), bswap_32big(0x06a3b8f1U), bswap_32big(0xcb1dfdb6U), + bswap_32big(0x6c39b842U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000007U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000001fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x12bd3407U), bswap_32big(0x3cfdda92U), bswap_32big(0x568480cbU), + bswap_32big(0x41c5a77eU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc8e83836U), bswap_32big(0x5eae7d6aU), bswap_32big(0x523963bdU), + bswap_32big(0x8b39b682U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000003U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe4cf8d06U), bswap_32big(0xb76e6bcdU), bswap_32big(0x0f93404fU), + bswap_32big(0xe5bd611dU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x0199e556U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000000bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xec3e3599U), bswap_32big(0x7b92e833U), bswap_32big(0xf039b581U), + bswap_32big(0x8e41bc87U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x0000001bU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000001fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9f21502aU), bswap_32big(0x5940cf6cU), bswap_32big(0x317a571aU), + bswap_32big(0xfbde2f68U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000007U) + { + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000028U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000002fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8f124057U), bswap_32big(0xcc7e625dU), bswap_32big(0x5f49a9c8U), + bswap_32big(0x9f11f08fU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000008U) + { + WR1_PROG(REG_1600H, 0x0000b520U); + WR1_PROG(REG_1600H, 0x00000029U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800101c0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000003fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb3fa54f9U), bswap_32big(0x128fcf24U), bswap_32big(0xa9193973U), + bswap_32big(0xeac5840eU)); + } + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010100U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_OutDataLocation[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30003080U); + WR1_PROG(REG_1600H, 0x00070020U); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x0000001fU); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x0000000dU); + + WR1_PROG(REG_1600H, 0x00003685U); + WR1_PROG(REG_1600H, 0x00056e94U); + WR1_PROG(REG_1600H, 0x00003280U); + + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x30003080U); + WR1_PROG(REG_1600H, 0x00030020U); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x0000002fU); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000011U); + + WR1_PROG(REG_1600H, 0x00003685U); + WR1_PROG(REG_1600H, 0x00046e94U); + WR1_PROG(REG_1600H, 0x000036a5U); + WR1_PROG(REG_1600H, 0x00056eb4U); + WR1_PROG(REG_1600H, 0x00002695U); + WR1_PROG(REG_1600H, 0x00003280U); + + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1600H, 0x30003080U); + WR1_PROG(REG_1600H, 0x00050020U); + + WR1_PROG(REG_1600H, 0x0000b600U); + WR1_PROG(REG_1600H, 0x0000003fU); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1600H, 0x00000015U); + + WR1_PROG(REG_1600H, 0x00003685U); + WR1_PROG(REG_1600H, 0x00066e94U); + WR1_PROG(REG_1600H, 0x00003280U); + + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x00003628U); + WR1_PROG(REG_1600H, 0x0000262eU); + + WR1_PROG(REG_1600H, 0x34202a91U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x34202911U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x17ecf5d1U), bswap_32big(0x81f878a2U), bswap_32big(0x038d4301U), + bswap_32big(0x8f2051eaU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x6233df11U), bswap_32big(0x4c81567cU), bswap_32big(0x4700e274U), + bswap_32big(0x4b64a2b9U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x50061ef5U), bswap_32big(0x743fb9ebU), bswap_32big(0x1e955c91U), + bswap_32big(0xfff04a32U)); + + WR1_PROG(REG_1600H, 0x00000a73U); + + WR1_PROG(REG_1600H, 0x00000ab5U); + + WR1_PROG(REG_1600H, 0x000009efU); + + WR1_PROG(REG_1600H, 0x00000a94U); + + WR1_PROG(REG_1600H, 0x00000ad6U); + + WR1_PROG(REG_1600H, 0x00000af7U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + r_rsip_func100(bswap_32big(0x693e116bU), bswap_32big(0x67b68b94U), bswap_32big(0xf6860e15U), + bswap_32big(0x3d09544eU)); + WR1_PROG(REG_1608H, 0x810100a0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1600H, 0x34202a65U); + WR1_PROG(REG_1600H, 0x2000d2c0U); + WR1_PROG(REG_1600H, 0x00007c16U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x34202a35U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x000026b0U); + + WR1_PROG(REG_1600H, 0x34202aa8U); + WR1_PROG(REG_1600H, 0x100026f0U); + WR1_PROG(REG_1600H, 0x10002ee0U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xcc04d82fU), + bswap_32big(0xfca1088dU), + bswap_32big(0x19b61a23U), + bswap_32big(0xcd72ff27U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func101(bswap_32big(0xace5090fU), + bswap_32big(0xd63de514U), + bswap_32big(0xd79a14aaU), + bswap_32big(0x3a35994bU)); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KDFInfo[iLoop * OFS_ADR]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e701U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0992a21fU), + bswap_32big(0x06e5a9a3U), + bswap_32big(0xef1cec55U), + bswap_32big(0x142cecb4U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e701U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9c61fffbU), + bswap_32big(0x09e3315bU), + bswap_32big(0xcfd3ddfdU), + bswap_32big(0x24fcc7abU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < OFS_ADR - 5; ) + { + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KDFInfo[1 + jLoop + iLoop * OFS_ADR]); + + WR1_PROG(REG_1608H, 0x8084000fU); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a5e0U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000a440U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0xa571703aU), + bswap_32big(0x25c45bd7U), + bswap_32big(0x7bed084bU), + bswap_32big(0xaa19d7ddU)); + jLoop = jLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e3U); + WR1_PROG(REG_1600H, 0x0000abe0U); + WR1_PROG(REG_1600H, 0x00000005U); + + WR1_PROG(REG_1600H, 0x38000be2U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KDFInfo[1 + jLoop + iLoop * OFS_ADR]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x6cc70a6cU), + bswap_32big(0xf6257653U), + bswap_32big(0x5f254811U), + bswap_32big(0x51683710U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000d280U); + r_rsip_func101(bswap_32big(0x351a8e36U), + bswap_32big(0x7ae7c091U), + bswap_32big(0x8d865b3bU), + bswap_32big(0xc77621ecU)); + } + else + { + r_rsip_func101(bswap_32big(0x05209ca6U), + bswap_32big(0x1e31a528U), + bswap_32big(0x509d513bU), + bswap_32big(0x21856440U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x00002ea0U); + + WR1_PROG(REG_1600H, 0x00002e60U); + + r_rsip_func101(bswap_32big(0x0f72f0e1U), + bswap_32big(0xdf4699edU), + bswap_32big(0x39f23856U), + bswap_32big(0x5e7b7138U)); + } + + WR1_PROG(REG_1600H, 0x38000a65U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000e94U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + r_rsip_func100(bswap_32big(0xda13e26eU), bswap_32big(0xe133728eU), bswap_32big(0xaf77d4a4U), + bswap_32big(0x4db6ce65U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xd78e043cU), + bswap_32big(0x3dc1bafcU), + bswap_32big(0x8e723d8bU), + bswap_32big(0x63220465U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000e7U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdc3b6733U), + bswap_32big(0x382f721dU), + bswap_32big(0xc9407de3U), + bswap_32big(0x5f0b3e87U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e702U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2e0b0276U), + bswap_32big(0xad5fab07U), + bswap_32big(0xf3d5e64fU), + bswap_32big(0x93b1ee25U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x000034e9U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000e702U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2135551dU), + bswap_32big(0x1ea02da0U), + bswap_32big(0xd7ef2847U), + bswap_32big(0x5394ae29U)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x00002917U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x3420a8c0U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xcdadaf95U), + bswap_32big(0xd3a0e66aU), + bswap_32big(0x7b13edaaU), + bswap_32big(0xf2ca94f7U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WR1_PROG(REG_1600H, 0x00000ab5U); + + WR1_PROG(REG_1600H, 0x02003aa8U); + WR1_PROG(REG_1600H, 0x02003eafU); + + WR1_PROG(REG_1600H, 0x00002d00U); + WR1_PROG(REG_1600H, 0x00002de0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38000cc6U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x7fa36711U), + bswap_32big(0x6a700b27U), + bswap_32big(0xea1b607cU), + bswap_32big(0x7ddb8d2dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x44053fd0U), + bswap_32big(0x1a0e3326U), + bswap_32big(0xe2ed1fd7U), + bswap_32big(0xabd3cbfbU)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7009d05U); + + WR1_PROG(REG_1608H, 0x8184000fU); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + + r_rsip_func100(bswap_32big(0xcdcc2e2eU), + bswap_32big(0x6a772b76U), + bswap_32big(0x44bdff0eU), + bswap_32big(0x76dff7feU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + + r_rsip_func101(bswap_32big(0x1bc30a38U), + bswap_32big(0x93df629bU), + bswap_32big(0x557aa8cdU), + bswap_32big(0xbb007b11U)); + } + else + { + r_rsip_func100(bswap_32big(0x864f4d31U), + bswap_32big(0xc126923bU), + bswap_32big(0xb1917342U), + bswap_32big(0xb6a08bb0U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + + WR1_PROG(REG_1608H, 0x8188000fU); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + + r_rsip_func100(bswap_32big(0x42246865U), + bswap_32big(0x2b683870U), + bswap_32big(0x9e1aff84U), + bswap_32big(0x52fc3ab5U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + r_rsip_func101(bswap_32big(0xa03af004U), + bswap_32big(0xe69b5053U), + bswap_32big(0x7a3c7f56U), + bswap_32big(0x13733d7cU)); + } + + r_rsip_func100(bswap_32big(0xbfac564aU), + bswap_32big(0x479f3edaU), + bswap_32big(0xf4bf26c8U), + bswap_32big(0xbf659d4fU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + r_rsip_func102(bswap_32big(0x104da134U), + bswap_32big(0x22eaaa9fU), + bswap_32big(0x7e331779U), + bswap_32big(0xd6b28d59U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + else + { + WR1_PROG(REG_1600H, 0x3420a8c0U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xccfd197aU), + bswap_32big(0x5f232ab6U), + bswap_32big(0xfe915969U), + bswap_32big(0xa69328d8U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + for (iLoop = 0U; iLoop < 64U; iLoop++) + { + WR1_PROG(REG_1600H, 0x00000ab5U); + + WR1_PROG(REG_1600H, 0x02003aa8U); + WR1_PROG(REG_1600H, 0x02003eafU); + + WR1_PROG(REG_1600H, 0x00002d00U); + WR1_PROG(REG_1600H, 0x00002de0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x000008e7U); + + r_rsip_func100(bswap_32big(0x79ae61a0U), + bswap_32big(0x1608da44U), + bswap_32big(0x0549ac71U), + bswap_32big(0xf737a3c3U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00002dc0U); + WR1_PROG(REG_1600H, 0x000269ceU); + + WR1_PROG(REG_1608H, 0x810101c0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; ) + { + r_rsip_func100(bswap_32big(0xb95fec6bU), + bswap_32big(0xcd02edb3U), + bswap_32big(0x08a72052U), + bswap_32big(0xead94f63U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1608H, 0x8184000fU); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_HMACKeyIndex[iLoop + 1]); + + WR1_PROG(REG_1600H, 0x0000a5e0U); + WR1_PROG(REG_1600H, 0x00000010U); + + WR1_PROG(REG_1600H, 0x0000a4e0U); + WR1_PROG(REG_1600H, 0x00000004U); + + r_rsip_func101(bswap_32big(0x584cbaa9U), + bswap_32big(0x4100b76fU), + bswap_32big(0x25422872U), + bswap_32big(0x8fdedb23U)); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x380009c7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xc1f4458dU), + bswap_32big(0xc6ed5e97U), + bswap_32big(0x99814f08U), + bswap_32big(0xd2bbb6acU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_HMACKeyIndex[iLoop + 1]); + + r_rsip_func100(bswap_32big(0xe2576ba7U), + bswap_32big(0x024d360fU), + bswap_32big(0x1de5cf02U), + bswap_32big(0xbe08c4d2U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_HMACKeyIndex[0]); + + r_rsip_func102(bswap_32big(0x5e1bac4aU), + bswap_32big(0x09f27b17U), + bswap_32big(0xc35619beU), + bswap_32big(0x1f53ac69U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + else + { + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x00000ab5U); + + WR1_PROG(REG_1600H, 0x02003aa8U); + WR1_PROG(REG_1600H, 0x02003eafU); + + WR1_PROG(REG_1600H, 0x00002d00U); + WR1_PROG(REG_1600H, 0x00002de0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b5e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x380088c0U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0xc6903c6bU), + bswap_32big(0x21f6649bU), + bswap_32big(0x6ff1fb50U), + bswap_32big(0x935ca698U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1A24H, 0x08000105U); + WR1_PROG(REG_1608H, 0x8184000fU); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x07d58005U), + bswap_32big(0xa6d5047dU), + bswap_32big(0xa47b7ac7U), + bswap_32big(0xfc6f30b8U)); + } + else + { + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020080U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x380088c0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + r_rsip_func100(bswap_32big(0x8d6174c4U), + bswap_32big(0x662a3f1eU), + bswap_32big(0xe8a69f4cU), + bswap_32big(0x0f408ceeU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000394fU); + + WR1_PROG(REG_1600H, 0x00003564U); + WR1_PROG(REG_1600H, 0x00003585U); + + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1600H, 0x00000001U); + + r_rsip_func101(bswap_32big(0xf2d48b40U), bswap_32big(0x28b9ddbcU), + bswap_32big(0xdca6df5eU), bswap_32big(0xfe98daeeU)); + } + else + { + WR1_PROG(REG_1A24H, 0x08000105U); + WR1_PROG(REG_1608H, 0x8183000fU); + WR1_PROG(REG_1400H, 0x0089000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00800005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000964U); + WR1_PROG(REG_1600H, 0x00000985U); + + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1600H, 0x00000001U); + + r_rsip_func101(bswap_32big(0x67366776U), bswap_32big(0xfc5de326U), + bswap_32big(0x93ceaed1U), bswap_32big(0xa99d8678U)); + } + } + + r_rsip_func100(bswap_32big(0x2fe01943U), + bswap_32big(0x678b398fU), + bswap_32big(0x55180509U), + bswap_32big(0xb177a085U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7009d05U); + + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncIV[1]); + + r_rsip_func100(bswap_32big(0x515aac5fU), + bswap_32big(0x5176d607U), + bswap_32big(0xd5aee535U), + bswap_32big(0x97d45531U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncIV[5]); + + r_rsip_func100(bswap_32big(0x541431d4U), + bswap_32big(0xf3518144U), + bswap_32big(0x15642c73U), + bswap_32big(0xf072531dU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncIV[0]); + + r_rsip_func102(bswap_32big(0xdc55094cU), + bswap_32big(0x1ea32b4eU), + bswap_32big(0x2e3c8351U), + bswap_32big(0x9ce89533U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peef.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peef.c new file mode 100644 index 0000000000..29094af996 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peef.c @@ -0,0 +1,129 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_peef (uint32_t OutData_EncCertificateInfo[]) +{ + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000eefU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x1cd37b16U), + bswap_32big(0x79b1beb3U), + bswap_32big(0x387388f7U), + bswap_32big(0x52ed2c47U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ee02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4c3dd6ccU), + bswap_32big(0xa86d749dU), + bswap_32big(0xf233ee19U), + bswap_32big(0xbc017d62U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x010f6caaU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ee02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x102e4f3eU), + bswap_32big(0x3252d21bU), + bswap_32big(0xc487f5b4U), + bswap_32big(0xced32d82U)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x00000884U); + + r_rsip_func100(bswap_32big(0xe7428a00U), + bswap_32big(0x1e756033U), + bswap_32big(0x3b4f4374U), + bswap_32big(0xe6c30d65U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + + WR1_PROG(REG_1608H, 0x81880004U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[5]); + + r_rsip_func100(bswap_32big(0x58bf62c0U), + bswap_32big(0x7ba1c02eU), + bswap_32big(0x54b31bfcU), + bswap_32big(0xe4949015U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_EncCertificateInfo[9]); + + r_rsip_func100(bswap_32big(0x73a3ea16U), + bswap_32big(0xa7350895U), + bswap_32big(0x28302064U), + bswap_32big(0x0e271a19U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_EncCertificateInfo[0]); + + r_rsip_func102(bswap_32big(0x32eca69fU), + bswap_32big(0x65a6901fU), + bswap_32big(0x995a9fdaU), + bswap_32big(0x57867118U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peei.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peei.c new file mode 100644 index 0000000000..3a2360f31c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peei.c @@ -0,0 +1,240 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_peei (const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00ee0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420ab40U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x2000b740U); + WR1_PROG(REG_1600H, 0x00000001U); + + WR1_PROG(REG_1600H, 0x00000b9cU); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19600000U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1444H, 0x000007c7U); + WR1_PROG(REG_1608H, 0x8088001eU); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ee01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x6881723dU), + bswap_32big(0x5e922605U), + bswap_32big(0x654594d2U), + bswap_32big(0x80dd84f1U)); + r_rsip_func043(); + + r_rsip_func075(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ee01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x975d4441U), + bswap_32big(0x3dc40588U), + bswap_32big(0x69e740a6U), + bswap_32big(0x01acd926U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80900001U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WR1_PROG(REG_1400H, 0x03420021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + WR1_PROG(REG_1400H, 0x03420021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x76572b3eU), + bswap_32big(0x075bbbfcU), + bswap_32big(0x41fc863aU), + bswap_32big(0x674614aaU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x517e323cU), bswap_32big(0xf49aea0dU), bswap_32big(0xca6b6433U), + bswap_32big(0xb4180c01U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x8188001eU); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1608H, 0x8088001eU); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000eeU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xaa484c6bU), bswap_32big(0x9ac723ecU), bswap_32big(0x696da0a4U), + bswap_32big(0xd259590fU)); + r_rsip_func073(InData_DomainParam); + + r_rsip_func100(bswap_32big(0xcfc165e8U), bswap_32big(0x2b4d6258U), bswap_32big(0x5d798fd0U), + bswap_32big(0xd7166b79U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xf8faf438U), bswap_32big(0xd93145d3U), bswap_32big(0xdf989204U), + bswap_32big(0x3c62bc37U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1608H, 0x8188001eU); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x8088001eU); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x65df5d46U), bswap_32big(0x165b64f4U), bswap_32big(0x5f9c8edfU), + bswap_32big(0x385a15f8U)); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peff.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peff.c new file mode 100644 index 0000000000..2a4a3a91d7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_peff.c @@ -0,0 +1,514 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_peff (const uint32_t InData_Msg1[], + const uint32_t InData_Msg1Length[], + const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], + const uint32_t InData_Msg2[], + const uint32_t InData_Msg2Length[], + uint32_t OutData_KDFInfo[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000002c7U); + WR1_PROG(REG_1608H, 0x80030060U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg1Length[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncMsgLength[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg2Length[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008c60U); + WR1_PROG(REG_1600H, 0xfffffffeU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x912b85b6U), + bswap_32big(0xc9c65800U), + bswap_32big(0x0ecf516cU), + bswap_32big(0xb7d4a2c8U)); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1600H, 0x38008c80U); + WR1_PROG(REG_1600H, 0xfffffff7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func101(bswap_32big(0x0a2f296eU), bswap_32big(0xc606cf0bU), bswap_32big(0x9affb101U), + bswap_32big(0x7e1e7e36U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x38008c80U); + WR1_PROG(REG_1600H, 0xfffffff3U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func101(bswap_32big(0xbe2a64bdU), bswap_32big(0x83dc2d76U), bswap_32big(0x822e6f50U), + bswap_32big(0xb361d02bU)); + } + + r_rsip_func100(bswap_32big(0xa75ea818U), + bswap_32big(0x90e4b2c7U), + bswap_32big(0x72d98995U), + bswap_32big(0x9b71096bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x036781c8U), bswap_32big(0x9f77c096U), bswap_32big(0x24876c15U), + bswap_32big(0xc3fce0e3U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1600H, 0x00003405U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x17e6f7b5U), bswap_32big(0x2326a538U), bswap_32big(0xd1c2e2afU), + bswap_32big(0xe3ba47e2U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncMsg[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ef02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf8ad8543U), bswap_32big(0xb60379ecU), bswap_32big(0xf31ef472U), + bswap_32big(0x3f52931aU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ef02U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbf6fe5b4U), bswap_32big(0x6d602e23U), bswap_32big(0xd6043141U), + bswap_32big(0x00e9a965U)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x000038a7U); + + r_rsip_func100(bswap_32big(0x86a9c72cU), bswap_32big(0x59f68636U), bswap_32big(0x658afa86U), + bswap_32big(0x75cb3ea4U)); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[5]); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[9]); + + r_rsip_func101(bswap_32big(0x04512293U), + bswap_32big(0xd03dd040U), + bswap_32big(0xb0ffbdc5U), + bswap_32big(0x5bb5a28eU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1444H, 0x00000bc2U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[13]); + + r_rsip_func101(bswap_32big(0x7da17820U), + bswap_32big(0x3dc3c98dU), + bswap_32big(0x33620ba5U), + bswap_32big(0x8d267a3eU)); + } + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x4f6ef73aU), bswap_32big(0x7877b4bbU), bswap_32big(0xb8e03eb4U), + bswap_32big(0x3b2cec27U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00002c20U); + r_rsip_func101(bswap_32big(0x488fd84dU), + bswap_32big(0x6ab92535U), + bswap_32big(0x7c734030U), + bswap_32big(0x028b0329U)); + } + + r_rsip_func101(bswap_32big(0xacb377d6U), bswap_32big(0xf7eab2e3U), bswap_32big(0x0992b677U), + bswap_32big(0xeac7afaaU)); + } + + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x88ba8b6aU), bswap_32big(0x0c08c1e4U), bswap_32big(0x33c85669U), + bswap_32big(0x8edf50f8U)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xb21eadebU), bswap_32big(0x78879f51U), bswap_32big(0x5d3b12deU), + bswap_32big(0x30c6729cU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x7d890719U), bswap_32big(0xc5c3b34fU), bswap_32big(0x3e89f683U), + bswap_32big(0x4cd6c80bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg1[0]); + + r_rsip_func101(bswap_32big(0x501f8b00U), + bswap_32big(0x5e170e1eU), + bswap_32big(0xc13a5fd4U), + bswap_32big(0x6df67ceeU)); + } + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xe2b05523U), bswap_32big(0xcd9ac643U), bswap_32big(0x202624f6U), + bswap_32big(0x4467a339U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x3f7c9559U), + bswap_32big(0x1cb2f266U), + bswap_32big(0x1ed18246U), + bswap_32big(0x44906e2dU)); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x01430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x2df5a0d4U), + bswap_32big(0x5f54bdd2U), + bswap_32big(0x5c573239U), + bswap_32big(0xbf216d24U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x01430031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x700ec984U), + bswap_32big(0x50d7688aU), + bswap_32big(0xc52af0c3U), + bswap_32big(0x5e28323dU)); + } + + r_rsip_func101(bswap_32big(0x41819c42U), + bswap_32big(0x4fb29b8bU), + bswap_32big(0xd16b3cb0U), + bswap_32big(0x0c412750U)); + } + + r_rsip_func100(bswap_32big(0x52796222U), bswap_32big(0xfed00517U), bswap_32big(0xbad5c650U), + bswap_32big(0x48fa0f45U)); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg2Length[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x810100a0U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg2[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x00003801U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000efU)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0b2da105U), bswap_32big(0xaa38adb9U), bswap_32big(0xdfe8408aU), + bswap_32big(0x1dc7e855U)); + r_rsip_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e1U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ef03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xb7920be7U), bswap_32big(0xc312de92U), bswap_32big(0x409425a8U), + bswap_32big(0xed7f5f8bU)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ef03U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x011c06d2U), bswap_32big(0xdc4be9c6U), bswap_32big(0xadc89543U), + bswap_32big(0x6102e536U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x054b0e03U), bswap_32big(0x71cfd4c5U), bswap_32big(0xb2a0c86dU), + bswap_32big(0x87c222a7U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + r_rsip_func100(bswap_32big(0xef20b281U), + bswap_32big(0x56b0b01aU), + bswap_32big(0xf7d53e08U), + bswap_32big(0xbcb036a3U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1400H, 0x00850021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[5]); + + r_rsip_func100(bswap_32big(0xb3e26965U), + bswap_32big(0xa7b6d986U), + bswap_32big(0x9bdd98bcU), + bswap_32big(0xbb8bccf0U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[9]); + + r_rsip_func101(bswap_32big(0x08c90d6fU), + bswap_32big(0xf5d0ec43U), + bswap_32big(0x7553999bU), + bswap_32big(0x67e888beU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func100(bswap_32big(0xad1b458fU), + bswap_32big(0x43784c70U), + bswap_32big(0x7655bfc3U), + bswap_32big(0x9f05da3fU)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1400H, 0x00850031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[9]); + + r_rsip_func100(bswap_32big(0x4123d9a2U), + bswap_32big(0x19d41800U), + bswap_32big(0x6e094d6dU), + bswap_32big(0xf1da9dbaU)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KDFInfo[13]); + + r_rsip_func101(bswap_32big(0x27f4521cU), + bswap_32big(0x678099edU), + bswap_32big(0x37e88438U), + bswap_32big(0x2d4a9601U)); + } + + r_rsip_func100(bswap_32big(0x6ea82957U), bswap_32big(0x243be52dU), bswap_32big(0x0ac00f8eU), + bswap_32big(0xf231232eU)); + WR1_PROG(REG_1608H, 0x81010020U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KDFInfo[0]); + + r_rsip_func102(bswap_32big(0x37543e22U), bswap_32big(0x1c3ee44bU), bswap_32big(0x867b3852U), + bswap_32big(0xe9f5ef60U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefi.c new file mode 100644 index 0000000000..df07dc1adf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefi.c @@ -0,0 +1,90 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pefi (const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00ef0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a800U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1600H, 0x00000080U); + + r_rsip_func100(bswap_32big(0x7b182bb6U), + bswap_32big(0x87c6b37aU), + bswap_32big(0x09758de7U), + bswap_32big(0xd3862c96U)); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_2004H, 0x00000050U); + + r_rsip_func101(bswap_32big(0x106ca759U), bswap_32big(0x9ca1092bU), bswap_32big(0xd52dd3b7U), + bswap_32big(0xe93fcbe6U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_2004H, 0x000000a0U); + + r_rsip_func101(bswap_32big(0x988a59feU), bswap_32big(0x535def12U), bswap_32big(0x2d53878cU), + bswap_32big(0xe0bdcef2U)); + } + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x00003c01U); + + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_200CH, 0x00000100U); + + r_rsip_func101(bswap_32big(0x9d4ee5a3U), bswap_32big(0x2574e687U), bswap_32big(0x7eaa84f1U), + bswap_32big(0x9bc9143eU)); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_MsgLen[1]); + + r_rsip_func101(bswap_32big(0x87ecb52dU), bswap_32big(0x8ecb28a3U), bswap_32big(0x426d820aU), + bswap_32big(0xbd5801fcU)); + } + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefr.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefr.c new file mode 100644 index 0000000000..ebaaea0b26 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefr.c @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pefr (const uint32_t InData_HashType[], const uint32_t InData_State[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00ef0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a800U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1600H, 0x00000080U); + + r_rsip_func100(bswap_32big(0x7b182bb6U), + bswap_32big(0x87c6b37aU), + bswap_32big(0x09758de7U), + bswap_32big(0xd3862c96U)); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_2004H, 0x00001050U); + + r_rsip_func101(bswap_32big(0xcc361ddbU), bswap_32big(0x36bbf0d9U), bswap_32big(0xde00ab10U), + bswap_32big(0x5795df3bU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_2004H, 0x000010a0U); + + r_rsip_func101(bswap_32big(0x4f3f3ca3U), bswap_32big(0xc15a5763U), bswap_32big(0xc0347939U), + bswap_32big(0xad1c39e7U)); + } + + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_State[18]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_State[19]); + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2028H, InData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xf5beb7f7U), + bswap_32big(0xc4c3f2e5U), + bswap_32big(0x7502875bU), + bswap_32big(0xe78c8926U)); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefs.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefs.c new file mode 100644 index 0000000000..6785e3ec2c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefs.c @@ -0,0 +1,40 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pefs (uint32_t OutData_State[]) +{ + uint32_t iLoop = 0U; + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + RD1_ADDR(REG_202CH, &OutData_State[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + RD1_ADDR(REG_2014H, &OutData_State[18]); + RD1_ADDR(REG_2010H, &OutData_State[19]); + + r_rsip_func102(bswap_32big(0x08a1d13cU), + bswap_32big(0x003aace3U), + bswap_32big(0x216f09ddU), + bswap_32big(0x8ebb6116U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefu.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefu.c new file mode 100644 index 0000000000..1a8ceffb2b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pefu.c @@ -0,0 +1,370 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pefu (const uint32_t InData_Msg1[], + const uint32_t InData_Msg1Length[], + const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], + const uint32_t InData_Msg2[], + const uint32_t InData_Msg2Length[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000002c7U); + WR1_PROG(REG_1608H, 0x80030060U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg1Length[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncMsgLength[0]); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg2Length[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008c60U); + WR1_PROG(REG_1600H, 0xfffffffeU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00002423U); + WR1_PROG(REG_1600H, 0x00002424U); + WR1_PROG(REG_1600H, 0x00002425U); + + r_rsip_func100(bswap_32big(0x1c49160aU), + bswap_32big(0x7fe24e0fU), + bswap_32big(0xc384a3bdU), + bswap_32big(0x768406deU)); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1600H, 0x38008c80U); + WR1_PROG(REG_1600H, 0xfffffff7U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x38008c20U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func101(bswap_32big(0x1cef1d86U), bswap_32big(0x3fb53619U), bswap_32big(0x6d633336U), + bswap_32big(0x17338866U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1600H, 0x38008c80U); + WR1_PROG(REG_1600H, 0xfffffff3U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x38008c20U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func101(bswap_32big(0xfff41ebeU), bswap_32big(0x7693f902U), bswap_32big(0x13da4941U), + bswap_32big(0x708917a7U)); + } + + r_rsip_func100(bswap_32big(0xdf3b3537U), + bswap_32big(0xff9e4402U), + bswap_32big(0x76d5381bU), + bswap_32big(0x45e54921U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x94f24b7bU), bswap_32big(0x5adde9deU), bswap_32big(0x629a27a7U), + bswap_32big(0xf4c22bf6U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1600H, 0x00003405U); + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x17e531a9U), bswap_32big(0x4dd1b1b6U), bswap_32big(0x21bb2f5cU), + bswap_32big(0x4c74e2d6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_EncMsg[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ef01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x523d1173U), bswap_32big(0x462beca5U), bswap_32big(0xb2cfe07cU), + bswap_32big(0xc37b7158U)); + r_rsip_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x01799093U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000ef01U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4a3cb98eU), bswap_32big(0x4d794415U), bswap_32big(0xd8b528ffU), + bswap_32big(0x142012d1U)); + r_rsip_func044(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x000038a7U); + + r_rsip_func100(bswap_32big(0x17bd9c23U), bswap_32big(0x813e23d0U), bswap_32big(0x8921e85eU), + bswap_32big(0x772983c6U)); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[5]); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[9]); + + r_rsip_func101(bswap_32big(0xad13ae01U), + bswap_32big(0xe9ccdee6U), + bswap_32big(0xbcdb1f08U), + bswap_32big(0x338d143aU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1444H, 0x00000bc2U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_EncMsg[13]); + + r_rsip_func101(bswap_32big(0xb963669fU), + bswap_32big(0x41453a72U), + bswap_32big(0xe5c6220aU), + bswap_32big(0xa2758202U)); + } + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x7bc7555bU), bswap_32big(0xc2bfa16bU), bswap_32big(0x150655d5U), + bswap_32big(0x94ad17e1U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00002c20U); + r_rsip_func101(bswap_32big(0x220aae16U), + bswap_32big(0x8761fa71U), + bswap_32big(0xe0369152U), + bswap_32big(0x68c7e246U)); + } + + r_rsip_func101(bswap_32big(0x27e7d387U), bswap_32big(0x94fe36e6U), bswap_32big(0x9017d7bdU), + bswap_32big(0xbc18f312U)); + } + + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x42700e5eU), bswap_32big(0x8fb54b9bU), bswap_32big(0xd44313ecU), + bswap_32big(0x81e83bbeU)); + WR1_PROG(REG_143CH, 0x00400000U); + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x7bc54fc3U), bswap_32big(0x6240d020U), bswap_32big(0x7e292cb8U), + bswap_32big(0x5f5fb6caU)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x1a427d46U), bswap_32big(0x63db502eU), bswap_32big(0x9cadf6d2U), + bswap_32big(0x3d065d25U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg1[0]); + + r_rsip_func101(bswap_32big(0xeb3f2e4cU), + bswap_32big(0x342bb020U), + bswap_32big(0x11383c25U), + bswap_32big(0xc4b583a9U)); + } + + WR1_PROG(REG_1600H, 0x38000c84U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x92a3fdc3U), bswap_32big(0xd97d08bdU), bswap_32big(0x4ced105bU), + bswap_32big(0xa9a349c7U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0xd9753f61U), + bswap_32big(0x5a4498b5U), + bswap_32big(0x50c902fbU), + bswap_32big(0xcf683ddeU)); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x01430021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xebc76093U), + bswap_32big(0xd25821b0U), + bswap_32big(0x7b4f2340U), + bswap_32big(0x01c279dbU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x01430031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x110d28faU), + bswap_32big(0x5d2d66bcU), + bswap_32big(0x4615e1f0U), + bswap_32big(0xae1ac68eU)); + } + + r_rsip_func101(bswap_32big(0x63dd2833U), + bswap_32big(0x8d5f6f8aU), + bswap_32big(0x5fad6ca0U), + bswap_32big(0xf2ef5838U)); + } + + r_rsip_func100(bswap_32big(0xbbebbd41U), bswap_32big(0x115ea27dU), bswap_32big(0x0585a162U), + bswap_32big(0xfae7f1eeU)); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + WR1_PROG(REG_1444H, 0x00020064U); + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = 0; iLoop < (S_RAM[0] & 0x0000000fU); iLoop++) + { + WR1_PROG(REG_1420H, InData_Msg2[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (S_RAM[0] & 0x0000000fU); iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR16_ADDR(REG_1420H, &InData_Msg2[iLoop]); + iLoop = iLoop + 16U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1600H, 0x00003801U); + + r_rsip_func101(bswap_32big(0x1d50d86fU), bswap_32big(0xca4de9f8U), bswap_32big(0xadaa5f11U), + bswap_32big(0xe8524ff6U)); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf0.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf0.c new file mode 100644 index 0000000000..d7457ad076 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf0.c @@ -0,0 +1,578 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pf0 (const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00f00001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010380U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + WR1_PROG(REG_1444H, 0x000007c7U); + WR1_PROG(REG_1608H, 0x8088001eU); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000d3e0U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1600H, 0x000037beU); + WR1_PROG(REG_1600H, 0x0000a7a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000383dU); + WR1_PROG(REG_1600H, 0x38001001U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x30000f5aU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000d3e1U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x38000f9cU); + WR1_PROG(REG_1600H, 0x1000d3e1U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0xad943cc7U), + bswap_32big(0xe6faf11eU), + bswap_32big(0x75731945U), + bswap_32big(0xaec8b31eU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x3440fab9U), bswap_32big(0xb217c936U), bswap_32big(0x795ccbfbU), + bswap_32big(0x44b6f3e0U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x5fcd8054U), bswap_32big(0x2eaeb900U), bswap_32big(0x91b1ee4aU), + bswap_32big(0xd74e38a1U)); + r_rsip_func070(InData_DomainParam); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000430U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000430U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f001U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x84f434acU), bswap_32big(0x938080e5U), bswap_32big(0xe62dbce0U), + bswap_32big(0xa9ebae07U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f002U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe8640a31U), bswap_32big(0x16a3646cU), bswap_32big(0x8906c9d5U), + bswap_32big(0x75db279fU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000430U); + WR1_PROG(REG_1020H, 0x00000160U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14380000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000458U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xc717cd39U), bswap_32big(0x370fb1e7U), bswap_32big(0x21e731f0U), + bswap_32big(0x0e1ce929U)); + r_rsip_func071(InData_DomainParam); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9582e4d9U), bswap_32big(0xfca7c231U), bswap_32big(0xac8ed480U), + bswap_32big(0xaecf2821U)); + r_rsip_func088(); + + r_rsip_func100(bswap_32big(0x42e18846U), bswap_32big(0x1dcfc5b9U), bswap_32big(0x410a9ab0U), + bswap_32big(0x91e72c5aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x8884fc72U), bswap_32big(0x82cd92b1U), bswap_32big(0x0fd25f5fU), + bswap_32big(0xb215300aU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xd5125762U), bswap_32big(0x18717b28U), bswap_32big(0x5f8d167bU), + bswap_32big(0x44add58bU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xda04515fU), + bswap_32big(0x1946f207U), + bswap_32big(0x05d99e7aU), + bswap_32big(0xf2f48948U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x336ee2bfU), + bswap_32big(0x6be97e52U), + bswap_32big(0x05013765U), + bswap_32big(0x4fbb3ac7U)); + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x8188001eU); + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x8cefeb2fU), + bswap_32big(0x6bf813b3U), + bswap_32big(0xe62da24fU), + bswap_32big(0x82f7a1bcU)); + r_rsip_func043(); + + r_rsip_func074(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa803a5ffU), + bswap_32big(0x6704c1d5U), + bswap_32big(0xe152d377U), + bswap_32big(0x3fda26a9U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 8U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x284c7d1cU), + bswap_32big(0x31266d0bU), + bswap_32big(0xb846f628U), + bswap_32big(0x7d9fa82aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x12eaaabbU), + bswap_32big(0x36e0f4e4U), + bswap_32big(0x35e2998cU), + bswap_32big(0x5496f823U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xb188891eU), + bswap_32big(0xe2bbf010U), + bswap_32big(0x357aca8cU), + bswap_32big(0x4845a5ceU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe8fa1c64U), + bswap_32big(0xb61ec85bU), + bswap_32big(0x853af6f9U), + bswap_32big(0x9af14fa2U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0xb1f27de4U), + bswap_32big(0x6a2e2908U), + bswap_32big(0xe615c1b9U), + bswap_32big(0xadf8770cU)); + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + + r_rsip_func100(bswap_32big(0x4ed203a4U), + bswap_32big(0xce65a2c9U), + bswap_32big(0xad4a4f8fU), + bswap_32big(0x20cbd77cU)); + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[8]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[12]); + + r_rsip_func102(bswap_32big(0xf23a5a50U), + bswap_32big(0xfedaaef1U), + bswap_32big(0x4c4b0d63U), + bswap_32big(0x66910e7eU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf1.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf1.c new file mode 100644 index 0000000000..0b8dfae3da --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf1.c @@ -0,0 +1,268 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" +#include "r_rsip_sub_func.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pf1 (const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00f10001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010380U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + + WR1_PROG(REG_1444H, 0x000017c7U); + WR1_PROG(REG_1608H, 0x8098001eU); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Signature[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 3U; iLoop++) + { + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1600H, 0x0000d3e0U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1600H, 0x000037beU); + WR1_PROG(REG_1600H, 0x0000a7a0U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1600H, 0x0000383dU); + WR1_PROG(REG_1600H, 0x38001001U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1600H, 0x00000020U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30000f5aU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000d3e1U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x38000f9cU); + WR1_PROG(REG_1600H, 0x1000d3e1U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x32c0ec7eU), + bswap_32big(0xc5cfc4c2U), + bswap_32big(0x983ebc39U), + bswap_32big(0xbe19ea41U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x6ed9e479U), bswap_32big(0x71ac82ceU), bswap_32big(0xef3a81deU), + bswap_32big(0x07c68c49U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x8190001eU); + + WR1_PROG(REG_1404H, 0x19100000U); + r_rsip_func_sub002(0x00c90021U); + + WR1_PROG(REG_1404H, 0x19600000U); + r_rsip_func_sub002(0x00c90021U); + + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1608H, 0x8188001eU); + r_rsip_func_sub002(0x00890021U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1608H, 0x8088001eU); + r_rsip_func_sub002(0x03420021U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x43bb13fcU), bswap_32big(0x182dfc39U), bswap_32big(0x14837629U), + bswap_32big(0x70afd34dU)); + r_rsip_func043(); + + r_rsip_func075(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x05370189U), bswap_32big(0x02cb3a6cU), bswap_32big(0x560dc9a8U), + bswap_32big(0x0ae6382bU)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80900001U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + r_rsip_func_sub002(0x03420021U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + r_rsip_func_sub002(0x03420021U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + r_rsip_func_sub002(0x00820011U); + + r_rsip_func100(bswap_32big(0xb7566c0dU), bswap_32big(0x44124820U), bswap_32big(0xfb5c99e2U), + bswap_32big(0xd613fbcbU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x5833a262U), bswap_32big(0xeac3db6eU), bswap_32big(0x867651c0U), + bswap_32big(0x1fd00e06U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x170e9b9bU), bswap_32big(0xe26ae30aU), bswap_32big(0x0fd80b76U), + bswap_32big(0xd870027bU)); + r_rsip_func073(InData_DomainParam); + + r_rsip_func100(bswap_32big(0x9c73f404U), bswap_32big(0x46eabcedU), bswap_32big(0xe064ec0aU), + bswap_32big(0xcd0b8b17U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x7cf25279U), + bswap_32big(0x39473330U), + bswap_32big(0x9dc1eed4U), + bswap_32big(0x708b9f32U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x639bee41U), + bswap_32big(0x035ece36U), + bswap_32big(0x77984a33U), + bswap_32big(0xc28f2853U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf4.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf4.c new file mode 100644 index 0000000000..00b11f33b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf4.c @@ -0,0 +1,689 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pf4 (const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00f40001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010380U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3020ab80U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1600H, 0x00060020U); + WR1_PROG(REG_1600H, 0x0000b780U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x00000bffU); + + WR1_PROG(REG_1600H, 0x30000f5aU); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1600H, 0x0000d3e1U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1600H, 0x38000f9cU); + WR1_PROG(REG_1600H, 0x1000d3e1U); + WR1_PROG(REG_1600H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x6617e00fU), + bswap_32big(0x0fb8c49eU), + bswap_32big(0xe1cc6ecfU), + bswap_32big(0x3a150746U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xb2c5c516U), bswap_32big(0xcf74eae2U), bswap_32big(0x1ac38a14U), + bswap_32big(0xf5838829U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x4fc8d376U), bswap_32big(0x3234f97bU), bswap_32big(0x03936940U), + bswap_32big(0xe204a09eU)); + r_rsip_func070(InData_DomainParam); + + r_rsip_func100(bswap_32big(0xba76b48aU), bswap_32big(0xffcb8b5eU), bswap_32big(0xab7f7920U), + bswap_32big(0x1d6486d6U)); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12c80000U); + + WR1_PROG(REG_1600H, 0x00007c1cU); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f401U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x121d9228U), bswap_32big(0xb3ab30a1U), bswap_32big(0xbefc1aecU), + bswap_32big(0x42caee82U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0xa81c241eU), bswap_32big(0xb0ccc0e3U), bswap_32big(0x66f381c6U), + bswap_32big(0xee14dfe1U)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1400H, 0x00c0000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f402U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x030e7475U), bswap_32big(0x43af69dbU), bswap_32big(0x90e0f899U), + bswap_32big(0x91cd0fb0U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x867aacf0U), bswap_32big(0xef1ce7eaU), bswap_32big(0x4f422872U), + bswap_32big(0x951f706cU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func101(bswap_32big(0x1aa1bed1U), bswap_32big(0x62cd093bU), bswap_32big(0x756238baU), + bswap_32big(0x2e530390U)); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f403U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x3cafc8faU), bswap_32big(0xe3836cf7U), bswap_32big(0xc1a7138eU), + bswap_32big(0x90673b2cU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f404U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xda0b62cbU), bswap_32big(0xa5df7097U), bswap_32big(0x54555e3aU), + bswap_32big(0x470607f8U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11380000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x38f7eaaaU), bswap_32big(0xb7d43038U), bswap_32big(0xd016b84bU), + bswap_32big(0x121d4e16U)); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1404H, 0x12280000U); + WR1_PROG(REG_1608H, 0x808a0001U); + WR1_PROG(REG_1400H, 0x03430029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 10U; iLoop++) + { + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1600H, 0x20000842U); + WR1_PROG(REG_1600H, 0x10003841U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3800585eU); + WR1_PROG(REG_1600H, 0x20003460U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1600H, 0x100033c0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x14580000U); + WR1_PROG(REG_1400H, 0x00c00029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x05050009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00025U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003403U); + + WR1_PROG(REG_1600H, 0x00003060U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x05050007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x05050009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00003060U); + + r_rsip_func101(bswap_32big(0x4ab93b5bU), bswap_32big(0x9d8bb4fcU), bswap_32big(0xf4a2808dU), + bswap_32big(0x5e7762e9U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10e80000U); + WR1_PROG(REG_1400H, 0x00c00029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x9b8acc57U), bswap_32big(0x98ffda68U), bswap_32big(0x07642549U), + bswap_32big(0x974b479aU)); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0505000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0xfcda584eU), bswap_32big(0x9a5753a8U), bswap_32big(0x3c1c82cfU), + bswap_32big(0x09f97e1aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x05050009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0x31605fe6U), + bswap_32big(0xb6cc87d4U), + bswap_32big(0x5560877fU), + bswap_32big(0xa719936bU)); + } + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0505000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x05050009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1600H, 0x00003000U); + + r_rsip_func101(bswap_32big(0xffd3a8abU), bswap_32big(0xe8ef3151U), bswap_32big(0x295be620U), + bswap_32big(0xb73d897aU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x6ebb04e4U), bswap_32big(0x616b080aU), bswap_32big(0xa4559d22U), + bswap_32big(0x95548ccbU)); + r_rsip_func071(InData_DomainParam); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdbfa7d1bU), bswap_32big(0xb95a5a9eU), bswap_32big(0xb5783729U), + bswap_32big(0xc7ddaa5cU)); + r_rsip_func088(); + + r_rsip_func100(bswap_32big(0x512701b5U), bswap_32big(0xe76bc5d0U), bswap_32big(0x5af27f93U), + bswap_32big(0xb45e135dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x91afc90dU), bswap_32big(0xf08caab6U), bswap_32big(0xf7bfcf93U), + bswap_32big(0x27cf3b6dU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f405U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4e75d797U), bswap_32big(0xc97d0bb2U), bswap_32big(0x18a8e4f3U), + bswap_32big(0xa4174d71U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd0dfd48aU), bswap_32big(0x9f822fbeU), bswap_32big(0xf956a0ffU), + bswap_32big(0x19af8925U)); + r_rsip_func043(); + + r_rsip_func074(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xa252b155U), bswap_32big(0xdca02fb6U), bswap_32big(0xf3af16c7U), + bswap_32big(0x2ad3315cU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x3e14d045U), bswap_32big(0x0cf82f3eU), bswap_32big(0xfc01e8b8U), + bswap_32big(0x5f74db59U)); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x13200000U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[5]); + + r_rsip_func100(bswap_32big(0x1e2c02d0U), bswap_32big(0x6e5128cdU), bswap_32big(0x94b2c72aU), + bswap_32big(0x4a8add71U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[9]); + + r_rsip_func100(bswap_32big(0x3cb32abbU), bswap_32big(0x48517c70U), bswap_32big(0xc074a8ceU), + bswap_32big(0xe7a6df28U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f406U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x83b3de63U), bswap_32big(0x0f64b293U), bswap_32big(0xea88a295U), + bswap_32big(0x0cb2cbdaU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x7f209fdaU), bswap_32big(0x6d8eee4fU), bswap_32big(0x99c90cbbU), + bswap_32big(0x0c1f1884U)); + r_rsip_func043(); + + r_rsip_func075(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x902b3e4dU), bswap_32big(0x310844d1U), bswap_32big(0xe02ccdeeU), + bswap_32big(0x3d85fcbbU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xd68bf4faU), bswap_32big(0x1cf10efcU), bswap_32big(0x31c86effU), + bswap_32big(0x4393d99eU)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x12d00000U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[9]); + + r_rsip_func100(bswap_32big(0xb90cb549U), bswap_32big(0xa95583caU), bswap_32big(0x52b1ae93U), + bswap_32big(0x4fe2a324U)); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[13]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[17]); + + r_rsip_func100(bswap_32big(0xa4474311U), bswap_32big(0xa02f8b22U), bswap_32big(0x0df9f58cU), + bswap_32big(0xbd7ef89cU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + r_rsip_func102(bswap_32big(0x318dfa65U), bswap_32big(0xdedb0689U), bswap_32big(0x78293accU), + bswap_32big(0x6192aedfU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf5.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf5.c new file mode 100644 index 0000000000..f71af45533 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf5.c @@ -0,0 +1,544 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pf5 (const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00f50001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x3ef37318U), + bswap_32big(0x2d122113U), + bswap_32big(0xdb403830U), + bswap_32big(0xd8d6220eU)); + r_rsip_func027(InData_DomainParam); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000410U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000410U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f501U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc32a8626U), + bswap_32big(0xc6b3fd98U), + bswap_32big(0x1becfb7eU), + bswap_32big(0x3b645497U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f502U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x0bdb34b3U), + bswap_32big(0x07744e2cU), + bswap_32big(0x02c84356U), + bswap_32big(0xa1a4adadU)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f503U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcfef2c29U), + bswap_32big(0x781d91daU), + bswap_32big(0x6bdfcde3U), + bswap_32big(0x6e329512U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000410U); + WR1_PROG(REG_1020H, 0x00000160U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000448U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0xec9bcc1bU), + bswap_32big(0x5408880fU), + bswap_32big(0xeed25a5aU), + bswap_32big(0x97bf2c48U)); + r_rsip_func028(InData_DomainParam); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x2cfa0e64U), + bswap_32big(0x0554fcc1U), + bswap_32big(0xdaccf65eU), + bswap_32big(0x15a2d89dU)); + r_rsip_func089(); + + r_rsip_func100(bswap_32big(0xebd612ebU), + bswap_32big(0x3c495939U), + bswap_32big(0xee28a7c0U), + bswap_32big(0x8d54b5a6U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x30d99e8cU), bswap_32big(0xc8cdf727U), bswap_32big(0xad5d62d2U), + bswap_32big(0xf66a9da1U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xd29da73aU), bswap_32big(0xf2992113U), bswap_32big(0x8cb77152U), + bswap_32big(0xaff34196U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x6b5c3b4bU), bswap_32big(0xbf208582U), bswap_32big(0x24dc273fU), + bswap_32big(0xd05de7c1U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x59dfd870U), bswap_32big(0x9c9f4200U), bswap_32big(0x131c417bU), + bswap_32big(0xc21dddf4U)); + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00000bc2U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11300000U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MsgDgst[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd33b9a11U), bswap_32big(0x4478cc94U), bswap_32big(0xe104d378U), + bswap_32big(0xe9d5c89cU)); + r_rsip_func043(); + + r_rsip_func076(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbb5e4aa9U), bswap_32big(0x271ec5fbU), bswap_32big(0x28ad57c3U), + bswap_32big(0x5ac0b029U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x00000bc2U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x41eb651eU), bswap_32big(0xc62f40efU), bswap_32big(0x18071c33U), + bswap_32big(0xe1b1b6afU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x1709626fU), + bswap_32big(0xa4e527a1U), + bswap_32big(0xf9d2d845U), + bswap_32big(0xe7a7e284U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x06060005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xf652b323U), + bswap_32big(0xb8ce19c9U), + bswap_32big(0xc73ea39dU), + bswap_32big(0x9702e254U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x7349fdfcU), + bswap_32big(0xb1d6025eU), + bswap_32big(0xffb8d22cU), + bswap_32big(0x467d0df9U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func100(bswap_32big(0x10140491U), + bswap_32big(0xf5677872U), + bswap_32big(0x62dd4ea9U), + bswap_32big(0xa2c52141U)); + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[8]); + + r_rsip_func100(bswap_32big(0x5265c986U), + bswap_32big(0x8aef69f4U), + bswap_32big(0x04e10e93U), + bswap_32big(0x990d6caaU)); + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[12]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[16]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[20]); + + r_rsip_func102(bswap_32big(0x4ab13da4U), + bswap_32big(0xc18379dcU), + bswap_32big(0xb2c21c27U), + bswap_32big(0x45d1af2bU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf6.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf6.c new file mode 100644 index 0000000000..6a0b54a767 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf6.c @@ -0,0 +1,785 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" +#include "r_rsip_sub_func.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pf6 (const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00f60001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xbbc2583fU), + bswap_32big(0x0b77e50aU), + bswap_32big(0x47376bcbU), + bswap_32big(0xe796333bU)); + r_rsip_func043(); + + r_rsip_func077(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xe0fcd2bdU), + bswap_32big(0x5dff2296U), + bswap_32big(0xc7b73718U), + bswap_32big(0x9c0d7097U)); + r_rsip_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x40000500U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1608H, 0x80980001U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + r_rsip_func_sub002(0x03420031U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[21]); + r_rsip_func_sub002(0x03420031U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[25]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + r_rsip_func_sub002(0x00820011U); + + r_rsip_func100(bswap_32big(0xdd4d4326U), + bswap_32big(0xecc32e1bU), + bswap_32big(0x678374c8U), + bswap_32big(0xbeb6c400U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0x004ac751U), bswap_32big(0x1eb6ba0aU), bswap_32big(0xfd56ee83U), + bswap_32big(0x84dcb049U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_KEY_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000bc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x808c001fU); + for (iLoop = 0U; iLoop < 12U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + r_rsip_func100(bswap_32big(0x7b32a97eU), bswap_32big(0xe8f46b19U), bswap_32big(0x61547683U), + bswap_32big(0x3e1a957bU)); + r_rsip_func027(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19000000U); + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x00000500U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + r_rsip_func_sub002(0x00c20031U); + + WR1_PROG(REG_1404H, 0x19500000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + r_rsip_func_sub002(0x00c20031U); + + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0002dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000000c0U, 0x00000200U, 0x00000160U, 0x0606000aU); + + r_rsip_func_sub001(0x00000160U, 0x00000930U, 0x000001b0U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000930U, 0x00000200U, 0x000001b0U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000160U, 0x00000980U, 0x000001b0U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000980U, 0x00000200U, 0x000001b0U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xd0702932U), bswap_32big(0x67ebeff0U), bswap_32big(0xd9a33228U), + bswap_32big(0xf8cfc189U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xaae76fecU), bswap_32big(0xddbd1d83U), bswap_32big(0x58986dacU), + bswap_32big(0x3724e93bU)); + } + else + { + r_rsip_func100(bswap_32big(0x302f4ccfU), bswap_32big(0x369a3af5U), bswap_32big(0x959cb153U), + bswap_32big(0x4632d664U)); + + r_rsip_func_sub001(0x00000160U, 0x00000200U, 0x000001b0U, 0x0606000aU); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + r_rsip_func_sub003(0x000000c0U, 0x00000160U, 0x06060002U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1608H, 0x818c001fU); + r_rsip_func_sub002(0x00c90031U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x000000c0U, 0x00000480U, 0x06060002U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x000000c0U, 0x00000340U, 0x06060002U); + + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11300000U); + r_rsip_func_sub002(0x00c00031U); + + WR1_PROG(REG_1404H, 0x19800000U); + r_rsip_func_sub002(0x00c002d1U); + + WR1_PROG(REG_1014H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a70U, 0x06060004U); + + r_rsip_func_sub001(0x00000890U, 0x00000160U, 0x000002b8U, 0x06060009U); + + r_rsip_func_sub001(0x00000070U, 0x00000160U, 0x000002f0U, 0x06060009U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1608H, 0x818c0001U); + r_rsip_func_sub002(0x00c90031U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a00U, 0x06060002U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1608H, 0x818c001fU); + r_rsip_func_sub002(0x00c90031U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + r_rsip_func_sub003(0x00000070U, 0x00000a38U, 0x06060002U); + + r_rsip_func100(bswap_32big(0xc0401041U), bswap_32big(0x8a4ba88bU), bswap_32big(0x6d3c7918U), + bswap_32big(0x4fb8407fU)); + r_rsip_func028(InData_DomainParam); + + r_rsip_func_sub001(0x000001e0U, 0x00000160U, 0x00000af0U, 0x06060009U); + + r_rsip_func_sub001(0x00000218U, 0x00000160U, 0x00000b28U, 0x06060009U); + + r_rsip_func_sub001(0x00000a70U, 0x00000160U, 0x00000b60U, 0x06060009U); + + r_rsip_func_sub001(0x00000af0U, 0x00000a00U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000a00U, 0x00000af0U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000b28U, 0x00000a38U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000a38U, 0x00000b28U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xdc151ea5U), bswap_32big(0x190d8560U), bswap_32big(0x936bb66fU), + bswap_32big(0x3766db0aU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000b60U); + WR1_PROG(REG_1018H, 0x00000a70U); + r_rsip_func_sub003(0x00000070U, 0x00000c50U, 0x06060013U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0xf1fe4625U), + bswap_32big(0xbc007e74U), + bswap_32big(0x19fd1bfdU), + bswap_32big(0xdd83e8c3U)); + } + else + { + WR1_PROG(REG_1014H, 0x00000b60U); + r_rsip_func_sub003(0x000002f0U, 0x00000c50U, 0x06060014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x245a8d17U), + bswap_32big(0x8ae1d93fU), + bswap_32big(0x55ff9c00U), + bswap_32big(0x2dde1392U)); + } + + WR1_PROG(REG_1600H, 0x00000821U); + + WR1_PROG(REG_1404H, 0x14500000U); + WR1_PROG(REG_1608H, 0x808c0001U); + r_rsip_func_sub002(0x03430031U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1404H, 0x13100000U); + WR1_PROG(REG_1608H, 0x808c0001U); + r_rsip_func_sub002(0x03430031U); + + WR1_PROG(REG_1404H, 0x11600000U); + r_rsip_func_sub002(0x00c000f1U); + + WR1_PROG(REG_1600H, 0x00000821U); + + for (iLoop = 0U; iLoop < 12U; iLoop++) + { + WR1_PROG(REG_1600H, 0x000034a1U); + + WR1_PROG(REG_1600H, 0x00026ca5U); + + WR1_PROG(REG_1600H, 0x00003865U); + + WR1_PROG(REG_1600H, 0x0000a4a0U); + WR1_PROG(REG_1600H, 0x00000050U); + + WR1_PROG(REG_1600H, 0x00003885U); + + WR1_PROG(REG_1600H, 0x00000842U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x000008a5U); + + WR1_PROG(REG_1600H, 0x01816ca3U); + WR1_PROG(REG_1600H, 0x01816ca4U); + WR1_PROG(REG_1600H, 0x00016c63U); + WR1_PROG(REG_1600H, 0x00016c84U); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0002dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000001e0U, 0x00000160U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000250U, 0x00000160U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x78488daeU), + bswap_32big(0xa33ce35aU), + bswap_32big(0x9c7e3896U), + bswap_32big(0xcf165b32U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x000002f0U, 0x00000250U, 0x06060014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x5904743eU), + bswap_32big(0xc53b5d4aU), + bswap_32big(0x28eeaf58U), + bswap_32big(0x11663c56U)); + } + else + { + r_rsip_func101(bswap_32big(0x1eb9f769U), + bswap_32big(0xb418bd5dU), + bswap_32big(0x5dd5ea57U), + bswap_32big(0x3b5b332cU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000ca5U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + r_rsip_func100(bswap_32big(0x2d76c0acU), + bswap_32big(0x7618c9fcU), + bswap_32big(0x2d91762eU), + bswap_32big(0x85d4f3c9U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func100(bswap_32big(0x458705ccU), + bswap_32big(0xe267b315U), + bswap_32big(0xb4015c58U), + bswap_32big(0x958400bcU)); + + WR1_PROG(REG_1404H, 0x11300000U); + r_rsip_func_sub002(0x00c00031U); + + WR1_PROG(REG_1600H, 0x00007c05U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + r_rsip_func_sub001(0x00000a00U, 0x00000160U, 0x00000410U, 0x06060009U); + + r_rsip_func_sub001(0x00000a38U, 0x00000160U, 0x00000448U, 0x06060009U); + + r_rsip_func_sub001(0x00000a70U, 0x00000160U, 0x00000480U, 0x06060009U); + + r_rsip_func101(bswap_32big(0x17b5d499U), + bswap_32big(0xfac09d37U), + bswap_32big(0x19e9bfdeU), + bswap_32big(0x5952342aU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + r_rsip_func_sub001(0x00000af0U, 0x00000160U, 0x00000410U, 0x06060009U); + + r_rsip_func_sub001(0x00000b28U, 0x00000160U, 0x00000448U, 0x06060009U); + + r_rsip_func_sub001(0x00000b60U, 0x00000160U, 0x00000480U, 0x06060009U); + + r_rsip_func101(bswap_32big(0xc0042aa1U), + bswap_32big(0xdd9fb291U), + bswap_32big(0xa275e87dU), + bswap_32big(0xebec268dU)); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + r_rsip_func_sub001(0x00000be0U, 0x00000160U, 0x00000410U, 0x06060009U); + + r_rsip_func_sub001(0x00000c18U, 0x00000160U, 0x00000448U, 0x06060009U); + + r_rsip_func_sub001(0x00000c50U, 0x00000160U, 0x00000480U, 0x06060009U); + + r_rsip_func101(bswap_32big(0x307ebf99U), + bswap_32big(0xcd78573eU), + bswap_32big(0x698afb3eU), + bswap_32big(0x0ed028cfU)); + } + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0002dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x000001e0U, 0x00000160U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000250U, 0x00000160U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x6a073adaU), + bswap_32big(0x43a0cfadU), + bswap_32big(0x32c49c78U), + bswap_32big(0xf38d2e41U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func_sub001(0x00000410U, 0x00000160U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func_sub001(0x00000480U, 0x00000160U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x17fc605aU), + bswap_32big(0x28a89aabU), + bswap_32big(0x1425ac1fU), + bswap_32big(0x1fd898a5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func_sub001(0x000001e0U, 0x00000410U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000410U, 0x000001e0U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000218U, 0x00000448U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000448U, 0x00000218U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000250U, 0x00000480U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000480U, 0x00000250U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xe822ea65U), bswap_32big(0x254610d6U), + bswap_32big(0x93efde2eU), bswap_32big(0xf7f525bfU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + r_rsip_func_sub003(0x00000070U, 0x00000250U, 0x06060013U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x17bbf529U), bswap_32big(0x0c73b7caU), + bswap_32big(0x68fceefcU), bswap_32big(0xa0e4585dU)); + } + else + { + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x000002f0U, 0x00000250U, 0x06060014U); + WR1_PROG(REG_143CH, 0x00000d00U); + + r_rsip_func101(bswap_32big(0x5c601e67U), bswap_32big(0xab91835bU), + bswap_32big(0xf7500dd1U), bswap_32big(0x4c0721ccU)); + } + } + else + { + r_rsip_func101(bswap_32big(0xaea03807U), bswap_32big(0x49514dadU), + bswap_32big(0xe1045737U), bswap_32big(0xe97504a5U)); + } + } + else + { + WR1_PROG(REG_1404H, 0x11300000U); + r_rsip_func_sub002(0x00c00031U); + + r_rsip_func_sub001(0x00000410U, 0x00000160U, 0x000001e0U, 0x06060009U); + + r_rsip_func_sub001(0x00000448U, 0x00000160U, 0x00000218U, 0x06060009U); + + r_rsip_func_sub001(0x00000480U, 0x00000160U, 0x00000250U, 0x06060009U); + + r_rsip_func101(bswap_32big(0xa9feff43U), + bswap_32big(0x77d772dfU), + bswap_32big(0xd5697b9cU), + bswap_32big(0x3dd5bec1U)); + } + } + else + { + r_rsip_func101(bswap_32big(0x74f4c842U), + bswap_32big(0x6b55e0d5U), + bswap_32big(0x3ab7e5e0U), + bswap_32big(0x2e581b0fU)); + } + + WR1_PROG(REG_1600H, 0x00002c40U); + r_rsip_func101(bswap_32big(0x58661d5cU), + bswap_32big(0x307b56d8U), + bswap_32big(0x3840358bU), + bswap_32big(0x951d0d3aU)); + } + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002c20U); + + r_rsip_func101(bswap_32big(0x054d23b7U), + bswap_32big(0x1a639893U), + bswap_32big(0x52a47e89U), + bswap_32big(0x17199521U)); + } + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + r_rsip_func_sub002(0x00c0002dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000250U, 0x000002a0U, 0x000002f0U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0xd9b9f22cU), bswap_32big(0xb2a5026cU), bswap_32big(0xffba9197U), + bswap_32big(0x02c27a15U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0xa26c9c9cU), + bswap_32big(0x579ded4aU), + bswap_32big(0x13041f6eU), + bswap_32big(0xae04a268U)); + } + else + { + r_rsip_func100(bswap_32big(0x68d243dbU), + bswap_32big(0x81864761U), + bswap_32big(0xd34296afU), + bswap_32big(0xca5ba0fdU)); + + WR1_PROG(REG_1014H, 0x00000250U); + r_rsip_func_sub003(0x00000070U, 0x000002a0U, 0x06060004U); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + r_rsip_func_sub002(0x00c0002dU); + r_rsip_func_sub002(0x00c20005U); + r_rsip_func_sub002(0x0002000dU); + + r_rsip_func_sub001(0x00000070U, 0x00000160U, 0x00000110U, 0x0606000aU); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001e0U); + WR1_PROG(REG_1018H, 0x00000160U); + r_rsip_func_sub003(0x00000070U, 0x000002a0U, 0x06060002U); + + r_rsip_func_sub001(0x000002a0U, 0x00000930U, 0x000001b0U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func_sub001(0x00000930U, 0x000002a0U, 0x000001b0U, 0x0606000aU); + + WR1_PROG(REG_143CH, 0x00210000U); + + r_rsip_func100(bswap_32big(0x396ab264U), + bswap_32big(0xa4b4bcdaU), + bswap_32big(0x33643a68U), + bswap_32big(0x549ea493U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + + r_rsip_func101(bswap_32big(0x8b2bb26dU), + bswap_32big(0x5de6c6ceU), + bswap_32big(0x0fbe8043U), + bswap_32big(0x28650794U)); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1600H, 0x797935bbU); + + r_rsip_func101(bswap_32big(0x8d92baa8U), + bswap_32big(0xfbd58e93U), + bswap_32big(0xa600c8caU), + bswap_32big(0x22c2e085U)); + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0x2dcf05ffU), bswap_32big(0x91e573c9U), bswap_32big(0xc4577fc3U), + bswap_32big(0x817852c4U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xdbe846a4U), bswap_32big(0xd29e2f19U), bswap_32big(0x2f3393b8U), + bswap_32big(0x0fd59554U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + r_rsip_func102(bswap_32big(0x0c055d02U), bswap_32big(0x353d4708U), bswap_32big(0x17c65129U), + bswap_32big(0x873ebf7fU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf9.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf9.c new file mode 100644 index 0000000000..cf3daa02fe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_pf9.c @@ -0,0 +1,632 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_pf9 (const uint32_t InData_CurveType[], + const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return RSIP_RET_RESOURCE_CONFLICT; + } + + WR1_PROG(REG_1B00H, 0x00f90001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func100(bswap_32big(0xff1cb4a9U), + bswap_32big(0x3a72a3d1U), + bswap_32big(0x148e98fdU), + bswap_32big(0x258420dbU)); + r_rsip_func027(InData_DomainParam); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12b80000U); + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f901U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd5fe9314U), + bswap_32big(0x94a047e3U), + bswap_32big(0xe641d3fdU), + bswap_32big(0x116f2551U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f902U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdd32083dU), + bswap_32big(0x62c88b01U), + bswap_32big(0xcb6dae93U), + bswap_32big(0x06a15576U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f903U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd1316202U), + bswap_32big(0x78be438fU), + bswap_32big(0x93752d0fU), + bswap_32big(0xbc026a68U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f904U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xd3d50aa5U), + bswap_32big(0x45154693U), + bswap_32big(0x2bb870ebU), + bswap_32big(0x81ec6964U)); + r_rsip_func113(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11280000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x26a38baaU), + bswap_32big(0x6ab83ec9U), + bswap_32big(0x4dd0ad12U), + bswap_32big(0xdd25c61eU)); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1600H, 0x00000863U); + + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x808e0001U); + WR1_PROG(REG_1400H, 0x03430039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 14U; iLoop++) + { + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1600H, 0x20000842U); + WR1_PROG(REG_1600H, 0x10003841U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1600H, 0x0000001fU); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3800585eU); + WR1_PROG(REG_1600H, 0x20003460U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1600H, 0x100033c0U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1600H, 0x00000004U); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x14480000U); + WR1_PROG(REG_1400H, 0x00c00039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x07070009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00035U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003403U); + + WR1_PROG(REG_1600H, 0x00003060U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x07070007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x07070009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00003060U); + + r_rsip_func101(bswap_32big(0x727d92d1U), bswap_32big(0x6341c753U), bswap_32big(0x4ba8731aU), + bswap_32big(0xdcbf778fU)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10d80000U); + WR1_PROG(REG_1400H, 0x00c00039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + r_rsip_func100(bswap_32big(0x5e729a0dU), + bswap_32big(0x95a9dcfeU), + bswap_32big(0x96edb86aU), + bswap_32big(0x72bb9e88U)); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1600H, 0x00000040U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = bswap_32big(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0707000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + r_rsip_func100(bswap_32big(0x7012ccb7U), bswap_32big(0x8d630a74U), bswap_32big(0xba68cc1aU), + bswap_32big(0x7996aec5U)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x07070009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func101(bswap_32big(0xbe91ece6U), bswap_32big(0x75567f84U), bswap_32big(0x64c49cfeU), + bswap_32big(0x33a91e00U)); + } + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0707000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x07070009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1600H, 0x00003000U); + + r_rsip_func101(bswap_32big(0x1909bd64U), bswap_32big(0x70126e51U), bswap_32big(0xa4c004f8U), + bswap_32big(0x7520a026U)); + } + + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + r_rsip_func100(bswap_32big(0x958e6bc4U), + bswap_32big(0xdb6e4126U), + bswap_32big(0xc295359bU), + bswap_32big(0xfb5b92b1U)); + r_rsip_func028(InData_DomainParam); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x9ec5d94bU), + bswap_32big(0x522d9a32U), + bswap_32big(0x40b9e2a7U), + bswap_32big(0xb7336aebU)); + r_rsip_func089(); + + r_rsip_func100(bswap_32big(0xa3c3b359U), + bswap_32big(0x41849722U), + bswap_32big(0x917fe07eU), + bswap_32big(0x363f374dU)); + WR1_PROG(REG_143CH, 0x00400000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + r_rsip_func102(bswap_32big(0xe303feeaU), bswap_32big(0x0421fe89U), bswap_32big(0x0d312d05U), + bswap_32big(0x99ddada3U)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f905U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xcc169e7aU), bswap_32big(0x2d4e2a97U), bswap_32big(0x6e040cffU), + bswap_32big(0x180361b4U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xdd749240U), bswap_32big(0xb67e2bcfU), bswap_32big(0x8bd14cccU), + bswap_32big(0xb30c1609U)); + r_rsip_func043(); + + r_rsip_func076(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x000000f9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x412524d2U), bswap_32big(0xaef55453U), bswap_32big(0x352c5a90U), + bswap_32big(0x0b86b1f8U)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0xe55c29cfU), bswap_32big(0xaebb0977U), bswap_32big(0x356fa0a9U), + bswap_32big(0x87571be2U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x13100000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[9]); + + r_rsip_func100(bswap_32big(0xac63472eU), bswap_32big(0xd50ed40cU), bswap_32big(0xad0e6b30U), + bswap_32big(0x99a34fb8U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[13]); + + r_rsip_func100(bswap_32big(0x63338a5fU), bswap_32big(0xf9251a31U), bswap_32big(0x5e98a340U), + bswap_32big(0xe7192e73U)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x0000f906U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xc221b2a4U), bswap_32big(0x092a763dU), bswap_32big(0xe85a297dU), + bswap_32big(0xce9f4440U)); + r_rsip_func113(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000027U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0x4bf8303eU), bswap_32big(0x186fec56U), bswap_32big(0x328066f9U), + bswap_32big(0xb7d73264U)); + r_rsip_func043(); + + r_rsip_func077(); + + WR1_PROG(REG_1600H, 0x000034feU); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000028U)); + WR1_PROG(REG_1458H, 0x00000000U); + + r_rsip_func101(bswap_32big(0xda80c124U), bswap_32big(0xcf1c9722U), bswap_32big(0x63acc1c0U), + bswap_32big(0xe2a50a9bU)); + r_rsip_func044(); + + r_rsip_func100(bswap_32big(0x6b19d285U), bswap_32big(0x7c95c1a6U), bswap_32big(0x127178c2U), + bswap_32big(0x96c67df2U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[9]); + + r_rsip_func100(bswap_32big(0xa3935396U), bswap_32big(0x6b46fe89U), bswap_32big(0x9c0cdf7cU), + bswap_32big(0xf49096f8U)); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1404H, 0x12c00000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[13]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[17]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[21]); + + r_rsip_func100(bswap_32big(0x06ad8123U), bswap_32big(0x5cf6f22dU), bswap_32big(0x05ad5747U), + bswap_32big(0x77c01826U)); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, bswap_32big(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[25]); + + r_rsip_func100(bswap_32big(0x0acae8ceU), bswap_32big(0x72937d21U), bswap_32big(0x0baf6b18U), + bswap_32big(0xb37ef9fdU)); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + r_rsip_func102(bswap_32big(0xc6255c83U), bswap_32big(0xdfb7c330U), bswap_32big(0x459ec868U), + bswap_32big(0x878913dbU)); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return RSIP_RET_PASS; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_primitive.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_primitive.h new file mode 100644 index 0000000000..76cce3e006 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_primitive.h @@ -0,0 +1,584 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_PRIMITIVE_H +#define R_RSIP_PRIMITIVE_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_rsip_err.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define RSIP_PRV_WORD_SIZE_S_RAM (32U) +#define RSIP_PRV_WORD_SIZE_S_HEAP (940U) + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern uint32_t S_RAM[RSIP_PRV_WORD_SIZE_S_RAM]; +extern uint32_t S_HEAP[RSIP_PRV_WORD_SIZE_S_HEAP]; +extern uint32_t const * S_INST2; + +extern uint32_t const DomainParam_NIST_P192[]; +extern uint32_t const DomainParam_NIST_P224[]; +extern uint32_t const DomainParam_NIST_P256[]; +extern uint32_t const DomainParam_NIST_P384[]; +extern uint32_t const DomainParam_NIST_P521[]; +extern uint32_t const DomainParam_Ed25519[]; +extern uint32_t const DomainParam_Brainpool_256r1[]; +extern uint32_t const DomainParam_Brainpool_384r1[]; +extern uint32_t const DomainParam_Brainpool_512r1[]; +extern uint32_t const DomainParam_Koblitz_secp256k1[]; +extern uint32_t INST_DATA_SIZE; + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +void r_rsip_func008(void); +void r_rsip_func016(uint32_t ARG1); +void r_rsip_func017(uint32_t ARG1); +void r_rsip_func027(const uint32_t ARG1[]); +void r_rsip_func028(const uint32_t ARG1[]); +void r_rsip_func030(void); +void r_rsip_func031(const uint32_t ARG1[]); +void r_rsip_func040(void); +void r_rsip_func043(void); +void r_rsip_func044(void); +void r_rsip_func048(const uint32_t ARG1[]); +void r_rsip_func049(const uint32_t ARG1[]); +void r_rsip_func052(void); +void r_rsip_func053(void); +void r_rsip_func054(void); +void r_rsip_func055(void); +void r_rsip_func057(const uint32_t ARG1[], const uint32_t ARG2[], uint32_t ARG3[]); +void r_rsip_func058(const uint32_t ARG1[], uint32_t ARG2); +void r_rsip_func059(void); +void r_rsip_func061(const uint32_t ARG1, const uint32_t ARG2[]); +void r_rsip_func062(const uint32_t ARG1, uint32_t ARG2[]); +void r_rsip_func063(const uint32_t ARG1, const uint32_t ARG2[]); +void r_rsip_func065(const uint32_t ARG1, uint32_t ARG2[]); +void r_rsip_func066(void); +void r_rsip_func068(void); +void r_rsip_func070(const uint32_t ARG1[]); +void r_rsip_func071(const uint32_t ARG1[]); +void r_rsip_func073(const uint32_t ARG1[]); +void r_rsip_func074(void); +void r_rsip_func075(void); +void r_rsip_func076(void); +void r_rsip_func077(void); +void r_rsip_func078(const uint32_t ARG1[]); +void r_rsip_func079(const uint32_t ARG1[]); +void r_rsip_func081(void); +void r_rsip_func082(void); +void r_rsip_func083(const uint32_t ARG1[]); +void r_rsip_func086(const uint32_t ARG1[]); +void r_rsip_func087(const uint32_t ARG1[]); +void r_rsip_func088(void); +void r_rsip_func089(void); +void r_rsip_func090(void); +void r_rsip_func091(void); +void r_rsip_func092(void); +void r_rsip_func100(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void r_rsip_func101(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void r_rsip_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void r_rsip_func103(void); +void r_rsip_func113(void); +void r_rsip_func202(void); +void r_rsip_func214(void); +void r_rsip_func215(void); +void r_rsip_func216(void); +void r_rsip_func220(const uint32_t ARG1[], uint32_t ARG2, uint32_t ARG3[]); +void r_rsip_func302(void); +void r_rsip_func303(void); +void r_rsip_func304(void); +void r_rsip_func305(void); +void r_rsip_func310(void); +void r_rsip_func311(void); +void r_rsip_func312(void); +void r_rsip_func313(void); +void r_rsip_func314(void); +void r_rsip_func315(void); +void r_rsip_func316(void); +void r_rsip_func317(void); +void r_rsip_func318(void); +void r_rsip_func319(void); +void r_rsip_func320(void); +void r_rsip_func321(void); +void r_rsip_func322(void); +void r_rsip_func323(void); +void r_rsip_func324(void); +void r_rsip_func401(const uint32_t ARG1[]); +void r_rsip_func402(void); +void r_rsip_func403(void); +void r_rsip_func404(void); +void r_rsip_func405(void); +void r_rsip_func406(const uint32_t ARG1[]); +void r_rsip_func407(const uint32_t ARG1[]); +void r_rsip_func408(void); +void r_rsip_func420(void); +void r_rsip_func421(void); +void r_rsip_func422(const uint32_t ARG1[], uint32_t ARG2); +void r_rsip_func423(uint32_t ARG1[], uint32_t ARG2); +void r_rsip_func424(void); +void r_rsip_func501(uint32_t ARG1[], uint32_t ARG2); + +rsip_ret_t r_rsip_p47i(const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IVType[], + const uint32_t InData_IV[]); +void r_rsip_p47u(uint32_t const InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p47f(void); +rsip_ret_t r_rsip_p89i(const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void r_rsip_p89u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p89f(void); +rsip_ret_t r_rsip_p50i(const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IVType[], + const uint32_t InData_IV[]); +void r_rsip_p50u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p50f(void); + +void r_rsip_p00(void); +rsip_ret_t r_rsip_p11(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_p12(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +rsip_ret_t r_rsip_p13(const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_p1a(const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_p18(const uint32_t InData_PrivKeyIndex[], + const uint32_t InData_PubKeyIndex[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[], + uint64_t MAX_CNT); +rsip_ret_t r_rsip_p19(const uint32_t InData_KeyIndex[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[], + uint64_t MAX_CNT); +void r_rsip_p29a(const uint32_t InData_DataA[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p29f(const uint32_t InData_Text[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]); +rsip_ret_t r_rsip_p29i(const uint32_t InData_KeyIndex[], const uint32_t InData_IVType[], const uint32_t InData_IV[]); +void r_rsip_p29t(void); +void r_rsip_p29u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +void r_rsip_p32a(const uint32_t InData_DataA[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p32f(const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p32i(const uint32_t InData_KeyIndex[], const uint32_t InData_IVType[], const uint32_t InData_IV[]); +void r_rsip_p32t(void); +void r_rsip_p32u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +void r_rsip_p83a(const uint32_t InData_DataA[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p83f(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]); +rsip_ret_t r_rsip_p83i(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void r_rsip_p83t(void); +void r_rsip_p83u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +void r_rsip_p85a(const uint32_t InData_DataA[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p85f(const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataALen[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p85i(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void r_rsip_p85t(void); +void r_rsip_p85u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +void r_rsip_p34a(const uint32_t InData_DataA[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p34f(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]); +rsip_ret_t r_rsip_p34i(const uint32_t InData_KeyIndex[], const uint32_t InData_IVType[], const uint32_t InData_IV[]); +void r_rsip_p34t(void); +void r_rsip_p34u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +void r_rsip_p36a(const uint32_t InData_DataA[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p36f(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p36i(const uint32_t InData_KeyIndex[], const uint32_t InData_IVType[], const uint32_t InData_IV[]); +void r_rsip_p36t(void); +void r_rsip_p36u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p40(const uint32_t InData_LC[]); +rsip_ret_t r_rsip_p41f(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +rsip_ret_t r_rsip_p41i(const uint32_t InData_KeyIndex[]); +void r_rsip_p41u(const uint32_t InData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p87f(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +rsip_ret_t r_rsip_p87i(const uint32_t InData_KeyIndex[]); +void r_rsip_p87u(const uint32_t InData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p44f(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +rsip_ret_t r_rsip_p44i(const uint32_t InData_KeyIndex[]); +void r_rsip_p44u(const uint32_t InData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p20(uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p6f(const uint32_t InData_LC[], + const uint32_t InData_Cmd[], + const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p73i(const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]); +rsip_ret_t r_rsip_p73r(const uint32_t InData_HashType[], const uint32_t InData_State[]); +rsip_ret_t r_rsip_p73u(const uint32_t InData_Msg[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p73s(uint32_t OutData_State[]); +rsip_ret_t r_rsip_p73f(const uint32_t InData_Msg[], uint32_t MAX_CNT, uint32_t OutData_MsgDigest[]); +rsip_ret_t r_rsip_p81(void); +rsip_ret_t r_rsip_p82(void); +rsip_ret_t r_rsip_p95f(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t OutData_MAC[]); +rsip_ret_t r_rsip_p95i(const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + uint32_t Header_Len); +void r_rsip_p95u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p98f(const uint32_t InData_Text[], const uint32_t InData_MAC[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p98i(const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + uint32_t Header_Len); +void r_rsip_p98u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pa7f(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_MAC[]); +rsip_ret_t r_rsip_pa7i(const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + uint32_t Header_Len); +void r_rsip_pa7u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pb0f(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]); +rsip_ret_t r_rsip_pb0i(const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + uint32_t Header_Len); +void r_rsip_pb0u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pa1f(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_MAC[]); +rsip_ret_t r_rsip_pa1i(const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + uint32_t Header_Len); +void r_rsip_pa1u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pa4f(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]); +rsip_ret_t r_rsip_pa4i(const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + uint32_t Header_Len); +void r_rsip_pa4u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pb3f(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_pb3i(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void r_rsip_pb3u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pb6f(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_pb6i(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void r_rsip_pb6u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pb9f(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_pb9i(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void r_rsip_pb9u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pc2f(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_pc2i(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void r_rsip_pc2u(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p21(const uint32_t InData_HV[], + const uint32_t InData_IV[], + const uint32_t InData_Text[], + uint32_t OutData_DataT[], + uint32_t MAX_CNT); +rsip_ret_t r_rsip_p07(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p15(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p08(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p16(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p17(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p0a(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p0b(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p3c(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p3d(uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_p56(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p57(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p79(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p7a(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p7b(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_p7c(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +rsip_ret_t r_rsip_pf0(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_pf1(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +rsip_ret_t r_rsip_pf5(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_pf6(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +rsip_ret_t r_rsip_p7d(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_DomainParam[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_p7e(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +rsip_ret_t r_rsip_pf4(const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_pf9(const uint32_t InData_CurveType[], + const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_p7f(const uint32_t InData_DomainParam[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_p75(const uint32_t InData_KeyIndex[], + const uint32_t InData_Cmd[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_MAC[], + const uint32_t InData_length[], + const uint32_t InData_State[], + uint32_t OutData_MAC[], + uint32_t OutData_State[], + uint32_t MAX_CNT); +rsip_ret_t r_rsip_p75i(const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], + const uint32_t InData_MsgLen[], + uint32_t KEY_INDEX_SIZE); +rsip_ret_t r_rsip_p75r(const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], + const uint32_t InData_State[], + uint32_t KEY_INDEX_SIZE); +rsip_ret_t r_rsip_p75u(const uint32_t InData_Msg[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_p75s(uint32_t OutData_State[]); +rsip_ret_t r_rsip_p75f(const uint32_t InData_Cmd[], + const uint32_t InData_Msg[], + const uint32_t InData_MAC[], + const uint32_t InData_length[], + uint32_t MAX_CNT, + uint32_t OutData_MAC[]); +rsip_ret_t r_rsip_p31(const uint32_t InData_HashType[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + uint32_t OutData_MsgDigest[], + uint32_t MAX_CNT); +rsip_ret_t r_rsip_p2b(const uint32_t MAX_CNT, uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_p2c(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); +rsip_ret_t r_rsip_p2d(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); +rsip_ret_t r_rsip_p2e(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); +rsip_ret_t r_rsip_p3a(const uint32_t MAX_CNT, uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_p3b(const uint32_t MAX_CNT, uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); + +rsip_ret_t r_rsip_p8f(const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_WrappedKeyIndex[], + uint32_t OutData_Text[], + uint32_t KEY_INDEX_SIZE, + uint32_t WRAPPED_KEY_SIZE); +rsip_ret_t r_rsip_p90(const uint32_t InData_KeyType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_Text[], + uint32_t OutData_KeyIndex[], + uint32_t WRAPPED_KEY_SIZE, + uint32_t KEY_INDEX_SIZE); + +rsip_ret_t r_rsip_pe1(const uint32_t InData_Sel_KeyType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_pe2(const uint32_t InData_CurveType[], + const uint32_t InData_PubKeyType[], + const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_DomainParam[], + uint32_t OutData_EncSecret[]); +rsip_ret_t r_rsip_p4e(const uint32_t InData_CurveType[], + const uint32_t InData_PubKeyType[], + const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_DomainParam[], + uint32_t OutData_EncSecret[]); +rsip_ret_t r_rsip_p5e(const uint32_t InData_PubKeyType[], + const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_DomainParam[], + uint32_t OutData_EncSecret[]); +rsip_ret_t r_rsip_p4f(const uint32_t InData_PubKeyType[], + const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_DomainParam[], + uint32_t OutData_EncSecret[]); +rsip_ret_t r_rsip_pe3(const uint32_t InData_HashType[], + const uint32_t InData_CurveType[], + const uint32_t InData_EncSecret[], + uint32_t OutData_EncMsg[]); +rsip_ret_t r_rsip_pe4(const uint32_t InData_HashType[], + const uint32_t InData_CurveType[], + const uint32_t InData_EncSecret[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_pe5e(const uint32_t InData_EncMsg[], const uint32_t InData_EncMsgLength[]); +rsip_ret_t r_rsip_pe5f(const uint32_t InData_Msg[], + const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], + uint32_t OutData_KDFInfo[], + uint32_t MAX_CNT); +rsip_ret_t r_rsip_pe5i(const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], + const uint32_t InData_MsgLen[]); +rsip_ret_t r_rsip_pe5r(const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_HashType[], + const uint32_t InData_State[]); +rsip_ret_t r_rsip_pe5s(uint32_t OutData_State[]); +rsip_ret_t r_rsip_pe5u(const uint32_t InData_Msg[], uint32_t MAX_CNT); +rsip_ret_t r_rsip_pe6(const uint32_t InData_HashType[], + const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_pe7(const uint32_t InData_HashType[], + const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataType[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_HMACKeyIndex[], + uint32_t OutData_KeyIndex[], + uint32_t OutData_EncIV[]); +rsip_ret_t r_rsip_peef(uint32_t OutData_EncCertificateInfo[]); +rsip_ret_t r_rsip_peei(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +rsip_ret_t r_rsip_p51f(uint32_t OutData_EncCertificateInfo[]); +rsip_ret_t r_rsip_p51i(const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +rsip_ret_t r_rsip_p5ff(uint32_t OutData_EncCertificateInfo[]); +rsip_ret_t r_rsip_p5fi(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +rsip_ret_t r_rsip_p52f(uint32_t OutData_EncCertificateInfo[]); +rsip_ret_t r_rsip_p52i(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[], + const uint32_t InData_DomainParam[]); +rsip_ret_t r_rsip_peff(const uint32_t InData_Msg1[], + const uint32_t InData_Msg1Length[], + const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], + const uint32_t InData_Msg2[], + const uint32_t InData_Msg2Length[], + uint32_t OutData_KDFInfo[]); +rsip_ret_t r_rsip_pefi(const uint32_t InData_HashType[], const uint32_t InData_MsgLen[]); +rsip_ret_t r_rsip_pefr(const uint32_t InData_HashType[], const uint32_t InData_State[]); +rsip_ret_t r_rsip_pefs(uint32_t OutData_State[]); +rsip_ret_t r_rsip_pefu(const uint32_t InData_Msg1[], + const uint32_t InData_Msg1Length[], + const uint32_t InData_EncMsg[], + const uint32_t InData_EncMsgLength[], + const uint32_t InData_Msg2[], + const uint32_t InData_Msg2Length[]); + +rsip_ret_t r_rsip_p0c(const uint32_t InData_CurrentVer[], const uint32_t InData_NextVer[]); +rsip_ret_t r_rsip_p0d(const uint32_t InData_KeyCertificate[], + const uint32_t InData_KeyCertificateLength[], + const uint32_t InData_KeyCertificateSignature[], + const uint32_t InData_KeyCertificatePubKey[], + const uint32_t InData_ImgPkHash[], + const uint32_t InData_OemRootPkHashIndex[], + const uint32_t InData_CodeCertificate[], + const uint32_t InData_CodeCertificateLength[], + const uint32_t InData_CodeCertificateSignature[], + const uint32_t InData_CodeCertificatePubKey[], + const uint32_t InData_Image[], + const uint32_t InData_DomainParam[], + uint32_t MAX_CNT, + uint32_t OutData_MAC[]); +rsip_ret_t r_rsip_p0e(void); + +#endif /* R_RSIP_PRIMITIVE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_sub_func.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_sub_func.c new file mode 100644 index 0000000000..745dc66c44 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_sub_func.c @@ -0,0 +1,45 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" +#include "r_rsip_reg.h" +#include "r_rsip_util.h" +#include "r_rsip_sub_func.h" + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +void r_rsip_func_sub001 (uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4) +{ + WR1_PROG(REG_1014H, arg1); + WR1_PROG(REG_1018H, arg2); + WR1_PROG(REG_1020H, arg3); + + WR1_PROG(REG_1004H, arg4); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); +} + +void r_rsip_func_sub002 (uint32_t arg1) +{ + WR1_PROG(REG_1400H, arg1); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + +void r_rsip_func_sub003 (uint32_t arg1, uint32_t arg2, uint32_t arg3) +{ + WR1_PROG(REG_101CH, arg1); + WR1_PROG(REG_1020H, arg2); + + WR1_PROG(REG_1004H, arg3); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_sub_func.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_sub_func.h new file mode 100644 index 0000000000..571e5e993e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/primitive/ra_rsip_e51a/r_rsip_sub_func.h @@ -0,0 +1,17 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_SUB_FUNC_HEADER_FILE +#define R_RSIP_SUB_FUNC_HEADER_FILE + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +void r_rsip_func_sub001(uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4); +void r_rsip_func_sub002(uint32_t arg1); +void r_rsip_func_sub003(uint32_t arg1, uint32_t arg2, uint32_t arg3); + +#endif /* R_RSIP_SUB_FUNC_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/common.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/common.h new file mode 100644 index 0000000000..073985f55c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/common.h @@ -0,0 +1,45 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : common.h + * Version : 1.0 + * Description : . + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "types.h" +#include "regbase.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +#ifndef SRC_COMMON_COMMON_H_ +#define SRC_COMMON_COMMON_H_ + +#define RAM_GLOBAL_START ((uint32_t) 0x22000000) +#define RAM_GLOBAL_END ((uint32_t) 0x22000FFF) +#define RAM_STACK_START ((uint32_t) 0x22007800) +#define RAM_STACK_END ((uint32_t) 0x22007BFF) + +#define WORD_BYTE_SIZE ((uint32_t) 4) + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ + + +#endif /* SRC_COMMON_COMMON_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/regbase.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/regbase.h new file mode 100644 index 0000000000..23420f7851 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/regbase.h @@ -0,0 +1,49 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : regbase.h + * Version : 1.0 + * Description : . + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +#ifndef SRC_COMMON_REGBASE_H_ +#define SRC_COMMON_REGBASE_H_ + +#define CM_u32BASE_INFOAREA2 ((uint32_t)0x0100A000UL) +#define CM_u32BASE_FSBLOPTION ((uint32_t)0x27030000UL) +#define CM_u32BASE_ARM ((uint32_t)0xE000E000UL) +#define CM_u32BASE_CPSCU ((uint32_t)0x40008000UL) +#define CM_u32BASE_DMAC ((uint32_t)0x4000A000UL) +#define CM_u32BASE_DBGREG ((uint32_t)0x4001B000UL) +#define CM_u32BASE_FCACHE ((uint32_t)0x4001C100UL) +#define CM_u32BASE_SYS ((uint32_t)0x4001E000UL) +#define CM_u32BASE_MSTP ((uint32_t)0x40203000UL) +#define CM_u32BASE_PSCU ((uint32_t)0x40204000UL) +#define CM_u32BASE_CRC ((uint32_t)0x40310000UL) +#define CM_u32BASE_GPIO ((uint32_t)0x40400000UL) + + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ + +#endif /* SRC_COMMON_REGBASE_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/types.h new file mode 100644 index 0000000000..43c1333dc6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/common/types.h @@ -0,0 +1,42 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : types.h + * Version : 1.0 + * Description : . + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +#ifndef SRC_COMMON_TYPES_H_ +#define SRC_COMMON_TYPES_H_ + +#define TRUE ( (u8)1 ) +#define FALSE ( (u8)0 ) + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ + +#endif /* SRC_COMMON_TYPES_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/inc/r_cip_drv_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/inc/r_cip_drv_api.h new file mode 100644 index 0000000000..f68047f708 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/inc/r_cip_drv_api.h @@ -0,0 +1,230 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_cip_drv_api.h +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file defines the public macros, types and declarations in used the Crypto IP Driver. +**********************************************************************************************************************/ +#ifndef R_CIP_DRV_API_H +#define R_CIP_DRV_API_H + +#include + +/*===================================================================================================================== + Public macro definitions +=====================================================================================================================*/ +/* return value */ +#define CIP_DRV_RET_PASS ((cip_drv_ret_t)0x55555555UL) /* Successful completion */ +#define CIP_DRV_RET_SAME_IMAGE_VERSION ((cip_drv_ret_t)0x55005501UL) /* The same version as the current + image version was entered */ +#define CIP_DRV_RET_FAIL ((cip_drv_ret_t)0xAAAA0001UL) /* Abnormal termination */ +#define CIP_DRV_RET_RESOURCE_CONFLICT ((cip_drv_ret_t)0xAAAA0002UL) /* Resource collision occurs because + resources required for this process are + used by other processes */ +#define CIP_DRV_RET_RETRY ((cip_drv_ret_t)0xAAAA0003UL) /* Retryable error */ +#define CIP_DRV_RET_AUTH_FAIL ((cip_drv_ret_t)0xAAAA0004UL) /* Verification failed */ +#define CIP_DRV_RET_UNSUPPORTED_ALGORITHM ((cip_drv_ret_t)0xAAAA0005UL) /* Unsupported algorithm */ +#define CIP_DRV_RET_LOWER_IMAGE_VERSION ((cip_drv_ret_t)0xAAAA0006UL) /* A version lower than the current + image version has been entered */ +#define CIP_DRV_RET_PARAM_ERROR ((cip_drv_ret_t)0xAAAA0007UL) /* Parameter error */ + +#define CIP_DRV_RET_KEY_SET_FAIL ((cip_drv_ret_t)0xAAAA0008UL) /* Parameter error */ +#define CIP_DRV_RET_TAMPER_DETECT ((cip_drv_ret_t)0xAAAA0009UL) /* Tamper detect error */ +#define CIP_DRV_RET_CRC_MISMATCH ((cip_drv_ret_t)0xAAAA000AUL) /* CRC mismatch */ + +/* Root of Trust type */ +#define CIP_DRV_KEY_CERT_PK_CMP_SRC_ROT (0UL) +#define CIP_DRV_KEY_CERT_PK_CMP_SRC_IMG_PK (1UL) + + +/* HASH algorithm */ +#define CIP_DRV_HASH_ALGO_NONE (0UL) +#define CIP_DRV_HASH_ALGO_SHA2_224 (1UL) +#define CIP_DRV_HASH_ALGO_SHA2_256 (2UL) +#define CIP_DRV_HASH_ALGO_SHA2_384 (3UL) +#define CIP_DRV_HASH_ALGO_SHA2_512 (4UL) +#define CIP_DRV_HASH_ALGO_SHA3_224 (5UL) +#define CIP_DRV_HASH_ALGO_SHA3_256 (6UL) +#define CIP_DRV_HASH_ALGO_SHA3_384 (7UL) +#define CIP_DRV_HASH_ALGO_SHA3_512 (8UL) + +/* MAC algorithm */ +#define CIP_DRV_MAC_ALGO_NONE (0UL) +#define CIP_DRV_MAC_ALGO_HMAC_SHA2_224 (1UL) +#define CIP_DRV_MAC_ALGO_HMAC_SHA2_256 (2UL) +#define CIP_DRV_MAC_ALGO_HMAC_SHA2_384 (3UL) +#define CIP_DRV_MAC_ALGO_HMAC_SHA2_512 (4UL) +#define CIP_DRV_MAC_ALGO_HMAC_SHA3_224 (5UL) +#define CIP_DRV_MAC_ALGO_HMAC_SHA3_256 (6UL) +#define CIP_DRV_MAC_ALGO_HMAC_SHA3_384 (7UL) +#define CIP_DRV_MAC_ALGO_HMAC_SHA3_512 (8UL) +#define CIP_DRV_MAC_ALGO_CMAC_AES_128 (9UL) +#define CIP_DRV_MAC_ALGO_CMAC_AES_192 (10UL) +#define CIP_DRV_MAC_ALGO_CMAC_AES_256 (11UL) + +/* Signature algorithm */ +#define CIP_DRV_SIGN_ALGO_NONE (0UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_P192 (1UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_P224 (2UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_P256 (3UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_P384 (4UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_P521 (5UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_BP192R1 (6UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_BP224R1 (7UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_BP256R1 (8UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_BP384R1 (9UL) +#define CIP_DRV_SIGN_ALGO_ECDSA_BP512R1 (10UL) +#define CIP_DRV_SIGN_ALGO_EDDSA_ED25519 (11UL) +#define CIP_DRV_SIGN_ALGO_EDDSA_ED448 (12UL) +#define CIP_DRV_SIGN_ALGO_RSA1024 (13UL) +#define CIP_DRV_SIGN_ALGO_RSA2048 (14UL) +#define CIP_DRV_SIGN_ALGO_RSA3072 (15UL) +#define CIP_DRV_SIGN_ALGO_RSA4096 (16UL) + + +/* Signature scheme */ +#define CIP_DRV_SCHEME_NONE (0UL) +#define CIP_DRV_SCHEME_RSASSA_PKCS1_V1_5 (1UL) +#define CIP_DRV_SCHEME_RSASSA_PSS (2UL) + +/* Cipher algorithm */ +#define CIP_DRV_CIPHER_ALGO_NONE (0UL) +#define CIP_DRV_CIPHER_ALGO_AES128 (1UL) +#define CIP_DRV_CIPHER_ALGO_AES192 (2UL) +#define CIP_DRV_CIPHER_ALGO_AES256 (3UL) + +/* Cipher mode */ +#define CIP_DRV_CIPHER_MODE_NONE (0UL) +#define CIP_DRV_CIPHER_MODE_ECB (1UL) +#define CIP_DRV_CIPHER_MODE_CBC (2UL) +#define CIP_DRV_CIPHER_MODE_CFB (3UL) +#define CIP_DRV_CIPHER_MODE_OFB (4UL) +#define CIP_DRV_CIPHER_MODE_CTR (5UL) + +/* Key select */ +#define CIP_DRV_CIPHER_INFO_KEY_SEL_DEFAULT (0x00000000UL) +#define CIP_DRV_CIPHER_INFO_KEY_SEL_DEV_UNIQUE (0x00010000UL) +#define CIP_DRV_CIPHER_INFO_KEY_SEL_INSTALLED (0x00020000UL) + +/* IV select */ +#define CIP_DRV_CIPHER_INFO_IV_SEL_DEFAULT (0x00000000UL) +#define CIP_DRV_CIPHER_INFO_IV_SEL_DEV_UNIQUE (0x00010000UL) +#define CIP_DRV_CIPHER_INFO_IV_SEL_INSTALLED (0x00020000UL) +#define CIP_DRV_CIPHER_INFO_IV_SEL_STORED_CODE_CERT (0x00030000UL) + +/* Cipher timinig */ +#define CIP_DRV_CIPHER_TIMING_NONE (0UL) +#define CIP_DRV_CIPHER_TIMING_BEFORE_VERIFY (1UL) +#define CIP_DRV_CIPHER_TIMING_AFTER_VERIFY (2UL) + +/*===================================================================================================================== + Public type definitions +=====================================================================================================================*/ +/* cip_drv return type */ +typedef uint32_t cip_drv_ret_t; + +/* MAC verification parameter */ +typedef struct +{ + uint32_t mac_algo; + const uint32_t* p_mac; + uint32_t mac_len; + const uint32_t* p_code_cert; + uint32_t code_cert_len; + const uint32_t* p_img; + uint32_t img_len; + uint32_t is_save_img_pk; + const uint32_t* p_sign_pk; + uint32_t sign_pk_len; +} st_cip_drv_mac_param_t; + +/* Certificate chain verification KeyCert parameter */ +typedef struct +{ + uint32_t key_cert_pk_cmp_src; + uint32_t img_pk_hash_algo; + const uint32_t* p_img_pk_hash; + uint32_t img_pk_hash_len; + uint32_t sign_algo; + uint32_t sign_hash_algo; + uint32_t sign_scheme; + const uint32_t* p_sign_pk; + uint32_t sign_pk_len; + const uint32_t* p_sign; + uint32_t sign_len; + const uint32_t* p_key_cert; + uint32_t key_cert_sign_len; +} st_cip_drv_cc_key_cert_param_t; + +/* Certificate chain verification CodeCert parameter */ +typedef struct +{ + uint32_t sign_algo; + uint32_t sign_hash_algo; + uint32_t sign_scheme; + const uint32_t* p_sign_pk; + uint32_t sign_pk_len; + const uint32_t* p_sign; + uint32_t sign_len; + const uint32_t* p_code_cert; + uint32_t code_cert_len; + uint32_t code_cert_sign_len; + const uint32_t* p_img; + uint32_t img_len; + uint32_t img_hash_algo; + const uint32_t* p_img_hash; + uint32_t img_hash_len; + uint32_t is_save_img_pk; +} st_cip_drv_cc_code_cert_param_t; + +/* image cipher parameter */ +typedef struct +{ + uint32_t timing; + const uint32_t* p_img_src; + uint32_t* p_img_dst; + uint32_t img_len; + uint32_t cipher_algo; + uint32_t cipher_mode; + uint32_t key_select; + uint32_t iv_select; + const uint32_t* p_iv; + uint32_t iv_len; +}st_cip_drv_cipher_img_param_t; + +/* CRC check parameter */ +typedef struct +{ + uint32_t crc_algo; + const uint32_t * p_crc; + const uint32_t * p_img; + uint32_t img_len; +} st_cip_drv_crc_param_t; + + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global functions +=====================================================================================================================*/ +extern cip_drv_ret_t R_CIP_DRV_PrcDeriveMacKeyFromHuk(void); +extern cip_drv_ret_t R_CIP_DRV_PrcCheckIntegrity(const st_cip_drv_cc_key_cert_param_t* const p_cc_key_cert_param, + const st_cip_drv_cc_code_cert_param_t* const p_cc_code_cert_param, + const st_cip_drv_cipher_img_param_t* const p_dec_tmp_img_param, + const st_cip_drv_cipher_img_param_t* const p_enc_img_param, + const uint32_t mac_algo, uint32_t* const p_tag); +extern cip_drv_ret_t R_CIP_DRV_CheckImageVersion(const uint32_t image_version, + const uint32_t build_num); + +#endif /* R_CIP_DRV_API_H */ +/*===================================================================================================================== + End of File +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_drv_api.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_drv_api.c new file mode 100644 index 0000000000..8c15d624c3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_drv_api.c @@ -0,0 +1,330 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * File Name : r_tsip_api.c + * @brief Interface definition for the r_tsip module. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup grp_device_hal_tsip Device HAL TSIP Implementation + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include +#include "r_cip_private.h" +#include "r_sb_api.h" +#include "r_sb_manifest.h" +#include "r_vdev_fsbl_option.h" +#include "r_rsip_primitive.h" +#include "r_rsip_util.h" + +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ +#define QX_END_POSTION_OFFSET (31) +#define QY_START_POSTION_OFFSET (32) +#define QY_END_POSTION_OFFSET (63) + +#define KEY_CART_TLV_START_POSTION (9) +#define KEY_CART_TLV_LENGTH_POSTION (8) + +#define CRC_DMA_BLOCK_WORD_SIZE (64u) +#define CRC_DMA_BLOCK_BYTE_SIZE (256u) + +#define OEMBL_VER_INIT_VALUE (0xFF) +#define OEMBL_VER_MASK_INIT (0x80000000) +#define OEMBL_VER_LOOP_MASK (0x1F) +#define OEMBL_VER_MAX_VALUE (64) + +/*********************************************************************************************************************** + Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief The API for outputting random User Key Generation Information of AES256 bit. + * @param[in,out] *key_index Output the user Key Generation Information + * @retval TSIP_SUCCESS Success + * @retval TSIP_ERR_RESOURCE_CONFLICT Resource conflict + * @details This API outputs 256-bit AES user key index.@n + * This API generates a user key from a random number in the TSIP. Accordingly, user key input is unnecessary. + * By encrypting data using the user key index that is output by this API, dead copying of data + * can be prevented. + * @pre TSIP Enabled State + * @post TSIP Enabled State@n + **********************************************************************************************************************/ +cip_drv_ret_t R_CIP_DRV_CheckImageVersion(const uint32_t image_version, const uint32_t build_num) +{ + FSP_PARAMETER_NOT_USED(build_num); + + rsip_ret_t rsip_ret; + cip_drv_ret_t ret; + + uint32_t next_ver[1]; + uint32_t current_ver[1]; + uint32_t Fcntdata[2]; + uint8_t loop = 0; + uint8_t oembl_version = OEMBL_VER_INIT_VALUE; + + next_ver[0] = image_version; + + Fcntdata[0] = VFSBL_FCNTDATAR1; + Fcntdata[1] = VFSBL_FCNTDATAR0; + + /* Convert version value read from Flash to integer format */ + while( ( ( Fcntdata[(loop >> 5)] & ( OEMBL_VER_MASK_INIT >> ( loop & OEMBL_VER_LOOP_MASK ) ) ) == 0 ) ) + { + loop++; + + if( loop >= OEMBL_VER_MAX_VALUE ){ break; } + } + + oembl_version = OEMBL_VER_MAX_VALUE - loop; + + current_ver[0] = (uint32_t)oembl_version; + + rsip_ret = r_rsip_p0c(current_ver, next_ver); + + /* Convert error code */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + ret = CIP_DRV_RET_PASS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + ret = CIP_DRV_RET_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_VERIFICATION_FAIL: + { + ret = CIP_DRV_RET_LOWER_IMAGE_VERSION; + break; + } + + case RSIP_RET_VERSION_MATCH: + { + ret = CIP_DRV_RET_SAME_IMAGE_VERSION; + break; + } + + default: + { + ret = CIP_DRV_RET_FAIL; + } + } + + return ret; +} + +/*************************************** + End of function R_CIP_DRV_CheckImageVersion + ***************************************/ + +/*******************************************************************************************************************//** + * @brief The API unwraps Wraped Hardware Unique Key(W-HUK) and loads it inside IP. + * @retval CIP_DRV_RET_SUCCESS Success + * @retval CIP_DRV_RET_ERR_RESOURCE_CONFLICT Resource conflict + * @retval CIP_DRV_RET_ERR_FAIL Abnormal termination + * @details The API unwraps Wraped Hardware Unique Key(W-HUK) and loads it inside IP. + **********************************************************************************************************************/ +cip_drv_ret_t R_CIP_DRV_PrcDeriveMacKeyFromHuk(void) +{ + return CIP_DRV_RET_SUCCESS; +} +/*************************************** + End of function R_CIP_DRV_PrcDeriveMacKeyFromHuk + ***************************************/ + + +/*******************************************************************************************************************//** + * @brief Data (key certificate and code certificate) signature verification is performed. + * @param[in] *p_cc_key_cert_param key certification information, + * @param[in] p_cc_code_cert_param code certification information. + * @param[in] p_dec_tmp_img_param dummy + * @param[in] p_enc_img_param + * @param[in] mac_algo dummy + * @param[in,out] *p_tag MAC of Code Certificate. + * @retval CIP_DRV_RET_PASS Success + * @retval CIP_DRV_RET_RESOURCE_CONFLICT Resource conflict + * @retval CIP_DRV_RET_PARAM_ERROR Input parameter error + * @retval CIP_DRV_RET_FAIL Abnormal termination + * @details This API verifies the signatures of Data. + * If the signature verification is successful, the HMAC-SHA256 caluclation of the Image and Code certificate. + * Support elliptic curves are NIST P-256. + **********************************************************************************************************************/ +cip_drv_ret_t R_CIP_DRV_PrcCheckIntegrity(const st_cip_drv_cc_key_cert_param_t* const p_cc_key_cert_param, + const st_cip_drv_cc_code_cert_param_t* const p_cc_code_cert_param, + const st_cip_drv_cipher_img_param_t* const p_dec_tmp_img_param, + const st_cip_drv_cipher_img_param_t* const p_enc_img_param, + const uint32_t mac_algo, uint32_t* const p_tag) +{ + FSP_PARAMETER_NOT_USED(p_dec_tmp_img_param); + FSP_PARAMETER_NOT_USED(p_enc_img_param); + FSP_PARAMETER_NOT_USED(mac_algo); + + rsip_ret_t rsip_ret; + cip_drv_ret_t ret; + uint32_t KeyCertificateLength[1]; + uint32_t KeyCertificatePubKey[4]; + uint32_t ImgPkHash[2]; + uint32_t CodeCertificateLength[1]; + uint32_t CodeCertificatePubKey[4]; + uint32_t QxPubKeyPt; + uint32_t ImgPkHashPt; + uint32_t ImageLen; + const st_sb_search_tlv_type_t search_tlv_signer_id[1] = + { + { 0x10000000U, 0xFF000000U } + }; + st_sb_tlv_t signer_id_tlvs[1]; + cip_drv_ret_t ret_complement; + + if(p_cc_code_cert_param->img_len < R_SHIP_OEM_BL_MIN_SIZE) + { + return CIP_DRV_RET_PARAM_ERROR; + } + + KeyCertificateLength[0] = bswap_32big(p_cc_key_cert_param->key_cert_sign_len ) ; + QxPubKeyPt = (uint32_t) ((p_cc_key_cert_param->p_sign_pk - p_cc_key_cert_param->p_key_cert)<<2); + KeyCertificatePubKey[0] = bswap_32big(QxPubKeyPt); + KeyCertificatePubKey[1] = bswap_32big(QxPubKeyPt + QX_END_POSTION_OFFSET); + KeyCertificatePubKey[2] = bswap_32big(QxPubKeyPt + QY_START_POSTION_OFFSET); + KeyCertificatePubKey[3] = bswap_32big(QxPubKeyPt + QY_END_POSTION_OFFSET); + + ret = r_sb_mani_parse_tlvs((const uint8_t*)&p_cc_key_cert_param->p_key_cert[KEY_CART_TLV_START_POSTION] , + (p_cc_key_cert_param->p_key_cert[KEY_CART_TLV_LENGTH_POSTION]), + 1, search_tlv_signer_id, signer_id_tlvs); + if (SB_RET_SUCCESS != ret) + { + return CIP_DRV_RET_PARAM_ERROR; + } + ImgPkHashPt = (uint32_t) ((signer_id_tlvs->p_val - p_cc_key_cert_param->p_key_cert)<<2); + ImgPkHash[0] = bswap_32big(ImgPkHashPt ); + ImgPkHash[1] = bswap_32big((ImgPkHashPt + signer_id_tlvs->byte_len) -1 ); + + CodeCertificateLength[0] = bswap_32big(p_cc_code_cert_param->code_cert_sign_len); + QxPubKeyPt = (uint32_t) ((p_cc_code_cert_param->p_sign_pk - p_cc_code_cert_param->p_code_cert)<<2); + CodeCertificatePubKey[0] = bswap_32big(QxPubKeyPt); + CodeCertificatePubKey[1] = bswap_32big(QxPubKeyPt + QX_END_POSTION_OFFSET); + CodeCertificatePubKey[2] = bswap_32big(QxPubKeyPt + QY_START_POSTION_OFFSET); + CodeCertificatePubKey[3] = bswap_32big(QxPubKeyPt + QY_END_POSTION_OFFSET); + ImageLen = bswap_32big(p_cc_code_cert_param->img_len>>2); + + rsip_ret = r_rsip_p0d((uint32_t *) p_cc_key_cert_param->p_key_cert, + KeyCertificateLength, + (uint32_t *) p_cc_key_cert_param->p_sign, + KeyCertificatePubKey, + ImgPkHash, + (uint32_t *) VFSBL_OEMROOTPKHASH_ADDR, + (uint32_t *) p_cc_code_cert_param->p_code_cert, + CodeCertificateLength, + (uint32_t *) p_cc_code_cert_param->p_sign, + CodeCertificatePubKey, + (uint32_t *) p_cc_code_cert_param->p_img, + DomainParam_NIST_P256, + ImageLen, + &p_tag[1]); + + /* Convert error code */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + ret = CIP_DRV_RET_PASS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + ret = CIP_DRV_RET_RESOURCE_CONFLICT; + break; + } + + case RSIP_RET_PARAM_FAIL: + { + ret = CIP_DRV_RET_PARAM_ERROR; + break; + } + + case RSIP_RET_VERIFICATION_FAIL: + { + ret = CIP_DRV_RET_AUTH_FAIL; + break; + } + + default: + { + ret = CIP_DRV_RET_FAIL; + } + } + + if (CIP_DRV_RET_PASS == ret) + { + ret_complement = ~CIP_DRV_RET_PASS; + if((~ret) == ret_complement) + { + p_tag[0] = R_CIP_DRV_HMAC_SHA256_TLV; + rsip_ret = r_rsip_p0e(); + + /* Convert error code */ + switch (rsip_ret) + { + case RSIP_RET_PASS: + { + ret = CIP_DRV_RET_PASS; + break; + } + + case RSIP_RET_RESOURCE_CONFLICT: + { + ret = CIP_DRV_RET_RESOURCE_CONFLICT; + break; + } + + default: + { + ret = CIP_DRV_RET_FAIL; + } + } + } + else + { + ret = CIP_DRV_RET_TAMPER_DETECT; + } + } + else + { + __NOP(); + } + + return ret; +} +/*************************************** + End of function R_CIP_DRV_PrcCheckIntegrity + ***************************************/ + +/*******************************************************************************************************************//** + * @} (end addtogroup Device HAL TSIP (Trusted Secure IP modules)) + **********************************************************************************************************************/ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_drv_if.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_drv_if.h new file mode 100644 index 0000000000..e764b77ee8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_drv_if.h @@ -0,0 +1,169 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * File Name : r_cip_drv_if.h + * Description : Interface definition for the RSIP driver for RA8M1 module. + *********************************************************************************************************************** + * Supported Device : RA8M1(RA8x1) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + Includes , "Project Includes" + **********************************************************************************************************************/ +#include + +#ifndef R_CIP_HEADER_FILE +#define R_CIP_HEADER_FILE + +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ +/* Version Number of API. */ +#define CIP_VERSION_MAJOR (1u) +#define CIP_VERSION_MINOR (3u) + +#define R_CIP_SRAM_WORD_SIZE (256u) +#define R_CIP_SFLASH_WORD_SIZE (200u) + +#define R_CIP_HUK_INDEX_WORD_SIZE (12u) +#define R_CIP_OEM_KEY_INDEX_WORD_SIZE (9u) +#define R_CIP_PASSWORD_BYTE_SIZE (64u) +#define R_CIP_MAC_BYTE_SIZE (32u) +#define R_CIP_CHALLENGE_BYTE_SIZE (32u) + +#define R_CIP_KEY_UPDATE_KEY_INST_WORD_SIZE (12u) +#define R_CIP_KEY_UPDATE_KEY_INDEX_WORD_SIZE (13u) + +/* Return error codes */ +/* return value */ +#define CIP_DRV_RET_SUCCESS ((cip_drv_err_t)0x55555555UL) /* Successful completion */ +#define CIP_DRV_RET_ERR_FAIL ((cip_drv_err_t)0xAAAA0001UL) /* Abnormal termination */ +#define CIP_DRV_RET_ERR_RESOURCE_CONFLICT ((cip_drv_err_t)0xAAAA0002UL) /* Resource collision occurs because + resources required for this process are + used by other processes */ +#define CIP_DRV_RET_ERR_RETRY ((cip_drv_err_t)0xAAAA0003UL) /* Retryable error */ +#define CIP_DRV_RET_ERR_AUTH_FAIL ((cip_drv_err_t)0xAAAA0004UL) /* Verification failed */ +#define CIP_DRV_RET_UNSUPPORTED_ALGORITHM ((cip_drv_ret_t)0xAAAA0005UL) /* Unsupported algorithm */ +#define CIP_DRV_RET_LOWER_IMAGE_VERSION ((cip_drv_ret_t)0xAAAA0006UL) /* A version lower than the current + image version has been entered */ +#define CIP_DRV_RET_PARAM_ERROR ((cip_drv_ret_t)0xAAAA0007UL) /* Parameter error */ + +#define CIP_DRV_RET_ERR_KEY_SET_FAIL ((cip_drv_err_t)0xAAAA0008UL) /* Invalid key generation information */ +#define CIP_DRV_RET_TAMPER_DETECT ((cip_drv_ret_t)0xAAAA0009UL) /* Tampering was detected */ + +#define CIP_DRV_CALL_ONLY_INIT (0) +#define CIP_DRV_CALL_ONLY_UPDATE_FINAL (1) +#define CIP_DRV_AES_BLOCK_BYTE_SIZE (16) +#define CIP_DRV_FORMAT_DATA_SIZE (CIP_DRV_AES_BLOCK_BYTE_SIZE) +#define CIP_DRV_CCM_BUF_SIZE (CIP_DRV_AES_BLOCK_BYTE_SIZE*2) + +#define CIP_DRV_CCM_B_FORMAT_BYTE_SIZE (128u) +#define CIP_DRV_CCM_COUNTER_BYTE_SIZE (16u) + +/*********************************************************************************************************************** + Typedef definitions + **********************************************************************************************************************/ +/* cip_drv return type */ +typedef uint32_t cip_drv_err_t; + +/* Data structure for decrypting ciphertext */ +typedef struct { + uint32_t id; + uint8_t formatted_data[CIP_DRV_CCM_B_FORMAT_BYTE_SIZE]; + uint8_t counter[CIP_DRV_CCM_COUNTER_BYTE_SIZE]; + uint8_t ccm_buffer[CIP_DRV_CCM_BUF_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} ship_ccm_handle_t; + +/* LIFE CYCLE */ +typedef enum +{ + CIP_CM1 = 0, + CIP_CM2, + CIP_OEM = 4, + CIP_RMA_REQ = 7, + CIP_RMA_ACK, + CIP_RMA_RET, +} lifecycle_t; + +/* AUTHENTIC COMMAND*/ +typedef enum +{ + CIP_AUTH_CM1_CMD = 0, + CIP_AUTH_AL2_CMD, + CIP_AUTH_AL1_CMD, + CIP_AUTH_RMA_CMD, + CIP_AUTH_RMA_ACK_CMD, +} auth_cmd_t; + +/* OEM key type */ +typedef enum +{ + CIP_OEM_KEY_TYPE_AUTH_CM1 = 0, + CIP_OEM_KEY_TYPE_AUTH_AL2, + CIP_OEM_KEY_TYPE_AUTH_AL1, + CIP_OEM_KEY_TYPE_AUTH_RMA, + CIP_OEM_KEY_TYPE_AUTH_RMA_ACK, + CIP_OEM_KEY_TYPE_AES128, + CIP_OEM_KEY_TYPE_AES192, + CIP_OEM_KEY_TYPE_AES256, + CIP_OEM_KEY_TYPE_AES128_XTS, + CIP_OEM_KEY_TYPE_AES256_XTS, + CIP_OEM_KEY_TYPE_RSA1024_PUBLIC, + CIP_OEM_KEY_TYPE_RSA1024_PRIVATE, + CIP_OEM_KEY_TYPE_RSA2048_PUBLIC, + CIP_OEM_KEY_TYPE_RSA2048_PRIVATE, + CIP_OEM_KEY_TYPE_RSA3072_PUBLIC, + CIP_OEM_KEY_TYPE_RSA3072_PRIVATE, + CIP_OEM_KEY_TYPE_RSA4096_PUBLIC, + CIP_OEM_KEY_TYPE_RSA4096_PRIVATE, + CIP_OEM_KEY_TYPE_ECC_P192_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_P192_PRIVATE, + CIP_OEM_KEY_TYPE_ECC_P224_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_P224_PRIVATE, + CIP_OEM_KEY_TYPE_ECC_P256_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_P256_PRIVATE, + CIP_OEM_KEY_TYPE_ECC_P384_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_P384_PRIVATE, + CIP_OEM_KEY_TYPE_HMAC_SHA224, + CIP_OEM_KEY_TYPE_HMAC_SHA256, + CIP_OEM_KEY_TYPE_ECC_P256R1_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_P256R1_PRIVATE, + CIP_OEM_KEY_TYPE_ECC_P384R1_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_P384R1_PRIVATE, + CIP_OEM_KEY_TYPE_ECC_P512R1_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_P512R1_PRIVATE, + CIP_OEM_KEY_TYPE_ECC_SECP256K1_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_SECP256K1_PRIVATE, + CIP_OEM_KEY_TYPE_ECC_P521_PUBLIC, + CIP_OEM_KEY_TYPE_ECC_P521_PRIVATE, + CIP_OEM_KEY_TYPE_ED25519_PUBLIC, + CIP_OEM_KEY_TYPE_ED25519_PRIVATE, + CIP_OEM_KEY_TYPE_HMAC_SHA384, + CIP_OEM_KEY_TYPE_HMAC_SHA512, + CIP_OEM_KEY_TYPE_HMAC_SHA512_224, + CIP_OEM_KEY_TYPE_HMAC_SHA512_256, + CIP_OEM_KEY_TYPE_NUM, + CIP_OEM_KEY_TYPE_OEM_ROOT_PK = 0xfdU, + CIP_OEM_KEY_TYPE_RSA2048_PUBLIC_TLS, + CIP_OEM_KEY_TYPE_KEY_UPDATE_KEY, +} oem_key_type_t; + +#define USERKEYNUM (CIP_OEM_KEY_TYPE_NUM + 3) + +/*********************************************************************************************************************** + Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + + +#endif /* R_CIP_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_private.h new file mode 100644 index 0000000000..c97e611335 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_cip_private.h @@ -0,0 +1,56 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * File Name : r_tsip_rx_private.h + * Description : TSIP function private header file. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + Includes , "Project Includes" + **********************************************************************************************************************/ +#include "r_cip_drv_if.h" +#include "r_cip_drv_api.h" + +#ifndef R_CIP_PRIVATE_HEADER_FILE + #define R_CIP_PRIVATE_HEADER_FILE + +/*********************************************************************************************************************** + Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + Typedef definitions + **********************************************************************************************************************/ +#define R_SHIP_SHIP_BYTE_SWAP_SET (0x00010001U) +#define R_CIP_DRV_HMAC_SHA256_TLV (0x30184008) + +#define R_SHIP_SRAM_WORD_SIZE (256U) +#define R_SHIP_SHA256_HASH_LENGTH_BYTE_SIZE (64U) +#define R_SHIP_SHA256_HASH_LENGTH_WORD_SIZE (16U) +#define R_SHIP_CODE_CART_SIG_BYTE_SIZE (64U) +#define R_SHIP_CART_TLV_BYTE_SIZE (4U) +#define R_SHIP_CART_TLV_WORD_SIZE ((uint32_t) 1U) + +#define R_SHIP_WORD_BYTE_ROUND ((uint32_t) 3U) + +#define R_SHIP_BIT_TO_BYTE_CHANGE_LOWER (0x1FFFFFFFU) +#define R_SHIP_BIT_TO_BYTE_CHANGE_UPPER (0xE0000000U) +#define R_SHIP_BIT_TO_BYTE_SHIFT_LOWER (3U) +#define R_SHIP_BIT_TO_BYTE_SHIFT_UPPER (29U) +#define R_SHIP_BIT_BUFFER_SIZE (2U) + +#define R_SHIP_OEM_BL_MIN_SIZE (64U) + +/*********************************************************************************************************************** + Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif /* R_CIP_PRIVATE_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_vdev_fsbl_option.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_vdev_fsbl_option.h new file mode 100644 index 0000000000..28021c03ca --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/rsip/ra_rsip_e51a/src/r_vdev_fsbl_option.h @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_vdev_fsbl_option.h + * Version : 1.0 + * Description : . + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "common.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +#ifndef SRC_VDEV_R_VDEV_FSBL_OPTION_H_ +#define SRC_VDEV_R_VDEV_FSBL_OPTION_H_ + +#define VFSBL_u32FSBLCTRL0 (*(( volatile u32 *)( CM_u32BASE_FSBLOPTION + (u32)(0x00000080)))) +#define VFSBL_u32FSBLCTRL0_FSBLCLK_MASK ( (u32)0x00000E00 ) +#define VFSBL_u32FSBLCTRL0_FSBLCLK_BIT_NUM ( (u32)3 ) + +#define VFSBL_u32FSBLCTRL1 (*(( volatile u32 *)( CM_u32BASE_FSBLOPTION + (u32)(0x00000084)))) +#define VFSBL_u32FSBLCTRL1_FSBLEXMD_MASK ( (u32)0x00000003 ) +#define VFSBL_u32FSBLCTRL1_FSBLEXMD_00 ( (u32)0x00000000 ) +#define VFSBL_u32FSBLCTRL1_FSBLEXMD_01 ( (u32)0x00000001 ) +#define VFSBL_u32FSBLCTRL1_FSBLEXMD_10 ( (u32)0x00000002 ) +#define VFSBL_u32FSBLCTRL1_FSBLEXMD_11 ( (u32)0x00000003 ) + +#define VFSBL_u32FSBLCTRL2 (*(( volatile u32 *)( CM_u32BASE_FSBLOPTION + (u32)(0x00000088)))) +#define VFSBL_u32FSBLCTRL2_PORTPN_MASK ( (u32)0x0000000F ) +#define VFSBL_u32FSBLCTRL2_PORTGN_MASK ( (u32)0x000001F0 ) +#define VFSBL_u32FSBLCTRL2_PORTGN_SHIFT ( (u32)4 ) + +#define VFSBL_u32SACC0 (*(( volatile u32 *)( CM_u32BASE_FSBLOPTION + (u32)(0x0000008C)))) + +#define VFSBL_u32SACC1 (*(( volatile u32 *)( CM_u32BASE_FSBLOPTION + (u32)(0x00000090)))) + +#define VFSBL_u32SAMR (*(( volatile u32 *)( CM_u32BASE_FSBLOPTION + (u32)(0x00000094)))) + +#define VFSBL_OEMROOTPKHASH_ADDR ( CM_u32BASE_FSBLOPTION + (u32)(0x00000360)) + +#define VFSBL_FCNTDATAR0 (*(( volatile u32 *)( CM_u32BASE_FSBLOPTION + (u32)(0x00000878)))) +#define VFSBL_FCNTDATAR1 (*(( volatile u32 *)( CM_u32BASE_FSBLOPTION + (u32)(0x0000087C)))) + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ + +#endif /* SRC_VDEV_R_VDEV_FSBL_OPTION_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/inc/r_sb_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/inc/r_sb_api.h new file mode 100644 index 0000000000..9781c29863 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/inc/r_sb_api.h @@ -0,0 +1,342 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_api.h +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file defines the public macros, types and declarations in used the SB-Lib. +**********************************************************************************************************************/ + +#ifndef R_SB_API_H +/* Multiple inclusion protection macro */ +#define R_SB_API_H + +#include +/*!*********************************************************** + * \addtogroup SBLIB SecureBoot Library + * \{ + * \addtogroup SBLIBMod SecureBoot Library Modules + * \addtogroup SBLIBCfg SecureBoot Library Configurations + * \}********************************************************/ + +/*!*********************************************************** + * \addtogroup SBLIBMod SecureBoot Library Modules + * \{ + * \addtogroup SBLIBCommon SB-Lib Common module + * \addtogroup SBLIBSecureBoot SB-Lib SecureBoot module + * \addtogroup SBLIBCRC SB-Lib CRC module + * \addtogroup SBLIBManifest SB-Lib Manifest module + * \}********************************************************/ + +/*!*********************************************************** + * \addtogroup SBLIBCfg SecureBoot Library Configurations + * \{ + * \addtogroup SBLIBBC SB-Lib BuildConfiguration + * \}********************************************************/ + +/*===================================================================================================================== + Public macro definitions +=====================================================================================================================*/ +/*!********************************************************* + * \addtogroup SBLIBCommonDefines + * \{ + * \addtogroup group_return_code + * \addtogroup group_manifest_size + * \addtogroup group_unused_area + * \}******************************************************/ +/** SB-Lib return value definition */ +/**\addtogroup group_return_code Return code */ +/*! \{*/ +#define SB_RET_SUCCESS ((sb_ret_t)0x55555555UL) /**< API succeeded */ +#define SB_RET_SAME_IMAGE_VERSION ((sb_ret_t)0x55005501UL) /**< An image of the same version as the + current version is input + (verification completed successfully) */ +#define SB_RET_ERR_INTERNAL_FAIL ((sb_ret_t)0xAAAA0000UL) /**< A internal failure */ +#define SB_RET_ERR_INVALID_ARG ((sb_ret_t)0xAAAA0001UL) /**< An invalid argument was entered */ +#define SB_RET_ERR_UNSUPPORTED_FUNCTION ((sb_ret_t)0xAAAA0002UL) /**< Unsupported function executed */ +#define SB_RET_ERR_INVALID_ALIGNMENT ((sb_ret_t)0xAAAA0003UL) /**< Data entered with incorrect alignment */ +#define SB_RET_ERR_MANI_INVALID_MAGIC ((sb_ret_t)0xAAAA0100UL) /**< An invalid magic number is set */ +#define SB_RET_ERR_MANI_UNSUPPORTED_VERSION ((sb_ret_t)0xAAAA0101UL) /**< Unsupported version is set */ +#define SB_RET_ERR_MANI_OUT_OF_RANGE_LEN ((sb_ret_t)0xAAAA0102UL) /**< Out of range TLV Length is set */ +#define SB_RET_ERR_MANI_TLV_FIELD_ERR ((sb_ret_t)0xAAAA0103UL) /**< Missing required TLV field */ +#define SB_RET_ERR_MANI_TLV_INVALID_LEN ((sb_ret_t)0xAAAA0104UL) /**< The length exceeding the end of + the manifest is specified in Length + of the TLV field */ +#define SB_RET_ERR_MANI_INVALID_IMAGE_LEN ((sb_ret_t)0xAAAA0105UL) /**< An invalid image length is set */ +#define SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM ((sb_ret_t)0xAAAA0106UL) /**< There is a wrong combination of + signature algorithms */ +#define SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM ((sb_ret_t)0xAAAA0107UL) /**< An algorithm was specified that + the manifest does not support */ +#define SB_RET_ERR_CRYPTO_FAIL ((sb_ret_t)0xAAAA0200UL) /**< Cryptographic processing failure */ +#define SB_RET_ERR_CRYPTO_AUTH_FAIL ((sb_ret_t)0xAAAA0201UL) /**< Verification failed */ +#define SB_RET_ERR_CRYPTO_UNSUPPORTED_ALGORITHM ((sb_ret_t)0xAAAA0202UL) /**< Unsupported algorithm */ +#define SB_RET_ERR_CRYPTO_RESOURCE_CONFLICT ((sb_ret_t)0xAAAA0203UL) /**< Other resource is using CryptoIP. */ +#define SB_RET_ERR_CRYPTO_PARAM_ERR ((sb_ret_t)0xAAAA0204UL) /**< Parameter error */ +#define SB_RET_ERR_CRC_MISMATCH ((sb_ret_t)0xAAAA0300UL) /**< CRC mismatch */ +#define SB_RET_ERR_LOWER_IMAGE_VERSION ((sb_ret_t)0xAAAA0400UL) /**< Image version lower than the current + image version is installed */ +/*! \}*/ + +/** Manifest size definition */ +/**\addtogroup group_manifest_size Manifest size */ +/*! \{*/ +#define SB_MANIFEST_LEN_MIN (36UL) /**< Minimum manifest length */ +#define SB_MANIFEST_LEN_MAX (10240UL) /**< Maximum manifest length */ +/*! \}*/ + +/** Reserved WORD size definition */ +/**\addtogroup group_unused_area Reserved WORD size */ +/*! \{*/ +#define SB_KEY_CERT_RESERVED_WORD_SIZE (5U) /**< Key Certificate header reserved WORD size */ +/*! \}*/ + +/*===================================================================================================================== + Public type definitions +=====================================================================================================================*/ +/*!********************************************************* + * \addtogroup SBLIBCommonTypes + * \{*******************************************************/ +typedef uint32_t sb_ret_t; /**< SB-Lib return type */ + +/** MAC type value enumeration */ +typedef enum +{ + SB_MAC_TYPE_NONE = 0, /**< Type not used */ + SB_MAC_TYPE_HMAC_SHA2_224, /**< HMAC SHA2-224 */ + SB_MAC_TYPE_HMAC_SHA2_256, /**< HMAC SHA2-256 */ + SB_MAC_TYPE_HMAC_SHA2_384, /**< HMAC SHA2-384 */ + SB_MAC_TYPE_HMAC_SHA2_512, /**< HMAC SHA2-512 */ + SB_MAC_TYPE_HMAC_SHA3_224, /**< HMAC SHA3-224 */ + SB_MAC_TYPE_HMAC_SHA3_256, /**< HMAC SHA3-256 */ + SB_MAC_TYPE_HMAC_SHA3_384, /**< HMAC SHA3-384 */ + SB_MAC_TYPE_HMAC_SHA3_512, /**< HMAC SHA3-512 */ + SB_MAC_TYPE_CMAC_AES_128, /**< CMAC AES-128 */ + SB_MAC_TYPE_CMAC_AES_192, /**< CMAC AES-192 */ + SB_MAC_TYPE_CMAC_AES_256 /**< CMAC AES-256 */ +} e_sb_mac_type_t; + +/*! \}*/ + +/*!********************************************************* + * \addtogroup SBLIBManifestTypes + * \{*******************************************************/ +/** Key Certificate header structure */ +typedef struct +{ + uint32_t magic; /**< Magic number unique to KeyCertificate */ + uint32_t manifest_version; /**< Manifest version */ + uint32_t flags; /**< KeyCertificate flag (Unused in V.1.00) */ + uint32_t reserved[SB_KEY_CERT_RESERVED_WORD_SIZE]; /**< Unused area */ +} st_sb_key_cert_header_t; + +/** Code Certificate header structure */ +typedef struct +{ + uint32_t magic; /**< Magic number unique to CodeCertificate */ + uint32_t manifest_version; /**< Manifest version */ + uint32_t flags; /**< CodeCertificate flag */ + uint32_t load_addr; /**< Image storage address */ + uint32_t dest_addr; /**< Image expansion destination address */ + uint32_t img_len; /**< Image byte size */ + uint32_t img_version; /**< Image version */ + uint32_t build_num; /**< Image build number */ +} st_sb_code_cert_header_t; + +/** TLV type of search result */ +typedef struct +{ + uint32_t type; /**< TLV type */ + uint32_t byte_len; /**< TLV value length */ + const uint32_t * p_val; /**< TLV value field Address */ +} st_sb_tlv_t; + +/** TLV type search condition structure */ +typedef struct +{ + uint32_t type; /**< TLV type to search */ + uint32_t mask; /**< TLV type mask range */ +} st_sb_search_tlv_type_t; + +/** Code Certificate structure */ +typedef struct +{ + const st_sb_code_cert_header_t * p_header; /**< Header information address */ + uint32_t tlv_len; /**< TLV length */ + const uint8_t * p_tlv_top; /**< Start address of TLV field */ +} st_sb_code_cert_t; + +/*! \}*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global functions +=====================================================================================================================*/ + +/********************************************************************************************************************** +* Function Name : R_SB_CheckIntegrity +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBSecureBootAPIs + * \brief Performs image integrity verification using a certificate chain, + * If the verification is successful, generate a MAC for the image and Code Certificate + * \param [in] p_key_cert Specify the start address of Key Certificate \n + * Data must be aligned on 4-byte boundaries + * \param [in] key_cert_len_max Maximum byte length that Key Certificate can take \n + * Don't care when using secure boot with MAC. \n + * [range] #SB_MANIFEST_LEN_MIN - #SB_MANIFEST_LEN_MAX + * \param [in] p_code_cert Specify the start address of Code Certificate \n + * Data must be aligned on 4-byte boundaries + * \param [in] code_cert_len_max Maximum byte length that Code Certificate can take \n + * [range] #SB_MANIFEST_LEN_MIN - #SB_MANIFEST_LEN_MAX + * \param [in] mac_type Output MAC type \n + * \param [out] p_tag Specify MAC tag storage address \n + * Allocate necessary buffer size for the specified type \n + * Data must be aligned on 4-byte boundaries \n + * Values are output in big endian \n + * Specify NULL to not generate MAC + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_SAME_IMAGE_VERSION: The same version of the image has been entered \n + * (Verification and MAC generation completed normally) + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_INVALID_ARG: Invalid argument entered + * - #SB_RET_ERR_UNSUPPORTED_FUNCTION: Unsupported function executed + * - #SB_RET_ERR_INVALID_ALIGNMENT: Data entered with incorrect alignment + * - #SB_RET_ERR_MANI_INVALID_MAGIC: Incorrect magic number set in manifest + * - #SB_RET_ERR_MANI_UNSUPPORTED_VERSION: An unsupported version is set in the manifest + * - #SB_RET_ERR_MANI_OUT_OF_RANGE_LEN: Manifest size out of range + * - #SB_RET_ERR_MANI_TLV_FIELD_ERR: Missing required TLV fields or + * One or more TLV fields for selection are set + * - #SB_RET_ERR_MANI_TLV_INVALID_LEN: The length of the TLV field has a size that exceeds the end of + * the manifest. + * - #SB_RET_ERR_MANI_INVALID_IMAGE_LEN: An invalid image length is set + * - #SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM: There is a wrong combination of signature algorithms + * - #SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM: An algorithm was specified that the manifest does not support + * - #SB_RET_ERR_CRYPTO_FAIL: Encryption failed + * - #SB_RET_ERR_CRYPTO_AUTH_FAIL: Verification failed + * - #SB_RET_ERR_CRYPTO_UNSUPPORTED_ALGORITHM: Unsupported algorithm + * - #SB_RET_ERR_CRYPTO_PARAM_ERR: Parameter error + * - #SB_RET_ERR_LOWER_IMAGE_VERSION: An image version lower than the current image version is installed + * \par Global Variables + * - Image data [in] Binary data of the image to be verified \n + * Data must be aligned on 4-byte boundaries + * \par Call SB-Driver API + * - R_CIP_DRV_PrcDeriveMacKeyFromHuk (This API is actually called by #r_sb_sb_check_integrity) + * - R_CIP_DRV_PrcCheckIntegrity (This API is actually called by #r_sb_sb_check_integrity) + * - R_CIP_DRV_CheckImageVersion (This API is actually called by #r_sb_sb_check_integrity) + * \par Precondition + * - Cryptographic IP initialization is complete. + * - The target boot loader program has been copied to the Dest Addr field of the Code Certificate Header. + * \par Security components + * - yes + * \par Detailed description + * - The TLV field of Key Certificate and Code Certificate referenced by API is described below. + *| Type | Required/Choose/\n Optional| TLV Type(Class) | TLV Type(Use Type)| Description | + *|:---------------|:---------------------------|:----------------|:------------------|:----------------------------------------| + *|Key Certificate |Choose (Use Type) |Key |OEM root public key|Public key for signature verification of Key Certificate \n \ \n Set "OEM root public key" to Use type \n \ \n Set Use type to "Image public key"| + *|^ |^ |^ |Image public key |^ | + *|^ |Required |Hash |Image public key Hash|Hash value of public key for signature verification of Code Certificate| + *|^ |Required |Signature |Key Certificate signature|Signature value calculated for Key Certificate| + *|Code Certificate|Required |Key |Image public key|Public key for signature verification of Code Certificate| + *|^ |Required |Signature |Code Certificate + \n Image Signature|Signature value calculated for Code Certificate and image| + *|^ |Optional |Image Cipher info|Image Encryption/Decryption Information|Image encryption information \n (Required when using Image Cipher and using a key other than the default value)| + *|^ |Optional |IV |Image Cipher IV |IV used in decoding the image \n (Required when Image Cipher info IV select is "IV stored in Code Certificate")| + *|^ |Optional |Image Cipher info|Tenporary Image Decryption Information|Decryption information for temporarily encrypted images \n (Required when using Image Cipher and using a value other than the device default for decryption information)| + *|^ |Optional |IV |Tenporary Image Decryption IV|IV used in decrypting temporarily encrypted images| + * \par + * - Returns an error if the set TLV is in the following cases + * - "Required" TLV is not set + * - "Choose" TLV is not set + * - Two or more "Choose" TLVs are set + * - When multiple TLVs with the same Class and Use type are set, + * use the TLV found earlier when parsing from the beginning of the TLV field. + * - In MAC calculation in MAC generation, input data in the following order + * -# Code Certificate + * -# Image + * - In hash calculation for signature verification of Code Certificate in certificate chain verification, + * input data in the following order + * -# Code Certificate + * -# Image + * - Use a key derived from HUK for MAC verification \n This key is generated by Crypto IP + * - If the encryption process of the image in the Code Certificate \> Header \> Flags field is "1", + * encrypt the image after verifying the certificate chain \n + * In this case, MAC generation is performed on the encrypted image + * - If the decryption processing of the temporarily encrypted image in the + * Code Certificate \> Header \> Flags field is "1", + * decrypt the temporary encrypted image before verifying the certificate chain + * - Integrity verification process is only compiled if build configuration #SB_CFG_CHECK_INTEGRITY is enabled + * - Compare image versions \n + * If the image version stored in the anti-rollback counter is lower than the Image version set + * in the Code Certificate Header, return #SB_RET_ERR_LOWER_IMAGE_VERSION \n + * Returns #SB_RET_SAME_IMAGE_VERSION if they are the same + * + * Pseudo-code for the function can be found below. + * -# --- If #SB_CFG_CHECK_INTEGRITY is enabled --- + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# Set #SB_PRV_FALSE to flow_correct_ret + * -# Set the initial value for the flow counter with #r_sb_cmn_fc_ci_init + * -# If (NULL != p_key_cert) && (NULL != p_code_cert) && (NULL != p_tag) + * -# If (((uintptr_t)p_key_cert & #SB_PRV_REMAINDER_DIV4) == 0UL) && + * (((uintptr_t)p_code_cert & #SB_PRV_REMAINDER_DIV4) == 0UL) && + * (((uintptr_t)p_tag & #SB_PRV_REMAINDER_DIV4) == 0UL) + * -# Set Key cert structure with #r_sb_mani_set_key_cert_st + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set ret to #SB_RET_ERR_INTERNAL_FAIL + * -# Check Key cert with #r_sb_mani_chk_key_cert + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set ret to #SB_RET_ERR_INTERNAL_FAIL + * -# Set code cert structure with #r_sb_mani_set_code_cert_st + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set ret to #SB_RET_ERR_INTERNAL_FAIL + * -# Check code cert with #r_sb_mani_chk_code_cert + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set ret to #SB_RET_ERR_INTERNAL_FAIL + * -# Check Integrity with #r_sb_sb_check_integrity + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Set #SB_RET_ERR_INVALID_ALIGNMENT to ret + * -# Else + * -# Set #SB_RET_ERR_INVALID_ARG to ret + * -# Check if the CheckIntegrity flow is correct using #r_sb_cmn_fc_is_ci_flow_correct + * -# Set function result to flow_correct_ret + * -# If (#SB_RET_SUCCESS == ret) || (#SB_RET_SAME_IMAGE_VERSION == ret) + * -# If #SB_PRV_TRUE == flow_correct_ret + * -# Do nothing + * -# Else + * -# Set #SB_RET_ERR_INTERNAL_FAIL to ret + * -# Else + * -# Do nothing + * -# Return ret + * -# --- Else #SB_CFG_CHECK_INTEGRITY is enabled --- + * -# Return #SB_RET_ERR_UNSUPPORTED_FUNCTION + * -# --- Endif #SB_CFG_CHECK_INTEGRITY is enabled --- + * + * Note: The call graph below dose not include SB-Driver APIs. + * \callgraph + *********************************************************************************************************************/ +extern sb_ret_t R_SB_CheckIntegrity (const uint8_t * const p_key_cert, + const uint32_t key_cert_len_max, + const uint8_t * const p_code_cert, + const uint32_t code_cert_len_max, + const e_sb_mac_type_t mac_type, + uint32_t* const p_tag); + +#endif /* R_SB_API_H */ +/*===================================================================================================================== + End of File +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/inc/r_sb_manifest.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/inc/r_sb_manifest.h new file mode 100644 index 0000000000..529cd692b7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/inc/r_sb_manifest.h @@ -0,0 +1,374 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_manifest.h +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file defines the macros, types, declarations in used the Manifest module. +**********************************************************************************************************************/ + +#ifndef R_SB_MANIFEST_H +/* Multiple inclusion protection macro */ +#define R_SB_MANIFEST_H + +/*===================================================================================================================== + Public macro definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBManifestDefinesInternal + * \{ + * \addtogroup group_manifest_common + * \addtogroup group_codecert_flag + * \addtogroup group_tlv_type_class + * \addtogroup group_tlv_key_usetype + * \addtogroup group_tlv_hash_usetype + * \addtogroup group_tlv_sign_usetype + * \addtogroup group_tlv_sign_hashalgo + * \addtogroup group_tlv_sign_scheme + * \addtogroup group_tlv_mac_usetype + * \addtogroup group_tlv_crc_usetype + * \addtogroup group_tlv_crc_poly + * \addtogroup group_tlv_pc_usetype + * \addtogroup group_tlv_iv_usetype + * \addtogroup group_tlv_ici_usetype + * \addtogroup group_tlv_ici_cipher + * \addtogroup group_tlv_ici_key + * \addtogroup group_tlv_ici_iv + * \addtogroup group_tlv_crypto + * \}*****************************************************************/ +/**\addtogroup group_manifest_common ManifestCommon */ +/*! \{*/ +#define SB_PRV_MANI_HEADER_SIZE (32UL) /**< Manifest header size */ +#define SB_PRV_MANI_TLV_LEN_SIZE (4UL) /**< Manifest TLV length size */ +#define SB_PRV_TLV_TL_SIZE (4UL) /**< TLV Type & Length size */ +/*! \}*/ + +/** Code certificate header */ +/**\addtogroup group_codecert_flag Code Certificate Flag */ +/*! \{*/ +#define SB_PRV_CODE_CERT_HEADER_FLAGS_IMG_CIPHER_ENC (0x00000001UL) /**< Image cipher enable */ +#define SB_PRV_CODE_CERT_HEADER_FLAGS_TMP_IMG_DEC (0x00000002UL) /**< Decrypt temporarily encrypted images enable */ +#define SB_PRV_CODE_CERT_HEADER_FLAGS_SAVE_IMG_PK (0x00000004UL) /**< Save Image PK Hash enable */ +/*! \}*/ + +/** Type Class */ +/**\addtogroup group_tlv_type_class TLV TypeClass */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_POS (28UL) /**< Type Class Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_KEY (0x0UL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Class Key */ +#define SB_PRV_TLV_TYPE_CLS_HASH (0x1UL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Class Hash */ +#define SB_PRV_TLV_TYPE_CLS_SIGN (0x2UL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Class Signature */ +#define SB_PRV_TLV_TYPE_CLS_MAC (0x3UL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Class MAC */ +#define SB_PRV_TLV_TYPE_CLS_CRC (0x4UL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Class CRC */ +#define SB_PRV_TLV_TYPE_CLS_IV (0x5UL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Class IV */ +#define SB_PRV_TLV_TYPE_CLS_PC (0xDUL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Class Product class */ +#define SB_PRV_TLV_TYPE_CLS_ICI (0xEUL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Class Image Cipher info */ +#define SB_PRV_TLV_TYPE_CLS_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_POS)) /**< Type Class full bit */ +#define SB_PRV_TLV_TYPE_CLS_MASK (SB_PRV_TLV_TYPE_CLS_MAX) /**< Type Class mask */ +/*! \}*/ + +/** Use type of KEY class */ +/**\addtogroup group_tlv_key_usetype TLV KEY UseType */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_KEY_UT_POS (24UL) /**< Use Type Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_KEY_UT_OEM_ROOT_PK (0x0UL << (SB_PRV_TLV_TYPE_CLS_KEY_UT_POS)) /**< OEM root public key */ +#define SB_PRV_TLV_TYPE_CLS_KEY_UT_IMG_PK (0x1UL << (SB_PRV_TLV_TYPE_CLS_KEY_UT_POS)) /**< Image public key */ +#define SB_PRV_TLV_TYPE_CLS_KEY_UT_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_KEY_UT_POS)) /**< Use Type full bit */ +#define SB_PRV_TLV_TYPE_CLS_KEY_UT_MASK (SB_PRV_TLV_TYPE_CLS_KEY_UT_MAX) /**< Use Type mask */ +/*! \}*/ + +/** Use type of HASH class */ +/**\addtogroup group_tlv_hash_usetype TLV HASH UseType */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_HASH_UT_POS (24UL) /**< Use Type Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_HASH_UT_IMG_PK (0x0UL << (SB_PRV_TLV_TYPE_CLS_HASH_UT_POS)) /**< Image public key Hash */ +#define SB_PRV_TLV_TYPE_CLS_HASH_UT_IMG (0x1UL << (SB_PRV_TLV_TYPE_CLS_HASH_UT_POS)) /**< Image Hash */ +#define SB_PRV_TLV_TYPE_CLS_HASH_UT_ENCIMG (0x2UL << (SB_PRV_TLV_TYPE_CLS_HASH_UT_POS)) /**< Encrypt Image Hash */ +#define SB_PRV_TLV_TYPE_CLS_HASH_UT_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_HASH_UT_POS)) /**< Use Type full bit */ +#define SB_PRV_TLV_TYPE_CLS_HASH_UT_MASK (SB_PRV_TLV_TYPE_CLS_HASH_UT_MAX) /**< Use Type mask */ +/*! \}*/ + +/** Use type of Signature class */ +/**\addtogroup group_tlv_sign_usetype TLV SIGN UseType */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_SIGN_UT_POS (24UL) /**< Use Type Bit Position */ +/** Certificate Signature */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_UT_CERT (0x0UL << (SB_PRV_TLV_TYPE_CLS_SIGN_UT_POS)) +/** Code Certificate + Image Signature */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_UT_CODE_CERT_AND_IMG (0x5UL << (SB_PRV_TLV_TYPE_CLS_SIGN_UT_POS)) +/** Code Certificate + Encrypted Image Signature */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_UT_CODE_CERT_AND_ENCIMG (0x6UL << (SB_PRV_TLV_TYPE_CLS_SIGN_UT_POS)) +/** Use Type full bit */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_UT_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_SIGN_UT_POS)) +#define SB_PRV_TLV_TYPE_CLS_SIGN_UT_MASK (SB_PRV_TLV_TYPE_CLS_SIGN_UT_MAX) /**< Use Type mask */ +/*! \}*/ + +/** Hash Algorithm of Signature class */ +/**\addtogroup group_tlv_sign_hashalgo TLV SIGN HashAlgorithm */ +/*! \{*/ +/**< Hash Algorithm Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS (10UL) +/** SHA2-224 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_224 (0x0UL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** SHA2-256 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_256 (0x1UL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** SHA2-384 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_384 (0x2UL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** SHA2-512 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_512 (0x3UL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** SHA3-224 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_224 (0x4UL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** SHA3-256 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_256 (0x5UL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** SHA3-384 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_384 (0x6UL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** SHA3-512 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_512 (0x7UL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** Hash Algorithm full bit */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_POS)) +/** Hash Algorithm mask */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_MASK (SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_MAX) +/*! \}*/ + +/** Scheme of Signature class */ +/**\addtogroup group_tlv_sign_scheme TLV SIGN Scheme */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_POS (8UL) /**< Scheme Bit Position */ +/** RSASSA-PKCS1_v1_5 */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_RSASSA_PKCS1_V1_5 (0x0UL << (SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_POS)) +/** RSASSA-PSS */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_RSASSA_PSS (0x1UL << (SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_POS)) +/** Scheme full bit */ +#define SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_MAX (0x3UL << (SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_POS)) +#define SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_MASK (SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_MAX) /**< Scheme mask */ +/*! \}*/ + +/** Use type of MAC class */ +/**\addtogroup group_tlv_mac_usetype TLV MAC UseType */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_MAC_UT_POS (24UL) /**< Use Type Bit Position */ +/** Code Certificate + Image MAC */ +#define SB_PRV_TLV_TYPE_CLS_MAC_UT_CODE_CERT_AND_IMG (0x0UL << (SB_PRV_TLV_TYPE_CLS_MAC_UT_POS)) +/** Code Certificate + Encrypted Image MAC */ +#define SB_PRV_TLV_TYPE_CLS_MAC_UT_CODE_CERT_AND_ENCIMG (0x1UL << (SB_PRV_TLV_TYPE_CLS_MAC_UT_POS)) +/** Use Type full bit */ +#define SB_PRV_TLV_TYPE_CLS_MAC_UT_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_MAC_UT_POS)) +#define SB_PRV_TLV_TYPE_CLS_MAC_UT_MASK (SB_PRV_TLV_TYPE_CLS_MAC_UT_MAX) /**< Use Type mask */ +/*! \}*/ + +/** Use type of CRC class */ +/**\addtogroup group_tlv_crc_usetype TLV CRC UseType */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_CRC_UT_POS (24UL) /**< Use Type Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_CRC_UT_IMG (0x0UL << (SB_PRV_TLV_TYPE_CLS_CRC_UT_POS)) /**< Image CRC */ +#define SB_PRV_TLV_TYPE_CLS_CRC_UT_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_CRC_UT_POS)) /**< Use Type full bit */ +#define SB_PRV_TLV_TYPE_CLS_CRC_UT_MASK (SB_PRV_TLV_TYPE_CLS_CRC_UT_MAX) /**< Use Type mask */ +/*! \}*/ + +/** Polynomial of CRC class */ +/**\addtogroup group_tlv_crc_poly TLV CRC Polynomial */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_CRC_POLY_POS (20UL) /**< Polynomial Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_CRC_POLY_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_CRC_POLY_POS)) /**< Polynomial full bit */ +#define SB_PRV_TLV_TYPE_CLS_CRC_POLY_MASK (SB_PRV_TLV_TYPE_CLS_CRC_POLY_MAX) /**< Polynomial mask */ +/*! \}*/ + +/** Use type of Product Class(PC) class */ +/**\addtogroup group_tlv_pc_usetype TLV Product Class UseType */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_PC_UT_POS (24UL) /**< Use Type Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_PC_UT_VENDER_ID (0x0UL << (SB_PRV_TLV_TYPE_CLS_PC_UT_POS)) /**< Vender ID */ +#define SB_PRV_TLV_TYPE_CLS_PC_UT_PRODUCT_ID (0x1UL << (SB_PRV_TLV_TYPE_CLS_PC_UT_POS)) /**< Product ID */ +#define SB_PRV_TLV_TYPE_CLS_PC_UT_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_PC_UT_POS)) /**< Use Type full bit */ +#define SB_PRV_TLV_TYPE_CLS_PC_UT_MASK (SB_PRV_TLV_TYPE_CLS_PC_UT_MAX) /**< Use Type mask */ +/*! \}*/ + +/** Use type of IV class */ +/**\addtogroup group_tlv_iv_usetype TLV IV UseType */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_IV_UT_POS (24UL) /**< Use Type Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_IV_UT_IMG_CIPHER (0x0UL << (SB_PRV_TLV_TYPE_CLS_IV_UT_POS)) /**< Image Cipher IV */ +#define SB_PRV_TLV_TYPE_CLS_IV_UT_TMP_IMG_DEC (0x1UL << (SB_PRV_TLV_TYPE_CLS_IV_UT_POS)) /**< Temporary + Image Cipher IV */ +#define SB_PRV_TLV_TYPE_CLS_IV_UT_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_IV_UT_POS)) /**< Use Type full bit */ +#define SB_PRV_TLV_TYPE_CLS_IV_UT_MASK (SB_PRV_TLV_TYPE_CLS_IV_UT_MAX) /**< Use Type mask */ +/*! \}*/ + +/** Use type of Image Cipher Info(ICI) class */ +/**\addtogroup group_tlv_ici_usetype TLV Image Cipher Info UseType */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_ICI_UT_POS (24UL) /**< Use Type Bit Position */ +/** Image Encryption/Decryption Information */ +#define SB_PRV_TLV_TYPE_CLS_ICI_UT_IMG_ENC_DEC (0x0UL << (SB_PRV_TLV_TYPE_CLS_ICI_UT_POS)) +/** Temporary Image Decryption Information */ +#define SB_PRV_TLV_TYPE_CLS_ICI_UT_TMP_IMG_DEC (0x1UL << (SB_PRV_TLV_TYPE_CLS_ICI_UT_POS)) +#define SB_PRV_TLV_TYPE_CLS_ICI_UT_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_ICI_UT_POS)) /**< Use Type full bit */ +#define SB_PRV_TLV_TYPE_CLS_ICI_UT_MASK (SB_PRV_TLV_TYPE_CLS_ICI_UT_MAX) /**< Use Type mask */ +/*! \}*/ + +/** Cipher mode of Image Cipher Info(ICI) class */ +/**\addtogroup group_tlv_ici_cipher TLV Image Cipher Info CipherMode */ +/*! \{*/ +#define SB_PRV_TLV_TYPE_CLS_ICI_MODE_POS (10UL) /**< Cipher mode Bit Position */ +#define SB_PRV_TLV_TYPE_CLS_ICI_MODE_ECB (0x0UL << (SB_PRV_TLV_TYPE_CLS_ICI_MODE_POS)) /**< Mode ECB */ +#define SB_PRV_TLV_TYPE_CLS_ICI_MODE_CBC (0x1UL << (SB_PRV_TLV_TYPE_CLS_ICI_MODE_POS)) /**< Mode CBC */ +#define SB_PRV_TLV_TYPE_CLS_ICI_MODE_CFB (0x2UL << (SB_PRV_TLV_TYPE_CLS_ICI_MODE_POS)) /**< Mode CFB */ +#define SB_PRV_TLV_TYPE_CLS_ICI_MODE_OFB (0x3UL << (SB_PRV_TLV_TYPE_CLS_ICI_MODE_POS)) /**< Mode OFB */ +#define SB_PRV_TLV_TYPE_CLS_ICI_MODE_CTR (0x4UL << (SB_PRV_TLV_TYPE_CLS_ICI_MODE_POS)) /**< Mode CTR */ +#define SB_PRV_TLV_TYPE_CLS_ICI_MODE_MAX (0xFUL << (SB_PRV_TLV_TYPE_CLS_ICI_MODE_POS)) /**< Cipher mode full bit */ +#define SB_PRV_TLV_TYPE_CLS_ICI_MODE_MASK (SB_PRV_TLV_TYPE_CLS_ICI_MODE_MAX) /**< Cipher mode mask */ +/*! \}*/ + +/** Key Select of Image Cipher Info(ICI) class value */ +/**\addtogroup group_tlv_ici_key TLV Image Cipher Info KeySelect */ +/*! \{*/ +#define SB_PRV_TLV_VALUE_ICI_KEY_SEL_DEAULT (0x00000000UL) /**< Device Default key */ +#define SB_PRV_TLV_VALUE_ICI_KEY_SEL_DEV_UNIQUE (0x00010000UL) /**< Device Unique key */ +#define SB_PRV_TLV_VALUE_ICI_KEY_SEL_INSTALLED (0x00020000UL) /**< Installed key */ +/*! \}*/ + +/** IV Select of Image Cipher Info(ICI) class value */ +/**\addtogroup group_tlv_ici_iv TLV Image Cipher Info IVSelect */ +/*! \{*/ +#define SB_PRV_TLV_VALUE_ICI_IV_SEL_DEAULT (0x00000000UL) /**< Device Default IV */ +#define SB_PRV_TLV_VALUE_ICI_IV_SEL_DEV_UNIQUE (0x00010000UL) /**< Device Unique IV */ +#define SB_PRV_TLV_VALUE_ICI_IV_SEL_INSTALLED (0x00020000UL) /**< Installed IV */ +#define SB_PRV_TLV_VALUE_ICI_IV_SEL_STORED_CODE_CERT (0x00030000UL) /**< Use IV stored in code certificate */ +/*! \}*/ + +/** Cryptographic algorithm */ +/**\addtogroup group_tlv_crypto TLV CryptoAlgorithm */ +/*! \{*/ +/** Cryptographic Algorithm Bit Position */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS (14UL) +/** AES-128 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES128 (0x0000UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** AES-192 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES192 (0x0001UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** AES-256 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES256 (0x0002UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** RSA 1024 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA1024 (0x0010UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** RSA 2048 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA2048 (0x0011UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** RSA 3072 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA3072 (0x0012UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** RSA 4096 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA4096 (0x0013UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC NIST P-192 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P192 (0x0020UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC NIST P-224 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P224 (0x0021UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC NIST P-256 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P256 (0x0022UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC NIST P-384 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P384 (0x0023UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC NIST P-521 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P521 (0x0024UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC BrainpoolP192 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP192R1 (0x0030UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC BrainpoolP224 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP224R1 (0x0031UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC BrainpoolP256 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP256R1 (0x0032UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC BrainpoolP384 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP384R1 (0x0033UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** ECC BrainpoolP512 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP512R1 (0x0034UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** Curve25519 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_CURVE25519 (0x0040UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** Curve448 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_CURVE448 (0x0041UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** SHA2-224 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_224 (0x0050UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** SHA2-256 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_256 (0x0051UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** SHA2-384 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_384 (0x0052UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** SHA2-512 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_512 (0x0053UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** SHA3-224 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_224 (0x0054UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** SHA3-256 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_256 (0x0055UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** SHA3-384 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_384 (0x0056UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** SHA3-512 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_512 (0x0057UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** HMAC SHA2-224 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_HMAC_SHA2_224 (0x0060UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** HMAC SHA2-256 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_HMAC_SHA2_256 (0x0061UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** HMAC SHA2-384 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_HMAC_SHA2_384 (0x0062UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** HMAC SHA2-512 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_HMAC_SHA2_512 (0x0063UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** HMAC SHA3-224 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_HMAC_SHA3_224 (0x0064UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** HMAC SHA3-256 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_HMAC_SHA3_256 (0x0065UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** HMAC SHA3-384 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_HMAC_SHA3_384 (0x0066UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** HMAC SHA3-512 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_HMAC_SHA3_512 (0x0067UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** CMAC AES-128 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_CMAC_AES128 (0x0070UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** CMAC AES-192 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_CMAC_AES192 (0x0071UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** CMAC AES-256 */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_CMAC_AES256 (0x0072UL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** Algorithm full bit */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_MAX (0x03FFUL << (SB_PRV_TLV_TYPE_CRYPTO_ALGO_POS)) +/** Algorithm mask */ +#define SB_PRV_TLV_TYPE_CRYPTO_ALGO_MASK (SB_PRV_TLV_TYPE_CRYPTO_ALGO_MAX) +/*! \}*/ + +/*===================================================================================================================== + Public type definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBManifestTypesInternal + * \{******************************************************************/ +/** Key Certificate structure */ +typedef struct +{ + const st_sb_key_cert_header_t * p_header; /**< Header information address */ + uint32_t tlv_len; /**< TLV length */ + const uint8_t * p_tlv_top; /**< Start address of TLV field */ +} st_sb_key_cert_t; + +/** Image Cipher Info value structure */ +typedef struct +{ + uint32_t key_sel; /**< Specify the key used for encrypting / decrypting images */ + uint32_t iv_sel; /**< Specify the IV to be used for image encryption / decryption */ + uint32_t dest_addr; /**< Image output destination address after decryption */ +} st_sb_img_cip_info_val_t; +/*! \}*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global functions +=====================================================================================================================*/ +extern sb_ret_t r_sb_mani_set_key_cert_st (const uint8_t * const p_key_cert, st_sb_key_cert_t * const p_key_cert_st); +extern sb_ret_t r_sb_mani_set_code_cert_st (const uint8_t * const p_code_cert, + st_sb_code_cert_t * const p_code_cert_st); +extern sb_ret_t r_sb_mani_chk_key_cert (const st_sb_key_cert_t * const p_key_cert_st, const uint32_t key_cert_len_max); +extern sb_ret_t r_sb_mani_chk_code_cert (const st_sb_code_cert_t * const p_code_cert_st, + const uint32_t code_cert_len_max); +extern sb_ret_t r_sb_mani_parse_tlvs (const uint8_t * const p_top, const uint32_t tlv_len, + const uint32_t num_of_search_type, + const st_sb_search_tlv_type_t * const p_search_types, st_sb_tlv_t * const p_tlvs); + +#endif /* R_SB_MANIFEST_H */ +/*===================================================================================================================== + End of File +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_api.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_api.c new file mode 100644 index 0000000000..17a1027369 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_api.c @@ -0,0 +1,204 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_api.c +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file implements the SB-Lib public APIs. +**********************************************************************************************************************/ + +/*===================================================================================================================== + Includes , "Project Includes" +=====================================================================================================================*/ +#include +#include "r_sb_api.h" +#include "r_sb_build_config.h" +#include "r_sb_cmn.h" +#include "r_sb_manifest.h" +#include "r_sb_sb.h" + +/*===================================================================================================================== + Private macro definitions +=====================================================================================================================*/ +/* Error checking needs to be done where the settings are used, not in a configuration file. */ +#if (SB_CFG_PARAM_CHECKING_ENABLE == 1U) + #if (0U != SB_CFG_SB_MAC_VERIFICATION) && (1U != SB_CFG_SB_MAC_VERIFICATION) + #error This is an error check from the build configuration. Cause: SB_CFG_SB_MAC_VERIFICATION + #endif + #if (0U != SB_CFG_SB_CERT_CHAIN_VERIFICATION) && (1U != SB_CFG_SB_CERT_CHAIN_VERIFICATION) + #error This is an error check from the build configuration. Cause: SB_CFG_SB_CERT_CHAIN_VERIFICATION + #endif + #if (0U != SB_CFG_SB_CERT_CHAIN_USE_IMG_PK) && (1U != SB_CFG_SB_CERT_CHAIN_USE_IMG_PK) + #error This is an error check from the build configuration. Cause: SB_CFG_SB_CERT_CHAIN_USE_IMG_PK + #endif + #if (0U != SB_CFG_IMAGE_ENC_DEC) && (1U != SB_CFG_IMAGE_ENC_DEC) + #error This is an error check from the build configuration. Cause: SB_CFG_IMAGE_ENC_DEC + #endif + #if (0U != SB_CFG_CHECK_CRC) && (1U != SB_CFG_CHECK_CRC) + #error This is an error check from the build configuration. Cause: SB_CFG_CHECK_CRC + #endif + #if (0U != SB_CFG_CHECK_INTEGRITY) && (1U != SB_CFG_CHECK_INTEGRITY) + #error This is an error check from the build configuration. Cause: SB_CFG_CHECK_INTEGRITY + #endif +#endif + +/*===================================================================================================================== + Private type definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Private global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Private function prototypes +=====================================================================================================================*/ + +/*===================================================================================================================== + Public function definitions +=====================================================================================================================*/ + +/********************************************************************************************************************** +* Function Name : R_SB_CheckIntegrity +**********************************************************************************************************************/ +sb_ret_t R_SB_CheckIntegrity(const uint8_t* const p_key_cert, const uint32_t key_cert_len_max, + const uint8_t* const p_code_cert, const uint32_t code_cert_len_max, + const e_sb_mac_type_t mac_type, uint32_t* const p_tag) +{ +#if (SB_CFG_CHECK_INTEGRITY == 1U) + /*----------------------------------------------------------------------------------------------------------------- + Local variables + -----------------------------------------------------------------------------------------------------------------*/ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + sb_bool_t flow_correct_ret = SB_PRV_FALSE; + st_sb_key_cert_t key_cert_st; + st_sb_code_cert_t code_cert_st; + + /*----------------------------------------------------------------------------------------------------------------- + Function body + -----------------------------------------------------------------------------------------------------------------*/ + /* Initialize flow counter */ + r_sb_cmn_fc_ci_init(); + + /* Check NULL argument excepted mac_tlv */ + if ((NULL != p_key_cert) && (NULL != p_code_cert) && (NULL != p_tag)) + { + /* Check alignment */ + /* No problem with casting to pointer size */ + if ((((uintptr_t)p_key_cert & (uintptr_t)SB_PRV_REMAINDER_DIV4) == (uintptr_t)0UL) && + (((uintptr_t)p_code_cert & (uintptr_t)SB_PRV_REMAINDER_DIV4) == (uintptr_t)0UL) && /* Same cast as above */ + (((uintptr_t)p_tag & (uintptr_t)SB_PRV_REMAINDER_DIV4) == (uintptr_t)0UL)) /* Same cast as above */ + { + /* Set Key cert structure */ + ret = r_sb_mani_set_key_cert_st(p_key_cert, &key_cert_st); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Check key cert */ + ret = r_sb_mani_chk_key_cert(&key_cert_st, key_cert_len_max); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Set Code cert structure */ + ret = r_sb_mani_set_code_cert_st(p_code_cert, &code_cert_st); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Check code cert */ + ret = r_sb_mani_chk_code_cert(&code_cert_st, code_cert_len_max); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Verifies the image integrity with a certificate chain and generate MAC */ + ret = r_sb_sb_check_integrity(&key_cert_st, &code_cert_st, mac_type, p_tag); + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing. */ + } + } + else + { + /* Invalid alignment */ + ret = SB_RET_ERR_INVALID_ALIGNMENT; + } + } + else + { + /* Invalid argument */ + ret = SB_RET_ERR_INVALID_ARG; + } + + /* Verify flow counter */ + flow_correct_ret = r_sb_cmn_fc_is_ci_flow_correct(); + if ((SB_RET_SUCCESS == ret) || (SB_RET_SAME_IMAGE_VERSION == ret)) + { + if (SB_PRV_TRUE == flow_correct_ret) + { + /* Do nothing */ + } + else + { + /* Flow counter mismatch */ + ret = SB_RET_ERR_INTERNAL_FAIL; + } + } + else + { + /* Do nothing */ + } + + return ret; +#else /* (SB_CFG_CHECK_INTEGRITY == 1U) */ + return SB_RET_ERR_UNSUPPORTED_FUNCTION; +#endif /* (SB_CFG_CHECK_INTEGRITY == 1U) */ +} +/********************************************************************************************************************** +* End of function R_SB_CheckIntegrity() +**********************************************************************************************************************/ + +/*===================================================================================================================== + Private function definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + End of file +=====================================================================================================================*/ + diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_build_config.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_build_config.h new file mode 100644 index 0000000000..96412b2699 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_build_config.h @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_build_config.h +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file defines macros for build configuration. +**********************************************************************************************************************/ +#ifndef R_SB_BUILD_CONFIG_H +/* Multiple inclusion protection macro */ +#define R_SB_BUILD_CONFIG_H + +/*!*********************************************************** + * \addtogroup SBLIBBC + * \{ + * \addtogroup SBLIBBCDefines BuildConfiguration Definitions + * \}********************************************************/ + +/*===================================================================================================================== + Public macro definitions +=====================================================================================================================*/ +/*!********************************************************* + * \addtogroup SBLIBBCDefines + * \{*******************************************************/ +/** Select whether to check the setting value of the build configuration \n + - 1: This config is valid + - 0: This config is invalid */ +#define SB_CFG_PARAM_CHECKING_ENABLE (0U) + +/** Select whether to enable or disable Secure Boot function by Mac verification \n + - 1: This config is valid + - 0: This config is invalid */ +#define SB_CFG_SB_MAC_VERIFICATION (1U) + +/** Select whether to enable or disable Secure Boot function by Certificate chain verification \n + - 1: This config is valid + - 0: This config is invalid */ +#define SB_CFG_SB_CERT_CHAIN_VERIFICATION (0U) + +/** Select whether to enable or disable Certificate chain verification using the IMG PK of the previous stage \n + - 1: This config is valid + - 0: This config is invalid */ +#define SB_CFG_SB_CERT_CHAIN_USE_IMG_PK (0U) + +/** Select whether to enable or disable Image Encryption / Decryption function + and Tenporary Encrypted Image Decryption function \n + - 1: This config is valid + - 0: This config is invalid */ +#define SB_CFG_IMAGE_ENC_DEC (0U) + +/** Select whether to enable or disable CRC check function \n + - 1: This config is valid + - 0: This config is invalid */ +#define SB_CFG_CHECK_CRC (1U) + +/** Select whether to enable or disable Integrity check function that use in Flash programmer stage \n + - 1: This config is valid + - 0: This config is invalid */ +#define SB_CFG_CHECK_INTEGRITY (1U) + +/*! \}*/ + +/*===================================================================================================================== + Public type definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global functions +=====================================================================================================================*/ + +#endif /* R_SB_BUILD_CONFIG_H */ +/*===================================================================================================================== + End of File +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn.c new file mode 100644 index 0000000000..884ab5a1ba --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn.c @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_cmn.c +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file implements common APIs for the SB-Lib. +**********************************************************************************************************************/ + +/*===================================================================================================================== + Includes , "Project Includes" +=====================================================================================================================*/ +#include +#include +#include "r_sb_cmn.h" + +/*===================================================================================================================== + Private macro definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Private type definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ +/** Global variables used for flow verification */ +/*!******************************************************************** + * \addtogroup SBLIBCommonVariablesInternal + * \{******************************************************************/ +volatile uint32_t g_sb_flow_counter; /**< A variable that stores the count value for flow verification */ +/*! \}*/ + +/*===================================================================================================================== + Private global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Private function prototypes +=====================================================================================================================*/ + +/*===================================================================================================================== + Public function definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Private function definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + End of file +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn.h new file mode 100644 index 0000000000..f2472d8a7e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn.h @@ -0,0 +1,166 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_cmn.h +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file defines the common macros, types and declarations for SB-Lib. +***********************************************************************************************************************/ + +#ifndef R_SB_CMN_H +/* Multiple inclusion protection macro */ +#define R_SB_CMN_H + +/*===================================================================================================================== + Public macro definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBCommonDefinesInternal + * \{******************************************************************/ +#define SB_PRV_VERSION_MAJOR (1UL) /**< SB Library Major version */ +#define SB_PRV_VERSION_MINOR (0UL) /**< SB Library Minor version */ + +/** Secure Boot function Flow verification counter Initial value */ +#define SB_PRV_CMN_FC_SECUREBOOT_INIT (0xEB536A03UL) +/** Count value for Secure Boot function flow verification */ +#define SB_PRV_CMN_FC_SECUREBOOT_CNT (0xB65FC3UL) +/** Number of times the Secure Boot function Flow verification count is add */ +#define SB_PRV_CMN_FC_SECUREBOOT_NUM (5UL) +/** Total add value of Secure Boot function flow verification count value */ +#define SB_PRV_CMN_FC_SECUREBOOT_TOTAL_CNT ((SB_PRV_CMN_FC_SECUREBOOT_CNT)*(SB_PRV_CMN_FC_SECUREBOOT_NUM)) + +/** CheckIntegrity function Flow verification counter Initial value */ +#define SB_PRV_CMN_FC_CHECKINTEGRITY_INIT (0xB5270907UL) +/** Count value for CheckIntegrity function flow verification */ +#define SB_PRV_CMN_FC_CHECKINTEGRITY_CNT (0xF29113UL) +/** Number of times the CheckIntegrity function Flow verification count is add */ +#define SB_PRV_CMN_FC_CHECKINTEGRITY_NUM (2UL) +/** Total add value of CheckIntegrity function flow verification count value */ +#define SB_PRV_CMN_FC_CHECKINTEGRITY_TOTAL_CNT ((SB_PRV_CMN_FC_CHECKINTEGRITY_CNT)*(SB_PRV_CMN_FC_CHECKINTEGRITY_NUM)) + +#define SB_PRV_REMAINDER_DIV4 (0x3UL) /**< Remainder of divided by 4 */ +#define SB_PRV_REMAINDER_DIV16 (0xFUL) /**< Remainder of divided by 16 */ + +#define SB_PRV_TRUE ((sb_bool_t)0x55555555UL) /**< True value. Defines a value other than 0/1 to prevent glitches */ +#define SB_PRV_FALSE ((sb_bool_t)0xAAAAAAAAUL) /**< False value. Defines a value other than 0/1 to prevent glitches */ +/*! \}*/ + + +/*===================================================================================================================== + Public type definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBCommonTypesInternal + * \{******************************************************************/ +typedef uint32_t sb_bool_t; /**< SB-Lib Boolean type */ +/*! \}*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ +extern volatile uint32_t g_sb_flow_counter; + +/*===================================================================================================================== + Public global functions +=====================================================================================================================*/ +/********************************************************************************************************************** +* Function Name : r_sb_cmn_fc_sb_init +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Initialize SecureBoot flow counter \n + * This function is an inline function + * \return + * - None + * \par Global Variables + * - #g_sb_flow_counter + * + * \callgraph + *********************************************************************************************************************/ +static inline void r_sb_cmn_fc_sb_init(void) +{ + g_sb_flow_counter = SB_PRV_CMN_FC_SECUREBOOT_INIT; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_fc_sb_init() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_cmn_fc_ci_init +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Initialize CheckIntegrity flow counter \n + * This function is an inline function + * \return + * - None + * \par Global Variables + * - #g_sb_flow_counter + * + * \callgraph + *********************************************************************************************************************/ +static inline void r_sb_cmn_fc_ci_init(void) +{ + g_sb_flow_counter = SB_PRV_CMN_FC_CHECKINTEGRITY_INIT; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_fc_ci_init() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_cmn_fc_is_ci_flow_correct +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Check if the CheckIntegrity flow is correct \n + * This function is an inline function + * \return + * - SB_PRV_TRUE: (#SB_PRV_CMN_FC_CHECKINTEGRITY_INIT + #SB_PRV_CMN_FC_CHECKINTEGRITY_TOTAL_CNT) == #g_sb_flow_counter + * - SB_PRV_FALSE:(#SB_PRV_CMN_FC_CHECKINTEGRITY_INIT + #SB_PRV_CMN_FC_CHECKINTEGRITY_TOTAL_CNT) != #g_sb_flow_counter + * \par Global Variables + * - #g_sb_flow_counter + * + * \callgraph + *********************************************************************************************************************/ +static inline sb_bool_t r_sb_cmn_fc_is_ci_flow_correct(void) +{ + const uint32_t flow_counter = g_sb_flow_counter; + return ((SB_PRV_CMN_FC_CHECKINTEGRITY_INIT + SB_PRV_CMN_FC_CHECKINTEGRITY_TOTAL_CNT) == flow_counter) ? + SB_PRV_TRUE : SB_PRV_FALSE; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_fc_is_ci_flow_correct() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_cmn_fc_add_counter +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Add flow counter \n + * This function is an inline function + * \param [in] cnt Flow counter value to be added + * \return + * - None + * \par Global Variables + * - #g_sb_flow_counter + * + * \callgraph + *********************************************************************************************************************/ +static inline void r_sb_cmn_fc_add_counter(const uint32_t cnt) +{ + g_sb_flow_counter += cnt; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_fc_add_counter() +**********************************************************************************************************************/ + +#endif /* R_SB_CMN_H */ +/*===================================================================================================================== + End of File +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn_drv.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn_drv.c new file mode 100644 index 0000000000..c76fb2e37f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn_drv.c @@ -0,0 +1,1340 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_cmn_drv.c +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file implements common APIs for the CIP(CryptoIP) driver. +**********************************************************************************************************************/ + +/*!*********************************************************** + * \addtogroup SBLIBCommon + * \{ + * \addtogroup SBLIBCommonDefines Common Definitions + * \addtogroup SBLIBCommonTypes Common Types + * \addtogroup SBLIBCommonAPIs Common APIs + * \addtogroup SBLIBCommonDefinesInternal Common Internal Definitions + * \addtogroup SBLIBCommonTypesInternal Common Internal Types + * \addtogroup SBLIBCommonVariablesInternal Common Internal Variables + * \addtogroup SBLIBCommonAPIsInternal Common Internal APIs + * \}********************************************************/ + +/*===================================================================================================================== + Includes , "Project Includes" +=====================================================================================================================*/ +#include +#include "r_cip_drv_api.h" +#include "r_sb_build_config.h" +#include "r_sb_api.h" +#include "r_sb_cmn.h" +#include "r_sb_manifest.h" +#include "r_sb_cmn_drv.h" + +/*===================================================================================================================== + Private macro definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBCommonDefinesInternal + * \{******************************************************************/ +#define SB_PRV_RET_UPPER_MASK (0xFFFF0000UL) /**< Mask the upper 16 bits of the return value */ +#define SB_PRV_RET_LOWER_MASK (0x0000FFFFUL) /**< Mask the lower 16 bits of the return value */ +#define SB_PRV_RET_ERROR_BITS (0xAAAA0000UL) /**< Bits of error return value */ + +#define SB_PRV_RET_UNSUPPORTED_ALGO (0xFFFFFFFFUL) /**< Unsupported algorithm specified */ +/*! \}*/ + +/*===================================================================================================================== + Private type definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBCommonTypesInternal + * \{******************************************************************/ +/*! \}*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBCommonVariablesInternal + * \{******************************************************************/ + +/*! \}*/ + +/*===================================================================================================================== + Private global variables +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBCommonVariablesInternal + * \{******************************************************************/ + +/*! \}*/ + +/*===================================================================================================================== + Private function prototypes +=====================================================================================================================*/ +static uint32_t cmn_drv_get_hash_algo (const uint32_t type); +static uint32_t cmn_drv_get_sign_hash_algo (const uint32_t type); +static uint32_t cmn_drv_get_sign_algo (const uint32_t type); +static uint32_t cmn_drv_get_sign_scheme (const uint32_t type, const uint32_t sign_algo); +static uint32_t cmn_drv_get_img_cip_info_algo (const uint32_t type); +static uint32_t cmn_drv_get_img_cip_info_mode (const uint32_t type); + +/*===================================================================================================================== + Public function definitions +=====================================================================================================================*/ +/********************************************************************************************************************** +* Function Name : r_sb_cmn_drv_set_cc_key_cert_param +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Setting key certificate parameter with in Certificate Chain verification + * \param [in] p_key_cert_st Start address of Key Certificate Structure + * \param [in] p_img_pk_hash_tlv Start address of Image public key hash TLV + * \param [in] p_sign_pk_tlv Start address of Signature public key TLV + * \param [in] p_sign_tlv Start address of Signature TLV + * \param [out] p_cc_key_cert_param Starting address of the structure for setting the + * key certificate parameters used in the certificate chain + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM: There is a wrong combination of signature algorithms + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Convert Manifest information to SB-Driver definition and set it in parameter structure given as argument + * - This parameter is used in the following SB-Driver API + * - R_CIP_DRV_PrcVerifyCertChain + * - R_CIP_DRV_PrcCheckIntegrity + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_key_cert_st) && (NULL != p_img_pk_hash_tlv) && (NULL != p_sign_pk_tlv) && + * (NULL != p_sign_tlv) && (NULL != p_cc_key_cert_param) + * -# Get Signature public key algorithm with #cmn_drv_get_sign_algo and set to key_algo + * -# If (p_sign_pk_tlv->type & #SB_PRV_TLV_TYPE_CLS_SIGN_UT_MASK) == #SB_PRV_TLV_TYPE_CLS_KEY_UT_OEM_ROOT_PK + * -# Set p_cc_key_cert_param->key_cert_pk_cmp_src to CIP_DRV_KEY_CERT_PK_CMP_SRC_ROT + * -# Else + * -# Set p_cc_key_cert_param->key_cert_pk_cmp_src to CIP_DRV_KEY_CERT_PK_CMP_SRC_IMG_PK + * -# Get hash algorithm with #cmn_drv_get_hash_algo + * -# Set p_cc_key_cert_param->img_pk_hash_algo to function result + * -# Cast the p_img_pk_hash_tlv->p_val to uint32_t* type and set it to p_cc_key_cert_param->p_img_pk_hash + * -# Set p_cc_key_cert_param->img_pk_hash_len to p_img_pk_hash_tlv->byte_len + * -# Get sign algorithm with #cmn_drv_get_sign_algo + * -# Set p_cc_key_cert_param->sign_algo to function result + * -# Get sign hash algorithm with #cmn_drv_get_sign_hash_algo + * -# Set p_cc_key_cert_param->sign_hash_algo to function result + * -# Get sign scheme with #cmn_drv_get_sign_scheme + * -# Set p_cc_key_cert_param->sign_scheme to function result + * -# Cast the p_sign_pk_tlv->p_val to uint32_t* type and set it to p_cc_key_cert_param->p_sign_pk + * -# Set p_cc_key_cert_param->sign_pk_len to p_sign_pk_tlv->byte_len + * -# Cast the p_sign_tlv->p_val to uint32_t* type and set it to p_cc_key_cert_param->p_sign + * -# Set p_cc_key_cert_param->sign_len to p_sign_tlv->byte_len + * -# Cast the p_key_cert_st->p_header to uint32_t* type and set it to p_cc_key_cert_param->p_key_cert + * -# Calculate the signing target size of the key certificate and set it to p_cc_key_cert_param->key_cert_sign_len + * -# If (SB_PRV_RET_UNSUPPORTED_ALGO == key_algo) || + * (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_key_cert_param->img_pk_hash_algo) || + * (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_key_cert_param->sign_algo) || + * (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_key_cert_param->sign_hash_algo) || + * (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_key_cert_param->sign_scheme) + * -# Set ret to #SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM + * -# Else + * -# If p_cc_key_cert_param->sign_algo != key_algo + * -# Set ret to #SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM + * -# Else + * -# Set ret to #SB_RET_SUCCESS + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_cmn_drv_set_cc_key_cert_param(const st_sb_key_cert_t* const p_key_cert_st, + const st_sb_tlv_t* const p_img_pk_hash_tlv, + const st_sb_tlv_t* const p_sign_pk_tlv, + const st_sb_tlv_t* const p_sign_tlv, + st_cip_drv_cc_key_cert_param_t* const p_cc_key_cert_param) +{ + /*----------------------------------------------------------------------------------------------------------------- + Local variables + -----------------------------------------------------------------------------------------------------------------*/ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + uint32_t key_algo; + + /*----------------------------------------------------------------------------------------------------------------- + Function body + -----------------------------------------------------------------------------------------------------------------*/ + if ((NULL != p_key_cert_st) && (NULL != p_img_pk_hash_tlv) && (NULL != p_sign_pk_tlv) && + (NULL != p_sign_tlv) && (NULL != p_cc_key_cert_param)) + { + key_algo = cmn_drv_get_sign_algo(p_sign_pk_tlv->type); + if ((p_sign_pk_tlv->type & SB_PRV_TLV_TYPE_CLS_SIGN_UT_MASK) == SB_PRV_TLV_TYPE_CLS_KEY_UT_OEM_ROOT_PK) + { + p_cc_key_cert_param->key_cert_pk_cmp_src = CIP_DRV_KEY_CERT_PK_CMP_SRC_ROT; + } + else + { + p_cc_key_cert_param->key_cert_pk_cmp_src = CIP_DRV_KEY_CERT_PK_CMP_SRC_IMG_PK; + } + + p_cc_key_cert_param->img_pk_hash_algo = cmn_drv_get_hash_algo(p_img_pk_hash_tlv->type); + p_cc_key_cert_param->p_img_pk_hash = p_img_pk_hash_tlv->p_val; + p_cc_key_cert_param->img_pk_hash_len = p_img_pk_hash_tlv->byte_len; + p_cc_key_cert_param->sign_algo = cmn_drv_get_sign_algo(p_sign_tlv->type); + p_cc_key_cert_param->sign_hash_algo = cmn_drv_get_sign_hash_algo(p_sign_tlv->type); + p_cc_key_cert_param->sign_scheme = cmn_drv_get_sign_scheme(p_sign_tlv->type, p_cc_key_cert_param->sign_algo); + p_cc_key_cert_param->p_sign_pk = p_sign_pk_tlv->p_val; + p_cc_key_cert_param->sign_pk_len = p_sign_pk_tlv->byte_len; + p_cc_key_cert_param->p_sign = p_sign_tlv->p_val; + p_cc_key_cert_param->sign_len = p_sign_tlv->byte_len; + p_cc_key_cert_param->p_key_cert = (const uint32_t*)p_key_cert_st->p_header; /* Casting from pointer to + pointer is no problem */ + /* Key Cert signature length = Key Cert length - Key Cert signature TLV length */ + p_cc_key_cert_param->key_cert_sign_len = (SB_PRV_MANI_HEADER_SIZE + SB_PRV_MANI_TLV_LEN_SIZE + + p_key_cert_st->tlv_len) - (SB_PRV_TLV_TL_SIZE + p_sign_tlv->byte_len); + + /* Check algorithm */ + if ((SB_PRV_RET_UNSUPPORTED_ALGO == key_algo) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_key_cert_param->img_pk_hash_algo) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_key_cert_param->sign_algo) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_key_cert_param->sign_hash_algo) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_key_cert_param->sign_scheme)) + { + /* Unsupported algorithm */ + ret = SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM; + } + else + { + if (p_cc_key_cert_param->sign_algo != key_algo) + { + /* There is a wrong combination of signature algorithms */ + ret = SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM; + } + else + { + /* Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + } + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_drv_set_cc_key_cert_param() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_cmn_drv_set_cc_code_cert_param +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Setting code certificate parameter with in Certificate Chain verification + * \param [in] p_code_cert_st Start address of Code Certificate Structure + * \param [in] img_addr Address of the target image + * \param [in] p_sign_pk_tlv Start address of Signature public key TLV + * \param [in] p_sign_tlv Start address of Signature TLV + * \param [in] p_img_hash_tlv Start address of image hash TLV + * \param [out] p_cc_code_cert_param Starting address of the structure for setting the + * code certificate parameters used in the certificate chain + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM: There is a wrong combination of signature algorithms + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Convert Manifest information to SB-Driver definition and set it in parameter structure given as argument + * - This parameter is used in the following SB-Driver API + * - R_CIP_DRV_PrcVerifyCertChain + * - R_CIP_DRV_PrcCheckIntegrity + * - If build configuration #SB_CFG_SB_CERT_CHAIN_USE_IMG_PK is enabled, + * save the hash of the IMG PK of the code certificate + + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_code_cert_st) && (NULL != p_code_cert_st->p_header) && (NULL != p_sign_pk_tlv) && + * (NULL != p_sign_tlv) && (NULL != p_cc_code_cert_param) + * -# Get Signature public key algorithm with #cmn_drv_get_sign_algo and set to key_algo + * -# Get sign algorithm with #cmn_drv_get_sign_algo + * -# Set function result to p_cc_code_cert_param->sign_algo + * -# Get sign hash algorithm with #cmn_drv_get_sign_hash_algo + * -# Set function result to p_cc_code_cert_param->sign_hash_algo + * -# Get sign scheme with #cmn_drv_get_sign_scheme + * -# Set function result to p_cc_code_cert_param->sign_scheme + * -# Cast the p_sign_pk_tlv->p_val to uint32_t* type and set it to p_cc_code_cert_param->p_sign_pk + * -# Set p_sign_pk_tlv->byte_len to p_cc_code_cert_param->sign_pk_len + * -# Cast the p_sign_tlv->p_val to uint32_t* type and set it to p_cc_code_cert_param->p_sign + * -# Set p_sign_tlv->byte_len to p_cc_code_cert_param->sign_len + * -# Cast the p_code_cert_st->p_header to uint32_t* type and set it to p_cc_code_cert_param->p_code_cert + * -# Calculate the size of the code certificate and set it to p_cc_code_cert_param->code_cert_len + * -# Calculate the signing target size of the code certificate and + * set it to p_cc_code_cert_param->code_cert_sign_len + * -# Set p_code_cert_st->p_header->dest_addr to img_addr + * -# Set img_addr to p_cc_code_cert_param->p_img + * -# Set p_code_cert_st->p_header->img_len to p_cc_code_cert_param->img_len + * -# If (NULL != p_img_hash_tlv) + * -# Set cmn_drv_get_hash_algo(p_img_hash_tlv->type) to p_cc_code_cert_param->img_hash_algo + * -# Set p_img_hash_tlv->p_val to p_cc_code_cert_param->p_img_hash + * -# Set p_img_hash_tlv->byte_len to p_cc_code_cert_param->img_hash_len + * -# Else + * -# Set CIP_DRV_HASH_ALGO_NONE to p_cc_code_cert_param->img_hash_algo + * -# Set NULL to p_cc_code_cert_param->p_img_hash + * -# Set 0UL to p_cc_code_cert_param->img_hash_len + * -# --- If #SB_CFG_SB_CERT_CHAIN_USE_IMG_PK is enabled --- + * -# If (p_code_cert_st->p_header->flags & #SB_PRV_CODE_CERT_HEADER_FLAGS_SAVE_IMG_PK) != 0UL + * -# Set 1 to p_cc_code_cert_param->is_save_img_pk + * -# Else + * -# set 0 to p_cc_code_cert_param->is_save_img_pk + * -# --- Else #SB_CFG_SB_CERT_CHAIN_USE_IMG_PK is enabled --- + * -# Set 0 to p_cc_code_cert_param->is_save_img_pk + * -# --- Endif #SB_CFG_SB_CERT_CHAIN_USE_IMG_PK is enabled --- + * -# If (SB_PRV_RET_UNSUPPORTED_ALGO == key_algo) || + * (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_code_cert_param->sign_algo) || + * (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_code_cert_param->sign_hash_algo) || + * (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_code_cert_param->sign_scheme) || + * (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_code_cert_param->img_hash_algo) + * -# Set #SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM to ret + * -# Else + * -# If p_cc_code_cert_param->sign_algo != key_algo + * -# Set #SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM to ret + * -# Else + * -# Set ret to #SB_RET_SUCCESS + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_cmn_drv_set_cc_code_cert_param(const st_sb_code_cert_t* const p_code_cert_st, + const uint32_t img_addr, + const st_sb_tlv_t* const p_sign_pk_tlv, + const st_sb_tlv_t* const p_sign_tlv, + const st_sb_tlv_t* const p_img_hash_tlv, + st_cip_drv_cc_code_cert_param_t* const p_cc_code_cert_param) +{ + /*----------------------------------------------------------------------------------------------------------------- + Local variables + -----------------------------------------------------------------------------------------------------------------*/ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + volatile uintptr_t tmp_img_addr; + uint32_t key_algo; + + /*----------------------------------------------------------------------------------------------------------------- + Function body + -----------------------------------------------------------------------------------------------------------------*/ + if ((NULL != p_code_cert_st) && (NULL != p_code_cert_st->p_header) && (NULL != p_sign_pk_tlv) && + (NULL != p_sign_tlv) && (NULL != p_cc_code_cert_param)) + { + key_algo = cmn_drv_get_sign_algo(p_sign_pk_tlv->type); + p_cc_code_cert_param->sign_algo = cmn_drv_get_sign_algo(p_sign_tlv->type); + p_cc_code_cert_param->sign_hash_algo = cmn_drv_get_sign_hash_algo(p_sign_tlv->type); + p_cc_code_cert_param->sign_scheme = cmn_drv_get_sign_scheme(p_sign_tlv->type, + p_cc_code_cert_param->sign_algo); + p_cc_code_cert_param->p_sign_pk = p_sign_pk_tlv->p_val; + p_cc_code_cert_param->sign_pk_len = p_sign_pk_tlv->byte_len; + p_cc_code_cert_param->p_sign = p_sign_tlv->p_val; + p_cc_code_cert_param->sign_len = p_sign_tlv->byte_len; + p_cc_code_cert_param->p_code_cert = (const uint32_t*)p_code_cert_st->p_header; /* Casting from pointer + to pointer is no problem */ + p_cc_code_cert_param->code_cert_len = SB_PRV_MANI_HEADER_SIZE + SB_PRV_MANI_TLV_LEN_SIZE + + p_code_cert_st->tlv_len; + p_cc_code_cert_param->code_cert_sign_len = p_cc_code_cert_param->code_cert_len + - (SB_PRV_TLV_TL_SIZE + p_sign_tlv->byte_len); + /* Assign the address set in dest_addr once to a uintptr_t type variable + (32/64bit MPU countermeasures) */ + tmp_img_addr = img_addr; + p_cc_code_cert_param->p_img = (const uint32_t*)tmp_img_addr; /* Casts that do not exceed + the size of the type are fine */ + p_cc_code_cert_param->img_len = p_code_cert_st->p_header->img_len; + if (NULL != p_img_hash_tlv) + { + p_cc_code_cert_param->img_hash_algo = cmn_drv_get_hash_algo(p_img_hash_tlv->type); + p_cc_code_cert_param->p_img_hash = p_img_hash_tlv->p_val; + p_cc_code_cert_param->img_hash_len = p_img_hash_tlv->byte_len; + } + else + { + p_cc_code_cert_param->img_hash_algo = CIP_DRV_HASH_ALGO_NONE; + p_cc_code_cert_param->p_img_hash = NULL; + p_cc_code_cert_param->img_hash_len = 0UL; + } +#if (SB_CFG_SB_CERT_CHAIN_USE_IMG_PK == 1U) /* (Use only when SB_CFG_SB_CERT_CHAIN_USE_IMG_PK is Enable) */ + if ((p_code_cert_st->p_header->flags & SB_PRV_CODE_CERT_HEADER_FLAGS_SAVE_IMG_PK) != 0UL) + { + p_cc_code_cert_param->is_save_img_pk = 1UL; + } + else + { + p_cc_code_cert_param->is_save_img_pk = 0UL; + } +#else /* !(SB_CFG_SB_CERT_CHAIN_USE_IMG_PK == 1U) */ + p_cc_code_cert_param->is_save_img_pk = 0UL; +#endif /* !(SB_CFG_SB_CERT_CHAIN_USE_IMG_PK == 1U) */ + + /* Check algorithm */ + if ((SB_PRV_RET_UNSUPPORTED_ALGO == key_algo) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_code_cert_param->sign_algo) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_code_cert_param->sign_hash_algo) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_code_cert_param->sign_scheme) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cc_code_cert_param->img_hash_algo)) + { + /* Unsupported algorithm */ + ret = SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM; + } + else + { + if (p_cc_code_cert_param->sign_algo != key_algo) + { + /* There is a wrong combination of signature algorithms */ + ret = SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM; + } + else + { + /* Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + } + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_drv_set_cc_code_cert_param() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_cmn_drv_set_cipher_img_param +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Setting Image Cipher Information parameters + * \param [in] p_code_cert_st Start address of Code Certificate Structure + * \param [in] p_img_cip_info Start address of Signature public key TLV + * \param [in] p_img_cip_iv Start address of Signature TLV + * \param [in] is_overwrite_image Whether to overwrite Image + * - #SB_PRV_TRUE: Overwrite + * - #SB_PRV_FALSE: Do not overwrite + * \param [in] timing Cipher timing viewed from signature verification + * \param [out] p_cipher_img_param Starting address of the structure for setting image cipher parameters + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Convert Manifest information to SB-Driver definition and set it in parameter structure given as argument + * - This parameter is used in the following SB-Driver API + * - R_CIP_DRV_PrcDecryptImage + * - R_CIP_DRV_PrcCheckIntegrity + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_code_cert_st) && (NULL != p_code_cert_st->p_header) && (NULL != p_img_cip_info) && + * (NULL != p_cipher_img_param) && (NULL != p_img_cip_iv) + * -# Set p_cipher_img_param->timing to timing + * -# Set img_addr to p_code_cert_st->p_header->dest_addr + * -# Set p_cipher_img_param->p_img_src to img_addr + * -# Set p_cipher_img_param->img_len to p_code_cert_st->p_header->img_len + * -# Cast the p_img_cip_iv->p_val to uint32_t* type and set it to p_cipher_img_param->p_iv + * -# Set p_cipher_img_param->iv_len to p_img_cip_iv->byte_len + * -# If (NULL == p_img_cip_info->p_val) + * -# Set p_cipher_img_param->p_img_dst to img_addr + * -# Set p_cipher_img_param->cipher_algo to CIP_DRV_CIPHER_ALGO_NONE + * -# Set p_cipher_img_param->cipher_mode to CIP_DRV_CIPHER_MODE_NONE + * -# Set p_cipher_img_param->key_select to CIP_DRV_CIPHER_INFO_KEY_SEL_DEFAULT + * -# Set p_cipher_img_param->iv_select to CIP_DRV_CIPHER_INFO_IV_SEL_DEFAULT + * -# Else + * -# Cast the p_img_cip_info->p_val to const #st_sb_img_cip_info_val_t* type and set it to p_img_cip_info_val + * -# Get Cipher algorithm with #cmn_drv_get_img_cip_info_algo + * -# Set p_cipher_img_param->cipher_algo to function result + * -# Get Cipher mode with #cmn_drv_get_img_cip_info_mode + * -# Set p_cipher_img_param->cipher_mode to function result + * -# Set p_cipher_img_param->key_select to p_img_cip_info_val->key_sel + * -# Set p_cipher_img_param->iv_select to p_img_cip_info_val->iv_sel + * -# If #SB_PRV_TRUE == is_overwrite_image + * -# Set p_cipher_img_param->p_img_dst to p_cipher_img_param->p_img_src + * -# Else + * -# Set img_addr to p_img_cip_info_val->dest_addr + * -# Set p_cipher_img_param->p_img_dst to img_addr + * -# If (#SB_PRV_RET_UNSUPPORTED_ALGO == p_cipher_img_param->cipher_algo) || + * (#SB_PRV_RET_UNSUPPORTED_ALGO == p_cipher_img_param->cipher_mode)) + * -# Set ret to #SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM + * -# Else + * -# Set ret to #SB_RET_SUCCESS + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_cmn_drv_set_cipher_img_param(const st_sb_code_cert_t* const p_code_cert_st, + const st_sb_tlv_t* const p_img_cip_info, + const st_sb_tlv_t* const p_img_cip_iv, + const sb_bool_t is_overwrite_image, + const uint32_t timing, + st_cip_drv_cipher_img_param_t* const p_cipher_img_param) +{ + /*----------------------------------------------------------------------------------------------------------------- + Local variables + -----------------------------------------------------------------------------------------------------------------*/ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + const st_sb_img_cip_info_val_t * p_img_cip_info_val; + volatile uintptr_t img_addr; + + /*----------------------------------------------------------------------------------------------------------------- + Function body + -----------------------------------------------------------------------------------------------------------------*/ + if ((NULL != p_code_cert_st) && (NULL != p_code_cert_st->p_header) && (NULL != p_img_cip_info) && + (NULL != p_cipher_img_param) && (NULL != p_img_cip_iv)) + { + /* Set common parameters */ + p_cipher_img_param->timing = timing; + /* Assign the address set in dest_addr once to a uintptr_t type variable + (32/64bit MPU countermeasures) */ + img_addr = p_code_cert_st->p_header->dest_addr; + /* Casts that do not exceed the size of the type are fine */ + p_cipher_img_param->p_img_src = (const uint32_t*)img_addr; + p_cipher_img_param->img_len = p_code_cert_st->p_header->img_len; + p_cipher_img_param->p_iv = p_img_cip_iv->p_val; + p_cipher_img_param->iv_len = p_img_cip_iv->byte_len; + + if (NULL == p_img_cip_info->p_val) + { + /* Overwrite image */ + p_cipher_img_param->p_img_dst = (uint32_t*)img_addr; + + /* Use Device default parameters */ + p_cipher_img_param->cipher_algo = CIP_DRV_CIPHER_ALGO_NONE; + p_cipher_img_param->cipher_mode = CIP_DRV_CIPHER_MODE_NONE; + p_cipher_img_param->key_select = CIP_DRV_CIPHER_INFO_KEY_SEL_DEFAULT; + p_cipher_img_param->iv_select = CIP_DRV_CIPHER_INFO_IV_SEL_DEFAULT; + } + else + { + /* Use TLV parameters */ + p_img_cip_info_val = (const st_sb_img_cip_info_val_t*)(p_img_cip_info->p_val); /* Casting from pointer + to pointer is no problem */ + p_cipher_img_param->cipher_algo = cmn_drv_get_img_cip_info_algo(p_img_cip_info->type); + p_cipher_img_param->cipher_mode = cmn_drv_get_img_cip_info_mode(p_img_cip_info->type); + p_cipher_img_param->key_select = p_img_cip_info_val->key_sel; + p_cipher_img_param->iv_select = p_img_cip_info_val->iv_sel; + if (SB_PRV_TRUE == is_overwrite_image) + { + /* Casts that do not exceed the size of the type are fine */ + p_cipher_img_param->p_img_dst = (uint32_t*)img_addr; + } + else + { + /* Assign the address set in dest_addr once to a uintptr_t type variable + (32/64bit MPU countermeasures) */ + img_addr = p_img_cip_info_val->dest_addr; + /* Casts that do not exceed the size of the type are fine */ + p_cipher_img_param->p_img_dst = (uint32_t*)img_addr; + } + } + /* Check algorithm */ + if ((SB_PRV_RET_UNSUPPORTED_ALGO == p_cipher_img_param->cipher_algo) || + (SB_PRV_RET_UNSUPPORTED_ALGO == p_cipher_img_param->cipher_mode)) + { + /* Unsupported algorithm */ + ret = SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM; + } + else + { + /* Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_drv_set_cipher_img_param() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_cmn_drv_get_sb_ret_from_cip_ret +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Returns the return code corresponding to the return code of cipher driver + * \param [in] cip_ret Cipher Driver return code + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_SAME_IMAGE_VERSION: An image of the same version as the current version is + * input(verification completed successfully) + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_CRYPTO_FAIL: Encryption failed + * - #SB_RET_ERR_CRYPTO_AUTH_FAIL: Verification failed + * - #SB_RET_ERR_CRYPTO_UNSUPPORTED_ALGORITHM: Unsupported algorithm + * - #SB_RET_ERR_CRYPTO_RESOURCE_CONFLICT: CryptoIP resources are being used by other resources + * - #SB_RET_ERR_CRYPTO_PARAM_ERR: Parameter error + * - #SB_RET_ERR_LOWER_IMAGE_VERSION: Image version lower than the current image version is installed + * - #SB_RET_ERR_CRC_MISMATCH CRC mismatch + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Returns the return code corresponding to the return code of cipher driver + * - Implement the following as a glitch countermeasure : + * - Set success return value in two steps + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# Initialize the variable tmp_ret with #SB_RET_ERR_INTERNAL_FAIL + * -# switch cip_ret + * -# cip_ret == CIP_DRV_RET_PASS + * -# Set (#SB_RET_SUCCESS & #SB_PRV_RET_UPPER_MASK) to ret + * -# cip_ret == CIP_DRV_RET_SAME_IMAGE_VERSION + * -# Set (#SB_RET_SAME_IMAGE_VERSION & #SB_PRV_RET_UPPER_MASK) to ret + * -# cip_ret == CIP_DRV_RET_AUTH_FAIL, Set ret to #SB_RET_ERR_CRYPTO_AUTH_FAIL + * -# cip_ret == CIP_DRV_RET_UNSUPPORTED_ALGORITHM, Set ret to #SB_RET_ERR_CRYPTO_UNSUPPORTED_ALGORITHM + * -# cip_ret == CIP_DRV_RET_RESOURCE_CONFLICT, Set ret to #SB_RET_ERR_CRYPTO_RESOURCE_CONFLICT + * -# cip_ret == CIP_DRV_RET_LOWER_IMAGE_VERSION, Set ret to #SB_RET_ERR_LOWER_IMAGE_VERSION + * -# cip_ret == CIP_DRV_RET_PARAM_ERROR, Set ret to #SB_RET_ERR_CRYPTO_PARAM_ERR + * -# cip_ret == CIP_DRV_RET_CRC_MISMATCH, Set ret to #SB_RET_ERR_CRC_MISMATCH + * -# default, Set ret to #SB_RET_ERR_CRYPTO_FAIL + * -# switch cip_ret + * -# cip_ret == CIP_DRV_RET_PASS + * -# Set ret to (#SB_RET_SUCCESS & #SB_PRV_RET_LOWER_MASK) + * -# cip_ret == CIP_DRV_RET_SAME_IMAGE_VERSION + * -# Set ret to (#SB_RET_SAME_IMAGE_VERSION & #SB_PRV_RET_LOWER_MASK) + * -# default + * -# In case of error, do nothing because the return value has already been set + * -# If (ret & #SB_PRV_RET_ERROR_BITS) != #SB_PRV_RET_ERROR_BITS + * -# If (#SB_RET_SUCCESS == ret) || (#SB_RET_SAME_IMAGE_VERSION == ret) + * -# Do nothing + * -# Else + * -# Set ret to #SB_RET_ERR_INTERNAL_FAIL + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_cmn_drv_get_sb_ret_from_cip_ret(const cip_drv_ret_t cip_ret) +{ + /*----------------------------------------------------------------------------------------------------------------- + Local variables + -----------------------------------------------------------------------------------------------------------------*/ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + volatile sb_ret_t tmp_ret = SB_RET_ERR_INTERNAL_FAIL; + + /*----------------------------------------------------------------------------------------------------------------- + Function body + -----------------------------------------------------------------------------------------------------------------*/ + switch (cip_ret) + { + case CIP_DRV_RET_PASS: + tmp_ret = (SB_RET_SUCCESS & SB_PRV_RET_UPPER_MASK); + break; + case CIP_DRV_RET_SAME_IMAGE_VERSION: + tmp_ret = (SB_RET_SAME_IMAGE_VERSION & SB_PRV_RET_UPPER_MASK); + break; + case CIP_DRV_RET_AUTH_FAIL: + tmp_ret = SB_RET_ERR_CRYPTO_AUTH_FAIL; + break; + case CIP_DRV_RET_UNSUPPORTED_ALGORITHM: + tmp_ret = SB_RET_ERR_CRYPTO_UNSUPPORTED_ALGORITHM; + break; + case CIP_DRV_RET_RESOURCE_CONFLICT: + tmp_ret = SB_RET_ERR_CRYPTO_RESOURCE_CONFLICT; + break; + case CIP_DRV_RET_LOWER_IMAGE_VERSION: + tmp_ret = SB_RET_ERR_LOWER_IMAGE_VERSION; + break; + case CIP_DRV_RET_PARAM_ERROR: + tmp_ret = SB_RET_ERR_CRYPTO_PARAM_ERR; + break; + case CIP_DRV_RET_CRC_MISMATCH: + tmp_ret = SB_RET_ERR_CRC_MISMATCH; + break; + default: + tmp_ret = SB_RET_ERR_CRYPTO_FAIL; + break; + } + + switch (cip_ret) + { + case CIP_DRV_RET_PASS: + tmp_ret |= (SB_RET_SUCCESS & SB_PRV_RET_LOWER_MASK); + break; + case CIP_DRV_RET_SAME_IMAGE_VERSION: + tmp_ret |= (SB_RET_SAME_IMAGE_VERSION & SB_PRV_RET_LOWER_MASK); + break; + default: + /* In case of error, do nothing because the return value has already been set */ + break; + } + + /* Check route is passed */ + ret = tmp_ret; + if ((ret & SB_PRV_RET_ERROR_BITS) != SB_PRV_RET_ERROR_BITS) + { + if ((SB_RET_SUCCESS == ret) || (SB_RET_SAME_IMAGE_VERSION == ret)) + { + /* In case of two SUCCESS route is passed. Do nothing */ + } + else + { + /* In case of only one SUCCESS route is passed, set INTERNAL_FAIL to ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + + } + } + else + { + /* In case of ERROR route is passed. Do nothing */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_drv_get_sb_ret_from_cip_ret() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_cmn_drv_get_mac_algo_from_sb_mac_type +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Get MAC Algorithm + * \param [in] mac_type MAC Algorithm type + * \return + * - CIP_DRV_MAC_ALGO_HMAC_SHA2_224: MAC Algorithm HMAC SHA2-224 + * - CIP_DRV_MAC_ALGO_HMAC_SHA2_256: MAC Algorithm HMAC SHA2-256 + * - CIP_DRV_MAC_ALGO_HMAC_SHA2_384: MAC Algorithm HMAC SHA2-384 + * - CIP_DRV_MAC_ALGO_HMAC_SHA2_512: MAC Algorithm HMAC SHA2-512 + * - CIP_DRV_MAC_ALGO_HMAC_SHA3_224: MAC Algorithm HMAC SHA3-224 + * - CIP_DRV_MAC_ALGO_HMAC_SHA3_256: MAC Algorithm HMAC SHA3-256 + * - CIP_DRV_MAC_ALGO_HMAC_SHA3_384: MAC Algorithm HMAC SHA3-384 + * - CIP_DRV_MAC_ALGO_HMAC_SHA3_512: MAC Algorithm HMAC SHA3-512 + * - CIP_DRV_MAC_ALGO_CMAC_AES_128: MAC Algorithm CMAC AES-128 + * - CIP_DRV_MAC_ALGO_CMAC_AES_192: MAC Algorithm CMAC AES-192 + * - CIP_DRV_MAC_ALGO_CMAC_AES_256: MAC Algorithm CMAC AES-256 + * - SB_PRV_RET_UNSUPPORTED_ALGO: Unsupported algorithm specified + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Returns the MAC algorithm according to the argument + * - Convert SB-Lib MAC type to Crypto IP-Driver MAC algorithm value + * - This function gets the MAC algorithm value of Crypto IP-Driver from the MAC type of #e_sb_mac_type_t type + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with CIP_DRV_MAC_ALGO_NONE + * -# switch mac_type + * -# mac_type == #SB_MAC_TYPE_HMAC_SHA2_224, Set CIP_DRV_MAC_ALGO_HMAC_SHA2_224 to mac_algo + * -# mac_type == #SB_MAC_TYPE_HMAC_SHA2_256, Set CIP_DRV_MAC_ALGO_HMAC_SHA2_256 to mac_algo + * -# mac_type == #SB_MAC_TYPE_HMAC_SHA2_384, Set CIP_DRV_MAC_ALGO_HMAC_SHA2_384 to mac_algo + * -# mac_type == #SB_MAC_TYPE_HMAC_SHA2_512, Set CIP_DRV_MAC_ALGO_HMAC_SHA2_512 to mac_algo + * -# mac_type == #SB_MAC_TYPE_HMAC_SHA3_224, Set CIP_DRV_MAC_ALGO_HMAC_SHA3_224 to mac_algo + * -# mac_type == #SB_MAC_TYPE_HMAC_SHA3_256, Set CIP_DRV_MAC_ALGO_HMAC_SHA3_256 to mac_algo + * -# mac_type == #SB_MAC_TYPE_HMAC_SHA3_384, Set CIP_DRV_MAC_ALGO_HMAC_SHA3_384 to mac_algo + * -# mac_type == #SB_MAC_TYPE_HMAC_SHA3_512, Set CIP_DRV_MAC_ALGO_HMAC_SHA3_512 to mac_algo + * -# mac_type == #SB_MAC_TYPE_CMAC_AES_128, Set CIP_DRV_MAC_ALGO_CMAC_AES_128 to mac_algo + * -# mac_type == #SB_MAC_TYPE_CMAC_AES_192, Set CIP_DRV_MAC_ALGO_CMAC_AES_192 to mac_algo + * -# mac_type == #SB_MAC_TYPE_CMAC_AES_256, Set CIP_DRV_MAC_ALGO_CMAC_AES_256 to mac_algo + * -# In the default case, do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +uint32_t r_sb_cmn_drv_get_mac_algo_from_sb_mac_type(const e_sb_mac_type_t mac_type) +{ + uint32_t mac_algo = CIP_DRV_MAC_ALGO_NONE; + + switch (mac_type) + { + case SB_MAC_TYPE_HMAC_SHA2_224: + mac_algo = CIP_DRV_MAC_ALGO_HMAC_SHA2_224; + break; + case SB_MAC_TYPE_HMAC_SHA2_256: + mac_algo = CIP_DRV_MAC_ALGO_HMAC_SHA2_256; + break; + case SB_MAC_TYPE_HMAC_SHA2_384: + mac_algo = CIP_DRV_MAC_ALGO_HMAC_SHA2_384; + break; + case SB_MAC_TYPE_HMAC_SHA2_512: + mac_algo = CIP_DRV_MAC_ALGO_HMAC_SHA2_512; + break; + case SB_MAC_TYPE_HMAC_SHA3_224: + mac_algo = CIP_DRV_MAC_ALGO_HMAC_SHA3_224; + break; + case SB_MAC_TYPE_HMAC_SHA3_256: + mac_algo = CIP_DRV_MAC_ALGO_HMAC_SHA3_256; + break; + case SB_MAC_TYPE_HMAC_SHA3_384: + mac_algo = CIP_DRV_MAC_ALGO_HMAC_SHA3_384; + break; + case SB_MAC_TYPE_HMAC_SHA3_512: + mac_algo = CIP_DRV_MAC_ALGO_HMAC_SHA3_512; + break; + case SB_MAC_TYPE_CMAC_AES_128: + mac_algo = CIP_DRV_MAC_ALGO_CMAC_AES_128; + break; + case SB_MAC_TYPE_CMAC_AES_192: + mac_algo = CIP_DRV_MAC_ALGO_CMAC_AES_192; + break; + case SB_MAC_TYPE_CMAC_AES_256: + mac_algo = CIP_DRV_MAC_ALGO_CMAC_AES_256; + break; + default: /* In the default case, return CIP_DRV_MAC_ALGO_NONE */ + break; + } + + return mac_algo; +} +/********************************************************************************************************************** +* End of function r_sb_cmn_drv_get_mac_algo_from_sb_mac_type() +**********************************************************************************************************************/ + +/*===================================================================================================================== + Private function definitions +=====================================================================================================================*/ +/********************************************************************************************************************** +* Function Name : cmn_drv_get_hash_algo +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Get Hash Algorithm + * \param [in] type Hash Algorithm type + * \return + * - CIP_DRV_HASH_ALGO_SHA2_224: Hash Algorithm SHA2-224 + * - CIP_DRV_HASH_ALGO_SHA2_256: Hash Algorithm SHA2-256 + * - CIP_DRV_HASH_ALGO_SHA2_384: Hash Algorithm SHA2-384 + * - CIP_DRV_HASH_ALGO_SHA2_512: Hash Algorithm SHA2-512 + * - CIP_DRV_HASH_ALGO_SHA3_224: Hash Algorithm SHA3-224 + * - CIP_DRV_HASH_ALGO_SHA3_256: Hash Algorithm SHA3-256 + * - CIP_DRV_HASH_ALGO_SHA3_384: Hash Algorithm SHA3-384 + * - CIP_DRV_HASH_ALGO_SHA3_512: Hash Algorithm SHA3-512 + * - SB_PRV_RET_UNSUPPORTED_ALGO: Unsupported algorithm specified + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Returns the hash algorithm according to the argument + * - Convert SB-Lib HASH type to Crypto IP-Driver HASH algorithm value + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_PRV_RET_UNSUPPORTED_ALGO + * -# switch (type & #SB_PRV_TLV_TYPE_CRYPTO_ALGO_MASK) + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_224, Set CIP_DRV_HASH_ALGO_SHA2_224 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_256, Set CIP_DRV_HASH_ALGO_SHA2_256 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_384, Set CIP_DRV_HASH_ALGO_SHA2_384 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_512, Set CIP_DRV_HASH_ALGO_SHA2_512 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_224, Set CIP_DRV_HASH_ALGO_SHA3_224 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_256, Set CIP_DRV_HASH_ALGO_SHA3_256 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_384, Set CIP_DRV_HASH_ALGO_SHA3_384 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_512, Set CIP_DRV_HASH_ALGO_SHA3_512 to hash_algo + * -# In the default case, do nothing + * -# Return hash_algo + * + * \callgraph + *********************************************************************************************************************/ +static uint32_t cmn_drv_get_hash_algo(const uint32_t type) +{ + uint32_t hash_algo = SB_PRV_RET_UNSUPPORTED_ALGO; + + switch (type & SB_PRV_TLV_TYPE_CRYPTO_ALGO_MASK) + { + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_224: + hash_algo = CIP_DRV_HASH_ALGO_SHA2_224; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_256: + hash_algo = CIP_DRV_HASH_ALGO_SHA2_256; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_384: + hash_algo = CIP_DRV_HASH_ALGO_SHA2_384; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA2_512: + hash_algo = CIP_DRV_HASH_ALGO_SHA2_512; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_224: + hash_algo = CIP_DRV_HASH_ALGO_SHA3_224; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_256: + hash_algo = CIP_DRV_HASH_ALGO_SHA3_256; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_384: + hash_algo = CIP_DRV_HASH_ALGO_SHA3_384; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_SHA3_512: + hash_algo = CIP_DRV_HASH_ALGO_SHA3_512; + break; + default: /* In the default case, return SB_PRV_RET_UNSUPPORTED_ALGO */ + break; + } + + return hash_algo; +} +/********************************************************************************************************************** +* End of function cmn_drv_get_hash_algo() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : cmn_drv_get_sign_hash_algo +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Get Signature Hash Algorithm + * \param [in] type Signature Hash Algorithm type + * \return + * - CIP_DRV_HASH_ALGO_SHA2_224: Hash Algorithm SHA2-224 + * - CIP_DRV_HASH_ALGO_SHA2_256: Hash Algorithm SHA2-256 + * - CIP_DRV_HASH_ALGO_SHA2_384: Hash Algorithm SHA2-384 + * - CIP_DRV_HASH_ALGO_SHA2_512: Hash Algorithm SHA2-512 + * - CIP_DRV_HASH_ALGO_SHA3_224: Hash Algorithm SHA3-224 + * - CIP_DRV_HASH_ALGO_SHA3_256: Hash Algorithm SHA3-256 + * - CIP_DRV_HASH_ALGO_SHA3_384: Hash Algorithm SHA3-384 + * - CIP_DRV_HASH_ALGO_SHA3_512: Hash Algorithm SHA3-512 + * - SB_PRV_RET_UNSUPPORTED_ALGO: Unsupported algorithm specified + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Returns the hash algorithm according to the argument + * - Convert SB-Lib Signature HASH type to Crypto IP-Driver HASH algorithm value + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_PRV_RET_UNSUPPORTED_ALGO + * -# switch (type & #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_MASK) + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_224, Set CIP_DRV_HASH_ALGO_SHA2_224 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_256, Set CIP_DRV_HASH_ALGO_SHA2_256 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_384, Set CIP_DRV_HASH_ALGO_SHA2_384 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_512, Set CIP_DRV_HASH_ALGO_SHA2_512 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_224, Set CIP_DRV_HASH_ALGO_SHA3_224 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_256, Set CIP_DRV_HASH_ALGO_SHA3_256 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_384, Set CIP_DRV_HASH_ALGO_SHA3_384 to hash_algo + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_512, Set CIP_DRV_HASH_ALGO_SHA3_512 to hash_algo + * -# In the default case, do nothing + * -# Return hash_algo + * + * \callgraph + *********************************************************************************************************************/ +static uint32_t cmn_drv_get_sign_hash_algo(const uint32_t type) +{ + uint32_t hash_algo = SB_PRV_RET_UNSUPPORTED_ALGO; + + switch (type & SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_MASK) + { + case SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_224: + hash_algo = CIP_DRV_HASH_ALGO_SHA2_224; + break; + case SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_256: + hash_algo = CIP_DRV_HASH_ALGO_SHA2_256; + break; + case SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_384: + hash_algo = CIP_DRV_HASH_ALGO_SHA2_384; + break; + case SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA2_512: + hash_algo = CIP_DRV_HASH_ALGO_SHA2_512; + break; + case SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_224: + hash_algo = CIP_DRV_HASH_ALGO_SHA3_224; + break; + case SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_256: + hash_algo = CIP_DRV_HASH_ALGO_SHA3_256; + break; + case SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_384: + hash_algo = CIP_DRV_HASH_ALGO_SHA3_384; + break; + case SB_PRV_TLV_TYPE_CLS_SIGN_HASH_ALGO_SHA3_512: + hash_algo = CIP_DRV_HASH_ALGO_SHA3_512; + break; + default: /* In the default case, return SB_PRV_RET_UNSUPPORTED_ALGO */ + break; + } + + return hash_algo; +} +/********************************************************************************************************************** +* End of function cmn_drv_get_sign_hash_algo() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : cmn_drv_get_sign_algo +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Get Signature Algorithm + * \param [in] type Signature Algorithm type + * \return + * - CIP_DRV_SIGN_ALGO_ECDSA_P192: Signature Algorithm ECC NIST P-192 + * - CIP_DRV_SIGN_ALGO_ECDSA_P224: Signature Algorithm ECC NIST P-224 + * - CIP_DRV_SIGN_ALGO_ECDSA_P256: Signature Algorithm ECC NIST P-256 + * - CIP_DRV_SIGN_ALGO_ECDSA_P384: Signature Algorithm ECC NIST P-384 + * - CIP_DRV_SIGN_ALGO_ECDSA_P521: Signature Algorithm ECC NIST P-521 + * - CIP_DRV_SIGN_ALGO_ECDSA_BP192R1: Signature Algorithm ECC BrainpoolP192 + * - CIP_DRV_SIGN_ALGO_ECDSA_BP224R1: Signature Algorithm ECC BrainpoolP224 + * - CIP_DRV_SIGN_ALGO_ECDSA_BP256R1: Signature Algorithm ECC BrainpoolP256 + * - CIP_DRV_SIGN_ALGO_ECDSA_BP384R1: Signature Algorithm ECC BrainpoolP384 + * - CIP_DRV_SIGN_ALGO_ECDSA_BP512R1: Signature Algorithm ECC BrainpoolP512 + * - CIP_DRV_SIGN_ALGO_EDDSA_ED25519: Signature Algorithm EdDSA Ed25519 + * - CIP_DRV_SIGN_ALGO_EDDSA_ED448: Signature Algorithm EdDSA Ed448 + * - CIP_DRV_SIGN_ALGO_RSA1024: Signature Algorithm RSA 1024bit + * - CIP_DRV_SIGN_ALGO_RSA2048: Signature Algorithm RSA 2048bit + * - CIP_DRV_SIGN_ALGO_RSA3072: Signature Algorithm RSA 3072bit + * - CIP_DRV_SIGN_ALGO_RSA4096: Signature Algorithm RSA 4096bit + * - SB_PRV_RET_UNSUPPORTED_ALGO: Unsupported algorithm specified + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Returns the Signature algorithm according to the argument + * - Convert SB-Lib Signature algorithm type to Crypto IP-Driver Signature algorithm value + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_PRV_RET_UNSUPPORTED_ALGO + * -# switch (type & #SB_PRV_TLV_TYPE_CRYPTO_ALGO_MASK) + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P192, Set CIP_DRV_SIGN_ALGO_ECDSA_P192 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P224, Set CIP_DRV_SIGN_ALGO_ECDSA_P224 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P256, Set CIP_DRV_SIGN_ALGO_ECDSA_P256 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P384, Set CIP_DRV_SIGN_ALGO_ECDSA_P384 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P521, Set CIP_DRV_SIGN_ALGO_ECDSA_P521 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP192R1, Set CIP_DRV_SIGN_ALGO_ECDSA_BP192R1 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP224R1, Set CIP_DRV_SIGN_ALGO_ECDSA_BP224R1 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP256R1, Set CIP_DRV_SIGN_ALGO_ECDSA_BP256R1 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP384R1, Set CIP_DRV_SIGN_ALGO_ECDSA_BP384R1 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP512R1, Set CIP_DRV_SIGN_ALGO_ECDSA_BP512R1 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_CURVE25519, Set CIP_DRV_SIGN_ALGO_EDDSA_ED25519 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_CURVE448, Set CIP_DRV_SIGN_ALGO_EDDSA_ED448 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA1024, Set CIP_DRV_SIGN_ALGO_RSA1024 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA2048, Set CIP_DRV_SIGN_ALGO_RSA2048 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA3072, Set CIP_DRV_SIGN_ALGO_RSA3072 to sign_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA4096, Set CIP_DRV_SIGN_ALGO_RSA4096 to sign_algo + * -# In the default case, do nothing + * -# Return sign_algo + * + * \callgraph + *********************************************************************************************************************/ +static uint32_t cmn_drv_get_sign_algo(const uint32_t type) +{ + uint32_t sign_algo = SB_PRV_RET_UNSUPPORTED_ALGO; + + switch (type & SB_PRV_TLV_TYPE_CRYPTO_ALGO_MASK) + { + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P192: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_P192; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P224: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_P224; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P256: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_P256; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P384: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_P384; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_P521: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_P521; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP192R1: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_BP192R1; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP224R1: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_BP224R1; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP256R1: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_BP256R1; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP384R1: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_BP384R1; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_ECC_BP512R1: + sign_algo = CIP_DRV_SIGN_ALGO_ECDSA_BP512R1; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_CURVE25519: + sign_algo = CIP_DRV_SIGN_ALGO_EDDSA_ED25519; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_CURVE448: + sign_algo = CIP_DRV_SIGN_ALGO_EDDSA_ED448; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA1024: + sign_algo = CIP_DRV_SIGN_ALGO_RSA1024; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA2048: + sign_algo = CIP_DRV_SIGN_ALGO_RSA2048; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA3072: + sign_algo = CIP_DRV_SIGN_ALGO_RSA3072; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_RSA4096: + sign_algo = CIP_DRV_SIGN_ALGO_RSA4096; + break; + default: /* In the default case, return SB_PRV_RET_UNSUPPORTED_ALGO */ + break; + } + + return sign_algo; +} +/********************************************************************************************************************** +* End of function cmn_drv_get_sign_algo() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : cmn_drv_get_sign_scheme +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Get Signature Scheme + * \param [in] type Signature Scheme type + * \param [in] sign_algo Signature Algorithm + * \return + * - CIP_DRV_SCHEME_NONE: Signature Scheme none + * - CIP_DRV_SCHEME_RSASSA_PKCS1_V1_5: Signature Scheme RSASSA-PKCS1_v1_5 + * - CIP_DRV_SCHEME_RSASSA_PSS: Signature Scheme RSASSA-PSS + * - SB_PRV_RET_UNSUPPORTED_ALGO: Unsupported algorithm specified + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Returns the Signature scheme according to the argument + * - Convert SB-Lib Signature scheme type to Crypto IP-Driver Signature scheme value + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_PRV_RET_UNSUPPORTED_ALGO + * -# If (CIP_DRV_SIGN_ALGO_RSA1024 == sign_algo) || (CIP_DRV_SIGN_ALGO_RSA2048 == sign_algo) || + * (CIP_DRV_SIGN_ALGO_RSA3072 == sign_algo) || (CIP_DRV_SIGN_ALGO_RSA4096 == sign_algo) + * -# switch (type & #SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_MASK) + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_RSASSA_PKCS1_V1_5, Set CIP_DRV_SCHEME_RSASSA_PKCS1_V1_5 to sign_scheme + * -# type == #SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_RSASSA_PSS, Set CIP_DRV_SCHEME_RSASSA_PSS to sign_scheme + * -# In the default case, do nothing + * -# Else + * -# Set CIP_DRV_SCHEME_NONE to sign_scheme + * -# Return sign_scheme + * + * \callgraph + *********************************************************************************************************************/ +static uint32_t cmn_drv_get_sign_scheme(const uint32_t type, const uint32_t sign_algo) +{ + uint32_t sign_scheme = SB_PRV_RET_UNSUPPORTED_ALGO; + + if ((CIP_DRV_SIGN_ALGO_RSA1024 == sign_algo) || (CIP_DRV_SIGN_ALGO_RSA2048 == sign_algo) || + (CIP_DRV_SIGN_ALGO_RSA3072 == sign_algo) || (CIP_DRV_SIGN_ALGO_RSA4096 == sign_algo)) + { + switch (type & SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_MASK) + { + case SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_RSASSA_PKCS1_V1_5: + sign_scheme = CIP_DRV_SCHEME_RSASSA_PKCS1_V1_5; + break; + case SB_PRV_TLV_TYPE_CLS_SIGN_SCHEME_RSASSA_PSS: + sign_scheme = CIP_DRV_SCHEME_RSASSA_PSS; + break; + default: /* In the default case, return SB_PRV_RET_UNSUPPORTED_ALGO */ + break; + } + } + else + { + sign_scheme = CIP_DRV_SCHEME_NONE; + } + + return sign_scheme; +} +/********************************************************************************************************************** +* End of function cmn_drv_get_sign_scheme() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : cmn_drv_get_img_cip_info_algo +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Get Cipher algorithm + * \param [in] type Cipher algorithm type + * \return + * - CIP_DRV_CIPHER_ALGO_AES128: Cipher Algorithm AES-128 + * - CIP_DRV_CIPHER_ALGO_AES192: Cipher Algorithm AES-192 + * - CIP_DRV_CIPHER_ALGO_AES256: Cipher Algorithm AES-256 + * - SB_PRV_RET_UNSUPPORTED_ALGO: Unsupported algorithm specified + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Returns the Cipher algorithm according to the argument + * - Convert SB-Lib Cipher algorithm type to Crypto IP-Driver Cipher algorithm value + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_PRV_RET_UNSUPPORTED_ALGO + * -# switch (type & #SB_PRV_TLV_TYPE_CRYPTO_ALGO_MASK) + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES128, Set CIP_DRV_CIPHER_ALGO_AES128 to cip_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES192, Set CIP_DRV_CIPHER_ALGO_AES192 to cip_algo + * -# type == #SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES256, Set CIP_DRV_CIPHER_ALGO_AES256 to cip_algo + * -# In the default case, do nothing + * -# Return cip_algo + * + * \callgraph + *********************************************************************************************************************/ +static uint32_t cmn_drv_get_img_cip_info_algo(const uint32_t type) +{ + uint32_t cip_algo = SB_PRV_RET_UNSUPPORTED_ALGO; + + switch (type & SB_PRV_TLV_TYPE_CRYPTO_ALGO_MASK) + { + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES128: + cip_algo = CIP_DRV_CIPHER_ALGO_AES128; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES192: + cip_algo = CIP_DRV_CIPHER_ALGO_AES192; + break; + case SB_PRV_TLV_TYPE_CRYPTO_ALGO_AES256: + cip_algo = CIP_DRV_CIPHER_ALGO_AES256; + break; + default: /* In the default case, return SB_PRV_RET_UNSUPPORTED_ALGO */ + break; + } + + return cip_algo; +} +/********************************************************************************************************************** +* End of function cmn_drv_get_img_cip_info_algo() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : cmn_drv_get_img_cip_info_mode +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBCommonAPIsInternal + * \brief Get Cipher mode + * \param [in] type Cipher mode type + * \return + * - CIP_DRV_CIPHER_MODE_ECB: Cipher mode ECB + * - CIP_DRV_CIPHER_MODE_CBC: Cipher mode CBC + * - CIP_DRV_CIPHER_MODE_CFB: Cipher mode CFB + * - CIP_DRV_CIPHER_MODE_OFB: Cipher mode OFB + * - CIP_DRV_CIPHER_MODE_CTR: Cipher mode CTR + * - SB_PRV_RET_UNSUPPORTED_ALGO: Unsupported algorithm specified + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Returns the Cipher mode according to the argument + * - Convert SB-Lib Cipher mode type to Crypto IP-Driver Cipher mod value + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_PRV_RET_UNSUPPORTED_ALGO + * -# switch (type & #SB_PRV_TLV_TYPE_CLS_ICI_MODE_MASK) + * -# type == #SB_PRV_TLV_TYPE_CLS_ICI_MODE_ECB, Set CIP_DRV_CIPHER_MODE_ECB to cip_mode + * -# type == #SB_PRV_TLV_TYPE_CLS_ICI_MODE_CBC, Set CIP_DRV_CIPHER_MODE_CBC to cip_mode + * -# type == #SB_PRV_TLV_TYPE_CLS_ICI_MODE_CFB, Set CIP_DRV_CIPHER_MODE_CFB to cip_mode + * -# type == #SB_PRV_TLV_TYPE_CLS_ICI_MODE_OFB, Set CIP_DRV_CIPHER_MODE_OFB to cip_mode + * -# type == #SB_PRV_TLV_TYPE_CLS_ICI_MODE_CTR, Set CIP_DRV_CIPHER_MODE_CTR to cip_mode + * -# In the default case, do nothing + * -# Return cip_mode + * + * \callgraph + *********************************************************************************************************************/ +static uint32_t cmn_drv_get_img_cip_info_mode(const uint32_t type) +{ + uint32_t cip_mode = SB_PRV_RET_UNSUPPORTED_ALGO; + + switch (type & SB_PRV_TLV_TYPE_CLS_ICI_MODE_MASK) + { + case SB_PRV_TLV_TYPE_CLS_ICI_MODE_ECB: + cip_mode = CIP_DRV_CIPHER_MODE_ECB; + break; + case SB_PRV_TLV_TYPE_CLS_ICI_MODE_CBC: + cip_mode = CIP_DRV_CIPHER_MODE_CBC; + break; + case SB_PRV_TLV_TYPE_CLS_ICI_MODE_CFB: + cip_mode = CIP_DRV_CIPHER_MODE_CFB; + break; + case SB_PRV_TLV_TYPE_CLS_ICI_MODE_OFB: + cip_mode = CIP_DRV_CIPHER_MODE_OFB; + break; + case SB_PRV_TLV_TYPE_CLS_ICI_MODE_CTR: + cip_mode = CIP_DRV_CIPHER_MODE_CTR; + break; + default: /* In the default case, return SB_PRV_RET_UNSUPPORTED_ALGO */ + break; + } + + return cip_mode; +} +/********************************************************************************************************************** +* End of function cmn_drv_get_img_cip_info_mode() +**********************************************************************************************************************/ + +/*===================================================================================================================== + End of file +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn_drv.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn_drv.h new file mode 100644 index 0000000000..3d5dff52e9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_cmn_drv.h @@ -0,0 +1,58 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_cmn_drv.h +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file defines the macros, types and declarations used in the common API for +* CIP (CryptoIP) drivers. +***********************************************************************************************************************/ + +#ifndef R_SB_CMN_DRV_H +/* Multiple inclusion protection macro */ +#define R_SB_CMN_DRV_H + +/*===================================================================================================================== + Public macro definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Public type definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global functions +=====================================================================================================================*/ +extern sb_ret_t r_sb_cmn_drv_set_cc_key_cert_param (const st_sb_key_cert_t * const p_key_cert_st, + const st_sb_tlv_t * const p_img_pk_hash_tlv, + const st_sb_tlv_t * const p_sign_pk_tlv, + const st_sb_tlv_t * const p_sign_tlv, + st_cip_drv_cc_key_cert_param_t* const p_cc_key_cert_param); +extern sb_ret_t r_sb_cmn_drv_set_cc_code_cert_param (const st_sb_code_cert_t * const p_code_cert_st, + const uint32_t img_addr, + const st_sb_tlv_t * const p_sign_pk_tlv, + const st_sb_tlv_t * const p_sign_tlv, + const st_sb_tlv_t * const p_img_hash_tlv, + st_cip_drv_cc_code_cert_param_t* const p_cc_code_cert_param); +extern sb_ret_t r_sb_cmn_drv_set_cipher_img_param (const st_sb_code_cert_t * const p_code_cert_st, + const st_sb_tlv_t * const p_img_cip_info, + const st_sb_tlv_t * const p_img_cip_iv, + const sb_bool_t is_overwrite_image, + const uint32_t timing, + st_cip_drv_cipher_img_param_t * const p_cipher_img_param); +extern sb_ret_t r_sb_cmn_drv_get_sb_ret_from_cip_ret (const cip_drv_ret_t cip_ret); +extern uint32_t r_sb_cmn_drv_get_mac_algo_from_sb_mac_type (const e_sb_mac_type_t mac_type); + +#endif /* R_SB_CMN_DRV_H */ +/*===================================================================================================================== + End of File +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_manifest.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_manifest.c new file mode 100644 index 0000000000..3681fccab1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_manifest.c @@ -0,0 +1,617 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** +* \file : r_sb_manifest.c +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : None(Independ devices) +* \par Description : This file implements the Manifest module APIs. +***********************************************************************************************************************/ + +/*!*********************************************************** + * \addtogroup SBLIBManifest + * \{ + * \addtogroup SBLIBManifestTypes Manifest Types + * \addtogroup SBLIBManifestDefinesInternal Manifest Internal Definitions + * \addtogroup SBLIBManifestTypesInternal Manifest Internal Types + * \addtogroup SBLIBManifestAPIsInternal Manifest Internal APIs + * \}********************************************************/ + +/*===================================================================================================================== + Includes , "Project Includes" +=====================================================================================================================*/ +#include +#include "r_sb_build_config.h" +#include "r_sb_api.h" +#include "r_sb_cmn.h" +#include "r_sb_manifest.h" + +/*===================================================================================================================== + Private macro definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBManifestDefinesInternal + * \{ + * \addtogroup group_manifest_common + * \}*****************************************************************/ +/**\addtogroup group_manifest_common ManifestCommon */ +/*! \{*/ +#define SB_PRV_MANI_TLV_LEN_OFFSET (SB_PRV_MANI_HEADER_SIZE) /**< Manifest TLV length offset */ +/** Start position of manifest TLV */ +#define SB_PRV_MANI_TLV_TOP_OFFSET ((SB_PRV_MANI_TLV_LEN_OFFSET) + (SB_PRV_MANI_TLV_LEN_SIZE)) + +/** Magic number unique to Key Certificate */ +#define SB_PRV_KEY_CERT_HEADER_MAGIC (0x6b657963UL) +/** Major and minor versions of key Certificate */ +#define SB_PRV_KEY_CERT_HEADER_VERSION (0x00010000UL) + +/** Magic number unique to Code Certificate */ +#define SB_PRV_CODE_CERT_HEADER_MAGIC (0x636f6463UL) +/** Major and minor versions of Code Certificate */ +#define SB_PRV_CODE_CERT_HEADER_VERSION (0x00010000UL) + +#define SB_PRV_TLV_TL_TYPE_MASK (0xFFFFFF00UL) /**< Type Mask of TLV Type & Length */ +#define SB_PRV_TLV_TL_LEN_MASK (0x000000FFUL) /**< Length Mask of TLV Type & Length */ + +#define SB_PRV_BYTES_OF_WORD (4UL) /**< Byte size in a WORD */ +/*! \}*/ + +/*===================================================================================================================== + Private type definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBManifestTypesInternal + * \{******************************************************************/ + +/*! \}*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Private global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Private function prototypes +=====================================================================================================================*/ + +/*===================================================================================================================== + Public function definitions +=====================================================================================================================*/ +/********************************************************************************************************************** +* Function Name : r_sb_mani_set_key_cert_st +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBManifestAPIsInternal + * \brief Set value in key certificate structure + * \param [in] p_key_cert Start address of Key Certificate + * \param [out] p_key_cert_st Start address of Key Certificate Structure + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Set value in key certificate structure + * - Set the starting address of the header of the key certificate, the length of the TLV, + * and the starting address of the TLV + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_key_cert) && (NULL != p_key_cert_st) + * -# Cast the argument p_key_cert to #st_sb_key_cert_header_t* type and set it to p_key_cert_st->p_header + * -# Cast the #SB_PRV_MANI_TLV_LEN_OFFSET address of the argument p_key_cert to uint32_t* type and set it to + * p_key_cert_st->tlv_len + * -# Set p_key_cert_st->p_tlv_top to #SB_PRV_MANI_TLV_TOP_OFFSET address of argument p_key_cert + * -# Set ret to #SB_RET_SUCCESS + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_mani_set_key_cert_st(const uint8_t* const p_key_cert, st_sb_key_cert_t* const p_key_cert_st) +{ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + if ((NULL != p_key_cert) && (NULL != p_key_cert_st)) + { + /* Casting from pointer to pointer is no problem */ + p_key_cert_st->p_header = (const st_sb_key_cert_header_t*)p_key_cert; + /* Casts that do not exceed the size of the type are fine */ + p_key_cert_st->tlv_len = *(const uint32_t*)(&p_key_cert[SB_PRV_MANI_TLV_LEN_OFFSET]); + p_key_cert_st->p_tlv_top = &p_key_cert[SB_PRV_MANI_TLV_TOP_OFFSET]; + + ret = SB_RET_SUCCESS; + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_mani_set_key_cert_st() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_mani_set_code_cert_st +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBManifestAPIsInternal + * \brief Set value in code certificate structure + * \param [in] p_code_cert Start address of Code Certificate + * \param [out] p_code_cert_st Start address of Code Certificate Structure + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Set value in code certificate structure + * - Set the starting address of the header of the code certificate, the length of the TLV, + * and the starting address of the TLV + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_code_cert) && (NULL != p_code_cert_st) + * -# Cast the argument p_code_cert to #st_sb_code_cert_header_t* type and set it to p_code_cert_st->p_header + * -# Cast the #SB_PRV_MANI_TLV_LEN_OFFSET address of the argument p_code_cert to uint32_t* type and set it to + * p_code_cert_st->tlv_len + * -# Set p_code_cert_st->p_tlv_top to #SB_PRV_MANI_TLV_TOP_OFFSET address of argument p_code_cert + * -# Set ret to #SB_RET_SUCCESS + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_mani_set_code_cert_st(const uint8_t* const p_code_cert, st_sb_code_cert_t* const p_code_cert_st) +{ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + if ((NULL != p_code_cert) && (NULL != p_code_cert_st)) + { + /* Casting from pointer to pointer is no problem */ + p_code_cert_st->p_header = (const st_sb_code_cert_header_t*)p_code_cert; + /* Casts that do not exceed the size of the type are fine */ + p_code_cert_st->tlv_len = *(const uint32_t*)(&p_code_cert[SB_PRV_MANI_TLV_LEN_OFFSET]); + p_code_cert_st->p_tlv_top = &p_code_cert[SB_PRV_MANI_TLV_TOP_OFFSET]; + + ret = SB_RET_SUCCESS; + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_mani_set_code_cert_st() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_mani_chk_key_cert +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBManifestAPIsInternal + * \brief Check the setting value of the key certificate structure + * \param [in] p_key_cert_st Start address of Key Certificate Structure + * \param [in] key_cert_len_max Maximum byte length that Key Certificate can take + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_INVALID_ARG: Invalid argument entered + * - #SB_RET_ERR_MANI_INVALID_MAGIC: Incorrect magic number is set + * - #SB_RET_ERR_MANI_UNSUPPORTED_VERSION: Unsupported version is set + * - #SB_RET_ERR_MANI_OUT_OF_RANGE_LEN: Out of range TLV Length is set + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Check that the magic number in the key certificate header is the correct value + * - Check that the key certificate header's manifest version is the currently supported version + * - Check that Maximum byte length that Key Certificate can take is set within the normal range + * - Check that the length of the TLV is within the length of the key certificate + * excluding the header and size data length + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_key_cert_st) && (NULL != p_key_cert_st->p_header) + * -# If (#SB_PRV_KEY_CERT_HEADER_MAGIC == p_key_cert_st->p_header->magic) + * -# If (#SB_PRV_KEY_CERT_HEADER_VERSION == p_key_cert_st->p_header->manifest_version) + * -# If (key_cert_len_max >= #SB_MANIFEST_LEN_MIN) && (key_cert_len_max <= #SB_MANIFEST_LEN_MAX) + * -# If (p_key_cert_st->tlv_len <= (key_cert_len_max - #SB_PRV_MANI_HEADER_SIZE - #SB_PRV_MANI_TLV_LEN_SIZE)) + * -# Set ret to #SB_RET_SUCCESS + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_OUT_OF_RANGE_LEN + * -# Else + * -# Set ret to #SB_RET_ERR_INVALID_ARG + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_UNSUPPORTED_VERSION + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_INVALID_MAGIC + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_mani_chk_key_cert(const st_sb_key_cert_t* const p_key_cert_st, const uint32_t key_cert_len_max) +{ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + /* Check NULL */ + if ((NULL != p_key_cert_st) && (NULL != p_key_cert_st->p_header)) + { + /* Check magic */ + if (SB_PRV_KEY_CERT_HEADER_MAGIC == p_key_cert_st->p_header->magic) + { + /* Check version */ + if (SB_PRV_KEY_CERT_HEADER_VERSION == p_key_cert_st->p_header->manifest_version) + { + /* Check TLV len max */ + if ((key_cert_len_max >= SB_MANIFEST_LEN_MIN) && (key_cert_len_max <= SB_MANIFEST_LEN_MAX)) + { + /* Check TLV len */ + if (p_key_cert_st->tlv_len <= ((key_cert_len_max - SB_PRV_MANI_HEADER_SIZE) - + SB_PRV_MANI_TLV_LEN_SIZE)) + { + /* All checks passed. Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + else + { + /* Invalid TLV len */ + ret = SB_RET_ERR_MANI_OUT_OF_RANGE_LEN; + } + } + else + { + /* Invalid TLV len max */ + ret = SB_RET_ERR_INVALID_ARG; + } + } + else + { + /* Invalid version */ + ret = SB_RET_ERR_MANI_UNSUPPORTED_VERSION; + } + } + else + { + /* Invalid magic */ + ret = SB_RET_ERR_MANI_INVALID_MAGIC; + } + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_mani_chk_key_cert() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_mani_chk_code_cert +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBManifestAPIsInternal + * \brief Check the setting value of the code certificate structure + * \param [in] p_code_cert_st Start address of Code Certificate Structure + * \param [in] code_cert_len_max Maximum byte length that Code Certificate can take + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_INVALID_ARG: Invalid argument entered + * - #SB_RET_ERR_INVALID_ALIGNMENT: Data entered with incorrect alignment + * - #SB_RET_ERR_MANI_INVALID_MAGIC: Incorrect magic number is set + * - #SB_RET_ERR_MANI_UNSUPPORTED_VERSION: Unsupported version is set + * - #SB_RET_ERR_MANI_OUT_OF_RANGE_LEN: Out of range TLV Length is set + * - #SB_RET_ERR_MANI_INVALID_IMAGE_LEN: An invalid image length is set + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Check that the magic number in the code certificate header is the correct value + * - Check that the code certificate header's manifest version is the currently supported version + * - Check the image size is a multiple of 16 + * - Check that Maximum byte length that Code Certificate can take is set within the normal range + * - Check that the length of the TLV is within the length of the code certificate + * excluding the header and size data length + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_code_cert_st) && (NULL != p_code_cert_st->p_header) + * -# If (#SB_PRV_CODE_CERT_HEADER_MAGIC == p_code_cert_st->p_header->magic) + * -# If (#SB_PRV_CODE_CERT_HEADER_VERSION == p_code_cert_st->p_header->manifest_version) + * -# If (p_code_cert_st->p_header->dest_addr & #SB_PRV_REMAINDER_DIV4) == 0UL + * -# If (p_code_cert_st->p_header->img_len & #SB_PRV_REMAINDER_DIV16) == 0UL + * -# If (code_cert_len_max >= #SB_MANIFEST_LEN_MIN) && (code_cert_len_max <= #SB_MANIFEST_LEN_MAX) + * -# If (p_code_cert_st->tlv_len <= ((code_cert_len_max - #SB_PRV_MANI_HEADER_SIZE) - + * #SB_PRV_MANI_TLV_LEN_SIZE)) + * -# Set ret to #SB_RET_SUCCESS. + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_OUT_OF_RANGE_LEN + * -# Else + * -# Set ret to #SB_RET_ERR_INVALID_ARG + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_INVALID_IMAGE_LEN + * -# Else + * -# Set ret to #SB_RET_ERR_INVALID_ALIGNMENT + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_UNSUPPORTED_VERSION + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_INVALID_MAGIC + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_mani_chk_code_cert(const st_sb_code_cert_t* const p_code_cert_st, const uint32_t code_cert_len_max) +{ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + /* Check NULL */ + if ((NULL != p_code_cert_st) && (NULL != p_code_cert_st->p_header)) + { + /* Check magic */ + if (SB_PRV_CODE_CERT_HEADER_MAGIC == p_code_cert_st->p_header->magic) + { + /* Check version */ + if (SB_PRV_CODE_CERT_HEADER_VERSION == p_code_cert_st->p_header->manifest_version) + { + /* Check image alignment */ + if ((p_code_cert_st->p_header->dest_addr & SB_PRV_REMAINDER_DIV4) == 0UL) + { + /* Check image length */ + if ((p_code_cert_st->p_header->img_len & SB_PRV_REMAINDER_DIV16) == 0UL) + { + /* Check TLV len max */ + if ((code_cert_len_max >= SB_MANIFEST_LEN_MIN) && (code_cert_len_max <= SB_MANIFEST_LEN_MAX)) + { + /* Check TLV len */ + if (p_code_cert_st->tlv_len <= ((code_cert_len_max - SB_PRV_MANI_HEADER_SIZE) - + SB_PRV_MANI_TLV_LEN_SIZE)) + { + /* All checks passed. Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + else + { + /* Invalid TLV len */ + ret = SB_RET_ERR_MANI_OUT_OF_RANGE_LEN; + } + } + else + { + /* Invalid TLV len max */ + ret = SB_RET_ERR_INVALID_ARG; + } + } + else + { + /* Invalid image length */ + ret = SB_RET_ERR_MANI_INVALID_IMAGE_LEN; + } + } + else + { + /* Invalid image alignment */ + ret = SB_RET_ERR_INVALID_ALIGNMENT; + } + } + else + { + /* Invalid version */ + ret = SB_RET_ERR_MANI_UNSUPPORTED_VERSION; + } + } + else + { + /* Invalid magic */ + ret = SB_RET_ERR_MANI_INVALID_MAGIC; + } + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_mani_chk_code_cert() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : r_sb_mani_parse_tlvs +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBManifestAPIsInternal + * \brief Search TLV of specified type from TLV field + * \param [in] p_top Start address of TLV field + * \param [in] tlv_len TLV field length + * \param [in] num_of_search_type Number of search type + * \param [in] p_search_types Start address of search TLV type \n * Set the same number of search + * targets as the number specified in num_of_search_type + * \param [out] p_tlvs Start address of the structure that stores the parsed TLV \n * Allocate + * the same number of arrays as the number specified in num_of_search_type + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_MANI_TLV_INVALID_LEN: The length of the TLV field has a size that exceeds the end of + * the manifest. + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Search TLV of specified type from TLV field + * - If the target type is found, set the value to p_tlvs at the same index as p_search_types + * - If the target type is not found, set NULL to val member of p_tlvs + * - Terminate search when all search targets are found or parsed to end of TLV field + * - Return #SB_RET_SUCCESS even if there is no target + * - If the end of the TLV field is exceeded during parsing, return #SB_RET_ERR_MANI_TLV_INVALID_LEN + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_top) && (NULL != p_search_types) && (NULL != p_tlvs) + * -# Set 0 to offset + * -# Set 0 to hit_cnt + * -# Loop while hit_cnt is smaller than num_of_search_type and offset is smaller than tlv_len + * -# Mask the type value from the Type & Length field and set it to type + * -# Mask the Length value of the Type & Length field, and set the value changed from WORD to BYTE to byte_len + * -# Set 0 to search_i + * -# Loop while search_i is less than num_of_search_type + * -# If (type & p_search_types[search_i].mask) == + * (p_search_types[search_i].type & p_search_types[search_i].mask) + * -# If NULL == p_tlvs[search_i].p_val + * -# Set type to p_tlvs[i].type + * -# Set byte_len to p_tlvs[i].byte_len + * -# Set the start address of the value field to p_tlvs[i].p_val + * -# Increment hit_cnt + * -# Else + * -# Do nothing + * -# break + * -# Else + * -# Do nothing + * -# Increment search_i + * -# Add the value obtained by adding byte_len to #SB_PRV_TLV_TL_SIZE to offset + * -# If (offset > tlv_len) + * -# Set #SB_RET_ERR_MANI_TLV_INVALID_LEN to ret + * -# Else + * -# Set ret to #SB_RET_SUCCESS + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +sb_ret_t r_sb_mani_parse_tlvs(const uint8_t* const p_top, const uint32_t tlv_len, const uint32_t num_of_search_type, + const st_sb_search_tlv_type_t* const p_search_types, st_sb_tlv_t* const p_tlvs) +{ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + uint32_t offset; + uint32_t search_i; + uint32_t type; + uint32_t byte_len; + uint32_t hit_cnt; + + if ((NULL != p_top) && (NULL != p_search_types) && (NULL != p_tlvs)) + { + /* Initialize before parse */ + offset = 0UL; + hit_cnt = 0UL; + for (search_i = 0UL; search_i < num_of_search_type; search_i++) + { + p_tlvs[search_i].p_val = NULL; + } + + while ((hit_cnt < num_of_search_type) && (offset < tlv_len)) + { + /* Get Type&Length field */ + /* Casts that do not exceed the size of the type are fine */ + type = ((*(const uint32_t*)(&p_top[offset])) & SB_PRV_TLV_TL_TYPE_MASK); + /* Same cast as above */ + byte_len = ((*(const uint32_t*)(&p_top[offset])) & SB_PRV_TLV_TL_LEN_MASK) * SB_PRV_BYTES_OF_WORD; + + /* Search type table */ + search_i = 0UL; + while (search_i < num_of_search_type) + { + if ((type & p_search_types[search_i].mask) == + (p_search_types[search_i].type & p_search_types[search_i].mask)) + { + if (NULL == p_tlvs[search_i].p_val) + { + p_tlvs[search_i].type = type; + p_tlvs[search_i].byte_len = byte_len; + /* Casting from pointer to pointer is no problem */ + p_tlvs[search_i].p_val = (const uint32_t*)(&p_top[offset + SB_PRV_TLV_TL_SIZE]); + hit_cnt++; + } + else + { + /* Target type already found. Do nothing */ + } + } + else + { + /* Do nothing */ + } + search_i++; + } + + /* Next TLV */ + offset += (SB_PRV_TLV_TL_SIZE + byte_len); + } + + /* Check TLV total length over */ + if (offset > tlv_len) + { + ret = SB_RET_ERR_MANI_TLV_INVALID_LEN; + } + else + { + /* Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +/********************************************************************************************************************** +* End of function r_sb_mani_parse_tlvs() +**********************************************************************************************************************/ + +/*===================================================================================================================== + Private function definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + End of file +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_sb.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_sb.c new file mode 100644 index 0000000000..cb6ddf168e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_sb.c @@ -0,0 +1,868 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_sb.c +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file implements the SecureBoot module APIs. +**********************************************************************************************************************/ + +/*!*********************************************************** + * \addtogroup SBLIBSecureBoot + * \{ + * \addtogroup SBLIBSecureBootAPIs SecureBoot APIs + * \addtogroup SBLIBSecureBootDefinesInternal SecureBoot Internal Definitions + * \addtogroup SBLIBSecureBootAPIsInternal SecureBoot Internal APIs + * \}********************************************************/ + +/*===================================================================================================================== + Includes , "Project Includes" +=====================================================================================================================*/ +#include +#include "r_cip_drv_api.h" +#include "r_sb_build_config.h" +#include "r_sb_api.h" +#include "r_sb_manifest.h" +#include "r_sb_cmn.h" +#include "r_sb_cmn_drv.h" +#include "r_sb_sb.h" + +/*===================================================================================================================== + Private macro definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBSecureBootDefinesInternal + * \{ + * \addtogroup group_tlv_search_type + * \addtogroup group_tlv_search_kc + * \addtogroup group_tlv_search_sb_cc + * \addtogroup group_tlv_search_ci + * \addtogroup group_tlv_search_sb_mac + * \}*****************************************************************/ + +/** Search by certificate chain verification */ +/**\addtogroup group_tlv_search_type TLV search type and mask */ +/*! \{*/ +/** Class & Use type of OEM root public key */ +#define SB_PRV_TLV_KEY_OEM_ROOT_PK_TYPE (SB_PRV_TLV_TYPE_CLS_KEY | SB_PRV_TLV_TYPE_CLS_KEY_UT_OEM_ROOT_PK) +/** Class & Use type of Image public key */ +#define SB_PRV_TLV_KEY_IMG_PK_TYPE (SB_PRV_TLV_TYPE_CLS_KEY | SB_PRV_TLV_TYPE_CLS_KEY_UT_IMG_PK) +/** Class mask & Use type mask of key */ +#define SB_PRV_TLV_KEY_MASK (SB_PRV_TLV_TYPE_CLS_MASK | SB_PRV_TLV_TYPE_CLS_KEY_UT_MASK) + +/** Class & Use type of Image public key hash */ +#define SB_PRV_TLV_HASH_IMG_PK_TYPE (SB_PRV_TLV_TYPE_CLS_HASH | SB_PRV_TLV_TYPE_CLS_HASH_UT_IMG_PK) +/** Class & Use type of Image hash */ +#define SB_PRV_TLV_HASH_IMG_TYPE (SB_PRV_TLV_TYPE_CLS_HASH | SB_PRV_TLV_TYPE_CLS_HASH_UT_IMG) +/** Class & Use type of Image hash */ +#define SB_PRV_TLV_HASH_ENCIMG_TYPE (SB_PRV_TLV_TYPE_CLS_HASH | SB_PRV_TLV_TYPE_CLS_HASH_UT_ENCIMG) +/** Class mask & Use type mask of Image public key hash */ +#define SB_PRV_TLV_HASH_MASK (SB_PRV_TLV_TYPE_CLS_MASK | SB_PRV_TLV_TYPE_CLS_HASH_UT_MASK) + +/** Class & Use type of Key Certificate signature */ +#define SB_PRV_TLV_SIGN_CERT_TYPE (SB_PRV_TLV_TYPE_CLS_SIGN | SB_PRV_TLV_TYPE_CLS_SIGN_UT_CERT) +/** Class & Use type of Code Certificate and image signature */ +#define SB_PRV_TLV_SIGN_CERT_IMG_TYPE (SB_PRV_TLV_TYPE_CLS_SIGN | SB_PRV_TLV_TYPE_CLS_SIGN_UT_CODE_CERT_AND_IMG) +/** Class & Use type of Code Certificate and encryption image signature */ +#define SB_PRV_TLV_SIGN_CERT_ENCIMG_TYPE (SB_PRV_TLV_TYPE_CLS_SIGN | SB_PRV_TLV_TYPE_CLS_SIGN_UT_CODE_CERT_AND_ENCIMG) +/** Class mask & Use type mask of signature */ +#define SB_PRV_TLV_SIGN_MASK (SB_PRV_TLV_TYPE_CLS_MASK | SB_PRV_TLV_TYPE_CLS_SIGN_UT_MASK) + +/** Class & Use type of Code Certificate + Image MAC */ +#define SB_PRV_TLV_MAC_CERT_IMG_TYPE (SB_PRV_TLV_TYPE_CLS_MAC | SB_PRV_TLV_TYPE_CLS_MAC_UT_CODE_CERT_AND_IMG) +/** Class & Use type of Code Certificate + Encrypted Image MAC */ +#define SB_PRV_TLV_MAC_CERT_ENCIMG_TYPE (SB_PRV_TLV_TYPE_CLS_MAC | SB_PRV_TLV_TYPE_CLS_MAC_UT_CODE_CERT_AND_ENCIMG) +/** Class mask & Use type mask of MAC */ +#define SB_PRV_TLV_MAC_MASK (SB_PRV_TLV_TYPE_CLS_MASK | SB_PRV_TLV_TYPE_CLS_MAC_UT_MASK) + +/** Class & Use type of Image Cipher IV */ +#define SB_PRV_TLV_IMG_CIP_IV_TYPE (SB_PRV_TLV_TYPE_CLS_IV | SB_PRV_TLV_TYPE_CLS_IV_UT_IMG_CIPHER) +/** Class & Use type of Temp Image Decryption IV */ +#define SB_PRV_TLV_CI_TMP_IMG_DEC_IV_TYPE (SB_PRV_TLV_TYPE_CLS_IV | SB_PRV_TLV_TYPE_CLS_IV_UT_TMP_IMG_DEC) +/** Class mask & Use type mask of Temp Image Decryption IV */ +#define SB_PRV_TLV_IV_MASK (SB_PRV_TLV_TYPE_CLS_MASK | SB_PRV_TLV_TYPE_CLS_IV_UT_MASK) + +/** Class & Use type of Image Cipher Info */ +#define SB_PRV_TLV_IMG_CIP_INFO_TYPE (SB_PRV_TLV_TYPE_CLS_ICI | SB_PRV_TLV_TYPE_CLS_ICI_UT_IMG_ENC_DEC) +/** Class & Use type of Temp Image Decryption Info */ +#define SB_PRV_TLV_CI_TMP_IMG_DEC_INFO_TYPE (SB_PRV_TLV_TYPE_CLS_ICI | SB_PRV_TLV_TYPE_CLS_ICI_UT_TMP_IMG_DEC) +/** Class mask & Use type mask of Image Cipher Info */ +#define SB_PRV_TLV_ICI_MASK (SB_PRV_TLV_TYPE_CLS_MASK | SB_PRV_TLV_TYPE_CLS_ICI_UT_MASK) +/*! \}*/ + +/** key certificate TLV to search SecureBoot & CheckIntegrity */ +/**\addtogroup group_tlv_search_kc TLV search Key Certificate */ +/*! \{*/ +#define SB_PRV_TLV_KEY_CERT_KEY_OEM_ROOT_PK_IDX (0U) /**< Index of OEM root public key */ +#define SB_PRV_TLV_KEY_CERT_KEY_IMG_PK_IDX (1U) /**< Index of Image public key */ +#define SB_PRV_TLV_KEY_CERT_HASH_IMG_PK_IDX (2U) /**< Index of Image public key hash */ +#define SB_PRV_TLV_KEY_CERT_SIGN_CERT_IDX (3U) /**< Index of Key Certificate signature */ +#define SB_PRV_TLV_KEY_CERT_NUM (4U) /**< Number of Key Certificate TLVs */ +/*! \}*/ + +/** code certificate TLV to search by SecureBoot(certificate chain verification) */ +/**\addtogroup group_tlv_search_sb_cc TLV search Code Certificate for Certificate Chain verification */ +/*! \{*/ +#define SB_PRV_TLV_CC_CODE_CERT_KEY_IMG_PK_IDX (0U) /**< Index of Image public key */ +#define SB_PRV_TLV_CC_CODE_CERT_HASH_IMG_IDX (1U) /**< Index of Image hash */ +#define SB_PRV_TLV_CC_CODE_CERT_HASH_ENCIMG_IDX (2U) /**< Index of encryption image hash */ +#define SB_PRV_TLV_CC_CODE_CERT_IMG_CIP_INFO_IDX (3U) /**< Index of Image Cipher Info */ +#define SB_PRV_TLV_CC_CODE_CERT_IMG_CIP_IV_IDX (4U) /**< Index of Image Cipher IV */ +#define SB_PRV_TLV_CC_CODE_CERT_SIGN_CERT_IDX (5U) /**< Index of Certificate signature */ +#define SB_PRV_TLV_CC_CODE_CERT_SIGN_IMG_IDX (6U) /**< Index of Code Certificate and image signature */ +#define SB_PRV_TLV_CC_CODE_CERT_SIGN_ENCIMG_IDX (7U) /**< Index of Code Certificate and encryption image signature */ +#define SB_PRV_TLV_CC_CODE_CERT_NUM (8U) /**< Number of Code Certificate TLVs for SecureBoot */ +/*! \}*/ + +/** code certificate TLV to search by SecureBoot(MAC verification) */ +/**\addtogroup group_tlv_search_sb_mac TLV search Code certificate for MAC verification */ +/*! \{*/ +#define SB_PRV_TLV_MAC_IMG_CIP_INFO_IDX (0U) /**< Index number of Image Cipher Info */ +#define SB_PRV_TLV_MAC_IMG_CIP_IV_IDX (1U) /**< Index number of Image Cipher IV */ +#if (SB_CFG_SB_CERT_CHAIN_USE_IMG_PK == 1U) /* (Use only when SB_CFG_SB_CERT_CHAIN_USE_IMG_PK is Enable) */ +#define SB_PRV_TLV_MAC_KEY_IMG_PK_IDX (2U) /**< Index number of Image public key */ +#define SB_PRV_TLV_MAC_NUM (3U) /**< Number of Code Certificate TLVs for MAC verify */ +#else /* #if (SB_CFG_SB_CERT_CHAIN_USE_IMG_PK == 1U) */ +#define SB_PRV_TLV_MAC_NUM (2U) /**< Number of Code Certificate TLVs for MAC verify */ +#endif /* #if (SB_CFG_SB_CERT_CHAIN_USE_IMG_PK == 1U) */ +/*! \}*/ + +/** code certificate TLV to search by CheckIntegrity */ +/**\addtogroup group_tlv_search_ci TLV search Code Certificate for CheckIntegrity */ +/*! \{*/ +#define SB_PRV_TLV_CI_CODE_CERT_KEY_IMG_PK_IDX (0U) /**< Index of Image public key */ +#define SB_PRV_TLV_CI_CODE_CERT_HASH_IMG_IDX (1U) /**< Index of Image hash */ +#define SB_PRV_TLV_CI_CODE_CERT_IMG_CIP_INFO_IDX (2U) /**< Index of Image Cipher Info */ +#define SB_PRV_TLV_CI_CODE_CERT_IMG_CIP_IV_IDX (3U) /**< Index of Image Cipher IV */ +#define SB_PRV_TLV_CI_CODE_CERT_TMP_IMG_DEC_INFO_IDX (4U) /**< Index of Temp Image Decryption Info */ +#define SB_PRV_TLV_CI_CODE_CERT_TMP_IMG_DEC_IV_IDX (5U) /**< Index of Temp Image Decryption IV */ +#define SB_PRV_TLV_CI_CODE_CERT_SIGN_CERT_IDX (6U) /**< Index of Certificate signature */ +#define SB_PRV_TLV_CI_CODE_CERT_SIGN_IMG_IDX (7U) /**< Index of Code Certificate and image signature */ +#define SB_PRV_TLV_CI_CODE_CERT_NUM (8U) /**< Number of Code Certificate TLVs for CheckIntegrity */ +/*! \}*/ + +/*===================================================================================================================== + Private type definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Private global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Private function prototypes +=====================================================================================================================*/ + +#if (SB_CFG_CHECK_INTEGRITY == 1U) +static sb_ret_t sb_check_check_integrity_tlv (const st_sb_tlv_t * const p_key_cert_tlvs, + const st_sb_tlv_t * const p_code_cert_tlvs); +#endif /* (SB_CFG_CHECK_INTEGRITY == 1U) */ + +#if (SB_CFG_SB_CERT_CHAIN_VERIFICATION == 1U) || (SB_CFG_CHECK_INTEGRITY == 1U) +static sb_ret_t sb_get_cc_tlv (const st_sb_key_cert_t * const p_key_cert_st, + const st_sb_code_cert_t * const p_code_cert_st, + const st_sb_search_tlv_type_t * const p_search_tlv_key_cert, + const uint32_t search_tlv_key_cert_num, + const st_sb_search_tlv_type_t * const p_search_tlv_code_cert, + const uint32_t search_tlv_code_cert_num, + st_sb_tlv_t * const p_key_cert_tlvs, + st_sb_tlv_t * const p_code_cert_tlvs); +#endif /* (SB_CFG_SB_CERT_CHAIN_VERIFICATION == 1U) || (SB_CFG_CHECK_INTEGRITY == 1U) */ + +/*===================================================================================================================== + Public function definitions +=====================================================================================================================*/ + +/********************************************************************************************************************** +* Function Name : r_sb_sb_check_integrity +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBSecureBootAPIsInternal + * \brief Verify the integrity of the image by certificate chain verification and create a MAC + * for the Code Certificate and the image with a HUK derived key + * \param [in] p_key_cert_st Start address of Key Certificate Structure + * \param [in] p_code_cert_st Start address of Code Certificate Structure + * \param [in] mac_type MAC algorithm type used to generate the MAC of the code certificate + * \param [out] p_tag Specify MAC tag storage address + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_SAME_IMAGE_VERSION: An image with the same version as the current image version is + * installed + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_MANI_TLV_FIELD_ERR: Missing required TLV field + * - #SB_RET_ERR_MANI_TLV_INVALID_LEN: The length of the TLV field has a size that exceeds the end of + * the manifest. + * - #SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM: There is a wrong combination of signature algorithms + * - #SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM: There is a wrong combination of signature algorithms + * - #SB_RET_ERR_CRYPTO_FAIL: Encryption failed + * - #SB_RET_ERR_CRYPTO_AUTH_FAIL: Verification failed + * - #SB_RET_ERR_CRYPTO_UNSUPPORTED_ALGORITHM: Unsupported algorithm + * - #SB_RET_ERR_CRYPTO_PARAM_ERR: Parameter error + * - #SB_RET_ERR_LOWER_IMAGE_VERSION: An image version lower than the current image version is installed + * \par Global Variables + * - None + * \par Call SB-Driver API + * - R_CIP_DRV_CheckImageVersion + * - R_CIP_DRV_PrcDeriveMacKeyFromHuk + * - R_CIP_DRV_PrcCheckIntegrity + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Check the value by parsing the TLV from the manifest + * - Parse the Image Cipher info TLV of the code certificate and check the value + * - Implement the following as a glitch countermeasure : + * - Add a flow counter before and after calling R_CIP_DRV_PrcCheckIntegrity + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# Initialize the variable cip_ret with CIP_DRV_RET_LOWER_IMAGE_VERSION + * -# Initialize the variable ret_ver with #SB_RET_ERR_LOWER_IMAGE_VERSION + * -# Set TLV search condition of Key Certificate to search_tlv_key_cert + * -# Set TLV search condition of Code Certificate to search_tlv_code_cert + * -# Set TLV search condition of Image Cipher Info to search_tlv_enc_img + * -# If (NULL != p_key_cert_st) && (NULL != p_code_cert_st) && (NULL != p_code_cert_st->p_header) && (NULL != p_tag) + * -# Get TLV for key certificate and code certificate with #sb_get_cc_tlv + * -# Set function result to ret + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set #SB_RET_ERR_INTERNAL_FAIL to ret + * -# Check certificate chain verification tlv with #sb_check_check_integrity_tlv + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set #SB_RET_ERR_INTERNAL_FAIL to ret + * -# Set key certificate driver parameters with #r_sb_cmn_drv_set_cc_key_cert_param + * -# Set function result to ret + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set #SB_RET_ERR_INTERNAL_FAIL to ret + * -# If the certificate signature value of the code certificate is not NULL + * -# Set the start address of the certificate signature TLV to p_code_cert_sign_tlv. + * -# Set the start address of the Image hash TLV to p_img_hash_tlv. + * -# Else + * -# Set the start address of the Encrypted Image Signature TLV to p_code_cert_sign_tlv. + * -# Set null to p_img_hash_tlv + * -# Set code certificate driver parameters with #r_sb_cmn_drv_set_cc_code_cert_param + * -# Set function result to ret + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set #SB_RET_ERR_INTERNAL_FAIL to ret + * -# If (p_code_cert_st->p_header->flags & #SB_PRV_CODE_CERT_HEADER_FLAGS_IMG_CIPHER_ENC) + * -# --- If #SB_CFG_IMAGE_ENC_DEC is enabled --- + * -# Set the address of img_param to p_img_param + * -# Set Image Cipher Info parameters with #r_sb_cmn_drv_set_cipher_img_param + * -# Set function result to ret + * -# --- Else #SB_CFG_IMAGE_ENC_DEC is enabled --- + * -# Set #SB_RET_ERR_UNSUPPORTED_FUNCTION to ret + * -# --- Endif #SB_CFG_IMAGE_ENC_DEC is enabled --- + * -# Else + * -# Set NULL to p_img_param + * -# Set ret to #SB_RET_SUCCESS + * -# If #SB_RET_SUCCESS == ret + * -# If (p_code_cert_st->p_header->flags & #SB_PRV_CODE_CERT_HEADER_FLAGS_TMP_IMG_DEC) + * -# --- If #SB_CFG_IMAGE_ENC_DEC is enabled --- + * -# Set the address of tmp_img_param to p_tmp_img_param + * -# Set Image Cipher Info parameters with #r_sb_cmn_drv_set_cipher_img_param + * -# Set function result to ret + * -# --- Else #SB_CFG_IMAGE_ENC_DEC is enabled --- + * -# Set #SB_RET_ERR_UNSUPPORTED_FUNCTION to ret + * -# --- Endif #SB_CFG_IMAGE_ENC_DEC is enabled --- + * -# Else + * -# Set NULL to p_tmp_img_param + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set ret to #SB_RET_ERR_INTERNAL_FAIL + * -# Call SB-Driver API R_CIP_DRV_CheckImageVersion + * -# Set SB-Driver API result to cip_ret + * -# Get the return code from the value of cpi_ret with #r_sb_cmn_drv_get_sb_ret_from_cip_ret + * -# Set function result to ret_ver + * -# To clear ret, set cip_ret to CIP_DRV_RET_FAIL + * -# If (#SB_RET_SUCCESS == ret_ver) || (#SB_RET_SAME_IMAGE_VERSION == ret_ver) + * -# Call SB-Driver API R_CIP_DRV_PrcDeriveMacKeyFromHuk + * -# Set SB-Driver API result to cip_ret + * -# Get the return code from the value of cpi_ret with #r_sb_cmn_drv_get_sb_ret_from_cip_ret + * -# Set function result to ret + * -# If #SB_RET_SUCCESS == ret + * -# Get MAC algorithm with #r_sb_cmn_drv_get_mac_algo_from_sb_mac_type + * -# Set function result to mac_algo + * -# To clear ret, set #SB_RET_ERR_INTERNAL_FAIL to ret and set CIP_DRV_RET_FAIL to cip_ret + * -# Add #SB_PRV_CMN_FC_CHECKINTEGRITY_CNT to flow counter with #r_sb_cmn_fc_add_counter + * -# Call SB-Driver API R_CIP_DRV_PrcCheckIntegrity + * -# Set SB-Driver API result to cip_ret + * -# Get the return code from the value of cpi_ret with #r_sb_cmn_drv_get_sb_ret_from_cip_ret + * -# Set function result to ret + * -# Add #SB_PRV_CMN_FC_CHECKINTEGRITY_CNT to flow counter with #r_sb_cmn_fc_add_counter + * -# If #SB_RET_SUCCESS == ret + * -# Set ret_ver to ret + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Set ret_ver to ret + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Return ret + * + * Note: The call graph below dose not include SB-Driver APIs. + * \callgraph + *********************************************************************************************************************/ +#if (SB_CFG_CHECK_INTEGRITY == 1U) +sb_ret_t r_sb_sb_check_integrity(const st_sb_key_cert_t* const p_key_cert_st, + const st_sb_code_cert_t* const p_code_cert_st, + const e_sb_mac_type_t mac_type, uint32_t* const p_tag) +{ + /*----------------------------------------------------------------------------------------------------------------- + Local variables + -----------------------------------------------------------------------------------------------------------------*/ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + sb_ret_t ret_ver = SB_RET_ERR_LOWER_IMAGE_VERSION; /* for version check */ + cip_drv_ret_t cip_ret = CIP_DRV_RET_LOWER_IMAGE_VERSION; + uint32_t mac_algo; + st_sb_tlv_t key_cert_tlvs[SB_PRV_TLV_KEY_CERT_NUM]; + st_sb_tlv_t code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_NUM]; + const st_sb_tlv_t * p_code_cert_sign_tlv; + const st_sb_tlv_t * p_img_hash_tlv; + st_cip_drv_cc_key_cert_param_t key_cert_param; + st_cip_drv_cc_code_cert_param_t code_cert_param; + st_cip_drv_cipher_img_param_t * p_img_param; + st_cip_drv_cipher_img_param_t * p_tmp_img_param; +#if (SB_CFG_IMAGE_ENC_DEC == 1U) + st_cip_drv_cipher_img_param_t img_param; + st_cip_drv_cipher_img_param_t tmp_img_param; +#endif /* (SB_CFG_IMAGE_ENC_DEC == 1U) */ + const st_sb_tlv_t * p_key_cert_signer_pk_tlv; + + const st_sb_search_tlv_type_t search_tlv_key_cert[SB_PRV_TLV_KEY_CERT_NUM] = + { + {SB_PRV_TLV_KEY_OEM_ROOT_PK_TYPE, SB_PRV_TLV_KEY_MASK}, /* KEY_CERT_KEY_OEM_ROOT_PK_IDX */ + {SB_PRV_TLV_KEY_IMG_PK_TYPE, SB_PRV_TLV_KEY_MASK}, /* KEY_CERT_KEY_IMG_PK_IDX */ + {SB_PRV_TLV_HASH_IMG_PK_TYPE, SB_PRV_TLV_HASH_MASK}, /* KEY_CERT_HASH_IMG_PK_IDX */ + {SB_PRV_TLV_SIGN_CERT_TYPE, SB_PRV_TLV_SIGN_MASK} /* KEY_CERT_SIGN_CERT_IDX */ + }; + + const st_sb_search_tlv_type_t search_tlv_code_cert[SB_PRV_TLV_CI_CODE_CERT_NUM] = + { + {SB_PRV_TLV_KEY_IMG_PK_TYPE, SB_PRV_TLV_KEY_MASK}, /* CI_CODE_CERT_KEY_IMG_PK_IDX */ + {SB_PRV_TLV_HASH_IMG_TYPE, SB_PRV_TLV_HASH_MASK}, /* CI_CODE_CERT_HASH_IMG_IDX */ + {SB_PRV_TLV_IMG_CIP_INFO_TYPE, SB_PRV_TLV_ICI_MASK}, /* CI_CODE_CERT_IMG_CIP_INFO_IDX */ + {SB_PRV_TLV_IMG_CIP_IV_TYPE, SB_PRV_TLV_IV_MASK}, /* CI_CODE_CERT_IMG_CIP_IV_IDX */ + {SB_PRV_TLV_CI_TMP_IMG_DEC_INFO_TYPE, SB_PRV_TLV_ICI_MASK}, /* CI_CODE_CERT_TMP_IMG_DEC_INFO_IDX */ + {SB_PRV_TLV_CI_TMP_IMG_DEC_IV_TYPE, SB_PRV_TLV_IV_MASK}, /* CI_CODE_CERT_TMP_IMG_DEC_IV_IDX */ + {SB_PRV_TLV_SIGN_CERT_TYPE, SB_PRV_TLV_SIGN_MASK}, /* CI_CODE_CERT_SIGN_CERT_IDX */ + {SB_PRV_TLV_SIGN_CERT_IMG_TYPE, SB_PRV_TLV_SIGN_MASK} /* CI_CODE_CERT_SIGN_IMG_IDX */ + }; + + /*----------------------------------------------------------------------------------------------------------------- + Function body + -----------------------------------------------------------------------------------------------------------------*/ + if ((NULL != p_key_cert_st) && (NULL != p_code_cert_st) && (NULL != p_code_cert_st->p_header) && (NULL != p_tag)) + { + /* Get TLVs */ + ret = sb_get_cc_tlv(p_key_cert_st, p_code_cert_st, + search_tlv_key_cert, SB_PRV_TLV_KEY_CERT_NUM, + search_tlv_code_cert, SB_PRV_TLV_CI_CODE_CERT_NUM, + key_cert_tlvs, code_cert_tlvs); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Check cert chain tlv */ + ret = sb_check_check_integrity_tlv(key_cert_tlvs, code_cert_tlvs); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Select kye cert signer public key TLV */ + p_key_cert_signer_pk_tlv = (NULL == key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_OEM_ROOT_PK_IDX].p_val) ? + (&key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_IMG_PK_IDX]) : + (&key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_OEM_ROOT_PK_IDX]); + + /* Set key certificate driver parameters */ + ret = r_sb_cmn_drv_set_cc_key_cert_param(p_key_cert_st, + &key_cert_tlvs[SB_PRV_TLV_KEY_CERT_HASH_IMG_PK_IDX], + p_key_cert_signer_pk_tlv, + &key_cert_tlvs[SB_PRV_TLV_KEY_CERT_SIGN_CERT_IDX], + &key_cert_param); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Set code certificate driver parameters */ + if (NULL != code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_CERT_IDX].p_val) + { + p_code_cert_sign_tlv = &code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_CERT_IDX]; + p_img_hash_tlv = &code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_HASH_IMG_IDX]; + } + else /* NULL != code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_IMG_IDX].p_val */ + { + p_code_cert_sign_tlv = &code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_IMG_IDX]; + p_img_hash_tlv = NULL; /* Does not use image hash TLV */ + } + + /* Set code certificate driver parameters */ + ret = r_sb_cmn_drv_set_cc_code_cert_param(p_code_cert_st, + p_code_cert_st->p_header->dest_addr, + &code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_KEY_IMG_PK_IDX], + p_code_cert_sign_tlv, + p_img_hash_tlv, + &code_cert_param); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Set driver parameters of image cipher */ + if ((p_code_cert_st->p_header->flags & SB_PRV_CODE_CERT_HEADER_FLAGS_IMG_CIPHER_ENC) != 0UL) + { +#if (SB_CFG_IMAGE_ENC_DEC == 1U) + p_img_param = &img_param; + ret = r_sb_cmn_drv_set_cipher_img_param(p_code_cert_st, + &code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_IMG_CIP_INFO_IDX], + &code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_IMG_CIP_IV_IDX], + SB_PRV_TRUE, + CIP_DRV_CIPHER_TIMING_AFTER_VERIFY, + p_img_param); +#else /* !(SB_CFG_IMAGE_ENC_DEC == 1U) */ + /* Code decryption not supported */ + ret = SB_RET_ERR_UNSUPPORTED_FUNCTION; +#endif /* (SB_CFG_IMAGE_ENC_DEC == 1U) */ + } + else + { + p_img_param = NULL; + + /* Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + + if (SB_RET_SUCCESS == ret) + { + /* Set driver parameters of temporary image decryption */ + if ((p_code_cert_st->p_header->flags & SB_PRV_CODE_CERT_HEADER_FLAGS_TMP_IMG_DEC) != 0UL) + { +#if (SB_CFG_IMAGE_ENC_DEC == 1U) + p_tmp_img_param = &tmp_img_param; + ret = r_sb_cmn_drv_set_cipher_img_param(p_code_cert_st, + &code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_TMP_IMG_DEC_INFO_IDX], + &code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_TMP_IMG_DEC_IV_IDX], + SB_PRV_TRUE, + CIP_DRV_CIPHER_TIMING_BEFORE_VERIFY, + p_tmp_img_param); +#else /* !(SB_CFG_IMAGE_ENC_DEC == 1U) */ + /* Code decryption not supported */ + ret = SB_RET_ERR_UNSUPPORTED_FUNCTION; +#endif /* (SB_CFG_IMAGE_ENC_DEC == 1U) */ + } + else + { + p_tmp_img_param = NULL; + } + + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Check image version */ + cip_ret = R_CIP_DRV_CheckImageVersion(p_code_cert_st->p_header->img_version, + p_code_cert_st->p_header->build_num); + ret_ver = r_sb_cmn_drv_get_sb_ret_from_cip_ret(cip_ret); + + /* Clear ret */ + cip_ret = CIP_DRV_RET_FAIL; + (void) cip_ret; + + if ((SB_RET_SUCCESS == ret_ver) || (SB_RET_SAME_IMAGE_VERSION == ret_ver)) + { + /* Call derive MAC Key from HUK */ + cip_ret = R_CIP_DRV_PrcDeriveMacKeyFromHuk(); + ret = r_sb_cmn_drv_get_sb_ret_from_cip_ret(cip_ret); + if (SB_RET_SUCCESS == ret) + { + /* get MAC algorithm */ + mac_algo = r_sb_cmn_drv_get_mac_algo_from_sb_mac_type(mac_type); + + /* Clear ret */ + cip_ret = CIP_DRV_RET_AUTH_FAIL; + (void) cip_ret; + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + /* Add verify count to flow counter */ + r_sb_cmn_fc_add_counter(SB_PRV_CMN_FC_CHECKINTEGRITY_CNT); + + /* Call check integrity */ + cip_ret = R_CIP_DRV_PrcCheckIntegrity(&key_cert_param, + &code_cert_param, + p_tmp_img_param, + p_img_param, + mac_algo, + p_tag); + ret = r_sb_cmn_drv_get_sb_ret_from_cip_ret(cip_ret); + r_sb_cmn_fc_add_counter(SB_PRV_CMN_FC_CHECKINTEGRITY_CNT); + if(SB_RET_SUCCESS == ret) + { + /* Set version check result(SUCCESS or SAME_IMAGE_VERSION) to ret */ + ret = ret_ver; + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Set version check result to ret */ + ret = ret_ver; + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* If there are null arguments, return SB_RET_ERR_INTERNAL_FAIL */ + } + + return ret; +} +#endif /* (SB_CFG_CHECK_INTEGRITY == 1U) */ +/********************************************************************************************************************** +* End of function r_sb_sb_check_integrity() +**********************************************************************************************************************/ + +/*===================================================================================================================== + Private function definitions +=====================================================================================================================*/ + +/********************************************************************************************************************** +* Function Name : sb_check_check_integrity_tlv +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBSecureBootAPIsInternal + * \brief Check the obtained TLV of Check Integrity + * \param [in] p_key_cert_tlvs Start address of Key Certificate TLVs + * \param [in] p_code_cert_tlvs Start address of Code Certificate TLVs + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_UNSUPPORTED_FUNCTION: Unsupported function executed + * - #SB_RET_ERR_MANI_TLV_FIELD_ERR: Missing required TLV fields + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Check that the TLV of the key certificate has Image public key Hash and Key Certificate signature + * - Confirm that the OEM root public key or Image public key is specified in the key class TLV of the + * key certificate. (NG if both are specified) + * - Confirm that Code Certificate TLV has signature verification public key + * - Confirm that Code Certificate TLV has signature + * - Confirm that Code Certificate TLV has image hash (When only the certificate is to be signed) + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_key_cert_tlvs) && (NULL != p_code_cert_tlvs) + * -# If the value of Image public key hash TLV of the key certificate is not NULL and + * the value of Key Certificate signature TLV is not NULL + * -# If the value of the OEM_ROOT_PK TLV of the key certificate is not NULL and + * the value of the Image public key TLV is NULL, or \n + * if the value of the OEM_ROOT_PK TLV of the key certificate is NULL and + * the value of the Image public key TLV is not NULL + * -# If the value of Image public key TLV of the code certificate is not NULL + * -# If only one of the following is non-NULL \n + * Certificate Signature TLV \n + * Certificate and Image Signature TLV \n + * -# If Signature TLV is Certificate only + * -# If only one of the following is non-NULL \n + * Image Hash TLV \n + * -# TLV field OK. Set ret to #SB_RET_SUCCESS + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_TLV_FIELD_ERR + * -# Else + * -# TLV field OK. Set ret to #SB_RET_SUCCESS + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_TLV_FIELD_ERR + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_TLV_FIELD_ERR + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_TLV_FIELD_ERR + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_TLV_FIELD_ERR + * -# Else + * -# Set ret to #SB_RET_ERR_MANI_TLV_FIELD_ERR + * -# --- If #SB_CFG_SB_CERT_CHAIN_USE_IMG_PK is disabled --- + * -# If (SB_RET_SUCCESS == ret) && + * (NULL != p_key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_IMG_PK_IDX].p_val) + * -# Set ret to #SB_RET_ERR_UNSUPPORTED_FUNCTION + * -# Else + * -# Do nothing + * -# --- Endif #SB_CFG_SB_CERT_CHAIN_USE_IMG_PK is disabled --- + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +#if (SB_CFG_CHECK_INTEGRITY == 1U) +static sb_ret_t sb_check_check_integrity_tlv(const st_sb_tlv_t* const p_key_cert_tlvs, + const st_sb_tlv_t* const p_code_cert_tlvs) +{ + /*----------------------------------------------------------------------------------------------------------------- + Local variables + -----------------------------------------------------------------------------------------------------------------*/ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + /*----------------------------------------------------------------------------------------------------------------- + Function body + -----------------------------------------------------------------------------------------------------------------*/ + if ((NULL != p_key_cert_tlvs) && (NULL != p_code_cert_tlvs)) + { + /* Check request TLV in key cert */ + if ((NULL != p_key_cert_tlvs[SB_PRV_TLV_KEY_CERT_HASH_IMG_PK_IDX].p_val) && + (NULL != p_key_cert_tlvs[SB_PRV_TLV_KEY_CERT_SIGN_CERT_IDX].p_val)) + { + /* Check select TLV in key cert */ + if (((NULL != p_key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_OEM_ROOT_PK_IDX].p_val) && + (NULL == p_key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_IMG_PK_IDX].p_val)) || + ((NULL == p_key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_OEM_ROOT_PK_IDX].p_val) && + (NULL != p_key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_IMG_PK_IDX].p_val)) ) + { + /* Check requeste TLV in code cert */ + if (NULL != p_code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_KEY_IMG_PK_IDX].p_val) + { + /* Check select TLV in code cert */ + if (((NULL != p_code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_CERT_IDX].p_val) && + (NULL == p_code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_IMG_IDX].p_val)) || + ((NULL == p_code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_CERT_IDX].p_val) && + (NULL != p_code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_IMG_IDX].p_val)) ) + { + if (NULL != p_code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_SIGN_CERT_IDX].p_val) + { + if (NULL != p_code_cert_tlvs[SB_PRV_TLV_CI_CODE_CERT_HASH_IMG_IDX].p_val) + { + /* TLV field OK. Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + else + { + ret = SB_RET_ERR_MANI_TLV_FIELD_ERR; + } + } + else + { + /* TLV field OK. Set ret to the success code */ + ret = SB_RET_SUCCESS; + } + } + else + { + ret = SB_RET_ERR_MANI_TLV_FIELD_ERR; + } + } + else + { + ret = SB_RET_ERR_MANI_TLV_FIELD_ERR; + } + } + else + { + ret = SB_RET_ERR_MANI_TLV_FIELD_ERR; + } + } + else + { + ret = SB_RET_ERR_MANI_TLV_FIELD_ERR; + } +#if (SB_CFG_SB_CERT_CHAIN_USE_IMG_PK == 0U) + if((SB_RET_SUCCESS == ret) && + (NULL != p_key_cert_tlvs[SB_PRV_TLV_KEY_CERT_KEY_IMG_PK_IDX].p_val)) + { + ret = SB_RET_ERR_UNSUPPORTED_FUNCTION; + } + else + { + /* Do nothing */ + } +#endif /* (SB_CFG_SB_CERT_CHAIN_USE_IMG_PK == 0U) */ + } + else + { + /* Since this function is only called from within the library, this route is not usually taken */ + } + + return ret; +} +#endif /* (SB_CFG_CHECK_INTEGRITY == 1U) */ +/********************************************************************************************************************** +* End of function sb_check_check_integrity_tlv() +**********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name : sb_get_cc_tlv +**********************************************************************************************************************/ +/*!****************************************************************************************************************//** + * \ingroup SBLIBSecureBootAPIsInternal + * \brief Search key certificate and code certificate TLVs and confirm the obtained TLVs + * \param [in] p_key_cert_st Start address of Key Certificate Structure + * \param [in] p_code_cert_st Start address of Code Certificate Structure + * \param [in] p_search_tlv_key_cert Start address of Key certificate TLVs search information + * \param [in] search_tlv_key_cert_num Number of Key certificates TLV to search + * \param [in] p_search_tlv_code_cert Start address of Code certificate TLVs search information + * \param [in] search_tlv_code_cert_num Number of Code certificates TLV to search + * \param [out] p_key_cert_tlvs Output address of Key certificate TLVs + * \param [out] p_code_cert_tlvs Output address of Code certificate TLVs + * \return + * - #SB_RET_SUCCESS: Successful completion + * - #SB_RET_ERR_INTERNAL_FAIL: Internal processing failed + * - #SB_RET_ERR_MANI_TLV_FIELD_ERR: Missing required TLV fields + * - #SB_RET_ERR_MANI_TLV_INVALID_LEN: The length of the TLV field has a size that exceeds the end of + * the manifest. + * \par Global Variables + * - None + * \par Call SB-Driver API + * - None + * \par Precondition + * - None + * \par Security components + * - yes + * \par Detailed description + * - Parse the Key certificate TLV based on the search conditions passed in the arguments + * - Parse the Code certificate TLV based on the search conditions passed in the arguments + * - Check if the parsed TLV information is correct + * + * Pseudo-code for the function can be found below. + * -# Initialize the variable ret with #SB_RET_ERR_INTERNAL_FAIL + * -# If (NULL != p_key_cert_st) && (NULL != p_code_cert_st) && (NULL != p_search_tlv_key_cert) && + * (NULL != p_search_tlv_code_cert) && (NULL != p_key_cert_tlvs) && (NULL != p_code_cert_tlvs) + * -# Parse the key certificate TLV with #r_sb_mani_parse_tlvs + * -# Set function result to ret + * -# If #SB_RET_SUCCESS == ret + * -# To clear ret, set #SB_RET_ERR_INTERNAL_FAIL to ret. + * -# Parse the code certificate TLV with #r_sb_mani_parse_tlvs + * -# Set function result to ret + * -# Else + * -# Do nothing + * -# Else + * -# Do nothing + * -# Return ret + * + * \callgraph + *********************************************************************************************************************/ +#if (SB_CFG_SB_CERT_CHAIN_VERIFICATION == 1U) || (SB_CFG_CHECK_INTEGRITY == 1U) +static sb_ret_t sb_get_cc_tlv(const st_sb_key_cert_t* const p_key_cert_st, + const st_sb_code_cert_t* const p_code_cert_st, + const st_sb_search_tlv_type_t* const p_search_tlv_key_cert, + const uint32_t search_tlv_key_cert_num, + const st_sb_search_tlv_type_t* const p_search_tlv_code_cert, + const uint32_t search_tlv_code_cert_num, + st_sb_tlv_t* const p_key_cert_tlvs, + st_sb_tlv_t* const p_code_cert_tlvs) +{ + /*----------------------------------------------------------------------------------------------------------------- + Local variables + -----------------------------------------------------------------------------------------------------------------*/ + sb_ret_t ret = SB_RET_ERR_INTERNAL_FAIL; + + /*----------------------------------------------------------------------------------------------------------------- + Function body + -----------------------------------------------------------------------------------------------------------------*/ + /* Check NULL argument */ + if ((NULL != p_key_cert_st) && (NULL != p_code_cert_st) && (NULL != p_search_tlv_key_cert) && + (NULL != p_search_tlv_code_cert) && (NULL != p_key_cert_tlvs) && (NULL != p_code_cert_tlvs)) + { + /* Get Key cert TLVs */ + ret = r_sb_mani_parse_tlvs(p_key_cert_st->p_tlv_top, p_key_cert_st->tlv_len, search_tlv_key_cert_num, + p_search_tlv_key_cert, p_key_cert_tlvs); + if (SB_RET_SUCCESS == ret) + { + /* Clear ret */ + ret = SB_RET_ERR_INTERNAL_FAIL; + (void) ret; + + ret = r_sb_mani_parse_tlvs(p_code_cert_st->p_tlv_top, p_code_cert_st->tlv_len, search_tlv_code_cert_num, + p_search_tlv_code_cert, p_code_cert_tlvs); + } + else + { + /* Do nothing */ + } + } + else + { + /* Since this function is only called from within the library, this route is not usually taken */ + } + + return ret; +} +#endif /* (SB_CFG_SB_CERT_CHAIN_VERIFICATION == 1U) || (SB_CFG_CHECK_INTEGRITY == 1U) */ +/********************************************************************************************************************** +* End of function sb_get_cc_tlv() +**********************************************************************************************************************/ + +/*===================================================================================================================== + End of file +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_sb.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_sb.h new file mode 100644 index 0000000000..6822b5392a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/lib/sb_lib/src/r_sb_sb.h @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*!******************************************************************************************************************** +* \file : r_sb_sb.h +* \par version : 1.00 +* \par Product Name : Renesas-SB-Lib FSBL Custom +* \par Device(s) : Does not depend on specific hardware +* \par Description : This file defines the macros, types and declarations in used the SecureBoot module. +**********************************************************************************************************************/ +#ifndef R_SB_SB_H +/* Multiple inclusion protection macro */ +#define R_SB_SB_H + +/*===================================================================================================================== + Public macro definitions +=====================================================================================================================*/ +/*!******************************************************************** + * \addtogroup SBLIBSecureBootDefinesInternal + * \{******************************************************************/ + +/*! \}*/ + +/*===================================================================================================================== + Public type definitions +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global variables +=====================================================================================================================*/ + +/*===================================================================================================================== + Public global functions +=====================================================================================================================*/ +extern sb_ret_t r_sb_sb_check_integrity (const st_sb_key_cert_t * const p_key_cert_st, + const st_sb_code_cert_t * const p_code_cert_st, + const e_sb_mac_type_t mac_type, uint32_t * const p_tag); +#endif /* R_SB_SB_H */ +/*===================================================================================================================== + End of File +=====================================================================================================================*/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_hal.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_hal.c new file mode 100644 index 0000000000..517d1b9fb4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_hal.c @@ -0,0 +1,136 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_private.h" +#include "r_rsip_primitive.h" +#include "r_rsip_util.h" +#include "r_rsip_reg.h" +#include "r_rsip_wrapper.h" +#include "r_rsip_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_open (void) +{ + uint32_t LC[1] = {0}; + rsip_ret_t rsip_ret = RSIP_RET_FAIL; + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Casting structure pointer is used for address. */ + R_BSP_MODULE_START(FSP_IP_SCE, 0U); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + + r_rsip_p00(); + + rsip_ret = r_rsip_p81(); + + if (RSIP_RET_PASS == rsip_ret) + { + WR1_PROG(REG_1424H, RSIP_PRV_CMD_REG_1424H); + WR1_PROG(REG_1428H, RSIP_PRV_CMD_REG_1428H); + rsip_ret = r_rsip_p82(); + if (RSIP_RET_RETRY == rsip_ret) + { + rsip_ret = r_rsip_p82(); + if (RSIP_RET_RETRY == rsip_ret) + { + rsip_ret = r_rsip_p82(); + } + } + } + + if (RSIP_RET_PASS == rsip_ret) + { + LC[0] = (R_PSCU->DLMMON); + rsip_ret = r_rsip_p40(LC); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_close (void) +{ + r_rsip_p00(); + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Casting structure pointer is used for address. */ + R_BSP_MODULE_STOP(FSP_IP_SCE, 0U); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + + return RSIP_RET_PASS; +} + +void r_rsip_kuk_set (const void * p_key_update_key) +{ + S_INST2 = (uint32_t *) p_key_update_key; +} + +fsp_err_t get_rfc3394_key_wrap_param (rsip_key_type_t key_type, + uint32_t * wrapped_key_type, + uint32_t * key_index_size, + uint32_t * wrapped_key_size) +{ + fsp_err_t err = FSP_ERR_INVALID_ARGUMENT; + + switch (key_type) + { + case RSIP_KEY_TYPE_AES_128: + { + wrapped_key_type[0] = BSWAP_32BIG_C(0U); + *key_index_size = r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_AES_128)); + *wrapped_key_size = r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_PLAIN_KEY(RSIP_KEY_TYPE_AES_128) + 8); + err = FSP_SUCCESS; + break; + } + + case RSIP_KEY_TYPE_AES_256: + { + wrapped_key_type[0] = BSWAP_32BIG_C(2U); + *key_index_size = r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_WRAPPED_KEY(RSIP_KEY_TYPE_AES_256)); + *wrapped_key_size = r_rsip_byte_to_word_convert(RSIP_BYTE_SIZE_PLAIN_KEY(RSIP_KEY_TYPE_AES_256) + 8); + err = FSP_SUCCESS; + break; + } + + default: + { + /* Do nothing */ + } + } + + return err; +} + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.c new file mode 100644 index 0000000000..5393c50a2a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.c @@ -0,0 +1,2100 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_private.h" +#include "r_rsip_primitive.h" +#include "r_rsip_wrapper.h" +#include "r_rsip_reg.h" +#include "r_rsip_addr.h" +#include "r_rsip_util.h" +#include "r_rsip_public.h" +#include "r_rsip_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* For AES-CCM/GCMC */ +#define RSIP_PRV_KEY_TYPE_AES_CCM_GCM_GENERAL_KEY (0U) +#define RSIP_PRV_KEY_TYPE_AES_CCM_GCM_TLS_KEY (1U) +#define RSIP_PRV_KEY_TYPE_AES_CCM_GCM_DLMS_COSEM_KEY (2U) +#define RSIP_PRV_KEY_TYPE_AES_CCM_GCM_IAR_KEY (3U) +#define RSIP_PRV_KEY_TYPE_AES_CCM_GCM_TLS_1_3_KEY (4U) + +/* For AES-CMAC. These commands do not require byte swapping */ +#define RSIP_PRV_CMD_AES_CMAC_GENERATE_WITHOUT_REMAINDER (0U) +#define RSIP_PRV_CMD_AES_CMAC_GENERATE_WITH_REMAINDER (1U) +#define RSIP_PRV_CMD_AES_CMAC_VERIFY_WITHOUT_REMAINDER (2U) +#define RSIP_PRV_CMD_AES_CMAC_VERIFY_WITH_REMAINDER (3U) + +/* For RSA */ + +/* + * Maximum retry count of RSA key generation derived from FIPS186-4 B.3.3. 4.7 and 5.8 (1024, 2048, 3072) + * Maximum retry count of RSA key generation derived from FIPS186-5 A.1.3. 4.7 and 5.8 (4096) + */ +#define RSIP_PRV_MAX_RETRY_COUNT_KEY_GEN_RSA_2048 (2 * (5 * 2048 / 2)) +#define RSIP_PRV_MAX_RETRY_COUNT_KEY_GEN_RSA_3072 (2 * (5 * 3072 / 2)) +#define RSIP_PRV_MAX_RETRY_COUNT_KEY_GEN_RSA_4096 (5 * 4096 + 10 * 4096) + +/* For RFC3394 Key Wrap */ +#define RSIP_PRV_WORD_SIZE_RFC3394_WRAPPED_KEY_AES_128 (6U) +#define RSIP_PRV_WORD_SIZE_RFC3394_WRAPPED_KEY_AES_256 (10U) + +/* For ECC */ +#define RSIP_PRV_WORD_SIZE_ECC_521_SIGNATURE (40U) +#define RSIP_PRV_WORD_SIZE_ECC_521_PUBLIC_KEY (40U) +#define RSIP_PRV_BYTE_SIZE_ECC_521_PADDING (14U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +typedef enum e_cmd +{ + CMD_AES_KEY_WRAP_AES128 = 0, + CMD_AES_KEY_WRAP_AES256 = 1, + + CMD_AES_MODE_ECB_ENCRYPT = 0, + CMD_AES_MODE_ECB_DECRYPT = 1, + CMD_AES_MODE_CBC_ENCRYPT = 2, + CMD_AES_MODE_CBC_DECRYPT = 3, + CMD_AES_MODE_CTR_CRYPT = 4, + + CMD_AES_IV_TYPE_PLAIN = 0, + CMD_AES_IV_TYPE_WRAPPED = 1, + + CMD_AES_CMAC_GENERATE_WITHOUT_REMAINDER = 0, + CMD_AES_CMAC_GENERATE_WITH_REMAINDER = 1, + CMD_AES_CMAC_VERIFY_WITHOUT_REMAINDER = 2, + CMD_AES_CMAC_VERIFY_WITH_REMAINDER = 3, + + CMD_CHACHA20_POLY1305_MODE_ENCRYPT = 0, + CMD_CHACHA20_POLY1305_MODE_DECRYPT = 1, + + CMD_ECC_TYPE_NIST = 0, + CMD_ECC_TYPE_BRAINPOOL = 1, + CMD_ECC_TYPE_KOBLITZ = 2, + + CMD_ECC_KEY_LENGTH_256 = 0, + + CMD_ECDH_PUBKEY_TYPE_PLAIN = 0, + CMD_ECDH_PUBKEY_TYPE_WRAPPED = 1, + + CMD_HMAC_HASH_TYPE_SHA1 = 0, + CMD_HMAC_HASH_TYPE_SHA224 = 1, + CMD_HMAC_HASH_TYPE_SHA256 = 2, + + CMD_PKI_KEY_TYPE_RSA_2048 = 0, + CMD_PKI_KEY_TYPE_ECC_SECP256R1 = 3, + CMD_PKI_KEY_TYPE_ECC_SECP384R1 = 4, + CMD_PKI_KEY_TYPE_ECC_SECP521R1 = 5, + CMD_PKI_KEY_TYPE_ECC_BRAINPOOLP256R1 = 6, + CMD_PKI_KEY_TYPE_ECC_BRAINPOOLP384R1 = 7, + CMD_PKI_KEY_TYPE_ECC_BRAINPOOLP512R1 = 8, + + CMD_KDF_HASH_TYPE_SHA256 = 0, + CMD_KDF_HASH_TYPE_SHA384 = 1, + CMD_KDF_HASH_TYPE_SHA512 = 2, + + CMD_KDF_OUTDATA_TYPE_AES128 = 0, + CMD_KDF_OUTDATA_TYPE_AES256 = 1, + CMD_KDF_OUTDATA_TYPE_IV_AES = 2, + CMD_KDF_OUTDATA_TYPE_IV_TLS12 = 3, + CMD_KDF_OUTDATA_TYPE_HMAC_SHA1 = 5, + CMD_KDF_OUTDATA_TYPE_HMAC_SHA256 = 6, + CMD_KDF_OUTDATA_TYPE_HMAC_SHA384 = 7, + CMD_KDF_OUTDATA_TYPE_HMAC_SHA512 = 8, + + CMD_KDF_TLS12_PRF_VERIFY_DATA_CLIENT = 0, + CMD_KDF_TLS12_PRF_VERIFY_DATA_SERVER = 1, + + CMD_OTF_CHANNEL_0 = 0, + CMD_OTF_CHANNEL_1 = 1, + + CMD_AUTH_HASH_TYPE_JTAG_DEBUG_LEVEL1 = 0, + CMD_AUTH_HASH_TYPE_JTAG_DEBUG_LEVEL2 = 1, +} cmd_t; + +typedef enum e_rsip_oem_cmd +{ + RSIP_OEM_CMD_INVALID = 0, + RSIP_OEM_CMD_AES128 = 5, + RSIP_OEM_CMD_AES192, + RSIP_OEM_CMD_AES256, + RSIP_OEM_CMD_AES128_XTS, + RSIP_OEM_CMD_AES256_XTS, + RSIP_OEM_CMD_RSA1024_PUBLIC, + RSIP_OEM_CMD_RSA1024_PRIVATE, + RSIP_OEM_CMD_RSA2048_PUBLIC, + RSIP_OEM_CMD_RSA2048_PRIVATE, + RSIP_OEM_CMD_RSA3072_PUBLIC, + RSIP_OEM_CMD_RSA3072_PRIVATE, + RSIP_OEM_CMD_RSA4096_PUBLIC, + RSIP_OEM_CMD_RSA4096_PRIVATE, + RSIP_OEM_CMD_ECC_P192_PUBLIC, + RSIP_OEM_CMD_ECC_P192_PRIVATE, + RSIP_OEM_CMD_ECC_P224_PUBLIC, + RSIP_OEM_CMD_ECC_P224_PRIVATE, + RSIP_OEM_CMD_ECC_SECP256R1_PUBLIC, + RSIP_OEM_CMD_ECC_SECP256R1_PRIVATE, + RSIP_OEM_CMD_ECC_SECP384R1_PUBLIC, + RSIP_OEM_CMD_ECC_SECP384R1_PRIVATE, + RSIP_OEM_CMD_HMAC_SHA224, + RSIP_OEM_CMD_HMAC_SHA256, + RSIP_OEM_CMD_ECC_BRAINPOOLP256R1_PUBLIC, + RSIP_OEM_CMD_ECC_BRAINPOOLP256R1_PRIVATE, + RSIP_OEM_CMD_ECC_BRAINPOOLP384R1_PUBLIC, + RSIP_OEM_CMD_ECC_BRAINPOOLP384R1_PRIVATE, + RSIP_OEM_CMD_ECC_BRAINPOOLP512R1_PUBLIC, + RSIP_OEM_CMD_ECC_BRAINPOOLP512R1_PRIVATE, + RSIP_OEM_CMD_ECC_SECP256K1_PUBLIC, + RSIP_OEM_CMD_ECC_SECP256K1_PRIVATE, + RSIP_OEM_CMD_ECC_SECP521R1_PUBLIC, + RSIP_OEM_CMD_ECC_SECP521R1_PRIVATE, + RSIP_OEM_CMD_ECC_EDWARDS25519_PUBLIC, + RSIP_OEM_CMD_ECC_EDWARDS25519_PRIVATE, + RSIP_OEM_CMD_HMAC_SHA384, + RSIP_OEM_CMD_HMAC_SHA512, + RSIP_OEM_CMD_HMAC_SHA512_224, + RSIP_OEM_CMD_HMAC_SHA512_256, + RSIP_OEM_CMD_CHACHA20 = 0x30, + RSIP_OEM_CMD_RAS_2048_PUBLIC_FOR_TLS = 0xfe, + RSIP_OEM_CMD_NUM +} rsip_oem_cmd_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +RSIP_PRV_STATIC_INLINE uint64_t r_rsip_byte_to_word_convert_u64(const uint64_t bytes); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static const uint32_t gs_cmd[9] = +{ + BSWAP_32BIG_C(0U), BSWAP_32BIG_C(1U), BSWAP_32BIG_C(2U), BSWAP_32BIG_C(3U), BSWAP_32BIG_C(4U), BSWAP_32BIG_C(5U), + BSWAP_32BIG_C(6U), BSWAP_32BIG_C(7U), BSWAP_32BIG_C(8U) +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +rsip_ret_t r_rsip_wrapper_pf0_secp256r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + const uint32_t InData_Cmd[1] = {bswap_32big(RSIP_ECC_CMD_P256)}; + const uint32_t * InData_DomainParam = DomainParam_NIST_P256; + uint32_t cv_type = bswap_32big(RSIP_ECC_CURVE_TYPE_NIST); + + return r_rsip_pf0(&cv_type, InData_Cmd, InData_KeyIndex, InData_MsgDgst, InData_DomainParam, OutData_Signature); +} + +rsip_ret_t r_rsip_wrapper_pf1_secp256r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + const uint32_t InData_Cmd[1] = {bswap_32big(RSIP_ECC_CMD_P256)}; + const uint32_t * InData_DomainParam = DomainParam_NIST_P256; + uint32_t cv_type = bswap_32big(RSIP_ECC_CURVE_TYPE_NIST); + + return r_rsip_pf1(&cv_type, InData_Cmd, InData_KeyIndex, InData_MsgDgst, InData_Signature, InData_DomainParam); +} + +rsip_ret_t r_rsip_wrapper_pf4_secp256r1 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t InData_CurveType[1] = {RSIP_ECC_CURVE_TYPE_NIST}; + uint32_t InData_Cmd[1] = {RSIP_ECC_CMD_P256}; + uint32_t const * p_domain_param = DomainParam_NIST_P256; + + return r_rsip_pf4(InData_CurveType, InData_Cmd, p_domain_param, OutData_PubKeyIndex, OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pf5_secp384r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + const uint32_t * InData_DomainParam = DomainParam_NIST_P384; + uint32_t cv_type = bswap_32big(RSIP_ECC_CURVE_TYPE_NIST); + + return r_rsip_pf5(&cv_type, InData_KeyIndex, InData_MsgDgst, InData_DomainParam, OutData_Signature); +} + +rsip_ret_t r_rsip_wrapper_pf6_secp384r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + const uint32_t * InData_DomainParam = DomainParam_NIST_P384; + uint32_t cv_type = bswap_32big(RSIP_ECC_CURVE_TYPE_NIST); + + return r_rsip_pf6(&cv_type, InData_KeyIndex, InData_MsgDgst, InData_Signature, InData_DomainParam); +} + +rsip_ret_t r_rsip_wrapper_pf9_secp384r1 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t InData_CurveType[1] = {RSIP_ECC_CURVE_TYPE_NIST}; + uint32_t const * p_domain_param = DomainParam_NIST_P384; + + return r_rsip_pf9(InData_CurveType, p_domain_param, OutData_PubKeyIndex, OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p11_secp521r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + rsip_ret_t rsip_ret; + const uint32_t * InData_DomainParam = DomainParam_NIST_P521; + uint32_t Signature[RSIP_PRV_WORD_SIZE_ECC_521_SIGNATURE] = {0}; + const uint32_t signature_r_pad_byte = RSIP_PRV_BYTE_SIZE_ECC_521_PADDING; + const uint32_t signature_s_pad_byte = RSIP_PRV_BYTE_SIZE_ECC_521_PADDING + + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM + + RSIP_PRV_BYTE_SIZE_ECC_521_PADDING; + + rsip_ret = r_rsip_p11(InData_KeyIndex, InData_MsgDgst, InData_DomainParam, Signature); + if (RSIP_RET_PASS == rsip_ret) + { + memcpy((uint8_t *) OutData_Signature, + (uint8_t *) Signature + signature_r_pad_byte, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + memcpy((uint8_t *) OutData_Signature + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM, + (uint8_t *) Signature + signature_s_pad_byte, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + } + + return rsip_ret; +} + +rsip_ret_t r_rsip_wrapper_p12_secp521r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + const uint32_t * InData_DomainParam = DomainParam_NIST_P521; + uint32_t Signature[RSIP_PRV_WORD_SIZE_ECC_521_SIGNATURE] = {0}; + const uint32_t signature_r_pad_byte = RSIP_PRV_BYTE_SIZE_ECC_521_PADDING; + const uint32_t signature_s_pad_byte = RSIP_PRV_BYTE_SIZE_ECC_521_PADDING + + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM + + RSIP_PRV_BYTE_SIZE_ECC_521_PADDING; + + memcpy((uint8_t *) Signature + signature_r_pad_byte, (uint8_t *) InData_Signature, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + memcpy((uint8_t *) Signature + signature_s_pad_byte, + (uint8_t *) InData_Signature + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + + return r_rsip_p12(InData_KeyIndex, InData_MsgDgst, Signature, InData_DomainParam); +} + +rsip_ret_t r_rsip_wrapper_p13_secp521r1 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t const * p_domain_param = DomainParam_NIST_P521; + + return r_rsip_p13(p_domain_param, OutData_PubKeyIndex, OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pf0_secp256k1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + return r_rsip_pf0(&gs_cmd[CMD_ECC_TYPE_KOBLITZ], + &gs_cmd[CMD_ECC_KEY_LENGTH_256], + InData_KeyIndex, + InData_MsgDgst, + DomainParam_Koblitz_secp256k1, + OutData_Signature); +} + +rsip_ret_t r_rsip_wrapper_pf1_secp256k1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_pf1(&gs_cmd[CMD_ECC_TYPE_KOBLITZ], + &gs_cmd[CMD_ECC_KEY_LENGTH_256], + InData_KeyIndex, + InData_MsgDgst, + InData_Signature, + DomainParam_Koblitz_secp256k1); +} + +rsip_ret_t r_rsip_wrapper_pf4_secp256k1 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + return r_rsip_pf4(&gs_cmd[CMD_ECC_TYPE_KOBLITZ], + &gs_cmd[CMD_ECC_KEY_LENGTH_256], + DomainParam_Koblitz_secp256k1, + OutData_PubKeyIndex, + OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pf0_brainpoolp256r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + return r_rsip_pf0(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + &gs_cmd[CMD_ECC_KEY_LENGTH_256], + InData_KeyIndex, + InData_MsgDgst, + DomainParam_Brainpool_256r1, + OutData_Signature); +} + +rsip_ret_t r_rsip_wrapper_pf1_brainpoolp256r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_pf1(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + &gs_cmd[CMD_ECC_KEY_LENGTH_256], + InData_KeyIndex, + InData_MsgDgst, + InData_Signature, + DomainParam_Brainpool_256r1); +} + +rsip_ret_t r_rsip_wrapper_pf4_brainpoolp256r1 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + return r_rsip_pf4(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + &gs_cmd[CMD_ECC_KEY_LENGTH_256], + DomainParam_Brainpool_256r1, + OutData_PubKeyIndex, + OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pf5_brainpoolp384r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + return r_rsip_pf5(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + InData_KeyIndex, + InData_MsgDgst, + DomainParam_Brainpool_384r1, + OutData_Signature); +} + +rsip_ret_t r_rsip_wrapper_pf6_brainpoolp384r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_pf6(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + InData_KeyIndex, + InData_MsgDgst, + InData_Signature, + DomainParam_Brainpool_384r1); +} + +rsip_ret_t r_rsip_wrapper_pf9_brainpoolp384r1 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + return r_rsip_pf9(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + DomainParam_Brainpool_384r1, + OutData_PubKeyIndex, + OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p7d_brainpoolp512r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + return r_rsip_p7d(InData_KeyIndex, InData_MsgDgst, DomainParam_Brainpool_512r1, OutData_Signature); +} + +rsip_ret_t r_rsip_wrapper_p7e_brainpoolp512r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_p7e(InData_KeyIndex, InData_MsgDgst, InData_Signature, DomainParam_Brainpool_512r1); +} + +rsip_ret_t r_rsip_wrapper_p7f_brainpoolp512r1 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + return r_rsip_p7f(DomainParam_Brainpool_512r1, OutData_PubKeyIndex, OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p18_edwards25519 (const uint32_t InData_PrivKeyIndex[], + const uint32_t InData_PubKeyIndex[], + const uint32_t InData_Msg[], + const uint64_t InData_MsgLen, + uint32_t OutData_Signature[]) +{ + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(InData_MsgLen), + r_rsip_byte_to_bit_convert_lower(InData_MsgLen) + }; + + msg_len[0] = bswap_32big(msg_len[0]); + msg_len[1] = bswap_32big(msg_len[1]); + + uint64_t max_cnt = r_rsip_byte_to_word_convert_u64(InData_MsgLen); + + return r_rsip_p18(InData_PrivKeyIndex, + InData_PubKeyIndex, + InData_Msg, + msg_len, + DomainParam_Ed25519, + OutData_Signature, + max_cnt); +} + +rsip_ret_t r_rsip_wrapper_p19_edwards25519 (const uint32_t InData_KeyIndex[], + const uint32_t InData_Msg[], + const uint64_t InData_MsgLen, + const uint32_t InData_Signature[]) +{ + uint32_t msg_len[2] = + { + r_rsip_byte_to_bit_convert_upper(InData_MsgLen), + r_rsip_byte_to_bit_convert_lower(InData_MsgLen) + }; + + msg_len[0] = bswap_32big(msg_len[0]); + msg_len[1] = bswap_32big(msg_len[1]); + + uint64_t max_cnt = r_rsip_byte_to_word_convert_u64(InData_MsgLen); + + return r_rsip_p19(InData_KeyIndex, InData_Msg, msg_len, InData_Signature, DomainParam_Ed25519, max_cnt); +} + +rsip_ret_t r_rsip_wrapper_p1a_edwards25519 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + return r_rsip_p1a(DomainParam_Ed25519, OutData_PubKeyIndex, OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p2b_rsa2048 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + return r_rsip_p2b(RSIP_PRV_MAX_RETRY_COUNT_KEY_GEN_RSA_2048, OutData_PubKeyIndex, OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p3a_rsa3072 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + return r_rsip_p3a(RSIP_PRV_MAX_RETRY_COUNT_KEY_GEN_RSA_3072, OutData_PubKeyIndex, OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p3b_rsa4096 (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + return r_rsip_p3b(RSIP_PRV_MAX_RETRY_COUNT_KEY_GEN_RSA_4096, OutData_PubKeyIndex, OutData_PrivKeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_aes128 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_AES128)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_AES128_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_aes192 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_AES192)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_AES192_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_aes256 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_AES256)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_AES256_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_aes128xts (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_AES128_XTS)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_aes256xts (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_AES256_XTS)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_chacha20 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_CHACHA20)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_CHACHA20_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_secp256r1_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_SECP256R1_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_SECP256R1_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_secp256r1_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_SECP256R1_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_SECP256R1_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_secp384r1_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_SECP384R1_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_SECP384R1_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_secp384r1_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_SECP384R1_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_SECP384R1_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_secp521r1_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_SECP521R1_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_SECP521R1_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_secp521r1_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_SECP521R1_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_SECP521R1_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_secp256k1_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_SECP256K1_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_SECP256K1_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_secp256k1_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_SECP256K1_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_SECP256K1_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp256r1_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_BRAINPOOLP256R1_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP256R1_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp256r1_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_BRAINPOOLP256R1_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP256R1_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp384r1_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_BRAINPOOLP384R1_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP384R1_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp384r1_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_BRAINPOOLP384R1_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP384R1_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp512r1_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_BRAINPOOLP512R1_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP512R1_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp512r1_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_BRAINPOOLP512R1_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP512R1_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_edwards25519_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_EDWARDS25519_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_EDWARDS25519_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_edwards25519_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_ECC_EDWARDS25519_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_ECC_EDWARDS25519_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_rsa2048_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_RSA2048_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_RSA2048_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_rsa2048_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_RSA2048_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_rsa3072_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_RSA3072_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_RSA3072_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_rsa3072_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_RSA3072_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_rsa4096_pub (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_RSA4096_PUBLIC)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_RSA4096_PUBLIC_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_rsa4096_priv (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_RSA4096_PRIVATE)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_hmacsha224 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_HMAC_SHA224)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_HMAC_SHA224_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_hmacsha256 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_HMAC_SHA256)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_HMAC_SHA256_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_hmacsha384 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_HMAC_SHA384)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_HMAC_SHA384_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p6f_hmacsha512 (const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t CMD[1] = {bswap_32big(RSIP_OEM_CMD_HMAC_SHA512)}; + uint32_t LC[1] = {0}; + LC[0] = R_PSCU->DLMMON; + INST_DATA_SIZE = RSIP_OEM_KEY_SIZE_HMAC_SHA512_KEY_INST_DATA_WORD; + + return r_rsip_p6f(LC, CMD, InData_IV, InData_InstData, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_p8f_aes128 (const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_WrappedKeyIndex[], + uint32_t OutData_Text[], + uint32_t KEY_INDEX_SIZE, + uint32_t WRAPPED_KEY_SIZE) +{ + return r_rsip_p8f(&gs_cmd[CMD_AES_KEY_WRAP_AES128], + InData_KeyIndex, + InData_WrappedKeyType, + InData_WrappedKeyIndex, + OutData_Text, + KEY_INDEX_SIZE, + WRAPPED_KEY_SIZE); +} + +rsip_ret_t r_rsip_wrapper_p8f_aes256 (const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_WrappedKeyIndex[], + uint32_t OutData_Text[], + uint32_t KEY_INDEX_SIZE, + uint32_t WRAPPED_KEY_SIZE) +{ + return r_rsip_p8f(&gs_cmd[CMD_AES_KEY_WRAP_AES256], + InData_KeyIndex, + InData_WrappedKeyType, + InData_WrappedKeyIndex, + OutData_Text, + KEY_INDEX_SIZE, + WRAPPED_KEY_SIZE); +} + +rsip_ret_t r_rsip_wrapper_p90_aes128 (const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_Text[], + uint32_t OutData_KeyIndex[], + uint32_t WRAPPED_KEY_SIZE, + uint32_t KEY_INDEX_SIZE) +{ + return r_rsip_p90(&gs_cmd[0], + &gs_cmd[CMD_AES_KEY_WRAP_AES128], + InData_KeyIndex, + InData_WrappedKeyType, + InData_Text, + OutData_KeyIndex, + WRAPPED_KEY_SIZE, + KEY_INDEX_SIZE); +} + +rsip_ret_t r_rsip_wrapper_p90_aes256 (const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_Text[], + uint32_t OutData_KeyIndex[], + uint32_t WRAPPED_KEY_SIZE, + uint32_t KEY_INDEX_SIZE) +{ + return r_rsip_p90(&gs_cmd[0], + &gs_cmd[CMD_AES_KEY_WRAP_AES256], + InData_KeyIndex, + InData_WrappedKeyType, + InData_Text, + OutData_KeyIndex, + WRAPPED_KEY_SIZE, + KEY_INDEX_SIZE); +} + +rsip_ret_t r_rsip_wrapper_p47i_ecb_enc (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p47i(&gs_cmd[CMD_AES_MODE_ECB_ENCRYPT], InData_KeyIndex, NULL, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p47i_ecb_dec (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p47i(&gs_cmd[CMD_AES_MODE_ECB_DECRYPT], InData_KeyIndex, NULL, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p47i_cbc_enc (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p47i(&gs_cmd[CMD_AES_MODE_CBC_ENCRYPT], InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_PLAIN], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p47i_cbc_dec (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p47i(&gs_cmd[CMD_AES_MODE_CBC_DECRYPT], InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_PLAIN], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p47i_cbc_enc_wrapped_iv (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p47i(&gs_cmd[CMD_AES_MODE_CBC_ENCRYPT], InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_WRAPPED], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p47i_cbc_dec_wrapped_iv (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p47i(&gs_cmd[CMD_AES_MODE_CBC_DECRYPT], InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_WRAPPED], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p47i_ctr (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p47i(&gs_cmd[CMD_AES_MODE_CTR_CRYPT], InData_KeyIndex, NULL, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p50i_ecb_enc (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p50i(&gs_cmd[CMD_AES_MODE_ECB_ENCRYPT], InData_KeyIndex, NULL, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p50i_ecb_dec (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p50i(&gs_cmd[CMD_AES_MODE_ECB_DECRYPT], InData_KeyIndex, NULL, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p50i_cbc_enc (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p50i(&gs_cmd[CMD_AES_MODE_CBC_ENCRYPT], InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_PLAIN], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p50i_cbc_dec (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p50i(&gs_cmd[CMD_AES_MODE_CBC_DECRYPT], InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_PLAIN], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p50i_cbc_enc_wrapped_iv (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p50i(&gs_cmd[CMD_AES_MODE_CBC_ENCRYPT], InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_WRAPPED], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p50i_cbc_dec_wrapped_iv (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p50i(&gs_cmd[CMD_AES_MODE_CBC_DECRYPT], InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_WRAPPED], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p50i_ctr (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p50i(&gs_cmd[CMD_AES_MODE_CTR_CRYPT], InData_KeyIndex, NULL, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p29i_plain_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p29i(InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_PLAIN], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p29i_wrapped_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p29i(InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_WRAPPED], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p32i_plain_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p32i(InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_PLAIN], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p32i_wrapped_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p32i(InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_WRAPPED], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p34i_plain_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p34i(InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_PLAIN], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p34i_wrapped_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p34i(InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_WRAPPED], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p36i_plain_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p36i(InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_PLAIN], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p36i_wrapped_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p36i(InData_KeyIndex, &gs_cmd[CMD_AES_IV_TYPE_WRAPPED], InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p83i_plain_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p83i(InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p83i_wrapped_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p83i(InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p85i_plain_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p85i(InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p85i_wrapped_iv (const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) +{ + return r_rsip_p85i(InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p89i_ecb_enc (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p89i(&gs_cmd[CMD_AES_MODE_ECB_ENCRYPT], InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p89i_ecb_dec (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p89i(&gs_cmd[CMD_AES_MODE_ECB_DECRYPT], InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p89i_cbc_enc (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p89i(&gs_cmd[CMD_AES_MODE_CBC_ENCRYPT], InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p89i_cbc_dec (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p89i(&gs_cmd[CMD_AES_MODE_CBC_DECRYPT], InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p89i_cbc_enc_wrapped_iv (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p89i(&gs_cmd[CMD_AES_MODE_CBC_ENCRYPT], InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p89i_cbc_dec_wrapped_iv (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p89i(&gs_cmd[CMD_AES_MODE_CBC_DECRYPT], InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p89i_ctr (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + return r_rsip_p89i(&gs_cmd[CMD_AES_MODE_CTR_CRYPT], InData_KeyIndex, InData_IV); +} + +rsip_ret_t r_rsip_wrapper_p95i_aes128ccm_encrypt (const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len) +{ + uint32_t InData_KeyType[1] = {bswap_32big(RSIP_PRV_KEY_TYPE_AES_CCM_GCM_GENERAL_KEY)}; + uint32_t InData_DataType[1] = {0}; + uint32_t InData_Cmd[1] = {0}; + uint32_t InData_SeqNum[2] = {0}; + + return r_rsip_p95i(InData_KeyType, + InData_DataType, + InData_Cmd, + InData_TextLen, + InData_KeyIndex, + InData_IV, + InData_Header, + InData_SeqNum, + Header_Len); +} + +rsip_ret_t r_rsip_wrapper_p95f_aes128ccm_encrypt (const uint32_t * InData_Text, + const uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_MAC) +{ + (void) InData_TextLen; + + return r_rsip_p95f(InData_Text, OutData_Text, OutData_MAC); +} + +rsip_ret_t r_rsip_wrapper_p98i_aes128ccm_decrypt (const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_MACLength, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len) +{ + uint32_t InData_KeyType[1] = {bswap_32big(RSIP_PRV_KEY_TYPE_AES_CCM_GCM_GENERAL_KEY)}; + uint32_t InData_DataType[1] = {0}; + uint32_t InData_Cmd[1] = {0}; + uint32_t InData_SeqNum[2] = {0}; + + return r_rsip_p98i(InData_KeyType, + InData_DataType, + InData_Cmd, + InData_TextLen, + InData_MACLength, + InData_KeyIndex, + InData_IV, + InData_Header, + InData_SeqNum, + Header_Len); +} + +rsip_ret_t r_rsip_wrapper_p98f_aes128ccm_decrypt (const uint32_t * InData_Text, + const uint32_t * InData_TextLen, + const uint32_t * InData_MAC, + const uint32_t * InData_MACLength, + uint32_t * OutData_Text) +{ + (void) InData_TextLen; + (void) InData_MACLength; + + return r_rsip_p98f(InData_Text, InData_MAC, OutData_Text); +} + +rsip_ret_t r_rsip_wrapper_pa7i_aes192ccm_encrypt (const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len) +{ + (void) InData_TextLen; + + return r_rsip_pa7i(InData_KeyIndex, InData_IV, InData_Header, Header_Len); +} + +rsip_ret_t r_rsip_wrapper_pa7f_aes192ccm_encrypt (const uint32_t * InData_Text, + const uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_MAC) +{ + return r_rsip_pa7f(InData_Text, InData_TextLen, OutData_Text, OutData_MAC); +} + +rsip_ret_t r_rsip_wrapper_pb0i_aes192ccm_decrypt (const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_MACLength, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len) +{ + (void) InData_TextLen; + (void) InData_MACLength; + + return r_rsip_pb0i(InData_KeyIndex, InData_IV, InData_Header, Header_Len); +} + +rsip_ret_t r_rsip_wrapper_pb0f_aes192ccm_decrypt (const uint32_t * InData_Text, + const uint32_t * InData_TextLen, + const uint32_t * InData_MAC, + const uint32_t * InData_MACLength, + uint32_t * OutData_Text) +{ + return r_rsip_pb0f(InData_Text, InData_TextLen, InData_MAC, InData_MACLength, OutData_Text); +} + +rsip_ret_t r_rsip_wrapper_pa1i_aes256ccm_encrypt (const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len) +{ + uint32_t InData_KeyType[1] = {bswap_32big(RSIP_PRV_KEY_TYPE_AES_CCM_GCM_GENERAL_KEY)}; + (void) InData_TextLen; + + return r_rsip_pa1i(InData_KeyType, InData_KeyIndex, InData_IV, InData_Header, Header_Len); +} + +rsip_ret_t r_rsip_wrapper_pa4i_aes256ccm_decrypt (const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_MACLength, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len) +{ + uint32_t InData_KeyType[1] = {bswap_32big(RSIP_PRV_KEY_TYPE_AES_CCM_GCM_GENERAL_KEY)}; + (void) InData_TextLen; + (void) InData_MACLength; + + return r_rsip_pa4i(InData_KeyType, InData_KeyIndex, InData_IV, InData_Header, Header_Len); +} + +rsip_ret_t r_rsip_wrapper_p41f_aes128mac_generate (const uint32_t * InData_Text, + uint32_t * OutData_DataT, + const uint32_t all_msg_len) +{ + uint32_t InData_Cmd[1] = + { + ((0 == (all_msg_len % 16)) && + (0 != + all_msg_len)) ? RSIP_PRV_CMD_AES_CMAC_GENERATE_WITHOUT_REMAINDER : + RSIP_PRV_CMD_AES_CMAC_GENERATE_WITH_REMAINDER + }; + uint32_t InData_DataT = 0; + + return r_rsip_p41f(InData_Cmd, InData_Text, &InData_DataT, (uint32_t *) &all_msg_len, OutData_DataT); +} + +rsip_ret_t r_rsip_wrapper_p41f_aes128mac_verify (const uint32_t * InData_Text, + const uint32_t * InData_DataT, + const uint32_t * InData_DataTLen, + const uint32_t all_msg_len) +{ + uint32_t InData_Cmd[1] = + { + ((0 == (all_msg_len % 16)) && + (0 != + all_msg_len)) ? RSIP_PRV_CMD_AES_CMAC_VERIFY_WITHOUT_REMAINDER : + RSIP_PRV_CMD_AES_CMAC_VERIFY_WITH_REMAINDER + }; + uint32_t OutData_DataT[4] = {0}; + (void) all_msg_len; + + return r_rsip_p41f(InData_Cmd, InData_Text, InData_DataT, InData_DataTLen, OutData_DataT); +} + +rsip_ret_t r_rsip_wrapper_p87f_aes192mac_generate (const uint32_t * InData_Text, + uint32_t * OutData_DataT, + const uint32_t all_msg_len) +{ + uint32_t InData_Cmd[1] = + { + ((0 == (all_msg_len % 16)) && + (0 != + all_msg_len)) ? RSIP_PRV_CMD_AES_CMAC_GENERATE_WITHOUT_REMAINDER : + RSIP_PRV_CMD_AES_CMAC_GENERATE_WITH_REMAINDER + }; + uint32_t InData_DataT = 0; + + return r_rsip_p87f(InData_Cmd, InData_Text, &InData_DataT, (uint32_t *) &all_msg_len, OutData_DataT); +} + +rsip_ret_t r_rsip_wrapper_p87f_aes192mac_verify (const uint32_t * InData_Text, + const uint32_t * InData_DataT, + const uint32_t * InData_DataTLen, + const uint32_t all_msg_len) +{ + uint32_t InData_Cmd[1] = + { + ((0 == (all_msg_len % 16)) && + (0 != + all_msg_len)) ? RSIP_PRV_CMD_AES_CMAC_VERIFY_WITHOUT_REMAINDER : + RSIP_PRV_CMD_AES_CMAC_VERIFY_WITH_REMAINDER + }; + uint32_t OutData_DataT[4] = {0}; + (void) all_msg_len; + + return r_rsip_p87f(InData_Cmd, InData_Text, InData_DataT, InData_DataTLen, OutData_DataT); +} + +rsip_ret_t r_rsip_wrapper_p44f_aes256mac_generate (const uint32_t * InData_Text, + uint32_t * OutData_DataT, + const uint32_t all_msg_len) +{ + uint32_t InData_Cmd[1] = + { + ((0 == (all_msg_len % 16)) && + (0 != + all_msg_len)) ? RSIP_PRV_CMD_AES_CMAC_GENERATE_WITHOUT_REMAINDER : + RSIP_PRV_CMD_AES_CMAC_GENERATE_WITH_REMAINDER + }; + uint32_t InData_DataT = 0; + + return r_rsip_p44f(InData_Cmd, InData_Text, &InData_DataT, (uint32_t *) &all_msg_len, OutData_DataT); +} + +rsip_ret_t r_rsip_wrapper_p44f_aes256mac_verify (const uint32_t * InData_Text, + const uint32_t * InData_DataT, + const uint32_t * InData_DataTLen, + const uint32_t all_msg_len) +{ + uint32_t InData_Cmd[1] = + { + ((0 == (all_msg_len % 16)) && + (0 != + all_msg_len)) ? RSIP_PRV_CMD_AES_CMAC_VERIFY_WITHOUT_REMAINDER : + RSIP_PRV_CMD_AES_CMAC_VERIFY_WITH_REMAINDER + }; + uint32_t OutData_DataT[4] = {0}; + (void) all_msg_len; + + return r_rsip_p44f(InData_Cmd, InData_Text, InData_DataT, InData_DataTLen, OutData_DataT); +} + +#if BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED +rsip_ret_t r_rsip_wrapper_p97i_enc (const uint32_t * InData_KeyIndex, + const uint32_t * InData_Nonce, + const uint32_t * InData_TextLen, + const uint32_t * InData_DataALen) +{ + return r_rsip_p97i(InData_KeyIndex, + &gs_cmd[CMD_CHACHA20_POLY1305_MODE_ENCRYPT], + InData_Nonce, + InData_TextLen, + InData_DataALen); +} + +rsip_ret_t r_rsip_wrapper_p97i_dec (const uint32_t * InData_KeyIndex, + const uint32_t * InData_Nonce, + const uint32_t * InData_TextLen, + const uint32_t * InData_DataALen) +{ + return r_rsip_p97i(InData_KeyIndex, + &gs_cmd[CMD_CHACHA20_POLY1305_MODE_DECRYPT], + InData_Nonce, + InData_TextLen, + InData_DataALen); +} + +rsip_ret_t r_rsip_wrapper_p97r_enc (const uint32_t * InData_KeyIndex, + const uint32_t * InData_Nonce, + const uint32_t * InData_State) +{ + return r_rsip_p97r(InData_KeyIndex, &gs_cmd[CMD_CHACHA20_POLY1305_MODE_ENCRYPT], InData_Nonce, InData_State); +} + +rsip_ret_t r_rsip_wrapper_p97r_dec (const uint32_t * InData_KeyIndex, + const uint32_t * InData_Nonce, + const uint32_t * InData_State) +{ + return r_rsip_p97r(InData_KeyIndex, &gs_cmd[CMD_CHACHA20_POLY1305_MODE_DECRYPT], InData_Nonce, InData_State); +} + +#endif + +rsip_ret_t r_rsip_wrapper_pe2_wrapped_secp256r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_pe2(&gs_cmd[CMD_ECC_TYPE_NIST], + &gs_cmd[CMD_ECDH_PUBKEY_TYPE_WRAPPED], + InData_PubKey, + InData_KeyIndex, + DomainParam_NIST_P256, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_pe2_plain_secp256r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_pe2(&gs_cmd[CMD_ECC_TYPE_NIST], + &gs_cmd[CMD_ECDH_PUBKEY_TYPE_PLAIN], + InData_PubKey, + InData_KeyIndex, + DomainParam_NIST_P256, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_pe2_wrapped_brainpoolp256r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_pe2(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + &gs_cmd[CMD_ECDH_PUBKEY_TYPE_WRAPPED], + InData_PubKey, + InData_KeyIndex, + DomainParam_Brainpool_256r1, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_pe2_plain_brainpoolp256r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_pe2(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + &gs_cmd[CMD_ECDH_PUBKEY_TYPE_PLAIN], + InData_PubKey, + InData_KeyIndex, + DomainParam_Brainpool_256r1, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_p4e_wrapped_secp384r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_p4e(&gs_cmd[CMD_ECC_TYPE_NIST], + &gs_cmd[CMD_ECDH_PUBKEY_TYPE_WRAPPED], + InData_PubKey, + InData_KeyIndex, + DomainParam_NIST_P384, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_p4e_plain_secp384r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_p4e(&gs_cmd[CMD_ECC_TYPE_NIST], + &gs_cmd[CMD_ECDH_PUBKEY_TYPE_PLAIN], + InData_PubKey, + InData_KeyIndex, + DomainParam_NIST_P384, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_p4e_wrapped_brainpoolp384r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_p4e(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + &gs_cmd[CMD_ECDH_PUBKEY_TYPE_WRAPPED], + InData_PubKey, + InData_KeyIndex, + DomainParam_Brainpool_384r1, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_p4e_plain_brainpoolp384r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_p4e(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + &gs_cmd[CMD_ECDH_PUBKEY_TYPE_PLAIN], + InData_PubKey, + InData_KeyIndex, + DomainParam_Brainpool_384r1, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_p4f_wrapped_secp521r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_p4f(&gs_cmd[CMD_ECDH_PUBKEY_TYPE_WRAPPED], + InData_PubKey, + InData_KeyIndex, + DomainParam_NIST_P521, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_p4f_plain_secp521r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + uint32_t PubKey[RSIP_PRV_WORD_SIZE_ECC_521_PUBLIC_KEY] = {0}; + const uint32_t public_key_qx_pad_byte = RSIP_PRV_BYTE_SIZE_ECC_521_PADDING; + const uint32_t public_key_qy_pad_byte = RSIP_PRV_BYTE_SIZE_ECC_521_PADDING + + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM + + RSIP_PRV_BYTE_SIZE_ECC_521_PADDING; + + memcpy((uint8_t *) PubKey + public_key_qx_pad_byte, (uint8_t *) InData_PubKey, RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + memcpy((uint8_t *) PubKey + public_key_qy_pad_byte, + (uint8_t *) InData_PubKey + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + + return r_rsip_p4f(&gs_cmd[CMD_ECDH_PUBKEY_TYPE_PLAIN], + PubKey, + InData_KeyIndex, + DomainParam_NIST_P521, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_p5e_wrapped_brainpoolp512r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_p5e(&gs_cmd[CMD_ECDH_PUBKEY_TYPE_WRAPPED], + InData_PubKey, + InData_KeyIndex, + DomainParam_Brainpool_512r1, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_p5e_plain_brainpoolp512r1 (const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]) +{ + return r_rsip_p5e(&gs_cmd[CMD_ECDH_PUBKEY_TYPE_PLAIN], + InData_PubKey, + InData_KeyIndex, + DomainParam_Brainpool_512r1, + OutData_EncSecret); +} + +rsip_ret_t r_rsip_wrapper_peei_secp256r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_peei(&gs_cmd[CMD_ECC_TYPE_NIST], + InData_KeyIndex, + InData_MsgDgst, + InData_Signature, + DomainParam_NIST_P256); +} + +rsip_ret_t r_rsip_wrapper_peei_brainpoolp256r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_peei(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + InData_KeyIndex, + InData_MsgDgst, + InData_Signature, + DomainParam_Brainpool_256r1); +} + +rsip_ret_t r_rsip_wrapper_p51i_secp384r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_p51i(&gs_cmd[CMD_ECC_TYPE_NIST], + InData_KeyIndex, + InData_MsgDgst, + InData_Signature, + DomainParam_NIST_P384); +} + +rsip_ret_t r_rsip_wrapper_p51i_brainpoolp384r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_p51i(&gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + InData_KeyIndex, + InData_MsgDgst, + InData_Signature, + DomainParam_Brainpool_384r1); +} + +rsip_ret_t r_rsip_wrapper_p52i_secp521r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + uint32_t Signature[RSIP_PRV_WORD_SIZE_ECC_521_SIGNATURE] = {0}; + const uint32_t signature_r_pad_byte = RSIP_PRV_BYTE_SIZE_ECC_521_PADDING; + const uint32_t signature_s_pad_byte = RSIP_PRV_BYTE_SIZE_ECC_521_PADDING + + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM + + RSIP_PRV_BYTE_SIZE_ECC_521_PADDING; + + memcpy((uint8_t *) Signature + signature_r_pad_byte, (uint8_t *) InData_Signature, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + memcpy((uint8_t *) Signature + signature_s_pad_byte, + (uint8_t *) InData_Signature + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM, + RSIP_PRV_BYTE_SIZE_ECC_521_PARAM); + + return r_rsip_p52i(InData_KeyIndex, InData_MsgDgst, Signature, DomainParam_NIST_P521); +} + +rsip_ret_t r_rsip_wrapper_p5fi_brainpoolp512r1 (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + return r_rsip_p5fi(InData_KeyIndex, InData_MsgDgst, InData_Signature, DomainParam_Brainpool_512r1); +} + +rsip_ret_t r_rsip_wrapper_pe1_secp256r1 (const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_HashType); + + return r_rsip_pe1(&gs_cmd[CMD_PKI_KEY_TYPE_ECC_SECP256R1], + InData_Certificate, + InData_CertificateLength, + InData_CertificatePubKey, + InData_EncCertificateInfo, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe1_secp384r1 (const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_HashType); + + return r_rsip_pe1(&gs_cmd[CMD_PKI_KEY_TYPE_ECC_SECP384R1], + InData_Certificate, + InData_CertificateLength, + InData_CertificatePubKey, + InData_EncCertificateInfo, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe1_secp521r1 (const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_HashType); + + return r_rsip_pe1(&gs_cmd[CMD_PKI_KEY_TYPE_ECC_SECP521R1], + InData_Certificate, + InData_CertificateLength, + InData_CertificatePubKey, + InData_EncCertificateInfo, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe1_brainpoolp256r1 (const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_HashType); + + return r_rsip_pe1(&gs_cmd[CMD_PKI_KEY_TYPE_ECC_BRAINPOOLP256R1], + InData_Certificate, + InData_CertificateLength, + InData_CertificatePubKey, + InData_EncCertificateInfo, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe1_brainpoolp384r1 (const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_HashType); + + return r_rsip_pe1(&gs_cmd[CMD_PKI_KEY_TYPE_ECC_BRAINPOOLP384R1], + InData_Certificate, + InData_CertificateLength, + InData_CertificatePubKey, + InData_EncCertificateInfo, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe1_brainpoolp512r1 (const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_HashType); + + return r_rsip_pe1(&gs_cmd[CMD_PKI_KEY_TYPE_ECC_BRAINPOOLP512R1], + InData_Certificate, + InData_CertificateLength, + InData_CertificatePubKey, + InData_EncCertificateInfo, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe3_sha256 (const uint32_t InData_EncSecret[], uint32_t OutData_EncMsg[]) +{ + return r_rsip_pe3(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], NULL, InData_EncSecret, OutData_EncMsg); +} + +rsip_ret_t r_rsip_wrapper_pe3_sha384 (const uint32_t InData_EncSecret[], uint32_t OutData_EncMsg[]) +{ + return r_rsip_pe3(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], NULL, InData_EncSecret, OutData_EncMsg); +} + +rsip_ret_t r_rsip_wrapper_pe3_sha512_secp521r1 (const uint32_t InData_EncSecret[], uint32_t OutData_EncMsg[]) +{ + return r_rsip_pe3(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], &gs_cmd[CMD_ECC_TYPE_NIST], InData_EncSecret, OutData_EncMsg); +} + +rsip_ret_t r_rsip_wrapper_pe3_sha512_brainpoolp512r1 (const uint32_t InData_EncSecret[], uint32_t OutData_EncMsg[]) +{ + return r_rsip_pe3(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], + &gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + InData_EncSecret, + OutData_EncMsg); +} + +rsip_ret_t r_rsip_wrapper_pe4_sha256 (const uint32_t InData_EncSecret[], uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe4(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], NULL, InData_EncSecret, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe4_sha384 (const uint32_t InData_EncSecret[], uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe4(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], NULL, InData_EncSecret, OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe4_sha512_secp521r1 (const uint32_t InData_EncSecret[], uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe4(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], &gs_cmd[CMD_ECC_TYPE_NIST], InData_EncSecret, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe4_sha512_brainpoolp512r1 (const uint32_t InData_EncSecret[], uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe4(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], + &gs_cmd[CMD_ECC_TYPE_BRAINPOOL], + InData_EncSecret, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe6_sha256 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe6(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], + InData_KDFInfo, + InData_KDFInfo_Count, + InData_OutDataLength, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe6_sha384 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe6(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], + InData_KDFInfo, + InData_KDFInfo_Count, + InData_OutDataLength, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe6_sha512 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe6(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], + InData_KDFInfo, + InData_KDFInfo_Count, + InData_OutDataLength, + OutData_KeyIndex); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha256_aes128 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], InData_KDFInfo, InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_AES128], InData_OutDataLocation, NULL, NULL, OutData_KeyIndex, NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha256_aes256 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], InData_KDFInfo, InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_AES256], InData_OutDataLocation, NULL, NULL, OutData_KeyIndex, NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha256_hmac_sha256 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA256], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha256_hmac_sha384 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA384], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha256_hmac_sha512 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA512], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha256_iv_aes (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_EncIV[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA256], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_IV_AES], + InData_OutDataLocation, + InData_SeqNum, + NULL, + NULL, + OutData_EncIV); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha384_aes128 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], InData_KDFInfo, InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_AES128], InData_OutDataLocation, NULL, NULL, OutData_KeyIndex, NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha384_aes256 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], InData_KDFInfo, InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_AES256], InData_OutDataLocation, NULL, NULL, OutData_KeyIndex, NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha384_hmac_sha256 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA256], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha384_hmac_sha384 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA384], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha384_hmac_sha512 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA512], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha384_iv_aes (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_EncIV[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA384], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_IV_AES], + InData_OutDataLocation, + InData_SeqNum, + NULL, + NULL, + OutData_EncIV); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha512_aes128 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], InData_KDFInfo, InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_AES128], InData_OutDataLocation, NULL, NULL, OutData_KeyIndex, NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha512_aes256 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], InData_KDFInfo, InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_AES256], InData_OutDataLocation, NULL, NULL, OutData_KeyIndex, NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha512_hmac_sha256 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA256], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha512_hmac_sha384 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA384], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha512_hmac_sha512 (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_HMAC_SHA512], + InData_OutDataLocation, + NULL, + OutData_HMACKeyIndex, + NULL, + NULL); +} + +rsip_ret_t r_rsip_wrapper_pe7_sha512_iv_aes (const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_EncIV[]) +{ + return r_rsip_pe7(&gs_cmd[CMD_KDF_HASH_TYPE_SHA512], + InData_KDFInfo, + InData_KDFInfo_Count, + &gs_cmd[CMD_KDF_OUTDATA_TYPE_IV_AES], + InData_OutDataLocation, + InData_SeqNum, + NULL, + NULL, + OutData_EncIV); +} + +rsip_ret_t r_rsip_wrapper_p2c_ch0 (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ +#if BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED + + return r_rsip_p2c(InData_KeyIndex, InData_DOTFSEED); +#else + + return r_rsip_p2c(&gs_cmd[CMD_OTF_CHANNEL_0], InData_KeyIndex, InData_DOTFSEED); +#endif +}; + +rsip_ret_t r_rsip_wrapper_p2d_ch0 (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ +#if BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED + + return r_rsip_p2d(InData_KeyIndex, InData_DOTFSEED); +#else + + return r_rsip_p2d(&gs_cmd[CMD_OTF_CHANNEL_0], InData_KeyIndex, InData_DOTFSEED); +#endif +}; + +rsip_ret_t r_rsip_wrapper_p2e_ch0 (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ +#if BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED + + return r_rsip_p2e(InData_KeyIndex, InData_DOTFSEED); +#else + + return r_rsip_p2e(&gs_cmd[CMD_OTF_CHANNEL_0], InData_KeyIndex, InData_DOTFSEED); +#endif +}; + +#if BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED +rsip_ret_t r_rsip_wrapper_p2c_ch1 (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ + return r_rsip_p2c(&gs_cmd[CMD_OTF_CHANNEL_1], InData_KeyIndex, InData_DOTFSEED); +}; + +rsip_ret_t r_rsip_wrapper_p2d_ch1 (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ + return r_rsip_p2d(&gs_cmd[CMD_OTF_CHANNEL_1], InData_KeyIndex, InData_DOTFSEED); +}; + +rsip_ret_t r_rsip_wrapper_p2e_ch1 (const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]) +{ + return r_rsip_p2e(&gs_cmd[CMD_OTF_CHANNEL_1], InData_KeyIndex, InData_DOTFSEED); +}; +#endif + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Converts byte length to word (4-byte) length and rounds up it. For unsigned 64-bit data. + * + * @param[in] bytes Byte length + * + * @return Word length + ***********************************************************************************************************************/ +RSIP_PRV_STATIC_INLINE uint64_t r_rsip_byte_to_word_convert_u64 (const uint64_t bytes) +{ + return (bytes + 3) >> 2; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.h new file mode 100644 index 0000000000..6a434a18d8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/private/ra_rsip_e5xx/r_rsip_wrapper.h @@ -0,0 +1,1011 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_RSIP_WRAPPER_H +#define R_RSIP_WRAPPER_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_primitive.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Primitive function names */ +#define RSIP_PRV_FUNC_NAME_RANDOM_NUMBER_GENERATE r_rsip_p20 + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_128 r_rsip_p07 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_128 r_rsip_wrapper_p6f_aes128 + +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_128 r_rsip_wrapper_p47i_ecb_enc +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_128 r_rsip_wrapper_p47i_ecb_dec +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_128 r_rsip_wrapper_p47i_cbc_enc +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_128 r_rsip_wrapper_p47i_cbc_dec +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_128_WRAPPED_IV r_rsip_wrapper_p47i_cbc_enc_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_128_WRAPPED_IV r_rsip_wrapper_p47i_cbc_dec_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_128 r_rsip_wrapper_p47i_ctr +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_128 r_rsip_p47u +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_128 r_rsip_p47f + +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_128 r_rsip_wrapper_p29i_plain_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_128_WRAPPED_IV r_rsip_wrapper_p29i_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_128 r_rsip_p29a +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_128 r_rsip_p29t +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_128 r_rsip_p29u +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_128 r_rsip_p29f +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_128 r_rsip_wrapper_p32i_plain_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_128_WRAPPED_IV r_rsip_wrapper_p32i_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_128 r_rsip_p32a +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_128 r_rsip_p32t +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_128 r_rsip_p32u +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_128 r_rsip_p32f + +#define RSIP_PRV_FUNC_NAME_GHASH_COMPUTE r_rsip_p21 + +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_128 r_rsip_wrapper_p95i_aes128ccm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_128 r_rsip_p95u +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_128 r_rsip_wrapper_p95f_aes128ccm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_128 r_rsip_wrapper_p98i_aes128ccm_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_128 r_rsip_p98u +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_128 r_rsip_wrapper_p98f_aes128ccm_decrypt + +#define RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_128 r_rsip_p41i +#define RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_128 r_rsip_p41u +#define RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_128 r_rsip_wrapper_p41f_aes128mac_generate +#define RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_128 r_rsip_wrapper_p41f_aes128mac_verify + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_192 r_rsip_p15 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_192 r_rsip_wrapper_p6f_aes192 + +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_192 r_rsip_wrapper_p89i_ecb_enc +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_192 r_rsip_wrapper_p89i_ecb_dec +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_192 r_rsip_wrapper_p89i_cbc_enc +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_192 r_rsip_wrapper_p89i_cbc_dec +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_192_WRAPPED_IV r_rsip_wrapper_p89i_cbc_enc_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_192_WRAPPED_IV r_rsip_wrapper_p89i_cbc_dec_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_192 r_rsip_wrapper_p89i_ctr +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_192 r_rsip_p89u +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_192 r_rsip_p89f + +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_192 r_rsip_wrapper_p83i_plain_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_192_WRAPPED_IV r_rsip_wrapper_p83i_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_192 r_rsip_p83a +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_192 r_rsip_p83t +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_192 r_rsip_p83u +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_192 r_rsip_p83f +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_192 r_rsip_wrapper_p85i_plain_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_192_WRAPPED_IV r_rsip_wrapper_p85i_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_192 r_rsip_p85a +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_192 r_rsip_p85t +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_192 r_rsip_p85u +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_192 r_rsip_p85f + +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_192 r_rsip_wrapper_pa7i_aes192ccm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_192 r_rsip_pa7u +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_192 r_rsip_wrapper_pa7f_aes192ccm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_192 r_rsip_wrapper_pb0i_aes192ccm_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_192 r_rsip_pb0u +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_192 r_rsip_wrapper_pb0f_aes192ccm_decrypt + +#define RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_192 r_rsip_p87i +#define RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_192 r_rsip_p87u +#define RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_192 r_rsip_wrapper_p87f_aes192mac_generate +#define RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_192 r_rsip_wrapper_p87f_aes192mac_verify + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_AES_256 r_rsip_p08 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_AES_256 r_rsip_wrapper_p6f_aes256 + +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_ENC_256 r_rsip_wrapper_p50i_ecb_enc +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_ECB_DEC_256 r_rsip_wrapper_p50i_ecb_dec +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_256 r_rsip_wrapper_p50i_cbc_enc +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_256 r_rsip_wrapper_p50i_cbc_dec +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_ENC_256_WRAPPED_IV r_rsip_wrapper_p50i_cbc_enc_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CBC_DEC_256_WRAPPED_IV r_rsip_wrapper_p50i_cbc_dec_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_INIT_CTR_256 r_rsip_wrapper_p50i_ctr +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_UPDATE_256 r_rsip_p50u +#define RSIP_PRV_FUNC_NAME_AES_CIPHER_FINAL_256 r_rsip_p50f + +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_256 r_rsip_wrapper_p34i_plain_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_INIT_256_WRAPPED_IV r_rsip_wrapper_p34i_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_AAD_256 r_rsip_p34a +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_TRANSITION_256 r_rsip_p34t +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_UPDATE_256 r_rsip_p34u +#define RSIP_PRV_FUNC_NAME_AES_GCM_ENC_FINAL_256 r_rsip_p34f +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_256 r_rsip_wrapper_p36i_plain_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_INIT_256_WRAPPED_IV r_rsip_wrapper_p36i_wrapped_iv +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_AAD_256 r_rsip_p36a +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_TRANSITION_256 r_rsip_p36t +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_UPDATE_256 r_rsip_p36u +#define RSIP_PRV_FUNC_NAME_AES_GCM_DEC_FINAL_256 r_rsip_p36f + +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_INIT_256 r_rsip_wrapper_pa1i_aes256ccm_encrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_UPDATE_256 r_rsip_pa1u +#define RSIP_PRV_FUNC_NAME_AES_CCM_ENC_FINAL_256 r_rsip_pa1f +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_INIT_256 r_rsip_wrapper_pa4i_aes256ccm_decrypt +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_UPDATE_256 r_rsip_pa4u +#define RSIP_PRV_FUNC_NAME_AES_CCM_DEC_FINAL_256 r_rsip_pa4f + +#define RSIP_PRV_FUNC_NAME_AES_CMAC_INIT_256 r_rsip_p44i +#define RSIP_PRV_FUNC_NAME_AES_CMAC_UPDATE_256 r_rsip_p44u +#define RSIP_PRV_FUNC_NAME_AES_CMAC_GENERATE_FINAL_256 r_rsip_wrapper_p44f_aes256mac_generate +#define RSIP_PRV_FUNC_NAME_AES_CMAC_VERIFY_FINAL_256 r_rsip_wrapper_p44f_aes256mac_verify +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_XTS_AES_128 r_rsip_p16 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_XTS_AES_128 r_rsip_wrapper_p6f_aes128xts + +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_INIT_128 r_rsip_pb3i +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_UPDATE_128 r_rsip_pb3u +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_FINAL_128 r_rsip_pb3f +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_INIT_128 r_rsip_pb6i +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_UPDATE_128 r_rsip_pb6u +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_FINAL_128 r_rsip_pb6f + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_XTS_AES_256 r_rsip_p17 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_XTS_AES_256 r_rsip_wrapper_p6f_aes256xts + +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_INIT_256 r_rsip_pb9i +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_UPDATE_256 r_rsip_pb9u +#define RSIP_PRV_FUNC_NAME_XTS_AES_ENC_FINAL_256 r_rsip_pb9f +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_INIT_256 r_rsip_pc2i +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_UPDATE_256 r_rsip_pc2u +#define RSIP_PRV_FUNC_NAME_XTS_AES_DEC_FINAL_256 r_rsip_pc2f + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_CHACHA20 r_rsip_p39 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_CHACHA20 r_rsip_wrapper_p6f_chacha20 + +#define RSIP_PRV_FUNC_NAME_CHACHA20_INIT r_rsip_p96i +#define RSIP_PRV_FUNC_NAME_CHACHA20_UPDATE r_rsip_p96u +#define RSIP_PRV_FUNC_NAME_CHACHA20_FINAL r_rsip_p96f +#define RSIP_PRV_FUNC_NAME_CHACHA20_SUSPEND r_rsip_p96s +#define RSIP_PRV_FUNC_NAME_CHACHA20_RESUME r_rsip_p96r + +#if BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_ENC_INIT r_rsip_wrapper_p97i_enc + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_DEC_INIT r_rsip_wrapper_p97i_dec + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE_AAD r_rsip_p97a + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE_TRANSITION r_rsip_p97t + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE r_rsip_p97u + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_FINAL r_rsip_p97f + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_SUSPEND r_rsip_p97s + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_ENC_RESUME r_rsip_wrapper_p97r_enc + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_DEC_RESUME r_rsip_wrapper_p97r_dec +#else + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_ENC_INIT NULL + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_DEC_INIT NULL + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE_AAD NULL + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE_TRANSITION NULL + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_UPDATE NULL + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_FINAL NULL + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_SUSPEND NULL + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_ENC_RESUME NULL + #define RSIP_PRV_FUNC_NAME_CHACHA20_POLY1305_DEC_RESUME NULL +#endif + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP256R1 r_rsip_wrapper_pf4_secp256r1 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256R1_PUBLIC r_rsip_wrapper_p6f_secp256r1_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256R1_PRIVATE r_rsip_wrapper_p6f_secp256r1_priv + +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP256R1 r_rsip_wrapper_pf0_secp256r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP256R1 r_rsip_wrapper_pf1_secp256r1 + +#define RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_SECP256R1 r_rsip_wrapper_pe2_wrapped_secp256r1 +#define RSIP_PRV_FUNC_NAME_ECDH_PLAIN_SECP256R1 r_rsip_wrapper_pe2_plain_secp256r1 + +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_SECP256R1 r_rsip_wrapper_peei_secp256r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_SECP256R1 r_rsip_peef +#define RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_SECP256R1 r_rsip_wrapper_pe1_secp256r1 + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP384R1 r_rsip_wrapper_pf9_secp384r1 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP384R1_PUBLIC r_rsip_wrapper_p6f_secp384r1_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP384R1_PRIVATE r_rsip_wrapper_p6f_secp384r1_priv + +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP384R1 r_rsip_wrapper_pf5_secp384r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP384R1 r_rsip_wrapper_pf6_secp384r1 + +#define RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_SECP384R1 r_rsip_wrapper_p4e_wrapped_secp384r1 +#define RSIP_PRV_FUNC_NAME_ECDH_PLAIN_SECP384R1 r_rsip_wrapper_p4e_plain_secp384r1 + +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_SECP384R1 r_rsip_wrapper_p51i_secp384r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_SECP384R1 r_rsip_p51f +#define RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_SECP384R1 r_rsip_wrapper_pe1_secp384r1 + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP521R1 r_rsip_wrapper_p13_secp521r1 +#define RSIP_PRV_FUNC_NAME_KEY_WRAP_ECC_SECP521R1_PUBLIC r_rsip_wrapper_p6f_secp521r1_pub +#define RSIP_PRV_FUNC_NAME_KEY_WRAP_ECC_SECP521R1_PRIVATE r_rsip_wrapper_p6f_secp521r1_priv + +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP521R1 r_rsip_wrapper_p11_secp521r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP521R1 r_rsip_wrapper_p12_secp521r1 + +#define RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_SECP521R1 r_rsip_wrapper_p4f_wrapped_secp521r1 +#define RSIP_PRV_FUNC_NAME_ECDH_PLAIN_SECP521R1 r_rsip_wrapper_p4f_plain_secp521r1 + +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_SECP521R1 r_rsip_wrapper_p52i_secp521r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_SECP521R1 r_rsip_p52f +#define RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_SECP521R1 r_rsip_wrapper_pe1_secp521r1 + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_SECP256K1 r_rsip_wrapper_pf4_secp256k1 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256K1_PUBLIC r_rsip_wrapper_p6f_secp256k1_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_SECP256K1_PRIVATE r_rsip_wrapper_p6f_secp256k1_priv +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_SECP256K1 r_rsip_wrapper_pf0_secp256k1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_SECP256K1 r_rsip_wrapper_pf1_secp256k1 + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_BRAINPOOLP256R1 r_rsip_wrapper_pf4_brainpoolp256r1 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PUBLIC r_rsip_wrapper_p6f_brainpoolp256r1_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP256R1_PRIVATE r_rsip_wrapper_p6f_brainpoolp256r1_priv +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_BRAINPOOLP256R1 r_rsip_wrapper_pf0_brainpoolp256r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_BRAINPOOLP256R1 r_rsip_wrapper_pf1_brainpoolp256r1 +#define RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_BRAINPOOLP256R1 r_rsip_wrapper_pe2_wrapped_brainpoolp256r1 +#define RSIP_PRV_FUNC_NAME_ECDH_PLAIN_BRAINPOOLP256R1 r_rsip_wrapper_pe2_plain_brainpoolp256r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP256R1 r_rsip_wrapper_peei_brainpoolp256r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP256R1 r_rsip_peef +#define RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP256R1 r_rsip_wrapper_pe1_brainpoolp256r1 + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_BRAINPOOLP384R1 r_rsip_wrapper_pf9_brainpoolp384r1 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PUBLIC r_rsip_wrapper_p6f_brainpoolp384r1_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP384R1_PRIVATE r_rsip_wrapper_p6f_brainpoolp384r1_priv +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_BRAINPOOLP384R1 r_rsip_wrapper_pf5_brainpoolp384r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_BRAINPOOLP384R1 r_rsip_wrapper_pf6_brainpoolp384r1 +#define RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_BRAINPOOLP384R1 r_rsip_wrapper_p4e_wrapped_brainpoolp384r1 +#define RSIP_PRV_FUNC_NAME_ECDH_PLAIN_BRAINPOOLP384R1 r_rsip_wrapper_p4e_plain_brainpoolp384r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP384R1 r_rsip_wrapper_p51i_brainpoolp384r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP384R1 r_rsip_p51f +#define RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP384R1 r_rsip_wrapper_pe1_brainpoolp384r1 + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_BRAINPOOLP512R1 r_rsip_wrapper_p7f_brainpoolp512r1 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PUBLIC r_rsip_wrapper_p6f_brainpoolp512r1_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_BRAINPOOLP512R1_PRIVATE r_rsip_wrapper_p6f_brainpoolp512r1_priv +#define RSIP_PRV_FUNC_NAME_ECDSA_SIGN_BRAINPOOLP512R1 r_rsip_wrapper_p7d_brainpoolp512r1 +#define RSIP_PRV_FUNC_NAME_ECDSA_VERIFY_BRAINPOOLP512R1 r_rsip_wrapper_p7e_brainpoolp512r1 +#define RSIP_PRV_FUNC_NAME_ECDH_WRAPPED_BRAINPOOLP512R1 r_rsip_wrapper_p5e_wrapped_brainpoolp512r1 +#define RSIP_PRV_FUNC_NAME_ECDH_PLAIN_BRAINPOOLP512R1 r_rsip_wrapper_p5e_plain_brainpoolp512r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_INIT_BRAINPOOLP512R1 r_rsip_wrapper_p5fi_brainpoolp512r1 +#define RSIP_PRV_FUNC_NAME_PKI_ECDSA_VERIFY_FINAL_BRAINPOOLP512R1 r_rsip_p5ff +#define RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_ECC_BRAINPOOLP512R1 r_rsip_wrapper_pe1_brainpoolp512r1 + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_ECC_EDWARDS25519 r_rsip_wrapper_p1a_edwards25519 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_EDWARDS25519_PUBLIC r_rsip_wrapper_p6f_edwards25519_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_ECC_EDWARDS25519_PRIVATE r_rsip_wrapper_p6f_edwards25519_priv +#define RSIP_PRV_FUNC_NAME_EDDSA_SIGN_EDWARDS25519 r_rsip_wrapper_p18_edwards25519 +#define RSIP_PRV_FUNC_NAME_EDDSA_VERIFY_EDWARDS25519 r_rsip_wrapper_p19_edwards25519 + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_2048 r_rsip_wrapper_p2b_rsa2048 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_2048_PUBLIC r_rsip_wrapper_p6f_rsa2048_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_2048_PRIVATE r_rsip_wrapper_p6f_rsa2048_priv + +#define RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_2048 r_rsip_p56 +#define RSIP_PRV_FUNC_NAME_RSA_DECRYPT_2048 r_rsip_p57 + +#define RSIP_PRV_FUNC_NAME_PKI_RSA_VERIFY_INIT_2048 NULL +#define RSIP_PRV_FUNC_NAME_PKI_RSA_VERIFY_FINAL_2048 NULL +#define RSIP_PRV_FUNC_NAME_PKI_CERT_KEY_IMPORT_RSA_2048 NULL + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_3072 r_rsip_wrapper_p3a_rsa3072 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_3072_PUBLIC r_rsip_wrapper_p6f_rsa3072_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_3072_PRIVATE r_rsip_wrapper_p6f_rsa3072_priv + +#define RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_3072 r_rsip_p79 +#define RSIP_PRV_FUNC_NAME_RSA_DECRYPT_3072 r_rsip_p7a + +#define RSIP_PRV_FUNC_NAME_KEY_PAIR_GENERATE_RSA_4096 r_rsip_wrapper_p3b_rsa4096 +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_4096_PUBLIC r_rsip_wrapper_p6f_rsa4096_pub +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_RSA_4096_PRIVATE r_rsip_wrapper_p6f_rsa4096_priv + +#define RSIP_PRV_FUNC_NAME_RSA_ENCRYPT_4096 r_rsip_p7b +#define RSIP_PRV_FUNC_NAME_RSA_DECRYPT_4096 r_rsip_p7c + +#define RSIP_PRV_FUNC_NAME_SHA1SHA2_INIT r_rsip_p73i +#define RSIP_PRV_FUNC_NAME_SHA1SHA2_RESUME r_rsip_p73r +#define RSIP_PRV_FUNC_NAME_SHA1SHA2_UPDATE r_rsip_p73u +#define RSIP_PRV_FUNC_NAME_SHA1SHA2_SUSPEND r_rsip_p73s +#define RSIP_PRV_FUNC_NAME_SHA1SHA2_FINAL r_rsip_p73f + +#if RSIP_CFG_SHA3_224_ENABLE || RSIP_CFG_SHA3_256_ENABLE || RSIP_CFG_SHA3_384_ENABLE || RSIP_CFG_SHA3_512_ENABLE + #define RSIP_PRV_FUNC_NAME_SHA3_INIT r_rsip_p78i + #define RSIP_PRV_FUNC_NAME_SHA3_RESUME r_rsip_p78r + #define RSIP_PRV_FUNC_NAME_SHA3_UPDATE r_rsip_p78u + #define RSIP_PRV_FUNC_NAME_SHA3_SUSPEND r_rsip_p78s + #define RSIP_PRV_FUNC_NAME_SHA3_FINAL r_rsip_p78f +#endif + +#define RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_INIT r_rsip_p75i +#define RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_RESUME r_rsip_p75r +#define RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_UPDATE r_rsip_p75u +#define RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_SUSPEND r_rsip_p75s +#define RSIP_PRV_FUNC_NAME_HMAC_SHA1SHA2_FINAL r_rsip_p75f + +#define RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_INIT r_rsip_pefi +#define RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_RESUME r_rsip_pefr +#define RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_ENC_UPDATE r_rsip_pefe +#define RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_UPDATE r_rsip_pefu +#define RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_SUSPEND r_rsip_pefs +#define RSIP_PRV_FUNC_NAME_KDF_SHA1SHA2_FINAL r_rsip_peff + +#define RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_INIT r_rsip_pe5i +#define RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_RESUME r_rsip_pe5r +#define RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_ENC_UPDATE r_rsip_pe5e +#define RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_UPDATE r_rsip_pe5u +#define RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_SUSPEND r_rsip_pe5s +#define RSIP_PRV_FUNC_NAME_KDF_HMAC_SHA1SHA2_FINAL r_rsip_pe5f + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA224 r_rsip_p0a +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA224 r_rsip_wrapper_p6f_hmacsha224 + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA256 r_rsip_p0b +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA256 r_rsip_wrapper_p6f_hmacsha256 + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA384 r_rsip_p3c +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA384 r_rsip_wrapper_p6f_hmacsha384 + +#define RSIP_PRV_FUNC_NAME_KEY_GENERATE_HMAC_SHA512 r_rsip_p3d +#define RSIP_PRV_FUNC_NAME_ENC_KEY_WRAP_HMAC_SHA512 r_rsip_wrapper_p6f_hmacsha512 + +#define RSIP_PRV_FUNC_NAME_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA256 r_rsip_wrapper_pe3_sha256 +#define RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_128 r_rsip_wrapper_pe7_sha256_aes128 +#define RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_KEY_IMPORT_SHA256_AES_256 r_rsip_wrapper_pe7_sha256_aes256 +#define RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_IV_WRAP_SHA256_AES r_rsip_wrapper_pe7_sha256_iv_aes + +#define RSIP_PRV_FUNC_NAME_KDF_SHA_ECDH_SECRET_MSG_WRAP_SHA384 r_rsip_wrapper_pe3_sha384 +#define RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_128 r_rsip_wrapper_pe7_sha384_aes128 +#define RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_KEY_IMPORT_SHA384_AES_256 r_rsip_wrapper_pe7_sha384_aes256 +#define RSIP_PRV_FUNC_NAME_KDF_SHA_DERIVED_IV_WRAP_SHA384_AES r_rsip_wrapper_pe7_sha384_iv_aes + +#define RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_KEY_IMPORT_SHA256 r_rsip_wrapper_pe4_sha256 +#define RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_MSG_WRAP_SHA256 r_rsip_wrapper_pe3_sha256 +#define RSIP_PRV_FUNC_NAME_KDF_MAC_KEY_IMPORT_SHA256 r_rsip_wrapper_pe6_sha256 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_AES_128 r_rsip_wrapper_pe7_sha256_aes128 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_AES_256 r_rsip_wrapper_pe7_sha256_aes256 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA1 NULL +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA256 r_rsip_wrapper_pe7_sha256_hmac_sha256 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA384 r_rsip_wrapper_pe7_sha256_hmac_sha384 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA256_HMAC_SHA512 r_rsip_wrapper_pe7_sha256_hmac_sha512 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA256_AES r_rsip_wrapper_pe7_sha256_iv_aes +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA256_TLS12 NULL +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA256_TLS13 NULL + +#define RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_KEY_IMPORT_SHA384 r_rsip_wrapper_pe4_sha384 +#define RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_MSG_WRAP_SHA384 r_rsip_wrapper_pe3_sha384 +#define RSIP_PRV_FUNC_NAME_KDF_MAC_KEY_IMPORT_SHA384 r_rsip_wrapper_pe6_sha384 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_AES_128 r_rsip_wrapper_pe7_sha384_aes128 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_AES_256 r_rsip_wrapper_pe7_sha384_aes256 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA1 NULL +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA256 r_rsip_wrapper_pe7_sha384_hmac_sha256 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA384 r_rsip_wrapper_pe7_sha384_hmac_sha384 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA384_HMAC_SHA512 r_rsip_wrapper_pe7_sha384_hmac_sha512 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA384_AES r_rsip_wrapper_pe7_sha384_iv_aes +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA384_TLS12 NULL +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA384_TLS13 NULL + +#define RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_SECP521R1 r_rsip_wrapper_pe4_sha512_secp521r1 +#define RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_KEY_IMPORT_SHA512_BRAINPOOLP512R1 \ + r_rsip_wrapper_pe4_sha512_brainpoolp512r1 +#define RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_MSG_WRAP_SHA512_SECP521R1 r_rsip_wrapper_pe3_sha512_secp521r1 +#define RSIP_PRV_FUNC_NAME_KDF_ECDH_SECRET_MSG_WRAP_SHA512_BRAINPOOLP512R1 r_rsip_wrapper_pe3_sha512_brainpoolp512r1 +#define RSIP_PRV_FUNC_NAME_KDF_MAC_KEY_IMPORT_SHA512 r_rsip_wrapper_pe6_sha512 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_AES_128 r_rsip_wrapper_pe7_sha512_aes128 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_AES_256 r_rsip_wrapper_pe7_sha512_aes256 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA1 NULL +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA256 r_rsip_wrapper_pe7_sha512_hmac_sha256 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA384 r_rsip_wrapper_pe7_sha512_hmac_sha384 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_KEY_IMPORT_SHA512_HMAC_SHA512 r_rsip_wrapper_pe7_sha512_hmac_sha512 +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA512_AES r_rsip_wrapper_pe7_sha512_iv_aes +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA512_TLS12 NULL +#define RSIP_PRV_FUNC_NAME_KDF_DERIVED_IV_WRAP_SHA512_TLS13 NULL + +#define RSIP_PRV_FUNC_NAME_RFC3394_AES_128_KEY_WRAP r_rsip_wrapper_p8f_aes128 +#define RSIP_PRV_FUNC_NAME_RFC3394_AES_128_KEY_UNWRAP r_rsip_wrapper_p90_aes128 +#define RSIP_PRV_FUNC_NAME_RFC3394_AES_256_KEY_WRAP r_rsip_wrapper_p8f_aes256 +#define RSIP_PRV_FUNC_NAME_RFC3394_AES_256_KEY_UNWRAP r_rsip_wrapper_p90_aes256 + +#define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_128 r_rsip_wrapper_p2c_ch0 +#define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_192 r_rsip_wrapper_p2d_ch0 +#define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_0_AES_256 r_rsip_wrapper_p2e_ch0 +#if BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED + #define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_128 r_rsip_wrapper_p2c_ch1 + #define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_192 r_rsip_wrapper_p2d_ch1 + #define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_256 r_rsip_wrapper_p2e_ch1 +#else + #define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_128 NULL + #define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_192 NULL + #define RSIP_PRV_FUNC_NAME_OTF_CHANNEL_1_AES_256 NULL +#endif + +/* Key update inst data word */ +#define RSIP_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0U) +#define RSIP_OEM_KEY_SIZE_AES128_INST_DATA_WORD (8U) +#define RSIP_OEM_KEY_SIZE_AES192_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_AES256_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD (20U) + +#define RSIP_OEM_KEY_SIZE_CHACHA20_INST_DATA_WORD (12U) + +#define RSIP_OEM_KEY_SIZE_ECC_SECP256R1_PUBLIC_KEY_INST_DATA_WORD (20U) +#define RSIP_OEM_KEY_SIZE_ECC_SECP256R1_PRIVATE_KEY_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_ECC_SECP384R1_PUBLIC_KEY_INST_DATA_WORD (28U) +#define RSIP_OEM_KEY_SIZE_ECC_SECP384R1_PRIVATE_KEY_INST_DATA_WORD (16U) +#define RSIP_OEM_KEY_SIZE_ECC_SECP521R1_PUBLIC_KEY_INST_DATA_WORD (44U) +#define RSIP_OEM_KEY_SIZE_ECC_SECP521R1_PRIVATE_KEY_INST_DATA_WORD (24U) +#define RSIP_OEM_KEY_SIZE_ECC_SECP256K1_PUBLIC_KEY_INST_DATA_WORD (20U) +#define RSIP_OEM_KEY_SIZE_ECC_SECP256K1_PRIVATE_KEY_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP256R1_PUBLIC_KEY_INST_DATA_WORD (20U) +#define RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP256R1_PRIVATE_KEY_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP384R1_PUBLIC_KEY_INST_DATA_WORD (28U) +#define RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP384R1_PRIVATE_KEY_INST_DATA_WORD (16U) +#define RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP512R1_PUBLIC_KEY_INST_DATA_WORD (36U) +#define RSIP_OEM_KEY_SIZE_ECC_BRAINPOOLP512R1_PRIVATE_KEY_INST_DATA_WORD (20U) +#define RSIP_OEM_KEY_SIZE_ECC_EDWARDS25519_PUBLIC_KEY_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_ECC_EDWARDS25519_PRIVATE_KEY_INST_DATA_WORD (12U) + +#define RSIP_OEM_KEY_SIZE_HMAC_SHA224_KEY_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_HMAC_SHA256_KEY_INST_DATA_WORD (12U) +#define RSIP_OEM_KEY_SIZE_HMAC_SHA384_KEY_INST_DATA_WORD (16U) +#define RSIP_OEM_KEY_SIZE_HMAC_SHA512_KEY_INST_DATA_WORD (20U) + +#define RSIP_OEM_KEY_SIZE_RSA2048_PUBLIC_KEY_INST_DATA_WORD (72U) +#define RSIP_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132U) +#define RSIP_OEM_KEY_SIZE_RSA3072_PUBLIC_KEY_INST_DATA_WORD (104U) +#define RSIP_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD (196U) +#define RSIP_OEM_KEY_SIZE_RSA4096_PUBLIC_KEY_INST_DATA_WORD (136U) +#define RSIP_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD (260U) + +#define RSIP_PRV_PKI_HASH_TYPE_SHA1 (0U) +#define RSIP_PRV_PKI_HASH_TYPE_SHA224 (0U) +#define RSIP_PRV_PKI_HASH_TYPE_SHA256 (1U) +#define RSIP_PRV_PKI_HASH_TYPE_SHA384 (4U) +#define RSIP_PRV_PKI_HASH_TYPE_SHA512 (5U) +#define RSIP_PRV_PKI_HASH_TYPE_SHA512_224 (2U) +#define RSIP_PRV_PKI_HASH_TYPE_SHA512_256 (3U) + +typedef enum e_rsip_ecc_curve_type +{ + RSIP_ECC_CURVE_TYPE_NIST +} rsip_ecc_type_t; + +typedef enum e_rsip_ecc_cmd_type +{ + RSIP_ECC_CMD_P256 +} rsip_ecc_cmd_type_t; + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +rsip_ret_t r_rsip_wrapper_pf0_secp256r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf1_secp256r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf4_secp256r1(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pf5_secp384r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf6_secp384r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf9_secp384r1(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_p11_secp521r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_wrapper_p12_secp521r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); +rsip_ret_t r_rsip_wrapper_p13_secp521r1(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pf0_secp256k1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf1_secp256k1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf4_secp256k1(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pf0_brainpoolp256r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf1_brainpoolp256r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf4_brainpoolp256r1(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pf5_brainpoolp384r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf6_brainpoolp384r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); +rsip_ret_t r_rsip_wrapper_pf9_brainpoolp384r1(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_p7d_brainpoolp512r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_wrapper_p7e_brainpoolp512r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); +rsip_ret_t r_rsip_wrapper_p7f_brainpoolp512r1(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_p18_edwards25519(const uint32_t InData_PrivKeyIndex[], + const uint32_t InData_PubKeyIndex[], + const uint32_t InData_Msg[], + const uint64_t InData_MsgLen, + uint32_t OutData_Signature[]); +rsip_ret_t r_rsip_wrapper_p19_edwards25519(const uint32_t InData_KeyIndex[], + const uint32_t InData_Msg[], + const uint64_t InData_MsgLen, + const uint32_t InData_Signature[]); +rsip_ret_t r_rsip_wrapper_p1a_edwards25519(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_p2b_rsa2048(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_p3a_rsa3072(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_p3b_rsa4096(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_aes128(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_aes192(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_aes256(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_aes128xts(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_aes256xts(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_chacha20(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_secp256r1_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_secp256r1_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_secp384r1_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_secp384r1_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_secp521r1_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_secp521r1_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_secp256k1_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_secp256k1_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp256r1_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp256r1_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp384r1_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp384r1_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp512r1_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_brainpoolp512r1_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_edwards25519_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_edwards25519_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_rsa2048_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_rsa2048_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_rsa3072_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_rsa3072_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_rsa4096_pub(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_rsa4096_priv(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_hmacsha224(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_hmacsha256(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_hmacsha384(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p6f_hmacsha512(const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_p8f_aes128(const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_WrappedKeyIndex[], + uint32_t OutData_Text[], + uint32_t KEY_INDEX_SIZE, + uint32_t WRAPPED_KEY_SIZE); +rsip_ret_t r_rsip_wrapper_p8f_aes256(const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_WrappedKeyIndex[], + uint32_t OutData_Text[], + uint32_t KEY_INDEX_SIZE, + uint32_t WRAPPED_KEY_SIZE); +rsip_ret_t r_rsip_wrapper_p90_aes128(const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_Text[], + uint32_t OutData_KeyIndex[], + uint32_t WRAPPED_KEY_SIZE, + uint32_t KEY_INDEX_SIZE); +rsip_ret_t r_rsip_wrapper_p90_aes256(const uint32_t InData_KeyIndex[], + const uint32_t InData_WrappedKeyType[], + const uint32_t InData_Text[], + uint32_t OutData_KeyIndex[], + uint32_t WRAPPED_KEY_SIZE, + uint32_t KEY_INDEX_SIZE); + +/* AES-ECB/CBC/CTR */ +rsip_ret_t r_rsip_wrapper_p47i_ecb_enc(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p47i_ecb_dec(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p47i_cbc_enc(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p47i_cbc_dec(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p47i_cbc_enc_wrapped_iv(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p47i_cbc_dec_wrapped_iv(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p47i_ctr(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p50i_ecb_enc(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p50i_ecb_dec(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p50i_cbc_enc(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p50i_cbc_dec(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p50i_cbc_enc_wrapped_iv(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p50i_cbc_dec_wrapped_iv(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p50i_ctr(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p89i_ecb_enc(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p89i_ecb_dec(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p89i_cbc_enc(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p89i_cbc_dec(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p89i_cbc_enc_wrapped_iv(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p89i_cbc_dec_wrapped_iv(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +rsip_ret_t r_rsip_wrapper_p89i_ctr(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); + +/* AES-GCM */ +rsip_ret_t r_rsip_wrapper_p29i_plain_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p29i_wrapped_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p32i_plain_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p32i_wrapped_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p34i_plain_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p34i_wrapped_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p36i_plain_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p36i_wrapped_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p83i_plain_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p83i_wrapped_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p85i_plain_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); +rsip_ret_t r_rsip_wrapper_p85i_wrapped_iv(const uint32_t * InData_KeyIndex, const uint32_t * InData_IV); + +/* AES-CCM */ +rsip_ret_t r_rsip_wrapper_p95i_aes128ccm_encrypt(const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len); +rsip_ret_t r_rsip_wrapper_p95f_aes128ccm_encrypt(const uint32_t * InData_Text, + const uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); +rsip_ret_t r_rsip_wrapper_p98i_aes128ccm_decrypt(const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_MACLength, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len); +rsip_ret_t r_rsip_wrapper_p98f_aes128ccm_decrypt(const uint32_t * InData_Text, + const uint32_t * InData_TextLen, + const uint32_t * InData_MAC, + const uint32_t * InData_MACLength, + uint32_t * OutData_Text); +rsip_ret_t r_rsip_wrapper_pa7i_aes192ccm_encrypt(const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len); +rsip_ret_t r_rsip_wrapper_pa7f_aes192ccm_encrypt(const uint32_t * InData_Text, + const uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); +rsip_ret_t r_rsip_wrapper_pb0i_aes192ccm_decrypt(const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_MACLength, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len); +rsip_ret_t r_rsip_wrapper_pb0f_aes192ccm_decrypt(const uint32_t * InData_Text, + const uint32_t * InData_TextLen, + const uint32_t * InData_MAC, + const uint32_t * InData_MACLength, + uint32_t * OutData_Text); +rsip_ret_t r_rsip_wrapper_pa1i_aes256ccm_encrypt(const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len); +rsip_ret_t r_rsip_wrapper_pa4i_aes256ccm_decrypt(const uint32_t * InData_KeyIndex, + const uint32_t * InData_TextLen, + const uint32_t * InData_MACLength, + const uint32_t * InData_IV, + const uint32_t * InData_Header, + uint32_t Header_Len); + +/* AES-MAC */ +rsip_ret_t r_rsip_wrapper_p41f_aes128mac_generate(const uint32_t * InData_Text, + uint32_t * OutData_DataT, + const uint32_t all_msg_len); +rsip_ret_t r_rsip_wrapper_p41f_aes128mac_verify(const uint32_t * InData_Text, + const uint32_t * InData_DataT, + const uint32_t * InData_DataTLen, + const uint32_t all_msg_len); +rsip_ret_t r_rsip_wrapper_p87f_aes192mac_generate(const uint32_t * InData_Text, + uint32_t * OutData_DataT, + const uint32_t all_msg_len); +rsip_ret_t r_rsip_wrapper_p87f_aes192mac_verify(const uint32_t * InData_Text, + const uint32_t * InData_DataT, + const uint32_t * InData_DataTLen, + const uint32_t all_msg_len); +rsip_ret_t r_rsip_wrapper_p44f_aes256mac_generate(const uint32_t * InData_Text, + uint32_t * OutData_DataT, + const uint32_t all_msg_len); +rsip_ret_t r_rsip_wrapper_p44f_aes256mac_verify(const uint32_t * InData_Text, + const uint32_t * InData_DataT, + const uint32_t * InData_DataTLen, + const uint32_t all_msg_len); + +/* ChaCha20-Poly1305 */ +rsip_ret_t r_rsip_wrapper_p97i_enc(const uint32_t * InData_KeyIndex, + const uint32_t * InData_Nonce, + const uint32_t * InData_TextLen, + const uint32_t * InData_DataALen); +rsip_ret_t r_rsip_wrapper_p97i_dec(const uint32_t * InData_KeyIndex, + const uint32_t * InData_Nonce, + const uint32_t * InData_TextLen, + const uint32_t * InData_DataALen); +rsip_ret_t r_rsip_wrapper_p97r_enc(const uint32_t * InData_KeyIndex, + const uint32_t * InData_Nonce, + const uint32_t * InData_State); +rsip_ret_t r_rsip_wrapper_p97r_dec(const uint32_t * InData_KeyIndex, + const uint32_t * InData_Nonce, + const uint32_t * InData_State); + +/* ECDH */ +rsip_ret_t r_rsip_wrapper_pe2_wrapped_secp256r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_pe2_plain_secp256r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_pe2_wrapped_brainpoolp256r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_pe2_plain_brainpoolp256r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_p4e_wrapped_secp384r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_p4e_plain_secp384r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_p4e_wrapped_brainpoolp384r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_p4e_plain_brainpoolp384r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_p4f_wrapped_secp521r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_p4f_plain_secp521r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_p5e_wrapped_brainpoolp512r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +rsip_ret_t r_rsip_wrapper_p5e_plain_brainpoolp512r1(const uint32_t InData_PubKey[], + const uint32_t InData_KeyIndex[], + uint32_t OutData_EncSecret[]); + +/* PKI */ +rsip_ret_t r_rsip_wrapper_peei_secp256r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); + +rsip_ret_t r_rsip_wrapper_peei_brainpoolp256r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); + +rsip_ret_t r_rsip_wrapper_p51i_secp384r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); + +rsip_ret_t r_rsip_wrapper_p51i_brainpoolp384r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); + +rsip_ret_t r_rsip_wrapper_p52i_secp521r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); + +rsip_ret_t r_rsip_wrapper_p5fi_brainpoolp512r1(const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]); + +rsip_ret_t r_rsip_wrapper_pe1_secp256r1(const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]); + +rsip_ret_t r_rsip_wrapper_pe1_brainpoolp256r1(const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]); + +rsip_ret_t r_rsip_wrapper_pe1_secp384r1(const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]); + +rsip_ret_t r_rsip_wrapper_pe1_brainpoolp384r1(const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]); + +rsip_ret_t r_rsip_wrapper_pe1_secp521r1(const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]); + +rsip_ret_t r_rsip_wrapper_pe1_brainpoolp512r1(const uint32_t InData_HashType[], + const uint32_t InData_Certificate[], + const uint32_t InData_CertificateLength[], + const uint32_t InData_CertificatePubKey[], + const uint32_t InData_EncCertificateInfo[], + uint32_t OutData_KeyIndex[]); + +/* KDF */ +rsip_ret_t r_rsip_wrapper_pe3_sha256(const uint32_t InData_EncSecret[], uint32_t OutData_EncMsg[]); +rsip_ret_t r_rsip_wrapper_pe3_sha384(const uint32_t InData_EncSecret[], uint32_t OutData_EncMsg[]); +rsip_ret_t r_rsip_wrapper_pe3_sha512_secp521r1(const uint32_t InData_EncSecret[], uint32_t OutData_EncMsg[]); +rsip_ret_t r_rsip_wrapper_pe3_sha512_brainpoolp512r1(const uint32_t InData_EncSecret[], uint32_t OutData_EncMsg[]); +rsip_ret_t r_rsip_wrapper_pe4_sha256(const uint32_t InData_EncSecret[], uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe4_sha384(const uint32_t InData_EncSecret[], uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe4_sha512_secp521r1(const uint32_t InData_EncSecret[], uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe4_sha512_brainpoolp512r1(const uint32_t InData_EncSecret[], uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe6_sha256(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe6_sha384(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe6_sha512(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLength[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha256_aes128(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha256_aes256(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha256_hmac_sha256(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha256_hmac_sha384(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha256_hmac_sha512(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha256_iv_aes(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_EncIV[]); +rsip_ret_t r_rsip_wrapper_pe7_sha384_aes128(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha384_aes256(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha384_hmac_sha256(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha384_hmac_sha384(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha384_hmac_sha512(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha384_iv_aes(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_EncIV[]); +rsip_ret_t r_rsip_wrapper_pe7_sha512_aes128(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha512_aes256(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_KeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha512_hmac_sha256(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha512_hmac_sha384(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha512_hmac_sha512(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + uint32_t OutData_HMACKeyIndex[]); +rsip_ret_t r_rsip_wrapper_pe7_sha512_iv_aes(const uint32_t InData_KDFInfo[], + const uint32_t InData_KDFInfo_Count[], + const uint32_t InData_OutDataLocation[], + const uint32_t InData_SeqNum[], + uint32_t OutData_EncIV[]); +rsip_ret_t r_rsip_wrapper_p2c_ch0(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); +rsip_ret_t r_rsip_wrapper_p2d_ch0(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); +rsip_ret_t r_rsip_wrapper_p2e_ch0(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); +rsip_ret_t r_rsip_wrapper_p2c_ch1(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); +rsip_ret_t r_rsip_wrapper_p2d_ch1(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); +rsip_ret_t r_rsip_wrapper_p2e_ch1(const uint32_t InData_KeyIndex[], const uint32_t InData_DOTFSEED[]); + +#endif /* R_RSIP_WRAPPER_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/public/r_rsip_ra.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/public/r_rsip_ra.c new file mode 100644 index 0000000000..eb80ce4be7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rsip_protected/crypto_procedures_protected/src/rsip/ra/public/r_rsip_ra.c @@ -0,0 +1,264 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rsip_public.h" +#include "r_rsip_primitive.h" +#include "r_rsip_wrapper.h" +#if RSIP_CFG_FW_UPDATE_ENABLE + #include "r_sb_api.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup RSIP_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Verifies a Manifest signature and outputs the MAC of image and code certificate. + * The hash algorithm only supports HMAC-SHA256. + * The signature algorithm only supports ECDSA secp256r1. + * + * @par State transition + * This API can only be executed in **STATE_MAIN**, and does not cause any state transitions. + * + * @note If this API returns FSP_ERR_SB_LOWER_IMAGE_VERSION or FSP_ERR_SB_CRYPTO_AUTH_FAIL, RSIP stops working. + * In this case, RSIP can be resumed by executing R_RSIP_Close() and R_RSIP_Open() in that order. + * + * @param[in,out] p_ctrl Pointer to control block. + * @param[in] p_key_cert Pointer to key certificate. + * @param[in] key_cert_max_length Maximum length of key certificate. + * @param[in] p_code_cert Pointer to key code certificate. + * @param[in] code_cert_max_length Maximum length of code certificate. + * @param[out] p_mac Pointer to output MAC. + * It is output in TLV format and consists of a 4-byte Type-Length and a 32-byte Value. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Internal state is illegal. + * + * @retval FSP_ERR_SB_INTERNAL_FAIL An internal failure. + * @retval FSP_ERR_SB_INVALID_ARG An invalid argument was entered. + * @retval FSP_ERR_SB_UNSUPPORTED_FUNCTION Unsupported function executed. + * @retval FSP_ERR_SB_INVALID_ALIGNMENT Data entered with incorrect alignment. + * @retval FSP_ERR_SB_SAME_IMAGE_VERSION An image of the same version as the current version is input. + * (verification completed successfully) + * @retval FSP_ERR_SB_LOWER_IMAGE_VERSION Image version lower than the current image version is installed. + * @retval FSP_ERR_SB_MANI_INVALID_MAGIC An invalid magic number is set. + * @retval FSP_ERR_SB_MANI_UNSUPPORTED_VERSION Unsupported version is set. + * @retval FSP_ERR_SB_MANI_OUT_OF_RANGE_LEN Out of range TLV Length is set. + * @retval FSP_ERR_SB_MANI_TLV_FIELD_ERR Missing required TLV field. + * @retval FSP_ERR_SB_MANI_TLV_INVALID_LEN The length exceeding the end of the manifest is specified + * in length of the TLV field. + * @retval FSP_ERR_SB_MANI_INVALID_IMAGE_LEN An invalid image length is set. + * @retval FSP_ERR_SB_MANI_MISMATCH_SIGN_ALGORITHM There is a wrong combination of signature algorithms. + * @retval FSP_ERR_SB_MANI_UNSUPPORTED_ALGORITHM An algorithm was specified that the manifest does not support. + * @retval FSP_ERR_SB_CRYPTO_FAIL Cryptographic processing failure. + * @retval FSP_ERR_SB_CRYPTO_AUTH_FAIL Verification failed. + * @retval FSP_ERR_SB_CRYPTO_PARAM_ERR Parameter error. + * @retval FSP_ERR_SB_CRYPTO_RESOURCE_CONFLICT CryptoIP is in use. + * @retval FSP_ERR_UNSUPPORTED This API is not supported on this device. + **********************************************************************************************************************/ +fsp_err_t R_RSIP_FSBL_OEM_BL_Digest_Generate (rsip_ctrl_t * const p_ctrl, + uint8_t const * const p_key_cert, + uint32_t const key_cert_max_length, + uint8_t const * const p_code_cert, + uint32_t const code_cert_max_length, + uint32_t * const p_mac) +{ + fsp_err_t err = FSP_ERR_CRYPTO_RSIP_FATAL; + +#if RSIP_CFG_FW_UPDATE_ENABLE + rsip_instance_ctrl_t * p_instance_ctrl = (rsip_instance_ctrl_t *) p_ctrl; + + #if RSIP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_mac); + FSP_ERROR_RETURN(RSIP_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + /* Check state */ + FSP_ERROR_RETURN(RSIP_STATE_MAIN == p_instance_ctrl->state, FSP_ERR_INVALID_STATE); + + /* Call SB-Lib function */ + sb_ret_t sb_ret = R_SB_CheckIntegrity(p_key_cert, + key_cert_max_length, + p_code_cert, + code_cert_max_length, + SB_MAC_TYPE_HMAC_SHA2_256, + p_mac); + + /* Check error */ + switch (sb_ret) + { + case SB_RET_SUCCESS: + { + err = FSP_SUCCESS; + break; + } + + case SB_RET_ERR_INTERNAL_FAIL: + { + err = (fsp_err_t) FSP_ERR_SB_INTERNAL_FAIL; + break; + } + + case SB_RET_ERR_INVALID_ARG: + { + err = (fsp_err_t) FSP_ERR_SB_INVALID_ARG; + break; + } + + case SB_RET_ERR_UNSUPPORTED_FUNCTION: + { + err = (fsp_err_t) FSP_ERR_SB_UNSUPPORTED_FUNCTION; + break; + } + + case SB_RET_ERR_INVALID_ALIGNMENT: + { + err = (fsp_err_t) FSP_ERR_SB_INVALID_ALIGNMENT; + break; + } + + case SB_RET_SAME_IMAGE_VERSION: + { + err = (fsp_err_t) FSP_ERR_SB_SAME_IMAGE_VERSION; + break; + } + + case SB_RET_ERR_LOWER_IMAGE_VERSION: + { + err = (fsp_err_t) FSP_ERR_SB_LOWER_IMAGE_VERSION; + break; + } + + case SB_RET_ERR_MANI_INVALID_MAGIC: + { + err = (fsp_err_t) FSP_ERR_SB_MANI_INVALID_MAGIC; + break; + } + + case SB_RET_ERR_MANI_UNSUPPORTED_VERSION: + { + err = (fsp_err_t) FSP_ERR_SB_MANI_UNSUPPORTED_VERSION; + break; + } + + case SB_RET_ERR_MANI_OUT_OF_RANGE_LEN: + { + err = (fsp_err_t) FSP_ERR_SB_MANI_OUT_OF_RANGE_LEN; + break; + } + + case SB_RET_ERR_MANI_TLV_FIELD_ERR: + { + err = (fsp_err_t) FSP_ERR_SB_MANI_TLV_FIELD_ERR; + break; + } + + case SB_RET_ERR_MANI_TLV_INVALID_LEN: + { + err = (fsp_err_t) FSP_ERR_SB_MANI_TLV_INVALID_LEN; + break; + } + + case SB_RET_ERR_MANI_INVALID_IMAGE_LEN: + { + err = (fsp_err_t) FSP_ERR_SB_MANI_INVALID_IMAGE_LEN; + break; + } + + case SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM: + { + err = (fsp_err_t) FSP_ERR_SB_MANI_MISMATCH_SIGN_ALGORITHM; + break; + } + + case SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM: + { + err = (fsp_err_t) FSP_ERR_SB_MANI_UNSUPPORTED_ALGORITHM; + break; + } + + case SB_RET_ERR_CRYPTO_FAIL: + { + err = (fsp_err_t) FSP_ERR_SB_CRYPTO_FAIL; + break; + } + + case SB_RET_ERR_CRYPTO_AUTH_FAIL: + { + err = (fsp_err_t) FSP_ERR_SB_CRYPTO_AUTH_FAIL; + break; + } + + case SB_RET_ERR_CRYPTO_PARAM_ERR: + { + err = (fsp_err_t) FSP_ERR_SB_CRYPTO_PARAM_ERR; + break; + } + + case SB_RET_ERR_CRYPTO_RESOURCE_CONFLICT: + { + err = (fsp_err_t) FSP_ERR_SB_CRYPTO_RESOURCE_CONFLICT; + break; + } + + default: + { + err = (fsp_err_t) FSP_ERR_SB_INTERNAL_FAIL; + } + } + +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_key_cert); + FSP_PARAMETER_NOT_USED(key_cert_max_length); + FSP_PARAMETER_NOT_USED(p_code_cert); + FSP_PARAMETER_NOT_USED(code_cert_max_length); + FSP_PARAMETER_NOT_USED(p_mac); + + err = FSP_ERR_UNSUPPORTED; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup RSIP_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rtc/r_rtc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rtc/r_rtc.c new file mode 100644 index 0000000000..a3ebaa8e7f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_rtc/r_rtc.c @@ -0,0 +1,1729 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_rtc.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define RTC_MASK_MSB (0x0F) +#define RTC_MASK_LSB (0xF0) + +#define RTC_FIRST_DAY_OF_A_MONTH (1) + +/* Day of week : valid range between 0 to 6. */ +#define RTC_DAYS_IN_A_WEEK (6) + +/* Month : valid range between 0 to 11.*/ +#define RTC_MONTHS_IN_A_YEAR (11) +#define RTC_LAST_DAY_OF_LEAP_FEB_MONTH (29) +#define RTC_LAST_DAY_OF_A_MONTH (31) +#define RTC_YEAR_VALUE_MIN (100) +#define RTC_YEAR_VALUE_MAX (199) + +/* Seconds : valid range between 0 to 59.*/ +#define RTC_SECONDS_IN_A_MINUTE (59) + +/* Minute : valid range between 0 to 59. */ +#define RTC_MINUTES_IN_A_HOUR (59) + +/* Hours : valid range between 0 to 23. */ +#define RTC_HOURS_IN_A_DAY (23) + +/* In Zeller algorithm value of (-[Y/100] + [Y/400]) is 15 for Y = 2000 to Y = 2099) */ +#define RTC_ZELLER_ALGM_CONST_FIFTEEN (15) + +/* Macro definitions for February and March months */ +#define RTC_FEBRUARY_MONTH (2U) +#define RTC_MARCH_MONTH (3U) + +#define RTC_TIME_H_MONTH_OFFSET (1) + +/*The RTC has a 100 year calendar to match the starting year 2000, year offset(1900) is added like 117 + 1900 = 2017 */ +#define RTC_TIME_H_YEAR_OFFSET (1900) + +/** "RTC" in ASCII, used to determine if device is open. */ +#define RTC_OPEN (0x00525443ULL) + +#if BSP_FEATURE_RTC_HAS_RADJ_ADJ6 + #define RTC_MAX_ERROR_ADJUSTMENT_VALUE (0x7FU) + #define RTC_MAX_ADJ_VALUE (0x3FU) + #define RTC_ADJ6_ADJUSTMENT_VALUE (0x40U) +#else + #define RTC_MAX_ERROR_ADJUSTMENT_VALUE (0x3FU) +#endif + +#define RTC_RHRCNT_HOUR_MASK (0x3f) +#define RTC_COMPARE_ENB_BIT (7U) +#define RTC_MASK_8TH_BIT (0x7F) + +/* As per HW manual, value of Year is between 0 to 99, the RTC has a 100 year calendar from 2000 to 2099. + * But as per C standards, tm_year is years since 1900.*/ +#define RTC_C_TIME_OFFSET (100) + +/* See "Frequency Register (RFRH/RFRL)" description in the RTC section of the relevant hardware manual. */ +#define RTC_RFRL_MIN_VALUE_LOCO (0x7U) +#define RTC_RFRL_MAX_VALUE_LOCO (0x1FFU) + +#define RTC_ALARM_REG_SIZE (0x20) + +#define BSP_DELAY_US_PER_SECOND (1000000) +#define NOISE_FILTER_SET_NUMBER_DELAY (3) +#define NOISE_FILTER_CLOCK_DIVIDE_1 (1) +#define NOISE_FILTER_CLOCK_DIVIDE_32 (32) +#define NOISE_FILTER_CLOCK_DIVIDE_4096 (4096) +#define NOISE_FILTER_CLOCK_DIVIDE_8192 (8192) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * rtc_prv_ns_callback)(rtc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile rtc_prv_ns_callback)(rtc_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static uint8_t rtc_dec_to_bcd(uint8_t to_convert); +static uint8_t rtc_bcd_to_dec(uint8_t to_convert); +void rtc_alarm_periodic_isr(void); +void rtc_carry_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** RTC Implementation of Real Time Clock */ +const rtc_api_t g_rtc_on_rtc = +{ + .open = R_RTC_Open, + .close = R_RTC_Close, + .clockSourceSet = R_RTC_ClockSourceSet, + .calendarTimeGet = R_RTC_CalendarTimeGet, + .calendarTimeSet = R_RTC_CalendarTimeSet, + .calendarAlarmGet = R_RTC_CalendarAlarmGet, + .calendarAlarmSet = R_RTC_CalendarAlarmSet, + .periodicIrqRateSet = R_RTC_PeriodicIrqRateSet, + .infoGet = R_RTC_InfoGet, + .errorAdjustmentSet = R_RTC_ErrorAdjustmentSet, + .callbackSet = R_RTC_CallbackSet, + .timeCaptureSet = R_RTC_TimeCaptureSet, + .timeCaptureGet = R_RTC_TimeCaptureGet, +}; + +#if RTC_CFG_PARAM_CHECKING_ENABLE + +/* Number of days in each months start from January to December */ +static const uint8_t days_in_months[12] = {31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; +#endif + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +static void r_rtc_set_clock_source(rtc_instance_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); + +static void r_rtc_start_bit_update(uint8_t value); + +static void r_rtc_software_reset(void); + +static void r_rtc_config_rtc_interrupts(rtc_instance_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); + +static void r_rtc_irq_set(bool irq_enable_flag, uint8_t mask); + +static void r_rtc_call_callback(rtc_instance_ctrl_t * p_ctrl, rtc_event_t event); + +#if RTC_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_rtc_rfrl_validate(uint32_t value); + +static fsp_err_t r_rtc_err_adjustment_parameter_check(rtc_error_adjustment_cfg_t const * const err_adj_cfg); + +static fsp_err_t r_rtc_time_and_date_validate(rtc_time_t * const p_time); + +static fsp_err_t r_rtc_time_validate(rtc_time_t * const p_time); + +static fsp_err_t r_rtc_date_validate(rtc_time_t * const p_time); + +static fsp_err_t r_rtc_alarm_time_and_date_validate(rtc_alarm_time_t * const p_time); + +static fsp_err_t r_rtc_alarm_time_validate(rtc_alarm_time_t * const p_time); + +static fsp_err_t r_rtc_alarm_month_and_year_validate(rtc_alarm_time_t * const p_time); + +static fsp_err_t r_rtc_alarm_dayofmonth_and_dayofweek_validate(rtc_alarm_time_t * const p_time); + +#endif + +static void r_rtc_error_adjustment_set(rtc_error_adjustment_cfg_t const * const err_adj_cfg); + +/*******************************************************************************************************************//** + * @addtogroup RTC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens and configures the RTC driver module. Implements @ref rtc_api_t::open. + * Configuration includes clock source, and interrupt callback function. + * + * Example: + * @snippet r_rtc_example.c R_RTC_Open + * + * @retval FSP_SUCCESS Initialization was successful and RTC has started. + * @retval FSP_ERR_ASSERTION Invalid p_ctrl or p_cfg pointer. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid time parameter field. + **********************************************************************************************************************/ +fsp_err_t R_RTC_Open (rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + + /* Parameter checking */ +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN(RTC_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Save the configuration */ + p_instance_ctrl->p_cfg = p_cfg; + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + +#if RTC_CFG_PARAM_CHECKING_ENABLE + + /* IRTC only use Subclock */ + #if BSP_FEATURE_RTC_IS_IRTC + FSP_ERROR_RETURN(RTC_CLOCK_SOURCE_SUBCLK == p_cfg->clock_source, FSP_ERR_INVALID_ARGUMENT); + #endif + + /* Verify the frequency comparison value for RFRL when using LOCO */ + if (RTC_CLOCK_SOURCE_LOCO == p_cfg->clock_source) + { + FSP_ERROR_RETURN(FSP_SUCCESS == r_rtc_rfrl_validate(p_cfg->freq_compare_value), FSP_ERR_INVALID_ARGUMENT); + } + /* Validate the error adjustment parameters when using SubClock */ + else + { + FSP_ERROR_RETURN(FSP_SUCCESS == r_rtc_err_adjustment_parameter_check(p_instance_ctrl->p_cfg->p_err_cfg), + FSP_ERR_INVALID_ARGUMENT); + } +#endif + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable the RTC Register Read/Write clock if it was disabled in startup. */ + bsp_prv_rtc_register_clock_set(true); +#endif + + p_instance_ctrl->carry_isr_triggered = false; + +#if RTC_CFG_OPEN_SET_CLOCK_SOURCE + + /* Set the clock source for RTC. + * The count source must be selected only once before making the initial settings of the RTC registers + * at power on. (see "RTC Control Register 4 (RCR4)" description in the relevant hardware manual)*/ + r_rtc_set_clock_source(p_instance_ctrl, p_cfg); +#endif + + r_rtc_config_rtc_interrupts(p_instance_ctrl, p_cfg); + + /** Mark driver as open by initializing it to "RTC" in its ASCII equivalent. */ + p_instance_ctrl->open = RTC_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Close the RTC driver. + * Implements @ref rtc_api_t::close + * + * @retval FSP_SUCCESS De-Initialization was successful and RTC driver closed. + * @retval FSP_ERR_ASSERTION Invalid p_ctrl. + * @retval FSP_ERR_NOT_OPEN Driver not open already for close. + **********************************************************************************************************************/ +fsp_err_t R_RTC_Close (rtc_ctrl_t * const p_ctrl) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear PIE, AIE, CIE*/ + R_RTC->RCR1 = 0U; + + /* When the RCR1 register is modified, check that all the bits are updated before proceeding + * (see "RTC Control Register 1 (RCR1)" description in the relevant hardware manual.)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR1, 0); + + /* Set the START bit to 0 */ + r_rtc_start_bit_update(0U); + + if (p_instance_ctrl->p_cfg->periodic_irq >= 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->periodic_irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->periodic_irq, NULL); + } + + if (p_instance_ctrl->p_cfg->alarm_irq >= 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->alarm_irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->alarm_irq, NULL); + } + +#if BSP_FEATURE_RTC_HAS_ALARM1 + if (((rtc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->alarm1_irq >= 0) + { + R_BSP_IrqDisable(((rtc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->alarm1_irq); + R_FSP_IsrContextSet(((rtc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->alarm1_irq, NULL); + } +#endif + if (p_instance_ctrl->p_cfg->carry_irq >= 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->carry_irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->carry_irq, NULL); + } + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Disable the RTC Register Read/Write clock. */ + bsp_prv_rtc_register_clock_set(false); +#endif + + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the RTC clock source. Implements @ref rtc_api_t::clockSourceSet. + * + * Example: + * @snippet r_rtc_example.c R_RTC_ClockSourceSet + * + * @retval FSP_SUCCESS Initialization was successful and RTC has started. + * @retval FSP_ERR_ASSERTION Invalid p_ctrl or p_cfg pointer. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid clock source. + **********************************************************************************************************************/ +fsp_err_t R_RTC_ClockSourceSet (rtc_ctrl_t * const p_ctrl) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + + /* Parameter checking */ +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #if BSP_FEATURE_RTC_IS_IRTC + FSP_ERROR_RETURN(RTC_CLOCK_SOURCE_SUBCLK == p_instance_ctrl->p_cfg->clock_source, FSP_ERR_INVALID_ARGUMENT); + #endif +#endif + + /* Set the clock source for RTC. + * The count source must be selected only once before making the initial settings of the RTC registers + * at power on. (see "RTC Control Register 4 (RCR4)" description in the relevant hardware manual)*/ + r_rtc_set_clock_source(p_instance_ctrl, p_instance_ctrl->p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the calendar time. + * + * Implements @ref rtc_api_t::calendarTimeSet. + * + * @retval FSP_SUCCESS Calendar time set operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid time parameter field. + **********************************************************************************************************************/ +fsp_err_t R_RTC_CalendarTimeSet (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time) +{ + fsp_err_t err = FSP_SUCCESS; + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(p_time); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify the seconds, minutes, hours, year ,day of the week, day of the month, month and year are valid values */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_rtc_time_and_date_validate(p_time), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* See "Setting the Time" in the RTC section of the relevant hardware manual for steps to set the time and error + * adjustment value */ + + /* Set the START bit to 0 */ + r_rtc_start_bit_update(0U); + + /* Set the year, month, day of the week, ... */ + R_RTC->RSECCNT = rtc_dec_to_bcd((uint8_t) p_time->tm_sec); + R_RTC->RMINCNT = rtc_dec_to_bcd((uint8_t) p_time->tm_min); + R_RTC->RHRCNT = rtc_dec_to_bcd((uint8_t) p_time->tm_hour) & RTC_RHRCNT_HOUR_MASK; + R_RTC->RWKCNT = rtc_dec_to_bcd((uint8_t) p_time->tm_wday); + R_RTC->RDAYCNT = rtc_dec_to_bcd((uint8_t) p_time->tm_mday); + + /* Add one to match with HW register */ + R_RTC->RMONCNT = rtc_dec_to_bcd((uint8_t) (p_time->tm_mon + 1)); + + /* Subtract 100 to match with HW register */ + R_RTC->RYRCNT = rtc_dec_to_bcd((uint8_t) (p_time->tm_year - RTC_C_TIME_OFFSET)); + + if (RTC_CLOCK_SOURCE_SUBCLK == p_instance_ctrl->p_cfg->clock_source) + { + /* Set Error Adjustment values */ + r_rtc_error_adjustment_set(p_instance_ctrl->p_cfg->p_err_cfg); + } + + /* Set the START bit to 1 */ + r_rtc_start_bit_update(1U); + + return err; +} + +/*******************************************************************************************************************//** + * Get the calendar time. + * @warning Do not call this function from a critical section or from an interrupt with higher priority than the carry + * interrupt, or the time returned may be inaccurate. + * + * Implements @ref rtc_api_t::calendarTimeGet + * + * @retval FSP_SUCCESS Calendar time get operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + * @retval FSP_ERR_IRQ_BSP_DISABLED User IRQ parameter not valid + **********************************************************************************************************************/ +fsp_err_t R_RTC_CalendarTimeGet (rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(p_time); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_instance_ctrl->p_cfg->carry_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + fsp_err_t err = FSP_SUCCESS; + + uint32_t carry_irq_status = NVIC_GetEnableIRQ(p_instance_ctrl->p_cfg->carry_irq); + + if ((uint32_t) 0U == carry_irq_status) + { + r_rtc_irq_set(true, R_RTC_RCR1_CIE_Msk); + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->carry_irq); + } + + /* If a carry occurs while the 64-Hz counter and time are being read, the correct time is not obtained, + * therefore they must be read again. "Reading 64-Hz Counter and Time" in the RTC section of the relevant + * hardware manual.*/ + do + { + p_instance_ctrl->carry_isr_triggered = false; /** This flag will be set to 'true' in the carry ISR */ + p_time->tm_sec = (int32_t) rtc_bcd_to_dec(R_RTC->RSECCNT); + p_time->tm_min = (int32_t) rtc_bcd_to_dec(R_RTC->RMINCNT); + p_time->tm_hour = (int32_t) rtc_bcd_to_dec(R_RTC->RHRCNT & RTC_RHRCNT_HOUR_MASK); + p_time->tm_wday = (int32_t) rtc_bcd_to_dec(R_RTC->RWKCNT); + p_time->tm_mday = (int32_t) rtc_bcd_to_dec(R_RTC->RDAYCNT); + + /* Subtract one to match with C time.h standards */ + p_time->tm_mon = (int32_t) rtc_bcd_to_dec(R_RTC->RMONCNT) - 1; + + /* Add 100 to match with C time.h standards */ + p_time->tm_year = (int32_t) rtc_bcd_to_dec((uint8_t) R_RTC->RYRCNT) + RTC_C_TIME_OFFSET; + } while (p_instance_ctrl->carry_isr_triggered); + + /** Restore the state of carry IRQ. */ + if ((uint32_t) 0U == carry_irq_status) + { + r_rtc_irq_set(false, R_RTC_RCR1_CIE_Msk); + + /* Disable this interrupt in the NVIC */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->carry_irq); + } + + return err; +} + +/*******************************************************************************************************************//** + * Set the calendar alarm time. + * + * Implements @ref rtc_api_t::calendarAlarmSet. + * + * @pre The calendar counter must be running before the alarm can be set. + * + * @retval FSP_SUCCESS Calendar alarm time set operation was successful. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid time parameter field. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + * @retval FSP_ERR_IRQ_BSP_DISABLED User IRQ parameter not valid + **********************************************************************************************************************/ +fsp_err_t R_RTC_CalendarAlarmSet (rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_alarm); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #if BSP_FEATURE_RTC_HAS_ALARM1 + FSP_ERROR_RETURN((p_alarm->channel == RTC_ALARM_CHANNEL_0 && p_instance_ctrl->p_cfg->alarm_irq >= 0) || + (p_alarm->channel == RTC_ALARM_CHANNEL_1 && + ((rtc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->alarm1_irq >= 0), + FSP_ERR_IRQ_BSP_DISABLED); + #else + FSP_ERROR_RETURN(p_instance_ctrl->p_cfg->alarm_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + #endif + + /* Verify the seconds, minutes, hours, year ,day of the week, day of the month and month are valid values */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_rtc_alarm_time_and_date_validate(p_alarm), FSP_ERR_INVALID_ARGUMENT); +#endif + + volatile uint8_t * p_reg; + volatile uint16_t * p_reg_ryrar; + + IRQn_Type alarm_irq = p_instance_ctrl->p_cfg->alarm_irq; + rtc_alarm_channel_t alarm_channel = RTC_ALARM_CHANNEL_0; + +#if BSP_FEATURE_RTC_HAS_ALARM1 + alarm_channel = p_alarm->channel; + if (RTC_ALARM_CHANNEL_1 == alarm_channel) + { + alarm_irq = ((rtc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->alarm1_irq; + } +#endif + + /* Disable the ICU alarm interrupt request */ + R_BSP_IrqDisable(alarm_irq); + + /* Set alarm time */ + volatile uint8_t field; + if (p_alarm->sec_match) + { + field = rtc_dec_to_bcd((uint8_t) p_alarm->time.tm_sec) | (uint8_t) (p_alarm->sec_match << RTC_COMPARE_ENB_BIT); + } + else + { + field = 0U; + } + + p_reg = &R_RTC->RSECAR + (RTC_ALARM_REG_SIZE * alarm_channel); + *p_reg = field; + + if (p_alarm->min_match) + { + field = rtc_dec_to_bcd((uint8_t) p_alarm->time.tm_min) | (uint8_t) (p_alarm->min_match << RTC_COMPARE_ENB_BIT); + } + else + { + field = 0U; + } + + p_reg = &R_RTC->RMINAR + (RTC_ALARM_REG_SIZE * alarm_channel); + (*p_reg) = field; + + if (p_alarm->hour_match) + { + field = rtc_dec_to_bcd((uint8_t) p_alarm->time.tm_hour) | + (uint8_t) (p_alarm->hour_match << RTC_COMPARE_ENB_BIT); + } + else + { + field = 0U; + } + + p_reg = &R_RTC->RHRAR + (RTC_ALARM_REG_SIZE * alarm_channel); + (*p_reg) = field; + + if (p_alarm->dayofweek_match) + { + field = (uint8_t) p_alarm->time.tm_wday | (uint8_t) (p_alarm->dayofweek_match << RTC_COMPARE_ENB_BIT); + } + else + { + field = 0U; + } + + p_reg = &R_RTC->RWKAR + (RTC_ALARM_REG_SIZE * alarm_channel); + (*p_reg) = field; + + if (p_alarm->mday_match) + { + field = rtc_dec_to_bcd((uint8_t) p_alarm->time.tm_mday) | + (uint8_t) (p_alarm->mday_match << RTC_COMPARE_ENB_BIT); + } + else + { + field = 1U; + } + + p_reg = &R_RTC->RDAYAR + (RTC_ALARM_REG_SIZE * alarm_channel); + (*p_reg) = field; + + if (p_alarm->mon_match) + { + /* Add one to month to match with HW register */ + field = rtc_dec_to_bcd((uint8_t) (p_alarm->time.tm_mon + 1)) | + (uint8_t) (p_alarm->mon_match << RTC_COMPARE_ENB_BIT); + } + else + { + field = 0U; + } + + p_reg = &R_RTC->RMONAR + (RTC_ALARM_REG_SIZE * alarm_channel); + (*p_reg) = field; + + if (p_alarm->year_match) + { + field = rtc_dec_to_bcd((uint8_t) (p_alarm->time.tm_year - RTC_C_TIME_OFFSET)); + } + else + { + field = 0U; + } + + /*It is a pointer to uint16_t so the offset needs to be halved */ + p_reg_ryrar = &R_RTC->RYRAR + (RTC_ALARM_REG_SIZE * alarm_channel) / 2; + (*p_reg_ryrar) = field; + + p_reg = &R_RTC->RYRAREN + (RTC_ALARM_REG_SIZE * alarm_channel); + (*p_reg) = (uint8_t) (p_alarm->year_match << R_RTC_RYRAREN_ENB_Pos); + + /* Enable the alarm interrupt */ + r_rtc_irq_set(true, R_RTC_RCR1_AIE_Msk); + + R_BSP_IrqEnable(alarm_irq); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get the calendar alarm time. + * + * Implements @ref rtc_api_t::calendarAlarmGet + * + * @retval FSP_SUCCESS Calendar alarm time get operation was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_CalendarAlarmGet (rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm) +{ +#if RTC_CFG_PARAM_CHECKING_ENABLE + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_alarm); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + volatile uint8_t * p_reg; + volatile uint16_t * p_reg_ryrar; + uint8_t reg_val; + uint16_t reg_ryrar_val; + + rtc_alarm_channel_t alarm_channel = RTC_ALARM_CHANNEL_0; + +#if BSP_FEATURE_RTC_HAS_ALARM1 + alarm_channel = p_alarm->channel; +#endif + + p_reg = &R_RTC->RSECAR + (RTC_ALARM_REG_SIZE * alarm_channel); + reg_val = *p_reg; + p_alarm->time.tm_sec = rtc_bcd_to_dec(reg_val & RTC_MASK_8TH_BIT); + p_alarm->sec_match = (bool) (reg_val & R_RTC_RSECAR_ENB_Msk); + + p_reg = &R_RTC->RMINAR + (RTC_ALARM_REG_SIZE * alarm_channel); + reg_val = *p_reg; + p_alarm->time.tm_min = rtc_bcd_to_dec(reg_val & RTC_MASK_8TH_BIT); + p_alarm->min_match = (bool) (reg_val & R_RTC_RMINAR_ENB_Msk); + + p_reg = &R_RTC->RHRAR + (RTC_ALARM_REG_SIZE * alarm_channel); + reg_val = *p_reg; + p_alarm->time.tm_hour = rtc_bcd_to_dec(reg_val & RTC_MASK_8TH_BIT); + p_alarm->hour_match = (bool) (reg_val & R_RTC_RHRAR_ENB_Msk); + + p_reg = &R_RTC->RWKAR + (RTC_ALARM_REG_SIZE * alarm_channel); + reg_val = *p_reg; + p_alarm->time.tm_wday = rtc_bcd_to_dec(reg_val & RTC_MASK_8TH_BIT); + p_alarm->dayofweek_match = (bool) (reg_val & R_RTC_RWKAR_ENB_Msk); + + p_reg = &R_RTC->RDAYAR + (RTC_ALARM_REG_SIZE * alarm_channel); + reg_val = *p_reg; + p_alarm->time.tm_mday = rtc_bcd_to_dec(reg_val & RTC_MASK_8TH_BIT); + p_alarm->mday_match = (bool) (reg_val & R_RTC_RDAYAR_ENB_Msk); + + /* Subtract one from month to match with C time.h standards */ + p_reg = &R_RTC->RMONAR + (RTC_ALARM_REG_SIZE * alarm_channel); + reg_val = *p_reg; + p_alarm->time.tm_mon = rtc_bcd_to_dec(reg_val & RTC_MASK_8TH_BIT) - (uint8_t) 1; + p_alarm->mon_match = (bool) (reg_val & R_RTC_RMONAR_ENB_Msk); + + /*It is a pointer to uint16_t so the offset needs to be halved */ + p_reg_ryrar = &R_RTC->RYRAR + (RTC_ALARM_REG_SIZE * alarm_channel) / 2; + reg_ryrar_val = *p_reg_ryrar; + + /* Add 100 to the year to match with C time.h standards */ + p_alarm->time.tm_year = rtc_bcd_to_dec((uint8_t) reg_ryrar_val) + (uint8_t) RTC_C_TIME_OFFSET; + + p_reg = &R_RTC->RYRAREN + (RTC_ALARM_REG_SIZE * alarm_channel); + reg_val = *p_reg; + p_alarm->year_match = (bool) (reg_val & R_RTC_RYRAREN_ENB_Msk); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the periodic interrupt rate and enable periodic interrupt. + * + * Implements @ref rtc_api_t::periodicIrqRateSet + * + * @note To start the RTC @ref R_RTC_CalendarTimeSet must be called at least once. + * + * Example: + * @snippet r_rtc_example.c R_RTC_PeriodicIrqRateSet + * + * @retval FSP_SUCCESS The periodic interrupt rate was successfully set. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + * @retval FSP_ERR_IRQ_BSP_DISABLED User IRQ parameter not valid + **********************************************************************************************************************/ +fsp_err_t R_RTC_PeriodicIrqRateSet (rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_select_t const rate) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(p_instance_ctrl->p_cfg->periodic_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); +#endif + fsp_err_t err = FSP_SUCCESS; + + uint8_t rcr1 = R_RTC->RCR1; + rcr1 &= (uint8_t) ~R_RTC_RCR1_PES_Msk; + R_RTC->RCR1 = (uint8_t) (rcr1 | (rate << R_RTC_RCR1_PES_Pos)); + + /* When the RCR1 register is modified, check that all the bits are updated before proceeding + * (see "RTC Control Register 1 (RCR1)" description in the relevant hardware manual)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR1 >> R_RTC_RCR1_PES_Pos, rate); + + r_rtc_irq_set(true, R_RTC_RCR1_PIE_Msk); + + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->periodic_irq); + + return err; +} + +/*******************************************************************************************************************//** + * Set RTC clock source and running status information ad store it in provided pointer p_rtc_info + * + * Implements @ref rtc_api_t::infoGet + * + * @retval FSP_SUCCESS Get information Successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + **********************************************************************************************************************/ +fsp_err_t R_RTC_InfoGet (rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_rtc_info); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_rtc_info->clock_source = p_instance_ctrl->p_cfg->clock_source; + p_rtc_info->status = (rtc_status_t) R_RTC->RCR2_b.START; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function sets time error adjustment + * + * Implements @ref rtc_api_t::errorAdjustmentSet + * + * @retval FSP_SUCCESS Time error adjustment successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open for operation. + * @retval FSP_ERR_UNSUPPORTED The clock source is not sub-clock. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid error adjustment value. + **********************************************************************************************************************/ +fsp_err_t R_RTC_ErrorAdjustmentSet (rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; +#if RTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Error adjustment is supported only if clock source is sub-clock */ + if (p_instance_ctrl->p_cfg->clock_source != RTC_CLOCK_SOURCE_SUBCLK) + { + return FSP_ERR_UNSUPPORTED; + } + + /* Verify the frequecy comparison valure for RFRL when using LOCO */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_rtc_err_adjustment_parameter_check(err_adj_cfg), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Set Error Adjustment values */ + r_rtc_error_adjustment_set(err_adj_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements rtc_api_t::callbackSet + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to RTC control block is NULL or the RTC is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_RTC_CallbackSet (rtc_ctrl_t * const p_ctrl, + void ( * p_callback)(rtc_callback_args_t *), + void * const p_context, + rtc_callback_args_t * const p_callback_memory) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + +#if (RTC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if RTC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + rtc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(rtc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set time capture configuration for the provided channel. + * + * Implements @ref rtc_api_t::timeCaptureSet + * + * @note Updating capture settings requires significant software delay. Timing considerations should be carefully + * considered when calling this function. + * + * @retval FSP_SUCCESS Setting for Time capture was successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + * @retval FSP_ERR_INVALID_CHANNEL Invalid input channel set. + * @retval FSP_ERR_UNSUPPORTED Hardware not support this feature. + **********************************************************************************************************************/ +fsp_err_t R_RTC_TimeCaptureSet (rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture) +{ +#if BSP_FEATURE_RTC_HAS_ALARM1 + #if (RTC_CFG_PARAM_CHECKING_ENABLE) + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time_capture); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_RTC_RTCCR_CHANNELS > p_time_capture->channel, FSP_ERR_INVALID_CHANNEL); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Clear config, set TCEN bit before set other bit. */ + R_RTC->RTCCR[p_time_capture->channel].RTCCR = R_RTC_RTCCR_RTCCR_TCEN_Msk; + + /* When RTCCRn is modified, check that all the bits except the TCST bit are updated before continuing with + * additional processing. (see "RTCCRn : Time Capture Control Register n (n = 0 to 2)" + * in the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[p_time_capture->channel].RTCCR, (uint8_t) R_RTC_RTCCR_RTCCR_TCEN_Msk); + + R_RTC->RTCCR[p_time_capture->channel].RTCCR |= + (uint8_t) (p_time_capture->noise_filter << R_RTC_RTCCR_RTCCR_TCNF_Pos); + + /* When the noise filter is used, set the TCNF[2:0] bits,wait for 3 cycles of the specified sampling period (see + * "RTCCRn : Time Capture Control Register n (n = 0 to 2)" in the relevant hardware manual) */ + uint32_t noise_filter_delay_us = 0; + switch (p_time_capture->noise_filter) + { + case RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_32: + { + noise_filter_delay_us = BSP_DELAY_US_PER_SECOND * (NOISE_FILTER_CLOCK_DIVIDE_32 / BSP_SUBCLOCK_FREQ_HZ); + break; + } + + case RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_4096: + { + noise_filter_delay_us = BSP_DELAY_US_PER_SECOND * (NOISE_FILTER_CLOCK_DIVIDE_4096 / BSP_SUBCLOCK_FREQ_HZ); + break; + } + + case RTC_TIME_CAPTURE_NOISE_FILTER_ON_DIVIDER_8192: + { + noise_filter_delay_us = BSP_DELAY_US_PER_SECOND * (NOISE_FILTER_CLOCK_DIVIDE_8192 / BSP_SUBCLOCK_FREQ_HZ); + break; + } + + default: + { + noise_filter_delay_us = BSP_DELAY_US_PER_SECOND * (NOISE_FILTER_CLOCK_DIVIDE_1 / BSP_SUBCLOCK_FREQ_HZ); + break; + } + } + + R_BSP_SoftwareDelay(NOISE_FILTER_SET_NUMBER_DELAY * noise_filter_delay_us, BSP_DELAY_UNITS_MICROSECONDS); + + /* When RTCCRn is modified, check that all the bits except the TCST bit are updated before continuing with + * additional processing. (see "RTCCRn : Time Capture Control Register n (n = 0 to 2)" + * in the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[p_time_capture->channel].RTCCR_b.TCNF, + (uint8_t) p_time_capture->noise_filter); + + R_RTC->RTCCR[p_time_capture->channel].RTCCR |= (uint8_t) (p_time_capture->source << R_RTC_RTCCR_RTCCR_TCCT_Pos); + + /* When RTCCRn is modified, check that all the bits except the TCST bit are updated before continuing with + * additional processing. (see "RTCCRn : Time Capture Control Register n (n = 0 to 2)" + * in the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[p_time_capture->channel].RTCCR_b.TCCT, (uint8_t) p_time_capture->source); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_time_capture); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Get time capture value of the provided channel. + * + * Implements @ref rtc_api_t::timeCaptureGet + * + * @retval FSP_SUCCESS Get time capture successful. + * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_NOT_OPEN Driver not open already for operation. + * @retval FSP_ERR_INVALID_CHANNEL Invalid input channel get. + * @retval FSP_ERR_INVALID_STATE Invalid operation state. + * @retval FSP_ERR_UNSUPPORTED Hardware not support this feature. + **********************************************************************************************************************/ +fsp_err_t R_RTC_TimeCaptureGet (rtc_ctrl_t * const p_ctrl, rtc_time_capture_t * const p_time_capture) +{ +#if BSP_FEATURE_RTC_HAS_ALARM1 + #if (RTC_CFG_PARAM_CHECKING_ENABLE) + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_time_capture); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_RTC_RTCCR_CHANNELS > p_time_capture->channel, FSP_ERR_INVALID_CHANNEL); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* The event is detected only during count operation (RCR2.START bit = 1). Before reading the capture register, + * make sure that this bit is set to 1. */ + FSP_ERROR_RETURN(R_RTC->RCR2_b.START == 1U, FSP_ERR_INVALID_STATE); + + /* Capture event detected */ + FSP_ERROR_RETURN(R_RTC->RTCCR[p_time_capture->channel].RTCCR_b.TCST == 1U, FSP_ERR_INVALID_STATE); + + /* Get configuration of capture source and noise filter */ + p_time_capture->source = (rtc_time_capture_source_t) R_RTC->RTCCR[p_time_capture->channel].RTCCR_b.TCCT; + p_time_capture->noise_filter = (rtc_time_capture_noise_filter_t) R_RTC->RTCCR[p_time_capture->channel].RTCCR_b.TCNF; + + /* Before reading from this register, the time capture event detection should be stopped using the RTCCRn.TCCT[1:0] + * bits.(see "RSECCPn : Second Capture Register n (n = 0 to 2) (in Calendar Count Mode)" + * in the RTC section of the relevant hardware manual.) */ + uint8_t rtccr = R_RTC->RTCCR[p_time_capture->channel].RTCCR; + R_RTC->RTCCR[p_time_capture->channel].RTCCR = rtccr & ((uint8_t) ~R_RTC_RTCCR_RTCCR_TCCT_Msk); + + /* When RTCCRn is modified, check that all the bits except the TCST bit are updated before continuing with + * additional processing. (see "RTCCRn : Time Capture Control Register n (n = 0 to 2)" + * in the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[p_time_capture->channel].RTCCR, + (uint8_t) (rtccr & ((uint8_t) ~R_RTC_RTCCR_RTCCR_TCCT_Msk))); + + p_time_capture->time.tm_sec = rtc_bcd_to_dec(R_RTC->CP[p_time_capture->channel].RSEC & RTC_MASK_8TH_BIT); + p_time_capture->time.tm_min = rtc_bcd_to_dec(R_RTC->CP[p_time_capture->channel].RMIN & RTC_MASK_8TH_BIT); + p_time_capture->time.tm_hour = rtc_bcd_to_dec(R_RTC->CP[p_time_capture->channel].RHR & RTC_MASK_8TH_BIT); + p_time_capture->time.tm_mday = rtc_bcd_to_dec(R_RTC->CP[p_time_capture->channel].RDAY & RTC_MASK_8TH_BIT); + + /* Subtract one from month to match with C time.h standards */ + p_time_capture->time.tm_mon = rtc_bcd_to_dec(R_RTC->CP[p_time_capture->channel].RMON & RTC_MASK_8TH_BIT) - + (uint8_t) 1; + + /* Restore setting and clear Time capture status bit */ + R_RTC->RTCCR[p_time_capture->channel].RTCCR = rtccr & ((uint8_t) ~R_RTC_RTCCR_RTCCR_TCST_Msk); + + /* When RTCCRn is modified, check that all the bits except the TCST bit are updated before continuing with + * additional processing. (see "RTCCRn : Time Capture Control Register n (n = 0 to 2)" + * in the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[p_time_capture->channel].RTCCR, + (uint8_t) (rtccr & ((uint8_t) ~R_RTC_RTCCR_RTCCR_TCST_Msk))); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_time_capture); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * @} (end addtpgroup RTC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Update the start bit + * + * @param[in] value Value to be updated + **********************************************************************************************************************/ +static void r_rtc_start_bit_update (uint8_t value) +{ + /* Set or Clear START bit in RCR2 register depending on the value */ + R_RTC->RCR2_b.START = value & 1U; + + /* The START bit is updated in synchronization with the next cycle of the count source. Check if the bit is updated + * before proceeding (see "RTC Control Register 2 (RCR2)" in the relevant hardware manual)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.START, value); +} + +/*******************************************************************************************************************//** + * Perform a software reset + **********************************************************************************************************************/ +static void r_rtc_software_reset (void) +{ + /* Set the RESET bit in the RCR2 register */ + R_RTC->RCR2_b.RESET = 1U; + + /* When 1 is written to this bit, initialization starts in synchronization with the count source. When the + * initialization is completed, the RESET bit is automatically set to 0. Check that this bit is 0 before proceeding. + * (see "RTC Control Register 2 (RCR2)" in the relevant hardware manual)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.RESET, 0U); +} + +/*******************************************************************************************************************//** + * Set the RTC clock source + * + * @param[in] p_ctrl Instance control block + * @param[in] p_cfg Pointer to rtc configuration. + **********************************************************************************************************************/ +static void r_rtc_set_clock_source (rtc_instance_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg) +{ + /* Select the count source (RCKSEL) */ + R_RTC->RCR4 = (uint8_t) p_ctrl->p_cfg->clock_source; + + /* Supply 6 clocks of the count source (LOCO/SOSC, 183us, 32kHZ). + * See "Clock and Count Mode Setting Procedure" in the RTC section of the relevant hardware manual)*/ + R_BSP_SoftwareDelay(BSP_PRV_RTC_RESET_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS); + + r_rtc_start_bit_update(0U); + + if (RTC_CLOCK_SOURCE_LOCO == p_ctrl->p_cfg->clock_source) + { + /* Write 0 before writing to the RFRL register after a cold start. (see + * "Frequency Register (RFRH/RFRL)" description in the RTC section of the relevant hardware manual) */ + R_RTC->RFRH = 0; + + R_RTC->RFRL = (uint16_t) p_cfg->freq_compare_value; + } + + R_RTC->RCR2 = 0; + + /* When setting the count mode, execute an RTC software reset and start again from the initial settings. + * This bit is updated synchronously with the count source, and its value is fixed before the RTC software + * reset is completed (see "RTC Control Register 2 (RCR2)" description in the relevant hardware manual)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.CNTMD, RTC_CALENDAR_MODE); + + r_rtc_software_reset(); + + /* Disable RTC interrupts */ + R_RTC->RCR1 = 0; + + /* When the RCR1 register is modified, check that all the bits are updated before proceeding + * (see "RTC Control Register 1 (RCR1)" description in the relevant hardware manual)*/ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR1, 0); + + /* Force RTC to 24 hour mode. Set HR24 bit in the RCR2 register */ + R_RTC->RCR2_b.HR24 = 1U; + + /* + * See "Notes on Writing to and Reading from Registers" in the RTC section of the relevant hardware manual. + * The value written is reflected when fourth read operations are performed after writing. + */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.HR24, 1); + +#if BSP_FEATURE_RTC_HAS_TCEN + for (uint8_t index = 0U; index < BSP_FEATURE_RTC_RTCCR_CHANNELS; index++) + { + /* RTCCRn.TCEN must be cleared after reset. */ + R_RTC->RTCCR[index].RTCCR_b.TCEN = 0U; + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RTCCR[index].RTCCR_b.TCEN, 0); + } +#endif +} + +/*******************************************************************************************************************//** + * Set IRQ priority and control info for IRQ handler . + * + * @param[in] p_ctrl Instance control block + * @param[in] p_cfg Pointer to rtc configuration. + **********************************************************************************************************************/ +static void r_rtc_config_rtc_interrupts (rtc_instance_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg) +{ + if (p_cfg->periodic_irq >= 0) + { + R_BSP_IrqCfg(p_cfg->periodic_irq, p_cfg->periodic_ipl, p_ctrl); + } + + if (p_cfg->alarm_irq >= 0) + { + R_BSP_IrqCfg(p_cfg->alarm_irq, p_cfg->alarm_ipl, p_ctrl); + } + +#if BSP_FEATURE_RTC_HAS_ALARM1 + if (((rtc_extended_cfg_t *) p_cfg->p_extend)->alarm1_irq >= 0) + { + R_BSP_IrqCfg(((rtc_extended_cfg_t *) p_cfg->p_extend)->alarm1_irq, + ((rtc_extended_cfg_t *) p_cfg->p_extend)->alarm1_ipl, + p_ctrl); + } +#endif + if (p_cfg->carry_irq >= 0) + { + R_BSP_IrqCfg(p_cfg->carry_irq, p_cfg->carry_ipl, p_ctrl); + } +} + +/*******************************************************************************************************************//** + * Helper function to enable or disable the Alarm/ Periodic/ Carry interrupt + * + * @param[in] irq_enable_flag Interrupt enable + * @param[in] mask Mask for the corresponding interrupt enable bit in RCR1 + **********************************************************************************************************************/ +static void r_rtc_irq_set (bool irq_enable_flag, uint8_t mask) +{ + /* Enable the RTC carry interrupt request */ + if (irq_enable_flag) + { + /* Set the Interrupt Enable in RCR1 */ + R_RTC->RCR1 |= mask; + + /* When the RCR1 register is modified, check that all the bits are updated before proceeding + * (see "RTC Control Register 1 (RCR1)" description in the RTC section of the relevant hardware manual)*/ + FSP_HARDWARE_REGISTER_WAIT((R_RTC->RCR1 & mask), mask); + } + else + { + /* Clear the Interrupt Enable in RCR1 */ + R_RTC->RCR1 &= (uint8_t) ~mask; + + FSP_HARDWARE_REGISTER_WAIT((R_RTC->RCR1 & mask), 0U); + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to RTC instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_rtc_call_callback (rtc_instance_ctrl_t * p_ctrl, rtc_event_t event) +{ + rtc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + rtc_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + rtc_prv_ns_callback p_callback = (rtc_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +#if RTC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Validate RFRL value for LOCO + * + * @param[in] value Frequency Comparison Value + * @retval FSP_SUCCESS validation successful + * @retval FSP_ERR_INVALID_ARGUMENT invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_rfrl_validate (uint32_t value) +{ + fsp_err_t err; + err = FSP_SUCCESS; + + /* A value from 0007h through 01FFh can be specified as the frequency comparison value (see + * Frequency Register (RFRH/RFRL)" description in the RTC section of the relevant hardware manual.) */ + if ((RTC_RFRL_MIN_VALUE_LOCO >= value) || + (RTC_RFRL_MAX_VALUE_LOCO <= value)) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + + return err; +} + +/*******************************************************************************************************************//** + * Validate Error Adjustment configuration when using SubClock + * + * @param[in] err_adj_cfg Pointer to error adjustment config + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid error configuration + **********************************************************************************************************************/ +static fsp_err_t r_rtc_err_adjustment_parameter_check (rtc_error_adjustment_cfg_t const * const err_adj_cfg) +{ + rtc_error_adjustment_mode_t mode = err_adj_cfg->adjustment_mode; + rtc_error_adjustment_period_t period = err_adj_cfg->adjustment_period; + uint32_t value = err_adj_cfg->adjustment_value; + + /* Validate adjustment mode and period */ + if (RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC == mode) + { + if (RTC_ERROR_ADJUSTMENT_PERIOD_NONE == period) + { + return FSP_ERR_INVALID_ARGUMENT; + } + } + + /* Validate adjustment value */ + if (value > RTC_MAX_ERROR_ADJUSTMENT_VALUE) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validate time and date fields of time parameter fields + * Checking for seconds, minutes, hours are valid values by calling sub-function time validate. + * Checking for year, month, day of the week and day of a month are valid values by calling sub-function + * date validate. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_time_and_date_validate (rtc_time_t * const p_time) +{ + fsp_err_t err = FSP_SUCCESS; + err = r_rtc_time_validate(p_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + err = r_rtc_date_validate(p_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validate time fields of time type parameter + * Checking for the seconds, minutes, hours values for valid specified range. + * Seconds 0 to 59. + * Minutes 0 to 59. + * Hours 0 to 23. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_time_validate (rtc_time_t * p_time) +{ + fsp_err_t err; + err = FSP_SUCCESS; + if ((p_time->tm_sec < 0) || (p_time->tm_sec > RTC_SECONDS_IN_A_MINUTE) || + (p_time->tm_min < 0) || (p_time->tm_min > RTC_MINUTES_IN_A_HOUR) || + (p_time->tm_hour < 0) || (p_time->tm_hour > RTC_HOURS_IN_A_DAY)) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + + return err; +} + +/*******************************************************************************************************************//** + * Validate date fields of time type parameter + * validating r_rtc date fields and setting day of a Week using Zeller's congruence. + * Checking for year, month, day of the week and day of a month are valid values. + * Leap year validation and Week of the day is calculated and updated in rtc time. + * Day of week between 0 to 6 + * Day between 1 to 31 + * Month between 0 to 11 as per standard time.h, There's a mismatch between hardware configuration, + * UM indicates that "A value from 01 through 12 (in BCD) can be specified" for Month Counter register in the RTC. + * This difference will be taken care in the Set and Get functions. + * + * As per HW manual, value of Year is between 0 to 99, the RTC has a 100 year calendar from 2000 to 2099. + * (see section "Overview" in the RTC section of the relevant hardware manual) + * But as per C standards, tm_year is years since 1900. + * A sample year set in an application would be like time.tm_year = 2019-1900; (to set year 2019) + * Since RTC API follows the Date and time structure defined in C standard library , the valid value of year is + * between 100 and 199, which will be internally converted to HW required value. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_date_validate (rtc_time_t * const p_time) +{ + uint32_t day_of_week; + uint32_t num_days_month; + uint32_t day_of_a_month; + uint32_t temp_month; + uint32_t temp_year; + + day_of_a_month = (uint32_t) p_time->tm_mday; + temp_month = (uint32_t) (p_time->tm_mon + RTC_TIME_H_MONTH_OFFSET); + + /* The valid value of year is between 100 to 199, The RTC has a 100 year calendar from 2000 to 2099 + * to match the starting year 2000, a sample year offset(1900) is added like 117 + 1900 = 2017*/ + temp_year = (uint32_t) (p_time->tm_year + RTC_TIME_H_YEAR_OFFSET); + + /* Checking the error condition for year and months values, here valid value of year is between 100 to 199 + * and for month 0 to 11*/ + if ((p_time->tm_year < RTC_YEAR_VALUE_MIN) || (p_time->tm_year > RTC_YEAR_VALUE_MAX) || + (p_time->tm_mon < 0) || (p_time->tm_mon > RTC_MONTHS_IN_A_YEAR)) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + /*For particular valid month, number of days in a month is updated */ + num_days_month = days_in_months[p_time->tm_mon]; + + /* Checking for February month and Conditions for Leap year : Every fourth year is a leap year, + * The RTC has a 100 year calendar from 2000 to 2099 */ + if ((RTC_FEBRUARY_MONTH == temp_month) && ((temp_year % 4U) == 0)) + { + num_days_month = RTC_LAST_DAY_OF_LEAP_FEB_MONTH; + } + + /* Checking for day of a month values for valid range */ + if ((p_time->tm_mday >= RTC_FIRST_DAY_OF_A_MONTH) && (day_of_a_month <= num_days_month)) + { + /* Adjust month to run from 3 to 14 for March to February */ + if (temp_month < RTC_MARCH_MONTH) + { + temp_month = (temp_month + 12U); + + /* Adjust year if January or February*/ + --temp_year; + } + + /*For the Gregorian calendar, Zeller's congruence formulas is + * h = ( q + [13(m+1)/5] + Y + [Y/4] - [Y/100] + [Y/400])mod 7 (mod : modulo) + * h is the day of the week , q is the day of the month, + * m is the month (3 = March, 4 = April,..., 14 = February) + * Y is year, which is Y - 1 during January and February */ + day_of_week = (uint32_t) p_time->tm_mday + ((13 * (temp_month + 1)) / 5) + temp_year + (temp_year / 4); + day_of_week = (day_of_week - RTC_ZELLER_ALGM_CONST_FIFTEEN) % 7; + + /* Day of week between 0 to 6 :- Sunday to Saturday */ + /* d = (h + 6)mod 7 (mod : modulo) */ + p_time->tm_wday = (int16_t) ((day_of_week + 6U) % 7U); + + return FSP_SUCCESS; + } + + return FSP_ERR_INVALID_ARGUMENT; +} + +/*******************************************************************************************************************//** + * Validate alarm time and date of Alarm time type parameter + * Checking for alarm enable bit with the seconds, minutes, hours are valid values. + * Checking for alarm enable bit with year, month, day of the week and day of a month are valid values. + * If alarm enable bit is set for year, month, and day of a month for valid range, Week of the day is + * calculated and updated in alarm time. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_alarm_time_and_date_validate (rtc_alarm_time_t * const p_time) +{ + fsp_err_t err = FSP_SUCCESS; + err = r_rtc_alarm_time_validate(p_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + + /* Checking for alarm enable bit for year, month, day of the month */ + if ((p_time->year_match) && (p_time->mon_match) && (p_time->mday_match)) + { + err = r_rtc_date_validate(&p_time->time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + } + else + { + err = r_rtc_alarm_month_and_year_validate(p_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + err = r_rtc_alarm_dayofmonth_and_dayofweek_validate(p_time); + FSP_ERROR_RETURN(err == FSP_SUCCESS, err); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validate alarm time fields of Alarm time type parameter + * Checking for alarm enable bit with the seconds, minutes, hours value for valid specified range. + * Seconds 0 to 59. + * Minutes 0 to 59. + * Hours 0 to 23. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_alarm_time_validate (rtc_alarm_time_t * const p_time) +{ + fsp_err_t err; + err = FSP_SUCCESS; + if (((p_time->sec_match) && + ((p_time->time.tm_sec < 0) || (p_time->time.tm_sec > RTC_SECONDS_IN_A_MINUTE))) || + ((p_time->min_match) && + ((p_time->time.tm_min < 0) || (p_time->time.tm_min > RTC_MINUTES_IN_A_HOUR))) || + ((p_time->hour_match) && + ((p_time->time.tm_hour < 0) || (p_time->time.tm_hour > RTC_HOURS_IN_A_DAY)))) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + + return err; +} + +/*******************************************************************************************************************//** + * Validate alarm month and year of time type parameter + * Checking for alarm enable bit with month and year value for valid specified range. + * Month : 0 to 11. + * Year : 100 to 199. + * Since RTC API follows the Date and time structure defined in C standard library , the valid value of year is + * between 100 to 199. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_alarm_month_and_year_validate (rtc_alarm_time_t * const p_time) +{ + fsp_err_t err; + err = FSP_SUCCESS; + if (((p_time->mon_match) && + ((p_time->time.tm_mon < 0) || (p_time->time.tm_mon > RTC_MONTHS_IN_A_YEAR))) || + ((p_time->year_match) && + ((p_time->time.tm_year < RTC_YEAR_VALUE_MIN) || (p_time->time.tm_year > RTC_YEAR_VALUE_MAX)))) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + + return err; +} + +/*******************************************************************************************************************//** + * Validate alarm day of a month and day of the week of time type parameter + * Checking for alarm enable bit with day of a month and day of the week values for valid specified range. + * Day of a month : 1 to 31. + * Day of the week : 0 to 6. + * If alarm enable bit is set for particular valid month, number of days in a month is updated from that particular + * month, by default 31 days in a month and for February month days are considered as 29 days in a month. + * + * @param[in] p_time Pointer to rtc_time_t + * @retval FSP_SUCCESS Validation successful + * @retval FSP_ERR_INVALID_ARGUMENT Invalid field in rtc_time_t structure + **********************************************************************************************************************/ +static fsp_err_t r_rtc_alarm_dayofmonth_and_dayofweek_validate (rtc_alarm_time_t * const p_time) +{ + fsp_err_t err; + uint8_t num_days_month; + uint8_t day_of_a_month; + + day_of_a_month = (uint8_t) p_time->time.tm_mday; + err = FSP_SUCCESS; + + /* checking for alarm enable bit of valid month */ + if (p_time->mon_match) + { + /* Checking condition for February month in time.h months start from 0 to 11, for February 1 */ + if ((RTC_FEBRUARY_MONTH - 1U) == p_time->time.tm_mon) + { + /*For February month, number of days can be 28 for regular year and 29 for leap year. + * Hence consider 29 days for February.*/ + num_days_month = (uint8_t) RTC_LAST_DAY_OF_LEAP_FEB_MONTH; + } + else + { + /* For valid month, number of days in month is assigned*/ + num_days_month = days_in_months[p_time->time.tm_mon]; + } + } + else + { + /* default 31 days in a month*/ + num_days_month = (uint8_t) RTC_LAST_DAY_OF_A_MONTH; + } + + if (((p_time->mday_match) && + ((p_time->time.tm_mday < RTC_FIRST_DAY_OF_A_MONTH) || (day_of_a_month > num_days_month))) || + ((p_time->dayofweek_match) && + ((p_time->time.tm_wday < 0) || (p_time->time.tm_wday > RTC_DAYS_IN_A_WEEK)))) + { + err = FSP_ERR_INVALID_ARGUMENT; + } + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * This function sets time error adjustment mode, period, type and value. + * + *@param[in] err_adj_cfg Pointer to the Error Adjustment Configuration + **********************************************************************************************************************/ +static void r_rtc_error_adjustment_set (rtc_error_adjustment_cfg_t const * const err_adj_cfg) +{ + rtc_error_adjustment_mode_t mode = err_adj_cfg->adjustment_mode; + rtc_error_adjustment_period_t period = err_adj_cfg->adjustment_period; + rtc_error_adjustment_t type = err_adj_cfg->adjustment_type; + uint32_t value = err_adj_cfg->adjustment_value; + + /* Check if mode change is required */ + if (mode != R_RTC->RCR2_b.AADJE) + { + /* Clear error adjustment before configuring the error adjustment mode + * (see section "Procedure for changing the mode of adjustment" in the RTC section of the + * relevant hardware manual) */ + R_RTC->RADJ = 0U; + + /* When RADJ is modified, check that all the bits are updated before continuing with more processing. + * (see "Time Error Adjustment Register (RADJ)" description in the RTC section of the relevant + * hardware manual.) */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RADJ, 0U); + + /* Set the error adjustment enable, 1: Enable Automatic adjsutment 0: Disable Automatic adjsutment */ + R_RTC->RCR2_b.AADJE = (uint8_t) mode & 1U; + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.AADJE, mode); + } + + /* Set the period if mode is Automatic adjustment */ + if (RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC == mode) + { + /* Check if period change is required */ + if (period != R_RTC->RCR2_b.AADJP) + { + /* Set time error adjustment period */ + R_RTC->RCR2_b.AADJP = (uint8_t) (period & 1U); + + /* When RCR2 is modified, check that all the bits are updated before continuing with more processing. + * (see "RTC Control Register 2 (RCR2)" description in the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RCR2_b.AADJP, period); + } + } + +#if BSP_FEATURE_RTC_HAS_RADJ_ADJ6 + uint16_t error_adjustment = + (uint16_t) ((uint16_t) (((value & RTC_ADJ6_ADJUSTMENT_VALUE) > 0) << R_RTC_RADJ_ADJ6_Pos) | + ((uint8_t) (type << R_RTC_RADJ_PMADJ_Pos) | + (value & RTC_MAX_ADJ_VALUE))); +#else + uint8_t error_adjustment = (uint8_t) ((uint8_t) (((uint8_t) type) << R_RTC_RADJ_PMADJ_Pos) | + (RTC_MAX_ERROR_ADJUSTMENT_VALUE & value)); +#endif + + R_RTC->RADJ = error_adjustment; + + /* When RADJ is modified, check that all the bits are updated before continuing with more processing. + * (see "Time Error Adjustment Register (RADJ)" in the RTC section of the relevant hardware manual) */ + FSP_HARDWARE_REGISTER_WAIT(R_RTC->RADJ, error_adjustment); +} + +/*******************************************************************************************************************//** + * RTC Callback ISR for alarm and periodic interrupt. + * + * Saves context if RTOS is used, stops the timer if one-shot mode, clears interrupts, calls callback if one was + * provided in the open function, and restores context if RTOS is used. + **********************************************************************************************************************/ + +void rtc_alarm_periodic_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + rtc_instance_ctrl_t * p_ctrl = (rtc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable the RTC Register Read/Write clock if it was disabled prior to entering LPM. */ + bsp_prv_rtc_register_clock_set(true); +#endif + + /* Call the callback routine if one is available */ + if (NULL != p_ctrl->p_callback) + { + /* Set data to identify callback to user, then call user callback. */ + rtc_event_t event; + if (irq == p_ctrl->p_cfg->alarm_irq) + { + event = RTC_EVENT_ALARM_IRQ; + } + +#if BSP_FEATURE_RTC_HAS_ALARM1 + else if (irq == ((rtc_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->alarm1_irq) + { + event = RTC_EVENT_ALARM1_IRQ; + } +#endif + else + { + event = RTC_EVENT_PERIODIC_IRQ; + } + + /* Call callback */ + r_rtc_call_callback(p_ctrl, event); + } + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * RTC Carry ISR. + * + * Saves context if RTOS is used, clears interrupts, calls callback if one was + * provided in the open function, and restores context if RTOS is used. + **********************************************************************************************************************/ +void rtc_carry_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + rtc_instance_ctrl_t * p_ctrl = (rtc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + +#if BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE + + /* Enable the RTC Register Read/Write clock if it was disabled prior to entering LPM. */ + bsp_prv_rtc_register_clock_set(true); +#endif + + p_ctrl->carry_isr_triggered = true; + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Convert decimal to BCD + * + * @param[in] to_convert Decimal Value to be converted + **********************************************************************************************************************/ +static uint8_t rtc_dec_to_bcd (uint8_t to_convert) +{ + return (uint8_t) ((((to_convert / (uint8_t) 10) << 4) & (uint8_t) RTC_MASK_LSB) | (to_convert % (uint8_t) 10)); +} + +/*******************************************************************************************************************//** + * Convert BCD to decimal + * + * @param[in] to_convert BCD Value to be converted + **********************************************************************************************************************/ +static uint8_t rtc_bcd_to_dec (uint8_t to_convert) +{ + return (uint8_t) ((((to_convert & (uint8_t) RTC_MASK_LSB) >> 4) * (uint8_t) 10) + + (to_convert & (uint8_t) RTC_MASK_MSB)); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_i2c/r_sau_i2c.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_i2c/r_sau_i2c.c new file mode 100644 index 0000000000..15b83935e9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_i2c/r_sau_i2c.c @@ -0,0 +1,1080 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_sau_i2c.h" + +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + #include "r_dtc.h" +#endif + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "SI2C" in ASCII, used to determine if channel is open. */ +#define SAU_I2C_OPEN (0x53493243ULL) + +/* DTC transfer settings for TX descriptor when reading data (for dummy write)*/ +#define SAU_I2C_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_CHAIN_MODE_DISABLED << \ + TRANSFER_SETTINGS_CHAIN_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +/* DTC transfer settings for TX descriptor when writing data */ +#define SAU_I2C_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_CHAIN_MODE_DISABLED << \ + TRANSFER_SETTINGS_CHAIN_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#define SAU_I2C_PRV_DUMMY_WRITE_DATA_FOR_READ_OP (0xFFU) + +#define SAU_I2C_PRV_SMR_INIT (0x0024U) +#define SAU_I2C_PRV_SCR_REG_INIT (0x8017U) +#define SAU_I2C_PRV_SO0_REG_INIT (0x0101U) +#define SAU_I2C_PRV_SAU0_SPS_REG_INIT ((BSP_CFG_SAU_CK01_DIV << R_SAU0_SPS_PRS1_Pos) | \ + BSP_CFG_SAU_CK00_DIV) +#define SAU_I2C_PRV_SAU1_SPS_REG_INIT ((BSP_CFG_SAU_CK11_DIV << R_SAU0_SPS_PRS1_Pos) | \ + BSP_CFG_SAU_CK10_DIV) +#define SAU_I2C_PRV_SCR_TE_MASK (0x8000U) +#define SAU_I2C_PRV_SCR_RE_MASK (0x4000U) + +#define SAU_I2C_SO_SCL_HIGH (1 << R_SAU0_SO_CKO_Pos) +#define SAU_I2C_SO_SDA_HIGH (1 << R_SAU0_SO_SO_Pos) + +#define SAU_I2C_PRV_SIR_MASK (R_SAU0_SIR_OVCT_Msk | R_SAU0_SIR_PECT_Msk | \ + R_SAU0_SIR_FECT_Msk) + +#if 0 == SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE /* Only IIC00 used (Unit 0 Channel 0) */ + #define SAU_I2C_PRV_CHANNEL (0) + #define SAU_I2C_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_I2C_PRV_SPS_REG_INIT (SAU_I2C_PRV_SAU0_SPS_REG_INIT) +#elif 1 == SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE /* Only IIC01 used (Unit 0 Channel 1) */ + #define SAU_I2C_PRV_CHANNEL (1) + #define SAU_I2C_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_I2C_PRV_SPS_REG_INIT (SAU_I2C_PRV_SAU0_SPS_REG_INIT) +#elif 10 == SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE /* Only IIC10 used (Unit 0 Channel 2) */ + #define SAU_I2C_PRV_CHANNEL (2) + #define SAU_I2C_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_I2C_PRV_SPS_REG_INIT (SAU_I2C_PRV_SAU0_SPS_REG_INIT) +#elif 11 == SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE /* Only IIC11 used (Unit 0 Channel 3) */ + #define SAU_I2C_PRV_CHANNEL (3) + #define SAU_I2C_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_I2C_PRV_SPS_REG_INIT (SAU_I2C_PRV_SAU0_SPS_REG_INIT) +#elif 20 == SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE /* Only IIC20 used (Unit 1 Channel 0) */ + #define SAU_I2C_PRV_CHANNEL (0) + #define SAU_I2C_PRV_UNIT (1) + #define SAU_REG (R_SAU1) + #define SAU_I2C_PRV_SPS_REG_INIT (SAU_I2C_PRV_SAU1_SPS_REG_INIT) +#elif 21 == SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE /* Only IIC21 used (Unit 1 Channel 1) */ + #define SAU_I2C_PRV_CHANNEL (1) + #define SAU_I2C_PRV_UNIT (1) + #define SAU_REG (R_SAU1) + #define SAU_I2C_PRV_SPS_REG_INIT (SAU_I2C_PRV_SAU1_SPS_REG_INIT) +#endif + +#if -1 == SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE /* Multiple IICxx instances used */ + #define SAU_REG (p_ctrl->p_reg) + #define SAU_I2C_PRV_UNIT (p_extend->i2c_unit) + #define SAU_I2C_PRV_CHANNEL_DECLARATION uint8_t i2c_channel = p_ctrl->p_cfg->channel + #define SAU_I2C_PRV_CHANNEL (i2c_channel) + #define SAU_I2C_PRV_SPS_REG_INIT (SAU_I2C_PRV_UNIT ? \ + SAU_I2C_PRV_SAU1_SPS_REG_INIT : SAU_I2C_PRV_SAU0_SPS_REG_INIT) +#else + #define SAU_I2C_PRV_CHANNEL_DECLARATION +#endif + +#if SAU_I2C_CFG_CRITICAL_SECTION_ENABLE + #define SAU_I2C_CRITICAL_SECTION_ENTER() FSP_CRITICAL_SECTION_DEFINE; FSP_CRITICAL_SECTION_ENTER + #define SAU_I2C_CRITICAL_SECTION_EXIT() FSP_CRITICAL_SECTION_EXIT; +#else + #define SAU_I2C_CRITICAL_SECTION_ENTER() + #define SAU_I2C_CRITICAL_SECTION_EXIT() +#endif + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* I2C read/write enumeration */ +typedef enum e_sau_i2c_transfer_dir +{ + SAU_I2C_TRANSFER_DIR_WRITE = 0x0, + SAU_I2C_TRANSFER_DIR_READ = 0x1 +} sau_i2c_transfer_dir_t; + +/********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/* Internal helper functions */ +static void r_sau_i2c_transfer_complete(sau_i2c_instance_ctrl_t * const p_ctrl, + bool is_nack, + i2c_master_event_t const event); +static void r_sau_i2c_abort_seq_master(sau_i2c_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_sau_i2c_read_write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + sau_i2c_transfer_dir_t direction); + +/* Functions that manipulate hardware */ +static void r_sau_i2c_open_hw_master(sau_i2c_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg); +static void r_sau_i2c_hw_stop(sau_i2c_instance_ctrl_t * const p_ctrl); + +void sau_i2c_tei_isr(void); + +static void r_sau_i2c_tei_handler(sau_i2c_instance_ctrl_t * const p_ctrl); +static bool r_sau_i2c_do_tx_rx(sau_i2c_instance_ctrl_t * const p_ctrl, i2c_master_event_t * const p_event); + +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE +static fsp_err_t r_sau_i2c_transfer_open(sau_i2c_instance_ctrl_t * p_ctrl, i2c_master_cfg_t const * const p_cfg); +static fsp_err_t r_sau_i2c_transfer_configure(sau_i2c_instance_ctrl_t * p_ctrl, transfer_instance_t const * p_transfer); +static void r_sau_i2c_reconfigure_dtc_for_transfer(sau_i2c_instance_ctrl_t * const p_ctrl); +static void r_sau_i2c_dtc_transfer_enable(sau_i2c_instance_ctrl_t * const p_ctrl, + transfer_info_t * const p_info, + uint16_t bytes_to_transfer); + +#endif + +/********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + +/* constant used as the source location for the DTC dummy write */ +static const uint8_t g_dummy_write_data_for_read_op = SAU_I2C_PRV_DUMMY_WRITE_DATA_FOR_READ_OP; +#endif + +/********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* Simple I2C on SAU HAL API mapping for I2C Master interface */ +i2c_master_api_t const g_i2c_master_on_sau = +{ + .open = R_SAU_I2C_Open, + .read = R_SAU_I2C_Read, + .write = R_SAU_I2C_Write, + .abort = R_SAU_I2C_Abort, + .slaveAddressSet = R_SAU_I2C_SlaveAddressSet, + .close = R_SAU_I2C_Close, + .callbackSet = R_SAU_I2C_CallbackSet, + .statusGet = R_SAU_I2C_StatusGet +}; + +/*******************************************************************************************************************//** + * @addtogroup SAU_I2C + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Opens the SAU device. + * + * @retval FSP_SUCCESS Requested clock rate was set exactly. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. p_api_ctrl or p_cfg is NULL. + * 2. extended parameter is NULL. + * 3. Callback parameter is NULL. + * 4. Clock rate requested is greater than 400KHz + * 5. Invalid IRQ number assigned + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + sau_i2c_instance_ctrl_t * p_ctrl = (sau_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SAU_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_cfg != NULL); + FSP_ASSERT(p_cfg->p_extend != NULL); + FSP_ASSERT((I2C_MASTER_RATE_STANDARD == p_cfg->rate) || (I2C_MASTER_RATE_FAST == p_cfg->rate) || + (I2C_MASTER_RATE_FASTPLUS == p_cfg->rate)); + FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); + FSP_ERROR_RETURN(SAU_I2C_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + +#if -1 == SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE + sau_i2c_extended_cfg_t const * const p_extend = (sau_i2c_extended_cfg_t *) p_cfg->p_extend; + #ifdef R_SAU1 + SAU_REG = + (R_SAU0_Type *) ((uint32_t) R_SAU0_BASE + + (SAU_I2C_PRV_UNIT * ((uint32_t) R_SAU1_BASE - (uint32_t) R_SAU0_BASE))); + #else + SAU_REG = R_SAU0; + #endif +#endif + + /* Record the configuration on the device for use later */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->slave = (uint8_t) p_cfg->slave; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + + /* When DTC is enabled, data read and write will be done using DTC. + * There is only 1 IRQ for SAU I2C, so chain transfer mode will be used. + * p_transfer_tx points to an array of two transfer info descriptors. + * The first one is for reading data from SDR, + * and the second one is for writing data to SDR. + * For write operation, only the second transfer descriptor will be used. + */ + fsp_err_t err = r_sau_i2c_transfer_open(p_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + R_BSP_MODULE_START(FSP_IP_SAU, SAU_I2C_PRV_UNIT); + + /* Open the hardware in master mode */ + r_sau_i2c_open_hw_master(p_ctrl, p_cfg); + + /* Exact value is don't-care, but loaded and total must have same initial value + * to indicate that a transfer is not currently in progress */ + p_ctrl->loaded = p_ctrl->total; + +#if SAU_I2C_CFG_RESTART_ENABLE + p_ctrl->restarted = false; + p_ctrl->restart = false; +#endif + p_ctrl->open = SAU_I2C_OPEN; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Performs a read from the I2C device. + * The caller will be notified when the operation has completed (successfully) by an + * I2C_MASTER_EVENT_RX_COMPLETE in the callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION The parameter p_api_ctrl, p_dest is NULL, bytes is 0. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than uint16_t size (65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_Read (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart) +{ +#if SAU_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); + FSP_ASSERT(bytes != 0U); +#endif +#if SAU_I2C_CFG_RESTART_ENABLE + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of r_sau_i2c_read_write to 4. */ + ((sau_i2c_instance_ctrl_t *) p_api_ctrl)->restart = restart; +#else + FSP_PARAMETER_NOT_USED(restart); +#endif + + /* Call the common helper function to perform I2C Read operation.*/ + fsp_err_t err = r_sau_i2c_read_write(p_api_ctrl, p_dest, bytes, SAU_I2C_TRANSFER_DIR_READ); + + return err; +} + +/******************************************************************************************************************//** + * Performs a write to the I2C device. + * + * This function will fail if there is already an in-progress I2C transfer on the associated channel. Otherwise, the + * I2C write operation will begin. + * The write operation is non-blocking and the caller will be notified when the operation has finished by + * an I2C_EVENT_TX_COMPLETE in the callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_api_ctrl, p_src is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than uint16_t size (65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_Write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart) +{ +#if SAU_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); +#endif +#if SAU_I2C_CFG_RESTART_ENABLE + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of r_sau_i2c_read_write to 4. */ + ((sau_i2c_instance_ctrl_t *) p_api_ctrl)->restart = restart; +#else + FSP_PARAMETER_NOT_USED(restart); +#endif + + /* Call the common helper function to perform I2C Write operation.*/ + fsp_err_t err = r_sau_i2c_read_write(p_api_ctrl, p_src, bytes, SAU_I2C_TRANSFER_DIR_WRITE); + + return err; +} + +/******************************************************************************************************************//** + * Aborts any in-progress transfer and forces the I2C peripheral into a ready state. + * + * This function will safely terminate any in-progress I2C transfer with the device. If a transfer is aborted, the user + * will be notified via callback with an abort event. + * + * @retval FSP_SUCCESS Transaction was aborted without issue. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_Abort (i2c_master_ctrl_t * const p_api_ctrl) +{ + sau_i2c_instance_ctrl_t * p_ctrl = (sau_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SAU_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(SAU_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Abort any transfer happening on the channel */ + r_sau_i2c_abort_seq_master(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets address of the slave device. + * + * This function is used to set the device address of the slave without reconfiguring the entire bus. + * + * @retval FSP_SUCCESS Address of the slave is set correctly. + * @retval FSP_ERR_ASSERTION p_ctrl or address is NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + * @retval FSP_ERR_IN_USE An I2C Transaction is in progress. + * + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode) +{ + sau_i2c_instance_ctrl_t * p_ctrl = (sau_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SAU_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(SAU_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Fail if there is already a transfer in progress */ + FSP_ERROR_RETURN((p_ctrl->loaded == p_ctrl->total) && (false == p_ctrl->restart), FSP_ERR_IN_USE); + + /* Fail if the addr_mode is not 7-bit mode */ + FSP_ASSERT(I2C_MASTER_ADDR_MODE_7BIT == addr_mode); +#else + FSP_PARAMETER_NOT_USED(addr_mode); +#endif + + /* Sets the address of the slave device */ + p_ctrl->slave = (uint8_t) slave; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback. + * + * @note p_callback_memory is not used in this implementation and can be set to NULL. + * + * Implements i2c_master_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory) +{ + sau_i2c_instance_ctrl_t * p_ctrl = (sau_i2c_instance_ctrl_t *) p_api_ctrl; + +#if (SAU_I2C_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SAU_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_PARAMETER_NOT_USED(p_callback_memory); + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides driver status. + * + * @retval FSP_SUCCESS Status stored in p_status. + * @retval FSP_ERR_ASSERTION NULL pointer. + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_StatusGet (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status) +{ + sau_i2c_instance_ctrl_t * p_ctrl = (sau_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SAU_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_status != NULL); +#endif + + p_status->open = (SAU_I2C_OPEN == p_ctrl->open); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Closes the I2C device. Power down I2C peripheral. + * + * This function will safely terminate any in-progress I2C transfer with the device. If a transfer is aborted, the user + * will be notified via callback with an abort event. + * + * @retval FSP_SUCCESS Device closed without issue. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_Close (i2c_master_ctrl_t * const p_api_ctrl) +{ + sau_i2c_instance_ctrl_t * p_ctrl = (sau_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SAU_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(SAU_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Abort an in-progress transfer with this device only */ + r_sau_i2c_abort_seq_master(p_ctrl); + + /* Disable interrupts */ + i2c_master_cfg_t const * const p_cfg = p_ctrl->p_cfg; + R_BSP_IrqDisable(p_cfg->tei_irq); + + /* The device is now considered closed */ + p_ctrl->open = 0U; + +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + if (NULL != p_cfg->p_transfer_tx) + { + p_cfg->p_transfer_tx->p_api->close(p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * @} (end defgroup SAU_I2C) + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Helper function for handling I2C Read or Write. + * + * @param p_api_ctrl Pointer to control block + * @param p_buffer Pointer to the buffer to store read/write data. + * @param[in] bytes Number of bytes to be read/written. + * @param[in] direction Read or Write + * + * @retval FSP_SUCCESS Function executed successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_buffer is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than UINT16_MAX(= 65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +static fsp_err_t r_sau_i2c_read_write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + sau_i2c_transfer_dir_t direction) +{ + sau_i2c_instance_ctrl_t * p_ctrl = (sau_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SAU_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_buffer != NULL); + FSP_ERROR_RETURN((SAU_I2C_OPEN == p_ctrl->open), FSP_ERR_NOT_OPEN); + FSP_ASSERT(((sau_i2c_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); + #if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + + /* DTC on RX could actually receive 65535+3 = 65538 bytes as 3 bytes are handled separately. + * Forcing to 65535 to keep TX and RX uniform with respect to max transaction length via DTC. + */ + FSP_ERROR_RETURN((bytes <= UINT16_MAX), FSP_ERR_INVALID_SIZE); + #endif +#endif + + /* Initialize fields used during transfer */ + p_ctrl->p_buff = p_buffer; + p_ctrl->total = bytes; + p_ctrl->loaded = 0U; + p_ctrl->read = (bool) direction; + + /* In case of read operation the first ACK detected on the bus is from the slave after the address is sent. + * Since we are reading on every ACK detection on the bus [in this case from this driver], + * we skip the first read corresponding to the address. */ + p_ctrl->do_dummy_read = (bool) direction; + +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + r_sau_i2c_reconfigure_dtc_for_transfer(p_ctrl); +#endif + + /* Clear error flag */ + R_SAU0_Type * p_reg = SAU_REG; + SAU_I2C_PRV_CHANNEL_DECLARATION; + p_reg->SIR[SAU_I2C_PRV_CHANNEL] = SAU_I2C_PRV_SIR_MASK; + + /* Set operation mode to transmission */ + uint16_t scr = p_reg->SCR[SAU_I2C_PRV_CHANNEL]; + p_reg->SCR[SAU_I2C_PRV_CHANNEL] = (scr & (uint16_t) (~R_SAU0_SCR_TRXE_Msk)) | SAU_I2C_PRV_SCR_TE_MASK; + +#if !SAU_I2C_CFG_MANUAL_START_STOP_ENABLE + (void) R_SAU_I2C_Start(p_ctrl); +#endif + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Single point for managing the logic around notifying a transfer has finished. + * + * @param[in] p_ctrl Pointer to transfer that is ending. + * @param[in] is_nack True if the transmission completed due to NACK, false otherwise + * @param[in] event The event code to pass to the callback. + **********************************************************************************************************************/ +static void r_sau_i2c_transfer_complete (sau_i2c_instance_ctrl_t * const p_ctrl, + bool is_nack, + i2c_master_event_t const event) +{ +#if SAU_I2C_CFG_RESTART_ENABLE + + /* Suppress stop if restart was requested, unless NACK response was received */ + if (p_ctrl->restart && !is_nack) + { + p_ctrl->restarted = true; + } + else +#else + FSP_PARAMETER_NOT_USED(is_nack); +#endif + { + r_sau_i2c_hw_stop(p_ctrl); + } + + i2c_master_callback_args_t args; + i2c_master_callback_args_t * p_args = &args; + p_args->p_context = p_ctrl->p_context; + p_args->event = event; + + /* Now do the callback here */ + p_ctrl->p_callback(p_args); +} + +/******************************************************************************************************************//** + * Single point for managing the logic around aborting a transfer when operating as a master. + * + * @param[in] p_ctrl Pointer to control struct of specific device + **********************************************************************************************************************/ +static void r_sau_i2c_abort_seq_master (sau_i2c_instance_ctrl_t * const p_ctrl) +{ + r_sau_i2c_hw_stop(p_ctrl); + +#if SAU_I2C_CFG_RESTART_ENABLE + p_ctrl->restarted = false; + p_ctrl->restart = false; +#endif + + /* Update state to make sure interrupts no longer progress */ + p_ctrl->loaded = p_ctrl->total; +} + +/******************************************************************************************************************//** + * Performs the hardware initialization sequence when operating as a master. + * + * @param[in] p_ctrl Pointer to control structure + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS Hardware initialized with proper configurations + * @retval FSP_ERR_INVALID_RATE The requested rate cannot be set. + **********************************************************************************************************************/ +static void r_sau_i2c_open_hw_master (sau_i2c_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + R_SAU0_Type * p_reg = SAU_REG; + sau_i2c_extended_cfg_t const * const p_extend = (sau_i2c_extended_cfg_t *) p_cfg->p_extend; + sau_i2c_clock_settings_t const * const p_clock_settings = &p_extend->clock_settings; + + /* See in hardware manual: SAU > Table "Initial Setting Procedure for Simplified I2C Address Field Transmission" */ + + /* Configure the operation clock divisor based on BSP settings */ + p_reg->SPS = SAU_I2C_PRV_SPS_REG_INIT; + + /* Configure the SAU channel in Simple I2C mode */ + SAU_I2C_PRV_CHANNEL_DECLARATION; + p_reg->SMR[SAU_I2C_PRV_CHANNEL] = + ((uint16_t) (p_clock_settings->operation_clock << R_SAU0_SMR_CKS_Pos) | SAU_I2C_PRV_SMR_INIT); + + /* Set a communication format */ + p_reg->SCR[SAU_I2C_PRV_CHANNEL] = SAU_I2C_PRV_SCR_REG_INIT; + + /* Set the bit rate register SDRmn(setting the transfer clock by dividing the operating clock (fMCK)) in the hardware */ + p_reg->SDR[SAU_I2C_PRV_CHANNEL] = (uint16_t) (p_clock_settings->stclk << R_SAU0_SDR_STCLK_Pos); + + SAU_I2C_CRITICAL_SECTION_ENTER(); + + /* Set the initial output level (1) of the serial data (SOmn) and serial clock (CKOmn). */ + p_reg->SO |= (uint16_t) (SAU_I2C_PRV_SO0_REG_INIT << SAU_I2C_PRV_CHANNEL); + + SAU_I2C_CRITICAL_SECTION_EXIT(); + + R_BSP_IrqCfgEnable(p_cfg->tei_irq, p_cfg->ipl, p_ctrl); +} + +/******************************************************************************************************************//** + * Handles the STI interrupt + * + *********************************************************************************************************************/ +void sau_i2c_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sau_i2c_instance_ctrl_t * p_ctrl = (sau_i2c_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Call the handler */ + r_sau_i2c_tei_handler(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/******************************************************************************************************************//** + * Handles transmission or reception of the I2C data + * + * @note Called from ISR context + * + * @param[in] p_ctrl Pointer to transfer control block + * @param[in] p_event Pointer to transfer completion event code. Valid only if return value from this function is 1, + * indicating transfer completed successfully. + * + * @returns 1 if the transfer has completed, 0 otherwise + *********************************************************************************************************************/ +static bool r_sau_i2c_do_tx_rx (sau_i2c_instance_ctrl_t * const p_ctrl, i2c_master_event_t * const p_event) +{ + R_SAU0_Type * p_reg = SAU_REG; + SAU_I2C_PRV_CHANNEL_DECLARATION; + uint8_t data = SAU_I2C_PRV_DUMMY_WRITE_DATA_FOR_READ_OP; + bool is_rx = p_ctrl->read; + bool transfer_complete; + uint8_t * p_buff = &p_ctrl->p_buff[p_ctrl->loaded]; + + if (!is_rx && (p_ctrl->loaded < p_ctrl->total)) + { + /* Write the next data to SDR */ + data = *p_buff; + p_ctrl->loaded++; + transfer_complete = false; + } + else if (is_rx) + { + if (p_ctrl->do_dummy_read) + { + p_ctrl->do_dummy_read = false; + + /* Set operation mode to reception. It is not necessary to actually read SDR to do a dummy + * read because we were previously in transmission mode to send the slave address. */ + uint16_t scr = p_reg->SCR[SAU_I2C_PRV_CHANNEL]; + p_reg->SCR[SAU_I2C_PRV_CHANNEL] = (scr & (uint16_t) ~R_SAU0_SCR_TRXE_Msk) | SAU_I2C_PRV_SCR_RE_MASK; + +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + + /* If transfer interface is available, use it. + * Enable the transfer interfaces if the number of bytes to be read is greater than 2. + * The last two bytes will be read through interrupt, this is for support NACK before STOP. + */ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if ((NULL != p_transfer_tx) && (p_ctrl->total > 2U)) + { + r_sau_i2c_dtc_transfer_enable(p_ctrl, p_transfer_tx->p_cfg->p_info, (uint16_t) (p_ctrl->total - 2U)); + } +#endif + } + else + { + /* Read the received data into the buffer */ + *p_buff = (uint8_t) (p_reg->SDR_b[SAU_I2C_PRV_CHANNEL].DAT); + p_ctrl->loaded++; + } + + /* Check if the next byte will be the last byte */ + if ((p_ctrl->loaded + 1) == p_ctrl->total) + { + SAU_I2C_CRITICAL_SECTION_ENTER(); + + /* During a receive operation, the SOE[n] bit of serial output enable register m (SOEm) is cleared to 0 + * before receiving the last data. Refer to hardware manual: SAU > Operation of Simplified I2C > + * Figure "Timing of stop condition generation" */ + p_reg->SOE &= (uint16_t) ~(1 << SAU_I2C_PRV_CHANNEL); + + SAU_I2C_CRITICAL_SECTION_EXIT(); + } + + /* Update transfer complete after updating state since a read is complete + * after the last byte is loaded into the buffer (unlike a write, which + * is not complete until the ISR after the last byte is written to ISR) */ + transfer_complete = p_ctrl->loaded == p_ctrl->total; + *p_event = I2C_MASTER_EVENT_RX_COMPLETE; + } + else + { + /* TX completion event */ + transfer_complete = true; + *p_event = I2C_MASTER_EVENT_TX_COMPLETE; + } + + if (!transfer_complete) + { + /* A dummy byte should be written to SDR to generate SCL during reception. + * Refer to hardware manual: SAU > Operation of Simplified I2C > Table "Procedure for data reception" */ + p_reg->SDR_b[SAU_I2C_PRV_CHANNEL].DAT = data; + } + + return transfer_complete; +} + +/******************************************************************************************************************//** + * Handles the interrupt. + * + * @param[in] p_ctrl pointer to the I2C control block. + **********************************************************************************************************************/ +static void r_sau_i2c_tei_handler (sau_i2c_instance_ctrl_t * const p_ctrl) +{ + R_SAU0_Type * p_reg = SAU_REG; + SAU_I2C_PRV_CHANNEL_DECLARATION; + i2c_master_event_t event; + bool is_nack = false; + + uint16_t status = p_reg->SSR[SAU_I2C_PRV_CHANNEL]; + + /* Check if NACK was detected */ + if (R_SAU0_SSR_PEF_Msk & status) + { + /* Handle NACK */ + p_reg->SIR[SAU_I2C_PRV_CHANNEL] &= (uint16_t) ~SAU_I2C_PRV_SIR_MASK; + + event = I2C_MASTER_EVENT_ABORTED; + is_nack = true; + + /* Update internal state to reflect transfer complete */ + p_ctrl->loaded = p_ctrl->total; + } + +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + + /* This is the first interrupt after the completion of DTC operation, ignore it */ + else if (p_ctrl->activation_on_txi) + { + p_ctrl->activation_on_txi = false; + + return; + } +#endif + else + { + bool transfer_complete = r_sau_i2c_do_tx_rx(p_ctrl, &event); + + if (!transfer_complete) + { + + /* Transfer still in-progress */ + return; + } + } + + /* If we didn't return early (due to transfer still in progress), finish + * the transfer and notify the user of transfer completion */ + r_sau_i2c_transfer_complete(p_ctrl, is_nack, event); +} + +/*******************************************************************************************************************//** + * This function starts/restarts the IIC condition. + * + * @param[in] p_ctrl Instance control structure. + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_Start (sau_i2c_instance_ctrl_t * const p_ctrl) +{ + SAU_I2C_CRITICAL_SECTION_ENTER(); + R_SAU0_Type * p_reg = SAU_REG; + SAU_I2C_PRV_CHANNEL_DECLARATION; + +#if SAU_I2C_CFG_RESTART_ENABLE + if (p_ctrl->restarted) + { + /* Writing 1 to the STmn bit to stop operation */ + p_reg->ST = (uint16_t) (1 << SAU_I2C_PRV_CHANNEL); + + /* Disable IIC output */ + p_reg->SOE &= (uint16_t) ~(1 << SAU_I2C_PRV_CHANNEL); + + /* Set IIC SCL */ + p_reg->SO |= (uint16_t) (SAU_I2C_SO_SCL_HIGH << SAU_I2C_PRV_CHANNEL); + + p_ctrl->restarted = false; + } +#endif + + /* Clear IIC SDA */ + p_reg->SO &= (uint16_t) ~(SAU_I2C_SO_SDA_HIGH << SAU_I2C_PRV_CHANNEL); + + SAU_I2C_CRITICAL_SECTION_EXIT(); + + /* Set delay time before setting SCL. Refer to hardware manual: SAU > Operation of Simplified I2C > + * Table "Procedure for simplified I2C address field transmission" */ + sau_i2c_extended_cfg_t const * const p_extend = (sau_i2c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + R_BSP_SoftwareDelay(p_extend->delay_time, BSP_DELAY_UNITS_MICROSECONDS); + +#if SAU_I2C_CFG_CRITICAL_SECTION_ENABLE + FSP_CRITICAL_SECTION_ENTER; +#endif + + /* Clear IIC SCL */ + p_reg->SO &= (uint16_t) ~(SAU_I2C_SO_SCL_HIGH << SAU_I2C_PRV_CHANNEL); + + /* Enable IIC output */ + p_reg->SOE |= (1 << SAU_I2C_PRV_CHANNEL); + + /* Enable IIC */ + p_reg->SS |= (1 << SAU_I2C_PRV_CHANNEL); + + SAU_I2C_CRITICAL_SECTION_EXIT(); + + /* Set the address byte according to a 7-bit slave address */ + uint8_t slave_address = (uint8_t) ((p_ctrl->slave << 1U) | (uint8_t) p_ctrl->read); + + /* Write slave address to data register to start the transfer */ + p_reg->SDR_b[SAU_I2C_PRV_CHANNEL].DAT = slave_address; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function generates the I2C stop condition + * + * @param[in] p_ctrl Instance control structure. + **********************************************************************************************************************/ +static void r_sau_i2c_hw_stop (sau_i2c_instance_ctrl_t * const p_ctrl) +{ +#if -1 != SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_SAU0_Type * p_reg = SAU_REG; + SAU_I2C_PRV_CHANNEL_DECLARATION; + + SAU_I2C_CRITICAL_SECTION_ENTER(); + + /* See in hardware manual: SAU > Operation of Simplified I2C > Table "Procedure for stop condition generation" */ + + /* Writing 1 to the STmn bit to stop operation */ + p_reg->ST = (uint16_t) (1 << SAU_I2C_PRV_CHANNEL); + + /* Disable IIC output */ + p_reg->SOE &= (uint16_t) ~(1 << SAU_I2C_PRV_CHANNEL); + + /* Clear SDA and set SCL */ + p_reg->SO &= (uint16_t) ~(SAU_I2C_SO_SDA_HIGH << SAU_I2C_PRV_CHANNEL); + + p_reg->SO |= (uint16_t) (SAU_I2C_SO_SCL_HIGH << SAU_I2C_PRV_CHANNEL); + + SAU_I2C_CRITICAL_SECTION_EXIT(); + +#if !SAU_I2C_CFG_MANUAL_START_STOP_ENABLE + + /* Delay the required wait time, then release SDA to send the I2C + * stop condition, unless manual start/stop is enabled. */ + (void) R_SAU_I2C_Stop(p_ctrl); +#endif +} + +/*******************************************************************************************************************//** + * This function stops the IIC condition. + * + * @param[in] p_ctrl Instance control structure. + **********************************************************************************************************************/ +fsp_err_t R_SAU_I2C_Stop (sau_i2c_instance_ctrl_t * const p_ctrl) +{ + /* Set delay time before setting SCL + * See in hardware manual: SAU > Operation of Simplified I2C > Table "Procedure for stop condition generation" */ + sau_i2c_extended_cfg_t const * const p_extend = (sau_i2c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + R_BSP_SoftwareDelay(p_extend->delay_time, BSP_DELAY_UNITS_MICROSECONDS); + + R_SAU0_Type * p_reg = SAU_REG; + SAU_I2C_PRV_CHANNEL_DECLARATION; + + SAU_I2C_CRITICAL_SECTION_ENTER(); + + /* Set IIC SDA */ + p_reg->SO |= (uint16_t) (SAU_I2C_SO_SDA_HIGH << SAU_I2C_PRV_CHANNEL); + + SAU_I2C_CRITICAL_SECTION_EXIT(); + + return FSP_SUCCESS; +} + +#if SAU_I2C_CFG_DTC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Configures SAU I2C related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to SAU I2C specific control structure + * @param[in] p_cfg Pointer to SAU I2C specific configuration structure + * + * @retval FSP_SUCCESS If configures SAU I2C related transfer drivers + * @retval FSP_ERR_ASSERTION Transfer configuration for tx/rx not proper. + **********************************************************************************************************************/ +static fsp_err_t r_sau_i2c_transfer_open (sau_i2c_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + if (NULL != p_cfg->p_transfer_tx) + { + fsp_err_t err = r_sau_i2c_transfer_configure(p_ctrl, p_cfg->p_transfer_tx); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures DTC + * @param[in] p_ctrl Pointer to I2C specific control structure + * @param[in] p_transfer Pointer to DTC instance structure + * + * @retval FSP_SUCCESS Transfer interface opened successfully + * @retval FSP_ERR_ASSERTION Transfer instance not correctly initialized (NULL pointer) + **********************************************************************************************************************/ +static fsp_err_t r_sau_i2c_transfer_configure (sau_i2c_instance_ctrl_t * p_ctrl, transfer_instance_t const * p_transfer) +{ + #if -1 != SAU_I2C_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Set default transfer info and open receive transfer module, if enabled. */ + #if (SAU_I2C_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_ctrl); + FSP_ASSERT(NULL != p_transfer->p_cfg); + #endif + R_SAU0_Type * p_reg = SAU_REG; + SAU_I2C_PRV_CHANNEL_DECLARATION; + void * sdr = (void *) &p_reg->SDR[SAU_I2C_PRV_CHANNEL]; + + /* Runtime initialization for the first transfer info in the chain transfer info list */ + transfer_info_t * p_info_rx = p_transfer->p_cfg->p_info; + p_info_rx->p_src = sdr; + + /* Runtime initialization for the second transfer info in the chain transfer info list */ + transfer_info_t * p_info_tx = p_info_rx + 1; + p_info_tx->p_dest = sdr; + + fsp_err_t err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Starts the DTC transfer + * + * @param[in] p_ctrl Transfer control block + * @param[in] p_info Pointer to transfer info to start + * @param loaded Count of data bytes already transferred + **********************************************************************************************************************/ +static void r_sau_i2c_dtc_transfer_enable (sau_i2c_instance_ctrl_t * const p_ctrl, + transfer_info_t * const p_info, + uint16_t bytes_to_transfer) +{ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + + /* Update the tracker variables */ + p_ctrl->loaded = bytes_to_transfer; + + /* Start the transfer (reconfigure can be used to enable transfers since p_info is valid) */ + p_transfer_tx->p_api->reconfigure(p_transfer_tx->p_ctrl, p_info); + + /* Mark DTC activation for TXI */ + p_ctrl->activation_on_txi = true; +} + +/******************************************************************************************************************//** + * Reconfigures the DTC for the current transfer (read or write) + * + * @param[in] p_ctrl transfer control block + **********************************************************************************************************************/ +static void r_sau_i2c_reconfigure_dtc_for_transfer (sau_i2c_instance_ctrl_t * const p_ctrl) +{ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if (NULL != p_transfer_tx) + { + transfer_info_t * p_info_tx = &(p_transfer_tx->p_cfg->p_info[1]); + uint16_t transfer_length = (uint16_t) p_ctrl->total; + + if (p_ctrl->read) + { + transfer_info_t * p_info_rx = &(p_transfer_tx->p_cfg->p_info[0]); + transfer_length -= 2; // Last 2B received handled in ISR + + /* Update the rx transfer descriptor for reading data from SDR into the buffer + * The transfer will be enabled from interrupt context after sending the address. */ + p_info_rx->p_dest = (void *) (p_ctrl->p_buff); + p_info_rx->length = transfer_length; + + /* Update the tx transfer descriptor for the dummy write */ + p_info_tx->p_src = (void *) &g_dummy_write_data_for_read_op; + p_info_tx->length = transfer_length; + p_info_tx->transfer_settings_word = SAU_I2C_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS; + } + else + { + /* Update the tx transfer descriptor for writing data from the buffer to SDR */ + p_info_tx->p_src = (void *) (p_ctrl->p_buff); + p_info_tx->length = transfer_length; + p_info_tx->transfer_settings_word = SAU_I2C_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + + /* Enable the write transfer */ + r_sau_i2c_dtc_transfer_enable(p_ctrl, p_info_tx, transfer_length); + } + } +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_lin/r_sau_lin.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_lin/r_sau_lin.c new file mode 100644 index 0000000000..391d067c29 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_lin/r_sau_lin.c @@ -0,0 +1,1451 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_sau_lin.h" +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + #include "r_icu.h" +#endif +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + #include "r_tau.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "SLIN" in ASCII. Used to determine if the control block is open for SAU LIN. */ +#define SAU_LIN_OPEN (0x534C494EU) + +/* Mask for checking valid frame identifiers */ +#define SAU_LIN_FRAME_ID_MASK (0x3FU) + +/* Number of pulse intervals required to measure the sync byte in slave mode */ +#define SAU_LIN_PULSE_INTERVAL_MAX_COUNT (5) + +/* LIN Wakeup Pattern */ +#define SAU_LIN_WAKEUP (0x80U) + +/* LIN Sync Word Pattern */ +#define SAU_LIN_SYNC (0x55U) + +/* LIN Break Field Pattern */ +#define SAU_LIN_BREAK_FIELD (0x00U) + +/* Microseconds per second */ +#define SAU_LIN_MICROSECONDS_PER_SECOND (1000000U) + +/* Number of bits to detect break field */ +#define SAU_LIN_DETECTED_BREAK_FIELD_WIDTH (11) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* LIN on SAU HAL API mapping for LIN interface */ +const lin_api_t g_lin_on_sau_lin = +{ + .open = R_SAU_LIN_Open, + .read = R_SAU_LIN_Read, + .write = R_SAU_LIN_Write, + .communicationAbort = R_SAU_LIN_CommunicationAbort, + .callbackSet = R_SAU_LIN_CallbackSet, + .close = R_SAU_LIN_Close, + .sleepEnter = R_SAU_LIN_SleepEnter, + .sleepExit = R_SAU_LIN_SleepExit, + .wakeupSend = R_SAU_LIN_WakeupSend, + .informationFrameRead = R_SAU_LIN_InformationFrameRead, // [DEPRECATED] + .startFrameWrite = R_SAU_LIN_StartFrameWrite, // [DEPRECATED] + .informationFrameWrite = R_SAU_LIN_InformationFrameWrite, // [DEPRECATED] +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/* Checksum helper functions */ +#if SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE +static uint8_t r_sau_lin_checksum_initialize(uint8_t id, lin_checksum_type_t checksum_type); +static uint8_t r_sau_lin_checksum_add_byte_to_sum(uint8_t byte, uint8_t current_sum); +static uint8_t r_sau_lin_checksum_calculate(uint8_t id, + uint8_t const * const p_data, + uint8_t num_bytes, + lin_checksum_type_t checksum_type); + +#endif + +#if (SAU_LIN_CFG_PARAM_CHECKING_ENABLE) +static fsp_err_t r_sau_lin_common_parameter_checking(sau_lin_instance_ctrl_t const * const p_ctrl); + +static fsp_err_t r_sau_lin_read_write_param_check(sau_lin_instance_ctrl_t const * const p_ctrl, + lin_transfer_params_t const * const p_transfer_params); + +#endif + +/* Transmission/reception helper functions */ +static fsp_err_t r_sau_lin_communication_abort(sau_lin_instance_ctrl_t * const p_ctrl); +static fsp_err_t r_sau_lin_frame_write(sau_lin_instance_ctrl_t * const p_ctrl, + const lin_transfer_params_t * const p_transfer_params, + uint8_t const send_header); +static void r_sau_lin_call_callback(sau_lin_instance_ctrl_t * p_ctrl, lin_event_t event); + +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE +static uint32_t r_sau_lin_uart_current_baudrate_get(const uart_instance_t * p_uart); + + #if SAU_LIN_AUTO_SYNC_SUPPORT_ENABLE +static bool r_sau_lin_verify_sync_baudrate(uint32_t current_baud, uint32_t sync_baud); + + #endif +#endif + +/* PID helper functions */ +static uint8_t r_sau_lin_pid_calculate(uint8_t id); + +static void r_sau_lin_tx_complete(sau_lin_instance_ctrl_t * const p_ctrl, sau_uart_instance_ctrl_t * const p_uart_ctrl); +static void r_sau_lin_rx_complete(sau_lin_instance_ctrl_t * const p_ctrl, sau_uart_instance_ctrl_t * const p_uart_ctrl); +static void r_sau_lin_err_complete(sau_lin_instance_ctrl_t * const p_ctrl, uart_callback_args_t const * const p_args); + +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE +static fsp_err_t r_sau_lin_set_state_active(sau_lin_instance_ctrl_t * const p_ctrl); + +void r_sau_lin_icu_callback(external_irq_callback_args_t * p_args); + +#endif + +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE +void r_sau_lin_tau_callback(timer_callback_args_t * p_args); + +#endif +void r_sau_lin_uart_callback(uart_callback_args_t * p_args); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* 1 byte "buffer" used to transmit header sync word. */ +#if SAU_LIN_CFG_MASTER_SUPPORT_ENABLE +static const uint8_t g_header_sync_word = SAU_LIN_SYNC; +static const uint8_t g_header_break_field_word = SAU_LIN_BREAK_FIELD; +#endif + +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE +static const uint8_t g_wake_up_send_word = SAU_LIN_WAKEUP; +#endif + +/*******************************************************************************************************************//** + * @addtogroup SAU_LIN + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the LIN driver channel based on the input configuration. + * + * Implements @ref lin_api_t::open. + * + * Example: + * @snippet r_sau_lin_example.c R_SAU_LIN_Open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block, configuration structure, or required dependency is NULL + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_MODE Setting not supported for selected mode + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_Open (lin_ctrl_t * const p_api_ctrl, lin_cfg_t const * const p_cfg) +{ + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; +#if (SAU_LIN_CFG_PARAM_CHECKING_ENABLE) + + /* Check for null parameters */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_callback); +#endif + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_cfg->p_extend; +#if (SAU_LIN_CFG_PARAM_CHECKING_ENABLE) + + /* Check for null parameters */ + FSP_ASSERT(NULL != p_extend); + + /* Check control block isn't already open */ + FSP_ERROR_RETURN(p_ctrl->open != SAU_LIN_OPEN, FSP_ERR_ALREADY_OPEN); + #if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + + /* Check for required modules for slave mode */ + FSP_ASSERT(NULL != p_extend->p_timer || LIN_MODE_MASTER == p_cfg->mode); + + #if SAU_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Auto Synchronization not supported in master mode */ + FSP_ERROR_RETURN((SAU_LIN_AUTO_SYNCHRONIZATION_DISABLE == p_extend->auto_synchronization) || + (LIN_MODE_SLAVE == p_cfg->mode), + FSP_ERR_INVALID_MODE); + #endif + #endif + + /* Check for required modules for both modes */ + FSP_ASSERT(NULL != p_extend->p_uart); +#endif + + /* Initialize control block */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_data = NULL; + p_ctrl->state = SAU_LIN_STATE_NONE; + + /* Open the UART driver */ + const uart_instance_t * p_uart = p_extend->p_uart; + fsp_err_t status = R_SAU_UART_Open(p_uart->p_ctrl, p_uart->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* Set the callback function and context for the UART driver */ + status = R_SAU_UART_CallbackSet(p_uart->p_ctrl, r_sau_lin_uart_callback, p_ctrl, NULL); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + const external_irq_instance_t * p_icu = p_extend->p_icu; + if (NULL != p_icu) + { + /* Critical section required because ISC register is shared with other instances. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Set IRQn input source for the wakeup signal detection */ + R_PORGA->ISC |= R_PORGA_ISC_ISC0_Msk; + + FSP_CRITICAL_SECTION_EXIT; + + /* Open the ICU driver */ + status = R_ICU_ExternalIrqOpen(p_icu->p_ctrl, p_icu->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* Set the callback function and context for the ICU driver */ + status = R_ICU_ExternalIrqCallbackSet(p_icu->p_ctrl, r_sau_lin_icu_callback, p_ctrl, NULL); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* Initialize bus state */ + status = r_sau_lin_set_state_active(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + } +#endif + +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + if (LIN_MODE_SLAVE == p_ctrl->p_cfg->mode) + { + /* Configure the TAU to detect the break field */ + const timer_instance_t * p_timer = p_extend->p_timer; + status = R_TAU_Open(p_timer->p_ctrl, p_timer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* Set the callback function and context for the TAU driver */ + status = R_TAU_CallbackSet(p_timer->p_ctrl, r_sau_lin_tau_callback, p_ctrl, NULL); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* Start the TAU */ + status = R_TAU_Start(p_timer->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + } +#endif + + /* Mark the control block as open */ + p_ctrl->open = SAU_LIN_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Begins non-blocking transmission of a LIN frame. + * + * In master mode, the LIN header (break, sync and protected identifier) is sent before the LIN data. + * - To transmit the LIN header only, set p_transfer_params->p_data to NULL. + * - To transmit both header and data, set p_transfer_params->p_data to the TX buffer to transmit. + * + * The LIN header is not transmitted in slave mode. Set p_transfer_params->p_data to the TX buffer to transmit. + * + * On successful header-only transmission completion, the callback is called with event @ref lin_event_t::LIN_EVENT_TX_HEADER_COMPLETE. + * On successful data transmission or header+data transmission completion, the callback is called with event @ref lin_event_t::LIN_EVENT_TX_DATA_COMPLETE. + * + * Implements @ref lin_api_t::write. + * + * Example: + * @snippet r_sau_lin_example.c R_SAU_LIN_Write + * + * @retval FSP_SUCCESS Data transmission started successfully. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block, transfer parameters, or tx/rx buffer is NULL, or 0 bytes length provided。 + * @retval FSP_ERR_IN_USE A transmission or reception is currently in progress. Call @ref R_SAU_LIN_CommunicationAbort + * to cancel it if desired, or wait for the current transfer operation to complete before starting a new one. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_Write (lin_ctrl_t * const p_api_ctrl, const lin_transfer_params_t * const p_transfer_params) +{ + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; + fsp_err_t status = FSP_SUCCESS; + +#if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_transfer_params); + fsp_err_t err = r_sau_lin_read_write_param_check(p_ctrl, p_transfer_params); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + uint8_t is_master_write = (LIN_MODE_MASTER == p_ctrl->p_cfg->mode); + +#if SAU_LIN_CFG_PARAM_CHECKING_ENABLE && SAU_LIN_CFG_MASTER_SUPPORT_ENABLE + + /* Check ID is at most 6 bits (only for master header transmission) */ + FSP_ERROR_RETURN((0 == (p_transfer_params->id & 0xC0)) || !is_master_write, FSP_ERR_INVALID_ARGUMENT); +#endif + +#if SAU_LIN_CFG_PARAM_CHECKING_ENABLE && SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + + /* Check p_data is not null in slave mode */ + FSP_ASSERT(NULL != p_transfer_params->p_data || is_master_write); +#endif + + status = r_sau_lin_frame_write(p_ctrl, p_transfer_params, is_master_write); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Begins non-blocking data reception to receive user specified number of bytes into destination buffer pointer. + * + * The checksum type specifies the checksum type used for validation. If a non-standard algorithm is used, + * or the application prefers to validate the checksum outside the driver, or the application prefers + * to skip checksum validation, specify @ref lin_checksum_type_t::LIN_CHECKSUM_TYPE_NONE. If checksum + * validation is skipped, the @ref lin_checksum_type_t::LIN_EVENT_ERR_INVALID_CHECKSUM event is not possible. + * When @ref lin_checksum_type_t::LIN_CHECKSUM_TYPE_NONE is used, the number of bytes specified in the receive + * buffer length will be received (the driver will not expect to receive an additional 1 checksum byte), so + * if a non-standard checksum is used, sufficient space must be allocated in the write buffer and accounted for + * in the provided length. + * + * On successful data reception, the callback is called with event @ref lin_event_t::LIN_EVENT_RX_DATA_COMPLETE. + * + * Implements @ref lin_api_t::read. + * + * Example: + * @snippet r_sau_lin_example.c R_SAU_LIN_Read + * + * @retval FSP_SUCCESS Data reception started successfully. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block, transfer parameters, or tx/rx buffer is NULL, or 0 bytes length provided, + * no header matching pid was received(only for slave mode). + * @retval FSP_ERR_IN_USE A transmission or reception is currently in progress. Call @ref R_SAU_LIN_CommunicationAbort + * to cancel it if desired, or wait for the current transfer operation to complete before starting a new one. + * + * @retval FSP_ERR_INVALID_CALL Data reception is not possible because a header frame has not been received yet (slave mode only). + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_Read (lin_ctrl_t * const p_api_ctrl, lin_transfer_params_t * const p_transfer_params) +{ + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; + fsp_err_t status; +#if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + status = r_sau_lin_read_write_param_check(p_ctrl, p_transfer_params); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + FSP_ASSERT(NULL != p_transfer_params->p_data); + + /* In slave mode, check that data reception is possible (due to successful header reception) */ + FSP_ERROR_RETURN((LIN_MODE_MASTER == p_ctrl->p_cfg->mode) || (SAU_LIN_STATE_HEADER_RECEIVED == p_ctrl->state), + FSP_ERR_INVALID_CALL); +#endif + +#if SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE + p_ctrl->checksum = 0; + p_ctrl->checksum_type = p_transfer_params->checksum_type; + p_ctrl->validate_checksum = p_transfer_params->checksum_type != LIN_CHECKSUM_TYPE_NONE; +#endif + p_ctrl->count = p_transfer_params->num_bytes; + p_ctrl->p_data = p_transfer_params->p_data; + p_ctrl->state = SAU_LIN_STATE_AWAITING_DATA; + + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + status = R_SAU_UART_Read(p_extend->p_uart->p_ctrl, p_transfer_params->p_data, p_transfer_params->num_bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Cancels in progress data read or write, or header read or write. Break field reception cannot be + * cancelled. For slave nodes, reception of a new header reception is still enabled after a call to this function. + * + * Implements @ref lin_api_t::communicationAbort. + * + * @retval FSP_SUCCESS Data transfer aborted successfully or no transfer was in progress. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block is NULL. + * @retval FSP_ERR_INVALID_STATE Driver is in bus sleep state. Call @ref R_SAU_LIN_SleepExit to return to active state or wait for wakeup signal. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_CommunicationAbort (lin_ctrl_t * const p_api_ctrl) +{ + fsp_err_t status = FSP_SUCCESS; + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; +#if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + status = r_sau_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); +#endif + + status = r_sau_lin_communication_abort(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + return status; +} + +/*******************************************************************************************************************//** + * Updates the user callback and callback context. + * @note Providing callback memory is not supported, pass NULL to this function for p_callback_memory. + * + * Implements @ref lin_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block, callback function is NULL, or p_callback_memory is not NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_STATE Driver is in bus sleep state. Call @ref R_SAU_LIN_SleepExit to return to active state or wait for wakeup signal. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_CallbackSet (lin_ctrl_t * const p_api_ctrl, + void ( * p_callback)(lin_callback_args_t *), + void * const p_context, + lin_callback_args_t * const p_callback_memory) +{ + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; + +#if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t status = r_sau_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* Check for null parameters */ + FSP_ASSERT(NULL == p_callback_memory); + FSP_ASSERT(NULL != p_callback); +#endif + FSP_PARAMETER_NOT_USED(p_callback_memory); + + p_ctrl->p_context = p_context; + p_ctrl->p_callback = p_callback; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Begins non-blocking transmission of the LIN wakeup signal. + * + * On successful wakeup signal transmission, the callback is called with event @ref lin_event_t::LIN_EVENT_TX_WAKEUP_COMPLETE. + * + * Implements @ref lin_api_t::wakeupSend. + * + * Example: + * @snippet r_sau_lin_example.c R_SAU_LIN_WakeupSend + * + * @retval FSP_SUCCESS Wakeup signal transmission successfully started. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED Unsupported when Wake-up Support build option is disabled. + * @retval FSP_ERR_INVALID_STATE Driver is in bus sleep state. Call @ref R_SAU_LIN_SleepExit to return to active state or wait for wakeup signal. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_WakeupSend (lin_ctrl_t * const p_api_ctrl) +{ +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; + + #if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t status = r_sau_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + #endif + + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + p_ctrl->state = SAU_LIN_STATE_SENDING_WAKEUP; + + return R_SAU_UART_Write(p_extend->p_uart->p_ctrl, &g_wake_up_send_word, 1); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Places the LIN node in bus sleep mode. Enables the external IRQ that can be used to detect the LIN wakeup signal. + * + * On wakeup signal reception, the callback is called with event @ref lin_event_t::LIN_EVENT_RX_WAKEUP_COMPLETE and + * bus sleep mode is automatically exited. + * + * @note This function does not put the MCU into a low power mode. Call this function prior to entering a low power mode + * to enable LIN wakeup signal detection support. + * + * Implements @ref lin_api_t::sleepEnter. + * + * Example: + * @snippet r_sau_lin_example.c R_SAU_LIN_SleepEnter + * + * @retval FSP_SUCCESS Bus successfully transitioned to sleep state. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED Unsupported when Wake-up Support build option is disabled. + * @retval FSP_ERR_INVALID_STATE Driver is in bus sleep state. Call @ref R_SAU_LIN_SleepExit to return to active state or wait for wakeup signal. + * @retval FSP_ERR_NOT_ENABLED ICU module is not enabled. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_SleepEnter (lin_ctrl_t * const p_api_ctrl) +{ +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; + fsp_err_t status; + + #if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + status = r_sau_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + #endif + + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + #if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + + /* Ensure sleep/wakeup is enabled */ + FSP_ERROR_RETURN(NULL != p_extend->p_icu, FSP_ERR_NOT_ENABLED); + #endif + + icu_instance_ctrl_t * p_icu_ctrl = (icu_instance_ctrl_t *) p_extend->p_icu->p_ctrl; + + p_ctrl->state = SAU_LIN_STATE_BUS_SLEEP; + status = R_ICU_ExternalIrqEnable(p_icu_ctrl); + + if (FSP_SUCCESS != status) + { + p_ctrl->state = SAU_LIN_STATE_NONE; + } + + return status; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Exits the bus sleep mode for LIN device. Disables wakeup signal detection. + * + * Implements @ref lin_api_t::sleepExit. + * + * @retval FSP_SUCCESS Bus successfully transitioned to active state + * @retval FSP_ERR_ASSERTION Pointer to LIN control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED Unsupported when Wake-up Support build option is disabled. + * @retval FSP_ERR_NOT_ENABLED ICU module is not enabled. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_SleepExit (lin_ctrl_t * const p_api_ctrl) +{ +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + fsp_err_t status = FSP_SUCCESS; + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; + + #if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SAU_LIN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + FSP_ERROR_RETURN(NULL != p_extend->p_icu, FSP_ERR_NOT_ENABLED); + #endif + + status = r_sau_lin_set_state_active(p_ctrl); + + return status; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Closes the LIN driver. + * + * Implements @ref lin_api_t::close. + * + * Example: + * @snippet r_sau_lin_example.c R_SAU_LIN_Close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_Close (lin_ctrl_t * const p_api_ctrl) +{ + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; +#if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SAU_LIN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + const external_irq_instance_t * p_icu = p_extend->p_icu; + if (NULL != p_icu) + { + /* Critical section required because ISC register is shared with other instances. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Restore IRQn input source */ + R_PORGA->ISC &= (uint8_t) ~R_PORGA_ISC_ISC0_Msk; + + FSP_CRITICAL_SECTION_EXIT; + + /* Close the ICU driver */ + R_ICU_ExternalIrqClose(p_icu->p_ctrl); + } +#endif + +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + if (LIN_MODE_SLAVE == p_ctrl->p_cfg->mode) + { + /* Close the TAU driver */ + const timer_instance_t * p_timer = p_extend->p_timer; + R_TAU_Close(p_timer->p_ctrl); + } +#endif + + /* Close the UART driver */ + R_SAU_UART_Close(p_extend->p_uart->p_ctrl); + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * DEPRECATED. Use @ref R_SAU_LIN_Read. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_InformationFrameRead (lin_ctrl_t * const p_api_ctrl, + lin_transfer_params_t * const p_transfer_params) +{ + return R_SAU_LIN_Read(p_api_ctrl, p_transfer_params); +} + +/*******************************************************************************************************************//** + * [DEPRECATED] Use @ref R_SAU_LIN_Write + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_StartFrameWrite (lin_ctrl_t * const p_api_ctrl, uint8_t const id) +{ +#if SAU_LIN_CFG_MASTER_SUPPORT_ENABLE + lin_transfer_params_t params = + { + .id = id, + .p_data = NULL, + .num_bytes = 0, + .checksum_type = LIN_CHECKSUM_TYPE_NONE, + }; + + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; + fsp_err_t status; + #if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + status = r_sau_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* Check ID is at most 6 bits */ + FSP_ERROR_RETURN(0 == (id & 0xC0), FSP_ERR_INVALID_ARGUMENT); + + /* Function only supported for master mode */ + FSP_ERROR_RETURN(LIN_MODE_MASTER == p_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); + FSP_ERROR_RETURN(SAU_LIN_STATE_NONE == p_ctrl->state, FSP_ERR_IN_USE); + #endif + + status = r_sau_lin_frame_write(p_ctrl, ¶ms, true); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(id); + + return FSP_ERR_INVALID_MODE; +#endif +} + +/*******************************************************************************************************************//** + * [DEPRECATED] Use @ref R_SAU_LIN_Write + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_SAU_LIN_InformationFrameWrite (lin_ctrl_t * const p_api_ctrl, + const lin_transfer_params_t * const p_transfer_params) +{ + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_api_ctrl; + fsp_err_t status = FSP_SUCCESS; + +#if SAU_LIN_CFG_PARAM_CHECKING_ENABLE + + /* Common parameter checking */ + status = r_sau_lin_read_write_param_check(p_ctrl, p_transfer_params); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + FSP_ASSERT(NULL != p_transfer_params->p_data); +#endif + + status = r_sau_lin_frame_write(p_ctrl, p_transfer_params, false); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SAU_LIN) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (SAU_LIN_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Verifies the control structure is not NULL and the module is open. This reduces code size when parameter checking is + * enabled. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * + * @retval FSP_SUCCESS No error detected. + * @retval FSP_ERR_ASSERTION NULL input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_STATE Driver is in bus sleep state. Call @ref R_SAU_LIN_SleepExit to return to active state or wait for wakeup signal. + **********************************************************************************************************************/ +static fsp_err_t r_sau_lin_common_parameter_checking (sau_lin_instance_ctrl_t const * const p_ctrl) +{ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SAU_LIN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(SAU_LIN_STATE_BUS_SLEEP != p_ctrl->state, FSP_ERR_INVALID_STATE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Parameter error check function for R_SAU_LIN_Write and R_SAU_LIN_Read + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] p_transfer_params Pointer to the transfer parameters for the transfer + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A transmission or reception is currently in progress. Call R_SAU_LIN_CommunicationAbort + * to cancel it if desired, or wait for the current transfer operation to complete before starting a new one. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block, transfer parameters, or tx/rx buffer is NULL, or 0 bytes length provided + * @retval FSP_ERR_INVALID_STATE Driver is in bus sleep state. Call @ref R_SAU_LIN_SleepExit to return to active state or wait for wakeup signal. + **********************************************************************************************************************/ +static fsp_err_t r_sau_lin_read_write_param_check (sau_lin_instance_ctrl_t const * const p_ctrl, + lin_transfer_params_t const * const p_transfer_params) +{ + fsp_err_t status = r_sau_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + FSP_ASSERT(NULL != p_transfer_params); + + /* Number of bytes and checksum parameters are only checked for data transfers */ + if (NULL != p_transfer_params->p_data) + { + FSP_ASSERT(p_transfer_params->num_bytes > 0); + FSP_ASSERT(((p_transfer_params->num_bytes < UINT8_MAX) || + (LIN_CHECKSUM_TYPE_NONE == p_transfer_params->checksum_type))); + } + + /* Cannot start read/write when another write is in progress */ + FSP_ERROR_RETURN((SAU_LIN_STATE_NONE == p_ctrl->state) || (SAU_LIN_STATE_HEADER_RECEIVED == p_ctrl->state), + FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Calculates the protected identifier. + * + * Implements the algorithm according to LIN Protocol Specification Rev. 2.2A pg.53. + * + * The PID is an 8 bit field: [p1 p0 id5 id4 id3 id2 id1 id0]. + * P1 is bit 7 and is calculated as id1 XOR id3 XOR id4 XOR id5. + * P0 is bit 6 and is calculated as id0 XOR id1 XOR ix2 XOR id4. + * + * @param[in] id LIN unprotected frame identifier + * + * @retval LIN protected frame identifier result + **********************************************************************************************************************/ +static uint8_t r_sau_lin_pid_calculate (uint8_t id) +{ + /* ID is 6 bits */ + uint8_t pid = id & SAU_LIN_FRAME_ID_MASK; + + /* P0 = id0 ^ id1 ^ id2 ^ id4*/ + uint8_t tmp = (((id >> 0) ^ (id >> 1) ^ (id >> 2) ^ (id >> 4)) & 0x01); + pid |= (uint8_t) (tmp << 6U); + + /* P1 = ~(id1 ^ id3 ^ id4 ^ id5) */ + tmp = (uint8_t) ~(((id >> 1) ^ (id >> 3) ^ (id >> 4) ^ (id >> 5)) & 0x01); + pid |= (uint8_t) (tmp << 7U); + + return pid; +} + +#if SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Add byte to checksum + * + * @param[in] byte Byte to add to current sum + * @param[in] current_sum Current checksum (intermediate sum) + * + * @retval New checksum result (after adding byte) + **********************************************************************************************************************/ +static uint8_t r_sau_lin_checksum_add_byte_to_sum (uint8_t byte, uint8_t current_sum) +{ + uint16_t new_sum = current_sum; + + new_sum += byte; + + /* LIN Protocol Specification Rev. 2.2A pg.32 section 2.3.1.5: + * 8-bit sum with carry is equivalent to sum all values and subtract + * 255 every time the sum is greater than or equal to 256 */ + if (new_sum > UINT8_MAX) + { + new_sum -= UINT8_MAX; + } + + return (uint8_t) new_sum; +} + +/*******************************************************************************************************************//** + * Initialize the checksum based on the checksum type + * + * @param[in] id LIN unprotected frame identifier + * @param[in] checksum_type Checksum type (classic or enhanced) + * + * @retval Initial checksum value for the provided checksum type + **********************************************************************************************************************/ +static uint8_t r_sau_lin_checksum_initialize (uint8_t id, lin_checksum_type_t checksum_type) +{ + uint8_t checksum = 0; + + if (LIN_CHECKSUM_TYPE_ENHANCED == checksum_type) + { + /* Compute PID and add to checksum. Enhanced checksum includes data and PID. Standard is data only. */ + checksum = r_sau_lin_pid_calculate(id); + } + + return checksum; +} + +/*******************************************************************************************************************//** + * Calculates the LIN checksum on data to be transmitted. For received frames, + * the checksum is calculated at the end of the reception. + * + * @param[in] id LIN unprotected frame identifier. + * @param[in] p_data Pointer to frame data. + * @param[in] num_bytes Frame data length. + * @param[in] checksum_type Checksum type (classic or enhanced). Frame ID 0x3C and 0x3D always use classic checksum. + * + * @retval LIN checksum result + **********************************************************************************************************************/ +static uint8_t r_sau_lin_checksum_calculate (uint8_t id, + uint8_t const * const p_data, + uint8_t num_bytes, + lin_checksum_type_t checksum_type) +{ + uint8_t checksum = r_sau_lin_checksum_initialize(id, checksum_type); + + for (uint8_t i = 0; i < num_bytes; i++) + { + checksum = r_sau_lin_checksum_add_byte_to_sum(p_data[i], checksum); + } + + return (uint8_t) ~checksum; +} + +#endif + +/*******************************************************************************************************************//** + * Transmit the LIN frame + * + * @param[in] p_ctrl Pointer to driver control block + * @param[in] p_transfer_params Pointer to the transfer parameters for the transfer + * @param[in] send_header Set to true if the LIN header should be transmitted before the data (master mode only) + * + * @retval FSP_SUCCESS Transmission started successfully + * @retval FSP_ERR_ASSERTION The new SDR register setting will exceed the register upper limit, + * please increase the baud rate or adjust the clock setting first. + * **********************************************************************************************************************/ +static fsp_err_t r_sau_lin_frame_write (sau_lin_instance_ctrl_t * const p_ctrl, + const lin_transfer_params_t * const p_transfer_params, + uint8_t const send_header) +{ + fsp_err_t status = FSP_SUCCESS; + uint8_t * p_data = p_transfer_params->p_data; + uint8_t num_bytes = p_transfer_params->num_bytes; + +#if SAU_LIN_CFG_MASTER_SUPPORT_ENABLE + if (p_data) +#endif + { +#if SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE + p_ctrl->validate_checksum = p_transfer_params->checksum_type != LIN_CHECKSUM_TYPE_NONE; + + if (p_ctrl->validate_checksum) + { + /* If checksum generation is enabled, calculate the checksum */ + p_ctrl->checksum = r_sau_lin_checksum_calculate(p_transfer_params->id, + p_data, + num_bytes, + p_transfer_params->checksum_type); + } +#endif + p_ctrl->p_data = p_data; + p_ctrl->count = num_bytes; + p_ctrl->state = SAU_LIN_STATE_SENDING_DATA; + } + + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + sau_uart_instance_ctrl_t * p_uart_ctrl = (sau_uart_instance_ctrl_t *) p_extend->p_uart->p_ctrl; + +#if SAU_LIN_CFG_MASTER_SUPPORT_ENABLE + if (send_header) + { + /* Configure the baud rate for sending the break field */ + status = R_SAU_UART_BaudSet(p_uart_ctrl, p_extend->p_break_field_baudrate); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + + /* Calculation and set protected identifier */ + p_ctrl->last_pid = r_sau_lin_pid_calculate(p_transfer_params->id); + + p_ctrl->state = SAU_LIN_STATE_SENDING_BREAK_FIELD; + p_data = (uint8_t *) &g_header_break_field_word; + num_bytes = 1; + } + +#else + FSP_PARAMETER_NOT_USED(send_header); +#endif + + status = R_SAU_UART_Write(p_uart_ctrl, p_data, num_bytes); + + return status; +} + +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Place the LIN bus in the active state by disabling wakeup interrupt + * + * @param[in] p_ctrl Pointer to driver control block + * + * @retval FSP_SUCCESS Transmission started successfully + **********************************************************************************************************************/ +static fsp_err_t r_sau_lin_set_state_active (sau_lin_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t status = FSP_SUCCESS; + + /* Disable IRQ interrupt */ + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + const external_irq_instance_t * p_icu = p_extend->p_icu; + status = R_ICU_ExternalIrqDisable(p_icu->p_ctrl); + p_ctrl->state = SAU_LIN_STATE_NONE; + + return status; +} + +#endif + +/*******************************************************************************************************************//** + * Abort communication + * + * @param[in] p_ctrl Pointer to driver control block + * + * @retval FSP_SUCCESS Communication aborted successfully + **********************************************************************************************************************/ +static fsp_err_t r_sau_lin_communication_abort (sau_lin_instance_ctrl_t * const p_ctrl) +{ + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + fsp_err_t status = R_SAU_UART_Abort(p_extend->p_uart->p_ctrl, UART_DIR_RX_TX); + FSP_ERROR_RETURN(FSP_SUCCESS == status, status); + p_ctrl->p_data = NULL; + p_ctrl->state = SAU_LIN_STATE_NONE; + p_ctrl->count = 0; + + return status; +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to LIN instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sau_lin_call_callback (sau_lin_instance_ctrl_t * p_ctrl, lin_event_t event) +{ + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + sau_uart_instance_ctrl_t * p_uart_ctrl = p_extend->p_uart->p_ctrl; + uint8_t received_bytes = (uint8_t) (p_ctrl->count - p_uart_ctrl->rx_count); + + lin_callback_args_t args; + + args.channel = 0; // not used for SAU LIN + args.event = event; + args.pid = p_ctrl->last_pid; + args.p_context = p_ctrl->p_context; + args.checksum = p_ctrl->checksum; + args.bytes_received = received_bytes; + + p_ctrl->p_callback(&args); +} + +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Callback function called in the ICU driver callback function when LIN is used. + * + * @param[in] p_args ICU callback parameters + * + * @retval none + **********************************************************************************************************************/ +void r_sau_lin_icu_callback (external_irq_callback_args_t * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); + + /* Recover ISR context saved in open. */ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + icu_instance_ctrl_t * p_icu_ctrl = (icu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_icu_ctrl->p_context; + + r_sau_lin_set_state_active(p_ctrl); + + r_sau_lin_call_callback(p_ctrl, LIN_EVENT_RX_WAKEUP_COMPLETE); +} + +#endif + +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * TAU driver callback function. + * + * Handles break field detection and baud rate adjustment during sync byte measurement. + * + * @param[in] p_args TAU callback parameters + * + * @retval none + **********************************************************************************************************************/ +void r_sau_lin_tau_callback (timer_callback_args_t * p_args) +{ + if (TIMER_EVENT_CAPTURE_EDGE == p_args->event) + { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + tau_instance_ctrl_t * p_tau_ctrl = (tau_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_tau_ctrl->p_context; + sau_lin_extended_cfg_t const * const p_extend = (sau_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + uint32_t current_baud = r_sau_lin_uart_current_baudrate_get(p_extend->p_uart); + + #if SAU_LIN_AUTO_SYNC_SUPPORT_ENABLE + if ((SAU_LIN_AUTO_SYNCHRONIZATION_ENABLE == p_extend->auto_synchronization) && + (SAU_LIN_STATE_AWAITING_SYNC_SIGNAL == p_ctrl->state)) + { + /* Ignore the first measurement, refer to hardware manual: SAU > Operation of LIN Communication > + * LIN Reception > Figure "Flowchart of LIN reception" */ + if ((0 < p_ctrl->sync_bits_received) && (SAU_LIN_PULSE_INTERVAL_MAX_COUNT > p_ctrl->sync_bits_received)) + { + p_ctrl->sync_bits_sum += p_args->capture; + } + + p_ctrl->sync_bits_received++; + + if (SAU_LIN_PULSE_INTERVAL_MAX_COUNT == p_ctrl->sync_bits_received) + { + uint32_t sync_baud = (p_extend->timer_clock_frequency / p_ctrl->sync_bits_sum) * 8; + sau_uart_instance_ctrl_t * p_uart_ctrl = p_extend->p_uart->p_ctrl; + sau_uart_extended_cfg_t * p_uart_extend = (sau_uart_extended_cfg_t *) p_uart_ctrl->p_cfg->p_extend; + + if ((r_sau_lin_verify_sync_baudrate(current_baud, sync_baud)) && + (FSP_SUCCESS == R_SAU_UART_BaudCalculate(p_uart_ctrl, sync_baud, p_uart_extend->p_baudrate))) + { + R_SAU_UART_BaudSet(p_uart_ctrl, p_uart_extend->p_baudrate); + p_ctrl->state = SAU_LIN_STATE_AWAITING_PID_SIGNAL; + R_SAU_UART_Read(p_uart_ctrl, &p_ctrl->last_pid, 1); + } + else + { + p_ctrl->state = SAU_LIN_STATE_NONE; + } + + R_TAU_LinMeasurementFuncSwitch(p_tau_ctrl, TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT); + } + } + else + #endif + { + uint32_t break_field_threshold_ticks = + (SAU_LIN_DETECTED_BREAK_FIELD_WIDTH * p_extend->timer_clock_frequency) / current_baud; + + /* If the detected pulse width is 11 bits or more, it is judged as the break field. + * See in hardware manual: SAU > Operation of LIN Communication > LIN Reception */ + if (p_args->capture >= break_field_threshold_ticks) + { + p_ctrl->state = SAU_LIN_STATE_AWAITING_SYNC_SIGNAL; + + #if SAU_LIN_AUTO_SYNC_SUPPORT_ENABLE + if (SAU_LIN_AUTO_SYNCHRONIZATION_ENABLE == p_extend->auto_synchronization) + { + p_ctrl->sync_bits_sum = 0; + p_ctrl->sync_bits_received = 0; + + R_TAU_LinMeasurementFuncSwitch(p_tau_ctrl, TAU_FUNCTION_INPUT_PULSE_INTERVAL_MEASUREMENT); + } + else + #endif + { + sau_uart_instance_ctrl_t * p_uart_ctrl = p_extend->p_uart->p_ctrl; + R_SAU_UART_Read(p_uart_ctrl, &p_ctrl->last_pid, 1); + } + } + } + } +} + + #if SAU_LIN_AUTO_SYNC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Helper function to verify synchronization baudrate. + * + * @param[in] current_baud Baudrate before synchronization + * @param[in] sync_baud Baudrate measured by TAU after synchronization + * + * @return 1 if the sync baudrate within +-12.5% of baudrate before synchronization, 0 otherwise + **********************************************************************************************************************/ +static bool r_sau_lin_verify_sync_baudrate (uint32_t current_baud, uint32_t sync_baud) +{ + /* Compute absolute value of difference in bit duration */ + uint32_t delta = current_baud > sync_baud ? (current_baud - sync_baud) : (sync_baud - current_baud); + + /* Check that measured baudrate is within 12.5% of the current baudrate */ + uint32_t threshold = (current_baud >> 3U); + + return delta <= threshold; +} + + #endif + +/*******************************************************************************************************************//** + * Helper function to calculate the baud rate. + * + * @param[in] p_uart UART instance control + * + * @return Baud rate [bps]. + **********************************************************************************************************************/ +static uint32_t r_sau_lin_uart_current_baudrate_get (const uart_instance_t * p_uart) +{ + sau_uart_extended_cfg_t * p_uart_extend = (sau_uart_extended_cfg_t *) p_uart->p_cfg->p_extend; + + uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK); + uint32_t fmck_clock = peripheral_clock >> p_uart_extend->p_baudrate->prs; + + /* (Baud rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn.STCLK[6:0] + 1) ÷ 2 [bps] */ + return (fmck_clock / (p_uart_extend->p_baudrate->stclk + 1)) >> 1; +} + +#endif + +/*******************************************************************************************************************//** + * UART receive complete processing. + * + * @param[in] p_ctrl LIN instance control + * @param[in] p_uart_ctrl UART instance control + * + * @retval none + **********************************************************************************************************************/ +static void r_sau_lin_rx_complete (sau_lin_instance_ctrl_t * const p_ctrl, sau_uart_instance_ctrl_t * const p_uart_ctrl) +{ + lin_event_t event = LIN_EVENT_NONE; + + if (SAU_LIN_STATE_AWAITING_CHECKSUM == p_ctrl->state) + { +#if SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE + if (p_ctrl->validate_checksum) + { + uint8_t sum = r_sau_lin_checksum_calculate(p_ctrl->last_pid, + p_ctrl->p_data, + p_ctrl->count, + p_ctrl->checksum_type); + + /* Validate checksum. At this point, p_ctrl->checksum contains the checksum over the data bytes. */ + event = + (sum == p_ctrl->checksum) ? LIN_EVENT_RX_DATA_COMPLETE : LIN_EVENT_ERR_INVALID_CHECKSUM; + p_ctrl->p_data = NULL; + p_ctrl->state = SAU_LIN_STATE_NONE; + } + +#else + FSP_PARAMETER_NOT_USED(p_uart_ctrl); +#endif + } + else if (SAU_LIN_STATE_AWAITING_DATA == p_ctrl->state) + { +#if SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE + if (p_ctrl->validate_checksum) + { + R_SAU_UART_Read(p_uart_ctrl, &p_ctrl->checksum, 1); + + p_ctrl->state = SAU_LIN_STATE_AWAITING_CHECKSUM; + + /* Since the checksum data has not yet been received, the callback call is not required now. */ + return; + } +#endif + event = LIN_EVENT_RX_DATA_COMPLETE; + p_ctrl->p_data = NULL; + p_ctrl->state = SAU_LIN_STATE_NONE; + } + +#if SAU_LIN_CFG_SLAVE_SUPPORT_ENABLE + else if (SAU_LIN_STATE_AWAITING_PID_SIGNAL == p_ctrl->state) + { + uint8_t pid = p_ctrl->last_pid; + + if (r_sau_lin_pid_calculate(pid) != pid) + { + p_ctrl->state = SAU_LIN_STATE_NONE; + event = LIN_EVENT_ERR_PARITY; + } + else + { + p_ctrl->state = SAU_LIN_STATE_HEADER_RECEIVED; + event = LIN_EVENT_RX_HEADER_COMPLETE; + } + } + else if (SAU_LIN_STATE_AWAITING_SYNC_SIGNAL == p_ctrl->state) + { + p_ctrl->state = SAU_LIN_STATE_AWAITING_PID_SIGNAL; + R_SAU_UART_Read(p_uart_ctrl, &p_ctrl->last_pid, 1); + } +#endif + else + { + + /* No conditions are met. */ + return; + } + + if (event) + { + /* Call user callback */ + r_sau_lin_call_callback(p_ctrl, event); + } +} + +/*******************************************************************************************************************//** + * UART transmit complete processing. + * + * @param[in] p_ctrl LIN instance control + * @param[in] p_uart_ctrl UART instance control + * + * @retval none + **********************************************************************************************************************/ +static void r_sau_lin_tx_complete (sau_lin_instance_ctrl_t * const p_ctrl, sau_uart_instance_ctrl_t * const p_uart_ctrl) +{ + lin_event_t event = LIN_EVENT_NONE; + + switch (p_ctrl->state) + { +#if SAU_LIN_CFG_WAKEUP_SUPPORT_ENABLE + case SAU_LIN_STATE_SENDING_WAKEUP: + { + FSP_PARAMETER_NOT_USED(p_uart_ctrl); + event = LIN_EVENT_TX_WAKEUP_COMPLETE; + + break; + } +#endif +#if SAU_LIN_CFG_MASTER_SUPPORT_ENABLE + case SAU_LIN_STATE_SENDING_BREAK_FIELD: + { + sau_uart_extended_cfg_t * p_uart_extend = (sau_uart_extended_cfg_t *) p_uart_ctrl->p_cfg->p_extend; + R_SAU_UART_BaudSet(p_uart_ctrl, p_uart_extend->p_baudrate); + + p_ctrl->state = SAU_LIN_STATE_SENDING_SYNC; + R_SAU_UART_Write(p_uart_ctrl, &g_header_sync_word, 1); + + break; + } + + case SAU_LIN_STATE_SENDING_SYNC: + { + p_ctrl->state = SAU_LIN_STATE_SENDING_PID; + R_SAU_UART_Write(p_uart_ctrl, &(p_ctrl->last_pid), 1); + + break; + } + + case SAU_LIN_STATE_SENDING_PID: + { + if (p_ctrl->p_data) + { + p_ctrl->state = SAU_LIN_STATE_SENDING_DATA; + R_SAU_UART_Write(p_uart_ctrl, p_ctrl->p_data, p_ctrl->count); + } + else + { + event = LIN_EVENT_TX_HEADER_COMPLETE; + } + + break; + } +#endif + case SAU_LIN_STATE_SENDING_DATA: + { +#if SAU_LIN_CFG_CHECKSUM_SUPPORT_ENABLE + if (p_ctrl->validate_checksum) + { + p_ctrl->validate_checksum = false; + R_SAU_UART_Write(p_uart_ctrl, &p_ctrl->checksum, 1); + + /* Since the checksum data has not yet been sent, the callback call is not required now. */ + break; + } +#endif + FSP_PARAMETER_NOT_USED(p_uart_ctrl); + p_ctrl->p_data = NULL; + event = LIN_EVENT_TX_DATA_COMPLETE; + + break; + } + + default: + { + break; + } + } + + if (event) + { + /* Reset state */ + p_ctrl->state = SAU_LIN_STATE_NONE; + + /* Call user callback */ + r_sau_lin_call_callback(p_ctrl, event); + } +} + +/*******************************************************************************************************************//** + * UART transfer error processing. + * + * @param[in] p_args UART callback parameters + * @param[in] p_ctrl LIN instance control + * + * @retval none + **********************************************************************************************************************/ +static void r_sau_lin_err_complete (sau_lin_instance_ctrl_t * const p_ctrl, uart_callback_args_t const * const p_args) +{ + lin_event_t event = LIN_EVENT_NONE; + + if (UART_EVENT_ERR_OVERFLOW == p_args->event) + { + event = LIN_EVENT_ERR_OVERRUN; + } + else if (UART_EVENT_ERR_FRAMING == p_args->event) + { + if ((p_ctrl->state <= SAU_LIN_STATE_AWAITING_SYNC_SIGNAL) || (NULL == p_ctrl->p_data)) + { + + /* In the break field signal phase, LIN will have a frame error exception that does not require a callback call. */ + return; + } + + event = LIN_EVENT_ERR_FRAMING; + } + else + { + /* No handler. */ + } + + if (event) + { + /* Stop reception */ + r_sau_lin_communication_abort(p_ctrl); + + /* Call user callback */ + r_sau_lin_call_callback(p_ctrl, event); + } +} + +/*******************************************************************************************************************//** + * Callback function called in the UART driver callback function when LIN is used. + * + * @param[in] p_args UART callback parameters + * + * @retval none + **********************************************************************************************************************/ +void r_sau_lin_uart_callback (uart_callback_args_t * p_args) +{ + /* Recover ISR context saved in open. */ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sau_uart_instance_ctrl_t * p_uart_ctrl = (sau_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + sau_lin_instance_ctrl_t * p_ctrl = (sau_lin_instance_ctrl_t *) p_uart_ctrl->p_context; + + if (UART_EVENT_RX_COMPLETE == p_args->event) + { + r_sau_lin_rx_complete(p_ctrl, p_uart_ctrl); + } + else if (UART_EVENT_TX_COMPLETE == p_args->event) + { + r_sau_lin_tx_complete(p_ctrl, p_uart_ctrl); + } + else if (UART_EVENT_RX_CHAR == p_args->event) + { + /* No handle for rx char data */ + } + else + { + r_sau_lin_err_complete(p_ctrl, p_args); + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_spi/r_sau_spi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_spi/r_sau_spi.c new file mode 100644 index 0000000000..0c4c88d466 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_spi/r_sau_spi.c @@ -0,0 +1,1305 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sau_spi.h" +#include "r_sau_spi_cfg.h" +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + #include "r_dtc.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define R_SAU0_SCR_DCP1_Pos (13U) +#define SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_CHAIN_MODE_EACH << \ + TRANSFER_SETTINGS_CHAIN_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SAU_SPI_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_CHAIN_MODE_DISABLED << \ + TRANSFER_SETTINGS_CHAIN_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_CHAIN_MODE_DISABLED << \ + TRANSFER_SETTINGS_CHAIN_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SAU_REG_SIZE (R_SAU1_BASE - R_SAU0_BASE) +#define SAU_SPI_SMR_INIT_VALUE (0x0020U) +#define SAU_SPI_SCR_INIT_VALUE (0x0007U | \ + (SAU_SPI_TRANSFER_OPERATION_MODE << R_SAU0_SCR_TRXE_Pos)) +#define SAU0_SPS_REG_INIT ((BSP_CFG_SAU_CK01_DIV << R_SAU0_SPS_PRS1_Pos) | \ + BSP_CFG_SAU_CK00_DIV) +#define SAU1_SPS_REG_INIT ((BSP_CFG_SAU_CK11_DIV << R_SAU0_SPS_PRS1_Pos) | \ + BSP_CFG_SAU_CK10_DIV) + +#define SAU_SPI_PSR_MIN_DIV_2 (2U) +#define SAU_SPI_PSR_MIN_DIV_4 (4U) +#define SAU_SPI_SDR_STCLK_MAX_DIV (256U) +#define SAU_SPI_PSR_MAX_DIV (32768U) +#define R_SAU_SDR_DUMMY_DATA (0xFFU) +#define SAU_SPI_STCLK_MAX (127) + +#if 0 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI00 used (Unit 0 Channel 0) */ + #define SAU_SPI_PRV_CHANNEL (0) + #define SAU_SPI_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) +#elif 1 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI01 used (Unit 0 Channel 1) */ + #define SAU_SPI_PRV_CHANNEL (1) + #define SAU_SPI_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) +#elif 10 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI10 used (Unit 0 Channel 2) */ + #define SAU_SPI_PRV_CHANNEL (2) + #define SAU_SPI_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) +#elif 11 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI11 used (Unit 0 Channel 3) */ + #define SAU_SPI_PRV_CHANNEL (3) + #define SAU_SPI_PRV_UNIT (0) + #define SAU_REG (R_SAU0) + #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) +#elif 20 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI20 used (Unit 1 Channel 0) */ + #define SAU_SPI_PRV_CHANNEL (0) + #define SAU_SPI_PRV_UNIT (1) + #define SAU_REG (R_SAU1) + #define SAU_SPS_REG_INIT (SAU1_SPS_REG_INIT) +#elif 21 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Only SPI21 used (Unit 1 Channel 1) */ + #define SAU_SPI_PRV_CHANNEL (1) + #define SAU_SPI_PRV_UNIT (1) + #define SAU_REG (R_SAU1) + #define SAU_SPS_REG_INIT (SAU1_SPS_REG_INIT) +#endif + +#if -1 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE /* Single channel configuration disabled. */ + #define SAU_REG (p_ctrl->p_reg) + #define SAU_SPI_PRV_UNIT (p_extend->sau_unit) + #define SAU_SPI_PRV_CHANNEL_DECLARATION uint8_t channel = p_ctrl->p_cfg->channel + #define SAU_SPI_PRV_CHANNEL (channel) + #define SAU_SPS_REG_INIT (SAU_SPI_PRV_UNIT ? SAU1_SPS_REG_INIT : SAU0_SPS_REG_INIT) +#else + #define SAU_SPI_PRV_CHANNEL_DECLARATION +#endif + +/** "SAU" in ASCII, used to determine if channel is open. */ +#define SAU_SPI_OPEN (0x53415553ULL) + +/*********************************************************************************************************************** + * Private global variables. + **********************************************************************************************************************/ + +const spi_api_t g_spi_on_sau = +{ + .open = R_SAU_SPI_Open, + .read = R_SAU_SPI_Read, + .write = R_SAU_SPI_Write, + .writeRead = R_SAU_SPI_WriteRead, + .close = R_SAU_SPI_Close, + .callbackSet = R_SAU_SPI_CallbackSet +}; + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function declarations. + **********************************************************************************************************************/ + +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE == 1 + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION || \ + SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION + +/* constant used as the source location for the DTC dummy write */ +static const uint8_t g_dummy_write_data_for_read_op = R_SAU_SDR_DUMMY_DATA; + #endif +static fsp_err_t r_sau_spi_transfer_config(sau_spi_instance_ctrl_t * const p_ctrl); +static void r_sau_spi_reconfigure_for_transfer(sau_spi_instance_ctrl_t * const p_ctrl, uint8_t const length); + + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION +static uint8_t dummy_rx; + #endif +#endif +static void r_sau_spi_hw_config(sau_spi_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_sau_spi_write_read_common(sau_spi_instance_ctrl_t * const p_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); +static void r_sau_spi_start_transfer(sau_spi_instance_ctrl_t * const p_ctrl); + +#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION || \ + SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION +static void r_sau_spi_transmit(sau_spi_instance_ctrl_t * p_ctrl); + +#endif +#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION || \ + SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION +static void r_sau_spi_receive(sau_spi_instance_ctrl_t * p_ctrl); + +#endif +static void r_sau_spi_call_callback(sau_spi_instance_ctrl_t * p_ctrl, spi_event_t event); + +#if (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION) +static void r_sau_spi_do_transmission(sau_spi_instance_ctrl_t * p_ctrl); + +#elif (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION) +static void r_sau_spi_do_reception(sau_spi_instance_ctrl_t * p_ctrl); + +#else +static void r_sau_spi_do_transmission_reception(sau_spi_instance_ctrl_t * p_ctrl); + +#endif +#if SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE +static void r_sau_spi_reset_pin(sau_spi_instance_ctrl_t * p_ctrl, bool reset); + +#endif +void sau_spi_txrxi_isr(void); + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup SAU_SPI + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize a channel for SPI communication mode. Implements @ref spi_api_t::open. + * + * This function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Enables the clock for the SAU channel. + * - Initializes the associated registers with default value and the user-configurable options. + * - Provides the channel handle for use with other API functions. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_cfg Pointer to a configuration structure. + * + * @retval FSP_SUCCESS Channel initialized successfully. + * @retval FSP_ERR_ASSERTION An input parameter is invalid or NULL. + * @retval FSP_ERR_ALREADY_OPEN The instance has already been opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel number is invalid. + **********************************************************************************************************************/ +fsp_err_t R_SAU_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; +#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); +#endif + +#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SAU_SPI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(p_cfg->tei_irq >= 0); +#endif + sau_spi_extended_cfg_t const * const p_extend = (sau_spi_extended_cfg_t *) p_cfg->p_extend; +#if -1 == SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE + #ifdef R_SAU1 + p_ctrl->p_reg = ((R_SAU0_Type *) (R_SAU0_BASE + (SAU_REG_SIZE * SAU_SPI_PRV_UNIT))); + #else + p_ctrl->p_reg = R_SAU0; + #endif +#endif + p_ctrl->p_cfg = p_cfg; + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->transfer_in_progress = false; + +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE == 1 + + /* Open the SAU SPI transfer interface if available. */ + err = r_sau_spi_transfer_config(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Enable Clock for the SAU Channel. */ + R_BSP_MODULE_START(FSP_IP_SAU, SAU_SPI_PRV_UNIT); + + /* Write user configuration to registers. */ + r_sau_spi_hw_config(p_ctrl); + + /* Enable required interrupts. */ + R_BSP_IrqCfgEnable(p_cfg->tei_irq, p_cfg->tei_ipl, p_ctrl); + + p_ctrl->open = SAU_SPI_OPEN; + + /* Set SCK pin to input in slave mode by clearing PDR. */ + if (SPI_MODE_SLAVE == p_cfg->operating_mode) + { + R_BSP_PinAccessEnable(); + R_BSP_PinCfg(p_extend->sck_pin_settings.pin, + (uint32_t) (p_extend->sck_pin_settings.cfg & ~R_PFS_PORT_PIN_PmnPFS_PDR_Msk)); + R_BSP_PinAccessDisable(); + } + +#if SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE + r_sau_spi_reset_pin(p_ctrl, true); +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Receive data from an SPI device. Implements @ref spi_api_t::read. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Enable transmitter. + * - Enable receiver. + * - Enable interrupts. + * - Start data transmission by writing data to the TXD register. + * - Receive data from receive buffer full interrupt occurs and copy data to the buffer of destination. + * - Complete data reception via receive buffer full interrupt and transmitting dummy data. + * - Disable transmitter. + * - Disable receiver. + * - Disable interrupts. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_dest Pointer to the destination buffer. + * @param[in] length The number of bytes to transfer. + * @param[in] bit_width Data frame length (Set to SPI_BIT_WIDTH_7_BITS or SPI_BIT_WIDTH_8_BITS). + * + * @retval FSP_SUCCESS Read operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_api_ctrl is NULL + * - Bit width is not 8 bits + * - Length is equal to 0 + * - Pointer to destination is NULL + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_UNSUPPORTED The given bit_width is not supported. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * - @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +fsp_err_t R_SAU_SPI_Read (spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SAU_SPI_TRANSFER_OPERATION_MODE != SAU_SPI_TRANSFER_MODE_TRANSMISSION + #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + + /* Check the destination, should not be NULL. */ + FSP_ASSERT(NULL != p_dest); + #endif + sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; + + return r_sau_spi_write_read_common(p_ctrl, NULL, p_dest, length, bit_width); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(length); + FSP_PARAMETER_NOT_USED(bit_width); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmit data to a SPI device. Implements @ref spi_api_t::write. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Enable transmitter. + * - Enable interrupts. + * - Start data transmission with data via transmit buffer empty interrupt. + * - Copy data from source buffer to the SPI data register for transmission. + * - Complete data transmission via transmit buffer empty interrupt. + * - Disable transmitter. + * - Disable receiver. + * - Disable interrupts. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_src Pointer to the source buffer. + * @param[in] length The number of bytes to transfer. + * @param[in] bit_width Data frame length (Set to SPI_BIT_WIDTH_7_BITS or SPI_BIT_WIDTH_8_BITS). + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_api_ctrl is NULL + * - Pointer to source is NULL + * - Length is equal to 0 + * - Bit width is not equal to 8 bits + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_UNSUPPORTED The given bit_width is not supported. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * - @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +fsp_err_t R_SAU_SPI_Write (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SAU_SPI_TRANSFER_OPERATION_MODE != SAU_SPI_TRANSFER_MODE_RECEPTION + #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_src); + #endif + sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; + #if SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE + r_sau_spi_reset_pin(p_ctrl, false); + #endif + + return r_sau_spi_write_read_common(p_ctrl, p_src, NULL, length, bit_width); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(length); + FSP_PARAMETER_NOT_USED(bit_width); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Simultaneously transmit data to SPI device while receiving data from SPI device (full duplex). + * Implements @ref spi_api_t::writeRead. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Enable transmitter. + * - Enable receiver. + * - Enable interrupts. + * - Start data transmission using transmit buffer empty interrupt (or by writing to the TDR register). + * - Copy data from source buffer to the SPI data register for transmission. + * - Receive data from receive buffer full interrupt and copy data to the destination buffer. + * - Complete data transmission and reception via transmit end interrupt. + * - Disable transmitter. + * - Disable receiver. + * - Disable interrupts. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_src Pointer to the source buffer. + * @param p_dest Pointer to the destination buffer. + * @param[in] length The number of bytes to transfer. + * @param[in] bit_width Data frame length (Set to SPI_BIT_WIDTH_7_BITS or SPI_BIT_WIDTH_8_BITS). + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_api_ctrl is NULL + * - Pointer to source is NULL + * - Pointer to destination is NULL + * - Length is equal to 0 + * - Bit width is not equal to 8 bits + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_UNSUPPORTED The given bit_width is not supported. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * - @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +fsp_err_t R_SAU_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION + #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); + #endif + sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; + + #if SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE + r_sau_spi_reset_pin(p_ctrl, false); + #endif + + return r_sau_spi_write_read_common(p_ctrl, p_src, p_dest, length, bit_width); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(length); + FSP_PARAMETER_NOT_USED(bit_width); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements spi_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SAU_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory) +{ + sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; + +#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SAU_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_PARAMETER_NOT_USED(p_callback_memory); + + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable the SAU channel and set the instance as not open. Implements @ref spi_api_t::close. + * + * @param p_api_ctrl Pointer to an opened instance. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION The parameter p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + **********************************************************************************************************************/ +fsp_err_t R_SAU_SPI_Close (spi_ctrl_t * const p_api_ctrl) +{ + sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) p_api_ctrl; + +#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SAU_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + /* Clear the RE and TE bits in SCR. */ + SAU_REG->SCR[SAU_SPI_PRV_CHANNEL] = 0; + +#if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; +#endif + SAU_REG->ST |= (uint16_t) (1 << SAU_SPI_PRV_CHANNEL); + SAU_REG->SOE &= (uint16_t) ~(1 << SAU_SPI_PRV_CHANNEL); +#if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE + FSP_CRITICAL_SECTION_EXIT; +#endif + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + + p_ctrl->open = 0U; + +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculate the register settings required to achieve the desired bitrate. + * + * @note This function calculates the bitrate settings with both operation clocks CK0 and CK1, then selects the operation + * clock and register setting combination that would produce the lowest error. + * + * @param[in] bitrate bitrate [bps]. For example, 250,000; 500,00; 16,000,000 (max), etc. + * @param[out] sclk_div Pointer to sau_spi_div_setting_t used to configure baudrate settings. + * @param sau_unit SAU unit. + * @param channel SAU channel. + * + * @retval FSP_SUCCESS Bitrate is calculated successfully. + * @retval FSP_ERR_ASSERTION Bitrate is not achievable or not valid for the selected unit/channel. + **********************************************************************************************************************/ +fsp_err_t R_SAU_SPI_CalculateBitrate (uint32_t bitrate, + sau_spi_div_setting_t * sclk_div, + uint8_t sau_unit, + uint8_t channel) +{ + uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK); + +#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != sclk_div); + FSP_ASSERT(bitrate); + if ((0 == sau_unit) && (0 == channel)) + { + FSP_ASSERT(bitrate <= peripheral_clock / SAU_SPI_PSR_MIN_DIV_2); + } + else + { + FSP_ASSERT(bitrate <= peripheral_clock / SAU_SPI_PSR_MIN_DIV_4); + } + + FSP_ASSERT(bitrate >= peripheral_clock / SAU_SPI_SDR_STCLK_MAX_DIV / SAU_SPI_PSR_MAX_DIV); +#else + FSP_PARAMETER_NOT_USED(channel); +#endif + uint32_t best_delta_error = UINT32_MAX; + +#if SAU_SPI_CFG_SINGLE_CHANNEL_ENABLE != -1 + const uint32_t sps = SAU_SPS_REG_INIT; + FSP_PARAMETER_NOT_USED(sau_unit); +#else + const uint32_t sps = sau_unit ? SAU1_SPS_REG_INIT : SAU0_SPS_REG_INIT; +#endif + + /* Calculate settings twice, once for CK0 and once for CK1, selecting the result with the lowest error */ + for (uint8_t prs_shift = 0; prs_shift <= R_SAU0_SPS_PRS1_Pos; prs_shift += R_SAU0_SPS_PRS1_Pos) + { + uint8_t prs = (sps >> prs_shift) & R_SAU0_SPS_PRS0_Msk; + + /* To get the stclk divider calculate the divisor to apply to ICLK. There's a built in div/2. */ + const uint32_t divisor = bitrate << (prs + 1); + + /* Calculate stclk register value: STCLK = (f_mck / (2*bitrate)) - 1 */ + const uint32_t stclk = (peripheral_clock + (divisor >> 1)) / divisor - 1; + + /* Get the actual bitrate given the current settings. + * peripheral_clock / 2^prs / (2 * (stclk + 1)) */ + const uint32_t actual_bitrate = (peripheral_clock >> (prs + 1)) / (stclk + 1); + uint32_t delta_error = bitrate > actual_bitrate ? bitrate - actual_bitrate : actual_bitrate - bitrate; + + /* Keep settings which are valid and provide the lowest error. */ + if ((stclk <= SAU_SPI_STCLK_MAX) && (delta_error < best_delta_error)) + { + best_delta_error = delta_error; + sclk_div->stclk = (uint8_t) stclk; + sclk_div->operation_clock = (sau_spi_operation_clock_t) (prs_shift == R_SAU0_SPS_PRS1_Pos); + } + } + + /* Return an error if no valid STCLK setting was found with either operation clock */ + FSP_ERROR_RETURN(best_delta_error != UINT32_MAX, FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SAU_SPI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures SAU registers based on the user configuration. + * @param p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_sau_spi_hw_config (sau_spi_instance_ctrl_t * const p_ctrl) +{ + spi_cfg_t const * p_cfg = p_ctrl->p_cfg; + sau_spi_extended_cfg_t * p_extend = (sau_spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + R_SAU0_Type * p_reg = SAU_REG; + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + /* Initialize registers to their reset values. */ + uint16_t smr = SAU_SPI_SMR_INIT_VALUE; + uint16_t scr = SAU_SPI_SCR_INIT_VALUE; + + /* Write settings that are common to master and slave mode. */ +#if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + smr |= ((uint16_t) (p_cfg->operating_mode << R_SAU0_SMR_CCS_Pos) | + (uint16_t) (p_extend->transfer_mode << R_SAU0_SMR_MD0_Pos)); +#else + smr |= (uint16_t) (p_cfg->operating_mode << R_SAU0_SMR_CCS_Pos); +#endif + scr |= (uint16_t) (p_extend->data_phase << R_SAU0_SCR_DCP1_Pos) | + (uint16_t) (p_extend->clock_phase << R_SAU0_SCR_DCP_Pos) | + (uint16_t) (p_cfg->bit_order << R_SAU0_SCR_DIR_Pos); + +#if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE + + /* Enter critical section when modifying registers that are shared between channels (SPS, SS, SO, SOE). */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; +#endif + + uint16_t so = p_reg->SO; + uint16_t sdr = 0; + + if (SPI_MODE_MASTER == p_cfg->operating_mode) + { + /* Write settings that are only used in master mode. */ + p_reg->SPS = SAU_SPS_REG_INIT; + + smr |= (uint16_t) (p_extend->clk_div.operation_clock << R_SAU0_SMR_CKS_Pos); + sdr = (uint16_t) (p_extend->clk_div.stclk << R_SAU0_SDR_STCLK_Pos); + + if (SAU_SPI_CLOCK_PHASE_REVERSE == p_extend->clock_phase) + { + so &= (uint16_t) ~(1 << (R_SAU0_SO_CKO_Pos + SAU_SPI_PRV_CHANNEL)); + } + else + { + so |= (uint16_t) (1 << (R_SAU0_SO_CKO_Pos + SAU_SPI_PRV_CHANNEL)); + } + } + else + { + /* Write settings that are only used in slave mode. */ + if ((0 == SAU_SPI_PRV_UNIT) && (0 == SAU_SPI_PRV_CHANNEL)) + { + /* Enable IRQ0 pin as an external interrupt for SAU unit 0 channel 0. */ + R_PORGA->ISC_b.SSIE00 = 1U; + } + } + +#if SAU_SPI_TRANSFER_OPERATION_MODE != SAU_SPI_TRANSFER_MODE_RECEPTION + + /* Set initial serial output data to 0 if transmit is enabled. */ + so &= (uint16_t) ~(1 << SAU_SPI_PRV_CHANNEL); + + /* Only enable serial output if transmit is enabled. */ + p_reg->SOE |= (uint16_t) (1 << (SAU_SPI_PRV_CHANNEL)); +#endif + + p_reg->SMR[SAU_SPI_PRV_CHANNEL] = smr; + p_reg->SCR[SAU_SPI_PRV_CHANNEL] = scr; + p_reg->SDR[SAU_SPI_PRV_CHANNEL] = sdr; + p_reg->SO = so; + + SAU_REG->SS = (uint16_t) (1 << (SAU_SPI_PRV_CHANNEL)); + +#if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE == 1 + +/*******************************************************************************************************************//** + * Configures SAU SPI related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to the control structure. + * + * @retval FSP_SUCCESS Operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_cfg is NULL + * - Interrupt is not enabled + * @retval FSP_ERR_INVALID_ARGUMENT DTC is used for data transmission but not used for data reception or + * vice versa. + **********************************************************************************************************************/ +static fsp_err_t r_sau_spi_transfer_config (sau_spi_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + spi_cfg_t const * const p_cfg = p_ctrl->p_cfg; + + /* Set default transfer info and open receive transfer module, if enabled. */ + #if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg->p_transfer_tx->p_api); + FSP_ASSERT(NULL != p_cfg->p_transfer_tx->p_ctrl); + FSP_ASSERT(NULL != p_cfg->p_transfer_tx->p_cfg); + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION + transfer_info_t * p_info_rx = &(p_cfg->p_transfer_tx->p_cfg->p_info[0]); + transfer_info_t * p_info_tx = &(p_cfg->p_transfer_tx->p_cfg->p_info[1]); + + /* Set the initial configuration for the rx transfer instance. */ + p_info_rx->transfer_settings_word = SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_info_rx->p_src = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + + /* Set the initial configuration for the tx transfer instance. */ + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_info_tx->p_dest = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION + transfer_info_t * p_info_tx = &(p_cfg->p_transfer_tx->p_cfg->p_info[1]); + + /* Set the initial configuration for the tx transfer instance. */ + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_info_tx->p_dest = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION + transfer_info_t * p_info_rx = &(p_cfg->p_transfer_tx->p_cfg->p_info[0]); + transfer_info_t * p_info_tx = &(p_cfg->p_transfer_tx->p_cfg->p_info[1]); + if (SPI_MODE_MASTER == p_cfg->operating_mode) + { + p_info_rx->transfer_settings_word = SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_info_rx->p_src = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + + /* Set the initial configuration for the tx transfer instance. */ + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_info_tx->p_dest = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + } + else + { + /* Set the initial configuration for the tx transfer instance. */ + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS; + p_info_tx->p_src = (void *) (&(SAU_REG->SDR[p_cfg->channel])); + } + #endif + err = p_cfg->p_transfer_tx->p_api->open(p_cfg->p_transfer_tx->p_ctrl, p_cfg->p_transfer_tx->p_cfg); + + return err; +} + +/******************************************************************************************************************//** + * Reconfigure the address mode for transfer interface + * + * @param[in] p_ctrl Pointer to the control structure. + * @param[in] p_cfg Pointer to a configuration structure. + * @param[in] length Number of data already transferred. + **********************************************************************************************************************/ +static void r_sau_spi_reconfigure_for_transfer (sau_spi_instance_ctrl_t * const p_ctrl, uint8_t const length) +{ + spi_cfg_t const * const p_cfg = p_ctrl->p_cfg; + + transfer_instance_t const * p_transfer = p_cfg->p_transfer_tx; + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION + transfer_info_t * p_info_tx = &(p_transfer->p_cfg->p_info[1]); + p_info_tx->length = (uint16_t) (p_ctrl->count - length); + p_info_tx->p_src = p_ctrl->p_src + length; + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info_tx); + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION + SAU_SPI_PRV_CHANNEL_DECLARATION; + + transfer_info_t * p_info_rx = &(p_transfer->p_cfg->p_info[0]); + transfer_info_t * p_info_tx = &(p_transfer->p_cfg->p_info[1]); + p_info_tx->length = (uint16_t) (p_ctrl->count - length); + + if (SPI_MODE_MASTER == p_cfg->operating_mode) + { + p_info_rx->p_dest = p_ctrl->p_dest; + p_info_tx->p_src = (void *) &g_dummy_write_data_for_read_op; + p_info_tx->p_dest = (void *) &(SAU_REG->SDR[SAU_SPI_PRV_CHANNEL]); + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info_rx); + } + else + { + /* Configure the tx transfer instance. */ + p_info_tx->p_src = (void *) &(SAU_REG->SDR[SAU_SPI_PRV_CHANNEL]); + p_info_tx->transfer_settings_word = SAU_SPI_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS; + p_info_tx->p_dest = p_ctrl->p_dest; + + /* Enable the transfer instance. */ + p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info_tx); + } + #endif + #if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION + transfer_info_t * p_info_rx = &(p_transfer->p_cfg->p_info[0]); + transfer_info_t * p_info_tx = &(p_transfer->p_cfg->p_info[1]); + p_info_tx->length = (uint16_t) (p_ctrl->count - length); + if (NULL == p_ctrl->p_dest) + { + p_info_rx->p_dest = &dummy_rx; + p_info_rx->transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info_tx->p_src = p_ctrl->p_src + length; + } + else if (NULL == p_ctrl->p_src) + { + p_info_rx->p_dest = p_ctrl->p_dest; + p_info_rx->transfer_settings_word = SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_info_tx->p_src = (void *) &g_dummy_write_data_for_read_op; + } + else + { + p_info_rx->p_dest = p_ctrl->p_dest; + p_info_rx->transfer_settings_word = SAU_SPI_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_info_tx->p_src = p_ctrl->p_src + length; + } + p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_info_rx); + #endif + p_ctrl->activation_on_tei = true; +} + +#endif + +/*******************************************************************************************************************//** + * Initiates write or read process. Common routine used by SPI API write or read functions. + * + * @param[in] p_ctrl Pointer to the control block. + * @param[in] p_src Pointer to data buffer which need to be sent. + * @param[out] p_dest Pointer to buffer where received data will be stored. + * @param[in] length Number of data transactions to be performed. + * @param[in] bit_width Data frame length (Set to SPI_BIT_WIDTH_7_BITS or SPI_BIT_WIDTH_8_BITS). + * + * @retval FSP_SUCCESS Operation successfully completed. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_ctrl is NULL + * - length == 0 + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * - @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +static fsp_err_t r_sau_spi_write_read_common (sau_spi_instance_ctrl_t * const p_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SAU_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SAU_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(0 != length); + FSP_ERROR_RETURN((SPI_BIT_WIDTH_8_BITS == bit_width) || (SPI_BIT_WIDTH_7_BITS == bit_width), FSP_ERR_UNSUPPORTED); + + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + + /* DTC on RX could actually receive 65535+3 = 65538 bytes as 3 bytes are handled separately. + * Forcing to 65535 to keep TX and RX uniform with respect to max transaction length via DTC. + */ + FSP_ASSERT(length <= UINT16_MAX); + #endif +#endif + + FSP_ERROR_RETURN(p_ctrl->transfer_in_progress == false, FSP_ERR_IN_USE); + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + /* Writing to SCR is prohibited while the channel is enabled. If the bit width is changed, disable communication + * before writing to SCR. See in hardware manual: SAU > Register Descriptions > SCRm0 */ + SAU_REG->ST = (uint16_t) (1 << SAU_SPI_PRV_CHANNEL); + + /* Bit width is configured in SCR::DLS[1:0]: + * - 7bit: 0b10 + * - 8bit: 0b11 + */ + uint16_t tmp = SAU_REG->SCR[SAU_SPI_PRV_CHANNEL]; + SAU_REG->SCR[SAU_SPI_PRV_CHANNEL] = (uint16_t) (tmp & (uint16_t) ~1) | (SPI_BIT_WIDTH_8_BITS == bit_width); + + SAU_REG->SS = (uint16_t) (1 << SAU_SPI_PRV_CHANNEL); +#if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + sau_spi_extended_cfg_t * p_extend = (sau_spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + tmp = SAU_REG->SMR[SAU_SPI_PRV_CHANNEL]; + if (SAU_SPI_TRANSFER_MODE_CONTINUOUS == p_extend->transfer_mode) + { + tmp &= (uint16_t) ~R_SAU0_SMR_MD0_Msk; + + /* Continuous mode can be used only when length > 1. When DTC is enabled, the length needs to be greater than 2. */ + if (2 < length) + { + tmp |= (uint16_t) R_SAU0_SMR_MD0_Msk; + } + + SAU_REG->SMR[SAU_SPI_PRV_CHANNEL] = tmp; + } +#endif + + /* Setup the control block. */ + p_ctrl->count = length; + p_ctrl->tx_count = 0U; + p_ctrl->rx_count = 0U; + p_ctrl->p_src = (uint8_t *) p_src; + p_ctrl->p_dest = (uint8_t *) p_dest; +#if SAU_SPI_CFG_DTC_SUPPORT_ENABLE == 1 + p_ctrl->activation_on_tei = false; + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + if ((1 < length) && !(tmp & (SAU_SPI_TRANSFER_MODE_CONTINUOUS << R_SAU0_SMR_MD0_Pos))) + #else + if (1 < length) + #endif + { + r_sau_spi_reconfigure_for_transfer(p_ctrl, 1); + } +#endif + + /* Enable transmit and receive interrupts. */ + r_sau_spi_start_transfer(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Start transmit data Settings. + * + * @param p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_sau_spi_start_transfer (sau_spi_instance_ctrl_t * const p_ctrl) +{ + p_ctrl->transfer_in_progress = true; +#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + spi_cfg_t const * p_cfg = p_ctrl->p_cfg; + if (SPI_MODE_MASTER == p_cfg->operating_mode) + { + /* start receive by dummy write */ + SAU_REG->SDR[SAU_SPI_PRV_CHANNEL] = R_SAU_SDR_DUMMY_DATA; + } + +#else + + /* When transmitting from the TXRXI interrupt, the first byte must be written here because the transmit buffer + * empty IRQ is disabled. */ + r_sau_spi_transmit(p_ctrl); +#endif +} + +#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION || \ + SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION + +/*******************************************************************************************************************//** + * Transmit a single byte of data. + * @param p_ctrl Pointer to the control structure. + **********************************************************************************************************************/ +static void r_sau_spi_transmit (sau_spi_instance_ctrl_t * p_ctrl) +{ + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + uint16_t dat = p_ctrl->p_src ? p_ctrl->p_src[p_ctrl->tx_count] : R_SAU_SDR_DUMMY_DATA; + SAU_REG->SDR[SAU_SPI_PRV_CHANNEL] = dat; + + p_ctrl->tx_count++; +} + +#endif + +#if SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION || \ + SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION_RECEPTION + +/*******************************************************************************************************************//** + * The receive buffer is read the data register. + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_sau_spi_receive (sau_spi_instance_ctrl_t * p_ctrl) +{ + spi_cfg_t const * p_cfg = p_ctrl->p_cfg; + uint8_t dat = (uint8_t) (SAU_REG->SDR[p_cfg->channel] & R_SAU_SDR_DUMMY_DATA); + if (p_ctrl->p_dest) + { + p_ctrl->p_dest[p_ctrl->rx_count] = dat; + } + + p_ctrl->rx_count++; +} + +#endif + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SPI instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sau_spi_call_callback (sau_spi_instance_ctrl_t * p_ctrl, spi_event_t event) +{ + spi_callback_args_t args; + + args.channel = p_ctrl->p_cfg->channel; + args.event = event; + args.p_context = p_ctrl->p_context; + + p_ctrl->p_callback(&args); +#if SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE + r_sau_spi_reset_pin(p_ctrl, true); +#endif +} + +/*******************************************************************************************************************//** + * This function is the ISR handler for R_SAU_SPI Transmit End IRQ. + * + * The Transmit End IRQ is enabled after the last byte of data has been transferred. + * + **********************************************************************************************************************/ +void sau_spi_txrxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sau_spi_instance_ctrl_t * p_ctrl = (sau_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + uint16_t err_type = SAU_REG->SSR[SAU_SPI_PRV_CHANNEL] & R_SAU0_SSR_OVF_Msk; + if (err_type) + { + SAU_REG->SIR[SAU_SPI_PRV_CHANNEL] = err_type; + r_sau_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); + } + else + { +#if (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION) + r_sau_spi_do_reception(p_ctrl); +#elif (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION) + r_sau_spi_do_transmission(p_ctrl); +#else + r_sau_spi_do_transmission_reception(p_ctrl); +#endif + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#if (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_RECEPTION) +static void r_sau_spi_do_reception (sau_spi_instance_ctrl_t * p_ctrl) +{ + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + uint16_t smr = SAU_REG->SMR[SAU_SPI_PRV_CHANNEL]; + uint8_t continuous_transfer = smr & R_SAU0_SMR_MD0_Msk; + #endif + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + if (true == p_ctrl->activation_on_tei) + { + p_ctrl->activation_on_tei = false; + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + p_ctrl->rx_count = p_ctrl->count - 1 - continuous_transfer; + #else + p_ctrl->rx_count = p_ctrl->count - 1; + #endif + p_ctrl->tx_count = p_ctrl->count; + + return; + } + #endif + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + if (continuous_transfer) + { + if (0 == p_ctrl->tx_count) + { + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + r_sau_spi_reconfigure_for_transfer(p_ctrl, 2); + #endif + SAU_REG->SDR_b[SAU_SPI_PRV_CHANNEL].DAT = R_SAU_SDR_DUMMY_DATA; + p_ctrl->tx_count++; + } + else + { + r_sau_spi_receive(p_ctrl); + if (p_ctrl->rx_count < (p_ctrl->count - 1U)) + { + SAU_REG->SDR[SAU_SPI_PRV_CHANNEL] = R_SAU_SDR_DUMMY_DATA; + } + else if (p_ctrl->rx_count == (p_ctrl->count - 1U)) + { + smr &= (uint16_t) ~SAU_SPI_TRANSFER_MODE_CONTINUOUS; + SAU_REG->SMR[SAU_SPI_PRV_CHANNEL] = smr; + } + else + { + r_sau_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + p_ctrl->transfer_in_progress = false; + } + } + } + else + #endif + { + r_sau_spi_receive(p_ctrl); + if (p_ctrl->rx_count == p_ctrl->count) + { + r_sau_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + p_ctrl->transfer_in_progress = false; + } + else + { + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) + { + SAU_REG->SDR[SAU_SPI_PRV_CHANNEL] = R_SAU_SDR_DUMMY_DATA; + } + } + } +} + +#elif (SAU_SPI_TRANSFER_OPERATION_MODE == SAU_SPI_TRANSFER_MODE_TRANSMISSION) +static void r_sau_spi_do_transmission (sau_spi_instance_ctrl_t * p_ctrl) +{ + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + uint16_t smr = SAU_REG->SMR[SAU_SPI_PRV_CHANNEL]; + uint8_t continuous_transfer = smr & R_SAU0_SMR_MD0_Msk; + #endif + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + if (true == p_ctrl->activation_on_tei) + { + p_ctrl->activation_on_tei = false; + p_ctrl->tx_count = p_ctrl->count; + + return; + } + + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + if (continuous_transfer) + { + if (1U == p_ctrl->tx_count) + { + r_sau_spi_reconfigure_for_transfer(p_ctrl, 2); + } + } + #endif + #endif + if (p_ctrl->tx_count < p_ctrl->count) + { + r_sau_spi_transmit(p_ctrl); + } + + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + else if (continuous_transfer) + { + smr &= (uint16_t) ~SAU_SPI_TRANSFER_MODE_CONTINUOUS; + SAU_REG->SMR[SAU_SPI_PRV_CHANNEL] = smr; + } + #endif + else + { + r_sau_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + p_ctrl->transfer_in_progress = false; + } +} + +#else +static void r_sau_spi_do_transmission_reception (sau_spi_instance_ctrl_t * p_ctrl) +{ + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + uint16_t smr = SAU_REG->SMR[SAU_SPI_PRV_CHANNEL]; + uint8_t continuous_transfer = smr & R_SAU0_SMR_MD0_Msk; + #endif + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + if (true == p_ctrl->activation_on_tei) + { + p_ctrl->activation_on_tei = false; + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + p_ctrl->rx_count = p_ctrl->count - 1 - continuous_transfer; + #else + p_ctrl->rx_count = p_ctrl->count - 1; + #endif + p_ctrl->tx_count = p_ctrl->count; + + return; + } + #endif + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + if (continuous_transfer) + { + if (1U < p_ctrl->tx_count) + { + r_sau_spi_receive(p_ctrl); + } + + #if SAU_SPI_CFG_DTC_SUPPORT_ENABLE + else + { + r_sau_spi_reconfigure_for_transfer(p_ctrl, 2); + } + #endif + } + else + #endif + { + r_sau_spi_receive(p_ctrl); + } + + if (p_ctrl->tx_count < p_ctrl->count) + { + r_sau_spi_transmit(p_ctrl); + } + + #if SAU_SPI_TRANSFER_MODE_CONTINUOUS_ENABLE + else if (continuous_transfer) + { + /* 2nd to last byte */ + smr &= (uint16_t) ~SAU_SPI_TRANSFER_MODE_CONTINUOUS; + SAU_REG->SMR[SAU_SPI_PRV_CHANNEL] = smr; + } + #endif + else + { + /* last byte */ + r_sau_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + p_ctrl->transfer_in_progress = false; + } +} + +#endif + +#if SAU_SPI_CFG_MULTIPLE_SLAVE_COMPATIBILITY_MODE_ENABLE + +/*******************************************************************************************************************//** + * Reset SO pin setting. + * + * @param[in] p_ctrl Pointer to the control structure. + * @param[in] reset Reset SO pin. + **********************************************************************************************************************/ +static void r_sau_spi_reset_pin (sau_spi_instance_ctrl_t * p_ctrl, bool reset) +{ + spi_cfg_t const * p_cfg = p_ctrl->p_cfg; + if (SPI_MODE_SLAVE == p_cfg->operating_mode) + { + sau_spi_extended_cfg_t * p_extend = (sau_spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* If single channel is disabled, then save the channel number on the stack. */ + SAU_SPI_PRV_CHANNEL_DECLARATION; + + #if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + #endif + if (true == reset) + { + SAU_REG->SOE &= (uint16_t) ~(1 << SAU_SPI_PRV_CHANNEL); + } + else + { + SAU_REG->SOE |= (uint16_t) (1 << SAU_SPI_PRV_CHANNEL); + } + + #if SAU_SPI_CFG_CRITICAL_SECTION_ENABLE + FSP_CRITICAL_SECTION_EXIT; + #endif + R_BSP_PinAccessEnable(); + R_BSP_PinCfg(p_extend->so_pin_settings.pin, + reset ? ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) : p_extend->so_pin_settings.cfg); + R_BSP_PinAccessDisable(); + } +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_uart/r_sau_uart.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_uart/r_sau_uart.c new file mode 100644 index 0000000000..5def288eeb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sau_uart/r_sau_uart.c @@ -0,0 +1,1380 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sau_uart.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef SAU_UART_CFG_RX_ENABLE + #define SAU_UART_CFG_RX_ENABLE 1 +#endif +#ifndef SAU_UART_CFG_TX_ENABLE + #define SAU_UART_CFG_TX_ENABLE 1 +#endif + +#define SAU0_SPS_REG_INIT ((BSP_CFG_SAU_CK01_DIV << R_SAU0_SPS_PRS1_Pos) | BSP_CFG_SAU_CK00_DIV) +#define SAU1_SPS_REG_INIT ((BSP_CFG_SAU_CK11_DIV << R_SAU0_SPS_PRS1_Pos) | BSP_CFG_SAU_CK10_DIV) + +#if SAU_UART_CFG_SINGLE_CHANNEL > 2 + #define SAU_DEFINE_LOCALS(p_ctrl) /* Not used. All compile time macros instead. */ + #define SAU_REG (R_SAU1) + #define SAU_UNIT (1) + #define SAU_TX_INDEX ((SAU_UART_CFG_SINGLE_CHANNEL - 3) << 1) + #define SAU_RX_INDEX (SAU_TX_INDEX + 1) + #define SAU_SPS_REG_INIT (SAU1_SPS_REG_INIT) +#elif SAU_UART_CFG_SINGLE_CHANNEL > 0 + #define SAU_DEFINE_LOCALS(p_ctrl) /* Not used. All compile time macros instead. */ + #define SAU_REG (R_SAU0) + #define SAU_UNIT (0) + #define SAU_TX_INDEX ((SAU_UART_CFG_SINGLE_CHANNEL - 1) << 1) + #define SAU_RX_INDEX (SAU_TX_INDEX + 1) + #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) +#else + #ifdef R_SAU1 + #define SAU_DEFINE_LOCALS(p_ctrl) R_SAU0_Type * const _p_reg = (p_ctrl)->p_reg; \ + const uint8_t _sau_unit = (p_ctrl)->sau_unit; \ + const uint8_t _sau_tx_index = (p_ctrl)->sau_tx_channel; \ + const uint8_t _sau_rx_index = (p_ctrl)->sau_tx_channel + 1; \ + /* These locals will not always be used. Void cast to quiet unused variable warn */ \ + (void) _p_reg; (void) _sau_unit; (void) _sau_tx_index; (void) _sau_rx_index + #define SAU_REG (_p_reg) + #define SAU_UNIT (_sau_unit) + #define SAU_TX_INDEX (_sau_tx_index) + #define SAU_RX_INDEX (_sau_rx_index) + #define SAU_SPS_REG_INIT (SAU_UNIT ? SAU1_SPS_REG_INIT : SAU0_SPS_REG_INIT) + #else + #define SAU_DEFINE_LOCALS(p_ctrl) const uint8_t _sau_tx_index = (p_ctrl)->sau_tx_channel; \ + const uint8_t _sau_rx_index = (p_ctrl)->sau_tx_channel + 1; \ + /* These locals will not always be used. Void cast to quiet unused variable warn */ \ + (void) _sau_tx_index; (void) _sau_rx_index + #define SAU_TX_INDEX (_sau_tx_index) + #define SAU_RX_INDEX (_sau_rx_index) + #define SAU_REG (R_SAU0) + #define SAU_UNIT (0) + #define SAU_SPS_REG_INIT (SAU0_SPS_REG_INIT) + #endif +#endif + +#if SAU_UART_CFG_CRITICAL_SECTION_ENABLE + #define SAU_CRITICAL_SECTION_ENTER() {FSP_CRITICAL_SECTION_DEFINE; FSP_CRITICAL_SECTION_ENTER + #define SAU_CRITICAL_SECTION_EXIT() FSP_CRITICAL_SECTION_EXIT;} +#else + #define SAU_CRITICAL_SECTION_ENTER() + #define SAU_CRITICAL_SECTION_EXIT() +#endif + +#define SAU_UART_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS) | \ + (TRANSFER_REPEAT_AREA_DESTINATION << TRANSFER_SETTINGS_REPEAT_AREA_BITS)) +#define SAU_UART_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS) | \ + (TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS)) + +/* Mask of invalid data bits in 9-bit mode. */ +#define SAU_UART_ALIGN_2_BYTES (0x1U) + +/* No limit to the number of bytes to read or write if DTC is not used. */ +#define SAU_UART_MAX_READ_WRITE_NO_DTC (0xFFFFFFFFU) +#define SAU_UART_DTC_MAX_TRANSFER (0x10000U) + +/* "SAUU" in ASCII. Used to determine if the control block is open. */ +#define SAU_UART_OPEN (0x53415555U) +#define SAU_UART_SCR_TRXE_TRANSMISSION (2U << R_SAU0_SCR_TRXE_Pos) +#define SAU_UART_SCR_TRXE_RECEPTION (1U << R_SAU0_SCR_TRXE_Pos) +#define SAU_UART_SMR_STS_TRIGGER_SOFTWARE (0U << R_SAU0_SMR_STS_Pos) +#define SAU_UART_SMR_STS_TRIGGER_RXD (1U << R_SAU0_SMR_STS_Pos) +#define SAU_UART_SMR_MD1_UART_MODE (1U << R_SAU0_SMR_MD1_Pos) +#define SAU_UART_SMR_MD0_BUFFER_EMPTY (1U << R_SAU0_SMR_MD0_Pos) +#define SAU_UART_SCR_SLC_STOP_BIT1 (1U << R_SAU0_SCR_SLC_Pos) +#define SAU_UART_SIR_FRAME_ERROR_CLEAR (1U << R_SAU0_SIR_FECT_Pos) +#define SAU_UART_SIR_PARITY_ERROR_CLEAR (1U << R_SAU0_SIR_PECT_Pos) +#define SAU_UART_SIR_OVERRUN_ERROR_CLEAR (1U << R_SAU0_SIR_OVCT_Pos) +#define SAU_UART_SSR_OVF_OVERRUN (1U << R_SAU0_SSR_OVF_Pos) +#define SAU_UART_SSR_PEF_PARITY (1U << R_SAU0_SSR_PEF_Pos) +#define SAU_UART_SSR_FEF_FRAME (1U << R_SAU0_SSR_FEF_Pos) +#define SAU_UART_SOE_OUTPUT_ENABLE (1U << R_SAU0_SOE_SOE_Pos) +#define SAU_UART_SS_START_TRG_ON (1U << R_SAU0_SS_SS_Pos) +#define SAU_UART_ST_START_TRG_ON (1U << R_SAU0_ST_ST_Pos) +#define SAU_REG_CHANNEL_SIZE (R_SAU1_BASE - R_SAU0_BASE) + +#define SAU_UART_SMR_DEFAULT_VALUE (0x0020U) +#define SAU_UART_SCR_DEFAULT_VALUE (0x0004U) +#define SAU_UART_STCLK_MAX (127) +#define SAU_UART_STCLK_MIN (2) +#define SAU_UART_PRS_DIVIDER_MAX (0xFU) + +#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_sau_read_write_param_check(sau_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + +#endif + +static void r_sau_uart_config_set(sau_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +#if (SAU_UART_CFG_RX_ENABLE) +void sau_uart_eri_isr(void); +void sau_uart_rxi_isr(void); + +#endif + +#if (SAU_UART_CFG_TX_ENABLE) +void sau_uart_txi_isr(void); + +#endif + +#if SAU_UART_CFG_DTC_SUPPORT_ENABLE +static fsp_err_t r_sau_uart_transfer_disable(transfer_instance_t const * const p_transfer); +static fsp_err_t r_sau_uart_transfer_configure(sau_uart_instance_ctrl_t * const p_ctrl); + +#endif + +/* UART on SAU HAL API mapping for UART interface */ +const uart_api_t g_uart_on_sau = +{ + .open = R_SAU_UART_Open, + .close = R_SAU_UART_Close, + .write = R_SAU_UART_Write, + .read = R_SAU_UART_Read, + .infoGet = R_SAU_UART_InfoGet, + .baudSet = R_SAU_UART_BaudSet, + .communicationAbort = R_SAU_UART_Abort, + .callbackSet = R_SAU_UART_CallbackSet, + .readStop = R_SAU_UART_ReadStop, + .receiveSuspend = R_SAU_UART_ReceiveSuspend, + .receiveResume = R_SAU_UART_ReceiveResume, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup SAU_UART + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is + * enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_INVALID_ARGUMENT Flow control is enabled but flow control pin is not defined or selected channel + * does not support "Hardware CTS and Hardware RTS" flow control. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg) +{ + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + + sau_uart_extended_cfg_t * p_extend_cfg = (sau_uart_extended_cfg_t *) p_cfg->p_extend; + + FSP_ASSERT(p_extend_cfg); + FSP_ASSERT(p_extend_cfg->p_baudrate); + + #if (SAU_UART_CFG_TX_ENABLE) + FSP_ERROR_RETURN(p_cfg->txi_irq >= 0, FSP_ERR_INVALID_ARGUMENT); + #endif + + #if (SAU_UART_CFG_RX_ENABLE) + FSP_ERROR_RETURN(p_cfg->rxi_irq >= 0, FSP_ERR_INVALID_ARGUMENT); + if (FSP_INVALID_VECTOR != p_cfg->eri_irq) + { + FSP_ERROR_RETURN(p_cfg->eri_irq >= 0, FSP_ERR_INVALID_ARGUMENT); + } + #endif + + FSP_ERROR_RETURN(SAU_UART_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + #if !SAU_UART_CFG_SINGLE_CHANNEL + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #else + FSP_ERROR_RETURN((SAU_UART_CFG_SINGLE_CHANNEL - 1) == p_cfg->channel, FSP_ERR_INVALID_ARGUMENT); + #endif +#endif + +#if !SAU_UART_CFG_SINGLE_CHANNEL + + /* Don't use the macros here since the macros use defined locals which copy from p_ctrl. */ + + #ifdef R_SAU1 + + /* Each SAU can contain up to two UART channels */ + p_ctrl->sau_unit = p_cfg->channel / 2; + #else + p_ctrl->sau_unit = 0; + #endif + + /* The transmission channel only occupies the even channels of the current SAU unit. */ + p_ctrl->sau_tx_channel = (uint8_t) ((p_cfg->channel & 1) << 1); + + #ifdef R_SAU1 + p_ctrl->p_reg = (R_SAU0_Type *) (R_SAU0_BASE + (SAU_REG_CHANNEL_SIZE * p_ctrl->sau_unit)); + #else + p_ctrl->p_reg = R_SAU0; + #endif + + SAU_DEFINE_LOCALS(p_ctrl); +#endif + + p_ctrl->p_cfg = p_cfg; + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->extra_data_byte = (UART_DATA_BITS_9 == p_cfg->data_bits); + +#if SAU_UART_CFG_DTC_SUPPORT_ENABLE + + /* Configure the transfer interface for transmission and reception if provided. */ + fsp_err_t err = r_sau_uart_transfer_configure(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Enable the SAU unit */ + R_BSP_MODULE_START(FSP_IP_SAU, SAU_UNIT); + + /* Set the UART configuration settings provided in ::uart_cfg_t and ::sau_uart_extended_cfg_t. */ + r_sau_uart_config_set(p_ctrl, p_cfg); + + p_ctrl->p_src = NULL; + p_ctrl->tx_count = 0U; + p_ctrl->p_dest = NULL; + p_ctrl->rx_count = 0U; + +#if (SAU_UART_CFG_RX_ENABLE) + R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->rxi_ipl, p_ctrl); + if (FSP_INVALID_VECTOR != p_ctrl->p_cfg->eri_irq) + { + R_BSP_IrqCfgEnable(p_cfg->eri_irq, p_cfg->eri_ipl, p_ctrl); + } + SAU_REG->SS = (uint16_t) (SAU_UART_SS_START_TRG_ON << SAU_RX_INDEX); +#endif + +#if (SAU_UART_CFG_TX_ENABLE) + R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->txi_ipl, p_ctrl); + SAU_REG->SS = (uint16_t) (SAU_UART_SS_START_TRG_ON << SAU_TX_INDEX); +#endif + + p_ctrl->open = SAU_UART_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Removes power. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_Close (uart_ctrl_t * const p_api_ctrl) +{ + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + + FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + SAU_DEFINE_LOCALS(p_ctrl); + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + /* Stop the appropriate SAU channels. + * This is kept as an intermediate so the wait can be performed after. */ + uint16_t reg_st = 0; +#if (SAU_UART_CFG_TX_ENABLE) + reg_st |= (uint16_t) (SAU_UART_ST_START_TRG_ON << SAU_TX_INDEX); +#endif + +#if (SAU_UART_CFG_RX_ENABLE) + reg_st |= (uint16_t) (SAU_UART_ST_START_TRG_ON << SAU_RX_INDEX); +#endif + + /* Write stop trigger. */ + SAU_REG->ST = reg_st; + + /* Verify the channels are no longer enabled. */ + FSP_HARDWARE_REGISTER_WAIT((SAU_REG->SE & reg_st), 0U); + + /* Clear the TX/RX configuration. */ +#if (SAU_UART_CFG_TX_ENABLE) + SAU_REG->SCR[SAU_TX_INDEX] = 0U; + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); +#endif + +#if (SAU_UART_CFG_RX_ENABLE) + SAU_REG->SCR[SAU_RX_INDEX] = 0U; + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + if (FSP_INVALID_VECTOR != p_ctrl->p_cfg->eri_irq) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + } +#endif + +#if SAU_UART_CFG_DTC_SUPPORT_ENABLE + + /* Close UART instances. */ + #if (SAU_UART_CFG_RX_ENABLE) + transfer_instance_t const * p_dtc_rx = p_ctrl->p_cfg->p_transfer_rx; + if (NULL != p_dtc_rx) + { + p_dtc_rx->p_api->close(p_dtc_rx->p_ctrl); + } + #endif + + #if (SAU_UART_CFG_TX_ENABLE) + transfer_instance_t const * p_dtc_tx = p_ctrl->p_cfg->p_transfer_tx; + if (NULL != p_dtc_tx) + { + p_dtc_tx->p_api->close(p_dtc_tx->p_ctrl); + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures UART related registers based on user configurations. Assumes the channel is stopped. + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sau_uart_config_set (sau_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ +#if SAU_UART_CFG_SINGLE_CHANNEL + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + sau_uart_extended_cfg_t * p_extend_cfg = (sau_uart_extended_cfg_t *) p_cfg->p_extend; + + SAU_DEFINE_LOCALS(p_ctrl); + +#if (0 == SAU_UART_CFG_FIXED_BAUDRATE_ENABLE) + sau_uart_baudrate_setting_t * p_sau_baud_setting = p_extend_cfg->p_baudrate; + + /* Configure the operation clock divisor based on extended configuration settings */ + uint32_t sps_prs_offset = p_sau_baud_setting->operation_clock * R_SAU0_SPS_PRS1_Pos; + uint32_t sps_prs_mask = R_SAU0_SPS_PRS0_Msk << sps_prs_offset; + SAU_REG->SPS = + (uint16_t) ((SAU_REG->SPS & (~sps_prs_mask)) | + ((uint32_t) p_sau_baud_setting->prs << sps_prs_offset)); +#else + + /* Configure the operation clock divisor based on BSP settings */ + SAU_REG->SPS = SAU_SPS_REG_INIT; +#endif + +#if (SAU_UART_CFG_TX_ENABLE) + + /* Configure register SMR setting. */ + SAU_REG->SMR[SAU_TX_INDEX] = (uint16_t) (SAU_UART_SMR_DEFAULT_VALUE | + (uint16_t) (p_extend_cfg->p_baudrate->operation_clock << + R_SAU0_SMR_CKS_Pos) | + SAU_UART_SMR_STS_TRIGGER_SOFTWARE | + SAU_UART_SMR_MD1_UART_MODE | + SAU_UART_SMR_MD0_BUFFER_EMPTY); + + /* Configure register SCR setting. */ + SAU_REG->SCR[SAU_TX_INDEX] = (uint16_t) ((SAU_UART_SCR_DEFAULT_VALUE | + SAU_UART_SCR_TRXE_TRANSMISSION) | + (uint16_t) (p_cfg->parity << R_SAU0_SCR_PTC_Pos) | + (uint16_t) (p_extend_cfg->sequence << R_SAU0_SCR_DIR_Pos) | + (uint16_t) ((p_cfg->stop_bits + 1) << R_SAU0_SCR_SLC_Pos) | + p_cfg->data_bits); + + /* Set SDR register value. */ + SAU_REG->SDR[SAU_TX_INDEX] = (uint16_t) (p_extend_cfg->p_baudrate->stclk << R_SAU0_SDR_STCLK_Pos); + + const uint16_t tx_mask = (uint16_t) (1U << SAU_TX_INDEX); + const uint16_t tx_clr_mask = (uint16_t) ~tx_mask; +#else + + /* Configure register SMR setting (setting for transmit channel in Reception only mode). */ + SAU_REG->SMR[SAU_TX_INDEX] = SAU_UART_SMR_DEFAULT_VALUE | + (uint16_t) (p_extend_cfg->p_baudrate->operation_clock << R_SAU0_SMR_CKS_Pos) | + SAU_UART_SMR_STS_TRIGGER_RXD | + SAU_UART_SMR_MD1_UART_MODE; +#endif + + SAU_CRITICAL_SECTION_ENTER(); +#if SAU_UART_CFG_TX_ENABLE + + /* Output levels cannot be changed while output is enabled. Disable, make changes, then re-enable. */ + uint16_t reg_soe = (uint16_t) (SAU_REG->SOE & tx_clr_mask); + SAU_REG->SOE = reg_soe; + + /* Set the idle output level and signal level for the UART TX pin. */ + uint16_t reg_sol = SAU_REG->SOL; + uint16_t reg_so = SAU_REG->SO; + + if (SAU_UART_SIGNAL_LEVEL_INVERTED == p_extend_cfg->signal_level) + { + reg_sol |= tx_mask; // Inverted signal + reg_so &= tx_clr_mask; // Set idle to low + } + else + { + reg_sol &= tx_clr_mask; // Normal signal + reg_so |= tx_mask; // Set idle to high + } + + SAU_REG->SOL = reg_sol; + SAU_REG->SO = reg_so; + + /* Configure register SOE setting to enable serial output. */ + SAU_REG->SOE = (uint16_t) (reg_soe | tx_mask); +#endif + +#if SAU_UART_CFG_RX_ENABLE + + /* Configure register SNFENn setting. + * Use a critical section since I2C and SPI need this to be disabled for their channels. */ + R_PORGA->SNFEN |= (uint8_t) (R_PORGA_SNFEN_SNFEN00_Msk << (p_cfg->channel << 1)); +#endif + SAU_CRITICAL_SECTION_EXIT(); + +#if (SAU_UART_CFG_RX_ENABLE) + + /* Configure register SIR setting. */ + SAU_REG->SIR[SAU_RX_INDEX] = (uint16_t) (SAU_UART_SIR_FRAME_ERROR_CLEAR | + SAU_UART_SIR_PARITY_ERROR_CLEAR | + SAU_UART_SIR_OVERRUN_ERROR_CLEAR); + + /* Configure register SMR setting. */ + SAU_REG->SMR[SAU_RX_INDEX] = (uint16_t) (SAU_UART_SMR_DEFAULT_VALUE | + (uint16_t) (p_extend_cfg->p_baudrate->operation_clock << + R_SAU0_SMR_CKS_Pos) | + SAU_UART_SMR_STS_TRIGGER_RXD | + (uint16_t) (p_extend_cfg->signal_level << R_SAU0_SMR_SIS0_Pos) | + SAU_UART_SMR_MD1_UART_MODE); + + /* Configure register SCR setting. */ + SAU_REG->SCR[SAU_RX_INDEX] = (uint16_t) (SAU_UART_SCR_DEFAULT_VALUE | + SAU_UART_SCR_TRXE_RECEPTION | + (BSP_IRQ_DISABLED != p_cfg->eri_ipl ? R_SAU0_SCR_EOC_Msk : 0U) | + (uint16_t) (p_cfg->parity << R_SAU0_SCR_PTC_Pos) | + (uint16_t) (p_extend_cfg->sequence << R_SAU0_SCR_DIR_Pos) | + SAU_UART_SCR_SLC_STOP_BIT1 | + p_cfg->data_bits); + + /* Set SDR register value. */ + SAU_REG->SDR[SAU_RX_INDEX] = (uint16_t) (p_extend_cfg->p_baudrate->stclk << R_SAU0_SDR_STCLK_Pos); +#endif +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_INVALID_ARGUMENT Destination address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @retval FSP_ERR_UNSUPPORTED current operation mode is transmission only. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + * @note If 9-bit data length is specified at R_SAU_UART_Open call, p_dest must be aligned 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ +#if (SAU_UART_CFG_RX_ENABLE) + fsp_err_t err = FSP_SUCCESS; + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; + + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sau_read_write_param_check(p_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->rx_count, FSP_ERR_IN_USE); + #endif + + SAU_DEFINE_LOCALS(p_ctrl); + + /* Total number of words to read in this transfer. + * Bytes is total length of the buffer, so for 9-bit it needs to be divided by 2. */ + uint32_t words = bytes >> p_ctrl->extra_data_byte; + + /* Save the destination address and size for use in sr_isr. */ + p_ctrl->p_dest = p_dest; + p_ctrl->rx_count = words; + + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + const transfer_instance_t * p_dtc_rx = p_ctrl->p_cfg->p_transfer_rx; + + /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ + if (NULL != p_dtc_rx) + { + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(words <= SAU_UART_DTC_MAX_TRANSFER); + #endif + err = p_dtc_rx->p_api->reset(p_dtc_rx->p_ctrl, NULL, (void *) p_dest, (uint16_t) words); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + return err; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_INVALID_ARGUMENT Source address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UART transmission is in progress + * @retval FSP_ERR_UNSUPPORTED SAU_UART_CFG_TX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + * @note If 9-bit data length is specified at R_SAU_UART_Open call, p_src must be aligned on a 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ +#if (SAU_UART_CFG_TX_ENABLE) + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; + + #if SAU_UART_CFG_PARAM_CHECKING_ENABLE || SAU_UART_CFG_DTC_SUPPORT_ENABLE + fsp_err_t err = FSP_SUCCESS; + #endif + + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sau_read_write_param_check(p_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->tx_count, FSP_ERR_IN_USE); + + FSP_ERROR_RETURN(p_ctrl->p_cfg, FSP_ERR_INVALID_ARGUMENT); + #endif + + SAU_DEFINE_LOCALS(p_ctrl); + + /* Total number of words to write in this transfer. + * Bytes is total length of the buffer, so for 9-bit it needs to be divided by 2. + * Subtract one to take into account the manual write at the end of this function. */ + const uint32_t words = (bytes >> p_ctrl->extra_data_byte) - 1; + + /* Enable interrupt on buffer empty. */ + SAU_REG->SMR[SAU_TX_INDEX] |= SAU_UART_SMR_MD0_BUFFER_EMPTY; + + p_ctrl->p_src = (uint8_t *) (p_src + p_ctrl->extra_data_byte + 1); + + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + const transfer_instance_t * p_dtc_tx = p_ctrl->p_cfg->p_transfer_tx; + + /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested data. */ + if ((NULL != p_dtc_tx) && (words > 0)) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(words <= SAU_UART_DTC_MAX_TRANSFER); + #endif + + err = p_dtc_tx->p_api->reset(p_dtc_tx->p_ctrl, (void const *) p_ctrl->p_src, NULL, (uint16_t) words); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + else + #endif + { + /* TX Count is only used for non-DTC transfers. It can be ignored if the DTC is being used. */ + p_ctrl->tx_count = words; + } + + /* Manually write the first data word. + * Use p_src instead of p_ctrl->p_src because the latter is already adjusted for the next byte. */ + uint16_t data_word = 0; + + if (p_ctrl->extra_data_byte) + { + /* Using 2 data bytes for 9-bit transfers. */ + data_word = *((uint16_t *) p_src); + } + else + { + data_word = *p_src; + } + + SAU_REG->SDR[SAU_TX_INDEX] = data_word; + + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->txi_irq); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a sau_uart_baudrate_setting_t structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * @warning This function may change the operation clock frequency. Select a unique operation clock for each SAU + * instance if using this function. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer p_ctrl is NULL + * @retval FSP_ERR_INVALID_ARGUMENT p_api_ctrl is empty. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_UNSUPPORTED Fixed baud rate is enabled + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) +{ +#if SAU_UART_CFG_FIXED_BAUDRATE_ENABLE + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_baud_setting); + + return FSP_ERR_UNSUPPORTED; +#else + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; + sau_uart_baudrate_setting_t * p_sau_baud_setting = (sau_uart_baudrate_setting_t *) p_baud_setting; + + #if (0 == SAU_UART_CFG_SINGLE_CHANNEL || (0 == SAU_UART_CFG_PARAM_CHECKING_ENABLE)) + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(p_sau_baud_setting, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + SAU_DEFINE_LOCALS(p_ctrl); + + uint16_t reg_ss = 0U; + #if (SAU_UART_CFG_TX_ENABLE) + reg_ss |= (uint16_t) (SAU_UART_ST_START_TRG_ON << SAU_TX_INDEX); + #endif + + #if (SAU_UART_CFG_RX_ENABLE) + reg_ss |= (uint16_t) (SAU_UART_ST_START_TRG_ON << SAU_RX_INDEX); + #endif + + /* Request the channels stop and wait for it to apply. */ + SAU_REG->ST = reg_ss; + FSP_HARDWARE_REGISTER_WAIT((SAU_REG->SE & reg_ss), 0U); + + /* Configure the operation clock divisor */ + uint32_t sps_prs_offset = p_sau_baud_setting->operation_clock * R_SAU0_SPS_PRS1_Pos; + uint32_t sps_prs_mask = R_SAU0_SPS_PRS0_Msk << sps_prs_offset; + SAU_REG->SPS = + (uint16_t) ((SAU_REG->SPS & (~sps_prs_mask)) | + ((uint32_t) p_sau_baud_setting->prs << sps_prs_offset)); + + /* Set SDR register value and re-enable. */ + reg_ss = 0U; + #if (SAU_UART_CFG_RX_ENABLE) + SAU_REG->SDR[SAU_RX_INDEX] = (uint16_t) (p_sau_baud_setting->stclk << R_SAU0_SDR_STCLK_Pos); + reg_ss |= (uint16_t) (SAU_UART_SS_START_TRG_ON << SAU_RX_INDEX); + #endif + + #if (SAU_UART_CFG_TX_ENABLE) + SAU_REG->SDR[SAU_TX_INDEX] = (uint16_t) (p_sau_baud_setting->stclk << R_SAU0_SDR_STCLK_Pos); + reg_ss |= (uint16_t) (SAU_UART_SS_START_TRG_ON << SAU_TX_INDEX); + #endif + + /* Request the channels start and wait for it to apply. */ + SAU_REG->SS = reg_ss; + FSP_HARDWARE_REGISTER_WAIT((SAU_REG->SE & reg_ss), reg_ss); + + return FSP_SUCCESS; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION Pointer p_ctrl is NULL or p_callback_memory is not NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(NULL == p_callback_memory); + FSP_ERROR_RETURN(p_callback, FSP_ERR_ASSERTION); + FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + FSP_PARAMETER_NOT_USED(p_callback_memory); + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_INVALID_ARGUMENT Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info) +{ +#if SAU_UART_CFG_PARAM_CHECKING_ENABLE || SAU_UART_CFG_DTC_SUPPORT_ENABLE + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + +#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ERROR_RETURN(p_ctrl, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(p_info, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SAU_UART_CFG_RX_ENABLE) + p_info->read_bytes_max = SAU_UART_MAX_READ_WRITE_NO_DTC; + + /* Store number of bytes that can be read at a time. */ + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_info->read_bytes_max = SAU_UART_DTC_MAX_TRANSFER; + } + #endif +#endif + +#if (SAU_UART_CFG_TX_ENABLE) + p_info->write_bytes_max = SAU_UART_MAX_READ_WRITE_NO_DTC; + + /* Store number of bytes that can be written at a time. */ + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_info->write_bytes_max = SAU_UART_DTC_MAX_TRANSFER; + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) +{ +#if !(SAU_UART_CFG_TX_ENABLE) && !(SAU_UART_CFG_RX_ENABLE) + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(communication_to_abort); + + return FSP_ERR_UNSUPPORTED; +#else + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + + #if (SAU_UART_CFG_TX_ENABLE) || (SAU_UART_CFG_DTC_SUPPORT_ENABLE) + uart_cfg_t const * const p_cfg = p_ctrl->p_cfg; + #endif + + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + #if (SAU_UART_CFG_TX_ENABLE) + if (UART_DIR_TX & communication_to_abort) + { + R_BSP_IrqDisable(p_cfg->txi_irq); + p_ctrl->tx_count = 0; + + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + err = r_sau_uart_transfer_disable(p_cfg->p_transfer_tx); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + } + #endif + + #if (SAU_UART_CFG_RX_ENABLE) + if (UART_DIR_RX & communication_to_abort) + { + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + err = r_sau_uart_transfer_disable(p_cfg->p_transfer_rx); + #endif + + p_ctrl->rx_count = 0; + } + #endif + + return err; +#endif +} + +#if SAU_UART_CFG_DTC_SUPPORT_ENABLE + +/** + * Performs a NULL check and disables a transfer instance. + * @param[in] p_transfer Transfer instance to disable + * @return The error code from the disable api or FSP_SUCCESS if p_transfer is NULL. + */ +static fsp_err_t r_sau_uart_transfer_disable (transfer_instance_t const * const p_transfer) +{ + if (NULL == p_transfer) + { + return FSP_SUCCESS; + } + + return p_transfer->p_api->disable(p_transfer->p_ctrl); +} + +#endif + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes) +{ +#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE || SAU_UART_CFG_RX_ENABLE) + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) p_api_ctrl; +#endif + +#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SAU_UART_CFG_RX_ENABLE) + *remaining_bytes = p_ctrl->rx_count; + p_ctrl->rx_count = 0U; + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + transfer_instance_t const * const p_dtc_rx = p_ctrl->p_cfg->p_transfer_rx; + if (NULL != p_dtc_rx) + { + fsp_err_t err = p_dtc_rx->p_api->disable(p_dtc_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + transfer_properties_t transfer_info; + err = p_dtc_rx->p_api->infoGet(p_dtc_rx->p_ctrl, &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + *remaining_bytes = transfer_info.transfer_length_remaining; + } + #endif + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(remaining_bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings (SDR.STCLK) for the specified SAU unit. + * + * @param[in] p_ctrl Pointer to the SAU UART control block. + * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is successfully calculated + * @retval FSP_ERR_UNSUPPORTED Fixed baudrate is being used + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is not achievable with selected operation clock frequency + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_BaudCalculate (sau_uart_instance_ctrl_t * const p_ctrl, + uint32_t baudrate, + sau_uart_baudrate_setting_t * const p_baud_setting) +{ +#if SAU_UART_CFG_FIXED_BAUDRATE_ENABLE + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(baudrate); + FSP_PARAMETER_NOT_USED(p_baud_setting); + + return FSP_ERR_UNSUPPORTED; +#else + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ERROR_RETURN(p_baud_setting, FSP_ERR_ASSERTION); + FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT); + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + SAU_DEFINE_LOCALS(p_ctrl); + + #if SAU_UART_CFG_SINGLE_CHANNEL + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK); + + /* Calculate the optimal value of STCLK for the given CKn clock. The divisor with the lowest error + * is always the smallest divisor that produces valid STCLK settings. Since we search the divisors + * low to high, the first divisor is the optimal divisor. */ + for (uint8_t prs = 0; prs <= SAU_UART_PRS_DIVIDER_MAX; prs++) + { + /* To get the stclk divider calculate the divisor to apply to ICLK. There's a built in div/2. */ + const uint32_t divisor = baudrate << (prs + 1); + + /* Calculate stclk register value: STCLK = (f_mck / (2*bitrate)) - 1 */ + const uint32_t stclk = (peripheral_clock + (divisor >> 1)) / divisor - 1; + + if ((SAU_UART_STCLK_MIN <= stclk) && (stclk <= SAU_UART_STCLK_MAX)) + { + /* Save the settings that provide the lowest error. */ + p_baud_setting->prs = prs; + p_baud_setting->stclk = (uint8_t) stclk; + p_baud_setting->operation_clock = + ((sau_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->p_baudrate->operation_clock; + + return FSP_SUCCESS; + } + } + + /* Return an error if no valid STCLK setting was found */ + return FSP_ERR_INVALID_ARGUMENT; +#endif +} + +/*******************************************************************************************************************//** + * Suspend Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_ReceiveSuspend (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Resume Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_SAU_UART_ReceiveResume (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SAU_UART) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer p_ctrl is NULL + * @retval FSP_ERR_INVALID_ARGUMENT Address is not aligned to 2-byte boundary or size is the odd number when the data + * length is 9-bit + **********************************************************************************************************************/ +static fsp_err_t r_sau_read_write_param_check (sau_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(addr, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(0U != bytes, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(SAU_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + if (p_ctrl->extra_data_byte) + { + /* Do not allow odd buffer address if data length is 9 bits. */ + FSP_ERROR_RETURN((0U == ((uint32_t) addr & SAU_UART_ALIGN_2_BYTES)), FSP_ERR_INVALID_ARGUMENT); + + /* Do not allow odd number of data bytes if data length is 9 bits. */ + FSP_ERROR_RETURN(0U == (bytes & 1U), FSP_ERR_INVALID_ARGUMENT); + } + + return FSP_SUCCESS; +} + +#endif + +#if SAU_UART_CFG_DTC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Subroutine to apply common UART transfer settings. + * + * @param[in] p_ctrl Pointer to instance control block. + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer + **********************************************************************************************************************/ +static fsp_err_t r_sau_uart_transfer_configure (sau_uart_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + transfer_info_t * p_info = NULL; + + SAU_DEFINE_LOCALS(p_ctrl); + + #if (SAU_UART_CFG_RX_ENABLE) + transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + + /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ + if (NULL != p_transfer_rx) + { + /* Configure the transfer instance, if enabled. */ + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer_rx->p_api); + FSP_ASSERT(NULL != p_transfer_rx->p_ctrl); + FSP_ASSERT(NULL != p_transfer_rx->p_cfg); + FSP_ASSERT(NULL != p_transfer_rx->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer_rx->p_cfg->p_extend); + #endif + + p_info = p_transfer_rx->p_cfg->p_info; + + p_info->transfer_settings_word = SAU_UART_DTC_RX_TRANSFER_SETTINGS; + p_info->transfer_settings_word_b.size = (transfer_size_t) p_ctrl->extra_data_byte; + p_info->p_src = (void *) &(SAU_REG->SDR[SAU_RX_INDEX]); + + err = p_transfer_rx->p_api->open(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + #if (SAU_UART_CFG_TX_ENABLE) + transfer_instance_t const * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + + /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ + if (NULL != p_transfer_tx) + { + /* Configure the transfer instance, if enabled. */ + #if (SAU_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer_tx->p_api); + FSP_ASSERT(NULL != p_transfer_tx->p_ctrl); + FSP_ASSERT(NULL != p_transfer_tx->p_cfg); + FSP_ASSERT(NULL != p_transfer_tx->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer_tx->p_cfg->p_extend); + #endif + + p_info = p_transfer_tx->p_cfg->p_info; + + p_info->transfer_settings_word = SAU_UART_DTC_TX_TRANSFER_SETTINGS; + p_info->transfer_settings_word_b.size = (transfer_size_t) p_ctrl->extra_data_byte; + p_info->p_dest = (void *) &(SAU_REG->SDR[SAU_TX_INDEX]); + + err = p_transfer_tx->p_api->open(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg); + + #if (SAU_UART_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_transfer_rx)) + { + p_transfer_rx->p_api->close(p_transfer_rx->p_ctrl); + } + #endif + } + #endif + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sau_uart_call_callback (sau_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) +{ + if (NULL == p_ctrl->p_callback) + { + return; + } + + uart_callback_args_t args; + + args.channel = p_ctrl->p_cfg->channel; + args.data = data; + args.event = event; + args.p_context = p_ctrl->p_context; + + p_ctrl->p_callback(&args); +} + +#if (SAU_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * INTSTn interrupt processing for UART mode. This function is UART0 write interrupt service routine + **********************************************************************************************************************/ +void sau_uart_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + SAU_DEFINE_LOCALS(p_ctrl); + + uint16_t reg_smr = SAU_REG->SMR[SAU_TX_INDEX]; + + if ((p_ctrl->tx_count) && (NULL == p_ctrl->p_cfg->p_transfer_rx)) + { + uint16_t reg_sdr = 0U; + + if (0U != p_ctrl->extra_data_byte) + { + reg_sdr = *((uint16_t *) p_ctrl->p_src); + } + else + { + reg_sdr = *p_ctrl->p_src; + } + + SAU_REG->SDR[SAU_TX_INDEX] = reg_sdr; + p_ctrl->p_src += 1 + p_ctrl->extra_data_byte; + + p_ctrl->tx_count--; + + if (!p_ctrl->tx_count) + { + /* Change the TX interrupt to end of transfer instead so the complete callback happens at the right time. */ + reg_smr &= (uint16_t) ~SAU_UART_SMR_MD0_BUFFER_EMPTY; + } + } + else + { + /* Could be the end of a DTC transfer so reset all the TX intermediates. */ + p_ctrl->p_src = NULL; + if (reg_smr & R_SAU0_SMR_MD0_Msk) + { + /* Change the TX interrupt to end of transfer instead so the complete callback happens at the right time. */ + reg_smr &= (uint16_t) ~SAU_UART_SMR_MD0_BUFFER_EMPTY; + } + else if (!SAU_REG->SSR[SAU_TX_INDEX]) + { + /* Only send TX COMPLETE if the SAU channel has returned to idle. */ + r_sau_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + else + { + /* Do nothing. The second to last word has finished transmitting. Keep waiting for the last one.*/ + } + } + + /* Commit any changes to the SMR. */ + SAU_REG->SMR[SAU_TX_INDEX] = reg_smr; + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +#if (SAU_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * INTSRn interrupt processing for UART mode. This function is UART0 receive interrupt service routine + **********************************************************************************************************************/ +void sau_uart_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + SAU_DEFINE_LOCALS(p_ctrl); + + const uint16_t data = SAU_REG->SDR[SAU_RX_INDEX]; + + if (!p_ctrl->rx_count) + { + /* This is the case where an abort or readStop was called. + * Notify the application of the received data using a callback. */ + p_ctrl->p_dest = NULL; + r_sau_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR); + } + else + { + #if SAU_UART_CFG_DTC_SUPPORT_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_dest = NULL; + p_ctrl->rx_count = 0; + r_sau_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + else + #endif + { + if (p_ctrl->extra_data_byte) + { + *((uint16_t *) p_ctrl->p_dest) = data; + p_ctrl->p_dest += 2; + } + else + { + *p_ctrl->p_dest = (uint8_t) data; + p_ctrl->p_dest += 1; + } + + p_ctrl->rx_count--; + + if (!p_ctrl->rx_count) + { + p_ctrl->p_dest = NULL; + r_sau_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * INTSREn interrupt processing for UART mode. This function is UART0 receive error interrupt service routine + **********************************************************************************************************************/ +void sau_uart_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sau_uart_instance_ctrl_t * p_ctrl = (sau_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + SAU_DEFINE_LOCALS(p_ctrl); + + /* The data buffer must be read as part of clearing the error to avoid an overrun error after recovery. */ + const uint16_t data = SAU_REG->SDR[SAU_RX_INDEX]; + const uint16_t ssr_reg = SAU_REG->SSR[SAU_RX_INDEX]; + uart_event_t event = (uart_event_t) 0U; + uint16_t flag = 0U; + + if (SAU_UART_SSR_OVF_OVERRUN & ssr_reg) + { + flag = SAU_UART_SSR_OVF_OVERRUN; + event = UART_EVENT_ERR_OVERFLOW; + } + else if (SAU_UART_SSR_PEF_PARITY & ssr_reg) + { + flag = SAU_UART_SSR_PEF_PARITY; + event = UART_EVENT_ERR_PARITY; + } + else if (SAU_UART_SSR_FEF_FRAME & ssr_reg) + { + flag = SAU_UART_SSR_FEF_FRAME; + event = UART_EVENT_ERR_FRAMING; + } + else + { + // Do nothing. Undefined error type. + } + + if (event) + { + SAU_REG->SIR[SAU_RX_INDEX] = flag; + r_sau_uart_call_callback(p_ctrl, data, event); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/SCE_ProcCommon.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/SCE_ProcCommon.h new file mode 100644 index 0000000000..54752f9fc1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/SCE_ProcCommon.h @@ -0,0 +1,5754 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef __SCE_ProcCommon_h__ +#define __SCE_ProcCommon_h__ + +#include + +#include "bsp_api.h" /* For Crypto Error codes */ +#include "SCE_module.h" + +/* ================================================================================ */ +/* ================ SCE ================ */ +/* ================================================================================ */ + +/** + * @brief Trusted Security IP (SCE) + */ +typedef struct +{ + union + { + __IOM uint32_t REG_00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_00H_b; + }; + union + { + __IOM uint32_t REG_04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_04H_b; + }; + union + { + __IOM uint32_t REG_08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_08H_b; + }; + union + { + __IOM uint32_t REG_0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_0CH_b; + }; + union + { + __IOM uint32_t REG_10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10H_b; + }; + union + { + __IOM uint32_t REG_14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14H_b; + }; + union + { + __IOM uint32_t REG_18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18H_b; + }; + union + { + __IOM uint32_t REG_1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CH_b; + }; + union + { + __IOM uint32_t REG_20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20H_b; + }; + union + { + __IOM uint32_t REG_24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24H_b; + }; + union + { + __IOM uint32_t REG_28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_28H_b; + }; + union + { + __IOM uint32_t REG_2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2CH_b; + }; + union + { + __IOM uint32_t REG_30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_30H_b; + }; + union + { + __IOM uint32_t REG_34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_34H_b; + }; + union + { + __IOM uint32_t REG_38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_38H_b; + }; + union + { + __IOM uint32_t REG_3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3CH_b; + }; + union + { + __IOM uint32_t REG_40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_40H_b; + }; + union + { + __IOM uint32_t REG_44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_44H_b; + }; + union + { + __IOM uint32_t REG_48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_48H_b; + }; + union + { + __IOM uint32_t REG_4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4CH_b; + }; + union + { + __IOM uint32_t REG_50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_50H_b; + }; + union + { + __IOM uint32_t REG_54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_54H_b; + }; + union + { + __IOM uint32_t REG_58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_58H_b; + }; + union + { + __IOM uint32_t REG_5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5CH_b; + }; + union + { + __IOM uint32_t REG_60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_60H_b; + }; + union + { + __IOM uint32_t REG_64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_64H_b; + }; + union + { + __IOM uint32_t REG_68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_68H_b; + }; + union + { + __IOM uint32_t REG_6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6CH_b; + }; + union + { + __IOM uint32_t REG_70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_70H_b; + }; + union + { + __IOM uint32_t REG_74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_74H_b; + }; + union + { + __IOM uint32_t REG_78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_78H_b; + }; + union + { + __IOM uint32_t REG_7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7CH_b; + }; + union + { + __IOM uint32_t REG_80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_80H_b; + }; + union + { + __IOM uint32_t REG_84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_84H_b; + }; + union + { + __IOM uint32_t REG_88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_88H_b; + }; + union + { + __IOM uint32_t REG_8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8CH_b; + }; + union + { + __IOM uint32_t REG_90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_90H_b; + }; + union + { + __IOM uint32_t REG_94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_94H_b; + }; + union + { + __IOM uint32_t REG_98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_98H_b; + }; + union + { + __IOM uint32_t REG_9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9CH_b; + }; + union + { + __IOM uint32_t REG_A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A0H_b; + }; + union + { + __IOM uint32_t REG_A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A4H_b; + }; + union + { + __IOM uint32_t REG_A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A8H_b; + }; + union + { + __IOM uint32_t REG_ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ACH_b; + }; + union + { + __IOM uint32_t REG_B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B0H_b; + }; + union + { + __IOM uint32_t REG_B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B4H_b; + }; + union + { + __IOM uint32_t REG_B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B8H_b; + }; + union + { + __IOM uint32_t REG_BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BCH_b; + }; + union + { + __IOM uint32_t REG_C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C0H_b; + }; + union + { + __IOM uint32_t REG_C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C4H_b; + }; + union + { + __IOM uint32_t REG_C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C8H_b; + }; + union + { + __IOM uint32_t REG_CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CCH_b; + }; + union + { + __IOM uint32_t REG_D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D0H_b; + }; + union + { + __IOM uint32_t REG_D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D4H_b; + }; + union + { + __IOM uint32_t REG_D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D8H_b; + }; + union + { + __IOM uint32_t REG_DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DCH_b; + }; + union + { + __IOM uint32_t REG_E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E0H_b; + }; + union + { + __IOM uint32_t REG_E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E4H_b; + }; + union + { + __IOM uint32_t REG_E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E8H_b; + }; + union + { + __IOM uint32_t REG_ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ECH_b; + }; + union + { + __IOM uint32_t REG_F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F0H_b; + }; + union + { + __IOM uint32_t REG_F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F4H_b; + }; + union + { + __IOM uint32_t REG_F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F8H_b; + }; + union + { + __IOM uint32_t REG_FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FCH_b; + }; + union + { + __IOM uint32_t REG_100H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_100H_b; + }; + union + { + __IOM uint32_t REG_104H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_104H_b; + }; + union + { + __IOM uint32_t REG_108H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_108H_b; + }; + union + { + __IOM uint32_t REG_10CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10CH_b; + }; + union + { + __IOM uint32_t REG_110H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_110H_b; + }; + union + { + __IOM uint32_t REG_114H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_114H_b; + }; + union + { + __IOM uint32_t REG_118H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_118H_b; + }; + union + { + __IOM uint32_t REG_11CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11CH_b; + }; + union + { + __IOM uint32_t REG_120H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_120H_b; + }; + union + { + __IOM uint32_t REG_124H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_124H_b; + }; + union + { + __IOM uint32_t REG_128H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_128H_b; + }; + union + { + __IOM uint32_t REG_12CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12CH_b; + }; + union + { + __IOM uint32_t REG_130H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_130H_b; + }; + union + { + __IOM uint32_t REG_134H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_134H_b; + }; + union + { + __IOM uint32_t REG_138H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_138H_b; + }; + union + { + __IOM uint32_t REG_13CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13CH_b; + }; + union + { + __IOM uint32_t REG_140H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_140H_b; + }; + union + { + __IOM uint32_t REG_144H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_144H_b; + }; + union + { + __IOM uint32_t REG_148H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_148H_b; + }; + union + { + __IOM uint32_t REG_14CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14CH_b; + }; + union + { + __IOM uint32_t REG_150H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_150H_b; + }; + union + { + __IOM uint32_t REG_154H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_154H_b; + }; + union + { + __IOM uint32_t REG_158H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_158H_b; + }; + union + { + __IOM uint32_t REG_15CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15CH_b; + }; + union + { + __IOM uint32_t REG_160H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_160H_b; + }; + union + { + __IOM uint32_t REG_164H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_164H_b; + }; + union + { + __IOM uint32_t REG_168H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_168H_b; + }; + union + { + __IOM uint32_t REG_16CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16CH_b; + }; + union + { + __IOM uint32_t REG_170H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_170H_b; + }; + union + { + __IOM uint32_t REG_174H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_174H_b; + }; + union + { + __IOM uint32_t REG_178H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_178H_b; + }; + union + { + __IOM uint32_t REG_17CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17CH_b; + }; + union + { + __IOM uint32_t REG_180H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_180H_b; + }; + union + { + __IOM uint32_t REG_184H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_184H_b; + }; + union + { + __IOM uint32_t REG_188H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_188H_b; + }; + union + { + __IOM uint32_t REG_18CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18CH_b; + }; + union + { + __IOM uint32_t REG_190H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_190H_b; + }; + union + { + __IOM uint32_t REG_194H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_194H_b; + }; + union + { + __IOM uint32_t REG_198H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_198H_b; + }; + union + { + __IOM uint32_t REG_19CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19CH_b; + }; + union + { + __IOM uint32_t REG_1A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A0H_b; + }; + union + { + __IOM uint32_t REG_1A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A4H_b; + }; + union + { + __IOM uint32_t REG_1A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A8H_b; + }; + union + { + __IOM uint32_t REG_1ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ACH_b; + }; + union + { + __IOM uint32_t REG_1B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B0H_b; + }; + union + { + __IOM uint32_t REG_1B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B4H_b; + }; + union + { + __IOM uint32_t REG_1B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B8H_b; + }; + union + { + __IOM uint32_t REG_1BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BCH_b; + }; + union + { + __IOM uint32_t REG_1C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C0H_b; + }; + union + { + __IOM uint32_t REG_1C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C4H_b; + }; + union + { + __IOM uint32_t REG_1C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C8H_b; + }; + union + { + __IOM uint32_t REG_1CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CCH_b; + }; + union + { + __IOM uint32_t REG_1D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D0H_b; + }; + union + { + __IOM uint32_t REG_1D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D4H_b; + }; + union + { + __IOM uint32_t REG_1D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D8H_b; + }; + union + { + __IOM uint32_t REG_1DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DCH_b; + }; + union + { + __IOM uint32_t REG_1E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E0H_b; + }; + union + { + __IOM uint32_t REG_1E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E4H_b; + }; + union + { + __IOM uint32_t REG_1E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E8H_b; + }; + union + { + __IOM uint32_t REG_1ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ECH_b; + }; + union + { + __IOM uint32_t REG_1F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F0H_b; + }; + union + { + __IOM uint32_t REG_1F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F4H_b; + }; + union + { + __IOM uint32_t REG_1F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F8H_b; + }; + union + { + __IOM uint32_t REG_1FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FCH_b; + }; +} SCE_Type; + +// for bit access + +/* -------------------------------- SCE.REG_xxxH -------------------------------- */ +#define SCE_REG_0_Pos 0 /*!< SCE REG_xxxH: bit 0 Position */ +#define SCE_REG_0_Msk (0x01UL << SCE_REG_0_Pos) /*!< SCE REG_xxxH: bit 0 Mask */ +#define SCE_REG_1_Pos 1 /*!< SCE REG_xxxH: bit 1 Position */ +#define SCE_REG_1_Msk (0x01UL << SCE_REG_1_Pos) /*!< SCE REG_xxxH: bit 1 Mask */ +#define SCE_REG_2_Pos 2 /*!< SCE REG_xxxH: bit 2 Position */ +#define SCE_REG_2_Msk (0x01UL << SCE_REG_2_Pos) /*!< SCE REG_xxxH: bit 2 Mask */ +#define SCE_REG_3_Pos 3 /*!< SCE REG_xxxH: bit 3 Position */ +#define SCE_REG_3_Msk (0x01UL << SCE_REG_3_Pos) /*!< SCE REG_xxxH: bit 3 Mask */ +#define SCE_REG_4_Pos 4 /*!< SCE REG_xxxH: bit 4 Position */ +#define SCE_REG_4_Msk (0x01UL << SCE_REG_4_Pos) /*!< SCE REG_xxxH: bit 4 Mask */ +#define SCE_REG_5_Pos 5 /*!< SCE REG_xxxH: bit 5 Position */ +#define SCE_REG_5_Msk (0x01UL << SCE_REG_5_Pos) /*!< SCE REG_xxxH: bit 5 Mask */ +#define SCE_REG_6_Pos 6 /*!< SCE REG_xxxH: bit 6 Position */ +#define SCE_REG_6_Msk (0x01UL << SCE_REG_6_Pos) /*!< SCE REG_xxxH: bit 6 Mask */ +#define SCE_REG_7_Pos 7 /*!< SCE REG_xxxH: bit 7 Position */ +#define SCE_REG_7_Msk (0x01UL << SCE_REG_7_Pos) /*!< SCE REG_xxxH: bit 7 Mask */ +#define SCE_REG_8_Pos 8 /*!< SCE REG_xxxH: bit 8 Position */ +#define SCE_REG_8_Msk (0x01UL << SCE_REG_8_Pos) /*!< SCE REG_xxxH: bit 8 Mask */ +#define SCE_REG_9_Pos 9 /*!< SCE REG_xxxH: bit 9 Position */ +#define SCE_REG_9_Msk (0x01UL << SCE_REG_9_Pos) /*!< SCE REG_xxxH: bit 9 Mask */ +#define SCE_REG_10_Pos 10 /*!< SCE REG_xxxH: bit 10 Position */ +#define SCE_REG_10_Msk (0x01UL << SCE_REG_10_Pos) /*!< SCE REG_xxxH: bit 10 Mask */ +#define SCE_REG_11_Pos 11 /*!< SCE REG_xxxH: bit 11 Position */ +#define SCE_REG_11_Msk (0x01UL << SCE_REG_11_Pos) /*!< SCE REG_xxxH: bit 11 Mask */ +#define SCE_REG_12_Pos 12 /*!< SCE REG_xxxH: bit 12 Position */ +#define SCE_REG_12_Msk (0x01UL << SCE_REG_12_Pos) /*!< SCE REG_xxxH: bit 12 Mask */ +#define SCE_REG_13_Pos 13 /*!< SCE REG_xxxH: bit 13 Position */ +#define SCE_REG_13_Msk (0x01UL << SCE_REG_13_Pos) /*!< SCE REG_xxxH: bit 13 Mask */ +#define SCE_REG_14_Pos 14 /*!< SCE REG_xxxH: bit 14 Position */ +#define SCE_REG_14_Msk (0x01UL << SCE_REG_14_Pos) /*!< SCE REG_xxxH: bit 14 Mask */ +#define SCE_REG_15_Pos 15 /*!< SCE REG_xxxH: bit 15 Position */ +#define SCE_REG_15_Msk (0x01UL << SCE_REG_15_Pos) /*!< SCE REG_xxxH: bit 15 Mask */ +#define SCE_REG_16_Pos 16 /*!< SCE REG_xxxH: bit 16 Position */ +#define SCE_REG_16_Msk (0x01UL << SCE_REG_16_Pos) /*!< SCE REG_xxxH: bit 16 Mask */ +#define SCE_REG_17_Pos 17 /*!< SCE REG_xxxH: bit 17 Position */ +#define SCE_REG_17_Msk (0x01UL << SCE_REG_17_Pos) /*!< SCE REG_xxxH: bit 17 Mask */ +#define SCE_REG_18_Pos 18 /*!< SCE REG_xxxH: bit 18 Position */ +#define SCE_REG_18_Msk (0x01UL << SCE_REG_18_Pos) /*!< SCE REG_xxxH: bit 18 Mask */ +#define SCE_REG_19_Pos 19 /*!< SCE REG_xxxH: bit 19 Position */ +#define SCE_REG_19_Msk (0x01UL << SCE_REG_19_Pos) /*!< SCE REG_xxxH: bit 19 Mask */ +#define SCE_REG_20_Pos 20 /*!< SCE REG_xxxH: bit 20 Position */ +#define SCE_REG_20_Msk (0x01UL << SCE_REG_20_Pos) /*!< SCE REG_xxxH: bit 20 Mask */ +#define SCE_REG_21_Pos 21 /*!< SCE REG_xxxH: bit 21 Position */ +#define SCE_REG_21_Msk (0x01UL << SCE_REG_21_Pos) /*!< SCE REG_xxxH: bit 21 Mask */ +#define SCE_REG_22_Pos 22 /*!< SCE REG_xxxH: bit 22 Position */ +#define SCE_REG_22_Msk (0x01UL << SCE_REG_22_Pos) /*!< SCE REG_xxxH: bit 22 Mask */ +#define SCE_REG_23_Pos 23 /*!< SCE REG_xxxH: bit 23 Position */ +#define SCE_REG_23_Msk (0x01UL << SCE_REG_23_Pos) /*!< SCE REG_xxxH: bit 23 Mask */ +#define SCE_REG_24_Pos 24 /*!< SCE REG_xxxH: bit 24 Position */ +#define SCE_REG_24_Msk (0x01UL << SCE_REG_24_Pos) /*!< SCE REG_xxxH: bit 24 Mask */ +#define SCE_REG_25_Pos 25 /*!< SCE REG_xxxH: bit 25 Position */ +#define SCE_REG_25_Msk (0x01UL << SCE_REG_25_Pos) /*!< SCE REG_xxxH: bit 25 Mask */ +#define SCE_REG_26_Pos 26 /*!< SCE REG_xxxH: bit 26 Position */ +#define SCE_REG_26_Msk (0x01UL << SCE_REG_26_Pos) /*!< SCE REG_xxxH: bit 26 Mask */ +#define SCE_REG_27_Pos 27 /*!< SCE REG_xxxH: bit 27 Position */ +#define SCE_REG_27_Msk (0x01UL << SCE_REG_27_Pos) /*!< SCE REG_xxxH: bit 27 Mask */ +#define SCE_REG_28_Pos 28 /*!< SCE REG_xxxH: bit 28 Position */ +#define SCE_REG_28_Msk (0x01UL << SCE_REG_28_Pos) /*!< SCE REG_xxxH: bit 28 Mask */ +#define SCE_REG_29_Pos 29 /*!< SCE REG_xxxH: bit 29 Position */ +#define SCE_REG_29_Msk (0x01UL << SCE_REG_29_Pos) /*!< SCE REG_xxxH: bit 29 Mask */ +#define SCE_REG_30_Pos 30 /*!< SCE REG_xxxH: bit 30 Position */ +#define SCE_REG_30_Msk (0x01UL << SCE_REG_30_Pos) /*!< SCE REG_xxxH: bit 30 Mask */ +#define SCE_REG_31_Pos 31 /*!< SCE REG_xxxH: bit 31 Position */ +#define SCE_REG_31_Msk (0x01UL << SCE_REG_31_Pos) /*!< SCE REG_xxxH: bit 31 Mask */ + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define SCE ((SCE_Type *) SCE_BASE) + +// macro definishion + +#define SCE_DELAY(delay) \ + for (volatile uint32_t count = 0; count < delay; count++) \ + { \ + ; \ + } + +// [R RD 1 B] +#define RD1_PROG(regName) \ + (SCE->regName) + +// [R WR 1 B] +#define WR1_PROG(regName, value) \ + SCE->regName = value + +// [R WR 2 B0 B1] +#define WR2_PROG(regName, value0, value1) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); + +// [R WR 3 B0 B1 B2] +#define WR3_PROG(regName, value0, value1, value2) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2) + +// [R WR 4 B0 B1 B2 B3] +#define WR4_PROG(regName, value0, value1, value2, value3) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3) + +// [R WR 16 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15] +#define WR16_PROG(regName, \ + value0, \ + value1, \ + value2, \ + value3, \ + value4, \ + value5, \ + value6, \ + value7, \ + value8, \ + value9, \ + value10, \ + value11, \ + value12, \ + value13, \ + value14, \ + value15) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15) + +// [R RD 1 B] +#define RD1_EVAL(regName, value) \ + if (SCE->regname != value) \ + return FSP_ERR_CRYPTO_SCE_FAIL + +// [R CHK_STATUS A B] +#define CHCK_STS(regName, bitPos, value) \ + (((SCE->regName & (0x01UL << bitPos)) >> bitPos) == value) + +// [R CHK_REG A (!= B)] +#define RD1_MASK(regName, maskValue) \ + (SCE->regName & maskValue) + +// [R WAIT_STATUS A B] +#define WAIT_STS(regName, bitPos, value) \ + while (!CHCK_STS(regName, bitPos, value)) + +// [R WR 1 MEM[Ofs]] +#define WR1_ADDR(regName, addr) \ + SCE->regName = *(addr) + +// [R WR 2 MEM[Ofs]] +#define WR2_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); + +// [R WR 3 MEM[Ofs]] +#define WR3_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); + +// [R WR 4 MEM[Ofs]] +#define WR4_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3) + +// [R WR 5 MEM[Ofs]] +#define WR5_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4) + +// [R WR 6 MEM[Ofs]] +#define WR6_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5) + +// [R WR 7 MEM[Ofs]] +#define WR7_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6) + +// [R WR 8 MEM[Ofs]] +#define WR8_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7) + +// [R WR 12 MEM[Ofs]] +#define WR12_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11) + +// [R WR 16 MEM[Ofs]] +#define WR16_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15) + +// [R WR 32 MEM[Ofs]] +#define WR32_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15); \ + WR1_ADDR(regName, (addr) + 16); \ + WR1_ADDR(regName, (addr) + 17); \ + WR1_ADDR(regName, (addr) + 18); \ + WR1_ADDR(regName, (addr) + 19); \ + WR1_ADDR(regName, (addr) + 20); \ + WR1_ADDR(regName, (addr) + 21); \ + WR1_ADDR(regName, (addr) + 22); \ + WR1_ADDR(regName, (addr) + 23); \ + WR1_ADDR(regName, (addr) + 24); \ + WR1_ADDR(regName, (addr) + 25); \ + WR1_ADDR(regName, (addr) + 26); \ + WR1_ADDR(regName, (addr) + 27); \ + WR1_ADDR(regName, (addr) + 28); \ + WR1_ADDR(regName, (addr) + 29); \ + WR1_ADDR(regName, (addr) + 30); \ + WR1_ADDR(regName, (addr) + 31) + +// [R WR 64 MEM[Ofs]] +#define WR64_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15); \ + WR1_ADDR(regName, (addr) + 16); \ + WR1_ADDR(regName, (addr) + 17); \ + WR1_ADDR(regName, (addr) + 18); \ + WR1_ADDR(regName, (addr) + 19); \ + WR1_ADDR(regName, (addr) + 20); \ + WR1_ADDR(regName, (addr) + 21); \ + WR1_ADDR(regName, (addr) + 22); \ + WR1_ADDR(regName, (addr) + 23); \ + WR1_ADDR(regName, (addr) + 24); \ + WR1_ADDR(regName, (addr) + 25); \ + WR1_ADDR(regName, (addr) + 26); \ + WR1_ADDR(regName, (addr) + 27); \ + WR1_ADDR(regName, (addr) + 28); \ + WR1_ADDR(regName, (addr) + 29); \ + WR1_ADDR(regName, (addr) + 30); \ + WR1_ADDR(regName, (addr) + 31); \ + WR1_ADDR(regName, (addr) + 32); \ + WR1_ADDR(regName, (addr) + 33); \ + WR1_ADDR(regName, (addr) + 34); \ + WR1_ADDR(regName, (addr) + 35); \ + WR1_ADDR(regName, (addr) + 36); \ + WR1_ADDR(regName, (addr) + 37); \ + WR1_ADDR(regName, (addr) + 38); \ + WR1_ADDR(regName, (addr) + 39); \ + WR1_ADDR(regName, (addr) + 40); \ + WR1_ADDR(regName, (addr) + 41); \ + WR1_ADDR(regName, (addr) + 42); \ + WR1_ADDR(regName, (addr) + 43); \ + WR1_ADDR(regName, (addr) + 44); \ + WR1_ADDR(regName, (addr) + 45); \ + WR1_ADDR(regName, (addr) + 46); \ + WR1_ADDR(regName, (addr) + 47); \ + WR1_ADDR(regName, (addr) + 48); \ + WR1_ADDR(regName, (addr) + 49); \ + WR1_ADDR(regName, (addr) + 50); \ + WR1_ADDR(regName, (addr) + 51); \ + WR1_ADDR(regName, (addr) + 52); \ + WR1_ADDR(regName, (addr) + 53); \ + WR1_ADDR(regName, (addr) + 54); \ + WR1_ADDR(regName, (addr) + 55); \ + WR1_ADDR(regName, (addr) + 56); \ + WR1_ADDR(regName, (addr) + 57); \ + WR1_ADDR(regName, (addr) + 58); \ + WR1_ADDR(regName, (addr) + 59); \ + WR1_ADDR(regName, (addr) + 60); \ + WR1_ADDR(regName, (addr) + 61); \ + WR1_ADDR(regName, (addr) + 62); \ + WR1_ADDR(regName, (addr) + 63) + +// [R RD 1 MEM[Ofs]] +#define RD1_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; + +// [R RD 2 MEM[Ofs]] +#define RD2_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; + +// [R RD 3 MEM[Ofs]] +#define RD3_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; + +// [R RD 4 MEM[Ofs]] +#define RD4_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName + +// [R RD 5 MEM[Ofs]] +#define RD5_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName + +// [R RD 6 MEM[Ofs]] +#define RD6_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName + +// [R RD 7 MEM[Ofs]] +#define RD7_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName + +// [R RD 8 MEM[Ofs]] +#define RD8_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName + +// [R RD 12 MEM[Ofs]] +#define RD12_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName + +// [R RD 16 MEM[Ofs]] +#define RD16_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName + +// [R RD 32 MEM[Ofs]] +#define RD32_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName; \ + *((addr) + 16) = SCE->regName; \ + *((addr) + 17) = SCE->regName; \ + *((addr) + 18) = SCE->regName; \ + *((addr) + 19) = SCE->regName; \ + *((addr) + 20) = SCE->regName; \ + *((addr) + 21) = SCE->regName; \ + *((addr) + 22) = SCE->regName; \ + *((addr) + 23) = SCE->regName; \ + *((addr) + 24) = SCE->regName; \ + *((addr) + 25) = SCE->regName; \ + *((addr) + 26) = SCE->regName; \ + *((addr) + 27) = SCE->regName; \ + *((addr) + 28) = SCE->regName; \ + *((addr) + 29) = SCE->regName; \ + *((addr) + 30) = SCE->regName; \ + *((addr) + 31) = SCE->regName + +// [R RD 64 MEM[Ofs]] +#define RD64_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName; \ + *((addr) + 16) = SCE->regName; \ + *((addr) + 17) = SCE->regName; \ + *((addr) + 18) = SCE->regName; \ + *((addr) + 19) = SCE->regName; \ + *((addr) + 20) = SCE->regName; \ + *((addr) + 21) = SCE->regName; \ + *((addr) + 22) = SCE->regName; \ + *((addr) + 23) = SCE->regName; \ + *((addr) + 24) = SCE->regName; \ + *((addr) + 25) = SCE->regName; \ + *((addr) + 26) = SCE->regName; \ + *((addr) + 27) = SCE->regName; \ + *((addr) + 28) = SCE->regName; \ + *((addr) + 29) = SCE->regName; \ + *((addr) + 30) = SCE->regName; \ + *((addr) + 31) = SCE->regName; \ + *((addr) + 32) = SCE->regName; \ + *((addr) + 33) = SCE->regName; \ + *((addr) + 34) = SCE->regName; \ + *((addr) + 35) = SCE->regName; \ + *((addr) + 36) = SCE->regName; \ + *((addr) + 37) = SCE->regName; \ + *((addr) + 38) = SCE->regName; \ + *((addr) + 39) = SCE->regName; \ + *((addr) + 40) = SCE->regName; \ + *((addr) + 41) = SCE->regName; \ + *((addr) + 42) = SCE->regName; \ + *((addr) + 43) = SCE->regName; \ + *((addr) + 44) = SCE->regName; \ + *((addr) + 45) = SCE->regName; \ + *((addr) + 46) = SCE->regName; \ + *((addr) + 47) = SCE->regName; \ + *((addr) + 48) = SCE->regName; \ + *((addr) + 49) = SCE->regName; \ + *((addr) + 50) = SCE->regName; \ + *((addr) + 51) = SCE->regName; \ + *((addr) + 52) = SCE->regName; \ + *((addr) + 53) = SCE->regName; \ + *((addr) + 54) = SCE->regName; \ + *((addr) + 55) = SCE->regName; \ + *((addr) + 56) = SCE->regName; \ + *((addr) + 57) = SCE->regName; \ + *((addr) + 58) = SCE->regName; \ + *((addr) + 59) = SCE->regName; \ + *((addr) + 60) = SCE->regName; \ + *((addr) + 61) = SCE->regName; \ + *((addr) + 62) = SCE->regName; \ + *((addr) + 63) = SCE->regName + +// [TEST_BUSY WAIT A] +#define WAI_BUSY(value) \ + WAIT_STS(SCE->REG_00H, 31, value) + +void SC32_function001(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC32_function002(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC32_function003(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); + +void SC327_function001(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC327_function002(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC327_function003(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); + +// [R WR 32 B0 B1 B2 B3 B4 .... B31] +#define WR32_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31) + +// [R WR 48 B0 B1 B2 B3 B4 .... B47] +#define WR48_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31, value32, value33, value34, value35, value36, value37, value38, value39, \ + value40, value41, value42, value43, value44, value45, value46, value47 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31); \ + WR1_PROG(regName, value32); \ + WR1_PROG(regName, value33); \ + WR1_PROG(regName, value34); \ + WR1_PROG(regName, value35); \ + WR1_PROG(regName, value36); \ + WR1_PROG(regName, value37); \ + WR1_PROG(regName, value38); \ + WR1_PROG(regName, value39); \ + WR1_PROG(regName, value40); \ + WR1_PROG(regName, value41); \ + WR1_PROG(regName, value42); \ + WR1_PROG(regName, value43); \ + WR1_PROG(regName, value44); \ + WR1_PROG(regName, value45); \ + WR1_PROG(regName, value46); \ + WR1_PROG(regName, value47) + +// [R WR 48 B0 B1 B2 B3 B4 .... B47] +#define WR64_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31, value32, value33, value34, value35, value36, value37, value38, value39, \ + value40, value41, value42, value43, value44, value45, value46, value47, value48, value49, \ + value50, value51, value52, value53, value54, value55, value56, value57, value58, value59, \ + value60, value61, value62, value63 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31); \ + WR1_PROG(regName, value32); \ + WR1_PROG(regName, value33); \ + WR1_PROG(regName, value34); \ + WR1_PROG(regName, value35); \ + WR1_PROG(regName, value36); \ + WR1_PROG(regName, value37); \ + WR1_PROG(regName, value38); \ + WR1_PROG(regName, value39); \ + WR1_PROG(regName, value40); \ + WR1_PROG(regName, value41); \ + WR1_PROG(regName, value42); \ + WR1_PROG(regName, value43); \ + WR1_PROG(regName, value44); \ + WR1_PROG(regName, value45); \ + WR1_PROG(regName, value46); \ + WR1_PROG(regName, value47); \ + WR1_PROG(regName, value48); \ + WR1_PROG(regName, value49); \ + WR1_PROG(regName, value50); \ + WR1_PROG(regName, value51); \ + WR1_PROG(regName, value52); \ + WR1_PROG(regName, value53); \ + WR1_PROG(regName, value54); \ + WR1_PROG(regName, value55); \ + WR1_PROG(regName, value56); \ + WR1_PROG(regName, value57); \ + WR1_PROG(regName, value58); \ + WR1_PROG(regName, value59); \ + WR1_PROG(regName, value60); \ + WR1_PROG(regName, value61); \ + WR1_PROG(regName, value62); \ + WR1_PROG(regName, value63) + +#endif // __SCE_ProcCommon_h__ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/SCE_module.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/SCE_module.h new file mode 100644 index 0000000000..4cabc070dd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/SCE_module.h @@ -0,0 +1,17 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H +#include "bsp_api.h" + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ +#define SCE1_TRNG_BASE 0x400D1000UL +#define SCE1_AES_BASE 0x400D0000UL + +#endif // HW_SCE_MODULE_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h new file mode 100644 index 0000000000..b1829beae9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/hw_sce_ra_private.h @@ -0,0 +1,446 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ +#ifndef HW_SCE_RA_PRIVATE_HEADER_FILE +#define HW_SCE_RA_PRIVATE_HEADER_FILE + +#include "hw_sce_aes_private.h" + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +#define SIZE_AES_GCM_IN_DATA_BYTES (256) +#define SIZE_AES_GCM_IN_DATA_IV_LEN_BYTES (16) +#define SIZE_AES_GCM_IN_DATA_IV_GCM_LEN_BYTES (512) +#define SIZE_AES_GCM_IN_DATA_AAD_LEN_BYTES (128) + +#define SCE_AES_GCM_IN_DATA_IV_LEN_LOC (32) + +#define SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION (0x00000000U) +#define SCE_AES_IN_DATA_CMD_ECB_DECRYPTION (0x00000001U) +#define SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION (0x00000002U) +#define SCE_AES_IN_DATA_CMD_CBC_DECRYPTION (0x00000003U) +#define SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION (0x00000004U) + +#define SCE_AES_IN_DATA_CMD_CCM_128_ENC_COMMON_INIT (0U) +#define SCE_AES_IN_DATA_CMD_CCM_192_ENC_COMMON_INIT (1U) +#define SCE_AES_IN_DATA_CMD_CCM_256_ENC_COMMON_INIT (2U) +#define SCE_AES_IN_DATA_CMD_CCM_ENC_COUNTER_GENERATE (3U) +#define SCE_AES_IN_DATA_CMD_CCM_ENC_FORMAT_A_DATA (4U) +#define SCE_AES_IN_DATA_CMD_CCM_ENC_CTR_ENCRYPT (5U) +#define SCE_AES_IN_DATA_CMD_CCM_ENC_GENERATE_TAG (6U) +#define SCE_AES_IN_DATA_CMD_CCM_128_DEC_COMMON_INIT (7U) +#define SCE_AES_IN_DATA_CMD_CCM_192_DEC_COMMON_INIT (8U) +#define SCE_AES_IN_DATA_CMD_CCM_256_DEC_COMMON_INIT (9U) +#define SCE_AES_IN_DATA_CMD_CCM_DEC_COUNTER_GENERATE (10U) +#define SCE_AES_IN_DATA_CMD_CCM_DEC_CTR_DECRYPT (11U) +#define SCE_AES_IN_DATA_CMD_CCM_DEC_FORMAT_A_DATA (12U) +#define SCE_AES_IN_DATA_CMD_CCM_DEC_FORMAT_PAYLOAD (13U) +#define SCE_AES_IN_DATA_CMD_CCM_DEC_GENERATE_TAG (14U) + +/* Wrapped keys not supported on RA2; these definitions are added to let the code compile. */ +#define SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED (1) +#define SIZE_AES_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 8) +#define SIZE_AES_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 32) + +#define SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED (2) /* 192 not supported on SCE5 */ +#define SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 8) +#define SIZE_AES_192BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 32) + +#define SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED (3) +#define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8) +#define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32) + +#define R_AES_AESCNTH_INIT (0x8000UL) /*!< AESCNTH initialization: Initialization AES Circuit */ +#define R_AES_AESCNTH_DEINIT (0x0000UL) /*!< AESCNTH deinitialization: Don’t Initialize AES Circuit */ +#define R_AES_AESCNTL_GCM_MODE (0x00A0UL) /*!< AESCNTL: Assign bit of Cipher use Mode: GCM mode */ +#define R_AES_AESCNTL_128_DEC (0x0008UL) /*!< AESCNTL: Decryption 128 bit (Bit 0-3 Selection bit of Encryption/Decryption and Key Length) */ + +#define R_AES_AESCNTL_CBC_128_ENC (0x0000UL) /*!< AESCNTL: Encryption - CBC mode - 128 bits */ +#define R_AES_AESCNTL_CBC_192_ENC (0x0002UL) /*!< AESCNTL: Encryption - CBC mode - 192 bits */ +#define R_AES_AESCNTL_CBC_256_ENC (0x0004UL) /*!< AESCNTL: Encryption - CBC mode - 256 bits */ +#define R_AES_AESCNTL_CBC_128_DEC (0x0008UL) /*!< AESCNTL: Decryption - CBC mode - 128 bits */ +#define R_AES_AESCNTL_CBC_192_DEC (0x000AUL) /*!< AESCNTL: Decryption - CBC mode - 128 bits */ +#define R_AES_AESCNTL_CBC_256_DEC (0x000CUL) /*!< AESCNTL: Decryption - CBC mode - 128 bits */ + +#define R_AES_AESCNTL_ECB_128_ENC (0x0010UL) /*!< AESCNTL: Encryption - ECB mode - 128 bits */ +#define R_AES_AESCNTL_ECB_192_ENC (0x0012UL) /*!< AESCNTL: Encryption - ECB mode - 192 bits */ +#define R_AES_AESCNTL_ECB_256_ENC (0x0014UL) /*!< AESCNTL: Encryption - ECB mode - 256 bits */ +#define R_AES_AESCNTL_ECB_128_DEC (0x0018UL) /*!< AESCNTL: Decryption - ECB mode - 128 bits */ +#define R_AES_AESCNTL_ECB_192_DEC (0x001AUL) /*!< AESCNTL: Decryption - ECB mode - 128 bits */ +#define R_AES_AESCNTL_ECB_256_DEC (0x001CUL) /*!< AESCNTL: Decryption - ECB mode - 128 bits */ + +#define R_AES_AESCNTL_CTR_128_ENC (0x0040UL) /*!< AESCNTL: Encryption - CTR mode - 128 bits */ +#define R_AES_AESCNTL_CTR_192_ENC (0x0042UL) /*!< AESCNTL: Encryption - CTR mode - 192 bits */ +#define R_AES_AESCNTL_CTR_256_ENC (0x0044UL) /*!< AESCNTL: Encryption - CTR mode - 256 bits */ +#define R_AES_AESCNTL_CTR_128_DEC (0x0048UL) /*!< AESCNTL: Decryption - CTR mode - 128 bits */ +#define R_AES_AESCNTL_CTR_192_DEC (0x004AUL) /*!< AESCNTL: Decryption - CTR mode - 128 bits */ +#define R_AES_AESCNTL_CTR_256_DEC (0x004CUL) /*!< AESCNTL: Decryption - CTR mode - 128 bits */ + +#define R_AES_AESCNTL_CMAC_128_ENC (0x0080UL) /*!< AESCNTL: Encryption - CMAC mode - 128 bits */ +#define R_AES_AESCNTL_CMAC_192_ENC (0x0082UL) /*!< AESCNTL: Encryption - CMAC mode - 192 bits */ +#define R_AES_AESCNTL_CMAC_256_ENC (0x0084UL) /*!< AESCNTL: Encryption - CMAC mode - 256 bits */ +#define R_AES_AESCNTL_CMAC_128_DEC (0x0088UL) /*!< AESCNTL: Decryption - CMAC mode - 128 bits */ +#define R_AES_AESCNTL_CMAC_192_DEC (0x008AUL) /*!< AESCNTL: Decryption - CMAC mode - 128 bits */ +#define R_AES_AESCNTL_CMAC_256_DEC (0x008CUL) /*!< AESCNTL: Decryption - CMAC mode - 128 bits */ + +#define R_AES_AESCNTL_GCM_128_ENC (0x00A0UL) /*!< AESCNTL: Encryption - GCM mode - 128 bits */ +#define R_AES_AESCNTL_GCM_192_ENC (0x00A2UL) /*!< AESCNTL: Encryption - GCM mode - 192 bits */ +#define R_AES_AESCNTL_GCM_256_ENC (0x00A4UL) /*!< AESCNTL: Encryption - GCM mode - 256 bits */ +#define R_AES_AESCNTL_GCM_128_DEC (0x00A8UL) /*!< AESCNTL: Decryption - GCM mode - 128 bits */ +#define R_AES_AESCNTL_GCM_192_DEC (0x00AAUL) /*!< AESCNTL: Decryption - GCM mode - 128 bits */ +#define R_AES_AESCNTL_GCM_256_DEC (0x00ACUL) /*!< AESCNTL: Decryption - GCM mode - 128 bits */ + +#define R_AES_AESCNTL_CCM_128_ENC (0x00C0UL) /*!< AESCNTL: Encryption - CCM mode - 128 bits */ +#define R_AES_AESCNTL_CCM_192_ENC (0x00C2UL) /*!< AESCNTL: Encryption - CCM mode - 192 bits */ +#define R_AES_AESCNTL_CCM_256_ENC (0x00C4UL) /*!< AESCNTL: Encryption - CCM mode - 256 bits */ +#define R_AES_AESCNTL_CCM_128_DEC (0x00C8UL) /*!< AESCNTL: Decryption - CCM mode - 128 bits */ +#define R_AES_AESCNTL_CCM_192_DEC (0x00CAUL) /*!< AESCNTL: Decryption - CCM mode - 128 bits */ +#define R_AES_AESCNTL_CCM_256_DEC (0x00CCUL) /*!< AESCNTL: Decryption - CCM mode - 128 bits */ + +#define R_AES_AESDCNTL_BIT_2_3_MODE_1 (0x0008UL) /*!< AESDCNTL: Key update assign bit: Enable + First block contents control assign bit: Use (AES-ECB, AES-GCM) */ +#define R_AES_AESDCNTL_BIT_2_3_MODE_2 (0x000CUL) /*!< AESDCNTL: Key update assign bit: Enable + First block contents control assign bit: Not use (AES-CBC, AES-CTR) */ +#define R_AES_AESDCNTL_CALCULATE_START (0x0003UL) /*!< AESDCNTL: Start AES calculation - Start reflect AES Encryption/Decryption calculation result to AESODATnRegister */ +#define R_AES_AESDCNTL_BIT_2 (0x0004UL) /*!< AESDCNTL: Bit 2 */ +#define R_AES_AESDCNTL_BIT_3 (0x0008UL) /*!< AESDCNTL: Bit 3 */ +#define R_AES_AESDCNTL_BIT_4 (0x0010UL) /*!< AESDCNTL: Bit 4 */ +#define R_AES_AESDCNTL_BIT_5 (0x0020UL) /*!< AESDCNTL: Bit 5 */ +#define R_AES_AESDCNTL_BIT_6 (0x0040UL) /*!< AESDCNTL: Bit 6 */ + +#define R_AES_AESDCNTL_FIST_SET (0x0004UL) /*!< AESDCNTL: FIRST = 1: The result of the previous calculation is not used for the calculation of the first block */ +#define R_AES_AESDCNTL_NEW_KEY_SET (0x0008UL) /*!< AESDCNTL: NEW_KEY = 1: Key data are updated using the data set in the AESKEYn registers */ +#define R_AES_AESDCNTL_ATTR_CCM_MODE_1 (0x0020UL) /*!< AESDCNTL: ATTR[2:0] = 001: The input data as the parameter B0 of the formatting function */ +#define R_AES_AESDCNTL_ATTR_CCM_MODE_2 (0x0040UL) /*!< AESDCNTL: ATTR[2:0] = 010: In encryption: Setting prohibited, In decryption: A ciphertext */ +#define R_AES_AESDCNTL_ATTR_CCM_MODE_3 (0x0060UL) /*!< AESDCNTL: ATTR[2:0] = 011: The input data as A (associated data) of the formatting function */ +#define R_AES_AESDCNTL_ATTR_CCM_MODE_4 (0x0080UL) /*!< AESDCNTL: ATTR[2:0] = 100: Indicating the input data are a plaintext */ +#define R_AES_AESDCNTL_ATTR_CCM_MODE_5 (0x0000UL) /*!< AESDCNTL: ATTR[2:0] = 000: In encryption: The dummy input data used for calculation of T XOR MSBTlen(S0) + * In decryption: Setting prohibited */ +#define R_AES_AESDCNTL_ATTR_CCM_MODE_6 (0x00A0UL) /*!< AESDCNTL: ATTR[2:0] = 101: In encryption: Setting prohibited + * In decryption: The input data to be calculated by T XOR MSBTlen(S0) */ + +#define R_AES_AESSTSL_BIT_5 (0x0020UL) /*!< AESSTSL: Bit 5: Status Bit to show AES operation status */ +#define R_AES_AESSTSL_CALCULATE_COMPLETED (0x0003UL) /*!< AESSTSL: Bit 0-1: Status Bit to show AES Encryption/Decryption completion */ +#define R_AES_AESSTSCL_DATA_CLEAN (0x0003UL) /*!< AESSTSCL: Bit 0-1: clear bit1.0 state in AES Status Register */ + +#define R_AES_AESDCNTH_EXECUTE_TAG_CALCULATION (0x0002UL) /*!< AESDCNTH: Bit 1 = 1: The calculation of tag is executed, and result is stored in the AESODATn registers */ +#define R_AES_AESDCNTH_NOT_EXECUTE_TAG_CALCULATION (0x0000UL) /*!< AESDCNTH: Bit 1 = 0: Don't execute calculation of tag */ + +#define HW_AES_DATA_FIT_TO_BLOCK_SIZE(x) ((uint32_t) x & 0xFFFFFFF0) +#define HW_AES_DATA_GET_LAST_REMAINS(x) ((uint32_t) x & 0x0000000F) +#define HW_32BIT_ALIGNED(x) !(x & 0x03) + +/********************************************************************************************************************** + * Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions + *********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ +uint32_t change_endian_long(uint32_t data); +void hw_aes_set_key(uint8_t * key, uint32_t KeyLen); +void hw_aes_set_iv(uint8_t * initialize_vetor); +fsp_err_t hw_aes_start(uint8_t * input, uint8_t * output, uint32_t block); +void hw_aes_ccm_mode_start(uint8_t * input, uint8_t * output, uint32_t block); +fsp_err_t hw_gcm_calculation(uint8_t * input, + uint8_t * output, + uint32_t data_len, + uint8_t * atag, + uint8_t * initial_vector, + uint32_t iv_len, + uint8_t * aad, + uint32_t aad_len); + +void HW_SCE_AesCcmDecryptCounterGenerate(uint32_t InData_TextLength, + uint32_t InData_Hdrlen, + uint32_t InData_MacLength, + uint32_t InData_IVLength); + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); + +void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +void HW_SCE_Aes192EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +void HW_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void); + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void HW_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes128GcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void HW_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes128GcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void HW_SCE_Aes192GcmEncryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes192GcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void HW_SCE_Aes192GcmDecryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes192GcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void HW_SCE_Aes256GcmEncryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes256GcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void HW_SCE_Aes256GcmDecryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes256GcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); +fsp_err_t HW_SCE_AES_128CtrEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); +fsp_err_t HW_SCE_AES_192CtrEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); +fsp_err_t HW_SCE_AES_256CtrEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); +fsp_err_t HW_SCE_AES_128CtrDecrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t HW_SCE_AES_192CtrDecrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t HW_SCE_AES_256CtrDecrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len); + +fsp_err_t HW_SCE_Aes192CcmEncryptInitSub(const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len); + +fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len); + +void HW_SCE_Aes128CcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); + +void HW_SCE_Aes192CcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); + +void HW_SCE_Aes256CcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub(const uint32_t InData_Text[], uint32_t OutData_Text[], + uint32_t OutData_MAC[]); + +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub(const uint32_t InData_Text[], uint32_t OutData_Text[], + uint32_t OutData_MAC[]); + +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(const uint32_t InData_Text[], uint32_t OutData_Text[], + uint32_t OutData_MAC[]); + +fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len); + +fsp_err_t HW_SCE_Aes192CcmDecryptInitSub(const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len); + +fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len); + +void HW_SCE_Aes128CcmDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); + +void HW_SCE_Aes192CcmDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); + +void HW_SCE_Aes256CcmDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]); + +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]); + +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]); + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral(uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum); + +#endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c new file mode 100644 index 0000000000..ef5435d3d5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/r_sce_AES_adapt.c @@ -0,0 +1,1532 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ +#include "hw_sce_ra_private.h" +#include "bsp_api.h" +#include + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/* Waitting time to make sure calculation is finished + * Refer to Table 1.3 Numbers of Clock Cycles Required for Processing in the CCM Mode + * Waiting time for 91 Clock Cycles Required for Processing in the CCM Mode with PCLKB 32MHz + * Note: waiting for 91 clock cycles is still not enough for encryption of AES-CCM 256 bits key length. + * Must be to 146 clock cycles. + * */ + +#define HW_SCE_AES_CCM_WAITING_CYCLES (146U) +#define HW_SCE_FREQUENCY_IN_HZ (1000000U) +#define HW_SCE_AES2_MAX_WAIT_USECONDS (0xFFFFFFFF) // Set the maximum value for uint32_t +#define HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS 10 // Set a 10 microsecond status check interval + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Imported global variables and functions + ***********************************************************************************************************************/ + +extern void HW_SCE_AesCcmEncryptKeyOperation(uint32_t * InData_KeyIndex, + uint32_t InData_KeyType, + uint32_t * InData_IV, + uint32_t InData_IVLength); + +extern void HW_SCE_AesCcmDecryptKeyOperation(uint32_t * InData_KeyIndex, + uint32_t InData_KeyType, + uint32_t * InData_IV, + uint32_t InData_IVLength); + +extern void HW_SCE_AesCcmEncryptCounterGenerate(uint32_t InData_TextLength, + uint32_t InData_Hdrlen, + uint32_t InData_MacLength, + uint32_t InData_IVLength); + +extern void HW_SCE_AesCcmEncryptInputAssociatedData(uint32_t * InData_Header, uint32_t InData_Hdrlen); + +extern void HW_SCE_AesCcmDecryptInputAssociatedData(uint32_t * InData_Header, uint32_t InData_Hdrlen); + +extern void HW_SCE_AesCcmEncryptPlaintextInputInit(); + +extern void HW_SCE_AesCcmEncryptGenerateTag(uint32_t * OutData_MAC); + +extern void hw_aes_ccm_decrypt_init(uint32_t indata_cmd); + +/*********************************************************************************************************************** + * Exported global variables + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +static uint8_t __attribute__((aligned(32))) InputData_DataA[SIZE_AES_GCM_IN_DATA_AAD_LEN_BYTES] = {0}; +static uint8_t __attribute__((aligned(32))) InputData_IV_GCM[SIZE_AES_GCM_IN_DATA_IV_GCM_LEN_BYTES] = {0}; +static uint8_t InputData_IV_GCM_LEN_BYTES = 0; + +uint32_t change_endian_long (uint32_t a) +{ + return __REV(a); +} + +/*********************************************************************************************************************** + * Function Name: hw_aes_set_key + * Description : This function move the key from specified address (1st arg "key" to AES peripheral register with define + * length (2nd arg "KeyLen") + * Arguments : key : key data area + * KeyLen : key length in bits + * Return Value : None + ***********************************************************************************************************************/ +void hw_aes_set_key (uint8_t * key, uint32_t KeyLen) +{ + uint16_t * ptr = (uint16_t *) key; + + if (KeyLen > SIZE_AES_192BIT_KEYLEN_BYTES) + { + R_AES_B->AESKEY7.AESKEYH = *ptr; + R_AES_B->AESKEY7.AESKEYL = *(ptr + 1); + R_AES_B->AESKEY6.AESKEYH = *(ptr + 2); + R_AES_B->AESKEY6.AESKEYL = *(ptr + 3); + ptr += 4; + } + + if (KeyLen > SIZE_AES_128BIT_KEYLEN_BYTES) + { + R_AES_B->AESKEY5.AESKEYH = *ptr; + R_AES_B->AESKEY5.AESKEYL = *(ptr + 1); + R_AES_B->AESKEY4.AESKEYH = *(ptr + 2); + R_AES_B->AESKEY4.AESKEYL = *(ptr + 3); + ptr += 4; + } + + R_AES_B->AESKEY3.AESKEYH = *ptr; + R_AES_B->AESKEY3.AESKEYL = *(ptr + 1); + R_AES_B->AESKEY2.AESKEYH = *(ptr + 2); + R_AES_B->AESKEY2.AESKEYL = *(ptr + 3); + R_AES_B->AESKEY1.AESKEYH = *(ptr + 4); + R_AES_B->AESKEY1.AESKEYL = *(ptr + 5); + R_AES_B->AESKEY0.AESKEYH = *(ptr + 6); + R_AES_B->AESKEY0.AESKEYL = *(ptr + 7); +} + +/*********************************************************************************************************************** + * Function Name: hw_aes_set_iv + * Description : This function move Initialize vector from specified address (1st arg. "iv") to AES register. + * Arguments : iv : Initialization vector area (16 byte) + * Return Value : None + ***********************************************************************************************************************/ +void hw_aes_set_iv (uint8_t * initialize_vector) +{ + uint16_t * p_in = (uint16_t *) initialize_vector; + + R_AES_B->AESIV3.AESIVH = *p_in; + R_AES_B->AESIV3.AESIVL = *(p_in + 1); + R_AES_B->AESIV2.AESIVH = *(p_in + 2); + R_AES_B->AESIV2.AESIVL = *(p_in + 3); + R_AES_B->AESIV1.AESIVH = *(p_in + 4); + R_AES_B->AESIV1.AESIVL = *(p_in + 5); + R_AES_B->AESIV0.AESIVH = *(p_in + 6); + R_AES_B->AESIV0.AESIVL = *(p_in + 7); +} + +/*********************************************************************************************************************** + * Function Name: hw_aes_set_plaintext + * Description : This function move input data from specified address(1st arg. "ptext") to AES Data Input register. + * Arguments : ptext : Input data area (block * 16bytes) + * Return Value : None + ***********************************************************************************************************************/ +static void hw_aes_set_plaintext (uint8_t * ptext) +{ + uint16_t * p_in = (uint16_t *) ptext; + + R_AES_B->AESIDAT3.AESIDATH = *p_in; + R_AES_B->AESIDAT3.AESIDATL = *(p_in + 1); + R_AES_B->AESIDAT2.AESIDATH = *(p_in + 2); + R_AES_B->AESIDAT2.AESIDATL = *(p_in + 3); + R_AES_B->AESIDAT1.AESIDATH = *(p_in + 4); + R_AES_B->AESIDAT1.AESIDATL = *(p_in + 5); + R_AES_B->AESIDAT0.AESIDATH = *(p_in + 6); + R_AES_B->AESIDAT0.AESIDATL = *(p_in + 7); +} + +/*********************************************************************************************************************** + * Function Name: hw_aes_get_ciphertext + * Description : This function move AES register output to specified address (1st arg. "output"). + * Arguments : output : output data area (block * 16bytes) + * Return Value : None + ***********************************************************************************************************************/ +static void hw_aes_get_ciphertext (uint8_t * output) +{ + uint16_t * ptr; + ptr = (uint16_t *) output; + + *ptr = R_AES_B->AESODAT3.AESODATH; + *(ptr + 1) = R_AES_B->AESODAT3.AESODATL; + *(ptr + 2) = R_AES_B->AESODAT2.AESODATH; + *(ptr + 3) = R_AES_B->AESODAT2.AESODATL; + *(ptr + 4) = R_AES_B->AESODAT1.AESODATH; + *(ptr + 5) = R_AES_B->AESODAT1.AESODATL; + *(ptr + 6) = R_AES_B->AESODAT0.AESODATH; + *(ptr + 7) = R_AES_B->AESODAT0.AESODATL; +} + +fsp_err_t hw_aes_start (uint8_t * input, uint8_t * output, uint32_t block) +{ + uint8_t * ptr; + uint8_t * ptr_out; + uint32_t block_ctr = 0; + uint32_t wait_count_useconds = HW_SCE_AES2_MAX_WAIT_USECONDS; + + ptr = input; + ptr_out = output; + block_ctr = 0; + do + { + hw_aes_set_plaintext(ptr); + R_AES_B->AESDCNTL |= R_AES_AESDCNTL_CALCULATE_START; + + while (((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) && (wait_count_useconds > 0U)) + { + R_BSP_SoftwareDelay(HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS, BSP_DELAY_UNITS_MICROSECONDS); + wait_count_useconds -= HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS; + } + + if (0 == wait_count_useconds) + { + return FSP_ERR_TIMEOUT; + } + + if ((R_AES_B->AESSTSL & R_AES_AESSTSL_CALCULATE_COMPLETED) != 0) + { + hw_aes_get_ciphertext(ptr_out); + R_AES_B->AESSTSCL = R_AES_AESSTSCL_DATA_CLEAN; + R_AES_B->AESDCNTL = 0; + } + + ptr += 16; + ptr_out += 16; + block_ctr++; + } while (block_ctr < block); + + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** + * Function Name: hw_aes_ccm_mode_start + * Description : This function move input data from specified address(1st arg. "input") to AES Data Input register + * and move AES register output to specified address(2nd arg. "output"). + * In case 1st arg. "input" is NULL, this function move AES register output to "output" only. + * In case 2nd arg. "output" is NULL, this function move input data from "input" to AES Data Input register only. + * Arguments : input : Input data area (block * 16bytes) + * output: Output data area (block * 16bytes) + * Return Value : None + ***********************************************************************************************************************/ +void hw_aes_ccm_mode_start (uint8_t * input, uint8_t * output, uint32_t block) +{ + uint32_t block_ctr; + uint32_t pclkb_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / HW_SCE_FREQUENCY_IN_HZ; + uint32_t iclk_mhz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_ICLK) / HW_SCE_FREQUENCY_IN_HZ; + uint8_t ratio = 0U; + + while (iclk_mhz > pclkb_mhz) + { + iclk_mhz = iclk_mhz >> 1U; + ratio++; + } + + for (block_ctr = 0U; block_ctr < block; block_ctr++) + { + if (NULL != input) + { + hw_aes_set_plaintext(input); + R_AES_B->AESDCNTL |= R_AES_AESDCNTL_CALCULATE_START; + bsp_prv_software_delay_loop(BSP_DELAY_LOOPS_CALCULATE(HW_SCE_AES_CCM_WAITING_CYCLES << ratio)); + } + + if (NULL != output) + { + hw_aes_get_ciphertext(output); + output += SIZE_AES_BLOCK_BYTES; + } + + input += SIZE_AES_BLOCK_BYTES; + } +} + +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub (uint32_t * OutData_KeyIndex) +{ + FSP_PARAMETER_NOT_USED(OutData_KeyIndex); + + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub (uint32_t * OutData_KeyIndex) +{ + FSP_PARAMETER_NOT_USED(OutData_KeyIndex); + + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub (uint32_t * OutData_KeyIndex) +{ + FSP_PARAMETER_NOT_USED(OutData_KeyIndex); + + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Cmd == (const uint32_t *) 0) || + (InData_KeyIndex == (const uint32_t *) 0) || + (InData_IV == (const uint32_t *) 0)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } +#endif + + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_192BIT_KEYLEN_BYTES); + hw_aes_set_iv((uint8_t *) InData_IV); + switch (change_endian_long(*InData_Cmd)) + { + case SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_192_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_1; + R_AES_B->AESCNTL = R_AES_AESCNTL_ECB_192_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_ECB_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_1; + R_AES_B->AESCNTL = R_AES_AESCNTL_ECB_192_DEC; + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CBC_192_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CBC_192_DEC; + break; + } + } + + return FSP_SUCCESS; +} + +void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, MAX_CNT / 4); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub (void) +{ + uint32_t wait_count_useconds = HW_SCE_AES2_MAX_WAIT_USECONDS; + + while (((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) && (wait_count_useconds > 0U)) + { + R_BSP_SoftwareDelay(HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS, BSP_DELAY_UNITS_MICROSECONDS); + wait_count_useconds -= HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS; + } + + if (0 == wait_count_useconds) + { + return FSP_ERR_TIMEOUT; + } + + if ((R_AES_B->AESSTSL & R_AES_AESSTSL_CALCULATE_COMPLETED) != 0) + { + R_AES_B->AESSTSCL = R_AES_AESSTSCL_DATA_CLEAN; + R_AES_B->AESDCNTL = 0; + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Cmd == (const uint32_t *) 0) || + (InData_KeyIndex == (const uint32_t *) 0) || + (InData_IV == (const uint32_t *) 0)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } +#endif + + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_128BIT_KEYLEN_BYTES); + hw_aes_set_iv((uint8_t *) InData_IV); + switch (change_endian_long(*InData_Cmd)) + { + case SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_128_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_1; + R_AES_B->AESCNTL = R_AES_AESCNTL_ECB_128_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_ECB_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_1; + R_AES_B->AESCNTL = R_AES_AESCNTL_ECB_128_DEC; + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CBC_128_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CBC_128_DEC; + break; + } + } + + return FSP_SUCCESS; +} + +void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, MAX_CNT / 4); +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub (void) +{ + uint32_t wait_count_useconds = HW_SCE_AES2_MAX_WAIT_USECONDS; + + while (((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) && (wait_count_useconds > 0U)) + { + R_BSP_SoftwareDelay(HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS, BSP_DELAY_UNITS_MICROSECONDS); + wait_count_useconds -= HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS; + } + + if (0 == wait_count_useconds) + { + return FSP_ERR_TIMEOUT; + } + + if ((R_AES_B->AESSTSL & R_AES_AESSTSL_CALCULATE_COMPLETED) != 0) + { + R_AES_B->AESSTSCL = R_AES_AESSTSCL_DATA_CLEAN; + R_AES_B->AESDCNTL = 0; + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Cmd == (const uint32_t *) 0) || + (InData_KeyIndex == (const uint32_t *) 0) || + (InData_IV == (const uint32_t *) 0)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } +#endif + + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_256BIT_KEYLEN_BYTES); + hw_aes_set_iv((uint8_t *) InData_IV); + switch (change_endian_long(*InData_Cmd)) + { + case SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_256_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_1; + R_AES_B->AESCNTL = R_AES_AESCNTL_ECB_256_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_ECB_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_1; + R_AES_B->AESCNTL = R_AES_AESCNTL_ECB_256_DEC; + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CBC_256_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_DECRYPTION: + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + R_AES_B->AESCNTL = R_AES_AESCNTL_CBC_256_DEC; + break; + } + } + + return FSP_SUCCESS; +} + +void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, MAX_CNT / 4); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub (void) +{ + uint32_t wait_count_useconds = HW_SCE_AES2_MAX_WAIT_USECONDS; + + while (((R_AES_B->AESSTSL & R_AES_AESSTSL_BIT_5) != 0) && (wait_count_useconds > 0U)) + { + R_BSP_SoftwareDelay(HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS, BSP_DELAY_UNITS_MICROSECONDS); + wait_count_useconds -= HW_SCE_AES2_AESSTSL_CHECK_INTERVAL_USECONDS; + } + + if (0 == wait_count_useconds) + { + return FSP_ERR_TIMEOUT; + } + + if ((R_AES_B->AESSTSL & R_AES_AESSTSL_CALCULATE_COMPLETED) != 0) + { + R_AES_B->AESSTSCL = R_AES_AESSTSCL_DATA_CLEAN; + R_AES_B->AESDCNTL = 0; + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub (uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + R_AES_B->AESCNTL = R_AES_AESCNTL_GCM_128_ENC; + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_128BIT_KEYLEN_BYTES); + InputData_IV_GCM_LEN_BYTES = (uint8_t) *((unsigned int *) InData_KeyIndex + SCE_AES_GCM_IN_DATA_IV_LEN_LOC); + memcpy(&InputData_IV_GCM[0], (uint8_t *) InData_IV, InputData_IV_GCM_LEN_BYTES); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes128GcmEncryptUpdateAADSub (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(MAX_CNT); + if (InData_DataA != 0) + { + memcpy(&InputData_DataA[0], (uint8_t *) InData_DataA, sizeof(InputData_DataA)); + } +} + +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub (void) +{ +} + +void HW_SCE_Aes128GcmEncryptUpdateSub (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub (uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT) +{ + fsp_err_t status; + status = hw_gcm_calculation((uint8_t *) InData_Text, + (uint8_t *) OutData_Text, + *InData_TextLen, + (uint8_t *) OutData_DataT, + &InputData_IV_GCM[0], + InputData_IV_GCM_LEN_BYTES, + &InputData_DataA[0], + *InData_DataALen); + + return status; +} + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub (uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + R_AES_B->AESCNTL = R_AES_AESCNTL_GCM_128_DEC; + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_128BIT_KEYLEN_BYTES); + InputData_IV_GCM_LEN_BYTES = (uint8_t) *((unsigned int *) InData_KeyIndex + SCE_AES_GCM_IN_DATA_IV_LEN_LOC); + memcpy(&InputData_IV_GCM[0], (uint8_t *) InData_IV, InputData_IV_GCM_LEN_BYTES); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes128GcmDecryptUpdateAADSub (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(MAX_CNT); + if (InData_DataA != 0) + { + memcpy(&InputData_DataA[0], (uint8_t *) InData_DataA, sizeof(InputData_DataA)); + } +} + +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub (void) +{ +} + +void HW_SCE_Aes128GcmDecryptUpdateSub (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub (uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text) +{ + uint8_t Tag[16]; + uint8_t temp; + fsp_err_t status; + uint8_t Target_Tag[16] = {0}; + memcpy(&Target_Tag[0], InData_DataT, (uint8_t) *InData_DataTLen); + + status = hw_gcm_calculation((uint8_t *) InData_Text, + (uint8_t *) OutData_Text, + *InData_TextLen, + &Tag[0], + &InputData_IV_GCM[0], + InputData_IV_GCM_LEN_BYTES, + &InputData_DataA[0], + *InData_DataALen); + if (status != FSP_SUCCESS) + { + return FSP_ERR_CRYPTO_UNKNOWN; + } + + /* Athentication Tag Verification*/ + if ((uint8_t) *InData_DataTLen != 0) + { + for (uint8_t iLoop = 0; iLoop < (uint8_t) *InData_DataTLen; iLoop++) + { + temp = Target_Tag[iLoop]; + if (temp != Tag[iLoop]) + { + status = FSP_ERR_INVALID_ARGUMENT; + break; + } + } + + if (status == FSP_ERR_INVALID_ARGUMENT) + { + memset(OutData_Text, 0, *InData_TextLen); + + return FSP_ERR_CRYPTO_UNKNOWN; + } + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub (uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + R_AES_B->AESCNTL = R_AES_AESCNTL_GCM_192_ENC; + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_192BIT_KEYLEN_BYTES); + InputData_IV_GCM_LEN_BYTES = (uint8_t) *((unsigned int *) InData_KeyIndex + SCE_AES_GCM_IN_DATA_IV_LEN_LOC); + memcpy(&InputData_IV_GCM[0], (uint8_t *) InData_IV, InputData_IV_GCM_LEN_BYTES); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes192GcmEncryptUpdateAADSub (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(MAX_CNT); + if (InData_DataA != 0) + { + memcpy(&InputData_DataA[0], (uint8_t *) InData_DataA, sizeof(InputData_DataA)); + } +} + +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub (void) +{ +} + +void HW_SCE_Aes192GcmEncryptUpdateSub (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub (uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT) +{ + fsp_err_t status; + status = hw_gcm_calculation((uint8_t *) InData_Text, + (uint8_t *) OutData_Text, + *InData_TextLen, + (uint8_t *) OutData_DataT, + &InputData_IV_GCM[0], + InputData_IV_GCM_LEN_BYTES, + &InputData_DataA[0], + *InData_DataALen); + + return status; +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub (uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + R_AES_B->AESCNTL = R_AES_AESCNTL_GCM_192_DEC; + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_192BIT_KEYLEN_BYTES); + InputData_IV_GCM_LEN_BYTES = (uint8_t) *((unsigned int *) InData_KeyIndex + SCE_AES_GCM_IN_DATA_IV_LEN_LOC); + memcpy(&InputData_IV_GCM[0], (uint8_t *) InData_IV, InputData_IV_GCM_LEN_BYTES); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes192GcmDecryptUpdateAADSub (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(MAX_CNT); + if (InData_DataA != 0) + { + memcpy(&InputData_DataA[0], (uint8_t *) InData_DataA, sizeof(InputData_DataA)); + } +} + +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub (void) +{ +} + +void HW_SCE_Aes192GcmDecryptUpdateSub (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub (uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text) +{ + uint8_t Tag[16]; + uint8_t temp; + fsp_err_t status; + uint8_t Target_Tag[16] = {0}; + memcpy(&Target_Tag[0], InData_DataT, (uint8_t) *InData_DataTLen); + + status = hw_gcm_calculation((uint8_t *) InData_Text, + (uint8_t *) OutData_Text, + *InData_TextLen, + &Tag[0], + &InputData_IV_GCM[0], + InputData_IV_GCM_LEN_BYTES, + &InputData_DataA[0], + *InData_DataALen); + if (status != FSP_SUCCESS) + { + return FSP_ERR_CRYPTO_UNKNOWN; + } + + /* Athentication Tag Verification*/ + if (*InData_DataTLen != 0) + { + for (uint32_t iLoop = 0; iLoop < (uint8_t) *InData_DataTLen; iLoop++) + { + temp = Target_Tag[iLoop]; + if (temp != Tag[iLoop]) + { + status = FSP_ERR_INVALID_ARGUMENT; + break; + } + } + + if (status == FSP_ERR_INVALID_ARGUMENT) + { + memset(OutData_Text, 0, *InData_TextLen); + + return FSP_ERR_CRYPTO_UNKNOWN; + } + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub (uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + R_AES_B->AESCNTL = R_AES_AESCNTL_GCM_256_ENC; + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_256BIT_KEYLEN_BYTES); + InputData_IV_GCM_LEN_BYTES = (uint8_t) *((unsigned int *) InData_KeyIndex + SCE_AES_GCM_IN_DATA_IV_LEN_LOC); + memcpy(&InputData_IV_GCM[0], (uint8_t *) InData_IV, InputData_IV_GCM_LEN_BYTES); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes256GcmEncryptUpdateAADSub (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(MAX_CNT); + if (InData_DataA != 0) + { + memcpy(&InputData_DataA[0], (uint8_t *) InData_DataA, sizeof(InputData_DataA)); + } +} + +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub (void) +{ +} + +void HW_SCE_Aes256GcmEncryptUpdateSub (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub (uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT) +{ + fsp_err_t status; + status = hw_gcm_calculation((uint8_t *) InData_Text, + (uint8_t *) OutData_Text, + *InData_TextLen, + (uint8_t *) OutData_DataT, + &InputData_IV_GCM[0], + InputData_IV_GCM_LEN_BYTES, + &InputData_DataA[0], + *InData_DataALen); + + return status; +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub (uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + R_AES_B->AESCNTL = R_AES_AESCNTL_GCM_256_DEC; + hw_aes_set_key((uint8_t *) InData_KeyIndex, SIZE_AES_256BIT_KEYLEN_BYTES); + InputData_IV_GCM_LEN_BYTES = (uint8_t) *((unsigned int *) InData_KeyIndex + SCE_AES_GCM_IN_DATA_IV_LEN_LOC); + memcpy((uint8_t *) &InputData_IV_GCM[0], (uint8_t *) InData_IV, InputData_IV_GCM_LEN_BYTES); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes256GcmDecryptUpdateAADSub (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(MAX_CNT); + if (InData_DataA != 0) + { + memcpy((uint8_t *) &InputData_DataA[0], (uint8_t *) InData_DataA, sizeof(InputData_DataA)); + } +} + +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub (void) +{ +} + +void HW_SCE_Aes256GcmDecryptUpdateSub (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub (uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text) +{ + uint8_t Tag[16]; + uint8_t temp; + fsp_err_t status; + uint8_t Target_Tag[16] = {0}; + memcpy(&Target_Tag[0], InData_DataT, (uint8_t) *InData_DataTLen); + + status = hw_gcm_calculation((uint8_t *) InData_Text, + (uint8_t *) OutData_Text, + *InData_TextLen, + &Tag[0], + &InputData_IV_GCM[0], + InputData_IV_GCM_LEN_BYTES, + InputData_DataA, + *InData_DataALen); + if (status != 0) + { + return FSP_ERR_CRYPTO_UNKNOWN; + } + + /* Athentication Tag Verification*/ + if (*InData_DataTLen != 0) + { + for (uint32_t iLoop = 0; iLoop < (uint8_t) *InData_DataTLen; iLoop++) + { + temp = Target_Tag[iLoop]; + if (temp != Tag[iLoop]) + { + status = FSP_ERR_INVALID_ARGUMENT; + break; + } + } + + if (status == FSP_ERR_INVALID_ARGUMENT) + { + memset(OutData_Text, 0, *InData_TextLen); + + return FSP_ERR_CRYPTO_UNKNOWN; + } + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + uint32_t InData_IVLen = InData_Cmd[0]; + uint32_t InData_MACLen = InData_Cmd[1]; + + /* Apply key operations */ + HW_SCE_AesCcmEncryptKeyOperation((uint32_t *) InData_KeyIndex, + SIZE_AES_128BIT_KEYLEN_BYTES, + (uint32_t *) InData_IV, + InData_IVLen); + + /* Formatting function and counter generation function */ + HW_SCE_AesCcmEncryptCounterGenerate(*InData_TextLen, Header_Len, InData_MACLen, InData_IVLen); + + /* Apply formating function with associated data */ + HW_SCE_AesCcmEncryptInputAssociatedData((uint32_t *) InData_Header, Header_Len); + + /* Plaintext input initialization */ + HW_SCE_AesCcmEncryptPlaintextInputInit(); + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes192CcmEncryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + uint32_t InData_IVLen = InData_Cmd[0]; + uint32_t InData_MACLen = InData_Cmd[1]; + + /* Apply key operations */ + HW_SCE_AesCcmEncryptKeyOperation((uint32_t *) InData_KeyIndex, + SIZE_AES_192BIT_KEYLEN_BYTES, + (uint32_t *) InData_IV, + InData_IVLen); + + /* Formatting function and counter generation function */ + HW_SCE_AesCcmEncryptCounterGenerate(*InData_TextLen, Header_Len, InData_MACLen, InData_IVLen); + + /* Apply formating function with associated data */ + HW_SCE_AesCcmEncryptInputAssociatedData((uint32_t *) InData_Header, Header_Len); + + /* Plaintext input initialization */ + HW_SCE_AesCcmEncryptPlaintextInputInit(); + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes256CcmEncryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + uint32_t InData_IVLen = InData_Cmd[0]; + uint32_t InData_MACLen = InData_Cmd[1]; + + /* Apply key operations */ + HW_SCE_AesCcmEncryptKeyOperation((uint32_t *) InData_KeyIndex, + SIZE_AES_256BIT_KEYLEN_BYTES, + (uint32_t *) InData_IV, + InData_IVLen); + + /* Formatting function and counter generation function */ + HW_SCE_AesCcmEncryptCounterGenerate(*InData_TextLen, Header_Len, InData_MACLen, InData_IVLen); + + /* Apply formating function with associated data */ + HW_SCE_AesCcmEncryptInputAssociatedData((uint32_t *) InData_Header, Header_Len); + + /* Plaintext input initialization */ + HW_SCE_AesCcmEncryptPlaintextInputInit(); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes128CcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + hw_aes_ccm_mode_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, MAX_CNT / 4); +} + +void HW_SCE_Aes192CcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + hw_aes_ccm_mode_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, MAX_CNT / 4); +} + +void HW_SCE_Aes256CcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + hw_aes_ccm_mode_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, MAX_CNT / 4); +} + +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub (const uint32_t InData_Text[], uint32_t OutData_Text[], + uint32_t OutData_MAC[]) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + + /* Generate tag */ + HW_SCE_AesCcmEncryptGenerateTag(OutData_MAC); + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub (const uint32_t InData_Text[], uint32_t OutData_Text[], + uint32_t OutData_MAC[]) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + + /* Generate tag */ + HW_SCE_AesCcmEncryptGenerateTag(OutData_MAC); + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub (const uint32_t InData_Text[], uint32_t OutData_Text[], + uint32_t OutData_MAC[]) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + + /* Generate tag */ + HW_SCE_AesCcmEncryptGenerateTag(OutData_MAC); + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes128CcmDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + uint32_t InData_IVLen = InData_Cmd[0]; + + /* + * Check length requirements: SP800-38C A.1 + * Additional requirement: a < 2^16 - 2^8 to simplify the code. + * 'length' checked later (when writing it to the first block) + * + * Also, loosen the requirements to enable support for CCM* (IEEE 802.15.4). + */ + if ((*InData_MACLength == 2) || (*InData_MACLength > 16) || (*InData_MACLength % 2 != 0)) + { + return FSP_ERR_CRYPTO_INVALID_SIZE; + } + + if (*InData_DataType == 0) + { + FSP_PARAMETER_NOT_USED(InData_Header); + + /* Apply key operations */ + uint8_t A_InData_IV[SIZE_AES_BLOCK_BYTES] = {0}; + memcpy(&A_InData_IV[SIZE_AES_BLOCK_BYTES - InData_IVLen], InData_IV, InData_IVLen); + HW_SCE_AesCcmDecryptKeyOperation((uint32_t *) InData_KeyIndex, + *InData_KeyType, + (uint32_t *) A_InData_IV, + SIZE_AES_128BIT_KEYLEN_BYTES); + + /* Formatting function and counter generation function */ + HW_SCE_AesCcmDecryptCounterGenerate((*InData_TextLen - *InData_MACLength), + Header_Len, + *InData_MACLength, + InData_IVLen); + } + else + { + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + + /* Apply formating function with associated data */ + HW_SCE_AesCcmDecryptInputAssociatedData((uint32_t *) InData_Header, Header_Len); + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes192CcmDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + uint32_t InData_IVLen = InData_Cmd[0]; + + /* + * Check length requirements: SP800-38C A.1 + * Additional requirement: a < 2^16 - 2^8 to simplify the code. + * 'length' checked later (when writing it to the first block) + * + * Also, loosen the requirements to enable support for CCM* (IEEE 802.15.4). + */ + if ((*InData_MACLength == 2) || (*InData_MACLength > 16) || (*InData_MACLength % 2 != 0)) + { + return FSP_ERR_CRYPTO_INVALID_SIZE; + } + + if (*InData_DataType == 0) + { + FSP_PARAMETER_NOT_USED(InData_Header); + + /* Apply key operations */ + uint8_t A_InData_IV[SIZE_AES_BLOCK_BYTES] = {0}; + memcpy(&A_InData_IV[SIZE_AES_BLOCK_BYTES - InData_IVLen], InData_IV, InData_IVLen); + HW_SCE_AesCcmDecryptKeyOperation((uint32_t *) InData_KeyIndex, + *InData_KeyType, + (uint32_t *) A_InData_IV, + SIZE_AES_128BIT_KEYLEN_BYTES); + + /* Formatting function and counter generation function */ + HW_SCE_AesCcmDecryptCounterGenerate((*InData_TextLen - *InData_MACLength), + Header_Len, + *InData_MACLength, + InData_IVLen); + } + else + { + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + + /* Apply formating function with associated data */ + HW_SCE_AesCcmDecryptInputAssociatedData((uint32_t *) InData_Header, Header_Len); + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes256CcmDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + uint32_t InData_IVLen = InData_Cmd[0]; + + /* + * Check length requirements: SP800-38C A.1 + * Additional requirement: a < 2^16 - 2^8 to simplify the code. + * 'length' checked later (when writing it to the first block) + * + * Also, loosen the requirements to enable support for CCM* (IEEE 802.15.4). + */ + if ((*InData_MACLength == 2) || (*InData_MACLength > 16) || (*InData_MACLength % 2 != 0)) + { + return FSP_ERR_CRYPTO_INVALID_SIZE; + } + + if (*InData_DataType == 0) + { + FSP_PARAMETER_NOT_USED(InData_Header); + + /* Apply key operations */ + uint8_t A_InData_IV[SIZE_AES_BLOCK_BYTES] = {0}; + memcpy(&A_InData_IV[SIZE_AES_BLOCK_BYTES - InData_IVLen], InData_IV, InData_IVLen); + HW_SCE_AesCcmDecryptKeyOperation((uint32_t *) InData_KeyIndex, + InData_KeyType[0], + (uint32_t *) A_InData_IV, + SIZE_AES_128BIT_KEYLEN_BYTES); + + /* Formatting function and counter generation function */ + HW_SCE_AesCcmDecryptCounterGenerate((*InData_TextLen - *InData_MACLength), + Header_Len, + *InData_MACLength, + InData_IVLen); + } + else + { + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + + /* Apply formating function with associated data */ + HW_SCE_AesCcmDecryptInputAssociatedData((uint32_t *) InData_Header, Header_Len); + } + + return FSP_SUCCESS; +} + +void HW_SCE_Aes128CcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + /* CTR decryption */ + hw_aes_ccm_decrypt_init(SCE_AES_IN_DATA_CMD_CCM_DEC_CTR_DECRYPT); + hw_aes_ccm_mode_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, MAX_CNT / 4); +} + +void HW_SCE_Aes192CcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + HW_SCE_Aes128CcmDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); +} + +void HW_SCE_Aes256CcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + HW_SCE_Aes128CcmDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); +} + +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]) +{ + fsp_err_t err = FSP_SUCCESS; + bool mac_unaligned = !HW_32BIT_ALIGNED((uint32_t) &InData_Text[0]); + bool dst_unaligned = !HW_32BIT_ALIGNED((uint32_t) &OutData_Text[0]); + uint32_t payload_len = *InData_TextLen - *InData_MACLength; + uint32_t block_num = HW_AES_DATA_FIT_TO_BLOCK_SIZE(payload_len) / + SIZE_AES_BLOCK_BYTES; + uint32_t payload_remain = HW_AES_DATA_GET_LAST_REMAINS(payload_len); + uint8_t Yr[SIZE_AES_BLOCK_BYTES] = {0}; + uint8_t Tag[SIZE_AES_BLOCK_BYTES] = {0}; + uint8_t LSB_C_Tlen[SIZE_AES_BLOCK_BYTES] = {0}; + + FSP_PARAMETER_NOT_USED(InData_Text); + + /* Formatting function for payload */ + /* SCE AES hardware configuration for formatting function for payload */ + hw_aes_ccm_decrypt_init(SCE_AES_IN_DATA_CMD_CCM_DEC_FORMAT_PAYLOAD); + if ((true == dst_unaligned) || (true == mac_unaligned)) + { + uint32_t data_tmp[SIZE_AES_BLOCK_BYTES / 4]; + uint8_t * p_buf_in = (uint8_t *) OutData_Text; + uint8_t * p_local_in = (uint8_t *) data_tmp; + uint32_t index; + + for (index = 0; index < block_num; index++) + { + memset(p_local_in, 0, SIZE_AES_BLOCK_BYTES); + memcpy(p_local_in, p_buf_in, SIZE_AES_BLOCK_BYTES); + hw_aes_ccm_mode_start(p_local_in, NULL, SIZE_AES_BLOCK_BYTES / SIZE_AES_BLOCK_BYTES); + p_buf_in += SIZE_AES_BLOCK_BYTES; + } + + if (payload_remain) + { + p_local_in = (uint8_t *) data_tmp; + memset(p_local_in, 0, SIZE_AES_BLOCK_BYTES); + memcpy(p_local_in, p_buf_in, payload_remain); + hw_aes_ccm_mode_start(p_local_in, NULL, SIZE_AES_BLOCK_BYTES / SIZE_AES_BLOCK_BYTES); + } + + hw_aes_ccm_mode_start(NULL, &Yr[0], SIZE_AES_BLOCK_BYTES / SIZE_AES_BLOCK_BYTES); + + if (true == mac_unaligned) + { + p_local_in = (uint8_t *) data_tmp; + memset(p_local_in, 0, SIZE_AES_BLOCK_BYTES); + memcpy(p_local_in, (uint8_t *) InData_MAC, *InData_MACLength); + memcpy(&LSB_C_Tlen[0], p_local_in, *InData_MACLength); + } + else + { + memcpy(&LSB_C_Tlen[0], InData_MAC, *InData_MACLength); + } + } + else + { + /* Out is uint32_t aligned */ + uint8_t * p_buf_in = (uint8_t *) OutData_Text; + if (block_num) + { + hw_aes_ccm_mode_start((uint8_t *) p_buf_in, (uint8_t *) NULL, block_num); + p_buf_in += block_num * SIZE_AES_BLOCK_BYTES; + } + + if (payload_remain) + { + uint32_t InOut_DataTmp[SIZE_AES_BLOCK_BYTES / sizeof(uint32_t)]; + memset(InOut_DataTmp, 0, SIZE_AES_BLOCK_BYTES); + memcpy(InOut_DataTmp, p_buf_in, payload_remain); + hw_aes_ccm_mode_start((uint8_t *) InOut_DataTmp, + (uint8_t *) NULL, + SIZE_AES_BLOCK_BYTES / SIZE_AES_BLOCK_BYTES); + } + + hw_aes_ccm_mode_start(NULL, &Yr[0], SIZE_AES_BLOCK_BYTES / SIZE_AES_BLOCK_BYTES); + + memcpy(&LSB_C_Tlen[0], InData_MAC, *InData_MACLength); + } + + /* SCE AES hardware configuration for TAG generation */ + hw_aes_ccm_decrypt_init(SCE_AES_IN_DATA_CMD_CCM_DEC_GENERATE_TAG); + hw_aes_ccm_mode_start((uint8_t *) &LSB_C_Tlen[0], (uint8_t *) &Tag[0], SIZE_AES_BLOCK_BYTES / SIZE_AES_BLOCK_BYTES); + + if (0 != memcmp(Tag, Yr, *InData_MACLength)) + { + err = FSP_ERR_CRYPTO_SCE_VERIFY_FAIL; + } + + return err; +} + +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]) +{ + fsp_err_t err = FSP_SUCCESS; + err = HW_SCE_Aes128CcmDecryptFinalSub(InData_Text, InData_TextLen, InData_MAC, InData_MACLength, OutData_Text); + + return err; +} + +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]) +{ + fsp_err_t err = FSP_SUCCESS; + err = HW_SCE_Aes128CcmDecryptFinalSub(InData_Text, InData_TextLen, InData_MAC, InData_MACLength, OutData_Text); + + return err; +} + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes128GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes128GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyMode); + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes192EncryptDecryptInitSub(InData_Cmd, InData_KeyIndex, InData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/r_sce_if.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/r_sce_if.h new file mode 100644 index 0000000000..fbed2cf763 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/adaptors/r_sce_if.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ + +#include "bsp_api.h" + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +#ifndef R_SCE_IF_HEADER_FILE + #define R_SCE_IF_HEADER_FILE + + #define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) + #define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) + +/* OEM Command */ +typedef enum e_sce_oem_cmd +{ + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES192, + SCE_OEM_CMD_AES256, + SCE_OEM_CMD_AES128_XTS, + SCE_OEM_CMD_AES256_XTS, + SCE_OEM_CMD_RSA1024_PUBLIC, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA224, + SCE_OEM_CMD_HMAC_SHA256, + SCE_OEM_CMD_ECC_P256R1_PUBLIC, + SCE_OEM_CMD_ECC_P256R1_PRIVATE, + SCE_OEM_CMD_ECC_P384R1_PUBLIC, + SCE_OEM_CMD_ECC_P384R1_PRIVATE, + SCE_OEM_CMD_ECC_P512R1_PUBLIC, + SCE_OEM_CMD_ECC_P512R1_PRIVATE, + SCE_OEM_CMD_ECC_SECP256K1_PUBLIC, + SCE_OEM_CMD_ECC_SECP256K1_PRIVATE, + SCE_OEM_CMD_NUM +} sce_oem_cmd_t; + +typedef enum e_sce_oem_key_type +{ + SCE_OEM_KEY_TYPE_ENCRYPTED = 0, + SCE_OEM_KEY_TYPE_PLAIN = 1 +} sce_oem_key_type_t; + +#endif /* R_SCE_IF_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_ccm_mode.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_ccm_mode.c new file mode 100644 index 0000000000..9faea371d3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_ccm_mode.c @@ -0,0 +1,538 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "hw_sce_aes_private.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ +#define HW_BYTE_TO_BIT_LENGTH(x) ((x) << 3) + +#define SCE_AES_PRV_CCM_TLEN_VALUE_OFFSET (16 / 8) +#define SCE_AES_PRV_CCM_TLEN_MIN_VALUE (32 / 8) + +#define SCE_AES_PRV_CCM_NLEN_VALUE_OFFSET (8 / 8) +#define SCE_AES_PRV_CCM_NLEN_MIN_VALUE (56 / 8) + +#define HW_SCE_AES_CCM_B0_TLEN_32BITS_CFG (0x00000000) +#define HW_SCE_AES_CCM_B0_TLEN_48BITS_CFG (0x00000001) +#define HW_SCE_AES_CCM_B0_TLEN_64BITS_CFG (0x00000002) +#define HW_SCE_AES_CCM_B0_TLEN_80BITS_CFG (0x00000003) +#define HW_SCE_AES_CCM_B0_TLEN_96BITS_CFG (0x00000004) +#define HW_SCE_AES_CCM_B0_TLEN_112BITS_CFG (0x00000005) +#define HW_SCE_AES_CCM_B0_TLEN_128BITS_CFG (0x00000006) + +#define HW_SCE_AES_CCM_B0_NLEN_56BITS_CFG (0x00000000) +#define HW_SCE_AES_CCM_B0_NLEN_64BITS_CFG (0x00000001) +#define HW_SCE_AES_CCM_B0_NLEN_72BITS_CFG (0x00000002) +#define HW_SCE_AES_CCM_B0_NLEN_80BITS_CFG (0x00000003) +#define HW_SCE_AES_CCM_B0_NLEN_88BITS_CFG (0x00000004) +#define HW_SCE_AES_CCM_B0_NLEN_96BITS_CFG (0x00000005) +#define HW_SCE_AES_CCM_B0_NLEN_104BITS_CFG (0x00000006) + +#define PARAM_B0_PLEN_3BITS_MSB_OFFSET (29) +#define PARAM_B0_ALEN_3BITS_MSB_OFFSET (13) +#define PARAM_B0_B127_B96_MASK (0x0007FFF8) +#define PARAM_B0_B95_B64_MASK (0x00770000) +#define PARAM_B0_B63_B32_MASK (0x00000007) +#define PARAM_B0_B31_B0_MASK (0xFFFFFFF8) +#define PARAM_B0_B95_B64_TLEN_OFFSET (16) +#define PARAM_B0_B95_B64_NLEN_OFFSET (20) + +#define HW_AES_BLOCK_LAST_WORD (3) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ +typedef struct B0_param +{ + uint32_t B31_B0; /*!< B0[31:30]: bitfield of Plen */ + uint32_t B63_B32; /*!< B0[63:32]: bitfield of Plen */ + uint32_t B95_B64; /*!< B0[66:64]: bitfield of Plen, B0[79:67]: reserved, B0[82:80]: bitfield of Tlen, + * B0[83:83]: reserved, B0[86:84]: bitfield of Nlen, B0[95:87]: reserved */ + uint32_t B127_B96; /*!< B0[114:96]: bitfield of Alen, B0[127:115]: reserved */ +} st_AES_Ccm_B0_param_t; + +/*********************************************************************************************************************** + * Imported global variables and functions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private variables and functions + ***********************************************************************************************************************/ +static uint32_t const g_aes_ccm_tlen_cfg_lut[] = +{ + HW_SCE_AES_CCM_B0_TLEN_32BITS_CFG, HW_SCE_AES_CCM_B0_TLEN_48BITS_CFG, HW_SCE_AES_CCM_B0_TLEN_64BITS_CFG, + HW_SCE_AES_CCM_B0_TLEN_80BITS_CFG, HW_SCE_AES_CCM_B0_TLEN_96BITS_CFG, HW_SCE_AES_CCM_B0_TLEN_112BITS_CFG, + HW_SCE_AES_CCM_B0_TLEN_128BITS_CFG +}; + +static uint32_t const g_aes_ccm_nlen_cfg_lut[] = +{ + HW_SCE_AES_CCM_B0_NLEN_56BITS_CFG, HW_SCE_AES_CCM_B0_NLEN_64BITS_CFG, HW_SCE_AES_CCM_B0_NLEN_72BITS_CFG, + HW_SCE_AES_CCM_B0_NLEN_80BITS_CFG, HW_SCE_AES_CCM_B0_NLEN_88BITS_CFG, HW_SCE_AES_CCM_B0_NLEN_96BITS_CFG, + HW_SCE_AES_CCM_B0_NLEN_104BITS_CFG +}; + +static void hw_aes_ccm_calculate_b0(st_AES_Ccm_B0_param_t * Out_ParamB0, + uint32_t plen, + uint32_t alen, + uint32_t tlen, + uint32_t nlen); +static void hw_aes_ccm_encrypt_init(uint32_t indata_cmd); + +static void aes_block_swap_endian(uint32_t * InOut_Block, uint32_t MaxBlock); + +/*********************************************************************************************************************** + * Global variables and functions + ***********************************************************************************************************************/ +void hw_aes_ccm_decrypt_init(uint32_t indata_cmd); +void HW_SCE_AesCcmEncryptKeyOperation(uint32_t * InData_KeyIndex, + uint32_t InData_KeyType, + uint32_t * InData_IV, + uint32_t InData_IVLength); +void HW_SCE_AesCcmDecryptKeyOperation(uint32_t * InData_KeyIndex, + uint32_t InData_KeyType, + uint32_t * InData_IV, + uint32_t InData_IVLength); +void HW_SCE_AesCcmEncryptCounterGenerate(uint32_t InData_TextLength, + uint32_t InData_Hdrlen, + uint32_t InData_MacLength, + uint32_t InData_IVLength); +void HW_SCE_AesCcmDecryptCounterGenerate(uint32_t InData_TextLength, + uint32_t InData_Hdrlen, + uint32_t InData_MacLength, + uint32_t InData_IVLength); +void HW_SCE_AesCcmEncryptInputAssociatedData(uint32_t * InData_Header, uint32_t InData_Hdrlen); +void HW_SCE_AesCcmDecryptInputAssociatedData(uint32_t * InData_Header, uint32_t InData_Hdrlen); +void HW_SCE_AesCcmEncryptPlaintextInputInit(); +void HW_SCE_AesCcmEncryptGenerateTag(uint32_t * OutData_MAC); + +/*********************************************************************************************************************** + * @brief Swap byte-order of an AES block + * + * @param[in,out] InOut_Block pointer to blocks need to convert endianess + * @param[in] MaxBlock number of block need to convert + ***********************************************************************************************************************/ +static void aes_block_swap_endian (uint32_t * InOut_Block, uint32_t MaxBlock) +{ + uint32_t aes_block_tmp[SIZE_AES_BLOCK_BYTES / 4]; + uint32_t * InBlock = InOut_Block; + uint32_t block_cnt; + + for (block_cnt = 0; block_cnt < MaxBlock; block_cnt++) + { + uint32_t index; + for (index = 0; index <= HW_AES_BLOCK_LAST_WORD; index++) + { + aes_block_tmp[HW_AES_BLOCK_LAST_WORD - index] = __REV(*(InBlock + index)); + } + + memcpy(InBlock, aes_block_tmp, SIZE_AES_BLOCK_BYTES); + InBlock += 4; + } +} + +/*********************************************************************************************************************** + * @brief Implement common operation, input key and IV for encryption + * + * @param[in] InData_KeyIndex pointer to key to be input + * @param[in] InData_KeyType to determine which key type is input + * @param[in] InData_IV pointer to IV to be input + * @param[in] InData_IVLength to determine IV length in byte to be input + ***********************************************************************************************************************/ +void HW_SCE_AesCcmEncryptKeyOperation (uint32_t * InData_KeyIndex, + uint32_t InData_KeyType, + uint32_t * InData_IV, + uint32_t InData_IVLength) +{ + uint8_t InData_IV_tmp[SIZE_AES_BLOCK_BYTES] = {0}; + + /* SCE AES hardware configuration for key operation */ + if (SIZE_AES_128BIT_KEYLEN_BYTES == InData_KeyType) + { + hw_aes_ccm_encrypt_init(SCE_AES_IN_DATA_CMD_CCM_128_ENC_COMMON_INIT); + } + else if (SIZE_AES_192BIT_KEYLEN_BYTES == InData_KeyType) + { + hw_aes_ccm_encrypt_init(SCE_AES_IN_DATA_CMD_CCM_192_ENC_COMMON_INIT); + } + else + { + /* Input key is 256bits length */ + hw_aes_ccm_encrypt_init(SCE_AES_IN_DATA_CMD_CCM_256_ENC_COMMON_INIT); + } + + /* Key input */ + hw_aes_set_key((uint8_t *) InData_KeyIndex, InData_KeyType); + + /* IV input */ + memcpy(&InData_IV_tmp[SIZE_AES_BLOCK_BYTES - InData_IVLength], InData_IV, InData_IVLength); + hw_aes_set_iv(InData_IV_tmp); +} + +/*********************************************************************************************************************** + * @brief Implement common operation, input key and IV for decryption + * + * @param[in] InData_KeyIndex pointer to key to be input + * @param[in] InData_KeyType to determine which key type is input + * @param[in] InData_IV pointer to IV to be input + * @param[in] InData_IVLength to determine IV length in byte to be input + ***********************************************************************************************************************/ +void HW_SCE_AesCcmDecryptKeyOperation (uint32_t * InData_KeyIndex, + uint32_t InData_KeyType, + uint32_t * InData_IV, + uint32_t InData_IVLength) +{ + uint8_t InData_IV_tmp[SIZE_AES_BLOCK_BYTES] = {0}; + + /* SCE AES hardware configuration for key operation */ + if (SIZE_AES_128BIT_KEYLEN_BYTES == InData_KeyType) + { + hw_aes_ccm_decrypt_init(SCE_AES_IN_DATA_CMD_CCM_128_DEC_COMMON_INIT); + } + else if (SIZE_AES_192BIT_KEYLEN_BYTES == InData_KeyType) + { + hw_aes_ccm_decrypt_init(SCE_AES_IN_DATA_CMD_CCM_192_DEC_COMMON_INIT); + } + else + { + /* Input key is 256bits length */ + hw_aes_ccm_decrypt_init(SCE_AES_IN_DATA_CMD_CCM_256_DEC_COMMON_INIT); + } + + /* Key input */ + hw_aes_set_key((uint8_t *) InData_KeyIndex, InData_KeyType); + + /* IV input */ + memcpy(&InData_IV_tmp[SIZE_AES_BLOCK_BYTES - InData_IVLength], InData_IV, InData_IVLength); + hw_aes_set_iv(InData_IV_tmp); +} + +/*********************************************************************************************************************** + * @brief Implement common operation to generate counter and input parameter B0 + * + * @param[in] InData_TextLength length in byte of payload data to be input + * @param[in] InData_Hdrlen length in byte of associated data to be input + * @param[in] InData_MacLength length in byte of tag need to be generated + * @param[in] InData_IVLength length in byte of IV to be input + ***********************************************************************************************************************/ +void HW_SCE_AesCcmEncryptCounterGenerate (uint32_t InData_TextLength, + uint32_t InData_Hdrlen, + uint32_t InData_MacLength, + uint32_t InData_IVLength) +{ + st_AES_Ccm_B0_param_t param_B0; + + /* SCE AES hardware configuration for parameter B0 input */ + hw_aes_ccm_encrypt_init(SCE_AES_IN_DATA_CMD_CCM_ENC_COUNTER_GENERATE); + + /* Apply formatting function for parameter B0 */ + hw_aes_ccm_calculate_b0(¶m_B0, InData_TextLength, InData_Hdrlen, InData_MacLength, InData_IVLength); + + /* Swap endian to have parameter B0 with big endian */ + aes_block_swap_endian((uint32_t *) ¶m_B0, sizeof(st_AES_Ccm_B0_param_t) / SIZE_AES_BLOCK_BYTES); + + /* Input parameter B0 and apply counter generation function */ + hw_aes_ccm_mode_start((uint8_t *) ¶m_B0, NULL, sizeof(st_AES_Ccm_B0_param_t) / SIZE_AES_BLOCK_BYTES); +} + +/*********************************************************************************************************************** + * @brief Implement common operation to generate counter and input parameter B0 + * + * @param[in] InData_TextLength length in byte of payload data to be input + * @param[in] InData_Hdrlen length in byte of associated data to be input + * @param[in] InData_MacLength length in byte of tag need to be generated + * @param[in] InData_IVLength length in byte of IV to be input + ***********************************************************************************************************************/ +void HW_SCE_AesCcmDecryptCounterGenerate (uint32_t InData_TextLength, + uint32_t InData_Hdrlen, + uint32_t InData_MacLength, + uint32_t InData_IVLength) +{ + st_AES_Ccm_B0_param_t param_B0; + + /* SCE AES hardware configuration for parameter B0 input */ + hw_aes_ccm_decrypt_init(SCE_AES_IN_DATA_CMD_CCM_DEC_COUNTER_GENERATE); + + /* Apply formatting function for parameter B0 */ + hw_aes_ccm_calculate_b0(¶m_B0, InData_TextLength, InData_Hdrlen, InData_MacLength, InData_IVLength); + + /* Swap endian to have parameter B0 with big endian */ + aes_block_swap_endian((uint32_t *) ¶m_B0, sizeof(st_AES_Ccm_B0_param_t) / SIZE_AES_BLOCK_BYTES); + + /* Input parameter B0 and apply counter generation function */ + hw_aes_ccm_mode_start((uint8_t *) ¶m_B0, NULL, sizeof(st_AES_Ccm_B0_param_t) / SIZE_AES_BLOCK_BYTES); +} + +/*********************************************************************************************************************** + * @brief Implement common operation and input associated data + * + * @param[in] InData_Header pointer to associated data string need to be input + * @param[in] InData_Hdrlen length in byte of associated data string + ***********************************************************************************************************************/ +void HW_SCE_AesCcmEncryptInputAssociatedData (uint32_t * InData_Header, uint32_t InData_Hdrlen) +{ + /* SCE AES hardware configuration for associated data input */ + hw_aes_ccm_encrypt_init(SCE_AES_IN_DATA_CMD_CCM_ENC_FORMAT_A_DATA); + + /* Input associated data */ + uint8_t * p_a_data = (uint8_t *) InData_Header; + uint32_t block_cnt = HW_AES_DATA_FIT_TO_BLOCK_SIZE(InData_Hdrlen); + if (0 < block_cnt) + { + hw_aes_ccm_mode_start((uint8_t *) InData_Header, NULL, block_cnt / SIZE_AES_BLOCK_BYTES); + p_a_data += block_cnt; + } + + uint32_t remain_data = HW_AES_DATA_GET_LAST_REMAINS(InData_Hdrlen); + if (0 < remain_data) + { + uint32_t a_data_tmp[SIZE_AES_BLOCK_BYTES / sizeof(uint32_t)] = {0}; + memcpy(a_data_tmp, p_a_data, remain_data); + hw_aes_ccm_mode_start((uint8_t *) a_data_tmp, NULL, SIZE_AES_BLOCK_BYTES / SIZE_AES_BLOCK_BYTES); + } +} + +/*********************************************************************************************************************** + * @brief Implement common operation and input associated data + * + * @param[in] InData_Header pointer to associated data string need to be input + * @param[in] InData_Hdrlen length in byte of associated data string + ***********************************************************************************************************************/ +void HW_SCE_AesCcmDecryptInputAssociatedData (uint32_t * InData_Header, uint32_t InData_Hdrlen) +{ + /* SCE AES hardware configuration for associated data input */ + hw_aes_ccm_decrypt_init(SCE_AES_IN_DATA_CMD_CCM_DEC_FORMAT_A_DATA); + + /* Input associated data */ + uint8_t * p_a_data = (uint8_t *) InData_Header; + uint32_t block_cnt = HW_AES_DATA_FIT_TO_BLOCK_SIZE(InData_Hdrlen); + if (0 < block_cnt) + { + hw_aes_ccm_mode_start((uint8_t *) InData_Header, NULL, block_cnt / SIZE_AES_BLOCK_BYTES); + p_a_data += block_cnt; + } + + uint32_t remain_data = HW_AES_DATA_GET_LAST_REMAINS(InData_Hdrlen); + if (0 < remain_data) + { + uint32_t a_data_tmp[SIZE_AES_BLOCK_BYTES / sizeof(uint32_t)] = {0}; + memcpy(a_data_tmp, p_a_data, remain_data); + hw_aes_ccm_mode_start((uint8_t *) a_data_tmp, NULL, SIZE_AES_BLOCK_BYTES / SIZE_AES_BLOCK_BYTES); + } +} + +/*********************************************************************************************************************** + * @brief Implement common operation before in put plaintext to be encrypted + * + ***********************************************************************************************************************/ +void HW_SCE_AesCcmEncryptPlaintextInputInit () +{ + /* Hardware config to input plaintext */ + hw_aes_ccm_encrypt_init(SCE_AES_IN_DATA_CMD_CCM_ENC_CTR_ENCRYPT); +} + +/*********************************************************************************************************************** + * @brief Implement common operations and generate Tag + * + * @param[out] OutData_MAC pointer to memory to output Tag + ***********************************************************************************************************************/ +void HW_SCE_AesCcmEncryptGenerateTag (uint32_t * OutData_MAC) +{ + uint32_t dummy_data[SIZE_AES_BLOCK_BYTES / sizeof(uint32_t)] = {0}; + + /* Generate Tag */ + hw_aes_ccm_encrypt_init(SCE_AES_IN_DATA_CMD_CCM_ENC_GENERATE_TAG); + hw_aes_ccm_mode_start((uint8_t *) dummy_data, (uint8_t *) OutData_MAC, sizeof(dummy_data) / SIZE_AES_BLOCK_BYTES); +} + +/*********************************************************************************************************************** + * @brief Assign value for parameter B0 to setting HW SCE AES CCM mode, output parameter B0 as little endian order + * + * @param[in,out] Out_ParamB0 pointer to parameter B0 block + * @param[in] plen payload length in byte + * @param[in] alen associated length in byte + * @param[in] tlen tag length in byte + * @param[in] nlen nonce length in byte + ***********************************************************************************************************************/ +static void hw_aes_ccm_calculate_b0 (st_AES_Ccm_B0_param_t * Out_ParamB0, + uint32_t plen, + uint32_t alen, + uint32_t tlen, + uint32_t nlen) +{ + uint32_t index; + memset(Out_ParamB0, 0, sizeof(st_AES_Ccm_B0_param_t)); + + /* Assign Plaintext length Bit */ + Out_ParamB0->B31_B0 = HW_BYTE_TO_BIT_LENGTH(plen) & PARAM_B0_B31_B0_MASK; + Out_ParamB0->B63_B32 = (plen >> PARAM_B0_PLEN_3BITS_MSB_OFFSET) & PARAM_B0_B63_B32_MASK; + + /* Assign Tag length Bit */ + uint32_t b95_b64 = 0; + index = (tlen - SCE_AES_PRV_CCM_TLEN_MIN_VALUE) / SCE_AES_PRV_CCM_TLEN_VALUE_OFFSET; + b95_b64 = g_aes_ccm_tlen_cfg_lut[index] << PARAM_B0_B95_B64_TLEN_OFFSET; + + /* Assign Nonce length Bit */ + index = (nlen - SCE_AES_PRV_CCM_NLEN_MIN_VALUE) / SCE_AES_PRV_CCM_NLEN_VALUE_OFFSET; + b95_b64 |= g_aes_ccm_nlen_cfg_lut[index] << PARAM_B0_B95_B64_NLEN_OFFSET; + Out_ParamB0->B95_B64 = b95_b64 & PARAM_B0_B95_B64_MASK; + + /* Assign Non-Encryption word length Bit */ + Out_ParamB0->B127_B96 = HW_BYTE_TO_BIT_LENGTH(alen) & PARAM_B0_B127_B96_MASK; +} + +/*********************************************************************************************************************** + * @brief Configure AES module to run CCM mode encryption operation + * + * @param[in] indata_cmd to be determined which operation need to be initial + **********************************************************************************************************************/ +static void hw_aes_ccm_encrypt_init (uint32_t indata_cmd) +{ + switch (indata_cmd) + { + case SCE_AES_IN_DATA_CMD_CCM_128_ENC_COMMON_INIT: + { + R_AES_B->AESCNTH = R_AES_AESCNTH_INIT; + R_AES_B->AESCNTL = R_AES_AESCNTL_CCM_128_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_192_ENC_COMMON_INIT: + { + R_AES_B->AESCNTH = R_AES_AESCNTH_INIT; + R_AES_B->AESCNTL = R_AES_AESCNTL_CCM_192_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_256_ENC_COMMON_INIT: + { + R_AES_B->AESCNTH = R_AES_AESCNTH_INIT; + R_AES_B->AESCNTL = R_AES_AESCNTL_CCM_256_ENC; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_ENC_COUNTER_GENERATE: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_NOT_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_1 | + R_AES_AESDCNTL_FIST_SET | + R_AES_AESDCNTL_NEW_KEY_SET; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_ENC_FORMAT_A_DATA: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_NOT_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_3; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_ENC_CTR_ENCRYPT: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_NOT_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_4; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_ENC_GENERATE_TAG: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_5; + break; + } + + default: + { + break; + } + } +} + +/*********************************************************************************************************************** + * @brief Configure AES module to run CCM mode decryption operation + * + * @param[in] indata_cmd to be determined which operation need to be initial + **********************************************************************************************************************/ +void hw_aes_ccm_decrypt_init (uint32_t indata_cmd) +{ + switch (indata_cmd) + { + case SCE_AES_IN_DATA_CMD_CCM_128_DEC_COMMON_INIT: + { + R_AES_B->AESCNTH = R_AES_AESCNTH_INIT; + R_AES_B->AESCNTL = R_AES_AESCNTL_CCM_128_DEC; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_192_DEC_COMMON_INIT: + { + R_AES_B->AESCNTH = R_AES_AESCNTH_INIT; + R_AES_B->AESCNTL = R_AES_AESCNTL_CCM_192_DEC; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_256_DEC_COMMON_INIT: + { + R_AES_B->AESCNTH = R_AES_AESCNTH_INIT; + R_AES_B->AESCNTL = R_AES_AESCNTL_CCM_256_DEC; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_DEC_COUNTER_GENERATE: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_NOT_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_1 | + R_AES_AESDCNTL_FIST_SET | + R_AES_AESDCNTL_NEW_KEY_SET; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_DEC_CTR_DECRYPT: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_NOT_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_2; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_DEC_FORMAT_A_DATA: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_NOT_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_3; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_DEC_FORMAT_PAYLOAD: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_NOT_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_4; + break; + } + + case SCE_AES_IN_DATA_CMD_CCM_DEC_GENERATE_TAG: + { + R_AES_B->AESDCNTH = R_AES_AESDCNTH_EXECUTE_TAG_CALCULATION; + R_AES_B->AESDCNTL = R_AES_AESDCNTL_ATTR_CCM_MODE_6; + break; + } + + default: + { + break; + } + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_ctr_mode.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_ctr_mode.c new file mode 100644 index 0000000000..4b09a49252 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_ctr_mode.c @@ -0,0 +1,197 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ + +#include "bsp_api.h" +#include "hw_sce_aes_private.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** + * Global variables and functions + ***********************************************************************************************************************/ + +fsp_err_t HW_SCE_AES_128CtrEncrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + fsp_err_t iret = FSP_SUCCESS; + FSP_PARAMETER_NOT_USED(OutData_IV); +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Key == (const uint32_t *) 0) || + ((InData_IV == (const uint32_t *) 0) || (InData_Text == (const uint32_t *) 0)) || + (OutData_Text == (const uint32_t *) 0) || (num_words == 0)) + { + iret = FSP_ERR_INVALID_ARGUMENT; + } +#endif + + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_128_ENC; + hw_aes_set_key((uint8_t *) InData_Key, SIZE_AES_128BIT_KEYLEN_BYTES); + + if (FSP_SUCCESS == iret) + { + hw_aes_set_iv((uint8_t *) InData_IV); + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, num_words); + } + + return iret; +} + +fsp_err_t HW_SCE_AES_192CtrEncrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + fsp_err_t iret = FSP_SUCCESS; + FSP_PARAMETER_NOT_USED(OutData_IV); +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Key == (const uint32_t *) 0) || + ((InData_IV == (const uint32_t *) 0) || (InData_Text == (const uint32_t *) 0)) || + (OutData_Text == (const uint32_t *) 0) || (num_words == 0)) + { + iret = FSP_ERR_INVALID_ARGUMENT; + } +#endif + + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_192_ENC; + hw_aes_set_key((uint8_t *) InData_Key, SIZE_AES_192BIT_KEYLEN_BYTES); + + if (FSP_SUCCESS == iret) + { + hw_aes_set_iv((uint8_t *) InData_IV); + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, num_words); + } + + return iret; +} + +fsp_err_t HW_SCE_AES_256CtrEncrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + fsp_err_t iret = FSP_SUCCESS; + FSP_PARAMETER_NOT_USED(OutData_IV); +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Key == (const uint32_t *) 0) || + ((InData_IV == (const uint32_t *) 0) || (InData_Text == (const uint32_t *) 0)) || + (OutData_Text == (const uint32_t *) 0) || (num_words == 0)) + { + iret = FSP_ERR_INVALID_ARGUMENT; + } +#endif + + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_256_ENC; + hw_aes_set_key((uint8_t *) InData_Key, SIZE_AES_256BIT_KEYLEN_BYTES); + + if (FSP_SUCCESS == iret) + { + hw_aes_set_iv((uint8_t *) InData_IV); + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, num_words); + } + + return iret; +} + +fsp_err_t HW_SCE_AES_128CtrDecrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + fsp_err_t iret = FSP_SUCCESS; +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Key == (const uint32_t *) 0) || + ((InData_IV == (const uint32_t *) 0) || (InData_Text == (const uint32_t *) 0)) || + (OutData_Text == (const uint32_t *) 0)) + { + iret = FSP_ERR_INVALID_ARGUMENT; + } +#endif + + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_128_DEC; + hw_aes_set_key((uint8_t *) InData_Key, SIZE_AES_128BIT_KEYLEN_BYTES); + + if (FSP_SUCCESS == iret) + { + hw_aes_set_iv((uint8_t *) InData_IV); + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, num_words); + } + + return iret; +} + +fsp_err_t HW_SCE_AES_192CtrDecrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + fsp_err_t iret = FSP_SUCCESS; +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Key == (const uint32_t *) 0) || + ((InData_IV == (const uint32_t *) 0) || (InData_Text == (const uint32_t *) 0)) || + (OutData_Text == (const uint32_t *) 0)) + { + iret = FSP_ERR_INVALID_ARGUMENT; + } +#endif + + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_192_DEC; + hw_aes_set_key((uint8_t *) InData_Key, SIZE_AES_192BIT_KEYLEN_BYTES); + + if (FSP_SUCCESS == iret) + { + hw_aes_set_iv((uint8_t *) InData_IV); + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, num_words); + } + + return iret; +} + +fsp_err_t HW_SCE_AES_256CtrDecrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + fsp_err_t iret = FSP_SUCCESS; +#if RM_TINYCRYPT_PORT_CFG_PARAM_CHECKING_ENABLE + if ((InData_Key == (const uint32_t *) 0) || + ((InData_IV == (const uint32_t *) 0) || (InData_Text == (const uint32_t *) 0)) || + (OutData_Text == (const uint32_t *) 0)) + { + iret = FSP_ERR_INVALID_ARGUMENT; + } +#endif + + R_AES_B->AESCNTL = R_AES_AESCNTL_CTR_256_DEC; + hw_aes_set_key((uint8_t *) InData_Key, SIZE_AES_256BIT_KEYLEN_BYTES); + + if (FSP_SUCCESS == iret) + { + hw_aes_set_iv((uint8_t *) InData_IV); + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2_3_MODE_2; + hw_aes_start((uint8_t *) InData_Text, (uint8_t *) OutData_Text, num_words); + } + + return iret; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_gcm_mode.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_gcm_mode.c new file mode 100644 index 0000000000..61773e4d3c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/aes2/aes2_gcm_mode.c @@ -0,0 +1,230 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ + +#include "bsp_api.h" +#include "hw_sce_aes_private.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** + * Global variables and functions + ***********************************************************************************************************************/ +static void gcm_inc32 (unsigned char * counter_block) +{ + unsigned char result; + + /* Add one for last byte. */ + result = (unsigned char) (counter_block[15] + 1); + counter_block[15] = (unsigned char) (result & 0xFF); + + /* Handle carry. */ + result = (unsigned char) ((result >> 8) + counter_block[14]); + counter_block[14] = (unsigned char) (result & 0xFF); + result = (unsigned char) ((result >> 8) + counter_block[13]); + counter_block[13] = (unsigned char) (result & 0xFF); + result = (unsigned char) ((result >> 8) + counter_block[12]); + counter_block[12] = (unsigned char) (result & 0xFF); +} + +fsp_err_t hw_gcm_calculation (uint8_t * input, + uint8_t * output, + uint32_t data_len, + uint8_t * atag, + uint8_t * initial_vector, + uint32_t iv_len, + uint8_t * aad, + uint32_t aad_len) +{ + uint32_t remaining_len = 0; + uint32_t block_len = 0; + uint32_t temp_value = 0; + uint32_t temp_len = 0; + uint8_t first_block_null_aad = 0; + uint8_t Jn[SIZE_AES_BLOCK_BYTES] = {0}; + uint8_t J0[SIZE_AES_BLOCK_BYTES] = {0}; + uint8_t temp_block[SIZE_AES_BLOCK_BYTES] = {0}; + uint32_t local_in[SIZE_AES_BLOCK_BYTES / 4] = {0}; + uint32_t local_out[SIZE_AES_BLOCK_BYTES / 4] = {0}; + uint8_t * current_in_ptr; + uint8_t * current_out_ptr; + fsp_err_t status = FSP_SUCCESS; + + bool src_unaligned = !HW_32BIT_ALIGNED((uint32_t) input); + bool dst_unaligned = !HW_32BIT_ALIGNED((uint32_t) output); + + current_in_ptr = input; + current_out_ptr = output; + + /* J0 Calculation from IV */ + if (iv_len == 12) + { + memcpy(J0, initial_vector, 12); + J0[15] = 1; + } + else + { + uint8_t * iv_ptr = initial_vector; + remaining_len = iv_len; + + R_AES_B->AESDCNTL |= R_AES_AESDCNTL_BIT_2 | R_AES_AESDCNTL_BIT_3; + + while (remaining_len > 0) + { + block_len = (remaining_len < 16) ? remaining_len : 16; + + if (block_len < 16) + { + memset(temp_block, 0, sizeof(temp_block)); + memcpy(temp_block, iv_ptr, block_len); + hw_aes_start(temp_block, J0, 1); + } + else + { + hw_aes_start(iv_ptr, J0, 1); + } + + iv_ptr += block_len; + remaining_len -= block_len; + } + + uint64_t iv_bit_len = (uint64_t) iv_len * 8; + uint8_t iv_data[16] = {0}; + for (int i = 0; i < 8; i++) + { + iv_data[15 - i] = (uint8_t) (iv_bit_len >> (8 * i)); + } + + hw_aes_start(iv_data, J0, 1); + } + + /* Flow to Obtain J1 from J0 */ + memcpy(Jn, J0, 16); + gcm_inc32(Jn); + hw_aes_set_iv(Jn); + + /* Acquire hash value of AAD */ + if (aad_len > 0) + { + uint8_t * aad_ptr = aad; + remaining_len = aad_len; + + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_3 | R_AES_AESDCNTL_BIT_2; + + while (remaining_len > 0) + { + block_len = (remaining_len < SIZE_AES_BLOCK_BYTES) ? remaining_len : SIZE_AES_BLOCK_BYTES; + + if (block_len < SIZE_AES_BLOCK_BYTES) + { + memset(temp_block, 0, sizeof(temp_block)); + memcpy(temp_block, aad_ptr, block_len); + hw_aes_start(temp_block, temp_block, 1); + } + else + { + hw_aes_start(aad_ptr, temp_block, 1); + } + + aad_ptr += block_len; + remaining_len -= block_len; + } + } + else + { + first_block_null_aad = 1; + } + + /* Encryption Flow Start */ + if (data_len > 0) + { + remaining_len = data_len; + + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_5; + if (first_block_null_aad == 1) + { + first_block_null_aad = 0; + R_AES_B->AESDCNTL |= R_AES_AESDCNTL_BIT_3 | R_AES_AESDCNTL_BIT_2; + } + + do + { + block_len = (remaining_len < SIZE_AES_BLOCK_BYTES) ? remaining_len : SIZE_AES_BLOCK_BYTES; + if ((src_unaligned || dst_unaligned) && (block_len == SIZE_AES_BLOCK_BYTES)) + { + if (src_unaligned) + { + memset(local_in, 0, SIZE_AES_BLOCK_BYTES); + memcpy(local_in, current_in_ptr, block_len); + hw_aes_start((uint8_t *) local_in, (uint8_t *) local_out, 1); + } + else + { + hw_aes_start(current_in_ptr, (uint8_t *) local_out, 1); + } + + memcpy(current_out_ptr, local_out, block_len); + } + else if (block_len == SIZE_AES_BLOCK_BYTES) + { + hw_aes_start(current_in_ptr, current_out_ptr, 1); + } + else + { + temp_value = block_len * 8; + temp_value <<= 8; + temp_value |= R_AES_AESDCNTL_BIT_4; + R_AES_B->AESDCNTL |= (uint16_t) temp_value; + + memset(temp_block, 0, sizeof(temp_block)); + memcpy(temp_block, current_in_ptr, block_len); + hw_aes_start(temp_block, (uint8_t *) local_out, 1); + memcpy(current_out_ptr, local_out, block_len); + } + + current_in_ptr += block_len; + current_out_ptr += block_len; + remaining_len -= block_len; + + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_5; + } while (remaining_len > 0); + } + + /* Encryption Flow End */ + + /* Authentication Tag Creation Start */ + hw_aes_set_iv(J0); + for (int16_t iLoop = 0; iLoop < 8; iLoop++) + { + temp_len = aad_len * 8; + temp_len >>= (8 * iLoop); + Jn[7 - iLoop] = (uint8_t) temp_len; + temp_len = data_len * 8; + temp_len >>= (8 * iLoop); + Jn[15 - iLoop] = (uint8_t) temp_len; + } + + if (((uint8_t) iv_len == 12) && (aad_len == 0) && (data_len == 0)) + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2 | R_AES_AESDCNTL_BIT_3 | R_AES_AESDCNTL_BIT_6; + } + else if (((uint8_t) iv_len != 12) && (aad_len == 0) && (data_len == 0)) + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_2 | R_AES_AESDCNTL_BIT_6; + } + else + { + R_AES_B->AESDCNTL = R_AES_AESDCNTL_BIT_6; + } + + memset(atag, 0, 16); + hw_aes_start(Jn, atag, 1); + + /* Authentication Tag Creation End */ + return status; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/common/hw_sce_common.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/common/hw_sce_common.h new file mode 100644 index 0000000000..35a801729b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/common/hw_sce_common.h @@ -0,0 +1,81 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup SCE + * @{ + ***********************************************************************************************************************/ + +#ifndef HW_SCE_COMMON_H +#define HW_SCE_COMMON_H + +/********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sce_if.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ +#define R_SCE_BITS_TO_BYTES(x) (((x) + 7U) >> 3U) +#define R_SCE_BYTES_TO_BITS(x) ((x) << 3U) +#define R_SCE_WORDS_TO_BYTES(x) ((x) << 2U) +#define R_SCE_BYTES_TO_WORDS(x) (((x) + 3U) >> 2U) + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + ***********************************************************************************************************************/ +uint32_t change_endian_long(uint32_t data); + +/*******************************************************************************************************************//** + * + **********************************************************************************************************************/ +__STATIC_INLINE void HW_SCE_PowerOn (void) +{ +#if BSP_FEATURE_TRNG_HAS_MODULE_STOP + + // RA2 MCU series has separate power control for RNG + R_MSTP->MSTPCRC_b.MSTPC28 = 0; +#endif + + // power on the SCE module + R_MSTP->MSTPCRC_b.MSTPC31 = 0; +} + +__STATIC_INLINE void HW_SCE_PowerOff (void) +{ +#if BSP_FEATURE_TRNG_HAS_MODULE_STOP + + // Disable hardware TRNG before module stop. + // Note: Must perform this step BEFORE TRNG module stop, or the TRNG hardware will draw excessive current in power off. + R_TRNG->TRNGSCR0_b.SGCEN = 0; + + // RA2 MCU series has separate power control for RNG + R_MSTP->MSTPCRC_b.MSTPC28 = 1; +#endif + + // power off the SCE module + R_MSTP->MSTPCRC_b.MSTPC31 = 1; +} + +#endif /* HW_SCE_COMMON_H */ + +/*******************************************************************************************************************//** + * @} + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c new file mode 100644 index 0000000000..cc17fbf9dd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/adaptors/r_sce_adapt.c @@ -0,0 +1,665 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "SCE_ProcCommon.h" +#include "hw_sce_ra_private.h" +#include "hw_sce_private.h" +#include "hw_sce_trng_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +uint32_t INST_DATA_SIZE; + +/******************************************************* + * The following are valid SCE lifecycle states: + * + * CM1(Lifecycle state) + * + * CM2(Lifecycle state) + * + * SSD(Lifecycle state) + * + * NSECSD(Lifecycle state) + * + * DPL(Lifecycle state) + * + * LCK_DBG(Lifecycle state) + * + * LCK_BOOT(Lifecycle state) + * + * RMA_REQ(Lifecycle state) + * + * RMA_ACK(Lifecycle state) + ****************************************************/ + +#define FSP_SCE_DLMMON_MASK 0x0000000F /* for lcs in stored in R_PSCU->DLMMON */ + +const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM] = +{ + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD, +}; + +/* Dummy domain parameter structure create for all RSIP devices to allow using the same API for all engines. */ + +uint32_t const DomainParam_NIST_P256 = {0}; +uint32_t const DomainParam_NIST_P384 = {0}; +uint32_t const DomainParam_Brainpool_256r1 = {0}; +uint32_t const DomainParam_Brainpool_384r1 = {0}; +uint32_t const DomainParam_Koblitz_secp256k1 = {0}; + +/* Find the lifecycle state load the hardware unique key */ +/* returns fsp_err_t */ + +/* SCE5 specific initialization functions */ +/* returns fsp_err_t */ + +fsp_err_t HW_SCE_McuSpecificInit (void) +{ + fsp_err_t iret = FSP_ERR_CRYPTO_SCE_FAIL; + + // power on the SCE module + HW_SCE_PowerOn(); + + HW_SCE_SoftwareResetSub(); + iret = HW_SCE_SelfCheck1Sub(); + + if (FSP_SUCCESS == iret) + { + /* Change SCE to little endian mode */ + SCE->REG_1D4H = 0x0000ffff; + + if (FSP_SUCCESS == iret) + { + /* This check is moved from before the endian setting for the updated fastboot procedures */ + iret = HW_SCE_SelfCheck2Sub(); + } + } + + return iret; +} + +fsp_err_t HW_SCE_RNG_Read (uint32_t * OutData_Text) +{ + if (FSP_SUCCESS != HW_SCE_GenerateRandomNumberSub(OutData_Text)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type, + const sce_oem_cmd_t cmd, + const uint8_t * encrypted_provisioning_key, + const uint8_t * iv, + const uint8_t * encrypted_oem_key, + uint32_t * key_index) +{ + uint32_t indata_key_type[1] = {0}; + uint32_t install_key_ring_index[1] = {0}; + indata_key_type[0] = key_type; + install_key_ring_index[0] = 0U; + + INST_DATA_SIZE = sce_oem_key_size[cmd] - 4U; + + fsp_err_t ret = FSP_SUCCESS; + + if (key_type == SCE_OEM_KEY_TYPE_PLAIN) + { + if (cmd == SCE_OEM_CMD_AES128) + { + ret = HW_SCE_GenerateAes128PlainKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + } + else if (cmd == SCE_OEM_CMD_AES256) + { + ret = HW_SCE_GenerateAes256PlainKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + } + else if (cmd == SCE_OEM_CMD_AES128_XTS) + { + ret = HW_SCE_GenerateAes128XtsKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + } + else + { + ret = FSP_ERR_ASSERTION; + } + } + + return ret; + +} + +uint32_t change_endian_long (uint32_t a) +{ + return __REV(a); +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyMode); + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes192EncryptDecryptInitSub(InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub (void) +{ + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes192GcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, + const uint32_t *InData_DataALen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(InData_DataALen); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(OutData_DataT); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes192GcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_DataALen, + const uint32_t *InData_DataT, const uint32_t *InData_DataTLen, uint32_t *OutData_Text) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(InData_DataT); + FSP_PARAMETER_NOT_USED(InData_DataALen); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_DataTLen); + FSP_PARAMETER_NOT_USED(OutData_Text); + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub(void) +{ + +} + +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub(void) +{ + +} + +void HW_SCE_Aes192GcmEncryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_DataA); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +void HW_SCE_Aes192GcmDecryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_DataA); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_GhashSub (uint32_t *InData_HV, + uint32_t *InData_IV, + uint32_t *InData_Text, + uint32_t *OutData_DataT, + uint32_t MAX_CNT) +{ + return HW_SCE_Ghash(InData_HV, InData_IV, InData_Text, OutData_DataT, MAX_CNT); +} + +fsp_err_t HW_SCE_Aes128CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + return HW_SCE_Aes128CmacInitSub((uint32_t *)InData_KeyIndex); +} + +fsp_err_t HW_SCE_Aes192CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes256CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + return HW_SCE_Aes256CmacInitSub((uint32_t *)InData_KeyIndex); +} + +void HW_SCE_Aes128CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + HW_SCE_Aes128CmacUpdateSub((uint32_t *)InData_Text, (uint32_t)MAX_CNT); +} + +void HW_SCE_Aes192CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +void HW_SCE_Aes256CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + HW_SCE_Aes256CmacUpdateSub((uint32_t *)InData_Text, (uint32_t)MAX_CNT); +} + +fsp_err_t HW_SCE_Aes128CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + return HW_SCE_Aes128CmacFinalSub((uint32_t *)InData_Cmd, (uint32_t *)InData_Text, (uint32_t *)InData_DataT, + (uint32_t *)InData_DataTLen, OutData_DataT); +} + +fsp_err_t HW_SCE_Aes192CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(InData_DataT); + FSP_PARAMETER_NOT_USED(InData_DataTLen); + FSP_PARAMETER_NOT_USED(OutData_DataT); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes256CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + return HW_SCE_Aes256CmacFinalSub((uint32_t *)InData_Cmd, (uint32_t *)InData_Text, (uint32_t *)InData_DataT, + (uint32_t *)InData_DataTLen, OutData_DataT); +} + +void HW_SCE_Aes192CcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +void HW_SCE_Aes192CcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_MAC); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_MAC, const uint32_t *InData_MACLength, uint32_t *OutData_Text) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MAC); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(OutData_Text); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return (HW_SCE_Aes128CcmEncryptInitSub(InData_KeyIndex, InData_IV, InData_Header, Header_Len)); +} + +fsp_err_t HW_SCE_Aes192CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + FSP_PARAMETER_NOT_USED(InData_Header); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + FSP_PARAMETER_NOT_USED(Header_Len); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes256CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return (HW_SCE_Aes256CcmEncryptInitSub(InData_KeyIndex, InData_IV, InData_Header, Header_Len)); +} + +fsp_err_t HW_SCE_Aes128CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_MACLength[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return (HW_SCE_Aes128CcmDecryptInitSub(InData_KeyIndex, InData_IV, InData_Header, Header_Len)); +} + +fsp_err_t HW_SCE_Aes192CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_MACLength[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + FSP_PARAMETER_NOT_USED(InData_Header); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + FSP_PARAMETER_NOT_USED(Header_Len); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes256CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], + uint32_t InData_DataType[], + uint32_t InData_Cmd[], + uint32_t InData_TextLen[], + uint32_t InData_MACLength[], + uint32_t InData_KeyIndex[], + uint32_t InData_IV[], + uint32_t InData_Header[], + uint32_t InData_SeqNum[], + uint32_t Header_Len) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_TextLen); + FSP_PARAMETER_NOT_USED(InData_MACLength); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + return (HW_SCE_Aes256CcmDecryptInitSub(InData_KeyIndex, InData_IV, InData_Header, Header_Len)); +} + +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSubGeneral (const uint32_t *InData_Text, const uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + return (HW_SCE_Aes128CcmEncryptFinalSub(InData_TextLen, InData_Text, OutData_Text, OutData_MAC)); +} + +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSubGeneral(const uint32_t *InData_Text, + const uint32_t *InData_TextLen, + const uint32_t *InData_MAC, + const uint32_t *InData_MACLength, + uint32_t *OutData_Text) +{ + return (HW_SCE_Aes128CcmDecryptFinalSub(InData_Text, InData_TextLen, InData_MAC, InData_MACLength, OutData_Text)); +} + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return (HW_SCE_Aes128GcmEncryptInitSub (InData_KeyType, InData_KeyIndex, InData_IV)); +} + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return (HW_SCE_Aes128GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV)); +} + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmEncryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_KeyType); + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes192GcmDecryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmEncryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t * InData_KeyType, + uint32_t * InData_DataType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_SeqNum) +{ + FSP_PARAMETER_NOT_USED(InData_DataType); + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_SeqNum); + + return HW_SCE_Aes256GcmDecryptInitSub(InData_KeyType, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes128XtsEncryptInitSubGeneral (uint32_t InData_KeyMode[], + uint32_t InData_KeyIndex[], + uint32_t InData_Key[], + uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyMode); + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes128XtsEncryptInitSub(InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes128XtsDecryptInitSubGeneral (uint32_t InData_KeyMode[], + uint32_t InData_KeyIndex[], + uint32_t InData_Key[], + uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyMode); + FSP_PARAMETER_NOT_USED(InData_Key); + return HW_SCE_Aes128XtsDecryptInitSub(InData_KeyIndex, InData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func001.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func001.c new file mode 100644 index 0000000000..1deacd1e5d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func001.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_func001(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x400f388dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); + /* WAIT_LOOP */ + while (0U != SCE->REG_A8H_b.B16) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_func001.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func002.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func002.c new file mode 100644 index 0000000000..03a9545db0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func002.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_func002(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x400e388dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); + /* WAIT_LOOP */ + while (0U != SCE->REG_A8H_b.B17) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_func002.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func003.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func003.c new file mode 100644 index 0000000000..3eac31cdd6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func003.c @@ -0,0 +1,79 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_func003(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x400d388dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_func003.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func205.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func205.c new file mode 100644 index 0000000000..c8fd40076d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func205.c @@ -0,0 +1,81 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_func205(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_A8H_b.B6) + { + /* waiting */ + } + SCE->REG_1CH = 0x002c0000U; + SCE->REG_1CH = 0x002d0000U; + SCE->REG_B0H = 0x00000001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_func205.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func206.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func206.c new file mode 100644 index 0000000000..08ff309f27 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func206.c @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_func206(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_04H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + SCE->REG_1CH = 0x002c0000U; + SCE->REG_1CH = 0x002d0000U; + SCE->REG_B0H = 0x00000001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_func206.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func207.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func207.c new file mode 100644 index 0000000000..4bf602ef68 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_func207.c @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_func207(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_04H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_A8H_b.B6) + { + /* waiting */ + } + SCE->REG_1CH = 0x002c0000U; + SCE->REG_1CH = 0x002d0000U; + SCE->REG_B0H = 0x00000001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_func207.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p00.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p00.c new file mode 100644 index 0000000000..e119d68e18 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p00.c @@ -0,0 +1,72 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_SoftwareResetSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p00.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p01.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p01.c new file mode 100644 index 0000000000..f4d1a8ad1b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p01.c @@ -0,0 +1,124 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_SelfCheck1Sub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_SelfCheck1SubSub(); + + SCE->REG_138H = 0xf597806AU; + SCE->REG_F0H = 0x00000000U; + SCE->REG_04H = 0x00000001U; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_80H = 0x00000001U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_84H = 0x00010101U; + SCE->REG_13CH = 0x00000F00U; + SCE->REG_88H = 0x00008003U; + SCE->REG_104H = 0x00000351U; + HW_SCE_func002(change_endian_long(0x4c1d2affU), change_endian_long(0x60ebc80aU), change_endian_long(0xdf041ee8U), change_endian_long(0x394548fdU)); + SCE->REG_88H = 0x00000000U; + SCE->REG_104H = 0x00000351U; + SCE->REG_A4H = 0x400f380dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0xe6be653cU; + SCE->REG_100H = 0xcfa7022cU; + SCE->REG_100H = 0xb7f12cbfU; + SCE->REG_100H = 0x7eb98ec1U; + HW_SCE_func002(change_endian_long(0x851be22bU), change_endian_long(0xa6e93a47U), change_endian_long(0x5714620aU), change_endian_long(0x5f2d7b1fU)); + HW_SCE_func001(change_endian_long(0xc0a8e4c8U), change_endian_long(0xb08ee757U), change_endian_long(0x6bd1dd36U), change_endian_long(0x11fc0e56U)); + SCE->REG_04H = 0x00001001U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_18H_b.B13)) + { + SCE->REG_1BCH = 0x00000020U; + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_13CH = 0x00000201U; + HW_SCE_func003(change_endian_long(0x7153c22dU), change_endian_long(0xb402a12dU), change_endian_long(0x355fb000U), change_endian_long(0x55e578a7U)); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p01.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p02.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p02.c new file mode 100644 index 0000000000..8bcfb07c2e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p02.c @@ -0,0 +1,429 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_SelfCheck2Sub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000201U; + SCE->REG_108H = 0x00000000U; + SCE->REG_ECH = 0x3000a800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func001(0x0ffbd2c9U, 0xaa8ff051U, 0x6a474c72U, 0x43516ad7U); + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0000005CU; + HW_SCE_func002(0x3c4a5c81U, 0x208257cdU, 0x5b474dd8U, 0x01b5a09dU); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0000005eU; + HW_SCE_func002(0x41db671fU, 0x82356453U, 0xb3918a3bU, 0x3859a49cU); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0000005dU; + HW_SCE_func002(0x33c7fc89U, 0xb0cd3eb8U, 0xa2a73968U, 0xd8ba9e19U); + } + SCE->REG_A4H = 0x00040804U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_SelfCheck2SubSub(); + + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008107U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000010fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002c00U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func001(0xb9375233U, 0x86b67a72U, 0x6f0ee8f9U, 0x71ff9697U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x48ed8c84U, 0xb2d01eceU, 0xa0661789U, 0xdbb74e30U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_RETRY; + } + else + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0000001cU; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00200684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0xc0200c9dU; + SCE->REG_00H = 0x00001413U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000000U; + SCE->REG_E0H = 0x80040080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x8627d9acU, 0x6d2369bfU, 0x733c08b5U, 0x97487af9U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x000b0804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000351U; + SCE->REG_A4H = 0x00010805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000001U); + HW_SCE_func001(0x5a86b499U, 0x9e5788daU, 0x09eddf92U, 0xba75eec3U); + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x0020b6bfU; + SCE->REG_E0H = 0x81080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00010805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xa0a89032U, 0x36a7c63dU, 0x750cd4f0U, 0x8740312fU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x3788782dU, 0x0b828de3U, 0xbd8bcd51U, 0xbd9bc999U); + SCE->REG_A4H = 0x000d0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xbebbf494U, 0x95c03fa1U, 0x5ae6458cU, 0xc0016389U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xa6b90b54U, 0x61ab03a7U, 0x2ce6e649U, 0x19ed264bU); + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[4+0 + 0] = SCE->REG_100H; + S_RAM[4+0 + 1] = SCE->REG_100H; + S_RAM[4+0 + 2] = SCE->REG_100H; + S_RAM[4+0 + 3] = SCE->REG_100H; + SCE->REG_13CH = 0x00000202U; + HW_SCE_func003(0xe729aae7U, 0x00446087U, 0x8445ae02U, 0x63abd977U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p02.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p06.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p06.c new file mode 100644 index 0000000000..fb73cebb66 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p06.c @@ -0,0 +1,284 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000601U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xd5d93ab8U, 0x5a88a67eU, 0x514d1e4bU, 0xcde045a3U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x8ad6ce23U, 0x3b09b780U, 0x36b9f537U, 0x816cdb27U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + HW_SCE_func001(0xcdb2986eU, 0x03cf3311U, 0x1ab8e0e1U, 0x00890f96U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x8ff2f5ceU, 0xc3bc59e4U, 0x80415a70U, 0x55935064U); + SCE->REG_A4H = 0x42e406bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000351U; + SCE->REG_A4H = 0x400009cdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_04H = 0x00000122U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func003(0x7213a768U, 0x20388bc9U, 0xcd2486d5U, 0x98481c7aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p06.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p07.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p07.c new file mode 100644 index 0000000000..8f16f6dfb7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p07.c @@ -0,0 +1,366 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000701U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xcc6fe9d0U, 0x5cbf301fU, 0x8cbd1fbeU, 0x1128a4a2U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xea71be3dU, 0x1a5f410fU, 0x3f6fd9b4U, 0x5357f8b2U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + HW_SCE_func001(0xe0b6371fU, 0xe967c338U, 0x425ef5d1U, 0x400d6d0fU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x2e427851U, 0xb3f38c24U, 0x7498bf66U, 0x01efe670U); + SCE->REG_E0H = 0x80080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xb263f6d6U, 0x59548f1cU, 0xca73685cU, 0x63ae6af6U); + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x42e486bfU; + SCE->REG_E0H = 0x81080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000351U; + SCE->REG_A4H = 0x400009cdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000002U); + SCE->REG_04H = 0x00000132U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + HW_SCE_func003(0x77642a42U, 0xb279f8dcU, 0xfbe63265U, 0xe162833fU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p07.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p09.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p09.c new file mode 100644 index 0000000000..8c862bccdf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p09.c @@ -0,0 +1,148 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000901U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x3f063139U, 0xcb903ce7U, 0x4c5616a7U, 0x4970827aU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x19e279b0U, 0x849def2cU, 0xc9afeb32U, 0xc5e5e8c0U); + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_func003(0x3471330bU, 0x4e06dd6cU, 0x6e2f6a05U, 0x1300bca9U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p09.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p16.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p16.c new file mode 100644 index 0000000000..0c716d5eef --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p16.c @@ -0,0 +1,366 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00001601U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xb29e5969U, 0x5e4703caU, 0x38fdb8abU, 0x00771ea8U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x3afab9bfU, 0xa6aee36aU, 0x4d04eaf6U, 0x0d38f2f7U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x2d8daf39U); + HW_SCE_func001(0xfc1fc44aU, 0x4a43489fU, 0x458962c4U, 0x4173cbebU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x864fd5aeU, 0x1d202218U, 0x82b56d96U, 0x6d09dc7dU); + SCE->REG_E0H = 0x80080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x82750538U, 0x1c0ec684U, 0x1912ae7dU, 0xd870558cU); + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x42e486bfU; + SCE->REG_E0H = 0x81080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000351U; + SCE->REG_A4H = 0x400009cdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000002U); + SCE->REG_04H = 0x00000132U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + HW_SCE_func003(0x775fa887U, 0xdf6828d9U, 0xcf49352aU, 0xaed42e2bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p16.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p17.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p17.c new file mode 100644 index 0000000000..c24cb0ed06 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p17.c @@ -0,0 +1,521 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00001701U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x069c2e54U, 0x6c7be636U, 0xea7c104dU, 0x7f271a3dU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x9d17e379U, 0x19ae942dU, 0xe43e2d82U, 0x056f7c89U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5737b943U); + HW_SCE_func001(0x790f4d3dU, 0x51b61d27U, 0xc27aa958U, 0x6085a7deU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x6388f234U, 0xf210cb6bU, 0x92d58b26U, 0x602f9c57U); + SCE->REG_E0H = 0x80080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xbf80940cU, 0x5ef1969fU, 0x36f3cc6eU, 0x2e50a692U); + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x42e486bfU; + SCE->REG_E0H = 0x81080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000122U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0x189d504aU, 0x4e514a8fU, 0x38d652e2U, 0xab6638ceU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xdd0ef7b5U, 0x1363967dU, 0x535a94e7U, 0x652489e7U); + SCE->REG_E0H = 0x80080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x45765ba0U, 0xc0e4fef7U, 0x04ecae5aU, 0x30d8776bU); + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x40e486bfU; + SCE->REG_E0H = 0x81080000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000351U; + SCE->REG_A4H = 0x400009cdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000004U); + SCE->REG_04H = 0x00000132U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[16] = SCE->REG_100H; + OutData_KeyIndex[17] = SCE->REG_100H; + OutData_KeyIndex[18] = SCE->REG_100H; + OutData_KeyIndex[19] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[20] = SCE->REG_100H; + OutData_KeyIndex[21] = SCE->REG_100H; + OutData_KeyIndex[22] = SCE->REG_100H; + OutData_KeyIndex[23] = SCE->REG_100H; + HW_SCE_func003(0x2903686bU, 0xf771fbe0U, 0x4121546dU, 0xe67f54ceU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p17.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p22.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p22.c new file mode 100644 index 0000000000..9e8056399f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p22.c @@ -0,0 +1,139 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Ghash(uint32_t *InData_HV, uint32_t *InData_IV, uint32_t *InData_Text, uint32_t *OutData_DataT, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002201U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xe564a7b7U, 0x74d6026dU, 0x90ed01e5U, 0x9fa5252cU); + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_74H = 0x00000006U; + SCE->REG_104H = 0x00000364U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_HV[0]; + SCE->REG_100H = InData_HV[1]; + SCE->REG_100H = InData_HV[2]; + SCE->REG_100H = InData_HV[3]; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000364U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_74H = 0x00000002U; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_104H = 0x00000000U; + SCE->REG_74H = 0x00000008U; + SCE->REG_04H = 0x00000512U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_func003(0x93f9900eU, 0x65abac8bU, 0xe4310bd5U, 0xebadbea5U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p22.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p23.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p23.c new file mode 100644 index 0000000000..5d7bfb66ec --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p23.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_StartUpdateFirmwareSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002301U; + SCE->REG_108H = 0x00000000U; + SCE->REG_13CH = 0x00000204U; + HW_SCE_func003(0x9488f22aU, 0x7d807559U, 0x756f22afU, 0x7248a5dbU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p23.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p30.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p30.c new file mode 100644 index 0000000000..0306d2d245 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p30.c @@ -0,0 +1,201 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)InData_KeyType; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00003001U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xdb4cd513U, 0x18163648U, 0x97321fa5U, 0x8479718aU); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xc9fc6f2eU, 0xe5d31ae0U, 0x4e75da96U, 0x67e66934U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x123d9c8aU, 0xea52e660U, 0x7f3daf54U, 0xd5aa43afU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040080U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0000088cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00000006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p30.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p31.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p31.c new file mode 100644 index 0000000000..d63f3fdc43 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p31.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmEncryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000U; + HW_SCE_func002(0xeb8bbf1aU, 0x47f29db9U, 0x61d7f637U, 0x5b8a3030U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p31.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p32.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p32.c new file mode 100644 index 0000000000..1a94d42b94 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p32.c @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_AesGcmEncryptDecryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x0000863cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p32.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p33.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p33.c new file mode 100644 index 0000000000..5fb3f0dd44 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p33.c @@ -0,0 +1,104 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop+4) + { + HW_SCE_func001(0x4238b344U, 0xa022f79eU, 0x8a9cbeaaU, 0xe6c7048fU); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x000086bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_A4H = 0x00000885U; + SCE->REG_00H = 0x00004113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + HW_SCE_func002(0xf5cafe54U, 0xbba27bb1U, 0x635b428dU, 0x96453d1cU); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p33.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p34.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p34.c new file mode 100644 index 0000000000..50db5ed333 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p34.c @@ -0,0 +1,272 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_DataALen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80820001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000168U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003822U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003802U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007FU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xFFFFFF00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x04a02841U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x1dd8c755U, 0xed55b6b7U, 0x900b5ee5U, 0x1001c3d4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x875f4780U, 0x8e6d834eU, 0xa9f0c940U, 0x9381fd93U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00036800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x08008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x68dd183cU, 0x436261a3U, 0xb957edc3U, 0x0d88b76dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0xf5f71d06U, 0x2290dc7cU, 0xda61f11bU, 0x74795eefU); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x000086bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_A4H = 0x00000885U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00004813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_func002(0x4cf4f5f4U, 0x0ca3f52bU, 0x69a71dc9U, 0x3bc5d3f8U); + } + HW_SCE_func001(0x28215800U, 0xc743b779U, 0xdaeed44fU, 0x3f05cc51U); + SCE->REG_104H = 0x00000164U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81820001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x000086bdU; + SCE->REG_00H = 0x00001513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_func003(0x12eb1e99U, 0x7e8f8f75U, 0x3a56763dU, 0x77775791U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p34.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p35.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p35.c new file mode 100644 index 0000000000..0a4d6dfc9e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p35.c @@ -0,0 +1,201 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)InData_KeyType; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00003501U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x21ed2347U, 0x5f306177U, 0x23b607f3U, 0xadd94d14U); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x14e8157aU, 0x6a6f6e95U, 0xcdc23daaU, 0x26738eefU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x9d701c42U, 0xc58cd7bfU, 0xa91be178U, 0x2624317bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040080U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0000088cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00000006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p35.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p36.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p36.c new file mode 100644 index 0000000000..864c620026 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p36.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmDecryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000U; + HW_SCE_func002(0x9434f133U, 0x4562c474U, 0x19dac137U, 0xaf2affd6U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p36.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p38.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p38.c new file mode 100644 index 0000000000..c8546bad32 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p38.c @@ -0,0 +1,125 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x923875e0U, 0x064ae6c5U, 0xd38bb2aaU, 0x1b48391fU); + SCE->REG_104H = 0x000000b5U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x000086beU; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + HW_SCE_func206(); + HW_SCE_func002(0x584f91e0U, 0x3ad5fe5bU, 0xd65a75e1U, 0x186c1e4bU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p38.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p39.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p39.c new file mode 100644 index 0000000000..04ca0b7c56 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p39.c @@ -0,0 +1,392 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_DataALen, const uint32_t *InData_DataT, const uint32_t *InData_DataTLen, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0xd2eba9a0U, 0xc14878bbU, 0xc25ddf0eU, 0x86b64fc3U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x9302436bU, 0x16aec248U, 0x66917839U, 0x0ef0d3afU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xdd8ab537U, 0x5545a52aU, 0x9a328b9aU, 0xf0978213U); + } + else + { + HW_SCE_func002(0xa1199f7dU, 0x3605f5adU, 0x2c1fb9f5U, 0xf075e83cU); + } + HW_SCE_func003(0xdba9bb48U, 0xb432714eU, 0xfbce8074U, 0xbe6b7b82U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80820001U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003822U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003802U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007FU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xFFFFFF00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x04a02841U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010040U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008840U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x34202862U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x038417e2U, 0x66b7ed48U, 0x38664936U, 0x6aecc3f2U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x31a07bc9U, 0x3024964bU, 0x32d163feU, 0xd1fd5849U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00036800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x08008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0xc36200a4U, 0x97e9e41dU, 0xbe43e605U, 0xb3650b73U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0x5aecc5f9U, 0x5bab7431U, 0x695d6952U, 0x58041c09U); + SCE->REG_B0H = 0x00000020U; + SCE->REG_104H = 0x00000365U; + SCE->REG_A4H = 0x000086bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + HW_SCE_func002(0xab6b5e9eU, 0x97cf5b8dU, 0x500efb27U, 0xb2ad0173U); + } + SCE->REG_104H = 0x00000164U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81820001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x000086bdU; + SCE->REG_00H = 0x00001513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002862U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00050805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func001(0xce6b097aU, 0x3c72c9bdU, 0xd4d05384U, 0x05ceadc6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xaf4d5361U, 0x768ce068U, 0x3f4c8250U, 0x6f09dc33U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_func003(0x06df48c9U, 0xb4dc54d1U, 0xa376d6f5U, 0xf1d175faU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p39.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p40.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p40.c new file mode 100644 index 0000000000..662576a2f3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p40.c @@ -0,0 +1,213 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)InData_KeyType; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004001U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xa0dfeb6eU, 0x577509d6U, 0xbeead778U, 0x9391ce67U); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0x8375898fU, 0xd30beab9U, 0xb26ab2d5U, 0x14f4f73fU); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xd648b357U, 0x17fcdf6dU, 0x83da5146U, 0xfb130cedU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x126afcb6U, 0x4a624192U, 0xe7620cd6U, 0x6dde57ddU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040080U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0000888cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00000006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p40.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p41.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p41.c new file mode 100644 index 0000000000..2cec1f9b32 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p41.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmEncryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000U; + HW_SCE_func002(0x943780b6U, 0x63b17cc1U, 0x8dab1c0eU, 0xa1fd4f5fU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p41.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p42.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p42.c new file mode 100644 index 0000000000..765263673c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p42.c @@ -0,0 +1,104 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop+4) + { + HW_SCE_func001(0xafe5afbcU, 0x95dba3d7U, 0xafa4264cU, 0x3d54623eU); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x000086bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_A4H = 0x00000885U; + SCE->REG_00H = 0x00004113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + HW_SCE_func002(0xe5410fceU, 0x683dbb17U, 0xf6708251U, 0x80e3a0dcU); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p42.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p43.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p43.c new file mode 100644 index 0000000000..eb539ef44a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p43.c @@ -0,0 +1,272 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_DataALen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80820001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000168U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003822U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003802U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007FU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xFFFFFF00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x04a02841U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x70e7edbfU, 0x76f89372U, 0x485f97b6U, 0xe3f65e86U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x23d1cd62U, 0xc0b557c4U, 0x86acecf5U, 0xb2d6e7a2U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00036800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x08008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0xce97ea4bU, 0xa361d014U, 0x9e14d1deU, 0x0a491960U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0xa25ad62dU, 0x383cac2eU, 0x6a526762U, 0xec07b999U); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x000086bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_A4H = 0x00000885U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00004813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_func002(0x70493f9cU, 0x2d1d1672U, 0xd6b74524U, 0x66bf8946U); + } + HW_SCE_func001(0xfe8e38beU, 0xd68e600eU, 0xa07dd953U, 0xd046acb5U); + SCE->REG_104H = 0x00000164U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81820001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x000086bdU; + SCE->REG_00H = 0x00001513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_func003(0xdaaf1756U, 0x3dcce280U, 0xcdc6d6b7U, 0x9dfee37bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p43.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p44.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p44.c new file mode 100644 index 0000000000..de65602690 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p44.c @@ -0,0 +1,213 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)InData_KeyType; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004401U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x4e453abbU, 0x2616f4b7U, 0x1bc44347U, 0x99e60a67U); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0x28b887e3U, 0xb4b9febdU, 0xf78d391eU, 0x80a75c5dU); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xdee755d1U, 0xac8531c0U, 0x75e8967cU, 0xcacdd399U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xd6ddc783U, 0xe2527ac7U, 0xedb26f90U, 0x5ba0b255U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040080U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0000888cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00000006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p44.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p45.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p45.c new file mode 100644 index 0000000000..d709f8efe3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p45.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmDecryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000U; + HW_SCE_func002(0x36e2d0c8U, 0x6f4180a6U, 0xcf29d863U, 0xe342dcf3U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p45.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p46.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p46.c new file mode 100644 index 0000000000..d92438b760 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p46.c @@ -0,0 +1,125 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x41ac49a8U, 0x867b1918U, 0x06f85819U, 0xfd099f46U); + SCE->REG_104H = 0x000000b5U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x000086beU; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + HW_SCE_func206(); + HW_SCE_func002(0x91bb8586U, 0x3ad3c555U, 0x7baf6ed8U, 0xe022da48U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p46.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p47.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p47.c new file mode 100644 index 0000000000..2f4fd3ddef --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p47.c @@ -0,0 +1,392 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_DataALen, const uint32_t *InData_DataT, const uint32_t *InData_DataTLen, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x0541cb7cU, 0x602ed641U, 0x9623725aU, 0x69334525U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x46fb9bb4U, 0xf24287b1U, 0x611bf16fU, 0xe4cad300U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x15ca5f3dU, 0x8c6e9a06U, 0x2ce282c2U, 0x527884efU); + } + else + { + HW_SCE_func002(0xd6ffdfd0U, 0x9a68e15bU, 0x4bc38c0fU, 0xf2d17922U); + } + HW_SCE_func003(0xc963406eU, 0x0a254c37U, 0x9cab8cdcU, 0x647f95d6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80820001U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003822U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003802U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007FU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xFFFFFF00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x04a02841U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010040U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008840U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x34202862U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0xd56502c5U, 0x8dedc70aU, 0x43737485U, 0x620b3250U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x7b44fedaU, 0x18946a25U, 0xee56a374U, 0x226fe029U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00036800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x08008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x24a2919dU, 0x56bba70bU, 0x405ae47fU, 0x754cb155U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0xc5bbd165U, 0x4f251a62U, 0x98088995U, 0x756e5341U); + SCE->REG_B0H = 0x40000020U; + SCE->REG_104H = 0x00000365U; + SCE->REG_A4H = 0x000086bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + HW_SCE_func002(0xf0b780b1U, 0xfbcebcf6U, 0xb9bb1883U, 0x22748e54U); + } + SCE->REG_104H = 0x00000164U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81820001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x000086bdU; + SCE->REG_00H = 0x00001513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002862U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00050805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func001(0xbd7d54bcU, 0x1fe8fc2aU, 0x3fd628bdU, 0xc24ed7f7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x53d5e107U, 0xe5c7ca0aU, 0xeb52af17U, 0xb3df007eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_func003(0xa37a7191U, 0x3959cfc9U, 0x8cf58b51U, 0x7f541d46U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p47.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p50.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p50.c new file mode 100644 index 0000000000..3ad9812c6c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p50.c @@ -0,0 +1,147 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005001U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xce90f1c6U, 0x6a2d1927U, 0xc0382844U, 0x83121125U); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x533a0cc7U, 0xa15b079cU, 0x7bbb01c5U, 0x3163ac11U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x652ad3a6U, 0x72c4804cU, 0x556a150bU, 0x43b411a6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p50.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p51.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p51.c new file mode 100644 index 0000000000..222faefbdb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p51.c @@ -0,0 +1,85 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00000c1eU; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + } + HW_SCE_func205(); + HW_SCE_func002(0x3aa3e203U, 0xd1be079bU, 0xdfd4ae5eU, 0x240f5606U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p51.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p52.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p52.c new file mode 100644 index 0000000000..f8d9408bb3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p52.c @@ -0,0 +1,349 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x85f1f743U, 0x9d0167c7U, 0xf01a6eb3U, 0xa34dd05aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x416db2deU, 0x8d5e184cU, 0xbee699caU, 0x2a7ddeadU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xfaa6589dU, 0xd8ccc330U, 0x25cd199fU, 0x326492e1U); + } + else + { + HW_SCE_func002(0x898f1535U, 0x537f84c2U, 0xd85382b9U, 0x411ae863U); + } + HW_SCE_func003(0x2b77689dU, 0x996540ebU, 0x0bc29f41U, 0xfa8e373dU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0000088cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + SCE->REG_A4H = 0x00400885U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xd3436cecU, 0x641fac01U, 0x2465213fU, 0x47686bd4U); + } + else + { + SCE->REG_A4H = 0x00500885U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x87b567d9U, 0x7812f09bU, 0xf1a07779U, 0x05440fe3U); + } + SCE->REG_A4H = 0x00040605U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + HW_SCE_func001(0x5f2d6047U, 0x4a2eb549U, 0xf274c14eU, 0x60ec98caU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00000c9dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_func003(0xdc02c966U, 0x9c8070e5U, 0x63d21f46U, 0x18f82684U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010040U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x3420a840U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x34202862U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x46290762U, 0xfdd11c85U, 0x1ac1e40bU, 0x860fe3acU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x66b8ede0U, 0x0ec5e9dcU, 0x9836cab3U, 0xc9d891e3U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00000c9dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e2U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000568e7U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00026ce7U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003827U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003402U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000028c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008cc0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00004406U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007421U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c27U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000034c2U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000568c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000034e6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00026ce7U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 4; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3420a8e0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000dU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x10003c27U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000a4e0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00900c05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + HW_SCE_func001(0x4ac5bc17U, 0xe24b751cU, 0x2b5ed4fbU, 0xa226455aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x8f229174U, 0x15a111cbU, 0xdbf9222fU, 0xf3c1e792U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_func003(0x485ab686U, 0x0e200f29U, 0x22c4e46cU, 0xdf45c32bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p52.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p53.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p53.c new file mode 100644 index 0000000000..db15926f36 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p53.c @@ -0,0 +1,158 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CmacInitSub(uint32_t *InData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005301U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x656b4828U, 0x229a9ed9U, 0x3a883acbU, 0x56056e53U); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0xfbb2edb2U, 0x04cb120eU, 0x7bc34e61U, 0x3bc22103U); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x2eef8c66U, 0x416ebb64U, 0x9177b3dfU, 0xcd7f39dfU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x3350ce25U, 0x4ba5497fU, 0x2e5a024dU, 0x3b06da4fU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p53.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p54.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p54.c new file mode 100644 index 0000000000..1585283e2a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p54.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008c1eU; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + } + HW_SCE_func205(); + HW_SCE_func002(0xb3ad8b17U, 0xbd01ccf3U, 0x70daf165U, 0x24af51cdU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p54.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p55.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p55.c new file mode 100644 index 0000000000..7c62b6c523 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p55.c @@ -0,0 +1,354 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0xa6f98bbaU, 0xa970edabU, 0x1f533fbdU, 0xb8a09834U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x01b67f98U, 0xa3fb7fe3U, 0xf628f47bU, 0xd2657899U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xcdcad000U, 0xabc39a21U, 0xd55a0d65U, 0x32ddcdccU); + } + else + { + HW_SCE_func002(0x16f971e4U, 0xb309e92dU, 0x2ebd6e4bU, 0xbd8d8005U); + } + HW_SCE_func003(0x57fae2dfU, 0x68afc29dU, 0xb2b54c36U, 0x466b977bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0000888cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00408885U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x4ca5a4cfU, 0x0212ce29U, 0xdbe9a869U, 0xa9674776U); + } + else + { + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00508885U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xa491fea2U, 0x83857da3U, 0x6754c2b5U, 0xdfc9f322U); + } + SCE->REG_A4H = 0x00040605U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + HW_SCE_func001(0x3159f8d9U, 0x47045150U, 0xb59ffaa8U, 0xcc13badeU); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00048c9dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_func003(0xf17e6870U, 0x1275c6edU, 0xd6710bbaU, 0xec0d58abU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010040U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x3420a840U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x34202862U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x2855c8a0U, 0xd0dd89ebU, 0x50f42494U, 0x8f1a59e4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x58ed489eU, 0x0b5080aaU, 0xeed388c1U, 0x65e9d116U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008c9dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e2U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000568e7U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00026ce7U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003827U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003402U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000028c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008cc0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00004406U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007421U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c27U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000034c2U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000568c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000034e6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00026ce7U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 4; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3420a8e0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000dU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x10003c27U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000a4e0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00900c05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + HW_SCE_func001(0x3cceb3f7U, 0xb8705e83U, 0xb76e8f69U, 0x1d4e9fdcU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xcbf2af21U, 0x1f4f967fU, 0xa0337d6bU, 0x034fa02cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_func003(0xf6456957U, 0xafc77358U, 0xc6839628U, 0xb22ae4d0U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p55.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p60.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p60.c new file mode 100644 index 0000000000..3cbe9e99f7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p60.c @@ -0,0 +1,223 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t *InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)InData_KeyType; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00006001U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xed19ab94U, 0x93c9c505U, 0x1d873666U, 0x20ab5f24U); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x136006ddU, 0x08a23e9dU, 0x63289167U, 0x1a14175dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xb48f6d49U, 0xf6c5502dU, 0x36addd72U, 0xc7209976U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_func001(0x1329ae05U, 0xb174626dU, 0xf42fe21bU, 0x66e9d647U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x3000a800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x56a4bb4eU, 0x2c0f47d0U, 0x2241eef6U, 0x6234eac4U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0xd0665c19U, 0x04772908U, 0xad4d20a4U, 0xe41fde9aU); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_func002(0xcb399d18U, 0x4323efb7U, 0x1a22dfa6U, 0xf473e241U); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_func002(0x2e60444bU, 0x7c03b08bU, 0xe6c02ef7U, 0xde95dca4U); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_func002(0x6d7ec53dU, 0xf03ac2a7U, 0xb47c9921U, 0x2cc5b591U); + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p60.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p61.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p61.c new file mode 100644 index 0000000000..9f98f751f8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p61.c @@ -0,0 +1,174 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0xc099fa80U, 0x55f8d7e7U, 0xb1b81cd1U, 0xe45dc05cU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x0000088eU; + SCE->REG_04H = 0x0000c100U; + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0xc4afbe43U, 0xfbe23476U, 0x3869f8fbU, 0xa1ddf110U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x0000488eU; + SCE->REG_04H = 0x0000c100U; + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0x222a7ebeU, 0xfa5080beU, 0x9dc5000cU, 0x2cb50d11U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00000c9eU; + SCE->REG_04H = 0x0000c100U; + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0x96b0d912U, 0x5f0ba5e6U, 0x3ffcce56U, 0xbd9481eeU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x000049aeU; + SCE->REG_04H = 0x0000c100U; + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0xec8fa4d2U, 0x1a6dc8d2U, 0x4067dba7U, 0x266ae636U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x000006beU; + SCE->REG_04H = 0x0000c100U; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0x6d31fdbeU, 0xf4147098U, 0x7a374888U, 0xbb9e479cU); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0x797ba3d2U, 0x4de21909U, 0x07e3a19dU, 0xb981a166U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0x2debffd0U, 0x75734739U, 0xf9eabd2dU, 0x004be10eU); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0x4cfe8eb3U, 0xb71cf565U, 0x8714d05fU, 0x093a1f3dU); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0xa919894bU, 0x90f11cf5U, 0x3cdb87c5U, 0x8882d91fU); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p61.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p62.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p62.c new file mode 100644 index 0000000000..39cba1dc47 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p62.c @@ -0,0 +1,133 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x04806bcfU, 0xb5854414U, 0xfbf66061U, 0xa4c71fc9U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x3784ca5eU, 0x302e119eU, 0xa3fc989cU, 0x09811f45U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x087df25eU, 0x779ae4feU, 0xe50d522eU, 0x3dbe8185U); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0xe40057a3U, 0xead57b67U, 0xc952cde2U, 0x9d709058U); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0xf9c9f3f5U, 0xc7667faeU, 0xf459287cU, 0xfa7570ccU); + } + HW_SCE_func001(0x69c4bcb1U, 0xb00dc893U, 0x4623fdf8U, 0x6e8dd8dbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x52d2dcbbU, 0x678c2567U, 0x797c8252U, 0xdf776986U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xca3b5acfU, 0x43d40531U, 0x1bf0b353U, 0xd6c5b6cdU); + } + else + { + HW_SCE_func002(0xfcb4c6feU, 0x5d137a36U, 0xf872aea4U, 0xa77ebf44U); + } + HW_SCE_func003(0x05a69693U, 0x5a5507b3U, 0xbceaeed1U, 0x4b659931U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func003(0xc4af11caU, 0xbdaa0ea4U, 0xd888cdb6U, 0xe9083d8aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p62.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p63.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p63.c new file mode 100644 index 0000000000..511d2492e4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p63.c @@ -0,0 +1,234 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t *InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)InData_KeyType; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00006301U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x1181b7efU, 0x556d5729U, 0x8e42ba80U, 0xfc72400aU); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0x0f6f0746U, 0x8225ff4bU, 0x73e11648U, 0x142bdf5eU); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xa2b7f698U, 0x3fc26c77U, 0xf118c4a2U, 0x7f6a6cb7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x5c586ce9U, 0xa51ddc06U, 0xff572e79U, 0x132f7c1dU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_func001(0x6aaef7e4U, 0x64119651U, 0xa6b9e1aaU, 0xbe50041cU); + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x3000a800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x68565bc4U, 0x5f1eb3deU, 0xfc951fb7U, 0xd93bf4eeU); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x7da76e5aU, 0xc1494e81U, 0xd6661801U, 0x5e0ec87cU); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_func002(0x70291ae4U, 0xcf68385aU, 0x7af0b727U, 0xffb9508eU); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_func002(0x2a2948b6U, 0xd36e6ccdU, 0x1ed0187eU, 0x2772eba4U); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_func002(0xc5a7b7ebU, 0x9b24214bU, 0xe12cdb8fU, 0x16062e27U); + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p63.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p64.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p64.c new file mode 100644 index 0000000000..bb8f532f77 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p64.c @@ -0,0 +1,179 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0x624aadcbU, 0xe50f8155U, 0x4711c39cU, 0xfd2ef7b1U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0000888eU; + SCE->REG_04H = 0x0000c100U; + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0xc4422ed7U, 0x384f3f12U, 0x38eb866fU, 0x68b545e7U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0000c88eU; + SCE->REG_04H = 0x0000c100U; + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0x32d07d47U, 0x3dd04bfbU, 0x9032f3fdU, 0x62191c6eU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008c9eU; + SCE->REG_04H = 0x0000c100U; + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0x99a6263aU, 0xe91d3aa8U, 0x104e62bcU, 0xcd57cfa6U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0000c9aeU; + SCE->REG_04H = 0x0000c100U; + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + HW_SCE_func001(0x5dffe167U, 0x69f359d3U, 0xb3fa7680U, 0x8792a6a3U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x000086beU; + SCE->REG_04H = 0x0000c100U; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0xff48cf0eU, 0xc56d4fb1U, 0x690b30c9U, 0xec43e750U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0xd3fc3930U, 0x1ad2ed42U, 0xaf63893cU, 0x7cf9d506U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0xfcb04506U, 0xdfd7fbebU, 0xac25a3fbU, 0x3025878eU); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0xe54e9a91U, 0x5cf3e032U, 0x7fd66d73U, 0x2b438f10U); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func206(); + HW_SCE_func002(0x144f6b8bU, 0x0696d7b6U, 0x13c8804cU, 0x40bbcfbdU); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p64.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p65.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p65.c new file mode 100644 index 0000000000..894977c74e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p65.c @@ -0,0 +1,133 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x877ac003U, 0x1f55a80eU, 0x56f67726U, 0xb2fb1b27U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x020800e5U, 0x3739cd04U, 0x46c9610cU, 0xafb0bc84U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0xba294c51U, 0x14afd546U, 0x1c1f8d84U, 0xb8b3e317U); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0x93006859U, 0x575f3d59U, 0xc776b5e7U, 0xd92e9ecbU); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + HW_SCE_func002(0xc74f2e16U, 0x4e88787cU, 0x52b4731cU, 0x6d9858d0U); + } + HW_SCE_func001(0x0fd7d09bU, 0xa7b8d27cU, 0x46c75262U, 0x8075b7beU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x4037084eU, 0xff71ad85U, 0x1b8b2e00U, 0x99824528U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x050a08feU, 0x4fc6390eU, 0xa111da36U, 0x975d32a8U); + } + else + { + HW_SCE_func002(0x0d3b9483U, 0x0aa68236U, 0x866fe1a6U, 0xee77a58dU); + } + HW_SCE_func003(0xcd084c94U, 0xd2324d31U, 0x5dd83952U, 0xcebaf319U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func003(0x35ca3d10U, 0xbe886693U, 0xae5873e3U, 0x2477eafbU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p65.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p70.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p70.c new file mode 100644 index 0000000000..1219e6c114 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p70.c @@ -0,0 +1,225 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007001U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x4f76d710U, 0x3506fc3eU, 0x474af469U, 0xfd2b083cU); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xce07a567U, 0xf26796a2U, 0x622be46aU, 0x84e28ab5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x4a210f5fU, 0x89c79c1dU, 0x70a9661eU, 0x7edc2d6eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0000063cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00e00806U; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_func205(); + HW_SCE_func001(0xe080e469U, 0xe932f980U, 0x52beaaf4U, 0x36d108d4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x029f7674U, 0x495e76a6U, 0x6b51e1dbU, 0x08298bccU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x98ebe856U, 0x9ca0ca1eU, 0xe6c0bfb3U, 0x06203b15U); + } + else + { + HW_SCE_func002(0x89e65a8eU, 0xf24a4ce1U, 0x6c248261U, 0x681c05c8U); + } + HW_SCE_func003(0xe40afa1aU, 0xaa12b29fU, 0xc038d54eU, 0x3f35a595U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p70.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p71.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p71.c new file mode 100644 index 0000000000..d9dbe4282c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p71.c @@ -0,0 +1,114 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128CcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x574fb855U, 0x3bb4cd74U, 0x3bb0e245U, 0x4d89454aU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00e006beU; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + HW_SCE_func207(); + HW_SCE_func002(0x9ee3ad58U, 0x28328df2U, 0x97d79733U, 0x67b60daaU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p71.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p72.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p72.c new file mode 100644 index 0000000000..7e54d41208 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p72.c @@ -0,0 +1,234 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub(const uint32_t *InData_TextLen, const uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0xbfedbb70U, 0x35182d4bU, 0xb2629fb6U, 0x94cab2abU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0xd82804c6U, 0x8706f8e8U, 0xab5f2a5cU, 0xdb64b1c5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xc0be7778U, 0x6c18ba79U, 0x1566ea97U, 0x478a36c6U); + } + else + { + HW_SCE_func002(0xd36e91d0U, 0xa5f26c5aU, 0x7417b4b8U, 0x65d0d7d7U); + } + HW_SCE_func003(0xd2dc8619U, 0x9ec5a34bU, 0x8e45c32cU, 0x9adc9855U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x8f0494d6U, 0x8334273dU, 0x81a350a5U, 0x902b59baU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0x7d96daf0U, 0xf6ca0690U, 0xf491df6eU, 0xfe413cc6U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00e006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + HW_SCE_func002(0x252f8db7U, 0x72b6eb6cU, 0xaa304b08U, 0x67357b0cU); + } + else + { + HW_SCE_func002(0x90e12ea7U, 0x5ec40150U, 0x9adb4738U, 0x6cc52e90U); + } + HW_SCE_func001(0x3efa62bfU, 0x3895f0daU, 0xf1ec52c8U, 0x5898ef8fU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000e84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + HW_SCE_func003(0x6d40063eU, 0x1d491143U, 0x1d451713U, 0x1355d1a3U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p72.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p73.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p73.c new file mode 100644 index 0000000000..77e7d7efcc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p73.c @@ -0,0 +1,225 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007301U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x4e150ef1U, 0x31b1008bU, 0x19b488daU, 0x42810d0aU); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x60b7262fU, 0xd87e9a85U, 0x186ff7acU, 0xfdc7c8b8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x98793f82U, 0x9ac6c5c5U, 0x71d4d29cU, 0x19c0807eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0000063cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00f00806U; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_func205(); + HW_SCE_func001(0x794cebc2U, 0x27a53180U, 0xd459ce03U, 0xaef0d86bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0xee6ff299U, 0xd58cdec1U, 0xbadd2f4fU, 0xb7d39176U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xe11df6acU, 0x3a2600d2U, 0x96bab086U, 0xd4ccc931U); + } + else + { + HW_SCE_func002(0x902118a3U, 0x2d470afaU, 0x8d517b92U, 0xf15d228fU); + } + HW_SCE_func003(0xd534ab9dU, 0x60f0a05dU, 0x1a2b787aU, 0xc8fe0ccfU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p73.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p74.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p74.c new file mode 100644 index 0000000000..494ab32e31 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p74.c @@ -0,0 +1,96 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128CcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x8fcd9e5fU, 0x6f9ca8f0U, 0x22e9a3dfU, 0x249a2646U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00f006beU; + SCE->REG_04H = 0x0000c100U; + for (iLoop = 0; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + } + HW_SCE_func207(); + HW_SCE_func002(0x48ebfd0eU, 0xf475c055U, 0x9348b29fU, 0xaada3241U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_230630/230630/RA4M1/Cryptographic/HW_SCE_p74_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p75.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p75.c new file mode 100644 index 0000000000..c9be716862 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p75.c @@ -0,0 +1,338 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_MAC, const uint32_t *InData_MACLength, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x03277c49U, 0x8e193f66U, 0xc9cf63feU, 0xb74618d0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0xb35d1e0fU, 0xff00e7b2U, 0x96c1dc5fU, 0xfe72ba7dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xa299f3abU, 0x026740b2U, 0x4394de1fU, 0xf0d640b3U); + } + else + { + HW_SCE_func002(0x6b11547eU, 0x6e17df68U, 0xbce39ca3U, 0x90ff5737U); + } + HW_SCE_func003(0x8ac8c4aaU, 0x9d144aabU, 0x6de24d59U, 0x09a0a1c9U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MACLength[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x380088e0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x34202867U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x61fcff09U, 0x42c625fdU, 0x45bab911U, 0x7738038bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xd9fe57a2U, 0x5b414279U, 0xef7fa9f1U, 0xf1cd71f4U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x6a98724dU, 0xcd5807e2U, 0x42f14461U, 0x136fb23bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + HW_SCE_func001(0xf4f241ceU, 0x28abadc0U, 0x3061c997U, 0xc3a9e8c1U); + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + SCE->REG_A4H = 0x00000c5dU; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x6749b394U, 0x65ebdb0fU, 0x24614a0dU, 0x264c70a8U); + } + else + { + HW_SCE_func002(0xbc34b019U, 0xdd98ddb8U, 0xb89d3639U, 0x1cc775caU); + } + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000ec4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x010006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002867U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00050805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func001(0x22dd6ae1U, 0x455af888U, 0x4c2723d9U, 0x2dcc539eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xe4541ebeU, 0x78c42eafU, 0xd11f806dU, 0x2877f4f4U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func003(0xc92b5b5cU, 0x9a282efeU, 0x5cee6eb1U, 0x8203d38cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p75.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p76.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p76.c new file mode 100644 index 0000000000..11ce2ea935 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p76.c @@ -0,0 +1,237 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007601U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xcc7af8caU, 0x72c14309U, 0xcf01651bU, 0x216e102bU); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0x7760ecb2U, 0x92dfd01eU, 0xa3dc67a0U, 0xe9f2e535U); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x2bc4792dU, 0x35a8ac2aU, 0x1695cdcaU, 0x179bb722U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x74bd4587U, 0xbc302cc5U, 0xe3e728c3U, 0x21ac9e1cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0000063cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00058c5eU; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_func205(); + HW_SCE_func001(0x5ca267faU, 0x96c7704dU, 0x6142dfbaU, 0x5a344361U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x636c6ea4U, 0x3577a818U, 0x426ad611U, 0xeeb15feaU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xff965dcfU, 0x66a3c209U, 0xf5d7f5c7U, 0x34d3cfbcU); + } + else + { + HW_SCE_func002(0x4787300dU, 0xa7d863f8U, 0xf9179a6eU, 0xf197c741U); + } + HW_SCE_func003(0x0605b95cU, 0x24c9b37bU, 0x0ac5474fU, 0x37d910e5U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p76.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p77.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p77.c new file mode 100644 index 0000000000..8c9e72e5d5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p77.c @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256CcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0xd86ce509U, 0xa426411bU, 0x0ecedb6bU, 0x1d12ffb6U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00e086beU; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + HW_SCE_func207(); + HW_SCE_func002(0xffe1cab8U, 0x6d4114bdU, 0x942c97ddU, 0x3b98d4a8U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p77.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p78.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p78.c new file mode 100644 index 0000000000..e2be79ca4b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p78.c @@ -0,0 +1,236 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0xe33fc47bU, 0x30fd9834U, 0x07a46aebU, 0x1b3e4bfeU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0xca49a938U, 0xdd98fe7eU, 0xf755568eU, 0x7f5c6088U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xae59daf8U, 0x357657b3U, 0x783de32dU, 0x5a14c65bU); + } + else + { + HW_SCE_func002(0xa564cd90U, 0x63af148bU, 0x4bf414bdU, 0x50eb4925U); + } + HW_SCE_func003(0x2aaf06ddU, 0xec87a067U, 0x4d7e15ffU, 0x901854fcU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0xf9db203fU, 0xf5fb0808U, 0x93af0526U, 0x211add2fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0x6a5e5b39U, 0x79427bd5U, 0xb1c833c6U, 0xe72e9266U); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00e086bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + HW_SCE_func002(0x173944a8U, 0x0e7bafd8U, 0x19114cb7U, 0xe75b3f8cU); + } + else + { + HW_SCE_func002(0xe72ebe74U, 0xaf093eddU, 0xe8f8b697U, 0xf6d4191fU); + } + HW_SCE_func001(0x66a54a33U, 0x2ebea6baU, 0x04519495U, 0x3ae3bc45U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000e84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x000089cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + HW_SCE_func003(0x15387217U, 0x8afab3beU, 0x2cca8763U, 0x51327d35U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p78.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p79.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p79.c new file mode 100644 index 0000000000..fdb15014b7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p79.c @@ -0,0 +1,237 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007901U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xb20a7c92U, 0x1dd2b54fU, 0x6aed6a93U, 0xcccee09dU); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0x974ff911U, 0xf030adaaU, 0xd37d1bcbU, 0xf5d204d2U); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xfe5cb552U, 0xf493318bU, 0x659f1a66U, 0x6b76895bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x9247c15aU, 0xd573b5a3U, 0x561d0112U, 0x7a4b1e64U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0000063cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00058c5eU; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + HW_SCE_func205(); + HW_SCE_func001(0x327611a5U, 0xfa0ea4a5U, 0x5a23ab4dU, 0x62f55590U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x4c83bcb3U, 0xf5ed605aU, 0x49f449a1U, 0x25cf72c5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xb44b63e2U, 0x29c4463fU, 0x74b891c2U, 0xb0e9a2b5U); + } + else + { + HW_SCE_func002(0x04228297U, 0xdc09d514U, 0xbfde7f4eU, 0x36f7606bU); + } + HW_SCE_func003(0x8685c57bU, 0x697d3074U, 0xef5986aeU, 0x2a8e8ee6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p79.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p80.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p80.c new file mode 100644 index 0000000000..2dfd3c5560 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p80.c @@ -0,0 +1,97 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256CcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x3ef4c7f0U, 0x74e340fdU, 0x4568b95aU, 0x5b8f40e6U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00f086beU; + SCE->REG_04H = 0x0000c100U; + for (iLoop = 0; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + } + HW_SCE_func207(); + HW_SCE_func002(0xf5b910a7U, 0x90d64152U, 0x9aece215U, 0x3e8e44daU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_230630/230630/RA4M1/Cryptographic/HW_SCE_p80_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p81.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p81.c new file mode 100644 index 0000000000..b6d57a5025 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p81.c @@ -0,0 +1,341 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_MAC, const uint32_t *InData_MACLength, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0xa70b2107U, 0x1b584345U, 0x4125e25bU, 0x955e95b3U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0xcf41d2b5U, 0xfb1010c9U, 0x708df706U, 0x22abf5b8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x3267a8e0U, 0xa81aea60U, 0x31d3670fU, 0xf221a76dU); + } + else + { + HW_SCE_func002(0x295e6f7dU, 0x5fcaa357U, 0x81c1c79bU, 0x678302b2U); + } + HW_SCE_func003(0xb78d9597U, 0xb85fa1adU, 0xafdbc15dU, 0x44553c60U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MACLength[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x380088e0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x34202867U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x098cc749U, 0xe3808805U, 0x697846a2U, 0x96f9a032U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x3a78cafeU, 0xf31528d0U, 0xaae53fd9U, 0x87af9b37U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0xf76adefbU, 0x19a0b516U, 0xbf0475e1U, 0x56880b94U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0x31c7fd38U, 0x8d2d7b40U, 0xf483d8abU, 0x7f9ae0c9U); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x000086bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002860U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008c5dU; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x32b3a18fU, 0xe36f31d8U, 0x133dca0cU, 0xdd77eadfU); + } + else + { + HW_SCE_func002(0x21070664U, 0xf0d841deU, 0x6e301872U, 0x6f4e5340U); + } + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000ec4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x010086bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002867U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x12003c23U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00050805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func001(0x369c85c1U, 0x1b74ddc3U, 0xdfa9a261U, 0xec2f7e00U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x282747faU, 0x78607218U, 0xd4b6909eU, 0xc9b6a68bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func003(0xe1d4dc16U, 0x646d60e1U, 0x62cb1049U, 0x63df74cbU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p81.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p84.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p84.c new file mode 100644 index 0000000000..59a4f08e1a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p84.c @@ -0,0 +1,603 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes128PlainKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008401U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800103e0U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x2b38f6e1U, 0xb2ee9d83U, 0x265b79ceU, 0x4527c8b5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xfffffff0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x2d26a53cU, 0x3411202dU, 0x4edbbc4cU, 0x25fd475dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xdf748238U, 0x22304026U, 0x928b4178U, 0x645fcbe6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0xccbad478U, 0xf3238b4cU, 0xba462dc1U, 0x695d7d82U); + OFS_ADR = InData_SharedKeyIndex[0]*8; + SCE->REG_A4H = 0x400c3a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x129e32e8U); + SCE->REG_A4H = 0x400c0a0cU; + SCE->REG_E0H = 0x81010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x42fa063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR + 3]; + HW_SCE_func001(0xeb350f83U, 0x7d2faa02U, 0xb4a60d94U, 0x16b362b3U); + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0008680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[0]; + SCE->REG_100H = InData_SessionKey[1]; + SCE->REG_100H = InData_SessionKey[2]; + SCE->REG_100H = InData_SessionKey[3]; + HW_SCE_func001(0x928739beU, 0x12238d6cU, 0x73cf8e31U, 0xceac6ccaU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0009680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[4]; + SCE->REG_100H = InData_SessionKey[5]; + SCE->REG_100H = InData_SessionKey[6]; + SCE->REG_100H = InData_SessionKey[7]; + HW_SCE_func001(0xefd962f4U, 0x56443df8U, 0xf6f69197U, 0x54f495a6U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x35cf0f9dU, 0xa0fe8cf1U, 0xddee3d74U, 0xfbe6f5a5U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + SCE->REG_A4H = 0x43e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + HW_SCE_func001(0x65a6e055U, 0x939551e8U, 0xe6b5702bU, 0x6b3bbc7cU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x076faf67U, 0xc204b8f4U, 0x263186b8U, 0xc6195441U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x10be6df0U, 0x4489ee44U, 0x461e50caU, 0xb639e428U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x1e59e0abU, 0xd0a58cfaU, 0xedde2681U, 0x7f213335U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0xdb4518b5U, 0x83279165U, 0x5eb6fbc7U, 0x93bcd37cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_func001(0x3f1e4052U, 0x7830c312U, 0x6af66249U, 0x088be5baU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x5a847decU, 0xa628fa18U, 0x79d8e198U, 0x403cd5dfU); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00000885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + SCE->REG_A4H = 0x43e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + HW_SCE_func001(0x452ebb38U, 0xad4b097aU, 0x10e2d767U, 0xca22d27fU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0xc2df453bU, 0xf7cd3032U, 0x420bbc49U, 0x8b8267d5U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0x06ecda62U, 0x02879bd3U, 0x8fb2beafU, 0x414f899dU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic_PlainKey/HW_SCEp_p84.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p85.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p85.c new file mode 100644 index 0000000000..6f64200fa9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p85.c @@ -0,0 +1,653 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes256PlainKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008501U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800103e0U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x046050b8U, 0x5f4634c3U, 0xeaef7838U, 0x27b7e43aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xfffffff0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x52981ea7U, 0x2f8abb24U, 0x9d8e5cbbU, 0x032ecf88U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xd86d5ebdU, 0x2d9e1a60U, 0x69e14652U, 0xef15c0d7U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x995b2953U, 0x9c9489b4U, 0xd336e83cU, 0x0c49eadeU); + OFS_ADR = InData_SharedKeyIndex[0]*8; + SCE->REG_A4H = 0x400c3a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x129e32e8U); + SCE->REG_A4H = 0x400c0a0cU; + SCE->REG_E0H = 0x81010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x42fa063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR + 3]; + HW_SCE_func001(0xd24fe8a7U, 0xa1caffafU, 0x739b49c1U, 0x6efa0559U); + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0008680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[0]; + SCE->REG_100H = InData_SessionKey[1]; + SCE->REG_100H = InData_SessionKey[2]; + SCE->REG_100H = InData_SessionKey[3]; + HW_SCE_func001(0x67b3e11aU, 0x2b37be6eU, 0x90bd0173U, 0xa1b8a807U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0009680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[4]; + SCE->REG_100H = InData_SessionKey[5]; + SCE->REG_100H = InData_SessionKey[6]; + SCE->REG_100H = InData_SessionKey[7]; + HW_SCE_func001(0x615968c2U, 0xd2fdab2aU, 0x0bcb1933U, 0xd2395d81U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xe0860099U, 0x9b0e3201U, 0xef96a873U, 0x9ec8430eU); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + SCE->REG_A4H = 0x43e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + HW_SCE_func001(0x8525eb6cU, 0x8fb5ac0fU, 0x0aa7a378U, 0x014e7acdU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_A4H = 0x41e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0x890c7546U, 0xcd12f341U, 0x8a61e47bU, 0xa58fb1e8U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xc3e7a455U, 0x0d1c8705U, 0x16d865efU, 0xd502572aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x28782014U, 0xca7d9527U, 0x66211539U, 0x7825e0c6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x747dfec6U, 0xe6140a23U, 0x465afcc8U, 0xa0b72700U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0x792cb424U, 0xa0e331e9U, 0xa4c7f197U, 0xb90337e2U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_func001(0x9ee5d86bU, 0x1bc1ef1bU, 0xf118b20aU, 0xb0b6751cU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x2590ac62U, 0x0cebe7e6U, 0x9d4592f6U, 0x152beb4dU); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_104H = 0x00000761U; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x43e086bfU; + SCE->REG_00H = 0x00001123U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000122U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0x028b7994U, 0xe2e79faaU, 0x45a1cbdeU, 0x99a2c6d1U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + HW_SCE_func001(0xc076a3cdU, 0x8ddadcfcU, 0x5751d101U, 0xd1ebb33cU); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0x1af3fa71U, 0xafcf6218U, 0x86941d73U, 0x72f24b45U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_230630/230630/RA4M1/Cryptographic_PlainKey/HW_SCEp_p85_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p86.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p86.c new file mode 100644 index 0000000000..d3be3ecebe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p86.c @@ -0,0 +1,653 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateUpdatePlainKeyRingKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008601U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800103e0U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x0b30da3aU, 0xe9dc5c7eU, 0x774519f5U, 0x8834f0d0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xfffffff0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x7ac4a2dbU, 0x1bbf9c13U, 0x5a9a5884U, 0xbe4ec95aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xf1b551eaU, 0xca9b4a97U, 0xbb91c91eU, 0x1775cf1aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x722dd39eU, 0xd1a400afU, 0x28a5525aU, 0x8628711fU); + OFS_ADR = InData_SharedKeyIndex[0]*8; + SCE->REG_A4H = 0x400c3a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x129e32e8U); + SCE->REG_A4H = 0x400c0a0cU; + SCE->REG_E0H = 0x81010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x42fa063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR + 3]; + HW_SCE_func001(0x9cb0e2ccU, 0xd05c6cf5U, 0x72da7489U, 0xae89703fU); + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0008680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[0]; + SCE->REG_100H = InData_SessionKey[1]; + SCE->REG_100H = InData_SessionKey[2]; + SCE->REG_100H = InData_SessionKey[3]; + HW_SCE_func001(0x4110ef44U, 0xcea3f21fU, 0xc998f32bU, 0x872f08e2U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0009680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[4]; + SCE->REG_100H = InData_SessionKey[5]; + SCE->REG_100H = InData_SessionKey[6]; + SCE->REG_100H = InData_SessionKey[7]; + HW_SCE_func001(0xb1c9c3b7U, 0x7346a6f6U, 0x4e1b168fU, 0xfaa6451dU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x80c18131U, 0xf5555b0eU, 0x5c011bdfU, 0x4a14326cU); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xda0168d1U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + SCE->REG_A4H = 0x43e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[4] = SCE->REG_100H; + OutData_InstData[5] = SCE->REG_100H; + OutData_InstData[6] = SCE->REG_100H; + OutData_InstData[7] = SCE->REG_100H; + HW_SCE_func001(0xa0f047b2U, 0xe1478f0fU, 0x6c5ce606U, 0xe4bd8512U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_A4H = 0x41e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[8] = SCE->REG_100H; + OutData_InstData[9] = SCE->REG_100H; + OutData_InstData[10] = SCE->REG_100H; + OutData_InstData[11] = SCE->REG_100H; + HW_SCE_func001(0x3d12bc49U, 0x0626ac2bU, 0x67ad583eU, 0xbd55550bU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[12] = SCE->REG_100H; + OutData_InstData[13] = SCE->REG_100H; + OutData_InstData[14] = SCE->REG_100H; + OutData_InstData[15] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x85493597U, 0xb917951eU, 0x198034feU, 0xa8cee0b4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xb690776aU, 0x32dffc49U, 0xfff1a6a8U, 0x416329dfU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0xb29a3390U, 0x8c5e4403U, 0xc9c25eccU, 0x3ff63e44U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[3] = SCE->REG_100H; + HW_SCE_func003(0xdc9c0b53U, 0x8c2fa011U, 0x87b542f7U, 0x4b78c524U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_func001(0x755f5cc4U, 0x92d922e1U, 0xfdcbbd51U, 0xd4afc0aaU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xed26366aU, 0x5feabe52U, 0xd303b728U, 0xcde0c6c8U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xda0168d1U); + SCE->REG_104H = 0x00000761U; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x43e086bfU; + SCE->REG_00H = 0x00001123U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000122U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[4] = SCE->REG_100H; + OutData_InstData[5] = SCE->REG_100H; + OutData_InstData[6] = SCE->REG_100H; + OutData_InstData[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[8] = SCE->REG_100H; + OutData_InstData[9] = SCE->REG_100H; + OutData_InstData[10] = SCE->REG_100H; + OutData_InstData[11] = SCE->REG_100H; + HW_SCE_func001(0x4a91dc05U, 0xb9573f8aU, 0xe21176a0U, 0x1d4254dcU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[12] = SCE->REG_100H; + OutData_InstData[13] = SCE->REG_100H; + OutData_InstData[14] = SCE->REG_100H; + OutData_InstData[15] = SCE->REG_100H; + HW_SCE_func001(0x88046d6aU, 0x472e59e4U, 0x2a647995U, 0xe158a673U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[3] = SCE->REG_100H; + HW_SCE_func003(0xca984a1fU, 0xca8616e7U, 0xd721353dU, 0x8ba9b685U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_240119/240119/RA4M1/Cryptographic_PlainKey/HW_SCEp_p86_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p87.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p87.c new file mode 100644 index 0000000000..ef5cd835a8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p87.c @@ -0,0 +1,653 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes128XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008701U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000ce7U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0xd7f83c6aU, 0x40157d24U, 0x75b98bfcU, 0xd4e29e1dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xfffffff0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x8f4899b2U, 0x42ce94beU, 0x1c929b57U, 0x65a9f00aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x136515a8U, 0xcbfe3c1eU, 0xb5c04a26U, 0xed3d0d06U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0xd31bc27eU, 0xfa51eb81U, 0x3afc1603U, 0x9dba13b3U); + OFS_ADR = InData_SharedKeyIndex[0]*8; + SCE->REG_A4H = 0x400c3a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x129e32e8U); + SCE->REG_A4H = 0x400c0a0cU; + SCE->REG_E0H = 0x81010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x42fa063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR + 3]; + HW_SCE_func001(0xbb07333bU, 0x1ced036fU, 0x738c8fdbU, 0xd93c2a27U); + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0008680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[0]; + SCE->REG_100H = InData_SessionKey[1]; + SCE->REG_100H = InData_SessionKey[2]; + SCE->REG_100H = InData_SessionKey[3]; + HW_SCE_func001(0x6ca1d45dU, 0x8d854a62U, 0x4eab7c9bU, 0xea1f2c86U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0009680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[4]; + SCE->REG_100H = InData_SessionKey[5]; + SCE->REG_100H = InData_SessionKey[6]; + SCE->REG_100H = InData_SessionKey[7]; + HW_SCE_func001(0xa357dd65U, 0x247297dfU, 0x314188b7U, 0x27b9b7ebU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xb8684052U, 0xc9857894U, 0x3867c3e4U, 0xf07616c2U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x2d8daf39U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + SCE->REG_A4H = 0x43e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + HW_SCE_func001(0x2d80595cU, 0xe51db6a7U, 0xf5d5d55aU, 0x3bc0fcddU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_A4H = 0x41e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0x55329028U, 0x440900fbU, 0x9ebf1aaeU, 0x43b05a7aU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x34432947U, 0xcf5f52d3U, 0xe566bbbdU, 0x0e633757U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x4329a13cU, 0x7ea3b844U, 0x3db6c977U, 0x78fb1082U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x245a1b51U, 0x7661a44eU, 0x5f0df10bU, 0x8dca005bU); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0xec110d41U, 0x24765d84U, 0xe2f095d9U, 0x32d12ca0U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_func001(0x74745802U, 0x94b5da2eU, 0xd156499bU, 0x7687a57fU); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xc23cde81U, 0x790a2f24U, 0xcc15c1eeU, 0xc9d475c2U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x2d8daf39U); + SCE->REG_104H = 0x00000761U; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x43e086bfU; + SCE->REG_00H = 0x00001123U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000122U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0x492cbe9eU, 0x43bd6eeaU, 0xc223afe4U, 0x4404e219U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + HW_SCE_func001(0xb8808aa8U, 0x5ff991a3U, 0xab71689cU, 0x5af1efd0U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0x4a88f02eU, 0x3ba00792U, 0x7b0a0c43U, 0xebbadd2fU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_230630/230630/RA4M1/Cryptographic_PlainKey/HW_SCEp_p87_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p88.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p88.c new file mode 100644 index 0000000000..839aaf33b6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p88.c @@ -0,0 +1,763 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes256XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008801U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000ce7U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_func001(0x7812c91cU, 0x79980cf1U, 0x1b960d51U, 0xcb864decU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xfffffff0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x669f2861U, 0x75c7ec15U, 0x001dc3ddU, 0xc7a034e6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x6f3ae3deU, 0xf5389f99U, 0xcbee3cecU, 0xa0ccfcb6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x9f3e45b6U, 0xb4f7f68eU, 0xfd571442U, 0x07c6ffe0U); + OFS_ADR = InData_SharedKeyIndex[0]*8; + SCE->REG_A4H = 0x400c3a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x129e32e8U); + SCE->REG_A4H = 0x400c0a0cU; + SCE->REG_E0H = 0x81010000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x42fa063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR + 3]; + HW_SCE_func001(0x9f4c843cU, 0x6c25c292U, 0xc4cabfcfU, 0xfdc89425U); + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0008680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[0]; + SCE->REG_100H = InData_SessionKey[1]; + SCE->REG_100H = InData_SessionKey[2]; + SCE->REG_100H = InData_SessionKey[3]; + HW_SCE_func001(0xe467b33aU, 0x68096e86U, 0x69383a5eU, 0x8da81018U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0009680dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[4]; + SCE->REG_100H = InData_SessionKey[5]; + SCE->REG_100H = InData_SessionKey[6]; + SCE->REG_100H = InData_SessionKey[7]; + HW_SCE_func001(0x8ee89e62U, 0x1702b576U, 0x1a47faebU, 0x7cc8590fU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x06b49853U, 0x70fc0efaU, 0xb3d1ffa2U, 0xc8709266U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5737b943U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + SCE->REG_A4H = 0x43e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + HW_SCE_func001(0x69969a1eU, 0xa7f2d3c1U, 0x5c53732bU, 0xbe560befU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_A4H = 0x41e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0x6b30d18aU, 0x3ffd8b74U, 0x53a78328U, 0x7f0bdc03U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + SCE->REG_A4H = 0x41e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + HW_SCE_func001(0x2a84f900U, 0x9ee0f1b2U, 0x46ee44bdU, 0xab188c48U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[12]; + SCE->REG_100H = InData_InstData[13]; + SCE->REG_100H = InData_InstData[14]; + SCE->REG_100H = InData_InstData[15]; + SCE->REG_A4H = 0x41e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[16] = SCE->REG_100H; + OutData_KeyIndex[17] = SCE->REG_100H; + OutData_KeyIndex[18] = SCE->REG_100H; + OutData_KeyIndex[19] = SCE->REG_100H; + HW_SCE_func001(0x9c7b80c4U, 0x27d73f3eU, 0xc260b8caU, 0x29d7179bU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[20] = SCE->REG_100H; + OutData_KeyIndex[21] = SCE->REG_100H; + OutData_KeyIndex[22] = SCE->REG_100H; + OutData_KeyIndex[23] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[16]; + SCE->REG_100H = InData_InstData[17]; + SCE->REG_100H = InData_InstData[18]; + SCE->REG_100H = InData_InstData[19]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x6c137248U, 0x2381af58U, 0x32ccda71U, 0xc04f2285U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x9da4e88aU, 0x51866987U, 0x84b2ac8eU, 0x15009c45U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0xdfdc9266U, 0x951e2fceU, 0x3309db47U, 0x9e03e046U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0x760a2a2cU, 0xf884a8c2U, 0xf10bfd10U, 0xf9869f9cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_func001(0xd3e961caU, 0xa9de9718U, 0xc91035e0U, 0x204ce292U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xfd79cc47U, 0x06880f36U, 0xecc79dcaU, 0x85413a7cU); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5737b943U); + SCE->REG_104H = 0x00000761U; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x43e086bfU; + SCE->REG_00H = 0x00001123U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000122U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0xdf816f93U, 0x47525829U, 0x807f9f17U, 0x4c4d33f3U); + SCE->REG_104H = 0x00000761U; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[12]; + SCE->REG_100H = InData_InstData[13]; + SCE->REG_100H = InData_InstData[14]; + SCE->REG_100H = InData_InstData[15]; + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x41e086bfU; + SCE->REG_00H = 0x00001123U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000122U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[16] = SCE->REG_100H; + OutData_KeyIndex[17] = SCE->REG_100H; + OutData_KeyIndex[18] = SCE->REG_100H; + OutData_KeyIndex[19] = SCE->REG_100H; + HW_SCE_func001(0x8ba9f501U, 0x099be69dU, 0xf35ba183U, 0x9d0c67a3U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[20] = SCE->REG_100H; + OutData_KeyIndex[21] = SCE->REG_100H; + OutData_KeyIndex[22] = SCE->REG_100H; + OutData_KeyIndex[23] = SCE->REG_100H; + HW_SCE_func001(0xa5dc0026U, 0xc1de13a4U, 0x4b1ac6a0U, 0xdc937aa6U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0x37122ea1U, 0x54c0dea5U, 0x9aea8f74U, 0x8c4af148U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_230630/230630/RA4M1/Cryptographic_PlainKey/HW_SCEp_p88_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p91.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p91.c new file mode 100644 index 0000000000..0cc6aee64c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p91.c @@ -0,0 +1,360 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_UpdateAes128KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B4H & 0x1dU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009101U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x40543bcaU, 0xee79ca5eU, 0x7e4e115cU, 0xab408d19U); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[0]; + SCE->REG_100H = S_INST2[1]; + SCE->REG_100H = S_INST2[2]; + SCE->REG_100H = S_INST2[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xda0168d1U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4]; + SCE->REG_100H = S_INST2[5]; + SCE->REG_100H = S_INST2[6]; + SCE->REG_100H = S_INST2[7]; + HW_SCE_func001(0xf5684750U, 0xb65448ddU, 0xae1d59b6U, 0x100f6e7bU); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4+4 + 0]; + SCE->REG_100H = S_INST2[4+4 + 1]; + SCE->REG_100H = S_INST2[4+4 + 2]; + SCE->REG_100H = S_INST2[4+4 + 3]; + HW_SCE_func001(0xd678d933U, 0xf3368dceU, 0x665f65ceU, 0x23237a46U); + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4+8 + 0]; + SCE->REG_100H = S_INST2[4+8 + 1]; + SCE->REG_100H = S_INST2[4+8 + 2]; + SCE->REG_100H = S_INST2[4+8 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0xcabdbe3dU, 0xb447bb55U, 0xd658e088U, 0xa3cd13bfU); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xef138998U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + SCE->REG_A4H = 0x43e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + HW_SCE_func001(0xf7325a34U, 0x2c199b9eU, 0x08feb68bU, 0x9bf08468U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xd95becc3U, 0x13a4b556U, 0x4163dd4aU, 0xb7e4add0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xb1c87d34U, 0x240827a8U, 0x80c18dd2U, 0xb6c19ca6U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0xa27ff213U, 0x59207485U, 0x1e68fcb8U, 0x4ba8f3c6U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0x6a5c84fcU, 0xe74df1e0U, 0x135217f8U, 0x4a34c9ccU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_p91.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p92.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p92.c new file mode 100644 index 0000000000..c81a591c83 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_p92.c @@ -0,0 +1,390 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_UpdateAes256KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B4H & 0x1dU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009201U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x1e49006bU, 0xa8379218U, 0xb9127517U, 0xcb467d04U); + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[0]; + SCE->REG_100H = S_INST2[1]; + SCE->REG_100H = S_INST2[2]; + SCE->REG_100H = S_INST2[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xda0168d1U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4]; + SCE->REG_100H = S_INST2[5]; + SCE->REG_100H = S_INST2[6]; + SCE->REG_100H = S_INST2[7]; + HW_SCE_func001(0x4d6e3494U, 0x8613e864U, 0x6b4ff9f2U, 0x49288caeU); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4+4 + 0]; + SCE->REG_100H = S_INST2[4+4 + 1]; + SCE->REG_100H = S_INST2[4+4 + 2]; + SCE->REG_100H = S_INST2[4+4 + 3]; + HW_SCE_func001(0x61a62fbbU, 0x0eec13d9U, 0xfc8d6007U, 0xd865121cU); + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4+8 + 0]; + SCE->REG_100H = S_INST2[4+8 + 1]; + SCE->REG_100H = S_INST2[4+8 + 2]; + SCE->REG_100H = S_INST2[4+8 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x000b0805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func001(0x236030deU, 0xf7044cf3U, 0x42e830e0U, 0x3c4f3f08U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x600c3a0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x213f32e4U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + SCE->REG_A4H = 0x43e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + HW_SCE_func001(0xad91bbdaU, 0x42a3b34dU, 0x8a149661U, 0xda279a22U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + SCE->REG_A4H = 0x41e006bdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + HW_SCE_func001(0x4c79ec6dU, 0x055e07b6U, 0x3d7a992aU, 0x0296a067U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000684U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x410009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049adU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xe7e70d69U, 0xc2efe34dU, 0xc963fef6U, 0xc28c1c04U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x729dd717U, 0xe7a38086U, 0xd4c37b0fU, 0x98b1a911U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0xb0cdd070U, 0xed1befb5U, 0x3adbbaefU, 0xa7462121U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_func003(0x8f863da1U, 0xfd0d8173U, 0x684c5b5dU, 0x7393d27cU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_230630/230630/RA4M1/Cryptographic/HW_SCE_p92_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3f.c new file mode 100644 index 0000000000..3325f8a733 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3f.c @@ -0,0 +1,503 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextBitLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00076821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00026c21U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000d0c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x2000a820U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000cc6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0xada7a2a7U, 0x3c06c766U, 0xcee96d8cU, 0xbb06f9afU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x20c968f6U, 0x7ca4814cU, 0x7273f13aU, 0x569a4247U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xef49cf67U, 0x79b08e3fU, 0x0f25d451U, 0x920ba087U); + } + else + { + HW_SCE_func002(0x16103be5U, 0x18f5fa4cU, 0xd1e03853U, 0xaea3c1f5U); + } + HW_SCE_func003(0x4ddf8916U, 0x048eb860U, 0xc424455bU, 0xaabb9316U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x79fc81b5U, 0x059e6c78U, 0xf0460d58U, 0x5a190490U); + SCE->REG_E0H = 0x81010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + HW_SCE_func001(0xc195e91dU, 0x6f1bf5e5U, 0x09713592U, 0xce791577U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x00008daeU; + SCE->REG_04H = 0x0000c100U; + iLoop = 0; + if(S_RAM[0] >= 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + HW_SCE_func206(); + HW_SCE_func001(0x6ccff8f0U, 0x6a9b3933U, 0x4a1440c8U, 0x4c71a2e3U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0xd0bae410U, 0x4d1061c6U, 0xf751cda8U, 0x94c38a99U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xa4668cddU, 0xe7c37c21U, 0x705c7557U, 0xa8f88eb4U); + } + else + { + HW_SCE_func002(0x4f1c669eU, 0x21ea31d5U, 0x1e96f4c1U, 0x3ab4e6b8U); + } + HW_SCE_func003(0x38f4dbbaU, 0x93ad1091U, 0x47cf57e0U, 0x7f78ca80U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x211f4540U, 0xf8091d27U, 0xc3bb854cU, 0x0b847558U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0xd9e0ddd6U, 0x4e7f16a9U, 0xa5de5dacU, 0xc5d2ef87U); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x00008dadU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840006U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80840003U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+4 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+5 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+6 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+7 + 0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xffffffffU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00004402U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007484U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000034a0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000368a5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008ca0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002465U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003826U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003843U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c24U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00001484U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c44U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00001041U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c43U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000a440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002822U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00056821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003846U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c43U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003020U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func002(0x3dee1511U, 0xde3b88feU, 0x2e4c5e9aU, 0x2105aeb3U); + } + HW_SCE_func001(0x16223a72U, 0x70c9e73eU, 0x621cf19dU, 0xe6a1dabfU); + SCE->REG_ECH = 0x38000c21U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x00008dadU; + SCE->REG_E0H = 0x81840003U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003826U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c24U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c26U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000842U; + SCE->REG_1D0H = 0x00000000U; + for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c46U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003000U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func002(0x5fd415a4U, 0x053385b5U, 0x1d6211daU, 0xb850974aU); + } + HW_SCE_func001(0x309fc174U, 0x83ac880bU, 0xf4b95fc3U, 0x5bb8b140U); + SCE->REG_ECH = 0x38000c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840006U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+4 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+5 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+6 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+7 + 0] = SCE->REG_100H; + HW_SCE_func002(0x35e1960dU, 0xd45960b2U, 0xe6dadf8cU, 0x914fbfa7U); + } + HW_SCE_func003(0xc5d51ffbU, 0xa4de3279U, 0x9411dddbU, 0xf093895eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb3f.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3i.c new file mode 100644 index 0000000000..5f8e317938 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3i.c @@ -0,0 +1,162 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000b301U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0x7a76264dU, 0x29f884a3U, 0x2bdcd3a2U, 0xf9e03db0U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x2d8daf39U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0x77640d25U, 0x14318a53U, 0x0668c7ebU, 0x022e5cbdU); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x1e0b1d16U, 0xd9250389U, 0x73afb6aeU, 0xaf08cd95U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0x9bbda832U, 0x404b9385U, 0x2c45350fU, 0xb3ec64b1U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0004180dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb3i.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3u.c new file mode 100644 index 0000000000..26ad2d7747 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb3u.c @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x9a9fd229U, 0xb2b401a8U, 0x0717ce6bU, 0xe6b432aeU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x00008daeU; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + HW_SCE_func206(); + HW_SCE_func002(0xd9167d5bU, 0x078a27eeU, 0xcfa43850U, 0x244fa44aU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb3u.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6f.c new file mode 100644 index 0000000000..b5bb49a285 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6f.c @@ -0,0 +1,528 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextBitLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00076821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00026c21U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000d0c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x2000a820U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000cc6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x04a1a3adU, 0xb7ae1bb2U, 0x96919b7aU, 0xae7bca18U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0xd8e7b9ceU, 0x8e48f4d4U, 0x0cf65781U, 0xcbc06fdfU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x494c4865U, 0x975f1863U, 0x1dee465bU, 0x2fe166ecU); + } + else + { + HW_SCE_func002(0xd2c2702fU, 0xa95166c0U, 0xb41110eeU, 0x06c2a737U); + } + HW_SCE_func003(0x64e39d0eU, 0xbaaacb50U, 0x5002b105U, 0x99165728U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x78f0a60aU, 0x5719b14bU, 0xa4385167U, 0x9195283fU); + SCE->REG_E0H = 0x81010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + HW_SCE_func001(0x621d84bbU, 0xe8c8553fU, 0x8ec52b15U, 0xa850847eU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x0000cdaeU; + SCE->REG_04H = 0x0000c100U; + iLoop = 0; + if(S_RAM[0] >= 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + HW_SCE_func206(); + HW_SCE_func001(0x6af85827U, 0x986f2951U, 0xcd494103U, 0x4f332451U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x1a02ab9eU, 0xa489ea6dU, 0x2e2cd1d5U, 0xbcb840cdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x1abad95eU, 0x2a5721e1U, 0x209eafb9U, 0x182c4fa7U); + } + else + { + HW_SCE_func002(0x7dc66de0U, 0x53ae55dbU, 0x2160bba0U, 0x7d5c0f1eU); + } + HW_SCE_func003(0x9a611b88U, 0x9eb9266eU, 0xbadf9271U, 0x5c17d597U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x1369afc1U, 0xe520ca03U, 0x9c86ba8aU, 0x58d9062bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0x56512253U, 0x591af8aaU, 0x317d00e3U, 0x9b083202U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050604U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x0000cd2cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x0000cdadU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840006U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80840003U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+4 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+5 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+6 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+7 + 0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xffffffffU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00004402U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007484U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000034a0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000368a5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008ca0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002465U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003826U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003843U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c24U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00001484U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c44U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00001041U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c43U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000a440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002822U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00056821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003846U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c43U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003020U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func002(0xd677f598U, 0xd2e09b40U, 0x039486f9U, 0xb04463deU); + } + HW_SCE_func001(0xea307e71U, 0x053d7261U, 0x15a2c000U, 0xd5f6b634U); + SCE->REG_ECH = 0x38000c21U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00040644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x0000cdadU; + SCE->REG_E0H = 0x81840003U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003826U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c24U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c26U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000842U; + SCE->REG_1D0H = 0x00000000U; + for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c46U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003000U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func002(0x790cf255U, 0xd2a06165U, 0xc0da2c52U, 0x9db4aba4U); + } + HW_SCE_func001(0xdcf8b5a3U, 0xc198b5caU, 0x4bc15577U, 0xb0cd47f1U); + SCE->REG_ECH = 0x38000c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840006U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+4 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+5 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+6 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+7 + 0] = SCE->REG_100H; + HW_SCE_func002(0xf55d04efU, 0x65c1ba06U, 0x46edae79U, 0x5919b454U); + } + HW_SCE_func003(0x28a11de3U, 0x4dc4fddaU, 0xfdada47dU, 0x3f895a0eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb6f.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6i.c new file mode 100644 index 0000000000..c6d0e423b4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6i.c @@ -0,0 +1,163 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000b601U; + SCE->REG_108H = 0x00000000U; + HW_SCE_func001(0xc360df21U, 0x85ca3bf7U, 0x776419f7U, 0x1483725dU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x2d8daf39U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0xce05b262U, 0xd9c2e222U, 0x3ea8f17fU, 0xde299ffcU); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x9f6891d5U, 0x73922d45U, 0xa03c6f7cU, 0xc62f3bbfU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func003(0xf04c8dd7U, 0x6b239c27U, 0x570de152U, 0x2380be58U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x0004180dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb6i.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6u.c new file mode 100644 index 0000000000..d2275ba15f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb6u.c @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x4c778cd9U, 0xd8ba587aU, 0x9db74827U, 0xcf1851c6U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x0000cdaeU; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + HW_SCE_func206(); + HW_SCE_func002(0xb10ae393U, 0x0f9f09cfU, 0xe84ecfa1U, 0x0b7c1be7U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb6u.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9f.c new file mode 100644 index 0000000000..6764d2af96 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9f.c @@ -0,0 +1,530 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextBitLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00076821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00026c21U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000d0c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x2000a820U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000cc6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0xe3d7cd5fU, 0xfe4d305bU, 0x10ca5e65U, 0xf453caccU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x99091361U, 0x1488f34aU, 0x30a16f63U, 0xcec8b940U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x3566a77fU, 0x3f7e8a14U, 0x94e39633U, 0x192b2e5dU); + } + else + { + HW_SCE_func002(0x531b7461U, 0xdac9105fU, 0x50a1d923U, 0xb0c66d32U); + } + HW_SCE_func001(0x20f0967fU, 0x5bccc8dbU, 0x9828ed15U, 0x5260c813U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x010b0644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func003(0x825432f1U, 0x95184069U, 0x2388bdf5U, 0xd5ed4928U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x79902488U, 0x90ac2eafU, 0x55780219U, 0x37904342U); + SCE->REG_E0H = 0x81010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + HW_SCE_func001(0x4975b4acU, 0x8226d9ddU, 0x491df082U, 0x853efa8bU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x00008daeU; + SCE->REG_04H = 0x0000c100U; + iLoop = 0; + if(S_RAM[0] >= 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + HW_SCE_func206(); + HW_SCE_func001(0x26d5c2bcU, 0xffda44beU, 0x1ca188bcU, 0xd045c96fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x573c4303U, 0x29ee731eU, 0xfa9f417dU, 0xeec5611aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x5c93420eU, 0x625fa6d5U, 0xd92b5d00U, 0x5488c446U); + } + else + { + HW_SCE_func002(0x7f90ca60U, 0x4da9a2ebU, 0x9d1f39bbU, 0x95cdb4b2U); + } + HW_SCE_func001(0xe59e2853U, 0x9d9e56f0U, 0xfbafdeeaU, 0x35934401U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x010b0644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func003(0xbe820c8fU, 0x2c8b1dc6U, 0xec1af11dU, 0xda87d583U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x7915accdU, 0x7ab62473U, 0x775f9db6U, 0x45dc8e36U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0x4de076b9U, 0xb10ac7b9U, 0x4e697c78U, 0x4a57cbe5U); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x00008dadU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840006U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80840003U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+4 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+5 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+6 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+7 + 0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xffffffffU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00004402U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007484U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000034a0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000368a5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008ca0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002465U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003826U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003843U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c24U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00001484U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c44U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00001041U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c43U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000a440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002822U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00056821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003846U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c43U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003020U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func002(0xa62c1099U, 0x3d72cd2bU, 0xc31de1feU, 0x4bee9f13U); + } + HW_SCE_func001(0xb02d577bU, 0x9fd9e562U, 0xb281ff0cU, 0x997d8400U); + SCE->REG_ECH = 0x38000c21U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x00008dadU; + SCE->REG_E0H = 0x81840003U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003826U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c24U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c26U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000842U; + SCE->REG_1D0H = 0x00000000U; + for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c46U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003000U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func002(0xac8ef2b1U, 0xc2fe571cU, 0x1a5adf4eU, 0xf27a67b2U); + } + HW_SCE_func001(0xe8576321U, 0x972e49f3U, 0x05af01efU, 0x19f4699bU); + SCE->REG_ECH = 0x38000c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840006U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+4 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+5 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+6 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+7 + 0] = SCE->REG_100H; + HW_SCE_func002(0x8a7b089fU, 0xd21e6af5U, 0x28dce7b2U, 0xb264a678U); + } + HW_SCE_func001(0xfb595513U, 0x993b1bfbU, 0xb229e17fU, 0x7f506d0bU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x010b0644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func003(0xdea4c319U, 0x1870122dU, 0x567cba9dU, 0x24e3e4d0U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb9f.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9i.c new file mode 100644 index 0000000000..9fe098eb91 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9i.c @@ -0,0 +1,232 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000b901U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00070805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0xe2c6c619U, 0xe6583873U, 0x8bec795cU, 0x8b3ed753U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5737b943U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0x0b6f6163U, 0x6a372131U, 0x9cc9fb41U, 0x03f0f273U); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + HW_SCE_func001(0xb3a9613eU, 0xf5926368U, 0x46ef4880U, 0xe69b245aU); + SCE->REG_A4H = 0x40fa063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + HW_SCE_func001(0x0981c6feU, 0xfd6734dfU, 0xa303e9b9U, 0x8da82124U); + SCE->REG_A4H = 0x40fb063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_100H = InData_KeyIndex[21]; + SCE->REG_100H = InData_KeyIndex[22]; + SCE->REG_100H = InData_KeyIndex[23]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x445ad96dU, 0xb3cff680U, 0xfff2d822U, 0xb76b3a88U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0xac230876U, 0x4d9f7fdfU, 0x7d2718bfU, 0xe8ecca0aU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x010b0644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func003(0x05522c3cU, 0x4834f34aU, 0x2b23b2dfU, 0x66fc1ca9U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0004a80dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb9i.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9u.c new file mode 100644 index 0000000000..3467a51263 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pb9u.c @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0x651deaa6U, 0xb808f13aU, 0xf28b2e1bU, 0x90941ffcU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x00008daeU; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + HW_SCE_func206(); + HW_SCE_func002(0x73f0fcbeU, 0x69bf1ccfU, 0xad57d2e1U, 0x66e4e4b5U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pb9u.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2f.c new file mode 100644 index 0000000000..77c000f539 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2f.c @@ -0,0 +1,555 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextBitLen[0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00076821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00026c21U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000d0c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x2000a820U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000cc6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0xce9accb2U, 0xcdcc26e2U, 0xd91fa9edU, 0xab15a636U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x22df0fb7U, 0xc2a78deaU, 0xc78df098U, 0x2fd15e14U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0x1fd615f9U, 0xf33df947U, 0xb9b40855U, 0x36adf76fU); + } + else + { + HW_SCE_func002(0x4dccb1e1U, 0xbd1f45faU, 0xc5c33d20U, 0x400b0df4U); + } + HW_SCE_func001(0xec71656cU, 0xa352f213U, 0xd2c9122aU, 0x46093feaU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x010b0644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func003(0xaaf565b6U, 0xa14023eeU, 0x0a9561e1U, 0x10c72774U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_func001(0x5ae5c7a0U, 0xd1c87403U, 0xf1bb78f0U, 0x4ae3820fU); + SCE->REG_E0H = 0x81010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + HW_SCE_func001(0xa6de294cU, 0x6e2d19e0U, 0xf8f5bd40U, 0x1918fceeU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x0000cdaeU; + SCE->REG_04H = 0x0000c100U; + iLoop = 0; + if(S_RAM[0] >= 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + HW_SCE_func206(); + HW_SCE_func001(0x59ac3e9fU, 0x34ae6ff2U, 0x5ce7e8cdU, 0xb3cd0f1dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_1CH = 0x002d0000U; + HW_SCE_func001(0x95e388c1U, 0x8c85dcebU, 0xe27a815dU, 0x5a60e683U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_00H = 0x00000113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func002(0xf277f06dU, 0x03318561U, 0x1900dfeeU, 0xf2f91da3U); + } + else + { + HW_SCE_func002(0x3e25783cU, 0x8d1906f6U, 0xae010de0U, 0xde84e80dU); + } + HW_SCE_func001(0x2c7d9a60U, 0x1f750dd1U, 0xd01a6b39U, 0x26c7bceaU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x010b0644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func003(0x5007b925U, 0xb5010564U, 0x130075acU, 0x5dd666ffU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38008c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_func001(0x3a5ffb0eU, 0x7107479aU, 0x75504e7cU, 0x351e41bbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0xb7b3056eU, 0xe3c02d5bU, 0x7d96a9ecU, 0xe1f61ea8U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050604U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x0000cd2cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x0000cdadU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80840006U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80840003U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+4 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+5 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+6 + 0]; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+7 + 0]; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0xffffffffU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00004402U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00007484U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000034a0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000368a5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008ca0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002465U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003826U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003843U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c24U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00001484U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c44U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00001041U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c43U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000007fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x1000a440U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002822U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00056821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003846U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c43U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003020U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func002(0xcb48c703U, 0xee2dc584U, 0xe2638516U, 0xb9d2ef96U); + } + HW_SCE_func001(0x721b4e10U, 0xf5d4dc8eU, 0x2083fee8U, 0xc4f55818U); + SCE->REG_ECH = 0x38000c21U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00040644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x0000cdadU; + SCE->REG_E0H = 0x81840003U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000112U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + OutData_Text[iLoop + 1] = SCE->REG_100H; + OutData_Text[iLoop + 2] = SCE->REG_100H; + OutData_Text[iLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003826U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000c24U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c26U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000842U; + SCE->REG_1D0H = 0x00000000U; + for (jLoop = 0; jLoop < (int32_t)S_RAM[0]; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003c46U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00003000U; + SCE->REG_1D0H = 0x00000000U; + HW_SCE_func002(0x470dbb5eU, 0x77fcf121U, 0x82a42003U, 0xf494beccU); + } + HW_SCE_func001(0x0b847bfdU, 0xc4c48c6eU, 0xad20a312U, 0x6e3e81c5U); + SCE->REG_ECH = 0x38000c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x81840006U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+4 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+5 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+6 + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+7 + 0] = SCE->REG_100H; + HW_SCE_func002(0x8da3c818U, 0x56364771U, 0xee0081e9U, 0x3815eb4cU); + } + HW_SCE_func001(0x40750ce0U, 0x171fd58bU, 0x60aac93eU, 0xdabce961U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x010b0644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func003(0x98cfbfeeU, 0x4c6ffa00U, 0x97f1a35fU, 0x24761a97U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pc2f.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2i.c new file mode 100644 index 0000000000..d9a60fc46d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2i.c @@ -0,0 +1,232 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000c201U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000251U; + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x0020363cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x002036bcU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x0021340cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x00070805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x1da03fa7U, 0xee7b2471U, 0x35d6996bU, 0x88d327f2U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x600c3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_A4H = 0x400c0a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5737b943U); + SCE->REG_A4H = 0x42f8063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + HW_SCE_func001(0x570167b9U, 0x56ee8455U, 0x769701b3U, 0xef7bfda2U); + SCE->REG_A4H = 0x40f9063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + HW_SCE_func001(0x8f2e5af0U, 0x883a208aU, 0x4236c1cbU, 0xe1dc5831U); + SCE->REG_A4H = 0x40fa063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + HW_SCE_func001(0x28420221U, 0xcb9471dbU, 0x52476198U, 0x43584bd9U); + SCE->REG_A4H = 0x40fb063dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_A4H = 0x400006bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_100H = InData_KeyIndex[21]; + SCE->REG_100H = InData_KeyIndex[22]; + SCE->REG_100H = InData_KeyIndex[23]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_func001(0x8547eb4eU, 0xd0b2ccc4U, 0x0ce3d227U, 0xf3e5d8d6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_func001(0x014c27a6U, 0xf19098cbU, 0x92029b0fU, 0xd5d99b1eU); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x010b0644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_func003(0xf1ca0383U, 0xd6c2c942U, 0x41b4415fU, 0x3f9246b2U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0004a80dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pc2i.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2u.c new file mode 100644 index 0000000000..a5a0c82d64 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_pc2u.c @@ -0,0 +1,115 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_func001(0xa0abc7cbU, 0xf959aa62U, 0x6e4bfd28U, 0xf5f70337U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x0000cdaeU; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + HW_SCE_func206(); + HW_SCE_func002(0xa0cca9a3U, 0x7c4fc59fU, 0x7303fb1dU, 0xf8a2e023U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_pc2u.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_subprc01.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_subprc01.c new file mode 100644 index 0000000000..795ba09ae3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_subprc01.c @@ -0,0 +1,191 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_SelfCheck1SubSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0xf597806AU; + SCE->REG_10CH = 0x00010001U; + SCE->REG_80H = 0x00000001U; + SCE->REG_A4H = 0x00000008U; + SCE->REG_8CH = 0x00000100U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_14H = 0x10103005U; + SCE->REG_10H = 0x01234567U; + SCE->REG_14H = 0x10103015U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + SCE->REG_138H = 0xf597806AU; + SCE->REG_F0H = 0x00000000U; + SCE->REG_10CH = 0x00010001U; + SCE->REG_80H = 0x00000001U; + SCE->REG_A4H = 0x00000008U; + SCE->REG_8CH = 0x00000102U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_14H = 0x10303005U; + SCE->REG_10H = 0xefa59826U; + SCE->REG_14H = 0x10303015U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + SCE->REG_138H = 0xf597806AU; + SCE->REG_F0H = 0x00000000U; + SCE->REG_10CH = 0x00010001U; + SCE->REG_80H = 0x00000001U; + SCE->REG_A4H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_8CH = 0x00000100U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_78H = 0x00000001U; + SCE->REG_14H = 0x10303005U; + SCE->REG_10H = 0x6159465eU; + SCE->REG_14H = 0x10303015U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + SCE->REG_138H = 0xf597806AU; + SCE->REG_F0H = 0x00000000U; + SCE->REG_10CH = 0x00010001U; + SCE->REG_80H = 0x00000001U; + SCE->REG_A4H = 0x00000008U; + SCE->REG_8CH = 0x00000103U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_68H = 0x00000005U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_78H = 0x00000005U; + SCE->REG_14H = 0x70303005U; + SCE->REG_10H = 0xb785467cU; + SCE->REG_14H = 0x70303015U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + SCE->REG_138H = 0xf597806AU; + SCE->REG_F0H = 0x00000000U; + SCE->REG_10CH = 0x00010001U; + SCE->REG_ECH = 0x00000c00U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x08008802U; + SCE->REG_80H = 0x00000001U; + SCE->REG_A4H = 0x00000008U; + SCE->REG_8CH = 0xfffff1dfU; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_68H = 0x00000005U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_78H = 0x00000005U; + SCE->REG_14H = 0x10300007U; + SCE->REG_10H = 0x9a59a424U; + SCE->REG_14H = 0x10300017U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_subprc01.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_subprc02.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_subprc02.c new file mode 100644 index 0000000000..02b62646ab --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/hw_sce_subprc02.c @@ -0,0 +1,220 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_SelfCheck2SubSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x40083a8cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x63a83a19U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00010804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x00000800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x80880000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00400003U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_A4H = 0xc0200c1eU; + for(iLoop=0; iLoop<1024; iLoop=iLoop+1) + { + SCE->REG_E0H = 0x80010020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00008407U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034c1U; + SCE->REG_1D0H = 0x00000000U; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_ECH = 0x0c016cc6U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x100008c7U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_E0H = 0x810100c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_00H = 0x00001807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + for(jLoop=0; jLoop<8; jLoop=jLoop+1) + { + SCE->REG_ECH = 0x00003441U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00008c40U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000884U; + SCE->REG_1D0H = 0x00000000U; + for(kLoop=0; kLoop<16; kLoop=kLoop+1) + { + SCE->REG_ECH = 0x010038a0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38000844U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x10002ca0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x01003ca0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002403U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c80U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_ECH = 0x00046821U; + SCE->REG_1D0H = 0x00000000U; + } + } + /* WAIT_LOOP */ + while (0U != SCE->REG_A8H_b.B6) + { + /* waiting */ + } + SCE->REG_A4H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1CH = 0x00000400U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000B50U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000800U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_1D0H = 0x00000000U; + for(iLoop=0; iLoop<16; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x010038a0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x30002885U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00005023U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x000024c5U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002c60U; + SCE->REG_1D0H = 0x00000000U; + } + SCE->REG_ECH = 0x380088c0U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00002000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x38008820U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE_Sec_200408/200408/RA4M1/Cryptographic/HW_SCE_subprc02.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/s_flash.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/s_flash.c new file mode 100644 index 0000000000..0f7bddecf6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/primitive/s_flash.c @@ -0,0 +1,107 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : s_flash.c + * Version : 1.09 + * Description : Key information file. + *********************************************************************************************************************/ +/********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.03.2020 1.09 First Release + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "r_sce_if.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global variables + *********************************************************************************************************************/ +uint32_t const S_FLASH[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0x92f41cea, 0x2309b379, 0xb7d5e7b4, 0x0e53336d, + 0xe8cf625a, 0x19e79b10, 0x9dc85a10, 0x4d197093, + 0xbb94e956, 0xe38beca2, 0x9ed529ec, 0xb40e4b25, + 0x7fff4a80, 0x37c2251a, 0x0819a70c, 0x03666eba, + 0x74c55cd1, 0x9a0bc71d, 0x9cdafc90, 0xdef69ba5, + 0xb5431194, 0x006473e9, 0xb1acfd4a, 0xfd7dc888, + 0xb9cdc199, 0x32bd21b0, 0x6dd06b62, 0x88a15abb, + 0x5f9e4d6d, 0xa680b579, 0x702a5be7, 0x7f05e917, + 0x67902610, 0x5ddd6b35, 0xba3443c1, 0x5daa8d40, + 0xbecae6a6, 0x62584c47, 0x89a99ac7, 0x4d76f91a, + 0x313af776, 0x91e9d697, 0x57af6a0a, 0xd4c7e3e7, + 0xd09c715f, 0x22e3f7f0, 0x7cac0867, 0xdf8bd4d9, + 0x04e246b3, 0x1d50adaa, 0xd7404f94, 0x60fd642f, + 0xc8f3b8a4, 0x0cc8d4ef, 0x8c81684b, 0x4480724a, + 0x5569ded3, 0x322b8e85, 0x6187bfc5, 0x47166c34, + 0x1b9cfd57, 0xa092fbf0, 0x7b152f0e, 0x187731c0, + 0x819460ae, 0xb195c4d5, 0xc89dce93, 0xb1f082c2, + 0xebe23482, 0xf7ba9c09, 0x0ed87573, 0x629450be, + 0x2679d43f, 0xeffad241, 0xb2a2f72a, 0x79f04a49, + 0x2ec41794, 0xaa2de611, 0x56019ccb, 0x9d05fefe, + 0x626a52aa, 0x65051b73, 0x3ff7b5b8, 0x4258f3b1, + 0xb2a6abac, 0xc766eedb, 0x685deafc, 0xe32e8e7f, + 0xe4cab55d, 0x266ada78, 0x596f5930, 0x06c09e9e, + 0x81a822b1, 0xe93f12b9, 0x7b0f6ad9, 0x26cea2f4, + 0x23b058e7, 0x8117b8d9, 0xa64088d0, 0xe07fd1fb, + 0x21024258, 0xb59ba1a2, 0xf6c40124, 0x8c74e284, + 0x2309cf83, 0xe2a0cb8b, 0xaf024e64, 0x796e29ed, + 0xe48c48a9, 0x67e9630b, 0x47cf8506, 0x54879af5, + 0xebb7e35b, 0xd16f2922, 0x810768ec, 0x96c94bf3, + 0xf82acd5e, 0x3e0e9a66, 0xdd76d024, 0x6b931381, + 0xe8f1075e, 0x602a4438, 0x37328b5b, 0x45d2343b, + 0x5ccab479, 0x9940f6c0, 0xe4b10d54, 0x8c508659, +#else /* Big endian */ + 0xea1cf492, 0x79b30923, 0xb4e7d5b7, 0x6d33530e, + 0x5a62cfe8, 0x109be719, 0x105ac89d, 0x9370194d, + 0x56e994bb, 0xa2ec8be3, 0xec29d59e, 0x254b0eb4, + 0x804aff7f, 0x1a25c237, 0x0ca71908, 0xba6e6603, + 0xd15cc574, 0x1dc70b9a, 0x90fcda9c, 0xa59bf6de, + 0x941143b5, 0xe9736400, 0x4afdacb1, 0x88c87dfd, + 0x99c1cdb9, 0xb021bd32, 0x626bd06d, 0xbb5aa188, + 0x6d4d9e5f, 0x79b580a6, 0xe75b2a70, 0x17e9057f, + 0x10269067, 0x356bdd5d, 0xc14334ba, 0x408daa5d, + 0xa6e6cabe, 0x474c5862, 0xc79aa989, 0x1af9764d, + 0x76f73a31, 0x97d6e991, 0x0a6aaf57, 0xe7e3c7d4, + 0x5f719cd0, 0xf0f7e322, 0x6708ac7c, 0xd9d48bdf, + 0xb346e204, 0xaaad501d, 0x944f40d7, 0x2f64fd60, + 0xa4b8f3c8, 0xefd4c80c, 0x4b68818c, 0x4a728044, + 0xd3de6955, 0x858e2b32, 0xc5bf8761, 0x346c1647, + 0x57fd9c1b, 0xf0fb92a0, 0x0e2f157b, 0xc0317718, + 0xae609481, 0xd5c495b1, 0x93ce9dc8, 0xc282f0b1, + 0x8234e2eb, 0x099cbaf7, 0x7375d80e, 0xbe509462, + 0x3fd47926, 0x41d2faef, 0x2af7a2b2, 0x494af079, + 0x9417c42e, 0x11e62daa, 0xcb9c0156, 0xfefe059d, + 0xaa526a62, 0x731b0565, 0xb8b5f73f, 0xb1f35842, + 0xacaba6b2, 0xdbee66c7, 0xfcea5d68, 0x7f8e2ee3, + 0x5db5cae4, 0x78da6a26, 0x30596f59, 0x9e9ec006, + 0xb122a881, 0xb9123fe9, 0xd96a0f7b, 0xf4a2ce26, + 0xe758b023, 0xd9b81781, 0xd08840a6, 0xfbd17fe0, + 0x58420221, 0xa2a19bb5, 0x2401c4f6, 0x84e2748c, + 0x83cf0923, 0x8bcba0e2, 0x644e02af, 0xed296e79, + 0xa9488ce4, 0x0b63e967, 0x0685cf47, 0xf59a8754, + 0x5be3b7eb, 0x22296fd1, 0xec680781, 0xf34bc996, + 0x5ecd2af8, 0x669a0e3e, 0x24d076dd, 0x8113936b, + 0x5e07f1e8, 0x38442a60, 0x5b8b3237, 0x3b34d245, + 0x79b4ca5c, 0xc0f64099, 0x540db1e4, 0x5986508c, +#endif /* defined __ARMEB__ */ +}; + +/********************************************************************************************************************** + Private (static) variables and functions + *********************************************************************************************************************/ + diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/SCE_module.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/SCE_module.h new file mode 100644 index 0000000000..76fc6c4769 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/SCE_module.h @@ -0,0 +1,16 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define SCE_BASE 0x400C0000UL + +#endif // HW_SCE_MODULE_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h new file mode 100644 index 0000000000..1f89db5b63 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h @@ -0,0 +1,393 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : hw_sce_ra_private.h + * Version : 1.09 + * Description : SCE function private header file. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "r_sce_if.h" +#include "SCE_ProcCommon.h" + +#ifndef HW_SCE_RA_PRIVATE_HEADER_FILE +#define HW_SCE_RA_PRIVATE_HEADER_FILE + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +#if SCE_SECURE_BOOT != 0 +/* Required for each variable definition with no initial value to be placed in the SECURE_BOOT section. */ +#define SCE_PRV_SEC_B_SECURE_BOOT R_BSP_ATTRIB_SECTION_CHANGE(B, SECURE_BOOT, 4) +/* Required for each function definition to be placed in the SECURE_BOOT section. */ +#define SCE_PRV_SEC_P_SECURE_BOOT R_BSP_ATTRIB_SECTION_CHANGE(P, SECURE_BOOT) +/* Revert to default section. */ +#define SCE_PRV_SEC_DEFAULT R_BSP_ATTRIB_SECTION_CHANGE_END +#else +/* Required for each variable definition with no initial value to be placed in the SECURE_BOOT section.(dummy) */ +#define SCE_PRV_SEC_B_SECURE_BOOT +/* Required for each function definition to be placed in the SECURE_BOOT section.(dummy) */ +#define SCE_PRV_SEC_P_SECURE_BOOT +/* Revert to default section.(dummy) */ +#define SCE_PRV_SEC_DEFAULT +#endif /* SCE_SECURE_BOOT != 0 */ + + #define SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED (384) + #define SIZE_AES_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED (544) /* Added 32 bits here to differentiate 192 wrapped key from 256 wrapped key in the psa_crypto stack. */ + #define SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_192BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED (512) + #define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED (512) + #define SIZE_AES_XTS_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED (768) + #define SIZE_AES_XTS_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 32) + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ +extern uint32_t const S_FLASH[]; + +extern uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +extern uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +extern uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +extern uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +extern SCE_GEN_MAC_CB_FUNC_T SCE_GEN_MAC_CB_FUNC; + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ +/* --------------------- SCE driver wrapper layer ---------------------- */ + +fsp_err_t HW_SCE_Aes128EcbEncryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128EcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EcbEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes128EcbDecryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128EcbDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EcbDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes128CbcEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128CbcEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CbcEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes128CbcDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128CbcDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CbcDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); + +fsp_err_t HW_SCE_Aes256EcbEncryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256EcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EcbEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes256EcbDecryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256EcbDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EcbDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes256CbcEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256CbcEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CbcEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes256CbcDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256CbcDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CbcDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); + +fsp_err_t HW_SCE_Aes128GcmEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128GcmEncryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128GcmEncryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes128GcmDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128GcmDecryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128GcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256GcmEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256GcmEncryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256GcmEncryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes256GcmDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256GcmDecryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256GcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); +void HW_SCE_AesGcmEncryptUpdateTransitionPrivate(void); +void HW_SCE_AesGcmDecryptUpdateTransitionPrivate(void); + +fsp_err_t HW_SCE_Aes128CcmEncryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes128CcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmEncryptFinalPrivate(const uint32_t *InData_TextLen, const uint32_t *InData_Text, + uint32_t *OutData_Text, uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes128CcmDecryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes128CcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmDecryptFinalPrivate(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_MAC, + const uint32_t *InData_MACLength, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256CcmEncryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmEncryptFinalPrivate(uint32_t *InData_TextLen, uint32_t *InData_Text, + uint32_t *OutData_Text, uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes256CcmDecryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, + uint32_t *InData_MACLength, uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Aes128CmacGenerateInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128CmacGenerateUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, + uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes128CmacVerifyInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128CmacVerifyUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CmacVerifyFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen); + +fsp_err_t HW_SCE_Aes256CmacGenerateInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256CmacGenerateUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, + uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes256CmacVerifyInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256CmacVerifyUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CmacVerifyFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen); + +void HW_SCE_Aes192CcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, uint32_t *OutData_Text, + uint32_t *OutData_MAC); +void HW_SCE_Aes192CcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_MAC, + const uint32_t *InData_MACLength, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], uint32_t InData_DataType[], + uint32_t InData_Cmd[], uint32_t InData_TextLen[], uint32_t InData_KeyIndex[], uint32_t InData_IV[], + uint32_t InData_Header[], uint32_t InData_SeqNum[], uint32_t Header_Len); +fsp_err_t HW_SCE_Aes192CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], uint32_t InData_DataType[], + uint32_t InData_Cmd[],uint32_t InData_TextLen[], uint32_t InData_KeyIndex[],uint32_t InData_IV[], + uint32_t InData_Header[], uint32_t InData_SeqNum[],uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmEncryptInitSubGeneral (uint32_t InData_KeyType[], uint32_t InData_DataType[], + uint32_t InData_Cmd[],uint32_t InData_TextLen[], uint32_t InData_KeyIndex[],uint32_t InData_IV[], + uint32_t InData_Header[], uint32_t InData_SeqNum[],uint32_t Header_Len); +fsp_err_t HW_SCE_Aes128CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], uint32_t InData_DataType[], + uint32_t InData_Cmd[], uint32_t InData_TextLen[], uint32_t InData_MACLength[], uint32_t InData_KeyIndex[], + uint32_t InData_IV[], uint32_t InData_Header[], uint32_t InData_SeqNum[], uint32_t Header_Len); +fsp_err_t HW_SCE_Aes192CcmDecryptInitSubGeneral (uint32_t InData_KeyType[], uint32_t InData_DataType[], + uint32_t InData_Cmd[], uint32_t InData_TextLen[], uint32_t InData_MACLength[], uint32_t InData_KeyIndex[], + uint32_t InData_IV[], uint32_t InData_Header[], uint32_t InData_SeqNum[], uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmDecryptInitSubGeneral (uint32_t InData_KeyType[],uint32_t InData_DataType[], + uint32_t InData_Cmd[],uint32_t InData_TextLen[],uint32_t InData_MACLength[],uint32_t InData_KeyIndex[], + uint32_t InData_IV[],uint32_t InData_Header[],uint32_t InData_SeqNum[],uint32_t Header_Len); +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSubGeneral (const uint32_t *InData_Text, const uint32_t *InData_TextLen, + uint32_t *OutData_Text, uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSubGeneral(const uint32_t *InData_Text, const uint32_t *InData_TextLen, + const uint32_t *InData_MAC, const uint32_t *InData_MACLength, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSubGeneral (uint32_t *InData_KeyType, uint32_t *InData_DataType, + uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_SeqNum); +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +void HW_SCE_Aes192EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void); +/* --------------------- SCE control procedure related ---------------------- */ + +void HW_SCE_SoftwareResetSub(void); +fsp_err_t HW_SCE_SelfCheck1Sub(void); +fsp_err_t HW_SCE_SelfCheck2Sub(void); + +fsp_err_t HW_SCE_GenerateAes128KeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes256KeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes128PlainKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes256PlainKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes128XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, + uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes256XtsKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, + uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text); +fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData); +fsp_err_t HW_SCE_GenerateUpdatePlainKeyRingKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData); + +fsp_err_t HW_SCE_UpdateAes128KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateAes256KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); + +fsp_err_t HW_SCE_StartUpdateFirmwareSub(void); +fsp_err_t HW_SCE_GenerateFirmwareMacSub(uint32_t *InData_KeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_UpProgram, uint32_t *InData_IV, uint32_t *OutData_Program, uint32_t MAX_CNT/*, + sce_firmware_generate_mac_resume_handle_t *sce_firmware_generate_mac_resume_handle*/); +fsp_err_t HW_SCE_VerifyFirmwareMacSub(uint32_t *InData_Program, uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t *InData_KeyType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_Key[], const uint32_t InData_IV[]); +void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t *InData_KeyType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +void HW_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void); + +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes128XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes128XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes256XtsEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes256XtsDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(uint32_t *InData_TextBitLen, uint32_t *InData_Text, uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Ghash(uint32_t *InData_HV, uint32_t *InData_IV, uint32_t *InData_Text, uint32_t *OutData_DataT, + uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes128GcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, + const uint32_t *InData_DataALen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes128GcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_DataALen, + const uint32_t *InData_DataT, const uint32_t *InData_DataTLen, uint32_t *OutData_Text); +void HW_SCE_AesGcmEncryptDecryptUpdateTransitionSub(void); +void HW_SCE_Aes128GcmEncryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT); +void HW_SCE_Aes128GcmDecryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes256GcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, + const uint32_t *InData_DataALen,uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes256GcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_DataALen, + const uint32_t *InData_DataT, const uint32_t *InData_DataTLen, uint32_t *OutData_Text); +void HW_SCE_Aes256GcmEncryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT); +void HW_SCE_Aes256GcmDecryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes192GcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, + const uint32_t *InData_DataALen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes192GcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_DataALen, + const uint32_t *InData_DataT, const uint32_t *InData_DataTLen, uint32_t *OutData_Text); +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes192GcmEncryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT); +void HW_SCE_Aes192GcmDecryptUpdateAADSub(const uint32_t *InData_DataA, const uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes128CcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub(const uint32_t *InData_TextLen, const uint32_t *InData_Text, uint32_t *OutData_Text, + uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes128CcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_MAC, + const uint32_t *InData_MACLength, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes256CcmEncryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, uint32_t *OutData_Text, + uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes256CcmDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(const uint32_t *InData_Text, const uint32_t *InData_TextLen, const uint32_t *InData_MAC, + const uint32_t *InData_MACLength, uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyIndex); +void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes256CmacInitSub(uint32_t *InData_KeyIndex); +void HW_SCE_Aes256CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_GhashSub (uint32_t *InData_HV, uint32_t *InData_IV, uint32_t *InData_Text, uint32_t *OutData_DataT, + uint32_t MAX_CNT); +void HW_SCE_SelfCheck1SubSub(void); +void HW_SCE_SelfCheck2SubSub(void); + +void HW_SCE_func001(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_func002(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_func003(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_func205(void); +void HW_SCE_func206(void); +void HW_SCE_func207(void); + +void firm_mac_read(uint32_t *InData_Program); + +uint32_t change_endian_long(uint32_t data); + +fsp_err_t HW_SCE_Aes128CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +fsp_err_t HW_SCE_Aes192CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +fsp_err_t HW_SCE_Aes256CmacInit(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +void HW_SCE_Aes128CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes192CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes256CmacUpdate(const uint32_t InData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes192CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes256CmacFinal(const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes128XtsEncryptInitSubGeneral (uint32_t InData_KeyMode[], + uint32_t InData_KeyIndex[], + uint32_t InData_Key[], + uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes128XtsDecryptInitSubGeneral (uint32_t InData_KeyMode[], + uint32_t InData_KeyIndex[], + uint32_t InData_Key[], + uint32_t InData_IV[]); +#endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h new file mode 100644 index 0000000000..5140c951b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h @@ -0,0 +1,1168 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_sce_if.h + * Version : 1.10 + * Description : Interface definition for the r_sce module. + * TSIP means the "Trusted Secure IP" that is Renesas original security IP. + * Strong point 1: + * TSIP can hide the "Critical Security Parameter (CSP)" inside the "Cryptographic Boundary". + * These words are defined in NIST FIPS140-2. + * Strong point 2: + * TSIP can support AES, SHA, DES, RSA, ECC, Key Wrap, TRNG(with DRBG), + * already certified NIST CAVP test. + * TSIP-Lite can support AES, TRNG(with DRBG), already certified NIST CAVP test. + * Strong point 3: + * TSIP can accelerate some crypto operation. + * Supported Device: + * TSIP = RX651, RX65N, RX66N, RX72M, RX72N + * TSIP-Lite = RX231, RX23W, RX66T, RX72T + *********************************************************************************************************************/ +/********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 27.06.2015 1.00 First Release + * : 15.05.2017 1.01 Add AES-CMAC + * : 30.09.2017 1.03 Add Init/Update/Final API and SHA, RSA + * : 28.02.2018 1.04 Change Init/Update/Final API for RX231, add TLS function and + * : return values change FIT rules. + * : 30.04.2018 1.05 Add TDES, MD5 and RSAES-PKCS1-v1_5 API + * : 28.09.2018 1.06 Add RSA Key Generation, AES, TDES, RSA Key update features, RX66T support + * : 28.12.2018 1.07 Add RX72T support + * : 30.09.2019 1.08 Added support for GCC and IAR compiler, ECC API, RX23W and RX72M + * : 31.03.2020 1.09 Added support for AES-CCM, HMAC key generation, ECDH, Key Wrap API, RX66N and RX72N + * : 30.06.2020 1.10 Added support for ARC4, ECC(P-384) API + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +// added for RA4M1 start +//#include "platform.h" +#include "bsp_api.h" +// added for RA4M1 end + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ + +#ifndef R_SCE_IF_HEADER_FILE +#define R_SCE_IF_HEADER_FILE + + +// added for RA4M1 start +#if 0 +// added for RA4M1 end + +#if R_BSP_VERSION_MAJOR < 5 +#error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif +#if (defined BSP_MCU_RX231 || defined BSP_MCU_RX23W) && (BSP_CFG_MCU_PART_VERSION == 0xB) /* B */ +#elif (defined BSP_MCU_RX66T || defined BSP_MCU_RX72T) && ((BSP_CFG_MCU_PART_FUNCTION == 0xE /* E */) || \ + (BSP_CFG_MCU_PART_FUNCTION == 0xF /* F */) || (BSP_CFG_MCU_PART_FUNCTION == 0x10 /* G */)) +#elif (defined BSP_MCU_RX65N || defined BSP_MCU_RX651) && (BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED == true) +#elif (defined BSP_MCU_RX72M || defined BSP_MCU_RX72N || defined BSP_MCU_RX66N) && \ + (BSP_CFG_MCU_PART_FUNCTION == 0x11 /* H */) +#else +#error "Your MCU does not support SCE functions. Please confirm BSP_MCU_xxx macro in r_bsp_config.h." +#endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W && BSP_CFG_MCU_PART_VERSION == 0xB */ + +// added for RA4M1 start +#endif +// added for RA4M1 end + +/* Version Number of API. */ +#define SCE_VERSION_MAJOR (1U) +#define SCE_VERSION_MINOR (10U) + +/* Various information. */ +#define HW_SCE_SRAM_WORD_SIZE (32U) +#define HW_SCE_SINST_WORD_SIZE (140U) +#define HW_SCE_SINST2_WORD_SIZE (16U) +#define HW_SCE_SHEAP_WORD_SIZE (1504U) +#define HW_SCE_MAC_SIZE (16U) + +/* For AES operation. */ +#define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (12U) +#define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_AES128_KEY_WORD_SIZE (4U) +#define HW_SCE_AES256_KEY_WORD_SIZE (8U) +#define HW_SCE_AES128_KEY_BYTE_SIZE (16U) +#define HW_SCE_AES256_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_BLOCK_BIT_SIZE (128U) +#define HW_SCE_AES_CBC_IV_BYTE_SIZE (16U) +#define HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE (16U) +#define HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE (128U) +#define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) +#define HW_SCE_KEYWRAP_AES128 (0U) +#define HW_SCE_KEYWRAP_AES256 (2U) +#define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) +#define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) +#define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) + +/* For TDES operation. */ +#define HW_SCE_TDES_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_TDES_KEY_WORD_SIZE (8U) +#define HW_SCE_TDES_KEY_BYTE_SIZE (32U) +#define HW_SCE_TDES_BLOCK_BYTE_SIZE (8U) +#define HW_SCE_TDES_CBC_IV_BYTE_SIZE (8U) + +/* For ARC4 operation. */ +#define HW_SCE_ARC4_KEY_INDEX_WORD_SIZE (72U) +#define HW_SCE_ARC4_KEY_WORD_SIZE (64U) +#define HW_SCE_ARC4_KEY_BYTE_SIZE (256U) +#define HW_SCE_ARC4_BLOCK_BYTE_SIZE (16U) + +/* For SHA operation. */ +#define HW_SCE_SHA1_HASH_LENGTH_BYTE_SIZE (20U) +#define HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE (32U) +#define HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE (48U) +#define HW_SCE_SHA256_HASH_STATE_BUFFER_SIZE (8U) + +/* For MD5 operation. */ +#define HW_SCE_MD5_HASH_LENGTH_BYTE_SIZE (16U) + +/* For HMAC operation. */ +#define HW_SCE_HMAC_KEY_INDEX_BYTE_SIZE (64U) +#define HW_SCE_HMAC_KEY_INDEX_WORD_SIZE (16U) + +/* For RSA operation. */ +#define HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_1024_KEY_D_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_2048_KEY_D_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_3072_KEY_D_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_4096_KEY_D_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (36U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (19U) +#define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (19U) +#define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE (12U) +#define HW_SCE_RSA1024_NE_KEY_BYTE_SIZE (144U) +#define HW_SCE_RSA1024_ND_KEY_BYTE_SIZE (256U) +#define HW_SCE_RSA2048_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_RSA2048_ND_KEY_BYTE_SIZE (512U) +#define HW_SCE_RSA3072_NE_KEY_BYTE_SIZE (96 * 4 + 16U) +#define HW_SCE_RSA3072_ND_KEY_BYTE_SIZE (192 * 4U) +#define HW_SCE_RSA4096_NE_KEY_BYTE_SIZE (128 * 4 + 16U) +#define HW_SCE_RSA4096_ND_KEY_BYTE_SIZE (256 * 4U) +#define HW_SCE_RSA1024_NE_KEY_INDEX_WORD_SIZE (73U) +#define HW_SCE_RSA1024_ND_KEY_INDEX_WORD_SIZE (101U) +#define HW_SCE_RSA2048_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA2048_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA3072_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA3072_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA4096_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA4096_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA1024_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (76U) +#define HW_SCE_RSA1024_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (104U) +#define HW_SCE_RSA2048_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +#define HW_SCE_RSA2048_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +//#define HW_SCE_RSA3072_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +//#define HW_SCE_RSA3072_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +//#define HW_SCE_RSA4096_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +//#define HW_SCE_RSA4096_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +#define HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE (11U) +#define HW_SCE_RSA_1024_DATA_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_DATA_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_DATA_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_DATA_BYTE_SIZE (128 * 4U) + +/* RSA HASH type. */ +#define HW_SCE_RSA_HASH_MD5 (0x00) /* MD5 */ +#define HW_SCE_RSA_HASH_SHA1 (0x01) /* SHA-1 */ +#define HW_SCE_RSA_HASH_SHA256 (0x02) /* SHA-256 */ + +/* For ECC operation. */ +#define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (112U) +#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE (4U) +#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (20U) +#define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) +#define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) +#define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) +#define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) +#define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) +#define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) +#define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_ALGORITHM_ID_ENCODED_DATA_BYTE_SIZE (7U) + +/* For TLS. */ +#define HW_SCE_TLS_RSA_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_TLS_RSA_NE_KEY_INDEX_WORD_SIZE (140U) +#define HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE (140U) +#define HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_EPHEMERAL_ECDH_PUBLIC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_MASTER_SECRET_WORD_SIZE (20U) +#define HW_SCE_TLS_GENERATE_MAC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_GENERATE_AES128_CRYPTO_KEY_WORD_SIZE (12U) +#define HW_SCE_TLS_GENERATE_AES256_CRYPTO_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_GENERATE_VERIFY_DATA_BYTE_SIZE (12U) +#define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA (0U) +#define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA (1U) +#define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 (2U) +#define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA256 (3U) +#define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (4U) +#define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (5U) +#define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (6U) +#define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (7U) +#define HW_SCE_TLS_GENERATE_CLIENT_VERIFY (0U) +#define HW_SCE_TLS_GENERATE_SERVER_VERIFY (1U) +#define HW_SCE_TLS_PUBLIC_KEY_TYPE_RSA2048 (0U) +#define HW_SCE_TLS_PUBLIC_KEY_TYPE_ECDSA_P256 (2U) + +/* TLS-HMAC. */ +#define HW_SCE_TLS_HMAC_KEY_INDEX_BYTE_SIZE (64U) +#define HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE (16U) + +/* TLS-AES. */ +#define HW_SCE_TLS_AES128_KEY_INDEX_WORD_SIZE (12U) +#define HW_SCE_TLS_AES256_KEY_INDEX_WORD_SIZE (16U) + +/* Key update. */ +#define HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE (16U) + +/* Firmware update. */ +#define HW_SCE_FIRMWARE_MAC_BYTE_SIZE (16U) +#if defined BSP_MCU_RX231 || defined BSP_MCU_RX23W +#define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF8000) +#else +#define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF0000) +#endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W */ + +#define SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0) +#define SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD (8) +#define SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD (20) + +#define SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD (40) +#define SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD (68) +#define SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD (72) +#define SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132) +#define SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD (104) +#define SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD (196) +#define SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD (136) +#define SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD (260) + +#define SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD (36) +#define SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD (12) + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ + +/* request type for Callback of firmware update */ +typedef enum +{ + SCE_FW_CB_REQ_PRG_WT = 0U, + SCE_FW_CB_REQ_PRG_RD, + SCE_FW_CB_REQ_BUFF_CNT, + SCE_FW_CB_REQ_PRG_WT_LAST_BLK, + SCE_FW_CB_REQ_GET_UPDATE_PRG_CHKSUM, + SCE_FW_CB_REQ_STORE_MAC, +} SCE_FW_CB_REQ_TYPE; + +/* key index type */ +typedef enum +{ + SCE_KEY_INDEX_TYPE_INVALID = 0U, + SCE_KEY_INDEX_TYPE_AES128, + SCE_KEY_INDEX_TYPE_AES256, + SCE_KEY_INDEX_TYPE_TDES, + SCE_KEY_INDEX_TYPE_ARC4, + SCE_KEY_INDEX_TYPE_HMAC_SHA1, + SCE_KEY_INDEX_TYPE_HMAC_SHA256, + SCE_KEY_INDEX_TYPE_RSA1024_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA1024_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA2048_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA2048_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA3072_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA3072_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA4096_PRIVATE, + SCE_KEY_INDEX_TYPE_AES128_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES192_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES256_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS, + SCE_KEY_INDEX_TYPE_UPDATE_KEY_RING, + SCE_KEY_INDEX_TYPE_TLS_CA_CERTIFICATION_PUBLIC_KEY, + SCE_KEY_INDEX_TYPE_TLS_P256_ECC_KEY, + SCE_KEY_INDEX_TYPE_ECC_P192_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P224_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P192_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECDH_SHARED_SECRET, + SCE_KEY_INDEX_TYPE_AES128_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES256_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_KEY_WRAP_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_GCM_WITH_IV +} SCE_KEY_INDEX_TYPE; + +// added for RA6M4 start +/* LIFE CYCLE */ +typedef enum +{ + SCE_CM1 = 0, + SCE_CM2, + SCE_SSD, + SCE_NSECSD, + SCE_DPL, + SCE_LCK_DBG, + SCE_LCK_BOOT, + SCE_RMA_REQ, + SCE_RMA_ACK, +} lifecycle_t; + +/* OEM Command */ +typedef enum +{ + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES192, + SCE_OEM_CMD_AES256, + SCE_OEM_CMD_AES128_XTS, + SCE_OEM_CMD_AES256_XTS, + SCE_OEM_CMD_RSA1024_PUBLIC, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA224, + SCE_OEM_CMD_HMAC_SHA256, + SCE_OEM_CMD_ECC_P256R1_PUBLIC, + SCE_OEM_CMD_ECC_P256R1_PRIVATE, + SCE_OEM_CMD_ECC_P384R1_PUBLIC, + SCE_OEM_CMD_ECC_P384R1_PRIVATE, + SCE_OEM_CMD_ECC_P512R1_PUBLIC, + SCE_OEM_CMD_ECC_P512R1_PRIVATE, + SCE_OEM_CMD_ECC_SECP256K1_PUBLIC, + SCE_OEM_CMD_ECC_SECP256K1_PRIVATE, + SCE_OEM_CMD_NUM +} sce_oem_cmd_t; +// added for RA6M4 end + +typedef enum e_sce_hash_type +{ + SCE_OEM_CMD_HASH_TYPE_SHA1 = 0, + SCE_OEM_CMD_HASH_TYPE_SHA224 = 1, + SCE_OEM_CMD_HASH_TYPE_SHA256 = 2, + SCE_OEM_CMD_HASH_TYPE_SHA512_224 = 3, + SCE_OEM_CMD_HASH_TYPE_SHA512_256 = 4, + SCE_OEM_CMD_HASH_TYPE_SHA384 = 5, + SCE_OEM_CMD_HASH_TYPE_SHA512 = 6 +} sce_hash_type_t; + +typedef enum e_sce_hash_cmd +{ + SCE_OEM_CMD_HASH_ONESHOT = 0, + SCE_OEM_CMD_HASH_INIT_TO_SUSPEND = 1, + SCE_OEM_CMD_HASH_RESUME_TO_SUSPEND = 2, + SCE_OEM_CMD_HASH_RESUME_TO_FINAL = 3 +} sce_hash_cmd_t; + +typedef struct sce_hash_user_ctx +{ + uint32_t hash_data_state[HW_SCE_SHA256_HASH_STATE_BUFFER_SIZE]; + sce_hash_cmd_t operation_cmd; +}sce_hash_user_ctx_t; + +typedef enum e_sce_oem_key_type +{ + SCE_OEM_KEY_TYPE_ENCRYPTED = 0, + SCE_OEM_KEY_TYPE_PLAIN = 1 +} sce_oem_key_type_t; + +/* Byte data structure */ +typedef struct sce_byte_data +{ + uint8_t *pdata; + uint32_t data_length; + uint32_t data_type; +} sce_byte_data_t; + +/* RSA byte data structure */ +typedef sce_byte_data_t sce_rsa_byte_data_t; + +/* ECDSA byte data structure */ +typedef sce_byte_data_t sce_ecdsa_byte_data_t; + +/* AES key index data structure */ +typedef struct sce_aes_key_index +{ + uint32_t type; + /* AES128, AES256, AES128 for TLS, AES256 for TLS are supported */ + uint32_t value[HW_SCE_TLS_AES256_KEY_INDEX_WORD_SIZE]; +} sce_aes_key_index_t; + +/* TDES key index data structure */ +typedef struct sce_tdes_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TDES_KEY_INDEX_WORD_SIZE]; /* DES/TDES are supported */ +} sce_tdes_key_index_t; + +/* ARC4 key index data structure */ +typedef struct sce_arc4_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_ARC4_KEY_INDEX_WORD_SIZE]; /* ARC4 are supported */ +} sce_arc4_key_index_t; + +/* HMAC-SHA key index data structure */ +typedef struct sce_hmac_sha_key_index +{ + uint32_t type; + /* HMAC-SHA1, HMAC-SHA256, HMAC-SHA for TLS, HMAC-SHA256 for TLS are supported */ + uint32_t value[HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE]; +} sce_hmac_sha_key_index_t; + +/* RSA 1024bit public key index data structure */ +typedef struct sce_rsa1024_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa1024_public_key_index_t; + +/* RSA 1024bit private key index data structure */ +typedef struct sce_rsa1024_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa1024_private_key_index_t; + +/* RSA 2048bit public key index data structure */ +typedef struct sce_rsa2048_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa2048_public_key_index_t; + +/* RSA 2048bit private key index data structure */ +typedef struct sce_rsa2048_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa2048_private_key_index_t; + +/* RSA 3072bit public key index data structure */ +typedef struct sce_rsa3072_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa3072_public_key_index_t; + +/* RSA 3072bit private key index data structure */ +typedef struct sce_rsa3072_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa3072_private_key_index_t; + +/* RSA 4096bit public key index data structure */ +typedef struct sce_rsa4096_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa4096_public_key_index_t; + +/* RSA 4096bit private key index data structure */ +typedef struct sce_rsa4096_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa4096_private_key_index_t; + +/* RSA 1024bit key index pair structure */ +typedef struct sce_rsa1024_key_pair_index +{ + sce_rsa1024_private_key_index_t priv_key; + sce_rsa1024_public_key_index_t pub_key; +} sce_rsa1024_key_pair_index_t; + +/* RSA 2048bit key index pair structure */ +typedef struct sce_rsa2048_key_pair_index +{ + sce_rsa2048_private_key_index_t priv_key; + sce_rsa2048_public_key_index_t pub_key; +} sce_rsa2048_key_pair_index_t; + +/* RSA 3072bit key index pair structure */ +typedef struct sce_rsa3072_key_pair_index +{ + sce_rsa3072_private_key_index_t priv_key; + sce_rsa3072_public_key_index_t pub_key; +} sce_rsa3072_key_pair_index_t; + +/* RSA 4096bit key index pair structure */ +typedef struct sce_rsa4096_key_pair_index +{ + sce_rsa4096_private_key_index_t priv_key; + sce_rsa4096_public_key_index_t pub_key; +} sce_rsa4096_key_pair_index_t; + +/* ECC P-192/224/256 public key index data structure */ +typedef struct sce_ecc_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE]; + uint8_t key_q[HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE]; + } + value; +} sce_ecc_public_key_index_t; + +/* ECC private key index data structure */ +typedef struct sce_ecc_private_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE]; +} sce_ecc_private_key_index_t; + +/* ECC key index pair structure */ +typedef struct sce_ecc_key_pair_index +{ + sce_ecc_private_key_index_t priv_key; + sce_ecc_public_key_index_t pub_key; +} sce_ecc_key_pair_index_t; + +/* ECDH key index data structure */ +typedef struct sce_ecdh_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE]; +} sce_ecdh_key_index_t; + +/* TLS CA certification public key index data structure */ +typedef struct sce_tls_ca_certification_public_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE]; +} sce_tls_ca_certification_public_key_index_t; + +/* TLS P-256 ECC key index data structure */ +typedef struct sce_tls_p256_ecc_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE]; +} sce_tls_p256_ecc_key_index_t; + +/* Update key ring index data structure */ +typedef struct sce_update_key_ring +{ + uint32_t type; + uint32_t value[HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE]; +} sce_update_key_ring_t; + + +/* The work area for AES */ +typedef struct sce_aes_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t last_2_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; + uint8_t current_ivec[HW_SCE_AES_CBC_IV_BYTE_SIZE]; + uint8_t current_icounter[HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_aes_handle_t; + +/* The work area for TDES */ +typedef struct sce_tdes_handle +{ + uint32_t id; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_TDES_BLOCK_BYTE_SIZE]; + uint8_t current_ivec[HW_SCE_TDES_CBC_IV_BYTE_SIZE*2]; + uint8_t flag_call_init; +} sce_tdes_handle_t; + +/* The work area for ARC4 */ +typedef struct sce_arc4_handle +{ + uint32_t id; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_ARC4_BLOCK_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_arc4_handle_t; + +/* The work area for MD5 */ +typedef struct sce_sha_md5_handle +{ + uint32_t id; + uint8_t sha_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; + uint32_t all_received_length; + uint32_t buffering_length; + /* SHA1(20byte), SHA256(32byte), MD5(16byte) are supported */ + uint8_t current_hash[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_sha_md5_handle_t; + +/* The work area for HMAC-SHA */ +typedef struct sce_hmac_sha_handle +{ + uint32_t id; + sce_hmac_sha_key_index_t key_index; + uint8_t hmac_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_hmac_sha_handle_t; + +/* The work area for CMAC */ +typedef struct sce_cmac_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t cmac_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_cmac_handle_t; + +/* The work area for GCM */ +typedef struct sce_gcm_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t gcm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t gcm_aad_buffer[HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t all_received_aad_length; + uint32_t buffering_length; + uint32_t buffering_aad_length; + uint8_t flag_call_init; + uint8_t flag_update_input_data; +} sce_gcm_handle_t; + +/* The work area for CCM */ +typedef struct sce_ccm_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t formatted_data[HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE]; + uint8_t counter[HW_SCE_AES_CCM_COUNTER_BYTE_SIZE]; + uint8_t ccm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_ccm_handle_t; + +/* The work area for ECDH */ +typedef struct sce_ecdh_handle +{ + uint32_t id; + uint32_t flag_use_key_id; + uint32_t key_id; + uint32_t key_type; + uint8_t flag_call_init; + uint8_t flag_call_make_public; + uint8_t flag_call_read_public; + uint8_t flag_call_shared_secret; +} sce_ecdh_handle_t; + +/* The work area for firmware update */ +typedef struct sce_firmware_generate_mac_resume_handle +{ + uint32_t iLoop; + uint32_t counter; + uint32_t previous_counter; + bool use_resume_flag; +} sce_firmware_generate_mac_resume_handle_t; + +/* The callback function pointer type for HW_SCE_GenerateFirmwareMAC */ +typedef void (*SCE_GEN_MAC_CB_FUNC_T) (SCE_FW_CB_REQ_TYPE req_type, uint32_t iLoop, uint32_t *counter, + uint32_t *InData_UpProgram, uint32_t *OutData_Program, uint32_t MAX_CNT); + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ +#if defined(TSIPTEST_SCE_FULL) /* TSIP-Full */ +fsp_err_t HW_SCE_Open(lifecycle_t lifecycle, sce_tls_ca_certification_public_key_index_t *key_index_1, +#else +fsp_err_t HW_SCE_Open(sce_tls_ca_certification_public_key_index_t *key_index_1, +#endif + sce_update_key_ring_t *key_index_2); +fsp_err_t HW_SCE_Close(void); +void HW_SCE_SoftwareReset(void); + +// added for RA4M1 start +#if defined(TSIPTEST_SCE_FULL) /* TSIP-Full */ +fsp_err_t HW_SCE_FwIntegrityCheck(void); +#endif +fsp_err_t HW_SCE_UpdateOemKeyIndex(lifecycle_t lifecycle, sce_oem_cmd_t key_type, uint8_t *iv, uint8_t *encrypted_oem_key, uint32_t *key_index); + +// added for RA4M1 end + +fsp_err_t HW_SCE_GenerateAes128KeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, + sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes256KeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, + sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateTdesKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, + sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateArc4KeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, + sce_arc4_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa1024PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa1024_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa1024PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa1024_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa2048PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa2048_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa2048PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa2048_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa3072PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa3072_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa3072PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa3072_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa4096PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa4096_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa4096PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa4096_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateTlsRsaPublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_tls_ca_certification_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP192PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP224PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP256PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP384PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP192PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP224PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP256PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP384PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateSha1HmacKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateSha256HmacKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateTlsP256EccKeyIndex(sce_tls_p256_ecc_key_index_t *tls_p256_ecc_key_index, + uint8_t *ephemeral_ecdh_public_key); +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndex(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndex(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa1024RandomKeyIndex(sce_rsa1024_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndex(sce_rsa2048_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateRsa3072RandomKeyIndex(sce_rsa3072_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateRsa4096RandomKeyIndex(sce_rsa4096_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateTdesRandomKeyIndex(sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateArc4RandomKeyIndex(sce_arc4_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP192RandomKeyIndex(uint32_t *indata_curvetype, sce_ecc_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateEccP224RandomKeyIndex(uint32_t *indata_curvetype, sce_ecc_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateEccP256RandomKeyIndex(uint32_t *indata_curvetype, sce_ecc_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndex(uint32_t *indata_curvetype, sce_ecc_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateRandomNumber(uint32_t *random); +#if defined(TSIPTEST_SCE_FULL) /* TSIP-Full */ +fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndex(lifecycle_t lifecycle, uint8_t *encrypted_provisioning_key, uint8_t *iv, +#else +fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, +#endif + uint8_t *encrypted_key, sce_update_key_ring_t *key_index); +uint32_t HW_SCE_GetVersion(void); + +#if defined(TSIPTEST_SCE_FULL) /* TSIP-Full */ +fsp_err_t HW_SCE_UpdateAes128KeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateAes256KeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +#else +fsp_err_t HW_SCE_UpdateAes128KeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateAes256KeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +#endif +fsp_err_t HW_SCE_UpdateTdesKeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateArc4KeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_arc4_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa1024PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa1024_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa1024PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa1024_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa2048PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa2048_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa2048PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa2048_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateTlsRsaPublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_tls_ca_certification_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP192PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP224PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP256PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP384PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP192PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP224PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP256PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP384PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateSha1HmacKeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateSha256HmacKeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_hmac_sha_key_index_t *key_index); + +fsp_err_t HW_SCE_StartUpdateFirmware(void); +fsp_err_t HW_SCE_GenerateFirmwareMAC(uint32_t *InData_KeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_UpProgram, uint32_t *InData_IV, uint32_t *OutData_Program, uint32_t MAX_CNT, + SCE_GEN_MAC_CB_FUNC_T p_callback, + sce_firmware_generate_mac_resume_handle_t *sce_firmware_generate_mac_resume_handle); +fsp_err_t HW_SCE_VerifyFirmwareMAC(uint32_t *InData_Program, uint32_t MAX_CNT, uint32_t *InData_MAC); + +fsp_err_t HW_SCE_Aes128EcbEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128EcbEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128EcbEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes128EcbDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128EcbDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128EcbDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_Aes128CbcEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes128CbcEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CbcEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes128CbcDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes128CbcDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CbcDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Aes256EcbEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256EcbEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256EcbEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes256EcbDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256EcbDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256EcbDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_Aes256CbcEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes256CbcEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CbcEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes256CbcDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes256CbcDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CbcDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Aes128GcmEncryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes128GcmEncryptUpdate(sce_gcm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes128GcmEncryptFinal(sce_gcm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_data_len, + uint8_t *atag); +fsp_err_t HW_SCE_Aes128GcmDecryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes128GcmDecryptUpdate(sce_gcm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes128GcmDecryptFinal(sce_gcm_handle_t *handle, uint8_t *plain, uint32_t *plain_data_len, + uint8_t *atag, uint32_t atag_len); +fsp_err_t HW_SCE_Aes256GcmEncryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes256GcmEncryptUpdate(sce_gcm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes256GcmEncryptFinal(sce_gcm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_data_len, + uint8_t *atag); +fsp_err_t HW_SCE_Aes256GcmDecryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes256GcmDecryptUpdate(sce_gcm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes256GcmDecryptFinal(sce_gcm_handle_t *handle, uint8_t *plain, uint32_t *plain_data_len, + uint8_t *atag, uint32_t atag_len); + +fsp_err_t HW_SCE_Aes128CcmEncryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes128CcmEncryptUpdate(sce_ccm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CcmEncryptFinal(sce_ccm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length, + uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes128CcmDecryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes128CcmDecryptUpdate(sce_ccm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CcmDecryptFinal(sce_ccm_handle_t *handle, uint8_t *plain, uint32_t *plain_length, + uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CcmEncryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes256CcmEncryptUpdate(sce_ccm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CcmEncryptFinal(sce_ccm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length, + uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CcmDecryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes256CcmDecryptUpdate(sce_ccm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CcmDecryptFinal(sce_ccm_handle_t *handle, uint8_t *plain, uint32_t *plain_length, + uint8_t *mac, uint32_t mac_length); + +fsp_err_t HW_SCE_Aes128CmacGenerateInit(sce_cmac_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128CmacGenerateUpdate(sce_cmac_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Aes128CmacGenerateFinal(sce_cmac_handle_t *handle, uint8_t *mac); +fsp_err_t HW_SCE_Aes128CmacVerifyInit(sce_cmac_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128CmacVerifyUpdate(sce_cmac_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Aes128CmacVerifyFinal(sce_cmac_handle_t *handle, uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CmacGenerateInit(sce_cmac_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256CmacGenerateUpdate(sce_cmac_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Aes256CmacGenerateFinal(sce_cmac_handle_t *handle, uint8_t *mac); +fsp_err_t HW_SCE_Aes256CmacVerifyInit(sce_cmac_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256CmacVerifyUpdate(sce_cmac_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Aes256CmacVerifyFinal(sce_cmac_handle_t *handle, uint8_t *mac, uint32_t mac_length); + +fsp_err_t HW_SCE_Aes128KeyWrap(sce_aes_key_index_t *wrap_key_index, uint32_t target_key_type, + sce_aes_key_index_t *target_key_index, uint32_t *wrapped_key); +fsp_err_t HW_SCE_Aes256KeyWrap(sce_aes_key_index_t *wrap_key_index, uint32_t target_key_type, + sce_aes_key_index_t *target_key_index, uint32_t *wrapped_key); +fsp_err_t HW_SCE_Aes128KeyUnwrap(sce_aes_key_index_t *wrap_key_index, uint32_t target_key_type, + uint32_t *wrapped_key, sce_aes_key_index_t *target_key_index); +fsp_err_t HW_SCE_Aes256KeyUnwrap(sce_aes_key_index_t *wrap_key_index, uint32_t target_key_type, + uint32_t *wrapped_key, sce_aes_key_index_t *target_key_index); + +fsp_err_t HW_SCE_TdesEcbEncryptInit(sce_tdes_handle_t *handle, sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_TdesEcbEncryptUpdate(sce_tdes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_TdesEcbEncryptFinal(sce_tdes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_TdesEcbDecryptInit(sce_tdes_handle_t *handle, sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_TdesEcbDecryptUpdate(sce_tdes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_TdesEcbDecryptFinal(sce_tdes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_TdesCbcEncryptInit(sce_tdes_handle_t *handle, sce_tdes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_TdesCbcEncryptUpdate(sce_tdes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_TdesCbcEncryptFinal(sce_tdes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_TdesCbcDecryptInit(sce_tdes_handle_t *handle, sce_tdes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_TdesCbcDecryptUpdate(sce_tdes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_TdesCbcDecryptFinal(sce_tdes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Arc4EncryptInit(sce_arc4_handle_t *handle, sce_arc4_key_index_t *key_index); +fsp_err_t HW_SCE_Arc4EncryptUpdate(sce_arc4_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Arc4EncryptFinal(sce_arc4_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Arc4DecryptInit(sce_arc4_handle_t *handle, sce_arc4_key_index_t *key_index); +fsp_err_t HW_SCE_Arc4DecryptUpdate(sce_arc4_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Arc4DecryptFinal(sce_arc4_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Md5Init(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Md5Update(sce_sha_md5_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Md5Final(sce_sha_md5_handle_t *handle, uint8_t *digest, uint32_t *digest_length); + +fsp_err_t HW_SCE_Sha1Init(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Sha1Update(sce_sha_md5_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1Final(sce_sha_md5_handle_t *handle, uint8_t *digest, uint32_t *digest_length); +fsp_err_t HW_SCE_Sha256Init(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Sha256Update(sce_sha_md5_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256Final(sce_sha_md5_handle_t *handle, uint8_t *digest, uint32_t *digest_length); + +fsp_err_t HW_SCE_Sha1HmacGenerateInit(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha1HmacGenerateUpdate(sce_hmac_sha_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1HmacGenerateFinal(sce_hmac_sha_handle_t *handle, uint8_t *mac); +fsp_err_t HW_SCE_Sha256HmacGenerateInit(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha256HmacGenerateUpdate(sce_hmac_sha_handle_t *handle, uint8_t *message, + uint32_t message_length); +fsp_err_t HW_SCE_Sha256HmacGenerateFinal(sce_hmac_sha_handle_t *handle, uint8_t *mac); +fsp_err_t HW_SCE_Sha1HmacVerifyInit(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha1HmacVerifyUpdate(sce_hmac_sha_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1HmacVerifyFinal(sce_hmac_sha_handle_t *handle, uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Sha256HmacVerifyInit(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha256HmacVerifyUpdate(sce_hmac_sha_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256HmacVerifyFinal(sce_hmac_sha_handle_t *handle, uint8_t *mac, uint32_t mac_length); + +fsp_err_t HW_SCE_RsassaPkcs1024SignatureGenerate(sce_rsa_byte_data_t *message_hash, + sce_rsa_byte_data_t *signature, sce_rsa1024_private_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs1024SignatureVerification(sce_rsa_byte_data_t *signature, + sce_rsa_byte_data_t *message_hash, sce_rsa1024_public_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs2048SignatureGenerate(sce_rsa_byte_data_t *message_hash, + sce_rsa_byte_data_t *signature, sce_rsa2048_private_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs2048SignatureVerification(sce_rsa_byte_data_t *signature, + sce_rsa_byte_data_t *message_hash, sce_rsa2048_public_key_index_t *key_index, uint8_t hash_type); + +fsp_err_t HW_SCE_RsaesPkcs1024Encrypt(sce_rsa_byte_data_t *plain, sce_rsa_byte_data_t *cipher, + sce_rsa1024_public_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs1024Decrypt(sce_rsa_byte_data_t *cipher, sce_rsa_byte_data_t *plain, + sce_rsa1024_private_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs2048Encrypt(sce_rsa_byte_data_t *plain, sce_rsa_byte_data_t *cipher, + sce_rsa2048_public_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs2048Decrypt(sce_rsa_byte_data_t *cipher, sce_rsa_byte_data_t *plain, + sce_rsa2048_private_key_index_t *key_index); + +fsp_err_t HW_SCE_TlsRootCertificateVerification(uint32_t public_key_type, uint8_t *certificate, + uint32_t certificate_length, uint32_t public_key_n_start_position, uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, uint32_t public_key_e_end_position, uint8_t *signature, + uint32_t *encrypted_root_public_key); +fsp_err_t HW_SCE_TlsCertificateVerification(uint32_t public_key_type, uint32_t *encrypted_input_public_key, + uint8_t *certificate, uint32_t certificate_length, uint8_t *signature, uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, uint32_t public_key_e_start_position, uint32_t public_key_e_end_position, + uint32_t *encrypted_output_public_key); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecret(uint32_t *sce_pre_master_secret); +fsp_err_t HW_SCE_TlsGenerateMasterSecret(uint32_t select_cipher_suite, uint32_t *sce_pre_master_secret, + uint8_t *client_random, uint8_t *server_random, uint32_t *sce_master_secret); +fsp_err_t HW_SCE_TlsEncryptPreMasterSecretWithRsa2048PublicKey(uint32_t *encrypted_public_key, + uint32_t *sce_pre_master_secret, uint8_t *encrypted_pre_master_secret); +fsp_err_t HW_SCE_TlsGenerateSessionKey(uint32_t select_cipher_suite, uint32_t *sce_master_secret, + uint8_t *client_random, uint8_t *server_random, uint8_t* nonce_explicit, + sce_hmac_sha_key_index_t *client_mac_key_index, sce_hmac_sha_key_index_t *server_mac_key_index, + sce_aes_key_index_t *client_crypto_key_index, sce_aes_key_index_t *server_crypto_key_index, + uint8_t *client_iv, uint8_t *server_iv); +fsp_err_t HW_SCE_TlsGenerateVerifyData(uint32_t select_verify_data, uint32_t *sce_master_secret, + uint8_t *hand_shake_hash, uint8_t *verify_data); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecretWithEccP256Key(uint32_t *encrypted_public_key, + sce_tls_p256_ecc_key_index_t *tls_p256_ecc_key_index, uint32_t *sce_pre_master_secret); +fsp_err_t HW_SCE_TlsServersEphemeralEcdhPublicKeyRetrieves(uint32_t public_key_type, uint8_t *client_random, + uint8_t *server_random, uint8_t *server_ephemeral_ecdh_public_key, uint8_t *server_key_exchange_signature, + uint32_t *encrypted_public_key, uint32_t *encrypted_ephemeral_ecdh_public_key); + +fsp_err_t HW_SCE_EcdsaP192SignatureGenerate(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *message_hash, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP224SignatureGenerate(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *message_hash, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP256SignatureGenerate(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *message_hash, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP384SignatureGenerate(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *message_hash, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP192SignatureVerification(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *signature, + sce_ecdsa_byte_data_t *message_hash, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP224SignatureVerification(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *signature, + sce_ecdsa_byte_data_t *message_hash, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP256SignatureVerification(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *signature, + sce_ecdsa_byte_data_t *message_hash, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP384SignatureVerification(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *signature, + sce_ecdsa_byte_data_t *message_hash, sce_ecc_public_key_index_t *key_index); + +fsp_err_t HW_SCE_EcdhP256Init(sce_ecdh_handle_t *handle, uint32_t key_type, uint32_t use_key_id); +fsp_err_t HW_SCE_EcdhP256ReadPublicKey(sce_ecdh_handle_t *handle, sce_ecc_public_key_index_t *public_key_index, + uint8_t *public_key_data, sce_ecdsa_byte_data_t *signature, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_EcdhP256MakePublicKey(sce_ecdh_handle_t *handle, sce_ecc_public_key_index_t *public_key_index, + sce_ecc_private_key_index_t *private_key_index, uint8_t *public_key, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdhP256CalculateSharedSecretIndex(sce_ecdh_handle_t *handle, + sce_ecc_public_key_index_t *public_key_index, sce_ecc_private_key_index_t *private_key_index, + sce_ecdh_key_index_t *shared_secret_index); +fsp_err_t HW_SCE_EcdhP256KeyDerivation(sce_ecdh_handle_t *handle, sce_ecdh_key_index_t *shared_secret_index, + uint32_t algorithm_id, uint8_t *other_info, uint32_t other_info_length, sce_aes_key_index_t *key_index); + +#if SCE_USER_SHA_384_ENABLED != 0 +uint32_t SCE_USER_SHA_384_FUNCTION(uint8_t *message, uint8_t *digest, uint32_t message_length); +#endif /* SCE_USER_SHA_384_ENABLED != 0 */ + +#endif /* R_SCE_IF_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_aes_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_aes_private.h new file mode 100644 index 0000000000..d9577ff0c6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_aes_private.h @@ -0,0 +1,366 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef HW_SCE_AES_PRIVATE_H +#define HW_SCE_AES_PRIVATE_H + +#include +#include "bsp_api.h" + +/* AES key lengths defined for SCE operations. */ +#define SIZE_AES_128BIT_KEYLEN_BITS (128) +#define SIZE_AES_128BIT_KEYLEN_BYTES ((SIZE_AES_128BIT_KEYLEN_BITS) / 8) +#define SIZE_AES_128BIT_KEYLEN_WORDS ((SIZE_AES_128BIT_KEYLEN_BITS) / 32) + +#define SIZE_AES_192BIT_KEYLEN_BITS (192) +#define SIZE_AES_192BIT_KEYLEN_BYTES ((SIZE_AES_192BIT_KEYLEN_BITS) / 8) +#define SIZE_AES_192BIT_KEYLEN_WORDS ((SIZE_AES_192BIT_KEYLEN_BITS) / 32) + +#define SIZE_AES_256BIT_KEYLEN_BITS (256) +#define SIZE_AES_256BIT_KEYLEN_BYTES ((SIZE_AES_256BIT_KEYLEN_BITS) / 8) +#define SIZE_AES_256BIT_KEYLEN_WORDS ((SIZE_AES_256BIT_KEYLEN_BITS) / 32) + +#define SIZE_AES_BLOCK_BITS (128U) +#define SIZE_AES_BLOCK_BYTES ((SIZE_AES_BLOCK_BITS) / 8) +#define SIZE_AES_BLOCK_WORDS ((SIZE_AES_BLOCK_BITS) / 32) + +#define SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION (0x00000000U) +#define SCE_AES_IN_DATA_CMD_ECB_DECRYPTION (0x00000001U) +#define SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION (0x00000002U) +#define SCE_AES_IN_DATA_CMD_CBC_DECRYPTION (0x00000003U) +#define SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION (0x00000004U) + +typedef struct st_sce_data +{ + uint32_t length; + uint32_t * p_data; +} r_sce_data_t; + +typedef fsp_err_t (* hw_sce_cmac_init_t)(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +typedef void (* hw_sce_cmac_update_t)(const uint32_t InData_Text[], const uint32_t MAX_CNT); +typedef fsp_err_t (* hw_sce_cmac_final_t)(const uint32_t InData_Cmd[], const uint32_t InData_Text[], + const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]); + +typedef fsp_err_t (* hw_sce_aes_gcm_crypt_init_t)(uint32_t * InData_KeyType, uint32_t * InData_DataType, + uint32_t * InData_Cmd, uint32_t * InData_KeyIndex, + uint32_t * InData_IV, uint32_t * InData_SeqNum); +typedef void (* hw_sce_aes_gcm_update_aad_t)(const uint32_t * InData_DataA, const uint32_t MAX_CNT); +typedef void (* hw_sce_aes_gcm_crypt_update_transition_t)(void); +typedef void (* hw_sce_aes_gcm_crypt_update_t)(const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT); +typedef fsp_err_t (* hw_sce_aes_gcm_encrypt_final_t)(const uint32_t * InData_Text, const uint32_t * InData_TextLen, + const uint32_t * InData_DataALen, uint32_t * OutData_Text, + uint32_t * OutData_DataT); +typedef fsp_err_t (* hw_sce_aes_gcm_decrypt_final_t)(const uint32_t * InData_Text, const uint32_t * InData_TextLen, + const uint32_t * InData_DataALen, const uint32_t * InData_DataT, + const uint32_t * InData_DataTLen, + uint32_t * OutData_Text); +typedef fsp_err_t (* hw_sce_aes_ccm_encrypt_init_t)(uint32_t * InData_KeyType, uint32_t * InData_DataType, + uint32_t * InData_Cmd, uint32_t * InData_TextLen, + uint32_t * InData_KeyIndex, uint32_t * InData_IV, + uint32_t * InData_Header, uint32_t * InData_SeqNum, + uint32_t Header_Len); +typedef fsp_err_t (* hw_sce_aes_ccm_decrypt_init_t)(uint32_t * InData_KeyType, uint32_t * InData_DataType, + uint32_t * InData_Cmd, uint32_t * InData_TextLen, + uint32_t * InData_MACLength, uint32_t * InData_KeyIndex, + uint32_t * InData_IV, uint32_t * InData_Header, + uint32_t * InData_SeqNum, uint32_t Header_Len); + +typedef void (* hw_sce_aes_ccm_crypt_update_t)(const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT); +typedef fsp_err_t (* hw_sce_aes_ccm_encrypt_final_t)(const uint32_t * InData_Text, const uint32_t * InData_TextLen, + uint32_t * OutData_Text, uint32_t * OutData_MAC); +typedef fsp_err_t (* hw_sce_aes_ccm_decrypt_final_t)(const uint32_t * InData_Text, const uint32_t * InData_TextLen, + const uint32_t * InData_MAC, const uint32_t * InData_MACLength, + uint32_t * OutData_Text); +typedef fsp_err_t (* hw_sce_aes_ecb_encrypt_using_encrypted_key)(const uint32_t * InData_KeyIndex, + const uint32_t num_words, const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_128EcbEncrypt(const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_128EcbDecrypt(const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_128CbcEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_128CbcDecrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_128CtrEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_128XtsEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t * InData_Len, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_128XtsDecrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t * InData_Len, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_192EcbEncrypt(const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_192EcbDecrypt(const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_192CbcEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_192CbcDecrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_192CtrEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_256EcbEncrypt(const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_256EcbDecrypt(const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_256CbcEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_256CbcDecrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_256CtrEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_256XtsEncrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t * InData_Len, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_256XtsDecrypt(const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t * InData_Len, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t * OutData_KeyIndex); +extern fsp_err_t HW_SCE_AES_128CreateEncryptedKey(uint32_t * OutData_KeyIndex); + +extern fsp_err_t HW_SCE_AES_128EcbEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_128EcbDecryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_128CbcEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_128CbcDecryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_128CtrEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub(uint32_t * OutData_KeyIndex); +extern fsp_err_t HW_SCE_AES_192CreateEncryptedKey(uint32_t * OutData_KeyIndex); + +extern fsp_err_t HW_SCE_AES_192EcbEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_192EcbDecryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_192CbcEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_192CbcDecryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_192CtrEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t * OutData_KeyIndex); +extern fsp_err_t HW_SCE_AES_256CreateEncryptedKey(uint32_t * OutData_KeyIndex); + +extern fsp_err_t HW_SCE_AES_256EcbEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_256EcbDecryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +extern fsp_err_t HW_SCE_AES_256CbcEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_256CbcDecryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_AES_256CtrEncryptUsingEncryptedKey(const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +extern fsp_err_t HW_SCE_Aes128EncryptDecryptInit(const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); + +extern void HW_SCE_Aes128EncryptDecryptUpdate(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t num_words); + +extern fsp_err_t HW_SCE_Aes128EncryptDecryptFinal(void); + +extern fsp_err_t HW_SCE_Aes192EncryptDecryptInit(const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); + +extern void HW_SCE_Aes192EncryptDecryptUpdate(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t num_words); + +extern fsp_err_t HW_SCE_Aes192EncryptDecryptFinal(void); + +extern fsp_err_t HW_SCE_Aes256EncryptDecryptInit(const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); + +extern void HW_SCE_Aes256EncryptDecryptUpdate(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t num_words); + +extern fsp_err_t HW_SCE_Aes256EncryptDecryptFinal(void); + +fsp_err_t HW_SCE_Aes128EcbEncryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t HW_SCE_Aes128EcbDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +fsp_err_t HW_SCE_Aes192EcbEncryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t HW_SCE_Aes192EcbDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +fsp_err_t HW_SCE_Aes256EcbEncryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t HW_SCE_Aes256EcbDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +fsp_err_t HW_SCE_Aes128CbcEncryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t HW_SCE_Aes128CbcDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +fsp_err_t HW_SCE_Aes192CbcEncryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t HW_SCE_Aes192CbcDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +fsp_err_t HW_SCE_Aes256CbcEncryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t HW_SCE_Aes256CbcDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +fsp_err_t HW_SCE_Aes128CtrEncryptDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +fsp_err_t HW_SCE_Aes192CtrEncryptDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +fsp_err_t HW_SCE_Aes256CtrEncryptDecryptInitSubGeneral(uint32_t * InData_KeyIndex, uint32_t * InData_IV); + +void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); + +#endif /* HW_SCE_AES_PRIVATE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_ecc_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_ecc_private.h new file mode 100644 index 0000000000..1b2a9e22df --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_ecc_private.h @@ -0,0 +1,247 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * File Name : hw_sce_ecc_private.h + * Description : SCE HW procedures for ECC algorithm + ***********************************************************************************************************************/ + +#ifndef HW_SCE_ECC_PRIVATE_H +#define HW_SCE_ECC_PRIVATE_H + +#include "bsp_api.h" +#include "hw_sce_common.h" + +#define ECC_224_PRIVATE_KEY_LENGTH_BITS (224U) +#define ECC_224_PUBLIC_KEY_LENGTH_WORDS (7U) + +/* ECC P-256 */ +#define ECC_256_DOMAIN_PARAMETER_WITH_ORDER_LENGTH_WORDS (32U) +#define ECC_256_DOMAIN_PARAMETER_WITHOUT_ORDER_LENGTH_WORDS (24U) +#define ECC_256_POINT_ON_CURVE_LENGTH_WORDS (16U) +#define ECC_256_GENERATOR_POINT_LENGTH_WORDS (16U) +#define ECC_256_PUBLIC_KEY_LENGTH_WORDS (16U) +#define ECC_256_PRIVATE_KEY_LENGTH_WORDS (8U) +#define ECC_256_PRIVATE_KEY_LENGTH_BITS (256U) +#define ECC_256_MESSAGE_DIGEST_LENGTH_WORDS (8U) +#define ECC_256_SIGNATURE_R_LENGTH_WORDS (8U) +#define ECC_256_SIGNATURE_S_LENGTH_WORDS (8U) + +/* ECC P-384 */ +#define ECC_384_DOMAIN_PARAMETER_WITH_ORDER_LENGTH_WORDS (48U) +#define ECC_384_DOMAIN_PARAMETER_WITHOUT_ORDER_LENGTH_WORDS (36U) +#define ECC_384_POINT_ON_CURVE_LENGTH_WORDS (24U) +#define ECC_384_GENERATOR_POINT_LENGTH_WORDS (24U) +#define ECC_384_PUBLIC_KEY_LENGTH_WORDS (24U) +#define ECC_384_PRIVATE_KEY_LENGTH_WORDS (12U) +#define ECC_384_PRIVATE_KEY_LENGTH_BITS (384U) +#define ECC_384_MESSAGE_DIGEST_LENGTH_WORDS (12U) +#define ECC_384_SIGNATURE_R_LENGTH_WORDS (12U) +#define ECC_384_SIGNATURE_S_LENGTH_WORDS (12U) + +/* ECC P-521 */ +#define ECC_521_PRIVATE_KEY_LENGTH_BITS (521U) +#define ECC_521_PRIVATE_KEY_LENGTH_WORDS (20U) + +/* ECC ED-25519 */ +#define ECC_25519_PRIVATE_KEY_LENGTH_BITS (255U) +#define ECC_25519_PRIVATE_KEY_LENGTH_WORDS (8U) + +/* SCE based wrapped keys are at most 20/32 bytes larger than corresponding plain private keys */ +#define HW_SCE_ECC_WRAPPED_KEY_ADJUST(x) ((x) + ((HW_SCE_PRIVATE_KEY_WRAPPING_WORD_SIZE) * 4)) + +/* Function pointer declarations */ +#if BSP_FEATURE_RSIP_SCE9_SUPPORTED || BSP_FEATURE_RSIP_SCE7_SUPPORTED || BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED || \ + BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED || BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED || BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED + #define ECC_PUBLIC_KEY_SIZE_BYTES(curve_size) (curve_size * 2 + 20U) +typedef fsp_err_t (* hw_sce_ecc_scalarmultiplication_t)(const uint32_t * InData_CurveType, const uint32_t * InData_Cmd, + const uint32_t * InData_K, const uint32_t * InData_P, + const uint32_t * Domain_Param, uint32_t * OutData_R); +#else +typedef fsp_err_t (* hw_sce_ecc_scalarmultiplication_t)(const uint32_t * InData_DomainParam, const uint32_t * InData_K, + const uint32_t * InData_P, uint32_t * OutData_R); +#endif +typedef fsp_err_t (* hw_sce_ecc_generatekey_t)(const uint32_t * InData_DomainParam, const uint32_t * InData_G, + uint32_t * OutData_PubKey, uint32_t * OutData_PrivKey); + +typedef fsp_err_t (* hw_sce_ecc_generatesign_t)(const uint32_t * InData_CurveType, const uint32_t * InData_G, + const uint32_t * InData_PrivKey, const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, uint32_t * OutData_S); + +typedef fsp_err_t (* hw_sce_ecc_verifysign_t)(const uint32_t * InData_DomainParam, const uint32_t * InData_G, + const uint32_t * InData_PubKey, const uint32_t * InData_MsgDgst, + const uint32_t * InData_R, const uint32_t * InData_S); + +/* ECC - 256 HW Procedure definitions */ +fsp_err_t HW_SCE_ECC_256ScalarMultiplication(const uint32_t * InData_DomainParam, + const uint32_t * InData_K, + const uint32_t * InData_P, + uint32_t * OutData_R); + +fsp_err_t HW_SCE_ECC_256GenerateKey(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + uint32_t * OutData_PubKey, + uint32_t * OutData_PrivKey); + +fsp_err_t HW_SCE_ECC_256GenerateSign(const uint32_t * InData_CurveType, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_256VerifySign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PubKey, + const uint32_t * InData_MsgDgst, + const uint32_t * InData_R, + const uint32_t * InData_S); + +/* ECC - 256 Wrapped key HW Procedure definitions */ +fsp_err_t HW_SCE_ECC_256HrkGenerateKey(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + uint32_t * OutData_KeyIndex, + uint32_t * OutData_PubKey); + +fsp_err_t HW_SCE_ECC_256HrkGenerateSign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_256HrkScalarMultiplication(const uint32_t * InData_DomainParam, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + uint32_t * OutData_R); + +fsp_err_t HW_SCE_ECC_256WrappedScalarMultiplication(const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + const uint32_t * Domain_Param, + uint32_t * OutData_R); + +/* ECC - 384 HW Procedure definitions */ +fsp_err_t HW_SCE_ECC_384ScalarMultiplication(const uint32_t * InData_DomainParam, + const uint32_t * InData_K, + const uint32_t * InData_P, + uint32_t * OutData_R); + +fsp_err_t HW_SCE_ECC_384GenerateKey(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + uint32_t * OutData_PubKey, + uint32_t * OutData_PrivKey); + +fsp_err_t HW_SCE_ECC_384GenerateSign(const uint32_t * InData_CurveType, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_384VerifySign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PubKey, + const uint32_t * InData_MsgDgst, + const uint32_t * InData_R, + const uint32_t * InData_S); + +/* ECC - 384 Wrapped key HW Procedure definitions */ +fsp_err_t HW_SCE_ECC_384HrkGenerateKey(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + uint32_t * OutData_KeyIndex, + uint32_t * OutData_PubKey); + +fsp_err_t HW_SCE_ECC_384HrkGenerateSign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_384HrkScalarMultiplication(const uint32_t * InData_DomainParam, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + uint32_t * OutData_R); + +#if BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED || BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED +fsp_err_t HW_SCE_ECC_521GenerateSign(const uint32_t * InData_CurveType, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_521VerifySign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PubKey, + const uint32_t * InData_MsgDgst, + const uint32_t * InData_R, + const uint32_t * InData_S); + +fsp_err_t HW_SCE_ECC_521HrkGenerateSign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_521WrappedScalarMultiplication(const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + const uint32_t * Domain_Param, + uint32_t * OutData_R); + +#endif +#if BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED || BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED || BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED +fsp_err_t HW_SCE_ECC_255GenerateSign(const uint32_t * InData_CurveType, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_255HrkGenerateSign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +#endif + +fsp_err_t HW_SCE_ECC_384WrappedScalarMultiplication(const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + const uint32_t * Domain_Param, + uint32_t * OutData_R); + +fsp_err_t HW_SCE_ECC_ED25519WrappedScalarMultiplication(const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + const uint32_t * Domain_Param, + uint32_t * OutData_R); + +/* ECC - 224 HW Procedure definitions */ +fsp_err_t HW_SCE_ECC_224GenerateSign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S); + +fsp_err_t HW_SCE_ECC_224VerifySign(const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PubKey, + const uint32_t * InData_MsgDgst, + const uint32_t * InData_R, + const uint32_t * InData_S); + +#endif /* HW_SCE_ECC_PRIVATE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_hash_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_hash_private.h new file mode 100644 index 0000000000..431bbed46c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_hash_private.h @@ -0,0 +1,77 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef HW_SCE_HASH_PRIVATE_H +#define HW_SCE_HASH_PRIVATE_H + +/********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ +#include "bsp_api.h" +#include "hw_sce_common.h" + +#define HW_SCE_LARGE_DATA_VALUE_0 (0x80000000U) +#define HW_SCE_LARGE_DATA_VALUE_1 (0x00000000U) + +/*******************************************************************************************************************//** + * Converts byte data to bit data. This function returns upper 3 digits. + ***********************************************************************************************************************/ +static inline uint32_t r_sce_byte_to_bit_convert_upper (const uint64_t bytes) +{ + return (uint32_t) (bytes >> 29); +} + +/*******************************************************************************************************************//** + * Converts byte data to bit data. This function returns lower 32 digits. + ***********************************************************************************************************************/ +static inline uint32_t r_sce_byte_to_bit_convert_lower (const uint64_t bytes) +{ + return (uint32_t) (bytes << 3); +} + +fsp_err_t HW_SCE_SHA256_UpdateHash(const uint32_t * p_source, uint32_t num_words, uint32_t * p_digest); +extern fsp_err_t HW_SCE_Sha224256GenerateMessageDigestSub(const uint32_t * InData_InitVal, + const uint32_t * InData_PaddedMsg, + const uint32_t MAX_CNT, + uint32_t * OutData_MsgDigest); + +#if BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED +extern fsp_err_t HW_SCE_ShaGenerateMessageDigestSub(const uint32_t InData_InitVal[], + const uint32_t InData_PaddedMsg[], + uint32_t OutData_MsgDigest[], + const uint32_t MAX_CNT); + +#else +extern fsp_err_t HW_SCE_ShaGenerateMessageDigestSub(const uint32_t InData_HashType[], + const uint32_t InData_Cmd[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_State[], + uint32_t OutData_MsgDigest[], + uint32_t OutData_State[], + const uint32_t MAX_CNT); + +#endif +extern fsp_err_t HW_SCE_ShaGenerateMessageDigestSubGeneral(const uint32_t InData_HashType[], + const uint32_t InData_Cmd[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_State[], + uint32_t OutData_MsgDigest[], + uint32_t OutData_State[], + const uint32_t MAX_CNT, + const uint32_t InData_InitVal[]); + +extern fsp_err_t HW_SCE_Sha3GenerateMessageDigestSubGeneral(const uint32_t InData_HashType[], + const uint32_t InData_Cmd[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_State[], + uint32_t OutData_MsgDigest[], + uint32_t OutData_State[], + const uint32_t MAX_CNT); + +#endif /* HW_SCE_HASH_PRIVATE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_private.h new file mode 100644 index 0000000000..9a8beb3860 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_private.h @@ -0,0 +1,96 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup SCE + * @addtogroup SCE_PROC + * @{ + ***********************************************************************************************************************/ + +#ifndef HW_SCE_PRIVATE_H +#define HW_SCE_PRIVATE_H + +/********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ +#include "bsp_api.h" +#include "hw_sce_common.h" +#include "hw_sce_ra_private.h" + +/********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ +#define SCE_ECC_CURVE_TYPE_NIST (0x00000000U) +#define SCE_ECC_CURVE_TYPE_BRAINPOOL (0x01000000U) +#define SCE_ECC_CURVE_TYPE_KOBLITZ (0x02000000U) + +/********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +typedef enum e_crypto_word_endian +{ + CRYPTO_WORD_ENDIAN_BIG = 0, + CRYPTO_WORD_ENDIAN_LITTLE = 1 +} crypto_word_endian_t; + +/* + * typedef enum e_sce_oem_key_type + * { + * SCE_OEM_KEY_TYPE_ENCRYPTED = 0, + * SCE_OEM_KEY_TYPE_PLAIN = 1 + * } sce_oem_key_type_t; + */ + +/********************************************************************************************************************** + * Function Prototypes + ***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ + +extern uint32_t S_RAM[]; +extern uint32_t S_HEAP[]; +extern uint32_t S_INST[]; +extern uint32_t S_INST2[]; +extern uint32_t INST_DATA_SIZE; +extern void HW_SCE_SoftReset(void); + +extern fsp_err_t HW_SCE_Initialization1(void); + +extern fsp_err_t HW_SCE_Initialization2(void); + +void HW_SCE_Initialization1_Subproc1(void); +void HW_SCE_Initialization2_Subproc2(void); +void SC32_Subprc03(void); +void SC32_Subprc04(void); +void SC32_Subprc05(void); +fsp_err_t HW_SCE_secureBoot(void); + +void HW_SCE_EndianSetBig(void); +void HW_SCE_EndianSetLittle(void); +crypto_word_endian_t HW_SCE_EndianFlagGet(void); +fsp_err_t HW_SCE_McuSpecificInit(void); + +fsp_err_t HW_SCE_FW_IntegrityChk(void); +fsp_err_t HW_SCE_HUK_Load(uint32_t * InData_LC); +fsp_err_t HW_SCE_HUK_Load_LCS(void); +fsp_err_t HW_SCE_p07(uint32_t * OutData_KeyIndex); +void HW_SCE_ChangeToLittleEndian(void); + +fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate(const sce_oem_key_type_t key_type, + const sce_oem_cmd_t cmd, + const uint8_t * encrypted_provisioning_key, + const uint8_t * iv, + const uint8_t * encrypted_oem_key, + uint32_t * key_index); + +#endif /* HW_SCE_PRIVATE_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROC) + ***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_rsa_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_rsa_private.h new file mode 100644 index 0000000000..ca93fa1140 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_rsa_private.h @@ -0,0 +1,75 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef HW_SCE_RSA_PRIVATE_H +#define HW_SCE_RSA_PRIVATE_H + +/********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ +#include "bsp_api.h" +#include "hw_sce_common.h" + +typedef fsp_err_t (* hw_sce_rsa_generatekey_t)(uint32_t num_tries, uint32_t * OutData_KeyIndex, uint32_t * OutData_N, + uint32_t * OutData_DomainParam); + +typedef fsp_err_t (* hw_sce_rsa_private_decrypt_t)(const uint32_t * InData_Text, const uint32_t * InData_KeyIndex, + const uint32_t * InData_N, uint32_t * OutData_Text); + +typedef fsp_err_t (* hw_sce_rsa_public_encrypt_t)(const uint32_t * InData_Text, const uint32_t * InData_PublicKey, + const uint32_t * InData_N, uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_4096PublicKeyEncrypt(const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_3072PublicKeyEncrypt(const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_2048PublicKeyEncrypt(const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_2048PrivateKeyDecrypt(const uint32_t * InData_Text, + const uint32_t * InData_PrivateKey, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_2048KeyGenerate(uint32_t num_tries, + uint32_t * OutData_PrivateKey, + uint32_t * OutData_N, + uint32_t * OutData_DomainParam); + +fsp_err_t HW_SCE_HRK_RSA_2048PrivateKeyDecrypt(const uint32_t * InData_Text, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_1024PublicKeyEncrypt(const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_1024PrivateKeyDecrypt(const uint32_t * InData_Text, + const uint32_t * InData_PrivateKey, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_1024KeyGenerate(uint32_t num_tries, + uint32_t * OutData_PrivateKey, + uint32_t * OutData_N, + uint32_t * OutData_DomainParam); + +fsp_err_t HW_SCE_HRK_RSA_1024PrivateKeyDecrypt(const uint32_t * InData_Text, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +#endif /* HW_SCE_RSA_PRIVATE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_trng_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_trng_private.h new file mode 100644 index 0000000000..12145eed6c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/hw_sce_trng_private.h @@ -0,0 +1,24 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef HW_SCE_TRNG_PRIVATE_H +#define HW_SCE_TRNG_PRIVATE_H + +/********************************************************************************************************************** + * Includes + ***********************************************************************************************************************/ +#include "bsp_api.h" +#include "hw_sce_common.h" + +// TRNG + +/** + * @brief Generate 128-bit random number using SCE HW TRNG + * @param[out] OutData_Text 128-bit random number will be stored in this buffer + */ +fsp_err_t HW_SCE_RNG_Read(uint32_t * OutData_Text); + +#endif /* HW_SCE_TRNG_PRIVATE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_endian.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_endian.c new file mode 100644 index 0000000000..8b7fd7d9a1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_endian.c @@ -0,0 +1,27 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "hw_sce_private.h" + +static crypto_word_endian_t s1_endian_flag = CRYPTO_WORD_ENDIAN_BIG; + +void HW_SCE_EndianSetBig (void) +{ + s1_endian_flag = CRYPTO_WORD_ENDIAN_BIG; +} + +void HW_SCE_EndianSetLittle (void) +{ + s1_endian_flag = CRYPTO_WORD_ENDIAN_LITTLE; +} + +crypto_word_endian_t HW_SCE_EndianFlagGet (void) +{ + return s1_endian_flag; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p04.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p04.prc.c new file mode 100644 index 0000000000..8aaae1e46a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p04.prc.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +///////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 04 // +// File name : SC324_p04.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[4] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// Return Value : Pass, Fail or Resource_Conflict // +// ---------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : 259 + (MAX_CNT/4-1)*44 cycle // +// polling access : 11 + (MAX_CNT/4-1)*2 times // +// write access : 44 + (MAX_CNT-4) times // +// read access : 4 + (MAX_CNT-4) times // +///////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-128 Encryption with ECB Mode. + * + * @param[in] InData_Key In data key + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_128EcbEncrypt (const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_ENCRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_128; + aesCtrl.mode = SC324_AES_ECB; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, InData_Key, NULL, num_words, InData_Text, OutData_Text, NULL); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p05.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p05.prc.c new file mode 100644 index 0000000000..6259b4acfb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p05.prc.c @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +///////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 05 // +// File name : SC324_p05.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[4] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// Return Value : Pass, Fail or Resource_Conflict // +// ---------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : 303 + (MAX_CNT/4-1)*44 cycle // +// polling access : 11 + (MAX_CNT/4-1)*2 times // +// write access : 44 + (MAX_CNT-4) times // +// read access : 4 + (MAX_CNT-4) times // +///////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-128 Decryption with ECB Mode + * + * @param[in] InData_Key In data key + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_128EcbDecrypt (const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_DECRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_128; + aesCtrl.mode = SC324_AES_ECB; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, InData_Key, NULL, num_words, InData_Text, OutData_Text, NULL); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p06.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p06.prc.c new file mode 100644 index 0000000000..228d42e07b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p06.prc.c @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +///////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 06 // +// File name : SC324_p06.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[4] // +// : InData_IV[4] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// OutData_IV[4] // +// Return Value : Pass, Fail or Resource_Conflict // +// ---------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : 329 + (MAX_CNT/4-1)*44 cycle // +// polling access : 12 + (MAX_CNT/4-1)*2 times // +// write access : 50 + (MAX_CNT-4) times // +// read access : 4 + (MAX_CNT-4) times // +///////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" + +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * Encryption with AES 128-bit key in CBC chaining mode. + * + * @param[in] InData_Key In data key + * @param[in] InData_IV In data iv + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * @param OutData_IV The out data iv + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_128CbcEncrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_ENCRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_128; + aesCtrl.mode = SC324_AES_CBC; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, + InData_Key, + InData_IV, + num_words, + InData_Text, + OutData_Text, + OutData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p07.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p07.prc.c new file mode 100644 index 0000000000..362156c1a2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p07.prc.c @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +///////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 07 // +// File name : SC324_p07.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[4] // +// : InData_IV[4] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// OutData_IV[4] // +// Return Value : Pass, Fail or Resource_Conflict // +// ---------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : // +// polling access : // +// write access : // +// read access : // +///////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" + +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-128 Decryption with CBC Mode + * + * @param[in] InData_Key In data key + * @param[in] InData_IV In data iv + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * @param OutData_IV The out data iv + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_128CbcDecrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_DECRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_128; + aesCtrl.mode = SC324_AES_CBC; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, + InData_Key, + InData_IV, + num_words, + InData_Text, + OutData_Text, + OutData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p08.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p08.prc.c new file mode 100644 index 0000000000..164dd2c3e0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p08.prc.c @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +///////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 08 // +// File name : SC324_p08.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[4] // +// : InData_IV[4] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// OutData_IV[4] // +// Return Value : Pass, Fail or Resource_Conflict // +// ---------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : // +// polling access : // +// write access : // +// read access : // +///////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" + +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-128 Encryption/Decryption with CTR Mode + * + * @param[in] InData_Key In data key + * @param[in] InData_IV In data iv + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * @param OutData_IV The out data iv + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_128CtrEncrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_ENCRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_128; + aesCtrl.mode = SC324_AES_CTR; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, + InData_Key, + InData_IV, + num_words, + InData_Text, + OutData_Text, + OutData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p20.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p20.prc.c new file mode 100644 index 0000000000..2e2927e597 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p20.prc.c @@ -0,0 +1,54 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +///////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 20 // +// File name : SC324_p20.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[8] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// Return Value : Pass, Fail or Resource_Conflict // +// ---------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : // +// polling access : // +// write access : // +// read access : // +///////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" + +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-256 Encryption ECB Mode + * + * @param[in] InData_Key In data key + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_256EcbEncrypt (const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_ENCRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_256; + aesCtrl.mode = SC324_AES_ECB; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, InData_Key, NULL, num_words, InData_Text, OutData_Text, NULL); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p21.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p21.prc.c new file mode 100644 index 0000000000..aa5bcb3b06 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p21.prc.c @@ -0,0 +1,54 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +///////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 21 // +// File name : SC324_p21.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[8] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// Return Value : Pass, Fail or Resource_Conflict // +// ---------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : // +// polling access : // +// write access : // +// read access : // +///////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" + +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-256 Decryption ECB Mode + * + * @param[in] InData_Key In data key + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_256EcbDecrypt (const uint32_t * InData_Key, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_DECRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_256; + aesCtrl.mode = SC324_AES_ECB; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, InData_Key, NULL, num_words, InData_Text, OutData_Text, NULL); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p22.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p22.prc.c new file mode 100644 index 0000000000..5d7f8796e3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p22.prc.c @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 22 // +// File name : SC324_p22.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[8] // +// : InData_IV[4] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// OutData_IV[4] // +// Return Value : Pass, Fail or Resource_Conflict // +// ------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : // +// polling access : // +// write access : // +// read access : // +////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" + +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-256 Encryption CBC Mode + * + * @param[in] InData_Key In data key + * @param[in] InData_IV In data iv + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * @param OutData_IV The out data iv + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_256CbcEncrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_ENCRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_256; + aesCtrl.mode = SC324_AES_CBC; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, + InData_Key, + InData_IV, + num_words, + InData_Text, + OutData_Text, + OutData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p23.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p23.prc.c new file mode 100644 index 0000000000..8085cb5a93 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p23.prc.c @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 23 // +// File name : SC324_p23.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[8] // +// : InData_IV[4] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// OutData_IV[4] // +// Return Value : Pass, Fail or Resource_Conflict // +// ------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : // +// polling access : // +// write access : // +// read access : // +////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-256 Decryption CBC Mode + * + * @param[in] InData_Key In data key + * @param[in] InData_IV In data iv + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * @param OutData_IV The out data iv + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_256CbcDecrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_DECRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_256; + aesCtrl.mode = SC324_AES_CBC; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, + InData_Key, + InData_IV, + num_words, + InData_Text, + OutData_Text, + OutData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p24.prc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p24.prc.c new file mode 100644 index 0000000000..1d39acc9cf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SC324_p24.prc.c @@ -0,0 +1,65 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +////////////////////////////////////////////////////////////////////// +// // +// Procedure number: 24 // +// File name : SC324_p24.prc // +// State Diagram : main(FSM1) // +// Start State : main03 // +// End State : main03 // +// Input Data : InData_Key[8] // +// : InData_IV[4] // +// : InData_Text[MAX_CNT] // +// Output Data : OutData_Text[MAX_CNT] // +// : (MAX_CNT is Multiples of four.) // +// OutData_IV[4] // +// Return Value : Pass, Fail or Resource_Conflict // +// ------------------------------------------------------------------// +// total cycle : polling + write access + read access // +// polling : // +// polling access : // +// write access : // +// read access : // +////////////////////////////////////////////////////////////////////// + +#include "sc324_aes_private.h" +#include "hw_sce_aes_private.h" + +/*******************************************************************************************************************//** + * AES-256 Encryption/Decryption with CTR Mode + * + * @param[in] InData_Key In data key + * @param[in] InData_IV In data iv + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * @param OutData_IV The out data iv + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_AES_256CtrEncrypt (const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + hw_sc324_aes_ctrl_t aesCtrl; + + aesCtrl.encrypt_flag = SC324_AES_ENCRYPT; + aesCtrl.keysize = SC324_AES_KEYSIZE_256; + aesCtrl.mode = SC324_AES_CTR; + + return hw_sc324_aes_kernel_process_data(&aesCtrl, + InData_Key, + InData_IV, + num_words, + InData_Text, + OutData_Text, + OutData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SCE_module.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SCE_module.h new file mode 100644 index 0000000000..4cabc070dd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/SCE_module.h @@ -0,0 +1,17 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H +#include "bsp_api.h" + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ +#define SCE1_TRNG_BASE 0x400D1000UL +#define SCE1_AES_BASE 0x400D0000UL + +#endif // HW_SCE_MODULE_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/hw_sce_ra_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/hw_sce_ra_private.h new file mode 100644 index 0000000000..6cd4162829 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/hw_sce_ra_private.h @@ -0,0 +1,103 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : hw_sce_ra_private.h + * Version : 1.09 + * Description : SCE function private header file. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ +#ifndef HW_SCE_RA_PRIVATE_HEADER_FILE +#define HW_SCE_RA_PRIVATE_HEADER_FILE + +#include "hw_sce_aes_private.h" + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ +#define SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION (0x00000000U) +#define SCE_AES_IN_DATA_CMD_ECB_DECRYPTION (0x00000001U) +#define SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION (0x00000002U) +#define SCE_AES_IN_DATA_CMD_CBC_DECRYPTION (0x00000003U) +#define SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION (0x00000004U) + +/* Wrapped keys not supported on RA2; these definitions are added to let the code compile. */ +#define SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED (1) +#define SIZE_AES_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 8) +#define SIZE_AES_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED) / 32) + +#define SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED (2) /* 192 not supported on SCE5 */ +#define SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 8) +#define SIZE_AES_192BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED) / 32) + +#define SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED (3) +#define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8) +#define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32) + +/********************************************************************************************************************** + * Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions + *********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ +uint32_t change_endian_long(uint32_t data); + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor(const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]); + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub(const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +void HW_SCE_Aes192EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +void HW_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void); + +#endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/r_sce_AES_adapt.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/r_sce_AES_adapt.c new file mode 100644 index 0000000000..84e79d9ed4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/r_sce_AES_adapt.c @@ -0,0 +1,284 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + ***********************************************************************************************************************/ +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Imported global variables and functions (from other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ +static uint32_t InputData_KeyType; +static uint32_t InputData_Cmd; +static uint32_t InputData_KeyIndex[44] /*[SIZE_AES_256BIT_KEYLEN_BYTES]*/; +static uint32_t InputData_IV[16]; + +uint32_t change_endian_long (uint32_t a) +{ + return __REV(a); +} + +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub (uint32_t * OutData_KeyIndex) +{ + FSP_PARAMETER_NOT_USED(OutData_KeyIndex); + + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub (uint32_t * OutData_KeyIndex) +{ + FSP_PARAMETER_NOT_USED(OutData_KeyIndex); + + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub (uint32_t * OutData_KeyIndex) +{ + FSP_PARAMETER_NOT_USED(OutData_KeyIndex); + + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + FSP_PARAMETER_NOT_USED(InData_Cmd); + FSP_PARAMETER_NOT_USED(InData_KeyIndex); + FSP_PARAMETER_NOT_USED(InData_IV); + + return FSP_ERR_UNSUPPORTED; +} + +void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(InData_Text); + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(MAX_CNT); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub (void) +{ + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + InputData_KeyType = *(InData_KeyType); + + if (InputData_KeyType != 0U) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + InputData_Cmd = *(InData_Cmd); + + memcpy(InputData_KeyIndex, InData_KeyIndex, sizeof(InputData_KeyIndex[0]) * 16U); + + memcpy(InputData_IV, InData_IV, sizeof(InputData_IV)); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + switch (change_endian_long(InputData_Cmd)) + { + case SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION: + { + HW_SCE_AES_128EcbEncrypt((uint32_t *) &InputData_KeyIndex[0], MAX_CNT, InData_Text, OutData_Text); + break; + } + + case SCE_AES_IN_DATA_CMD_ECB_DECRYPTION: + { + HW_SCE_AES_128EcbDecrypt((uint32_t *) &InputData_KeyIndex[0], MAX_CNT, InData_Text, OutData_Text); + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION: + { + HW_SCE_AES_128CbcEncrypt((uint32_t *) &InputData_KeyIndex[0], + &InputData_IV[0], + MAX_CNT, + InData_Text, + OutData_Text, + &InputData_IV[0]); + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_DECRYPTION: + { + HW_SCE_AES_128CbcDecrypt((uint32_t *) &InputData_KeyIndex[0], + &InputData_IV[0], + MAX_CNT, + InData_Text, + OutData_Text, + &InputData_IV[0]); + break; + } + + case SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION: + { + HW_SCE_AES_128CtrEncrypt((uint32_t *) &InputData_KeyIndex[0], + &InputData_IV[0], + MAX_CNT, + InData_Text, + OutData_Text, + &InputData_IV[0]); + break; + } + } +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub (void) +{ + memset(InputData_KeyIndex, 0U, sizeof(InputData_KeyIndex)); + memset(InputData_IV, 0U, sizeof(InputData_IV)); + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + InputData_KeyType = *(InData_KeyType); + if (InputData_KeyType != 0U) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + InputData_Cmd = *(InData_Cmd); + + memcpy(InputData_KeyIndex, InData_KeyIndex, sizeof(InputData_KeyIndex[0]) * 32U); + memcpy(InputData_IV, InData_IV, sizeof(InputData_IV)); + + return FSP_SUCCESS; +} + +void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + switch (change_endian_long(InputData_Cmd)) + { + case SCE_AES_IN_DATA_CMD_ECB_ENCRYPTION: + { + HW_SCE_AES_256EcbEncrypt((uint32_t *) &InputData_KeyIndex[0], MAX_CNT, InData_Text, OutData_Text); + break; + } + + case SCE_AES_IN_DATA_CMD_ECB_DECRYPTION: + { + HW_SCE_AES_256EcbDecrypt((uint32_t *) &InputData_KeyIndex[0], MAX_CNT, InData_Text, OutData_Text); + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_ENCRYPTION: + { + HW_SCE_AES_256CbcEncrypt((uint32_t *) &InputData_KeyIndex[0], + &InputData_IV[0], + MAX_CNT, + InData_Text, + OutData_Text, + &InputData_IV[0]); + break; + } + + case SCE_AES_IN_DATA_CMD_CBC_DECRYPTION: + { + HW_SCE_AES_256CbcDecrypt((uint32_t *) &InputData_KeyIndex[0], + &InputData_IV[0], + MAX_CNT, + InData_Text, + OutData_Text, + &InputData_IV[0]); + break; + } + + case SCE_AES_IN_DATA_CMD_CTR_ENCRYPTION_DECRYPTION: + { + HW_SCE_AES_256CtrEncrypt((uint32_t *) &InputData_KeyIndex[0], + &InputData_IV[0], + MAX_CNT, + InData_Text, + OutData_Text, + &InputData_IV[0]); + break; + } + } +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub (void) +{ + memset(InputData_KeyIndex, 0U, sizeof(InputData_KeyIndex)); + memset(InputData_IV, 0U, sizeof(InputData_IV)); + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes128EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_KeyMode); + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes192EncryptDecryptInitSub(InData_Cmd, InData_KeyIndex, InData_IV); +} + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSubAdaptor (const uint32_t InData_KeyMode[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_Key[], + const uint32_t InData_IV[]) +{ + FSP_PARAMETER_NOT_USED(InData_Key); + + return HW_SCE_Aes256EncryptDecryptInitSub(InData_KeyMode, InData_Cmd, InData_KeyIndex, InData_IV); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/r_sce_if.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/r_sce_if.h new file mode 100644 index 0000000000..966810b8a2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/adaptors/r_sce_if.h @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * File Name : r_sce_if.h + * Version : 1.09 + * Description : Interface definition for the r_sce module. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ + +// added for RA6M4 start +// #include "platform.h" +#include "bsp_api.h" + +// added for RA6M4 end + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +#ifndef R_SCE_IF_HEADER_FILE + #define R_SCE_IF_HEADER_FILE + + #define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) + #define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) + +/* OEM Command */ +typedef enum e_sce_oem_cmd +{ + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES192, + SCE_OEM_CMD_AES256, + SCE_OEM_CMD_AES128_XTS, + SCE_OEM_CMD_AES256_XTS, + SCE_OEM_CMD_RSA1024_PUBLIC, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA224, + SCE_OEM_CMD_HMAC_SHA256, + SCE_OEM_CMD_ECC_P256R1_PUBLIC, + SCE_OEM_CMD_ECC_P256R1_PRIVATE, + SCE_OEM_CMD_ECC_P384R1_PUBLIC, + SCE_OEM_CMD_ECC_P384R1_PRIVATE, + SCE_OEM_CMD_ECC_P512R1_PUBLIC, + SCE_OEM_CMD_ECC_P512R1_PRIVATE, + SCE_OEM_CMD_ECC_SECP256K1_PUBLIC, + SCE_OEM_CMD_ECC_SECP256K1_PRIVATE, + SCE_OEM_CMD_NUM +} sce_oem_cmd_t; + +typedef enum e_sce_oem_key_type +{ + SCE_OEM_KEY_TYPE_ENCRYPTED = 0, + SCE_OEM_KEY_TYPE_PLAIN = 1 +} sce_oem_key_type_t; + +#endif /* R_SCE_IF_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/sc324_aes_private.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/sc324_aes_private.c new file mode 100644 index 0000000000..d56f93e183 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/sc324_aes_private.c @@ -0,0 +1,250 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "sc324_aes_private.h" +#include "hw_sce_private.h" +#include "hw_sce_aes_private.h" + +__STATIC_INLINE void hw_sc324_aes_kernel_module_enable () +{ + R_AES->AESMOD_b.MODEN = 1; +} + +__STATIC_INLINE void hw_sc324_aes_kernel_module_disable () +{ + R_AES->AESMOD_b.MODEN = 0; +} + +__STATIC_INLINE void hw_sc324_aes_kernel_wait_com_write_ready () +{ + // wait for com_write_ready + while (R_AES->AESCMD_b.CWRDY == 0) + { + ; + } +} + +__STATIC_INLINE void hw_sc324_aes_kernel_inverse_cipher_set (hw_sc324_aes_encrypt_flag_t flag) +{ + // wait for com_write_ready + hw_sc324_aes_kernel_wait_com_write_ready(); + + // set the inverse_cipher mode to encrypt + R_AES->AESCMD_b.INVCIP = flag; +} + +__STATIC_INLINE void hw_sc324_aes_kernel_chaining_mode_set (hw_sc324_aes_modes_t aes_chaining_mode) +{ + // wait for com_write_ready + hw_sc324_aes_kernel_wait_com_write_ready(); + R_AES->AESCMD_b.CHAIN = aes_chaining_mode; +} + +static void hw_sc324_aes_endian_convert (uint32_t * p_dest, const uint32_t * p_source, uint32_t num_words) +{ + uint32_t nw; + for (nw = 0; nw < num_words; nw++) + { + p_dest[nw] = __REV(p_source[nw]); + } +} + +static void hw_sc324_aes_kernel_key_set (const uint32_t * p_key, hw_sc324_aes_keysizes_t key_length) +{ + uint32_t temp[4]; + + // wait for com_write_ready + hw_sc324_aes_kernel_wait_com_write_ready(); + + // set the key_length + R_AES->AESCMD_b.KEYLN = key_length; + + // wait for key_write_ready0 + while (R_AES->AESCMD_b.KWRDY0 == 0) + { + ; + } + + hw_sc324_aes_endian_convert(temp, (uint32_t *) p_key, 4); + R_AES->AESKW0 = temp[0]; + R_AES->AESKW0 = temp[1]; + R_AES->AESKW0 = temp[2]; + R_AES->AESKW0 = temp[3]; + + if (key_length == SC324_AES_KEYSIZE_128) + { + return; + } + + // wait for key_write_ready1 + while (R_AES->AESCMD_b.KWRDY1 == 0) + { + ; + } + + hw_sc324_aes_endian_convert(temp, (uint32_t *) p_key + 4, 4); + R_AES->AESKW1 = temp[0]; + R_AES->AESKW1 = temp[1]; + R_AES->AESKW1 = temp[2]; + R_AES->AESKW1 = temp[3]; +} + +static void hw_sc324_aes_kernel_iv_set (const uint32_t * p_iv) +{ + uint32_t temp[4]; + + // wait for iv_write_ready + while (R_AES->AESCMD_b.IWRDY == 0) + { + ; + } + + hw_sc324_aes_endian_convert(temp, p_iv, 4); + R_AES->AESIVW = temp[0]; + R_AES->AESIVW = temp[1]; + R_AES->AESIVW = temp[2]; + R_AES->AESIVW = temp[3]; +} + +static void hw_sc324_aes_kernel_iv_get (uint32_t * p_iv) +{ + uint32_t temp[4]; + + // wait for iv_read_ready + while (R_AES->AESCMD_b.IRRDY == 0) + { + ; + } + + temp[0] = R_AES->AESIVW; + temp[1] = R_AES->AESIVW; + temp[2] = R_AES->AESIVW; + temp[3] = R_AES->AESIVW; + + hw_sc324_aes_endian_convert(p_iv, temp, 4); +} + +static void hw_sc324_aes_kernel_data_write (const uint32_t * p_data) +{ + uint32_t temp[4]; + + // wait for write_ready + while (R_AES->AESCMD_b.DWRDY == 0) + { + ; + } + + hw_sc324_aes_endian_convert(temp, (uint32_t *) p_data, 4); + R_AES->AESDW = temp[0]; + R_AES->AESDW = temp[1]; + R_AES->AESDW = temp[2]; + R_AES->AESDW = temp[3]; +} + +static void hw_sc324_aes_kernel_data_read (uint32_t * p_data) +{ + uint32_t temp[4]; + + // wait for read_ready + while (R_AES->AESCMD_b.DRRDY == 0) + { + ; + } + + temp[0] = R_AES->AESDW; + temp[1] = R_AES->AESDW; + temp[2] = R_AES->AESDW; + temp[3] = R_AES->AESDW; + hw_sc324_aes_endian_convert(p_data, temp, 4); +} + +/*******************************************************************************************************************//** + * Helper routine to process AES encryption and Decryption. + * + * @param p_ctrl The control + * @param[in] InData_Key In data key + * @param[in] InData_IV In data iv + * @param[in] num_words The number words + * @param[in] InData_Text In data text + * @param OutData_Text The out data text + * @param OutData_IV The out data iv + * + * @retval FSP_SUCCESS The operation completed successfully. + * @retval FSP_ERR_CRYPTO_INVALID_SIZE The size of the data must be multiples of 4 WORDS / 16 bytes. + * + **********************************************************************************************************************/ +fsp_err_t hw_sc324_aes_kernel_process_data (hw_sc324_aes_ctrl_t * p_ctrl, + const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV) +{ + // truncate the number of words to process to multiples of 16 bytes (1 block of data) + if ((0 == num_words) || (0 != (num_words % SIZE_AES_BLOCK_WORDS))) + { + return FSP_ERR_CRYPTO_INVALID_SIZE; + } + + // 1. Enable AES Module (set the AESMOD.module_en to 1) + hw_sc324_aes_kernel_module_enable(); + + // 2. Write the key to key_register0 or key_register1 + // When writing to the key-register0, write 1 word (32 bits) to AESKW0 + // after confirmation of key_write_ready0 = 1 + // When writing to the key-register1, write 1 word (32 bits) to AESKW1 + // after confirmation of key_write_ready1 = 1 + hw_sc324_aes_kernel_key_set(InData_Key, p_ctrl->keysize); + + // 3. In CBC or CTR mode, write IV data to iv-register + // When writing to iv-register, you must write the whole 4 words of data. + hw_sc324_aes_kernel_chaining_mode_set(p_ctrl->mode); + if (InData_IV) + { + hw_sc324_aes_kernel_iv_set(InData_IV); + } + + // 4. Write the setting data to AESCMD + // When writing to the AESCMD, check if the AESCMD.com_write_ready is 1 + hw_sc324_aes_kernel_inverse_cipher_set(p_ctrl->encrypt_flag); + + for (uint32_t indx = 0; indx < num_words; indx += SIZE_AES_BLOCK_WORDS) + { + // 5. Write data to data-register (one block (128 bits) of data). + // When writing to data-register, write 1 word (32 bits) to AESDW after confirmation of write_ready=1 + // When you write to the data-register, you write the whole 4 words of data. + hw_sc324_aes_kernel_data_write(InData_Text + indx); + + // 6. When encrypt (decrypt) is completed, read_ready will be 1. The read_request will be asserted + // and you will be able to read the data on which encrypt (decrypt) was done. Please read + // 1 word (32 bits) from AESDW. + // When reading iv_data, read 1 word (32 bits) from AESIVW after confirmation of iv_read_ready=1 + // When you read the iv-window, you must read the whole 4 words of data. + hw_sc324_aes_kernel_data_read(OutData_Text + indx); + + // 7. When encrypt (decrypt) is completed, write_ready will be 1. The write_request will be + // asserted. When continuing encrypting (decrypting), write 1 block of data (128 bits) to + // data-register. + // When you write to the data-window, you must write the whole 4 words of data. + // When writing to data-register, write 1 word (32 bits) to AESDW after confirmation of write_ready=1 + continue; + } + + if (OutData_IV) + { + hw_sc324_aes_kernel_iv_get(OutData_IV); + } + + // 8. When ending use of a AES module, please write 0 to mode-register.module_en + hw_sc324_aes_kernel_module_disable(); + + return FSP_SUCCESS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/sc324_aes_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/sc324_aes_private.h new file mode 100644 index 0000000000..3352096606 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/ra2/sc324_aes_private.h @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef SC324_AES_PRIVATE_H +#define SC324_AES_PRIVATE_H + +#include +#include "bsp_api.h" + +typedef enum e_hw_sc324_aes_modes +{ + SC324_AES_ECB = 0, + SC324_AES_CBC = 1, + SC324_AES_CTR = 2, +} hw_sc324_aes_modes_t; + +typedef enum e_hw_sc324_aes_keysize +{ + SC324_AES_KEYSIZE_128 = 0, + SC324_AES_KEYSIZE_256 = 1 +} hw_sc324_aes_keysizes_t; + +typedef enum e_hw_sc324_aes_encrypt_flag +{ + SC324_AES_ENCRYPT = 0, + SC324_AES_DECRYPT = 1 +} hw_sc324_aes_encrypt_flag_t; + +typedef struct st_hw_sc324_aes_cfg +{ + hw_sc324_aes_keysizes_t keysize; + hw_sc324_aes_modes_t mode; +} hw_sc324_aes_cfg_t; + +typedef struct st_hw_sc324_aes_ctrl +{ + hw_sc324_aes_keysizes_t keysize; + hw_sc324_aes_modes_t mode; + hw_sc324_aes_encrypt_flag_t encrypt_flag; +} hw_sc324_aes_ctrl_t; + +fsp_err_t hw_sc324_aes_kernel_process_data(hw_sc324_aes_ctrl_t * p_ctrl, + const uint32_t * InData_Key, + const uint32_t * InData_IV, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_IV); + +#endif /* SC324_AES_PRIVATE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/hw_sce_ra_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/hw_sce_ra_private.h new file mode 100644 index 0000000000..244d7f8416 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/hw_sce_ra_private.h @@ -0,0 +1,33 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ +#ifndef HW_SCE_RA_PRIVATE_HEADER_FILE +#define HW_SCE_RA_PRIVATE_HEADER_FILE + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions + *********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + ***********************************************************************************************************************/ + +#endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_if.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_if.h new file mode 100644 index 0000000000..fbed2cf763 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_if.h @@ -0,0 +1,66 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ + +#include "bsp_api.h" + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +#ifndef R_SCE_IF_HEADER_FILE + #define R_SCE_IF_HEADER_FILE + + #define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) + #define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) + +/* OEM Command */ +typedef enum e_sce_oem_cmd +{ + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES192, + SCE_OEM_CMD_AES256, + SCE_OEM_CMD_AES128_XTS, + SCE_OEM_CMD_AES256_XTS, + SCE_OEM_CMD_RSA1024_PUBLIC, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA224, + SCE_OEM_CMD_HMAC_SHA256, + SCE_OEM_CMD_ECC_P256R1_PUBLIC, + SCE_OEM_CMD_ECC_P256R1_PRIVATE, + SCE_OEM_CMD_ECC_P384R1_PUBLIC, + SCE_OEM_CMD_ECC_P384R1_PRIVATE, + SCE_OEM_CMD_ECC_P512R1_PUBLIC, + SCE_OEM_CMD_ECC_P512R1_PRIVATE, + SCE_OEM_CMD_ECC_SECP256K1_PUBLIC, + SCE_OEM_CMD_ECC_SECP256K1_PRIVATE, + SCE_OEM_CMD_NUM +} sce_oem_cmd_t; + +typedef enum e_sce_oem_key_type +{ + SCE_OEM_KEY_TYPE_ENCRYPTED = 0, + SCE_OEM_KEY_TYPE_PLAIN = 1 +} sce_oem_key_type_t; + +#endif /* R_SCE_IF_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_trng.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_trng.c new file mode 100644 index 0000000000..d149f80090 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_trng.c @@ -0,0 +1,41 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "hw_sce_trng_private.h" + +/*******************************************************************************************************************//** + * 128bit Random Number Generation + * @param OutData_Text The out data text + * @retval FSP_SUCCESS The operation completed successfully. + **********************************************************************************************************************/ +fsp_err_t HW_SCE_RNG_Read (uint32_t * OutData_Text) { + uint8_t * ptmp = (uint8_t *) OutData_Text; + uint32_t k; + for (k = 0; k < 4; k++) // read 4 words of random data similar (to make this API consistent with S7 and S3 implementation) + { + /* Set SGCEN bit and SGSTART bit */ + R_TRNG->TRNGSCR0_b.SGCEN = 1; + R_TRNG->TRNGSCR0_b.SGSTART = 1; + + /* Wait for RDRDY bit to be set */ + while (0 == R_TRNG->TRNGSCR0_b.RDRDY) + { + } + + /* Read generated random data */ + *ptmp++ = R_TRNG->TRNGSDR; + *ptmp++ = R_TRNG->TRNGSDR; + *ptmp++ = R_TRNG->TRNGSDR; + *ptmp++ = R_TRNG->TRNGSDR; + } + + return FSP_SUCCESS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_utils.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_utils.c new file mode 100644 index 0000000000..a64f836c8e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce/trng/r_sce_utils.c @@ -0,0 +1,20 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#include "bsp_api.h" +#include "hw_sce_private.h" + +/*******************************************************************************************************************//** + * Initialize the crypto engine + * @retval FSP_SUCCESS The operation completed successfully. + **********************************************************************************************************************/ + +fsp_err_t HW_SCE_McuSpecificInit (void) +{ + // power on the SCE module + HW_SCE_PowerOn(); + + return FSP_SUCCESS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h new file mode 100644 index 0000000000..3674f007a6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h @@ -0,0 +1,2196 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SECURITY_INTERFACES + * @defgroup SCE_PROTECTED_API SCE Interface + * @brief Interface for Secure Crypto Engine (SCE) functions. + * + * @section SCE_PROTECTED_API_Summary Summary + * The SCE interface provides SCE functionality. + * + * The SCE interface can be implemented by: + * - @ref SCE_PROTECTED + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_SCE_API_H +#define R_SCE_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* For AES operation. */ +#define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (9U) +#define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (13U) +#define HW_SCE_AES128_KEY_WORD_SIZE (4U) +#define HW_SCE_AES256_KEY_WORD_SIZE (8U) +#define HW_SCE_AES128_KEY_BYTE_SIZE (16U) +#define HW_SCE_AES256_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_BLOCK_BIT_SIZE (128U) +#define HW_SCE_AES_CBC_IV_BYTE_SIZE (16U) +#define HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE (128U) +#define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) + +/* For SHA operation. */ +#define HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE (32U) +#define HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE (48U) + +/* For HMAC operation. */ +#define HW_SCE_HMAC_KEY_INDEX_BYTE_SIZE (52U) +#define HW_SCE_HMAC_KEY_INDEX_WORD_SIZE (13U) +#define HW_SCE_HMAC_SHA256_KEY_BYTE_SIZE (32U) + +/* For RSA operation. */ +#define HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_1024_KEY_D_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_2048_KEY_D_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_3072_KEY_D_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_4096_KEY_D_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (36U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) +#define HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE (12U) +#define HW_SCE_RSA1024_NE_KEY_BYTE_SIZE (144U) +#define HW_SCE_RSA1024_ND_KEY_BYTE_SIZE (256U) +#define HW_SCE_RSA2048_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_RSA2048_ND_KEY_BYTE_SIZE (512U) +#define HW_SCE_RSA3072_NE_KEY_BYTE_SIZE (96 * 4 + 16U) +#define HW_SCE_RSA3072_ND_KEY_BYTE_SIZE (192 * 4U) +#define HW_SCE_RSA4096_NE_KEY_BYTE_SIZE (128 * 4 + 16U) +#define HW_SCE_RSA4096_ND_KEY_BYTE_SIZE (256 * 4U) +#define HW_SCE_RSA1024_NE_KEY_INDEX_WORD_SIZE (73U) +#define HW_SCE_RSA1024_ND_KEY_INDEX_WORD_SIZE (101U) +#define HW_SCE_RSA2048_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA2048_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA3072_NE_KEY_INDEX_WORD_SIZE (105U) +#define HW_SCE_RSA3072_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA4096_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA4096_ND_KEY_INDEX_WORD_SIZE (261U) +#define HW_SCE_RSA1024_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (73U) +#define HW_SCE_RSA1024_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (101U) +#define HW_SCE_RSA2048_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA2048_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (197U) + +#define HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE (11U) +#define HW_SCE_RSA_1024_DATA_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_DATA_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_DATA_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_DATA_BYTE_SIZE (128 * 4U) + +/* RSA HASH type. */ +#define HW_SCE_RSA_HASH_SHA256 (0x03) /* SHA-256 */ + +/* For ECC operation. */ +#define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (112U) +#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE (1U) +#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (17U) +#define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) +#define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) +#define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) +#define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) +#define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) +#define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) +#define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (13U) + +/* Key update. */ +#define HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE (16U) + +#define SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0) +#define SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD (8) +#define SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD (12) + +#define SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD (40) +#define SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD (68) +#define SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD (72) +#define SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132) +#define SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD (104) +#define SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD (196) +#define SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD (136) +#define SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD (260) + +#define SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD (12) + +/* For TLS. */ +#define SCE_TLS_RSA_NE_KEY_BYTE_SIZE (272U) +#define SCE_TLS_RSA_NE_KEY_INDEX_WORD_SIZE (140U) +#define SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE (137U) +#define SCE_TLS_P256_ECC_KEY_WORD_SIZE (16U) +#define SCE_TLS_EPHEMERAL_ECDH_PUBLIC_KEY_WORD_SIZE (16U) +#define SCE_TLS_MASTER_SECRET_WORD_SIZE (20U) +#define SCE_TLS_GENERATE_MAC_KEY_WORD_SIZE (16U) +#define SCE_TLS_GENERATE_AES128_CRYPTO_KEY_WORD_SIZE (12U) +#define SCE_TLS_GENERATE_AES256_CRYPTO_KEY_WORD_SIZE (16U) +#define SCE_TLS_GENERATE_VERIFY_DATA_BYTE_SIZE (12U) +#define SCE_TLS_RSA_WITH_AES_128_CBC_SHA (0U) +#define SCE_TLS_RSA_WITH_AES_256_CBC_SHA (1U) +#define SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 (2U) +#define SCE_TLS_RSA_WITH_AES_256_CBC_SHA256 (3U) +#define SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (4U) +#define SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (5U) +#define SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (6U) +#define SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (7U) +#define SCE_TLS_GENERATE_CLIENT_VERIFY (0U) +#define SCE_TLS_GENERATE_SERVER_VERIFY (1U) +#define SCE_TLS_PUBLIC_KEY_TYPE_RSA2048 (0U) +#define SCE_TLS_PUBLIC_KEY_TYPE_ECDSA_P256 (2U) + +/* TLS-HMAC. */ +#define SCE_TLS_HMAC_KEY_INDEX_BYTE_SIZE (64U) +#define SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE (16U) + +/* TLS-AES. */ +#define SCE_TLS_AES128_KEY_INDEX_WORD_SIZE (12U) +#define SCE_TLS_AES256_KEY_INDEX_WORD_SIZE (16U) + +#define SCE_INSTALL_KEY_RING_INDEX (0) /* 0-15 */ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Byte data structure */ +typedef struct sce_byte_data +{ + uint8_t * pdata; ///< pointer + uint32_t data_length; ///< data_length + uint32_t data_type; ///< data type +} sce_byte_data_t; + +/** RSA byte data structure */ +typedef sce_byte_data_t sce_rsa_byte_data_t; ///< byte data + +/** ECDSA byte data structure */ +typedef sce_byte_data_t sce_ecdsa_byte_data_t; ///< byte data + +/** AES wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_aes_wrapped_key +{ + uint32_t type; ///< key type + + /* AES128, AES256 are supported */ + uint32_t value[SCE_TLS_AES256_KEY_INDEX_WORD_SIZE]; ///< wrapped key value
@note The size of the "value" array and the definition name depends on the used SCE. See the header file for detail. +} sce_aes_wrapped_key_t; + +/** HMAC-SHA wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_hmac_sha_wrapped_key +{ + uint32_t type; ///< key type + + /* HMAC-SHA256 is supported */ + uint32_t value[SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE]; ///< wrapped key value +} sce_hmac_sha_wrapped_key_t; + +/** RSA 1024bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa1024_public_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 1024-bit public key n (plaintext) + uint8_t key_e[HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE]; ///< RSA 1024-bit public key e (plaintext) + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; ///< dummy + uint32_t key_management_info2[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa1024_public_wrapped_key_t; + +/** RSA 1024bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa1024_private_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 1024-bit private key n (plaintext) + uint32_t key_management_info2[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa1024_private_wrapped_key_t; + +/** RSA 2048bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa2048_public_wrapped_key +{ + uint32_t type; ///< Key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 2048-bit public key n (plaintext) + uint8_t key_e[HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE]; ///< RSA 2048-bit public key e (plaintext) + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; ///< dummy + uint32_t key_management_info2[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa2048_public_wrapped_key_t; + +/** RSA 2048bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa2048_private_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 2048-bit private key n (plaintext) + uint32_t key_management_info2[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa2048_private_wrapped_key_t; + +/** RSA 3072bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa3072_public_wrapped_key +{ + uint32_t type; ///< Key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 3072-bit public key n (plaintext) + uint8_t key_e[HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE]; ///< RSA 3072-bit public key e (plaintext) + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; ///< dummy + uint32_t key_management_info2[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa3072_public_wrapped_key_t; + +/** RSA 4096bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa4096_public_wrapped_key +{ + uint32_t type; ///< Key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 4096-bit public key n (plaintext) + uint8_t key_e[HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE]; ///< RSA 4096-bit public key e (plaintext) + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; ///< dummy + uint32_t key_management_info2[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa4096_public_wrapped_key_t; + +/** RSA 1024bit wrapped key pair structure. DO NOT MODIFY. */ +typedef struct sce_rsa1024_wrapped_pair_key +{ + sce_rsa1024_private_wrapped_key_t priv_key; ///< RSA 1024-bit private wrapped key + sce_rsa1024_public_wrapped_key_t pub_key; ///< RSA 1024-bit public wrapped key +} sce_rsa1024_wrapped_pair_key_t; + +/** RSA 2048bit wrapped key pair structure. DO NOT MODIFY. */ +typedef struct sce_rsa2048_wrapped_pair_key +{ + sce_rsa2048_private_wrapped_key_t priv_key; ///< RSA 2048-bit private wrapped key + sce_rsa2048_public_wrapped_key_t pub_key; ///< RSA 2048-bit public wrapped key +} sce_rsa2048_wrapped_pair_key_t; + +/** ECC P-192/224/256 public wrapped key data structure */ +typedef struct sce_ecc_public_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE]; ///< key management information + uint8_t key_q[HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE]; ///< ECC public key Q (plaintext) + } value; +} sce_ecc_public_wrapped_key_t; + +/** ECC P-192/224/256 private wrapped key data structure */ +typedef struct sce_ecc_private_wrapped_key +{ + uint32_t type; ///< key type + uint32_t value[HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE]; ///< wrapped key value +} sce_ecc_private_wrapped_key_t; + +/** ECC P-192/224/256 wrapped key pair structure */ +typedef struct sce_ecc_wrapped_pair_key +{ + sce_ecc_private_wrapped_key_t priv_key; ///< ECC private wrapped key + sce_ecc_public_wrapped_key_t pub_key; ///< ECC public wrapped key +} sce_ecc_wrapped_pair_key_t; + +/** ECDH wrapped key data structure */ +typedef struct sce_ecdh_wrapped_key +{ + uint32_t type; ///< key type + uint32_t value[HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE]; ///< wrapped key value +} sce_ecdh_wrapped_key_t; + +/* TLS CA certification public key index data structure */ +typedef struct sce_tls_ca_certification_public_wrapped_key +{ + uint32_t type; + uint32_t value[SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE]; +} sce_tls_ca_certification_public_wrapped_key_t; + +/* TLS P-256 ECC key index data structure */ +typedef struct sce_tls_p256_ecc_wrapped_key +{ + uint32_t type; + uint32_t value[SCE_TLS_P256_ECC_KEY_WORD_SIZE]; +} sce_tls_p256_ecc_wrapped_key_t; + +/** Update key ring index data structure. DO NOT MODIFY. */ +typedef struct sce_key_update_key +{ + uint32_t type; ///< key type + uint32_t value[HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE]; ///< wrapped key value
@note The size of the "value" array and the definition name depends on the used SCE. See the header file for detail. +} sce_key_update_key_t; + +/** The work area for AES. DO NOT MODIFY. */ +typedef struct sce_aes_handle +{ + uint32_t id; ///< serial number of this handle + sce_aes_wrapped_key_t wrapped_key; ///< wrapped key + uint32_t current_input_data_size; ///< text size under encryption / decryption + uint8_t last_1_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE]; ///< text array less than the block long + uint8_t last_2_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; ///< reserved + uint8_t current_initial_vector[HW_SCE_AES_CBC_IV_BYTE_SIZE]; ///< current initialization vector used in CBC mode + uint8_t flag_call_init; ///< control flag of calling function +} sce_aes_handle_t; + +/** The work area for GCM. DO NOT MODIFY. */ +typedef struct sce_gcm_handle +{ + uint32_t id; ///< serial number of this handle + sce_aes_wrapped_key_t wrapped_key; ///< wrapped key + uint8_t gcm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; ///< text array less than the block long + uint8_t gcm_aad_buffer[HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE]; ///< AAD array less than the block long + uint32_t all_received_length; ///< entire length of text + uint32_t all_received_aad_length; ///< entire length of text + uint32_t buffering_length; ///< text array length less than the block long + uint32_t buffering_aad_length; ///< AAD array length less than the block long + uint8_t flag_call_init; ///< control flag of calling function + uint8_t flag_update_input_data; ///< control flag of next input data +} sce_gcm_handle_t; + +/** The work area for CCM. DO NOT MODIFY. */ +typedef struct sce_ccm_handle +{ + uint32_t id; ///< serial number of this handle + sce_aes_wrapped_key_t wrapped_key; ///< wrapped key + uint8_t formatted_data[HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE]; ///< formatted data area + uint8_t counter[HW_SCE_AES_CCM_COUNTER_BYTE_SIZE]; ///< counter of CTR mode + uint8_t ccm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; ///< text array less than the block long + uint32_t all_received_length; ///< entire length of text + uint32_t buffering_length; ///< text array length less than the block long + uint8_t flag_call_init; ///< control flag of calling function +} sce_ccm_handle_t; + +/** The work area for CMAC. DO NOT MODIFY. */ +typedef struct sce_cmac_handle +{ + uint32_t id; ///< serial number of this handle + sce_aes_wrapped_key_t wrapped_key; ///< wrapped key + uint8_t cmac_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; ///< message array less than the block long + uint32_t all_received_length; ///< entire length of message + uint32_t buffering_length; ///< message array length less than the block long + uint8_t flag_call_init; ///< control flag of calling function +} sce_cmac_handle_t; + +/** The work area for SHA. DO NOT MODIFY. */ +typedef struct sce_sha_md5_handle +{ + uint32_t id; ///< serial number of this handle + uint8_t sha_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; ///< message array length less than the block long + uint32_t all_received_length; ///< entire length of message + uint32_t buffering_length; ///< message array length less than the block long + + /* SHA1(20byte), SHA256(32byte), MD5(16byte) are supported */ + uint8_t current_hash[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE]; ///< last hash value + uint8_t flag_call_init; ///< control flag of calling function +} sce_sha_md5_handle_t; + +/** The work area for HMAC-SHA. DO NOT MODIFY. */ +typedef struct sce_hmac_sha_handle +{ + uint32_t id; ///< serial number of this handle + sce_hmac_sha_wrapped_key_t wrapped_key; ///< wrapped key + uint8_t hmac_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; ///< message array length less than the block long + uint32_t all_received_length; ///< entire length of message + uint32_t buffering_length; ///< message array length less than the block long + uint8_t flag_call_init; ///< control flag of calling function +} sce_hmac_sha_handle_t; + +/** The work area for ECDH */ +typedef struct sce_ecdh_handle +{ + uint32_t id; ///< serial number of this handle + uint32_t flag_use_key_id; ///< control frag that the key_id has already used or not + uint32_t key_id; ///< serial number of the wrapped key + uint32_t key_type; ///< key type + uint8_t flag_call_init; ///< control flag of calling function + uint8_t flag_call_make_public; ///< control flag of calling function + uint8_t flag_call_read_public; ///< control flag of calling function + uint8_t flag_call_shared_secret; ///< control flag of calling function +} sce_ecdh_handle_t; + +/** SCE Control block. Allocate an instance specific control block to pass into the API calls. + * @par Implemented as + * - sce_instance_ctrl_t + */ +typedef void sce_ctrl_t; + +/** User configuration structure, used in open function */ +typedef struct st_sce_cfg +{ + /* No structure members */ +} sce_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_sce_api +{ + /** Enables use of SCE functionality. + * @par Implemented as + * - @ref R_SCE_Open() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + + /***** TODO: Replace "struct st_sce_ctrl" to "void" *****/ + fsp_err_t (* open)(sce_ctrl_t * const p_ctrl, sce_cfg_t const * const p_cfg); + + /** Stops supply of power to the SCE. + * @par Implemented as + * - @ref R_SCE_Close() + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(sce_ctrl_t * const p_ctrl); + + /** Software reset to SCE. + * @par Implemented as + * - @ref R_SCE_SoftwareReset() + * + */ + fsp_err_t (* softwareReset)(void); + + /** Generates 4 words random number. + * @par Implemented as + * - @ref R_SCE_RandomNumberGenerate() + * + * @param[in,out] random Stores 4words (16 bytes) random data. + */ + fsp_err_t (* randomNumberGenerate)(uint32_t * random); + + /** This API outputs 128-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES128_WrappedKeyGenerate() + * + * @param[in,out] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128_WrappedKeyGenerate)(sce_aes_wrapped_key_t * wrapped_key); + + /** This API outputs 256-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES256_WrappedKeyGenerate() + * + * @param[in,out] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256_WrappedKeyGenerate)(sce_aes_wrapped_key_t * wrapped_key); + + /** This API outputs 128-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES128_EncryptedKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128_EncryptedKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, sce_aes_wrapped_key_t * wrapped_key); + + /** This API outputs 256-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES256_EncryptedKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256_EncryptedKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, sce_aes_wrapped_key_t * wrapped_key); + + /** This API outputs 128-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES128_RFC3394KeyWrap() + * + * @param[in] master_key AES-128 key used for wrapping. + * @param[in] target_key_type Selects key to be wrapped. + * @param[in] target_key Key to be wrapped. + * @param[out] rfc3394_wrapped_key Wrapped key. + */ + fsp_err_t (* AES128_RFC3394KeyWrap)(sce_aes_wrapped_key_t * master_key, uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, uint32_t * rfc3394_wrapped_key); + + /** This API outputs 256-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES256_RFC3394KeyWrap() + * + * @param[in] master_key AES-256 key used for wrapping. + * @param[in] target_key_type Selects key to be wrapped. + * @param[in] target_key Key to be wrapped. + * @param[out] rfc3394_wrapped_key Wrapped key. + */ + fsp_err_t (* AES256_RFC3394KeyWrap)(sce_aes_wrapped_key_t * master_key, uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, uint32_t * rfc3394_wrapped_key); + + /** This API outputs 128-bit AES unwrapped key. + * @par Implemented as + * - @ref R_SCE_AES128_RFC3394KeyUnwrap() + * + * @param[in] master_key AES-128 key used for unwrapping. + * @param[in] target_key_type Selects key to be unwrapped. + * @param[in] rfc3394_wrapped_key Wrapped key. + * @param[out] target_key Key to be unwrapped. + */ + fsp_err_t (* AES128_RFC3394KeyUnwrap)(sce_aes_wrapped_key_t * master_key, uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, sce_aes_wrapped_key_t * target_key); + + /** This API outputs 256-bit AES unwrapped key. + * @par Implemented as + * - @ref R_SCE_AES256_RFC3394KeyUnwrap() + * + * @param[in] master_key AES-256 key used for unwrapping. + * @param[in] target_key_type Selects key to be unwrapped. + * @param[in] rfc3394_wrapped_key Wrapped key. + * @param[out] target_key Key to be unwrapped. + */ + fsp_err_t (* AES256_RFC3394KeyUnwrap)(sce_aes_wrapped_key_t * master_key, uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, sce_aes_wrapped_key_t * target_key); + + /** Initialize AES128ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_EncryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128ECB_EncryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES128ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_EncryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + */ + fsp_err_t (* AES128ECB_EncryptUpdate)(sce_aes_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES128ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_EncryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + */ + fsp_err_t (* AES128ECB_EncryptFinal)(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); + + /** Initialize AES128ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_DecryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128ECB_DecryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES128ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_DecryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + */ + fsp_err_t (* AES128ECB_DecryptUpdate)(sce_aes_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES128ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_DecryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + */ + fsp_err_t (* AES128ECB_DecryptFinal)(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + + /** Initialize AES256ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_EncryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256ECB_EncryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES256ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_EncryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + */ + fsp_err_t (* AES256ECB_EncryptUpdate)(sce_aes_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES256ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_EncryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + */ + fsp_err_t (* AES256ECB_EncryptFinal)(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); + + /** Initialize AES256ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_DecryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256ECB_DecryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES256ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_DecryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + */ + fsp_err_t (* AES256ECB_DecryptUpdate)(sce_aes_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES256ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_DecryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + */ + fsp_err_t (* AES256ECB_DecryptFinal)(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + + /** Initialize AES128CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_EncryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + */ + fsp_err_t (* AES128CBC_EncryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); + + /** Update AES128CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_EncryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + */ + fsp_err_t (* AES128CBC_EncryptUpdate)(sce_aes_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES128CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_EncryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + */ + fsp_err_t (* AES128CBC_EncryptFinal)(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); + + /** Initialize AES128CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_DecryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + */ + fsp_err_t (* AES128CBC_DecryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); + + /** Update AES128CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_DecryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + */ + fsp_err_t (* AES128CBC_DecryptUpdate)(sce_aes_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES128CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_DecryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + */ + fsp_err_t (* AES128CBC_DecryptFinal)(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + + /** Initialize AES256CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_EncryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + */ + fsp_err_t (* AES256CBC_EncryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); + + /** Update AES256CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_EncryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + */ + fsp_err_t (* AES256CBC_EncryptUpdate)(sce_aes_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES256CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_EncryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + */ + fsp_err_t (* AES256CBC_EncryptFinal)(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); + + /** Initialize AES256CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_DecryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + */ + fsp_err_t (* AES256CBC_DecryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); + + /** Update AES256CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_DecryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + */ + fsp_err_t (* AES256CBC_DecryptUpdate)(sce_aes_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES256CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_DecryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + */ + fsp_err_t (* AES256CBC_DecryptFinal)(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + + /** Initialize AES128GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_EncryptInit() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + */ + fsp_err_t (* AES128GCM_EncryptInit)(sce_gcm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, uint32_t initial_vector_length); + + /** Update AES128GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_EncryptUpdate() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_data_length plaintext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + */ + fsp_err_t (* AES128GCM_EncryptUpdate)(sce_gcm_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_data_length, uint8_t * aad, uint32_t aad_length); + + /** Finalize AES128GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_EncryptFinal() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area (cipher_data_length byte) + * @param[in,out] cipher_data_length ciphertext data length (0 always written here) + * @param[in,out] atag authentication tag area + */ + fsp_err_t (* AES128GCM_EncryptFinal)(sce_gcm_handle_t * handle, uint8_t * cipher, uint32_t * cipher_data_length, + uint8_t * atag); + + /** Initialize AES128GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_DecryptInit() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + */ + fsp_err_t (* AES128GCM_DecryptInit)(sce_gcm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, uint32_t initial_vector_length); + + /** Update AES128GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_DecryptUpdate() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in] plain plaintext data area + * @param[in] cipher_data_length ciphertext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + */ + fsp_err_t (* AES128GCM_DecryptUpdate)(sce_gcm_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_data_length, uint8_t * aad, uint32_t aad_length); + + /** Finalize AES128GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_DecryptFinal() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] plain plaintext data area (cipher_data_length byte) + * @param[in,out] plain_data_length plaintext data length (0 always written here) + * @param[in,out] atag authentication tag area (atag_length byte) + * @param[in] atag_length authentication tag length (4,8,12,13,14,15,16 bytes) + */ + fsp_err_t (* AES128GCM_DecryptFinal)(sce_gcm_handle_t * handle, uint8_t * plain, uint32_t * plain_data_length, + uint8_t * atag, uint32_t atag_length); + + /** Initialize AES256GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_EncryptInit() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + */ + fsp_err_t (* AES256GCM_EncryptInit)(sce_gcm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, uint32_t initial_vector_length); + + /** Update AES256GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_EncryptUpdate() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_data_length plaintext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + */ + fsp_err_t (* AES256GCM_EncryptUpdate)(sce_gcm_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_data_length, uint8_t * aad, uint32_t aad_length); + + /** Finalize AES256GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_EncryptFinal() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area (cipher_data_length byte) + * @param[in,out] cipher_data_length ciphertext data length (0 always written here) + * @param[in,out] atag authentication tag area + */ + fsp_err_t (* AES256GCM_EncryptFinal)(sce_gcm_handle_t * handle, uint8_t * cipher, uint32_t * cipher_data_length, + uint8_t * atag); + + /** Initialize AES256GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_DecryptInit() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + */ + fsp_err_t (* AES256GCM_DecryptInit)(sce_gcm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, uint32_t initial_vector_length); + + /** Update AES256GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_DecryptUpdate() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in] plain plaintext data area + * @param[in] cipher_data_length ciphertext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + */ + fsp_err_t (* AES256GCM_DecryptUpdate)(sce_gcm_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_data_length, uint8_t * aad, uint32_t aad_length); + + /** Finalize AES256GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_DecryptFinal() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] plain plaintext data area (cipher_data_length byte) + * @param[in,out] plain_data_length plaintext data length (0 always written here) + * @param[in,out] atag authentication tag area (atag_length byte) + * @param[in] atag_length authentication tag length (4,8,12,13,14,15,16 bytes) + */ + fsp_err_t (* AES256GCM_DecryptFinal)(sce_gcm_handle_t * handle, uint8_t * plain, uint32_t * plain_data_length, + uint8_t * atag, uint32_t atag_length); + + /** Initialize AES128CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_EncryptInit() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES128CCM_EncryptInit)(sce_ccm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, uint8_t * nonce, + uint32_t nonce_length, uint8_t * adata, uint8_t a_length, + uint32_t payload_length, uint32_t mac_length); + + /** Update AES128CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_EncryptUpdate() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_length plaintext data length + */ + fsp_err_t (* AES128CCM_EncryptUpdate)(sce_ccm_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES128CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_EncryptFinal() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in,out] cipher_length ciphertext data length + * @param[in,out] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES128CCM_EncryptFinal)(sce_ccm_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length, + uint8_t * mac, uint32_t mac_length); + + /** Initialize AES128CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_DecryptInit() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES128CCM_DecryptInit)(sce_ccm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, uint8_t * nonce, + uint32_t nonce_length, uint8_t * adata, uint8_t a_length, + uint32_t payload_length, uint32_t mac_length); + + /** Update AES128CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_DecryptUpdate() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in] cipher_length ciphertext data length + */ + fsp_err_t (* AES128CCM_DecryptUpdate)(sce_ccm_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES128CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_DecryptFinal() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] plain plaintext data area + * @param[in,out] plain_length plaintext data length + * @param[in] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES128CCM_DecryptFinal)(sce_ccm_handle_t * handle, uint8_t * plain, uint32_t * plain_length, + uint8_t * mac, uint32_t mac_length); + + /** Initialize AES256CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_EncryptInit() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES256CCM_EncryptInit)(sce_ccm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, uint8_t * nonce, + uint32_t nonce_length, uint8_t * adata, uint8_t a_length, + uint32_t payload_length, uint32_t mac_length); + + /** Update AES256CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_EncryptUpdate() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_length plaintext data length + */ + fsp_err_t (* AES256CCM_EncryptUpdate)(sce_ccm_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES256CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_EncryptFinal() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in,out] cipher_length ciphertext data length + * @param[in,out] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES256CCM_EncryptFinal)(sce_ccm_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length, + uint8_t * mac, uint32_t mac_length); + + /** Initialize AES256CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_DecryptInit() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES256CCM_DecryptInit)(sce_ccm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, uint8_t * nonce, + uint32_t nonce_length, uint8_t * adata, uint8_t a_length, + uint32_t payload_length, uint32_t mac_length); + + /** Update AES256CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_DecryptUpdate() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in] cipher_length ciphertext data length + */ + fsp_err_t (* AES256CCM_DecryptUpdate)(sce_ccm_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES256CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_DecryptFinal() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] plain plaintext data area + * @param[in,out] plain_length plaintext data length + * @param[in] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES256CCM_DecryptFinal)(sce_ccm_handle_t * handle, uint8_t * plain, uint32_t * plain_length, + uint8_t * mac, uint32_t mac_length); + + /** Initialize AES128CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_GenerateInit() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128CMAC_GenerateInit)(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES128CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_GenerateUpdate() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + */ + fsp_err_t (* AES128CMAC_GenerateUpdate)(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize AES128CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_GenerateFinal() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (16byte) + */ + fsp_err_t (* AES128CMAC_GenerateFinal)(sce_cmac_handle_t * handle, uint8_t * mac); + + /** Initialize AES128CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_VerifyInit() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128CMAC_VerifyInit)(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES128CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_VerifyUpdate() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + */ + fsp_err_t (* AES128CMAC_VerifyUpdate)(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize AES128CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_VerifyFinal() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (mac_length byte) + * @param[in,out] mac_length MAC data length (2 to 16 bytes) + */ + fsp_err_t (* AES128CMAC_VerifyFinal)(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); + + /** Initialize AES256CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_GenerateInit() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256CMAC_GenerateInit)(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES256CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_GenerateUpdate() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + */ + fsp_err_t (* AES256CMAC_GenerateUpdate)(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize AES256CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_GenerateFinal() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (16byte) + */ + fsp_err_t (* AES256CMAC_GenerateFinal)(sce_cmac_handle_t * handle, uint8_t * mac); + + /** Initialize AES256CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_VerifyInit() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256CMAC_VerifyInit)(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES256CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_VerifyUpdate() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + */ + fsp_err_t (* AES256CMAC_VerifyUpdate)(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize AES256CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_VerifyFinal() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (mac_length byte) + * @param[in,out] mac_length MAC data length (2 to 16 bytes) + */ + fsp_err_t (* AES256CMAC_VerifyFinal)(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); + + /** Initialize SHA-256 Calculation. + * @par Implemented as + * - @ref R_SCE_SHA256_Init() + * + * @param[in,out] handle SHA handler (work area) + */ + fsp_err_t (* SHA256_Init)(sce_sha_md5_handle_t * handle); + + /** Update SHA-256 Calculation. + * @par Implemented as + * - @ref R_SCE_SHA256_Update() + * + * @param[in,out] handle SHA handler (work area) + * @param[in] message message data area + * @param[in] message_length message data length + */ + fsp_err_t (* SHA256_Update)(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize SHA-256 Calculation. + * @par Implemented as + * - @ref R_SCE_SHA256_Final() + * + * @param[in,out] handle SHA handler (work area) + * @param[in,out] digest hasha data area + * @param[in,out] digest_length hash data length (32bytes) + */ + fsp_err_t (* SHA256_Final)(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); + + /** This API outputs 1024-bit RSA wrapped pair key. + * @par Implemented as + * - @ref R_SCE_RSA1024_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* RSA1024_WrappedKeyPairGenerate)(sce_rsa1024_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs 2048-bit RSA wrapped pair key. + * @par Implemented as + * - @ref R_SCE_RSA2048_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* RSA2048_WrappedKeyPairGenerate)(sce_rsa2048_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs 1024-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA1024_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 1024-bit RSA public wrapped key + */ + fsp_err_t (* RSA1024_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_public_wrapped_key_t * wrapped_key); + + /** This API outputs 1024-bit RSA private wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA1024_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 1024-bit RSA private wrapped key + */ + fsp_err_t (* RSA1024_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_private_wrapped_key_t * wrapped_key); + + /** This API outputs 2048-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA2048_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 2048-bit RSA public wrapped key + */ + fsp_err_t (* RSA2048_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_public_wrapped_key_t * wrapped_key); + + /** This API outputs 2048-bit RSA private wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA2048_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 2048-bit RSA private wrapped key + */ + fsp_err_t (* RSA2048_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_private_wrapped_key_t * wrapped_key); + + /** This API outputs 3072-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA3072_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 3072-bit RSA public wrapped key + */ + fsp_err_t (* RSA3072_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa3072_public_wrapped_key_t * wrapped_key); + + /** This API outputs 4096-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA4096_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 4096-bit RSA public wrapped key + */ + fsp_err_t (* RSA4096_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa4096_public_wrapped_key_t * wrapped_key); + + /** RSASSA-PKCS1-V1_5 signature generation. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS1024_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Inputs the 1024-bit RSA private wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS1024_SignatureGenerate)(sce_rsa_byte_data_t * message_hash, sce_rsa_byte_data_t * signature, + sce_rsa1024_private_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature generation. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS2048_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Inputs the 2048-bit RSA private wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS2048_SignatureGenerate)(sce_rsa_byte_data_t * message_hash, sce_rsa_byte_data_t * signature, + sce_rsa2048_private_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature verification. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS1024_SignatureVerify() + * + * @param[in] signature Signature text information to verify + * @param[in] message_hash Message text or hash value to verify + * @param[in] wrapped_key Inputs the 1024-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS1024_SignatureVerify)(sce_rsa_byte_data_t * signature, sce_rsa_byte_data_t * message_hash, + sce_rsa1024_public_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature verification. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS2048_SignatureVerify() + * + * @param[in] signature Signature text information to verify + * @param[in] message_hash Message text or hash value to verify + * @param[in] wrapped_key Inputs the 2048-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS2048_SignatureVerify)(sce_rsa_byte_data_t * signature, sce_rsa_byte_data_t * message_hash, + sce_rsa2048_public_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature verification. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS3072_SignatureVerify() + * + * @param[in] signature Signature text information to verify + * @param[in] message_hash Message text or hash value to verify + * @param[in] wrapped_key Inputs the 3072-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS3072_SignatureVerify)(sce_rsa_byte_data_t * signature, sce_rsa_byte_data_t * message_hash, + sce_rsa3072_public_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature verification. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS4096_SignatureVerify() + * + * @param[in] signature Signature text information to verify + * @param[in] message_hash Message text or hash value to verify + * @param[in] wrapped_key Inputs the 4096-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS4096_SignatureVerify)(sce_rsa_byte_data_t * signature, sce_rsa_byte_data_t * message_hash, + sce_rsa4096_public_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSAES-PKCS1-V1_5 encryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS1024_Encrypt() + * + * @param[in] plain plaintext + * @param[in,out] cipher ciphertext + * @param[in] wrapped_key Inputs the 1024-bit RSA public wrapped key. + */ + fsp_err_t (* RSAES_PKCS1024_Encrypt)(sce_rsa_byte_data_t * plain, sce_rsa_byte_data_t * cipher, + sce_rsa1024_public_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 encryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS2048_Encrypt() + * + * @param[in] plain plaintext + * @param[in,out] cipher ciphertext + * @param[in] wrapped_key Inputs the 2048-bit RSA public wrapped key. + */ + fsp_err_t (* RSAES_PKCS2048_Encrypt)(sce_rsa_byte_data_t * plain, sce_rsa_byte_data_t * cipher, + sce_rsa2048_public_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 encryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS3072_Encrypt() + * + * @param[in] plain plaintext + * @param[in,out] cipher ciphertext + * @param[in] wrapped_key Inputs the 3072-bit RSA public wrapped key. + */ + fsp_err_t (* RSAES_PKCS3072_Encrypt)(sce_rsa_byte_data_t * plain, sce_rsa_byte_data_t * cipher, + sce_rsa3072_public_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 encryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS4096_Encrypt() + * + * @param[in] plain plaintext + * @param[in,out] cipher ciphertext + * @param[in] wrapped_key Inputs the 4096-bit RSA public wrapped key. + */ + fsp_err_t (* RSAES_PKCS4096_Encrypt)(sce_rsa_byte_data_t * plain, sce_rsa_byte_data_t * cipher, + sce_rsa4096_public_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 decryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS1024_Decrypt() + * + * @param[in] cipher ciphertext + * @param[in,out] plain plaintext + * @param[in] wrapped_key Inputs the 1024-bit RSA private wrapped key. + */ + fsp_err_t (* RSAES_PKCS1024_Decrypt)(sce_rsa_byte_data_t * cipher, sce_rsa_byte_data_t * plain, + sce_rsa1024_private_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 decryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS2048_Decrypt() + * + * @param[in] cipher ciphertext + * @param[in,out] plain plaintext + * @param[in] wrapped_key Inputs the 2048-bit RSA private wrapped key. + */ + fsp_err_t (* RSAES_PKCS2048_Decrypt)(sce_rsa_byte_data_t * cipher, sce_rsa_byte_data_t * plain, + sce_rsa2048_private_wrapped_key_t * wrapped_key); + + /** This API outputs HMAC-SHA256 wrapped key. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_EncryptedKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key HMAC-SHA256 wrapped key + */ + fsp_err_t (* SHA256HMAC_EncryptedKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_hmac_sha_wrapped_key_t * wrapped_key); + + /** Initialize HMAC-SHA256 generation. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_GenerateInit() + * + * @param[in,out] handle SHA-HMAC handler (work area) + * @param[in] wrapped_key MAC wrapped key + */ + fsp_err_t (* SHA256HMAC_GenerateInit)(sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key); + + /** Update HMAC-SHA256 generation. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_GenerateUpdate() + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] message Message area + * @param[in] message_length Message length + */ + fsp_err_t (* SHA256HMAC_GenerateUpdate)(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize HMAC-SHA256 generation. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_GenerateFinal() + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in,out] mac HMAC area (32 bytes) + */ + fsp_err_t (* SHA256HMAC_GenerateFinal)(sce_hmac_sha_handle_t * handle, uint8_t * mac); + + /** Initialize HMAC-SHA256 verification. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_VerifyInit() + * + * @param[in,out] handle SHA-HMAC handler (work area) + * @param[in] wrapped_key MAC wrapped key + */ + fsp_err_t (* SHA256HMAC_VerifyInit)(sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key); + + /** Update HMAC-SHA256 verification. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_VerifyUpdate() + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] message Message area + * @param[in] message_length Message length + */ + fsp_err_t (* SHA256HMAC_VerifyUpdate)(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize HMAC-SHA256 verification. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_VerifyFinal() + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] mac HMAC area + * @param[in] mac_length HMAC length + */ + fsp_err_t (* SHA256HMAC_VerifyFinal)(sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length); + + /** This API outputs secp192r1 wrapped pair key. + * @par Implemented as + * - @ref R_SCE_ECC_secp192r1_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp192r1 public key and private key pair + */ + fsp_err_t (* ECC_secp192r1_WrappedKeyPairGenerate)(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs secp224r1 wrapped pair key. + * @par Implemented as + * - @ref R_SCE_ECC_secp224r1_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp224r1 public key and private key pair + */ + fsp_err_t (* ECC_secp224r1_WrappedKeyPairGenerate)(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs secp256r1 wrapped pair key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256r1_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp256r1 public key and private key pair + */ + fsp_err_t (* ECC_secp256r1_WrappedKeyPairGenerate)(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs secp384r1 wrapped pair key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp384r1 public key and private key pair + */ + fsp_err_t (* ECC_secp384r1_WrappedKeyPairGenerate)(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs secp192r1 public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp192r1_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp192r1 public wrapped key + */ + fsp_err_t (* ECC_secp192r1_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** This API outputs secp224r1 public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp224r1_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp224r1 public wrapped key + */ + fsp_err_t (* ECC_secp224r1_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** This API outputs secp256r1 public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp256r1 public wrapped key + */ + fsp_err_t (* ECC_secp256r1_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** This API outputs secp384r1 public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp384r1 public wrapped key + */ + fsp_err_t (* ECC_secp384r1_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** This API outputs secp192r1 private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp192r1_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp192r1 private wrapped key + */ + fsp_err_t (* ECC_secp192r1_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** This API outputs secp224r1 private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp224r1_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp224r1 private wrapped key + */ + fsp_err_t (* ECC_secp224r1_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** This API outputs secp256r1 private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp256r1 private wrapped key + */ + fsp_err_t (* ECC_secp256r1_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** This API outputs secp384r1 private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp384r1 private wrapped key + */ + fsp_err_t (* ECC_secp384r1_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature generation. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp192r1_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Input wrapped key of secp192r1 private key. + */ + fsp_err_t (* ECDSA_secp192r1_SignatureGenerate)(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature generation. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp224r1_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Input wrapped key of secp224r1 private key. + */ + fsp_err_t (* ECDSA_secp224r1_SignatureGenerate)(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature generation. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp256r1_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Input wrapped key of secp256r1 private key. + */ + fsp_err_t (* ECDSA_secp256r1_SignatureGenerate)(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature generation. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp384r1_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Input wrapped key of secp384r1 private key. + */ + fsp_err_t (* ECDSA_secp384r1_SignatureGenerate)(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature verification. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp192r1_SignatureVerify() + * + * @param[in] signature Signature text information to be verified + * @param[in,out] message_hash Message or hash value to be verified + * @param[in] wrapped_key Input wrapped key of secp192r1 public key. + */ + fsp_err_t (* ECDSA_secp192r1_SignatureVerify)(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** ECDSA signature verification. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp224r1_SignatureVerify() + * + * @param[in] signature Signature text information to be verified + * @param[in,out] message_hash Message or hash value to be verified + * @param[in] wrapped_key Input wrapped key of secp224r1 public key. + */ + fsp_err_t (* ECDSA_secp224r1_SignatureVerify)(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** ECDSA signature verification. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp256r1_SignatureVerify() + * + * @param[in] signature Signature text information to be verified + * @param[in,out] message_hash Message or hash value to be verified + * @param[in] wrapped_key Input wrapped key of secp256r1 public key. + */ + fsp_err_t (* ECDSA_secp256r1_SignatureVerify)(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** ECDSA signature verification. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp384r1_SignatureVerify() + * + * @param[in] signature Signature text information to be verified + * @param[in,out] message_hash Message or hash value to be verified + * @param[in] wrapped_key Input wrapped key of secp384r1 public key. + */ + fsp_err_t (* ECDSA_secp384r1_SignatureVerify)(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** secp256r1 ECDH Initialization. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_Init() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] key_type Key exchange type + * @param[in] use_key_id use key_id or not + */ + fsp_err_t (* ECDH_secp256r1_Init)(sce_ecdh_handle_t * handle, uint32_t key_type, uint32_t use_key_id); + + /** secp256r1 ECDH public key Signature. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_PublicKeySign() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] ecc_public_wrapped_key For ECDHE, input a null pointer. For ECDH, input the wrapped key of a secp256r1 public key. + * @param[in] ecc_private_wrapped_key secp256r1 private key for signature generation + * @param[in,out] public_key User secp256r1 public key (512-bit) for key exchange. + * @param[in,out] signature Signature text storage destination information + * @param[in,out] wrapped_key For ECDHE, a private wrapped key generated from a random number. Not output for ECDH. + */ + fsp_err_t (* ECDH_secp256r1_PublicKeySign)(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + uint8_t * public_key, sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** secp256r1 ECDH public key verification. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_PublicKeyVerify() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] ecc_public_wrapped_key Public wrapped key area for signature verification + * @param[in] public_key_data secp256r1 public key (512-bit) + * @param[in] signature ECDSA secp256r1 signature of ecc_public_wrapped_key + * @param[in,out] wrapped_key wrapped key of ecc_public_wrapped_key + */ + fsp_err_t (* ECDH_secp256r1_PublicKeyVerify)(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + uint8_t * public_key_data, sce_ecdsa_byte_data_t * signature, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** Output the key index of QeU without signature verification. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_PublicKeyReadWithoutSignature() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] public_key_data secp256r1 public key (512-bit). When key_id is used: + * key_id (8-bit) || public key (512-bit) + * @param[in,out] wrapped_key wrapped key of ecc_public_wrapped_key + */ + fsp_err_t (* ECDH_secp256r1_PublicKeyReadWithoutSignature)(sce_ecdh_handle_t * handle, + uint8_t * public_key_data, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** secp256r1 ECDH shared secret calculation. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_SharedSecretCalculate() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] ecc_public_wrapped_key Public wrapped key + * @param[in] ecc_private_wrapped_key Private wrapped key + * @param[in,out] shared_secret_wrapped_key Wrapped key of shared secret Z calculated by ECDH key exchange + */ + fsp_err_t (* ECDH_secp256r1_SharedSecretCalculate)(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key); + + /** secp256r1 ECDH key derivation. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_KeyDerivation() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] shared_secret_wrapped_key Z wrapped key calculated by R_SCE_ECDH_secp256r1_SharedSecretCalculate + * @param[in] key_type Derived key type + * @param[in] kdf_type Algorithm used for key derivation calculation + * @param[in] other_info Additional data used for key derivation calculation + * @param[in] other_info_length Data length of other_info + * @param[in] salt_wrapped_key Salt wrapped key + * @param[in,out] wrapped_key Wrapped key corresponding to key_type. + */ + fsp_err_t (* ECDH_secp256r1_KeyDerivation)(sce_ecdh_handle_t * handle, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key, uint32_t key_type, + uint32_t kdf_type, uint8_t * other_info, + uint32_t other_info_length, + sce_hmac_sha_wrapped_key_t * salt_wrapped_key, + sce_aes_wrapped_key_t * wrapped_key); + + /** Generate TLS RSA Public key index data + * @par Implemented as + * - @ref R_SCE_TLS_RootCertificateRSA2048PublicKeyInstall() + * + * @param[in] encrypted_provisioning_key the provisioning key includes encrypted CBC/CBC-MAC key for user key + * @param[in] initial_vector the initial_vector for user key CBC encrypt + * @param[in] encrypted_key the user key encrypted with AES128-ECB mode + * @param[out] wrapped_key the user Key Generation Information (141 words) of RSA2048 bit + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_RootCertificateRSA2048PublicKeyInstall)(uint8_t * encrypted_provisioning_key, + uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_tls_ca_certification_public_wrapped_key_t * wrapped_key); + + /** Generate TLS ECC key pair + * @par Implemented as + * - @ref R_SCE_TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate() + * + * @param[in] tls_p256_ecc_wrapped_key P256 ECC key index for TLS + * @param[in] ephemeral_ecdh_public_key ephemeral ECDH public key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate)(sce_tls_p256_ecc_wrapped_key_t * tls_p256_ecc_wrapped_key, + uint8_t * ephemeral_ecdh_public_key); + + /** Verify root CA certificate. + * @par Implemented as + * - @ref R_SCE_TLS_RootCertificateVerify() + * + * @param[in] public_key_type key type + * @param[in] certificate certificates. + * @param[in] certificate_length byte size of certificates. + * @param[in] public_key_n_start_position start position of public key n. + * @param[in] public_key_n_end_position end position of public key n. + * @param[in] public_key_e_start_position start position of public key e. + * @param[in] public_key_e_end_position end position of public key e. + * @param[in] signature signature for certificates. + * @param[out] encrypted_root_public_key public key for RSA 2048bit. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + */ + fsp_err_t (* TLS_RootCertificateVerify)(uint32_t public_key_type, + uint8_t *certificate, + uint32_t certificate_length, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint8_t *signature, + uint32_t *encrypted_root_public_key); + + /** Verify server certificate and intermediate certificate. + * @par Implemented as + * - @ref R_SCE_TLS_CertificateVerify() + * + * @param[in] public_key_type key type + * @param[in] input_public_key public key. + * @param[in] certificate certificates. + * @param[in] certificate_length byte size of certificates. + * @param[in] signature signature for certificates. + * @param[in] public_key_n_start_position start position of public key n. + * @param[in] public_key_n_end_position end position of public key n. + * @param[in] public_key_e_start_position start position of public key e. + * @param[in] public_key_e_end_position end position of public key e. + * @param[out] encrypted_output_public_key public key for RSA 2048bit. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_CertificateVerify)(uint32_t public_key_type, + uint32_t *encrypted_input_public_key, + uint8_t *certificate, + uint32_t certificate_length, + uint8_t *signature, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint32_t *encrypted_output_public_key); + + /** Generate encrypted pre-master secret. + * @par Implemented as + * - @ref R_SCE_TLS_PreMasterSecretGenerateForRSA2048() + * + * @param[out] sce_pre_master_secret pre-master secret value for SCE. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + */ + fsp_err_t (* TLS_PreMasterSecretGenerateForRSA2048)(uint32_t *sce_pre_master_secret); + + /** Generate encrypted master secret. + * @par Implemented as + * - @ref R_SCE_TLS_MasterSecretGenerate() + * + * @param[in] select_cipher_suite cipher suite type + * @param[in] sce_pre_master_secret pre-master secret value for SCE. + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[out] sce_master_secret master secret value with SCE-specific conversion. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_MasterSecretGenerate)(uint32_t select_cipher_suite, + uint32_t *sce_pre_master_secret, + uint8_t *client_random, + uint8_t *server_random, + uint32_t *sce_master_secret); + + /** Output the result encrypted pre-master secret with RSA 2048bit + * @par Implemented as + * - @ref R_SCE_TLS_PreMasterSecretEncryptWithRSA2048() + * + * @param[in] encrypted_public_key public key data. + * @param[in] sce_pre_master_secret pre-master secret value. + * @param[out] encrypted_pre_master_secret the value encrypted pre-master secret. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_PreMasterSecretEncryptWithRSA2048)(uint32_t *encrypted_public_key, + uint32_t *sce_pre_master_secret, + uint8_t *encrypted_pre_master_secret); + + /** Output various key information. + * @par Implemented as + * - @ref R_SCE_TLS_SessionKeyGenerate() + * + * @param[in] select_cipher_suite Key suite information number. + * @param[in] sce_master_secret master secret value. + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[in] nonce_explicit nonce value + * @param[out] client_mac_wrapped_key the mac key during communication from client to server. + * @param[out] server_mac_wrapped_key the mac key during communication from server to client. + * @param[out] client_crypto_wrapped_key the crypto key during communication from client to server. + * @param[out] server_crypto_wrapped_key the crypto key during communication from server to client. + * @param[in] client_initial_vector not use. + * @param[in] server_initial_vector not use. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_SessionKeyGenerate)(uint32_t select_cipher_suite, + uint32_t *sce_master_secret, + uint8_t *client_random, + uint8_t *server_random, + uint8_t* nonce_explicit, + sce_hmac_sha_wrapped_key_t *client_mac_wrapped_key, + sce_hmac_sha_wrapped_key_t *server_mac_wrapped_key, + sce_aes_wrapped_key_t *client_crypto_wrapped_key, + sce_aes_wrapped_key_t *server_crypto_wrapped_key, + uint8_t *client_initial_vector, + uint8_t *server_initial_vector); + + /** Generate verify data. + * @par Implemented as + * - @ref R_SCE_TLS_VerifyDataGenerate() + * + * @param[in] select_verify_data Select Client/Server data. + * @param[in] sce_master_secret master secret data. + * @param[in] hand_shake_hash TLS hand shake message SHA256 HASH value. + * @param[out] verify_data verify data. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_VerifyDataGenerate)(uint32_t select_verify_data, + uint32_t *sce_master_secret, + uint8_t *hand_shake_hash, + uint8_t *verify_data); + + /** Retrives ECDH public key. + * @par Implemented as + * - @ref R_SCE_TLS_ServerKeyExchangeVerify() + * + * @param[in] public_key_type key type + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[in] server_ephemeral_ecdh_public_key Ephemeral ECDH public key from Server. + * @param[in] server_key_exchange_sigunature Server Key Exchange sigunature. + * @param[in] encrypted_public_key encrypted public key. + * @param[out] encrypted_ephemeral_ecdh_public_key encrypted Ephemeral ECDH public key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_ServerKeyExchangeVerify)(uint32_t public_key_type, + uint8_t *client_random, + uint8_t *server_random, + uint8_t *server_ephemeral_ecdh_public_key, + uint8_t *server_key_exchange_signature, + uint32_t *encrypted_public_key, + uint32_t *encrypted_ephemeral_ecdh_public_key); + + /** Generate encrypted pre-master secret. + * @par Implemented as + * - @ref R_SCE_TLS_PreMasterSecretGenerateForECC_secp256r1() + * + * @param[in] encrypted_public_key encrypted public key + * @param[in] tls_p256_ecc_wrapped_key P-256 ECC key index. + * @param[out] sce_pre_master_secret encrypted pre-master secret value for SCE. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_PreMasterSecretGenerateForECC_secp256r1)(uint32_t *encrypted_public_key, + sce_tls_p256_ecc_wrapped_key_t *tls_p256_ecc_wrapped_key, + uint32_t *sce_pre_master_secret); + +} sce_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_sce_instance +{ + sce_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + sce_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + sce_api_t const * p_api; ///< Pointer to the API structure for this instance +} sce_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_SCE_API_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED_API) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h new file mode 100644 index 0000000000..f4b7e414e5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h @@ -0,0 +1,598 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup SCE_PROTECTED + * @{ + **********************************************************************************************************************/ + +#ifndef R_SCE_H +#define R_SCE_H + +#include "bsp_api.h" +#include "r_sce_cfg.h" +#include "r_sce_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Version Number of Module. */ +#define FSP_R_SCE9_PROTECTED_VERSION_MAJOR (1U) +#define FSP_R_SCE9_PROTECTED_VERSION_MINOR (1U) +#define FSP_R_SCE9_PROTECTED_VERSION_PATCH (0U) + +/* Various information. */ +#define HW_SCE_SRAM_WORD_SIZE (32U) +#define HW_SCE_SINST_WORD_SIZE (140U) +#define HW_SCE_SINST2_WORD_SIZE (16U) +#define HW_SCE_SHEAP_WORD_SIZE (1504U) +#define HW_SCE_MAC_SIZE (16U) + +/* ECC curve types. */ +#define SCE_ECC_CURVE_TYPE_NIST (0) +#define SCE_ECC_CURVE_TYPE_BRAINPOOL (1) +#define SCE_ECC_CURVE_TYPE_KOBLITZ (2) + +/* ECC curve size */ +#define SCE_ECC_KEY_LENGTH_256 (0) +#define SCE_ECC_KEY_LENGTH_224 (1) +#define SCE_ECC_KEY_LENGTH_192 (2) + +/* For AES operation. */ +#define SCE_KEYWRAP_AES128 (0U) +#define SCE_KEYWRAP_AES256 (1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* key index type */ +typedef enum +{ + SCE_KEY_INDEX_TYPE_INVALID = 0U, + SCE_KEY_INDEX_TYPE_AES128, + SCE_KEY_INDEX_TYPE_AES256, + SCE_KEY_INDEX_TYPE_TDES, + SCE_KEY_INDEX_TYPE_HMAC_SHA1, + SCE_KEY_INDEX_TYPE_HMAC_SHA256, + SCE_KEY_INDEX_TYPE_RSA1024_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA1024_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA2048_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA2048_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA3072_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA3072_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA4096_PRIVATE, + SCE_KEY_INDEX_TYPE_AES128_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES192_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES256_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS, + SCE_KEY_INDEX_TYPE_UPDATE_KEY_RING, + SCE_KEY_INDEX_TYPE_TLS_CA_CERTIFICATION_PUBLIC_KEY, + SCE_KEY_INDEX_TYPE_TLS_P256_ECC_KEY, + SCE_KEY_INDEX_TYPE_ECC_P192_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P224_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P192_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECDH_SHARED_SECRET, + SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH, + SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH, + SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_ECDH, + SCE_KEY_INDEX_TYPE_AES128_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES256_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_KEY_WRAP_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_GCM_WITH_IV, +} SCE_KEY_INDEX_TYPE; + +/* OEM Command */ +typedef enum e_sce_oem_cmd +{ + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES256 = 7, + SCE_OEM_CMD_RSA1024_PUBLIC = 10, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA256 = 27, + SCE_OEM_CMD_NUM +} sce_oem_cmd_t; + +/** SCE private control block. DO NOT MODIFY. Initialization occurs when R_SCE_Open() is called. */ +typedef struct st_sce_instance_ctrl +{ + uint32_t open; // Indicates whether the open() API has been successfully +} sce_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const sce_api_t g_sce_protected_on_sce; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_SCE_Open(sce_ctrl_t * const p_ctrl, sce_cfg_t const * const p_cfg); +fsp_err_t R_SCE_Close(sce_ctrl_t * const p_ctrl); +fsp_err_t R_SCE_SoftwareReset(void); + +fsp_err_t R_SCE_AES128_WrappedKeyGenerate(sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256_WrappedKeyGenerate(sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA1024_WrappedKeyPairGenerate(sce_rsa1024_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_RSA2048_WrappedKeyPairGenerate(sce_rsa2048_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_ECC_secp192r1_WrappedKeyPairGenerate(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_ECC_secp224r1_WrappedKeyPairGenerate(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_ECC_secp256r1_WrappedKeyPairGenerate(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_ECC_secp384r1_WrappedKeyPairGenerate(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_RandomNumberGenerate(uint32_t * random); + +fsp_err_t R_SCE_AES128_EncryptedKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256_EncryptedKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128_RFC3394KeyWrap(sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, + uint32_t * rfc3394_wrapped_key); +fsp_err_t R_SCE_AES256_RFC3394KeyWrap(sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, + uint32_t * rfc3394_wrapped_key); +fsp_err_t R_SCE_AES128_RFC3394KeyUnwrap(sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, + sce_aes_wrapped_key_t * target_key); +fsp_err_t R_SCE_AES256_RFC3394KeyUnwrap(sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, + sce_aes_wrapped_key_t * target_key); +fsp_err_t R_SCE_SHA256HMAC_EncryptedKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_hmac_sha_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_RSA1024_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA1024_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA2048_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA2048_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA3072_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa3072_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA4096_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa4096_public_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_ECC_secp192r1_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp224r1_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp192r1_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp224r1_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_AES128ECB_EncryptInit(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128ECB_EncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES128ECB_EncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t R_SCE_AES128ECB_DecryptInit(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128ECB_DecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES128ECB_DecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t R_SCE_AES256ECB_EncryptInit(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256ECB_EncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES256ECB_EncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t R_SCE_AES256ECB_DecryptInit(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256ECB_DecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES256ECB_DecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t R_SCE_AES128CBC_EncryptInit(sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); +fsp_err_t R_SCE_AES128CBC_EncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES128CBC_EncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t R_SCE_AES128CBC_DecryptInit(sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); +fsp_err_t R_SCE_AES128CBC_DecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES128CBC_DecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t R_SCE_AES256CBC_EncryptInit(sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); +fsp_err_t R_SCE_AES256CBC_EncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES256CBC_EncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t R_SCE_AES256CBC_DecryptInit(sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); +fsp_err_t R_SCE_AES256CBC_DecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES256CBC_DecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t R_SCE_AES128GCM_EncryptInit(sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length); +fsp_err_t R_SCE_AES128GCM_EncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_length, + uint8_t * aad, + uint32_t aad_length); +fsp_err_t R_SCE_AES128GCM_EncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_length, + uint8_t * atag); +fsp_err_t R_SCE_AES128GCM_DecryptInit(sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length); +fsp_err_t R_SCE_AES128GCM_DecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_length, + uint8_t * aad, + uint32_t aad_length); +fsp_err_t R_SCE_AES128GCM_DecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_length, + uint8_t * atag, + uint32_t atag_length); + +fsp_err_t R_SCE_AES256GCM_EncryptInit(sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length); +fsp_err_t R_SCE_AES256GCM_EncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_length, + uint8_t * aad, + uint32_t aad_length); +fsp_err_t R_SCE_AES256GCM_EncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_length, + uint8_t * atag); +fsp_err_t R_SCE_AES256GCM_DecryptInit(sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length); +fsp_err_t R_SCE_AES256GCM_DecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_length, + uint8_t * aad, + uint32_t aad_length); +fsp_err_t R_SCE_AES256GCM_DecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_length, + uint8_t * atag, + uint32_t atag_length); + +fsp_err_t R_SCE_AES128CCM_EncryptInit(sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t adata_length, + uint32_t payload_length, + uint32_t mac_length); +fsp_err_t R_SCE_AES128CCM_EncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES128CCM_EncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t R_SCE_AES128CCM_DecryptInit(sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t adata_length, + uint32_t payload_length, + uint32_t mac_length); +fsp_err_t R_SCE_AES128CCM_DecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES128CCM_DecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t R_SCE_AES256CCM_EncryptInit(sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t adata_length, + uint32_t payload_length, + uint32_t mac_length); +fsp_err_t R_SCE_AES256CCM_EncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES256CCM_EncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t R_SCE_AES256CCM_DecryptInit(sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t adata_length, + uint32_t payload_length, + uint32_t mac_length); +fsp_err_t R_SCE_AES256CCM_DecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES256CCM_DecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t R_SCE_AES128CMAC_GenerateInit(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128CMAC_GenerateUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_AES128CMAC_GenerateFinal(sce_cmac_handle_t * handle, uint8_t * mac); +fsp_err_t R_SCE_AES128CMAC_VerifyInit(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128CMAC_VerifyUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_AES128CMAC_VerifyFinal(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); +fsp_err_t R_SCE_AES256CMAC_GenerateInit(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256CMAC_GenerateUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_AES256CMAC_GenerateFinal(sce_cmac_handle_t * handle, uint8_t * mac); +fsp_err_t R_SCE_AES256CMAC_VerifyInit(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256CMAC_VerifyUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_AES256CMAC_VerifyFinal(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); + +fsp_err_t R_SCE_SHA256_Init(sce_sha_md5_handle_t * handle); +fsp_err_t R_SCE_SHA256_Update(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_SHA256_Final(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); + +fsp_err_t R_SCE_SHA256HMAC_GenerateInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_SHA256HMAC_GenerateUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_SHA256HMAC_GenerateFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac); +fsp_err_t R_SCE_SHA256HMAC_VerifyInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_SHA256HMAC_VerifyUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_SHA256HMAC_VerifyFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length); + +fsp_err_t R_SCE_RSASSA_PKCS1024_SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa1024_private_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS1024_SignatureVerify(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa1024_public_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS2048_SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa2048_private_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS2048_SignatureVerify(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa2048_public_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS3072_SignatureVerify(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa3072_public_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS4096_SignatureVerify(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa4096_public_wrapped_key_t * wrapped_key, + uint8_t hash_type); + +fsp_err_t R_SCE_RSAES_PKCS1024_Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa1024_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS1024_Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa1024_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS2048_Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa2048_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS2048_Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa2048_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS3072_Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa3072_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS4096_Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa4096_public_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_ECDSA_secp192r1_SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp224r1_SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp256r1_SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp384r1_SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp192r1_SignatureVerify(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp224r1_SignatureVerify(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp256r1_SignatureVerify(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp384r1_SignatureVerify(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_ECDH_secp256r1_Init(sce_ecdh_handle_t * handle, uint32_t key_type, uint32_t use_key_id); +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeySign(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + uint8_t * public_key, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeyVerify(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + uint8_t * public_key_data, + sce_ecdsa_byte_data_t * signature, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeyReadWithoutSignature(sce_ecdh_handle_t * handle, + uint8_t * public_key_data, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDH_secp256r1_SharedSecretCalculate(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key); +fsp_err_t R_SCE_ECDH_secp256r1_KeyDerivation(sce_ecdh_handle_t * handle, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key, + uint32_t key_type, + uint32_t kdf_type, + uint8_t * other_info, + uint32_t other_info_length, + sce_hmac_sha_wrapped_key_t * salt_wrapped_key, + sce_aes_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_TLS_RootCertificateRSA2048PublicKeyInstall(uint8_t *encrypted_provisioning_key, uint8_t *initial_vector, + uint8_t *encrypted_key, sce_tls_ca_certification_public_wrapped_key_t *wrapped_key); +fsp_err_t R_SCE_TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate(sce_tls_p256_ecc_wrapped_key_t *tls_p256_ecc_wrapped_key, + uint8_t *ephemeral_ecdh_public_key); +fsp_err_t R_SCE_TLS_RootCertificateVerify(uint32_t public_key_type, uint8_t *certificate, + uint32_t certificate_length, uint32_t public_key_n_start_position, uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, uint32_t public_key_e_end_position, uint8_t *signature, + uint32_t *encrypted_root_public_key); +fsp_err_t R_SCE_TLS_CertificateVerify(uint32_t public_key_type, uint32_t *encrypted_input_public_key, + uint8_t *certificate, uint32_t certificate_length, uint8_t *signature, uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, uint32_t public_key_e_start_position, uint32_t public_key_e_end_position, + uint32_t *encrypted_output_public_key); +fsp_err_t R_SCE_TLS_PreMasterSecretEncryptWithRSA2048(uint32_t *encrypted_public_key, + uint32_t *sce_pre_master_secret, uint8_t *encrypted_pre_master_secret); +fsp_err_t R_SCE_TLS_PreMasterSecretGenerateForRSA2048(uint32_t *sce_pre_master_secret); +fsp_err_t R_SCE_TLS_MasterSecretGenerate (uint32_t select_cipher_suite, uint32_t *sce_pre_master_secret, + uint8_t *client_random, uint8_t *server_random, uint32_t *sce_master_secret); +fsp_err_t R_SCE_TLS_SessionKeyGenerate(uint32_t select_cipher_suite, uint32_t *sce_master_secret, + uint8_t *client_random, uint8_t *server_random, uint8_t* nonce_explicit, + sce_hmac_sha_wrapped_key_t *client_mac_wrapped_key, sce_hmac_sha_wrapped_key_t *server_mac_wrapped_key, + sce_aes_wrapped_key_t *client_crypto_wrapped_key, sce_aes_wrapped_key_t *server_crypto_wrapped_key, + uint8_t *client_initial_vector, uint8_t *server_initial_vector); +fsp_err_t R_SCE_TLS_VerifyDataGenerate(uint32_t select_verify_data, uint32_t *sce_master_secret, + uint8_t *hand_shake_hash, uint8_t *verify_data); +fsp_err_t R_SCE_TLS_ServerKeyExchangeVerify(uint32_t public_key_type, uint8_t *client_random, + uint8_t *server_random, uint8_t *server_ephemeral_ecdh_public_key, uint8_t *server_key_exchange_signature, + uint32_t *encrypted_public_key, uint32_t *encrypted_ephemeral_ecdh_public_key); +fsp_err_t R_SCE_TLS_PreMasterSecretGenerateForECC_secp256r1(uint32_t *encrypted_public_key, + sce_tls_p256_ecc_wrapped_key_t *tls_p256_ecc_wrapped_key, uint32_t *sce_pre_master_secret); + +uint32_t SCE_USER_SHA_384_FUNCTION(uint8_t * message, uint8_t * digest, uint32_t message_length); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_SCE_H + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func000.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func000.c new file mode 100644 index 0000000000..64a1d8a230 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func000.c @@ -0,0 +1,100 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func000(uint32_t *InData_PaddedMsg, int32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < (uint32_t)MAX_CNT; iLoop = iLoop + 16) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[iLoop + 0]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 1]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 2]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 3]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 4]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 5]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 6]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 7]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 8]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 9]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 10]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 11]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 12]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 13]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 14]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 15]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_104H = 0x00000000U; + SCE->REG_1CH = 0x00001600U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func000.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func001.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func001.c new file mode 100644 index 0000000000..273e49422a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func001.c @@ -0,0 +1,134 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func001(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00050805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00005143U; + SCE->REG_104H = 0x00000f51U; + SCE->REG_A4H = 0x00000c85U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_A4H = 0x00000cc5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func001.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func002.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func002.c new file mode 100644 index 0000000000..132c0a6c74 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func002.c @@ -0,0 +1,116 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func002(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_00H = 0x00005143U; + SCE->REG_104H = 0x00000f51U; + SCE->REG_A4H = 0x00000c85U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_A4H = 0x00000cc5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_B0H = 0x00000100U; + SCE->REG_A4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func002.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func003.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func003.c new file mode 100644 index 0000000000..e6424dee02 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func003.c @@ -0,0 +1,1059 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func003_r1(uint32_t* ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_28H = 0x00870001U; + OFS_ADR = 128; + R_SCE_func100(0xea3764daU, 0xebb4b66dU, 0xebd4ecb9U, 0x7dd67d43U); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000403U; + SCE->REG_24H = 0x8000e8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010360U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f0U); + R_SCE_func101(0x10831ca1U, 0xc281a506U, 0x17374301U, 0xe4d3212cU); + R_SCE_func006(); + R_SCE_func100(0x582a5ed6U, 0x0a427c5fU, 0xc5125e60U, 0x64386bb9U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x399f44b1U, 0x8b4e6131U, 0xbfe405a2U, 0x82f3103bU); + } + else + { + R_SCE_func100(0x0e020092U, 0xf0b2e70eU, 0xaa972bdcU, 0x6e2a711cU); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xba8cb150U, 0x59aa1fe3U, 0x84900f4fU, 0x3d4a7d23U); + R_SCE_func103(); + R_SCE_func100(0x76272c57U, 0xd7c1946bU, 0x146dc60cU, 0xb38d6331U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01080c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x530ee80bU, 0x825a9a41U, 0x5dea54ccU, 0xd0141d7bU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000aaU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000223U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[0] = SCE->REG_100H; + S_HEAP[1] = SCE->REG_100H; + S_HEAP[2] = SCE->REG_100H; + S_HEAP[3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[4] = SCE->REG_100H; + S_HEAP[5] = SCE->REG_100H; + S_HEAP[6] = SCE->REG_100H; + S_HEAP[7] = SCE->REG_100H; + R_SCE_func100(0xf7040eccU, 0xff42e53dU, 0xd783ce09U, 0xcfe0b390U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000abU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000223U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[8] = SCE->REG_100H; + S_HEAP[9] = SCE->REG_100H; + S_HEAP[10] = SCE->REG_100H; + S_HEAP[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[12] = SCE->REG_100H; + S_HEAP[13] = SCE->REG_100H; + S_HEAP[14] = SCE->REG_100H; + S_HEAP[15] = SCE->REG_100H; + R_SCE_func100(0x5fa88adaU, 0x24425fb0U, 0xadc8f0deU, 0xc3256a37U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000a8U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000223U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[16] = SCE->REG_100H; + S_HEAP[17] = SCE->REG_100H; + S_HEAP[18] = SCE->REG_100H; + S_HEAP[19] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[20] = SCE->REG_100H; + S_HEAP[21] = SCE->REG_100H; + S_HEAP[22] = SCE->REG_100H; + S_HEAP[23] = SCE->REG_100H; + R_SCE_func100(0x36ab2e42U, 0xaf522ca7U, 0x455a7df8U, 0x89a46c78U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000a9U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000223U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[24] = SCE->REG_100H; + S_HEAP[25] = SCE->REG_100H; + S_HEAP[26] = SCE->REG_100H; + S_HEAP[27] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[28] = SCE->REG_100H; + S_HEAP[29] = SCE->REG_100H; + S_HEAP[30] = SCE->REG_100H; + S_HEAP[31] = SCE->REG_100H; + R_SCE_func100(0xff14ab87U, 0xe9063228U, 0xe10a46ecU, 0xc003e706U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x0000002aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000223U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[32] = SCE->REG_100H; + S_HEAP[33] = SCE->REG_100H; + S_HEAP[34] = SCE->REG_100H; + S_HEAP[35] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[36] = SCE->REG_100H; + S_HEAP[37] = SCE->REG_100H; + S_HEAP[38] = SCE->REG_100H; + S_HEAP[39] = SCE->REG_100H; + R_SCE_func100(0x960ffa68U, 0xd6e49372U, 0x6040d1b1U, 0x5f85e6cdU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x0000002bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000223U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[40] = SCE->REG_100H; + S_HEAP[41] = SCE->REG_100H; + S_HEAP[42] = SCE->REG_100H; + S_HEAP[43] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[44] = SCE->REG_100H; + S_HEAP[45] = SCE->REG_100H; + S_HEAP[46] = SCE->REG_100H; + S_HEAP[47] = SCE->REG_100H; + R_SCE_func100(0x4a6fc245U, 0xb66f99f9U, 0x1916205fU, 0xcfe4a20dU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000223U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[48] = SCE->REG_100H; + S_HEAP[49] = SCE->REG_100H; + S_HEAP[50] = SCE->REG_100H; + S_HEAP[51] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[52] = SCE->REG_100H; + S_HEAP[53] = SCE->REG_100H; + S_HEAP[54] = SCE->REG_100H; + S_HEAP[55] = SCE->REG_100H; + R_SCE_func100(0xec1a7029U, 0xa1765d2eU, 0xae2bbaecU, 0x95c70385U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000223U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[56] = SCE->REG_100H; + S_HEAP[57] = SCE->REG_100H; + S_HEAP[58] = SCE->REG_100H; + S_HEAP[59] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[60] = SCE->REG_100H; + S_HEAP[61] = SCE->REG_100H; + S_HEAP[62] = SCE->REG_100H; + S_HEAP[63] = SCE->REG_100H; + R_SCE_func100(0x699d0600U, 0xaeb1bdf6U, 0x2f612c33U, 0x857d0108U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000213U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[64] = SCE->REG_100H; + S_HEAP[65] = SCE->REG_100H; + S_HEAP[66] = SCE->REG_100H; + S_HEAP[67] = SCE->REG_100H; + R_SCE_func100(0x3d62468cU, 0x9d641ddeU, 0xb04bcb68U, 0x22da51caU); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000403U; + SCE->REG_24H = 0x8000e8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x800058d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x8000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + SCE->REG_2CH = 0x00000094U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x0000001dU; + SCE->REG_104H = 0x00000767U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[0]; + SCE->REG_100H = ARG1[1]; + SCE->REG_100H = ARG1[2]; + SCE->REG_100H = ARG1[3]; + SCE->REG_100H = ARG1[4]; + SCE->REG_100H = ARG1[5]; + SCE->REG_100H = ARG1[6]; + SCE->REG_100H = ARG1[7]; + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000767U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[8]; + SCE->REG_100H = ARG1[9]; + SCE->REG_100H = ARG1[10]; + SCE->REG_100H = ARG1[11]; + SCE->REG_100H = ARG1[12]; + SCE->REG_100H = ARG1[13]; + SCE->REG_100H = ARG1[14]; + SCE->REG_100H = ARG1[15]; + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0002b208U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x3ef22588U, 0x6a7d7afeU, 0xa92dad9dU, 0xac7e07cdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x4d316739U, 0x41c9f42bU, 0x9687f998U, 0x1abab41cU); + } + else + { + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x8000fcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x5e194be2U, 0x88ccf668U, 0x25469559U, 0xbbf829b0U); + R_SCE_func009(); + R_SCE_func100(0x7e527544U, 0xca96159bU, 0xf8863d50U, 0x30fc468cU); + SCE->REG_34H = 0x00000410U; + SCE->REG_24H = 0x800098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func005_r1(OFS_ADR); + R_SCE_func100(0x74052956U, 0x1e74f390U, 0x70f9080bU, 0xa3ebd23fU); + SCE->REG_34H = 0x00000110U; + SCE->REG_24H = 0x800019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000110U; + SCE->REG_24H = 0x80001ec0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000330U; + SCE->REG_24H = 0x800019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000330U; + SCE->REG_24H = 0x80001ec0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func007(); + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00231030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x5cd41677U, 0xd60e6b13U, 0x4d025716U, 0x6647711cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x2fa62f65U, 0xf8419f52U, 0x85a35c73U, 0x6b7f5edfU); + } + else + { + SCE->REG_24H = 0x0000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000b20cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000908U; + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000908U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00008c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000a4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0002b208U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00a10000U; + R_SCE_func100(0xfa21fea5U, 0x5c4198b3U, 0xca598f46U, 0xaee0bb8aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0xe99d5d5dU, 0xcdff99d6U, 0x1760c984U, 0x01b9a5f5U); + } + else + { + SCE->REG_ECH = 0x0000d000U; + R_SCE_func101(0xed89af9aU, 0xd96477e8U, 0x61f940bbU, 0x9e982112U); + } + } + } + } + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func003_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func004.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func004.c new file mode 100644 index 0000000000..55aea839a2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func004.c @@ -0,0 +1,274 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func004_r1(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01542614U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01ba24feU; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01bb59d6U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00870001U; + SCE->REG_C4H = 0x00443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c3e1cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00002f62U; + SCE->REG_D0H = 0x00000b00U; + SCE->REG_C4H = 0x02f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+68 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+72 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000015U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+76 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+80 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+84 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+88 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+92 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+96 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+100 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+104 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+108 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+112 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+116 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func004_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func005.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func005.c new file mode 100644 index 0000000000..72292eb809 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func005.c @@ -0,0 +1,326 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func005_r1(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x017c67d8U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0126ddb5U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01bcfa36U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00870001U; + SCE->REG_C4H = 0x00443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c3e1cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x02f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+0 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+4 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+8 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+12 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+16 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+20 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000098U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+24 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+28 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000099U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+32 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+36 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000094U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+40 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+44 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000095U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+48 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+52 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+56 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+60 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+64 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func005_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func006.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func006.c new file mode 100644 index 0000000000..ea05302e2f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func006.c @@ -0,0 +1,590 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func006(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x527811b7U, 0x22817203U, 0x42620cbaU, 0x2dfcd2abU); + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000f008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x8000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000011U; + SCE->REG_104H = 0x00000757U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00001030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_34H = 0x00000c08U; + SCE->REG_24H = 0x8000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c08U; + SCE->REG_24H = 0x8000f4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x8000f4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_38H = 0x00002000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_38H = 0x00003000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xe0915d1fU, 0x0638582aU, 0x4d455a4aU, 0x0ede0328U); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000001U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800090d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000001U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x80006cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800090d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000830U; + SCE->REG_24H = 0x800098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000830U; + SCE->REG_24H = 0x8000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x80006cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x8000f4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x80006cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_38H = 0x00002000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_38H = 0x00003000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_ECH = 0x00007c1bU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func006.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func007.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func007.c new file mode 100644 index 0000000000..af149d184a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func007.c @@ -0,0 +1,297 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func007(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[0]; + SCE->REG_100H = S_HEAP[1]; + SCE->REG_100H = S_HEAP[2]; + SCE->REG_100H = S_HEAP[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[4]; + SCE->REG_100H = S_HEAP[5]; + SCE->REG_100H = S_HEAP[6]; + SCE->REG_100H = S_HEAP[7]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000094U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[8]; + SCE->REG_100H = S_HEAP[9]; + SCE->REG_100H = S_HEAP[10]; + SCE->REG_100H = S_HEAP[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[12]; + SCE->REG_100H = S_HEAP[13]; + SCE->REG_100H = S_HEAP[14]; + SCE->REG_100H = S_HEAP[15]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000095U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[16]; + SCE->REG_100H = S_HEAP[17]; + SCE->REG_100H = S_HEAP[18]; + SCE->REG_100H = S_HEAP[19]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[20]; + SCE->REG_100H = S_HEAP[21]; + SCE->REG_100H = S_HEAP[22]; + SCE->REG_100H = S_HEAP[23]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[24]; + SCE->REG_100H = S_HEAP[25]; + SCE->REG_100H = S_HEAP[26]; + SCE->REG_100H = S_HEAP[27]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[28]; + SCE->REG_100H = S_HEAP[29]; + SCE->REG_100H = S_HEAP[30]; + SCE->REG_100H = S_HEAP[31]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[32]; + SCE->REG_100H = S_HEAP[33]; + SCE->REG_100H = S_HEAP[34]; + SCE->REG_100H = S_HEAP[35]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[36]; + SCE->REG_100H = S_HEAP[37]; + SCE->REG_100H = S_HEAP[38]; + SCE->REG_100H = S_HEAP[39]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000092U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[40]; + SCE->REG_100H = S_HEAP[41]; + SCE->REG_100H = S_HEAP[42]; + SCE->REG_100H = S_HEAP[43]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[44]; + SCE->REG_100H = S_HEAP[45]; + SCE->REG_100H = S_HEAP[46]; + SCE->REG_100H = S_HEAP[47]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000093U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[48]; + SCE->REG_100H = S_HEAP[49]; + SCE->REG_100H = S_HEAP[50]; + SCE->REG_100H = S_HEAP[51]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[52]; + SCE->REG_100H = S_HEAP[53]; + SCE->REG_100H = S_HEAP[54]; + SCE->REG_100H = S_HEAP[55]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[56]; + SCE->REG_100H = S_HEAP[57]; + SCE->REG_100H = S_HEAP[58]; + SCE->REG_100H = S_HEAP[59]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[60]; + SCE->REG_100H = S_HEAP[61]; + SCE->REG_100H = S_HEAP[62]; + SCE->REG_100H = S_HEAP[63]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[64]; + SCE->REG_100H = S_HEAP[65]; + SCE->REG_100H = S_HEAP[66]; + SCE->REG_100H = S_HEAP[67]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func007.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func008.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func008.c new file mode 100644 index 0000000000..0fec68c39e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func008.c @@ -0,0 +1,234 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func008(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_34H = 0x00000403U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x80006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000806U; + SCE->REG_24H = 0x80006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000900cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000030U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000900cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000001U; + SCE->REG_24H = 0x80000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_34H = 0x00000001U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func008.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func009.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func009.c new file mode 100644 index 0000000000..2858c9f1b1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func009.c @@ -0,0 +1,255 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func009(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x800098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000ac0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x8000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x8000c8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x8088000aU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x000000a5U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x8088000aU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8088000aU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x0000002aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_E0H = 0x8088000aU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x000000adU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x0000080cU; + SCE->REG_24H = 0x8000f4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000810U; + SCE->REG_24H = 0x80009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000808U; + SCE->REG_24H = 0x80009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000808U; + SCE->REG_24H = 0x8000b0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func009.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func010.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func010.c new file mode 100644 index 0000000000..b50c7f8991 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func010.c @@ -0,0 +1,1047 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func010_r1(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_28H = 0x00870001U; + OFS_ADR = ARG1; + R_SCE_func100(0xa3e58761U, 0x4784d143U, 0xd2c20f17U, 0x60f15828U); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000403U; + SCE->REG_24H = 0x8000e8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010360U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f5U); + R_SCE_func101(0xc1699819U, 0x44c32a09U, 0x6e4449e4U, 0xe19b248fU); + R_SCE_func006(); + R_SCE_func100(0x728b5ca6U, 0x61eaaec6U, 0xa08796bdU, 0x847497a1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x52a0e566U, 0xf2aff9fbU, 0xc070f093U, 0xe02ec2d5U); + } + else + { + R_SCE_func100(0xe355b0b0U, 0xdf09216dU, 0x1fc3dff0U, 0xc1445cc7U); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x2fd881feU, 0x166cc540U, 0x154508a9U, 0x06fa0f49U); + R_SCE_func103(); + R_SCE_func100(0xa25ef88bU, 0xd16125abU, 0xf37f1dedU, 0x2a1cead5U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01080c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0xd3c41c27U, 0xefd89eaeU, 0xbaadce2bU, 0x046f46acU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000aaU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[0] = SCE->REG_100H; + S_HEAP[1] = SCE->REG_100H; + S_HEAP[2] = SCE->REG_100H; + S_HEAP[3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[4] = SCE->REG_100H; + S_HEAP[5] = SCE->REG_100H; + S_HEAP[6] = SCE->REG_100H; + S_HEAP[7] = SCE->REG_100H; + R_SCE_func100(0x0c559c4dU, 0x82ebbaaaU, 0x40f747edU, 0x77c11716U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000abU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[8] = SCE->REG_100H; + S_HEAP[9] = SCE->REG_100H; + S_HEAP[10] = SCE->REG_100H; + S_HEAP[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[12] = SCE->REG_100H; + S_HEAP[13] = SCE->REG_100H; + S_HEAP[14] = SCE->REG_100H; + S_HEAP[15] = SCE->REG_100H; + R_SCE_func100(0xb77baa6cU, 0xb802375cU, 0xf3db14f0U, 0x4337331bU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000a8U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[16] = SCE->REG_100H; + S_HEAP[17] = SCE->REG_100H; + S_HEAP[18] = SCE->REG_100H; + S_HEAP[19] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[20] = SCE->REG_100H; + S_HEAP[21] = SCE->REG_100H; + S_HEAP[22] = SCE->REG_100H; + S_HEAP[23] = SCE->REG_100H; + R_SCE_func100(0x1cc07cd9U, 0x4df1a983U, 0x8ed6d11fU, 0xc1a3cb39U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000a9U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[24] = SCE->REG_100H; + S_HEAP[25] = SCE->REG_100H; + S_HEAP[26] = SCE->REG_100H; + S_HEAP[27] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[28] = SCE->REG_100H; + S_HEAP[29] = SCE->REG_100H; + S_HEAP[30] = SCE->REG_100H; + S_HEAP[31] = SCE->REG_100H; + R_SCE_func100(0x61f969c3U, 0x0fbab58bU, 0x97b49f41U, 0xc3b4b092U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x0000002aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[32] = SCE->REG_100H; + S_HEAP[33] = SCE->REG_100H; + S_HEAP[34] = SCE->REG_100H; + S_HEAP[35] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[36] = SCE->REG_100H; + S_HEAP[37] = SCE->REG_100H; + S_HEAP[38] = SCE->REG_100H; + S_HEAP[39] = SCE->REG_100H; + R_SCE_func100(0x44f63baeU, 0x210b6b25U, 0xb4d0e8dbU, 0xe017b826U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x0000002bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[40] = SCE->REG_100H; + S_HEAP[41] = SCE->REG_100H; + S_HEAP[42] = SCE->REG_100H; + S_HEAP[43] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[44] = SCE->REG_100H; + S_HEAP[45] = SCE->REG_100H; + S_HEAP[46] = SCE->REG_100H; + S_HEAP[47] = SCE->REG_100H; + R_SCE_func100(0x8f08c6beU, 0x60716a73U, 0xe90c26aaU, 0xc7721d8bU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[48] = SCE->REG_100H; + S_HEAP[49] = SCE->REG_100H; + S_HEAP[50] = SCE->REG_100H; + S_HEAP[51] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[52] = SCE->REG_100H; + S_HEAP[53] = SCE->REG_100H; + S_HEAP[54] = SCE->REG_100H; + S_HEAP[55] = SCE->REG_100H; + R_SCE_func100(0x7ac3c7c5U, 0x62d6031cU, 0x6638c658U, 0xf155dee3U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[56] = SCE->REG_100H; + S_HEAP[57] = SCE->REG_100H; + S_HEAP[58] = SCE->REG_100H; + S_HEAP[59] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[60] = SCE->REG_100H; + S_HEAP[61] = SCE->REG_100H; + S_HEAP[62] = SCE->REG_100H; + S_HEAP[63] = SCE->REG_100H; + R_SCE_func100(0xf7cc5b15U, 0x35014d18U, 0xdaa7b0caU, 0x336d57f9U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[64] = SCE->REG_100H; + S_HEAP[65] = SCE->REG_100H; + S_HEAP[66] = SCE->REG_100H; + S_HEAP[67] = SCE->REG_100H; + R_SCE_func100(0xb2458f0eU, 0xb7239865U, 0x3f364418U, 0x10fec43aU); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000403U; + SCE->REG_24H = 0x8000e8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x800058d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x8000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + SCE->REG_2CH = 0x00000094U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000908U; + SCE->REG_E0H = 0x81900008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0002b208U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x3acf6dc6U, 0xd7c2978fU, 0x7b836d7eU, 0x3045c605U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0xc951ba02U, 0x1cfe5807U, 0x2a21b050U, 0x4c0b36f7U); + } + else + { + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x8000fcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xccb973c0U, 0xc1d1659cU, 0x79fb095dU, 0x74880771U); + R_SCE_func009(); + R_SCE_func100(0x9c6a7796U, 0x294e7ae0U, 0x2828963fU, 0x29f2496bU); + SCE->REG_34H = 0x00000410U; + SCE->REG_24H = 0x800098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func005_r1(OFS_ADR); + R_SCE_func100(0x6c58093aU, 0x7a6cee3bU, 0xefefda33U, 0x32afcf9eU); + SCE->REG_34H = 0x00000110U; + SCE->REG_24H = 0x800019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000110U; + SCE->REG_24H = 0x80001ec0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000330U; + SCE->REG_24H = 0x800019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000330U; + SCE->REG_24H = 0x80001ec0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func011(S_HEAP); + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00231030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x51b991e0U, 0xb5c55aefU, 0xd420ca0bU, 0xfdac0d48U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x968937ffU, 0xcb874811U, 0xcaf93400U, 0x8ae79797U); + } + else + { + SCE->REG_24H = 0x0000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000b20cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000908U; + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000908U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00008c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000a4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0002b208U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00a10000U; + R_SCE_func100(0xdb198263U, 0x80cd38c6U, 0x36b80d5cU, 0x832a7068U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x4015da74U, 0xe22c4e5dU, 0xddab7197U, 0x1911a758U); + } + else + { + SCE->REG_ECH = 0x0000d000U; + R_SCE_func101(0x7a0dcfdaU, 0xf8651439U, 0x37ae8b10U, 0x6aba4842U); + } + } + } + } + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func010_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func011.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func011.c new file mode 100644 index 0000000000..0f9d9d0b89 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func011.c @@ -0,0 +1,297 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func011(uint32_t* ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[0]; + SCE->REG_100H = ARG1[1]; + SCE->REG_100H = ARG1[2]; + SCE->REG_100H = ARG1[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[4]; + SCE->REG_100H = ARG1[5]; + SCE->REG_100H = ARG1[6]; + SCE->REG_100H = ARG1[7]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000094U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[8]; + SCE->REG_100H = ARG1[9]; + SCE->REG_100H = ARG1[10]; + SCE->REG_100H = ARG1[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[12]; + SCE->REG_100H = ARG1[13]; + SCE->REG_100H = ARG1[14]; + SCE->REG_100H = ARG1[15]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000095U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[16]; + SCE->REG_100H = ARG1[17]; + SCE->REG_100H = ARG1[18]; + SCE->REG_100H = ARG1[19]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[20]; + SCE->REG_100H = ARG1[21]; + SCE->REG_100H = ARG1[22]; + SCE->REG_100H = ARG1[23]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[24]; + SCE->REG_100H = ARG1[25]; + SCE->REG_100H = ARG1[26]; + SCE->REG_100H = ARG1[27]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[28]; + SCE->REG_100H = ARG1[29]; + SCE->REG_100H = ARG1[30]; + SCE->REG_100H = ARG1[31]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[32]; + SCE->REG_100H = ARG1[33]; + SCE->REG_100H = ARG1[34]; + SCE->REG_100H = ARG1[35]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[36]; + SCE->REG_100H = ARG1[37]; + SCE->REG_100H = ARG1[38]; + SCE->REG_100H = ARG1[39]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000092U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[40]; + SCE->REG_100H = ARG1[41]; + SCE->REG_100H = ARG1[42]; + SCE->REG_100H = ARG1[43]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[44]; + SCE->REG_100H = ARG1[45]; + SCE->REG_100H = ARG1[46]; + SCE->REG_100H = ARG1[47]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000093U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[48]; + SCE->REG_100H = ARG1[49]; + SCE->REG_100H = ARG1[50]; + SCE->REG_100H = ARG1[51]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[52]; + SCE->REG_100H = ARG1[53]; + SCE->REG_100H = ARG1[54]; + SCE->REG_100H = ARG1[55]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[56]; + SCE->REG_100H = ARG1[57]; + SCE->REG_100H = ARG1[58]; + SCE->REG_100H = ARG1[59]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[60]; + SCE->REG_100H = ARG1[61]; + SCE->REG_100H = ARG1[62]; + SCE->REG_100H = ARG1[63]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[64]; + SCE->REG_100H = ARG1[65]; + SCE->REG_100H = ARG1[66]; + SCE->REG_100H = ARG1[67]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func011.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func022.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func022.c new file mode 100644 index 0000000000..eb34da6702 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func022.c @@ -0,0 +1,79 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func022(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000017U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000015U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000013U; + SCE->REG_ECH = 0x00000080U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func022.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func023.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func023.c new file mode 100644 index 0000000000..2a8cac0289 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func023.c @@ -0,0 +1,79 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func023(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000016U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000012U; + SCE->REG_ECH = 0x00000080U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func023.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func025.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func025.c new file mode 100644 index 0000000000..8153cf036a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func025.c @@ -0,0 +1,354 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func025_r1(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x018473b6U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01ab9622U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0138e816U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00870001U; + SCE->REG_C4H = 0x00443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c3e1cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x02f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+120 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+120 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+120 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+120 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+124 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+124 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+124 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+124 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000104U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+128 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+128 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+128 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+128 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+132 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+132 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+132 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+132 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000018U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000108U; + SCE->REG_24H = 0x800012c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+136 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+136 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+136 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+136 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+140 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+140 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+140 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+140 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000091U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000304U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+144 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+144 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+144 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+144 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+148 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+148 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+148 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+148 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000019U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000308U; + SCE->REG_24H = 0x800016c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+152 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+152 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+152 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+152 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+156 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+156 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+156 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+156 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000092U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+160 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+160 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+160 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+160 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+164 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+164 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+164 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+164 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000093U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+168 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+168 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+168 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+168 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+172 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+172 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+172 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+172 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+176 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+176 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+176 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+176 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+180 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+180 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+180 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+180 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+184 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+184 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+184 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+184 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func025_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func027.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func027.c new file mode 100644 index 0000000000..b27f23986d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func027.c @@ -0,0 +1,326 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func027_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01305c44U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0142859dU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_C4H = 0x00443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c3e1cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00003b62U; + SCE->REG_D0H = 0x00000e00U; + SCE->REG_C4H = 0x02f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+28 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+32 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+36 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 3]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x00000015U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+40 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+44 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+48 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 3]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+52 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+56 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+60 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 3]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x0000001dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+64 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+68 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+72 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 3]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x0000001cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+76 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+80 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+84 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 3]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x00000200U; + SCE->REG_C4H = 0x00f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+88 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+92 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+96 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 3]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+100 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func027_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func028.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func028.c new file mode 100644 index 0000000000..c9e72411ba --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func028.c @@ -0,0 +1,183 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func028_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01166403U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x013659ffU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_C4H = 0x00443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c3e1cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00001762U; + SCE->REG_D0H = 0x00000500U; + SCE->REG_C4H = 0x02f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+0 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+4 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+8 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 3]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+12 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+16 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+20 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 3]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+24 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func028_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func030.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func030.c new file mode 100644 index 0000000000..033342ed30 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func030.c @@ -0,0 +1,92 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func030(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000b4a0U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x1000b4c0U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_ECH = 0x1000b4e0U; + SCE->REG_ECH = 0x00000009U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x1000b4a0U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x1000b4c0U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_ECH = 0x1000b4e0U; + SCE->REG_ECH = 0x0000000dU; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x1000b4a0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x1000b4c0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_ECH = 0x1000b4e0U; + SCE->REG_ECH = 0x0000000dU; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func030.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func040.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func040.c new file mode 100644 index 0000000000..7b11e27fdc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func040.c @@ -0,0 +1,100 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func040(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x6c4af65bU, 0x374ae9f9U, 0x061f66eaU, 0xb45c10feU); + SCE->REG_C4H = 0x20443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x20083e1cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ea725dU); + R_SCE_func100(0xc2589885U, 0x833a518fU, 0xf17e6423U, 0x7b134d37U); + SCE->REG_C4H = 0x20443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x20093e1cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x02ea725dU); + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func040.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func043.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func043.c new file mode 100644 index 0000000000..7f47ecbde2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func043.c @@ -0,0 +1,176 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func043(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x4eca480aU, 0xf8aa4483U, 0xee3a2733U, 0x15d5c185U); + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x000001d0U; + SCE->REG_E0H = 0x8188000aU; + SCE->REG_C4H = 0x00080805U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x8b5d6b0aU, 0xbee22289U, 0x3211327fU, 0xabf736b0U); + SCE->REG_C4H = 0x00090805U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x72e72278U, 0xce027894U, 0xb60d35d2U, 0xe5ac20fbU); + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x000001c0U; + SCE->REG_E0H = 0x8184000aU; + SCE->REG_C4H = 0x000c0805U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xa59c2239U, 0xa1b3d892U, 0xf9d4181eU, 0x580d124eU); + SCE->REG_C4H = 0x00000b8cU; + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80040140U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00008d40U; + SCE->REG_ECH = 0x00ffffffU; + SCE->REG_ECH = 0x00009140U; + SCE->REG_ECH = 0x01000000U; + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00448a04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00008e95U; + SCE->REG_E0H = 0x81040140U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00008d40U; + SCE->REG_ECH = 0x00ffffffU; + SCE->REG_ECH = 0x00009140U; + SCE->REG_ECH = 0x02000000U; + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00448a04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00098e15U; + SCE->REG_E0H = 0x81040140U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x748f8130U, 0x9b736d6fU, 0x7098dca3U, 0xe06c1677U); + SCE->REG_C4H = 0x00080805U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func043.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func044.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func044.c new file mode 100644 index 0000000000..ad0e1b2cbe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func044.c @@ -0,0 +1,126 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func044(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xcbc1d054U, 0xb53a07e9U, 0x4e7ce350U, 0x018416b4U); + SCE->REG_ECH = 0x00008ce0U; + SCE->REG_ECH = 0x00ffffffU; + SCE->REG_ECH = 0x000090e0U; + SCE->REG_ECH = 0x01000000U; + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00448a04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00008e94U; + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00008ce0U; + SCE->REG_ECH = 0x00ffffffU; + SCE->REG_ECH = 0x000090e0U; + SCE->REG_ECH = 0x02000000U; + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00448a04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00098e14U; + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd9c982f6U, 0x988082a5U, 0xd9d6f51cU, 0x4dc1c446U); + SCE->REG_C4H = 0x00080805U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func044.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func048.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func048.c new file mode 100644 index 0000000000..4275f2da3e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func048.c @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func048(uint32_t* ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1[0]); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func048.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func049.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func049.c new file mode 100644 index 0000000000..763810ff3d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func049.c @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func049(uint32_t* ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010080U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1[0]); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func049.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func050.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func050.c new file mode 100644 index 0000000000..0799f7620c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func050.c @@ -0,0 +1,72 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func050(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0xf597806AU; + SCE->REG_F0H = 0x00000000U; + SCE->REG_14H = 0x10000000U; + SCE->REG_10CH = change_endian_long(ARG1); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func050.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func051.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func051.c new file mode 100644 index 0000000000..89cfdad103 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func051.c @@ -0,0 +1,71 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func051(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0xf597806AU; + SCE->REG_F0H = 0x00000000U; + SCE->REG_10CH = 0x00010001U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func051.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func052.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func052.c new file mode 100644 index 0000000000..6432d595c4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func052.c @@ -0,0 +1,80 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func052(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func051(); + SCE->REG_28H = 0x00000001U; + SCE->REG_3CH = change_endian_long(ARG1); + SCE->REG_14H = 0x00003008U; + SCE->REG_14H = 0x00003018U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func052.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func053.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func053.c new file mode 100644 index 0000000000..0876d6e9e7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func053.c @@ -0,0 +1,80 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func053(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func051(); + SCE->REG_80H = 0x00000001U; + SCE->REG_8CH = change_endian_long(ARG1); + SCE->REG_14H = 0x00003008U; + SCE->REG_14H = 0x00003018U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func053.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func054.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func054.c new file mode 100644 index 0000000000..67312ae558 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func054.c @@ -0,0 +1,72 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func054(uint32_t ARG1, uint32_t ARG2) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_14H = change_endian_long(ARG1); + SCE->REG_14H = change_endian_long(ARG2); + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func054.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func057.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func057.c new file mode 100644 index 0000000000..621720ebed --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func057.c @@ -0,0 +1,520 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func057_r3(uint32_t* ARG1, uint32_t* ARG2, uint32_t* ARG3) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xb5fa2aa7U, 0x59fc8a39U, 0x574c4badU, 0x1cb2c0faU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[0]; + SCE->REG_100H = ARG1[1]; + SCE->REG_100H = ARG1[2]; + SCE->REG_100H = ARG1[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000ffU); + R_SCE_func101(0x43c21d19U, 0x2690df3eU, 0xe50a58e7U, 0xc4a2b4f9U); + R_SCE_func043(); + SCE->REG_ECH = 0x000034e4U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000feU); + R_SCE_func101(0x6b73e029U, 0x554c9c6bU, 0x8ef8d0dcU, 0x88940519U); + R_SCE_func044(); + R_SCE_func100(0x497677e9U, 0x83adb760U, 0x0f956503U, 0x53d97513U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func081(); + SCE->REG_ECH = 0x00007c01U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x122f2c5fU, 0xe220aef4U, 0xbcb4a9fcU, 0xb6936250U); + SCE->REG_00H = 0x80002100U; + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00d049a6U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02e087b6U; + SCE->REG_04H = 0x0000c200U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[0]; + SCE->REG_100H = ARG2[1]; + SCE->REG_100H = ARG2[2]; + SCE->REG_100H = ARG2[3]; + for (iLoop = 0; iLoop < (INST_DATA_SIZE-8) ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[4+iLoop + 0]; + SCE->REG_100H = ARG2[4+iLoop + 1]; + SCE->REG_100H = ARG2[4+iLoop + 2]; + SCE->REG_100H = ARG2[4+iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+iLoop + 0] = SCE->REG_100H; + ARG3[1+iLoop + 1] = SCE->REG_100H; + ARG3[1+iLoop + 2] = SCE->REG_100H; + ARG3[1+iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+iLoop + 0] = SCE->REG_100H; + ARG3[1+iLoop + 1] = SCE->REG_100H; + ARG3[1+iLoop + 2] = SCE->REG_100H; + ARG3[1+iLoop + 3] = SCE->REG_100H; + iLoop = iLoop + 4; + oLoop = iLoop; + R_SCE_func202();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0xae42bbf5U, 0x719d12c0U, 0x28a9c4baU, 0x5417ca87U); + } + else if (0x0a000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x15c14dd7U, 0xf7e17e56U, 0x5936cd8bU, 0xc7e17967U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_00H = 0x00003183U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func061(0,ARG2); + iLoop = 0 + 32; + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x02e08887U; + SCE->REG_04H = 0x00000282U; + for(oLoop=0; oLoop<32; oLoop=oLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x283cb8a9U, 0xc6ebc99bU, 0xc90412f2U, 0xa43d389bU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + iLoop = iLoop + 4; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e08885U; + SCE->REG_00H = 0x00002113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + R_SCE_func100(0xa3ba6d53U, 0x799a8942U, 0x31fc06e6U, 0x45eb9319U); + R_SCE_func060(); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func062(36,ARG3); + oLoop = 36 + 32; + R_SCE_func101(0xc00f0ff8U, 0xd2a607a6U, 0xdd98d770U, 0xcf9f172cU); + } + else if (0x0b000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0xb23ee3a6U, 0x980de4c5U, 0x357824d0U, 0x0cabf2b8U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_00H = 0x00003183U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func061(0,ARG2); + iLoop = 0 + 32; + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func062(0,ARG3); + oLoop = 0 + 32; + R_SCE_func100(0x458fc640U, 0x50261cc3U, 0xe4202208U, 0x6d0a4b50U); + SCE->REG_00H = 0x00003183U; + SCE->REG_2CH = 0x00000011U; + R_SCE_func061(32,ARG2); + iLoop = 32 + 32; + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000021U; + R_SCE_func062(32,ARG3); + oLoop = 32 + 32; + R_SCE_func100(0x9f976c71U, 0xf7735f2aU, 0x0200a790U, 0xbe03fb66U); + R_SCE_func060(); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func062(64,ARG3); + oLoop = 64 + 32; + R_SCE_func101(0xe1f95173U, 0x22b9c4c5U, 0x0bcaf056U, 0xa4438138U); + } + else if (0x0c000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x41312fdfU, 0xf45eb02bU, 0x0507f044U, 0x582d0555U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_00H = 0x00013103U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func063(0,ARG2); + iLoop = 0 + 64; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x02e08887U; + SCE->REG_04H = 0x00000202U; + for(oLoop=0; oLoop<64; oLoop=oLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x3536950cU, 0xaa005c53U, 0x17df86caU, 0xe41d70f6U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + iLoop = iLoop + 4; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e08885U; + SCE->REG_00H = 0x00002113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + R_SCE_func100(0x5356fbabU, 0xaa4e174dU, 0xd9b892faU, 0x5160840bU); + R_SCE_func060(); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func064(68,ARG3); + oLoop = 68 + 64; + R_SCE_func101(0x1ae55db3U, 0xf757fc20U, 0x0b5726e7U, 0xd6b1f58fU); + } + else if (0x0d000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0xb6fe6903U, 0xbd2a18b0U, 0xe45fbb4aU, 0xaa7a49a8U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_00H = 0x00013103U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func063(0,ARG2); + iLoop = 0 + 64; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func064(0,ARG3); + oLoop = 0 + 64; + R_SCE_func100(0x56902e0fU, 0xdd31160dU, 0xe0d9af9bU, 0x0522e107U); + SCE->REG_00H = 0x00013103U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func063(64,ARG2); + iLoop = 64 + 64; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func064(64,ARG3); + oLoop = 64 + 64; + R_SCE_func100(0x1343a428U, 0x294890b2U, 0x4934f23bU, 0x9dd420c0U); + R_SCE_func060(); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func064(128,ARG3); + oLoop = 128 + 64; + R_SCE_func101(0x7ce803d0U, 0x63acd9bcU, 0xe94d8c2cU, 0xd0dc55d5U); + } + else if (0x12000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x93159ddcU, 0xd692ed5aU, 0xb444f63cU, 0x838a92f9U); + SCE->REG_00H = 0x80002100U; + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00d049a6U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02e08886U; + SCE->REG_04H = 0x0000c200U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[0]; + SCE->REG_100H = ARG2[1]; + SCE->REG_100H = ARG2[2]; + SCE->REG_100H = ARG2[3]; + for (iLoop = 0; iLoop < (INST_DATA_SIZE-8) ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[4+iLoop + 0]; + SCE->REG_100H = ARG2[4+iLoop + 1]; + SCE->REG_100H = ARG2[4+iLoop + 2]; + SCE->REG_100H = ARG2[4+iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+iLoop + 0] = SCE->REG_100H; + ARG3[1+iLoop + 1] = SCE->REG_100H; + ARG3[1+iLoop + 2] = SCE->REG_100H; + ARG3[1+iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+iLoop + 0] = SCE->REG_100H; + ARG3[1+iLoop + 1] = SCE->REG_100H; + ARG3[1+iLoop + 2] = SCE->REG_100H; + ARG3[1+iLoop + 3] = SCE->REG_100H; + iLoop = iLoop + 4; + oLoop = iLoop; + R_SCE_func202();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0xfc1ed21cU, 0x83b5b45bU, 0x7df40298U, 0xe26f3919U); + } + R_SCE_func100(0x1d10f3f2U, 0xaae17e31U, 0xe4f361daU, 0x007171faU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00007c1cU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func057_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func059.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func059.c new file mode 100644 index 0000000000..28f5fc41a2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func059.c @@ -0,0 +1,106 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func059(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x360cd89eU, 0xcbf6aa10U, 0xf73f5dbbU, 0x7474f188U); + SCE->REG_ECH = 0x00008d40U; + SCE->REG_ECH = 0x00ffffffU; + SCE->REG_ECH = 0x00009140U; + SCE->REG_ECH = 0x01000000U; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00442a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x00082e0dU; + SCE->REG_E0H = 0x81040140U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xbe97f1d5U, 0xcf552fedU, 0xec1700ddU, 0x9edff943U); + SCE->REG_ECH = 0x00008d40U; + SCE->REG_ECH = 0x00ffffffU; + SCE->REG_ECH = 0x00009140U; + SCE->REG_ECH = 0x02000000U; + SCE->REG_C4H = 0x00092e0dU; + SCE->REG_E0H = 0x81040140U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func059.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func060.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func060.c new file mode 100644 index 0000000000..8bfcdb89ee --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func060.c @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func060(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x00004404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func060.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func061.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func061.c new file mode 100644 index 0000000000..787cc67b38 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func061.c @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func061(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00001f61U; + SCE->REG_B0H = 0x00000700U; + SCE->REG_A4H = 0x00d0c9a7U; + for(iLoop=ARG1; iLoopREG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func061.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func062.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func062.c new file mode 100644 index 0000000000..958e89fd31 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func062.c @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func062(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000282U; + for(oLoop=ARG1; oLoopREG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func062.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func063.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func063.c new file mode 100644 index 0000000000..df5f058bf8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func063.c @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func063(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00003f61U; + SCE->REG_B0H = 0x00000f00U; + SCE->REG_A4H = 0x00d0c9a7U; + for(iLoop=ARG1; iLoopREG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func063.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func064.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func064.c new file mode 100644 index 0000000000..0c64d00e44 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func064.c @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func064(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000202U; + for(oLoop=ARG1; oLoopREG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func064.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func068.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func068.c new file mode 100644 index 0000000000..1ebcfcb495 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func068.c @@ -0,0 +1,106 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func068(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xe6b68cd4U, 0xf4f72556U, 0x97e00a50U, 0x44ef2fa0U); + SCE->REG_ECH = 0x00008d40U; + SCE->REG_ECH = 0x00ffffffU; + SCE->REG_ECH = 0x00009140U; + SCE->REG_ECH = 0x01000000U; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00442a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x00082e0cU; + SCE->REG_E0H = 0x81010140U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x4b48b267U, 0x75c1d1afU, 0xe49c17d3U, 0xc0bf38eeU); + SCE->REG_ECH = 0x00008d40U; + SCE->REG_ECH = 0x00ffffffU; + SCE->REG_ECH = 0x00009140U; + SCE->REG_ECH = 0x02000000U; + SCE->REG_C4H = 0x00092e0cU; + SCE->REG_E0H = 0x81010140U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func068.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func069.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func069.c new file mode 100644 index 0000000000..b16e0e881c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func069.c @@ -0,0 +1,157 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func069(uint32_t* ARG1, uint32_t ARG2) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x2036318fU, 0x3ed26c48U, 0x9ea4ee9cU, 0x043eb99eU); + SCE->REG_C4H = 0x00443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c3e1cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0174d08aU); + R_SCE_func100(0x4ca1777fU, 0xede51934U, 0x42927c2dU, 0x11f34924U); + SCE->REG_ECH = 0x00009020U; + SCE->REG_ECH = 0x01000000U; + SCE->REG_C4H = 0x00440a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c0e1cU; + SCE->REG_E0H = 0x81010020U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x689e55d6U, 0x1a48d167U, 0xbea2e6d3U, 0x58ba682cU); + SCE->REG_A4H = 0x02fb073dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG2 + 0]; + SCE->REG_100H = S_FLASH2[ARG2 + 1]; + SCE->REG_100H = S_FLASH2[ARG2 + 2]; + SCE->REG_100H = S_FLASH2[ARG2 + 3]; + R_SCE_func100(0xd1b6bac4U, 0xa95fcbe3U, 0x1ceb8b25U, 0x34e7b36cU); + SCE->REG_A4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG2+4 + 0]; + SCE->REG_100H = S_FLASH2[ARG2+4 + 1]; + SCE->REG_100H = S_FLASH2[ARG2+4 + 2]; + SCE->REG_100H = S_FLASH2[ARG2+4 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00087a05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[0]; + SCE->REG_100H = ARG1[1]; + SCE->REG_100H = ARG1[2]; + SCE->REG_100H = ARG1[3]; + R_SCE_func100(0x84658f6dU, 0x742293b1U, 0x7f99c5aaU, 0x19aa0bddU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00097a05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[4]; + SCE->REG_100H = ARG1[5]; + SCE->REG_100H = ARG1[6]; + SCE->REG_100H = ARG1[7]; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func069.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func070.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func070.c new file mode 100644 index 0000000000..a0a193adc1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func070.c @@ -0,0 +1,282 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func070_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003340U; + SCE->REG_ECH = 0x00050020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0131ec45U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x014bb610U; + SCE->REG_ECH = 0x00070040U; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01542614U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01ba24feU; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01bb59d6U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00870001U; + SCE->REG_C4H = 0x00443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c3e1cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00002f62U; + SCE->REG_D0H = 0x00000b00U; + SCE->REG_C4H = 0x02f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+68 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+72 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000015U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+76 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+80 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+84 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+88 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+92 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+96 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+100 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+104 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+108 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+112 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+116 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func070_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func071.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func071.c new file mode 100644 index 0000000000..8dee411f20 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func071.c @@ -0,0 +1,334 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func071_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003340U; + SCE->REG_ECH = 0x00050020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x017d423aU; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0163c737U; + SCE->REG_ECH = 0x00070040U; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x017c67d8U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0126ddb5U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01bcfa36U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00870001U; + SCE->REG_C4H = 0x00443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000c3e1cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x02f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+0 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+4 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+8 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+12 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+16 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+20 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000098U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+24 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+28 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000099U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+32 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+36 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000094U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+40 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+44 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000095U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+48 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+52 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+56 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+60 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 3]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+64 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func071_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func073.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func073.c new file mode 100644 index 0000000000..619706350a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func073.c @@ -0,0 +1,1047 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func073_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_28H = 0x00870001U; + OFS_ADR = ARG1; + R_SCE_func100(0x5494a7e5U, 0xed0d7466U, 0xa092dc78U, 0x3ca4558fU); + R_SCE_func070_r2(OFS_ADR); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000403U; + SCE->REG_24H = 0x8000e8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010360U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f1U); + R_SCE_func101(0x8ad3d2cdU, 0x5e779bb7U, 0x0e85d5baU, 0x24e51ed7U); + R_SCE_func006(); + R_SCE_func100(0x3eab9b2cU, 0x1bb56cf8U, 0x80e22677U, 0xb8c0e8adU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x1cbf07d8U, 0xbc46e258U, 0x0989cfa2U, 0xfb2caab8U); + } + else + { + R_SCE_func100(0x5f223b5dU, 0xba508857U, 0x27e54efdU, 0x022e4c01U); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000010U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xa1877d3cU, 0x0331b725U, 0xb2a3b08eU, 0xf5d7db38U); + R_SCE_func103(); + R_SCE_func100(0xcfc2fbf2U, 0x703ecdbcU, 0x113f770bU, 0x8473c0f6U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01080c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0xb16d3e4aU, 0xdc676402U, 0x4b6214d5U, 0xf9efa276U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000aaU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[0] = SCE->REG_100H; + S_HEAP[1] = SCE->REG_100H; + S_HEAP[2] = SCE->REG_100H; + S_HEAP[3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[4] = SCE->REG_100H; + S_HEAP[5] = SCE->REG_100H; + S_HEAP[6] = SCE->REG_100H; + S_HEAP[7] = SCE->REG_100H; + R_SCE_func100(0x6b5acf8eU, 0x206e9286U, 0xc06643e1U, 0x87bf06c1U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000abU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[8] = SCE->REG_100H; + S_HEAP[9] = SCE->REG_100H; + S_HEAP[10] = SCE->REG_100H; + S_HEAP[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[12] = SCE->REG_100H; + S_HEAP[13] = SCE->REG_100H; + S_HEAP[14] = SCE->REG_100H; + S_HEAP[15] = SCE->REG_100H; + R_SCE_func100(0x0a05d835U, 0x6ab17b84U, 0x2bd216acU, 0x080a9292U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000a8U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[16] = SCE->REG_100H; + S_HEAP[17] = SCE->REG_100H; + S_HEAP[18] = SCE->REG_100H; + S_HEAP[19] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[20] = SCE->REG_100H; + S_HEAP[21] = SCE->REG_100H; + S_HEAP[22] = SCE->REG_100H; + S_HEAP[23] = SCE->REG_100H; + R_SCE_func100(0x267fdec4U, 0x8b07b543U, 0x77b10204U, 0x7a951cb7U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000a9U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[24] = SCE->REG_100H; + S_HEAP[25] = SCE->REG_100H; + S_HEAP[26] = SCE->REG_100H; + S_HEAP[27] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[28] = SCE->REG_100H; + S_HEAP[29] = SCE->REG_100H; + S_HEAP[30] = SCE->REG_100H; + S_HEAP[31] = SCE->REG_100H; + R_SCE_func100(0x4c6bd155U, 0x44bf577bU, 0xee3a2c44U, 0x9de04f7aU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x0000002aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[32] = SCE->REG_100H; + S_HEAP[33] = SCE->REG_100H; + S_HEAP[34] = SCE->REG_100H; + S_HEAP[35] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[36] = SCE->REG_100H; + S_HEAP[37] = SCE->REG_100H; + S_HEAP[38] = SCE->REG_100H; + S_HEAP[39] = SCE->REG_100H; + R_SCE_func100(0x20a23b71U, 0x03f89d43U, 0xebab5818U, 0xaaae6467U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x0000002bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[40] = SCE->REG_100H; + S_HEAP[41] = SCE->REG_100H; + S_HEAP[42] = SCE->REG_100H; + S_HEAP[43] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[44] = SCE->REG_100H; + S_HEAP[45] = SCE->REG_100H; + S_HEAP[46] = SCE->REG_100H; + S_HEAP[47] = SCE->REG_100H; + R_SCE_func100(0xf26b0d0bU, 0x01c5202fU, 0xb04de638U, 0x40090be8U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[48] = SCE->REG_100H; + S_HEAP[49] = SCE->REG_100H; + S_HEAP[50] = SCE->REG_100H; + S_HEAP[51] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[52] = SCE->REG_100H; + S_HEAP[53] = SCE->REG_100H; + S_HEAP[54] = SCE->REG_100H; + S_HEAP[55] = SCE->REG_100H; + R_SCE_func100(0xb371889aU, 0xe65f05c8U, 0x10378f82U, 0x4b65089bU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[56] = SCE->REG_100H; + S_HEAP[57] = SCE->REG_100H; + S_HEAP[58] = SCE->REG_100H; + S_HEAP[59] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[60] = SCE->REG_100H; + S_HEAP[61] = SCE->REG_100H; + S_HEAP[62] = SCE->REG_100H; + S_HEAP[63] = SCE->REG_100H; + R_SCE_func100(0xaff0a84dU, 0xd1d74c3aU, 0x6201c09dU, 0x2c9919e2U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[64] = SCE->REG_100H; + S_HEAP[65] = SCE->REG_100H; + S_HEAP[66] = SCE->REG_100H; + S_HEAP[67] = SCE->REG_100H; + R_SCE_func100(0x60a55d8cU, 0x6795ce6fU, 0x0828aaf8U, 0xd4ce851cU); + R_SCE_func070_r2(OFS_ADR); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000403U; + SCE->REG_24H = 0x8000e8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x800058d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x8000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + SCE->REG_2CH = 0x00000094U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000908U; + SCE->REG_E0H = 0x81900008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0002b208U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x61e0c43dU, 0x4c4a90c1U, 0xd4a8dcc5U, 0xcee94750U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x853bd147U, 0x98bd78a0U, 0x7ee4c60aU, 0xfe2f49efU); + } + else + { + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x8000fcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xd3d8f585U, 0x628a7321U, 0xd2f1fad4U, 0x26bd2049U); + R_SCE_func009(); + R_SCE_func100(0xdc8a4af5U, 0x27d85f05U, 0x360b0b28U, 0x51d25448U); + SCE->REG_34H = 0x00000410U; + SCE->REG_24H = 0x800098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func071_r2(OFS_ADR); + R_SCE_func100(0xc3bde520U, 0xb5ca3b2cU, 0x2df162c8U, 0x8c01693aU); + SCE->REG_34H = 0x00000110U; + SCE->REG_24H = 0x800019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000110U; + SCE->REG_24H = 0x80001ec0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000330U; + SCE->REG_24H = 0x800019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000330U; + SCE->REG_24H = 0x80001ec0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func011(S_HEAP); + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00231030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x1b200d82U, 0x6ab73200U, 0x8fe3ed2fU, 0xc6242385U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x47a4d0cfU, 0xf5ccaee3U, 0xfbea38beU, 0xcb49368aU); + } + else + { + SCE->REG_24H = 0x0000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000b20cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000908U; + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000908U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00008c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000a4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0002b208U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00a10000U; + R_SCE_func100(0xa1cff671U, 0x1948b2a1U, 0xfa0d17f2U, 0xf049a4adU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00000800U; + R_SCE_func101(0x501f9387U, 0xa5871675U, 0xdaa1fe30U, 0x89014122U); + } + else + { + SCE->REG_ECH = 0x0000d000U; + R_SCE_func101(0x1f653ae7U, 0x345efc2fU, 0x8513230eU, 0xafd9c18bU); + } + } + } + } + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func073_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func074.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func074.c new file mode 100644 index 0000000000..525cdba6ff --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func074.c @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func074_r1(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003340U; + SCE->REG_ECH = 0x00050020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000023U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001dU; + SCE->REG_ECH = 0x00070040U; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000017U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000015U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000013U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func074_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func075.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func075.c new file mode 100644 index 0000000000..6ab0d58ee8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func075.c @@ -0,0 +1,88 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func075_r1(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003340U; + SCE->REG_ECH = 0x00050020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000022U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_ECH = 0x00070040U; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000016U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000012U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func075_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func076.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func076.c new file mode 100644 index 0000000000..e5773af60f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func076.c @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func076(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000019U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x00000080U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func076.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func077.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func077.c new file mode 100644 index 0000000000..a91b9c492d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func077.c @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func077(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001eU; + SCE->REG_ECH = 0x00000080U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func077.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func080.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func080.c new file mode 100644 index 0000000000..1401f47d26 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func080.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func080(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x00440a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x00080e9cU; + SCE->REG_E0H = 0x81010020U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func080.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func081.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func081.c new file mode 100644 index 0000000000..276ab80241 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func081.c @@ -0,0 +1,150 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func081(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x00003424U; + SCE->REG_ECH = 0x3420a880U; + SCE->REG_ECH = 0x0000000aU; + SCE->REG_ECH = 0x10000821U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000dU; + SCE->REG_ECH = 0x342028e4U; + SCE->REG_ECH = 0x10000821U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000012U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_104H = 0x00000958U; + SCE->REG_E0H = 0x808a001fU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000012U); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000014U); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000016U); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000018U); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000001cU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000001eU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000020U); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000000eU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000010U); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000022U); + for(iLoop=0; iLoop<10; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x00003bdfU; + SCE->REG_ECH = 0x3800089eU; + SCE->REG_ECH = 0x10003427U; + SCE->REG_ECH = 0x000027fdU; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func081.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func100.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func100.c new file mode 100644 index 0000000000..a764f54980 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func100.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func100(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x000f3a8dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B16) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func100.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func101.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func101.c new file mode 100644 index 0000000000..a5f9d5ea32 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func101.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func101(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x000e3a8dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B17) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func101.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func102.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func102.c new file mode 100644 index 0000000000..7ff66330af --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func102.c @@ -0,0 +1,78 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x000d3a8dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func102.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func103.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func103.c new file mode 100644 index 0000000000..fce37a3fa2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func103.c @@ -0,0 +1,114 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func103(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000252U; + SCE->REG_C4H = 0x01003774U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x010037f4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x010037f4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x00060805U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01073644U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000b0805U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func103.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func200.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func200.c new file mode 100644 index 0000000000..22b1a13a69 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func200.c @@ -0,0 +1,85 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func200(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_04H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + SCE->REG_1CH = 0x002c0000U; + SCE->REG_1CH = 0x002d0000U; + SCE->REG_B0H = 0x00000001U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000000U; + SCE->REG_1CH = 0x002e0000U; + SCE->REG_1CH = 0x002f0000U; + SCE->REG_D0H = 0x00000001U; + SCE->REG_C4H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func200.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func202.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func202.c new file mode 100644 index 0000000000..752edc2078 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func202.c @@ -0,0 +1,75 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func202(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_04H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + SCE->REG_A4H = 0x00000000U; + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000000U; + SCE->REG_C4H = 0x00000000U; + SCE->REG_1CH = 0x00000900U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func202.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func205.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func205.c new file mode 100644 index 0000000000..8440ee7f4b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func205.c @@ -0,0 +1,78 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func205(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_A8H_b.B6) + { + /* waiting */ + } + SCE->REG_1CH = 0x002c0000U; + SCE->REG_1CH = 0x002d0000U; + SCE->REG_B0H = 0x00000001U; + SCE->REG_A4H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func205.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func206.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func206.c new file mode 100644 index 0000000000..cbe1ed3799 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func206.c @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func206(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_04H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + SCE->REG_1CH = 0x002c0000U; + SCE->REG_1CH = 0x002d0000U; + SCE->REG_B0H = 0x00000001U; + SCE->REG_A4H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func206.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func207.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func207.c new file mode 100644 index 0000000000..573f83eb2b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func207.c @@ -0,0 +1,79 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func207(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_04H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_A8H_b.B6) + { + /* waiting */ + } + SCE->REG_1CH = 0x002c0000U; + SCE->REG_1CH = 0x002d0000U; + SCE->REG_B0H = 0x00000001U; + SCE->REG_A4H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func207.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func300.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func300.c new file mode 100644 index 0000000000..e2da04d534 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func300.c @@ -0,0 +1,1178 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func300(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38008fc0U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x1000381fU; + SCE->REG_ECH = 0x100027e1U; + SCE->REG_ECH = 0x00002fc0U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_ECH = 0x20002c40U; + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x1000d060U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_ECH = 0x2000d061U; + SCE->REG_ECH = 0x38008860U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x5827b5e6U, 0x0adbb8bcU, 0x19dc3fa5U, 0x96422a70U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xde0601d6U, 0x4441332eU, 0x2b790f35U, 0x2f0f54b5U); + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x80000a41U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x80000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280U; + SCE->REG_24H = 0x800019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008860U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xe17382d4U, 0xbc2b724aU, 0x63719741U, 0xb4b36a4cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xb77c8511U, 0x8a463943U, 0x9f12e57dU, 0x56cf6d7eU); + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x55b85d63U, 0x06dc5aafU, 0xaa747e02U, 0xe5f690e2U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x26a1ab54U, 0xbb20a26dU, 0xcd1c0658U, 0x9aaf461eU); + } + else + { + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x4ccf6a83U, 0xb60b8ac2U, 0x0bcb5d75U, 0xb09976b8U); + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x900019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280U; + SCE->REG_24H = 0x800019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800040c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x800012c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x32b56529U, 0x5359ec29U, 0xddf89049U, 0xdf307b63U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x6251bf0bU, 0x5e47c602U, 0x4cd52464U, 0x0ce0b253U); + } + else + { + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xdbc3b158U, 0xcc77e34bU, 0x7a89b27bU, 0x26839762U); + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800060c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000145U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x9c30351fU, 0x8c746876U, 0x763e30c3U, 0x507e7d42U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x5ad49836U, 0x5ec75f50U, 0x6a6eb10fU, 0xeb16cfecU); + } + else + { + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x71c2236dU, 0x7f7565c3U, 0xed8c9b2fU, 0x488aec92U); + } + SCE->REG_ECH = 0x38000bc4U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x0e28e871U, 0x68911775U, 0x5c0e2a26U, 0x1f46065cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002f80U; + R_SCE_func100(0x90fc5456U, 0x1ec510acU, 0x589f1800U, 0x24194fb2U); + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000208U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001141U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x800019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xb4bf4fe6U, 0xe992d7cfU, 0xca7e0753U, 0xe53f79feU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xc99853e5U, 0xed2a9a6dU, 0xe8057ea8U, 0xc93d3893U); + } + else + { + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xe54de8c1U, 0x6539c53eU, 0x6a2045c0U, 0xbe5f6b21U); + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x800002d1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x8000014aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00016c00U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func300.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func301.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func301.c new file mode 100644 index 0000000000..594904a8cd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func301.c @@ -0,0 +1,262 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func301(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800012c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800016c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func301.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func302.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func302.c new file mode 100644 index 0000000000..e66ecd8ace --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func302.c @@ -0,0 +1,1170 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func302(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38008fc0U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x1000381fU; + SCE->REG_ECH = 0x100027e1U; + SCE->REG_ECH = 0x00002fc0U; + SCE->REG_ECH = 0x38008c00U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_ECH = 0x20002c40U; + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xadf2ea2cU, 0x2e445cf9U, 0x80455996U, 0xf2c38ab7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x3800d81fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x23434b1cU, 0xce3d950eU, 0x6044fe6bU, 0xce38fa88U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xb5fd619dU, 0xfe8c3303U, 0x1f805e42U, 0x275ec111U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x3789ad0cU, 0x3b594634U, 0x547c6e10U, 0xda3cda70U); + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x80000a41U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x80000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280U; + SCE->REG_24H = 0x800019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xf62a96dfU, 0xc770e449U, 0x270286ddU, 0x9fc8f9a8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x8b2550b4U, 0x9d61e941U, 0xf83539aaU, 0xe6d91e5bU); + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x44669171U, 0xfa82b075U, 0x6723b09eU, 0x59504dcbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x2b59b119U, 0xbd294ef6U, 0xf4427e36U, 0xdda42933U); + } + else + { + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xd9ca12c5U, 0xb5b78ba5U, 0x4a3858d2U, 0xc4ddd51cU); + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x900019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280U; + SCE->REG_24H = 0x800019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800040c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x800012c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x7cbfdc49U, 0x1aebcd31U, 0xee07bf36U, 0xdc042aafU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xc52665a7U, 0xbacd9ff5U, 0xdc63ede9U, 0xedd212a4U); + } + else + { + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x00e44fadU, 0xbf55df48U, 0x64353b5cU, 0xf2ed3fb2U); + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800060c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000145U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xf4b585a8U, 0xabf37af5U, 0x09ee7e4dU, 0xc882e0aaU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xf4c24636U, 0x73cb9efcU, 0xcec0a4c3U, 0xd521a281U); + } + else + { + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x74b5720cU, 0x83ba22c1U, 0xe798de76U, 0xd4038326U); + } + } + else + { + R_SCE_func101(0x2065e4eeU, 0x27d63aa6U, 0x38fcdf7eU, 0xb53725dbU); + } + SCE->REG_ECH = 0x38000bc4U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x1cfcbb89U, 0x684613d7U, 0x313a1abbU, 0x5f5726f7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002f80U; + R_SCE_func100(0x87f9c856U, 0xc7ca05aaU, 0x6a55a4c9U, 0x2943d6eeU); + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000208U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001141U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x800019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x800002d1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x8000014aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00016c00U; + R_SCE_func101(0xfa943f43U, 0x37fdd85bU, 0xe56a3104U, 0x9e36ce1dU); + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; + } + } + else + { + SCE->REG_ECH = 0x00016c00U; + R_SCE_func101(0x96a8ace5U, 0xcad1b5d4U, 0x88752ce4U, 0xf9bbba59U); + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func302.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func303.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func303.c new file mode 100644 index 0000000000..5da607aec6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func303.c @@ -0,0 +1,170 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func303(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x76020552U, 0x7e2bdf8bU, 0x2a9e19cfU, 0x2e45d635U); + SCE->REG_24H = 0x00005004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000345eU; + SCE->REG_ECH = 0x00026c42U; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0; iLoopREG_ECH = 0x0000381fU; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00016c00U; + R_SCE_func100(0xee62aa0bU, 0xb64faf81U, 0x9b503850U, 0x2f01184dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xed5c5338U, 0x4a7ded33U, 0xc2f07decU, 0x24413714U); + } + else + { + R_SCE_func101(0x2547ab50U, 0x8ca1a46cU, 0x3343101cU, 0x295bc8c2U); + } + } + SCE->REG_ECH = 0x000027e1U; + R_SCE_func101(0x845a232aU, 0x88db9951U, 0x8a3b5d1eU, 0xb30dd7d1U); + } + SCE->REG_ECH = 0x00000be2U; + SCE->REG_ECH = 0x00007c1fU; + SCE->REG_1CH = 0x00602000U; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func303.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func304.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func304.c new file mode 100644 index 0000000000..37776a9847 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func304.c @@ -0,0 +1,2171 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func304_r1(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000024U; + SCE->REG_ECH = 0x00003c1eU; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000d779U; + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x00000b18U; + SCE->REG_E0H = 0x80010300U; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x000000adU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000031fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x3800db1fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x4f14f489U, 0xfa10fda3U, 0xda4c5453U, 0xf2914203U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x30aacd26U, 0xc5edc197U, 0xddbcc6a2U, 0x57abf381U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000d379U; + R_SCE_func101(0xc74af482U, 0x99c93ee9U, 0xb2744daaU, 0x2f1fb4e4U); + } + R_SCE_func100(0x173c9c4dU, 0xd60a7bf1U, 0x60093bfdU, 0x2ec74acfU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x017da167U); + R_SCE_func080(); + R_SCE_func100(0xa85d0bd8U, 0xcc60ad18U, 0x3e085308U, 0xe87efa5aU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func313(1156); + R_SCE_func100(0xe5fce155U, 0x689bcd24U, 0xa47eb743U, 0x7dc3af71U); + R_SCE_func314(1156+64); + SCE->REG_ECH = 0x00000b5aU; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d77cU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x3800db7aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa8f8757cU, 0xc2532beaU, 0xfbba4cc5U, 0x84c7d682U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000157U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000110U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xa7e9686fU, 0xda8e5b68U, 0x81f149bdU, 0x6b78d9e6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00003340U; + R_SCE_func101(0xb7418b1eU, 0xab29cb8bU, 0xee70cb7dU, 0xa4d90812U); + } + else + { + R_SCE_func101(0xa8273f89U, 0x45442134U, 0xd4850bfcU, 0xcccddce6U); + oLoop1 = 0; + } + } + SCE->REG_ECH = 0x0000d37cU; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x00002b9aU; + SCE->REG_ECH = 0x0000375cU; + R_SCE_func101(0xa5d35c20U, 0x5cbdfacdU, 0x1df44fc2U, 0xb0433084U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xba805753U, 0x852ca913U, 0x4fd9cedbU, 0x5f9bf052U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x63c32367U, 0x9986dc87U, 0x19768848U, 0x94f141ceU); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00002f40U; + R_SCE_func101(0xeb85c7e8U, 0x15dbf0eeU, 0xb6f4532bU, 0x068b44aeU); + } + } + R_SCE_func101(0x1993b44bU, 0x690f4b3bU, 0x87d17206U, 0x390becc4U); + } + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000b39U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d77dU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x3800db7bU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x07464bfaU, 0xa41ec7a0U, 0xe48ea12fU, 0x92351e93U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000157U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000110U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x97652807U, 0x3725e7edU, 0xa93ced2bU, 0x511fbee0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00003320U; + R_SCE_func101(0xdebb77c3U, 0x5a323f95U, 0xa39ef0dfU, 0x8f2ce0b8U); + } + else + { + R_SCE_func101(0x0ee7d020U, 0x1e0c8005U, 0x590cbe94U, 0xa5c2a969U); + oLoop1 = 0; + } + } + SCE->REG_ECH = 0x0000d37dU; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x00002b99U; + SCE->REG_ECH = 0x0000373cU; + R_SCE_func101(0x43e466efU, 0xf4483116U, 0x35524ff7U, 0x335fb075U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xb2a344d7U, 0x6766834fU, 0xba498b36U, 0x575d104cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xb5428e25U, 0xf1ee76a5U, 0xb74a8042U, 0x667e80e1U); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00002f20U; + R_SCE_func101(0xfc31d44fU, 0x2cafedcaU, 0xea8a4d0fU, 0xd90074ccU); + } + } + R_SCE_func101(0xfe80d7c9U, 0xf195e713U, 0xea86d754U, 0x3095b9cfU); + } + R_SCE_func100(0xa9a633feU, 0x165fa494U, 0xc9b98bb2U, 0x9f348831U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013fd1d7U); + R_SCE_func080(); + R_SCE_func100(0x84ac0b6fU, 0x105f3192U, 0xb42c04f2U, 0x5e89f356U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(1088); + R_SCE_func100(0xe7b483f6U, 0x7d0d7774U, 0xdf86636dU, 0xaf59265aU); + R_SCE_func314(1088+64); + R_SCE_func100(0x829ce331U, 0xb3fcb53cU, 0x182da1e8U, 0xfbfb9d4cU); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000050U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a2b89bU); + R_SCE_func080(); + R_SCE_func100(0x36a2ffd9U, 0x6876d72fU, 0x7993c31fU, 0x7f0068ebU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(1224); + R_SCE_func100(0x1a40bf95U, 0x1310b477U, 0x63845836U, 0xeabe9fb4U); + R_SCE_func314(1224+64); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00800001U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000080aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x80010380U; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x800103a0U; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x000000adU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000031fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000012U; + SCE->REG_104H = 0x00000767U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x40000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_34H = 0x00000030U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800dbbeU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xcfee5b98U, 0x14e9e7a5U, 0x4735cd59U, 0xd6c8f45aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d375U; + R_SCE_func101(0x62dbb035U, 0xc5080e3cU, 0xf420a58aU, 0x0ff31dbcU); + } + else + { + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d775U; + R_SCE_func101(0x5a8eebccU, 0x2a5f321cU, 0x7aee6d6fU, 0xaaadc8d8U); + } + R_SCE_func100(0xa02f1c27U, 0x9115aaabU, 0xa806611aU, 0xf0e6896aU); + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x8000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013d2cc1U); + R_SCE_func080(); + R_SCE_func100(0x23ec631fU, 0xea71d0c0U, 0xa6206b37U, 0x3312d30cU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func313(1428); + R_SCE_func100(0x03c4bc4eU, 0x5f69a0d7U, 0xa0a5a1acU, 0xa13175c8U); + R_SCE_func314(1428+64); + R_SCE_func100(0x24b3860cU, 0x17cbef28U, 0x1bb0fe5fU, 0xcff028beU); + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000050U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c80cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a2b89bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(1224); + SCE->REG_ECH = 0x0000d776U; + SCE->REG_ECH = 0x3800db75U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xdb721df3U, 0x8814ee7dU, 0x5fe43ab2U, 0x5a1ce76eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xb2c9b808U, 0x5203c390U, 0xda823217U, 0x83024e8eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000d376U; + SCE->REG_28H = 0x00800001U; + SCE->REG_104H = 0x00000257U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_2CH = 0x00000110U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xFFFFFFFFU); + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xd52facf8U, 0x8c1cdffcU, 0x4ad010a5U, 0x9e5888d0U); + } + else + { + SCE->REG_ECH = 0x0000d776U; + SCE->REG_28H = 0x00800001U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000067U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x134325c4U, 0x4ba6582aU, 0xde413a22U, 0x8b0f3924U); + } + } + else + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xac3be9bbU, 0x975f21f0U, 0x7b9c0e6dU, 0xb479aacbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000d376U; + SCE->REG_28H = 0x00800001U; + SCE->REG_104H = 0x00000257U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_2CH = 0x00000110U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xFFFFFFFFU); + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x51c94560U, 0x8e6e6599U, 0xea4892a9U, 0x7662cc6fU); + } + else + { + SCE->REG_ECH = 0x0000d776U; + SCE->REG_28H = 0x00800001U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000067U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x0b77a168U, 0xb53edd31U, 0xb2cf3a59U, 0x67a5fce4U); + } + } + R_SCE_func100(0xc29f1ef9U, 0xa11202baU, 0x4608d26cU, 0x59575c66U); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000189U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02000189U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000189U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02000189U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016be062U); + R_SCE_func080(); + R_SCE_func100(0x7fd8687dU, 0x59f33691U, 0x67e26de8U, 0x8f1a435cU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(1360); + R_SCE_func100(0xb7d8d104U, 0xd03fc109U, 0x6fcd0cbaU, 0x5a202c97U); + R_SCE_func314(1360+64); + R_SCE_func100(0x49d39b7fU, 0x1a11709dU, 0xb916b6f4U, 0xc66464e6U); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x000037dcU; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016be062U); + R_SCE_func080(); + R_SCE_func100(0xdf08d7eeU, 0x96b345e7U, 0xa9d22a61U, 0x8198e092U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(1360); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x017da167U); + R_SCE_func080(); + R_SCE_func100(0x5fbc667aU, 0xf7ca0146U, 0x216ca9efU, 0xdc2b921bU); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(1156); + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x80010380U; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000080aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x81010380U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000080aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000080aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x800103c0U; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00008fc0U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_ECH = 0x0000d777U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x3000dbc3U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x00002bddU; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000d377U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x00002b9eU; + SCE->REG_ECH = 0x000037dcU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013d2cc1U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(1428); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x3800db77U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa02e78abU, 0x8cdbbf6bU, 0xedf2e965U, 0xc1f8374bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func100(0x74a0fb2dU, 0x1f242d1fU, 0xae5d98fcU, 0x91e71762U); + SCE->REG_E0H = 0x810103c0U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00002fe0U; + R_SCE_func101(0xefdd5812U, 0x82089e95U, 0xd17ef168U, 0xaa29a094U); + } + R_SCE_func101(0x96f44f7cU, 0xdb16c62dU, 0xde56b0a0U, 0x4ab8e241U); + } + else + { + R_SCE_func100(0xf93b9b92U, 0x945f6d5dU, 0x3e0c3e56U, 0x06ef9c7dU); + SCE->REG_E0H = 0x810103c0U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00002fe0U; + R_SCE_func101(0x9c44d017U, 0x6e2aaf0cU, 0xdaed6879U, 0xfbd8e08cU); + } + R_SCE_func101(0x64751973U, 0xac4fd03aU, 0xfd004cbcU, 0xda40b9f0U); + } + SCE->REG_ECH = 0x38000bdfU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func100(0xbf319692U, 0xb45847feU, 0x961a5b99U, 0xba92bd78U); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016be062U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(1360); + SCE->REG_ECH = 0x3800db76U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x32c05eb1U, 0x1af4747bU, 0x65a2d1ebU, 0x6e53d91bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000190U); + R_SCE_func101(0xdf9f8695U, 0xc9d30237U, 0x400af7bcU, 0x8af14fd3U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x781149b1U, 0x2713ae81U, 0x08637c82U, 0x21dc84e7U); + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d378U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d778U; + SCE->REG_ECH = 0x00000080U; + R_SCE_func100(0x8a55234aU, 0x1c58b72fU, 0xa6636cf5U, 0xbe997152U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016efbeaU); + R_SCE_func080(); + R_SCE_func100(0x2926188cU, 0x91e465bbU, 0xee232e57U, 0xc45a6f23U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(1292); + R_SCE_func100(0x561468bdU, 0x2b678626U, 0x7896fb83U, 0xc446a4a9U); + R_SCE_func314(1292+64); + R_SCE_func100(0xe8d9928dU, 0x4abaaa93U, 0x148dd000U, 0x67fdeaa0U); + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x81010320U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81010340U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000080aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x80010300U; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000d77eU; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x3000db7cU; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x00002fc0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x3000db7dU; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x00002fc0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x3000dbc0U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d77eU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d37eU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013fd1d7U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(1088); + SCE->REG_ECH = 0x3000db7cU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d76bU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d36bU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x000037daU; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000094U; + R_SCE_func101(0xd829182cU, 0xc047fe4aU, 0xb8f1178eU, 0x311c4301U); + R_SCE_func310(); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3000db7dU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d76bU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d36bU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x000037d9U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000095U; + R_SCE_func101(0xe0b1214eU, 0x643ced42U, 0xd081e694U, 0x4ff3b264U); + R_SCE_func310(); + R_SCE_func100(0x1edc8c2bU, 0xa331f7c6U, 0xfe78ce71U, 0xc98d8c82U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x017da167U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(1156); + SCE->REG_ECH = 0x3000db7eU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d76bU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d36bU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x000037d8U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000096U; + R_SCE_func101(0x274cdf79U, 0x168d2df4U, 0x70dbae58U, 0x1fc0b450U); + R_SCE_func310(); + R_SCE_func100(0x79509467U, 0x157a6536U, 0x0f364fdeU, 0x331f1e3eU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016efbeaU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(1292); + SCE->REG_ECH = 0x3800db78U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x765323ebU, 0x5f07d838U, 0x08a60b85U, 0x97010f18U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00800001U; + SCE->REG_104H = 0x00000257U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_2CH = 0x00000190U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xFFFFFFFFU); + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x383e941aU, 0x8cb6cb0fU, 0xd6cd380eU, 0xa92c012eU); + } + else + { + R_SCE_func101(0xdbcdfe3aU, 0xb3df35d7U, 0xe8ce3c87U, 0x4632da37U); + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x3800db79U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa65d5472U, 0x9892f0e0U, 0xb4f3eb48U, 0x1e379814U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func100(0xec28935eU, 0xa835a732U, 0x0264c69eU, 0x99367e05U); + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d368U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d768U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a2b89bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(1224); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d372U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d772U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x341a1247U, 0x991801fdU, 0x99b06d2aU, 0x48fde684U); + } + else + { + R_SCE_func100(0xfa62f3d1U, 0x45d873f3U, 0xd70b5db4U, 0x62b9d483U); + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d368U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d768U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000d772U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a2b89bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(1224); + R_SCE_func101(0x5f430397U, 0x24c39b0dU, 0x6e36db4eU, 0x8f177f91U); + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000024U; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func304_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func305.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func305.c new file mode 100644 index 0000000000..d5916b1145 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func305.c @@ -0,0 +1,554 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func305(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x80000a41U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x80000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280U; + SCE->REG_24H = 0x800019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x900019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280U; + SCE->REG_24H = 0x800019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800040c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200U; + SCE->REG_24H = 0x800012c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080U; + SCE->REG_24H = 0x800060c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000145U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func305.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func307.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func307.c new file mode 100644 index 0000000000..cb983c2dba --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func307.c @@ -0,0 +1,519 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func307_r1(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000090U; + SCE->REG_ECH = 0x00003c1eU; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000080U; + R_SCE_func101(0x89e510feU, 0x394c1c77U, 0xd552f2e2U, 0x6ac5d5aaU); + R_SCE_func311_r1(); + SCE->REG_ECH = 0x00000a73U; + SCE->REG_ECH = 0x00000a31U; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x00002e20U; + SCE->REG_ECH = 0x38002673U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x61daf1ddU, 0x3ee980fbU, 0xcdef1fceU, 0x18899658U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x0086bf00U, 0xf2bc533fU, 0x8f0aba9aU, 0x051899ccU); + } + else + { + R_SCE_func100(0x2bfa9d5fU, 0x2dc12fecU, 0x52a3134cU, 0x319750beU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beU); + R_SCE_func080(); + R_SCE_func100(0x3a2013c3U, 0xd669fc60U, 0xeb24818dU, 0xaea9b0c6U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(204); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1U); + R_SCE_func080(); + R_SCE_func100(0x1181c28cU, 0xfbff07a7U, 0xa43865ddU, 0xce1e7827U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(136); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45U); + R_SCE_func080(); + R_SCE_func100(0x2ca72a98U, 0xa3faf9e9U, 0x4c2440b8U, 0x7805dbe7U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(476); + R_SCE_func100(0x2e5a1e50U, 0x2bfda642U, 0x5911957cU, 0xe6bbfd15U); + R_SCE_func314(476+64); + R_SCE_func100(0x38550e61U, 0xca22047aU, 0x734955faU, 0x881bdd0cU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91U); + R_SCE_func080(); + R_SCE_func100(0x4a6f1244U, 0x6f2b65a2U, 0x14ad6998U, 0x94d29709U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(612); + R_SCE_func100(0xb02e1c9dU, 0x81d2d607U, 0x19430f7eU, 0x51961d36U); + R_SCE_func314(612+64); + R_SCE_func100(0x40e9e6b1U, 0x64a3945eU, 0xa63fc42bU, 0xc2a79424U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdU); + R_SCE_func080(); + R_SCE_func100(0x62fb4204U, 0x8290c756U, 0xc455a66bU, 0x7caef83eU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(408); + R_SCE_func100(0xc82c09c6U, 0x0241efeaU, 0x420d1d29U, 0xaeb0e145U); + R_SCE_func314(408+64); + R_SCE_func100(0xec5c5ffbU, 0x5abee79eU, 0x1a441a53U, 0x60c468e9U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3dU); + R_SCE_func080(); + R_SCE_func100(0x13968a26U, 0x8c211329U, 0xb83768a4U, 0xd8693026U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(544); + R_SCE_func100(0x10a68846U, 0x08636b6fU, 0x5ae4fa29U, 0x822e4f1fU); + R_SCE_func314(544+64); + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000081U; + R_SCE_func101(0x59e2797cU, 0x9b3a97d6U, 0x0d8cad4cU, 0xccf47f58U); + R_SCE_func309_r1(); + R_SCE_func100(0x4d425083U, 0xab1bd6e2U, 0x32f75dc3U, 0x0a0d3f01U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beU); + R_SCE_func080(); + R_SCE_func100(0xc2fcfbe0U, 0x2af3b8a4U, 0x7c6bc05dU, 0xf82d796aU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(204); + R_SCE_func100(0x57639e92U, 0x0bbfedcaU, 0x2ce6433cU, 0x99e24a79U); + R_SCE_func314(204+64); + R_SCE_func100(0xa7b2a175U, 0xe220547eU, 0xa0200b97U, 0x842e0187U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1U); + R_SCE_func080(); + R_SCE_func100(0xaf2aef4eU, 0xa21fd2e4U, 0x85719cb1U, 0xfef6ad92U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(136); + R_SCE_func100(0x930d52b5U, 0xdcf0bf05U, 0x4217e47dU, 0x865a86cdU); + R_SCE_func314(136+64); + R_SCE_func101(0x6afebc6fU, 0x01926f79U, 0xc2bb4135U, 0xe1777db3U); + } + SCE->REG_ECH = 0x3800da9fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xd131ee14U, 0x0560e33cU, 0xdf44e4ccU, 0x2af89076U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0xcbf6dbc7U, 0x0fa7a039U, 0xc8445df8U, 0x636729feU); + } + else + { + R_SCE_func100(0x09140813U, 0xc3224ddfU, 0xe4c93453U, 0x7945f068U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beU); + R_SCE_func080(); + R_SCE_func100(0x2424db58U, 0x7ffb18a8U, 0x9f76e498U, 0xd416be93U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(204); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(136); + R_SCE_func100(0xf4795071U, 0xeab4e990U, 0xa5b67fdaU, 0xd4b2759fU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45U); + R_SCE_func080(); + R_SCE_func100(0x884a8911U, 0x3acaf644U, 0xfda7ca34U, 0x1d7d19cfU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(476); + R_SCE_func100(0x56381697U, 0xc6ee8f18U, 0xed459860U, 0xfec25ca4U); + R_SCE_func314(476+64); + R_SCE_func100(0x5fd6098eU, 0xb0a4aa6fU, 0x6fbf8a9bU, 0x8d3d485cU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdU); + R_SCE_func080(); + R_SCE_func100(0x95d32d78U, 0xa45457b5U, 0xe5f8e953U, 0x38f617afU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(408); + R_SCE_func100(0x734032afU, 0xdb8e964cU, 0x99579a76U, 0x77372250U); + R_SCE_func314(408+64); + R_SCE_func100(0x05d01d46U, 0x51c80911U, 0x1f9533bbU, 0x559a990cU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bU); + R_SCE_func080(); + R_SCE_func100(0x26ec1a66U, 0xa360484aU, 0x1fc4554aU, 0xec5faf33U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(68); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7aU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(0); + R_SCE_func100(0x5f778260U, 0xe3de8be1U, 0x812451fcU, 0x1fe75f22U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91U); + R_SCE_func080(); + R_SCE_func100(0xd8080861U, 0xcf4e71c6U, 0x6139f572U, 0xca85541aU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(612); + R_SCE_func100(0x7bace3d0U, 0xf031163fU, 0x89edc410U, 0x753d81f2U); + R_SCE_func314(612+64); + R_SCE_func100(0x9aaa72f5U, 0x2cc19247U, 0x5ed1ebc1U, 0x31ad1ebcU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3dU); + R_SCE_func080(); + R_SCE_func100(0xac0242f2U, 0x02712c2fU, 0x67bf3657U, 0xefa0c8a9U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(544); + R_SCE_func100(0x03654065U, 0xe7dc14aaU, 0x18333d86U, 0x09ef6142U); + R_SCE_func314(544+64); + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000082U; + R_SCE_func101(0xb813cd50U, 0xaa5a905cU, 0x8b4a9838U, 0x864d3a8fU); + R_SCE_func309_r1(); + R_SCE_func100(0xe86ac439U, 0x52299c20U, 0x34cb67a5U, 0x9406a945U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beU); + R_SCE_func080(); + R_SCE_func100(0xb8f0ebd6U, 0x59ca3d05U, 0x4cd45e93U, 0x3f4e0c81U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(204); + R_SCE_func100(0x47accc40U, 0xfef83151U, 0x8db0ab0bU, 0xb47061efU); + R_SCE_func314(204+64); + R_SCE_func100(0xfe6a2d71U, 0x87544900U, 0xefa8d3cfU, 0x24dc7d30U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1U); + R_SCE_func080(); + R_SCE_func100(0x2743f352U, 0x033635bdU, 0x7422794bU, 0x940927bfU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(136); + R_SCE_func100(0xc775d898U, 0xabfd9871U, 0x28a2e994U, 0xdf9e4dfcU); + R_SCE_func314(136+64); + SCE->REG_ECH = 0x0000d260U; + R_SCE_func101(0x81c8537aU, 0x705d86b7U, 0x819bd7adU, 0xb6ba1cdfU); + } + SCE->REG_ECH = 0x01816e94U; + R_SCE_func101(0x5ed5f9eaU, 0x14860d1aU, 0x8571a921U, 0xac206235U); + } + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func100(0xd16111aaU, 0xdac93babU, 0x81f19e66U, 0xfdd4e647U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beU); + R_SCE_func080(); + R_SCE_func100(0x2e29d960U, 0x6a155b86U, 0x3c9eb07eU, 0xcc418cacU); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(204); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1U); + R_SCE_func080(); + R_SCE_func100(0x9436ca24U, 0x9893f89dU, 0xede2c2f5U, 0xeda17933U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(136); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45U); + R_SCE_func080(); + R_SCE_func100(0x67ddbb73U, 0xae88e0b5U, 0xfdc29736U, 0x5907a3bfU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(476); + R_SCE_func100(0x9c7f220aU, 0x91fa1ae6U, 0xbbdaa77dU, 0x94004114U); + R_SCE_func314(476+64); + R_SCE_func100(0x1553daabU, 0x2f499705U, 0xeeb4dbfcU, 0x17caeee7U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdU); + R_SCE_func080(); + R_SCE_func100(0x6bbeceb9U, 0x6dc208d7U, 0x20b99a2aU, 0x9a590740U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(408); + R_SCE_func100(0xfd77d1a1U, 0x5d4f6bb3U, 0xb25cbde6U, 0x370c6a7fU); + R_SCE_func314(408+64); + R_SCE_func100(0xa70adc0cU, 0x282235caU, 0x5246eefdU, 0x3a8acb3fU); + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91U); + R_SCE_func080(); + R_SCE_func100(0xedd5d76dU, 0x30e4c572U, 0xae423d4aU, 0xb1505115U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(612); + R_SCE_func100(0x7d722467U, 0xdcfa17a6U, 0xc268e6f1U, 0xf56a728eU); + R_SCE_func314(612+64); + R_SCE_func100(0x845df7abU, 0x175293b7U, 0x16d25074U, 0x386c2376U); + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3dU); + R_SCE_func080(); + R_SCE_func100(0x4962e3c6U, 0x39ba3becU, 0xa2e3f229U, 0xd5fb2bfdU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(544); + R_SCE_func100(0x660ac077U, 0x4c484ec5U, 0xa5ef837dU, 0xfd258a4bU); + R_SCE_func314(544+64); + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000083U; + R_SCE_func101(0x0a8b5e81U, 0x3381ec5fU, 0x8db9ae0bU, 0x3ee54ba8U); + R_SCE_func309_r1(); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000090U; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func307_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func308.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func308.c new file mode 100644 index 0000000000..34fb5fce45 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func308.c @@ -0,0 +1,425 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func308(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xb057384eU, 0x03004eb8U, 0x03f35059U, 0xb36635fcU); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000024U; + SCE->REG_ECH = 0x00003c1eU; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000b5aU; + SCE->REG_ECH = 0x0000d77cU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x3800db7aU; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d37cU; + SCE->REG_ECH = 0x00003bbeU; + SCE->REG_ECH = 0x00002b5dU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x00003b5eU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0161d833U); + R_SCE_func080(); + R_SCE_func100(0xa18ca9eeU, 0xb5e621a1U, 0x3eb74dfeU, 0xc710978eU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(1020); + R_SCE_func100(0x1dd54be3U, 0xe6f59cf4U, 0x04914cdbU, 0x22b50074U); + R_SCE_func314(1020+64); + R_SCE_func100(0x5fb01cc1U, 0x2256e3f5U, 0x17791ea3U, 0x0d2da591U); + SCE->REG_ECH = 0x00000b39U; + SCE->REG_ECH = 0x0000d77dU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x3800db7bU; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d37dU; + SCE->REG_ECH = 0x00003bbeU; + SCE->REG_ECH = 0x00002b3dU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x00003b3eU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013fd1d7U); + R_SCE_func080(); + R_SCE_func100(0xe5b3569eU, 0xae1103ebU, 0xed441d47U, 0xc892c069U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(1088); + R_SCE_func100(0x374c7bfbU, 0x694d725fU, 0xeecbbb46U, 0xa6649637U); + R_SCE_func314(1088+64); + R_SCE_func100(0xe876f669U, 0x33c26364U, 0x775159efU, 0x6a2365eeU); + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000080aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x81010320U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81010340U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000080aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x80010300U; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000d77eU; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x3000db7cU; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x00002fc0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x3000db7dU; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x00002fc0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x3000dbc0U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d77eU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d37eU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000058d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013fd1d7U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(1088); + SCE->REG_ECH = 0x3000db7cU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d76bU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d36bU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x000037daU; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000097U; + R_SCE_func101(0x24476abdU, 0xed2cc61fU, 0xc70dbde0U, 0x52944ee5U); + R_SCE_func310(); + R_SCE_func100(0x4a3c9820U, 0x80165372U, 0xabc7c2f8U, 0xec6de5f4U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0161d833U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(1020); + SCE->REG_ECH = 0x3000db7dU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d76bU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d36bU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x000037d9U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000098U; + R_SCE_func101(0xddec318fU, 0x3f251416U, 0x36ab4a6cU, 0x281950aaU); + R_SCE_func310(); + SCE->REG_ECH = 0x3800db7eU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xaab3ec60U, 0xd1b13aeeU, 0x77a5d71cU, 0x795a21e6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x81010300U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x80001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x92cee587U, 0x111485cfU, 0x8ef45a4cU, 0x8cb01b1dU); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x81010300U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x80001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xf4fd8549U, 0xd195a747U, 0xe15df35dU, 0x8702e714U); + } + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d372U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d772U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000d768U; + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000024U; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func308.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func309.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func309.c new file mode 100644 index 0000000000..f6c07436cb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func309.c @@ -0,0 +1,3064 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func309_r1(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xc9497620U, 0x866c5700U, 0xfeb665d0U, 0x22c9a6bbU); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000028U; + SCE->REG_ECH = 0x00003c1eU; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000b7bU; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45U); + R_SCE_func080(); + R_SCE_func100(0x056065a2U, 0x12ea8a76U, 0x1368ce4aU, 0x2a3de50eU); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(476); + SCE->REG_ECH = 0x0000d77aU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(612); + SCE->REG_ECH = 0x0000d77bU; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000090U; + R_SCE_func101(0x4ac0cb7eU, 0x5aaad032U, 0x5bd81569U, 0xa9240905U); + R_SCE_func308(); + R_SCE_func100(0x65a81509U, 0x2f80ad84U, 0xa9ce0862U, 0xa8b16e2cU); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_ECH = 0x00003bbeU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x00003fbeU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f0b809U); + R_SCE_func080(); + R_SCE_func100(0xc3978dfaU, 0xd86edae6U, 0x7801300eU, 0x85190f12U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(884); + R_SCE_func100(0xeb9204ccU, 0xe1ff0601U, 0x8d356106U, 0x2ddac834U); + R_SCE_func314(884+64); + R_SCE_func100(0x90ae1312U, 0xd76c960aU, 0x66422980U, 0x25eb51fcU); + SCE->REG_ECH = 0x3000db72U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d770U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d366U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d766U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + R_SCE_func100(0x8998d772U, 0xeeba55e7U, 0xf1b97798U, 0xf3db04d2U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func313(816); + R_SCE_func100(0xe03a23fbU, 0x0502d76fU, 0xa5e303abU, 0x8ab8c5eaU); + R_SCE_func314(816+64); + R_SCE_func100(0xa1171a4fU, 0x6503528fU, 0x1bec2a37U, 0xf3188f78U); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x000000a0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d371U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d771U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfU); + R_SCE_func080(); + R_SCE_func100(0x312d693eU, 0x885b4cbdU, 0xdf5f1540U, 0xf3862899U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(952); + R_SCE_func100(0x653e2156U, 0xa4a401d3U, 0x25fce12cU, 0xeb50b072U); + R_SCE_func314(952+64); + R_SCE_func100(0xc4f3d006U, 0x40d182c0U, 0x006bd509U, 0xa755cb36U); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3dU); + R_SCE_func080(); + R_SCE_func100(0x15efd281U, 0xfb20a67fU, 0x0f5b7093U, 0x61aa8c45U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(544); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91U); + R_SCE_func080(); + R_SCE_func100(0x3e72a381U, 0x9588b4feU, 0x9e492c5fU, 0xa38f8108U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(612); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000d77bU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdU); + R_SCE_func080(); + R_SCE_func100(0x8d2e52e0U, 0x1300f0a1U, 0xda2e4d6eU, 0x0d1b5c12U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(408); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(476); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000000cU; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000d77aU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000091U; + R_SCE_func101(0x9772fa14U, 0xe01b0b89U, 0x94b1a65dU, 0x7d0de12aU); + R_SCE_func308(); + R_SCE_func100(0x2ba1c177U, 0xbbd9c4f5U, 0x8e516c93U, 0x06216eccU); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(816); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x3800db66U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x56980b36U, 0x6aec4eb5U, 0x721341eaU, 0xf44ae362U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000110U); + R_SCE_func101(0x846ef339U, 0x3d5ab58bU, 0xdd143b7aU, 0x534890b9U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x17b1fe6dU, 0xef4daec6U, 0xca3f81caU, 0x14101586U); + } + R_SCE_func100(0x917cfba7U, 0xe14936dfU, 0x9a334628U, 0x450a93b7U); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000d766U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + R_SCE_func100(0xee68ca77U, 0xdd0fc4f1U, 0xb512c047U, 0x7da75dfeU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(816); + R_SCE_func100(0x2c598c56U, 0x22b2e36cU, 0x153ed168U, 0x7bae1f6dU); + R_SCE_func314(816+64); + R_SCE_func100(0xeb0c65d8U, 0xee968b4cU, 0xf4864fcaU, 0x227e7684U); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(952); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_ECH = 0x3800db71U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xbbefa963U, 0x4616e5dcU, 0x6f84cd1eU, 0x9c882529U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000110U); + R_SCE_func101(0xafcac712U, 0x13cf3623U, 0x7f68142aU, 0x782923cfU); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x08d18960U, 0xe3f8f928U, 0xecf93710U, 0x3f8a09eeU); + } + R_SCE_func100(0xbf6e7fa5U, 0xa933fa11U, 0x76309954U, 0xa1a7b56eU); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d371U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d771U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfU); + R_SCE_func080(); + R_SCE_func100(0xd34d10fdU, 0xf14c7ec4U, 0x2878fd42U, 0x3d896fe4U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(952); + R_SCE_func100(0xb4d3a326U, 0x84c7f992U, 0x2ab3997dU, 0x1a345d87U); + R_SCE_func314(952+64); + R_SCE_func100(0x6990032dU, 0x2c1bef62U, 0x1d9cf13eU, 0x245b1835U); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdU); + R_SCE_func080(); + R_SCE_func100(0xa80ff0adU, 0x2417fcd2U, 0x2bd6d6adU, 0xa670e68aU); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(408); + SCE->REG_ECH = 0x0000d77aU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3dU); + R_SCE_func080(); + R_SCE_func100(0x60e11786U, 0xaa724960U, 0x9491d91fU, 0xb1985116U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(544); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000d77bU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(680); + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000092U; + R_SCE_func101(0x6b69288eU, 0xd1ecfcbaU, 0x82e19566U, 0x6b62af3aU); + R_SCE_func304_r1(); + R_SCE_func100(0x368d2f14U, 0x93f1d277U, 0x8ccd8026U, 0x3381bbe1U); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(816); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_ECH = 0x3800db72U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xdaff94beU, 0x192a36deU, 0x8d68cf48U, 0x67aa70e2U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000190U); + R_SCE_func101(0x0848476eU, 0xc735ae41U, 0x0f65a3a1U, 0x18236a1dU); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x129e0c32U, 0x33d5181bU, 0xbd152f92U, 0x83634ab8U); + } + R_SCE_func100(0xaf945a08U, 0x76e6d0a6U, 0x0b951159U, 0xf4386352U); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d366U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d766U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + R_SCE_func100(0xba2ae63aU, 0xa6539f83U, 0xd13eeb08U, 0x3e02c748U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(816); + R_SCE_func100(0x05c8ab2cU, 0xcfbfe041U, 0x93ef8646U, 0x773d783eU); + R_SCE_func314(816+64); + R_SCE_func100(0xb223ce42U, 0xcff4a48fU, 0xeb4798baU, 0x805894ceU); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(952); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_ECH = 0x3800db71U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x723e4f09U, 0x6fe3bf6bU, 0xbbd40e45U, 0xd08992d8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000110U); + R_SCE_func101(0xc7c45474U, 0x19983a69U, 0xbc067586U, 0x5305214fU); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x324eb05dU, 0x917ab405U, 0xa787dd7dU, 0x49538a46U); + } + R_SCE_func100(0xd98570c9U, 0xa8db5ad0U, 0xd5bd3aa6U, 0x732a9600U); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d371U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d771U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfU); + R_SCE_func080(); + R_SCE_func100(0xf4f0c4e2U, 0x43c34df9U, 0x28054165U, 0x0c25de26U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(952); + R_SCE_func100(0xc7ba66bcU, 0x97b26d5cU, 0x2d755917U, 0xf73639ecU); + R_SCE_func314(952+64); + R_SCE_func100(0x85d722b0U, 0xa94023feU, 0x3b8520b9U, 0xdeac91eeU); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_ECH = 0x00003b9eU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3000db68U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d77aU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d37aU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(748); + SCE->REG_ECH = 0x0000d77bU; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000093U; + R_SCE_func101(0x93c64f76U, 0xe68789b5U, 0xab51aa7aU, 0xb21bbb14U); + R_SCE_func308(); + R_SCE_func100(0x57bd6f00U, 0x0c886102U, 0xdfefc085U, 0xa5ca49a2U); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f0b809U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(884); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_ECH = 0x3800db72U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x9305ae89U, 0xe37db1d8U, 0x251ed0dfU, 0x77ff28d7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000190U); + R_SCE_func101(0xa20706e1U, 0xfa887457U, 0x77852390U, 0xa67a3c3eU); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xc786ca2fU, 0xaa1706d3U, 0x27f0b69bU, 0x96b1c95cU); + } + R_SCE_func100(0x4595af69U, 0x8e586200U, 0xf24564d6U, 0x4f1039f1U); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d370U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d770U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f0b809U); + R_SCE_func080(); + R_SCE_func100(0xfd730458U, 0xc8fe8c44U, 0x844467b4U, 0x150b4fceU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(884); + R_SCE_func100(0xe0255f01U, 0xf11d3b68U, 0x50a7fef5U, 0xbc4c6830U); + R_SCE_func314(884+64); + R_SCE_func100(0x1120981aU, 0x498f9ad7U, 0x4f5df720U, 0x9ef9c90cU); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(816); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x3800db66U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xaf1b3f51U, 0xc407883fU, 0x5d58d23fU, 0x2530c593U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000110U); + R_SCE_func101(0xb428bd01U, 0x64d98544U, 0x6a7f0124U, 0x2859e5c4U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xc1e2626bU, 0xb973e6f7U, 0xd82fe9b1U, 0xd14b7268U); + } + R_SCE_func100(0xee4fa77fU, 0xbb5880cfU, 0x40c5cc5aU, 0x908892d7U); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d366U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d766U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + R_SCE_func100(0x5cd4ea6aU, 0x3176e314U, 0x859d405fU, 0x2d0a1068U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(816); + R_SCE_func100(0x99468bc5U, 0x961dccd5U, 0xa6dd6826U, 0xcbeae596U); + R_SCE_func314(816+64); + R_SCE_func100(0xe76d23deU, 0x7934ce14U, 0x247368e4U, 0x0a0045efU); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(952); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_ECH = 0x3800db71U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x944114f4U, 0xda6fcbc3U, 0xc5e68002U, 0xe3dbdef8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000110U); + R_SCE_func101(0x04b0a7b2U, 0xd52949b2U, 0x247774efU, 0x5cd2539aU); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xb042a7b6U, 0xa96d1895U, 0xd18dd35fU, 0xbf086bffU); + } + R_SCE_func100(0x755e79feU, 0x7cfa4788U, 0xa1fb3f6aU, 0xe4ee11b9U); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d371U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d771U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000014U; + SCE->REG_ECH = 0x00003b9eU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_ECH = 0x3000db71U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d77aU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d37aU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000d77bU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(680); + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000094U; + R_SCE_func101(0x76e2fda6U, 0x0de14033U, 0xe3bbccb0U, 0x6cdee050U); + R_SCE_func304_r1(); + R_SCE_func100(0xe49c519cU, 0x97153a06U, 0xcb96ad65U, 0x2fd3f2a8U); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(816); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x3800db66U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x9849bd95U, 0x48605585U, 0xc68e82e2U, 0x330655fdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000110U); + R_SCE_func101(0x2489efffU, 0x1b079a46U, 0xe92655c0U, 0xf593ef9fU); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xa1bf1379U, 0xeb0a8be9U, 0x21f7462dU, 0x374525bcU); + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_ECH = 0x3800db72U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x7dffb181U, 0x763fc10eU, 0xe633a50aU, 0x95617badU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000190U); + R_SCE_func101(0xb58dc8f7U, 0x9bc95df4U, 0xf02bf893U, 0xd97d9ff9U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x827589d1U, 0x85dbfdfdU, 0x3a05e242U, 0xa86ae06dU); + } + R_SCE_func100(0x6a56d422U, 0xe3225b60U, 0x5ea7e3f1U, 0x36f4ee8bU); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d366U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d766U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + R_SCE_func100(0x57395970U, 0xc884887fU, 0xa3fda2e3U, 0x5e5404e3U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(816); + R_SCE_func100(0x20b18da3U, 0xec8ce86eU, 0xee70ef5bU, 0x349f8bcdU); + R_SCE_func314(816+64); + R_SCE_func100(0xb4a186f3U, 0x41ec7aa9U, 0xee9975b9U, 0xc3a09f57U); + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_ECH = 0x00003b9eU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3000db68U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d77aU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d37aU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(748); + SCE->REG_ECH = 0x0000d77bU; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000095U; + R_SCE_func101(0x18dc12dcU, 0xfedf4fadU, 0x38eaa911U, 0xbd76a830U); + R_SCE_func308(); + R_SCE_func100(0x35a1d788U, 0xb3dae31bU, 0x5b837588U, 0x3b6109deU); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000c8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(816); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x3800db66U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa952f5b3U, 0x10a39d4fU, 0x44932a05U, 0xc6b012b5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000110U); + R_SCE_func101(0xb329a1d4U, 0xcae5801dU, 0x5a9b2cf9U, 0x775981dcU); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x19c1eae7U, 0xf124c7dfU, 0x21674703U, 0xb2fcdc21U); + } + R_SCE_func100(0x68dd0067U, 0x1397966aU, 0x18ccd0b1U, 0x9d2988dbU); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d366U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d766U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f0b809U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(884); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x3800db70U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa6a51a04U, 0xabed4cb9U, 0xe6280cc9U, 0xf61c86ebU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000110U); + R_SCE_func101(0x58ccd2fcU, 0xe601b4d5U, 0x8ecb4b3cU, 0x63947123U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x3bdfd0abU, 0x993a3658U, 0x19fd9437U, 0xdaecb896U); + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000018U; + SCE->REG_ECH = 0x3800db72U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xf8718155U, 0x69adcb54U, 0x390bb37bU, 0x1088effdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func315(0x00000190U); + R_SCE_func101(0xe5bb3db2U, 0x3d85e004U, 0x02cebd78U, 0x132d6343U); + } + else + { + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xd1c12944U, 0x4004e6e0U, 0x307b0af9U, 0xa7b4d853U); + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x3800db66U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xb2e76836U, 0xda1ba345U, 0x556ef2c8U, 0x5f571763U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x04000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x00003b9eU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000004cU; + SCE->REG_ECH = 0x00003f9eU; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x00800001U; + SCE->REG_104H = 0x00000257U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_2CH = 0x00000190U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xFFFFFFFFU); + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x2f82caadU, 0x7a1f23b5U, 0x6bda5545U, 0xaa3483e9U); + } + else + { + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0x121eb339U, 0x6a675b8dU, 0x0377749aU, 0x98d7ab8aU); + } + R_SCE_func100(0x7bc076d8U, 0x3190ba23U, 0x0ea9c00dU, 0x04a12dd9U); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x02816fdeU; + SCE->REG_ECH = 0x30008bc0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00020020U; + SCE->REG_ECH = 0x0000d37eU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000d77eU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9U); + R_SCE_func080(); + R_SCE_func100(0xfd22029aU, 0x9186349aU, 0x1dc3a93aU, 0x13fe01baU); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(680); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(748); + SCE->REG_ECH = 0x3800db7eU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x14897332U, 0xefb8f2bdU, 0xde971716U, 0x795bdc4eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + oLoop1 = 1; + while(oLoop1 == 1) + { + R_SCE_func100(0x9e0141c8U, 0xa5964252U, 0xd5fc56cdU, 0x45a5bc93U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x06001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000050U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x000000a0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_104H = 0x00000157U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000110U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000050U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xee699b8aU, 0x2584d6b5U, 0x82dad7a8U, 0x1b259d57U); + } + else + { + R_SCE_func101(0x2e3dfe53U, 0x1edd9cecU, 0x16936127U, 0xf9439d41U); + oLoop1 = 0; + } + } + R_SCE_func101(0x1932fa92U, 0xd379a7d0U, 0xb4088718U, 0x8edb462aU); + } + else + { + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x06001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000050U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x000000a0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000050U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd334a49cU, 0x58a841f6U, 0xc819bbfeU, 0x6bd1b9f7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x43b973a6U, 0x021cb33aU, 0x041fe7baU, 0x7a896230U); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x06001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x80c0001eU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000050U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x8088001eU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x000000a0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x00800001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_104H = 0x00000157U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000110U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x8081001eU; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000050U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000090U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_E0H = 0x81c0001eU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x403817d6U, 0x80059b03U, 0xbed534dcU, 0x1b72170aU); + } + } + R_SCE_func101(0xb9cdfcb5U, 0x50c5e00cU, 0xe277d5e3U, 0x6ccef386U); + } + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000028U; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func309_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func310.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func310.c new file mode 100644 index 0000000000..db6e872faf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func310.c @@ -0,0 +1,195 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func310(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x3800db6bU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xc094f164U, 0x1d827e7bU, 0x202314eeU, 0xc142d25bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func100(0x22ee3311U, 0xda03ed5bU, 0xa322186fU, 0x908d04e0U); + SCE->REG_E0H = 0x810103c0U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00002fe0U; + R_SCE_func101(0x799e51d4U, 0xc02cb3e6U, 0x02e64b98U, 0xd73a35c6U); + } + R_SCE_func101(0xebd240c2U, 0x5e43bbe1U, 0x87d780ccU, 0xe8fc58c0U); + } + else + { + R_SCE_func100(0x83d590e0U, 0x33b47405U, 0x06286c82U, 0xd57f1264U); + SCE->REG_E0H = 0x810103c0U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x82001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00002fe0U; + R_SCE_func101(0xf45886ccU, 0x2464d117U, 0x5c8ba823U, 0x97ea0b11U); + } + R_SCE_func101(0xbec7fd0dU, 0xb754fb17U, 0x6ba41fb4U, 0x54e8d888U); + } + SCE->REG_ECH = 0x38000bdfU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func310.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func311.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func311.c new file mode 100644 index 0000000000..c314b240c2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func311.c @@ -0,0 +1,658 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func311_r1(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x73528994U, 0x73843df3U, 0x788210e1U, 0xf7479a52U); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000002cU; + SCE->REG_ECH = 0x00003c1eU; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x04000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9U); + R_SCE_func080(); + R_SCE_func100(0xda994b8aU, 0xd2235665U, 0x9b2cea4aU, 0xee2a57d1U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(680); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(748); + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + oLoop1 = 1; + while(oLoop1 == 1) + { + R_SCE_func100(0x6fdf6c08U, 0xa2722980U, 0x48fcacb7U, 0xad2aa6b2U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x534e0a0dU, 0x2a6da938U, 0xe0f8ce9dU, 0xfc414a50U); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func101(0x32d40389U, 0xc8fe545bU, 0x7940e3a4U, 0x95763cb4U); + } + } + R_SCE_func100(0x93fe9a76U, 0x91cfe05bU, 0x9527b0f2U, 0xa1687aeaU); + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1U); + R_SCE_func080(); + R_SCE_func100(0x99858efaU, 0x1f95d811U, 0x2a0efd63U, 0x0a7155a0U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(136); + R_SCE_func100(0x40722065U, 0xdc14ea5cU, 0x56b8396bU, 0x701248dcU); + R_SCE_func314(136+64); + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xce0c5cabU, 0x08fc0f2dU, 0x7ab5caf9U, 0x7099eb64U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beU); + R_SCE_func080(); + R_SCE_func100(0xc75c36c6U, 0x08bf7526U, 0xa0805931U, 0xf35c625fU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(204); + R_SCE_func100(0x9b330478U, 0xbbe194d3U, 0x67fd1f35U, 0x6650c462U); + R_SCE_func314(204+64); + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000a52U; + for (iLoop = 0; iLoop < 256; iLoop = iLoop + 1) + { + R_SCE_func100(0xe1f04f65U, 0x8a0278bbU, 0xafa9eaceU, 0x0a473291U); + SCE->REG_24H = 0x040049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0400d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9U); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(680); + SCE->REG_ECH = 0x00002e40U; + R_SCE_func101(0x4eca043bU, 0x7bf6a009U, 0xff72fe5aU, 0x6c33e6a9U); + } + R_SCE_func100(0x9c0c4a3bU, 0x0b81844aU, 0xcc522fe2U, 0x40b55a7eU); + SCE->REG_ECH = 0x38008a40U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_24H = 0x040049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x040019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0400d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x020019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9U); + R_SCE_func080(); + R_SCE_func100(0xc8fa73dcU, 0x13a1c885U, 0x3665eef1U, 0x757770acU); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(680); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdU); + R_SCE_func080(); + R_SCE_func100(0x0b7254e4U, 0xf5746033U, 0xeedc483cU, 0xefc2e8e6U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(408); + R_SCE_func100(0x1a10c0a9U, 0x791abd27U, 0xa886a58fU, 0x45e8296bU); + R_SCE_func314(408+64); + R_SCE_func100(0xea326835U, 0x66be423cU, 0x53c01fefU, 0x1d06c555U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3dU); + R_SCE_func080(); + R_SCE_func100(0xb4422e59U, 0xe0ca3e46U, 0xbd31e2c1U, 0xb725d8aaU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(544); + R_SCE_func100(0x656e0585U, 0x0558d20bU, 0x10a6cd2cU, 0xf7d20198U); + R_SCE_func314(544+64); + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x90252b1fU, 0x57108521U, 0xbf1c6553U, 0x6921810bU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45U); + R_SCE_func080(); + R_SCE_func100(0x68e52833U, 0x99d2e2c2U, 0xd30409ddU, 0x48ea4ffcU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(476); + R_SCE_func100(0x999f97cfU, 0xdcc7d5d8U, 0x74b11220U, 0x89c15bd6U); + R_SCE_func314(476+64); + R_SCE_func100(0x1ea20d50U, 0x0baeaea8U, 0x1ffc161aU, 0x60906c7eU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91U); + R_SCE_func080(); + R_SCE_func100(0x5a3541d0U, 0xe4c243d7U, 0x72fa1d1dU, 0x8a8193b1U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(612); + R_SCE_func100(0x4493349bU, 0xdffc6cefU, 0x5531c167U, 0xe783fc74U); + R_SCE_func314(612+64); + SCE->REG_ECH = 0x00000a52U; + for (iLoop = 0; iLoop < 4; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000085U; + R_SCE_func101(0xd2fab61cU, 0x19e55020U, 0xbfd2c9cfU, 0xa138f98aU); + R_SCE_func309_r1(); + R_SCE_func100(0xfe6cc685U, 0xf2374263U, 0x7d4e35eaU, 0x54b68c15U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45U); + R_SCE_func080(); + R_SCE_func100(0x861265b4U, 0x796577c1U, 0x0d8bfd62U, 0x8e34e848U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(476); + R_SCE_func100(0x3e0a0580U, 0x5e233edaU, 0xc28a5e6aU, 0x47e8ac83U); + R_SCE_func314(476+64); + R_SCE_func100(0x3bd8e4c2U, 0x71b182fdU, 0x61503290U, 0x8a694105U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91U); + R_SCE_func080(); + R_SCE_func100(0x11295d01U, 0xacd34627U, 0x6dfbfc6cU, 0x7b0910b6U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(612); + R_SCE_func100(0xf536312eU, 0xef63f865U, 0xa6f9e409U, 0x125db8e1U); + R_SCE_func314(612+64); + R_SCE_func100(0xdadaf6e7U, 0x4cd299f0U, 0xf0bd3e4fU, 0xd47134b3U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdU); + R_SCE_func080(); + R_SCE_func100(0xd1d2fc3bU, 0x821e77f4U, 0x1223e73bU, 0x9a3e45d7U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(408); + R_SCE_func100(0xbbffc3baU, 0x4fcd1362U, 0xcb888c5cU, 0x64df995bU); + R_SCE_func314(408+64); + R_SCE_func100(0xdefbf735U, 0x0c1ef570U, 0x9c62c5a5U, 0x0ee26750U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3dU); + R_SCE_func080(); + R_SCE_func100(0x39012b26U, 0xc601dd1fU, 0x959065f3U, 0x63387816U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(544); + R_SCE_func100(0xabcebe49U, 0x179c5fafU, 0xe662a18eU, 0xed98e35dU); + R_SCE_func314(544+64); + SCE->REG_ECH = 0x00002e40U; + R_SCE_func101(0x0c93bb26U, 0xbf5f443dU, 0xbe68a205U, 0x75195beaU); + } + SCE->REG_ECH = 0x38008a40U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func100(0x0d28278aU, 0x6a7e5e5cU, 0x72ed7be3U, 0x679800c1U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45U); + R_SCE_func080(); + R_SCE_func100(0x5732c361U, 0xc468617aU, 0xa21f5955U, 0xf91d83beU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(476); + R_SCE_func100(0x75f12e8bU, 0x5d7db927U, 0x622d4a34U, 0x455cf1b1U); + R_SCE_func314(476+64); + R_SCE_func100(0xa7b733b2U, 0x289d6efdU, 0x55acdc7aU, 0xad72dedaU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdU); + R_SCE_func080(); + R_SCE_func100(0xc0606955U, 0x53025a57U, 0x2ba842ebU, 0xe1c79ca7U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(408); + R_SCE_func100(0x3be2a735U, 0xcbd16da2U, 0x0938b594U, 0xdae27863U); + R_SCE_func314(408+64); + R_SCE_func100(0x908c1057U, 0x585ed4e4U, 0xc38508a7U, 0x46f60643U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bU); + R_SCE_func080(); + R_SCE_func100(0x57131858U, 0x2ce8a582U, 0x296d4c16U, 0x39d08c82U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(68); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7aU); + R_SCE_func080(); + R_SCE_func100(0x84c0cd15U, 0x2b620dd4U, 0xf287e327U, 0x01072788U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(0); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91U); + R_SCE_func080(); + R_SCE_func100(0x2d3fc6a3U, 0xc945cfa8U, 0xf1bdfd78U, 0x7d834f68U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(612); + R_SCE_func100(0x00abad6bU, 0xe8eace98U, 0x9bbc0fa6U, 0x15bdea7dU); + R_SCE_func314(612+64); + R_SCE_func100(0x401f4023U, 0x1c42be4bU, 0x7205844fU, 0xccd09e1cU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3dU); + R_SCE_func080(); + R_SCE_func100(0xc3bc9b24U, 0x68c0800eU, 0xbb607b1eU, 0x3de7f2a1U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(544); + R_SCE_func100(0x438adbc6U, 0x26cb7a4fU, 0xbbe48db0U, 0x8dcc8ce7U); + R_SCE_func314(544+64); + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000086U; + R_SCE_func101(0xc2bab545U, 0x4b633385U, 0x800a7901U, 0xfe430d39U); + R_SCE_func309_r1(); + R_SCE_func100(0x7569cd34U, 0x193e9b08U, 0x5bfba64aU, 0xb7275878U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bU); + R_SCE_func080(); + R_SCE_func100(0xb93ceb35U, 0xab0f1a81U, 0x1afd42daU, 0x8f11e61aU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(68); + R_SCE_func100(0x785ffadbU, 0x376e09bfU, 0xa3893c05U, 0x0bf8b1d1U); + R_SCE_func314(68+64); + R_SCE_func100(0x7f7c47b6U, 0x96812191U, 0xa6cbb794U, 0x7d92aa44U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7aU); + R_SCE_func080(); + R_SCE_func100(0xe3bf1a4eU, 0xea987511U, 0x61b1a8d9U, 0x8f86988bU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(0); + R_SCE_func100(0x2fb432eaU, 0x28b2a2eeU, 0x25691e4aU, 0x2940a60cU); + R_SCE_func314(0+64); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000002cU; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func311_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func312.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func312.c new file mode 100644 index 0000000000..b17ee46107 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func312.c @@ -0,0 +1,107 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func312(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42f087bfU; + for (iLoop2 = 0; iLoop2 < 64 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func312.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func313.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func313.c new file mode 100644 index 0000000000..06d48da148 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func313.c @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func313(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_04H = 0x00000202U; + for (iLoop2 = 0; iLoop2 < 64 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[ARG1+iLoop2 + 0] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 1] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 2] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func313.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func314.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func314.c new file mode 100644 index 0000000000..ff90bcb555 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func314.c @@ -0,0 +1,94 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func314(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000213U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[ARG1 + 0] = SCE->REG_100H; + S_HEAP[ARG1 + 1] = SCE->REG_100H; + S_HEAP[ARG1 + 2] = SCE->REG_100H; + S_HEAP[ARG1 + 3] = SCE->REG_100H; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func314.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func315.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func315.c new file mode 100644 index 0000000000..7d190b534e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func315.c @@ -0,0 +1,94 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func315(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_28H = 0x00800001U; + SCE->REG_104H = 0x00000157U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_E0H = 0x8181001eU; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = ARG1; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000050U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00bf0001U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func315.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func316.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func316.c new file mode 100644 index 0000000000..30f7836749 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func316.c @@ -0,0 +1,701 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func316(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x00003fbeU; + SCE->REG_28H = 0x009f0001U; + SCE->REG_ECH = 0x0000d779U; + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x80010300U; + SCE->REG_00H = 0x00008307U; + SCE->REG_2CH = 0x000000acU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000031fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000e0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_ECH = 0x3800db1fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x40b7e74cU, 0x3052472cU, 0xec56aed1U, 0x34a95f47U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00a70001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x00000682U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d379U; + R_SCE_func101(0x12c11525U, 0x4ee976f3U, 0xffab05bcU, 0x7893a0d4U); + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x0000001cU; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f0U; + R_SCE_func101(0xea6923e9U, 0xb68fd237U, 0xbbf9f1f5U, 0x197c38b3U); + R_SCE_func317(); + SCE->REG_ECH = 0x00003759U; + SCE->REG_24H = 0x000050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x0000001dU; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f1U; + R_SCE_func101(0xb21a93beU, 0x208b468dU, 0xc6ad078eU, 0xdc017f7bU); + R_SCE_func317(); + SCE->REG_24H = 0x000050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x0000b0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x8000ecd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + for(oLoop2 = 0; oLoop2 < 32; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x00000189U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000030U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000002c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x00001151U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xa448658fU, 0x6c782044U, 0xe71eb7ebU, 0x884a0f9dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x6073cce1U, 0x4146ebfbU, 0x8439025cU, 0x32d89076U); + } + else + { + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000006c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x040091c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xcecf1cf1U, 0x438b4c42U, 0x0a9d3608U, 0xc0bb6d6bU); + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000006c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x302650b1U, 0x54a2bc55U, 0x03697c61U, 0x2f82a689U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xf0fd1c1eU, 0x24834496U, 0xb1b99c74U, 0xe49ec474U); + } + else + { + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000006c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x040091c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x6232b0e4U, 0xd8fd0f9cU, 0xc8078527U, 0x1980ee65U); + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800db20U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x8918301cU, 0xe74dade2U, 0x8fadb8d6U, 0x1f09e06eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000002c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000002c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x00001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xf7220e1dU, 0x35ac4980U, 0x2a65b73cU, 0x3926d84eU); + } + else + { + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x0000d4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x8000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x97cccc98U, 0x67c74453U, 0x595e71efU, 0xfb494dc5U); + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x00004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + R_SCE_func100(0x3a6e7c26U, 0xc218e005U, 0x780a1fa6U, 0x0a58b5f1U); + SCE->REG_E0H = 0x81010340U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x3800db7cU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa86f85e5U, 0xa171519bU, 0xaba7e235U, 0x9c01fb92U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00002fe0U; + R_SCE_func101(0x28296f58U, 0x09545ac2U, 0x4fb93888U, 0x4d7ad0a0U); + } + R_SCE_func101(0x01f2a6ecU, 0xe88edcddU, 0xf2261636U, 0x29218a38U); + } + else + { + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x00001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00002fe0U; + R_SCE_func101(0x90b18c78U, 0x65513aceU, 0x64969dbcU, 0xc3b353f1U); + } + R_SCE_func101(0xa18a2e97U, 0x59f1b496U, 0x6c213132U, 0x56092fbfU); + } + SCE->REG_ECH = 0x38000b5fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800db79U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x8c6658a9U, 0x85e48da6U, 0x01c0b839U, 0x5ca27868U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xc17ead24U, 0x2a699312U, 0x0f92974fU, 0x530c32b7U); + } + else + { + R_SCE_func101(0xae36c5dcU, 0x355a711cU, 0x64f3a02aU, 0x31bd2d28U); + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x00003bbeU; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func316.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func317.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func317.c new file mode 100644 index 0000000000..27d84d2663 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func317.c @@ -0,0 +1,249 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func317(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x00003fbeU; + SCE->REG_28H = 0x00a30001U; + SCE->REG_ECH = 0x00000b39U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x800103c0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3800dbdfU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x151139a8U, 0x3497875cU, 0xdda9a87dU, 0x0d9d6c6bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00a30001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x800103c0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00a30001U; + SCE->REG_ECH = 0x3800dbdfU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x3e417644U, 0x4830b414U, 0x8b1fb172U, 0xefc315e1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00002f20U; + R_SCE_func101(0x12bd9edcU, 0x7748bfc5U, 0x17a2217dU, 0x3d2dfb1aU); + } + else + { + R_SCE_func101(0xf1a67a11U, 0x09ef2610U, 0x350d6edbU, 0x31735e20U); + oLoop1 = 0; + } + } + SCE->REG_ECH = 0x0000537fU; + R_SCE_func101(0x5054260fU, 0xd3d85424U, 0x956fe496U, 0xbe942e2fU); + } + else + { + SCE->REG_28H = 0x00a30001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x800103c0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00a30001U; + SCE->REG_ECH = 0x3800dbdfU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xeaac2040U, 0xa7759217U, 0xbb1695e0U, 0x96aa0527U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x895f52e0U, 0x526148b4U, 0xb1fd05b2U, 0x28a1e88fU); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00002f20U; + R_SCE_func101(0xc148ecaaU, 0xef80ca0cU, 0xf3c55bc0U, 0x7c6f9e4cU); + } + } + SCE->REG_ECH = 0x0000577fU; + R_SCE_func101(0x6bd36181U, 0xa406d6a4U, 0xbd1bbc88U, 0x4ce342a3U); + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x00003bbeU; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func317.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func318.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func318.c new file mode 100644 index 0000000000..bf9ae68798 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func318.c @@ -0,0 +1,3212 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func318(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_ECH = 0x00003fbeU; + R_SCE_func100(0x7301f6afU, 0xa2e43a96U, 0x085014d4U, 0xa0f1f332U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0x7ea9a8e8U, 0x9dae87abU, 0xb8e4ff4eU, 0xfc14f36dU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000015U; + R_SCE_func320(480); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9U); + R_SCE_func080(); + R_SCE_func100(0x02ee115fU, 0x2006eda8U, 0xaad9dc2dU, 0xf0b445c6U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(616); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0xdbc3d67bU, 0xa17d647aU, 0xdb90f11cU, 0xe7534d1bU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(444); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123U); + R_SCE_func080(); + R_SCE_func100(0xb4fec5a8U, 0x63aea9ceU, 0x06617566U, 0x56ea99f2U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(580); + R_SCE_func323(); + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x48d10106U, 0x57af76b9U, 0xe79e1fcbU, 0x2fcbb474U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func321(816); + R_SCE_func100(0x6fcb3e02U, 0xeeebc6d7U, 0xe56480a7U, 0x5b584bc5U); + R_SCE_func314(816+36); + R_SCE_func100(0x2f95e115U, 0x0af86cc9U, 0xc18848b6U, 0x382c6423U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x752ad143U, 0xffc2321cU, 0x0e4bd426U, 0x246202cbU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func321(856); + R_SCE_func100(0xac0039f7U, 0xbb30222aU, 0xc7e41d63U, 0x7977476dU); + R_SCE_func314(856+36); + R_SCE_func100(0xbdb02592U, 0x55ef0f19U, 0x1fe1c157U, 0x52a442f3U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0x9a64096fU, 0x9abb165aU, 0xa3cc1273U, 0xdaba5b9cU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000015U; + R_SCE_func320(408); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730U); + R_SCE_func080(); + R_SCE_func100(0xc276bbeaU, 0xcbb1d556U, 0x89709a9fU, 0xb8ffbc92U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(544); + R_SCE_func323(); + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x59189e01U, 0xf2cde2beU, 0xbd0dabadU, 0xbebe0b3bU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func321(992); + R_SCE_func100(0x4b49462fU, 0xc8367d3dU, 0xd74562ceU, 0x1d07df5eU); + R_SCE_func314(992+36); + R_SCE_func100(0xfdffaa80U, 0x5f9d355fU, 0xa4505dc0U, 0x856b5316U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x326bd82fU, 0x4365081bU, 0x652f03a6U, 0xf1e9fe2bU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func322(816); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x05a121d4U, 0x01e6f8a2U, 0xa87fca3aU, 0x4e92a9b3U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func321(816); + R_SCE_func100(0xa6b0b307U, 0xc81babd4U, 0x3384194cU, 0x7a17a1d2U); + R_SCE_func314(816+36); + R_SCE_func100(0x26380096U, 0x66d2d381U, 0xc73e996eU, 0x23e0c7d9U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0xd88f20ecU, 0x702f8689U, 0x33b8fbdfU, 0x8b48ad27U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000015U; + R_SCE_func320(444); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123U); + R_SCE_func080(); + R_SCE_func100(0x42b788dcU, 0x0bf39b64U, 0x62136015U, 0xcb2b6e3cU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(580); + R_SCE_func323(); + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162U); + R_SCE_func080(); + R_SCE_func100(0x0523fc19U, 0x3424c82eU, 0x1ab204adU, 0x885928eeU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func321(952); + R_SCE_func100(0x66bd04e9U, 0xdcab4797U, 0x0ba98d72U, 0xd78b72ffU); + R_SCE_func314(952+36); + R_SCE_func100(0xa40e00deU, 0xd40f5a52U, 0x1ca31476U, 0xa859f3faU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0xf1c84e91U, 0x824b1944U, 0xacea390eU, 0xbba43d47U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func322(992); + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x64fb6cc4U, 0x52adecabU, 0x38bbcf54U, 0xd58ea7eaU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func321(992); + R_SCE_func100(0xb8b173e8U, 0x3aa7754cU, 0x5ff735eaU, 0x938539c2U); + R_SCE_func314(992+36); + R_SCE_func100(0x4bd64f5bU, 0xc9cec4cdU, 0x9f7b4506U, 0x033a86e9U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x70057b1cU, 0xc1228d3eU, 0x63d8a6afU, 0xc932fba9U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(856); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x8a092b3eU, 0xbd455d61U, 0x0954606cU, 0x5ccb541bU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(856); + R_SCE_func100(0x2fc4762fU, 0x975ae16aU, 0x57abfd77U, 0xbde3b98bU); + R_SCE_func314(856+36); + R_SCE_func100(0x93302376U, 0xefcd0c66U, 0x519a401bU, 0x792080afU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x2beceb85U, 0x107833d1U, 0xa5561c14U, 0xff56f181U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(992); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0xe57e8ab1U, 0xcd9aa59dU, 0xa45e377bU, 0x5e573ce1U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(992); + R_SCE_func100(0x6e9f78c1U, 0x84f6ede8U, 0x4c0b8da7U, 0x22bbcd78U); + R_SCE_func314(992+36); + R_SCE_func100(0xf5ea4d87U, 0x31cf7783U, 0xa660fc6cU, 0x6a4c655fU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x3d41c989U, 0x992167d1U, 0xcb4f9467U, 0x423b7dd0U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x17d5f624U, 0x2f612252U, 0x332fbe63U, 0xfb97779eU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0x573e62c3U, 0x3d443ebaU, 0xed1d0b0fU, 0x74f20245U); + R_SCE_func314(816+36); + R_SCE_func100(0xd76526dfU, 0x0a92a236U, 0x0d3cb2abU, 0xde6a21aaU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162U); + R_SCE_func080(); + R_SCE_func100(0x7d1770c2U, 0x64b25e21U, 0xfca12774U, 0x9f7dee90U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(952); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162U); + R_SCE_func080(); + R_SCE_func100(0xc4ca9045U, 0xfbc63f32U, 0xfcdad2d2U, 0x620dc579U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(952); + R_SCE_func100(0xf972ac1eU, 0x6515ba68U, 0x4018c867U, 0x755cf6c3U); + R_SCE_func314(952+36); + R_SCE_func100(0x2958a235U, 0x5856a072U, 0x4a0a4083U, 0xefe8ed3aU); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0x5ee4997bU, 0x71c13469U, 0x409ab06fU, 0x957c5797U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(480); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9U); + R_SCE_func080(); + R_SCE_func100(0x5c53d776U, 0x92c70653U, 0x38df44e5U, 0xdbd53b16U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(616); + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_24H = 0x0000c8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420U); + R_SCE_func080(); + R_SCE_func100(0x6df97ecaU, 0x26849aa3U, 0x050465c8U, 0x8a12278dU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(896); + R_SCE_func100(0x6949b5f8U, 0x4529de33U, 0xa2c9c04aU, 0xb66414f9U); + R_SCE_func314(896+36); + R_SCE_func100(0xfe8204eaU, 0x446377c6U, 0x94046ab5U, 0x3ff2d743U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x1d5943c8U, 0x813f931cU, 0x480f3522U, 0xb6818432U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(856); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x5be27d18U, 0xc5675cdbU, 0x676e536eU, 0xf0e929daU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(856); + R_SCE_func100(0xc2b48322U, 0x78681058U, 0x36379134U, 0x753f1745U); + R_SCE_func314(856+36); + R_SCE_func100(0xfde6f63eU, 0xfb4e4cabU, 0x10c4b876U, 0xbe3596ccU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0xee8793b0U, 0x3d2a84b4U, 0xc6415643U, 0x55942a21U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x14db0b1fU, 0x43891444U, 0x8549b8f3U, 0xa21f4eedU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0x3ed36b49U, 0xe3fa47a8U, 0xfcfe5d9aU, 0x9b9b30d1U); + R_SCE_func314(816+36); + R_SCE_func100(0x248100ebU, 0x7e089cc6U, 0xeba85e04U, 0x5cb0a332U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0xe6241337U, 0xa4d5b1dfU, 0xb01b4176U, 0x432b6d66U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(992); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x3ab4d3fcU, 0xc4d0ece9U, 0x9b0bc83bU, 0x6a0dbecbU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(992); + R_SCE_func100(0x1ac9c4f0U, 0x33eb3da9U, 0xdee6f4b4U, 0xc8d550a4U); + R_SCE_func314(992+36); + R_SCE_func100(0x13d9e8c4U, 0x80aae640U, 0x7eed3fa9U, 0xa4e455c8U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0x811f9244U, 0x847adc84U, 0x3da44a58U, 0xc3593a96U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(680); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0x4836a1f7U, 0x6abeb483U, 0x6ae3b9eaU, 0x28d4e723U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(408); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730U); + R_SCE_func080(); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(544); + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f0U; + R_SCE_func101(0xdea3f7faU, 0xa08f46e9U, 0x5f0cf626U, 0x80ac51b5U); + R_SCE_func316(); + R_SCE_func100(0x43f38674U, 0xccdc8f42U, 0x9cc9f784U, 0x2cf2535eU); + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0xed26a6bfU, 0xaa36f104U, 0x39112e62U, 0x0f0a647aU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0xa05c50a5U, 0xc10a0ac6U, 0x6ef2ee05U, 0x7191c4bbU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0xf853314aU, 0x7e295d32U, 0x3df236b2U, 0x10602cfbU); + R_SCE_func314(816+36); + R_SCE_func100(0xfe8c8406U, 0xab608ac9U, 0x554ee475U, 0x9c66e46fU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162U); + R_SCE_func080(); + R_SCE_func100(0x722236ddU, 0x57bb3c22U, 0xd80968e1U, 0x9e1dc6a8U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(952); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162U); + R_SCE_func080(); + R_SCE_func100(0x2f72d0a8U, 0xaf4b377eU, 0x25e03009U, 0x71b5c0c5U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(952); + R_SCE_func100(0x3f440a36U, 0x0a5378c5U, 0x45abae51U, 0xc05fdaf7U); + R_SCE_func314(952+36); + R_SCE_func100(0x645c0551U, 0xab4271e6U, 0x3fdb667dU, 0x19c419daU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0xe0f23592U, 0xd1b03f8eU, 0x5f1ba51bU, 0xe62fb898U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(992); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x77850f1eU, 0x59c634eeU, 0xa99d1f3eU, 0x6dc3e242U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(992); + R_SCE_func100(0x1b7193ecU, 0x159d8e03U, 0xadcb540eU, 0xfba64c84U); + R_SCE_func314(992+36); + R_SCE_func100(0x40b14cb8U, 0x84e9f7f0U, 0x81e7e6e5U, 0x63758ed2U); + SCE->REG_28H = 0x008f0001U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000408U; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000080cU; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x8000f4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_24H = 0x000050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cU); + R_SCE_func080(); + R_SCE_func100(0xf14fd41fU, 0xbdbeee1fU, 0x819b1f09U, 0x42d00685U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(752); + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420U); + R_SCE_func080(); + R_SCE_func100(0xde9406d7U, 0x05927008U, 0x202477c7U, 0x3a33491bU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(896); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420U); + R_SCE_func080(); + R_SCE_func100(0x88606427U, 0x6036f077U, 0xb3867c22U, 0xff9623f0U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(896); + R_SCE_func100(0x77c94cd9U, 0xc6ad2e99U, 0xc92bca69U, 0x9385c14bU); + R_SCE_func314(896+36); + R_SCE_func100(0x09dd2f1cU, 0xb140a30fU, 0x17bbc0f6U, 0xf475a11dU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x86ccd603U, 0xe286b95fU, 0x14a77c6eU, 0x16873e05U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(856); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x743fda67U, 0x62cc1e27U, 0xbeba3639U, 0x217ce92eU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(856); + R_SCE_func100(0x240c5821U, 0x25c41b17U, 0x5a6ba87cU, 0x13cf1460U); + R_SCE_func314(856+36); + R_SCE_func100(0x6b475705U, 0x89094f3aU, 0xe89f2f5dU, 0x658ffb52U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x61ad790fU, 0x8da28e8bU, 0x9c83c181U, 0xc9cd002cU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0xb86aa76fU, 0x3fc8f4f8U, 0x6b518a04U, 0xb010e0f2U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0x7e428dfcU, 0xcfcbf0ceU, 0xd7ff64b5U, 0x9d7c2cfcU); + R_SCE_func314(816+36); + R_SCE_func100(0xb0e5e3b6U, 0x9df372c9U, 0xddaf35c6U, 0x0e4db241U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x36e0d5b6U, 0x93f9096cU, 0x2091bfcfU, 0x1588ee52U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(992); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x9cc00091U, 0x1d36c01eU, 0x74aaa668U, 0x7728753dU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(992); + R_SCE_func100(0x3ec5ca73U, 0x697904daU, 0x5cb61c0cU, 0xfe026a09U); + R_SCE_func314(992+36); + R_SCE_func100(0x537723a1U, 0xa5a12c9fU, 0xd3a0fc3eU, 0x7c535b92U); + SCE->REG_28H = 0x008f0001U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000810U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000030U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + R_SCE_func100(0x2743d1e2U, 0x1d020bf8U, 0x0a876514U, 0x442a71dcU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(716); + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0xc9229d76U, 0xc1cd23b8U, 0x4f8e869dU, 0xb6144740U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(856); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0xf07a11b4U, 0x10b43c37U, 0x42ae9daaU, 0x1fdda8f2U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(856); + R_SCE_func100(0x403a7598U, 0xb42694bbU, 0x2f796521U, 0x02268955U); + R_SCE_func314(856+36); + R_SCE_func100(0xd7a26be2U, 0x51610ad5U, 0x34fa706aU, 0x2996a10bU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x922dd6d0U, 0x0b5a99e8U, 0x93618b64U, 0x2b4f903aU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x03e00fe4U, 0x6bcdc3caU, 0x72a4f9efU, 0x3d1e4086U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0x4ce79edeU, 0x181d2741U, 0x0eb99d6cU, 0xbb775ad3U); + R_SCE_func314(816+36); + R_SCE_func100(0x1fe53d97U, 0xfdca5332U, 0x207d37b2U, 0x2b33c950U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162U); + R_SCE_func080(); + R_SCE_func100(0xef88d05eU, 0x12a93706U, 0x9f389d7dU, 0x52daf208U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(952); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162U); + R_SCE_func080(); + R_SCE_func100(0x0bf610d8U, 0x8f8b0151U, 0xe1359a54U, 0x9f44e9cbU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(952); + R_SCE_func100(0xdec039f3U, 0xd8aa1f66U, 0x011510e4U, 0xcb14f413U); + R_SCE_func314(952+36); + R_SCE_func100(0x6854292aU, 0x53637b51U, 0xa1484812U, 0x582ba503U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0xe036f3a4U, 0x91c5bb93U, 0x977fa2d8U, 0x3cd91265U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(992); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x49ec776eU, 0x6d9db6e0U, 0x8c72e89eU, 0x38247d82U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(992); + R_SCE_func100(0xc13ff91cU, 0x6a3cab99U, 0x77b0216cU, 0xbfd759c8U); + R_SCE_func314(992+36); + R_SCE_func100(0x6b82e003U, 0xf7c17b5cU, 0x47d3c4eeU, 0x0f992698U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0x2e47e91dU, 0xb323c5a7U, 0xda241b39U, 0x2f4771e1U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(680); + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162U); + R_SCE_func080(); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func322(952); + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f1U; + R_SCE_func101(0x4c7fc365U, 0x32b6b13dU, 0xb9aef57aU, 0xdace120aU); + R_SCE_func316(); + R_SCE_func100(0x984a67cfU, 0x1d8ff24fU, 0x693552b6U, 0x03b4193eU); + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0xc8b85d56U, 0x121a1d2dU, 0xed50ecd9U, 0x388c29edU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(992); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0xe1599e90U, 0xd998a93aU, 0xe4289afeU, 0x88be2404U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(992); + R_SCE_func100(0xbc397e43U, 0x5a214cd6U, 0xe33e86f4U, 0x54de26f5U); + R_SCE_func314(992+36); + R_SCE_func100(0xbe038b01U, 0xd43d933eU, 0x52d8e9d5U, 0xa2f890a7U); + SCE->REG_28H = 0x008f0001U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000408U; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000080cU; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x8000f4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_24H = 0x000050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cU); + R_SCE_func080(); + R_SCE_func100(0x3fdd0ef1U, 0x82d6f36fU, 0x901b0933U, 0x4787ec5aU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(752); + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0xb3b89345U, 0x69612f4eU, 0x3fc7b4caU, 0xc80e1f5cU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(856); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0xc3ddf579U, 0x2da37448U, 0xd8935424U, 0xa15c7b78U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(856); + R_SCE_func100(0x30ae294dU, 0xfcd7157aU, 0xb86f7f3aU, 0xdf387158U); + R_SCE_func314(856+36); + R_SCE_func100(0x21482dcdU, 0x4ff04b9fU, 0xc5ccfa8fU, 0x4d5e6059U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x1444ca15U, 0xa2a96786U, 0x5734a6a8U, 0xb620b0d1U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x726b3ec5U, 0xfb2d0d3cU, 0x5c0c9ec3U, 0xaae221b5U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0x110666c2U, 0xb0c52da3U, 0x429d7097U, 0x9591f50eU); + R_SCE_func314(816+36); + R_SCE_func100(0x5cbb4691U, 0xaadcfd5eU, 0x7780130dU, 0x2bb5d57cU); + SCE->REG_28H = 0x008f0001U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000810U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000030U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + R_SCE_func100(0xfb6e2134U, 0x09f7c91bU, 0xf9ea5865U, 0xedf4f446U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(716); + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x8b78e5ccU, 0x800c7c29U, 0x22eefb04U, 0x565375c7U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0xfca22bb2U, 0x52d7c5c1U, 0x655cb6a8U, 0xa6a5daedU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0x604c6980U, 0x5be6fb00U, 0xf0506ad3U, 0x536a2aa5U); + R_SCE_func314(816+36); + R_SCE_func100(0x5e23272cU, 0x43b5f301U, 0x48042cbfU, 0x82db1a81U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x0440b8e4U, 0x0b364ca9U, 0xdf6309adU, 0xab4a598dU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(992); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + R_SCE_func100(0x4a971b28U, 0xf38ff73eU, 0x6ce1ec63U, 0x21ad9d5bU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(992); + R_SCE_func100(0x58dcfedeU, 0xa3fec5d7U, 0xf3c7654cU, 0x1216e257U); + R_SCE_func314(992+36); + R_SCE_func100(0x78e69936U, 0x47a9638fU, 0x4802fd7cU, 0x9d394316U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0xc7b10292U, 0xa6580db6U, 0xe7922787U, 0xaa9a9afcU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(680); + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beU); + R_SCE_func080(); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func322(992); + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f2U; + R_SCE_func101(0xdded1fd4U, 0x23dab4ddU, 0x586378b6U, 0xdef4ea11U); + R_SCE_func316(); + R_SCE_func100(0x63f8abe6U, 0x7d1d9cd9U, 0x5e033906U, 0x4626bd04U); + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x139f3f4cU, 0xbc1b1f44U, 0xe2be2abbU, 0x6dabf567U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0xd09d83ecU, 0x81ce8424U, 0x72696314U, 0x260f5d88U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0xacfb40e3U, 0x56fb170fU, 0x42239336U, 0x6b00e166U); + R_SCE_func314(816+36); + R_SCE_func100(0x9609949fU, 0x154f5562U, 0x600f1f93U, 0xcc487c25U); + SCE->REG_28H = 0x008f0001U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000408U; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000080cU; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x8000f4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_24H = 0x000050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cU); + R_SCE_func080(); + R_SCE_func100(0xfb853215U, 0xc01b4dfbU, 0x66d123a6U, 0xb42a1211U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(752); + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420U); + R_SCE_func080(); + R_SCE_func100(0x372a899fU, 0x05b2990cU, 0x9a23f97bU, 0xdbe9bcb5U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(896); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420U); + R_SCE_func080(); + R_SCE_func100(0x03e607b1U, 0x153ab930U, 0x69b99779U, 0x6ef64341U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(896); + R_SCE_func100(0xb53a0a02U, 0xbc8f728aU, 0xf8d4e2c0U, 0xe0aea320U); + R_SCE_func314(896+36); + R_SCE_func100(0x6a9ec828U, 0xeadb95f6U, 0x38290728U, 0x00535632U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x5be8f1b4U, 0xeddfc668U, 0xa9135cafU, 0x02b06c39U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(856); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0xe30f0785U, 0x534b0b88U, 0xf67684e9U, 0x39e9ad62U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(856); + R_SCE_func100(0x30a29e72U, 0x1aaee90fU, 0x0b2a6848U, 0x2dce8f9dU); + R_SCE_func314(856+36); + R_SCE_func100(0xd734cdfeU, 0x4a9c3852U, 0x7d3bdd37U, 0xd223d74dU); + SCE->REG_28H = 0x008f0001U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000810U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20U; + SCE->REG_24H = 0x80005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000030U; + SCE->REG_24H = 0x80007cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + R_SCE_func100(0x0f28538fU, 0x2d9e2b97U, 0x80f1104cU, 0x98f70fc5U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(716); + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x82ce615aU, 0xf3f4c11aU, 0x791257c0U, 0xc835effeU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(856); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x04f1679dU, 0x9386f125U, 0xe79207d8U, 0x2b4e7ce3U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func322(816); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x56b968d4U, 0xbb4542c4U, 0xc7fdf1a6U, 0xb74902e8U); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func321(816); + R_SCE_func100(0x91bccc1eU, 0xe9aa700bU, 0x2f16c337U, 0xd42f1beeU); + R_SCE_func314(816+36); + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x800103e0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x800103c0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x3800dbffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa0a32930U, 0xee7ad79dU, 0x8a9b73b0U, 0x72e3f467U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0xffffffffU; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xacdb7295U, 0x481a09cdU, 0xe19df18cU, 0x0e6d7070U); + } + else + { + SCE->REG_ECH = 0x00000800U; + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x472d3a91U, 0x41c50148U, 0xfa167367U, 0x071d944cU); + } + R_SCE_func100(0xd7f90576U, 0xc6d8e8edU, 0xc11dd4bcU, 0xe0889a30U); + SCE->REG_ECH = 0x000034ffU; + SCE->REG_ECH = 0x00003420U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_ECH = 0x00003460U; + SCE->REG_ECH = 0x00003480U; + SCE->REG_ECH = 0x000034a0U; + SCE->REG_ECH = 0x000034c0U; + SCE->REG_E0H = 0x81080000U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000804U; + SCE->REG_24H = 0x800090d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c04U; + SCE->REG_24H = 0x800090d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x8000b0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x2baf06cdU, 0xceabba9dU, 0x6f325b5fU, 0x128c3dfbU); + SCE->REG_00H = 0x00002393U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func321(856); + R_SCE_func100(0x06a281abU, 0x29577c24U, 0x6a60fabaU, 0x3c4fd844U); + R_SCE_func314(856+36); + R_SCE_func100(0xd218cc15U, 0x5b32e7b5U, 0x9cf75f12U, 0xe7e27ac7U); + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800090d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420U); + R_SCE_func080(); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func322(896); + SCE->REG_28H = 0x00a30001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x3800dbdfU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x2b323db5U, 0xec65dceaU, 0x10c67c33U, 0x673bfdccU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0xffffffffU; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x82001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x8a78a013U, 0xba3c256dU, 0x8cecbd71U, 0xe1b1f2b5U); + } + else + { + SCE->REG_ECH = 0x00000800U; + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800080d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x8945eb8fU, 0x02f1b21cU, 0x0c0670e7U, 0x6c8ccd5eU); + } + SCE->REG_ECH = 0x000034feU; + SCE->REG_ECH = 0x00003420U; + SCE->REG_ECH = 0x00003440U; + SCE->REG_ECH = 0x00003460U; + SCE->REG_ECH = 0x00003480U; + SCE->REG_ECH = 0x000034a0U; + SCE->REG_ECH = 0x000034c0U; + SCE->REG_E0H = 0x81080000U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000804U; + SCE->REG_24H = 0x800090d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c04U; + SCE->REG_24H = 0x800090d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x8000b0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x0bbfba54U, 0xbe72dc2eU, 0x70ff4cc5U, 0xf901d02cU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058U); + R_SCE_func080(); + R_SCE_func100(0x6b9735d3U, 0xbf036b7cU, 0x9ca9e12fU, 0x194aaa27U); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func322(816); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63U); + R_SCE_func080(); + R_SCE_func100(0x5fdd5dedU, 0x648128f9U, 0x2a6600e9U, 0x7b573f5dU); + SCE->REG_00H = 0x00003293U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func322(856); + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000012c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0xae90bdbdU, 0xc2ad7a3cU, 0x0fdcf164U, 0xcb258d9cU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(680); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + R_SCE_func100(0x64628748U, 0x8c07f7e1U, 0xb8d692b2U, 0xb8b193eeU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000015U; + R_SCE_func320(716); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cU); + R_SCE_func080(); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(752); + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x800060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x800103e0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x3800dbffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x36902af6U, 0x5e67376dU, 0x90349b01U, 0xab907f1aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x800103e0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3800dbffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x6854bf0bU, 0xbd60364dU, 0xaa9b54dbU, 0x709ad19bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x9ac23d34U, 0x03a9e720U, 0x9cc54721U, 0x178492eaU); + oLoop1 = 0; + } + else + { + R_SCE_func101(0x00dfd565U, 0x568cd553U, 0xa872e139U, 0x978c7965U); + } + } + } + else + { + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x800103e0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3800dbffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xccbb14a0U, 0x64e553c2U, 0xd459eed0U, 0x53d4c0e3U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x3e3faeb8U, 0xe332932fU, 0x74810598U, 0x70b6d1f5U); + oLoop1 = 0; + } + else + { + R_SCE_func101(0xbcf0e6b4U, 0x8c156494U, 0x028cdf93U, 0xe04f4ec8U); + } + } + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_ECH = 0x00003bbeU; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func318.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func319.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func319.c new file mode 100644 index 0000000000..b3e60dfe10 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func319.c @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func319(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x00000700U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_04H = 0x00000282U; + for (iLoop2 = 0; iLoop2 < 32 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[ARG1+iLoop2 + 0] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 1] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 2] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func319.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func320.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func320.c new file mode 100644 index 0000000000..5c4d115011 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func320.c @@ -0,0 +1,107 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func320(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00001f62U; + SCE->REG_D0H = 0x00000700U; + SCE->REG_C4H = 0x42f087bfU; + for (iLoop2 = 0; iLoop2 < 32 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func320.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func321.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func321.c new file mode 100644 index 0000000000..cd7da9e10d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func321.c @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func321(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x00000800U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_04H = 0x00000292U; + for (iLoop2 = 0; iLoop2 < 36 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[ARG1+iLoop2 + 0] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 1] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 2] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func321.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func322.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func322.c new file mode 100644 index 0000000000..95705aadf0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func322.c @@ -0,0 +1,107 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func322(uint32_t ARG1) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00002362U; + SCE->REG_D0H = 0x00000800U; + SCE->REG_C4H = 0x42f087bfU; + for (iLoop2 = 0; iLoop2 < 36 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func322.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func323.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func323.c new file mode 100644 index 0000000000..9096483777 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func323.c @@ -0,0 +1,182 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func323(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x000060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000002c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_24H = 0x00000981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000002c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001U; + SCE->REG_24H = 0x00001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000480aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func323.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func324.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func324.c new file mode 100644 index 0000000000..2754308fea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func324.c @@ -0,0 +1,942 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func324(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00003fbeU; + R_SCE_func100(0x429de192U, 0xa16d9682U, 0x418795f3U, 0xe9239d90U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0x00512c7dU, 0xb2e066fbU, 0x2da6f8f2U, 0x29977d57U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(680); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + R_SCE_func100(0x222fc4deU, 0x0bd3a9cdU, 0xa8b95887U, 0x285e7485U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000015U; + R_SCE_func320(716); + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cU); + R_SCE_func080(); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(752); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + oLoop1 = 1; + while(oLoop1 == 1) + { + R_SCE_func100(0xafcf0809U, 0xe2265259U, 0x7768feafU, 0x320f0fcbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x40a54325U, 0xaeef9d77U, 0x30adfefeU, 0xd0040ad2U); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func101(0x2295cc6cU, 0xf9e30bb5U, 0xe57ac962U, 0xd1b2dda3U); + } + } + R_SCE_func100(0x68757846U, 0xd8685994U, 0x65ee0365U, 0xf90a0df9U); + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cU); + R_SCE_func080(); + R_SCE_func100(0x3461e611U, 0xf04c888dU, 0x42b43f82U, 0x14db3542U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(136); + R_SCE_func100(0x5c08a548U, 0x9b5d3c83U, 0x19770369U, 0x641e4213U); + R_SCE_func314(136+32); + R_SCE_func100(0x97562bf0U, 0x4e966879U, 0x73bb6401U, 0xc8ea7174U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6U); + R_SCE_func080(); + R_SCE_func100(0x2fa6101aU, 0x3eef4bb6U, 0x3ec58dfbU, 0x52d243b0U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(172); + R_SCE_func100(0x80554a29U, 0xbac83d5eU, 0xa3e18209U, 0x51346e43U); + R_SCE_func314(172+32); + R_SCE_func100(0xc3424aa9U, 0x650486ebU, 0x85b67ffeU, 0x2c144f41U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1U); + R_SCE_func080(); + R_SCE_func100(0x555c07d3U, 0x5622185aU, 0x6242cca1U, 0xce1345feU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(208); + R_SCE_func100(0xd7ad59a8U, 0xbfc6dcafU, 0x90f394ebU, 0x637e4e40U); + R_SCE_func314(208+32); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000a52U; + for (iLoop = 0; iLoop < 128; iLoop = iLoop + 1) + { + R_SCE_func100(0x6ec8063dU, 0x22eb9ea5U, 0x9f6d07aeU, 0x8fab2affU); + SCE->REG_24H = 0x040049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0400d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02000149U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0x8afbdd55U, 0x8b82f03cU, 0x1fa8fab3U, 0xe293d320U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(680); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000015U; + R_SCE_func320(716); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00002e40U; + R_SCE_func101(0x318d1c4aU, 0x2eb21cf3U, 0xbc389f93U, 0x8dee3437U); + } + SCE->REG_ECH = 0x38008a40U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func100(0x1776415eU, 0xa47b9dc0U, 0xe55c378dU, 0x8f9360e1U); + SCE->REG_24H = 0x040049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x040019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0400d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x020019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0x59d90514U, 0x07ceab5fU, 0x25b7f032U, 0xb6fe2a07U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(680); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + R_SCE_func100(0x10b25a83U, 0xba221802U, 0x00f94ba4U, 0x5b582f2eU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000015U; + R_SCE_func320(716); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0x1c7af639U, 0xb715e1e8U, 0x04cba709U, 0x44648b64U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(408); + R_SCE_func100(0x388a7f76U, 0x1907bb17U, 0xe9688385U, 0x0e33ee71U); + R_SCE_func314(408+32); + R_SCE_func100(0x2f3e6a11U, 0x92b21123U, 0x9890bcabU, 0x22efd7dcU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0xd5439bcaU, 0x1dfcdff3U, 0xf8a3c6e2U, 0x4b08c893U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(444); + R_SCE_func100(0x639f523cU, 0x7f22c2aeU, 0x35b2dfdcU, 0xb7629597U); + R_SCE_func314(444+32); + R_SCE_func100(0x183f24f4U, 0x51672d5dU, 0xbe1aa4f9U, 0x5c631c4eU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730U); + R_SCE_func080(); + R_SCE_func100(0x4c452484U, 0xd7cfec48U, 0xfc4979f4U, 0x5749b02cU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(544); + R_SCE_func100(0x8d9fea97U, 0x8c7429feU, 0xb110c9ebU, 0x3a4bd5a5U); + R_SCE_func314(544+32); + R_SCE_func100(0xd02f485eU, 0xff4c069cU, 0xe2b919d1U, 0x7f54f343U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123U); + R_SCE_func080(); + R_SCE_func100(0x0bfcc270U, 0x8a9ea7c0U, 0x67d45212U, 0x8bf4084cU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(580); + R_SCE_func100(0x819d87b5U, 0xc2a94a8aU, 0x262f0072U, 0x28afab02U); + R_SCE_func314(580+32); + R_SCE_func100(0x28714cdeU, 0xee98a453U, 0xb4127422U, 0xe3c5faabU); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0x0be5ab75U, 0x876af442U, 0x8cab5b07U, 0xd97c16d2U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(480); + R_SCE_func100(0x9955ffc5U, 0x788a5c58U, 0x2dc38677U, 0x918d0bc3U); + R_SCE_func314(480+32); + R_SCE_func100(0x44caa811U, 0x693f746eU, 0xf086598eU, 0xddcc39f7U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9U); + R_SCE_func080(); + R_SCE_func100(0x4b253f69U, 0x2e6d8306U, 0x980ff2faU, 0x32b41e2bU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(616); + R_SCE_func100(0x41af8c4dU, 0x3d54687cU, 0x017cfc3eU, 0xe342e1ecU); + R_SCE_func314(616+32); + SCE->REG_ECH = 0x00000a52U; + for (iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f0U; + R_SCE_func101(0x9b1ff368U, 0x4d24aca2U, 0x8a2921baU, 0x6e85a843U); + R_SCE_func318(); + R_SCE_func100(0x81d9aff3U, 0x7367f41bU, 0x9984bacfU, 0xc03b1097U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0x45c55453U, 0x937fcc24U, 0xf9641819U, 0x08a66517U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(408); + R_SCE_func100(0xfdbce1dfU, 0x51695a47U, 0x716e460bU, 0xf5051005U); + R_SCE_func314(408+32); + R_SCE_func100(0xc5071c70U, 0x70927937U, 0x796a3d8bU, 0x96a6b537U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0x835d0de8U, 0xec0c509bU, 0xa22176c7U, 0xd1a34c28U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(444); + R_SCE_func100(0x890ec5c3U, 0x1d13c4a4U, 0xd1062b82U, 0x70ae5b5eU); + R_SCE_func314(444+32); + R_SCE_func100(0xb86747fdU, 0x6ef17382U, 0xd9bbb572U, 0xc4451452U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0x5b0cef20U, 0x5049f5cfU, 0x8ef92436U, 0x4a039351U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(480); + R_SCE_func100(0x87d35587U, 0xc1846f2dU, 0xd29efed1U, 0xa1f22ea7U); + R_SCE_func314(480+32); + R_SCE_func100(0x3b9f198aU, 0xc82cedb5U, 0xbdff48e6U, 0x3b28799fU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730U); + R_SCE_func080(); + R_SCE_func100(0x0ac8ef5aU, 0x4dcb4f13U, 0xb920af68U, 0x892e4d61U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(544); + R_SCE_func100(0xc44766f1U, 0xd92045ccU, 0xc72b724bU, 0xdc75527bU); + R_SCE_func314(544+32); + R_SCE_func100(0x47a32024U, 0x5e5c6264U, 0xabad0bf0U, 0x8bef0a8dU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123U); + R_SCE_func080(); + R_SCE_func100(0xadaf2346U, 0x8b8cd487U, 0xef661c72U, 0xfba75a20U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(580); + R_SCE_func100(0xbe3dd14fU, 0xe26b0965U, 0xd6023466U, 0x9d9bedd3U); + R_SCE_func314(580+32); + R_SCE_func100(0x59bccd45U, 0x61c1e417U, 0xe8015039U, 0xc3ef0fdeU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9U); + R_SCE_func080(); + R_SCE_func100(0x9203fb89U, 0x4e066d76U, 0x1c201e78U, 0x2bedb566U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(616); + R_SCE_func100(0xb6cf0cfdU, 0x1cbc0e56U, 0xb971023fU, 0xe7b05c43U); + R_SCE_func314(616+32); + SCE->REG_ECH = 0x00002e40U; + R_SCE_func101(0x5560f6eeU, 0x27632186U, 0x0ef19804U, 0xb4018f81U); + } + SCE->REG_ECH = 0x38008a40U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f1U; + R_SCE_func101(0xe5ce2b69U, 0x42ca9a52U, 0x4168e50eU, 0xf53e4bc9U); + R_SCE_func318(); + R_SCE_func100(0x31338abbU, 0x54b02d89U, 0x60484eedU, 0x81edd3fdU); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0x3f87dcaeU, 0x4d0d13c8U, 0xce04b35aU, 0x1d18dfe0U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(408); + R_SCE_func100(0xcb0c6b2dU, 0xa0238485U, 0x52437900U, 0x84f3223fU); + R_SCE_func314(408+32); + R_SCE_func100(0xb30570f7U, 0x550e5073U, 0x833895feU, 0x1f096b6aU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0xec38ef60U, 0x905fbef5U, 0xfa4f292fU, 0xb4770a02U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(444); + R_SCE_func100(0x6d7e5f89U, 0xe754abecU, 0xeb71227dU, 0x51a744dcU); + R_SCE_func314(444+32); + R_SCE_func100(0x38caef72U, 0x59315978U, 0x9c2df5b1U, 0x5d8c5881U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0xd1b3702dU, 0x223bb42dU, 0xc707ca74U, 0xccd4be7bU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(480); + R_SCE_func100(0x2b002e59U, 0x6564762eU, 0xa88743baU, 0x4d76e65eU); + R_SCE_func314(480+32); + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f2U; + R_SCE_func101(0xab310cadU, 0x1a6dca44U, 0x97176702U, 0xfa7c0ff0U); + R_SCE_func318(); + R_SCE_func100(0x7bb51f88U, 0x40a88938U, 0x74900bcaU, 0xc3e6d98dU); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d34587U); + R_SCE_func080(); + R_SCE_func100(0x46f636eaU, 0xae5727e9U, 0x17ad1439U, 0x7c106643U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(272); + R_SCE_func100(0x244cf7a6U, 0x2f8e4941U, 0x84d900eeU, 0x835417eeU); + R_SCE_func314(272+32); + R_SCE_func100(0xabb3f445U, 0x029cfcbaU, 0x58ece236U, 0xc2b8ce24U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01315552U); + R_SCE_func080(); + R_SCE_func100(0x2a3a3da1U, 0x35c62dadU, 0xb1091148U, 0xbf194399U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(308); + R_SCE_func100(0x733b65c9U, 0xd4df45e5U, 0xa1f7a313U, 0xe2d839b7U); + R_SCE_func314(308+32); + R_SCE_func100(0x34569306U, 0x2c1f5275U, 0x1041511aU, 0x376aac73U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011a27dfU); + R_SCE_func080(); + R_SCE_func100(0x2b2f00d7U, 0x4afe6c1bU, 0x50446006U, 0xfca93898U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(344); + R_SCE_func100(0x3e2eb434U, 0xa39ea329U, 0x159ff237U, 0xb88019efU); + R_SCE_func314(344+32); + R_SCE_func100(0x3ac7452dU, 0x7a09e2aaU, 0x8db465ffU, 0x363be7e5U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0x94fa60e7U, 0x9d459e0dU, 0x530f958bU, 0x5be9a16cU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(408); + R_SCE_func100(0x11c507deU, 0xb21f112eU, 0xa8d75ec7U, 0x6c1073c7U); + R_SCE_func314(408+32); + R_SCE_func100(0x9899dcaeU, 0x20b54bb0U, 0xb3bcd7a3U, 0x1c6120e0U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0x60e30c92U, 0x0c85d6d0U, 0xf2e9becdU, 0x2a727b4bU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(444); + R_SCE_func100(0x93f0cef1U, 0xcd9397b5U, 0x859a25f2U, 0xdd0814d8U); + R_SCE_func314(444+32); + R_SCE_func100(0xbc9ff10cU, 0xbc2cf830U, 0xf76d73f9U, 0x1d7c91f4U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0x2ed705bbU, 0xaba0d099U, 0x0e58d5bfU, 0x00b631daU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(480); + R_SCE_func100(0xa54075aeU, 0xb4f2bb0eU, 0xb727972aU, 0x62d373e6U); + R_SCE_func314(480+32); + R_SCE_func100(0x525ca907U, 0x4dea3d68U, 0xca687068U, 0xfff525c5U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091U); + R_SCE_func080(); + R_SCE_func100(0xb2b2a788U, 0xd5162840U, 0xe98d6baeU, 0x3d8887f4U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(0); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4U); + R_SCE_func080(); + R_SCE_func100(0x47e414afU, 0xa3d215d7U, 0x5fd450f5U, 0xdaa9831aU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000013U; + R_SCE_func320(36); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420U); + R_SCE_func080(); + R_SCE_func100(0x5c073441U, 0xb1b7d0a4U, 0x54afdfe9U, 0x428aab6aU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(72); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730U); + R_SCE_func080(); + R_SCE_func100(0x06fada7fU, 0x91d16c9dU, 0xc69c303aU, 0xf29e27c9U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(544); + R_SCE_func100(0xf12eea57U, 0x9c7a9746U, 0x94ba172bU, 0x8a98a7f3U); + R_SCE_func314(544+32); + R_SCE_func100(0xcfb9e44eU, 0x67a00eccU, 0x9f4ab7daU, 0xb8155a69U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123U); + R_SCE_func080(); + R_SCE_func100(0xf4ac2160U, 0xcce69e5cU, 0x4bf3f1f6U, 0x6874de45U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(580); + R_SCE_func100(0x80cfd405U, 0x0d90d9b3U, 0x6f5bbb8cU, 0xc5208b78U); + R_SCE_func314(580+32); + R_SCE_func100(0x87a70014U, 0x2f1596f6U, 0xe10448d9U, 0xf177200fU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9U); + R_SCE_func080(); + R_SCE_func100(0xf480cf8eU, 0x9865a7adU, 0x1cb9a0ccU, 0xb511e0acU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(616); + R_SCE_func100(0x63ad7fd6U, 0x135155a2U, 0x5157be4dU, 0xd7467a88U); + R_SCE_func314(616+32); + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f3U; + R_SCE_func101(0xef91da34U, 0x491d24c5U, 0xe1cb37c9U, 0x7822bc7fU); + R_SCE_func318(); + R_SCE_func100(0x61374fa5U, 0xfba64b54U, 0x17a2bb60U, 0x64e10b2bU); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091U); + R_SCE_func080(); + R_SCE_func100(0xd36c8788U, 0x33f7fcefU, 0x4b3678e6U, 0x6d7ca149U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(0); + R_SCE_func100(0x8f8db157U, 0x66a51e0fU, 0xf4ba03ebU, 0x3bc031e8U); + R_SCE_func314(0+32); + R_SCE_func100(0xbe1491d9U, 0x689fa1faU, 0x03c77f53U, 0x95f9dcbcU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4U); + R_SCE_func080(); + R_SCE_func100(0x2d7492eaU, 0x4b601209U, 0xbec2c501U, 0xdd80624cU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(36); + R_SCE_func100(0x8c75f085U, 0xdc06e331U, 0x7bb203adU, 0x2b28ab69U); + R_SCE_func314(36+32); + R_SCE_func100(0xf6ddd89eU, 0xa015673eU, 0x5c73b7caU, 0xa48d5a8eU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420U); + R_SCE_func080(); + R_SCE_func100(0x0eb0c917U, 0xe78a5902U, 0x1988afe2U, 0x366b221dU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(72); + R_SCE_func100(0x8ea1777aU, 0x5a8c56c5U, 0xa93e7fa8U, 0x4fc44a55U); + R_SCE_func314(72+32); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00003bbeU; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func324.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func325.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func325.c new file mode 100644 index 0000000000..c1b58667ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func325.c @@ -0,0 +1,708 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_func325_r1(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00003fbeU; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f0U; + R_SCE_func101(0x01df4410U, 0x25186facU, 0xc0075b91U, 0x7743fcadU); + R_SCE_func324(); + SCE->REG_ECH = 0x00000a73U; + SCE->REG_ECH = 0x00000a31U; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x00002e20U; + SCE->REG_ECH = 0x38002673U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x908f652fU, 0x12371bfeU, 0x96ad2afeU, 0x6d9d50f3U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x11e5f4f1U, 0x6d84a57aU, 0xc809f751U, 0x99636076U); + } + else + { + R_SCE_func100(0xfa2e0ea1U, 0xea818c35U, 0x206dd7d8U, 0xa982af56U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cU); + R_SCE_func080(); + R_SCE_func100(0x601d254bU, 0xc6c8196aU, 0x822d4883U, 0x9884b420U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(136); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6U); + R_SCE_func080(); + R_SCE_func100(0x7db7dc7bU, 0xc4a198eeU, 0x9110a238U, 0x0e1526e3U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000013U; + R_SCE_func320(172); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1U); + R_SCE_func080(); + R_SCE_func100(0x1f97b750U, 0xabf9cf2dU, 0x02f06b86U, 0x607cf951U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(208); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0x775c82b8U, 0xbffd76d9U, 0xf0b31502U, 0x55643534U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(408); + R_SCE_func100(0xb39891fbU, 0x61bdd3d2U, 0x9cdcf4a3U, 0x9547c3d6U); + R_SCE_func314(408+32); + R_SCE_func100(0x2d57513fU, 0xcdc90ceaU, 0x422ca489U, 0xf15cd933U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0x446d6820U, 0x9a780882U, 0xa6e287a6U, 0x0e609579U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(444); + R_SCE_func100(0xe0c086e1U, 0xd25b71bbU, 0xf516549aU, 0x86a946efU); + R_SCE_func314(444+32); + R_SCE_func100(0xe56eed48U, 0x85b8e7b6U, 0x1acaef41U, 0xd213ea22U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0xb91c5c86U, 0x79eafe0aU, 0xaea965e8U, 0xd122ee72U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(480); + R_SCE_func100(0x587c5d00U, 0x624336d5U, 0x253445a1U, 0xbdacb006U); + R_SCE_func314(480+32); + R_SCE_func100(0x9cd90b3eU, 0x5eb55e97U, 0x87cfa963U, 0x77434f39U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730U); + R_SCE_func080(); + R_SCE_func100(0xc17847b2U, 0x8830192fU, 0x546a11d8U, 0x99341ce0U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(544); + R_SCE_func100(0x210ad79dU, 0x19a3f01dU, 0x5892e46dU, 0x50c7d007U); + R_SCE_func314(544+32); + R_SCE_func100(0x1007e210U, 0x980e5ae9U, 0xfbbd5ad2U, 0x5a9d8c47U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123U); + R_SCE_func080(); + R_SCE_func100(0xbc75c1adU, 0x16be37efU, 0x073750ffU, 0x0194fc3cU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(580); + R_SCE_func100(0x342e81f6U, 0x80bcaddaU, 0x643a5cb6U, 0xfb297621U); + R_SCE_func314(580+32); + R_SCE_func100(0xc4f9eb6dU, 0x84423fb8U, 0x9ef8a114U, 0x0e872738U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9U); + R_SCE_func080(); + R_SCE_func100(0x27437ef9U, 0x737420f5U, 0xf2152a8cU, 0x8f3366fbU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(616); + R_SCE_func100(0x5e070d2bU, 0x2861ec9cU, 0xddebfea5U, 0x5e6be40aU); + R_SCE_func314(616+32); + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f4U; + R_SCE_func101(0xff70890fU, 0x42bf2db5U, 0x47f3d876U, 0x15efdd95U); + R_SCE_func318(); + R_SCE_func100(0x33b2c103U, 0x35cb8539U, 0x56b06866U, 0x4496966fU); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cU); + R_SCE_func080(); + R_SCE_func100(0xea115848U, 0xc136437aU, 0x04fe56c0U, 0xd48d25ddU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(136); + R_SCE_func100(0xbc4c710eU, 0xc7de105dU, 0xc8d43f55U, 0x27945787U); + R_SCE_func314(136+32); + R_SCE_func100(0x65d1858eU, 0x03b01766U, 0x42993855U, 0x94615f05U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6U); + R_SCE_func080(); + R_SCE_func100(0x9e9a7975U, 0xdc725576U, 0xef02d451U, 0xa467d07bU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(172); + R_SCE_func100(0x6a7e51c7U, 0x0eb23b27U, 0x03540e70U, 0xe742d295U); + R_SCE_func314(172+32); + R_SCE_func100(0x317f2bafU, 0xb085e6b7U, 0x9f0747f6U, 0x64a609a5U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1U); + R_SCE_func080(); + R_SCE_func100(0xd3e19b21U, 0xb41fa8a9U, 0x435dd6abU, 0xbe11660eU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(208); + R_SCE_func100(0x5576a380U, 0x6246414cU, 0xad16a8caU, 0x4339e99eU); + R_SCE_func314(208+32); + R_SCE_func101(0xbb2ae5dfU, 0x7a22b126U, 0xac410c1cU, 0x20aeb880U); + } + SCE->REG_ECH = 0x3800da9fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa9d5449cU, 0xe39f423dU, 0x8ff10b63U, 0x073b3b82U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0xefb7b8baU, 0x7e980dcbU, 0x1ee49179U, 0x3586b701U); + } + else + { + R_SCE_func100(0x6236b7f6U, 0x7ca8b230U, 0x2beb8a3eU, 0xe9c3edf7U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cU); + R_SCE_func080(); + R_SCE_func100(0x2495874bU, 0xf92c43dbU, 0xabc3130dU, 0xffbeee97U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(136); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6U); + R_SCE_func080(); + R_SCE_func100(0xed242108U, 0xbcaca17bU, 0xec49b686U, 0x9e592caeU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000013U; + R_SCE_func320(172); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1U); + R_SCE_func080(); + R_SCE_func100(0x0bcb5242U, 0x104610faU, 0xda01cde6U, 0xcf0537efU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(208); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0x43c6fc85U, 0x9f089d2dU, 0xd7a50b8aU, 0x291459afU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(408); + R_SCE_func100(0xaeced1cbU, 0x972bea38U, 0x2e208deaU, 0xa9378501U); + R_SCE_func314(408+32); + R_SCE_func100(0x5a418b38U, 0xa59b548bU, 0xc3aa4612U, 0x0a4269f2U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0x4d05f620U, 0xcb0fa529U, 0x1cdd6d5bU, 0x0cc0daf0U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(444); + R_SCE_func100(0xc2a94833U, 0x617cecb0U, 0xb0855d1fU, 0xd5fa993eU); + R_SCE_func314(444+32); + R_SCE_func100(0x090a524dU, 0x2727222eU, 0xa181dc2fU, 0x2bcd369eU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0x426074f3U, 0x912a899eU, 0x0778666eU, 0xf074b79cU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(480); + R_SCE_func100(0xbb422d79U, 0xa1a4a813U, 0x89b0018bU, 0xb0190a52U); + R_SCE_func314(480+32); + R_SCE_func100(0xd1416e14U, 0x81b8018eU, 0x2aa99d77U, 0x5da75233U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091U); + R_SCE_func080(); + R_SCE_func100(0x5ecf3095U, 0x7125a761U, 0xaff4ef2cU, 0xc491d26bU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(0); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4U); + R_SCE_func080(); + R_SCE_func100(0x2195c9cdU, 0x9edd401fU, 0x095ffd48U, 0x957e05c1U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000013U; + R_SCE_func320(36); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420U); + R_SCE_func080(); + R_SCE_func100(0x5e05c154U, 0x9dc5de79U, 0x5b9d8e95U, 0xc72b0350U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(72); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730U); + R_SCE_func080(); + R_SCE_func100(0x73475eaeU, 0xc4f26631U, 0xbcfb74dbU, 0x8b0350ceU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(544); + R_SCE_func100(0x2e04d1b2U, 0xabefad23U, 0xf52411ecU, 0x5e724018U); + R_SCE_func314(544+32); + R_SCE_func100(0x3cbc8a76U, 0x2fded6c9U, 0x2cf5498bU, 0x275e02e1U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123U); + R_SCE_func080(); + R_SCE_func100(0xaf402062U, 0xad155a0eU, 0xa5900c85U, 0xdb1608d0U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(580); + R_SCE_func100(0x9dce9b00U, 0x123ca2e7U, 0x01139d9fU, 0x738d77acU); + R_SCE_func314(580+32); + R_SCE_func100(0xa3448e88U, 0x03d0664bU, 0xb55fac14U, 0xdea30f7bU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9U); + R_SCE_func080(); + R_SCE_func100(0x5aa8caecU, 0xf96ce569U, 0xb803673bU, 0x365dacafU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(616); + R_SCE_func100(0x0b5d830eU, 0x25e4e603U, 0xddf8cacdU, 0x8cc7eea0U); + R_SCE_func314(616+32); + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f5U; + R_SCE_func101(0x5e20bf36U, 0x3430e9e4U, 0x748595e5U, 0x1fa1c9d6U); + R_SCE_func318(); + R_SCE_func100(0xc2ba1825U, 0x298bad26U, 0x9071d1a1U, 0x66e7b5dcU); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cU); + R_SCE_func080(); + R_SCE_func100(0x996c6c24U, 0x58ae383bU, 0xcae34a0dU, 0x11cb0722U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(136); + R_SCE_func100(0x16da167aU, 0x70428448U, 0x883bc530U, 0x348535edU); + R_SCE_func314(136+32); + R_SCE_func100(0x0282e010U, 0xaf6c444aU, 0xce5dfdc8U, 0x973108adU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6U); + R_SCE_func080(); + R_SCE_func100(0x5a2de7abU, 0x358ae496U, 0xe8681248U, 0xe641ba7bU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(172); + R_SCE_func100(0xaa0cd971U, 0x6f2b0338U, 0x56b40b8eU, 0xcb3e497dU); + R_SCE_func314(172+32); + R_SCE_func100(0x7fdf44c1U, 0x759c90c9U, 0x2b088811U, 0x79fa617fU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1U); + R_SCE_func080(); + R_SCE_func100(0x7574fb68U, 0xade5f513U, 0x46a83200U, 0xb32cac21U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(208); + R_SCE_func100(0x5fd23420U, 0x31d8cb19U, 0x253a683bU, 0x2e50909dU); + R_SCE_func314(208+32); + SCE->REG_ECH = 0x0000d260U; + R_SCE_func101(0xaf15ab61U, 0xd69547d4U, 0x1b1dfc32U, 0x1f03a066U); + } + SCE->REG_ECH = 0x01816e94U; + R_SCE_func101(0x359452aaU, 0x98453f58U, 0x1fd0e35dU, 0x137f3a69U); + } + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func100(0x8101ab22U, 0xcd7e8c3aU, 0x769521d6U, 0xfe12b1f9U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cU); + R_SCE_func080(); + R_SCE_func100(0x1184d29aU, 0xee27bc01U, 0x767b805fU, 0x243fa62aU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(136); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6U); + R_SCE_func080(); + R_SCE_func100(0xd5e8c1beU, 0x2acf111aU, 0x502f6a82U, 0x92bd2dcfU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000013U; + R_SCE_func320(172); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1U); + R_SCE_func080(); + R_SCE_func100(0x21739cdcU, 0x951190acU, 0x45685982U, 0xe86e44c2U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(208); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9U); + R_SCE_func080(); + R_SCE_func100(0xa0dfa6bbU, 0xc3707f6cU, 0x1d070527U, 0xa7a76986U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(408); + R_SCE_func100(0xe15f6095U, 0x5e7571fbU, 0xc056da74U, 0x4ce96450U); + R_SCE_func314(408+32); + R_SCE_func100(0xf8bed511U, 0x1fd12dacU, 0x049f4f8cU, 0xfaac7c32U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffU); + R_SCE_func080(); + R_SCE_func100(0x2613c29fU, 0x2f7124f8U, 0x58c80261U, 0x9e8fad30U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(444); + R_SCE_func100(0xe377d1adU, 0xf2cc2950U, 0x3e3f9828U, 0x8c99bba0U); + R_SCE_func314(444+32); + R_SCE_func100(0xcff395d4U, 0x3a143213U, 0x86331293U, 0xd9b29133U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eaU); + R_SCE_func080(); + R_SCE_func100(0x2b9a1733U, 0xabd070c3U, 0x02d6bdfdU, 0xfce33528U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(480); + R_SCE_func100(0x24e5bf06U, 0xba03c1efU, 0x92b67d68U, 0x5ddd0b41U); + R_SCE_func314(480+32); + R_SCE_func100(0xacf41896U, 0x49c475acU, 0xe8c0c3caU, 0x87c58bbaU); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000001c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9U); + R_SCE_func080(); + R_SCE_func100(0xdd218c06U, 0xfc98d24eU, 0xb309d670U, 0xa81a4505U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(616); + R_SCE_func100(0x99cb872bU, 0x1976524cU, 0x5a0fe391U, 0x647562c5U); + R_SCE_func314(616+32); + R_SCE_func100(0xb44723a9U, 0xaf5d6bf9U, 0xe5892cb2U, 0xfaee8697U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730U); + R_SCE_func080(); + R_SCE_func100(0xe67063b6U, 0xa02bc232U, 0xe36a9c0dU, 0x7c54ca07U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(544); + R_SCE_func100(0x07975b62U, 0xd726d261U, 0xdb1e7d62U, 0x5c2f39d8U); + R_SCE_func314(544+32); + R_SCE_func100(0x99557507U, 0x377308f8U, 0x3bef2dd5U, 0xebd6a27eU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123U); + R_SCE_func080(); + R_SCE_func100(0x490d95cdU, 0xac3d9a2fU, 0x67d4e72fU, 0x5aac6e67U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000023U; + R_SCE_func319(580); + R_SCE_func100(0x88f4a784U, 0x630c5a7aU, 0x26cbe993U, 0xf47e6630U); + R_SCE_func314(580+32); + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f6U; + R_SCE_func101(0xaa073ed7U, 0x47dc9a56U, 0xc4576573U, 0xa0389521U); + R_SCE_func318(); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00003bbeU; + SCE->REG_ECH = 0x00007c1dU; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_func325_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p00.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p00.c new file mode 100644 index 0000000000..a5cf492627 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p00.c @@ -0,0 +1,72 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_SoftwareResetSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; + SCE->REG_1D0H = 0x00000000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p00.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p07.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p07.c new file mode 100644 index 0000000000..24c01e1010 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p07.c @@ -0,0 +1,199 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000702U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0x63c21e1bU, 0x4aa3e3b6U, 0x6258b1a6U, 0xd32ccc23U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000007U); + R_SCE_func101(0x46dfba59U, 0x2d2be5f2U, 0x50aa8c6cU, 0x6f6ba28fU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000007U); + R_SCE_func101(0xe180c617U, 0x438e0551U, 0xc04f8fbfU, 0x10fde223U); + R_SCE_func044(); + R_SCE_func100(0xfbfb2470U, 0xcab8f8e6U, 0x3c6419faU, 0x28d25074U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + R_SCE_func100(0xb6e02eb1U, 0x7b6389a6U, 0x002bc8abU, 0x4866fe6eU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02e487b5U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x3a35fe91U, 0x29806944U, 0x69fd901bU, 0xd54ffe60U); + SCE->REG_104H = 0x00000352U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + R_SCE_func102(0x0b59c831U, 0xe48a65e8U, 0x87850d40U, 0xd9b5c1acU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p07_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p08.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p08.c new file mode 100644 index 0000000000..d3f32f3489 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p08.c @@ -0,0 +1,225 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000802U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0x2487ce5aU, 0x38d94622U, 0x0e2fa8bbU, 0xe25cb7eaU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000008U); + R_SCE_func101(0x941283a0U, 0xcbbb508cU, 0x2985163aU, 0x71e7670fU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000008U); + R_SCE_func101(0xa311e3b1U, 0xcbd4c1c2U, 0xbd415c35U, 0xe9e618f2U); + R_SCE_func044(); + R_SCE_func100(0xfecf26cbU, 0xf3b63500U, 0x687d5cc8U, 0xcb79510aU); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + R_SCE_func100(0x6ea1d680U, 0xad017341U, 0xde07b586U, 0x44b219afU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80080000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xb99ac13dU, 0xab83d1f9U, 0xf4f5b915U, 0x7984e8d9U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x242ce73fU, 0xfb6d3483U, 0x65ec8b5fU, 0x76d5f2daU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e487b7U; + SCE->REG_E0H = 0x81080000U; + SCE->REG_00H = 0x00002823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000352U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000002U); + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + OutData_KeyIndex[12] = SCE->REG_100H; + R_SCE_func102(0xc8370a5eU, 0x4d7f2021U, 0x7e18e458U, 0x2a141e4aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p08_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p20.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p20.c new file mode 100644 index 0000000000..8cbbff8ec1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p20.c @@ -0,0 +1,103 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002002U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0xc9a708a8U, 0xb46352d8U, 0x81824784U, 0x125978eaU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0xd831dbf5U, 0x23fc1f37U, 0x68dde70bU, 0x6a29b0a7U); + SCE->REG_04H = 0x00000213U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + R_SCE_func102(0x07e3c3daU, 0xbc12d510U, 0x3a8e90ebU, 0x98e872aeU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p20_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p21.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p21.c new file mode 100644 index 0000000000..bb0e4fa546 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p21.c @@ -0,0 +1,138 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Ghash(uint32_t *InData_HV, uint32_t *InData_IV, uint32_t *InData_Text, uint32_t *OutData_DataT, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002101U; + SCE->REG_108H = 0x00000000U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_74H = 0x00001000U; + SCE->REG_104H = 0x00000364U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_HV[0]; + SCE->REG_100H = InData_HV[1]; + SCE->REG_100H = InData_HV[2]; + SCE->REG_100H = InData_HV[3]; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000364U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_74H = 0x00000002U; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_104H = 0x00000000U; + R_SCE_func100(0xba14a103U, 0x34579837U, 0x8fa75c12U, 0x1ebbc4dfU); + SCE->REG_74H = 0x00000008U; + SCE->REG_04H = 0x00000513U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + R_SCE_func102(0xb68d229cU, 0xa85d289dU, 0x3002617bU, 0x62dfd530U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p21.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p26.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p26.c new file mode 100644 index 0000000000..7e0b4f1513 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p26.c @@ -0,0 +1,93 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_FwIntegrityCheckSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002601U; + SCE->REG_108H = 0x00000000U; + SCE->REG_84H = 0x00010002U; + SCE->REG_13CH = 0x00000F01U; + SCE->REG_84H = 0x00010003U; + SCE->REG_13CH = 0x00000F01U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000001f0U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00003ffeU; + SCE->REG_84H = 0x00010001U; + SCE->REG_13CH = 0x00000202U; + R_SCE_func102(0x3c69ba59U, 0x7226272cU, 0x2591c7b0U, 0x826e3d54U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p26_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29a.c new file mode 100644 index 0000000000..1092bd0f6a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29a.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000U; + R_SCE_func101(0xf56af1bcU, 0x0294681eU, 0xdfb4a12eU, 0x51673967U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p29a_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29f.c new file mode 100644 index 0000000000..8f0718fcdb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29f.c @@ -0,0 +1,230 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80020100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x0000007FU; + SCE->REG_ECH = 0x0000b5a0U; + SCE->REG_ECH = 0xFFFFFF00U; + SCE->REG_ECH = 0x0c0029a9U; + SCE->REG_ECH = 0x04a02988U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x5cd20f19U, 0x1499e8a4U, 0xc5208c32U, 0xe57b3b71U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x0ed1a01eU, 0x568f0530U, 0x48d59eb2U, 0xc15e066cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409U; + SCE->REG_ECH = 0x00036800U; + SCE->REG_ECH = 0x08008c00U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xe07a96f5U, 0x2fdabfdeU, 0xf7c83f52U, 0xe15502c9U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bffU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0U; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + R_SCE_func100(0x0b7805e3U, 0xe2f76512U, 0x1fad4b47U, 0x06f9d909U); + SCE->REG_A4H = 0x00000885U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00004813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + R_SCE_func101(0xfd0e247cU, 0x82acd4bcU, 0xf64b5c34U, 0x259008f3U); + } + SCE->REG_104H = 0x00000164U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xf104e050U, 0x049b910cU, 0xe2571d7bU, 0xe354f4c9U); + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x000087b5U; + SCE->REG_00H = 0x00001513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + R_SCE_func102(0x5477872fU, 0x7f4775c6U, 0x499a1171U, 0x0b93c42eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p29f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29i.c new file mode 100644 index 0000000000..7567a27704 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29i.c @@ -0,0 +1,399 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002902U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xe6bd48a9U, 0x35f890e1U, 0x0eb48ee0U, 0xd6e5b454U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x8166a6f8U, 0x7c5ae97bU, 0xa3ff2ad6U, 0x9674f973U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000029U); + R_SCE_func101(0x590a0a66U, 0x9d3c2152U, 0x84920a64U, 0x8ddb814dU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + R_SCE_func101(0xc15dbcc0U, 0x9766df32U, 0xc984dd51U, 0x37cea1b3U); + } + else + { + SCE->REG_ECH = 0x00003547U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000029U); + R_SCE_func101(0x9400b020U, 0x85587f68U, 0x07c9878bU, 0xe075fa2cU); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x2a46c04bU; + R_SCE_func101(0x29b849a3U, 0x982e5234U, 0x97964f42U, 0x5f7b3670U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000029U); + R_SCE_func101(0xc3783633U, 0x5e086612U, 0xd585c269U, 0x71f7aee8U); + R_SCE_func044(); + R_SCE_func100(0x208628f4U, 0xa98648dbU, 0x34926e8dU, 0xe158f78cU); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040080U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + R_SCE_func101(0x4466b958U, 0x39825a7bU, 0x3a476f4aU, 0x9d04060eU); + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00120000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x3800d80fU; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000feU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000029U); + R_SCE_func101(0x7936f504U, 0xacd107a6U, 0x80b56949U, 0x159bddc0U); + R_SCE_func059(); + R_SCE_func100(0x0c96ba44U, 0x48b9f981U, 0xb9c3faa1U, 0xf9bf7ed9U); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_E0H = 0x80040080U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x725f569bU, 0x71ee1fc9U, 0x24633732U, 0x387483e1U); + } + R_SCE_func100(0xd5e2a736U, 0xa07462eaU, 0x728a3e6eU, 0xd0293da4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb7ceeb14U, 0x98bd7231U, 0x9fc6dc6eU, 0x9ba86139U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00001000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p29i_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29t.c new file mode 100644 index 0000000000..f958b10206 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29t.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128GcmEncryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x00008734U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p29t_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29u.c new file mode 100644 index 0000000000..0485b5afde --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29u.c @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x3d760ddaU, 0xe5fe1c23U, 0xe075aa85U, 0xa12011d7U); + SCE->REG_00H = 0x80007100U; + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x000087b6U; + SCE->REG_C4H = 0x00000886U; + SCE->REG_04H = 0x0000c200U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + R_SCE_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x60b590cdU, 0xc0d1584cU, 0x05d2c79dU, 0xe410d8fcU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p29u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2a.c new file mode 100644 index 0000000000..06f8d7ef4c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2a.c @@ -0,0 +1,2311 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateRsa1024RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PrivKeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002a02U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0x8e8a0453U, 0xd1cb093fU, 0x42064020U, 0x378e2ee2U); + R_SCE_func103(); + R_SCE_func100(0x9e9f2684U, 0x464073e8U, 0x58437fc5U, 0x7b7b3506U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01080c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x00000a31U; + for(kLoop = 0; kLoop < MAX_CNT; kLoop = kLoop + 1) + { + SCE->REG_28H = 0x00bf0001U; + SCE->REG_00H = 0x00003043U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00002f57U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00030005U); + SCE->REG_100H = change_endian_long(0x0007000bU); + SCE->REG_100H = change_endian_long(0x000d0011U); + SCE->REG_100H = change_endian_long(0x00130017U); + SCE->REG_100H = change_endian_long(0x001d001fU); + SCE->REG_100H = change_endian_long(0x00250029U); + SCE->REG_100H = change_endian_long(0x002b002fU); + SCE->REG_100H = change_endian_long(0x003b003dU); + SCE->REG_100H = change_endian_long(0x00430047U); + SCE->REG_100H = change_endian_long(0x0049004fU); + SCE->REG_100H = change_endian_long(0x00530059U); + SCE->REG_100H = change_endian_long(0x00610065U); + SCE->REG_100H = change_endian_long(0x0067006bU); + SCE->REG_100H = change_endian_long(0x006d0071U); + SCE->REG_100H = change_endian_long(0x007f0083U); + SCE->REG_100H = change_endian_long(0x0089008bU); + SCE->REG_100H = change_endian_long(0x00950097U); + SCE->REG_100H = change_endian_long(0x009d00a3U); + SCE->REG_100H = change_endian_long(0x00a700adU); + SCE->REG_100H = change_endian_long(0x00b300b5U); + SCE->REG_100H = change_endian_long(0x00bf00c1U); + SCE->REG_100H = change_endian_long(0x00c500c7U); + SCE->REG_100H = change_endian_long(0x00d300dfU); + SCE->REG_100H = change_endian_long(0x00e300e5U); + SCE->REG_100H = change_endian_long(0x00e900efU); + SCE->REG_100H = change_endian_long(0x00f100fbU); + SCE->REG_100H = change_endian_long(0x01010107U); + SCE->REG_100H = change_endian_long(0x010d010fU); + SCE->REG_100H = change_endian_long(0x01150119U); + SCE->REG_100H = change_endian_long(0x011b0125U); + SCE->REG_100H = change_endian_long(0x01330137U); + SCE->REG_100H = change_endian_long(0x0139013dU); + SCE->REG_100H = change_endian_long(0x014b0151U); + SCE->REG_100H = change_endian_long(0x015b015dU); + SCE->REG_100H = change_endian_long(0x01610167U); + SCE->REG_100H = change_endian_long(0x016f0175U); + SCE->REG_100H = change_endian_long(0x017b017fU); + SCE->REG_100H = change_endian_long(0x0185018dU); + SCE->REG_100H = change_endian_long(0x01910199U); + SCE->REG_100H = change_endian_long(0x01a301a5U); + SCE->REG_100H = change_endian_long(0x01af01b1U); + SCE->REG_100H = change_endian_long(0x01b701bbU); + SCE->REG_100H = change_endian_long(0x01c101c9U); + SCE->REG_100H = change_endian_long(0x01cd01cfU); + SCE->REG_100H = change_endian_long(0x01d301dfU); + SCE->REG_100H = change_endian_long(0x01e701ebU); + SCE->REG_100H = change_endian_long(0x01f301f7U); + SCE->REG_100H = change_endian_long(0x01fd0000U); + SCE->REG_ECH = 0x000008c6U; + SCE->REG_00H = 0x00000343U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80b00006U; + SCE->REG_00H = 0x000083c3U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x008f0001U; + R_SCE_func100(0x1433fef4U, 0x2cf339cbU, 0xb5739cd6U, 0xa71aa798U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000d01fU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00003813U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + for(iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + R_SCE_func100(0xfddd44c0U, 0xf214e276U, 0xe065d848U, 0x016bcf71U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x1fb14dfbU, 0xd3fa36ccU, 0x075c75b3U, 0x88ace583U); + } + R_SCE_func100(0xfddd44c0U, 0xf214e276U, 0xe065d848U, 0x016bcf71U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000d060U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00003813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000011U; + SCE->REG_104H = 0x00000f57U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xB51EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB80EU); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x82ca9906U, 0xbad7f644U, 0xc0a71c64U, 0x1c75aa6aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x191d1724U, 0xe6e12466U, 0x6cc20458U, 0x9f120e20U); + continue; + } + else + { + R_SCE_func101(0x120c14a7U, 0xfec6001bU, 0x070aad6aU, 0x6b136edaU); + } + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x1cb278ceU, 0xb5d70f4aU, 0x942d6f2aU, 0xc276ae0fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xc1eafebfU, 0xd4c8fbe2U, 0xa094ff6aU, 0x5cfbd681U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x6b2ad09fU, 0xa9f08f24U, 0x2f5082aeU, 0x94409804U); + } + else + { + R_SCE_func101(0xe1f6c1c9U, 0x2d5578f9U, 0xbf04168cU, 0x1f38db9cU); + } + SCE->REG_2CH = 0x00000011U; + SCE->REG_104H = 0x00000357U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x10000000U); + SCE->REG_00H = 0x00003033U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00001591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xb8107bb4U, 0xa52a43a2U, 0x37f7c4dfU, 0x22f1812aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0xebbcb2a9U, 0xf25e5a02U, 0x6b27301bU, 0x58fcb35eU); + continue; + } + else + { + R_SCE_func101(0xacdada94U, 0xcf36c28eU, 0xc484c54dU, 0x4f4a53ecU); + } + } + else + { + R_SCE_func101(0x7337a0d4U, 0x8b1ecbc8U, 0x5fc40365U, 0xac9e1661U); + } + SCE->REG_ECH = 0x000008c6U; + SCE->REG_ECH = 0x0000094aU; + for(iLoop = 0; iLoop < 96; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x01003906U; + SCE->REG_ECH = 0x00002cc0U; + SCE->REG_ECH = 0x00002cc0U; + SCE->REG_E0H = 0x81010100U; + SCE->REG_00H = 0x0000303fU; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00004006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x8fc90b75U, 0x61959598U, 0x573c9ff0U, 0xbf691eeeU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000d140U; + R_SCE_func101(0x202a8956U, 0xed49578cU, 0xac0a870cU, 0xacf2acabU); + break; + } + else + { + R_SCE_func101(0x5cb7f3e6U, 0x0a6740e3U, 0x9c9da436U, 0x92971316U); + } + } + SCE->REG_ECH = 0x38008940U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x9dcc8b3bU, 0xc73dacf9U, 0x18a4419bU, 0xed552f7dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0xd2aed1fcU, 0xae3b1366U, 0x82859c63U, 0x3f42b7dbU); + continue; + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x0000303fU; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000057U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00010001U); + SCE->REG_24H = 0x00004006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x97229af8U, 0xb8b53dcfU, 0xb9e3dab1U, 0x4556bb88U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x9344a8caU, 0x6f51f83bU, 0x26833f9eU, 0x7c8fc0c8U); + } + else + { + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8002d008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000189U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xa8d2cdfbU, 0x54a08d6bU, 0x266d2b7eU, 0x07bd56adU); + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00004080U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000044d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x8bb501c7U, 0x2dd3f096U, 0x56064844U, 0x25eefa69U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0xbba919ebU, 0x69125496U, 0xd4ea8fa4U, 0x164e09b0U); + continue; + } + SCE->REG_24H = 0x000098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x8090000aU; + SCE->REG_00H = 0x00008343U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b560U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_B0H = 0x00000300U; + SCE->REG_A4H = 0x42e0873fU; + SCE->REG_00H = 0x00001343U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x400009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x126c5638U, 0xaccc23f3U, 0x65e51fefU, 0x9862a7e3U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_7CH = 0x00000021U; + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x1adc7911U, 0xbcb75392U, 0x3005fefbU, 0x005a2e39U); + } + else + { + SCE->REG_7CH = 0x00000041U; + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xf309540bU, 0xb6b4bc11U, 0x370ec592U, 0x80c0181aU); + } + R_SCE_func100(0xcc67ccdcU, 0x65217d42U, 0x697ba19aU, 0x80f9e19dU); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000929U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_ECH = 0x000000fcU; + SCE->REG_ECH = 0x00003906U; + SCE->REG_ECH = 0x00008d00U; + SCE->REG_ECH = 0xfffffffeU; + SCE->REG_ECH = 0x00003d06U; + SCE->REG_ECH = 0x00000908U; + for(iLoop = 0; iLoop < 32; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x000038e6U; + SCE->REG_ECH = 0x0000a8c0U; + SCE->REG_ECH = 0x00000004U; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x38008900U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x11816907U; + SCE->REG_ECH = 0x38008900U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x10002d20U; + SCE->REG_ECH = 0x000168e7U; + } + } + SCE->REG_ECH = 0x00003549U; + SCE->REG_ECH = 0x0000a540U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x0002694aU; + SCE->REG_E0H = 0x81010140U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037eaU; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_24H = 0x00000185U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x000033e0U; + R_SCE_func101(0xa0a6ce69U, 0xe2c2f3bbU, 0x1a46944dU, 0xcea254d4U); + } + SCE->REG_ECH = 0x00007c1fU; + SCE->REG_1CH = 0x00602000U; + R_SCE_func100(0x2f2359beU, 0xe1a26d66U, 0x7e1389ecU, 0x6a9ff022U); + SCE->REG_ECH = 0x00026d4aU; + SCE->REG_ECH = 0x00002949U; + SCE->REG_E0H = 0x81010140U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037eaU; + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_24H = 0x2000018dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x000033e0U; + R_SCE_func101(0x932fc629U, 0xdf9f760cU, 0x6ecb16dbU, 0x09de3471U); + } + SCE->REG_ECH = 0x00007c1fU; + SCE->REG_1CH = 0x00602000U; + R_SCE_func100(0xc0d0f9baU, 0x39157912U, 0xadf26f47U, 0x5afe6552U); + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000a52U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x81010160U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_2CH = 0x00000010U; + for(jLoop = 0; jLoop < 16; jLoop = jLoop + 4) + { + R_SCE_func100(0xe409cdd1U, 0x5a131af1U, 0x5ddb2d0aU, 0xa52421e3U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xdb401411U, 0xf7b937ecU, 0x2fa31df5U, 0x4280d03fU); + } + R_SCE_func100(0x66d8f568U, 0xc9ecf390U, 0xe3201514U, 0xfee819cfU); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000c40U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x587796faU, 0x98629af6U, 0xdf8e1a45U, 0x68e49257U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e40U; + R_SCE_func101(0x3460d862U, 0xd682b1ecU, 0x8edbe559U, 0x0b8d6029U); + } + else + { + R_SCE_func100(0x0f54f666U, 0xdd75031fU, 0x245d2a49U, 0x850e803dU); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x81010120U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0+1 + 0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037e9U; + for(jLoop = 0; jLoop < (int32_t)S_RAM[0+1]; jLoop = jLoop + 1) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x38b150f7U, 0x8c6f1bf8U, 0xab48616cU, 0xf93357e7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e40U; + R_SCE_func101(0x5cf9d035U, 0x3160e71aU, 0xce083098U, 0x2f481c14U); + break; + } + else + { + SCE->REG_24H = 0x00004c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xa6d02aefU, 0x112168a8U, 0xf8b5b941U, 0x8643ca61U); + } + } + SCE->REG_ECH = 0x38008a40U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x7fc75c5fU, 0x4737e1e7U, 0xe96f516eU, 0xd2b13102U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x74f134a0U, 0x3a1451eeU, 0x7521ebacU, 0x66fb8bf0U); + break; + } + else + { + R_SCE_func101(0x4a6789b3U, 0xb2c8a7d5U, 0xe4742987U, 0xb1030db8U); + } + } + } + SCE->REG_ECH = 0x38000a4bU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x4831f88cU, 0x08d6b986U, 0x755af025U, 0x0212f9afU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e20U; + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x0c260d11U, 0xf97459aaU, 0xdcd3bfd6U, 0x831f46cbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x727c1a6dU, 0x38f6dfdbU, 0x3987a270U, 0xfb1b2654U); + break; + } + else + { + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xcf4c0db8U, 0x9105b584U, 0x05986d0bU, 0xaae63411U); + } + } + else + { + R_SCE_func101(0x2cd0933bU, 0xfc92937bU, 0xa2966f6bU, 0x62f1c417U); + } + } + } + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x07edbb80U, 0xb9e1c250U, 0x7ff1d49eU, 0x3c0e75e4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x4a80b6f6U, 0xbfe449d7U, 0xe71a1c9bU, 0x501a3f6aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + R_SCE_func100(0xacddb3abU, 0xcb6e19bdU, 0x70327786U, 0xd212fc7cU); + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x00010001U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x800019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_D0H = 0x00000700U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_04H = 0x00000282U; + for (iLoop = 0; iLoop < 32; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0xbb71974aU, 0xb2f44f59U, 0x11e6b79dU, 0x6f127640U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + SCE->REG_28H = 0x008f0001U; + SCE->REG_24H = 0x0000b0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + while(1) + { + SCE->REG_24H = 0x00008006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x09bbbd69U, 0x6a1b76d0U, 0x9d94f140U, 0x7824ca3bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x869d9db2U, 0xe09ca568U, 0x247c73cfU, 0xc1cc027fU); + break; + } + else + { + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x19a5b6a7U, 0x4dce3358U, 0x510ea254U, 0x25ecdb85U); + } + } + SCE->REG_24H = 0x000094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000c002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000980aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_00H = 0x0000307fU; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000057U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00010001U); + SCE->REG_2CH = 0x00000002U; + SCE->REG_24H = 0x0000c002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x800100c0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00010001U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + while(1) + { + R_SCE_func100(0xe30a6de5U, 0xd295745aU, 0x086d5e87U, 0x50b7e665U); + R_SCE_func103(); + R_SCE_func100(0x46f21f4dU, 0x24c39c94U, 0x3df7d493U, 0xde50364fU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01090c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x80a0000aU; + SCE->REG_00H = 0x00008383U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x28276a7fU, 0x69f1ba01U, 0x61a5c8ccU, 0xa8c75465U); + SCE->REG_D0H = 0x00000700U; + SCE->REG_C4H = 0x42e097bfU; + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000282U; + for (iLoop=36; iLoop<68; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x71243e05U, 0x96a046c3U, 0x111a98c0U, 0xd1d2e5f3U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400019cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + SCE->REG_28H = 0x008f0001U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_00H = 0x0000301fU; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x810100c0U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000301fU; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81010100U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00003506U; + SCE->REG_E0H = 0x800100c0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x0000002cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x380088c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xb4239b04U, 0xe736bd41U, 0x98796f5bU, 0x63bac957U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x008f0001U; + SCE->REG_104H = 0x00001f61U; + SCE->REG_B0H = 0x00000700U; + SCE->REG_A4H = 0x42f087bfU; + SCE->REG_00H = 0x00003143U; + SCE->REG_2CH = 0x00000015U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003143U; + SCE->REG_2CH = 0x00000014U; + for (iLoop = 16; iLoop < 32; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x021dd55cU, 0x16737918U, 0xd922c7fbU, 0x94d15244U); + break; + } + else + { + SCE->REG_28H = 0x008f0001U; + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x00003043U; + SCE->REG_2CH = 0x00000018U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x0000890eU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00001f62U; + SCE->REG_D0H = 0x00000700U; + SCE->REG_C4H = 0x42f097bfU; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + for (iLoop=36; iLoop<68; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001de1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x81a0000aU; + SCE->REG_00H = 0x00003883U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x1ed50a3bU, 0x9b006326U, 0x73edec73U, 0x2d374c63U); + } + } + SCE->REG_ECH = 0x00007c06U; + SCE->REG_1CH = 0x00602000U; + SCE->REG_A4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x24362cbdU, 0x55cbb20dU, 0x7919cebaU, 0x041626e5U); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000b8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000002U; + SCE->REG_24H = 0x00007b0aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000ccd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000002aU); + R_SCE_func101(0xd301fb40U, 0x6120eaedU, 0x9b62d844U, 0xd4d58e73U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000aU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000002aU); + R_SCE_func101(0x365ee21cU, 0x4c46d86dU, 0xdc3e3a2cU, 0x5e0eba39U); + R_SCE_func044(); + R_SCE_func100(0x18cbd98cU, 0x8a96dfe0U, 0x1cfdc247U, 0xf4f14b46U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[0] = SCE->REG_100H; + R_SCE_func100(0xb88ce30eU, 0x29fb036bU, 0x4727e574U, 0xffeaa827U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x02e08887U; + SCE->REG_04H = 0x00000282U; + for(iLoop=0; iLoop<32; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd4b01345U, 0xe25c1161U, 0xb3735364U, 0x73010503U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e08884U; + SCE->REG_E0H = 0x810101c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[33] = SCE->REG_100H; + OutData_PubKeyIndex[34] = SCE->REG_100H; + OutData_PubKeyIndex[35] = SCE->REG_100H; + OutData_PubKeyIndex[36] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + R_SCE_func100(0x3ae43d29U, 0x90843fa5U, 0xf444d9a6U, 0x8c6906beU); + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x00004404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000282U; + for(iLoop=36; iLoop<68; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xcf5346b4U, 0xd0d55adbU, 0xd1d277a9U, 0x0bb315a3U); + SCE->REG_104H = 0x00000352U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000008U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[69] = SCE->REG_100H; + OutData_PubKeyIndex[70] = SCE->REG_100H; + OutData_PubKeyIndex[71] = SCE->REG_100H; + OutData_PubKeyIndex[72] = SCE->REG_100H; + R_SCE_func100(0x1e0fb4eeU, 0x1ed5e83eU, 0x60466a1fU, 0xb0ab6ef9U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000020U); + R_SCE_func101(0x107adf4eU, 0xb30f3f24U, 0x4b60a785U, 0x6d5e524cU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000bU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000020U); + R_SCE_func101(0x14c0d8aaU, 0x49480269U, 0x3bb34ed7U, 0x39e214f4U); + R_SCE_func044(); + R_SCE_func100(0x75a8467eU, 0x8aede686U, 0xafed8f40U, 0x0f2fe649U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[0] = SCE->REG_100H; + R_SCE_func100(0x75ce7ca2U, 0x6fb6f1e9U, 0xe15bc7e9U, 0xd3bcab49U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000282U; + for(iLoop=0; iLoop<32; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x679a4970U, 0x6e30195eU, 0xe6a51b69U, 0xcabf0b1bU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000282U; + for(iLoop=32; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd7530eaeU, 0xd19e0258U, 0xc1ae9698U, 0xf04ceff7U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000282U; + for(iLoop=64; iLoop<96; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xb0b3fb65U, 0xae12bdccU, 0x5ebda80cU, 0xb916ba3bU); + SCE->REG_104H = 0x00000352U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000018U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[97] = SCE->REG_100H; + OutData_PrivKeyIndex[98] = SCE->REG_100H; + OutData_PrivKeyIndex[99] = SCE->REG_100H; + OutData_PrivKeyIndex[100] = SCE->REG_100H; + R_SCE_func102(0xe14d37b0U, 0x5289ac41U, 0xa41d194aU, 0xc3f7767aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p2a_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2b.c new file mode 100644 index 0000000000..9303e48ebf --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2b.c @@ -0,0 +1,2299 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PrivKeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002b02U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0xa5b6dcb3U, 0xed6ad1f7U, 0x249f777dU, 0x4201651aU); + R_SCE_func103(); + R_SCE_func100(0x8db9affaU, 0x8d66f896U, 0x969ffd93U, 0x10a2bdedU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01080c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x00000a31U; + for(kLoop = 0; kLoop < MAX_CNT; kLoop = kLoop + 1) + { + SCE->REG_28H = 0x00bf0001U; + SCE->REG_00H = 0x00003043U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00002f57U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00030005U); + SCE->REG_100H = change_endian_long(0x0007000bU); + SCE->REG_100H = change_endian_long(0x000d0011U); + SCE->REG_100H = change_endian_long(0x00130017U); + SCE->REG_100H = change_endian_long(0x001d001fU); + SCE->REG_100H = change_endian_long(0x00250029U); + SCE->REG_100H = change_endian_long(0x002b002fU); + SCE->REG_100H = change_endian_long(0x003b003dU); + SCE->REG_100H = change_endian_long(0x00430047U); + SCE->REG_100H = change_endian_long(0x0049004fU); + SCE->REG_100H = change_endian_long(0x00530059U); + SCE->REG_100H = change_endian_long(0x00610065U); + SCE->REG_100H = change_endian_long(0x0067006bU); + SCE->REG_100H = change_endian_long(0x006d0071U); + SCE->REG_100H = change_endian_long(0x007f0083U); + SCE->REG_100H = change_endian_long(0x0089008bU); + SCE->REG_100H = change_endian_long(0x00950097U); + SCE->REG_100H = change_endian_long(0x009d00a3U); + SCE->REG_100H = change_endian_long(0x00a700adU); + SCE->REG_100H = change_endian_long(0x00b300b5U); + SCE->REG_100H = change_endian_long(0x00bf00c1U); + SCE->REG_100H = change_endian_long(0x00c500c7U); + SCE->REG_100H = change_endian_long(0x00d300dfU); + SCE->REG_100H = change_endian_long(0x00e300e5U); + SCE->REG_100H = change_endian_long(0x00e900efU); + SCE->REG_100H = change_endian_long(0x00f100fbU); + SCE->REG_100H = change_endian_long(0x01010107U); + SCE->REG_100H = change_endian_long(0x010d010fU); + SCE->REG_100H = change_endian_long(0x01150119U); + SCE->REG_100H = change_endian_long(0x011b0125U); + SCE->REG_100H = change_endian_long(0x01330137U); + SCE->REG_100H = change_endian_long(0x0139013dU); + SCE->REG_100H = change_endian_long(0x014b0151U); + SCE->REG_100H = change_endian_long(0x015b015dU); + SCE->REG_100H = change_endian_long(0x01610167U); + SCE->REG_100H = change_endian_long(0x016f0175U); + SCE->REG_100H = change_endian_long(0x017b017fU); + SCE->REG_100H = change_endian_long(0x0185018dU); + SCE->REG_100H = change_endian_long(0x01910199U); + SCE->REG_100H = change_endian_long(0x01a301a5U); + SCE->REG_100H = change_endian_long(0x01af01b1U); + SCE->REG_100H = change_endian_long(0x01b701bbU); + SCE->REG_100H = change_endian_long(0x01c101c9U); + SCE->REG_100H = change_endian_long(0x01cd01cfU); + SCE->REG_100H = change_endian_long(0x01d301dfU); + SCE->REG_100H = change_endian_long(0x01e701ebU); + SCE->REG_100H = change_endian_long(0x01f301f7U); + SCE->REG_100H = change_endian_long(0x01fd0000U); + SCE->REG_ECH = 0x000008c6U; + SCE->REG_00H = 0x00000343U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80b00006U; + SCE->REG_00H = 0x000083c3U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x009f0001U; + R_SCE_func100(0x92442479U, 0xb6bbc6ecU, 0xb64748ceU, 0x8d1bfc0aU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000d01fU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00003813U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + for(iLoop = 0; iLoop < 24; iLoop = iLoop + 4) + { + R_SCE_func100(0xdc0d5af6U, 0xbd12c604U, 0xc6a01bddU, 0xe46a6d37U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x1c3ebb0aU, 0xb9a23b76U, 0x0270bcd9U, 0x1de14b5eU); + } + R_SCE_func100(0xdc0d5af6U, 0xbd12c604U, 0xc6a01bddU, 0xe46a6d37U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000d060U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00003813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000011U; + SCE->REG_104H = 0x00001f57U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xB51EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB851U); + SCE->REG_100H = change_endian_long(0xEB851EB8U); + SCE->REG_100H = change_endian_long(0x51EB851EU); + SCE->REG_100H = change_endian_long(0xB851EB85U); + SCE->REG_100H = change_endian_long(0x1EB851EBU); + SCE->REG_100H = change_endian_long(0x851EB851U); + SCE->REG_100H = change_endian_long(0xEB851B5CU); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x5ad8cda7U, 0x62048bc4U, 0x86a5759eU, 0xaea4ff60U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x6676f283U, 0x9ba9080aU, 0xbdd78178U, 0xe0903ba9U); + continue; + } + else + { + R_SCE_func101(0x65317c53U, 0xbc70d6c2U, 0x5441d8e3U, 0xb945c2d3U); + } + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x84630910U, 0x62797a2fU, 0x8e56b500U, 0x1eda6d62U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x44e7eb40U, 0x6768a961U, 0xd7144ab5U, 0x170f220eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x10156e72U, 0x8cc9c88cU, 0xd9d7e887U, 0xe5e7d5f9U); + } + else + { + R_SCE_func101(0x303fb30aU, 0x6cfba06dU, 0x6620c812U, 0x59960c0fU); + } + SCE->REG_2CH = 0x00000011U; + SCE->REG_104H = 0x00000357U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x10000000U); + SCE->REG_00H = 0x00003073U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00001591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xa1104f56U, 0x294ae338U, 0xcebacfc2U, 0x3ab40673U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x177827aeU, 0x8619839cU, 0x6b9fe109U, 0xdf2abd62U); + continue; + } + else + { + R_SCE_func101(0xd659d2f2U, 0x055f7d3eU, 0xc9e402c3U, 0xa1899eaaU); + } + } + else + { + R_SCE_func101(0x7d644ce1U, 0xef19c703U, 0xab47e11fU, 0x0acd12c5U); + } + SCE->REG_ECH = 0x000008c6U; + SCE->REG_ECH = 0x0000094aU; + for(iLoop = 0; iLoop < 96; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x01003906U; + SCE->REG_ECH = 0x00002cc0U; + SCE->REG_ECH = 0x00002cc0U; + SCE->REG_E0H = 0x81010100U; + SCE->REG_00H = 0x0000307fU; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00004006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xe710891fU, 0xc42b9f48U, 0xb7d9dc7bU, 0x5f101fbbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000d140U; + R_SCE_func101(0x2af0a95dU, 0x4988a3b9U, 0x167570e5U, 0x8445c739U); + break; + } + else + { + R_SCE_func101(0x695f9debU, 0x1226bf6eU, 0xec5af709U, 0x95c8c661U); + } + } + SCE->REG_ECH = 0x38008940U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xb4500ab0U, 0x5d9e286cU, 0x13f71830U, 0xf4dd053eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x0f9d849dU, 0x12ff3971U, 0x8638b124U, 0xf25f9d13U); + continue; + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x0000307fU; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000057U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00010001U); + SCE->REG_24H = 0x00004006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xce8db60cU, 0x150bed3dU, 0x443a1514U, 0x136faa52U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x8f77518eU, 0xc53878f6U, 0x02979a45U, 0x1f480ae0U); + } + else + { + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000189U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xa6d36ce0U, 0x0ccf1c75U, 0x9d058d00U, 0xa0dc7698U); + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00004080U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000044d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x42765fc8U, 0xf8956ad1U, 0xb31a8bb0U, 0x4e7a849cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0xaa5a6a8bU, 0x8b5adf21U, 0x0dd909bbU, 0x80450c86U); + continue; + } + SCE->REG_24H = 0x000098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x80a0000aU; + SCE->REG_00H = 0x00008383U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b560U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_B0H = 0x00000700U; + SCE->REG_A4H = 0x42e0873fU; + SCE->REG_00H = 0x00001383U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x400009cdU; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xd074aa3aU, 0x87e6862cU, 0x282a6f5eU, 0xf151c1dfU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_7CH = 0x00000021U; + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x1eff8031U, 0x640f93a1U, 0xd6ec3790U, 0x30429447U); + } + else + { + SCE->REG_7CH = 0x00000041U; + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xad46038bU, 0x03072792U, 0x9fdb5c00U, 0x4016ab53U); + } + R_SCE_func100(0x779dcabcU, 0x62898055U, 0x314a9e98U, 0xe914e2b1U); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000929U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_ECH = 0x000000fcU; + SCE->REG_ECH = 0x00003906U; + SCE->REG_ECH = 0x00008d00U; + SCE->REG_ECH = 0xfffffffeU; + SCE->REG_ECH = 0x00003d06U; + SCE->REG_ECH = 0x00000908U; + for(iLoop = 0; iLoop < 32; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x000038e6U; + SCE->REG_ECH = 0x0000a8c0U; + SCE->REG_ECH = 0x00000004U; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x38008900U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x11816907U; + SCE->REG_ECH = 0x38008900U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x10002d20U; + SCE->REG_ECH = 0x000168e7U; + } + } + SCE->REG_ECH = 0x00003549U; + SCE->REG_ECH = 0x0000a540U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x0002694aU; + SCE->REG_E0H = 0x81010140U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037eaU; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_24H = 0x00000185U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x000033e0U; + R_SCE_func101(0x49280d66U, 0x305c394cU, 0x1b479599U, 0xc67af230U); + } + SCE->REG_ECH = 0x00007c1fU; + SCE->REG_1CH = 0x00602000U; + R_SCE_func100(0x37bbd1cbU, 0xf9ea6a6cU, 0x0bfe71b0U, 0x2d18f113U); + SCE->REG_ECH = 0x00026d4aU; + SCE->REG_ECH = 0x00002949U; + SCE->REG_E0H = 0x81010140U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037eaU; + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_24H = 0x2000018dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x000033e0U; + R_SCE_func101(0xa5eef22dU, 0xd8b34e6fU, 0xf293ed5dU, 0x27367962U); + } + SCE->REG_ECH = 0x00007c1fU; + SCE->REG_1CH = 0x00602000U; + R_SCE_func100(0x71eef8b7U, 0x013dee0aU, 0x8aa23bfeU, 0xb7f89b02U); + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000a52U; + SCE->REG_24H = 0x00006404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x81010160U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_2CH = 0x00000010U; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 4) + { + R_SCE_func100(0x45703240U, 0x6434c517U, 0xd9732713U, 0x5c487d86U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xb4095821U, 0xc571b2dcU, 0x82013581U, 0x98b2ee91U); + } + R_SCE_func100(0x8721c59aU, 0x1fba425dU, 0xcd6812f6U, 0x4a92f6f7U); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000c40U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x50b07a2dU, 0xa919932dU, 0x8d61da2aU, 0x2527551cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e40U; + R_SCE_func101(0xd2aa5059U, 0x69986543U, 0xe9521bcbU, 0xf36550d9U); + } + else + { + R_SCE_func100(0x7dab1164U, 0x0d1f6b6eU, 0x555bfb9aU, 0xfc3a2a6bU); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x81010120U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0+1 + 0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037e9U; + for(jLoop = 0; jLoop < (int32_t)S_RAM[0+1]; jLoop = jLoop + 1) + { + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x8f2574f0U, 0x6a6aec33U, 0xd1a35a1fU, 0x0bde026eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e40U; + R_SCE_func101(0xcb24a47dU, 0x5b98e3f7U, 0xfc0bfcb3U, 0x8c5c1dcdU); + break; + } + else + { + SCE->REG_24H = 0x00004c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xa61e2c9aU, 0x4b749da4U, 0x27d4f0f7U, 0x5cf35267U); + } + } + SCE->REG_ECH = 0x38008a40U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x1637e74aU, 0x922ba8a8U, 0x6be1187eU, 0x1dc2f8edU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x1b879c9dU, 0x6c0782e5U, 0xde66656dU, 0x702c359aU); + break; + } + else + { + R_SCE_func101(0xe75699d4U, 0x4082d188U, 0xfcc85dccU, 0x6eaf82b5U); + } + } + } + SCE->REG_ECH = 0x38000a4bU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x52109273U, 0x7569c715U, 0x565a942eU, 0xc0242ca8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e20U; + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x72f62bb0U, 0xca307657U, 0xe2890891U, 0x2fe84ce6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x83ecc02fU, 0x1e7c7752U, 0x685d01d0U, 0x90cc3456U); + break; + } + else + { + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x545eb67bU, 0x0d2cc963U, 0xea3a2fdbU, 0x80b913c5U); + } + } + else + { + R_SCE_func101(0xe073e65cU, 0xc9ee69a6U, 0x8947c379U, 0xbafefb7eU); + } + } + } + SCE->REG_ECH = 0x38008a20U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x18e47f34U, 0x1884fb0aU, 0xa4ca32efU, 0xf9d0ab66U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x51de014dU, 0x33e1ad9aU, 0xffec29ffU, 0x95776928U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + R_SCE_func100(0xd9e2b8e7U, 0xe950901cU, 0xe0486221U, 0xbc3e860fU); + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x00010001U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_04H = 0x00000202U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x1516b75eU, 0x0e239e32U, 0x6a166d1bU, 0xa6c89764U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + while(1) + { + SCE->REG_24H = 0x00008006U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xc649a206U, 0xa18db666U, 0xaa98a57fU, 0xc2111e03U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func101(0x6029ecd9U, 0x9a4a1d8fU, 0x4c38f31fU, 0x7101fbc3U); + break; + } + else + { + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000d0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0x616d9225U, 0x75bbe7f3U, 0x135c9e2aU, 0x5b8ef0d6U); + } + } + SCE->REG_24H = 0x000094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000c002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000U; + SCE->REG_24H = 0x0000b80aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_00H = 0x000030ffU; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000057U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00010001U); + SCE->REG_2CH = 0x00000002U; + SCE->REG_24H = 0x0000c002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_E0H = 0x800100c0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00010001U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + while(1) + { + R_SCE_func100(0x31a8a36fU, 0xb31b2ee3U, 0xbcf5a0d7U, 0x14fbe491U); + R_SCE_func103(); + R_SCE_func100(0xca8db3d0U, 0xa00b6625U, 0xa2c83245U, 0x4f4f4c5cU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01090c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x80c0000aU; + SCE->REG_00H = 0x00018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x3746a344U, 0x9f44ba6cU, 0x35bb51f4U, 0x4c0d1991U); + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42e097bfU; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000202U; + for (iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x27be7167U, 0x17c8cdfdU, 0xf01afed2U, 0x3301a3d5U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400019cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_00H = 0x0000301fU; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x810100c0U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000301fU; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81010100U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000000U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00003506U; + SCE->REG_E0H = 0x800100c0U; + SCE->REG_00H = 0x0000031fU; + SCE->REG_2CH = 0x0000002cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x380088c0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x3654ea74U, 0x1fd1cc3fU, 0xfc04a87dU, 0xcc28b43aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00003f61U; + SCE->REG_B0H = 0x00000f00U; + SCE->REG_A4H = 0x42f087bfU; + SCE->REG_00H = 0x00013103U; + SCE->REG_2CH = 0x00000014U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xa8e7d727U, 0xfdc6a8daU, 0x844ee6f2U, 0x00b0b96cU); + break; + } + else + { + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x00003083U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x0000880eU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42f097bfU; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + for (iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x81c0000aU; + SCE->REG_00H = 0x00013803U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xaa5e6f19U, 0x8e2e22e4U, 0x947483bdU, 0x8ad8139bU); + } + } + SCE->REG_ECH = 0x00007c06U; + SCE->REG_1CH = 0x00602000U; + SCE->REG_A4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xb833bda0U, 0x5c4c9605U, 0x3c9248f5U, 0xfa28bae6U); + SCE->REG_28H = 0x00bf0001U; + R_SCE_func103(); + R_SCE_func100(0xe6d75747U, 0x7ad48da5U, 0xca36e100U, 0x0818a927U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01090c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x497f8681U, 0x673c28fcU, 0x1a470b9eU, 0xd5549ffbU); + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42e097bfU; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + SCE->REG_04H = 0x00000202U; + for (iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x8846e6ffU, 0x3a8401bfU, 0x6e286aa1U, 0x079872f4U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400019cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0xf4c59366U, 0xd36da880U, 0xbc610906U, 0xc4ee03deU); + SCE->REG_28H = 0x009f0001U; + SCE->REG_24H = 0x0000b8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000002U; + SCE->REG_24H = 0x00007b0aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0xfcbf0001U; + SCE->REG_24H = 0x0000c8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000002bU); + R_SCE_func101(0x6ab98776U, 0x58e8a14bU, 0x78865269U, 0xc34ab9f1U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000002bU); + R_SCE_func101(0xf201f748U, 0x5c87c622U, 0xc5c0deb4U, 0x7e69236cU); + R_SCE_func044(); + R_SCE_func100(0xa8c17ffbU, 0x12ae4b7cU, 0x6f3471c5U, 0x0d2adfa0U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[0] = SCE->REG_100H; + R_SCE_func100(0x54202126U, 0x61df8c16U, 0xf766cceeU, 0xda3f5c49U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x02e08887U; + SCE->REG_04H = 0x00000202U; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x1bfce66dU, 0x873a200eU, 0x0ba3530fU, 0xbbf531acU); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e08884U; + SCE->REG_E0H = 0x810101c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[65] = SCE->REG_100H; + OutData_PubKeyIndex[66] = SCE->REG_100H; + OutData_PubKeyIndex[67] = SCE->REG_100H; + OutData_PubKeyIndex[68] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + R_SCE_func100(0x62caf56aU, 0xaea4a5c2U, 0xbffb0b7fU, 0xaea7002dU); + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x00004404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000202U; + for(iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x3131149aU, 0x11bf462fU, 0x71b885dcU, 0x6a0fdd2eU); + SCE->REG_104H = 0x00000352U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000010U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[133] = SCE->REG_100H; + OutData_PubKeyIndex[134] = SCE->REG_100H; + OutData_PubKeyIndex[135] = SCE->REG_100H; + OutData_PubKeyIndex[136] = SCE->REG_100H; + R_SCE_func100(0xff3c2dbeU, 0x060f91ecU, 0xcc73f6daU, 0xb7be39d1U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000fdU); + R_SCE_func101(0xbb004206U, 0x83367280U, 0xcf594deaU, 0xf68a314eU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000dU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000fdU); + R_SCE_func101(0x990e90aeU, 0xc3053983U, 0x557ddf50U, 0x8973f306U); + R_SCE_func044(); + R_SCE_func100(0x722ff02bU, 0xf75d5865U, 0xfc29d717U, 0xea177bf8U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[0] = SCE->REG_100H; + R_SCE_func100(0xb0850381U, 0xc4dd3713U, 0x38ad8efaU, 0x1a75c26dU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000202U; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xcdb6eacfU, 0x47e24249U, 0x3cfaa2a2U, 0xcc672c7eU); + SCE->REG_00H = 0x00012103U; + SCE->REG_104H = 0x00000031U; + SCE->REG_B0H = 0x00000f00U; + SCE->REG_A4H = 0x42f097bfU; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000202U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[68]; + SCE->REG_100H = S_HEAP[69]; + SCE->REG_100H = S_HEAP[70]; + SCE->REG_100H = S_HEAP[71]; + for (iLoop = 64; iLoop < 124 ; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+8 + 0]; + SCE->REG_100H = S_HEAP[iLoop+8 + 1]; + SCE->REG_100H = S_HEAP[iLoop+8 + 2]; + SCE->REG_100H = S_HEAP[iLoop+8 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + SCE->REG_A4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[132]; + SCE->REG_100H = S_HEAP[133]; + SCE->REG_100H = S_HEAP[134]; + SCE->REG_100H = S_HEAP[135]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x23908e74U, 0x00fdbcecU, 0xf291c22eU, 0x4c0cc4fdU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000202U; + for(iLoop=128; iLoop<192; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd96db8efU, 0x196981a3U, 0xe8c6e4a5U, 0xa21b6ba1U); + SCE->REG_104H = 0x00000352U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000030U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[193] = SCE->REG_100H; + OutData_PrivKeyIndex[194] = SCE->REG_100H; + OutData_PrivKeyIndex[195] = SCE->REG_100H; + OutData_PrivKeyIndex[196] = SCE->REG_100H; + R_SCE_func102(0xf7c434feU, 0xc787e528U, 0xb90a4a06U, 0xd4ff2cd5U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p2b_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32a.c new file mode 100644 index 0000000000..29f155f7e9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32a.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000U; + R_SCE_func101(0xade14948U, 0x4648cb43U, 0x299ec858U, 0x21d909f4U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p32a_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32f.c new file mode 100644 index 0000000000..ef26b0aef4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32f.c @@ -0,0 +1,299 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80020100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x0000007FU; + SCE->REG_ECH = 0x0000b5a0U; + SCE->REG_ECH = 0xFFFFFF00U; + SCE->REG_ECH = 0x0c0029a9U; + SCE->REG_ECH = 0x04a02988U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_ECH = 0x38008940U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x34202beaU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x55abbdadU, 0xadf622c7U, 0x43c39314U, 0x830084e5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x6e718cefU, 0xb456b827U, 0x7143fb47U, 0xbd7173e7U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409U; + SCE->REG_ECH = 0x00036800U; + SCE->REG_ECH = 0x08008c00U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xecec9d3bU, 0xcd5afbe3U, 0xb000fa42U, 0xba315de1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00000885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_D0H = 0x00000020U; + SCE->REG_C4H = 0x000087b5U; + SCE->REG_00H = 0x00007113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bffU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0U; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + R_SCE_func100(0x90023d8fU, 0xc21859edU, 0xf7d1da75U, 0x8f701a14U); + SCE->REG_C4H = 0x00000885U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000213U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + R_SCE_func101(0x9b988dc6U, 0xf5a3968cU, 0x395d0f05U, 0xecefbf7fU); + } + SCE->REG_104H = 0x00000164U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_C4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x00000020U; + SCE->REG_C4H = 0x000087b5U; + SCE->REG_00H = 0x00002513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bffU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beaU; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + SCE->REG_104H = 0x00000362U; + SCE->REG_C4H = 0x00050805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x00000000U; + R_SCE_func100(0x663de4deU, 0x9ef1352eU, 0xc52dda0dU, 0x0a945c93U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x534133d9U, 0x5ca82ea6U, 0x6b5803b9U, 0x5b3ca8e9U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + R_SCE_func102(0x08d6d5f4U, 0xd7549839U, 0xeb0605e4U, 0x9ad61126U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p32f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32i.c new file mode 100644 index 0000000000..89c803857a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32i.c @@ -0,0 +1,514 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00003202U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x339b3c0aU, 0x88130dd8U, 0x8d0966b7U, 0x221ff0cbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xe465019dU, 0xf12361acU, 0xae3836e9U, 0xcd341658U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000032U); + R_SCE_func101(0xb65e47f1U, 0x191b6741U, 0x2052e71eU, 0x90d1e08fU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + R_SCE_func101(0x9f3b3c3aU, 0xbddeae34U, 0xfdbf4874U, 0xc61a1508U); + } + else + { + SCE->REG_ECH = 0x00003547U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000032U); + R_SCE_func101(0x3d78c93aU, 0x8f52dd0fU, 0x060996cfU, 0x4c592513U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x2a46c04bU; + R_SCE_func101(0x5714dc0cU, 0x7a843bc7U, 0xacdf3500U, 0x3688019fU); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000032U); + R_SCE_func101(0xb0570d09U, 0x6b0c8020U, 0x49429399U, 0x9d0832c1U); + R_SCE_func044(); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040080U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + R_SCE_func101(0x1a7e2169U, 0xc66bbb3fU, 0x2d3c84f3U, 0xaec9e067U); + } + else + { + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x87cf69deU, 0x46c77794U, 0x414bedefU, 0x09d9de8cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00120000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x3800d80eU; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000feU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000032U); + R_SCE_func101(0xecf56b74U, 0x17c45c78U, 0xd1dd8126U, 0xfaa83147U); + R_SCE_func059(); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_E0H = 0x80040080U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x6c9606f4U, 0x90038562U, 0xd135e198U, 0xd7f7475bU); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000005U); + R_SCE_func101(0x4e6044daU, 0x1553ee83U, 0x9d8aabc1U, 0xe77ba651U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x01ad8717U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000005U); + R_SCE_func101(0x780fd8c4U, 0x8cd7551cU, 0x946dd44dU, 0xe22072b7U); + R_SCE_func044(); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_E0H = 0x80040080U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xc5486f55U, 0x401fcaa6U, 0x99876486U, 0x7e63b743U); + } + } + R_SCE_func100(0x0a9a5c59U, 0x1eb36824U, 0x8038cdebU, 0xc3b30a91U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x821c9497U, 0xd1f5ef0bU, 0x34c7816dU, 0x8698da62U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0xca6f7eceU, 0x1fec61eeU, 0x72e054acU, 0x7d7695d7U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_C4H = 0x00080805U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005213U; + SCE->REG_74H = 0x00001000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p32i_r4.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32t.c new file mode 100644 index 0000000000..9724d85bc1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32t.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128GcmDecryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x00000020U; + SCE->REG_C4H = 0x00008734U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p32t_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32u.c new file mode 100644 index 0000000000..bf3e0d6b4a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32u.c @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x815d574bU, 0x63126d08U, 0x86aa6659U, 0x3e1e1363U); + SCE->REG_00H = 0x80007100U; + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00000886U; + SCE->REG_D0H = 0x00000020U; + SCE->REG_C4H = 0x000087b6U; + SCE->REG_04H = 0x0000c200U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + R_SCE_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0xe7632fe5U, 0x87345a24U, 0xe0a0333bU, 0x610577cbU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p32u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34a.c new file mode 100644 index 0000000000..f766b330a1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34a.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000U; + R_SCE_func101(0x548bd578U, 0x8ce6077eU, 0x8d991096U, 0x1bae6855U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p34a_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34f.c new file mode 100644 index 0000000000..4aadf0bb39 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34f.c @@ -0,0 +1,230 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80020100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x0000007FU; + SCE->REG_ECH = 0x0000b5a0U; + SCE->REG_ECH = 0xFFFFFF00U; + SCE->REG_ECH = 0x0c0029a9U; + SCE->REG_ECH = 0x04a02988U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xdc98478bU, 0x02595abfU, 0xe4958f8dU, 0x1ba86102U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x67ca4c85U, 0x95ba32c4U, 0x0c0b361fU, 0x110f247eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409U; + SCE->REG_ECH = 0x00036800U; + SCE->REG_ECH = 0x08008c00U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xae1ce454U, 0x4b0f6398U, 0x3cd6becdU, 0x06c3c62bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bffU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0U; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + R_SCE_func100(0x15c4fba8U, 0xdb827724U, 0x01717229U, 0x75630c64U); + SCE->REG_A4H = 0x00000885U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00004813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + R_SCE_func101(0xa8d3b575U, 0xb4609ca7U, 0xf3b9e900U, 0x8aee245eU); + } + SCE->REG_104H = 0x00000164U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x7e37ce37U, 0xfb4a669dU, 0x98ead448U, 0x5c92fa4fU); + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x000087b5U; + SCE->REG_00H = 0x00001513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + R_SCE_func102(0x911918b6U, 0x31a6b8c1U, 0xa0a049a0U, 0xc0bc4653U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p34f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34i.c new file mode 100644 index 0000000000..3792f0b267 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34i.c @@ -0,0 +1,311 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00003402U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x540ea6fdU, 0x75f84078U, 0x836b6700U, 0x75f1a44cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x5a7da548U, 0xeb2fcad0U, 0xfd47104aU, 0xad45fc38U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xc6a28b52U, 0x76e44b66U, 0xf09eaae4U, 0xbd3e182fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000034U); + R_SCE_func101(0xd88a88a8U, 0xbe50d192U, 0xf2b71a06U, 0xe60167ecU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + R_SCE_func101(0xc9d76c67U, 0xd720c7c7U, 0xb3a4f9bcU, 0x2563c7c6U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000034U); + R_SCE_func101(0xd27305f9U, 0x1198c9e0U, 0x2fb8e616U, 0x78dc7d8fU); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x85d04999U; + R_SCE_func101(0x42948000U, 0xb4db3e6bU, 0x347c98faU, 0xa1f8649aU); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000034U); + R_SCE_func101(0xc430b631U, 0x33edde3eU, 0x476aa4bbU, 0xbcc0bdf1U); + R_SCE_func044(); + R_SCE_func100(0xfe5a6638U, 0xacef2a67U, 0x830f7828U, 0x86cf83a3U); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xc1f2817eU, 0xae2d07c9U, 0x6e096e65U, 0xd08ee453U); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x7699aca2U, 0x175d6228U, 0x124d9b44U, 0x6a079fc5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xbd671b62U, 0xdd5c7bb8U, 0xb8b0cc14U, 0xc27ca0c0U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040080U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00001000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p34i_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34t.c new file mode 100644 index 0000000000..2113361168 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34t.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256GcmEncryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x00000020U; + SCE->REG_A4H = 0x00008734U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p34t_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34u.c new file mode 100644 index 0000000000..3ff0fb0336 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34u.c @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x9641bbfeU, 0x4a18fb1fU, 0x51c92854U, 0xc5ba2a93U); + SCE->REG_00H = 0x80007100U; + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000020U; + SCE->REG_A4H = 0x000087b6U; + SCE->REG_C4H = 0x00000886U; + SCE->REG_04H = 0x0000c200U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + R_SCE_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x1abb2323U, 0xb0269093U, 0x6215a2ebU, 0x2da03e83U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p34u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36a.c new file mode 100644 index 0000000000..7c94f1a1b3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36a.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000U; + R_SCE_func101(0x97cadfacU, 0x4ef31143U, 0xc72a6568U, 0x19bf7c29U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p36a_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36f.c new file mode 100644 index 0000000000..d580e74b9b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36f.c @@ -0,0 +1,299 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80020100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x0000007FU; + SCE->REG_ECH = 0x0000b5a0U; + SCE->REG_ECH = 0xFFFFFF00U; + SCE->REG_ECH = 0x0c0029a9U; + SCE->REG_ECH = 0x04a02988U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_ECH = 0x38008940U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x34202beaU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xa724b128U, 0x8a1ae603U, 0xcf8e994bU, 0x8ad3c610U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xf7823209U, 0x55e27e6eU, 0x73acecc3U, 0x66f8daefU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409U; + SCE->REG_ECH = 0x00036800U; + SCE->REG_ECH = 0x08008c00U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xdda901a3U, 0xad536aadU, 0x2c7cb539U, 0x1bf544bdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00000885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_D0H = 0x40000020U; + SCE->REG_C4H = 0x000087b5U; + SCE->REG_00H = 0x00007113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bffU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0U; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + R_SCE_func100(0x88c47318U, 0xafa03b50U, 0xbdb95668U, 0x13e496f8U); + SCE->REG_C4H = 0x00000885U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000213U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + R_SCE_func101(0x55f20429U, 0x09cfd376U, 0x9062b637U, 0x3d96f6a6U); + } + SCE->REG_104H = 0x00000164U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_C4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x40000020U; + SCE->REG_C4H = 0x000087b5U; + SCE->REG_00H = 0x00002513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bffU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beaU; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + SCE->REG_104H = 0x00000362U; + SCE->REG_C4H = 0x00050805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x00000000U; + R_SCE_func100(0x12143f89U, 0x91f106dbU, 0x6fb0f7b0U, 0x0d54a352U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x403f5ca9U, 0xe5da4c7aU, 0x9f8adb35U, 0x35890f5cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + R_SCE_func102(0x314b28e3U, 0xe4034b3bU, 0xd055338cU, 0x0381d40aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p36f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36i.c new file mode 100644 index 0000000000..f6d939c791 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36i.c @@ -0,0 +1,320 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00003602U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xf721aa65U, 0x5d8787e6U, 0xa66b69c3U, 0xbf92942cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x7abe2877U, 0x2f23a3b2U, 0xdb0f69e9U, 0xcfdbaf28U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xa0f0c4deU, 0xdab200b7U, 0x5acbaf5dU, 0x716b8640U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000036U); + R_SCE_func101(0xaeaee44cU, 0x0352ab08U, 0x574f87e3U, 0x469a5827U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + R_SCE_func101(0x196bbddeU, 0x3a4abd2dU, 0xea140939U, 0x1d56ecfeU); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000036U); + R_SCE_func101(0x02ab7cd5U, 0x7e524484U, 0xd2d565cbU, 0x461b2544U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x85d04999U; + R_SCE_func101(0x4f3dcce6U, 0xb42d9a57U, 0xfe3b6f4fU, 0x72477687U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000036U); + R_SCE_func101(0x8e858f1dU, 0x4eabe477U, 0x4e7dff87U, 0x8b34b8f8U); + R_SCE_func044(); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_E0H = 0x80080000U; + SCE->REG_00H = 0x00008223U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xeebf1c66U, 0xbbfb2950U, 0x4c3b19a3U, 0x2e328634U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x212063b9U, 0x2fade8c4U, 0x6ee7d515U, 0x7de42d0aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0xfe3d92deU, 0xf9cf25fbU, 0x39866f77U, 0xf4f1c0b7U); + SCE->REG_E0H = 0x81080000U; + SCE->REG_C4H = 0x00080805U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xabf45396U, 0x938df4c4U, 0xb439eb17U, 0xc9b5c7a5U); + SCE->REG_C4H = 0x00090805U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040080U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00008a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005213U; + SCE->REG_74H = 0x00001000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p36i_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36t.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36t.c new file mode 100644 index 0000000000..a7a281cf2d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36t.c @@ -0,0 +1,86 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256GcmDecryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x00040805U; + SCE->REG_E0H = 0x81040080U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x00000020U; + SCE->REG_C4H = 0x00008734U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p36t_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36u.c new file mode 100644 index 0000000000..c6051fce3f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36u.c @@ -0,0 +1,121 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xeb8cf888U, 0xa09d1a93U, 0x2aae5e3fU, 0x8247988dU); + SCE->REG_00H = 0x80007100U; + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00000886U; + SCE->REG_D0H = 0x40000020U; + SCE->REG_C4H = 0x000087b6U; + SCE->REG_04H = 0x0000c200U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + R_SCE_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x6a7ce2f2U, 0xb90a3735U, 0x4fd72715U, 0x482727adU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p36u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p40.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p40.c new file mode 100644 index 0000000000..17e20a8bb3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p40.c @@ -0,0 +1,259 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_LoadHukSub(uint32_t *InData_LC) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004001U; + SCE->REG_108H = 0x00000000U; + R_SCE_func048(InData_LC); + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000009U; + SCE->REG_ECH = 0x34202801U; + SCE->REG_ECH = 0x20003401U; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00602000U; + if (InData_LC[0] == 0x00000000) + { + SCE->REG_1CH = 0x00b80000U; + R_SCE_func101(0x910462eeU, 0xc019489bU, 0x423f71caU, 0xd2f2c484U); + } + else if (InData_LC[0] == 0x00000001) + { + SCE->REG_1CH = 0x00b00000U; + R_SCE_func101(0x0757ac60U, 0xd2bf9036U, 0x6f9557efU, 0x97b40d75U); + } + else if (InData_LC[0] == 0x00000002) + { + SCE->REG_1CH = 0x00b10000U; + R_SCE_func101(0x248eecceU, 0x6a647475U, 0x4b2d3e05U, 0xcd67a1c0U); + } + else if (InData_LC[0] == 0x00000003) + { + SCE->REG_1CH = 0x00b20000U; + R_SCE_func101(0x69da3cd7U, 0xa5d27e49U, 0xedaaaca6U, 0x3b74f8e8U); + } + else if (InData_LC[0] == 0x00000004) + { + SCE->REG_1CH = 0x00b30000U; + R_SCE_func101(0xd3577449U, 0xa802a60dU, 0xacd705b0U, 0xde5d62cdU); + } + else if (InData_LC[0] == 0x00000005) + { + SCE->REG_1CH = 0x00b40000U; + R_SCE_func101(0x30538696U, 0xa8e7a5c8U, 0x6548cd7eU, 0xe4849bafU); + } + else if (InData_LC[0] == 0x00000006) + { + SCE->REG_1CH = 0x00b50000U; + R_SCE_func101(0x30239a5eU, 0xf543ab1dU, 0x9d7944e6U, 0xef8e76dbU); + } + else if (InData_LC[0] == 0x00000007) + { + SCE->REG_1CH = 0x00b60000U; + R_SCE_func101(0x13fc13ebU, 0x62a27527U, 0xcbaa64faU, 0x3f75ba45U); + } + else if (InData_LC[0] == 0x00000008) + { + SCE->REG_1CH = 0x00b70000U; + R_SCE_func101(0x3cc5aa3fU, 0xf5189eafU, 0x1dd14f5cU, 0xbce9f462U); + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func101(0x125e03f6U, 0x852ac185U, 0xf4527cb6U, 0x7995d726U); + } + R_SCE_func100(0xfa382636U, 0x2cc695f9U, 0x8103ad09U, 0x8874586cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xbd3f4ffbU, 0x6cf73347U, 0x34307717U, 0xcbda6163U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000040U); + R_SCE_func101(0x137090ecU, 0x06be17caU, 0xc7ba1504U, 0xe9018f7dU); + R_SCE_func040(); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b5U; + SCE->REG_E8H = 0x80000000U; + SCE->REG_00H = 0x00002613U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + SCE->REG_E8H = 0x80000004U; + SCE->REG_00H = 0x00002613U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x000001d0U; + SCE->REG_E0H = 0x80880001U; + SCE->REG_00H = 0x00008223U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x000001b0U; + SCE->REG_ECH = 0x00003c01U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + SCE->REG_E8H = 0x80000008U; + SCE->REG_00H = 0x00002613U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xf05b4952U, 0x6e695becU, 0x81e946b3U, 0x941f422eU); + SCE->REG_C4H = 0x20443a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x200c3e1cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0152db38U); + SCE->REG_C4H = 0x00440a0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x00000e9cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f7370eU); + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x000001c0U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_13CH = 0x00000211U; + R_SCE_func102(0xcc23e22eU, 0x1dccf1a2U, 0x0dd974e8U, 0xa1d0098dU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p40_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41f.c new file mode 100644 index 0000000000..068a91e0ce --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41f.c @@ -0,0 +1,283 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x77191c41U, 0x53d4bb4fU, 0x384821ceU, 0x68eb6fb2U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x781337e7U, 0x2f75a020U, 0x59e168e8U, 0x813c5902U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00400a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func101(0x57a4dc0fU, 0x5026295aU, 0x0094987dU, 0x525c1e3dU); + } + else + { + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00500a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func101(0xc86836bfU, 0x14e2554aU, 0xd083c13aU, 0xd730e985U); + } + SCE->REG_A4H = 0x00040c05U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + R_SCE_func100(0x6d83a471U, 0x8f1cc5ebU, 0x5e6419c6U, 0xf6625b15U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00000e95U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + R_SCE_func102(0xad64c352U, 0xcb673186U, 0x3b27a3a2U, 0x2b9c70f1U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_ECH = 0x3420a840U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x34202862U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xd78cc9fcU, 0x96cf6384U, 0xf5f9ce64U, 0x30115a4aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x5b484a5dU, 0xfecf589eU, 0x0ebcc19cU, 0x71f30fb5U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00000e95U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e2U; + SCE->REG_ECH = 0x000568e7U; + SCE->REG_ECH = 0x00026ce7U; + SCE->REG_ECH = 0x00003827U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x00003402U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x000028c0U; + SCE->REG_ECH = 0x00008cc0U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x00004406U; + SCE->REG_ECH = 0x00007421U; + SCE->REG_ECH = 0x00007821U; + SCE->REG_ECH = 0x00003c27U; + SCE->REG_ECH = 0x000034c2U; + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x000568c6U; + SCE->REG_ECH = 0x000034e6U; + SCE->REG_ECH = 0x00026ce7U; + SCE->REG_ECH = 0x00000821U; + for (iLoop = 0; iLoop < 4; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3420a8e0U; + SCE->REG_ECH = 0x0000000dU; + SCE->REG_ECH = 0x10003c27U; + SCE->REG_ECH = 0x1000a4e0U; + SCE->REG_ECH = 0x00000004U; + } + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00900c05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + R_SCE_func100(0x6a9a696fU, 0x92542a6eU, 0xdaf3bd9cU, 0xc8cc3eabU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x23f7fa74U, 0xb4c3e8fdU, 0x409d1fecU, 0xfe9fbe22U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + R_SCE_func102(0xff29fa67U, 0x3ac06831U, 0x26688af2U, 0x4550992cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p41f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41i.c new file mode 100644 index 0000000000..2fa9f76983 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41i.c @@ -0,0 +1,244 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128CmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004102U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x806b69a1U, 0x4401f601U, 0x159813a3U, 0x31e6b840U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xc818d564U, 0x446358b3U, 0x9f5ade09U, 0xaa36c0b3U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x84480b5eU, 0x702af309U, 0x667db8cfU, 0x653a1de7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000041U); + R_SCE_func101(0x0c6833f6U, 0x7e3a76aaU, 0x64ec58dbU, 0x195b3244U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + R_SCE_func101(0xccce5a7dU, 0xb398ca55U, 0x0d1b916bU, 0x5ceb7815U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000041U); + R_SCE_func101(0x0bf36470U, 0x140fe110U, 0x14d4a69dU, 0x7cbd6b5dU); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x2a46c04bU; + R_SCE_func101(0xa69fd8c9U, 0x4ab8579dU, 0xe252329fU, 0x62141c53U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000041U); + R_SCE_func101(0xdd306e5aU, 0x69d8b67cU, 0xac3d0851U, 0x1a6dbd30U); + R_SCE_func044(); + R_SCE_func100(0xd21dbd30U, 0x4e255cd0U, 0x6fab84abU, 0xc63c660cU); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x1919413fU, 0x8d4d2143U, 0x6c5a4fabU, 0xc2209b55U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xa5119c11U, 0x944dc431U, 0x12212f3fU, 0x884e44a1U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p41i_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41u.c new file mode 100644 index 0000000000..24bb06c217 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41u.c @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00000e16U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + } + R_SCE_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + R_SCE_func101(0xed3b8673U, 0xdbc4c102U, 0x3ca62e09U, 0x7ac78d98U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p41u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44f.c new file mode 100644 index 0000000000..8759fd0732 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44f.c @@ -0,0 +1,287 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataTLen, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x3c99268aU, 0xe56ce5cdU, 0x32be5a4fU, 0xe39bce14U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x0caeb77fU, 0x6c7a25ebU, 0x72a43244U, 0x8df6d1dcU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00408a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func101(0xfd2e6958U, 0x9a7bd1eaU, 0x6a3e0bb4U, 0x433d7c1dU); + } + else + { + SCE->REG_104H = 0x00000051U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00508a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func101(0x0b0487f7U, 0xa16daf98U, 0x28b00b2dU, 0x5b41d76aU); + } + SCE->REG_A4H = 0x00040c05U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + R_SCE_func100(0xcd42a58cU, 0xa9facab0U, 0x1ff04d18U, 0x7df762c9U); + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008e95U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + R_SCE_func102(0xd240bfa2U, 0x20607f20U, 0xea5ffc9aU, 0xbcda7f4fU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_ECH = 0x3420a840U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x34202862U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x4cdb1e5fU, 0x7d48183dU, 0xce648b35U, 0xb2cb1eddU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xd4840de4U, 0x7e04fdb3U, 0x328f5ff6U, 0xb59e7936U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008e95U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e2U; + SCE->REG_ECH = 0x000568e7U; + SCE->REG_ECH = 0x00026ce7U; + SCE->REG_ECH = 0x00003827U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x00003402U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x000028c0U; + SCE->REG_ECH = 0x00008cc0U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x00004406U; + SCE->REG_ECH = 0x00007421U; + SCE->REG_ECH = 0x00007821U; + SCE->REG_ECH = 0x00003c27U; + SCE->REG_ECH = 0x000034c2U; + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x000568c6U; + SCE->REG_ECH = 0x000034e6U; + SCE->REG_ECH = 0x00026ce7U; + SCE->REG_ECH = 0x00000821U; + for (iLoop = 0; iLoop < 4; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3420a8e0U; + SCE->REG_ECH = 0x0000000dU; + SCE->REG_ECH = 0x10003c27U; + SCE->REG_ECH = 0x1000a4e0U; + SCE->REG_ECH = 0x00000004U; + } + SCE->REG_A4H = 0x00040805U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00900c05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + R_SCE_func100(0xfc7d371bU, 0x98382b69U, 0x94b36463U, 0xf8affb93U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x36dd3a0fU, 0x555b2131U, 0x0cf8896aU, 0xa402ff55U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + R_SCE_func102(0x4bcb12d8U, 0xb4d7fa3cU, 0xf015b3c8U, 0xe3378a56U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p44f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44i.c new file mode 100644 index 0000000000..d57a3bad00 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44i.c @@ -0,0 +1,262 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256CmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004402U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x0641bef4U, 0x285a183eU, 0xf3f948a7U, 0x52d5e2cbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x7311bfe6U, 0x679a1d46U, 0x529df907U, 0x94540dccU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x50afc838U, 0xde48f6d5U, 0x7b9ea712U, 0x67a6dd17U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000044U); + R_SCE_func101(0x36190b03U, 0x0e26676fU, 0x9e6d7a11U, 0x13d7b1e2U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + R_SCE_func101(0xa7bcf663U, 0x6accbc81U, 0xdb4c6330U, 0x4417a024U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000044U); + R_SCE_func101(0x030dbc94U, 0x4878bbfbU, 0x656d139bU, 0xe8480b15U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x85d04999U; + R_SCE_func101(0xaf7589dcU, 0x9121b8f1U, 0xd4b94ebcU, 0x3bee5261U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000044U); + R_SCE_func101(0xe80b1607U, 0x67675794U, 0x21ca9d08U, 0xbeb7b287U); + R_SCE_func044(); + R_SCE_func100(0xc402a2b4U, 0x63500607U, 0x52382e08U, 0xa9309ba5U); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xdd1785a2U, 0x936f21dcU, 0x92a88c2eU, 0x1f9994e9U); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x9e6b9e6fU, 0x229393a2U, 0x9ad2114fU, 0xbcfe6dacU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x433a0cf9U, 0x7ba59941U, 0xa289ba40U, 0x30ac3164U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p44i_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44u.c new file mode 100644 index 0000000000..fb4d6e979a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44u.c @@ -0,0 +1,85 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008e16U; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + } + R_SCE_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + R_SCE_func101(0x72046884U, 0x0acb4da6U, 0x0e4f3272U, 0x0d75bcbeU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p44u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47f.c new file mode 100644 index 0000000000..73a613940e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47f.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128EncryptDecryptFinalSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0x5d063e63U, 0x29d2ef22U, 0xf2e8e8f7U, 0x2421c5d1U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0xa5a092e1U, 0x7cc8cf80U, 0xa74cd72aU, 0x222c79ccU); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0xe48b67a5U, 0x6bbab303U, 0xe3b5ec9aU, 0x92b11554U); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0xdf132e78U, 0x24928b1eU, 0xeb097e2fU, 0x8dc218ffU); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0x84f4cd75U, 0xcb9045d4U, 0xb5b191ccU, 0x5f269dd1U); + } + R_SCE_func100(0x0fd5f67dU, 0x5ec2f7abU, 0x5c991269U, 0xfd47b15fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x32ee6a1cU, 0x79534996U, 0xeca36e51U, 0x5d6e0b76U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func102(0x2c562bd3U, 0x65273f48U, 0x339e1c90U, 0x3c2bbcf8U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p47f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47i.c new file mode 100644 index 0000000000..0374725828 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47i.c @@ -0,0 +1,431 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004702U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_E0H = 0x80020000U; + SCE->REG_104H = 0x00000168U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008820U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x48e01049U, 0x46a5a173U, 0x132207eeU, 0x0f0b3456U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x5e259f11U, 0xdc6dd68fU, 0x143bc940U, 0x6d60cd8bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x3000a800U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_ECH = 0x00010020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xbd09a089U, 0xc02fc7c3U, 0x58e2c804U, 0x809159e0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x38000c21U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xa9e65619U, 0xd606cb32U, 0x36ed3ee2U, 0xc82d425bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000047U); + R_SCE_func101(0x1f773430U, 0x6263a607U, 0x9816545cU, 0x4749c435U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + R_SCE_func101(0xd4455ea7U, 0x83b5d047U, 0xf0e768fdU, 0xe41a93e2U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000047U); + R_SCE_func101(0x9a7234d4U, 0x9541e0f9U, 0xe6159252U, 0xad0ec75dU); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x2a46c04bU; + R_SCE_func101(0xd71ed4a6U, 0xe35e7667U, 0xb862af8fU, 0x2ab18fddU); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000047U); + R_SCE_func101(0xb06d6acfU, 0x445dc592U, 0x8ef705a9U, 0x057928b9U); + R_SCE_func044(); + R_SCE_func100(0x1bc3eebdU, 0x1eba307dU, 0xe766b1fcU, 0x1c0d0c66U); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xb7ea05efU, 0xe3690f71U, 0xd995eaa1U, 0x726087d6U); + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e2U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_ECH = 0x1000b540U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_ECH = 0x2000b540U; + SCE->REG_ECH = 0x0000000eU; + SCE->REG_ECH = 0x3800584aU; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e2U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000feU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x0000a800U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000047U); + R_SCE_func101(0x788c8f0dU, 0x8f527d94U, 0xd6a056fdU, 0x2690b02fU); + R_SCE_func059(); + R_SCE_func100(0x48542acaU, 0x2807dcfeU, 0x2750972dU, 0xb07a75a2U); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x99721353U, 0x8a7aa142U, 0xb14ce98fU, 0x2aaae150U); + } + R_SCE_func100(0x014371b8U, 0x5770b55bU, 0x00a05634U, 0xe0ed98b7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x16e5db17U, 0xa734fe38U, 0xa52fb198U, 0x3d114ea6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x2ed70e21U, 0xe69b2fe0U, 0x4fc6a845U, 0x9c17efdfU); + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0x35e98f7cU, 0x6f05fe1cU, 0x6a2ff2c0U, 0x88defdc8U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0xf8811a36U, 0x5ea76048U, 0x920db2c8U, 0x6e67cd17U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + R_SCE_func101(0x2a2d0e47U, 0x4e122129U, 0x9b3f4b2dU, 0x99109537U); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + R_SCE_func101(0x78040bd6U, 0xea6ce037U, 0xe3221812U, 0xe6f5831dU); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + R_SCE_func101(0xb815fa8aU, 0xbf2c5ed0U, 0x88c591a2U, 0xb065eca3U); + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p47i_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47u.c new file mode 100644 index 0000000000..d36e8e7782 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47u.c @@ -0,0 +1,173 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0xc08deceaU, 0x8caa4f21U, 0x26011832U, 0xc5f51687U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00000a86U; + SCE->REG_04H = 0x0000c100U; + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0xf069623aU, 0x0c6013d8U, 0x974361e1U, 0x3c6a996bU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00004a86U; + SCE->REG_04H = 0x0000c100U; + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0x5a3d8e53U, 0x5fdb5e75U, 0x59e8b6ceU, 0x9f150b09U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00000e96U; + SCE->REG_04H = 0x0000c100U; + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0x2f1d1b6cU, 0xd15facfcU, 0x11e575ffU, 0x9cda8093U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x000049a6U; + SCE->REG_04H = 0x0000c100U; + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0x74a849e6U, 0x949a5695U, 0x88348f60U, 0x5752e2eeU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x000007b6U; + SCE->REG_04H = 0x0000c100U; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0xcf4567e3U, 0x341b3387U, 0x73b36185U, 0x8010c277U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0xc663f336U, 0x87d18954U, 0x49517e1fU, 0xccd83916U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0xc09de111U, 0xba877e4fU, 0x80fbdd05U, 0x69261dc1U); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x26b603beU, 0xab0304e2U, 0x638ce19cU, 0xb9e7a794U); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x74274a46U, 0xa78af843U, 0x5e2fb49aU, 0x7e43a459U); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p47u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50f.c new file mode 100644 index 0000000000..7e4df8acfd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50f.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256EncryptDecryptFinalSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0xb3ea37b8U, 0x6ad17bf2U, 0x710bb8a3U, 0x460cf1b6U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0x91275c19U, 0x74d9d0abU, 0xddf7783cU, 0xd67778dfU); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0x3bb45434U, 0xcc9d51d6U, 0xc15fc69fU, 0xdbabc79bU); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0xb3e0a471U, 0x1b3bdff5U, 0x64476686U, 0x1768142fU); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0x7264772aU, 0x3a7218d5U, 0xeef3ee6dU, 0xc3562d7dU); + } + R_SCE_func100(0xcf26bed4U, 0xee7d1b1aU, 0x62c36f9aU, 0x32bda1dfU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xaf316b16U, 0xe78ceafeU, 0x0bb27edeU, 0xb6a6d348U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func102(0xad806256U, 0xd495f48fU, 0x3bc0b975U, 0xf4fe45aaU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p50f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50i.c new file mode 100644 index 0000000000..e3217fba7d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50i.c @@ -0,0 +1,467 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005002U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_E0H = 0x80020000U; + SCE->REG_104H = 0x00000168U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008820U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xd9a3c43eU, 0x74e81ed3U, 0xef4322e8U, 0xf2636962U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xe89b71acU, 0x7c710834U, 0x5382871aU, 0x21913ecfU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x3000a800U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_ECH = 0x00010020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xe0d80bb6U, 0xa9729556U, 0xc2e70d14U, 0xbda5e8dcU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x38000c21U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x1b2825c9U, 0x2160dd9cU, 0xc961235fU, 0x3f976065U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000050U); + R_SCE_func101(0xcece3ac8U, 0x807c71beU, 0xc43e5778U, 0x258a1c2cU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + R_SCE_func101(0xd2fe05a5U, 0x23ff8b8bU, 0x5680db62U, 0xf1e9c0a1U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000050U); + R_SCE_func101(0x3ac8371dU, 0x972a635eU, 0x6349922cU, 0x73e27fafU); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x85d04999U; + R_SCE_func101(0x1af275c3U, 0x65cba4d1U, 0x9aab259dU, 0x1982b405U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000050U); + R_SCE_func101(0x2debc2e8U, 0xb4d89566U, 0x20b2e67aU, 0xd5bfabfaU); + R_SCE_func044(); + R_SCE_func100(0x51f45d2aU, 0x6847e058U, 0xcabf6e84U, 0x13323cb4U); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x71a1f7c9U, 0x46921b40U, 0x8e04cf35U, 0xb0774acfU); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xdd031e7cU, 0x054b70fcU, 0xab970395U, 0xaa314c37U); + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e2U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00010000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_ECH = 0x1000b540U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_ECH = 0x2000b540U; + SCE->REG_ECH = 0x0000000eU; + SCE->REG_ECH = 0x3800584aU; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e2U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000feU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x0000a800U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000050U); + R_SCE_func101(0xf81cec2aU, 0x18cb66cdU, 0xa894f791U, 0xc0d7bba7U); + R_SCE_func059(); + R_SCE_func100(0x8161675eU, 0xa87e8a65U, 0xa911cfc0U, 0x77f736aaU); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xfba9c719U, 0xd5ad5ef3U, 0xd3c8570bU, 0xf460133bU); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x7626a17dU, 0xd41a80eeU, 0x30b71d12U, 0x8b2ae299U); + } + R_SCE_func100(0x936208f7U, 0xf5a0ece4U, 0x1297b685U, 0x40b886e9U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x0221dc04U, 0x0659357dU, 0x06dae8b4U, 0x821817d9U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0xa63e2490U, 0xef971612U, 0xe43e1f98U, 0xc9c1ab57U); + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0x3663cd22U, 0xb0751e36U, 0x284e91eaU, 0x6669be63U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func101(0xf6b4975eU, 0xaf5c7a03U, 0x86a73cf7U, 0x845710e9U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + R_SCE_func101(0x6df29989U, 0xeb7d4bf6U, 0x301fd413U, 0x77f0409cU); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + R_SCE_func101(0x35e803fbU, 0x0568343cU, 0x3e769176U, 0x9c8483d5U); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + R_SCE_func101(0x472abad5U, 0x4aa9e6c7U, 0xb97a556eU, 0xbbcff903U); + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p50i_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50u.c new file mode 100644 index 0000000000..11921486d0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50u.c @@ -0,0 +1,178 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0x128e5264U, 0x59e9387eU, 0x5fe79e18U, 0x3d15d141U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008a86U; + SCE->REG_04H = 0x0000c100U; + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0x3a3a928dU, 0xccbb107eU, 0x999d6b35U, 0xcdff2fd9U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0000ca86U; + SCE->REG_04H = 0x0000c100U; + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0x84d19817U, 0x81d9c173U, 0x053e9c1bU, 0x65660ffdU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008e96U; + SCE->REG_04H = 0x0000c100U; + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0x2ce0913eU, 0x8dd1daf5U, 0x434a4259U, 0xbeb15720U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x0000c9a6U; + SCE->REG_04H = 0x0000c100U; + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_104H = 0x00000362U; + R_SCE_func100(0xc3bd00d2U, 0xdfcdffe8U, 0x21bfc115U, 0x5220d5e9U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x000087b6U; + SCE->REG_04H = 0x0000c100U; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x604b6104U, 0xacdd30b8U, 0x31071817U, 0xf9f45895U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x9461b710U, 0xe0f6ea4dU, 0x81f18309U, 0xf773a8eeU); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x96f513bfU, 0x1dd583ddU, 0x8119c69eU, 0x5c42786fU); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x133a4c90U, 0x78a68808U, 0x0478a49dU, 0xadf672efU); + } + else if (0x04000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x317b2a2eU, 0x5e04d777U, 0xf918ab42U, 0xad0cbde7U); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p50u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p53.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p53.c new file mode 100644 index 0000000000..24a0f3da98 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p53.c @@ -0,0 +1,332 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Rsa1024ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, const uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005301U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000053U); + R_SCE_func101(0x94ddb97fU, 0x655472f1U, 0xb9f739b8U, 0x4d1557caU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000aU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000053U); + R_SCE_func101(0x618968baU, 0x4f7ea0adU, 0x4e75d829U, 0x63b95a10U); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00000001U; + SCE->REG_28H = 0x009f0001U; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + SCE->REG_104H = 0x00004362U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x02e08887U; + for(iLoop=0; iLoop<32; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e08885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[33]; + SCE->REG_100H = InData_KeyIndex[34]; + SCE->REG_100H = InData_KeyIndex[35]; + SCE->REG_100H = InData_KeyIndex[36]; + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x00f087b7U; + for(iLoop=36; iLoop<68; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[69]; + SCE->REG_100H = InData_KeyIndex[70]; + SCE->REG_100H = InData_KeyIndex[71]; + SCE->REG_100H = InData_KeyIndex[72]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x9ea88494U, 0x84ce73bcU, 0xfbd04922U, 0xd92d4d9cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2dfb5b3fU, 0xc8967dbcU, 0x9691aa74U, 0xfceceb89U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x4894eb25U, 0xaaf13b89U, 0xb83aaac5U, 0xed92ffd8U); + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00001f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_24H = 0x000068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000730U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + R_SCE_func100(0x6cdfa4e0U, 0x986358f9U, 0x22a6e61aU, 0xcca19ed0U); + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000383U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + R_SCE_func102(0xf325ef4bU, 0xe75a1041U, 0x4080d146U, 0x162e5c40U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p53.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p54.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p54.c new file mode 100644 index 0000000000..49572128f0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p54.c @@ -0,0 +1,320 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Rsa1024ModularExponentDecryptSub(uint32_t *InData_KeyIndex, const uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005402U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000054U); + R_SCE_func101(0xb78d1284U, 0x22fe7606U, 0xbff361d8U, 0xd710f739U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000bU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000054U); + R_SCE_func101(0xcd244c25U, 0x699a5812U, 0xc2ea367dU, 0xe819f639U); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00000001U; + SCE->REG_28H = 0x009f0001U; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + SCE->REG_104H = 0x00005f62U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x02f087b7U; + for(iLoop=0; iLoop<32; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000011U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x00f087b7U; + for(iLoop=32; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + SCE->REG_D0H = 0x40000700U; + SCE->REG_C4H = 0x00f087b7U; + for(iLoop=64; iLoop<96; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[97]; + SCE->REG_100H = InData_KeyIndex[98]; + SCE->REG_100H = InData_KeyIndex[99]; + SCE->REG_100H = InData_KeyIndex[100]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x57a1563aU, 0x2f914180U, 0x1a5f3579U, 0x60a1140dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x11bb16e5U, 0x7b0bc355U, 0x0e9e4673U, 0xb30c91a7U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x7f65bd2aU, 0x4545ad03U, 0xef52eb72U, 0x1f78fe97U); + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00001f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_24H = 0x000068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000440U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + R_SCE_func100(0xf38a6174U, 0x3b18e576U, 0xa04d9ef6U, 0x1fbb3333U); + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000383U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + R_SCE_func102(0xccd22f91U, 0xfe4774edU, 0x665dc0d1U, 0xa9723b73U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p54_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p56.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p56.c new file mode 100644 index 0000000000..24f550b163 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p56.c @@ -0,0 +1,390 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Rsa2048ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, const uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005601U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000056U); + R_SCE_func101(0xf84402aeU, 0x144edd72U, 0x9efe800aU, 0xc90137b3U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000056U); + R_SCE_func101(0x88709601U, 0x4afe835bU, 0x2a36088aU, 0x876e1cadU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00000001U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + SCE->REG_104H = 0x00008362U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x02e08887U; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e08885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[65]; + SCE->REG_100H = InData_KeyIndex[66]; + SCE->REG_100H = InData_KeyIndex[67]; + SCE->REG_100H = InData_KeyIndex[68]; + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00f087b7U; + for(iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[133]; + SCE->REG_100H = InData_KeyIndex[134]; + SCE->REG_100H = InData_KeyIndex[135]; + SCE->REG_100H = InData_KeyIndex[136]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x72d9b007U, 0xaffb697bU, 0x0689545fU, 0x513db4e3U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xeb0331ecU, 0x7ff6afb7U, 0x41bb4054U, 0xd554b8ddU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0xd4427409U, 0xd35eb229U, 0xe5292126U, 0x47c865d0U); + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00003f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_100H = InData_Text[32]; + SCE->REG_100H = InData_Text[33]; + SCE->REG_100H = InData_Text[34]; + SCE->REG_100H = InData_Text[35]; + SCE->REG_100H = InData_Text[36]; + SCE->REG_100H = InData_Text[37]; + SCE->REG_100H = InData_Text[38]; + SCE->REG_100H = InData_Text[39]; + SCE->REG_100H = InData_Text[40]; + SCE->REG_100H = InData_Text[41]; + SCE->REG_100H = InData_Text[42]; + SCE->REG_100H = InData_Text[43]; + SCE->REG_100H = InData_Text[44]; + SCE->REG_100H = InData_Text[45]; + SCE->REG_100H = InData_Text[46]; + SCE->REG_100H = InData_Text[47]; + SCE->REG_100H = InData_Text[48]; + SCE->REG_100H = InData_Text[49]; + SCE->REG_100H = InData_Text[50]; + SCE->REG_100H = InData_Text[51]; + SCE->REG_100H = InData_Text[52]; + SCE->REG_100H = InData_Text[53]; + SCE->REG_100H = InData_Text[54]; + SCE->REG_100H = InData_Text[55]; + SCE->REG_100H = InData_Text[56]; + SCE->REG_100H = InData_Text[57]; + SCE->REG_100H = InData_Text[58]; + SCE->REG_100H = InData_Text[59]; + SCE->REG_100H = InData_Text[60]; + SCE->REG_100H = InData_Text[61]; + SCE->REG_100H = InData_Text[62]; + SCE->REG_100H = InData_Text[63]; + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000338U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + R_SCE_func100(0x5a3dc203U, 0x76ce43faU, 0x97f683ccU, 0x56825eecU); + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000303U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + OutData_Text[32] = SCE->REG_100H; + OutData_Text[33] = SCE->REG_100H; + OutData_Text[34] = SCE->REG_100H; + OutData_Text[35] = SCE->REG_100H; + OutData_Text[36] = SCE->REG_100H; + OutData_Text[37] = SCE->REG_100H; + OutData_Text[38] = SCE->REG_100H; + OutData_Text[39] = SCE->REG_100H; + OutData_Text[40] = SCE->REG_100H; + OutData_Text[41] = SCE->REG_100H; + OutData_Text[42] = SCE->REG_100H; + OutData_Text[43] = SCE->REG_100H; + OutData_Text[44] = SCE->REG_100H; + OutData_Text[45] = SCE->REG_100H; + OutData_Text[46] = SCE->REG_100H; + OutData_Text[47] = SCE->REG_100H; + OutData_Text[48] = SCE->REG_100H; + OutData_Text[49] = SCE->REG_100H; + OutData_Text[50] = SCE->REG_100H; + OutData_Text[51] = SCE->REG_100H; + OutData_Text[52] = SCE->REG_100H; + OutData_Text[53] = SCE->REG_100H; + OutData_Text[54] = SCE->REG_100H; + OutData_Text[55] = SCE->REG_100H; + OutData_Text[56] = SCE->REG_100H; + OutData_Text[57] = SCE->REG_100H; + OutData_Text[58] = SCE->REG_100H; + OutData_Text[59] = SCE->REG_100H; + OutData_Text[60] = SCE->REG_100H; + OutData_Text[61] = SCE->REG_100H; + OutData_Text[62] = SCE->REG_100H; + OutData_Text[63] = SCE->REG_100H; + R_SCE_func102(0x67be3736U, 0xea551508U, 0xbec3b966U, 0x44f93950U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p56.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p57.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p57.c new file mode 100644 index 0000000000..825e3bef36 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p57.c @@ -0,0 +1,385 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Rsa2048ModularExponentDecryptSub(uint32_t *InData_KeyIndex, const uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005702U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000057U); + R_SCE_func101(0x101a4f3fU, 0x890709bdU, 0xa19ab822U, 0x22cddc9fU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000dU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000057U); + R_SCE_func101(0x79521f65U, 0x25404e2bU, 0xc0275b33U, 0x77d58bbaU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00000001U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + SCE->REG_104H = 0x0000bf62U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x02f087b7U; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80c00001U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00f087b7U; + SCE->REG_00H = 0x00018203U; + for(iLoop=65; iLoop<129; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00f087b7U; + for(iLoop=128; iLoop<192; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[193]; + SCE->REG_100H = InData_KeyIndex[194]; + SCE->REG_100H = InData_KeyIndex[195]; + SCE->REG_100H = InData_KeyIndex[196]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x749acb4cU, 0x43467e72U, 0xa630450bU, 0xc4de5b59U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x282712a3U, 0xbc66da2eU, 0x2f91eb35U, 0xbb70eddfU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x77153f5dU, 0x3fe9b986U, 0xb83f3d45U, 0x2facdd3aU); + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00003f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_100H = InData_Text[32]; + SCE->REG_100H = InData_Text[33]; + SCE->REG_100H = InData_Text[34]; + SCE->REG_100H = InData_Text[35]; + SCE->REG_100H = InData_Text[36]; + SCE->REG_100H = InData_Text[37]; + SCE->REG_100H = InData_Text[38]; + SCE->REG_100H = InData_Text[39]; + SCE->REG_100H = InData_Text[40]; + SCE->REG_100H = InData_Text[41]; + SCE->REG_100H = InData_Text[42]; + SCE->REG_100H = InData_Text[43]; + SCE->REG_100H = InData_Text[44]; + SCE->REG_100H = InData_Text[45]; + SCE->REG_100H = InData_Text[46]; + SCE->REG_100H = InData_Text[47]; + SCE->REG_100H = InData_Text[48]; + SCE->REG_100H = InData_Text[49]; + SCE->REG_100H = InData_Text[50]; + SCE->REG_100H = InData_Text[51]; + SCE->REG_100H = InData_Text[52]; + SCE->REG_100H = InData_Text[53]; + SCE->REG_100H = InData_Text[54]; + SCE->REG_100H = InData_Text[55]; + SCE->REG_100H = InData_Text[56]; + SCE->REG_100H = InData_Text[57]; + SCE->REG_100H = InData_Text[58]; + SCE->REG_100H = InData_Text[59]; + SCE->REG_100H = InData_Text[60]; + SCE->REG_100H = InData_Text[61]; + SCE->REG_100H = InData_Text[62]; + SCE->REG_100H = InData_Text[63]; + SCE->REG_E0H = 0x00000100U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000fcU; + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000248U; + SCE->REG_E0H = 0x81c0001fU; + SCE->REG_00H = 0x00013803U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_E0H = 0x00000000U; + R_SCE_func100(0x6278f89dU, 0xc5512232U, 0xeda389acU, 0x5cc606c3U); + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000303U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + OutData_Text[32] = SCE->REG_100H; + OutData_Text[33] = SCE->REG_100H; + OutData_Text[34] = SCE->REG_100H; + OutData_Text[35] = SCE->REG_100H; + OutData_Text[36] = SCE->REG_100H; + OutData_Text[37] = SCE->REG_100H; + OutData_Text[38] = SCE->REG_100H; + OutData_Text[39] = SCE->REG_100H; + OutData_Text[40] = SCE->REG_100H; + OutData_Text[41] = SCE->REG_100H; + OutData_Text[42] = SCE->REG_100H; + OutData_Text[43] = SCE->REG_100H; + OutData_Text[44] = SCE->REG_100H; + OutData_Text[45] = SCE->REG_100H; + OutData_Text[46] = SCE->REG_100H; + OutData_Text[47] = SCE->REG_100H; + OutData_Text[48] = SCE->REG_100H; + OutData_Text[49] = SCE->REG_100H; + OutData_Text[50] = SCE->REG_100H; + OutData_Text[51] = SCE->REG_100H; + OutData_Text[52] = SCE->REG_100H; + OutData_Text[53] = SCE->REG_100H; + OutData_Text[54] = SCE->REG_100H; + OutData_Text[55] = SCE->REG_100H; + OutData_Text[56] = SCE->REG_100H; + OutData_Text[57] = SCE->REG_100H; + OutData_Text[58] = SCE->REG_100H; + OutData_Text[59] = SCE->REG_100H; + OutData_Text[60] = SCE->REG_100H; + OutData_Text[61] = SCE->REG_100H; + OutData_Text[62] = SCE->REG_100H; + OutData_Text[63] = SCE->REG_100H; + R_SCE_func102(0xca06c470U, 0xb9809f5eU, 0x7749719aU, 0x10d8c9bfU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p57_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5a.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5a.c new file mode 100644 index 0000000000..3c3d313733 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5a.c @@ -0,0 +1,491 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_DlmsCosemQeuSignatureVerificationSub(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_data, uint32_t *InData_Signature, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005a02U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_104H = 0x00000f68U; + SCE->REG_E0H = 0x8090001eU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[iLoop + 0]; + } + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005aU); + R_SCE_func101(0x52ba6846U, 0x632ad48dU, 0xf0a1ef74U, 0xcb233ce5U); + R_SCE_func043(); + R_SCE_func023(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005aU); + R_SCE_func101(0xe822100cU, 0x9c7a7e7fU, 0x6a8a73aaU, 0xad48c94eU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e08887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000091U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x01e3d7efU, 0x3846a65cU, 0x10013f6eU, 0x4be4e5e6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2a54b280U, 0xb447575eU, 0xb4463ffaU, 0x14f7cd4eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x99beda16U, 0x24bc02a8U, 0x9f480062U, 0x80f3e1baU); + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_74H = 0x00000002U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_104H = 0x0000106cU; + SCE->REG_E0H = 0x8091001eU; + for (iLoop = 0; iLoop < 17; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_data[iLoop + 0]; + } + SCE->REG_104H = 0x00000e64U; + for(iLoop = 17; iLoop < 32; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_data[iLoop + 0]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x0000013CU; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000001F8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005aU); + R_SCE_func101(0xed687a0fU, 0x47030bdfU, 0xd0cfbf4fU, 0x0e6b4f87U); + R_SCE_func010_r1(OFS_ADR); + R_SCE_func100(0xe903ca1aU, 0xe289b369U, 0x0ec44677U, 0x884a646bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xdf598a30U, 0xf59b0f74U, 0x0d7c57c1U, 0xef5b27d0U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_28H = 0x008f0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x2fe0c432U, 0xe3a94ae5U, 0xb6fad6e1U, 0xf37f2ef5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x8190001eU; + SCE->REG_00H = 0x00003843U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xd61f62e2U, 0x11b6ca6aU, 0x0a08ebbeU, 0x0a697ce6U); + } + else + { + SCE->REG_E0H = 0x8191001eU; + SCE->REG_00H = 0x08000807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08013803U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x78388171U, 0x9e4c2147U, 0xa626838bU, 0x8ef355c8U); + } + R_SCE_func100(0x40280ed0U, 0x61568988U, 0xa7716d91U, 0x5d40a21fU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005aU); + R_SCE_func101(0x326c8453U, 0x7d6a8e30U, 0x79fdedc6U, 0x1c9688c2U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x75614788U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000021U); + R_SCE_func101(0xf595fc97U, 0x193af4a0U, 0x5b882267U, 0xfeb3e8aeU); + R_SCE_func044(); + R_SCE_func100(0x8054ff5eU, 0x871121f1U, 0x6f12550bU, 0x0aa03c8eU); + SCE->REG_00H = 0x00002343U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000242U; + for (iLoop = 1; iLoop < 17; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x010eaa89U, 0x74239963U, 0x25f56e98U, 0x55a79c54U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0xe6269f98U, 0x78a7533dU, 0x32d4e62dU, 0x9eb17913U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + R_SCE_func102(0x2332a93dU, 0xcdc103a2U, 0xc3424ca2U, 0xae18bc76U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p5a_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5aIA.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5aIA.c new file mode 100644 index 0000000000..2cc021f72a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5aIA.c @@ -0,0 +1,265 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_EcdhP256QeuOutputSub(uint32_t *InData_Cmd, uint32_t *InData_data, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005a02U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_104H = 0x00001068U; + SCE->REG_E0H = 0x8091001eU; + for (iLoop = 0; iLoop < 17; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_data[iLoop + 0]; + } + SCE->REG_28H = 0x008f0001U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x63ef3c96U, 0x8bd4214cU, 0xecd20b25U, 0x9ea5f2f5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x8190001eU; + SCE->REG_00H = 0x00003843U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x7f6df52dU, 0x8f3e0234U, 0xc9cd1bf9U, 0xc4727d98U); + } + else + { + SCE->REG_E0H = 0x8191001eU; + SCE->REG_00H = 0x08000807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08013803U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x2573acd4U, 0x299be00dU, 0x10b37e28U, 0x87a8d24dU); + } + R_SCE_func100(0xa5d912eaU, 0x44c782a2U, 0xf513e6d0U, 0xa0882fe4U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000048U); + R_SCE_func101(0x34956140U, 0x1fe2187aU, 0x29db1464U, 0x3b891a7bU); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x01771788U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000048U); + R_SCE_func101(0x56a9f7cfU, 0xb7993096U, 0xa91cda35U, 0x4bd9fe11U); + R_SCE_func044(); + R_SCE_func100(0xfcbf927fU, 0xbe320726U, 0x926ce5b1U, 0xb5548303U); + SCE->REG_00H = 0x00002343U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000242U; + for (iLoop = 1; iLoop < 17; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x21acc534U, 0x4d6a5977U, 0xa402e93cU, 0x34bdbe6dU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0x642e5b3eU, 0x38c3cf91U, 0xc9eb5311U, 0xd5782200U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + R_SCE_func102(0x6b1e07a9U, 0x05f193f9U, 0x5c98f1b7U, 0xd9b346d5U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p5a_IAR.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5b.c new file mode 100644 index 0000000000..793f33d6e7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5b.c @@ -0,0 +1,1583 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_DlmsCosemQevSignatureGenerationSub(uint32_t *InData_Cmd, uint32_t *InData_KeyType, uint32_t *InData_PubKeyIndex, uint32_t *InData_PrivKeyIndex, uint32_t *InData_key_id, uint32_t *OutData_data, uint32_t *OutData_Signature, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005b02U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010320U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38000f39U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xe7faef79U, 0x3cafb841U, 0x98211b32U, 0xc1e489f4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func100(0xea67e567U, 0x760bfc88U, 0x00d3d68bU, 0x0fe5deddU); + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + R_SCE_func100(0x74eb11c0U, 0x5c455d6fU, 0x05e29862U, 0x03f86b08U); + R_SCE_func004_r1(OFS_ADR); + R_SCE_func100(0xbf05ffb7U, 0xf99e84b4U, 0x19016930U, 0xa71be3d1U); + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x8000c0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00890001U; + R_SCE_func103(); + R_SCE_func100(0xfd045a9cU, 0x9a3f328aU, 0x043bc47eU, 0x7de92c4eU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + R_SCE_func100(0xee99878fU, 0xb8cdf0f2U, 0x56992297U, 0xa7cee5e9U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x0000320bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00890001U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x0000a206U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000016c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000682U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + R_SCE_func100(0x874ba89cU, 0x9ee296ebU, 0x269018d4U, 0xf71e8232U); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func005_r1(OFS_ADR); + R_SCE_func100(0xa0deab0bU, 0x21db8910U, 0xd0b07063U, 0x55f9a46eU); + R_SCE_func025_r1(OFS_ADR); + R_SCE_func100(0x7192245eU, 0x1732a5d0U, 0x29574164U, 0x51b47bacU); + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x8000b8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000ec0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000f008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00311030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x3942522bU, 0xf0e98d8fU, 0x5e5fd5f4U, 0xa8f37079U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func101(0xeef22898U, 0xcfa4573eU, 0x9abd9352U, 0x298df8b6U); + } + else + { + R_SCE_func100(0xb534bd61U, 0x3767a7b6U, 0x41362273U, 0x0fcc2ad5U); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000040c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x6b9666b8U, 0x614c27d4U, 0xb0526600U, 0x957ee16bU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010080U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003544U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005bU); + R_SCE_func101(0xf11b8ebaU, 0x342c8c8bU, 0x5b50aed7U, 0x37271e14U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x6ff334f0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005bU); + R_SCE_func101(0x33684180U, 0xc79813f4U, 0x969e798eU, 0xbd2d0808U); + R_SCE_func044(); + R_SCE_func100(0x7d722dd4U, 0x829f4da7U, 0x78d8b8c9U, 0xb54f50c3U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x0000002aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + R_SCE_func100(0x42cb5af2U, 0x24d2537dU, 0xcb4d29f2U, 0xcfad354eU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + OutData_KeyIndex[12] = SCE->REG_100H; + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func101(0xa8f44139U, 0x0139dd9dU, 0x51ef9d6dU, 0x8d2358f1U); + } + } + else + { + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005bU); + R_SCE_func101(0x4944c738U, 0x2856c6ccU, 0x01f1c31bU, 0x7fb9c548U); + R_SCE_func043(); + R_SCE_func023(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000026U); + R_SCE_func101(0x5ec66cf5U, 0xca77b555U, 0xfba37855U, 0x9091fddbU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e08887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[1]; + SCE->REG_100H = InData_PubKeyIndex[2]; + SCE->REG_100H = InData_PubKeyIndex[3]; + SCE->REG_100H = InData_PubKeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[5]; + SCE->REG_100H = InData_PubKeyIndex[6]; + SCE->REG_100H = InData_PubKeyIndex[7]; + SCE->REG_100H = InData_PubKeyIndex[8]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000092U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[9]; + SCE->REG_100H = InData_PubKeyIndex[10]; + SCE->REG_100H = InData_PubKeyIndex[11]; + SCE->REG_100H = InData_PubKeyIndex[12]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[13]; + SCE->REG_100H = InData_PubKeyIndex[14]; + SCE->REG_100H = InData_PubKeyIndex[15]; + SCE->REG_100H = InData_PubKeyIndex[16]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[17]; + SCE->REG_100H = InData_PubKeyIndex[18]; + SCE->REG_100H = InData_PubKeyIndex[19]; + SCE->REG_100H = InData_PubKeyIndex[20]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xc4932866U, 0xc020b934U, 0xdbbb60a7U, 0x31ea98feU); + } + R_SCE_func100(0x7e047847U, 0x7153fa6cU, 0x2d6534cfU, 0x6412db81U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xabcff604U, 0x29fd87f5U, 0xbd890bd5U, 0xc36cfcb6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_28H = 0x008f0001U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x8081001fU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xd5cd95f2U, 0x97415d85U, 0xa14a0955U, 0x0823b8cdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func100(0xc350d6fdU, 0xe2da0ba3U, 0x97558541U, 0x10ef1ccbU); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x8090001fU; + SCE->REG_00H = 0x00008343U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x8190001fU; + SCE->REG_04H = 0x00000642U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_data[iLoop + 0] = SCE->REG_100H; + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_ECH = 0x00000200U; + R_SCE_func101(0x9d08f134U, 0x94622518U, 0x817d36d2U, 0x6f01faeaU); + } + else + { + R_SCE_func100(0x5efc688eU, 0x1f97326aU, 0x78a3e04fU, 0x3dc453b7U); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x8091001fU; + SCE->REG_00H = 0x08008007U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08018303U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0800800fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_key_id[0]; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x02003c1fU; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x8191001fU; + SCE->REG_04H = 0x00000646U; + for (iLoop = 0; iLoop < 17; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_data[iLoop + 0] = SCE->REG_100H; + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000061U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_ECH = 0x00000208U; + R_SCE_func101(0x94702511U, 0x98fa5e61U, 0x74fc2c22U, 0xfffd795cU); + } + R_SCE_func100(0x53ac7d78U, 0xbdc4edd2U, 0x89f83ee2U, 0x7844b9bcU); + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x02003fdfU; + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x8191001fU; + SCE->REG_00H = 0x00005847U; + SCE->REG_74H = 0x00000002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_F8H = 0x00000040U; + SCE->REG_E0H = 0x81020020U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_74H = 0x00000000U; + SCE->REG_1CH = 0x00001600U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008523U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00870001U; + OFS_ADR = 128; + R_SCE_func004_r1(OFS_ADR); + R_SCE_func100(0x79654b1dU, 0x3187c934U, 0xf711a7f8U, 0x126bf99fU); + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + R_SCE_func100(0x2dcd0c24U, 0x333ecec7U, 0xcce5243fU, 0x3f07491cU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000b208U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xcc184981U, 0xab8a9056U, 0xac2add56U, 0xf833644aU); + R_SCE_func005_r1(OFS_ADR); + R_SCE_func100(0xafcb0316U, 0x07cc3894U, 0xc6cb9e44U, 0x4c9d6899U); + R_SCE_func025_r1(OFS_ADR); + R_SCE_func100(0x58378b45U, 0x141968f8U, 0xffe41c67U, 0x5a7bc199U); + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x8000b8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000ec0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000f008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00311030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x91d5e88eU, 0x2bb72cdeU, 0x706c1373U, 0x3674cd99U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2176f95dU, 0xd98d2d55U, 0x1c56710dU, 0xd155e41bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xaa5a6faaU, 0x8dd8979dU, 0x19c580d4U, 0x0d4b615dU); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000040c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x8000d4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004808U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x85e2f399U, 0xeebea4a0U, 0x540b81adU, 0x5715b32cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xcc04217fU, 0xad99e2fbU, 0xfdeb63deU, 0x91af4c54U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x2d1427fbU, 0xfb568446U, 0x54b73bb5U, 0xdd3900fdU); + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b8U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000404U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000001U; + SCE->REG_24H = 0x80008c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000001U; + SCE->REG_24H = 0x8000ae0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PrivKeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000026U); + R_SCE_func101(0xe02301daU, 0x04f93fb6U, 0x71e327f7U, 0xaf143528U); + R_SCE_func043(); + R_SCE_func022(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000012U); + R_SCE_func101(0x794bb44eU, 0x62126fc6U, 0xd23fc9ddU, 0xc9a60febU); + R_SCE_func044(); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000018U; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PrivKeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_PrivKeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_PrivKeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_PrivKeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PrivKeyIndex[9]; + SCE->REG_100H = InData_PrivKeyIndex[10]; + SCE->REG_100H = InData_PrivKeyIndex[11]; + SCE->REG_100H = InData_PrivKeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xfb3c8ebbU, 0xd66b3434U, 0x66b62fa9U, 0xafab536dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xe0c530a3U, 0x293736f7U, 0x5c9a5b5cU, 0x5f1fcb74U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x80006c0dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x80004c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xd9b81bc8U, 0x93fe6616U, 0x1b143bffU, 0x6097cdfcU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x3be7d15eU, 0x1ac2af7cU, 0xb14fcb8aU, 0xbee14a9eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x9e0bbd41U, 0xdd32b753U, 0xa8233cfeU, 0xaa1fe799U); + SCE->REG_2CH = 0x0000002bU; + SCE->REG_04H = 0x00000322U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[0] = SCE->REG_100H; + OutData_Signature[1] = SCE->REG_100H; + OutData_Signature[2] = SCE->REG_100H; + OutData_Signature[3] = SCE->REG_100H; + OutData_Signature[4] = SCE->REG_100H; + OutData_Signature[5] = SCE->REG_100H; + OutData_Signature[6] = SCE->REG_100H; + OutData_Signature[7] = SCE->REG_100H; + R_SCE_func100(0xf78eeb4dU, 0x0b4d339aU, 0x69679ce8U, 0xb2fb30b4U); + SCE->REG_2CH = 0x0000002aU; + SCE->REG_04H = 0x00000322U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[8] = SCE->REG_100H; + OutData_Signature[9] = SCE->REG_100H; + OutData_Signature[10] = SCE->REG_100H; + OutData_Signature[11] = SCE->REG_100H; + OutData_Signature[12] = SCE->REG_100H; + OutData_Signature[13] = SCE->REG_100H; + OutData_Signature[14] = SCE->REG_100H; + OutData_Signature[15] = SCE->REG_100H; + SCE->REG_ECH = 0x38000f39U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x9a25cd3bU, 0x2a70c95fU, 0xf3b2443dU, 0x407c7138U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func100(0x0416aa29U, 0xd7ea24dcU, 0x248fe218U, 0x187af7eeU); + SCE->REG_E0H = 0x81010080U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + R_SCE_func101(0xad6a78c1U, 0x7a90d1c3U, 0x8cdcfbacU, 0xce7157e3U); + } + R_SCE_func102(0x118232e7U, 0x9a40eacbU, 0x9e5df756U, 0x61831e66U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p5b_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5c.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5c.c new file mode 100644 index 0000000000..e366561a4d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5c.c @@ -0,0 +1,812 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_DlmsCosemCalculateZSub(uint32_t *InData_KeyType, uint32_t *InData_PubKeyIndex, uint32_t *InData_PrivKeyIndex, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005c02U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x30003340U; + SCE->REG_ECH = 0x00040020U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x75614788U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x01771788U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005cU); + R_SCE_func101(0xa1e573d7U, 0x39ff347dU, 0x5d2d5606U, 0x9bce0f82U); + R_SCE_func068(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005cU); + R_SCE_func101(0x4ca26984U, 0xfebf0385U, 0xa0acd658U, 0xb6d98282U); + R_SCE_func044(); + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x8090000aU; + SCE->REG_00H = 0x00008243U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_PubKeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_PubKeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_PubKeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKeyIndex[17]; + SCE->REG_100H = InData_PubKeyIndex[18]; + SCE->REG_100H = InData_PubKeyIndex[19]; + SCE->REG_100H = InData_PubKeyIndex[20]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd13b6d3aU, 0x059c2356U, 0x8cd6e03dU, 0x39aeee58U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x6a476a9dU, 0x5bbb78f7U, 0x535733c0U, 0x60735454U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_ECH = 0x00000b9cU; + OFS_ADR = 128; + R_SCE_func100(0x337257f0U, 0x8b78c27dU, 0x39bfedeeU, 0x0a8cb5acU); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PrivKeyIndex[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x6f5379e8U, 0xb6f69173U, 0xae6260ebU, 0x9025e97cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00003540U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000020U); + R_SCE_func101(0x0fdb49f8U, 0xba97bfdfU, 0xb0aa2ea8U, 0x39536c16U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x6ff334f0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000011U); + R_SCE_func101(0x311bef69U, 0xc57cb5d6U, 0x8ef36fe9U, 0xf1cd1d6aU); + R_SCE_func044(); + R_SCE_func101(0x19fc1aadU, 0xea0c1e72U, 0x2e3252bcU, 0x5ce4aa39U); + } + else + { + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005cU); + R_SCE_func101(0x7c32d651U, 0x114b30d7U, 0x37f84c24U, 0x7f1d673cU); + R_SCE_func043(); + R_SCE_func022(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000002eU); + R_SCE_func101(0x97e0e6c2U, 0x6901c63aU, 0xbea94ec2U, 0x835b355dU); + R_SCE_func044(); + R_SCE_func101(0xcc811fa6U, 0x523f7bb9U, 0x268bd1a1U, 0x9b65f9d8U); + } + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000011U; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PrivKeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_PrivKeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_PrivKeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_PrivKeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PrivKeyIndex[9]; + SCE->REG_100H = InData_PrivKeyIndex[10]; + SCE->REG_100H = InData_PrivKeyIndex[11]; + SCE->REG_100H = InData_PrivKeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd6aa5774U, 0xb4606decU, 0x60b2bbe2U, 0xdc25ec1dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb74dfe6cU, 0x58a4881aU, 0xdfb7cc37U, 0x68be2144U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x5b5a3185U, 0xcc16c9e1U, 0x475a2a51U, 0x24641097U); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x8000e808U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000908U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00001000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x10feea38U, 0x5eaeaabbU, 0x77095c55U, 0x7093230cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xcb77246cU, 0xf50b975cU, 0x192667c9U, 0x26f329aaU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x1ecb55dcU, 0xa07467d4U, 0x8edc3285U, 0xcaa821a5U); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + R_SCE_func100(0xc2e9f5c6U, 0x19b2e504U, 0x78d20ba1U, 0xaf092443U); + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3420ab40U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xd5d2395dU, 0x1a14e0eeU, 0x7fa47423U, 0xe5808771U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x718cf94fU; + R_SCE_func101(0x64bce423U, 0x6906ed92U, 0x7f1aae29U, 0xd518fb2eU); + } + else + { + SCE->REG_28H = 0x00870001U; + R_SCE_func100(0xc6d33e0cU, 0x0251422aU, 0x264a38fcU, 0x635e213fU); + SCE->REG_2CH = 0x00000022U; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_7CH = 0x00000041U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000a84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00005113U; + SCE->REG_74H = 0x00001000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_74H = 0x00000004U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_74H = 0x00000002U; + SCE->REG_00H = 0x00000313U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00005313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000080U); + SCE->REG_A4H = 0x00000885U; + SCE->REG_00H = 0x00001313U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003113U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x01ad8717U; + R_SCE_func101(0x2a4556c4U, 0x547488aaU, 0xd3a532d8U, 0x4746621dU); + } + SCE->REG_ECH = 0x00003540U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000021U); + R_SCE_func101(0xe8194f49U, 0x85c9b90aU, 0x335790a1U, 0x59da6a33U); + R_SCE_func068(); + SCE->REG_ECH = 0x000034ffU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000082U); + R_SCE_func101(0xea2da884U, 0xd2ddc417U, 0x09114880U, 0xe11a6466U); + R_SCE_func044(); + R_SCE_func100(0x5078579fU, 0x620c4bcdU, 0x9e178c33U, 0xb9118fc9U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + R_SCE_func100(0x38d7769cU, 0x4ba65cf1U, 0xd0c80cf0U, 0x62bd77f1U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + OutData_KeyIndex[12] = SCE->REG_100H; + R_SCE_func100(0x69ee56a8U, 0xb5ad1016U, 0xc8e80a40U, 0xd8253bb3U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + R_SCE_func102(0x9cc904e3U, 0xcd140c8bU, 0x8bb84c75U, 0xdfbe9b9cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p5c_r4.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5d.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5d.c new file mode 100644 index 0000000000..6995c86a1e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5d.c @@ -0,0 +1,747 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_DlmsCosemCalculateKekSub(uint32_t *InData_KeyIndexType, uint32_t *InData_KeyIndex, uint32_t *InData_KDFType, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT, uint32_t *InData_SaltKeyIndex, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005d02U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005dU); + R_SCE_func101(0x7d1addb3U, 0x2057f3b8U, 0x9160b333U, 0x2551ed24U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x718cf94fU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005dU); + R_SCE_func101(0xe9851c96U, 0x1fd63f1eU, 0xfac6a708U, 0x3312765bU); + R_SCE_func044(); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x6ad1012fU, 0xd55e33d6U, 0x84da10daU, 0x6f52e33bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2eedcee1U, 0xfc1251bdU, 0xc75fa57eU, 0xcd14f0f9U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80020200U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[1]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800103e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KDFType[0]; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_7CH = 0x00000011U; + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_74H = 0x00000002U; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x49ad495aU, 0x8c87d651U, 0x3d56988eU, 0xf5decbf6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000054U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_00H = 0x00005323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81020200U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000464U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[2]; + SCE->REG_100H = InData_PaddedMsg[3]; + SCE->REG_100H = InData_PaddedMsg[4]; + SCE->REG_100H = InData_PaddedMsg[5]; + SCE->REG_100H = InData_PaddedMsg[6]; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 7; iLoop < MAX_CNT-7; iLoop = iLoop+16) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[iLoop + 0]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 1]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 2]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 3]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 4]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 5]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 6]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 7]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 8]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 9]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 10]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 11]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 12]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 13]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 14]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 15]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + R_SCE_func101(0xed4f005cU, 0x4bd8b063U, 0xbc8a39e2U, 0xe4972507U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SaltKeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000005dU); + R_SCE_func101(0x899496f9U, 0xe196ae97U, 0xc89579d4U, 0xff2042aeU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000001bU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000014U); + R_SCE_func101(0x21bd3ba3U, 0xace59435U, 0x2144095fU, 0xcbed6a94U); + R_SCE_func044(); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SaltKeyIndex[1]; + SCE->REG_100H = InData_SaltKeyIndex[2]; + SCE->REG_100H = InData_SaltKeyIndex[3]; + SCE->REG_100H = InData_SaltKeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SaltKeyIndex[5]; + SCE->REG_100H = InData_SaltKeyIndex[6]; + SCE->REG_100H = InData_SaltKeyIndex[7]; + SCE->REG_100H = InData_SaltKeyIndex[8]; + SCE->REG_E0H = 0x80080000U; + SCE->REG_00H = 0x00008223U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SaltKeyIndex[9]; + SCE->REG_100H = InData_SaltKeyIndex[10]; + SCE->REG_100H = InData_SaltKeyIndex[11]; + SCE->REG_100H = InData_SaltKeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x6ef83b2eU, 0xdff7fc1eU, 0x626672f8U, 0x06755467U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b780U; + SCE->REG_ECH = 0x00000001U; + R_SCE_func101(0x257e9a39U, 0xa8410bdaU, 0xa184d788U, 0xec6ce470U); + } + else + { + R_SCE_func001(); + SCE->REG_104H = 0x00000054U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_00H = 0x00005323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81020200U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000464U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[2]; + SCE->REG_100H = InData_PaddedMsg[3]; + SCE->REG_100H = InData_PaddedMsg[4]; + SCE->REG_100H = InData_PaddedMsg[5]; + SCE->REG_100H = InData_PaddedMsg[6]; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_104H = 0x000000b4U; + for (iLoop = 7; iLoop < MAX_CNT-7; iLoop = iLoop+16) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[iLoop + 0]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 1]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 2]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 3]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 4]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 5]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 6]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 7]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 8]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 9]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 10]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 11]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 12]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 13]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 14]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 15]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_74H = 0x00000002U; + R_SCE_func002(); + SCE->REG_00H = 0x00005323U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000054U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x80000000U); + SCE->REG_F8H = 0x00000040U; + SCE->REG_104H = 0x00000154U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000300U); + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_74H = 0x00000000U; + SCE->REG_1CH = 0x00001600U; + R_SCE_func101(0xd45fbaa4U, 0xd6b6a7dbU, 0xcb09a1fbU, 0x26188556U); + } + } + SCE->REG_ECH = 0x38000f9cU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x3816cfa4U, 0xa6fa0faaU, 0xb5459fbbU, 0x282936b1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb936bc32U, 0xb65915bbU, 0xc45b6d2eU, 0xe7498928U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x2b2e99dcU, 0xe776097bU, 0x5180886eU, 0xb5312f2eU); + R_SCE_func103(); + R_SCE_func100(0x86aa76c1U, 0x6271b792U, 0x5a03d80aU, 0x224c3c70U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010140U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81010140U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000081U); + R_SCE_func101(0xc3cbb51cU, 0x2f7aa6e5U, 0xbac139a2U, 0x6ebb4cdeU); + R_SCE_func068(); + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800103c0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndexType[0]; + SCE->REG_ECH = 0x300033c0U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x2a46c04bU; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x85d04999U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0xb6e3697fU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000081U); + R_SCE_func101(0x44ad26bbU, 0xaeaa3cc3U, 0xbf6bb0c7U, 0xf7b67c23U); + R_SCE_func044(); + SCE->REG_ECH = 0x38000fdeU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xd8ec021fU, 0x769b4c9eU, 0xb86cdc9aU, 0xc7568ab6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func100(0x52aeefd3U, 0xa30f9bcbU, 0xb9a2815cU, 0x2a23b288U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02e087b5U; + SCE->REG_00H = 0x00002513U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000513U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000352U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000001U); + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + R_SCE_func101(0x17d49992U, 0x1526ab6bU, 0x5b5abaefU, 0x512ad050U); + } + else + { + R_SCE_func100(0x3fdf81c7U, 0x9c20822fU, 0x0e12f06cU, 0xe0ea9f9bU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002523U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000352U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000002U); + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + OutData_KeyIndex[12] = SCE->REG_100H; + R_SCE_func101(0xf9aa64d8U, 0xa956b871U, 0x2f54cc87U, 0xa9a69c72U); + } + R_SCE_func102(0x4cf439b5U, 0x4daa3831U, 0x93e896fcU, 0x85fd331eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p5d_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p6f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p6f.c new file mode 100644 index 0000000000..7c32e87ef0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p6f.c @@ -0,0 +1,240 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_UpdateOemKeyIndexSub(uint32_t *InData_LC, uint32_t *InData_Cmd, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00006f02U; + SCE->REG_108H = 0x00000000U; + R_SCE_func048(InData_LC); + R_SCE_func049(InData_Cmd); + SCE->REG_ECH = 0x3420a800U; + SCE->REG_ECH = 0x00000009U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x000037e4U; + SCE->REG_ECH = 0x3420a880U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3420a880U; + SCE->REG_ECH = 0x00000024U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xd410979fU, 0x406e85c4U, 0x3ec02d1fU, 0xe047c6f9U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x89ccaed0U, 0x56724337U, 0x4e91391aU, 0x3c6b4627U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000349fU; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000006fU); + R_SCE_func101(0xe49bcc6eU, 0xf0c2338eU, 0xa1c8db1bU, 0x84c332f4U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000006fU); + R_SCE_func101(0xc2a81f72U, 0x2c0a16edU, 0x803fc568U, 0xd8fcd51aU); + R_SCE_func044(); + R_SCE_func100(0x37fb9978U, 0x51e6b046U, 0x27f17604U, 0xc663678dU); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[0+1 + 0]; + SCE->REG_100H = S_INST2[0+1 + 1]; + SCE->REG_100H = S_INST2[0+1 + 2]; + SCE->REG_100H = S_INST2[0+1 + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[0+5 + 0]; + SCE->REG_100H = S_INST2[0+5 + 1]; + SCE->REG_100H = S_INST2[0+5 + 2]; + SCE->REG_100H = S_INST2[0+5 + 3]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x9d9498c5U, 0x47395849U, 0x4354ff79U, 0xd893da46U); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[0+9 + 0]; + SCE->REG_100H = S_INST2[0+9 + 1]; + SCE->REG_100H = S_INST2[0+9 + 2]; + SCE->REG_100H = S_INST2[0+9 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010380U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000006fU); + R_SCE_func101(0xe7732816U, 0xd3a1a1b0U, 0x4af1ada7U, 0x8dd67b02U); + R_SCE_func057_r3(InData_IV,InData_InstData,OutData_KeyIndex); + R_SCE_func100(0xcfefe71eU, 0xf719a7a8U, 0xd7ae4eb6U, 0x9b3112a2U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x8ed15b56U, 0xac9d7d60U, 0x99256f0bU, 0x1347665cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x7a1086b7U, 0xd02d663bU, 0x467aef18U, 0x2611950dU); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + R_SCE_func102(0x4adff803U, 0x6cba76f9U, 0x44237a97U, 0x9271f894U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p6f_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p72.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p72.c new file mode 100644 index 0000000000..0ff312582f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p72.c @@ -0,0 +1,148 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Sha224256GenerateMessageDigestSub(const uint32_t *InData_InitVal, const uint32_t *InData_PaddedMsg, const uint32_t MAX_CNT, uint32_t *OutData_MsgDigest) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007201U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0xfb2b56d5U, 0xe26d4898U, 0x26103057U, 0x276b6c33U); + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000764U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InitVal[0]; + SCE->REG_100H = InData_InitVal[1]; + SCE->REG_100H = InData_InitVal[2]; + SCE->REG_100H = InData_InitVal[3]; + SCE->REG_100H = InData_InitVal[4]; + SCE->REG_100H = InData_InitVal[5]; + SCE->REG_100H = InData_InitVal[6]; + SCE->REG_100H = InData_InitVal[7]; + SCE->REG_104H = 0x000000b4U; + SCE->REG_74H = 0x08000002U; + for (iLoop = 0; iLoop < MAX_CNT ; iLoop = iLoop + 16) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 0]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 1]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 2]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 3]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 4]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 5]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 6]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 7]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 8]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 9]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 10]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 11]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 12]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 13]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 14]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 15]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_74H = 0x00000000U; + SCE->REG_104H = 0x00000000U; + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000008U; + SCE->REG_04H = 0x00000523U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MsgDigest[0] = SCE->REG_100H; + OutData_MsgDigest[1] = SCE->REG_100H; + OutData_MsgDigest[2] = SCE->REG_100H; + OutData_MsgDigest[3] = SCE->REG_100H; + OutData_MsgDigest[4] = SCE->REG_100H; + OutData_MsgDigest[5] = SCE->REG_100H; + OutData_MsgDigest[6] = SCE->REG_100H; + OutData_MsgDigest[7] = SCE->REG_100H; + R_SCE_func102(0x6a815b4bU, 0xce37585cU, 0x5c537d01U, 0x83023271U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p72.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76f.c new file mode 100644 index 0000000000..662d75ad1a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76f.c @@ -0,0 +1,311 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Sha256HmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_MAC, uint32_t *InData_length, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_74H = 0x00000000U; + SCE->REG_28H = 0x00870001U; + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_74H = 0x00000002U; + R_SCE_func002(); + SCE->REG_00H = 0x00005323U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000054U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x80000000U); + SCE->REG_F8H = 0x00000040U; + SCE->REG_104H = 0x00000154U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000300U); + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_74H = 0x00000000U; + SCE->REG_1CH = 0x00001600U; + SCE->REG_E0H = 0x80010000U; + SCE->REG_104H = 0x00000068U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x38000c00U; + SCE->REG_ECH = 0x1000b780U; + SCE->REG_ECH = 0x00002000U; + SCE->REG_ECH = 0x2000b780U; + SCE->REG_ECH = 0x00001000U; + SCE->REG_ECH = 0x38000f9bU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x8ed66e4dU, 0x615bc8d3U, 0x8a006271U, 0x7d6cfe05U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x0f463b4dU, 0x16904ff1U, 0xd88fe44bU, 0x04b5ff30U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xf518bd90U, 0xd723455eU, 0xa4c21b91U, 0xe70a347cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func100(0x6c3eda06U, 0xfabde0adU, 0xb0a7a91bU, 0x14627794U); + SCE->REG_74H = 0x00000008U; + SCE->REG_04H = 0x00000523U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + OutData_MAC[4] = SCE->REG_100H; + OutData_MAC[5] = SCE->REG_100H; + OutData_MAC[6] = SCE->REG_100H; + OutData_MAC[7] = SCE->REG_100H; + R_SCE_func102(0x7632454fU, 0xd66a870dU, 0x37b6ae62U, 0xca4a4017U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_length[0]; + SCE->REG_ECH = 0x3420a820U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3420a820U; + SCE->REG_ECH = 0x00000021U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x9bba432fU, 0x90ff31d8U, 0xd20bc5ebU, 0x3bad6d87U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x25dc0061U, 0xe51833a0U, 0x33b95ac2U, 0x909bf44bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008523U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000800U; + for (iLoop = 0; iLoop < 32; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be1U; + SCE->REG_ECH = 0x12003c1fU; + SCE->REG_ECH = 0x00002fe0U; + } + SCE->REG_A4H = 0x00040805U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00050805U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000761U; + SCE->REG_A4H = 0x00900c05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[4]; + SCE->REG_100H = InData_MAC[5]; + SCE->REG_100H = InData_MAC[6]; + SCE->REG_100H = InData_MAC[7]; + R_SCE_func100(0x29c4a913U, 0xa12e9e66U, 0x89c4a9d0U, 0x54429e24U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x6b8cef9cU, 0x78c8da32U, 0x10d7f8b7U, 0x46c192d6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func102(0xd8d9c817U, 0x307becf7U, 0xd9349aabU, 0x873ecdf7U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p76f_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76i.c new file mode 100644 index 0000000000..3fe97d75bd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76i.c @@ -0,0 +1,373 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t LEN) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)LEN; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007602U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x70dc952bU, 0x54422a49U, 0x86f2fd91U, 0x8699a61aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x7d782132U, 0x1532f59bU, 0xc9b6e0d7U, 0x592428adU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000076U); + R_SCE_func101(0x2e28f293U, 0x6199463aU, 0xbd5272ebU, 0x96b497beU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000001bU; + R_SCE_func101(0x9b59b4b5U, 0x3320a5f1U, 0xb939e0d9U, 0xd8223c7aU); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000076U); + R_SCE_func101(0xb4d445cbU, 0xd826d0e0U, 0xfd9c8557U, 0x2c2cf69dU); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0xb6e3697fU; + R_SCE_func101(0x13118bc2U, 0x5157aa61U, 0x563d7209U, 0x9afc5692U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000076U); + R_SCE_func101(0x51cd5a22U, 0x73e30194U, 0xaf356ffaU, 0x9cc8ee2dU); + R_SCE_func044(); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_E0H = 0x80080000U; + SCE->REG_00H = 0x00008223U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b760U; + SCE->REG_ECH = 0x00003000U; + R_SCE_func101(0x416bc19fU, 0x57bd535aU, 0x4a579fa6U, 0x45581fa8U); + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00020000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x38008fe0U; + SCE->REG_ECH = 0x00003000U; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x00003760U; + SCE->REG_ECH = 0x00008f60U; + SCE->REG_ECH = 0x00003000U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000feU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000076U); + R_SCE_func101(0xb023b717U, 0xe6a42f61U, 0x7bd1ddc0U, 0x6b0f78f1U); + R_SCE_func059(); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_E0H = 0x80080000U; + SCE->REG_00H = 0x00008223U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xfb45654cU, 0x8501e5b9U, 0xc738b67cU, 0x5928b899U); + } + R_SCE_func100(0x3b3bbc10U, 0xd46829afU, 0x53e5257aU, 0xa520ca05U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x82609309U, 0x00068e21U, 0x9cee145dU, 0x6caff82eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_74H = 0x00000002U; + R_SCE_func001(); + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p76i_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76u.c new file mode 100644 index 0000000000..190c351ad5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76u.c @@ -0,0 +1,70 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Sha256HmacUpdateSub(uint32_t *InData_PaddedMsg, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func000(InData_PaddedMsg, (int32_t)MAX_CNT); + R_SCE_func101(0xc7a82f5dU, 0x7a795eecU, 0x006a8ae6U, 0x188736f0U); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p76u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p79.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p79.c new file mode 100644 index 0000000000..d5f0764a7d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p79.c @@ -0,0 +1,829 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Rsa3072ModularExponentEncryptSub(uint32_t *InData_KeyIndex, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007903U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000079U); + R_SCE_func101(0x0094c566U, 0x10986435U, 0x9f31addfU, 0xc8301f32U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000000eU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000079U); + R_SCE_func101(0xf5d62600U, 0xb1abe549U, 0x6a33cbc3U, 0xd04a30cbU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00006362U; + SCE->REG_D0H = 0x40001800U; + SCE->REG_C4H = 0x02e08887U; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + for(iLoop=0; iLoop<32; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + for(iLoop=32; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + for(iLoop=64; iLoop<96; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_E0H = 0x80010280U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 3]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x2bd4de17U, 0x936d99ffU, 0x2fa1d6b0U, 0x6693146dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2691e276U, 0x93a1552aU, 0xf28c0224U, 0xd2253a99U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0xcae1ea65U, 0xf76049bfU, 0xbb4332b1U, 0x971fd234U); + R_SCE_func103(); + R_SCE_func100(0x90487217U, 0xc7b0affcU, 0x026e5761U, 0xb1a55416U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x010c0c04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x8608f20bU, 0xb5bdb91dU, 0xb8c153d9U, 0x05083d7aU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cU); + R_SCE_func080(); + R_SCE_func100(0xd925b2baU, 0x5f87235fU, 0x4cb02c53U, 0xc5a41b88U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(752); + R_SCE_func100(0xba8fe304U, 0x822c1026U, 0x1577ad01U, 0xd78a2a1cU); + R_SCE_func314(752+32); + R_SCE_func100(0x57e81972U, 0xcfec4cb2U, 0x412b52a2U, 0x785da8f7U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + R_SCE_func100(0xa58363ffU, 0xa1ab3397U, 0x83965bcbU, 0x6830d52fU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func319(716); + R_SCE_func100(0x2c41d291U, 0x8e8520a0U, 0x25501a9fU, 0xd841477eU); + R_SCE_func314(716+32); + R_SCE_func100(0x018c1b2bU, 0xed8b7d12U, 0x4a5be87eU, 0xfe509361U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0x968273c9U, 0x99dbcfc1U, 0xab022f11U, 0x6c2b9e0dU); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func319(680); + R_SCE_func100(0xe14b6150U, 0xb6403443U, 0x22f77d54U, 0x9c08de82U); + R_SCE_func314(680+32); + SCE->REG_00H = 0x0000037fU; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x800103e0U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3800dbe0U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00001f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_2CH = 0x00000014U; + SCE->REG_104H = 0x00003f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[32]; + SCE->REG_100H = InData_Text[33]; + SCE->REG_100H = InData_Text[34]; + SCE->REG_100H = InData_Text[35]; + SCE->REG_100H = InData_Text[36]; + SCE->REG_100H = InData_Text[37]; + SCE->REG_100H = InData_Text[38]; + SCE->REG_100H = InData_Text[39]; + SCE->REG_100H = InData_Text[40]; + SCE->REG_100H = InData_Text[41]; + SCE->REG_100H = InData_Text[42]; + SCE->REG_100H = InData_Text[43]; + SCE->REG_100H = InData_Text[44]; + SCE->REG_100H = InData_Text[45]; + SCE->REG_100H = InData_Text[46]; + SCE->REG_100H = InData_Text[47]; + SCE->REG_100H = InData_Text[48]; + SCE->REG_100H = InData_Text[49]; + SCE->REG_100H = InData_Text[50]; + SCE->REG_100H = InData_Text[51]; + SCE->REG_100H = InData_Text[52]; + SCE->REG_100H = InData_Text[53]; + SCE->REG_100H = InData_Text[54]; + SCE->REG_100H = InData_Text[55]; + SCE->REG_100H = InData_Text[56]; + SCE->REG_100H = InData_Text[57]; + SCE->REG_100H = InData_Text[58]; + SCE->REG_100H = InData_Text[59]; + SCE->REG_100H = InData_Text[60]; + SCE->REG_100H = InData_Text[61]; + SCE->REG_100H = InData_Text[62]; + SCE->REG_100H = InData_Text[63]; + SCE->REG_100H = InData_Text[64]; + SCE->REG_100H = InData_Text[65]; + SCE->REG_100H = InData_Text[66]; + SCE->REG_100H = InData_Text[67]; + SCE->REG_100H = InData_Text[68]; + SCE->REG_100H = InData_Text[69]; + SCE->REG_100H = InData_Text[70]; + SCE->REG_100H = InData_Text[71]; + SCE->REG_100H = InData_Text[72]; + SCE->REG_100H = InData_Text[73]; + SCE->REG_100H = InData_Text[74]; + SCE->REG_100H = InData_Text[75]; + SCE->REG_100H = InData_Text[76]; + SCE->REG_100H = InData_Text[77]; + SCE->REG_100H = InData_Text[78]; + SCE->REG_100H = InData_Text[79]; + SCE->REG_100H = InData_Text[80]; + SCE->REG_100H = InData_Text[81]; + SCE->REG_100H = InData_Text[82]; + SCE->REG_100H = InData_Text[83]; + SCE->REG_100H = InData_Text[84]; + SCE->REG_100H = InData_Text[85]; + SCE->REG_100H = InData_Text[86]; + SCE->REG_100H = InData_Text[87]; + SCE->REG_100H = InData_Text[88]; + SCE->REG_100H = InData_Text[89]; + SCE->REG_100H = InData_Text[90]; + SCE->REG_100H = InData_Text[91]; + SCE->REG_100H = InData_Text[92]; + SCE->REG_100H = InData_Text[93]; + SCE->REG_100H = InData_Text[94]; + SCE->REG_100H = InData_Text[95]; + SCE->REG_28H = 0x009f0001U; + R_SCE_func100(0x334d09ccU, 0x2524049aU, 0xa6f0a0ecU, 0x7a2115e4U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420U); + R_SCE_func080(); + R_SCE_func100(0x86fb7a96U, 0xbe6bdc21U, 0xf5ecf8dbU, 0xc0c6b984U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func319(72); + R_SCE_func100(0x840fdf71U, 0x1f169255U, 0xa1b1efb1U, 0x555756faU); + R_SCE_func314(72+32); + R_SCE_func100(0xe836c33eU, 0x66ba0d4cU, 0xd379eb0fU, 0x1232fef2U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4U); + R_SCE_func080(); + R_SCE_func100(0x920ec563U, 0x76061a03U, 0x67937367U, 0x8eef3d82U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000025U; + R_SCE_func319(36); + R_SCE_func100(0x9389e6faU, 0x789df45aU, 0xa3481096U, 0xe82b4249U); + R_SCE_func314(36+32); + R_SCE_func100(0xfdf89268U, 0x4102be99U, 0x640574b3U, 0xf35decb6U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091U); + R_SCE_func080(); + R_SCE_func100(0x0a829422U, 0x66823532U, 0x273db663U, 0x40cf4369U); + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func319(0); + R_SCE_func100(0x22e4d97eU, 0xa11d4053U, 0xef031ce3U, 0xc4fc54c9U); + R_SCE_func314(0+32); + R_SCE_func100(0x2bbb753cU, 0xfecdf56fU, 0x57596fa1U, 0x66aaa8a7U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000040d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00a10000U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfU); + R_SCE_func080(); + R_SCE_func100(0x7a022d1dU, 0xccdb45d5U, 0x0fcb103eU, 0x6ff16ea3U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(680); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4U); + R_SCE_func080(); + R_SCE_func100(0x14a62edbU, 0x079a9d1eU, 0x2d13b4c4U, 0x20b1211cU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000011U; + R_SCE_func320(716); + SCE->REG_24H = 0x000016c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cU); + R_SCE_func080(); + R_SCE_func100(0xe69ca1b6U, 0xfbe4980aU, 0xeb9f822aU, 0x4342a555U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func320(752); + SCE->REG_24H = 0x000060d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x000080d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091U); + R_SCE_func080(); + R_SCE_func100(0x779f0ef9U, 0xe57d33bcU, 0x1da42781U, 0xf33ec00aU); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func320(0); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4U); + R_SCE_func080(); + R_SCE_func100(0x8b2c605eU, 0x0044090bU, 0x5b2c5203U, 0x95272c73U); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000015U; + R_SCE_func320(36); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420U); + R_SCE_func080(); + SCE->REG_00H = 0x00003283U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func320(72); + SCE->REG_24H = 0x0000a0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001U; + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xd32f396bU, 0xe0e4b72eU, 0x9066e0a4U, 0xaeabb5efU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x94bcd5e6U, 0xaee6e985U, 0xf19fcc91U, 0x71b9e9e6U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000079U; + R_SCE_func101(0xf53c859fU, 0x88e5bcc8U, 0x4a2d21a2U, 0xb21edb0aU); + R_SCE_func325_r1(); + SCE->REG_28H = 0x009f0001U; + R_SCE_func100(0xa2e7d0afU, 0xbd515886U, 0x04c2396aU, 0xf20f30eaU); + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000382U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func100(0xdebd9710U, 0x790c4a14U, 0x530cf67fU, 0x69c3affaU); + SCE->REG_2CH = 0x00000022U; + SCE->REG_04H = 0x00000302U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[32] = SCE->REG_100H; + OutData_Text[33] = SCE->REG_100H; + OutData_Text[34] = SCE->REG_100H; + OutData_Text[35] = SCE->REG_100H; + OutData_Text[36] = SCE->REG_100H; + OutData_Text[37] = SCE->REG_100H; + OutData_Text[38] = SCE->REG_100H; + OutData_Text[39] = SCE->REG_100H; + OutData_Text[40] = SCE->REG_100H; + OutData_Text[41] = SCE->REG_100H; + OutData_Text[42] = SCE->REG_100H; + OutData_Text[43] = SCE->REG_100H; + OutData_Text[44] = SCE->REG_100H; + OutData_Text[45] = SCE->REG_100H; + OutData_Text[46] = SCE->REG_100H; + OutData_Text[47] = SCE->REG_100H; + OutData_Text[48] = SCE->REG_100H; + OutData_Text[49] = SCE->REG_100H; + OutData_Text[50] = SCE->REG_100H; + OutData_Text[51] = SCE->REG_100H; + OutData_Text[52] = SCE->REG_100H; + OutData_Text[53] = SCE->REG_100H; + OutData_Text[54] = SCE->REG_100H; + OutData_Text[55] = SCE->REG_100H; + OutData_Text[56] = SCE->REG_100H; + OutData_Text[57] = SCE->REG_100H; + OutData_Text[58] = SCE->REG_100H; + OutData_Text[59] = SCE->REG_100H; + OutData_Text[60] = SCE->REG_100H; + OutData_Text[61] = SCE->REG_100H; + OutData_Text[62] = SCE->REG_100H; + OutData_Text[63] = SCE->REG_100H; + OutData_Text[64] = SCE->REG_100H; + OutData_Text[65] = SCE->REG_100H; + OutData_Text[66] = SCE->REG_100H; + OutData_Text[67] = SCE->REG_100H; + OutData_Text[68] = SCE->REG_100H; + OutData_Text[69] = SCE->REG_100H; + OutData_Text[70] = SCE->REG_100H; + OutData_Text[71] = SCE->REG_100H; + OutData_Text[72] = SCE->REG_100H; + OutData_Text[73] = SCE->REG_100H; + OutData_Text[74] = SCE->REG_100H; + OutData_Text[75] = SCE->REG_100H; + OutData_Text[76] = SCE->REG_100H; + OutData_Text[77] = SCE->REG_100H; + OutData_Text[78] = SCE->REG_100H; + OutData_Text[79] = SCE->REG_100H; + OutData_Text[80] = SCE->REG_100H; + OutData_Text[81] = SCE->REG_100H; + OutData_Text[82] = SCE->REG_100H; + OutData_Text[83] = SCE->REG_100H; + OutData_Text[84] = SCE->REG_100H; + OutData_Text[85] = SCE->REG_100H; + OutData_Text[86] = SCE->REG_100H; + OutData_Text[87] = SCE->REG_100H; + OutData_Text[88] = SCE->REG_100H; + OutData_Text[89] = SCE->REG_100H; + OutData_Text[90] = SCE->REG_100H; + OutData_Text[91] = SCE->REG_100H; + OutData_Text[92] = SCE->REG_100H; + OutData_Text[93] = SCE->REG_100H; + OutData_Text[94] = SCE->REG_100H; + OutData_Text[95] = SCE->REG_100H; + R_SCE_func102(0x49e2f88cU, 0x05b4f64eU, 0xec164a7bU, 0x0f11324eU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p79_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p7b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p7b.c new file mode 100644 index 0000000000..3eed3edb3f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p7b.c @@ -0,0 +1,785 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007b03U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000007bU); + R_SCE_func101(0x7ad72a9bU, 0xc0d644cbU, 0xfaca9314U, 0x11bbba6bU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000007bU); + R_SCE_func101(0x205a7830U, 0x6c4a6d70U, 0xc9421de4U, 0xbf1d257eU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00007f62U; + SCE->REG_D0H = 0x40001f00U; + SCE->REG_C4H = 0x02e08887U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + for(iLoop=64; iLoop<128; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e08885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_E0H = 0x80010280U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 3]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xb7f64b98U, 0xce8be4f2U, 0xdaecb29fU, 0xba4bee57U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x38f2ba28U, 0x7b5fd1f3U, 0x2cf26fd2U, 0xc1024f2fU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x5dcd5dc9U, 0x76547c90U, 0x8501b35bU, 0x48978d2eU); + R_SCE_func103(); + R_SCE_func100(0x8e5ab704U, 0xd3215d65U, 0xf6885c91U, 0xf9dc448eU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x010c0c04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x022fb9d2U, 0x81775805U, 0xda776150U, 0x273acd23U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7U); + R_SCE_func080(); + R_SCE_func100(0xb68fe435U, 0x408234a3U, 0x7502469dU, 0x151fa101U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(748); + R_SCE_func100(0xf7b240d4U, 0x5d10b4a0U, 0xe463f3acU, 0xffa56053U); + R_SCE_func314(748+64); + R_SCE_func100(0x2295a160U, 0xab9ce977U, 0x5025c0c8U, 0x36815466U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9U); + R_SCE_func080(); + R_SCE_func100(0x795c26baU, 0xf985e8b5U, 0x4f24dd66U, 0xc556109bU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + R_SCE_func313(680); + R_SCE_func100(0x8344f51cU, 0x970d22abU, 0x026ab0a7U, 0xbdf9063bU); + R_SCE_func314(680+64); + SCE->REG_00H = 0x000003ffU; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x800103e0U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3800dbe0U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xd2a1b049U, 0x70be50b2U, 0x7fa58ad6U, 0xfe642e4cU); + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00003f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_100H = InData_Text[32]; + SCE->REG_100H = InData_Text[33]; + SCE->REG_100H = InData_Text[34]; + SCE->REG_100H = InData_Text[35]; + SCE->REG_100H = InData_Text[36]; + SCE->REG_100H = InData_Text[37]; + SCE->REG_100H = InData_Text[38]; + SCE->REG_100H = InData_Text[39]; + SCE->REG_100H = InData_Text[40]; + SCE->REG_100H = InData_Text[41]; + SCE->REG_100H = InData_Text[42]; + SCE->REG_100H = InData_Text[43]; + SCE->REG_100H = InData_Text[44]; + SCE->REG_100H = InData_Text[45]; + SCE->REG_100H = InData_Text[46]; + SCE->REG_100H = InData_Text[47]; + SCE->REG_100H = InData_Text[48]; + SCE->REG_100H = InData_Text[49]; + SCE->REG_100H = InData_Text[50]; + SCE->REG_100H = InData_Text[51]; + SCE->REG_100H = InData_Text[52]; + SCE->REG_100H = InData_Text[53]; + SCE->REG_100H = InData_Text[54]; + SCE->REG_100H = InData_Text[55]; + SCE->REG_100H = InData_Text[56]; + SCE->REG_100H = InData_Text[57]; + SCE->REG_100H = InData_Text[58]; + SCE->REG_100H = InData_Text[59]; + SCE->REG_100H = InData_Text[60]; + SCE->REG_100H = InData_Text[61]; + SCE->REG_100H = InData_Text[62]; + SCE->REG_100H = InData_Text[63]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bU); + R_SCE_func080(); + R_SCE_func100(0xd4b4e6e1U, 0xa785f78bU, 0x6c79a84dU, 0x7d23f718U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + R_SCE_func313(68); + R_SCE_func100(0xffa9408cU, 0x5afbfcf1U, 0xccb0ac56U, 0xb77df063U); + R_SCE_func314(68+64); + R_SCE_func100(0x25d15aabU, 0x77aa55a3U, 0x099062d6U, 0x88f4f775U); + SCE->REG_2CH = 0x00000014U; + SCE->REG_104H = 0x00003f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[64]; + SCE->REG_100H = InData_Text[65]; + SCE->REG_100H = InData_Text[66]; + SCE->REG_100H = InData_Text[67]; + SCE->REG_100H = InData_Text[68]; + SCE->REG_100H = InData_Text[69]; + SCE->REG_100H = InData_Text[70]; + SCE->REG_100H = InData_Text[71]; + SCE->REG_100H = InData_Text[72]; + SCE->REG_100H = InData_Text[73]; + SCE->REG_100H = InData_Text[74]; + SCE->REG_100H = InData_Text[75]; + SCE->REG_100H = InData_Text[76]; + SCE->REG_100H = InData_Text[77]; + SCE->REG_100H = InData_Text[78]; + SCE->REG_100H = InData_Text[79]; + SCE->REG_100H = InData_Text[80]; + SCE->REG_100H = InData_Text[81]; + SCE->REG_100H = InData_Text[82]; + SCE->REG_100H = InData_Text[83]; + SCE->REG_100H = InData_Text[84]; + SCE->REG_100H = InData_Text[85]; + SCE->REG_100H = InData_Text[86]; + SCE->REG_100H = InData_Text[87]; + SCE->REG_100H = InData_Text[88]; + SCE->REG_100H = InData_Text[89]; + SCE->REG_100H = InData_Text[90]; + SCE->REG_100H = InData_Text[91]; + SCE->REG_100H = InData_Text[92]; + SCE->REG_100H = InData_Text[93]; + SCE->REG_100H = InData_Text[94]; + SCE->REG_100H = InData_Text[95]; + SCE->REG_100H = InData_Text[96]; + SCE->REG_100H = InData_Text[97]; + SCE->REG_100H = InData_Text[98]; + SCE->REG_100H = InData_Text[99]; + SCE->REG_100H = InData_Text[100]; + SCE->REG_100H = InData_Text[101]; + SCE->REG_100H = InData_Text[102]; + SCE->REG_100H = InData_Text[103]; + SCE->REG_100H = InData_Text[104]; + SCE->REG_100H = InData_Text[105]; + SCE->REG_100H = InData_Text[106]; + SCE->REG_100H = InData_Text[107]; + SCE->REG_100H = InData_Text[108]; + SCE->REG_100H = InData_Text[109]; + SCE->REG_100H = InData_Text[110]; + SCE->REG_100H = InData_Text[111]; + SCE->REG_100H = InData_Text[112]; + SCE->REG_100H = InData_Text[113]; + SCE->REG_100H = InData_Text[114]; + SCE->REG_100H = InData_Text[115]; + SCE->REG_100H = InData_Text[116]; + SCE->REG_100H = InData_Text[117]; + SCE->REG_100H = InData_Text[118]; + SCE->REG_100H = InData_Text[119]; + SCE->REG_100H = InData_Text[120]; + SCE->REG_100H = InData_Text[121]; + SCE->REG_100H = InData_Text[122]; + SCE->REG_100H = InData_Text[123]; + SCE->REG_100H = InData_Text[124]; + SCE->REG_100H = InData_Text[125]; + SCE->REG_100H = InData_Text[126]; + SCE->REG_100H = InData_Text[127]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7aU); + R_SCE_func080(); + R_SCE_func100(0x38359f99U, 0x72026843U, 0x34de71ddU, 0xeb37ea65U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + R_SCE_func313(0); + R_SCE_func100(0x5207d298U, 0x39dcd15dU, 0x680983ceU, 0xb6628fd8U); + R_SCE_func314(0+64); + R_SCE_func100(0x4dd8e7c0U, 0x0c001f8fU, 0x9cc0ac77U, 0xc283a6d8U); + SCE->REG_24H = 0x000040d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00a10000U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9U); + R_SCE_func080(); + R_SCE_func100(0xd40fcc2eU, 0x9ade18b0U, 0x8545ef60U, 0xe90f552aU); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(680); + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7U); + R_SCE_func080(); + R_SCE_func100(0x0cf3ad46U, 0xd701fb04U, 0xbdac7452U, 0x6eb22107U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + R_SCE_func312(748); + SCE->REG_24H = 0x000080d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7aU); + R_SCE_func080(); + R_SCE_func100(0x527b0f66U, 0x887690e8U, 0x7aa948f6U, 0xa84eb5e8U); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + R_SCE_func312(0); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bU); + R_SCE_func080(); + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000010U; + R_SCE_func312(68); + SCE->REG_24H = 0x04001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x8616b1c2U, 0xf15b1d65U, 0x0b519337U, 0x546a6a9bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x306d1ceaU, 0x8538343eU, 0x71f1a4c7U, 0x29c40b79U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x0000007bU; + R_SCE_func101(0x6d2f8001U, 0x84e44900U, 0xefad9bb2U, 0x7eae5acdU); + R_SCE_func307_r1(); + R_SCE_func100(0xc9dbdeffU, 0x9dc1302aU, 0x9293827eU, 0xa2d5d039U); + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000302U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + OutData_Text[32] = SCE->REG_100H; + OutData_Text[33] = SCE->REG_100H; + OutData_Text[34] = SCE->REG_100H; + OutData_Text[35] = SCE->REG_100H; + OutData_Text[36] = SCE->REG_100H; + OutData_Text[37] = SCE->REG_100H; + OutData_Text[38] = SCE->REG_100H; + OutData_Text[39] = SCE->REG_100H; + OutData_Text[40] = SCE->REG_100H; + OutData_Text[41] = SCE->REG_100H; + OutData_Text[42] = SCE->REG_100H; + OutData_Text[43] = SCE->REG_100H; + OutData_Text[44] = SCE->REG_100H; + OutData_Text[45] = SCE->REG_100H; + OutData_Text[46] = SCE->REG_100H; + OutData_Text[47] = SCE->REG_100H; + OutData_Text[48] = SCE->REG_100H; + OutData_Text[49] = SCE->REG_100H; + OutData_Text[50] = SCE->REG_100H; + OutData_Text[51] = SCE->REG_100H; + OutData_Text[52] = SCE->REG_100H; + OutData_Text[53] = SCE->REG_100H; + OutData_Text[54] = SCE->REG_100H; + OutData_Text[55] = SCE->REG_100H; + OutData_Text[56] = SCE->REG_100H; + OutData_Text[57] = SCE->REG_100H; + OutData_Text[58] = SCE->REG_100H; + OutData_Text[59] = SCE->REG_100H; + OutData_Text[60] = SCE->REG_100H; + OutData_Text[61] = SCE->REG_100H; + OutData_Text[62] = SCE->REG_100H; + OutData_Text[63] = SCE->REG_100H; + R_SCE_func100(0xf1ec3171U, 0x776ebc7aU, 0xefbfa3baU, 0x9ea08d5eU); + SCE->REG_2CH = 0x00000022U; + SCE->REG_04H = 0x00000302U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[64] = SCE->REG_100H; + OutData_Text[65] = SCE->REG_100H; + OutData_Text[66] = SCE->REG_100H; + OutData_Text[67] = SCE->REG_100H; + OutData_Text[68] = SCE->REG_100H; + OutData_Text[69] = SCE->REG_100H; + OutData_Text[70] = SCE->REG_100H; + OutData_Text[71] = SCE->REG_100H; + OutData_Text[72] = SCE->REG_100H; + OutData_Text[73] = SCE->REG_100H; + OutData_Text[74] = SCE->REG_100H; + OutData_Text[75] = SCE->REG_100H; + OutData_Text[76] = SCE->REG_100H; + OutData_Text[77] = SCE->REG_100H; + OutData_Text[78] = SCE->REG_100H; + OutData_Text[79] = SCE->REG_100H; + OutData_Text[80] = SCE->REG_100H; + OutData_Text[81] = SCE->REG_100H; + OutData_Text[82] = SCE->REG_100H; + OutData_Text[83] = SCE->REG_100H; + OutData_Text[84] = SCE->REG_100H; + OutData_Text[85] = SCE->REG_100H; + OutData_Text[86] = SCE->REG_100H; + OutData_Text[87] = SCE->REG_100H; + OutData_Text[88] = SCE->REG_100H; + OutData_Text[89] = SCE->REG_100H; + OutData_Text[90] = SCE->REG_100H; + OutData_Text[91] = SCE->REG_100H; + OutData_Text[92] = SCE->REG_100H; + OutData_Text[93] = SCE->REG_100H; + OutData_Text[94] = SCE->REG_100H; + OutData_Text[95] = SCE->REG_100H; + OutData_Text[96] = SCE->REG_100H; + OutData_Text[97] = SCE->REG_100H; + OutData_Text[98] = SCE->REG_100H; + OutData_Text[99] = SCE->REG_100H; + OutData_Text[100] = SCE->REG_100H; + OutData_Text[101] = SCE->REG_100H; + OutData_Text[102] = SCE->REG_100H; + OutData_Text[103] = SCE->REG_100H; + OutData_Text[104] = SCE->REG_100H; + OutData_Text[105] = SCE->REG_100H; + OutData_Text[106] = SCE->REG_100H; + OutData_Text[107] = SCE->REG_100H; + OutData_Text[108] = SCE->REG_100H; + OutData_Text[109] = SCE->REG_100H; + OutData_Text[110] = SCE->REG_100H; + OutData_Text[111] = SCE->REG_100H; + OutData_Text[112] = SCE->REG_100H; + OutData_Text[113] = SCE->REG_100H; + OutData_Text[114] = SCE->REG_100H; + OutData_Text[115] = SCE->REG_100H; + OutData_Text[116] = SCE->REG_100H; + OutData_Text[117] = SCE->REG_100H; + OutData_Text[118] = SCE->REG_100H; + OutData_Text[119] = SCE->REG_100H; + OutData_Text[120] = SCE->REG_100H; + OutData_Text[121] = SCE->REG_100H; + OutData_Text[122] = SCE->REG_100H; + OutData_Text[123] = SCE->REG_100H; + OutData_Text[124] = SCE->REG_100H; + OutData_Text[125] = SCE->REG_100H; + OutData_Text[126] = SCE->REG_100H; + OutData_Text[127] = SCE->REG_100H; + R_SCE_func102(0xcea23837U, 0x87b642a5U, 0x5c40ed39U, 0xd3083ffeU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p7b_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p81.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p81.c new file mode 100644 index 0000000000..ce76108d1e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p81.c @@ -0,0 +1,126 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_SelfCheck1Sub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_SelfCheck1SubSub(); + + SCE->REG_138H = 0xf597806AU; + SCE->REG_F0H = 0x00000000U; + SCE->REG_04H = 0x00000001U; + SCE->REG_10CH = 0x0010057bU; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_80H = 0x00000001U; + SCE->REG_28H = 0x00000001U; + SCE->REG_7CH = 0x00000001U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_84H = 0x00018101U; + SCE->REG_13CH = 0x00000F00U; + SCE->REG_88H = 0x00008003U; + SCE->REG_104H = 0x00000352U; + R_SCE_func101(change_endian_long(0xa96bc3beU), change_endian_long(0xbe184d62U), change_endian_long(0x8b01907dU), change_endian_long(0x40a6b77bU)); + SCE->REG_88H = 0x00000000U; + SCE->REG_104H = 0x00000352U; + SCE->REG_C4H = 0x000f3a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x89eef104U; + SCE->REG_100H = 0x27cb57f1U; + SCE->REG_100H = 0x4e73d8edU; + SCE->REG_100H = 0xdf279f2dU; + R_SCE_func101(change_endian_long(0x42e60ac9U), change_endian_long(0xf0aac65aU), change_endian_long(0xf1ebbe17U), change_endian_long(0x8b8c3583U)); + R_SCE_func100(change_endian_long(0xec22205dU), change_endian_long(0xe603d843U), change_endian_long(0x38af658dU), change_endian_long(0x263a7d69U)); + SCE->REG_04H = 0x00001001U; + SCE->REG_1D0H = 0x00000000U; + if (0U == (SCE->REG_18H_b.B13)) + { + SCE->REG_1BCH = 0x00000020U; + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_08H = 0x0000FFFFU; + SCE->REG_13CH = 0x00000220U; + R_SCE_func102(change_endian_long(0xd809d6d2U), change_endian_long(0x14972febU), change_endian_long(0x5bfb7e32U), change_endian_long(0xa7987feaU)); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p81.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p82.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p82.c new file mode 100644 index 0000000000..e0689bab42 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p82.c @@ -0,0 +1,340 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_SelfCheck2Sub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008202U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00093b8cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01c7ba56U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00070804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x3000a820U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x00010020U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x00000080U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00002008U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_ECH = 0x00000013U; + SCE->REG_ECH = 0x0000b620U; + SCE->REG_ECH = 0x00000355U; + for(jLoop = 0; jLoop < 2; jLoop = jLoop + 1) + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020905cU; + SCE->REG_C4H = 0x41001e5eU; + SCE->REG_00H = 0x80002401U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001200U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B30) + { + /* waiting */ + } + SCE->REG_00H = 0x00000001U; + SCE->REG_C4H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0010B008U; + SCE->REG_ECH = 0x00000800U; + SCE->REG_E0H = 0x80900000U; + SCE->REG_00H = 0x00008443U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000038a0U; + SCE->REG_ECH = 0x34202a25U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000400U; + SCE->REG_ECH = 0x04202905U; + SCE->REG_ECH = 0x34202a28U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000005AU; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b4a0U; + SCE->REG_ECH = 0x00000002U; + for(iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x01003804U; + SCE->REG_ECH = 0x342028e0U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x00002440U; + SCE->REG_ECH = 0x00002cc0U; + SCE->REG_ECH = 0x00002485U; + } + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000037U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x0000003cU; + SCE->REG_ECH = 0x01003804U; + SCE->REG_ECH = 0x342028e0U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x00002cc0U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x0000003eU; + SCE->REG_ECH = 0x01003804U; + SCE->REG_ECH = 0x342028e0U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x8084000aU; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000a540U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x0000a4c0U; + SCE->REG_ECH = 0x00000002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00002008U; + R_SCE_func101(0x2f9974edU, 0x5b81fb15U, 0x12b2aaacU, 0xa489d594U); + } + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000200U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x38008860U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x8752b825U, 0x94164081U, 0x0f3acfb3U, 0x0aac3e7aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x6334ebb3U, 0x3709c96eU, 0x91cd611cU, 0x7a3c897eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_RETRY; + } + else + { + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000001f0U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x8a681df7U; + SCE->REG_ECH = 0x00003ffeU; + R_SCE_func100(0xf61cad5fU, 0xbf13df5cU, 0x354511c2U, 0x7f6841b7U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x000b0804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000352U; + SCE->REG_C4H = 0x00070805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000001U); + R_SCE_func100(0xcac08e72U, 0xb14b6522U, 0xd325a3aeU, 0x4dda977fU); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x0100b7f7U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8188000aU; + SCE->REG_00H = 0x00002823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x000b0805U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x00070805U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x2b6949adU, 0xcaad5bf9U, 0xf3e6089aU, 0x88cf1187U); + R_SCE_func103(); + R_SCE_func100(0x9f426479U, 0x73398377U, 0x91e1526aU, 0x8925be3eU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x010d0c04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x0a5890c4U, 0x96324e42U, 0x76850e62U, 0x2e8870a3U); + R_SCE_func103(); + R_SCE_func100(0x3fa01441U, 0xbb928ba2U, 0xd264e2e4U, 0x83034508U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[20] = SCE->REG_100H; + S_RAM[21] = SCE->REG_100H; + S_RAM[22] = SCE->REG_100H; + S_RAM[23] = SCE->REG_100H; + SCE->REG_13CH = 0x00000202U; + R_SCE_func102(0x55dd773aU, 0xaf263f67U, 0xa18300fdU, 0xb7af8e2aU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p82_r4.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p8f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p8f.c new file mode 100644 index 0000000000..2e5096b05d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p8f.c @@ -0,0 +1,515 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_AesKeyWrapSub(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, int32_t KEY_INDEX_SIZE, uint32_t *InData_WrappedKeyType, uint32_t *InData_WrappedKeyIndex, uint32_t WRAPPED_KEY_SIZE, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B4H & 0x1dU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00008f01U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80020100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_WrappedKeyType[0]; + SCE->REG_ECH = 0x00003409U; + SCE->REG_ECH = 0x3420a900U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x305b5351U, 0x83de6717U, 0x6cba8950U, 0xa2b864e1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x5c3a55e3U, 0xa0c3ecc3U, 0xfe11efd2U, 0x27f3f41cU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000008fU); + R_SCE_func101(0xe07b9c32U, 0x4dadeecaU, 0x1d32404dU, 0x513c7ae7U); + R_SCE_func043(); + SCE->REG_ECH = 0x38000d08U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xfe2d3562U, 0x35b00141U, 0x0321e8e0U, 0xbc1264c3U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000008fU); + R_SCE_func101(0x555e89e1U, 0x2019090bU, 0xe3fbb932U, 0x730f87e1U); + R_SCE_func044(); + R_SCE_func100(0x3fbf2779U, 0x177c865eU, 0xcb70763fU, 0x9c30d3ceU); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_B0H = 0x00000000U; + R_SCE_func101(0x051c7a41U, 0xf3e46c79U, 0x1db171daU, 0xf478499aU); + } + else + { + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000049U); + R_SCE_func101(0x073eb526U, 0x8866c426U, 0x2499eabcU, 0xd50a629cU); + R_SCE_func044(); + R_SCE_func100(0x36ac2bd4U, 0x7e94cd53U, 0xf5089cb2U, 0x96149e95U); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x5b8c39f8U, 0x9d5a1504U, 0x1d407669U, 0xfe2a943eU); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_B0H = 0x40000000U; + R_SCE_func101(0x3a16aecfU, 0x6e42d934U, 0x977e9877U, 0x5eabd49bU); + } + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xe29deb0cU, 0xd6a8327bU, 0xf3ba375bU, 0x0f489ec9U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x0c0c0f82U, 0x8b143776U, 0x2a13a8aeU, 0xa90178d7U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func030(); + SCE->REG_ECH = 0x000035c7U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_WrappedKeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000004aU); + R_SCE_func101(0xfd520067U, 0xbb3e0262U, 0xb2168269U, 0xfa545989U); + R_SCE_func043(); + SCE->REG_ECH = 0x000034e6U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000004aU); + R_SCE_func101(0xc297c1e4U, 0xe8534007U, 0xc26cf313U, 0x57c0f657U); + R_SCE_func044(); + SCE->REG_ECH = 0x000034eeU; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_ECH = 0x0000b780U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x0000b760U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000a8e0U; + SCE->REG_ECH = 0x00000005U; + for(iLoop = 0; iLoop < (uint32_t)KEY_INDEX_SIZE-5; iLoop = iLoop + 4) + { + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_WrappedKeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_WrappedKeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_WrappedKeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_WrappedKeyIndex[iLoop+1 + 3]; + SCE->REG_E0H = 0x8084001fU; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000027fcU; + SCE->REG_ECH = 0x000027dbU; + R_SCE_func101(0x7929fa04U, 0xd415ca63U, 0x79d9e785U, 0xbb4704abU); + } + SCE->REG_ECH = 0x38000bc7U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_WrappedKeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_WrappedKeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_WrappedKeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_WrappedKeyIndex[iLoop+1 + 3]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x5fdb42e0U, 0xe6f0f23eU, 0x6335e689U, 0x3da1fd30U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x1843c1a2U, 0xb52d7749U, 0xf91ab81aU, 0x9f2bceedU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0xa6a6a6a6U; + SCE->REG_ECH = 0x00003420U; + SCE->REG_ECH = 0x0000b760U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_ECH = 0x0000b780U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x00000bdeU; + for(jLoop = 0; jLoop <= 5; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x000037fbU; + SCE->REG_ECH = 0x00000bbdU; + for(iLoop = 1; iLoop <= (WRAPPED_KEY_SIZE-2)/2; iLoop = iLoop + 1) + { + SCE->REG_A4H = 0x00008a85U; + SCE->REG_E0H = 0x81020000U; + SCE->REG_00H = 0x0000180bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x8182001fU; + SCE->REG_00H = 0x0000180bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000824U; + SCE->REG_ECH = 0x00003c5fU; + SCE->REG_ECH = 0x000027fcU; + SCE->REG_ECH = 0x00003c7fU; + SCE->REG_ECH = 0x000027fcU; + SCE->REG_ECH = 0x00002c80U; + SCE->REG_ECH = 0x00002fa0U; + R_SCE_func101(0xda78279fU, 0x0a5f1eb6U, 0xc06af53dU, 0xeab4c9a0U); + } + SCE->REG_ECH = 0x38000ba5U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00002fc0U; + R_SCE_func101(0x34d25252U, 0x40dbdb6dU, 0x99df6038U, 0x67fa964aU); + } + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x00003c1fU; + SCE->REG_ECH = 0x000027fcU; + SCE->REG_ECH = 0x00003c3fU; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037a5U; + SCE->REG_ECH = 0x00002fa0U; + SCE->REG_ECH = 0x0000b780U; + SCE->REG_ECH = 0x00000008U; + for(iLoop = 0; iLoop < WRAPPED_KEY_SIZE; iLoop = iLoop + 2) + { + SCE->REG_ECH = 0x000008c6U; + SCE->REG_ECH = 0x34202bddU; + SCE->REG_ECH = 0x2000d0c0U; + SCE->REG_ECH = 0x00007c06U; + SCE->REG_1CH = 0x00602000U; + R_SCE_func100(0x6f510921U, 0xe28adf5bU, 0x31e7aa86U, 0x438b03b1U); + SCE->REG_E0H = 0x8182001fU; + SCE->REG_04H = 0x0000060aU; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop + 0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop+1 + 0] = SCE->REG_100H; + SCE->REG_ECH = 0x000027fcU; + SCE->REG_ECH = 0x00002fc0U; + R_SCE_func101(0xb9ed7705U, 0x23665053U, 0x13bd71d9U, 0x4e7a1e30U); + } + SCE->REG_ECH = 0x38000bddU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func102(0x1a61c563U, 0x297d72b2U, 0x6448120bU, 0xb7ec730eU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p8f.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p90.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p90.c new file mode 100644 index 0000000000..468bbe2a02 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p90.c @@ -0,0 +1,697 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_AesKeyUnwrapSub(uint32_t *InData_KeyType, uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t KEY_INDEX_SIZE, uint32_t *InData_WrappedKeyType, uint32_t *InData_Text, uint32_t WRAPPED_KEY_SIZE, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B4H & 0x1dU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009002U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000268U; + SCE->REG_E0H = 0x80030100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_WrappedKeyType[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x00003409U; + SCE->REG_ECH = 0x3420a900U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x1000d3e0U; + SCE->REG_ECH = 0x38008940U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x38008940U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x013b1e01U, 0x3ed91013U, 0x75cef122U, 0x686111b4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x701f15e6U, 0x1c0eaf89U, 0xaeaff00eU, 0xad21bf66U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000d08U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x350fc5c3U, 0xc528af97U, 0xd3652a67U, 0x387556f5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x38000d4aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xac414127U, 0x5c826013U, 0x59885dccU, 0x305a35f5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000090U); + R_SCE_func101(0x9a649d4aU, 0x7d38bb48U, 0x84abb158U, 0x7d1ff96cU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + R_SCE_func101(0x255b8a49U, 0x35655738U, 0x6a540c00U, 0x701eaec7U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000090U); + R_SCE_func101(0xb13aede3U, 0x8b1ab543U, 0x62497669U, 0xe968f992U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x2a46c04bU; + R_SCE_func101(0xcec6b20bU, 0x27fe62a1U, 0x0e58bb77U, 0x36b3f68eU); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000090U); + R_SCE_func101(0x21ca5987U, 0x967db75cU, 0x24a7de57U, 0x48dd3feaU); + R_SCE_func044(); + R_SCE_func100(0x41b5fa12U, 0x1752068eU, 0xb987c905U, 0x83248635U); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_B0H = 0x00000000U; + R_SCE_func101(0x6153243dU, 0x1a3a6645U, 0xe9c0a3e7U, 0x8b5092d6U); + } + else + { + SCE->REG_ECH = 0x38000d4aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xa71fb63fU, 0xfaae8da0U, 0xba82cba4U, 0x3f705ee6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000004bU); + R_SCE_func101(0xbbc1a3ffU, 0xde68b0d2U, 0x56e701b8U, 0x271de72aU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + R_SCE_func101(0x502b9941U, 0xba6abd1aU, 0x3e89b84aU, 0x5c0ca06aU); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000004bU); + R_SCE_func101(0x56c60799U, 0x157a19afU, 0x443ea058U, 0x9cb6521aU); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x85d04999U; + R_SCE_func101(0x90c124aeU, 0x0e14c73bU, 0x3d8b606dU, 0xa5b520e2U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000004bU); + R_SCE_func101(0xe219faa4U, 0xfa424404U, 0x6e59d37fU, 0xfe0d892cU); + R_SCE_func044(); + R_SCE_func100(0x1dbcaba0U, 0x9ed5fd0dU, 0x5ab891b4U, 0x7d13d03fU); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xee080bc6U, 0xb8f87a13U, 0x080634dfU, 0x5a646b43U); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_B0H = 0x40000000U; + R_SCE_func101(0x50b8629fU, 0x77898abcU, 0x52887e66U, 0x26d40cd1U); + } + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x1897c744U, 0xa689db7cU, 0x4ce07427U, 0x65c6c3aaU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2f7fd432U, 0x588a652eU, 0x58538107U, 0x4b50f35aU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func030(); + SCE->REG_ECH = 0x00002ca0U; + SCE->REG_ECH = 0x00003500U; + SCE->REG_ECH = 0x000035c7U; + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x80020000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[1]; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00002fc0U; + SCE->REG_ECH = 0x0000b780U; + SCE->REG_ECH = 0x00000008U; + for(iLoop = 2; iLoop < WRAPPED_KEY_SIZE; iLoop = iLoop + 2) + { + SCE->REG_104H = 0x00000168U; + SCE->REG_E0H = 0x8082001fU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop+1 + 0]; + SCE->REG_ECH = 0x000027fcU; + SCE->REG_ECH = 0x00002fc0U; + R_SCE_func101(0x1f3e6773U, 0x8a5e4aabU, 0xea325d29U, 0x14f8aa6eU); + } + SCE->REG_ECH = 0x38000bc5U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x0000377fU; + SCE->REG_ECH = 0x0000ab60U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_ECH = 0x00003785U; + SCE->REG_ECH = 0x00003380U; + SCE->REG_ECH = 0x0000349cU; + SCE->REG_ECH = 0x00026c84U; + SCE->REG_ECH = 0x00016f9cU; + SCE->REG_ECH = 0x0000249cU; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x0000b720U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b740U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_ECH = 0x00003785U; + SCE->REG_ECH = 0x00003380U; + for(jLoop = 5; jLoop >= 0; jLoop = jLoop - 1) + { + SCE->REG_ECH = 0x000037fbU; + SCE->REG_ECH = 0x00000bbdU; + for(iLoop = (WRAPPED_KEY_SIZE/2)-1; iLoop >= 1; iLoop = iLoop - 1) + { + SCE->REG_ECH = 0x00000824U; + SCE->REG_A4H = 0x0000ca85U; + SCE->REG_E0H = 0x81020000U; + SCE->REG_00H = 0x0000180bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x8182001fU; + SCE->REG_00H = 0x0000180bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003c5fU; + SCE->REG_ECH = 0x000027f9U; + SCE->REG_ECH = 0x00003c7fU; + SCE->REG_ECH = 0x00002bfaU; + SCE->REG_ECH = 0x00003080U; + SCE->REG_ECH = 0x00002fa0U; + R_SCE_func101(0xe41fab11U, 0x74336dbcU, 0x3c5d2ab1U, 0xc41c71ccU); + } + SCE->REG_ECH = 0x38000bbcU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00002fc0U; + R_SCE_func101(0x1ba8af0eU, 0xa0dc1032U, 0xdd5f8bd1U, 0xe8448a27U); + } + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0xa6a6a6a6U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x38008820U; + SCE->REG_ECH = 0xa6a6a6a6U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x17c48646U, 0x82b08a4fU, 0xb4bda1a7U, 0x7e148723U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xc77afd82U, 0x7161196aU, 0xaa804308U, 0xda5e3562U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x149ee113U, 0xe1ddeffaU, 0x5930b8cdU, 0x3620afe7U); + SCE->REG_ECH = 0x00003408U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000004cU); + R_SCE_func101(0xb1032f26U, 0x2c69b53fU, 0x8475208fU, 0xf248f615U); + R_SCE_func043(); + SCE->REG_ECH = 0x000034e6U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000004cU); + R_SCE_func101(0xc581f586U, 0xaa698625U, 0xc0c8e6f5U, 0xa141aee6U); + R_SCE_func044(); + SCE->REG_ECH = 0x000034eeU; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x0000b760U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b780U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x0000a8e0U; + SCE->REG_ECH = 0x00000005U; + for(iLoop = 0; iLoop < KEY_INDEX_SIZE-5; iLoop = iLoop + 4) + { + SCE->REG_ECH = 0x000008c6U; + SCE->REG_ECH = 0x34202bc7U; + SCE->REG_ECH = 0x2000d0c0U; + SCE->REG_ECH = 0x00007c06U; + SCE->REG_1CH = 0x00602000U; + R_SCE_func100(0xcc519213U, 0xdb736583U, 0x5afe0b62U, 0x207b921dU); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e087b5U; + SCE->REG_E0H = 0x8184001fU; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop+1 + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x000027fcU; + SCE->REG_ECH = 0x000027dbU; + R_SCE_func101(0x093a652bU, 0xe1621c12U, 0x60276291U, 0xe177c523U); + } + SCE->REG_ECH = 0x38000bc7U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func100(0x4a54fc7bU, 0xa99b26c7U, 0x80496a5cU, 0x41c6f607U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop+1 + 3] = SCE->REG_100H; + R_SCE_func100(0x73c5eeb4U, 0x34c7700fU, 0x5c343d34U, 0x87b2e576U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + R_SCE_func102(0x91c710f0U, 0x2a68a69eU, 0x7725a9d4U, 0x9f728aa7U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p90.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p92.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p92.c new file mode 100644 index 0000000000..e7e292e437 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p92.c @@ -0,0 +1,438 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_SelfCheck3Sub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009203U; + SCE->REG_108H = 0x00000000U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x000001f0U; + SCE->REG_ECH = 0x00003bfeU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x8a681df7U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xbc62f8eeU, 0xf60c8b68U, 0xacc557c3U, 0xe1c5ea3fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00093b8cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01c7ba56U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00070804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_ECH = 0x3000a820U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x00010020U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x00000080U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00002008U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x00000884U; + SCE->REG_ECH = 0x000008a5U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_ECH = 0x00000013U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000348U; + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x000000b7U; + for(jLoop = 0; jLoop < 1; jLoop = jLoop + 1) + { + R_SCE_func100(0xd85048b3U, 0x472af28dU, 0x35179f10U, 0x25a5e550U); + SCE->REG_ECH = 0x00007c01U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901cU; + R_SCE_func101(0xf6774c41U, 0x8a1dd359U, 0xd8e1be85U, 0x2ed06095U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901eU; + R_SCE_func101(0x3a523fceU, 0x1f9b5c85U, 0x5c13d0d3U, 0x255c00c8U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901dU; + R_SCE_func101(0x83274642U, 0xaee9de82U, 0x46dfb756U, 0x5b9db442U); + } + SCE->REG_C4H = 0x41001e5eU; + SCE->REG_00H = 0x80002401U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001200U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B30) + { + /* waiting */ + } + SCE->REG_00H = 0x00000001U; + SCE->REG_C4H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0010B008U; + SCE->REG_ECH = 0x00000800U; + SCE->REG_E0H = 0x80900000U; + SCE->REG_00H = 0x00008443U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000038a0U; + SCE->REG_ECH = 0x00003405U; + SCE->REG_ECH = 0x00002804U; + SCE->REG_ECH = 0x342028e0U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x34202808U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x00003485U; + R_SCE_func101(0x89a92a87U, 0x829fdab7U, 0x3373183eU, 0x17a9a49dU); + } + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0000005AU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x000008c6U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b4a0U; + SCE->REG_ECH = 0x00000002U; + for(iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x01003804U; + SCE->REG_ECH = 0x342028e0U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x00002440U; + SCE->REG_ECH = 0x00002cc0U; + SCE->REG_ECH = 0x00002485U; + } + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x38008840U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000033U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x0000003cU; + SCE->REG_ECH = 0x01003804U; + SCE->REG_ECH = 0x342028e0U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x00002cc0U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x0000003eU; + SCE->REG_ECH = 0x01003804U; + SCE->REG_ECH = 0x342028e0U; + SCE->REG_ECH = 0x10005066U; + SCE->REG_ECH = 0x38008860U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xb0599c44U, 0xa004f708U, 0xb622fb4bU, 0x26ebcfa1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x5befaa57U, 0xb61fc722U, 0xe545fd8fU, 0x40e2a67cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_RETRY; + } + else + { + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0000001cU; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x41001eddU; + SCE->REG_00H = 0x00002413U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000000U; + SCE->REG_E0H = 0x80040080U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x601c5c9eU, 0x36c5cc20U, 0xe9624f37U, 0xe1ab5fcfU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x000b0804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000352U; + SCE->REG_C4H = 0x00070805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000001U); + R_SCE_func100(0xc5c449c3U, 0x2addf698U, 0x2450f511U, 0xa2488d64U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x0100b7f7U; + SCE->REG_E0H = 0x81080000U; + SCE->REG_00H = 0x00002823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x000b0805U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x00070805U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xbcd93370U, 0x7f78034aU, 0x704cbbdfU, 0xf752e923U); + R_SCE_func103(); + R_SCE_func100(0x7cc92e49U, 0xefe795eeU, 0xb1bf9563U, 0x00aaf299U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x010d0c04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x68b792eeU, 0x7b995f71U, 0x995e79b3U, 0xe6982885U); + R_SCE_func103(); + R_SCE_func100(0x49c5ae79U, 0x3fa4474cU, 0xa8ec11b5U, 0xbee69bb9U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[24] = change_endian_long(SCE->REG_100H); + S_RAM[25] = change_endian_long(SCE->REG_100H); + S_RAM[26] = change_endian_long(SCE->REG_100H); + S_RAM[27] = change_endian_long(SCE->REG_100H); + SCE->REG_13CH = 0x00000202U; + R_SCE_func102(0x977284d5U, 0x7758325cU, 0xec1cd437U, 0xcef3304cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + else + { + R_SCE_func100(0xd161ba91U, 0x5df63514U, 0xf9982d16U, 0xf6e4c2cfU); + R_SCE_func103(); + R_SCE_func100(0x45b30ae4U, 0xa43436f8U, 0xb42bd4d9U, 0xd02d8034U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x010d0c04U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x695c8fa0U, 0x9988b18bU, 0xb8d9b454U, 0x21cbfb17U); + R_SCE_func103(); + R_SCE_func100(0x1c3b2f77U, 0xbf895b6bU, 0x240da1cfU, 0x8856aea9U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[24] = change_endian_long(SCE->REG_100H); + S_RAM[25] = change_endian_long(SCE->REG_100H); + S_RAM[26] = change_endian_long(SCE->REG_100H); + S_RAM[27] = change_endian_long(SCE->REG_100H); + SCE->REG_13CH = 0x00000202U; + R_SCE_func102(0xf549d5d0U, 0x14c317c0U, 0x7f720bf8U, 0x61c94f96U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p92_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95f.c new file mode 100644 index 0000000000..a4b176b0f4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95f.c @@ -0,0 +1,206 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xbe5686d5U, 0x0f06d819U, 0x7c22bf43U, 0xd5b30f1cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xac09da14U, 0xa0b0b35dU, 0xeaf51311U, 0xcb22fb91U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xdb482441U, 0xe196935bU, 0xe2de7433U, 0x4ce17933U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00e007b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0U; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + R_SCE_func100(0xeea8a77fU, 0x827f4fd8U, 0xb1831de3U, 0x33a9ef07U); + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_04H = 0x00000613U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + R_SCE_func101(0xee2c4e6eU, 0x3c7200c1U, 0x89b501c2U, 0x826aaba1U); + } + else + { + R_SCE_func101(0xeb164b37U, 0x9f02b370U, 0xb2d8cf72U, 0xc398cac5U); + } + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0xcd145369U, 0xa1d6bf68U, 0x8a1fda70U, 0x0f37a2fdU); + SCE->REG_A4H = 0x000009c5U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + R_SCE_func102(0x156c2b81U, 0x3627f80eU, 0x735bda4eU, 0x3b1eeb05U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p95f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95i.c new file mode 100644 index 0000000000..37a6bff9a7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95i.c @@ -0,0 +1,303 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128CcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009502U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x40882738U, 0xc1d4845cU, 0x24fcaed2U, 0xfba1f59aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x4d12a240U, 0xfa90c800U, 0xb7f6de26U, 0xbaa2b58dU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x21d4a991U, 0xddab2789U, 0x73cb4398U, 0xbc233299U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000095U); + R_SCE_func101(0x5114e723U, 0x1ba8c6acU, 0x5e74535dU, 0x00a6375bU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + R_SCE_func101(0xd54851e1U, 0x7b8c9f6bU, 0x3a2eb089U, 0x95bfa8eaU); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000095U); + R_SCE_func101(0x56ab18d4U, 0x7d85789aU, 0xee4d79adU, 0x9fddbcd6U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x2a46c04bU; + R_SCE_func101(0x40f2d7eeU, 0x6b213ee2U, 0xa7a5ea78U, 0x2a9a2463U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000095U); + R_SCE_func101(0x1e2c6ce7U, 0xfa4690e4U, 0xe514cea8U, 0xc7fbd4aaU); + R_SCE_func044(); + R_SCE_func100(0xf2d9ce1cU, 0xdce5eabdU, 0xc5869827U, 0xc7552a1cU); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xe9343cc4U, 0x52fa451cU, 0xfc2fd1b9U, 0x820a4aa1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xc1dadacbU, 0x4cda8dfeU, 0x4ed45a3aU, 0xc3617451U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000734U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00e00806U; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + R_SCE_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + R_SCE_func100(0x51c05912U, 0x55c6f5a3U, 0xfefc3cc8U, 0x933df0d0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x518c76ffU, 0x3e6ee029U, 0x605176d2U, 0xd4c39e42U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p95i_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95u.c new file mode 100644 index 0000000000..5d22646f48 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95u.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xf8ba9a7fU, 0xbf8285edU, 0x7f28d71cU, 0x812907f6U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00e007b6U; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + R_SCE_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x0736a57eU, 0x1ebd36d7U, 0x9b58cf19U, 0x927d7deaU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p95u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98f.c new file mode 100644 index 0000000000..c42ebc873a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98f.c @@ -0,0 +1,299 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xa7d161b2U, 0x08916af5U, 0x4b10382bU, 0xfe8c37fbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x13ff4c69U, 0x5080d3beU, 0xedf46dc6U, 0x20aa2bdeU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MACLength[0]; + SCE->REG_ECH = 0x38008940U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x34202beaU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xc6fe6dc6U, 0xbb00a8f8U, 0x77d3af08U, 0x4e638313U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xcbe276a6U, 0xd20e41a2U, 0x9cb6afaaU, 0x394111e0U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xff4080f7U, 0xa56c4ac4U, 0xca60dc12U, 0x2c29646cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000007b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0U; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + R_SCE_func100(0x2ea80017U, 0xf617ca64U, 0xf57f4b87U, 0x28d56d13U); + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_04H = 0x00000613U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + SCE->REG_A4H = 0x00000e55U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xd06a9940U, 0x3b2200f7U, 0x9b79925cU, 0xf866ebf7U); + } + else + { + R_SCE_func101(0x00ea433eU, 0x76012293U, 0x8bc71133U, 0x86d1a7f6U); + } + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_A4H = 0x010007b5U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000a540U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000821U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beaU; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00050805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00000000U; + R_SCE_func100(0xce751d84U, 0x1832c7c0U, 0xc2978b79U, 0x825e4eaaU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x524ed7a8U, 0x0e41a8c4U, 0x4b410ad9U, 0x4b5eee94U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func102(0x52c1de68U, 0xbbcba771U, 0x480e3e89U, 0x90ef5432U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p98f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98i.c new file mode 100644 index 0000000000..ed000bfc32 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98i.c @@ -0,0 +1,303 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009802U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x3b0bbd2bU, 0xcf11790cU, 0x76b21321U, 0x37d766bfU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xdb9a0cbdU, 0x0b9deb2cU, 0x90033290U, 0xb936e955U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xe1c1adb2U, 0x81eed4e3U, 0x23e2a25dU, 0xe0a2d5b8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000098U); + R_SCE_func101(0x3c9d0e2bU, 0x0d86f820U, 0xe65201c4U, 0xdf256fdbU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000005U; + R_SCE_func101(0xaaf2b8b4U, 0x3061202aU, 0x512aaf27U, 0x9d0820f3U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000041U); + R_SCE_func101(0x11f6bb78U, 0xfa335be5U, 0x433e1f35U, 0x39b850f3U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x2a46c04bU; + R_SCE_func101(0x1504504dU, 0xbd51bcd2U, 0x2cb8dcc7U, 0x4690444bU); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000098U); + R_SCE_func101(0x136fb9f0U, 0x0b59156eU, 0xa9743671U, 0x29093f79U); + R_SCE_func044(); + R_SCE_func100(0xbbcede17U, 0xc6f4a032U, 0x2b10839fU, 0x29fabe6dU); + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xe40f1d24U, 0x60e058fcU, 0xb83a2e29U, 0xee9309ccU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2c6e4392U, 0x7a888073U, 0x132479daU, 0x1c9e65d8U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000734U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00f00806U; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + R_SCE_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + R_SCE_func100(0x3713fe09U, 0xe954d584U, 0x5eaa2ed8U, 0x7855d0c4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xc7b1b0c7U, 0xbd91217bU, 0x15d40814U, 0x63f9d2f7U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p98i_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98u.c new file mode 100644 index 0000000000..fbbe602a0b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98u.c @@ -0,0 +1,113 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes128CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x7ca2a2a7U, 0x937bce9bU, 0x64814dd1U, 0x94c31515U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_A4H = 0x00f007b6U; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + R_SCE_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0x1fb79f6bU, 0x06b2d242U, 0x80c817c2U, 0xaf92768bU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p98u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p9e.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p9e.c new file mode 100644 index 0000000000..e6e8e351e5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p9e.c @@ -0,0 +1,287 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_EcdsaNistP256SignatureVerificationSub(uint32_t *InData_KeyIndex, uint32_t *InData_MsgDgst, uint32_t *InData_Signature) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009e03U; + SCE->REG_108H = 0x00000000U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_104H = 0x00001768U; + SCE->REG_E0H = 0x8098001eU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[iLoop + 0]; + } + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[iLoop + 0]; + } + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000009eU); + R_SCE_func101(0x584681d8U, 0xbdafbbbdU, 0x816b5be5U, 0x879e996fU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000016U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000009eU); + R_SCE_func101(0x152b19cbU, 0xc060b615U, 0xc1845cb9U, 0x02e68eadU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e08887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000091U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x426170c0U, 0x96b2d644U, 0x73894407U, 0x2a420925U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x4ef50b7aU, 0x53a2345aU, 0x9ab8b8d6U, 0x0afe84bbU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + R_SCE_func100(0x8b486f93U, 0x6d98b0e7U, 0x645b2118U, 0xd9a5c2eeU); + SCE->REG_7CH = 0x00000011U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8188001eU; + SCE->REG_00H = 0x00005823U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + SCE->REG_ECH = 0x00000b5aU; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000009eU); + R_SCE_func101(0xef9ba832U, 0x6dbb85caU, 0xea8ce17cU, 0xd467f51aU); + R_SCE_func073_r2(OFS_ADR); + R_SCE_func100(0xa3192968U, 0xcafbc778U, 0x59fbbd95U, 0x2eee7a6bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x7a591970U, 0x15e49bafU, 0xc4607f2bU, 0xfdc3a6a3U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func102(0x2cc1ca82U, 0xbab96ed1U, 0x20afd3f7U, 0x6c01f9e6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_p9e.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1f.c new file mode 100644 index 0000000000..d32bc92878 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1f.c @@ -0,0 +1,208 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xeaf34f80U, 0x8415bd38U, 0x0de3be3bU, 0x772ae243U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xfcf18586U, 0x4ce367a6U, 0xa4a77879U, 0x9ab68284U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x9a24763eU, 0x0c8f9e52U, 0xec5bcc27U, 0xd0cb9c9aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00e087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0U; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + R_SCE_func100(0xd553443cU, 0x0e30325cU, 0x6157ec62U, 0x6cbdc1d7U); + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_04H = 0x00000613U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + R_SCE_func101(0xdae4d602U, 0xafa75fd7U, 0x693a3142U, 0xc01eba0dU); + } + else + { + R_SCE_func101(0x4046f165U, 0x8925fdcdU, 0x5270c75aU, 0xd70f18c8U); + } + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x46bd029fU, 0x79302468U, 0xaf009791U, 0x871958e8U); + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x000089c5U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000113U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + R_SCE_func102(0xb6b0c327U, 0xc9950e14U, 0x7b8996e2U, 0x3b2a37e3U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pa1f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1i.c new file mode 100644 index 0000000000..72767f185d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1i.c @@ -0,0 +1,322 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000a102U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x071514dbU, 0x728f6e48U, 0x01017c18U, 0xaf4cc6f1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x80485ee5U, 0x3da78749U, 0x79647f5fU, 0x97d47768U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x9a1c3c30U, 0xd234a55dU, 0x8ac4d064U, 0xce307dd8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a1U); + R_SCE_func101(0x2bf186e2U, 0x3887d856U, 0x15873b61U, 0xdcc23130U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + R_SCE_func101(0x692b9713U, 0x0c998b99U, 0xa33e14fdU, 0x7b09f9aaU); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a1U); + R_SCE_func101(0x3c04eaf7U, 0xfc9bc703U, 0xf1b9b14aU, 0x850bdd81U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x85d04999U; + R_SCE_func101(0xc1c43a08U, 0x0d921fc5U, 0xdd7cab74U, 0x7095efa7U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a1U); + R_SCE_func101(0x323ef535U, 0x7fa15f30U, 0x45e966f6U, 0xb68289c5U); + R_SCE_func044(); + R_SCE_func100(0xca76c8a6U, 0xd62ab9b0U, 0x1f557190U, 0x52eabcf5U); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd6ae99d4U, 0x4c760dc6U, 0x4ac6e1ecU, 0xbcd5c657U); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x93a9b8c2U, 0xcf932627U, 0x9c07a703U, 0x3bef7573U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb54d6f35U, 0xd3b9f14eU, 0x15287d7dU, 0x2f6b652bU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000734U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00058e56U; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + R_SCE_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + R_SCE_func100(0x1b770fd3U, 0x6ab3717bU, 0xc037592dU, 0x15a122adU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2b58d3a9U, 0xe40af2c1U, 0x4c755500U, 0x4a1b04b4U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pa1i_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1u.c new file mode 100644 index 0000000000..ff991ae99b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1u.c @@ -0,0 +1,114 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0x04f23741U, 0x141a1ee0U, 0x8a584ce3U, 0xc364aeceU); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00e087b6U; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + R_SCE_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0xfdced782U, 0xbee63fbdU, 0x8eea42beU, 0x4bccd5ceU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pa1u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4f.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4f.c new file mode 100644 index 0000000000..6dddead53c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4f.c @@ -0,0 +1,302 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, uint32_t *InData_MACLength, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xb98f1f55U, 0xea9990ddU, 0x8fb728d4U, 0x513a5a8cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x497f7c9cU, 0xa730bfb2U, 0xcfd3201cU, 0x8d485df6U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MACLength[0]; + SCE->REG_ECH = 0x38008940U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x34202beaU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x319bd30fU, 0x75eb463bU, 0x311256eeU, 0x38dda86dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x45e455e9U, 0x994f0ec1U, 0x59b938aaU, 0xd3757d71U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xe93e6239U, 0x4ab6bf7dU, 0xdcfcdcf4U, 0x78b7fb05U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0U; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + R_SCE_func100(0x8dc7f627U, 0x896c18c2U, 0x54f2115cU, 0x7af67b0bU); + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_04H = 0x00000613U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[3] = SCE->REG_100H; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008e55U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x71288159U, 0xbb84ea4bU, 0xf466b153U, 0x0098af1dU); + } + else + { + R_SCE_func101(0x40d570a5U, 0xfd322c0aU, 0x52e75990U, 0x680b82bbU); + } + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x010087b5U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000a540U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000821U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beaU; + SCE->REG_ECH = 0x12003c3fU; + SCE->REG_ECH = 0x00002fe0U; + } + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00050805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81840001U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00000000U; + R_SCE_func100(0x7e2fa286U, 0x199438daU, 0x8d80a24fU, 0xdd69dc47U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb88c8afaU, 0xdf448822U, 0xf2c940f9U, 0x006a87abU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func102(0x56ba266cU, 0x3790be2aU, 0x3df0cb38U, 0x7db73c6cU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pa4f_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4i.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4i.c new file mode 100644 index 0000000000..41cc1a5a95 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4i.c @@ -0,0 +1,322 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_Aes256CcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000a402U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x16b5e670U, 0xbb4dbc15U, 0xbb6e537dU, 0x34abedccU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x83d3cec4U, 0x55840465U, 0x276c0c52U, 0xc1478746U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x8ae02bb5U, 0xc844bd42U, 0x834adb31U, 0xbe865e83U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a4U); + R_SCE_func101(0x2b36e1c2U, 0x63ac24f1U, 0x97f8f8b1U, 0x6784b907U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x00000007U; + R_SCE_func101(0xf07f0bbbU, 0x282e6072U, 0x05405fd6U, 0x3d5007d3U); + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a4U); + R_SCE_func101(0x8ba8a06cU, 0x5b321aa0U, 0xcc0d48e8U, 0xe0020843U); + R_SCE_func068(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x85d04999U; + R_SCE_func101(0x5bfbc11cU, 0x5c3afa6aU, 0xbe5cf827U, 0x194bbc75U); + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000a4U); + R_SCE_func101(0x9c2d8154U, 0x733791a0U, 0x89a4b42bU, 0xd9221222U); + R_SCE_func044(); + R_SCE_func100(0x1641a278U, 0x7e724641U, 0x29b303e1U, 0x976d8931U); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x723e6004U, 0xb5b9044aU, 0x60f54f72U, 0xbc2bf94fU); + SCE->REG_A4H = 0x00090805U; + SCE->REG_00H = 0x00001213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x472189d1U, 0x9a078d76U, 0x86278134U, 0x2db96666U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xbcabc315U, 0x13d18048U, 0x9896341eU, 0xd13a92d8U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00000734U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00008e56U; + for (iLoop = 0; iLoop < Header_Len; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Header[iLoop + 0]; + SCE->REG_100H = InData_Header[iLoop + 1]; + SCE->REG_100H = InData_Header[iLoop + 2]; + SCE->REG_100H = InData_Header[iLoop + 3]; + } + R_SCE_func205();//DisableINTEGRATE_WRRDYBinthisfunction. + R_SCE_func100(0xf6a75afaU, 0x609fb37eU, 0x8b78467cU, 0x8125534cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x6a2b6110U, 0x8772a529U, 0x61b669edU, 0x5d284989U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pa4i_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4u.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4u.c new file mode 100644 index 0000000000..9e398fbc2e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4u.c @@ -0,0 +1,114 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_Aes256CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + R_SCE_func100(0xe8b2bbf8U, 0xfe89748eU, 0x7bd1cc87U, 0xa994a8e6U); + SCE->REG_104H = 0x000000b1U; + SCE->REG_B0H = 0x40000000U; + SCE->REG_A4H = 0x00f087b6U; + SCE->REG_04H = 0x0000c100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + R_SCE_func207();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + R_SCE_func101(0xab9c3adeU, 0x73c1e819U, 0x4092a6dbU, 0x392d9b6bU); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pa4u_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pdf.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pdf.c new file mode 100644 index 0000000000..494c68df1c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pdf.c @@ -0,0 +1,391 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateTlsRsaInstallDataSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000df02U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010020U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_ECH = 0x38008c20U; + SCE->REG_ECH = 0xfffffff0U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xce906ce4U, 0x83ba59cfU, 0xca39662fU, 0x5c42f1b4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x76746755U, 0xde65f15bU, 0x73e65b7aU, 0x032d0e8fU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + OFS_ADR = InData_SharedKeyIndex[0] << 3; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000dfU); + R_SCE_func101(0x2f63a8f4U, 0x3d99d99cU, 0xb859edbcU, 0xff5b1c94U); + R_SCE_func069(InData_SessionKey,OFS_ADR); + R_SCE_func100(0xa34f1b37U, 0x9925e9c5U, 0x5dfbe2acU, 0x52a3b414U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000dfU); + R_SCE_func101(0x11f46329U, 0x602107baU, 0xcf516939U, 0xf19dda60U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x01ba9fa3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000dfU); + R_SCE_func101(0x91b85fb1U, 0x43dd63a9U, 0x7fa550c3U, 0xb9f15e30U); + R_SCE_func044(); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x01000001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000003U); + R_SCE_func101(0xb7a04c94U, 0x1596c1c2U, 0x01dca8a4U, 0x7f142767U); + R_SCE_func044(); + R_SCE_func100(0x7a0afabaU, 0x0998a5c3U, 0x8d594547U, 0xe55963b1U); + SCE->REG_00H = 0x00013103U; + SCE->REG_2CH = 0x00000014U; + SCE->REG_104H = 0x00003f61U; + SCE->REG_B0H = 0x00000f00U; + SCE->REG_A4H = 0x00d0c9a7U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[iLoop + 0]; + SCE->REG_100H = InData_InstData[iLoop + 1]; + SCE->REG_100H = InData_InstData[iLoop + 2]; + SCE->REG_100H = InData_InstData[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000202U; + for (jLoop = 0; jLoop < 64; jLoop = jLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[1+jLoop + 0] = SCE->REG_100H; + OutData_InstData[1+jLoop + 1] = SCE->REG_100H; + OutData_InstData[1+jLoop + 2] = SCE->REG_100H; + OutData_InstData[1+jLoop + 3] = SCE->REG_100H; + } + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x00005004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + R_SCE_func100(0x7d03abc9U, 0xe83e9888U, 0x0bca03e9U, 0x30a10901U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000202U; + for (jLoop = 64; jLoop < 128; jLoop = jLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[1+jLoop + 0] = SCE->REG_100H; + OutData_InstData[1+jLoop + 1] = SCE->REG_100H; + OutData_InstData[1+jLoop + 2] = SCE->REG_100H; + OutData_InstData[1+jLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x7f407a0eU, 0xd442e5acU, 0x5274b069U, 0x8b1faab1U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[iLoop + 0]; + SCE->REG_100H = InData_InstData[iLoop + 1]; + SCE->REG_100H = InData_InstData[iLoop + 2]; + SCE->REG_100H = InData_InstData[iLoop + 3]; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e087b5U; + SCE->REG_00H = 0x00002113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[1+jLoop + 0] = SCE->REG_100H; + OutData_InstData[1+jLoop + 1] = SCE->REG_100H; + OutData_InstData[1+jLoop + 2] = SCE->REG_100H; + OutData_InstData[1+jLoop + 3] = SCE->REG_100H; + R_SCE_func100(0xea03b026U, 0xea546fe6U, 0x42fa0dc1U, 0x322aaba7U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[1+jLoop+4 + 0] = SCE->REG_100H; + OutData_InstData[1+jLoop+4 + 1] = SCE->REG_100H; + OutData_InstData[1+jLoop+4 + 2] = SCE->REG_100H; + OutData_InstData[1+jLoop+4 + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[68]; + SCE->REG_100H = InData_InstData[69]; + SCE->REG_100H = InData_InstData[70]; + SCE->REG_100H = InData_InstData[71]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xd7483102U, 0xc30803feU, 0x56e1a9d2U, 0xd9b61a87U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x8ff3e735U, 0x3d0c9dccU, 0xfdb71852U, 0x4b2b2844U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x7b27b65aU, 0x1637db88U, 0x7f5fad37U, 0xd95a10cbU); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_InstData[0] = SCE->REG_100H; + R_SCE_func102(0x12cb3374U, 0x16325920U, 0xb1786dafU, 0xcc806b30U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pdf_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe0.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe0.c new file mode 100644 index 0000000000..e9b40e390e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe0.c @@ -0,0 +1,1487 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsRootCertificateVerificationSub(uint32_t *InData_Sel_PubKeyType, uint32_t *InData_Certificates, uint32_t *InData_CertificatesLength, uint32_t *InData_Signature, uint32_t *InData_CertificatesInfo, uint32_t length, uint32_t *OutData_PubKey) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)length; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e002U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + R_SCE_func100(0x2371b7edU, 0x6272bd79U, 0xfc7b9804U, 0x39d8853eU); + R_SCE_func103(); + R_SCE_func100(0x26a9adc7U, 0x44115aebU, 0xdcb1b9f3U, 0x6f8bd6d9U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01090c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800101e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Sel_PubKeyType[0]; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x38000defU; + SCE->REG_ECH = 0x1000d3e0U; + SCE->REG_ECH = 0x380089e0U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x66515816U, 0xba82a87bU, 0x4d3ca0bdU, 0x0e2e0b69U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x878abce1U, 0x8b5d8020U, 0x22582ebfU, 0xc8d788a5U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xb064c1c6U, 0x316ee407U, 0xd55c5863U, 0x01ddcec7U); + SCE->REG_104H = 0x00000468U; + SCE->REG_E0H = 0x800502c0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CertificatesLength[0]; + for (iLoop = 0; iLoop < 4; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CertificatesInfo[iLoop + 0]; + } + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_ECH = 0x3c002af8U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b19U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b59U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x3c002b56U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x00003417U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x000000ffU; + SCE->REG_ECH = 0x08002818U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00003419U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x0c00281aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func101(0x24898a4bU, 0xbd1494c1U, 0xcaabc15cU, 0xa1215d56U); + } + else + { + SCE->REG_ECH = 0x3c002af8U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b19U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b3aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b56U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x00003417U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x08002818U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00003419U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x0800281aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func101(0x69561b3eU, 0x36dcac61U, 0x3457d481U, 0xf1bcf5e3U); + } + R_SCE_func100(0x8a162f8eU, 0x6c038816U, 0x6a09cc83U, 0xbfd556b0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x56a62d7fU, 0xbfa8e901U, 0x79f573a1U, 0xfa77f228U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e0U); + R_SCE_func101(0x21bfcf8aU, 0x9e1b4c77U, 0x67dcbbaeU, 0x9f4aaa76U); + R_SCE_func043(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x01ba9fa3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e0U); + R_SCE_func101(0x1a03e686U, 0xb01c7b0bU, 0x9c49dc62U, 0xc0a911c7U); + R_SCE_func044(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x01000001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000004U); + R_SCE_func101(0x1fd2d326U, 0x7d1aba23U, 0xe1d1c4aeU, 0x7ae7ef2bU); + R_SCE_func044(); + R_SCE_func100(0x959342faU, 0xa6b3df3fU, 0x39b514f6U, 0xb1fd25f8U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + SCE->REG_104H = 0x00007f62U; + SCE->REG_D0H = 0x40001f00U; + SCE->REG_C4H = 0x02f087b7U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST[1+iLoop + 0]; + SCE->REG_100H = S_INST[1+iLoop + 1]; + SCE->REG_100H = S_INST[1+iLoop + 2]; + SCE->REG_100H = S_INST[1+iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + for (; iLoop < 128; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST[1+iLoop + 0]; + SCE->REG_100H = S_INST[1+iLoop + 1]; + SCE->REG_100H = S_INST[1+iLoop + 2]; + SCE->REG_100H = S_INST[1+iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST[1+iLoop + 0]; + SCE->REG_100H = S_INST[1+iLoop + 1]; + SCE->REG_100H = S_INST[1+iLoop + 2]; + SCE->REG_100H = S_INST[1+iLoop + 3]; + iLoop = iLoop+4; + SCE->REG_E0H = 0x80040140U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST[1+iLoop + 0]; + SCE->REG_100H = S_INST[1+iLoop + 1]; + SCE->REG_100H = S_INST[1+iLoop + 2]; + SCE->REG_100H = S_INST[1+iLoop + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_74H = 0x00000002U; + SCE->REG_ECH = 0x00003417U; + SCE->REG_ECH = 0x00046800U; + SCE->REG_ECH = 0x00026c00U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000008a5U; + for (iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + SCE->REG_104H = 0x00000364U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Certificates[iLoop + 0]; + SCE->REG_100H = InData_Certificates[iLoop + 1]; + SCE->REG_100H = InData_Certificates[iLoop + 2]; + SCE->REG_100H = InData_Certificates[iLoop + 3]; + SCE->REG_ECH = 0x0000a4a0U; + SCE->REG_ECH = 0x00000004U; + R_SCE_func101(0x3a9374ddU, 0xcb0d3a44U, 0x2c81df2cU, 0x9500cc5eU); + } + R_SCE_func100(0x740c6fe3U, 0xd23d1089U, 0x35f82430U, 0xdcb7c46aU); + SCE->REG_ECH = 0x38000805U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x4cae2ba0U, 0x0f3885e9U, 0x47cd9a26U, 0x112f231bU); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_ECH = 0x00003416U; + SCE->REG_ECH = 0x00026800U; + SCE->REG_ECH = 0x38008ec0U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x20002c00U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x00003445U; + SCE->REG_ECH = 0x00026c42U; + SCE->REG_ECH = 0x000034d6U; + SCE->REG_ECH = 0x000030c0U; + SCE->REG_ECH = 0x00000a10U; + for (; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Certificates[iLoop + 0]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + for (jLoop = 0; jLoop < 4; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x00003020U; + SCE->REG_ECH = 0x01886ce8U; + SCE->REG_ECH = 0x00086d08U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c002859U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x3c002b42U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x30000c63U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x00186ce7U; + SCE->REG_ECH = 0x01886e07U; + SCE->REG_ECH = 0x001868e7U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c002857U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x3c002b02U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x1e586482U, 0x505cf219U, 0xfe5da9e3U, 0x895e57b9U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x4d7c545fU, 0x1a23a336U, 0x813072b8U, 0xb95c42d2U); + } + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c0028c2U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xec025d6cU, 0x801eb789U, 0x347b58f6U, 0x373e1899U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xe5f8eb70U, 0x147f8087U, 0xf22e1dd9U, 0x7be2bb4fU); + } + SCE->REG_ECH = 0x00002c40U; + R_SCE_func101(0xa5e2d6d4U, 0x2009eb35U, 0xf032f142U, 0x505b1c3aU); + } + SCE->REG_ECH = 0x08000c21U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00002ca0U; + R_SCE_func101(0xbe8439a2U, 0x6bdfc436U, 0x9662e70fU, 0x243c6edaU); + } + SCE->REG_ECH = 0x38000805U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func101(0xa38ef5deU, 0x734f61e7U, 0x1d0ea811U, 0x1ec114f3U); + } + else + { + R_SCE_func100(0x3e7d9c13U, 0x83d53570U, 0xd392fed2U, 0xb140e6c3U); + SCE->REG_28H = 0x008f0001U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_ECH = 0x00003416U; + SCE->REG_ECH = 0x00026800U; + SCE->REG_ECH = 0x38008ec0U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x20002c00U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x00003445U; + SCE->REG_ECH = 0x00026c42U; + SCE->REG_ECH = 0x000034d6U; + SCE->REG_ECH = 0x000030c0U; + SCE->REG_ECH = 0x00000a10U; + for (; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Certificates[iLoop + 0]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + for (jLoop = 0; jLoop < 4; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x00003020U; + SCE->REG_ECH = 0x01886ce8U; + SCE->REG_ECH = 0x00086d08U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c002859U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x3c002b42U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xd33f3aa7U, 0x40bc0260U, 0x46b91350U, 0xc08b815eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xd55dab2cU, 0xe3f35323U, 0x246d6010U, 0x3fc988abU); + } + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c002857U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x3c002b02U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x9841900bU, 0x07651becU, 0x70b70563U, 0x94b08159U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x28406a2bU, 0x60d747ddU, 0x9d064e52U, 0x31e11afdU); + } + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c0028c2U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x904194a8U, 0xc8b145c8U, 0x6f5c4f30U, 0x5b9b43fcU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x2c682db1U, 0xf1d227d7U, 0x69ead2c9U, 0xb37ec3bbU); + } + SCE->REG_ECH = 0x00002c40U; + R_SCE_func101(0xdc68bbb9U, 0xc303dc2aU, 0xfeb15896U, 0x366425e4U); + } + SCE->REG_ECH = 0x08000c21U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00002ca0U; + R_SCE_func101(0x7bc527baU, 0x3de115edU, 0x0d17bcb7U, 0x88b87563U); + } + SCE->REG_ECH = 0x38000805U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func101(0xd332f609U, 0xe239426eU, 0x447e4227U, 0xfe8457acU); + } + R_SCE_func100(0x653e1f32U, 0x1de3332fU, 0xe4818756U, 0xaeb023cfU); + SCE->REG_ECH = 0x00003416U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00002840U; + SCE->REG_E0H = 0x81010040U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000008a5U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x80000000U; + for (iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_E0H = 0x81010060U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00086c63U; + SCE->REG_ECH = 0x00002ca0U; + R_SCE_func101(0x855fa33cU, 0x2c4b6404U, 0x1f2d89f5U, 0x32c2a2f6U); + } + R_SCE_func100(0x43b5b359U, 0x68f8d181U, 0xbf4e767cU, 0xcb9a4f56U); + SCE->REG_ECH = 0x38000845U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_F8H = 0x00000040U; + SCE->REG_ECH = 0x00000800U; + SCE->REG_ECH = 0x00003436U; + SCE->REG_ECH = 0x01836c01U; + SCE->REG_ECH = 0x00036c21U; + SCE->REG_E0H = 0x81020000U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0xd51de90fU, 0x869b0976U, 0xf3b5c8ffU, 0x8603a1dfU); + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42e097bfU; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000202U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0xe5d8bcf1U, 0xe0796193U, 0xb27bce2cU, 0xca6a2a6bU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400019cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + R_SCE_func101(0xd4fca22dU, 0xaf2b9859U, 0x0e3a386cU, 0x3c678019U); + } + else + { + R_SCE_func100(0x03c80255U, 0x531d045eU, 0x573c5ebaU, 0xe90208e8U); + SCE->REG_D0H = 0x00000300U; + SCE->REG_C4H = 0x42e097bfU; + SCE->REG_00H = 0x00002343U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000242U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0xc340fa3cU, 0xb6ac91acU, 0x9c875708U, 0x6af4b668U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400019cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func101(0xed9bbae3U, 0x320781d0U, 0xb4ca91b9U, 0x6a572aeaU); + } + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00003f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[0]; + SCE->REG_100H = InData_Signature[1]; + SCE->REG_100H = InData_Signature[2]; + SCE->REG_100H = InData_Signature[3]; + SCE->REG_100H = InData_Signature[4]; + SCE->REG_100H = InData_Signature[5]; + SCE->REG_100H = InData_Signature[6]; + SCE->REG_100H = InData_Signature[7]; + SCE->REG_100H = InData_Signature[8]; + SCE->REG_100H = InData_Signature[9]; + SCE->REG_100H = InData_Signature[10]; + SCE->REG_100H = InData_Signature[11]; + SCE->REG_100H = InData_Signature[12]; + SCE->REG_100H = InData_Signature[13]; + SCE->REG_100H = InData_Signature[14]; + SCE->REG_100H = InData_Signature[15]; + SCE->REG_100H = InData_Signature[16]; + SCE->REG_100H = InData_Signature[17]; + SCE->REG_100H = InData_Signature[18]; + SCE->REG_100H = InData_Signature[19]; + SCE->REG_100H = InData_Signature[20]; + SCE->REG_100H = InData_Signature[21]; + SCE->REG_100H = InData_Signature[22]; + SCE->REG_100H = InData_Signature[23]; + SCE->REG_100H = InData_Signature[24]; + SCE->REG_100H = InData_Signature[25]; + SCE->REG_100H = InData_Signature[26]; + SCE->REG_100H = InData_Signature[27]; + SCE->REG_100H = InData_Signature[28]; + SCE->REG_100H = InData_Signature[29]; + SCE->REG_100H = InData_Signature[30]; + SCE->REG_100H = InData_Signature[31]; + SCE->REG_100H = InData_Signature[32]; + SCE->REG_100H = InData_Signature[33]; + SCE->REG_100H = InData_Signature[34]; + SCE->REG_100H = InData_Signature[35]; + SCE->REG_100H = InData_Signature[36]; + SCE->REG_100H = InData_Signature[37]; + SCE->REG_100H = InData_Signature[38]; + SCE->REG_100H = InData_Signature[39]; + SCE->REG_100H = InData_Signature[40]; + SCE->REG_100H = InData_Signature[41]; + SCE->REG_100H = InData_Signature[42]; + SCE->REG_100H = InData_Signature[43]; + SCE->REG_100H = InData_Signature[44]; + SCE->REG_100H = InData_Signature[45]; + SCE->REG_100H = InData_Signature[46]; + SCE->REG_100H = InData_Signature[47]; + SCE->REG_100H = InData_Signature[48]; + SCE->REG_100H = InData_Signature[49]; + SCE->REG_100H = InData_Signature[50]; + SCE->REG_100H = InData_Signature[51]; + SCE->REG_100H = InData_Signature[52]; + SCE->REG_100H = InData_Signature[53]; + SCE->REG_100H = InData_Signature[54]; + SCE->REG_100H = InData_Signature[55]; + SCE->REG_100H = InData_Signature[56]; + SCE->REG_100H = InData_Signature[57]; + SCE->REG_100H = InData_Signature[58]; + SCE->REG_100H = InData_Signature[59]; + SCE->REG_100H = InData_Signature[60]; + SCE->REG_100H = InData_Signature[61]; + SCE->REG_100H = InData_Signature[62]; + SCE->REG_100H = InData_Signature[63]; + SCE->REG_ECH = 0x0000342aU; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000000e0U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x000000f0U; + SCE->REG_E0H = 0x81840007U; + SCE->REG_C4H = 0x00000885U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80040100U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x6520f9b6U, 0xd7f6a708U, 0x997b69c0U, 0x465419fcU); + R_SCE_TlsRootCertificateVerificationSubSub(); + + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x000000f0U; + SCE->REG_E0H = 0x81040100U; + SCE->REG_C4H = 0x00000885U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80840007U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xaa73062aU, 0x8e330412U, 0x6a926048U, 0xd4e62a73U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2dcb2ec3U, 0x03f5c58fU, 0x09053cafU, 0x5e69c55cU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xd3bb9320U, 0x4cc89f41U, 0xda823e6eU, 0xc124fe79U); + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0xa30c0768U, 0x4dd11d4bU, 0x4ad4936bU, 0x8a9e0636U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42f097bfU; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x00005004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01050801U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030020U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e0U); + R_SCE_func101(0x23c066cfU, 0xc7cb3c72U, 0xb5efb75fU, 0x48ff625eU); + R_SCE_func059(); + R_SCE_func100(0xca1d14a3U, 0x8772c5ceU, 0xde55afe8U, 0x3f437e04U); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000202U; + for (iLoop = 4; iLoop < 68; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0xe07566c8U, 0xc322a98bU, 0xb4eb4af2U, 0x30bf659aU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000202U; + for (; iLoop < 132; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x05ac9a90U, 0x612ba53bU, 0x8381d5a1U, 0x59efe3eeU); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e087b4U; + SCE->REG_E0H = 0x81010200U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0x8c360eeeU, 0xfe2fceb1U, 0xca255c25U, 0x825f4157U); + iLoop = iLoop+4; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0x079a95caU, 0x5dd49aeaU, 0x6a38d9d8U, 0xf0f28cdaU); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[3] = SCE->REG_100H; + R_SCE_func102(0x6ea8c435U, 0x5bd2084eU, 0x6b6d9e75U, 0x8947a61eU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x00000b9cU; + OFS_ADR = 128; + R_SCE_func100(0x18dde013U, 0x23867526U, 0x8df1c8a1U, 0xae8d6b1eU); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x008f0001U; + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x00000300U; + SCE->REG_C4H = 0x42f097bfU; + SCE->REG_00H = 0x00003243U; + SCE->REG_2CH = 0x00000010U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func008(); + R_SCE_func100(0x083d3c66U, 0x2396b2c5U, 0xe1147f0cU, 0xc4fa26feU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb520657bU, 0xc8aed843U, 0x96499ebcU, 0x0427341eU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x8f2556b7U, 0x6ceb627fU, 0x94c1f559U, 0x9ef61d40U); + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000404U; + SCE->REG_24H = 0x80009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x008f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01310801U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030020U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000030U); + R_SCE_func101(0x38278e23U, 0x3ec0949dU, 0x0448e630U, 0x9f92d3f3U); + R_SCE_func059(); + R_SCE_func100(0x235d4601U, 0x85bf4f7cU, 0x4bc35a5dU, 0xe7a15bdaU); + SCE->REG_00H = 0x00002343U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000242U; + for (iLoop = 4; iLoop < 20; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x46017b0aU, 0xb7571533U, 0xa0c304f7U, 0xf16246ccU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0x42c32d5bU, 0xc5718df0U, 0x3f71aac3U, 0x9ed04c33U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[3] = SCE->REG_100H; + R_SCE_func102(0xc954a99cU, 0x1e9c3dc7U, 0x4a9cdce6U, 0x6d4ebf07U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe0_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe1.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe1.c new file mode 100644 index 0000000000..c710389405 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe1.c @@ -0,0 +1,1771 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsCertificateVerificationSub(uint32_t *InData_Sel_PubKeyType, uint32_t *InData_PubKey, uint32_t *InData_TBSCertificate, uint32_t *InData_TBSCertificateLength, uint32_t *InData_Signature, uint32_t *InData_TBSCertificateInfo, uint32_t length, uint32_t *OutData_PubKey) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)length; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e102U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + R_SCE_func100(0xef052e03U, 0x240fa96cU, 0xc54ba1d1U, 0xa3fe0d51U); + R_SCE_func103(); + R_SCE_func100(0xbf513907U, 0x8fc5768dU, 0xeeab50f9U, 0x918bc84cU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01090c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800101e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Sel_PubKeyType[0]; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x38000defU; + SCE->REG_ECH = 0x1000d3e0U; + SCE->REG_ECH = 0x380089e0U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xa27f8bbbU, 0xa1919d58U, 0x513a62c9U, 0xc008ee36U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x01ded869U, 0x6aa5a125U, 0x26b16d94U, 0x4a9c1befU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xd6bc5519U, 0x6f508f1eU, 0xeb578458U, 0x945087f6U); + SCE->REG_104H = 0x00000468U; + SCE->REG_E0H = 0x800502c0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TBSCertificateLength[0]; + for (iLoop = 0; iLoop < 4; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TBSCertificateInfo[iLoop + 0]; + } + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_ECH = 0x3c002af8U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b19U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b59U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x3c002b56U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x00003417U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x000000ffU; + SCE->REG_ECH = 0x08002818U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00003419U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x0c00281aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func101(0x90cc7471U, 0x6152a3dcU, 0xa01a9648U, 0xb3dc31cdU); + } + else + { + SCE->REG_ECH = 0x3c002af8U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b19U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b3aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x3c002b56U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x00003417U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x08002818U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00003419U; + SCE->REG_ECH = 0x0000a400U; + SCE->REG_ECH = 0x0000001fU; + SCE->REG_ECH = 0x0800281aU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func101(0x03fd5729U, 0x124feb7eU, 0x484a0c88U, 0x88e1fb74U); + } + R_SCE_func100(0xd50ea903U, 0xdc3a4088U, 0xd18d8cffU, 0xdc96b385U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xfc9660beU, 0x2810541bU, 0x39a11812U, 0xe1542928U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00050000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x10000a31U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00310000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x1000b620U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x3800d80bU; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000ffU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x88a74c91U, 0x315e3786U, 0x60a03d05U, 0xc1058e89U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x948f2158U, 0x32cc45cfU, 0x7d3a2378U, 0x7e7acc5fU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e1U); + R_SCE_func101(0x6f8645f8U, 0x0ca19a85U, 0x5cf217b4U, 0x6e65a90dU); + R_SCE_func059(); + R_SCE_func100(0x3da99d57U, 0xaab13e6fU, 0x44edf808U, 0x5f5ca63dU); + SCE->REG_ECH = 0x00007c11U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00008362U; + SCE->REG_D0H = 0x40001f00U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+68 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + for (iLoop = 0; iLoop < 4; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+132 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 3]; + } + SCE->REG_E0H = 0x80010140U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[136]; + SCE->REG_100H = InData_PubKey[137]; + SCE->REG_100H = InData_PubKey[138]; + SCE->REG_100H = InData_PubKey[139]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xb3886ce3U, 0x517400a5U, 0x55fe4528U, 0xdb07c918U); + } + else + { + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009bU; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000012U; + for (iLoop = 8; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[20]; + SCE->REG_100H = InData_PubKey[21]; + SCE->REG_100H = InData_PubKey[22]; + SCE->REG_100H = InData_PubKey[23]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x7514f548U, 0x17192abeU, 0x2901bb8bU, 0x629e6a2aU); + } + R_SCE_func100(0xd685dcf6U, 0xd06f2b31U, 0x67b4aff4U, 0xea1fdab0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x7f4c0e01U, 0xa0c58818U, 0x3e7f7c75U, 0x966b7571U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xa3daa30eU, 0x49300241U, 0xfc9f537fU, 0x69c2b99fU); + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_74H = 0x00000002U; + SCE->REG_ECH = 0x00003417U; + SCE->REG_ECH = 0x00046800U; + SCE->REG_ECH = 0x00026c00U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000008a5U; + for (iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 4) + { + SCE->REG_104H = 0x00000364U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TBSCertificate[iLoop + 0]; + SCE->REG_100H = InData_TBSCertificate[iLoop + 1]; + SCE->REG_100H = InData_TBSCertificate[iLoop + 2]; + SCE->REG_100H = InData_TBSCertificate[iLoop + 3]; + SCE->REG_ECH = 0x0000a4a0U; + SCE->REG_ECH = 0x00000004U; + R_SCE_func101(0x027ff99cU, 0xfafccfe6U, 0xd3963506U, 0x1bd74cf4U); + } + R_SCE_func100(0xcc802844U, 0x52852bfeU, 0x78931bb3U, 0x99121dc0U); + SCE->REG_ECH = 0x38000805U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x5ca379d6U, 0x0e2d51bfU, 0x4116161bU, 0xb8aea971U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_ECH = 0x00003416U; + SCE->REG_ECH = 0x00026800U; + SCE->REG_ECH = 0x38008ec0U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x20002c00U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x00003445U; + SCE->REG_ECH = 0x00026c42U; + SCE->REG_ECH = 0x000034d6U; + SCE->REG_ECH = 0x000030c0U; + SCE->REG_ECH = 0x00000a10U; + for (; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TBSCertificate[iLoop + 0]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + for (jLoop = 0; jLoop < 4; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x00003020U; + SCE->REG_ECH = 0x01886ce8U; + SCE->REG_ECH = 0x00086d08U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c002859U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x3c002b42U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x30000c63U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x00186ce7U; + SCE->REG_ECH = 0x01886e07U; + SCE->REG_ECH = 0x001868e7U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c002857U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x3c002b02U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xaa4535c8U, 0x96c5f49bU, 0xd27cb1faU, 0x26a36d3dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x1aa528a5U, 0xb67f7933U, 0x4f40c9f8U, 0x73cb3da2U); + } + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c0028c2U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x88f0b169U, 0x4a785c63U, 0x14fe8d51U, 0xa2932d04U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x675a0664U, 0x56e96b14U, 0x52cbc4f1U, 0xafc84c9bU); + } + SCE->REG_ECH = 0x00002c40U; + R_SCE_func101(0x76fd9fa7U, 0xcc4f60a5U, 0x9861aa93U, 0x9ab3ff64U); + } + SCE->REG_ECH = 0x08000c21U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00002ca0U; + R_SCE_func101(0x1d5c098fU, 0x3889d9bbU, 0x1214915eU, 0x5b554333U); + } + SCE->REG_ECH = 0x38000805U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func101(0x08f72ff1U, 0x286b46deU, 0x33955155U, 0x5a12feadU); + } + else + { + R_SCE_func100(0x2d4df4adU, 0x875c19b9U, 0xe875d798U, 0x3264edaeU); + SCE->REG_28H = 0x008f0001U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_ECH = 0x00003416U; + SCE->REG_ECH = 0x00026800U; + SCE->REG_ECH = 0x38008ec0U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x20002c00U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x00003445U; + SCE->REG_ECH = 0x00026c42U; + SCE->REG_ECH = 0x000034d6U; + SCE->REG_ECH = 0x000030c0U; + SCE->REG_ECH = 0x00000a10U; + for (; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010100U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TBSCertificate[iLoop + 0]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + for (jLoop = 0; jLoop < 4; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x00003020U; + SCE->REG_ECH = 0x01886ce8U; + SCE->REG_ECH = 0x00086d08U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c002859U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x3c002b42U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x4fd6948dU, 0x023fb7d5U, 0xd49baf7bU, 0x0c4e82ddU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xe2dbafa3U, 0x2e8eefefU, 0x36f680aeU, 0x90258c36U); + } + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c002857U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x3c002b02U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x30aafe58U, 0x199e2254U, 0xadee54fcU, 0x5fe4cb8aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x07c2d547U, 0x1a578abdU, 0x55b39de7U, 0x514d4e68U); + } + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x3c0028c2U; + SCE->REG_ECH = 0x20002c60U; + SCE->REG_ECH = 0x38000c63U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xa7ce9d3cU, 0x7ac71894U, 0x6ef062f3U, 0xdddd9f83U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_E0H = 0x810100e0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0xfc401ce9U, 0x8193a542U, 0x580b2549U, 0x1045b077U); + } + SCE->REG_ECH = 0x00002c40U; + R_SCE_func101(0xb01873a9U, 0xf891bfc8U, 0x2ccbaea7U, 0xf254191aU); + } + SCE->REG_ECH = 0x08000c21U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_ECH = 0x00002ca0U; + R_SCE_func101(0xa4b10905U, 0x7047ab0aU, 0xc4772532U, 0xbb0bbca2U); + } + SCE->REG_ECH = 0x38000805U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func101(0xfa13891eU, 0x4c2045deU, 0x0a80752eU, 0xbeaaa9f1U); + } + R_SCE_func100(0x43778663U, 0xc3616dc7U, 0x001b20cbU, 0x3897a204U); + SCE->REG_ECH = 0x00003416U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x0000b440U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00002840U; + SCE->REG_E0H = 0x81010040U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000008a5U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x80000000U; + for (iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_E0H = 0x81010060U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00086c63U; + SCE->REG_ECH = 0x00002ca0U; + R_SCE_func101(0x7dd8ff61U, 0x5ce07b00U, 0xd9ed8f0cU, 0xfaa940c0U); + } + R_SCE_func100(0x03df2cd2U, 0x82be7aa1U, 0x37843aefU, 0xaa2f7b14U); + SCE->REG_ECH = 0x38000845U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_1CH = 0x00402000U; + SCE->REG_F8H = 0x00000040U; + SCE->REG_ECH = 0x00000800U; + SCE->REG_ECH = 0x00003436U; + SCE->REG_ECH = 0x01836c01U; + SCE->REG_ECH = 0x00036c21U; + SCE->REG_E0H = 0x81020000U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x9b028911U, 0x587d62a1U, 0x8fdaa628U, 0x33e80c92U); + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42e097bfU; + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000202U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop+68 + 0] = SCE->REG_100H; + S_HEAP[iLoop+68 + 1] = SCE->REG_100H; + S_HEAP[iLoop+68 + 2] = SCE->REG_100H; + S_HEAP[iLoop+68 + 3] = SCE->REG_100H; + } + R_SCE_func100(0x1564a25fU, 0xc4816d45U, 0x570efae3U, 0x530862d1U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400019cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop+68 + 0] = SCE->REG_100H; + S_HEAP[iLoop+68 + 1] = SCE->REG_100H; + S_HEAP[iLoop+68 + 2] = SCE->REG_100H; + S_HEAP[iLoop+68 + 3] = SCE->REG_100H; + R_SCE_func101(0xd04dc59eU, 0x8f47cd2fU, 0x8657a204U, 0xf714e8b5U); + } + else + { + R_SCE_func100(0xbb79836bU, 0xa316c4f9U, 0xaba66a89U, 0x3f398b80U); + SCE->REG_D0H = 0x00000300U; + SCE->REG_C4H = 0x42e097bfU; + SCE->REG_00H = 0x00002343U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000242U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop+68 + 0] = SCE->REG_100H; + S_HEAP[iLoop+68 + 1] = SCE->REG_100H; + S_HEAP[iLoop+68 + 2] = SCE->REG_100H; + S_HEAP[iLoop+68 + 3] = SCE->REG_100H; + } + R_SCE_func100(0xc87a9a37U, 0x59e6f29fU, 0xc0d49986U, 0x0ac9d256U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400019cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop+68 + 0] = SCE->REG_100H; + S_HEAP[iLoop+68 + 1] = SCE->REG_100H; + S_HEAP[iLoop+68 + 2] = SCE->REG_100H; + S_HEAP[iLoop+68 + 3] = SCE->REG_100H; + R_SCE_func101(0xc49ceca9U, 0xeb905358U, 0xce61a5adU, 0x3e5462cbU); + } + R_SCE_func100(0xbd2bf945U, 0x6870cf38U, 0x25ccd117U, 0x456d8a5aU); + SCE->REG_ECH = 0x00007c11U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0xc3b5dabfU, 0xc6161d9fU, 0xa9c4e77bU, 0x520d4cd9U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00003f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[0]; + SCE->REG_100H = InData_Signature[1]; + SCE->REG_100H = InData_Signature[2]; + SCE->REG_100H = InData_Signature[3]; + SCE->REG_100H = InData_Signature[4]; + SCE->REG_100H = InData_Signature[5]; + SCE->REG_100H = InData_Signature[6]; + SCE->REG_100H = InData_Signature[7]; + SCE->REG_100H = InData_Signature[8]; + SCE->REG_100H = InData_Signature[9]; + SCE->REG_100H = InData_Signature[10]; + SCE->REG_100H = InData_Signature[11]; + SCE->REG_100H = InData_Signature[12]; + SCE->REG_100H = InData_Signature[13]; + SCE->REG_100H = InData_Signature[14]; + SCE->REG_100H = InData_Signature[15]; + SCE->REG_100H = InData_Signature[16]; + SCE->REG_100H = InData_Signature[17]; + SCE->REG_100H = InData_Signature[18]; + SCE->REG_100H = InData_Signature[19]; + SCE->REG_100H = InData_Signature[20]; + SCE->REG_100H = InData_Signature[21]; + SCE->REG_100H = InData_Signature[22]; + SCE->REG_100H = InData_Signature[23]; + SCE->REG_100H = InData_Signature[24]; + SCE->REG_100H = InData_Signature[25]; + SCE->REG_100H = InData_Signature[26]; + SCE->REG_100H = InData_Signature[27]; + SCE->REG_100H = InData_Signature[28]; + SCE->REG_100H = InData_Signature[29]; + SCE->REG_100H = InData_Signature[30]; + SCE->REG_100H = InData_Signature[31]; + SCE->REG_100H = InData_Signature[32]; + SCE->REG_100H = InData_Signature[33]; + SCE->REG_100H = InData_Signature[34]; + SCE->REG_100H = InData_Signature[35]; + SCE->REG_100H = InData_Signature[36]; + SCE->REG_100H = InData_Signature[37]; + SCE->REG_100H = InData_Signature[38]; + SCE->REG_100H = InData_Signature[39]; + SCE->REG_100H = InData_Signature[40]; + SCE->REG_100H = InData_Signature[41]; + SCE->REG_100H = InData_Signature[42]; + SCE->REG_100H = InData_Signature[43]; + SCE->REG_100H = InData_Signature[44]; + SCE->REG_100H = InData_Signature[45]; + SCE->REG_100H = InData_Signature[46]; + SCE->REG_100H = InData_Signature[47]; + SCE->REG_100H = InData_Signature[48]; + SCE->REG_100H = InData_Signature[49]; + SCE->REG_100H = InData_Signature[50]; + SCE->REG_100H = InData_Signature[51]; + SCE->REG_100H = InData_Signature[52]; + SCE->REG_100H = InData_Signature[53]; + SCE->REG_100H = InData_Signature[54]; + SCE->REG_100H = InData_Signature[55]; + SCE->REG_100H = InData_Signature[56]; + SCE->REG_100H = InData_Signature[57]; + SCE->REG_100H = InData_Signature[58]; + SCE->REG_100H = InData_Signature[59]; + SCE->REG_100H = InData_Signature[60]; + SCE->REG_100H = InData_Signature[61]; + SCE->REG_100H = InData_Signature[62]; + SCE->REG_100H = InData_Signature[63]; + SCE->REG_18H = 0x00000004U; + SCE->REG_34H = 0x00000000U; + SCE->REG_38H = 0x00000338U; + SCE->REG_E0H = 0x81010140U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_104H = 0x00003757U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0001ffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0x00303130U); + SCE->REG_100H = change_endian_long(0x0d060960U); + SCE->REG_100H = change_endian_long(0x86480165U); + SCE->REG_100H = change_endian_long(0x03040201U); + SCE->REG_100H = change_endian_long(0x05000420U); + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func101(0xebb5d198U, 0x93f9c294U, 0xf8d14679U, 0x25243ab6U); + } + else + { + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x8000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_104H = 0x00000f68U; + SCE->REG_E0H = 0x8090001eU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[iLoop + 0]; + } + SCE->REG_ECH = 0x00000b9cU; + OFS_ADR = 128; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e1U); + R_SCE_func101(0x1c2d8b1eU, 0xf9269806U, 0x8613d8e4U, 0x03ce85baU); + R_SCE_func003_r1(InData_Signature); + R_SCE_func101(0x4a454aceU, 0xf9d43be9U, 0x6d591b60U, 0xf03d232dU); + } + R_SCE_func100(0x6704d999U, 0x3b3b30d9U, 0xdc32ab2fU, 0xf792c581U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb4e14136U, 0xf9f6c909U, 0x6d2f8225U, 0xd3aaf3d1U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x121ffac2U, 0xa11eac78U, 0x22ca680eU, 0xe8c43443U); + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x46d36418U, 0xd295a29cU, 0x82274183U, 0xb15f1f39U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00003f62U; + SCE->REG_D0H = 0x00000f00U; + SCE->REG_C4H = 0x42f097bfU; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+68 + 0]; + SCE->REG_100H = S_HEAP[iLoop+68 + 1]; + SCE->REG_100H = S_HEAP[iLoop+68 + 2]; + SCE->REG_100H = S_HEAP[iLoop+68 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+68 + 0]; + SCE->REG_100H = S_HEAP[iLoop+68 + 1]; + SCE->REG_100H = S_HEAP[iLoop+68 + 2]; + SCE->REG_100H = S_HEAP[iLoop+68 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000005c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x00005004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01058801U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030020U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000031U); + R_SCE_func101(0x93294027U, 0x2b1b7a91U, 0xc5bb9331U, 0xac005bc3U); + R_SCE_func059(); + R_SCE_func100(0xc7411328U, 0xd0056c8aU, 0xf634844aU, 0xf9a330ceU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000024U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000202U; + for (iLoop = 4; iLoop < 68; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0x5d566accU, 0x3511b249U, 0x606e726fU, 0x43a5c67bU); + SCE->REG_00H = 0x00012303U; + SCE->REG_2CH = 0x00000022U; + SCE->REG_D0H = 0x40000f00U; + SCE->REG_C4H = 0x00e087b7U; + SCE->REG_04H = 0x00000202U; + for (; iLoop < 132; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0xc4df0317U, 0x61760657U, 0x520a41f0U, 0x9e900f43U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e087b4U; + SCE->REG_E0H = 0x81010200U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0x38ef57ceU, 0x4e2cdfe4U, 0xcb42f310U, 0x791c18bfU); + iLoop = iLoop+4; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0x91bbf9a6U, 0x9179b77cU, 0xc3bd67a1U, 0x03b4ae01U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[3] = SCE->REG_100H; + R_SCE_func102(0x24fd9247U, 0xab5e7c27U, 0x7b576b5bU, 0xd7404e59U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x00000b9cU; + OFS_ADR = 128; + R_SCE_func100(0x5cf8da3fU, 0x62ed1bdaU, 0x1c28f209U, 0x9cbaaf99U); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x008f0001U; + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x00000300U; + SCE->REG_C4H = 0x42f097bfU; + SCE->REG_00H = 0x00003243U; + SCE->REG_2CH = 0x00000010U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+68 + 0]; + SCE->REG_100H = S_HEAP[iLoop+68 + 1]; + SCE->REG_100H = S_HEAP[iLoop+68 + 2]; + SCE->REG_100H = S_HEAP[iLoop+68 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+68 + 0]; + SCE->REG_100H = S_HEAP[iLoop+68 + 1]; + SCE->REG_100H = S_HEAP[iLoop+68 + 2]; + SCE->REG_100H = S_HEAP[iLoop+68 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func008(); + R_SCE_func100(0x2b96475eU, 0x24d0fc12U, 0xe0559746U, 0x187e3af6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xca783692U, 0x91ab0ec7U, 0x8bd589acU, 0x09e75e98U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x22bf58b1U, 0xfeb6bea9U, 0x32741975U, 0xb4a11460U); + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000404U; + SCE->REG_24H = 0x80009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x008f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01310801U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030020U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000020U); + R_SCE_func101(0x5bd5fab7U, 0xeb5a38c5U, 0x80588e35U, 0x68f7839cU); + R_SCE_func059(); + R_SCE_func100(0xb3222b07U, 0x1a52c9a6U, 0xe0c5fb33U, 0xed989deeU); + SCE->REG_00H = 0x00002343U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000242U; + for (iLoop = 4; iLoop < 20; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x596ef83eU, 0x91ba2375U, 0xcc25c61cU, 0x73d04be2U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[iLoop + 0] = SCE->REG_100H; + OutData_PubKey[iLoop + 1] = SCE->REG_100H; + OutData_PubKey[iLoop + 2] = SCE->REG_100H; + OutData_PubKey[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0xb4dbcc80U, 0xe818c300U, 0x5d8f4fcaU, 0x7ef22a85U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[3] = SCE->REG_100H; + R_SCE_func102(0x90855fa8U, 0xe3f70507U, 0xd9811172U, 0x4b728c9dU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe1_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe2.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe2.c new file mode 100644 index 0000000000..3b023bf9be --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe2.c @@ -0,0 +1,637 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, uint32_t *InData_PreMasterSecret, uint32_t *OutData_PreMasterSecret) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e202U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00050000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x3800d80fU; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000ffU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x005628bdU, 0x8a27a8d0U, 0x905e1fc2U, 0x76697d45U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x2c161f67U, 0x2447ead2U, 0x547bb529U, 0x5688a5eeU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[3]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e2U); + R_SCE_func101(0x98596d75U, 0x5189c6e8U, 0xa41d4275U, 0x92fa3206U); + R_SCE_func059(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0154569cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e2U); + R_SCE_func101(0xef911932U, 0x2487de81U, 0xd0dc90d1U, 0xbe5963daU); + R_SCE_func044(); + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[4]; + SCE->REG_100H = InData_PreMasterSecret[5]; + SCE->REG_100H = InData_PreMasterSecret[6]; + SCE->REG_100H = InData_PreMasterSecret[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[8]; + SCE->REG_100H = InData_PreMasterSecret[9]; + SCE->REG_100H = InData_PreMasterSecret[10]; + SCE->REG_100H = InData_PreMasterSecret[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[12]; + SCE->REG_100H = InData_PreMasterSecret[13]; + SCE->REG_100H = InData_PreMasterSecret[14]; + SCE->REG_100H = InData_PreMasterSecret[15]; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x808c0004U; + SCE->REG_00H = 0x00008233U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[16]; + SCE->REG_100H = InData_PreMasterSecret[17]; + SCE->REG_100H = InData_PreMasterSecret[18]; + SCE->REG_100H = InData_PreMasterSecret[19]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x4dc8a4d7U, 0xdb76879eU, 0xb551ef4aU, 0x8e1f272eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x68a2f4e0U, 0x579ea402U, 0x54645b27U, 0x47a7be32U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000033U); + R_SCE_func101(0x3b251d0aU, 0xfa0f3fc1U, 0xca291eb5U, 0xbce85ebbU); + R_SCE_func059(); + SCE->REG_28H = 0x00bf0001U; + R_SCE_func100(0xa1920ec8U, 0xd98054ceU, 0x30ffcea1U, 0x02225004U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00008c00U; + SCE->REG_ECH = 0x0000ffffU; + SCE->REG_ECH = 0x00009000U; + SCE->REG_ECH = 0x00028080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_00H = 0x00003807U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x01020408U; + SCE->REG_ECH = 0x0000b4a0U; + SCE->REG_ECH = 0x10204080U; + SCE->REG_ECH = 0x0000b4c0U; + SCE->REG_ECH = 0x80200802U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x40100401U; + SCE->REG_ECH = 0x00000bdeU; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 1) + { + R_SCE_func100(0x5bd4d0fdU, 0xae6b3e6bU, 0xb8181053U, 0x0fd28120U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00001004U; + SCE->REG_ECH = 0x00001025U; + SCE->REG_ECH = 0x00001046U; + SCE->REG_ECH = 0x00001067U; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00003813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002fc0U; + R_SCE_func101(0xc0a8f0c1U, 0xc42d345aU, 0xc8c657a1U, 0xba5cf61fU); + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x0000000CU; + SCE->REG_ECH = 0x38000bdfU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_1CH = 0x00402000U; + R_SCE_func100(0x39eeb6a8U, 0xdcf76541U, 0x917b2452U, 0xd3b48a54U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030000U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00001004U; + SCE->REG_ECH = 0x00001025U; + SCE->REG_ECH = 0x00001046U; + SCE->REG_E0H = 0x80010140U; + SCE->REG_104H = 0x00000058U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffff00U); + SCE->REG_ECH = 0x00000c4aU; + SCE->REG_E0H = 0x81030000U; + SCE->REG_00H = 0x0000380fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x818c0001U; + SCE->REG_00H = 0x00003833U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00008362U; + SCE->REG_D0H = 0x40001f00U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+68 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + for (iLoop = 0; iLoop < 4; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+132 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 3]; + } + SCE->REG_E0H = 0x800100a0U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[136]; + SCE->REG_100H = InData_PubKey[137]; + SCE->REG_100H = InData_PubKey[138]; + SCE->REG_100H = InData_PubKey[139]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xb629d2c3U, 0xd93838caU, 0xe271a7d0U, 0x32a2cd0dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x760bc72bU, 0x4ee8cb9bU, 0x18714374U, 0x12001ccdU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x691066faU, 0x21763fa7U, 0xfcff045bU, 0x9cd65631U); + SCE->REG_18H = 0x00000004U; + SCE->REG_34H = 0x00000000U; + SCE->REG_38H = 0x00000338U; + SCE->REG_E0H = 0x810100a0U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func100(0x79834932U, 0xb044a0deU, 0x4b1ad868U, 0xf0dd49e6U); + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000302U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecret[0] = SCE->REG_100H; + OutData_PreMasterSecret[1] = SCE->REG_100H; + OutData_PreMasterSecret[2] = SCE->REG_100H; + OutData_PreMasterSecret[3] = SCE->REG_100H; + OutData_PreMasterSecret[4] = SCE->REG_100H; + OutData_PreMasterSecret[5] = SCE->REG_100H; + OutData_PreMasterSecret[6] = SCE->REG_100H; + OutData_PreMasterSecret[7] = SCE->REG_100H; + OutData_PreMasterSecret[8] = SCE->REG_100H; + OutData_PreMasterSecret[9] = SCE->REG_100H; + OutData_PreMasterSecret[10] = SCE->REG_100H; + OutData_PreMasterSecret[11] = SCE->REG_100H; + OutData_PreMasterSecret[12] = SCE->REG_100H; + OutData_PreMasterSecret[13] = SCE->REG_100H; + OutData_PreMasterSecret[14] = SCE->REG_100H; + OutData_PreMasterSecret[15] = SCE->REG_100H; + OutData_PreMasterSecret[16] = SCE->REG_100H; + OutData_PreMasterSecret[17] = SCE->REG_100H; + OutData_PreMasterSecret[18] = SCE->REG_100H; + OutData_PreMasterSecret[19] = SCE->REG_100H; + OutData_PreMasterSecret[20] = SCE->REG_100H; + OutData_PreMasterSecret[21] = SCE->REG_100H; + OutData_PreMasterSecret[22] = SCE->REG_100H; + OutData_PreMasterSecret[23] = SCE->REG_100H; + OutData_PreMasterSecret[24] = SCE->REG_100H; + OutData_PreMasterSecret[25] = SCE->REG_100H; + OutData_PreMasterSecret[26] = SCE->REG_100H; + OutData_PreMasterSecret[27] = SCE->REG_100H; + OutData_PreMasterSecret[28] = SCE->REG_100H; + OutData_PreMasterSecret[29] = SCE->REG_100H; + OutData_PreMasterSecret[30] = SCE->REG_100H; + OutData_PreMasterSecret[31] = SCE->REG_100H; + OutData_PreMasterSecret[32] = SCE->REG_100H; + OutData_PreMasterSecret[33] = SCE->REG_100H; + OutData_PreMasterSecret[34] = SCE->REG_100H; + OutData_PreMasterSecret[35] = SCE->REG_100H; + OutData_PreMasterSecret[36] = SCE->REG_100H; + OutData_PreMasterSecret[37] = SCE->REG_100H; + OutData_PreMasterSecret[38] = SCE->REG_100H; + OutData_PreMasterSecret[39] = SCE->REG_100H; + OutData_PreMasterSecret[40] = SCE->REG_100H; + OutData_PreMasterSecret[41] = SCE->REG_100H; + OutData_PreMasterSecret[42] = SCE->REG_100H; + OutData_PreMasterSecret[43] = SCE->REG_100H; + OutData_PreMasterSecret[44] = SCE->REG_100H; + OutData_PreMasterSecret[45] = SCE->REG_100H; + OutData_PreMasterSecret[46] = SCE->REG_100H; + OutData_PreMasterSecret[47] = SCE->REG_100H; + OutData_PreMasterSecret[48] = SCE->REG_100H; + OutData_PreMasterSecret[49] = SCE->REG_100H; + OutData_PreMasterSecret[50] = SCE->REG_100H; + OutData_PreMasterSecret[51] = SCE->REG_100H; + OutData_PreMasterSecret[52] = SCE->REG_100H; + OutData_PreMasterSecret[53] = SCE->REG_100H; + OutData_PreMasterSecret[54] = SCE->REG_100H; + OutData_PreMasterSecret[55] = SCE->REG_100H; + OutData_PreMasterSecret[56] = SCE->REG_100H; + OutData_PreMasterSecret[57] = SCE->REG_100H; + OutData_PreMasterSecret[58] = SCE->REG_100H; + OutData_PreMasterSecret[59] = SCE->REG_100H; + OutData_PreMasterSecret[60] = SCE->REG_100H; + OutData_PreMasterSecret[61] = SCE->REG_100H; + OutData_PreMasterSecret[62] = SCE->REG_100H; + OutData_PreMasterSecret[63] = SCE->REG_100H; + R_SCE_func102(0xfaa4f63bU, 0x63cfd0deU, 0x3d38e146U, 0x063a5a44U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe2_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe3.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe3.c new file mode 100644 index 0000000000..654d2a5c0f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe3.c @@ -0,0 +1,298 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsGeneratePreMasterSecretSub(uint32_t *OutData_PreMasterSecret) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e302U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_ECH = 0x00003441U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000010U; + R_SCE_func100(0x859b003bU, 0x8cbaa106U, 0xacb2f580U, 0xc319a807U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002420U; + R_SCE_func100(0x6a612639U, 0x0c8f9f71U, 0x68cbfc56U, 0xfa4eabb2U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002420U; + R_SCE_func100(0x16b25d08U, 0xde9e5bdeU, 0x53b7658eU, 0x991d9670U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80840001U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003422U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000303U; + SCE->REG_ECH = 0x01003c01U; + R_SCE_func100(0x5ee4705bU, 0x4ced1fecU, 0xeb52b6b3U, 0xad23577dU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e3U); + R_SCE_func101(0x4d905202U, 0xfc30a9f0U, 0x6d1b0354U, 0x9dec6a9bU); + R_SCE_func059(); + SCE->REG_E0H = 0x81040000U; + SCE->REG_C4H = 0x00060805U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0154569cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e3U); + R_SCE_func101(0x330a8f2bU, 0x7da8d6c6U, 0xa258f5cfU, 0x3b3f78c9U); + R_SCE_func044(); + R_SCE_func100(0xd7bf3fd4U, 0x9fd30b57U, 0x97867224U, 0xfc437c46U); + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x818c0001U; + SCE->REG_00H = 0x00002833U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecret[4] = SCE->REG_100H; + OutData_PreMasterSecret[5] = SCE->REG_100H; + OutData_PreMasterSecret[6] = SCE->REG_100H; + OutData_PreMasterSecret[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecret[8] = SCE->REG_100H; + OutData_PreMasterSecret[9] = SCE->REG_100H; + OutData_PreMasterSecret[10] = SCE->REG_100H; + OutData_PreMasterSecret[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecret[12] = SCE->REG_100H; + OutData_PreMasterSecret[13] = SCE->REG_100H; + OutData_PreMasterSecret[14] = SCE->REG_100H; + OutData_PreMasterSecret[15] = SCE->REG_100H; + R_SCE_func100(0xf0b143e2U, 0x21b3f041U, 0xf361845fU, 0x47796392U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecret[16] = SCE->REG_100H; + OutData_PreMasterSecret[17] = SCE->REG_100H; + OutData_PreMasterSecret[18] = SCE->REG_100H; + OutData_PreMasterSecret[19] = SCE->REG_100H; + R_SCE_func100(0x42f7380cU, 0x3a2937c7U, 0xd0d22060U, 0x505c1df5U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecret[0] = SCE->REG_100H; + OutData_PreMasterSecret[1] = SCE->REG_100H; + OutData_PreMasterSecret[2] = SCE->REG_100H; + OutData_PreMasterSecret[3] = SCE->REG_100H; + R_SCE_func102(0x843f5e60U, 0x8b89b89cU, 0xad49c1cbU, 0x07db4a0fU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe3_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe4.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe4.c new file mode 100644 index 0000000000..37575527b6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe4.c @@ -0,0 +1,663 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsGenerateMasterSecretSub(uint32_t *InData_Sel_CipherSuite, uint32_t *InData_PreMasterSecret, uint32_t *InData_ClientRandom, uint32_t *InData_ServerRandom, uint32_t *OutData_MasterSecret) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e402U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Sel_CipherSuite[0]; + SCE->REG_ECH = 0x3420a800U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xa59d2b56U, 0x8755a254U, 0xb11c9cf6U, 0x07478cb8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x1320633aU, 0x86546a8aU, 0xd4ab96b7U, 0xc919095bU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[3]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e4U); + R_SCE_func101(0x2118adebU, 0xc5bfe441U, 0xd7c63cefU, 0x35b00ae5U); + R_SCE_func059(); + SCE->REG_ECH = 0x3420a800U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0x209cdfe0U, 0x34ae0cb2U, 0xb8883696U, 0x8faaef69U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0154569cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e4U); + R_SCE_func101(0xfdcbdd26U, 0xe7e9e149U, 0x41e87163U, 0x3275e5baU); + R_SCE_func044(); + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[4]; + SCE->REG_100H = InData_PreMasterSecret[5]; + SCE->REG_100H = InData_PreMasterSecret[6]; + SCE->REG_100H = InData_PreMasterSecret[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[8]; + SCE->REG_100H = InData_PreMasterSecret[9]; + SCE->REG_100H = InData_PreMasterSecret[10]; + SCE->REG_100H = InData_PreMasterSecret[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[12]; + SCE->REG_100H = InData_PreMasterSecret[13]; + SCE->REG_100H = InData_PreMasterSecret[14]; + SCE->REG_100H = InData_PreMasterSecret[15]; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x808c0000U; + SCE->REG_00H = 0x00008233U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[16]; + SCE->REG_100H = InData_PreMasterSecret[17]; + SCE->REG_100H = InData_PreMasterSecret[18]; + SCE->REG_100H = InData_PreMasterSecret[19]; + R_SCE_func101(0x6f5bc605U, 0x2fa93724U, 0x66f2da6cU, 0x80f8d4f5U); + } + else + { + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x01c1817fU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000030U); + R_SCE_func101(0xcc67dbfbU, 0x06d55bbbU, 0x97b48a8bU, 0xafbb18abU); + R_SCE_func044(); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[4]; + SCE->REG_100H = InData_PreMasterSecret[5]; + SCE->REG_100H = InData_PreMasterSecret[6]; + SCE->REG_100H = InData_PreMasterSecret[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[8]; + SCE->REG_100H = InData_PreMasterSecret[9]; + SCE->REG_100H = InData_PreMasterSecret[10]; + SCE->REG_100H = InData_PreMasterSecret[11]; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x808c0000U; + SCE->REG_00H = 0x00008223U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[12]; + SCE->REG_100H = InData_PreMasterSecret[13]; + SCE->REG_100H = InData_PreMasterSecret[14]; + SCE->REG_100H = InData_PreMasterSecret[15]; + R_SCE_func101(0xd99c6b1fU, 0xb74cda8cU, 0xd740f9b0U, 0x757390c8U); + } + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x3139c8e6U, 0x830404edU, 0x061ba820U, 0x023c8821U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xe0d513b2U, 0xbe24df6bU, 0x68013ccbU, 0x69455443U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000352U; + SCE->REG_C4H = 0x00000885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6d617374U); + SCE->REG_100H = change_endian_long(0x65722073U); + SCE->REG_100H = change_endian_long(0x65637265U); + SCE->REG_100H = change_endian_long(0x74000000U); + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x80830003U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000074U); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ClientRandom[0]; + SCE->REG_100H = InData_ClientRandom[1]; + SCE->REG_100H = InData_ClientRandom[2]; + SCE->REG_100H = InData_ClientRandom[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ClientRandom[4]; + SCE->REG_100H = InData_ClientRandom[5]; + SCE->REG_100H = InData_ClientRandom[6]; + SCE->REG_100H = InData_ClientRandom[7]; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x0000002cU; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + SCE->REG_E0H = 0x80010020U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x01986c01U; + SCE->REG_ECH = 0x00003c03U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_ECH = 0x00000004U; + } + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ServerRandom[0]; + SCE->REG_100H = InData_ServerRandom[1]; + SCE->REG_100H = InData_ServerRandom[2]; + SCE->REG_100H = InData_ServerRandom[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ServerRandom[4]; + SCE->REG_100H = InData_ServerRandom[5]; + SCE->REG_100H = InData_ServerRandom[6]; + SCE->REG_100H = InData_ServerRandom[7]; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + SCE->REG_E0H = 0x80010020U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x01986c01U; + SCE->REG_ECH = 0x00003c03U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_ECH = 0x00000004U; + } + SCE->REG_ECH = 0x00186c00U; + SCE->REG_ECH = 0x00003c03U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x0000b560U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x0000098cU; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000004dU; + R_SCE_func101(0x3d4bddc9U, 0x4907b8edU, 0x4d1aac9bU, 0xd5d1d31fU); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000006dU; + R_SCE_func101(0xf3a8894bU, 0xe4099076U, 0x50fcf137U, 0x1d3454aaU); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_E0H = 0x8188000cU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000098cU; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x00000020U; + R_SCE_func101(0xf90914feU, 0x15cd84e8U, 0x21da8135U, 0x3a872e56U); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000006dU; + R_SCE_func101(0xbf2c6705U, 0x5b3fcc9cU, 0xbb0c385aU, 0xa342a75bU); + R_SCE_TlsGenerateSubSub(); + + R_SCE_func100(0x624ad8c6U, 0xcd3be473U, 0x2cd1d6aeU, 0xc1048fb8U); + SCE->REG_E0H = 0x8184000cU; + SCE->REG_00H = 0x00003813U; + SCE->REG_2CH = 0x0000009bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x808c0001U; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x0000002bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00008313U; + SCE->REG_2CH = 0x000000abU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000034U); + R_SCE_func101(0xeac6002eU, 0x93a16f34U, 0xc899ec90U, 0x796688ebU); + R_SCE_func059(); + SCE->REG_E0H = 0x81040000U; + SCE->REG_C4H = 0x00060805U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0126a005U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000031U); + R_SCE_func101(0x089a1575U, 0xf103978eU, 0x238910caU, 0x335dacd5U); + R_SCE_func044(); + R_SCE_func100(0x57721ee9U, 0xb6fae5aaU, 0x0eea3d29U, 0x4e4713d6U); + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x818c0001U; + SCE->REG_00H = 0x00002833U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MasterSecret[4] = SCE->REG_100H; + OutData_MasterSecret[5] = SCE->REG_100H; + OutData_MasterSecret[6] = SCE->REG_100H; + OutData_MasterSecret[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MasterSecret[8] = SCE->REG_100H; + OutData_MasterSecret[9] = SCE->REG_100H; + OutData_MasterSecret[10] = SCE->REG_100H; + OutData_MasterSecret[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MasterSecret[12] = SCE->REG_100H; + OutData_MasterSecret[13] = SCE->REG_100H; + OutData_MasterSecret[14] = SCE->REG_100H; + OutData_MasterSecret[15] = SCE->REG_100H; + R_SCE_func100(0x3f81dce8U, 0xe87679adU, 0x5e6fd517U, 0x62abf1f8U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MasterSecret[16] = SCE->REG_100H; + OutData_MasterSecret[17] = SCE->REG_100H; + OutData_MasterSecret[18] = SCE->REG_100H; + OutData_MasterSecret[19] = SCE->REG_100H; + R_SCE_func100(0x49800391U, 0x598cfbd0U, 0xba5fc2c3U, 0x2c894fb8U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MasterSecret[0] = SCE->REG_100H; + OutData_MasterSecret[1] = SCE->REG_100H; + OutData_MasterSecret[2] = SCE->REG_100H; + OutData_MasterSecret[3] = SCE->REG_100H; + R_SCE_func102(0x4e33abb3U, 0x20035c03U, 0xc225e7d4U, 0xbeeeb324U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe4_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe5.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe5.c new file mode 100644 index 0000000000..41730103b8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe5.c @@ -0,0 +1,2995 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsGenerateSessionKeySub(uint32_t *InData_Sel_CipherSuite, uint32_t *InData_MasterSecret, uint32_t *InData_ClientRandom, uint32_t *InData_ServerRandom, uint32_t *InData_NonceExplicit, uint32_t *OutData_ClientMACKeyOperationCode, uint32_t *OutData_ServerMACKeyOperationCode, uint32_t *OutData_ClientEncKeyOperationCode, uint32_t *OutData_ServerEncKeyOperationCode, uint32_t OutLen) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)OutLen; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e502U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Sel_CipherSuite[0]; + SCE->REG_ECH = 0x00003780U; + SCE->REG_ECH = 0x3420ab80U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xc5c85654U, 0xa9db5f32U, 0x435cb747U, 0x1a20ca94U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x0a565757U, 0xacf7c9fbU, 0x072b0c01U, 0xc50361efU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[3]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e5U); + R_SCE_func101(0x693dfb95U, 0x2a2cf8efU, 0x9162fb7eU, 0xea58c30cU); + R_SCE_func059(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0126a005U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e5U); + R_SCE_func101(0x66f5e0c2U, 0x302fd292U, 0x58e59ad7U, 0x2b5b05c2U); + R_SCE_func044(); + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[4]; + SCE->REG_100H = InData_MasterSecret[5]; + SCE->REG_100H = InData_MasterSecret[6]; + SCE->REG_100H = InData_MasterSecret[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[8]; + SCE->REG_100H = InData_MasterSecret[9]; + SCE->REG_100H = InData_MasterSecret[10]; + SCE->REG_100H = InData_MasterSecret[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[12]; + SCE->REG_100H = InData_MasterSecret[13]; + SCE->REG_100H = InData_MasterSecret[14]; + SCE->REG_100H = InData_MasterSecret[15]; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x808c0000U; + SCE->REG_00H = 0x00008233U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[16]; + SCE->REG_100H = InData_MasterSecret[17]; + SCE->REG_100H = InData_MasterSecret[18]; + SCE->REG_100H = InData_MasterSecret[19]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xf6dfe02bU, 0x5af8207fU, 0xc7da0cdfU, 0x7c648670U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x310753efU, 0x66c22afbU, 0x98df016cU, 0xf138b2c2U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000352U; + SCE->REG_C4H = 0x00000885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6b657920U); + SCE->REG_100H = change_endian_long(0x65787061U); + SCE->REG_100H = change_endian_long(0x6e73696fU); + SCE->REG_100H = change_endian_long(0x6e000000U); + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x80830003U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000006eU); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ServerRandom[0]; + SCE->REG_100H = InData_ServerRandom[1]; + SCE->REG_100H = InData_ServerRandom[2]; + SCE->REG_100H = InData_ServerRandom[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ServerRandom[4]; + SCE->REG_100H = InData_ServerRandom[5]; + SCE->REG_100H = InData_ServerRandom[6]; + SCE->REG_100H = InData_ServerRandom[7]; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x0000002cU; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + SCE->REG_E0H = 0x80010020U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x01986c01U; + SCE->REG_ECH = 0x00003c03U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_ECH = 0x00000004U; + } + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ClientRandom[0]; + SCE->REG_100H = InData_ClientRandom[1]; + SCE->REG_100H = InData_ClientRandom[2]; + SCE->REG_100H = InData_ClientRandom[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ClientRandom[4]; + SCE->REG_100H = InData_ClientRandom[5]; + SCE->REG_100H = InData_ClientRandom[6]; + SCE->REG_100H = InData_ClientRandom[7]; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + SCE->REG_E0H = 0x80010020U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x01986c01U; + SCE->REG_ECH = 0x00003c03U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_ECH = 0x00000004U; + } + SCE->REG_ECH = 0x00186c00U; + SCE->REG_ECH = 0x00003c03U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x0000b560U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x0000098cU; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000004dU; + R_SCE_func101(0x500c38e6U, 0x336b8577U, 0x8202e518U, 0x1a11adf5U); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000006dU; + R_SCE_func101(0x7ca5e69fU, 0x3de93ad2U, 0x147ee0c8U, 0x727f46deU); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_E0H = 0x8188000cU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000009aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000098cU; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x00000020U; + R_SCE_func101(0xf21255d9U, 0x5ffa1986U, 0x4eb30f51U, 0x6def656cU); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000006dU; + R_SCE_func101(0x31489cecU, 0x37009fe9U, 0x94adfb4dU, 0x4b37ceddU); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_E0H = 0x8188000cU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000098cU; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x00000020U; + R_SCE_func101(0x46076dccU, 0xebf31dbbU, 0x023519aeU, 0x4f0c235bU); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000006dU; + R_SCE_func101(0x8c06dba9U, 0xa77d01e6U, 0xf881d70bU, 0xbe126888U); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_E0H = 0x8188000cU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000092U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000098cU; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x00000020U; + R_SCE_func101(0x6461b7e1U, 0x0445b7a9U, 0x33f8057fU, 0x3e5a02fdU); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000b580U; + SCE->REG_ECH = 0x000000a0U; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000006dU; + R_SCE_func101(0x4e633f25U, 0x47057a44U, 0xd5f4cd49U, 0x7ea85623U); + R_SCE_TlsGenerateSubSub(); + + R_SCE_func100(0x74da32dcU, 0xe0fb5941U, 0x4a5d3c00U, 0x1917c9cbU); + SCE->REG_E0H = 0x8188000cU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x009f0001U; + SCE->REG_ECH = 0x000034dcU; + SCE->REG_ECH = 0x3420ab80U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x2000b4c0U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x3420ab80U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_ECH = 0x2000b4c0U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_ECH = 0x00007c06U; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x5c75a1ecU, 0xe833c1c0U, 0xacaf6bf5U, 0xb84083acU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01032001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000035U); + R_SCE_func101(0x7d54c0d8U, 0x49d729ccU, 0x526da749U, 0xafdc0687U); + R_SCE_func059(); + R_SCE_func100(0xd6b7ab60U, 0x65358c2bU, 0x68dac91aU, 0xc9a2323aU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002317U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000200fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xf75ef456U, 0x846f86f0U, 0xf34299f9U, 0xfd6215afU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + SCE->REG_D0H = 0x40000000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[12] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[13] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[14] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x61b563dfU, 0x2f4068dcU, 0xaabd49c2U, 0x72fbea90U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x04918999U, 0xa42af7a7U, 0xa56d8003U, 0xa1384909U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01031001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000036U); + R_SCE_func101(0x02415da3U, 0x7d1673e8U, 0x823e459cU, 0x7c15244aU); + R_SCE_func059(); + R_SCE_func100(0xc250fee7U, 0x61b45f06U, 0xafdb7209U, 0xffd6d721U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002317U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000200fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xa46b314eU, 0x6ebaac1bU, 0xb0edd9a2U, 0xc09b6329U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[12] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[13] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[14] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x7c55225bU, 0x86367fe5U, 0x1f9d3bf4U, 0xede4ca3fU); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x8cf75c6aU, 0xbf318fa6U, 0x1dd0dcebU, 0xe96bb683U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01008001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000037U); + R_SCE_func101(0x2bbbefd3U, 0x2aa9effcU, 0xed2b49f6U, 0x62af13e6U); + R_SCE_func059(); + R_SCE_func100(0xa6024b24U, 0xb3e84f66U, 0x11ddb7cbU, 0x41a42d0dU); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02e087b5U; + SCE->REG_00H = 0x00002313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[7] = SCE->REG_100H; + R_SCE_func100(0xe92a97b6U, 0xb7cd22f5U, 0x7b122ce3U, 0xdd5b1567U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xafac3f38U, 0x67fda146U, 0xc96042feU, 0xe7ebc910U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x2287441cU, 0xcddaff0aU, 0x16dfaf9aU, 0xebb502a5U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01004001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000038U); + R_SCE_func101(0x6d6c231cU, 0x4fbbd326U, 0x5587f15eU, 0xcdeab0efU); + R_SCE_func059(); + R_SCE_func100(0xd071731eU, 0xef39ec2bU, 0x499fad0dU, 0x073e5346U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02e087b5U; + SCE->REG_00H = 0x00002313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000033bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[7] = SCE->REG_100H; + R_SCE_func100(0xf2d62f7fU, 0x850ce6b1U, 0x745d078fU, 0x4350bbb4U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0x7323a70cU, 0xd045a764U, 0x36b69fffU, 0x5d037d45U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func101(0xbd5bcbd8U, 0x56b4d7c0U, 0xd67bd56cU, 0xb4feafffU); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x693fb073U, 0x7a17330aU, 0x40598b4aU, 0x8887dddeU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01032001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000039U); + R_SCE_func101(0xbf69a5b0U, 0xdb9dd14cU, 0x42705909U, 0x9891f6d6U); + R_SCE_func059(); + R_SCE_func100(0xfcafb0c4U, 0x4bd5c522U, 0xc6fe94afU, 0xeb8f47d9U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002317U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000200fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0x75bc18bcU, 0xa1f515daU, 0xae684115U, 0x2245b246U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[12] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[13] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[14] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0xdcc19d27U, 0xed8f3d59U, 0xcbaaf91eU, 0xa26ced1eU); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x6c7925a2U, 0xccf6c44cU, 0xd3f5ad54U, 0x2a7bf4bdU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01031001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000040U); + R_SCE_func101(0xbd8a5b0cU, 0x6e236b7dU, 0x0ea57d11U, 0x50020e43U); + R_SCE_func059(); + R_SCE_func100(0x57b9b39cU, 0xfff74f40U, 0x0008b02cU, 0x80d82a47U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002317U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000200fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xb46b547cU, 0xb242fa96U, 0x69c98beeU, 0xe3081c52U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[12] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[13] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[14] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x09e3309aU, 0xe2330215U, 0xf48b8d42U, 0x1ab3f600U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x2cb6d424U, 0xcb926dbdU, 0x3dd58691U, 0x7515d0e5U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01018001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000041U); + R_SCE_func101(0xcba11f7bU, 0x8914d9d7U, 0x5c5462f4U, 0xb1843fbfU); + R_SCE_func059(); + R_SCE_func100(0x02746de3U, 0x3c6f5224U, 0x0824317dU, 0xe4245f12U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0x8d924761U, 0x1c50acf5U, 0x6b00e4dfU, 0xcaa9eb8cU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[12] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[13] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[14] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x3d07116aU, 0x30d55e07U, 0x3d86bf9cU, 0x5dc44cb4U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0xc431f37fU, 0xcbdbb664U, 0xff7c51d4U, 0x40170aacU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01014001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000042U); + R_SCE_func101(0xf160e1e9U, 0x82775694U, 0xd14edbe2U, 0x916fe4f6U); + R_SCE_func059(); + R_SCE_func100(0x698c2423U, 0x9aed4762U, 0x4f97d4a9U, 0x2079da9cU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000031bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xc57ee13cU, 0x4c8a0750U, 0xf06c587bU, 0x3f6a0be8U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[12] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[13] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[14] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x8ec268e6U, 0x6e2bcc4dU, 0x40fa4c4eU, 0xf0f5c92cU); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func101(0x2562d957U, 0xf6276487U, 0x6c2e4f9bU, 0x4a97c281U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x30e9b085U, 0xfa0c07c3U, 0x32806bd5U, 0x534179e4U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01022001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000043U); + R_SCE_func101(0x843e57cfU, 0x5e51ba7fU, 0x16207549U, 0x55a94cc0U); + R_SCE_func059(); + R_SCE_func100(0xe0c00ca2U, 0x3e9eef70U, 0x9077e269U, 0xef4323f2U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0x75e57ad6U, 0x78c42cceU, 0xdcdc4ee6U, 0x26b88322U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[12] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[13] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[14] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x74332081U, 0x2e5bca18U, 0xdbf88913U, 0xf6e7dcb4U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x19fad6aeU, 0x2d215e19U, 0x53b433aeU, 0x579279ffU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01021001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000044U); + R_SCE_func101(0x74066268U, 0xbc6f0e9fU, 0x76a400bbU, 0x2743f156U); + R_SCE_func059(); + R_SCE_func100(0x3189e954U, 0xaa8978f2U, 0xe331348cU, 0xa2111302U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xf35c3a41U, 0x13b43483U, 0x70f0ee73U, 0x6e1b4665U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[12] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[13] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[14] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x01cc1996U, 0x89e39590U, 0x68420704U, 0x46b54ba3U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x5a2cbfb3U, 0x9b461dbcU, 0xb8931a2aU, 0x3fcb5587U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01008001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000045U); + R_SCE_func101(0x307aa78cU, 0xcd89b52eU, 0xc61ddc1dU, 0x34e6f076U); + R_SCE_func059(); + R_SCE_func100(0xf19277deU, 0xf5193cb0U, 0xe2f64477U, 0xb399bc5bU); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02e087b5U; + SCE->REG_00H = 0x00002313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[7] = SCE->REG_100H; + R_SCE_func100(0xa871e7f1U, 0xe54220eeU, 0x2ba25dd9U, 0xe421a210U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xcc9983faU, 0x7642fe8eU, 0x82f52172U, 0x8a2ca89aU); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x00652492U, 0xbb2e38bbU, 0x7b934bd6U, 0xa9fd0800U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01004001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000046U); + R_SCE_func101(0x6c30233bU, 0x33e0e721U, 0x6c9d661cU, 0x83ddd9c8U); + R_SCE_func059(); + R_SCE_func100(0x0fd9ab7eU, 0x039c70c8U, 0x8eee4a00U, 0xf28da9e2U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x02e087b5U; + SCE->REG_00H = 0x00002313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000323U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[7] = SCE->REG_100H; + R_SCE_func100(0x7cbae145U, 0xab9d57e3U, 0xad7800baU, 0x1af5760cU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0x905b14d3U, 0xe1ea9e39U, 0x53a09e10U, 0xeda857b0U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func101(0xa36fc5b6U, 0x4135b001U, 0x013006bbU, 0x7f76b0d1U); + } + else if (0x03000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x5396cd59U, 0xdae9e557U, 0x381105bbU, 0x5aa2f64dU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01022001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000021U); + R_SCE_func101(0x4a7d177eU, 0x10298af1U, 0xe458f86fU, 0x9b69d476U); + R_SCE_func059(); + R_SCE_func100(0x01db4253U, 0xb764e5afU, 0x8f022087U, 0x097eb48dU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0x39ce140cU, 0x8fee909aU, 0x6bc1034eU, 0xd7025579U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[12] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[13] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[14] = SCE->REG_100H; + OutData_ClientMACKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x9f885f43U, 0x631a0a16U, 0x008b60c1U, 0xfcd16548U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientMACKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x772d5fe5U, 0x00d1bd61U, 0x5e123603U, 0x75cba3f1U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01021001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000048U); + R_SCE_func101(0x07a7255fU, 0x1aea69bbU, 0x8640ceccU, 0x986ee422U); + R_SCE_func059(); + R_SCE_func100(0xe4a6b9e8U, 0x2a75331eU, 0x381cf253U, 0xc5fcdda5U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xf82fda1cU, 0x2ab810f2U, 0x17e97920U, 0xf43fdacfU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[12] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[13] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[14] = SCE->REG_100H; + OutData_ServerMACKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0xa03077c9U, 0xb4731ef0U, 0x4b2af05dU, 0x5ba751afU); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerMACKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0xeeaefe4bU, 0x05de1213U, 0xe0541d32U, 0x1f4334d1U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01018001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000049U); + R_SCE_func101(0x531ce644U, 0x3120efd0U, 0x40cfb4f0U, 0xc69c081cU); + R_SCE_func059(); + R_SCE_func100(0x401cdeedU, 0xc8e159a6U, 0xce061e5aU, 0xd03b6ee4U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xe340e384U, 0xffa4f2fdU, 0xf0700e76U, 0x262e1e15U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[12] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[13] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[14] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0xfa48895fU, 0x4a72598bU, 0xa8379cf0U, 0x09aa09e2U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0xf385c1a9U, 0x693ecd43U, 0x7a4b1563U, 0x1806c4adU); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01014001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000026U); + R_SCE_func101(0x40f3b61dU, 0x2e645724U, 0xcd2ad425U, 0x0837effcU); + R_SCE_func059(); + R_SCE_func100(0x0e96be0eU, 0xc535cd0dU, 0x9b19720cU, 0x45fcc98aU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xe6e8a154U, 0x9ac149b6U, 0x97fb6450U, 0x18d20914U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[12] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[13] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[14] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0x135cf8e9U, 0x22e34a6fU, 0xd538c9b6U, 0x8860e6fdU); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func101(0xb8a02f80U, 0x6869578bU, 0x0d019f50U, 0x0a081d23U); + } + else if (0x06000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0x9efee54dU, 0x0154eeaaU, 0xb09040e7U, 0x57f42b2eU); + SCE->REG_A4H = 0x00040805U; + SCE->REG_00H = 0x00001313U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x00050805U; + SCE->REG_00H = 0x00001313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80010280U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x800202a0U; + SCE->REG_104H = 0x00000168U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_NonceExplicit[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_NonceExplicit[1]; + SCE->REG_ECH = 0x0000b6e0U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x81040280U; + SCE->REG_A4H = 0x00060805U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80010280U; + SCE->REG_00H = 0x00008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000035bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81040280U; + SCE->REG_A4H = 0x00070805U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01128001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000051U); + R_SCE_func101(0x8343eb18U, 0x67ebfa36U, 0xcf951dbeU, 0xf206e369U); + R_SCE_func059(); + R_SCE_func100(0x0483d9bdU, 0xb29fdd54U, 0x6f4d8d56U, 0x221f70dbU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00002113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00002113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0xba35a2e6U, 0xabc58c2eU, 0x039e6913U, 0x3ee9bb84U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[12] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[13] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[14] = SCE->REG_100H; + OutData_ClientEncKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0xae3a749aU, 0xd06fb41dU, 0x144edc0eU, 0xa6263915U); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ClientEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func100(0x4b4792eaU, 0x672c493eU, 0xfaa4a3ddU, 0xd2692197U); + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010040U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01124001U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030060U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003542U; + SCE->REG_ECH = 0x00003563U; + SCE->REG_ECH = 0x00003584U; + SCE->REG_ECH = 0x000035a5U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000052U); + R_SCE_func101(0x49e3ab69U, 0xf85e072aU, 0xc6a78f31U, 0x939f9ff3U); + R_SCE_func059(); + R_SCE_func100(0xc7c69dc5U, 0x291d6a17U, 0xdec99feeU, 0x3011005eU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_104H = 0x00000151U; + SCE->REG_A4H = 0x00000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00002113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x01000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00002113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[4] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[5] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[6] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[8] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[9] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[10] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[11] = SCE->REG_100H; + R_SCE_func100(0x28967aaeU, 0x417ee6d0U, 0x5060ac94U, 0x0d65555cU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[12] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[13] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[14] = SCE->REG_100H; + OutData_ServerEncKeyOperationCode[15] = SCE->REG_100H; + R_SCE_func100(0xd215727cU, 0x737d6f68U, 0x0ef52161U, 0xee4bfe8aU); + SCE->REG_E0H = 0x81040040U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_ServerEncKeyOperationCode[3] = SCE->REG_100H; + R_SCE_func101(0x9c788226U, 0xfb2e64bfU, 0x06dd0c95U, 0x7eadb016U); + } + R_SCE_func102(0xc5005a6bU, 0x0b80a4d3U, 0x23fa6350U, 0xe5e04365U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe5_r3.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe6.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe6.c new file mode 100644 index 0000000000..c603ff6bab --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe6.c @@ -0,0 +1,411 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsGenerateVerifyDataSub(uint32_t *InData_Sel_VerifyData, uint32_t *InData_MasterSecret, uint32_t *InData_HandShakeHash, uint32_t *OutData_VerifyData) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1BCH & 0x1fU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e602U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010380U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Sel_VerifyData[0]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037fcU; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0xfffffffeU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x42725bd9U, 0xd68ae495U, 0x2874ceebU, 0x5b1e6c80U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x7f43f836U, 0xaa211e9bU, 0xb77495f6U, 0xa5a2b98dU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040140U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[3]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e6U); + R_SCE_func101(0x226b73c7U, 0x6e4f30a7U, 0x3a9fe8e5U, 0x1f38e4ddU); + R_SCE_func059(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x0126a005U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e6U); + R_SCE_func101(0xace0c4fdU, 0x95aa2c99U, 0xbd2ed299U, 0xdcce1864U); + R_SCE_func044(); + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02f087b7U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[4]; + SCE->REG_100H = InData_MasterSecret[5]; + SCE->REG_100H = InData_MasterSecret[6]; + SCE->REG_100H = InData_MasterSecret[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[8]; + SCE->REG_100H = InData_MasterSecret[9]; + SCE->REG_100H = InData_MasterSecret[10]; + SCE->REG_100H = InData_MasterSecret[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[12]; + SCE->REG_100H = InData_MasterSecret[13]; + SCE->REG_100H = InData_MasterSecret[14]; + SCE->REG_100H = InData_MasterSecret[15]; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_E0H = 0x808c0000U; + SCE->REG_00H = 0x00008233U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MasterSecret[16]; + SCE->REG_100H = InData_MasterSecret[17]; + SCE->REG_100H = InData_MasterSecret[18]; + SCE->REG_100H = InData_MasterSecret[19]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xf50dc336U, 0x77e3b0d6U, 0x3753e3e0U, 0xbdade766U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xc1049c42U, 0x49cd3d25U, 0xe56c91a5U, 0x6a15e7f5U); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x000037fcU; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x0000000fU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xe1ef5191U, 0x4ff7f391U, 0x79e6aff9U, 0xf7c9687eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000352U; + SCE->REG_C4H = 0x00000885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x636c6965U); + SCE->REG_100H = change_endian_long(0x6e742066U); + SCE->REG_100H = change_endian_long(0x696e6973U); + SCE->REG_100H = change_endian_long(0x68656400U); + R_SCE_func101(0xfe4b107bU, 0xb8b23584U, 0xa1dcf904U, 0x9e8f01f1U); + } + else + { + SCE->REG_104H = 0x00000352U; + SCE->REG_C4H = 0x00000885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x73657276U); + SCE->REG_100H = change_endian_long(0x65722066U); + SCE->REG_100H = change_endian_long(0x696e6973U); + SCE->REG_100H = change_endian_long(0x68656400U); + R_SCE_func101(0x4b65d6d9U, 0xf7938205U, 0x07b72bc6U, 0x8c5214c3U); + } + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x80830001U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00686564U); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x00008887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_HandShakeHash[0]; + SCE->REG_100H = InData_HandShakeHash[1]; + SCE->REG_100H = InData_HandShakeHash[2]; + SCE->REG_100H = InData_HandShakeHash[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_HandShakeHash[4]; + SCE->REG_100H = InData_HandShakeHash[5]; + SCE->REG_100H = InData_HandShakeHash[6]; + SCE->REG_100H = InData_HandShakeHash[7]; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x0000002cU; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + SCE->REG_E0H = 0x80010020U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x01886c01U; + SCE->REG_ECH = 0x00003c03U; + SCE->REG_ECH = 0x00003401U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_ECH = 0x00000004U; + } + SCE->REG_ECH = 0x00086c00U; + SCE->REG_ECH = 0x00003c03U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000010U; + SCE->REG_ECH = 0x0000b560U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x0000098cU; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000002fU; + R_SCE_func101(0xb8a4becfU, 0x6a533f04U, 0x9e503e67U, 0x3cacdd1cU); + R_SCE_TlsGenerateSubSub(); + + SCE->REG_ECH = 0x00002c20U; + SCE->REG_ECH = 0x0000096bU; + SCE->REG_ECH = 0x0000098cU; + SCE->REG_ECH = 0x0000b5c0U; + SCE->REG_ECH = 0x0000004fU; + R_SCE_func101(0x64443922U, 0xc413a4a1U, 0x3fd447ffU, 0xd7d7c2acU); + R_SCE_TlsGenerateSubSub(); + + R_SCE_func100(0x51686b98U, 0xc07a2829U, 0x23472153U, 0x1333cb0dU); + SCE->REG_C4H = 0x00000885U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x81830001U; + SCE->REG_00H = 0x0000280fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00002007U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x0000020eU; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_VerifyData[0] = SCE->REG_100H; + OutData_VerifyData[1] = SCE->REG_100H; + OutData_VerifyData[2] = SCE->REG_100H; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func102(0x936f2936U, 0x95c646a6U, 0x5eb5daebU, 0xc3c5c83eU); + SCE->REG_1BCH = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe6_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe7.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe7.c new file mode 100644 index 0000000000..afb11c5a91 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe7.c @@ -0,0 +1,1155 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsServersEphemeralEcdhPublicKeyRetrievesSub(uint32_t *InData_Sel_PubKeyType, uint32_t *InData_ClientRandom, uint32_t *InData_ServerRandom, uint32_t *InData_Sel_CompressType, uint32_t *InData_SKE_Message, uint32_t *InData_SKE_Signature, uint32_t *InData_PubKey, uint32_t *OutData_EphemeralPubKey) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + (void)InData_Sel_CompressType; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e702U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + R_SCE_func100(0x0d9230beU, 0x454059abU, 0x94f33436U, 0x3c39ace1U); + R_SCE_func103(); + R_SCE_func100(0x08fbe3eeU, 0x8a9b7a2dU, 0x7ff0d272U, 0x12c7c86dU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01090c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800101e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Sel_PubKeyType[0]; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x38000defU; + SCE->REG_ECH = 0x1000d3e0U; + SCE->REG_ECH = 0x380089e0U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + R_SCE_func100(0xbbab3a93U, 0x95b4e10aU, 0x69df03c3U, 0x238dcac2U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xdac88ed0U, 0xefd18ea0U, 0x689eb32fU, 0x5151034bU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x300089e0U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00050000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00310000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x3800d80bU; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000ffU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xb487d0c4U, 0x35311d95U, 0xc97d5899U, 0xf4d76b5aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xd28e9578U, 0xc091a5adU, 0xb0f0ce34U, 0x3d0f6b98U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e7U); + R_SCE_func101(0x62877533U, 0x26b1b9edU, 0xa8d60c52U, 0x71ee0821U); + R_SCE_func059(); + R_SCE_func100(0xb4058388U, 0xc5d4e719U, 0x7b874c76U, 0x3a5563c5U); + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_28H = 0x00bf0001U; + SCE->REG_104H = 0x00008362U; + SCE->REG_D0H = 0x40001f00U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000014U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00013203U; + SCE->REG_2CH = 0x00000012U; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+68 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00f087b5U; + for (iLoop = 0; iLoop < 4; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+132 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 3]; + } + SCE->REG_E0H = 0x80010140U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[136]; + SCE->REG_100H = InData_PubKey[137]; + SCE->REG_100H = InData_PubKey[138]; + SCE->REG_100H = InData_PubKey[139]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x100687f3U, 0x1302b6cbU, 0xd4038e26U, 0x3cb6d735U); + } + else + { + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000009bU; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000091U; + for (iLoop = 8; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[20]; + SCE->REG_100H = InData_PubKey[21]; + SCE->REG_100H = InData_PubKey[22]; + SCE->REG_100H = InData_PubKey[23]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func101(0x496375c0U, 0x1b5f3cb4U, 0xd65b2350U, 0xea5f5d00U); + } + R_SCE_func100(0x807ae9feU, 0x755b9943U, 0x612b0059U, 0x1cd61442U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x0f2eb44aU, 0x2249fd41U, 0x719b370bU, 0x5b8190deU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_74H = 0x00000002U; + SCE->REG_104H = 0x00000f64U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ClientRandom[0]; + SCE->REG_100H = InData_ClientRandom[1]; + SCE->REG_100H = InData_ClientRandom[2]; + SCE->REG_100H = InData_ClientRandom[3]; + SCE->REG_100H = InData_ClientRandom[4]; + SCE->REG_100H = InData_ClientRandom[5]; + SCE->REG_100H = InData_ClientRandom[6]; + SCE->REG_100H = InData_ClientRandom[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_ServerRandom[0]; + SCE->REG_100H = InData_ServerRandom[1]; + SCE->REG_100H = InData_ServerRandom[2]; + SCE->REG_100H = InData_ServerRandom[3]; + SCE->REG_100H = InData_ServerRandom[4]; + SCE->REG_100H = InData_ServerRandom[5]; + SCE->REG_100H = InData_ServerRandom[6]; + SCE->REG_100H = InData_ServerRandom[7]; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x03001741U; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800103c0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SKE_Message[0]; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x60865debU, 0x653e9efaU, 0xb92d9458U, 0x53c8c5f5U); + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x00000200U; + SCE->REG_C4H = 0x42e097bfU; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SKE_Message[iLoop+1 + 0]; + SCE->REG_100H = InData_SKE_Message[iLoop+1 + 1]; + SCE->REG_100H = InData_SKE_Message[iLoop+1 + 2]; + SCE->REG_100H = InData_SKE_Message[iLoop+1 + 3]; + } + SCE->REG_04H = 0x00000232U; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop+68 + 0] = SCE->REG_100H; + S_HEAP[iLoop+68 + 1] = SCE->REG_100H; + S_HEAP[iLoop+68 + 2] = SCE->REG_100H; + S_HEAP[iLoop+68 + 3] = SCE->REG_100H; + } + R_SCE_func100(0x1e464166U, 0x485af5b2U, 0x81e31de9U, 0x8b9ed8feU); + SCE->REG_104H = 0x00000362U; + SCE->REG_C4H = 0x40e017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SKE_Message[13]; + SCE->REG_100H = InData_SKE_Message[14]; + SCE->REG_100H = InData_SKE_Message[15]; + SCE->REG_100H = InData_SKE_Message[16]; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop+68 + 0] = SCE->REG_100H; + S_HEAP[iLoop+68 + 1] = SCE->REG_100H; + S_HEAP[iLoop+68 + 2] = SCE->REG_100H; + S_HEAP[iLoop+68 + 3] = SCE->REG_100H; + R_SCE_func100(0xba88b46fU, 0x25e0af43U, 0x360805c6U, 0x90af43c1U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400019cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop+72 + 0] = SCE->REG_100H; + S_HEAP[iLoop+72 + 1] = SCE->REG_100H; + S_HEAP[iLoop+72 + 2] = SCE->REG_100H; + S_HEAP[iLoop+72 + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x00000300U; + SCE->REG_C4H = 0x42f097bfU; + SCE->REG_00H = 0x08015203U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+68 + 0]; + SCE->REG_100H = S_HEAP[iLoop+68 + 1]; + SCE->REG_100H = S_HEAP[iLoop+68 + 2]; + SCE->REG_100H = S_HEAP[iLoop+68 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_C4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+68 + 0]; + SCE->REG_100H = S_HEAP[iLoop+68 + 1]; + SCE->REG_100H = S_HEAP[iLoop+68 + 2]; + SCE->REG_100H = S_HEAP[iLoop+68 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x0800580fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08000807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_F8H = 0x00000040U; + SCE->REG_104H = 0x00000154U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000428U); + R_SCE_func100(0x0141edd2U, 0x342b8f5fU, 0x3832bc72U, 0x1e7f787eU); + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_ECH = 0x00007c0fU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + R_SCE_func100(0xe4b4ab65U, 0x4fc85decU, 0x83723a13U, 0xa45a7a51U); + SCE->REG_28H = 0x00bf0001U; + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00003f67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SKE_Signature[0]; + SCE->REG_100H = InData_SKE_Signature[1]; + SCE->REG_100H = InData_SKE_Signature[2]; + SCE->REG_100H = InData_SKE_Signature[3]; + SCE->REG_100H = InData_SKE_Signature[4]; + SCE->REG_100H = InData_SKE_Signature[5]; + SCE->REG_100H = InData_SKE_Signature[6]; + SCE->REG_100H = InData_SKE_Signature[7]; + SCE->REG_100H = InData_SKE_Signature[8]; + SCE->REG_100H = InData_SKE_Signature[9]; + SCE->REG_100H = InData_SKE_Signature[10]; + SCE->REG_100H = InData_SKE_Signature[11]; + SCE->REG_100H = InData_SKE_Signature[12]; + SCE->REG_100H = InData_SKE_Signature[13]; + SCE->REG_100H = InData_SKE_Signature[14]; + SCE->REG_100H = InData_SKE_Signature[15]; + SCE->REG_100H = InData_SKE_Signature[16]; + SCE->REG_100H = InData_SKE_Signature[17]; + SCE->REG_100H = InData_SKE_Signature[18]; + SCE->REG_100H = InData_SKE_Signature[19]; + SCE->REG_100H = InData_SKE_Signature[20]; + SCE->REG_100H = InData_SKE_Signature[21]; + SCE->REG_100H = InData_SKE_Signature[22]; + SCE->REG_100H = InData_SKE_Signature[23]; + SCE->REG_100H = InData_SKE_Signature[24]; + SCE->REG_100H = InData_SKE_Signature[25]; + SCE->REG_100H = InData_SKE_Signature[26]; + SCE->REG_100H = InData_SKE_Signature[27]; + SCE->REG_100H = InData_SKE_Signature[28]; + SCE->REG_100H = InData_SKE_Signature[29]; + SCE->REG_100H = InData_SKE_Signature[30]; + SCE->REG_100H = InData_SKE_Signature[31]; + SCE->REG_100H = InData_SKE_Signature[32]; + SCE->REG_100H = InData_SKE_Signature[33]; + SCE->REG_100H = InData_SKE_Signature[34]; + SCE->REG_100H = InData_SKE_Signature[35]; + SCE->REG_100H = InData_SKE_Signature[36]; + SCE->REG_100H = InData_SKE_Signature[37]; + SCE->REG_100H = InData_SKE_Signature[38]; + SCE->REG_100H = InData_SKE_Signature[39]; + SCE->REG_100H = InData_SKE_Signature[40]; + SCE->REG_100H = InData_SKE_Signature[41]; + SCE->REG_100H = InData_SKE_Signature[42]; + SCE->REG_100H = InData_SKE_Signature[43]; + SCE->REG_100H = InData_SKE_Signature[44]; + SCE->REG_100H = InData_SKE_Signature[45]; + SCE->REG_100H = InData_SKE_Signature[46]; + SCE->REG_100H = InData_SKE_Signature[47]; + SCE->REG_100H = InData_SKE_Signature[48]; + SCE->REG_100H = InData_SKE_Signature[49]; + SCE->REG_100H = InData_SKE_Signature[50]; + SCE->REG_100H = InData_SKE_Signature[51]; + SCE->REG_100H = InData_SKE_Signature[52]; + SCE->REG_100H = InData_SKE_Signature[53]; + SCE->REG_100H = InData_SKE_Signature[54]; + SCE->REG_100H = InData_SKE_Signature[55]; + SCE->REG_100H = InData_SKE_Signature[56]; + SCE->REG_100H = InData_SKE_Signature[57]; + SCE->REG_100H = InData_SKE_Signature[58]; + SCE->REG_100H = InData_SKE_Signature[59]; + SCE->REG_100H = InData_SKE_Signature[60]; + SCE->REG_100H = InData_SKE_Signature[61]; + SCE->REG_100H = InData_SKE_Signature[62]; + SCE->REG_100H = InData_SKE_Signature[63]; + SCE->REG_18H = 0x00000004U; + SCE->REG_34H = 0x00000000U; + SCE->REG_38H = 0x00000338U; + SCE->REG_E0H = 0x81010140U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_104H = 0x00003757U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0001ffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0xffffffffU); + SCE->REG_100H = change_endian_long(0x00303130U); + SCE->REG_100H = change_endian_long(0x0d060960U); + SCE->REG_100H = change_endian_long(0x86480165U); + SCE->REG_100H = change_endian_long(0x03040201U); + SCE->REG_100H = change_endian_long(0x05000420U); + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + R_SCE_func101(0xc57043c2U, 0xc795b1b7U, 0x59e88183U, 0xe3cff38aU); + } + else + { + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x00000b9cU; + OFS_ADR = 128; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e7U); + R_SCE_func101(0xea126629U, 0xd77ad021U, 0x0273a7ffU, 0x3e24bee9U); + R_SCE_func003_r1(InData_SKE_Signature); + R_SCE_func101(0x504fe8d8U, 0x2972efcbU, 0x85ff4f77U, 0xf1713252U); + } + R_SCE_func100(0xb909527eU, 0x25929460U, 0x20e1017aU, 0xa41770e0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x96a5aef5U, 0x8e435ae7U, 0x7d445d8eU, 0xc0e3eb5fU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x00000b9cU; + OFS_ADR = 128; + R_SCE_func100(0x6c3422cfU, 0xc3fd9efcU, 0x8fbb7deeU, 0x278522ddU); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x008f0001U; + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x00000300U; + SCE->REG_C4H = 0x42f097bfU; + SCE->REG_00H = 0x00003243U; + SCE->REG_2CH = 0x00000010U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+68 + 0]; + SCE->REG_100H = S_HEAP[iLoop+68 + 1]; + SCE->REG_100H = S_HEAP[iLoop+68 + 2]; + SCE->REG_100H = S_HEAP[iLoop+68 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400017bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+68 + 0]; + SCE->REG_100H = S_HEAP[iLoop+68 + 1]; + SCE->REG_100H = S_HEAP[iLoop+68 + 2]; + SCE->REG_100H = S_HEAP[iLoop+68 + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00870001U; + SCE->REG_34H = 0x00000004U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func008(); + R_SCE_func100(0x1fc7fc2cU, 0x63e47ac7U, 0x22a374ccU, 0xc504973fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x1eaca43bU, 0x44127cacU, 0x076cc9d2U, 0x8d90d614U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xbf9802d2U, 0x43bc12ecU, 0x8f84300fU, 0xad68cf6cU); + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000404U; + SCE->REG_24H = 0x80009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x008f0001U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01310201U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030020U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000053U); + R_SCE_func101(0x28b35c2bU, 0x5b363b65U, 0xf49dc395U, 0xa072db0fU); + R_SCE_func059(); + R_SCE_func100(0x8268449cU, 0x7352e0c4U, 0x87c3ce24U, 0xf7a5e8dfU); + SCE->REG_00H = 0x00002343U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_04H = 0x00000242U; + for (iLoop = 4; iLoop < 20; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_EphemeralPubKey[iLoop + 0] = SCE->REG_100H; + OutData_EphemeralPubKey[iLoop + 1] = SCE->REG_100H; + OutData_EphemeralPubKey[iLoop + 2] = SCE->REG_100H; + OutData_EphemeralPubKey[iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x1a03594bU, 0x6be00182U, 0xd9979282U, 0x07a9b7feU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_EphemeralPubKey[iLoop + 0] = SCE->REG_100H; + OutData_EphemeralPubKey[iLoop + 1] = SCE->REG_100H; + OutData_EphemeralPubKey[iLoop + 2] = SCE->REG_100H; + OutData_EphemeralPubKey[iLoop + 3] = SCE->REG_100H; + R_SCE_func100(0xc487bcc1U, 0x2138717cU, 0x7543a75fU, 0xf949b162U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_EphemeralPubKey[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_EphemeralPubKey[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_EphemeralPubKey[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_EphemeralPubKey[3] = SCE->REG_100H; + R_SCE_func102(0x6ec4a47cU, 0xd2050286U, 0xedf81e48U, 0xf7626f1fU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe7_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe8.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe8.c new file mode 100644 index 0000000000..6514cd6ae3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe8.c @@ -0,0 +1,736 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_TlsGeneratePreMasterSecretWithEccP256KeySub(uint32_t *InData_PubKey, uint32_t *InData_KeyIndex, uint32_t *OutData_PreMasterSecretIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e802U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00310000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x3800d809U; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000ffU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x6a5be6afU, 0xe9848368U, 0x1261721aU, 0x69c9b933U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xcfe2637dU, 0x810259acU, 0xe4c2366bU, 0xf3a016caU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e8U); + R_SCE_func101(0x34c6f8f7U, 0x1c7fabddU, 0x2250f267U, 0xdaba3fa4U); + R_SCE_func059(); + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x8090000aU; + SCE->REG_00H = 0x00008243U; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[20]; + SCE->REG_100H = InData_PubKey[21]; + SCE->REG_100H = InData_PubKey[22]; + SCE->REG_100H = InData_PubKey[23]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xb5c01937U, 0xc95dbe48U, 0x89adbacfU, 0x9ba25f38U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x3b1ac20eU, 0xd029df78U, 0x84f43b45U, 0xe9aef584U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00000b9cU; + OFS_ADR = 128; + R_SCE_func100(0xca63ca7eU, 0x4aa0d63aU, 0xe0ee4007U, 0x0dce1a55U); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_104H = 0x00000368U; + SCE->REG_E0H = 0x80040000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x00ff0000U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00390000U; + SCE->REG_ECH = 0x1000d3c0U; + SCE->REG_ECH = 0x3800d809U; + SCE->REG_ECH = 0x2000d3c1U; + SCE->REG_ECH = 0x000037e0U; + SCE->REG_ECH = 0x00008fe0U; + SCE->REG_ECH = 0x000000ffU; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x1000d3c2U; + SCE->REG_ECH = 0x38008bc0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x861fd358U, 0xb58de811U, 0x5f769a8eU, 0x8ea1f294U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x38fc31abU, 0x43e00935U, 0xde48474bU, 0xbb3b1b60U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000054U); + R_SCE_func101(0xd8880f8bU, 0x5332c748U, 0x1f4b6a6dU, 0x7b55fd7bU); + R_SCE_func059(); + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000011U; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+4 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+4 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+4 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x180acc23U, 0xf1e45c85U, 0x8270b290U, 0x5fb463ceU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x42966309U, 0x13b63901U, 0x248b6ecfU, 0x0c10d785U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xd2e59594U, 0xe1e0508fU, 0x83f00e28U, 0x312bf9adU); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x8000e808U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000908U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_E0H = 0x81880008U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00001000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x5fa9c0d9U, 0x93041fd9U, 0x7872c82fU, 0x326c0ff5U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x6cc1b731U, 0x93072b72U, 0x68ec43e2U, 0x96a18e42U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xf40a42c9U, 0x68e7c9f5U, 0xc53ad351U, 0x5b4771e3U); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + R_SCE_func100(0x49df7962U, 0xaf05c0dcU, 0x2f0b1ce7U, 0x1ab1dcceU); + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000055U); + R_SCE_func101(0x4056d95fU, 0xcbd8ee3bU, 0x46794c86U, 0x1f523346U); + R_SCE_func059(); + SCE->REG_ECH = 0x0000b4e0U; + SCE->REG_ECH = 0x01c1817fU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e8U); + R_SCE_func101(0x0417e7e5U, 0x4a1627f6U, 0xf490085eU, 0xa5680662U); + R_SCE_func044(); + R_SCE_func100(0xc6402425U, 0x42c0efffU, 0x0f4ec971U, 0xb3877abcU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecretIndex[4] = SCE->REG_100H; + OutData_PreMasterSecretIndex[5] = SCE->REG_100H; + OutData_PreMasterSecretIndex[6] = SCE->REG_100H; + OutData_PreMasterSecretIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecretIndex[8] = SCE->REG_100H; + OutData_PreMasterSecretIndex[9] = SCE->REG_100H; + OutData_PreMasterSecretIndex[10] = SCE->REG_100H; + OutData_PreMasterSecretIndex[11] = SCE->REG_100H; + R_SCE_func100(0x07eb6b17U, 0x0f67900aU, 0xf0d831c9U, 0x24aab76bU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecretIndex[12] = SCE->REG_100H; + OutData_PreMasterSecretIndex[13] = SCE->REG_100H; + OutData_PreMasterSecretIndex[14] = SCE->REG_100H; + OutData_PreMasterSecretIndex[15] = SCE->REG_100H; + R_SCE_func100(0x4d2eed2dU, 0x78488de5U, 0xbc08c9efU, 0x75bad497U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecretIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecretIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecretIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecretIndex[3] = SCE->REG_100H; + R_SCE_func102(0xa8a57ce7U, 0xea9852c1U, 0xbe885f74U, 0x68a6295fU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe8_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe9.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe9.c new file mode 100644 index 0000000000..0809b5afe3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe9.c @@ -0,0 +1,607 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateTlsP256EccKeyIndexSub(uint32_t *OutData_KeyIndex, uint32_t *OutData_PubKey) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e902U; + SCE->REG_108H = 0x00000000U; + SCE->REG_C4H = 0x200e1a0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[20+0 + 0]; + SCE->REG_100H = S_RAM[20+0 + 1]; + SCE->REG_100H = S_RAM[20+0 + 2]; + SCE->REG_100H = S_RAM[20+0 + 3]; + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x00000b9cU; + OFS_ADR = 128; + R_SCE_func100(0x317c876fU, 0xbb9de575U, 0x2faac8b5U, 0x764de931U); + R_SCE_func004_r1(OFS_ADR); + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x8000c0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00890001U; + R_SCE_func100(0x42b8e370U, 0x41c22b6cU, 0x00c7532cU, 0xc8e6fddfU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x500a18f9U, 0x228bf4c2U, 0xcdb111a7U, 0x18146bc3U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x22dbcfbcU, 0xa625dfa2U, 0xc57f56b1U, 0x1429d311U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x0000320bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x0000a206U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000016c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000682U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x3140cf98U, 0x1178bfb1U, 0x9d47eeaeU, 0xa1a6de28U); + R_SCE_func005_r1(OFS_ADR); + R_SCE_func100(0x870eea31U, 0x7924d113U, 0x6bf60ed9U, 0xb2bc9dd5U); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x8000e808U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00001030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000c00U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x283878b9U, 0xebfa2693U, 0x24e7702cU, 0x516b442eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x144841e4U, 0xbec4f086U, 0x0cd0cecdU, 0x3f555900U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xb33ecdb0U, 0x0f7ccce2U, 0xa94c4474U, 0xa4f84d42U); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01390201U); + R_SCE_func100(0x7d82b33cU, 0x79594255U, 0xedf53295U, 0x67da7c93U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80030020U; + SCE->REG_00H = 0x0000820fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00000207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003540U; + SCE->REG_ECH = 0x00003561U; + SCE->REG_ECH = 0x00003582U; + SCE->REG_ECH = 0x000035a3U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e9U); + R_SCE_func101(0x66bb3a78U, 0xee291e2bU, 0x8eb3b228U, 0x0b0583cbU); + R_SCE_func059(); + R_SCE_func100(0xfa82bf83U, 0xb0f5ed7aU, 0x1184a9ccU, 0xcd112300U); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x000000a8U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + R_SCE_func100(0xfeb1b97bU, 0x2c76d01dU, 0xb2b220abU, 0x6805a26dU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + R_SCE_func100(0xa61bc03eU, 0x74420568U, 0xab9d5fccU, 0xced0e607U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + R_SCE_func100(0x643c5054U, 0x3edd04f8U, 0xb0915661U, 0xb1f1292aU); + SCE->REG_2CH = 0x00000022U; + SCE->REG_04H = 0x00000322U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[0] = SCE->REG_100H; + OutData_PubKey[1] = SCE->REG_100H; + OutData_PubKey[2] = SCE->REG_100H; + OutData_PubKey[3] = SCE->REG_100H; + OutData_PubKey[4] = SCE->REG_100H; + OutData_PubKey[5] = SCE->REG_100H; + OutData_PubKey[6] = SCE->REG_100H; + OutData_PubKey[7] = SCE->REG_100H; + R_SCE_func100(0x75f665d7U, 0x44db8f1fU, 0xe721a02aU, 0x0f54519cU); + SCE->REG_2CH = 0x00000023U; + SCE->REG_04H = 0x00000322U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKey[8] = SCE->REG_100H; + OutData_PubKey[9] = SCE->REG_100H; + OutData_PubKey[10] = SCE->REG_100H; + OutData_PubKey[11] = SCE->REG_100H; + OutData_PubKey[12] = SCE->REG_100H; + OutData_PubKey[13] = SCE->REG_100H; + OutData_PubKey[14] = SCE->REG_100H; + OutData_PubKey[15] = SCE->REG_100H; + R_SCE_func102(0xe9d38798U, 0x702a5b50U, 0x3c9556e6U, 0xb6ff39b1U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pe9_r2.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf0.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf0.c new file mode 100644 index 0000000000..62c66c9eca --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf0.c @@ -0,0 +1,1873 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_EcdsaSignatureGenerateSub(uint32_t *InData_CurveType, uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f002U; + SCE->REG_108H = 0x00000000U; + SCE->REG_28H = 0x00870001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010380U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_104H = 0x00000768U; + SCE->REG_E0H = 0x8088001eU; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[iLoop + 0]; + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000d3e0U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x38000c00U; + SCE->REG_ECH = 0x1000d3e0U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x000037beU; + SCE->REG_ECH = 0x0000a7a0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000383dU; + SCE->REG_ECH = 0x38001001U; + SCE->REG_ECH = 0x1000d3e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x30000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d3e1U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x38000f9cU; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x1a448823U, 0x6a3a423fU, 0xbcd9e8e2U, 0xcacc0caeU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x8ed1208dU, 0xdbf7077fU, 0x507fb8b2U, 0x33c0ffdbU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x6a7bb13dU, 0x4d21208cU, 0x0404d573U, 0x6ba466e9U); + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x30003340U; + SCE->REG_ECH = 0x00050020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000004C8U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x0000031CU; + SCE->REG_ECH = 0x00070040U; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x0000013CU; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000001F8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + R_SCE_func100(0x75e6190dU, 0x75c068caU, 0xdb3f287fU, 0xdd0d8ad5U); + R_SCE_func070_r2(OFS_ADR); + R_SCE_func100(0xb897dde9U, 0x49145a8bU, 0x1080a889U, 0xfc598151U); + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + R_SCE_func100(0x2402576fU, 0x097cdc2dU, 0xb8005e2dU, 0x91fa30ccU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00001228U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x4d2112fcU, 0xa91850faU, 0x56bcdaadU, 0x6b15ee85U); + R_SCE_func103(); + R_SCE_func100(0xcb8ab6ecU, 0xf31e9e6eU, 0x8c036f67U, 0x9d1873cdU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01080c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x4e233698U, 0x8762b73aU, 0xaaf97837U, 0xfb15b664U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[0] = SCE->REG_100H; + S_HEAP[1] = SCE->REG_100H; + S_HEAP[2] = SCE->REG_100H; + S_HEAP[3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[4] = SCE->REG_100H; + S_HEAP[5] = SCE->REG_100H; + S_HEAP[6] = SCE->REG_100H; + S_HEAP[7] = SCE->REG_100H; + R_SCE_func100(0xb26b813dU, 0xdaf2e7c5U, 0x29d9a5e8U, 0x5749d586U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x0000002aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[8] = SCE->REG_100H; + S_HEAP[9] = SCE->REG_100H; + S_HEAP[10] = SCE->REG_100H; + S_HEAP[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[12] = SCE->REG_100H; + S_HEAP[13] = SCE->REG_100H; + S_HEAP[14] = SCE->REG_100H; + S_HEAP[15] = SCE->REG_100H; + R_SCE_func100(0x34680293U, 0x39dd9da8U, 0x9de57739U, 0xf0213a92U); + SCE->REG_D0H = 0x00000100U; + SCE->REG_C4H = 0x40e087bfU; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[16] = SCE->REG_100H; + S_HEAP[17] = SCE->REG_100H; + S_HEAP[18] = SCE->REG_100H; + S_HEAP[19] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[20] = SCE->REG_100H; + S_HEAP[21] = SCE->REG_100H; + S_HEAP[22] = SCE->REG_100H; + S_HEAP[23] = SCE->REG_100H; + R_SCE_func100(0x135be492U, 0xfcebca2fU, 0x13209927U, 0x69b81b01U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[24] = SCE->REG_100H; + S_HEAP[25] = SCE->REG_100H; + S_HEAP[26] = SCE->REG_100H; + S_HEAP[27] = SCE->REG_100H; + R_SCE_func100(0x08e7e299U, 0xbc12519eU, 0x04c40bbfU, 0xa614af79U); + R_SCE_func071_r2(OFS_ADR); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x38615939U, 0xd2efd875U, 0x9f932baaU, 0x32ba18ffU); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + R_SCE_func100(0x32dff07dU, 0x0579e031U, 0x3916c950U, 0x647d7461U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000c28U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d41U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x6f5c7973U, 0x5d3bb475U, 0x8d7ba199U, 0xa2e3c634U); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f0U; + SCE->REG_ECH = 0x0000373cU; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + R_SCE_func101(0x7a838a51U, 0x6cce7ddfU, 0xee2b1e5fU, 0xe71c048fU); + R_SCE_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0xb5ca6269U, 0xd2aa2e94U, 0x9a4952d4U, 0xee7c2192U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xd3d2ab1aU, 0x645767f3U, 0xd3f45929U, 0xaa121ce1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x765d5237U, 0x65a3d761U, 0x00c15f28U, 0x7bc8560bU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000029U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000828U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xb8c94f32U, 0xd2bbbd16U, 0xef613e67U, 0xac60674aU); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + R_SCE_func101(0x7a4e80f2U, 0xdf244a3cU, 0x932b9183U, 0x12582515U); + R_SCE_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0x759e4039U, 0x1747ee2fU, 0x736005abU, 0x2275520fU); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x22e485b0U, 0x2d734131U, 0xfaeebc70U, 0xac70c4f6U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xc4ac4363U, 0xac282526U, 0x8065d742U, 0x1f486f7aU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f0U); + R_SCE_func101(0xaf83a94bU, 0x7c2b7d43U, 0xceccec83U, 0xbee4238fU); + R_SCE_func303(); + R_SCE_func301(); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x0000000aU; + SCE->REG_24H = 0x80000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000000aU; + SCE->REG_24H = 0x8000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000018U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000019U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000015U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func305(); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xb153a145U, 0x8f010bbdU, 0x2111b502U, 0x24e06cb0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x4d058847U, 0x732c3fd3U, 0xf8232eabU, 0xd256c1e3U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000004U); + R_SCE_func101(0xac9d7a87U, 0x8a1a8270U, 0xa13b56caU, 0x76873dafU); + R_SCE_func303(); + R_SCE_func301(); + SCE->REG_104H = 0x00001762U; + SCE->REG_D0H = 0x00000500U; + SCE->REG_C4H = 0x42f087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[0]; + SCE->REG_100H = S_HEAP[1]; + SCE->REG_100H = S_HEAP[2]; + SCE->REG_100H = S_HEAP[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[4]; + SCE->REG_100H = S_HEAP[5]; + SCE->REG_100H = S_HEAP[6]; + SCE->REG_100H = S_HEAP[7]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[8]; + SCE->REG_100H = S_HEAP[9]; + SCE->REG_100H = S_HEAP[10]; + SCE->REG_100H = S_HEAP[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[12]; + SCE->REG_100H = S_HEAP[13]; + SCE->REG_100H = S_HEAP[14]; + SCE->REG_100H = S_HEAP[15]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[16]; + SCE->REG_100H = S_HEAP[17]; + SCE->REG_100H = S_HEAP[18]; + SCE->REG_100H = S_HEAP[19]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[20]; + SCE->REG_100H = S_HEAP[21]; + SCE->REG_100H = S_HEAP[22]; + SCE->REG_100H = S_HEAP[23]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[24]; + SCE->REG_100H = S_HEAP[25]; + SCE->REG_100H = S_HEAP[26]; + SCE->REG_100H = S_HEAP[27]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000828U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x3a1a3204U, 0x07b935d2U, 0xc28bfa31U, 0xb83db6fbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xcb7335eeU, 0x310a5cbdU, 0x7c67bc91U, 0x5abc5de7U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00000ac0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000005U); + R_SCE_func101(0xa4ab2b7dU, 0xf9acd790U, 0x2504beb9U, 0xfceb227eU); + R_SCE_func303(); + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f0U); + R_SCE_func101(0xaa191445U, 0xafee2bd5U, 0x9c17bdb8U, 0xe3948940U); + R_SCE_func043(); + SCE->REG_ECH = 0x00003799U; + R_SCE_func074_r1(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f0U); + R_SCE_func101(0xe8510b39U, 0xcca18a70U, 0xe151c6b3U, 0x39b7bdedU); + R_SCE_func044(); + SCE->REG_104H = 0x00000762U; + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000018U; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xc7bc8bf6U, 0x1ee0510aU, 0x67650962U, 0x8e587dfbU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x907b6d34U, 0x94fbd420U, 0xc6323182U, 0x81ba2497U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x80000c2dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x8000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x33a8a531U, 0xf5d8f41eU, 0x7de14417U, 0xdc4d6438U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x1d930db0U, 0x45cf8691U, 0x9532f2ebU, 0x3f70576aU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0xd1dda6abU, 0xfc0b53b0U, 0x720fbd8fU, 0xba3333eaU); + SCE->REG_2CH = 0x0000002bU; + SCE->REG_04H = 0x00000322U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[0] = SCE->REG_100H; + OutData_Signature[1] = SCE->REG_100H; + OutData_Signature[2] = SCE->REG_100H; + OutData_Signature[3] = SCE->REG_100H; + OutData_Signature[4] = SCE->REG_100H; + OutData_Signature[5] = SCE->REG_100H; + OutData_Signature[6] = SCE->REG_100H; + OutData_Signature[7] = SCE->REG_100H; + R_SCE_func100(0x8102dd45U, 0xf907dcd3U, 0xcd465204U, 0xd195885aU); + SCE->REG_2CH = 0x0000002aU; + SCE->REG_04H = 0x00000322U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[8] = SCE->REG_100H; + OutData_Signature[9] = SCE->REG_100H; + OutData_Signature[10] = SCE->REG_100H; + OutData_Signature[11] = SCE->REG_100H; + OutData_Signature[12] = SCE->REG_100H; + OutData_Signature[13] = SCE->REG_100H; + OutData_Signature[14] = SCE->REG_100H; + OutData_Signature[15] = SCE->REG_100H; + R_SCE_func102(0x9a9a7812U, 0xbcade75fU, 0x588e4ce5U, 0x59fa7e00U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pf0_r4.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf1.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf1.c new file mode 100644 index 0000000000..9b76dd651a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf1.c @@ -0,0 +1,1877 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_EcdsaSignatureVerificationSub(uint32_t *InData_CurveType, uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_MsgDgst, uint32_t *InData_Signature) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f101U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010380U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_104H = 0x00001768U; + SCE->REG_E0H = 0x8098001eU; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[iLoop + 0]; + } + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[iLoop + 0]; + } + for (iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000d3e0U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x38000c00U; + SCE->REG_ECH = 0x1000d3e0U; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000381eU; + SCE->REG_ECH = 0x000037beU; + SCE->REG_ECH = 0x0000a7a0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000383dU; + SCE->REG_ECH = 0x38001001U; + SCE->REG_ECH = 0x1000d3e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + SCE->REG_ECH = 0x0000a7c0U; + SCE->REG_ECH = 0x00000020U; + } + SCE->REG_ECH = 0x30000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d3e1U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x38000f9cU; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0xbf79d23bU, 0xf07cf107U, 0x750aed1eU, 0xcaeff594U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x3d034ce4U, 0xc57b218aU, 0xb9eed770U, 0xed2741d5U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_28H = 0x00870001U; + R_SCE_func100(0x0ce64850U, 0x878b0a23U, 0xe1cb6cc2U, 0x0f5c41d9U); + SCE->REG_ECH = 0x30003340U; + SCE->REG_ECH = 0x00050020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000004C8U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x0000031CU; + SCE->REG_ECH = 0x00070040U; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x0000013CU; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000001F8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + R_SCE_func100(0x87a8449aU, 0xcf671f93U, 0xee106edcU, 0x755cb143U); + R_SCE_func070_r2(OFS_ADR); + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8190001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000015U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xdaba6e72U, 0xb57ff7b1U, 0x5a939e80U, 0xdbc4e356U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x671b6ea8U, 0x9dd05ee5U, 0x88fcff59U, 0x475410f3U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f1U); + R_SCE_func101(0x39ec3342U, 0x23c1a691U, 0x90ace9b4U, 0x5994bf83U); + R_SCE_func303(); + R_SCE_func100(0xaf87ca1eU, 0xe21969cbU, 0xd22539baU, 0x6f99812cU); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x8088000aU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x8000d4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func071_r2(OFS_ADR); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8088000aU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f1U; + SCE->REG_ECH = 0x0000377cU; + SCE->REG_ECH = 0x00000b9cU; + R_SCE_func100(0x1452f4c9U, 0x98d73272U, 0x50b9f2a7U, 0xb34bad2fU); + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + R_SCE_func101(0x3089bf38U, 0x72054e04U, 0xf5147853U, 0xf8e27515U); + R_SCE_func302(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0x6e0cf91eU, 0x08da40caU, 0x512d9b67U, 0x3212a4caU); + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8188000aU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x25315488U, 0x40777691U, 0xad4c9d37U, 0xf2f44df1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x28b09d30U, 0x494dc8d6U, 0xa42eb978U, 0x8d6225feU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000006U); + R_SCE_func101(0x4633cb6fU, 0x94d3f17eU, 0x43c907bcU, 0xf47839ceU); + R_SCE_func303(); + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000379bU; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f1U); + R_SCE_func101(0x6b5ae87fU, 0x029b2c69U, 0x118b193eU, 0xf083ab01U); + R_SCE_func043(); + R_SCE_func075_r1(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f1U); + R_SCE_func101(0xdfea1497U, 0x4968a198U, 0x7f5581cfU, 0xe0d013feU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00000f62U; + SCE->REG_D0H = 0x40000300U; + SCE->REG_C4H = 0x02e08887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xac7cc0baU, 0xccc0c65dU, 0x37851923U, 0x8a567077U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x6037d272U, 0xe4279fb8U, 0xa63d6985U, 0x5d45927cU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8088000aU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x8088000aU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_ECH = 0x00000b9cU; + R_SCE_func100(0xc994220eU, 0x8947a3ffU, 0x31df28f3U, 0xd5fe9d71U); + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + R_SCE_func101(0xf67f1bc0U, 0x6722559cU, 0xd3153beaU, 0x8317be89U); + R_SCE_func302(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0xdddceea0U, 0x48cffb92U, 0x9741baa2U, 0x8c23c845U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x2648299aU, 0x1035dc95U, 0xe92aaafaU, 0x09f2ee5cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xaa09cd3aU, 0x8510da83U, 0x78b3a219U, 0x740c6e37U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8188000aU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x8188000aU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func305(); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xbd4dc745U, 0xce29c19cU, 0x919bb35bU, 0x07b8965fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xfaa695f3U, 0x4dfc1194U, 0x82cdde98U, 0x8d791f55U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800048d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000007U); + R_SCE_func101(0xe13c5110U, 0xf2ca31a5U, 0xada8273aU, 0x8d7400a0U); + R_SCE_func303(); + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x8188000aU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xd82c0a4eU, 0x77a96771U, 0x936d8c25U, 0xbd4e8cbdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x7e5c8cdfU, 0x3bcc0c66U, 0x2e99b8fcU, 0xaf63e3e3U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func102(0x78de24cdU, 0x6eea7b40U, 0x097d48aaU, 0x45796886U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pf1_r4.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf4.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf4.c new file mode 100644 index 0000000000..c575c454f3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf4.c @@ -0,0 +1,1365 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateEccRandomKeyIndexSub(uint32_t *InData_CurveType, uint32_t *InData_Cmd, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PrivKeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f402U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010380U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x3020ab80U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x00060020U; + SCE->REG_ECH = 0x0000b780U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_ECH = 0x30000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000d3e1U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x38000f9cU; + SCE->REG_ECH = 0x1000d3e1U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x38008be0U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + R_SCE_func100(0x8155dc50U, 0x0d1869b9U, 0x7213dafbU, 0x29d38597U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xa05109acU, 0xd0e24564U, 0x0f9c3ca0U, 0xaf6b7352U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x411f0528U, 0x15c03807U, 0x83cc0c83U, 0xaca27c2dU); + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x30003340U; + SCE->REG_ECH = 0x00050020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000004C8U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x0000031CU; + SCE->REG_ECH = 0x00070040U; + SCE->REG_ECH = 0x30003380U; + SCE->REG_ECH = 0x00070020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00030040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x0000013CU; + SCE->REG_ECH = 0x00050040U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000001F8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + R_SCE_func100(0x89e767c7U, 0x3b5adcdcU, 0x166c61e0U, 0x42952bfaU); + R_SCE_func070_r2(OFS_ADR); + R_SCE_func100(0xfc4a946bU, 0xb61d5f70U, 0x0ebd9f53U, 0x8d13364aU); + SCE->REG_34H = 0x00000003U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000400U; + SCE->REG_24H = 0x8000c0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00890001U; + R_SCE_func103(); + R_SCE_func100(0x8f7ac3b7U, 0x218684ddU, 0xfe14a6c4U, 0x838c4da6U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + R_SCE_func100(0x482a2664U, 0x9938e8a3U, 0x57ba858cU, 0xe5f47d50U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + R_SCE_func100(0xde0838d4U, 0x5f03e854U, 0x328d488dU, 0x2e545c0fU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x0000320bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00007c1cU; + SCE->REG_1CH = 0x00600000U; + SCE->REG_1D0H = 0x00000000U; + if (0x00000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_28H = 0x00890001U; + R_SCE_func101(0xaddbfa7aU, 0x9d98446aU, 0x5c8c28bfU, 0x8fcf0da8U); + } + else if (0x01000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_28H = 0x00880001U; + R_SCE_func101(0x7cfe0a7cU, 0xc42a03a3U, 0x02d6630dU, 0xeaa1c652U); + } + else if (0x02000000U == (SCE->REG_1CH & 0xff000000U)) + { + SCE->REG_28H = 0x00870001U; + R_SCE_func101(0xbc44913aU, 0x2e9dd705U, 0xf8112889U, 0x4b75da35U); + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x0000a206U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000016c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000682U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xc22a42f0U, 0xd7513ef3U, 0x141945b8U, 0x4f9677cbU); + R_SCE_func071_r2(OFS_ADR); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x0a80b6b0U, 0xd0860a65U, 0xb3795e56U, 0x738ec97aU); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + R_SCE_func100(0x33b12a00U, 0x5f8a73ffU, 0x6cfe2a4cU, 0x97d6bd7cU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + R_SCE_func100(0xe5b76a52U, 0x4d78dc94U, 0x0689ede0U, 0xaacd6c42U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000c28U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d41U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f4U; + SCE->REG_ECH = 0x0000377cU; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + R_SCE_func101(0xc91d7184U, 0x21193a7dU, 0xd6243ba3U, 0xee90d6c5U); + R_SCE_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0x7c8eadaeU, 0x7dcb07ebU, 0x260f06b4U, 0x41d8a178U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xbc10b89dU, 0x39391c8cU, 0xe24b5d13U, 0x3c1a8ba2U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x432a1136U, 0xda828672U, 0x50fa59ecU, 0x561f4660U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000029U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000828U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xec9c2d1eU, 0xb6c118b9U, 0xbde212c7U, 0xcdfed6d5U); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000005U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + R_SCE_func101(0x7f728af4U, 0x9ee9c0c1U, 0xb2c2115cU, 0x51d5f5aeU); + R_SCE_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0xdbd0a215U, 0x381d8b8aU, 0x1e5c7897U, 0xb706692fU); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x6e8596f1U, 0x40c25e30U, 0xce5ac6a9U, 0x67388ce1U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x9ee0f0ecU, 0x59940651U, 0xedb5f553U, 0x5c33c111U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f4U); + R_SCE_func101(0x4fd23f3eU, 0x8ccf2e1cU, 0xaa410902U, 0x35952722U); + R_SCE_func303(); + R_SCE_func301(); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x0000000aU; + SCE->REG_24H = 0x80000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000000aU; + SCE->REG_24H = 0x8000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000018U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000019U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000015U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func305(); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x8034e0c2U, 0x1d984d4fU, 0x124cb87bU, 0x09f02c0cU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb28ad0c6U, 0x5f17e046U, 0x18d69106U, 0xfcd9f238U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x8088001fU; + SCE->REG_00H = 0x00008323U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000008U); + R_SCE_func101(0xcd2be246U, 0x764dbf66U, 0x5b73978aU, 0x3e5fc7caU); + R_SCE_func303(); + R_SCE_func301(); + R_SCE_func100(0x49ac0cc8U, 0x255c3125U, 0xff9b57cfU, 0xa1c1a0e7U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f4U); + R_SCE_func101(0x704820f0U, 0xbfaa4790U, 0xeb57dc91U, 0x134f733bU); + R_SCE_func043(); + SCE->REG_ECH = 0x0000379bU; + R_SCE_func074_r1(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f4U); + R_SCE_func101(0xfa1e3b20U, 0xa1b1b225U, 0xd9b69d10U, 0xa2e0dd0eU); + R_SCE_func044(); + R_SCE_func100(0xd83ba1ccU, 0x1eee6285U, 0x1b2b6e07U, 0x6989a98cU); + SCE->REG_D0H = 0x40000100U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x8188001fU; + SCE->REG_00H = 0x00002823U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[1] = SCE->REG_100H; + OutData_PrivKeyIndex[2] = SCE->REG_100H; + OutData_PrivKeyIndex[3] = SCE->REG_100H; + OutData_PrivKeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[5] = SCE->REG_100H; + OutData_PrivKeyIndex[6] = SCE->REG_100H; + OutData_PrivKeyIndex[7] = SCE->REG_100H; + OutData_PrivKeyIndex[8] = SCE->REG_100H; + R_SCE_func100(0x7e889b5eU, 0xdd638f3dU, 0x9c2841e2U, 0xe10cc3b9U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[9] = SCE->REG_100H; + OutData_PrivKeyIndex[10] = SCE->REG_100H; + OutData_PrivKeyIndex[11] = SCE->REG_100H; + OutData_PrivKeyIndex[12] = SCE->REG_100H; + R_SCE_func100(0xcb315cd5U, 0xb29c331aU, 0x5698c4a9U, 0x57e92ceaU); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[0] = SCE->REG_100H; + R_SCE_func100(0xbdeab0a1U, 0x7e8f4addU, 0x19e92afdU, 0xa7945b04U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001U); + R_SCE_func101(0xa5f69687U, 0x0ff1f787U, 0x09eadd7eU, 0xa27b413aU); + R_SCE_func043(); + R_SCE_func075_r1(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000002U); + R_SCE_func101(0x08a7c0d0U, 0x2be8f4e7U, 0x18659546U, 0x45c92644U); + R_SCE_func044(); + R_SCE_func100(0x8f48872bU, 0x7b9007fbU, 0xc94927edU, 0x76ecbb1bU); + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02e08887U; + SCE->REG_00H = 0x00002323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00002313U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[1] = SCE->REG_100H; + OutData_PubKeyIndex[2] = SCE->REG_100H; + OutData_PubKeyIndex[3] = SCE->REG_100H; + OutData_PubKeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[5] = SCE->REG_100H; + OutData_PubKeyIndex[6] = SCE->REG_100H; + OutData_PubKeyIndex[7] = SCE->REG_100H; + OutData_PubKeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[9] = SCE->REG_100H; + OutData_PubKeyIndex[10] = SCE->REG_100H; + OutData_PubKeyIndex[11] = SCE->REG_100H; + OutData_PubKeyIndex[12] = SCE->REG_100H; + R_SCE_func100(0xc557b19bU, 0xdbbdcffbU, 0xf2f98ccaU, 0xff226369U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x00e08885U; + SCE->REG_00H = 0x00002313U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000222U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[13] = SCE->REG_100H; + OutData_PubKeyIndex[14] = SCE->REG_100H; + OutData_PubKeyIndex[15] = SCE->REG_100H; + OutData_PubKeyIndex[16] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[17] = SCE->REG_100H; + OutData_PubKeyIndex[18] = SCE->REG_100H; + OutData_PubKeyIndex[19] = SCE->REG_100H; + OutData_PubKeyIndex[20] = SCE->REG_100H; + R_SCE_func100(0x8b7e2612U, 0xd2051faaU, 0xb9904e1eU, 0x603d6860U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[0] = SCE->REG_100H; + R_SCE_func102(0x584df465U, 0x76e68729U, 0x9667a566U, 0x6c6f89e8U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pf4_r5.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf5.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf5.c new file mode 100644 index 0000000000..aee3cadf77 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf5.c @@ -0,0 +1,1758 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_EcdsaP384SignatureGenerateSub(uint32_t *InData_CurveType, uint32_t *InData_KeyIndex, uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f502U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0x167265a4U, 0x52398114U, 0x35b37231U, 0x2f3a6abaU); + SCE->REG_28H = 0x008b0001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000002B4U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000003D8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + R_SCE_func100(0x5088b8f9U, 0x0c306a82U, 0x57f52388U, 0xf0571cb1U); + R_SCE_func027_r2(OFS_ADR); + R_SCE_func100(0x4a74ff13U, 0x5e7b3dd0U, 0x00ba597bU, 0x2009e88eU); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800098d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001U; + R_SCE_func103(); + R_SCE_func100(0x621ac5baU, 0xc1262c80U, 0x6ac3397cU, 0x8341ac5cU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01080c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + R_SCE_func100(0x86f0c862U, 0x22c5bd88U, 0xadff83caU, 0xad3e2e17U); + SCE->REG_D0H = 0x00000700U; + SCE->REG_C4H = 0x42e087bfU; + SCE->REG_00H = 0x00002383U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_04H = 0x00000282U; + for (iLoop=0; iLoop<32; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + R_SCE_func100(0xac2fb8b6U, 0xfca66694U, 0x506a5f5bU, 0x206056ceU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x400009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + SCE->REG_28H = 0x008b0001U; + R_SCE_func100(0xe2fb0784U, 0xa65f0843U, 0xa8f8e74bU, 0x453f3515U); + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + R_SCE_func100(0x8c1846c4U, 0x93acc07eU, 0x0ec5dd3dU, 0x156513f4U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xafee66dcU, 0x93872315U, 0xb70e27cbU, 0xaa689dfdU); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00001228U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xaee9cdddU, 0x9ea77476U, 0x1ca7e00eU, 0xbcc8c71bU); + R_SCE_func028_r2(OFS_ADR); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xa70bce34U, 0x1c751c8dU, 0x146eb308U, 0xbca419bfU); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + R_SCE_func100(0x5c7e8d07U, 0x858d4b79U, 0x6307637bU, 0xde746086U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x70d2a921U, 0xf697dfd4U, 0xc403c9bdU, 0xdf017928U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000c28U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d41U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x2fe4121bU, 0xab75a8e1U, 0x64f57b43U, 0x13ca4219U); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000180U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f5U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + R_SCE_func101(0xbbf1567dU, 0x4038110bU, 0x373e1825U, 0x691c62dcU); + R_SCE_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0x0a69ebd4U, 0xef1436fbU, 0x9b52d3feU, 0x30af8d94U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xef64a081U, 0x956ed81aU, 0x9d2a68c9U, 0x310d6a70U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb6cfa9b1U, 0xfaf4b60eU, 0xce6aa392U, 0xa66e9f0dU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000029U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000828U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0x606b0eabU, 0x67bb0bb0U, 0xb63ab233U, 0xf83d8a68U); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000180U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000006U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + R_SCE_func101(0x4d7fd74dU, 0x96593dfaU, 0xd962d9ffU, 0x0eed7246U); + R_SCE_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0x5c6e4fd0U, 0x03589975U, 0x384794fcU, 0xac6b2fd1U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xb38fdffcU, 0x84dedba1U, 0xe74a0902U, 0xbe462952U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xd50e7ddcU, 0x6c847d8bU, 0x8411db64U, 0xad92d393U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f5U); + R_SCE_func101(0x8e2d5328U, 0xe723bd66U, 0xf3f3eef8U, 0xc59f319bU); + R_SCE_func303(); + R_SCE_func301(); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x0000000aU; + SCE->REG_24H = 0x80000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000000aU; + SCE->REG_24H = 0x8000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000018U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000019U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000015U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func305(); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x44a0f298U, 0x62b21cb2U, 0x5b638628U, 0x80e6bba8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xeafda8aeU, 0x3cd6eddaU, 0x3e671197U, 0x4c08c367U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000009U); + R_SCE_func101(0x12024cbaU, 0x9b0d3209U, 0x0e05fb6cU, 0x7b322d96U); + R_SCE_func303(); + R_SCE_func301(); + SCE->REG_28H = 0x008f0001U; + SCE->REG_104H = 0x00001f62U; + SCE->REG_D0H = 0x00000700U; + SCE->REG_C4H = 0x42f087bfU; + SCE->REG_00H = 0x00003243U; + SCE->REG_2CH = 0x00000014U; + for (iLoop=0; iLoop<16; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00003243U; + SCE->REG_2CH = 0x0000001dU; + for (iLoop=16; iLoop<32; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x400007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_C4H = 0x00800c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x008b0001U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000828U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xcc7ce5c7U, 0x43d5457dU, 0x7cff2d04U, 0xb9b0c464U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x03a571a8U, 0xf8ec296aU, 0xfe6bc66dU, 0x90c48b2fU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00000ac0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000011U); + R_SCE_func101(0xb1bf1d19U, 0xc5f35afdU, 0xef5d474cU, 0x15bcd454U); + R_SCE_func303(); + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000011U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[0]; + SCE->REG_100H = InData_MsgDgst[1]; + SCE->REG_100H = InData_MsgDgst[2]; + SCE->REG_100H = InData_MsgDgst[3]; + SCE->REG_100H = InData_MsgDgst[4]; + SCE->REG_100H = InData_MsgDgst[5]; + SCE->REG_100H = InData_MsgDgst[6]; + SCE->REG_100H = InData_MsgDgst[7]; + SCE->REG_100H = InData_MsgDgst[8]; + SCE->REG_100H = InData_MsgDgst[9]; + SCE->REG_100H = InData_MsgDgst[10]; + SCE->REG_100H = InData_MsgDgst[11]; + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020U; + SCE->REG_24H = 0x80001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f5U); + R_SCE_func101(0x3df70650U, 0xf22ea7f6U, 0x764f1294U, 0x329705a0U); + R_SCE_func043(); + R_SCE_func076(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f5U); + R_SCE_func101(0x95dd8c7fU, 0x06ede9a5U, 0x8277a394U, 0x962295dfU); + R_SCE_func044(); + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02f087b7U; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x00000018U; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xf5f2eb8aU, 0x558a8f7cU, 0x16cdd519U, 0xfb450314U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x0c1abe11U, 0x5a35450eU, 0x41b6b04dU, 0xabd15dadU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x80000c2dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x8000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xcb515f22U, 0xbe10a362U, 0xc57d5625U, 0x1b90bdc4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xf1a753d3U, 0x1537e22eU, 0x8ac68cbdU, 0x88eb12d4U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func100(0x0d0b368aU, 0x6f91c3e6U, 0x4a7bd43dU, 0x67e1b70eU); + SCE->REG_2CH = 0x0000002bU; + SCE->REG_04H = 0x00000332U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[0] = SCE->REG_100H; + OutData_Signature[1] = SCE->REG_100H; + OutData_Signature[2] = SCE->REG_100H; + OutData_Signature[3] = SCE->REG_100H; + OutData_Signature[4] = SCE->REG_100H; + OutData_Signature[5] = SCE->REG_100H; + OutData_Signature[6] = SCE->REG_100H; + OutData_Signature[7] = SCE->REG_100H; + OutData_Signature[8] = SCE->REG_100H; + OutData_Signature[9] = SCE->REG_100H; + OutData_Signature[10] = SCE->REG_100H; + OutData_Signature[11] = SCE->REG_100H; + R_SCE_func100(0xd5bf6a4fU, 0x2928c95aU, 0xe85a7b76U, 0x232ab1b3U); + SCE->REG_2CH = 0x0000002aU; + SCE->REG_04H = 0x00000332U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[12] = SCE->REG_100H; + OutData_Signature[13] = SCE->REG_100H; + OutData_Signature[14] = SCE->REG_100H; + OutData_Signature[15] = SCE->REG_100H; + OutData_Signature[16] = SCE->REG_100H; + OutData_Signature[17] = SCE->REG_100H; + OutData_Signature[18] = SCE->REG_100H; + OutData_Signature[19] = SCE->REG_100H; + OutData_Signature[20] = SCE->REG_100H; + OutData_Signature[21] = SCE->REG_100H; + OutData_Signature[22] = SCE->REG_100H; + OutData_Signature[23] = SCE->REG_100H; + R_SCE_func102(0xc3115788U, 0x0a3c02e9U, 0x3af86351U, 0x625e93e9U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pf5_r4.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf6.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf6.c new file mode 100644 index 0000000000..cb0f0ac932 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf6.c @@ -0,0 +1,1854 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_EcdsaP384SignatureVerificationSub(uint32_t *InData_CurveType, uint32_t *InData_KeyIndex, uint32_t *InData_MsgDgst, uint32_t *InData_Signature) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f601U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0x4576b7d9U, 0x64629363U, 0x5888f7b4U, 0x5730d0a0U); + SCE->REG_28H = 0x008b0001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000002B4U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000003D8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + R_SCE_func100(0xfbe0cca9U, 0x90cbb085U, 0xf9638a1aU, 0x19ce51d0U); + R_SCE_func027_r2(OFS_ADR); + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x80006cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000bcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000015U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[0]; + SCE->REG_100H = InData_Signature[1]; + SCE->REG_100H = InData_Signature[2]; + SCE->REG_100H = InData_Signature[3]; + SCE->REG_100H = InData_Signature[4]; + SCE->REG_100H = InData_Signature[5]; + SCE->REG_100H = InData_Signature[6]; + SCE->REG_100H = InData_Signature[7]; + SCE->REG_100H = InData_Signature[8]; + SCE->REG_100H = InData_Signature[9]; + SCE->REG_100H = InData_Signature[10]; + SCE->REG_100H = InData_Signature[11]; + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[12]; + SCE->REG_100H = InData_Signature[13]; + SCE->REG_100H = InData_Signature[14]; + SCE->REG_100H = InData_Signature[15]; + SCE->REG_100H = InData_Signature[16]; + SCE->REG_100H = InData_Signature[17]; + SCE->REG_100H = InData_Signature[18]; + SCE->REG_100H = InData_Signature[19]; + SCE->REG_100H = InData_Signature[20]; + SCE->REG_100H = InData_Signature[21]; + SCE->REG_100H = InData_Signature[22]; + SCE->REG_100H = InData_Signature[23]; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x4ad15b3dU, 0x815dd2caU, 0xf7d610ddU, 0x31294f37U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x7dfabf6aU, 0x9586d325U, 0xd3f5f94eU, 0x5c5f8727U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f6U); + R_SCE_func101(0x47438803U, 0xcb30a035U, 0x1f901d93U, 0xfaf03445U); + R_SCE_func303(); + R_SCE_func100(0xa61ba019U, 0x0a7e8da6U, 0x4212022dU, 0xd058c337U); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000094aU; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[0]; + SCE->REG_100H = InData_MsgDgst[1]; + SCE->REG_100H = InData_MsgDgst[2]; + SCE->REG_100H = InData_MsgDgst[3]; + SCE->REG_100H = InData_MsgDgst[4]; + SCE->REG_100H = InData_MsgDgst[5]; + SCE->REG_100H = InData_MsgDgst[6]; + SCE->REG_100H = InData_MsgDgst[7]; + SCE->REG_100H = InData_MsgDgst[8]; + SCE->REG_100H = InData_MsgDgst[9]; + SCE->REG_100H = InData_MsgDgst[10]; + SCE->REG_100H = InData_MsgDgst[11]; + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x8000d4d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func028_r2(OFS_ADR); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000180U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f6U; + SCE->REG_ECH = 0x00000b9cU; + R_SCE_func100(0xc4deee4cU, 0x6decadd0U, 0xa28c2b5cU, 0x6109d39cU); + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + R_SCE_func101(0x20e787edU, 0xe6c7f710U, 0x6e89a21bU, 0x59255b84U); + R_SCE_func302(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0xce00acb7U, 0x48f74d37U, 0xe51625cdU, 0x413d581cU); + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x818c000aU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x94358768U, 0x8788e338U, 0x42bbbc7aU, 0xf5df9ffdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb8e6bbc7U, 0x8ab60c35U, 0xe54538e9U, 0xc52d5662U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00004404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000012U); + R_SCE_func101(0x012547ecU, 0xf0d4808eU, 0x3af52df7U, 0x03db2b32U); + R_SCE_func303(); + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800100e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f6U); + R_SCE_func101(0x3a2d77daU, 0xbab4b2e7U, 0x1c849ba4U, 0x7de03458U); + R_SCE_func043(); + R_SCE_func077(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f6U); + R_SCE_func101(0xefcc3c63U, 0x8c1440a0U, 0x5060ab47U, 0xd1a98bdeU); + R_SCE_func044(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00040804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_104H = 0x00001762U; + SCE->REG_D0H = 0x40000500U; + SCE->REG_C4H = 0x02e08887U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_100H = InData_KeyIndex[16]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_100H = InData_KeyIndex[20]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[21]; + SCE->REG_100H = InData_KeyIndex[22]; + SCE->REG_100H = InData_KeyIndex[23]; + SCE->REG_100H = InData_KeyIndex[24]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000087b5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[25]; + SCE->REG_100H = InData_KeyIndex[26]; + SCE->REG_100H = InData_KeyIndex[27]; + SCE->REG_100H = InData_KeyIndex[28]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xc4aae4c4U, 0x0e48f5d8U, 0x7770796dU, 0x19492279U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xc59d14d9U, 0x05dde658U, 0xd2aeb160U, 0xa2660844U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000180U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000002U; + SCE->REG_ECH = 0x00000b9cU; + R_SCE_func100(0x671bab3aU, 0x875e98d9U, 0x3c12995aU, 0x4d5de973U); + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + R_SCE_func101(0x3152de7eU, 0xe2908fc2U, 0x8b64fa9cU, 0x88d51965U); + R_SCE_func302(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0xa96e95beU, 0x85da0420U, 0x695bfe58U, 0x4d423555U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x7bb05104U, 0x8bf81b66U, 0x6bef9c3bU, 0xa535e0d0U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x74ebeb22U, 0xf1a0da4bU, 0xb264a82eU, 0x9d9383a6U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x818c000aU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x818c000aU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func305(); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x022d1f7aU, 0x46b3905fU, 0x8abbf9cbU, 0xba6dc8bdU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x46de9d75U, 0xbd99ee58U, 0x7206ab0fU, 0xb1c84ebdU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000013U); + R_SCE_func101(0xe45d4f83U, 0x4cb52e20U, 0x4758767eU, 0x6d895cd0U); + R_SCE_func303(); + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x818c000aU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x082d5495U, 0xc802eb4aU, 0xa116accdU, 0xb07ef84dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xd35db910U, 0xe692732dU, 0xaaf5ff18U, 0x88876567U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + R_SCE_func102(0xa0c82708U, 0x1894af63U, 0x2bd558a5U, 0x5a576d51U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pf6_r4.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf9.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf9.c new file mode 100644 index 0000000000..ad680d67bd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf9.c @@ -0,0 +1,1331 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t R_SCE_GenerateEccP384RandomKeyIndexSub(uint32_t *InData_CurveType, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PrivKeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f902U; + SCE->REG_108H = 0x00000000U; + R_SCE_func100(0xc7afef81U, 0x48345805U, 0x93156e87U, 0xc74abc8aU); + SCE->REG_28H = 0x008b0001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000002B4U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000003D8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + R_SCE_func100(0x46e7df26U, 0x81f3e8b6U, 0xa396710dU, 0xfdefaaefU); + R_SCE_func027_r2(OFS_ADR); + R_SCE_func100(0xa7841f65U, 0xb187cdb0U, 0xcf849412U, 0x151372c9U); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x008d0001U; + R_SCE_func103(); + R_SCE_func100(0x10f916f8U, 0xa801ce29U, 0x8253997cU, 0xde19254fU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + R_SCE_func100(0x3b9dc7cbU, 0x5b37795aU, 0xe136d56cU, 0x709b3213U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + R_SCE_func100(0x2a37054dU, 0x4bc6cb0bU, 0x08b9ca7cU, 0x1e6483daU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x0000320bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_24H = 0x0000a206U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x000016c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000682U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c2U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x008b0001U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0x3a0e2512U, 0xe2ef86edU, 0x69a6588dU, 0x77641f10U); + R_SCE_func028_r2(OFS_ADR); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xc25e97abU, 0xea176d21U, 0xd43f80d4U, 0xdef20804U); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func103(); + R_SCE_func100(0x8ea04f22U, 0x24a15cecU, 0x319a6a88U, 0x2c98d571U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + R_SCE_func100(0xf8218e10U, 0x1f2c97fcU, 0xe91247e8U, 0xe8bb190fU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func103(); + R_SCE_func100(0x65536e29U, 0xc4642c00U, 0xfe80bd7aU, 0x06f04bc8U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000c28U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d41U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000180U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x000000f9U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + R_SCE_func101(0x361c125fU, 0xfdfc9737U, 0xedd62214U, 0x1b17d0b5U); + R_SCE_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0xdda84da8U, 0x54de67b1U, 0x7f9336d7U, 0x1175c629U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x982ff807U, 0x7eb84b02U, 0xc1713c28U, 0x53ed0d1eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xb3365104U, 0x8b33fcf5U, 0x88a70324U, 0x5f4cb20dU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000013U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000029U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00000828U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + R_SCE_func100(0xf823cb0dU, 0x8533930fU, 0x7a86ad39U, 0x6c2a8bb3U); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000180U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x00000007U; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + R_SCE_func101(0x8f63dc4eU, 0x8a36e097U, 0xbc47e32eU, 0xac7d8b6cU); + R_SCE_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + R_SCE_func101(0x254d1b5aU, 0x004fb84aU, 0x0e89e7d0U, 0x94871414U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0x88c47862U, 0xab80ab75U, 0x6602dc7cU, 0x60a9e92dU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0xf6d060b8U, 0xf77ba8b8U, 0x6e22e11aU, 0x02e96631U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f9U); + R_SCE_func101(0x21363b46U, 0x671f5d1cU, 0x6c6263ddU, 0xcfd62e64U); + R_SCE_func303(); + R_SCE_func301(); + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x0000000aU; + SCE->REG_24H = 0x80000a2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000000aU; + SCE->REG_24H = 0x8000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000018U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x000000c0U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000019U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000100U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000015U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func305(); + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + R_SCE_func100(0xa057fd81U, 0xc1b8bf0fU, 0x29906e9cU, 0x249e1454U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + R_SCE_func102(0x03c73c0dU, 0x24847ce1U, 0xd1a04157U, 0x9329a5b1U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7c0U; + SCE->REG_ECH = 0x0000000cU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000014U); + R_SCE_func101(0x0cb80e60U, 0x1a1ffc94U, 0x916436bcU, 0x9ee1ae7fU); + R_SCE_func303(); + R_SCE_func301(); + R_SCE_func100(0x66d3eef4U, 0xb3e7f42fU, 0xb67ef69bU, 0x464b0f80U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f9U); + R_SCE_func101(0x45966ffaU, 0x5e90be93U, 0x00a08602U, 0xf71fa1f2U); + R_SCE_func043(); + R_SCE_func076(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f9U); + R_SCE_func101(0x9d95aaeaU, 0xf69a2b63U, 0x69374eb2U, 0x1816c351U); + R_SCE_func044(); + R_SCE_func100(0x50c95905U, 0xcafd39d0U, 0x44b053e8U, 0x8bd072efU); + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02e087b7U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000140U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00002833U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[1] = SCE->REG_100H; + OutData_PrivKeyIndex[2] = SCE->REG_100H; + OutData_PrivKeyIndex[3] = SCE->REG_100H; + OutData_PrivKeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[5] = SCE->REG_100H; + OutData_PrivKeyIndex[6] = SCE->REG_100H; + OutData_PrivKeyIndex[7] = SCE->REG_100H; + OutData_PrivKeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[9] = SCE->REG_100H; + OutData_PrivKeyIndex[10] = SCE->REG_100H; + OutData_PrivKeyIndex[11] = SCE->REG_100H; + OutData_PrivKeyIndex[12] = SCE->REG_100H; + R_SCE_func100(0x02051f83U, 0xff7a5860U, 0xc9b56e52U, 0x9406b088U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c5U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[13] = SCE->REG_100H; + OutData_PrivKeyIndex[14] = SCE->REG_100H; + OutData_PrivKeyIndex[15] = SCE->REG_100H; + OutData_PrivKeyIndex[16] = SCE->REG_100H; + R_SCE_func100(0x3903097dU, 0xbc45f4baU, 0x6fc46f67U, 0xc686ffb4U); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[0] = SCE->REG_100H; + R_SCE_func100(0x537a1aafU, 0x17d59a23U, 0x0e6839e9U, 0x4e990fe3U); + R_SCE_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80010000U; + SCE->REG_00H = 0x00008207U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0000020fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000034e0U; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000027U); + R_SCE_func101(0xf028941cU, 0x40ae6233U, 0x9d13746cU, 0x94d40692U); + R_SCE_func043(); + R_SCE_func077(); + SCE->REG_ECH = 0x000034feU; + SCE->REG_104H = 0x00000058U; + SCE->REG_E0H = 0x800103a0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000028U); + R_SCE_func101(0x28cd0f41U, 0x665c946dU, 0x7d055887U, 0xda792d85U); + R_SCE_func044(); + R_SCE_func100(0x0a59a206U, 0x2b22a646U, 0x827d3755U, 0x9443a4deU); + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x02e08887U; + SCE->REG_00H = 0x00002333U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[1] = SCE->REG_100H; + OutData_PubKeyIndex[2] = SCE->REG_100H; + OutData_PubKeyIndex[3] = SCE->REG_100H; + OutData_PubKeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[5] = SCE->REG_100H; + OutData_PubKeyIndex[6] = SCE->REG_100H; + OutData_PubKeyIndex[7] = SCE->REG_100H; + OutData_PubKeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[9] = SCE->REG_100H; + OutData_PubKeyIndex[10] = SCE->REG_100H; + OutData_PubKeyIndex[11] = SCE->REG_100H; + OutData_PubKeyIndex[12] = SCE->REG_100H; + R_SCE_func100(0xb7232ec8U, 0x82ae7eceU, 0xa325d6e0U, 0x5569f582U); + SCE->REG_D0H = 0x40000200U; + SCE->REG_C4H = 0x00e08887U; + SCE->REG_00H = 0x00002333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[13] = SCE->REG_100H; + OutData_PubKeyIndex[14] = SCE->REG_100H; + OutData_PubKeyIndex[15] = SCE->REG_100H; + OutData_PubKeyIndex[16] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[17] = SCE->REG_100H; + OutData_PubKeyIndex[18] = SCE->REG_100H; + OutData_PubKeyIndex[19] = SCE->REG_100H; + OutData_PubKeyIndex[20] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[21] = SCE->REG_100H; + OutData_PubKeyIndex[22] = SCE->REG_100H; + OutData_PubKeyIndex[23] = SCE->REG_100H; + OutData_PubKeyIndex[24] = SCE->REG_100H; + R_SCE_func100(0xd619fdb5U, 0xdc06410cU, 0xc7c61fbbU, 0x9819ffcbU); + SCE->REG_104H = 0x00000052U; + SCE->REG_D0H = 0x40000000U; + SCE->REG_C4H = 0x000089c4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[25] = SCE->REG_100H; + OutData_PubKeyIndex[26] = SCE->REG_100H; + OutData_PubKeyIndex[27] = SCE->REG_100H; + OutData_PubKeyIndex[28] = SCE->REG_100H; + R_SCE_func100(0x48ba2865U, 0x9b9af849U, 0xf04412f3U, 0x4aaaa45eU); + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[0] = SCE->REG_100H; + R_SCE_func102(0xef2c39afU, 0x6aa8b7efU, 0x22db227eU, 0x38824fe2U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_pf9_r5.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc01.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc01.c new file mode 100644 index 0000000000..4b89821c10 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc01.c @@ -0,0 +1,211 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_SelfCheck1SubSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0xf597806AU; + SCE->REG_10CH = 0x00010001U; + SCE->REG_10H = 0x01234567U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_78H = 0x00008007U; + SCE->REG_134H = 0x76543210U; + R_SCE_func054(change_endian_long(0x00003008U), change_endian_long(0x00003018U)); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + R_SCE_func050(change_endian_long(0x00010001U)); + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_68H = 0x00000417U; + SCE->REG_6CH = 0xabcdef01U; + R_SCE_func054(change_endian_long(0x10003008U), change_endian_long(0x10003018U)); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + R_SCE_func050(change_endian_long(0x00000001U)); + SCE->REG_28H = 0x00000001U; + SCE->REG_3CH = 0x00010173U; + SCE->REG_4CH = 0x23456789U; + SCE->REG_80H = 0x00000001U; + SCE->REG_8CH = 0x000080BBU; + SCE->REG_94H = 0xabcdef01U; + SCE->REG_7CH = 0x00000001U; + SCE->REG_78H = 0x0000011fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_68H = 0x00000017U; + R_SCE_func054(change_endian_long(0x72f01007U), change_endian_long(0x72f01017U)); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + for(iLoop = 0; iLoop < 6; iLoop = iLoop + 1) + { + R_SCE_func050(change_endian_long(0x00000001U)); + R_SCE_func054(change_endian_long(0x72f03007U), change_endian_long(0x72f03017U)); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + } + for(iLoop = 0; iLoop < 6; iLoop = iLoop + 1) + { + R_SCE_func050(change_endian_long(0x00000001U)); + SCE->REG_28H = 0x00000001U; + SCE->REG_80H = 0x00000001U; + SCE->REG_7CH = 0x00000001U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + R_SCE_func054(change_endian_long(0x72f03007U), change_endian_long(0x72f03017U)); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + R_SCE_func050(change_endian_long(0x00000001U)); + SCE->REG_28H = 0x00000001U; + SCE->REG_3CH = 0x00010173U; + SCE->REG_80H = 0x00000001U; + SCE->REG_B0H = 0x40000010U; + SCE->REG_D0H = 0x40000010U; + SCE->REG_A4H = 0x00008000U; + SCE->REG_C4H = 0x00008000U; + SCE->REG_8CH = 0x0000888BU; + SCE->REG_7CH = 0x00000001U; + SCE->REG_78H = 0x00000007U; + /* WAIT_LOOP */ + while (0U != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008U; + SCE->REG_68H = 0x00000017U; + R_SCE_func054(change_endian_long(0x7af03007U), change_endian_long(0x7af03017U)); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + } + R_SCE_func051(); + SCE->REG_28H = 0x00000001U; + SCE->REG_3CH = 0x00810173U; + R_SCE_func054(change_endian_long(0x00003008U), change_endian_long(0x00003018U)); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B31) + { + /* waiting */ + } + for(iLoop = 0; iLoop < 6; iLoop = iLoop + 1) + { + R_SCE_func052(change_endian_long(0x00810173U)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + R_SCE_func052(change_endian_long(0x0080197fU)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + R_SCE_func052(change_endian_long(0x00fe017bU)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + R_SCE_func052(change_endian_long(0x00af091FU)); + } + R_SCE_func053(change_endian_long(0x000380BBU)); + for(iLoop = 0; iLoop < 6; iLoop = iLoop + 1) + { + R_SCE_func053(change_endian_long(0x000380BBU)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + R_SCE_func053(change_endian_long(0x000191BBU)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + R_SCE_func053(change_endian_long(0x000185B7U)); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_subprc01.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc03.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc03.c new file mode 100644 index 0000000000..c6e691de5f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc03.c @@ -0,0 +1,477 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_TlsRootCertificateVerificationSubSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_28H = 0x00bf0001U; + R_SCE_func100(0x552875bbU, 0x392d0115U, 0xf49cf0c4U, 0x3a401b1dU); + SCE->REG_18H = 0x00000004U; + SCE->REG_34H = 0x00000000U; + SCE->REG_38H = 0x00000338U; + SCE->REG_E0H = 0x81010020U; + SCE->REG_00H = 0x00003807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B20) + { + /* waiting */ + } + SCE->REG_1CH = 0x00000e00U; + SCE->REG_28H = 0x00870001U; + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_28H = 0x00bf0001U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_E0H = 0x80a00001U; + SCE->REG_00H = 0x00008383U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x80980001U; + SCE->REG_00H = 0x0000835fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0800830fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08008007U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x000000e0U; + SCE->REG_E0H = 0x80880001U; + SCE->REG_00H = 0x08008383U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80010020U; + SCE->REG_00H = 0x0800800fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08008307U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x3800a820U; + SCE->REG_ECH = 0x000000bcU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x00003861U; + SCE->REG_ECH = 0x38008c60U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_28H = 0x00870001U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x000000e0U; + SCE->REG_E0H = 0x81880001U; + SCE->REG_00H = 0x00003823U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x00000884U; + for (iLoop = 0; iLoop < 7; iLoop = iLoop + 1) + { + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_00H = 0x00005323U; + SCE->REG_2CH = 0x00000020U; + SCE->REG_74H = 0x00000002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x81010080U; + SCE->REG_00H = 0x00005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000054U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x80000000U); + SCE->REG_F8H = 0x00000040U; + SCE->REG_104H = 0x00000154U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000120U); + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_74H = 0x00000008U; + for (jLoop = 0; jLoop < 2; jLoop = jLoop + 1) + { + SCE->REG_C4H = 0x00040805U; + SCE->REG_00H = 0x00002513U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x00000c85U; + SCE->REG_E0H = 0x81840003U; + SCE->REG_00H = 0x00002813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x80840003U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000a460U; + SCE->REG_ECH = 0x00000010U; + } + SCE->REG_ECH = 0x00002c80U; + } + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x00003861U; + SCE->REG_ECH = 0x00008c60U; + SCE->REG_ECH = 0x7fffffffU; + SCE->REG_ECH = 0x00003c61U; + SCE->REG_ECH = 0x00000821U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x000000deU; + SCE->REG_ECH = 0x00002862U; + for (iLoop = 0; iLoop < 223; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x02003881U; + SCE->REG_ECH = 0x30002823U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x3800a880U; + SCE->REG_ECH = 0x00000001U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x30002823U; + SCE->REG_ECH = 0x00000020U; + SCE->REG_ECH = 0x3800a880U; + SCE->REG_ECH = 0x00000000U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x38000884U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00002c20U; + } + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_00H = 0x0000500bU; + SCE->REG_74H = 0x00000002U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00005323U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00003422U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x000000dfU; + SCE->REG_ECH = 0x00002862U; + R_SCE_func100(0x8205a284U, 0x2faefdf3U, 0x75a6f71fU, 0xc5ad2813U); + SCE->REG_E0H = 0x81010020U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x00003020U; + SCE->REG_ECH = 0x02003883U; + SCE->REG_E0H = 0x81010080U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00002c60U; + R_SCE_func101(0x96a06628U, 0xe99a9100U, 0xf8b5bf5dU, 0x9ba5c681U); + } + SCE->REG_ECH = 0x00007c01U; + SCE->REG_1CH = 0x00602000U; + SCE->REG_ECH = 0x00003462U; + SCE->REG_ECH = 0x00008c60U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00002823U; + SCE->REG_ECH = 0x0000b460U; + SCE->REG_ECH = 0x80000000U; + R_SCE_func100(0x679beab0U, 0x8173e672U, 0xec3c6895U, 0x80fb8b8fU); + SCE->REG_E0H = 0x81010020U; + SCE->REG_04H = 0x00000707U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x00003020U; + SCE->REG_E0H = 0x81010060U; + SCE->REG_00H = 0x08005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x0800080fU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00086c63U; + R_SCE_func101(0xdd1d206aU, 0x1ca8a5f6U, 0x6d73765bU, 0x8f85f3dcU); + } + SCE->REG_ECH = 0x00007c01U; + SCE->REG_1CH = 0x00602000U; + SCE->REG_F8H = 0x00000040U; + SCE->REG_ECH = 0x00000863U; + SCE->REG_ECH = 0x00003482U; + SCE->REG_ECH = 0x0000a480U; + SCE->REG_ECH = 0x00000028U; + SCE->REG_ECH = 0x01836c64U; + SCE->REG_ECH = 0x00036c84U; + SCE->REG_E0H = 0x81020060U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000U; + SCE->REG_ECH = 0x00007c00U; + SCE->REG_1CH = 0x00602000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_subprc03_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc04.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc04.c new file mode 100644 index 0000000000..7cc7f7c632 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc04.c @@ -0,0 +1,312 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce.h" +#include "r_sce_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void R_SCE_TlsGenerateSubSub(void) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_7CH = 0x00000011U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_ECH = 0x0000b5a0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_ECH = 0x0000b5e0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_74H = 0x00000002U; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x0000394dU; + SCE->REG_ECH = 0x00008940U; + SCE->REG_ECH = 0x36363636U; + SCE->REG_E0H = 0x81010140U; + SCE->REG_00H = 0x00005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000025afU; + } + SCE->REG_ECH = 0x00007c0dU; + SCE->REG_1CH = 0x00602000U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + SCE->REG_100H = change_endian_long(0x36363636U); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000035aeU; + SCE->REG_ECH = 0x000269adU; + R_SCE_func100(0xde30fd3bU, 0xa1a421cdU, 0xdb782423U, 0x3d06a9daU); + SCE->REG_E0H = 0x810101a0U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_E0H = 0x8181000bU; + SCE->REG_00H = 0x00005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000a560U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x000031a0U; + R_SCE_func101(0x0fa9b055U, 0xdd060480U, 0x835c7670U, 0x2851f1a5U); + } + SCE->REG_ECH = 0x00007c0dU; + SCE->REG_1CH = 0x00602000U; + SCE->REG_ECH = 0x0000354eU; + SCE->REG_ECH = 0x00008d40U; + SCE->REG_ECH = 0x00000003U; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b5e0U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_ECH = 0x00003decU; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x000039ebU; + SCE->REG_ECH = 0x0000b560U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000296aU; + SCE->REG_ECH = 0x0000354bU; + SCE->REG_ECH = 0x00036d4aU; + SCE->REG_ECH = 0x0000440aU; + SCE->REG_ECH = 0x000075efU; + SCE->REG_ECH = 0x0000b560U; + SCE->REG_ECH = 0x80000000U; + SCE->REG_ECH = 0x01886debU; + SCE->REG_ECH = 0x0000a940U; + SCE->REG_ECH = 0x00000008U; + SCE->REG_ECH = 0x0000440aU; + SCE->REG_ECH = 0x000079efU; + SCE->REG_ECH = 0x00003decU; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x8181000cU; + SCE->REG_00H = 0x00005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000a5c0U; + SCE->REG_ECH = 0x00000040U; + SCE->REG_ECH = 0x00036dceU; + SCE->REG_F8H = 0x00000040U; + SCE->REG_ECH = 0x000009adU; + SCE->REG_E0H = 0x810201a0U; + SCE->REG_00H = 0x0000580bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_28H = 0x00870001U; + SCE->REG_00H = 0x00003523U; + SCE->REG_74H = 0x00000008U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000754U; + SCE->REG_74H = 0x00000004U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667U); + SCE->REG_100H = change_endian_long(0xbb67ae85U); + SCE->REG_100H = change_endian_long(0x3c6ef372U); + SCE->REG_100H = change_endian_long(0xa54ff53aU); + SCE->REG_100H = change_endian_long(0x510e527fU); + SCE->REG_100H = change_endian_long(0x9b05688cU); + SCE->REG_100H = change_endian_long(0x1f83d9abU); + SCE->REG_100H = change_endian_long(0x5be0cd19U); + SCE->REG_ECH = 0x0000b5a0U; + SCE->REG_ECH = 0x00000070U; + SCE->REG_ECH = 0x0000b5e0U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_74H = 0x00000002U; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x0000394dU; + SCE->REG_ECH = 0x00008940U; + SCE->REG_ECH = 0x5c5c5c5cU; + SCE->REG_E0H = 0x81010140U; + SCE->REG_00H = 0x00005807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x000025afU; + } + SCE->REG_ECH = 0x00007c0dU; + SCE->REG_1CH = 0x00602000U; + SCE->REG_104H = 0x00000354U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + SCE->REG_100H = change_endian_long(0x5c5c5c5cU); + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00005323U; + SCE->REG_2CH = 0x00000020U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000754U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x80000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_100H = change_endian_long(0x00000300U); + /* WAIT_LOOP */ + while (0U != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600U; + SCE->REG_74H = 0x00000000U; + SCE->REG_E0H = 0x8088000cU; + SCE->REG_00H = 0x00008523U; + SCE->REG_74H = 0x00000008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + R_SCE_func100(0xf4c92da6U, 0x935fd722U, 0x0b3821fdU, 0x8dc68b00U); + SCE->REG_ECH = 0x00007c01U; + SCE->REG_1CH = 0x00600000U; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic/R_SCE_subprc04_r1.prc +***********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/s_flash2.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/s_flash2.c new file mode 100644 index 0000000000..67346cfa6e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/s_flash2.c @@ -0,0 +1,748 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/********************************************************************************************************************** + * File Name : s_flash2.c + * Version : 1.01 + * Description : Key information file. + *********************************************************************************************************************/ +/********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "r_sce.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global variables + *********************************************************************************************************************/ +uint32_t const S_FLASH2[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0xad78b7ce, 0xf485a034, 0xcb79fe33, 0xde0206f4, + 0xd724cdb7, 0xffc1c3fb, 0x8ec8b097, 0x75147619, + 0x7a747536, 0x9a9f225c, 0x8db851be, 0x332e46eb, + 0x5315ec11, 0xed2d9a01, 0x785e1417, 0x710be082, + 0x9bd5cfc4, 0x803958d8, 0x65371697, 0x9332ece2, + 0xc1fbda82, 0xa39f1f88, 0xe3c70320, 0x7b3eb514, + 0xc246e4dd, 0xb98512cc, 0x077290a0, 0x852dff73, + 0x79edda48, 0xad95daf3, 0x135207b4, 0xa559c171, + 0xe4427203, 0x04a673d8, 0xc953eabc, 0xdb54226b, + 0x2a152052, 0xde86f990, 0x715aa1c2, 0xa42047f5, + 0x8f4e7169, 0x2ff8d793, 0x57280c0f, 0xb9ca5163, + 0xecffa856, 0x827ef6e0, 0x5f424cf3, 0xddd4f654, + 0xd7682af1, 0x89f5525a, 0x0925501d, 0x29e94fe2, + 0x19be4b41, 0xbf761fab, 0x8e3013bd, 0xa1a97207, + 0x1432d5d4, 0x8637f40e, 0x59f8bdbe, 0xa68b9ee0, + 0x67ed60c6, 0x54ee5b4b, 0x7bdf9c18, 0x623561a9, + 0xee881a24, 0x0fe13417, 0xecabc9d7, 0x07b0f6cd, + 0x9d2fb554, 0xea830811, 0x60bbf204, 0x532e919e, + 0xd79072e2, 0x60e5c587, 0x092271ec, 0x72fab7b6, + 0x4e00ad87, 0xd49a737c, 0xcb4e2e8f, 0xf0974963, + 0xf9bc9a4a, 0x482c13b3, 0xf61580b3, 0x99aa1a84, + 0x51149b14, 0x0ca6bab4, 0xc834df5b, 0xe55a08c3, + 0x5f4f5997, 0x94fc624b, 0x5d090f02, 0x01313fa9, + 0x4c1331ee, 0x47c531ee, 0x5b55f12e, 0x45512449, + 0x4552105f, 0x31238514, 0x3081a3d4, 0x2471f8d4, + 0xcf8bd178, 0xf289fc71, 0x1d01c385, 0x3c9bd983, + 0x2236584e, 0xd24fa393, 0x3f013ab2, 0x2401202b, + 0x44f04f3f, 0x2c1731b8, 0x9735437c, 0x523294d9, + 0x6673c3b4, 0xc5f333fa, 0x7e74296d, 0x2b77f78b, + 0x8ad5533d, 0xd2a323a7, 0xa7565c0a, 0x50887e94, + 0x4c3c7a7e, 0xe69e848a, 0xfc0aabe1, 0x1ee10b86, + 0x5a543d6a, 0x0ea7ec9a, 0xec62a28e, 0x9a8e19c8, + 0xd693dfc4, 0x617e2298, 0x9312d81e, 0x16377a11, + 0x99fee12f, 0xd61b5bb5, 0xe4ba72c2, 0x88ef6b51, + 0x92f8a700, 0xf7e72b1f, 0x36405e75, 0x77a1251f, + 0xfdef1161, 0xc96c84d3, 0x39718323, 0x8bcee018, + 0x39dd415c, 0x95565903, 0x5f98893f, 0xf2a1f6e1, + 0x301e8b7b, 0xc3f584a5, 0xa640dfb9, 0x9bec650b, + 0x55bd6a31, 0x71348032, 0xdc4aa649, 0xeac3f267, + 0x8ea986e4, 0x415b9fc6, 0x5452a145, 0xcb7ea535, + 0x79c53d53, 0x15f2f3ed, 0x1eb1bae9, 0xc955735d, + 0x062925b6, 0x6cdcf074, 0x4783ad93, 0x2aa83a2b, + 0xd13efca5, 0xb1a88d5c, 0xc13557de, 0x7236deb5, + 0x9b710768, 0x2fe5c387, 0xa023a059, 0x53a6dad1, + 0xe92fa9fb, 0x64ecb595, 0x670dc6f7, 0x078ff273, + 0xca4df9c3, 0x752cc089, 0x164117f6, 0x8f367e18, + 0xff07e9a6, 0xf05017cd, 0xa8fd9094, 0x117657fe, + 0x7732e086, 0xf53acf4d, 0x66b122cd, 0xe06ff062, + 0xce16bf08, 0xe239afbb, 0xce19cee7, 0xb1a1a1e4, + 0x9760e317, 0x691933ac, 0x3ff47837, 0x37a98542, + 0x82dd3a4c, 0x8d33b9fe, 0x66383758, 0xba254288, + 0x3073bc2c, 0x0bc7ef02, 0xeb8980a0, 0x89d73944, + 0x4d1998ce, 0xc6a84435, 0xdfeae1a8, 0xb7cea4d8, + 0xe48a7dca, 0x6d2e4833, 0x0bc61d21, 0x6406ba72, + 0xbcfb3740, 0x284f77da, 0xeeda9f19, 0x4013584d, + 0xae77def9, 0xb52ed4d1, 0xea53840e, 0xc58c1c93, + 0x57caa4ef, 0xf49815f6, 0x39de04df, 0xee3e82cd, + 0x94fa315f, 0x9089f7f6, 0x8c148c62, 0xaea86eb9, + 0xee4d92a1, 0x53e22273, 0x320a1a49, 0x6062458c, + 0x83f899dd, 0x130cd15d, 0x2254b89a, 0xb47adbde, + 0xb00fa169, 0x79e37a18, 0x2e83b3d0, 0x52a50351, + 0x88d45f8d, 0x26e83c7e, 0xe31d675a, 0xa86ee007, + 0x9a6df643, 0x31c6fb04, 0x6abb3f42, 0xbd6d955d, + 0x8c5fbcc3, 0x6c343ccb, 0x61e18836, 0xc279bad9, + 0xa12ae050, 0x4794b96f, 0x20a151e8, 0x2b7cee93, + 0xfea27c67, 0x362554bc, 0x8cf0b632, 0x9449694d, + 0xe9eb3752, 0x4dfbb874, 0x96ee12e7, 0xcc0bab5b, + 0x1d1d454e, 0x0346a061, 0xa06707ae, 0xbdb76aa4, + 0x45e15add, 0x2bf3fe1c, 0xfaaaffac, 0xee5b079d, + 0x49a3f4b3, 0xc3f5a0d2, 0x8363720f, 0xb35da70b, + 0xd06c0ad3, 0x8a83b325, 0x0c6f419d, 0xb8ad75f7, + 0x85f8211c, 0x0e9aa552, 0xdb4eea0a, 0xf3a81af9, + 0xcdd0a2be, 0x1678793d, 0xf15a4107, 0xd4a0cf7b, + 0x6940f0d4, 0x020549a6, 0x6372983d, 0xb8d3f734, + 0x694ff9a7, 0xefa49bdf, 0x42831ff8, 0x27a0c27c, + 0xcedf518d, 0xeedb44f4, 0xc7a724de, 0x4a52d583, + 0x43eb80f5, 0x5ca362a6, 0xb13fd822, 0xfbe540a2, + 0xdc785c16, 0xcb58458a, 0x74cf432d, 0x967c6b61, + 0x62167c74, 0xaa40d95f, 0x0ca80521, 0x1feb9633, + 0xa0b968ab, 0xfba2b2db, 0xb74cbf74, 0x2d8a21ff, + 0xe3a80f4f, 0x90fea7fe, 0x73d0828c, 0x85b97cfc, + 0xae6d737b, 0x8c76de29, 0x34c4b173, 0x04c04e21, + 0xc4005344, 0x39691984, 0x039bf0ce, 0x697fce5b, + 0x0d0ed2b6, 0xce6b8ac6, 0x5a32f56c, 0x43c35359, + 0x5b3803f0, 0x6b97a563, 0x650b708d, 0xb275f0d2, + 0x21447967, 0x8890ca7e, 0xf64dcfae, 0xe6581cb8, + 0x5b7c4163, 0x8de977ba, 0x824e2654, 0xe36811e7, + 0x2cc2625f, 0xad9f4ad5, 0x202feb20, 0xcd85413b, + 0xc9190d84, 0x3ed08b6a, 0x506d4a1f, 0xa2a1e8d7, + 0xc70c01f1, 0xd3b8ddcf, 0xce141c89, 0xa19b31fa, + 0xf1b37042, 0x7e5cb4c5, 0x0a2088c9, 0x207c3366, + 0x705c1a48, 0x05352a16, 0xf2236556, 0x061b4e2f, + 0xf7be8a2e, 0x20bc58ed, 0x4ea6a298, 0x2489282e, + 0x50c9aa2c, 0x00791346, 0xaec86312, 0x24f8f2cd, + 0x187678a6, 0x90045d55, 0x07c3277a, 0xa47ff698, + 0x29cc0f62, 0x0103f887, 0x341fa96d, 0x86d54d2c, + 0xf31712d8, 0x00a33b7d, 0x2c43b2f8, 0xf3ac68af, + 0x27785c02, 0x0b1fc86c, 0x06119876, 0x3707c3ce, + 0xcad84f69, 0x3a5ef643, 0x8464b479, 0x4439b78f, + 0x1727d533, 0x81a383b5, 0x1b92975c, 0x5006a634, + 0xb8f0e0b2, 0x4e6d7415, 0x13590f5e, 0x4414d3f7, + 0xc4f1f111, 0xb9dc6d5d, 0xdd544f92, 0xf14de9a6, + 0xa626265c, 0x1e07e4b6, 0x655033c6, 0x56a425d1, + 0x3c102773, 0x31641587, 0x35be4499, 0x6e7bcbad, + 0x073d1c86, 0xdd0c786d, 0x0871ab1b, 0x805af125, + 0x3ec11642, 0xdbb154e8, 0xa866d423, 0x26f1e26d, + 0x6228f64e, 0x80217ade, 0xf966b1ed, 0x4a664d5b, + 0xce50a089, 0xe71a0846, 0x6bb935d2, 0xa2838885, + 0xce6a9ca9, 0x14d09b86, 0xeff642e0, 0x3446f4e3, + 0x8efc125e, 0x6c18ba57, 0x32c27f0b, 0x4a7d9b9e, + 0x75a08670, 0xae0f3372, 0x9655ae09, 0x017c9312, + 0x3836eeba, 0xa4169358, 0xba319d22, 0x055b6ce4, + 0xe706d8d9, 0xf4160e72, 0x99a30673, 0x9a99f174, + 0x85ab677c, 0xcb76bfec, 0x54bd20ba, 0x66b58ca3, + 0xf2a6609e, 0x0e40e3fb, 0xf18e1d75, 0x3db67a96, + 0xd7561e85, 0x8d07c345, 0x0440e605, 0xf7e551f6, + 0x38d9dc21, 0xfc6fcc63, 0x1b4e95df, 0xfeff7756, + 0x04b6eceb, 0xadead1d6, 0xfd67d45e, 0xa1b1d273, + 0xc508c6a7, 0xe5d582db, 0x527fabee, 0x4bea7a44, + 0x471063cd, 0xbb8c0f82, 0xb8e8d98f, 0xfc246cc6, + 0xca417726, 0xb2f63429, 0xcd408eb3, 0x26e5f88a, + 0x57a1f600, 0x21154b8c, 0xba77816a, 0xe9f6f447, + 0xec18caaa, 0x4c37bcff, 0x4854e740, 0x7173da47, + 0xb18f1c0b, 0xd5d2e739, 0xb5cce51a, 0x7da4de1f, + 0x2073cbe8, 0x37c2c87d, 0x3063058a, 0x468a7f18, + 0x7323419e, 0x8e1a8186, 0x49a92e14, 0xf67dee26, + 0xbc9c1a64, 0xa8c7aef1, 0x556ca70e, 0xb8fc261e, + 0xeb40656c, 0xd4c84476, 0x38433e0b, 0x13792038, + 0xf5c20c0e, 0x7000a994, 0x52b36412, 0x9b4e4d14, + 0xc8916c36, 0x793b6a21, 0xe46ee83a, 0x0416a9da, + 0x1fb8ac7d, 0x5c9922da, 0xaf5ae1e1, 0xe55ee839, + 0xdbd1c7ff, 0x18b52cea, 0xad61d711, 0x20769f0a, + 0x19d2b4ab, 0x1dd6272b, 0x97b37865, 0x9d56c45d, + 0xdbe6183b, 0x6bf759a6, 0x836bd3e3, 0x0410083c, + 0xc27555c1, 0x27f6bd7a, 0xd75b2ddb, 0x41ee4c81, + 0xa198ccbb, 0xff399a8e, 0x8b87e36b, 0x788e6f1a, + 0x6a0ed92c, 0x8be87eda, 0x423e7e3b, 0x2766ea9e, + 0xcdef7371, 0x32e22a57, 0x8f079b53, 0xc801c87c, + 0x5d73565f, 0xe523bfd0, 0x11cdb2df, 0x24d65f2e, + 0x8b3c28d2, 0x0583181c, 0x32ba110b, 0x917d557e, + 0x93a7d01b, 0xbc91da09, 0x83ffe873, 0x3bb39f2e, + 0xe26093e9, 0xe160e16d, 0x5ed67962, 0x2df8719c, + 0x2c1ef993, 0x90c41821, 0x25ce335c, 0x39912698, + 0x8f5df038, 0x976f324c, 0xde5afbb9, 0x7453ac8f, + 0x8877ec75, 0x0a3687b2, 0x019adaec, 0x542930f7, + 0x017e5e03, 0x7414500d, 0x192aaf58, 0x7bc0ed61, + 0x6b650d47, 0x9c8ebe21, 0xe7970cb4, 0x87db9ef2, + 0x09eb26fe, 0xe64243c2, 0xdf062583, 0xb2563e12, + 0x0a2532e7, 0xfbf631b1, 0x104e6c3c, 0x3c5e63a3, + 0xd463e061, 0xf2ef1d35, 0x684f64e2, 0x839a2da7, + 0x84d28ca5, 0xe3ec7dae, 0xeb7a75a5, 0x3ac14923, + 0x4040f5bf, 0x140e2a37, 0xbdf017af, 0x9ecdbaa2, + 0x505f4ed4, 0x99f163d4, 0x6f4fa78c, 0xb52db623, + 0x1ac48739, 0x0a86fc18, 0xd00ff2b9, 0xe2036f93, + 0xeeeb068e, 0x917779a9, 0xcf4688e5, 0x52264c45, + 0x16bdcc49, 0x5b6c1a5d, 0x67b53024, 0x4a5b67a3, + 0x84f24183, 0x0ec06dfd, 0x6e4b3751, 0x483cc294, + 0xfa14dcd6, 0x4e234ff1, 0x0fed8f86, 0xf59271da, + 0x529c56f2, 0xbbebeac3, 0x0f77f16e, 0x0dca89fb, + 0xc6ff4eeb, 0x5e09896c, 0x451d9e36, 0xf94dc1b9, + 0xc7da035f, 0xe5a3e3e5, 0x7b8346c0, 0x8e23cb38, + 0x4c6b24ba, 0x6bbec422, 0xfeeb33b5, 0x09b2425f, + 0x413b39c7, 0xad9136a0, 0x92e7f60d, 0x1f3a0df4, + 0x08d2778e, 0x3067de6a, 0x098d4bcb, 0x10625f9d, + 0x64abac10, 0xb2830643, 0x94e9969d, 0x4fdd4d0d, + 0xa81cf5e5, 0x42a47c77, 0x8f3c1e69, 0xe46160bc, + 0xee399b53, 0x6a0c080e, 0x769d77ed, 0xbc9ccf9a, + 0xef007244, 0x6f8b2f06, 0x454d1666, 0xadeb361f, + 0xa1382a16, 0xd0181a2e, 0x7a72ba9f, 0xa1af160a, + 0x62b7ab48, 0x89748586, 0x30be6312, 0x517f468f, + 0xf2668d4b, 0x53cb3ad7, 0xca1fc9b2, 0xab52352c, + 0xf37c7bdb, 0x9d727d00, 0xe5f61ed5, 0x5f42361b, + 0x87434502, 0x41e3102e, 0x2ee03064, 0xd2b2ff6e, + 0x718a0e01, 0x0d6a32d2, 0x23753c2a, 0x17ce213e, + 0x67ec2873, 0x2f043590, 0x9ce3f47f, 0x94bdf807, + 0xe7c34a2e, 0xac6a9525, 0xc96a0e6c, 0xb9571ebf, + 0xc3d75569, 0xbb3d469d, 0x47568330, 0x0f1d97b1, + 0xe6e096dd, 0xb235560b, 0x02aa2212, 0x3c2f8ee5, + 0x605dd867, 0x04761613, 0xbfc51805, 0x0d6ff887, + 0xf31457fb, 0x53a277aa, 0x94d53086, 0xb973b7e3, + 0x82844baa, 0xb49a8934, 0xe38631f2, 0x57eafd13, + 0xae1f298e, 0x591f5ae4, 0x4d5c2754, 0x2055f9ad, + 0xda6d1d53, 0x5428245a, 0x133df432, 0x99e18dd3, + 0xf566ed22, 0x6959e3f2, 0x393f42a5, 0xf77c2430, + 0x2cb8ce85, 0x55c7d5bc, 0x9eb79021, 0x8068d650, + 0xd8bfb406, 0x43a7e773, 0xdca584b9, 0x97166d46, + 0xbee94513, 0xbb932e5b, 0xd5cb562b, 0xbf7537e6, + 0x11035ec9, 0xec66d5e8, 0xc10c49b5, 0x859ca138, + 0x62d925e5, 0x5294d361, 0xc19057a6, 0xab2dbc63, + 0x64e5434d, 0x6364a2e8, 0x362ae565, 0x3524ed35, + 0x2b27d97e, 0xd9306b26, 0xbccff4ae, 0x66875ce5, + 0x1d90119d, 0x7a35af65, 0x7d8455cf, 0x8d37e43a, + 0x9dc3af95, 0xa3c19115, 0xead12535, 0xf12d7507, + 0xdd178ed2, 0xdec73bfe, 0x85fba2e6, 0x39568c8b, + 0x8fc1a449, 0x2cf1d471, 0x9baece78, 0xf36b8e52, + 0x6eca1700, 0x58f51ef8, 0x33ab7a99, 0x9fbf7225, + 0x259c7276, 0x150b5987, 0x75a98c0d, 0xb2b52445, + 0xc54233c0, 0x7dbb5474, 0x37efa2ae, 0x638fe8f1, + 0xb30c509c, 0x043c5cdf, 0x44d042a4, 0xec33ca06, + 0x406dbc04, 0x80318f7f, 0x4b26002a, 0x4dd523a3, + 0x0dc16862, 0x2b790de3, 0x42e0de46, 0x072f3919, + 0x03517e7f, 0x02c7aa48, 0x3067ee94, 0x5ffefbb3, + 0x7617ef70, 0x2b63ad83, 0x5426902f, 0x3d78b187, + 0xe3460d3f, 0x1d5453bc, 0x7cbc37aa, 0xf49dd33f, + 0x8ec83672, 0x9784c880, 0x8e095378, 0x77998bb0, + 0x741cfcad, 0x97707a64, 0xdf2a3d5c, 0x0160da53, + 0x134fe8bb, 0xff2c52a6, 0xb0388e2e, 0x8bf4986a, + 0x537c777e, 0x92e690d4, 0xd8649ee9, 0x9534e260, + 0xbb2bf1bd, 0x0d7cf870, 0xe5838c51, 0x826abd18, + 0x566b90e1, 0x2795531b, 0x9243b4b0, 0x26f3bc1e, + 0x4d543eb4, 0xb153c05a, 0x09b68083, 0xf007c6ae, + 0x67a1cd5e, 0xfc56b513, 0x0d365369, 0x6d3b5c2c, + 0xade5ec6a, 0x80045fcf, 0x4da66d69, 0x06894d5b, + 0x0ed1cb94, 0xb06b7cf1, 0x62d0ee57, 0x9d592242, + 0x62678e5c, 0x55d5dc9e, 0x41fed9a9, 0x01eed9e2, + 0x80e0e1af, 0x4cc2d1d8, 0xfe31b4f9, 0xabfb5428, + 0xa401aad7, 0x4db199c1, 0xecd0a771, 0x617a6a96, + 0xd767b885, 0x032b6e8e, 0x942e638e, 0x2cddd5db, + 0xb4eef740, 0x05fa1e17, 0xd0c87adc, 0x921aa8ea, + 0x6ce2c256, 0x22c54b08, 0x815b07f7, 0xc9f13170, + 0x721783dc, 0x115b4392, 0x8eafd75b, 0x91a1cda3, + 0x0dbdb102, 0xccd6c9c6, 0x70c9403c, 0xa69fd812, + 0x316187a2, 0x43308b58, 0x49b563a3, 0xc8869daf, + 0xe66d0ebe, 0x7a168b7d, 0xb419a3e5, 0x7644caa5, + 0x6d5847ca, 0xfb07974d, 0xa7dbf662, 0xe5c52a8a, + 0x526f76ab, 0xf506c5c2, 0xf5655c05, 0xb6a6ff7f, + 0x3c7e73e9, 0x79e3d89f, 0x00822b07, 0xf5f92875, + 0x4110dda7, 0xcf5f4c36, 0x60ac4580, 0xcf4b5421, + 0x18e88d0f, 0x8a0904b4, 0x754e8a45, 0x41eaef0a, + 0xf4b50e33, 0x15f8480d, 0xba006b1c, 0x5d9ec804, + 0x376dff2d, 0xa5434ccf, 0xf7528fb3, 0xd5932e03, + 0x0c5cdde3, 0x16ab47c8, 0x1e765717, 0xba7fc2da, + 0x721bf153, 0xef53dd81, 0x5d79ee44, 0xe261b422, + 0x0390dd78, 0xb4aa77e6, 0xf3bc8dee, 0x61a6b960, + 0x5b6005ff, 0x2dc3cae8, 0xffea8090, 0xa23bc5ae, + 0xcbd3758c, 0x82c99c15, 0xb52f0ebd, 0xe969cda9, + 0x56268ad3, 0x3670da61, 0x7b6cde3f, 0xa6da4504, + 0xbcacccc8, 0x7af23a70, 0x728dab94, 0x85f110f9, + 0x4ee9f86a, 0x475f7e8c, 0xd36d3bc8, 0x3b581db2, + 0x376ca887, 0xc50ed90b, 0xc0f71fe9, 0xa4dee98f, + 0x57828808, 0xb1384311, 0x53bfab22, 0xb1aaa36a, + 0x270f0aec, 0x3d107e75, 0xb167a511, 0xdf640078, + 0xf63b98e7, 0xcc6c6893, 0x369667c2, 0xa9cfd952, + 0x16b937e7, 0x04adb37b, 0xd674ec6f, 0xadc5aa0d, + 0xf04ba0ff, 0x88d300e9, 0xb3038196, 0x5c3060c3, + 0x45892304, 0x672cb274, 0x972199aa, 0xe6a9bb18, + 0xb79ab2fa, 0x37223e41, 0xfc82a4ff, 0xdc0acceb, + 0xa809d1be, 0xd6110ec0, 0xb6f01ba8, 0x8d829cf6, + 0x5e49844d, 0xca0075a5, 0x35d5a4b8, 0xc06c7e11, + 0xe688c9b3, 0x0acf49eb, 0x42a5f8f0, 0x704e0479, + 0x4dc6fc87, 0x2ac4d4b2, 0x5da5213e, 0x38798d90, + 0xeb48dc66, 0x49525830, 0x1a0f35dc, 0xb887ce89, + 0x6a2db320, 0xb5e290bb, 0x945ef0eb, 0xb19277da, + 0x51e4cac8, 0x3c61c05f, 0x2c3a1a03, 0x955642bc, + 0x968c18b4, 0x687d6e9b, 0x8fc33c5a, 0x78464a1b, + 0x3b3cee58, 0x000d6946, 0xa2cbab20, 0x7104a36d, + 0x5099e49e, 0xf14a2223, 0x58325291, 0xf1fc50c2, + 0xea594db1, 0x42522deb, 0xa4f974f5, 0xd67a54c0, + 0x6746450a, 0x0550cffa, 0x31cdddae, 0x181ee273, + 0xb26e8ab3, 0x773b3f12, 0x03ec9bdd, 0x08edf6e3, + 0x6a8b3677, 0x83f41f37, 0xac569f85, 0x32d55f87, + 0xd3be6a9e, 0x7cc27593, 0x1b46185f, 0x5bf35f74, + 0xdb4741ad, 0x51a7e06a, 0x7b7c54c0, 0x6377312b, + 0x2c2dd650, 0xc7ad211f, 0x5882527c, 0x0f95ef48, + 0x02e4af0e, 0xd9f53012, 0xabb93fb2, 0xee5ed3bd, + 0x66f1506d, 0xcf9166b8, 0x47bd54cb, 0x579b6a54, + 0xc07a04d2, 0xaf8c09eb, 0xb41011bc, 0x2258e0ed, + 0x61abf396, 0xad9cab5e, 0x0a2c18a2, 0x09412ef0, + 0xa37ad2d8, 0xf861863c, 0x3e6a51d5, 0x41f34b4f, + 0xbf023a6b, 0xf463c7f6, 0x8688b684, 0x0fc37237, + 0x0c215d46, 0x359a9ecd, 0xf3a403b2, 0xadeeb7d5, + 0x5890465c, 0x42a69fe7, 0xac624b62, 0x8b8bb173, + 0xf1657e63, 0xc3c7e5fa, 0x4d4ee3df, 0x8831e396, + 0x05ec4e6d, 0x6be7f36a, 0x34b02899, 0x1362af8d, + 0x3c07bda4, 0x6fab3d4c, 0xc44f95f8, 0x6d147101, + 0x3b7fef86, 0x8fbd05aa, 0xf5e01b97, 0xc0e296e5, + 0xea832026, 0x92700bdf, 0x1a5d1b4d, 0xb01ea0ba, + 0x856a7c9a, 0xf6f19e2b, 0x6848cd8f, 0xb0573d7c, + 0xc651fdd9, 0xca780370, 0xa8ed392d, 0x22026ddb, + 0x5bfdb3fc, 0xfddee7ac, 0x8bd364f5, 0x453e8461, + 0xbc687ebd, 0xba3666a4, 0x3e2e8327, 0x94124360, + 0xa05b150e, 0x75643ddb, 0x3086fdd6, 0xa6b4b7a2, + 0xb5194151, 0x4e7f6d86, 0xd5a8a31a, 0x057a6561, + 0x32c83190, 0x999168c3, 0x59d3eafe, 0x6e248352, + 0x4c17916b, 0xec0266d9, 0x3934c9b7, 0x5c83e546, + 0x4ba27f28, 0xf0ebbab5, 0xfa7c4ca7, 0x63347956, + 0x31cbf261, 0xb3594cee, 0x06dfcc14, 0x963a7a4d, + 0xdf95b26d, 0x58a7498b, 0x7aee7d3b, 0x33571a2f, + 0x52dd80b8, 0xe8955985, 0xbed140a7, 0xf2fe7527, + 0x7ed1a883, 0xf66ec1e1, 0x3cbaca54, 0x5a258d0e, + 0x46235bb1, 0x8beedba3, 0x55db81e2, 0xb3ce5e61, + 0xefce6dae, 0x9f81d49a, 0x91cfabd3, 0x56597a09, + 0xc9bd5434, 0x54081084, 0xa791ac58, 0x189c4c29, + 0xc9b32fea, 0xbbbf9c57, 0x657fd931, 0xc96b0719, + 0x65f1ec81, 0xbdaa21e0, 0x882fc032, 0x5b05da67, + 0x577868d8, 0x5c1f91f3, 0x09e136f6, 0xacd3ad00, + 0xba32702a, 0xbb8b6aef, 0xf29fccde, 0x1bcfd9a5, + 0xd15b1af4, 0xdf5e1004, 0x0dc88c1e, 0xd66cada7, + 0x28cadec9, 0xf1eafe0d, 0xd791d9ff, 0x08d42687, + 0x3d167403, 0x3a3e84e0, 0x6ee427e7, 0xba4e9824, + 0x576ff3c2, 0x5af749f0, 0xe4984a6c, 0x79f9ed22, + 0xfbe9e2b9, 0x8955b116, 0xb8007b8e, 0x04fddc93, + 0x9760385f, 0xb3561117, 0x5cfa9176, 0xb9652c4e, + 0xe9a16941, 0x35c0431a, 0x5c93ec85, 0xc6229a6e, + 0x91a5455c, 0x12246a5b, 0x418a4d90, 0xfd6ecdbc, + 0x855f6731, 0xeea8b82f, 0xc408d702, 0x12d37de6, + 0xbad36dbe, 0x265f821e, 0x2643771c, 0x2eaaee32, + 0xdaed9b58, 0x20a70137, 0x29af4613, 0x54cb80eb, + 0xac5e9c36, 0xf4708d5a, 0xc139d828, 0x604b2bb6, + 0xb188a825, 0x6c3b3bbd, 0xd3d7106d, 0x1ef37d9d, + 0xfc1becdf, 0x4a98a9ac, 0xac080fef, 0xe1ba9ee5, + 0x0025a248, 0x7da83ae2, 0xc476f3a2, 0xa4df02a0, + 0x7ec40699, 0xabb61727, 0x7a71dc76, 0x30d9969b, + 0xf2aa88f4, 0x57e37476, 0x48806278, 0x91f224eb, + 0x2865417a, 0x87cefef8, 0x2d373407, 0xd6ab05a4, + 0x4fc32de6, 0xbeef8739, 0xd88310b2, 0xa220afbf, + 0x66b0f668, 0xb2a2719d, 0xc0fe9c5e, 0xbde8b9bd, + 0xa877a290, 0x54355f17, 0xf19fb70a, 0x95c686f6, + 0x37c1f8d9, 0xa504aad7, 0xfe0c661f, 0xab47da0a, + 0x9b7b830f, 0xf60da290, 0xd777f871, 0x39fa0de6, + 0x5a0a8904, 0x25d9406a, 0xd5d63a68, 0x8897c0d8, + 0x0bc7c81b, 0x5c985ba8, 0x32e20e7b, 0xfd916425, + 0x0fd5082a, 0x16407eed, 0xa92f7791, 0x76a875dd, + 0x29c7efb6, 0xfebda3fe, 0x844e232f, 0xe6761ce3, + 0x22253ef3, 0xb5079bfe, 0xd4a04ac0, 0xe76d1f2a, + 0x7ce73530, 0xb247eb66, 0x899c404d, 0xee87825c, + 0x78980343, 0x16346878, 0xb895388d, 0x6ac7c031, + 0x76908e23, 0x103a995f, 0x0add4443, 0x9672bc36, + 0x2eb2b525, 0xebcff9cf, 0x9bcdea28, 0xd3abc08c, + 0x98cb3b8c, 0xfcebb335, 0x2a0c0bc1, 0x53f37e12, + 0x7bba0bd7, 0xbcbb3531, 0x1998d0b1, 0xd2a9e818, + 0xd39ee1ee, 0xb19276b7, 0x529cf200, 0x228ad4a9, + 0xf6ae580b, 0x4217eceb, 0x8bc0257c, 0xd9ff3e73, + 0x372a88c3, 0xb94cc100, 0xcc5b18bb, 0x15e613a7, + 0x7862041e, 0xb2a2f6ed, 0xcc0b9dec, 0x1011c965, + 0x8efd57b9, 0xca18dafd, 0xc1b66321, 0x3b9d7b37, + 0xe9b3c769, 0x49c8fb85, 0xa1fe1f2b, 0xf7b351b4, + 0xef655e43, 0x5dc14b65, 0x376b283b, 0x7b43e360, + 0xd34e1464, 0x4d864c45, 0xd9281dd0, 0xfb01cebc, + 0x44aa42e5, 0xf085000a, 0xca56b3d1, 0xd6dc961e, + 0xa215886f, 0x46cafa03, 0x0c7bafc8, 0xb39177fa, + 0xba084749, 0x58dfcb08, 0x6f7f0c91, 0xa5ba86f8, + 0x61e82a0c, 0xb7365259, 0x9f05977e, 0xa825ccca, + 0x8bb72d1f, 0x9ef507ac, 0xcf3efdd6, 0x66b9f77d, + 0x337ec357, 0x69bd52ea, 0xb6915240, 0x1738280e, + 0xb0c1a8ee, 0x544f1b72, 0x610212dd, 0x78672dea, + 0xc9900261, 0xd58deda2, 0xaa95f866, 0x027a6ad2, + 0xd9608a3a, 0xc8f56bd9, 0x5c190a07, 0x57856e18, + 0xabb9a3f9, 0xaecfdff7, 0xd73632a3, 0x7c044fc3, + 0x458a4f30, 0x6d254e42, 0xd314e3ac, 0x534df8bc, + 0x05052b27, 0x68ea7326, 0xc9d5fdce, 0x7f73ebe0, + 0x6d0165fd, 0xaee2f3aa, 0x0108c342, 0xb6836226, + 0xf2bf35e0, 0xf6ac4171, 0xf14a5a0f, 0xca50912a, +#else /* Big endian */ + 0xceb778ad, 0x34a085f4, 0x33fe79cb, 0xf40602de, + 0xb7cd24d7, 0xfbc3c1ff, 0x97b0c88e, 0x19761475, + 0x3675747a, 0x5c229f9a, 0xbe51b88d, 0xeb462e33, + 0x11ec1553, 0x019a2ded, 0x17145e78, 0x82e00b71, + 0xc4cfd59b, 0xd8583980, 0x97163765, 0xe2ec3293, + 0x82dafbc1, 0x881f9fa3, 0x2003c7e3, 0x14b53e7b, + 0xdde446c2, 0xcc1285b9, 0xa0907207, 0x73ff2d85, + 0x48daed79, 0xf3da95ad, 0xb4075213, 0x71c159a5, + 0x037242e4, 0xd873a604, 0xbcea53c9, 0x6b2254db, + 0x5220152a, 0x90f986de, 0xc2a15a71, 0xf54720a4, + 0x69714e8f, 0x93d7f82f, 0x0f0c2857, 0x6351cab9, + 0x56a8ffec, 0xe0f67e82, 0xf34c425f, 0x54f6d4dd, + 0xf12a68d7, 0x5a52f589, 0x1d502509, 0xe24fe929, + 0x414bbe19, 0xab1f76bf, 0xbd13308e, 0x0772a9a1, + 0xd4d53214, 0x0ef43786, 0xbebdf859, 0xe09e8ba6, + 0xc660ed67, 0x4b5bee54, 0x189cdf7b, 0xa9613562, + 0x241a88ee, 0x1734e10f, 0xd7c9abec, 0xcdf6b007, + 0x54b52f9d, 0x110883ea, 0x04f2bb60, 0x9e912e53, + 0xe27290d7, 0x87c5e560, 0xec712209, 0xb6b7fa72, + 0x87ad004e, 0x7c739ad4, 0x8f2e4ecb, 0x634997f0, + 0x4a9abcf9, 0xb3132c48, 0xb38015f6, 0x841aaa99, + 0x149b1451, 0xb4baa60c, 0x5bdf34c8, 0xc3085ae5, + 0x97594f5f, 0x4b62fc94, 0x020f095d, 0xa93f3101, + 0xee31134c, 0xee31c547, 0x2ef1555b, 0x49245145, + 0x5f105245, 0x14852331, 0xd4a38130, 0xd4f87124, + 0x78d18bcf, 0x71fc89f2, 0x85c3011d, 0x83d99b3c, + 0x4e583622, 0x93a34fd2, 0xb23a013f, 0x2b200124, + 0x3f4ff044, 0xb831172c, 0x7c433597, 0xd9943252, + 0xb4c37366, 0xfa33f3c5, 0x6d29747e, 0x8bf7772b, + 0x3d53d58a, 0xa723a3d2, 0x0a5c56a7, 0x947e8850, + 0x7e7a3c4c, 0x8a849ee6, 0xe1ab0afc, 0x860be11e, + 0x6a3d545a, 0x9aeca70e, 0x8ea262ec, 0xc8198e9a, + 0xc4df93d6, 0x98227e61, 0x1ed81293, 0x117a3716, + 0x2fe1fe99, 0xb55b1bd6, 0xc272bae4, 0x516bef88, + 0x00a7f892, 0x1f2be7f7, 0x755e4036, 0x1f25a177, + 0x6111effd, 0xd3846cc9, 0x23837139, 0x18e0ce8b, + 0x5c41dd39, 0x03595695, 0x3f89985f, 0xe1f6a1f2, + 0x7b8b1e30, 0xa584f5c3, 0xb9df40a6, 0x0b65ec9b, + 0x316abd55, 0x32803471, 0x49a64adc, 0x67f2c3ea, + 0xe486a98e, 0xc69f5b41, 0x45a15254, 0x35a57ecb, + 0x533dc579, 0xedf3f215, 0xe9bab11e, 0x5d7355c9, + 0xb6252906, 0x74f0dc6c, 0x93ad8347, 0x2b3aa82a, + 0xa5fc3ed1, 0x5c8da8b1, 0xde5735c1, 0xb5de3672, + 0x6807719b, 0x87c3e52f, 0x59a023a0, 0xd1daa653, + 0xfba92fe9, 0x95b5ec64, 0xf7c60d67, 0x73f28f07, + 0xc3f94dca, 0x89c02c75, 0xf6174116, 0x187e368f, + 0xa6e907ff, 0xcd1750f0, 0x9490fda8, 0xfe577611, + 0x86e03277, 0x4dcf3af5, 0xcd22b166, 0x62f06fe0, + 0x08bf16ce, 0xbbaf39e2, 0xe7ce19ce, 0xe4a1a1b1, + 0x17e36097, 0xac331969, 0x3778f43f, 0x4285a937, + 0x4c3add82, 0xfeb9338d, 0x58373866, 0x884225ba, + 0x2cbc7330, 0x02efc70b, 0xa08089eb, 0x4439d789, + 0xce98194d, 0x3544a8c6, 0xa8e1eadf, 0xd8a4ceb7, + 0xca7d8ae4, 0x33482e6d, 0x211dc60b, 0x72ba0664, + 0x4037fbbc, 0xda774f28, 0x199fdaee, 0x4d581340, + 0xf9de77ae, 0xd1d42eb5, 0x0e8453ea, 0x931c8cc5, + 0xefa4ca57, 0xf61598f4, 0xdf04de39, 0xcd823eee, + 0x5f31fa94, 0xf6f78990, 0x628c148c, 0xb96ea8ae, + 0xa1924dee, 0x7322e253, 0x491a0a32, 0x8c456260, + 0xdd99f883, 0x5dd10c13, 0x9ab85422, 0xdedb7ab4, + 0x69a10fb0, 0x187ae379, 0xd0b3832e, 0x5103a552, + 0x8d5fd488, 0x7e3ce826, 0x5a671de3, 0x07e06ea8, + 0x43f66d9a, 0x04fbc631, 0x423fbb6a, 0x5d956dbd, + 0xc3bc5f8c, 0xcb3c346c, 0x3688e161, 0xd9ba79c2, + 0x50e02aa1, 0x6fb99447, 0xe851a120, 0x93ee7c2b, + 0x677ca2fe, 0xbc542536, 0x32b6f08c, 0x4d694994, + 0x5237ebe9, 0x74b8fb4d, 0xe712ee96, 0x5bab0bcc, + 0x4e451d1d, 0x61a04603, 0xae0767a0, 0xa46ab7bd, + 0xdd5ae145, 0x1cfef32b, 0xacffaafa, 0x9d075bee, + 0xb3f4a349, 0xd2a0f5c3, 0x0f726383, 0x0ba75db3, + 0xd30a6cd0, 0x25b3838a, 0x9d416f0c, 0xf775adb8, + 0x1c21f885, 0x52a59a0e, 0x0aea4edb, 0xf91aa8f3, + 0xbea2d0cd, 0x3d797816, 0x07415af1, 0x7bcfa0d4, + 0xd4f04069, 0xa6490502, 0x3d987263, 0x34f7d3b8, + 0xa7f94f69, 0xdf9ba4ef, 0xf81f8342, 0x7cc2a027, + 0x8d51dfce, 0xf444dbee, 0xde24a7c7, 0x83d5524a, + 0xf580eb43, 0xa662a35c, 0x22d83fb1, 0xa240e5fb, + 0x165c78dc, 0x8a4558cb, 0x2d43cf74, 0x616b7c96, + 0x747c1662, 0x5fd940aa, 0x2105a80c, 0x3396eb1f, + 0xab68b9a0, 0xdbb2a2fb, 0x74bf4cb7, 0xff218a2d, + 0x4f0fa8e3, 0xfea7fe90, 0x8c82d073, 0xfc7cb985, + 0x7b736dae, 0x29de768c, 0x73b1c434, 0x214ec004, + 0x445300c4, 0x84196939, 0xcef09b03, 0x5bce7f69, + 0xb6d20e0d, 0xc68a6bce, 0x6cf5325a, 0x5953c343, + 0xf003385b, 0x63a5976b, 0x8d700b65, 0xd2f075b2, + 0x67794421, 0x7eca9088, 0xaecf4df6, 0xb81c58e6, + 0x63417c5b, 0xba77e98d, 0x54264e82, 0xe71168e3, + 0x5f62c22c, 0xd54a9fad, 0x20eb2f20, 0x3b4185cd, + 0x840d19c9, 0x6a8bd03e, 0x1f4a6d50, 0xd7e8a1a2, + 0xf1010cc7, 0xcfddb8d3, 0x891c14ce, 0xfa319ba1, + 0x4270b3f1, 0xc5b45c7e, 0xc988200a, 0x66337c20, + 0x481a5c70, 0x162a3505, 0x566523f2, 0x2f4e1b06, + 0x2e8abef7, 0xed58bc20, 0x98a2a64e, 0x2e288924, + 0x2caac950, 0x46137900, 0x1263c8ae, 0xcdf2f824, + 0xa6787618, 0x555d0490, 0x7a27c307, 0x98f67fa4, + 0x620fcc29, 0x87f80301, 0x6da91f34, 0x2c4dd586, + 0xd81217f3, 0x7d3ba300, 0xf8b2432c, 0xaf68acf3, + 0x025c7827, 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0xeb2d5242, 0xf574f9a4, 0xc0547ad6, + 0x0a454667, 0xfacf5005, 0xaeddcd31, 0x73e21e18, + 0xb38a6eb2, 0x123f3b77, 0xdd9bec03, 0xe3f6ed08, + 0x77368b6a, 0x371ff483, 0x859f56ac, 0x875fd532, + 0x9e6abed3, 0x9375c27c, 0x5f18461b, 0x745ff35b, + 0xad4147db, 0x6ae0a751, 0xc0547c7b, 0x2b317763, + 0x50d62d2c, 0x1f21adc7, 0x7c528258, 0x48ef950f, + 0x0eafe402, 0x1230f5d9, 0xb23fb9ab, 0xbdd35eee, + 0x6d50f166, 0xb86691cf, 0xcb54bd47, 0x546a9b57, + 0xd2047ac0, 0xeb098caf, 0xbc1110b4, 0xede05822, + 0x96f3ab61, 0x5eab9cad, 0xa2182c0a, 0xf02e4109, + 0xd8d27aa3, 0x3c8661f8, 0xd5516a3e, 0x4f4bf341, + 0x6b3a02bf, 0xf6c763f4, 0x84b68886, 0x3772c30f, + 0x465d210c, 0xcd9e9a35, 0xb203a4f3, 0xd5b7eead, + 0x5c469058, 0xe79fa642, 0x624b62ac, 0x73b18b8b, + 0x637e65f1, 0xfae5c7c3, 0xdfe34e4d, 0x96e33188, + 0x6d4eec05, 0x6af3e76b, 0x9928b034, 0x8daf6213, + 0xa4bd073c, 0x4c3dab6f, 0xf8954fc4, 0x0171146d, + 0x86ef7f3b, 0xaa05bd8f, 0x971be0f5, 0xe596e2c0, + 0x262083ea, 0xdf0b7092, 0x4d1b5d1a, 0xbaa01eb0, + 0x9a7c6a85, 0x2b9ef1f6, 0x8fcd4868, 0x7c3d57b0, + 0xd9fd51c6, 0x700378ca, 0x2d39eda8, 0xdb6d0222, + 0xfcb3fd5b, 0xace7defd, 0xf564d38b, 0x61843e45, + 0xbd7e68bc, 0xa46636ba, 0x27832e3e, 0x60431294, + 0x0e155ba0, 0xdb3d6475, 0xd6fd8630, 0xa2b7b4a6, + 0x514119b5, 0x866d7f4e, 0x1aa3a8d5, 0x61657a05, + 0x9031c832, 0xc3689199, 0xfeead359, 0x5283246e, + 0x6b91174c, 0xd96602ec, 0xb7c93439, 0x46e5835c, + 0x287fa24b, 0xb5baebf0, 0xa74c7cfa, 0x56793463, + 0x61f2cb31, 0xee4c59b3, 0x14ccdf06, 0x4d7a3a96, + 0x6db295df, 0x8b49a758, 0x3b7dee7a, 0x2f1a5733, + 0xb880dd52, 0x855995e8, 0xa740d1be, 0x2775fef2, + 0x83a8d17e, 0xe1c16ef6, 0x54caba3c, 0x0e8d255a, + 0xb15b2346, 0xa3dbee8b, 0xe281db55, 0x615eceb3, + 0xae6dceef, 0x9ad4819f, 0xd3abcf91, 0x097a5956, + 0x3454bdc9, 0x84100854, 0x58ac91a7, 0x294c9c18, + 0xea2fb3c9, 0x579cbfbb, 0x31d97f65, 0x19076bc9, + 0x81ecf165, 0xe021aabd, 0x32c02f88, 0x67da055b, + 0xd8687857, 0xf3911f5c, 0xf636e109, 0x00add3ac, + 0x2a7032ba, 0xef6a8bbb, 0xdecc9ff2, 0xa5d9cf1b, + 0xf41a5bd1, 0x04105edf, 0x1e8cc80d, 0xa7ad6cd6, + 0xc9deca28, 0x0dfeeaf1, 0xffd991d7, 0x8726d408, + 0x0374163d, 0xe0843e3a, 0xe727e46e, 0x24984eba, + 0xc2f36f57, 0xf049f75a, 0x6c4a98e4, 0x22edf979, + 0xb9e2e9fb, 0x16b15589, 0x8e7b00b8, 0x93dcfd04, + 0x5f386097, 0x171156b3, 0x7691fa5c, 0x4e2c65b9, + 0x4169a1e9, 0x1a43c035, 0x85ec935c, 0x6e9a22c6, + 0x5c45a591, 0x5b6a2412, 0x904d8a41, 0xbccd6efd, + 0x31675f85, 0x2fb8a8ee, 0x02d708c4, 0xe67dd312, + 0xbe6dd3ba, 0x1e825f26, 0x1c774326, 0x32eeaa2e, + 0x589bedda, 0x3701a720, 0x1346af29, 0xeb80cb54, + 0x369c5eac, 0x5a8d70f4, 0x28d839c1, 0xb62b4b60, + 0x25a888b1, 0xbd3b3b6c, 0x6d10d7d3, 0x9d7df31e, + 0xdfec1bfc, 0xaca9984a, 0xef0f08ac, 0xe59ebae1, + 0x48a22500, 0xe23aa87d, 0xa2f376c4, 0xa002dfa4, + 0x9906c47e, 0x2717b6ab, 0x76dc717a, 0x9b96d930, + 0xf488aaf2, 0x7674e357, 0x78628048, 0xeb24f291, + 0x7a416528, 0xf8fece87, 0x0734372d, 0xa405abd6, + 0xe62dc34f, 0x3987efbe, 0xb21083d8, 0xbfaf20a2, + 0x68f6b066, 0x9d71a2b2, 0x5e9cfec0, 0xbdb9e8bd, + 0x90a277a8, 0x175f3554, 0x0ab79ff1, 0xf686c695, + 0xd9f8c137, 0xd7aa04a5, 0x1f660cfe, 0x0ada47ab, + 0x0f837b9b, 0x90a20df6, 0x71f877d7, 0xe60dfa39, + 0x04890a5a, 0x6a40d925, 0x683ad6d5, 0xd8c09788, + 0x1bc8c70b, 0xa85b985c, 0x7b0ee232, 0x256491fd, + 0x2a08d50f, 0xed7e4016, 0x91772fa9, 0xdd75a876, + 0xb6efc729, 0xfea3bdfe, 0x2f234e84, 0xe31c76e6, + 0xf33e2522, 0xfe9b07b5, 0xc04aa0d4, 0x2a1f6de7, + 0x3035e77c, 0x66eb47b2, 0x4d409c89, 0x5c8287ee, + 0x43039878, 0x78683416, 0x8d3895b8, 0x31c0c76a, + 0x238e9076, 0x5f993a10, 0x4344dd0a, 0x36bc7296, + 0x25b5b22e, 0xcff9cfeb, 0x28eacd9b, 0x8cc0abd3, + 0x8c3bcb98, 0x35b3ebfc, 0xc10b0c2a, 0x127ef353, + 0xd70bba7b, 0x3135bbbc, 0xb1d09819, 0x18e8a9d2, + 0xeee19ed3, 0xb77692b1, 0x00f29c52, 0xa9d48a22, + 0x0b58aef6, 0xebec1742, 0x7c25c08b, 0x733effd9, + 0xc3882a37, 0x00c14cb9, 0xbb185bcc, 0xa713e615, + 0x1e046278, 0xedf6a2b2, 0xec9d0bcc, 0x65c91110, + 0xb957fd8e, 0xfdda18ca, 0x2163b6c1, 0x377b9d3b, + 0x69c7b3e9, 0x85fbc849, 0x2b1ffea1, 0xb451b3f7, + 0x435e65ef, 0x654bc15d, 0x3b286b37, 0x60e3437b, + 0x64144ed3, 0x454c864d, 0xd01d28d9, 0xbcce01fb, + 0xe542aa44, 0x0a0085f0, 0xd1b356ca, 0x1e96dcd6, + 0x6f8815a2, 0x03faca46, 0xc8af7b0c, 0xfa7791b3, + 0x494708ba, 0x08cbdf58, 0x910c7f6f, 0xf886baa5, + 0x0c2ae861, 0x595236b7, 0x7e97059f, 0xcacc25a8, + 0x1f2db78b, 0xac07f59e, 0xd6fd3ecf, 0x7df7b966, + 0x57c37e33, 0xea52bd69, 0x405291b6, 0x0e283817, + 0xeea8c1b0, 0x721b4f54, 0xdd120261, 0xea2d6778, + 0x610290c9, 0xa2ed8dd5, 0x66f895aa, 0xd26a7a02, + 0x3a8a60d9, 0xd96bf5c8, 0x070a195c, 0x186e8557, + 0xf9a3b9ab, 0xf7dfcfae, 0xa33236d7, 0xc34f047c, + 0x304f8a45, 0x424e256d, 0xace314d3, 0xbcf84d53, + 0x272b0505, 0x2673ea68, 0xcefdd5c9, 0xe0eb737f, + 0xfd65016d, 0xaaf3e2ae, 0x42c30801, 0x266283b6, + 0xe035bff2, 0x7141acf6, 0x0f5a4af1, 0x2a9150ca, +#endif /* defined __ARMEB__ */ +}; + +/********************************************************************************************************************** + Private (static) variables and functions + *********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_ProcCommon.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_ProcCommon.h new file mode 100644 index 0000000000..08a0020e2a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_ProcCommon.h @@ -0,0 +1,4763 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : SCE_ProcCommon.h +* Description : IO definition for FSP SCE +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2018 1.00 First Release. +***********************************************************************************************************************/ +#ifndef HW_SCE_E017_H +#define HW_SCE_E017_H + +#include "bsp_api.h" +#include "SCE_module.h" + +#define SCE ((SCE_Type*) SCE_BASE) + +typedef struct { + union { + __IOM uint32_t REG_00H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_00H_b; + }; + union { + __IOM uint32_t REG_04H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_04H_b; + }; + union { + __IOM uint32_t REG_08H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_08H_b; + }; + union { + __IOM uint32_t REG_0CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_0CH_b; + }; + union { + __IOM uint32_t REG_10H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_10H_b; + }; + union { + __IOM uint32_t REG_14H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_14H_b; + }; + union { + __IOM uint32_t REG_18H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_18H_b; + }; + union { + __IOM uint32_t REG_1CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1CH_b; + }; + union { + __IOM uint32_t REG_20H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_20H_b; + }; + union { + __IOM uint32_t REG_24H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_24H_b; + }; + union { + __IOM uint32_t REG_28H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_28H_b; + }; + union { + __IOM uint32_t REG_2CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_2CH_b; + }; + union { + __IOM uint32_t REG_30H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_30H_b; + }; + union { + __IOM uint32_t REG_34H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_34H_b; + }; + union { + __IOM uint32_t REG_38H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_38H_b; + }; + union { + __IOM uint32_t REG_3CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_3CH_b; + }; + union { + __IOM uint32_t REG_40H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_40H_b; + }; + union { + __IOM uint32_t REG_44H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_44H_b; + }; + union { + __IOM uint32_t REG_48H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_48H_b; + }; + union { + __IOM uint32_t REG_4CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_4CH_b; + }; + union { + __IOM uint32_t REG_50H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_50H_b; + }; + union { + __IOM uint32_t REG_54H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_54H_b; + }; + union { + __IOM uint32_t REG_58H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_58H_b; + }; + union { + __IOM uint32_t REG_5CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_5CH_b; + }; + union { + __IOM uint32_t REG_60H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_60H_b; + }; + union { + __IOM uint32_t REG_64H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_64H_b; + }; + union { + __IOM uint32_t REG_68H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_68H_b; + }; + union { + __IOM uint32_t REG_6CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_6CH_b; + }; + union { + __IOM uint32_t REG_70H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_70H_b; + }; + union { + __IOM uint32_t REG_74H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_74H_b; + }; + union { + __IOM uint32_t REG_78H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_78H_b; + }; + union { + __IOM uint32_t REG_7CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_7CH_b; + }; + union { + __IOM uint32_t REG_80H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_80H_b; + }; + union { + __IOM uint32_t REG_84H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_84H_b; + }; + union { + __IOM uint32_t REG_88H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_88H_b; + }; + union { + __IOM uint32_t REG_8CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_8CH_b; + }; + union { + __IOM uint32_t REG_90H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_90H_b; + }; + union { + __IOM uint32_t REG_94H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_94H_b; + }; + union { + __IOM uint32_t REG_98H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_98H_b; + }; + union { + __IOM uint32_t REG_9CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_9CH_b; + }; + union { + __IOM uint32_t REG_A0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_A0H_b; + }; + union { + __IOM uint32_t REG_A4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_A4H_b; + }; + union { + __IOM uint32_t REG_A8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_A8H_b; + }; + union { + __IOM uint32_t REG_ACH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_ACH_b; + }; + union { + __IOM uint32_t REG_B0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_B0H_b; + }; + union { + __IOM uint32_t REG_B4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_B4H_b; + }; + union { + __IOM uint32_t REG_B8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_B8H_b; + }; + union { + __IOM uint32_t REG_BCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_BCH_b; + }; + union { + __IOM uint32_t REG_C0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_C0H_b; + }; + union { + __IOM uint32_t REG_C4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_C4H_b; + }; + union { + __IOM uint32_t REG_C8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_C8H_b; + }; + union { + __IOM uint32_t REG_CCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_CCH_b; + }; + union { + __IOM uint32_t REG_D0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_D0H_b; + }; + union { + __IOM uint32_t REG_D4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_D4H_b; + }; + union { + __IOM uint32_t REG_D8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_D8H_b; + }; + union { + __IOM uint32_t REG_DCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_DCH_b; + }; + union { + __IOM uint32_t REG_E0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_E0H_b; + }; + union { + __IOM uint32_t REG_E4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_E4H_b; + }; + union { + __IOM uint32_t REG_E8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_E8H_b; + }; + union { + __IOM uint32_t REG_ECH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_ECH_b; + }; + union { + __IOM uint32_t REG_F0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_F0H_b; + }; + union { + __IOM uint32_t REG_F4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_F4H_b; + }; + union { + __IOM uint32_t REG_F8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_F8H_b; + }; + union { + __IOM uint32_t REG_FCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_FCH_b; + }; + union { + __IOM uint32_t REG_100H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_100H_b; + }; + union { + __IOM uint32_t REG_104H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_104H_b; + }; + union { + __IOM uint32_t REG_108H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_108H_b; + }; + union { + __IOM uint32_t REG_10CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_10CH_b; + }; + union { + __IOM uint32_t REG_110H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_110H_b; + }; + union { + __IOM uint32_t REG_114H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_114H_b; + }; + union { + __IOM uint32_t REG_118H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_118H_b; + }; + union { + __IOM uint32_t REG_11CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_11CH_b; + }; + union { + __IOM uint32_t REG_120H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_120H_b; + }; + union { + __IOM uint32_t REG_124H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_124H_b; + }; + union { + __IOM uint32_t REG_128H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_128H_b; + }; + union { + __IOM uint32_t REG_12CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_12CH_b; + }; + union { + __IOM uint32_t REG_130H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_130H_b; + }; + union { + __IOM uint32_t REG_134H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_134H_b; + }; + union { + __IOM uint32_t REG_138H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_138H_b; + }; + union { + __IOM uint32_t REG_13CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_13CH_b; + }; + union { + __IOM uint32_t REG_140H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_140H_b; + }; + union { + __IOM uint32_t REG_144H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_144H_b; + }; + union { + __IOM uint32_t REG_148H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_148H_b; + }; + union { + __IOM uint32_t REG_14CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_14CH_b; + }; + union { + __IOM uint32_t REG_150H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_150H_b; + }; + union { + __IOM uint32_t REG_154H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_154H_b; + }; + union { + __IOM uint32_t REG_158H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_158H_b; + }; + union { + __IOM uint32_t REG_15CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_15CH_b; + }; + union { + __IOM uint32_t REG_160H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_160H_b; + }; + union { + __IOM uint32_t REG_164H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_164H_b; + }; + union { + __IOM uint32_t REG_168H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_168H_b; + }; + union { + __IOM uint32_t REG_16CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_16CH_b; + }; + union { + __IOM uint32_t REG_170H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_170H_b; + }; + union { + __IOM uint32_t REG_174H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_174H_b; + }; + union { + __IOM uint32_t REG_178H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_178H_b; + }; + union { + __IOM uint32_t REG_17CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_17CH_b; + }; + union { + __IOM uint32_t REG_180H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_180H_b; + }; + union { + __IOM uint32_t REG_184H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_184H_b; + }; + union { + __IOM uint32_t REG_188H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_188H_b; + }; + union { + __IOM uint32_t REG_18CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_18CH_b; + }; + union { + __IOM uint32_t REG_190H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_190H_b; + }; + union { + __IOM uint32_t REG_194H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_194H_b; + }; + union { + __IOM uint32_t REG_198H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_198H_b; + }; + union { + __IOM uint32_t REG_19CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_19CH_b; + }; + union { + __IOM uint32_t REG_1A0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1A0H_b; + }; + union { + __IOM uint32_t REG_1A4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1A4H_b; + }; + union { + __IOM uint32_t REG_1A8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1A8H_b; + }; + union { + __IOM uint32_t REG_1ACH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1ACH_b; + }; + union { + __IOM uint32_t REG_1B0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1B0H_b; + }; + union { + __IOM uint32_t REG_1B4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1B4H_b; + }; + union { + __IOM uint32_t REG_1B8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1B8H_b; + }; + union { + __IOM uint32_t REG_1BCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1BCH_b; + }; + union { + __IOM uint32_t REG_1C0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1C0H_b; + }; + union { + __IOM uint32_t REG_1C4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1C4H_b; + }; + union { + __IOM uint32_t REG_1C8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1C8H_b; + }; + union { + __IOM uint32_t REG_1CCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1CCH_b; + }; + union { + __IOM uint32_t REG_1D0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1D0H_b; + }; + union { + __IOM uint32_t REG_1D4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1D4H_b; + }; + union { + __IOM uint32_t REG_1D8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1D8H_b; + }; + union { + __IOM uint32_t REG_1DCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1DCH_b; + }; + union { + __IOM uint32_t REG_1E0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1E0H_b; + }; + union { + __IOM uint32_t REG_1E4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1E4H_b; + }; + union { + __IOM uint32_t REG_1E8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1E8H_b; + }; + union { + __IOM uint32_t REG_1ECH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1ECH_b; + }; + union { + __IOM uint32_t REG_1F0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1F0H_b; + }; + union { + __IOM uint32_t REG_1F4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1F4H_b; + }; + union { + __IOM uint32_t REG_1F8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1F8H_b; + }; + union { + __IOM uint32_t REG_1FCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1FCH_b; + }; +} SCE_Type; + +#define MSTP_SECURITY R_MSTP->MSTPCRC_b.MSTPC31 + +#endif /* HW_SCE_E017_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h new file mode 100644 index 0000000000..e203a186b7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h @@ -0,0 +1,16 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define SCE_BASE 0x40161000UL + +#endif // HW_SCE_MODULE_H diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h new file mode 100644 index 0000000000..f09626c68d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h @@ -0,0 +1,792 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef R_SCE_PRIVATE_HEADER_FILE +#define R_SCE_PRIVATE_HEADER_FILE + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_sce.h" +#include "SCE_ProcCommon.h" +#include "r_sce_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern uint32_t const S_FLASH2[]; + +extern uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +extern uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +extern uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +extern uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +extern uint32_t INST_DATA_SIZE; +extern const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM]; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/* --------------------- SCE driver wrapper layer ---------------------- */ + +fsp_err_t R_SCE_SelfCheck1Private(void); +fsp_err_t R_SCE_SelfCheck2Private(void); +fsp_err_t R_SCE_SelfCheck3Private(void); +fsp_err_t R_SCE_LoadHukPrivate(void); +fsp_err_t R_SCE_FwIntegrityCheckPrivate(void); + +fsp_err_t R_SCE_UpdateOemKeyIndexPrivate(sce_oem_cmd_t key_type, + uint8_t * iv, + uint8_t * encrypted_oem_key, + uint32_t * key_index); + +fsp_err_t R_SCE_Aes128EcbEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes128EcbEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128EcbEncryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes128EcbDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes128EcbDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128EcbDecryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes128CbcEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes128CbcEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CbcEncryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes128CbcDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes128CbcDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CbcDecryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); + +fsp_err_t R_SCE_Aes256EcbEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes256EcbEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256EcbEncryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes256EcbDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes256EcbDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256EcbDecryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes256CbcEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes256CbcEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CbcEncryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes256CbcDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes256CbcDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CbcDecryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); + +fsp_err_t R_SCE_Aes128GcmEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes128GcmEncryptUpdateAadPrivate(uint32_t * InData_DataA, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128GcmEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes128GcmEncryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); +fsp_err_t R_SCE_Aes128GcmDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes128GcmDecryptUpdateAadPrivate(uint32_t * InData_DataA, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128GcmDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes128GcmDecryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +fsp_err_t R_SCE_Aes256GcmEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes256GcmEncryptUpdateAadPrivate(uint32_t * InData_DataA, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256GcmEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes256GcmEncryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); +fsp_err_t R_SCE_Aes256GcmDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes256GcmDecryptUpdateAadPrivate(uint32_t * InData_DataA, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256GcmDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes256GcmDecryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +void R_SCE_Aes128GcmEncryptUpdateTransitionPrivate(void); +void R_SCE_Aes128GcmDecryptUpdateTransitionPrivate(void); +void R_SCE_Aes256GcmEncryptUpdateTransitionPrivate(void); +void R_SCE_Aes256GcmDecryptUpdateTransitionPrivate(void); + +fsp_err_t R_SCE_Aes128CcmEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +fsp_err_t R_SCE_Aes128CcmEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CcmEncryptFinalPrivate(uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); +fsp_err_t R_SCE_Aes128CcmDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +fsp_err_t R_SCE_Aes128CcmDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CcmDecryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text); + +fsp_err_t R_SCE_Aes256CcmEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +fsp_err_t R_SCE_Aes256CcmEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CcmEncryptFinalPrivate(uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); +fsp_err_t R_SCE_Aes256CcmDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +fsp_err_t R_SCE_Aes256CcmDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CcmDecryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text); + +fsp_err_t R_SCE_Aes128CmacGenerateInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes128CmacGenerateUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t * InData_Text, uint32_t * OutData_DataT); +fsp_err_t R_SCE_Aes128CmacVerifyInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes128CmacVerifyUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CmacVerifyFinalPrivate(uint32_t All_Msg_Len, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen); + +fsp_err_t R_SCE_Aes256CmacGenerateInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes256CmacGenerateUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t * InData_Text, uint32_t * OutData_DataT); +fsp_err_t R_SCE_Aes256CmacVerifyInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes256CmacVerifyUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CmacVerifyFinalPrivate(uint32_t All_Msg_Len, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen); + +fsp_err_t R_SCE_Sha256InitPrivate(sce_sha_md5_handle_t * handle); +fsp_err_t R_SCE_Sha256UpdatePrivate(sce_sha_md5_handle_t * handle, uint32_t * InData_PaddedMsg, uint32_t MAX_CNT); +fsp_err_t R_SCE_Sha256FinalPrivate(sce_sha_md5_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT, + uint32_t * OutData_MsgDigest, + uint32_t * OutData_Length); + +fsp_err_t R_SCE_Sha256HmacGenerateInitPrivate(sce_hmac_sha_handle_t * handle, + sce_hmac_sha_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Sha256HmacGenerateUpdatePrivate(sce_hmac_sha_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT); +fsp_err_t R_SCE_Sha256HmacGenerateFinalPrivate(sce_hmac_sha_handle_t * handle, uint32_t * OutData_Mac); +fsp_err_t R_SCE_Sha256HmacVerifyInitPrivate(sce_hmac_sha_handle_t * handle, + sce_hmac_sha_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Sha256HmacVerifyUpdatePrivate(sce_hmac_sha_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT); +fsp_err_t R_SCE_Sha256HmacVerifyFinalPrivate(sce_hmac_sha_handle_t * handle, + uint32_t * InData_Mac, + uint32_t * InData_length); + +fsp_err_t R_SCE_Rsa1024ModularExponentEncryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa1024ModularExponentDecryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa2048ModularExponentEncryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa2048ModularExponentDecryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa3072ModularExponentEncryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa4096ModularExponentEncryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); + +fsp_err_t R_SCE_EcdhReadPublicKeyPrivate(uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_data, + uint32_t * InData_Signature, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_EcdhReadPublicKeyWithoutSignaturePrivate(uint32_t * InData_Cmd, + uint32_t * InData_data, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_EcdhMakePublicKeyPrivate(uint32_t * InData_Cmd, + uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * InData_key_id, + uint32_t * OutData_data, + uint32_t * OutData_Signature, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_EcdhCalculateSharedSecretIndexPrivate(uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_EcdhKeyDerivationPrivate(uint32_t * InData_KeyIndexType, + uint32_t * InData_KeyIndex, + uint32_t * InData_KDFType, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT, + uint32_t * InData_SaltKeyIndex, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_Aes128KeyWrapPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_WrappedKeyIndex, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes256KeyWrapPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_WrappedKeyIndex, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes128KeyUnWrapPrivate(sce_aes_wrapped_key_t * InData_MasterKey, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_Text, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_Aes256KeyUnWrapPrivate(sce_aes_wrapped_key_t * InData_MasterKey, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_Text, + uint32_t * OutData_KeyIndex); +/* --------------------- SCE control procedure related ---------------------- */ + +void R_SCE_SoftwareResetSub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_SelfCheck1Sub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_RETRY **/ +fsp_err_t R_SCE_SelfCheck2Sub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_RETRY **/ +fsp_err_t R_SCE_SelfCheck3Sub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_LoadHukSub(uint32_t * InData_LC); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_FwIntegrityCheckSub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_UpdateOemKeyIndexSub(uint32_t * InData_LC, + uint32_t * InData_Cmd, + uint32_t * InData_IV, + uint32_t * InData_InstData, + uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_GenerateAes128RandomKeyIndexSub(uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_GenerateAes256RandomKeyIndexSub(uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateRsa1024RandomKeyIndexSub(uint32_t MAX_CNT, + uint32_t * OutData_PubKeyIndex, + uint32_t * OutData_PrivKeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, + uint32_t * OutData_PubKeyIndex, + uint32_t * OutData_PrivKeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateTlsRsaInstallDataSub(uint32_t *InData_SharedKeyIndex, + uint32_t *InData_SessionKey, + uint32_t *InData_IV, + uint32_t *InData_InstData, + uint32_t *OutData_InstData); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateTlsP256EccKeyIndexSub(uint32_t *OutData_KeyIndex, uint32_t *OutData_PubKey); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateEccRandomKeyIndexSub(uint32_t * InData_CurveType, + uint32_t * InData_Cmd, + uint32_t * OutData_PubKeyIndex, + uint32_t * OutData_PrivKeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateEccP384RandomKeyIndexSub(uint32_t * InData_CurveType, + uint32_t * OutData_PubKeyIndex, + uint32_t * OutData_PrivKeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_GenerateRandomNumberSub(uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128EncryptDecryptInitSub(const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +void R_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128EncryptDecryptFinalSub(void); + + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256EncryptDecryptInitSub(const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +void R_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256EncryptDecryptFinalSub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_Ghash(uint32_t * InData_HV, + uint32_t * InData_IV, + uint32_t * InData_Text, + uint32_t * OutData_DataT, + uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes128GcmEncryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void R_SCE_Aes128GcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128GcmEncryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes128GcmDecryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void R_SCE_Aes128GcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION **/ +fsp_err_t R_SCE_Aes128GcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256GcmEncryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void R_SCE_Aes256GcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256GcmEncryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256GcmDecryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void R_SCE_Aes256GcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION **/ +fsp_err_t R_SCE_Aes256GcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +void R_SCE_Aes128GcmDecryptUpdateTransitionSub(void); +void R_SCE_Aes128GcmEncryptUpdateTransitionSub(void); +void R_SCE_Aes256GcmDecryptUpdateTransitionSub(void); +void R_SCE_Aes256GcmEncryptUpdateTransitionSub(void); +void R_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void R_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void R_SCE_Aes256GcmEncryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void R_SCE_Aes256GcmDecryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes128CcmEncryptInitSub(uint32_t * InData_KeyType, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +void R_SCE_Aes128CcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128CcmEncryptFinalSub(uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes128CcmDecryptInitSub(uint32_t * InData_KeyType, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +void R_SCE_Aes128CcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128CcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes256CcmEncryptInitSub(uint32_t * InData_KeyType, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +void R_SCE_Aes256CcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256CcmEncryptFinalSub(uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes256CcmDecryptInitSub(uint32_t * InData_KeyType, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +void R_SCE_Aes256CcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256CcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128CmacInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex); +void R_SCE_Aes128CmacUpdateSub(uint32_t * InData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION **/ +fsp_err_t R_SCE_Aes128CmacFinalSub(uint32_t * InData_Cmd, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen, + uint32_t * OutData_DataT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256CmacInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex); +void R_SCE_Aes256CmacUpdateSub(uint32_t * InData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION **/ +fsp_err_t R_SCE_Aes256CmacFinalSub(uint32_t * InData_Cmd, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen, + uint32_t * OutData_DataT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_Sha224256GenerateMessageDigestSub(const uint32_t * InData_InitVal, + const uint32_t * InData_PaddedMsg, + const uint32_t MAX_CNT, + uint32_t * OutData_MsgDigest); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_Sha256HmacInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t LEN); +void R_SCE_Sha256HmacUpdateSub(uint32_t * InData_PaddedMsg, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Sha256HmacFinalSub(uint32_t * InData_Cmd, + uint32_t * InData_MAC, + uint32_t * InData_length, + uint32_t * OutData_MAC); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsRootCertificateVerificationSub(uint32_t *InData_Sel_PubKeyType, + uint32_t *InData_Certificates, + uint32_t *InData_CertificatesLength, + uint32_t *InData_Signature, + uint32_t *InData_CertificatesInfo, + uint32_t length, + uint32_t *OutData_PubKey); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsCertificateVerificationSub(uint32_t *InData_Sel_PubKeyType, + uint32_t *InData_PubKey, + uint32_t *InData_TBSCertificate, + uint32_t *InData_TBSCertificateLength, + uint32_t *InData_Signature, + uint32_t *InData_TBSCertificateInfo, + uint32_t length, + uint32_t *OutData_PubKey); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, + uint32_t *InData_PreMasterSecret, + uint32_t *OutData_PreMasterSecret); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_TlsGeneratePreMasterSecretSub(uint32_t *OutData_PreMasterSecret); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsGenerateMasterSecretSub(uint32_t *InData_Sel_CipherSuite, + uint32_t *InData_PreMasterSecret, + uint32_t *InData_ClientRandom, + uint32_t *InData_ServerRandom, + uint32_t *OutData_MasterSecret); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsGenerateSessionKeySub(uint32_t *InData_Sel_CipherSuite, + uint32_t *InData_MasterSecret, + uint32_t *InData_ClientRandom, + uint32_t *InData_ServerRandom, + uint32_t *InData_NonceExplicit, + uint32_t *OutData_ClientMACKeyOperationCode, + uint32_t *OutData_ServerMACKeyOperationCode, + uint32_t *OutData_ClientEncKeyOperationCode, + uint32_t *OutData_ServerEncKeyOperationCode, + uint32_t OutLen); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsGenerateVerifyDataSub(uint32_t *InData_Sel_VerifyData, + uint32_t *InData_MasterSecret, + uint32_t *InData_HandShakeHash, + uint32_t *OutData_VerifyData); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsServersEphemeralEcdhPublicKeyRetrievesSub(uint32_t *InData_Sel_PubKeyType, + uint32_t *InData_ClientRandom, + uint32_t *InData_ServerRandom, + uint32_t *InData_Sel_CompressType, + uint32_t *InData_SKE_Message, + uint32_t *InData_SKE_Signature, + uint32_t *InData_PubKey, + uint32_t *OutData_EphemeralPubKey); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsGeneratePreMasterSecretWithEccP256KeySub(uint32_t *InData_PubKey, + uint32_t *InData_KeyIndex, + uint32_t *OutData_PreMasterSecretIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa1024ModularExponentEncryptSub(const uint32_t * InData_KeyIndex, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa1024ModularExponentDecryptSub(uint32_t * InData_KeyIndex, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa2048ModularExponentEncryptSub(const uint32_t * InData_KeyIndex, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa2048ModularExponentDecryptSub(uint32_t * InData_KeyIndex, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa3072ModularExponentEncryptSub(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaSignatureGenerateSub(uint32_t * InData_CurveType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_MsgDgst, + uint32_t * OutData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaP384SignatureGenerateSub(uint32_t * InData_CurveType, + uint32_t * InData_KeyIndex, + uint32_t * InData_MsgDgst, + uint32_t * OutData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaSignatureVerificationSub(uint32_t * InData_CurveType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_MsgDgst, + uint32_t * InData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaNistP256SignatureVerificationSub(uint32_t *InData_KeyIndex, + uint32_t *InData_MsgDgst, + uint32_t *InData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaP384SignatureVerificationSub(uint32_t * InData_CurveType, + uint32_t * InData_KeyIndex, + uint32_t * InData_MsgDgst, + uint32_t * InData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_DlmsCosemQeuSignatureVerificationSub(uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_data, + uint32_t * InData_Signature, + uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_EcdhP256QeuOutputSub(uint32_t *InData_Cmd, + uint32_t *InData_data, + uint32_t *OutData_KeyIndex); +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_DlmsCosemQevSignatureGenerationSub(uint32_t * InData_Cmd, + uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * InData_key_id, + uint32_t * OutData_data, + uint32_t * OutData_Signature, + uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_DlmsCosemCalculateZSub(uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_DlmsCosemCalculateKekSub(uint32_t *InData_KeyIndexType, + uint32_t * InData_KeyIndex, + uint32_t * InData_KDFType, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT, + uint32_t * InData_SaltKeyIndex, + uint32_t * OutData_KeyIndex); +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_AesKeyWrapSub(uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + int32_t KEY_INDEX_SIZE, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_WrappedKeyIndex, + uint32_t WRAPPED_KEY_SIZE, + uint32_t * OutData_Text); +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_AesKeyUnwrapSub(uint32_t * InData_KeyType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t KEY_INDEX_SIZE, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_Text, + uint32_t WRAPPED_KEY_SIZE, + uint32_t * OutData_KeyIndex); + +void R_SCE_SelfCheck1SubSub(void); +void R_SCE_TlsRootCertificateVerificationSubSub(void); +void R_SCE_TlsGenerateSubSub(void); + +void R_SCE_func000(uint32_t * InData_PaddedMsg, int32_t MAX_CNT); +void R_SCE_func001(void); +void R_SCE_func002(void); +void R_SCE_func003_r1(uint32_t* ARG1); +void R_SCE_func004_r1(uint32_t ARG1); +void R_SCE_func005_r1(uint32_t ARG1); +void R_SCE_func006(void); +void R_SCE_func007(void); +void R_SCE_func008(void); +void R_SCE_func009(void); +void R_SCE_func010_r1(uint32_t ARG1); +void R_SCE_func011(uint32_t * ARG1); +void R_SCE_func022(void); +void R_SCE_func023(void); +void R_SCE_func025_r1(uint32_t ARG1); +void R_SCE_func027_r2(uint32_t ARG1); +void R_SCE_func028_r2(uint32_t ARG1); +void R_SCE_func030(void); +void R_SCE_func040(void); +void R_SCE_func043(void); +void R_SCE_func044(void); +void R_SCE_func048(uint32_t * ARG1); +void R_SCE_func049(uint32_t * ARG1); +void R_SCE_func050(uint32_t ARG1); +void R_SCE_func051(void); +void R_SCE_func052(uint32_t ARG1); +void R_SCE_func053(uint32_t ARG1); +void R_SCE_func054(uint32_t ARG1, uint32_t ARG2); +void R_SCE_func057_r3(uint32_t * ARG1, uint32_t * ARG2, uint32_t * ARG3); +void R_SCE_func059(void); +void R_SCE_func060(void); +void R_SCE_func061(uint32_t ARG1, uint32_t * ARG2); +void R_SCE_func062(uint32_t ARG1, uint32_t * ARG2); +void R_SCE_func063(uint32_t ARG1, uint32_t * ARG2); +void R_SCE_func064(uint32_t ARG1, uint32_t * ARG2); +void R_SCE_func068(void); +void R_SCE_func069(uint32_t* ARG1, uint32_t ARG2); +void R_SCE_func070_r2(uint32_t ARG1); +void R_SCE_func071_r2(uint32_t ARG1); +void R_SCE_func073_r2(uint32_t ARG1); +void R_SCE_func074_r1(void); +void R_SCE_func075_r1(void); +void R_SCE_func076(void); +void R_SCE_func077(void); +void R_SCE_func080(void); +void R_SCE_func081(void); +void R_SCE_func100(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void R_SCE_func101(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void R_SCE_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void R_SCE_func103(void); +void R_SCE_func200(void); +void R_SCE_func202(void); +void R_SCE_func205(void); +void R_SCE_func206(void); +void R_SCE_func207(void); +void R_SCE_func300(void); +void R_SCE_func301(void); +void R_SCE_func302(void); +void R_SCE_func303(void); +void R_SCE_func304_r1(void); +void R_SCE_func305(void); +void R_SCE_func307_r1(void); +void R_SCE_func308(void); +void R_SCE_func309_r1(void); +void R_SCE_func310(void); +void R_SCE_func311_r1(void); +void R_SCE_func312(uint32_t ARG1); +void R_SCE_func313(uint32_t ARG1); +void R_SCE_func314(uint32_t ARG1); +void R_SCE_func315(uint32_t ARG1); +void R_SCE_func316(void); +void R_SCE_func317(void); +void R_SCE_func318(void); +void R_SCE_func319(uint32_t ARG1); +void R_SCE_func320(uint32_t ARG1); +void R_SCE_func321(uint32_t ARG1); +void R_SCE_func322(uint32_t ARG1); +void R_SCE_func323(void); +void R_SCE_func324(void); +void R_SCE_func325_r1(void); + +uint32_t change_endian_long(uint32_t data); + +#endif /* R_SCE_PRIVATE_HEADER_FILE */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c new file mode 100644 index 0000000000..acb4b08638 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c @@ -0,0 +1,2150 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sce_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef SCE_HEX_6A09E667 + #define SCE_HEX_6A09E667 0x6a09e667UL +#endif +#ifndef SCE_HEX_BB67AE85 + #define SCE_HEX_BB67AE85 0xbb67ae85UL +#endif +#ifndef SCE_HEX_3C6EF372 + #define SCE_HEX_3C6EF372 0x3c6ef372UL +#endif +#ifndef SCE_HEX_A54FF53A + #define SCE_HEX_A54FF53A 0xa54ff53aUL +#endif +#ifndef SCE_HEX_510E527F + #define SCE_HEX_510E527F 0x510e527fUL +#endif +#ifndef SCE_HEX_9B05688C + #define SCE_HEX_9B05688C 0x9b05688cUL +#endif +#ifndef SCE_HEX_1F83D9AB + #define SCE_HEX_1F83D9AB 0x1f83d9abUL +#endif +#ifndef SCE_HEX_5BE0CD19 + #define SCE_HEX_5BE0CD19 0x5be0cd19UL +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES ECB mode algorithm with AES 128 key. + * + * @param InData_KeyIndex User key generation information area. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128EcbEncryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + uint32_t indata_iv[4] = /* dummy */ + { + 0 + }; + + if ((SCE_KEY_INDEX_TYPE_AES128 != InData_KeyIndex->type) && (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH != InData_KeyIndex->type)) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + indata_cmd = change_endian_long(0); /* ECB-Encrypt command */ + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes128EncryptDecryptInitSub(&indata_keytype, &indata_cmd, InData_KeyIndex->value, indata_iv); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES ECB mode algorithm with AES 128 key. + * + * @param InData_Text Input plain text. + * @param OutData_Text Output cipher text. + * @param MAX_CNT Input byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128EcbEncryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes128EncryptDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES ECB mode algorithm with AES 128 key. + * + * @param OutData_Text Output cipher text. + * @param OutData_length Output byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128EcbEncryptFinalPrivate (uint32_t * OutData_Text, uint32_t * OutData_length) +{ + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_length); + + return R_SCE_Aes128EncryptDecryptFinalSub(); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES ECB mode algorithm with AES 128 key. + * + * @param InData_KeyIndex User key generation information area. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128EcbDecryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + uint32_t indata_iv[4] = /* dummy */ + { + 0 + }; + + if ((SCE_KEY_INDEX_TYPE_AES128 != InData_KeyIndex->type) && (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH != InData_KeyIndex->type)) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + indata_cmd = change_endian_long(1); /* ECB-Decrypt command */ + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes128EncryptDecryptInitSub(&indata_keytype, &indata_cmd, InData_KeyIndex->value, indata_iv); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES ECB mode algorithm with AES 128 key. + * + * @param InData_Text Input cipher text. + * @param OutData_Text Output plain text. + * @param MAX_CNT Input byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128EcbDecryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes128EncryptDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES ECB mode algorithm with AES 128 key. + * + * @param OutData_Text Output plain text. + * @param OutData_length Output byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128EcbDecryptFinalPrivate (uint32_t * OutData_Text, uint32_t * OutData_length) +{ + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_length); + + return R_SCE_Aes128EncryptDecryptFinalSub(); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES ECB mode algorithm with AES 256 key. + * + * @param InData_KeyIndex User key generation information area. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256EcbEncryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + uint32_t indata_iv[4] = /* dummy */ + { + 0 + }; + + if ((SCE_KEY_INDEX_TYPE_AES256 != InData_KeyIndex->type) && (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH != InData_KeyIndex->type)) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + indata_cmd = change_endian_long(0); /* ECB-Encrypt command */ + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes256EncryptDecryptInitSub(&indata_keytype, &indata_cmd, InData_KeyIndex->value, indata_iv); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES ECB mode algorithm with AES 256 key. + * + * @param InData_Text Input plain text. + * @param OutData_Text Output cipher text. + * @param MAX_CNT Input byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256EcbEncryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes256EncryptDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES ECB mode algorithm with AES 256 key. + * + * @param OutData_Text Output cipher text. + * @param OutData_length Output byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256EcbEncryptFinalPrivate (uint32_t * OutData_Text, uint32_t * OutData_length) +{ + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_length); + + return R_SCE_Aes256EncryptDecryptFinalSub(); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES ECB mode algorithm with AES 256 key. + * + * @param InData_KeyIndex User key generation information area. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256EcbDecryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + uint32_t indata_iv[4] = /* dummy */ + { + 0 + }; + + if ((SCE_KEY_INDEX_TYPE_AES256 != InData_KeyIndex->type) && (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH != InData_KeyIndex->type)) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + indata_cmd = change_endian_long(1); /* ECB-Decrypt command */ + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes256EncryptDecryptInitSub(&indata_keytype, &indata_cmd, InData_KeyIndex->value, indata_iv); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES ECB mode algorithm with AES 256 key. + * + * @param InData_Text Input cipher text. + * @param OutData_Text Output plain text. + * @param MAX_CNT Input byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256EcbDecryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes256EncryptDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES ECB mode algorithm with AES 256 key. + * + * @param OutData_Text Output plain text. + * @param OutData_length Output byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256EcbDecryptFinalPrivate (uint32_t * OutData_Text, uint32_t * OutData_length) +{ + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_length); + + return R_SCE_Aes256EncryptDecryptFinalSub(); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CBC mode algorithm with AES 128 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CbcEncryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + + if ((SCE_KEY_INDEX_TYPE_AES128 != InData_KeyIndex->type) && ((SCE_KEY_INDEX_TYPE_AES128_FOR_TLS != InData_KeyIndex->type) + && (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH != InData_KeyIndex->type))) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + if (SCE_KEY_INDEX_TYPE_AES128_FOR_TLS != InData_KeyIndex->type) + { + indata_cmd = change_endian_long(2); /* CBC-Encrypt command */ + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + } + else + { + indata_cmd = change_endian_long(5); /* CBC-Encrypt for TLS command */ + } + return R_SCE_Aes128EncryptDecryptInitSub(&indata_keytype, &indata_cmd, InData_KeyIndex->value, InData_IV); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CBC mode algorithm with AES 128 key. + * + * @param InData_Text Input plain text. + * @param OutData_Text Output cipher text. + * @param MAX_CNT Input byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CbcEncryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes128EncryptDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CBC mode algorithm with AES 128 key. + * + * @param OutData_Text Output cipher text. + * @param OutData_length Output byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CbcEncryptFinalPrivate (uint32_t * OutData_Text, uint32_t * OutData_length) +{ + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_length); + + return R_SCE_Aes128EncryptDecryptFinalSub(); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CBC mode algorithm with AES 128 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CbcDecryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + + if ((SCE_KEY_INDEX_TYPE_AES128 != InData_KeyIndex->type) && ((SCE_KEY_INDEX_TYPE_AES128_FOR_TLS != InData_KeyIndex->type) + && (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH != InData_KeyIndex->type))) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + if (SCE_KEY_INDEX_TYPE_AES128_FOR_TLS != InData_KeyIndex->type) + { + indata_cmd = change_endian_long(3); /* CBC-Decrypt command */ + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + } + else + { + indata_cmd = change_endian_long(6); /* CBC-Decrypt for TLS command */ + } + return R_SCE_Aes128EncryptDecryptInitSub(&indata_keytype, &indata_cmd, InData_KeyIndex->value, InData_IV); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CBC mode algorithm with AES 128 key. + * + * @param InData_Text Input cipher text. + * @param OutData_Text Output plain text. + * @param MAX_CNT Input byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CbcDecryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes128EncryptDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CBC mode algorithm with AES 128 key. + * + * @param OutData_Text Output plain text. + * @param OutData_length Output byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CbcDecryptFinalPrivate (uint32_t * OutData_Text, uint32_t * OutData_length) +{ + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_length); + + return R_SCE_Aes128EncryptDecryptFinalSub(); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CBC mode algorithm with AES 256 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CbcEncryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + + if ((SCE_KEY_INDEX_TYPE_AES256 != InData_KeyIndex->type) && ((SCE_KEY_INDEX_TYPE_AES256_FOR_TLS != InData_KeyIndex->type) + && (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH != InData_KeyIndex->type))) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + if (SCE_KEY_INDEX_TYPE_AES256_FOR_TLS != InData_KeyIndex->type) + { + indata_cmd = change_endian_long(2); /* CBC-Encrypt command */ + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + } + else + { + indata_cmd = change_endian_long(5); /* CBC-Encrypt for TLS command */ + } + return R_SCE_Aes256EncryptDecryptInitSub(&indata_keytype, &indata_cmd, InData_KeyIndex->value, InData_IV); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CBC mode algorithm with AES 256 key. + * + * @param InData_Text Input plain text. + * @param OutData_Text Output cipher text. + * @param MAX_CNT Input byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CbcEncryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes256EncryptDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CBC mode algorithm with AES 256 key. + * + * @param OutData_Text Output cipher text. + * @param OutData_length Output byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CbcEncryptFinalPrivate (uint32_t * OutData_Text, uint32_t * OutData_length) +{ + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_length); + + return R_SCE_Aes256EncryptDecryptFinalSub(); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CBC mode algorithm with AES 256 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CbcDecryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + + if ((SCE_KEY_INDEX_TYPE_AES256 != InData_KeyIndex->type) && ((SCE_KEY_INDEX_TYPE_AES256_FOR_TLS != InData_KeyIndex->type) + && (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH != InData_KeyIndex->type))) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + if (SCE_KEY_INDEX_TYPE_AES256_FOR_TLS != InData_KeyIndex->type) + { + indata_cmd = change_endian_long(3); /* CBC-Decrypt command */ + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + } + else + { + indata_cmd = change_endian_long(6); /* CBC-Decrypt for TLS command */ + } + return R_SCE_Aes256EncryptDecryptInitSub(&indata_keytype, &indata_cmd, InData_KeyIndex->value, InData_IV); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CBC mode algorithm with AES 256 key. + * + * @param InData_Text Input cipher text. + * @param OutData_Text Output plain text. + * @param MAX_CNT Input byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CbcDecryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes256EncryptDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CBC mode algorithm with AES 256 key. + * + * @param OutData_Text Output plain text. + * @param OutData_length Output byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CbcDecryptFinalPrivate (uint32_t * OutData_Text, uint32_t * OutData_length) +{ + FSP_PARAMETER_NOT_USED(OutData_Text); + FSP_PARAMETER_NOT_USED(OutData_length); + + return R_SCE_Aes256EncryptDecryptFinalSub(); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES GCM algorithm with AES 128 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128GcmEncryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV) +{ + uint32_t indata_cmd = 0; + + if (SCE_KEY_INDEX_TYPE_AES128 == InData_KeyIndex->type) + { + indata_cmd = change_endian_long(0); /* GCM-Encrypt command */ + } + if (SCE_KEY_INDEX_TYPE_AES128_FOR_TLS == InData_KeyIndex->type) + { + indata_cmd = change_endian_long(1); /* For TLS */ + } + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_cmd = change_endian_long(2); /* For ECDH */ + } + + return R_SCE_Aes128GcmEncryptInitSub(&indata_cmd, InData_KeyIndex->value, InData_IV); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES GCM algorithm with AES 128 key for additional authentication data. + * + * @param InData_DataA Input additional authentication data. + * @param MAX_CNT Input additional authenticated data byte size. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128GcmEncryptUpdateAadPrivate (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + R_SCE_Aes128GcmEncryptUpdateAADSub(InData_DataA, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES GCM algorithm with AES 128 key. + * + * @param InData_Text Input plain text. + * @param MAX_CNT Input byte size of plain. + * @param OutData_Text Output cipher text. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128GcmEncryptUpdatePrivate (uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text) +{ + R_SCE_Aes128GcmEncryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES GCM algorithm with AES 128 key. + * + * @param InData_Text Input plain text. + * @param InData_DataALen Input byte size of additional authentication data. + * @param InData_TextLen Input byte size of plain. + * @param OutData_Text Output cipher text. + * @param OutData_DataT Output atag. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128GcmEncryptFinalPrivate (uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT) +{ + return R_SCE_Aes128GcmEncryptFinalSub(InData_Text, InData_DataALen, InData_TextLen, OutData_Text, OutData_DataT); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES GCM algorithm with AES 128 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128GcmDecryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV) +{ + uint32_t indata_cmd = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES128 == InData_KeyIndex->type) + { + indata_cmd = change_endian_long(0); /* GCM-Encrypt command */ + } + if (SCE_KEY_INDEX_TYPE_AES128_FOR_TLS == InData_KeyIndex->type) + { + indata_cmd = change_endian_long(1); /* For TLS */ + } + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_cmd = change_endian_long(2); /* For ECDH */ + } + if (SCE_KEY_INDEX_TYPE_AES128_GCM_WITH_IV == InData_KeyIndex->type) + { + indata_cmd = change_endian_long(3); + } + return R_SCE_Aes128GcmDecryptInitSub(&indata_cmd, InData_KeyIndex->value, InData_IV); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES GCM algorithm with AES 128 key for additional authentication data. + * + * @param InData_DataA Input additional authentication data. + * @param MAX_CNT Input additional authenticated data byte size. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128GcmDecryptUpdateAadPrivate (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + R_SCE_Aes128GcmDecryptUpdateAADSub(InData_DataA, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES GCM algorithm with AES 128 key. + * + * @param InData_Text Input cipher text. + * @param MAX_CNT Input byte size of cipher. + * @param OutData_Text Output plain text. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128GcmDecryptUpdatePrivate (uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text) +{ + R_SCE_Aes128GcmDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES GCM algorithm with AES 128 key. + * + * @param InData_Text Input plain text. + * @param InData_DataT Input atag. + * @param InData_DataALen Input byte size of additional authentication data. + * @param InData_TextLen Input byte size of cipher. + * @param InData_DataTLen Input byte size of atag. + * @param OutData_Text Output plain text. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication NG + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128GcmDecryptFinalPrivate (uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text) +{ + return R_SCE_Aes128GcmDecryptFinalSub(InData_Text, + InData_DataT, + InData_DataALen, + InData_TextLen, + InData_DataTLen, + OutData_Text); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES GCM mode algorithm with AES 256 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256GcmEncryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes256GcmEncryptInitSub(&indata_keytype, InData_KeyIndex->value, InData_IV); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES GCM algorithm with AES 256 key for additional authentication data. + * + * @param InData_DataA Input additional authentication data. + * @param MAX_CNT Input additional authenticated data byte size. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256GcmEncryptUpdateAadPrivate (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + R_SCE_Aes256GcmEncryptUpdateAADSub(InData_DataA, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES GCM algorithm with AES 256 key. + * + * @param InData_Text Input plain text. + * @param MAX_CNT Input byte size of plain. + * @param OutData_Text Output cipher text. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256GcmEncryptUpdatePrivate (uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text) +{ + R_SCE_Aes256GcmEncryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES GCM algorithm with AES 256 key. + * + * @param InData_Text Input plain text. + * @param InData_DataALen Input byte size of additional authentication data. + * @param InData_TextLen Input byte size of plain. + * @param OutData_Text Output cipher text. + * @param OutData_DataT Output atag. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256GcmEncryptFinalPrivate (uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT) +{ + return R_SCE_Aes256GcmEncryptFinalSub(InData_Text, InData_DataALen, InData_TextLen, OutData_Text, OutData_DataT); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES GCM algorithm with AES 256 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256GcmDecryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes256GcmDecryptInitSub(&indata_keytype, InData_KeyIndex->value, InData_IV); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES GCM algorithm with AES 256 key for additional authentication data. + * + * @param InData_DataA Input additional authentication data. + * @param MAX_CNT Input additional authenticated data byte size. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256GcmDecryptUpdateAadPrivate (uint32_t * InData_DataA, uint32_t MAX_CNT) +{ + R_SCE_Aes256GcmDecryptUpdateAADSub(InData_DataA, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES GCM algorithm with AES 256 key. + * + * @param InData_Text Input cipher text. + * @param MAX_CNT Input byte size of cipher. + * @param OutData_Text Output plain text. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256GcmDecryptUpdatePrivate (uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text) +{ + R_SCE_Aes256GcmDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES GCM algorithm with AES 256 key. + * + * @param InData_Text Input plain text. + * @param InData_DataT Input atag. + * @param InData_DataALen Input byte size of additional authentication data. + * @param InData_TextLen Input byte size of cipher. + * @param InData_DataTLen Input byte size of atag. + * @param OutData_Text Output plain text. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication NG + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256GcmDecryptFinalPrivate (uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text) +{ + return R_SCE_Aes256GcmDecryptFinalSub(InData_Text, + InData_DataT, + InData_DataALen, + InData_TextLen, + InData_DataTLen, + OutData_Text); +} + +/*******************************************************************************************************************//** + * Transition SCE mode for encrypt data using AES128 GCM algorithm. + **********************************************************************************************************************/ +void R_SCE_Aes128GcmEncryptUpdateTransitionPrivate (void) +{ + R_SCE_Aes128GcmEncryptUpdateTransitionSub(); +} + +/*******************************************************************************************************************//** + * Transition SCE mode for decrypt data using AES128 GCM algorithm. + **********************************************************************************************************************/ +void R_SCE_Aes128GcmDecryptUpdateTransitionPrivate (void) +{ + R_SCE_Aes128GcmDecryptUpdateTransitionSub(); +} + +/*******************************************************************************************************************//** + * Transition SCE mode for encrypt data using AES256 GCM algorithm. + **********************************************************************************************************************/ +void R_SCE_Aes256GcmEncryptUpdateTransitionPrivate (void) +{ + R_SCE_Aes256GcmEncryptUpdateTransitionSub(); +} + +/*******************************************************************************************************************//** + * Transition SCE mode for decrypt data using AES256 GCM algorithm. + **********************************************************************************************************************/ +void R_SCE_Aes256GcmDecryptUpdateTransitionPrivate (void) +{ + R_SCE_Aes256GcmDecryptUpdateTransitionSub(); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CCM algorithm with AES 128 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * @param InData_Header Formatted data area. + * @param Header_Len Formatted data length. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CcmEncryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes128CcmEncryptInitSub(&indata_keytype, InData_KeyIndex->value, InData_IV, InData_Header, Header_Len); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CCM algorithm with AES 128 key. + * + * @param InData_Text Input plain text. + * @param OutData_Text Output cipher text. + * @param MAX_CNT Input byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CcmEncryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes128CcmEncryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CCM algorithm with AES 128 key. + * + * @param InData_TextLen Input byte size of plain. + * @param InData_Text Input plain text. + * @param OutData_Text Output cipher text. + * @param OutData_MAC Output MAC data. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CcmEncryptFinalPrivate (uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC) +{ + return R_SCE_Aes128CcmEncryptFinalSub(InData_TextLen, InData_Text, OutData_Text, OutData_MAC); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CCM algorithm with AES 128 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * @param InData_Header Formatted data area. + * @param Header_Len Formatted data length. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CcmDecryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes128CcmDecryptInitSub(&indata_keytype, InData_KeyIndex->value, InData_IV, InData_Header, Header_Len); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CCM algorithm with AES 128 key. + * + * @param InData_Text Input cipher text. + * @param OutData_Text Output plain text. + * @param MAX_CNT Input byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CcmDecryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes128CcmDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CCM algorithm with AES 128 key. + * + * @param InData_Text Input cipher text. + * @param InData_TextLen Input byte size of cipher. + * @param InData_MAC Input MAC data. + * @param InData_MACLength Input byte size of MAC data. + * @param OutData_Text Output plain text. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CcmDecryptFinalPrivate (uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text) +{ + return R_SCE_Aes128CcmDecryptFinalSub(InData_Text, InData_TextLen, InData_MAC, InData_MACLength, OutData_Text); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CCM algorithm with AES 256 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * @param InData_Header Formatted data area. + * @param Header_Len Formatted data length. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CcmEncryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes256CcmEncryptInitSub(&indata_keytype, InData_KeyIndex->value, InData_IV, InData_Header, Header_Len); +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CCM algorithm with AES 256 key. + * + * @param InData_Text Input plain text. + * @param OutData_Text Output cipher text. + * @param MAX_CNT Input byte size of plain. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CcmEncryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes256CcmEncryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Encrypt data to cipher using AES CCM algorithm with AES 256 key. + * + * @param InData_TextLen Input byte size of plain. + * @param InData_Text Input plain text. + * @param OutData_Text Output cipher text. + * @param OutData_MAC Output MAC data. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CcmEncryptFinalPrivate (uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC) +{ + return R_SCE_Aes256CcmEncryptFinalSub(InData_TextLen, InData_Text, OutData_Text, OutData_MAC); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CCM algorithm with AES 256 key. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_IV Input initial vector. + * @param InData_Header Formatted data area. + * @param Header_Len Formatted data length. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CcmDecryptInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes256CcmDecryptInitSub(&indata_keytype, InData_KeyIndex->value, InData_IV, InData_Header, Header_Len); +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CCM algorithm with AES 256 key. + * + * @param InData_Text Input cipher text. + * @param OutData_Text Output plain text. + * @param MAX_CNT Input byte size of cipher. + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CcmDecryptUpdatePrivate (uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes256CcmDecryptUpdateSub(InData_Text, OutData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Decrypt data to plain using AES CCM algorithm with AES 256 key. + * + * @param InData_Text Input cipher text. + * @param InData_TextLen Input byte size of cipher. + * @param InData_MAC Input MAC data. + * @param InData_MACLength Input byte size of MAC data. + * @param OutData_Text Output plain text. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CcmDecryptFinalPrivate (uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text) +{ + return R_SCE_Aes256CcmDecryptFinalSub(InData_Text, InData_TextLen, InData_MAC, InData_MACLength, OutData_Text); +} + +/*******************************************************************************************************************//** + * Prepare to execute AES calculation. + * + * @param InData_KeyIndex User key generation information area + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CmacGenerateInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes128CmacInitSub(&indata_keytype, InData_KeyIndex->value); +} + +/*******************************************************************************************************************//** + * Generates a MAC value from the message specified. + * + * @param InData_Text Message data area (data_len byte) + * @param MAX_CNT Message data length (0 to arbitrary byte) + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CmacGenerateUpdatePrivate (uint32_t * InData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes128CmacUpdateSub(InData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Outputs the Mac value. + * + * @param All_Msg_Len Input byte size of message data. + * @param InData_Text Input message data. + * @param OutData_DataT MAC data area (data_len byte) + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Reserved. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CmacGenerateFinalPrivate (uint32_t All_Msg_Len, uint32_t * InData_Text, uint32_t * OutData_DataT) +{ + uint32_t indata_cmd = 0; + uint32_t indata_datat[4] = /* dummy */ + { + 0 + }; + uint32_t indata_datat_len = 0; /* dummy */ + + if ((0 == (All_Msg_Len % 16)) && (0 != All_Msg_Len)) + { + indata_cmd = 0; + } + else + { + indata_cmd = 1; + } + + return R_SCE_Aes128CmacFinalSub(&indata_cmd, InData_Text, indata_datat, &indata_datat_len, OutData_DataT); +} + +/*******************************************************************************************************************//** + * Prepare to execute CMAC calculation. + * + * @param InData_KeyIndex User key generation information area + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CmacVerifyInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes128CmacInitSub(&indata_keytype, InData_KeyIndex->value); +} + +/*******************************************************************************************************************//** + * Verifies the MAC value. + * + * @param InData_Text Message data area (data_len byte) + * @param MAX_CNT Message data length (0 to arbitrary byte) + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CmacVerifyUpdatePrivate (uint32_t * InData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes128CmacUpdateSub(InData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validates the Mac value. + * + * @param All_Msg_Len Input byte size of message data. + * @param InData_Text Input message data. + * @param InData_DataT MAC data area (data_len byte) + * @param InData_DataTLen MAC data length + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication NG + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128CmacVerifyFinalPrivate (uint32_t All_Msg_Len, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen) +{ + uint32_t indata_cmd = 0; + uint32_t out_data[4] = + { + 0 + }; + + if ((0 == (All_Msg_Len % 16)) && (0 != All_Msg_Len)) + { + indata_cmd = 2; + } + else + { + indata_cmd = 3; + } + + return R_SCE_Aes128CmacFinalSub(&indata_cmd, InData_Text, InData_DataT, InData_DataTLen, out_data); +} + +/*******************************************************************************************************************//** + * Prepare to execute AES calculation. + * + * @param InData_KeyIndex User key generation information area + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CmacGenerateInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes256CmacInitSub(&indata_keytype, InData_KeyIndex->value); +} + +/*******************************************************************************************************************//** + * Generates a MAC value from the message specified. + * + * @param InData_Text Message data area (data_len byte) + * @param MAX_CNT Message data length (0 to arbitrary byte) + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CmacGenerateUpdatePrivate (uint32_t * InData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes256CmacUpdateSub(InData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Outputs the Mac value. + * + * @param All_Msg_Len Input byte size of message data. + * @param InData_Text Input message data. + * @param OutData_DataT MAC data area (data_len byte) + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Reserved. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CmacGenerateFinalPrivate (uint32_t All_Msg_Len, uint32_t * InData_Text, uint32_t * OutData_DataT) +{ + uint32_t indata_cmd = 0; + uint32_t indata_datat[4] = /* dummy */ + { + 0 + }; + uint32_t indata_datat_len = 0; /* dummy */ + + if ((0 == (All_Msg_Len % 16)) && (0 != All_Msg_Len)) + { + indata_cmd = 0; + } + else + { + indata_cmd = 1; + } + + return R_SCE_Aes256CmacFinalSub(&indata_cmd, InData_Text, indata_datat, &indata_datat_len, OutData_DataT); +} + +/*******************************************************************************************************************//** + * Prepare to execute CMAC calculation. + * + * @param InData_KeyIndex User key generation information area + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CmacVerifyInitPrivate (sce_aes_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + return R_SCE_Aes256CmacInitSub(&indata_keytype, InData_KeyIndex->value); +} + +/*******************************************************************************************************************//** + * Verifies the MAC value. + * + * @param InData_Text Message data area (data_len byte) + * @param MAX_CNT Message data length (0 to arbitrary byte) + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CmacVerifyUpdatePrivate (uint32_t * InData_Text, uint32_t MAX_CNT) +{ + R_SCE_Aes256CmacUpdateSub(InData_Text, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Validates the Mac value. + * + * @param All_Msg_Len Input byte size of message data. + * @param InData_Text Input message data. + * @param InData_DataT MAC data area (data_len byte) + * @param InData_DataTLen MAC data length + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication NG + **********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256CmacVerifyFinalPrivate (uint32_t All_Msg_Len, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen) +{ + uint32_t indata_cmd = 0; + uint32_t out_data[4] = + { + 0 + }; + + if ((0 == (All_Msg_Len % 16)) && (0 != All_Msg_Len)) + { + indata_cmd = 2; + } + else + { + indata_cmd = 3; + } + + return R_SCE_Aes256CmacFinalSub(&indata_cmd, InData_Text, InData_DataT, InData_DataTLen, out_data); +} + +/*******************************************************************************************************************//** + * prepares to execute the SHA256 hash operation + * + * @param handle SHA256 handler (work area) + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256InitPrivate (sce_sha_md5_handle_t * handle) +{ + uint32_t indata_sha256initval[8] = + { + 0 + }; + + FSP_PARAMETER_NOT_USED(handle); + + indata_sha256initval[0] = change_endian_long(SCE_HEX_6A09E667); + indata_sha256initval[1] = change_endian_long(SCE_HEX_BB67AE85); + indata_sha256initval[2] = change_endian_long(SCE_HEX_3C6EF372); + indata_sha256initval[3] = change_endian_long(SCE_HEX_A54FF53A); + indata_sha256initval[4] = change_endian_long(SCE_HEX_510E527F); + indata_sha256initval[5] = change_endian_long(SCE_HEX_9B05688C); + indata_sha256initval[6] = change_endian_long(SCE_HEX_1F83D9AB); + indata_sha256initval[7] = change_endian_long(SCE_HEX_5BE0CD19); + + memcpy(handle->current_hash, indata_sha256initval, HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * calculate a hash value + * + * @param handle SHA256 handler (work area) + * @param InData_PaddedMsg Input message. + * @param MAX_CNT Input message length + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256UpdatePrivate (sce_sha_md5_handle_t * handle, uint32_t * InData_PaddedMsg, uint32_t MAX_CNT) +{ + uint32_t out_data[8] = + { + 0 + }; + fsp_err_t ercd = FSP_SUCCESS; + + FSP_PARAMETER_NOT_USED(handle); + + /*Casting uint32_t pointer is used for address.*/ + ercd = R_SCE_Sha224256GenerateMessageDigestSub((uint32_t *) handle->current_hash, + InData_PaddedMsg, + MAX_CNT, + out_data); + memcpy(handle->current_hash, out_data, HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE); + + return ercd; +} + +/*******************************************************************************************************************//** + * calculate a hash value + * + * @param handle SHA256 handler (work area). + * @param InData_PaddedMsg Input Message data + * @param MAX_CNT Input message length + * @param OutData_MsgDigest Output Hash data + * @param OutData_Length Output Hash length + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256FinalPrivate (sce_sha_md5_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT, + uint32_t * OutData_MsgDigest, + uint32_t * OutData_Length) +{ + fsp_err_t ercd = FSP_SUCCESS; + + FSP_PARAMETER_NOT_USED(handle); + + /*Casting uint32_t pointer is used for address.*/ + ercd = R_SCE_Sha224256GenerateMessageDigestSub((uint32_t *) handle->current_hash, + InData_PaddedMsg, + MAX_CNT, + OutData_MsgDigest); + memcpy(handle->current_hash, OutData_MsgDigest, HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE); + *OutData_Length = HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE; + + return ercd; +} + +/*******************************************************************************************************************//** + * Modular exponentiation operation with RSA 1024bit public key + * + * @param InData_KeyIndex the public key index information + * @param InData_Text input data + * @param OutData_Text output data + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Rsa1024ModularExponentEncryptPrivate (uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return R_SCE_Rsa1024ModularExponentEncryptSub(InData_KeyIndex, InData_Text, OutData_Text); +} + +/*******************************************************************************************************************//** + * Modular exponentiation operation with RSA 1024bit private key + * + * @param InData_KeyIndex the private key index information + * @param InData_Text input data + * @param OutData_Text output data + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Rsa1024ModularExponentDecryptPrivate (uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return R_SCE_Rsa1024ModularExponentDecryptSub(InData_KeyIndex, InData_Text, OutData_Text); +} + +/*******************************************************************************************************************//** + * Modular exponentiation operation with RSA 2048bit public key + * + * @param InData_KeyIndex the public key index information + * @param InData_Text input data + * @param OutData_Text output data + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Rsa2048ModularExponentEncryptPrivate (uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return R_SCE_Rsa2048ModularExponentEncryptSub(InData_KeyIndex, InData_Text, OutData_Text); +} + +/*******************************************************************************************************************//** + * Modular exponentiation operation with RSA 2048bit private key + * + * @param InData_KeyIndex the private key index information + * @param InData_Text input data + * @param OutData_Text output data + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Rsa2048ModularExponentDecryptPrivate (uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return R_SCE_Rsa2048ModularExponentDecryptSub(InData_KeyIndex, InData_Text, OutData_Text); +} + +/*******************************************************************************************************************//** + * Modular exponentiation operation with RSA 3072bit public key + * + * @param InData_KeyIndex the public key index information + * @param InData_Text input data + * @param OutData_Text output data + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Rsa3072ModularExponentEncryptPrivate (uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return R_SCE_Rsa3072ModularExponentEncryptSub(InData_KeyIndex, InData_Text, OutData_Text); +} + +/*******************************************************************************************************************//** + * Modular exponentiation operation with RSA 4096bit public key + * + * @param InData_KeyIndex the public key index information + * @param InData_Text input data + * @param OutData_Text output data + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Rsa4096ModularExponentEncryptPrivate (uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return R_SCE_Rsa4096ModularExponentEncryptSub(InData_KeyIndex, InData_Text, OutData_Text); +} + +/*******************************************************************************************************************//** + * prepares to generate the SHA256 HMAC hash value + * + * @param handle SHA256 hamc handler (work area). + * @param InData_KeyIndex key index + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256HmacGenerateInitPrivate (sce_hmac_sha_handle_t * handle, + sce_hmac_sha_wrapped_key_t * InData_KeyIndex) +{ + uint32_t indata_keytype = 0; + uint32_t key_length = HW_SCE_HMAC_KEY_INDEX_WORD_SIZE; + + FSP_PARAMETER_NOT_USED(handle); + + if (SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + if (SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(1); /* For TLS */ + key_length = SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE; + } + return R_SCE_Sha256HmacInitSub(&indata_keytype, InData_KeyIndex->value, key_length); +} + +/*******************************************************************************************************************//** + * Calculate the SHA256 HMAC hash value + * + * @param handle SHA256 HMAC handler (work area). + * @param InData_PaddedMsg Input value + * @param MAX_CNT Input value byte size + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256HmacGenerateUpdatePrivate (sce_hmac_sha_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(handle); + + R_SCE_Sha256HmacUpdateSub(InData_PaddedMsg, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Generate the SHA256 HMAC hash value + * + * @param handle SHA256 HMAC handler (work area). + * @param OutData_Mac Output MAC value + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256HmacGenerateFinalPrivate (sce_hmac_sha_handle_t * handle, uint32_t * OutData_Mac) +{ + FSP_PARAMETER_NOT_USED(handle); + + uint32_t indata_cmd = 0; + uint32_t indata_mac = 0; /*dummy*/ + uint32_t indata_length = 0; /*dummy*/ + + indata_cmd = change_endian_long(0); + + return R_SCE_Sha256HmacFinalSub(&indata_cmd, &indata_mac, &indata_length, OutData_Mac); +} + +/*******************************************************************************************************************//** + * prepares to generate the SHA256 HMAC hash value for TLS + * + * @param handle SHA256 HMAC handler (work area). + * @param InData_KeyIndex key index + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256HmacVerifyInitPrivate (sce_hmac_sha_handle_t * handle, + sce_hmac_sha_wrapped_key_t * InData_KeyIndex) +{ + FSP_PARAMETER_NOT_USED(handle); + + uint32_t indata_keytype = 0; + uint32_t key_length = SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE; + + if (SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_ECDH == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + if (SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS == InData_KeyIndex->type) + { + indata_keytype = change_endian_long(1); /* For TLS */ + key_length = SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE; + } + return R_SCE_Sha256HmacInitSub(&indata_keytype, InData_KeyIndex->value, key_length); +} + +/*******************************************************************************************************************//** + * Calculate the SHA256 HMAC hash value + * + * @param handle SHA256 HMAC handler (work area). + * @param InData_PaddedMsg Input value + * @param MAX_CNT Input value byte size + * + * @retval FSP_SUCCESS Normal termination. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256HmacVerifyUpdatePrivate (sce_hmac_sha_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT) +{ + FSP_PARAMETER_NOT_USED(handle); + + R_SCE_Sha256HmacUpdateSub(InData_PaddedMsg, MAX_CNT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Verify the SHA256 HMAC hash value + * + * @param handle SHA256 HMAC handler (work area). + * @param InData_Mac Input MAC value + * @param InData_length Input MAC value byte size + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Sha256HmacVerifyFinalPrivate (sce_hmac_sha_handle_t * handle, + uint32_t * InData_Mac, + uint32_t * InData_length) +{ + uint32_t indata_cmd = 0; + uint32_t outdata_mac = 0; + + FSP_PARAMETER_NOT_USED(handle); + + indata_cmd = change_endian_long(1); + + return R_SCE_Sha256HmacFinalSub(&indata_cmd, InData_Mac, InData_length, &outdata_mac); +} + +/*******************************************************************************************************************//** + * Verify signature of ECC P-256 public key and output public key generation information. + * + * @param InData_Cmd key_id use or not + * @param InData_KeyIndex public key index for signature verification + * @param InData_data API function argument "public_key_data" plus "stop bit" and "message length" + * @param InData_Signature signature text + * @param OutData_KeyIndex public key index for API function argument "public_key_data" + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred or signature verification failed. + **********************************************************************************************************************/ +fsp_err_t R_SCE_EcdhReadPublicKeyPrivate (uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_data, + uint32_t * InData_Signature, + uint32_t * OutData_KeyIndex) +{ + return R_SCE_DlmsCosemQeuSignatureVerificationSub(InData_Cmd, + InData_KeyIndex, + InData_data, + InData_Signature, + OutData_KeyIndex); +} + +/*******************************************************************************************************************//** + * Output the key index of QeU without signature verification. + * + * @param InData_Cmd key_id use or not + * @param InData_data API function argument "public_key_data" plus "stop bit" and "message length" + * @param OutData_KeyIndex public key index for API function argument "public_key_data" + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +fsp_err_t R_SCE_EcdhReadPublicKeyWithoutSignaturePrivate (uint32_t * InData_Cmd, + uint32_t * InData_data, + uint32_t * OutData_KeyIndex) +{ + return R_SCE_EcdhP256QeuOutputSub(InData_Cmd, InData_data, OutData_KeyIndex); +} + +/*******************************************************************************************************************//** + * Generate signature for public key generation information for ECDH key exchange. + * + * @param InData_Cmd key_id use or not + * @param InData_KeyType type of key to be exchanged + * @param InData_PubKeyIndex public key index(for ECDH) + * @param InData_PrivKeyIndex private key index for signature generation + * @param InData_key_id key_id + * @param OutData_data public key for key exchange + * @param OutData_Signature signature text + * @param OutData_KeyIndex private key index generated from random numbers(for ECDHE) + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_EcdhMakePublicKeyPrivate (uint32_t * InData_Cmd, + uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * InData_key_id, + uint32_t * OutData_data, + uint32_t * OutData_Signature, + uint32_t * OutData_KeyIndex) +{ + return R_SCE_DlmsCosemQevSignatureGenerationSub(InData_Cmd, + InData_KeyType, + InData_PubKeyIndex, + InData_PrivKeyIndex, + InData_key_id, + OutData_data, + OutData_Signature, + OutData_KeyIndex); +} + +/*******************************************************************************************************************//** + * Output key generation information of shared secret "Z" from partner public key and your private key. + * + * @param InData_KeyType type of key to be exchanged + * @param InData_PubKeyIndex public key index + * @param InData_PrivKeyIndex private key index + * @param OutData_KeyIndex key index of shared secret "Z" + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_EcdhCalculateSharedSecretIndexPrivate (uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * OutData_KeyIndex) +{ + return R_SCE_DlmsCosemCalculateZSub(InData_KeyType, InData_PubKeyIndex, InData_PrivKeyIndex, OutData_KeyIndex); +} + +/*******************************************************************************************************************//** + * Key is derived using the shared secret "Z" as the key material. + * + * @param InData_KeyIndexType Derived key type(0:AES-128, 1:AES-256, 2:HMAC-SHA256) + * @param InData_KeyIndex key index of shared secret "Z" + * @param InData_KDFType Algorithm used for key derivation calculation(0:SHA256, 1:HMAC-SHA256) + * @param InData_PaddedMsg additional data used for key derivation, preceded by Algorithm ID encoded value, + * followed by stop bit and data length + * @param MAX_CNT maximum number of loops when reading InData_PaddedMsg + * @param InData_SaltKeyIndex Salt key index + * @param OutData_KeyIndex key index of KEK + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + **********************************************************************************************************************/ +fsp_err_t R_SCE_EcdhKeyDerivationPrivate (uint32_t *InData_KeyIndexType, uint32_t *InData_KeyIndex, + uint32_t *InData_KDFType, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT, uint32_t *InData_SaltKeyIndex, + uint32_t *OutData_KeyIndex) +{ + return R_SCE_DlmsCosemCalculateKekSub(InData_KeyIndexType, InData_KeyIndex, InData_KDFType, InData_PaddedMsg, + MAX_CNT, InData_SaltKeyIndex, OutData_KeyIndex); +} + +/*******************************************************************************************************************//** + * Wrap InData_WrappedKeyIndex with InData_KeyIndex. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_WrappedKeyType select key to be wrapped. + * @param InData_WrappedKeyIndex key to be wrapped. + * @param OutData_Text wrapped key. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + *********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128KeyWrapPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_WrappedKeyIndex, + uint32_t * OutData_Text) +{ + uint32_t indata_cmd = 0; + int32_t key_index_size = 0; + uint32_t wrapped_key_size = 0; + + indata_cmd = change_endian_long(0); + + if (SCE_KEYWRAP_AES128 == (*InData_WrappedKeyType)) + { + wrapped_key_size = 6; + key_index_size = 9; + } + else + { + wrapped_key_size = 10; + key_index_size = 13; + } + + *InData_WrappedKeyType = change_endian_long(*InData_WrappedKeyType); + return R_SCE_AesKeyWrapSub(&indata_cmd, InData_KeyIndex, key_index_size, InData_WrappedKeyType, + InData_WrappedKeyIndex, wrapped_key_size, OutData_Text); +} + +/*******************************************************************************************************************//** + * Wrap InData_WrappedKeyIndex with InData_KeyIndex. + * + * @param InData_KeyIndex User key generation information area. + * @param InData_WrappedKeyType select key to be wrapped. + * @param InData_WrappedKeyIndex key to be wrapped. + * @param OutData_Text wrapped key. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + *********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256KeyWrapPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_WrappedKeyIndex, + uint32_t * OutData_Text) +{ + uint32_t indata_cmd = 0; + int32_t key_index_size = 0; + uint32_t wrapped_key_size = 0; + + indata_cmd = change_endian_long(1); + + if (SCE_KEYWRAP_AES128 == (*InData_WrappedKeyType)) + { + wrapped_key_size = 6; + key_index_size = 9; + } + else + { + wrapped_key_size = 10; + key_index_size = 13; + } + + *InData_WrappedKeyType = change_endian_long(*InData_WrappedKeyType); + + return R_SCE_AesKeyWrapSub(&indata_cmd, InData_KeyIndex, key_index_size, InData_WrappedKeyType, + InData_WrappedKeyIndex, wrapped_key_size, OutData_Text); +} + +/*******************************************************************************************************************//** + * Unwrap InData_Text with key_index. + * + * @param InData_MasterKey key used for unwrapping. + * @param InData_WrappedKeyType select key to be wrapped. + * @param InData_Text wrapped key. + * @param OutData_KeyIndex key to be unwrapped. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + *********************************************************************************************************************/ +fsp_err_t R_SCE_Aes128KeyUnWrapPrivate(sce_aes_wrapped_key_t * InData_MasterKey, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_Text, + uint32_t * OutData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + uint32_t key_index_size = 0; + uint32_t wrapped_key_size = 0; + + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == InData_MasterKey->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + indata_cmd = change_endian_long(0); + + if (SCE_KEYWRAP_AES128 == (*InData_WrappedKeyType)) + { + wrapped_key_size = 6; + key_index_size = 9; + } + else + { + wrapped_key_size = 10; + key_index_size = 13; + } + + *InData_WrappedKeyType = change_endian_long(*InData_WrappedKeyType); + + return R_SCE_AesKeyUnwrapSub(&indata_keytype, &indata_cmd, InData_MasterKey->value, key_index_size, + InData_WrappedKeyType, InData_Text, wrapped_key_size, OutData_KeyIndex); +} + +/*******************************************************************************************************************//** + * Unwrap InData_Text with key_index. + * + * @param InData_MasterKey key used for unwrapping. + * @param InData_WrappedKeyType select key to be wrapped. + * @param InData_Text wrapped key. + * @param OutData_KeyIndex key to be unwrapped. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + *********************************************************************************************************************/ +fsp_err_t R_SCE_Aes256KeyUnWrapPrivate(sce_aes_wrapped_key_t * InData_MasterKey, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_Text, + uint32_t * OutData_KeyIndex) +{ + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + uint32_t key_index_size = 0; + uint32_t wrapped_key_size = 0; + + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == InData_MasterKey->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + indata_cmd = change_endian_long(1); + + if (SCE_KEYWRAP_AES128 == (*InData_WrappedKeyType)) + { + wrapped_key_size = 6; + key_index_size = 9; + } + else + { + wrapped_key_size = 10; + key_index_size = 13; + } + + *InData_WrappedKeyType = change_endian_long(*InData_WrappedKeyType); + + return R_SCE_AesKeyUnwrapSub(&indata_keytype, &indata_cmd, InData_MasterKey->value, key_index_size, + InData_WrappedKeyType, InData_Text, wrapped_key_size, OutData_KeyIndex); +} + +/*******************************************************************************************************************//** + * change endian + * + * @param data input data + * + * @return the data changing endian + **********************************************************************************************************************/ + +uint32_t change_endian_long (uint32_t data) +{ +#ifndef __ARMEB__ /* Little endian */ + + /* Casting is valid because it matches the type to the right side or argument. */ + return __REV(data); +#else /* Big endian */ + return data; +#endif /* defined __LIT */ +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c new file mode 100644 index 0000000000..ccc03cf412 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c @@ -0,0 +1,1980 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sce_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +uint32_t INST_DATA_SIZE; + +const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM] = +{ + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD, +}; + +uint32_t g_private_id_counter; +extern uint32_t g_aes128ecbenc_private_id; +extern uint32_t g_aes128ecbdec_private_id; +extern uint32_t g_aes256ecbenc_private_id; +extern uint32_t g_aes256ecbdec_private_id; +extern uint32_t g_aes128cbcenc_private_id; +extern uint32_t g_aes128cbcdec_private_id; +extern uint32_t g_aes256cbcenc_private_id; +extern uint32_t g_aes256cbcdec_private_id; +extern uint32_t g_aes128cmacgen_private_id; +extern uint32_t g_aes128cmacver_private_id; +extern uint32_t g_aes256cmacgen_private_id; +extern uint32_t g_aes256cmacver_private_id; +extern uint32_t g_aes128gcmenc_private_id; +extern uint32_t g_aes128gcmdec_private_id; +extern uint32_t g_aes256gcmenc_private_id; +extern uint32_t g_aes256gcmdec_private_id; +extern uint32_t g_aes128ccmenc_private_id; +extern uint32_t g_aes128ccmdec_private_id; +extern uint32_t g_aes256ccmenc_private_id; +extern uint32_t g_aes256ccmdec_private_id; +extern uint32_t g_sha256_private_id; +extern uint32_t g_sha256hmacgen_private_id; +extern uint32_t g_sha256hmacver_private_id; +extern uint32_t g_ecdh256_private_id; + +const sce_api_t g_sce_protected_on_sce = +{ + .open = R_SCE_Open, + .close = R_SCE_Close, + .softwareReset = R_SCE_SoftwareReset, + .randomNumberGenerate = R_SCE_RandomNumberGenerate, + .AES128_WrappedKeyGenerate = R_SCE_AES128_WrappedKeyGenerate, + .AES256_WrappedKeyGenerate = R_SCE_AES256_WrappedKeyGenerate, + .AES128_EncryptedKeyWrap = R_SCE_AES128_EncryptedKeyWrap, + .AES256_EncryptedKeyWrap = R_SCE_AES256_EncryptedKeyWrap, + .AES128_RFC3394KeyWrap = R_SCE_AES128_RFC3394KeyWrap, + .AES256_RFC3394KeyWrap = R_SCE_AES256_RFC3394KeyWrap, + .AES128_RFC3394KeyUnwrap = R_SCE_AES128_RFC3394KeyUnwrap, + .AES256_RFC3394KeyUnwrap = R_SCE_AES256_RFC3394KeyUnwrap, + .AES128ECB_EncryptInit = R_SCE_AES128ECB_EncryptInit, + .AES128ECB_EncryptUpdate = R_SCE_AES128ECB_EncryptUpdate, + .AES128ECB_EncryptFinal = R_SCE_AES128ECB_EncryptFinal, + .AES128ECB_DecryptInit = R_SCE_AES128ECB_DecryptInit, + .AES128ECB_DecryptUpdate = R_SCE_AES128ECB_DecryptUpdate, + .AES128ECB_DecryptFinal = R_SCE_AES128ECB_DecryptFinal, + .AES256ECB_EncryptInit = R_SCE_AES256ECB_EncryptInit, + .AES256ECB_EncryptUpdate = R_SCE_AES256ECB_EncryptUpdate, + .AES256ECB_EncryptFinal = R_SCE_AES256ECB_EncryptFinal, + .AES256ECB_DecryptInit = R_SCE_AES256ECB_DecryptInit, + .AES256ECB_DecryptUpdate = R_SCE_AES256ECB_DecryptUpdate, + .AES256ECB_DecryptFinal = R_SCE_AES256ECB_DecryptFinal, + .AES128CBC_EncryptInit = R_SCE_AES128CBC_EncryptInit, + .AES128CBC_EncryptUpdate = R_SCE_AES128CBC_EncryptUpdate, + .AES128CBC_EncryptFinal = R_SCE_AES128CBC_EncryptFinal, + .AES128CBC_DecryptInit = R_SCE_AES128CBC_DecryptInit, + .AES128CBC_DecryptUpdate = R_SCE_AES128CBC_DecryptUpdate, + .AES128CBC_DecryptFinal = R_SCE_AES128CBC_DecryptFinal, + .AES256CBC_EncryptInit = R_SCE_AES256CBC_EncryptInit, + .AES256CBC_EncryptUpdate = R_SCE_AES256CBC_EncryptUpdate, + .AES256CBC_EncryptFinal = R_SCE_AES256CBC_EncryptFinal, + .AES256CBC_DecryptInit = R_SCE_AES256CBC_DecryptInit, + .AES256CBC_DecryptUpdate = R_SCE_AES256CBC_DecryptUpdate, + .AES256CBC_DecryptFinal = R_SCE_AES256CBC_DecryptFinal, + .AES128GCM_EncryptInit = R_SCE_AES128GCM_EncryptInit, + .AES128GCM_EncryptUpdate = R_SCE_AES128GCM_EncryptUpdate, + .AES128GCM_EncryptFinal = R_SCE_AES128GCM_EncryptFinal, + .AES128GCM_DecryptInit = R_SCE_AES128GCM_DecryptInit, + .AES128GCM_DecryptUpdate = R_SCE_AES128GCM_DecryptUpdate, + .AES128GCM_DecryptFinal = R_SCE_AES128GCM_DecryptFinal, + .AES256GCM_EncryptInit = R_SCE_AES256GCM_EncryptInit, + .AES256GCM_EncryptUpdate = R_SCE_AES256GCM_EncryptUpdate, + .AES256GCM_EncryptFinal = R_SCE_AES256GCM_EncryptFinal, + .AES256GCM_DecryptInit = R_SCE_AES256GCM_DecryptInit, + .AES256GCM_DecryptUpdate = R_SCE_AES256GCM_DecryptUpdate, + .AES256GCM_DecryptFinal = R_SCE_AES256GCM_DecryptFinal, + .AES128CCM_EncryptInit = R_SCE_AES128CCM_EncryptInit, + .AES128CCM_EncryptUpdate = R_SCE_AES128CCM_EncryptUpdate, + .AES128CCM_EncryptFinal = R_SCE_AES128CCM_EncryptFinal, + .AES128CCM_DecryptInit = R_SCE_AES128CCM_DecryptInit, + .AES128CCM_DecryptUpdate = R_SCE_AES128CCM_DecryptUpdate, + .AES128CCM_DecryptFinal = R_SCE_AES128CCM_DecryptFinal, + .AES256CCM_EncryptInit = R_SCE_AES256CCM_EncryptInit, + .AES256CCM_EncryptUpdate = R_SCE_AES256CCM_EncryptUpdate, + .AES256CCM_EncryptFinal = R_SCE_AES256CCM_EncryptFinal, + .AES256CCM_DecryptInit = R_SCE_AES256CCM_DecryptInit, + .AES256CCM_DecryptUpdate = R_SCE_AES256CCM_DecryptUpdate, + .AES256CCM_DecryptFinal = R_SCE_AES256CCM_DecryptFinal, + .AES128CMAC_GenerateInit = R_SCE_AES128CMAC_GenerateInit, + .AES128CMAC_GenerateUpdate = R_SCE_AES128CMAC_GenerateUpdate, + .AES128CMAC_GenerateFinal = R_SCE_AES128CMAC_GenerateFinal, + .AES128CMAC_VerifyInit = R_SCE_AES128CMAC_VerifyInit, + .AES128CMAC_VerifyUpdate = R_SCE_AES128CMAC_VerifyUpdate, + .AES128CMAC_VerifyFinal = R_SCE_AES128CMAC_VerifyFinal, + .AES256CMAC_GenerateInit = R_SCE_AES256CMAC_GenerateInit, + .AES256CMAC_GenerateUpdate = R_SCE_AES256CMAC_GenerateUpdate, + .AES256CMAC_GenerateFinal = R_SCE_AES256CMAC_GenerateFinal, + .AES256CMAC_VerifyInit = R_SCE_AES256CMAC_VerifyInit, + .AES256CMAC_VerifyUpdate = R_SCE_AES256CMAC_VerifyUpdate, + .AES256CMAC_VerifyFinal = R_SCE_AES256CMAC_VerifyFinal, + .SHA256_Init = R_SCE_SHA256_Init, + .SHA256_Update = R_SCE_SHA256_Update, + .SHA256_Final = R_SCE_SHA256_Final, + .RSA1024_WrappedKeyPairGenerate = R_SCE_RSA1024_WrappedKeyPairGenerate, + .RSA2048_WrappedKeyPairGenerate = R_SCE_RSA2048_WrappedKeyPairGenerate, + .RSA1024_EncryptedPublicKeyWrap = R_SCE_RSA1024_EncryptedPublicKeyWrap, + .RSA1024_EncryptedPrivateKeyWrap = R_SCE_RSA1024_EncryptedPrivateKeyWrap, + .RSA2048_EncryptedPublicKeyWrap = R_SCE_RSA2048_EncryptedPublicKeyWrap, + .RSA2048_EncryptedPrivateKeyWrap = R_SCE_RSA2048_EncryptedPrivateKeyWrap, + .RSA3072_EncryptedPublicKeyWrap = R_SCE_RSA3072_EncryptedPublicKeyWrap, + .RSA4096_EncryptedPublicKeyWrap = R_SCE_RSA4096_EncryptedPublicKeyWrap, + .RSASSA_PKCS1024_SignatureGenerate = R_SCE_RSASSA_PKCS1024_SignatureGenerate, + .RSASSA_PKCS2048_SignatureGenerate = R_SCE_RSASSA_PKCS2048_SignatureGenerate, + .RSASSA_PKCS1024_SignatureVerify = R_SCE_RSASSA_PKCS1024_SignatureVerify, + .RSASSA_PKCS2048_SignatureVerify = R_SCE_RSASSA_PKCS2048_SignatureVerify, + .RSASSA_PKCS3072_SignatureVerify = R_SCE_RSASSA_PKCS3072_SignatureVerify, + .RSASSA_PKCS4096_SignatureVerify = R_SCE_RSASSA_PKCS4096_SignatureVerify, + .RSAES_PKCS1024_Encrypt = R_SCE_RSAES_PKCS1024_Encrypt, + .RSAES_PKCS2048_Encrypt = R_SCE_RSAES_PKCS2048_Encrypt, + .RSAES_PKCS3072_Encrypt = R_SCE_RSAES_PKCS3072_Encrypt, + .RSAES_PKCS4096_Encrypt = R_SCE_RSAES_PKCS4096_Encrypt, + .RSAES_PKCS1024_Decrypt = R_SCE_RSAES_PKCS1024_Decrypt, + .RSAES_PKCS2048_Decrypt = R_SCE_RSAES_PKCS2048_Decrypt, + .SHA256HMAC_EncryptedKeyWrap = R_SCE_SHA256HMAC_EncryptedKeyWrap, + .SHA256HMAC_GenerateInit = R_SCE_SHA256HMAC_GenerateInit, + .SHA256HMAC_GenerateUpdate = R_SCE_SHA256HMAC_GenerateUpdate, + .SHA256HMAC_GenerateFinal = R_SCE_SHA256HMAC_GenerateFinal, + .SHA256HMAC_VerifyInit = R_SCE_SHA256HMAC_VerifyInit, + .SHA256HMAC_VerifyUpdate = R_SCE_SHA256HMAC_VerifyUpdate, + .SHA256HMAC_VerifyFinal = R_SCE_SHA256HMAC_VerifyFinal, + .ECC_secp192r1_WrappedKeyPairGenerate = R_SCE_ECC_secp192r1_WrappedKeyPairGenerate, + .ECC_secp224r1_WrappedKeyPairGenerate = R_SCE_ECC_secp224r1_WrappedKeyPairGenerate, + .ECC_secp256r1_WrappedKeyPairGenerate = R_SCE_ECC_secp256r1_WrappedKeyPairGenerate, + .ECC_secp384r1_WrappedKeyPairGenerate = R_SCE_ECC_secp384r1_WrappedKeyPairGenerate, + .ECC_secp192r1_EncryptedPublicKeyWrap = R_SCE_ECC_secp192r1_EncryptedPublicKeyWrap, + .ECC_secp224r1_EncryptedPublicKeyWrap = R_SCE_ECC_secp224r1_EncryptedPublicKeyWrap, + .ECC_secp256r1_EncryptedPublicKeyWrap = R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap, + .ECC_secp384r1_EncryptedPublicKeyWrap = R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap, + .ECC_secp192r1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp192r1_EncryptedPrivateKeyWrap, + .ECC_secp224r1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp224r1_EncryptedPrivateKeyWrap, + .ECC_secp256r1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap, + .ECC_secp384r1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap, + .ECDSA_secp192r1_SignatureGenerate = R_SCE_ECDSA_secp192r1_SignatureGenerate, + .ECDSA_secp224r1_SignatureGenerate = R_SCE_ECDSA_secp224r1_SignatureGenerate, + .ECDSA_secp256r1_SignatureGenerate = R_SCE_ECDSA_secp256r1_SignatureGenerate, + .ECDSA_secp384r1_SignatureGenerate = R_SCE_ECDSA_secp384r1_SignatureGenerate, + .ECDSA_secp192r1_SignatureVerify = R_SCE_ECDSA_secp192r1_SignatureVerify, + .ECDSA_secp224r1_SignatureVerify = R_SCE_ECDSA_secp224r1_SignatureVerify, + .ECDSA_secp256r1_SignatureVerify = R_SCE_ECDSA_secp256r1_SignatureVerify, + .ECDSA_secp384r1_SignatureVerify = R_SCE_ECDSA_secp384r1_SignatureVerify, + .ECDH_secp256r1_Init = R_SCE_ECDH_secp256r1_Init, + .ECDH_secp256r1_PublicKeySign = R_SCE_ECDH_secp256r1_PublicKeySign, + .ECDH_secp256r1_PublicKeyVerify = R_SCE_ECDH_secp256r1_PublicKeyVerify, + .ECDH_secp256r1_SharedSecretCalculate = R_SCE_ECDH_secp256r1_SharedSecretCalculate, + .ECDH_secp256r1_KeyDerivation = R_SCE_ECDH_secp256r1_KeyDerivation, + .ECDH_secp256r1_PublicKeyReadWithoutSignature = R_SCE_ECDH_secp256r1_PublicKeyReadWithoutSignature, + .TLS_RootCertificateRSA2048PublicKeyInstall = R_SCE_TLS_RootCertificateRSA2048PublicKeyInstall, + .TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate = R_SCE_TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate, + .TLS_RootCertificateVerify = R_SCE_TLS_RootCertificateVerify, + .TLS_CertificateVerify = R_SCE_TLS_CertificateVerify, + .TLS_PreMasterSecretGenerateForRSA2048 = R_SCE_TLS_PreMasterSecretGenerateForRSA2048, + .TLS_MasterSecretGenerate = R_SCE_TLS_MasterSecretGenerate, + .TLS_PreMasterSecretEncryptWithRSA2048 = R_SCE_TLS_PreMasterSecretEncryptWithRSA2048, + .TLS_SessionKeyGenerate = R_SCE_TLS_SessionKeyGenerate, + .TLS_VerifyDataGenerate = R_SCE_TLS_VerifyDataGenerate, + .TLS_ServerKeyExchangeVerify = R_SCE_TLS_ServerKeyExchangeVerify, + .TLS_PreMasterSecretGenerateForECC_secp256r1 = R_SCE_TLS_PreMasterSecretGenerateForECC_secp256r1 +}; + +/*******************************************************************************************************************//** + * @addtogroup SCE_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enables use of SCE functionality. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL The error-detection self-test failed to terminate normally. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_RETRY Indicates that an entropy evaluation failure occurred. + * Run the function again. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + * + * @note The valid pre-run state is SCE disabled. + * The pre-run state is SCE Disabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Open (sce_ctrl_t * const p_ctrl, sce_cfg_t const * const p_cfg) +{ + sce_instance_ctrl_t * p_instance_ctrl = (sce_instance_ctrl_t *) p_ctrl; + +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_cfg); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + + p_instance_ctrl->open = 1; + FSP_PARAMETER_NOT_USED(p_cfg); + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Casting structure pointer is used for address. */ + MSTP_SECURITY = 0U; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + R_SCE_SoftwareReset(); + error_code = R_SCE_SelfCheck1Private(); + +#ifndef __ARMEB__ /* Little endian */ + /* Casting structure pointer is used for address. */ + const uint32_t register_value = 0x0000ffff; + SCE->REG_1D4H = register_value; +#endif + + if (FSP_SUCCESS == error_code) + { + error_code = R_SCE_LoadHukPrivate(); + } + + if (FSP_SUCCESS == error_code) + { + error_code = R_SCE_FwIntegrityCheckPrivate(); + } + +#if (0 == SCE_USER_FAST_BOOT) + if (FSP_SUCCESS == error_code) + { + error_code = R_SCE_SelfCheck2Private(); + } +#endif + + if (FSP_SUCCESS == error_code) + { + error_code = R_SCE_SelfCheck3Private(); + } + + g_private_id_counter = 0; + g_aes128ecbenc_private_id = 0; + g_aes128ecbdec_private_id = 0; + g_aes256ecbenc_private_id = 0; + g_aes256ecbdec_private_id = 0; + g_aes128cbcenc_private_id = 0; + g_aes128cbcdec_private_id = 0; + g_aes256cbcenc_private_id = 0; + g_aes256cbcdec_private_id = 0; + g_aes128cmacgen_private_id = 0; + g_aes128cmacver_private_id = 0; + g_aes256cmacgen_private_id = 0; + g_aes256cmacver_private_id = 0; + g_aes128gcmenc_private_id = 0; + g_aes128gcmdec_private_id = 0; + g_aes256gcmenc_private_id = 0; + g_aes256gcmdec_private_id = 0; + g_aes128ccmenc_private_id = 0; + g_aes128ccmdec_private_id = 0; + g_aes256ccmenc_private_id = 0; + g_aes256ccmdec_private_id = 0; + g_sha256_private_id = 0; + g_sha256hmacgen_private_id = 0; + g_sha256hmacver_private_id = 0; + g_ecdh256_private_id = 0; + + return error_code; +} + +/*******************************************************************************************************************//** + * Stops supply of power to the SCE. + * + * @param[in] p_ctrl Pointer to control structure. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * + * @note The pre-run state is any state. + * After the function runs the state transitions to SCE Disabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_Close (sce_ctrl_t * const p_ctrl) +{ + sce_instance_ctrl_t * p_instance_ctrl = (sce_instance_ctrl_t *) p_ctrl; + +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); +#endif + + p_instance_ctrl->open = 0; + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Casting structure pointer is used for address. */ + MSTP_SECURITY = 1U; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Software reset to SCE. + * + * Reverts the state to the SCE initial state. + * + * @retval FSP_SUCCESS Normal termination + * + * @note The pre-run state is any state. + * After the function runs the state transitions to SCE Disabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SoftwareReset (void) +{ + R_SCE_SoftwareResetSub(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This API can generate 4 words random number. + * + * @param[in,out] random Stores 4words (16 bytes) random data. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RandomNumberGenerate (uint32_t * random) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(random); +#endif + + return R_SCE_GenerateRandomNumberSub(random); +} + +/*******************************************************************************************************************//** + * This API outputs 128-bit AES wrapped key from a random number. + * + * This API generates a wrapped key from a random number in the SCE. Accordingly, user key input is unnecessary. + * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented. + * + * @param[in,out] wrapped_key 128-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Disabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128_WrappedKeyGenerate (sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + error_code = R_SCE_GenerateAes128RandomKeyIndexSub(wrapped_key->value); + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_AES128; + } + else if (FSP_SUCCESS == FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + else + { + /* not used */ + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API outputs 256-bit AES wrapped key from a random number. + * + * This API generates a wrapped key from a random number in the SCE. Accordingly, user key input is unnecessary. + * By encrypting data using the wrapped key is output by this API, dead copying of data can be prevented. + * + * @param[in,out] wrapped_key 256-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Disabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256_WrappedKeyGenerate (sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + error_code = R_SCE_GenerateAes256RandomKeyIndexSub(wrapped_key->value); + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_AES256; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 128-bit AES key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 128-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128_EncryptedKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_AES128; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_AES128; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 256-bit AES key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 256-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256_EncryptedKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_AES256; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_AES256; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 128-bit AES key within the user routine. + * @param[in] master_key AES-128 key used for wrapping. + * @param[in] target_key_type Selects key to be wrapped. + * @param[in] target_key Key to be wrapped. + * @param[out] rfc3394_wrapped_key Wrapped key. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128_RFC3394KeyWrap (sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, + uint32_t * rfc3394_wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(master_key); + FSP_ASSERT(target_key); + FSP_ASSERT(rfc3394_wrapped_key); +#endif + + return R_SCE_Aes128KeyWrapPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &master_key->value, + &target_key_type, + (uint32_t *) &target_key->value, + rfc3394_wrapped_key); +} + +/*******************************************************************************************************************//** + * This API wraps 256-bit AES key within the user routine. + * @param[in] master_key AES-256 key used for wrapping. + * @param[in] target_key_type Selects key to be wrapped. + * @param[in] target_key Key to be wrapped. + * @param[out] rfc3394_wrapped_key Wrapped key. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256_RFC3394KeyWrap (sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, + uint32_t * rfc3394_wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(master_key); + FSP_ASSERT(target_key); + FSP_ASSERT(rfc3394_wrapped_key); +#endif + + return R_SCE_Aes256KeyWrapPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &master_key->value, + &target_key_type, + (uint32_t *) &target_key->value, + rfc3394_wrapped_key); +} + +/*******************************************************************************************************************//** + * This API unwraps 128-bit AES key within the user routine. + * @param[in] master_key AES-128 key used for unwrapping. + * @param[in] target_key_type Selects key to be unwrapped. + * @param[in] rfc3394_wrapped_key Wrapped key. + * @param[out] target_key Key to be unwrapped. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128_RFC3394KeyUnwrap (sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, + sce_aes_wrapped_key_t * target_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(master_key); + FSP_ASSERT(rfc3394_wrapped_key); + FSP_ASSERT(target_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + + error_code = R_SCE_Aes128KeyUnWrapPrivate(master_key, &target_key_type, rfc3394_wrapped_key, target_key->value); + if (FSP_SUCCESS == error_code) + { + if (SCE_KEYWRAP_AES128 == target_key_type) + { + target_key->type = SCE_KEY_INDEX_TYPE_AES128; + } + else /* if (SCE_KEYWRAP_AES128 == target_key_type) */ + { + target_key->type = SCE_KEY_INDEX_TYPE_AES256; + } + } + else + { + target_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API unwraps 256-bit AES key within the user routine. + * @param[in] master_key AES-256 key used for unwrapping. + * @param[in] target_key_type Selects key to be unwrapped. + * @param[in] rfc3394_wrapped_key Wrapped key. + * @param[out] target_key Key to be unwrapped. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256_RFC3394KeyUnwrap (sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, + sce_aes_wrapped_key_t * target_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(master_key); + FSP_ASSERT(rfc3394_wrapped_key); + FSP_ASSERT(target_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + + error_code = R_SCE_Aes256KeyUnWrapPrivate(master_key, &target_key_type, rfc3394_wrapped_key, target_key->value); + if (FSP_SUCCESS == error_code) + { + if (SCE_KEYWRAP_AES128 == target_key_type) + { + target_key->type = SCE_KEY_INDEX_TYPE_AES128; + } + else /* if (SCE_KEYWRAP_AES128 == target_key_type) */ + { + target_key->type = SCE_KEY_INDEX_TYPE_AES256; + } + } + else + { + target_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps HMAC-SHA256 key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key HMAC-SHA256 wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256HMAC_EncryptedKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_hmac_sha_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_HMAC_SHA256; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA256; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API outputs a wrapped key pair for a 1024-bit RSA public key and private key pair. These keys are generated + * from a random value produced internally by the SCE. Consequently, there is no need to input a user key. + * Dead copying of data can be prevented by encrypting the data using the wrapped key output by this API. + * A public wrapped key is generated by wrapped_pair_key->pub_key, and a private wrapped key is generated by + * wrapped_pair_key->priv_key. As the public key exponent, only 0x00010001 is generated. + * + * @param [in,out] wrapped_pair_key User key index for RSA 1024-bit public key and private key pair + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. Key generation failed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA1024_WrappedKeyPairGenerate (sce_rsa1024_wrapped_pair_key_t * wrapped_pair_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(wrapped_pair_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + error_code = R_SCE_GenerateRsa1024RandomKeyIndexSub(SCE_RSA_RETRY_COUNT_FOR_RSA_KEY_GENERATION, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_pair_key->pub_key.value, + (uint32_t *) &wrapped_pair_key->priv_key.value); + if (FSP_SUCCESS == error_code) + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_RSA1024_PUBLIC; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_RSA1024_PRIVATE; + } + else + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_INVALID; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API outputs a wrapped key pair for a 2048-bit RSA public key and private key pair. These keys are generated + * from a random value produced internally by the SCE. Consequently, there is no need to input a user key. + * Dead copying of data can be prevented by encrypting the data using the wrapped key output by this API. + * A public wrapped key is generated by wrapped_pair_key->pub_key, and a private wrapped key is generated by + * wrapped_pair_key->priv_key. As the public key exponent, only 0x00010001 is generated. + * + * @param [in,out] wrapped_pair_key User key index for RSA 2048-bit public key and private key pair + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. Key generation failed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA2048_WrappedKeyPairGenerate (sce_rsa2048_wrapped_pair_key_t * wrapped_pair_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(wrapped_pair_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + error_code = R_SCE_GenerateRsa2048RandomKeyIndexSub(SCE_RSA_RETRY_COUNT_FOR_RSA_KEY_GENERATION, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_pair_key->pub_key.value, + (uint32_t *) &wrapped_pair_key->priv_key.value); + if (FSP_SUCCESS == error_code) + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_RSA2048_PUBLIC; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_RSA2048_PRIVATE; + } + else + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_INVALID; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 1024-bit RSA public key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 1024-bit RSA public wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA1024_EncryptedPublicKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA1024_PUBLIC; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_RSA1024_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 1024-bit RSA private key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 1024-bit RSA private wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA1024_EncryptedPrivateKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA1024_PRIVATE; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_RSA1024_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 2048-bit RSA public key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 1024-bit RSA public wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA2048_EncryptedPublicKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA2048_PUBLIC; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_RSA2048_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 2048-bit RSA private key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 2048-bit RSA private wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA2048_EncryptedPrivateKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA2048_PRIVATE; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_RSA2048_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 3072-bit RSA public key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 3072-bit RSA public wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA3072_EncryptedPublicKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa3072_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA3072_PUBLIC; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_RSA3072_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 4096-bit RSA public key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 1024-bit RSA public wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA4096_EncryptedPublicKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa4096_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_RSA4096_PUBLIC; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This is an API for outputting a wrapped key pair for secp192r1 public key and private key pair. These keys are generated + * from a random number value internally within the SCE. + * There is therefore no need to input user keys. It is possible to prevent dead copying of data by using the + * wrapped key output by this API to encrypt the data. The public key index is generated in wrapped_pair_key->pub_key, + * and the private key index is generated in wrapped_pair_key->priv_key. + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp192r1 public key and private key pair + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp192r1_WrappedKeyPairGenerate (sce_ecc_wrapped_pair_key_t * wrapped_pair_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(wrapped_pair_key); +#endif + + uint32_t indata_cmd; + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + + indata_cmd = change_endian_long(SCE_ECC_KEY_LENGTH_192); + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_GenerateEccRandomKeyIndexSub(&curvetype, + /* Casting uint32_t pointer is used for address. */ + &indata_cmd, + (uint32_t *) &wrapped_pair_key->pub_key.value, + (uint32_t *) &wrapped_pair_key->priv_key.value); + if (FSP_SUCCESS == error_code) + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_ECC_P192_PUBLIC; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_ECC_P192_PRIVATE; + } + else + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_INVALID; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This is an API for outputting a wrapped key pair for secp224r1 public key and private key pair. These keys are generated + * from a random number value internally within the SCE. + * There is therefore no need to input user keys. It is possible to prevent dead copying of data by using the + * wrapped key output by this API to encrypt the data. The public key index is generated in wrapped_pair_key->pub_key, + * and the private key index is generated in wrapped_pair_key->priv_key. + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp224r1 public key and private key pair + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp224r1_WrappedKeyPairGenerate (sce_ecc_wrapped_pair_key_t * wrapped_pair_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(wrapped_pair_key); +#endif + + uint32_t indata_cmd; + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + + indata_cmd = change_endian_long(SCE_ECC_KEY_LENGTH_224); + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_GenerateEccRandomKeyIndexSub(&curvetype, + /* Casting uint32_t pointer is used for address. */ + &indata_cmd, + (uint32_t *) &wrapped_pair_key->pub_key.value, + (uint32_t *) &wrapped_pair_key->priv_key.value); + if (FSP_SUCCESS == error_code) + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_ECC_P224_PUBLIC; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE; + } + else + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_INVALID; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This is an API for outputting a wrapped key pair for secp256r1 public key and private key pair. These keys are generated + * from a random number value internally within the SCE. + * There is therefore no need to input user keys. It is possible to prevent dead copying of data by using the + * wrapped key output by this API to encrypt the data. The public key index is generated in wrapped_pair_key->pub_key, + * and the private key index is generated in wrapped_pair_key->priv_key. + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp256r1 public key and private key pair + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp256r1_WrappedKeyPairGenerate (sce_ecc_wrapped_pair_key_t * wrapped_pair_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(wrapped_pair_key); +#endif + + uint32_t indata_cmd; + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + + indata_cmd = change_endian_long(SCE_ECC_KEY_LENGTH_256); + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_GenerateEccRandomKeyIndexSub(&curvetype, + /* Casting uint32_t pointer is used for address. */ + &indata_cmd, + (uint32_t *) &wrapped_pair_key->pub_key.value, + (uint32_t *) &wrapped_pair_key->priv_key.value); + if (FSP_SUCCESS == error_code) + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE; + } + else + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_INVALID; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This is an API for outputting a wrapped key pair for secp384r1 public key and private key pair. These keys are generated + * from a random number value internally within the SCE. + * There is therefore no need to input user keys. It is possible to prevent dead copying of data by using the + * wrapped key output by this API to encrypt the data. The public key index is generated in wrapped_pair_key->pub_key, + * and the private key index is generated in wrapped_pair_key->priv_key. + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp384r1 public key and private key pair + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp384r1_WrappedKeyPairGenerate (sce_ecc_wrapped_pair_key_t * wrapped_pair_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(wrapped_pair_key); +#endif + + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_GenerateEccP384RandomKeyIndexSub( + /* Casting uint32_t pointer is used for address. */ + &curvetype, + (uint32_t *) &wrapped_pair_key->pub_key.value, + (uint32_t *) &wrapped_pair_key->priv_key.value); + if (FSP_SUCCESS == error_code) + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE; + } + else + { + wrapped_pair_key->pub_key.type = SCE_KEY_INDEX_TYPE_INVALID; + wrapped_pair_key->priv_key.type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps secp192r1 public key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp192r1 public wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp192r1_EncryptedPublicKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P192_PUBLIC; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P192_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps secp224r1 public key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp224r1 public wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp224r1_EncryptedPublicKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P224_PUBLIC; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P224_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps secp256r1 public key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp256r1 public wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P256_PUBLIC; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps secp384r1 public key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp384r1 public wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P384_PUBLIC; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps secp192r1 private key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp192r1 private wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp192r1_EncryptedPrivateKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P192_PRIVATE; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P192_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps secp224r1 private key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp224r1 private wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp224r1_EncryptedPrivateKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P224_PRIVATE; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps secp256r1 private key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp256r1 private wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P256_PRIVATE; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps secp384r1 private key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp384r1 private wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap (uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(key_update_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + sce_oem_cmd_t key_type = SCE_OEM_CMD_ECC_P384_PRIVATE; + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = R_SCE_UpdateOemKeyIndexPrivate(key_type, + initial_vector, + encrypted_key, + (uint32_t *) &wrapped_key->value); + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * Generate TLS RSA Public key index data + * + * @param[in] encrypted_provisioning_key the provisioning key includes encrypted CBC/CBC-MAC key for user key + * @param[in] initial_vector the initial_vector for user key CBC encrypt + * @param[in] encrypted_key the user key encrypted with AES128-ECB mode + * @param[out] wrapped_key the user Key Generation Information (141 words) of RSA2048 bit + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_RootCertificateRSA2048PublicKeyInstall ( + uint8_t * encrypted_provisioning_key, + uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_tls_ca_certification_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(encrypted_provisioning_key); + FSP_ASSERT(initial_vector); + FSP_ASSERT(encrypted_key); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + uint32_t install_key_ring_index = SCE_INSTALL_KEY_RING_INDEX; + error_code = R_SCE_GenerateTlsRsaInstallDataSub(&install_key_ring_index, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) encrypted_provisioning_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + wrapped_key->value); + if (FSP_SUCCESS == error_code) + { + memcpy(S_INST, wrapped_key->value, sizeof(wrapped_key->value)); + wrapped_key->type = SCE_KEY_INDEX_TYPE_TLS_CA_CERTIFICATION_PUBLIC_KEY; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * Generate TLS ECC key pair + * + * @param[in] tls_p256_ecc_wrapped_key P256 ECC key index for TLS + * @param[in] ephemeral_ecdh_public_key ephemeral ECDH public key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate ( + sce_tls_p256_ecc_wrapped_key_t * tls_p256_ecc_wrapped_key, + uint8_t * ephemeral_ecdh_public_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(tls_p256_ecc_wrapped_key); + FSP_ASSERT(ephemeral_ecdh_public_key); +#endif + + fsp_err_t error_code = FSP_SUCCESS; + error_code = R_SCE_GenerateTlsP256EccKeyIndexSub(tls_p256_ecc_wrapped_key->value, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) ephemeral_ecdh_public_key); + if (FSP_SUCCESS == error_code) + { + tls_p256_ecc_wrapped_key->type = SCE_KEY_INDEX_TYPE_TLS_P256_ECC_KEY; + } + else + { + tls_p256_ecc_wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This API Loads Hardware Unique Key. + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL self-test1 fail + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +fsp_err_t R_SCE_LoadHukPrivate (void) +{ + uint32_t LC[1]; + LC[0] = R_PSCU->DLMMON; + + return R_SCE_LoadHukSub(LC); +} + +/*******************************************************************************************************************//** + * Self check No1 + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL self-test1 fail + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +fsp_err_t R_SCE_SelfCheck1Private (void) +{ + return R_SCE_SelfCheck1Sub(); +} + +/*******************************************************************************************************************//** + * Self check No2 + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RETRY self-test2 fail + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +fsp_err_t R_SCE_SelfCheck2Private (void) +{ + return R_SCE_SelfCheck2Sub(); +} + +/*******************************************************************************************************************//** + * Self check No3 + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RETRY self-test3 fail + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +fsp_err_t R_SCE_SelfCheck3Private (void) +{ + return R_SCE_SelfCheck3Sub(); +} + +/*******************************************************************************************************************//** + * Firmware integrity check + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +fsp_err_t R_SCE_FwIntegrityCheckPrivate (void) +{ + return R_SCE_FwIntegrityCheckSub(); +} + +/*******************************************************************************************************************//** + * This API Updates OEM key index (wrapped key). + * + * @retval FSP_SUCCESS + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT + * @retval FSP_ERR_CRYPTO_SCE_FAIL + **********************************************************************************************************************/ +fsp_err_t R_SCE_UpdateOemKeyIndexPrivate (sce_oem_cmd_t key_type, + uint8_t * iv, + uint8_t * encrypted_oem_key, + uint32_t * key_index) +{ + fsp_err_t error_code = FSP_SUCCESS; + uint32_t CMD[1] = {0}; + uint32_t LC[1] = {0}; + CMD[0] = key_type; + LC[0] = R_PSCU->DLMMON; + + INST_DATA_SIZE = sce_oem_key_size[key_type]; + + error_code = R_SCE_UpdateOemKeyIndexSub(LC, CMD, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + + return error_code; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c new file mode 100644 index 0000000000..667bff3e6d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c @@ -0,0 +1,4438 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sce_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* GCM related */ +#define GCM_IV_MAX_BYTE_SIZE (12) +#define GCM_INPUT_DATA_TEXT (1) +#define GCM_INPUT_DATA_AAD (0) + +/* Initialization function call state */ +#define CALL_ONLY_INIT (0) +#define CALL_ONLY_UPDATE_FINAL (1) + +/* Magic numbers */ +#ifndef SCE_HEX_E000000 + #define SCE_HEX_E000000 0xe000000U +#endif +#ifndef SCE_DEC_110 + #define SCE_DEC_110 110 +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static fsp_err_t prepare_gcm_iv(uint8_t * initial_vector, + uint32_t initial_vector_length, + sce_aes_wrapped_key_t * wrapped_key, + uint32_t wrapped_key_word_size, + uint32_t * hashed_ivec); +static void aes_ccm_b_counter_formatter(uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len, + uint8_t * counter, + uint8_t * formatted_data, + uint32_t * formatted_length); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern uint32_t g_private_id_counter; +uint32_t g_aes128ecbenc_private_id; +uint32_t g_aes128ecbdec_private_id; +uint32_t g_aes256ecbenc_private_id; +uint32_t g_aes256ecbdec_private_id; +uint32_t g_aes128cbcenc_private_id; +uint32_t g_aes128cbcdec_private_id; +uint32_t g_aes256cbcenc_private_id; +uint32_t g_aes256cbcdec_private_id; +uint32_t g_aes128cmacgen_private_id; +uint32_t g_aes128cmacver_private_id; +uint32_t g_aes256cmacgen_private_id; +uint32_t g_aes256cmacver_private_id; +uint32_t g_aes128gcmenc_private_id; +uint32_t g_aes128gcmdec_private_id; +uint32_t g_aes256gcmenc_private_id; +uint32_t g_aes256gcmdec_private_id; +uint32_t g_aes128ccmenc_private_id; +uint32_t g_aes128ccmdec_private_id; +uint32_t g_aes256ccmenc_private_id; +uint32_t g_aes256ccmdec_private_id; + +/*******************************************************************************************************************//** + * @addtogroup SCE_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * The R_SCE_AES128ECB_EncryptInit() function performs preparations for the execution of an AES calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument + * in the subsequent R_SCE_AES128ECB_EncryptUpdate() function and R_SCE_AES128ECB_EncryptFinal() function. + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal wrapped key. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128ECB_EncryptInit (sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + + memset(handle, 0, sizeof(sce_aes_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128ecbenc_private_id = g_private_id_counter; + handle->id = g_aes128ecbenc_private_id; + + return R_SCE_Aes128EcbEncryptInitPrivate(wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128ECB_EncryptUpdate() function encrypts the second argument, plain, utilizing the key index stored + * in the handle specified in the first argument, handle, and writes the ongoing status to this first argument. + * In addition, it writes the encryption result to the third argument, cipher. After plaintext input is completed, + * call R_SCE_AES128ECB_EncryptFinal(). + * + * Specify areas for plain and cipher that do not overlap. For plain and cipher, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128ECB_EncryptUpdate (sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(cipher); + FSP_ERROR_RETURN(!(plain_length & 0xF), FSP_ERR_CRYPTO_SCE_PARAMETER); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128ecbenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + memcpy(handle->last_1_block_as_fraction, + (plain + (plain_length / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE), + (plain_length % HW_SCE_AES_BLOCK_BYTE_SIZE)); + handle->current_input_data_size = plain_length; + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes128EcbEncryptUpdatePrivate((uint32_t *) (plain), (uint32_t *) (cipher), plain_length >> 2); +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_AES128ECB_EncryptFinal() function writes + * the calculation result to the second argument, cipher, and writes the length of the calculation result + * to the third argument, cipher_length. The original intent was for a portion of the encryption + * result that was not a multiple of 16 bytes to be written to the second argument. + * However, as a result of the restriction that only multiples of 16 can be input to the Update function, + * nothing is ever written to cipher, and 0 is always written to cipher_length. The arguments cipher and cipher_length + * are provided for compatibility in anticipation of the time when this restriction is lifted. + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128ECB_EncryptFinal (sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher_length); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128ecbenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + *cipher_length = 0; + memset(handle, 0, sizeof(sce_aes_handle_t)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes128EcbEncryptFinalPrivate((uint32_t *) (cipher), cipher_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128ECB_DecryptInit() function performs preparations for the execution of an AES calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument + * in the subsequent R_SCE_AES128ECB_DecryptUpdate() function and R_SCE_AES128ECB_DecryptFinal() function. + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal wrapped key. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128ECB_DecryptInit (sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + + memset(handle, 0, sizeof(sce_aes_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128ecbdec_private_id = g_private_id_counter; + handle->id = g_aes128ecbdec_private_id; + + return R_SCE_Aes128EcbDecryptInitPrivate(wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128ECB_DecryptUpdate() function decrypts the second argument, cipher, utilizing the key index stored + * in the handle specified in the first argument, handle, and writes the ongoing status to this first argument. + * In addition, it writes the decryption result to the third argument, plain. After plaintext input is completed, + * call R_SCE_AES128ECB_DecryptFinal(). + * + * Specify areas for plain and cipher that do not overlap. For plain and cipher, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128ECB_DecryptUpdate (sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(plain); + FSP_ERROR_RETURN(!(cipher_length & 0xF), FSP_ERR_CRYPTO_SCE_PARAMETER); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128ecbdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->current_input_data_size = cipher_length; + memcpy(handle->last_1_block_as_fraction, + (cipher + (cipher_length / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE), + (cipher_length % HW_SCE_AES_BLOCK_BYTE_SIZE)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes128EcbDecryptUpdatePrivate((uint32_t *) (cipher), (uint32_t *) (plain), cipher_length >> 2); +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_AES128ECB_DecryptFinal() function writes + * the calculation result to the second argument, plain, and writes the length of the calculation result + * to the third argument, plain_length. The original intent was for a portion of the decryption + * result that was not a multiple of 16 bytes to be written to the second argument. + * However, as a result of the restriction that only multiples of 16 can be input to the Update function, + * nothing is ever written to plain, and 0 is always written to plain_length. The arguments plain and plain_length + * are provided for compatibility in anticipation of the time when this restriction is lifted. + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128ECB_DecryptFinal (sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(plain_length); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128ecbdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + *plain_length = 0; + memset(handle, 0, sizeof(sce_aes_handle_t)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes128EcbDecryptFinalPrivate((uint32_t *) (plain), plain_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256ECB_EncryptInit() function performs preparations for the execution of an AES calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument + * in the subsequent R_SCE_AES256ECB_EncryptUpdate() function and R_SCE_AES256ECB_EncryptFinal() function. + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal wrapped key. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256ECB_EncryptInit (sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + + memset(handle, 0, sizeof(sce_aes_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256ecbenc_private_id = g_private_id_counter; + handle->id = g_aes256ecbenc_private_id; + + return R_SCE_Aes256EcbEncryptInitPrivate(wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256ECB_EncryptUpdate() function encrypts the second argument, plain, utilizing the key index stored + * in the handle specified in the first argument, handle, and writes the ongoing status to this first argument. + * In addition, it writes the encryption result to the third argument, cipher. After plaintext input is completed, + * call R_SCE_AES256ECB_EncryptFinal(). + * + * Specify areas for plain and cipher that do not overlap. For plain and cipher, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256ECB_EncryptUpdate (sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(cipher); + FSP_ERROR_RETURN(!(plain_length & 0xF), FSP_ERR_CRYPTO_SCE_PARAMETER); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256ecbenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->current_input_data_size = plain_length; + memcpy(handle->last_1_block_as_fraction, + (plain + (plain_length / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE), + (plain_length % HW_SCE_AES_BLOCK_BYTE_SIZE)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes256EcbEncryptUpdatePrivate((uint32_t *) (plain), (uint32_t *) (cipher), plain_length >> 2); +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_AES256ECB_EncryptFinal() function writes + * the calculation result to the second argument, cipher, and writes the length of the calculation result + * to the third argument, cipher_length. The original intent was for a portion of the encryption + * result that was not a multiple of 16 bytes to be written to the second argument. + * However, as a result of the restriction that only multiples of 16 can be input to the Update function, + * nothing is ever written to cipher, and 0 is always written to cipher_length. The arguments cipher and cipher_length + * are provided for compatibility in anticipation of the time when this restriction is lifted. + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256ECB_EncryptFinal (sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher_length); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256ecbenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + *cipher_length = 0; + memset(handle, 0, sizeof(sce_aes_handle_t)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes256EcbEncryptFinalPrivate((uint32_t *) (cipher), cipher_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128ECB_DecryptInit() function performs preparations for the execution of an AES calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument + * in the subsequent R_SCE_AES128ECB_DecryptUpdate() function and R_SCE_AES128ECB_DecryptFinal() function. + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal wrapped key. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256ECB_DecryptInit (sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + + memset(handle, 0, sizeof(sce_aes_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256ecbdec_private_id = g_private_id_counter; + handle->id = g_aes256ecbdec_private_id; + + return R_SCE_Aes256EcbDecryptInitPrivate(wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256ECB_DecryptUpdate() function decrypts the second argument, cipher, utilizing the key index stored + * in the handle specified in the first argument, handle, and writes the ongoing status to this first argument. + * In addition, it writes the decryption result to the third argument, plain. After plaintext input is completed, + * call R_SCE_AES256ECB_DecryptFinal(). + * + * Specify areas for plain and cipher that do not overlap. For plain and cipher, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256ECB_DecryptUpdate (sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(plain); + FSP_ERROR_RETURN(!(cipher_length & 0xF), FSP_ERR_CRYPTO_SCE_PARAMETER); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256ecbdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->current_input_data_size = cipher_length; + memcpy(handle->last_1_block_as_fraction, + (cipher + (cipher_length / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE), + (cipher_length % HW_SCE_AES_BLOCK_BYTE_SIZE)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes256EcbDecryptUpdatePrivate((uint32_t *) (cipher), (uint32_t *) (plain), cipher_length >> 2); +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_AES256ECB_DecryptFinal() function writes + * the calculation result to the second argument, plain, and writes the length of the calculation result + * to the third argument, plain_length. The original intent was for a portion of the decryption + * result that was not a multiple of 16 bytes to be written to the second argument. + * However, as a result of the restriction that only multiples of 16 can be input to the Update function, + * nothing is ever written to plain, and 0 is always written to plain_length. The arguments plain and plain_length + * are provided for compatibility in anticipation of the time when this restriction is lifted. + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256ECB_DecryptFinal (sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(plain_length); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256ecbdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + *plain_length = 0; + memset(handle, 0, sizeof(sce_aes_handle_t)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes256EcbDecryptFinalPrivate((uint32_t *) (plain), plain_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CBC_EncryptInit() function performs preparations for the execution of an AES calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument + * in the subsequent R_SCE_AES128CBC_EncryptUpdate() function and R_SCE_AES128CBC_EncryptFinal() function. + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initialization vector area (16byte) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal wrapped key. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CBC_EncryptInit (sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(initial_vector); +#endif + + memset(handle, 0, sizeof(sce_aes_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128cbcenc_private_id = g_private_id_counter; + handle->id = g_aes128cbcenc_private_id; + memcpy(handle->current_initial_vector, initial_vector, sizeof(handle->current_initial_vector)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes128CbcEncryptInitPrivate(wrapped_key, (uint32_t *) (initial_vector)); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CBC_EncryptUpdate() function encrypts the second argument, plain, utilizing the key index stored + * in the handle specified in the first argument, handle, and writes the ongoing status to this first argument. + * In addition, it writes the encryption result to the third argument, cipher. After plaintext input is completed, + * call R_SCE_AES128CBC_EncryptFinal(). + * + * Specify areas for plain and cipher that do not overlap. For plain and cipher, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CBC_EncryptUpdate (sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(cipher); + FSP_ERROR_RETURN(!(plain_length & 0xF), FSP_ERR_CRYPTO_SCE_PARAMETER); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128cbcenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->current_input_data_size = plain_length; + memcpy(handle->last_1_block_as_fraction, + (plain + (plain_length / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE), + (plain_length % HW_SCE_AES_BLOCK_BYTE_SIZE)); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes128CbcEncryptUpdatePrivate((uint32_t *) (plain), (uint32_t *) (cipher), plain_length >> 2); + memcpy(handle->current_initial_vector, + (cipher + (plain_length - HW_SCE_AES_BLOCK_BYTE_SIZE)), + HW_SCE_AES_CBC_IV_BYTE_SIZE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_AES128CBC_EncryptFinal() function writes + * the calculation result to the second argument, cipher, and writes the length of the calculation result + * to the third argument, cipher_length. The original intent was for a portion of the encryption + * result that was not a multiple of 16 bytes to be written to the second argument. + * However, as a result of the restriction that only multiples of 16 can be input to the Update function, + * nothing is ever written to cipher, and 0 is always written to cipher_length. The arguments cipher and cipher_length + * are provided for compatibility in anticipation of the time when this restriction is lifted. + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CBC_EncryptFinal (sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher_length); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128cbcenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + *cipher_length = 0; + memset(handle, 0, sizeof(sce_aes_handle_t)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes128CbcEncryptFinalPrivate((uint32_t *) (cipher), cipher_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CBC_DecryptInit() function performs preparations for the execution of an AES calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument + * in the subsequent R_SCE_AES128CBC_DecryptUpdate() function and R_SCE_AES128CBC_DecryptFinal() function. + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initialization vector area (16byte) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal wrapped key. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CBC_DecryptInit (sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(initial_vector); +#endif + + memset(handle, 0, sizeof(sce_aes_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128cbcdec_private_id = g_private_id_counter; + handle->id = g_aes128cbcdec_private_id; + memcpy(handle->current_initial_vector, initial_vector, sizeof(handle->current_initial_vector)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes128CbcDecryptInitPrivate(wrapped_key, (uint32_t *) (handle->current_initial_vector)); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CBC_DecryptUpdate() function decrypts the second argument, cipher, utilizing the key index stored + * in the handle specified in the first argument, handle, and writes the ongoing status to this first argument. + * In addition, it writes the decryption result to the third argument, plain. After plaintext input is completed, + * call R_SCE_AES128CBC_DecryptFinal(). + * + * Specify areas for plain and cipher that do not overlap. For plain and cipher, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CBC_DecryptUpdate (sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(plain); + FSP_ERROR_RETURN(!(cipher_length & 0xF), FSP_ERR_CRYPTO_SCE_PARAMETER); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128cbcdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->current_input_data_size = cipher_length; + memcpy(handle->last_1_block_as_fraction, + (cipher + (cipher_length / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE), + (cipher_length % HW_SCE_AES_BLOCK_BYTE_SIZE)); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes128CbcDecryptUpdatePrivate((uint32_t *) (cipher), (uint32_t *) (plain), cipher_length >> 2); + memcpy(handle->current_initial_vector, + (plain + (cipher_length - HW_SCE_AES_BLOCK_BYTE_SIZE)), + HW_SCE_AES_CBC_IV_BYTE_SIZE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_AES128CBC_DecryptFinal() function writes + * the calculation result to the second argument, plain, and writes the length of the calculation result + * to the third argument, plain_length. The original intent was for a portion of the decryption + * result that was not a multiple of 16 bytes to be written to the second argument. + * However, as a result of the restriction that only multiples of 16 can be input to the Update function, + * nothing is ever written to plain, and 0 is always written to plain_length. The arguments plain and plain_length + * are provided for compatibility in anticipation of the time when this restriction is lifted. + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CBC_DecryptFinal (sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(plain_length); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128cbcdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + *plain_length = 0; + memset(handle, 0, sizeof(sce_aes_handle_t)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes128CbcDecryptFinalPrivate((uint32_t *) (plain), plain_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CBC_EncryptInit() function performs preparations for the execution of an AES calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument + * in the subsequent R_SCE_AES256CBC_EncryptUpdate() function and R_SCE_AES256CBC_EncryptFinal() function. + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal wrapped key. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CBC_EncryptInit (sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(initial_vector); +#endif + + memset(handle, 0, sizeof(sce_aes_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256cbcenc_private_id = g_private_id_counter; + handle->id = g_aes256cbcenc_private_id; + memcpy(handle->current_initial_vector, initial_vector, sizeof(handle->current_initial_vector)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes256CbcEncryptInitPrivate(wrapped_key, (uint32_t *) (handle->current_initial_vector)); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CBC_EncryptUpdate() function encrypts the second argument, plain, utilizing the key index stored + * in the handle specified in the first argument, handle, and writes the ongoing status to this first argument. + * In addition, it writes the encryption result to the third argument, cipher. After plaintext input is completed, + * call R_SCE_AES256CBC_EncryptFinal(). + * + * Specify areas for plain and cipher that do not overlap. For plain and cipher, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CBC_EncryptUpdate (sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(cipher); + FSP_ERROR_RETURN(!(plain_length & 0xF), FSP_ERR_CRYPTO_SCE_PARAMETER); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256cbcenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->current_input_data_size = plain_length; + memcpy(handle->last_1_block_as_fraction, + (plain + (plain_length / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE), + (plain_length % HW_SCE_AES_BLOCK_BYTE_SIZE)); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes256CbcEncryptUpdatePrivate((uint32_t *) (plain), (uint32_t *) (cipher), plain_length >> 2); + memcpy(handle->current_initial_vector, + cipher + (plain_length - HW_SCE_AES_BLOCK_BYTE_SIZE), + HW_SCE_AES_CBC_IV_BYTE_SIZE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_AES256CBC_EncryptFinal() function writes + * the calculation result to the second argument, cipher, and writes the length of the calculation result + * to the third argument, cipher_length. The original intent was for a portion of the encryption + * result that was not a multiple of 16 bytes to be written to the second argument. + * However, as a result of the restriction that only multiples of 16 can be input to the Update function, + * nothing is ever written to cipher, and 0 is always written to cipher_length. The arguments cipher and cipher_length + * are provided for compatibility in anticipation of the time when this restriction is lifted. + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CBC_EncryptFinal (sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher_length); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256cbcenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + *cipher_length = 0; + memset(handle, 0, sizeof(sce_aes_handle_t)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes256CbcEncryptFinalPrivate((uint32_t *) (cipher), cipher_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CBC_DecryptInit() function performs preparations for the execution of an AES calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument + * in the subsequent R_SCE_AES256CBC_DecryptUpdate() function and R_SCE_AES256CBC_DecryptFinal() function. + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initialization vector area (16byte) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal wrapped key. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CBC_DecryptInit (sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(initial_vector); +#endif + + memset(handle, 0, sizeof(sce_aes_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256cbcdec_private_id = g_private_id_counter; + handle->id = g_aes256cbcdec_private_id; + memcpy(handle->current_initial_vector, initial_vector, sizeof(handle->current_initial_vector)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes256CbcDecryptInitPrivate(wrapped_key, (uint32_t *) (handle->current_initial_vector)); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CBC_DecryptUpdate() function decrypts the second argument, cipher, utilizing the key index stored + * in the handle specified in the first argument, handle, and writes the ongoing status to this first argument. + * In addition, it writes the decryption result to the third argument, plain. After plaintext input is completed, + * call R_SCE_AES256CBC_DecryptFinal(). + * + * Specify areas for plain and cipher that do not overlap. For plain and cipher, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CBC_DecryptUpdate (sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(plain); + FSP_ERROR_RETURN(!(cipher_length & 0xF), FSP_ERR_CRYPTO_SCE_PARAMETER); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256cbcdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->current_input_data_size = cipher_length; + memcpy(handle->last_1_block_as_fraction, + (cipher + (cipher_length / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE), + (cipher_length % HW_SCE_AES_BLOCK_BYTE_SIZE)); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes256CbcDecryptUpdatePrivate((uint32_t *) (cipher), (uint32_t *) (plain), cipher_length >> 2); + memcpy(handle->current_initial_vector, + plain + (cipher_length - HW_SCE_AES_BLOCK_BYTE_SIZE), + HW_SCE_AES_CBC_IV_BYTE_SIZE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_AES256CBC_DecryptFinal() function writes + * the calculation result to the second argument, plain, and writes the length of the calculation result + * to the third argument, plain_length. The original intent was for a portion of the decryption + * result that was not a multiple of 16 bytes to be written to the second argument. + * However, as a result of the restriction that only multiples of 16 can be input to the Update function, + * nothing is ever written to plain, and 0 is always written to plain_length. The arguments plain and plain_length + * are provided for compatibility in anticipation of the time when this restriction is lifted. + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CBC_DecryptFinal (sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(plain_length); +#endif + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256cbcdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + *plain_length = 0; + memset(handle, 0, sizeof(sce_aes_handle_t)); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_Aes256CbcDecryptFinalPrivate((uint32_t *) (plain), plain_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128GCM_EncryptInit() function performs preparations for the execution of an GCM calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument in the subsequent + * R_SCE_AES128GCM_EncryptUpdate() function and R_SCE_AES128GCM_EncryptFinal() function. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128GCM_EncryptInit (sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(initial_vector); +#endif + + uint32_t hashed_ivec[4] = + { + 0 + }; + fsp_err_t ercd = FSP_SUCCESS; + + if ((SCE_KEY_INDEX_TYPE_AES128 == wrapped_key->type) || (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == wrapped_key->type)) + { + if (0 == initial_vector_length) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + } + else + { + if (SCE_KEY_INDEX_TYPE_AES128_FOR_TLS != wrapped_key->type) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + } + + memset(handle, 0, sizeof(sce_gcm_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128gcmenc_private_id = g_private_id_counter; + handle->id = g_aes128gcmenc_private_id; + if ((SCE_KEY_INDEX_TYPE_AES128 == wrapped_key->type) || (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == wrapped_key->type)) + { + ercd = prepare_gcm_iv(initial_vector, + initial_vector_length, + wrapped_key, + HW_SCE_AES128_KEY_INDEX_WORD_SIZE, + hashed_ivec); + if (FSP_SUCCESS != ercd) + { + memset(handle, 0, sizeof(sce_gcm_handle_t)); + + return ercd; + } + } + + handle->flag_update_input_data = GCM_INPUT_DATA_AAD; + + return R_SCE_Aes128GcmEncryptInitPrivate(wrapped_key, hashed_ivec); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128GCM_EncryptUpdate() function encrypts the plaintext specified in the second argument, plain, + * in GCM mode using the values specified for wrapped_key and initial_vector in R_SCE_AES128GCM_EncryptInit(), + * along with the additional authentication data specified in the fifth argument, aad. Inside this function, + * the data that is input by the user is buffered until the input values of aad and plain exceed 16 bytes. + * After the input data from plain reaches 16 bytes or more, the encryption result is output + * to the ciphertext data area specified in the third argument, cipher. The lengths of the plain and aad data to input + * are respectively specified in the fourth argument, plain_data_length, and the sixth argument, aad_length. For these, + * specify not the total byte count for the aad and plain input data, but rather the data length to input + * when the user calls this function. If the input values plain and aad are not divisible by 16 bytes, + * they will be padded inside the function. First process the data that is input from aad, and then process the data + * that is input from plain. If aad data is input after starting to input plain data, an error will occur. + * If aad data and plain data are input to this function at the same time, the aad data will be processed, + * and then the function will transition to the plain data input state. + * + * Specify areas for plain and cipher that do not overlap. For plain, cipher, initial_vector, and aad, specify RAM addresses + * that are multiples of 4 + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_data_length plaintext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER After the data from plain was input, + * an invalid handle was input from aad. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128GCM_EncryptUpdate (sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_length, + uint8_t * aad, + uint32_t aad_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain || (0 == plain_data_length)); + FSP_ASSERT(cipher); + FSP_ASSERT(aad || (0 == aad_length)); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_rest = 0; + uint32_t length_aad_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128gcmenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (0 != aad_length) + { + if (GCM_INPUT_DATA_TEXT == handle->flag_update_input_data) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_aad_length += aad_length; + if ((handle->buffering_aad_length + aad_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->gcm_aad_buffer[0] + handle->buffering_aad_length), + aad, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + ercd = R_SCE_Aes128GcmEncryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_aad_rest = aad_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + memset(handle->gcm_aad_buffer, 0, sizeof(handle->gcm_aad_buffer)); + if (length_aad_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + ercd = R_SCE_Aes128GcmEncryptUpdateAadPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (aad + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length)), + ((length_aad_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_aad_rest -= ((length_aad_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_aad_length = 0; + memcpy(handle->gcm_aad_buffer, aad + (aad_length - length_aad_rest), length_aad_rest); + handle->buffering_aad_length = length_aad_rest; + } + else + { + memcpy(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, aad, aad_length); + handle->buffering_aad_length += aad_length; + } + } + + if (0 != plain_data_length) + { + if (GCM_INPUT_DATA_AAD == handle->flag_update_input_data) + { + handle->flag_update_input_data = GCM_INPUT_DATA_TEXT; + if (0 != (handle->buffering_aad_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + memset(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, + 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + ercd = R_SCE_Aes128GcmEncryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + handle->buffering_aad_length = 0; + } + + R_SCE_Aes128GcmEncryptUpdateTransitionPrivate(); + } + + handle->all_received_length += plain_data_length; + if ((handle->buffering_length + plain_data_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->gcm_buffer[0] + handle->buffering_length), + plain, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + ercd = R_SCE_Aes128GcmEncryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->gcm_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2, + (uint32_t *) (cipher)); + length_rest = plain_data_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + memset(handle->gcm_buffer, 0, sizeof(handle->gcm_buffer)); + if (length_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + ercd = R_SCE_Aes128GcmEncryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (plain + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (cipher + HW_SCE_AES_BLOCK_BYTE_SIZE)); + length_rest -= ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memcpy(handle->gcm_buffer, plain + (plain_data_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->gcm_buffer[0] + handle->buffering_length, plain, plain_data_length); + handle->buffering_length += plain_data_length; + } + } + + return ercd; +} + +/*******************************************************************************************************************//** + * If there is 16-byte fractional data indicated by the total data length of the value of plain that was input + * by R_SCE_AES128GCM_EncryptUpdate (), the R_SCE_AES128GCM_EncryptFinal() function will output the result of encrypting + * that fractional data to the ciphertext data area specified in the second argument, cipher. Here, the portion + * that does not reach 16 bytes will be padded with zeros. The authentication tag is output to the fourth argument, + * atag. For cipher and atag, specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area (cipher_data_length byte) + * @param[in,out] cipher_data_length ciphertext data length (0 always written here) + * @param[in,out] atag authentication tag area + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128GCM_EncryptFinal (sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_length, + uint8_t * atag) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher_data_length); + FSP_ASSERT(atag); +#endif + + uint32_t aad_bit_size[2] = + { + 0 + }; + uint32_t data_bit_size[2] = + { + 0 + }; + fsp_err_t ercd = FSP_SUCCESS; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128gcmenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (GCM_INPUT_DATA_AAD == handle->flag_update_input_data) + { + handle->flag_update_input_data = GCM_INPUT_DATA_TEXT; + if (0 != (handle->buffering_aad_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + memset(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, + 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes128GcmEncryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + handle->buffering_aad_length = 0; + } + + R_SCE_Aes128GcmEncryptUpdateTransitionPrivate(); + } + + if ((0 != (handle->all_received_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) || (0 == handle->all_received_length)) + { + memset(handle->gcm_buffer + handle->buffering_length, 0, + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)); + } + + aad_bit_size[0] = change_endian_long((handle->all_received_aad_length & SCE_HEX_E000000) >> 29U); + aad_bit_size[1] = change_endian_long(handle->all_received_aad_length << 3U); + + data_bit_size[0] = change_endian_long((handle->all_received_length & SCE_HEX_E000000) >> 29U); + data_bit_size[1] = change_endian_long(handle->all_received_length << 3U); + *cipher_data_length = handle->all_received_length; + + ercd = R_SCE_Aes128GcmEncryptFinalPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->gcm_buffer), + aad_bit_size, + data_bit_size, + (uint32_t *) cipher, + (uint32_t *) atag); + memset(handle, 0, sizeof(sce_gcm_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128GCM_DecryptInit() function performs preparations for the execution of an GCM calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument in the subsequent + * R_SCE_AES128GCM_DecryptUpdate() function and R_SCE_AES128GCM_DecryptFinal() function. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128GCM_DecryptInit (sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(initial_vector || (wrapped_key->type == SCE_KEY_INDEX_TYPE_AES128_GCM_WITH_IV)); +#endif + + uint32_t hashed_ivec[4] = + { + 0 + }; + fsp_err_t ercd = FSP_SUCCESS; + + if ((SCE_KEY_INDEX_TYPE_AES128 == wrapped_key->type) || (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == wrapped_key->type)) + { + if (0 == initial_vector_length) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + } + else + { + if ((SCE_KEY_INDEX_TYPE_AES128_FOR_TLS != wrapped_key->type) && + (SCE_KEY_INDEX_TYPE_AES128_GCM_WITH_IV != wrapped_key->type)) + { + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + } + + memset(handle, 0, sizeof(sce_gcm_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128gcmdec_private_id = g_private_id_counter; + handle->id = g_aes128gcmdec_private_id; + if ((SCE_KEY_INDEX_TYPE_AES128 == wrapped_key->type) || (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == wrapped_key->type)) + { + ercd = prepare_gcm_iv(initial_vector, + initial_vector_length, + wrapped_key, + HW_SCE_AES128_KEY_INDEX_WORD_SIZE, + hashed_ivec); + if (FSP_SUCCESS != ercd) + { + memset(handle, 0, sizeof(sce_gcm_handle_t)); + + return ercd; + } + } + + handle->flag_update_input_data = GCM_INPUT_DATA_AAD; + + return R_SCE_Aes128GcmDecryptInitPrivate(wrapped_key, hashed_ivec); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128GCM_DecryptUpdate() function decrypts the ciphertext specified in the second argument, cipher, + * in GCM mode using the values specified for wrapped_key and initial_vector in R_SCE_AES128GCM_DecryptInit(), + * along with the additional authentication data specified in the fifth argument, aad. Inside this function, + * the data that is input by the user is buffered until the input values of aad and plain exceed 16 bytes. + * After the input data from cipher reaches 16 bytes or more, the decryption result is output to the plaintext data area + * specified in the third argument, plain. The lengths of the cipher and aad data to input are respectively specified + * in the fourth argument, cipher_data_length, and the sixth argument, aad_length. For these, specify not the total byte count + * for the aad and cipher input data, but rather the data length to input when the user calls this function. + * If the input values cipher and aad are not divisible by 16 bytes, they will be padded inside the function. + * First process the data that is input from aad, and then process the data that is input from cipher. + * If aad data is input after starting to input cipher data, an error will occur. If aad data and cipher data are + * input to this function at the same time, the aad data will be processed, and then the function will transition + * to the cipher data input state. + * Specify areas for plain and cipher that do not overlap. For plain, cipher, stage, initial_vector, and aad, specify RAM addresses + * that are multiples of 4. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in] plain plaintext data area + * @param[in] cipher_data_length ciphertext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER After the data from plain was input, + * an invalid handle was input from aad. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128GCM_DecryptUpdate (sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_length, + uint8_t * aad, + uint32_t aad_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher || (0 == cipher_data_length)); + FSP_ASSERT(plain); + FSP_ASSERT(aad || (0 == aad_length)); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_rest = 0; + uint32_t length_aad_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128gcmdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (0 != aad_length) + { + if (GCM_INPUT_DATA_TEXT == handle->flag_update_input_data) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_aad_length += aad_length; + if ((handle->buffering_aad_length + aad_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->gcm_aad_buffer[0] + handle->buffering_aad_length), + aad, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + ercd = R_SCE_Aes128GcmDecryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_aad_rest = aad_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + memset(handle->gcm_aad_buffer, 0, sizeof(handle->gcm_aad_buffer)); + if (length_aad_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + ercd = R_SCE_Aes128GcmDecryptUpdateAadPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (aad + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length)), + ((length_aad_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_aad_rest -= ((length_aad_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_aad_length = 0; + memcpy(handle->gcm_aad_buffer, aad + (aad_length - length_aad_rest), length_aad_rest); + handle->buffering_aad_length = length_aad_rest; + } + else + { + memcpy(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, aad, aad_length); + handle->buffering_aad_length += aad_length; + } + } + + if (0 != cipher_data_length) + { + if (GCM_INPUT_DATA_AAD == handle->flag_update_input_data) + { + handle->flag_update_input_data = GCM_INPUT_DATA_TEXT; + if (0 != (handle->buffering_aad_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + memset(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, + 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + ercd = R_SCE_Aes128GcmDecryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + handle->buffering_aad_length = 0; + } + + R_SCE_Aes128GcmDecryptUpdateTransitionPrivate(); + } + + handle->all_received_length += cipher_data_length; + if ((handle->buffering_length + cipher_data_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->gcm_buffer[0] + handle->buffering_length), + cipher, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + ercd = R_SCE_Aes128GcmDecryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->gcm_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2, + (uint32_t *) (plain)); + length_rest = cipher_data_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + memset(handle->gcm_buffer, 0, sizeof(handle->gcm_buffer)); + if (length_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + ercd = R_SCE_Aes128GcmDecryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (cipher + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (plain + HW_SCE_AES_BLOCK_BYTE_SIZE)); + length_rest -= ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memcpy(handle->gcm_buffer, cipher + (cipher_data_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->gcm_buffer[0] + handle->buffering_length, cipher, cipher_data_length); + handle->buffering_length += cipher_data_length; + } + } + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128GCM_DecryptFinal() function decrypts, in GCM mode, the fractional ciphertext specified + * by R_SCE_AES128GCM_DecryptUpdate() that does not reach 16 bytes, and ends GCM decryption. + * The encryption data and authentication tag are respectively output to the plaintext data area specified + * in the second argument, plain, and the authentication tag area specified in the fourth argument, atag. + * The decoded data length is output to the third argument, plain_data_length. If authentication fails, + * the return value will be TSIP_ERR_AUTHENTICATION. For the fourth argument, atag, input 16 bytes or less. + * If it is less than 16 bytes, it will be padded with zeros inside the function. For plain and atag, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] plain plaintext data area (cipher_data_length byte) + * @param[in,out] plain_data_length plaintext data length (0 always written here) + * @param[in,out] atag authentication tag area (atag_length byte) + * @param[in] atag_length authentication tag length (4,8,12,13,14,15,16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication failed + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128GCM_DecryptFinal (sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_length, + uint8_t * atag, + uint32_t atag_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(plain_data_length); + FSP_ASSERT(atag); +#endif + + uint32_t aad_bit_size[2] = + { + 0 + }; + uint32_t data_bit_size[2] = + { + 0 + }; + uint32_t atag_length_tmp = 0; + uint32_t atag_tmp[16 / sizeof(uint32_t)] = + { + 0 /* atag_tmp is initialized with 0. */ + }; + fsp_err_t ercd = FSP_SUCCESS; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128gcmdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (((1 > atag_length) || (16 < atag_length)) || ((atag_length < 12) && (0 != (atag_length % 4)))) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (GCM_INPUT_DATA_AAD == handle->flag_update_input_data) + { + handle->flag_update_input_data = GCM_INPUT_DATA_TEXT; + if (0 != (handle->buffering_aad_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + memset(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, + 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes128GcmDecryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + handle->buffering_aad_length = 0; + } + + R_SCE_Aes128GcmDecryptUpdateTransitionPrivate(); + } + + if ((0 != (handle->all_received_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) || (0 == handle->all_received_length)) + { + memset(handle->gcm_buffer + handle->buffering_length, 0, + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)); + } + + memcpy(atag_tmp, atag, atag_length); + + aad_bit_size[0] = change_endian_long((handle->all_received_aad_length & SCE_HEX_E000000) >> 29U); + aad_bit_size[1] = change_endian_long(handle->all_received_aad_length << 3U); + + data_bit_size[0] = change_endian_long((handle->all_received_length & SCE_HEX_E000000) >> 29U); + data_bit_size[1] = change_endian_long(handle->all_received_length << 3U); + + atag_length_tmp = change_endian_long(atag_length); + + *plain_data_length = handle->all_received_length; + + ercd = R_SCE_Aes128GcmDecryptFinalPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->gcm_buffer, + (uint32_t *) atag_tmp, + aad_bit_size, + data_bit_size, + &atag_length_tmp, + (uint32_t *) plain); + memset(handle, 0, sizeof(sce_gcm_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256GCM_EncryptInit() function performs preparations for the execution of an GCM calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument in the subsequent + * R_SCE_AES256GCM_EncryptUpdate() function and R_SCE_AES256GCM_EncryptFinal() function. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256GCM_EncryptInit (sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(initial_vector); +#endif + + uint32_t hashed_ivec[4] = + { + 0 + }; + fsp_err_t ercd = FSP_SUCCESS; + + if ((SCE_KEY_INDEX_TYPE_AES256 == wrapped_key->type) || + (SCE_KEY_INDEX_TYPE_AES256_GCM_FOR_DLMS_COSEM == wrapped_key->type)) + { + if (0 == initial_vector_length) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + } + + memset(handle, 0, sizeof(sce_gcm_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256gcmenc_private_id = g_private_id_counter; + handle->id = g_aes256gcmenc_private_id; + ercd = prepare_gcm_iv(initial_vector, + initial_vector_length, + wrapped_key, + HW_SCE_AES256_KEY_INDEX_WORD_SIZE, + hashed_ivec); + if (FSP_SUCCESS != ercd) + { + memset(handle, 0, sizeof(sce_gcm_handle_t)); + + return ercd; + } + + handle->flag_update_input_data = GCM_INPUT_DATA_AAD; + + return R_SCE_Aes256GcmEncryptInitPrivate(wrapped_key, hashed_ivec); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256GCM_EncryptUpdate() function encrypts the plaintext specified in the second argument, plain, + * in GCM mode using the values specified for wrapped_key and initial_vector in R_SCE_AES256GCM_EncryptInit(), + * along with the additional authentication data specified in the fifth argument, aad. Inside this function, + * the data that is input by the user is buffered until the input values of aad and plain exceed 16 bytes. + * After the input data from plain reaches 16 bytes or more, the encryption result is output + * to the ciphertext data area specified in the third argument, cipher. The lengths of the plain and aad data to input + * are respectively specified in the fourth argument, plain_data_length, and the sixth argument, aad_length. For these, + * specify not the total byte count for the aad and plain input data, but rather the data length to input + * when the user calls this function. If the input values plain and aad are not divisible by 16 bytes, + * they will be padded inside the function. First process the data that is input from aad, and then process the data + * that is input from plain. If aad data is input after starting to input plain data, an error will occur. + * If aad data and plain data are input to this function at the same time, the aad data will be processed, + * and then the function will transition to the plain data input state. + * + * Specify areas for plain and cipher that do not overlap. For plain, cipher, initial_vector, and aad, specify RAM addresses + * that are multiples of 4 + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_data_length plaintext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER After the data from plain was input, + * an invalid handle was input from aad. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256GCM_EncryptUpdate (sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_length, + uint8_t * aad, + uint32_t aad_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain || (0 == plain_data_length)); + FSP_ASSERT(cipher); + FSP_ASSERT(aad || (0 == aad_length)); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_rest = 0; + uint32_t length_aad_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256gcmenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (0 != aad_length) + { + if (GCM_INPUT_DATA_TEXT == handle->flag_update_input_data) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_aad_length += aad_length; + if ((handle->buffering_aad_length + aad_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->gcm_aad_buffer[0] + handle->buffering_aad_length), + aad, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + ercd = + R_SCE_Aes256GcmEncryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + (HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_aad_rest = aad_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + memset(handle->gcm_aad_buffer, 0, sizeof(handle->gcm_aad_buffer)); + if (length_aad_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + ercd = R_SCE_Aes256GcmEncryptUpdateAadPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (aad + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length)), + ((length_aad_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_aad_rest -= ((length_aad_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_aad_length = 0; + memcpy(handle->gcm_aad_buffer, aad + (aad_length - length_aad_rest), length_aad_rest); + handle->buffering_aad_length = length_aad_rest; + } + else + { + memcpy(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, aad, aad_length); + handle->buffering_aad_length += aad_length; + } + } + + if (0 != plain_data_length) + { + if (GCM_INPUT_DATA_AAD == handle->flag_update_input_data) + { + handle->flag_update_input_data = GCM_INPUT_DATA_TEXT; + if (0 != (handle->buffering_aad_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + memset(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, + 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + ercd = R_SCE_Aes256GcmEncryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + handle->buffering_aad_length = 0; + } + + R_SCE_Aes256GcmEncryptUpdateTransitionPrivate(); + } + + handle->all_received_length += plain_data_length; + if ((handle->buffering_length + plain_data_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->gcm_buffer[0] + handle->buffering_length), + plain, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + ercd = R_SCE_Aes256GcmEncryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->gcm_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2, + (uint32_t *) (cipher)); + length_rest = plain_data_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + memset(handle->gcm_buffer, 0, sizeof(handle->gcm_buffer)); + if (length_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + ercd = R_SCE_Aes256GcmEncryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (plain + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (cipher + HW_SCE_AES_BLOCK_BYTE_SIZE)); + length_rest -= ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memcpy(handle->gcm_buffer, plain + (plain_data_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->gcm_buffer[0] + handle->buffering_length, plain, plain_data_length); + handle->buffering_length += plain_data_length; + } + } + + return ercd; +} + +/*******************************************************************************************************************//** + * If there is 16-byte fractional data indicated by the total data length of the value of plain that was input + * by R_SCE_AES256GCM_EncryptUpdate (), the R_SCE_AES256GCM_EncryptFinal() function will output the result of encrypting + * that fractional data to the ciphertext data area specified in the second argument, cipher. Here, the portion + * that does not reach 16 bytes will be padded with zeros. The authentication tag is output to the fourth argument, + * atag. For cipher and atag, specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area (cipher_data_length byte) + * @param[in,out] cipher_data_length ciphertext data length (0 always written here) + * @param[in,out] atag authentication tag area + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256GCM_EncryptFinal (sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_length, + uint8_t * atag) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher_data_length); + FSP_ASSERT(atag); +#endif + + uint32_t aad_bit_size[2] = + { + 0 + }; + uint32_t data_bit_size[2] = + { + 0 + }; + fsp_err_t ercd = FSP_SUCCESS; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256gcmenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (GCM_INPUT_DATA_AAD == handle->flag_update_input_data) + { + handle->flag_update_input_data = GCM_INPUT_DATA_TEXT; + if (0 != (handle->buffering_aad_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + memset(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, + 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes256GcmEncryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + handle->buffering_aad_length = 0; + } + + R_SCE_Aes256GcmEncryptUpdateTransitionPrivate(); + } + + if ((0 != (handle->all_received_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) || (0 == handle->all_received_length)) + { + memset(handle->gcm_buffer + handle->buffering_length, 0, + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)); + } + + aad_bit_size[0] = change_endian_long((handle->all_received_aad_length & SCE_HEX_E000000) >> 29U); + aad_bit_size[1] = change_endian_long(handle->all_received_aad_length << 3U); + + data_bit_size[0] = change_endian_long((handle->all_received_length & SCE_HEX_E000000) >> 29U); + data_bit_size[1] = change_endian_long(handle->all_received_length << 3U); + *cipher_data_length = handle->all_received_length; + + ercd = R_SCE_Aes256GcmEncryptFinalPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->gcm_buffer), + aad_bit_size, + data_bit_size, + (uint32_t *) cipher, + (uint32_t *) atag); + memset(handle, 0, sizeof(sce_gcm_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256GCM_DecryptInit() function performs preparations for the execution of an GCM calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument in the subsequent + * R_SCE_AES256GCM_DecryptUpdate() function and R_SCE_AES256GCM_DecryptFinal() function. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256GCM_DecryptInit (sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(initial_vector); +#endif + + uint32_t hashed_ivec[4] = + { + 0 + }; + fsp_err_t ercd = FSP_SUCCESS; + + if (0 == initial_vector_length) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + memset(handle, 0, sizeof(sce_gcm_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256gcmdec_private_id = g_private_id_counter; + handle->id = g_aes256gcmdec_private_id; + memcpy(handle->wrapped_key.value, wrapped_key->value, HW_SCE_AES256_KEY_INDEX_WORD_SIZE * 4); + ercd = prepare_gcm_iv(initial_vector, + initial_vector_length, + wrapped_key, + HW_SCE_AES256_KEY_INDEX_WORD_SIZE, + hashed_ivec); + if (FSP_SUCCESS != ercd) + { + memset(handle, 0, sizeof(sce_gcm_handle_t)); + + return ercd; + } + + handle->flag_update_input_data = GCM_INPUT_DATA_AAD; + + return R_SCE_Aes256GcmDecryptInitPrivate(wrapped_key, hashed_ivec); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256GCM_DecryptUpdate() function decrypts the ciphertext specified in the second argument, cipher, + * in GCM mode using the values specified for wrapped_key and initial_vector in R_SCE_AES256GCM_DecryptInit(), + * along with the additional authentication data specified in the fifth argument, aad. Inside this function, + * the data that is input by the user is buffered until the input values of aad and plain exceed 16 bytes. + * After the input data from cipher reaches 16 bytes or more, the decryption result is output to the plaintext data area + * specified in the third argument, plain. The lengths of the cipher and aad data to input are respectively specified + * in the fourth argument, cipher_data_length, and the sixth argument, aad_length. For these, specify not the total byte count + * for the aad and cipher input data, but rather the data length to input when the user calls this function. + * If the input values cipher and aad are not divisible by 16 bytes, they will be padded inside the function. + * First process the data that is input from aad, and then process the data that is input from cipher. + * If aad data is input after starting to input cipher data, an error will occur. If aad data and cipher data are + * input to this function at the same time, the aad data will be processed, and then the function will transition + * to the cipher data input state. + * Specify areas for plain and cipher that do not overlap. For plain, cipher, stage, initial_vector, and aad, specify RAM addresses + * that are multiples of 4. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in] plain plaintext data area + * @param[in] cipher_data_length ciphertext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER After the data from plain was input, + * an invalid handle was input from aad. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256GCM_DecryptUpdate (sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_length, + uint8_t * aad, + uint32_t aad_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher || (0 == cipher_data_length)); + FSP_ASSERT(plain); + FSP_ASSERT(aad || (0 == aad_length)); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_rest = 0; + uint32_t length_aad_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256gcmdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (0 != aad_length) + { + if (GCM_INPUT_DATA_TEXT == handle->flag_update_input_data) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_aad_length += aad_length; + if ((handle->buffering_aad_length + aad_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->gcm_aad_buffer[0] + handle->buffering_aad_length), + aad, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + ercd = R_SCE_Aes256GcmDecryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_aad_rest = aad_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + memset(handle->gcm_aad_buffer, 0, sizeof(handle->gcm_aad_buffer)); + if (length_aad_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + ercd = R_SCE_Aes256GcmDecryptUpdateAadPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (aad + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length)), + ((length_aad_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_aad_rest -= ((length_aad_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_aad_length = 0; + memcpy(handle->gcm_aad_buffer, aad + (aad_length - length_aad_rest), length_aad_rest); + handle->buffering_aad_length = length_aad_rest; + } + else + { + memcpy(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, aad, aad_length); + handle->buffering_aad_length += aad_length; + } + } + + if (0 != cipher_data_length) + { + if (GCM_INPUT_DATA_AAD == handle->flag_update_input_data) + { + handle->flag_update_input_data = GCM_INPUT_DATA_TEXT; + if (0 != (handle->buffering_aad_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + memset(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, + 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + ercd = R_SCE_Aes256GcmDecryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + handle->buffering_aad_length = 0; + } + + R_SCE_Aes256GcmDecryptUpdateTransitionPrivate(); + } + + handle->all_received_length += cipher_data_length; + if ((handle->buffering_length + cipher_data_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->gcm_buffer[0] + handle->buffering_length), + cipher, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + ercd = R_SCE_Aes256GcmDecryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->gcm_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2, + (uint32_t *) (plain)); + length_rest = cipher_data_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + memset(handle->gcm_buffer, 0, sizeof(handle->gcm_buffer)); + if (length_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + ercd = R_SCE_Aes256GcmDecryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (cipher + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (plain + HW_SCE_AES_BLOCK_BYTE_SIZE)); + length_rest -= ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memcpy(handle->gcm_buffer, cipher + (cipher_data_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->gcm_buffer[0] + handle->buffering_length, cipher, cipher_data_length); + handle->buffering_length += cipher_data_length; + } + } + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256GCM_DecryptFinal() function decrypts, in GCM mode, the fractional ciphertext specified + * by R_SCE_AES256GCM_DecryptUpdate() that does not reach 16 bytes, and ends GCM decryption. + * The encryption data and authentication tag are respectively output to the plaintext data area specified + * in the second argument, plain, and the authentication tag area specified in the fourth argument, atag. + * The decoded data length is output to the third argument, plain_data_length. If authentication fails, + * the return value will be TSIP_ERR_AUTHENTICATION. For the fourth argument, atag, input 16 bytes or less. + * If it is less than 16 bytes, it will be padded with zeros inside the function. For plain and atag, + * specify RAM addresses that are multiples of 4. + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] plain plaintext data area (cipher_data_length byte) + * @param[in,out] plain_data_length plaintext data length (0 always written here) + * @param[in,out] atag authentication tag area (atag_length byte) + * @param[in] atag_length authentication tag length (4,8,12,13,14,15,16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication failed + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256GCM_DecryptFinal (sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_length, + uint8_t * atag, + uint32_t atag_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(plain_data_length); + FSP_ASSERT(atag); +#endif + + uint32_t aad_bit_size[2] = + { + 0 + }; + uint32_t data_bit_size[2] = + { + 0 + }; + uint32_t atag_length_tmp = 0; + uint32_t atag_tmp[16 / sizeof(uint32_t)] = + { + 0 /* atag_tmp is initialized with 0. */ + }; + fsp_err_t ercd = FSP_SUCCESS; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256gcmdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (((1 > atag_length) || (16 < atag_length)) || ((atag_length < 12) && (0 != (atag_length % 4)))) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (GCM_INPUT_DATA_AAD == handle->flag_update_input_data) + { + handle->flag_update_input_data = GCM_INPUT_DATA_TEXT; + if (0 != (handle->buffering_aad_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + memset(&handle->gcm_aad_buffer[0] + handle->buffering_aad_length, + 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_aad_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes256GcmDecryptUpdateAadPrivate((uint32_t *) (handle->gcm_aad_buffer), + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + handle->buffering_aad_length = 0; + } + + R_SCE_Aes256GcmDecryptUpdateTransitionPrivate(); + } + + if ((0 != (handle->all_received_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) || (0 == handle->all_received_length)) + { + memset(handle->gcm_buffer + handle->buffering_length, 0, + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)); + } + + memcpy(atag_tmp, atag, atag_length); + + aad_bit_size[0] = change_endian_long((handle->all_received_aad_length & SCE_HEX_E000000) >> 29U); + aad_bit_size[1] = change_endian_long(handle->all_received_aad_length << 3U); + + data_bit_size[0] = change_endian_long((handle->all_received_length & SCE_HEX_E000000) >> 29U); + data_bit_size[1] = change_endian_long(handle->all_received_length << 3U); + + atag_length_tmp = change_endian_long(atag_length); + + *plain_data_length = handle->all_received_length; + + ercd = R_SCE_Aes256GcmDecryptFinalPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->gcm_buffer, + (uint32_t *) atag_tmp, + aad_bit_size, + data_bit_size, + &atag_length_tmp, + (uint32_t *) plain); + memset(handle, 0, sizeof(sce_gcm_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CCM_EncryptInit() function prepares to perform CCM computation and writes the result to the first + * argument, handle. The succeeding functions R_SCE_AES128CCM_EncryptUpdate() and R_SCE_AES128CCM_EncryptFinal() + * use handle as an argument. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CCM_EncryptInit (sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t a_length, + uint32_t payload_length, + uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(nonce); + FSP_ASSERT(adata || (0 == a_length)); +#endif + + uint32_t formatted_length = 0; + + memset(handle, 0, sizeof(sce_ccm_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128ccmenc_private_id = g_private_id_counter; + handle->id = g_private_id_counter; + memcpy(&handle->wrapped_key, wrapped_key, sizeof(sce_aes_wrapped_key_t)); + + aes_ccm_b_counter_formatter(nonce, + nonce_length, + adata, + a_length, + payload_length, + mac_length, + handle->counter, + handle->formatted_data, + &formatted_length); + + return R_SCE_Aes128CcmEncryptInitPrivate(wrapped_key, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->counter, + (uint32_t *) handle->formatted_data, + formatted_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CCM_EncryptUpdate() function encrypts the plaintext specified in the second argument, plain, + * in CCM mode using the values specified by wrapped_key, nonce, and adata in R_SCE_AES128CCM_EncryptInit(). + * This function buffers internally the data input by the user until the input value of plain exceeds 16 bytes. + * Once the amount of plain input data is 16 bytes or greater, the encrypted result is output to cipher, + * which is specified in the third argument. Use payload_length in R_SCE_AES128CCM_EncryptInit() to specify the total data + * length of plain that will be input. Use plain_length in this function to specify the data length to be input + * when the user calls this function. If the input value of plain is less than 16 bytes, the function performs + * padding internally. + * + * Ensure that the areas allocated to plain and cipher do not overlap. Also, specify RAM addresses that are + * multiples of 4 for plain and cipher. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_length plaintext data length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CCM_EncryptUpdate (sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain || (0 == plain_length)); + FSP_ASSERT(cipher); +#endif + + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128ccmenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += plain_length; + if ((handle->buffering_length + plain_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->ccm_buffer[0] + handle->buffering_length), + plain, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes128CcmEncryptUpdatePrivate((uint32_t *) handle->ccm_buffer, + (uint32_t *) cipher, + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_rest = plain_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + if (length_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + R_SCE_Aes128CcmEncryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (plain + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + (uint32_t *) + (cipher + HW_SCE_AES_BLOCK_BYTE_SIZE), + ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_rest -= ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memset(handle->ccm_buffer, 0, sizeof(handle->ccm_buffer)); + memcpy(handle->ccm_buffer, plain + (plain_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->ccm_buffer[0] + handle->buffering_length, plain, plain_length); + handle->buffering_length += plain_length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * If the data length of plain input in R_SCE_AES128CCM_EncryptUpdate() results in leftover data after 16 bytes, + * the R_SCE_AES128CCM_EncryptFinal() function outputs the leftover encrypted data to cipher, which is specified + * in the second argument. The MAC value is output to the fourth argument, mac. Set the fifth argument, mac_length + * to the same value as that specified for the argument mac_length in Aes128CcmEncryptInit(). Also, specify RAM addresses + * that are multiples of 4 for cipher and mac. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in,out] cipher_length ciphertext data length + * @param[in,out] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CCM_EncryptFinal (sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher_length); + FSP_ASSERT(mac); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_tmp = 0; + uint32_t mac_length_tmp = 0; + uint32_t mac_tmp[16 / sizeof(uint32_t)] = + { + 0 + }; + uint32_t cipher_tmp[16 / sizeof(uint32_t)] = + { + 0 + }; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128ccmenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + mac_length_tmp = (((handle->formatted_data[0] >> 3) & 0x07UL) * 2UL) + 2UL; + if ((mac_length != mac_length_tmp) || (2 == mac_length_tmp)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + length_tmp = change_endian_long(handle->all_received_length); + ercd = R_SCE_Aes128CcmEncryptFinalPrivate(&length_tmp, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->ccm_buffer, + (uint32_t *) cipher_tmp, + (uint32_t *) mac_tmp); + if (FSP_SUCCESS == ercd) + { + *cipher_length = handle->all_received_length; + memcpy(mac, mac_tmp, mac_length); + memcpy(cipher, cipher_tmp, (handle->all_received_length & 0x0000000F)); + } + + memset(handle, 0, sizeof(sce_ccm_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CCM_DecryptInit() function prepares to perform CCM computation and writes the result to the first + * argument, handle. The succeeding functions R_SCE_AES128CCM_DecryptUpdate() and R_SCE_AES128CCM_DecryptFinal() + * use handle as an argument. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CCM_DecryptInit (sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t a_length, + uint32_t payload_length, + uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(nonce); + FSP_ASSERT(adata || (0 == a_length)); +#endif + + uint32_t formatted_length = 0; + + memset(handle, 0, sizeof(sce_ccm_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128ccmdec_private_id = g_private_id_counter; + handle->id = g_private_id_counter; + memcpy(&handle->wrapped_key, wrapped_key, sizeof(sce_aes_wrapped_key_t)); + + aes_ccm_b_counter_formatter(nonce, + nonce_length, + adata, + a_length, + payload_length, + mac_length, + handle->counter, + handle->formatted_data, + &formatted_length); + + return R_SCE_Aes128CcmDecryptInitPrivate(wrapped_key, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->counter, + (uint32_t *) handle->formatted_data, + formatted_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CCM_DecryptUpdate() function decrypts the ciphertext specified by the second argument, cipher, + * in CCM mode using the values specified by wrapped_key, nonce, and adata in in R_SCE_AES128CCM_DecryptInit(). + * This function buffers internally the data input by the user until the input value of cipher exceeds 16 bytes. + * Once the amount of cipher input data is 16 bytes or greater, the decrypted result is output to plain, + * which is specified in the third argument. Use payload_length in R_SCE_AES128CCM_DecryptInit() to specify the total data + * length of cipher that will be input. Use cipher_length in this function to specify the data length to be input + * when the user calls this function. If the input value of cipher is less than 16 bytes, the function performs + * padding internally. + * + * Ensure that the areas allocated to cipher and plain do not overlap. Also, specify RAM addresses that are + * multiples of 4 for cipher and plain. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in] cipher_length ciphertext data length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CCM_DecryptUpdate (sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher || (0 == cipher_length)); + FSP_ASSERT(plain); +#endif + + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128ccmdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += cipher_length; + if ((handle->buffering_length + cipher_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->ccm_buffer[0] + handle->buffering_length), + cipher, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes128CcmDecryptUpdatePrivate((uint32_t *) handle->ccm_buffer, + (uint32_t *) plain, + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_rest = cipher_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + if (length_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + R_SCE_Aes128CcmDecryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (cipher + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + (uint32_t *) + (plain + HW_SCE_AES_BLOCK_BYTE_SIZE), + ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_rest -= ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memset(handle->ccm_buffer, 0, sizeof(handle->ccm_buffer)); + memcpy(handle->ccm_buffer, cipher + (cipher_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->ccm_buffer[0] + handle->buffering_length, cipher, cipher_length); + handle->buffering_length += cipher_length; + } + + return FSP_SUCCESS; +} + +/******************************* + * End of function HW_SCE_Aes128CcmDecryptUpdate + *******************************/ + +/*******************************************************************************************************************//** + * If the data length of cipher input in R_SCE_AES128GCM_DecryptUpdate() results in leftover data after 16 bytes, + * the R_SCE_AES128GCM_DecryptFinal() function outputs the leftover decrypted data to cipher, which is specified + * in the second argument. In addition, the function verifies the fourth argument, mac. Set the fifth argument, + * mac_length, to the same value as that specified for the argument mac_length in Aes128CcmDecryptInit(). + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] plain plaintext data area + * @param[in,out] plain_length plaintext data length + * @param[in] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error, or authentication failed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CCM_DecryptFinal (sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(plain_length); + FSP_ASSERT(mac); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_tmp = 0; + uint32_t mac_length_tmp = 0; + uint32_t mac_tmp[16 / sizeof(uint32_t)] = + { + 0 + }; + uint32_t plain_tmp[16 / sizeof(uint32_t)] = + { + 0 + }; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128ccmdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + mac_length_tmp = (((handle->formatted_data[0] >> 3UL) & 0x07UL) * 2UL) + 2UL; + if ((mac_length != mac_length_tmp) || (2 == mac_length_tmp)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + length_tmp = change_endian_long(handle->all_received_length); + mac_length_tmp = change_endian_long(mac_length); + memcpy(mac_tmp, mac, mac_length); + ercd = R_SCE_Aes128CcmDecryptFinalPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->ccm_buffer, + &length_tmp, + (uint32_t *) mac_tmp, + &mac_length_tmp, + (uint32_t *) plain_tmp); + if (FSP_SUCCESS == ercd) + { + *plain_length = handle->all_received_length; + memcpy(plain, plain_tmp, (handle->all_received_length & 0x0000000F)); + } + + memset(handle, 0, sizeof(sce_ccm_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CCM_EncryptInit() function prepares to perform CCM computation and writes the result to the first + * argument, handle. The succeeding functions R_SCE_AES256CCM_EncryptUpdate() and R_SCE_AES256CCM_EncryptFinal() + * use handle as an argument. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CCM_EncryptInit (sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t a_length, + uint32_t payload_length, + uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(nonce); + FSP_ASSERT(adata || (0 == a_length)); +#endif + + uint32_t formatted_length = 0; + + memset(handle, 0, sizeof(sce_ccm_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256ccmenc_private_id = g_private_id_counter; + handle->id = g_private_id_counter; + memcpy(&handle->wrapped_key, wrapped_key, sizeof(sce_aes_wrapped_key_t)); + + aes_ccm_b_counter_formatter(nonce, + nonce_length, + adata, + a_length, + payload_length, + mac_length, + handle->counter, + handle->formatted_data, + &formatted_length); + + return R_SCE_Aes256CcmEncryptInitPrivate(wrapped_key, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->counter, + (uint32_t *) handle->formatted_data, + formatted_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CCM_EncryptUpdate() function encrypts the plaintext specified in the second argument, plain, + * in CCM mode using the values specified by wrapped_key, nonce, and adata in R_SCE_AES256CCM_EncryptInit(). + * This function buffers internally the data input by the user until the input value of plain exceeds 16 bytes. + * Once the amount of plain input data is 16 bytes or greater, the encrypted result is output to cipher, + * which is specified in the third argument. Use payload_length in R_SCE_AES256CCM_EncryptInit() to specify the total data + * length of plain that will be input. Use plain_length in this function to specify the data length to be input + * when the user calls this function. If the input value of plain is less than 16 bytes, the function performs + * padding internally. + * + * Ensure that the areas allocated to plain and cipher do not overlap. Also, specify RAM addresses that are + * multiples of 4 for plain and cipher. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_length plaintext data length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CCM_EncryptUpdate (sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain || (0 == plain_length)); + FSP_ASSERT(cipher); +#endif + + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256ccmenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += plain_length; + if ((handle->buffering_length + plain_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->ccm_buffer[0] + handle->buffering_length), + plain, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes256CcmEncryptUpdatePrivate((uint32_t *) handle->ccm_buffer, + (uint32_t *) cipher, + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_rest = plain_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + if (length_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + R_SCE_Aes256CcmEncryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (plain + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + (uint32_t *) + (cipher + HW_SCE_AES_BLOCK_BYTE_SIZE), + ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_rest -= ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memset(handle->ccm_buffer, 0, sizeof(handle->ccm_buffer)); + memcpy(handle->ccm_buffer, plain + (plain_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->ccm_buffer[0] + handle->buffering_length, plain, plain_length); + handle->buffering_length += plain_length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * If the data length of plain input in R_SCE_AES256CCM_EncryptUpdate() results in leftover data after 16 bytes, + * the R_SCE_AES256CCM_EncryptFinal() function outputs the leftover encrypted data to cipher, which is specified + * in the second argument. The MAC value is output to the fourth argument, mac. Set the fifth argument, mac_length + * to the same value as that specified for the argument mac_length in Aes256CcmEncryptInit(). Also, specify RAM addresses + * that are multiples of 4 for cipher and mac. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in,out] cipher_length ciphertext data length + * @param[in,out] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CCM_EncryptFinal (sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher_length); + FSP_ASSERT(mac); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_tmp = 0; + uint32_t mac_length_tmp = 0; + uint32_t mac_tmp[16 / sizeof(uint32_t)] = + { + 0 + }; + uint32_t cipher_tmp[16 / sizeof(uint32_t)] = + { + 0 + }; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256ccmenc_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + mac_length_tmp = (((handle->formatted_data[0] >> 3UL) & 0x07UL) * 2UL) + 2UL; + if ((mac_length != mac_length_tmp) || (2 == mac_length_tmp)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + length_tmp = change_endian_long(handle->all_received_length); + ercd = R_SCE_Aes256CcmEncryptFinalPrivate(&length_tmp, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->ccm_buffer, + (uint32_t *) cipher_tmp, + (uint32_t *) mac_tmp); + if (FSP_SUCCESS == ercd) + { + *cipher_length = handle->all_received_length; + memcpy(mac, mac_tmp, mac_length); + memcpy(cipher, cipher_tmp, (handle->all_received_length & 0x0000000F)); + } + + memset(handle, 0, sizeof(sce_ccm_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CCM_DecryptInit() function prepares to perform CCM computation and writes the result to the first + * argument, handle. The succeeding functions R_SCE_AES256CCM_DecryptUpdate() and R_SCE_AES256CCM_DecryptFinal() + * use handle as an argument. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CCM_DecryptInit (sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t a_length, + uint32_t payload_length, + uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); + FSP_ASSERT(nonce); + FSP_ASSERT(adata || (0 == a_length)); +#endif + + uint32_t formatted_length = 0; + + memset(handle, 0, sizeof(sce_ccm_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256ccmdec_private_id = g_private_id_counter; + handle->id = g_private_id_counter; + memcpy(&handle->wrapped_key, wrapped_key, sizeof(sce_aes_wrapped_key_t)); + + aes_ccm_b_counter_formatter(nonce, + nonce_length, + adata, + a_length, + payload_length, + mac_length, + handle->counter, + handle->formatted_data, + &formatted_length); + + return R_SCE_Aes256CcmDecryptInitPrivate(wrapped_key, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->counter, + (uint32_t *) handle->formatted_data, + formatted_length); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CCM_DecryptUpdate() function decrypts the ciphertext specified by the second argument, cipher, + * in CCM mode using the values specified by wrapped_key, nonce, and adata in in R_SCE_AES256CCM_DecryptInit(). + * This function buffers internally the data input by the user until the input value of cipher exceeds 16 bytes. + * Once the amount of cipher input data is 16 bytes or greater, the decrypted result is output to plain, + * which is specified in the third argument. Use payload_length in R_SCE_AES256CCM_DecryptInit() to specify the total data + * length of cipher that will be input. Use cipher_length in this function to specify the data length to be input + * when the user calls this function. If the input value of cipher is less than 16 bytes, the function performs + * padding internally. + * + * Ensure that the areas allocated to cipher and plain do not overlap. Also, specify RAM addresses that are + * multiples of 4 for cipher and plain. + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in] cipher_length ciphertext data length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CCM_DecryptUpdate (sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(cipher || (0 == cipher_length)); + FSP_ASSERT(plain); +#endif + + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256ccmdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += cipher_length; + if ((handle->buffering_length + cipher_length) >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->ccm_buffer[0] + handle->buffering_length), + cipher, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes256CcmDecryptUpdatePrivate((uint32_t *) handle->ccm_buffer, + (uint32_t *) plain, + HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_rest = cipher_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + if (length_rest >= HW_SCE_AES_BLOCK_BYTE_SIZE) + { + R_SCE_Aes256CcmDecryptUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (cipher + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + (uint32_t *) + (plain + HW_SCE_AES_BLOCK_BYTE_SIZE), + ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_rest -= ((length_rest / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memset(handle->ccm_buffer, 0, sizeof(handle->ccm_buffer)); + memcpy(handle->ccm_buffer, cipher + (cipher_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->ccm_buffer[0] + handle->buffering_length, cipher, cipher_length); + handle->buffering_length += cipher_length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * If the data length of cipher input in R_SCE_AES256GCM_DecryptUpdate() results in leftover data after 16 bytes, + * the R_SCE_AES256GCM_DecryptFinal() function outputs the leftover decrypted data to cipher, which is specified + * in the second argument. In addition, the function verifies the fourth argument, mac. Set the fifth argument, + * mac_length, to the same value as that specified for the argument mac_length in Aes256CcmDecryptInit(). + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] plain plaintext data area + * @param[in,out] plain_length plaintext data length + * @param[in] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error, or authentication failed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CCM_DecryptFinal (sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(plain); + FSP_ASSERT(plain_length); + FSP_ASSERT(mac); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_tmp = 0; + uint32_t mac_length_tmp = 0; + uint32_t mac_tmp[16 / sizeof(uint32_t)] = + { + 0 + }; + uint32_t plain_tmp[16 / sizeof(uint32_t)] = + { + 0 + }; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256ccmdec_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + mac_length_tmp = (((handle->formatted_data[0] >> 3UL) & 0x07UL) * 2UL) + 2UL; + if ((mac_length != mac_length_tmp) || (2 == mac_length_tmp)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + length_tmp = change_endian_long(handle->all_received_length); + mac_length_tmp = change_endian_long(mac_length); + memcpy(mac_tmp, mac, mac_length); + ercd = R_SCE_Aes256CcmDecryptFinalPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->ccm_buffer, + &length_tmp, + (uint32_t *) mac_tmp, + &mac_length_tmp, + (uint32_t *) plain_tmp); + if (FSP_SUCCESS == ercd) + { + *plain_length = handle->all_received_length; + memcpy(plain, plain_tmp, (handle->all_received_length & 0x0000000F)); + } + + memset(handle, 0, sizeof(sce_ccm_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CMAC_GenerateInit() function performs preparations for the execution of an CMAC calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument in the subsequent + * R_SCE_AES128CMAC_GenerateUpdate() function and R_SCE_AES128CMAC_GenerateFinal() function. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CMAC_GenerateInit (sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + + memset(handle, 0, sizeof(sce_cmac_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128cmacgen_private_id = g_private_id_counter; + handle->id = g_aes128cmacgen_private_id; + memcpy(handle->wrapped_key.value, wrapped_key->value, HW_SCE_AES128_KEY_INDEX_WORD_SIZE * 4); + memset(handle->cmac_buffer, 0, sizeof(handle->cmac_buffer)); + + return R_SCE_Aes128CmacGenerateInitPrivate(wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CMAC_GenerateUpdate() function performs MAC value generation based on the message specified + * in the second argument, message, using the value specified for wrapped_key in R_SCE_AES128CMAC_GenerateInit(). + * Inside this function, the data that is input by the user is buffered until the input value of message + * exceeds 16 bytes. The length of the message data to input is specified in the third argument, message_len. + * For these, input not the total byte count for message input data, but rather the message data length + * to input when the user calls this function. If the input value, message, is not a multiple of 16 bytes, + * it will be padded within the function. For message, specify a RAM address that are multiples of 4. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CMAC_GenerateUpdate (sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(message || (0 == message_length)); +#endif + + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128cmacgen_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += message_length; + if ((handle->buffering_length + message_length) > HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->cmac_buffer[0] + handle->buffering_length), + message, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes128CmacGenerateUpdatePrivate((uint32_t *) (handle->cmac_buffer), HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_rest = message_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + memset(handle->cmac_buffer, 0, sizeof(handle->cmac_buffer)); + if (length_rest > HW_SCE_AES_BLOCK_BYTE_SIZE) + { + R_SCE_Aes128CmacGenerateUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (message + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + (((length_rest - 1) / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_rest -= (((length_rest - 1) / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memcpy(handle->cmac_buffer, message + (message_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->cmac_buffer[0] + handle->buffering_length, message, message_length); + handle->buffering_length += message_length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CMAC_GenerateFinal() function outputs the MAC value to the MAC data area specified + * in the second argument, mac, and ends CMAC mode. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (16byte) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Not used. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CMAC_GenerateFinal (sce_cmac_handle_t * handle, uint8_t * mac) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(mac); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128cmacgen_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((0 != (handle->buffering_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) || (0 == handle->all_received_length)) + { + handle->cmac_buffer[handle->buffering_length] = 1 << 7; + memset(handle->cmac_buffer + (handle->buffering_length + 1), 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - (handle->buffering_length + 1)); + } + + ercd = R_SCE_Aes128CmacGenerateFinalPrivate(handle->all_received_length, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->cmac_buffer), + (uint32_t *) (mac)); + memset(handle, 0, sizeof(sce_cmac_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CMAC_VerifyInit() function performs preparations for the execution of a CMAC calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argumentin the subsequent + * R_SCE_AES128CMAC_VerifyUpdate() function and R_SCE_AES128CMAC_VerifyFinal() function. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CMAC_VerifyInit (sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + + memset(handle, 0, sizeof(sce_cmac_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes128cmacver_private_id = g_private_id_counter; + handle->id = g_aes128cmacver_private_id; + memcpy(handle->wrapped_key.value, wrapped_key->value, HW_SCE_AES128_KEY_INDEX_WORD_SIZE * 4); + memset(handle->cmac_buffer, 0, sizeof(handle->cmac_buffer)); + + return R_SCE_Aes128CmacVerifyInitPrivate(wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CMAC_VerifyUpdate() function performs MAC value generation based on the message specified + * in the second argument, message, using the value specified for wrapped_key in R_SCE_AES128CMAC_VerifyInit(). + * Inside this function, the data that is input by the user is buffered until the input value of message + * exceeds 16 bytes. The length of the message data to input is specified in the third argument, message_len. + * For these, input not the total byte count for message input data, but rather the message data length to input + * when the user calls this function. If the input value, message, is not a multiple of 16 bytes, + * it will be padded within the function. For message, specify a RAM address that are multiples of 4. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CMAC_VerifyUpdate (sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(message || (0 == message_length)); +#endif + + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes128cmacver_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += message_length; + if ((handle->buffering_length + message_length) > HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->cmac_buffer[0] + handle->buffering_length), + message, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes128CmacVerifyUpdatePrivate((uint32_t *) (handle->cmac_buffer), HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_rest = message_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + memset(handle->cmac_buffer, 0, sizeof(handle->cmac_buffer)); + if (length_rest > HW_SCE_AES_BLOCK_BYTE_SIZE) + { + R_SCE_Aes128CmacVerifyUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (message + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + (((length_rest - 1) / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_rest -= (((length_rest - 1) / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memcpy(handle->cmac_buffer, message + (message_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->cmac_buffer[0] + handle->buffering_length, message, message_length); + handle->buffering_length += message_length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES128CMAC_VerifyFinal() function inputs the MAC value in the MAC data area specified + * in the second argument, mac, and verifies the MAC value. If authentication fails, the return value will be + * TSIP_ERR_AUTHENTICATION. If the MAC value is less than 16 bytes, it will be padded with zeros inside the function. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (mac_length byte) + * @param[in,out] mac_length MAC data length (2 to 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication failed + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES128CMAC_VerifyFinal (sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(mac); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t mac_tmp[16 / sizeof(uint32_t)] = + { + 0 /* mac_tmp is initialized with 0. */ + }; + uint32_t mac_length_bit = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes128cmacver_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((2 > mac_length) || (mac_length > HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((0 != (handle->buffering_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) || (0 == handle->all_received_length)) + { + handle->cmac_buffer[handle->buffering_length] = 1 << 7; + memset(handle->cmac_buffer + (handle->buffering_length + 1), 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - (handle->buffering_length + 1)); + } + + memcpy(mac_tmp, mac, mac_length); + mac_length_bit = change_endian_long(mac_length * 8); + + ercd = R_SCE_Aes128CmacVerifyFinalPrivate(handle->all_received_length, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->cmac_buffer, + (uint32_t *) mac_tmp, + &mac_length_bit); + memset(handle, 0, sizeof(sce_cmac_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CMAC_GenerateInit() function performs preparations for the execution of an CMAC calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument in the subsequent + * R_SCE_AES256CMAC_GenerateUpdate() function and R_SCE_AES256CMAC_GenerateFinal() function. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CMAC_GenerateInit (sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + + memset(handle, 0, sizeof(sce_cmac_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256cmacgen_private_id = g_private_id_counter; + handle->id = g_aes256cmacgen_private_id; + memcpy(handle->wrapped_key.value, wrapped_key->value, HW_SCE_AES256_KEY_INDEX_WORD_SIZE * 4); + memset(handle->cmac_buffer, 0, sizeof(handle->cmac_buffer)); + + return R_SCE_Aes256CmacGenerateInitPrivate(wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CMAC_GenerateUpdate() function performs MAC value generation based on the message specified + * in the second argument, message, using the value specified for wrapped_key in R_SCE_AES256CMAC_GenerateInit(). + * Inside this function, the data that is input by the user is buffered until the input value of message + * exceeds 16 bytes. The length of the message data to input is specified in the third argument, message_len. + * For these, input not the total byte count for message input data, but rather the message data length + * to input when the user calls this function. If the input value, message, is not a multiple of 16 bytes, + * it will be padded within the function. For message, specify a RAM address that are multiples of 4. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CMAC_GenerateUpdate (sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(message || (0 == message_length)); +#endif + + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256cmacgen_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += message_length; + if ((handle->buffering_length + message_length) > HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->cmac_buffer[0] + handle->buffering_length), + message, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes256CmacGenerateUpdatePrivate((uint32_t *) (handle->cmac_buffer), HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_rest = message_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + memset(handle->cmac_buffer, 0, sizeof(handle->cmac_buffer)); + if (length_rest > HW_SCE_AES_BLOCK_BYTE_SIZE) + { + R_SCE_Aes256CmacGenerateUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (message + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + (((length_rest - 1) / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_rest -= (((length_rest - 1) / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memcpy(handle->cmac_buffer, message + (message_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->cmac_buffer[0] + handle->buffering_length, message, message_length); + handle->buffering_length += message_length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CMAC_GenerateFinal() function outputs the MAC value to the MAC data area specified + * in the second argument, mac, and ends CMAC mode. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (16byte) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Not used. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CMAC_GenerateFinal (sce_cmac_handle_t * handle, uint8_t * mac) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(mac); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256cmacgen_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((0 != (handle->buffering_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) || (0 == handle->all_received_length)) + { + handle->cmac_buffer[handle->buffering_length] = 1 << 7; + memset(handle->cmac_buffer + (handle->buffering_length + 1), 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - (handle->buffering_length + 1)); + } + + ercd = R_SCE_Aes256CmacGenerateFinalPrivate(handle->all_received_length, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->cmac_buffer), + (uint32_t *) (mac)); + memset(handle, 0, sizeof(sce_cmac_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CMAC_VerifyInit() function performs preparations for the execution of a CMAC calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argumentin the subsequent + * R_SCE_AES256CMAC_VerifyUpdate() function and R_SCE_AES256CMAC_VerifyFinal() function. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CMAC_VerifyInit (sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + + memset(handle, 0, sizeof(sce_cmac_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_aes256cmacver_private_id = g_private_id_counter; + handle->id = g_aes256cmacver_private_id; + memcpy(handle->wrapped_key.value, wrapped_key->value, HW_SCE_AES256_KEY_INDEX_WORD_SIZE * 4); + memset(handle->cmac_buffer, 0, sizeof(handle->cmac_buffer)); + + return R_SCE_Aes256CmacVerifyInitPrivate(wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CMAC_VerifyUpdate() function performs MAC value generation based on the message specified + * in the second argument, message, using the value specified for wrapped_key in R_SCE_AES256CMAC_VerifyInit(). + * Inside this function, the data that is input by the user is buffered until the input value of message + * exceeds 16 bytes. The length of the message data to input is specified in the third argument, message_len. + * For these, input not the total byte count for message input data, but rather the message data length to input + * when the user calls this function. If the input value, message, is not a multiple of 16 bytes, + * it will be padded within the function. For message, specify a RAM address that are multiples of 4. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CMAC_VerifyUpdate (sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(message || (0 == message_length)); +#endif + + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_aes256cmacver_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += message_length; + if ((handle->buffering_length + message_length) > HW_SCE_AES_BLOCK_BYTE_SIZE) + { + memcpy((&handle->cmac_buffer[0] + handle->buffering_length), + message, + HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + + /* Casting uint32_t pointer is used for address. */ + R_SCE_Aes256CmacVerifyUpdatePrivate((uint32_t *) (handle->cmac_buffer), HW_SCE_AES_BLOCK_BYTE_SIZE >> 2); + length_rest = message_length - (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length); + memset(handle->cmac_buffer, 0, sizeof(handle->cmac_buffer)); + if (length_rest > HW_SCE_AES_BLOCK_BYTE_SIZE) + { + R_SCE_Aes256CmacVerifyUpdatePrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (message + (HW_SCE_AES_BLOCK_BYTE_SIZE - handle->buffering_length)), + (((length_rest - 1) / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE) >> 2); + length_rest -= (((length_rest - 1) / HW_SCE_AES_BLOCK_BYTE_SIZE) * HW_SCE_AES_BLOCK_BYTE_SIZE); + } + + handle->buffering_length = 0; + memcpy(handle->cmac_buffer, message + (message_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->cmac_buffer[0] + handle->buffering_length, message, message_length); + handle->buffering_length += message_length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The R_SCE_AES256CMAC_VerifyFinal() function inputs the MAC value in the MAC data area specified + * in the second argument, mac, and verifies the MAC value. If authentication fails, the return value will be + * TSIP_ERR_AUTHENTICATION. If the MAC value is less than 16 bytes, it will be padded with zeros inside the function. + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (mac_length byte) + * @param[in,out] mac_length MAC data length (2 to 16 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication failed + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_AES256CMAC_VerifyFinal (sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(mac); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint32_t mac_tmp[16 / sizeof(uint32_t)] = + { + 0 /* mac_tmp is initialized with 0. */ + }; + uint32_t mac_length_bit = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_aes256cmacver_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((2 > mac_length) || (mac_length > HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((0 != (handle->buffering_length % HW_SCE_AES_BLOCK_BYTE_SIZE)) || (0 == handle->all_received_length)) + { + handle->cmac_buffer[handle->buffering_length] = 1 << 7; + memset(handle->cmac_buffer + (handle->buffering_length + 1), 0, + HW_SCE_AES_BLOCK_BYTE_SIZE - (handle->buffering_length + 1)); + } + + memcpy(mac_tmp, mac, mac_length); + mac_length_bit = change_endian_long(mac_length * 8); + + ercd = R_SCE_Aes256CmacVerifyFinalPrivate(handle->all_received_length, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) handle->cmac_buffer, + (uint32_t *) mac_tmp, + &mac_length_bit); + memset(handle, 0, sizeof(sce_cmac_handle_t)); + + return ercd; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Generation of input parameter for R_SCE_AESXXXGCM_XXX function. + * + * @param[in] initial_vector Input initial vector. + * @param[in] initial_vector_length Input initial vector byte size. + * @param[in] wrapped_key Wrapped key area. + * @param[in] wrapped_key_word_size Wrapped key word size. + * @param[in,out] hashed_ivec Output initialization vector( using length of initial_vector_length as a condition) + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT Resource conflict + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Input illegal user Key Generation Information + *********************************************************************************************************************/ +static fsp_err_t prepare_gcm_iv (uint8_t * initial_vector, + uint32_t initial_vector_length, + sce_aes_wrapped_key_t * wrapped_key, + uint32_t wrapped_key_word_size, + uint32_t * hashed_ivec) +{ + uint32_t hash_subkey[4] = + { + 0 + }; + uint32_t hashed_ivec_tmp[4] = + { + 0 + }; + uint32_t zero[4] = + { + 0 + }; + uint32_t ivec_length_rest = 0; + uint32_t ivec_bit_len[4] = + { + 0 + }; + uint32_t ivec_tmp[4] = + { + 0 + }; + fsp_err_t ret = FSP_SUCCESS; + + /* when iv_len is 12 (96 bit), add 0x00000001 padding */ + if (12U == initial_vector_length) + { + memcpy(hashed_ivec, initial_vector, 12U); + hashed_ivec[3] = change_endian_long(0x00000001U); + } + /* when iv_len is not 12 (96 bit), add ghash padding */ + else + { + uint32_t indata_keytype = 0; /* For normal */ + uint32_t indata_cmd = 0; + + /* generate hash_subkey */ + indata_cmd = change_endian_long(0); /* ECB-Encrypt command */ + if (HW_SCE_AES128_KEY_INDEX_WORD_SIZE == wrapped_key_word_size) + { + if (SCE_KEY_INDEX_TYPE_AES128 == wrapped_key->type) + { + if (SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH == wrapped_key->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + + ret = R_SCE_Aes128EncryptDecryptInitSub(&indata_keytype, &indata_cmd, wrapped_key->value, zero); + if (FSP_SUCCESS == ret) + { + R_SCE_Aes128EncryptDecryptUpdateSub(zero, hash_subkey, 4); + ret = R_SCE_Aes128EncryptDecryptFinalSub(); + } + } + } + else /* if (SCE_KEY_INDEX_TYPE_AES256 == key_index_word_size) */ + { + if (SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH == wrapped_key->type) + { + indata_keytype = change_endian_long(2); /* For ECDH */ + } + + ret = R_SCE_Aes256EncryptDecryptInitSub(&indata_keytype, &indata_cmd, wrapped_key->value, zero); + if (FSP_SUCCESS == ret) + { + R_SCE_Aes256EncryptDecryptUpdateSub(zero, hash_subkey, 4); + ret = R_SCE_Aes256EncryptDecryptFinalSub(); + } + } + + if (FSP_SUCCESS == ret) + { + if (16 <= initial_vector_length) + { + /* Casting uint32_t pointer is used for address. */ + ret = + R_SCE_Ghash(hash_subkey, zero, (uint32_t *) initial_vector, hashed_ivec_tmp, + (initial_vector_length / 16U) * 4); + if (FSP_SUCCESS == ret) + { + ivec_length_rest = initial_vector_length % 16; + if (0 != ivec_length_rest) + { + memcpy(ivec_tmp, initial_vector + (initial_vector_length - ivec_length_rest), ivec_length_rest); + + /* Casting uint32_t pointer is used for address. */ + ret = R_SCE_Ghash(hash_subkey, hashed_ivec_tmp, ivec_tmp, hashed_ivec_tmp, 4); + } + } + } + else + { + memcpy(ivec_tmp, initial_vector, initial_vector_length); + + /* Casting uint32_t pointer is used for address. */ + ret = R_SCE_Ghash(hash_subkey, zero, ivec_tmp, hashed_ivec_tmp, 4); + } + + if (FSP_SUCCESS == ret) + { + /* calculate ivec bit length */ + ivec_bit_len[0] = 0U; + ivec_bit_len[1] = 0U; + ivec_bit_len[2] = change_endian_long(initial_vector_length >> 29U); /* need endian change when big endian */ + ivec_bit_len[3] = change_endian_long(initial_vector_length << 3U); /* need endian change when big endian */ + + ret = R_SCE_Ghash(hash_subkey, hashed_ivec_tmp, ivec_bit_len, hashed_ivec, 4); + } + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Formatting and counter generation. + * + * @param[in] nonce Nonce. + * @param[in] nonce_len Nonce data length(byte). + * @param[in] adata Associated data. + * @param[in] a_len Associated data length(byte). + * @param[in] payload_len Payload length(byte). + * @param[in] mac_len MAC data length(byte). + * @param[in,out] counter Counter blocks area. + * @param[in,out] formatted_data Formatted data area. + * @param[in,out] formatted_length Formatted data length. + *********************************************************************************************************************/ +static void aes_ccm_b_counter_formatter (uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len, + uint8_t * counter, + uint8_t * formatted_data, + uint32_t * formatted_length) +{ + uint8_t flag = 0; + uint8_t mac_len_tmp = 0; + uint8_t q_len = 0; + uint32_t formatted_length_tmp = 0; + + /* Out of range check */ + if (((7 > nonce_len) || (13 < nonce_len)) || + (((4 > mac_len) || (16 < mac_len)) || ((0 != (mac_len % 2)) || (SCE_DEC_110 < a_len)))) + { + return; + } + + /* formatting flag section in formatted data B */ + if (0 < a_len) + { + flag = 1 << 6; + } + + mac_len_tmp = (uint8_t) ((mac_len - 2) / 2); + mac_len_tmp = (uint8_t) (mac_len_tmp << 3); + flag |= mac_len_tmp; + q_len = (uint8_t) (15 - nonce_len); + flag |= (uint8_t) (q_len - 1); + formatted_data[formatted_length_tmp] = flag; + formatted_length_tmp++; + + /* adding nonce to formatted data B */ + memcpy(formatted_data + formatted_length_tmp, nonce, nonce_len); + formatted_length_tmp += 11; + if (12 <= nonce_len) + { + formatted_length_tmp++; + } + + if (13 <= nonce_len) + { + formatted_length_tmp++; + } + + /* adding Q to formatted data B */ + do + { + /* Casting uint32_t data to uint8_t data array. */ + formatted_data[formatted_length_tmp] = (uint8_t) (payload_len >> (8 * (15 - formatted_length_tmp))); + formatted_length_tmp++; + } while (16 != formatted_length_tmp); + + /* adding Adata to formatted data B */ + if (0 < a_len) + { + formatted_length_tmp++; + formatted_data[formatted_length_tmp] = a_len; + formatted_length_tmp++; + memcpy(formatted_data + formatted_length_tmp, adata, a_len); + formatted_length_tmp += a_len; + if (0 != (formatted_length_tmp % HW_SCE_AES_BLOCK_BYTE_SIZE)) + { + formatted_length_tmp += (HW_SCE_AES_BLOCK_BYTE_SIZE - (formatted_length_tmp % HW_SCE_AES_BLOCK_BYTE_SIZE)); + } + } + + *formatted_length = formatted_length_tmp >> 2; + + /* formatting flag section in counter0 */ + flag = (uint8_t) (q_len - 1); + counter[0] = flag; + + /* adding nonce to counter0 */ + memcpy(counter + 1, nonce, nonce_len); +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c new file mode 100644 index 0000000000..e25cef3a33 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c @@ -0,0 +1,1361 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sce_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define SCE_PRV_HASH_WORD_POS_ECDSA_P192 (2) /* Hash data output position for ECDSA P-192. : (256 - 192) / 32 */ +#define SCE_PRV_HASH_WORD_POS_ECDSA_P224 (1) /* Hash data output position for ECDSA P-224. : (256 - 224) / 32 */ +#define SCE_PRV_HASH_WORD_POS_ECDSA_P256 (0) /* Hash data output position for ECDSA P-256. : (256 - 256) / 32 */ +#define SCE_PRV_HASH_WORD_POS_ECDSA_P384 (0xFFFFFFFCUL) /* For ECDSA P-384 : (256 - 384) / 32 */ + +/* Block length (in bytes) of ECDH */ +#define SCE_PRV_INDATA_BYTEDATA_LEN (32 * 4) /* 32 words */ +#define SCE_PRV_OTHER_INFO_BYTE_LEN_2B ((7 + 16 * 1) * 4) /* 2 blocks */ +#define SCE_PRV_OTHER_INFO_BYTE_LEN_3B ((7 + 16 * 2) * 4) /* 3 blocks */ +#define SCE_PRV_OTHER_INFO_BYTE_LEN_SUPP (288) /* suppPubInfo + suppPrivInfo */ + +#ifndef SCE_HEX_FF + #define SCE_HEX_FF (0xFF) +#endif +#ifndef SCE_HEX_80 + #define SCE_HEX_80 (0x80) +#endif +#ifndef SCE_DEC_64 + #define SCE_DEC_64 (64) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* For R_SCE_ECDH_secp256r1_PublicKeyVerify */ +typedef struct st_read_public_key +{ + uint32_t cmd; + uint8_t bytedata[SCE_PRV_INDATA_BYTEDATA_LEN]; +} st_read_public_key_t; + +/* For R_SCE_ECDH_secp256r1_KeyDerivation */ +typedef struct st_key_derivation +{ + uint32_t keyindextype; + uint32_t kdftype; + uint32_t max_cnt_byte; + uint8_t paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_3B]; +} st_key_derivation_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static fsp_err_t set_ecdsa_hash_data(sce_ecdsa_byte_data_t * p_message_hash, + uint32_t * data_buff, + uint32_t hash_word_pos); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +static const SCE_KEY_INDEX_TYPE s_key_index_type[3] = +{ + SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH, SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH, SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_ECDH +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern uint32_t g_private_id_counter; +uint32_t g_ecdh256_private_id; + +/*******************************************************************************************************************//** + * @addtogroup SCE_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * When a message is specified in the first argument, message_hash->data_type, a SHA-256 hash of the message text + * input as the first argument, message_hash->pdata, is calculated, and the signature text is written to the second + * argument, signature, in accordance with secp192r1 using the private wrapped key input as the third argument, + * wrapped_key. + * + * When a hash value is specified in the first argument, message_hash->data_type, the signature text for the first + * 24 bytes of the SHA-256 hash value input to the first argument, message_hash->pdata, is written to the second + * argument, signature, in accordance with secp192r1 using the private wrapped key input as the third argument, + * wrapped_key. + * + * @param[in] message_hash Message or hash value to which to attach signature + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in,out] signature Signature text storage destination information + * @arg signature->pdata : Specifies pointer to array storing signature text + * The signature format is "0 padding (64 bits) || + * signature r (192 bits) || 0 padding (64 bits) || + * signature s (192 bits)". + * @arg signature->data_length : Data length (byte units) + * @param[in] wrapped_key Input wrapped key of secp192r1 private key. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDSA_secp192r1_SignatureGenerate (sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(wrapped_key); +#endif + + uint32_t indata_cmd; + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + uint32_t data_buff[SCE_PRV_HASH_WORD_POS_ECDSA_P192 + (HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t))] = + { + 0 + }; + + error_code = set_ecdsa_hash_data(message_hash, data_buff, SCE_PRV_HASH_WORD_POS_ECDSA_P192); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + indata_cmd = change_endian_long(SCE_ECC_KEY_LENGTH_192); + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_EcdsaSignatureGenerateSub( + /* Casting uint32_t pointer is used for address. */ + &curvetype, + &indata_cmd, + (uint32_t *) &wrapped_key->value, + (uint32_t *) data_buff, + (uint32_t *) signature->pdata); + signature->data_length = HW_SCE_ECDSA_DATA_BYTE_SIZE; + + return error_code; +} + +/*******************************************************************************************************************//** + * When a message is specified in the first argument, message_hash->data_type, a SHA-256 hash of the message text + * input as the first argument, message_hash->pdata, is calculated, and the signature text is written to the second + * argument, signature, in accordance with secp224r1 using the private wrapped key input as the third argument, + * wrapped_key. + * + * When a hash value is specified in the first argument, message_hash->data_type, the signature text for the first + * 28 bytes of the SHA-256 hash value input to the first argument, message_hash->pdata, is written to the second + * argument, signature, in accordance with secp224r1 using the private wrapped key input as the third argument, + * wrapped_key. + * + * @param[in] message_hash Message or hash value to which to attach signature + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in,out] signature Signature text storage destination information + * @arg signature->pdata : Specifies pointer to array storing signature text + * The signature format is "0 padding (32 bits) || + * signature r (224 bits) || 0 padding (32 bits) || + * signature s (224 bits)". + * @arg signature->data_length : Data length (byte units) + * @param[in] wrapped_key Input wrapped key of secp224r1 private key. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDSA_secp224r1_SignatureGenerate (sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(wrapped_key); +#endif + uint32_t indata_cmd; + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + uint32_t data_buff[SCE_PRV_HASH_WORD_POS_ECDSA_P224 + (HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t))] = + { + 0 + }; + + error_code = set_ecdsa_hash_data(message_hash, data_buff, SCE_PRV_HASH_WORD_POS_ECDSA_P224); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + indata_cmd = change_endian_long(SCE_ECC_KEY_LENGTH_224); + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_EcdsaSignatureGenerateSub( + /* Casting uint32_t pointer is used for address. */ + &curvetype, + &indata_cmd, + (uint32_t *) &wrapped_key->value, + (uint32_t *) data_buff, + (uint32_t *) signature->pdata); + signature->data_length = HW_SCE_ECDSA_DATA_BYTE_SIZE; + + return error_code; +} + +/*******************************************************************************************************************//** + * When a message is specified in the first argument, message_hash->data_type, a SHA-256 hash of the message text + * input as the first argument, message_hash->pdata, is calculated, and the signature text is written to the second + * argument, signature, in accordance with secp256r1 using the private wrapped key input as the third argument, + * wrapped_key. + * + * When a hash value is specified in the first argument, message_hash->data_type, the signature text for the first + * 32 bytes of the SHA-256 hash value input to the first argument, message_hash->pdata, is written to the second + * argument, signature, in accordance with secp256r1 using the private wrapped key input as the third argument, + * wrapped_key. + * + * @param[in] message_hash Message or hash value to which to attach signature + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in,out] signature Signature text storage destination information + * @arg signature->pdata : Specifies pointer to array storing signature text + * The signature format is "signature r (256 bits) || + * signature s (256 bits)". + * @arg signature->data_length : Data length (byte units) + * @param[in] wrapped_key Input wrapped key of secp256r1 private key. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDSA_secp256r1_SignatureGenerate (sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(wrapped_key); +#endif + uint32_t indata_cmd; + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + uint32_t data_buff[SCE_PRV_HASH_WORD_POS_ECDSA_P256 + (HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t))] = + { + 0 + }; + + error_code = set_ecdsa_hash_data(message_hash, data_buff, SCE_PRV_HASH_WORD_POS_ECDSA_P256); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + indata_cmd = change_endian_long(SCE_ECC_KEY_LENGTH_256); + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_EcdsaSignatureGenerateSub( + /* Casting uint32_t pointer is used for address. */ + &curvetype, + &indata_cmd, + (uint32_t *) &wrapped_key->value, + (uint32_t *) data_buff, + (uint32_t *) signature->pdata); + signature->data_length = HW_SCE_ECDSA_DATA_BYTE_SIZE; + + return error_code; +} + +/*******************************************************************************************************************//** + * When a message is specified in the first argument, message_hash->data_type, a SHA-384 hash of the message text + * input as the first argument, message_hash->pdata, is calculated, and the signature text is written to the second + * argument, signature, in accordance with secp384r1 using the private wrapped key input as the third argument, + * wrapped_key. + * + * To use message input, prepare a user-defined function for SHA384. + * + * When a hash value is specified in the first argument, message_hash->data_type, the signature text for the first + * 48 bytes of the SHA-384 hash value input to the first argument, message_hash->pdata, is written to the second + * argument, signature, in accordance with secp384r1 using the private wrapped key input as the third argument, + * wrapped_key. + * + * @param[in] message_hash Message or hash value to which to attach signature + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in,out] signature Signature text storage destination information + * @arg signature->pdata : Specifies pointer to array storing signature text + * The signature format is "signature r (384 bits) || + * signature s (384 bits)". + * @arg signature->data_length : Data length (byte units) + * @param[in] wrapped_key Input wrapped key of secp384r1 private key. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDSA_secp384r1_SignatureGenerate (sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(wrapped_key); +#endif + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + uint32_t data_buff[(HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t))] = + { + 0 + }; + + error_code = set_ecdsa_hash_data(message_hash, data_buff, SCE_PRV_HASH_WORD_POS_ECDSA_P384); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_EcdsaP384SignatureGenerateSub( + /* Casting uint32_t pointer is used for address. */ + &curvetype, + (uint32_t *) &wrapped_key->value, + (uint32_t *) data_buff, + (uint32_t *) signature->pdata); + signature->data_length = HW_SCE_ECDSA_P384_DATA_BYTE_SIZE; + + return error_code; +} + +/*******************************************************************************************************************//** + * When a message is specified in the second argument, message_hash->data_type, a SHA-256 hash of the message text + * input as the second argument, message_hash->pdata, is calculated, and the signature text input to the first argument, + * signature, is validated in accordance with secp192r1 using the public wrapped key input as the third argument, + * wrapped_key. + * + * When a hash value is specified in the second argument, message_hash->data_type, the signature text for the first + * 24 bytes of the SHA-256 hash value input to the second argument, message_hash->pdata, input to the first argument, + * signature, is validated in accordance with secp192r1 using the public wrapped key input as the third argument, + * wrapped_key. + * + * @param[in] signature Signature text information to be verified + * @arg signature->pdata : Specifies pointer to array storing signature text + * The signature format is "0 padding (64 bits) || + * signature r (192 bits) || 0 padding (64 bits) || + * signature s (192 bits)". + * @arg signature->data_length : Specifies the data length (byte units) (nonuse) + * @param[in,out] message_hash Message or hash value to be verified + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in] wrapped_key Input wrapped key of secp192r1 public key. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred or signature verification failed. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDSA_secp192r1_SignatureVerify (sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(wrapped_key); +#endif + uint32_t indata_cmd; + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + uint32_t data_buff[SCE_PRV_HASH_WORD_POS_ECDSA_P192 + (HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t))] = + { + 0 + }; + + error_code = set_ecdsa_hash_data(message_hash, data_buff, SCE_PRV_HASH_WORD_POS_ECDSA_P192); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + indata_cmd = change_endian_long(SCE_ECC_KEY_LENGTH_192); + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_EcdsaSignatureVerificationSub( + /* Casting uint32_t pointer is used for address. */ + &curvetype, + &indata_cmd, + (uint32_t *) &wrapped_key->value, + (uint32_t *) data_buff, + (uint32_t *) signature->pdata); + + return error_code; +} + +/*******************************************************************************************************************//** + * When a message is specified in the second argument, message_hash->data_type, a SHA-256 hash of the message text + * input as the second argument, message_hash->pdata, is calculated, and the signature text input to the first argument, + * signature, is validated in accordance with secp224r1 using the public wrapped key input as the third argument, + * wrapped_key. + * + * When a hash value is specified in the second argument, message_hash->data_type, the signature text for the first + * 28 bytes of the SHA-256 hash value input to the second argument, message_hash->pdata, input to the first argument, + * signature, is validated in accordance with secp224r1 using the public wrapped key input as the third argument, + * wrapped_key. + * + * @param[in] signature Signature text information to be verified + * @arg signature->pdata : Specifies pointer to array storing signature text + * The signature format is "0 padding (32 bits) || + * signature r (224 bits) || 0 padding (32 bits) || + * signature s (224 bits)". + * @arg signature->data_length : Specifies the data length (byte units) (nonuse) + * @param[in,out] message_hash Message or hash value to be verified + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in] wrapped_key Input wrapped key of secp224r1 public key. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred or signature verification failed. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDSA_secp224r1_SignatureVerify (sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(wrapped_key); +#endif + uint32_t indata_cmd; + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + uint32_t data_buff[SCE_PRV_HASH_WORD_POS_ECDSA_P224 + (HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t))] = + { + 0 + }; + + error_code = set_ecdsa_hash_data(message_hash, data_buff, SCE_PRV_HASH_WORD_POS_ECDSA_P224); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + indata_cmd = change_endian_long(SCE_ECC_KEY_LENGTH_224); + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_EcdsaSignatureVerificationSub( + /* Casting uint32_t pointer is used for address. */ + &curvetype, + &indata_cmd, + (uint32_t *) &wrapped_key->value, + (uint32_t *) data_buff, + (uint32_t *) signature->pdata); + + return error_code; +} + +/*******************************************************************************************************************//** + * When a message is specified in the second argument, message_hash->data_type, a SHA-256 hash of the message text + * input as the second argument, message_hash->pdata, is calculated, and the signature text input to the first argument, + * signature, is validated in accordance with secp256r1 using the public wrapped key input as the third argument, + * wrapped_key. + * + * When a hash value is specified in the second argument, message_hash->data_type, the signature text for the first + * 32 bytes of the SHA-256 hash value input to the second argument, message_hash->pdata, input to the first argument, + * signature, is validated in accordance with secp256r1 using the public wrapped key input as the third argument, + * wrapped_key. + * + * @param[in] signature Signature text information to be verified + * @arg signature->pdata : Specifies pointer to array storing signature text + * The signature format is "signature r (256 bits) || + * signature s (256 bits)". + * @arg signature->data_length : Specifies the data length (byte units) (nonuse) + * @param[in,out] message_hash Message or hash value to be verified + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in] wrapped_key Input wrapped key of secp256r1 public key. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred or signature verification failed. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDSA_secp256r1_SignatureVerify (sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t error_code = FSP_SUCCESS; + uint32_t data_buff[SCE_PRV_HASH_WORD_POS_ECDSA_P256 + (HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t))] = + { + 0 + }; + + error_code = set_ecdsa_hash_data(message_hash, data_buff, SCE_PRV_HASH_WORD_POS_ECDSA_P256); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + error_code = R_SCE_EcdsaNistP256SignatureVerificationSub( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) data_buff, + (uint32_t *) signature->pdata); + + return error_code; +} + +/*******************************************************************************************************************//** + * When a message is specified in the second argument, message_hash->data_type, a SHA-256 hash of the message text + * input as the second argument, message_hash->pdata, is calculated, and the signature text input to the first argument, + * signature, is validated in accordance with secp384r1 using the public wrapped key input as the third argument, + * wrapped_key. + * + * To use message input, prepare a user-defined function for SHA384. + * + * When a hash value is specified in the second argument, message_hash->data_type, the signature text for the first + * 48 bytes of the SHA-256 hash value input to the second argument, message_hash->pdata, input to the first argument, + * signature, is validated in accordance with secp384r1 using the public wrapped key input as the third argument, + * wrapped_key. + * + * @param[in] signature Signature text information to be verified + * @arg signature->pdata : Specifies pointer to array storing signature text + * The signature format is "signature r (384 bits) || + * signature s (384 bits)". + * @arg signature->data_length : Specifies the data length (byte units) (nonuse) + * @param[in,out] message_hash Message or hash value to be verified + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in] wrapped_key Input wrapped key of secp384r1 public key. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred or signature verification failed. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDSA_secp384r1_SignatureVerify (sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(wrapped_key); +#endif + uint32_t curvetype; + fsp_err_t error_code = FSP_SUCCESS; + uint32_t data_buff[(HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t))] = + { + 0 + }; + + error_code = set_ecdsa_hash_data(message_hash, data_buff, SCE_PRV_HASH_WORD_POS_ECDSA_P384); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + curvetype = change_endian_long(SCE_ECC_CURVE_TYPE_NIST); + error_code = R_SCE_EcdsaP384SignatureVerificationSub( + /* Casting uint32_t pointer is used for address. */ + &curvetype, + (uint32_t *) &wrapped_key->value, + (uint32_t *) data_buff, + (uint32_t *) signature->pdata); + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_ECDH_secp256r1_Init() function prepares to perform ECDH key exchange computation and writes the result to + * the first argument, handle. The succeeding functions R_SCE_ECDH_secp256r1_PublicKeySign(), + * R_SCE_ECDH_secp256r1_PublicKeyVerify(), R_SCE_ECDH_secp256r1_SharedSecretCalculate(), + * and R_SCE_ECDH_secp256r1_KeyDerivation() use handle as an argument. + * + * Use the second argument, key_type, to select the type of ECDH key exchange. When ECDHE is selected, + * the R_SCE_ECDH_secp256r1_PublicKeySign() function uses the SCE's random number generation functionality to generate + * an secp256r1 key pair. When ECDH is selected, keys installed beforehand are used for key exchange. + * + * Input 1 as the third argument, use_key_id, to use key_id when key exchange is performed. key_id is for applications + * conforming to the DLMS/COSEM standard for smart meters. + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] key_type Key exchange type (0: ECDHE, 1: ECDH, 2:ECDH(AES-GCM-128 with IV)) + * @param[in] use_key_id 0: key_id not used, 1: key_id used + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDH_secp256r1_Init (sce_ecdh_handle_t * handle, uint32_t key_type, uint32_t use_key_id) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); +#endif + fsp_err_t error_code = FSP_SUCCESS; + if ((2 >= key_type) && (1 >= use_key_id)) + { + memset(handle, 0, sizeof(sce_ecdh_handle_t)); + handle->flag_call_init = 1; + g_private_id_counter++; + g_ecdh256_private_id = g_private_id_counter; + handle->id = g_ecdh256_private_id; + handle->key_type = key_type; + handle->flag_use_key_id = use_key_id; + } + else + { + error_code = FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_ECDH_secp256r1_PublicKeySign() function calculates a signature for a public key user wrapped key used for + * ECDH key exchange. + * + * If ECDHE is specified by the key_type argument of the R_SCE_ECDH_secp256r1_Init() function, the SCE's random number + * generation functionality is used to generate an secp256r1 key pair. The public key is output to public_key + * and the private key is output to wrapped_key. + * + * If ECDH is specified by the key_type argument of the R_SCE_ECDH_secp256r1_Init() function, the public key input + * as ecc_public_wrapped_key is output to public_key and nothing is output to wrapped_key. + * + * The succeeding function R_SCE_ECDH_secp256r1_SharedSecretCalculate() uses the first argument, handle, as an argument. + * R_SCE_ECDH_secp256r1_SharedSecretCalculate() function uses wrapped_key as input to calculate Z. + * + * @param[in,out] handle ECDH handler (work area) + * When using key_id, input handle->key_id after running R_SCE_ECDH_secp256r1_Init(). + * @param[in] ecc_public_wrapped_key For ECDHE, input a null pointer. + * For ECDH, input the wrapped key of a secp256r1 public key. + * @param[in] ecc_private_wrapped_key secp256r1 private key for signature generation + * @param[in,out] public_key User secp256r1 public key (512-bit) for key exchange. + * When using key_id, + * key_id (8-bit) || public key (512-bit) || 0 padding (24-bit) + * @param[in,out] signature Signature text storage destination information + * @arg signature->pdata : Specifies pointer to array storing signature text. + * The signature format is "signature r (256 bits) || + * signature s (256 bits)" + * @arg signature->data_length : Data length (in byte units) + * @param[in,out] wrapped_key For ECDHE, a private wrapped key generated from a random number. + * Not output for ECDH. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeySign (sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + uint8_t * public_key, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(ecc_public_wrapped_key || (0 == handle->key_type)); // 0 = ECDHE + FSP_ASSERT(ecc_private_wrapped_key); + FSP_ASSERT(public_key); + FSP_ASSERT(signature); + FSP_ASSERT(wrapped_key); +#endif + uint32_t indata_cmd = 0; + uint32_t ecdh_key_type = 0; + uint32_t key_id = 0; + fsp_err_t error_code = FSP_SUCCESS; + + if ((0 == handle->flag_call_init) || (1 == handle->flag_call_make_public)) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_ecdh256_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->flag_call_make_public = 1; + + if (1 == handle->key_type) + { + ecdh_key_type = change_endian_long(1); + } + + if (1 == handle->flag_use_key_id) + { + indata_cmd = change_endian_long(1); + key_id = change_endian_long(handle->key_id & SCE_HEX_FF); + } + else + { + indata_cmd = change_endian_long(0); + } + + error_code = R_SCE_EcdhMakePublicKeyPrivate(&indata_cmd, + &ecdh_key_type, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &ecc_public_wrapped_key->value, + (uint32_t *) &ecc_private_wrapped_key->value, + &key_id, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) public_key, + (uint32_t *) signature->pdata, + (uint32_t *) &wrapped_key->value); + signature->data_length = HW_SCE_ECDSA_DATA_BYTE_SIZE; + if (1 != handle->key_type) + { + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_ECDH_secp256r1_PublicKeyVerify() function verifies the signature of the secp256r1 public key of the other + * ECDH key exchange party. If the signature is correct, it outputs the public wrapped key to the fifth argument. + * The first argument, handle, is used as an argument in the subsequent function + * R_SCE_ECDH_secp256r1_SharedSecretCalculate(). + * R_SCE_ECDH_secp256r1_SharedSecretCalculate() uses wrapped_key as input to calculate Z. + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] ecc_public_wrapped_key Public wrapped key area for signature verification + * @param[in] public_key_data secp256r1 public key (512-bit). When key_id is used: + * key_id (8-bit) || public key (512-bit) + * @param[in] signature ECDSA secp256r1 signature of ecc_public_wrapped_key + * @param[in,out] wrapped_key wrapped key of ecc_public_wrapped_key + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred or signature verification failed. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeyVerify (sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + uint8_t * public_key_data, + sce_ecdsa_byte_data_t * signature, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(ecc_public_wrapped_key); + FSP_ASSERT(public_key_data); + FSP_ASSERT(signature); + FSP_ASSERT(wrapped_key); +#endif + st_read_public_key_t indata = + { + 0 + }; + fsp_err_t error_code = FSP_SUCCESS; + + if ((0 == handle->flag_call_init) || (1 == handle->flag_call_read_public)) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_ecdh256_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->flag_call_read_public = 1; + + if (1 == handle->flag_use_key_id) + { + indata.cmd = change_endian_long(1); + memcpy(indata.bytedata, public_key_data, 1 + HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE); /* key_id || QeU copy */ + indata.bytedata[1 + HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE] = SCE_HEX_80; /* stop bit */ + indata.bytedata[SCE_PRV_INDATA_BYTEDATA_LEN - 2] = 0x02; + indata.bytedata[SCE_PRV_INDATA_BYTEDATA_LEN - 1] = 0x08; /* message length is 520bit */ + } + else + { + indata.cmd = change_endian_long(0); + memcpy(indata.bytedata, public_key_data, HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE); /* QeU copy */ + indata.bytedata[HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE] = SCE_HEX_80; /* stop bit */ + indata.bytedata[SCE_PRV_INDATA_BYTEDATA_LEN - 2] = 0x02; + indata.bytedata[SCE_PRV_INDATA_BYTEDATA_LEN - 1] = 0x00; /* message length is 512bit */ + } + + error_code = R_SCE_EcdhReadPublicKeyPrivate(&indata.cmd, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &ecc_public_wrapped_key->value, + (uint32_t *) indata.bytedata, + (uint32_t *) signature->pdata, + (uint32_t *) + &wrapped_key->value); + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_ECDH_secp256r1_PublicKeyReadWithoutSignature() function reads the secp256r1 public key of the other + * ECDH key exchange party and outputs the public wrapped key to the third argument. + * The first argument, handle, is used as an argument in the subsequent function + * R_SCE_ECDH_secp256r1_SharedSecretCalculate(). + * R_SCE_ECDH_secp256r1_SharedSecretCalculate() uses wrapped_key as input to calculate Z. + * This API does not verify signature of public_key_data, please protect this data by upper layer software. + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] public_key_data secp256r1 public key (512-bit). When key_id is used: + * key_id (8-bit) || public key (512-bit) + * @param[in,out] wrapped_key wrapped key of public_key_data + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * @note Please note that this is slightly contrary to the protected mode policy as it omits signature verification. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeyReadWithoutSignature (sce_ecdh_handle_t * handle, + uint8_t * public_key_data, + sce_ecc_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(public_key_data); + FSP_ASSERT(wrapped_key); +#endif + + st_read_public_key_t indata = + { + 0 + }; + fsp_err_t error_code = FSP_SUCCESS; + + if ((0 == handle->flag_call_init) || (1 == handle->flag_call_read_public)) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_ecdh256_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->flag_call_read_public = 1; + + if (1 == handle->flag_use_key_id) + { + indata.cmd = change_endian_long(1); + memcpy(indata.bytedata, public_key_data, 1 + HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE); /* key_id || QeU copy */ + indata.bytedata[1 + HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE] = SCE_HEX_80; /* stop bit */ + indata.bytedata[SCE_PRV_INDATA_BYTEDATA_LEN - 2] = 0x02; + indata.bytedata[SCE_PRV_INDATA_BYTEDATA_LEN - 1] = 0x08; /* message length is 520bit */ + } + else + { + indata.cmd = change_endian_long(0); + memcpy(indata.bytedata, public_key_data, HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE); /* QeU copy */ + indata.bytedata[HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE] = SCE_HEX_80; /* stop bit */ + indata.bytedata[SCE_PRV_INDATA_BYTEDATA_LEN - 2] = 0x02; + indata.bytedata[SCE_PRV_INDATA_BYTEDATA_LEN - 1] = 0x00; /* message length is 512bit */ + } + + error_code = R_SCE_EcdhReadPublicKeyWithoutSignaturePrivate(&indata.cmd, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) indata.bytedata, + (uint32_t *) &wrapped_key->value); + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_ECDH_secp256r1_SharedSecretCalculate() function uses the ECDH key exchange algorithm to output the + * wrapped key of the shared secret Z derived from the public key of the other key exchange party and your own private + * key. + * Input as the second argument, ecc_public_wrapped_key, the public wrapped key whose signature was verified + * by R_SCE_ECDH_secp256r1_PublicKeyVerify(). + * When key_type of R_SCE_ECDH_secp256r1_Init() is 0, input as the third argument, ecc_private_wrapped_key, + * the private wrapped key generated from a random number by R_SCE_ECDH_secp256r1_PublicKeySign(), and when key_type is + * other than 0, input the private wrapped key that forms a pair with the second argument of + * R_SCE_ECDH_secp256r1_PublicKeySign(). + * The subsequent R_SCE_ECDH_secp256r1_KeyDerivation() function uses shared_secret_wrapped_key as key material + * for outputting the wrapped key. + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] ecc_public_wrapped_key Public wrapped key whose signature was verified by + * R_SCE_ECDH_secp256r1_PublicKeyVerify() + * @param[in] ecc_private_wrapped_key Private wrapped key + * @param[in,out] shared_secret_wrapped_key Wrapped key of shared secret Z calculated by ECDH key exchange + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDH_secp256r1_SharedSecretCalculate (sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(ecc_public_wrapped_key); + FSP_ASSERT(ecc_private_wrapped_key); + FSP_ASSERT(shared_secret_wrapped_key); +#endif + uint32_t ecdh_key_type = 0; + fsp_err_t error_code = FSP_SUCCESS; + + if (0 == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_ecdh256_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->flag_call_shared_secret = 1; + + ecdh_key_type = change_endian_long(handle->key_type); + + error_code = R_SCE_EcdhCalculateSharedSecretIndexPrivate(&ecdh_key_type, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &ecc_public_wrapped_key->value, + (uint32_t *) &ecc_private_wrapped_key->value, + (uint32_t *) &shared_secret_wrapped_key->value); + if (FSP_SUCCESS == error_code) + { + if (3 == handle->key_type) + { + shared_secret_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES128_GCM_WITH_IV; + } + else + { + shared_secret_wrapped_key->type = SCE_KEY_INDEX_TYPE_ECDH_SHARED_SECRET; + } + } + else + { + shared_secret_wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_ECDH_secp256r1_KeyDerivation() function uses the shared secret "Z (shared_secret_index)" calculated + * by the R_SCE_ECDH_secp256r1_SharedSecretCalculate() function as the key material to derive the wrapped key + * specified by the third argument, key_type. The key derivation algorithm is one-step key derivation as defined + * in NIST SP800-56C. Either SHA-256 or SHA-256 HMAC is specified by the fourth argument, kdf_type. + * When SHA-256 HMAC is specified, the wrapped key output by the R_SCE_SHA256HMAC_EncryptedKeyWrap() function + * is specified as the seventh argument, salt_wrapped_key. + * Enter a fixed value for deriving a key shared with the key exchange partner in the fifth argument, other_info. + * A wrapped key corresponding to key_type is output as the eighth argument, wrapped_key. The correspondences + * between the types of derived wrapped_key and the functions with which they can be used as listed below. + * - AES-128: All AES-128 Init functions + * - AES-256: All AES-256 Init functions + * - SHA256-HMAC: R_SCE_SHA256HMAC_GenerateInit() function and R_SCE_SHA256HMAC_VerifyInit() function + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] shared_secret_wrapped_key Z wrapped key calculated by R_SCE_ECDH_secp256r1_SharedSecretCalculate + * @param[in] key_type Derived key type (0: AES-128, 1: AES-256, 2:SHA256-HMAC, 3: AES-GCM-128 with IV) + * @param[in] kdf_type Algorithm used for key derivation calculation (0: SHA-256, 1:SHA256-HMAC) + * @param[in] other_info Additional data used for key derivation calculation: + * AlgorithmID || PartyUInfo || PartyVInfo + * @param[in] other_info_length Data length of other_info (up to 147 byte units) + * @param[in] salt_wrapped_key Salt wrapped key (Input NULL when kdf_type is 0.) + * @param[in,out] wrapped_key Wrapped key corresponding to key_type. + * When the value of key_type is 2, an SHA256-HMAC wrapped key is output. + * wrapped_key can be specified by casting the start address of the area reserved + * beforehand by the sce_hmac_sha_wrapped_key_t type with the + * (sce_aes_wrapped_key_t*) type. + * + * @retval FSP_SUCCESS Normal end + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource required + * by the processing is in use by other processing. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECDH_secp256r1_KeyDerivation (sce_ecdh_handle_t * handle, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key, + uint32_t key_type, + uint32_t kdf_type, + uint8_t * other_info, + uint32_t other_info_length, + sce_hmac_sha_wrapped_key_t * salt_wrapped_key, + sce_aes_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(shared_secret_wrapped_key); + FSP_ASSERT(other_info || (0 == other_info_length)); + FSP_ASSERT(salt_wrapped_key || (0 == kdf_type)); /* 0: SHA-256 */ + FSP_ASSERT(wrapped_key); +#endif + + /* InData_PaddedMsg = AlgorithmID || PartyUInfo || PartyVInfo || 1 || 0padding || Message length(64bit) + * Message length value = AlgorithmID bit length + PartyUInfo bit length + PartyVInfo bit length + 288bit + * MAX_CNT(word) = 7 + 16n */ + + fsp_err_t error_code = FSP_SUCCESS; + st_key_derivation_t indata = + { + 0 + }; + uint32_t message_bit_length = 0; + + if (0 == handle->flag_call_shared_secret) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = 0; + handle->flag_call_make_public = 0; + handle->flag_call_read_public = 0; + handle->flag_call_shared_secret = 0; + if (handle->id != g_ecdh256_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (3 == key_type) + { + if (2 == handle->key_type) + { + memcpy(wrapped_key->value, shared_secret_wrapped_key->value, sizeof(wrapped_key->value)); + wrapped_key->type = SCE_KEY_INDEX_TYPE_AES128_GCM_WITH_IV; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + error_code = FSP_ERR_CRYPTO_SCE_FAIL; + } + + memset(handle, 0, sizeof(sce_ecdh_handle_t)); + + return error_code; + } + + /* 147 = SCE_PRV_OTHER_INFO_BYTE_LEN_3B - 9 */ + if (((2 < key_type) || (1 < kdf_type)) || ((SCE_PRV_OTHER_INFO_BYTE_LEN_3B - 9) < other_info_length)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + message_bit_length = (other_info_length * 8) + SCE_PRV_OTHER_INFO_BYTE_LEN_SUPP; + if (0 != kdf_type) + { + message_bit_length += (SCE_DEC_64 * 8); + } + + memcpy(indata.paddedmsg, other_info, other_info_length); + indata.paddedmsg[other_info_length] = SCE_HEX_80; /* stop bit */ + + if ((SCE_PRV_OTHER_INFO_BYTE_LEN_2B - 9) >= other_info_length) + { + /* another block unnecessary */ + /* Casting uint32_t data to uint8_t data array. */ + indata.paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_2B - 4] = (uint8_t) ((message_bit_length >> 24) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + indata.paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_2B - 3] = (uint8_t) ((message_bit_length >> 16) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + indata.paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_2B - 2] = (uint8_t) ((message_bit_length >> 8) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + indata.paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_2B - 1] = (uint8_t) ((message_bit_length) & SCE_HEX_FF); + indata.max_cnt_byte = SCE_PRV_OTHER_INFO_BYTE_LEN_2B; + } + else + { + /* Casting uint32_t data to uint8_t data array. */ + indata.paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_3B - 4] = (uint8_t) ((message_bit_length >> 24) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + indata.paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_3B - 3] = (uint8_t) ((message_bit_length >> 16) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + indata.paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_3B - 2] = (uint8_t) ((message_bit_length >> 8) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + indata.paddedmsg[SCE_PRV_OTHER_INFO_BYTE_LEN_3B - 1] = (uint8_t) ((message_bit_length) & SCE_HEX_FF); + indata.max_cnt_byte = SCE_PRV_OTHER_INFO_BYTE_LEN_3B; + } + + indata.keyindextype = change_endian_long(key_type); + indata.kdftype = change_endian_long(kdf_type); + + error_code = R_SCE_EcdhKeyDerivationPrivate(&indata.keyindextype, + shared_secret_wrapped_key->value, + &indata.kdftype, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) indata.paddedmsg, + indata.max_cnt_byte >> 2, + salt_wrapped_key->value, + wrapped_key->value); + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = s_key_index_type[key_type]; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + memset(handle, 0, sizeof(sce_ecdh_handle_t)); + + return error_code; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * For messages, SHA hash operation is performed and the hash value is set according to ECDSA. + * + * @param p_message_hash message or hash value information + * @param data_buff pointer to the hash value area, including 0 padding + * @param hash_word_pos hash value output word position from the beginning of the data_buff + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input parameter illegal + * @retval FSP_ERR_CRYPTO_SCE_FAIL Internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + **********************************************************************************************************************/ +static fsp_err_t set_ecdsa_hash_data (sce_ecdsa_byte_data_t * p_message_hash, + uint32_t * data_buff, + uint32_t hash_word_pos) +{ + fsp_err_t error_code = FSP_SUCCESS; + sce_sha_md5_handle_t ex_sha_handle = + { + 0 + }; + uint32_t hash_length = 0; + + if (0 == p_message_hash->data_type) + { + if (SCE_PRV_HASH_WORD_POS_ECDSA_P384 != hash_word_pos) + { + R_SCE_SHA256_Init(&ex_sha_handle); + error_code = R_SCE_SHA256_Update(&ex_sha_handle, p_message_hash->pdata, p_message_hash->data_length); + if (FSP_SUCCESS == error_code) + { + /* Casting uint8_t pointer is used for address. */ + error_code = R_SCE_SHA256_Final(&ex_sha_handle, (uint8_t *) &data_buff[hash_word_pos], &hash_length); + } + } + else + { +#if SCE_USER_SHA_384_ENABLED != 0 + + /* Casting uint8_t pointer is used for address. */ + if (0 != + SCE_USER_SHA_384_FUNCTION(p_message_hash->pdata, (uint8_t *) data_buff, p_message_hash->data_length)) +#else +#endif /* SCE_USER_SHA_384_ENABLED != 0 */ + { + error_code = FSP_ERR_CRYPTO_SCE_FAIL; + } + } + } + else if (1 == p_message_hash->data_type) + { + if (SCE_PRV_HASH_WORD_POS_ECDSA_P384 != hash_word_pos) + { + memcpy(&data_buff[hash_word_pos], + p_message_hash->pdata, + HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE - hash_word_pos * sizeof(uint32_t)); + } + else + { + memcpy(data_buff, p_message_hash->pdata, HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE); + } + } + else + { + error_code = FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + return error_code; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c new file mode 100644 index 0000000000..18a45e1bfb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c @@ -0,0 +1,1416 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sce_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define SCE_RSA_SIG_SHA256_PREFIX_00 0x30 +#define SCE_RSA_SIG_SHA256_PREFIX_01 0x31 +#define SCE_RSA_SIG_SHA256_PREFIX_02 0x30 +#define SCE_RSA_SIG_SHA256_PREFIX_03 0x0d +#define SCE_RSA_SIG_SHA256_PREFIX_04 0x06 +#define SCE_RSA_SIG_SHA256_PREFIX_05 0x09 +#define SCE_RSA_SIG_SHA256_PREFIX_06 0x60 +#define SCE_RSA_SIG_SHA256_PREFIX_07 0x86 +#define SCE_RSA_SIG_SHA256_PREFIX_08 0x48 +#define SCE_RSA_SIG_SHA256_PREFIX_09 0x01 +#define SCE_RSA_SIG_SHA256_PREFIX_10 0x65 +#define SCE_RSA_SIG_SHA256_PREFIX_11 0x03 +#define SCE_RSA_SIG_SHA256_PREFIX_12 0x04 +#define SCE_RSA_SIG_SHA256_PREFIX_13 0x02 +#define SCE_RSA_SIG_SHA256_PREFIX_14 0x01 +#define SCE_RSA_SIG_SHA256_PREFIX_15 0x05 +#define SCE_RSA_SIG_SHA256_PREFIX_16 0x00 +#define SCE_RSA_SIG_SHA256_PREFIX_17 0x04 +#define SCE_RSA_SIG_SHA256_PREFIX_18 0x20 + +#ifndef SCE_HEX_FF + #define SCE_HEX_FF 0xff +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static fsp_err_t calc_hash_data(uint8_t * p_mes, uint8_t * p_hash, uint32_t mes_len, uint8_t hash_type); +static fsp_err_t set_rsassapkcs_hash_data(sce_rsa_byte_data_t * p_message_hash, + uint8_t hash_type, + uint32_t rsa_key_byte_size, + uint8_t * data_buff); +static uint32_t get_keyn_size(uint32_t * prsa_key_index, uint32_t key_max_size); +static fsp_err_t get_rand_rsaes_pkcs(uint32_t rand_size, uint8_t * prand_data); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +static uint8_t gs_rsa_sig_sha256_prefix[] = +{ + SCE_RSA_SIG_SHA256_PREFIX_00, + SCE_RSA_SIG_SHA256_PREFIX_01, + SCE_RSA_SIG_SHA256_PREFIX_02, + SCE_RSA_SIG_SHA256_PREFIX_03, + SCE_RSA_SIG_SHA256_PREFIX_04, + SCE_RSA_SIG_SHA256_PREFIX_05, + SCE_RSA_SIG_SHA256_PREFIX_06, + SCE_RSA_SIG_SHA256_PREFIX_07, + SCE_RSA_SIG_SHA256_PREFIX_08, + SCE_RSA_SIG_SHA256_PREFIX_09, + SCE_RSA_SIG_SHA256_PREFIX_10, + SCE_RSA_SIG_SHA256_PREFIX_11, + SCE_RSA_SIG_SHA256_PREFIX_12, + SCE_RSA_SIG_SHA256_PREFIX_13, + SCE_RSA_SIG_SHA256_PREFIX_14, + SCE_RSA_SIG_SHA256_PREFIX_15, + SCE_RSA_SIG_SHA256_PREFIX_16, + SCE_RSA_SIG_SHA256_PREFIX_17, + SCE_RSA_SIG_SHA256_PREFIX_18 +}; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup SCE_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * The R_SCE_RSASSA_PKCS1024_SignatureGenerate() function generates, in accordance with RSASSA-PKCS1-V1_5, a signature + * from the message text or hash value that is input in the first argument, message_hash, using the private wrapped + * key input to the third argument, wrapped_key, and writes the signature text to the second argument, signature. + * When a message is specified in the first argument, message_hash->data_type, a hash value is calculated for + * the message as specified by the fourth argument, hash_type. When specifying a hash value in the first argument, + * message_hash->data_type, a hash value calculated with a hash algorithm as specified by the fourth argument, + * hash_type, must be input to message_hash->pdata. + * + * @param[in] message_hash Message or hash value to which to attach signature + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in,out] signature Signature text storage destination information + * @arg signature->pdata : Specifies pointer to array storing the signature text + * @arg signature->data_length : data length + * @param[in] wrapped_key Inputs the 1024-bit RSA private wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSASSA_PKCS1024_SignatureGenerate (sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa1024_private_wrapped_key_t * wrapped_key, + uint8_t hash_type) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t error_code = FSP_SUCCESS; + uint8_t data_buff[HW_SCE_RSA_1024_DATA_BYTE_SIZE] = + { + 0 + }; + + error_code = set_rsassapkcs_hash_data(message_hash, hash_type, HW_SCE_RSA_1024_DATA_BYTE_SIZE, data_buff); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + error_code = R_SCE_Rsa1024ModularExponentDecryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (data_buff), + (uint32_t *) (signature->pdata)); + + signature->data_length = HW_SCE_RSA_1024_DATA_BYTE_SIZE; + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSASSA_PKCS1024_SignatureVerify() function verifies, in accordance with RSASSA-PKCS1-V1_5, the signature text + * input to the first argument signature, and the message text or hash value input to the second argument, + * message_hash, using the public wrapped key input to the third argument, wrapped_key. When a message is specified + * in the second argument, message_hash->data_type, a hash value is calculated using the public wrapped key input to + * the third argument, wrapped_key, and as specified by the fourth argument, hash_type. When specifying a hash value + * in the second argument, message_hash->data_type, a hash value calculated with a hash algorithm as specified by the + * fourth argument, hash_type, must be input to message_hash->pdata. + * + * @param[in] signature Signature text information to verify + * @arg signature->pdata : Specifies pointer to array storing the signature text + * @arg signature->data_length : Specifies effective data length of the array + * @param[in] message_hash Message text or hash value to verify + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in] wrapped_key Inputs the 1024-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication failed + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSASSA_PKCS1024_SignatureVerify (sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa1024_public_wrapped_key_t * wrapped_key, + uint8_t hash_type) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t error_code = FSP_SUCCESS; + uint8_t data_buff[HW_SCE_RSA_1024_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t decrypt_data[HW_SCE_RSA_1024_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t data_ptr = 0; + + if (signature->data_length > HW_SCE_RSA_1024_DATA_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + data_ptr = HW_SCE_RSA_1024_DATA_BYTE_SIZE - signature->data_length; + memcpy(data_buff + data_ptr, signature->pdata, signature->data_length); + + error_code = R_SCE_Rsa1024ModularExponentEncryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (data_buff), + (uint32_t *) (decrypt_data)); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + error_code = set_rsassapkcs_hash_data(message_hash, hash_type, HW_SCE_RSA_1024_DATA_BYTE_SIZE, data_buff); + if (FSP_SUCCESS == error_code) + { + if (memcmp(data_buff, decrypt_data, HW_SCE_RSA_1024_DATA_BYTE_SIZE)) + { + error_code = FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSAES_PKCS1024_Encrypt() function RSA-encrypts the plaintext input to the first argument, plain, + * according to RSAES-PKCS1-V1_5. It writes the encryption result to the second argument, cipher. + * + * @param[in] plain plaintext + * @arg plain->pdata : Specifies pointer to array containing plaintext. + * @arg plain->data_length : Specifies valid data length of plaintext array. + * data size <= public key n size - 11 + * @param[in,out] cipher ciphertext + * @arg cipher->pdata : Specifies pointer to array containing ciphertext. + * @arg cipher->data_length : Inputs ciphertext buffer size. + * Outputs valid data length after encryption + * (public key n size). + * @param[in] wrapped_key Inputs the 1024-bit RSA public wrapped key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Incorrect wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSAES_PKCS1024_Encrypt (sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa1024_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(plain); + FSP_ASSERT(plain->pdata); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher->pdata); + FSP_ASSERT(wrapped_key); +#endif + + fsp_err_t ercd = FSP_SUCCESS; + uint8_t input_data_arry[HW_SCE_RSA_1024_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t output_data_arry[HW_SCE_RSA_1024_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t key_size = 0; + uint32_t ptr = 0; + + /* Casting uint32_t pointer is used for address. */ + key_size = get_keyn_size((uint32_t *) &wrapped_key->value.key_n, HW_SCE_RSA_1024_DATA_BYTE_SIZE); + if (key_size < HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((plain->data_length) > (key_size - HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (cipher->data_length < key_size) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + cipher->data_length = key_size; + + /*** RSAES-PKCS#1_V1.5 format ***/ + /* (1) | (2) | (3) | (4) | (5) */ + /* EM = [0x00] | [0x02] | [PS] | [0x00] | [M] */ + ptr = HW_SCE_RSA_1024_DATA_BYTE_SIZE - key_size; + input_data_arry[ptr] = 0x00; + ptr++; + input_data_arry[ptr] = 0x02; + ptr++; + + get_rand_rsaes_pkcs(((key_size - plain->data_length) - 3), &input_data_arry[ptr]); + ptr += ((key_size - plain->data_length) - 3); + input_data_arry[ptr] = 0x00; + ptr++; + + memcpy(&input_data_arry[ptr], plain->pdata, plain->data_length); + + ercd = R_SCE_Rsa1024ModularExponentEncryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (input_data_arry), + (uint32_t *) (output_data_arry)); + memcpy(cipher->pdata, &output_data_arry[HW_SCE_RSA_1024_DATA_BYTE_SIZE - key_size], cipher->data_length); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSAES_PKCS1024_Decrypt() function RSA-decrypts the ciphertext input to the first argument, cipher, + * according to RSAES-PKCS1-V1_5. It writes the decryption result to the second argument, plain. + * + * @param[in] cipher ciphertext + * @arg cipher->pdata : Specifies pointer to array containing ciphertext. + * @arg cipher->data_length : Inputs ciphertext buffer size. + * Outputs valid data length after encryption + * (public key n size). + * @param[in,out] plain plaintext + * @arg plain->pdata : Specifies pointer to array containing plaintext. + * @arg plain->data_length : Inputs plaintext buffer size. + * The following size is required. + * Plaintext buffer size >= public key n size -11. + * Outputs valid data length after decryption + * (public key n size). + * @param[in] wrapped_key Inputs the 1024-bit RSA private wrapped key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Incorrect wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSAES_PKCS1024_Decrypt (sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa1024_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(cipher); + FSP_ASSERT(cipher->pdata); + FSP_ASSERT(plain); + FSP_ASSERT(plain->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t ercd = FSP_SUCCESS; + uint8_t input_data_arry[HW_SCE_RSA_1024_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t output_data_arry[HW_SCE_RSA_1024_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t key_size = 0; + uint32_t ptr = 0; + uint32_t ptr_start = 0; + uint8_t * p_start = 0; + uint8_t * p_zero_ptr = 0; + + /* Casting uint32_t pointer is used for address. */ + key_size = get_keyn_size((uint32_t *) &wrapped_key->value.key_n, HW_SCE_RSA_1024_DATA_BYTE_SIZE); + if (key_size < HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (cipher->data_length != key_size) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (plain->data_length < (key_size - HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + memcpy(&input_data_arry[HW_SCE_RSA_1024_DATA_BYTE_SIZE - key_size], cipher->pdata, cipher->data_length); + ercd = R_SCE_Rsa1024ModularExponentDecryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (input_data_arry), + (uint32_t *) (output_data_arry)); + if (FSP_SUCCESS != ercd) + { + return ercd; + } + + /*** RSAES-PKCS#1_V1.5 format ***/ + /* (1) | (2) | (3) | (4) | (5) */ + /* EM = [0x00] | [0x02] | [PS] | [0x00] | [M] */ + ptr = HW_SCE_RSA_1024_DATA_BYTE_SIZE - key_size; + ptr_start = ptr; + + /* (1) */ + if (0x00 != output_data_arry[ptr]) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + ptr++; + + /* (2) */ + if (0x02 != output_data_arry[ptr]) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + ptr++; + + /* (3) and (4) */ + p_start = &output_data_arry[ptr]; + + /* Casting uint8_t pointer is used for address. */ + p_zero_ptr = (uint8_t *) memchr(p_start, 0x00, key_size - 2); /* "2" is (1)+(2) */ + if (NULL == p_zero_ptr) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + if ((HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE - 3) > (uint32_t) (p_zero_ptr - p_start)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + ptr += (uint32_t) ((p_zero_ptr - p_start) + 1); + + plain->data_length = key_size - (ptr - ptr_start); + memcpy(plain->pdata, &output_data_arry[ptr], plain->data_length); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSASSA_PKCS2048_SignatureGenerate() function generates, in accordance with RSASSA-PKCS1-V1_5, a signature + * from the message text or hash value that is input in the first argument, message_hash, using the private wrapped + * key input to the third argument, wrapped_key, and writes the signature text to the second argument, signature. + * When a message is specified in the first argument, message_hash->data_type, a hash value is calculated for + * the message as specified by the fourth argument, hash_type. When specifying a hash value in the first argument, + * message_hash->data_type, a hash value calculated with a hash algorithm as specified by the fourth argument, + * hash_type, must be input to message_hash->pdata. + * + * @param[in] message_hash Message or hash value to which to attach signature + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in,out] signature Signature text storage destination information + * @arg signature->pdata : Specifies pointer to array storing the signature text + * @arg signature->data_length : data length + * @param[in] wrapped_key Inputs the 2048-bit RSA private wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSASSA_PKCS2048_SignatureGenerate (sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa2048_private_wrapped_key_t * wrapped_key, + uint8_t hash_type) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t error_code = FSP_SUCCESS; + uint8_t data_buff[HW_SCE_RSA_2048_DATA_BYTE_SIZE] = + { + 0 + }; + + error_code = set_rsassapkcs_hash_data(message_hash, hash_type, HW_SCE_RSA_2048_DATA_BYTE_SIZE, data_buff); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + error_code = R_SCE_Rsa2048ModularExponentDecryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (data_buff), + (uint32_t *) (signature->pdata)); + + signature->data_length = HW_SCE_RSA_2048_DATA_BYTE_SIZE; + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSASSA_PKCS2048_SignatureVerify() function verifies, in accordance with RSASSA-PKCS1-V1_5, the signature text + * input to the first argument signature, and the message text or hash value input to the second argument, + * message_hash, using the public wrapped key input to the third argument, wrapped_key. When a message is specified + * in the second argument, message_hash->data_type, a hash value is calculated using the public wrapped key input to + * the third argument, wrapped_key, and as specified by the fourth argument, hash_type. When specifying a hash value + * in the second argument, message_hash->data_type, a hash value calculated with a hash algorithm as specified by the + * fourth argument, hash_type, must be input to message_hash->pdata. + * + * @param[in] signature Signature text information to verify + * @arg signature->pdata : Specifies pointer to array storing the signature text + * @arg signature->data_length : Specifies effective data length of the array + * @param[in] message_hash Message text or hash value to verify + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in] wrapped_key Inputs the 1024-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication failed + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSASSA_PKCS2048_SignatureVerify (sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa2048_public_wrapped_key_t * wrapped_key, + uint8_t hash_type) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t error_code = FSP_SUCCESS; + uint8_t data_buff[HW_SCE_RSA_2048_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t decrypt_data[HW_SCE_RSA_2048_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t data_ptr = 0; + + if (signature->data_length > HW_SCE_RSA_2048_DATA_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + data_ptr = HW_SCE_RSA_2048_DATA_BYTE_SIZE - signature->data_length; + memcpy(data_buff + data_ptr, signature->pdata, signature->data_length); + + error_code = R_SCE_Rsa2048ModularExponentEncryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (data_buff), + (uint32_t *) (decrypt_data)); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + error_code = set_rsassapkcs_hash_data(message_hash, hash_type, HW_SCE_RSA_2048_DATA_BYTE_SIZE, data_buff); + if (FSP_SUCCESS == error_code) + { + if (memcmp(data_buff, decrypt_data, HW_SCE_RSA_2048_DATA_BYTE_SIZE)) + { + error_code = FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSASSA_PKCS3072_SignatureVerify() function verifies, in accordance with RSASSA-PKCS1-V1_5, the signature text + * input to the first argument signature, and the message text or hash value input to the second argument, + * message_hash, using the public wrapped key input to the third argument, wrapped_key. When a message is specified + * in the second argument, message_hash->data_type, a hash value is calculated using the public wrapped key input to + * the third argument, wrapped_key, and as specified by the fourth argument, hash_type. When specifying a hash value + * in the second argument, message_hash->data_type, a hash value calculated with a hash algorithm as specified by the + * fourth argument, hash_type, must be input to message_hash->pdata. + * + * @param[in] signature Signature text information to verify + * @arg signature->pdata : Specifies pointer to array storing the signature text + * @arg signature->data_length : Specifies effective data length of the array + * @param[in] message_hash Message text or hash value to verify + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in] wrapped_key Inputs the 3072-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication failed + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSASSA_PKCS3072_SignatureVerify (sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa3072_public_wrapped_key_t * wrapped_key, + uint8_t hash_type) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t error_code = FSP_SUCCESS; + uint8_t data_buff[HW_SCE_RSA_3072_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t decrypt_data[HW_SCE_RSA_3072_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t data_ptr = 0; + + if (signature->data_length > HW_SCE_RSA_3072_DATA_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + data_ptr = HW_SCE_RSA_3072_DATA_BYTE_SIZE - signature->data_length; + memcpy(data_buff + data_ptr, signature->pdata, signature->data_length); + + error_code = R_SCE_Rsa3072ModularExponentEncryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (data_buff), + (uint32_t *) (decrypt_data)); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + error_code = set_rsassapkcs_hash_data(message_hash, hash_type, HW_SCE_RSA_3072_DATA_BYTE_SIZE, data_buff); + if (FSP_SUCCESS == error_code) + { + if (memcmp(data_buff, decrypt_data, HW_SCE_RSA_3072_DATA_BYTE_SIZE)) + { + error_code = FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSASSA_PKCS4096_SignatureVerify() function verifies, in accordance with RSASSA-PKCS1-V1_5, the signature text + * input to the first argument signature, and the message text or hash value input to the second argument, + * message_hash, using the public wrapped key input to the third argument, wrapped_key. When a message is specified + * in the second argument, message_hash->data_type, a hash value is calculated using the public wrapped key input to + * the third argument, wrapped_key, and as specified by the fourth argument, hash_type. When specifying a hash value + * in the second argument, message_hash->data_type, a hash value calculated with a hash algorithm as specified by the + * fourth argument, hash_type, must be input to message_hash->pdata. + * + * @param[in] signature Signature text information to verify + * @arg signature->pdata : Specifies pointer to array storing the signature text + * @arg signature->data_length : Specifies effective data length of the array + * @param[in] message_hash Message text or hash value to verify + * @arg message_hash->pdata : Specifies pointer to array storing the message or + * hash value + * @arg message_hash->data_length : Specifies effective data length of the array + * (Specify only when Message is selected) + * @arg message_hash->data_type : Selects the data type of message_hash + * (Message: 0 Hash value: 1) + * @param[in] wrapped_key Inputs the 1024-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Invalid wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION Authentication failed + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is invalid. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSASSA_PKCS4096_SignatureVerify (sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa4096_public_wrapped_key_t * wrapped_key, + uint8_t hash_type) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(signature); + FSP_ASSERT(signature->pdata); + FSP_ASSERT(message_hash); + FSP_ASSERT(message_hash->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t error_code = FSP_SUCCESS; + uint8_t data_buff[HW_SCE_RSA_4096_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t decrypt_data[HW_SCE_RSA_4096_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t data_ptr = 0; + + if (signature->data_length > HW_SCE_RSA_4096_DATA_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + data_ptr = HW_SCE_RSA_4096_DATA_BYTE_SIZE - signature->data_length; + memcpy(data_buff + data_ptr, signature->pdata, signature->data_length); + + error_code = R_SCE_Rsa4096ModularExponentEncryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (data_buff), + (uint32_t *) (decrypt_data)); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + error_code = set_rsassapkcs_hash_data(message_hash, hash_type, HW_SCE_RSA_4096_DATA_BYTE_SIZE, data_buff); + if (FSP_SUCCESS == error_code) + { + if (memcmp(data_buff, decrypt_data, HW_SCE_RSA_4096_DATA_BYTE_SIZE)) + { + error_code = FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + } + + return error_code; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSAES_PKCS2048_Encrypt() function RSA-encrypts the plaintext input to the first argument, plain, + * according to RSAES-PKCS1-V1_5. It writes the encryption result to the second argument, cipher. + * + * @param[in] plain plaintext + * @arg plain->pdata : Specifies pointer to array containing plaintext. + * @arg plain->data_length : Specifies valid data length of plaintext array. + * data size <= public key n size - 11 + * @param[in,out] cipher ciphertext + * @arg cipher->pdata : Specifies pointer to array containing ciphertext. + * @arg cipher->data_length : Inputs ciphertext buffer size. + * Outputs valid data length after encryption + * (public key n size). + * @param[in] wrapped_key Inputs the 2048-bit RSA public wrapped key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Incorrect wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSAES_PKCS2048_Encrypt (sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa2048_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(plain); + FSP_ASSERT(plain->pdata); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t ercd = FSP_SUCCESS; + uint8_t input_data_arry[HW_SCE_RSA_2048_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t output_data_arry[HW_SCE_RSA_2048_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t key_size = 0; + uint32_t ptr = 0; + + /* Casting uint32_t pointer is used for address. */ + key_size = get_keyn_size((uint32_t *) &wrapped_key->value.key_n, HW_SCE_RSA_2048_DATA_BYTE_SIZE); + if (key_size < HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((plain->data_length) > (key_size - HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (cipher->data_length < key_size) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + cipher->data_length = key_size; + + /*** RSAES-PKCS#1_V1.5 format ***/ + /* (1) | (2) | (3) | (4) | (5) */ + /* EM = [0x00] | [0x02] | [PS] | [0x00] | [M] */ + ptr = HW_SCE_RSA_2048_DATA_BYTE_SIZE - key_size; + input_data_arry[ptr] = 0x00; + ptr++; + input_data_arry[ptr] = 0x02; + ptr++; + + get_rand_rsaes_pkcs(((key_size - plain->data_length) - 3), &input_data_arry[ptr]); + ptr += ((key_size - plain->data_length) - 3); + input_data_arry[ptr] = 0x00; + ptr++; + + memcpy(&input_data_arry[ptr], plain->pdata, plain->data_length); + + ercd = R_SCE_Rsa2048ModularExponentEncryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (input_data_arry), + (uint32_t *) (output_data_arry)); + memcpy(cipher->pdata, &output_data_arry[HW_SCE_RSA_2048_DATA_BYTE_SIZE - key_size], cipher->data_length); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSAES_PKCS2048_Decrypt() function RSA-decrypts the ciphertext input to the first argument, cipher, + * according to RSAES-PKCS1-V1_5. It writes the decryption result to the second argument, plain. + * + * @param[in] cipher ciphertext + * @arg cipher->pdata : Specifies pointer to array containing ciphertext. + * @arg cipher->data_length : Inputs ciphertext buffer size. + * Outputs valid data length after encryption + * (public key n size). + * @param[in,out] plain plaintext + * @arg plain->pdata : Specifies pointer to array containing plaintext. + * @arg plain->data_length : Inputs plaintext buffer size. + * The following size is required. + * Plaintext buffer size >= public key n size -11. + * Outputs valid data length after decryption + * (public key n size). + * @param[in] wrapped_key Inputs the 1024-bit RSA private wrapped key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Incorrect wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSAES_PKCS2048_Decrypt (sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa2048_private_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(plain); + FSP_ASSERT(plain->pdata); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t ercd = FSP_SUCCESS; + uint8_t input_data_arry[HW_SCE_RSA_2048_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t output_data_arry[HW_SCE_RSA_2048_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t key_size = 0; + uint32_t ptr = 0; + uint32_t ptr_start = 0; + uint8_t * p_start = 0; + uint8_t * p_zero_ptr = 0; + + /* Casting uint32_t pointer is used for address. */ + key_size = get_keyn_size((uint32_t *) &wrapped_key->value.key_n, HW_SCE_RSA_2048_DATA_BYTE_SIZE); + if (key_size < HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (cipher->data_length != key_size) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (plain->data_length < (key_size - HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + memcpy(&input_data_arry[HW_SCE_RSA_2048_DATA_BYTE_SIZE - key_size], cipher->pdata, cipher->data_length); + ercd = R_SCE_Rsa2048ModularExponentDecryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (input_data_arry), + (uint32_t *) (output_data_arry)); + if (FSP_SUCCESS != ercd) + { + return ercd; + } + + /*** RSAES-PKCS#1_V1.5 format ***/ + /* (1) | (2) | (3) | (4) | (5) */ + /* EM = [0x00] | [0x02] | [PS] | [0x00] | [M] */ + ptr = HW_SCE_RSA_2048_DATA_BYTE_SIZE - key_size; + ptr_start = ptr; + + /* (1) */ + if (0x00 != output_data_arry[ptr]) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + ptr++; + + /* (2) */ + if (0x02 != output_data_arry[ptr]) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + ptr++; + + /* (3) and (4) */ + p_start = &output_data_arry[ptr]; + + /* Casting uint8_t pointer is used for address. */ + p_zero_ptr = (uint8_t *) memchr(p_start, 0x00, key_size - 2); /* "2" is (1)+(2) */ + if (NULL == p_zero_ptr) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + if ((HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE - 3) > (uint32_t) (p_zero_ptr - p_start)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + ptr += (uint32_t) ((p_zero_ptr - p_start) + 1); + + plain->data_length = key_size - (ptr - ptr_start); + memcpy(plain->pdata, &output_data_arry[ptr], plain->data_length); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSAES_PKCS3072_Encrypt() function RSA-encrypts the plaintext input to the first argument, plain, + * according to RSAES-PKCS1-V1_5. It writes the encryption result to the second argument, cipher. + * + * @param[in] plain plaintext + * @arg plain->pdata : Specifies pointer to array containing plaintext. + * @arg plain->data_length : Specifies valid data length of plaintext array. + * data size <= public key n size - 11 + * @param[in,out] cipher ciphertext + * @arg cipher->pdata : Specifies pointer to array containing ciphertext. + * @arg cipher->data_length : Inputs ciphertext buffer size. + * Outputs valid data length after encryption + * (public key n size). + * @param[in] wrapped_key Inputs the 3072-bit RSA public wrapped key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Incorrect wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSAES_PKCS3072_Encrypt (sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa3072_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(plain); + FSP_ASSERT(plain->pdata); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t ercd = FSP_SUCCESS; + uint8_t input_data_arry[HW_SCE_RSA_3072_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t output_data_arry[HW_SCE_RSA_3072_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t key_size = 0; + uint32_t ptr = 0; + + /* Casting uint32_t pointer is used for address. */ + key_size = get_keyn_size((uint32_t *) &wrapped_key->value.key_n, HW_SCE_RSA_3072_DATA_BYTE_SIZE); + if (key_size < HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((plain->data_length) > (key_size - HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (cipher->data_length < key_size) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + cipher->data_length = key_size; + + /*** RSAES-PKCS#1_V1.5 format ***/ + /* (1) | (2) | (3) | (4) | (5) */ + /* EM = [0x00] | [0x02] | [PS] | [0x00] | [M] */ + ptr = HW_SCE_RSA_3072_DATA_BYTE_SIZE - key_size; + input_data_arry[ptr] = 0x00; + ptr++; + input_data_arry[ptr] = 0x02; + ptr++; + + get_rand_rsaes_pkcs(((key_size - plain->data_length) - 3), &input_data_arry[ptr]); + ptr += ((key_size - plain->data_length) - 3); + input_data_arry[ptr] = 0x00; + ptr++; + + memcpy(&input_data_arry[ptr], plain->pdata, plain->data_length); + + ercd = R_SCE_Rsa3072ModularExponentEncryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (input_data_arry), + (uint32_t *) (output_data_arry)); + memcpy(cipher->pdata, &output_data_arry[HW_SCE_RSA_3072_DATA_BYTE_SIZE - key_size], cipher->data_length); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_RSAES_PKCS4096_Encrypt() function RSA-encrypts the plaintext input to the first argument, plain, + * according to RSAES-PKCS1-V1_5. It writes the encryption result to the second argument, cipher. + * + * @param[in] plain plaintext + * @arg plain->pdata : Specifies pointer to array containing plaintext. + * @arg plain->data_length : Specifies valid data length of plaintext array. + * data size <= public key n size - 11 + * @param[in,out] cipher ciphertext + * @arg cipher->pdata : Specifies pointer to array containing ciphertext. + * @arg cipher->data_length : Inputs ciphertext buffer size. + * Outputs valid data length after encryption + * (public key n size). + * @param[in] wrapped_key Inputs the 4096-bit RSA public wrapped key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL Incorrect wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input data is illegal. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSAES_PKCS4096_Encrypt (sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa4096_public_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(plain); + FSP_ASSERT(plain->pdata); + FSP_ASSERT(cipher); + FSP_ASSERT(cipher->pdata); + FSP_ASSERT(wrapped_key); +#endif + fsp_err_t ercd = FSP_SUCCESS; + uint8_t input_data_arry[HW_SCE_RSA_4096_DATA_BYTE_SIZE] = + { + 0 + }; + uint8_t output_data_arry[HW_SCE_RSA_4096_DATA_BYTE_SIZE] = + { + 0 + }; + uint32_t key_size = 0; + uint32_t ptr = 0; + + /* Casting uint32_t pointer is used for address. */ + key_size = get_keyn_size((uint32_t *) &wrapped_key->value.key_n, HW_SCE_RSA_4096_DATA_BYTE_SIZE); + if (key_size < HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if ((plain->data_length) > (key_size - HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (cipher->data_length < key_size) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + cipher->data_length = key_size; + + /*** RSAES-PKCS#1_V1.5 format ***/ + /* (1) | (2) | (3) | (4) | (5) */ + /* EM = [0x00] | [0x02] | [PS] | [0x00] | [M] */ + ptr = HW_SCE_RSA_4096_DATA_BYTE_SIZE - key_size; + input_data_arry[ptr] = 0x00; + ptr++; + input_data_arry[ptr] = 0x02; + ptr++; + + get_rand_rsaes_pkcs(((key_size - plain->data_length) - 3), &input_data_arry[ptr]); + ptr += ((key_size - plain->data_length) - 3); + input_data_arry[ptr] = 0x00; + ptr++; + + memcpy(&input_data_arry[ptr], plain->pdata, plain->data_length); + + ercd = R_SCE_Rsa4096ModularExponentEncryptPrivate( + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) &wrapped_key->value, + (uint32_t *) (input_data_arry), + (uint32_t *) (output_data_arry)); + memcpy(cipher->pdata, &output_data_arry[HW_SCE_RSA_4096_DATA_BYTE_SIZE - key_size], cipher->data_length); + + return ercd; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Hash message text according to the hash type. + * + * @param p_mes message text + * @param p_hash pointer of hash data + * @param mes_len message size(byte) + * @param hash_type hash type + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input parameter illegal + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + **********************************************************************************************************************/ +static fsp_err_t calc_hash_data (uint8_t * p_mes, uint8_t * p_hash, uint32_t mes_len, uint8_t hash_type) +{ + fsp_err_t error_code = FSP_SUCCESS; + sce_sha_md5_handle_t ex_sha_handle = + { + 0 + }; + uint32_t hash_length = 0; + + if (HW_SCE_RSA_HASH_SHA256 == hash_type) + { + R_SCE_SHA256_Init(&ex_sha_handle); + error_code = R_SCE_SHA256_Update(&ex_sha_handle, p_mes, mes_len); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + + error_code = R_SCE_SHA256_Final(&ex_sha_handle, p_hash, &hash_length); + } + + return error_code; +} + +/*******************************************************************************************************************//** + * Prefix the hash of the message according to RSASSA-PKCS1-V1_5. + * + * @param p_message_hash message text or hash value + * @param hash_type hash type + * @param rsa_key_byte_size RSA data size + * @param data_buff pointer of Sig data + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER Input parameter illegal + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + **********************************************************************************************************************/ +static fsp_err_t set_rsassapkcs_hash_data (sce_rsa_byte_data_t * p_message_hash, + uint8_t hash_type, + uint32_t rsa_key_byte_size, + uint8_t * data_buff) +{ + fsp_err_t error_code = FSP_SUCCESS; + sce_rsa_byte_data_t prefix = + { + 0 + }; + uint32_t hash_data_buff[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE / sizeof(uint32_t)] = + { + 0 + }; + uint32_t hash_length = 0; + uint32_t data_ptr = 0; + + if ((HW_SCE_RSA_HASH_SHA256 < hash_type) || (1 < p_message_hash->data_type)) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + if (0 == p_message_hash->data_type) + { + /* Casting uint8_t pointer is used for address. */ + error_code = calc_hash_data(p_message_hash->pdata, + (uint8_t *) hash_data_buff, + p_message_hash->data_length, + hash_type); + if (FSP_SUCCESS != error_code) + { + return error_code; + } + } + + if (HW_SCE_RSA_HASH_SHA256 == hash_type) + { + prefix.pdata = gs_rsa_sig_sha256_prefix; + prefix.data_length = sizeof(gs_rsa_sig_sha256_prefix); + hash_length = HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE; + } + + data_buff[0] = 0x00; + data_buff[1] = 0x01; + data_ptr = ((rsa_key_byte_size - prefix.data_length) - hash_length) - 1; + memset(data_buff + 2, SCE_HEX_FF, data_ptr); + data_buff[data_ptr] = 0x0; + data_ptr++; + memcpy(data_buff + data_ptr, prefix.pdata, prefix.data_length); + data_ptr += prefix.data_length; + if (0 == p_message_hash->data_type) + { + memcpy(data_buff + data_ptr, hash_data_buff, hash_length); + } + else /* if (1 == p_message_hash->data_type) */ + { + memcpy(data_buff + data_ptr, p_message_hash->pdata, hash_length); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get key n size from RSA key index + * + * @param prsa_key_index RSA key index + * @param key_max_size key data max byte size + * + * @return key_size + **********************************************************************************************************************/ +static uint32_t get_keyn_size (uint32_t * prsa_key_index, uint32_t key_max_size) +{ + bool get_output_data_length = false; + + /* Casting uint8_t pointer is used for address. */ + uint8_t * p_rsa_key_n_data = (uint8_t *) prsa_key_index; + uint32_t key_size_tmp = 0; + + key_size_tmp = key_max_size; + for (uint32_t i = 0; i < (key_max_size); i++) + { + if (!get_output_data_length) + { + if (0 == p_rsa_key_n_data[i]) + { + key_size_tmp--; + } + else + { + get_output_data_length = true; + } + } + } + + return key_size_tmp; +} + +/*******************************************************************************************************************//** + * In accordance with RSAES-PKCS1-V1_5 to obtain random number data of rand_size that does not contain 0. + * + * @param rand_size random data size + * @param prand_data random data area pointer + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT resource conflict + **********************************************************************************************************************/ +static fsp_err_t get_rand_rsaes_pkcs (uint32_t rand_size, uint8_t * prand_data) +{ + fsp_err_t ercd = FSP_SUCCESS; + uint8_t rand_tmp[16] = + { + 0 + }; + uint32_t rest_size = rand_size; + uint32_t rand_ptr = 0; + uint32_t i = 0; + + while (rest_size) + { +#if defined RSA_ENC_TEST_MODE + memset(rand_tmp, SCE_HEX_FF, sizeof(rand_tmp)); +#else + + /* Casting uint32_t pointer is used for address. */ + ercd = R_SCE_RandomNumberGenerate((uint32_t *) rand_tmp); + if (FSP_SUCCESS != ercd) + { + break; + } +#endif /* defined RSA_ENC_TEST_MODE */ + for (i = 0; i < 16; i++) + { + if (0 != rand_tmp[i]) + { + prand_data[rand_ptr] = rand_tmp[i]; + rand_ptr++; + rest_size--; + } + + if (0 == rest_size) + { + break; + } + } + } + + return ercd; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c new file mode 100644 index 0000000000..c0473b704f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c @@ -0,0 +1,671 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Block length (in bytes) of SHA */ +#define SHA_BLOCK8_LEN (64U) + +/* Initialization function call state */ +#define CALL_ONLY_INIT (0) +#define CALL_ONLY_UPDATE_FINAL (1) + +#ifndef SCE_HEX_FF + #define SCE_HEX_FF 0xff +#endif +#ifndef SCE_HEX_80 + #define SCE_HEX_80 0x80 +#endif +#ifndef SCE_DEC_32 + #define SCE_DEC_32 32 +#endif +#ifndef SCE_DEC_64 + #define SCE_DEC_64 64 +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern uint32_t g_private_id_counter; +uint32_t g_sha256_private_id; +uint32_t g_sha256hmacgen_private_id; +uint32_t g_sha256hmacver_private_id; + +/*******************************************************************************************************************//** + * @addtogroup SCE_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * The R_SCE_SHA256_Init() function performs preparations for the execution of an SHA-256 hash calculation, + * and writes the result to the first argument, handle. The value of handle is used as an argument in the subsequent + * R_SCE_SHA256_Update() function and R_SCE_SHA256_Final() function. + * + * @param[in,out] handle SHA handler (work area) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256_Init (sce_sha_md5_handle_t * handle) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); +#endif + + memset(handle, 0, sizeof(sce_sha_md5_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_sha256_private_id = g_private_id_counter; + handle->id = g_sha256_private_id; + memset(handle->sha_buffer, 0, sizeof(handle->sha_buffer)); + + return R_SCE_Sha256InitPrivate(handle); +} + +/*******************************************************************************************************************//** + * The R_SCE_SHA256_Update() function calculates a hash value based on the second argument, message, + * and the third argument, message_length, and writes the ongoing status to the first argument, handle. + * After message input is completed, call R_SCE_SHA256_Final(). + * + * @param[in,out] handle SHA handler (work area) + * @param[in] message message data area + * @param[in] message_length message data length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256_Update (sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(message || (0 == message_length)); +#endif + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_sha256_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += message_length; + if ((handle->buffering_length + message_length) >= SHA_BLOCK8_LEN) + { + memcpy(handle->sha_buffer + handle->buffering_length, message, SHA_BLOCK8_LEN - handle->buffering_length); + + /*Casting uint32_t pointer is used for address.*/ + ercd = R_SCE_Sha256UpdatePrivate(handle, (uint32_t *) (handle->sha_buffer), SHA_BLOCK8_LEN >> 2); + length_rest = message_length - (SHA_BLOCK8_LEN - handle->buffering_length); + memset(handle->sha_buffer, 0, sizeof(handle->sha_buffer)); + if (length_rest >= SHA_BLOCK8_LEN) + { + ercd = R_SCE_Sha256UpdatePrivate(handle, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (message + (SHA_BLOCK8_LEN - handle->buffering_length)), + ((length_rest / SHA_BLOCK8_LEN) * SHA_BLOCK8_LEN) >> 2); + length_rest -= ((length_rest / SHA_BLOCK8_LEN) * SHA_BLOCK8_LEN); + } + + handle->buffering_length = 0; + memcpy(handle->sha_buffer, message + (message_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(handle->sha_buffer + handle->buffering_length, message, message_length); + handle->buffering_length += message_length; + } + + return ercd; +} + +/*******************************************************************************************************************//** + * Using the handle specified in the first argument, handle, the R_SCE_SHA256_Final() function writes the calculation + * result to the second argument, digest, and writes the length of the calculation result to the third argument, + * digest_length. + * + * @param[in,out] handle SHA handler (work area) + * @param[in,out] digest hasha data area + * @param[in,out] digest_length hash data length (32bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256_Final (sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(digest); + FSP_ASSERT(digest_length); +#endif + uint32_t max_cnt_byte = 0; + fsp_err_t ercd = FSP_SUCCESS; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_sha256_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->sha_buffer[handle->buffering_length] = SCE_HEX_80; + if ((SHA_BLOCK8_LEN - handle->buffering_length) >= 9) /* another block unnecessary */ + { + memset(handle->sha_buffer + (handle->buffering_length + 1), 0, + (SHA_BLOCK8_LEN - 4) - (handle->buffering_length + 1)); + + /* According c., but support only l < 2**32 case */ + /* Casting uint32_t data to uint8_t data array. */ + handle->sha_buffer[SHA_BLOCK8_LEN - 4] = (uint8_t) ((handle->all_received_length * 8) >> 24); + + /* Casting uint32_t data to uint8_t data array. */ + handle->sha_buffer[SHA_BLOCK8_LEN - 3] = (uint8_t) (((handle->all_received_length * 8) >> 16) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->sha_buffer[SHA_BLOCK8_LEN - 2] = (uint8_t) (((handle->all_received_length * 8) >> 8) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->sha_buffer[SHA_BLOCK8_LEN - 1] = (uint8_t) ((handle->all_received_length * 8) & SCE_HEX_FF); + max_cnt_byte = SHA_BLOCK8_LEN; + } + else + { + /* another block necessary */ + memset(handle->sha_buffer + (handle->buffering_length + 1), 0, + ((2 * SHA_BLOCK8_LEN) - 4) - (handle->buffering_length + 1)); + + /* Casting uint32_t data to uint8_t data array. */ + handle->sha_buffer[(2 * SHA_BLOCK8_LEN) - 4] = (uint8_t) ((handle->all_received_length * 8) >> 24); + + /* Casting uint32_t data to uint8_t data array. */ + handle->sha_buffer[(2 * SHA_BLOCK8_LEN) - + 3] = (uint8_t) (((handle->all_received_length * 8) >> 16) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->sha_buffer[(2 * SHA_BLOCK8_LEN) - + 2] = (uint8_t) (((handle->all_received_length * 8) >> 8) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->sha_buffer[(2 * SHA_BLOCK8_LEN) - 1] = (uint8_t) ((handle->all_received_length * 8) & SCE_HEX_FF); + max_cnt_byte = 2 * SHA_BLOCK8_LEN; + } + + ercd = R_SCE_Sha256FinalPrivate(handle, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (handle->sha_buffer), + max_cnt_byte >> 2, + (uint32_t *) (digest), + digest_length); + handle->all_received_length = 0; + handle->buffering_length = 0; + memset(handle->sha_buffer, 0, sizeof(handle->sha_buffer)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_SHA256HMAC_GenerateInit() function uses the second argument wrapped_key to prepare for execution of + * SHA256-HMAC calculation, then writes the result to the first argument handle. The argument handle is used + * by the subsequent R_SCE_SHA256HMAC_GenerateUpdate() function or R_SCE_SHA256HMAC_GenerateFinal() function. + * + * @param[in,out] handle SHA-HMAC handler (work area) + * @param[in] wrapped_key MAC wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL An invalid MAC wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256HMAC_GenerateInit (sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + memset(handle, 0, sizeof(sce_hmac_sha_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_sha256hmacgen_private_id = g_private_id_counter; + handle->id = g_sha256hmacgen_private_id; + memcpy(&handle->wrapped_key, wrapped_key, sizeof(sce_hmac_sha_wrapped_key_t)); + + return R_SCE_Sha256HmacGenerateInitPrivate(handle, wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_SHA256HMAC_GenerateUpdate() function uses the handle specified by the first argument handle, + * calculates a hash value from the second argument message and third argument message_length, then writes + * the intermediate result to the first argument handle. After message input finishes, + * call the R_SCE_SHA256HMAC_GenerateFinal() function. + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] message Message area + * @param[in] message_length Message length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256HMAC_GenerateUpdate (sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(message || (0 == message_length)); +#endif + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_sha256hmacgen_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += message_length; + if ((handle->buffering_length + message_length) >= SHA_BLOCK8_LEN) + { + memcpy((&handle->hmac_buffer[0] + handle->buffering_length), message, + SHA_BLOCK8_LEN - handle->buffering_length); + + /*Casting uint32_t pointer is used for address.*/ + ercd = R_SCE_Sha256HmacGenerateUpdatePrivate(handle, + (uint32_t *) (handle->hmac_buffer), + (SHA_BLOCK8_LEN) >> 2); + length_rest = message_length - (SHA_BLOCK8_LEN - handle->buffering_length); + memset(handle->hmac_buffer, 0, sizeof(handle->hmac_buffer)); + if (length_rest >= SHA_BLOCK8_LEN) + { + ercd = R_SCE_Sha256HmacGenerateUpdatePrivate(handle, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (message + + (SHA_BLOCK8_LEN - handle->buffering_length)), + ((length_rest / SHA_BLOCK8_LEN) * SHA_BLOCK8_LEN) >> 2); + length_rest -= ((length_rest / SHA_BLOCK8_LEN) * SHA_BLOCK8_LEN); + } + + handle->buffering_length = 0; + memcpy(handle->hmac_buffer, message + (message_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->hmac_buffer[0] + handle->buffering_length, message, message_length); + handle->buffering_length += message_length; + } + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_SHA256HMAC_GenerateFinal() function uses the handle specified by the first argument handle and + * writes the calculation result to the second argument mac. + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in,out] mac HMAC area (32 bytes) + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256HMAC_GenerateFinal (sce_hmac_sha_handle_t * handle, uint8_t * mac) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(mac); +#endif + uint32_t max_cnt_byte = 0; + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_tmp = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_sha256hmacgen_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->hmac_buffer[handle->buffering_length] = SCE_HEX_80; + length_tmp = handle->all_received_length + SCE_DEC_64; + if ((SHA_BLOCK8_LEN - handle->buffering_length) >= 9) /* another block unnecessary */ + { + memset(handle->hmac_buffer + (handle->buffering_length + 1), 0, + (SHA_BLOCK8_LEN - 4) - (handle->buffering_length + 1)); + + /* According c., but support only l < 2**32 case */ + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[SHA_BLOCK8_LEN - 4] = (uint8_t) ((length_tmp * 8) >> 24); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[SHA_BLOCK8_LEN - 3] = (uint8_t) (((length_tmp * 8) >> 16) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[SHA_BLOCK8_LEN - 2] = (uint8_t) (((length_tmp * 8) >> 8) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[SHA_BLOCK8_LEN - 1] = (uint8_t) ((length_tmp * 8) & SCE_HEX_FF); + max_cnt_byte = SHA_BLOCK8_LEN; + } + else /* another block necessary */ + { + memset(handle->hmac_buffer + (handle->buffering_length + 1), 0, + ((2 * SHA_BLOCK8_LEN) - 4) - (handle->buffering_length + 1)); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[(2 * SHA_BLOCK8_LEN) - 4] = (uint8_t) ((length_tmp * 8) >> 24); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[(2 * SHA_BLOCK8_LEN) - 3] = (uint8_t) (((length_tmp * 8) >> 16) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[(2 * SHA_BLOCK8_LEN) - 2] = (uint8_t) (((length_tmp * 8) >> 8) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[(2 * SHA_BLOCK8_LEN) - 1] = (uint8_t) ((length_tmp * 8) & SCE_HEX_FF); + max_cnt_byte = 2 * SHA_BLOCK8_LEN; + } + + /*Casting uint32_t pointer is used for address.*/ + R_SCE_Sha256HmacGenerateUpdatePrivate(handle, (uint32_t *) (handle->hmac_buffer), (max_cnt_byte) >> 2); + + /*Casting uint32_t pointer is used for address.*/ + ercd = R_SCE_Sha256HmacGenerateFinalPrivate(handle, (uint32_t *) (mac)); + handle->all_received_length = 0; + handle->buffering_length = 0; + memset(handle->hmac_buffer, 0, sizeof(handle->hmac_buffer)); + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_SHA256HMAC_VerifyInit() function uses the second argument wrapped_key to prepare for execution of + * SHA256-HMAC calculation, then writes the result to the first argument handle. The argument handle is used + * by the subsequent R_SCE_SHA256HMAC_VerifyUpdate() function or R_SCE_SHA256HMAC_VerifyFinal() function. + * + * @param[in,out] handle SHA-HMAC handler (work area) + * @param[in] wrapped_key MAC wrapped key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL An invalid MAC wrapped key was input. + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256HMAC_VerifyInit (sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(wrapped_key); +#endif + memset(handle, 0, sizeof(sce_hmac_sha_handle_t)); + handle->flag_call_init = CALL_ONLY_UPDATE_FINAL; + g_private_id_counter++; + g_sha256hmacver_private_id = g_private_id_counter; + handle->id = g_sha256hmacver_private_id; + memcpy(&handle->wrapped_key, wrapped_key, sizeof(sce_hmac_sha_wrapped_key_t)); + + return R_SCE_Sha256HmacVerifyInitPrivate(handle, wrapped_key); +} + +/*******************************************************************************************************************//** + * The R_SCE_SHA256HMAC_VerifyUpdate() function uses the handle specified by the first argument handle, calculates + * a hash value from the second argument message and third argument message_length, then writes the intermediate + * result to the first argument handle. After message input finishes, call the R_SCE_SHA256HMAC_VerifyFinal() function. + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] message Message area + * @param[in] message_length Message length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256HMAC_VerifyUpdate (sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(message || (0 == message_length)); +#endif + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_rest = 0; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + if (handle->id != g_sha256hmacver_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->all_received_length += message_length; + if ((handle->buffering_length + message_length) >= SHA_BLOCK8_LEN) + { + memcpy((&handle->hmac_buffer[0] + handle->buffering_length), message, + SHA_BLOCK8_LEN - handle->buffering_length); + + /*Casting uint32_t pointer is used for address.*/ + ercd = R_SCE_Sha256HmacVerifyUpdatePrivate(handle, + (uint32_t *) (handle->hmac_buffer), + (SHA_BLOCK8_LEN) >> 2); + length_rest = message_length - (SHA_BLOCK8_LEN - handle->buffering_length); + memset(handle->hmac_buffer, 0, sizeof(handle->hmac_buffer)); + if (length_rest >= SHA_BLOCK8_LEN) + { + ercd = R_SCE_Sha256HmacVerifyUpdatePrivate(handle, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (message + + (SHA_BLOCK8_LEN - handle->buffering_length)), + ((length_rest / SHA_BLOCK8_LEN) * SHA_BLOCK8_LEN) >> 2); + length_rest -= ((length_rest / SHA_BLOCK8_LEN) * SHA_BLOCK8_LEN); + } + + handle->buffering_length = 0; + memcpy(handle->hmac_buffer, message + (message_length - length_rest), length_rest); + handle->buffering_length = length_rest; + } + else + { + memcpy(&handle->hmac_buffer[0] + handle->buffering_length, message, message_length); + handle->buffering_length += message_length; + } + + return ercd; +} + +/*******************************************************************************************************************//** + * The R_SCE_SHA256HMAC_VerifyFinal() function uses the handle specified by the first argument handle and verifies + * the mac value from the second argument mac and third argument mac_length. Input a value in bytes from + * 4 to 32 as mac_length. + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] mac HMAC area + * @param[in] mac_length HMAC length + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_ASSERTION A required parameter is NULL. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * @retval FSP_ERR_CRYPTO_SCE_PARAMETER An invalid handle was input. + * @retval FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION An invalid function was called. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_SHA256HMAC_VerifyFinal (sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length) +{ +#if SCE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(handle); + FSP_ASSERT(mac); +#endif + uint32_t max_cnt_byte = 0; + fsp_err_t ercd = FSP_SUCCESS; + uint32_t length_tmp = 0; + uint32_t mac_length_tmp = 0; + uint8_t mac_tmp[SCE_DEC_32] = + { + 0 + }; + + if (CALL_ONLY_INIT == handle->flag_call_init) + { + return FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION; + } + + handle->flag_call_init = CALL_ONLY_INIT; + if (handle->id != g_sha256hmacver_private_id) + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + handle->hmac_buffer[handle->buffering_length] = SCE_HEX_80; + length_tmp = handle->all_received_length + SCE_DEC_64; + if ((SHA_BLOCK8_LEN - handle->buffering_length) >= 9) /* another block unnecessary */ + { + memset(handle->hmac_buffer + (handle->buffering_length + 1), 0, + (SHA_BLOCK8_LEN - 4) - (handle->buffering_length + 1)); + + /* According c., but support only l < 2**32 case */ + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[SHA_BLOCK8_LEN - 4] = (uint8_t) ((length_tmp * 8) >> 24); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[SHA_BLOCK8_LEN - 3] = (uint8_t) (((length_tmp * 8) >> 16) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[SHA_BLOCK8_LEN - 2] = (uint8_t) (((length_tmp * 8) >> 8) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[SHA_BLOCK8_LEN - 1] = (uint8_t) ((length_tmp * 8) & SCE_HEX_FF); + max_cnt_byte = SHA_BLOCK8_LEN; + } + else /* another block necessary */ + { + memset(handle->hmac_buffer + (handle->buffering_length + 1), 0, + ((2 * SHA_BLOCK8_LEN) - 4) - (handle->buffering_length + 1)); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[(2 * SHA_BLOCK8_LEN) - 4] = (uint8_t) ((length_tmp * 8) >> 24); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[(2 * SHA_BLOCK8_LEN) - 3] = (uint8_t) (((length_tmp * 8) >> 16) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[(2 * SHA_BLOCK8_LEN) - 2] = (uint8_t) (((length_tmp * 8) >> 8) & SCE_HEX_FF); + + /* Casting uint32_t data to uint8_t data array. */ + handle->hmac_buffer[(2 * SHA_BLOCK8_LEN) - 1] = (uint8_t) ((length_tmp * 8) & SCE_HEX_FF); + max_cnt_byte = 2 * SHA_BLOCK8_LEN; + } + + memcpy(mac_tmp, mac, mac_length); + if ((4 <= mac_length) && (mac_length <= SCE_DEC_32)) + { + memset(mac_tmp + mac_length, 0, sizeof(mac_tmp) - mac_length); + } + else + { + return FSP_ERR_CRYPTO_SCE_PARAMETER; + } + + mac_length_tmp = change_endian_long(mac_length); + + /*Casting uint32_t pointer is used for address.*/ + R_SCE_Sha256HmacVerifyUpdatePrivate(handle, (uint32_t *) (handle->hmac_buffer), (max_cnt_byte) >> 2); + + /*Casting uint32_t pointer is used for address.*/ + ercd = R_SCE_Sha256HmacVerifyFinalPrivate(handle, (uint32_t *) (mac_tmp), &mac_length_tmp); + handle->all_received_length = 0; + handle->buffering_length = 0; + memset(handle->hmac_buffer, 0, sizeof(handle->hmac_buffer)); + + return ercd; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c new file mode 100644 index 0000000000..0675a00fa3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c @@ -0,0 +1,472 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sce_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup SCE_PROTECTED + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Verify root CA certificate. + * + * @param[in] public_key_type key type + * @param[in] certificate certificates. + * @param[in] certificate_length byte size of certificates. + * @param[in] public_key_n_start_position start position of public key n. + * @param[in] public_key_n_end_position end position of public key n. + * @param[in] public_key_e_start_position start position of public key e. + * @param[in] public_key_e_end_position end position of public key e. + * @param[in] signature signature for certificates. + * @param[out] encrypted_root_public_key public key for RSA 2048bit. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_RootCertificateVerify (uint32_t public_key_type, + uint8_t * certificate, + uint32_t certificate_length, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint8_t * signature, + uint32_t * encrypted_root_public_key) +{ + uint32_t information[4] = + { + 0 + }; + uint32_t certificate_length_sub = 0; + uint32_t certificate_length_sub2 = 0; + uint32_t public_key_type_sub = 0; + + public_key_type_sub = change_endian_long(public_key_type); + certificate_length_sub = change_endian_long(certificate_length); + certificate_length_sub2 = (certificate_length + 3) / 4; + certificate_length_sub2 = change_endian_long(certificate_length_sub2); + + information[0] = change_endian_long(public_key_n_start_position); + information[1] = change_endian_long(public_key_n_end_position); + information[2] = change_endian_long(public_key_e_start_position); + information[3] = change_endian_long(public_key_e_end_position); + + return R_SCE_TlsRootCertificateVerificationSub( + /* Casting uint32_t pointer is used for address. */ + /* uint32_t *InData_Sel_PubKeyType, */ &public_key_type_sub, + /* uint32_t *InData_Certificates, */ (uint32_t *) (certificate), + /* uint32_t *InData_CertificatesLength, */ &certificate_length_sub, + /* uint32_t *InData_Signature, */ (uint32_t *) (signature), + /* uint32_t *InData_CertificatesInfo, */ information, + /* uint32_t length, */ certificate_length_sub2, + /* uint32_t *OutData_PubKey, */ encrypted_root_public_key); +} + +/*******************************************************************************************************************//** + * Verify server certificate and intermediate certificate. + * + * @param[in] public_key_type key type + * @param[in] encrypted_input_public_key public key. + * @param[in] certificate certificates. + * @param[in] certificate_length byte size of certificates. + * @param[in] signature signature for certificates. + * @param[in] public_key_n_start_position start position of public key n. + * @param[in] public_key_n_end_position end position of public key n. + * @param[in] public_key_e_start_position start position of public key e. + * @param[in] public_key_e_end_position end position of public key e. + * @param[out] encrypted_output_public_key public key for RSA 2048bit. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_CertificateVerify (uint32_t public_key_type, + uint32_t * encrypted_input_public_key, + uint8_t * certificate, + uint32_t certificate_length, + uint8_t * signature, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint32_t * encrypted_output_public_key) +{ + uint32_t information[4] = + { + 0 + }; + uint32_t certificate_length_sub = 0; + uint32_t certificate_length_sub2 = 0; + uint32_t tmp_public_key_type = 0; + + tmp_public_key_type = change_endian_long(public_key_type); + certificate_length_sub = change_endian_long(certificate_length); + certificate_length_sub2 = (certificate_length + 3) / 4; + certificate_length_sub2 = change_endian_long(certificate_length_sub2); + + information[0] = change_endian_long(public_key_n_start_position); + information[1] = change_endian_long(public_key_n_end_position); + information[2] = change_endian_long(public_key_e_start_position); + information[3] = change_endian_long(public_key_e_end_position); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_TlsCertificateVerificationSub( + /* uint32_t *InData_Sel_PubKeyType, */ &tmp_public_key_type, + /* uint32_t *InData_PubKey, */ encrypted_input_public_key, + /* uint32_t *InData_TBSCertificate, */ (uint32_t *) certificate, + /* uint32_t *InData_TBSCertificateLength, */ &certificate_length_sub, + /* uint32_t *InData_Signature, */ (uint32_t *) signature, + /* uint32_t *InData_TBSCertificatesInfo, */ information, + /* uint32_t length, */ certificate_length_sub2, + /* uint32_t *OutData_PubKey); */ encrypted_output_public_key); +} + +/*******************************************************************************************************************//** + * Generate encrypted pre-master secret. + * + * @param[out] sce_pre_master_secret pre-master secret value for SCE. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_PreMasterSecretGenerateForRSA2048 (uint32_t * sce_pre_master_secret) +{ + return R_SCE_TlsGeneratePreMasterSecretSub(sce_pre_master_secret); +} + +/*******************************************************************************************************************//** + * Generate encrypted master secret. + * + * @param[in] select_cipher_suite cipher suite type + * @param[in] sce_pre_master_secret pre-master secret value for SCE. + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[out] sce_master_secret master secret value with SCE-specific conversion. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_MasterSecretGenerate (uint32_t select_cipher_suite, + uint32_t * sce_pre_master_secret, + uint8_t * client_random, + uint8_t * server_random, + uint32_t * sce_master_secret) +{ + uint32_t cipher_suite_sub = 0; + + cipher_suite_sub = change_endian_long(select_cipher_suite); + + return R_SCE_TlsGenerateMasterSecretSub(&cipher_suite_sub, + sce_pre_master_secret, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) (client_random), + (uint32_t *) (server_random), + sce_master_secret); +} + +/*******************************************************************************************************************//** + * Output the result encrypted pre-master secret with RSA 2048bit + * + * @param[in] encrypted_public_key public key data. + * @param[in] sce_pre_master_secret pre-master secret value. + * @param[out] encrypted_pre_master_secret the value encrypted pre-master secret. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_PreMasterSecretEncryptWithRSA2048 (uint32_t * encrypted_public_key, + uint32_t * sce_pre_master_secret, + uint8_t * encrypted_pre_master_secret) +{ + return R_SCE_TlsEncryptPreMasterSecretSub(encrypted_public_key, + sce_pre_master_secret, + /* Casting uint32_t pointer is used for address. */ + (uint32_t *) encrypted_pre_master_secret); +} + +/*******************************************************************************************************************//** + * Output various key information. + * + * @param[in] select_cipher_suite Key suite information number. + * @param[in] sce_master_secret master secret value. + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[in] nonce_explicit nonce value + * @param[out] client_mac_wrapped_key the mac key during communication from client to server. + * @param[out] server_mac_wrapped_key the mac key during communication from server to client. + * @param[out] client_crypto_wrapped_key the crypto key during communication from client to server. + * @param[out] server_crypto_wrapped_key the crypto key during communication from server to client. + * @param[in] client_initial_vector not use. + * @param[in] server_initial_vector not use. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_SessionKeyGenerate (uint32_t select_cipher_suite, + uint32_t * sce_master_secret, + uint8_t * client_random, + uint8_t * server_random, + uint8_t * nonce_explicit, + sce_hmac_sha_wrapped_key_t * client_mac_wrapped_key, + sce_hmac_sha_wrapped_key_t * server_mac_wrapped_key, + sce_aes_wrapped_key_t * client_crypto_wrapped_key, + sce_aes_wrapped_key_t * server_crypto_wrapped_key, + uint8_t * client_initial_vector, + uint8_t * server_initial_vector) +{ + FSP_PARAMETER_NOT_USED(client_initial_vector); + FSP_PARAMETER_NOT_USED(server_initial_vector); + + fsp_err_t error_code = FSP_SUCCESS; + uint32_t cipher_suite = 0; + + cipher_suite = change_endian_long(select_cipher_suite); + + /* Casting uint32_t pointer is used for address. */ + error_code = R_SCE_TlsGenerateSessionKeySub( + /* uint32_t *InData_Sel_CipherSuite, */ &cipher_suite, + /* uint32_t *InData_MasterSecret, */ sce_master_secret, + /* uint32_t *InData_ClientRandom, */ (uint32_t *) (client_random), + /* uint32_t *InData_ServerRandom, */ (uint32_t *) (server_random), + /* uint32_t *InData_NonceExplicit, */ (uint32_t *) (nonce_explicit), + /* uint32_t *OutData_ClientMACKeyOperationCode, */ (uint32_t *) client_mac_wrapped_key->value, + /* uint32_t *OutData_ServerMACKeyOperationCode, */ (uint32_t *) server_mac_wrapped_key->value, + /* uint32_t *OutData_ClientEncKeyOperationCode, */ (uint32_t *) client_crypto_wrapped_key->value, + /* uint32_t *OutData_ServerEncKeyOperationCode, */ (uint32_t *) server_crypto_wrapped_key->value, + /* uint32_t OutLen); */ 0); + + if (FSP_SUCCESS == error_code) + { + if (SCE_TLS_RSA_WITH_AES_128_CBC_SHA == select_cipher_suite) + { + client_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS; + server_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS; + client_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES128_FOR_TLS; + server_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES128_FOR_TLS; + } + else if (SCE_TLS_RSA_WITH_AES_256_CBC_SHA == select_cipher_suite) + { + client_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS; + server_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS; + client_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES256_FOR_TLS; + server_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES256_FOR_TLS; + } + else if (SCE_TLS_RSA_WITH_AES_256_CBC_SHA256 == select_cipher_suite) + { + client_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS; + server_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS; + client_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES256_FOR_TLS; + server_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES256_FOR_TLS; + } + else + { + /* These 5 cases are intentionally combined. */ + /* SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 */ + /* SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 */ + /* SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 */ + /* SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 */ + /* SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 */ + if ((SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 != select_cipher_suite) && + (SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 != select_cipher_suite)) + { + /* These 3 cases are intentionally combined. */ + /* SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 */ + /* SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 */ + /* SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 */ + client_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS; + server_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS; + } + + client_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES128_FOR_TLS; + server_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_AES128_FOR_TLS; + } + } + else + { + client_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + server_mac_wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + client_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + server_crypto_wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * Generate verify data. + * + * @param[in] select_verify_data Select Client/Server data. + * @param[in] sce_master_secret master secret data. + * @param[in] hand_shake_hash TLS hand shake message SHA256 HASH value. + * @param[out] verify_data verify data. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_VerifyDataGenerate (uint32_t select_verify_data, + uint32_t * sce_master_secret, + uint8_t * hand_shake_hash, + uint8_t * verify_data) +{ + uint32_t tmp_select_verify_data = 0; + + tmp_select_verify_data = change_endian_long(select_verify_data); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_TlsGenerateVerifyDataSub( + /* uint32_t *InData_Sel_VerifyData, */ &tmp_select_verify_data, + /* uint32_t *InData_MasterSecret, */ sce_master_secret, + /* uint32_t *InData_HandShakeHash, */ (uint32_t *) (hand_shake_hash), + /* uint32_t *OutData_VerifyData); */ (uint32_t *) (verify_data)); +} + +/*******************************************************************************************************************//** + * Retrives ECDH public key. + * + * @param[in] public_key_type key type + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[in] server_ephemeral_ecdh_public_key Ephemeral ECDH public key from Server. + * @param[in] server_key_exchange_signature Server Key Exchange sigunature. + * @param[in] encrypted_public_key encrypted public key. + * @param[out] encrypted_ephemeral_ecdh_public_key encrypted Ephemeral ECDH public key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_ServerKeyExchangeVerify (uint32_t public_key_type, + uint8_t * client_random, + uint8_t * server_random, + uint8_t * server_ephemeral_ecdh_public_key, + uint8_t * server_key_exchange_signature, + uint32_t * encrypted_public_key, + uint32_t * encrypted_ephemeral_ecdh_public_key) +{ + uint32_t tmp_public_key_type = 0; + uint32_t tmp_compless_type = 0; + + tmp_public_key_type = change_endian_long(public_key_type); + + /* Casting uint32_t pointer is used for address. */ + return R_SCE_TlsServersEphemeralEcdhPublicKeyRetrievesSub( + /* uint32_t *InData_Sel_PubKeyType, */ &tmp_public_key_type, + /* uint32_t *InData_ClientRandom, */ (uint32_t *) client_random, + /* uint32_t *InData_ServerRandom, */ (uint32_t *) server_random, + /* uint32_t *InData_Sel_CompressType, */ &tmp_compless_type, + /* uint32_t *InData_SKE_Message, */ (uint32_t *) server_ephemeral_ecdh_public_key, + /* uint32_t *InData_SKE_Signature, */ (uint32_t *) server_key_exchange_signature, + /* uint32_t *InData_PubKey, */ encrypted_public_key, + /* uint32_t *OutData_EphemeralPubKey */ encrypted_ephemeral_ecdh_public_key); +} + +/*******************************************************************************************************************//** + * Generate encrypted pre-master secret. + * + * @param[in] encrypted_public_key encrypted public key + * @param[in] tls_p256_ecc_wrapped_key P-256 ECC key index. + * @param[out] sce_pre_master_secret encrypted pre-master secret value for SCE. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + * + **********************************************************************************************************************/ +fsp_err_t R_SCE_TLS_PreMasterSecretGenerateForECC_secp256r1 (uint32_t * encrypted_public_key, + sce_tls_p256_ecc_wrapped_key_t * tls_p256_ecc_wrapped_key, + uint32_t * sce_pre_master_secret) +{ + return R_SCE_TlsGeneratePreMasterSecretWithEccP256KeySub( + /* uint32_t *InData_PubKey, */ encrypted_public_key, + /* uint32_t *InData_KeyIndex, */ tls_p256_ecc_wrapped_key->value, + /* uint32_t *OutData_PreMasterSecretIndex */ sce_pre_master_secret); +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c new file mode 100644 index 0000000000..330c23cfb4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c @@ -0,0 +1,1821 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sci_b_uart.h" +#include + +/***********************************************************************************************************************fCCR0 + * Macro definitions + **********************************************************************************************************************/ +#ifndef SCI_B_UART_CFG_RX_ENABLE + #define SCI_B_UART_CFG_RX_ENABLE 1 +#endif +#ifndef SCI_B_UART_CFG_TX_ENABLE + #define SCI_B_UART_CFG_TX_ENABLE 1 +#endif + +/* Number of divisors in the data table used for baud rate calculation. */ +#define SCI_B_UART_NUM_DIVISORS_ASYNC (13U) + +/* Valid range of values for the modulation duty register is 128 - 256 (256 = modulation disabled). */ +#define SCI_B_UART_MDDR_MIN (128U) +#define SCI_B_UART_MDDR_MAX (256U) + +/* The bit rate setting field is of 8-bits, so the maximum value is 255. */ +#define SCI_B_UART_BRR_MAX (255U) + +/* No limit to the number of bytes to read or write if DTC is not used. */ +#define SCI_B_UART_MAX_READ_WRITE_NO_DTC (0xFFFFFFFFU) + +/* Mask off invalid data bits in 9-bit mode. */ +#define SCI_B_UART_ALIGN_2_BYTES (0x1U) + +/* "SCIB" in ASCII. Used to determine if the control block is open. */ +#define SCI_B_UART_OPEN (0x53434942U) + +/* Default SCI Register values. */ +#define SCI_B_UART_CCR2_DEFAULT_VALUE (0xFF00FF04U) +#define SCI_B_UART_FCR_DEFAULT_VALUE (0x1F1F0000U) + +/* SCI CCR1 register bit offsets and masks */ +#define SCI_B_UART_CCR1_SPB2_OFFSET (4U) +#define SCI_B_UART_CCR1_SPB2_MASK (0x00000030U) +#define SCI_B_UART_CCR1_PARITY_OFFSET (8U) +#define SCI_B_UART_CCR1_PARITY_MASK (0x00000300U) +#define SCI_B_UART_CCR1_FLOW_CTSRTS_MASK (0x00000003U) + +/* SCI CCR3 register bit offsets and masks */ +#define SCI_B_UART_CCR3_CHAR_OFFSET (8U) +#define SCI_B_UART_CCR3_CHAR_MASK (0x00000300U) +#define SCI_B_UART_CCR3_CKE_OFFSET (24U) +#define SCI_B_UART_CCR3_CKE_MASK (0x03000000U) + +/* SCI Data register bit masks */ +#define SCI_B_UART_TDR_TDAT_MASK_9BITS (0x000091FFU) + +/* SCI CSR register receiver error (overflow, framing, parity) bits masks */ +#define SCI_B_UART_RCVR_ERR_MASK (R_SCI_B0_CSR_ORER_Msk | R_SCI_B0_CSR_FER_Msk | R_SCI_B0_CSR_PER_Msk) + +/* SCI Error event masks */ +#define SCI_B_UART_ORR_EVENT8_MASK (0x20) +#define SCI_B_UART_ERR_EVENT8_MASK (0x38) + +/* SCI CFCLR register bit masks */ +#define SCI_B_UART_CFCLR_CLEAR_ALL_MASK (0x9D070010U) +#define SCI_B_UART_CFCLR_RDRFC_MASK (0x80000000U) +#define SCI_B_UART_CFCLR_TDREC_MASK (0x20000000U) + +/* SCI FFCLR register bit masks */ +#define SCI_B_UART_FFCLR_CLEAR_ALL_MASK (0x00000001U) + +/* SCI chanel size */ +#define SCI_B_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE) + +#define SCI_B_UART_INVALID_16BIT_PARAM (0xFFFFU) +#define SCI_B_UART_DTC_MAX_TRANSFER (0x10000U) + +/* SCI FCR register bit masks */ +#define SCI_B_UART_FCR_TRIGGER_MASK (0xF) +#define SCI_B_UART_FCR_RESET_TX_RX (0x00808000U) + +/* DTC Configuration for Receive operation */ +#define SCI_B_UART_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +/* DTC Configuration for Transmit operation */ +#define SCI_B_UART_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +/* Flow Control pin active state */ +#ifndef SCI_B_UART_FLOW_CONTROL_ACTIVE + #define SCI_B_UART_FLOW_CONTROL_ACTIVE BSP_IO_LEVEL_HIGH +#endif + +/* Flow Control pin inactive state */ +#ifndef SCI_B_UART_FLOW_CONTROL_INACTIVE + #define SCI_B_UART_FLOW_CONTROL_INACTIVE BSP_IO_LEVEL_LOW +#endif + +/*********************************************************************************************************************** + * Private constants + **********************************************************************************************************************/ +static const int32_t SCI_B_UART_100_PERCENT_X_1000 = 100000; +static const int32_t SCI_B_UART_MDDR_DIVISOR = 256; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) +static const uint32_t SCI_B_UART_MAX_BAUD_RATE_ERROR_X_1000 = 15000; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_baud_setting_const_t +{ + uint8_t bgdm : 1; /**< BGDM value to get divisor */ + uint8_t abcs : 1; /**< ABCS value to get divisor */ + uint8_t abcse : 1; /**< ABCSE value to get divisor */ + uint8_t cks : 2; /**< CKS value to get divisor (CKS = N) */ +} baud_setting_const_t; + +/* Noise filter setting definition */ +typedef enum e_noise_cancel_lvl +{ + NOISE_CANCEL_LVL1 = 0, /**< Noise filter level 1(weak) */ + NOISE_CANCEL_LVL2 = 2, /**< Noise filter level 2 */ + NOISE_CANCEL_LVL3 = 4, /**< Noise filter level 3 */ + NOISE_CANCEL_LVL4 = 8, /**< Noise filter level 4(strong) */ +} noise_cancel_lvl_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * sci_b_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_b_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) +static fsp_err_t r_sci_b_read_write_param_check(sci_b_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + +#endif + +static void r_sci_b_uart_config_set(sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +#if SCI_B_UART_CFG_DTC_SUPPORTED +static fsp_err_t r_sci_b_uart_transfer_configure(sci_b_uart_instance_ctrl_t * const p_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t address); + +static fsp_err_t r_sci_b_uart_transfer_open(sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +static void r_sci_b_uart_transfer_close(sci_b_uart_instance_ctrl_t * p_ctrl); + +#endif + +static void r_sci_b_uart_call_callback(sci_b_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); + +#if SCI_B_UART_CFG_FIFO_SUPPORT +static void r_sci_b_uart_fifo_cfg(sci_b_uart_instance_ctrl_t * const p_ctrl); + +#endif + +static void r_sci_b_irq_cfg(sci_b_uart_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const p_irq); + +static void r_sci_b_irqs_cfg(sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +#if (SCI_B_UART_CFG_RX_ENABLE) +void sci_b_uart_rxi_isr(void); + +void sci_b_uart_eri_isr(void); + +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) +void sci_b_uart_txi_isr(void); +void sci_b_uart_tei_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Baud rate divisor information (UART mode) */ +static const baud_setting_const_t g_async_baud[SCI_B_UART_NUM_DIVISORS_ASYNC] = +{ + {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ + {1U, 1U, 0U, 0U}, + {1U, 0U, 0U, 0U}, + {0U, 0U, 1U, 1U}, + {0U, 0U, 0U, 0U}, + {1U, 0U, 0U, 1U}, + {0U, 0U, 1U, 2U}, + {0U, 0U, 0U, 1U}, + {1U, 0U, 0U, 2U}, + {0U, 0U, 1U, 3U}, + {0U, 0U, 0U, 2U}, + {1U, 0U, 0U, 3U}, + {0U, 0U, 0U, 3U} +}; + +static const uint16_t g_div_coefficient[SCI_B_UART_NUM_DIVISORS_ASYNC] = +{ + 6U, + 8U, + 16U, + 24U, + 32U, + 64U, + 96U, + 128U, + 256U, + 384U, + 512U, + 1024U, + 2048U, +}; + +/* UART on SCI HAL API mapping for UART interface */ +const uart_api_t g_uart_on_sci_b = +{ + .open = R_SCI_B_UART_Open, + .close = R_SCI_B_UART_Close, + .write = R_SCI_B_UART_Write, + .read = R_SCI_B_UART_Read, + .infoGet = R_SCI_B_UART_InfoGet, + .baudSet = R_SCI_B_UART_BaudSet, + .communicationAbort = R_SCI_B_UART_Abort, + .callbackSet = R_SCI_B_UART_CallbackSet, + .readStop = R_SCI_B_UART_ReadStop, + .receiveSuspend = R_SCI_B_UART_ReceiveSuspend, + .receiveResume = R_SCI_B_UART_ReceiveResume, +}; + +/*******************************************************************************************************************//** + * @addtogroup SCI_B_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is + * enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_INVALID_ARGUMENT Flow control is enabled but flow control pin is not defined. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(((sci_b_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting); + FSP_ERROR_RETURN(SCI_B_UART_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS_MASK & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + if (((sci_b_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control == SCI_B_UART_FLOW_CONTROL_CTSRTS) + { + FSP_ERROR_RETURN( + ((sci_b_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control_pin != SCI_B_UART_INVALID_16BIT_PARAM, + FSP_ERR_INVALID_ARGUMENT); + } + + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); +#endif + + p_ctrl->p_reg = (R_SCI_B0_Type *) (R_SCI0_BASE + (SCI_B_REG_SIZE * p_cfg->channel)); + + p_ctrl->fifo_depth = 0U; +#if SCI_B_UART_CFG_FIFO_SUPPORT + + /* Check if the channel supports fifo */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK & (1U << p_cfg->channel)) + { + /* Set fifo depth. */ + p_ctrl->fifo_depth = BSP_FEATURE_SCI_UART_FIFO_DEPTH; + } +#endif + + p_ctrl->p_cfg = p_cfg; + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + sci_b_uart_extended_cfg_t * p_extend = (sci_b_uart_extended_cfg_t *) p_cfg->p_extend; + + p_ctrl->data_bytes = 1U; + if (UART_DATA_BITS_9 == p_cfg->data_bits) + { + p_ctrl->data_bytes = 2U; + } + + /* Configure the interrupts. */ + r_sci_b_irqs_cfg(p_ctrl, p_cfg); + +#if SCI_B_UART_CFG_DTC_SUPPORTED + + /* Configure the transfer interface for transmission and reception if provided. */ + fsp_err_t err = r_sci_b_uart_transfer_open(p_ctrl, p_cfg); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + uint32_t ccr0 = R_SCI_B0_CCR0_IDSEL_Msk; + + /* Enable the SCI channel */ + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + + /* Initialize registers as defined in "SCI Initialization in Asynchronous Mode" + * in relevant hardware manual. */ + p_ctrl->p_reg->CCR0 = ccr0; + + /* Set the UART configuration settings provided in ::uart_cfg_t and ::sci_b_uart_extended_cfg_t. */ + r_sci_b_uart_config_set(p_ctrl, p_cfg); + + p_ctrl->p_tx_src = NULL; + p_ctrl->tx_src_bytes = 0U; + p_ctrl->p_rx_dest = NULL; + p_ctrl->rx_dest_bytes = 0; + + /* Set flow control pins. */ + p_ctrl->flow_pin = p_extend->flow_control_pin; + +#if SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT + if (p_ctrl->flow_pin != SCI_B_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_B_UART_FLOW_CONTROL_INACTIVE); + R_BSP_PinAccessDisable(); + } +#endif + + /* Clear all flags in CSR register. */ + p_ctrl->p_reg->CFCLR = SCI_B_UART_CFCLR_CLEAR_ALL_MASK; + +#if SCI_B_UART_CFG_FIFO_SUPPORT + p_ctrl->p_reg->FFCLR = SCI_B_UART_FFCLR_CLEAR_ALL_MASK; +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, enable reception. */ + ccr0 |= R_SCI_B0_CCR0_RE_Msk; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->eri_irq); + + ccr0 |= R_SCI_B0_CCR0_RIE_Msk; +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) + + /* NOTE: Transmitter and its interrupt are enabled in R_SCI_B_UART_Write(). */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->tei_irq); + + ccr0 |= R_SCI_B0_CCR0_TE_Msk; +#endif + p_ctrl->p_reg->CCR0 = ccr0; + + /* Wait until interanl state of RE is 1 as it takes some time for the state to be reflected internally after + * rewriting the control register. See "CESR : Communication Enable Status Register" description + * in the SCI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.RIST, 1U); + + p_ctrl->open = SCI_B_UART_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Removes power. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Close (uart_ctrl_t * const p_api_ctrl) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); +#endif + + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + +#if (SCI_B_UART_CFG_TX_ENABLE) + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth > 0U) + { + /* Reset the transmit fifo */ + p_ctrl->p_reg->FCR_b.TFRST = 1U; + + /* Clear the CCR3_b.FM bit. This is necessary to set the TEND bit before setting the TE bit. If TEND is 0 + * when TE is set to 0, the SCI peripheral works abnormally next time the TE made to 1.*/ + p_ctrl->p_reg->CCR3 = 0U; + } + #endif + + /* Disable transmission */ + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); + + /* Wait until interanl state of TE is 0 as it takes some time for the state to be reflected internally after + * rewriting the control register. See "CESR : Communication Enable Status Register" description + * in the SCI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.TIST, 0U); + + /* If transmission is enabled at build time, disable transmission irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_RIE_Msk); + + /* If reception is enabled at build time, disable reception irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); +#endif + +#if SCI_B_UART_CFG_DTC_SUPPORTED + + /* Close the lower level transfer instances. */ + r_sci_b_uart_transfer_close(p_ctrl); +#endif + + /* Remove power to the channel. */ + R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel); + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_INVALID_ARGUMENT Destination address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @retval FSP_ERR_UNSUPPORTED SCI_B_UART_CFG_RX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + * @note If 9-bit data length is specified at R_SCI_B_UART_Open call, p_dest must be aligned 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ +#if (SCI_B_UART_CFG_RX_ENABLE) + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_b_read_write_param_check(p_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->rx_dest_bytes, FSP_ERR_IN_USE); + #endif + + #if SCI_B_UART_CFG_DTC_SUPPORTED + + /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + uint32_t size = bytes >> (p_ctrl->data_bytes - 1); + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(size <= SCI_B_UART_DTC_MAX_TRANSFER); + #endif + err = + p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, NULL, (void *) p_dest, + (uint16_t) size); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Save the destination address and size for use in rxi_isr. */ + p_ctrl->p_rx_dest = p_dest; + p_ctrl->rx_dest_bytes = bytes; + + return err; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_INVALID_ARGUMENT Source address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UART transmission is in progress + * @retval FSP_ERR_UNSUPPORTED SCI_B_UART_CFG_TX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + * @note If 9-bit data length is specified at R_SCI_B_UART_Open call, p_src must be aligned on a 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ +#if (SCI_B_UART_CFG_TX_ENABLE) + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + #if SCI_B_UART_CFG_PARAM_CHECKING_ENABLE || SCI_B_UART_CFG_DTC_SUPPORTED + fsp_err_t err = FSP_SUCCESS; + #endif + + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_b_read_write_param_check(p_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE); + #endif + + /* Transmit interrupts must be disabled to start with. */ + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + /* Make sure no transmission is in progress. Setting CCR0_b.TE to 0 when CSR_b.TEND is 0 causes SCI peripheral + * to work abnormally. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CSR_b.TEND, 1U); + + /* Set TE bit to 0. This is done to set TE and TIE bit simultaneously at the end of this function. + * See "Serial Data Transmission in Asynchronous Mode" in the SCI section of the relevant hardware manual. */ + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); + + /* Wait until interanl state of TE is 0 as it takes some time for the state to be reflected internally after + * rewriting the control register. See "CESR : Communication Enable Status Register" description + * in the SCI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.TIST, 0U); + + p_ctrl->tx_src_bytes = bytes; + p_ctrl->p_tx_src = p_src; + + #if SCI_B_UART_CFG_DTC_SUPPORTED + + /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested + * data. */ + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && p_ctrl->tx_src_bytes) + { + uint32_t data_bytes = p_ctrl->data_bytes; + uint32_t num_transfers = p_ctrl->tx_src_bytes >> (data_bytes - 1); + p_ctrl->tx_src_bytes = 0U; + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(num_transfers <= SCI_B_UART_DTC_MAX_TRANSFER); + #endif + + err = p_ctrl->p_cfg->p_transfer_tx->p_api->reset(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + (void const *) p_ctrl->p_tx_src, + NULL, + (uint16_t) num_transfers); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Set TE and TIE bits simultaneously by single instruction to enable TIE interrupt. + * See "Serial Data Transmission in Asynchronous Mode" in the SCI section of the relevant + * hardware manual. */ + p_ctrl->p_reg->CCR0 |= (uint32_t) (R_SCI_B0_CCR0_TE_Msk | R_SCI_B0_CCR0_TIE_Msk); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_B_UART_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + uart_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(uart_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a + * sci_b_baud_setting_t structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify that the On-Chip baud rate generator is currently selected. */ + FSP_ASSERT((p_ctrl->p_reg->CCR3_b.CKE & 0x2) == 0U); +#endif + + /* Save SCR configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is + * not supported. */ + uint32_t preserved_ccr0 = p_ctrl->p_reg->CCR0 & (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + /* Disables transmitter and receiver. This terminates any in-progress transmission. */ + p_ctrl->p_reg->CCR0 = preserved_ccr0 & + (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk | R_SCI_B0_CCR0_RE_Msk | R_SCI_B0_CCR0_RIE_Msk); + p_ctrl->p_tx_src = NULL; + + /* Apply new baud rate register settings. */ + p_ctrl->p_reg->CCR2 = ((sci_b_baud_setting_t *) p_baud_setting)->baudrate_bits; + + /* Restore all settings except transmit interrupts. */ + p_ctrl->p_reg->CCR0 = preserved_ccr0; + + /* Restore all settings except transmit interrupts. */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info) +{ +#if SCI_B_UART_CFG_PARAM_CHECKING_ENABLE || SCI_B_UART_CFG_DTC_SUPPORTED + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_info); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_info->read_bytes_max = SCI_B_UART_MAX_READ_WRITE_NO_DTC; + p_info->write_bytes_max = SCI_B_UART_MAX_READ_WRITE_NO_DTC; + +#if (SCI_B_UART_CFG_RX_ENABLE) + + /* Store number of bytes that can be read at a time. */ + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_info->read_bytes_max = SCI_B_UART_DTC_MAX_TRANSFER; + } + #endif +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) + + /* Store number of bytes that can be written at a time. */ + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_info->write_bytes_max = SCI_B_UART_DTC_MAX_TRANSFER; + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) + if (UART_DIR_TX & communication_to_abort) + { + err = FSP_SUCCESS; + + /* Transmit interrupts must be disabled to start with. */ + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + /* Make sure no transmission is in progress. Setting CCR0_b.TE to 0 when CSR_b.TEND is 0 causes SCI peripheral + * to work abnormally. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CSR_b.TEND, 1U); + + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); + + /* Wait until interanl state of TE is 0 as it takes some time for the state to be reflected + * internally after rewriting the control register. See "CESR : Communication + * Enable Status Register" description in the SCI section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.TIST, 0U); + + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + err = p_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif + + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth > 0U) + { + /* Reset the transmit fifo */ + p_ctrl->p_reg->FCR_b.TFRST = 1U; + } + #endif + p_ctrl->tx_src_bytes = 0U; + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif +#if (SCI_B_UART_CFG_RX_ENABLE) + if (UART_DIR_RX & communication_to_abort) + { + err = FSP_SUCCESS; + + p_ctrl->rx_dest_bytes = 0U; + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_ctrl->p_reg->FCR_b.RFRST = 1U; + } + #endif + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes) +{ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + *remaining_bytes = p_ctrl->rx_dest_bytes; + p_ctrl->rx_dest_bytes = 0U; + #if SCI_B_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + transfer_properties_t transfer_info; + err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + *remaining_bytes = transfer_info.transfer_length_remaining; + } + #endif + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_ctrl->p_reg->FCR_b.RFRST = 1U; + } + #endif +#else + + return FSP_ERR_UNSUPPORTED; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. + * + * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. + * @param[in] bitrate_modulation Enable bitrate modulation + * @param[in] baud_rate_error_x_1000 Max baud rate error. At most <baud_rate_percent_error> x 1000 required + * for module to function. Absolute max baud_rate_error is 15000 (15%). + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is set successfully + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', error in calculated baud rate is larger than requested + * max error, or requested max error in baud rate is larger than 15%. + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_BaudCalculate (uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + sci_b_baud_setting_t * const p_baud_setting) +{ +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN(SCI_B_UART_MAX_BAUD_RATE_ERROR_X_1000 >= baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT); +#endif + + p_baud_setting->baudrate_bits_b.brr = SCI_B_UART_BRR_MAX; + p_baud_setting->baudrate_bits_b.brme = 0U; + p_baud_setting->baudrate_bits_b.mddr = SCI_B_UART_MDDR_MIN; + + /* Find the best BRR (bit rate register) value. + * In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values. Each set of divisors + * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as + * follows and it must be 255 or less: + * BRR = (PCLK / (div_coefficient * baud)) - 1 + */ + int32_t hit_bit_err = SCI_B_UART_100_PERCENT_X_1000; + uint8_t hit_mddr = 0U; + uint32_t divisor = 0U; + +#if (BSP_FEATURE_SCI_HAS_SCISPI_CLOCK) + uint32_t freq_hz = R_FSP_SciSpiClockHzGet(); +#else + uint32_t freq_hz = R_FSP_SciClockHzGet(); +#endif + + for (uint32_t select_16_base_clk_cycles = 0U; + select_16_base_clk_cycles <= 1U && (hit_bit_err > ((int32_t) baud_rate_error_x_1000)); + select_16_base_clk_cycles++) + { + for (uint32_t i = 0U; i < SCI_B_UART_NUM_DIVISORS_ASYNC; i++) + { + /* if select_16_base_clk_cycles == true: Skip this calculation for divisors that are not achievable with 16 base clk cycles per bit. + * if select_16_base_clk_cycles == false: Skip this calculation for divisors that are only achievable without 16 base clk cycles per bit. + */ + if (((uint8_t) select_16_base_clk_cycles) ^ (g_async_baud[i].abcs | g_async_baud[i].abcse)) + { + continue; + } + + divisor = (uint32_t) g_div_coefficient[i] * baudrate; + uint32_t temp_brr = freq_hz / divisor; + + if (temp_brr <= (SCI_B_UART_BRR_MAX + 1U)) + { + while (temp_brr > 0U) + { + temp_brr -= 1U; + + /* Calculate the bit rate error. The formula is as follows: + * bit rate error[%] = {(PCLK / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * calculates bit rate error[%] to three decimal places + */ + int32_t err_divisor = (int32_t) (divisor * (temp_brr + 1U)); + + /* Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. (temp_brr + 1) can be off by an upper limit of 1 due to rounding from the calculation: + * freq_hz / divisor, or: + * freq_hz / divisor <= (temp_brr + 1) < (freq_hz / divisor) + 1 + * 2. Solving for err_divisor: + * freq_hz <= err_divisor < freq_hz + divisor + * 3. Solving for bit_err: + * 0 >= bit_err >= (freq_hz * 100000 / (freq_hz + divisor)) - 100000 + * 4. freq_hz >= divisor (or temp_brr would be -1 and we would never enter this while loop), so: + * 0 >= bit_err >= 100000 / freq_hz - 100000 + * 5. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the bit_err approaches -100000, so: + * 0 >= bit_err >= -100000 + * 6. bit_err is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ + int32_t bit_err = (int32_t) (((((int64_t) freq_hz) * SCI_B_UART_100_PERCENT_X_1000) / + err_divisor) - SCI_B_UART_100_PERCENT_X_1000); + + uint8_t mddr = 0U; + if (bitrate_modulation) + { + /* Calculate the MDDR (M) value if bit rate modulation is enabled, + * The formula to calculate MBBR (from the M and N relationship given in the hardware manual) is as follows + * and it must be between 128 and 255. + * MDDR = ((div_coefficient * baud * 256) * (BRR + 1)) / PCLK */ + mddr = (uint8_t) ((uint32_t) err_divisor / (freq_hz / SCI_B_UART_MDDR_MAX)); + + /* MDDR value must be greater than or equal to SCI_B_UART_MDDR_MIN. */ + if (mddr < SCI_B_UART_MDDR_MIN) + { + break; + } + + /* Adjust bit rate error for bit rate modulation. The following formula is used: + * bit rate error [%] = ((bit rate error [%, no modulation] + 100) * MDDR / 256) - 100 + */ + bit_err = (((bit_err + SCI_B_UART_100_PERCENT_X_1000) * (int32_t) mddr) / + SCI_B_UART_MDDR_DIVISOR) - SCI_B_UART_100_PERCENT_X_1000; + } + + /* Take the absolute value of the bit rate error. */ + if (bit_err < 0) + { + bit_err = -bit_err; + } + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if (bit_err < hit_bit_err) + { + p_baud_setting->baudrate_bits_b.bgdm = g_async_baud[i].bgdm; + p_baud_setting->baudrate_bits_b.abcs = g_async_baud[i].abcs; + p_baud_setting->baudrate_bits_b.abcse = g_async_baud[i].abcse; + p_baud_setting->baudrate_bits_b.cks = g_async_baud[i].cks; + p_baud_setting->baudrate_bits_b.brr = (uint8_t) temp_brr; + hit_bit_err = bit_err; + hit_mddr = mddr; + } + + if (bitrate_modulation) + { + p_baud_setting->baudrate_bits_b.brme = 1U; + p_baud_setting->baudrate_bits_b.mddr = hit_mddr; + } + else + { + break; + } + } + } + } + } + + /* Return an error if the percent error is larger than the maximum percent error allowed for this instance */ + FSP_ERROR_RETURN((hit_bit_err <= (int32_t) baud_rate_error_x_1000), FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Suspend Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_ReceiveSuspend (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Resume Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_SCI_B_UART_ReceiveResume (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_B_UART) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL + * @retval FSP_ERR_INVALID_ARGUMENT Address is not aligned to 2-byte boundary or size is the odd number when the data + * length is 9-bit + **********************************************************************************************************************/ +static fsp_err_t r_sci_b_read_write_param_check (sci_b_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(addr); + FSP_ASSERT(0U != bytes); + FSP_ERROR_RETURN(SCI_B_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + if (2U == p_ctrl->data_bytes) + { + /* Do not allow odd buffer address if data length is 9 bits. */ + FSP_ERROR_RETURN((0U == ((uint32_t) addr & SCI_B_UART_ALIGN_2_BYTES)), FSP_ERR_INVALID_ARGUMENT); + + /* Do not allow odd number of data bytes if data length is 9 bits. */ + FSP_ERROR_RETURN(0U == (bytes % 2U), FSP_ERR_INVALID_ARGUMENT); + } + + return FSP_SUCCESS; +} + +#endif +#if SCI_B_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Subroutine to apply common UART transfer settings. + * + * @param[in] p_cfg Pointer to UART specific configuration structure + * @param[in] p_transfer Pointer to transfer instance to configure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer + **********************************************************************************************************************/ +static fsp_err_t r_sci_b_uart_transfer_configure (sci_b_uart_instance_ctrl_t * const p_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t sci_buffer_address) +{ + /* Configure the transfer instance, if enabled. */ + #if (SCI_B_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend); + #endif + + transfer_info_t * p_info = p_transfer->p_cfg->p_info; + + p_info->transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE; + + if (UART_DATA_BITS_9 == p_ctrl->p_cfg->data_bits) + { + p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + } + + /* Casting for compatibility with 7 or 8 bit mode. */ + *p_transfer_reg = sci_buffer_address; + + fsp_err_t err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +#endif + +#if SCI_B_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Configures UART related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer or required interrupt not enabled in vector table + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +static fsp_err_t r_sci_b_uart_transfer_open (sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_B_UART_CFG_RX_ENABLE) + + /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_rx) + { + transfer_info_t * p_info = p_cfg->p_transfer_rx->p_cfg->p_info; + + p_info->transfer_settings_word = SCI_B_UART_DTC_RX_TRANSFER_SETTINGS; + + err = + r_sci_b_uart_transfer_configure(p_ctrl, p_cfg->p_transfer_rx, (uint32_t *) &p_info->p_src, + (uint32_t) &(p_ctrl->p_reg->RDR)); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + #if (SCI_B_UART_CFG_TX_ENABLE) + + /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_tx) + { + transfer_info_t * p_info = p_cfg->p_transfer_tx->p_cfg->p_info; + + p_info->transfer_settings_word = SCI_B_UART_DTC_TX_TRANSFER_SETTINGS; + + err = r_sci_b_uart_transfer_configure(p_ctrl, + p_cfg->p_transfer_tx, + (uint32_t *) &p_info->p_dest, + (uint32_t) &p_ctrl->p_reg->TDR); + + #if (SCI_B_UART_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_cfg->p_transfer_rx)) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + #endif + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Configures UART related registers based on user configurations. + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_b_uart_config_set (sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + sci_b_uart_extended_cfg_t * p_extend = (sci_b_uart_extended_cfg_t *) p_cfg->p_extend; + sci_b_baud_setting_t * p_baud_setting = p_extend->p_baud_setting; + uint32_t ccr2 = 0U; + + /* Set Character length, Stop bit length, Start bit edge detection and SCI mode as Asynchronous mode. */ + uint32_t ccr3 = (uint32_t) R_SCI_B0_CCR3_LSBF_Msk; + ccr3 |= ((uint32_t) p_cfg->data_bits << SCI_B_UART_CCR3_CHAR_OFFSET) & SCI_B_UART_CCR3_CHAR_MASK; + ccr3 |= ((uint32_t) p_cfg->stop_bits << R_SCI_B0_CCR3_STP_Pos) & R_SCI_B0_CCR3_STP_Msk; + ccr3 |= ((uint32_t) p_extend->rx_edge_start << R_SCI_B0_CCR3_RXDESEL_Pos) & R_SCI_B0_CCR3_RXDESEL_Msk; + ccr3 |= ((uint32_t) p_extend->rs485_setting.enable << R_SCI_B0_CCR3_DEN_Pos) & R_SCI_B0_CCR3_DEN_Msk; + ccr3 |= ((uint32_t) p_extend->clock << SCI_B_UART_CCR3_CKE_OFFSET) & SCI_B_UART_CCR3_CKE_MASK; +#if SCI_B_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth > 0U) + { + ccr3 |= (1U << R_SCI_B0_CCR3_FM_Pos) & R_SCI_B0_CCR3_FM_Msk; + } +#endif + p_ctrl->p_reg->CCR3 = ccr3; + + if ((SCI_B_UART_CLOCK_EXT8X == p_extend->clock) || (SCI_B_UART_CLOCK_EXT16X == p_extend->clock)) + { + /* Use external clock for baud rate */ + ccr2 = SCI_B_UART_CCR2_DEFAULT_VALUE; + + if (SCI_B_UART_CLOCK_EXT8X == p_extend->clock) + { + /* Set baud rate as (external clock / 8) */ + ccr2 |= 1U << R_SCI_B0_CCR2_ABCS_Pos; + } + } + else + { + /* Set the baud rate settings for the internal baud rate generator. */ + ccr2 |= p_baud_setting->baudrate_bits; + } + + p_ctrl->p_reg->CCR2 = ccr2; + + /* Configure flow control pin. */ + uint32_t ccr1 = ((uint32_t) (p_extend->flow_control << R_SCI_B0_CCR1_CTSE_Pos) & SCI_B_UART_CCR1_FLOW_CTSRTS_MASK); + + /* TXD pin is at high level when TE is 0. */ + ccr1 |= (3U << SCI_B_UART_CCR1_SPB2_OFFSET) & SCI_B_UART_CCR1_SPB2_MASK; + + if (0 != p_cfg->parity) + { + ccr1 |= + (((UART_PARITY_EVEN == + p_cfg->parity) ? 1U : 3U) << SCI_B_UART_CCR1_PARITY_OFFSET) & SCI_B_UART_CCR1_PARITY_MASK; + } + + ccr1 |= ((uint32_t) p_extend->noise_cancel << R_SCI_B0_CCR1_NFEN_Pos) & + R_SCI_B0_CCR1_NFEN_Msk; + p_ctrl->p_reg->CCR1 = ccr1; + + p_ctrl->p_reg->CCR4 = 0U; + +#if SCI_B_UART_CFG_FIFO_SUPPORT + + /* Configure FIFO related registers. */ + r_sci_b_uart_fifo_cfg(p_ctrl); +#else + + /* If fifo support is disabled and the current channel supports fifo set FCR to default */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK & (1U << p_cfg->channel)) + { + p_ctrl->p_reg->FCR = SCI_B_UART_FCR_DEFAULT_VALUE; + } +#endif + + /* Configure RS-485 DE assertion settings. */ + uint32_t dcr = ((uint32_t) (p_extend->rs485_setting.polarity << R_SCI_B0_DCR_DEPOL_Pos)) & R_SCI_B0_DCR_DEPOL_Msk; + dcr |= ((uint32_t) p_extend->rs485_setting.assertion_time << R_SCI_B0_DCR_DEAST_Pos) & + R_SCI_B0_DCR_DEAST_Msk; + dcr |= ((uint32_t) p_extend->rs485_setting.negation_time << R_SCI_B0_DCR_DENGT_Pos) & + R_SCI_B0_DCR_DENGT_Msk; + p_ctrl->p_reg->DCR = dcr; +} + +#if SCI_B_UART_CFG_FIFO_SUPPORT + +/*******************************************************************************************************************//** + * Resets FIFO related registers. + * + * @param[in] p_ctrl Pointer to UART instance control + * @param[in] p_cfg Pointer to UART configuration structure + **********************************************************************************************************************/ +static void r_sci_b_uart_fifo_cfg (sci_b_uart_instance_ctrl_t * const p_ctrl) +{ + if (0U != p_ctrl->fifo_depth) + { + uint32_t fcr = 0U; + + /* Set the tx and rx reset bits */ + p_ctrl->p_reg->FCR = (uint32_t) (SCI_B_UART_FCR_RESET_TX_RX); + + #if SCI_B_UART_CFG_RX_ENABLE + #if SCI_B_UART_CFG_DTC_SUPPORTED + + /* If DTC is used keep the receive trigger at the default level of 0. */ + if (NULL == p_ctrl->p_cfg->p_transfer_rx) + #endif + { + /* Otherwise, set receive trigger number as configured by the user. */ + sci_b_uart_extended_cfg_t const * p_extend = p_ctrl->p_cfg->p_extend; + + /* RTRG(Receive FIFO Data Trigger Number) controls when the RXI interrupt will be generated. If data is + * received but the trigger number is not met the RXI interrupt will be generated after 15 ETUs from + * the last stop bit in asynchronous mode. For more information see the FIFO Selected section of "Serial + * Data Reception in Asynchronous Mode" in the SCI section of the relevant hardware manual. */ + fcr |= (((p_ctrl->fifo_depth - 1U) & p_extend->rx_fifo_trigger) & SCI_B_UART_FCR_TRIGGER_MASK) << + R_SCI_B0_FCR_RTRG_Pos; + } + + /* RTS asserts when the amount of received data stored in the fifo is equal or less than this value. */ + fcr |= ((p_ctrl->fifo_depth - 1U) & SCI_B_UART_FCR_TRIGGER_MASK) << R_SCI_B0_FCR_RSTRG_Pos; + #endif + + /* Set the FCR and reset the fifos. */ + p_ctrl->p_reg->FCR |= fcr; + } +} + +#endif + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info. + * + * @param[in] p_ctrl Pointer to driver control block + * @param[in] ipl Interrupt priority level + * @param[in] irq IRQ number for this interrupt + **********************************************************************************************************************/ +static void r_sci_b_irq_cfg (sci_b_uart_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const irq) +{ + /* Disable interrupts, set priority, and store control block in the vector information so it can be accessed + * from the callback. */ + R_BSP_IrqDisable(irq); + R_BSP_IrqStatusClear(irq); + R_BSP_IrqCfg(irq, ipl, p_ctrl); +} + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info for all interrupts. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_b_irqs_cfg (sci_b_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ +#if (SCI_B_UART_CFG_RX_ENABLE) + + /* ERI is optional. */ + r_sci_b_irq_cfg(p_ctrl, p_cfg->eri_ipl, p_cfg->eri_irq); + r_sci_b_irq_cfg(p_ctrl, p_cfg->rxi_ipl, p_cfg->rxi_irq); +#endif +#if (SCI_B_UART_CFG_TX_ENABLE) + r_sci_b_irq_cfg(p_ctrl, p_cfg->txi_ipl, p_cfg->txi_irq); + r_sci_b_irq_cfg(p_ctrl, p_cfg->tei_ipl, p_cfg->tei_irq); +#endif +} + +#if SCI_B_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Closes transfer interfaces. + * + * @param[in] p_ctrl Pointer to UART instance control block + **********************************************************************************************************************/ +static void r_sci_b_uart_transfer_close (sci_b_uart_instance_ctrl_t * p_ctrl) +{ + #if (SCI_B_UART_CFG_RX_ENABLE) + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if (SCI_B_UART_CFG_TX_ENABLE) + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_b_uart_call_callback (sci_b_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) +{ + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + uart_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_b_uart_prv_ns_callback p_callback = (sci_b_uart_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +#if (SCI_B_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TXI interrupt processing for UART mode. TXI interrupt fires when the data in the data register or FIFO register has + * been transferred to the data shift register, and the next data can be written. This interrupt writes the next data. + * After the last data byte is written, this interrupt disables the TXI interrupt and enables the TEI (transmit end) + * interrupt. + **********************************************************************************************************************/ +void sci_b_uart_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if ((NULL == p_ctrl->p_cfg->p_transfer_tx) && (0U != p_ctrl->tx_src_bytes)) + { + /* Fill the FIFO if its used. Otherwise write data to the TDR. */ + #if SCI_B_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + uint32_t fifo_count = p_ctrl->p_reg->FTSR_b.T; + for (uint32_t cnt = fifo_count; (cnt < p_ctrl->fifo_depth) && p_ctrl->tx_src_bytes; cnt++) + { + if ((2U == p_ctrl->data_bytes)) + { + /* Write 16-bit data to TDR register */ + p_ctrl->p_reg->TDR = (uint32_t) (*(uint16_t *) (p_ctrl->p_tx_src)) & SCI_B_UART_TDR_TDAT_MASK_9BITS; + } + else + { + /* Write 1byte data to TDR_BY register */ + p_ctrl->p_reg->TDR_BY = (*(p_ctrl->p_tx_src)); + } + + p_ctrl->tx_src_bytes -= p_ctrl->data_bytes; + p_ctrl->p_tx_src += p_ctrl->data_bytes; + } + + /* Clear TDRE flag */ + p_ctrl->p_reg->CFCLR |= SCI_B_UART_CFCLR_TDREC_MASK; + } + else + #endif + { + if ((2U == p_ctrl->data_bytes)) + { + /* Write 16-bit data to TDR register */ + p_ctrl->p_reg->TDR = (uint32_t) (*(uint16_t *) (p_ctrl->p_tx_src)) & SCI_B_UART_TDR_TDAT_MASK_9BITS; + } + else + { + /* Write 1byte data to TDR_BY register */ + p_ctrl->p_reg->TDR_BY = (*(p_ctrl->p_tx_src)); + } + + p_ctrl->tx_src_bytes -= p_ctrl->data_bytes; + p_ctrl->p_tx_src += p_ctrl->data_bytes; + } + } + + if (0U == p_ctrl->tx_src_bytes) + { + /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */ + uint32_t ccr0_temp = p_ctrl->p_reg->CCR0; + ccr0_temp |= R_SCI_B0_CCR0_TEIE_Msk; + ccr0_temp &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk); + p_ctrl->p_reg->CCR0 = ccr0_temp; + + p_ctrl->p_tx_src = NULL; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + r_sci_b_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY); + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * RXI interrupt processing for UART mode. RXI interrupt happens when data arrives to the data register or the FIFO + * register. This function calls callback function when it meets conditions below. + * - UART_EVENT_RX_COMPLETE: The number of data which has been read reaches to the number specified in R_SCI_B_UART_Read() + * if a transfer instance is used for reception. + * - UART_EVENT_RX_CHAR: Data is received asynchronously (read has not been called) + * + * This interrupt also calls the callback function for RTS pin control if it is registered in R_SCI_B_UART_Open(). This is + * special functionality to expand SCI hardware capability and make RTS/CTS hardware flow control possible. If macro + * 'SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT' is set, it is called at the beginning in this function to set the RTS pin high, + * then it is it is called again just before leaving this function to set the RTS pin low. + * @retval none + **********************************************************************************************************************/ +void sci_b_uart_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + #if SCI_B_UART_CFG_DTC_SUPPORTED + if ((p_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_ctrl->rx_dest_bytes)) + #endif + { + #if (SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_ctrl->flow_pin != SCI_B_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + + /* Pause the transmission of data from the other device. */ + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_B_UART_FLOW_CONTROL_ACTIVE); + } + #endif + + uint32_t data; + #if SCI_B_UART_CFG_FIFO_SUPPORT + do + { + if ((p_ctrl->fifo_depth > 0U)) + { + if (p_ctrl->p_reg->FRSR_b.R > 0U) + { + if (2U == p_ctrl->data_bytes) + { + data = p_ctrl->p_reg->RDR & R_SCI_B0_RDR_RDAT_Msk; + } + else + { + data = p_ctrl->p_reg->RDR_BY; + } + } + else + { + break; + } + } + else if (2U == p_ctrl->data_bytes) + #else + { + if (2U == p_ctrl->data_bytes) + #endif + { + data = p_ctrl->p_reg->RDR & R_SCI_B0_RDR_RDAT_Msk; + } + else + { + data = p_ctrl->p_reg->RDR_BY; + } + + if (0 == p_ctrl->rx_dest_bytes) + { + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call user callback with the data. */ + r_sci_b_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR); + } + } + else + { + memcpy((void *) p_ctrl->p_rx_dest, &data, p_ctrl->data_bytes); + p_ctrl->p_rx_dest += p_ctrl->data_bytes; + p_ctrl->rx_dest_bytes -= p_ctrl->data_bytes; + + if (0 == p_ctrl->rx_dest_bytes) + { + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + r_sci_b_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + } + + #if SCI_B_UART_CFG_FIFO_SUPPORT + } while ((p_ctrl->fifo_depth > 0U) && ((p_ctrl->p_reg->FRSR_b.R) > 0U)); + + if (p_ctrl->fifo_depth > 0U) + { + p_ctrl->p_reg->CFCLR |= SCI_B_UART_CFCLR_RDRFC_MASK; + } + + #else + } + #endif + #if (SCI_B_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_ctrl->flow_pin != SCI_B_UART_INVALID_16BIT_PARAM) + { + /* Resume the transmission of data from the other device. */ + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_B_UART_FLOW_CONTROL_INACTIVE); + R_BSP_PinAccessDisable(); + } + #endif + } + + #if SCI_B_UART_CFG_DTC_SUPPORTED + else + { + p_ctrl->rx_dest_bytes = 0; + + p_ctrl->p_rx_dest = NULL; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call callback */ + r_sci_b_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + #endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_B_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TEI interrupt processing for UART mode. The TEI interrupt fires after the last byte is transmitted on the TX pin. + * The user callback function is called with the UART_EVENT_TX_COMPLETE event code (if it is registered in + * R_SCI_B_UART_Open()). + **********************************************************************************************************************/ +void sci_b_uart_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk | R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */ + r_sci_b_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_B_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * ERI interrupt processing for UART mode. When an ERI interrupt fires, the user callback function is called if it is + * registered in R_SCI_B_UART_Open() with the event code that triggered the interrupt. + **********************************************************************************************************************/ +void sci_b_uart_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_b_uart_instance_ctrl_t * p_ctrl = (sci_b_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t data = 0U; + + /* Read data. */ + if (2U == p_ctrl->data_bytes) + { + data = p_ctrl->p_reg->RDR & R_SCI_B0_RDR_RDAT_Msk; + } + else + { + data = p_ctrl->p_reg->RDR_BY; + } + + /* Determine cause of error. */ + uint32_t csr = p_ctrl->p_reg->CSR; + uart_event_t event = (uart_event_t) ((((csr & R_SCI_B0_CSR_ORER_Msk) == R_SCI_B0_CSR_ORER_Msk) << 5U) | + (((csr & R_SCI_B0_CSR_FER_Msk) == R_SCI_B0_CSR_FER_Msk) << 4U) | + (((csr & R_SCI_B0_CSR_PER_Msk) == R_SCI_B0_CSR_PER_Msk) << 3U)); + + /* Check if there is a break detected. */ + if ((UART_EVENT_ERR_FRAMING == (event & UART_EVENT_ERR_FRAMING)) && (0U == p_ctrl->p_reg->CSR_b.RXDMON)) + { + event |= UART_EVENT_BREAK_DETECT; + } + + /* Clear error condition. */ + p_ctrl->p_reg->CFCLR |= SCI_B_UART_RCVR_ERR_MASK; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call callback. */ + r_sci_b_uart_call_callback(p_ctrl, data, event); + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_i2c/r_sci_i2c.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_i2c/r_sci_i2c.c new file mode 100644 index 0000000000..f0f0c7f3d4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_i2c/r_sci_i2c.c @@ -0,0 +1,1353 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_sci_i2c.h" + +#if SCI_I2C_CFG_DTC_ENABLE + #include "r_dtc.h" +#endif + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "SI2C" in ASCII, used to determine if channel is open. */ +#define SCI_I2C_OPEN (0x53493243ULL) + +#define SCI_I2C_PRV_CODE_READ (0x01U) +#define SCI_I2C_PRV_CODE_10BIT (0xF0U) + +#define SCI_I2C_PRV_SLAVE_10_BIT_ADDR_LEN_ADJUST (2U) + +#define SCI_I2C_PRV_SMR_CKS_VALUE_MASK (0x03U) ///< CKS: 2 bits + +#define SCI_I2C_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#define SCI_I2C_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#define SCI_I2C_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << \ + TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << \ + TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << \ + TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << \ + TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << \ + TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SCI_I2C_PRV_SIMR3_STARTREQ (0x51U) +#define SCI_I2C_PRV_SIMR3_RESTARTREQ (0x52U) +#define SCI_I2C_PRV_SIMR3_STOPREQ (0x54U) +#define SCI_I2C_PRV_SIMR3_CLEARREQ (0x00U) +#define SCI_I2C_PRV_SIMR3_HALTPREQ (0xF0U) + +#define SCI_I2C_PRV_MDDR_REG_MIN (0x80) + +/* SCI SCR register bit masks */ +#define SCI_I2C_PRV_SCR_TE_RE_MASK (0x30U) +#define SCI_I2C_PRV_SCR_TIE_TE_RE_TEIE_ENABLE_MASK (0xB4) +#define SCI_I2C_PRV_SCR_TIE_RIE_TE_RE_TEIE_ENABLE_MASK (0xF4) + +#define SCI_I2C_PRV_SIMR1_REG_MODE_I2C (0x1U) +#define SCI_I2C_PRV_SCMR_REG_INIT (0xFAU) +#define SCI_I2C_PRV_SIMR2_REG_SETTING_MASK (0x23U) +#define SCI_I2C_PRV_SIMR2_REG_INTERRUPT_SOURCE_ACK_NACK_SETTING_MASK (0x22U) +#define SCI_I2C_PRV_SIMR2_REG_SETTING_NACK_TRANSMISSION_MASK (0x20U) + +#define SCI_I2C_PRV_DUMMY_WRITE_DATA_FOR_READ_OP (0xFFU) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* I2C read/write enumeration */ +typedef enum e_sci_i2c_transfer_dir_option +{ + SCI_I2C_TRANSFER_DIR_WRITE = 0x0, + SCI_I2C_TRANSFER_DIR_READ = 0x1 +} sci_i2c_transfer_dir_t; + +/* DTC TXI/RXI enumeration */ +typedef enum e_sci_i2c_dtc_interrupt_trigger +{ + SCI_I2C_DTC_INTERRUPT_TRIGGER_TXI = 0x0, + SCI_I2C_DTC_INTERRUPT_TRIGGER_RXI = 0x1 +} sci_i2c_dtc_interrupt_trigger_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * sci_i2c_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_i2c_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#endif + +/********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/* Internal helper functions */ +void sci_i2c_notify(sci_i2c_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event); +static void sci_i2c_abort_seq_master(sci_i2c_instance_ctrl_t * const p_ctrl); + +static fsp_err_t sci_i2c_read_write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + sci_i2c_transfer_dir_t direction); + +/* Functions that manipulate hardware */ +static void sci_i2c_open_hw_master(sci_i2c_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg); +static void sci_i2c_run_hw_master(sci_i2c_instance_ctrl_t * const p_ctrl); + +void sci_i2c_txi_isr(void); +void sci_i2c_tei_isr(void); + +static void sci_i2c_txi_send_data(sci_i2c_instance_ctrl_t * const p_ctrl); +static void sci_i2c_tei_send_address(sci_i2c_instance_ctrl_t * const p_ctrl); + +static void sci_i2c_tei_handler(sci_i2c_instance_ctrl_t * const p_ctrl); +static void sci_i2c_txi_handler(sci_i2c_instance_ctrl_t * const p_ctrl); +static void sci_i2c_txi_process_nack(sci_i2c_instance_ctrl_t * const p_ctrl); +static void sci_i2c_issue_restart_or_stop(sci_i2c_instance_ctrl_t * const p_ctrl); + +#if SCI_I2C_CFG_DTC_ENABLE +void sci_i2c_rxi_isr(void); +static fsp_err_t sci_i2c_transfer_open(sci_i2c_instance_ctrl_t * p_ctrl, i2c_master_cfg_t const * const p_cfg); +static fsp_err_t sci_i2c_transfer_configure(sci_i2c_instance_ctrl_t * p_ctrl, + transfer_instance_t const * p_transfer, + sci_i2c_dtc_interrupt_trigger_t trigger); +static void sci_i2c_reconfigure_interrupts_for_transfer(sci_i2c_instance_ctrl_t * const p_ctrl); +static void sci_i2c_enable_transfer_support_tx(sci_i2c_instance_ctrl_t * const p_ctrl); + +#endif + +/********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* constant used as the source location for the DTC dummy write */ +static const uint8_t g_dummy_write_data_for_read_op = SCI_I2C_PRV_DUMMY_WRITE_DATA_FOR_READ_OP; + +/********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* Simple I2C on SCI HAL API mapping for I2C Master interface */ +i2c_master_api_t const g_i2c_master_on_sci = +{ + .open = R_SCI_I2C_Open, + .read = R_SCI_I2C_Read, + .write = R_SCI_I2C_Write, + .abort = R_SCI_I2C_Abort, + .slaveAddressSet = R_SCI_I2C_SlaveAddressSet, + .close = R_SCI_I2C_Close, + .callbackSet = R_SCI_I2C_CallbackSet, + .statusGet = R_SCI_I2C_StatusGet +}; + +/*******************************************************************************************************************//** + * @addtogroup SCI_I2C + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Opens the I2C device. + * + * @retval FSP_SUCCESS Requested clock rate was set exactly. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel is not available on this MCU. + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. p_api_ctrl or p_cfg is NULL. + * 2. extended parameter is NULL. + * 3. Callback parameter is NULL. + * 4. Clock rate requested is greater than 400KHz + * 5. Invalid IRQ number assigned + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) p_api_ctrl; +#if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_cfg != NULL); + FSP_ASSERT(p_cfg->p_extend != NULL); + FSP_ASSERT((p_cfg->rate == I2C_MASTER_RATE_STANDARD) || (p_cfg->rate == I2C_MASTER_RATE_FAST)); + FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); + FSP_ERROR_RETURN(SCI_I2C_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN((p_cfg->channel < 8 * sizeof(unsigned int)) && + (BSP_FEATURE_SCI_CHANNELS_MASK & (1U << p_cfg->channel)), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + sci_i2c_extended_cfg_t * pextend = (sci_i2c_extended_cfg_t *) p_cfg->p_extend; + if (true == pextend->clock_settings.bitrate_modulation) + { + FSP_ASSERT(pextend->clock_settings.mddr_value >= SCI_I2C_PRV_MDDR_REG_MIN); + } + + #if SCI_I2C_CFG_DTC_ENABLE + if (NULL != p_cfg->p_transfer_rx) + { + FSP_ASSERT(p_cfg->rxi_irq >= (IRQn_Type) 0); + FSP_ASSERT(p_cfg->p_transfer_tx != NULL); + } + #endif +#endif +#if SCI_I2C_CFG_DTC_ENABLE + fsp_err_t err = FSP_SUCCESS; +#endif + + p_ctrl->p_reg = (R_SCI0_Type *) ((uint32_t) R_SCI0 + (p_cfg->channel * ((uint32_t) R_SCI1 - (uint32_t) R_SCI0)));; + + /* Record the configuration on the device for use later */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->slave = p_cfg->slave; + p_ctrl->addr_mode = p_cfg->addr_mode; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + +#if SCI_I2C_CFG_DTC_ENABLE + + /* Open transfer interfaces if available + * In case of Read operations both p_transfer_tx and p_transfer_rx are used. + * p_transfer_tx writes 0xFF to the TDR and p_transfer_rx reads from the RDR. + * If p_transfer_tx is set to NULL, 0xFF would be written to TDR using the CPU + * and the p_transfer_rx will be used to read the RDR. + * Such a configuration will make the read operation CPU dependent and there would be + * no benefit to use DRC on p_transfer_rx only. + * + * In case of Write operation p_transfer_tx is used to write to the TDR. + */ + err = sci_i2c_transfer_open(p_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + + /* Open the hardware in master mode */ + sci_i2c_open_hw_master(p_ctrl, p_cfg); + + p_ctrl->p_buff = NULL; + p_ctrl->total = 0U; + p_ctrl->remain = 0U; + p_ctrl->loaded = 0U; + p_ctrl->read = false; + p_ctrl->restart = false; + p_ctrl->err = false; + p_ctrl->restarted = false; + p_ctrl->open = SCI_I2C_OPEN; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Performs a read from the I2C device. + * The caller will be notified when the operation has completed (successfully) by an + * I2C_MASTER_EVENT_RX_COMPLETE in the callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl, p_dest is NULL, bytes is 0. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than uint16_t size (65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_NOT_OPEN Device was not even opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_Read (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart) +{ +#if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); + FSP_ASSERT(bytes != 0U); +#endif + fsp_err_t err = FSP_SUCCESS; + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of iic_master_read_write to 4. */ + ((sci_i2c_instance_ctrl_t *) p_api_ctrl)->restart = restart; + + /* Call the common helper function to perform I2C Read operation.*/ + err = sci_i2c_read_write(p_api_ctrl, p_dest, bytes, SCI_I2C_TRANSFER_DIR_READ); + + return err; +} + +/******************************************************************************************************************//** + * Performs a write to the I2C device. + * + * This function will fail if there is already an in-progress I2C transfer on the associated channel. Otherwise, the + * I2C write operation will begin. When no callback is provided by the user, this function performs a blocking write. + * Otherwise, the write operation is non-blocking and the caller will be notified when the operation has finished by + * an I2C_EVENT_TX_COMPLETE in the callback. + * + * @retval FSP_SUCCESS Function executed without issue. + * @retval FSP_ERR_ASSERTION p_ctrl, p_src is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than uint16_t size (65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_NOT_OPEN Device was not even opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_Write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart) +{ +#if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl != NULL); +#endif + fsp_err_t err = FSP_SUCCESS; + + /* Record the restart information about this transfer. + * This is done here to keep the parameter (argument) list of iic_master_read_write to 4. */ + ((sci_i2c_instance_ctrl_t *) p_api_ctrl)->restart = restart; + + /* Call the common helper function to perform I2C Write operation.*/ + err = sci_i2c_read_write(p_api_ctrl, p_src, bytes, SCI_I2C_TRANSFER_DIR_WRITE); + + return err; +} + +/******************************************************************************************************************//** + * Aborts any in-progress transfer and forces the I2C peripheral into a ready state. + * + * This function will safely terminate any in-progress I2C transfer with the device. If a transfer is aborted, the user + * will be notified via callback with an abort event. Since the callback is optional, this function will also return + * a specific error code in this situation. + * + * @retval FSP_SUCCESS Transaction was aborted without issue. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Device was not even opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_Abort (i2c_master_ctrl_t * const p_api_ctrl) +{ + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) p_api_ctrl; +#if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(SCI_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Abort any transfer happening on the channel */ + sci_i2c_abort_seq_master(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets address and addressing mode of the slave device. + * + * This function is used to set the device address and addressing mode of the slave without reconfiguring the entire bus. + * + * @retval FSP_SUCCESS Address of the slave is set correctly. + * @retval FSP_ERR_ASSERTION p_ctrl or address is NULL. + * @retval FSP_ERR_NOT_OPEN Device was not even opened. + * @retval FSP_ERR_IN_USE An I2C Transaction is in progress. + * + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode) +{ + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(SCI_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Fail if there is already a transfer in progress */ + FSP_ERROR_RETURN(((0 == p_ctrl->remain) && (false == p_ctrl->restarted)), FSP_ERR_IN_USE); +#endif + + /* Sets the address of the slave device */ + p_ctrl->slave = slave; + + /* Sets the mode of addressing */ + p_ctrl->addr_mode = addr_mode; + + return err; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2c_master_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void * const p_context, + i2c_master_callback_args_t * const p_callback_memory) +{ + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_I2C_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2c_master_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2c_master_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides driver status. + * + * @retval FSP_SUCCESS Status stored in p_status. + * @retval FSP_ERR_ASSERTION NULL pointer. + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_StatusGet (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status) +{ + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ASSERT(p_status != NULL); +#endif + + p_status->open = (SCI_I2C_OPEN == p_ctrl->open); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Closes the I2C device. Power down I2C peripheral. + * + * This function will safely terminate any in-progress I2C transfer with the device. If a transfer is aborted, the user + * will be notified via callback with an abort event. Since the callback is optional, this function will also return + * a specific error code in this situation. + * + * @retval FSP_SUCCESS Device closed without issue. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Device was not even opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_Close (i2c_master_ctrl_t * const p_api_ctrl) +{ + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl != NULL); + FSP_ERROR_RETURN(SCI_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disables all interrupts */ + p_ctrl->p_reg->SCR = 0U; + + /* Abort an in-progress transfer with this device only */ + sci_i2c_abort_seq_master(p_ctrl); + + /* The device is now considered closed */ + p_ctrl->open = 0U; + +#if SCI_I2C_CFG_DTC_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * @} (end defgroup SCI_I2C) + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Helper function for handling I2C Read or Write. + * + * @param p_api_ctrl Pointer to control block + * @param p_buffer Pointer to the buffer to store read/write data. + * @param[in] bytes Number of bytes to be read/written. + * @param[in] direction Read or Write + * + * @retval FSP_SUCCESS Function executed successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl or p_buffer is NULL. + * @retval FSP_ERR_INVALID_SIZE Provided number of bytes more than UINT16_MAX(= 65535) while DTC is used + * for data transfer. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_IIC_MASTER_Open to initialize the control block. + **********************************************************************************************************************/ +static fsp_err_t sci_i2c_read_write (i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_buffer, + uint32_t const bytes, + sci_i2c_transfer_dir_t direction) +{ + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) p_api_ctrl; + +#if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_buffer != NULL); + FSP_ERROR_RETURN((p_ctrl->open == SCI_I2C_OPEN), FSP_ERR_NOT_OPEN); + FSP_ASSERT(((sci_i2c_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); + + #if SCI_I2C_CFG_DTC_ENABLE + + /* DTC on RX could actually receive 65535+3 = 65538 bytes as 3 bytes are handled separately. + * Forcing to 65535 to keep TX and RX uniform with respect to max transaction length via DTC. + */ + FSP_ERROR_RETURN((bytes <= UINT16_MAX), FSP_ERR_INVALID_SIZE); + #endif +#endif + + p_ctrl->p_buff = p_buffer; + p_ctrl->total = bytes; + + /* Handle the (different) addressing mode(s) */ + if (p_ctrl->addr_mode == I2C_MASTER_ADDR_MODE_7BIT) + { + /* Set the address bytes according to a 7-bit slave read command */ + p_ctrl->addr_high = 0U; + p_ctrl->addr_low = (uint8_t) ((p_ctrl->slave << 1U) | (uint8_t) direction); + p_ctrl->addr_total = 1U; + } + +#if SCI_I2C_CFG_ADDR_MODE_10_BIT_ENABLE + else + { + /* Set the address bytes according to a 10-bit slave read command */ + p_ctrl->addr_high = + (uint8_t) (((p_ctrl->slave >> 7U) | SCI_I2C_PRV_CODE_10BIT) & (uint8_t) ~(SCI_I2C_PRV_CODE_READ)); + p_ctrl->addr_low = (uint8_t) p_ctrl->slave; + + /* Addr total = 3 for Read and 2 for Write. + * See "Communication Data Format" in the IIC section of the relevant hardware manual. + */ + p_ctrl->addr_total = (uint8_t) ((uint8_t) direction + SCI_I2C_PRV_SLAVE_10_BIT_ADDR_LEN_ADJUST); + } +#endif + + p_ctrl->read = (bool) direction; + + /* Kickoff the read operation as a master */ + sci_i2c_run_hw_master(p_ctrl); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Single point for managing the logic around notifying a transfer has finished. + * + * @param[in] p_ctrl Pointer to transfer that is ending. + * @param[in] event The event code to pass to the callback. + **********************************************************************************************************************/ +void sci_i2c_notify (sci_i2c_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event) +{ + i2c_master_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2c_master_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_ctrl->p_context; + p_args->event = event; + +#if SCI_I2C_CFG_DTC_ENABLE + + /* Stop any DTC assisted transfer for tx */ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if ((NULL != p_transfer_tx) && (!p_ctrl->read)) + { + p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + } + + /* Stop any DTC assisted transfer for rx */ + const transfer_instance_t * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if ((NULL != p_transfer_rx) && (p_ctrl->read)) + { + p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); + } +#endif + + /* Now do the callback here */ +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_i2c_prv_ns_callback p_callback = (sci_i2c_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/******************************************************************************************************************//** + * Single point for managing the logic around aborting a transfer when operating as a master. + * + * @param[in] p_ctrl Pointer to control struct of specific device + **********************************************************************************************************************/ +static void sci_i2c_abort_seq_master (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + /* Safely stop the hardware from operating */ + /* Disable channel interrupts */ + p_ctrl->p_reg->SCR = 0U; + + /* Clear I2C mode register command issuing flag and sets SDA/SCL to high-impedance state */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_HALTPREQ; + + /* Update the transfer descriptor to show no longer in-progress and an error */ + p_ctrl->remain = 0U; + p_ctrl->restarted = false; + p_ctrl->restart = false; + + /* Update the transfer descriptor to make sure interrupts no longer process */ + p_ctrl->addr_loaded = p_ctrl->addr_total; + p_ctrl->loaded = p_ctrl->total; +} + +/******************************************************************************************************************//** + * Performs the hardware initialization sequence when operating as a master. + * + * @param[in] p_ctrl Pointer to control structure + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS Hardware initialized with proper configurations + * @retval FSP_ERR_INVALID_RATE The requested rate cannot be set. + **********************************************************************************************************************/ +static void sci_i2c_open_hw_master (sci_i2c_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + sci_i2c_extended_cfg_t * pextend = (sci_i2c_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Refer flow diagram of master I2C initialization as described in hardware manual (see + * "Example flow of SCI initialization in simple IIC mode" + * in the SCI section of the relevant hardware manual). */ + + /* Perform the first part of the initialization sequence */ + p_ctrl->p_reg->SCR = 0U; + + /* Drive SDAn and SCLn pin to high-impedance state */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_HALTPREQ; + + p_ctrl->p_reg->SMR = (uint8_t) (SCI_I2C_PRV_SMR_CKS_VALUE_MASK & pextend->clock_settings.clk_divisor_value); + p_ctrl->p_reg->SCMR = SCI_I2C_PRV_SCMR_REG_INIT; + + /* Set the bit rate register in the hardware */ + /* Setting the BRR bits for the baud rate register */ + p_ctrl->p_reg->BRR = pextend->clock_settings.brr_value; + + /*1. Enable or Disable bit-rate modulation function + * 2. Enable noise filter */ + p_ctrl->p_reg->SEMR = + (uint8_t) ((uint8_t) ((uint8_t) (pextend->clock_settings.bitrate_modulation) << R_SCI0_SEMR_BRME_Pos) | + (uint8_t) R_SCI0_SEMR_NFEN_Msk); + + p_ctrl->p_reg->SNFR = pextend->clock_settings.snfr_value; + + p_ctrl->p_reg->MDDR = pextend->clock_settings.mddr_value; + + /* 1. Set SDA Output Delay + * 2. Set this SCI channel to operate in simple I2C mode + */ + p_ctrl->p_reg->SIMR1 = + (uint8_t) ((uint8_t) ((pextend->clock_settings.cycles_value & 0x1F) << R_SCI0_SIMR1_IICDL_Pos) | + (uint8_t) SCI_I2C_PRV_SIMR1_REG_MODE_I2C); + + /* 1. Enable clock synchronization + * 2. NACK transmission and ACK/NACK reception + * 3. Select Interrupt Source Transmission/.Reception interrupt */ + p_ctrl->p_reg->SIMR2 = SCI_I2C_PRV_SIMR2_REG_SETTING_MASK; + + /* Clear SPI Mode register (SPMR) */ + p_ctrl->p_reg->SPMR = 0U; + + R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->tei_irq, p_cfg->ipl, p_ctrl); +#if SCI_I2C_CFG_DTC_ENABLE + if (p_cfg->rxi_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->ipl, p_ctrl); + } +#endif + + /* Step #7 of writing to the SCR is done under helper function sci_i2c_run_hw_master */ +} + +/******************************************************************************************************************//** + * Performs the data transfer described by the parameters when operating as a master. + * + * @param[in] p_ctrl Pointer to Control structure of specific device. + * + * @retval FSP_SUCCESS Data transferred when operating as a master. + * @retval FSP_ERR_ABORTED If there is an in-progress transfer. + **********************************************************************************************************************/ +static void sci_i2c_run_hw_master (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + /* Initialize fields used during transfer */ + p_ctrl->addr_loaded = 0U; + p_ctrl->loaded = 0U; + p_ctrl->remain = p_ctrl->total; + p_ctrl->addr_remain = p_ctrl->addr_total; + p_ctrl->err = false; + p_ctrl->do_dummy_read = false; + p_ctrl->activation_on_txi = false; + + /* In case of read operation the first ACK detected on the bus is from the slave after the address is sent. + * Since we are reading on every ACK detection on the bus [in this case from this driver], + * we skip the first read corresponding to the address. + */ + if (true == p_ctrl->read) + { + p_ctrl->do_dummy_read = true; + } + + /* Re-enable TXI and TEIE. Keep TE and RE enabled. */ + p_ctrl->p_reg->SCR = SCI_I2C_PRV_SCR_TIE_TE_RE_TEIE_ENABLE_MASK; +#if SCI_I2C_CFG_DTC_ENABLE + sci_i2c_reconfigure_interrupts_for_transfer(p_ctrl); +#endif + + /* Check if this is a new transaction or a continuation */ + if (!p_ctrl->restarted) + { + /* Set the I2C into master mode and start interrupt processing */ + /* The IICRSTARREQ, IICSDAS, IICSCLS bits must be set simultaneously */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_STARTREQ; + } + else + { + /* Clear for next transfer */ + p_ctrl->restarted = false; + +#if SCI_I2C_CFG_DTC_ENABLE + + /* Enable transfer support for tx if this is the last address byte */ + if (1U == p_ctrl->addr_total) + { + sci_i2c_enable_transfer_support_tx(p_ctrl); + } +#endif + + /* Send MSB or LSB based on the addressing mode */ + /* Write 1 byte data to data register */ + p_ctrl->p_reg->TDR = (1U == p_ctrl->addr_total) ? (p_ctrl->addr_low) : (p_ctrl->addr_high); + + /* Update the trackers */ + p_ctrl->addr_remain--; + p_ctrl->addr_loaded++; + } +} + +/******************************************************************************************************************//** + * ISR for ACK/RXI interrupt + * + **********************************************************************************************************************/ +#if SCI_I2C_CFG_DTC_ENABLE +void sci_i2c_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* This interrupt is invoked once DTC supported Read transfer is completed. Nothing to be done here. */ + + /* Clear pending IRQ */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +/******************************************************************************************************************//** + * ISR for NACK/TXI interrupt + * + **********************************************************************************************************************/ +void sci_i2c_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Clear pending IRQ */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Call the handler */ + sci_i2c_txi_handler(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * Handles the STI interrupt + * + *********************************************************************************************************************/ +void sci_i2c_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Call the handler */ + sci_i2c_tei_handler(p_ctrl); + + /* Clear pending IRQ */ + R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * Handles the NACK/TXI interrupt . + * + * @param[in] p_ctrl pointer to the I2C control block. + **********************************************************************************************************************/ + +static void sci_i2c_txi_handler (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + /* Check if ACK is detected */ + if (0U == p_ctrl->p_reg->SISR_b.IICACKR) + { + /* 10 bit address, transfer the remaining address or generate RESTART */ + if (p_ctrl->addr_total != p_ctrl->addr_loaded) + { + /* Issue a RESTART as this is 10 bit address read and we have already transmitted the LSB */ + if ((p_ctrl->read) && (2U == p_ctrl->addr_loaded)) + { + /* The IICRSTARREQ, IICSDAS, IICSCLS bits must be set simultaneously */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_RESTARTREQ; + } + /* Transmit the LSB of the address */ + else + { +#if SCI_I2C_CFG_DTC_ENABLE + sci_i2c_enable_transfer_support_tx(p_ctrl); +#endif + + /* Write 1byte p_ctrl->addr_low to p_ctrl->addr_low register */ + p_ctrl->p_reg->TDR = p_ctrl->addr_low; + + /* Update tracker that we have completed an address byte */ + p_ctrl->addr_remain--; + p_ctrl->addr_loaded++; + } + } + +#if SCI_I2C_CFG_DTC_ENABLE + + /* This is the first interrupt after the completion of DTC operation, ignore it */ + else if (true == p_ctrl->activation_on_txi) + { + p_ctrl->activation_on_txi = false; + } +#endif + + /* Transmit/Receive data */ + else if (0U < p_ctrl->remain) + { + sci_i2c_txi_send_data(p_ctrl); + } + /* All transfers complete, send the required bus condition */ + else + { + sci_i2c_issue_restart_or_stop(p_ctrl); + } + } + /* NACK detected: Either a NACK interrupt or TXI interrupt with NACK flag set */ + else + { + sci_i2c_txi_process_nack(p_ctrl); + } +} + +/******************************************************************************************************************//** + * Handles the START/STOP interrupt . + * + * @param[in] p_ctrl pointer to the I2C control block. + **********************************************************************************************************************/ +static void sci_i2c_tei_handler (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + /* Clear the interrupt flag */ + /* Clear the interrupt STI flag */ + p_ctrl->p_reg->SIMR3_b.IICSTIF = 0U; + + if (p_ctrl->err) + { + /* Release SCL and SDA lines */ + /* Clear I2C mode register command issuing flag and sets SDA/SCL to high-impedance state */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_HALTPREQ; + + /* Notify the user of the error */ + sci_i2c_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED); + } + /* Address transmission is not complete, this could be the START condition prior to the transmission + * of first address byte or RESTART condition in between a 10 bit address read */ + else if (p_ctrl->addr_total != p_ctrl->addr_loaded) + { + /* Check to send address */ + sci_i2c_tei_send_address(p_ctrl); + } + /*This a STOP or RESTART after completion of the read/write operation */ + else if (0U == p_ctrl->remain) + { + i2c_master_event_t event = p_ctrl->read ? I2C_MASTER_EVENT_RX_COMPLETE : I2C_MASTER_EVENT_TX_COMPLETE; + + /* Set the SCL/SDA lines to the required state */ + if (p_ctrl->restarted) + { + /* Ready for transfer */ + /* Clear I2C mode register command issuing flag and enable SDA/SCL for serial data output mode */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_CLEARREQ; + } + else + { + /* Release SCL and SDA lines */ + /* Clear I2C mode register command issuing flag and sets SDA/SCL to high-impedance state */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_HALTPREQ; + + /* Disable the transmitter and receiver */ + p_ctrl->p_reg->SCR &= (uint8_t) (~SCI_I2C_PRV_SCR_TE_RE_MASK); + } + + /* Notify anyone waiting that the transfer is finished */ + sci_i2c_notify(p_ctrl, event); + } + else + { + /*Do nothing*/ + } +} + +#if SCI_I2C_CFG_DTC_ENABLE + +/*******************************************************************************************************************//** + * Configures SCI I2C related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to SCI I2C specific control structure + * @param[in] p_cfg Pointer to SCI I2C specific configuration structure + * + * @retval FSP_SUCCESS If configures SCI I2C related transfer drivers + * @retval FSP_ERR_ASSERTION Transfer configuration for tx/rx not proper. + **********************************************************************************************************************/ +static fsp_err_t sci_i2c_transfer_open (sci_i2c_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + if (NULL != p_cfg->p_transfer_rx) + { + err = sci_i2c_transfer_configure(p_ctrl, p_cfg->p_transfer_rx, SCI_I2C_DTC_INTERRUPT_TRIGGER_RXI); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (NULL != p_cfg->p_transfer_tx) + { + err = sci_i2c_transfer_configure(p_ctrl, p_cfg->p_transfer_tx, SCI_I2C_DTC_INTERRUPT_TRIGGER_TXI); + if (FSP_SUCCESS != err) + { + if (NULL != p_cfg->p_transfer_rx) + { + err = p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + + return err; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures DTC + * @param[in] p_ctrl Pointer to I2C specific control structure + * @param[in] p_transfer Pointer to DTC instance structure + * @param[in] trigger TXI or RXI to be set as trigger + * + * @retval FSP_SUCCESS Transfer interface is configured with valid parameters. + * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL. + **********************************************************************************************************************/ +static fsp_err_t sci_i2c_transfer_configure (sci_i2c_instance_ctrl_t * p_ctrl, + transfer_instance_t const * p_transfer, + sci_i2c_dtc_interrupt_trigger_t trigger) +{ + fsp_err_t err; + + /* Set default transfer info and open receive transfer module, if enabled. */ + #if (SCI_I2C_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_ctrl); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + #endif + transfer_info_t * p_cfg = p_transfer->p_cfg->p_info; + if (SCI_I2C_DTC_INTERRUPT_TRIGGER_RXI == trigger) + { + p_cfg->transfer_settings_word = SCI_I2C_PRV_DTC_RX_FOR_READ_TRANSFER_SETTINGS; + p_cfg->p_src = (void *) (&(p_ctrl->p_reg->RDR)); + } + else + { + /* In case of read operation using DTC, the TXI interrupt will trigger the DTC to write 0xFF into TDR. */ + + /* Refer flow diagram of master reception as described in hardware manual (see Figure + * "Example flow of master reception in simple IIC mode with transmission interrupts and reception interrupts" + * in the SCI section of the relevant hardware manual). */ + + /* In case of Write operation this will be reconfigured */ + p_cfg->transfer_settings_word = SCI_I2C_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS; + p_cfg->p_dest = (void *) (&(p_ctrl->p_reg->TDR)); + } + + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Reconfigure the address mode for transfer interface + * + * @param[in] p_ctrl transfer control block + * + * @retval FSP_SUCCESS Address mode for transfer interface reconfigured. + **********************************************************************************************************************/ +static void sci_i2c_reconfigure_interrupts_for_transfer (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + + if (NULL != p_transfer_tx) + { + transfer_info_t * p_info = p_transfer_tx->p_cfg->p_info; + + /* Disable the transmitter and receiver for reconfiguring interrupt source */ + p_ctrl->p_reg->SCR = 0; + if (p_ctrl->read) + { + /* Re-adjust address modes */ + p_info->transfer_settings_word = SCI_I2C_PRV_DTC_TX_FOR_READ_TRANSFER_SETTINGS; + p_info->p_src = (void *) &g_dummy_write_data_for_read_op; + } + else /* This is a write operation */ + { + /* Re-adjust address modes */ + p_info->transfer_settings_word = SCI_I2C_PRV_DTC_TX_FOR_WRITE_TRANSFER_SETTINGS; + } + + /* Set the interrupt source to RXI/TXI */ + p_ctrl->p_reg->SIMR2 = SCI_I2C_PRV_SIMR2_REG_SETTING_MASK; + p_ctrl->p_reg->SCR = SCI_I2C_PRV_SCR_TIE_TE_RE_TEIE_ENABLE_MASK; + } +} + +/*******************************************************************************************************************//** + * Enables the dtc transfer interface for the transmit operation + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void sci_i2c_enable_transfer_support_tx (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + + if ((NULL != p_transfer_tx) && (!p_ctrl->read)) + { + /* Enable transfer interface to write to TDR + * Re-configures the source buffer to the user buffer as this is a Write operation. + */ + p_transfer_tx->p_api->reset(p_transfer_tx->p_ctrl, (void *) (p_ctrl->p_buff), NULL, + (uint16_t) (p_ctrl->remain)); + + p_ctrl->remain = 0U; + p_ctrl->loaded = p_ctrl->total; + + p_ctrl->activation_on_txi = true; + } +} + +#endif + +/*******************************************************************************************************************//** + * Check for the receive condition. + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void sci_i2c_txi_send_data (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + /* As per the hardware manual, a byte should be written to TDR to generate SCL. + * If we are doing an I2C read, we will write 0xFF to the TDR */ + uint8_t data = g_dummy_write_data_for_read_op; + + /* This is a write operation, update the data byte from user buffer */ + if (!p_ctrl->read) + { + data = p_ctrl->p_buff[p_ctrl->loaded]; + + /* Update trackers */ + p_ctrl->remain--; + p_ctrl->loaded++; + } + /* This is a read operation, move data from RDR and do dummy write to TDR + * Since SIMR2.IICINTM bit is 1, this interrupt is generated from an ACK bit sent by master as a + * response to the read data from the slave. + * Since the ACK is sent, RDR is safe to read out from. + * + * In case SIMR2.IICINTM bit is 0, we do the dummy read here and set the DTC module to perform the read operation. + */ + else + { + /* Skip updating the buffer on first interrupt as it is the ACK of address */ + if (true == p_ctrl->do_dummy_read) + { + p_ctrl->do_dummy_read = false; +#if SCI_I2C_CFG_DTC_ENABLE + + /* If transfer interface is available, use it. + * Enable the transfer interfaces if the number of bytes to be read is greater than 2. + * The last two bytes will be read through interrupt, this is for support NACK before STOP. + */ + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && (NULL != p_ctrl->p_cfg->p_transfer_rx) && + (p_ctrl->total > 2U)) + { + /* Enable RXI interrupt */ + p_ctrl->p_reg->SCR = SCI_I2C_PRV_SCR_TIE_RIE_TE_RE_TEIE_ENABLE_MASK; + + /* Enable transfer interface for reading data from RDR */ + p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, NULL, + (void *) (p_ctrl->p_buff), (uint16_t) (p_ctrl->total - 2U)); + + /* Enable transfer interface to do dummy write into TDR */ + p_ctrl->p_cfg->p_transfer_tx->p_api->reset(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + NULL, + NULL, + (uint16_t) (p_ctrl->total - 2U)); + + /* Update the tracker variables */ + p_ctrl->remain = 2U; + p_ctrl->loaded = p_ctrl->total - 2U; + + /* Mark DTC activation for TXI */ + p_ctrl->activation_on_txi = true; + } +#endif + + /* Writing to the SIMR2 register when TE and RE bit in SCR is not equal to 0 will only allow to update the + * IICACKT bit.(see Note 1 under Section 34.2.22 'IIC Mode Register 2 (SIMR2)' + */ + + /* If number of bytes to be received is greater than one, set ACK transmission + * NACK transmission will be set before the last byte is read. + */ + if (1U < p_ctrl->remain) + { + p_ctrl->p_reg->SIMR2 = (uint8_t) (0x0U); /* SIMR2.IICACKT = 0 */ + } + } + /* Read data into the buffer */ + else + { + p_ctrl->p_buff[p_ctrl->loaded] = p_ctrl->p_reg->RDR; + + /* Update trackers */ + p_ctrl->remain--; + p_ctrl->loaded++; + } + + /* Writing to the SIMR2 register when TE and RE bit in SCR is not equal to 0 will only allow to update the + * IICACKT bit.(see Note 1 under Section 34.2.22 'IIC Mode Register 2 (SIMR2)' + */ + + /* Enable NACK transmission prior to the reception of the last byte */ + if (1U == p_ctrl->remain) + { + p_ctrl->p_reg->SIMR2 = SCI_I2C_PRV_SIMR2_REG_SETTING_NACK_TRANSMISSION_MASK; /* SIMR2.IICACKT = 1 */ + } + } + + /* Write 1 byte data to data register. + * In case of write operation this will be data from user buffer. + * In case of read operation this will be 0xFF as required by HW. + * Refer flow diagram of master transmission and reception as described in hardware manual (see Figure + * "Example flow of master transmission in simple IIC mode with transmission interrupts and reception interrupts" + * and Figure + * "Example flow of master reception in simple IIC mode with transmission interrupts and reception interrupts" + * in the SCI section of the relevant hardware manual). + */ + p_ctrl->p_reg->TDR = data; +} + +/*******************************************************************************************************************//** + * Enables transfer support while handling the tei interrupt + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void sci_i2c_tei_send_address (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + uint8_t data = 0U; + + /* This is the first address byte */ + if (0U == p_ctrl->addr_loaded) + { +#if SCI_I2C_CFG_DTC_ENABLE + + /* Enable transfer support for tx if this is the last address byte */ + if (1U == p_ctrl->addr_total) + { + sci_i2c_enable_transfer_support_tx(p_ctrl); + } +#endif + + /* if 7 bit addressing, send LSB else send MSB of address word */ + data = (1U == p_ctrl->addr_total) ? p_ctrl->addr_low : p_ctrl->addr_high; + } + /* This is a 10 bit read operation, issue the address as per the protocol */ + else if ((p_ctrl->read) && (p_ctrl->addr_loaded == 2U)) + { + /* Write address MSB with R/W bit set to read */ + data = p_ctrl->addr_high | (uint8_t) SCI_I2C_PRV_CODE_READ; + } + /* Shouldn't have come here, do nothing */ + else + { + /* Do Nothing */ + } + + /* Clear the SDA/SCL line for data transmission */ + /* Clear I2C mode register command issuing flag and enable SDA/SCL for serial data output mode */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_CLEARREQ; + + /* Write 1 byte data to data register */ + p_ctrl->p_reg->TDR = data; + + /* Update the number of address bytes remain for next pass */ + p_ctrl->addr_remain--; + p_ctrl->addr_loaded++; +} + +/*******************************************************************************************************************//** + * Process NACK reception within TXI interrupt + * + * @param[in] p_ctrl Pointer to transfer control block + **********************************************************************************************************************/ +static void sci_i2c_txi_process_nack (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + /* If we are doing master write, or address is NACKed during read operation, this is an error condition, set error and send stop */ + if ((!p_ctrl->read) || (true == p_ctrl->do_dummy_read)) + { + p_ctrl->remain = 0U; + p_ctrl->err = true; + + /* The IICRSTARREQ, IICSDAS, IICSCLS bits must be set simultaneously */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_STOPREQ; + } + /* If we are doing master read, this marks the end of transaction, read the last byte from RDR before + * generating the required bus condition */ + else + { + /* Load the RDR into user buffer */ + p_ctrl->p_buff[p_ctrl->loaded] = p_ctrl->p_reg->RDR; + + /* Update trackers */ + p_ctrl->remain--; + p_ctrl->loaded++; + + sci_i2c_issue_restart_or_stop(p_ctrl); + } +} + +/*******************************************************************************************************************//** + * This helper function issues a Restart or a Stop condition on the channel. + * + * @param[in] p_ctrl Instance control structure. + **********************************************************************************************************************/ +static void sci_i2c_issue_restart_or_stop (sci_i2c_instance_ctrl_t * const p_ctrl) +{ + /* Send a RESTART or STOP as requested by the user */ + if (true == p_ctrl->restart) + { + /* The IICRSTARREQ, IICSDAS, IICSCLS bits must be set simultaneously */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_RESTARTREQ; + p_ctrl->restarted = true; + } + else + { + /* The IICRSTARREQ, IICSDAS, IICSCLS bits must be set simultaneously */ + p_ctrl->p_reg->SIMR3 = SCI_I2C_PRV_SIMR3_STOPREQ; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_lin/r_sci_lin.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_lin/r_sci_lin.c new file mode 100644 index 0000000000..8add9e3795 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_lin/r_sci_lin.c @@ -0,0 +1,2496 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/********************************************************************************************************************** + * Includes + *********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sci_lin.h" + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +#define SCI_LIN_FRAME_ID_MASK (0x3FU) + +/* "LIN" in ASCII. Used to determine if the control block is open. */ +#define SCI_LIN_OPEN (0x4C494EU) + +/* Max/Min value of break field length */ +#define SCI_LIN_MAX_TIMER_INTERVAL (0x10000) + +/* Range of LIN timer supported TCSS values */ +#define SCI_LIN_TCSS_MIN (SCI_LIN_TIMER_DIV_1) +#define SCI_LIN_TCSS_MAX (SCI_LIN_TIMER_DIV_128) +#define SCI_LIN_TCSS_MASK (0x07U) + +/* Max value of CKS for setting baud rate */ +#define SCI_LIN_CKS_MAX (3U) + +#define SCI_LIN_MIN_BAUD_DIVISOR_SHIFT (5) + +/* Used to validate the checksum of received data */ +#define SCI_LIN_CHECKSUM_OK (0xFFU) + +/* LIN Sync Word (Control Field 0) */ +#define SCI_LIN_SYNC (0x55U) + +/* Header data length */ +#define SCI_LIN_HEADER_NUM_BYTES (2U) + +/* SCI SCR register initial value */ +#define SCI_LIN_SCR_INITIAL_VALUE (0U) + +/* SCI CR1 register masks */ +#define SCI_LIN_CR1_MASK_SLAVE (R_SCI0_CR1_BFE_Msk | R_SCI0_CR1_CF0RE_Msk) + +/* SCI CR3 register masks */ +#define SCI_LIN_CR3_MASK_SLAVE (R_SCI0_CR3_SDST_Msk) + +/* SCI CF0DR register masks */ +#define SCI_LIN_CF0DR_MASK_SLAVE (SCI_LIN_SYNC) + +/* SCI CF0CR register masks */ +#define SCI_LIN_CF0CR_MASK_SLAVE (0xFFU) + +/* SCI SCMR register masks */ +#define SCI_LIN_SCMR_DEFAULT_VALUE (0xF2U) + +/* SCI PCR register masks */ +#define SCI_LIN_PCR_DEFAULT_VALUE (0U) + +/* SCI STCR register masks */ +#define SCI_LIN_STCR_CLEAR_MASK (R_SCI0_STCR_BFDCL_Msk | R_SCI0_STCR_CF0MCL_Msk | \ + R_SCI0_STCR_CF1MCL_Msk | R_SCI0_STCR_PIBDCL_Msk | \ + R_SCI0_STCR_BCDCL_Msk | R_SCI0_STCR_AEDCL_Msk) +#define SCI_LIN_ERROR_STCR_EVENTS_CLEAR_MASK (R_SCI0_STCR_BFDCL_Msk | R_SCI0_STCR_BCDCL_Msk | \ + R_SCI0_STCR_AEDCL_Msk) + +/* SCI SSR register masks */ +#define SCI_LIN_SSR_CLEAR_MASK (R_SCI0_SSR_PER_Msk | R_SCI0_SSR_FER_Msk | \ + R_SCI0_SSR_ORER_Msk | R_SCI0_SSR_RDRF_Msk) +#define SCI_LIN_ERROR_SSR_EVENTS_CLEAR_MASK (SCI_LIN_SSR_CLEAR_MASK) + +/* SCI ICR register masks for Slave */ +#define SCI_LIN_ICR_CONTROL_FIELD_MASK (R_SCI0_ICR_CF0MIE_Msk | R_SCI0_ICR_CF1MIE_Msk) + +/* SCI TMR register masks */ +#define SCI_LIN_TIMER_MODE (0U) +#define SCI_LIN_BREAK_FIELD_DETERMINATION_MODE (1U) +#define SCI_LIN_BREAK_FIELD_OUTPUT_MODE (2U) + +/* SCI FCR register default value */ +#define SCI_LIN_FCR_DEFAULT_VALUE (0xF800U) + +/* SCI SIMR1 register default value */ +#define SCI_LIN_SIMR1_DEFAULT_VALUE (0U) + +/* SCI SPMR register default value */ +#define SCI_LIN_SPMR_DEFAULT_VALUE (0U) + +/* SCI MDDR register default value */ +#define SCI_LIN_MDDR_DEFAULT_VALUE (0xFFU) + +/* Number of consecutive measurements used to synchronize the bit rate */ +#define SCI_LIN_SYNC_EDGES (8U) + +/* Number of bits to wait before CF1 detection */ +#define SCI_LIN_CF1_WAIT_BIT_COUNT (15U) + +/********************************************************************************************************************** + * Typedef definitions + *********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * sci_lin_prv_ns_callback)(lin_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_lin_prv_ns_callback)(lin_callback_args_t * p_args); +#endif + +/********************************************************************************************************************** + * Private function prototypes + *********************************************************************************************************************/ + +/* PID and checksum helper functions */ +static uint8_t r_sci_lin_pid_calculate(uint8_t id); + +#if SCI_LIN_CHECKSUM_SUPPORT_ENABLE +static uint8_t r_sci_lin_checksum_calculate(uint8_t id, + uint8_t const * const p_data, + uint8_t num_bytes, + lin_checksum_type_t checksum_type); +static uint8_t r_sci_lin_checksum_initialize(uint8_t id, lin_checksum_type_t checksum_type); +static uint8_t r_sci_lin_checksum_add_byte_to_sum(uint8_t byte, uint8_t current_sum); + +#endif + +/* Initialization helper functions */ +static void r_sci_lin_hw_configure(sci_lin_instance_ctrl_t * const p_ctrl); +static void r_sci_lin_irq_cfg(IRQn_Type const irq); +static void r_sci_lin_irqs_cfg(sci_lin_instance_ctrl_t * const p_ctrl); +static void r_sci_lin_irq_enable(IRQn_Type irq, uint8_t ipl, void * p_context); +static void r_sci_lin_irq_disable(IRQn_Type irq, uint8_t ipl, void * p_context); +static inline void r_sci_lin_irqs_enable_disable(sci_lin_instance_ctrl_t * const p_ctrl, + void ( * irqEnableDisableFunc)( + IRQn_Type irq, + uint8_t ipl, + void * p_context)); + +#if (SCI_LIN_CFG_PARAM_CHECKING_ENABLE) +static fsp_err_t r_sci_lin_common_parameter_checking(sci_lin_instance_ctrl_t const * const p_ctrl); +static fsp_err_t r_sci_lin_read_write_parameter_checking(sci_lin_instance_ctrl_t const * const p_ctrl, + lin_transfer_params_t const * const p_transfer_params); + +#endif + +/* Transmission/reception helper functions */ +static fsp_err_t r_sci_lin_write(sci_lin_instance_ctrl_t * const p_ctrl, + const lin_transfer_params_t * const p_transfer_params, + uint8_t const send_header); + +static void r_sci_lin_call_callback(sci_lin_instance_ctrl_t * p_ctrl, lin_event_t event); +static lin_event_t r_sci_lin_rxi_handler(sci_lin_instance_ctrl_t * const p_ctrl); +static void r_sci_lin_txi_handler(sci_lin_instance_ctrl_t * const p_ctrl); +static lin_event_t r_sci_lin_eri_handler(sci_lin_instance_ctrl_t * const p_ctrl); +static void r_sci_lin_scix0_handler(sci_lin_instance_ctrl_t * const p_ctrl); +static lin_event_t r_sci_lin_scix1_handler(sci_lin_instance_ctrl_t * const p_ctrl); + +#if SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE +static lin_event_t r_sci_lin_scix2_handler(sci_lin_instance_ctrl_t * const p_ctrl); + +#endif + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE +static void r_sci_lin_scix3_handler(sci_lin_instance_ctrl_t * const p_ctrl); +static bool r_sci_lin_scix3_latest_bit_has_error(sci_lin_instance_ctrl_t * const p_ctrl, uint32_t count); + +/* Auto Synchronization helper functions */ +static void r_sci_lin_scix3_synchronize(sci_lin_instance_ctrl_t * const p_ctrl); +static void r_sci_lin_scix3_reset(sci_lin_instance_ctrl_t * const p_ctrl); + +#endif + +/* Baud and timing helper functions */ +static fsp_err_t r_sci_lin_baud_setting_calculate(sci_lin_baud_params_t const * const p_baud_params, + sci_lin_baud_setting_t * const p_baud_setting); +static fsp_err_t r_sci_lin_timer_setting_calculate(sci_lin_baud_params_t const * const p_baud_params, + sci_lin_timer_setting_t * const p_timer_setting); +static fsp_err_t r_sci_lin_baud_and_timer_setting_calculate(sci_lin_baud_params_t const * const p_baud_params, + sci_lin_baud_setting_t * const p_baud_setting); + +static void r_sci_lin_flags_clear(R_SCI0_Type * const p_reg, uint8_t ssr, uint8_t stcr); +static void r_sci_lin_break_field_detection_reset(sci_lin_instance_ctrl_t * const p_ctrl); +static void r_sci_lin_transfer_state_reset(sci_lin_instance_ctrl_t * const p_ctrl); + +/********************************************************************************************************************** + * ISR prototypes + *********************************************************************************************************************/ +void sci_lin_rxi_isr(void); +void sci_lin_tei_isr(void); +void sci_lin_txi_isr(void); +void sci_lin_eri_isr(void); +void sci_lin_scix0_isr(void); +void sci_lin_scix1_isr(void); +void sci_lin_scix2_isr(void); +void sci_lin_scix3_isr(void); + +/********************************************************************************************************************** + * Global variables + *********************************************************************************************************************/ + +/* LIN on SCI HAL API mapping for LIN interface */ +const lin_api_t g_lin_on_sci = +{ + .open = R_SCI_LIN_Open, + .write = R_SCI_LIN_Write, + .read = R_SCI_LIN_Read, + .communicationAbort = R_SCI_LIN_CommunicationAbort, + .callbackSet = R_SCI_LIN_CallbackSet, + .close = R_SCI_LIN_Close, + .sleepEnter = R_SCI_LIN_SleepEnter, + .sleepExit = R_SCI_LIN_SleepExit, + .wakeupSend = R_SCI_LIN_WakeupSend, + .informationFrameRead = R_SCI_LIN_InformationFrameRead, // [DEPRECATED] + .startFrameWrite = R_SCI_LIN_StartFrameWrite, // [DEPRECATED] + .informationFrameWrite = R_SCI_LIN_InformationFrameWrite, // [DEPRECATED] +}; + +/******************************************************************************************************************//** + * @addtogroup SCI_LIN + * @{ + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Functions + *********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Configures the LIN driver channel based on the input configuration. + * + * Implements @ref lin_api_t::open. + * + * Example: + * @snippet r_sci_lin_example.c R_SCI_LIN_Open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block or configuration structure is NULL. + * @retval FSP_ERR_INVALID_CHANNEL The requested channel does not exist on this MCU or the channel does not + * support LIN mode. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_MODE Setting not supported for selected mode + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_Open (lin_ctrl_t * const p_api_ctrl, lin_cfg_t const * const p_cfg) +{ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + + /* Check for null parameters */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_cfg->p_callback); + + /* Check control block isn't already open */ + FSP_ERROR_RETURN(p_ctrl->open != SCI_LIN_OPEN, FSP_ERR_ALREADY_OPEN); + + /* Make sure this channel supports LIN Mode (some MCUs do not support it on all SCI channels) */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_LIN_CHANNELS_MASK & (1U << p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_cfg->p_extend; + + /* Check for required IRQs */ + FSP_ASSERT(p_extend->rxi_irq >= 0); + FSP_ASSERT(p_extend->txi_irq >= 0); + FSP_ASSERT(p_extend->tei_irq >= 0); + FSP_ASSERT(p_extend->eri_irq >= 0); + FSP_ASSERT(p_extend->scix0_irq >= 0); + + /* Reception Control Field 1 must be disabled in master mode and enabled in slave mode */ + FSP_ERROR_RETURN((LIN_MODE_MASTER == p_cfg->mode) ^ (p_extend->scix1_irq >= 0), FSP_ERR_INVALID_MODE); + + #if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Auto Synchronization not supported in master mode */ + FSP_ERROR_RETURN((LIN_MODE_SLAVE == p_cfg->mode) || (p_extend->scix3_irq < 0), FSP_ERR_INVALID_MODE); + #endif +#else + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_cfg->p_extend; +#endif + + /* Initialize control block */ + p_ctrl->p_reg = + (R_SCI0_Type *) (R_SCI0_BASE + ((R_SCI1_BASE - R_SCI0_BASE) * p_cfg->channel)); + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + + /* Initialize variables preparing for transmission/reception */ + r_sci_lin_transfer_state_reset(p_ctrl); + + /* Calculate timer frequency */ + sci_lin_timer_divider_t timer_divider = (sci_lin_timer_divider_t) p_extend->p_baud_setting->timer_setting.tcss; + uint32_t system_clock = R_FSP_SystemClockHzGet(BSP_FEATURE_SCI_CLOCK); + p_ctrl->timer_freq_hz = (system_clock / (1U << timer_divider)); + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + + /* Report error if break duration ticks exceed UINT32_MAX */ + uint64_t break_duration_ticks; + if ((LIN_MODE_MASTER == p_cfg->mode) || (p_extend->scix3_irq < 0)) + { + break_duration_ticks = (uint64_t) p_ctrl->timer_freq_hz * p_extend->break_bits; + } + else + { + break_duration_ticks = (uint64_t) system_clock * p_extend->break_bits; + } + FSP_ERROR_RETURN(break_duration_ticks <= UINT32_MAX, FSP_ERR_INVALID_ARGUMENT); +#endif + + /* Configure, but do not enable the interrupts in the NVIC */ + r_sci_lin_irqs_cfg(p_ctrl); + + /* Initialize the SCI in LIN mode. */ + r_sci_lin_hw_configure(p_ctrl); + + /* Mark the control block as open */ + p_ctrl->open = SCI_LIN_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Begins non-blocking transmission of a LIN frame. + * + * In master mode, the LIN header (break, sync and protected identifier) is sent before the LIN data. + * - To transmit the LIN header only, set p_transfer_params->p_data to NULL. + * - To transmit both header and data, set p_transfer_params->p_data to the TX buffer to transmit. + * + * The LIN header is not transmitted in slave mode. Set p_transfer_params->p_data to the TX buffer to transmit. + * + * On successful header-only transmission completion, the callback is called with event @ref lin_event_t::LIN_EVENT_TX_HEADER_COMPLETE. + * On successful data transmission or header+data transmission completion, the callback is called with event @ref lin_event_t::LIN_EVENT_TX_DATA_COMPLETE. + * + * Implements @ref lin_api_t::write. + * + * Example: + * @snippet r_sci_lin_example.c R_SCI_LIN_Write + * + * @retval FSP_SUCCESS Data transmission started successfully. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block, transfer parameters, or tx/rx buffer is NULL, or 0 + * bytes length provided + * @retval FSP_ERR_IN_USE A transmission or reception is currently in progress. Call + * R_SCI_LIN_CommunicationAbort to cancel it if desired, or wait for the current + * transfer operation to complete before starting a new one. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_Write (lin_ctrl_t * const p_api_ctrl, const lin_transfer_params_t * const p_transfer_params) +{ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_transfer_params); + fsp_err_t err = r_sci_lin_read_write_parameter_checking(p_ctrl, p_transfer_params); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Send the header before the data in master mode only */ + uint8_t send_header = LIN_MODE_MASTER == p_ctrl->p_cfg->mode; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + + /* Check ID is at most 6 bits (only for master header transmission) */ + FSP_ERROR_RETURN((0 == (p_transfer_params->id & 0xC0)) || !send_header, FSP_ERR_INVALID_ARGUMENT); + + /* Check p_data is not null in slave mode */ + FSP_ASSERT(NULL != p_transfer_params->p_data || send_header); +#endif + + return r_sci_lin_write(p_ctrl, p_transfer_params, send_header); +} + +/******************************************************************************************************************//** + * Begins non-blocking data reception to receive user specified number of bytes into destination + * buffer pointer. + * + * The checksum type specifies the checksum type used for validation. If a non-standard algorithm is used, + * or the application prefers to validate the checksum outside the driver, or the application prefers + * to skip checksum validation, specify @ref lin_checksum_type_t::LIN_CHECKSUM_TYPE_NONE. If checksum + * validation is skipped, the @ref lin_checksum_type_t::LIN_EVENT_ERR_INVALID_CHECKSUM event is not possible. + * When @ref lin_checksum_type_t::LIN_CHECKSUM_TYPE_NONE is used, the number of bytes specified in the receive + * buffer length will be received (the driver will not expect to receive an additional 1 checksum byte), so + * if a non-standard checksum is used, sufficient space must be allocated in the write buffer and accounted for + * in the provided length. + * + * On successful data reception completion, the callback is called with event + * @ref lin_event_t::LIN_EVENT_RX_DATA_COMPLETE. + * + * Implements @ref lin_api_t::read. + * + * Example: + * @snippet r_sci_lin_example.c R_SCI_LIN_Read + * + * @retval FSP_SUCCESS Data reception started successfully. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block, transfer parameters, or tx/rx buffer is NULL, or 0 + * bytes length provided + * @retval FSP_ERR_IN_USE A transmission or reception is currently in progress. Call + * R_SCI_LIN_CommunicationAbort to cancel it if desired, or wait for the current + * transfer operation to complete before starting a new one. + * @retval FSP_ERR_INVALID_CALL Data reception is not possible because a header frame has not been received yet + * (slave mode only). + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_Read (lin_ctrl_t * const p_api_ctrl, lin_transfer_params_t * const p_transfer_params) +{ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_sci_lin_read_write_parameter_checking(p_api_ctrl, p_transfer_params); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + FSP_ASSERT(NULL != p_transfer_params->p_data); +#endif + + R_SCI0_Type * p_reg = p_ctrl->p_reg; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + + /* In slave mode, check that data reception is possible (due to successful header reception) */ + FSP_ERROR_RETURN((LIN_MODE_MASTER == p_ctrl->p_cfg->mode) || (0 == (R_SCI0_CR0_SFSF_Msk & p_reg->CR0)), + FSP_ERR_INVALID_CALL); +#endif + + /* Disable reception interrupts */ + uint8_t scr = p_reg->SCR; + p_reg->SCR = scr & (uint8_t) ~R_SCI0_SCR_RIE_Msk; + + /* Prepare receive state */ + p_ctrl->p_data = p_transfer_params->p_data; + p_ctrl->rx_bytes_expected = p_transfer_params->num_bytes; + p_ctrl->rx_bytes_received = 0; + p_ctrl->checksum = 0; + +#if SCI_LIN_CHECKSUM_SUPPORT_ENABLE + p_ctrl->validate_checksum = p_transfer_params->checksum_type != LIN_CHECKSUM_TYPE_NONE; + + /* Initialize checksum tracking fields */ + if (p_ctrl->validate_checksum) + { + p_ctrl->rx_bytes_expected++; + p_ctrl->checksum = r_sci_lin_checksum_initialize(p_transfer_params->id, p_transfer_params->checksum_type); + } +#endif + + /* Enable reception interrupts */ + p_reg->SSR &= (uint8_t) (~SCI_LIN_ERROR_SSR_EVENTS_CLEAR_MASK); + p_reg->SCR = scr | R_SCI0_SCR_RIE_Msk; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Cancels in progress frame data read or write, or header read or write. Break field reception cannot be + * cancelled. For slave nodes, reception of a new header is still enabled after a call to this function. + * + * Implements @ref lin_api_t::communicationAbort. + * + * @retval FSP_SUCCESS Data transfer aborted successfully or no transfer was in progress. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block is NULL. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_CommunicationAbort (lin_ctrl_t * const p_api_ctrl) +{ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_sci_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + /* Disable transmit interrupts, transmission, and reception interrupts */ + p_reg->SCR &= + (uint8_t) ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk | R_SCI0_SCR_RIE_Msk | R_SCI0_SCR_TE_Msk); + + /* Reset any in progress transmission/reception */ + r_sci_lin_transfer_state_reset(p_ctrl); + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Reset bit rate measurement hardware state in preparation to receive next start frame (slave only) */ + r_sci_lin_scix3_reset(p_ctrl); +#endif + + /* Reset break field detection in slave mode */ + r_sci_lin_break_field_detection_reset(p_ctrl); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * + * Implements @ref lin_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block or callback is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_CallbackSet (lin_ctrl_t * const p_api_ctrl, + void ( * p_callback)(lin_callback_args_t *), + void * const p_context, + lin_callback_args_t * const p_callback_memory) +{ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_sci_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check for null parameters */ + FSP_ASSERT(NULL != p_callback); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + lin_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(lin_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Calculates baud rate and LIN timer (TCNT, TPRE and TCSS) register settings. This function evaluates and determines + * the most accurate settings for the baud rate and timer related registers. + * + * The LIN timer setting is used for break field transmission/detection. Because the timer setting is specified in + * terms of bits, and the duration of a bit varies depending on baud rate, the baud rate register settings and timer + * register settings are related. The smallest possible LIN timer divider which can achieve the desired break field + * bits setting at the configured baud rate is selected to provide the highest measurement accuracy. + * + * The baud rate cannot be updated at runtime with this function. This function is provided to ease configuration of + * the initial baud settings. + * + * @param[in] p_baud_params Parameters required to calculate the baud rate + * @param[out] p_baud_setting If calculation succeeds, contains computed values to achieve requested baud rate. + * If calculation fails, the input structure is not modified. + * + * @retval FSP_SUCCESS Register settings updated in provided p_baud_setting + * @retval FSP_ERR_ASSERTION p_baud_setting was NULL + * @retval FSP_ERR_INVALID_ARGUMENT Cannot achieve combination of break field bits and baudrate with provided + * settings or p_baud_params->baudrate was 0 or p_baud_params->break_bits was 0 + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_BaudCalculate (sci_lin_baud_params_t const * const p_baud_params, + sci_lin_baud_setting_t * const p_baud_setting) +{ +#if (SCI_LIN_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_baud_params); + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN((0U != p_baud_params->break_bits), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != p_baud_params->baudrate), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((1U <= p_baud_params->delimiter_bits), FSP_ERR_INVALID_ARGUMENT); +#endif + + return r_sci_lin_baud_and_timer_setting_calculate(p_baud_params, p_baud_setting); +} + +/******************************************************************************************************************//** + * Set the the ID filter settings for filtering control field 1 (PID byte). + * + * NOTE: Setting the ID filter will abort any in-progress LIN header reception, as the ID filter + * settings cannot be changed during reception of the header. The next header will be received with the + * new settings. + * + * @snippet r_sci_lin_example.c R_SCI_LIN_IdFilterSet + * + * @param[in] p_api_ctrl Pointer to the LIN control block. + * @param[in] p_config The ID filter settings to apply + * + * @retval FSP_SUCCESS ID filter updated successfully. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block or p_config is NULL. + * @retval FSP_ERR_INVALID_MODE Function called by master node (not supported for master nodes) + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_IdFilterSet (lin_ctrl_t * const p_api_ctrl, sci_lin_id_filter_setting_t const * const p_config) +{ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_sci_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check for null parameters */ + FSP_ASSERT(NULL != p_config); + + /* Function only supported for slave mode */ + FSP_ERROR_RETURN(LIN_MODE_SLAVE == p_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); +#endif + + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + uint8_t cr1 = p_reg->CR1; + uint8_t icr = p_reg->ICR; + + /* Clear CR3.SDST and ESMER.ESME will initialize the HW and allow to set a new filter. */ + p_reg->CR3 = 0; + p_reg->ESMER = 0; + + /* Clear current CR1 filter settings and apply new setting for CR1 */ + cr1 &= (uint8_t) ~(R_SCI0_CR1_PIBS_Msk | R_SCI0_CR1_PIBE_Msk | R_SCI0_CR1_CF1DS_Msk); + cr1 |= (p_config->priority_interrupt_bit_select << R_SCI0_CR1_PIBS_Pos) | + (p_config->priority_interrupt_enable << R_SCI0_CR1_PIBE_Pos) | + (p_config->compare_data_select << R_SCI0_CR1_CF1DS_Pos); + + /* Apply new setting for all related register */ + p_reg->CR1 = cr1; + p_reg->CF1CR = p_config->compare_data_mask; + p_reg->PCF1DR = p_config->primary_compare_data; + p_reg->SCF1DR = p_config->secondary_compare_data; + + p_reg->ICR = (icr & (uint8_t) ~((uint8_t) R_SCI0_ICR_PIBDIE_Msk)) | + (uint8_t) (p_config->priority_interrupt_enable << R_SCI0_ICR_PIBDIE_Pos); + + /* After setting new filter, enable CR3.SDST and ESMER.ESME */ + p_reg->ESMER = R_SCI0_ESMER_ESME_Msk; + p_reg->CR3 = SCI_LIN_CR3_MASK_SLAVE; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Returns the currently configured ID filter settings. + * + * @param[in] p_api_ctrl Pointer to the LIN control block. + * @param[out] p_config The current ID filter settings + * + * @retval FSP_SUCCESS ID filter updated successfully. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block or p_config is NULL. + * @retval FSP_ERR_INVALID_MODE Function called by master node (not supported for master nodes) + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_IdFilterGet (lin_ctrl_t * const p_api_ctrl, sci_lin_id_filter_setting_t * const p_config) +{ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_sci_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check for null parameters */ + FSP_ASSERT(NULL != p_config); + + /* Function only supported for slave mode */ + FSP_ERROR_RETURN(LIN_MODE_SLAVE == p_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); +#endif + + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + uint16_t cr1 = p_reg->CR1; + uint8_t cf1cr = p_reg->CF1CR; + uint8_t pcf1dr = p_reg->PCF1DR; + uint8_t scf1dr = p_reg->SCF1DR; + + p_config->compare_data_mask = cf1cr; + p_config->primary_compare_data = pcf1dr; + p_config->secondary_compare_data = scf1dr; + p_config->priority_interrupt_bit_select = (uint8_t) ((cr1 & R_SCI0_CR1_PIBS_Msk) >> R_SCI0_CR1_PIBS_Pos); + p_config->priority_interrupt_enable = (uint8_t) ((cr1 & R_SCI0_CR1_PIBE_Msk) >> R_SCI0_CR1_PIBE_Pos); + p_config->compare_data_select = (uint8_t) ((cr1 & R_SCI0_CR1_CF1DS_Msk) >> R_SCI0_CR1_CF1DS_Pos); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Closes the LIN driver. + * + * Implements @ref lin_api_t::close. + * + * Example: + * @snippet r_sci_lin_example.c R_SCI_LIN_Close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. + *********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_Close (lin_ctrl_t * const p_api_ctrl) +{ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_sci_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + /* Disable transmission and reception */ + p_reg->SCR = SCI_LIN_SCR_INITIAL_VALUE; + p_reg->ESMER = 0; + p_reg->CR3 = 0; + p_reg->TCR = 0; + + /* Disable irqs */ + r_sci_lin_irqs_enable_disable(p_ctrl, r_sci_lin_irq_disable); + + /* Disable the clock to the SCI channel. */ + R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel); + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Send wakeup is not supported on the SCI LIN driver. + * + * Implements @ref lin_api_t::wakeupSend. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_WakeupSend (lin_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Sleep is not supported on the SCI LIN driver. + * + * Implements @ref lin_api_t::sleepEnter. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_SleepEnter (lin_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Sleep is not supported on the SCI LIN driver. + * + * Implements @ref lin_api_t::sleepExit. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_SleepExit (lin_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * [DEPRECATED] Use @ref R_SCI_LIN_Read. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_InformationFrameRead (lin_ctrl_t * const p_api_ctrl, + lin_transfer_params_t * const p_transfer_params) +{ + return R_SCI_LIN_Read(p_api_ctrl, p_transfer_params); +} + +/*******************************************************************************************************************//** + * [DEPRECATED] Use @ref R_SCI_LIN_Write + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_StartFrameWrite (lin_ctrl_t * const p_api_ctrl, uint8_t const id) +{ + lin_transfer_params_t params = + { + .id = id, + .p_data = NULL, + .num_bytes = 0, + .checksum_type = LIN_CHECKSUM_TYPE_NONE + }; + +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = r_sci_lin_read_write_parameter_checking(p_ctrl, ¶ms); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check ID is at most 6 bits */ + FSP_ERROR_RETURN(0 == (id & 0xC0), FSP_ERR_INVALID_ARGUMENT); + + /* Function only supported for master mode */ + FSP_ERROR_RETURN(LIN_MODE_MASTER == p_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); +#endif + + return r_sci_lin_write(p_api_ctrl, ¶ms, true); +} + +/*******************************************************************************************************************//** + * [DEPRECATED] Use @ref R_SCI_LIN_Write + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_SCI_LIN_InformationFrameWrite (lin_ctrl_t * const p_api_ctrl, + const lin_transfer_params_t * const p_transfer_params) +{ +#if SCI_LIN_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = + r_sci_lin_read_write_parameter_checking((sci_lin_instance_ctrl_t *) p_api_ctrl, p_transfer_params); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + FSP_ASSERT(NULL != p_transfer_params->p_data); +#endif + + return r_sci_lin_write(p_api_ctrl, p_transfer_params, false); +} + +/******************************************************************************************************************//** + * @} (end addtogroup SCI_LIN) + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Private Functions + *********************************************************************************************************************/ + +#if (SCI_LIN_CFG_PARAM_CHECKING_ENABLE) + +/******************************************************************************************************************//** + * Verifies the control structure is not NULL and the module is open. This reduces code size when parameter checking is + * enabled. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * + * @retval FSP_SUCCESS No error detected. + * @retval FSP_ERR_ASSERTION NULL input argument. + * @retval FSP_ERR_NOT_OPEN Module is not open. + *********************************************************************************************************************/ +static fsp_err_t r_sci_lin_common_parameter_checking (sci_lin_instance_ctrl_t const * const p_ctrl) +{ + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SCI_LIN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Parameter error check function for R_SCI_LIN_Write and R_SCI_LIN_Read + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] p_transfer_params Pointer to the transfer parameters for the transfer + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A transmission or reception is currently in progress. Call + * R_SCI_LIN_CommunicationAbort to cancel it if desired, or wait for the current + * transfer operation to complete before starting a new one. + * @retval FSP_ERR_ASSERTION Pointer to LIN control block, transfer parameters, or tx/rx buffer is NULL, or 0 + * bytes length provided + *********************************************************************************************************************/ +static fsp_err_t r_sci_lin_read_write_parameter_checking (sci_lin_instance_ctrl_t const * const p_ctrl, + lin_transfer_params_t const * const p_transfer_params) +{ + fsp_err_t err = r_sci_lin_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(NULL != p_transfer_params); + + /* Number of bytes and checksum parameters are only checked for data transfers */ + if (NULL != p_transfer_params->p_data) + { + FSP_ASSERT(p_transfer_params->num_bytes > 0); + FSP_ASSERT(((p_transfer_params->num_bytes < UINT8_MAX) || + (LIN_CHECKSUM_TYPE_NONE == p_transfer_params->checksum_type))); + } + + /* Check that a header transmission, data transmission, or data reception is not currently in progress */ + FSP_ERROR_RETURN((0 == p_ctrl->tx_header_bytes) && (0 == p_ctrl->tx_src_bytes) && (0 == p_ctrl->rx_bytes_expected), + FSP_ERR_IN_USE); + + return FSP_SUCCESS; +} + +#endif + +/******************************************************************************************************************//** + * Calculates both baud rate and timer register settings + * + * @param[in] p_baud_params Function inputs required to calculate the baud rate + * @param[out] p_baud_setting Baud rate calculation result + * + * @retval FSP_SUCCESS Calculation succeeded + * @retval FSP_ERR_INVALID_ARGUMENT Calculation failed/register settings not possible + *********************************************************************************************************************/ +static fsp_err_t r_sci_lin_baud_and_timer_setting_calculate (sci_lin_baud_params_t const * const p_baud_params, + sci_lin_baud_setting_t * const p_baud_setting) +{ + fsp_err_t err; + + /* Use temp variable in order to not update output arg unless both baud and timer calculations succeed */ + sci_lin_baud_setting_t tmp_baud_setting; + + err = r_sci_lin_baud_setting_calculate(p_baud_params, &tmp_baud_setting); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = r_sci_lin_timer_setting_calculate(p_baud_params, &tmp_baud_setting.timer_setting); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + *p_baud_setting = tmp_baud_setting; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Calculates the baud rate register settings + * + * @param[in] p_baud_params Function inputs required to calculate the baud rate + * @param[out] p_baud_setting Baud rate calculation result + * + * @retval FSP_SUCCESS Calculation succeeded + * @retval FSP_ERR_INVALID_ARGUMENT Calculation failed/register settings not possible + *********************************************************************************************************************/ +static fsp_err_t r_sci_lin_baud_setting_calculate (sci_lin_baud_params_t const * const p_baud_params, + sci_lin_baud_setting_t * const p_baud_setting) +{ + uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_SCI_CLOCK); + uint32_t divisor = 0; + uint32_t brr = 0; + int8_t cks = -1; + uint32_t divisor_shift; + + /* Get ABCS value from user's setting */ + uint8_t abcs = (uint8_t) p_baud_params->base_clock_cycles_per_bit; + + /* BRR is calculated by testing whether each possible divisor produces a valid BRR setting. + * Note ABCS is set in the user configuration and BGDM is fixed to 0. + * The divisors are checked in order, from smallest to largest. Since the smallest divisor always produces the lowest + * error, we can break out of the loop as soon as a valid BRR setting is found, since no other setting can have + * a smaller error. */ + for (uint8_t i = 0; i <= SCI_LIN_CKS_MAX; i++) + { + cks++; + divisor_shift = SCI_LIN_MIN_BAUD_DIVISOR_SHIFT + ((uint32_t) cks << 1U) - (uint32_t) (abcs); + divisor = (1U << divisor_shift) * p_baud_params->baudrate; + brr = (freq_hz / divisor) - 1U; + if (brr <= UINT8_MAX) + { + /* Save the baud settings. */ + p_baud_setting->semr_baudrate_bits = (uint8_t) (abcs << R_SCI0_SEMR_ABCS_Pos); + p_baud_setting->cks = (uint8_t) ((uint32_t) cks & R_SCI0_SMR_CKS_Msk); + p_baud_setting->brr = (uint8_t) brr; + + return FSP_SUCCESS; + } + } + + /* No valid setting found */ + return FSP_ERR_INVALID_ARGUMENT; +} + +/******************************************************************************************************************//** + * Calculates the lin timer register settings + * + * @param[in] p_baud_params Function inputs required to calculate the baud rate + * @param[out] p_timer_setting Timer setting calculation result + * + * @retval FSP_SUCCESS Calculation succeeded + * @retval FSP_ERR_INVALID_ARGUMENT Calculation failed/register settings not possible + *********************************************************************************************************************/ +static fsp_err_t r_sci_lin_timer_setting_calculate (sci_lin_baud_params_t const * const p_baud_params, + sci_lin_timer_setting_t * const p_timer_setting) +{ + sci_lin_timer_divider_t tcss; + uint32_t break_field = SCI_LIN_MAX_TIMER_INTERVAL; + uint32_t system_clock = R_FSP_SystemClockHzGet(BSP_FEATURE_SCI_CLOCK); + uint32_t lin_timer_freq_hz; + + /* TCSS is calculated so that the smallest divider that produces a valid value for Break field is selected */ + for (tcss = SCI_LIN_TCSS_MIN; tcss <= SCI_LIN_TCSS_MAX; tcss++) + { + lin_timer_freq_hz = (system_clock / (1U << tcss)); + + /* Compute break field */ + break_field = (lin_timer_freq_hz * p_baud_params->break_bits) / p_baud_params->baudrate; + + if (break_field <= SCI_LIN_MAX_TIMER_INTERVAL) + { + break; + } + } + + FSP_ERROR_RETURN(break_field <= SCI_LIN_MAX_TIMER_INTERVAL, FSP_ERR_INVALID_ARGUMENT); + + /* Compute break delimiter */ + uint32_t break_delimiter = (lin_timer_freq_hz * p_baud_params->delimiter_bits) / p_baud_params->baudrate; + + FSP_ERROR_RETURN(break_delimiter <= SCI_LIN_MAX_TIMER_INTERVAL, FSP_ERR_INVALID_ARGUMENT); + + /* Save the clock divider setting and counter setting for break field output */ + p_timer_setting->tcss = (uint8_t) (tcss & SCI_LIN_TCSS_MASK); + + /* (TCNT+1) x (TPRE+1) = ticks + * Let TCNT = ticks/256 + * => TPRE = (ticks/(TCNT+1)) -1 */ + p_timer_setting->break_field_tcnt = (uint8_t) (break_field >> 8U); + p_timer_setting->break_field_tpre = + (uint8_t) (((break_field + p_timer_setting->break_field_tcnt) / (p_timer_setting->break_field_tcnt + 1)) - 1); + + /* Save counter setting for break delimiter */ + p_timer_setting->delimiter_tcnt = (uint8_t) (break_delimiter >> 8U); + p_timer_setting->delimiter_tpre = + (uint8_t) (((break_delimiter + p_timer_setting->delimiter_tcnt) / (p_timer_setting->delimiter_tcnt + 1)) - 1); + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Calculates the protected identifier. + * + * Implements the algorithm according to LIN Protocol Specification Rev. 2.2A pg.53. + * + * The PID is an 8 bit field: [p1 p0 id5 id4 id3 id2 id1 id0]. + * P1 is bit 7 and is calculated as id1 XOR id3 XOR id4 XOR id5. + * P0 is bit 6 and is calculated as id0 XOR id1 XOR ix2 XOR id4. + * + * @param[in] id LIN unprotected frame identifier + * + * @retval LIN protected frame identifier result + *********************************************************************************************************************/ +static uint8_t r_sci_lin_pid_calculate (uint8_t id) +{ + /* ID is 6 bits */ + uint8_t pid = id & SCI_LIN_FRAME_ID_MASK; + + /* P0 = id0 ^ id1 ^ id2 ^ id4*/ + uint8_t tmp = (((id >> 0) ^ (id >> 1) ^ (id >> 2) ^ (id >> 4)) & 0x01); + pid |= (uint8_t) (tmp << 6U); + + /* P1 = ~(id1 ^ id3 ^ id4 ^ id5) */ + tmp = (uint8_t) ~(((id >> 1) ^ (id >> 3) ^ (id >> 4) ^ (id >> 5)) & 0x01); + pid |= (uint8_t) (tmp << 7U); + + return pid; +} + +#if SCI_LIN_CHECKSUM_SUPPORT_ENABLE + +/******************************************************************************************************************//** + * Add byte to checksum + * + * @param[in] byte Byte to add to current sum + * @param[in] current_sum Current checksum (intermediate sum) + * + * @retval New checksum result (after adding byte) + *********************************************************************************************************************/ +static uint8_t r_sci_lin_checksum_add_byte_to_sum (uint8_t byte, uint8_t current_sum) +{ + uint16_t new_sum = current_sum; + + new_sum += byte; + + /* LIN Protocol Specification Rev. 2.2A pg.32 section 2.3.1.5: + * 8-bit sum with carry is equivalent to sum all values and subtract + * 255 every time the sum is greater than or equal to 256 */ + if (new_sum > UINT8_MAX) + { + new_sum -= UINT8_MAX; + } + + return (uint8_t) new_sum; +} + +#endif + +#if SCI_LIN_CHECKSUM_SUPPORT_ENABLE + +/******************************************************************************************************************//** + * Initialize the checksum based on the checksum type + * + * @param[in] id LIN unprotected frame identifier + * @param[in] checksum_type Checksum type (classic or enhanced) + * + * @retval Initial checksum value for the provided checksum type + *********************************************************************************************************************/ +static uint8_t r_sci_lin_checksum_initialize (uint8_t id, lin_checksum_type_t checksum_type) +{ + uint8_t checksum = 0; + + if (LIN_CHECKSUM_TYPE_ENHANCED == checksum_type) + { + /* Compute PID and add to checksum. Enhanced checksum includes data and PID. Standard is data only. */ + checksum = r_sci_lin_pid_calculate(id); + } + + return checksum; +} + +#endif + +#if SCI_LIN_CHECKSUM_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Calculates the LIN checksum on data to be transmitted. For received frames, + * the checksum is calculated incrementally with each byte. + * + * @param[in] id LIN unprotected frame identifier. + * @param[in] p_data Pointer to data. + * @param[in] num_bytes Data frame data length. + * @param[in] checksum_type Checksum type (classic or enhanced). Frame ID 0x3C and 0x3D always use classic checksum. + * + * @retval LIN checksum result + **********************************************************************************************************************/ +static uint8_t r_sci_lin_checksum_calculate (uint8_t id, + uint8_t const * const p_data, + uint8_t num_bytes, + lin_checksum_type_t checksum_type) +{ + uint8_t checksum = r_sci_lin_checksum_initialize(id, checksum_type); + + for (uint8_t i = 0; i < num_bytes; i++) + { + checksum = r_sci_lin_checksum_add_byte_to_sum(p_data[i], checksum); + } + + return (uint8_t) ~checksum; +} + +#endif + +/******************************************************************************************************************//** + * Initializes the SCI common and LIN register settings and enable LIN interrupts. + * + * Initial settings are based on Figure "Example of Start Frame transmission" and Figure "Sample + * flowchart for reception of a Start Frame" and related Table "Example flow of SCI initialization + * in asynchronous mode with non-FIFO selected" in the SCI section of the relevant hardware manual. + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static void r_sci_lin_hw_configure (sci_lin_instance_ctrl_t * const p_ctrl) +{ + lin_cfg_t const * p_cfg = p_ctrl->p_cfg; + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_cfg->p_extend; + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + uint8_t cr0 = 0; + uint8_t cr2 = 0; + uint8_t icr = R_SCI0_ICR_BFDIE_Msk; + uint8_t tmr; + + /* Enable the SCI channel */ + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + + /* Ensure transmission and reception are disabled during initialization. */ + p_reg->SCR = SCI_LIN_SCR_INITIAL_VALUE; + + /* Make node-specific settings */ + if (LIN_MODE_SLAVE == p_cfg->mode) + { + p_reg->CR1 = (uint8_t) ((uint8_t) SCI_LIN_CR1_MASK_SLAVE | + (p_extend->filter_setting.priority_interrupt_bit_select << R_SCI0_CR1_PIBS_Pos) | + (p_extend->filter_setting.priority_interrupt_enable << R_SCI0_CR1_PIBE_Pos) | + (p_extend->filter_setting.compare_data_select << R_SCI0_CR1_CF1DS_Pos)); + p_reg->CF1CR = p_extend->filter_setting.compare_data_mask; + p_reg->PCF1DR = p_extend->filter_setting.primary_compare_data; + p_reg->SCF1DR = p_extend->filter_setting.secondary_compare_data; + p_reg->CF0CR = SCI_LIN_CF0CR_MASK_SLAVE; + p_reg->CF0DR = SCI_LIN_CF0DR_MASK_SLAVE; + tmr = SCI_LIN_BREAK_FIELD_DETERMINATION_MODE << R_SCI0_TMR_TOMS_Pos; + icr |= SCI_LIN_ICR_CONTROL_FIELD_MASK; + icr |= p_extend->filter_setting.priority_interrupt_enable << R_SCI0_ICR_PIBDIE_Pos; + } + else + { + tmr = SCI_LIN_BREAK_FIELD_OUTPUT_MODE << R_SCI0_TMR_TOMS_Pos; + } + + /* Configure LIN timer divider */ + tmr |= (p_extend->p_baud_setting->timer_setting.tcss << R_SCI0_TMR_TCSS_Pos); + +#if SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE + + /* Configure bus conflict detection clock */ + cr2 |= (uint8_t) (p_extend->bus_conflict_clock << R_SCI0_CR2_BCCS_Pos); + + /* Enable LIN bus collision interrupt if bus conflict detection support is enabled */ + icr |= (p_extend->scix2_irq >= 0) << (uint8_t) R_SCI0_ICR_BCDIE_Pos; +#endif + + /* Configure digital filter clock */ + cr2 |= (uint8_t) (p_extend->digital_filter_clock << R_SCI0_CR2_DFCS_Pos); + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Check whether or not auto synchronize is enabled */ + if (p_extend->scix3_irq >= 0) + { + /* Configure SCIX3 interrupt. */ + icr |= (uint8_t) R_SCI0_ICR_AEDIE_Msk; + + /* Configure auto synchronization setting. */ + cr0 |= (uint8_t) R_SCI0_CR0_BRME_Msk; + } +#endif + + /* Set required LIN settings. */ + p_reg->CR0 = cr0; + p_reg->CR2 = cr2; + p_reg->PCR = SCI_LIN_PCR_DEFAULT_VALUE; + p_reg->TMR = tmr; + p_reg->TPRE = p_extend->p_baud_setting->timer_setting.break_field_tpre; + p_reg->TCNT = p_extend->p_baud_setting->timer_setting.break_field_tcnt; + + /* Write the settings to the SCI control registers in the order specified by the initialization flow. */ + p_reg->FCR = SCI_LIN_FCR_DEFAULT_VALUE; + p_reg->SIMR1 = SCI_LIN_SIMR1_DEFAULT_VALUE; + p_reg->SPMR = SCI_LIN_SPMR_DEFAULT_VALUE; + p_reg->SMR = (uint8_t) (p_extend->p_baud_setting->cks << R_SCI0_SMR_CKS_Pos); + p_reg->SCMR = SCI_LIN_SCMR_DEFAULT_VALUE; + p_reg->SEMR = (uint8_t) (R_SCI0_SEMR_RXDESEL_Msk | p_extend->p_baud_setting->semr_baudrate_bits); + p_reg->BRR = p_extend->p_baud_setting->brr; + p_reg->MDDR = SCI_LIN_MDDR_DEFAULT_VALUE; + + /* Enable reception */ + p_reg->SCR = SCI_LIN_SCR_INITIAL_VALUE | R_SCI0_SCR_RE_Msk; + + /* Clear all flags BFDF, CF0MF, CF1MF, PIBDF, BCDF, AEDF */ + p_reg->STCR = SCI_LIN_STCR_CLEAR_MASK; + + /* Set LIN interrupt enable bits */ + p_reg->ICR = icr; + + /* Enable the LIN mode control. */ + p_reg->ESMER = R_SCI0_ESMER_ESME_Msk; + + /* Enable break field detection in slave mode */ + r_sci_lin_break_field_detection_reset(p_ctrl); + + /* Enable interrupt handlers in the NVIC */ + r_sci_lin_irqs_enable_disable(p_ctrl, r_sci_lin_irq_enable); +} + +/******************************************************************************************************************//** + * Clear LIN status flags (STCR and SSR) + * + * @param[in] p_reg SCI register pointer + * @param[in] ssr SSR flags to clear + * @param[in] stcr STCR flags to clear + * + *********************************************************************************************************************/ +static void r_sci_lin_flags_clear (R_SCI0_Type * const p_reg, uint8_t ssr, uint8_t stcr) +{ + p_reg->SSR &= (~ssr); + p_reg->STCR = stcr; +} + +/******************************************************************************************************************//** + * Enables the requested IRQ and sets the interrupt context + * + * @param[in] irq IRQ to enable + * @param[in] ipl Interrupt priority + * @param[in] p_context Pointer to interrupt context + *********************************************************************************************************************/ +static void r_sci_lin_irq_enable (IRQn_Type irq, uint8_t ipl, void * p_context) +{ + if (irq >= 0) + { + R_BSP_IrqCfgEnable(irq, ipl, p_context); + } +} + +/******************************************************************************************************************//** + * Disables the requested IRQ. + * + * @param[in] irq IRQ to disable + * @param[in] ipl Interrupt priority + * @param[in] p_context Pointer to interrupt context + *********************************************************************************************************************/ +static void r_sci_lin_irq_disable (IRQn_Type irq, uint8_t ipl, void * p_context) +{ + /* Parameters unused to allow using same function signature in r_sci_lin_irqs_enable_disable which reduces + * codes size */ + FSP_PARAMETER_NOT_USED(ipl); + FSP_PARAMETER_NOT_USED(p_context); + + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + } +} + +/******************************************************************************************************************//** + * Disables interrupt and clears pending status + * + * @param[in] irq IRQ number for this interrupt + *********************************************************************************************************************/ +static void r_sci_lin_irq_cfg (IRQn_Type const irq) +{ + r_sci_lin_irq_disable(irq, 0, 0); + + if (irq >= 0) + { + R_BSP_IrqStatusClear(irq); + } +} + +/******************************************************************************************************************//** + * Intializes interrupts in the NVIC, but does not enable them + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static void r_sci_lin_irqs_cfg (sci_lin_instance_ctrl_t * const p_ctrl) +{ + lin_cfg_t const * p_cfg = p_ctrl->p_cfg; + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_cfg->p_extend; + + /* Required */ + r_sci_lin_irq_cfg(p_extend->rxi_irq); + r_sci_lin_irq_cfg(p_extend->txi_irq); + r_sci_lin_irq_cfg(p_extend->tei_irq); + r_sci_lin_irq_cfg(p_extend->eri_irq); + r_sci_lin_irq_cfg(p_extend->scix0_irq); + if (LIN_MODE_SLAVE == p_cfg->mode) + { + r_sci_lin_irq_cfg(p_extend->scix1_irq); + } + +#if SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE + r_sci_lin_irq_cfg(p_extend->scix2_irq); +#endif +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + if (LIN_MODE_SLAVE == p_cfg->mode) + { + r_sci_lin_irq_cfg(p_extend->scix3_irq); + } +#endif +} + +/******************************************************************************************************************//** + * Enables or disables all LIN interrupts in the NVIC. Enable does not necessarily enable them in the SCI. + * + * @param[in] p_ctrl Pointer to driver control block + * @param[in] irqEnableDisableFunc r_sci_lin_irq_enable to enable interrupts. r_sci_lin_irq_disable to + * disable interrupts. + *********************************************************************************************************************/ +static inline void r_sci_lin_irqs_enable_disable (sci_lin_instance_ctrl_t * const p_ctrl, + void ( * irqEnableDisableFunc)( + IRQn_Type irq, + uint8_t ipl, + void * p_context)) +{ + lin_cfg_t const * p_cfg = p_ctrl->p_cfg; + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_cfg->p_extend; + + irqEnableDisableFunc(p_extend->rxi_irq, p_extend->rxi_ipl, p_ctrl); + irqEnableDisableFunc(p_extend->txi_irq, p_extend->txi_ipl, p_ctrl); + irqEnableDisableFunc(p_extend->tei_irq, p_extend->tei_ipl, p_ctrl); + irqEnableDisableFunc(p_extend->eri_irq, p_extend->eri_ipl, p_ctrl); + irqEnableDisableFunc(p_extend->scix0_irq, p_extend->scix0_ipl, p_ctrl); + if (LIN_MODE_SLAVE == p_cfg->mode) + { + irqEnableDisableFunc(p_extend->scix1_irq, p_extend->scix1_ipl, p_ctrl); + } + +#if SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE + irqEnableDisableFunc(p_extend->scix2_irq, p_extend->scix2_ipl, p_ctrl); +#endif + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + irqEnableDisableFunc(p_extend->scix3_irq, p_extend->scix3_ipl, p_ctrl); +#endif +} + +/*******************************************************************************************************************//** + * Transmit the LIN frame + * + * Header transmission is based on flow chart process in Figure + * "Example of Start Frame transmission" in the SCI section of the relevant hardware manual. + * + * @param[in] p_ctrl Pointer to driver control block + * @param[in] p_transfer_params Pointer to the transfer parameters for the transfer + * @param[in] send_header Set to true if the LIN header should be transmitted before the frame data (master mode only) + * + * @retval FSP_SUCCESS Transmission started successfully + **********************************************************************************************************************/ +static fsp_err_t r_sci_lin_write (sci_lin_instance_ctrl_t * const p_ctrl, + const lin_transfer_params_t * const p_transfer_params, + uint8_t const send_header) +{ + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + /* Stop any in-progress break field transmission */ + p_reg->TCR = 0; + + /* Disable transmit interrupts, transmission, and reception interrupts */ + p_reg->SCR &= + (uint8_t) ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk | R_SCI0_SCR_RIE_Msk | R_SCI0_SCR_TE_Msk); + + /* Prepare the data transmission state. */ + p_ctrl->p_data = p_transfer_params->p_data; + p_ctrl->tx_src_bytes = 0; + p_ctrl->event = LIN_EVENT_NONE; + p_ctrl->checksum = 0; + + if (p_transfer_params->p_data) + { + p_ctrl->tx_src_bytes = p_transfer_params->num_bytes; + +#if SCI_LIN_CHECKSUM_SUPPORT_ENABLE + if (p_transfer_params->checksum_type != LIN_CHECKSUM_TYPE_NONE) + { + /* If checksum generation is enabled, calculate the checksum */ + p_ctrl->checksum = r_sci_lin_checksum_calculate(p_transfer_params->id, + p_transfer_params->p_data, + p_transfer_params->num_bytes, + p_transfer_params->checksum_type); + p_ctrl->tx_src_bytes++; + } + else +#endif + { + /* User requested not to append checksum. Therefore either we are not using a checksum, + * or we are using a custom checksum. Copy last byte into 'checksum' field. + * From txi_isr perspective, last byte is always read from checksum, regardless of + * whether that byte represents a literal checksum. */ + p_ctrl->checksum = p_transfer_params->p_data[p_transfer_params->num_bytes - 1]; + } + } + + if (send_header) + { + /* Set number of header bytes remaining to transmit */ + p_ctrl->tx_header_bytes = SCI_LIN_HEADER_NUM_BYTES; + + /* Save the PID of the last attempted transmit */ + p_ctrl->last_pid = r_sci_lin_pid_calculate(p_transfer_params->id); + + /* Ensure transmission is enabled. Do not set SCR.TE and TIE to 1 at the same time to + * avoid SCIn_TXI output before the Break Field */ + p_reg->SCR |= (uint8_t) (R_SCI0_SCR_TE_Msk); + + /* Clear flags */ + r_sci_lin_flags_clear(p_reg, SCI_LIN_SSR_CLEAR_MASK, SCI_LIN_STCR_CLEAR_MASK); + + /* Start outputting break field. */ + p_reg->TCR = R_SCI0_TCR_TCST_Msk; + } + else + { + /* Clear flags */ + r_sci_lin_flags_clear(p_ctrl->p_reg, SCI_LIN_SSR_CLEAR_MASK, SCI_LIN_STCR_CLEAR_MASK); + + /* Enable transmit interrupt to start transmission. Setting TE and TIE together causes a + * TXI interrupt which will kick of transmission of the first byte. */ + p_reg->SCR |= (uint8_t) (R_SCI0_SCR_TE_Msk | R_SCI0_SCR_TIE_Msk); + } + + return FSP_SUCCESS; +} + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + +/******************************************************************************************************************//** + * Calculates the detected baud rate and updates the baud rate and break field threshold register settings to + * synchronize with the master's rate. + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static void r_sci_lin_scix3_synchronize (sci_lin_instance_ctrl_t * const p_ctrl) +{ + R_SCI0_Type * const p_reg = p_ctrl->p_reg; + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + sci_lin_baud_setting_t * p_baud_setting = p_extend->p_baud_setting; + + /* Calculate the baud rate from the measured bit time */ + uint32_t baudrate = (p_ctrl->timer_freq_hz * SCI_LIN_SYNC_EDGES) / p_ctrl->sync_bits_sum; + + sci_lin_baud_params_t baud_params = + { + baudrate, + p_extend->break_bits, + p_extend->delimiter_bits, + (sci_lin_base_clock_t) p_extend->p_baud_setting->semr_baudrate_bits_b.abcs, + }; + + /* Calculate new baud and timer settings. Only update register settings if they are possible in the hardware */ + if (FSP_SUCCESS == r_sci_lin_baud_and_timer_setting_calculate(&baud_params, p_baud_setting)) + { + /* Disable LIN mode for re-initialization */ + p_reg->ESMER = 0; + p_reg->TCR = 0; + + /* Disable bit rate measurement */ + p_reg->CR0_b.BRME = 0; + + /* Disable start frame detection */ + p_reg->CR3 = 0; + + /* Clearing and resetting RE cancels the in-progress reception. Disable BFE and CF0RE + * because we have already received them, and prepare to receive a CF1-only start frame */ + p_reg->CR1 &= (uint8_t) ~SCI_LIN_CR1_MASK_SLAVE; + + /* Update timer frequency */ + sci_lin_timer_divider_t timer_divider = (sci_lin_timer_divider_t) p_baud_setting->timer_setting.tcss; + p_ctrl->timer_freq_hz = (R_FSP_SystemClockHzGet(BSP_FEATURE_SCI_CLOCK) / (1U << timer_divider)); + uint8_t tmr = p_reg->TMR; + p_reg->TMR = (tmr & (uint8_t) ~R_SCI0_TMR_TCSS_Msk) | (uint8_t) (timer_divider << R_SCI0_TMR_TCSS_Pos); + + /* Apply new baud setting. BRR, SMR, SEMR can only be written to when SCR.TE and SCR.RE are 0. + * TE is already 0, but we must clear RE here to update the baud settings. */ + uint8_t scr = p_reg->SCR & (uint8_t) ~R_SCI0_SCR_RIE_Msk; + p_reg->SCR = scr & (uint8_t) ~R_SCI0_SCR_RE_Msk; + p_reg->SMR = (uint8_t) (p_baud_setting->cks << R_SCI0_SMR_CKS_Pos); + p_reg->SEMR = (uint8_t) (R_SCI0_SEMR_RXDESEL_Msk | p_baud_setting->semr_baudrate_bits); + p_reg->BRR = p_baud_setting->brr; + + /* Compute 1.5 bytes (15 Tbit) duration to wait whether CF1 is detected. */ + uint32_t delay_time = (p_ctrl->timer_freq_hz * SCI_LIN_CF1_WAIT_BIT_COUNT) / baudrate; + delay_time = (delay_time < SCI_LIN_MAX_TIMER_INTERVAL) ? delay_time : (SCI_LIN_MAX_TIMER_INTERVAL - 1); + + uint8_t delay_tcnt = (uint8_t) (delay_time >> 8U); + uint8_t delay_tpre = (uint8_t) (((delay_time + delay_tcnt) / (delay_tcnt + 1)) - 1); + + /* Switch to timer mode to time the CF1 timeout */ + p_reg->TMR_b.TOMS = SCI_LIN_TIMER_MODE; + + /* Setting counter for delay time */ + p_reg->TPRE = delay_tpre; + p_reg->TCNT = delay_tcnt; + + /* Discard received data and clear the CF0 received and FER flags to advance start frame reception state */ + r_sci_lin_flags_clear(p_reg, R_SCI0_SSR_RDRF_Msk | R_SCI0_SSR_FER_Msk, R_SCI0_STCR_CF0MCL_Msk); + + /* Enable the timer to start counting 15 Tbit */ + p_reg->TCR = R_SCI0_TCR_TCST_Msk; + + /* Re-enable reception */ + p_reg->SCR = scr; + + /* Re-enable LIN mode. */ + p_reg->ESMER = R_SCI0_ESMER_ESME_Msk; + + /* Restart reception. Expect a start frame with CF1 only. */ + p_reg->CR3 = SCI_LIN_CR3_MASK_SLAVE; + } +} + +#endif + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Check for errors in received SCIX3 measurement data. Because the SCIX3 interrupt detects edges, the level of the + * RXDn line is of limited usefulness (it will always alternate between 0 and 1 as we expect in the sync byte because + * we are detecting all edge changes). But in the event of a bit error, it will appear as if multiple bit times have + * elapsed between edges instead of just 1. Comparing the duration of each bit to the average bit duration received + * so far can detect bit errors/missed bits and avoid adjusting the baud rate to the wrong value. + * + * @param[in] p_ctrl Pointer to driver control block + * @param[in] count Latest counter measurement + * + * @returns true if an error occurred, false otherwise + **********************************************************************************************************************/ +static bool r_sci_lin_scix3_latest_bit_has_error (sci_lin_instance_ctrl_t * const p_ctrl, uint32_t count) +{ + bool has_error = false; + + /* Increment of sync bit received */ + p_ctrl->sync_bits_received++; + + /* Check collected all sync edges, except 2 delimiter raising and falling edge */ + if (p_ctrl->sync_bits_received > 2) + { + p_ctrl->sync_bits_sum += count; + + uint32_t avg_count = (p_ctrl->sync_bits_sum / (uint32_t) (p_ctrl->sync_bits_received - 2)); + + /* Compute absolute value of difference in bit duration */ + uint32_t delta = avg_count > count ? (avg_count - count) : (count - avg_count); + + /* Check that this bit is within 12.5% of the duration of the average */ + uint32_t threshold = (avg_count >> 3U); + + has_error = delta > threshold; + } + + return has_error; +} + +#endif + +/******************************************************************************************************************//** + * Handle error interrupt + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static lin_event_t r_sci_lin_eri_handler (sci_lin_instance_ctrl_t * const p_ctrl) +{ + R_SCI0_Type * p_reg = p_ctrl->p_reg; + lin_event_t event = LIN_EVENT_NONE; + uint8_t scr = p_reg->SCR; + uint8_t ssr = p_reg->SSR; + + /* Begin error handling according to flow chart process in Figure + * "Example of Flowchart for Receive Error Handling (during Reception of the Start Frame)" + * in the SCI section of the relevant hardware manual. */ + + /* Stop counting by the timer */ + p_reg->TCR = 0; + + /* Disable LIN mode. The state of the LIN mode control section is initialized. */ + p_reg->ESMER = 0; + + /* Enable LIN mode. */ + p_reg->ESMER = R_SCI0_ESMER_ESME_Msk; + + /* Suspend transmission and transmit interrupts, and reception interrupts */ + p_reg->SCR = scr & + (uint8_t) ~(R_SCI0_SCR_TE_Msk | R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk | R_SCI0_SCR_RIE_Msk); + + /* Determine cause of error. */ + if (ssr & R_SCI0_SSR_FER_Msk) + { + event = LIN_EVENT_ERR_FRAMING; + } + else if (ssr & R_SCI0_SSR_ORER_Msk) + { + event = LIN_EVENT_ERR_OVERRUN; + } + else + { + /* Do nothing */ + } + + /* Clear error conditions and discard RDR data. */ + r_sci_lin_flags_clear(p_ctrl->p_reg, SCI_LIN_ERROR_SSR_EVENTS_CLEAR_MASK, SCI_LIN_ERROR_STCR_EVENTS_CLEAR_MASK); + + /* Reset break field detection in slave mode */ + r_sci_lin_break_field_detection_reset(p_ctrl); + + return event; +} + +/********************************************************************************************************************** + * Process received data byte and return an event if the user should be notified via callback. 0 is returned + * if no event of user interest is detected. + * + * @param[in] p_ctrl Pointer to driver control block + * @return 0 if no event present (rx still in progress), otherwise the lin_event_t to pass to the user callback + *********************************************************************************************************************/ +lin_event_t r_sci_lin_rxi_handler (sci_lin_instance_ctrl_t * const p_ctrl) +{ + lin_event_t event = LIN_EVENT_NONE; + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + /* Data byte */ + if (p_ctrl->rx_bytes_expected > p_ctrl->rx_bytes_received) + { + uint8_t bytes_remaining = p_ctrl->rx_bytes_expected - p_ctrl->rx_bytes_received; + + /* Read data byte from RDR */ + uint8_t rx_byte = p_reg->RDR; + + /* Check if this is the last byte in the transfer */ + if (1 == bytes_remaining) + { + event = LIN_EVENT_RX_DATA_COMPLETE; + +#if SCI_LIN_CHECKSUM_SUPPORT_ENABLE + + /* Perform checksum validation if requested */ + if (p_ctrl->validate_checksum) + { + /* Validate checksum. At this point, p_ctrl->checksum contains the checksum over the data bytes. */ + if (((p_ctrl->checksum + rx_byte)) != SCI_LIN_CHECKSUM_OK) + { + event = LIN_EVENT_ERR_INVALID_CHECKSUM; + } + + /* Save the received checksum byte */ + p_ctrl->checksum = rx_byte; + } + else +#endif + { + /* Checksum validation skipped (nonstandard checksum or checksum not present). + * Store the received byte as data. */ + *p_ctrl->p_data++ = rx_byte; + p_ctrl->rx_bytes_received++; + } + + /* Data reception complete. Reset receive state and stop reception interrupts. */ + p_ctrl->rx_bytes_expected = 0; + p_ctrl->p_data = NULL; + p_reg->SCR_b.RIE = 0; +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Reset bit rate measurement hardware state in preparation to receive next start frame (slave only) */ + r_sci_lin_scix3_reset(p_ctrl); +#endif + + /* Reset break field detection in slave mode */ + r_sci_lin_break_field_detection_reset(p_ctrl); + } + /* Received a byte which is not the last byte */ + else + { +#if SCI_LIN_CHECKSUM_SUPPORT_ENABLE + + /* Add the received byte to the running checksum */ + if (p_ctrl->validate_checksum) + { + p_ctrl->checksum = r_sci_lin_checksum_add_byte_to_sum(rx_byte, p_ctrl->checksum); + } +#endif + + /* Store the received byte */ + *p_ctrl->p_data++ = rx_byte; + p_ctrl->rx_bytes_received++; + } + } + else + { + /* Byte received out of sequence or frame is ignored due to filering (no CF1 match). */ + + /* Discard the byte */ + p_reg->SSR_b.RDRF = 0; + + /* Stop reception interrupts. */ + p_reg->SCR_b.RIE = 0; + + /* Reset break field detection in slave mode */ + r_sci_lin_break_field_detection_reset(p_ctrl); + } + + return event; +} + +/******************************************************************************************************************//** + * Transmit next data byte + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static void r_sci_lin_txi_handler (sci_lin_instance_ctrl_t * const p_ctrl) +{ + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + if (p_ctrl->tx_header_bytes || p_ctrl->tx_src_bytes) + { + if (p_ctrl->tx_header_bytes) + { + /* Write the sync word if this is the first header byte. Otherwise, this is the second header byte (the PID). */ + p_reg->TDR = (SCI_LIN_HEADER_NUM_BYTES == p_ctrl->tx_header_bytes) ? + SCI_LIN_SYNC : p_ctrl->last_pid; + + p_ctrl->event = LIN_EVENT_TX_HEADER_COMPLETE; + p_ctrl->tx_header_bytes--; + } + else if (1 < p_ctrl->tx_src_bytes) + { + /* Write next data byte */ + p_reg->TDR = *p_ctrl->p_data++; + p_ctrl->tx_src_bytes--; + } + else + { + /* Write checksum byte when there is only 1 data byte remaining to transmit */ + p_reg->TDR = p_ctrl->checksum; + p_ctrl->event = LIN_EVENT_TX_DATA_COMPLETE; + p_ctrl->tx_src_bytes = 0; + } + + if ((0 == p_ctrl->tx_header_bytes) && (0 == p_ctrl->tx_src_bytes)) + { + /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */ + uint8_t scr_temp = p_reg->SCR; + scr_temp |= R_SCI0_SCR_TEIE_Msk; + scr_temp &= (uint8_t) ~(R_SCI0_SCR_TIE_Msk); + p_reg->SCR = scr_temp; + p_ctrl->p_data = NULL; + } + } +} + +/********************************************************************************************************************** + * Handle break field detected + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static void r_sci_lin_scix0_handler (sci_lin_instance_ctrl_t * const p_ctrl) +{ + lin_cfg_t const * p_cfg = p_ctrl->p_cfg; + R_SCI0_Type * const p_reg = p_ctrl->p_reg; + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Clear the BFDF flag */ + p_reg->STCR = R_SCI0_STCR_BFDCL_Msk; + + if (LIN_MODE_MASTER == p_cfg->mode) + { + /* Stop the timer counting after Break Field low width, before the next underflow of time occurs */ + p_reg->TCR = 0; + + if (SCI_LIN_BREAK_FIELD_OUTPUT_MODE == p_reg->TMR_b.TOMS) + { + /* Switch to timer mode to time the break delimiter */ + p_reg->TMR_b.TOMS = SCI_LIN_TIMER_MODE; + + /* Setting counter for break delimiter */ + p_reg->TPRE = p_extend->p_baud_setting->timer_setting.delimiter_tpre; + p_reg->TCNT = p_extend->p_baud_setting->timer_setting.delimiter_tcnt; + + /* Start the counter */ + p_reg->TCR = R_SCI0_TCR_TCST_Msk; + } + else + { + /* Switch to break field low width output mode */ + p_reg->TMR_b.TOMS = SCI_LIN_BREAK_FIELD_OUTPUT_MODE; + + /* Setting the counter as the original value for the next break field length */ + p_reg->TPRE = p_extend->p_baud_setting->timer_setting.break_field_tpre; + p_reg->TCNT = p_extend->p_baud_setting->timer_setting.break_field_tcnt; + + /* Disable transmit function, then re-enable it with TIE to generate a TXI interrupt request. + * Refer to Figure "Example of Start Frame Transmission (2/2)" in the SCI section of the + * relevant hardware manual. */ + p_reg->SCR &= (uint8_t) (~R_SCI0_SCR_TE_Msk); + p_reg->SCR |= (uint8_t) (R_SCI0_SCR_TE_Msk | R_SCI0_SCR_TIE_Msk); + } + } + else + { + /* Clear flags that may have occurred during previous frames to prepare for reception */ + r_sci_lin_flags_clear(p_reg, SCI_LIN_ERROR_SSR_EVENTS_CLEAR_MASK, SCI_LIN_ERROR_STCR_EVENTS_CLEAR_MASK); + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + if (SCI_LIN_TIMER_MODE == p_reg->TMR_b.TOMS) + { + /* Disable LIN mode for re-initialization */ + p_reg->ESMER = 0; + p_reg->TCR = 0; + + /* Switch to break field low width determination mode */ + p_reg->TMR_b.TOMS = SCI_LIN_BREAK_FIELD_DETERMINATION_MODE; + + /* Set the counter value for the next break field */ + p_reg->TPRE = p_extend->p_baud_setting->timer_setting.break_field_tpre; + p_reg->TCNT = p_extend->p_baud_setting->timer_setting.break_field_tcnt; + + /* Start the timer */ + p_reg->TCR = R_SCI0_TCR_TCST_Msk; + + /* Re-enable break field start frame receiving */ + p_reg->CR1 |= (uint8_t) SCI_LIN_CR1_MASK_SLAVE; + + /* Re-enable LIN mode. */ + p_reg->ESMER = R_SCI0_ESMER_ESME_Msk; + + /* Slave Start Frame Detection Start */ + p_reg->CR3 = SCI_LIN_CR3_MASK_SLAVE; + } + else + { + /* Reset auto synchronization state before starting the next baudrate auto synchronize function */ + p_ctrl->sync_bits_received = 0; + p_ctrl->sync_bits_sum = 0; + p_reg->CR0_b.BRME = 1; + } +#endif + } +} + +/********************************************************************************************************************** + * Handle control field 0/1 match and priority interrupt bit detected + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +lin_event_t r_sci_lin_scix1_handler (sci_lin_instance_ctrl_t * const p_ctrl) +{ + lin_event_t event = LIN_EVENT_NONE; + R_SCI0_Type * p_reg = p_ctrl->p_reg; +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; +#endif + uint8_t str = p_reg->STR; + + /* Check if control field 0 was received*/ + if (str & R_SCI0_STR_CF0MF_Msk) + { + /* Discard received data and clear the CF0 received flag to advance header reception state */ + r_sci_lin_flags_clear(p_reg, R_SCI0_SSR_RDRF_Msk, R_SCI0_STCR_CF0MCL_Msk); + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Disable bit rate measurement once CF0 is received. It will have been disabled already in the + * SCIX3 handler if bit rate measurement completed successfully. But it is possible for bit rate + * measurement to fail and the frame to still be received as long as the baud rates of sender + * and receiver are close enough. */ + p_reg->CR0_b.BRME = 0; +#endif + } + else if (str & (R_SCI0_STR_PIBDF_Msk | R_SCI0_STR_CF1MF_Msk)) + { +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + if (SCI_LIN_TIMER_MODE == p_reg->TMR_b.TOMS) + { + /* Stop the timer counting */ + p_reg->TCR = 0; + + /* Switch to break field low width determination mode */ + p_reg->TMR_b.TOMS = SCI_LIN_BREAK_FIELD_DETERMINATION_MODE; + + /* Set the counter value for the next break field */ + p_reg->TPRE = p_extend->p_baud_setting->timer_setting.break_field_tpre; + p_reg->TCNT = p_extend->p_baud_setting->timer_setting.break_field_tcnt; + } + + /* Re-enable break field start frame receiving */ + p_reg->CR1 |= (uint8_t) SCI_LIN_CR1_MASK_SLAVE; +#endif + + /* Clear CF1MF flag in the STR register */ + p_reg->STCR = R_SCI0_STCR_PIBDCL_Msk | R_SCI0_STCR_CF1MCL_Msk; + + /* Read the received data */ + uint8_t pid = p_reg->RDR; + + /* Set the event to notify the application (slave node only). */ + event = LIN_EVENT_RX_HEADER_COMPLETE; + + /* Check parity */ + if (r_sci_lin_pid_calculate(pid) != pid) + { + event = LIN_EVENT_ERR_PARITY; + + /* Reset break field detection in slave mode */ + r_sci_lin_break_field_detection_reset(p_ctrl); + } + else + { + /* Save received PID (Control Field 1) */ + p_ctrl->last_pid = pid; + } + + /* Enable reception interrupts to receive the data frame */ + p_reg->SCR |= R_SCI0_SCR_RIE_Msk; + } + else + { + /* Do nothing */ + } + + return event; +} + +#if SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE + +/********************************************************************************************************************** + * Handle bus collision detected + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static lin_event_t r_sci_lin_scix2_handler (sci_lin_instance_ctrl_t * const p_ctrl) +{ + R_SCI0_Type * p_reg = p_ctrl->p_reg; + uint8_t scr = p_reg->SCR; + + /* Suspend transmission and transmit interrupts, and reception interrupts */ + p_reg->SCR = scr & + (uint8_t) ~(R_SCI0_SCR_TE_Msk | R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk | + R_SCI0_SCR_RIE_Msk); + + /* Clear error conditions and discard RDR data. */ + r_sci_lin_flags_clear(p_reg, SCI_LIN_ERROR_SSR_EVENTS_CLEAR_MASK, SCI_LIN_ERROR_STCR_EVENTS_CLEAR_MASK); + + #if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Reset bit rate measurement hardware state in preparation to receive next start frame (slave only) */ + r_sci_lin_scix3_reset(p_ctrl); + #endif + + /* Reset break field detection in slave mode */ + r_sci_lin_break_field_detection_reset(p_ctrl); + + return LIN_EVENT_ERR_BUS_COLLISION_DETECTED; +} + +#endif + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + +/******************************************************************************************************************//** + * Resets bit rate measurement for the next frame by clearing BRME, then resetting it at the same time. + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static void r_sci_lin_scix3_reset (sci_lin_instance_ctrl_t * const p_ctrl) +{ + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + if (p_extend->scix3_irq >= 0) + { + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + uint8_t cr0 = p_reg->CR0; + + /* Stop bit rate measurement and start frame reception */ + p_reg->CR0 = cr0 & (uint8_t) ~(R_SCI0_CR0_BRME_Msk); + + /* Reset bit rate measurement for next frame */ + p_reg->CR0 = cr0 | (uint8_t) (R_SCI0_CR0_BRME_Msk); + } +} + +#endif + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + +/******************************************************************************************************************//** + * Handles active edge detection when auto synchronization is enabled. + * + * The SCIX3 interrupt triggers on the rising edge of the first data bit of control field 0, and on each subsequent + * edge (rising or falling) of control field 0. + * + * @par Measurement Synchronization + * + * The TPRE/TCNT contains the duration, in LIN timer ticks, since the previous detected edge. Since the value of control + * field 0 is 0x55 (alternating ones and zeros), it can be used to measure the duration of each bit and update the + * baud rate and break field width register settings. + * + * Every time a control field 0 edge is received, its duration is added to an accumulated sum. + * On reception of each edge, if no error occurred, the bit duration is added to a running sum. Once + * SCI_LIN_SYNC_EDGES are received, the average bit duration is calculated, and used + * to estimate the baud rate and adjust the baud rate and break field threshold register settings. + * + * @par Measurement Error Avoidance + * + * On each edge (rising and falling) of control field 0, TCNT/TPRE is read and compared to the previous TCNT/TPRE + * capture. If the baudrate differ by more than 6.25%, it is assumed that an error occurred, and the running sum is + * reset. If SCI_LIN_SYNC_EDGES are received without error subsequent to the error, the bit rate can still be + * estimated. Otherwise, the bit rate will not be updated. + * + * @param[in] p_ctrl Pointer to driver control block + *********************************************************************************************************************/ +static void r_sci_lin_scix3_handler (sci_lin_instance_ctrl_t * const p_ctrl) +{ + R_SCI0_Type * p_reg = p_ctrl->p_reg; + sci_lin_extended_cfg_t const * const p_extend = (sci_lin_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Get the bit duration (in LIN timer ticks) of the most recently received bit of control field 0. + * For the most accurate measurement, read this register as early as possible in the ISR. */ + uint8_t tpre = p_reg->TPRE; + uint8_t tcnt = p_reg->TCNT; + + uint8_t tcnt_base = p_extend->p_baud_setting->timer_setting.break_field_tcnt; + uint8_t tpre_base = p_extend->p_baud_setting->timer_setting.break_field_tpre; + + /* Calculate the elapsed ticks based on the timer counters: + * - The prescaler (TPRE) counts down from TPRE_base to 0. + * - Each time TPRE reloads back to TPRE_base, the main counter (TCNT) decreases by 1. + * 1) The number of times TCNT has decreased: (TCNT_base - TCNT) + * 2) Each TCNT decrement corresponds to (TPRE_base + 1) prescaler ticks. + * 3) Add the remaining partial prescaler ticks counted so far: (TPRE_base - TPRE) */ + uint32_t counter = (uint32_t) (((tcnt_base - tcnt) * (tpre_base + 1)) + tpre_base - tpre); + + /* Clear AEDF flag immediately */ + p_reg->STCR = R_SCI0_STCR_AEDCL_Msk; + + /* Check for bit errors */ + if (false == r_sci_lin_scix3_latest_bit_has_error(p_ctrl, counter)) + { + /* Check if we received enough bits to syncrhonize, except 2 delimiter raising and falling edge */ + if (SCI_LIN_SYNC_EDGES == (p_ctrl->sync_bits_received - 2)) + { + /* Perform synchronization. */ + r_sci_lin_scix3_synchronize(p_ctrl); + + /* Clear the data after synchronization */ + p_ctrl->sync_bits_received = 0; + p_ctrl->sync_bits_sum = 0; + } + } + else + { + /* Measurement error occurred. + * + * The frame can stil be received, even if there was a measurement error. + * We set BRME=0 here in case the measurement error to not receive another edge + * Enable reception interrupts to check if any framing error during auto synchronization. + * If there is a reception error, it will be caught and handled in the ERI handler. */ + p_reg->CR0_b.BRME = 0; + p_ctrl->sync_bits_received = 0; + p_ctrl->sync_bits_sum = 0; + + p_reg->SCR |= R_SCI0_SCR_RIE_Msk; + } +} + +#endif + +/******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to LIN instance control block + * @param[in] event Event code + *********************************************************************************************************************/ +static void r_sci_lin_call_callback (sci_lin_instance_ctrl_t * p_ctrl, lin_event_t event) +{ + lin_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + lin_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->pid = p_ctrl->last_pid; + p_args->p_context = p_ctrl->p_context; + p_args->bytes_received = p_ctrl->rx_bytes_received; + p_args->checksum = p_ctrl->checksum; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the + * callback. */ + sci_lin_prv_ns_callback p_callback = (sci_lin_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the + * callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/******************************************************************************************************************//** + * Reset break field detection + * + * @param[in] p_ctrl Pointer to LIN instance control block + *********************************************************************************************************************/ +static void r_sci_lin_break_field_detection_reset (sci_lin_instance_ctrl_t * const p_ctrl) +{ + if (LIN_MODE_SLAVE == p_ctrl->p_cfg->mode) + { + R_SCI0_Type * p_reg = p_ctrl->p_reg; + + /* Enable timer in preparation to receive next header */ + p_reg->TCR = R_SCI0_TCR_TCST_Msk; + + /* Slave Start Frame Detection Start */ + p_reg->CR3 = SCI_LIN_CR3_MASK_SLAVE; + } +} + +/******************************************************************************************************************//** + * Reset any in progress transmission/reception + * + * @param[in] p_ctrl Pointer to LIN instance control block + *********************************************************************************************************************/ +static void r_sci_lin_transfer_state_reset (sci_lin_instance_ctrl_t * const p_ctrl) +{ + /* Reset any in progress transmission/reception */ + p_ctrl->rx_bytes_expected = 0U; + p_ctrl->rx_bytes_received = 0U; + p_ctrl->tx_src_bytes = 0U; + p_ctrl->tx_header_bytes = 0U; + p_ctrl->p_data = NULL; + p_ctrl->p_callback_memory = NULL; + p_ctrl->event = LIN_EVENT_NONE; +} + +/********************************************************************************************************************** + * Interrupt service routines + *********************************************************************************************************************/ + +/******************************************************************************************************************//** + * TXI interrupt processing for LIN mode. TXI interrupt fires when the data in the data register has + * been transferred to the data shift register, and the next data can be written. + * + * @retval none + *********************************************************************************************************************/ +void sci_lin_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear Interrupt Status Flag IR */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Transmit the next byte */ + r_sci_lin_txi_handler(p_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * RXI interrupt processing for LIN mode. RXI interrupt fires when data arrives to the data register. + * + * @retval none + *********************************************************************************************************************/ +void sci_lin_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Process the received data and determine whether there is a callback event present */ + lin_event_t event = r_sci_lin_rxi_handler(p_ctrl); + + /* If callback event occurred, call the callback */ + if (event) + { + r_sci_lin_call_callback(p_ctrl, event); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * TEI interrupt processing for LIN mode. The TEI interrupt fires after the last byte is transmitted on the + * TX pin. + * + * @retval none + *********************************************************************************************************************/ +void sci_lin_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Disable transmission and transmit interrupts */ + p_ctrl->p_reg->SCR &= (uint8_t) ~(R_SCI0_SCR_TE_Msk | R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); + + /* Call user callback */ + if (p_ctrl->event) + { + r_sci_lin_call_callback(p_ctrl, p_ctrl->event); + } + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Reset bit rate measurement hardware state in preparation to receive next start frame (slave only) */ + r_sci_lin_scix3_reset(p_ctrl); +#endif + + /* Reset break field detection in slave mode */ + r_sci_lin_break_field_detection_reset(p_ctrl); + + /* Clear Interrupt Status Flag IR */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * ERI interrupt processing for LIN mode. The ERI interrupt fires when an error that is detectable by the SCI + * hardware occurs. + * + * @retval none + *********************************************************************************************************************/ +void sci_lin_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Determine the error event */ + lin_event_t event = r_sci_lin_eri_handler(p_ctrl); + + /* Call user callback */ + r_sci_lin_call_callback(p_ctrl, event); +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + + /* Reset bit rate measurement hardware state in preparation to receive next start frame (slave only) */ + r_sci_lin_scix3_reset(p_ctrl); +#endif + + /* Reset any in progress transmission/reception */ + r_sci_lin_transfer_state_reset(p_ctrl); + + /* Clear Interrupt Status Flag IR */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * SCIX0 interrupt processing for LIN mode. The SCIX0 interrupt fires when a break field is detected by the + * hardware, signaling the start of a LIN frame. + * + * @retval none + *********************************************************************************************************************/ +void sci_lin_scix0_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Process the break field */ + r_sci_lin_scix0_handler(p_ctrl); + + /* Clear Interrupt Status Flag IR */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/******************************************************************************************************************//** + * SCIX1 interrupt processing for LIN mode. The SCIX1 interrupt fires when a control field 0/1 is matched or + * priority interrupt bit deteced by the hardware + * + * @retval none + *********************************************************************************************************************/ +void sci_lin_scix1_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Process the Control field event */ + lin_event_t event = r_sci_lin_scix1_handler(p_ctrl); + + /* If callback event occurred, call the callback */ + if (event) + { + r_sci_lin_call_callback(p_ctrl, event); + } + + /* Clear Interrupt Status Flag IR */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#if SCI_LIN_BUS_CONFLICT_DETECTION_SUPPORT_ENABLE + +/******************************************************************************************************************//** + * SCIX2 interrupt processing for LIN mode. The SCIX2 interrupt fires when a bus collision detected by the + * hardware + * @retval none + *********************************************************************************************************************/ +void sci_lin_scix2_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Process the bus collisions event */ + lin_event_t event = r_sci_lin_scix2_handler(p_ctrl); + + /* Call user callback */ + r_sci_lin_call_callback(p_ctrl, event); + + /* Reset any in progress transmission/reception */ + r_sci_lin_transfer_state_reset(p_ctrl); + + /* Clear Interrupt Status Flag IR */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if SCI_LIN_AUTO_SYNC_SUPPORT_ENABLE + +/******************************************************************************************************************//** + * SCIX3 interrupt processing for LIN mode auto synchronization during control field 0 reception + * (slave only). + * + * @retval none + *********************************************************************************************************************/ +void sci_lin_scix3_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_lin_instance_ctrl_t * p_ctrl = (sci_lin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Process the edge detect event */ + r_sci_lin_scix3_handler(p_ctrl); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_smci/r_sci_smci.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_smci/r_sci_smci.c new file mode 100644 index 0000000000..1a11023a48 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_smci/r_sci_smci.c @@ -0,0 +1,1193 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sci_smci.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "SMCI" in ASCII. Used to determine if the control block is open. */ +#define SCI_SMCI_OPEN (0x534D4349U) /*literal ascii 'SMCI'*/ + +#define SCI_SMCI_SCI_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE) + +/* The bit rate register is 8-bits, so the maximum value is 255. */ +#define SCI_SMCI_BRR_MAX (255U) + +/* Number of divisors in input clock calculation. */ +#define SCI_SMCI_NUM_DIVISORS (4U) + +#define SCI_SMCI_SSR_ERR_MASK (R_SCI0_SSR_SMCI_PER_Msk | R_SCI0_SSR_SMCI_ERS_Msk | \ + R_SCI0_SSR_SMCI_ORER_Msk) + +#define SCI_SMCI_100_PERCENT_X_1000 (100000) + +#define SCI_SMCI_MAX_BAUD_RATE_ERROR_X_1000 (20000) /* 20 percent Error */ + +#define SCI_SMCI_S_LOOKUP_TABLE_ENTRIES (8) +#define SCI_SMCI_CKS_MASK (0x03) /* only two bits*/ + +/*********************************************************************************************************************** + * Private constants + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_sci_smci_bcp_setting_const_t +{ + uint8_t smr_smci_bcp01 : 2; + uint8_t scmr_bcp2 : 1; + uint16_t bit_clock_conversion_number_s; /* number of base clock cycles S in a 1-bit data transfer, + * referred to as S in HW Manual*/ +} sci_smci_bcp_setting_const_t; + +typedef struct st_sci_smci_ffmax_lut_const_t +{ + uint16_t f_value; + uint32_t freq_max; +} sci_smci_ffmax_lut_const_t; + +typedef enum e_smci_clock_conversion_ratio_s +{ + SMCI_CLOCK_CONVERSION_RATIO_32 = 0U, ///< 32 base clock cycles for 1-bit period + SMCI_CLOCK_CONVERSION_RATIO_64 = 1U, ///< 64 base clock cycles for 1-bit period + SMCI_CLOCK_CONVERSION_RATIO_93 = 2U, ///< 93 base clock cycles for 1-bit period + SMCI_CLOCK_CONVERSION_RATIO_128 = 3U, ///< 128 base clock cycles for 1-bit period + SMCI_CLOCK_CONVERSION_RATIO_186 = 4U, ///< 186 base clock cycles for 1-bit period + SMCI_CLOCK_CONVERSION_RATIO_256 = 5U, ///< 256 base clock cycles for 1-bit period + SMCI_CLOCK_CONVERSION_RATIO_372 = 6U, ///< 372 base clock cycles for 1-bit period + SMCI_CLOCK_CONVERSION_RATIO_512 = 7U, ///< 512 base clock cycles for 1-bit period + SMCI_CLOCK_CONVERSION_RATIO_UNSUPPORTED = 8U, ///< Unsupported Clock Cycles +} smci_clock_conversion_ratio_s_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_sci_irqs_cfg(sci_smci_instance_ctrl_t * const p_ctrl, smci_cfg_t const * const p_cfg); +static void r_sci_smci_config_set(sci_smci_instance_ctrl_t * const p_ctrl, + smci_transfer_mode_t * p_transfer_mode_params); +static fsp_err_t r_sci_smci_brr_calculate(smci_speed_params_t const * const p_speed_params, + uint32_t baud_rate_error_x_1000, + smci_baud_setting_t * const p_baud_setting); +static void r_sci_smci_baud_set(R_SCI0_Type * p_sci_reg, smci_baud_setting_t const * const p_baud_setting); + +void sci_smci_rxi_isr(void); +void sci_smci_txi_isr(void); +void sci_smci_eri_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Base Clock Cycles for 1-bit transfer period information (Smart Card mode) */ + +/* this is just a lookup table for S (which is different than F)*/ + +/* This table is the "Combinations of the SCMR.BCP2 and SMR_SMCI.BCP[1:0] bits" table from the + * SCI section of the relevant hardware manual */ +static const sci_smci_bcp_setting_const_t g_bit_clock_conversion_setting_lut[SCI_SMCI_S_LOOKUP_TABLE_ENTRIES] = +{ + /*bcp01,bcp2,S*/ + {0U, 1U, 32 }, + {1U, 1U, 64 }, + {0U, 0U, 93 }, + {1U, 0U, 128}, + {2U, 0U, 186}, + {3U, 1U, 256}, + {2U, 1U, 372}, + {3U, 0U, 512} +}; + +/* This is "Table 7 — Fi and f (max.) Bits" & from ISO/IEC7816-3 Third edition + * 2006-11-01".. NOTE only the F values that can yield at last one possible supported + * S value are listed. */ +static const sci_smci_ffmax_lut_const_t g_f_value_lut[SMCI_CLOCK_CONVERSION_INTEGER_MAX] = +{ + [0] = {372, 4000000 }, + [1] = {372, 5000000 }, + [2] = {0, 0 }, /* there is no value of the associated f value (558) that the SMCI hardware will support*/ + [3] = {744, 8000000 }, + [4] = {1116, 1200000 }, + [5] = {1488, 1600000 }, + [6] = {1860, 2000000 }, + [7] = {0, 0 }, + [8] = {0, 0 }, + [9] = {512, 5000000 }, + [10] = {768, 7500000 }, + [11] = {1024, 10000000 }, + [12] = {1536, 15000000 }, + [13] = {2048, 20000000 }, + [14] = {0, 0 }, + [15] = {0, 0 } +}; + +static const uint8_t g_d_value_lut[SMCI_BAUDRATE_ADJUSTMENT_INTEGER_MAX] = +{ + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 4, + [4] = 8, + [5] = 16, + [6] = 32, + [7] = 64, + [8] = 12, + [9] = 20, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 +}; + +/* This is the divisor 2^(2n+1) as defined in Table "Relationship between N setting in BRR and bit rate B" + * in the SCI section of the relevant hardware manual */ +static const uint8_t g_clock_div_setting[SCI_SMCI_NUM_DIVISORS] = +{ + 2U, + 8U, + 32U, + 128U +}; + +/* SMCI on SCI HAL API mapping for SMCI interface */ +const smci_api_t g_smci_on_sci = +{ + .open = R_SCI_SMCI_Open, + .close = R_SCI_SMCI_Close, + .write = R_SCI_SMCI_Write, + .read = R_SCI_SMCI_Read, + .transferModeSet = R_SCI_SMCI_TransferModeSet, + .baudSet = R_SCI_SMCI_BaudSet, + .statusGet = R_SCI_SMCI_StatusGet, + .clockControl = R_SCI_SMCI_ClockControl, + .callbackSet = R_SCI_SMCI_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup SCI_SMCI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the Smart Card Interface driver based on the input configurations. The interface stays in the clock-off + * state without enabling reception at the end of this function. ISO7816-3 default communication parameters are used to initial + * ize SMCI port speed and parameters, as the ATR message is always sent in that format. Only if Inverse convention is + * expected should the transfer mode be changed after reset. Implements @ref smci_api_t::open + * + * @param[inout] p_api_ctrl Pointer to SMCI control block that is to be opened + * @param[in] p_cfg Pointer to the config structure that shall be used to set parameters of the SMCI + * baud calculations needed to be have done and set into + * p_cfg->p_extend->p_smci_baud_setting + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to SMCI control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_Open (smci_ctrl_t * const p_api_ctrl, smci_cfg_t const * const p_cfg) +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; + sci_smci_extended_cfg_t * p_ext; + smci_transfer_mode_t comm_params; + +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + + FSP_ERROR_RETURN(SCI_SMCI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); +#endif + + p_ext = (sci_smci_extended_cfg_t *) p_cfg->p_extend; + +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_cfg->p_callback); + FSP_ASSERT(p_ext); + FSP_ASSERT(p_ext->p_smci_baud_setting); + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS_MASK & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + + p_ctrl->p_reg = ((R_SCI0_Type *) (R_SCI0_BASE + (SCI_SMCI_SCI_REG_SIZE * p_cfg->channel))); + p_ctrl->p_cfg = p_cfg; + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + comm_params.protocol = SMCI_PROTOCOL_TYPE_T0; + comm_params.convention = SMCI_CONVENTION_TYPE_DIRECT; + comm_params.gsm_mode = false; + + /* Configure the interrupts. */ + r_sci_irqs_cfg(p_ctrl, p_cfg); + + /* Enable the SCI channel */ + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + + /* Initialize registers as defined in section "Example flow of SCI initialization in smart card interface mode" + * in the SCI section of the relevant hardware manual. */ + r_sci_smci_config_set(p_ctrl, &comm_params); + + p_ctrl->p_tx_src = NULL; + p_ctrl->tx_src_bytes = 0U; + p_ctrl->p_rx_dest = NULL; + p_ctrl->rx_dest_bytes = 0; + p_ctrl->rx_bytes_received = 0; + + /* NOTE: Receiver and its interrupt are enabled at clock out. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->eri_irq); + + /* NOTE: Transmitter and its interrupt are enabled in SCI_SMCI_Write(). */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + + r_sci_smci_baud_set(p_ctrl->p_reg, p_ext->p_smci_baud_setting); + + p_ctrl->open = SCI_SMCI_OPEN; + p_ctrl->smci_state = SMCI_STATE_IDLE_CLOCK_OFF; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref smci_api_t::write + * + * @param[inout] p_api_ctrl Pointer to SMCI control block that is to be opened + * @param[in] p_src Pointer to buffer that will be written out + * @param[in] bytes Number of bytes to be transferred + * + * @retval FSP_SUCCESS Data transmission started successfully. + * @retval FSP_ERR_ASSERTION Pointer to SMCI control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A SMCI transmission is in progress + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + * + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_Write (smci_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; + uint8_t scr; +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_src); + FSP_ASSERT(0U != bytes); + FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(SCI_SMCI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + scr = p_ctrl->p_reg->SCR_SMCI; + + /* disable the receiver ,and enable the receiver*/ + scr &= (uint8_t) ~(R_SCI0_SCR_SMCI_RE_Msk | R_SCI0_SCR_SMCI_RIE_Msk); + scr |= R_SCI0_SCR_SMCI_TE_Msk; + + p_ctrl->p_reg->SCR_SMCI = scr; + + /* The FIFO is not used, so the first write will be done from this function. Subsequent writes will be done + * from txi_isr */ + p_ctrl->tx_src_bytes = bytes - 1; + p_ctrl->p_tx_src = p_src + 1; + + p_ctrl->smci_state = SMCI_STATE_TX_PROGRESSING; + + /* Enable the TX interrupt before putting data in TDR.. also enable RIE as it enables the error intterupts + * that may occur */ + p_ctrl->p_reg->SCR_SMCI |= (R_SCI0_SCR_SMCI_TIE_Msk | R_SCI0_SCR_SMCI_RIE_Msk); + + p_ctrl->p_reg->TDR = *(p_src); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Receiving is done at the isr level as + * there is no FIFO. If 0 is passed in as the length, reception will always invoke the user callback. + * Implements @ref smci_api_t::read + * + * @param[inout] p_api_ctrl Pointer to SMCI control block that is to be opened + * @param[inout] p_dest Pointer to the buffer top be read into + * @param[in] bytes Number of bytes to copy from the SMCI receive register + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to SMCI control block or read buffer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + * + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_Read (smci_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT((p_dest) || (bytes == 0)); + FSP_ERROR_RETURN(SCI_SMCI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((bytes == 0) || (0U == p_ctrl->rx_dest_bytes - p_ctrl->rx_bytes_received), FSP_ERR_IN_USE); +#endif + if (0 == bytes) /* 0 bytes indicate a reset of the read states */ + { + p_ctrl->smci_state = SMCI_STATE_TX_RX_IDLE; + } + +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + FSP_ERROR_RETURN((SMCI_STATE_TX_RX_IDLE == p_ctrl->smci_state), FSP_ERR_IN_USE); +#endif + + /* Transmit and receive interrupts must be disabled to start with */ + /* Disable transmit */ + p_ctrl->p_reg->SCR_SMCI &= (uint8_t) ~(R_SCI0_SCR_SMCI_TIE_Msk | R_SCI0_SCR_SMCI_TE_Msk | R_SCI0_SCR_SMCI_RIE_Msk); + + /* Save the destination address and size for use in rxi_isr. */ + p_ctrl->p_rx_dest = p_dest; + p_ctrl->rx_dest_bytes = bytes; + p_ctrl->rx_bytes_received = 0; + + /* Enable receiver and its interrupt */ + p_ctrl->p_reg->SCR_SMCI |= (R_SCI0_SCR_SMCI_RIE_Msk | R_SCI0_SCR_SMCI_RE_Msk); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the settings of block transfer mode and data transfer convention. The SCMR and SMR_SMCI registers + * will be set according to the input arguments of protocol type, data convention type, and mode. + * Implements @ref smci_api_t::transferModeSet + * + * @param[inout] p_api_ctrl Pointer to SMCI control block that is to be modified + * @param[in] p_transfer_mode_params Pointer to SMCI settings like protocol, convention, and gsm_mode + * + * @warning This terminates any in-progress transmission and reception. + * + * @retval FSP_SUCCESS Transfer mode and data transfer direction was successfully changed. + * @retval FSP_ERR_IN_USE Unable to change transfer mode as device has clock off or is actively RX or TX + * @retval FSP_ERR_ASSERTION Null pointer was passed as a parameter + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_TransferModeSet (smci_ctrl_t * const p_api_ctrl, + smci_transfer_mode_t const * const p_transfer_mode_params) + +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_transfer_mode_params); + + FSP_ERROR_RETURN(SCI_SMCI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + FSP_ERROR_RETURN((SMCI_STATE_IDLE_CLOCK_OFF == p_ctrl->smci_state) || + (SMCI_STATE_TX_RX_IDLE == p_ctrl->smci_state), + FSP_ERR_IN_USE); +#endif + + /* Save SCR configurations except transmit interrupts. Resuming transmission after reconfiguring transfer mode is + * not supported. */ + uint8_t preserved_scr_smci = p_ctrl->p_reg->SCR_SMCI & + (uint8_t) ~((R_SCI0_SCR_SMCI_TIE_Msk) | (R_SCI0_SCR_SMCI_TE_Msk)); + + /* If TX and RX arent disable writing to speed and mode registers wont occure according to datasheet*/ + p_ctrl->p_reg->SCR_SMCI = preserved_scr_smci & (uint8_t) ~(R_SCI0_SCR_SMCI_TE_Msk | R_SCI0_SCR_SMCI_RE_Msk); + p_ctrl->p_tx_src = NULL; + + uint8_t smr_smci = 0; + uint8_t scmr = 0; + + smr_smci = p_ctrl->p_reg->SMR_SMCI; + scmr = p_ctrl->p_reg->SCMR; + + /* Enable parity for SMCI mode */ + smr_smci |= (uint8_t) (R_SCI0_SMR_SMCI_PE_Msk); + + if (SMCI_PROTOCOL_TYPE_T1 == p_transfer_mode_params->protocol) + { + smr_smci |= (uint8_t) (SMCI_PROTOCOL_TYPE_T1 << R_SCI0_SMR_SMCI_BLK_Pos); + } + else + { + smr_smci &= (uint8_t) (~(SMCI_PROTOCOL_TYPE_T1 << R_SCI0_SMR_SMCI_BLK_Pos)); + } + + if (SMCI_CONVENTION_TYPE_DIRECT == p_transfer_mode_params->convention) + { + smr_smci &= (uint8_t) (~R_SCI0_SMR_SMCI_PM_Msk); + scmr &= (uint8_t) (~R_SCI0_SCMR_SINV_Msk); + scmr &= (uint8_t) (~R_SCI0_SCMR_SDIR_Msk); + } + else if (SMCI_CONVENTION_TYPE_INVERSE == p_transfer_mode_params->convention) + { + smr_smci |= R_SCI0_SMR_SMCI_PM_Msk; /* Because the SINV bit of the MCU only inverts data bits D7 to D0, */ + /* write 1 to the PM bit in SMR_SMCI to invert the parity bit for */ + /* both transmission and reception.*/ + scmr |= R_SCI0_SCMR_SINV_Msk; + scmr |= R_SCI0_SCMR_SDIR_Msk; + } + else + { + /* unhandled convention type*/ + } + + /* save off and set thwe GSM mode */ + if (p_transfer_mode_params->gsm_mode) + { + smr_smci |= (uint8_t) (R_SCI0_SMR_SMCI_GM_Msk); + } + else + { + smr_smci &= (uint8_t) (~R_SCI0_SMR_SMCI_GM_Msk); + } + + p_ctrl->p_reg->SMR_SMCI = smr_smci; + p_ctrl->p_reg->SCMR = scmr; + + /* Restore all settings except transmit enable interrupts. */ + /* Keep the receiver on, thats the normal idle state */ + p_ctrl->p_reg->SCR_SMCI = (preserved_scr_smci | R_SCI0_SCR_SMCI_RE_Msk | R_SCI0_SCR_SMCI_RIE_Msk); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate and clock output. p_baud_setting is a pointer to a smci_baud_setting_t structure that needs + * to have already been filled by R_SCI_SMCI_BaudCalculate + * Implements @ref smci_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @param[inout] p_api_ctrl Pointer to SMCI control block that is to be modified + * @param[in] p_baud_setting Pointer to baud setting information to be written to the SMCI hardware registers + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to SMCI control block or p_baud_setting is NUL + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT The p_baud_setting does not seem to be set correctly + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_BaudSet (smci_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN(SCI_SMCI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(((smci_baud_setting_t *) p_baud_setting)->computed_baud_rate != 0, FSP_ERR_INVALID_ARGUMENT); +#endif + + /* Save SCR configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is + * not supported. */ + uint8_t preserved_scr_smci = p_ctrl->p_reg->SCR_SMCI & (uint8_t) ~(R_SCI0_SCR_SMCI_TIE_Msk); + + /* If TX and RX arent disable writing to speed and mode registers wont occure according to datasheet*/ + p_ctrl->p_reg->SCR_SMCI = preserved_scr_smci & (uint8_t) ~(R_SCI0_SCR_SMCI_TE_Msk | R_SCI0_SCR_SMCI_RE_Msk); + + p_ctrl->p_tx_src = NULL; + + /* Apply new baud rate register settings. */ + r_sci_smci_baud_set(p_ctrl->p_reg, p_baud_setting); + + /* Restore all settings except transmit enable interrupts. */ + /* Keep the receiver on, thats the normal idle state */ + p_ctrl->p_reg->SCR_SMCI = (preserved_scr_smci | R_SCI0_SCR_SMCI_RE_Msk | R_SCI0_SCR_SMCI_RIE_Msk); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the state of the driver and the # of bytes received since read was called + * Implements @ref smci_api_t::statusGet + * + * @param[in] p_api_ctrl Pointer to SMCI control block of this SMCI instance + * @param[out] p_status Pointer structure that will be filled in with status info + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to SMCI control block, or info structure is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_StatusGet (smci_ctrl_t * const p_api_ctrl, smci_status_t * const p_status) +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_status); + FSP_ERROR_RETURN(SCI_SMCI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_status->smci_state = p_ctrl->smci_state; + + /* the number of bytes received */ + p_status->bytes_recvd = p_ctrl->rx_bytes_received; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable or disable the clock signal that is provided by interface the baud rate. When the clock is enabled, reception + * is enabled at the end of this function. Clock output control as defined in "Clock Output Control" of + * "Operation in Smart Card Interface Mode" in the SCI section of the relevant hardware manual. + * Implements @ref smci_api_t::clockControl + * + * @warning This terminates any in-progress transmission and reception. + * + * @param[inout] p_api_ctrl Pointer to SMCI control block + * @param[in] clock_enable true=Enable or false=disable the Smart Card Interface clock + * + * @retval FSP_SUCCESS Clock output setting was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to SMCI control block is NULL + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_INVALID_MODE Clock cannot be disabled if GSM mode isnt active + * + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_ClockControl (smci_ctrl_t * const p_api_ctrl, bool clock_enable) +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; + uint8_t smci_temp; +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_SMCI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* only allow clock off in GSM Mode */ + if (clock_enable == false) + { + FSP_ERROR_RETURN((1 == p_ctrl->p_reg->SMR_SMCI_b.GM), FSP_ERR_INVALID_MODE); + } +#endif + smci_temp = p_ctrl->p_reg->SCR_SMCI; + + /* Clock Enable control bit can be written only when TE=0 and RE=0 + * The setting of RIE and TIE are reset because resuming reception or transmission after clock state change is not supported */ + p_ctrl->p_reg->SCR_SMCI = smci_temp & (uint8_t) ~(R_SCI0_SCR_SMCI_RE_Msk | + R_SCI0_SCR_SMCI_TE_Msk | R_SCI0_SCR_SMCI_RIE_Msk | + R_SCI0_SCR_SMCI_TIE_Msk); + + if (clock_enable) + { + /* output clock */ + p_ctrl->p_reg->SCR_SMCI_b.CKE = 1; + + /* enable received transfer as default */ + p_ctrl->p_reg->SCR_SMCI |= R_SCI0_SCR_SMCI_RIE_Msk | R_SCI0_SCR_SMCI_RE_Msk; + p_ctrl->p_reg->SCR_SMCI &= (uint8_t) ~(R_SCI0_SCR_SMCI_TIE_Msk | R_SCI0_SCR_SMCI_TE_Msk); + + /* indicate we are ready to transmit*/ + p_ctrl->smci_state = SMCI_STATE_TX_RX_IDLE; + } + else + { + /* stop clock */ + p_ctrl->p_reg->SCR_SMCI_b.CKE = 0; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements smci_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_CallbackSet (smci_ctrl_t * const p_api_ctrl, + void ( * p_callback)(smci_callback_args_t *), + void * const p_context, + smci_callback_args_t * const p_callback_memory) +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_SMCI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_SMCI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + smci_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(smci_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. + * Implements @ref smci_api_t::close + * + * @param[in] p_api_ctrl Pointer to SMCI control block that is reqested to close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to SMCI control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_Close (smci_ctrl_t * const p_api_ctrl) +{ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) p_api_ctrl; +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_SMCI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + /* Disable interrupts, receiver, and transmitter. Disable baud clock output.*/ + p_ctrl->p_reg->SCR_SMCI = 0U; + + /* Disable reception irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + + /* Disable transmission irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + + /* Enter module stop mode */ + R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. And then updates the SCI registers. + * + * @param[in] p_speed_params structure including speed defining paramets, baud, F, D, and max frequency + * @param[in] baud_rate_error_x_1000 <baud_rate_percent_error> x 1000 required for module to function. + * Absolute max baud_rate_error is 20000 (20%) according to the ISO spec. + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate setting calculation successful + * @retval FSP_ERR_ASSERTION p_speed params or p_baud is a null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', freq is '0', or error in + * calculated baud rate is larger than 20%. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SMCI_BaudCalculate (smci_speed_params_t const * const p_speed_params, + uint32_t baud_rate_error_x_1000, + void * const p_baud_setting) +{ + smci_baud_setting_t * p_baud = (smci_baud_setting_t *) p_baud_setting; + +#if (SCI_SMCI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_speed_params); + FSP_ERROR_RETURN((0U != p_speed_params->baudrate), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != g_f_value_lut[p_speed_params->fi].freq_max), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(SCI_SMCI_MAX_BAUD_RATE_ERROR_X_1000 > baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT); + FSP_ASSERT(p_baud); +#endif + + fsp_err_t err; + + /* Update the SCI baudrate registers configuration. The TE, RE should be set to 0 prior to this step */ + err = r_sci_smci_brr_calculate(p_speed_params, baud_rate_error_x_1000, p_baud); + + if (FSP_SUCCESS != err) + { + p_baud->computed_baud_rate = 0; + } + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_SMCI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info for all interrupts. + * + * @param[in] p_ctrl Pointer to SMCI control block + * @param[in] p_cfg Pointer to SMCI specific configuration structure + **********************************************************************************************************************/ +static void r_sci_irqs_cfg (sci_smci_instance_ctrl_t * const p_ctrl, smci_cfg_t const * const p_cfg) +{ + R_BSP_IrqCfg(p_cfg->eri_irq, p_cfg->eri_ipl, p_ctrl); + R_BSP_IrqCfg(p_cfg->rxi_irq, p_cfg->rxi_ipl, p_ctrl); + R_BSP_IrqCfg(p_cfg->txi_irq, p_cfg->txi_ipl, p_ctrl); +} + +/*******************************************************************************************************************//** + * computes the brr register value required for the given input params + * @param[in] p_speed_params Pointer to structure containing etu definition params + * @param[in] baud_rate_error_x_1000 Allowable baud rate error + * @param[out] p_baud_setting Pointer to structure containing computed values to achieve baud/error rate + * + * @retval FSP_SUCCESS Register settings updated in provided p_baud_setting + * @retval FSP_ERR_INVALID_ARGUMENT Cant achieve output etu/freq with given params + **********************************************************************************************************************/ +static fsp_err_t r_sci_smci_brr_calculate (smci_speed_params_t const * const p_speed_params, + uint32_t baud_rate_error_x_1000, + smci_baud_setting_t * const p_baud_setting) +{ + uint32_t max_baudrate = 0U; + static uint32_t actual_baudrate = 0U; + int32_t hit_bit_err = SCI_SMCI_100_PERCENT_X_1000; + static uint32_t divisor = 0U; + uint32_t f_value = 0U; + uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_SCI_CLOCK); + int32_t err_divisor = 0; + int32_t bit_err = 0; + uint32_t temp_brr = 0; + uint32_t s_value = 0U; + uint8_t s_index = 0; + uint32_t target_baudrate = 0U; + + target_baudrate = p_speed_params->baudrate; + + /* Find the best BRR (bit rate register) value in Smart Card mode */ + + /* first determine if we can get to the spec'd baudrate withe params given*/ + f_value = (uint32_t) g_f_value_lut[p_speed_params->fi].f_value; + + max_baudrate = (g_d_value_lut[p_speed_params->di] * g_f_value_lut[p_speed_params->fi].freq_max) / f_value; + + s_value = f_value / g_d_value_lut[p_speed_params->di]; + if (target_baudrate > max_baudrate) + { + /* Error out if the parameters supplied will not allow the baud rate generated to be within error range */ + FSP_ERROR_RETURN(((((target_baudrate - max_baudrate) * 100000) / max_baudrate) < baud_rate_error_x_1000), + FSP_ERR_INVALID_ARGUMENT); + target_baudrate = max_baudrate; + } + + /* validate that a S value for the given F and D exists on the SMCI hardware*/ + /* find the S value that corresponds, from our look up table */ + while ((s_index < SCI_SMCI_S_LOOKUP_TABLE_ENTRIES) && + (s_value != g_bit_clock_conversion_setting_lut[s_index].bit_clock_conversion_number_s)) + { + s_index++; + } + + FSP_ERROR_RETURN((s_index != SCI_SMCI_S_LOOKUP_TABLE_ENTRIES), FSP_ERR_INVALID_ARGUMENT); + + for (uint8_t cks_value = 0U; + cks_value < (SCI_SMCI_NUM_DIVISORS) && (hit_bit_err > ((int32_t) baud_rate_error_x_1000)); + cks_value++) + { + /* This is the based on smci brr setting as defined in "Relationship between N setting in BRR and bit rate B" + * in the SCI section of the relevant hardware manual */ + divisor = (uint32_t) g_clock_div_setting[cks_value] * target_baudrate * + s_value; + temp_brr = freq_hz / divisor; + + if (temp_brr <= (SCI_SMCI_BRR_MAX + 1U)) + { + if (temp_brr > 0U) + { + temp_brr -= 1U; + + /* Calculate the bit rate error. The formula is as follows: + * bit rate error[%] = {(PCLK / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * calculates bit rate error[%] to three decimal places + */ + err_divisor = (int32_t) (divisor * (temp_brr + 1U)); + + /* Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. (temp_brr + 1) can be off by an upper limit of 1 due to rounding from the calculation: + * freq_hz / divisor, or: + * freq_hz / divisor <= (temp_brr + 1) < (freq_hz / divisor) + 1 + * 2. Solving for err_divisor: + * freq_hz <= err_divisor < freq_hz + divisor + * 3. Solving for bit_err: + * 0 >= bit_err >= (freq_hz * 100000 / (freq_hz + divisor)) - 100000 + * 4. freq_hz >= divisor (or temp_brr would be -1 and we would never enter this while loop), so: + * 0 >= bit_err >= 100000 / freq_hz - 100000 + * 5. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the bit_err approaches -100000, so: + * 0 >= bit_err >= -100000 + * 6. bit_err is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ + bit_err = (int32_t) (((((int64_t) freq_hz) * SCI_SMCI_100_PERCENT_X_1000) / + err_divisor) - SCI_SMCI_100_PERCENT_X_1000); + + /* Bit error will always be > 0 because we are effectively rouding down brr, so we dont need to + * do absolute value */ + + actual_baudrate = + (uint32_t) (freq_hz / + (g_clock_div_setting[cks_value] * s_value * + (temp_brr + 1U))); + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if (bit_err < hit_bit_err) + { + /* look up the settings based on the s_index we found above*/ + p_baud_setting->smr_smci_clock_bits_b.bcp01 = + g_bit_clock_conversion_setting_lut[s_index].smr_smci_bcp01; + p_baud_setting->smr_smci_clock_bits_b.cks = (uint8_t) (cks_value & SCI_SMCI_CKS_MASK); + p_baud_setting->scmr_bcp2 = g_bit_clock_conversion_setting_lut[s_index].scmr_bcp2; + p_baud_setting->brr = (uint8_t) temp_brr; + hit_bit_err = bit_err; + } + } + } + } + + p_baud_setting->computed_baud_rate = actual_baudrate; + FSP_ERROR_RETURN((p_baud_setting->brr > 0), FSP_ERR_INVALID_ARGUMENT); + + /* Return an error if the percent error is larger than the maximum percent error allowed for this instance */ + FSP_ERROR_RETURN((hit_bit_err <= (int32_t) baud_rate_error_x_1000), FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Changes baud rate based on predetermined register settings. + * + * @param[in] p_sci_reg Base pointer for SCI registers + * @param[in] p_baud_setting Pointer to other divisor related settings + * + * @note The transmitter and receiver (TE and RE bits in SCR) must be disabled prior to calling this function. + **********************************************************************************************************************/ +static void r_sci_smci_baud_set (R_SCI0_Type * p_sci_reg, smci_baud_setting_t const * const p_baud_setting) +{ + uint8_t smr_smci = + (p_sci_reg->SMR_SMCI) & (uint8_t) + ~((R_SCI0_SMR_SMCI_BCP_Msk | R_SCI0_SMR_SMCI_CKS_Msk)); + + /* Set Base Clock Pulse 0, 1 */ + /* and Clock Select */ + smr_smci |= + (uint8_t) (((uint8_t) ((p_baud_setting->smr_smci_clock_bits_b.bcp01 << R_SCI0_SMR_SMCI_BCP_Pos) & + (uint8_t) R_SCI0_SMR_SMCI_BCP_Msk) | + ((uint8_t) ((p_baud_setting->smr_smci_clock_bits_b.cks << R_SCI0_SMR_SMCI_CKS_Pos) & + (uint8_t) R_SCI0_SMR_SMCI_CKS_Msk)))); + + p_sci_reg->SMR_SMCI = smr_smci; + + /* Set Base Clock Pulse 2 */ + p_sci_reg->SCMR_b.BCP2 = p_baud_setting->scmr_bcp2; + + /* Set the BRR */ + p_sci_reg->BRR = p_baud_setting->brr; +} + +/*******************************************************************************************************************//** + * Configures SCI related registers for Smart Card mode. + * + * @param[in] p_ctrl Pointer to SMCI control structure + * @param[in] p_transfer_mode_params Pointer to SMCI specific comm parameters + **********************************************************************************************************************/ +static void r_sci_smci_config_set (sci_smci_instance_ctrl_t * const p_ctrl, + smci_transfer_mode_t * p_transfer_mode_params) +{ + /* Stop communication and initialize CKE - Set TIE, RIE, TE, RE, TEIE, CKE to 0 */ + p_ctrl->p_reg->SCR_SMCI = 0U; + + p_ctrl->p_reg->SIMR1 = 0U; /* ensure iic mode is not selected */ + + /* Set to smart card interface mode. */ + p_ctrl->p_reg->SIMR1_b.IICM = 0U; + p_ctrl->p_reg->SCMR_b.SMIF = 1; + + /* Write to SSR_SMCI after read SSR_SMCI - Set SSR_SMCI.ORER, ERS, PER to 0*/ + p_ctrl->p_reg->SSR_SMCI = + (p_ctrl->p_reg->SSR_SMCI & + (uint8_t) (~(R_SCI0_SSR_SMCI_ORER_Msk | R_SCI0_SSR_SMCI_ERS_Msk | R_SCI0_SSR_SMCI_PER_Msk))); + + /* Set the transmission or reception format in SPMR - Set SPMR.CKPH, CKPOL */ + p_ctrl->p_reg->SPMR_b.CKPOL = 0U; + p_ctrl->p_reg->SPMR_b.CKPH = 0U; + + /* Set the operation mode and the transmission or reception format in SMR_SMCI. */ + uint8_t smr_smci = p_ctrl->p_reg->SMR_SMCI; + uint8_t scmr = p_ctrl->p_reg->SCMR; + + /* Enable parity for SMCI mode */ + smr_smci |= (uint8_t) (R_SCI0_SMR_SMCI_PE_Msk); + + if (true == p_transfer_mode_params->gsm_mode) + { + smr_smci |= (uint8_t) (R_SCI0_SMR_SMCI_GM_Msk); + } + else + { + smr_smci &= (uint8_t) (~R_SCI0_SMR_SMCI_GM_Msk); + } + + if (SMCI_PROTOCOL_TYPE_T1 == p_transfer_mode_params->protocol) + { + smr_smci |= (uint8_t) (SMCI_PROTOCOL_TYPE_T1 << R_SCI0_SMR_SMCI_BLK_Pos); + } + else + { + smr_smci &= (uint8_t) (~(SMCI_PROTOCOL_TYPE_T1 << R_SCI0_SMR_SMCI_BLK_Pos)); + } + + if (SMCI_CONVENTION_TYPE_DIRECT == p_transfer_mode_params->convention) + { + smr_smci &= (uint8_t) (~R_SCI0_SMR_SMCI_PM_Msk); + scmr &= (uint8_t) (~R_SCI0_SCMR_SINV_Msk); + scmr &= (uint8_t) (~R_SCI0_SCMR_SDIR_Msk); + } + else if (SMCI_CONVENTION_TYPE_INVERSE == p_transfer_mode_params->convention) + { + smr_smci |= (uint8_t) (R_SCI0_SMR_SMCI_PM_Msk); /* need to invert parity as well */ + scmr |= R_SCI0_SCMR_SINV_Msk; + scmr |= R_SCI0_SCMR_SDIR_Msk; + } + else + { + /* unhandled convention type*/ + } + + p_ctrl->p_reg->SEMR = 0; + + p_ctrl->p_reg->SMR_SMCI = smr_smci; + + /* Set the transmission or reception format in to 8-bit mode */ + scmr |= R_SCI0_SCMR_CHR1_Msk; + p_ctrl->p_reg->SCMR = scmr; + + /* Set SPTR to initial value */ + p_ctrl->p_reg->SPTR = (uint8_t) ~(R_SCI0_SPTR_SPB2IO_Msk | R_SCI0_SPTR_RINV_Msk | R_SCI0_SPTR_TINV_Msk); +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SMCI instance control block + * @param[in] data See smci_callback_args_t in r_smci_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_smci_call_callback (sci_smci_instance_ctrl_t * p_ctrl, uint8_t data, smci_event_t event) +{ + smci_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + smci_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_smci_prv_ns_callback p_callback = (sci_smci_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Receiver ISR receives data into the receive buffer or initiates user callback. + * + **********************************************************************************************************************/ +void sci_smci_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint8_t data; + + data = p_ctrl->p_reg->RDR; + + if (0 == (p_ctrl->rx_dest_bytes - p_ctrl->rx_bytes_received)) + { + /* Call user callback with the data. */ + r_sci_smci_call_callback(p_ctrl, data, SMCI_EVENT_RX_CHAR); + } + else + { + *p_ctrl->p_rx_dest = data; + p_ctrl->p_rx_dest += 1; + p_ctrl->rx_bytes_received += 1; + p_ctrl->smci_state = SMCI_STATE_RX_PROGRESSING; + if (0 == p_ctrl->rx_dest_bytes - p_ctrl->rx_bytes_received) + { + p_ctrl->smci_state = SMCI_STATE_TX_RX_IDLE; + r_sci_smci_call_callback(p_ctrl, 0U, SMCI_EVENT_RX_COMPLETE); + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * Transmit ISR, loads the transmit register from the transmit buffer, until all data is sent + * after which callback is initiated + * + **********************************************************************************************************************/ +void sci_smci_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if (0U != p_ctrl->tx_src_bytes) + { + /* Write 1byte (uint8_t) data to (uint8_t) data register */ + p_ctrl->p_reg->TDR = *(p_ctrl->p_tx_src); + + /* Update pointer to the next data and number of remaining bytes in the control block. */ + p_ctrl->tx_src_bytes -= 1; + p_ctrl->p_tx_src += 1; + } + else + { + p_ctrl->p_tx_src = NULL; + p_ctrl->smci_state = SMCI_STATE_TX_RX_IDLE; + + uint8_t scr_temp = p_ctrl->p_reg->SCR_SMCI; + scr_temp &= (uint8_t) ~(R_SCI0_SCR_SMCI_TIE_Msk | R_SCI0_SCR_SMCI_TE_Msk); + scr_temp |= (R_SCI0_SCR_SMCI_RE_Msk); + p_ctrl->p_reg->SCR_SMCI = scr_temp; + + r_sci_smci_call_callback(p_ctrl, 0U, SMCI_EVENT_TX_COMPLETE); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * Error ISR, clears all three error Error Signal Status, Parity Error Flag, and Overrun Error Flag, then initiates + * the callback with an event code + **********************************************************************************************************************/ + +void sci_smci_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_smci_instance_ctrl_t * p_ctrl = (sci_smci_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint8_t data = 0U; + volatile uint8_t forceRead; + smci_event_t event; + + /* Read data. */ + data = p_ctrl->p_reg->RDR; + + event = (smci_event_t) (p_ctrl->p_reg->SSR_SMCI & SCI_SMCI_SSR_ERR_MASK); + + p_ctrl->p_reg->SSR_SMCI &= + (uint8_t) ~(R_SCI0_SSR_SMCI_ORER_Msk | R_SCI0_SSR_SMCI_ERS_Msk | R_SCI0_SSR_SMCI_PER_Msk); + + /* The data sheet says after writing you should readback 0 from the error bit */ + forceRead = p_ctrl->p_reg->SSR_SMCI; + forceRead++; + + /* Call callback. */ + r_sci_smci_call_callback(p_ctrl, data, event); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_spi/r_sci_spi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_spi/r_sci_spi.c new file mode 100644 index 0000000000..7e7ba34a42 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_spi/r_sci_spi.c @@ -0,0 +1,1008 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sci_spi.h" +#include "r_sci_spi_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SCI_SPI_PRV_SCMR_RESERVED_MASK (0x62U) + +#define SCI_SPI_PRV_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << 30U) | (TRANSFER_SIZE_1_BYTE << 28U) | \ + (TRANSFER_ADDR_MODE_FIXED << 26U) | (TRANSFER_IRQ_END << 21U) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << 18U)) + +#define SCI_SPI_PRV_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << 30U) | (TRANSFER_SIZE_1_BYTE << 28U) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << 26U) | (TRANSFER_IRQ_END << 21U) | \ + (TRANSFER_ADDR_MODE_FIXED << 18U)) + +#define SCI_SPI_PRV_CLK_MIN_DIV (4U) +#define SCI_SPI_PRV_CLK_MAX_DIV ((UINT16_MAX + 1U) * 2U) + +/** "SCIS" in ASCII, used to determine if channel is open. */ +#define SCI_SPI_OPEN (0x53434953ULL) + +/*********************************************************************************************************************** + * Private global variables. + **********************************************************************************************************************/ + +const spi_api_t g_spi_on_sci = +{ + .open = R_SCI_SPI_Open, + .read = R_SCI_SPI_Read, + .write = R_SCI_SPI_Write, + .writeRead = R_SCI_SPI_WriteRead, + .close = R_SCI_SPI_Close, + .callbackSet = R_SCI_SPI_CallbackSet +}; + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * sci_spi_prv_ns_callback)(spi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_spi_prv_ns_callback)(spi_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function declarations. + **********************************************************************************************************************/ + +static void r_sci_spi_hw_config(sci_spi_instance_ctrl_t * const p_ctrl); + +#if SCI_SPI_DTC_SUPPORT_ENABLE == 1 +static fsp_err_t r_sci_spi_transfer_config(sci_spi_instance_ctrl_t * const p_ctrl); + +#endif +static fsp_err_t r_sci_spi_write_read_common(sci_spi_instance_ctrl_t * const p_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length); +static void r_sci_spi_start_transfer(sci_spi_instance_ctrl_t * const p_ctrl); +static void r_sci_spi_transmit(sci_spi_instance_ctrl_t * p_ctrl); +static void r_sci_spi_call_callback(sci_spi_instance_ctrl_t * p_ctrl, spi_event_t event); + +void sci_spi_txi_isr(void); +void sci_spi_rxi_isr(void); +void sci_spi_tei_isr(void); +void sci_spi_eri_isr(void); + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup SCI_SPI + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize a channel for SPI communication mode. Implements @ref spi_api_t::open. + * + * This function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Enables the clock for the SCI channel. + * - Initializes the associated registers with default value and the user-configurable options. + * - Provides the channel handle for use with other API functions. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_cfg Pointer to a configuration structure. + * + * @retval FSP_SUCCESS Channel initialized successfully. + * @retval FSP_ERR_ASSERTION An input parameter is invalid or NULL. + * @retval FSP_ERR_ALREADY_OPEN The instance has already been opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel number is invalid. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) +{ + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SCI_SPI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS_MASK & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); +#endif + + p_ctrl->p_reg = (R_SCI0_Type *) ((R_SCI1_BASE - R_SCI0_BASE) * p_cfg->channel + R_SCI0_BASE); + p_ctrl->p_cfg = p_cfg; + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + +#if SCI_SPI_DTC_SUPPORT_ENABLE == 1 + + /* Open the SCI SPI transfer interface if available. */ + err = r_sci_spi_transfer_config(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Write user configuration to registers. */ + r_sci_spi_hw_config(p_ctrl); + + /* Enable required interrupts. */ + R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->rxi_ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->txi_ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->tei_irq, p_cfg->tei_ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_cfg->eri_irq, p_cfg->eri_ipl, p_ctrl); + + p_ctrl->open = SCI_SPI_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Receive data from an SPI device. Implements @ref spi_api_t::read. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Enable transmitter. + * - Enable receiver. + * - Enable interrupts. + * - Start data transmission by writing data to the TXD register. + * - Receive data from receive buffer full interrupt occurs and copy data to the buffer of destination. + * - Complete data reception via receive buffer full interrupt and transmitting dummy data. + * - Disable transmitter. + * - Disable receiver. + * - Disable interrupts. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_dest Pointer to the destination buffer. + * @param[in] length The number of bytes to transfer. + * @param[in] bit_width Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS). + * + * @retval FSP_SUCCESS Read operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_api_ctrl is NULL + * - Bit width is not 8 bits + * - Length is equal to 0 + * - Pointer to destination is NULL + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_UNSUPPORTED The given bit_width is not supported. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * - @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_Read (spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl; + +#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + + /* Check bit_width parameter, in simple SPI, only 8 bits operation is allowed. */ + FSP_ERROR_RETURN(SPI_BIT_WIDTH_8_BITS == bit_width, FSP_ERR_UNSUPPORTED); + + /* Check the destination, should not be NULL. */ + FSP_ASSERT(NULL != p_dest); +#else + FSP_PARAMETER_NOT_USED(bit_width); +#endif + + return r_sci_spi_write_read_common(p_ctrl, NULL, p_dest, length); +} + +/*******************************************************************************************************************//** + * Transmit data to a SPI device. Implements @ref spi_api_t::write. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Enable transmitter. + * - Enable interrupts. + * - Start data transmission with data via transmit buffer empty interrupt. + * - Copy data from source buffer to the SPI data register for transmission. + * - Complete data transmission via transmit buffer empty interrupt. + * - Disable transmitter. + * - Disable receiver. + * - Disable interrupts. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_src Pointer to the source buffer. + * @param[in] length The number of bytes to transfer. + * @param[in] bit_width Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS). + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_api_ctrl is NULL + * - Pointer to source is NULL + * - Length is equal to 0 + * - Bit width is not equal to 8 bits + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_UNSUPPORTED The given bit_width is not supported. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * - @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_Write (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl; + +#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(SPI_BIT_WIDTH_8_BITS == bit_width, FSP_ERR_UNSUPPORTED); + FSP_ASSERT(NULL != p_src); +#else + FSP_PARAMETER_NOT_USED(bit_width); +#endif + + return r_sci_spi_write_read_common(p_ctrl, p_src, NULL, length); +} + +/*******************************************************************************************************************//** + * Simultaneously transmit data to SPI device while receiving data from SPI device (full duplex). + * Implements @ref spi_api_t::writeRead. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Enable transmitter. + * - Enable receiver. + * - Enable interrupts. + * - Start data transmission using transmit buffer empty interrupt (or by writing to the TDR register). + * - Copy data from source buffer to the SPI data register for transmission. + * - Receive data from receive buffer full interrupt and copy data to the destination buffer. + * - Complete data transmission and reception via transmit end interrupt. + * - Disable transmitter. + * - Disable receiver. + * - Disable interrupts. + * + * @param p_api_ctrl Pointer to the control structure. + * @param p_src Pointer to the source buffer. + * @param p_dest Pointer to the destination buffer. + * @param[in] length The number of bytes to transfer. + * @param[in] bit_width Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS). + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_api_ctrl is NULL + * - Pointer to source is NULL + * - Pointer to destination is NULL + * - Length is equal to 0 + * - Bit width is not equal to 8 bits + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_UNSUPPORTED The given bit_width is not supported. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * - @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl; + +#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(SPI_BIT_WIDTH_8_BITS == bit_width, FSP_ERR_UNSUPPORTED); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); +#else + FSP_PARAMETER_NOT_USED(bit_width); +#endif + + return r_sci_spi_write_read_common(p_ctrl, p_src, p_dest, length); +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements spi_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory) +{ + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_SPI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + spi_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(spi_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disable the SCI channel and set the instance as not open. Implements @ref spi_api_t::close. + * + * @param p_api_ctrl Pointer to an opened instance. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION The parameter p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_Close (spi_ctrl_t * const p_api_ctrl) +{ + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl; + +#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SCI_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Clear the RE and TE bits in SCR. */ + p_ctrl->p_reg->SCR = 0; + + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + + /* Disable the clock to the SCI channel. */ + R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel); + + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + + p_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculate the register settings required to achieve the desired bitrate. + * + * @param[in] bitrate bitrate [bps]. For example, 250,000; 500,00; 2,500,000 (max), etc. + * @param sclk_div Pointer to sci_spi_div_setting_t used to configure baudrate settings. + * @param[in] use_mddr Calculate the divider settings for use with MDDR. + * + * @retval FSP_SUCCESS Baud rate is set successfully. + * @retval FSP_ERR_ASSERTION Baud rate is not achievable. + * @note The application must pause for 1 bit time after the BRR register is loaded before transmitting/receiving + * to allow time for the clock to settle. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_CalculateBitrate (uint32_t bitrate, sci_spi_div_setting_t * sclk_div, bool use_mddr) +{ + uint32_t peripheral_clock = R_FSP_SystemClockHzGet(BSP_FEATURE_SCI_CLOCK); + +#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != sclk_div); + FSP_ASSERT(bitrate); + uint32_t clock_max_div = use_mddr ? SCI_SPI_PRV_CLK_MAX_DIV : (SCI_SPI_PRV_CLK_MAX_DIV / 2); + FSP_ASSERT(bitrate >= (peripheral_clock + clock_max_div - 1U) / clock_max_div); +#endif + + int32_t divisor = 0; + int32_t brr = 0; + int32_t cks = -1; + + for (uint32_t i = 0; i <= 3; i++) + { + cks++; + divisor = (1 << (2 * (i + 1))) * (int32_t) bitrate; + + /* Calculate BRR so that the bit rate is the largest possible value less than or equal to the desired + * bitrate. */ + brr = ((int32_t) peripheral_clock + divisor - 1) / divisor - 1; + + if (brr <= UINT8_MAX) + { + break; + } + } + + /* If mddr is not used, set it to 0. */ + int64_t mddr = 0; + + if (use_mddr) + { + /* Calculate BRR by rounding down. */ + brr = (int32_t) peripheral_clock / divisor - 1; + + /* + * If a bit rate greater than the max possible bit rate is passed in, this + * calculation will be negative. + */ + if (brr < 0) + { + brr = 0; + } + + /* In the most extreme case this will result in a bit rate that is ~2 times the + * desired bitrate (This will be compensated for by setting MDDR). + */ + if (brr > UINT8_MAX) + { + brr = UINT8_MAX; + } + + /* The maximum result of this calculation is 256 which occurs when the exact bitrate can be achieved without + * using mddr (promote to 64 bit so the intermediate calculation does not overflow). */ + mddr = (int64_t) divisor * (brr + 1) * (UINT8_MAX + 1) / peripheral_clock; + + if (mddr > UINT8_MAX) + { + /* Set MDDR to 0 to disable it. */ + mddr = 0; + } + } + + sclk_div->brr = (uint8_t) brr; + sclk_div->cks = (uint8_t) (cks & 3); + sclk_div->mddr = (uint8_t) mddr; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_SPI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures SCI registers based on the user configuration. + * @param p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_sci_spi_hw_config (sci_spi_instance_ctrl_t * const p_ctrl) +{ + spi_cfg_t const * p_cfg = p_ctrl->p_cfg; + sci_spi_extended_cfg_t * p_extend = (sci_spi_extended_cfg_t *) p_cfg->p_extend; + + /* Initialize registers to their reset values. */ + uint32_t smr = R_SCI0_SMR_CM_Msk; + uint32_t scr = 0; + uint32_t scmr = (2U << R_SCI0_SCMR_CHR1_Pos) | R_SCI0_SCMR_BCP2_Msk | SCI_SPI_PRV_SCMR_RESERVED_MASK; + uint32_t spmr = 0U; + uint32_t mddr = UINT8_MAX; + uint32_t semr = 0; + + /* Select the baud rate generator clock divider. */ + smr |= (uint32_t) (p_extend->clk_div.cks << R_SCI0_SMR_CKS_Pos); + + if (p_extend->clk_div.mddr > INT8_MAX) + { + /* If a valid MDDR setting is given than enable MDDR. */ + semr |= R_SCI0_SEMR_BRME_Msk; + mddr = p_extend->clk_div.mddr; + } + + if (SPI_MODE_SLAVE == p_cfg->operating_mode) + { + /* Select slave mode. */ + spmr |= R_SCI0_SPMR_MSS_Msk; + + /* Select to use SSLn input pin */ + spmr |= R_SCI0_SPMR_SSE_Msk; + + /* Use external clock for baud rate (Default is on-chip baud rate generator). */ + scr |= (2U << R_SCI0_SCR_CKE_Pos); + } + + if (SPI_CLK_PHASE_EDGE_EVEN == p_cfg->clk_phase) + { + /* In order to get sampling on the even clock edge (CPHA = 1) set SPMR.CKPH to 0. */ + if (SPI_CLK_POLARITY_LOW == p_cfg->clk_polarity) + { + /* If SPMR.CKPH is set to 0 then CKPOL must be set to 1 to make the clock low during idle (CPOL = 0). + * See "Relation between clock signal and transmit or receive data in simple SPI mode" + * in the SCI section of the relevant hardware manual. */ + spmr |= R_SCI0_SPMR_CKPOL_Msk; + } + } + else + { + /* In order to get sampling on the ODD edge (CPHA = 0) set SPMR.CKPH to 1. */ + spmr |= R_SCI0_SPMR_CKPH_Msk; + + if (SPI_CLK_POLARITY_HIGH == p_cfg->clk_polarity) + { + /* If SPMR.CKPH is set to 1 then CKPOL must be set to 1 to make the clock high during idle (CPOL = 1). + * See "Relation between clock signal and transmit or receive data in simple SPI mode" + * in the SCI section of the relevant hardware manual. */ + spmr |= R_SCI0_SPMR_CKPOL_Msk; + } + } + + if (SPI_BIT_ORDER_MSB_FIRST == p_cfg->bit_order) + { + /* Configure MSB first (Default is LSB). */ + scmr |= R_SCI0_SCMR_SDIR_Msk; + } + + /* Enable Clock for the SCI Channel. */ + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + + /* Clear the RE and TE bits before writing other settings. See "Register Descriptions" + * in the SCI section of the relevant hardware manual. */ + p_ctrl->p_reg->SCR = 0; + + /* Must read SSR in order to clear the RX overflow error. See "Serial Status Register (SSR)" description + * in the SCI section of the relevant hardware manual. */ + p_ctrl->p_reg->SSR; + + /* Clear the error status flags. */ + p_ctrl->p_reg->SSR = (uint8_t) (R_SCI0_SSR_TDRE_Msk | R_SCI0_SSR_TEND_Msk); + + /* Disable fifo mode. See "Example flow of SCI initialization in clock synchronous mode with non-FIFO + * selected" in the SCI section of the relevant hardware manual. */ + p_ctrl->p_reg->FCR = R_SCI0_FCR_RSTRG_Msk | (8U << R_SCI0_FCR_RTRG_Pos); + + /* Write settings to registers. */ + p_ctrl->p_reg->SMR = (uint8_t) smr; + p_ctrl->p_reg->SCR = (uint8_t) scr; + p_ctrl->p_reg->SCMR = (uint8_t) scmr; + p_ctrl->p_reg->BRR = p_extend->clk_div.brr; + p_ctrl->p_reg->MDDR = (uint8_t) mddr; + p_ctrl->p_reg->SEMR = (uint8_t) semr; + p_ctrl->p_reg->SPMR = (uint8_t) spmr; + + /* Set unused registers to their value after reset. */ + p_ctrl->p_reg->SNFR = 0; + p_ctrl->p_reg->SIMR1 = 0; + p_ctrl->p_reg->SIMR2 = 0; + p_ctrl->p_reg->SIMR3 = 0; + p_ctrl->p_reg->CDR = 0; + p_ctrl->p_reg->DCCR = R_SCI0_DCCR_IDSEL_Msk; + p_ctrl->p_reg->SPTR = R_SCI0_SPTR_SPB2DT_Msk; +} + +#if SCI_SPI_DTC_SUPPORT_ENABLE == 1 + +/*******************************************************************************************************************//** + * Configures SCI SPI related transfer drivers (if enabled). + * + * @param[in] p_cfg Pointer to SCI SPI specific configuration structure. + * @param[in] p_fsp_feature FSP feature. + * + * @retval FSP_SUCCESS Operation successfully completed. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_cfg is NULL + * - Interrupt is not enabled + * @retval FSP_ERR_INVALID_ARGUMENT DTC is used for data transmission but not used for data reception or + * vice versa. + **********************************************************************************************************************/ +static fsp_err_t r_sci_spi_transfer_config (sci_spi_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + spi_cfg_t const * const p_cfg = p_ctrl->p_cfg; + + if (NULL != p_cfg->p_transfer_rx) + { + /* Set the initial configuration for the rx transfer instance. */ + transfer_instance_t const * p_transfer = p_cfg->p_transfer_rx; + p_transfer->p_cfg->p_info->transfer_settings_word = SCI_SPI_PRV_DTC_RX_TRANSFER_SETTINGS; + p_transfer->p_cfg->p_info->p_src = (void *) &p_ctrl->p_reg->RDR; + + /* Open the transfer instance. */ + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (NULL != p_cfg->p_transfer_tx) + { + /* Set the initial configuration for the tx transfer instance. */ + transfer_instance_t const * p_transfer = p_cfg->p_transfer_tx; + p_transfer->p_cfg->p_info->transfer_settings_word = SCI_SPI_PRV_DTC_TX_TRANSFER_SETTINGS; + p_transfer->p_cfg->p_info->p_dest = (void *) &p_ctrl->p_reg->TDR; + + /* Open the transfer instance. */ + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + if (FSP_SUCCESS != err) + { + if (NULL != p_cfg->p_transfer_rx) + { + /* If the tx transfer instance could not be opened, close the rx transfer instance. */ + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + + return err; + } + } + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Initiates writ or read process. Common routine used by SPI API write or read functions. + * + * @param[in] p_ctrl Pointer to the control block. + * @param[in] p_src Pointer to data buffer which need to be sent. + * @param[out] p_dest Pointer to buffer where received data will be stored. + * @param[in] length Number of data transactions to be performed. + * + * @retval FSP_SUCCESS Operation successfully completed. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_ASSERTION One of the following invalid parameters passed: + * - Pointer p_ctrl is NULL + * - length == 0 + * - if DTC is used and length > UINT16_MAX + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * - @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +static fsp_err_t r_sci_spi_write_read_common (sci_spi_instance_ctrl_t * const p_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length) +{ +#if SCI_SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SCI_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(0 != length); + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) || (NULL != p_ctrl->p_cfg->p_transfer_rx)) + { + /* The DTC is only capable of a max of 64K transfers. */ + FSP_ASSERT(length <= UINT16_MAX); + } +#endif + + /* TE and RE must be zero in order to write one to TE or RE (TE and RE will only be set if there is a transfer in + * progress. See "Serial Control Register (SCR)" description in the SCI section of the relevant hardware manual.) */ + FSP_ERROR_RETURN(0 == (p_ctrl->p_reg->SCR & (R_SCI0_SCR_RE_Msk | R_SCI0_SCR_TE_Msk)), FSP_ERR_IN_USE); + + /* Setup the control block. */ + p_ctrl->count = length; + p_ctrl->tx_count = 0U; + p_ctrl->rx_count = 0U; + p_ctrl->p_src = (uint8_t *) p_src; + p_ctrl->p_dest = (uint8_t *) p_dest; + +#if SCI_SPI_DTC_SUPPORT_ENABLE == 1 + if (p_ctrl->p_cfg->p_transfer_tx) + { + /* Configure the tx transfer instance. */ + p_ctrl->tx_count = length; + transfer_instance_t const * p_transfer = p_ctrl->p_cfg->p_transfer_tx; + p_transfer->p_cfg->p_info->length = (uint16_t) length; + + if (NULL == p_src) + { + /* If the source is NULL transmit using a dummy value using FIXED mode. */ + static uint8_t tx_dummy = 0; + p_transfer->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_transfer->p_cfg->p_info->p_src = &tx_dummy; + } + else + { + p_transfer->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_transfer->p_cfg->p_info->p_src = p_src; + } + + /* Enable the transfer instance. */ + fsp_err_t err = p_transfer->p_api->reconfigure(p_transfer->p_ctrl, p_transfer->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + /* The rx transfer instance is not used if p_dest is NULL. */ + if ((NULL != p_ctrl->p_cfg->p_transfer_rx) && (NULL != p_dest)) + { + /* Configure the rx transfer instance. */ + p_ctrl->rx_count = length; + transfer_instance_t const * p_transfer = p_ctrl->p_cfg->p_transfer_rx; + + /* Enable the transfer instance. */ + fsp_err_t err = p_transfer->p_api->reset(p_transfer->p_ctrl, NULL, p_dest, (uint16_t) length); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif + + /* Enable transmit and receive interrupts. */ + r_sci_spi_start_transfer(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables and disables Receive and Transmit mode based on the current configuration. + * + * @param p_ctrl Pointer to control structure. + **********************************************************************************************************************/ +static void r_sci_spi_start_transfer (sci_spi_instance_ctrl_t * const p_ctrl) +{ + /* TE must always be enabled even when receiving data. When RE is enabled without also enabling TE, the SCI will + * continue transferring data until the RE bit is cleared. At high bitrates, it is not possible to clear the RE bit + * fast enough and there will be additional clock pulses at the end of the transfer. */ + uint32_t interrupt_settings = R_SCI0_SCR_TE_Msk; + + if ((NULL == p_ctrl->p_dest) || (NULL != p_ctrl->p_cfg->p_transfer_tx) || (NULL != p_ctrl->p_cfg->p_transfer_rx)) + { + /* Enable the transmit IRQ. */ + interrupt_settings |= R_SCI0_SCR_TIE_Msk; + } + + if (NULL != p_ctrl->p_dest) + { + /* Enable Receive mode and the Receive buffer full IRQ. */ + interrupt_settings |= (R_SCI0_SCR_RE_Msk | R_SCI0_SCR_RIE_Msk); + } + + /* Write the transfer settings. */ + p_ctrl->p_reg->SCR |= (uint8_t) interrupt_settings; + + /* Transmit from RXI interrupt. */ + if ((NULL == p_ctrl->p_cfg->p_transfer_tx) && (NULL == p_ctrl->p_cfg->p_transfer_rx) && (NULL != p_ctrl->p_dest)) + { + /* The rxi interrupt must be disabled so that r_sci_spi_transmit is not interrupted before it updates the + * tx_count. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + + /* When transmitting from the RXI interrupt, the first byte must be written here because the transmit buffer + * empty IRQ is disabled. */ + r_sci_spi_transmit(p_ctrl); + + if ((SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode) && (1 < p_ctrl->count)) + { + /* First call writes directly to the TSR register. The second call writes to the TDR register. */ + r_sci_spi_transmit(p_ctrl); + } + + /* In master mode the rxi interrupt will fire as soon as it is enabled. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->rxi_irq); + } +} + +/*******************************************************************************************************************//** + * Transmit a single byte of data. + * @param p_ctrl Pointer to the control structure. + **********************************************************************************************************************/ +static void r_sci_spi_transmit (sci_spi_instance_ctrl_t * p_ctrl) +{ + if (p_ctrl->tx_count < p_ctrl->count) + { + if (p_ctrl->p_src) + { + p_ctrl->p_reg->TDR = p_ctrl->p_src[p_ctrl->tx_count]; + } + else + { + /* Do a dummy write if there is no tx buffer. */ + p_ctrl->p_reg->TDR = 0; + } + + p_ctrl->tx_count++; + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SPI instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_spi_call_callback (sci_spi_instance_ctrl_t * p_ctrl, spi_event_t event) +{ + spi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + spi_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_spi_prv_ns_callback p_callback = (sci_spi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * This function is the ISR handler for R_SCI_SPI Transmit Buffer Empty IRQ. + * + * The Transmit Buffer Empty IRQ is enabled in the following conditions: + * - The transfer is started using R_SCI_SPI_Write API (There is no data to receive). + * - The rxi IRQ is serviced using a DTC instance. + * - The txi IRQ is serviced using a DTC instance (The interrupt will fire on the last byte transferred). + * + **********************************************************************************************************************/ +void sci_spi_txi_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Write the next byte to the TDR register. */ + r_sci_spi_transmit(p_ctrl); + + if ((p_ctrl->tx_count == p_ctrl->count) && (NULL == p_ctrl->p_dest)) + { + /* If the last byte is transmitted and there is no data to receive then enable the transmit end IRQ and disable + * the transmit IRQ. */ + p_ctrl->p_reg->SCR = (uint8_t) ((p_ctrl->p_reg->SCR & ~R_SCI0_SCR_TIE_Msk) | R_SCI0_SCR_TEIE_Msk); + } + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * This function is the ISR handler for R_SCI_SPI Receive Buffer Full IRQ. + * This handler also handles Transmit Buffer Empty IRQs. + * + * The Receive Buffer Full IRQ is enabled in the following conditions: + * - The transfer is started using either the R_SCI_SPI_Read or R_SCI_SPI_WriteRead API. + * + **********************************************************************************************************************/ +void sci_spi_rxi_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Write the next byte to the TDR register + * (Whenever the rxi isr is enabled, the transmit isr is disabled and transmit is handled here). */ + r_sci_spi_transmit(p_ctrl); + + /* Read the next byte from the RDR register. */ + if (p_ctrl->rx_count < p_ctrl->count) + { + p_ctrl->p_dest[p_ctrl->rx_count++] = p_ctrl->p_reg->RDR; + } + + if (p_ctrl->rx_count == p_ctrl->count) + { + /* If the last byte is received then enable the transmit end IRQ and disable the receive and transmit IRQs. */ + p_ctrl->p_reg->SCR = + (uint8_t) ((p_ctrl->p_reg->SCR & ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_RIE_Msk)) | R_SCI0_SCR_TEIE_Msk); + } + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * This function is the ISR handler for R_SCI_SPI Transmit End IRQ. + * + * The Transmit End IRQ is enabled after the last byte of data has been transferred. + * + **********************************************************************************************************************/ +void sci_spi_tei_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Disables receiver, transmitter and transmit end IRQ. */ + p_ctrl->p_reg->SCR &= (uint8_t) R_SCI0_SCR_CKE_Msk; + + /* Notify the user that the transfer has completed. */ + r_sci_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * This function is the ISR handler for R_SCI_SPI Error IRQs. + * + * This handler is only enabled if the user passes in a valid IRQ number in Pointer to a configuration structure. + * structure. + **********************************************************************************************************************/ +void sci_spi_eri_isr (void) +{ + /* Save context if RTOS is used. */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Disables receiver, transmitter and transmit end IRQ. */ + p_ctrl->p_reg->SCR &= (uint8_t) R_SCI0_SCR_CKE_Msk; + + /* Must read SSR in order to clear the RX overflow error. See "Serial Status Register (SSR)" description + * in the SCI section of the relevant hardware manual. */ + p_ctrl->p_reg->SSR; + + /* Clear the error status flags (The only possible error is an RX overflow). */ + p_ctrl->p_reg->SSR = (uint8_t) (R_SCI0_SSR_TDRE_Msk | R_SCI0_SSR_TEND_Msk); + + /* Notify the user that an error occurred. */ + r_sci_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting. */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used. */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_uart/r_sci_uart.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_uart/r_sci_uart.c new file mode 100644 index 0000000000..2427818a91 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sci_uart/r_sci_uart.c @@ -0,0 +1,2028 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sci_uart.h" +#include + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef SCI_UART_CFG_RX_ENABLE + #define SCI_UART_CFG_RX_ENABLE 1 +#endif +#ifndef SCI_UART_CFG_TX_ENABLE + #define SCI_UART_CFG_TX_ENABLE 1 +#endif + +/* Number of divisors in the data table used for baud rate calculation. */ +#define SCI_UART_NUM_DIVISORS_ASYNC (13U) + +/* Valid range of values for the modulation duty register is 128 - 256 (256 = modulation disabled). */ +#define SCI_UART_MDDR_MIN (128U) +#define SCI_UART_MDDR_MAX (256U) + +/* The bit rate register is 8-bits, so the maximum value is 255. */ +#define SCI_UART_BRR_MAX (255U) + +/* No limit to the number of bytes to read or write if DTC is not used. */ +#define SCI_UART_MAX_READ_WRITE_NO_DTC (0xFFFFFFFFU) + +/* Mask of invalid data bits in 9-bit mode. */ +#define SCI_UART_ALIGN_2_BYTES (0x1U) + +/* "SCIU" in ASCII. Used to determine if the control block is open. */ +#define SCI_UART_OPEN (0x53434955U) + +#define SCI_UART_SCMR_DEFAULT_VALUE (0xF2U) +#define SCI_UART_BRR_DEFAULT_VALUE (0xFFU) +#define SCI_UART_MDDR_DEFAULT_VALUE (0xFFU) +#define SCI_UART_FCR_DEFAULT_VALUE (0xF800) +#define SCI_UART_DCCR_DEFAULT_VALUE (0x40U) + +#define SCI_UART_FIFO_DAT_MASK (0x1FFU) + +#define FRDR_TDAT_MASK_9BITS (0x01FFU) +#define SPTR_SPB2D_BIT (1U) +#define SPTR_OUTPUT_ENABLE_MASK (0x04U) + +#define SCI_UART_SSR_FIFO_DR_RDF (0x41) + +#define SCI_UART_SPMR_CTSE_OFFSET (1U) + +/* SCI SCR register bit masks */ +#define SCI_SCR_TEIE_MASK (0x04U) ///< Transmit End Interrupt Enable +#define SCI_SCR_RE_MASK (0x10U) ///< Receive Enable +#define SCI_SCR_TE_MASK (0x20U) ///< Transmit Enable +#define SCI_SCR_RIE_MASK (0x40U) ///< Receive Interrupt Enable +#define SCI_SCR_TIE_MASK (0x80U) ///< Transmit Interrupt Enable + +/* SCI SEMR register bit offsets */ +#define SCI_UART_SEMR_BRME_OFFSET (2U) +#define SCI_UART_SEMR_ABCSE_OFFSET (3U) +#define SCI_UART_SEMR_ABCS_OFFSET (4U) +#define SCI_UART_SEMR_BGDM_OFFSET (6U) +#define SCI_UART_SEMR_BAUD_SETTING_MASK ((1U << SCI_UART_SEMR_BRME_OFFSET) | \ + (1U << SCI_UART_SEMR_ABCSE_OFFSET) | \ + (1U << SCI_UART_SEMR_ABCS_OFFSET) | (1U << SCI_UART_SEMR_BGDM_OFFSET)) + +/* SCI SMR register bit masks */ +#define SCI_SMR_CKS_VALUE_MASK (0x03U) ///< CKS: 2 bits + +/* SCI SSR register receiver error bit masks */ +#define SCI_SSR_ORER_MASK (0x20U) ///< overflow error +#define SCI_SSR_FER_MASK (0x10U) ///< framing error +#define SCI_SSR_PER_MASK (0x08U) ///< parity err +#define SCI_SSR_FIFO_RESERVED_MASK (0x02U) ///< Reserved bit mask for SSR_FIFO register +#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK) + +#define SCI_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE) + +#define SCI_UART_INVALID_8BIT_PARAM (0xFFU) +#define SCI_UART_INVALID_16BIT_PARAM (0xFFFFU) + +#define SCI_UART_DTC_MAX_TRANSFER (0x10000U) + +#define SCI_UART_FCR_TRIGGER_MASK (0xF) +#define SCI_UART_FCR_RSTRG_OFFSET (12) +#define SCI_UART_FCR_RTRG_OFFSET (8) +#define SCI_UART_FCR_TTRG_OFFSET (4) +#define SCI_UART_FCR_RESET_TX_RX (0x6) + +#define SCI_UART_9BIT_TRANSFER_BUFFER_OFFSET (0xB) +#define SCI_UART_FIFO_TRANSFER_BUFFER_OFFSET (0xC) + +#define SCI_UART_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#define SCI_UART_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) +#ifndef SCI_UART_FLOW_CONTROL_ACTIVE + #define SCI_UART_FLOW_CONTROL_ACTIVE BSP_IO_LEVEL_HIGH +#endif + +#ifndef SCI_UART_FLOW_CONTROL_INACTIVE + #define SCI_UART_FLOW_CONTROL_INACTIVE BSP_IO_LEVEL_LOW +#endif + +/*********************************************************************************************************************** + * Private constants + **********************************************************************************************************************/ +static const int32_t SCI_UART_100_PERCENT_X_1000 = 100000; +static const int32_t SCI_UART_MDDR_DIVISOR = 256; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) +static const uint32_t SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 = 15000; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_baud_setting_const_t +{ + uint8_t bgdm : 1; /**< BGDM value to get divisor */ + uint8_t abcs : 1; /**< ABCS value to get divisor */ + uint8_t abcse : 1; /**< ABCSE value to get divisor */ + uint8_t cks : 2; /**< CKS value to get divisor (CKS = N) */ +} baud_setting_const_t; + +/* Noise filter setting definition */ +typedef enum e_noise_cancel_lvl +{ + NOISE_CANCEL_LVL1, /**< Noise filter level 1(weak) */ + NOISE_CANCEL_LVL2, /**< Noise filter level 2 */ + NOISE_CANCEL_LVL3, /**< Noise filter level 3 */ + NOISE_CANCEL_LVL4 /**< Noise filter level 4(strong) */ +} noise_cancel_lvl_t; + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * sci_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static void r_sci_negate_de_pin(sci_uart_instance_ctrl_t const * const p_ctrl); + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_sci_read_write_param_check(sci_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + +#endif + +#if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT +static void r_sci_irda_enable(sci_uart_extended_cfg_t const * const p_extended); +static void r_sci_irda_disable(sci_uart_extended_cfg_t const * const p_extended); + + #endif +#endif + +static void r_sci_uart_config_set(sci_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +#if SCI_UART_CFG_DTC_SUPPORTED +static fsp_err_t r_sci_uart_transfer_configure(sci_uart_instance_ctrl_t * const p_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t address); + +static fsp_err_t r_sci_uart_transfer_open(sci_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +static void r_sci_uart_transfer_close(sci_uart_instance_ctrl_t * p_ctrl); + +#endif + +static void r_sci_uart_baud_set(R_SCI0_Type * p_sci_reg, baud_setting_t const * const p_baud_setting); +static void r_sci_uart_call_callback(sci_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); + +#if SCI_UART_CFG_FIFO_SUPPORT +static void r_sci_uart_fifo_cfg(sci_uart_instance_ctrl_t * const p_ctrl); + +#endif + +static void r_sci_irq_cfg(sci_uart_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const p_irq); + +static void r_sci_irqs_cfg(sci_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + +#if (SCI_UART_CFG_TX_ENABLE) +void r_sci_uart_write_no_transfer(sci_uart_instance_ctrl_t * const p_ctrl); + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) +void r_sci_uart_rxi_read_no_transfer(sci_uart_instance_ctrl_t * const p_ctrl); + +void sci_uart_rxi_isr(void); + +void r_sci_uart_read_data(sci_uart_instance_ctrl_t * const p_ctrl, uint32_t * const p_data); + +void sci_uart_eri_isr(void); + +#endif + +#if (SCI_UART_CFG_TX_ENABLE) +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/* Baud rate divisor information (UART mode) */ +static const baud_setting_const_t g_async_baud[SCI_UART_NUM_DIVISORS_ASYNC] = +{ + {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ + {1U, 1U, 0U, 0U}, + {1U, 0U, 0U, 0U}, + {0U, 0U, 1U, 1U}, + {0U, 0U, 0U, 0U}, + {1U, 0U, 0U, 1U}, + {0U, 0U, 1U, 2U}, + {0U, 0U, 0U, 1U}, + {1U, 0U, 0U, 2U}, + {0U, 0U, 1U, 3U}, + {0U, 0U, 0U, 2U}, + {1U, 0U, 0U, 3U}, + {0U, 0U, 0U, 3U} +}; + +static const uint16_t g_div_coefficient[SCI_UART_NUM_DIVISORS_ASYNC] = +{ + 6U, + 8U, + 16U, + 24U, + 32U, + 64U, + 96U, + 128U, + 256U, + 384U, + 512U, + 1024U, + 2048U, +}; + +/* UART on SCI HAL API mapping for UART interface */ +const uart_api_t g_uart_on_sci = +{ + .open = R_SCI_UART_Open, + .close = R_SCI_UART_Close, + .write = R_SCI_UART_Write, + .read = R_SCI_UART_Read, + .infoGet = R_SCI_UART_InfoGet, + .baudSet = R_SCI_UART_BaudSet, + .communicationAbort = R_SCI_UART_Abort, + .callbackSet = R_SCI_UART_CallbackSet, + .readStop = R_SCI_UART_ReadStop, + .receiveSuspend = R_SCI_UART_ReceiveSuspend, + .receiveResume = R_SCI_UART_ReceiveResume, +}; + +/*******************************************************************************************************************//** + * @addtogroup SCI_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is + * enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_INVALID_ARGUMENT Flow control is enabled but flow control pin is not defined or selected channel + * does not support "Hardware CTS and Hardware RTS" flow control. + * (or) restricted channel is selected. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_CHANNEL IrDA is requested for a channel that does not support IrDA. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg) +{ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(((sci_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting); + FSP_ERROR_RETURN(SCI_UART_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS_MASK & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + if (((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control == SCI_UART_FLOW_CONTROL_CTSRTS) + { + FSP_ERROR_RETURN( + ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control_pin != SCI_UART_INVALID_16BIT_PARAM, + FSP_ERR_INVALID_ARGUMENT); + } + + if (((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control == SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS) + { + FSP_ERROR_RETURN((0U != (((1U << (p_cfg->channel)) & BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK))), + FSP_ERR_INVALID_ARGUMENT); + } + + #if (SCI_UART_CFG_RS485_SUPPORT) + if (((sci_uart_extended_cfg_t *) p_cfg->p_extend)->rs485_setting.enable == SCI_UART_RS485_ENABLE) + { + FSP_ERROR_RETURN( + ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->rs485_setting.de_control_pin != SCI_UART_INVALID_16BIT_PARAM, + FSP_ERR_INVALID_ARGUMENT); + } + #endif + + #if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT + if (((sci_uart_extended_cfg_t *) p_cfg->p_extend)->irda_setting.ircr_bits_b.ire) + { + FSP_ERROR_RETURN(BSP_FEATURE_SCI_IRDA_CHANNEL_MASK & (1 << p_cfg->channel), FSP_ERR_INVALID_CHANNEL); + } + #endif + #endif + + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); +#endif + + /* Verify that the selected channel is not among the restricted channels when ABCSE is 1. Refer "Limitations" section of r_sci_uart module in FSP User Manual */ + FSP_ERROR_RETURN(!((BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK & (1 << p_cfg->channel)) && + ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting->semr_baudrate_bits_b.abcse), + FSP_ERR_INVALID_ARGUMENT); + + p_ctrl->p_reg = ((R_SCI0_Type *) (R_SCI0_BASE + (SCI_REG_SIZE * p_cfg->channel))); + + p_ctrl->fifo_depth = 0U; +#if SCI_UART_CFG_FIFO_SUPPORT + + /* Check if the channel supports fifo */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK & (1U << p_cfg->channel)) + { + p_ctrl->fifo_depth = BSP_FEATURE_SCI_UART_FIFO_DEPTH; + } +#endif + + p_ctrl->p_cfg = p_cfg; + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + p_ctrl->data_bytes = 1U; + if (UART_DATA_BITS_9 == p_cfg->data_bits) + { + p_ctrl->data_bytes = 2U; + } + + /* Configure the interrupts. */ + r_sci_irqs_cfg(p_ctrl, p_cfg); + +#if SCI_UART_CFG_DTC_SUPPORTED + + /* Configure the transfer interface for transmission and reception if provided. */ + fsp_err_t err = r_sci_uart_transfer_open(p_ctrl, p_cfg); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Negate driver enable if RS-485 mode is enabled. */ + r_sci_negate_de_pin(p_ctrl); + +#if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT + + /* Set the IrDA configuration settings provided in ::sci_uart_extended_cfg_t. */ + r_sci_irda_enable(p_cfg->p_extend); + #endif +#endif + + /* Enable the SCI channel */ + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + + /* Initialize registers as defined in section "SCI Initialization in Asynchronous Mode" + * in the relevant hardware manual */ + p_ctrl->p_reg->SCR = 0U; + p_ctrl->p_reg->SSR = 0U; + p_ctrl->p_reg->SIMR1 = 0U; + p_ctrl->p_reg->SIMR2 = 0U; + p_ctrl->p_reg->SIMR3 = 0U; + p_ctrl->p_reg->CDR = 0U; + + /* Check if the channel supports address matching */ + if (BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS_MASK & (1U << p_cfg->channel)) + { + p_ctrl->p_reg->DCCR = SCI_UART_DCCR_DEFAULT_VALUE; + } + + /* Set the default level of the TX pin to 1. */ + p_ctrl->p_reg->SPTR = (uint8_t) (1U << SPTR_SPB2D_BIT) | SPTR_OUTPUT_ENABLE_MASK; + + /* Set the UART configuration settings provided in ::uart_cfg_t and ::sci_uart_extended_cfg_t. */ + r_sci_uart_config_set(p_ctrl, p_cfg); + + p_ctrl->p_tx_src = NULL; + p_ctrl->tx_src_bytes = 0U; + p_ctrl->p_rx_dest = NULL; + p_ctrl->rx_dest_bytes = 0; + + sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend; + + uint32_t scr = ((uint8_t) p_extend->clock) & 0x3U; +#if (SCI_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, enable reception. */ + /* NOTE: Transmitter and its interrupt are enabled in R_SCI_UART_Write(). */ + scr |= SCI_SCR_RE_MASK; + R_BSP_IrqEnable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->eri_irq); + + scr |= SCI_SCR_RIE_MASK; +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqEnable(p_ctrl->p_cfg->tei_irq); + scr |= SCI_SCR_TE_MASK; +#endif + p_ctrl->p_reg->SCR = (uint8_t) scr; + + p_ctrl->flow_pin = p_extend->flow_control_pin; + +#if SCI_UART_CFG_FLOW_CONTROL_SUPPORT + if (p_ctrl->flow_pin != SCI_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_UART_FLOW_CONTROL_INACTIVE); + R_BSP_PinAccessDisable(); + } +#endif + + p_ctrl->open = SCI_UART_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Removes power. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Close (uart_ctrl_t * const p_api_ctrl) +{ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Mark the channel not open so other APIs cannot use it. */ + p_ctrl->open = 0U; + + /* Disable interrupts, receiver, and transmitter. Disable baud clock output.*/ + p_ctrl->p_reg->SCR = 0U; + +#if (SCI_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, disable reception irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); +#endif +#if (SCI_UART_CFG_TX_ENABLE) + + /* If transmission is enabled at build time, disable transmission irqs. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); +#endif + +#if SCI_UART_CFG_DTC_SUPPORTED + + /* Close the lower level transfer instances. */ + r_sci_uart_transfer_close(p_ctrl); +#endif + + /* Remove power to the channel. */ + R_BSP_MODULE_STOP(FSP_IP_SCI, p_ctrl->p_cfg->channel); + + /* Negate driver enable if RS-485 mode is enabled. */ + r_sci_negate_de_pin(p_ctrl); + +#if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT + + /* To disable IrDA. */ + r_sci_irda_disable(p_ctrl->p_cfg->p_extend); + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_INVALID_ARGUMENT Destination address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @retval FSP_ERR_UNSUPPORTED SCI_UART_CFG_RX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + * @note If 9-bit data length is specified at R_SCI_UART_Open call, p_dest must be aligned 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ +#if (SCI_UART_CFG_RX_ENABLE) + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_read_write_param_check(p_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->rx_dest_bytes, FSP_ERR_IN_USE); + #endif + + #if SCI_UART_CFG_DTC_SUPPORTED + + /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + uint32_t size = bytes >> (p_ctrl->data_bytes - 1); + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(size <= SCI_UART_DTC_MAX_TRANSFER); + #endif + err = + p_ctrl->p_cfg->p_transfer_rx->p_api->reset(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, NULL, (void *) p_dest, + (uint16_t) size); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Save the destination address and size for use in rxi_isr. */ + p_ctrl->p_rx_dest = p_dest; + p_ctrl->rx_dest_bytes = bytes; + + return err; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_INVALID_ARGUMENT Source address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UART transmission is in progress + * @retval FSP_ERR_UNSUPPORTED SCI_UART_CFG_TX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + * @note If 9-bit data length is specified at R_SCI_UART_Open call, p_src must be aligned on a 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ +#if (SCI_UART_CFG_TX_ENABLE) + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; + #if SCI_UART_CFG_PARAM_CHECKING_ENABLE || SCI_UART_CFG_DTC_SUPPORTED + fsp_err_t err = FSP_SUCCESS; + #endif + + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_read_write_param_check(p_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE); + #endif + + #if (SCI_UART_CFG_RS485_SUPPORT) + sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* If RS-485 is enabled, then assert the driver enable pin at the start of a write transfer. */ + if (p_extend->rs485_setting.enable) + { + R_BSP_PinAccessEnable(); + + bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH == + p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_HIGH : BSP_IO_LEVEL_LOW; + R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level); + + R_BSP_PinAccessDisable(); + } + #endif + + /* Transmit interrupts must be disabled to start with. */ + p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK); + + /* If the fifo is not used the first write will be done from this function. Subsequent writes will be done + * from txi_isr. */ + #if SCI_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth > 0U) + { + p_ctrl->tx_src_bytes = bytes; + p_ctrl->p_tx_src = p_src; + } + else + #endif + { + p_ctrl->tx_src_bytes = bytes - p_ctrl->data_bytes; + p_ctrl->p_tx_src = p_src + p_ctrl->data_bytes; + } + + #if SCI_UART_CFG_DTC_SUPPORTED + + /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested + * data. */ + if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && p_ctrl->tx_src_bytes) + { + uint32_t data_bytes = p_ctrl->data_bytes; + uint32_t num_transfers = p_ctrl->tx_src_bytes >> (data_bytes - 1); + p_ctrl->tx_src_bytes = 0U; + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(num_transfers <= SCI_UART_DTC_MAX_TRANSFER); + #endif + + err = p_ctrl->p_cfg->p_transfer_tx->p_api->reset(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + (void const *) p_ctrl->p_tx_src, + NULL, + (uint16_t) num_transfers); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Trigger a TXI interrupt. This triggers the transfer instance or a TXI interrupt if the transfer instance is + * not used. */ + p_ctrl->p_reg->SCR |= SCI_SCR_TIE_MASK; + #if SCI_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth == 0U) + #endif + { + /* On channels with no FIFO, the first byte is sent from this function to trigger the first TXI event. This + * method is used instead of setting TE and TIE at the same time as recommended in the hardware manual to avoid + * the one frame delay that occurs when the TE bit is set. */ + if (2U == p_ctrl->data_bytes) + { + p_ctrl->p_reg->FTDRHL = *((uint16_t *) (p_src)) | (uint16_t) ~(SCI_UART_FIFO_DAT_MASK); + } + else + { + p_ctrl->p_reg->TDR = *(p_src); + } + } + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_UART_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + uart_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(uart_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a baud_setting_t structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT Restricted channel is selected. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) +{ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify that the On-Chip baud rate generator is currently selected. */ + FSP_ASSERT((p_ctrl->p_reg->SCR_b.CKE & 0x2) == 0U); +#endif + + /* Verify that the selected channel is not among the restricted channels when ABCSE is 1. Refer "Limitations" section of r_sci_uart module in FSP User Manual */ + FSP_ERROR_RETURN(!((BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS_MASK & (1 << p_ctrl->p_cfg->channel)) && + (((baud_setting_t *) p_baud_setting)->semr_baudrate_bits_b.abcse)), + FSP_ERR_INVALID_ARGUMENT); + + /* Save SCR configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is + * not supported. */ + uint8_t preserved_scr = p_ctrl->p_reg->SCR & (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK); + + /* Disables transmitter and receiver. This terminates any in-progress transmission. */ + p_ctrl->p_reg->SCR = preserved_scr & (uint8_t) ~(SCI_SCR_TE_MASK | SCI_SCR_RE_MASK | SCI_SCR_RIE_MASK); + p_ctrl->p_tx_src = NULL; + + /* Apply new baud rate register settings. */ + r_sci_uart_baud_set(p_ctrl->p_reg, p_baud_setting); + + /* Restore all settings except transmit interrupts. */ + p_ctrl->p_reg->SCR = preserved_scr; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info) +{ +#if SCI_UART_CFG_PARAM_CHECKING_ENABLE || SCI_UART_CFG_DTC_SUPPORTED + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_info); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_info->read_bytes_max = SCI_UART_MAX_READ_WRITE_NO_DTC; + p_info->write_bytes_max = SCI_UART_MAX_READ_WRITE_NO_DTC; + +#if (SCI_UART_CFG_RX_ENABLE) + + /* Store number of bytes that can be read at a time. */ + #if SCI_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_info->read_bytes_max = SCI_UART_DTC_MAX_TRANSFER; + } + #endif +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + + /* Store number of bytes that can be written at a time. */ + #if SCI_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_info->write_bytes_max = SCI_UART_DTC_MAX_TRANSFER; + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) +{ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + if (UART_DIR_TX & communication_to_abort) + { + err = FSP_SUCCESS; + p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK); + #if SCI_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + err = p_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif + + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + /* Reset the transmit fifo */ + p_ctrl->p_reg->FCR_b.TFRST = 1U; + + /* Wait until TFRST cleared after 1 PCLK according to "FIFO Control Register (FCR)" description + * in the SCI section of the relevant hardware manual.*/ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR_b.TFRST, 0U); + } + #endif + p_ctrl->tx_src_bytes = 0U; + + /* Negate driver enable if RS-485 mode is enabled. */ + r_sci_negate_de_pin(p_ctrl); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif +#if (SCI_UART_CFG_RX_ENABLE) + if (UART_DIR_RX & communication_to_abort) + { + err = FSP_SUCCESS; + + p_ctrl->rx_dest_bytes = 0U; + #if SCI_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_ctrl->p_reg->FCR_b.RFRST = 1U; + + /* Wait until RFRST cleared after 1 PCLK according to "FIFO Control Register (FCR)" description + * in the SCI section of the relevant hardware manual.*/ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR_b.RFRST, 0U); + } + #endif + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes) +{ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + *remaining_bytes = p_ctrl->rx_dest_bytes; + p_ctrl->rx_dest_bytes = 0U; + #if SCI_UART_CFG_DTC_SUPPORTED + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + transfer_properties_t transfer_info; + err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + *remaining_bytes = transfer_info.transfer_length_remaining; + } + #endif +#else + + return FSP_ERR_UNSUPPORTED; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. + * @note For limitations of this API, refer to the 'Limitations' section of r_sci_uart module in FSP User Manual. + * + * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. + * @param[in] bitrate_modulation Enable bitrate modulation + * @param[in] baud_rate_error_x_1000 Max baud rate error. At most <baud_rate_percent_error> x 1000 required + * for module to function. Absolute max baud_rate_error is 15000 (15%). + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is set successfully + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', error in calculated baud rate is larger than requested + * max error, or requested max error in baud rate is larger than 15%. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_BaudCalculate (uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + baud_setting_t * const p_baud_setting) +{ +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN(SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 >= baud_rate_error_x_1000, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT); +#endif + + p_baud_setting->brr = SCI_UART_BRR_MAX; + p_baud_setting->semr_baudrate_bits_b.brme = 0U; + p_baud_setting->mddr = SCI_UART_MDDR_MIN; + + /* Find the best BRR (bit rate register) value. + * In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values. Each set of divisors + * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as + * follows and it must be 255 or less: + * BRR = (PCLK / (div_coefficient * baud)) - 1 + */ + int32_t hit_bit_err = SCI_UART_100_PERCENT_X_1000; + uint8_t hit_mddr = 0U; + uint32_t divisor = 0U; + + uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_SCI_CLOCK); + + for (uint32_t select_16_base_clk_cycles = 0U; + select_16_base_clk_cycles <= 1U && (hit_bit_err > ((int32_t) baud_rate_error_x_1000)); + select_16_base_clk_cycles++) + { + for (uint32_t i = 0U; i < SCI_UART_NUM_DIVISORS_ASYNC; i++) + { + /* if select_16_base_clk_cycles == true: Skip this calculation for divisors that are not achievable with 16 base clk cycles per bit. + * if select_16_base_clk_cycles == false: Skip this calculation for divisors that are only achievable without 16 base clk cycles per bit. + */ + if (((uint8_t) select_16_base_clk_cycles) ^ (g_async_baud[i].abcs | g_async_baud[i].abcse)) + { + continue; + } + + divisor = (uint32_t) g_div_coefficient[i] * baudrate; + uint32_t temp_brr = freq_hz / divisor; + + if (temp_brr <= (SCI_UART_BRR_MAX + 1U)) + { + while (temp_brr > 0U) + { + temp_brr -= 1U; + + /* Calculate the bit rate error. The formula is as follows: + * bit rate error[%] = {(PCLK / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * calculates bit rate error[%] to three decimal places + */ + int32_t err_divisor = (int32_t) (divisor * (temp_brr + 1U)); + + /* Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. (temp_brr + 1) can be off by an upper limit of 1 due to rounding from the calculation: + * freq_hz / divisor, or: + * freq_hz / divisor <= (temp_brr + 1) < (freq_hz / divisor) + 1 + * 2. Solving for err_divisor: + * freq_hz <= err_divisor < freq_hz + divisor + * 3. Solving for bit_err: + * 0 >= bit_err >= (freq_hz * 100000 / (freq_hz + divisor)) - 100000 + * 4. freq_hz >= divisor (or temp_brr would be -1 and we would never enter this while loop), so: + * 0 >= bit_err >= 100000 / freq_hz - 100000 + * 5. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the bit_err approaches -100000, so: + * 0 >= bit_err >= -100000 + * 6. bit_err is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ + int32_t bit_err = (int32_t) (((((int64_t) freq_hz) * SCI_UART_100_PERCENT_X_1000) / + err_divisor) - SCI_UART_100_PERCENT_X_1000); + + uint8_t mddr = 0U; + if (bitrate_modulation) + { + /* Calculate the MDDR (M) value if bit rate modulation is enabled, + * The formula to calculate MBBR (from the M and N relationship given in the hardware manual) is as follows + * and it must be between 128 and 255. + * MDDR = ((div_coefficient * baud * 256) * (BRR + 1)) / PCLK */ + mddr = (uint8_t) ((uint32_t) err_divisor / (freq_hz / SCI_UART_MDDR_MAX)); + + /* MDDR value must be greater than or equal to SCI_UART_MDDR_MIN. */ + if (mddr < SCI_UART_MDDR_MIN) + { + break; + } + + /* Adjust bit rate error for bit rate modulation. The following formula is used: + * bit rate error [%] = ((bit rate error [%, no modulation] + 100) * MDDR / 256) - 100 + */ + bit_err = (((bit_err + SCI_UART_100_PERCENT_X_1000) * (int32_t) mddr) / + SCI_UART_MDDR_DIVISOR) - SCI_UART_100_PERCENT_X_1000; + } + + /* Take the absolute value of the bit rate error. */ + if (bit_err < 0) + { + bit_err = -bit_err; + } + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if (bit_err < hit_bit_err) + { + p_baud_setting->semr_baudrate_bits_b.bgdm = g_async_baud[i].bgdm; + p_baud_setting->semr_baudrate_bits_b.abcs = g_async_baud[i].abcs; + p_baud_setting->semr_baudrate_bits_b.abcse = g_async_baud[i].abcse; + p_baud_setting->cks = g_async_baud[i].cks; + p_baud_setting->brr = (uint8_t) temp_brr; + hit_bit_err = bit_err; + hit_mddr = mddr; + } + + if (bitrate_modulation) + { + p_baud_setting->semr_baudrate_bits_b.brme = 1U; + p_baud_setting->mddr = hit_mddr; + } + else + { + break; + } + } + } + } + } + + /* Return an error if the percent error is larger than the maximum percent error allowed for this instance */ + FSP_ERROR_RETURN((hit_bit_err <= (int32_t) baud_rate_error_x_1000), FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Suspend Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_ReceiveSuspend (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Resume Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_ReceiveResume (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_UART) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Negate the DE pin if it is enabled. + * + * @param[in] p_ctrl Pointer to the control block for the channel. + **********************************************************************************************************************/ +static void r_sci_negate_de_pin (sci_uart_instance_ctrl_t const * const p_ctrl) +{ +#if (SCI_UART_CFG_RS485_SUPPORT) + sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* If RS-485 is enabled, then negate the driver enable pin at the end of a write transfer. */ + if (p_extend->rs485_setting.enable) + { + R_BSP_PinAccessEnable(); + + bsp_io_level_t level = SCI_UART_RS485_DE_POLARITY_HIGH == + p_extend->rs485_setting.polarity ? BSP_IO_LEVEL_LOW : BSP_IO_LEVEL_HIGH; + R_BSP_PinWrite(p_extend->rs485_setting.de_control_pin, level); + + R_BSP_PinAccessDisable(); + } + +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif +} + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL + * @retval FSP_ERR_INVALID_ARGUMENT Address is not aligned to 2-byte boundary or size is the odd number when the data + * length is 9-bit + **********************************************************************************************************************/ +static fsp_err_t r_sci_read_write_param_check (sci_uart_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(addr); + FSP_ASSERT(0U != bytes); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + if (2U == p_ctrl->data_bytes) + { + /* Do not allow odd buffer address if data length is 9 bits. */ + FSP_ERROR_RETURN((0U == ((uint32_t) addr & SCI_UART_ALIGN_2_BYTES)), FSP_ERR_INVALID_ARGUMENT); + + /* Do not allow odd number of data bytes if data length is 9 bits. */ + FSP_ERROR_RETURN(0U == (bytes % 2U), FSP_ERR_INVALID_ARGUMENT); + } + + return FSP_SUCCESS; +} + +#endif +#if SCI_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Subroutine to apply common UART transfer settings. + * + * @param[in] p_cfg Pointer to UART specific configuration structure + * @param[in] p_transfer Pointer to transfer instance to configure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer + **********************************************************************************************************************/ +static fsp_err_t r_sci_uart_transfer_configure (sci_uart_instance_ctrl_t * const p_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t sci_buffer_address) +{ + /* Configure the transfer instance, if enabled. */ + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_ctrl); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend); + #endif + transfer_info_t * p_info = p_transfer->p_cfg->p_info; + + /* Casting for compatibility with 7 or 8 bit mode. */ + *p_transfer_reg = sci_buffer_address; + + #if SCI_UART_CFG_FIFO_SUPPORT + if (p_ctrl->fifo_depth > 0U) + { + /* Casting for compatibility with 7 or 8 bit mode. */ + *p_transfer_reg = sci_buffer_address + SCI_UART_FIFO_TRANSFER_BUFFER_OFFSET; + } + #endif + + if (UART_DATA_BITS_9 == p_ctrl->p_cfg->data_bits) + { + p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + + /* Casting for compatibility with 7 or 8 bit mode. */ + *p_transfer_reg = sci_buffer_address + SCI_UART_9BIT_TRANSFER_BUFFER_OFFSET; + } + + fsp_err_t err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +#endif + +#if SCI_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Configures UART related transfer drivers (if enabled). + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer or required interrupt not enabled in vector table + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +static fsp_err_t r_sci_uart_transfer_open (sci_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_UART_CFG_RX_ENABLE) + + /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_rx) + { + transfer_info_t * p_info = p_cfg->p_transfer_rx->p_cfg->p_info; + + p_info->transfer_settings_word = SCI_UART_DTC_RX_TRANSFER_SETTINGS; + + err = + r_sci_uart_transfer_configure(p_ctrl, p_cfg->p_transfer_rx, (uint32_t *) &p_info->p_src, + (uint32_t) &(p_ctrl->p_reg->RDR)); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + #if (SCI_UART_CFG_TX_ENABLE) + + /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_tx) + { + transfer_info_t * p_info = p_cfg->p_transfer_tx->p_cfg->p_info; + + p_info->transfer_settings_word = SCI_UART_DTC_TX_TRANSFER_SETTINGS; + + err = r_sci_uart_transfer_configure(p_ctrl, + p_cfg->p_transfer_tx, + (uint32_t *) &p_info->p_dest, + (uint32_t) &p_ctrl->p_reg->TDR); + + #if (SCI_UART_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_cfg->p_transfer_rx)) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + #endif + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + return err; +} + +#endif + +#if BSP_PERIPHERAL_IRDA_PRESENT + #if SCI_UART_CFG_IRDA_SUPPORT + +/*******************************************************************************************************************//** + * Init IrDA module based on user configurations. + * + * @param[in] p_extended Pointer to extended settings + **********************************************************************************************************************/ +static void r_sci_irda_enable (sci_uart_extended_cfg_t const * const p_extended) +{ + /* The ire bit should only be set for the channel that is IrDA capable */ + if (p_extended->irda_setting.ircr_bits_b.ire) + { + /* Enable the IrDA interface */ + R_BSP_MODULE_START(FSP_IP_IRDA, 0); + + R_IRDA->IRCR = p_extended->irda_setting.ircr_bits; + } +} + +/*******************************************************************************************************************//** + * Stop IrDA module. + * + * @param[in] p_extended Pointer to extended settings + **********************************************************************************************************************/ +static void r_sci_irda_disable (sci_uart_extended_cfg_t const * const p_extended) +{ + /* Only disable IrDA interface on the channel it is enabled. */ + if (p_extended->irda_setting.ircr_bits_b.ire) + { + /* Don't need to clear IRCR as interface is to be disabled. */ + + /* Disable the IrDA interface */ + R_BSP_MODULE_STOP(FSP_IP_IRDA, 0); + } +} + + #endif +#endif + +/*******************************************************************************************************************//** + * Configures UART related registers based on user configurations. + * + * @param[in] p_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_uart_config_set (sci_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ +#if SCI_UART_CFG_FIFO_SUPPORT + + /* Configure FIFO related registers. */ + r_sci_uart_fifo_cfg(p_ctrl); +#else + + /* If fifo support is disabled and the current channel supports fifo make sure it's disabled. */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS_MASK & (1U << p_cfg->channel)) + { + p_ctrl->p_reg->FCR = SCI_UART_FCR_DEFAULT_VALUE; + } +#endif + + /* Configure parity and stop bits. */ + uint32_t smr = (((uint32_t) p_cfg->parity << 4U) | ((uint32_t) p_cfg->stop_bits << 3U)); + uint32_t scmr = SCI_UART_SCMR_DEFAULT_VALUE; + + /* Configure data size. */ + if (UART_DATA_BITS_7 == p_cfg->data_bits) + { + /* Set the SMR.CHR bit & SCMR.CHR1 bit as selected (Character Length) + * Character Length + * (CHR1,CHR) + * (1, 1) Transmit/receive in 7-bit data length*3 + */ + smr |= (1U << 6); + } + else if (UART_DATA_BITS_9 == p_cfg->data_bits) + { + /* Set the SMR.CHR bit & SCMR.CHR1 bit as selected (Character Length) + * Character Length + * (CHR1,CHR) + * (0, 0) Transmit/receive in 9-bit data length + */ + scmr &= ~(1U << 4); + } + else + { + /* Do nothing. Default is 8-bit mode. */ + } + + /* Write to the SMR register. */ + p_ctrl->p_reg->SMR = (uint8_t) smr; + + /* Write to the SCMR register. */ + p_ctrl->p_reg->SCMR = (uint8_t) scmr; + + sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend; + + /* Configure flow control if CTS/RTS flow control is enabled. */ +#if BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS_MASK + if (p_extend->flow_control == SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS) + { + p_ctrl->p_reg->SPMR = R_SCI0_SPMR_CSTPEN_Msk | R_SCI0_SPMR_CTSE_Msk; + } + else +#endif + { + p_ctrl->p_reg->SPMR = ((uint8_t) (p_extend->flow_control << R_SCI0_SPMR_CTSE_Pos) & R_SCI0_SPMR_CTSE_Msk); + } + + uint32_t semr = 0; + + /* Starts reception on falling edge of RXD if enabled in extension (otherwise reception starts at low level + * of RXD). */ + semr |= (p_extend->rx_edge_start & 1U) << 7; + + /* Enables the noise cancellation, fixed to the minimum level, if enabled in the extension. */ + semr |= (p_extend->noise_cancel & 1U) << 5; + + p_ctrl->p_reg->SNFR = NOISE_CANCEL_LVL1; + + if ((SCI_UART_CLOCK_EXT8X == p_extend->clock) || (SCI_UART_CLOCK_EXT16X == p_extend->clock)) + { + /* Use external clock for baud rate */ + p_ctrl->p_reg->BRR = SCI_UART_BRR_DEFAULT_VALUE; + + if (SCI_UART_CLOCK_EXT8X == p_extend->clock) + { + /* Set baud rate as (external clock / 8) */ + semr |= 1U << SCI_UART_SEMR_ABCS_OFFSET; + } + + p_ctrl->p_reg->SEMR = (uint8_t) semr; + } + else + { + p_ctrl->p_reg->SEMR = (uint8_t) semr; + + /* Set the baud rate settings for the internal baud rate generator. */ + r_sci_uart_baud_set(p_ctrl->p_reg, p_extend->p_baud_setting); + } +} + +#if SCI_UART_CFG_FIFO_SUPPORT + +/*******************************************************************************************************************//** + * Resets FIFO related registers. + * + * @param[in] p_ctrl Pointer to UART instance control + * @param[in] p_cfg Pointer to UART configuration structure + **********************************************************************************************************************/ +static void r_sci_uart_fifo_cfg (sci_uart_instance_ctrl_t * const p_ctrl) +{ + if (0U != p_ctrl->fifo_depth) + { + /* Enable the fifo and set the tx and rx reset bits */ + uint32_t fcr = 1U; + + #if (SCI_UART_CFG_RX_ENABLE) + #if SCI_UART_CFG_DTC_SUPPORTED + + /* If DTC is used keep the receive trigger at the default level of 0. */ + if (NULL == p_ctrl->p_cfg->p_transfer_rx) + #endif + { + /* Otherwise, set receive trigger number as configured by the user. */ + sci_uart_extended_cfg_t const * p_extend = p_ctrl->p_cfg->p_extend; + + /* RTRG(Receive FIFO Data Trigger Number) controls when the RXI interrupt will be generated. If data is + * received but the trigger number is not met the RXI interrupt will be generated after 15 ETUs from + * the last stop bit in asynchronous mode. For more information see the FIFO Selected section of "Serial + * Data Reception in Asynchronous Mode" in the SCI section of the relevant hardware manual */ + fcr |= (((p_ctrl->fifo_depth - 1U) & p_extend->rx_fifo_trigger) & SCI_UART_FCR_TRIGGER_MASK) << + SCI_UART_FCR_RTRG_OFFSET; + } + + /* RTS asserts when the amount of received data stored in the fifo is equal or less than this value. */ + fcr |= ((p_ctrl->fifo_depth - 1U) & SCI_UART_FCR_TRIGGER_MASK) << SCI_UART_FCR_RSTRG_OFFSET; + #endif + + /* Set the FCR and reset the fifos. */ + p_ctrl->p_reg->FCR = (uint16_t) (fcr | SCI_UART_FCR_RESET_TX_RX); + + /* Wait for the fifo reset to complete after 1 PCLK according to "FIFO Control Register (FCR)" description + * in the SCI section of the relevant hardware manual.*/ + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->FCR, fcr); + } +} + +#endif + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info. + * + * @param[in] p_ctrl Pointer to driver control block + * @param[in] ipl Interrupt priority level + * @param[in] irq IRQ number for this interrupt + **********************************************************************************************************************/ +static void r_sci_irq_cfg (sci_uart_instance_ctrl_t * const p_ctrl, uint8_t const ipl, IRQn_Type const irq) +{ + /* Disable interrupts, set priority, and store control block in the vector information so it can be accessed + * from the callback. */ + R_BSP_IrqDisable(irq); + R_BSP_IrqStatusClear(irq); + R_BSP_IrqCfg(irq, ipl, p_ctrl); +} + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info for all interrupts. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_irqs_cfg (sci_uart_instance_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ +#if (SCI_UART_CFG_RX_ENABLE) + + /* ERI is optional. */ + r_sci_irq_cfg(p_ctrl, p_cfg->eri_ipl, p_cfg->eri_irq); + r_sci_irq_cfg(p_ctrl, p_cfg->rxi_ipl, p_cfg->rxi_irq); +#endif +#if (SCI_UART_CFG_TX_ENABLE) + r_sci_irq_cfg(p_ctrl, p_cfg->txi_ipl, p_cfg->txi_irq); + + r_sci_irq_cfg(p_ctrl, p_cfg->tei_ipl, p_cfg->tei_irq); +#endif +} + +#if SCI_UART_CFG_DTC_SUPPORTED + +/*******************************************************************************************************************//** + * Closes transfer interfaces. + * + * @param[in] p_ctrl Pointer to UART instance control block + **********************************************************************************************************************/ +static void r_sci_uart_transfer_close (sci_uart_instance_ctrl_t * p_ctrl) +{ + #if (SCI_UART_CFG_RX_ENABLE) + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if (SCI_UART_CFG_TX_ENABLE) + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Changes baud rate based on predetermined register settings. + * + * @param[in] p_sci_reg Base pointer for SCI registers + * @param[in] p_baud_setting Pointer to other divisor related settings + * + * @note The transmitter and receiver (TE and RE bits in SCR) must be disabled prior to calling this function. + **********************************************************************************************************************/ +static void r_sci_uart_baud_set (R_SCI0_Type * p_sci_reg, baud_setting_t const * const p_baud_setting) +{ + /* Set BRR register value. */ + p_sci_reg->BRR = p_baud_setting->brr; + + /* Set clock source for the on-chip baud rate generator. */ + p_sci_reg->SMR_b.CKS = (uint8_t) (SCI_SMR_CKS_VALUE_MASK & p_baud_setting->cks); + + /* Set MDDR register value. */ + p_sci_reg->MDDR = p_baud_setting->mddr; + + /* Set clock divisor settings. */ + p_sci_reg->SEMR = (uint8_t) ((p_sci_reg->SEMR & ~(SCI_UART_SEMR_BAUD_SETTING_MASK)) | + (p_baud_setting->semr_baudrate_bits & SCI_UART_SEMR_BAUD_SETTING_MASK)); +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_uart_call_callback (sci_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) +{ + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + uart_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_uart_prv_ns_callback p_callback = (sci_uart_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +#if (SCI_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TXI interrupt processing for UART mode. TXI interrupt fires when the data in the data register or FIFO register has + * been transferred to the data shift register, and the next data can be written. This interrupt writes the next data. + * After the last data byte is written, this interrupt disables the TXI interrupt and enables the TEI (transmit end) + * interrupt. + **********************************************************************************************************************/ +void sci_uart_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if ((NULL == p_ctrl->p_cfg->p_transfer_tx) && (0U != p_ctrl->tx_src_bytes)) + { + /* Write the data to the FIFO if the channel has a FIFO. Otherwise write data based on size to the transmit + * register. Write to 16-bit TDRHL for 9-bit data, or 8-bit TDR otherwise. */ + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_ctrl->fifo_depth) + { + uint32_t fifo_count = (uint32_t) p_ctrl->p_reg->FDR_b.T; + for (uint32_t cnt = fifo_count; (cnt < p_ctrl->fifo_depth) && p_ctrl->tx_src_bytes; cnt++) + { + if (2U == p_ctrl->data_bytes) + { + p_ctrl->p_reg->FTDRHL = + (uint16_t) (*((uint16_t *) p_ctrl->p_tx_src) | (uint16_t) ~(SCI_UART_FIFO_DAT_MASK)); + } + else + { + p_ctrl->p_reg->FTDRL = *p_ctrl->p_tx_src; + } + + p_ctrl->tx_src_bytes -= p_ctrl->data_bytes; + p_ctrl->p_tx_src += p_ctrl->data_bytes; + } + + /* Clear TDFE flag */ + /* Don't acess the flag via bit fields because bit 1 is reserved. It must be written as '1' and has an */ + /* undefined read value. Bit fields will attempt to do a read-modify-write which could have unintended */ + /* side effects provided the undefined read behavior. */ + uint8_t ssr_fifo = + (uint8_t) ((p_ctrl->p_reg->SSR_FIFO | SCI_SSR_FIFO_RESERVED_MASK) & ~R_SCI0_SSR_FIFO_TDFE_Msk); + p_ctrl->p_reg->SSR_FIFO = ssr_fifo; + } + else + #endif + { + if ((2U == p_ctrl->data_bytes)) + { + /* Write 16-bit data to TDRHL register */ + p_ctrl->p_reg->TDRHL = *((uint16_t *) (p_ctrl->p_tx_src)) | (uint16_t) ~(SCI_UART_FIFO_DAT_MASK); + } + else + { + /* Write 1byte (uint8_t) data to (uint8_t) data register */ + p_ctrl->p_reg->TDR = *(p_ctrl->p_tx_src); + } + + /* Update pointer to the next data and number of remaining bytes in the control block. */ + p_ctrl->tx_src_bytes -= p_ctrl->data_bytes; + p_ctrl->p_tx_src += p_ctrl->data_bytes; + } + } + + if (0U == p_ctrl->tx_src_bytes) + { + /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */ + uint8_t scr_temp = p_ctrl->p_reg->SCR; + scr_temp |= SCI_SCR_TEIE_MASK; + scr_temp &= (uint8_t) ~SCI_SCR_TIE_MASK; + p_ctrl->p_reg->SCR = scr_temp; + + p_ctrl->p_tx_src = NULL; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY); + } + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * RXI interrupt processing for UART mode. RXI interrupt happens when data arrives to the data register or the FIFO + * register. This function calls callback function when it meets conditions below. + * - UART_EVENT_RX_COMPLETE: The number of data which has been read reaches to the number specified in R_SCI_UART_Read() + * if a transfer instance is used for reception. + * - UART_EVENT_RX_CHAR: Data is received asynchronously (read has not been called) + * + * This interrupt also calls the callback function for RTS pin control if it is registered in R_SCI_UART_Open(). This is + * special functionality to expand SCI hardware capability and make RTS/CTS hardware flow control possible. If macro + * 'SCI_UART_CFG_FLOW_CONTROL_SUPPORT' is set, it is called at the beginning in this function to set the RTS pin high, + * then it is called again just before leaving this function to set the RTS pin low. + * @retval none + **********************************************************************************************************************/ +void sci_uart_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + #if SCI_UART_CFG_DTC_SUPPORTED + if ((p_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_ctrl->rx_dest_bytes)) + #endif + { + #if (SCI_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_ctrl->flow_pin != SCI_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + + /* Pause the transmission of data from the other device. */ + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_UART_FLOW_CONTROL_ACTIVE); + } + #endif + + uint32_t data; + #if SCI_UART_CFG_FIFO_SUPPORT + do + { + if ((p_ctrl->fifo_depth > 0U)) + { + if (p_ctrl->p_reg->FDR_b.R > 0U) + { + data = p_ctrl->p_reg->FRDRHL & FRDR_TDAT_MASK_9BITS; + } + else + { + break; + } + } + else if (2U == p_ctrl->data_bytes) + #else + { + if (2U == p_ctrl->data_bytes) + #endif + { + data = p_ctrl->p_reg->RDRHL & FRDR_TDAT_MASK_9BITS; + } + else + { + data = p_ctrl->p_reg->RDR; + } + + if (0 == p_ctrl->rx_dest_bytes) + { + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call user callback with the data. */ + r_sci_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR); + } + } + else + { + memcpy((void *) p_ctrl->p_rx_dest, &data, p_ctrl->data_bytes); + p_ctrl->p_rx_dest += p_ctrl->data_bytes; + p_ctrl->rx_dest_bytes -= p_ctrl->data_bytes; + + if (0 == p_ctrl->rx_dest_bytes) + { + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + } + + #if SCI_UART_CFG_FIFO_SUPPORT + } while ((p_ctrl->fifo_depth > 0U) && ((p_ctrl->p_reg->FDR_b.R) > 0U)); + + if (p_ctrl->fifo_depth > 0U) + { + p_ctrl->p_reg->SSR_FIFO = (uint8_t) ~(SCI_UART_SSR_FIFO_DR_RDF); + } + + #else + } + #endif + #if (SCI_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_ctrl->flow_pin != SCI_UART_INVALID_16BIT_PARAM) + { + /* Resume the transmission of data from the other device. */ + R_BSP_PinWrite(p_ctrl->flow_pin, SCI_UART_FLOW_CONTROL_INACTIVE); + R_BSP_PinAccessDisable(); + } + #endif + } + + #if SCI_UART_CFG_DTC_SUPPORTED + else + { + p_ctrl->rx_dest_bytes = 0; + + p_ctrl->p_rx_dest = NULL; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call callback */ + r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + #endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TEI interrupt processing for UART mode. The TEI interrupt fires after the last byte is transmitted on the TX pin. + * The user callback function is called with the UART_EVENT_TX_COMPLETE event code (if it is registered in + * R_SCI_UART_Open()). + **********************************************************************************************************************/ +void sci_uart_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */ + p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK); + + /* Negate driver enable if RS-485 mode is enabled. */ + r_sci_negate_de_pin(p_ctrl); + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * ERI interrupt processing for UART mode. When an ERI interrupt fires, the user callback function is called if it is + * registered in R_SCI_UART_Open() with the event code that triggered the interrupt. + **********************************************************************************************************************/ +void sci_uart_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t data = 0U; + uart_event_t event; + + /* Read data. */ + if ( + #if SCI_UART_CFG_FIFO_SUPPORT + (p_ctrl->fifo_depth > 0U) || + #endif + (2U == p_ctrl->data_bytes)) + { + { + data = p_ctrl->p_reg->RDRHL & SCI_UART_FIFO_DAT_MASK; + } + } + else + { + data = p_ctrl->p_reg->RDR; + } + + /* Determine cause of error. */ + event = (uart_event_t) (p_ctrl->p_reg->SSR & SCI_RCVR_ERR_MASK); + + /* Check if there is a break detected. */ + if ((UART_EVENT_ERR_FRAMING == (event & UART_EVENT_ERR_FRAMING)) && (0U == p_ctrl->p_reg->SPTR_b.RXDMON)) + { + event |= UART_EVENT_BREAK_DETECT; + } + + /* Clear error condition. */ + p_ctrl->p_reg->SSR &= (uint8_t) (~SCI_RCVR_ERR_MASK); + + /* Negate driver enable if RS-485 mode is enabled. */ + r_sci_negate_de_pin(p_ctrl); + + /* If a callback was provided, call it with the argument */ + if (NULL != p_ctrl->p_callback) + { + /* Call callback. */ + r_sci_uart_call_callback(p_ctrl, data, event); + } + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdadc/r_sdadc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdadc/r_sdadc.c new file mode 100644 index 0000000000..ef9d295388 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdadc/r_sdadc.c @@ -0,0 +1,1087 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_adc_api.h" + +/* Configuration for this package. */ +#include "r_sdadc_cfg.h" + +/* Private header file for this package. */ +#include "r_sdadc.h" + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if BSP_CFG_SDADCCLK_DIV == 8 + #define SDADC_PRIV_CLK_DIV (16U) +#elif BSP_CFG_SDADCCLK_DIV == 7 + #define SDADC_PRIV_CLK_DIV (12U) +#elif BSP_CFG_SDADCCLK_DIV == 6 + #define SDADC_PRIV_CLK_DIV (8U) +#else + #define SDADC_PRIV_CLK_DIV (BSP_CFG_SDADCCLK_DIV + 1U) +#endif + +#if BSP_CFG_SDADC_CLOCK_SOURCE == 0 + #define SDADC_PRIV_CLK_INPUT (BSP_HOCO_HZ) +#else + #define SDADC_PRIV_CLK_INPUT (BSP_CFG_XTAL_HZ) +#endif + +#define SDADC_PRIV_CLK_HZ (SDADC_PRIV_CLK_INPUT / SDADC_PRIV_CLK_DIV) +#define SDADC_PRIV_NORMAL_MODE_CLK_HZ (4000000U) +#define SDADC_PRIV_LOW_POWER_MODE_CLK_HZ (500000U) + +#if (SDADC_PRIV_CLK_HZ != SDADC_PRIV_NORMAL_MODE_CLK_HZ) && (SDADC_PRIV_CLK_HZ != SDADC_PRIV_LOW_POWER_MODE_CLK_HZ) + #error "SDADC clock must be 4 MHz" +#endif + +#define SDADC_PRIV_VSBIAS_STABILIZATION_US (80U) + +#define SDADC_PRIV_PGAC_DEFAULT (0x00010040U) +#define SDADC_PRIV_PGAC_PGACVE_SHIFT (30) +#define SDADC_PRIV_PGAC_PGAOFS_MASK (0x1F00U) + +/* Calibration was measured to take 3.4 ms per channel. A 10% buffer is added. So the timeout is 3.4 ms * 5 * 1.10 = 19 ms. */ +#define SDADC_PRIV_CALIBRATION_TIMEOUT_US (19000U) + +#define SDADC_PRIV_8_BITS (8U) +#define SDADC_PRIV_16_BITS (16U) + +#define SDADC_OPEN (0x53444144U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** SDADC power mode. */ +typedef enum e_sdadc_power_mode +{ + SDADC_POWER_MODE_NORMAL = 0, ///< Normal mode (reference clock 4 MHz, oversampling clock 1 MHz) + SDADC_POWER_MODE_LOW_POWER = 1, ///< Low power mode (reference clock 500 kHz, oversampling clock 125 kHz) +} sdadc_power_mode_t; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_sdadc_open_param_check(sdadc_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg); + +static fsp_err_t r_sdadc_open_param_check_2(adc_cfg_t const * const p_cfg); + +static fsp_err_t r_sdadc_calibrate_param_check(sdadc_instance_ctrl_t * const p_instance_ctrl, + sdadc_calibrate_args_t * p_calibrate); + +#endif + +static fsp_err_t r_sdadc_open_irq_cfg(sdadc_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg); + +static void r_sdadc_scan_configure(uint32_t scan_mask, adc_mode_t mode, adc_trigger_t trigger); + +static void r_sdadc_calibrate_end_restore(sdadc_instance_ctrl_t * const p_instance_ctrl); + +static void r_sdadc_disable_irq(IRQn_Type irq); + +void sdadc_adi_isr(void); +void sdadc_scanend_isr(void); +void sdadc_caliend_isr(void); + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** SDADC Implementation of ADC interface. */ +const adc_api_t g_adc_on_sdadc = +{ + .open = R_SDADC_Open, + .scanCfg = R_SDADC_ScanCfg, + .infoGet = R_SDADC_InfoGet, + .scanStart = R_SDADC_ScanStart, + .scanGroupStart = R_SDADC_ScanGroupStart, + .scanStop = R_SDADC_ScanStop, + .scanStatusGet = R_SDADC_StatusGet, + .offsetSet = R_SDADC_OffsetSet, + .read = R_SDADC_Read, + .read32 = R_SDADC_Read32, + .calibrate = R_SDADC_Calibrate, + .close = R_SDADC_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup SDADC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Applies power to the SDADC and initializes the hardware based on the user configuration. As part of this + * initialization, the SDADC clock is configured and enabled. If an interrupt priority is non-zero, enables an + * interrupt which will call a callback to notify the user when a conversion, scan, or calibration is complete. + * R_SDADC_Calibrate() must be called after this function before using the SDADC if any channels are used in + * differential mode. Implements @ref adc_api_t::open(). + * + * @note This function delays at least 2 ms as required by the SDADC power on procedure. + * + * @retval FSP_SUCCESS Configuration successful. + * @retval FSP_ERR_ASSERTION An input pointer is NULL or an input parameter is invalid. + * @retval FSP_ERR_ALREADY_OPEN Control block is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt is disabled + **********************************************************************************************************************/ +fsp_err_t R_SDADC_Open (adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + err = r_sdadc_open_param_check(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Set all p_instance_ctrl fields prior to using it in any functions. */ + p_instance_ctrl->p_cfg = p_cfg; + + /* Configure and enable interrupts. */ + err = r_sdadc_open_irq_cfg(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_instance_ctrl->calib_status = false; + + /* Initialize the hardware based on the configuration. */ + + /* Start the SDADC. */ + R_BSP_MODULE_START(FSP_IP_SDADC, 0U); + + /* Apply default settings to unused registers. */ + + /* All bits in STC1, ADC1, and PGACn are set during initialization. ADCR, ADAR, and CLBSSR are read-only. STC2 needs to + * be initialized to ensure all the power is not applied during initialization. */ + R_SDADC0->ADC2 = 0U; + R_SDADC0->CLBC = 0U; + R_SDADC0->CLBSTR = 0U; + R_SDADC0->STC2 = 0U; + + /* Configure the SDADC clock source and divisor to the clock source selected in the clock configuration. This must be + * done before the analog power supply is activated (See reference Note 1 of "Startup Control Register 1 + * (STC1)" description in the SDADC section of the relevant hardware manual). */ + + /* Set the A/D conversion operation mode (normal mode). */ + /* Set the reference voltage for sensors (internal or external VREF mode). */ + /* After discussions with the hardware design team, we do not need to step through changes to VSBIAS when BGRPON is 0. */ + sdadc_extended_cfg_t const * p_cfg_extend = p_cfg->p_extend; + uint32_t stc1 = BSP_CFG_SDADCCLK_DIV | (uint32_t) (SDADC_POWER_MODE_NORMAL << R_SDADC0_STC1_SDADLPM_Pos) | + (uint32_t) (p_cfg_extend->vref_src << R_SDADC0_STC1_VREFSEL_Pos) | + (uint32_t) (p_cfg_extend->vref_voltage << R_SDADC0_STC1_VSBIAS_Pos); + R_SDADC0->STC1 = (uint16_t) stc1; + + /* Activate the analog power supply as described in Figure "Analog power supply activation flow" + * in the SDADC section of the relevant hardware manual. */ + + /* Supply the 24-bit sigma-delta A/D converter clock (SDADCCLK). */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->SDADCCKCR |= R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /* Turn on the power of ADBGR, SBIAS, and ADREG. */ + R_SDADC0->STC2 = R_SDADC0_STC2_BGRPON_Msk; + + /* Stabilization wait time of 2 ms is required between power on of ADBGR/SBIAS/ADREG and VBIAS/channel/SDADC. */ + R_BSP_SoftwareDelay(2U, BSP_DELAY_UNITS_MILLISECONDS); + + /* Turn on the power of VBIAS, channel, and sigma-delta A/D converter. */ + R_SDADC0->STC2 = R_SDADC0_STC2_ADCPON_Msk | R_SDADC0_STC2_BGRPON_Msk; + + /* For each channel: */ + uint32_t scan_mask = 0U; + for (uint32_t i = 0U; i < SDADC_MAX_NUM_CHANNELS; i++) + { + p_instance_ctrl->results.results_32[i] = 0U; + if (NULL != p_cfg_extend->p_channel_cfgs[i]) + { + /* Set the oversampling ratio. */ + uint32_t pgac_register_value = p_cfg_extend->p_channel_cfgs[i]->pgac_setting; + + /* If differential mode is used and calibration during open is not skipped, enable calibration on this channel. */ + if (SDADC_CHANNEL_INPUT_DIFFERENTIAL == p_cfg_extend->p_channel_cfgs[i]->pgac_setting_b.input) + { + pgac_register_value |= 1U << SDADC_PRIV_PGAC_PGACVE_SHIFT; + } + + R_SDADC0->PGAC[(adc_channel_t) i] = pgac_register_value; + + /* Enable conversion for the channel. */ + scan_mask |= (1U << i); + } + else + { + R_SDADC0->PGAC[(adc_channel_t) i] = SDADC_PRIV_PGAC_DEFAULT; + } + } + + p_instance_ctrl->scan_mask = scan_mask; + p_instance_ctrl->scan_cfg_mask = scan_mask; + + /* Configure enabled channels and autoscan mode. */ + + /* If the A/D conversion trigger is ELC hardware events, the hardware events are enabled in + * @ref adc_api_t::scanStart(). */ + r_sdadc_scan_configure(p_instance_ctrl->scan_mask, p_cfg->mode, ADC_TRIGGER_SOFTWARE); + + /* Mark driver as open by initializing it to "SDAD" - its ASCII equivalent. */ + p_instance_ctrl->opened = SDADC_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the enabled channels of the ADC. Pass a pointer to @ref sdadc_scan_cfg_t to p_extend. Implements + * @ref adc_api_t::scanCfg(). + * + * @retval FSP_SUCCESS Information stored in p_adc_info. + * @retval FSP_ERR_ASSERTION An input pointer is NULL or an input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_ScanCfg (adc_ctrl_t * p_ctrl, void const * const p_extend) +{ + sdadc_scan_cfg_t const * p_scan_cfg = (sdadc_scan_cfg_t const *) p_extend; + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_scan_cfg); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + + /* Verify all channels to enable are configured. */ + FSP_ASSERT(p_instance_ctrl->scan_cfg_mask == (p_scan_cfg->scan_mask | p_instance_ctrl->scan_cfg_mask)); +#endif + + /* Update the enabled channels. */ + p_instance_ctrl->scan_mask = p_scan_cfg->scan_mask; + r_sdadc_scan_configure(p_instance_ctrl->scan_mask, p_instance_ctrl->p_cfg->mode, p_instance_ctrl->p_cfg->trigger); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Returns the address of the lowest number configured channel, the total number of results to be read in order to + * read the results of all configured channels, the size of each result, and the ELC event enumerations. Implements + * @ref adc_api_t::infoGet(). + * + * @retval FSP_SUCCESS Information stored in p_adc_info. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_InfoGet (adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_adc_info); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Retrieve the scan mask of active channels from the control block */ + uint32_t scan_mask = p_instance_ctrl->scan_mask; + + if (0U == scan_mask) + { + p_adc_info->length = 0U; + p_adc_info->p_address = NULL; + p_adc_info->transfer_size = TRANSFER_SIZE_2_BYTE; + } + else + { + /* Determine the lowest channel that is configured. */ + uint32_t temp_mask = 0U; + int32_t lowest_channel = -1; + while (0U == temp_mask) + { + lowest_channel++; + temp_mask = (uint32_t) (scan_mask & (1U << lowest_channel)); + } + + /* Determine the highest channel that is configured. */ + int32_t highest_channel = SDADC_MAX_NUM_CHANNELS; + temp_mask = 0U; + while (0U == temp_mask) + { + highest_channel--; + temp_mask = (uint32_t) (scan_mask & (1U << highest_channel)); + } + + /* Determine the size of data that must be read to read all the channels between and including the + * highest and lowest channels. */ + p_adc_info->length = (uint32_t) ((highest_channel - lowest_channel) + 1); + + /* Determine the base address and transfer size. */ + p_adc_info->p_address = (__I uint16_t *) &R_SDADC0->ADCR; + p_adc_info->transfer_size = TRANSFER_SIZE_4_BYTE; + } + + /* Specify the peripheral name in the ELC list */ + p_adc_info->elc_event = ELC_EVENT_SDADC0_ADI; + p_adc_info->elc_peripheral = ELC_PERIPHERAL_SDADC0; + + /* Set sensor information to invalid value */ + p_adc_info->calibration_data = UINT32_MAX; + p_adc_info->slope_microvolts = 0U; + + return err; +} + +/*******************************************************************************************************************//** + * If the SDADC is configured for hardware triggers, enables hardware triggers. Otherwise, starts a scan. + * Implements @ref adc_api_t::scanStart(). + * + * @retval FSP_SUCCESS Scan started or hardware triggers enabled successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + * @retval FSP_ERR_IN_USE A conversion or calibration is in progress. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_ScanStart (adc_ctrl_t * p_ctrl) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + + /* Conversion cannot be performed if conversion or calibration is already in progress. */ + FSP_ERROR_RETURN(0U == p_instance_ctrl->calib_status, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(0U == R_SDADC0->ADC2, FSP_ERR_IN_USE); +#endif + + /* If the unit is configured for software triggering, trigger a scan. */ + if (ADC_TRIGGER_SOFTWARE == p_instance_ctrl->p_cfg->trigger) + { + R_SDADC0->ADC2 = 1U; + } + else + { + /* Otherwise, enable hardware triggers. */ + R_SDADC0->ADC1_b.SDADTMD = 1U; + } + + /* Return the error code */ + return err; +} + +/*******************************************************************************************************************//** + * @ref adc_api_t::scanStart is not supported on the SDADC. Use scanStart instead. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_ScanGroupStart (adc_ctrl_t * p_ctrl, adc_group_mask_t group_id) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(group_id); + + /* Return the unsupported error. */ + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * If the SDADC is configured for hardware triggers, disables hardware triggers. Otherwise, stops any in-progress scan + * started by software. Implements @ref adc_api_t::scanStop(). + * + * @retval FSP_SUCCESS Scan stopped or hardware triggers disabled successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_ScanStop (adc_ctrl_t * p_ctrl) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* If the unit is configured for software triggering, stop the scan. */ + if (ADC_TRIGGER_SOFTWARE == p_instance_ctrl->p_cfg->trigger) + { + R_SDADC0->ADC2 = 0U; + } + else + { + /* Otherwise, disable hardware triggers. */ + R_SDADC0->ADC1_b.SDADTMD = 0U; + } + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Returns the status of a scan started by software, including calibration scans. It is not possible to determine the + * status of a scan started by a hardware trigger. Implements @ref adc_api_t::scanStatusGet(). + * + * @retval FSP_SUCCESS No software scan or calibration is in progress. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_StatusGet (adc_ctrl_t * p_ctrl, adc_status_t * p_status) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* If calibration is in progress or a scan was triggered by software, scan is in progress. */ + bool calib_status = p_instance_ctrl->calib_status; // non-volatile copy + p_status->state = (adc_state_t) (calib_status | R_SDADC0->ADC2); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the most recent conversion result from a channel. Truncates 24-bit results to the upper 16 bits. Implements + * @ref adc_api_t::read(). + * + * @note The result stored in p_data is signed when the SDADC channel is configured in differential mode. + * + * @note Do not use this API if the conversion end interrupt (SDADC0_ADI) is used to trigger the DTC unless the + * interrupt mode is set to TRANSFER_IRQ_EACH. + * + * @retval FSP_SUCCESS Conversion result in p_data. + * @retval FSP_ERR_ASSERTION An input pointer was NULL or an input parameter was invalid. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_Read (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ASSERT(0U != ((1U << (uint32_t) reg_id) & p_instance_ctrl->scan_mask)); +#endif + + /* Read the most recent conversion value into a 16-bit result. */ + if (ADC_RESOLUTION_24_BIT == p_instance_ctrl->p_cfg->resolution) + { + if (ADC_ALIGNMENT_LEFT == p_instance_ctrl->p_cfg->alignment) + { + *p_data = (uint16_t) (p_instance_ctrl->results.results_32[reg_id] >> SDADC_PRIV_16_BITS); + } + else + { + *p_data = (uint16_t) (p_instance_ctrl->results.results_32[reg_id] >> SDADC_PRIV_8_BITS); + } + } + else + { + *p_data = p_instance_ctrl->results.results_16[reg_id]; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the most recent conversion result from a channel. Implements @ref adc_api_t::read32(). + * + * @note The result stored in p_data is signed when the SDADC channel is configured in differential mode. When the + * SDADC is configured for 24-bit resolution and right alignment, the sign bit is bit 23, and the upper 8 bits are 0. + * When the SDADC is configured for 16-bit resolution and right alignment, the sign bit is bit 15, and the upper 16 + * bits are 0. + * + * @note Do not use this API if the conversion end interrupt (SDADC0_ADI) is used to trigger the DTC unless the + * interrupt mode is set to TRANSFER_IRQ_EACH. + * + * @retval FSP_SUCCESS Conversion result in p_data. + * @retval FSP_ERR_ASSERTION An input pointer was NULL or an input parameter was invalid. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_Read32 (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ASSERT(0U != ((1U << (uint32_t) reg_id) & p_instance_ctrl->scan_mask)); +#endif + + /* Read the most recent conversion value into a 32-bit result. */ + uint32_t result = 0U; + if (ADC_RESOLUTION_24_BIT == p_instance_ctrl->p_cfg->resolution) + { + result = p_instance_ctrl->results.results_32[reg_id]; + } + else + { + result = (uint32_t) p_instance_ctrl->results.results_16[reg_id]; + if (ADC_ALIGNMENT_LEFT == p_instance_ctrl->p_cfg->alignment) + { + result <<= SDADC_PRIV_16_BITS; + } + } + + *p_data = result; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the offset. Offset is applied after stage 1 of the input channel. Offset can only be applied when the channel + * is configured for differential input. Implements @ref adc_api_t::offsetSet(). + * + * Note: The offset is cleared if @ref adc_api_t::calibrate() is called. The offset can be re-applied if necessary + * after the the callback with event ADC_EVENT_CALIBRATION_COMPLETE is called. + * + * @param[in] p_ctrl See p_instance_ctrl in @ref adc_api_t::offsetSet(). + * @param[in] reg_id See reg_id in @ref adc_api_t::offsetSet(). + * @param[in] offset Must be between -15 and 15, offset (mV) = 10.9376 mV * offset_steps / stage 1 gain. + * + * @retval FSP_SUCCESS Offset updated successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL or an input parameter was invalid. + * @retval FSP_ERR_IN_USE A conversion or calibration is in progress. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_OffsetSet (adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t const offset) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT((offset >= -15) && (offset <= 15)); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + FSP_ASSERT(0U != ((1U << (uint32_t) reg_id) & p_instance_ctrl->scan_cfg_mask)); + + /* The channel must be configured for differential input. */ + FSP_ASSERT(SDADC_CHANNEL_INPUT_DIFFERENTIAL == (sdadc_channel_input_t) R_SDADC0->PGAC_b[reg_id].PGASEL); +#endif + + /* Offset cannot be updated if conversion or calibration is in progress. */ + FSP_ERROR_RETURN(0U == p_instance_ctrl->calib_status, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(0U == R_SDADC0->ADC2, FSP_ERR_IN_USE); + + /* Set the offset. */ + R_SDADC0->PGAC_b[reg_id].PGAOFS = (uint32_t) offset & 0x1FU; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Requires ::sdadc_calibrate_args_t passed to p_extend. Calibrates the specified channel. Calibration is not required + * or supported for single-ended mode. Calibration must be completed for differential mode before using the SDADC. A + * callback with the event ADC_EVENT_CALIBRATION_COMPLETE is called when calibration completes. Implements @ref + * adc_api_t::calibrate(). + * + * During external offset calibration, apply a differential voltage of 0 to ANSDnP - ANSDnN, where n is the input + * channel and ANSDnP is OPAMP0 for channel 4 and ANSDnN is OPAMP1 for channel 4. Complete external offset calibration + * before external gain calibration. + * + * During external gain calibration apply a voltage between 0.4 V / total_gain and 0.8 V / total_gain. The + * differential voltage applied during calibration is corrected to a conversion result of 0x7FFFFF, which is the + * maximum possible positive differential measurement. + * + * This function clears the offset value. If offset is required after calibration, it must be reapplied after + * calibration is complete using @ref adc_api_t::offsetSet. + * + * @retval FSP_SUCCESS Calibration began successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_IN_USE A conversion or calibration is in progress. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_Calibrate (adc_ctrl_t * const p_ctrl, void const * p_extend) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + sdadc_calibrate_args_t * p_calibrate = (sdadc_calibrate_args_t *) p_extend; + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + fsp_err_t err = r_sdadc_calibrate_param_check(p_instance_ctrl, p_calibrate); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Calibration cannot be performed if conversion or calibration is already in progress. */ + FSP_ERROR_RETURN(0U == p_instance_ctrl->calib_status, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(0U == R_SDADC0->ADC2, FSP_ERR_IN_USE); +#endif + + p_instance_ctrl->calib_status = 1U; + + /* Calibrate the SDADC as described in the figures "Internal calibration flow" and "External + * calibration flow" in the SDADC section of the relevant hardware manual. */ + + /* Select software trigger. */ + /* Select single scan mode. */ + r_sdadc_scan_configure(0U, ADC_MODE_SINGLE_SCAN, ADC_TRIGGER_SOFTWARE); + + /* Enable calibration and clear offset to 0 mV. */ + uint32_t pgac = R_SDADC0->PGAC[p_calibrate->channel]; + pgac &= ~SDADC_PRIV_PGAC_PGAOFS_MASK; + pgac |= 1U << SDADC_PRIV_PGAC_PGACVE_SHIFT; + R_SDADC0->PGAC[p_calibrate->channel] = pgac; + + /* Set the calibration mode. */ + R_SDADC0->CLBC = (uint8_t) p_calibrate->mode; + + /* Start calibration. */ + R_SDADC0->CLBSTR = 1U; + + /* Not verifying calibration started by checking CLBSSR because a context switch could cause the setting of CLBSSR + * to be missed since it clears itself when calibration completes. This could be avoided with a critical section, + * but CLBSSR is set after 2 PCLKB + 3 SDADCCLK, which could block interrupts for longer than desired depending + * on the divider of PCLKB. *//* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops any scan in progress, disables interrupts, and powers down the SDADC peripheral. Implements + * @ref adc_api_t::close(). + * + * @note This function delays at least 3 us as required by the SDADC24 stop procedure. + * + * @retval FSP_SUCCESS Instance control block closed successfully. + * @retval FSP_ERR_ASSERTION An input pointer was NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not open. + **********************************************************************************************************************/ +fsp_err_t R_SDADC_Close (adc_ctrl_t * p_ctrl) +{ + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) p_ctrl; + + /* Perform parameter checking*/ +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Mark driver as closed */ + p_instance_ctrl->opened = 0U; + + /* Follow the procedure in Figure "SDADC24 stop setting flow" in the SDADC section of the relevant hardware manual. */ + + /* Stop A/D conversion. */ + R_SDADC0->ADC1 = R_SDADC0_ADC1_SDADBMP_Msk; + R_SDADC0->ADC2 = 0U; + + /* Disable interrupts. */ + sdadc_extended_cfg_t const * p_cfg_extend = (sdadc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + r_sdadc_disable_irq(p_cfg_extend->conv_end_irq); + r_sdadc_disable_irq(p_instance_ctrl->p_cfg->scan_end_irq); + r_sdadc_disable_irq(p_instance_ctrl->p_cfg->scan_end_b_irq); + + /* Wait 3 us in normal mode. */ + R_BSP_SoftwareDelay(3U, BSP_DELAY_UNITS_MICROSECONDS); + + /* Turn off the power of VBIAS, channel, and sigma-delta A/D converter. */ + R_SDADC0->STC2 = R_SDADC0_STC2_BGRPON_Msk; + + /* Turn off the power of ADBGR, SBIAS, and ADREG. This must be done after clearing ADCPON according to + * Figure "SDADC24 stop setting flow" in the SDADC section of the relevant hardware manual. */ + R_SDADC0->STC2 = 0U; + + /* Stop the input clock for the 24-bit sigma-delta A/D converter (SDADCCLK). */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); + R_SYSTEM->SDADCCKCR &= (uint8_t) ~R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC); + + /* Enter the module-stop state. */ + R_BSP_MODULE_STOP(FSP_IP_SDADC, 0U); + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SDADC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Validates the input parameters to open(). + * + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS No invalid configurations identified. + * @retval FSP_ERR_ASSERTION An input parameter was invalid. + **********************************************************************************************************************/ +static fsp_err_t r_sdadc_open_param_check_2 (adc_cfg_t const * const p_cfg) +{ + /* When single-ended input is selected, oversampling must be 256 and gain at each stage must be 1. */ + sdadc_extended_cfg_t const * p_cfg_extend = (sdadc_extended_cfg_t *) p_cfg->p_extend; + uint32_t channels_configured = 0U; + for (uint32_t i = 0U; i < SDADC_MAX_NUM_CHANNELS; i++) + { + if (NULL != p_cfg_extend->p_channel_cfgs[i]) + { + channels_configured++; + if (SDADC_CHANNEL_INPUT_SINGLE_ENDED == p_cfg_extend->p_channel_cfgs[i]->pgac_setting_b.input) + { + FSP_ASSERT( + SDADC_CHANNEL_OVERSAMPLING_256 == p_cfg_extend->p_channel_cfgs[i]->pgac_setting_b.oversampling); + FSP_ASSERT(SDADC_CHANNEL_STAGE_1_GAIN_1 == + p_cfg_extend->p_channel_cfgs[i]->pgac_setting_b.stage_1_gain); + FSP_ASSERT(SDADC_CHANNEL_STAGE_2_GAIN_1 == + p_cfg_extend->p_channel_cfgs[i]->pgac_setting_b.stage_2_gain); + } + } + } + + /* At least one channel must be configured */ + FSP_ASSERT(channels_configured > 0U); + + /* Conversion end interrupt is required. */ + FSP_ASSERT(p_cfg_extend->conv_end_irq >= 0); + + /* Callback is required if scan end interrupt is enabled. */ + if (p_cfg->scan_end_irq >= 0) + { + FSP_ASSERT(NULL != p_cfg->p_callback); + } + + return FSP_SUCCESS; +} + +#endif + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Validates the input parameters to open(). + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS No invalid configurations identified. + * @retval FSP_ERR_ALREADY_OPEN Control block is already open. + * @retval FSP_ERR_ASSERTION An input pointer is NULL or an input parameter is invalid. + **********************************************************************************************************************/ +static fsp_err_t r_sdadc_open_param_check (sdadc_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg) +{ + /* Verify the pointers are not NULL. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + + /* Verify the control block has not already been initialized. */ + FSP_ERROR_RETURN(SDADC_OPEN != p_instance_ctrl->opened, FSP_ERR_ALREADY_OPEN); + + /* Resolution must be 24-bit or 16-bit. */ + FSP_ASSERT((ADC_RESOLUTION_24_BIT == p_cfg->resolution) || (ADC_RESOLUTION_16_BIT == p_cfg->resolution)); + + /* Group scan mode is not supported. */ + FSP_ASSERT(ADC_MODE_GROUP_SCAN != p_cfg->mode); + + /* External trigger mode is not supported. */ + FSP_ASSERT(ADC_TRIGGER_ASYNC_EXTERNAL != p_cfg->trigger); + + /* If hardware trigger is selected, the product always operates in single scan mode. See SDADTMD documentation + * in "Sigma-Delta A/D Converter Control Register 1 (ADC1)" description in the SDADC section of the relevant + * hardware manual. */ + if (ADC_TRIGGER_SYNC_ELC == p_cfg->trigger) + { + FSP_ASSERT(ADC_MODE_SINGLE_SCAN == p_cfg->mode); + } + + fsp_err_t err = r_sdadc_open_param_check_2(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Configures interrupts and ensures required interrupts are enabled. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS All required interrupts enabled. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt is disabled + **********************************************************************************************************************/ +static fsp_err_t r_sdadc_open_irq_cfg (sdadc_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg) +{ + sdadc_extended_cfg_t const * p_cfg_extend = (sdadc_extended_cfg_t *) p_cfg->p_extend; + +#if SDADC_CFG_PARAM_CHECKING_ENABLE + + /* Calibration interrupt is required if any channel is configured for differential mode. */ + for (uint32_t i = 0U; i < SDADC_MAX_NUM_CHANNELS; i++) + { + if (NULL != p_cfg_extend->p_channel_cfgs[i]) + { + if (SDADC_CHANNEL_INPUT_DIFFERENTIAL == p_cfg_extend->p_channel_cfgs[i]->pgac_setting_b.input) + { + FSP_ERROR_RETURN(FSP_INVALID_VECTOR != p_cfg->scan_end_b_irq, FSP_ERR_IRQ_BSP_DISABLED); + } + } + } +#endif + + /* Set the interrupt priorities. */ + /* scan_end_b_irq is used for the calibration end interrupt for SDADC. */ + if (p_cfg->scan_end_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->scan_end_irq, p_cfg->scan_end_ipl, p_instance_ctrl); + } + + if (p_cfg->scan_end_b_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->scan_end_b_irq, p_cfg->scan_end_b_ipl, p_instance_ctrl); + } + + if (p_cfg_extend->conv_end_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg_extend->conv_end_irq, p_cfg_extend->conv_end_ipl, p_instance_ctrl); + } + + return FSP_SUCCESS; +} + +#if (1 == SDADC_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Validates the input parameters to calibrate(). + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_calibrate Pointer to calibration configuration structure + * + * @retval FSP_SUCCESS No invalid configurations identified. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or an input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN The instance control block has not been opened. + **********************************************************************************************************************/ +static fsp_err_t r_sdadc_calibrate_param_check (sdadc_instance_ctrl_t * const p_instance_ctrl, + sdadc_calibrate_args_t * p_calibrate) +{ + /* Verify the pointers are not NULL and ensure the ADC unit is already open. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_calibrate); + FSP_ERROR_RETURN(SDADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN); + + /* The channel must be enabled during open. */ + uint32_t channel = (uint32_t) p_calibrate->channel; + uint32_t mask = 1U << channel; + FSP_ASSERT(0U != (mask & p_instance_ctrl->scan_cfg_mask)); + + /* The channel must be configured for differential input. */ + FSP_ASSERT(SDADC_CHANNEL_INPUT_DIFFERENTIAL == + (sdadc_channel_input_t) R_SDADC0->PGAC_b[p_calibrate->channel].PGASEL); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Sets the scan mask, scan mode, and trigger. + * + * @param[in] scan_mask Bitmask of enabled channels + * @param[in] mode Single scan or continuous scan mode. + * @param[in] trigger ELC or software trigger. + **********************************************************************************************************************/ +static void r_sdadc_scan_configure (uint32_t scan_mask, adc_mode_t mode, adc_trigger_t trigger) +{ + /* Select which channels to enable conversion on. */ + uint32_t adc1_setting = (~scan_mask & 0x1FU) << R_SDADC0_ADC1_SDADBMP_Pos; + + /* Select AUTOSCAN mode (single scan or continuous scan). */ + uint32_t adc1_mode_bit = !((uint32_t) mode); + adc1_setting |= adc1_mode_bit; + + /* Select software or hardware (ELC event) trigger. */ + uint32_t adc1_trigger_bit = (uint32_t) trigger & 0x1U; + adc1_trigger_bit <<= R_SDADC0_ADC1_SDADTMD_Pos; + adc1_setting |= adc1_trigger_bit; + + R_SDADC0->ADC1 = adc1_setting; +} + +/*******************************************************************************************************************//** + * Restores settings after calibration. + * + * @param[in] p_instance_ctrl Pointer to instance control block + **********************************************************************************************************************/ +static void r_sdadc_calibrate_end_restore (sdadc_instance_ctrl_t * const p_instance_ctrl) +{ + /* Disable calibration for all channels. */ + for (uint32_t i = 0U; i < SDADC_MAX_NUM_CHANNELS; i++) + { + R_SDADC0->PGAC_b[i].PGACVE = 0U; + } + + /* Restore scan mask, mode, and trigger. */ + r_sdadc_scan_configure(p_instance_ctrl->scan_mask, p_instance_ctrl->p_cfg->mode, p_instance_ctrl->p_cfg->trigger); + + /* Clear the calibration in progress software flag only after restoring scan mask, mode, and trigger settings. */ + p_instance_ctrl->calib_status = 0U; +} + +/*******************************************************************************************************************//** + * Disables an interrupt. + * + * @param[in] irq Interrupt to disable + **********************************************************************************************************************/ +static void r_sdadc_disable_irq (IRQn_Type irq) +{ + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + R_FSP_IsrContextSet(irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Scan complete interrupt. + **********************************************************************************************************************/ +void sdadc_scanend_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the BSP IRQ Flag. */ + R_BSP_IrqStatusClear(irq); + + /* If a callback was provided, call it with the argument */ + adc_callback_args_t args; + args.unit = 0U; + + /* Store the event into the callback argument */ + args.event = ADC_EVENT_SCAN_COMPLETE; + + args.p_context = p_instance_ctrl->p_cfg->p_context; + p_instance_ctrl->p_cfg->p_callback(&args); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Conversion complete interrupt. + **********************************************************************************************************************/ +void sdadc_adi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the BSP IRQ Flag. */ + R_BSP_IrqStatusClear(irq); + + /* Read the converted result. */ + uint32_t result = R_SDADC0->ADCR; + adc_channel_t channel = (adc_channel_t) ((result >> 25) - 1U); + if (3U == R_SDADC0->PGAC_b[channel].PGAAVE) + { + /* If averaging is enabled, read the averaged result. The regular result register is read first to determine + * the channel number. ADCR contains the last sample in the average if averaging is enabled. */ + result = R_SDADC0->ADAR; + channel = (adc_channel_t) ((result >> 25) - 1U); + } + + /* Mask off the upper 8 bits, which are not part of the result. */ + result = result & R_SDADC0_ADCR_SDADCRD_Msk; + + /* Store the result according to the configured resolution. */ + if (ADC_RESOLUTION_24_BIT == p_instance_ctrl->p_cfg->resolution) + { + if (ADC_ALIGNMENT_LEFT == p_instance_ctrl->p_cfg->alignment) + { + result <<= SDADC_PRIV_8_BITS; + } + + p_instance_ctrl->results.results_32[channel] = result; + } + else + { + result = result >> SDADC_PRIV_8_BITS; + p_instance_ctrl->results.results_16[channel] = (uint16_t) result; + } + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_cfg->p_callback) + { + /* Store the event into the callback argument */ + adc_callback_args_t args; + args.unit = 0U; + args.event = ADC_EVENT_CONVERSION_COMPLETE; + + args.channel = channel; + args.p_context = p_instance_ctrl->p_cfg->p_context; + p_instance_ctrl->p_cfg->p_callback(&args); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Calibration complete interrupt. + **********************************************************************************************************************/ +void sdadc_caliend_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sdadc_instance_ctrl_t * p_instance_ctrl = (sdadc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the BSP IRQ Flag. */ + R_BSP_IrqStatusClear(irq); + + /* Restore settings to their pre-calibration values. */ + r_sdadc_calibrate_end_restore(p_instance_ctrl); + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_cfg->p_callback) + { + /* Store the event into the callback argument */ + adc_callback_args_t args; + args.unit = 0U; + args.event = ADC_EVENT_CALIBRATION_COMPLETE; + args.p_context = p_instance_ctrl->p_cfg->p_context; + p_instance_ctrl->p_cfg->p_callback(&args); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdhi/r_sdhi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdhi/r_sdhi.c new file mode 100644 index 0000000000..33c922d853 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdhi/r_sdhi.c @@ -0,0 +1,2350 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_sdhi.h" +#include "r_sdhi_private.h" +#include "r_sdhi_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "SDHI" in ASCII, used to determine if channel is open. */ +#define SDHI_PRV_OPEN (0x53444849U) + +/* Create a bitmask of access errors. */ +#define SDHI_PRV_CARD_CMD_ERR (1U << 16) // Command error +#define SDHI_PRV_CARD_CRC_ERR (1U << 17) // CRC error +#define SDHI_PRV_CARD_END_ERR (1U << 18) // End bit error +#define SDHI_PRV_CARD_DTO (1U << 19) // Data Timeout +#define SDHI_PRV_CARD_ILW (1U << 20) // Illegal write address +#define SDHI_PRV_CARD_ILR (1U << 21) // Illegal read address +#define SDHI_PRV_CARD_RSPT (1U << 22) // Response timeout +#define SDHI_PRV_CARD_ILA_ERR (1U << 31) // Illegal access + +#define SDHI_PRV_ACCESS_ERROR_MASK \ + (SDHI_PRV_CARD_CMD_ERR | SDHI_PRV_CARD_CRC_ERR | SDHI_PRV_CARD_END_ERR | SDHI_PRV_CARD_DTO | \ + SDHI_PRV_CARD_ILW | SDHI_PRV_CARD_ILR | SDHI_PRV_CARD_RSPT | SDHI_PRV_CARD_ILA_ERR) + +/* The clock register can be accessed 8 SD clock cycles after the last command completes. */ + +/* SD_INFO1 */ +#define SDHI_PRV_SDHI_INFO1_RESPONSE_END (1U << 0) // Response End +#define SDHI_PRV_SDHI_INFO1_ACCESS_END (1U << 2) // Access End +#define SDHI_PRV_SDHI_INFO1_CARD_REMOVED (1U << 3) // Card Removed +#define SDHI_PRV_SDHI_INFO1_CARD_INSERTED (1U << 4) // Card Inserted +#define SDHI_PRV_SDHI_INFO1_CARD_DAT3_REMOVED (1U << 8) // Card Removed +#define SDHI_PRV_SDHI_INFO1_CARD_DAT3_INSERTED (1U << 9) // Card Inserted +#define SDHI_PRV_SDHI_INFO2_CARD_CMD_ERR (1U << 0) // Command error +#define SDHI_PRV_SDHI_INFO2_CARD_CRC_ERR (1U << 1) // CRC error +#define SDHI_PRV_SDHI_INFO2_CARD_END_ERR (1U << 2) // End bit error +#define SDHI_PRV_SDHI_INFO2_CARD_DTO (1U << 3) // Data Timeout +#define SDHI_PRV_SDHI_INFO2_CARD_ILW (1U << 4) // Illegal write address +#define SDHI_PRV_SDHI_INFO2_CARD_ILR (1U << 5) // Illegal read address +#define SDHI_PRV_SDHI_INFO2_CARD_RSPT (1U << 6) // Response timeout +#define SDHI_PRV_SDHI_INFO2_CARD_BRE (1U << 8) // Buffer read enable +#define SDHI_PRV_SDHI_INFO2_CARD_BWE (1U << 9) // Buffer write enable +#define SDHI_PRV_SDHI_INFO2_CARD_ILA_ERR (1U << 15) // Illegal access + +#define SDHI_PRV_SDHI_INFO2_MASK \ + ((SDHI_PRV_SDHI_INFO2_CARD_CMD_ERR | SDHI_PRV_SDHI_INFO2_CARD_CRC_ERR | SDHI_PRV_SDHI_INFO2_CARD_END_ERR | \ + SDHI_PRV_SDHI_INFO2_CARD_DTO | SDHI_PRV_SDHI_INFO2_CARD_ILW | SDHI_PRV_SDHI_INFO2_CARD_ILR | \ + SDHI_PRV_SDHI_INFO2_CARD_BRE | \ + SDHI_PRV_SDHI_INFO2_CARD_BWE | \ + SDHI_PRV_SDHI_INFO2_CARD_RSPT | SDHI_PRV_SDHI_INFO2_CARD_ILA_ERR)) + +#define SDHI_PRV_SDHI_INFO1_ACCESS_MASK ((SDHI_PRV_SDHI_INFO1_RESPONSE_END | \ + SDHI_PRV_SDHI_INFO1_ACCESS_END)) +#define SDHI_PRV_SDHI_INFO1_CARD_MASK ((SDHI_PRV_SDHI_INFO1_CARD_REMOVED | \ + SDHI_PRV_SDHI_INFO1_CARD_INSERTED | \ + SDHI_PRV_SDHI_INFO1_CARD_DAT3_REMOVED | \ + SDHI_PRV_SDHI_INFO1_CARD_DAT3_INSERTED)) +#define SDHI_PRV_SDHI_INFO1_CARD_REMOVED_MASK ((SDHI_PRV_SDHI_INFO1_CARD_REMOVED | \ + SDHI_PRV_SDHI_INFO1_CARD_DAT3_REMOVED)) +#define SDHI_PRV_SDHI_INFO1_CARD_INSERTED_MASK ((SDHI_PRV_SDHI_INFO1_CARD_INSERTED | \ + SDHI_PRV_SDHI_INFO1_CARD_DAT3_INSERTED)) + +/* Clear all masks to enable interrupts by all sources. + * Do not set BREM or BWEM when using DMA/DTC. This driver always uses DMA or DTC. */ +#define SDHI_PRV_SDHI_INFO2_MASK_CMD_SEND (0x00007C80U) + +/* The relationship of the SD Clock Control Register SD_CLK_CTRL CLKSEL to the division of the source PCLK + * b7 b0 + * 1 1 1 1 1 1 1 1: PCLK + * 0 0 0 0 0 0 0 0: PCLK/2 + * 0 0 0 0 0 0 0 1: PCLK/4 + * 0 0 0 0 0 0 1 0: PCLK/8 + * 0 0 0 0 0 1 0 0: PCLK/16 + * 0 0 0 0 1 0 0 0: PCLK/32 + * 0 0 0 1 0 0 0 0: PCLK/64 + * 0 0 1 0 0 0 0 0: PCLK/128 + * 0 1 0 0 0 0 0 0: PCLK/256 + * 1 0 0 0 0 0 0 0: PCLK/512. + * Other settings are prohibited. + */ +#define SDHI_PRV_MAX_CLOCK_DIVISION_SHIFT (9U) /* 512 (2^9) is max clock division supported */ + +#define SDHI_PRV_CLK_CTRL_DIV_INVALID (0xFFU) + +/* Delay up to 250 ms per sector before timing out waiting for response or response timeout flag. */ + +/* Delay up to 10 ms before timing out waiting for response or response timeout flag. */ +#define SDHI_PRV_RESPONSE_TIMEOUT_US (10000U) + +/* Delay up to 5 seconds before timing out waiting for busy after updating bus width or high speed status for eMMC. */ +#define SDHI_PRV_BUSY_TIMEOUT_US (5000000U) + +/* Delay up to 500 ms before timing out waiting for data or data timeout flag. */ +#define SDHI_PRV_DATA_TIMEOUT_US (500000U) + +/* Delay up to 100 ms before timing out waiting for access end flag after receiving data during initialization. */ +#define SDHI_PRV_ACCESS_TIMEOUT_US (100000U) + +/* 400 kHz maximum clock required for initialization. */ +#define SDHI_PRV_INIT_MAX_CLOCK_RATE_HZ (400000U) +#define SDHI_PRV_BITS_PER_COMMAD (48U) +#define SDHI_PRV_BITS_PER_RESPONSE (48U) +#define SDHI_PRV_CLOCKS_BETWEEN_COMMANDS (8U) +#define SDHI_PRV_MIN_CYCLES_PER_COMMAND_RESPONSE ((SDHI_PRV_BITS_PER_COMMAD + \ + SDHI_PRV_BITS_PER_RESPONSE) + \ + SDHI_PRV_CLOCKS_BETWEEN_COMMANDS) +#define SDHI_PRV_INIT_ONE_SECOND_TIMEOUT_ITERATIONS (SDHI_PRV_INIT_MAX_CLOCK_RATE_HZ / \ + SDHI_PRV_MIN_CYCLES_PER_COMMAND_RESPONSE) + +#define SDHI_PRV_CSD_REG_CCC_CLASS_10_BIT ((1U << 10)) // CCC_CLASS bit is set if the card supports high speed + +/* Startup delay in milliseconds. */ + +#define SDHI_PRV_SD_OPTION_DEFAULT (0x40E0U) +#define SDHI_PRV_SD_OPTION_WIDTH8_BIT (13) + +#define SDHI_PRV_BUS_WIDTH_1_BIT (4U) + +#define SDHI_PRV_SD_INFO2_MASK_BREM_BWEM_MASK (0x300U) +#define SDHI_PRV_EMMC_BUS_WIDTH_INDEX (183U) +#define SDHI_PRV_BYTES_PER_KILOBYTE (1024) +#define SDHI_PRV_SECTOR_COUNT_IN_EXT_CSD (0xFFFU) +#define SDHI_PRV_SD_CLK_CTRL_DEFAULT (0x20U) + +#define SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_MASK (0x4080) +#define SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_VAL (0x80) +#define SDHI_PRV_SD_CLK_CTRLEN_TIMEOUT (8U * 512U) +#define SDHI_PRV_SD_INFO1_MASK_MASK_ALL (0x31DU) +#define SDHI_PRV_SD_INFO1_MASK_CD_ENABLE (0x305U) +#define SDHI_PRV_SD_STOP_SD_SECCNT_ENABLE (0x100U) +#define SDHI_PRV_SD_DMAEN_DMAEN_SET (0x2U) + +#define SDHI_PRV_SDHI_PRV_SD_CLK_CTRL_CLKCTRLEN_MASK (1U << 9) +#define SDHI_PRV_SDHI_PRV_SD_CLK_CTRL_CLKEN_MASK (1U << 8) +#define SDHI_PRV_SDHI_PRV_SD_CLK_AUTO_CLOCK_ENABLE_MASK (0x300U) + +#define SDHI_PRV_ACCESS_BIT (2U) +#define SDHI_PRV_RESPONSE_BIT (0U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * sdhi_prv_ns_callback)(sdmmc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sdhi_prv_ns_callback)(sdmmc_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if SDHI_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_sdhi_open_param_check(sdhi_instance_ctrl_t * p_ctrl, sdmmc_cfg_t const * const p_cfg); + +#endif + +#if SDHI_CFG_EMMC_SUPPORT_ENABLE +static fsp_err_t r_sdhi_emmc_check(sdhi_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_sdhi_csd_extended_get(sdhi_instance_ctrl_t * const p_ctrl, uint32_t rca, uint8_t * p_device_type); + +#endif + +#if SDHI_CFG_SD_SUPPORT_ENABLE +static fsp_err_t r_sdhi_sd_card_check(sdhi_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_sdhi_sd_high_speed(sdhi_instance_ctrl_t * const p_ctrl); + +static void r_sdhi_write_protect_get(sdhi_instance_ctrl_t * const p_ctrl); + +#endif + +#if SDHI_CFG_SD_SUPPORT_ENABLE || SDHI_CFG_EMMC_SUPPORT_ENABLE +static fsp_err_t r_sdhi_clock_optimize(sdhi_instance_ctrl_t * const p_ctrl, + uint32_t rca, + sdmmc_priv_csd_reg_t * const p_csd_reg); + +static fsp_err_t r_sdhi_csd_save(sdhi_instance_ctrl_t * const p_ctrl, + uint32_t rca, + sdmmc_priv_csd_reg_t * const p_csd_reg); + +static fsp_err_t r_sdhi_read_and_block(sdhi_instance_ctrl_t * const p_ctrl, + uint32_t command, + uint32_t argument, + uint32_t byte_count); + +static fsp_err_t r_sdhi_bus_width_set(sdhi_instance_ctrl_t * const p_ctrl, uint32_t rca); + +#endif + +static fsp_err_t r_sdhi_erase_error_check(sdhi_instance_ctrl_t * const p_ctrl, + uint32_t const start_sector, + uint32_t const sector_count); + +static fsp_err_t r_sdhi_common_error_check(sdhi_instance_ctrl_t * const p_ctrl); + +static void r_sdhi_irq_enable(IRQn_Type irq, uint8_t priority, void * p_context); +static void r_sdhi_irq_disable(IRQn_Type irq); + +static void r_sdhi_access_irq_process(sdhi_instance_ctrl_t * p_ctrl, sdmmc_callback_args_t * p_args); + +static void r_sdhi_command_send_no_wait(sdhi_instance_ctrl_t * p_ctrl, uint32_t command, uint32_t argument); + +static fsp_err_t r_sdhi_command_send(sdhi_instance_ctrl_t * p_ctrl, uint32_t command, uint32_t argument); + +static fsp_err_t r_sdhi_max_clock_rate_set(sdhi_instance_ctrl_t * p_ctrl, uint32_t max_rate); + +static fsp_err_t r_sdhi_wait_for_event(sdhi_instance_ctrl_t * const p_ctrl, uint32_t bit, uint32_t timeout); + +static fsp_err_t r_sdhi_rca_get(sdhi_instance_ctrl_t * const p_ctrl, uint32_t * p_rca); + +static fsp_err_t r_sdhi_hw_cfg(sdhi_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_sdhi_card_identify(sdhi_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_sdhi_bus_cfg(sdhi_instance_ctrl_t * const p_ctrl); + +static fsp_err_t r_sdhi_wait_for_device(sdhi_instance_ctrl_t * const p_ctrl); + +static void r_sdhi_read_write_common(sdhi_instance_ctrl_t * const p_ctrl, + uint32_t sector_count, + uint32_t sector_size, + uint32_t command, + uint32_t argument); + +static fsp_err_t r_sdhi_transfer_read(sdhi_instance_ctrl_t * const p_ctrl, + uint32_t block_count, + uint32_t bytes, + void * p_data); + +static fsp_err_t r_sdhi_transfer_write(sdhi_instance_ctrl_t * const p_ctrl, + uint32_t block_count, + uint32_t bytes, + const uint8_t * p_data); + +static void r_sdhi_transfer_end(sdhi_instance_ctrl_t * const p_ctrl); + +static void r_sdhi_call_callback(sdhi_instance_ctrl_t * p_ctrl, sdmmc_callback_args_t * p_args); + +void r_sdhi_transfer_callback(sdhi_instance_ctrl_t * p_ctrl); + +void sdhimmc_accs_isr(void); + +void sdhimmc_card_isr(void); + +void sdhimmc_dma_req_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** SDMMC function pointers */ +const sdmmc_api_t g_sdmmc_on_sdhi = +{ + .open = R_SDHI_Open, + .mediaInit = R_SDHI_MediaInit, + .read = R_SDHI_Read, + .write = R_SDHI_Write, + .readIo = R_SDHI_ReadIo, + .writeIo = R_SDHI_WriteIo, + .readIoExt = R_SDHI_ReadIoExt, + .writeIoExt = R_SDHI_WriteIoExt, + .ioIntEnable = R_SDHI_IoIntEnable, + .statusGet = R_SDHI_StatusGet, + .erase = R_SDHI_Erase, + .callbackSet = R_SDHI_CallbackSet, + .close = R_SDHI_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup SDHI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens the driver. Resets SDHI, and enables card detection interrupts if card detection is enabled. + * @ref R_SDHI_MediaInit must be called after this function before any other functions can be used. + * + * Implements @ref sdmmc_api_t::open(). + * + * Example: + * @snippet r_sdhi_example.c R_SDHI_Open + * + * @retval FSP_SUCCESS Module is now open. + * @retval FSP_ERR_ASSERTION Null Pointer or block size is not in the valid range of 1-512. Block size + * must be 512 bytes for SD cards and eMMC devices. + * @retval FSP_ERR_ALREADY_OPEN Driver has already been opened with this instance of the control + * structure. + * @retval FSP_ERR_IRQ_BSP_DISABLED Access interrupt is not enabled. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel does not exist on this MCU. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_Open (sdmmc_ctrl_t * const p_api_ctrl, sdmmc_cfg_t const * const p_cfg) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + err = r_sdhi_open_param_check(p_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Open the transfer driver. Clear the transfer length in case the transfer_info_t structure is reused and the + * length was copied to the upper 8 bits for block mode. Configurations are updated before it is used. */ + p_cfg->p_lower_lvl_transfer->p_cfg->p_info->transfer_settings_word = 0U; + err = p_cfg->p_lower_lvl_transfer->p_api->open(p_cfg->p_lower_lvl_transfer->p_ctrl, + p_cfg->p_lower_lvl_transfer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Initialize control block. */ + memset(p_ctrl, 0, sizeof(*p_ctrl)); +#if BSP_FEATURE_SDHI_VALID_CHANNEL_MASK > 1U + p_ctrl->p_reg = p_cfg->channel ? R_SDHI1 : R_SDHI0; +#else + p_ctrl->p_reg = R_SDHI0; +#endif + p_ctrl->p_cfg = p_cfg; + + /* Clear module stop bit (turn module on). */ + R_BSP_MODULE_START(FSP_IP_SDHIMMC, p_cfg->channel); + + /* Reset stale interrupt flags */ + p_ctrl->p_reg->SD_INFO1 = 0U; + + /* Reset SDHI. */ + p_ctrl->p_reg->SOFT_RST = 0x0U; + p_ctrl->p_reg->SOFT_RST = 0x1U; + + /* Configure card detection. */ + if (SDMMC_CARD_DETECT_CD == p_ctrl->p_cfg->card_detect) + { + p_ctrl->p_reg->SD_INFO1_MASK = SDHI_PRV_SD_INFO1_MASK_CD_ENABLE; + } + else + { + p_ctrl->p_reg->SD_INFO1_MASK = SDHI_PRV_SD_INFO1_MASK_MASK_ALL; + } + + /* Set callback and context pointers, if configured */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + /* Configure and enable interrupts. */ + R_BSP_IrqCfgEnable(p_cfg->access_irq, p_cfg->access_ipl, p_ctrl); + r_sdhi_irq_enable(p_cfg->card_irq, p_cfg->card_ipl, p_ctrl); + r_sdhi_irq_enable(p_cfg->dma_req_irq, p_cfg->dma_req_ipl, p_ctrl); + + p_ctrl->initialized = false; + p_ctrl->open = SDHI_PRV_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Initializes the SDHI hardware and completes identification and configuration for the SD or eMMC device. This + * procedure requires several sequential commands. This function blocks until all identification and configuration + * commands are complete. + * + * Implements @ref sdmmc_api_t::mediaInit(). + * + * Example: + * @snippet r_sdhi_example.c R_SDHI_MediaInit + * + * @retval FSP_SUCCESS Module is now ready for read/write access. + * @retval FSP_ERR_ASSERTION Null Pointer or block size is not in the valid range of 1-512. Block size must + * be 512 bytes for SD cards and eMMC devices. + * @retval FSP_ERR_NOT_OPEN Driver has not been initialized. + * @retval FSP_ERR_CARD_INIT_FAILED Device was not identified as an SD card or eMMC device. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_MediaInit (sdmmc_ctrl_t * const p_api_ctrl, sdmmc_device_t * const p_device) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SDHI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Device is not initialized until this function completes. */ + p_ctrl->initialized = false; + + /* Configure SDHI peripheral. */ + err = r_sdhi_hw_cfg(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Perform the identification procedure for SD card or eMMC device. */ + err = r_sdhi_card_identify(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Configure bus clock, block size, and bus width. */ + err = r_sdhi_bus_cfg(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check to see if the card is write protected (SD cards only). */ +#if SDHI_CFG_SD_SUPPORT_ENABLE + r_sdhi_write_protect_get(p_ctrl); +#endif + + /* Return device information to user. */ + p_ctrl->device.sector_size_bytes = p_ctrl->p_cfg->block_size; + if (NULL != p_device) + { + *p_device = p_ctrl->device; + } + + p_ctrl->initialized = true; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads data from an SD or eMMC device. Up to 0x10000 sectors can be read at a time. Implements @ref sdmmc_api_t::read(). + * + * A callback with the event SDMMC_EVENT_TRANSFER_COMPLETE is called when the read data is available. + * + * Example: + * @snippet r_sdhi_example.c R_SDHI_Read + * + * @retval FSP_SUCCESS Data read successfully. + * @retval FSP_ERR_ASSERTION NULL pointer. + * @retval FSP_ERR_NOT_OPEN Driver has not been initialized. + * @retval FSP_ERR_CARD_NOT_INITIALIZED Card was unplugged. + * @retval FSP_ERR_DEVICE_BUSY Driver is busy with a previous operation. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_Read (sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const start_sector, + uint32_t const sector_count) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_dest); + FSP_ASSERT(sector_count <= (UINT16_MAX + 1)); +#endif + err = r_sdhi_common_error_check(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Configure the transfer interface for reading. */ + err = r_sdhi_transfer_read(p_ctrl, sector_count, p_ctrl->p_cfg->block_size, p_dest); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + uint32_t command = 0U; + uint32_t argument = start_sector; + if (!p_ctrl->sector_addressing) + { + /* Standard capacity SD cards and some eMMC devices use byte addressing. */ + argument *= p_ctrl->p_cfg->block_size; + } + + if (sector_count > 1U) + { + command = SDHI_PRV_CMD_READ_MULTIPLE_BLOCK; + } + else + { + command = SDHI_PRV_CMD_READ_SINGLE_BLOCK; + } + + r_sdhi_read_write_common(p_ctrl, sector_count, p_ctrl->p_cfg->block_size, command, argument); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes data to an SD or eMMC device. Up to 0x10000 sectors can be written at a time. Implements @ref sdmmc_api_t::write(). + * + * A callback with the event SDMMC_EVENT_TRANSFER_COMPLETE is called when the all data has been written and the device + * is no longer holding DAT0 low to indicate it is busy. + * + * Example: + * @snippet r_sdhi_example.c R_SDHI_Write + * + * @retval FSP_SUCCESS Card write finished successfully. + * @retval FSP_ERR_ASSERTION Handle or Source address is NULL. + * @retval FSP_ERR_NOT_OPEN Driver has not been initialized. + * @retval FSP_ERR_CARD_NOT_INITIALIZED Card was unplugged. + * @retval FSP_ERR_DEVICE_BUSY Driver is busy with a previous operation. + * @retval FSP_ERR_CARD_WRITE_PROTECTED SD card is Write Protected. + * @retval FSP_ERR_WRITE_FAILED Write operation failed. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_Write (sdmmc_ctrl_t * const p_api_ctrl, + uint8_t const * const p_source, + uint32_t const start_sector, + uint32_t const sector_count) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_source); + FSP_ASSERT(sector_count <= (UINT16_MAX + 1)); +#endif + err = r_sdhi_common_error_check(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Check for write protection */ + FSP_ERROR_RETURN(!p_ctrl->device.write_protected, FSP_ERR_CARD_WRITE_PROTECTED); + + /* Configure the transfer interface for writing. */ + err = r_sdhi_transfer_write(p_ctrl, sector_count, p_ctrl->p_cfg->block_size, p_source); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WRITE_FAILED); + + /* Call SDMMC protocol write function */ + uint32_t command = 0U; + uint32_t argument = start_sector; + if (!p_ctrl->sector_addressing) + { + /* Standard capacity SD cards and some eMMC devices use byte addressing. */ + argument *= p_ctrl->p_cfg->block_size; + } + + if (sector_count > 1U) + { + command = SDHI_PRV_CMD_WRITE_MULTIPLE_BLOCK; + } + else + { + command = SDHI_PRV_CMD_WRITE_SINGLE_BLOCK; + } + + /* Casting to uint16_t safe because block size verified in R_SDHI_Open */ + r_sdhi_read_write_common(p_ctrl, sector_count, p_ctrl->p_cfg->block_size, command, argument); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * The Read function reads a one byte register from an SDIO card. Implements @ref sdmmc_api_t::readIo(). + * + * @note This function is not supported. + * + * @retval FSP_ERR_UNSUPPORTED SDIO is not supported. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_ReadIo (sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_data, + uint32_t const function, + uint32_t const address) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_data); + FSP_PARAMETER_NOT_USED(function); + FSP_PARAMETER_NOT_USED(address); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * Writes a one byte register to an SDIO card. Implements @ref sdmmc_api_t::writeIo(). + * + * @note This function is not supported. + * + * @retval FSP_ERR_UNSUPPORTED SDIO is not supported. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_WriteIo (sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_data, + uint32_t const function, + uint32_t const address, + sdmmc_io_write_mode_t const read_after_write) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_data); + FSP_PARAMETER_NOT_USED(function); + FSP_PARAMETER_NOT_USED(address); + FSP_PARAMETER_NOT_USED(read_after_write); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * Reads data from an SDIO card function. Implements @ref sdmmc_api_t::readIoExt(). + * + * @note This function is not supported. + * + * @retval FSP_ERR_UNSUPPORTED SDIO is not supported. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_ReadIoExt (sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const function, + uint32_t const address, + uint32_t * const count, + sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(function); + FSP_PARAMETER_NOT_USED(address); + FSP_PARAMETER_NOT_USED(count); + FSP_PARAMETER_NOT_USED(transfer_mode); + FSP_PARAMETER_NOT_USED(address_mode); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * Writes data to an SDIO card function. Implements @ref sdmmc_api_t::writeIoExt(). + * + * @note This function is not supported. + * + * @retval FSP_ERR_UNSUPPORTED SDIO is not supported. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_WriteIoExt (sdmmc_ctrl_t * const p_api_ctrl, + uint8_t const * const p_source, + uint32_t const function, + uint32_t const address, + uint32_t const count, + sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_source); + FSP_PARAMETER_NOT_USED(function); + FSP_PARAMETER_NOT_USED(address); + FSP_PARAMETER_NOT_USED(count); + FSP_PARAMETER_NOT_USED(transfer_mode); + FSP_PARAMETER_NOT_USED(address_mode); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * Enables or disables the SDIO Interrupt. Implements @ref sdmmc_api_t::ioIntEnable(). + * + * @note This function is not supported. + * + * @retval FSP_ERR_UNSUPPORTED SDIO is not supported. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_IoIntEnable (sdmmc_ctrl_t * const p_api_ctrl, bool enable) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(enable); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * Provides driver status. Implements @ref sdmmc_api_t::statusGet(). + * + * @retval FSP_SUCCESS Status stored in p_status. + * @retval FSP_ERR_ASSERTION NULL pointer. + * @retval FSP_ERR_NOT_OPEN Driver has not been initialized. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_StatusGet (sdmmc_ctrl_t * const p_api_ctrl, sdmmc_status_t * const p_status) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + + /* Check pointers for NULL values */ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + + FSP_ERROR_RETURN(SDHI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Check CD pin. */ + if (SDMMC_CARD_DETECT_CD == p_ctrl->p_cfg->card_detect) + { + p_status->card_inserted = p_ctrl->p_reg->SD_INFO1_b.SDCDMON; + } + else + { + p_status->card_inserted = true; + } + + /* Whether or not the media is initialized. */ + p_status->initialized = p_ctrl->initialized; + + /* Check if the card is busy. */ + p_status->transfer_in_progress = + (SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_VAL != + (p_ctrl->p_reg->SD_INFO2 & SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_MASK)); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Erases sectors of an SD card or eMMC device. Implements @ref sdmmc_api_t::erase(). + * + * This function blocks until the erase command is sent. Poll the status to determine when erase is complete. + * + * @retval FSP_SUCCESS Erase operation requested. + * @retval FSP_ERR_ASSERTION A required pointer is NULL or an argument is invalid. + * @retval FSP_ERR_NOT_OPEN Driver has not been initialized. + * @retval FSP_ERR_CARD_NOT_INITIALIZED Card was unplugged. + * @retval FSP_ERR_CARD_WRITE_PROTECTED SD card is Write Protected. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is + * ongoing. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_Erase (sdmmc_ctrl_t * const p_api_ctrl, uint32_t const start_sector, uint32_t const sector_count) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + + fsp_err_t err = FSP_SUCCESS; + uint32_t start_address; + uint32_t end_address; + uint32_t start_command; + uint32_t end_command; + uint32_t argument; + + err = r_sdhi_erase_error_check(p_ctrl, start_sector, sector_count); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* SDHC, SDXC and eMMC high capacity media use block addressing. */ + if (true == p_ctrl->sector_addressing) + { + start_address = start_sector; + end_address = ((start_sector + sector_count) - 1); + } + else + { + start_address = (start_sector * p_ctrl->p_cfg->block_size); + end_address = ((start_sector + sector_count) * p_ctrl->p_cfg->block_size) - 1U; + } + +#if SDHI_CFG_EMMC_SUPPORT_ENABLE + if (SDMMC_CARD_TYPE_MMC == p_ctrl->device.card_type) + { + start_command = SDHI_PRV_CMD_TAG_ERASE_GROUP_START; + end_command = SDHI_PRV_CMD_TAG_ERASE_GROUP_END; + argument = SDHI_PRV_EMMC_ERASE_ARGUMENT_TRIM; + } + else +#endif + { + start_command = SDHI_PRV_CMD_ERASE_WR_BLK_START; + end_command = SDHI_PRV_CMD_ERASE_WR_BLK_END; + argument = 0U; // Argument unused for SD + } + + /* Send command to set start erase address (CMD35 for eMMC, CMD32 for SD). */ + err = r_sdhi_command_send(p_ctrl, start_command, start_address); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Send command to set end erase address (CMD36 for eMMC, CMD33 for SD). */ + err = r_sdhi_command_send(p_ctrl, end_command, end_address); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Send erase command (CMD38). */ + r_sdhi_command_send_no_wait(p_ctrl, SDHI_PRV_CMD_ERASE, argument); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref sdmmc_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_CallbackSet (sdmmc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(sdmmc_callback_args_t *), + void * const p_context, + sdmmc_callback_args_t * const p_callback_memory) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SDHI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SDHI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + sdmmc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(sdmmc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes an open SD/MMC device. Implements @ref sdmmc_api_t::close(). + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Driver has not been initialized. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_Close (sdmmc_ctrl_t * const p_api_ctrl) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + + FSP_ERROR_RETURN(SDHI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->open = 0U; + + /* Disable SDHI interrupts. */ + r_sdhi_irq_disable(p_ctrl->p_cfg->access_irq); + r_sdhi_irq_disable(p_ctrl->p_cfg->card_irq); + + /* Put the card in idle state (CMD0). */ + r_sdhi_command_send_no_wait(p_ctrl, SDHI_PRV_CMD_GO_IDLE_STATE, 0); + + /* Close the transfer driver. */ + p_ctrl->p_cfg->p_lower_lvl_transfer->p_api->close(p_ctrl->p_cfg->p_lower_lvl_transfer->p_ctrl); + + /* Do not set the module stop bit since the CMD0 may not be complete yet. Do not wait for CMD0 to complete because + * the card could be unplugged and waiting for the response timeout in this function is not desirable. */ + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SDMMC) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking for the open function. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] p_cfg Pointer to the instance configuration structure. + * + * @retval FSP_SUCCESS Parameters to open() are in the valid range. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL, or the block size is 0 or > 512 bytes. + * @retval FSP_ERR_ALREADY_OPEN Driver has already been opened with this instance of the control + * structure. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel does not exist on this MCU. + * @retval FSP_ERR_IRQ_BSP_DISABLED Access interrupt is not enabled. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_open_param_check (sdhi_instance_ctrl_t * p_ctrl, sdmmc_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_lower_lvl_transfer); + FSP_ERROR_RETURN(SDHI_PRV_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Verify the requested channel exists on the MCU. */ + FSP_ERROR_RETURN(0U != ((1U << p_cfg->channel) & BSP_FEATURE_SDHI_VALID_CHANNEL_MASK), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Some MCUs don't support card detection. */ + #if !BSP_FEATURE_SDHI_HAS_CARD_DETECTION + FSP_ASSERT(SDMMC_CARD_DETECT_NONE == p_cfg->card_detect); + #endif + + /* Some MCUs don't support 8-bit MMC. */ + #if !BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC + FSP_ASSERT(SDMMC_BUS_WIDTH_8_BITS != p_cfg->bus_width); + #endif + + /* SD and eMMC cards only support block size of 512 bytes on the SDHI hardware. */ + FSP_ASSERT(SDHI_MAX_BLOCK_SIZE == p_cfg->block_size); + + /* Access interrupt is required. */ + FSP_ERROR_RETURN(p_cfg->access_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Parameter checking for erase. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] start_sector First sector to write + * @param[in] sector_count Number of sectors to write + * + * @retval FSP_SUCCESS Erase operation requested. + * @retval FSP_ERR_ASSERTION A required pointer is NULL or an argument is invalid. + * @retval FSP_ERR_NOT_OPEN Driver has not been initialized. + * @retval FSP_ERR_CARD_NOT_INITIALIZED Card was unplugged. + * @retval FSP_ERR_DEVICE_BUSY Driver is busy with a previous operation. + * @retval FSP_ERR_CARD_WRITE_PROTECTED SD card is Write Protected. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_erase_error_check (sdhi_instance_ctrl_t * const p_ctrl, + uint32_t const start_sector, + uint32_t const sector_count) +{ + fsp_err_t err = r_sdhi_common_error_check(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + + /* Check for valid sector count. Must be a non-zero multiple of erase_sector_count. */ + + FSP_ASSERT(0U != sector_count); + FSP_ASSERT(0U == (sector_count % p_ctrl->device.erase_sector_count)); + + /* Check for valid start sector. Must be a multiple of erase_sector_count. */ + FSP_ASSERT(0U == (start_sector % p_ctrl->device.erase_sector_count)); +#else + FSP_PARAMETER_NOT_USED(start_sector); + FSP_PARAMETER_NOT_USED(sector_count); +#endif + + /* Check for write protection */ + FSP_ERROR_RETURN(!p_ctrl->device.write_protected, FSP_ERR_CARD_WRITE_PROTECTED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Parameter checking for runtime APIs. + * + * @param[in] p_ctrl Pointer to the instance control block. + * + * @retval FSP_SUCCESS Device is ready to be accessed. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver has not been initialized. + * @retval FSP_ERR_CARD_NOT_INITIALIZED Card was unplugged. + * @retval FSP_ERR_DEVICE_BUSY Driver is busy with a previous operation. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_common_error_check (sdhi_instance_ctrl_t * const p_ctrl) +{ +#if SDHI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SDHI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* To verify no command sequence is in progress in SDHI, verify SD_INFO2.CBSY is not set. To verify the card has + * completed the requested operation, verify SD_INFO2.SDD0MON is set. */ + FSP_ERROR_RETURN(SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_VAL == + (p_ctrl->p_reg->SD_INFO2 & SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_MASK), + FSP_ERR_DEVICE_BUSY); + +#if SDHI_CFG_SD_SUPPORT_ENABLE + + /* Verify the card has not been removed since the last card initialization. */ + FSP_ERROR_RETURN(p_ctrl->initialized, FSP_ERR_CARD_NOT_INITIALIZED); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures and enables an interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context Pointer to data required in the ISR. + **********************************************************************************************************************/ +static void r_sdhi_irq_enable (IRQn_Type irq, uint8_t priority, void * p_context) +{ + if (irq >= 0) + { + R_BSP_IrqCfgEnable(irq, priority, p_context); + } +} + +/*******************************************************************************************************************//** + * Disables an interrupt. + * + * @param[in] irq Interrupt to disable. + **********************************************************************************************************************/ +static void r_sdhi_irq_disable (IRQn_Type irq) +{ + if (irq >= 0) + { + /* Disables interrupts in the NVIC. */ + R_BSP_IrqDisable(irq); + + /* Clears the control block from the vector information array. */ + R_FSP_IsrContextSet(irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Stores access interrupt flags in the control block and calls the callback. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] p_args Pointer to SDMMC callback arguments. + **********************************************************************************************************************/ +static void r_sdhi_access_irq_process (sdhi_instance_ctrl_t * p_ctrl, sdmmc_callback_args_t * p_args) +{ + uint32_t info1; + uint32_t info2; + sdhi_event_t flags; + + /* Clear stop register after access end. */ + p_ctrl->p_reg->SD_STOP_b.STP = 0U; + + /* Read interrupt flag registers. */ + info1 = p_ctrl->p_reg->SD_INFO1; + info2 = p_ctrl->p_reg->SD_INFO2; + + /* Clear interrupt flags processed in this ISR. */ + info1 &= SDHI_PRV_SDHI_INFO1_ACCESS_MASK; + info2 &= SDHI_PRV_SDHI_INFO2_MASK; + p_ctrl->p_reg->SD_INFO1 = (~info1); + p_ctrl->p_reg->SD_INFO2 = (~info2); + + /* Combine all flags in one 32 bit word. */ + flags.word = (info1 | (info2 << 16)); + + if (flags.bit.response_end) + { + p_args->event |= SDMMC_EVENT_RESPONSE; + + /* Check the R1 response. */ + if (1U == p_ctrl->p_reg->SD_STOP_b.SEC) + { + /* Get the R1 response for multiple block read and write from SD_RSP54 since the response in SD_RSP10 may + * have been overwritten by the response to CMD12. */ + p_args->response.status = p_ctrl->p_reg->SD_RSP54; + } + else + { + p_args->response.status = p_ctrl->p_reg->SD_RSP10; + } + + if (SDHI_PRV_CMD_ERASE == p_ctrl->p_reg->SD_CMD) + { + /* Determine if erase is complete or not based on DAT0. Access interrupt is not required for erase. */ + if (SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_VAL == + (p_ctrl->p_reg->SD_INFO2 & SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_MASK)) + { + p_args->event |= SDMMC_EVENT_ERASE_COMPLETE; + } + else + { + p_args->event |= SDMMC_EVENT_ERASE_BUSY; + } + } + else + { + /* Enable the access interrupt. */ + /* Disable response end interrupt (set the bit) and enable access end interrupt (clear the bit). */ + uint32_t mask = p_ctrl->p_reg->SD_INFO1_MASK; + mask &= (~SDHI_PRV_SDHI_INFO1_ACCESS_END); + mask |= SDHI_PRV_SDHI_INFO1_RESPONSE_END; + p_ctrl->p_reg->SD_INFO1_MASK = mask; + } + } + + /* Check for errors */ + if (flags.word & SDHI_PRV_ACCESS_ERROR_MASK) + { + flags.bit.event_error = 1U; + p_args->event |= SDMMC_EVENT_TRANSFER_ERROR; + p_ctrl->p_reg->SD_STOP = 1U; + + /* Disable the transfer and clear related variables since an error occurred. */ + r_sdhi_transfer_end(p_ctrl); + } + else + { + /* Check for access end */ + if (flags.bit.access_end) + { + /* All aligned transfers end here. Unaligned write transfers also end here. Unaligned read transfers end + * in the transfer callback. */ + if (SDHI_TRANSFER_DIR_READ != p_ctrl->transfer_dir) + { + /* Disable the transfer and clear related variables since the transfer is complete. */ + r_sdhi_transfer_end(p_ctrl); + p_args->event |= SDMMC_EVENT_TRANSFER_COMPLETE; + } + } + } + + /* Combine all events for each command because this flag is polled in some functions. */ + p_ctrl->sdhi_event.word |= flags.word; +} + +/*******************************************************************************************************************//** + * Send a command to the SD or eMMC device. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] command Command to send. + * @param[in] argument Argument to send with the command. + **********************************************************************************************************************/ +static void r_sdhi_command_send_no_wait (sdhi_instance_ctrl_t * p_ctrl, uint32_t command, uint32_t argument) +{ + /* Clear Status */ + p_ctrl->p_reg->SD_INFO1 = 0U; + p_ctrl->p_reg->SD_INFO2 = 0U; + p_ctrl->sdhi_event.word = 0U; + + /* Enable response end interrupt. */ + /* Disable access end interrupt and enable response end interrupt. */ + uint32_t mask = p_ctrl->p_reg->SD_INFO1_MASK; + mask &= (~SDHI_PRV_SDHI_INFO1_RESPONSE_END); + mask |= SDHI_PRV_SDHI_INFO1_ACCESS_END; + p_ctrl->p_reg->SD_INFO1_MASK = mask; + p_ctrl->p_reg->SD_INFO2_MASK = SDHI_PRV_SDHI_INFO2_MASK_CMD_SEND; + + /* Enable Clock */ + p_ctrl->p_reg->SD_CLK_CTRL |= SDHI_PRV_SDHI_PRV_SD_CLK_AUTO_CLOCK_ENABLE_MASK; + + /* Write argument, then command to the SDHI peripheral. */ + p_ctrl->p_reg->SD_ARG = argument & UINT16_MAX; + p_ctrl->p_reg->SD_ARG1 = argument >> 16; + p_ctrl->p_reg->SD_CMD = command; +} + +/*******************************************************************************************************************//** + * Send a command to the SD or eMMC device and wait for response + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] command Command to send. + * @param[in] argument Argument to send with the command. + * + * @retval FSP_SUCCESS Command sent and response received, no errors in response. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_command_send (sdhi_instance_ctrl_t * p_ctrl, uint32_t command, uint32_t argument) +{ + /* Verify the device is not busy. */ + r_sdhi_wait_for_device(p_ctrl); + + /* Send the command. */ + r_sdhi_command_send_no_wait(p_ctrl, command, argument); + + /* Wait for end of response, error or timeout */ + return r_sdhi_wait_for_event(p_ctrl, SDHI_PRV_RESPONSE_BIT, SDHI_PRV_RESPONSE_TIMEOUT_US); +} + +/*******************************************************************************************************************//** + * Set the SD clock to a rate less than or equal to the requested maximum rate. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] max_rate Maximum SD clock rate to set + * + * @retval FSP_SUCCESS SD clock rate is less than or equal to the requested maximum rate. + * @retval FSP_ERR_CARD_INIT_FAILED Timeout setting divider or operation is still too fast at maximum divider + * (unlikely). + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_max_clock_rate_set (sdhi_instance_ctrl_t * p_ctrl, uint32_t max_rate) +{ + uint32_t setting = SDHI_PRV_CLK_CTRL_DIV_INVALID; + + /* Get the runtime frequency of the source of the SD clock */ + uint32_t frequency = R_FSP_SystemClockHzGet(BSP_FEATURE_SDHI_CLOCK); + + /* Iterate over all possible divisors, starting with the smallest, until the resulting clock rate is less than + * or equal to the requested maximum rate. */ + for (uint32_t divisor_shift = BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT; + divisor_shift <= SDHI_PRV_MAX_CLOCK_DIVISION_SHIFT; + divisor_shift++) + { + if ((frequency >> divisor_shift) <= max_rate) + { + /* If the calculated frequency is less than or equal to the maximum supported by the device, + * select this frequency. The register setting is the divisor value divided by 4, or 0xFF for no divider. */ + setting = divisor_shift ? ((1U << divisor_shift) >> 2U) : UINT8_MAX; + + /* Set the clock setting. */ + + /* The clock register is accessible 8 SD clock counts after the last command completes. Each register access + * requires at least one PCLK count, so check the register up to 8 times the maximum PCLK divisor value (512). */ + uint32_t timeout = SDHI_PRV_SD_CLK_CTRLEN_TIMEOUT; + + while (timeout > 0U) + { + /* Do not write to clock control register until this bit is set. */ + if (p_ctrl->p_reg->SD_INFO2_b.SD_CLK_CTRLEN) + { + /* Set the calculated divider and enable clock output to start the 74 clocks required before + * initialization. Do not change the automatic clock control setting. */ + uint32_t clkctrlen = p_ctrl->p_reg->SD_CLK_CTRL & SDHI_PRV_SDHI_PRV_SD_CLK_CTRL_CLKCTRLEN_MASK; + p_ctrl->p_reg->SD_CLK_CTRL = setting | clkctrlen | SDHI_PRV_SDHI_PRV_SD_CLK_CTRL_CLKEN_MASK; + p_ctrl->device.clock_rate = frequency >> divisor_shift; + + return FSP_SUCCESS; + } + + timeout--; + } + + /* Valid setting already found, stop looking. */ + break; + } + } + + return FSP_ERR_CARD_INIT_FAILED; +} + +/*******************************************************************************************************************//** + * Initializes SD host interface hardware. + * + * @param[in] p_ctrl Pointer to the instance control block. + * + * @retval FSP_SUCCESS Operation completed successfully. + * @retval FSP_ERR_CARD_INIT_FAILED Timeout setting divider or operation is still too fast at maximum divider + * (unlikely). + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_hw_cfg (sdhi_instance_ctrl_t * const p_ctrl) +{ + /* Reset SDHI. */ + p_ctrl->p_reg->SOFT_RST = 0x0U; + p_ctrl->p_reg->SOFT_RST = 0x1U; + + /* Execute software reset or check SD_INFO2.SD_CLK_CTRLEN prior to calling this function. */ + p_ctrl->p_reg->SD_CLK_CTRL = SDHI_PRV_SD_CLK_CTRL_DEFAULT; // Automatic clock control disabled. + p_ctrl->p_reg->SDIO_MODE = 0x00U; // SDIO not supported. + p_ctrl->p_reg->SD_DMAEN = 0x00U; // Not in DMA mode initially. + p_ctrl->p_reg->SDIF_MODE = 0x00U; // CRC check is valid. + p_ctrl->p_reg->EXT_SWAP = 0x00U; // Don't swap endianness + + /* Set the clock frequency to 400 kHz or less for identification. */ + fsp_err_t err = r_sdhi_max_clock_rate_set(p_ctrl, SDHI_PRV_INIT_MAX_CLOCK_RATE_HZ); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set initial bus width to one bit wide. */ + p_ctrl->p_reg->SD_OPTION = SDHI_PRV_SD_OPTION_DEFAULT | + (SDHI_PRV_BUS_WIDTH_1_BIT << SDHI_PRV_SD_OPTION_WIDTH8_BIT); + + /* The host shall supply at least 74 SD clocks to the SD card while keeping CMD line high. Reference section + * 6.4.1.1 "Power Up Time of Card" in the SD Physical Layer Specification Version 6.00. */ + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MILLISECONDS); + + /* Automatic clock control can be enabled only after 74 SD/MMC clock cycles are output. See + * "Automatic Control of SD/MMC Clock Output (SD/MMC)" in the SDHI section of the relevant hardware manual. */ + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Initializes driver and device. + * + * @param[in] p_ctrl Pointer to the instance control block. + * + * @retval FSP_SUCCESS Operation completed successfully. + * @retval FSP_ERR_CARD_INIT_FAILED Device could not be identified. + * @retval FSP_ERR_ASSERTION Card detection configured but not supported. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_card_identify (sdhi_instance_ctrl_t * const p_ctrl) +{ + /* For SD cards, follow the procedure in Figure 4-1 "SD Memory Card State Diagram (card identification mode" in + * Physical Layer Simplified Specification Version 6.00. */ + + /* For eMMC devices, follow the procedure in A.6.1 "Bus Initialization" in JEDEC Standard No. 84-B51A. */ + + /* Put the card in idle state. */ + fsp_err_t err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_GO_IDLE_STATE, 0); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + +#if SDHI_CFG_SD_SUPPORT_ENABLE || SDHI_CFG_EMMC_SUPPORT_ENABLE + #if SDHI_CFG_SD_SUPPORT_ENABLE + + /* Check to see if the device is an SD memory card (CMD8 + ACMD41). */ + err = r_sdhi_sd_card_check(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + if (SDMMC_CARD_TYPE_SD != p_ctrl->device.card_type) + #endif + { + #if SDHI_CFG_EMMC_SUPPORT_ENABLE + + /* If the device is not SD memory, check to see if it is an eMMC device (CMD1). */ + err = r_sdhi_emmc_check(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + if ((sdmmc_card_type_t) UINT8_MAX == p_ctrl->device.card_type) + { + + /* If the device is not identified as an SD memory card or eMMC, return an error. */ + return FSP_ERR_CARD_INIT_FAILED; + } + } + + /* Enter identification state (CMD2). */ + err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_ALL_SEND_CID, 0); /* send SD CMD2 */ + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Initializes bus clock, block length, and bus width. + * + * @param[in] p_ctrl Pointer to the instance control block. + * + * @retval FSP_SUCCESS Operation completed successfully. + * @retval FSP_ERR_CARD_INIT_FAILED Operation failed. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_bus_cfg (sdhi_instance_ctrl_t * const p_ctrl) +{ + /* Get relative card address (CMD3). */ + uint32_t rca; + fsp_err_t err = r_sdhi_rca_get(p_ctrl, &rca); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + +#if SDHI_CFG_SD_SUPPORT_ENABLE || SDHI_CFG_EMMC_SUPPORT_ENABLE + + /* Decode CSD register depending on version of card */ + sdmmc_priv_csd_reg_t csd_reg; + err = r_sdhi_csd_save(p_ctrl, rca, &csd_reg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Switch to transfer state (CMD7). */ + err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_SEL_DES_CARD, rca << 16); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set clock to highest supported frequency. */ + err = r_sdhi_clock_optimize(p_ctrl, rca, &csd_reg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set the block length (CMD16) to 512 bytes. */ + err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_SET_BLOCKLEN, p_ctrl->p_cfg->block_size); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set bus width. */ + err = r_sdhi_bus_width_set(p_ctrl, rca); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read or write data. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] sector_count Number of sectors to read or write. + * @param[in] sector_size Size of one sector in bytes. + * @param[in] command Command number + * @param[in] argument Argument + **********************************************************************************************************************/ +static void r_sdhi_read_write_common (sdhi_instance_ctrl_t * const p_ctrl, + uint32_t sector_count, + uint32_t sector_size, + uint32_t command, + uint32_t argument) +{ + /* Set the sector count. */ + if (sector_count > 1U) + { + p_ctrl->p_reg->SD_STOP = SDHI_PRV_SD_STOP_SD_SECCNT_ENABLE; + p_ctrl->p_reg->SD_SECCNT = sector_count; + } + else + { + p_ctrl->p_reg->SD_STOP = 0U; + } + + /* Set sector size */ + p_ctrl->p_reg->SD_SIZE = sector_size; + + /* Send command. */ + r_sdhi_command_send_no_wait(p_ctrl, command, argument); +} + +#if SDHI_CFG_SD_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Checks to see if the device is an SD card. + * + * @param[in] p_ctrl Pointer to the instance control block. + * + * @retval FSP_SUCCESS Card type is set if the device is an SD card. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_sd_card_check (sdhi_instance_ctrl_t * const p_ctrl) +{ + /* CMD8 must be sent before ACMD41. Reference Figure 4-1 "SD Memory Card State Diagram (card identification mode)" + * in the SD Physical Layer Specification Version 6.00. */ + uint32_t argument = ((SDHI_PRV_IF_COND_VOLTAGE << 8) | SDHI_PRV_IF_COND_CHECK_PATTERN); + fsp_err_t err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_IF_COND, argument); + if (FSP_ERR_TIMEOUT == err) + { + FSP_RETURN(err); + } + + /* An SD card responds to CMD8 by echoing the argument in the R7 response. An eMMC device responds to CMD8 with the + * extended CSD. If the response does not match the argument, return to check if this is an eMMC device. */ + sdmmc_response_t response; + response.status = p_ctrl->p_reg->SD_RSP10; + + /* CMD8 is not supported by spec V1.X so we have to try CMD41. */ + if ((FSP_ERR_RESPONSE == err) || (response.status == argument)) + { + /* Try to send ACMD41 for up to 1 second as long as the card is responding and initialization is not complete. + * Returns immediately if the card fails to respond to ACMD41. */ + + /* To ensure the 1 second timeout, consider that there are 48 bits in a command, 48 bits + * in a response, and 8 clock cycles minimum between commands, so there are 104 clocks minimum, + * and the maximum clock rate at this point is 400 kHz, so issue the command 400000 / 104 + * times to ensure a timeout of at least 1 second. */ + for (uint32_t i = 0U; i < SDHI_PRV_INIT_ONE_SECOND_TIMEOUT_ITERATIONS; i++) + { + /* Send App Command - CMD55 */ + err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_APP_CMD, 0U); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + uint32_t ocr = SDHI_PRV_OCR_VDD_SUPPORTED | SDHI_PRV_OCR_CAPACITY_HC; + + /* ACMD41 */ + err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_C_ACMD | SDHI_PRV_CMD_SD_SEND_OP_COND, ocr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* get response of ACMD41 (R3) */ + response.status = p_ctrl->p_reg->SD_RSP10; + + /* Initialization complete? */ + if (response.r3.power_up_status) + { + /* High capacity card ? */ + /* 0 = SDSC, 1 = SDHC or SDXC */ + p_ctrl->sector_addressing = (response.r3.card_capacity_status > 0U); + p_ctrl->device.card_type = SDMMC_CARD_TYPE_SD; + + break; + } + } + } + + return FSP_SUCCESS; +} + +#endif + +#if SDHI_CFG_EMMC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Checks to see if the device is an eMMC. + * + * @param[in] p_ctrl Pointer to the instance control block. + * + * @retval FSP_SUCCESS Card type is set if the device is an eMMC card. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_emmc_check (sdhi_instance_ctrl_t * const p_ctrl) +{ + uint32_t ocr; + sdmmc_response_t response = {0U}; + uint32_t capacity; + capacity = SDHI_PRV_OCR_CAPACITY_HC; /* SDHC cards supported */ + + /* Tries to send CMD1 for up to 1 second as long as the device is responding and initialization is not complete. + * Returns immediately if the device fails to respond to CMD1. */ + + /* To ensure the 1 second timeout, consider that there are 48 bits in a command, 48 bits in a response, and 8 clock + * cycles minimum between commands, so there are 104 clocks minimum, and the maximum clock rate at this point is 400 + * kHz, so issue the command 400000 / 104 times to ensure a timeout of at least 1 second. */ + for (uint32_t i = 0U; i < SDHI_PRV_INIT_ONE_SECOND_TIMEOUT_ITERATIONS; i++) + { + /* Format and send cmd: Volt. window is usually 0x00300000 (3.4-3.2v) */ + /* SD cards will not respond to CMD1 */ + ocr = SDHI_PRV_OCR_VDD_SUPPORTED; + ocr |= capacity; + + fsp_err_t err = r_sdhi_command_send(p_ctrl, SDHI_PRV_EMMC_SEND_OP_COND, ocr); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* get response of CMD1 */ + response.status = p_ctrl->p_reg->SD_RSP10; + + /* Initialization complete? */ + if (response.r3.power_up_status) + { + p_ctrl->sector_addressing = (response.r3.card_capacity_status > 0U); + p_ctrl->device.card_type = SDMMC_CARD_TYPE_MMC; + + return FSP_SUCCESS; + } + } + + return FSP_SUCCESS; +} + +#endif + +#if SDHI_CFG_SD_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Update write protection status in control block. + * + * @param[in] p_ctrl Pointer to the instance control block. + **********************************************************************************************************************/ +static void r_sdhi_write_protect_get (sdhi_instance_ctrl_t * const p_ctrl) +{ + /* Update write protection status in the control block if the device is a card. */ + if (p_ctrl->p_cfg->write_protect) + { + p_ctrl->device.write_protected = (p_ctrl->p_reg->SD_INFO1_b.SDWPMON == 0U); + } +} + +#endif + +/*******************************************************************************************************************//** + * Wait for the device. + * + * @param[in] p_ctrl Pointer to the instance control block. + * + * @retval FSP_SUCCESS Previous operation is complete, and SDHI is ready for the next operation. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_wait_for_device (sdhi_instance_ctrl_t * const p_ctrl) +{ + /* Wait for the device to stop holding DAT0 low. */ + uint32_t timeout = SDHI_PRV_BUSY_TIMEOUT_US; + while (SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_VAL != + (p_ctrl->p_reg->SD_INFO2 & SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_MASK)) + { + FSP_ERROR_RETURN(timeout > 0, FSP_ERR_DEVICE_BUSY); + + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); + timeout--; + } + + return FSP_SUCCESS; +} + +#if SDHI_CFG_SD_SUPPORT_ENABLE || SDHI_CFG_EMMC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Set SDHI clock to fastest allowable speed for card. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] rca Relative card address + * @param[in] p_csd_reg Pointer to card specific data. + * + * @retval FSP_SUCCESS Clock rate adjusted to the maximum speed allowed by both device and MCU. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_CARD_INIT_FAILED Timeout setting divider or operation is still too fast at maximum divider + * (unlikely). + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_clock_optimize (sdhi_instance_ctrl_t * const p_ctrl, + uint32_t rca, + sdmmc_priv_csd_reg_t * const p_csd_reg) +{ + fsp_err_t err = FSP_SUCCESS; + + uint32_t max_clock_rate = SDHI_PRV_SD_DEFAULT_CLOCK_RATE; + #if SDHI_CFG_EMMC_SUPPORT_ENABLE + if (SDMMC_CARD_TYPE_MMC == p_ctrl->device.card_type) + { + uint8_t device_type; + err = r_sdhi_csd_extended_get(p_ctrl, rca, &device_type); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + max_clock_rate = SDHI_PRV_EMMC_DEFAULT_CLOCK_RATE; + if ((SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT & device_type) > 0U) + { + /* 52 MHz high speed supported, switch to this mode (CMD6). */ + err = r_sdhi_command_send(p_ctrl, SDHI_PRV_EMMC_CMD_SWITCH_WBUSY, SDHI_PRV_EMMC_HIGH_SPEED_MODE); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + max_clock_rate = SDHI_PRV_EMMC_HIGH_SPEED_CLOCK_RATE; // Set clock rate to 52 MHz maximum + + /* Device may signal busy after CMD6. Wait for busy to clear. */ + r_sdhi_wait_for_device(p_ctrl); + } + } + else + #else + FSP_PARAMETER_NOT_USED(rca); + #endif + { + #if SDHI_CFG_SD_SUPPORT_ENABLE + + /* Ask SD card to switch to high speed if CMD6 is supported. CMD6 is supported if bit 10 of the CCC field + * in the CSD is set.*/ + if (SDHI_PRV_CSD_REG_CCC_CLASS_10_BIT == (SDHI_PRV_CSD_REG_CCC_CLASS_10_BIT & p_csd_reg->csd_v1_b.ccc)) + { + if (FSP_SUCCESS == r_sdhi_sd_high_speed(p_ctrl)) + { + max_clock_rate = SDHI_PRV_SD_HIGH_SPEED_CLOCK_RATE; // Set clock rate to 50 MHz maximum + } + } + + #else + FSP_PARAMETER_NOT_USED(p_csd_reg); + #endif + } + + err = r_sdhi_max_clock_rate_set(p_ctrl, max_clock_rate); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Waits for the access end interrupt. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] bit Bit to check in p_ctrl->sdhi_event + * @param[in] timeout_us Number of loops to check bit (at least 1 us per loop). + * + * @retval FSP_SUCCESS Requested bit (access end or response end) is set. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_wait_for_event (sdhi_instance_ctrl_t * const p_ctrl, uint32_t bit, uint32_t timeout_us) +{ + /* The event status is updated in the access interrupt. Use a local copy of the event status to make sure + * it isn't updated during the loop. */ + volatile sdhi_event_t event; + while (true) + { + /* Check for updates to the event status. */ + event.word = p_ctrl->sdhi_event.word; + + /* Return an error if a hardware error occurred. */ + if (event.bit.event_error) + { + FSP_RETURN(FSP_ERR_RESPONSE); + } + + /* If the requested bit is set, return success. */ + if (event.word & (1U << bit)) + { + return FSP_SUCCESS; + } + + /* Check for timeout. */ + timeout_us--; + if (0U == timeout_us) + { + FSP_RETURN(FSP_ERR_TIMEOUT); + } + + /* Wait 1 us for consistent loop timing. */ + R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS); + } +} + +#if SDHI_CFG_SD_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Checks to see if the SD card supports high speed. + * + * @param[in] p_ctrl Pointer to the instance control block. + * + * @retval FSP_SUCCESS SD clock set to the maximum supported by both host and device. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_INTERNAL Error in response from card during switch to high speed mode. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_sd_high_speed (sdhi_instance_ctrl_t * const p_ctrl) +{ + /* Issue CMD6 to switch to high speed. */ + fsp_err_t err = r_sdhi_read_and_block(p_ctrl, + SDHI_PRV_CMD_SWITCH, + SDHI_PRV_SD_HIGH_SPEED_MODE_SWITCH, + SDHI_PRV_SD_SWITCH_STATUS_SIZE); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Read the switch response to see if the high speed switch is supported and completed successfully. */ + uint8_t * p_read_data_8 = (uint8_t *) &p_ctrl->aligned_buff[0]; + + /* Check for successful switch. */ + if (SDHI_PRV_SD_SWITCH_HIGH_SPEED_OK == + (p_read_data_8[SDHI_PRV_SD_SWITCH_HIGH_SPEED_RESPONSE] & SDHI_PRV_SD_SWITCH_HIGH_SPEED_OK)) + { + err = FSP_SUCCESS; + } + + /* Check for error response to High speed Function. */ + if (SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR == + (p_read_data_8[SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR_RESPONSE] & + SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR)) + { + err = FSP_ERR_INTERNAL; + } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +#endif + +#if SDHI_CFG_SD_SUPPORT_ENABLE || SDHI_CFG_EMMC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Save Card Specific Data. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] rca Relative card address + * @param[out] p_csd_reg Pointer to card specific data. + * + * @retval FSP_SUCCESS Card specific data stored in provided pointer. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_csd_save (sdhi_instance_ctrl_t * const p_ctrl, + uint32_t rca, + sdmmc_priv_csd_reg_t * const p_csd_reg) +{ + /* Send CMD9 to get CSD */ + fsp_err_t err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_SEND_CSD, rca << 16); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* SDResponseR2 are bits from 8-127, first 8 MSBs are reserved */ + p_csd_reg->reg.sdrsp10 = p_ctrl->p_reg->SD_RSP10; + p_csd_reg->reg.sdrsp32 = p_ctrl->p_reg->SD_RSP32; + p_csd_reg->reg.sdrsp54 = p_ctrl->p_reg->SD_RSP54; + p_csd_reg->reg.sdrsp76 = p_ctrl->p_reg->SD_RSP76; + + /* Get the CSD version. */ + uint32_t csd_version = p_csd_reg->csd_v1_b.csd_structure; + + /* Save sector count (total number of sectors on device) and erase sector count (minimum erasable unit in + * sectors). */ + uint32_t mult; + if ((SDHI_PRV_CSD_VERSION_1_0 == csd_version) || (SDMMC_CARD_TYPE_MMC == p_ctrl->device.card_type)) + { + mult = (1U << (p_csd_reg->csd_v1_b.c_size_mult + 2)); + p_ctrl->device.sector_count = ((p_csd_reg->csd_v1_b.c_size + 1U) * mult); + + /* Scale the sector count by the actual block size. */ + uint32_t read_sector_size = 1U << p_csd_reg->csd_v1_b.read_bl_len; + p_ctrl->device.sector_count = p_ctrl->device.sector_count * (read_sector_size / SDHI_MAX_BLOCK_SIZE); + + if (SDMMC_CARD_TYPE_MMC == p_ctrl->device.card_type) + { + /* If c_size is 0xFFF, then sector_count should be obtained from the extended CSD. Set it to 0 to indicate it + * should come from the extended CSD later. */ + if (SDHI_PRV_SECTOR_COUNT_IN_EXT_CSD == p_csd_reg->csd_v1_b.c_size) + { + p_ctrl->device.sector_count = 0U; + } + } + } + + #if SDHI_CFG_SD_SUPPORT_ENABLE + else if (SDHI_PRV_CSD_VERSION_2_0 == csd_version) + { + p_ctrl->device.sector_count = (p_csd_reg->csd_v2_b.c_size + 1U) * SDHI_PRV_BYTES_PER_KILOBYTE; + } + else + { + /* Do Nothing */ + } + + if (SDHI_PRV_CSD_VERSION_1_0 == csd_version) + { + /* Get the minimum erasable unit (in 512 byte sectors). */ + p_ctrl->device.erase_sector_count = p_csd_reg->csd_v1_b.sector_size + 1U; + } + else + #endif + { + /* For SDHC and SDXC cards, there are no erase group restrictions. + * + * Using the eMMC TRIM operation, there are no erase group restrictions. */ + p_ctrl->device.erase_sector_count = 1U; + } + + return FSP_SUCCESS; +} + +#endif + +#if SDHI_CFG_EMMC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Get and store relevant extended card specific data. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] rca Relative card address + * @param[out] p_device_type Pointer to store device type, which is used to determine if high speed is supported. + * + * @retval FSP_SUCCESS Device type obtained from eMMC extended CSD. Sector count is also calculated here + * if it was not determined previously. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_csd_extended_get (sdhi_instance_ctrl_t * const p_ctrl, uint32_t rca, uint8_t * p_device_type) +{ + /* Ask card to send extended CSD (CMD8). */ + fsp_err_t err = + r_sdhi_read_and_block(p_ctrl, SDHI_PRV_EMMC_CMD_SEND_EXT_CSD, rca << 16, SDHI_PRV_EMMC_EXT_CSD_SIZE); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Store device type. Also store sector count if it is not already determined. */ + uint8_t * p_read_data_8 = (uint8_t *) &p_ctrl->aligned_buff[0]; + *p_device_type = p_read_data_8[SDHI_PRV_EMMC_EXT_CSD_DEVICE_TYPE_OFFSET]; + + if (0U == p_ctrl->device.sector_count) + { + p_ctrl->device.sector_count = p_ctrl->aligned_buff[SDHI_PRV_EMMC_EXT_CSD_SEC_COUNT_OFFSET / sizeof(uint32_t)]; + } + + return FSP_SUCCESS; +} + +#endif + +#if SDHI_CFG_SD_SUPPORT_ENABLE || SDHI_CFG_EMMC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Issue command expecting data to be returned, and block until read data is returned. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] command Command to issue. + * @param[in] argument Argument to send with command. + * @param[in] byte_count Expected number of bytes to read. + * + * @retval FSP_SUCCESS Requested data read into internal buffer. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_read_and_block (sdhi_instance_ctrl_t * const p_ctrl, + uint32_t command, + uint32_t argument, + uint32_t byte_count) +{ + /* Prepare transfer interface to read. */ + fsp_err_t err = r_sdhi_transfer_read(p_ctrl, 1U, byte_count, &p_ctrl->aligned_buff[0]); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Issue command. */ + r_sdhi_read_write_common(p_ctrl, 1U, byte_count, command, argument); + + /* Wait for access end, error, or timeout. */ + return r_sdhi_wait_for_event(p_ctrl, SDHI_PRV_ACCESS_BIT, SDHI_PRV_ACCESS_TIMEOUT_US); +} + +#endif + +/*******************************************************************************************************************//** + * Gets or assigns the relative card address. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[out] p_rca Pointer to store relative card address. + * + * @retval FSP_SUCCESS Relative card address is assigned and device is in standby state. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_rca_get (sdhi_instance_ctrl_t * const p_ctrl, uint32_t * p_rca) +{ + /* Send CMD3. For eMMC, assign an RCA of SDHI channel number + 2. These bits of the argument are ignored for SD + * cards. */ + uint32_t rca = (p_ctrl->p_cfg->channel + 2U); + fsp_err_t err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_SEND_RELATIVE_ADDR, rca << 16); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + +#if SDHI_CFG_SD_SUPPORT_ENABLE + sdmmc_response_t response = {0U}; + response.status = p_ctrl->p_reg->SD_RSP10; + if (SDMMC_CARD_TYPE_MMC != p_ctrl->device.card_type) + { + /* Get relative card address from the response if the device is an SD card. */ + rca = (response.r6.rca); + } +#endif + + *p_rca = rca; + + return FSP_SUCCESS; +} + +#if SDHI_CFG_SD_SUPPORT_ENABLE || SDHI_CFG_EMMC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Set bus width. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] rca Relative card address + * + * @retval FSP_SUCCESS Bus width updated on device. + * @retval FSP_ERR_RESPONSE Device responded with an error. + * @retval FSP_ERR_TIMEOUT Device did not respond. + * @retval FSP_ERR_DEVICE_BUSY Device is holding DAT0 low (device is busy) or another operation is ongoing. + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_bus_width_set (sdhi_instance_ctrl_t * const p_ctrl, uint32_t rca) +{ + uint32_t bus_width; + uint32_t bus_width_setting; + + bus_width = p_ctrl->p_cfg->bus_width; + + #if SDHI_CFG_EMMC_SUPPORT_ENABLE + if (SDMMC_CARD_TYPE_MMC == p_ctrl->device.card_type) + { + /* For eMMC, set bus width using CMD6. */ + bus_width_setting = ((bus_width >> 2U) & 0x03U); + fsp_err_t err = r_sdhi_command_send(p_ctrl, + SDHI_PRV_EMMC_CMD_SWITCH_WBUSY, + ((0x1U << SDHI_PRV_SWITCH_ACCESS_SHIFT) | + (SDHI_PRV_EMMC_BUS_WIDTH_INDEX << + SDHI_PRV_SWITCH_INDEX_SHIFT) | + (bus_width_setting << SDHI_PRV_SWITCH_VALUE_SHIFT))); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Device may signal busy after CMD6. Wait for busy to clear. */ + r_sdhi_wait_for_device(p_ctrl); + } + else + #endif + { + #if SDHI_CFG_SD_SUPPORT_ENABLE + + /* Send CMD55, app command. */ + bus_width_setting = ((bus_width >> 1U) & 0x03U); + fsp_err_t err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_APP_CMD, rca << 16); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* For SD cards, set bus width using ACMD6. */ + err = r_sdhi_command_send(p_ctrl, SDHI_PRV_CMD_C_ACMD | SDHI_PRV_CMD_SET_BUS_WIDTH, bus_width_setting); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #else + FSP_PARAMETER_NOT_USED(rca); + #endif + } + + /* Set the bus width in the SDHI peripheral. */ + uint32_t bus_width_reg = 0U; + if (SDMMC_BUS_WIDTH_8_BITS == bus_width) + { + bus_width_reg = 1U; + } + + if (SDMMC_BUS_WIDTH_1_BIT == bus_width) + { + bus_width_reg = SDHI_PRV_BUS_WIDTH_1_BIT; + } + + p_ctrl->p_reg->SD_OPTION = SDHI_PRV_SD_OPTION_DEFAULT | (bus_width_reg << SDHI_PRV_SD_OPTION_WIDTH8_BIT); + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Performs workaround in the transfer interrupt for unaligned reads and writes. + * + * @param[in] p_ctrl Pointer to the instance control block. + **********************************************************************************************************************/ +void r_sdhi_transfer_callback (sdhi_instance_ctrl_t * p_ctrl) +{ +#if SDMMC_CFG_UNALIGNED_ACCESS_ENABLE + if (p_ctrl->transfer_blocks_total != p_ctrl->transfer_block_current) + { + if (SDHI_TRANSFER_DIR_READ == p_ctrl->transfer_dir) + { + /* If the transfer is a read operation into an unaligned buffer, copy the block read from the aligned + * buffer in the control block to the application data buffer. */ + memcpy(p_ctrl->p_transfer_data, (void *) &p_ctrl->aligned_buff[0], p_ctrl->transfer_block_size); + } + + if (SDHI_TRANSFER_DIR_WRITE == p_ctrl->transfer_dir) + { + /* If the transfer is a write operation from an unaligned buffer, copy the next block to write from the + * application data buffer to the aligned buffer in the control block. */ + memcpy((void *) &p_ctrl->aligned_buff[0], p_ctrl->p_transfer_data, p_ctrl->transfer_block_size); + } + + p_ctrl->transfer_block_current++; + p_ctrl->p_transfer_data += p_ctrl->transfer_block_size; + } + + if (p_ctrl->transfer_blocks_total == p_ctrl->transfer_block_current) + { + if (SDHI_TRANSFER_DIR_READ == p_ctrl->transfer_dir) + { + /* After the entire read transfer to an unaligned buffer is complete, read transfer end and callback are + * performed in transfer interrupt to ensure the last block is in the application buffer before the + * callback is called. */ + r_sdhi_transfer_end(p_ctrl); + + sdmmc_callback_args_t args; + memset(&args, 0U, sizeof(args)); + args.p_context = p_ctrl->p_context; + args.event |= SDMMC_EVENT_TRANSFER_COMPLETE; + r_sdhi_call_callback(p_ctrl, &args); + } + } + +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif +} + +/*******************************************************************************************************************//** + * Set up transfer to read from device. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] block_count Number of blocks to transfer. + * @param[in] bytes Bytes per block. + * @param[in] p_data Pointer to data to read data from device into. + * + * @retval FSP_SUCCESS Transfer successfully configured to write data. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * * @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_transfer_read (sdhi_instance_ctrl_t * const p_ctrl, + uint32_t block_count, + uint32_t bytes, + void * p_data) +{ + transfer_info_t * p_info = p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info; + + /* When the SD_DMAEN.DMAEN bit is 1, set the SD_INFO2_MASK.BWEM bit to 1 and the SD_INFO2_MASK.BREM bit to 1. */ + p_ctrl->p_reg->SD_INFO2_MASK |= SDHI_PRV_SD_INFO2_MASK_BREM_BWEM_MASK; + p_ctrl->p_reg->SD_DMAEN = SDHI_PRV_SD_DMAEN_DMAEN_SET; + + uint32_t transfer_settings = (uint32_t) TRANSFER_MODE_BLOCK << TRANSFER_SETTINGS_MODE_BITS; + transfer_settings |= TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS; + transfer_settings |= TRANSFER_SIZE_4_BYTE << TRANSFER_SETTINGS_SIZE_BITS; + +#if SDMMC_CFG_UNALIGNED_ACCESS_ENABLE + + /* If the pointer is not 4-byte aligned or the number of bytes is not a multiple of 4, use a temporary buffer. + * Data will be transferred from the temporary buffer into the user buffer in an interrupt after each block transfer. */ + if ((0U != ((uint32_t) p_data & 0x3U)) || (0U != (bytes & 3U))) + { + transfer_settings |= TRANSFER_IRQ_EACH << TRANSFER_SETTINGS_IRQ_BITS; + p_info->p_dest = &p_ctrl->aligned_buff[0]; + + p_ctrl->transfer_block_current = 0U; + p_ctrl->transfer_blocks_total = block_count; + p_ctrl->p_transfer_data = (uint8_t *) p_data; + p_ctrl->transfer_dir = SDHI_TRANSFER_DIR_READ; + p_ctrl->transfer_block_size = bytes; + } + else +#endif + { + transfer_settings |= TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS; + p_info->p_dest = p_data; + } + + p_info->transfer_settings_word = transfer_settings; + p_info->p_src = (uint32_t *) (&p_ctrl->p_reg->SD_BUF0); + p_info->num_blocks = (uint16_t) block_count; + + /* Round up to the nearest multiple of 4 bytes for the transfer. */ + uint32_t words = (bytes + (sizeof(uint32_t) - 1U)) / sizeof(uint32_t); + p_info->length = (uint16_t) words; + + /* Configure the transfer driver to read from the SD buffer. */ + fsp_err_t err = p_ctrl->p_cfg->p_lower_lvl_transfer->p_api->reconfigure(p_ctrl->p_cfg->p_lower_lvl_transfer->p_ctrl, + p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set up transfer to write to device. + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] block_count Number of blocks to transfer. + * @param[in] bytes Bytes per block. + * @param[in] p_data Pointer to data to write to device. + * + * @retval FSP_SUCCESS Transfer successfully configured to write data. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: + * * @ref transfer_api_t::reconfigure + **********************************************************************************************************************/ +static fsp_err_t r_sdhi_transfer_write (sdhi_instance_ctrl_t * const p_ctrl, + uint32_t block_count, + uint32_t bytes, + const uint8_t * p_data) +{ + transfer_info_t * p_info = p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info; + + /* When the SD_DMAEN.DMAEN bit is 1, set the SD_INFO2_MASK.BWEM bit to 1 and the SD_INFO2_MASK.BREM bit to 1. */ + p_ctrl->p_reg->SD_INFO2_MASK |= SDHI_PRV_SD_INFO2_MASK_BREM_BWEM_MASK; + p_ctrl->p_reg->SD_DMAEN = SDHI_PRV_SD_DMAEN_DMAEN_SET; + + uint32_t transfer_settings = (uint32_t) TRANSFER_MODE_BLOCK << TRANSFER_SETTINGS_MODE_BITS; + transfer_settings |= TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS; + transfer_settings |= TRANSFER_SIZE_4_BYTE << TRANSFER_SETTINGS_SIZE_BITS; + +#if SDMMC_CFG_UNALIGNED_ACCESS_ENABLE + if ((0U != ((uint32_t) p_data & 0x3U)) || (0U != (bytes & 3U))) + { + transfer_settings |= TRANSFER_IRQ_EACH << TRANSFER_SETTINGS_IRQ_BITS; + transfer_settings |= TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS; + + /* If the pointer is not 4-byte aligned or the number of bytes is not a multiple of 4, use a temporary buffer. + * Transfer the first block to the temporary buffer before enabling the transfer. Subsequent blocks will be + * transferred from the user buffer to the temporary buffer in an interrupt after each block transfer. */ + memcpy((void *) &p_ctrl->aligned_buff[0], p_data, bytes); + p_info->p_src = &p_ctrl->aligned_buff[0]; + + p_ctrl->transfer_block_current = 1U; + p_ctrl->transfer_blocks_total = block_count; + p_ctrl->p_transfer_data = (uint8_t *) &p_data[bytes]; + p_ctrl->transfer_dir = SDHI_TRANSFER_DIR_WRITE; + p_ctrl->transfer_block_size = bytes; + } + else +#endif + { + p_info->p_src = p_data; + } + + p_info->transfer_settings_word = transfer_settings; + p_info->p_dest = (uint32_t *) (&p_ctrl->p_reg->SD_BUF0); + p_info->num_blocks = (uint16_t) block_count; + + /* Round up to the nearest multiple of 4 bytes for the transfer. */ + uint32_t words = (bytes + (sizeof(uint32_t) - 1U)) / sizeof(uint32_t); + p_info->length = (uint16_t) words; + + /* Configure the transfer driver to write to the SD buffer. */ + fsp_err_t err = p_ctrl->p_cfg->p_lower_lvl_transfer->p_api->reconfigure(p_ctrl->p_cfg->p_lower_lvl_transfer->p_ctrl, + p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Close transfer driver, clear transfer data, and disable transfer in the SDHI peripheral. + * + * @param[in] p_ctrl Pointer to the instance control block. + **********************************************************************************************************************/ +static void r_sdhi_transfer_end (sdhi_instance_ctrl_t * const p_ctrl) +{ + p_ctrl->transfer_block_current = 0U; + p_ctrl->transfer_blocks_total = 0U; + p_ctrl->p_transfer_data = NULL; + p_ctrl->transfer_dir = SDHI_TRANSFER_DIR_NONE; + p_ctrl->transfer_block_size = 0U; + + p_ctrl->p_cfg->p_lower_lvl_transfer->p_api->disable(p_ctrl->p_cfg->p_lower_lvl_transfer->p_ctrl); + p_ctrl->p_reg->SD_DMAEN = 0U; +} + +/*******************************************************************************************************************//** + * Calls user callback + * + * @param[in] p_ctrl Pointer to the instance control block. + * @param[in] p_args Pointer to callback arguments with event and response set. + **********************************************************************************************************************/ +static void r_sdhi_call_callback (sdhi_instance_ctrl_t * p_ctrl, sdmmc_callback_args_t * p_args) +{ + /* Call user callback if provided, if an event was determined, and if the driver is initialized. */ + if (NULL != p_ctrl->p_callback) + { + sdmmc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + sdmmc_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + + p_args_memory->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sdhi_prv_ns_callback p_callback = (sdhi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } + } +} + +/*******************************************************************************************************************//** + * Calls user callback after response or data transfer complete. + **********************************************************************************************************************/ +void sdhimmc_accs_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + sdmmc_callback_args_t args; + memset(&args, 0U, sizeof(args)); + r_sdhi_access_irq_process(p_ctrl, &args); + + /* Call user callback */ + if ((p_ctrl->initialized) && (0U != args.event)) + { + r_sdhi_call_callback(p_ctrl, &args); + } + + /* Clear the IR flag in the ICU */ + /* Clearing the IR bit must be done after clearing the interrupt source in the the peripheral */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Calls user callback when card insertion or removal interrupt fires. + **********************************************************************************************************************/ +void sdhimmc_card_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + sdmmc_callback_args_t args; + memset(&args, 0U, sizeof(args)); + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + sdhi_event_t info1 = {0U}; + info1.word = p_ctrl->p_reg->SD_INFO1; + + if (0U != (info1.word & SDHI_PRV_SDHI_INFO1_CARD_REMOVED_MASK)) + { + p_ctrl->initialized = false; + args.event |= SDMMC_EVENT_CARD_REMOVED; + } + + if (0U != (info1.word & SDHI_PRV_SDHI_INFO1_CARD_INSERTED_MASK)) + { + args.event |= SDMMC_EVENT_CARD_INSERTED; + } + + /* Clear interrupt flags processed in this ISR. */ + info1.word &= SDHI_PRV_SDHI_INFO1_CARD_MASK; + p_ctrl->p_reg->SD_INFO1 = (~info1.word); + + /* Call user callback if provided */ + args.p_context = p_ctrl->p_context; + r_sdhi_call_callback(p_ctrl, &args); + + /* Clear the IR flag in the ICU */ + /* Clearing the IR bit must be done after clearing the interrupt source in the the peripheral */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * DMA ISR. Called when a DTC transfer completes. Not used for DMAC. + * + * Handles data copy for unaligned buffers and transfer complete processing. + **********************************************************************************************************************/ +void sdhimmc_dma_req_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + r_sdhi_transfer_callback(p_ctrl); + + /* Clear the IR flag in the ICU. + * This must be after the callback because the next DTC transfer will begin when this bit is cleared. */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdhi/r_sdhi_private.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdhi/r_sdhi_private.h new file mode 100644 index 0000000000..7d505a3d86 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_sdhi/r_sdhi_private.h @@ -0,0 +1,260 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +#ifndef SDHI_PRV_R_SDHI_PRIVATE_H +#define SDHI_PRV_R_SDHI_PRIVATE_H + +/********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define SDHI_PRV_CSD_VERSION_1_0 (0U) +#define SDHI_PRV_CSD_VERSION_2_0 (1U) /* value of 1 is CSD 2.0 according to SD spec. */ + +#define SDHI_PRV_CMD_GO_IDLE_STATE (0U) +#define SDHI_PRV_CMD_SEND_OP_COND (1U) +#define SDHI_PRV_CMD_ALL_SEND_CID (2U) +#define SDHI_PRV_CMD_SEND_RELATIVE_ADDR (3U) +#define SDHI_PRV_CMD_SET_BUS_WIDTH (6U) +#define SDHI_PRV_CMD_SWITCH (6U) +#define SDHI_PRV_CMD_SEL_DES_CARD (7U) +#define SDHI_PRV_CMD_IF_COND (8U) +#define SDHI_PRV_CMD_SEND_CSD (9U) +#define SDHI_PRV_CMD_SET_BLOCKLEN (16U) +#define SDHI_PRV_CMD_READ_SINGLE_BLOCK (17U) +#define SDHI_PRV_CMD_READ_MULTIPLE_BLOCK (18U) +#define SDHI_PRV_CMD_WRITE_SINGLE_BLOCK (24U) +#define SDHI_PRV_CMD_WRITE_MULTIPLE_BLOCK (25U) +#define SDHI_PRV_CMD_ERASE_WR_BLK_START (32U) +#define SDHI_PRV_CMD_ERASE_WR_BLK_END (33U) +#define SDHI_PRV_CMD_TAG_ERASE_GROUP_START (0x423U) +#define SDHI_PRV_CMD_TAG_ERASE_GROUP_END (0x424U) +#define SDHI_PRV_CMD_ERASE (38U) +#define SDHI_PRV_CMD_SD_SEND_OP_COND (41U) +#define SDHI_PRV_CMD_IO_RW_DIRECT (52U) +#define SDHI_PRV_CMD_IO_READ_EXT_SINGLE_BLOCK (0x1c35U) +#define SDHI_PRV_CMD_IO_EXT_MULTI_BLOCK (0x6000U) +#define SDHI_PRV_CMD_IO_WRITE_EXT_SINGLE_BLOCK (0x0c35U) + +#define SDHI_PRV_CMD_APP_CMD (55U) +#define SDHI_PRV_CMD_C_ACMD (1U << 6) /* APP Command */ + +#define SDHI_PRV_IF_COND_VOLTAGE (1U) +#define SDHI_PRV_IF_COND_CHECK_PATTERN (0xAAU) + +#define SDHI_PRV_OCR_CAPACITY_HC (1U << 30) + +#define SDHI_PRV_OCR_VDD_2_7_V (1U << 15) +#define SDHI_PRV_OCR_VDD_2_8_V (1U << 16) +#define SDHI_PRV_OCR_VDD_2_9_V (1U << 17) +#define SDHI_PRV_OCR_VDD_3_0_V (1U << 18) +#define SDHI_PRV_OCR_VDD_3_1_V (1U << 19) +#define SDHI_PRV_OCR_VDD_3_2_V (1U << 20) +#define SDHI_PRV_OCR_VDD_3_3_V (1U << 21) +#define SDHI_PRV_OCR_VDD_3_4_V (1U << 22) +#define SDHI_PRV_OCR_VDD_3_5_V (1U << 23) +#define SDHI_PRV_OCR_VDD_SUPPORTED \ + (SDHI_PRV_OCR_VDD_2_7_V | SDHI_PRV_OCR_VDD_2_8_V | SDHI_PRV_OCR_VDD_2_9_V | SDHI_PRV_OCR_VDD_3_0_V | \ + SDHI_PRV_OCR_VDD_3_1_V | \ + SDHI_PRV_OCR_VDD_3_2_V | SDHI_PRV_OCR_VDD_3_3_V | SDHI_PRV_OCR_VDD_3_4_V | SDHI_PRV_OCR_VDD_3_5_V) + +/* SWITCH command argument's bit position */ +#define SDHI_PRV_SWITCH_ACCESS_SHIFT (24U) +#define SDHI_PRV_SWITCH_INDEX_SHIFT (16U) +#define SDHI_PRV_SWITCH_VALUE_SHIFT (8U) + +#define SDHI_PRV_EMMC_EXT_CSD_SIZE (512U) + +/* Offsets */ +#define SDHI_PRV_EMMC_EXT_CSD_HS_TIMING_OFFSET (185U) +#define SDHI_PRV_EMMC_EXT_CSD_DEVICE_TYPE_OFFSET (196U) +#define SDHI_PRV_EMMC_EXT_CSD_SEC_COUNT_OFFSET (212U) + +/* Commands */ +#define SDHI_PRV_EMMC_SWITCH_ACCESS_WRITE_BYTE (3U) +#define SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT (2U) +#define SDHI_PRV_EMMC_HIGH_SPEED_MODE (((SDHI_PRV_EMMC_SWITCH_ACCESS_WRITE_BYTE << 24U) | \ + (SDHI_PRV_EMMC_EXT_CSD_HS_TIMING_OFFSET << 16U)) | \ + (SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT << 8U)) + +#define SDHI_PRV_SD_SWITCH_STATUS_SIZE (64U) +#define SDHI_PRV_SD_SWITCH_HIGH_SPEED_RESPONSE (13U) +#define SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR_RESPONSE (16U) +#define SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR (0x0fU) +#define SDHI_PRV_SD_SWITCH_HIGH_SPEED_OK (0x02U) + +#define SDHI_PRV_EMMC_SEND_OP_COND (0x701U) +#define SDHI_PRV_EMMC_CMD_SWITCH_WBUSY (0x506U) /* eMMC CMD6 switch command "with response busy" */ +#define SDHI_PRV_EMMC_CMD_SEND_EXT_CSD (0x1C08U) /* CMD 8, read data */ +#define SDHI_PRV_EMMC_DEFAULT_CLOCK_RATE (26000000U) /* 26 MHz */ +#define SDHI_PRV_EMMC_HIGH_SPEED_CLOCK_RATE (52000000U) /* 52 MHz */ +#define SDHI_PRV_SD_HIGH_SPEED_MODE_SWITCH (0x80FFFFF1U) /* set SD high speed */ +#define SDHI_PRV_SD_DEFAULT_CLOCK_RATE (25000000U) /* 25 MHz */ +#define SDHI_PRV_SD_HIGH_SPEED_CLOCK_RATE (50000000U) /* 50 MHz */ + +#define SDHI_PRV_EMMC_ERASE_ARGUMENT_TRIM (1U) + +#define SDHI_PRV_CSD_CID_SERIAL_NUMBER_BITS (32) +#define SDHI_PRV_CSD_CID_PRODUCT_NAME_BITS (40) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef enum e_sdmmc_priv_sd_state +{ + SDMMC_PRIV_SD_STATE_IDLE, + SDMMC_PRIV_SD_STATE_READY, + SDMMC_PRIV_SD_STATE_IDENT, + SDMMC_PRIV_SD_STATE_STBY, + SDMMC_PRIV_SD_STATE_TRANSFER, + SDMMC_PRIV_SD_STATE_DATA, + SDMMC_PRIV_SD_STATE_RCV, + SDMMC_PRIV_SD_STATE_PROG, + SDMMC_PRIV_SD_STATE_DIS, + SDMMC_PRIV_SD_STATE_RSVD9, + SDMMC_PRIV_SD_STATE_RSVD10, + SDMMC_PRIV_SD_STATE_RSVD11, + SDMMC_PRIV_SD_STATE_RSVD12, + SDMMC_PRIV_SD_STATE_RSVD13, + SDMMC_PRIV_SD_STATE_RSVD14, + SDMMC_PRIV_SD_STATE_RSVD15 +} sdmmc_priv_sd_state_t; + +/** SDMMC card specific data */ +typedef struct st_sdmmc_priv_csd_reg +{ + union + { + uint8_t array[16]; + + /* All structures in this union must be packed since some bitfields span more than one 32-bit word. */ +#if defined(__ICCARM__) + __packed struct +#elif defined(__GNUC__) + struct __attribute__((__packed__)) +#endif + { + volatile uint32_t sdrsp10; + volatile uint32_t sdrsp32; + volatile uint32_t sdrsp54; + volatile uint32_t sdrsp76; + } reg; + + /* All structures in this union must be packed since some bitfields span more than one 32-bit word. */ +#if defined(__ICCARM__) + __packed struct +#elif defined(__GNUC__) + struct __attribute__((__packed__)) +#endif + { + uint32_t reserved_8 : 2; ///< [9:8] + uint32_t file_format : 2; ///< [11:10] file format + uint32_t tmp_write_protect : 1; ///< [12] temporary write protection + uint32_t perm_write_protect : 1; ///< [13] permanent write protection + uint32_t copy : 1; ///< [14] copy flag + uint32_t file_format_grp : 1; ///< [15] file format group + uint32_t reserved_20 : 5; ///< [16-20] + uint32_t write_bl_partial : 1; ///< [21] partial blocks for write allowed + uint32_t write_bl_len : 4; ///< [25:22] max. write data block length + uint32_t r2w_factor : 3; ///< [28:26] write speed factor + uint32_t reserved_29 : 2; ///< [30:29] + uint32_t wp_grp_enable : 1; ///< [31] write protect group enable + uint32_t wp_grp_size : 7; ///< [38:32] write protect group size + uint32_t sector_size : 7; ///< [45:39] erase sector size + uint32_t erase_blk_en : 1; ///< [46] erase single block enable + uint32_t c_size_mult : 3; ///< [49:47] device size multiplier*/ + uint32_t vdd_w_curr_max : 3; ///< [52:50] max. write current for vdd max + uint32_t vdd_w_curr_min : 3; ///< [55:53] max. write current for vdd min + uint32_t vdd_r_curr_max : 3; ///< [58:56] max. read current for vdd max + uint32_t vdd_r_curr_min : 3; ///< [61:59] max. read current for vdd min + uint32_t c_size : 12; ///< [73:62] device size + uint32_t reserved_74 : 2; ///< [75:74] + uint32_t dsr_imp : 1; ///< [76] dsr implemented + uint32_t read_blk_misalign : 1; ///< [77] read block misalignment + uint32_t write_blk_misalign : 1; ///< [78] write block misalignment + uint32_t read_bl_partial : 1; ///< [79] partial blocks for read allowed + uint32_t read_bl_len : 4; ///< [83:80] max read data block length + uint32_t ccc : 12; ///< [95:84] card command classes + uint32_t tran_speed : 8; ///< [103:96] max. data transfer rate + uint32_t nsac : 8; ///< [111:104] data read access-time-2 clk cycles + uint32_t taac : 8; ///< [119:112] data read access-time-1 + uint32_t reserved_120 : 6; ///< [125:120] + uint32_t csd_structure : 2; ///< [127:126] csd structure + uint32_t reserved_128 : 8; ///< [135:128] + } csd_v1_b; + + /* All structures in this union must be packed since some bitfields span more than one 32-bit word. */ +#if defined(__ICCARM__) + __packed struct +#elif defined(__GNUC__) + struct __attribute__((__packed__)) +#endif + { + uint32_t reserved_8 : 2; ///< [9:8] + uint32_t file_format : 2; ///< [11:10] file format + uint32_t tmp_write_protect : 1; ///< [12] temporary write protection + uint32_t perm_write_protect : 1; ///< [13] permanent write protection + uint32_t copy : 1; ///< [14] copy flag + uint32_t file_format_grp : 1; ///< [15] file format group + uint32_t reserved_20 : 5; ///< [20:16] + uint32_t write_bl_partial : 1; ///< [21] partial blocks for write allowed + uint32_t write_bl_len : 4; ///< [25:22] max. write data block length + uint32_t r2w_factor : 3; ///< [28:26] write speed factor + uint32_t reserved_29 : 2; ///< [30:29] + uint32_t wp_grp_enable : 1; ///< [31] write protect group enable + uint32_t wp_grp_size : 7; ///< [38:32] write protect group size + uint32_t sector_size : 7; ///< [45:39] erase sector size + uint32_t erase_blk_en : 1; ///< [46] erase single block enable + uint32_t reserved_47 : 1; ///< [47] + uint32_t c_size : 22; ///< [69:48] device size + uint32_t reserved_70 : 6; ///< [75:70] + uint32_t dsr_imp : 1; ///< [76] dsr implemented + uint32_t read_blk_misalign : 1; ///< [77] read block misalignment + uint32_t write_blk_misalign : 1; ///< [78] write block misalignment + uint32_t read_bl_partial : 1; ///< [79] partial blocks for read allowed + uint32_t read_bl_len : 4; ///< [83:80] max read data block length + uint32_t ccc : 12; ///< [95:84] card command classes + uint32_t tran_speed : 8; ///< [103:96] max. data transfer rate + uint32_t nsac : 8; ///< [111:104] data read access-time-2 clk cycles + uint32_t taac : 8; ///< [119:112] data read access-time-1 + uint32_t reserved_120 : 6; ///< [125:120] + uint32_t csd_structure : 2; ///< [127:126] csd structure + uint32_t reserved_128 : 8; ///< [135:128] + } csd_v2_b; + + /* All structures in this union must be packed since some bitfields span more than one 32-bit word. */ +#if defined(__ICCARM__) + __packed struct +#elif defined(__GNUC__) + struct __attribute__((__packed__)) +#endif + { + uint32_t reserved_0 : 1; + + uint32_t crc : 7; + uint32_t mfg_date : 12; + uint32_t reserved_23 : 4; + uint32_t serial_number : SDHI_PRV_CSD_CID_SERIAL_NUMBER_BITS; + uint32_t product_revision : 8; + uint64_t product_name : SDHI_PRV_CSD_CID_PRODUCT_NAME_BITS; + uint32_t oem_id : 16; + uint32_t mfg_id : 8; + uint32_t reserved_128 : 8; + } cid; + }; +} sdmmc_priv_csd_reg_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_spi/r_spi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_spi/r_spi.c new file mode 100644 index 0000000000..d7fa60eea7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_spi/r_spi.c @@ -0,0 +1,1406 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi.h" +#include "r_spi_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "SPI" in ASCII, used to determine if channel is open. */ +#define SPI_OPEN (0x52535049ULL) + +/** SPI base register access macro. */ +#define SPI_REG(channel) ((R_SPI0_Type *) ((uint32_t) R_SPI0 + \ + ((uint32_t) R_SPI1 - (uint32_t) R_SPI0) * \ + (channel))) + +#define SPI_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SPI_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SPI_CLK_N_DIV_MULTIPLIER (512U) ///< Maximum divider for N=0 +#define SPI_CLK_MAX_DIV (4096U) ///< Maximum SPI CLK divider +#define SPI_CLK_MIN_DIV (2U) ///< Minimum SPI CLK divider + +/* SPCMD0 Bit Field Definitions */ +#define R_SPI0_SPCMD0_CPHA_Pos (0U) ///< Clock Phase setting offset +#define R_SPI0_SPCMD0_CPHA_Msk (1U << R_SPI0_SPCMD0_CPHA_Pos) ///< Clock Phase setting mask +#define R_SPI0_SPCMD0_CPOL_Pos (1U) ///< Clock Polarity setting offset +#define R_SPI0_SPCMD0_CPOL_Msk (1U << R_SPI0_SPCMD0_CPOL_Pos) ///< Clock Polarity setting mask +#define R_SPI0_SPCMD0_BRDV_Pos (2U) ///< Bitrate division setting offset +#define R_SPI0_SPCMD0_BRDV_Msk (0x0003U << R_SPI0_SPCMD0_BRDV_Pos) ///< Bitrate division setting mask +#define R_SPI0_SPCMD0_SSLA_Pos (4U) ///< SSL Signal selection setting offset +#define R_SPI0_SPCMD0_SSLA_Msk (0x0007U << R_SPI0_SPCMD0_SSLA_Pos) ///< SSL Signal selection setting mask +#define R_SPI0_SPCMD0_SSLKP_Pos (7U) ///< SSL Level Keep setting offset +#define R_SPI0_SPCMD0_SSLKP_Msk (1U << R_SPI0_SPCMD0_SSLKP_Pos) ///< SSL Level Keep setting mask +#define R_SPI0_SPCMD0_SPB_Pos (8U) ///< Bit Width setting offset +#define R_SPI0_SPCMD0_SPB_Msk (0x000FU << R_SPI0_SPCMD0_SPB_Pos) ///< Bit Width setting mask +#define R_SPI0_SPCMD0_LSBF_Pos (12U) ///< LSB/MSB setting offset +#define R_SPI0_SPCMD0_LSBF_Msk (1U << R_SPI0_SPCMD0_LSBF_Pos) ///< LSB/MSB setting mask +#define R_SPI0_SPCMD0_SPNDEN_Pos (13) ///< SPI Next-Access Delay Enable setting offset +#define R_SPI0_SPCMD0_SPNDEN_Msk (1U << R_SPI0_SPCMD0_SPNDEN_Pos) ///< SPI Next-Access Delay Enable setting mask +#define R_SPI0_SPCMD0_SLNDEN_Pos (14) ///< SSL Negation Delay Setting Enable setting offset +#define R_SPI0_SPCMD0_SLNDEN_Msk (1U << R_SPI0_SPCMD0_SLNDEN_Pos) ///< SSL Negation Delay Setting Enable setting mask +#define R_SPI0_SPCMD0_SCKDEN_Pos (15) ///< RSPCK Delay Setting Enable setting offset +#define R_SPI0_SPCMD0_SCKDEN_Msk (1U << R_SPI0_SPCMD0_SCKDEN_Pos) ///< RSPCK Delay Setting Enable setting mask + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * spi_prv_ns_callback)(spi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile spi_prv_ns_callback)(spi_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function declarations + **********************************************************************************************************************/ +static fsp_err_t r_spi_transfer_config(spi_cfg_t const * const p_cfg); +static void r_spi_hw_config(spi_instance_ctrl_t * p_ctrl); +static void r_spi_nvic_config(spi_instance_ctrl_t * p_ctrl); + +static void r_spi_bit_width_config(spi_instance_ctrl_t * p_ctrl); +static void r_spi_start_transfer(spi_instance_ctrl_t * p_ctrl); +static fsp_err_t r_spi_write_read_common(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +static void r_spi_receive(spi_instance_ctrl_t * p_ctrl); +static void r_spi_transmit(spi_instance_ctrl_t * p_ctrl); +static void r_spi_call_callback(spi_instance_ctrl_t * p_ctrl, spi_event_t event); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); + +void spi_rx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); +void spi_tx_dmac_callback(spi_instance_ctrl_t const * const p_ctrl); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* SPI implementation of SPI interface. */ +const spi_api_t g_spi_on_spi = +{ + .open = R_SPI_Open, + .read = R_SPI_Read, + .write = R_SPI_Write, + .writeRead = R_SPI_WriteRead, + .close = R_SPI_Close, + .callbackSet = R_SPI_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup SPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This functions initializes a channel for SPI communication mode. Implements @ref spi_api_t::open. + * + * This function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Configures the pperipheral registers according to the configuration. + * - Initialize the control structure for use in other @ref SPI_API functions. + * + * @retval FSP_SUCCESS Channel initialized successfully. + * @retval FSP_ERR_ALREADY_OPEN Instance was already initialized. + * @retval FSP_ERR_ASSERTION An invalid argument was given in the configuration structure. + * @retval FSP_ERR_UNSUPPORTED A requested setting is not possible on this device with the current build + * configuration. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel number is invalid. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: @ref transfer_api_t::open + * @note This function is reentrant. + **********************************************************************************************************************/ +fsp_err_t R_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(BSP_FEATURE_SPI_NUM_CHANNELS > p_cfg->channel, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); + + /* CPHA=0 is not supported in slave mode because of hardware limitations. See "Slave + * mode operation" in the SPI section of the relevant hardware manual. */ + if (SPI_MODE_SLAVE == p_cfg->operating_mode) + { + FSP_ERROR_RETURN(SPI_CLK_PHASE_EDGE_EVEN == p_cfg->clk_phase, FSP_ERR_UNSUPPORTED); + } + + #if (BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0) || (SPI_TRANSMIT_FROM_RXI_ISR == 1) || \ + (BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED == 1) + spi_extended_cfg_t * p_extend = (spi_extended_cfg_t *) p_cfg->p_extend; + + #if SPI_TRANSMIT_FROM_RXI_ISR == 1 + + /* Half Duplex - Transmit Only mode is not supported when transmit interrupt is handled in the RXI ISR. */ + FSP_ERROR_RETURN(p_extend->spi_comm != SPI_COMMUNICATION_TRANSMIT_ONLY, FSP_ERR_UNSUPPORTED); + + /* When the TXI Interrupt is handled in the RXI ISR, a TX DTC instance must be present if there is a + * RX DTC instance present otherwise the TXI Interrupts will not be processed. */ + if (p_cfg->p_transfer_rx) + { + FSP_ERROR_RETURN(0 != p_cfg->p_transfer_tx, FSP_ERR_UNSUPPORTED); + } + #endif + + #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0 || BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED == 1 + if ((SPI_MODE_MASTER == p_cfg->operating_mode)) + { + #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0 + + /* 4-Wire Mode is not supported in master mode on devices without SSL_LEVEL_KEEP */ + FSP_ERROR_RETURN(SPI_SSL_MODE_SPI != p_extend->spi_clksyn, FSP_ERR_UNSUPPORTED); + #endif + #if BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED + if (SPI_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay) + { + /* SPI burst transfer without delay is not supported in Clock Synchronous operation. */ + FSP_ERROR_RETURN(SPI_SSL_MODE_CLK_SYN != ((spi_extended_cfg_t *) p_cfg->p_extend)->spi_clksyn, + FSP_ERR_UNSUPPORTED); + } + #endif + } + #endif + #endif +#endif + + /* Configure transfers if they are provided in p_cfg. */ + err = r_spi_transfer_config(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Get the register address of the channel. */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + p_ctrl->p_regs = SPI_REG(p_ctrl->p_cfg->channel); + + /* Configure hardware registers according to the r_spi_api configuration structure. */ + r_spi_hw_config(p_ctrl); + + /* Enable interrupts in NVIC. */ + r_spi_nvic_config(p_ctrl); + + p_ctrl->open = SPI_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * This function receives data from a SPI device. Implements @ref spi_api_t::read. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI read operation. + * + * @retval FSP_SUCCESS Read operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or destination parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_Read (spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + return r_spi_write_read_common(p_api_ctrl, NULL, p_dest, length, bit_width); +} + +/*******************************************************************************************************************//** + * This function transmits data to a SPI device using the TX Only Communications Operation Mode. + * Implements @ref spi_api_t::write. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI write operation. + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or source parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_Write (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + return r_spi_write_read_common(p_api_ctrl, p_src, NULL, length, bit_width); +} + +/*******************************************************************************************************************//** + * This function simultaneously transmits and receive data. Implements @ref spi_api_t::writeRead. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI writeRead operation. + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control, source or destination parameters or + * transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + *********************************************************************************************************************/ +fsp_err_t R_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_src != NULL); + FSP_ASSERT(p_dest != NULL); +#endif + + return r_spi_write_read_common(p_api_ctrl, p_src, p_dest, length, bit_width); +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements spi_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory) +{ + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if (SPI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SPI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + spi_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(spi_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function manages the closing of a channel by the following task. Implements @ref spi_api_t::close. + * + * Disables SPI operations by disabling the SPI bus. + * - Disables the SPI peripheral. + * - Disables all the associated interrupts. + * - Update control structure so it will not work with @ref SPI_API functions. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION A required pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + **********************************************************************************************************************/ +fsp_err_t R_SPI_Close (spi_ctrl_t * const p_api_ctrl) +{ + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->open = 0; + +#if SPI_DMA_SUPPORT_ENABLE == 1 + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + /* Disable interrupts in NVIC. */ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + } + + if (p_ctrl->p_cfg->rxi_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + } + + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0U; + + /* Clear the status register. */ + + /* The status register must be read before cleared. See "SPI Status Register (SPSR)" description + * in the relevant hardware manual. */ + p_ctrl->p_regs->SPSR; + p_ctrl->p_regs->SPSR = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates the SPBR register value and the BRDV bits for a desired bitrate. + * If the desired bitrate is faster than the maximum bitrate, than the bitrate is set to the + * maximum bitrate. If the desired bitrate is slower than the minimum bitrate, than an error is returned. + * + * @param[in] bitrate Desired bitrate + * @param[out] spck_div Memory location to store bitrate register settings. + * + * @retval FSP_SUCCESS Valid spbr and brdv values were calculated + * @retval FSP_ERR_UNSUPPORTED Bitrate is not achievable + **********************************************************************************************************************/ +fsp_err_t R_SPI_CalculateBitrate (uint32_t bitrate, rspck_div_setting_t * spck_div) +{ + /* desired_divider = Smallest integer greater than or equal to SPI_CLK / bitrate. */ + uint32_t desired_divider = (R_FSP_SystemClockHzGet(BSP_FEATURE_SPI_CLOCK) + bitrate - 1) / bitrate; + + /* Can't achieve bitrate slower than desired. */ + if (desired_divider > SPI_CLK_MAX_DIV) + { + return FSP_ERR_UNSUPPORTED; + } + + if (desired_divider < SPI_CLK_MIN_DIV) + { + /* Configure max bitrate (SPI_CLK / 2) */ + spck_div->brdv = 0; + spck_div->spbr = 0; + + return FSP_SUCCESS; + } + + /* + * Possible SPI_CLK dividers for values of N: + * N = 0; div = [2,4,6,..,512] + * N = 1; div = [4,8,12,..,1024] + * N = 2; div = [8,16,32,..,2048] + * N = 3; div = [16,32,64,..,4096] + */ + uint8_t i; + for (i = 0; i < 4; i++) + { + /* Select smallest value for N possible. */ + + /* div <= 512; N = 0 + * 512 < div <= 1024; N=1 + * ... + */ + if (desired_divider <= (SPI_CLK_N_DIV_MULTIPLIER << i)) + { + break; + } + } + + spck_div->brdv = i & 0x03U; + + /* + * desired_divider = 2 * (spbr + 1) * 2^i. + * + * With desired_divider and i known, solve for spbr. + * + * spbr = SPI_CLK_DIV / (2 * 2^i) - 1 + */ + uint32_t spbr_divisor = (2U * (1U << i)); + + /* spbr = (Smallest integer greater than or equal to SPI_CLK_DIV / (2 * 2^i)) - 1. */ + spck_div->spbr = (uint8_t) (((desired_divider + spbr_divisor - 1U) / spbr_divisor) - 1U) & UINT8_MAX; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SPI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure the given transfer instances for receiving and transmitting data without CPU intervention. + * + * @param p_cfg Configuration structure with references to receive and transmit transfer instances. + * + * @retval FSP_SUCCESS The given transfer instances were configured successfully. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally + * calls @ref transfer_api_t::open. + **********************************************************************************************************************/ +static fsp_err_t r_spi_transfer_config (spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + +#if SPI_DMA_SUPPORT_ENABLE == 1 + const transfer_instance_t * p_transfer_tx = p_cfg->p_transfer_tx; + void * p_spdr = (void *) &(SPI_REG(p_cfg->channel)->SPDR); + if (p_transfer_tx) + { + p_transfer_tx->p_cfg->p_info->transfer_settings_word = SPI_DTC_TX_TRANSFER_SETTINGS; + p_transfer_tx->p_cfg->p_info->p_dest = p_spdr; + + err = p_transfer_tx->p_api->open(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + const transfer_instance_t * p_transfer_rx = p_cfg->p_transfer_rx; + if (p_transfer_rx) + { + p_transfer_rx->p_cfg->p_info->transfer_settings_word = SPI_DTC_RX_TRANSFER_SETTINGS; + p_transfer_rx->p_cfg->p_info->p_src = p_spdr; + + err = p_transfer_rx->p_api->open(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg); + + if ((FSP_SUCCESS != err) && p_transfer_tx) + { + p_transfer_tx->p_api->close(p_transfer_tx->p_ctrl); + } + } + +#else + FSP_PARAMETER_NOT_USED(p_cfg); +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Hardware configuration for settings given by the configuration structure. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_hw_config (spi_instance_ctrl_t * p_ctrl) +{ + uint32_t spcr = 0; + uint32_t sslp = 0; + uint32_t sppcr = 0; + uint32_t spcr2 = 0; + uint32_t spckd = 0; + uint32_t sslnd = 0; + uint32_t spnd = 0; + uint32_t spcmd0 = 0; + uint32_t spdcr2 = 0; + + /* Enable Receive Buffer Full interrupt. */ + spcr |= R_SPI0_SPCR_SPRIE_Msk; + + /* The TXI interrupt is not needed when TRANSMIT_FROM_RXI_ISR optimization is enabled. */ +#if SPI_TRANSMIT_FROM_RXI_ISR == 0 + + /* Enable Transmit Buffer Empty interrupt. */ + spcr |= R_SPI0_SPCR_SPTIE_Msk; +#endif + + /* Enable Error interrupt. */ + spcr |= R_SPI0_SPCR_SPEIE_Msk; + + /* Configure Master Mode setting. */ + spcr |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI0_SPCR_MSTR_Pos; + + /* Enable SCK Auto Stop setting in order to prevent RX Overflow in Master Mode */ + spcr2 |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI0_SPCR2_SCKASE_Pos; + + /* Configure CPHA setting. */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_phase << R_SPI0_SPCMD0_CPHA_Pos; + + /* Configure CPOL setting. */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_polarity << R_SPI0_SPCMD0_CPOL_Pos; + + /* Configure Bit Order (MSB,LSB) */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->bit_order << R_SPI0_SPCMD0_LSBF_Pos; + + if (p_ctrl->p_cfg->p_transfer_tx) + { + /* Transmit Buffer Empty IRQ must be enabled for DTC even if TRANSMIT_FROM_RXI is enabled. */ + spcr |= R_SPI0_SPCR_SPTIE_Msk; + } + + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + if (SPI_SSL_MODE_SPI == p_extend->spi_clksyn) + { +#if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 1 + if ((1 << p_ctrl->p_cfg->channel) & BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK) + { + /* Configure SSL Level Keep Setting. */ + spcmd0 |= (uint32_t) (!p_ctrl->p_cfg->operating_mode << R_SPI0_SPCMD0_SSLKP_Pos); + } +#endif + + /* Configure 4-Wire Mode Setting. */ + spcr &= ~R_SPI0_SPCR_SPMS_Msk; + } + else + { + /* Configure 3-Wire Mode Setting. */ + spcr |= R_SPI0_SPCR_SPMS_Msk; + } + + /* Configure Full Duplex or TX Only Setting. */ + spcr &= (uint32_t) ~(p_extend->spi_comm << R_SPI0_SPCR_SPRIE_Pos), + spcr |= + (uint32_t) ((p_extend->spi_comm << R_SPI0_SPCR_TXMD_Pos) | + (p_extend->spi_comm << R_SPI0_SPCR_SPTIE_Pos)); + + /* Configure SSLn polarity setting. */ + sslp &= ~0x0FU; + sslp |= (uint32_t) p_extend->ssl_polarity << p_extend->ssl_select; + + /* Configure SSLn setting. (SSL0, SSL1, SSL2, SSL3)*/ + spcmd0 &= ~R_SPI0_SPCMD0_SSLA_Msk; + spcmd0 |= (uint32_t) p_extend->ssl_select << R_SPI0_SPCMD0_SSLA_Pos; + + if (SPI_MOSI_IDLE_VALUE_FIXING_DISABLE != p_extend->mosi_idle) + { + /* Enable mosi value fixing */ + sppcr |= R_SPI0_SPPCR_MOIFE_Msk; + + if (SPI_MOSI_IDLE_VALUE_FIXING_HIGH == p_extend->mosi_idle) + { + sppcr |= R_SPI0_SPPCR_MOIFV_Msk; + } + } + + if (SPI_PARITY_MODE_DISABLE != p_extend->parity) + { + /* Enable Parity Mode. */ + spcr2 |= R_SPI0_SPCR2_SPPE_Msk; + + if (SPI_PARITY_MODE_ODD == p_extend->parity) + { + /* Configure ODD Parity Setting. */ + spcr2 |= R_SPI0_SPCR2_SPOE_Msk; + } + } + + /* Configure byte swapping for 16/32-Bit mode. */ + spdcr2 |= p_extend->byte_swap; + + /* Configure the Bit Rate Division Setting */ + spcmd0 |= (uint32_t) p_extend->spck_div.brdv << R_SPI0_SPCMD0_BRDV_Pos; + + /* Enable all delay settings. */ + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) + { + /* Note that disabling delay settings is same as setting delay to 1. */ + spcmd0 |= (uint32_t) R_SPI0_SPCMD0_SPNDEN_Msk | R_SPI0_SPCMD0_SLNDEN_Msk | R_SPI0_SPCMD0_SCKDEN_Msk; + + spckd = p_extend->spck_delay; + sslnd = p_extend->ssl_negation_delay; + spnd = p_extend->next_access_delay; + } + + /* Power up the SPI module. */ + R_BSP_MODULE_START(FSP_IP_SPI, p_ctrl->p_cfg->channel); + + /* Clear the status register. */ + + /* The status register must be read before cleared. See "SPI Status Register (SPSR)" description + * in the relevant hardware manual. */ + p_ctrl->p_regs->SPSR; + p_ctrl->p_regs->SPSR = 0; + + /* Write registers */ + p_ctrl->p_regs->SPCR = (uint8_t) spcr; + p_ctrl->p_regs->SSLP = (uint8_t) sslp; + p_ctrl->p_regs->SPPCR = (uint8_t) sppcr; + p_ctrl->p_regs->SPBR = p_extend->spck_div.spbr; + p_ctrl->p_regs->SPCKD = (uint8_t) spckd; + p_ctrl->p_regs->SSLND = (uint8_t) sslnd; + p_ctrl->p_regs->SPND = (uint8_t) spnd; + p_ctrl->p_regs->SPCR2 = (uint8_t) spcr2; + p_ctrl->p_regs->SPCMD[0] = (uint16_t) spcmd0; + p_ctrl->p_regs->SPDCR2 = (uint8_t) spdcr2; + +#if BSP_FEATURE_SPI_HAS_SPCR3 == 1 + uint8_t spcr3 = R_SPI0_SPCR3_CENDIE_Msk; + #if BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (SPI_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay)) + { + /* Enable burst transfer without delay. */ + spcr3 |= R_SPI0_SPCR3_BFDS_Msk; + } + #endif + p_ctrl->p_regs->SPCR3 = spcr3; +#endif +} + +/*******************************************************************************************************************//** + * Enable Receive Buffer Full, Transmit Buffer Empty, and Error Interrupts in the NVIC. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_nvic_config (spi_instance_ctrl_t * p_ctrl) +{ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->txi_irq, p_ctrl->p_cfg->txi_ipl, p_ctrl); + } + + if (p_ctrl->p_cfg->rxi_irq >= 0) + { + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->rxi_irq, p_ctrl->p_cfg->rxi_ipl, p_ctrl); + } + + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->eri_irq, p_ctrl->p_cfg->eri_ipl, p_ctrl); + + R_BSP_IrqCfg(p_ctrl->p_cfg->tei_irq, p_ctrl->p_cfg->tei_ipl, p_ctrl); + + /* Note tei_irq is not enabled until the last data frame is transferred. */ +} + +/*******************************************************************************************************************//** + * Setup the bit width configuration for a transfer. + * + * @param[in] p_ctrl pointer to control structure. + * + * Note: For 8-Bit wide data frames, the devices require the SPBYT bit to enable byte level access to the + * data register. Although this register is not documented in some MCU hardware manuals, it does seem to be available + * on all of them. + **********************************************************************************************************************/ +static void r_spi_bit_width_config (spi_instance_ctrl_t * p_ctrl) +{ + uint32_t spdcr = p_ctrl->p_regs->SPDCR; + uint32_t spcmd0 = p_ctrl->p_regs->SPCMD[0]; + + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths of 20, 24 or 32 bits */ + { + /* Configure Word access to data register. */ + spdcr &= ~R_SPI0_SPDCR_SPBYT_Msk; + spdcr |= R_SPI0_SPDCR_SPLW_Msk; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/ + { + /* Set SPBYT so 8bit transfer works with the DTC/DMAC. */ + spdcr |= R_SPI0_SPDCR_SPBYT_Msk; + } + else /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */ + { + /* Configure Half-Word access to data register. */ + spdcr &= ~(R_SPI0_SPDCR_SPBYT_Msk | R_SPI0_SPDCR_SPLW_Msk); + } + + /* Configure data length based on the selected bit width . */ + uint32_t bit_width = p_ctrl->bit_width; + if (bit_width > SPI_BIT_WIDTH_16_BITS) + { + bit_width = ((bit_width + 1) >> 2) - 5; + } + + spcmd0 &= ~R_SPI0_SPCMD0_SPB_Msk; + spcmd0 |= bit_width << R_SPI0_SPCMD0_SPB_Pos; + +#if BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay))) + { + if (1 != p_ctrl->count) + { + /* Configure SSL Level Keep Setting if length is greater than 1. */ + spcmd0 |= R_SPI0_SPCMD0_SSLKP_Msk; + } + else + { + /* Disable SSL Level Keep since length is 1 (not a burst transfer). */ + spcmd0 &= ~R_SPI0_SPCMD0_SSLKP_Msk; + } + } +#endif + + p_ctrl->p_regs->SPDCR = (uint8_t) spdcr; + p_ctrl->p_regs->SPCMD[0] = (uint16_t) spcmd0; +} + +/*******************************************************************************************************************//** + * Initiates a SPI transfer by setting the SPE bit in SPCR. + * + * @param[in] p_ctrl pointer to control structure. + * + * Note: When not using the DTC to transmit, this function pre-loads the SPI shift-register and shift-register-buffer + * instead of waiting for the transmit buffer empty interrupt. This is required when transmitting from the + * Receive Buffer Full interrupt, but it does not interfere with transmitting when using the transmit buffer empty + * interrupt. + **********************************************************************************************************************/ +static void r_spi_start_transfer (spi_instance_ctrl_t * p_ctrl) +{ +#if SPI_TRANSMIT_FROM_RXI_ISR == 1 + if (!p_ctrl->p_cfg->p_transfer_tx) + { + /* Handle the first two transmit empty events here because transmit interrupt may not be enabled. */ + + /* Critical section required so that the txi interrupt can be handled here instead of in the ISR. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Enable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 1; + + /* Must call transmit to kick off transfer when transmitting from rxi ISR. */ + r_spi_transmit(p_ctrl); ///< First data immediately copied into the SPI shift register. + + /* Second transmit significantly improves slave mode performance. */ + r_spi_transmit(p_ctrl); ///< Second data copied into the SPI transmit buffer. + + /* Must clear the txi IRQ status (The interrupt was handled here). */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + + FSP_CRITICAL_SECTION_EXIT; + } + else + { + /* Enable the SPI Transfer and TX buffer empty interrupt */ + p_ctrl->p_regs->SPCR |= R_SPI0_SPCR_SPTIE_Msk | R_SPI0_SPCR_SPE_Msk; + } + +#else + + /* Enable the SPI Transfer and TX buffer empty interrupt */ + p_ctrl->p_regs->SPCR |= R_SPI0_SPCR_SPTIE_Msk | R_SPI0_SPCR_SPE_Msk; +#endif +} + +/*******************************************************************************************************************//** + * Configures the driver state and initiates a SPI transfer for all modes of operation. + * + * @param[in] p_api_ctrl pointer to control structure. + * @param p_src Buffer to transmit data from. + * @param p_dest Buffer to store received data in. + * @param[in] length Number of transfers + * @param[in] bit_width Data frame size (8-Bit, 16-Bit, 32-Bit) + * + * @retval FSP_SUCCESS Transfer was started successfully. + * @retval FSP_ERR_ASSERTION An argument is invalid. + * @retval FSP_ERR_NOT_OPEN The instance has not been initialized. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally + * calls @ref transfer_api_t::reconfigure. + **********************************************************************************************************************/ +static fsp_err_t r_spi_write_read_common (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(p_src || p_dest); + FSP_ASSERT(0 != length); + + #if SPI_DMA_SUPPORT_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + transfer_properties_t transfer_info; + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(length <= transfer_info.transfer_length_max); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + transfer_properties_t transfer_info; + fsp_err_t err = p_ctrl->p_cfg->p_transfer_tx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(length <= transfer_info.transfer_length_max); + } + #endif + + /* Reject bit width settings not compatible with R_SPI */ + FSP_ASSERT(!((bit_width < SPI_BIT_WIDTH_8_BITS) || + ((bit_width > SPI_BIT_WIDTH_16_BITS) && ((bit_width + 1) & 0x3)) || + (bit_width == SPI_BIT_WIDTH_28_BITS))); +#endif + + FSP_ERROR_RETURN(0 == (p_ctrl->p_regs->SPCR & R_SPI0_SPCR_SPE_Msk), FSP_ERR_IN_USE); + + p_ctrl->p_tx_data = p_src; + p_ctrl->p_rx_data = p_dest; + p_ctrl->tx_count = 0; + p_ctrl->rx_count = 0; + p_ctrl->count = length; + p_ctrl->bit_width = bit_width; + +#if SPI_DMA_SUPPORT_ENABLE == 1 + if (p_ctrl->p_cfg->p_transfer_rx) + { + /* When the rxi interrupt is called, all transfers will be finished. */ + p_ctrl->rx_count = length; + + /* Configure the receive DMA instance. */ + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE; + } + else + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + } + + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = (uint16_t) length; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = p_dest; + + if (NULL == p_dest) + { + static uint32_t dummy_rx; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word_b.dest_addr_mode = + TRANSFER_ADDR_MODE_FIXED; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = &dummy_rx; + } + + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (p_ctrl->p_cfg->p_transfer_tx) + { + /* When the txi interrupt is called, all transfers will be finished. */ + p_ctrl->tx_count = length; + + /* Configure the transmit DMA instance. */ + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_4_BYTE; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE; + } + else + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.size = TRANSFER_SIZE_2_BYTE; + } + + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_INCREMENTED; + + #if BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay)) && + (1 != p_ctrl->count)) + { + /* When the txi interrupt is called, length - 1 frames have already been transferred. */ + p_ctrl->tx_count = length - 1; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = (uint16_t) (length - 1U); + } + else + #endif + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = (uint16_t) length; + } + + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = p_src; + + if (NULL == p_src) + { + static uint32_t dummy_tx = 0; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word_b.src_addr_mode = + TRANSFER_ADDR_MODE_FIXED; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = &dummy_tx; + } + + /* Disable the TX buffer empty interrupt before enabling transfer. */ + p_ctrl->p_regs->SPCR_b.SPTIE = 0; + + fsp_err_t err = p_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif + + r_spi_bit_width_config(p_ctrl); + r_spi_start_transfer(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Copy configured bit width from the SPI data register to the current rx data location. + * If the receive buffer is NULL, just read the SPI data register. + * If the total transfer length has already been received than do nothing. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_receive (spi_instance_ctrl_t * p_ctrl) +{ + uint32_t rx_count = p_ctrl->rx_count; + if (rx_count == p_ctrl->count) + { + return; + } + + if (0 == p_ctrl->p_rx_data) + { + /* Read the received data but do nothing with it. */ + p_ctrl->p_regs->SPDR; + } + else + { + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths of 20, 24 or 32 bits */ + { + ((uint32_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/ + { + ((uint8_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR_BY; + } + else /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */ + { + ((uint16_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR_HA; + } + } + + p_ctrl->rx_count = rx_count + 1; +} + +/*******************************************************************************************************************//** + * Copy configured bit width from the current tx data location into the SPI data register. + * If the transmit buffer is NULL, than write zero to the SPI data register. + * If the total transfer length has already been transmitted than do nothing. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_transmit (spi_instance_ctrl_t * p_ctrl) +{ + uint32_t tx_count = p_ctrl->tx_count; + +#if BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay)) && + (0 == (p_ctrl->p_regs->SPSR & (1 << R_SPI0_SPSR_SPTEF_Pos)))) + { + + /* The TXI interrupt is triggered by DTC automatically. + * Skip handling it, as the transmit buffer is already preloaded with data. */ + return; + } + + if (tx_count == (p_ctrl->count - 1)) + { + /* Disable SSLKP bit in last frame. */ + p_ctrl->p_regs->SPCMD[0] &= (uint16_t) (~R_SPI0_SPCMD0_SSLKP_Msk); + } +#endif + + if (tx_count == p_ctrl->count) + { + return; + } + + if (0 == p_ctrl->p_tx_data) + { + /* Transmit zero if no tx buffer present. */ + p_ctrl->p_regs->SPDR = 0; + } + else + { + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths of 20, 24 or 32 bits */ + { + p_ctrl->p_regs->SPDR = ((uint32_t *) p_ctrl->p_tx_data)[tx_count]; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/ + { + p_ctrl->p_regs->SPDR_BY = ((uint8_t *) p_ctrl->p_tx_data)[tx_count]; + } + else /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */ + { + p_ctrl->p_regs->SPDR_HA = ((uint16_t *) p_ctrl->p_tx_data)[tx_count]; + } + } + + p_ctrl->tx_count = tx_count + 1; +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SPI instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_spi_call_callback (spi_instance_ctrl_t * p_ctrl, spi_event_t event) +{ + spi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + spi_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + spi_prv_ns_callback p_callback = (spi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Callback that must be called after a RX DMAC transfer completes. + * + * @param[in] p_ctrl Pointer to SPI instance control block + **********************************************************************************************************************/ +void spi_rx_dmac_callback (spi_instance_ctrl_t const * const p_ctrl) +{ + /* If the transmit and receive ISRs are too slow to keep up at high bitrates, + * the hardware will generate an interrupt before all of the transfers are completed. + * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); +} + +/*******************************************************************************************************************//** + * ISR called when data is loaded into SPI data register from the shift register. + **********************************************************************************************************************/ +void spi_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + r_spi_receive(p_ctrl); + +#if SPI_TRANSMIT_FROM_RXI_ISR == 1 + #if BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + /* Skip r_spi_transmit() when operating in master mode with burst transfer without delay and a transfer instance is used. */ + if ((!p_ctrl->p_cfg->p_transfer_tx) || + (!(p_extend && (SPI_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay))) || + (SPI_MODE_MASTER != p_ctrl->p_cfg->operating_mode)) + #endif + { + /* It is a little faster to handle the transmit buffer empty event in the receive buffer full ISR. + * Note that this is only possible when the instance is not using a transfer instance to receive data. */ + r_spi_transmit(p_ctrl); + } +#endif + + if (p_ctrl->rx_count == p_ctrl->count) + { + /* If the transmit and receive ISRs are too slow to keep up at high bitrates, + * the hardware will generate an interrupt before all of the transfers are completed. + * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Callback that must be called after a TX DMAC transfer completes. + * + * @param[in] p_ctrl Pointer to SPI instance control block + **********************************************************************************************************************/ +void spi_tx_dmac_callback (spi_instance_ctrl_t const * const p_ctrl) +{ +#if SPI_TRANSMIT_FROM_RXI_ISR == 0 || BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED == 1 + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + #if BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED + + /* Send last frame if transfer length is greater than 1. */ + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay)) && + (1 != p_ctrl->count)) + { + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_regs->SPSR_b.SPTEF, 1U); + r_spi_transmit((spi_instance_ctrl_t *) p_ctrl); + } + #endif + + #if SPI_TRANSMIT_FROM_RXI_ISR == 0 + if (p_extend && (SPI_COMMUNICATION_TRANSMIT_ONLY == p_extend->spi_comm)) + { + /* Only enable the transfer end ISR if there are no receive buffer full interrupts expected to be handled + * after this interrupt. */ + + /* If DMA is used to transmit data, enable the interrupt after all the data has been transferred, but do not + * clear the IRQ Pending Bit. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + #endif +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif +} + +/*******************************************************************************************************************//** + * ISR called when data is copied from the SPI data register into the SPI shift register. + **********************************************************************************************************************/ +void spi_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if SPI_TRANSMIT_FROM_RXI_ISR == 0 || BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED == 1 + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + #if SPI_TRANSMIT_FROM_RXI_ISR == 0 + if (p_extend && (SPI_COMMUNICATION_TRANSMIT_ONLY == p_extend->spi_comm)) + { + /* Only enable the transfer end ISR if there are no receive buffer full interrupts expected to be handled + * after this interrupt. */ + if (p_ctrl->tx_count == p_ctrl->count - 1) + { + /* If the transmit and receive ISRs are too slow to keep up at high bitrates, + * the hardware will generate an interrupt before all of the transfers are completed. + * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->tei_irq); + } + else if (p_ctrl->p_cfg->p_transfer_tx) + { + /* If DMA is used to transmit data, enable the interrupt after all the data has been transferred, but do not + * clear the IRQ Pending Bit. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + else + { + } + } + + /* Transmit happens after checking if the last transfer has been written to the transmit buffer in order + * to ensure that the end interrupt is not enabled while there is data still in the transmit buffer. */ + r_spi_transmit(p_ctrl); + #else + #if BSP_FEATURE_SPI_BURST_TRANSFER_WITHOUT_DELAY_SUPPORTED + + /* Send last frame in master mode with burst transfer without delay. */ + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay))) + { + r_spi_transmit(p_ctrl); + } + #endif + #endif +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR called when the SPI peripheral transitions from the transferring state to the IDLE state. + **********************************************************************************************************************/ +void spi_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if ((0 == p_ctrl->p_regs->SPSR_b.IDLNF) || (SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode)) + { + R_BSP_IrqDisable(irq); + + /* Writing 0 to SPE generates a TXI IRQ. Disable the TXI IRQ. + * (See "SPI Control Register" description in the relevant hardware manual). */ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + } + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0; + + /* Re-enable the TXI IRQ and clear the pending IRQ. */ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + } + + /* Signal that a transfer has completed. */ + r_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR called in the event that an error occurs (Ex: RX_OVERFLOW). + **********************************************************************************************************************/ +void spi_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Writing 0 to SPE generatates a TXI IRQ. Disable the TXI IRQ. + * (See "SPI Control Register" description in the relevant hardware manual). */ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + } + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0; + + /* Re-enable the TXI IRQ and clear the pending IRQ. */ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + } + + /* Read the status register. */ + uint8_t status = p_ctrl->p_regs->SPSR; + + /* Clear the status register. */ + p_ctrl->p_regs->SPSR = 0; + + /* Check if the error is a Parity Error. */ + if (R_SPI0_SPSR_PERF_Msk & status) + { + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_PARITY); + } + + /* Check if the error is a Receive Buffer Overflow Error. */ + if (R_SPI0_SPSR_OVRF_Msk & status) + { + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); + } + + /* Check if the error is a Mode Fault Error. */ + if (R_SPI0_SPSR_MODF_Msk & status) + { + /* Check if the error is a Transmit Buffer Underflow Error. */ + if (R_SPI0_SPSR_UDRF_Msk & status) + { + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_MODE_UNDERRUN); + } + } + + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/* End of file R_SPI. */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_spi_b/r_spi_b.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_spi_b/r_spi_b.c new file mode 100644 index 0000000000..1fd58e25dd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_spi_b/r_spi_b.c @@ -0,0 +1,1340 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_b.h" +#include "r_spi_b_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "SPI" in ASCII, used to determine if channel is open. */ +#define SPI_B_OPEN (0x52535049ULL) + +/** SPI base register access macro. */ +#define SPI_B_REG(channel) ((R_SPI_B0_Type *) ((uint32_t) R_SPI_B0 + \ + ((uint32_t) R_SPI_B1 - (uint32_t) R_SPI_B0) * \ + (channel))) + +#define SPI_B_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SPI_B_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SPI_B_CLK_N_DIV_MULTIPLIER (512U) ///< Maximum divider for N=0 +#define SPI_B_CLK_MAX_DIV (4096U) ///< Maximum SPI CLK divider +#define SPI_B_CLK_MIN_DIV (2U) ///< Minimum SPI CLK divider + +#define SPI_B_PRV_SPSRC_ALL_CLEAR (0xFD800000U) ///< Clear all status flags + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * spi_prv_ns_callback)(spi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile spi_prv_ns_callback)(spi_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function declarations + **********************************************************************************************************************/ +static fsp_err_t r_spi_b_transfer_config(spi_cfg_t const * const p_cfg); +static void r_spi_b_hw_config(spi_b_instance_ctrl_t * p_ctrl); +static void r_spi_b_nvic_config(spi_b_instance_ctrl_t * p_ctrl); + +static void r_spi_b_bit_width_config(spi_b_instance_ctrl_t * p_ctrl); +static void r_spi_b_start_transfer(spi_b_instance_ctrl_t * p_ctrl); +static fsp_err_t r_spi_b_write_read_common(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +static void r_spi_b_receive(spi_b_instance_ctrl_t * p_ctrl); +static void r_spi_b_transmit(spi_b_instance_ctrl_t * p_ctrl); +static void r_spi_b_call_callback(spi_b_instance_ctrl_t * p_ctrl, spi_event_t event); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void spi_b_rxi_isr(void); +void spi_b_txi_isr(void); +void spi_b_tei_isr(void); +void spi_b_eri_isr(void); + +void spi_b_rx_dmac_callback(spi_b_instance_ctrl_t const * const p_ctrl); +void spi_b_tx_dmac_callback(spi_b_instance_ctrl_t const * const p_ctrl); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* SPI implementation of SPI interface. */ +const spi_api_t g_spi_on_spi_b = +{ + .open = R_SPI_B_Open, + .read = R_SPI_B_Read, + .write = R_SPI_B_Write, + .writeRead = R_SPI_B_WriteRead, + .close = R_SPI_B_Close, + .callbackSet = R_SPI_B_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup SPI_B + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This functions initializes a channel for SPI communication mode. Implements @ref spi_api_t::open. + * + * This function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Configures the peripheral registers according to the configuration. + * - Initialize the control structure for use in other @ref SPI_API functions. + * + * @retval FSP_SUCCESS Channel initialized successfully. + * @retval FSP_ERR_ALREADY_OPEN Instance was already initialized. + * @retval FSP_ERR_ASSERTION An invalid argument was given in the configuration structure. + * @retval FSP_ERR_UNSUPPORTED A requested setting is not possible on this device with the current build + * configuration. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel number is invalid. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: @ref transfer_api_t::open + * @note This function is reentrant. + **********************************************************************************************************************/ +fsp_err_t R_SPI_B_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + spi_b_instance_ctrl_t * p_ctrl = (spi_b_instance_ctrl_t *) p_api_ctrl; + +#if SPI_B_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_B_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(BSP_FEATURE_SPI_NUM_CHANNELS > p_cfg->channel, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); + + spi_b_extended_cfg_t * p_extend = (spi_b_extended_cfg_t *) p_cfg->p_extend; + if (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay) + { + /* SPI_B burst transfer without delay is not supported in Clock Synchronous operation. */ + FSP_ERROR_RETURN(SPI_B_SSL_MODE_CLK_SYN != p_extend->spi_clksyn, FSP_ERR_UNSUPPORTED); + } + + #if SPI_B_TRANSMIT_FROM_RXI_ISR == 1 + + /* Half Duplex - Transmit Only mode is not supported when transmit interrupt is handled in the RXI ISR. */ + FSP_ERROR_RETURN(p_extend->spi_comm != SPI_B_COMMUNICATION_TRANSMIT_ONLY, FSP_ERR_UNSUPPORTED); + + /* When the TXI Interrupt is handled in the RXI ISR, a TX DTC instance must be present if there is a + * RX DTC instance present otherwise the TXI Interrupts will not be processed. */ + if (p_cfg->p_transfer_rx) + { + FSP_ERROR_RETURN(0 != p_cfg->p_transfer_tx, FSP_ERR_UNSUPPORTED); + } + #endif +#endif + + /* Configure transfers if they are provided in p_cfg. */ + err = r_spi_b_transfer_config(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Get the register address of the channel. */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + p_ctrl->p_regs = SPI_B_REG(p_ctrl->p_cfg->channel); + + /* Configure hardware registers according to the r_spi_api configuration structure. */ + r_spi_b_hw_config(p_ctrl); + + /* Enable interrupts in NVIC. */ + r_spi_b_nvic_config(p_ctrl); + + p_ctrl->open = SPI_B_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * This function receives data from a SPI device. Implements @ref spi_api_t::read. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI read operation. + * + * @retval FSP_SUCCESS Read operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or destination parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_B_Read (spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + return r_spi_b_write_read_common(p_api_ctrl, NULL, p_dest, length, bit_width); +} + +/*******************************************************************************************************************//** + * This function transmits data to a SPI device using the TX Only Communications Operation Mode. + * Implements @ref spi_api_t::write. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI write operation. + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or source parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_B_Write (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + return r_spi_b_write_read_common(p_api_ctrl, p_src, NULL, length, bit_width); +} + +/*******************************************************************************************************************//** + * This function simultaneously transmits and receive data. Implements @ref spi_api_t::writeRead. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI writeRead operation. + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control, source or destination parameters or + * transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + *********************************************************************************************************************/ +fsp_err_t R_SPI_B_WriteRead (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SPI_B_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_src != NULL); + FSP_ASSERT(p_dest != NULL); +#endif + + return r_spi_b_write_read_common(p_api_ctrl, p_src, p_dest, length, bit_width); +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements spi_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SPI_B_CallbackSet (spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void * const p_context, + spi_callback_args_t * const p_callback_memory) +{ + spi_b_instance_ctrl_t * p_ctrl = (spi_b_instance_ctrl_t *) p_api_ctrl; + +#if (SPI_B_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SPI_B_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SPI_B_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + spi_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(spi_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function manages the closing of a channel by the following task. Implements @ref spi_api_t::close. + * + * Disables SPI operations by disabling the SPI bus. + * - Disables the SPI peripheral. + * - Disables all the associated interrupts. + * - Update control structure so it will not work with @ref SPI_API functions. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION A required pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + **********************************************************************************************************************/ +fsp_err_t R_SPI_B_Close (spi_ctrl_t * const p_api_ctrl) +{ + spi_b_instance_ctrl_t * p_ctrl = (spi_b_instance_ctrl_t *) p_api_ctrl; + +#if SPI_B_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_B_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->open = 0; + +#if SPI_B_CFG_DMA_SUPPORT_ENABLE == 1 + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + /* Disable SPI interrupts. */ + p_ctrl->p_regs->SPCR &= + ~(R_SPI_B0_SPCR_SPTIE_Msk | R_SPI_B0_SPCR_SPRIE_Msk | R_SPI_B0_SPCR_CENDIE_Msk | R_SPI_B0_SPCR_SPEIE_Msk); + + /* Disable interrupts in NVIC. When using DMA for data transfer, TXI and RXI interrupts + * are not required and typically disabled. Check if the IRQ number is valid (>= 0) before calling R_BSP_IrqDisable() + * to avoid disabling nonexistent interrupts. */ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + } + + if (p_ctrl->p_cfg->rxi_irq >= 0) + { + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + } + + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0U; + + /* Clear the status register. */ + p_ctrl->p_regs->SPSRC = SPI_B_PRV_SPSRC_ALL_CLEAR; + + /* Reset FIFO buffer (TX/RX pointers initialized). */ + p_ctrl->p_regs->SPFCR = R_SPI_B0_SPFCR_SPFRST_Msk; + + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == + ((spi_b_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->burst_interframe_delay)) + { + /* Reset TTRG to 0. */ + p_ctrl->p_regs->SPDCR2 &= ~(R_SPI_B0_SPDCR2_TTRG_Msk); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates the SPBR register value and the BRDV bits for a desired bitrate. + * If the desired bitrate is faster than the maximum bitrate, than the bitrate is set to the + * maximum bitrate. If the desired bitrate is slower than the minimum bitrate, than an error is returned. + * + * @param[in] bitrate Desired bitrate + * @param[in] clock_source SPI communication clock source to be used + * @param[out] spck_div Memory location to store bitrate register settings. + * + * @retval FSP_SUCCESS Valid spbr and brdv values were calculated + * @retval FSP_ERR_UNSUPPORTED Bitrate is not achievable + **********************************************************************************************************************/ +fsp_err_t R_SPI_B_CalculateBitrate (uint32_t bitrate, spi_b_clock_source_t clock_source, rspck_div_setting_t * spck_div) +{ + /* desired_divider = Smallest integer greater than or equal to TCLK / bitrate. */ + uint32_t desired_divider; + if (SPI_B_CLOCK_SOURCE_PCLK == clock_source) + { + desired_divider = R_FSP_SystemClockHzGet(BSP_FEATURE_SPI_CLOCK); + } + else + { +#if BSP_FEATURE_SCI_HAS_SCISPI_CLOCK + desired_divider = R_FSP_SciSpiClockHzGet(); +#elif BSP_FEATURE_SPI_HAS_CLOCK + desired_divider = R_FSP_SpiClockHzGet(); +#endif + } + + desired_divider = (desired_divider + bitrate - 1) / bitrate; + + /* Can't achieve bitrate slower than desired. */ + if (desired_divider > SPI_B_CLK_MAX_DIV) + { + return FSP_ERR_UNSUPPORTED; + } + + if (desired_divider < SPI_B_CLK_MIN_DIV) + { + /* Configure max bitrate (TCLK / 2) */ + spck_div->brdv = 0; + spck_div->spbr = 0; + + return FSP_SUCCESS; + } + + /* + * Possible TCLK dividers for values of N: + * N = 0; div = [2,4,6,..,512] + * N = 1; div = [4,8,12,..,1024] + * N = 2; div = [8,16,32,..,2048] + * N = 3; div = [16,32,64,..,4096] + */ + uint8_t i; + for (i = 0; i < 4; i++) + { + /* Select smallest value for N possible. */ + + /* div <= 512; N = 0 + * 512 < div <= 1024; N=1 + * ... + */ + if (desired_divider <= (SPI_B_CLK_N_DIV_MULTIPLIER << i)) + { + break; + } + } + + spck_div->brdv = i & 0x03U; + + /* + * desired_divider = 2 * (spbr + 1) * 2^i. + * + * With desired_divider and i known, solve for spbr. + * + * spbr = TCLK_DIV / (2 * 2^i) - 1 + */ + uint32_t spbr_divisor = (2U * (1U << i)); + + /* spbr = (Smallest integer greater than or equal to TCLK_DIV / (2 * 2^i)) - 1. */ + spck_div->spbr = (uint8_t) (((desired_divider + spbr_divisor - 1U) / spbr_divisor) - 1U) & UINT8_MAX; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SPI_B) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure the given transfer instances for receiving and transmitting data without CPU intervention. + * + * @param p_cfg Configuration structure with references to receive and transmit transfer instances. + * + * @retval FSP_SUCCESS The given transfer instances were configured successfully. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally + * calls @ref transfer_api_t::open. + **********************************************************************************************************************/ +static fsp_err_t r_spi_b_transfer_config (spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + +#if SPI_B_CFG_DMA_SUPPORT_ENABLE == 1 + const transfer_instance_t * p_transfer_tx = p_cfg->p_transfer_tx; + void * p_spdr = (void *) &(SPI_B_REG(p_cfg->channel)->SPDR); + if (p_transfer_tx) + { + p_transfer_tx->p_cfg->p_info->transfer_settings_word = SPI_B_DTC_TX_TRANSFER_SETTINGS; + p_transfer_tx->p_cfg->p_info->p_dest = p_spdr; + + err = p_transfer_tx->p_api->open(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + const transfer_instance_t * p_transfer_rx = p_cfg->p_transfer_rx; + if (p_transfer_rx) + { + p_transfer_rx->p_cfg->p_info->transfer_settings_word = SPI_B_DTC_RX_TRANSFER_SETTINGS; + p_transfer_rx->p_cfg->p_info->p_src = p_spdr; + + err = p_transfer_rx->p_api->open(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg); + + if ((FSP_SUCCESS != err) && p_transfer_tx) + { + p_transfer_tx->p_api->close(p_transfer_tx->p_ctrl); + } + } + +#else + FSP_PARAMETER_NOT_USED(p_cfg); +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Hardware configuration for settings given by the configuration structure. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_b_hw_config (spi_b_instance_ctrl_t * p_ctrl) +{ + uint32_t spcr = 0; + uint32_t spcr2 = 0; + uint32_t spcr3 = 0; + uint32_t spdecr = 0; + uint32_t spcmd0 = 0; + uint32_t spdcr = 0; + +#if SPI_B_TRANSMIT_FROM_RXI_ISR + if (p_ctrl->p_cfg->p_transfer_tx) +#endif + { + /* Transmit Buffer Empty IRQ must be enabled for DTC even if TRANSMIT_FROM_RXI is enabled. */ + spcr |= R_SPI_B0_SPCR_SPTIE_Msk; + } + + /* Enable Error interrupt. */ + spcr |= R_SPI_B0_SPCR_SPEIE_Msk; + + /* Enable Communication End interrupt. */ + spcr |= R_SPI_B0_SPCR_CENDIE_Msk; + + /* Configure Master Mode setting. */ + spcr |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI_B0_SPCR_MSTR_Pos; + + /* Enable SCK Auto Stop setting in order to prevent RX Overflow in Master Mode */ + spcr |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI_B0_SPCR_SCKASE_Pos; + + /* Configure CPHA setting. */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_phase << R_SPI_B0_SPCMD0_CPHA_Pos; + + /* Configure CPOL setting. */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_polarity << R_SPI_B0_SPCMD0_CPOL_Pos; + + /* Configure Bit Order (MSB,LSB) */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->bit_order << R_SPI_B0_SPCMD0_LSBF_Pos; + + spi_b_extended_cfg_t * p_extend = ((spi_b_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + /* Set clock source */ + spcr |= (uint32_t) (p_extend->clock_source << R_SPI_B0_SPCR_BPEN_Pos); + + if (SPI_B_SSL_MODE_SPI == p_extend->spi_clksyn) + { + /* Configure SSL Level Keep Setting. */ + spcmd0 |= (uint32_t) (!p_ctrl->p_cfg->operating_mode << R_SPI_B0_SPCMD0_SSLKP_Pos); + } + else + { + /* Configure 3-Wire Mode Setting. */ + spcr |= R_SPI_B0_SPCR_SPMS_Msk; + } + + if (SPI_B_COMMUNICATION_FULL_DUPLEX == p_extend->spi_comm) + { + /* Enable Receive Buffer Full interrupt. */ + spcr |= R_SPI_B0_SPCR_SPRIE_Msk; + } + + /* Set TX Only or Full Duplex */ + spcr |= (uint32_t) (p_extend->spi_comm << R_SPI_B0_SPCR_TXMD_Pos); + + /* Configure SSLn polarity setting. */ + spcr3 &= ~0x0FU; + spcr3 |= (uint32_t) p_extend->ssl_polarity << p_extend->ssl_select; + + /* Configure bitrate */ + spcr3 |= ((uint32_t) p_extend->spck_div.spbr) << R_SPI_B0_SPCR3_SPBR_Pos; + + /* Configure SSLn setting. (SSL0, SSL1, SSL2, SSL3)*/ + spcmd0 &= ~R_SPI_B0_SPCMD0_SSLA_Msk; + spcmd0 |= (uint32_t) p_extend->ssl_select << R_SPI_B0_SPCMD0_SSLA_Pos; + + if (SPI_B_MOSI_IDLE_VALUE_FIXING_DISABLE != p_extend->mosi_idle) + { + /* Enable MOSI value fixing */ + spcr2 |= R_SPI_B0_SPCR2_MOIFE_Msk; + + if (SPI_B_MOSI_IDLE_VALUE_FIXING_HIGH == p_extend->mosi_idle) + { + spcr2 |= R_SPI_B0_SPCR2_MOIFV_Msk; + } + } + + if (SPI_B_PARITY_MODE_DISABLE != p_extend->parity) + { + /* Enable Parity Mode. */ + spcr |= R_SPI_B0_SPCR_SPPE_Msk; + + if (SPI_B_PARITY_MODE_ODD == p_extend->parity) + { + /* Configure ODD Parity Setting. */ + spcr |= R_SPI_B0_SPCR_SPOE_Msk; + } + } + + /* Configure byte swapping for 16/32-Bit mode. */ + spdcr |= p_extend->byte_swap; + + /* Configure the Bit Rate Division Setting */ + spcmd0 |= (uint32_t) p_extend->spck_div.brdv << R_SPI_B0_SPCMD0_BRDV_Pos; + + /* Enable all delay settings. */ + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) + { + if (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay) + { + /* Enable burst transfer without delay. */ + spcr |= R_SPI_B0_SPCR_BFDS_Msk; + + /* Transmit buffer empty flag is raised only when FIFO is fully empty (TTRG = 3). */ + p_ctrl->p_regs->SPDCR2 |= R_SPI_B0_SPDCR2_TTRG_Msk; + } + + /* Note that disabling delay settings is same as setting delay to 1. */ + spcmd0 |= (uint32_t) R_SPI_B0_SPCMD0_SPNDEN_Msk | R_SPI_B0_SPCMD0_SLNDEN_Msk | R_SPI_B0_SPCMD0_SCKDEN_Msk; + + spdecr = (uint32_t) ((p_extend->spck_delay << R_SPI_B0_SPDECR_SCKDL_Pos) | + (p_extend->ssl_negation_delay << R_SPI_B0_SPDECR_SLNDL_Pos) | + (p_extend->next_access_delay << R_SPI_B0_SPDECR_SPNDL_Pos)); + } + + /* Enable the SPI module. */ + R_BSP_MODULE_START(FSP_IP_SPI, p_ctrl->p_cfg->channel); + + /* Clear the status register. */ + p_ctrl->p_regs->SPSRC = SPI_B_PRV_SPSRC_ALL_CLEAR; + + /* Write registers */ + p_ctrl->p_regs->SPCR3 = spcr3; + p_ctrl->p_regs->SPDECR = spdecr; + p_ctrl->p_regs->SPCR2 = spcr2; + p_ctrl->p_regs->SPCMD0 = spcmd0; + p_ctrl->p_regs->SPDCR = spdcr; + + /* Set all SPCR bits except MSTR */ + p_ctrl->p_regs->SPCR = spcr & ~R_SPI_B0_SPCR_MSTR_Msk; + + /* Read back SPCR to ensure 1 TCLK has passed + * (see Note 1 of figure "Transmission flow in master mode" in the SPI section of the relevant hardware manual) */ + p_ctrl->p_regs->SPCR; + + /* Include MSTR bit */ + p_ctrl->p_regs->SPCR = spcr; +} + +/*******************************************************************************************************************//** + * Enable Receive Buffer Full, Transmit Buffer Empty, and Error Interrupts in the NVIC. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_b_nvic_config (spi_b_instance_ctrl_t * p_ctrl) +{ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->txi_irq, p_ctrl->p_cfg->txi_ipl, p_ctrl); + } + + if (p_ctrl->p_cfg->rxi_irq >= 0) + { + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->rxi_irq, p_ctrl->p_cfg->rxi_ipl, p_ctrl); + } + + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->eri_irq, p_ctrl->p_cfg->eri_ipl, p_ctrl); + + R_BSP_IrqCfg(p_ctrl->p_cfg->tei_irq, p_ctrl->p_cfg->tei_ipl, p_ctrl); + + /* Note tei_irq is not enabled until the last data frame is transferred. */ +} + +/*******************************************************************************************************************//** + * Setup the bit width configuration for a transfer. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_b_bit_width_config (spi_b_instance_ctrl_t * p_ctrl) +{ + uint32_t spcmd0 = p_ctrl->p_regs->SPCMD0; + + /* Configure data length based on the selected bit width . */ + spcmd0 &= ~R_SPI_B0_SPCMD0_SPB_Msk; + spcmd0 |= (uint32_t) (p_ctrl->bit_width) << R_SPI_B0_SPCMD0_SPB_Pos; + + spi_b_extended_cfg_t * p_extend = ((spi_b_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay))) + { + if (1 != p_ctrl->count) + { + /* Configure SSL Level Keep Setting if length is greater than 1. */ + spcmd0 |= R_SPI_B0_SPCMD0_SSLKP_Msk; + } + else + { + /* Disable SSL Level Keep since length is 1 (not a burst transfer). */ + spcmd0 &= ~R_SPI_B0_SPCMD0_SSLKP_Msk; + } + } + + p_ctrl->p_regs->SPCMD0 = spcmd0; +} + +/*******************************************************************************************************************//** + * Initiates a SPI transfer by setting the SPE bit in SPCR. + * + * @param[in] p_ctrl pointer to control structure. + * + * Note: When not using the DTC to transmit, this function pre-loads the SPI shift-register and shift-register-buffer + * instead of waiting for the transmit buffer empty interrupt. This is required when transmitting from the + * Receive Buffer Full interrupt, but it does not interfere with transmitting when using the transmit buffer empty + * interrupt. + **********************************************************************************************************************/ +static void r_spi_b_start_transfer (spi_b_instance_ctrl_t * p_ctrl) +{ + /* Clear FIFOs */ + p_ctrl->p_regs->SPFCR = 1; + +#if SPI_B_TRANSMIT_FROM_RXI_ISR == 1 + if (!p_ctrl->p_cfg->p_transfer_tx) + { + /* Handle the first two transmit empty events here because transmit interrupt may not be enabled. */ + + /* Critical section required so that the txi interrupt can be handled here instead of in the ISR. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Enable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 1; + + /* Must call transmit to kick off transfer when transmitting from rxi ISR. */ + r_spi_b_transmit(p_ctrl); ///< First data immediately copied into the SPI shift register. + + /* Second transmit significantly improves slave mode performance. */ + r_spi_b_transmit(p_ctrl); ///< Second data copied into the SPI transmit buffer. + + /* Must clear the txi IRQ status (The interrupt was handled here). */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + + FSP_CRITICAL_SECTION_EXIT; + } + else + { + /* Enable the SPI Transfer and TX buffer empty interrupt */ + p_ctrl->p_regs->SPCR |= R_SPI_B0_SPCR_SPTIE_Msk | R_SPI_B0_SPCR_SPE_Msk; + } + +#else + + /* Enable the SPI Transfer and TX buffer empty interrupt */ + p_ctrl->p_regs->SPCR |= R_SPI_B0_SPCR_SPTIE_Msk | R_SPI_B0_SPCR_SPE_Msk; +#endif +} + +/*******************************************************************************************************************//** + * Configures the driver state and initiates a SPI transfer for all modes of operation. + * + * @param[in] p_api_ctrl pointer to control structure. + * @param p_src Buffer to transmit data from. + * @param p_dest Buffer to store received data in. + * @param[in] length Number of transfers + * @param[in] bit_width Data frame size (8-Bit, 16-Bit, 32-Bit) + * + * @retval FSP_SUCCESS Transfer was started successfully. + * @retval FSP_ERR_ASSERTION An argument is invalid. + * @retval FSP_ERR_NOT_OPEN The instance has not been initialized. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally + * calls @ref transfer_api_t::reconfigure. + **********************************************************************************************************************/ +static fsp_err_t r_spi_b_write_read_common (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + spi_b_instance_ctrl_t * p_ctrl = (spi_b_instance_ctrl_t *) p_api_ctrl; + +#if SPI_B_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_B_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(p_src || p_dest); + FSP_ASSERT(0 != length); + + #if SPI_B_CFG_DMA_SUPPORT_ENABLE + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + transfer_properties_t transfer_info; + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(length <= transfer_info.transfer_length_max); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + transfer_properties_t transfer_info; + fsp_err_t err = p_ctrl->p_cfg->p_transfer_tx->p_api->infoGet(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ASSERT(length <= transfer_info.transfer_length_max); + } + #endif +#endif + + /* Check to ensure SPE is cleared after the last transmission. + * (see figure "Transmission flow in master mode" in the SPI section of the relevant hardware manual) */ + FSP_ERROR_RETURN(0 == p_ctrl->p_regs->SPPSR, FSP_ERR_IN_USE); + + p_ctrl->p_tx_data = p_src; + p_ctrl->p_rx_data = p_dest; + p_ctrl->tx_count = 0; + p_ctrl->rx_count = 0; + p_ctrl->count = length; + p_ctrl->bit_width = bit_width; + +#if SPI_B_CFG_DMA_SUPPORT_ENABLE == 1 + + /* Determine DTC transfer size */ + transfer_size_t size; + if (p_ctrl->bit_width > SPI_BIT_WIDTH_16_BITS) /* Bit Widths of 17-32 bits */ + { + size = TRANSFER_SIZE_4_BYTE; + } + else if (p_ctrl->bit_width > SPI_BIT_WIDTH_8_BITS) /* Bit Widths of 9-16 bits*/ + { + size = TRANSFER_SIZE_2_BYTE; + } + else /* Bit Widths of 4-8 bits */ + { + size = TRANSFER_SIZE_1_BYTE; + } + + if (p_ctrl->p_cfg->p_transfer_rx) + { + /* When the rxi interrupt is called, all transfers will be finished. */ + p_ctrl->rx_count = length; + + transfer_instance_t * p_transfer_rx = (transfer_instance_t *) p_ctrl->p_cfg->p_transfer_rx; + transfer_info_t * p_info = p_transfer_rx->p_cfg->p_info; + + /* Configure the receive DMA instance. */ + p_info->transfer_settings_word_b.size = size; + p_info->length = (uint16_t) length; + p_info->transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info->p_dest = p_dest; + + if (NULL == p_dest) + { + static uint32_t dummy_rx; + p_info->transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info->p_dest = &dummy_rx; + } + + fsp_err_t err = p_transfer_rx->p_api->reconfigure(p_transfer_rx->p_ctrl, p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (p_ctrl->p_cfg->p_transfer_tx) + { + /* When the txi interrupt is called, all transfers will be finished. */ + p_ctrl->tx_count = length; + + transfer_instance_t * p_transfer_tx = (transfer_instance_t *) p_ctrl->p_cfg->p_transfer_tx; + transfer_info_t * p_info = p_transfer_tx->p_cfg->p_info; + + /* Configure the transmit DMA instance. */ + p_info->transfer_settings_word_b.size = size; + + spi_b_extended_cfg_t * p_extend = ((spi_b_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay)) && + (1 != p_ctrl->count)) + { + /* When the txi interrupt is called, length - 1 frames have already been transferred. */ + p_ctrl->tx_count = length - 1; + p_info->length = (uint16_t) (length - 1U); + } + else + { + p_info->length = (uint16_t) length; + } + + p_info->transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info->p_src = p_src; + + if (NULL == p_src) + { + static uint32_t dummy_tx = 0; + p_info->transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info->p_src = &dummy_tx; + } + + /* Disable the TX buffer empty interrupt before enabling transfer. */ + p_ctrl->p_regs->SPCR_b.SPTIE = 0; + + fsp_err_t err = p_transfer_tx->p_api->reconfigure(p_transfer_tx->p_ctrl, p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif + + r_spi_b_bit_width_config(p_ctrl); + r_spi_b_start_transfer(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Copy configured bit width from the SPI data register to the current rx data location. + * If the receive buffer is NULL, just read the SPI data register. + * If the total transfer length has already been received than do nothing. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_b_receive (spi_b_instance_ctrl_t * p_ctrl) +{ + uint32_t rx_count = p_ctrl->rx_count; + if (rx_count == p_ctrl->count) + { + return; + } + + if (0 == p_ctrl->p_rx_data) + { + /* Read the received data but do nothing with it. */ + p_ctrl->p_regs->SPDR; + } + else + { + if (p_ctrl->bit_width > SPI_BIT_WIDTH_16_BITS) /* Bit Widths of 17-32 bits */ + { + ((uint32_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR; + } + else if (p_ctrl->bit_width > SPI_BIT_WIDTH_8_BITS) /* Bit Widths of 9-16 bits*/ + { + ((uint16_t *) (p_ctrl->p_rx_data))[rx_count] = (uint16_t) p_ctrl->p_regs->SPDR; + } + else /* Bit Widths of 4-8 bits */ + { + ((uint8_t *) (p_ctrl->p_rx_data))[rx_count] = (uint8_t) p_ctrl->p_regs->SPDR; + } + } + + /* Clear Receive Full flag */ + p_ctrl->p_regs->SPSRC = R_SPI_B0_SPSRC_SPRFC_Msk; + + p_ctrl->rx_count = rx_count + 1; +} + +/*******************************************************************************************************************//** + * Copy configured bit width from the current tx data location into the SPI data register. + * If the transmit buffer is NULL, than write zero to the SPI data register. + * If the total transfer length has already been transmitted than do nothing. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_b_transmit (spi_b_instance_ctrl_t * p_ctrl) +{ + uint32_t tx_count = p_ctrl->tx_count; + spi_b_extended_cfg_t * p_extend = ((spi_b_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay))) + { + if (0 == (p_ctrl->p_regs->SPSR & (1 << R_SPI_B0_SPSR_SPTEF_Pos))) + { + + /* The TXI interrupt is triggered by DTC automatically. + * Skip handling it, as the transmit buffer is already preloaded with data. */ + return; + } + + if (tx_count == (p_ctrl->count - 1)) + { + /* Disable SSLKP bit in last frame. */ + p_ctrl->p_regs->SPCMD0 &= (uint32_t) (~R_SPI_B0_SPCMD0_SSLKP_Msk); + } + } + + if (tx_count == p_ctrl->count) + { + return; + } + + if (0 == p_ctrl->p_tx_data) + { + /* Transmit zero if no tx buffer present. */ + p_ctrl->p_regs->SPDR = 0; + } + else + { + if (p_ctrl->bit_width > SPI_BIT_WIDTH_16_BITS) /* Bit Widths of 17-32 bits */ + { + p_ctrl->p_regs->SPDR = ((uint32_t *) p_ctrl->p_tx_data)[tx_count]; + } + else if (p_ctrl->bit_width > SPI_BIT_WIDTH_8_BITS) /* Bit Widths of 9-16 bits*/ + { + p_ctrl->p_regs->SPDR = ((uint16_t *) p_ctrl->p_tx_data)[tx_count]; + } + else /* Bit Widths of 4-8 bits */ + { + p_ctrl->p_regs->SPDR = ((uint8_t *) p_ctrl->p_tx_data)[tx_count]; + } + } + + /* Clear Transmit Empty flag */ + p_ctrl->p_regs->SPSRC = R_SPI_B0_SPSRC_SPTEFC_Msk; + + p_ctrl->tx_count = tx_count + 1; +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SPI instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_spi_b_call_callback (spi_b_instance_ctrl_t * p_ctrl, spi_event_t event) +{ + spi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + spi_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + spi_prv_ns_callback p_callback = (spi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Callback that must be called after a RX DMAC transfer completes. + * + * @param[in] p_ctrl Pointer to SPI_B instance control block + **********************************************************************************************************************/ +void spi_b_rx_dmac_callback (spi_b_instance_ctrl_t const * const p_ctrl) +{ + /* If the transmit and receive ISRs are too slow to keep up at high bitrates, + * the hardware will generate an interrupt before all of the transfers are completed. + * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); +} + +/*******************************************************************************************************************//** + * ISR called when data is loaded into SPI data register from the shift register. + **********************************************************************************************************************/ +void spi_b_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + spi_b_instance_ctrl_t * p_ctrl = (spi_b_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + r_spi_b_receive(p_ctrl); + +#if SPI_B_TRANSMIT_FROM_RXI_ISR == 1 + spi_b_extended_cfg_t * p_extend = ((spi_b_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + /* Skip r_spi_b_transmit() when operating in master mode with burst transfer without delay and a transfer instance is used. */ + if ((!p_ctrl->p_cfg->p_transfer_tx) || + (!(p_extend && (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay))) || + (SPI_MODE_MASTER != p_ctrl->p_cfg->operating_mode)) + { + /* It is a little faster to handle the transmit buffer empty event in the receive buffer full ISR. + * Note that this is only possible when the instance is not using a transfer instance to receive data. */ + r_spi_b_transmit(p_ctrl); + } +#endif + + if (p_ctrl->rx_count == p_ctrl->count) + { + /* If the transmit and receive ISRs are too slow to keep up at high bitrates, + * the hardware will generate an interrupt before all of the transfers are completed. + * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR called when data is copied from the SPI data register into the SPI shift register. + **********************************************************************************************************************/ +void spi_b_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + spi_b_instance_ctrl_t * p_ctrl = (spi_b_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + spi_b_extended_cfg_t * p_extend = ((spi_b_extended_cfg_t *) p_ctrl->p_cfg->p_extend); +#if SPI_B_TRANSMIT_FROM_RXI_ISR == 0 + if (SPI_B_COMMUNICATION_TRANSMIT_ONLY == p_extend->spi_comm) + { + /* Only enable the transfer end ISR if there are no receive buffer full interrupts expected to be handled + * after this interrupt. */ + if (p_ctrl->tx_count == p_ctrl->count - 1) + { + /* If the transmit and receive ISRs are too slow to keep up at high bitrates, + * the hardware will generate an interrupt before all of the transfers are completed. + * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->tei_irq); + } + else if (p_ctrl->p_cfg->p_transfer_tx) + { + /* If DMA is used to transmit data, enable the interrupt after all the data has been transferred, but do not + * clear the IRQ Pending Bit. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + else + { + } + } + + /* Transmit happens after checking if the last transfer has been written to the transmit buffer in order + * to ensure that the end interrupt is not enabled while there is data still in the transmit buffer. */ + r_spi_b_transmit(p_ctrl); +#else + + /* Send last frame in master mode with burst transfer without delay. */ + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay))) + { + r_spi_b_transmit(p_ctrl); + } +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR called when the SPI peripheral transitions from the transferring state to the IDLE state. + **********************************************************************************************************************/ +void spi_b_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + spi_b_instance_ctrl_t * p_ctrl = (spi_b_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if ((0 == p_ctrl->p_regs->SPSR_b.IDLNF) || (SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode)) + { + R_BSP_IrqDisable(irq); + + /* Writing 0 to SPE generatates a TXI IRQ. Disable the TXI IRQ. + * (See "SPI Control Register (SPCR)" description in the relevant hardware manual). */ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + /* Writing 0 to SPE generatates a TXI IRQ. Disable the TXI IRQ.* (See "SPI Control Register (SPCR)" description in the relevant hardware manual). */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0; + + /* Re-enable the TXI IRQ and clear the pending IRQ. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + } + else + { + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0; + } + + /* Signal that a transfer has completed. */ + r_spi_b_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * ISR called in the event that an error occurs (Ex: RX_OVERFLOW). + **********************************************************************************************************************/ +void spi_b_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + spi_b_instance_ctrl_t * p_ctrl = (spi_b_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Writing 0 to SPE generatates a TXI IRQ. Disable the TXI IRQ. + * (See "SPI Control Register (SPCR)" description in the relevant hardware manual). */ + if (p_ctrl->p_cfg->txi_irq >= 0) + { + /* Writing 0 to SPE generatates a TXI IRQ. Disable the TXI IRQ.* (See "SPI Control Register (SPCR)" description in the relevant hardware manual). */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0; + + /* Re-enable the TXI IRQ and clear the pending IRQ. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + } + else + { + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0; + } + + /* Read the status register. */ + uint32_t status = p_ctrl->p_regs->SPSR; + + /* Clear the status register. */ + p_ctrl->p_regs->SPSRC = SPI_B_PRV_SPSRC_ALL_CLEAR; + + /* Check if the error is a Parity Error. */ + if (R_SPI_B0_SPSR_PERF_Msk & status) + { + r_spi_b_call_callback(p_ctrl, SPI_EVENT_ERR_PARITY); + } + + /* Check if the error is a Receive Buffer Overflow Error. */ + if (R_SPI_B0_SPSR_OVRF_Msk & status) + { + r_spi_b_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); + } + + /* Check if the error is a Mode Fault Error. */ + if (R_SPI_B0_SPSR_MODF_Msk & status) + { + /* Check if the error is a Transmit Buffer Underflow Error. */ + if (R_SPI_B0_SPSR_UDRF_Msk & status) + { + r_spi_b_call_callback(p_ctrl, SPI_EVENT_ERR_MODE_UNDERRUN); + } + } + + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Callback that must be called after a TX DMAC transfer completes. + * + * @param[in] p_ctrl Pointer to SPI_B instance control block + **********************************************************************************************************************/ +void spi_b_tx_dmac_callback (spi_b_instance_ctrl_t const * const p_ctrl) +{ + spi_b_extended_cfg_t * p_extend = ((spi_b_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + +/* Send last frame if transfer length is greater than 1. */ + if ((SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) && + (p_extend && (SPI_B_BURST_TRANSFER_WITHOUT_DELAY == p_extend->burst_interframe_delay)) && + (1 != p_ctrl->count)) + { + FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_regs->SPSR_b.SPTEF, 1U); + r_spi_b_transmit((spi_b_instance_ctrl_t *) p_ctrl); + } + +#if SPI_B_TRANSMIT_FROM_RXI_ISR == 0 + if (p_extend && (SPI_B_COMMUNICATION_TRANSMIT_ONLY == p_extend->spi_comm)) + { + /* Only enable the transfer end ISR if there are no receive buffer full interrupts expected to be handled + * after this interrupt. */ + + /* If DMA is used to transmit data, enable the interrupt after all the data has been transferred, but do not + * clear the IRQ Pending Bit. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif +} + +/* End of file R_SPI. */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ssi/r_ssi.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ssi/r_ssi.c new file mode 100644 index 0000000000..489f1b403a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ssi/r_ssi.c @@ -0,0 +1,1282 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_i2s_api.h" +#include "r_ssi.h" +#include "r_ssi_cfg.h" +#if SSI_CFG_DTC_ENABLE + #include "r_dtc.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SSI_PRV_SSICR_REN_TEN_MASK (3U) +#define SSI_PRV_SSICR_TEN_BIT (2U) +#define SSI_PRV_SSICR_REN_BIT (1U) + +#define SSI_PRV_SSISR_EVENT_FLAG_MASK (0x3E000000U) +#define SSI_PRV_SSICR_TX_RX_IRQ_MASK (0x3C000000U) + +#define SSI_PRV_SSIFCR_AUCKE_BIT (31U) +#define SSI_PRV_SSIFCR_SSIRST_BIT (16U) +#define SSI_PRV_SSIFCR_TIE_BIT (3U) +#define SSI_PRV_SSIFCR_RIE_BIT (2U) +#define SSI_PRV_SSIFCR_TFRST_RFRST_MASK (3U) + +#define SSI_PRV_SSICR_TUIEN_BIT (29U) +#define SSI_PRV_SSICR_ROIEN_BIT (26U) +#define SSI_PRV_SSICR_IIEN_BIT (25U) +#define SSI_PRV_SSICR_CKS_BIT (30U) +#define SSI_PRV_SSICR_SWL_BIT (16U) +#define SSI_PRV_SSICR_DWL_BIT (19U) +#define SSI_PRV_SSICR_MST_BIT (14U) +#define SSI_PRV_SSICR_PDTA_BIT (9U) +#define SSI_PRV_SSICR_CKDV_BIT (4U) + +#define SSI_PRV_SSISR_TUIRQ_BIT (29U) +#define SSI_PRV_SSISR_ROIRQ_BIT (26U) + +#define SSI_PRV_SSIOFR_LRCONT_BIT (8U) + +#define SSI_PRV_TRANSFER_BLOCK_SIZE (2U) + +/* SSIFSR has two flags that can be cleared (TDE and RDF). The other fields in SSIFSR are read only or reserved. To + * clear one of these flags, set the other to 1 to avoid clearing it, and write all other bits to 0. */ +#define SSI_PRV_SSIFSR_RDF_CLEAR (1U << 16) +#define SSI_PRV_SSIFSR_TDE_CLEAR (1U) + +/* I2S protocol always has 2 channels (left and right). */ +#define SSI_PRV_I2S_CHANNELS (2U) +#define SSI_PRV_BITS_PER_BYTE (8U) + +/* "SSI" in ASCII, used to determine if driver is open. */ +#define SSI_PRV_OPEN (0x535349U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * i2s_prv_ns_callback)(i2s_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile i2s_prv_ns_callback)(i2s_callback_args_t * p_args); +#endif + +/* SSI communication direction */ +typedef enum e_ssi_dir +{ + SSI_DIR_RX = 1U, ///< Receive direction only + SSI_DIR_TX = 2U, ///< Transmit direction only + SSI_DIR_TX_RX = 3U, ///< Transmit and receive direction +} ssi_dir_t; + +/* Arguments are stored in a structure for transfer reset subroutine to avoid having more than 4 arguments. */ +typedef struct e_ssi_prv_transfer_reset +{ + void const * p_data; + uint32_t bytes; + void const * p_src; + void * p_dest; +} ssi_prv_transfer_reset_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/* ISRs */ +void ssi_txi_isr(void); +void ssi_rxi_isr(void); +void ssi_int_isr(void); + +static void r_ssi_call_callback(ssi_instance_ctrl_t * p_ctrl, i2s_event_t event); + +/* ISR subroutines */ +static void r_ssi_tx_fifo_write(ssi_instance_ctrl_t * p_instance_ctrl, uint32_t stages_to_write); +static void r_ssi_rx_fifo_read(ssi_instance_ctrl_t * p_instance_ctrl, uint32_t stages_to_read); + +/* FIFO subroutines */ +static void r_ssi_fifo_write(ssi_instance_ctrl_t * p_instance_ctrl); +static void r_ssi_fifo_read(ssi_instance_ctrl_t * p_instance_ctrl); + +/* Open subroutines */ + +static void r_ssi_interrupts_configure(ssi_instance_ctrl_t * const p_instance_ctrl, i2s_cfg_t const * const p_cfg); + +#if SSI_CFG_DTC_ENABLE +static fsp_err_t r_ssi_dependent_drivers_configure(R_SSI0_Type * p_reg, + i2s_cfg_t const * const p_cfg, + transfer_size_t fifo_access_size); + +#endif + +/* Stop subroutines */ +static void r_ssi_stop_sub(ssi_instance_ctrl_t * const p_instance_ctrl); + +/* Start subroutines */ +static fsp_err_t r_ssi_start(ssi_instance_ctrl_t * const p_instance_ctrl, ssi_dir_t dir); + +/* Read and write subroutines. */ +fsp_err_t r_ssi_tx_load_fifo(ssi_instance_ctrl_t * const p_instance_ctrl, void const * const p_src, + uint32_t const bytes); +fsp_err_t r_ssi_rx_unload_fifo(ssi_instance_ctrl_t * const p_instance_ctrl, void * const p_dest, uint32_t const bytes); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** SSI Implementation of I2S interface. */ +const i2s_api_t g_i2s_on_ssi = +{ + .open = R_SSI_Open, + .stop = R_SSI_Stop, + .write = R_SSI_Write, + .read = R_SSI_Read, + .writeRead = R_SSI_WriteRead, + .mute = R_SSI_Mute, + .statusGet = R_SSI_StatusGet, + .close = R_SSI_Close, + .callbackSet = R_SSI_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup SSI + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens the SSI. Implements @ref i2s_api_t::open. + * + * This function sets this clock divisor and the configurations specified in i2s_cfg_t. It also opens the timer and + * transfer instances if they are provided. + * + * @retval FSP_SUCCESS Ready for I2S communication. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl or p_cfg is null. + * @retval FSP_ERR_ALREADY_OPEN The control block has already been opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel number is not available on this MCU. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_SSI_Open (i2s_ctrl_t * const p_ctrl, i2s_cfg_t const * const p_cfg) +{ + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) p_ctrl; + +#if SSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(p_cfg->int_irq >= 0); + if (I2S_MODE_MASTER == p_cfg->operating_mode) + { + FSP_ASSERT(NULL != p_cfg->p_extend); + } + + #if SSI_CFG_DTC_ENABLE + if (NULL != p_cfg->p_transfer_rx) + { + dtc_extended_cfg_t * p_dtc_rx_cfg = (dtc_extended_cfg_t *) p_cfg->p_transfer_rx->p_cfg->p_extend; + FSP_ASSERT(NULL != p_dtc_rx_cfg); + FSP_ASSERT(p_cfg->rxi_irq == p_dtc_rx_cfg->activation_source); + } + + if (NULL != p_cfg->p_transfer_tx) + { + dtc_extended_cfg_t * p_dtc_tx_cfg = (dtc_extended_cfg_t *) p_cfg->p_transfer_tx->p_cfg->p_extend; + FSP_ASSERT(NULL != p_dtc_tx_cfg); + FSP_ASSERT(p_cfg->txi_irq == p_dtc_tx_cfg->activation_source); + } + #endif + + FSP_ERROR_RETURN(SSI_PRV_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(0U != ((1U << p_cfg->channel) & BSP_FEATURE_SSI_VALID_CHANNEL_MASK), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + +#if BSP_FEATURE_SSI_VALID_CHANNEL_MASK == 1 + uint32_t base_address = (uint32_t) R_SSI0; +#else + + /* Calculate base address for registers on this channel. */ + uint32_t base_address = (uint32_t) R_SSI0 + (p_cfg->channel * ((uint32_t) R_SSI1 - (uint32_t) R_SSI0)); +#endif + R_SSI0_Type * p_reg = (R_SSI0_Type *) base_address; + + /* Determine how to access the FIFO (1 byte, 2 byte, or 4 byte access). */ + transfer_size_t fifo_access_size = TRANSFER_SIZE_4_BYTE; + if (I2S_PCM_WIDTH_8_BITS == p_cfg->pcm_width) + { + fifo_access_size = TRANSFER_SIZE_1_BYTE; + } + + if (I2S_PCM_WIDTH_16_BITS == p_cfg->pcm_width) + { + fifo_access_size = TRANSFER_SIZE_2_BYTE; + } + +#if SSI_CFG_DTC_ENABLE + + /* Configure dependent timer and transfer drivers. */ + fsp_err_t err = r_ssi_dependent_drivers_configure(p_reg, p_cfg, fifo_access_size); + FSP_ERROR_RETURN((FSP_SUCCESS == err), err); +#endif + + /* Initialize the control structure. */ + p_instance_ctrl->p_reg = p_reg; + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->fifo_access_size = fifo_access_size; + + /* Configure interrupts. */ + r_ssi_interrupts_configure(p_instance_ctrl, p_cfg); + + /* Calculate register settings. */ + + /* Configure operating mode. */ + uint32_t ssifcr = (uint32_t) p_cfg->operating_mode << SSI_PRV_SSIFCR_AUCKE_BIT; + uint32_t ssicr = (uint32_t) p_cfg->operating_mode << SSI_PRV_SSICR_MST_BIT; + + /* Configure sample size, and word length. */ + ssicr |= (uint32_t) p_cfg->word_length << SSI_PRV_SSICR_SWL_BIT; + ssicr |= (uint32_t) p_cfg->pcm_width << SSI_PRV_SSICR_DWL_BIT; + if ((p_cfg->pcm_width > I2S_PCM_WIDTH_16_BITS) && (p_cfg->pcm_width < I2S_PCM_WIDTH_32_BITS)) + { + /* Right justify data for 18-bit, 20-bit, 22-bit, or 24-bit samples. This setting is prohibited for 8-bit, + * 16-bit, and 32-bit samples */ + ssicr |= (1U << SSI_PRV_SSICR_PDTA_BIT); + } + + /* Configure audio clock and WS continue in master mode only. */ + uint32_t ssiofr = 0U; + if (I2S_MODE_MASTER == p_cfg->operating_mode) + { + ssi_extended_cfg_t * p_extend = (ssi_extended_cfg_t *) p_cfg->p_extend; + ssicr |= (uint32_t) p_extend->bit_clock_div << SSI_PRV_SSICR_CKDV_BIT; + ssicr |= (uint32_t) p_extend->audio_clock << SSI_PRV_SSICR_CKS_BIT; + + if (I2S_WS_CONTINUE_ON == p_cfg->ws_continue) + { + ssiofr |= (1U << SSI_PRV_SSIOFR_LRCONT_BIT); + } + } + + /* Set SSIE receive FIFO watermark to exactly the DTC block size so the DTC triggers as soon as there is + * a block of data in the FIFO. */ + uint32_t rx_fifo_setting = SSI_PRV_TRANSFER_BLOCK_SIZE - 1U; + + /* Set SSIE transmit FIFO watermark to trigger when 1/2 of the FIFO is empty so that read and write are less + * likely to trigger at the same time. */ + uint32_t tx_fifo_setting = (BSP_FEATURE_SSI_FIFO_NUM_STAGES / 2U) - 1U; + uint32_t ssiscr = (tx_fifo_setting << 8) | rx_fifo_setting; + + /* Initialize the SSIE following the procedure in Figure "Procedure to start communication (CPU operation + * procedure)" in the SSIE section of the relevant hardware manual + * This function follows this procedure except for enabling + * interrupts and enabling communication, which are done before communication begins. */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + /* Enable PCLK to SSIE. */ + R_BSP_MODULE_START(FSP_IP_SSI, p_instance_ctrl->p_cfg->channel); + + /* Configure master/slave mode and associated clock settings for master mode. */ + p_instance_ctrl->p_reg->SSICR = ssicr; + + /* Reset SSIE and set operating mode. Set SSIRST, then clear it and wait for it to clear. This operation resets + * all interrupt flags in SSISR and empties the FIFOs. */ + p_instance_ctrl->p_reg->SSIFCR = ssifcr | (1U << SSI_PRV_SSIFCR_SSIRST_BIT); + p_instance_ctrl->p_reg->SSIFCR = ssifcr; + + /* Wait for SSIRST to clear before continuing. See SSIRST in "FIFO Control Register (SSIFCR)" description + * in the SSIE section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->SSIFCR, ssifcr); + + p_instance_ctrl->p_reg->SSISCR = ssiscr; + p_instance_ctrl->p_reg->SSIOFR = ssiofr; + + /* Initialization complete. */ + p_instance_ctrl->open = SSI_PRV_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes data buffer to SSI. Implements @ref i2s_api_t::write. + * + * This function resets the transfer if the transfer interface is used, or writes the length of data that fits in the + * FIFO then stores the remaining write buffer in the control block to be written in the ISR. + * + * Write() cannot be called if another write(), read() or writeRead() operation is in progress. Write can be called + * when the SSI is idle, or after the I2S_EVENT_TX_EMPTY event. + * + * @retval FSP_SUCCESS Write initiated successfully. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl or p_src was null, or bytes requested was 0. + * @retval FSP_ERR_IN_USE Another transfer is in progress, data was not written. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @retval FSP_ERR_UNDERFLOW A transmit underflow error is pending. Wait for the SSI to go idle before + * resuming communication. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. This function calls: + * * @ref transfer_api_t::reset + **********************************************************************************************************************/ +fsp_err_t R_SSI_Write (i2s_ctrl_t * const p_ctrl, void const * const p_src, uint32_t const bytes) +{ + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) p_ctrl; + +#if SSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_src); + + /* bytes must be a non-zero */ + FSP_ASSERT(bytes > 0U); +#endif + + /* If a transfer instance is provided for write, reset the transfer. Otherwise store data to transmit in the + * transmit interrupt. */ + fsp_err_t err = r_ssi_tx_load_fifo(p_instance_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If a transmit underflow is pending, return an error. This could happen if the application is in an interrupt + * context with a priority greater than or equal to the idle/error interrupt priority and does not reload the + * transmit FIFO before it underflows. */ + FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->SSISR_b.TUIRQ, FSP_ERR_UNDERFLOW); + + /* Make sure transmission is enabled. */ + err = r_ssi_start(p_instance_ctrl, SSI_DIR_TX); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads data into provided buffer. Implements @ref i2s_api_t::read. + * + * This function resets the transfer if the transfer interface is used, or reads the length of data available in the + * FIFO then stores the remaining read buffer in the control block to be filled in the ISR. + * + * Read() cannot be called if another write(), read() or writeRead() operation is in progress. Read can be called + * when the SSI is idle, or after the I2S_EVENT_RX_FULL event. + * + * @retval FSP_SUCCESS Read initiated successfully. + * @retval FSP_ERR_IN_USE Peripheral is in the wrong mode or not idle. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl or p_dest was null, or bytes requested was 0. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @retval FSP_ERR_OVERFLOW A receive overflow error is pending. Wait for the SSI to go idle before + * resuming communication. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. This function calls: + * * @ref transfer_api_t::reset + **********************************************************************************************************************/ +fsp_err_t R_SSI_Read (i2s_ctrl_t * const p_ctrl, void * const p_dest, uint32_t const bytes) +{ + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) p_ctrl; + +#if SSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_dest); + + /* bytes must be a non-zero */ + FSP_ASSERT(bytes > 0U); +#endif + + /* If a transfer instance is provided for read, reset the transfer. Otherwise store data to receive in the receive + * interrupt. */ + fsp_err_t err = r_ssi_rx_unload_fifo(p_instance_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If a receive overflow is pending, return an error. This could happen if the application is in an interrupt + * context with a priority greater than or equal to the idle/error interrupt priority and does not read from the + * receive FIFO before it overflows. */ + FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->SSISR_b.ROIRQ, FSP_ERR_OVERFLOW); + + /* Make sure reception is enabled. */ + err = r_ssi_start(p_instance_ctrl, SSI_DIR_RX); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes from source buffer and reads data into destination buffer. Implements @ref i2s_api_t::writeRead. + * + * This function calls R_SSI_Write and R_SSI_Read. + * + * writeRead() cannot be called if another write(), read() or writeRead() operation is in progress. writeRead() can be + * called when the SSI is idle, or after the I2S_EVENT_RX_FULL event. + * + * @retval FSP_SUCCESS Write and read initiated successfully. + * @retval FSP_ERR_IN_USE Peripheral is in the wrong mode or not idle. + * @retval FSP_ERR_ASSERTION An input parameter was invalid. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @retval FSP_ERR_UNDERFLOW A transmit underflow error is pending. Wait for the SSI to go idle before + * resuming communication. + * @retval FSP_ERR_OVERFLOW A receive overflow error is pending. Wait for the SSI to go idle before + * resuming communication. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. This function calls: + * * @ref transfer_api_t::reset + **********************************************************************************************************************/ +fsp_err_t R_SSI_WriteRead (i2s_ctrl_t * const p_ctrl, + void const * const p_src, + void * const p_dest, + uint32_t const bytes) +{ + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) p_ctrl; + +#if SSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* bytes must be a non-zero */ + FSP_ASSERT(bytes > 0U); +#endif + + /* If a transfer instance is provided for write, reset the transfer. Reset the transmit FIFO first since the + * transmit FIFO will underflow before the receive FIFO overflows during full duplex communication. */ + fsp_err_t err = r_ssi_tx_load_fifo(p_instance_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If a transfer instance is provided for read, reset the transfer. */ + err = r_ssi_rx_unload_fifo(p_instance_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* If a transmit underflow or receive overflow is pending, return an error. This could happen if the application + * is in an interrupt context with a priority greater than or equal to the idle/error interrupt priority and does + * not reload the FIFOs before they underflow/overflow. */ + uint32_t ssisr = p_instance_ctrl->p_reg->SSISR; + FSP_ERROR_RETURN(0U == (ssisr & (1U << SSI_PRV_SSISR_TUIRQ_BIT)), FSP_ERR_UNDERFLOW); + FSP_ERROR_RETURN(0U == (ssisr & (1U << SSI_PRV_SSISR_ROIRQ_BIT)), FSP_ERR_OVERFLOW); + + /* Make sure transmission and reception are enabled. */ + err = r_ssi_start(p_instance_ctrl, SSI_DIR_TX_RX); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops SSI. Implements @ref i2s_api_t::stop. + * + * This function disables both transmission and reception, and disables any transfer instances used. + * + * The SSI will stop on the next frame boundary. Do not restart SSI until it is idle. + * + * @retval FSP_SUCCESS I2S communication stop request issued. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + * @return See @ref RENESAS_ERROR_CODES or lower level drivers for other possible return codes. + **********************************************************************************************************************/ +fsp_err_t R_SSI_Stop (i2s_ctrl_t * const p_ctrl) +{ + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) p_ctrl; + +#if SSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Stop is complete after an I2S_EVENT_IDLE interrupt. */ + r_ssi_stop_sub(p_instance_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Mutes SSI on the next frame boundary. Implements @ref i2s_api_t::mute. + * + * Data is still written while mute is enabled, but the transmit line outputs zeros. + * + * @retval FSP_SUCCESS Transmission is muted. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_SSI_Mute (i2s_ctrl_t * const p_ctrl, i2s_mute_t const mute_enable) +{ + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) p_ctrl; + +#if SSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->p_reg->SSICR_b.MUEN = mute_enable; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Gets SSI status and stores it in provided pointer p_status. Implements @ref i2s_api_t::statusGet. + * + * @retval FSP_SUCCESS Information stored successfully. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl or p_status parameter was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_SSI_StatusGet (i2s_ctrl_t * const p_ctrl, i2s_status_t * const p_status) +{ + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) p_ctrl; + +#if SSI_CFG_PARAM_CHECKING_ENABLE + + /* Make sure parameters are valid. */ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_status->state = (i2s_state_t) p_instance_ctrl->p_reg->SSISR_b.IIRQ; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Closes SSI. Implements @ref i2s_api_t::close. + * + * This function powers down the SSI and closes the lower level timer and transfer drivers if they are used. + * + * @retval FSP_SUCCESS Device closed successfully. + * @retval FSP_ERR_ASSERTION The pointer to p_ctrl was null. + * @retval FSP_ERR_NOT_OPEN The channel is not opened. + **********************************************************************************************************************/ +fsp_err_t R_SSI_Close (i2s_ctrl_t * const p_ctrl) +{ + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) p_ctrl; +#if SSI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->open = 0U; + + /* Stop SSIE. */ + p_instance_ctrl->p_reg->SSICR = 0U; + p_instance_ctrl->p_reg->SSIFCR = 0U; + + /* Disable interrupts. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->int_irq); + if (p_instance_ctrl->p_cfg->rxi_irq >= 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->rxi_irq); + } + + if (p_instance_ctrl->p_cfg->txi_irq >= 0) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->txi_irq); + } + +#if SSI_CFG_DTC_ENABLE + + /* If transfer is used, disable transfer when stop is requested. */ + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + (void) p_instance_ctrl->p_cfg->p_transfer_rx->p_api->close(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + (void) p_instance_ctrl->p_cfg->p_transfer_tx->p_api->close(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + /* Stop feeding clock to SSI peripheral to deactivate it. */ + R_BSP_MODULE_STOP(FSP_IP_SSI, p_instance_ctrl->p_cfg->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2s_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SSI_CallbackSet (i2s_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2s_callback_args_t *), + void * const p_context, + i2s_callback_args_t * const p_callback_memory) +{ + ssi_instance_ctrl_t * p_ctrl = (ssi_instance_ctrl_t *) p_api_ctrl; + +#if (SSI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SSI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + i2s_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(i2s_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup R_SSI) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * For each interrupt, if it is enabled, sets the interrupt priority based on user configuration and stores the control + * block so it can be accessed in the ISR. + * + * @param[in] p_instance_ctrl Pointer to the control block. + * @param[in] p_cfg Pointer to the configuration structure. + **********************************************************************************************************************/ +static void r_ssi_interrupts_configure (ssi_instance_ctrl_t * const p_instance_ctrl, i2s_cfg_t const * const p_cfg) +{ + /* Set interrupt priority based on user configuration of interrupt number for FSP_SIGNAL_SSI_INT signal */ + R_BSP_IrqCfgEnable(p_cfg->int_irq, p_cfg->idle_err_ipl, p_instance_ctrl); + + /* Set interrupt priority based on user configuration of interrupt number for FSP_SIGNAL_SSI_RXI + * or FSP_SIGNAL_SSI_TXI_RXI signals */ + if (p_cfg->rxi_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->rxi_ipl, p_instance_ctrl); + } + + /* Set interrupt priority based on user configuration of interrupt number for FSP_SIGNAL_SSI_TXI + * or FSP_SIGNAL_SSI_TXI_RXI signals */ + if (p_cfg->txi_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->txi_ipl, p_instance_ctrl); + } +} + +#if SSI_CFG_DTC_ENABLE + +/*******************************************************************************************************************//** + * Configures any dependent drivers selected by the user, including transfer and timer drivers. + * + * @param[in] p_reg Pointer to SSIE base register address for this channel. + * @param[in] p_cfg Pointer to the configuration structure. + * + * @retval FSP_SUCCESS Dependent drivers configured successfully. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +static fsp_err_t r_ssi_dependent_drivers_configure (R_SSI0_Type * p_reg, + i2s_cfg_t const * const p_cfg, + transfer_size_t fifo_access_size) +{ + /* Prepare transfer configuration. */ + fsp_err_t err_transfer_tx = FSP_SUCCESS; + fsp_err_t err_transfer_rx = FSP_SUCCESS; + + /* Use block mode to fill or empty half the FIFO at a time. See Figure "Procedure to start + * communication (CPU operation procedure)" in the SSIE section of the relevant hardware manual. */ + uint32_t transfer_settings = (uint32_t) TRANSFER_MODE_BLOCK << TRANSFER_SETTINGS_MODE_BITS; + transfer_settings |= (uint32_t) fifo_access_size << TRANSFER_SETTINGS_SIZE_BITS; + + /* If a transfer instance is provided for write, open the transfer instance. */ + if (NULL != p_cfg->p_transfer_tx) + { + p_cfg->p_transfer_tx->p_cfg->p_info->p_dest = (void *) &(p_reg->SSIFTDR); + uint32_t transfer_settings_tx = transfer_settings | + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS); + p_cfg->p_transfer_tx->p_cfg->p_info->transfer_settings_word = transfer_settings_tx; + p_cfg->p_transfer_tx->p_cfg->p_info->length = SSI_PRV_TRANSFER_BLOCK_SIZE; + err_transfer_tx = p_cfg->p_transfer_tx->p_api->open(p_cfg->p_transfer_tx->p_ctrl, p_cfg->p_transfer_tx->p_cfg); + } + + #if SSI_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN((FSP_SUCCESS == err_transfer_tx), err_transfer_tx); + #else + FSP_PARAMETER_NOT_USED(err_transfer_tx); + #endif + + /* If a transfer instance is provided for read, open the transfer instance. */ + if (NULL != p_cfg->p_transfer_rx) + { + p_cfg->p_transfer_rx->p_cfg->p_info->p_src = (void *) &(p_reg->SSIFRDR); + uint32_t transfer_settings_rx = transfer_settings | + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS) | + (TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS); + p_cfg->p_transfer_rx->p_cfg->p_info->transfer_settings_word = transfer_settings_rx; + p_cfg->p_transfer_rx->p_cfg->p_info->length = SSI_PRV_TRANSFER_BLOCK_SIZE; + err_transfer_rx = p_cfg->p_transfer_rx->p_api->open(p_cfg->p_transfer_rx->p_ctrl, p_cfg->p_transfer_rx->p_cfg); + } + + #if SSI_CFG_PARAM_CHECKING_ENABLE + + /* If there was an error opening the receive transfer, close the transmit transfer before returning. */ + if (FSP_SUCCESS != err_transfer_rx) + { + if (NULL != p_cfg->p_transfer_tx) + { + p_cfg->p_transfer_tx->p_api->close(p_cfg->p_transfer_tx->p_ctrl); + } + } + + FSP_ERROR_RETURN((FSP_SUCCESS == err_transfer_rx), err_transfer_rx); + #else + FSP_PARAMETER_NOT_USED(err_transfer_rx); + #endif + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Disables SSI transmission and reception. + * + * @param[in] p_instance_ctrl Pointer to the control block. + **********************************************************************************************************************/ +static void r_ssi_stop_sub (ssi_instance_ctrl_t * const p_instance_ctrl) +{ + /* Stop communication following the procedure from Figure "Procedure to halt communication (CPU operation + * procedure)" in the SSIE section of the relevant hardware manual. */ + + /* Disable transmission and reception and associated interrupts. Enable idle interrupt. */ + uint32_t ssicr = p_instance_ctrl->p_reg->SSICR; + ssicr &= ~SSI_PRV_SSICR_REN_TEN_MASK; + ssicr &= ~SSI_PRV_SSICR_TX_RX_IRQ_MASK; + ssicr |= (1U << SSI_PRV_SSICR_IIEN_BIT); + + p_instance_ctrl->p_reg->SSICR = ssicr; + + uint32_t ssifcr = p_instance_ctrl->p_reg->SSIFCR; + ssifcr &= ~(R_SSI0_SSIFCR_TIE_Msk | R_SSI0_SSIFCR_RIE_Msk); + p_instance_ctrl->p_reg->SSIFCR = ssifcr; + +#if SSI_CFG_DTC_ENABLE + + /* If transfer is used, disable transfer when stop is requested. */ + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + (void) p_instance_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + (void) p_instance_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + /* Disable interrupt output. Clear RIE and TIE by clearing all bits except AUCKE, which is set or cleared depending + * on the mode. All other bits can be set to 0. */ + p_instance_ctrl->p_reg->SSIFCR = (uint32_t) p_instance_ctrl->p_cfg->operating_mode << SSI_PRV_SSIFCR_AUCKE_BIT; + + /* Clear control structure data. */ + p_instance_ctrl->p_tx_src = NULL; + p_instance_ctrl->tx_src_samples = 0U; + p_instance_ctrl->p_rx_dest = NULL; + p_instance_ctrl->rx_dest_samples = 0U; +} + +/*******************************************************************************************************************//** + * Configures the transmit FIFO to be loaded by DTC or stores the source data to be loaded into the FIFO in the transmit + * interrupt. + * + * @param[in] p_instance_ctrl Pointer to the control block. + * @param[in] p_src Pointer to the source buffer. + * @param[in] bytes Length of source buffer. + * + * @retval FSP_SUCCESS Transmit FIFO successfully loaded. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. This function calls: + * * @ref transfer_api_t::reset + **********************************************************************************************************************/ +fsp_err_t r_ssi_tx_load_fifo (ssi_instance_ctrl_t * const p_instance_ctrl, + void const * const p_src, + uint32_t const bytes) +{ + void * p_data = (void *) p_src; + uint32_t samples = bytes >> p_instance_ctrl->fifo_access_size; +#if SSI_CFG_DTC_ENABLE + + /* By default, bytes are written in the ISR. */ + + /* If a transfer instance is provided, reset the transfer. */ + transfer_instance_t const * const p_transfer = p_instance_ctrl->p_cfg->p_transfer_tx; + if (NULL != p_transfer) + { + /* We have already verified that the 'samples' is a non-zero multiple of 2 in parameter checking. */ + uint32_t transfer_blocks = samples / SSI_PRV_TRANSFER_BLOCK_SIZE; + + fsp_err_t err = p_transfer->p_api->reset(p_transfer->p_ctrl, p_src, NULL, (uint16_t) transfer_blocks); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_data = NULL; + samples = 0U; + } +#endif + + p_instance_ctrl->p_tx_src = p_data; + p_instance_ctrl->tx_src_samples = samples; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the receive FIFO to be unloaded by DTC or stores the destination buffer for data to be unloaded in the + * receive interrupt. + * + * @param[in] p_instance_ctrl Pointer to the control block. + * @param[in] p_dest Pointer to the destination buffer. + * @param[in] bytes Length of destination buffer. + * + * @retval FSP_SUCCESS Receive FIFO successfully unloaded. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other + * possible return codes. This function calls: + * * @ref transfer_api_t::reset + **********************************************************************************************************************/ +fsp_err_t r_ssi_rx_unload_fifo (ssi_instance_ctrl_t * const p_instance_ctrl, void * const p_dest, uint32_t const bytes) +{ + void * p_data = p_dest; + uint32_t samples = bytes >> p_instance_ctrl->fifo_access_size; +#if SSI_CFG_DTC_ENABLE + + /* By default, bytes are written in the ISR. */ + + /* If a transfer instance is provided for reception, reset the transfer. */ + transfer_instance_t const * const p_transfer = p_instance_ctrl->p_cfg->p_transfer_rx; + if (NULL != p_transfer) + { + /* Always read at least one sample from the receive interrupt. This ensures that the DTC transfer will be over + * by the time a transmit underflow occurs during R_SSI_WriteRead processing. This is important so the receive + * buffer can be flushed in the transmit underflow error processing. Without this, the last frame (two samples) + * could be lost during R_SSI_WriteRead. */ + uint32_t transfer_blocks = (samples / SSI_PRV_TRANSFER_BLOCK_SIZE) - 1U; + if (transfer_blocks > 0) + { + fsp_err_t err = p_transfer->p_api->reset(p_transfer->p_ctrl, NULL, p_dest, (uint16_t) transfer_blocks); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + /* The last frame (2 samples) is read in the interrupt. */ + samples = 2U; + p_data = (void *) ((uint32_t) p_data + (bytes - (2U << p_instance_ctrl->fifo_access_size))); + } +#endif + + p_instance_ctrl->p_rx_dest = p_data; + p_instance_ctrl->rx_dest_samples = samples; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables SSI transmission and/or reception. + * + * @param[in] p_instance_ctrl Pointer to the control block. + * @param[in] dir Start transmit, receive, or both. + * + * @retval FSP_SUCCESS Ready for I2S transmission. + * @retval FSP_ERR_IN_USE Peripheral is in the wrong mode or not idle. + **********************************************************************************************************************/ +static fsp_err_t r_ssi_start (ssi_instance_ctrl_t * const p_instance_ctrl, ssi_dir_t dir) +{ + uint32_t ssicr = p_instance_ctrl->p_reg->SSICR; + uint32_t current_ssicr_ren_ten = ssicr & SSI_PRV_SSICR_REN_TEN_MASK; + uint32_t desired_ssicr_ren_ten = (uint32_t) dir; + + /* If the peripheral is not already in the correct mode, attempt to start it. */ + if (desired_ssicr_ren_ten != (current_ssicr_ren_ten & desired_ssicr_ren_ten)) + { + /* If the peripheral is in the wrong mode or not idle, return an error. The SSI must be idle before setting + * REN or TEN. Reference "Switching transfer modes" in the SSIE section of the relevant hardware manual. */ + FSP_ERROR_RETURN(0U == current_ssicr_ren_ten, FSP_ERR_IN_USE); + FSP_ERROR_RETURN(1U == p_instance_ctrl->p_reg->SSISR_b.IIRQ, FSP_ERR_IN_USE); + + /* Reset SSIE FIFOs. Set TFRST and RFRST, then clear them and wait for them to clear. This operation empties + * the FIFOs. */ + uint32_t ssifcr = p_instance_ctrl->p_reg->SSIFCR; + p_instance_ctrl->p_reg->SSIFCR = ssifcr | SSI_PRV_SSIFCR_TFRST_RFRST_MASK; + p_instance_ctrl->p_reg->SSIFCR = ssifcr; + + /* Wait for TFRST and RFRST to clear before continuing. Reference TFRST and RFRST in section "FIFO + * Control Register (SSIFCR)" description in the SSIE section of the relevant hardware manual. */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->SSIFCR, ssifcr); + + /* If starting transmission, enable transmit interrupts. */ + ssicr |= desired_ssicr_ren_ten; + if ((desired_ssicr_ren_ten & SSI_PRV_SSICR_TEN_BIT) > 0U) + { + /* Setting to start SSI Tx */ + ssicr |= (1U << SSI_PRV_SSICR_TUIEN_BIT); + ssifcr |= (1U << SSI_PRV_SSIFCR_TIE_BIT); + } + + /* If starting reception, enable receive interrupts. */ + if ((desired_ssicr_ren_ten & SSI_PRV_SSICR_REN_BIT) > 0U) + { + /* Setting to start SSI Rx */ + ssicr |= (1U << SSI_PRV_SSICR_ROIEN_BIT); + ssifcr |= (1U << SSI_PRV_SSIFCR_RIE_BIT); + } + + /* Enabling communication clears related error flags in SSISR. */ + p_instance_ctrl->p_reg->SSIFCR = ssifcr; + p_instance_ctrl->p_reg->SSICR = ssicr; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes data to FIFO. + * + * @param[in] p_instance_ctrl Pointer to the control block. + * + * @return The number of stages written + **********************************************************************************************************************/ +static void r_ssi_fifo_write (ssi_instance_ctrl_t * p_instance_ctrl) +{ + /* Calculate the number of words to write, limited by the space available in the FIFO. */ + uint32_t stages_to_write = p_instance_ctrl->tx_src_samples; + + /* Calculate the number of free spaces in transmit FIFO. */ + uint32_t fifo_free_stages = BSP_FEATURE_SSI_FIFO_NUM_STAGES - p_instance_ctrl->p_reg->SSIFSR_b.TDC; + if (stages_to_write > fifo_free_stages) + { + stages_to_write = fifo_free_stages; + } + + r_ssi_tx_fifo_write(p_instance_ctrl, stages_to_write); + uint32_t bytes_written = stages_to_write << p_instance_ctrl->fifo_access_size; + p_instance_ctrl->tx_src_samples -= stages_to_write; + p_instance_ctrl->p_tx_src = (void *) ((uint32_t) p_instance_ctrl->p_tx_src + bytes_written); + + /* Clear TDE only if something was written to the FIFO, otherwise the transmit interrupt will fire repeatedly. */ + if (stages_to_write > 0U) + { + /* The TDE bit must be read as 1 before it can be cleared. */ + p_instance_ctrl->p_reg->SSIFSR; + p_instance_ctrl->p_reg->SSIFSR = SSI_PRV_SSIFSR_TDE_CLEAR; + } + + /* If transmission is complete, clear transmit buffer to NULL. */ + if (0U == p_instance_ctrl->tx_src_samples) + { + p_instance_ctrl->p_tx_src = NULL; + } +} + +/*******************************************************************************************************************//** + * Reads data from FIFO. + * + * @param[in] p_instance_ctrl Pointer to the control block. + **********************************************************************************************************************/ +static void r_ssi_fifo_read (ssi_instance_ctrl_t * p_instance_ctrl) +{ + /* Calculate the number of available bytes of data in receive FIFO. */ + uint32_t fifo_filled_stages = p_instance_ctrl->p_reg->SSIFSR_b.RDC; + + /* Calculate the number of FIFO stages requested to read. */ + uint32_t stages_to_read = 0U; + stages_to_read = p_instance_ctrl->rx_dest_samples; + if (stages_to_read > fifo_filled_stages) + { + stages_to_read = fifo_filled_stages; + } + + r_ssi_rx_fifo_read(p_instance_ctrl, stages_to_read); + uint32_t bytes_read = stages_to_read << p_instance_ctrl->fifo_access_size; + p_instance_ctrl->rx_dest_samples -= stages_to_read; + p_instance_ctrl->p_rx_dest = (void *) ((uint32_t) p_instance_ctrl->p_rx_dest + bytes_read); + + /* Clear RDF only if something was written to the FIFO, otherwise the receive interrupt will fire repeatedly. */ + if (stages_to_read > 0) + { + p_instance_ctrl->p_reg->SSIFSR; + p_instance_ctrl->p_reg->SSIFSR = SSI_PRV_SSIFSR_RDF_CLEAR; + } + + /* If reception is complete, clear receive buffer to NULL. */ + if (0U == p_instance_ctrl->rx_dest_samples) + { + p_instance_ctrl->p_rx_dest = NULL; + } +} + +/*******************************************************************************************************************//** + * Writes data to the transmit FIFO based on the FIFO access size. + * + * @param[in] p_instance_ctrl Pointer to the control block. + * @param[in] stages_to_write Number of times to write to the FIFO. + **********************************************************************************************************************/ +static void r_ssi_tx_fifo_write (ssi_instance_ctrl_t * p_instance_ctrl, uint32_t stages_to_write) +{ + if (TRANSFER_SIZE_4_BYTE == p_instance_ctrl->fifo_access_size) + { + uint32_t * p_src32 = (uint32_t *) p_instance_ctrl->p_tx_src; + for (uint32_t i = 0; i < stages_to_write; i++) + { + p_instance_ctrl->p_reg->SSIFTDR = *p_src32; + p_src32++; + } + } + + if (TRANSFER_SIZE_2_BYTE == p_instance_ctrl->fifo_access_size) + { + uint16_t * p_src16 = (uint16_t *) p_instance_ctrl->p_tx_src; + for (uint32_t i = 0; i < stages_to_write; i++) + { + p_instance_ctrl->p_reg->SSIFTDR16 = *p_src16; + p_src16++; + } + } + + if (TRANSFER_SIZE_1_BYTE == p_instance_ctrl->fifo_access_size) + { + uint8_t * p_src8 = (uint8_t *) p_instance_ctrl->p_tx_src; + for (uint32_t i = 0; i < stages_to_write; i++) + { + p_instance_ctrl->p_reg->SSIFTDR8 = *p_src8; + p_src8++; + } + } +} + +/*******************************************************************************************************************//** + * Reads data from the receive FIFO based on the FIFO access size. + * + * @param[in] p_instance_ctrl Pointer to the control block. + * @param[in] stages_to_read Number of times to read from the FIFO. + **********************************************************************************************************************/ +static void r_ssi_rx_fifo_read (ssi_instance_ctrl_t * p_instance_ctrl, uint32_t stages_to_read) +{ + if (TRANSFER_SIZE_4_BYTE == p_instance_ctrl->fifo_access_size) + { + uint32_t * p_dest32 = (uint32_t *) p_instance_ctrl->p_rx_dest; + for (uint32_t i = 0; i < stages_to_read; i++) + { + *p_dest32 = p_instance_ctrl->p_reg->SSIFRDR; + p_dest32++; + } + } + + if (TRANSFER_SIZE_2_BYTE == p_instance_ctrl->fifo_access_size) + { + uint16_t * p_dest16 = (uint16_t *) p_instance_ctrl->p_rx_dest; + for (uint32_t i = 0; i < stages_to_read; i++) + { + *p_dest16 = p_instance_ctrl->p_reg->SSIFRDR16; + p_dest16++; + } + } + + if (TRANSFER_SIZE_1_BYTE == p_instance_ctrl->fifo_access_size) + { + uint8_t * p_dest8 = (uint8_t *) p_instance_ctrl->p_rx_dest; + for (uint32_t i = 0; i < stages_to_read; i++) + { + *p_dest8 = p_instance_ctrl->p_reg->SSIFRDR8; + p_dest8++; + } + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to I2S instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_ssi_call_callback (ssi_instance_ctrl_t * p_ctrl, i2s_event_t event) +{ + i2s_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2s_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + i2s_prv_ns_callback p_callback = (i2s_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * Transmit ISR. Calls callback when transmission is complete. Fills FIFO if transfer interface is not used. + **********************************************************************************************************************/ +void ssi_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + if (NULL != p_instance_ctrl->p_tx_src) + { + /* If transfer is not used, write data. */ + r_ssi_fifo_write(p_instance_ctrl); + } + + /* If there are more samples to write to the FIFO or the FIFO is above the watermark, don't call the callback. */ + if ((p_instance_ctrl->tx_src_samples == 0) && + (p_instance_ctrl->p_reg->SSIFSR_b.TDC > (BSP_FEATURE_SSI_FIFO_NUM_STAGES / 2U))) + { + r_ssi_call_callback(p_instance_ctrl, I2S_EVENT_TX_EMPTY); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Receive ISR. Calls callback when reception is complete. Empties FIFO if transfer interface is not used. + **********************************************************************************************************************/ +void ssi_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + bool call_callback = true; + + if (NULL != p_instance_ctrl->p_rx_dest) + { + /* If transfer is not used, read data into the destination buffer. */ + r_ssi_fifo_read(p_instance_ctrl); + + /* If there is more space in the buffer, don't call the callback. */ + if (p_instance_ctrl->rx_dest_samples > 0U) + { + call_callback = false; + } + } + + if (call_callback) + { + r_ssi_call_callback(p_instance_ctrl, I2S_EVENT_RX_FULL); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Error and idle ISR. + * + * Handles transmit underflow errors and calls callback when idle interrupt occurs. + **********************************************************************************************************************/ +void ssi_int_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + ssi_instance_ctrl_t * p_instance_ctrl = (ssi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Events that are being serviced are being cleared. During this time if another error occurs then this + * interrupt will fire again */ + + /* Clear all flags in SSISR. These bits can only be cleared after reading them as 1. See + * "Status Register (SSISR)" description in the SSIE section of the relevant hardware manual. */ + uint32_t iirq_flag = p_instance_ctrl->p_reg->SSISR_b.IIRQ; + p_instance_ctrl->p_reg->SSISR = 0U; + + if (1U == iirq_flag) + { + /* Disable idle interrupt. */ + p_instance_ctrl->p_reg->SSICR_b.IIEN = 0U; + + /* If peripheral is idle, call idle callback. */ + r_ssi_call_callback(p_instance_ctrl, I2S_EVENT_IDLE); + } + else + { + if (NULL != p_instance_ctrl->p_rx_dest) + { + /* If there's more data to read, flush read data into the destination buffer. */ + r_ssi_fifo_read(p_instance_ctrl); + } + + /* SSIE must go idle after a transmit or receive error. See "When an error interrupt + * is generated" in the SSIE section of the relevant hardware manual. */ + r_ssi_stop_sub(p_instance_ctrl); + } + + /* Clear the IR flag in the ICU */ + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tau/r_tau.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tau/r_tau.c new file mode 100644 index 0000000000..15d2409c8f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tau/r_tau.c @@ -0,0 +1,1386 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_tau.h" +#include "r_tau_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "TAU" in ASCII, used to determine if channel is open. */ +#define TAU_OPEN (0x00544155ULL) +#define TAU_CLOSE (0U) + +/* TAU Channel */ +#define TAU_CH0 (0) +#define TAU_CH1 (1) +#define TAU_CH3 (3) +#define TAU_CH5 (5) +#define TAU_CH7 (7) + +/* Delay cycles */ +#define TAU_DELAY_2_CYCLE_FMCK (2U) + +/* Shift to higher 8-bit mode channels */ +#define TAU_BIT_MODE_HIGHER_8BIT_SHIFT (8U) + +/* Mask 9 bit for lower mode timer 8-bit */ +#define TAU_8BIT_MODE_MASK (0x00FFU) + +/* Mask 9 bit for higher mode timer 8-bit */ +#define TAU_BIT_MODE_HIGHER_8BIT_MASK (0xFF00U) + +/* These bitfield defines indicate which channels support a certain function */ +#define TAU_DIVIDER_MODE_CAPABLE_CHANNEL_MASK (1 << TAU_CH0) +#define TAU_8BIT_MODE_SUPPORT_CAPABLE_CHANNEL_MASK ((1 << TAU_CH1) | (1 << TAU_CH3)) +#define TAU_CK02_CK03_CAPABLE_CHANNELS_MASK ((1 << TAU_CH1) | (1 << TAU_CH3)) +#define TAU_INPUT_RXD_CAPABLE_CHANNEL_MASK (1 << TAU_CH7) +#define TAU_INPUT_CLOCK_CAPABLE_CHANNEL_MASK (1 << TAU_CH5) +#if BSP_FEATURE_ELC_VERSION + #define TAU_ELC_CAPABLE_CHANNELS_MASK ((1 << TAU_CH0) | (1 << TAU_CH1)) +#endif + +/* These bit fields are for the TS0 and TT0 registers. */ +#define TAU_TS0_TT0_16BIT_MODE_MASK (0x0001) +#define TAU_TS0_TT0_HIGHER_8BIT_MODE_MASK (0x0100) +#define TAU_TS0_TT0_LOWER_8BIT_MODE_MASK (0x0001) +#define TAU_TS0_TT0_HIGHER_LOWER_8BIT_MODE_MASK (0x0101) + +/* Setting low level measurement and high level measurement */ +#define TAU_INPUT_LOW_LEVEL_MEASUREMENT_SETTING (0x02) +#define TAU_INPUT_HIGH_LEVEL_MEASUREMENT_SETTING (0x03) + +/* Used for checking maximum period count in 16-bit mode (1 to 65536) */ +#define TAU_MAXIMUM_16BIT_TIMER_MODE (65536) + +/* Used for checking maximum period count in 8-bit mode (1 to 256) */ +#define TAU_MAXIMUM_8BIT_TIMER_MODE (256) + +/* Used for checking maximum divider value with both edge (1 to 65536) */ +#define TAU_MAXIMUM_BOTH_EDGE_DIVIDER_FUNCTION (65536) + +/* Used for checking maximum divider value with falling or rising edge (2 to 131072) */ +#define TAU_MAXIMUM_FALLING_RISING_EDGE_DIVIDER_FUNCTION (131072) + +/* Bitmask to convert TAU function into count direction */ +#define TAU_PRV_COUNT_DIRECTION_MASK (0x70U) + +/* Operation clock CK00, CK01 Mask */ +#define TAU_OPERATION_CLOCK_CK00_CK01_MASK (0x0FU) + +/* Operation clock CK02, CK03 Mask */ +#define TAU_OPERATION_CLOCK_CK02_CK03_MASK (0x03U) + +/* The number of available functions. */ +#define TAU_FUNCTIONS_COUNT (8) + +#define TAU_TDR_WRITE_MSK_BY_TIMER_MODE (0x8FU) +#define TAU_SUPPORT_8BIT_MSK_BY_TIMER_MODE (0x87U) + +/* Use for functions which support output pin */ +#define TAU_FUNCTION_SUPPORTED_OUTPUT_MASK (0x0AU) + +/* Use for functions which support input pin */ +#define TAU_FUNCTION_SUPPORTED_INPUT_MASK (0xFCU) + +/* Shifted mask for TPS0.PRS2 and .PRS3 bitfields */ +#define TAU_PRV_PRS2_PRS3_MASK (0x3U) + +/* Divisor settings for CK02 and CK03 */ +#define TAU_PRV_TPS0_PRS3_SETTING ((BSP_CFG_TAU_CK03 >> 1) & TAU_PRV_PRS2_PRS3_MASK) +#define TAU_PRV_TPS0_PRS2_SETTING ((BSP_CFG_TAU_CK02 >> 1) & TAU_PRV_PRS2_PRS3_MASK) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Timer Mode */ +typedef enum e_tau_timer_mode +{ + TAU_TIMER_MODE_INTERVAL = 0, ///< Interval timer mode + TAU_TIMER_MODE_CAPTURE = 2, ///< Capture timer mode + TAU_TIMER_MODE_EVENT_COUNTER = 3, ///< Event counter timer mode + TAU_TIMER_MODE_ONE_COUNT = 4, ///< One count timer mode + TAU_TIMER_MODE_CAPTURE_AND_ONE_COUNT = 6, ///< Capture and one-count mode +} tau_timer_mode_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static fsp_err_t r_tau_config_set(tau_instance_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +static fsp_err_t r_tau_cnt_set(timer_cfg_t const * const p_cfg, uint32_t period_counts, uint32_t period_8bit_counts); + +#if TAU_CFG_INPUT_SUPPORT_ENABLE +static void r_tau_config_input_set(tau_instance_ctrl_t * const p_ctrl); + +#endif + +#if TAU_CFG_OUTPUT_SUPPORT_ENABLE +static void r_tau_config_output_set(tau_instance_ctrl_t * const p_ctrl); + +#endif + +#if TAU_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_tau_open_param_checking(tau_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg); +static fsp_err_t r_tau_cnt_check(timer_cfg_t const * const p_cfg, uint32_t period_counts, uint32_t period_8bit_counts); + +#endif + +#if TAU_CFG_INTERRUPT_SUPPORT_ENABLE +static void r_tau_disable_irq(IRQn_Type irq); +static void r_tau_enable_irq(IRQn_Type const irq, uint32_t priority, void * p_context); + +static void tau_generic_isr(timer_event_t event); + +#endif + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +#if TAU_CFG_INTERRUPT_SUPPORT_ENABLE +void tau_tmi_isr(void); +void tau_tmih_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* Look-up table for mapping timer function and timer mode, index to this table is defined + * by the tau_function_t enum */ +static const uint16_t tau_func_setting_lut[TAU_FUNCTIONS_COUNT] = +{ + /* This setting supports to interval timer function */ + [TAU_FUNCTION_INTERVAL] = + (TAU_TIMER_MODE_INTERVAL << R_TAU_TMR0_MD_Pos) | ///< Setting interval timer mode. + (0 << R_TAU_TMR0_STS_Pos) | ///< Only software start. + (0 << R_TAU_TMR0_CCS_Pos), ///< Operation clock (fMCK). + + /* This setting supports to square wave output function */ + [TAU_FUNCTION_SQUARE_WAVE] = + (TAU_TIMER_MODE_INTERVAL << R_TAU_TMR0_MD_Pos) | ///< Setting interval timer mode. + (0 << R_TAU_TMR0_STS_Pos) | ///< Only software start. + (0 << R_TAU_TMR0_CCS_Pos), ///< Operation clock (fMCK). + + /* This setting supports to external event count function */ + [TAU_FUNCTION_EXTERNAL_EVENT_COUNT] = + (TAU_TIMER_MODE_EVENT_COUNTER << R_TAU_TMR0_MD_Pos) | ///< Setting event count mode. + (0 << R_TAU_TMR0_STS_Pos) | ///< Only software start. + (1 << R_TAU_TMR0_CCS_Pos), ///< The TI0n pin input valid edge. + + /* This setting supports to divider function */ + [TAU_FUNCTION_DIVIDER] = + (TAU_TIMER_MODE_INTERVAL << R_TAU_TMR0_MD_Pos) | ///< Setting interval timer mode. + (0 << R_TAU_TMR0_STS_Pos) | ///< Only software start. + (1 << R_TAU_TMR0_CCS_Pos), ///< The TI0n pin input valid edge. + + /* This setting supports to input pulse measurement function */ + [TAU_FUNCTION_INPUT_PULSE_INTERVAL_MEASUREMENT] = + (TAU_TIMER_MODE_CAPTURE << R_TAU_TMR0_MD_Pos) | ///< Setting capture mode. + (1 << R_TAU_TMR0_STS_Pos) | ///< The TI0n pin input valid edge. + (0 << R_TAU_TMR0_CCS_Pos), ///< Operation clock (fMCK). + + /* This setting supports to low level width measurement function */ + [TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT] = + (TAU_TIMER_MODE_CAPTURE_AND_ONE_COUNT << R_TAU_TMR0_MD_Pos) | ///< Setting capture & one-count mode. + (2 << R_TAU_TMR0_STS_Pos) | ///< The TI0n pin input valid edges. + (0 << R_TAU_TMR0_CCS_Pos), ///< Operation clock (fMCK). + + /* This setting supports to high level width measurement function */ + [TAU_FUNCTION_HIGH_LEVEL_WIDTH_MEASUREMENT] = + (TAU_TIMER_MODE_CAPTURE_AND_ONE_COUNT << R_TAU_TMR0_MD_Pos) | ///< Setting capture & one-count mode. + (2 << R_TAU_TMR0_STS_Pos) | ///< The TI0n pin input valid edges. + (0 << R_TAU_TMR0_CCS_Pos), ///< Operation clock (fMCK). + + /* This setting supports to delay count function */ + [TAU_FUNCTION_DELAY_COUNT] = + (TAU_TIMER_MODE_ONE_COUNT << R_TAU_TMR0_MD_Pos) | ///< Setting one-count mode. + (1 << R_TAU_TMR0_STS_Pos) | ///< The TI0n pin input valid edge. + (0 << R_TAU_TMR0_CCS_Pos) ///< Operation clock (fMCK). +}; + +/* TAU implementation of timer interface */ +const timer_api_t g_timer_on_tau = +{ + .open = R_TAU_Open, + .stop = R_TAU_Stop, + .start = R_TAU_Start, + .reset = R_TAU_Reset, + .enable = R_TAU_Enable, + .disable = R_TAU_Disable, + .periodSet = R_TAU_PeriodSet, + .compareMatchSet = R_TAU_CompareMatchSet, + .dutyCycleSet = R_TAU_DutyCycleSet, + .infoGet = R_TAU_InfoGet, + .statusGet = R_TAU_StatusGet, + .callbackSet = R_TAU_CallbackSet, + .close = R_TAU_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup TAU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open. + * + * The TAU implementation of the general timer can accept a tau_extended_cfg_t extension parameter. + * + * Example: + * @snippet r_tau_example.c R_TAU_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the period is not in the valid range + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_INVALID_CHANNEL The channel does not support this feature. + * @retval FSP_ERR_IRQ_BSP_DISABLED Timer_cfg_t::p_callback is not NULL, but ISR is not enabled. + * ISR must be enabled to use callback + * @retval FSP_ERR_INVALID_MODE Invalid configuration for p_extend. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + * @retval FSP_ERR_UNSUPPORTED Input source is not supported. + **********************************************************************************************************************/ +fsp_err_t R_TAU_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_instance_ctrl); +#endif + + uint32_t channel = p_cfg->channel; + p_instance_ctrl->channel_mask = (uint16_t) (1U << channel); + +#if TAU_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_tau_open_param_checking(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + + /* Enable the TAU channel and reset the registers to their initial state. */ + R_BSP_MODULE_START(FSP_IP_TAU, channel); + + /* Set the TAU configuration settings provided in ::tau_cfg_t and :: tau_extended_cfg_t. */ +#if TAU_CFG_PARAM_CHECKING_ENABLE + err = r_tau_config_set(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#else + r_tau_config_set(p_instance_ctrl, p_cfg); +#endif + +#if TAU_CFG_8BIT_MODE_SUPPORT_ENABLE + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_cfg->p_extend; + tau_bit_mode_t bit_mode = p_extend->bit_mode; + p_instance_ctrl->channel_bitmode_mask = (uint16_t) (((bit_mode != TAU_BIT_MODE_HIGHER_8BIT) | + ((bit_mode & TAU_BIT_MODE_HIGHER_8BIT) << 8)) << channel); +#else + p_instance_ctrl->channel_bitmode_mask = (uint16_t) (1U << channel); +#endif + +#if TAU_CFG_INTERRUPT_SUPPORT_ENABLE + r_tau_enable_irq(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + #if TAU_CFG_8BIT_MODE_SUPPORT_ENABLE + r_tau_enable_irq(p_extend->higher_8bit_cycle_end_irq, p_extend->higher_8bit_cycle_end_ipl, p_instance_ctrl); + #endif +#endif + +#if TAU_CFG_PARAM_CHECKING_ENABLE + p_instance_ctrl->open = TAU_OPEN; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops timer. Implements @ref timer_api_t::stop. + * + * Example: + * @snippet r_tau_example.c R_TAU_Stop + * + * @retval FSP_SUCCESS Timer successfully stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_Stop (timer_ctrl_t * const p_ctrl) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + R_TAU->TT0 = p_instance_ctrl->channel_bitmode_mask; + +#if TAU_CFG_OUTPUT_SUPPORT_ENABLE + timer_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_cfg->p_extend; + + if (TAU_PIN_OUTPUT_CFG_DISABLED != p_extend->initial_output) + { + R_TAU->TOE0 &= (uint16_t) (~(p_instance_ctrl->channel_mask)); + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts timer. Implements @ref timer_api_t::start. + * + * Example: + * @snippet r_tau_example.c R_TAU_Start + * + * @retval FSP_SUCCESS Timer successfully started. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_Start (timer_ctrl_t * const p_ctrl) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if TAU_CFG_OUTPUT_SUPPORT_ENABLE + timer_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_cfg->p_extend; + + if (TAU_PIN_OUTPUT_CFG_DISABLED != p_extend->initial_output) + { + R_TAU->TOE0 |= p_instance_ctrl->channel_mask; + } +#endif + + /* Start timer */ + R_TAU->TS0 = p_instance_ctrl->channel_bitmode_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter value to the period minus one. Input Pulse Function is reset counter value to 0. + * Implements @ref timer_api_t::reset. + * + * @note This function can not reset the counter when counter is stopped, + * and function High/Low Measurement Function is used. + * + * @retval FSP_SUCCESS The counter value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_Reset (timer_ctrl_t * const p_ctrl) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint16_t timer_channel = p_instance_ctrl->channel_bitmode_mask; + + if (timer_channel & R_TAU->TE0) + { + /* Stop counting. */ + R_TAU->TT0 = timer_channel; + + /* Start counting again. */ + R_TAU->TS0 = timer_channel; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable. + * + * Example: + * @snippet r_tau_example.c R_TAU_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_Enable (timer_ctrl_t * const p_ctrl) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Start counting. */ + R_TAU->TS0 = p_instance_ctrl->channel_bitmode_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables external event triggers that start, stop, clear, or capture the counter. + * Implements @ref timer_api_t::disable. + * @note The timer could be running after R_TAU_Disable(). To ensure it is stopped, call R_TAU_Stop(). + * + * Example: + * @snippet r_tau_example.c R_TAU_Disable + * + * @retval FSP_SUCCESS External events successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_Disable (timer_ctrl_t * const p_ctrl) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Stop counting. */ + R_TAU->TT0 = p_instance_ctrl->channel_bitmode_mask; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets period value provided. If the timer is running, the period will be updated after the next counter underflow. + * If the timer is stopped, this function resets the counter and updates the period. + * This Function is not supported for Input pulse Function, High-Low Measurement Function. + * Implements @ref timer_api_t::periodSet. + * + * @note if timer mode is Lower and Higher 8-bit Timer Mode, the last 8 bits are the lower 8-bits of the timer, + * and the subsequent 8 bits are the higher 8-bits of the timer + * + * Example: + * @snippet r_tau_example.c R_TAU_PeriodSet + * + * @retval FSP_SUCCESS Period value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL or period is invalid range. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_UNSUPPORTED Unsupported for Input pulse Function, High-Low Measurement Function + **********************************************************************************************************************/ +fsp_err_t R_TAU_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if TAU_CFG_PARAM_CHECKING_ENABLE || TAU_CFG_8BIT_MODE_SUPPORT_ENABLE + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; +#endif + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN((1U << p_extend->tau_func) & TAU_TDR_WRITE_MSK_BY_TIMER_MODE, FSP_ERR_UNSUPPORTED); +#endif + + uint32_t period = period_counts; + +#if TAU_CFG_8BIT_MODE_SUPPORT_ENABLE + uint32_t period_higher = period_counts; + + if (TAU_BIT_MODE_HIGHER_LOWER_8BIT == p_extend->bit_mode) + { + uint32_t tdr = period_counts - 1; + period = (uint32_t) ((tdr & TAU_8BIT_MODE_MASK) + 1); + period_higher = (uint32_t) + (((tdr >> TAU_BIT_MODE_HIGHER_8BIT_SHIFT) & TAU_8BIT_MODE_MASK) + 1); + } + + #if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(FSP_SUCCESS == r_tau_cnt_set(p_instance_ctrl->p_cfg, period, period_higher)); + #else + r_tau_cnt_set(p_instance_ctrl->p_cfg, period, period_higher); + #endif +#else + #if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(FSP_SUCCESS == r_tau_cnt_set(p_instance_ctrl->p_cfg, period, 0)); + #else + r_tau_cnt_set(p_instance_ctrl->p_cfg, period, 0); + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported compareMatch function. Implements @ref timer_api_t::compareMatchSet. + * + * @retval FSP_ERR_UNSUPPORTED TAU compare match is not supported. + **********************************************************************************************************************/ +fsp_err_t R_TAU_CompareMatchSet (timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel) +{ + /* This function isn't supported. It is defined only to implement a required function of timer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(compare_match_value); + FSP_PARAMETER_NOT_USED(match_channel); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @ref timer_api_t::dutyCycleSet is not supported on the R_TAU Independent channels. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_TAU_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(duty_cycle_counts); + FSP_PARAMETER_NOT_USED(pin); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * Get timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_tau_example.c R_TAU_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, frequency, and ELC event written to caller's + * structure successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_info was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint8_t specific_divider; + timer_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + + /* Get and store period */ + p_info->period_counts = (uint32_t) (R_TAU->TDR0[p_cfg->channel].TDR0n) + 1; + + /* Get and store clock counting direction. Read count direction setting */ + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_cfg->p_extend; + p_info->count_direction = (timer_direction_t) ((TAU_PRV_COUNT_DIRECTION_MASK >> p_extend->tau_func) & 1U); + + /* Get and store clock frequency */ + switch (p_extend->operation_clock) + { + case TAU_OPERATION_CK01: + { + specific_divider = BSP_CFG_TAU_CK01; + break; + } + + case TAU_OPERATION_CK02: + { + specific_divider = BSP_CFG_TAU_CK02; + break; + } + + case TAU_OPERATION_CK03: + { + specific_divider = BSP_CFG_TAU_CK03; + break; + } + + case TAU_OPERATION_CK00: + default: + { + specific_divider = BSP_CFG_TAU_CK00; + break; + } + } + + p_info->clock_frequency = SystemCoreClock >> specific_divider; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get current timer status and store it in provided pointer p_status. Implements @ref timer_api_t::statusGet. + * + * Example: + * @snippet r_tau_example.c R_TAU_StatusGet + * + * @retval FSP_SUCCESS Current timer state and counter value set successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_status->state = + (p_instance_ctrl->channel_bitmode_mask & R_TAU->TE0) ? TIMER_STATE_COUNTING : TIMER_STATE_STOPPED; + p_status->counter = R_TAU->TCR0[p_instance_ctrl->p_cfg->channel]; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + FSP_PARAMETER_NOT_USED(p_callback_memory); + +#if TAU_CFG_INTERRUPT_SUPPORT_ENABLE + tau_instance_ctrl_t * p_ctrl = (tau_instance_ctrl_t *) p_api_ctrl; + + #if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(TAU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_context); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_Close (timer_ctrl_t * const p_ctrl) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Mark driver as closed */ + p_instance_ctrl->open = TAU_CLOSE; +#endif + + /* Stop timer */ + R_TAU->TT0 = p_instance_ctrl->channel_bitmode_mask; + +#if TAU_CFG_OUTPUT_SUPPORT_ENABLE || (TAU_CFG_8BIT_MODE_SUPPORT_ENABLE && TAU_CFG_INTERRUPT_SUPPORT_ENABLE) + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; +#endif + +#if TAU_CFG_OUTPUT_SUPPORT_ENABLE + if (TAU_PIN_OUTPUT_CFG_DISABLED != p_extend->initial_output) + { + /* Disable timer output */ + R_TAU->TOE0 &= (uint16_t) (~(p_instance_ctrl->channel_mask)); + } +#endif + + /* Disable interrupts */ +#if TAU_CFG_INTERRUPT_SUPPORT_ENABLE + r_tau_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq); + #if TAU_CFG_8BIT_MODE_SUPPORT_ENABLE + r_tau_disable_irq(p_extend->higher_8bit_cycle_end_irq); + #endif +#endif + + /* Return the error code */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function is provided for the SAU LIN driver to support switching between low level measurement and input pulse + * measurement functions during LIN reception. + * It is not intended to be called directly by application code. + * + * @param[in] p_ctrl Pointer to TAU control structure + * @param[in] func Measurement functions (TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT, + * TAU_FUNCTION_INPUT_PULSE_INTERVAL_MEASUREMENT) + * + * @retval FSP_SUCCESS Switching was successful and measurement has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid input function. + **********************************************************************************************************************/ +fsp_err_t R_TAU_LinMeasurementFuncSwitch (timer_ctrl_t * const p_ctrl, tau_function_t func) +{ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) p_ctrl; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + FSP_ERROR_RETURN((TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT == func) || + (TAU_FUNCTION_INPUT_PULSE_INTERVAL_MEASUREMENT == func), + FSP_ERR_INVALID_ARGUMENT); +#endif + + timer_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + + /* Stop counting */ + R_TAU->TT0 = p_instance_ctrl->channel_bitmode_mask; + + r_tau_disable_irq(p_cfg->cycle_end_irq); + + uint32_t channel = p_cfg->channel; + + /* Keep the current value of OPIRQ and CKS register bit */ + uint32_t tmr = (R_TAU->TMR0[channel] & (R_TAU_TMR0_OPIRQ_Msk | R_TAU_TMR0_CKS_Msk)); + + /* Switch mode */ + tmr |= tau_func_setting_lut[func]; + + /* Setting trigger edge */ + uint32_t tmr_cis = (func == TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT) ? + TAU_INPUT_LOW_LEVEL_MEASUREMENT_SETTING : + TAU_TRIGGER_EDGE_FALLING; + + tmr |= tmr_cis << R_TAU_TMR0_CIS_Pos; + + /* Setting TMR0 register */ + R_TAU->TMR0[channel] = (uint16_t) tmr; + + r_tau_enable_irq(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + + /* Start counting again */ + R_TAU->TS0 = p_instance_ctrl->channel_bitmode_mask; + + return FSP_SUCCESS; +} + +/** @} (end addtogroup TAU) */ + +#if TAU_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking for R_TAU_Open. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * @param[in] p_cfg Configuration structure for this instance + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ALREADY_OPEN R_TAU_Open has already been called for this p_ctrl. + * @retval FSP_ERR_INVALID_CHANNEL The channel does not support this feature. + * @retval FSP_ERR_INVALID_MODE Invalid configuration for p_extend. + * @retval FSP_ERR_IRQ_BSP_DISABLED Timer_cfg_t::p_callback is not NULL, but ISR is not enabled. + * ISR must be enabled to use callback + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel number is not available on TAU. + * @retval FSP_ERR_UNSUPPORTED The selected input source is not supported on this MCU. + **********************************************************************************************************************/ +static fsp_err_t r_tau_open_param_checking (tau_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_cfg->p_extend; + + FSP_ERROR_RETURN(TAU_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Enable IRQ if user supplied a callback function */ + if (NULL != p_cfg->p_callback) + { + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0 || + (TAU_BIT_MODE_HIGHER_8BIT == p_extend->bit_mode), + FSP_ERR_IRQ_BSP_DISABLED); + + FSP_ERROR_RETURN(p_extend->higher_8bit_cycle_end_irq >= 0 || + (TAU_BIT_MODE_16BIT == p_extend->bit_mode) || + ((TAU_BIT_MODE_LOWER_8BIT == p_extend->bit_mode)), + FSP_ERR_IRQ_BSP_DISABLED); + } + + FSP_ERROR_RETURN((p_instance_ctrl->channel_mask & BSP_FEATURE_TAU_VALID_CHANNEL_MASK), + FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Divider Function is only available in channel 0 */ + FSP_ERROR_RETURN((TAU_FUNCTION_DIVIDER != p_extend->tau_func) || + (p_instance_ctrl->channel_mask & TAU_DIVIDER_MODE_CAPABLE_CHANNEL_MASK), + FSP_ERR_INVALID_CHANNEL); + + /* Higher 8-bit timer, lower 8-bit timer, Higher and lower 8-bit timer are available in channel 1 and 3 */ + FSP_ERROR_RETURN((TAU_BIT_MODE_16BIT == p_extend->bit_mode) || + (p_instance_ctrl->channel_mask & TAU_8BIT_MODE_SUPPORT_CAPABLE_CHANNEL_MASK), + FSP_ERR_INVALID_CHANNEL); + + if ((TAU_OPERATION_CK02 == p_extend->operation_clock) || (TAU_OPERATION_CK03 == p_extend->operation_clock)) + { + /* CK02, CK03 are only available in channels 1 and 3 */ + FSP_ERROR_RETURN(p_instance_ctrl->channel_mask & TAU_CK02_CK03_CAPABLE_CHANNELS_MASK, FSP_ERR_INVALID_CHANNEL); + } + else + { + /* Higher 8-bit timer, lower 8-bit timer, Higher and lower 8-bit timer are available when + * the "Operation Clock" is set to CK02 or CK03 */ + FSP_ERROR_RETURN(TAU_BIT_MODE_16BIT == p_extend->bit_mode, FSP_ERR_INVALID_MODE); + } + + #if TAU_CFG_INPUT_SUPPORT_ENABLE + if ((1 << p_extend->tau_func) & TAU_FUNCTION_SUPPORTED_INPUT_MASK) + { + /* Input source is different to No input signal When this function used input pin */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_NONE != p_extend->input_source), FSP_ERR_INVALID_MODE) + + /* Input signal of RXD is only available in channels 7 */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_RXD_PIN != p_extend->input_source) || + (p_instance_ctrl->channel_mask & TAU_INPUT_RXD_CAPABLE_CHANNEL_MASK), + FSP_ERR_INVALID_CHANNEL); + + /* Input signal of the RXD pin is only available in Input Pulse and + * High-Low Level Pulse Width Measure Function */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_RXD_PIN != p_extend->input_source) || + (TAU_FUNCTION_INPUT_PULSE_INTERVAL_MEASUREMENT == p_extend->tau_func) || + (TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT == p_extend->tau_func) || + (TAU_FUNCTION_HIGH_LEVEL_WIDTH_MEASUREMENT == p_extend->tau_func), + FSP_ERR_INVALID_MODE); + #if !BSP_FEATURE_CGC_HAS_MOCO + + /* MOCO input source is not supported */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_MOCO != p_extend->input_source), FSP_ERR_UNSUPPORTED); + #endif + #if !BSP_FEATURE_CGC_HAS_SOSC + + /* FSUB input source is not supported */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_FSUB != p_extend->input_source), FSP_ERR_UNSUPPORTED); + #endif + + /* Input signal of MOCO, LOCO, FSUB are only available in channels 5 */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_MOCO > p_extend->input_source) || + (TAU_INPUT_SOURCE_FSUB < p_extend->input_source) || + (p_instance_ctrl->channel_mask & TAU_INPUT_CLOCK_CAPABLE_CHANNEL_MASK), + FSP_ERR_INVALID_CHANNEL); + #if BSP_FEATURE_ELC_VERSION + + /* ELC input source is only available in channels 0 and 1 */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_ELC != p_extend->input_source) || + (p_instance_ctrl->channel_mask & TAU_ELC_CAPABLE_CHANNELS_MASK), + FSP_ERR_INVALID_CHANNEL); + + /* The noise filter should be disabled when ELC signal is selected as an input signal */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_ELC != p_extend->input_source) || + (TAU_INPUT_NOISE_FILTER_DISABLE == p_extend->tau_filter), + FSP_ERR_INVALID_MODE); + + /* ELC input source is only available External Event Counter, Input Pulse, and Delay Counter Function */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_ELC != p_extend->input_source) || + (TAU_FUNCTION_EXTERNAL_EVENT_COUNT == p_extend->tau_func) || + (TAU_FUNCTION_INPUT_PULSE_INTERVAL_MEASUREMENT == p_extend->tau_func) || + (TAU_FUNCTION_DELAY_COUNT == p_extend->tau_func), + FSP_ERR_INVALID_MODE); + #else + + /* ELC input source is not supported */ + FSP_ERROR_RETURN((TAU_INPUT_SOURCE_ELC != p_extend->input_source), FSP_ERR_UNSUPPORTED); + #endif + } + #endif + + #if TAU_CFG_OUTPUT_SUPPORT_ENABLE + if ((1 << p_extend->tau_func) & TAU_FUNCTION_SUPPORTED_OUTPUT_MASK) + { + /* Initial Output should not be disabled when function uses output pin */ + FSP_ERROR_RETURN(TAU_PIN_OUTPUT_CFG_DISABLED != p_extend->initial_output, FSP_ERR_INVALID_MODE); + } + #endif + + if ((1U << p_extend->tau_func) & TAU_SUPPORT_8BIT_MSK_BY_TIMER_MODE) + { + /* Higher-Lower 8 and higher 8-bit timer are available in Interval Timer function */ + FSP_ERROR_RETURN(((TAU_BIT_MODE_HIGHER_LOWER_8BIT != p_extend->bit_mode) && + (TAU_BIT_MODE_HIGHER_8BIT != p_extend->bit_mode)) || + (TAU_FUNCTION_INTERVAL == p_extend->tau_func), + FSP_ERR_INVALID_MODE); + } + else + { + /* This function is not supported for 8-bit mode */ + FSP_ERROR_RETURN(TAU_BIT_MODE_16BIT == p_extend->bit_mode, FSP_ERR_INVALID_MODE); + } + + tau_timer_mode_t mode_timer = + (tau_timer_mode_t) ((tau_func_setting_lut[p_extend->tau_func] & R_TAU_TMR0_MD_Msk) >> R_TAU_TMR0_MD_Pos); + + if ((TAU_TIMER_MODE_CAPTURE_AND_ONE_COUNT == mode_timer) || (TAU_TIMER_MODE_EVENT_COUNTER == mode_timer)) + { + /* Bit opirq should be 0 when Event counter mode or Capture & one-count mode is selected */ + FSP_ERROR_RETURN(TAU_INTERRUPT_OPIRQ_BIT_RESET == p_extend->opirq, FSP_ERR_INVALID_MODE); + + /* Trigger Edge Both is supported Measure Low Level Pulse Width and Measure High Level Pulse Width */ + if (TAU_TIMER_MODE_CAPTURE_AND_ONE_COUNT == mode_timer) + { + FSP_ERROR_RETURN(TAU_TRIGGER_EDGE_BOTH == p_extend->trigger_edge, FSP_ERR_INVALID_MODE); + } + } + + return FSP_SUCCESS; +} + +#endif + +#if TAU_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking valid range of period. + * + * @param[in] p_cfg Pointer to TAU config structure + * @param[in] period_counts Current timer period + * @param[in] period_8bit_counts Current higher 8-bit timer period + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION The period is not in the valid range + **********************************************************************************************************************/ +static fsp_err_t r_tau_cnt_check (timer_cfg_t const * const p_cfg, uint32_t period_counts, uint32_t period_8bit_counts) +{ + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_cfg->p_extend; + + uint32_t min_timer = 1; + uint32_t max_timer = TAU_MAXIMUM_16BIT_TIMER_MODE; + + /* Checking range of each function */ + switch (p_extend->tau_func) + { + case TAU_FUNCTION_INTERVAL: + case TAU_FUNCTION_SQUARE_WAVE: + { + if (TIMER_SOURCE_DIV_1 == p_cfg->source_div) + { + min_timer = 2; + } + + if (TAU_BIT_MODE_16BIT != p_extend->bit_mode) + { + max_timer = TAU_MAXIMUM_8BIT_TIMER_MODE; + } + + break; + } + + case TAU_FUNCTION_DIVIDER: + { + if (TAU_TRIGGER_EDGE_BOTH == p_extend->trigger_edge) + { + max_timer = TAU_MAXIMUM_BOTH_EDGE_DIVIDER_FUNCTION; + } + else + { + max_timer = TAU_MAXIMUM_FALLING_RISING_EDGE_DIVIDER_FUNCTION; + min_timer = 2; + } + + break; + } + + case TAU_FUNCTION_EXTERNAL_EVENT_COUNT: + case TAU_FUNCTION_DELAY_COUNT: + { + if (TAU_BIT_MODE_16BIT != p_extend->bit_mode) + { + max_timer = TAU_MAXIMUM_8BIT_TIMER_MODE; + } + + break; + } + + default: + { + break; + } + } + + if ((1U << p_extend->tau_func) & TAU_TDR_WRITE_MSK_BY_TIMER_MODE) + { + if (TAU_BIT_MODE_HIGHER_8BIT != p_extend->bit_mode) + { + FSP_ASSERT(max_timer >= period_counts); + FSP_ASSERT(min_timer <= period_counts); + } + + if ((TAU_BIT_MODE_HIGHER_8BIT == p_extend->bit_mode) || + (TAU_BIT_MODE_HIGHER_LOWER_8BIT == p_extend->bit_mode)) + { + FSP_ASSERT(max_timer >= period_8bit_counts); + FSP_ASSERT(min_timer <= period_8bit_counts); + } + } + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Configures TAU related registers based on user configurations. + * + * @param[in] p_ctrl Pointer to TAU control structure + * @param[in] p_cfg Pointer to TAU specific configuration structure + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION The period is not in the valid range. + **********************************************************************************************************************/ +static fsp_err_t r_tau_config_set (tau_instance_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ +#if !(TAU_CFG_INPUT_SUPPORT_ENABLE || TAU_CFG_OUTPUT_SUPPORT_ENABLE) + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_cfg->p_extend; + + uint32_t tmr_split = (p_extend->bit_mode == TAU_BIT_MODE_16BIT) ? 0U : R_TAU_TMR0_MASTER_SPLIT_Msk; + + /* Setting Function timer */ + uint32_t tmr = ((((uint32_t) p_extend->operation_clock) << R_TAU_TMR0_CKS_Pos) | + (((uint32_t) p_extend->opirq) << R_TAU_TMR0_OPIRQ_Pos) | + tmr_split | tau_func_setting_lut[p_extend->tau_func]); + +#if TAU_CFG_INPUT_SUPPORT_ENABLE + tau_function_t tau_func = p_extend->tau_func; + + if ((1 << tau_func) & TAU_FUNCTION_SUPPORTED_INPUT_MASK) + { + /* Setting trigger edge */ + uint32_t tmr0_cis; + + if (TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT == tau_func) + { + tmr0_cis = TAU_INPUT_LOW_LEVEL_MEASUREMENT_SETTING; + } + else if (TAU_FUNCTION_HIGH_LEVEL_WIDTH_MEASUREMENT == tau_func) + { + tmr0_cis = TAU_INPUT_HIGH_LEVEL_MEASUREMENT_SETTING; + } + else + { + tmr0_cis = p_extend->trigger_edge; + } + + tmr |= tmr0_cis << R_TAU_TMR0_CIS_Pos; + + r_tau_config_input_set(p_ctrl); + } +#endif + + /* Set TAU divisors based on BSP settings */ + R_TAU->TPS0 = (uint16_t) ((TAU_PRV_TPS0_PRS3_SETTING << R_TAU_TPS0_PRS3_Pos) | + (TAU_PRV_TPS0_PRS2_SETTING << R_TAU_TPS0_PRS2_Pos) | + (BSP_CFG_TAU_CK01 << R_TAU_TPS0_PRS1_Pos) | BSP_CFG_TAU_CK00); + + /* Set timer mode */ + R_TAU->TMR0[p_cfg->channel] = (uint16_t) tmr; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(FSP_SUCCESS == r_tau_cnt_set(p_cfg, p_cfg->period_counts, p_extend->period_higher_8bit_counts)); +#else + r_tau_cnt_set(p_cfg, p_cfg->period_counts, p_extend->period_higher_8bit_counts); +#endif + +#if TAU_CFG_OUTPUT_SUPPORT_ENABLE + r_tau_config_output_set(p_ctrl); +#endif + + return FSP_SUCCESS; +} + +#if TAU_CFG_INPUT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Configures input source of TAU related registers based on user configurations. + * + * @param[in] p_ctrl Pointer to TAU control structure + **********************************************************************************************************************/ +static void r_tau_config_input_set (tau_instance_ctrl_t * const p_ctrl) +{ + #if TAU_CFG_EXTRA_INPUT_SUPPORT_ENABLE + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + uint32_t channel = p_ctrl->p_cfg->channel; + uint32_t channel_mask = p_ctrl->channel_mask; + + uint8_t tnfen = R_PORGA->TNFEN; + tnfen &= (uint8_t) (~channel_mask); + tnfen |= (uint8_t) (p_extend->tau_filter << channel); + R_PORGA->TNFEN = tnfen; + + tau_input_source_t input_source = p_extend->input_source; + + if (channel_mask & TAU_INPUT_RXD_CAPABLE_CHANNEL_MASK) + { + uint8_t isc_value = R_PORGA->ISC; + isc_value &= (uint8_t) (~R_PORGA_ISC_ISC1_Msk); + + if (TAU_INPUT_SOURCE_RXD_PIN == input_source) + { + isc_value |= R_PORGA_ISC_ISC1_Msk; + } + + R_PORGA->ISC = isc_value; + } + + #if BSP_FEATURE_ELC_VERSION + if (channel_mask & TAU_ELC_CAPABLE_CHANNELS_MASK) + { + uint8_t tis1_value = R_PORGA->TIS1; + tis1_value &= (uint8_t) (~channel_mask); + + if (TAU_INPUT_SOURCE_ELC == input_source) + { + tis1_value |= (uint8_t) channel_mask; + } + + R_PORGA->TIS1 = tis1_value; + } + #endif + + if (channel_mask & TAU_INPUT_CLOCK_CAPABLE_CHANNEL_MASK) + { + uint8_t tis0_value = (input_source & R_PORGA_TIS0_TIS_Msk); + R_PORGA->TIS0 = tis0_value; + } + + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif +} + +#endif + +#if TAU_CFG_OUTPUT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Configures output of TAU related registers based on user configurations. + * + * @param[in] p_ctrl Pointer to TAU control structure + **********************************************************************************************************************/ +static void r_tau_config_output_set (tau_instance_ctrl_t * const p_ctrl) +{ + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + if ((1 << p_extend->tau_func) & TAU_FUNCTION_SUPPORTED_OUTPUT_MASK) + { + /* Sets master channel output mode. Note: r_tau does not support slave functionality.*/ + uint8_t inverted_channel_mask = (uint8_t) (~p_ctrl->channel_mask); + + uint16_t to0_value = R_TAU->TO0 & inverted_channel_mask; + + if (TAU_PIN_OUTPUT_CFG_START_LEVEL_HIGH == p_extend->initial_output) + { + to0_value |= p_ctrl->channel_mask; + } + + R_TAU->TO0 = to0_value; + R_TAU->TOE0 |= p_ctrl->channel_mask; + } +} + +#endif + +/*******************************************************************************************************************//** + * Set TAU counter registers based on user configurations. + * + * @param[in] p_cfg Pointer to TAU config structure + * @param[in] period_counts Current timer period (lower 8-bit or 16-bit timer) + * @param[in] period_8bit_counts Current higher 8-bit timer period + * + * @retval FSP_SUCCESS The counter was successful updated. + * @retval FSP_ERR_ASSERTION The period is not in the valid range + **********************************************************************************************************************/ +static fsp_err_t r_tau_cnt_set (timer_cfg_t const * const p_cfg, uint32_t period_counts, uint32_t period_8bit_counts) +{ + tau_extended_cfg_t * p_extend = (tau_extended_cfg_t *) p_cfg->p_extend; + +#if TAU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(FSP_SUCCESS == r_tau_cnt_check(p_cfg, period_counts, period_8bit_counts)); +#elif !TAU_CFG_8BIT_MODE_SUPPORT_ENABLE + FSP_PARAMETER_NOT_USED(period_8bit_counts); +#endif + + uint32_t tdr = period_counts - 1; + + if ((TAU_FUNCTION_DIVIDER == p_extend->tau_func) && (TAU_TRIGGER_EDGE_BOTH != p_extend->trigger_edge)) + { + tdr = (period_counts >> 1) - 1; + } + + volatile uint8_t * tdr0 = (volatile uint8_t *) &(R_TAU->TDR0[p_cfg->channel]); + +#if TAU_CFG_8BIT_MODE_SUPPORT_ENABLE + uint32_t tdr_8bit = period_8bit_counts - 1; + tau_bit_mode_t bit_mode = p_extend->bit_mode; + + if ((TAU_BIT_MODE_HIGHER_8BIT == bit_mode) || (TAU_BIT_MODE_HIGHER_LOWER_8BIT == bit_mode)) + { + /* In 8-bit modes, the upper 8 bits can only be written with an 8-bit write */ + *(tdr0 + 1) = (uint8_t) tdr_8bit; + } +#endif + + /* The upper 8 bits of this write are truncated in 8-bit modes */ + *(volatile uint16_t *) tdr0 = (uint16_t) tdr; + + return FSP_SUCCESS; +} + +#if TAU_CFG_INTERRUPT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Disables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + **********************************************************************************************************************/ +static void r_tau_disable_irq (IRQn_Type irq) +{ + /* Disable interrupts. */ + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + } +} + +/*******************************************************************************************************************//** + * Configures and enables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + **********************************************************************************************************************/ +static void r_tau_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + if (irq >= 0) + { + R_BSP_IrqCfgEnable(irq, priority, p_context); + } +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to TAU instance control block + * @param[in] event Event code + * @param[in] capture Event capture counts (if applicable) + **********************************************************************************************************************/ +static void r_tau_call_callback (tau_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture) +{ + timer_callback_args_t args; + + args.event = event; + args.p_context = p_ctrl->p_context; + + if (TIMER_EVENT_CAPTURE_EDGE == event) + { + /* Add in overflow if it occurred */ + capture += 1 + (((uint32_t) R_TAU->TSR0[p_ctrl->p_cfg->channel]) << 16); + } + + args.capture = capture; + + /* Call the callback */ + p_ctrl->p_callback(&args); +} + +/*******************************************************************************************************************//** + * Generic ISR function to handle both TAU interrupts. + * + * @param[in] event Event code + **********************************************************************************************************************/ +static void tau_generic_isr (timer_event_t event) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + tau_instance_ctrl_t * p_instance_ctrl = (tau_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + tau_function_t func = ((tau_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->tau_func; + uint32_t counter = 0; + + if ((TAU_FUNCTION_INPUT_PULSE_INTERVAL_MEASUREMENT == func) || (TAU_FUNCTION_LOW_LEVEL_WIDTH_MEASUREMENT == func) || + (TAU_FUNCTION_HIGH_LEVEL_WIDTH_MEASUREMENT == func)) + { + event = TIMER_EVENT_CAPTURE_EDGE; + + /* Get captured value. */ + counter = (uint32_t) (R_TAU->TDR0[p_instance_ctrl->p_cfg->channel].TDR0n); + } + + if (NULL != p_instance_ctrl->p_callback) + { + r_tau_call_callback(p_instance_ctrl, event, counter); + } +} + +/*******************************************************************************************************************//** + * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void tau_tmi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + tau_generic_isr(TIMER_EVENT_CYCLE_END); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + + #if TAU_CFG_8BIT_MODE_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Only supported for higher 8-bit timer mode. Notifies application of trough event. + **********************************************************************************************************************/ +void tau_tmih_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + tau_generic_isr(TIMER_EVENT_HIGHER_8BIT_CYCLE_END); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + + #endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tau_pwm/r_tau_pwm.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tau_pwm/r_tau_pwm.c new file mode 100644 index 0000000000..d343093436 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tau_pwm/r_tau_pwm.c @@ -0,0 +1,971 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_tau_pwm.h" +#include "r_tau_pwm_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "TAUP" in ASCII, used to determine if channel is open. */ +#define TAU_PWM_OPEN (0x54415550ULL) + +#define TAU_PWM_PRV_TMR0_MD_INTERVAL_TIMER (0U) +#define TAU_PWM_PRV_TMR0_MD_ONE_COUNT (4U) +#define TAU_PWM_PRV_TMR0_STS_TI0n_VALID_EDGE (1U) +#define TAU_PWM_PRV_TMR0_STS_TAU0_TMI0n (4U) + +#define TAU_PWM_PRV_PERIOD_MAX (0x10001U) +#define TAU_PWM_PRV_PERIOD_MIN (0x00002U) + +/* Shifted mask for TPS0.PRS2 and .PRS3 bitfields */ +#define TAU_PRV_PRS2_PRS3_MASK (0x3U) + +/* Divisor settings for CK02 and CK03 */ +#define TAU_PRV_TPS0_PRS3_SETTING ((BSP_CFG_TAU_CK03 >> 1) & TAU_PRV_PRS2_PRS3_MASK) +#define TAU_PRV_TPS0_PRS2_SETTING ((BSP_CFG_TAU_CK02 >> 1) & TAU_PRV_PRS2_PRS3_MASK) + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_tau_pwm_hardware_initialize(tau_pwm_instance_ctrl_t * const p_instance_ctrl, + timer_cfg_t const * const p_cfg); + +static void r_tau_pwm_master_channel_initialize(tau_pwm_instance_ctrl_t * p_instance_ctrl, + timer_cfg_t const * const p_cfg); + +static void r_tau_pwm_slave_channels_initialize(tau_pwm_instance_ctrl_t * p_instance_ctrl, + timer_cfg_t const * const p_cfg); + +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_tau_pwm_parameter_checking(tau_pwm_instance_ctrl_t * const p_instance_ctrl, + timer_cfg_t const * const p_cfg); + +#endif + +static void r_tau_pwm_disable_irq(IRQn_Type irq); + +static void r_tau_pwm_enable_irq(IRQn_Type const irq, uint32_t priority, void * p_context); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void tau_pwm_common_tmi_isr(timer_event_t event); +void tau_pwm_master_tmi_isr(void); +void tau_pwm_slave_tmi_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* TAU_PWM implementation of timer interface */ +const timer_api_t g_timer_on_tau_pwm = +{ + .open = R_TAU_PWM_Open, + .stop = R_TAU_PWM_Stop, + .start = R_TAU_PWM_Start, + .reset = R_TAU_PWM_Reset, + .enable = R_TAU_PWM_Enable, + .disable = R_TAU_PWM_Stop, + .periodSet = R_TAU_PWM_PeriodSet, + .compareMatchSet = R_TAU_PWM_CompareMatchSet, + .dutyCycleSet = R_TAU_PWM_DutyCycleSet, + .infoGet = R_TAU_PWM_InfoGet, + .statusGet = R_TAU_PWM_StatusGet, + .callbackSet = R_TAU_PWM_CallbackSet, + .close = R_TAU_PWM_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup TAU_PWM + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open. + * + * The TAU_PWM implementation of the timer requires a tau_pwm_extended_cfg_t extension parameter. + * + * Example: + * @snippet r_tau_pwm_example.c R_TAU_PWM_Open + * + * @retval FSP_SUCCESS Initialization was successful + * @retval FSP_ERR_ASSERTION A required input pointer is NULL, or one of the following is invalid: the + * count of source divider/period/duty cycle/slave channels, or the trigger + * source. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED ISR of master channel must be enabled + * @retval FSP_ERR_INVALID_MODE Invalid configuration option provided for selected timer mode + * @retval FSP_ERR_INVALID_CHANNEL The master/slave channel selected is not available on this device, + * slave channel number must be greater than master channel number. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + err = r_tau_pwm_parameter_checking(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Set configuration */ + p_instance_ctrl->p_cfg = p_cfg; + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + + r_tau_pwm_hardware_initialize(p_instance_ctrl, p_cfg); + +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + p_instance_ctrl->open = TAU_PWM_OPEN; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Stops timer. Implements @ref timer_api_t::stop. + * + * Example: + * @snippet r_tau_pwm_example.c R_TAU_PWM_Stop + * + * @retval FSP_SUCCESS Timer successfully stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_Stop (timer_ctrl_t * const p_ctrl) +{ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Stop timer */ + R_TAU->TT0 = p_instance_ctrl->channels_mask; + + /* Disable the output */ + R_TAU->TOE0 &= (uint16_t) ~(p_instance_ctrl->slave_channels_mask); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts timer (pwm mode) or triggers the one-shot pulse output by software (one-shot mode). + * Implements @ref timer_api_t::start. + * + * @note In one-shot mode, this function is supported only after the timer has been placed into the start trigger + * detection wait state by calling @ref timer_api_t::enable + * + * Example: + * @snippet r_tau_pwm_example.c R_TAU_PWM_Start + * + * @retval FSP_SUCCESS Timer successfully started. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_NOT_ENABLED In One-shot mode, timer must be enabled first. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_Start (timer_ctrl_t * const p_ctrl) +{ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + #if TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE + if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + /* Get the channel status */ + bool channel_in_use = R_TAU->TE0 & (1U << p_instance_ctrl->p_cfg->channel); + FSP_ERROR_RETURN(channel_in_use, FSP_ERR_NOT_ENABLED); + } + #endif +#endif + + uint16_t ts0 = 0; +#if TAU_PWM_CFG_PWM_MODE_ENABLE + if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + /* Enable the output */ + R_TAU->TOE0 |= (uint16_t) (p_instance_ctrl->slave_channels_mask); + + /* Start timer */ + ts0 = p_instance_ctrl->channels_mask; + } + + #if TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE + else + #endif +#endif +#if TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE + { + /* Start trigger the one-shot pulse output by software */ + ts0 = (uint16_t) (p_instance_ctrl->master_channel_mask); + } +#endif + + R_TAU->TS0 = ts0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter value to the current period and duty cycle. Implements @ref timer_api_t::reset. + * + * @note If the timer is stopped when calling this function, the timer counter is not reset. The counter will be + * reset one cycle after the timer is next started (or restarted), since it takes one cycle to reload the initial count + * when starting the timer. + * + * @retval FSP_SUCCESS Counter value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_Reset (timer_ctrl_t * const p_ctrl) +{ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Get the channel status */ + bool channel_in_use = R_TAU->TE0 & (1U << p_instance_ctrl->p_cfg->channel); + if (channel_in_use) + { + /* Stop timer */ + R_TAU->TT0 = p_instance_ctrl->channels_mask; + + /* Restart timer */ + R_TAU->TS0 = p_instance_ctrl->channels_mask; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables external event inputs that can start the counter and enables the software trigger. + * After a successful call to this function, the timer is placed into the trigger detection wait state. + * Implements @ref timer_api_t::enable. + * + * Example: + * @snippet r_tau_pwm_example.c R_TAU_PWM_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_MODE The mode is invalid, only called in TIMER_MODE_ONE_SHOT mode. + * @retval FSP_ERR_UNSUPPORTED Unsupported when one shot mode support is disabled + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_Enable (timer_ctrl_t * const p_ctrl) +{ +#if TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; + #if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Only called in one-shot mode */ + FSP_ERROR_RETURN(TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode, FSP_ERR_INVALID_MODE); + #endif + + /* Enable the output */ + R_TAU->TOE0 |= (uint16_t) (p_instance_ctrl->slave_channels_mask); + + /* Start timer and wait for trigger source to start count */ + R_TAU->TS0 = p_instance_ctrl->channels_mask; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Sets period value provided. If the timer is running, the period will be updated after the next counter underflow. + * If the timer is stopped, this function resets the counter and updates the period. + * Implements @ref timer_api_t::periodSet. + * + * Example: + * @snippet r_tau_pwm_example.c R_TAU_PWM_PeriodSet + * + * @retval FSP_SUCCESS Period value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Period counts is out of range. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; + +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(period_counts <= (UINT16_MAX + 1), FSP_ERR_INVALID_ARGUMENT); +#endif + + /* Sets the TDR register to the period minus 1 or 2 based on the timer mode */ + uint32_t tdr0 = period_counts - 2U; +#if TAU_PWM_CFG_PWM_MODE_ENABLE + if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + tdr0 = tdr0 + 1U; + } +#endif + R_TAU->TDR0[p_instance_ctrl->p_cfg->channel].TDR0n = (uint16_t) tdr0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported compareMatch function. Implements @ref timer_api_t::compareMatchSet. + * + * @retval FSP_ERR_UNSUPPORTED TAU PWM compare match is not supported. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_CompareMatchSet (timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel) +{ + /* This function isn't supported. It is defined only to implement a required function of timer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(compare_match_value); + FSP_PARAMETER_NOT_USED(match_channel); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Sets duty cycle on requested pin. Implements @ref timer_api_t::dutyCycleSet. + * + * Duty cycle is updated in the timer data register. The updated duty cycle is reflected after the next cycle end + * (counter underflow). + * + * Example: + * @snippet r_tau_pwm_example.c R_TAU_PWM_DutyCycleSet + * + * @param[in] p_ctrl Pointer to instance control block. + * @param[in] duty_cycle_counts Duty cycle to set in counts. + * @param[in] pin Use tau_pwm_io_pin_t to select the target slave channel + * + * @retval FSP_SUCCESS Duty cycle updated successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL or the pin is not one of tau_pwm_io_pin_t. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Duty cycle is out of range or larger than period. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; + + FSP_ASSERT(NULL != p_instance_ctrl); + + /* Duty cycle counts must be in valid range. */ + if (TIMER_SOURCE_DIV_1 == p_instance_ctrl->p_cfg->source_div) + { + FSP_ERROR_RETURN(1 <= duty_cycle_counts, FSP_ERR_INVALID_ARGUMENT); + } + + FSP_ERROR_RETURN(duty_cycle_counts <= UINT16_MAX, FSP_ERR_INVALID_ARGUMENT); + + /* Duty cycle must be <= period. */ + FSP_ERROR_RETURN(duty_cycle_counts <= p_instance_ctrl->p_cfg->period_counts, FSP_ERR_INVALID_ARGUMENT); + + /* Do not select the pin of master channel. */ + FSP_ASSERT(pin != p_instance_ctrl->p_cfg->channel); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Sets the TDR register for slave channels */ + R_TAU->TDR0[pin].TDR0n = (uint16_t) duty_cycle_counts; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_tau_pwm_example.c R_TAU_PWM_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, frequency written to caller's structure successfully + * @retval FSP_ERR_ASSERTION p_ctrl or p_info was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; + uint8_t specific_divider; + +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + timer_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + + tau_pwm_extended_cfg_t * p_extend = (tau_pwm_extended_cfg_t *) p_cfg->p_extend; + + /* Get and store period */ + p_info->period_counts = R_TAU->TDR0[p_instance_ctrl->p_cfg->channel].TDR0n + 2U; +#if TAU_PWM_CFG_PWM_MODE_ENABLE + if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + p_info->period_counts = p_info->period_counts - 1U; + } +#endif + + /* Get and store clock frequency */ + /* figure out which clock and associated divider is driving this channel */ + uint32_t bsp_ck0n_div = BSP_CFG_TAU_CK01 << 8 | BSP_CFG_TAU_CK00; + specific_divider = (uint8_t) (bsp_ck0n_div >> (p_extend->operation_clock << 2)); + + p_info->clock_frequency = SystemCoreClock >> specific_divider; + + /* Get and store clock count direction as down. */ + p_info->count_direction = TIMER_DIRECTION_DOWN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Retrieves the current timer state and master channel counter value and stores them in provided pointer p_status. + * Implements @ref timer_api_t::statusGet. + * + * Example: + * @snippet r_tau_pwm_example.c R_TAU_PWM_StatusGet + * + * @retval FSP_SUCCESS Current timer state and counter value retrieved successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint8_t channel = p_instance_ctrl->p_cfg->channel; + + /* Get counter state. */ + p_status->state = (timer_state_t) ((R_TAU->TE0 >> channel) & 1U); + + /* Get counter value */ + p_status->counter = R_TAU->TCR0[channel]; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_callback was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + tau_pwm_instance_ctrl_t * p_ctrl = (tau_pwm_instance_ctrl_t *) p_api_ctrl; + +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + FSP_PARAMETER_NOT_USED(p_callback_memory); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TAU_PWM_Close (timer_ctrl_t * const p_ctrl) +{ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) p_ctrl; + +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TAU_PWM_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Stop timer */ + R_TAU->TT0 = p_instance_ctrl->channels_mask; + + /* Disable the output */ + R_TAU->TOE0 &= (uint16_t) ~(p_instance_ctrl->slave_channels_mask); + + /* Disable interrupts. */ + const tau_pwm_extended_cfg_t * p_extend = (tau_pwm_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + r_tau_pwm_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq); +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + + /* Clear open flag. */ + p_instance_ctrl->open = 0U; +#endif + +#if (1 == TAU_PWM_CFG_MULTI_SLAVE_ENABLE) + + /* Save the active slave mask; shift right because channel 0 cant be a slave */ + uint8_t slave_channels_mask = (p_instance_ctrl->slave_channels_mask >> 1); + + uint8_t index = 0; + do + { + if (slave_channels_mask & 0x01) + { + r_tau_pwm_disable_irq(p_extend->p_slave_channel_cfgs[index]->cycle_end_irq); + index++; + } + + slave_channels_mask >>= 1; + } while (slave_channels_mask > 0); + + p_instance_ctrl->slave_channels_mask = 0; +#else + + /* Single slave mode always uses index 0 */ + if ((0 != p_instance_ctrl->slave_channels_mask) && (NULL != p_extend->p_slave_channel_cfgs[0])) + { + r_tau_pwm_disable_irq(p_extend->p_slave_channel_cfgs[0]->cycle_end_irq); + p_instance_ctrl->slave_channels_mask = 0; + } +#endif + + return FSP_SUCCESS; +} + +/** @} (end addtogroup TAU_PWM) */ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +#if TAU_PWM_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL, or one of the following is invalid: the + * count of source divider/period/duty cycle/slave channels, or the trigger + * source. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED ISR of master channel must be enabled + * @retval FSP_ERR_INVALID_MODE Simultaneous Channel Operation Function of TAU only support + * TIMER_MODE_ONE_SHOT and TIMER_MODE_PWM and event trigger source only + * supported in TIMER_MODE_ONE_SHOT mode + * @retval FSP_ERR_INVALID_CHANNEL The master/slave channel selected is not available on this device, + * slave channel number must be greater than master channel number. + **********************************************************************************************************************/ +static fsp_err_t r_tau_pwm_parameter_checking (tau_pwm_instance_ctrl_t * const p_instance_ctrl, + timer_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TIMER_MODE_PWM == p_cfg->mode || TIMER_MODE_ONE_SHOT == p_cfg->mode, FSP_ERR_INVALID_MODE); + FSP_ERROR_RETURN(TAU_PWM_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Master channel must available on the device and must be even */ + FSP_ERROR_RETURN(((1 << p_cfg->channel) & BSP_FEATURE_TAU_VALID_CHANNEL_MASK) && !(p_cfg->channel & 0x01), + FSP_ERR_INVALID_CHANNEL); + + /* Master channel's interrupt must be enabled */ + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + + tau_pwm_extended_cfg_t * p_extend = (tau_pwm_extended_cfg_t *) p_cfg->p_extend; + uint32_t slave_channels_configured = 0U; + + #if BSP_FEATURE_ELC_VERSION + if (TAU_PWM_SOURCE_ELC_EVENT == p_extend->trigger_source) + { + /* ELC event trigger source only supported in TIMER_MODE_ONE_SHOT mode. */ + FSP_ERROR_RETURN(TIMER_MODE_ONE_SHOT == p_cfg->mode, FSP_ERR_INVALID_MODE); + + /* Master channel must be 0 when ELC is used as the trigger source. */ + FSP_ERROR_RETURN(0 == p_cfg->channel, FSP_ERR_INVALID_CHANNEL); + + /* PCLK (undivided) must be selected when ELC is used as the trigger source. */ + FSP_ASSERT(TIMER_SOURCE_DIV_1 == p_cfg->source_div); + } + + #else + + /* Trigger source must be TAU_PWM_SOURCE_PIN_INPUT if ELC is not supported. */ + FSP_ASSERT(TAU_PWM_SOURCE_PIN_INPUT == p_extend->trigger_source); + #endif + + #if (0 == TAU_PWM_CFG_MULTI_SLAVE_ENABLE) + const uint8_t index = 0; + #else + for (uint8_t index = 0; index < TAU_PWM_MAX_NUM_SLAVE_CHANNELS; index++) + #endif + { + if (NULL != p_extend->p_slave_channel_cfgs[index]) + { + uint8_t slaveChannel = p_extend->p_slave_channel_cfgs[index]->channel; + slave_channels_configured++; + + /* Slave channel must be valid in range 1 to 7 and greater than master channel number */ + + FSP_ERROR_RETURN((slaveChannel > TAU_PWM_SLAVE_CHANNEL_UNUSED) && + (slaveChannel <= TAU_PWM_MAX_CHANNEL_NUM) && /*This is TAU_PWM_MAX_CHANNEL_NUM + * because even with a single slave it could be any slave + * from 1-7 */ + (p_extend->p_slave_channel_cfgs[index]->channel > p_cfg->channel), + FSP_ERR_INVALID_CHANNEL); + + /* Pulse width/duty cycle counts of slave channels must be in valid range */ + if (TIMER_SOURCE_DIV_1 == p_cfg->source_div) + { + FSP_ASSERT(1 <= p_extend->p_slave_channel_cfgs[index]->duty_cycle_counts); + } + } + } + + uint32_t master_counter_max = TAU_PWM_PRV_PERIOD_MAX; + uint32_t master_counter_min = TAU_PWM_PRV_PERIOD_MIN; + + if (TIMER_SOURCE_DIV_1 == p_cfg->source_div) + { + master_counter_min++; + } + + #if TAU_PWM_CFG_PWM_MODE_ENABLE + + /* decrement counters if mode is PWM */ + master_counter_min = master_counter_min - (TIMER_MODE_PWM == p_cfg->mode); + master_counter_max = master_counter_max - (TIMER_MODE_PWM == p_cfg->mode); + #endif + + /* Pulse period/delay time of master channel must be in valid range */ + FSP_ASSERT(master_counter_min <= p_cfg->period_counts); + FSP_ASSERT(p_cfg->period_counts <= master_counter_max); + + /* At least one slave channel must be configured */ + FSP_ASSERT(slave_channels_configured > 0U); + + #if TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE + + /* Only one slave channel must be configured in TIMER_MODE_ONE_SHOT mode */ + if (TIMER_MODE_ONE_SHOT == p_cfg->mode) + { + FSP_ASSERT(1U == slave_channels_configured); + } + #endif + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Performs hardware initialization of the TAU_PWM. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void r_tau_pwm_hardware_initialize (tau_pwm_instance_ctrl_t * const p_instance_ctrl, + timer_cfg_t const * const p_cfg) +{ + /* Set TAU divisors based on BSP settings */ + R_TAU->TPS0 = (uint16_t) ((TAU_PRV_TPS0_PRS3_SETTING << R_TAU_TPS0_PRS3_Pos) | + (TAU_PRV_TPS0_PRS2_SETTING << R_TAU_TPS0_PRS2_Pos) | + (BSP_CFG_TAU_CK01 << R_TAU_TPS0_PRS1_Pos) | BSP_CFG_TAU_CK00); + + /* Setting for master channel */ + r_tau_pwm_master_channel_initialize(p_instance_ctrl, p_cfg); + + /* Setting for slave channels */ + r_tau_pwm_slave_channels_initialize(p_instance_ctrl, p_cfg); +} + +/*******************************************************************************************************************//** + * Performs hardware initialization of the master channel. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void r_tau_pwm_master_channel_initialize (tau_pwm_instance_ctrl_t * p_instance_ctrl, + timer_cfg_t const * const p_cfg) +{ + /* Save pointer to extended configuration structure. */ + tau_pwm_extended_cfg_t * p_extend = (tau_pwm_extended_cfg_t *) p_cfg->p_extend; + p_instance_ctrl->master_channel_mask = (uint8_t) (1U << (p_cfg->channel)); + + /* Power on TAU to start module. */ + R_BSP_MODULE_START(FSP_IP_TAU, p_cfg->channel); + + /* Calculate TMR0 register for master channel */ + uint16_t tmr0 = 0; +#if TAU_PWM_CFG_ONE_SHOT_MODE_ENABLE + if (TIMER_MODE_ONE_SHOT == p_cfg->mode) + { + #if BSP_FEATURE_ELC_VERSION + if (0U == p_cfg->channel) + { + /* Sets the trigger source in case master channel is 0 */ + uint8_t tis1 = R_PORGA->TIS1; + tis1 &= (uint8_t) ~(p_instance_ctrl->master_channel_mask); + tis1 |= (uint8_t) p_extend->trigger_source; + R_PORGA->TIS1 = tis1; + } + #endif + + /* Clear the noise filter */ + uint8_t tnfen = R_PORGA->TNFEN & (uint8_t) ~(p_instance_ctrl->master_channel_mask); + if ((TAU_PWM_SOURCE_PIN_INPUT == p_extend->trigger_source)) + { + /* Enables the noise filter for input pin */ + tnfen |= p_instance_ctrl->master_channel_mask; + } + + R_PORGA->TNFEN = tnfen; + + /* Sets the operation mode to one count */ + tmr0 = TAU_PWM_PRV_TMR0_MD_ONE_COUNT << R_TAU_TMR0_MD_Pos; + + /* Sets the detection edge of input */ + tmr0 |= (uint32_t) (p_extend->detect_edge << R_TAU_TMR0_CIS_Pos); + + /* Sets the start trigger or capture trigger by valid edge of TI0n pin input*/ + tmr0 |= TAU_PWM_PRV_TMR0_STS_TI0n_VALID_EDGE << R_TAU_TMR0_STS_Pos; + } + + #if TAU_PWM_CFG_PWM_MODE_ENABLE + else + #endif +#endif +#if TAU_PWM_CFG_PWM_MODE_ENABLE + { + /* Sets the operation mode to interval timer */ + tmr0 = TAU_PWM_PRV_TMR0_MD_INTERVAL_TIMER << R_TAU_TMR0_MD_Pos; + + /* Generates TAU0_TMI0n when counting is started */ + tmr0 |= R_TAU_TMR0_OPIRQ_Msk; + } +#endif + + /* Sets the channel as master channel */ + tmr0 |= R_TAU_TMR0_MASTER_SPLIT_Msk; + + /* Sets the operation clock */ + tmr0 |= (uint16_t) (p_extend->operation_clock << R_TAU_TMR0_CKS_Pos); + + /* Set the TMR0 register to determines operation mode of master channel */ + R_TAU->TMR0[p_cfg->channel] = tmr0; + + /* Sets the TDR register to specify the counter data of master channel */ + uint32_t tdr0 = p_cfg->period_counts - 2U; +#if TAU_PWM_CFG_PWM_MODE_ENABLE + tdr0 += (TIMER_MODE_PWM == p_cfg->mode); +#endif + R_TAU->TDR0[p_cfg->channel].TDR0n = (uint16_t) tdr0; + + /* Sets output setting to default setting for master channel */ + if (0 < p_cfg->channel) + { + R_TAU->TOM0 &= (uint16_t) ~(p_instance_ctrl->master_channel_mask); + R_TAU->TOL0 &= (uint16_t) ~(p_instance_ctrl->master_channel_mask); + } + + R_TAU->TO0 &= (uint16_t) ~(p_instance_ctrl->master_channel_mask); + R_TAU->TOE0 &= (uint16_t) ~(p_instance_ctrl->master_channel_mask); + + /* Enables interrupt */ + r_tau_pwm_enable_irq(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); +} + +/*******************************************************************************************************************//** + * Performs hardware initialization of the slave channels. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + **********************************************************************************************************************/ +static void r_tau_pwm_slave_channels_initialize (tau_pwm_instance_ctrl_t * p_instance_ctrl, + timer_cfg_t const * const p_cfg) +{ + /* Save pointer to extended configuration structure. */ + tau_pwm_extended_cfg_t * p_extend = (tau_pwm_extended_cfg_t *) p_cfg->p_extend; + + /* Calculate TMR0 register for slave channels */ + uint16_t tmr0; + +#if (0 == TAU_PWM_CFG_MULTI_SLAVE_ENABLE) + const uint8_t index = 0; +#else + for (uint8_t index = 0; index < TAU_PWM_MAX_NUM_SLAVE_CHANNELS; index++) +#endif + { + if (NULL != p_extend->p_slave_channel_cfgs[index]) + { + const tau_pwm_channel_cfg_t * slave_channel_cfg = p_extend->p_slave_channel_cfgs[index]; + uint8_t slave_channel = slave_channel_cfg->channel; + uint8_t slave_channel_mask = (uint8_t) (1U << slave_channel); + + /* Sets the operation mode */ + tmr0 = TAU_PWM_PRV_TMR0_MD_ONE_COUNT << R_TAU_TMR0_MD_Pos; +#if TAU_PWM_CFG_PWM_MODE_ENABLE + if (TIMER_MODE_PWM == p_cfg->mode) + { + /* Trigger input is valid */ + tmr0 |= R_TAU_TMR0_OPIRQ_Msk; + } +#endif + + /* Sets the start trigger or capture trigger */ + tmr0 |= TAU_PWM_PRV_TMR0_STS_TAU0_TMI0n << R_TAU_TMR0_STS_Pos; + + /* Sets the operation clock */ + tmr0 |= (uint16_t) (p_extend->operation_clock << R_TAU_TMR0_CKS_Pos); + + /* Set the TMR0 register to determines operation mode of slave channel */ + R_TAU->TMR0[slave_channel] = tmr0; + + /* Sets the TDR register to specify the counter data of slave channel */ + R_TAU->TDR0[slave_channel].TDR0n = + slave_channel_cfg->duty_cycle_counts; + + /* Sets output setting for slave channel */ + R_TAU->TOM0 |= (uint16_t) (slave_channel_mask); + + uint16_t tol0 = R_TAU->TOL0; + tol0 &= (uint16_t) ~(slave_channel_mask); + tol0 |= (uint16_t) (slave_channel_cfg->output_polarity << slave_channel); + R_TAU->TOL0 = tol0; + + uint16_t to0 = R_TAU->TO0; + to0 &= (uint16_t) ~(slave_channel_mask); + to0 |= (uint16_t) (slave_channel_cfg->output_level << slave_channel); + R_TAU->TO0 = to0; + + p_instance_ctrl->slave_channels_mask |= slave_channel_mask; + + /* Enables interrupt */ + r_tau_pwm_enable_irq(slave_channel_cfg->cycle_end_irq, slave_channel_cfg->cycle_end_ipl, p_instance_ctrl); + } + } + + p_instance_ctrl->channels_mask = p_instance_ctrl->master_channel_mask | p_instance_ctrl->slave_channels_mask; +} + +/*******************************************************************************************************************//** + * Disables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + **********************************************************************************************************************/ +static void r_tau_pwm_disable_irq (IRQn_Type irq) +{ + /* Disable interrupts. */ + if (irq >= 0) + { + R_BSP_IrqDisable(irq); + R_FSP_IsrContextSet(irq, NULL); + } +} + +/*******************************************************************************************************************//** + * Configures and enables interrupt if it is a valid vector number. + * + * @param[in] irq Interrupt number + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + **********************************************************************************************************************/ +static void r_tau_pwm_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + if (irq >= 0) + { + R_BSP_IrqCfgEnable(irq, priority, p_context); + } +} + +/*******************************************************************************************************************//** + * Common ISR. + * + * Clears interrupt and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void tau_pwm_common_tmi_isr (timer_event_t event) +{ + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + tau_pwm_instance_ctrl_t * p_instance_ctrl = (tau_pwm_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* If a callback is provided, then call it with the event and context. */ + if (NULL != p_instance_ctrl->p_callback) + { + timer_callback_args_t args = {0}; + args.event = event; + args.p_context = p_instance_ctrl->p_context; + + /* Call the callback. */ + p_instance_ctrl->p_callback(&args); + } +} + +/*******************************************************************************************************************//** + * Master channel ISR. + **********************************************************************************************************************/ +void tau_pwm_master_tmi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Call the common isr function */ + tau_pwm_common_tmi_isr(TIMER_EVENT_MASTER_CYCLE_END); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/*******************************************************************************************************************//** + * Slave channel ISR. + **********************************************************************************************************************/ +void tau_pwm_slave_tmi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + /* Call the common isr function */ + tau_pwm_common_tmi_isr(TIMER_EVENT_SLAVE_CYCLE_END); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tml/r_tml.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tml/r_tml.c new file mode 100644 index 0000000000..8372fab38e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_tml/r_tml.c @@ -0,0 +1,1226 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_tml.h" +#include "r_tml_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "TML" in ASCII, used to determine if channel is open. */ +#define TML_OPEN (0x00544D4CULL) + +/* ITLCMP0n bit field definitions. */ +#define TML_PRV_ITLCMP0_UPPER_16_BIT_POS (16) +#define TML_PRV_ITLCMP0_UPPER_16_BIT_CLEARED (0x0000FFFFU) + +#define CHANNEL0_MASK (1U << 0) +#define CHANNEL2_MASK (1U << 2) +#define VALID_16_BIT_COUNTER_CHANNEL_MASK (CHANNEL0_MASK | CHANNEL2_MASK) +#define VALID_16_BIT_CAPTURE_CHANNEL_MASK (CHANNEL0_MASK) +#define VALID_32_BIT_COUNTER_CHANNEL_MASK (CHANNEL0_MASK) + +/* Counter clock selection (ISEL) */ +#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_TML_FITL0_SOURCE + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_HOCO) +#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_TML_FITL0_SOURCE + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_MOCO) +#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_TML_FITL0_SOURCE + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_MOSC) +#elif BSP_CFG_FSXP_SOURCE == BSP_CFG_TML_FITL0_SOURCE + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_LOCO_SOSC) +#else + #define TML_PRV_ITLCSEL0_ISEL_VALUE (TML_CLOCK_ELC_EVENT) +#endif + +/* Capture clock selection (CSEL) */ +#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_TML_FITL1_SOURCE + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_HOCO) +#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_TML_FITL1_SOURCE + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_MOCO) +#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_TML_FITL1_SOURCE + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_MOSC) +#elif BSP_CFG_FSXP_SOURCE == BSP_CFG_TML_FITL1_SOURCE + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_LOCO_SOSC) +#else + #define TML_PRV_ITLCSEL0_CSEL_VALUE (TML_CLOCK_ELC_EVENT) +#endif + +#if TML_CFG_CRITICAL_SECTION_ENABLE + #define TML_PRV_CRITICAL_SECTION_ENTER() {FSP_CRITICAL_SECTION_DEFINE; FSP_CRITICAL_SECTION_ENTER + #define TML_PRV_CRITICAL_SECTION_EXIT() FSP_CRITICAL_SECTION_EXIT;} +#else + #define TML_PRV_CRITICAL_SECTION_ENTER() + #define TML_PRV_CRITICAL_SECTION_EXIT() +#endif + +#if TML_CFG_SINGLE_CHANNEL_ENABLE + #define TML_PRV_CHANNEL (0U) + #define TML_PRV_CHANNEL_MASK (0x1U) + #define TML_PRV_ITLFDIV_ADDRESS (&(R_TML->ITLFDIV00)) + #define TML_PRV_ITLFDIV_POS (R_TML_ITLFDIV00_FDIV0_Pos) + #define TML_PRV_ITLFDIV_MASK (uint8_t) (R_TML_ITLFDIV00_FDIV0_Msk) +#else + #define TML_PRV_CHANNEL (p_instance_ctrl->p_cfg->channel) + #define TML_PRV_CHANNEL_MASK (p_instance_ctrl->channel_mask) + #define TML_PRV_ITLFDIV_ADDRESS (&(R_TML->ITLFDIV00) + TML_PRV_CHANNEL / 2) + #define TML_PRV_ITLFDIV_POS ((TML_PRV_CHANNEL & 0x01) * R_TML_ITLFDIV00_FDIV1_Pos) + #define TML_PRV_ITLFDIV_MASK (uint8_t) (R_TML_ITLFDIV00_FDIV0_Msk << TML_PRV_ITLFDIV_POS) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* TML channels. */ +typedef enum e_tml_channel +{ + TML_CHANNEL_0 = 0, // channel 0 + TML_CHANNEL_1 = 1, // channel 1 + TML_CHANNEL_2 = 2, // channel 2 + TML_CHANNEL_3 = 3, // channel 3 +} tml_channel_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static fsp_err_t r_tml_hardware_initialize(tml_instance_ctrl_t * const p_instance_ctrl, + timer_cfg_t const * const p_cfg); + +static void r_tml_period_counts_set(tml_instance_ctrl_t * const p_instance_ctrl, uint32_t const period_counts); + +static uint32_t r_tml_period_counts_get(tml_instance_ctrl_t * const p_instance_ctrl); + +#if TML_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_tml_open_param_checking(tml_instance_ctrl_t * const p_instance_ctrl, + timer_cfg_t const * const p_cfg); + +#endif + +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE +static fsp_err_t r_tml_enable_helper(timer_ctrl_t * const p_ctrl, bool enable); + +#endif + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE +void tml_itl_or_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE && (!TML_CFG_SINGLE_CHANNEL_ENABLE) + +/** Stored context for isr handler. */ +static tml_instance_ctrl_t * gp_tml_ctrls[BSP_FEATURE_TML_NUM_CHANNELS] = {NULL}; +#endif + +#if !TML_CFG_SINGLE_CHANNEL_ENABLE + +/** g_modeset is to track whether the mode has been set by an active channel. Incremented when a channel is opened, + * decremented when a channel is closed. This is done because the mode ITLCTL0_b.MD register doesn't have an + * "inactive" selection and we need to make sure the mode of a channel matches the modes of currently active + * channels. We can only set the mode on the first channel open.*/ +static uint8_t g_modeset = 0; +#endif + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* TML implementation of timer interface */ +const timer_api_t g_timer_on_tml = +{ + .open = R_TML_Open, + .stop = R_TML_Stop, + .start = R_TML_Start, + .reset = R_TML_Reset, + .enable = R_TML_Enable, + .disable = R_TML_Disable, + .periodSet = R_TML_PeriodSet, + .dutyCycleSet = R_TML_DutyCycleSet, + .compareMatchSet = R_TML_CompareMatchSet, + .infoGet = R_TML_InfoGet, + .statusGet = R_TML_StatusGet, + .callbackSet = R_TML_CallbackSet, + .close = R_TML_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup TML + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open. + * + * TML hardware does not support one-shot functionality natively. If one shot mode is desired, the user code should + * stop the timer after the timer expires the first time in an ISR after the requested period has elapsed. + * + * The TML implementation of the general timer can accept a tml_extended_cfg_t extension parameter. + * + * Example: + * @snippet r_tml_example.c R_TML_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the source divider is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED timer_cfg_t::p_callback is not NULL, but ISR is not enabled. + * ISR must be enabled to use one-shot mode or callback. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + * @retval FSP_ERR_INVALID_CHANNEL Selected channel is invalid + * @retval FSP_ERR_INVALID_MODE The mode requested in the p_cfg parameter is incorrect. + * It must be the same for all instances. + * @retval FSP_ERR_IN_USE Channel is running + **********************************************************************************************************************/ +fsp_err_t R_TML_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if TML_CFG_PARAM_CHECKING_ENABLE + err = r_tml_open_param_checking(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Initialize control structure. */ + p_instance_ctrl->p_cfg = p_cfg; + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + + err = r_tml_hardware_initialize(p_instance_ctrl, p_cfg); +#if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + p_instance_ctrl->open = TML_OPEN; +#endif + +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE && (!TML_CFG_SINGLE_CHANNEL_ENABLE) + gp_tml_ctrls[TML_PRV_CHANNEL] = p_instance_ctrl; +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Stops the counter and disable the capture. Implements @ref timer_api_t::stop. + * + * Example: + * @snippet r_tml_example.c R_TML_Stop + * + * @retval FSP_SUCCESS Timer successfully stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_TML_Stop (timer_ctrl_t * const p_ctrl) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; +#if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Critical section required because ITLCTL0 register is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t itlctl0 = R_TML->ITLCTL0; + + /* Stop timer */ + itlctl0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + + /* Save pointer to extended configuration structure. */ + tml_extended_cfg_t * p_tml_cfg = (tml_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) + { + if (TML_CAPTURE_TRIGGER_ITLCMP01 == p_tml_cfg->capture_trigger) + { + /* Stop timer channel 2 + 3 */ + itlctl0 &= (uint8_t) ~(R_TML_ITLCTL0_EN2_Msk); + } + } +#endif + + /* Write to registers */ + R_TML->ITLCTL0 = itlctl0; + + TML_PRV_CRITICAL_SECTION_EXIT(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts the counter and enable the capture. Implements @ref timer_api_t::start. + * + * Example: + * @snippet r_tml_example.c R_TML_Start + * + * @retval FSP_SUCCESS Timer successfully started. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_TML_Start (timer_ctrl_t * const p_ctrl) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; +#if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Critical section required because ITLCTL0 register is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t itlctl0 = R_TML->ITLCTL0; + uint8_t itls0 = R_TML->ITLS0; + uint8_t itlmkf0 = R_TML->ITLMKF0; + + /* Clear the ITF0i interrupt status flags for channel used. */ + itls0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + + /* Start timer */ + itlctl0 |= TML_PRV_CHANNEL_MASK; + +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + + /* Save pointer to extended configuration structure. */ + tml_extended_cfg_t * p_tml_cfg = (tml_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) + { + /* Clear the ITF0C interrupt status flags. */ + itls0 &= (uint8_t) ~(R_TML_ITLS0_ITF0C_Msk); + + if (TML_CAPTURE_TRIGGER_ITLCMP01 == p_tml_cfg->capture_trigger) + { + /* Enable the MKF02 masks of the ITF02 status flags. */ + itlmkf0 |= R_TML_ITLMKF0_MKF02_Msk; + + /* Clear the ITF02 interrupt status flags. */ + itls0 &= (uint8_t) ~(R_TML_ITLS0_ITF02_Msk); + + /* Start timer channel 2 + 3 */ + itlctl0 |= R_TML_ITLCTL0_EN2_Msk; + } + } +#endif + + /* Write to registers */ + R_TML->ITLMKF0 = itlmkf0; + R_TML->ITLS0 = itls0; + R_TML->ITLCTL0 = itlctl0; + + TML_PRV_CRITICAL_SECTION_EXIT(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter value to 0. Implements @ref timer_api_t::reset. + * + * @retval FSP_SUCCESS Counter value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_TML_Reset (timer_ctrl_t * const p_ctrl) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; +#if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Critical section required because ITLCTL0 register is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t channel_in_use = R_TML->ITLCTL0 & TML_PRV_CHANNEL_MASK; + + /* Modifying ITLCTL0:ENi from 1 to 0 clears the counter without synchronization with the count clock */ + R_TML->ITLCTL0 &= ~(channel_in_use); + + /* Restart the timer */ + R_TML->ITLCTL0 |= channel_in_use; + + TML_PRV_CRITICAL_SECTION_EXIT(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enable the interrupt generation from the selected channel @ref timer_api_t::enable. + * + * Example: + * @snippet r_tml_example.c R_TML_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_TML_Enable (timer_ctrl_t * const p_ctrl) +{ +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE + + return r_tml_enable_helper(p_ctrl, true); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Disable the interrupt generation for this timer. Implements @ref timer_api_t::disable. + * + * @note The timer could be stop after R_TML_Disable(). + * + * Example: + * @snippet r_tml_example.c R_TML_Disable + * + * @retval FSP_SUCCESS External events successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_TML_Disable (timer_ctrl_t * const p_ctrl) +{ +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE + + return r_tml_enable_helper(p_ctrl, false); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Sets period value provided. Only set this value when all timers are stop. + * Implements @ref timer_api_t::periodSet. + * + * Example: + * @snippet r_tml_example.c R_TML_PeriodSet + * + * @retval FSP_SUCCESS Period value written successfully. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IN_USE Channel is running + **********************************************************************************************************************/ +fsp_err_t R_TML_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; +#if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + uint8_t channel_status = R_TML->ITLCTL0 & TML_PRV_CHANNEL_MASK; + FSP_ERROR_RETURN(0U == channel_status, FSP_ERR_IN_USE); +#endif + + /* Specify a period value. */ + r_tml_period_counts_set(p_instance_ctrl, (period_counts - 1)); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @ref timer_api_t::dutyCycleSet is not supported on the TML. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_TML_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ + /* Prevent warnings */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(duty_cycle_counts); + FSP_PARAMETER_NOT_USED(pin); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +} + +/*******************************************************************************************************************//** + * @ref timer_api_t::compareMatchSet is not supported on the TML. + * + * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation. + **********************************************************************************************************************/ +fsp_err_t R_TML_CompareMatchSet (timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel) +{ + /* Prevent warnings */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(compare_match_value); + FSP_PARAMETER_NOT_USED(match_channel); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Get timer configuration information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_tml_example.c R_TML_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, frequency, and ELC event written to caller's + * structure successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_info was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_TML_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; +#if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_info); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Get and store period */ + p_info->period_counts = r_tml_period_counts_get(p_instance_ctrl) + 1; + + /* Get and store counter clock frequency */ +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + if (R_TML->ITLCC0_b.CAPEN && + (TIMER_MODE_16_BIT_COUNTER == p_instance_ctrl->p_cfg->mode) && + (BSP_CLOCKS_CLOCK_DISABLED != BSP_CFG_TML_FITL1_SOURCE)) + { + p_info->clock_frequency = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) BSP_CFG_TML_FITL1_SOURCE); + } + else +#endif + { + if (BSP_CLOCKS_CLOCK_DISABLED != BSP_CFG_TML_FITL0_SOURCE) + { + uint32_t clock_frequency = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) BSP_CFG_TML_FITL0_SOURCE); + p_info->clock_frequency = clock_frequency >> p_instance_ctrl->p_cfg->source_div; + } + } + + /* Get and store clock count direction as up. */ + p_info->count_direction = TIMER_DIRECTION_UP; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get current timer status and store it in provided pointer p_status. Implements @ref timer_api_t::statusGet. + * + * @note The counter value returned in p_status is always 0 because TML does not provide a readable counter register. + * + * Example: + * @snippet r_tml_example.c R_TML_StatusGet + * + * @retval FSP_SUCCESS Current timer state and counter value set successfully. + * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + **********************************************************************************************************************/ +fsp_err_t R_TML_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; +#if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Store 0 to current counter since cannot read the counter value. */ + p_status->counter = 0; + + /* Get counter state. */ + p_status->state = (timer_state_t) ((R_TML->ITLCTL0 & TML_PRV_CHANNEL_MASK) > 0); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_TML_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + FSP_PARAMETER_NOT_USED(p_callback_memory); + +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE + tml_instance_ctrl_t * p_ctrl = (tml_instance_ctrl_t *) p_api_ctrl; + + #if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(TML_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_context); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + * @retval FSP_ERR_IN_USE Channel is running + **********************************************************************************************************************/ +fsp_err_t R_TML_Close (timer_ctrl_t * const p_ctrl) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); +#endif + +#if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); +#endif + + /* Critical section required because ITLMKF0, ITLS0, ITLCTL0, ITLFDIV00, ITLFDIV01 registers are shared + * with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE + + /* Disable interrupts. */ + if (0 <= p_instance_ctrl->p_cfg->cycle_end_irq) + { + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->cycle_end_irq); + } +#endif + + uint8_t itlmkf0 = R_TML->ITLMKF0; + uint8_t itls0 = R_TML->ITLS0; + uint8_t itlctl0 = R_TML->ITLCTL0; + + /* Enable the interrupt generation from the selected channel by clearing the mask bits . */ + itlmkf0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + + /* Clear the ITF0i interrupt status flags. */ + itls0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + + /* Stop counter channel. */ + itlctl0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) + { + /* Disable the MKF0C masks of the ITF0C status flags. */ + itlmkf0 &= (uint8_t) ~(R_TML_ITLMKF0_MKF0C_Msk); + + /* Clear the ITF0C interrupt status flags. */ + itls0 &= (uint8_t) ~(R_TML_ITLS0_ITF0C_Msk); + + /* Save pointer to extended configuration structure. */ + tml_extended_cfg_t * p_tml_cfg = (tml_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (TML_CAPTURE_TRIGGER_ITLCMP01 == p_tml_cfg->capture_trigger) + { + /* Disable the MKF02 masks of the ITF02 status flags. */ + itlmkf0 &= (uint8_t) ~(R_TML_ITLMKF0_MKF02_Msk); + + /* Stop channels 2 + 3. */ + itlctl0 &= (uint8_t) ~(R_TML_ITLCTL0_EN2_Msk); + } + } +#endif + + /* Write to registers. */ + R_TML->ITLMKF0 = itlmkf0; + R_TML->ITLS0 = itls0; + R_TML->ITLCTL0 = itlctl0; + + /* Clear the frequency division ratio for the count source. */ + *(TML_PRV_ITLFDIV_ADDRESS) &= (uint8_t) ~(TML_PRV_ITLFDIV_MASK); + + TML_PRV_CRITICAL_SECTION_EXIT(); + +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) + { + /* Only set the ITLCC0.CAPEN and ITLCSEL0.CSEL when all timer channels are stopped. */ + FSP_ERROR_RETURN(0U == (BSP_FEATURE_TML_VALID_CHANNEL_MASK & R_TML->ITLCTL0), FSP_ERR_IN_USE); + + /* Disable capturing. */ + R_TML->ITLCC0 &= (uint8_t) ~(R_TML_ITLCC0_CAPEN_Msk); + + /* Clear the capture clock setting. */ + R_TML->ITLCSEL0 &= (uint8_t) ~(R_TML_ITLCSEL0_CSEL_Msk); + } +#endif +#if !TML_CFG_SINGLE_CHANNEL_ENABLE + #if TML_CFG_INTERRUPT_SUPPORT_ENABLE + + /* Clear instance. */ + gp_tml_ctrls[TML_PRV_CHANNEL] = NULL; + #endif + if (0U < g_modeset) + { + g_modeset--; + } +#endif + +#if TML_CFG_PARAM_CHECKING_ENABLE + + /* Clear open flag. */ + p_instance_ctrl->open = 0U; +#endif + + return err; +} + +/** @} (end addtogroup TML) */ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Performs hardware initialization of the TML. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + * + * @retval FSP_SUCCESS Successful initialize. + * @retval FSP_ERR_IN_USE Channel is running + **********************************************************************************************************************/ +fsp_err_t r_tml_hardware_initialize (tml_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + uint8_t channel = p_cfg->channel; + p_instance_ctrl->channel_mask = (uint8_t) (1U << channel); + uint8_t itlctl0; + uint8_t itlcsel0; + + /* Enable the TML channel and take module out of stop state. */ + R_BSP_MODULE_START(FSP_IP_TML, channel); + + /* Critical section required because ITLCTL0, ITLFDIV00, ITLFDIV01, ITLCSEL0 registers is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t timer_status = R_TML->ITLCTL0 & BSP_FEATURE_TML_VALID_CHANNEL_MASK; + +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + + /* Save pointer to extended configuration structure. */ + tml_extended_cfg_t * p_tml_cfg = (tml_extended_cfg_t *) p_cfg->p_extend; + + if (TIMER_MODE_16_BIT_CAPTURE == p_cfg->mode) + { + /* Only set the ITLCC0.CTRS, ITLCC0.CAPCCR and ITLCC0.CAPEN when all timer channels are stopped. */ + FSP_ERROR_RETURN(0U == timer_status, FSP_ERR_IN_USE); + + /* Select the capture trigger */ + uint8_t itlcc0 = R_TML_ITLCC0_CTRS_Msk & (uint8_t) (p_tml_cfg->capture_trigger << R_TML_ITLCC0_CTRS_Pos); + + /* Specify the clearing of the counter values in channels 0 and 1 after completion of capturing. */ + itlcc0 |= R_TML_ITLCC0_CAPCCR_Msk & (uint8_t) (p_tml_cfg->counter_status << R_TML_ITLCC0_CAPCCR_Pos); + + /* Enable capturing. */ + itlcc0 |= R_TML_ITLCC0_CAPEN_Msk; + + /* Write to ITLCC0 register */ + R_TML->ITLCC0 = itlcc0; + + /* Select the capture mode. */ + itlctl0 = R_TML_ITLCTL0_MD_Msk & (uint8_t) (TIMER_MODE_16_BIT_COUNTER << R_TML_ITLCTL0_MD_Pos); + } + else +#endif + { + /* Select the operation mode. */ + itlctl0 = R_TML_ITLCTL0_MD_Msk & (uint8_t) (p_cfg->mode << R_TML_ITLCTL0_MD_Pos); + } + + /* Select the count clock for the counter timer */ + itlcsel0 = R_TML_ITLCSEL0_ISEL_Msk & (uint8_t) (TML_PRV_ITLCSEL0_ISEL_VALUE << R_TML_ITLCSEL0_ISEL_Pos); + +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + + /* Select the count clock for the capture timer */ + if (R_TML->ITLCC0_b.CAPEN) + { + itlcsel0 |= (R_TML_ITLCSEL0_CSEL_Msk & (uint8_t) (TML_PRV_ITLCSEL0_CSEL_VALUE << R_TML_ITLCSEL0_CSEL_Pos)); + } +#endif + + /* Write to registers to setting mode/clock. */ +#if !TML_CFG_SINGLE_CHANNEL_ENABLE + if (0U == g_modeset++) +#endif + { + R_TML->ITLCTL0 = itlctl0 | timer_status; + } + + R_TML->ITLCSEL0 = itlcsel0; + + /* Select the frequency division ratio for the count source. */ + *(TML_PRV_ITLFDIV_ADDRESS) |= TML_PRV_ITLFDIV_MASK & + ((uint8_t) p_cfg->source_div << (TML_PRV_ITLFDIV_POS)); + + TML_PRV_CRITICAL_SECTION_EXIT(); + + /* Specify a period value for timer channel. */ + r_tml_period_counts_set(p_instance_ctrl, (p_cfg->period_counts - 1)); + +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE + + /* Enable CPU interrupts if callback is not null. */ + if (0 <= p_cfg->cycle_end_irq) + { + R_BSP_IrqCfgEnable(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Set the period value for counter channel. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] period_counts Time until timer should expire. + **********************************************************************************************************************/ +void r_tml_period_counts_set (tml_instance_ctrl_t * const p_instance_ctrl, uint32_t const period_counts) +{ + /* Specify a period value. */ + switch (p_instance_ctrl->p_cfg->mode) + { + case TIMER_MODE_8_BIT_COUNTER: + { + /* The ITLCMP00_L for channel 0 + * The ITLCMP00_H for channel 1 + * The ITLCMP01_L for channel 2 + * The ITLCMP01_H for channel 3 + */ + *(&(R_TML->ITLCMP00_L) + TML_PRV_CHANNEL) = (uint8_t) (period_counts); + break; + } + + case TIMER_MODE_16_BIT_COUNTER: + { + /* Set the ITLCMP0n register (n: 0, 1) */ + *(&(R_TML->ITLCMP00) + TML_PRV_CHANNEL / 2) = (uint16_t) (period_counts); + break; + } + + case TIMER_MODE_32_BIT_COUNTER: + { + /* Set the upper 16-bit period value in the ITLCMP01 register and the lower 16-bit period value + * in the ITLCMP00 register. */ + R_TML->ITLCMP01 = (uint16_t) (period_counts >> TML_PRV_ITLCMP0_UPPER_16_BIT_POS); + R_TML->ITLCMP00 = (uint16_t) (period_counts & TML_PRV_ITLCMP0_UPPER_16_BIT_CLEARED); + break; + } + +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + case TIMER_MODE_16_BIT_CAPTURE: + { + /* Save pointer to extended configuration structure. */ + tml_extended_cfg_t * p_tml_cfg = (tml_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (TML_CAPTURE_TRIGGER_ITLCMP01 == p_tml_cfg->capture_trigger) + { + /* Set the period value into ITLCMP01 register for channel 2 + 3 */ + R_TML->ITLCMP01 = (uint16_t) (period_counts); + } + + break; + } +#endif + + default: + { + break; + } + } +} + +#if TML_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking for R_TML_Open. + * + * @param[in] p_instance_ctrl Instance control block. + * @param[in] p_cfg Pointer to timer configuration. + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL, the source divider is invalid or + * the capture trigger source is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IRQ_BSP_DISABLED timer_cfg_t::p_callback is not NULL, but ISR is not enabled. + * ISR must be enabled to use one-shot mode or callback. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device. + * @retval FSP_ERR_INVALID_CHANNEL Selected channel is invalid + * @retval FSP_ERR_INVALID_MODE The mode requested in the p_cfg parameter is incorrect. + * It must be the same for all instances. + * @retval FSP_ERR_IN_USE Channel is running + **********************************************************************************************************************/ +fsp_err_t r_tml_open_param_checking (tml_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + /* Check NULL pointer. */ + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_instance_ctrl); + + timer_mode_t mode = p_cfg->mode; + uint8_t channel_mask = (uint8_t) (1U << p_cfg->channel); + + /* Check the status of channel selected. */ + FSP_ERROR_RETURN(TML_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Selected channel must be disabled (ITLCTL0.ENx is 0U). */ + FSP_ERROR_RETURN(0U == (R_TML->ITLCTL0 & channel_mask), FSP_ERR_IN_USE); + + #if !TML_CFG_SINGLE_CHANNEL_ENABLE + + /* Selected mode must be the same for all instance. */ + if (0U != g_modeset) + { + #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + tml_extended_cfg_t * p_cfg_ext = (tml_extended_cfg_t *) p_cfg->p_extend; + + /* Channels 2 and 3 can only be used in 16-bit counter mode when an interrupt on compare match with + * ITLCMP01 is not to be used as a capture trigger. */ + if (!(((TIMER_MODE_16_BIT_COUNTER == R_TML->ITLCTL0_b.MD) && + (TIMER_MODE_16_BIT_CAPTURE == mode) && + (TML_CAPTURE_TRIGGER_ITLCMP01 != p_cfg_ext->capture_trigger)) || + (R_TML->ITLCC0_b.CAPEN && + (TML_CAPTURE_TRIGGER_ITLCMP01 != R_TML->ITLCC0_b.CTRS) && + (TIMER_MODE_16_BIT_COUNTER == mode)))) + #endif + { + /* Selected mode must be the same for all instance. */ + FSP_ERROR_RETURN(mode == R_TML->ITLCTL0_b.MD, FSP_ERR_INVALID_MODE); + } + } + #endif + + /* Channel selected must be in range 0:3. */ + FSP_ERROR_RETURN((channel_mask & BSP_FEATURE_TML_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Check the maximum range of counter clock source division. */ + FSP_ASSERT(p_cfg->source_div <= BSP_FEATURE_TML_MAX_CLOCK_DIVIDER); + #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + #if !BSP_FEATURE_ELC_VERSION + + /* Triggering capture with ELC event is not supported. */ + FSP_ASSERT(TML_CAPTURE_TRIGGER_EVENT_ELC != + ((tml_extended_cfg_t *) p_cfg->p_extend)->capture_trigger); + #endif + + /* The clock source division must be 0 if 16-bit counter channel use CSEL as clock source. */ + if (R_TML->ITLCC0_b.CAPEN && (TIMER_MODE_16_BIT_COUNTER == mode)) + { + FSP_ASSERT(TIMER_SOURCE_DIV_1 == p_cfg->source_div); + } + #endif + + /* Validate period must be configured in correct range and channel must be selected according to each mode. */ + FSP_ASSERT(1 < p_cfg->period_counts); + + #if TML_CFG_SINGLE_CHANNEL_ENABLE + + /* Selected channel must match the channel selected by TML_CFG_SINGLE_CHANNEL_ENABLE */ + FSP_ERROR_RETURN(0U == p_cfg->channel, FSP_ERR_INVALID_CHANNEL); + #endif + + if (TIMER_MODE_8_BIT_COUNTER == mode) + { + FSP_ASSERT(1 < p_cfg->period_counts); + FSP_ASSERT(p_cfg->period_counts <= (UINT8_MAX + 1)); + } + else if ((TIMER_MODE_16_BIT_COUNTER == mode) || (TIMER_MODE_16_BIT_CAPTURE == mode)) + { + FSP_ASSERT(1 < p_cfg->period_counts); + FSP_ASSERT(p_cfg->period_counts <= (UINT16_MAX + 1)); + if (TIMER_MODE_16_BIT_COUNTER == mode) + { + FSP_ERROR_RETURN((channel_mask & VALID_16_BIT_COUNTER_CHANNEL_MASK), FSP_ERR_INVALID_CHANNEL); + } + + #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + else + { + FSP_ERROR_RETURN((channel_mask & VALID_16_BIT_CAPTURE_CHANNEL_MASK), FSP_ERR_INVALID_CHANNEL); + } + #endif + } + else // TIMER_MODE_32_BIT_COUNTER == mode + { + FSP_ERROR_RETURN((channel_mask & VALID_32_BIT_COUNTER_CHANNEL_MASK), FSP_ERR_INVALID_CHANNEL); + } + + /* Enable IRQ if user supplied a callback function. */ + if (p_cfg->p_callback) + { + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Get the period value for counter channel. + * + * @param[in] p_instance_ctrl Instance control block. + **********************************************************************************************************************/ +uint32_t r_tml_period_counts_get (tml_instance_ctrl_t * const p_instance_ctrl) +{ + uint32_t period_counts = 0; + + /* Get a period value. */ + switch (p_instance_ctrl->p_cfg->mode) + { + case TIMER_MODE_8_BIT_COUNTER: + { + /* The ITLCMP00_L for channel 0 + * The ITLCMP00_H for channel 1 + * The ITLCMP01_L for channel 2 + * The ITLCMP01_H for channel 3 + */ + period_counts = *(&(R_TML->ITLCMP00_L) + TML_PRV_CHANNEL); + break; + } + + case TIMER_MODE_16_BIT_COUNTER: + { + /* Set the ITLCMP0n register (n: 0, 1) */ + period_counts = *(&(R_TML->ITLCMP00) + TML_PRV_CHANNEL / 2); + break; + } + + case TIMER_MODE_32_BIT_COUNTER: + { + /* Get the upper 16-bit period value in the ITLCMP01 register and the lower 16-bit period value + * in the ITLCMP00 register. */ + period_counts = (uint32_t) R_TML->ITLCMP01 << 16; + period_counts |= R_TML->ITLCMP00; + break; + } + +#if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + case TIMER_MODE_16_BIT_CAPTURE: + { + /* Save pointer to extended configuration structure. */ + tml_extended_cfg_t * p_tml_cfg = (tml_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; + + if (TML_CAPTURE_TRIGGER_ITLCMP01 == p_tml_cfg->capture_trigger) + { + /* Get the period value into ITLCMP01 register for channel 2 + 3 */ + period_counts = R_TML->ITLCMP01; + } + + break; + } +#endif + + default: + { + break; + } + } + + return period_counts; +} + +#if TML_CFG_INTERRUPT_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Helper for enabling or disabling interrupts + * + * @param[in] p_ctrl Instance control block. + * @param[in] enable Whether or not to enable disable interrupts. + **********************************************************************************************************************/ +static fsp_err_t r_tml_enable_helper (timer_ctrl_t * const p_ctrl, bool enable) +{ + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) p_ctrl; + #if TML_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(TML_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(TML_PRV_CHANNEL_MASK & BSP_FEATURE_TML_VALID_CHANNEL_MASK, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + #endif + + #if TML_CFG_SINGLE_CHANNEL_ENABLE + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + #endif + + /* Critical section required because ITLMKF0, ITLS0, ITLCTL0 register is shared with other instances. */ + TML_PRV_CRITICAL_SECTION_ENTER(); + + uint8_t itls0 = R_TML->ITLS0; + uint8_t itlmkf0 = R_TML->ITLMKF0; + + /* Clear the ITF0i interrupt status flags for channel used. */ + itls0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + + if (enable) + { + /* Enable the interrupt generation from the selected channel by clearing the mask bits . */ + itlmkf0 &= (uint8_t) ~(TML_PRV_CHANNEL_MASK); + } + else + { + /* Disable the interrupt generation from the selected channel by setting the mask bits . */ + itlmkf0 |= TML_PRV_CHANNEL_MASK; + } + + #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + if (TIMER_MODE_16_BIT_CAPTURE == p_instance_ctrl->p_cfg->mode) + { + /* Clear the ITF0C interrupt status flags. */ + itls0 &= (uint8_t) ~(R_TML_ITLS0_ITF0C_Msk); + + if (enable) + { + /* Disable the MKF0C masks of the ITF0C status flags. */ + itlmkf0 &= (uint8_t) ~(R_TML_ITLMKF0_MKF0C_Msk); + } + else + { + /* Enable the MKF0C masks of the ITF0C status flags. */ + itlmkf0 |= R_TML_ITLMKF0_MKF0C_Msk; + } + } + #endif + + /* Write to registers */ + R_TML->ITLS0 = itls0; + R_TML->ITLMKF0 = itlmkf0; + + TML_PRV_CRITICAL_SECTION_EXIT(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Interrupt triggered by a compare match or capture. + * + * Clears interrupt, disables captures and calls callback if one was provided in the open function. + **********************************************************************************************************************/ +void tml_itl_or_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + #if TML_CFG_SINGLE_CHANNEL_ENABLE + IRQn_Type irq = R_FSP_CurrentIrqGet(); + tml_instance_ctrl_t * p_instance_ctrl = (tml_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + #else + tml_instance_ctrl_t * p_instance_ctrl = gp_tml_ctrls[TML_CHANNEL_0]; + #endif + uint8_t itls0 = R_TML->ITLS0; + uint32_t capture = 0; + timer_event_t event = TIMER_EVENT_CYCLE_END; + + #if TML_CFG_16_BIT_CAPTURE_MODE_ENABLE + if (itls0 & R_TML_ITLS0_ITF0C_Msk) + { + /* Clear the interrupt flag. */ + R_TML->ITLS0 = itls0 & ((uint8_t) ~R_TML_ITLS0_ITF0C_Msk); + + event = TIMER_EVENT_CAPTURE_EDGE; + + /* Get captured value */ + capture = R_TML->ITLCAP00; + } + else + #endif + { + #if !TML_CFG_SINGLE_CHANNEL_ENABLE + + /* Due to the shared IRQ for all of the TML we need to find the stored context from the channel instance. */ + for (tml_channel_t channel = TML_CHANNEL_0; channel < BSP_FEATURE_TML_NUM_CHANNELS; channel++) + { + if (itls0 & (1U << channel)) + { + p_instance_ctrl = gp_tml_ctrls[channel]; + break; + } + } + #endif + + /* Clear the interrupt flag. */ + R_TML->ITLS0 = itls0 & (uint8_t) ~(TML_PRV_CHANNEL_MASK); + } + + /* If a callback is provided, then call it with the captured counter value. */ + if (NULL != p_instance_ctrl->p_callback) + { + timer_callback_args_t args = + { + .p_context = p_instance_ctrl->p_context, + .event = event, + .capture = capture, + }; + + /* Call the callback. */ + p_instance_ctrl->p_callback(&args); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_uarta/r_uarta.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_uarta/r_uarta.c new file mode 100644 index 0000000000..99115be694 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_uarta/r_uarta.c @@ -0,0 +1,1341 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uarta.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef UARTA_CFG_RX_ENABLE + #define UARTA_CFG_RX_ENABLE 1 +#endif +#ifndef UARTA_CFG_TX_ENABLE + #define UARTA_CFG_TX_ENABLE 1 +#endif + +/* "UART" in ASCII. Used to determine if the control block is open. */ +#define UARTA_OPEN (0x55415254) + +/* UARTA parity bit mapping */ +#define UARTA_PARITY_OFF_MAPPING (0U) +#define UARTA_PARITY_ZERO_MAPPING (1U) +#define UARTA_PARITY_ODD_MAPPING (2U) +#define UARTA_PARITY_EVEN_MAPPING (3U) + +#define UARTA_MAX_TRANSFER_BYTES (0x10000) + +/* Number of clock select and divider */ +#define UARTA_UATCK_UATSEL_COUNT (4U) + +/* Mask for valid mapping of uart_clock_div_t to UTA0CK.CK */ +#define UARTA_CLOCK_DIV_MASK (0x07U) + +/* Maximum and minimum BRGCA*/ +#define UARTA_BRGCA_MAX (255) +#define UARTA_BRGCA_MIN (2) + +/* Mask 2 bit for bit UTA0CK.SEL[1:0] */ +#define UARTA_UTA0SEL_MASK (0x03U) + +/* DTC transfer setting information */ +#define UARTA_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS) | \ + (TRANSFER_REPEAT_AREA_DESTINATION << TRANSFER_SETTINGS_REPEAT_AREA_BITS)) +#define UARTA_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS) | \ + (TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS)) + +/* Wait time needs to be rounded up to enable TX/RX. */ +#define UARTA_CONVERT_TO_MICRO_SECOND (999999U) + +#define UARTA_MAX_BAUD_RATE_ERROR_10PPM (4740U) + +/* Scaling factor for baud rate error values, 10ppm or .001% */ +#define UARTA_BAUD_ERROR_SCALING_10PPM (100000) + +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + #define UARTA_MAX_BAUD_RATE (153600) +#endif + +/*********************************************************************************************************************** + * Private constants + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * uarta_prv_ns_callback)(uart_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile uarta_prv_ns_callback)(uart_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_uarta_read_write_param_check(uarta_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + + #if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) +static fsp_err_t r_uarta_operation_clock_validation(uarta_baud_setting_t const * const p_baud_setting); + + #endif + +#endif + +#if UARTA_CFG_DTC_SUPPORT_ENABLE +static fsp_err_t r_uarta_transfer_configure(uarta_instance_ctrl_t * const p_ctrl); +static fsp_err_t r_uarta_transfer_configure_helper(uarta_instance_ctrl_t * p_ctrl, + transfer_instance_t const * p_transfer, + uart_dir_t direction); + +#endif + +static void r_uarta_baud_set(uarta_instance_ctrl_t * p_ctrl, uarta_baud_setting_t const * const p_baud_setting); + +static void r_uarta_call_callback(uarta_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); + +static uint16_t r_uarta_calculate_wait_time(uarta_baud_setting_t const * const p_baud_setting); + +#if (UARTA_CFG_RX_ENABLE) + +void uarta_rxi_isr(void); +void uarta_eri_isr(void); + +#endif + +#if (UARTA_CFG_TX_ENABLE) + +void uarta_txi_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** Look-up table for parity values */ +static const uint8_t uarta_parity_lut[] = +{ + [UART_PARITY_OFF] = UARTA_PARITY_OFF_MAPPING << R_UARTA0_ASIMAn1_PS_Pos, + [UART_PARITY_ZERO] = UARTA_PARITY_ZERO_MAPPING << R_UARTA0_ASIMAn1_PS_Pos, + [UART_PARITY_EVEN] = UARTA_PARITY_EVEN_MAPPING << R_UARTA0_ASIMAn1_PS_Pos, + [UART_PARITY_ODD] = UARTA_PARITY_ODD_MAPPING << R_UARTA0_ASIMAn1_PS_Pos +}; + +/** Look-up table for converting UARTA clock source, used to get the clock value from R_BSP_SourceClockHzGet */ +static fsp_priv_source_clock_t uarta_f_uta0_sel_lut[] = +{ + [UARTA_CLOCK_SOURCE_SOSC_LOCO] = FSP_PRIV_CLOCK_LOCO, + [UARTA_CLOCK_SOURCE_SOSC] = FSP_PRIV_CLOCK_SUBCLOCK, + [UARTA_CLOCK_SOURCE_MOSC] = FSP_PRIV_CLOCK_MAIN_OSC, + [UARTA_CLOCK_SOURCE_HOCO] = FSP_PRIV_CLOCK_HOCO, + [UARTA_CLOCK_SOURCE_MOCO] = FSP_PRIV_CLOCK_MOCO +}; + +#if (UARTA_CFG_RX_ENABLE) + +/** Look-up table for event types */ +static const uint8_t uarta_event_lut[] = +{ + [0] = 0, + [1] = UART_EVENT_ERR_OVERFLOW, + [2] = UART_EVENT_ERR_FRAMING, + [3] = UART_EVENT_ERR_OVERFLOW | UART_EVENT_ERR_FRAMING, + [4] = UART_EVENT_ERR_PARITY, + [5] = UART_EVENT_ERR_PARITY | UART_EVENT_ERR_OVERFLOW, + [6] = UART_EVENT_ERR_PARITY | UART_EVENT_ERR_FRAMING, + [7] = UART_EVENT_ERR_OVERFLOW | UART_EVENT_ERR_FRAMING | UART_EVENT_ERR_PARITY +}; + + #define UARTA_ASISA_RCVR_ERR_MASK (R_UARTA0_ASISAn_OVEA_Msk | R_UARTA0_ASISAn_FEA_Msk | R_UARTA0_ASISAn_PEA_Msk) + +#endif + +/* UART on UARTA HAL API mapping for UART interface */ +const uart_api_t g_uart_on_uarta = +{ + .open = R_UARTA_Open, + .close = R_UARTA_Close, + .write = R_UARTA_Write, + .read = R_UARTA_Read, + .infoGet = R_UARTA_InfoGet, + .baudSet = R_UARTA_BaudSet, + .communicationAbort = R_UARTA_Abort, + .callbackSet = R_UARTA_CallbackSet, + .readStop = R_UARTA_ReadStop, + .receiveSuspend = R_UARTA_ReceiveSuspend, + .receiveResume = R_UARTA_ReceiveResume, +}; + +/*******************************************************************************************************************//** + * @addtogroup UARTA + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UARTA driver based on the input configurations. If transmission/reception is enabled at compile time, + * transmission/reception is enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UARTA control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid clock select (f_UTA0) and baudrate configuration. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_UARTA_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg) +{ + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(((uarta_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting); + FSP_ERROR_RETURN(UARTA_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(((1 << p_cfg->channel) & BSP_PERIPHERAL_UARTA_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) + + /* UARTA0_ERRI interrupt request should be greater than 0 when Receive Error Interrupt Mode is disabled */ + FSP_ASSERT(p_cfg->eri_irq >= 0); + #endif + + #if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + + /* Validate the f_uta before setting the baud rate*/ + FSP_ERROR_RETURN(FSP_SUCCESS == + r_uarta_operation_clock_validation(((uarta_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting), + FSP_ERR_INVALID_ARGUMENT); + #endif +#endif + + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + +#if (BSP_PERIPHERAL_UARTA_CHANNEL_MASK > 1) + + /* Calculate the register base address. */ + uint32_t address_gap = (uint32_t) R_UARTA1 - (uint32_t) R_UARTA0; + p_ctrl->p_reg = (R_UARTA0_Type *) ((uint32_t) R_UARTA0 + (address_gap * p_cfg->channel)); +#else + p_ctrl->p_reg = R_UARTA0; +#endif + +#if UARTA_CFG_DTC_SUPPORT_ENABLE + + /* Configure the transfer interface for transmission and reception if provided. */ + err = r_uarta_transfer_configure(p_ctrl); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Enable the UARTA channel */ + R_BSP_MODULE_START(FSP_IP_UARTA, 0); + + /* Set the UART configuration settings provided in ::uart_cfg_t and :: uarta_extended_cfg_t. */ + uarta_extended_cfg_t * p_extend = (uarta_extended_cfg_t *) p_ctrl->p_cfg->p_extend; + + /* Set the baud rate settings for the internal baud rate generator. */ + r_uarta_baud_set(p_ctrl, p_extend->p_baud_setting); + + /* Setting parity, length, stop, direction, and level bit */ + p_ctrl->p_reg->ASIMAn1 = (uint8_t) (uarta_parity_lut[p_cfg->parity] | + ((uint8_t) (p_cfg->data_bits << R_UARTA0_ASIMAn1_CL_Pos)) | + ((uint8_t) (p_cfg->stop_bits << R_UARTA0_ASIMAn1_SL_Pos)) | + ((uint8_t) (p_extend->transfer_dir << R_UARTA0_ASIMAn1_DIR_Pos)) | + ((uint8_t) (p_extend->transfer_level << R_UARTA0_ASIMAn1_ALV_Pos))); + + /* Setting interrupt for continuous transmission and receive interrupt mode select */ + uint8_t asima0 = (uint8_t) ((R_UARTA0_ASIMAn0_ISSMA_Msk) | + ((uint8_t) (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE << R_UARTA0_ASIMAn0_ISRMA_Pos))); + + /* Configure for register ASIMA0 */ + p_ctrl->p_reg->ASIMAn0 = asima0; + + /* Enables the UARTA operation clock */ + asima0 |= R_UARTA0_ASIMAn0_EN_Msk; + p_ctrl->p_reg->ASIMAn0 = asima0; + +#if (UARTA_CFG_RX_ENABLE) + p_ctrl->rx_dest_bytes = 0; + + /* If reception is enabled at build time, enable reception. */ + asima0 |= R_UARTA0_ASIMAn0_RXEA_Msk; +#endif + +#if (UARTA_CFG_TX_ENABLE) + p_ctrl->tx_src_bytes = 0; + + /* If transmission is enabled at build time, enable transmission. */ + asima0 |= R_UARTA0_ASIMAn0_TXEA_Msk; +#endif + + p_ctrl->p_reg->ASIMAn0 = asima0; + +#if (UARTA_CFG_RX_ENABLE) + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) + R_BSP_IrqCfgEnable(p_cfg->eri_irq, p_cfg->eri_ipl, p_ctrl); + #endif + R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->rxi_ipl, p_ctrl); +#endif + +#if (UARTA_CFG_TX_ENABLE) + + /* Wait for at least one cycle of the UARTA operation clock + * See in hardware manual: UARTA > Register Descriptions > ASIMA00 > Note */ + R_BSP_SoftwareDelay(p_extend->p_baud_setting->delay_time, BSP_DELAY_UNITS_MICROSECONDS); + + R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->txi_ipl, p_ctrl); +#endif + + p_ctrl->open = UARTA_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Removes power. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UARTA control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_UARTA_Close (uart_ctrl_t * const p_api_ctrl) +{ + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; + +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uart_cfg_t const * p_cfg = p_ctrl->p_cfg; + + /* Mark UARTA not open so it can be used again. */ + p_ctrl->open = 0; + + /* Disable receiver, and transmitter. */ + uint8_t current_value = p_ctrl->p_reg->ASIMAn0; + + /* Do read-modify-write for TXEA/RXEA */ + current_value &= (uint8_t) ~(R_UARTA0_ASIMAn0_TXEA_Msk | R_UARTA0_ASIMAn0_RXEA_Msk); + + p_ctrl->p_reg->ASIMAn0 = current_value; + + /* Disable baud clock output. Must be done separately after disabling TX/RX. */ + p_ctrl->p_reg->ASIMAn0 = (uint8_t) (current_value & ~R_UARTA0_ASIMAn0_EN_Msk); + +#if (UARTA_CFG_RX_ENABLE) + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) + R_BSP_IrqDisable(p_cfg->eri_irq); + #endif + + /* If reception is enabled at build time, disable reception irqs. */ + R_BSP_IrqDisable(p_cfg->rxi_irq); +#endif +#if (UARTA_CFG_TX_ENABLE) + + /* If transmission is enabled at build time, disable transmission irqs. */ + R_BSP_IrqDisable(p_cfg->txi_irq); +#endif + +#if UARTA_CFG_DTC_SUPPORT_ENABLE + #if (UARTA_CFG_RX_ENABLE) + transfer_instance_t const * p_transfer_rx = p_cfg->p_transfer_rx; + if (NULL != p_transfer_rx) + { + p_transfer_rx->p_api->close(p_transfer_rx->p_ctrl); + } + #endif + #if (UARTA_CFG_TX_ENABLE) + transfer_instance_t const * p_transfer_tx = p_cfg->p_transfer_tx; + if (NULL != p_transfer_tx) + { + p_transfer_tx->p_api->close(p_transfer_tx->p_ctrl); + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UARTA control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @retval FSP_ERR_UNSUPPORTED UARTA_CFG_RX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + **********************************************************************************************************************/ +fsp_err_t R_UARTA_Read (uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ +#if (UARTA_CFG_RX_ENABLE) + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + + #if (UARTA_CFG_PARAM_CHECKING_ENABLE) + err = r_uarta_read_write_param_check(p_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->rx_dest_bytes, FSP_ERR_IN_USE); + #endif + + #if UARTA_CFG_DTC_SUPPORT_ENABLE + transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + + /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ + if (NULL != p_transfer_rx) + { + err = p_transfer_rx->p_api->reset(p_transfer_rx->p_ctrl, NULL, (void *) p_dest, (uint16_t) bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Save the destination address and size for use in rxi_isr. */ + p_ctrl->p_rx_dest = p_dest; + p_ctrl->rx_dest_bytes = bytes; + + return err; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UARTA control block is NULL. + * Number of transfers outside the max or min boundary when transfer instance used + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UARTA transmission is in progress + * @retval FSP_ERR_UNSUPPORTED UART_CFG_TX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reset + * + **********************************************************************************************************************/ +fsp_err_t R_UARTA_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ +#if (UARTA_CFG_TX_ENABLE) + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; + #if UARTA_CFG_PARAM_CHECKING_ENABLE || UARTA_CFG_DTC_SUPPORT_ENABLE + fsp_err_t err = FSP_SUCCESS; + #endif + + #if (UARTA_CFG_PARAM_CHECKING_ENABLE) + err = r_uarta_read_write_param_check(p_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_ctrl->tx_src_bytes, FSP_ERR_IN_USE); + #endif + + /* Disable transmit interrupt */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + + /* The first data will be assigned to TXBA0, Get the next value for the next transmit */ + p_ctrl->p_tx_src = p_src + 1; + uint32_t num_transfers = bytes - 1; + + #if UARTA_CFG_DTC_SUPPORT_ENABLE + + /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested + * data. */ + transfer_instance_t const * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if ((NULL != p_transfer_tx) && (num_transfers)) + { + #if (UARTA_CFG_PARAM_CHECKING_ENABLE) + + /* Check that the number of transfers is within the 16-bit limit. */ + FSP_ASSERT(num_transfers <= UARTA_MAX_TRANSFER_BYTES); + #endif + + err = p_transfer_tx->p_api->reset(p_transfer_tx->p_ctrl, + (void const *) p_ctrl->p_tx_src, + NULL, + (uint16_t) num_transfers); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + p_ctrl->tx_src_bytes = num_transfers; + p_ctrl->p_reg->ASIMAn0_b.ISSMA = 1; + + /* Enable transmit interrupt */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + + /* Assign to first byte */ + p_ctrl->p_reg->TXBAn = *(p_src); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_UARTA_CallbackSet (uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; +#if UARTA_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if UARTA_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + uart_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(uart_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a uarta_baud_setting_t + * structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UARTA control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid clock select (f_UTA0) and baudrate configuration. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_UARTA_BaudSet (uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting) +{ + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; + +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + FSP_ERROR_RETURN(FSP_SUCCESS == + r_uarta_operation_clock_validation(p_baud_setting), + FSP_ERR_INVALID_ARGUMENT); + #endif +#endif + + /* Disable transmit interrupt. Resuming transmission after reconfiguring baud settings is + * not supported. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + + uint8_t preserved_asiman0 = p_ctrl->p_reg->ASIMAn0; + + /* Modify the BRGCAn bits while the TXEAn and RXEAn bits are 0 (in the transmission/reception stopped state).*/ + p_ctrl->p_reg->ASIMAn0 = (preserved_asiman0 & (uint8_t) (~(R_UARTA0_ASIMAn0_RXEA_Msk | R_UARTA0_ASIMAn0_TXEA_Msk))); + + /* Apply new baud rate register settings. */ + r_uarta_baud_set(p_ctrl, p_baud_setting); + + /* To enable transmission or reception again, set the TXEAn or RXEAn bit to 1 at least two cycles of the UARTAn + * operation clock after clearing the TXEAn or RXEAn bit to 0 + * See in hardware manual: UARTA > Register Descriptions > ASIMA00 > Note */ + uint16_t delay_time = r_uarta_calculate_wait_time(p_baud_setting); + R_BSP_SoftwareDelay((uint32_t) delay_time << 1U, BSP_DELAY_UNITS_MICROSECONDS); + + /* Restore all settings. */ + p_ctrl->p_reg->ASIMAn0 = preserved_asiman0; +#if (UARTA_CFG_TX_ENABLE) + + /* If transmission is enabled at build time, enable transmission. */ + if (preserved_asiman0 & R_UARTA0_ASIMAn0_TXEA_Msk) + { + /* Wait for at least one cycle of the UARTA operation clock + * See in hardware manual: UARTA > Register Descriptions > ASIMA00 > Note */ + R_BSP_SoftwareDelay((uint32_t) delay_time, BSP_DELAY_UNITS_MICROSECONDS); + } +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_UARTA_InfoGet (uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info) +{ +#if UARTA_CFG_PARAM_CHECKING_ENABLE + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_info); + FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + p_info->read_bytes_max = UARTA_MAX_TRANSFER_BYTES; + p_info->write_bytes_max = UARTA_MAX_TRANSFER_BYTES; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UARTA transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UARTA control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_UARTA_Abort (uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort) +{ +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) || (UARTA_CFG_TX_ENABLE) || (UARTA_CFG_RX_ENABLE) + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; +#endif + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (UARTA_CFG_TX_ENABLE) + if (UART_DIR_TX & communication_to_abort) + { + err = FSP_SUCCESS; + + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + + #if UARTA_CFG_DTC_SUPPORT_ENABLE + transfer_instance_t const * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + if (NULL != p_transfer_tx) + { + err = p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + p_ctrl->tx_src_bytes = 0; + } +#endif + +#if (UARTA_CFG_RX_ENABLE) + if (UART_DIR_RX & communication_to_abort) + { + err = FSP_SUCCESS; + + #if UARTA_CFG_DTC_SUPPORT_ENABLE + transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if (NULL != p_transfer_rx) + { + err = p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); + } + #endif + p_ctrl->rx_dest_bytes = 0U; + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UARTA transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UARTA control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_UARTA_ReadStop (uart_ctrl_t * const p_api_ctrl, uint32_t * p_remaining_bytes) +{ +#if (UARTA_CFG_RX_ENABLE) + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) p_api_ctrl; + + #if (UARTA_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + uint32_t remaining_bytes = p_ctrl->rx_dest_bytes; + p_ctrl->rx_dest_bytes = 0; + + #if UARTA_CFG_DTC_SUPPORT_ENABLE + transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + if (NULL != p_transfer_rx) + { + fsp_err_t err = p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + transfer_properties_t transfer_info; + err = p_transfer_rx->p_api->infoGet(p_transfer_rx->p_ctrl, &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + remaining_bytes = transfer_info.transfer_length_remaining; + } + #endif + + *p_remaining_bytes = remaining_bytes; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_remaining_bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. + * + * @param[in] baudrate Baud rate [bps]. For example, 19200, 57600, 115200, etc. + * @param[in] baud_rate_percent_error_x1000 Max baud rate error. At most baud_rate_percent_error x 1000 required + * for module to function. Absolute max baud_rate_error is 4740 (4.74%). + * @param[in] clock_source Clock Source. Required for module to generate baudrate. The clock sources + * can be select include UARTA_CLOCK_SOURCE_MOSC, UARTA_CLOCK_SOURCE_HOCO, + * UARTA_CLOCK_SOURCE_MOCO, UARTA_CLOCK_SOURCE_SOSC_LOCO. + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is set successfully + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Argument is out of available range, baud rate is '0'. + * @retval FSP_ERR_INVALID_RATE Baud rate error is outside the range or the baud rate could not be set given + * the current clock source. + **********************************************************************************************************************/ +fsp_err_t R_UARTA_BaudCalculate (uint32_t baudrate, + uint32_t baud_rate_percent_error_x1000, + uarta_clock_source_t clock_source, + uarta_baud_setting_t * const p_baud_setting) +{ +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN(UARTA_MAX_BAUD_RATE_ERROR_10PPM >= baud_rate_percent_error_x1000, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(UARTA_MAX_BAUD_RATE >= baudrate, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != baudrate), FSP_ERR_INVALID_ARGUMENT); +#endif + + fsp_err_t ret = FSP_ERR_INVALID_RATE; + + /* UARTA_MAX_BAUD_RATE * UARTA_MAX_BAUD_RATE_ERROR_10PPM < UINT32_MAX */ + uint32_t delta_max = baudrate * baud_rate_percent_error_x1000 / UARTA_BAUD_ERROR_SCALING_10PPM; + + uint32_t clock_source_value = R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[clock_source]); + +#if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + uint32_t pclk_constraint = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); +#endif + + /* Go ahead and set the clock source here. It stays constant through the baud rate search. */ + p_baud_setting->utanck_clock_b.utasel = (uint8_t) (clock_source & UARTA_UTA0SEL_MASK); + + for (uarta_clock_div_t f_uta0_div = UARTA_CLOCK_DIV_1; f_uta0_div < UARTA_CLOCK_DIV_COUNT; f_uta0_div++) + { + /* Calculate UARTA operation clock (f_UTA0)*/ + uint32_t f_uta0_value = clock_source_value >> f_uta0_div; + + /* Find the appropriate divider for the requested baud rate. + * divider = round(f_UTA0 / (2 * Desired baud rate)) + * Integer round to the nearest divider. + */ + uint32_t divider = ((f_uta0_value + baudrate) >> 1) / baudrate; + if ((divider >= UARTA_BRGCA_MIN) && (divider <= UARTA_BRGCA_MAX) +#if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + && (f_uta0_value <= pclk_constraint) +#endif + ) + { + /* Calculate actual baudrate using the divider. */ + uint32_t actual_baudrate = (f_uta0_value >> 1) / divider; + uint32_t delta = baudrate >= + actual_baudrate ? (baudrate - actual_baudrate) : (actual_baudrate - baudrate); + if (delta < delta_max) + { + delta_max = delta; + p_baud_setting->brgca = (uint8_t) divider; + p_baud_setting->utanck_clock_b.utanck = (uint8_t) (f_uta0_div & R_UARTA_CK_UTAnCK_CK_Msk); + ret = FSP_SUCCESS; + } + } + + if (UARTA_CLOCK_SOURCE_LOCO == clock_source) + { + p_baud_setting->utanck_clock_b.utanck = UARTA_UTAnCK_LOCO_SETTING; + break; + } + +#if (!BSP_FEATURE_BSP_HAS_FSXP_CLOCK) + if (UARTA_CLOCK_SOURCE_SOSC == clock_source) + { + p_baud_setting->utanck_clock_b.utanck = UARTA_UTAnCK_SOSC_SETTING; + break; + } +#endif + } + + return ret; +} + +/*******************************************************************************************************************//** + * Suspend Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_UARTA_ReceiveSuspend (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Resume Reception + * + * @retval FSP_ERR_UNSUPPORTED Functionality not supported by this driver instance + **********************************************************************************************************************/ +fsp_err_t R_UARTA_ReceiveResume (uart_ctrl_t * const p_api_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup UARTA) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer to UARTA control block or configuration structure is NULL + **********************************************************************************************************************/ +static fsp_err_t r_uarta_read_write_param_check (uarta_instance_ctrl_t const * const p_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_ctrl); + FSP_ASSERT(addr); + FSP_ASSERT(0U != bytes); + FSP_ASSERT(UARTA_MAX_TRANSFER_BYTES >= bytes); + FSP_ERROR_RETURN(UARTA_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + + return FSP_SUCCESS; +} + +#endif + +#if UARTA_CFG_DTC_SUPPORT_ENABLE + +/*******************************************************************************************************************//** + * Subroutine to apply common UARTA transfer settings. + * + * @param[in] p_ctrl Pointer to instance control block. + * + * @retval FSP_SUCCESS UARTA transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer + **********************************************************************************************************************/ +static fsp_err_t r_uarta_transfer_configure (uarta_instance_ctrl_t * const p_ctrl) +{ + fsp_err_t err = FSP_SUCCESS; + + #if (UARTA_CFG_RX_ENABLE) + transfer_instance_t const * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx; + + /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ + err = r_uarta_transfer_configure_helper(p_ctrl, p_transfer_rx, UART_DIR_RX); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + #endif + + #if (UARTA_CFG_TX_ENABLE) + transfer_instance_t const * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx; + + /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ + err = r_uarta_transfer_configure_helper(p_ctrl, p_transfer_tx, UART_DIR_TX); + #if (UARTA_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_transfer_rx)) + { + p_transfer_rx->p_api->close(p_transfer_rx->p_ctrl); + } + #endif + #endif + + return err; +} + +/*******************************************************************************************************************//** + * This function initializes transfer descriptor + * + * @param[in] p_transfer Pointer to transfer instance. + * @param[in] direction UART_DIR_TX or UART_DIR_RX. + **********************************************************************************************************************/ +static fsp_err_t r_uarta_transfer_configure_helper (uarta_instance_ctrl_t * const p_ctrl, + transfer_instance_t const * p_transfer, + uart_dir_t direction) +{ + fsp_err_t err = FSP_SUCCESS; + + if (NULL != p_transfer) + { + /* Configure the transfer instance, if enabled. */ + #if (UARTA_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_ctrl); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend); + #endif + + transfer_info_t * p_info = p_transfer->p_cfg->p_info; + + /* Casting for compatibility with 5, 7 or 8 bit mode. */ + if (UART_DIR_RX == direction) + { + p_info->transfer_settings_word = UARTA_DTC_RX_TRANSFER_SETTINGS; + p_info->p_src = (void *) &(p_ctrl->p_reg->RXBAn); + } + else + { + p_info->transfer_settings_word = UARTA_DTC_TX_TRANSFER_SETTINGS; + p_info->p_dest = (void *) &(p_ctrl->p_reg->TXBAn); + } + + err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + } + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Changes baud rate based on predetermined register settings. + * + * @param[in] p_ctrl Pointer to instance control block. + * @param[in] p_baud_setting Pointer to other divisor related settings + * + * @note The transmitter and receiver (TXEA and RXEA bits in ASIMA00) must be disabled prior to calling this function. + **********************************************************************************************************************/ +static void r_uarta_baud_set (uarta_instance_ctrl_t * p_ctrl, uarta_baud_setting_t const * const p_baud_setting) +{ + /* Set BRGCA register value. */ + p_ctrl->p_reg->BRGCAn = p_baud_setting->brgca; + uint8_t utack_value = p_baud_setting->utanck_clock; + +#if (BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT) + + /* Set the UART configuration settings provided in ::uart_cfg_t and :: uarta_extended_cfg_t. */ + utack_value |= (uint8_t) (((uarta_extended_cfg_t *) p_ctrl->p_cfg->p_extend)->clock_output << + R_UARTA_CK_UTAnCK_EN_Pos); +#endif + + /* Set UTA0CK/UTA1CK register value. */ + R_UARTA_CK->UTAnCK[p_ctrl->p_cfg->channel] = utack_value; + +#if (BSP_PERIPHERAL_UARTA_CHANNEL_MASK > 1) + + /* Set fSEL clock select */ + R_UARTA_CK->UTAnCK_b[0].SEL = p_baud_setting->utanck_clock_b.utasel; +#endif +} + +#if (UARTA_CFG_PARAM_CHECKING_ENABLE) + #if (BSP_FEATURE_UARTA_PCLK_RESTRICTION) + +/*******************************************************************************************************************//** + * Validates the baud rate divisor for the given UARTA clock frequency against PCLK constraints. + * + * This function checks if the UARTA operation clock (derived from the frequency settings of the baud rate generator) + * is within acceptable limits as defined by the PCLK. + * + * @param[in] p_baud_setting Pointer to the baud rate settings structure which includes the UARTA clock selection. + * @retval FSP_SUCCESS The UARTA operation clock is within acceptable limits. + * @retval FSP_ERR_INVALID_ARGUMENT The UARTA operation clock exceeds PCLK constraints. + **********************************************************************************************************************/ +static fsp_err_t r_uarta_operation_clock_validation (uarta_baud_setting_t const * const p_baud_setting) +{ + /* Retrieve the PCLKB constraint and operation clock uarta value */ + uint32_t pclk_constraint = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + uint32_t clock_source_value = R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[p_baud_setting->utanck_clock_b.utasel]); + uint32_t f_uta = clock_source_value >> (p_baud_setting->utanck_clock_b.utanck & UARTA_CLOCK_DIV_MASK); + + /* Check if UARTA operation clock exceeds the PCLK constraint */ + if (f_uta > pclk_constraint) + { + return FSP_ERR_INVALID_ARGUMENT; + } + + return FSP_SUCCESS; +} + + #endif +#endif + +/*******************************************************************************************************************//** + * This function calculates the wait time to enable TX + * + * @param[in] p_baud_setting Pointer to baud rate settings. + **********************************************************************************************************************/ +static uint16_t r_uarta_calculate_wait_time (uarta_baud_setting_t const * const p_baud_setting) +{ + uint8_t utanck = p_baud_setting->utanck_clock_b.utanck; + uint8_t utasel = p_baud_setting->utanck_clock_b.utasel; + + /* Get UARTA clock divider shift. + * Anything outside UARTA_CLOCK_DIV_MASK is not a valid divider and is probably LOCO/SOSC selection instead. + */ + uint32_t divider_shift = (uint32_t) (utanck & UARTA_CLOCK_DIV_MASK); + + /* Calculate frequency UARTA0 operation clock */ + uint32_t f_uta0 = (R_BSP_SourceClockHzGet(uarta_f_uta0_sel_lut[utasel]) >> divider_shift); + + /* Round up especially for the use case f_uta0 > UARTA_CONVERT_TO_MICRO_SECOND */ + return (uint16_t) ((UARTA_CONVERT_TO_MICRO_SECOND + f_uta0) / f_uta0); +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to UARTA instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_uarta_call_callback (uarta_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) +{ + if (NULL != p_ctrl->p_callback) + { + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + uart_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + uarta_prv_ns_callback p_callback = (uarta_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } + } +} + +#if (UARTA_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TXI interrupt processing for UART mode. TXI interrupt fires when: + * - The data in the data register has been transferred to the data shift register, and the next data can be + * written (ISSMAn = 1). This interrupt writes the next data. After the last data byte is written, set ISSMAn = 0. + * - After the last byte is transmitted on the TX pin (ISSMAn = 0). The user callback function is called with + * the UART_EVENT_TX_COMPLETE event code (if it is registered in R_UARTA_Open()). + **********************************************************************************************************************/ +void uarta_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + #endif + + /* Recover ISR context saved in open. */ + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if (0U < p_ctrl->tx_src_bytes) + { + #if UARTA_CFG_DTC_SUPPORT_ENABLE + if (NULL == p_ctrl->p_cfg->p_transfer_tx) + #endif + { + /* Write 1byte (uint8_t) data to (uint8_t) data register */ + p_ctrl->p_reg->TXBAn = *(p_ctrl->p_tx_src); + + /* Update pointer to the next data and number of remaining bytes in the control block. */ + p_ctrl->tx_src_bytes -= 1U; + p_ctrl->p_tx_src += 1U; + } + + #if UARTA_CFG_DTC_SUPPORT_ENABLE + else + { + p_ctrl->tx_src_bytes = 0; + } + #endif + } + else if (0U != (p_ctrl->p_reg->ASIMAn0 & R_UARTA0_ASIMAn0_ISSMA_Msk)) + { + p_ctrl->p_reg->ASIMAn0_b.ISSMA = 0U; + } + else if (0 == p_ctrl->tx_src_bytes) + { + r_uarta_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); + } + else + { + /* Do nothing */ + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +#endif + +#if (UARTA_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * RXI interrupt processing for UART mode. RXI interrupt happens when data arrives to the data register or the + * register. This function calls callback function when it meets conditions below. + * - UART_EVENT_RX_COMPLETE: The number of data which has been read reaches to the number specified in R_UARTA_Read() + * if a transfer instance is used for reception. + * - UART_EVENT_RX_CHAR: Data is received asynchronously (read has not been called) + * + * @retval none + **********************************************************************************************************************/ +void uarta_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + #endif + + /* Recover ISR context saved in open. */ + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + #if UARTA_CFG_DTC_SUPPORT_ENABLE + if ((p_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_ctrl->rx_dest_bytes)) + #endif + { + uint8_t data = p_ctrl->p_reg->RXBAn; + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE != 0) + + /* Determine cause of error. */ + uint8_t err_type = p_ctrl->p_reg->ASISAn; + + /* Clear error condition. */ + p_ctrl->p_reg->ASCTAn = UARTA_ASISA_RCVR_ERR_MASK; + + err_type &= (uint8_t) UARTA_ASISA_RCVR_ERR_MASK; + err_type = uarta_event_lut[err_type]; + if (err_type) + { + r_uarta_call_callback(p_ctrl, data, (uart_event_t) err_type); + } + else + #endif + { + if (0 == p_ctrl->rx_dest_bytes) + { + /* Call user callback with the data. */ + r_uarta_call_callback(p_ctrl, (uint32_t) data, UART_EVENT_RX_CHAR); + } + else + { + *(p_ctrl->p_rx_dest) = data; + p_ctrl->p_rx_dest += 1; + p_ctrl->rx_dest_bytes -= 1; + + if (0 == p_ctrl->rx_dest_bytes) + { + r_uarta_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + } + } + + #if UARTA_CFG_DTC_SUPPORT_ENABLE + else + { + p_ctrl->rx_dest_bytes = 0; + r_uarta_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + #endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * ERI interrupt processing for UARTA mode. When an ERI interrupt fires, the user callback function is called if it is + * registered in R_UARTA_Open() with the event code that triggered the interrupt. + **********************************************************************************************************************/ +void uarta_eri_isr (void) +{ + #if (UARTA_CFG_RECEIVE_ERROR_INTERRUPT_MODE == 0) + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + uarta_instance_ctrl_t * p_ctrl = (uarta_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint8_t data = p_ctrl->p_reg->RXBAn; + + uint8_t err_type = p_ctrl->p_reg->ASISAn; + + /* Clear error condition. */ + p_ctrl->p_reg->ASCTAn = UARTA_ASISA_RCVR_ERR_MASK; + + err_type &= (uint8_t) UARTA_ASISA_RCVR_ERR_MASK; + err_type = uarta_event_lut[err_type]; + r_uarta_call_callback(p_ctrl, data, (uart_event_t) err_type); + + #if (BSP_FEATURE_ICU_HAS_IELSR) + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + #endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + #endif +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ulpt/r_ulpt.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ulpt/r_ulpt.c new file mode 100644 index 0000000000..9a0dca3f72 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_ulpt/r_ulpt.c @@ -0,0 +1,909 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ulpt.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "ULPT" in ASCII, used to determine if channel is open. */ +#define ULPT_OPEN (0x554C5054ULL) + +#define ULPT_PRV_ULPTCR_STATUS_FLAGS (0xE0U) +#define ULPT_PRV_ULPTCMSR_VALID_BITS (0x77U) + +#define ULPT_PRV_ULPTCR_START_TIMER (0xE1U) +#define ULPT_PRV_ULPTCR_STOP_TIMER (0xE0U) +#define ULPT_PRV_ULPTCR_FORCE_STOP_TIMER (0xE4U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * ulpt_prv_ns_callback)(timer_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile ulpt_prv_ns_callback)(timer_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static fsp_err_t r_ulpt_common_preamble(ulpt_instance_ctrl_t * p_instance_ctrl); + +static void r_ulpt_hardware_cfg(ulpt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg); + +static void r_ulpt_period_register_set(ulpt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts); +static uint32_t r_ulpt_clock_frequency_get(R_ULPT0_Type * p_ulpt_regs); + +#if ULPT_CFG_PARAM_CHECKING_ENABLE +static fsp_err_t r_ulpt_open_param_checking(ulpt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg); + +#endif + +/* ISRs. */ +void ulpt_int_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/** ULPT implementation of General Timer Driver. */ +const timer_api_t g_timer_on_ulpt = +{ + .open = R_ULPT_Open, + .stop = R_ULPT_Stop, + .start = R_ULPT_Start, + .reset = R_ULPT_Reset, + .enable = R_ULPT_Enable, + .disable = R_ULPT_Disable, + .periodSet = R_ULPT_PeriodSet, + .dutyCycleSet = R_ULPT_DutyCycleSet, + .compareMatchSet = R_ULPT_CompareMatchSet, + .infoGet = R_ULPT_InfoGet, + .statusGet = R_ULPT_StatusGet, + .callbackSet = R_ULPT_CallbackSet, + .close = R_ULPT_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup ULPT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes the ULPT module instance. Implements @ref timer_api_t::open. + * + * The ULPT implementation of the general timer can accept an optional ulpt_extended_cfg_t extension parameter. For + * ULPT, the extension specifies the clock to be used as timer source and the output pin configurations. If the + * extension parameter is not specified (NULL), the default clock LOCO is used and the output pins are disabled. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_Open + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the period is not in the valid range of + * 1 to 0xFFFF. + * @retval FSP_ERR_ALREADY_OPEN R_ULPT_Open has already been called for this p_ctrl. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt has not been enabled in the vector table. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel number is not available on ULPT. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; + +#if ULPT_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_ulpt_open_param_checking(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + uint32_t base_address = (uint32_t) R_ULPT0_BASE + + (p_cfg->channel * ((uint32_t) R_ULPT1_BASE - (uint32_t) R_ULPT0_BASE)); + p_instance_ctrl->p_reg = (R_ULPT0_Type *) base_address; + + p_instance_ctrl->p_cfg = p_cfg; + + /* Power on the ULPT channel. */ + R_BSP_MODULE_START(FSP_IP_ULPT, p_cfg->channel); + + /* Clear ULPTCR. This stops the timer if it is running and clears the flags. */ + p_instance_ctrl->p_reg->ULPTCR = 0U; + + /* The timer is stopped in sync with the count source. */ + FSP_HARDWARE_REGISTER_WAIT(0U, p_instance_ctrl->p_reg->ULPTCR_b.TCSTF); + + /* Clear ULPTMR2 before ULPTMR1 to prevent clock destablization if the mode is changed. */ + p_instance_ctrl->p_reg->ULPTMR2 = 0U; + + /* Set count source and divider and configure pins. */ + r_ulpt_hardware_cfg(p_instance_ctrl, p_cfg); + + /* Set period register and update duty cycle if output mode is used. */ + r_ulpt_period_register_set(p_instance_ctrl, p_cfg->period_counts); + + if (p_cfg->cycle_end_irq >= 0) + { + R_BSP_IrqCfgEnable(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); + } + + /* Set callback and context pointers */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + p_instance_ctrl->open = ULPT_OPEN; + + /* All done. */ + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Starts timer. Implements @ref timer_api_t::start. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_Start + * + * @retval FSP_SUCCESS Timer started. + * @retval FSP_ERR_ASSERTION p_ctrl is null. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_Start (timer_ctrl_t * const p_ctrl) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Start timer */ + p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_START_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops the timer. Implements @ref timer_api_t::stop. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_Stop + * + * @retval FSP_SUCCESS Timer stopped. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_Stop (timer_ctrl_t * const p_ctrl) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Stop timer */ + p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_STOP_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets the counter value to the period minus one. Implements @ref timer_api_t::reset. + * + * @retval FSP_SUCCESS Counter reset. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_Reset (timer_ctrl_t * const p_ctrl) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Reset counter to period minus one. */ + p_instance_ctrl->p_reg->ULPTCNT = p_instance_ctrl->period - 1U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_Enable + * + * @retval FSP_SUCCESS External events successfully enabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_Enable (timer_ctrl_t * const p_ctrl) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; +#if ULPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ULPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Reset counter to period minus one. */ + p_instance_ctrl->p_reg->ULPTCNT = p_instance_ctrl->period - 1U; + + /* Enable captures. */ + p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_START_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_Disable + * + * @retval FSP_SUCCESS External events successfully disabled. + * @retval FSP_ERR_ASSERTION p_ctrl was NULL. + * @retval FSP_ERR_NOT_OPEN The instance is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_Disable (timer_ctrl_t * const p_ctrl) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; +#if ULPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ULPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Disable captures. */ + p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_STOP_TIMER; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates period. The new period is updated immediately and the counter is reset to the maximum value. Implements + * @ref timer_api_t::periodSet. + * + * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register. + * If this function is called while the timer is running and an AGT underflow occurs during processing, the duty cycle + * will not be the desired 50% duty cycle until the counter underflow after processing completes. + * + * @warning Stop the timer before calling this function if one-shot output is used. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_PeriodSet + * + * @retval FSP_SUCCESS Period value updated. + * @retval FSP_ERR_ASSERTION A required pointer was NULL, or the period was not in the valid range of + * 1 to 0xFFFF. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; +#if ULPT_CFG_PARAM_CHECKING_ENABLE + + /* Validate period parameter. */ + FSP_ASSERT(0U != period_counts); +#endif + + fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Set period. */ + r_ulpt_period_register_set(p_instance_ctrl, period_counts); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates duty cycle. If the timer is counting, the new duty cycle is reflected after the next counter underflow. + * Implements @ref timer_api_t::dutyCycleSet. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_DutyCycleSet + * + * @retval FSP_SUCCESS Duty cycle updated. + * @retval FSP_ERR_ASSERTION A required pointer was NULL, or the pin was not ULPT_ULPTO_ULPTOA or ULPT_ULPTO_ULPTOB. + * @retval FSP_ERR_INVALID_ARGUMENT Duty cycle was not in the valid range of 0 to period (counts) - 1 + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + * @retval FSP_ERR_UNSUPPORTED ULPT_CFG_OUTPUT_SUPPORT_ENABLE is 0. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) +{ +#if ULPT_CFG_OUTPUT_SUPPORT_ENABLE + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; + #if ULPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT((pin == ULPT_OUTPUT_PIN_ULPTOA) || (pin == ULPT_OUTPUT_PIN_ULPTOB)); + #endif + + fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if ULPT_CFG_PARAM_CHECKING_ENABLE + if (0U != p_instance_ctrl->period) + { + FSP_ERROR_RETURN(duty_cycle_counts < (p_instance_ctrl->period), FSP_ERR_INVALID_ARGUMENT); + } + #endif + + uint32_t temp_duty_cycle_counts = duty_cycle_counts; + uint32_t ulptcmsr_ulptoab_start_level_bit = 1U << 2 << (4 * pin); /* polarity set*/ + ulpt_extended_cfg_t const * p_extend = (ulpt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend; + if (p_extend->ulptoab_settings & ulptcmsr_ulptoab_start_level_bit) + { + /* Invert duty cycle if this pin starts high since the high portion is at the beginning of the cycle. */ + temp_duty_cycle_counts = p_instance_ctrl->period - temp_duty_cycle_counts - 1; + } + + /* Set duty cycle. */ + volatile uint32_t * const p_ulptcm = &p_instance_ctrl->p_reg->ULPTCMA; + p_ulptcm[pin] = temp_duty_cycle_counts; + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(duty_cycle_counts); + FSP_PARAMETER_NOT_USED(pin); + + FSP_RETURN(FSP_ERR_UNSUPPORTED); +#endif +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported compareMatch function. Implements @ref timer_api_t::compareMatchSet. + * + * @retval FSP_ERR_UNSUPPORTED ULPT compare match is not supported. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_CompareMatchSet (timer_ctrl_t * const p_ctrl, + uint32_t const compare_match_value, + timer_compare_match_t const match_channel) +{ + /* This function isn't supported. It is defined only to implement a required function of timer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(compare_match_value); + FSP_PARAMETER_NOT_USED(match_channel); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Gets timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_InfoGet + * + * @retval FSP_SUCCESS Period, count direction, and frequency stored in p_info. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; +#if ULPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_info); +#endif + + fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Get and store period */ + p_info->period_counts = p_instance_ctrl->period; + + /* Get and store clock frequency */ + /* ulpt_extended_cfg_t const * p_extend = (ulpt_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;*/ + p_info->clock_frequency = r_ulpt_clock_frequency_get(p_instance_ctrl->p_reg); + + /* ULPT supports only counting down direction */ + p_info->count_direction = TIMER_DIRECTION_DOWN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Retrieves the current state and counter value stores them in p_status. Implements @ref timer_api_t::statusGet. + * + * Example: + * @snippet r_ulpt_example.c R_ULPT_StatusGet + * + * @retval FSP_SUCCESS Current status and counter value provided in p_status. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; + +#if ULPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_status); +#endif + + fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Read the state. */ + p_status->state = (timer_state_t) p_instance_ctrl->p_reg->ULPTCR_b.TCSTF; + + /* Read counter value */ + p_status->counter = p_instance_ctrl->p_reg->ULPTCNT; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + ulpt_instance_ctrl_t * p_ctrl = (ulpt_instance_ctrl_t *) p_api_ctrl; + +#if ULPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(ULPT_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if ULPT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(timer_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Stops counter, disables interrupts, disables output pins, and clears internal driver data. Implements + * @ref timer_api_t::close. + * + * + * + * @retval FSP_SUCCESS Timer closed. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +fsp_err_t R_ULPT_Close (timer_ctrl_t * const p_ctrl) +{ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) p_ctrl; + + fsp_err_t err = r_ulpt_common_preamble(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Cleanup the device: Stop counter, disable interrupts, and power down if no other channels are in use. */ + + /* Stop timer */ + p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_FORCE_STOP_TIMER; + + /* Clear ULPT output. */ + p_instance_ctrl->p_reg->ULPTIOC = 0U; + + if (FSP_INVALID_VECTOR != p_instance_ctrl->p_cfg->cycle_end_irq) + { + NVIC_DisableIRQ(p_instance_ctrl->p_cfg->cycle_end_irq); + R_FSP_IsrContextSet(p_instance_ctrl->p_cfg->cycle_end_irq, p_instance_ctrl); + } + + p_instance_ctrl->open = 0U; + + return FSP_SUCCESS; +} + +/** @} (end addtogroup ULPT) */ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if ULPT_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * Parameter checking for R_ULPT_Open. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * @param[in] p_cfg Configuration structure for this instance + * + * @retval FSP_SUCCESS Initialization was successful and timer has started. + * @retval FSP_ERR_ASSERTION A required input pointer is NULL or an invalid parameter exists. + * @retval FSP_ERR_ALREADY_OPEN R_ULPT_Open has already been called for this p_ctrl. + * @retval FSP_ERR_IRQ_BSP_DISABLED A required interrupt has not been enabled in the vector table. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Requested channel number is not available on ULPT. + **********************************************************************************************************************/ +static fsp_err_t r_ulpt_open_param_checking (ulpt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(ULPT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Validate channel number. */ + FSP_ERROR_RETURN(((1U << p_cfg->channel) & BSP_FEATURE_ULPT_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + /* Enable IRQ if user supplied a callback function, + * or if the timer is a one-shot timer (so the driver is able to + * turn off the timer after one period. */ + if ((NULL != p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode)) + { + /* Return error if IRQ is required and not in the vector table. */ + FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); + } + + ulpt_extended_cfg_t const * p_extend = (ulpt_extended_cfg_t const *) p_cfg->p_extend; + + /* Validate mode specific settings. */ + if ((ULPT_CLOCK_LOCO == p_extend->count_source) || (ULPT_CLOCK_SUBCLOCK == p_extend->count_source)) + { + /* Timer mode */ + + /* Validate the divider. */ + FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_128); + + /* Count enable,start,amd restart functions are not allowed in timer mode. */ + FSP_ASSERT(p_extend->enable_function != ULPT_ENABLE_FUNCTION_ENABLE_LOW); + FSP_ASSERT(p_extend->enable_function != ULPT_ENABLE_FUNCTION_ENABLE_HIGH); + FSP_ASSERT(p_extend->enable_function != ULPT_ENABLE_FUNCTION_START); + FSP_ASSERT(p_extend->enable_function != ULPT_ENABLE_FUNCTION_RESTART); + } + else + { + /* Event counter mode */ + /* No Divider allowed. */ + FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_1); + } + + return FSP_SUCCESS; +} + +#endif + +/*******************************************************************************************************************//** + * Common code at the beginning of all ULPT functions except open. + * + * @param[in] p_instance_ctrl Pointer to instance control structure. + * + * @retval FSP_SUCCESS No invalid conditions detected, timer state matches expected state. + * @retval FSP_ERR_ASSERTION p_ctrl is null. + * @retval FSP_ERR_NOT_OPEN The instance control structure is not opened. + **********************************************************************************************************************/ +static fsp_err_t r_ulpt_common_preamble (ulpt_instance_ctrl_t * p_instance_ctrl) +{ +#if ULPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(ULPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Ensure timer state reflects expected status. */ + uint32_t ulptcr_tstart = p_instance_ctrl->p_reg->ULPTCR_b.TSTART; + FSP_HARDWARE_REGISTER_WAIT(ulptcr_tstart, p_instance_ctrl->p_reg->ULPTCR_b.TCSTF); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets count source, divider, and other hardware registers. + * + * @note Counter must be stopped before entering this function. + * + * @param[in] p_instance_ctrl Control block for this instance + * @param[in] p_cfg Configuration structure for this instance + **********************************************************************************************************************/ + +static void r_ulpt_hardware_cfg (ulpt_instance_ctrl_t * p_instance_ctrl, timer_cfg_t const * const p_cfg) +{ + ulpt_extended_cfg_t const * p_extend = (ulpt_extended_cfg_t const *) p_cfg->p_extend; + + /* ULPT register locals */ + uint32_t ulptmr1 = 0U; + uint32_t ulptmr2 = 0U; + uint32_t ulptmr3 = 0U; + uint32_t ulptioc = 0U; + uint32_t ulptisr = 0U; + uint32_t ulptcmsr = 0U; + + /* Configure the count source(LOCO or SCK) and mode(event or Timer). */ + ulptmr1 |= p_extend->count_source & (R_ULPT0_ULPTMR1_TMOD1_Msk | R_ULPT0_ULPTMR1_TCK1_Msk); + + if (TIMER_MODE_ONE_SHOT == p_cfg->mode) + { + ulptmr3 |= R_ULPT0_ULPTMR3_TCNTCTL_Msk; + } + + if (p_extend->count_source != ULPT_CLOCK_ULPTEVI) + { + /* Timer mode */ + ulptmr1 &= ~R_ULPT0_ULPTMR1_TMOD1_Msk; + + /* The divider is only used for normal timer operation. */ + ulptmr2 |= p_cfg->source_div & R_ULPT0_ULPTMR2_CKS_Msk; + } + +#if ULPT_CFG_INPUT_SUPPORT_ENABLE + else // (p_extend->count_source == ULPT_CLOCK_ULPTEVI) + { + /* Event counter mode */ + ulptmr1 |= R_ULPT0_ULPTMR1_TMOD1_Msk; + + /* Set the edge selection for for event pin. */ + /* For Falling we set it for rising edge and flip the polarity */ + ulptmr1 |= p_extend->event_pin & R_ULPT0_ULPTMR1_TEDGPL_Msk; + ulptmr3 |= p_extend->event_pin & R_ULPT0_ULPTMR3_TEVPOL_Msk; + + /* Configure input filtering */ + ulptioc |= p_extend->ulptevi_filter & R_ULPT0_ULPTIOC_TIPF_Msk; + + /* Select if the ULPTEE pin should be ignored. */ + ulptioc |= p_extend->enable_function & R_ULPT0_ULPTIOC_TIOGT0_Msk; + + /* Set the active polarity for ULPTEE. This is only set for count enable function. */ + ulptisr |= p_extend->enable_function & R_ULPT0_ULPTISR_RCCPSEL2_Msk; + } +#endif + + /* ULPTEE can be used in either timer or event mode. */ + /* Configure ULPTEE pin function and edge polarity for start or restart functions. */ + ulptmr3 |= p_extend->enable_function & R_ULPT0_ULPTMR3_TEECTL_Msk; + ulptmr3 |= p_extend->trigger_edge & R_ULPT0_ULPTMR3_TEEPOL_Msk; + +#if ULPT_CFG_OUTPUT_SUPPORT_ENABLE + + /* Set output if requested. */ + if (p_extend->ulpto != ULPT_PULSE_PIN_CFG_DISABLED) + { + ulptioc |= R_ULPT0_ULPTIOC_TOE_Msk; + + /* Now set the polarity*/ + if (p_extend->ulpto == ULPT_PULSE_PIN_CFG_ENABLED_START_LEVEL_HIGH) + { + ulptmr3 |= R_ULPT0_ULPTMR3_TOPOL_Msk; + } + else + { + ulptmr3 &= ~R_ULPT0_ULPTMR3_TOPOL_Msk; + } + } + + /* set enable match, output, and polarity of both match outputs*/ + ulptcmsr = p_extend->ulptoab_settings & ULPT_PRV_ULPTCMSR_VALID_BITS; + + /* Set initial duty cycle for PWM mode in open. Duty cycle is set for other modes in r_agt_period_register_set. */ + if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode) + { + uint32_t inverted_duty_cycle = p_instance_ctrl->p_cfg->period_counts - + p_instance_ctrl->p_cfg->duty_cycle_counts - 1; + + /*In this driver match A and match b have the same duty cycle*/ + uint32_t ulptcma = p_instance_ctrl->p_cfg->duty_cycle_counts; + uint32_t ulptcmb = p_instance_ctrl->p_cfg->duty_cycle_counts; + if (ULPT_MATCH_PIN_CFG_DISABLED != p_extend->ulptoab_settings_b.ulptoa) + { + if (ULPT_MATCH_PIN_CFG_START_LEVEL_HIGH == p_extend->ulptoab_settings_b.ulptoa) + { + ulptcma = inverted_duty_cycle; + } + + p_instance_ctrl->p_reg->ULPTCMA = ulptcma; + } + + if (ULPT_MATCH_PIN_CFG_DISABLED != p_extend->ulptoab_settings_b.ulptob) + { + if (ULPT_MATCH_PIN_CFG_START_LEVEL_HIGH == p_extend->ulptoab_settings_b.ulptob) + { + ulptcmb = inverted_duty_cycle; + } + + p_instance_ctrl->p_reg->ULPTCMB = ulptcmb; + } + } +#endif + + p_instance_ctrl->p_reg->ULPTMR1 = (uint8_t) ulptmr1; + p_instance_ctrl->p_reg->ULPTMR2 = (uint8_t) ulptmr2; + p_instance_ctrl->p_reg->ULPTMR3 = (uint8_t) ulptmr3; + p_instance_ctrl->p_reg->ULPTIOC = (uint8_t) ulptioc; + p_instance_ctrl->p_reg->ULPTISR = (uint8_t) ulptisr; + p_instance_ctrl->p_reg->ULPTCMSR = (uint8_t) ulptcmsr; +} + +/*******************************************************************************************************************//** + * Sets period register and updates compare match registers in one-shot and periodic mode. + * + * @param[in] p_instance_ctrl Control block for this instance + * @param[in] period_counts ULPT period in counts + **********************************************************************************************************************/ +static void r_ulpt_period_register_set (ulpt_instance_ctrl_t * p_instance_ctrl, uint32_t period_counts) +{ + /* Store the period value so it can be retrieved later. */ + p_instance_ctrl->period = period_counts; + + uint32_t period_reg = period_counts - 1U; + +#if ULPT_CFG_OUTPUT_SUPPORT_ENABLE + uint32_t duty_cycle_counts = 0U; + if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode) + { + duty_cycle_counts = (period_counts >> 1); + } + else if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode) + { + duty_cycle_counts = period_reg; + } + else + { + /* Do nothing, duty cycle should not be updated in R_ULPT_PeriodSet. */ + } + + if (TIMER_MODE_PWM != p_instance_ctrl->p_cfg->mode) + { + p_instance_ctrl->p_reg->ULPTCMA = duty_cycle_counts; + p_instance_ctrl->p_reg->ULPTCMB = duty_cycle_counts; + } +#endif + + /* Set counter to period minus one. */ + p_instance_ctrl->p_reg->ULPTCNT = period_reg; +} + +/*******************************************************************************************************************//** + * Obtains the clock frequency of ULPT for all clock sources + * + * @param[in] p_ulpt_regs Registers of ULPT channel used + * + * @return Source clock frequency of ULPT in Hz with prescaler divider applied + **********************************************************************************************************************/ +static uint32_t r_ulpt_clock_frequency_get (R_ULPT0_Type * p_ulpt_regs) +{ + uint32_t clock_freq_hz = 0U; + uint8_t count_source_int = p_ulpt_regs->ULPTMR1_b.TCK1; + uint8_t divider = p_ulpt_regs->ULPTMR2_b.CKS; + + if (ULPT_CLOCK_SUBCLOCK == (count_source_int & R_ULPT0_ULPTMR1_TCK1_Msk)) + { + clock_freq_hz = BSP_SUBCLOCK_FREQ_HZ; + } + else + { + clock_freq_hz = BSP_LOCO_FREQ_HZ; + } + + clock_freq_hz >>= divider; + + return clock_freq_hz; +} + +/********************************************************************************************************************* + * AGT counter underflow interrupt. + **********************************************************************************************************************/ +void ulpt_int_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + uint32_t statusMask; + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Clear pending IRQ to make sure it doesn't fire again after exiting */ + R_BSP_IrqStatusClear(irq); + + /* Recover ISR context saved in open. */ + ulpt_instance_ctrl_t * p_instance_ctrl = (ulpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Save ULPTCR to determine the source of the interrupt. */ + uint32_t ulptcr = p_instance_ctrl->p_reg->ULPTCR; + + /* Invoke the callback function if it is set. */ + if (NULL != p_instance_ctrl->p_callback) + { + /* Setup parameters for the user-supplied callback function. */ + timer_callback_args_t callback_args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + timer_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &callback_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + callback_args = *p_args; + } + + if (ulptcr & R_ULPT0_ULPTCR_TUNDF_Msk) + { + p_args->event = TIMER_EVENT_CYCLE_END; + } + else if (ulptcr & R_ULPT0_ULPTCR_TCMAF_Msk) + { + p_args->event = TIMER_EVENT_CAPTURE_A; + } + else if (ulptcr & R_ULPT0_ULPTCR_TCMBF_Msk) + { + p_args->event = TIMER_EVENT_CAPTURE_B; + } + else + { + } + + p_args->p_context = p_instance_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + ulpt_prv_ns_callback p_callback = (ulpt_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = callback_args; + } + + /* Retrieve AGTCR in case it was modified in the callback. */ + ulptcr = p_instance_ctrl->p_reg->ULPTCR; + } + + /* Clear flags in AGTCR. */ + /* In one shot mode we need to stop the timer*/ + statusMask = ULPT_PRV_ULPTCR_STATUS_FLAGS; + if (p_instance_ctrl->p_reg->ULPTMR3 & R_ULPT0_ULPTMR3_TCNTCTL_Msk) + { + statusMask |= R_ULPT0_ULPTCR_TSTART_Msk; + } + + p_instance_ctrl->p_reg->ULPTCR = (uint8_t) (ulptcr & ~statusMask); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/r_usb_basic.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/r_usb_basic.c new file mode 100644 index 0000000000..6854746d24 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/r_usb_basic.c @@ -0,0 +1,4287 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_cfg.h" + +#include +#include +#include + +#include "src/driver/inc/r_usb_typedef.h" +#include "src/driver/inc/r_usb_extern.h" +#include "src/hw/inc/r_usb_bitdefine.h" +#include "src/hw/inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS == 1) + #include "../../../microsoft/azure-rtos/usbx/common/core/inc/ux_api.h" + #include "../../../microsoft/azure-rtos/usbx/common/core/inc/ux_system.h" + #if defined(USB_CFG_HCDC_USE) + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_cdc_acm.h" + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_storage.h" + #endif /* defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_hid.h" + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_hid_keyboard.h" + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_hid_mouse.h" + #endif /* defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_printer.h" + #endif /* defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_video.h" + #endif /* defined(USB_CFG_HUVC_USE) */ + #if defined(USB_CFG_HAUD_USE) + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_audio.h" + #endif /* defined(USB_CFG_HAUD_USE) */ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_hub.h" + #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ +#endif /* #if (BSP_CFG_RTOS == 1) */ + +#if (BSP_CFG_RTOS != 0) + #include "src/driver/inc/r_usb_cstd_rtos.h" + +#endif /*(BSP_CFG_RTOS != 0)*/ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HCDC_USE) + #include "r_usb_hcdc_api.h" + #endif /* defined(USB_CFG_HCDC_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HHID_USE) + #include "r_usb_hhid_api.h" + #endif /* defined(USB_CFG_HHID_USE) */ +#endif /* (BSP_CFG_RTOS != 1) */ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HMSC_USE) + #include "r_usb_hmsc_api.h" + #include "../r_usb_hmsc/src/inc/r_usb_hmsc_driver.h" + #endif /* defined(USB_CFG_HMSC_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if defined(USB_CFG_PHID_USE) && !defined(USB_CFG_OTG_USE) + #include "r_usb_phid_api.h" +#endif /* defined(USB_CFG_PHID_USE) */ + +#if defined(USB_CFG_PPRN_USE) + #include "r_usb_pprn_api.h" +#endif /* defined(USB_CFG_PPRN_USE) */ + +#if defined(USB_CFG_OTG_USE) + #if defined(USB_CFG_PCDC_USE) + #include "r_usb_pcdc_api.h" + #include "r_usb_otg_cdc_cfg.h" + #endif /* (defined(USB_CFG_HCDC_USE) | defined(USB_CFG_PCDC_USE)) */ +#else /* defined(USB_CFG_OTG_USE) */ + #if defined(USB_CFG_PCDC_USE) + #include "r_usb_pcdc_api.h" + #include "r_usb_pcdc_cfg.h" + #endif /* defined(USB_CFG_PCDC_USE) */ +#endif /* defined(USB_CFG_OTG_USE) */ + +#if defined(USB_CFG_PMSC_USE) + #if (BSP_CFG_RTOS != 1) + #include "../r_usb_pmsc/src/inc/r_usb_pmsc_driver.h" + #endif /* #if (BSP_CFG_RTOS != 1) */ +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if (USB_CFG_DMA == USB_CFG_ENABLE) + #include "r_dmac.h" +#endif + +#if defined(USB_OTG_CFG_USE) + #include "r_icu.h" + #include "r_ioport.h" +#endif /* defined(USB_OTG_CFG_USE) */ + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ +#define USB_VALUE_50 (50) +#define USB_VALUE_100 (100) +#define USB_VALUE_7FH (0x7F) +#define USB_VALUE_80H (0x80) +#define USB_VALUE_FFH (0xFF) + +#define USB_MASK_ALIGN_2_BYTE (0x1U) +#define USB_MASK_ALIGN_4_BYTE (0x3U) + +#define USB_OTG_IRQ (0x7) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +#if (BSP_CFG_RTOS == 0) +usb_event_t g_usb_cstd_event; +uint16_t g_usb_change_device_state[USB_NUM_USBIP]; +#else /*(BSP_CFG_RTOS == 0)*/ +usb_instance_ctrl_t g_usb_cstd_event[USB_EVENT_MAX]; + +#endif /*(BSP_CFG_RTOS == 0)*/ +usb_callback_t * g_usb_apl_callback[USB_NUM_USBIP]; +usb_callback_args_t * g_usb_apl_callback_memory[USB_NUM_USBIP] = +{ + NULL, +#if 2 == USB_NUM_USBIP + NULL, +#endif /* 2 == USB_NUM_USBIP */ +}; + +#if defined(USB_CFG_OTG_USE) +usb_cfg_t * g_p_usb_otg_cfg; + +#endif /* defined (USB_CFG_OTG_USE) */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +usb_utr_t g_usb_hdata[USB_NUM_USBIP][USB_MAXPIPE_NUM + 1]; + #if (BSP_CFG_RTOS == 1) +extern UINT usb_host_usbx_initialize(UX_HCD * hcd); +extern uint32_t usb_host_usbx_uninitialize(uint32_t dcd_io); + + #endif /* (BSP_CFG_RTOS == 1) */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE +usb_compliance_cb_t * g_usb_compliance_callback[USB_NUM_USBIP]; + #endif /* #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +usb_utr_t g_usb_pdata[USB_MAXPIPE_NUM + 1]; + #if (BSP_CFG_RTOS == 1) +extern uint32_t usb_peri_usbx_initialize(uint32_t dcd_io); +extern uint32_t usb_peri_usbx_uninitialize(uint32_t dcd_io); + + #if defined(USB_CFG_PMSC_USE) +extern fsp_err_t usb_peri_usbx_pmsc_media_initialize(void * p_context); +extern fsp_err_t usb_peri_usbx_media_close(void); + + #endif /* defined(USB_CFG_PMSC_USE) */ + + #else /* (BSP_CFG_RTOS == 1) */ + #if defined(USB_CFG_PMSC_USE) +extern usb_utr_t g_usb_pmsc_utr; + #endif /* defined(USB_CFG_PMSC_USE) */ + #endif /* (BSP_CFG_RTOS == 1) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +volatile uint16_t g_usb_usbmode[USB_NUM_USBIP] = +{ + 0, +#if USB_NUM_USBIP == 2 + 0 +#endif +}; + +#if defined(USB_CFG_OTG_USE) +void (* g_p_otg_callback[USB_NUM_USBIP])(ULONG mode); +#endif /* USB_CFG_OTG_USE */ + +volatile uint32_t g_usb_open_class[USB_NUM_USBIP]; + +#if defined(USB_CFG_PMSC_USE) +uint8_t g_usb_pmsc_usbip = USB_VALUE_FFH; +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + #if (BSP_CFG_RTOS == 1) +const transfer_instance_t * g_p_usbx_transfer_tx[USB_NUM_USBIP]; +const transfer_instance_t * g_p_usbx_transfer_rx[USB_NUM_USBIP]; + #endif /* (BSP_CFG_RTOS == 1) */ +#endif /* (USB_CFG_DMA == USB_CFG_ENABLE) || (USB_CFG_DTC == USB_CFG_ENABLE)*/ + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ +static uint8_t is_init[USB_NUM_USBIP] = +{ + USB_NO, +#if USB_NUM_USBIP == 2 + USB_NO, +#endif +}; + +#if (BSP_CFG_RTOS != 0) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +static uint8_t gs_usb_suspend_ing[USB_NUM_USBIP] = +{ + USB_NO, + #if USB_NUM_USBIP == 2 + USB_NO, + #endif +}; + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +uint8_t g_usb_resume_ing[USB_NUM_USBIP] = +{ + USB_NO, + #if USB_NUM_USBIP == 2 + USB_NO, + #endif +}; +#endif /*#if (BSP_CFG_RTOS != 0)*/ + +#if defined(USB_CFG_OTG_USE) +uint8_t g_is_usbx_otg_host_class_init[USB_NUM_USBIP] = +{ + USB_NO, + #if USB_NUM_USBIP == 2 + USB_NO, + #endif +}; +#endif /* #if defined(USB_CFG_OTG_USE) */ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +const usb_api_t g_usb_on_usb = +{ + .open = R_USB_Open, + .close = R_USB_Close, + .read = R_USB_Read, + .write = R_USB_Write, + .stop = R_USB_Stop, + .suspend = R_USB_Suspend, + .resume = R_USB_Resume, + .vbusSet = R_USB_VbusSet, + .infoGet = R_USB_InfoGet, + .pipeRead = R_USB_PipeRead, + .pipeWrite = R_USB_PipeWrite, + .pipeStop = R_USB_PipeStop, + .usedPipesGet = R_USB_UsedPipesGet, + .pipeInfoGet = R_USB_PipeInfoGet, + .eventGet = R_USB_EventGet, + .callback = R_USB_Callback, + .pullUp = R_USB_PullUp, + .hostControlTransfer = R_USB_HostControlTransfer, + .periControlDataGet = R_USB_PeriControlDataGet, + .periControlDataSet = R_USB_PeriControlDataSet, + .periControlStatusSet = R_USB_PeriControlStatusSet, + .remoteWakeup = R_USB_RemoteWakeup, + .driverActivate = R_USB_DriverActivate, + .callbackMemorySet = R_USB_CallbackMemorySet, + .moduleNumberGet = R_USB_ModuleNumberGet, + .classTypeGet = R_USB_ClassTypeGet, + .deviceAddressGet = R_USB_DeviceAddressGet, + .pipeNumberGet = R_USB_PipeNumberGet, + .deviceStateGet = R_USB_DeviceStateGet, + .dataSizeGet = R_USB_DataSizeGet, + .setupGet = R_USB_SetupGet, + .otgCallbackSet = R_USB_OtgCallbackSet, + .otgSRP = R_USB_OtgSRP, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup USB USB + * @{ + **********************************************************************************************************************/ + +/**************************************************************************//** + * @brief Obtains completed USB related events. (OS-less Only) + * + * In USB host mode, the device address value of the USB device that completed + * an event is specified in the usb_ctrl_t structure member (address) specified + * by the event's argument. + * In USB peripheral mode, USB_NULL is specified in member (address). + * If this function is called in the RTOS execution environment, a failure is returned. + * + * @retval FSP_SUCCESS Event Get Success. + * @retval FSP_ERR_USB_FAILED If called in the RTOS environment, an error is returned. + * + * @note Do not use the same variable as the first argument of R_USB_Open for the first argument. + * @note Do not call this API in the interrupt function. + ******************************************************************************/ +fsp_err_t R_USB_EventGet (usb_ctrl_t * const p_api_ctrl, usb_status_t * event) +{ + USB_PREEMPTION_DISABLE(); + fsp_err_t result; +#if (BSP_CFG_RTOS == 0) + result = FSP_SUCCESS; + (*event) = USB_STATUS_NONE; + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + usb_cstd_usb_task(); + if (g_usb_cstd_event.write_pointer != g_usb_cstd_event.read_pointer) + { + *p_ctrl = g_usb_cstd_event.ctrl[g_usb_cstd_event.read_pointer]; + (*event) = g_usb_cstd_event.code[g_usb_cstd_event.read_pointer]; + g_usb_cstd_event.read_pointer++; + if (g_usb_cstd_event.read_pointer >= USB_EVENT_MAX) + { + g_usb_cstd_event.read_pointer = 0; + } + } + +#else /* (BSP_CFG_RTOS == 0) */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(*event); + result = FSP_ERR_USB_FAILED; +#endif /* (BSP_CFG_RTOS == 0) */ + + USB_PREEMPTION_ENABLE(); + + return result; +} /* End of function R_USB_EventGet() */ + +/**************************************************************************//** + * @brief Register a callback function to be called upon completion of a + * USB related event. (RTOS only) + * + * This function registers a callback function to be called when a USB-related event has completed. + * If this function is called in the OS-less execution environment, a failure is returned. + * + * @retval FSP_SUCCESS Successfully completed. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @note Do not call this API in the interrupt function. + ******************************************************************************/ +fsp_err_t R_USB_Callback (usb_callback_t * p_callback) +{ +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_callback) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + g_usb_apl_callback[0] = callback_is_secure ? p_callback : + (void (*)(usb_callback_args_t *))cmse_nsfptr_create(p_callback); +#else /* BSP_TZ_SECURE_BUILD */ + g_usb_apl_callback[0] = p_callback; +#endif /* BSP_TZ_SECURE_BUILD */ + +#if USB_NUM_USBIP == 2 + g_usb_apl_callback[1] = g_usb_apl_callback[0]; +#endif /* USB_NUM_USBIP == 2 */ + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} /* End of function R_USB_Callback() */ + +/**************************************************************************//** + * @brief Applies power to the USB module specified in the argument (p_ctrl). + * + * @retval FSP_SUCCESS Success in open. + * @retval FSP_ERR_USB_BUSY Specified USB module now in use. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; +#if (BSP_CFG_RTOS != 0) + usb_rtos_err_t os_err; +#endif /* (BSP_CFG_RTOS != 0) */ +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_utr_t utr; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if defined(USB_CFG_OTG_USE) + uint16_t syssts; +#endif /* defined(USB_CFG_OTG_USE) */ + + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + FSP_ASSERT(p_cfg) + + /* Check if the module number is valid */ + FSP_ERROR_RETURN(!((USB_IP0 != p_cfg->module_number) && (USB_IP1 != p_cfg->module_number)), FSP_ERR_USB_PARAMETER) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + +#if defined(USB_CFG_OTG_USE) +#endif /* !defined (USB_CFG_OTG_USE)*/ + p_ctrl->module_number = p_cfg->module_number; + p_ctrl->type = (usb_class_t) (p_cfg->type & USB_VALUE_7FH); + p_ctrl->p_context = p_cfg->p_context; +#if (BSP_CFG_RTOS == 1) + g_usb_apl_callback[p_ctrl->module_number] = usb_cstd_usbx_callback; +#else /* #if (BSP_CFG_RTOS == 1) */ + #if ((defined(USB_CFG_HCDC_USE) && defined(USB_CFG_HMSC_USE)) || (USB_CFG_HUB == USB_CFG_ENABLE)) + + /* Callback registration is not done yet. */ + #else + g_usb_apl_callback[p_ctrl->module_number] = p_cfg->p_usb_apl_callback; + #endif +#endif /* #if (BSP_CFG_RTOS == 1) */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + g_usb_compliance_callback[p_ctrl->module_number] = p_cfg->usb_complience_cb; + #endif /* #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ +#endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + +#if USB_CFG_PARAM_CHECKING_ENABLE + + /* Argument Checking */ + FSP_ERROR_RETURN(!(((USB_SPEED_HS != p_cfg->usb_speed) && (USB_SPEED_FS != p_cfg->usb_speed)) && + (USB_SPEED_LS != p_cfg->usb_speed) && + (USB_MODE_HOST != p_cfg->usb_mode)), + FSP_ERR_USB_PARAMETER) + + #if (USB_NUM_USBIP == 1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif /* USB_NUM_USBIP == 1 */ + + switch ((usb_class_internal_t) p_ctrl->type) + { + case USB_CLASS_INTERNAL_PCDC: + case USB_CLASS_INTERNAL_PHID: + case USB_CLASS_INTERNAL_PVND: + case USB_CLASS_INTERNAL_PMSC: + case USB_CLASS_INTERNAL_PAUD: + case USB_CLASS_INTERNAL_PPRN: + case USB_CLASS_INTERNAL_DFU: + { + FSP_ERROR_RETURN(USB_MODE_PERI == p_cfg->usb_mode, FSP_ERR_USB_PARAMETER) + + #if (BSP_CFG_RTOS == 1) + FSP_ERROR_RETURN(!(USB_SPEED_LS == p_cfg->usb_speed), FSP_ERR_USB_PARAMETER) + #else /* #if (BSP_CFG_RTOS == 1) */ + FSP_ERROR_RETURN(!((USB_SPEED_LS == p_cfg->usb_speed) || (USB_NULL == p_cfg->p_usb_reg)), + FSP_ERR_USB_PARAMETER) + #endif /* #if (BSP_CFG_RTOS == 1) */ + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP0 == p_ctrl->module_number) + { + FSP_ERROR_RETURN(USB_SPEED_HS != p_cfg->usb_speed, FSP_ERR_USB_PARAMETER) + } + + #else /* defined (USB_HIGH_SPEED_MODULE) */ + FSP_ERROR_RETURN(USB_SPEED_HS != p_cfg->usb_speed, FSP_ERR_USB_PARAMETER) + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + /* Host */ + case USB_CLASS_INTERNAL_HCDC: + case USB_CLASS_INTERNAL_HHID: + case USB_CLASS_INTERNAL_HVND: + case USB_CLASS_INTERNAL_HMSC: + case USB_CLASS_INTERNAL_HPRN: + case USB_CLASS_INTERNAL_HUVC: + case USB_CLASS_INTERNAL_HAUD: + { + #if defined(USB_NOT_SUPPORT_HOST) + + return FSP_ERR_USB_PARAMETER; + #else /* defined(USB_NOT_SUPPORT_HOST) */ + FSP_ERROR_RETURN(USB_MODE_HOST == p_cfg->usb_mode, FSP_ERR_USB_PARAMETER) + #if defined(USB_HIGH_SPEED_MODULE) + FSP_ERROR_RETURN(!((USB_SPEED_HS == p_cfg->usb_speed) && (USB_IP1 != p_ctrl->module_number)), + FSP_ERR_USB_PARAMETER) + #else /* defined (USB_HIGH_SPEED_MODULE) */ + FSP_ERROR_RETURN(USB_SPEED_HS != p_cfg->usb_speed, FSP_ERR_USB_PARAMETER) + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #endif /* defined(USB_NOT_SUPPORT_HOST) */ + break; + } + + default: + { + return FSP_ERR_USB_PARAMETER; + break; + } + } +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + +#if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + p_ctrl->p_transfer_tx = p_cfg->p_transfer_tx; + p_ctrl->p_transfer_rx = p_cfg->p_transfer_rx; + + #if (BSP_CFG_RTOS == 1) + g_p_usbx_transfer_tx[p_cfg->module_number] = p_cfg->p_transfer_tx; + g_p_usbx_transfer_rx[p_cfg->module_number] = p_cfg->p_transfer_rx; + #endif /* (BSP_CFG_RTOS == 1) */ + + #if defined(USB_CFG_PMSC_USE) + #if (BSP_CFG_RTOS != 1) + g_usb_pmsc_utr.p_transfer_rx = p_cfg->p_transfer_rx; + g_usb_pmsc_utr.p_transfer_tx = p_cfg->p_transfer_tx; + #endif /* (BSP_CFG_RTOS != 1) */ + #endif /* defined(USB_CFG_PMSC_USE) */ +#endif + if (USB_YES == is_init[p_ctrl->module_number]) + { + return FSP_ERR_USB_BUSY; + } + +#if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_ctrl->p_transfer_tx->p_api->open(p_ctrl->p_transfer_tx->p_ctrl, p_ctrl->p_transfer_tx->p_cfg); + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_ctrl->p_transfer_rx->p_api->open(p_ctrl->p_transfer_rx->p_ctrl, p_ctrl->p_transfer_rx->p_cfg); + } +#endif + + if (USB_MODE_HOST == p_cfg->usb_mode) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + + /* Be sure set USB_MODE_HOST to g_usb_usbmode variable before calling usb_rtos_configuration function. */ + g_usb_usbmode[p_ctrl->module_number] = USB_MODE_HOST; +#endif + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + + /* Be sure set USB_MODE_PERI to g_usb_usbmode variable before calling usb_rtos_configuration function. */ + g_usb_usbmode[p_ctrl->module_number] = USB_MODE_PERI; +#endif + } + +#if defined(USB_CFG_OTG_USE) + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; +#endif /* defined(USB_CFG_OTG_USE) */ + +#if (BSP_CFG_RTOS != 0) /* (USB_NUM_USBIP == 2) */ + os_err = usb_rtos_configuration(p_cfg); + if (UsbRtos_Success != os_err) + { + return FSP_ERR_USB_FAILED; + } /* (USB_NUM_USBIP == 2) */ +#endif /* (BSP_CFG_RTOS != 0) */ + +#if USB_NUM_USBIP == 2 + if ((USB_NO == is_init[USB_IP0]) && (USB_NO == is_init[USB_IP1])) +#endif /* USB_NUM_USBIP == 2 */ + { + memset((void *) &g_usb_cstd_event, 0, sizeof(g_usb_cstd_event)); + } + + is_init[p_ctrl->module_number] = USB_YES; + + g_usb_open_class[p_ctrl->module_number] = 0; + +#if (BSP_CFG_RTOS == 0) + g_usb_change_device_state[p_ctrl->module_number] = 0; +#endif /* (BSP_CFG_RTOS == 0) */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + g_usb_hstd_use_pipe[p_ctrl->module_number] = 0; + memset((void *) &g_usb_hdata[p_ctrl->module_number], 0, sizeof(usb_utr_t)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + memset((void *) &g_usb_pdata, 0, ((USB_MAXPIPE_NUM + 1) * sizeof(usb_utr_t))); +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +#if defined(USB_CFG_OTG_USE) + g_p_usb_otg_cfg = (usb_cfg_t *) p_cfg; +#endif /* defined (USB_CFG_OTG_USE) */ + + if (USB_MODE_HOST == p_cfg->usb_mode) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ip = p_ctrl->module_number; + utr.ipp = usb_hstd_get_usb_ip_adr((uint16_t) p_ctrl->module_number); /* Get the USB IP base address. */ + + err = usb_module_start(utr.ip); + if (FSP_SUCCESS == err) + { + /* USB driver initialization */ + usb_hdriver_init(&utr, p_cfg->type); + + /* Setting MCU(USB interrupt init) register */ + usb_cpu_usbint_init(utr.ip, p_cfg); + + g_usb_hstd_hs_enable[utr.ip] = USB_HS_DISABLE; + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_SPEED_HS == p_cfg->usb_speed) + { + g_usb_hstd_hs_enable[utr.ip] = USB_HS_ENABLE; + hw_usb_set_hse(&utr); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + /* Setting USB relation register */ + hw_usb_hmodule_init(utr.ip); /* MCU */ + + #if !defined(USB_CFG_OTG_USE) + #if defined(USB_CFG_HHID_USE) + if (USB_CLASS_INTERNAL_HHID == (usb_class_internal_t) p_ctrl->type) + { + hw_usb_hset_trnensel(&utr); + } + #endif /* defined(USB_CFG_HHID_USE) */ + #endif /* !defined (USB_CFG_OTG_USE) */ + + #if USB_CFG_TYPEC == USB_CFG_DISABLE + #if USB_CFG_VBUS == USB_CFG_LOW + + /* VBUS OFF process for Low Active Power IC */ + usb_hstd_vbus_control(&utr, (uint16_t) USB_VBOFF); + usb_cpu_delay_xms(USB_VALUE_50); + #endif /* USB_CFG_VBUS == USB_CFG_LOW */ + usb_hstd_vbus_control(&utr, (uint16_t) USB_VBON); + #if USB_CFG_BC == USB_CFG_DISABLE + usb_cpu_delay_xms((uint16_t) USB_VALUE_100); /* 100ms wait */ + #endif /* USB_CFG_BC == USB_CFG_DISABLE */ + #else /* USB_CFG_TYPEC == USB_CFG_DISABLE */ + usb_hstd_vbus_control(&utr, (uint16_t) USB_VBOFF); + #endif /* USB_CFG_TYPEC == USB_CFG_DISABLE */ + + #if (BSP_CFG_RTOS == 1) + #if !defined(USB_CFG_OTG_USE) + ux_host_stack_class_register(_ux_system_host_class_hub_name, ux_host_class_hub_entry); + #endif /* !defined(USB_CFG_OTG_USE) */ + + #if defined(USB_CFG_HCDC_USE) + if (USB_CLASS_HCDC == p_cfg->type) + { + ux_host_stack_class_register(_ux_system_host_class_cdc_acm_name, ux_host_class_cdc_acm_entry); + if (USB_SPEED_HS == p_cfg->usb_speed) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hcdc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + if (USB_IP0 == p_cfg->module_number) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hcdc_fs", + usb_host_usbx_initialize, + R_USB_FS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hcdc_hs", + usb_host_usbx_initialize, + R_USB_HS0_BASE, + 0); + } + } + } + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + if (USB_CLASS_HMSC == p_cfg->type) + { + ux_host_stack_class_register(_ux_system_host_class_storage_name, ux_host_class_storage_entry); + if (USB_SPEED_HS == p_cfg->usb_speed) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hmsc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + if (USB_IP0 == p_cfg->module_number) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hmsc_fs", + usb_host_usbx_initialize, + R_USB_FS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hmsc_hs", + usb_host_usbx_initialize, + R_USB_HS0_BASE, + 0); + } + } + } + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) + if (USB_CLASS_HHID == p_cfg->type) + { + ux_host_stack_class_register(_ux_system_host_class_hid_name, ux_host_class_hid_entry); + + ux_host_class_hid_client_register(_ux_system_host_class_hid_client_keyboard_name, + ux_host_class_hid_keyboard_entry); + ux_host_class_hid_client_register(_ux_system_host_class_hid_client_mouse_name, + ux_host_class_hid_mouse_entry); + + if (USB_IP1 == p_ctrl->module_number) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hhid_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hhid_fs", usb_host_usbx_initialize, R_USB_FS0_BASE, + 0); + } + } + #endif /* defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + if (USB_CLASS_HPRN == p_cfg->type) + { + ux_host_stack_class_register(_ux_system_host_class_printer_name, ux_host_class_printer_entry); + if (USB_SPEED_HS == p_cfg->usb_speed) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hprn_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + if (USB_IP0 == p_cfg->module_number) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hprn_fs", + usb_host_usbx_initialize, + R_USB_FS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hprn_hs", + usb_host_usbx_initialize, + R_USB_HS0_BASE, + 0); + } + } + } + #endif /* defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + if (USB_CLASS_HUVC == p_cfg->type) + { + ux_host_stack_class_register(_ux_system_host_class_video_name, ux_host_class_video_entry); + if (USB_SPEED_HS == p_cfg->usb_speed) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_huvc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + if (USB_IP0 == p_cfg->module_number) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_huvc_fs", + usb_host_usbx_initialize, + R_USB_FS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_huvc_hs", + usb_host_usbx_initialize, + R_USB_HS0_BASE, + 0); + } + } + } + #endif /* defined(USB_CFG_HUVC_USE) */ + #if defined(USB_CFG_HAUD_USE) + if (USB_CLASS_HAUD == p_cfg->type) + { + ux_host_stack_class_register(_ux_system_host_class_audio_name, ux_host_class_audio_entry); + if (USB_SPEED_HS == p_cfg->usb_speed) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_haud_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + if (USB_IP0 == p_cfg->module_number) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_haud_fs", + usb_host_usbx_initialize, + R_USB_FS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_haud_hs", + usb_host_usbx_initialize, + R_USB_HS0_BASE, + 0); + } + } + } + #endif /* defined(USB_CFG_HAUD_USE) */ + #endif /* #if (BSP_CFG_RTOS == 0) */ + } + else + { + USB_PRINTF0("### usb_module_start FSP_ERR_USB_BUSY\n"); + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if defined(USB_CFG_PMSC_USE) + g_usb_pmsc_usbip = p_ctrl->module_number; + #if (BSP_CFG_RTOS == 1) + err = usb_peri_usbx_pmsc_media_initialize(p_cfg->p_context); + #else + err = r_usb_pmsc_media_initialize(p_cfg->p_context); /* Register the media device driver. */ + #endif /* (BSP_CFG_RTOS == 1) */ + if (FSP_SUCCESS != err) + { + return err; + } + #endif /* defined(USB_CFG_PMSC_USE) */ + /* USB module start setting */ + err = usb_module_start(p_ctrl->module_number); + if (FSP_SUCCESS == err) + { + /* USB driver initialization */ + usb_pdriver_init(p_ctrl, p_cfg); + + /* Setting MCU(USB interrupt init) register */ + usb_cpu_usbint_init(p_ctrl->module_number, p_cfg); + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_SPEED_HS == p_cfg->usb_speed) + { + usb_utr_t hse_utr; + hse_utr.ip = p_ctrl->module_number; + hw_usb_set_hse(&hse_utr); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + /* Setting USB relation register */ + hw_usb_pmodule_init(p_ctrl->module_number); + + #if (BSP_CFG_RTOS == 1) + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == p_ctrl->module_number) + { + usb_peri_usbx_initialize(R_USB_HS0_BASE); + } + else + { + usb_peri_usbx_initialize(R_USB_FS0_BASE); + } + + #else + usb_peri_usbx_initialize(R_USB_FS0_BASE); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ + if (USB_ATTACH == usb_pstd_chk_vbsts(p_ctrl->module_number)) + { + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_set_cnen(p_ctrl->module_number); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + usb_cpu_delay_xms((uint16_t) 10); + hw_usb_pset_dprpu(p_ctrl->module_number); + } + } + else + { + USB_PRINTF1("### usb_module_start FSP_ERR_USB_BUSY:%d\n", err); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + + if (FSP_SUCCESS == err) + { + if (USB_MODE_HOST == p_cfg->usb_mode) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + g_usb_open_class[p_ctrl->module_number] |= (1 << p_ctrl->type); /* Set USB Open device class */ + + /* Check if both HCDC class and HMSC class are enabled */ + #if (defined(USB_CFG_HCDC_USE) && defined(USB_CFG_HMSC_USE) && (USB_CFG_MULTIPORT == USB_CFG_DISABLE)) + + /* Set USB Open device class for HCDC Class and HCDCC Class */ + g_usb_open_class[p_ctrl->module_number] |= + ((1 << USB_CLASS_INTERNAL_HCDC) | (1 << USB_CLASS_INTERNAL_HCDCC)); + #else + if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) + { + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_HCDCC); /* Set USB Open device class */ + } + #endif /* defined(USB_CFG_HCDC_USE) && defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_OTG_USE) + g_is_A_device[p_ctrl->module_number] = USB_YES; + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_A; + + (*g_p_otg_callback[p_ctrl->module_number])(UX_OTG_MODE_HOST); + #endif /* defined(USB_CFG_OTG_USE) */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { +#if defined(USB_CFG_PCDC_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PCDC); + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PCDCC); + #if defined(USB_CFG_PCDC2_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PCDC2); + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PCDCC2); + #endif /* defined(USB_CFG_PCDC2_USE) */ +#endif /* defined(USB_CFG_PCDC_USE) */ + +#if defined(USB_CFG_PHID_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PHID); + #if defined(USB_CFG_PHID2_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PHID2); + #endif /* defined(USB_CFG_PHID2_USE) */ +#endif /* defined(USB_CFG_PHID_USE) */ + +#if defined(USB_CFG_PMSC_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PMSC); +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if defined(USB_CFG_PAUD_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PAUD); +#endif /* defined(USB_CFG_PAUD_USE) */ + +#if defined(USB_CFG_PVND_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PVND); +#endif /* defined(USB_CFG_PVND_USE) */ + +#if defined(USB_CFG_PPRN_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_PPRN); +#endif /* defined(USB_CFG_PPRN_USE) */ + +#if defined(USB_CFG_DFU_USE) + g_usb_open_class[p_ctrl->module_number] |= (1 << USB_CLASS_INTERNAL_DFU); +#endif /* defined(USB_CFG_PPRN_USE) */ + +#if defined(USB_CFG_OTG_USE) + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_B; + (*g_p_otg_callback[p_ctrl->module_number])(UX_OTG_MODE_SLAVE); +#endif /* defined(USB_CFG_OTG_USE) */ + } + } + +#if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_OTG_USE) + + /* Check the A device cable is connected when starting up MCU */ + /* If A device cable is connected, the following callback function is called */ + utr.ip = p_ctrl->module_number; + syssts = hw_usb_read_syssts(&utr); + if (0 == (syssts & USB_IDMON)) + { + if (USB_IP0 == p_ctrl->module_number) + { + usb_otg_irq_callback(0); + } + + #if USB_NUM_USBIP == 2 + else + { + usb2_otg_irq_callback(0); + } + #endif /* USB_NUM_USBIP == 2 */ + } + #endif /* defined(USB_CFG_OTG_USB) */ +#endif /* (BSP_CFG_RTOS == 1) */ + + return err; +} + +/**************************************************************************//** + * @brief Terminates power to the USB module specified in argument (p_ctrl). + * USB0 module stops when USB_IP0 is specified to the member (module), + * USB1 module stops when USB_IP1 is specified to the member (module). + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_USB_NOT_OPEN USB module is not open. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) +{ +#if defined(USB_CFG_OTG_USE) + fsp_err_t ret_code; + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + uint16_t is_connect = USB_FALSE; + uint8_t class_code = USB_IFCLS_CDC; + usb_utr_t utr; + UINT old_threshold; + TX_THREAD * now_thread; + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(USB_NULL != p_api_ctrl) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif /* #if defined(BSP_BOARD_GROUP_RA2A1) */ + + USB_PREEMPTION_DISABLE(); + + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; + g_is_A_device[p_ctrl->module_number] = USB_NO; + + switch ((usb_class_internal_t) p_ctrl->type) + { + case USB_CLASS_INTERNAL_PCDC: + { + class_code = (uint8_t) USB_IFCLS_CDC; + break; + } + + case USB_CLASS_INTERNAL_PHID: + { + class_code = (uint8_t) USB_IFCLS_HID; + break; + } + + case USB_CLASS_INTERNAL_PMSC: + { + class_code = (uint8_t) USB_IFCLS_MAS; + break; + } + + case USB_CLASS_INTERNAL_PVND: + { + class_code = (uint8_t) USB_IFCLS_VEN; + break; + } + + case USB_CLASS_INTERNAL_PPRN: + { + class_code = (uint8_t) USB_IFCLS_PRN; + break; + } + + default: + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_ASSERTION; + break; + } + } + USB_PREEMPTION_ENABLE(); + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + utr.ip = p_ctrl->module_number; + is_connect = usb_pstd_chk_configured(&utr); + + #if (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) + hw_usb_clear_vdcen(); + #endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ + + ret_code = usb_module_stop(p_ctrl->module_number); + + if (FSP_SUCCESS == ret_code) + { + is_init[p_ctrl->module_number] = USB_NO; + + utr.ip = p_ctrl->module_number; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + + usb_hstd_driver_release(&utr, class_code); + + usb_hstd_clr_pipe_table(utr.ip, USB_ADDRESS1); + + if ((USB_NO == g_is_usbx_otg_host_class_init[p_ctrl->module_number]) || + (USB_YES == g_is_A_device[p_ctrl->module_number])) + { + if (USB_IP1 == p_ctrl->module_number) + { + #if defined(USB_CFG_HCDC_USE) + if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hcdc_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + if (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hmsc_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + if (USB_CLASS_INTERNAL_HHID == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hhid_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + if (USB_CLASS_INTERNAL_HPRN == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hprn_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + if (USB_CLASS_INTERNAL_HUVC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_huvc_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HUVC_USE) */ + #if defined(USB_CFG_HAUD_USE) + if (USB_CLASS_INTERNAL_HAUD == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_haud_hs", R_USB_HS0_BASE, 0); + } + #endif + usb_host_usbx_uninitialize(R_USB_HS0_BASE); + } + else + { + #if defined(USB_CFG_HCDC_USE) + if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hcdc_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + if (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hmsc_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + if (USB_CLASS_INTERNAL_HHID == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hhid_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + if (USB_CLASS_INTERNAL_HPRN == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hprn_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + if (USB_CLASS_INTERNAL_HUVC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_huvc_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HUVC_USE) */ + #if defined(USB_CFG_HAUD_USE) + if (USB_CLASS_INTERNAL_HAUD == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_haud_fs", R_USB_FS0_BASE, 0); + } + #endif + usb_host_usbx_uninitialize(R_USB_FS0_BASE); + } + + #if USB_CFG_MULTIPORT == USB_CFG_ENABLE + if ((g_usb_open_class[0] != g_usb_open_class[1]) || !(is_init[0] || is_init[1])) + #endif + { + #if defined(USB_CFG_HCDC_USE) + if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_cdc_acm_entry); + } + #endif /* #if defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + if (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_storage_entry); + } + #endif /* #if defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + if (USB_CLASS_INTERNAL_HHID == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_hid_entry); + } + #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + if (USB_CLASS_INTERNAL_HPRN == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_printer_entry); + } + #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + if (USB_CLASS_INTERNAL_HUVC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_video_entry); + } + #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HAUD_USE) + if (USB_CLASS_INTERNAL_HAUD == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_audio_entry); + } + #endif /* #if defined(USB_CFG_HAUD_USE) */ + } + } + + g_is_usbx_otg_host_class_init[utr.ip] = USB_NO; + + usb_pstd_driver_release(); /* Clear the information registered in the structure usb_pcdreg_t. */ + usb_pstd_clr_pipe_table(p_ctrl->module_number); + if (USB_TRUE == is_connect) + { + _ux_device_stack_disconnect(); + } + + if (USB_IP1 == p_ctrl->module_number) + { + usb_peri_usbx_uninitialize(R_USB_HS0_BASE); + } + else + { + usb_peri_usbx_uninitialize(R_USB_FS0_BASE); + } + + g_usb_open_class[p_ctrl->module_number] = 0; + + #if defined(USB_CFG_PMSC_USE) + ret_code = usb_peri_usbx_media_close(); + #endif /* defined(USB_CFG_PMSC_USE) */ + + /* Settings to prevent preemption. */ + now_thread = tx_thread_identify(); + tx_thread_preemption_change(now_thread, 0, &old_threshold); /* Disable dispatch to the other task */ + + usb_rtos_delete(p_ctrl->module_number); + + /* Remove settings that prevent preemption. */ + tx_thread_preemption_change(now_thread, old_threshold, &old_threshold); /* Enable dispach to the other task */ + + /* Be sure set 0 to g_usb_usbmode variable after calling usb_rtos_delete function. */ + g_usb_usbmode[p_ctrl->module_number] = 0; + } + else + { + USB_PRINTF0("### usb_module_stop FSP_ERR_USB_NOT_OPEN\n"); + ret_code = FSP_ERR_USB_NOT_OPEN; + } + + #if defined(USB_CFG_PMSC_USE) + g_usb_pmsc_usbip = USB_VALUE_FFH; + #endif /* defined(USB_CFG_PMSC_USE) */ + + g_is_A_device[p_ctrl->module_number] = USB_NO; + + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; + _ux_system_otg->ux_system_otg_slave_role_swap_flag = 0; + + USB_PREEMPTION_ENABLE(); + + return ret_code; +#else /* defined(USB_CFG_OTG_USE) */ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + uint8_t device_address = USB_NULL; + #endif + fsp_err_t ret_code; + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + #if (BSP_CFG_RTOS == 1) + usb_utr_t ux_utr; + #endif /* (BSP_CFG_RTOS == 1) */ + + #if (BSP_CFG_RTOS != 0) + #if (BSP_CFG_RTOS == 1) + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + uint16_t is_connect = USB_FALSE; + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + #endif /* (BSP_CFG_RTOS == 1) */ + #endif /* (BSP_CFG_RTOS != 0) */ + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + uint8_t class_code = USB_IFCLS_CDC; + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(USB_NULL != p_api_ctrl) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif /* #if defined(BSP_BOARD_GROUP_RA2A1) */ + + USB_PREEMPTION_DISABLE(); + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + switch ((usb_class_internal_t) p_ctrl->type) + { + case USB_CLASS_INTERNAL_HCDC: + { + class_code = (uint8_t) USB_IFCLS_CDC; + break; + } + + case USB_CLASS_INTERNAL_HHID: + { + class_code = (uint8_t) USB_IFCLS_HID; + break; + } + + case USB_CLASS_INTERNAL_HMSC: + { + class_code = (uint8_t) USB_IFCLS_MAS; + break; + } + + case USB_CLASS_INTERNAL_HVND: + { + class_code = (uint8_t) USB_IFCLS_VEN; + break; + } + + case USB_CLASS_INTERNAL_HPRN: + { + class_code = (uint8_t) USB_IFCLS_PRN; + break; + } + + case USB_CLASS_INTERNAL_HUVC: + { + class_code = (uint8_t) USB_IFCLS_VID; + break; + } + + case USB_CLASS_INTERNAL_HAUD: + { + class_code = (uint8_t) USB_IFCLS_AUD; + break; + } + + default: + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_ASSERTION; + break; + } + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + USB_PREEMPTION_ENABLE(); + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + #if (BSP_CFG_RTOS == 1) + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + ux_utr.ip = p_ctrl->module_number; + is_connect = usb_pstd_chk_configured(&ux_utr); + + usb_pstd_detach_process(&ux_utr); + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ux_utr.ip = p_ctrl->module_number; + ux_utr.ipp = usb_hstd_get_usb_ip_adr((uint16_t) p_ctrl->module_number); /* Get the USB IP base address. */ + + usb_hstd_detach_process(&ux_utr); + usb_cpu_delay_xms(USB_VALUE_50); + #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + #endif /* (BSP_CFG_RTOS == 1) */ + + #if (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) + hw_usb_clear_vdcen(); + #endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ + + #if defined(USB_SUPPORT_HOCO_MODULE) + if (0 == (R_SYSTEM->SCKSCR & R_SYSTEM_SCKSCR_CKSEL_Msk)) + { + /* Use HOCO */ + hw_usb_clear_uckselc(); + } + #endif /* defined(USB_SUPPORT_HOCO_MODULE) */ + + ret_code = usb_module_stop(p_ctrl->module_number); + + if (FSP_SUCCESS == ret_code) + { + is_init[p_ctrl->module_number] = USB_NO; + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_utr_t utr; + + utr.ip = p_ctrl->module_number; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + + usb_hstd_driver_release(&utr, class_code); + + for (device_address = USB_ADDRESS1; device_address < (USB_ADDRESS5 + 1); device_address++) + { + usb_hstd_clr_pipe_table(utr.ip, device_address); + } + + #if (BSP_CFG_RTOS == 1) + if (USB_IP1 == p_ctrl->module_number) + { + #if defined(USB_CFG_HCDC_USE) + if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hcdc_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + if (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hmsc_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + if (USB_CLASS_INTERNAL_HHID == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hhid_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + if (USB_CLASS_INTERNAL_HPRN == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hprn_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + if (USB_CLASS_INTERNAL_HUVC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_huvc_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HUVC_USE) */ + #if defined(USB_CFG_HAUD_USE) + if (USB_CLASS_INTERNAL_HAUD == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_haud_hs", R_USB_HS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HAUD_USE) */ + usb_host_usbx_uninitialize(R_USB_HS0_BASE); + } + else + { + #if defined(USB_CFG_HCDC_USE) + if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hcdc_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + if (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hmsc_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + if (USB_CLASS_INTERNAL_HHID == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hhid_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + if (USB_CLASS_INTERNAL_HPRN == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hprn_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + if (USB_CLASS_INTERNAL_HUVC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_huvc_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HUVC_USE) */ + #if defined(USB_CFG_HAUD_USE) + if (USB_CLASS_INTERNAL_HAUD == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_haud_fs", R_USB_FS0_BASE, 0); + } + #endif /* #if defined(USB_CFG_HAUD_USE) */ + usb_host_usbx_uninitialize(R_USB_FS0_BASE); + } + + #if USB_CFG_MULTIPORT == USB_CFG_ENABLE + if ((g_usb_open_class[0] != g_usb_open_class[1]) || !(is_init[0] || is_init[1])) + #endif + { + #if defined(USB_CFG_HCDC_USE) + if (USB_CLASS_INTERNAL_HCDC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_cdc_acm_entry); + } + #endif /* #if defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + if (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_storage_entry); + } + #endif /* #if defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + if (USB_CLASS_INTERNAL_HHID == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_hid_entry); + } + #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + if (USB_CLASS_INTERNAL_HPRN == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_printer_entry); + } + #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + if (USB_CLASS_INTERNAL_HUVC == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_video_entry); + } + #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HAUD_USE) + if (USB_CLASS_INTERNAL_HAUD == (usb_class_internal_t) p_ctrl->type) + { + ux_host_stack_class_unregister(ux_host_class_audio_entry); + } + #endif /* #if defined(USB_CFG_HAUD_USE) */ + } + + #if !defined(USB_CFG_OTG_USE) + #if USB_CFG_MULTIPORT == USB_CFG_ENABLE + if (!(is_init[0] || is_init[1])) + #endif + { + ux_host_stack_class_unregister(ux_host_class_hub_entry); + } + #endif /* !defined(USB_CFG_OTG_USE) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_pstd_driver_release(); /* Clear the information registered in the structure usb_pcdreg_t. */ + usb_pstd_clr_pipe_table(p_ctrl->module_number); + #if (BSP_CFG_RTOS == 1) + if (USB_TRUE == is_connect) + { + _ux_device_stack_disconnect(); + } + + if (USB_IP1 == p_ctrl->module_number) + { + usb_peri_usbx_uninitialize(R_USB_HS0_BASE); + } + else + { + usb_peri_usbx_uninitialize(R_USB_FS0_BASE); + } + #endif /* #if (BSP_CFG_RTOS == 1) */ + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + + g_usb_open_class[p_ctrl->module_number] = 0; + + #if defined(USB_CFG_PMSC_USE) + #if (BSP_CFG_RTOS == 1) + ret_code = usb_peri_usbx_media_close(); + #else + ret_code = r_usb_pmsc_media_close(); + #endif /* (BSP_CFG_RTOS == 1) */ + #endif /* defined(USB_CFG_PMSC_USE) */ + #if (BSP_CFG_RTOS != 0) + #if (BSP_CFG_RTOS == 1) + UINT old_threshold; + TX_THREAD * now_thread; + #endif /* (BSP_CFG_RTOS == 1) */ + /* (USB_NUM_USBIP == 2) */ + #if (BSP_CFG_RTOS == 1) + + /* Settings to prevent preemption. */ + now_thread = tx_thread_identify(); + tx_thread_preemption_change(now_thread, 0, &old_threshold); /* Disable dispatch to the other task */ + + usb_rtos_delete(p_ctrl->module_number); + + /* Remove settings that prevent preemption. */ + tx_thread_preemption_change(now_thread, old_threshold, &old_threshold); /* Enable dispatch ti the other task */ + #else /* (BSP_CFG_RTOS == 1) */ + usb_rtos_delete(p_ctrl->module_number); + #endif /* (BSP_CFG_RTOS == 1) */ + #endif /* (BSP_CFG_RTOS != 0) */ + + /* Be sure set 0 to g_usb_usbmode variable after calling usb_rtos_delete function. */ + g_usb_usbmode[p_ctrl->module_number] = 0; + } + else + { + USB_PRINTF0("### usb_module_stop FSP_ERR_USB_NOT_OPEN\n"); + ret_code = FSP_ERR_USB_NOT_OPEN; + } + + #if defined(USB_CFG_PMSC_USE) + g_usb_pmsc_usbip = USB_VALUE_FFH; + #endif /* defined(USB_CFG_PMSC_USE) */ + + USB_PREEMPTION_ENABLE(); + + return ret_code; +#endif /* defined(USB_CFG_OTG_USE) */ +} + +/**************************************************************************//** + * @brief Bulk/Interrupt data transfer + * + * Requests USB data read (bulk/interrupt transfer). + * The read data is stored in the area specified by argument (p_buf). + * After data read is completed, confirm the operation by checking the return value + * (USB_STATUS_READ_COMPLETE) of the R_USB_GetEvent function. The received data size is set in member + * (size) of the usb_ctrl_t structure. To figure out the size of the data when a read is complete, + * check the return value (USB_STATUS_READ_COMPLETE) of the R_USB_GetEvent function, and then + * refer to the member (size) of the usb_crtl_t structure. + * + * @retval FSP_SUCCESS Successfully completed (Data read request completed). + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_USB_BUSY Data receive request already in process for + * USB device with same device address. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note 1. Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + * @note 2. Allocate the following the storage area when using DMA transfer and specify the start address of the allocated storage area to the 2nd argument(p_buf). + * @note (1). When using High-speed and enabling continuous transfer mode, allocate the storage area with a size that is a multiple of 2048. + * @note (2). When using High-speed and disabling continuous transfer mode, allocate the storage area with a size that is a multiple of 512. + * @note (3). When using Full-speed, allocate the storage area with a size that is a multiple of 64. + * @note 3. Specify the following address to the 2nd argument (p_buf) when using DMA transfer. + * @note (1). When using High-speed module, specify start address of the buffer area aligned on 4-byte boundary. + * @note (2). When using Full-speed module, specify start address of the buffer area aligned on 2-byte boundary. + ******************************************************************************/ +fsp_err_t R_USB_Read (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t destination) +{ + usb_info_t info; + usb_er_t err; + fsp_err_t result = FSP_ERR_USB_FAILED; + + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(USB_NULL != p_api_ctrl) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) && defined(USB_CFG_HCDC_USE) + + /* The value of "type" member is changed to "USB_CLASS_INTERNAL_HCDCC" */ + /* when calling R_USB_HCDC_ControlDataRead function. */ + /* Also support for Host Composite (HCDC + HMSC) since these classes share an instance. */ + if (((usb_class_t) USB_CLASS_INTERNAL_HCDCC == p_ctrl->type) || + ((usb_class_t) USB_CLASS_INTERNAL_HMSC == p_ctrl->type)) + { + p_ctrl->type = (usb_class_t) USB_CLASS_INTERNAL_HCDC; + } +#endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) && defined(USB_CFG_HCDC_USE)*/ + +#if USB_CFG_PARAM_CHECKING_ENABLE + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + FSP_ERROR_RETURN(((USB_CLASS_PCDC <= destination) && (destination < USB_CLASS_END)), FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + FSP_ASSERT(destination) + FSP_ERROR_RETURN(USB_ADDRESS5 >= destination, FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + + FSP_ASSERT(!(((USB_NULL == p_buf)) || (USB_NULL == size))) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + FSP_ERROR_RETURN(!((USB_CLASS_INTERNAL_PCDCC == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_PCDCC2 == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_PVND == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_HVND == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_PMSC == (usb_class_internal_t) p_ctrl->type)), + FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & + (1 << p_ctrl->type)), + FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ + #elif ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + FSP_ERROR_RETURN(!((USB_CLASS_INTERNAL_PCDCC == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_PCDCC2 == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_PVND == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_HVND == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_PMSC == (usb_class_internal_t) (destination & USB_VALUE_7FH))), + FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & + (1 << (destination & USB_VALUE_7FH))), + FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + +#if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (USB_IP0 == p_ctrl->module_number) + { + /* Alignment checking if "p_buf" is 2-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_2_BYTE)), FSP_ERR_USB_PARAMETER) + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* Alignment checking if "p_buf" is 4-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_4_BYTE)), FSP_ERR_USB_PARAMETER) + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ +#endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + + USB_PREEMPTION_DISABLE(); + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + p_ctrl->type = (usb_class_t) (destination & USB_VALUE_7FH); +#endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = destination; +#endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS != result) + { + USB_PREEMPTION_ENABLE(); + + return result; + } + + if (USB_STATUS_CONFIGURED == info.device_status) + { + err = usb_data_read(p_ctrl, p_buf, size); + + if (USB_OK == err) + { + result = FSP_SUCCESS; + } + else if (USB_QOVR == err) + { + result = FSP_ERR_USB_BUSY; + } + else + { + result = FSP_ERR_USB_FAILED; + } + } + else + { + result = FSP_ERR_USB_FAILED; + } + + USB_PREEMPTION_ENABLE(); + + return result; +} + +/**************************************************************************//** + * @brief Bulk/Interrupt data transfer + * + * Requests USB data write (bulk/interrupt transfer). + * Stores write data in area specified by argument (p_buf). + * Set the device class type in usb_ctrl_t structure member (type). + * Confirm after data write is completed by checking the return value (USB_STATUS_WRITE_COMPLETE) + * of the R_USB_GetEvent function. + * For sending a zero-length packet, please refer the following Note. + * + * @retval FSP_SUCCESS Successfully completed. (Data write request completed) + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_USB_BUSY Data write request already in process for + * USB device with same device address. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note 1. The user needs to send the zero-length packet(ZLP) since this USB driver does not send the ZLP automatically. + * @note When sending a ZLP, the user sets USB_NULL in the third argument (size) of R_USB_Write function as follow. + * @note e.g) + * @note R_USB_Write (&g_basic0_ctrl, &g_buf, USB_NULL); + * @note 2. Specify the following address to the 2nd argument (p_buf) when using DMA transfer. + * @note (1). When using High-speed module, specify start address of the buffer area aligned on 4-byte boundary. + * @note (2). When using Full-speed module, specify start address of the buffer area aligned on 2-byte boundary. + * @note 3. Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_Write (usb_ctrl_t * const p_api_ctrl, uint8_t const * const p_buf, uint32_t size, uint8_t destination) +{ + usb_info_t info; + usb_er_t err; + fsp_err_t result = FSP_ERR_USB_FAILED; + + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(USB_NULL != p_api_ctrl) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) && defined(USB_CFG_HCDC_USE) + + /* The value of "type" member is changed to "USB_CLASS_INTERNAL_HCDCC" */ + /* when calling R_USB_HCDC_ControlDataRead function. */ + /* Also support for Host Composite (HCDC + HMSC) since these classes share an instance. */ + if (((usb_class_t) USB_CLASS_INTERNAL_HCDCC == p_ctrl->type) || + ((usb_class_t) USB_CLASS_INTERNAL_HMSC == p_ctrl->type)) + { + p_ctrl->type = (usb_class_t) USB_CLASS_INTERNAL_HCDC; + } +#endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) && defined(USB_CFG_HCDC_USE)*/ + +#if USB_CFG_PARAM_CHECKING_ENABLE + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + FSP_ERROR_RETURN(((USB_CLASS_PCDC <= destination) && (destination < USB_CLASS_END)), FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + FSP_ASSERT(destination) + FSP_ERROR_RETURN(USB_ADDRESS5 >= destination, FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + + FSP_ASSERT(!((USB_NULL == p_buf) && (0 != size))) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + FSP_ERROR_RETURN(!((USB_CLASS_INTERNAL_HCDCC == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_PVND == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_HVND == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_PMSC == (usb_class_internal_t) p_ctrl->type)), + FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & + (1 << p_ctrl->type)), + FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ + #elif ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + FSP_ERROR_RETURN(!((USB_CLASS_INTERNAL_HCDCC == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_PVND == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_HVND == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_PMSC == (usb_class_internal_t) (destination & USB_VALUE_7FH))), + FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & + (1 << (destination & USB_VALUE_7FH))), + FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + +#if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (USB_IP0 == p_ctrl->module_number) + { + /* Alignment checking if "p_buf" is 2-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_2_BYTE)), FSP_ERR_USB_PARAMETER) + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* Alignment checking if "p_buf" is 4-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_4_BYTE)), FSP_ERR_USB_PARAMETER) + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ +#endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + + USB_PREEMPTION_DISABLE(); + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + p_ctrl->type = (usb_class_t) (destination & USB_VALUE_7FH); +#endif /* USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = destination; +#endif /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS != result) + { + USB_PREEMPTION_ENABLE(); + + return result; + } + + if (USB_STATUS_CONFIGURED == info.device_status) + { + err = usb_data_write(p_ctrl, p_buf, size); + + if (USB_OK == err) + { + result = FSP_SUCCESS; + } + else if (USB_QOVR == err) + { + result = FSP_ERR_USB_BUSY; + } + else + { + result = FSP_ERR_USB_FAILED; + } + } + else + { + result = FSP_ERR_USB_FAILED; + } + + USB_PREEMPTION_ENABLE(); + + return result; +} + +/**************************************************************************//** + * @brief Requests a data read/write transfer be terminated + * when a data read/write transfer is being performed. + * + * To stop a data read, set USB_TRANSFER_READ as the argument (type); to stop a data write, + * specify USB_TRANSFER_WRITE as the argument (type). + * + * @retval FSP_SUCCESS Successfully completed. (stop completed) + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_BUSY Stop processing is called multiple times. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_Stop (usb_ctrl_t * const p_api_ctrl, usb_transfer_t direction, uint8_t destination) +{ + usb_info_t info; + usb_er_t err; + fsp_err_t result = FSP_ERR_USB_FAILED; + info.device_status = 0; + + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(USB_NULL != p_api_ctrl) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) && defined(USB_CFG_HCDC_USE) + + /* The value of "type" member is changed to "USB_CLASS_INTERNAL_HCDCC" */ + /* when calling R_USB_HCDC_ControlDataRead function. */ + /* Also support for Host Composite (HCDC + HMSC) since these classes share an instance. */ + if (((usb_class_t) USB_CLASS_INTERNAL_HCDCC == p_ctrl->type) || + ((usb_class_t) USB_CLASS_INTERNAL_HMSC == p_ctrl->type)) + { + p_ctrl->type = (usb_class_t) USB_CLASS_INTERNAL_HCDC; + } +#endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) && defined(USB_CFG_HCDC_USE)*/ + +#if USB_CFG_PARAM_CHECKING_ENABLE + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + FSP_ERROR_RETURN(((USB_CLASS_PCDC <= destination) && (destination < USB_CLASS_END)), FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + FSP_ASSERT(destination) + FSP_ERROR_RETURN(USB_ADDRESS5 >= destination, FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + + FSP_ERROR_RETURN(!((USB_TRANSFER_WRITE != direction) && (USB_TRANSFER_READ != direction)), FSP_ERR_USB_PARAMETER) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + FSP_ERROR_RETURN(!((USB_CLASS_INTERNAL_PVND == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_HVND == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) p_ctrl->type) || + (USB_CLASS_INTERNAL_PMSC == (usb_class_internal_t) p_ctrl->type)), + FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(!(((USB_CLASS_INTERNAL_HCDCC == (usb_class_internal_t) p_ctrl->type) && + (USB_TRANSFER_WRITE == direction)) || + ((USB_CLASS_INTERNAL_PCDCC == (usb_class_internal_t) p_ctrl->type) && + (USB_TRANSFER_READ == direction)) || + ((USB_CLASS_INTERNAL_PCDCC2 == (usb_class_internal_t) p_ctrl->type) && + (USB_TRANSFER_READ == direction))), + FSP_ERR_USB_PARAMETER) + #elif ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + FSP_ERROR_RETURN(!((USB_CLASS_INTERNAL_PVND == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_HVND == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_HMSC == (usb_class_internal_t) (destination & USB_VALUE_7FH)) || + (USB_CLASS_INTERNAL_PMSC == (usb_class_internal_t) (destination & USB_VALUE_7FH))), + FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(!(((USB_CLASS_INTERNAL_HCDCC == (usb_class_internal_t) (destination & USB_VALUE_7FH)) && + (USB_TRANSFER_WRITE == direction)) || + ((USB_CLASS_INTERNAL_PCDCC == (usb_class_internal_t) (destination & USB_VALUE_7FH)) && + (USB_TRANSFER_READ == direction)) || + ((USB_CLASS_INTERNAL_PCDCC2 == (usb_class_internal_t) (destination & USB_VALUE_7FH)) && + (USB_TRANSFER_READ == direction))), + FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + p_ctrl->type = (usb_class_t) (destination & USB_VALUE_7FH); +#endif /* USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = destination; +#endif /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + (void) R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (USB_STATUS_CONFIGURED != info.device_status) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + err = usb_data_stop(p_ctrl, direction); + + if (USB_OK == err) + { + result = FSP_SUCCESS; + } + else if (USB_QOVR == err) + { + result = FSP_ERR_USB_BUSY; + } + else + { + /* Nothing */ + } + + USB_PREEMPTION_ENABLE(); + + return result; +} + +/**************************************************************************//** + * @brief Sends a SUSPEND signal from the USB module assigned to the member + * (module) of the usb_crtl_t structure. + * + * After the suspend request is completed, confirm the operation with the return value + * (USB_STATUS_SUSPEND) of the R_USB_EventGet function. + * + * @retval FSP_SUCCESS Successfully completed. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_USB_BUSY During a suspend request to the specified USB module, + * or when the USB module is already in the suspended state. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_Suspend (usb_ctrl_t * const p_api_ctrl) +{ +#if USB_CFG_MODE == USB_CFG_PERI + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_USB_FAILED; /* Support Host only. */ +#else /* USB_CFG_MODE == USB_CFG_PERI */ + fsp_err_t ret_code = FSP_SUCCESS; + + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + FSP_PARAMETER_NOT_USED(*p_ctrl); + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_utr_t utr; + usb_info_t info; + usb_er_t err; + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + FSP_ERROR_RETURN(USB_MODE_PERI != g_usb_usbmode[p_ctrl->module_number], FSP_ERR_USB_FAILED) + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(USB_NULL != p_api_ctrl) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = USB_DEVICEADDR; + + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS != ret_code) + { + USB_PREEMPTION_ENABLE(); + + return ret_code; + } + + if (USB_STATUS_CONFIGURED != info.device_status) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + utr.ip = p_ctrl->module_number; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + #if (BSP_CFG_RTOS == 0) + if (USB_NULL != (g_usb_change_device_state[p_ctrl->module_number] & (1 << USB_STATUS_SUSPEND))) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_BUSY; + } + + err = usb_hstd_change_device_state(&utr, + (usb_cb_t) &usb_hstd_suspend_complete, + USB_DO_GLOBAL_SUSPEND, + USB_DEVICEADDR); + + if (USB_OK == err) + { + g_usb_change_device_state[p_ctrl->module_number] |= (1 << USB_STATUS_SUSPEND); + } + else + { + ret_code = FSP_ERR_USB_FAILED; + } + + #else /* (BSP_CFG_RTOS == 0) */ + if (USB_YES == gs_usb_suspend_ing[p_ctrl->module_number]) + { + ret_code = FSP_ERR_USB_BUSY; + } + else + { + gs_usb_suspend_ing[p_ctrl->module_number] = USB_YES; + } + + err = usb_hstd_change_device_state(&utr, + (usb_cb_t) &usb_hstd_suspend_complete, + USB_DO_GLOBAL_SUSPEND, + USB_DEVICEADDR); + + if (USB_OK != err) + { + ret_code = FSP_ERR_USB_FAILED; + } + gs_usb_suspend_ing[p_ctrl->module_number] = USB_NO; + #endif /* (BSP_CFG_RTOS == 0) */ + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + USB_PREEMPTION_ENABLE(); + + return ret_code; +#endif /* USB_CFG_MODE == USB_CFG_PERI */ +} + +/**************************************************************************//** + * @brief Sends a RESUME signal from the USB module assigned to the + * member (module) of the usb_ctrl_tstructure. + * + * After the resume request is completed, confirm the operation with the return + * value (USB_STATUS_RESUME) of the R_USB_EventGet function + * + * @retval FSP_SUCCESS Successfully completed. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_USB_BUSY Resume already requested for same device address. + * (USB host mode only) + * @retval FSP_ERR_USB_NOT_SUSPEND USB device is not in the SUSPEND state. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_Resume (usb_ctrl_t * const p_api_ctrl) +{ +#if USB_CFG_MODE == USB_CFG_PERI + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_USB_FAILED; /* Support Host only. */ +#else /* USB_CFG_MODE == USB_CFG_PERI */ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + usb_utr_t utr; + usb_er_t err; + + fsp_err_t ret_code = FSP_ERR_USB_FAILED; + usb_info_t info; + info.device_status = 0; + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(USB_NULL != p_api_ctrl) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif + + FSP_ERROR_RETURN(USB_MODE_PERI != g_usb_usbmode[p_ctrl->module_number], FSP_ERR_USB_PARAMETER) + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (USB_STATUS_SUSPEND != info.device_status) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_NOT_SUSPEND; + } + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ip = p_ctrl->module_number; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + + #if (BSP_CFG_RTOS == 0) + if (USB_NULL != (g_usb_change_device_state[p_ctrl->module_number] & (1 << USB_STATUS_RESUME))) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_BUSY; + } + + err = usb_hstd_change_device_state(&utr, + (usb_cb_t) &usb_hstd_resume_complete, + USB_DO_GLOBAL_RESUME, + p_ctrl->device_address); + if (USB_OK == err) + { + g_usb_change_device_state[p_ctrl->module_number] |= (1 << USB_STATUS_RESUME); + } + else + { + ret_code = FSP_ERR_USB_FAILED; + } + + #else /* (BSP_CFG_RTOS == 0) */ + if (USB_YES == g_usb_resume_ing[p_ctrl->module_number]) + { + ret_code = FSP_ERR_USB_BUSY; + } + else + { + g_usb_resume_ing[p_ctrl->module_number] = USB_YES; + } + + if (FSP_ERR_USB_BUSY == ret_code) + { + USB_PREEMPTION_ENABLE(); + + return ret_code; + } + + err = usb_hstd_change_device_state(&utr, + (usb_cb_t) &usb_hstd_resume_complete, + USB_DO_GLOBAL_RESUME, + p_ctrl->device_address); + if (USB_OK != err) + { + ret_code = FSP_ERR_USB_FAILED; + } + g_usb_resume_ing[p_ctrl->module_number] = USB_NO; + #endif /* (BSP_CFG_RTOS == 0) */ + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + USB_PREEMPTION_ENABLE(); + + return ret_code; +#endif /* USB_CFG_MODE == USB_CFG_PERI */ +} + +/**************************************************************************//** + * @brief Specifies starting or stopping the VBUS supply. + * + * @retval FSP_SUCCESS Successful completion. (VBUS supply start/stop completed) + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_VbusSet (usb_ctrl_t * const p_api_ctrl, uint16_t state) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if defined(USB_CFG_OTG_USE) + uint16_t syssts; +#endif /* defined(USB_CFG_OTG_USE) */ + +#if (USB_CFG_MODE == USB_CFG_PERI) + FSP_PARAMETER_NOT_USED(state); + FSP_PARAMETER_NOT_USED(*p_ctrl); + + return FSP_ERR_USB_FAILED; +#else + usb_utr_t utr; + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(USB_NULL != p_api_ctrl) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif /* defined(BSP_BOARD_GROUP_RA2A1) */ + + FSP_ERROR_RETURN(!((USB_ON != state) && (USB_OFF != state)), FSP_ERR_USB_PARAMETER) + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + utr.ip = p_ctrl->module_number; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + + if (USB_ON == state) + { + usb_hstd_vbus_control(&utr, (uint16_t) USB_VBON); + } + else + { + usb_hstd_vbus_control(&utr, (uint16_t) USB_VBOFF); + #if defined(USB_CFG_OTG_USE) + if (1 == g_is_A_device[utr.ip]) + { + usb_cpu_delay_xms((uint16_t) USB_VALUE_50); + + syssts = hw_usb_read_syssts(&utr); + + if (USB_SE0 == (syssts & USB_LNST)) + { + utr.ipp->INTENB1 |= USB_BCHGE; + } + } + else + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + #endif /* defined (USB_CFG_OTG_USE) */ + } + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +#endif /* (USB_CFG_MODE == USB_CFG_PERI) */ +} + +/**************************************************************************//** + * @brief Obtains completed USB-related events. + * + * @retval FSP_SUCCESS Successful completion. (VBUS supply start/stop completed) + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + ******************************************************************************/ +fsp_err_t R_USB_InfoGet (usb_ctrl_t * const p_api_ctrl, usb_info_t * p_info, uint8_t destination) +{ + fsp_err_t ret_code = FSP_SUCCESS; + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + usb_utr_t utr; + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + uint32_t status; + FSP_PARAMETER_NOT_USED(destination); +#endif /* ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + FSP_ASSERT(p_info) + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + FSP_ASSERT(destination) + FSP_ERROR_RETURN(USB_ADDRESS5 >= destination, FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif /* #if defined(BSP_BOARD_GROUP_RA2A1) */ +#else /* USB_CFG_PARAM_CHECKING_ENABLE */ + FSP_PARAMETER_NOT_USED(*p_ctrl); +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + FSP_ERROR_RETURN(0 != g_usb_open_class[p_ctrl->module_number], FSP_ERR_USB_FAILED) + + USB_PREEMPTION_DISABLE(); + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = destination; +#endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + + p_info->device_status = USB_STATUS_DETACH; /* Initialized for warning measures. */ + + utr.ip = p_ctrl->module_number; + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + + /* Set USB Device class */ + switch (g_usb_hstd_device_info[utr.ip][p_ctrl->device_address][3]) + { + case USB_IFCLS_CDC: + { + p_info->class_type = (uint8_t) USB_CLASS_PCDC; + break; + } + + case USB_IFCLS_HID: + { + p_info->class_type = (uint8_t) USB_CLASS_PHID; + break; + } + + case USB_IFCLS_MAS: + { + p_info->class_type = (uint8_t) USB_CLASS_PMSC; + break; + } + + case USB_IFCLS_VEN: + { + p_info->class_type = (uint8_t) USB_CLASS_PVND; + break; + } + + default: + { + p_info->class_type = USB_NULL; + break; + } + } + + /* Set USB connect speed */ + switch (g_usb_hstd_device_info[utr.ip][p_ctrl->device_address][4]) + { + case USB_NOCONNECT: + { + p_info->speed = USB_NULL; + break; + } + + case USB_HSCONNECT: + { + p_info->speed = USB_SPEED_HS; + break; + } + + case USB_FSCONNECT: + { + p_info->speed = USB_SPEED_FS; + break; + } + + case USB_LSCONNECT: + { + p_info->speed = USB_SPEED_LS; + break; + } + + default: + { + p_info->speed = USB_NULL; + break; + } + } + + /* Set USB device state */ + switch (g_usb_hstd_device_info[utr.ip][p_ctrl->device_address][1]) + { + case USB_POWERED: /* Power state */ + { + p_info->device_status = USB_STATUS_POWERED; + break; + } + + case USB_DEFAULT: /* Default state */ + { + p_info->device_status = USB_STATUS_DEFAULT; + break; + } + + case USB_ADDRESS: /* Address state */ + { + p_info->device_status = USB_STATUS_ADDRESS; + break; + } + + case USB_CONFIGURED: /* Configured state */ + { + p_info->device_status = USB_STATUS_CONFIGURED; + break; + } + + case USB_SUSPENDED: /* Suspend state */ + { + p_info->device_status = USB_STATUS_SUSPEND; + break; + } + + case USB_DETACHED: /* Disconnect(VBUSon) state */ + { + p_info->device_status = USB_STATUS_DETACH; + break; + } + + default: /* Error */ + { + p_info->device_status = USB_NULL; + break; + } + } + + /* Set USB Peri BC port state */ + #if USB_CFG_BC == USB_CFG_ENABLE + if (USB_DEVICEADDR == p_ctrl->device_address) /* Check Root port address */ + { + if (USB_BC_STATE_CDP == g_usb_hstd_bc[utr.ip].state) + { + p_info->bcport = USB_BCPORT_CDP; + } + else + { + p_info->bcport = USB_BCPORT_SDP; /* USB_SDP/USB_CDP/USB_DCP */ + } + } + else + { + p_info->bcport = USB_BCPORT_SDP; /* USB_SDP/USB_CDP/USB_DCP */ + } + + #else /* #if USB_CFG_BC == USB_CFG_ENABLE */ + p_info->bcport = USB_BCPORT_SDP; /* USB_SDP/USB_CDP/USB_DCP */ + #endif /* #if USB_CFG_BC == USB_CFG_ENABLE */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + p_info->class_type = USB_NULL; /* Device class */ + switch (usb_cstd_port_speed(&utr)) + { + case USB_NOCONNECT: + { + p_info->speed = USB_NULL; + break; + } + + case USB_HSCONNECT: + { + p_info->speed = USB_SPEED_HS; + break; + } + + case USB_FSCONNECT: + { + p_info->speed = USB_SPEED_FS; + break; + } + + case USB_LSCONNECT: + { + p_info->speed = USB_SPEED_LS; + break; + } + + default: + { + p_info->speed = USB_NULL; + break; + } + } + + status = hw_usb_read_intsts(p_ctrl->module_number); + switch ((uint16_t) (status & USB_DVSQ)) + { + case USB_DS_POWR: /* Power state */ + { + p_info->device_status = USB_STATUS_DETACH; + break; + } + + case USB_DS_DFLT: /* Default state */ + { + p_info->device_status = USB_STATUS_DEFAULT; + break; + } + + case USB_DS_ADDS: /* Address state */ + { + p_info->device_status = USB_STATUS_ADDRESS; + break; + } + + case USB_DS_CNFG: /* Configured state */ + { + p_info->device_status = USB_STATUS_CONFIGURED; + break; + } + + case USB_DS_SPD_POWR: /* Power suspend state */ + case USB_DS_SPD_DFLT: /* Default suspend state */ + case USB_DS_SPD_ADDR: /* Address suspend state */ + case USB_DS_SPD_CNFG: /* Configured Suspend state */ + { + p_info->device_status = USB_STATUS_SUSPEND; + break; + } + + default: /* Error */ + { + break; /* p_info->device_status = USB_STS_ERROR; */ + } + } + + #if USB_CFG_BC == USB_CFG_ENABLE + p_info->bcport = (uint8_t) g_usb_bc_detect; /* USB_SDP/USB_CDP/USB_DCP */ + #else /* USB_CFG_BC == USB_CFG_ENABLE */ + p_info->bcport = USB_BCPORT_SDP; /* USB_SDP */ + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + ret_code = FSP_SUCCESS; +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + + USB_PREEMPTION_ENABLE(); + + return ret_code; +} + +/**************************************************************************//** + * @brief Requests a data read (Bulk/Interrupt transfer) via the pipe specified in the argument. + * + * The read data is stored in the area specified in the argument (p_buf). + * After the data read is completed, confirm the operation with the R_USB_GetEvent function + * return value(USB_STATUS_READ_COMPLETE). + * To figure out the size of the data when a read is complete, check the return + * value (USB_STATUS_READ_COMPLETE) of the R_USB_GetEvent function, and then + * refer to the member (size) of the usb_crtl_t structure. + * + * @retval FSP_SUCCESS Successfully completed. + * @retval FSP_ERR_USB_BUSY Specified pipe now handling data receive/send request. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note 1. Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + * @note 2. Allocate the following the storage area when using DMA transfer and specify the start address of the allocated storage area to the 2nd argument(p_buf). + * @note (1). When using High-speed and enabling continuous transfer mode, allocate the storage area with a size that is a multiple of 2048. + * @note (2). When using High-speed and disabling continuous transfer mode, allocate the storage area with a size that is a multiple of 512. + * @note (3). When using Full-speed, allocate the storage area with a size that is a multiple of 64. + * @note 3. Specify the following address to the 2nd argument (p_buf) when using DMA transfer. + * @note (1). When using High-speed module, specify start address of the buffer area aligned on 4-byte boundary. + * @note (2). When using Full-speed module, specify start address of the buffer area aligned on 2-byte boundary. + ******************************************************************************/ +fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) + FSP_PARAMETER_NOT_USED(*p_ctrl); + FSP_PARAMETER_NOT_USED(*p_buf); + FSP_PARAMETER_NOT_USED(size); + FSP_PARAMETER_NOT_USED(pipe_number); + + return FSP_ERR_USB_FAILED; +#else /* !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) */ + fsp_err_t ret_code = FSP_ERR_USB_FAILED; + usb_utr_t * p_tran_data; + #if (BSP_CFG_RTOS != 0) + usb_utr_t tran_data; + #endif /* (BSP_CFG_RTOS != 0) */ + + usb_er_t err; + usb_info_t info; + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + + FSP_ERROR_RETURN(((USB_MIN_PIPE_NO <= pipe_number) && (pipe_number <= USB_MAX_PIPE_NO)), FSP_ERR_USB_PARAMETER) + + FSP_ASSERT(!((USB_NULL == p_buf) || (USB_NULL == size))) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & + (1 << p_ctrl->type)), + FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (USB_IP0 == p_ctrl->module_number) + { + /* Alignment checking if "p_buf" is 2-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_2_BYTE)), FSP_ERR_USB_PARAMETER) + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* Alignment checking if "p_buf" is 4-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_4_BYTE)), FSP_ERR_USB_PARAMETER) + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) */ + + USB_PREEMPTION_DISABLE(); + + p_ctrl->pipe = pipe_number; + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = USB_ADDRESS1; + #endif /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS != ret_code) + { + USB_PREEMPTION_ENABLE(); + + return ret_code; + } + + if (USB_STATUS_CONFIGURED == info.device_status) + { + /* PIPE Transfer set */ + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data; + #else /* (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_hdata[p_ctrl->module_number][p_ctrl->pipe]; + #endif /* (BSP_CFG_RTOS != 0) */ + + p_tran_data->ip = p_ctrl->module_number; + p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_tran_data->ip); + p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ + p_tran_data->p_tranadr = p_buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + p_tran_data->p_setup = 0; + p_tran_data->complete = usb_hvnd_read_complete; /* Callback function */ + p_tran_data->segment = USB_TRAN_END; + p_tran_data->read_req_len = size; /* Data Size */ + + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + + err = usb_hstd_transfer_start(p_tran_data); /* USB Transfer Start */ + if (USB_OK == err) + { + ret_code = FSP_SUCCESS; + } + else if (USB_QOVR == err) + { + ret_code = FSP_ERR_USB_BUSY; + } + else + { + ret_code = FSP_ERR_USB_FAILED; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data; + #else /* (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_pdata[p_ctrl->pipe]; + #endif /* (BSP_CFG_RTOS != 0) */ + + p_tran_data->ip = p_ctrl->module_number; /* USB Module Number */ + p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ + p_tran_data->p_tranadr = p_buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + p_tran_data->complete = (usb_cb_t) &usb_pvnd_read_complete; /* Callback function */ + p_tran_data->read_req_len = size; /* Data Size */ + p_tran_data->p_setup = 0; + + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + + err = usb_pstd_transfer_start(p_tran_data); /* USB Transfer Start */ + if (USB_OK == err) + { + ret_code = FSP_SUCCESS; + } + else if (USB_QOVR == err) + { + ret_code = FSP_ERR_USB_BUSY; + } + else + { + ret_code = FSP_ERR_USB_FAILED; + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + } + else + { + ret_code = FSP_ERR_USB_FAILED; + } + + USB_PREEMPTION_ENABLE(); + + return ret_code; +#endif /* !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) */ +} + +/**************************************************************************//** + * @brief Requests a data write (Bulk/Interrupt transfer). + * + * The write data is stored in the area specified in the argument (p_buf). + * After data write is completed, confirm the operation with the return value + * (USB_STATUS_WRITE_COMPLETE) of the EventGet function. + * For sending a zero-length packet, please refer the following Note. + * + * @retval FSP_SUCCESS Successfully completed. + * @retval FSP_ERR_USB_BUSY Specified pipe now handling data receive/send request. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note 1. The user needs to send the zero-length packet(ZLP) since this USB driver does not send the ZLP automatically. + * @note When sending a ZLP, the user sets USB_NULL in the third argument (size) of R_USB_PipeWrite function as follow. + * @note e.g) + * @note R_USB_PipeWrite (&g_basic0_ctrl, &g_buf, USB_NULL, pipe_number); + * @note 2. Specify the following address to the 2nd argument (p_buf) when using DMA transfer. + * @note (1). When using High-speed module, specify start address of the buffer area aligned on 4-byte boundary. + * @note (2). When using Full-speed module, specify start address of the buffer area aligned on 2-byte boundary. + * @note 3. Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) + FSP_PARAMETER_NOT_USED(*p_ctrl); + FSP_PARAMETER_NOT_USED(*p_buf); + FSP_PARAMETER_NOT_USED(size); + FSP_PARAMETER_NOT_USED(pipe_number); + + return FSP_ERR_USB_FAILED; +#else + usb_er_t err; + fsp_err_t ret_code; + usb_info_t info; + usb_utr_t * p_tran_data; + #if (BSP_CFG_RTOS != 0) + usb_utr_t tran_data; + #endif /* (BSP_CFG_RTOS != 0) */ + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(((USB_MIN_PIPE_NO <= pipe_number) && (pipe_number <= USB_MAX_PIPE_NO)), FSP_ERR_USB_PARAMETER) + + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + FSP_ASSERT(!((USB_NULL == p_buf) && (0 != size))) + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & (1 << p_ctrl->type)), FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ /* USB_CFG_PARAM_CHECKING_ENABLE */ + + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (USB_IP0 == p_ctrl->module_number) + { + /* Alignment checking if "p_buf" is 2-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_2_BYTE)), FSP_ERR_USB_PARAMETER) + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* Alignment checking if "p_buf" is 4-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_4_BYTE)), FSP_ERR_USB_PARAMETER) + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) */ + + USB_PREEMPTION_DISABLE(); + + p_ctrl->pipe = pipe_number; + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = USB_ADDRESS1; + #endif /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS != ret_code) + { + USB_PREEMPTION_ENABLE(); + + return ret_code; + } + + if (USB_STATUS_CONFIGURED == info.device_status) + { + /* PIPE Transfer set */ + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data; + #else /* (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_hdata[p_ctrl->module_number][p_ctrl->pipe]; + #endif /* (BSP_CFG_RTOS != 0) */ + + p_tran_data->ip = p_ctrl->module_number; + p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_ctrl->module_number); + p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ + p_tran_data->p_tranadr = p_buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + p_tran_data->complete = usb_hvnd_write_complete; /* Callback function */ + p_tran_data->segment = USB_TRAN_END; + p_tran_data->p_setup = 0; + + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + + err = usb_hstd_transfer_start(p_tran_data); + if (USB_OK == err) + { + ret_code = FSP_SUCCESS; + } + else if (USB_QOVR == err) + { + ret_code = FSP_ERR_USB_BUSY; + } + else + { + ret_code = FSP_ERR_USB_FAILED; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data; + #else /* (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_pdata[p_ctrl->pipe]; + #endif /* (BSP_CFG_RTOS != 0) */ + + p_tran_data->ip = p_ctrl->module_number; /* USB Module Number */ + p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ + p_tran_data->p_tranadr = p_buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + p_tran_data->complete = usb_pvnd_write_complete; /* Callback function */ + p_tran_data->p_setup = 0; + + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + + err = usb_pstd_transfer_start(p_tran_data); + + if (USB_OK == err) + { + ret_code = FSP_SUCCESS; + } + else if (USB_QOVR == err) + { + ret_code = FSP_ERR_USB_BUSY; + } + else + { + ret_code = FSP_ERR_USB_FAILED; + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + } + else + { + ret_code = FSP_ERR_USB_FAILED; + } + + USB_PREEMPTION_ENABLE(); + + return ret_code; +#endif /* #if !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) */ +} + +/**************************************************************************//** + * @brief Terminates a data read/write operation. + * + * @retval FSP_SUCCESS Successfully completed. (Stop request completed) + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_PipeStop (usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) + FSP_PARAMETER_NOT_USED(*p_ctrl); + FSP_PARAMETER_NOT_USED(pipe_number); + + return FSP_ERR_USB_FAILED; +#else + usb_er_t err = FSP_ERR_USB_FAILED; + fsp_err_t ret_code = FSP_ERR_USB_FAILED; + usb_info_t info = {USB_NULL, USB_NULL, USB_NULL, USB_NULL}; + usb_utr_t utr; + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(USB_PIPE0 != pipe_number, FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(USB_MAXPIPE_NUM > pipe_number, FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & (1 << p_ctrl->type)), FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + utr.ip = p_ctrl->module_number; /* Update USB module number */ + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + p_ctrl->device_address = USB_ADDRESS1; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + p_ctrl->pipe = pipe_number; + + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (USB_STATUS_CONFIGURED != info.device_status) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + err = usb_hstd_transfer_end(&utr, p_ctrl->pipe, (uint16_t) USB_DATA_STOP); + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + err = usb_pstd_transfer_end(&utr, p_ctrl->pipe); + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + + if (USB_OK == err) + { + ret_code = FSP_SUCCESS; + } + + USB_PREEMPTION_ENABLE(); + + return ret_code; +#endif /* !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) */ +} + +/**************************************************************************//** + * @brief Gets the selected pipe number (number of the pipe that has completed initialization) via bit map information. + * + * The bit map information is stored in the area specified in argument (p_pipe). + * Based on the information (module member and address member) assigned to the usb_ctrl_t structure, + * obtains the PIPE information of that USB device. + * + * @retval FSP_SUCCESS Successfully completed. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + ******************************************************************************/ +fsp_err_t R_USB_UsedPipesGet (usb_ctrl_t * const p_api_ctrl, uint16_t * p_pipe, uint8_t destination) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + usb_info_t info; + uint32_t pipe_no; + + info.device_status = 0; + + FSP_PARAMETER_NOT_USED(*p_ctrl); +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + FSP_PARAMETER_NOT_USED(destination); +#endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(!((USB_NULL == p_ctrl) || (USB_NULL == p_pipe))) + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + FSP_ASSERT(destination) + FSP_ERROR_RETURN(USB_ADDRESS5 >= destination, FSP_ERR_USB_PARAMETER) + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(USB_IP1 != p_ctrl->module_number, FSP_ERR_USB_PARAMETER) + #endif /* defined(BSP_BOARD_GROUP_RA2A1) */ +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_ctrl->device_address = destination; +#endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + } + + R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (USB_STATUS_CONFIGURED != info.device_status) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + /* Get PIPE Number from Endpoint address */ + *p_pipe = ((uint16_t) 1 << USB_PIPE0); + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + for (pipe_no = USB_MIN_PIPE_NO; pipe_no < (USB_MAX_PIPE_NO + 1); pipe_no++) + { + if (USB_TRUE == g_usb_pipe_table[p_ctrl->module_number][pipe_no].use_flag) + { + if ((((uint16_t) p_ctrl->device_address) << USB_DEVADDRBIT) == + (uint16_t) (g_usb_pipe_table[p_ctrl->module_number][pipe_no].pipe_maxp & USB_DEVSEL)) + { + (*p_pipe) = (uint16_t) ((*p_pipe) | (uint16_t) 1 << pipe_no); + } + } + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + for (pipe_no = USB_MIN_PIPE_NO; pipe_no < (USB_MAX_PIPE_NO + 1); pipe_no++) + { + if (USB_TRUE == g_usb_pipe_table[p_ctrl->module_number][pipe_no].use_flag) + { + (*p_pipe) = (uint16_t) ((*p_pipe) | (uint16_t) (1 << pipe_no)); + } + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief Gets the following pipe information regarding the pipe specified in the + * argument (p_ctrl) member (pipe): endpoint number, transfer type, + * transfer direction and maximum packet size. + * + * The obtained pipe information is stored in the area specified in the argument (p_info). + * + * @retval FSP_SUCCESS Successfully completed. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + ******************************************************************************/ +fsp_err_t R_USB_PipeInfoGet (usb_ctrl_t * const p_api_ctrl, usb_pipe_t * p_info, uint8_t pipe_number) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + usb_info_t info; + info.device_status = 0; + uint32_t pipe_type; + fsp_err_t result = FSP_ERR_ASSERTION; + usb_utr_t utr; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + FSP_ASSERT(p_info) + FSP_ASSERT(pipe_number) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) + + FSP_ERROR_RETURN(!(USB_MAXPIPE_NUM < pipe_number), FSP_ERR_USB_PARAMETER) + + #if defined(BSP_BOARD_GROUP_RA2A1) + FSP_ERROR_RETURN(!((USB_IP1 == p_ctrl->module_number) && (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number])), + FSP_ERR_USB_PARAMETER) + #endif +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + p_ctrl->pipe = pipe_number; + + utr.ip = p_ctrl->module_number; + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + p_ctrl->device_address = USB_ADDRESS1; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (USB_STATUS_CONFIGURED != info.device_status) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_info->endpoint = usb_hstd_pipe_to_epadr(&utr, p_ctrl->pipe); + pipe_type = usb_cstd_get_pipe_type(&utr, p_ctrl->pipe); + + switch (pipe_type) + { + case USB_TYPFIELD_ISO: + { + p_info->transfer_type = USB_TRANSFER_TYPE_ISO; /* Set Isochronous */ + break; + } + + case USB_TYPFIELD_BULK: + { + p_info->transfer_type = USB_TRANSFER_TYPE_BULK; /* Set Bulk */ + break; + } + + case USB_TYPFIELD_INT: + { + p_info->transfer_type = USB_TRANSFER_TYPE_INT; /* Set Interrupt */ + break; + } + + default: + { + result = FSP_ERR_USB_FAILED; + break; + } + } + + if (FSP_ERR_USB_FAILED != result) + { + p_info->maxpacketsize = usb_cstd_get_maxpacket_size(&utr, p_ctrl->pipe); /* Set Max packet size */ + result = FSP_SUCCESS; + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + + /* Get PIPE Number from Endpoint address */ + p_info->endpoint = (uint8_t) (g_usb_pipe_table[p_ctrl->module_number][p_ctrl->pipe].pipe_cfg & USB_EPNUMFIELD); /* Set EP num. */ + if (USB_DIR_P_IN == (g_usb_pipe_table[p_ctrl->module_number][p_ctrl->pipe].pipe_cfg & USB_DIRFIELD)) /* Check dir */ + { + p_info->endpoint |= USB_EP_DIR_IN; /* Set DIR IN */ + } + + pipe_type = usb_cstd_get_pipe_type(&utr, p_ctrl->pipe); + + switch (pipe_type) + { + case USB_TYPFIELD_ISO: + { + p_info->transfer_type = USB_TRANSFER_TYPE_ISO; /* Set Isochronous */ + break; + } + + case USB_TYPFIELD_BULK: + { + p_info->transfer_type = USB_TRANSFER_TYPE_BULK; /* Set Bulk */ + break; + } + + case USB_TYPFIELD_INT: + { + p_info->transfer_type = USB_TRANSFER_TYPE_INT; /* Set Interrupt */ + break; + } + + default: + { + result = FSP_ERR_USB_FAILED; + break; + } + } + + if (FSP_ERR_USB_FAILED != result) + { + p_info->maxpacketsize = usb_cstd_get_maxpacket_size(&utr, p_ctrl->pipe); /* Set Max packet size */ + result = FSP_SUCCESS; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + + USB_PREEMPTION_ENABLE(); + + return result; +} + +/**************************************************************************//** + * @brief This API enables or disables pull-up of D+/D- line. + * + * @retval FSP_SUCCESS Successful completion. (Pull-up enable/disable setting completed) + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_PullUp (usb_ctrl_t * const p_api_ctrl, uint8_t state) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if (USB_CFG_MODE == USB_CFG_HOST) + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(state); + + return FSP_ERR_USB_FAILED; +#else /* USB_CFG_MODE == USB_CFG_HOST */ + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + + /* Argument Checking */ + FSP_ERROR_RETURN(!((USB_ON != state) && (USB_OFF != state)), FSP_ERR_USB_PARAMETER) + #endif /* #if USB_CFG_PARAM_CHECKING_ENABLE */ + + FSP_ERROR_RETURN(!(USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]), FSP_ERR_USB_FAILED) /* Support Peri only. */ + + USB_PREEMPTION_DISABLE(); + + hw_usb_pcontrol_dprpu(p_ctrl->module_number, state); + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +#endif /* USB_CFG_MODE == USB_CFG_HOST */ +} /* End of function R_USB_PullUp */ + +/**************************************************************************//** + * @brief Performs settings and transmission processing when transmitting a setup packet. + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @retval FSP_ERR_USB_BUSY Specified pipe now handling data receive/send request. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_HostControlTransfer (usb_ctrl_t * const p_api_ctrl, + usb_setup_t * p_setup, + uint8_t * p_buf, + uint8_t device_address) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + usb_er_t err = USB_ERROR; + fsp_err_t result = FSP_ERR_USB_FAILED; + usb_info_t info; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + FSP_ASSERT(p_setup) + FSP_ASSERT(!((USB_NULL == p_buf) && (0 != p_setup->request_length))) + FSP_ASSERT(device_address) + + FSP_ERROR_RETURN(USB_MAXDEVADDR >= device_address, FSP_ERR_USB_PARAMETER) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + result = R_USB_InfoGet(p_ctrl, &info, device_address); + if (FSP_SUCCESS != result) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + p_ctrl->device_address = device_address; + p_ctrl->setup.request_type = p_setup->request_type; + p_ctrl->setup.request_value = p_setup->request_value; + p_ctrl->setup.request_index = p_setup->request_index; + p_ctrl->setup.request_length = p_setup->request_length; + + if ((p_ctrl->setup.request_type & USB_DEV_TO_HOST) == USB_DEV_TO_HOST) + { + err = usb_ctrl_read(p_ctrl, p_buf, p_ctrl->setup.request_length); /* Request Control transfer */ + } + else + { + err = usb_ctrl_write(p_ctrl, p_buf, p_ctrl->setup.request_length); /* Request Control transfer */ + } + + if (err == USB_QOVR) + { + result = FSP_ERR_USB_BUSY; + } + else if (err == USB_ERROR) + { + result = FSP_ERR_USB_FAILED; + } + else + { + result = FSP_SUCCESS; + } + + USB_PREEMPTION_ENABLE(); + + return result; +} + +/**************************************************************************//** + * @brief Receives data sent by control transfer. + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_BUSY Specified pipe now handling data receive/send request. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_PeriControlDataGet (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + usb_er_t err = USB_ERROR; + fsp_err_t result = FSP_ERR_USB_FAILED; + usb_info_t info; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + FSP_ASSERT(p_buf) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS != result) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + err = usb_ctrl_read(p_ctrl, p_buf, size); /* Request Control transfer */ + if (err == USB_QOVR) + { + result = FSP_ERR_USB_BUSY; + } + else if (err == USB_ERROR) + { + result = FSP_ERR_USB_FAILED; + } + else + { + result = FSP_SUCCESS; + } + + USB_PREEMPTION_ENABLE(); + + return result; +} + +/**************************************************************************//** + * @brief Performs transfer processing for control transfer. + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_BUSY Specified pipe now handling data receive/send request. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_PeriControlDataSet (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + usb_er_t err = USB_ERROR; + fsp_err_t result = FSP_ERR_USB_FAILED; + usb_info_t info; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + FSP_ASSERT(p_buf) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS != result) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + err = usb_ctrl_write(p_ctrl, p_buf, size); /* Request Control transfer */ + if (err == USB_QOVR) + { + result = FSP_ERR_USB_BUSY; + } + else if (err == USB_ERROR) + { + result = FSP_ERR_USB_FAILED; + } + else + { + result = FSP_SUCCESS; + } + + USB_PREEMPTION_ENABLE(); + + return result; +} + +/**************************************************************************//** + * @brief Set the response to the setup packet. + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_PARAMETER Parameter error. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_PeriControlStatusSet (usb_ctrl_t * const p_api_ctrl, usb_setup_status_t status) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + +#if (USB_CFG_MODE == USB_CFG_HOST) + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(status); + + return FSP_ERR_USB_FAILED; +#else /* USB_CFG_MODE == USB_CFG_HOST */ + fsp_err_t result = FSP_ERR_USB_FAILED; + usb_info_t info; + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + result = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); + if (FSP_SUCCESS != result) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + + p_ctrl->status = (uint16_t) status; + + hw_usb_pcontrol_dcpctr_pid(p_ctrl->module_number, (uint16_t) status); + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +#endif /* #if (USB_CFG_MODE == USB_CFG_HOST) */ +} + +/**************************************************************************//** + * @brief Sends a remote wake-up signal to the connected Host. + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @retval FSP_ERR_USB_NOT_SUSPEND Device is not suspended. + * @retval FSP_ERR_USB_BUSY The device is in resume operation. + * @note Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). + ******************************************************************************/ +fsp_err_t R_USB_RemoteWakeup (usb_ctrl_t * const p_api_ctrl) +{ + fsp_err_t ret_code = FSP_ERR_USB_FAILED; +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + usb_utr_t utr; + uint16_t ret_val; + + #if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + + utr.ip = p_ctrl->module_number; + + #if (BSP_CFG_RTOS == 0) + ret_val = usb_cstd_remote_wakeup(&utr); + switch (ret_val) + { + case USB_OK: + { + ret_code = FSP_SUCCESS; + break; + } + + case USB_QOVR: + { + ret_code = FSP_ERR_USB_NOT_SUSPEND; + break; + } + + case USB_ERROR: + default: + { + ret_code = FSP_ERR_USB_FAILED; + break; + } + } + + #else /* (BSP_CFG_RTOS == 0) */ + if (USB_YES == g_usb_resume_ing[p_ctrl->module_number]) + { + ret_code = FSP_ERR_USB_BUSY; + } + else + { + g_usb_resume_ing[p_ctrl->module_number] = USB_YES; + } + + if (FSP_ERR_USB_BUSY == ret_code) + { + USB_PREEMPTION_ENABLE(); + + return ret_code; + } + + ret_val = usb_cstd_remote_wakeup(&utr); + switch (ret_val) + { + case USB_OK: + { + ret_code = FSP_SUCCESS; + break; + } + + case USB_QOVR: + { + ret_code = FSP_ERR_USB_NOT_SUSPEND; + break; + } + + case USB_ERROR: + default: + { + ret_code = FSP_ERR_USB_FAILED; + break; + } + } + g_usb_resume_ing[p_ctrl->module_number] = USB_NO; + #endif /* BSP_CFG_RTOS == 0 */ +#else /*((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI)*/ + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif /*((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI)*/ + + USB_PREEMPTION_ENABLE(); + + return ret_code; +} + +/**************************************************************************//** + * @brief Activate USB Driver for USB Peripheral BareMetal. + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @note Call this API in the in the infinite loop of the application program or a timer interrupt. + ******************************************************************************/ +fsp_err_t R_USB_DriverActivate (usb_ctrl_t * const p_api_ctrl) +{ + fsp_err_t err = FSP_ERR_USB_FAILED; +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + +#if (BSP_CFG_RTOS == 0) + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + usb_cstd_usb_task(); + err = FSP_SUCCESS; + } + +#else /* (BSP_CFG_RTOS == 0) */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + err = FSP_ERR_USB_FAILED; +#endif /* (BSP_CFG_RTOS == 0) */ + + USB_PREEMPTION_ENABLE(); + + return err; +} + +/**************************************************************************//** + * @brief Set callback memory to USB Driver for USB Peripheral BareMetal. + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @note Call this API after calling R_USB_Open function. + ******************************************************************************/ +fsp_err_t R_USB_CallbackMemorySet (usb_ctrl_t * const p_api_ctrl, usb_callback_args_t * p_callback_memory) +{ + fsp_err_t err = FSP_ERR_USB_FAILED; + +#if USB_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_api_ctrl) + FSP_ASSERT(p_callback_memory) +#endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + + USB_PREEMPTION_DISABLE(); + +#if (BSP_CFG_RTOS == 0) + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + g_usb_apl_callback_memory[p_ctrl->module_number] = p_callback_memory; + err = FSP_SUCCESS; + } + +#else /* (BSP_CFG_RTOS == 0) */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_callback_memory); +#endif /* (BSP_CFG_RTOS == 0) */ + + USB_PREEMPTION_ENABLE(); + + return err; +} + +/**************************************************************************//** + * @brief This API gets the module number. + * + * @retval FSP_SUCCESS Successful completion. + ******************************************************************************/ +fsp_err_t R_USB_ModuleNumberGet (usb_ctrl_t * const p_api_ctrl, uint8_t * module_number) +{ + USB_PREEMPTION_DISABLE(); + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + *module_number = p_ctrl->module_number; + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief This API gets the class type. + * + * @retval FSP_SUCCESS Successful completion. + * @note In Bare-Metal, In the Bare-Metal version, please specify the variable specified by the 1st argument of + * the R_USB_EventGet function to the 1st argument of this API. + * @note In the FreeRTOS, please specify one of the following to the 1st argument of this API. + * @note 1. The 1st argument of the callback function specified in Conguration. + * @note 2. The start address of the area where the structure area of the 1st argument was copied. + ******************************************************************************/ +fsp_err_t R_USB_ClassTypeGet (usb_ctrl_t * const p_api_ctrl, usb_class_t * class_type) +{ + USB_PREEMPTION_DISABLE(); + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + *class_type = (usb_class_t) (p_ctrl->type | USB_VALUE_80H); + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief This API gets the device address. + * + * @retval FSP_SUCCESS Successful completion. + * @note In Bare-Metal, In the Bare-Metal version, please specify the variable specified by the 1st argument of + * the R_USB_EventGet function to the 1st argument of this API. + * @note In the FreeRTOS, please specify one of the following to the 1st argument of this API. + * @note 1. The 1st argument of the callback function specified in Conguration. + * @note 2. The start address of the area where the structure area of the 1st argument was copied. + ******************************************************************************/ +fsp_err_t R_USB_DeviceAddressGet (usb_ctrl_t * const p_api_ctrl, uint8_t * device_address) +{ + USB_PREEMPTION_DISABLE(); + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + *device_address = p_ctrl->device_address; + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief This API gets the pipe number. + * + * @retval FSP_SUCCESS Successful completion. + * @note In Bare-Metal, In the Bare-Metal version, please specify the variable specified by the 1st argument of + * the R_USB_EventGet function to the 1st argument of this API. + * @note In the FreeRTOS, please specify one of the following to the 1st argument of this API. + * @note 1. The 1st argument of the callback function specified in Conguration. + * @note 2. The start address of the area where the structure area of the 1st argument was copied. + ******************************************************************************/ +fsp_err_t R_USB_PipeNumberGet (usb_ctrl_t * const p_api_ctrl, uint8_t * pipe_number) +{ + USB_PREEMPTION_DISABLE(); + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + *pipe_number = p_ctrl->pipe; + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief This API gets the state of the device. + * + * @retval FSP_SUCCESS Successful completion. + * @note In Bare-Metal, In the Bare-Metal version, please specify the variable specified by the 1st argument of + * the R_USB_EventGet function to the 1st argument of this API. + * @note In the FreeRTOS, please specify one of the following to the 1st argument of this API. + * @note 1. The 1st argument of the callback function specified in Conguration. + * @note 2. The start address of the area where the structure area of the 1st argument was copied. + ******************************************************************************/ +fsp_err_t R_USB_DeviceStateGet (usb_ctrl_t * const p_api_ctrl, uint16_t * state) +{ + USB_PREEMPTION_DISABLE(); + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + switch (g_usb_hstd_device_info[p_ctrl->module_number][p_ctrl->device_address][1]) + { + case USB_POWERED: /* Power state */ + { + *state = USB_STATUS_POWERED; + break; + } + + case USB_DEFAULT: /* Default state */ + { + *state = USB_STATUS_DEFAULT; + break; + } + + case USB_ADDRESS: /* Address state */ + { + *state = USB_STATUS_ADDRESS; + break; + } + + case USB_CONFIGURED: /* Configured state */ + { + *state = USB_STATUS_CONFIGURED; + break; + } + + case USB_SUSPENDED: /* Suspend state */ + { + *state = USB_STATUS_SUSPEND; + break; + } + + case USB_DETACHED: /* Disconnect(VBUSon) state */ + { + *state = USB_STATUS_DETACH; + break; + } + + default: /* Error */ + { + *state = USB_NULL; + break; + } + } +#endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + uint16_t status; + + status = hw_usb_read_intsts(p_ctrl->module_number); + switch ((uint16_t) (status & USB_DVSQ)) + { + case USB_DS_POWR: /* Power state */ + { + *state = USB_STATUS_DETACH; + break; + } + + case USB_DS_DFLT: /* Default state */ + { + *state = USB_STATUS_DEFAULT; + break; + } + + case USB_DS_ADDS: /* Address state */ + { + *state = USB_STATUS_ADDRESS; + break; + } + + case USB_DS_CNFG: /* Configured state */ + { + *state = USB_STATUS_CONFIGURED; + break; + } + + case USB_DS_SPD_POWR: /* Power suspend state */ + case USB_DS_SPD_DFLT: /* Default suspend state */ + case USB_DS_SPD_ADDR: /* Address suspend state */ + case USB_DS_SPD_CNFG: /* Configured Suspend state */ + { + *state = USB_STATUS_SUSPEND; + break; + } + + default: /* Error */ + *state = USB_NULL; + } +#endif /* ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + } + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief This API gets the read data size. + * + * @retval FSP_SUCCESS Successful completion. + * @note In Bare-Metal, In the Bare-Metal version, please specify the variable specified by the 1st argument of + * the R_USB_EventGet function to the 1st argument of this API. + * @note In the FreeRTOS, please specify one of the following to the 1st argument of this API. + * @note 1. The 1st argument of the callback function specified in Conguration. + * @note 2. The start address of the area where the structure area of the 1st argument was copied. + ******************************************************************************/ +fsp_err_t R_USB_DataSizeGet (usb_ctrl_t * const p_api_ctrl, uint32_t * data_size) +{ + USB_PREEMPTION_DISABLE(); + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + *data_size = p_ctrl->data_size; + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief This API gets the setup information. + * + * @retval FSP_SUCCESS Successful completion. + * @note In Bare-Metal, In the Bare-Metal version, please specify the variable specified by the 1st argument of + * the R_USB_EventGet function to the 1st argument of this API. + * @note In the FreeRTOS, please specify one of the following to the 1st argument of this API. + * @note 1. The 1st argument of the callback function specified in Conguration. + * @note 2. The start address of the area where the structure area of the 1st argument was copied. + ******************************************************************************/ +fsp_err_t R_USB_SetupGet (usb_ctrl_t * const p_api_ctrl, usb_setup_t * setup) +{ + USB_PREEMPTION_DISABLE(); + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + *setup = p_ctrl->setup; + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief Set callback function to be called when the OTG role swap was completed on Azure RTOS + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + ******************************************************************************/ +fsp_err_t R_USB_OtgCallbackSet (usb_ctrl_t * const p_api_ctrl, usb_otg_callback_t * p_callback) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + FSP_ASSERT(USB_NULL != p_api_ctrl); + FSP_ASSERT(USB_NULL != p_callback); + + USB_PREEMPTION_DISABLE(); + +#if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_OTG_USE) + g_p_otg_callback[p_ctrl->module_number] = p_callback; + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; + #else /* defined(USB_CFG_OTG_USE) */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + #endif /* defined(USB_CFG_OTG_USE) */ +#else /* (BSP_CFG_RTOS == 1) */ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; +#endif /* (BSP_CFG_RTOS == 1) */ +} + +/**************************************************************************//** + * @brief Start the SRP processing for OTG on Azure RTOS + * + * @retval FSP_SUCCESS Successful completion. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_ASSERTION Parameter is NULL error. + * @note Do not support the VBUS Pulsing since OTG 2.0 does not support the VBUS Pulsing.. + ******************************************************************************/ +fsp_err_t R_USB_OtgSRP (usb_ctrl_t * const p_api_ctrl) +{ + usb_instance_ctrl_t * p_ctrl = (usb_instance_ctrl_t *) p_api_ctrl; + + FSP_ASSERT(USB_NULL != p_api_ctrl) + + USB_PREEMPTION_DISABLE(); + +#if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_OTG_USE) + usb_utr_t utr; + uint16_t syssts; + uint16_t intsts; + + if ((USB_MODE_PERI != g_usb_usbmode[p_ctrl->module_number]) || (USB_YES == g_is_A_device[p_ctrl->module_number])) + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + else + { + utr.ip = p_ctrl->module_number; + syssts = hw_usb_read_syssts(&utr); + intsts = hw_usb_read_intsts(utr.ip); + + if ((USB_SE0 == (syssts & USB_LNST)) && (0 == (intsts & USB_VBSTS))) + { + /* Data Pulsing Processing */ + hw_usb_pset_dprpu(utr.ip); // D+ PullUp ON + + usb_cpu_delay_xms((uint16_t) 5); + + hw_usb_pclear_dprpu(utr.ip); // D+ PullUp OFF + } + else + { + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + } + } + + USB_PREEMPTION_ENABLE(); + + return FSP_SUCCESS; + #else /* USB_CFG_OTG_USE */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; + #endif /* USB_CFG_OTG_USE */ +#else /* (BSP_CFG_RTOS == 1) */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + USB_PREEMPTION_ENABLE(); + + return FSP_ERR_USB_FAILED; +#endif /* (BSP_CFG_RTOS == 1) */ +} + +/*******************************************************************************************************************//** + * @} (end addtogroup USB) + **********************************************************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h new file mode 100644 index 0000000000..9fdd934e48 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h @@ -0,0 +1,1184 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef R_USB_BASIC_DEFINE_H + #define R_USB_BASIC_DEFINE_H + + #include "r_usb_basic_cfg.h" + + #define USB_CFG_LITTLE (0U) + #define USB_CFG_BIG (1U) + + #define USB_NOT_SUPPORT (0U) + #define USB_FS_MODULE (1U) + #define USB_HS_MODULE (2U) + + #define USB_CFG_ENDIAN (USB_CFG_LITTLE) + + #if defined(USB_DEBUG_ON) + #include /* @@@MISRA del */ + #include /* @@@MISRA del */ + #endif /* defined(USB_DEBUG_ON) */ + + #ifdef __cplusplus +extern "C" { + #endif + + #define R_USB_HmscTask usb_hmsc_task + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #if (BSP_FEATURE_USB_HAS_USBFS == 1) && (BSP_FEATURE_USB_HAS_USBHS == 1) + + #define USB_HIGH_SPEED_MODULE + #define USB_IP0_MODULE USB_FS_MODULE + #define USB_IP1_MODULE USB_HS_MODULE + + #define USB_NUM_USBIP (2U) + + #define USB_USBMCLK_HZ BSP_CFG_XTAL_HZ + + #endif + + #if (BSP_FEATURE_USB_HAS_USBFS == 1) && (BSP_FEATURE_USB_HAS_USBHS == 0) + #define USB_IP0_MODULE USB_FS_MODULE + #define USB_IP1_MODULE USB_NOT_SUPPORT + + #define USB_NUM_USBIP (1U) + #endif + + #if defined(__CM23_REV) + + #define USB_UNALIGNED_MEMORY_ACCESS_NG_MCU /* Coretex M23 etc */ + + #endif + + #if (BSP_FEATURE_USB_HAS_PIPE04567 == 1) + + #define USB_SUPPORT_MINI_MODULE + + #endif + + #if (BSP_FEATURE_USB_HAS_NOT_HOST == 1) + + #define USB_NOT_SUPPORT_HOST + + #endif + + #if (BSP_FEATURE_USB_HAS_USBLS_PERI == 1) + + #define USB_SUPPORT_PERI_LS /* USB Peripheral Low-speed Support Module */ + + #endif + + #if (BSP_FEATURE_USB_REG_UCKSEL_UCKSELC == 1) + + #define USB_SUPPORT_HOCO_MODULE /* UCKSELC bit */ + + #endif + + #if (BSP_FEATURE_USB_REG_USBMC_VDCEN == 1) + + #define USB_LDO_REGULATOR_MODULE /* VDCEN bit */ + + #endif + + #if (BSP_FEATURE_USB_REG_USBMC_VDDUSBE == 1) + + #define USB_SUPPORT_VDDUSBE /* VDDUSBE bit */ + + #endif + + #if (BSP_FEATURE_USB_REG_PHYSLEW == 1) + + #define USB_SUPPORT_PHYSLEW /* PHYSLEW bit */ + #define USB_PHYSLEW_VALUE BSP_FEATURE_USB_REG_PHYSLEW_VALUE + + #endif + + #if (BSP_FEATURE_USB_HAS_USBHS_BC == 1) + + #define BSP_FEATURE_USBHS_REG_SYSCFG_CNEN /* CNEN bit */ + #define USB_SUPPORT_BC_HS /* Battery Charging in High-speed module */ + + #endif + + #if (BSP_FEATURE_USB_HAS_USBFS_BC == 1) + + #define USB_SUPPORT_BC_FS /* Battery Charging in Full-speed module*/ + + #endif + + #if (BSP_FEATURE_USB_REG_PHYSECTRL_CNEN == 1) + + #define USB_CNEN_PHYSECTRL_USB_IP0 /* CNEN bit */ + + #endif + + #if (BSP_FEATURE_USB_HAS_TYPEC == 1) + + #define USB_SUPPORT_TYPEC /* USB Type-C Support Module */ + + #endif + +/* Version Number of API. */ + #define USB_VERSION_MAJOR (1) + #define USB_VERSION_MINOR (0) + + #define CLSDATASIZE (512U) /* Transfer data size for Standard Request */ + #if (BSP_CFG_RTOS != 0) + +/* The buffer size of interrupt info is increased to avoid overlapping interrupt events. */ + #define USB_INT_BUFSIZE (8U) /* Size of Interrupt info buffer */ + #else /* #if (BSP_CFG_RTOS != 0) */ + #define USB_INT_BUFSIZE (8U) /* Size of Interrupt info buffer */ + #endif /* #if (BSP_CFG_RTOS != 0) */ + #define USB_EVENT_MAX (10) + +/* Scheduler use define */ + #define USB_TBLCLR (0U) /* Table clear */ + #define USB_CNTCLR (0U) /* Counter clear */ + #define USB_FLGCLR (0U) /* Flag clear */ + #define USB_FLGSET (1U) /* Flag set */ + #define USB_IDCLR (0xFFU) /* Priority clear */ + +/* Task ID define */ + #define USB_TID_0 (0U) /* Task ID 0 */ + #define USB_TID_1 (1U) /* Task ID 1 */ + #define USB_TID_2 (2U) /* Task ID 2 */ + #define USB_TID_3 (3U) /* Task ID 3 */ + #define USB_TID_4 (4U) /* Task ID 4 */ + #define USB_TID_5 (5U) /* Task ID 5 */ + #define USB_TID_6 (6U) /* Task ID 6 */ + #define USB_TID_7 (7U) /* Task ID 7 */ + #define USB_TID_8 (8U) /* Task ID 8 */ + #define USB_TID_9 (9U) /* Task ID 9 */ + #define USB_TID_10 (10U) /* Task ID 9 */ + +/* Task priority define */ + #define USB_PRI_0 (0U) /* Priority 0 */ + #define USB_PRI_1 (1U) /* Priority 1 */ + #define USB_PRI_2 (2U) /* Priority 2 */ + #define USB_PRI_3 (3U) /* Priority 3 */ + #define USB_PRI_4 (4U) /* Priority 4 */ + #define USB_PRI_5 (5U) /* Priority 5 */ + #define USB_PRI_6 (6U) /* Priority 6 */ + +/* Host Control Driver Task */ + #define USB_HCD_TSK (USB_TID_1) /* Task ID */ + #define USB_HCD_MBX (USB_HCD_TSK) /* Mailbox ID */ + #define USB_HCD_MPL (USB_HCD_TSK) /* Memory pool ID */ + +/* Host Manager Task */ + #define USB_MGR_TSK (USB_TID_2) /* Task ID */ + #define USB_MGR_MBX (USB_MGR_TSK) /* Mailbox ID */ + #define USB_MGR_MPL (USB_MGR_TSK) /* Memory pool ID */ + +/* Hub Task */ + #define USB_HUB_TSK (USB_TID_3) /* Task ID */ + #define USB_HUB_MBX (USB_HUB_TSK) /* Mailbox ID */ + #define USB_HUB_MPL (USB_HUB_TSK) /* Memory pool ID */ + + #if (BSP_CFG_RTOS != 0) + +/* Class Request for Internal Communication */ + #define USB_CLS_TSK (USB_TID_4) /* Task ID */ + #define USB_CLS_MBX (USB_CLS_TSK) /* Mailbox ID */ + #define USB_CLS_MPL (USB_CLS_TSK) /* Memory pool ID */ + +/* Peripheral Control Driver Task */ + #define USB_PCD_TSK (USB_TID_5) /* Task ID */ + #define USB_PCD_MBX (USB_PCD_TSK) /* Mailbox ID */ + #endif /* #if (BSP_CFG_RTOS != 0) */ + +/* Error discrimination */ + #define USB_DEBUG_HOOK_HWR (0x0100) + #define USB_DEBUG_HOOK_HOST (0x0200) + #define USB_DEBUG_HOOK_PERI (0x0400) + #define USB_DEBUG_HOOK_STD (0x0800) + #define USB_DEBUG_HOOK_CLASS (0x1000) + #define USB_DEBUG_HOOK_APL (0x2000) + +/* Error Code */ + #define USB_DEBUG_HOOK_CODE1 (0x0001) + #define USB_DEBUG_HOOK_CODE2 (0x0002) + #define USB_DEBUG_HOOK_CODE3 (0x0003) + #define USB_DEBUG_HOOK_CODE4 (0x0004) + #define USB_DEBUG_HOOK_CODE5 (0x0005) + #define USB_DEBUG_HOOK_CODE6 (0x0006) + #define USB_DEBUG_HOOK_CODE7 (0x0007) + #define USB_DEBUG_HOOK_CODE8 (0x0008) + #define USB_DEBUG_HOOK_CODE9 (0x0009) + #define USB_DEBUG_HOOK_CODE10 (0x000A) + #define USB_DEBUG_HOOK_CODE11 (0x000B) + #define USB_DEBUG_HOOK_CODE12 (0x000C) + #define USB_DEBUG_HOOK_CODE13 (0x000D) + #define USB_DEBUG_HOOK_CODE14 (0x000E) + #define USB_DEBUG_HOOK_CODE15 (0x000F) + + #ifdef USB_DEBUG_HOOK_USE + #define USB_DEBUG_HOOK(x) (usb_cstd_debug_hook(x)) + #else + #define USB_DEBUG_HOOK(x) + #endif + +/* H/W function type */ + #define USB_BIT0 ((uint16_t) 0x0001) + #define USB_BIT1 ((uint16_t) 0x0002) + #define USB_BIT2 ((uint16_t) 0x0004) + #define USB_BIT3 ((uint16_t) 0x0008) + #define USB_BIT4 ((uint16_t) 0x0010) + #define USB_BIT5 ((uint16_t) 0x0020) + #define USB_BIT6 ((uint16_t) 0x0040) + #define USB_BIT7 ((uint16_t) 0x0080) + #define USB_BIT8 ((uint16_t) 0x0100) + #define USB_BIT9 ((uint16_t) 0x0200) + #define USB_BIT10 ((uint16_t) 0x0400) + #define USB_BIT11 ((uint16_t) 0x0800) + #define USB_BIT12 ((uint16_t) 0x1000) + #define USB_BIT13 ((uint16_t) 0x2000) + #define USB_BIT14 ((uint16_t) 0x4000) + #define USB_BIT15 ((uint16_t) 0x8000) + #define USB_BITSET(x) ((uint16_t) ((uint16_t) 1 << (x))) + +/* nonOS Use */ + #define USB_SEQ_0 ((uint16_t) 0x0000) + #define USB_SEQ_1 ((uint16_t) 0x0001) + #define USB_SEQ_2 ((uint16_t) 0x0002) + #define USB_SEQ_3 ((uint16_t) 0x0003) + #define USB_SEQ_4 ((uint16_t) 0x0004) + #define USB_SEQ_5 ((uint16_t) 0x0005) + #define USB_SEQ_6 ((uint16_t) 0x0006) + #define USB_SEQ_7 ((uint16_t) 0x0007) + #define USB_SEQ_8 ((uint16_t) 0x0008) + #define USB_SEQ_9 ((uint16_t) 0x0009) + #define USB_SEQ_10 ((uint16_t) 0x000a) + +/* USB HUB PIPE No. */ + #define USB_HUB_PIPE (9U) + + #define USB_HUB_P1 ((uint16_t) 0x0001) + #define USB_HUB_P2 ((uint16_t) 0x0002) + #define USB_HUB_P3 ((uint16_t) 0x0003) + #define USB_HUB_P4 ((uint16_t) 0x0004) + + #define USB_HUB (USB_CLASS_REQUEST + 1) + +/* Interrupt message num */ + #define USB_INTMSGMAX ((uint16_t) 15U) + +/* USB Device Connect */ + #define USB_DEV_NO_CONNECT ((uint16_t) 0U) + #define USB_DEV_CONNECTED ((uint16_t) 1U) + + #define USB_OK (0U) + #define USB_ERROR (0xff) + #define USB_ERR_TMOUT (0xfe) + #define USB_ERR_FIFO_ACCESS (0xfd) + #define USB_QOVR (0xd5) /* Submit overlap error */ + #define USB_PAR (0xef) /* parameter error */ + + #define USB_TRUE (1U) + #define USB_FALSE (0U) + + #define USB_YES (1U) + #define USB_NO (0U) + + #define USB_CFG_HIGH (0U) + #define USB_CFG_LOW (1U) + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/* USB module definition */ + #define USB_M0 (R_USB_FS0) + + #ifdef R_USB_HS0 + #define USB_M1 (R_USB_HS0) + #else /* R_USB_HS0 */ + #ifndef R_USB_HS0_BASE + #define R_USB_HS0_BASE (0x40060000) + #endif /* R_USB_HS0_BASE */ + + #define USB_M1 (((R_USB_FS0_Type *) R_USB_HS0_BASE)) + #endif /* R_USB_HS0 */ + +/* FIFO port register default access size */ + #define USB0_CFIFO_MBW (USB_MBW_16) + #define USB0_D0FIFO_MBW (USB_MBW_16) + #define USB0_D1FIFO_MBW (USB_MBW_16) + + #define USB1_CFIFO_MBW (USB_MBW_32) + #define USB1_D0FIFO_MBW (USB_MBW_32) + #define USB1_D1FIFO_MBW (USB_MBW_32) + +/* Start Pipe No */ + #if defined(USB_SUPPORT_MINI_MODULE) + #define USB_MIN_PIPE_NO (4U) + #define USB_MAXPIPE_BULK (5U) + #define USB_BULK_PIPE_START (4U) + #define USB_INT_PIPE_END (7U) + #define USB_MAX_PIPE_NO (7U) /* PIPE4 ... PIPE7 */ + #else /* defined(USB_MINI_MODULE_DMAC) || defined(USB_MINI_MODULE_NO_DMAC) */ + #define USB_MIN_PIPE_NO (1U) + #define USB_MAXPIPE_BULK (5U) + #define USB_BULK_PIPE_START (1U) + #define USB_INT_PIPE_END (9U) + #define USB_MAX_PIPE_NO (9U) /* PIPE0 ... PIPE9 */ + #endif /* defined(USB_MINI_MODULE_DMAC) || defined(USB_MINI_MODULE_NO_DMAC) */ + + #define USB_MAXPIPE_NUM (9U) + #define USB_INT_PIPE_START (6U) + #define USB_BULK_PIPE_END (5U) + + #define USB_ISO_PIPE_START (1U) + #define USB_ISO_PIPE_END (2U) + #define USB_MAXPIPE_ISO (2U) + +/*Max position pipe for USB class */ + #define USB_MAX_PIPE_POS_PERI (18U) + #define USB_MAX_PIPE_POS_HOST (72U) + +/* SPEED mode */ + #define USB_HS_DISABLE ((uint16_t) 0U) + #define USB_HS_ENABLE ((uint16_t) 1U) + + #define USBA_ADDRESS_OFFSET (0x0010) + #define USB_ADDRESS_MASK (0x000f) + #define USB_IP_MASK (0x00f0) + +/* USB Device address define */ + #define USB_DEVICEADDR (1U) /* PORT0 USB Address (1 to 10) */ + +/* HUB Address */ + #define USB_HUBDPADDR ((uint16_t) (USB_DEVICEADDR + 1U)) + + #define USB_PIPE_DIR_IN (0U) + #define USB_PIPE_DIR_OUT (1U) + #define USB_PIPE_DIR_MAX (2U) + + #define USB_CFG_ENABLE (1U) + #define USB_CFG_DISABLE (0U) + + #define USB_CFG_IP0 (0) + #define USB_CFG_IP1 (1) + #define USB_CFG_MULTI (2) + + #define USB_CFG_HOST (1) + #define USB_CFG_PERI (2) + + #define USB_CFG_CDC (0) + #define USB_CFG_VEN (1) + + #define USB_CFG_24MHZ (0) + #define USB_CFG_20MHZ (1) + #define USB_CFG_OTHER (2) + #define USB_CFG_12MHZ (3) + #define USB_CFG_48MHZ (4) + + #define USB_CLK_24MHZ (24000000) + #define USB_CLK_20MHZ (20000000) + #define USB_CLK_12MHZ (12000000) + #define USB_CLK_48MHZ (48000000) + +/* Channel Number */ + #define USB_CFG_CH0 (0U) + #define USB_CFG_CH1 (1U) + #define USB_CFG_CH2 (2U) + #define USB_CFG_CH3 (3U) + #define USB_CFG_CH4 (4U) + #define USB_CFG_CH5 (5U) + #define USB_CFG_CH6 (6U) + #define USB_CFG_CH7 (7U) + +/* Bus Wait */ + #define USB_CFG_BUSWAIT_0 (USB_BWAIT_0) + #define USB_CFG_BUSWAIT_1 (USB_BWAIT_1) + #define USB_CFG_BUSWAIT_2 (USB_BWAIT_2) + #define USB_CFG_BUSWAIT_3 (USB_BWAIT_3) + #define USB_CFG_BUSWAIT_4 (USB_BWAIT_4) + #define USB_CFG_BUSWAIT_5 (USB_BWAIT_5) + #define USB_CFG_BUSWAIT_6 (USB_BWAIT_6) + #define USB_CFG_BUSWAIT_7 (USB_BWAIT_7) + #define USB_CFG_BUSWAIT_8 (USB_BWAIT_8) + #define USB_CFG_BUSWAIT_9 (USB_BWAIT_9) + #define USB_CFG_BUSWAIT_10 (USB_BWAIT_10) + #define USB_CFG_BUSWAIT_11 (USB_BWAIT_11) + #define USB_CFG_BUSWAIT_12 (USB_BWAIT_12) + #define USB_CFG_BUSWAIT_13 (USB_BWAIT_13) + #define USB_CFG_BUSWAIT_14 (USB_BWAIT_14) + #define USB_CFG_BUSWAIT_15 (USB_BWAIT_15) + + #define USB_CFG_USE (0U) + #define USB_CFG_NOUSE (0xFFFFU) + + #define USB_CFG_ON (1U) + #define USB_CFG_OFF (0U) + + #define USB_CFG_FS (1) + #define USB_CFG_HS (2) + +/****************************************************************************** + * USB specification define + ******************************************************************************/ + +/* Standard Device Descriptor Define */ + #define USB_DEV_B_LENGTH (0U) /* Size of descriptor */ + #define USB_DEV_B_DESCRIPTOR_TYPE (1U) /* Descriptor type */ + #define USB_DEV_BCD_USB_L (2U) /* USB Specification Release Number */ + #define USB_DEV_BCD_USB_H (3U) /* USB Specification Release Number */ + #define USB_DEV_B_DEVICE_CLASS (4U) /* Class code */ + #define USB_DEV_B_DEVICE_SUBCLASS (5U) /* Subclass code */ + #define USB_DEV_B_DEVICE_PROTOCOL (6U) /* Protocol code */ + #define USB_DEV_B_MAX_PACKET_SIZE_0 (7U) /* Max packet size for EP0(only 8,16,32,64 are valid) */ + #define USB_DEV_ID_VENDOR_L (8U) /* Vendor ID */ + #define USB_DEV_ID_VENDOR_H (9U) /* Vendor ID */ + #define USB_DEV_ID_PRODUCT_L (10U) /* Product ID */ + #define USB_DEV_ID_PRODUCT_H (11U) /* Product ID */ + #define USB_DEV_BCD_DEVICE_L (12U) /* Device release number */ + #define USB_DEV_BCD_DEVICE_H (13U) /* Device release number */ + #define USB_DEV_I_MANUFACTURER (14U) /* Index of string descriptor describing manufacturer */ + #define USB_DEV_I_PRODUCT (15U) /* Index of string descriptor describing product */ + #define USB_DEV_I_SERIAL_NUMBER (16U) /* Device serial number */ + #define USB_DEV_B_NUM_CONFIGURATION (17U) /* Number of possible configuration */ + +/* Standard Configuration Descriptor Define */ + #define USB_DEV_W_TOTAL_LENGTH_L (2U) /* Total length of data returned for this configuration */ + #define USB_DEV_W_TOTAL_LENGTH_H (3U) /* Total length of data returned for this configuration */ + #define USB_DEV_B_NUM_INTERFACES (4U) /* Number of interfaces supported by this configuration */ + #define USB_DEV_B_CONFIGURATION_VALUE (5U) /* Configuration value */ + #define USB_DEV_I_CONFIGURATION (6U) /* Index of string descriptor describing this configuration */ + #define USB_DEV_BM_ATTRIBUTES (7U) /* Configuration characteristics */ + #define USB_DEV_B_MAX_POWER (8U) /* Max power consumption of the USB device from the bus */ + +/* Endpoint Descriptor Define */ + #define USB_EP_DIRMASK (0x80U) /* Endpoint direction mask [2] */ + #define USB_EP_NUMMASK (0x0FU) /* Endpoint number mask [2] */ + #define USB_EP_USGMASK (0x30U) /* Usage type mask [2] */ + #define USB_EP_SYNCMASK (0x0CU) /* Synchronization type mask [2] */ + #define USB_EP_TRNSMASK (0x03U) /* Transfer type mask [2] */ + #define USB_EP_CNTRL (0x00U) /* Control Transfer */ + + #define USB_EP_B_LENGTH (0U) /* Size of descriptor */ + #define USB_EP_B_DESCRIPTORTYPE (1U) /* Descriptor type */ + #define USB_EP_B_ENDPOINTADDRESS (2U) /* Endpoint No. , Dir */ + #define USB_EP_B_ATTRIBUTES (3U) /* Transfer Type */ + #define USB_EP_B_MAXPACKETSIZE_L (4U) /* Max packet size */ + #define USB_EP_B_MAXPACKETSIZE_H (5U) /* Max packet size */ + #define USB_EP_B_INTERVAL (6U) /* Interval */ + +/* Standard Interface Descriptor Offset Define */ + #define USB_IF_B_INTERFACENUMBER (2U) /* bInterfaceNumber */ + #define USB_IF_B_ALTERNATESETTING (3U) /* bAlternateSetting */ + #define USB_IF_B_NUMENDPOINTS (4U) /* bNumEndpoints */ + #define USB_IF_B_INTERFACECLASS (5U) /* bInterfaceClass */ + #define USB_IF_B_INTERFACESUBCLASS (6U) /* bInterfaceSubClass @@*/ + #define USB_IF_B_INTERFACEPROTOCOL (7U) /* bInterfacePtorocol */ + #define USB_IF_I_INTERFACE (8U) /* iInterface */ + +/* GET_STATUS request information */ +/* Standard Device status */ + #define USB_GS_BUSPOWERD (0x0000U) + #define USB_GS_SELFPOWERD (0x0001U) + #define USB_GS_REMOTEWAKEUP (0x0002U) + +/* Endpoint status */ + #define USB_GS_NOTHALT (0x0000U) + #define USB_GS_HALT (0x0001U) + +/* CLEAR_FEATURE/GET_FEATURE/SET_FEATURE request information */ +/* Standard Feature Selector */ + #define USB_ENDPOINT_HALT (0x0000U) + #define USB_DEV_REMOTE_WAKEUP (0x0001U) + #define USB_TEST_MODE (0x0002U) + +/* GET_DESCRIPTOR/SET_DESCRIPTOR request information */ +/* Standard Descriptor type */ + #define USB_HUB_DESCRIPTOR (0x0000U) + #define USB_DEV_DESCRIPTOR (0x0100U) + #define USB_CONF_DESCRIPTOR (0x0200U) + #define USB_STRING_DESCRIPTOR (0x0300U) + #define USB_INTERFACE_DESCRIPTOR (0x0400U) + #define USB_ENDPOINT_DESCRIPTOR (0x0500U) + #define USB_DEV_QUALIFIER_DESCRIPTOR (0x0600U) + #define USB_OTHER_SPEED_CONF_DESCRIPTOR (0x0700U) + #define USB_INTERFACE_POWER_DESCRIPTOR (0x0800U) + + #define USB_OTG_SELECTOR (0xF000U) + #define B_HNP_ENABLE (0x3U) + #define A_HNP_SUPPORT (0x4U) + +/* HUB CLASS REQUEST */ + #define USB_HUB_CLEAR_TT_BUFFER (0x0800U) + #define USB_HUB_RESET_TT (0x0900U) + #define USB_HUB_GET_TT_STATE (0x0A00U) + #define USB_HUB_STOP_TT (0x0B00U) + +/* HUB CLASS FEATURE SELECTER */ + #define USB_HUB_C_HUB_LOCAL_POWER (0x0000U) + #define USB_HUB_C_HUB_OVER_CURRENT (0x0001U) + #define USB_HUB_PORT_CONNECTION (0x0000U) + #define USB_HUB_PORT_ENABLE (0x0001U) + #define USB_HUB_PORT_SUSPEND (0x0002U) + #define USB_HUB_PORT_OVER_CURRENT (0x0003U) + #define USB_HUB_PORT_RESET (0x0004U) + #define USB_HUB_PORT_POWER (0x0008U) + #define USB_HUB_PORT_LOW_SPEED (0x0009U) + #define USB_HUB_PORT_HIGH_SPEED (0x000AU) + #define USB_HUB_C_PORT_CONNECTION (0x0010U) + #define USB_HUB_C_PORT_ENABLE (0x0011U) + #define USB_HUB_C_PORT_SUSPEND (0x0012U) + #define USB_HUB_C_PORT_OVER_CURRENT (0x0013U) + #define USB_HUB_C_PORT_RESET (0x0014U) + #define USB_HUB_PORT_TEST (0x0015U) + #define USB_HUB_PORT_INDICATOR (0x0016U) + +/* HUB PORT STAUS */ + #define USB_HUB_STS_PORT_CONNECT (0x0001U) + #define USB_HUB_STS_PORT_ENABLE (0x0002U) + #define USB_HUB_STS_PORT_SUSPEND (0x0004U) + #define USB_HUB_STS_PORT_OVRCURRNET (0x0008U) + #define USB_HUB_STS_PORT_RESET (0x0010U) + #define USB_HUB_STS_PORT_POWER (0x0100U) + #define USB_HUB_STS_PORT_LOWSPEED (0x0200U) + #define USB_HUB_STS_PORT_FULLSPEED (0x0000U) + #define USB_HUB_STS_PORT_HIGHSPEED (0x0400U) + #define USB_HUB_STS_PORT_TEST (0x0800U) + #define USB_HUB_STS_PORT_INDICATOR (0x1000U) + +/* HUB PORT CHANGE */ + #define USB_HUB_CHG_PORT_CONNECT (0x0001U) + #define USB_HUB_CHG_PORT_ENABLE (0x0002U) + #define USB_HUB_CHG_PORT_SUSPEND (0x0004U) + #define USB_HUB_CHG_PORT_OVRCURRNET (0x0008U) + #define USB_HUB_CHG_PORT_RESET (0x0010U) + +/* Device connect information */ + #define USB_ATTACH (0x0040U) + #define USB_ATTACHL (0x0041U) + #define USB_ATTACHF (0x0042U) + #define USB_DETACH (0x0043U) + +/* Reset Handshake result */ + #define USB_NOCONNECT (0x0000U) /* Speed undecidedness */ + #define USB_HSCONNECT (0x00C0U) /* Hi-Speed connect */ + #define USB_FSCONNECT (0x0080U) /* Full-Speed connect */ + #define USB_LSCONNECT (0x0040U) /* Low-Speed connect */ + +/* Pipe define */ + #define USB_USEPIPE (0x00FEU) + #define USB_PERIPIPE (0x00FDU) + #define USB_CLRPIPE (0x00FCU) /* Clear Pipe registration */ + +/* Pipe configuration table define */ + #define USB_EPL (6U) /* Pipe configuration table length */ + #define USB_TYPFIELD (0xC000U) /* Transfer type */ + #define USB_PERIODIC (0x8000U) /* Periodic pipe */ + #define USB_TYPFIELD_ISO (0xC000U) /* Isochronous */ + #define USB_TYPFIELD_INT (0x8000U) /* Interrupt */ + #define USB_TYPFIELD_BULK (0x4000U) /* Bulk */ + #define USB_TYPFIELD_NOUSE (0x2000U) /* Not Used Pipe */ + #define USB_NOUSE (0x0000U) /* Not configuration */ + #define USB_BFREFIELD (0x0400U) /* Buffer ready interrupt mode select */ + #define USB_BFREON (0x0400U) + #define USB_BFREOFF (0x0000U) + #define USB_DBLBFIELD (0x0200U) /* Double buffer mode select */ + #define USB_CFG_DBLBON (0x0200U) + #define USB_CFG_DBLBOFF (0x0000U) + #define USB_CNTMDFIELD (0x0100U) /* Continuous transfer mode select */ + #define USB_CFG_CNTMDON (0x0100U) + #define USB_CFG_CNTMDOFF (0x0000U) + #define USB_SHTNAKFIELD (0x0080U) /* Transfer end NAK */ + #define USB_DIRFIELD (0x0010U) /* Transfer direction select */ + #define USB_DIR_H_OUT (0x0010U) /* HOST OUT */ + #define USB_DIR_P_IN (0x0010U) /* PERI IN */ + #define USB_DIR_H_IN (0x0000U) /* HOST IN */ + #define USB_DIR_P_OUT (0x0000U) /* PERI OUT */ + #define USB_BUF2FIFO (0x0010U) /* Buffer --> FIFO */ + #define USB_FIFO2BUF (0x0000U) /* FIFO --> buffer */ + #define USB_EPNUMFIELD (0x000FU) /* Endpoint number select */ + #define USB_MAX_EP_NO (15U) /* EP0 EP1 ... EP15 */ + #define USB_ENDPOINT_DIRECTION (0x0080U) /* EndPoint Address direction */ + + #define USB_BUF_SIZE(x) ((uint16_t) (((x) / 64U) - 1U) << 10U) + #define USB_BUF_NUMB(x) (x) + + #define USB_IFISFIELD (0x1000U) /* Isochronous in-buf flash mode */ + #define USB_IFISON (0x1000U) + #define USB_IFISOFF (0x0000U) + #define USB_IITVFIELD (0x0007U) /* Isochronous interval */ + #define USB_IITV_TIME(x) (x) + +/* FIFO port & access define */ + #define USB_CUSE (0U) /* CFIFO trans */ + #define USB_D0USE (1U) /* D0FIFO trans */ + #define USB_D1USE (2U) /* D1FIFO trans */ + #define USB_FIFO_ACCESS_NUM_MAX (3U) /* MAX number for FIFO port define */ + +/****************************************************************************** + * Another define + ******************************************************************************/ + +/* FIFO read / write result */ + #define USB_FIFOERROR (USB_ERROR) /* FIFO not ready */ + #define USB_WRITEEND (0x0000U) /* End of write (but packet may not be outputting) */ + #define USB_WRITESHRT (0x0001U) /* End of write (send short packet) */ + #define USB_WRITING (0x0002U) /* Write continues */ + #define USB_READEND (0x0000U) /* End of read */ + #define USB_READSHRT (0x0001U) /* Insufficient (receive short packet) */ + #define USB_READING (0x0002U) /* Read continues */ + #define USB_READOVER (0x0003U) /* Buffer size over */ + +/* Pipe define table end code */ + #define USB_PDTBLEND (0xFFFFU) /* End of table */ + +/* Transfer status Type */ + #define USB_CTRL_END (0U) + #define USB_DATA_NONE (1U) + #define USB_DATA_WAIT (2U) + #define USB_DATA_OK (3U) + #define USB_DATA_SHT (4U) + #define USB_DATA_OVR (5U) + #define USB_DATA_STALL (6U) + #define USB_DATA_ERR (7U) + #define USB_DATA_STOP (8U) + #define USB_DATA_TMO (9U) + #define USB_CTRL_READING (17U) + #define USB_CTRL_WRITING (18U) + #define USB_DATA_READING (19U) + #define USB_DATA_WRITING (20U) + #define USB_DATA_FIFO_ERR (21U) + +/* Utr member (segment) */ + #define USB_TRAN_CONT (0x00U) + #define USB_TRAN_END (0x80U) + +/* Callback argument */ + #define USB_NO_ARG (0U) + +/* USB interrupt type (common)*/ + #define USB_INT_UNKNOWN (0x0000U) + #define USB_INT_BRDY (0x0001U) + #define USB_INT_BEMP (0x0002U) + #define USB_INT_NRDY (0x0003U) + #define USB_INT_DXFIFO (0x0004U) /* BSP_CFG_RTOS == 2 */ + +/* USB interrupt type (PERI)*/ + #define USB_INT_VBINT (0x0011U) + #define USB_INT_RESM (0x0012U) + #define USB_INT_SOFR (0x0013U) + #define USB_INT_DVST (0x0014U) + #define USB_INT_CTRT (0x0015U) + #define USB_INT_ATTACH (0x0016U) + #define USB_INT_DETACH (0x0017U) + +/* USB interrupt type (HOST)*/ + #define USB_INT_OVRCR0 (0x0041U) + #define USB_INT_BCHG0 (0x0042U) + #define USB_INT_DTCH0 (0x0043U) + #define USB_INT_ATTCH0 (0x0044U) + #define USB_INT_EOFERR0 (0x0045U) + #define USB_INT_PDDETINT0 (0x0046U) + #define USB_INT_OVRCR1 (0x0051U) + #define USB_INT_BCHG1 (0x0052U) + #define USB_INT_ATTCH1 (0x0053U) + #define USB_INT_DTCH1 (0x0054U) + #define USB_INT_EOFERR1 (0x0055U) + #define USB_INT_SACK (0x0061U) + #define USB_INT_SIGN (0x0062U) + +/* USB interrupt type (OTG)*/ + #define USB_INT_OTG_HOST_INIT (0x0071U) + + #define USB_UACTON (1U) + #define USB_UACTOFF (0U) + #define USB_VBON (1U) + #define USB_VBOFF (0U) + + #define USB_NOVENDOR (0xFFFFU) /* Vendor ID no check */ + #define USB_NOPRODUCT (0xFFFFU) /* Product ID no check */ + + #define USB_INTFCLSHET (0xAAU) /* Host electrical test class */ + +/* Root port */ + #define USB_NOPORT (0xFFFFU) /* Not connect */ + +/* Condition compilation by the difference of IP */ + #define USB_MAXDEVADDR (5U) + + #define USB_DEVICE_0 (0x0000U) /* Device address 0 */ + #define USB_DEVICE_1 (0x1000U) /* Device address 1 */ + #define USB_DEVICE_2 (0x2000U) /* Device address 2 */ + #define USB_DEVICE_3 (0x3000U) /* Device address 3 */ + #define USB_DEVICE_4 (0x4000U) /* Device address 4 */ + #define USB_DEVICE_5 (0x5000U) /* Device address 5 */ + #define USB_DEVICE_6 (0x6000U) /* Device address 6 */ + #define USB_DEVICE_7 (0x7000U) /* Device address 7 */ + #define USB_DEVICE_8 (0x8000U) /* Device address 8 */ + #define USB_DEVICE_9 (0x9000U) /* Device address 9 */ + #define USB_DEVICE_A (0xA000U) /* Device address A */ + #define USB_NODEVICE (0xF000U) /* No device */ + #define USB_DEVADDRBIT (12U) + +/* DCP Max packet size */ + #define USB_MAXPFIELD (0x007FU) /* Max packet size of DCP */ + +/* USB task preemption control */ + #if (BSP_CFG_RTOS == 2) + #define USB_PREEMPTION_ENABLE() xTaskResumeAll() + #define USB_PREEMPTION_DISABLE() vTaskSuspendAll() + #else + #define USB_PREEMPTION_ENABLE() + #define USB_PREEMPTION_DISABLE() + #endif + +/****************************************************************************** + * Another define + ******************************************************************************/ + +/* ControlPipe Max Packet size */ + #define USB_DEFPACKET (0x0040U) /* Default DCP Max packet size */ + +/* Device state define */ + #define USB_NONDEVICE (0U) + #define USB_NOTTPL (1U) + #define USB_DEVICEENUMERATION (3U) + #define USB_COMPLETEPIPESET (10U) + +/* Control Transfer Stage */ + #define USB_IDLEST (0U) /* Idle */ + #define USB_SETUPNDC (1U) /* Setup Stage No Data Control */ + #define USB_SETUPWR (2U) /* Setup Stage Control Write */ + #define USB_SETUPRD (3U) /* Setup Stage Control Read */ + #define USB_DATAWR (4U) /* Data Stage Control Write */ + #define USB_DATARD (5U) /* Data Stage Control Read */ + #define USB_STATUSRD (6U) /* Status stage */ + #define USB_STATUSWR (7U) /* Status stage */ + #define USB_SETUPWRCNT (17U) /* Setup Stage Control Write */ + #define USB_SETUPRDCNT (18U) /* Setup Stage Control Read */ + #define USB_DATAWRCNT (19U) /* Data Stage Control Write */ + #define USB_DATARDCNT (20U) /* Data Stage Control Read */ + +/****************************************************************************** + * HUB define + ******************************************************************************/ + + #if ((USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) || (USB_CFG_HHID_MULTI == USB_CFG_ENABLE) || \ + (USB_CFG_HMSC_MULTI == USB_CFG_ENABLE)) + #define USB_CFG_HUB (USB_CFG_ENABLE) + #endif + +/* HUB spec */ + #define USB_FSHUB (1U) + #define USB_HSHUBS (2U) + #define USB_HSHUBM (3U) + +/* Interface number */ + #define USB_HUB_INTNUMFS (1U) + #define USB_HUB_INTNUMHSS (1U) + #define USB_HUB_INTNUMHSM (1U) + +/* HUB Target peripheral list */ + #define USB_CFG_HUB_TPLCNT (1) + #define USB_CFG_HUB_TPL USB_NOVENDOR, USB_NOPRODUCT + +/* USB Manager mode */ + #define USB_PORTOFF (0U) /* Disconnect(VBUSoff) */ + #define USB_DETACHED (10U) /* Disconnect(VBUSon) */ + #define USB_ATTACHED (20U) /* Disconnect(HUBdiconfigured) */ + #define USB_POWERED (30U) /* Start reset handshake */ + #define USB_DEFAULT (40U) /* Set device address */ + #define USB_ADDRESS (50U) /* Enumeration start */ + #define USB_ENUMERATION (60U) /* Wait device enumeration */ + #define USB_CONFIGURED (70U) /* Detach detected */ + #define USB_SUSPENDED (80U) /* Device suspended */ + #define USB_DETACH_PROCESS (101U) /* Wait device detach */ + #define USB_SUSPENDED_PROCESS (102U) /* Wait device suspend */ + #define USB_RESUME_PROCESS (103U) /* Wait device resume */ + +/* HCD common task message command */ + #define USB_MSG_HCD_ATTACH (0x0101U) + #define USB_MSG_HCD_DETACH (0x0102U) + #define USB_MSG_HCD_USBRESET (0x0103U) + #define USB_MSG_HCD_SUSPEND (0x0104U) + #define USB_MSG_HCD_RESUME (0x0105U) + #define USB_MSG_HCD_REMOTE (0x0106U) + #define USB_MSG_HCD_VBON (0x0107U) + #define USB_MSG_HCD_VBOFF (0x0108U) + #define USB_MSG_HCD_CLR_STALL (0x0109U) + #define USB_MSG_HCD_DETACH_MGR (0x010AU) + #define USB_MSG_HCD_ATTACH_MGR (0x010BU) + + #define USB_MSG_HCD_CLR_STALL_RESULT (0x010CU) + #define USB_MSG_HCD_CLR_STALLBIT (0x010DU) + #define USB_MSG_HCD_SQTGLBIT (0x010FU) + +/* HCD task message command */ + #define USB_MSG_HCD_SETDEVICEINFO (0x0111U) + #define USB_MSG_HCD_SUBMITUTR (0x0112U) + #define USB_MSG_HCD_TRANSEND1 (0x0113U) + #define USB_MSG_HCD_TRANSEND2 (0x0114U) + #define USB_MSG_HCD_CLRSEQBIT (0x0115U) + #define USB_MSG_HCD_SETSEQBIT (0x0116U) + #define USB_MSG_HCD_INT (0x0117U) + #define USB_MSG_HCD_DMAINT (0x0119U) + + #define USB_MSG_HCD_OTG_SUSPEND (0x0120U) + + #define USB_MSG_HCD_D0FIFO_INT (0x0141U) + #define USB_MSG_HCD_D1FIFO_INT (0x0142U) + #define USB_MSG_HCD_RESM_INT (0x0143U) + #define USB_MSG_PCD_D0FIFO_INT (0x0144U) + #define USB_MSG_PCD_D1FIFO_INT (0x0145U) + #define USB_MSG_PCD_RESM_INT (0x0146U) + +/* USB Manager task message command */ + #define USB_MSG_MGR_AORDETACH (0x0121U) + #define USB_MSG_MGR_OVERCURRENT (0x0122U) + #define USB_MSG_MGR_STATUSRESULT (0x0123U) + #define USB_MSG_MGR_SUBMITRESULT (0x0124U) + #define USB_MSG_MGR_TRANSENDRESULT (0x0125U) + + #define USB_MSG_MGR_SETCONFIGURATION (0x0300) + #define USB_MSG_MGR_SETCONFIGURATION_RESULT (0x0301) + + #define USB_MSG_MGR_GETDESCRIPTOR (0x0400) + #define USB_MSG_MGR_GETDESCRIPTOR_RESULT (0x0401) + +/* USB HUB task message command */ + #define USB_MSG_HUB_HUB2HUBSTART (0x0131U) + #define USB_MSG_HUB_START (0x0132U) + #define USB_MSG_HUB_STOP (0x0133U) + #define USB_MSG_HUB_SUBMITRESULT (0x0134U) + #define USB_MSG_HUB_EVENT (0x0135U) /* nonOS */ + #define USB_MSG_HUB_ATTACH (0x0136U) /* nonOS */ + #define USB_MSG_HUB_RESET (0x0137U) /* nonOS */ + +/* CLS task message command */ + #define USB_MSG_CLS_CHECKREQUEST (0x0201U) /* nonOS */ + #define USB_MSG_CLS_INIT (0x0202U) /* nonOS */ + #define USB_MSG_CLS_TASK (0x0203U) /* nonOS */ + #define USB_MSG_CLS_WAIT (0x0204U) /* nonOS */ + #define USB_MSG_CLS_PROCESSRESULT (0x0205U) /* nonOS */ + +/* HET task message command */ + #define USB_MSG_HET_UACTOFF (0x0171U) + #define USB_MSG_HET_UACTON (0x0172U) + #define USB_MSG_HET_VBUSOFF (0x0173U) + #define USB_MSG_HET_VBUSON (0x0174U) + #define USB_MSG_HET_RESET (0x0175U) + #define USB_MSG_HET_SUSPEND (0x0176U) + #define USB_MSG_HET_RESUME (0x0177U) + #define USB_MSG_HET_ENUMERATION (0x0178U) + #define USB_MSG_HET_TESTNONE (0x0181U) + #define USB_MSG_HET_TESTPACKET (0x0182U) + #define USB_MSG_HET_TESTJ (0x0183U) + #define USB_MSG_HET_TESTK (0x0184U) + #define USB_MSG_HET_TESTSE0 (0x0185U) + #define USB_MSG_HET_TESTSIGSTOP (0x0186U) + #define USB_MSG_HET_SINGLESETUP (0x0187U) + #define USB_MSG_HET_SINGLEDATA (0x0188U) + +/* Descriptor index */ + #define USB_DEV_MAX_PKT_SIZE (7U) /* Index of bMAXPacketSize */ + #define USB_DEV_NUM_CONFIG (17U) /* Index of bNumConfigurations */ + #define USB_ALT_NO (255U) + #define USB_SOFT_CHANGE (0U) + +/* USB Peripheral task message command */ + #define USB_MSG_PCD_INT (0x0151U) + #define USB_MSG_PCD_SUBMITUTR (0x0152U) + #define USB_MSG_PCD_TRANSEND1 (0x0153U) + #define USB_MSG_PCD_TRANSEND2 (0x0154U) + #define USB_MSG_PCD_REMOTEWAKEUP (0x0155U) + #define USB_MSG_PCD_DETACH (0x0161U) + #define USB_MSG_PCD_ATTACH (0x0162U) + #define USB_MSG_PCD_CLRSEQBIT (0x0163U) + #define USB_MSG_PCD_SETSTALL (0x0164U) + #define USB_MSG_PCD_PCUTINT (0x0156U) + + #define USB_MSG_PCD_DP_ENABLE (0x0157U) + #define USB_MSG_PCD_DP_DISABLE (0x0158U) + #define USB_MSG_PCD_DM_ENABLE (0x0159U) + #define USB_MSG_PCD_DM_DISABLE (0x015AU) + + #define USB_MSG_PCD_DMAINT (0x015bU) + + #define USB_DO_REMOTEWAKEUP (USB_MSG_PCD_REMOTEWAKEUP) + #define USB_DP_ENABLE (USB_MSG_PCD_DP_ENABLE) + #define USB_DP_DISABLE (USB_MSG_PCD_DP_DISABLE) + #define USB_DM_ENABLE (USB_MSG_PCD_DM_ENABLE) + #define USB_DM_DISABLE (USB_MSG_PCD_DM_DISABLE) + + #define USB_DO_STALL (USB_MSG_PCD_SETSTALL) + + #define USB_DO_RESET_AND_ENUMERATION (0x0202U) /* USB_MSG_HCD_ATTACH */ + #define USB_PORT_ENABLE (0x0203U) /* USB_MSG_HCD_VBON */ + #define USB_PORT_DISABLE (0x0204U) /* USB_MSG_HCD_VBOFF */ + #define USB_DO_GLOBAL_SUSPEND (0x0205U) /* USB_MSG_HCD_SUSPEND */ + #define USB_DO_SELECTIVE_SUSPEND (0x0206U) /* USB_MSG_HCD_SUSPEND */ + #define USB_DO_GLOBAL_RESUME (0x0207U) /* USB_MSG_HCD_RESUME */ + #define USB_DO_SELECTIVE_RESUME (0x0208U) /* USB_MSG_HCD_RESUME */ + #define USB_DO_CLR_STALL (0x0209U) /* USB_MSG_HCD_CLR_STALL */ + #define USB_DO_SET_SQTGL (0x020AU) /* USB_MSG_HCD_SQTGLBIT */ + #define USB_DO_CLR_SQTGL (0x020BU) /* USB_MSG_HCD_CLRSEQBIT */ + +/* BC State Define */ + #define USB_BC_STATE_INIT (0x00U) + #define USB_BC_STATE_DET (0x01U) + #define USB_BC_STATE_CDP (0x02U) + #define USB_BC_STATE_SDP (0x03U) + #define USB_BC_STATE_DCP (0x04U) + #define USB_BC_STATE_MAX (0x05U) + +/* BC State Change Event Define */ + #define USB_BC_EVENT_VB (0x00U) + #define USB_BC_EVENT_AT (0x01U) + #define USB_BC_EVENT_DT (0x02U) + #define USB_BC_EVENT_MAX (0x03U) + +/* DCP Mode Setting Define */ + #define USB_BC_DCPMODE (0x01U) + +/*#define USB_BC_DCPMODE (0x00U)*/ + + #define USB_NOT_BC (0xFFFEU) + + #define USB_ODD (0x1U) + +/************************************************************************* + * old basic_cfg.h #define + *************************************************************************/ + #define USB_SND_MSG(ID, MESS) (usb_cstd_snd_msg((uint8_t) (ID), (usb_msg_t *) (MESS))) + #define USB_ISND_MSG(ID, MESS) (usb_cstd_isnd_msg((uint8_t) (ID), (usb_msg_t *) (MESS))) + #define USB_WAI_MSG(ID, MESS, TM) (usb_cstd_wai_msg((uint8_t) (ID), (usb_msg_t *) (MESS), (usb_tm_t) (TM))) + #define USB_RCV_MSG(ID, MESS) (usb_cstd_rec_msg((uint8_t) (ID), (usb_msg_t **) (MESS), (usb_tm_t) (0U))) + #define USB_TRCV_MSG(ID, MESS, TM) (usb_cstd_rec_msg((uint8_t) (ID), (usb_msg_t **) (MESS), (usb_tm_t) (TM))) + + #define USB_PGET_BLK(ID, BLK, IP) (usb_cstd_pget_blk((uint8_t) (ID), (usb_utr_t **) (BLK), (uint8_t) (IP))) + #define USB_REL_BLK(ID, BLK) (usb_cstd_rel_blk((uint8_t) (ID), (usb_utr_t *) (BLK))) + +/* Descriptor size */ + #define USB_DEVICESIZE (20U) /* Device Descriptor size */ + #if defined(USB_CFG_HUVC_USE) || defined(USB_CFG_HAUD_USE) + #define USB_CONFIGSIZE (3 * 1024) /* Configuration Descriptor size */ + #else + #define USB_CONFIGSIZE (1 * 1024) /* Configuration Descriptor size */ + #endif /* defined(USB_CFG_HUVC_USE) || defined(USB_CFG_HAUD_USE) */ + +/* Number of software retries when a no-response condition occurs during a transfer */ + #define USB_PIPEERROR (1U) + +/* Debug Print Buffer Size */ + #define USB_PRINT_BUF_SIZE (64U) + +/** [Output debugging message in a console of IDE.] + * not defined(USB_DEBUG_ON) : No output the debugging message + * defined(USB_DEBUG_ON) : Output the debugging message + */ + #if defined(USB_DEBUG_ON) + + #if USB_DEBUG_ON == 1 + #define USB_PRINTF0(FORM) (printf(FORM)) + #define USB_PRINTF1(FORM, x1) (printf((FORM), (x1))) + #define USB_PRINTF2(FORM, x1, x2) (printf((FORM), (x1), (x2))) + #define USB_PRINTF3(FORM, x1, x2, x3) (printf((FORM), (x1), (x2), (x3))) + #define USB_PRINTF4(FORM, x1, x2, x3, x4) (printf((FORM), (x1), (x2), (x3), (x4))) + #define USB_PRINTF5(FORM, x1, x2, x3, x4, x5) (printf((FORM), (x1), (x2), (x3), (x4), (x5))) + #define USB_PRINTF6(FORM, x1, x2, x3, x4, x5, x6) (printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6))) + #define USB_PRINTF7(FORM, x1, x2, x3, x4, x5, x6, \ + x7) (printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6), \ + (x7))) + #define USB_PRINTF8(FORM, \ + x1, \ + x2, \ + x3, \ + x4, \ + x5, \ + x6, \ + x7, \ + x8) (printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6), \ + (x7), (x8))) + #elif USB_DEBUG_ON == 2 + #define USB_PRINTF0(FORM) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #define USB_PRINTF1(FORM, x1) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #define USB_PRINTF2(FORM, x1, x2) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #define USB_PRINTF3(FORM, x1, x2, x3) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #define USB_PRINTF4(FORM, x1, x2, x3, x4) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #define USB_PRINTF5(FORM, x1, x2, x3, x4, x5) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4), \ + (x5)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #define USB_PRINTF6(FORM, x1, x2, x3, x4, x5, x6) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4), \ + (x5), \ + (x6)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #define USB_PRINTF7(FORM, x1, x2, x3, x4, x5, x6, x7) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4), \ + (x5), \ + (x6), \ + (x7)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #define USB_PRINTF8(FORM, x1, x2, x3, x4, x5, x6, x7, x8) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4), \ + (x5), \ + (x6), \ + (x7), \ + (x8)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer) + #elif USB_DEBUG_ON == 3 + #define USB_PRINTF0(FORM) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM)) + #define USB_PRINTF1(FORM, x1) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM), (x1)) + #define USB_PRINTF2(FORM, x1, x2) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM), (x1), (x2)) + #define USB_PRINTF3(FORM, x1, x2, x3) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM), (x1), (x2), (x3)) + #define USB_PRINTF4(FORM, x1, x2, x3, x4) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM), (x1), (x2), (x3), (x4)) + #define USB_PRINTF5(FORM, x1, x2, x3, x4, x5) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4), \ + (x5)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM), (x1), (x2), (x3), (x4), (x5)) + #define USB_PRINTF6(FORM, x1, x2, x3, x4, x5, x6) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4), \ + (x5), \ + (x6)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6)) + #define USB_PRINTF7(FORM, x1, x2, x3, x4, x5, x6, x7) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4), \ + (x5), \ + (x6), \ + (x7)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6), (x7)) + #define USB_PRINTF8(FORM, x1, x2, x3, x4, x5, x6, x7, x8) snprintf((char *) &g_usb_print_buffer[0], \ + USB_PRINT_BUF_SIZE, \ + (FORM), \ + (x1), \ + (x2), \ + (x3), \ + (x4), \ + (x5), \ + (x6), \ + (x7), \ + (x8)); \ + g_usb_qe_error_string_length = (uint8_t) strlen((const char *) g_usb_print_buffer); \ + printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6), (x7), (x8)) + + #endif + + #else /* defined(USB_DEBUG_ON) */ + #define USB_PRINTF0(FORM) + #define USB_PRINTF1(FORM, x1) + #define USB_PRINTF2(FORM, x1, x2) + #define USB_PRINTF3(FORM, x1, x2, x3) + #define USB_PRINTF4(FORM, x1, x2, x3, x4) + #define USB_PRINTF5(FORM, x1, x2, x3, x4, x5) + #define USB_PRINTF6(FORM, x1, x2, x3, x4, x5, x6) + #define USB_PRINTF7(FORM, x1, x2, x3, x4, x5, x6, x7) + #define USB_PRINTF8(FORM, x1, x2, x3, x4, x5, x6, x7, x8) + #endif /* defined(USB_DEBUG_ON) */ + + #ifdef __cplusplus +} + #endif + +#endif /* R_USB_BASIC_DEFINE_H */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h new file mode 100644 index 0000000000..abc0c8c5d7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h @@ -0,0 +1,131 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#include "r_usb_basic.h" +#include "r_usb_typedef.h" + +#if (BSP_CFG_RTOS != 0) + + #if (BSP_CFG_RTOS == 2) + #include "FreeRTOS.h" + #include "task.h" + #include "queue.h" + #elif (BSP_CFG_RTOS == 1) + #include "tx_api.h" + #endif + + #ifndef R_USB_CSTD_RTOS_H + #define R_USB_CSTD_RTOS_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + + #if (BSP_CFG_RTOS == 2) +typedef TaskHandle_t rtos_task_id_t; +typedef QueueHandle_t rtos_mbx_id_t; +typedef QueueHandle_t rtos_mem_id_t; +typedef SemaphoreHandle_t rtos_sem_id_t; +typedef TickType_t rtos_time_t; + +/** USB task's priority **/ + #define HCD_TSK_PRI (configMAX_PRIORITIES - 1) + #define HUB_TSK_PRI (configMAX_PRIORITIES - 3) + #define MGR_TSK_PRI (configMAX_PRIORITIES - 2) + #define PCD_TSK_PRI (configMAX_PRIORITIES - 1) + #define PMSC_TSK_PRI (configMAX_PRIORITIES - 2) + + #elif (BSP_CFG_RTOS == 1) +typedef TX_THREAD rtos_task_id_t; +typedef TX_QUEUE rtos_mbx_id_t; +typedef TX_BYTE_POOL rtos_mem_id_t; +typedef TX_SEMAPHORE rtos_sem_id_t; +typedef uint32_t rtos_time_t; + + #define USB_TASK_PRI_BASE (10) + #define HCD_TSK_PRI (USB_TASK_PRI_BASE) + #define HUB_TSK_PRI (HCD_TSK_PRI + 2) + #define MGR_TSK_PRI (HCD_TSK_PRI + 1) + #define PCD_TSK_PRI (USB_TASK_PRI_BASE) + #define PMSC_TSK_PRI (PCD_TSK_PRI + 1) + + #endif /* (BSP_CFG_RTOS == 2) */ + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/** Size of a queue **/ + #define QUEUE_SIZE (10) + +/** USB task stack size in words **/ + #if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_HMSC_USE) + #define HCD_STACK_SIZE (2048) + #define MGR_STACK_SIZE (2048) + #else + +// #define HCD_STACK_SIZE (1536) +// #define MGR_STACK_SIZE (1536) + #define HCD_STACK_SIZE (1536 + 1024) + #define MGR_STACK_SIZE (1536 + 1024) + #endif + #define HUB_STACK_SIZE (512) + #define PCD_STACK_SIZE (1024) + #define PMSC_STACK_SIZE (512) + #define HCDC_STACK_SIZE (512) + #define HHID_STACK_SIZE (512) + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + #define HCD_STACK_SIZE (512) + #define HUB_STACK_SIZE (512) + #define MGR_STACK_SIZE (512) + #define PCD_STACK_SIZE (512) + #define PMSC_STACK_SIZE (512) + #define HCDC_STACK_SIZE (512) + #define HHID_STACK_SIZE (512) + #endif /* #if (BSP_CFG_RTOS == 1) */ +/* Number of Memory Block */ + #define NUM_OF_BLOCK (8) + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ +typedef enum e_usb_rtos_err +{ + UsbRtos_Success = 0, // Successful + UsbRtos_Err_Init_Mbx, // Failure of Mailbox Creation + UsbRtos_Err_Init_Mpl, // Failure of Memory Pool Creation + UsbRtos_Err_Init_Tsk, // Failure of Task Creation + UsbRtos_Err_Init_Sem, // Failure of Semaphore Creation + UsbRtos_Err_Delete_Mbx, // Failure of Mailbox Delete + UsbRtos_Err_Delete_Mpl, // Failure of Memory Pool Delete + UsbRtos_Err_Delete_Tsk, // Failure of Task Delete + #if defined(USB_CFG_OTG_USE) + UsbRtos_Err_Init_OTG_Detach_Tmr, // Failure of OTG Detach Timer Creation + UsbRtos_Err_Delete_OTG_Detach_Tmr, // Failure of OTG Detach Timer Delete + UsbRtos_Err_Init_OTG_Chattering_Tmr, // Failure of OTG Chattering Timer Creation + UsbRtos_Err_Delete_OTG_Chattering_Tmr, // Failure of OTG Chattering Timer Creation + UsbRtos_Err_Init_OTG_HNP_Tmr, // Failure of OTG HNP Timer Creation + UsbRtos_Err_Delete_OTG_HNP_Tmr, // Failure of OTG HNP Timer Delete + #endif /* defined(USB_CFG_OTG_USE) */ +} usb_rtos_err_t; + +/****************************************************************************** + * Exported global variables + ******************************************************************************/ +extern rtos_mbx_id_t * g_mbx_table[]; +extern rtos_mem_id_t * g_mpl_table[]; + +/****************************************************************************** + * Exported global functions (to be accessed by other files) + ******************************************************************************/ +usb_rtos_err_t usb_rtos_configuration(usb_cfg_t const * const p_cfg); +usb_rtos_err_t usb_rtos_delete(uint8_t module_number); + + #endif /* #if (BSP_CFG_RTOS != 0) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_CSTD_RTOS_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h new file mode 100644 index 0000000000..64bae1d62f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h @@ -0,0 +1,902 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef R_USB_EXTERN_H +#define R_USB_EXTERN_H + +#include "r_usb_basic_api.h" +#if defined(USB_CFG_OTG_USE) + #include "r_external_irq_api.h" +#endif /* defined(USB_CFG_OTG_USE) */ + +#if (BSP_CFG_RTOS != 0) + #include "r_usb_cstd_rtos.h" +#endif /* #if (BSP_CFG_RTOS != 0) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/***************************************************************************** + * Public Variables + ******************************************************************************/ + +/* r_usbif_api.c */ +#if (BSP_CFG_RTOS == 0) +extern uint16_t g_usb_change_device_state[USB_NUM_USBIP]; +#endif + +/* r_usb_cdataio.c */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +extern usb_utr_t * g_p_usb_pstd_pipe[USB_MAX_PIPE_NO + 1U]; +extern uint32_t g_usb_pstd_data_cnt[USB_MAX_PIPE_NO + 1U]; /* PIPEn Buffer counter */ +extern uint8_t * gp_usb_pstd_data[USB_MAX_PIPE_NO + 1U]; /* PIPEn Buffer pointer(8bit) */ +extern uint8_t g_usb_pipe_peri[USB_MAX_PIPE_POS_PERI]; /* Pipe number of USB Peri transfer.(Read pipe/Write pipe) */ + + #if defined(USB_CFG_PCDC_USE) +extern uint8_t g_usb_pcdc_bulk_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_pcdc_bulk_out_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_pcdc_int_in_pipe[USB_NUM_USBIP]; + #if defined(USB_CFG_PCDC2_USE) +extern uint8_t g_usb_pcdc2_bulk_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_pcdc2_bulk_out_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_pcdc2_int_in_pipe[USB_NUM_USBIP]; + #endif /* defined(USB_CFG_PCDC2_USE) */ + #endif /* defined(USB_CFG_PCDC_USE) */ + + #if defined(USB_CFG_PHID_USE) +extern uint8_t g_usb_phid_int_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_phid_int_out_pipe[USB_NUM_USBIP]; + #if defined(USB_CFG_PHID2_USE) +extern uint8_t g_usb_phid2_int_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_phid2_int_out_pipe[USB_NUM_USBIP]; + #endif /* defined(USB_CFG_PHID2_USE) */ + #endif /* defined(USB_CFG_PHID_USE) */ + + #if defined(USB_CFG_PMSC_USE) +extern uint8_t g_usb_pmsc_bulk_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_pmsc_bulk_out_pipe[USB_NUM_USBIP]; + #endif /* defined(USB_CFG_PMSC_USE) */ + + #if defined(USB_CFG_PPRN_USE) +extern uint8_t g_usb_pprn_bulk_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_pprn_bulk_out_pipe[USB_NUM_USBIP]; + #endif /* defined(USB_CFG_PMSC_USE) */ +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +extern usb_utr_t * g_p_usb_hstd_pipe[][USB_MAX_PIPE_NO + 1U]; /* Message pipe */ +extern uint8_t * gp_usb_hstd_data_ptr[][USB_MAX_PIPE_NO + 1U]; /* PIPEn Buffer pointer(8bit) */ +extern uint32_t g_usb_hstd_data_cnt[][USB_MAX_PIPE_NO + 1U]; /* PIPEn Buffer counter */ +extern uint32_t g_usb_hstd_data_cnt_pipe0[]; /* PIPE0 Control transfer data stage receive size */ +extern uint16_t g_usb_hstd_hs_enable[]; /* Hi-speed enable */ +extern uint8_t g_usb_pipe_host[USB_MAX_PIPE_POS_HOST]; /* Pipe number of USB Host transfer.(Read pipe/Write pipe) */ + #if defined(USB_CFG_HCDC_USE) + #include "r_usb_hcdc_cfg.h" +extern uint8_t g_usb_hcdc_bulk_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_hcdc_bulk_out_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_hcdc_int_in_pipe[USB_NUM_USBIP]; + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) +extern uint8_t g_usb_hcdc2_bulk_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_hcdc2_bulk_out_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_hcdc2_int_in_pipe[USB_NUM_USBIP]; + #endif + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) + #include "r_usb_hhid_cfg.h" +extern uint8_t g_usb_hhid_int_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_hhid_int_out_pipe[USB_NUM_USBIP]; + #if (USB_CFG_HHID_MULTI == USB_CFG_ENABLE) +extern uint8_t g_usb_hhid2_int_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_hhid3_int_in_pipe[USB_NUM_USBIP]; + #endif + #endif /* defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) + #include "r_usb_hprn_cfg.h" +extern uint8_t g_usb_hprn_bulk_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_hprn_bulk_out_pipe[USB_NUM_USBIP]; + #if (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) +extern uint8_t g_usb_hprn2_bulk_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_hprn2_bulk_out_pipe[USB_NUM_USBIP]; + #endif + #endif /* defined(USB_CFG_HPRN_USE) */ + + #if defined(USB_CFG_HUVC_USE) +extern uint8_t g_usb_huvc_iso_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_huvc_iso_out_pipe[USB_NUM_USBIP]; + #endif /* defined(USB_CFG_HUVC_USE) */ + + #if defined(USB_CFG_HAUD_USE) +extern uint8_t g_usb_haud_iso_in_pipe[USB_NUM_USBIP]; +extern uint8_t g_usb_haud_iso_out_pipe[USB_NUM_USBIP]; + #endif /* defined(USB_CFG_HAUD_USE) */ + +/* r_usb_cinthandler_usbip0.c */ +extern usb_utr_t g_usb_cstd_int_msg[][USB_INTMSGMAX]; /* Interrupt message */ +extern uint16_t g_usb_cstd_int_msg_cnt[]; /* Interrupt message count */ + +/* r_usb_hdriver.c */ +extern uint16_t g_usb_hstd_ignore_cnt[][USB_MAX_PIPE_NO + 1U]; /* Ignore count */ +extern usb_hcdreg_t g_usb_hstd_device_drv[][USB_MAXDEVADDR + 1U]; /* Device driver (registration) */ +extern volatile uint16_t g_usb_hstd_device_info[][USB_MAXDEVADDR + 1U][8U]; +extern usb_ctrl_trans_t g_usb_ctrl_request[USB_NUM_USBIP][USB_MAXDEVADDR + 1]; + #if (BSP_CFG_RTOS != 0) +extern usb_hdl_t g_usb_hstd_sus_res_task_id[]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + +/* port status, config num, interface class, speed, */ +extern uint16_t g_usb_hstd_remort_port[]; +extern uint16_t g_usb_hstd_ctsq[]; /* Control transfer stage management */ +extern uint16_t g_usb_hstd_mgr_mode[]; /* Manager mode */ +extern uint16_t g_usb_hstd_dcp_register[][USB_MAXDEVADDR + 1U]; /* DEVSEL & DCPMAXP (Multiple device) */ +extern uint16_t g_usb_hstd_device_addr[]; /* Device address */ +extern uint16_t g_usb_hstd_device_speed[]; /* Reset handshake result */ +extern uint16_t g_usb_hstd_device_num[]; /* Device driver number */ + +/* r_usb_hmanager.c */ +extern uint16_t g_usb_hstd_enum_seq[]; /* Enumeration request */ +extern uint16_t g_usb_hstd_device_descriptor[][USB_DEVICESIZE / 2U]; +extern uint16_t g_usb_hstd_config_descriptor[][USB_CONFIGSIZE / 2U]; +extern uint16_t g_usb_hstd_suspend_pipe[][USB_MAX_PIPE_NO + 1U]; +extern uint16_t g_usb_hstd_check_enu_result[]; /* Enumeration result check */ +extern uint8_t g_usb_hstd_class_data[USB_NUM_USBIP][CLSDATASIZE]; + +/* r_usb_hcontrolrw.c */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE +extern uint16_t g_usb_hstd_response_counter[]; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + #if USB_CFG_BC == USB_CFG_ENABLE +extern usb_bc_status_t g_usb_hstd_bc[2U]; +extern void (* usb_hstd_bc_func[USB_BC_STATE_MAX][USB_BC_EVENT_MAX])(usb_utr_t * ptr); + + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/* r_usb_pdriver.c */ +extern usb_cb_t g_usb_pstd_stall_cb; /* Stall Callback function */ +extern uint16_t g_usb_pstd_config_num; /* Configuration Number */ +extern uint16_t g_usb_pstd_stall_pipe[USB_MAX_PIPE_NO + 1U]; /* Stall Pipe info */ +extern uint16_t g_usb_pstd_alt_num[]; /* Alternate */ +extern uint16_t g_usb_pstd_test_mode_select; /* Test Mode Selectors */ +extern uint16_t g_usb_pstd_test_mode_flag; /* Test Mode Flag */ +extern uint16_t g_usb_pstd_eptbl_index[2][USB_MAX_EP_NO + 1U]; /* Index of Endpoint Information table */ +extern uint16_t g_usb_pstd_req_type; /* Request type */ +extern uint16_t g_usb_pstd_req_value; /* Value */ +extern uint16_t g_usb_pstd_req_index; /* Index */ +extern uint16_t g_usb_pstd_req_length; /* Length */ +extern usb_pcdreg_t g_usb_pstd_driver; /* Driver registration */ +extern usb_setup_t g_usb_pstd_req_reg; /* Request variable */ +extern usb_int_t g_usb_pstd_usb_int; +extern uint16_t g_usb_pstd_pipe0_request; +extern uint16_t g_usb_pstd_std_request; +extern uint16_t g_usb_peri_connected; /* Peri CDC application enable */ + + #if defined(USB_CFG_PMSC_USE) +extern uint8_t g_usb_pmsc_usbip; + #endif /* defined(USB_CFG_PMSC_USE) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +extern uint16_t g_usb_pstd_remote_wakeup; /* Remote Wake up Enable Flag */ +extern uint16_t g_usb_pstd_remote_wakeup_state; /* Result for Remote wake up */ + +/* r_usb.c */ + +extern volatile uint16_t g_usb_usbmode[USB_NUM_USBIP]; /* USB mode HOST/PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +extern usb_utr_t g_usb_hdata[USB_NUM_USBIP][USB_MAXPIPE_NUM + 1]; + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +extern usb_utr_t g_usb_pdata[USB_MAXPIPE_NUM + 1]; + +#endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + +#if (BSP_CFG_RTOS != 0) +extern usb_instance_ctrl_t g_usb_cstd_event[]; +extern rtos_task_id_t g_usb_cur_task_hdl[]; +#else /* #if (BSP_CFG_RTOS != 0) */ +extern usb_event_t g_usb_cstd_event; +#endif /* #if (BSP_CFG_RTOS != 0) */ + +extern usb_pipe_table_t g_usb_pipe_table[USB_NUM_USBIP][USB_MAXPIPE_NUM + 1]; +extern uint16_t g_usb_cstd_bemp_skip[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; + +/* r_usb_creg_abs.c */ +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +extern uint16_t g_usb_hstd_use_pipe[]; + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if (BSP_CFG_RTOS != 0) +extern rtos_sem_id_t g_usb_semaphore_hdl[]; +extern usb_utr_t * get_usb_int_buf(void); + + #if (BSP_CFG_RTOS == 1) +extern TX_SEMAPHORE g_usb_host_usbx_sem[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1]; // usbx + #endif /* #if (BSP_CFG_RTOS == 1) */ +#endif + +/* #if (BSP_CFG_RTOS != 0) */ +extern usb_callback_t * g_usb_apl_callback[USB_NUM_USBIP]; +extern usb_callback_args_t * g_usb_apl_callback_memory[USB_NUM_USBIP]; + +/* r_usb_pbc.c */ +#if USB_CFG_BC == USB_CFG_ENABLE + #if (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI +extern uint16_t g_usb_bc_detect; + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ +#endif /* USB_CFG_BC == USB_CFG_ENABLE */ + +#if defined(USB_CFG_HMSC_USE) +extern uint8_t g_drive_search_lock; +extern uint8_t g_drive_search_que[]; +extern uint8_t g_drive_search_que_cnt; + +#endif /* defined(USB_CFG_HMSC_USE) */ + +#if defined(USB_CFG_OTG_USE) +extern uint8_t g_usb_otg_hnp_process[USB_NUM_USBIP]; +extern uint8_t g_is_A_device[USB_NUM_USBIP]; +extern uint8_t g_is_A_cable_detach[USB_NUM_USBIP]; +extern void (* g_p_otg_callback[USB_NUM_USBIP])(ULONG mode); +extern volatile uint8_t g_usb_is_otg_attach_interrupt[USB_NUM_USBIP]; + +extern TX_TIMER g_usb_otg_detach_timer; + #if USB_NUM_USBIP == 2 +extern TX_TIMER g_usb2_otg_detach_timer; + #endif /* USB_NUM_USBIP == 2 */ +extern volatile uint8_t g_usb_otg_hnp_counter; +extern TX_TIMER g_usb_otg_hnp_timer; +#endif /* defined(USB_CFG_OTG_USE) */ + +#if (USB_DEBUG_ON == 2) || (USB_DEBUG_ON == 3) + +/* Debug Print Buffer */ +extern uint8_t g_usb_print_buffer[]; +extern uint8_t g_usb_qe_error_string_length; +#endif /* USB_DEBUG_ON == 2 */ + +/***************************************************************************** + * Public Functions + ******************************************************************************/ + +/* r_usb.c */ +void Test_USB_Change_device_state(uint16_t state); +void Test_USB_Change_remote_wakeup(uint16_t data1, uint16_t data2); +void Test_USB_Change_usbmode(uint16_t data1); +void Test_USB_Change_read_write_pointer(uint16_t write_val, + uint16_t read_val, + usb_status_t code_val, + uint16_t request_val); +void Test_USB_Change_Info(usb_instance_ctrl_t * p_ctrl, uint16_t ifcls, uint16_t speed, uint16_t port, uint16_t state); +void Test_USB_Change_Pipe_flag(uint16_t data1, uint16_t data2, uint16_t pipe_no); + +fsp_err_t usb_module_start(uint8_t ip_type); +fsp_err_t usb_module_register_clear(uint8_t usb_ip); +fsp_err_t usb_module_stop(uint8_t ip_type); +void usb_cpu_delay_xms(uint16_t time); +void usb_cpu_delay_1us(uint16_t time); +void usb_cpu_usbint_init(uint8_t ip_type, usb_cfg_t const * const cfg); +uint16_t usb_chattaring(uint16_t * syssts); + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void usb_cpu_int_enable(void); +void usb_cpu_int_disable(void); + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ +bool usb_check_use_usba_module(usb_utr_t * ptr); + +/* r_usb_cdataio.c */ +uint8_t usb_get_usepipe(usb_instance_ctrl_t * p_ctrl, usb_transfer_t dir); +usb_er_t usb_data_read(usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size); +usb_er_t usb_ctrl_read(usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size); +usb_er_t usb_data_write(usb_instance_ctrl_t * p_ctrl, uint8_t const * const buf, uint32_t size); +usb_er_t usb_ctrl_write(usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size); +usb_er_t usb_data_stop(usb_instance_ctrl_t * p_ctrl, usb_transfer_t type); +usb_er_t usb_ctrl_stop(usb_instance_ctrl_t * p_ctrl); +void usb_cstd_debug_hook(uint16_t error_code); + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +usb_er_t usb_pstd_transfer_start(usb_utr_t * ptr); +usb_er_t usb_pstd_transfer_end(usb_utr_t * p_utr, uint16_t pipe); +void usb_pstd_change_device_state(uint16_t state, uint16_t keyword, usb_cb_t complete, usb_utr_t * p_utr); +void usb_pstd_driver_registration(usb_pcdreg_t * registinfo); +void usb_pstd_driver_release(void); + + #if defined(USB_HIGH_SPEED_MODULE) +uint16_t usb_pstd_get_pipe_buf_value(uint16_t pipe_no); + + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void usb_hstd_send_start(usb_utr_t * ptr, uint16_t pipe); +void usb_hstd_buf_to_fifo(usb_utr_t * ptr, uint16_t pipe, uint16_t useport); +uint16_t usb_hstd_write_data(usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode); +void usb_hstd_receive_start(usb_utr_t * ptr, uint16_t pipe); +void usb_hstd_fifo_to_buf(usb_utr_t * ptr, uint16_t pipe, uint16_t useport); +uint16_t usb_hstd_read_data(usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode); +void usb_hstd_data_end(usb_utr_t * ptr, uint16_t pipe, uint16_t status); +usb_er_t usb_hstd_transfer_end(usb_utr_t * ptr, uint16_t pipe, uint16_t status); +usb_er_t usb_hstd_change_device_state(usb_utr_t * ptr, usb_cb_t complete, uint16_t msginfo, uint16_t member); +usb_er_t usb_hstd_mgr_open(usb_utr_t * ptr); +void usb_hstd_driver_registration(usb_utr_t * ptr, usb_hcdreg_t * callback); +void usb_hstd_driver_release(usb_utr_t * ptr, uint8_t devclass); +void usb_hstd_set_pipe_info(uint16_t ip_no, uint16_t pipe_no, usb_pipe_table_reg_t * src_ep_tbl); +void usb_hstd_return_enu_mgr(usb_utr_t * ptr, uint16_t cls_result); +fsp_err_t usb_hstd_hcd_open(usb_utr_t * ptr); + +uint8_t usb_hstd_make_pipe_reg_info(uint16_t ip_no, + uint16_t address, + uint16_t usb_class, + uint16_t speed, + uint8_t * descriptor, + usb_pipe_table_reg_t * pipe_table_work); + + #if defined(USB_HIGH_SPEED_MODULE) +uint16_t usb_hstd_get_pipe_buf_value(uint16_t pipe_no); + + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +void usb_pstd_send_start(uint16_t pipe); +void usb_pstd_buf_to_fifo(uint16_t pipe, uint16_t useport, usb_utr_t * p_utr); +uint16_t usb_pstd_write_data(uint16_t pipe, uint16_t pipemode, usb_utr_t * p_utr); +void usb_pstd_receive_start(uint16_t pipe); +void usb_pstd_fifo_to_buf(uint16_t pipe, uint16_t useport, usb_utr_t * p_utr); +uint16_t usb_pstd_read_data(uint16_t pipe, uint16_t pipemode, usb_utr_t * p_utr); +void usb_pstd_data_end(uint16_t pipe, uint16_t status, usb_utr_t * p_utr); + +uint8_t usb_pstd_set_pipe_table(uint8_t * descriptor, usb_utr_t * p_utr, uint8_t class_info); +void usb_pstd_clr_pipe_table(uint8_t usb_ip); +void usb_pstd_set_pipe_reg(usb_utr_t * p_utr); +void usb_pstd_clr_pipe_reg(usb_utr_t * p_utr); +uint8_t usb_pstd_get_pipe_no(uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint8_t class_info); + +/* r_usb_cintfifo.c */ +void usb_pstd_nrdy_pipe_process(usb_utr_t * p_utr, uint16_t bitsts); +void usb_pstd_bemp_pipe_process(usb_utr_t * p_utr, uint16_t bitsts); +void usb_pstd_brdy_pipe_process(usb_utr_t * p_utr, uint16_t bitsts); + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void usb_hstd_nrdy_pipe_process(usb_utr_t * ptr, uint16_t bitsts); +void usb_hstd_bemp_pipe_process(usb_utr_t * ptr, uint16_t bitsts); +void usb_hstd_brdy_pipe_process(usb_utr_t * ptr, uint16_t bitsts); + +#endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + +/* r_usb_clibusbip.c */ +void usb_cstd_nrdy_enable(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_get_pid(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_port_speed(usb_utr_t * ptr); +uint16_t usb_cstd_get_maxpacket_size(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_get_pipe_dir(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_get_pipe_type(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_do_aclrm(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_set_buf(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_clr_stall(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_usb_task(void); +void usb_class_task(void); +void usb_set_event(usb_status_t event, usb_instance_ctrl_t * ctrl); +uint16_t usb_cstd_remote_wakeup(usb_utr_t * p_utr); + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +uint8_t usb_hstd_pipe_to_epadr(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_hstd_pipe2fport(usb_utr_t * ptr, uint16_t pipe); +void usb_hstd_dummy_function(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_hstd_suspend_complete(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_hstd_resume_complete(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_hstd_berne_enable(usb_utr_t * ptr); +void usb_hstd_sw_reset(usb_utr_t * ptr); +void usb_hstd_set_hse(usb_utr_t * ptr, uint16_t speed); +void usb_hstd_do_sqtgl(usb_utr_t * ptr, uint16_t pipe, uint16_t toggle); +uint16_t usb_hstd_get_devsel(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_hstd_get_device_address(usb_utr_t * ptr, uint16_t pipe); + +#endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + +#if (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI +uint16_t usb_pstd_epadr2pipe(uint16_t Dir_Ep, usb_utr_t * p_utr); +uint16_t usb_pstd_pipe2fport(usb_utr_t * p_utr, uint16_t pipe); +uint16_t usb_pstd_hi_speed_enable(usb_utr_t * p_utr); +void usb_pstd_dummy_function(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_pstd_dummy_trn(usb_setup_t * preq, uint16_t ctsq, usb_utr_t * p_utr); + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +/* r_usb_creg_abs.c */ +uint16_t usb_cstd_is_set_frdy(usb_utr_t * ptr, uint16_t pipe, uint16_t fifosel, uint16_t isel); +void usb_cstd_chg_curpipe(usb_utr_t * ptr, uint16_t pipe, uint16_t fifosel, uint16_t isel); +void usb_cstd_set_transaction_counter(usb_utr_t * ptr, uint16_t trnreg, uint16_t trncnt); +void usb_cstd_clr_transaction_counter(usb_utr_t * ptr, uint16_t trnreg); +void usb_cstd_pipe_init(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_clr_pipe_cnfg(usb_utr_t * ptr, uint16_t pipe_no); +void usb_cstd_set_nak(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_get_buf_size(usb_utr_t * ptr, uint16_t pipe); + +#if ((USB_CFG_MODE &USB_CFG_HOST) == USB_CFG_HOST) +uint8_t * usb_hstd_write_fifo(usb_utr_t * ptr, uint16_t count, uint16_t pipemode, uint8_t * write_p); +uint8_t * usb_hstd_read_fifo(usb_utr_t * ptr, uint16_t count, uint16_t pipemode, uint8_t * read_p); +void usb_hstd_forced_termination(usb_utr_t * ptr, uint16_t pipe, uint16_t status); +usb_regadr_t usb_hstd_get_usb_ip_adr(uint16_t ipnum); +void usb_hstd_nrdy_endprocess(usb_utr_t * ptr, uint16_t pipe); + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE &USB_CFG_PERI) == USB_CFG_PERI) +uint8_t * usb_pstd_write_fifo(uint16_t count, uint16_t pipemode, uint8_t * write_p, usb_utr_t * p_utr); +uint8_t * usb_pstd_read_fifo(uint16_t count, uint16_t pipemode, uint8_t * read_p, usb_utr_t * p_utr); +void usb_pstd_forced_termination(uint16_t pipe, uint16_t status, usb_utr_t * p_utr); +void usb_pstd_interrupt_clock(uint8_t usb_ip); +void usb_pstd_self_clock(uint8_t usb_ip); +void usb_pstd_stop_clock(uint8_t usb_ip); + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/* r_usb_cinthandler_usbip0.c */ +void usb_hstd_usb_handler(void); +void usb_hstd_dma_handler(void); +void usb_hstd_init_usb_message(usb_utr_t * ptr); + +/* r_usb_cinthandler_usbip1.c */ +void usb2_hstd_usb_handler(void); +void usb2_hstd_dma_handler(void); + +/* r_usb_hdriver.c */ +uint8_t * usb_hstd_dev_descriptor(usb_utr_t * ptr); +uint8_t * usb_hstd_con_descriptor(usb_utr_t * ptr); +void usb_hstd_device_resume(usb_utr_t * ptr, uint16_t devaddr); +usb_er_t usb_hstd_hcd_snd_mbx(usb_utr_t * ptr, uint16_t msginfo, uint16_t dat, uint16_t * adr, usb_cb_t callback); +void usb_hstd_mgr_snd_mbx(usb_utr_t * ptr, uint16_t msginfo, uint16_t dat, uint16_t res); + + #if (BSP_CFG_RTOS == 1) +void usb_hstd_hcd_task(ULONG entry_input); + + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_hstd_hcd_task(void * stacd); + + #endif /* #if (BSP_CFG_RTOS == 1) */ +usb_er_t usb_hstd_transfer_start(usb_utr_t * ptr); +usb_er_t usb_hstd_transfer_start_req(usb_utr_t * ptr); +void usb_hstd_hcd_rel_mpl(usb_utr_t * ptr, uint16_t n); +usb_er_t usb_hstd_clr_stall(usb_utr_t * ptr, uint16_t pipe, usb_cb_t complete); +usb_er_t usb_hstd_clr_feature(usb_utr_t * ptr, uint16_t addr, uint16_t epnum, usb_cb_t complete); +void usb_hstd_suspend(usb_utr_t * ptr); +void usb_hstd_bus_int_disable(usb_utr_t * ptr); +void usb_class_request_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +void usb_host_registration(usb_utr_t * ptr, usb_class_t type); +void usb_hstd_connect_err_event_set(uint16_t ip_no); + +/* r_usb_hcontrolrw.c */ +uint16_t usb_hstd_ctrl_write_start(usb_utr_t * ptr, uint32_t bsize, uint8_t * table); +void usb_hstd_ctrl_read_start(usb_utr_t * ptr, uint32_t bsize, uint8_t * table); +void usb_hstd_status_start(usb_utr_t * ptr); +void usb_hstd_ctrl_end(usb_utr_t * ptr, uint16_t status); +void usb_hstd_setup_start(usb_utr_t * ptr); + +/* r_usb_hintfifo.c */ +void usb_hstd_brdy_pipe(usb_utr_t * ptr); +void usb_hstd_nrdy_pipe(usb_utr_t * ptr); +void usb_hstd_bemp_pipe(usb_utr_t * ptr); + +/* r_usb_hstdfunction.c */ +void usb_hstd_bchg0function(usb_utr_t * ptr); +void usb_hstd_ls_connect_function(usb_utr_t * ptr); +void usb_hstd_attach_function(void); +void usb_hstd_ovrcr0function(usb_utr_t * ptr); + +void usb_hdriver_init(usb_utr_t * ptr, usb_class_t type); +void usb_class_driver_start(usb_utr_t * ptr); + + #if (BSP_CFG_RTOS != 0) +void class_trans_result(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +uint16_t class_trans_wait_tmo(usb_utr_t * ptr, uint16_t tmo); + + #endif /* #if (BSP_CFG_RTOS != 0) */ + +/* r_usb_hreg_abs */ +void usb_hstd_set_hub_port(usb_utr_t * ptr, uint16_t addr, uint16_t upphub, uint16_t hubport); +void usb_hstd_interrupt_handler(usb_utr_t * ptr); +uint16_t usb_hstd_chk_attach(usb_utr_t * ptr); +void usb_hstd_chk_clk(usb_utr_t * ptr, uint16_t event); +void usb_hstd_detach_process(usb_utr_t * ptr); +void usb_hstd_read_lnst(usb_utr_t * ptr, uint16_t * buf); +void usb_hstd_attach_process(usb_utr_t * ptr); +void usb_hstd_chk_sof(usb_utr_t * ptr); +void usb_hstd_bus_reset(usb_utr_t * ptr); +void usb_hstd_resume_process(usb_utr_t * ptr); +uint16_t usb_hstd_support_speed_check(usb_utr_t * ptr); + +/* r_usb_hlibusbip.c */ +void usb_hstd_set_dev_addr(usb_utr_t * ptr, uint16_t addr, uint16_t speed); +void usb_hstd_bchg_enable(usb_utr_t * ptr); +void usb_hstd_set_uact(usb_utr_t * ptr); +void usb_hstd_ovrcr_enable(usb_utr_t * ptr); +void usb_hstd_ovrcr_disable(usb_utr_t * ptr); +void usb_hstd_attch_enable(usb_utr_t * ptr); +void usb_hstd_attch_disable(usb_utr_t * ptr); +void usb_hstd_dtch_enable(usb_utr_t * ptr); +void usb_hstd_dtch_disable(usb_utr_t * ptr); +usb_er_t usb_hstd_set_pipe_reg_for_devadr(usb_utr_t * ptr, uint16_t device_address); +uint8_t usb_hstd_get_pipe_no(uint16_t ip_no, uint16_t address, uint16_t usb_class, uint8_t type, uint8_t dir); +uint16_t usb_hstd_get_pipe_peri_value(uint16_t speed, uint8_t binterval); +void usb_hstd_clr_pipe_table(uint16_t ip_no, uint16_t device_address); +void usb_hstd_set_pipe_reg(usb_utr_t * ptr, uint16_t pipe_no); + +uint16_t usb_hstd_chk_dev_addr(usb_utr_t * ptr, uint16_t addr); +uint16_t usb_hstd_get_dev_speed(usb_utr_t * ptr, uint16_t addr); +void usb_hstd_bchg_disable(usb_utr_t * ptr); + +/* r_usb_hsignal.c */ +void usb_hstd_vbus_control(usb_utr_t * ptr, uint16_t command); +void usb_hstd_suspend_process(usb_utr_t * ptr); +void usb_hstd_attach(usb_utr_t * ptr, uint16_t result); +void usb_hstd_detach(usb_utr_t * ptr); + +/* r_usb_hmanager.c */ +void usb_hstd_notif_ator_detach(usb_utr_t * ptr, uint16_t result); +void usb_hstd_ovcr_notifiation(usb_utr_t * ptr); +void usb_hstd_status_result(usb_utr_t * ptr, uint16_t data1, uint16_t result); +void usb_hstd_enum_get_descriptor(usb_utr_t * ptr, uint16_t addr, uint16_t cnt_value); +void usb_hstd_enum_set_address(usb_utr_t * ptr, uint16_t addr, uint16_t setaddr); +void usb_hstd_enum_set_configuration(usb_utr_t * ptr, uint16_t addr, uint16_t confnum); +void usb_hstd_enum_dummy_request(usb_utr_t * ptr, uint16_t addr, uint16_t cnt_value); +void usb_hstd_electrical_test_mode(usb_utr_t * ptr, uint16_t product_id); + + #if (BSP_CFG_RTOS == 1) +void usb_hstd_mgr_task(ULONG entry_input); + + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_hstd_mgr_task(void * stacd); + + #endif /* #if (BSP_CFG_RTOS == 1) */ + +extern void (* g_usb_hstd_enumaration_process[])(usb_utr_t *, uint16_t, uint16_t); + + #if (BSP_CFG_RTOS != 0) +uint16_t usb_hstd_get_string_desc(usb_utr_t * ptr, uint16_t addr, uint16_t string); +uint16_t usb_hstd_set_feature(usb_utr_t * ptr, uint16_t addr, uint16_t epnum); +uint16_t usb_hstd_get_config_desc(usb_utr_t * ptr, uint16_t addr, uint16_t length); + + #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) +void usb_hid_set_protocol(usb_utr_t * ptr, uint16_t addr, uint16_t setaddr); +void usb_hid_get_string_desc(usb_utr_t * ptr, uint16_t addr, uint16_t string); + + #endif + + #else /* #if (BSP_CFG_RTOS != 0) */ +uint16_t usb_hstd_get_string_desc(usb_utr_t * ptr, uint16_t addr, uint16_t string, usb_cb_t complete); +uint16_t usb_hstd_set_feature(usb_utr_t * ptr, uint16_t addr, uint16_t epnum, usb_cb_t complete); +uint16_t usb_hstd_get_config_desc(usb_utr_t * ptr, uint16_t addr, uint16_t length, usb_cb_t complete); + + #endif /* #if (BSP_CFG_RTOS != 0) */ + +void usb_hstd_submit_result(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_hstd_mgr_suspend(usb_utr_t * ptr, uint16_t info); +void usb_hstd_device_state_ctrl(usb_utr_t * ptr, uint16_t devaddr, uint16_t msginfo); +void usb_hstd_device_state_ctrl2(usb_utr_t * ptr, + usb_cb_t complete, + uint16_t devaddr, + uint16_t msginfo, + uint16_t mgr_msginfo); +void usb_hstd_mgr_reset(usb_utr_t * ptr, uint16_t addr); +void usb_hstd_mgr_resume(usb_utr_t * ptr, uint16_t info); + +uint16_t usb_hstd_std_req_check(uint16_t errcheck); + +/* r_usb_hhubsys.c */ +uint16_t usb_hhub_check_descriptor(uint8_t * table, uint16_t spec); +void usb_hhub_open(usb_utr_t * ptr, uint16_t devaddr, uint16_t data2); +void usb_hhub_close(usb_utr_t * ptr, uint16_t hubaddr, uint16_t data2); +void usb_hhub_registration(usb_utr_t * ptr, usb_hcdreg_t * callback); +uint16_t usb_hhub_get_hub_information(usb_utr_t * ptr, uint16_t hubaddr, usb_cb_t complete); +uint16_t usb_hhub_get_port_information(usb_utr_t * ptr, uint16_t hubaddr, uint16_t port, usb_cb_t complete); +void usb_hhub_task(void * stacd); +uint16_t usb_hhub_get_string_descriptor1(usb_utr_t * ptr, uint16_t devaddr, uint16_t index, usb_cb_t complete); +uint16_t usb_hhub_get_string_descriptor1check(uint16_t errcheck); +uint16_t usb_hhub_get_string_descriptor2(usb_utr_t * ptr, uint16_t devaddr, uint16_t index, usb_cb_t complete); +uint16_t usb_hhub_get_string_descriptor_to_check(uint16_t errcheck); + +/* r_usb_hbc.c */ + #if USB_CFG_BC == USB_CFG_ENABLE +void usb_hstd_pddetint_process(usb_utr_t * ptr); + + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + +/* r_usb_hostelectrical.c */ +void usb_hstd_test_stop(usb_utr_t * ptr); +void usb_hstd_test_signal(usb_utr_t * ptr, uint16_t command); +void usb_hstd_test_uact_ctrl(usb_utr_t * ptr, uint16_t command); +void usb_hstd_test_vbus_ctrl(usb_utr_t * ptr, uint16_t command); +void usb_hstd_test_bus_reset(usb_utr_t * ptr); +void usb_hstd_test_suspend(usb_utr_t * ptr); +void usb_hstd_test_resume(usb_utr_t * ptr); + +/* r_usb_hscheduler.c */ +fsp_err_t usb_cstd_wai_msg(uint8_t id, usb_msg_t * mess, usb_tm_t times); +void usb_cstd_wait_scheduler(void); +void usb_cstd_sche_init(void); +fsp_err_t usb_cstd_check(usb_er_t err); +uint8_t usb_cstd_check_schedule(void); +void usb_cstd_scheduler(void); +void usb_cstd_set_task_pri(uint8_t tasknum, uint8_t pri); + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +usb_er_t usb_cstd_pget_blk(uint8_t id, usb_utr_t ** blk, uint8_t ip); +usb_er_t usb_cstd_rel_blk(uint8_t id, usb_utr_t * blk); + +/* r_usb_hscheduler.c */ +usb_er_t usb_cstd_snd_msg(uint8_t id, usb_msg_t * mess); +usb_er_t usb_cstd_rec_msg(uint8_t id, usb_msg_t ** mess, usb_tm_t tm); +usb_er_t usb_cstd_isnd_msg(uint8_t id, usb_msg_t * mess); + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/* r_usb_pinthandler_usbip0.c */ +void usb_pstd_usb_handler(void); + +/* r_usb_pdriver.c */ + #if (BSP_CFG_RTOS == 1) +void usb_pstd_pcd_task(ULONG entry_input); + + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_pstd_pcd_task(void); + + #endif /* #if (BSP_CFG_RTOS == 1) */ +usb_er_t usb_pstd_set_submitutr(usb_utr_t * utrmsg); +void usb_pstd_clr_alt(void); +void usb_pstd_clr_mem(void); +void usb_pstd_set_config_num(uint16_t Value); +void usb_pstd_clr_eptbl_index(void); +uint16_t usb_pstd_get_interface_num(void); +uint16_t usb_pstd_get_alternate_num(uint16_t int_num); +void usb_pstd_set_eptbl_index(uint16_t int_num, uint16_t alt_num); +uint16_t usb_pstd_chk_remote(void); +uint8_t usb_pstd_get_current_power(void); + +/* r_usb_pcontrolrw.c */ +uint16_t usb_pstd_ctrl_read(uint32_t bsize, uint8_t * table, usb_utr_t * p_utr); +void usb_pstd_ctrl_write(uint32_t bsize, uint8_t * table, usb_utr_t * p_utr); +void usb_pstd_ctrl_end(uint16_t status, usb_utr_t * p_utr); + +/* r_usb_pintfifo.c */ +void usb_pstd_brdy_pipe(usb_utr_t * p_utr, uint16_t bitsts); +void usb_pstd_nrdy_pipe(usb_utr_t * p_utr, uint16_t bitsts); +void usb_pstd_bemp_pipe(usb_utr_t * p_utr, uint16_t bitsts); + +/* r_usb_pstdfunction.c */ +void usb_pstd_busreset_function(void); +void usb_pstd_suspend_function(void); +void usb_p_registration(usb_instance_ctrl_t * ctrl, usb_cfg_t * cfg); +void usb_pdriver_init(usb_instance_ctrl_t * ctrl, usb_cfg_t const * const cfg); + +/* r_usb_preg_abs.c */ +void usb_pstd_interrupt_handler(uint16_t * type, uint16_t * status, uint8_t usb_ip); +void usb_pstd_save_request(uint8_t usb_ip); +uint16_t usb_pstd_chk_configured(usb_utr_t * p_utr); +void usb_pstd_bus_reset(usb_utr_t * p_utr); +void usb_pstd_remote_wakeup(uint8_t usb_ip); +void usb_pstd_test_mode(usb_utr_t * p_utr); +void usb_pstd_attach_process(usb_utr_t * p_utr); +void usb_pstd_detach_process(usb_utr_t * p_utr); +void usb_pstd_suspend_process(usb_utr_t * p_utr); +void usb_pstd_resume_process(usb_utr_t * p_utr); +uint16_t usb_pstd_chk_vbsts(uint8_t usb_ip); +void usb_pstd_set_stall(uint16_t pipe, usb_utr_t * p_utr); +void usb_pstd_set_stall_pipe0(usb_utr_t * p_utr); + +/* r_usb_pstdrequest.c */ +void usb_pstd_stand_req0(usb_utr_t * p_utr); +void usb_pstd_stand_req1(usb_utr_t * p_utr); +void usb_pstd_stand_req2(usb_utr_t * p_utr); +void usb_pstd_stand_req3(usb_utr_t * p_utr); +void usb_pstd_stand_req4(usb_utr_t * p_utr); +void usb_pstd_stand_req5(usb_utr_t * p_utr); +void usb_pstd_set_feature_function(usb_utr_t * p_utr); + +/* peri_processing.c */ +void usb_peri_registration(usb_instance_ctrl_t * ctrl, usb_cfg_t const * const cfg); +void usb_peri_devdefault(usb_utr_t * ptr, uint16_t mode, uint16_t data2); +uint16_t usb_peri_pipe_info(uint8_t * table, uint16_t speed, uint16_t length, usb_utr_t * p_utr); +void usb_peri_configured(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_peri_detach(usb_utr_t * ptr, uint16_t usb_state, uint16_t data2); +void usb_peri_suspended(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_peri_resume(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_peri_interface(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_peri_class_request(usb_setup_t * preq, uint16_t ctsq, usb_utr_t * p_utr); +void usb_peri_class_request_ioss(usb_setup_t * req); +void usb_peri_class_request_rwds(usb_setup_t * req, usb_utr_t * p_utr); +void usb_peri_class_request_wds(usb_utr_t * p_utr); +void usb_peri_other_request(usb_setup_t * req, usb_utr_t * p_utr); +void usb_peri_class_request_wnss(usb_setup_t * req, usb_utr_t * p_utr); +void usb_peri_class_request_rss(usb_setup_t * req, usb_utr_t * p_utr); +void usb_peri_class_request_wss(usb_setup_t * req, usb_utr_t * p_utr); + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if defined(USB_CFG_PVND_USE) +extern void usb_pvnd_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_pvnd_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_PVND_USE) */ + +#if defined(USB_CFG_PCDC_USE) +extern void usb_pcdc_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_pcdc_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_PCDC_USE) */ + +#if defined(USB_CFG_PPRN_USE) +extern void usb_pprn_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_pprn_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_PPRN_USE) */ + +#if defined(USB_CFG_PHID_USE) +extern void usb_phid_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_phid_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_PHID_USE) */ + +#if defined(USB_CFG_PMSC_USE) + #if (BSP_CFG_RTOS != 1) +extern void usb_pmsc_task(void); + + #endif /* #if (BSP_CFG_RTOS != 1) */ +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if defined(USB_CFG_PAUD_USE) +extern void usb_paud_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_paud_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_PAUD_USE) */ + +#if defined(USB_CFG_HCDC_USE) +extern void usb_hcdc_read_complete(usb_utr_t * mess, uint16_t devadr, uint16_t data2); +extern void usb_hcdc_write_complete(usb_utr_t * mess, uint16_t devadr, uint16_t data2); +extern void usb_hcdc_registration(usb_utr_t * ptr); +extern void usb_hcdc_task(usb_vp_int_t stacd); +extern void usb_hcdc_driver_start(usb_utr_t * ptr); + +#endif /* defined(USB_CFG_HCDC_USE) */ + +#if defined(USB_CFG_HHID_USE) +extern void usb_hhid_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_hhid_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_hhid_registration(usb_utr_t * ptr); +extern void usb_hhid_task(usb_vp_int_t stacd); +extern void usb_hhid_driver_start(usb_utr_t * ptr); + +#endif /* defined(USB_CFG_HHID_USE) */ + +#if defined(USB_CFG_HMSC_USE) +extern void usb_hmsc_strg_cmd_complete(usb_utr_t * mess, uint16_t devadr, uint16_t data2); +extern void usb_hmsc_drive_complete(usb_utr_t * ptr, uint16_t addr, uint16_t data2); +extern void usb_hmsc_registration(usb_utr_t * ptr); +extern void usb_hmsc_driver_start(uint16_t ip_no); +extern void usb_hmsc_storage_driver_start(uint16_t ip_no); +extern void usb_hmsc_task(void); +extern void usb_hmsc_strg_drive_task(void); +extern uint16_t usb_hmsc_strg_drive_search(usb_utr_t * ptr, uint16_t addr, usb_cb_t complete); + +#endif /* defined(USB_CFG_HMSC_USE) */ + +#if defined(USB_CFG_HVND_USE) +extern void usb_hvnd_registration(usb_utr_t * ptr); +extern void usb_hvnd_read_complete(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +extern void usb_hvnd_write_complete(usb_utr_t * ptr, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_HVND_USE) */ + +#if defined(USB_CFG_HAUD_USE) +extern void usb_haud_read_complete(usb_utr_t * mess, uint16_t devadr, uint16_t data2); +extern void usb_haud_write_complete(usb_utr_t * mess, uint16_t devadr, uint16_t data2); +extern void usb_haud_registration(usb_utr_t * ptr); +extern void usb_haud_task(usb_vp_int_t stacd); +extern void usb_haud_driver_start(usb_utr_t * ptr); +extern void usb_haud_audio20_clock_source_descriptor_get(usb_utr_t * ptr, + uint8_t terminal_link, + uint8_t ep_direction, + uint8_t ** csd); + +#endif /* defined(USB_CFG_HAUD_USE) */ + +extern uint16_t g_usb_pstd_eptbl[]; + +#if defined(USB_CFG_PMSC_USE) +extern void usb_pmsc_receive_cbw(usb_utr_t * p_utr); +extern void usb_pmsc_get_max_lun(uint16_t value, uint16_t index, uint16_t length, usb_utr_t * p_utr); +extern void usb_pmsc_mass_strage_reset(uint16_t value, uint16_t index, uint16_t length, usb_utr_t * p_utr); + +#endif + +void usb_hstd_device_information(usb_utr_t * ptr, uint16_t devaddr, uint16_t * tbl); +void usb_pstd_device_information(usb_utr_t * ptr, uint16_t * tbl); +usb_er_t usb_pstd_set_stall_clr_feature(usb_utr_t * ptr, usb_cb_t complete, uint16_t pipe); + +#if USB_CFG_BC == USB_CFG_ENABLE + +/* BC State change function */ +void usb_hstd_bc_err(usb_utr_t * ptr); +void usb_hstd_bc_init_vb(usb_utr_t * ptr); +void usb_hstd_bc_det_at(usb_utr_t * ptr); +void usb_hstd_bc_cdp_dt(usb_utr_t * ptr); +void usb_hstd_bc_sdp_dt(usb_utr_t * ptr); + +/* BC State entry/exit function */ +void usb_hstd_bc_det_entry(usb_utr_t * ptr); +void usb_hstd_bc_det_exit(usb_utr_t * ptr); +void usb_hstd_bc_cdp_entry(usb_utr_t * ptr); +void usb_hstd_bc_cdp_exit(usb_utr_t * ptr); +void usb_hstd_bc_sdp_entry(usb_utr_t * ptr); +void usb_hstd_bc_sdp_exit(usb_utr_t * ptr); +void usb_hstd_bc_dcp_entry(usb_utr_t * ptr); + +void usb_hstd_pddetint_process(usb_utr_t * ptr); +void usb_pstd_bc_detect_process(usb_utr_t * p_utr); + +#endif /* USB_CFG_BC == USB_CFG_ENABLE */ + +#if (BSP_CFG_RTOS != 0) + +/* r_usb_cstd_rtos.c */ +void usb_cstd_pipe_msg_clear(usb_utr_t * ptr, uint16_t pipe_no); +void usb_cstd_pipe0_msg_clear(usb_utr_t * ptr, uint16_t dev_addr); +void usb_cstd_pipe_msg_re_forward(uint16_t ip_no, uint16_t pipe_no); +void usb_cstd_pipe0_msg_re_forward(uint16_t ip_no); +void usb_cstd_pipe_msg_forward(usb_utr_t * ptr, uint16_t pipe_no); +void usb_cstd_pipe0_msg_forward(usb_utr_t * ptr, uint16_t dev_addr); + +#endif /* #if (BSP_CFG_RTOS != 0) */ + +#if (BSP_CFG_RTOS == 1) +void usb_cstd_usbx_callback(usb_event_info_t * p_api_event, usb_hdl_t cur_task, usb_onoff_t usb_state); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void usb_host_usbx_registration(usb_utr_t * p_utr, usb_class_t type); +void usb_host_usbx_attach_init(uint8_t module_number); + + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +uint32_t usb_peri_usbx_initialize_complete(void); + + #endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + + #if defined(USB_CFG_OTG_USE) +void usb_otg_irq_callback(external_irq_callback_args_t * p_args); +void usb2_otg_irq_callback(external_irq_callback_args_t * p_args); +VOID usb_otg_detach_timer(ULONG args); +VOID usb2_otg_detach_timer(ULONG args); +VOID usb_otg_chattering_timer(ULONG args); +VOID usb_otg_hnp_timer(ULONG args); + + #endif /* defined(USB_CFG_OTG_USE) */ + +#endif /* #if (BSP_CFG_RTOS == 1) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_EXTERN_H */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h new file mode 100644 index 0000000000..7338ae1362 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h @@ -0,0 +1,257 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef R_USB_TYPEDEF_H +#define R_USB_TYPEDEF_H + +/****************************************************************************** + * Includes + ******************************************************************************/ +#include +#include "r_usb_basic_api.h" +#include "r_usb_cstd_rtos.h" +#include "r_usb_basic.h" +#include "r_usb_basic_define.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ +typedef void * VP; /* Pointer to variable */ +typedef long ER; /* Error code */ +typedef short ID; /* Object ID (xxxid) */ +typedef long TMO; /* Time out */ +typedef long VP_INT; /* Integer data */ + +/*----------- msghead -----------*/ +typedef struct +{ + VP msghead; /* Message header */ +} t_msg_t; + +typedef t_msg_t usb_msg_t; +typedef ER usb_er_t; +typedef ID usb_id_t; +typedef TMO usb_tm_t; +typedef VP usb_mh_t; +typedef VP_INT usb_vp_int_t; + +#if defined(USB_HIGH_SPEED_MODULE) +typedef volatile R_USB_HS0_Type * usb_regadr1_t; // @@ +#else /* defined(USB_HIGH_SPEED_MODULE) */ +typedef volatile R_USB_FS0_Type * usb_regadr1_t; +#endif /* defined(USB_HIGH_SPEED_MODULE) */ + +typedef volatile R_USB_FS0_Type * usb_regadr_t; + +typedef struct usb_utr usb_utr_t; +typedef void (* usb_cb_t)(struct usb_utr *, uint16_t, uint16_t); + +typedef struct usb_utr +{ + usb_mh_t msghead; /* Message header (for SH-solution) */ + usb_cb_t complete; /* Call Back Function Info */ + void const * p_tranadr; /* Transfer data Start address */ +#if (BSP_CFG_RTOS == 1) /* Azure RTOS */ + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + void const * p_tranadr_hold; + #endif /* #if (USB_CFG_DMA == USB_CFG_ENABLE) */ +#endif /* (BSP_CFG_RTOS == 1) */ + uint32_t read_req_len; /* Read Request Length */ + uint32_t tranlen; /* Transfer data length */ + uint16_t * p_setup; /* Setup packet(for control only) */ + void * p_usr_data; +#if (BSP_CFG_RTOS != 0) + usb_hdl_t cur_task_hdl; /* Task Handle */ +#endif /* #if (BSP_CFG_RTOS != 0) */ + uint16_t msginfo; /* Message Info for F/W */ + uint16_t keyword; /* Root port / Device address / Pipe number */ + uint8_t ip; /* USB module number(0 or 1) */ + uint16_t result; /* Result */ + uint16_t status; /* Status */ + uint16_t pipectr; /* Pipe control register */ +#if (BSP_CFG_RTOS != 0) + uint16_t setup_data[5]; /* Save setup for Request */ +#endif /* #if (BSP_CFG_RTOS != 0) */ + uint8_t errcnt; /* Error count */ + uint8_t segment; /* Last flag */ + const transfer_instance_t * p_transfer_tx; ///< Send context + const transfer_instance_t * p_transfer_rx; ///< Receive context + union + { + usb_regadr_t ipp; /* USB module startAddress(USB0/USB1)*/ +#if USB_NUM_USBIP == 2 + usb_regadr1_t ipp1; /* USB module start address(USBA) */ +#endif /* USB_NUM_USBIP == 2 */ + }; +#if (BSP_CFG_RTOS == 1) /* Azure RTOS */ + #if (defined(USB_CFG_PPRN_USE) || defined(USB_CFG_PCDC_USE)) + uint32_t timeout; + uint8_t is_timeout; + #endif /* define(USB_CFG_PPRN_USE) || defined(USB_CFG_PCDC_USE) */ +#endif /* (BSP_CFG_RTOS == 1) */ +} usb_message_t; + +typedef struct st_usb usb_stnbyint_t; + +typedef void (* usb_cb_check_t)(struct usb_utr *, uint16_t **); + +/* Class request processing function type. */ +typedef void (* usb_cb_trn_t)(usb_setup_t * preq, uint16_t ctsq, usb_utr_t * p_utr); + +typedef struct +{ + uint16_t rootport; /* Root port */ + uint16_t devaddr; /* Device address */ + uint16_t devstate; /* Device state */ + uint16_t ifclass; /* Interface Class */ + uint16_t * p_tpl; /* Target peripheral list(Vendor ID, Product ID) */ + usb_cb_t classinit; /* Driver init */ + usb_cb_check_t classcheck; /* Driver check */ + usb_cb_t devconfig; /* Device configured */ + usb_cb_t devdetach; /* Device detach */ + usb_cb_t devsuspend; /* Device suspend */ + usb_cb_t devresume; /* Device resume */ +} usb_hcdreg_t; + +typedef struct +{ + uint8_t * p_devicetbl; /* Device descriptor Table address */ + uint8_t * p_qualitbl; /* Qualifier descriptor Table address */ + uint8_t * p_configtbl; /* Configuration descriptor Table address */ + uint8_t * p_othertbl; /* Other configuration descriptor Table address */ + uint8_t ** p_stringtbl; /* String descriptor Table address */ + usb_cb_t devdefault; /* Device default */ + usb_cb_t devconfig; /* Device configured */ + usb_cb_t devdetach; /* Device detach */ + usb_cb_t devsuspend; /* Device suspend */ + usb_cb_t devresume; /* Device resume */ + usb_cb_t interface; /* Interface changed */ + usb_cb_trn_t ctrltrans; /* Control Transfer */ + uint8_t num_string; /* Num entry String Descriptor */ +} usb_pcdreg_t; + +typedef struct usb_utr usb_hcdinfo_t; +typedef struct usb_utr usb_mgrinfo_t; +typedef struct usb_utr usb_pcdinfo_t; +typedef struct usb_utr usb_clsinfo_t; + +typedef struct +{ + uint8_t state; /* BC State */ + uint8_t pd_detect; /* PD Detect Flag */ +} usb_bc_status_t; + +typedef struct usb_ctrl_trans +{ + usb_setup_t setup; /* Request command */ + uint16_t address; /* Device address setting */ +} usb_ctrl_trans_t; + +#if (BSP_CFG_RTOS == 0) +typedef struct +{ + uint16_t type; + uint16_t status; + usb_cfg_t * p_cfg; +} usb_int_info_t; +#endif /*(BSP_CFG_RTOS == 0)*/ + +typedef struct +{ +#if (BSP_CFG_RTOS != 0) + uint16_t type; + uint16_t status; + uint16_t ip; + uint16_t fifo_type; +#else /* #if (BSP_CFG_RTOS != 0) */ + usb_int_info_t buf[USB_INT_BUFSIZE]; /* Interrupt Info */ + uint8_t wp; /* Write pointer */ + uint8_t rp; /* Read pointer */ +#endif /* #if (BSP_CFG_RTOS != 0) */ +} usb_int_t; + +typedef struct +{ + uint16_t ip; /* USB IP(USB_IP0/USB_IP1) */ + uint16_t fifo_type; /* Use FIFO type(USB_CUSE/USB_D0USE/USB_D1USE) */ + usb_cfg_t * p_cfg; +} usb_fifo_type_t; + +typedef struct +{ +#if (BSP_CFG_RTOS != 0) + uint16_t type; + uint16_t status; + uint16_t ip; + uint16_t fifo_type; +#else /* #if (BSP_CFG_RTOS != 0) */ + usb_fifo_type_t buf[USB_INT_BUFSIZE]; /* Complete DMA Info */ + uint8_t wp; /* Write pointer */ + uint8_t rp; /* Read pointer */ +#endif /* #if (BSP_CFG_RTOS != 0) */ +} usb_dma_int_t; + +typedef struct usb_event +{ +#if (BSP_CFG_RTOS != 0) + usb_instance_ctrl_t ctrl; /* Control Information */ + uint8_t code; +#else /* #if (BSP_CFG_RTOS != 0) */ + uint8_t write_pointer; /* Write pointer */ + uint8_t read_pointer; /* Read pointer */ + usb_status_t code[USB_EVENT_MAX]; /* Event code */ + usb_instance_ctrl_t ctrl[USB_EVENT_MAX]; /* Control Information */ +#endif /* #if (BSP_CFG_RTOS != 0) */ +} usb_event_t; + +typedef struct usb_pipe_table +{ + uint16_t use_flag; + uint16_t pipe_cfg; + uint16_t pipe_buf; + uint16_t pipe_maxp; + uint16_t pipe_peri; +} usb_pipe_table_t; + +typedef struct usb_pipe_reg +{ + uint16_t pipe_cfg; + uint16_t pipe_buf; + uint16_t pipe_maxp; + uint16_t pipe_peri; +} usb_pipe_table_reg_t; + +typedef enum e_usb_class_internal +{ + USB_CLASS_INTERNAL_PCDC = 0, ///< PCDC Class 0 + USB_CLASS_INTERNAL_PCDCC, ///< PCDCC Class 1 + USB_CLASS_INTERNAL_PCDC2, ///< PCDC2 Class 2 + USB_CLASS_INTERNAL_PCDCC2, ///< PCDCC2 Class 3 + USB_CLASS_INTERNAL_PHID, ///< PHID Class 4 + USB_CLASS_INTERNAL_PHID2, ///< PHID2 Class 5 + USB_CLASS_INTERNAL_PAUD, ///< PAUD Class 6 + USB_CLASS_INTERNAL_PPRN, ///< PPRN Class 7 + USB_CLASS_INTERNAL_DFU, ///< DFU Class 8 + USB_CLASS_INTERNAL_PVND, ///< PVND Class 9 + USB_CLASS_INTERNAL_HCDC, ///< HCDC Class 10 + USB_CLASS_INTERNAL_HCDCC, ///< HCDCC Class 11 + USB_CLASS_INTERNAL_HHID, ///< HHID Class 12 + USB_CLASS_INTERNAL_HVND, ///< HVND Class 13 + USB_CLASS_INTERNAL_HMSC, ///< HMSC Class 14 + USB_CLASS_INTERNAL_PMSC, ///< PMSC Class 15 + USB_CLASS_INTERNAL_HPRN, ///< HPRN Class 16 + USB_CLASS_INTERNAL_HUVC, ///< HUVC Class 17 + USB_CLASS_INTERNAL_HAUD, ///< HAUD Class 18 + USB_CLASS_INTERNAL_REQUEST, ///< USB Class Request 19 + USB_CLASS_INTERNAL_END, ///< USB Class 20 +} usb_class_internal_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_TYPEDEF_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c new file mode 100644 index 0000000000..55284c97aa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c @@ -0,0 +1,788 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if defined(USB_CFG_OTG_USE) + #if (defined(USB_CFG_HCDC_USE) | defined(USB_CFG_PCDC_USE)) + #include "r_usb_otg_cdc_cfg.h" + #include "r_usb_pcdc_api.h" + #endif /* (defined(USB_CFG_HCDC_USE) | defined(USB_CFG_PCDC_USE)) */ +#else /* defined(USB_CFG_OTG_USE) */ + #if defined(USB_CFG_HCDC_USE) + #include "r_usb_hcdc_cfg.h" + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_PCDC_USE) + #include "r_usb_pcdc_api.h" + #include "r_usb_pcdc_cfg.h" + #endif /* defined(USB_CFG_PCDC_USE) */ +#endif /* defined(USB_CFG_OTG_USE) */ + +#if defined(USB_CFG_PPRN_USE) + #include "r_usb_pprn_api.h" + #if (BSP_CFG_RTOS != 1) + #include "r_usb_pprn_cfg.h" + #endif /* (BSP_CFG_RTOS != 1) */ +#endif /* defined(USB_CFG_PPRN_USE) */ + +#if defined(USB_CFG_HPRN_USE) + #include "r_usb_hprn_cfg.h" +#endif /* defined(USB_CFG_HPRN_USE) */ + +#if defined(USB_CFG_PMSC_USE) + #include "r_usb_pmsc_api.h" +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if defined(USB_CFG_PHID_USE) && !defined(USB_CFG_OTG_USE) + #include "r_usb_phid_api.h" +#endif /* defined(USB_CFG_PHID_USE) */ + +#if defined(USB_CFG_HHID_USE) && defined(USB_CFG_OTG_USE) + #include "r_usb_otg_hid_cfg.h" +#else + #if defined(USB_CFG_HHID_USE) + #include "r_usb_hhid_cfg.h" + #endif /* defined(USB_CFG_HHID_USE) */ +#endif /* defined(USB_CFG_HHID_USE) && defined(USB_CFG_OTG_USE) */ +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HMSC_USE) + #include "r_usb_hmsc.h" + #endif /* defined(USB_CFG_HMSC_USE) */ +#else /* #if (BSP_CFG_RTOS != 1) */ + #if defined(USB_CFG_PAUD_USE) + #include "r_usb_paud_cfg.h" + #endif /* defined(USB_CFG_PAUD_USE) */ + #if defined(USB_CFG_HUVC_USE) + #include "r_usb_huvc_cfg.h" + #endif /* defined(USB_CFG_HUVC_USE) */ + #if defined(USB_CFG_HAUD_USE) + #include "r_usb_haud_cfg.h" + #endif /* defined(USB_CFG_HAUD_USE) */ + +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "../hw/inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/* Pipe number of USB Host transfer.(Read pipe/Write pipe) */ +uint8_t g_usb_pipe_host[USB_MAX_PIPE_POS_HOST]; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/* Pipe number of USB Peri transfer.(Read pipe/Write pipe) */ +uint8_t g_usb_pipe_peri[USB_MAX_PIPE_POS_PERI]; +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/* USB data transfer */ +/* PIPEn Buffer counter */ +uint32_t g_usb_pstd_data_cnt[USB_MAX_PIPE_NO + 1U]; + +/* PIPEn Buffer pointer(8bit) */ +uint8_t * gp_usb_pstd_data[USB_MAX_PIPE_NO + 1U]; + +/* Message pipe */ +usb_utr_t * g_p_usb_pstd_pipe[USB_MAX_PIPE_NO + 1U]; + +#endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + +/* Callback function of USB Read/USB Write */ +void (* g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) = +{ + /* PCDC, PCDCC */ +#if defined(USB_CFG_PCDC_USE) + #if (BSP_CFG_RTOS == 1) + USB_NULL, USB_NULL, /* USB_PCDC (0) */ + USB_NULL, USB_NULL, /* USB_PCDCC (1) */ + USB_NULL, USB_NULL, /* USB_PCDC2 (2) */ + USB_NULL, USB_NULL, /* USB_PCDCC2 (3) */ + #else /* #if (BSP_CFG_RTOS == 1) */ + usb_pcdc_read_complete, usb_pcdc_write_complete, /* USB_PCDC (0) */ + USB_NULL, usb_pcdc_write_complete, /* USB_PCDCC (1) */ + usb_pcdc_read_complete, usb_pcdc_write_complete, /* USB_PCDC2 (2) */ + USB_NULL, usb_pcdc_write_complete, /* USB_PCDCC2 (3) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ +#else + USB_NULL, USB_NULL, /* USB_PCDC (0) */ + USB_NULL, USB_NULL, /* USB_PCDCC (1) */ + USB_NULL, USB_NULL, /* USB_PCDC2 (2) */ + USB_NULL, USB_NULL, /* USB_PCDCC2 (3) */ +#endif + + /* PHID */ +#if defined(USB_CFG_PHID_USE) + #if (BSP_CFG_RTOS != 1) + usb_phid_read_complete, usb_phid_write_complete, /* USB_PHID (4) */ + usb_phid_read_complete, usb_phid_write_complete, /* USB_PHID2 (5) */ + #else /* #if (BSP_CFG_RTOS == 1) */ + USB_NULL, USB_NULL, /* USB_PHID (4) */ + USB_NULL, USB_NULL, /* USB_PHID (5) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ +#else + USB_NULL, USB_NULL, /* USB_PHID (4) */ + USB_NULL, USB_NULL, /* USB_PHID (5) */ +#endif + + /* PAUD */ +#if defined(USB_CFG_PAUD_USE) + #if (BSP_CFG_RTOS != 1) + usb_paud_read_complete, usb_paud_write_complete, /* USB_PAUD (6) */ + #else /* #if (BSP_CFG_RTOS != 1) */ + USB_NULL, USB_NULL, /* USB_PAUD (6) */ + #endif /* #if (BSP_CFG_RTOS != 1) */ +#else + USB_NULL, USB_NULL, /* USB_PAUD (6) */ +#endif + + /* PPRN */ +#if defined(USB_CFG_PPRN_USE) + #if (BSP_CFG_RTOS != 1) + usb_pprn_read_complete, usb_pprn_write_complete, /* USB_PPRN (7) */ + #else /* BSP_CFG_RTOS != 1 */ + USB_NULL, USB_NULL, /* USB_PPRN (7) */ + #endif /* BSP_CFG_RTOS != 1 */ +#else /* defined(USB_CFG_PPRN_USE) */ + USB_NULL, USB_NULL, /* USB_PPRN (7) */ +#endif /* defined(USB_CFG_PPRN_USE) */ + + /* DFU */ + USB_NULL, USB_NULL, /* USB_DFU (8) */ + + /* PVND */ + USB_NULL, USB_NULL, /* USB_PVND (9) */ + + /* HCDC, HCDCC */ +#if defined(USB_CFG_HCDC_USE) + #if (BSP_CFG_RTOS == 1) + USB_NULL, USB_NULL, /* USB_HCDC (10) */ + USB_NULL, USB_NULL, /* USB_HCDCC (11) */ + #else /* #if (BSP_CFG_RTOS == 1) */ + usb_hcdc_read_complete, usb_hcdc_write_complete, /* USB_HCDC (10) */ + usb_hcdc_read_complete, USB_NULL, /* USB_HCDCC (11) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ +#else + USB_NULL, USB_NULL, /* USB_HCDC (10) */ + USB_NULL, USB_NULL, /* USB_HCDCC (11) */ +#endif + + /* HHID */ +#if defined(USB_CFG_HHID_USE) + #if (BSP_CFG_RTOS == 1) + USB_NULL, USB_NULL, /* USB_HHID (12) */ + #else /* #if (BSP_CFG_RTOS == 1) */ + usb_hhid_read_complete, usb_hhid_write_complete, /* USB_HHID (12) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ +#else + USB_NULL, USB_NULL, /* USB_HHID (12) */ +#endif + + /* HVND */ +#if defined(USB_CFG_HVND_USE) + usb_hvnd_read_complete, usb_hvnd_write_complete, /* USB_HVND (13) */ +#else + USB_NULL, USB_NULL, /* USB_HVND (13) */ +#endif + + /* HMSC */ + USB_NULL, USB_NULL, /* USB_HMSC (14) */ + + /* PMSC */ + USB_NULL, USB_NULL, /* USB_PMSC (15) */ + + /* HPRN */ +#if defined(USB_CFG_HPRN_USE) + #if (BSP_CFG_RTOS == 1) + USB_NULL, USB_NULL, /* USB_HPRN (16) */ + #else /* #if (BSP_CFG_RTOS == 1) */ + usb_hprn_read_complete, usb_hprn_write_complete, /* USB_HPRN (16) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ +#else + USB_NULL, USB_NULL, /* USB_HPRN (16) */ +#endif + + /* HUVC */ + + USB_NULL, USB_NULL, /* USB_HUVC (17) */ + + /* HAUD */ +#if defined(USB_CFG_HAUD_USE) + #if (BSP_CFG_RTOS == 1) + USB_NULL, USB_NULL, /* USB_HAUD (18) */ + #else /* #if (BSP_CFG_RTOS == 1) */ + usb_haud_read_complete, usb_haud_write_complete, /* USB_HAUD (18) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ +#else + USB_NULL, USB_NULL, /* USB_HAUD (18) */ +#endif +}; /* const void (g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) */ + +#if defined(USB_CFG_PCDC_USE) + +/* Abstract Control Model Notification - SerialState */ +uint8_t g_usb_pcdc_serialstate_table[USB_PCDC_SETUP_TBL_BSIZE] = +{ + USB_DEV_TO_HOST | USB_CLASS | USB_INTERFACE, /* bmRequestType */ + USB_PCDC_SERIAL_STATE, /* bNotification:SERIAL_STATE */ + 0x00, 0x00, /* wValue:Zero */ + 0x00, 0x00, /* wIndex:Interface */ + 0x02, 0x00, /* wLength:2 */ + 0x00, 0x00, /* Data:UART State bitmap */ +}; + +#endif /* defined(USB_CFG_PCDC_USE) */ + +usb_pipe_table_t g_usb_pipe_table[USB_NUM_USBIP][USB_MAXPIPE_NUM + 1]; +uint16_t g_usb_cstd_bemp_skip[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; + +#if USB_DEBUG_ON == 2 + +/* Debug Print Buffer */ +uint8_t g_usb_print_buffer[USB_PRINT_BUF_SIZE]; +uint8_t g_usb_qe_error_string_length; +#endif /* USB_DEBUG_ON == 2 */ + +/****************************************************************************** + * Renesas Abstracted common data I/O functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_debug_hook + * Description : Debug hook + * Arguments : uint16_t error_code : error code + * Return value : none + ******************************************************************************/ +void usb_cstd_debug_hook (uint16_t error_code) +{ + FSP_PARAMETER_NOT_USED(error_code); + + /* WAIT_LOOP */ + + while (1) + { + /* Non */ + } +} /* End of function usb_cstd_debug_hook() */ + +#if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_ctrl_read + * Description : Receive process for Control transfer + * Arguments : usb_instance_ctrl_t *p_ctrl: Control structure for USB API. + * : uint8_t *buf : transfer data address + * : uint32_t size : transfer length + * Return value : usb_er_t : USB_SUCCESS(USB_OK) / USB_ERROR. + ******************************************************************************/ +usb_er_t usb_ctrl_read (usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size) +{ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_er_t err; + usb_utr_t * p_tran_data; + #if (BSP_CFG_RTOS != 0) + usb_utr_t tran_data_host; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data_host; + #else /* #if (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_hdata[p_ctrl->module_number][USB_PIPE0]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + p_tran_data->read_req_len = size; /* Save Read Request Length */ + p_tran_data->keyword = USB_PIPE0; /* Pipe No */ + p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + + /* Callback function */ + p_tran_data->complete = usb_class_request_complete; + g_usb_ctrl_request[p_ctrl->module_number][p_ctrl->device_address].address = p_ctrl->device_address; + g_usb_ctrl_request[p_ctrl->module_number][p_ctrl->device_address].setup = p_ctrl->setup; + + /* Setup message address set */ + p_tran_data->p_setup = + (uint16_t *) &g_usb_ctrl_request[p_ctrl->module_number][p_ctrl->device_address]; + p_tran_data->segment = USB_TRAN_END; + p_tran_data->ip = p_ctrl->module_number; + p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_ctrl->module_number); + err = usb_hstd_transfer_start(p_tran_data); + + return err; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_utr_t tran_data_peri; + + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + if (USB_ON == g_usb_pstd_pipe0_request) + { + return USB_QOVR; + } + + tran_data_peri.ip = p_ctrl->module_number; + g_usb_pstd_std_request = USB_YES; + usb_pstd_ctrl_write(size, buf, &tran_data_peri); + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + + return USB_OK; +} /* End of function usb_ctrl_read() */ + +/****************************************************************************** + * Function Name : usb_ctrl_write + * Description : Send process for Control transfer + * Arguments : usb_instance_ctrl_t *p_ctrl: Control structure for USB API. + * : uint8_t *buf : transfer data address + * : uint32_t size : transfer length + * Return value : usb_er_t : USB_SUCCESS(USB_OK) / USB_ERROR. + ******************************************************************************/ +usb_er_t usb_ctrl_write (usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size) +{ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_er_t err; + usb_utr_t * p_tran_data; + #if (BSP_CFG_RTOS != 0) + usb_utr_t tran_data_host; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data_host; + #else /* #if (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_hdata[p_ctrl->module_number][USB_PIPE0]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + p_tran_data->read_req_len = size; /* Save Read Request Length */ + + p_tran_data->keyword = USB_PIPE0; /* Pipe No */ + p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + + /* Callback function */ + p_tran_data->complete = usb_class_request_complete; + g_usb_ctrl_request[p_ctrl->module_number][p_ctrl->device_address].address = p_ctrl->device_address; + g_usb_ctrl_request[p_ctrl->module_number][p_ctrl->device_address].setup = p_ctrl->setup; + + /* Setup message address set */ + p_tran_data->p_setup = + (uint16_t *) &g_usb_ctrl_request[p_ctrl->module_number][p_ctrl->device_address]; + p_tran_data->segment = USB_TRAN_END; + p_tran_data->ip = p_ctrl->module_number; + p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_ctrl->module_number); + err = usb_hstd_transfer_start(p_tran_data); + + return err; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_instance_ctrl_t ctrl; + usb_utr_t tran_data_peri; + + tran_data_peri.ip = p_ctrl->module_number; + + if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) + { + if ((USB_NULL == buf) && (USB_NULL == size)) + { + if (USB_SETUP_STATUS_ACK == p_ctrl->status) + { + usb_cstd_set_buf(&tran_data_peri, (uint16_t) USB_PIPE0); /* Set BUF */ + } + else /* USB_STALL */ + { + usb_pstd_set_stall_pipe0(&tran_data_peri); + } + + ctrl.setup = p_ctrl->setup; /* Save setup data. */ + ctrl.module_number = p_ctrl->module_number; + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + #if (BSP_CFG_RTOS == 1) + ctrl.p_data = (void *) tx_thread_identify(); + #elif (BSP_CFG_RTOS == 2) + ctrl.p_data = (void *) xTaskGetCurrentTaskHandle(); + #endif /* #if (BSP_CFG_RTOS == 1) */ + usb_set_event(USB_STATUS_REQUEST_COMPLETE, &ctrl); + } + else + { + if (USB_ON == g_usb_pstd_pipe0_request) + { + return USB_QOVR; + } + + g_usb_pstd_std_request = USB_YES; + usb_pstd_ctrl_read(size, buf, &tran_data_peri); + } + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + + return USB_OK; +} /* End of function usb_ctrl_write() */ + +/****************************************************************************** + * Function Name : usb_ctrl_stop + * Description : Stop of USB Control transfer. + * Arguments : usb_instance_ctrl_t *p_ctrl: Control structure for USB API. + * Return value : usb_er_t : USB_OK / USB_ERROR. + ******************************************************************************/ +usb_er_t usb_ctrl_stop (usb_instance_ctrl_t * p_ctrl) +{ + usb_er_t err = USB_OK; + usb_utr_t utr; + + if (USB_CLASS_INTERNAL_PVND < (usb_class_internal_t) (p_ctrl->type)) + { + /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ip = p_ctrl->module_number; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + err = usb_hstd_transfer_end(&utr, USB_PIPE0, (uint16_t) USB_DATA_STOP); + #endif + } + else + { + /* Peripheral only */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + utr.ip = p_ctrl->module_number; + err = usb_pstd_transfer_end(&utr, USB_PIPE0); + #endif + } + + return err; +} /* End of function usb_ctrl_stop() */ + +#endif /* #if (USB_UT_MODE == 0) */ + +/****************************************************************************** + * Function Name : usb_data_read + * Description : USB data read processing + * Arguments : usb_instance_ctrl_t *p_ctrl: Control structure for USB API. + * : uint8_t *buf : Transfer data address + * : uint32_t size : Transfer length + * Return value : usb_er_t : USB_OK / USB_ERROR. + ******************************************************************************/ +usb_er_t usb_data_read (usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size) +{ + uint8_t pipe; + usb_er_t err = USB_OK; + usb_utr_t * p_tran_data; +#if (BSP_CFG_RTOS != 0) + usb_utr_t tran_data; +#endif /* #if (BSP_CFG_RTOS != 0) */ + + pipe = usb_get_usepipe(p_ctrl, USB_TRANSFER_READ); + + if (USB_CLASS_INTERNAL_PVND < (usb_class_internal_t) (p_ctrl->type)) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data; + #else /* #if (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_hdata[p_ctrl->module_number][pipe]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + p_tran_data->read_req_len = size; /* Save Read Request Length */ + + p_tran_data->keyword = pipe; /* Pipe No */ + p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + p_tran_data->complete = g_usb_callback[p_ctrl->type * 2]; /* Callback function */ + p_tran_data->segment = USB_TRAN_END; + p_tran_data->ip = p_ctrl->module_number; + p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_ctrl->module_number); + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + err = usb_hstd_transfer_start(p_tran_data); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data; + #else /* #if (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_pdata[pipe]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + p_tran_data->read_req_len = size; /* Save Read Request Length */ + + p_tran_data->ip = p_ctrl->module_number; /* USB Module Number */ + p_tran_data->keyword = pipe; /* Pipe No */ + p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + p_tran_data->complete = (usb_cb_t) g_usb_callback[p_ctrl->type * 2]; /* Callback function */ + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + err = usb_pstd_transfer_start(p_tran_data); +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + + return err; +} /* End of function usb_data_read() */ + +/****************************************************************************** + * Function Name : usb_data_write + * Description : USB data write processing + * Arguments : usb_instance_ctrl_t *p_ctrl: Control structure for USB API. + * : uint8_t *buf : Transfer data address + * : uint32_t size : Transfer length + * Return value : usb_er_t : USB_OK / USB_ERROR. + ******************************************************************************/ +usb_er_t usb_data_write (usb_instance_ctrl_t * p_ctrl, uint8_t const * const buf, uint32_t size) +{ + uint8_t pipe; + usb_er_t err = USB_OK; + usb_utr_t * p_tran_data; +#if (BSP_CFG_RTOS != 0) + usb_utr_t tran_data; +#endif /* #if (BSP_CFG_RTOS != 0) */ + + pipe = usb_get_usepipe(p_ctrl, USB_TRANSFER_WRITE); + + if (USB_CLASS_INTERNAL_PVND < (usb_class_internal_t) (p_ctrl->type)) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data; + #else /* #if (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_hdata[p_ctrl->module_number][pipe]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + p_tran_data->keyword = pipe; /* Pipe No */ + p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + p_tran_data->complete = g_usb_callback[(p_ctrl->type * 2) + 1]; /* Callback function */ + p_tran_data->segment = USB_TRAN_END; + p_tran_data->ip = p_ctrl->module_number; + p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_ctrl->module_number); + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + err = usb_hstd_transfer_start(p_tran_data); +#endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (BSP_CFG_RTOS != 0) + p_tran_data = &tran_data; + #else /* #if (BSP_CFG_RTOS != 0) */ + p_tran_data = &g_usb_pdata[pipe]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + #if defined(USB_CFG_PCDC_USE) + if (g_usb_pcdc_int_in_pipe[p_ctrl->module_number] != pipe) + { + p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + } + else + { + g_usb_pcdc_serialstate_table[8] = buf[0]; + g_usb_pcdc_serialstate_table[9] = buf[1]; + p_tran_data->p_tranadr = g_usb_pcdc_serialstate_table; /* Data address */ + p_tran_data->tranlen = 10; /* Data Size */ + } + #else /* defined(USB_CFG_PCDC_USE) */ + p_tran_data->p_tranadr = buf; /* Data address */ + p_tran_data->tranlen = size; /* Data Size */ + #endif /* defined(USB_CFG_PCDC_USE) */ + p_tran_data->ip = p_ctrl->module_number; /* USB Module Number */ + p_tran_data->keyword = pipe; /* Pipe No */ + p_tran_data->complete = (usb_cb_t) g_usb_callback[(p_ctrl->type * 2) + 1]; /* Callback function */ + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (0 != p_ctrl->p_transfer_tx) + { + p_tran_data->p_transfer_tx = p_ctrl->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != p_ctrl->p_transfer_rx) + { + p_tran_data->p_transfer_rx = p_ctrl->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + err = usb_pstd_transfer_start(p_tran_data); +#endif /* ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + } + + return err; +} /* End of function usb_data_write() */ + +#if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_data_stop + * Description : USB data transfer stop processing + * Arguments : usb_instance_ctrl_t *p_ctrl: control structure for USB API. + * : usb_transfer_t type : USB_TRANSFER_READ(0)/USB_TRANSFER_WRITE(1) + * Return value : usb_er_t : USB_OK / USB_ERROR. + ******************************************************************************/ +usb_er_t usb_data_stop (usb_instance_ctrl_t * p_ctrl, usb_transfer_t type) +{ + uint8_t pipe; + usb_er_t err = USB_ERROR; + usb_utr_t utr; + + pipe = usb_get_usepipe(p_ctrl, type); + + if (USB_NULL == pipe) + { + USB_PRINTF1("*** usb_data_stop PipeNo ERROR %d\n", pipe); + + return USB_ERROR; + } + + if (USB_CLASS_INTERNAL_PVND < (usb_class_internal_t) (p_ctrl->type)) + { + /* Host only */ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ip = p_ctrl->module_number; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + err = usb_hstd_transfer_end(&utr, pipe, (uint16_t) USB_DATA_STOP); + #endif + } + else + { + /* Peripheral only */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + utr.ip = p_ctrl->module_number; + err = usb_pstd_transfer_end(&utr, pipe); + #endif + } + + return err; +} /* End of function usb_data_stop() */ + +#endif /* #if (USB_UT_MODE == 0) */ + +/****************************************************************************** + * Function Name : usb_get_usepipe + * Description : Get pipe number for USB Read/USB Write + * Arguments : usb_instance_ctrl_t *p_ctrl: Control structure for USB API. + * : usb_transfer_t dir : USB_TRANSFER_READ(0)/USB_TRANSFER_WRITE(1) + * Return value : Bitmap of Use pipe + ******************************************************************************/ +uint8_t usb_get_usepipe (usb_instance_ctrl_t * p_ctrl, usb_transfer_t dir) +{ + uint8_t pipe = USB_NULL; + uint8_t idx; + + if (USB_CLASS_INTERNAL_PVND < (usb_class_internal_t) (p_ctrl->type)) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + + /* Host */ + idx = + (uint8_t) (((((usb_class_internal_t) p_ctrl->type - USB_CLASS_INTERNAL_HCDC) * 8) + + ((p_ctrl->device_address - 1) * 2)) + dir); + pipe = g_usb_pipe_host[idx]; +#endif + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + + /* Peripheral */ + idx = (uint8_t) ((p_ctrl->type * 2) + dir); + pipe = g_usb_pipe_peri[idx]; +#endif + } + + return pipe; +} /* End of function usb_get_usepipe() */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_clibusbip.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_clibusbip.c new file mode 100644 index 0000000000..ca6ec8abd2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_clibusbip.c @@ -0,0 +1,777 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "inc/r_usb_basic_define.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HCDC_USE) + #include "r_usb_hcdc_api.h" + #endif /* defined(USB_CFG_HCDC_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HHID_USE) + #include "r_usb_hhid_api.h" + #endif /* defined(USB_CFG_HHID_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HMSC_USE) + #include "r_usb_hmsc_api.h" + #endif /* defined(USB_CFG_HMSC_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if defined(USB_CFG_PCDC_USE) + #include "r_usb_pcdc_api.h" + +#endif /* defined(USB_CFG_PCDC_USE) */ + +#if defined(USB_CFG_PPRN_USE) + #include "r_usb_pprn_api.h" + +#endif /* defined(USB_CFG_PPRN_USE) */ + +#if defined(USB_CFG_PMSC_USE) + #include "r_usb_pmsc_api.h" + +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "../hw/inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +/****************************************************************************** + * Macro definitions + *****************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * usb_prv_ns_callback)(usb_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile usb_prv_ns_callback)(usb_callback_args_t * p_args); +#endif + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + +/****************************************************************************** + * Private global variables and functions + *****************************************************************************/ + +fsp_err_t usb_cstd_get_semaphore(usb_instance_ctrl_t * p_ctrl); +fsp_err_t usb_cstd_rel_semaphore(usb_instance_ctrl_t * p_ctrl); + +/****************************************************************************** + * Renesas Abstracted Driver API functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_nrdy_enable + * Description : Enable NRDY interrupt of the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : none + ******************************************************************************/ +void usb_cstd_nrdy_enable (usb_utr_t * ptr, uint16_t pipe) +{ + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Enable NRDY */ + hw_usb_set_nrdyenb(ptr, pipe); +} + +/****************************************************************************** + * End of function usb_cstd_nrdy_enable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_get_pid + * Description : Fetch specified pipe's PID. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint16_t PID-bit status + ******************************************************************************/ +uint16_t usb_cstd_get_pid (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t buf; + + if (USB_MAX_PIPE_NO < pipe) + { + return USB_NULL; /* Error */ + } + + /* PIPE control reg read */ + buf = hw_usb_read_pipectr(ptr, pipe); + + return (uint16_t) (buf & USB_PID); +} + +/****************************************************************************** + * End of function usb_cstd_get_pid + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_get_maxpacket_size + * Description : Fetch MaxPacketSize of the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint16_t MaxPacketSize + ******************************************************************************/ +uint16_t usb_cstd_get_maxpacket_size (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t size; + uint16_t buffer; + + if (USB_MAX_PIPE_NO < pipe) + { + return USB_NULL; /* Error */ + } + + if (USB_PIPE0 == pipe) + { + buffer = hw_usb_read_dcpmaxp(ptr); + } + else + { + /* Pipe select */ + hw_usb_write_pipesel(ptr, pipe); + buffer = hw_usb_read_pipemaxp(ptr); + } + + /* Max Packet Size */ + size = (uint16_t) (buffer & USB_MXPS); + + return size; +} + +/****************************************************************************** + * End of function usb_cstd_get_maxpacket_size + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_get_pipe_dir + * Description : Get PIPE DIR + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint16_t pipe direction. + ******************************************************************************/ +uint16_t usb_cstd_get_pipe_dir (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t buffer; + + if (USB_MAX_PIPE_NO < pipe) + { + return USB_NULL; /* Error */ + } + + /* Pipe select */ + hw_usb_write_pipesel(ptr, pipe); + + /* Read Pipe direction */ + buffer = hw_usb_read_pipecfg(ptr); + + return (uint16_t) (buffer & USB_DIRFIELD); +} + +/****************************************************************************** + * End of function usb_cstd_get_pipe_dir + ******************************************************************************/ + +#if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_cstd_get_pipe_type + * Description : Fetch and return PIPE TYPE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint16_t pipe type + ******************************************************************************/ +uint16_t usb_cstd_get_pipe_type (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t buffer; + + if (USB_MAX_PIPE_NO < pipe) + { + return USB_NULL; /* Error */ + } + + /* Pipe select */ + hw_usb_write_pipesel(ptr, pipe); + + /* Read Pipe direction */ + buffer = hw_usb_read_pipecfg(ptr); + + return (uint16_t) (buffer & USB_TYPFIELD); +} + +/****************************************************************************** + * End of function usb_cstd_get_pipe_type + ******************************************************************************/ +#endif /* #if (USB_UT_MODE == 0) */ + +/****************************************************************************** + * Function Name : usb_cstd_do_aclrm + * Description : Set the ACLRM-bit (Auto Buffer Clear Mode) of the specified + * : pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : none + ******************************************************************************/ +void usb_cstd_do_aclrm (usb_utr_t * ptr, uint16_t pipe) +{ + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Control ACLRM */ + hw_usb_set_aclrm(ptr, pipe); + hw_usb_clear_aclrm(ptr, pipe); +} + +/****************************************************************************** + * End of function usb_cstd_do_aclrm + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_set_buf + * Description : Set PID (packet ID) of the specified pipe to BUF. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : none + ******************************************************************************/ +void usb_cstd_set_buf (usb_utr_t * ptr, uint16_t pipe) +{ + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* PIPE control reg set */ + hw_usb_set_pid(ptr, pipe, USB_PID_BUF); +} + +/****************************************************************************** + * End of function usb_cstd_set_buf + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_clr_stall + * Description : Set up to NAK the specified pipe, and clear the STALL-bit set + * : to the PID of the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : none + * Note : PID is set to NAK. + ******************************************************************************/ +void usb_cstd_clr_stall (usb_utr_t * ptr, uint16_t pipe) +{ + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Set NAK */ + usb_cstd_set_nak(ptr, pipe); + + /* Clear STALL */ + hw_usb_clear_pid(ptr, pipe, USB_PID_STALL); +} + +/****************************************************************************** + * End of function usb_cstd_clr_stall + ******************************************************************************/ + +#if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_cstd_port_speed + * Description : Get USB-speed of the specified port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * :Return value : uint16_t : HSCONNECT, Hi-Speed + * : : FSCONNECT : Full-Speed + * : : LSCONNECT : Low-Speed + * : : NOCONNECT : not connect + ******************************************************************************/ +uint16_t usb_cstd_port_speed (usb_utr_t * ptr) +{ + uint16_t buf; + uint16_t conn_inf; + + buf = hw_usb_read_dvstctr(ptr); + + /* Reset handshake status get */ + buf = (uint16_t) (buf & USB_RHST); + + switch (buf) + { + /* Get port speed */ + case USB_HSMODE: + { + conn_inf = USB_HSCONNECT; + break; + } + + case USB_FSMODE: + { + conn_inf = USB_FSCONNECT; + break; + } + + case USB_LSMODE: + { + conn_inf = USB_LSCONNECT; + break; + } + + case USB_HSPROC: + { + conn_inf = USB_NOCONNECT; + break; + } + + default: + { + conn_inf = USB_NOCONNECT; + break; + } + } + + return conn_inf; +} + +/****************************************************************************** + * End of function usb_cstd_port_speed + ******************************************************************************/ +#endif /* #if (USB_UT_MODE == 0) */ + +#if (!(USB_UT_MODE == 1 && BSP_CFG_RTOS != 0)) + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_call_callback + * Description : Call callback functiont. + * Arguments : usb_instance_ctrl_t *p_ctrl : control structure for USB API. + * Return value : none + ******************************************************************************/ +static void usb_call_callback (usb_instance_ctrl_t * p_ctrl) +{ + usb_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + usb_callback_args_t * p_args = g_usb_apl_callback_memory[p_ctrl->module_number]; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + *p_args = *p_ctrl; + + #if BSP_TZ_SECURE_BUILD + + /* g_usb_apl_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(g_usb_apl_callback[p_ctrl->module_number])) + { + /* If p_callback is secure, then the project does not need to change security state. */ + (*g_usb_apl_callback[p_ctrl->module_number])(p_args); + } + else + { + /* If g_usb_apl_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + usb_prv_ns_callback p_callback = (usb_prv_ns_callback) (g_usb_apl_callback[p_ctrl->module_number]); + + p_callback(p_args); + } + + #else /* BSP_TZ_SECURE_BUILD */ + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + + // p_ctrl->p_callback(p_args); + (*g_usb_apl_callback[p_ctrl->module_number])(p_args); + #endif /* BSP_TZ_SECURE_BUILD */ +} + + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_set_event + * Description : Set event. + * Arguments : uint16_t event : event code. + * : usb_instance_ctrl_t *p_ctrl : control structure for USB API. + * Return value : none + ******************************************************************************/ +void usb_set_event (usb_status_t event, usb_instance_ctrl_t * p_ctrl) +{ + #if (BSP_CFG_RTOS != 0) + static uint16_t count = 0; + + p_ctrl->event = event; + g_usb_cstd_event[count] = *p_ctrl; + + switch (event) + { + case USB_STATUS_DEFAULT: + case USB_STATUS_CONFIGURED: + case USB_STATUS_BC: + case USB_STATUS_OVERCURRENT: + case USB_STATUS_NOT_SUPPORT: + case USB_STATUS_DETACH: + { + (*g_usb_apl_callback[p_ctrl->module_number])(&g_usb_cstd_event[count], (usb_hdl_t) USB_NULL, USB_OFF); + break; + } + + case USB_STATUS_REQUEST: + { + (*g_usb_apl_callback[p_ctrl->module_number])(&g_usb_cstd_event[count], (usb_hdl_t) USB_NULL, USB_OFF); + break; + } + + case USB_STATUS_SUSPEND: + case USB_STATUS_RESUME: + { + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + (*g_usb_apl_callback[p_ctrl->module_number])(&g_usb_cstd_event[count], + g_usb_hstd_sus_res_task_id[p_ctrl->module_number], + USB_OFF); + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + (*g_usb_apl_callback[p_ctrl->module_number])(&g_usb_cstd_event[count], (usb_hdl_t) USB_NULL, USB_OFF); + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + + break; + } + + case USB_STATUS_REQUEST_COMPLETE: + { + if (USB_MODE_HOST == g_usb_usbmode[p_ctrl->module_number]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + (*g_usb_apl_callback[p_ctrl->module_number])(&g_usb_cstd_event[count], (usb_hdl_t) p_ctrl->p_data, + USB_OFF); + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (0 == p_ctrl->setup.request_length) + { + /* Processing for USB request has the no data stage */ + (*g_usb_apl_callback[p_ctrl->module_number])(&g_usb_cstd_event[count], (usb_hdl_t) USB_NULL, + USB_OFF); + } + else + { + /* Processing for USB request has the data state */ + (*g_usb_apl_callback[p_ctrl->module_number])(&g_usb_cstd_event[count], (usb_hdl_t) p_ctrl->p_data, + USB_OFF); + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + + break; + } + + /* UNCRUSTIFY-OFF */ + case USB_STATUS_READ_COMPLETE: + case USB_STATUS_WRITE_COMPLETE: + #if defined(USB_CFG_HMSC_USE) + case USB_STATUS_MSC_CMD_COMPLETE: + #endif /* defined(USB_CFG_HMSC_USE) */ + (*g_usb_apl_callback[p_ctrl->module_number])(&g_usb_cstd_event[count], (usb_hdl_t) p_ctrl->p_data, USB_OFF); + break; + + default: + /* Do Nothing */ + break; + } + + count = (uint16_t) ((count + 1) % USB_EVENT_MAX); + /* UNCRUSTIFY-ON */ + #else /* #if (BSP_CFG_RTOS != 0) */ + g_usb_cstd_event.code[g_usb_cstd_event.write_pointer] = event; + g_usb_cstd_event.ctrl[g_usb_cstd_event.write_pointer] = *p_ctrl; + g_usb_cstd_event.write_pointer++; + if (g_usb_cstd_event.write_pointer >= USB_EVENT_MAX) + { + g_usb_cstd_event.write_pointer = 0; + } + + if (NULL != g_usb_apl_callback[p_ctrl->module_number]) + { + p_ctrl->event = event; + usb_call_callback(p_ctrl); + } + #endif /* #if (BSP_CFG_RTOS != 0) */ + } /* End of function usb_set_event() */ + +#endif /* #if(!(USB_UT_MODE == 1 && BSP_CFG_RTOS == 2)) */ + +#if (BSP_CFG_RTOS != 0) + +/***************************************************************************//** + * @brief Getting semaphore processing for the thread safe function + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_FAILED Semaphore acquisition failure. + ******************************************************************************/ +fsp_err_t usb_cstd_get_semaphore (usb_instance_ctrl_t * p_ctrl) +{ + #if (USB_CFG_MULTIPLE_TASKS == USB_CFG_ENABLE) + BaseType_t retval = pdFAIL; + uint8_t usbip_no = p_ctrl->module; + + retval = xSemaphoreTake(g_usb_semaphore_hdl[usbip_no], USB_TMO_VAL); + + if (pdPASS == retval) + { + g_usb_cur_task_hdl[usbip_no] = xTaskGetCurrentTaskHandle(); + g_usb_semaphore_holder[usbip_no] = p_ctrl->address; + + return FSP_SUCCESS; + } + + return FSP_ERR_USB_FAILED; + #else /* (USB_CFG_MULTIPLE_TASKS == USB_CFG_ENABLE) */ + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_SUCCESS; + #endif /* (USB_CFG_MULTIPLE_TASKS == USB_CFG_ENABLE) */ +} + +/****************************************************************************** + * End of function usb_cstd_get_semaphore + ******************************************************************************/ + +/***************************************************************************//** + * @brief Releasing semaphore processing for the thread safe function + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_FAILED Semaphore release failure. + ******************************************************************************/ +fsp_err_t usb_cstd_rel_semaphore (usb_instance_ctrl_t * p_ctrl) +{ + #if (USB_CFG_MULTIPLE_TASKS == USB_CFG_ENABLE) + BaseType_t retval = pdFAIL; + uint8_t usbip_no = p_ctrl->module; + + if ((UBaseType_t) 0 == uxSemaphoreGetCount(g_usb_semaphore_hdl[usbip_no])) + { + retval = xSemaphoreGive(g_usb_semaphore_hdl[usbip_no]); + } + + if (pdPASS == retval) + { + g_usb_cur_task_hdl[usbip_no] = (rtos_task_id_t) USB_NULL; + g_usb_semaphore_holder[usbip_no] = 0; + + return FSP_SUCCESS; + } + + return FSP_ERR_USB_FAILED; + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + + return FSP_SUCCESS; + #endif +} + +/****************************************************************************** + * End of function usb_cstd_rel_semaphore + ******************************************************************************/ +#endif /* #if (BSP_CFG_RTOS != 0) */ + +#if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_cstd_usb_task + * Description : USB driver main loop processing. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_cstd_usb_task (void) +{ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if defined(USB_CFG_HMSC_USE) + do + { + usb_cstd_scheduler(); /* Scheduler */ + if (USB_FLGSET == usb_cstd_check_schedule()) /* Check for any task processing requests flags. */ + { + /** Use only in non-OS. In RTOS, the kernel will schedule these tasks, no polling. **/ + usb_hstd_hcd_task((void *) 0); /* HCD Task */ + usb_hstd_mgr_task((void *) 0); /* MGR Task */ + #if USB_CFG_HUB == USB_CFG_ENABLE + usb_hhub_task((void *) 0); /* HUB Task */ + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + usb_class_task(); + } + } + /* WAIT_LOOP */ + while (USB_FALSE != g_drive_search_lock); + + #else /* defined(USB_CFG_HMSC_USE) */ + usb_cstd_scheduler(); /* Scheduler */ + + if (USB_FLGSET == usb_cstd_check_schedule()) /* Check for any task processing requests flags. */ + { + /** Use only in non-OS. In RTOS, the kernel will schedule these tasks, no polling. **/ + usb_hstd_hcd_task((void *) 0); /* HCD Task */ + usb_hstd_mgr_task((void *) 0); /* MGR Task */ + #if USB_CFG_HUB == USB_CFG_ENABLE + usb_hhub_task((void *) 0); /* HUB Task */ + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + #if defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HVND_USE) + usb_class_task(); + #endif /* defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HVND_USE) */ + } + #endif /* defined(USB_CFG_HMSC_USE) */ + #endif /*( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST )*/ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_pstd_pcd_task(); + + #if defined(USB_CFG_PMSC_USE) + #if (USB_CFG_RTOS != 1) + usb_pmsc_task(); + #endif /* USB_CFG_RTOS != 1 */ + #endif /* defined(USB_CFG_PMSC_USE) */ + #endif /*( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI )*/ +} /* End of function usb_cstd_usb_task() */ + +/****************************************************************************** + * Function Name : usb_class_task + * Description : Each device class task processing + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_class_task (void) +{ + #if defined(USB_CFG_HMSC_USE) + usb_utr_t utr; + uint16_t addr; + + usb_hmsc_task(); /* USB Host MSC driver task */ + usb_hmsc_strg_drive_task(); /* HSTRG Task */ + + if (USB_FALSE == g_drive_search_lock) + { + if (g_drive_search_que_cnt > 0) + { + g_drive_search_lock = g_drive_search_que[0]; + + utr.ip = USB_IP0; + if (USBA_ADDRESS_OFFSET == (g_drive_search_lock & USB_IP_MASK)) + { + utr.ip = USB_IP1; + } + + addr = g_drive_search_lock & USB_ADDRESS_MASK; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); /* Get the USB IP base address. */ + + /* Storage drive search. */ + usb_hmsc_strg_drive_search(&utr, addr, (usb_cb_t) usb_hmsc_drive_complete); + } + } + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HCDC_USE) + usb_hcdc_task((usb_vp_int_t) 0); /* USB Host CDC driver task */ + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HHID_USE) + usb_hhid_task((usb_vp_int_t) 0); /* USB Host CDC driver task */ + #endif /* defined(USB_CFG_HHID_USE) */ +} /* End of function usb_class_task */ + +#endif /*(BSP_CFG_RTOS == 0)*/ + +/****************************************************************************** + * Function Name : usb_cstd_remote_wakeup + * Description : Remote wakeup + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure. + * Return value : uint16_t USB_ERROR + ******************************************************************************/ +uint16_t usb_cstd_remote_wakeup (usb_utr_t * p_utr) +{ +#if (USB_CFG_MODE == USB_CFG_PERI) + if (USB_TRUE == g_usb_pstd_remote_wakeup) + { + /* Support remote wakeup ? */ + usb_pstd_change_device_state(USB_DO_REMOTEWAKEUP, USB_NULL, (usb_cb_t) usb_pstd_dummy_function, p_utr); + } + else + { + USB_PRINTF0("###usb_cstd_remote_wakeup g_usb_pstd_remote_wakeup:FALSE \n"); + + return USB_ERROR; + } + + return g_usb_pstd_remote_wakeup_state; +#else /* (USB_CFG_MODE == USB_CFG_PERI) */ + FSP_PARAMETER_NOT_USED(p_utr); + + USB_PRINTF0("###usb_cstd_remote_wakeup MODE PERI ONLY!!! \n"); + + return USB_ERROR; +#endif /* (USB_CFG_MODE == USB_CFG_PERI) */ +} /* End of function usb_cstd_remote_wakeup */ + +#if (BSP_CFG_RTOS == 1) + +/****************************************************************************** + * Function Name : usb_cstd_usbx_callback + * Description : The callback function is not used when using USBX. + * Therefore, prepared an empty function. + * Arguments : usb_event_info_t *p_api_event : + * usb_hdl_t cur_task : + * usb_onoff_t usb_state : + * Return value : none + ******************************************************************************/ +void usb_cstd_usbx_callback (usb_event_info_t * p_api_event, usb_hdl_t cur_task, usb_onoff_t usb_state) +{ + FSP_PARAMETER_NOT_USED(p_api_event); + FSP_PARAMETER_NOT_USED(cur_task); + FSP_PARAMETER_NOT_USED(usb_state); +} + +/****************************************************************************** + * End of function usb_cstd_usbx_callback + ******************************************************************************/ +#endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c new file mode 100644 index 0000000000..9609572c33 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c @@ -0,0 +1,2260 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" + +#if defined(USB_CFG_HMSC_USE) + #if (BSP_CFG_RTOS != 1) + #include "r_usb_hmsc_api.h" + #endif /* #if (BSP_CFG_RTOS != 1) */ +#endif /* defined(USB_CFG_HMSC_USE) */ + +#if defined(USB_CFG_HCDC_USE) + #if (BSP_CFG_RTOS != 1) + #include "r_usb_hcdc_driver.h" + #endif /* #if (BSP_CFG_RTOS != 1) */ +#endif /* defined(USB_CFG_HCDC_USE) */ + +#if defined(USB_CFG_HHID_USE) + #if (BSP_CFG_RTOS != 1) + #include "r_usb_hhid.h" + #endif /* #if (BSP_CFG_RTOS != 1) */ +#endif /* defined(USB_CFG_HHID_USE) */ + +#if (BSP_CFG_RTOS != 0) + #include "inc/r_usb_cstd_rtos.h" + +/****************************************************************************** + * Macro definitions + *****************************************************************************/ + #define USB_TMO_VAL (3000) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + #if (BSP_CFG_RTOS == 1) +TX_SEMAPHORE g_usb_peri_usbx_sem[USB_MAX_PIPE_NO + 1]; + #if defined(USB_CFG_OTG_USE) +TX_TIMER g_usb_otg_detach_timer; +TX_TIMER g_usb_otg_chattering_timer; +TX_TIMER g_usb_otg_hnp_timer; + #if USB_NUM_USBIP == 2 +TX_TIMER g_usb2_otg_detach_timer; + #endif /* USB_NUM_USBIP == 2 */ + #endif /* defined(USB_CFG_OTG_USE) */ + + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ + #if ((BSP_CFG_RTOS != 0) && (USB_NUM_USBIP == 2)) +static uint8_t g_usb_rtos_is_create[2] = {USB_NO}; + #endif + +/** Declare a task handler for the created tasks. **/ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +rtos_task_id_t g_hcd_tsk_hdl; +static rtos_task_id_t g_mgr_tsk_hdl; + #if (BSP_CFG_RTOS != 1) + #if USB_CFG_HUB == USB_CFG_ENABLE +static rtos_task_id_t g_hub_tsk_hdl; + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + #endif /* BSP_CFG_RTOS != 1 */ + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +static rtos_task_id_t g_pcd_tsk_hdl; + #endif /* ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + + #if defined(USB_CFG_PMSC_USE) + #if (BSP_CFG_RTOS == 2) +static rtos_task_id_t g_pmsc_tsk_hdl; + #endif /* (BSP_CFG_RTOS == 2) */ + #endif /* defined(USB_CFG_PMSC_USE) */ + + #if defined(USB_CFG_HMSC_USE) +rtos_sem_id_t SemaphoreHandleRead; + #endif /* defined(USB_CFG_HMSC_USE) */ + +/** Declare a mailbox handler for the created tasks **/ +static rtos_mbx_id_t g_hcd_mbx_hdl; +static rtos_mbx_id_t g_mgr_mbx_hdl; +static rtos_mbx_id_t g_hub_mbx_hdl; + +static rtos_mbx_id_t g_pcd_mbx_hdl; +static rtos_mbx_id_t g_cls_mbx_hdl; +static rtos_mbx_id_t g_hmsc_mbx_hdl; +static rtos_mbx_id_t g_hmsc_req_mbx_hdl; +static rtos_mbx_id_t g_hcdc_mbx_hdl; +static rtos_mbx_id_t g_hhid_mbx_hdl; +static rtos_mbx_id_t g_pmsc_mbx_hdl; +static rtos_mbx_id_t g_hprn_mbx_hdl; + +static rtos_mbx_id_t g_pipe0_hdl[USB_NUM_USBIP][USB_MAXDEVADDR]; /* USB Transfer MBX for PIPE0 wait que */ +static rtos_mbx_id_t g_pipe_hdl[USB_NUM_USBIP][USB_MAXPIPE_NUM + 1]; /* USB Transfer MBX for PIPE1-9 wait que */ + +/** Declare an array of mailbox handlers. **/ + +rtos_mbx_id_t * g_mbx_table[] = +{ + NULL, /* Not used */ + &g_hcd_mbx_hdl, /* A mailbox handler of USB HCD task */ + &g_mgr_mbx_hdl, /* A mailbox handler of USB MGR task */ + &g_hub_mbx_hdl, /* A mailbox handler of USB HUB task */ + &g_cls_mbx_hdl, /* A mailbox handler of USB internal communication */ + &g_pcd_mbx_hdl, /* A mailbox handler of USB PCD task */ + &g_hmsc_mbx_hdl, /* A mailbox handler of USB HMSC */ + &g_hmsc_req_mbx_hdl, /* A mailbox handler for class request (via PIPE0) of USB HMSC */ + &g_hcdc_mbx_hdl, /* A mailbox handler of USB HCDC task */ + &g_hhid_mbx_hdl, /* A mailbox handler of USB HHID task */ + &g_pmsc_mbx_hdl, /* A mailbox handler of USB PMSC task */ + &g_hprn_mbx_hdl, /* A mailbox handler of USB HPRN task */ +}; + + #if (BSP_CFG_RTOS == 2) + +/** Declare a memory handler for the created tasks **/ +static rtos_mem_id_t g_hcd_mpl_hdl; +static rtos_mem_id_t g_mgr_mpl_hdl; +static rtos_mem_id_t g_hub_mpl_hdl; +static rtos_mem_id_t g_cls_mpl_hdl; +static rtos_mem_id_t g_hmsc_mpl_hdl; +static rtos_mem_id_t g_hmsc_req_mpl_hdl; +static rtos_mem_id_t g_hcdc_mpl_hdl; +static rtos_mem_id_t g_hhid_mpl_hdl; +static rtos_mem_id_t g_pmsc_mpl_hdl; + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +static void * g_p_hcd_mpl[QUEUE_SIZE]; +static void * g_p_mgr_mpl[QUEUE_SIZE]; +static void * g_p_hub_mpl[QUEUE_SIZE]; +static void * g_p_cls_mpl[QUEUE_SIZE]; + #if defined(USB_CFG_HMSC_USE) +static void * g_p_hmsc_mpl[QUEUE_SIZE]; +static void * g_p_hmsc_req_mpl[QUEUE_SIZE]; + #endif /* defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HCDC_USE) +static void * g_p_hcdc_mpl[QUEUE_SIZE]; + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) +static void * g_p_hhid_mpl[QUEUE_SIZE]; + #endif /* defined(USB_CFG_HHID_USE) */ + #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + +/** Declare an array of memory pool handlers. **/ +rtos_mem_id_t * g_mpl_table[] = +{ + NULL, /* Not used */ + &g_hcd_mpl_hdl, /* A memory pool handler of USB HCD task */ + &g_mgr_mpl_hdl, /* A memory pool handler of USB MGR task */ + &g_hub_mpl_hdl, /* A memory pool handler of USB HUB task */ + &g_cls_mpl_hdl, /* A memory pool handler of USB internal communication */ + NULL, + &g_hmsc_mpl_hdl, /* A memory pool handler of USB HMSC */ + &g_hmsc_req_mpl_hdl, /* A memory pool handler for class request (via PIPE0) of USB HMSC */ + &g_hcdc_mpl_hdl, /* A memory pool handler of USB HCDC task */ + &g_hhid_mpl_hdl, /* A memory pool handler of USB HHID task */ + &g_pmsc_mpl_hdl, /* A memory pool handler of USB PMSC task */ +}; + + #else /* #if (BSP_CFG_RTOS == 2) */ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +static uint8_t g_usb_hcd_stack[HCD_STACK_SIZE]; +static uint8_t g_usb_mgr_stack[MGR_STACK_SIZE]; + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +static uint8_t g_usb_pcd_stack[PCD_STACK_SIZE]; + #endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +static uint8_t g_rtos_usb_hcd_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; +static uint8_t g_rtos_usb_mgr_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; +static uint8_t g_rtos_usb_hub_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; +static uint8_t g_rtos_usb_cls_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +static uint8_t g_rtos_usb_pcd_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; + #endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + + #if defined(USB_CFG_HMSC_USE) +static uint8_t g_rtos_usb_hmsc_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; +static uint8_t g_rtos_usb_hmsc_req_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HCDC_USE) +static uint8_t g_rtos_usb_hcdc_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) +static uint8_t g_rtos_usb_hhid_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; + #endif /* defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HPRN_USE) +static uint8_t g_rtos_usb_hprn_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; + #endif /* defined(USB_CFG_HPRN_USE) */ + +static TX_BLOCK_POOL g_usb_block_pool_hdl[USB_NUM_USBIP]; +static uint8_t g_usb_rtos_fixed_memblk[USB_NUM_USBIP][((sizeof(usb_utr_t) + sizeof(void *)) * NUM_OF_BLOCK)]; + +static uint8_t g_rtos_usb_pipe0_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; +static uint8_t g_rtos_usb_pipe_mbx[sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE)]; + #endif /* (BSP_CFG_RTOS == 2) */ + +/****************************************************************************** + * Function Name: usb_rtos_configuration + * Description : Create mailboxes, memory pool using for the created tasks + * in usb system. + * Arguments : usb_cfg_t const * const p_cfg : USB configuration + * Return Value : UsbRtos_Success - + * Successful. + * UsbRtos_Err_Init_Mbx - + * Failed in mailbox allocation. + * UsbRtos_Err_Init_Mpl - + * Failed in memory pool allocation. + ******************************************************************************/ +usb_rtos_err_t usb_rtos_configuration (usb_cfg_t const * const p_cfg) +{ + usb_rtos_err_t err = UsbRtos_Success; + uint16_t ip_loop; + uint16_t pipe_loop; + uint16_t addr_loop; + #if (BSP_CFG_RTOS != 2) + FSP_PARAMETER_NOT_USED(p_cfg); + #endif + + #if (BSP_CFG_RTOS == 2) + BaseType_t ret; + if (USB_MODE_HOST == p_cfg->usb_mode) + { + #if (USB_NUM_USBIP == 2) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + #endif + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + uint16_t i; + void * tmptr = NULL; + + /** Create mailbox for each task. **/ + /** USB HCD task **/ + g_hcd_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_hcd_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB MGR task **/ + g_mgr_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_mgr_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB HUB task **/ + g_hub_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_hub_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Internal Communication mailbox **/ + g_cls_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_cls_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + #if defined(USB_CFG_HMSC_USE) + vSemaphoreCreateBinary(SemaphoreHandleRead); + + /** USB Host MSC **/ + g_hmsc_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_hmsc_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Host MSC (for class request) **/ + g_hmsc_req_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_hmsc_req_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HCDC_USE) + + /** USB Host CDC **/ + g_hcdc_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_hcdc_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HHID_USE) + + /** USB Host HID **/ + g_hhid_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_hhid_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HHID_USE) */ + + #if defined(USB_CFG_HPRN_USE) + + /** USB Host Printer **/ + g_hprn_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_hprn_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HPRN_USE) */ + + /** Create memory pool using for each task **/ + /** USB HCD task **/ + g_hcd_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL != g_hcd_mpl_hdl) + { + /* WAIT_LOOP */ + for (i = 0; i < QUEUE_SIZE; i++) + { + tmptr = pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == tmptr) + { + USB_PRINTF0("### usb_rtos_configuration pvPortMalloc ERROR\n"); + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + g_p_hcd_mpl[i] = tmptr; + xQueueSend(g_hcd_mpl_hdl, &tmptr, 0); + } + } + else + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + /** USB MGR task **/ + g_mgr_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL != g_mgr_mpl_hdl) + { + /* WAIT_LOOP */ + for (i = 0; i < QUEUE_SIZE; i++) + { + tmptr = pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == tmptr) + { + USB_PRINTF0("### usb_rtos_configuration pvPortMalloc ERROR\n"); + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + g_p_mgr_mpl[i] = tmptr; + xQueueSend(g_mgr_mpl_hdl, &tmptr, 0); + } + } + else + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + /** USB HUB task **/ + g_hub_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL != g_hub_mpl_hdl) + { + /* WAIT_LOOP */ + for (i = 0; i < QUEUE_SIZE; i++) + { + tmptr = pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == tmptr) + { + USB_PRINTF0("### usb_rtos_configuration pvPortMalloc ERROR\n"); + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + g_p_hub_mpl[i] = tmptr; + xQueueSend(g_hub_mpl_hdl, &tmptr, 0); + } + } + else + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + /** USB Internal Communication **/ + g_cls_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL != g_cls_mpl_hdl) + { + /* WAIT_LOOP */ + for (i = 0; i < QUEUE_SIZE; i++) + { + tmptr = pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == tmptr) + { + USB_PRINTF0("### usb_rtos_configuration pvPortMalloc ERROR\n"); + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + g_p_cls_mpl[i] = tmptr; + xQueueSend(g_cls_mpl_hdl, &tmptr, 0); + } + } + else + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + #if defined(USB_CFG_HMSC_USE) + + /** USB Host MSC **/ + g_hmsc_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL != g_hmsc_mpl_hdl) + { + /* WAIT_LOOP */ + for (i = 0; i < QUEUE_SIZE; i++) + { + tmptr = pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == tmptr) + { + USB_PRINTF0("### usb_rtos_configuration pvPortMalloc ERROR\n"); + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + g_p_hmsc_mpl[i] = tmptr; + xQueueSend(g_hmsc_mpl_hdl, &tmptr, 0); + } + } + else + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + /** USB Host MSC (for class request) **/ + g_hmsc_req_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL != g_hmsc_req_mpl_hdl) + { + /* WAIT_LOOP */ + for (i = 0; i < QUEUE_SIZE; i++) + { + tmptr = pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == tmptr) + { + USB_PRINTF0("### usb_rtos_configuration pvPortMalloc ERROR\n"); + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + g_p_hmsc_req_mpl[i] = tmptr; + xQueueSend(g_hmsc_req_mpl_hdl, &tmptr, 0); + } + } + else + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HCDC_USE) + + /** USB Host CDC **/ + g_hcdc_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL != g_hcdc_mpl_hdl) + { + /* WAIT_LOOP */ + for (i = 0; i < QUEUE_SIZE; i++) + { + tmptr = pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == tmptr) + { + USB_PRINTF0("### usb_rtos_configuration pvPortMalloc ERROR\n"); + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + g_p_hcdc_mpl[i] = tmptr; + xQueueSend(g_hcdc_mpl_hdl, &tmptr, 0); + } + } + else + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HHID_USE) + + /** USB Host HID **/ + g_hhid_mpl_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL != g_hhid_mpl_hdl) + { + /* WAIT_LOOP */ + for (i = 0; i < QUEUE_SIZE; i++) + { + tmptr = pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == tmptr) + { + USB_PRINTF0("### usb_rtos_configuration pvPortMalloc ERROR\n"); + err = UsbRtos_Err_Init_Mpl; + + return err; + } + + g_p_hhid_mpl[i] = tmptr; + xQueueSend(g_hhid_mpl_hdl, &tmptr, 0); + } + } + else + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + #endif /* defined(USB_CFG_HHID_USE) */ + + /** USB Tasks Creation **/ + ret = xTaskCreate((TaskFunction_t) usb_hstd_hcd_task, /** Entry function of USB HCD task **/ + "HCD_TSK", /** Name of USB HCD task **/ + HCD_STACK_SIZE, /** Stack size in words **/ + NULL, /** Task's parameter **/ + HCD_TSK_PRI, /** Task's priority **/ + &g_hcd_tsk_hdl); /** Task handler for use later **/ + if (pdPASS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + + #if USB_CFG_HUB == USB_CFG_ENABLE + ret = xTaskCreate((TaskFunction_t) usb_hhub_task, /** Entry function of USB HUB task **/ + "HUB_TSK", /** Name of USB HUB task **/ + HUB_STACK_SIZE, /** Stack size in words **/ + NULL, /** Task's parameter **/ + HUB_TSK_PRI, /** Task's priority **/ + &g_hub_tsk_hdl); /** Task handler for use later **/ + if (pdPASS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + + ret = xTaskCreate((TaskFunction_t) usb_hstd_mgr_task, /** Entry function of USB MGR task **/ + "MGR_TSK", /** Name of USB MGR task **/ + MGR_STACK_SIZE, /** Stack size in words **/ + NULL, /** Task's parameter **/ + MGR_TSK_PRI, /** Task's priority **/ + &g_mgr_tsk_hdl); /** Task handler for use later **/ + if (pdPASS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + } + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + + /** Create mailbox **/ + /** USB PCD task **/ + g_pcd_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_pcd_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Tasks Creation **/ + ret = xTaskCreate((TaskFunction_t) usb_pstd_pcd_task, /** Entry function of USB HCD task **/ + "PCD_TSK", /** Name of USB HCD task **/ + PCD_STACK_SIZE, /** Stack size in words **/ + NULL, /** Task's parameter **/ + PCD_TSK_PRI, /** Task's priority **/ + &g_pcd_tsk_hdl); /** Task handler for use later **/ + if (pdPASS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + + #if defined(USB_CFG_PMSC_USE) + + /** Create mailbox **/ + /** USB PMSC task **/ + g_pmsc_mbx_hdl = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_pmsc_mbx_hdl) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Tasks Creation **/ + ret = xTaskCreate((TaskFunction_t) usb_pmsc_task, /** Entry function of USB PMSC task **/ + "PMSC_TSK", /** Name of USB HCD task **/ + PMSC_STACK_SIZE, /** Stack size in words **/ + NULL, /** Task's parameter **/ + PMSC_TSK_PRI, /** Task's priority **/ + &g_pmsc_tsk_hdl); /** Task handler for use later **/ + if (pdPASS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + #endif /* defined(USB_CFG_PMSC_USE) */ + } + + #if (USB_NUM_USBIP == 2) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + #endif /* (USB_NUM_USBIP == 2) */ + { + /* WAIT_LOOP */ + for (ip_loop = 0; ip_loop < USB_NUM_USBIP; ip_loop++) + { + /** Create memory pool using for pipe process **/ + /* WAIT_LOOP */ + for (addr_loop = 0; addr_loop < USB_MAXDEVADDR; addr_loop++) + { + g_pipe0_hdl[ip_loop][addr_loop] = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_pipe0_hdl[ip_loop][addr_loop]) + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + } + + /* WAIT_LOOP */ + for (pipe_loop = 0; pipe_loop < (USB_MAXPIPE_NUM + 1); pipe_loop++) + { + g_pipe_hdl[ip_loop][pipe_loop] = xQueueCreate(QUEUE_SIZE, sizeof(void *)); + if (NULL == g_pipe_hdl[ip_loop][pipe_loop]) + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + } + } + } + + #elif (BSP_CFG_RTOS == 1) /* Azure RTOS */ + uint32_t ret; + + #if (USB_CFG_MULTIPORT == USB_CFG_ENABLE) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + { + for (ip_loop = 0; ip_loop < USB_NUM_USBIP; ip_loop++) + { + ret = + tx_block_pool_create(&g_usb_block_pool_hdl[ip_loop], + "USB_MEM_BLOCK", + sizeof(usb_utr_t), + (void *) &g_usb_rtos_fixed_memblk[ip_loop][0], + (uint32_t) ((sizeof(usb_utr_t) + sizeof(void *)) * NUM_OF_BLOCK)); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + } + } + + #else + ret = tx_block_pool_create(&g_usb_block_pool_hdl[p_cfg->module_number], + "USB_MEM_BLOCK", + sizeof(usb_utr_t), + (void *) &g_usb_rtos_fixed_memblk[p_cfg->module_number][0], + (uint32_t) ((sizeof(usb_utr_t) + sizeof(void *)) * NUM_OF_BLOCK)); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + #endif + + #if !defined(USB_CFG_OTG_USE) + if (USB_MODE_HOST == p_cfg->usb_mode) + #endif /* !defined (USB_CFG_OTG_USE)*/ + { + #if (USB_NUM_USBIP == 2) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + #endif + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + + /** Create mailbox for each task. **/ + /** USB HCD task **/ + ret = + tx_queue_create(&g_hcd_mbx_hdl, "USB_HCD_MBX", TX_1_ULONG, &g_rtos_usb_hcd_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB MGR task **/ + ret = + tx_queue_create(&g_mgr_mbx_hdl, "USB_MGR_MBX", TX_1_ULONG, &g_rtos_usb_mgr_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB HUB task **/ + ret = + tx_queue_create(&g_hub_mbx_hdl, "USB_HUB_MBX", TX_1_ULONG, &g_rtos_usb_hub_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Internal Communication mailbox **/ + ret = + tx_queue_create(&g_cls_mbx_hdl, "USB_CLS_MBX", TX_1_ULONG, &g_rtos_usb_cls_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + #if defined(USB_CFG_HMSC_USE) + ret = tx_semaphore_create(&SemaphoreHandleRead, "USB_HMSC_SEM", 1); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Sem; + + return err; + } + + /** USB Host MSC **/ + ret = + tx_queue_create(&g_hmsc_mbx_hdl, "USB_HMSC_MBX", TX_1_ULONG, &g_rtos_usb_hmsc_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Host MSC (for class request) **/ + ret = + tx_queue_create(&g_hmsc_req_mbx_hdl, "USB_HMSC_REQ_MBX", TX_1_ULONG, &g_rtos_usb_hmsc_req_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HCDC_USE) + + /** USB Host CDC **/ + ret = + tx_queue_create(&g_hcdc_mbx_hdl, "USB_HCDC_MBX", TX_1_ULONG, &g_rtos_usb_hcdc_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HHID_USE) + + /** USB Host HID **/ + + ret = + tx_queue_create(&g_hhid_mbx_hdl, "USB_HHID_MBX", TX_1_ULONG, &g_rtos_usb_hhid_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HHID_USE) */ + + #if defined(USB_CFG_HPRN_USE) + + /** USB Host Printer **/ + ret = + tx_queue_create(&g_hprn_mbx_hdl, "USB_HPRN_MBX", TX_1_ULONG, &g_rtos_usb_hprn_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HPRN_USE) */ + + ret = tx_thread_create(&g_hcd_tsk_hdl, /** Pointer to a thread control block. **/ + "HCD_TASK", /** Pointer to the name of the thread. **/ + usb_hstd_hcd_task, /** Entry function of USB HCD task **/ + (uint32_t) NULL, /** Task's parameter **/ + (void *) &g_usb_hcd_stack[0], /** Starting address of the stack fs memory area. **/ + HCD_STACK_SIZE, /** Number bytes in the stack memory area. **/ + HCD_TSK_PRI, /** Task's priority **/ + HCD_TSK_PRI, /** Preempt Threashold **/ + TX_NO_TIME_SLICE, /** Time Slice (Yes or No) **/ + TX_AUTO_START); /** Auto Start (Yes or No) **/ + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + + ret = tx_thread_create(&g_mgr_tsk_hdl, /** Pointer to a thread control block. **/ + "MGR_TSK", /** Pointer to the name of the thread. **/ + usb_hstd_mgr_task, /** Entry function of USB HCD task **/ + (uint32_t) NULL, /** Task's parameter **/ + (void *) &g_usb_mgr_stack[0], /** Starting address of the stack fs memory area. **/ + MGR_STACK_SIZE, /** Number bytes in the stack memory area. **/ + MGR_TSK_PRI, /** Task's priority **/ + MGR_TSK_PRI, /** Task's priority **/ + TX_NO_TIME_SLICE, /** Time Slice (Yes or No) **/ + TX_AUTO_START); /** Auto Start (Yes or No) **/ + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + } + } + + #if defined(USB_CFG_OTG_USE) + #else + else + #endif /* defined (USB_CFG_OTG_USE) */ + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + + /** Create mailbox **/ + /** USB PCD task **/ + ret = + tx_queue_create(&g_pcd_mbx_hdl, "USB_PCD_MBX", TX_1_ULONG, &g_rtos_usb_pcd_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Tasks Creation **/ + ret = tx_thread_create(&g_pcd_tsk_hdl, /** Pointer to a thread control block. **/ + "PCD_TSK", /** Pointer to the name of the thread. **/ + usb_pstd_pcd_task, /** Entry function of USB HCD task **/ + (uint32_t) NULL, /** Task's parameter **/ + (void *) &g_usb_pcd_stack[0], /** Starting address of the stack fs memory area. **/ + PCD_STACK_SIZE, /** Number bytes in the stack memory area. **/ + PCD_TSK_PRI, /** Task's priority **/ + PCD_TSK_PRI, /** Preempt_threshold **/ + TX_NO_TIME_SLICE, /** Time Slice (Yes or No) **/ + TX_AUTO_START); /** Auto Start (Yes or No) **/ + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + } + #if (USB_NUM_USBIP == 2) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + #endif + { + /* WAIT_LOOP */ + for (ip_loop = 0; ip_loop < USB_NUM_USBIP; ip_loop++) + { + /** Create memory pool using for pipe process **/ + /* WAIT_LOOP */ + for (addr_loop = 0; addr_loop < USB_MAXDEVADDR; addr_loop++) + { + ret = tx_queue_create(&g_pipe0_hdl[ip_loop][addr_loop], + "USB_PIPE0_MBX", + TX_1_ULONG, + &g_rtos_usb_pipe0_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + } + + /* WAIT_LOOP */ + for (pipe_loop = 0; pipe_loop < (USB_MAXPIPE_NUM + 1); pipe_loop++) + { + ret = + tx_queue_create(&g_pipe_hdl[ip_loop][pipe_loop], + "USB_PIPE_MBX", + TX_1_ULONG, + &g_rtos_usb_pipe_mbx[0], + (sizeof(ULONG) * (TX_1_ULONG) *(QUEUE_SIZE))); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + } + } + } + + #if defined(USB_CFG_OTG_USE) + ret = tx_timer_create(&g_usb_otg_detach_timer, /* Pointer to detach timer */ + "USB OTG Detach Timer", /* Detach Timer Name */ + usb_otg_detach_timer, /* Pointer to detach timer function */ + (ULONG) 0, /* Expiration Input */ + (ULONG) 5, /* Initial Ticks */ + (ULONG) 5, /* Reschedule Ticks */ + TX_NO_ACTIVATE); /* Auto Activate */ + + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_OTG_Detach_Tmr; + + return err; + } + + ret = tx_timer_create(&g_usb_otg_chattering_timer, /* Pointer to detach timer */ + "USB OTG Chattering Timer", /* Detach Timer Name */ + usb_otg_chattering_timer, /* Pointer to detach timer function */ + (ULONG) 0, /* Expiration Input */ + (ULONG) 4, /* Initial Ticks */ + (ULONG) 4, /* Reschedule Ticks */ + TX_AUTO_ACTIVATE); /* Auto Activate */ + + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_OTG_Chattering_Tmr; + + return err; + } + + ret = tx_timer_create(&g_usb_otg_hnp_timer, /* Pointer to detach timer */ + "USB OTG HNP Timer", /* Detach Timer Name */ + usb_otg_hnp_timer, /* Pointer to detach timer function */ + (ULONG) 0, /* Expiration Input */ + (ULONG) 10, /* Initial Ticks */ + (ULONG) 10, /* Reschedule Ticks */ + TX_NO_ACTIVATE); /* Auto Activate */ + + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_OTG_HNP_Tmr; + + return err; + } + + #if USB_NUM_USBIP == 2 + ret = tx_timer_create(&g_usb2_otg_detach_timer, /* Pointer to detach timer */ + "USB2 OTG Detach Timer", /* Detach Timer Name */ + usb2_otg_detach_timer, /* Pointer to detach timer function */ + (ULONG) 0, /* Expiration Input */ + (ULONG) 5, /* Initial Ticks */ + (ULONG) 5, /* Reschedule Ticks */ + TX_NO_ACTIVATE); /* Auto Activate */ + + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_OTG_Detach_Tmr; + + return err; + } + #endif /* USB_NUM_USBIP == 2 */ + #endif /* defined (USB_CFG_OTG_USE) */ + #endif /* BSP_CFG_RTOS */ + + #if (USB_NUM_USBIP == 2) + g_usb_rtos_is_create[p_cfg->module_number] = USB_YES; + #endif + + return err; +} /* End of function usb_rtos_configuration() */ + +/****************************************************************************** + * Function Name: usb_rtos_delete + * Description : Delete mailboxes, memory pool using for the deleted tasks + * in usb system. + * Arguments : uint8_t module_number : USB module number + * Return Value : UsbRtos_Success - + * Successful. + * UsbRtos_Err_Delete_Mbx - + * Failed in mailbox allocation. + * UsbRtos_Err_Delete_Mpl - + * Failed in memory pool allocation. + ******************************************************************************/ +usb_rtos_err_t usb_rtos_delete (uint8_t module_number) +{ + usb_rtos_err_t err = UsbRtos_Success; + uint16_t ip_loop; + uint16_t pipe_loop; + uint16_t addr_loop; + #if (USB_NUM_USBIP == 2) + g_usb_rtos_is_create[module_number] = USB_NO; + #endif + #if (BSP_CFG_RTOS == 2) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + uint16_t i; + #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + if (USB_MODE_HOST == g_usb_usbmode[module_number]) + { + #if (USB_NUM_USBIP == 2) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + #endif + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + + /** Delete mailbox for each task. **/ + /** USB HCD task **/ + vQueueDelete(g_hcd_mbx_hdl); + + /** USB MGR task **/ + vQueueDelete(g_mgr_mbx_hdl); + + /** USB HUB task **/ + vQueueDelete(g_hub_mbx_hdl); + + /** USB Internal Communication mailbox **/ + vQueueDelete(g_cls_mbx_hdl); + + #if defined(USB_CFG_HMSC_USE) + vSemaphoreDelete(SemaphoreHandleRead); + + /** USB Host MSC **/ + vQueueDelete(g_hmsc_mbx_hdl); + + /** USB Host MSC (for class request) **/ + vQueueDelete(g_hmsc_req_mbx_hdl); + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HCDC_USE) + + /** USB Host CDC **/ + vQueueDelete(g_hcdc_mbx_hdl); + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HHID_USE) + + /** USB Host HID **/ + vQueueDelete(g_hhid_mbx_hdl); + #endif /* defined(USB_CFG_HHID_USE) */ + + #if defined(USB_CFG_HPRN_USE) + + /** USB Host Printer **/ + vQueueDelete(g_hprn_mbx_hdl); + #endif /* defined(USB_CFG_HPRN_USE) */ + + /** Delete memory pool using for each task **/ + /** USB HCD task **/ + vQueueDelete(g_hcd_mpl_hdl); + for (i = 0; i < QUEUE_SIZE; i++) + { + vPortFree(g_p_hcd_mpl[i]); + } + + /** USB MGR task **/ + vQueueDelete(g_mgr_mpl_hdl); + for (i = 0; i < QUEUE_SIZE; i++) + { + vPortFree(g_p_mgr_mpl[i]); + } + + /** USB HUB task **/ + vQueueDelete(g_hub_mpl_hdl); + for (i = 0; i < QUEUE_SIZE; i++) + { + vPortFree(g_p_hub_mpl[i]); + } + + /** USB Internal Communication **/ + vQueueDelete(g_cls_mpl_hdl); + for (i = 0; i < QUEUE_SIZE; i++) + { + vPortFree(g_p_cls_mpl[i]); + } + + #if defined(USB_CFG_HMSC_USE) + + /** USB Host MSC **/ + vQueueDelete(g_hmsc_mpl_hdl); + for (i = 0; i < QUEUE_SIZE; i++) + { + vPortFree(g_p_hmsc_mpl[i]); + } + + /** USB Host MSC (for class request) **/ + vQueueDelete(g_hmsc_req_mpl_hdl); + for (i = 0; i < QUEUE_SIZE; i++) + { + vPortFree(g_p_hmsc_req_mpl[i]); + } + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HCDC_USE) + + /** USB Host CDC **/ + vQueueDelete(g_hcdc_mpl_hdl); + for (i = 0; i < QUEUE_SIZE; i++) + { + vPortFree(g_p_hcdc_mpl[i]); + } + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HHID_USE) + + /** USB Host HID **/ + vQueueDelete(g_hhid_mpl_hdl); + for (i = 0; i < QUEUE_SIZE; i++) + { + vPortFree(g_p_hhid_mpl[i]); + } + #endif /* defined(USB_CFG_HHID_USE) */ + + /** USB Tasks Creation **/ + vTaskDelete(g_hcd_tsk_hdl); + + #if USB_CFG_HUB == USB_CFG_ENABLE + vTaskDelete(g_hub_tsk_hdl); + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + vTaskDelete(g_mgr_tsk_hdl); + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + } + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + + /** USB Tasks Creation **/ + vTaskDelete(g_pcd_tsk_hdl); + + /** Delete mailbox **/ + /** USB PCD task **/ + vQueueDelete(g_pcd_mbx_hdl); + + #if defined(USB_CFG_PMSC_USE) + + /** USB Tasks Creation **/ + vTaskDelete(g_pmsc_tsk_hdl); + + /** Delete mailbox **/ + /** USB PMSC task **/ + vQueueDelete(g_pmsc_mbx_hdl); + #endif /* defined(USB_CFG_PMSC_USE) */ + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + } + + #if (USB_NUM_USBIP == 2) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + #endif /* (USB_NUM_USBIP == 2) */ + { + /* WAIT_LOOP */ + for (ip_loop = 0; ip_loop < USB_NUM_USBIP; ip_loop++) + { + /** Delete memory pool using for pipe process **/ + /* WAIT_LOOP */ + for (addr_loop = 0; addr_loop < USB_MAXDEVADDR; addr_loop++) + { + vQueueDelete(g_pipe0_hdl[ip_loop][addr_loop]); + } + + /* WAIT_LOOP */ + for (pipe_loop = 0; pipe_loop < (USB_MAXPIPE_NUM + 1); pipe_loop++) + { + vQueueDelete(g_pipe_hdl[ip_loop][pipe_loop]); + } + } + } /* (USB_NUM_USBIP == 2) */ + + #elif (BSP_CFG_RTOS == 1) /* Azure RTOS */ + uint32_t ret; + (void) module_number; + + #if (USB_CFG_MULTIPORT == USB_CFG_ENABLE) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + { + for (ip_loop = 0; ip_loop < USB_NUM_USBIP; ip_loop++) + { + ret = tx_block_pool_delete(&g_usb_block_pool_hdl[ip_loop]); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + } + } + + #else + ret = tx_block_pool_delete(&g_usb_block_pool_hdl[module_number]); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + #endif + + #if !defined(USB_CFG_OTG_USE) + if (USB_MODE_HOST == g_usb_usbmode[module_number]) + #endif /* !defined (USB_CFG_OTG_USE)*/ + { + #if (USB_NUM_USBIP == 2) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + #endif + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + + /** Delete mailbox for each task. **/ + /** USB HCD task **/ + ret = tx_queue_delete(&g_hcd_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB MGR task **/ + ret = tx_queue_delete(&g_mgr_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB HUB task **/ + ret = tx_queue_delete(&g_hub_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Internal Communication mailbox **/ + ret = tx_queue_delete(&g_cls_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + #if defined(USB_CFG_HMSC_USE) + ret = tx_semaphore_delete(&SemaphoreHandleRead); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Sem; + + return err; + } + + /** USB Host MSC **/ + ret = tx_queue_delete(&g_hmsc_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + + /** USB Host MSC (for class request) **/ + ret = tx_queue_delete(&g_hmsc_req_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HCDC_USE) + + /** USB Host CDC **/ + ret = tx_queue_delete(&g_hcdc_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HHID_USE) + + /** USB Host HID **/ + ret = tx_queue_delete(&g_hhid_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HHID_USE) */ + + #if defined(USB_CFG_HPRN_USE) + + /** USB Host Printer **/ + ret = tx_queue_delete(&g_hprn_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* defined(USB_CFG_HPRN_USE) */ + + ret = tx_thread_terminate(&g_hcd_tsk_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + + ret = tx_thread_delete(&g_hcd_tsk_hdl); /** Pointer to a thread control block. **/ + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + + ret = tx_thread_terminate(&g_mgr_tsk_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + + ret = tx_thread_delete(&g_mgr_tsk_hdl); /** Task handler for use later **/ + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + } + } + + #if defined(USB_CFG_OTG_USE) + #else + else + #endif + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + ret = tx_thread_terminate(&g_pcd_tsk_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + + /** USB Tasks Creation **/ + ret = tx_thread_delete(&g_pcd_tsk_hdl); /** Task handler for use later **/ + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Tsk; + + return err; + } + + /** Delete mailbox **/ + /** USB PCD task **/ + ret = tx_queue_delete(&g_pcd_mbx_hdl); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mbx; + + return err; + } + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + } + + #if (USB_NUM_USBIP == 2) + if (!(g_usb_rtos_is_create[0] || g_usb_rtos_is_create[1])) + #endif + { + /* WAIT_LOOP */ + for (ip_loop = 0; ip_loop < USB_NUM_USBIP; ip_loop++) + { + /** Delete memory pool using for pipe process **/ + /* WAIT_LOOP */ + for (addr_loop = 0; addr_loop < USB_MAXDEVADDR; addr_loop++) + { + ret = tx_queue_delete(&g_pipe0_hdl[ip_loop][addr_loop]); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + } + + /* WAIT_LOOP */ + for (pipe_loop = 0; pipe_loop < (USB_MAXPIPE_NUM + 1); pipe_loop++) + { + ret = tx_queue_delete(&g_pipe_hdl[ip_loop][pipe_loop]); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Init_Mpl; + + return err; + } + } + } + } + + #if defined(USB_CFG_OTG_USE) + tx_timer_deactivate(&g_usb_otg_detach_timer); + ret = tx_timer_delete(&g_usb_otg_detach_timer); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Delete_OTG_Detach_Tmr; + + return err; + } + + #if USB_NUM_USBIP == 2 + tx_timer_deactivate(&g_usb2_otg_detach_timer); + ret = tx_timer_delete(&g_usb2_otg_detach_timer); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Delete_OTG_Detach_Tmr; + + return err; + } + #endif /* USB_NUM_USBIP == 2 */ + ret = tx_timer_delete(&g_usb_otg_chattering_timer); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Delete_OTG_Chattering_Tmr; + + return err; + } + + ret = tx_timer_delete(&g_usb_otg_hnp_timer); + if (TX_SUCCESS != ret) + { + err = UsbRtos_Err_Delete_OTG_HNP_Tmr; + + return err; + } + #endif /* defined (USB_CFG_OTG_USE) */ + #endif /* BSP_CFG_RTOS */ + + return err; +} /* End of function usb_rtos_delete() */ + +/****************************************************************************** + * Function Name : usb_cstd_rec_msg + * Description : Receive a message to the specified id (mailbox). + * Argument : uint8_t id : ID number (mailbox). + * : usb_msg_t** mess : Message pointer + * : usb_tm_t tm : Timeout Value + * Return : uint16_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_rec_msg (uint8_t id, usb_msg_t ** mess, usb_tm_t tm) +{ + #if (BSP_CFG_RTOS == 2) + BaseType_t err; + #elif (BSP_CFG_RTOS == 1) + uint32_t err; + #endif + usb_er_t result; + + if (NULL == mess) + { + return USB_ERROR; + } + + *mess = NULL; + + if (0 == tm) + { + tm = USB_TMO_VAL; + } + + #if (BSP_CFG_RTOS == 2) + + /** Receive message from queue specified by *(mbx_table[id]) **/ + err = xQueueReceive(*(g_mbx_table[id]), (void *) mess, (TickType_t) tm); + if ((pdTRUE == err) && (NULL != (*mess))) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + + #elif (BSP_CFG_RTOS == 1) + err = tx_queue_receive(g_mbx_table[id], (void *) mess, (uint32_t) tm); + if ((TX_SUCCESS == err) && (NULL != mess)) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + #endif + + return result; +} + +/****************************************************************************** + * End of function usb_cstd_rec_msg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_snd_msg + * Description : Send a message to the specified id (mailbox). + * Argument : uint8_t id : ID number (mailbox). + * : usb_msg_t* mess : Message pointer + * Return : usb_er_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_snd_msg (uint8_t id, usb_msg_t * mess) +{ + #if (BSP_CFG_RTOS == 2) + BaseType_t err; + #elif (BSP_CFG_RTOS == 1) + uint32_t err; + #endif + usb_er_t result; + + if (NULL == mess) + { + return USB_ERROR; + } + + #if (BSP_CFG_RTOS == 2) + + /** Send message to queue specified by *(mbx_table[id]) **/ + err = xQueueSend(*(g_mbx_table[id]), (const void *) &mess, (TickType_t) (0)); + if (pdTRUE == err) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + + #elif (BSP_CFG_RTOS == 1) + err = tx_queue_send(g_mbx_table[id], (void *) &mess, TX_NO_WAIT); + if ((TX_SUCCESS == err) && (NULL != mess)) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + #endif + + return result; +} + +/****************************************************************************** + * End of function usb_cstd_snd_msg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_isnd_msg + * Description : Send a message to the specified id (mailbox) while executing + * : an interrupt. + * Argument : uint8_t id : ID number (mailbox). + * : usb_msg_t* mess : Message pointer + * Return : usb_er_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_isnd_msg (uint8_t id, usb_msg_t * mess) +{ + #if (BSP_CFG_RTOS == 2) + BaseType_t err; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + #elif (BSP_CFG_RTOS == 1) + uint32_t err; + #endif + usb_er_t result; + + if (NULL == mess) + { + return USB_ERROR; + } + + #if (BSP_CFG_RTOS == 2) + + /** Send message to queue specified by *(mbx_table[id]) from ISR **/ + err = xQueueSendFromISR(*(g_mbx_table[id]), (const void *) &mess, &xHigherPriorityTaskWoken); + if (pdTRUE == err) + { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + result = USB_OK; + } + else + { + result = USB_ERROR; + } + + #elif (BSP_CFG_RTOS == 1) + err = tx_queue_send(g_mbx_table[id], (void *) &mess, TX_NO_WAIT); + if ((TX_SUCCESS == err) && (NULL != mess)) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + #endif + + return result; +} + +/****************************************************************************** + * End of function usb_cstd_isnd_msg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_pget_blk + * Description : Get a memory block for the caller. + * Argument : uint8_t id : ID number (mailbox). + * : usb_utr_t** blk : Memory block pointer. + * Return : usb_er_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_pget_blk (uint8_t id, usb_utr_t ** blk, uint8_t ip) +{ + #if (BSP_CFG_RTOS == 2) + FSP_PARAMETER_NOT_USED(ip); + BaseType_t err; + QueueHandle_t handle; + #elif (BSP_CFG_RTOS == 1) + FSP_PARAMETER_NOT_USED(id); + uint32_t err; + #endif + usb_er_t result; + + if (NULL == blk) + { + return USB_ERROR; + } + + #if (BSP_CFG_RTOS == 2) + handle = *(g_mpl_table[id]); + *blk = NULL; + + /* Look for a free memory block */ + err = xQueueReceive(handle, (void *) blk, (TickType_t) (0)); + if ((pdTRUE == err) && (NULL != (*blk))) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + + #elif (BSP_CFG_RTOS == 1) + err = tx_block_allocate(&g_usb_block_pool_hdl[ip], (void **) blk, TX_NO_WAIT); + if ((TX_SUCCESS == err) && (NULL != (*blk))) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + #endif /* BSP_CFG_RTOS */ + + return result; +} + +/****************************************************************************** + * End of function usb_cstd_pget_blk + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_rel_blk + * Description : Release a memory block. + * Argument : uint8_t id : ID number (mailbox). + * : usb_utr_t* blk : Memory block pointer. + * Return : usb_er_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_rel_blk (uint8_t id, usb_utr_t * blk) +{ + #if (BSP_CFG_RTOS == 2) + BaseType_t err; + QueueHandle_t handle; + #elif (BSP_CFG_RTOS == 1) + FSP_PARAMETER_NOT_USED(id); + uint32_t err; + #endif + usb_er_t result; + + if (NULL == blk) + { + return USB_ERROR; + } + + #if (BSP_CFG_RTOS == 2) + handle = (*(g_mpl_table[id])); + + /* Release a memory block specified by id */ + err = xQueueSend(handle, (const void *) &blk, (TickType_t) (0)); + if (pdTRUE == err) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + + #elif (BSP_CFG_RTOS == 1) + err = tx_block_release((void *) blk); + if (TX_SUCCESS == err) + { + result = USB_OK; + } + else + { + result = USB_ERROR; + } + #endif /* BSP_CFG_RTOS */ + + return result; +} + +/****************************************************************************** + * End of function usb_cstd_rel_blk + ******************************************************************************/ + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/***************************************************************************//** + * @brief Runs USB_SND_MSG after running the scheduler the specified number of times. + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_FAILED Failed in acquiring version information. + ******************************************************************************/ +fsp_err_t usb_cstd_wai_msg (uint8_t id, usb_msg_t * mess, usb_tm_t times) +{ + usb_er_t err; + fsp_err_t result; + + #if (BSP_CFG_RTOS == 2) + vTaskDelay((TickType_t) ((uint16_t) times / portTICK_PERIOD_MS)); + #elif (BSP_CFG_RTOS == 1) + tx_thread_sleep((rtos_time_t) times); + #endif /* #if (BSP_CFG_RTOS == 1) */ + err = usb_cstd_snd_msg(id, mess); + + if (USB_OK == err) + { + result = FSP_SUCCESS; + } + else + { + result = FSP_ERR_USB_FAILED; + } + + return result; +} + +/****************************************************************************** + * End of function usb_cstd_wai_msg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_wait_scheduler + * Description : Schedules a wait request. + * Argument : none + * Return : none + ******************************************************************************/ +void usb_cstd_wait_scheduler (void) +{ +} + +/****************************************************************************** + * End of function usb_cstd_wait_scheduler + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_sche_init + * Description : Scheduler initialization. + * Argument : none + * Return : none + ******************************************************************************/ +void usb_cstd_sche_init (void) +{ +} + +/****************************************************************************** + * End of function usb_cstd_sche_init + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_set_task_pri + * Description : Set a task's priority. + * Argument : uint8_t tasknum : Task id. + * : uint8_t pri : The task priority to be set. + * Return : none + ******************************************************************************/ +void usb_cstd_set_task_pri (uint8_t tasknum, uint8_t pri) +{ + (void) tasknum; + (void) pri; +} + +/****************************************************************************** + * End of function usb_cstd_set_task_pri + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_check_schedule + * Description : Check schedule flag to see if caller's "time has come", then + * : clear it. + * Argument : none + * Return : flg : usb_scheduler_schedule_flag + ******************************************************************************/ +uint8_t usb_cstd_check_schedule (void) +{ + return USB_FLGSET; +} + +/****************************************************************************** + * End of function usb_cstd_check_schedule + ******************************************************************************/ + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : usb_cstd_pipe_msg_clear + * Description : Message clear for PIPE Transfer wait que. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe_no : Pipe no. + * Return : none + ******************************************************************************/ +void usb_cstd_pipe_msg_clear (usb_utr_t * ptr, uint16_t pipe_no) +{ + #if (BSP_CFG_RTOS == 2) + BaseType_t err; + #elif (BSP_CFG_RTOS == 1) + uint32_t err; + #endif + usb_msg_t * mess; + uint16_t ip; + + ip = ptr->ip; + + #if (BSP_CFG_RTOS == 2) + vPortFree(ptr); + if ((USB_MIN_PIPE_NO > pipe_no) || (USB_MAXPIPE_NUM < pipe_no)) + { + return; + } + + /* WAIT_LOOP */ + do + { + /** Receive message from queue specified by *(mbx_table[id]) **/ + err = xQueueReceive(g_pipe_hdl[ip][pipe_no], (void *) &mess, (TickType_t) (0)); + if ((pdTRUE == err) && (NULL != (mess))) + { + vPortFree(mess); + } + else + { + break; + } + } while (pdTRUE == err); + + #elif (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, ptr); + if ((USB_MIN_PIPE_NO > pipe_no) || (USB_MAXPIPE_NUM < pipe_no)) + { + return; + } + + /* WAIT_LOOP */ + do + { + /** Receive message from queue specified by *(mbx_table[id]) **/ + err = tx_queue_receive(&g_pipe_hdl[ip][pipe_no], (void *) &mess, TX_NO_WAIT); + if ((TX_SUCCESS == err) && (NULL != mess)) + { + USB_REL_BLK(1, mess); + } + else + { + break; + } + } while (TX_SUCCESS == err); + #endif +} + +/****************************************************************************** + * End of function usb_cstd_pipe_msg_clear + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_pipe0_msg_clear + * Description : Message clear for PIPE0 Transfer wait que. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t dev_addr : device address + * Return : none + ******************************************************************************/ +void usb_cstd_pipe0_msg_clear (usb_utr_t * ptr, uint16_t dev_addr) +{ + #if (BSP_CFG_RTOS == 2) + BaseType_t err; + #elif (BSP_CFG_RTOS == 1) + uint32_t err; + #endif + usb_msg_t * mess; + uint16_t ip; + + ip = ptr->ip; + + #if (BSP_CFG_RTOS == 2) + vPortFree(ptr); + if ((USB_DEVICEADDR > dev_addr) || (USB_MAXDEVADDR < dev_addr)) + { + return; + } + + /* WAIT_LOOP */ + do + { + /** Receive message from queue specified by *(mbx_table[id]) **/ + err = xQueueReceive(g_pipe0_hdl[ip][dev_addr], (void *) &mess, (TickType_t) (0)); + if ((pdTRUE == err) && (NULL != (mess))) + { + vPortFree(mess); + } + else + { + break; + } + } while (pdTRUE == err); + + #elif (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, ptr); + if ((USB_DEVICEADDR > dev_addr) || (USB_MAXDEVADDR < dev_addr)) + { + return; + } + + /* WAIT_LOOP */ + do + { + err = tx_queue_receive(&g_pipe_hdl[ip][dev_addr], (void *) &mess, TX_NO_WAIT); + if ((TX_SUCCESS == err) && (NULL != mess)) + { + USB_REL_BLK(1, mess); + } + else + { + break; + } + } while (TX_SUCCESS == err); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + tx_semaphore_put(&g_usb_host_usbx_sem[ptr->ip][0]); + #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + #endif +} + +/****************************************************************************** + * End of function usb_cstd_pipe0_msg_clear + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_pipe_msg_re_forward + * Description : Get PIPE Transfer wait que and Message send to HCD/PCD + * Argument : uint16_t pipe_no : Pipe no. + * Return : none + ******************************************************************************/ +void usb_cstd_pipe_msg_re_forward (uint16_t ip_no, uint16_t pipe_no) +{ + #if (BSP_CFG_RTOS == 2) + BaseType_t err; + #elif (BSP_CFG_RTOS == 1) + uint32_t err; + #endif + usb_msg_t * mess; + rtos_mbx_id_t handle; + uint8_t id; + + if ((USB_MIN_PIPE_NO > pipe_no) || (USB_MAXPIPE_NUM < pipe_no)) + { + return; + } + + #if (BSP_CFG_RTOS == 2) + + /** Receive message from queue specified by *(mbx_table[id]) **/ + err = xQueueReceive(g_pipe_hdl[ip_no][pipe_no], (void *) &mess, (TickType_t) (0)); + if ((pdTRUE == err) && (NULL != (mess))) + { + if (USB_MODE_HOST == g_usb_usbmode[ip_no]) + { + id = USB_HCD_MBX; + } + else + { + id = USB_PCD_MBX; + } + + handle = (*(g_mbx_table[id])); + + /** Send message to queue specified by *(mbx_table[id]) **/ + xQueueSend(handle, (const void *) &mess, (TickType_t) (0)); + } + + #elif (BSP_CFG_RTOS == 1) + + /** Receive message from queue specified by *(mbx_table[id]) **/ + err = tx_queue_receive(&g_pipe_hdl[ip_no][pipe_no], (void *) &mess, TX_NO_WAIT); + if ((TX_SUCCESS == err) && (NULL != mess)) + { + if (USB_MODE_HOST == g_usb_usbmode[ip_no]) + { + id = USB_HCD_MBX; + } + else + { + id = USB_PCD_MBX; + } + + handle = (*(g_mbx_table[id])); + + /** Send message to queue specified by *(mbx_table[id]) **/ + tx_queue_send(&handle, (void *) &mess, TX_NO_WAIT); + } + #endif +} + +/****************************************************************************** + * End of function usb_cstd_pipe_msg_re_forward + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_pipe0_msg_re_forward + * Description : Get PIPE0 Transfer wait que and Message send to HCD/PCD + * Argument : none + * Return : none + ******************************************************************************/ +void usb_cstd_pipe0_msg_re_forward (uint16_t ip_no) +{ + #if (BSP_CFG_RTOS == 2) + BaseType_t err; + #elif (BSP_CFG_RTOS == 1) + uint32_t err; + #endif + usb_msg_t * mess; + rtos_mbx_id_t handle; + uint8_t id; + uint8_t dev_addr; + + /* WAIT_LOOP */ + for (dev_addr = 0; dev_addr < USB_MAXDEVADDR; dev_addr++) + { + #if (BSP_CFG_RTOS == 2) + + /** Receive message from queue specified by *(mbx_table[id]) **/ + err = xQueueReceive(g_pipe0_hdl[ip_no][dev_addr], (void *) &mess, (TickType_t) (0)); + if ((pdTRUE == err) && (NULL != (mess))) + { + if (USB_MODE_HOST == g_usb_usbmode[ip_no]) + { + id = USB_HCD_MBX; + } + else + { + id = USB_PCD_MBX; + } + + handle = (*(g_mbx_table[id])); + + /** Send message to queue specified by *(mbx_table[id]) **/ + xQueueSend(handle, (const void *) &mess, (TickType_t) (0)); + + return; + } + + #elif (BSP_CFG_RTOS == 1) + + /** Receive message from queue specified by *(mbx_table[id]) **/ + err = tx_queue_receive(&g_pipe0_hdl[ip_no][dev_addr], (void *) &mess, TX_NO_WAIT); + if ((TX_SUCCESS == err) && (NULL != mess)) + { + if (USB_MODE_HOST == g_usb_usbmode[ip_no]) + { + id = USB_HCD_MBX; + } + else + { + id = USB_PCD_MBX; + } + + handle = (*(g_mbx_table[id])); + + /** Send message to queue specified by *(mbx_table[id]) **/ + tx_queue_send(&handle, (void *) &mess, TX_NO_WAIT); + } + #endif + } +} + +/****************************************************************************** + * End of function usb_cstd_pipe0_msg_re_forward + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_pipe_msg_forward + * Description : Message forward to PIPE Transfer wait que. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe_no : Pipe no. + * Return : none + ******************************************************************************/ +void usb_cstd_pipe_msg_forward (usb_utr_t * ptr, uint16_t pipe_no) +{ + if ((USB_MIN_PIPE_NO > pipe_no) || (USB_MAXPIPE_NUM < pipe_no)) + { + return; + } + + #if (BSP_CFG_RTOS == 2) + + /** Send message to queue specified by *(mbx_table[id]) **/ + xQueueSend(g_pipe_hdl[ptr->ip][pipe_no], (const void *) &ptr, (TickType_t) (0)); + #elif (BSP_CFG_RTOS == 1) + tx_queue_send(&g_pipe_hdl[ptr->ip][pipe_no], (void *) &ptr, TX_NO_WAIT); + #endif /* #if (BSP_CFG_RTOS == 2) */ +} + +/****************************************************************************** + * End of function usb_cstd_pipe_msg_forward + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_pipe0_msg_forward + * Description : Message forward to PIPE0 Transfer wait que. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t dev_addr : device address + * Return : none + ******************************************************************************/ +void usb_cstd_pipe0_msg_forward (usb_utr_t * ptr, uint16_t dev_addr) +{ + if ((USB_DEVICEADDR > dev_addr) || (USB_MAXDEVADDR < dev_addr)) + { + return; + } + + #if (BSP_CFG_RTOS == 2) + + /** Send message to queue specified by *(mbx_table[id]) **/ + xQueueSend(g_pipe0_hdl[ptr->ip][dev_addr], (const void *) &ptr, (TickType_t) (0)); + #elif (BSP_CFG_RTOS == 1) + tx_queue_send(&g_pipe_hdl[ptr->ip][dev_addr], (void *) &ptr, TX_NO_WAIT); + #endif /* #if (BSP_CFG_RTOS == 2) */ +} + +/****************************************************************************** + * End of function usb_cstd_pipe0_msg_forward + ******************************************************************************/ + +#endif /* #if (BSP_CFG_RTOS != 0) */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hbc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hbc.c new file mode 100644 index 0000000000..c6daf5992e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hbc.c @@ -0,0 +1,268 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if USB_CFG_BC == USB_CFG_ENABLE + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/* PD Detect Define */ + #define USB_BC_NODET (0x00U) + #define USB_BC_PDDET (0x01U) + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ + +/****************************************************************************** + * Exported global variables and functions (to be accessed by other files) + ******************************************************************************/ + +/* variables */ +usb_bc_status_t g_usb_hstd_bc[2U]; + +/* functions */ +void usb_hstd_pddetint_process(usb_utr_t * ptr); + +/* BC State change function table */ +void (* usb_hstd_bc_func[USB_BC_STATE_MAX][USB_BC_EVENT_MAX])(usb_utr_t * ptr) = +{ + /* VBUS_ON ATTACH DETACH */ + {usb_hstd_bc_init_vb, usb_hstd_bc_err, usb_hstd_bc_err }, /* USB_BC_STATE_INIT */ + {usb_hstd_bc_err, usb_hstd_bc_det_at, usb_hstd_bc_err }, /* USB_BC_STATE_DET */ + {usb_hstd_bc_err, usb_hstd_bc_err, usb_hstd_bc_cdp_dt}, /* USB_BC_STATE_CDP */ + {usb_hstd_bc_err, usb_hstd_bc_err, usb_hstd_bc_sdp_dt}, /* USB_BC_STATE_SDP */ + {usb_hstd_bc_err, usb_hstd_bc_err, usb_hstd_bc_err } /* USB_BC_STATE_DCP */ +}; + +/****************************************************************************** + * Renesas Abstracted USB host battery charging driver functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_pddetint_process + * Description : PDDETINT process + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_pddetint_process (usb_utr_t * ptr) +{ + uint16_t buf[3]; + + /* PDDETSTS chattering cut */ + /* WAIT_LOOP */ + do + { + buf[0] = hw_usb_read_bcctrl(ptr); + usb_cpu_delay_xms(1); + buf[1] = hw_usb_read_bcctrl(ptr); + usb_cpu_delay_xms(1); + buf[2] = hw_usb_read_bcctrl(ptr); + } while (((buf[0] & USB_PDDETSTS) != (buf[1] & USB_PDDETSTS)) || + ((buf[1] & USB_PDDETSTS) != (buf[2] & USB_PDDETSTS))); + + if (USB_PDDETSTS == (buf[0] & USB_PDDETSTS)) /* VDPSRC Detect */ + { + if (USB_VDMSRCE != (buf[0] & USB_VDMSRCE)) + { + hw_usb_set_vdmsrce(ptr); + } + } + else + + /* VDPSRC Not detect */ + { + if (USB_VDMSRCE == (buf[0] & USB_VDMSRCE)) + { + hw_usb_clear_vdmsrce(ptr); + g_usb_hstd_bc[ptr->ip].pd_detect = USB_BC_PDDET; + } + } +} /* End of function usb_hstd_pddetint_process() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_err + * Description : BC State change function [ERROR] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_err (usb_utr_t * ptr) +{ + (void) *ptr; +} /* End of function usb_hstd_bc_err() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_init_vb + * Description : BC State change function [INIT] [VbusOn] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_init_vb (usb_utr_t * ptr) +{ + #if USB_CFG_DCP == USB_CFG_ENABLE + g_usb_hstd_bc[ptr->ip].state = USB_BC_STATE_DCP; + usb_hstd_bc_dcp_entry(ptr); + #else /* USB_CFG_DCP == USB_CFG_ENABLE */ + g_usb_hstd_bc[ptr->ip].state = USB_BC_STATE_DET; + usb_hstd_bc_det_entry(ptr); + #endif /* USB_CFG_DCP == USB_CFG_ENABLE */ +} /* End of function usb_hstd_bc_init_vb() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_det_at + * Description : BC State change function [DET] [Attach] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_det_at (usb_utr_t * ptr) +{ + usb_hstd_bc_det_exit(ptr); + + if (g_usb_hstd_bc[ptr->ip].pd_detect) + { + g_usb_hstd_bc[ptr->ip].state = USB_BC_STATE_CDP; + usb_hstd_bc_cdp_entry(ptr); + } + else + { + g_usb_hstd_bc[ptr->ip].state = USB_BC_STATE_SDP; + usb_hstd_bc_sdp_entry(ptr); + } +} /* End of function usb_hstd_bc_det_at() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_cdp_dt + * Description : BC State change function [CDP] [Detach] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_cdp_dt (usb_utr_t * ptr) +{ + usb_hstd_bc_cdp_exit(ptr); + g_usb_hstd_bc[ptr->ip].state = USB_BC_STATE_DET; + usb_hstd_bc_det_entry(ptr); +} /* End of function usb_hstd_bc_cdp_dt() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_sdp_dt + * Description : BC State change function [SDP] [Detach] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_sdp_dt (usb_utr_t * ptr) +{ + usb_hstd_bc_sdp_exit(ptr); + g_usb_hstd_bc[ptr->ip].state = USB_BC_STATE_DET; + usb_hstd_bc_det_entry(ptr); +} /* End of function usb_hstd_bc_sdp_dt() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_det_entry + * Description : BC State entry function [DET] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_det_entry (usb_utr_t * ptr) +{ + hw_usb_set_idpsinke(ptr); + hw_usb_hclear_sts_pddetint(ptr); + hw_usb_hset_enb_pddetinte(ptr); +} /* End of function usb_hstd_bc_det_entry() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_det_exit + * Description : BC State exit function [DET] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_det_exit (usb_utr_t * ptr) +{ + hw_usb_hset_enb_pddetinte(ptr); + hw_usb_hclear_sts_pddetint(ptr); + hw_usb_clear_idpsinke(ptr); +} /* End of function usb_hstd_bc_det_exit() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_cdp_entry + * Description : BC State entry function [CDP] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t port : Port number. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_cdp_entry (usb_utr_t * ptr) +{ + (void) *ptr; +} /* End of function usb_hstd_bc_cdp_entry() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_cdp_exit + * Description : BC State exit function [CDP] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_cdp_exit (usb_utr_t * ptr) +{ + g_usb_hstd_bc[ptr->ip].pd_detect = USB_BC_NODET; +} /* End of function usb_hstd_bc_cdp_exit() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_sdp_entry + * Description : BC State entry function [SDP] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_sdp_entry (usb_utr_t * ptr) +{ + (void) *ptr; +} /* End of function usb_hstd_bc_sdp_entry() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_sdp_exit + * Description : BC State exit function [SDP] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_sdp_exit (usb_utr_t * ptr) +{ + (void) *ptr; +} /* End of function usb_hstd_bc_sdp_exit() */ + +/****************************************************************************** + * Function Name : usb_hstd_bc_dcp_entry + * Description : BC State entry function [DCP] + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bc_dcp_entry (usb_utr_t * ptr) +{ + hw_usb_clear_drpd(ptr); + hw_usb_hset_dcpmode(ptr); +} /* End of function usb_hstd_bc_dcp_entry() */ + + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c new file mode 100644 index 0000000000..91c4406850 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c @@ -0,0 +1,520 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Renesas USB FIFO Read/Write Host Driver API functions + ******************************************************************************/ + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE +uint16_t g_usb_hstd_response_counter[USB_NUM_USBIP]; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + +/****************************************************************************** + * Function Name : usb_hstd_ctrl_write_start + * Description : Start data stage of Control Write transfer. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint32_t Bsize : Data Size + * : uint8_t *Table : Data Table Address + * Return : uint16_t : USB_WRITEEND / USB_WRITING + * : : USB_WRITESHRT / USB_FIFOERROR + ******************************************************************************/ +uint16_t usb_hstd_ctrl_write_start (usb_utr_t * ptr, uint32_t Bsize, uint8_t * Table) +{ + uint16_t end_flag; + uint16_t toggle; + + /* PID=NAK & clear STALL */ + usb_cstd_clr_stall(ptr, (uint16_t) USB_PIPE0); + g_usb_hstd_data_cnt[ptr->ip][USB_PIPE0] = Bsize; /* Transfer size set */ + gp_usb_hstd_data_ptr[ptr->ip][USB_PIPE0] = Table; /* Transfer address set */ + + /* DCP Configuration Register (0x5C) */ + hw_usb_write_dcpcfg(ptr, (USB_CNTMDFIELD | USB_DIRFIELD)); + hw_usb_set_sqset(ptr, USB_PIPE0); /* SQSET=1, PID=NAK */ + if (USB_DATAWRCNT == g_usb_hstd_ctsq[ptr->ip]) + { + /* Next stage is Control read data stage */ + toggle = g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->pipectr; + usb_hstd_do_sqtgl(ptr, (uint16_t) USB_PIPE0, toggle); /* Do pipe SQTGL */ + } + + hw_usb_clear_status_bemp(ptr, USB_PIPE0); + + /* Ignore count clear */ + g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0] = (uint16_t) 0; + + /* Host Control sequence */ + end_flag = usb_hstd_write_data(ptr, USB_PIPE0, USB_CUSE); + + switch (end_flag) + { + /* End of data write */ + case USB_WRITESHRT: + { + /* Next stage is Control write status stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_STATUSWR; + + /* Enable Empty Interrupt */ + hw_usb_set_bempenb(ptr, (uint16_t) USB_PIPE0); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(ptr, (uint16_t) USB_PIPE0); + + /* Set BUF */ + usb_cstd_set_buf(ptr, (uint16_t) USB_PIPE0); + break; + } + + /* End of data write (not null) */ + case USB_WRITEEND: + + /* continue */ + /* Continue of data write */ + case USB_WRITING: + { + if (USB_SETUPWR == g_usb_hstd_ctsq[ptr->ip]) + { + /* Next stage is Control read data stage */ + /* Next stage is Control write data stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_DATAWR; + } + else + { + /* Next stage is Control read data stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_DATAWRCNT; + } + + /* Enable Empty Interrupt */ + hw_usb_set_bempenb(ptr, (uint16_t) USB_PIPE0); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(ptr, (uint16_t) USB_PIPE0); + + /* Set BUF */ + usb_cstd_set_buf(ptr, (uint16_t) USB_PIPE0); + break; + } + + /* FIFO access error */ + case USB_FIFOERROR: + { + USB_PRINTF0("### usb_hstd_ctrl_write_start USB_FIFOERROR\n"); + break; + } + + default: + { + break; + } + } + + /* End or Err or Continue */ + return end_flag; +} + +/****************************************************************************** + * End of function usb_hstd_ctrl_write_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_ctrl_read_start + * Description : Start data stage of Control Read transfer. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint32_t Bsize : Data Size + * : uint8_t *Table : Data Table Address + * Return : none + ******************************************************************************/ +void usb_hstd_ctrl_read_start (usb_utr_t * ptr, uint32_t Bsize, uint8_t * Table) +{ + uint16_t toggle; + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + g_usb_hstd_response_counter[ptr->ip] = 0; + + hw_usb_clear_sts_sofr(ptr); + hw_usb_set_intenb(ptr, USB_SOFE); + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + /* PID=NAK & clear STALL */ + usb_cstd_clr_stall(ptr, (uint16_t) USB_PIPE0); + + /* Transfer size set */ + g_usb_hstd_data_cnt[ptr->ip][USB_PIPE0] = Bsize; + + /* Transfer address set */ + gp_usb_hstd_data_ptr[ptr->ip][USB_PIPE0] = Table; + + /* DCP Configuration Register (0x5C) */ + hw_usb_write_dcpcfg(ptr, USB_SHTNAKFIELD); + hw_usb_hwrite_dcpctr(ptr, USB_SQSET); /* SQSET=1, PID=NAK */ + if (USB_DATARDCNT == g_usb_hstd_ctsq[ptr->ip]) + { + /* Next stage is Control read data stage */ + toggle = g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->pipectr; + usb_hstd_do_sqtgl(ptr, (uint16_t) USB_PIPE0, toggle); + } + + /* Host Control sequence */ + if (USB_SETUPRD == g_usb_hstd_ctsq[ptr->ip]) + { + /* Next stage is Control read data stage */ + /* Next stage is Control read data stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_DATARD; + } + else + { + /* Next stage is Control read data stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_DATARDCNT; + } + + /* Ignore count clear */ + g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0] = (uint16_t) 0; + + /* Interrupt enable */ + hw_usb_set_brdyenb(ptr, (uint16_t) USB_PIPE0); /* Enable Ready Interrupt */ + usb_cstd_nrdy_enable(ptr, (uint16_t) USB_PIPE0); /* Enable Not Ready Interrupt */ + usb_cstd_set_buf(ptr, (uint16_t) USB_PIPE0); /* Set BUF */ +} + +/****************************************************************************** + * End of function usb_hstd_ctrl_read_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_status_start + * Description : Start status stage of Control Command. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_status_start (usb_utr_t * ptr) +{ + uint16_t end_flag; + uint8_t buf1[16]; + + /* Interrupt Disable */ + /* BEMP0 Disable */ + hw_usb_clear_bempenb(ptr, (uint16_t) USB_PIPE0); + + /* BRDY0 Disable */ + hw_usb_clear_brdyenb(ptr, (uint16_t) USB_PIPE0); + + /* Transfer size set */ + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->tranlen = g_usb_hstd_data_cnt[ptr->ip][USB_PIPE0]; + + /* Save Data stage transfer size */ + g_usb_hstd_data_cnt_pipe0[ptr->ip] = g_usb_hstd_data_cnt[ptr->ip][USB_PIPE0]; + + /* Branch by the Control transfer stage management */ + switch (g_usb_hstd_ctsq[ptr->ip]) + { + /* Control Read Data */ + case USB_DATARD: + + /* continue */ + /* Control Read Data */ + case USB_DATARDCNT: + { + /* Control read Status */ + g_usb_hstd_ctsq[ptr->ip] = USB_DATARD; + + /* Control write start */ + end_flag = usb_hstd_ctrl_write_start(ptr, (uint32_t) 0, (uint8_t *) &buf1); + if (USB_FIFOERROR == end_flag) + { + USB_PRINTF0("### FIFO access error \n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); /* Control Read/Write End */ + } + else + { + /* Host Control sequence */ + /* Next stage is Control read status stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_STATUSRD; + } + + break; + } + + /* Control Write Data */ + case USB_STATUSWR: + + /* continue */ + /* NoData Control */ + case USB_SETUPNDC: + { + #if defined(USB_CFG_HUVC_USE) + if ((USB_SET_INTERFACE | USB_HOST_TO_DEV | USB_STANDARD | USB_INTERFACE) == hw_usb_read_usbreq(ptr->ip)) + { + usb_cpu_delay_xms((uint16_t) 50); + } + #endif + + /* Control Read Status */ + usb_hstd_ctrl_read_start(ptr, (uint32_t) 0, (uint8_t *) &buf1); + + /* Host Control sequence */ + /* Next stage is Control write status stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_STATUSWR; + break; + } + + default: + { + return; + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_status_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_ctrl_end + * Description : Call the user registered callback function that notifies + * : completion of a control transfer. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t status : Transfer status + * Return : none + ******************************************************************************/ +void usb_hstd_ctrl_end (usb_utr_t * ptr, uint16_t status) +{ + /* Interrupt Disable */ + hw_usb_clear_bempenb(ptr, (uint16_t) USB_PIPE0); /* BEMP0 Disable */ + hw_usb_clear_brdyenb(ptr, (uint16_t) USB_PIPE0); /* BRDY0 Disable */ + hw_usb_clear_nrdyenb(ptr, (uint16_t) USB_PIPE0); /* NRDY0 Disable */ + + usb_cstd_clr_stall(ptr, (uint16_t) USB_PIPE0); /* PID=NAK & clear STALL */ + if (USB_IP0 == ptr->ip) + { + hw_usb_set_mbw(ptr, USB_CUSE, USB0_CFIFO_MBW); + + /* SUREQ=1, SQCLR=1, PID=NAK */ + hw_usb_hwrite_dcpctr(ptr, (uint16_t) (USB_SUREQCLR | USB_SQCLR)); + } + else if (USB_IP1 == ptr->ip) + { + hw_usb_set_mbw(ptr, USB_CUSE, USB1_CFIFO_MBW); + + #if defined(USB_HIGH_SPEED_MODULE) + + /* CSCLR=1, SUREQ=1, SQCLR=1, PID=NAK */ + hw_usb_hwrite_dcpctr(ptr, (uint16_t) ((USB_CSCLR | USB_SUREQCLR) | USB_SQCLR)); + #else /* defined (USB_HIGH_SPEED_MODULE) */ + /* SUREQ=1, SQCLR=1, PID=NAK */ + hw_usb_hwrite_dcpctr(ptr, (uint16_t) (USB_SUREQCLR | USB_SQCLR)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + else + { + /* Non */ + } + + /* CFIFO buffer clear */ + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, USB_FALSE); + hw_usb_set_bclr(ptr, USB_CUSE); /* Clear BVAL */ + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, (uint16_t) USB_ISEL); + hw_usb_set_bclr(ptr, USB_CUSE); /* Clear BVAL */ + + /* Host Control sequence */ + if ((USB_CTRL_READING != status) && (USB_CTRL_WRITING != status)) + { + /* Next stage is idle */ + g_usb_hstd_ctsq[ptr->ip] = USB_IDLEST; + } + + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->status = status; + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->pipectr = hw_usb_read_pipectr(ptr, (uint16_t) USB_PIPE0); + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->errcnt = (uint8_t) g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0]; + + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->ipp = ptr->ipp; + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->ip = ptr->ip; + + /* Callback */ + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]) + { + if (USB_NULL != (g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->complete)) + { + /* Process Done Callback */ + (g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->complete)(g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0], USB_NULL, + USB_NULL); + } + } + + #if (BSP_CFG_RTOS == 0) + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0] = (usb_utr_t *) USB_NULL; + #else /* (BSP_CFG_RTOS == 0) */ + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0] = (usb_utr_t *) USB_NULL; + usb_cstd_pipe0_msg_re_forward(ptr->ip); /* Get PIPE0 Transfer wait que and Message send to HCD */ + #endif /* #if (BSP_CFG_RTOS == 0) */ + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + hw_usb_clear_enb_sofe(ptr); + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ +} + +/****************************************************************************** + * End of function usb_hstd_ctrl_end + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_setup_start + * Description : Start control transfer setup stage. (Set global function re- + * : quired to start control transfer, and USB register). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_setup_start (usb_utr_t * ptr) +{ + uint16_t segment; + uint16_t dir; + uint16_t setup_req; + uint16_t setup_val; + uint16_t setup_indx; + uint16_t setup_leng; + uint16_t * p_setup; + + segment = (uint16_t) (g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->segment); + p_setup = g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->p_setup; + + setup_req = *p_setup++; /* Set Request data */ + setup_val = *p_setup++; /* Set wValue data */ + setup_indx = *p_setup++; /* Set wIndex data */ + setup_leng = *p_setup++; /* Set wLength data */ + + /* Max Packet Size + Device Number select */ + hw_usb_write_dcpmxps(ptr, g_usb_hstd_dcp_register[ptr->ip][*p_setup]); + + /* Transfer Length check */ + + /* Check Last flag */ + if ((uint16_t) USB_TRAN_END == segment) + { + if (g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->tranlen < setup_leng) + { + setup_leng = (uint16_t) g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->tranlen; + } + } + + if (setup_leng < g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->tranlen) + { + g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]->tranlen = (uint32_t) setup_leng; + } + + /* Control sequence setting */ + dir = (uint16_t) (setup_req & USB_BMREQUESTTYPEDIR); + + /* Check wLength field */ + if (0 == setup_leng) + { + /* Check Dir field */ + if (0 == dir) + { + /* Check Last flag */ + if ((uint16_t) USB_TRAN_END == segment) + { + /* Next stage is NoData control status stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_SETUPNDC; + } + else + { + /* Error */ + g_usb_hstd_ctsq[ptr->ip] = USB_IDLEST; + } + } + else + { + /* Error */ + g_usb_hstd_ctsq[ptr->ip] = USB_IDLEST; + } + } + else + { + /* Check Dir field */ + if (0 == dir) + { + /* Check Last flag */ + if ((uint16_t) USB_TRAN_END == segment) + { + /* Next stage is Control Write data stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_SETUPWR; + } + else + { + /* Next stage is Control Write data stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_SETUPWRCNT; + } + } + else + { + /* Check Last flag */ + if ((uint16_t) USB_TRAN_END == segment) + { + /* Next stage is Control read data stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_SETUPRD; + } + else + { + /* Next stage is Control read data stage */ + g_usb_hstd_ctsq[ptr->ip] = USB_SETUPRDCNT; + } + } + } + + /* Control transfer idle stage? */ + if (USB_IDLEST == g_usb_hstd_ctsq[ptr->ip]) + { + /* Control Read/Write End */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_STOP); + } + else + { + /* SETUP request set */ + /* Set Request data */ + hw_usb_hwrite_usbreq(ptr, setup_req); + + hw_usb_hset_usbval(ptr, setup_val); + hw_usb_hset_usbindx(ptr, setup_indx); + hw_usb_hset_usbleng(ptr, setup_leng); + + /* Ignore count clear */ + g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0] = (uint16_t) 0; + + hw_usb_hclear_sts_sign(ptr); + hw_usb_hclear_sts_sack(ptr); + hw_usb_hset_enb_signe(ptr); + hw_usb_hset_enb_sacke(ptr); + hw_usb_hset_sureq(ptr); + } +} + +/****************************************************************************** + * End of function usb_hstd_setup_start + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c new file mode 100644 index 0000000000..8f107cd7a7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c @@ -0,0 +1,3511 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HCDC_USE) + #include "r_usb_hcdc_api.h" + + #endif /* defined(USB_CFG_HCDC_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HHID_USE) + #include "r_usb_hhid_api.h" + #endif /* defined(USB_CFG_HHID_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HMSC_USE) + #include "r_usb_hmsc_api.h" + + #endif /* defined(USB_CFG_HMSC_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if defined(USB_CFG_PCDC_USE) + #include "r_usb_pcdc_api.h" + +#endif /* defined(USB_CFG_PCDC_USE) */ + +#if defined(USB_CFG_PPRN_USE) + #include "r_usb_pprn_api.h" + +#endif /* defined(USB_CFG_PPRN_USE) */ + +#if defined(USB_CFG_PMSC_USE) + #include "r_usb_pmsc_api.h" + +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "../hw/inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +#if (BSP_CFG_RTOS != 0) + #include "inc/r_usb_cstd_rtos.h" +#endif /* #if (BSP_CFG_RTOS != 0) */ + +#if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_OTG_USE) + #include "ux_api.h" + #if defined(USB_CFG_HCDC_USE) + #include "ux_host_class_cdc_acm.h" + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) + #include "ux_host_class_hid.h" + #include "ux_host_class_hid_keyboard.h" + #include "ux_host_class_hid_mouse.h" + #include "ux_host_class_hid_remote_control.h" + #endif /* defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HMSC_USE) + #include "ux_host_class_storage.h" + #endif /* defined(USB_CFG_HMSC_USE) */ + #endif /* defined(USB_CFG_OTG_USE) */ +#endif /* #if (BSP_CFG_RTOS != 0) */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + #define USB_RESPONSE_COUNTER_VALUE (6000U) + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + #if defined(USB_CFG_HVND_USE) + #define USB_EP_PIPE_NUM (9) + #define USB_EP_TBL_WSIZE ((USB_EPL * USB_EP_PIPE_NUM) + 1) + #endif /* defined(USB_CFG_HVND_USE) */ + + #define USB_VALUE_FFH (0xFF) + #define USB_VALUE_3000 (3000) + #define USB_VALUE_100U (100U) + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ +static uint16_t usb_shstd_clr_stall_pipe[USB_NUM_USBIP]; +static uint16_t usb_shstd_clr_stall_request[USB_NUM_USBIP][5]; +static usb_utr_t usb_shstd_clr_stall_ctrl[USB_NUM_USBIP]; + + #if defined(USB_CFG_HVND_USE) +static usb_er_t usb_hvnd_set_pipe_registration(usb_utr_t * ptr, uint16_t dev_addr); +static void usb_hvnd_configured(usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2); +static void usb_hvnd_detach(usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2); +static void usb_hvnd_enumeration(usb_clsinfo_t * mess, uint16_t ** table); +static void usb_hvnd_pipe_info(usb_utr_t * p_utr, uint8_t * table, uint16_t speed, uint16_t length); +static uint8_t usb_hvnd_get_pipe_no(usb_utr_t * p_utr, uint8_t type, uint8_t dir); +static uint8_t usb_hvnd_make_pipe_reg_info(usb_utr_t * p_utr, + uint16_t address, + uint16_t speed, + uint8_t * descriptor, + usb_pipe_table_reg_t * pipe_table_work); + + #endif /* defined(USB_CFG_HVND_USE) */ + +static void usb_hstd_set_submitutr(usb_utr_t * ptr); +static void usb_hstd_set_retransfer(usb_utr_t * ptr, uint16_t pipe); + + #if (BSP_CFG_RTOS == 0) +static usb_cb_t usb_shstd_clr_stall_call; +static void usb_hstd_clr_stall_result(usb_utr_t * ptr, uint16_t data1, uint16_t data2); + + #endif /* (BSP_CFG_RTOS == 0) */ + + #if defined(USB_CFG_OTG_USE) +static void usb_hstd_otg_mode_to_peri(usb_utr_t * p_utr); +static void usb_pdriver_init_otg(void); +extern void usb_pstd_ux_descriptor_to_basic(usb_cfg_t * p_cfg); + +extern volatile uint32_t g_usb_open_class[]; +extern usb_cfg_t * g_p_usb_otg_cfg; +extern usb_descriptor_t g_usbx_descriptor; + #endif /* defined(USB_CFG_OTG_USE) */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE +extern const uint16_t USB_CFG_TPL_TABLE[]; + #endif /* #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + +/* Device driver (registration) */ +usb_hcdreg_t g_usb_hstd_device_drv[USB_NUM_USBIP][USB_MAXDEVADDR + 1U]; + +/* Root port, status, config num, interface class, speed, */ +volatile uint16_t g_usb_hstd_device_info[USB_NUM_USBIP][USB_MAXDEVADDR + 1U][8U]; +uint16_t g_usb_hstd_remort_port[USB_NUM_USBIP]; + +/* Control transfer stage management */ +uint16_t g_usb_hstd_ctsq[USB_NUM_USBIP]; + +/* Manager mode */ +uint16_t g_usb_hstd_mgr_mode[USB_NUM_USBIP]; + +/* DEVSEL & DCPMAXP (Multiple device) */ +uint16_t g_usb_hstd_dcp_register[USB_NUM_USBIP][USB_MAXDEVADDR + 1U]; + +/* Device address */ +uint16_t g_usb_hstd_device_addr[USB_NUM_USBIP]; + +/* Reset handshake result */ +uint16_t g_usb_hstd_device_speed[USB_NUM_USBIP]; + +/* Device driver number */ +uint16_t g_usb_hstd_device_num[USB_NUM_USBIP]; + +/* Ignore count */ +uint16_t g_usb_hstd_ignore_cnt[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; + +/* USB data transfer */ +/* PIPEn Buffer counter */ +uint32_t g_usb_hstd_data_cnt[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; +uint32_t g_usb_hstd_data_cnt_pipe0[USB_NUM_USBIP]; + +/* PIPEn Buffer pointer(8bit) */ +uint8_t * gp_usb_hstd_data_ptr[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; + +/* Message pipe */ +usb_utr_t * g_p_usb_hstd_pipe[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; + +/* Hi-speed enable */ +uint16_t g_usb_hstd_hs_enable[USB_NUM_USBIP]; +usb_ctrl_trans_t g_usb_ctrl_request[USB_NUM_USBIP][USB_MAXDEVADDR + 1]; + + #if defined(USB_CFG_OTG_USE) +volatile uint16_t g_usb_otg_intsts1 = 0; + #endif /* defined(USB_CFG_OTG_USE) */ + + #if BSP_CFG_RTOS == 0 +uint16_t g_usb_hstd_pipe_request[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; + #endif /* BSP_CFG_RTOS == 0 */ + + #if defined(USB_CFG_HVND_USE) + +/* Target Peripheral List */ +const uint16_t g_usb_apl_devicetpl[] = +{ + USB_CFG_TPLCNT, /* Number of list */ + 0, /* Reserved */ + USB_CFG_TPL /* Vendor ID, Product ID */ +}; + #endif /* defined(USB_CFG_HVND_USE) */ + + #if (BSP_CFG_RTOS != 0) +usb_hdl_t g_usb_hstd_sus_res_task_id[USB_NUM_USBIP]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + #if defined(USB_CFG_OTG_USE) +uint8_t g_usb_otg_suspend_flag[USB_NUM_USBIP] = +{ + USB_NO, + #if USB_NUM_USBIP == 2 + USB_NO, + #endif /* USB_NUM_USBIP == 2 */ +}; + +uint8_t g_is_A_device[USB_NUM_USBIP] = +{ + USB_NO, + #if USB_NUM_USBIP == 2 + USB_NO, + #endif /* USB_NUM_USBIP == 2 */ +}; + +uint8_t g_is_A_cable_detach[USB_NUM_USBIP] = +{ + USB_NO, + #if USB_NUM_USBIP == 2 + USB_NO, + #endif /* USB_NUM_USBIP == 2 */ +}; + +extern UINT usb_host_usbx_initialize(UX_HCD * hcd); + + #endif /* defined(USB_CFG_OTG_USE) */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE +extern usb_compliance_cb_t * g_usb_compliance_callback[USB_NUM_USBIP]; + #endif /* #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + +/****************************************************************************** + * Renesas USB Host Driver functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_dev_descriptor + * Description : Returns buffer header pointer to fetch device descriptor. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : uint8_t * : Device Descriptor Pointer + ******************************************************************************/ +uint8_t * usb_hstd_dev_descriptor (usb_utr_t * ptr) +{ + return (uint8_t *) &g_usb_hstd_device_descriptor[ptr->ip]; +} + +/****************************************************************************** + * End of function usb_hstd_dev_descriptor + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_con_descriptor + * Description : Returns buffer header pointer that includes the configuration + * : descriptor. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : uint8_t * : Configuration Descriptor Pointer + ******************************************************************************/ +uint8_t * usb_hstd_con_descriptor (usb_utr_t * ptr) +{ + return (uint8_t *) &g_usb_hstd_config_descriptor[ptr->ip]; +} + +/****************************************************************************** + * End of function usb_hstd_con_descriptor + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_transfer_start_req + * Description : Send a request for data transfer to HCD (Host Control Driver) + * : using the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : usb_er_t : USB_OK/USB_QOVR/USB_ERROR + ******************************************************************************/ +usb_er_t usb_hstd_transfer_start_req (usb_utr_t * ptr) +{ + usb_er_t err; + uint16_t pipenum; + uint16_t devsel; + #if (BSP_CFG_RTOS == 0) + uint16_t connect_inf; + #else /* (BSP_CFG_RTOS == 0) */ + usb_utr_t * p_tran_data; + #endif /* BSP_CFG_RTOS == 0 */ + + pipenum = ptr->keyword; + + if (USB_PIPE0 == pipenum) + { + devsel = (uint16_t) (ptr->p_setup[4] << USB_DEVADDRBIT); + } + else + { + /* Get device address from pipe number */ + devsel = usb_hstd_get_devsel(ptr, pipenum); + } + + if ((USB_DEVICE_0 == devsel) && (USB_PIPE0 != pipenum)) + { + USB_PRINTF1("### usb_hstd_transfer_start_req not configured %x\n", devsel); + + return USB_ERROR; + } + + ptr->msghead = (usb_mh_t) USB_NULL; + ptr->msginfo = USB_MSG_HCD_SUBMITUTR; + + if (USB_MAX_PIPE_NO < pipenum) + { + USB_PRINTF1("### usb_hstd_transfer_start_req PipeNo ERROR pipenum:%d\n", pipenum); + + return USB_ERROR; + } + + #if (BSP_CFG_RTOS == 0) + if (USB_ON == g_usb_hstd_pipe_request[ptr->ip][pipenum]) + { + return USB_QOVR; + } + + /* Pipe Transfer Process check */ + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][pipenum]) + { + /* Check PIPE TYPE */ + if (usb_cstd_get_pipe_type(ptr, pipenum) != USB_TYPFIELD_ISO) + { + USB_PRINTF1("### usb_hstd_transfer_start_req overlaps %d\n", pipenum); + + return USB_QOVR; + } + } + + /* Get device speed from device address */ + connect_inf = usb_hstd_get_dev_speed(ptr, devsel); + if (USB_NOCONNECT == connect_inf) + { + USB_PRINTF1("### usb_hstd_transfer_start_req not connect %x\n", devsel); + + return USB_ERROR; + } + + /* Send message */ + err = USB_SND_MSG(USB_HCD_MBX, (usb_msg_t *) ptr); + if (USB_OK == err) + { + g_usb_hstd_pipe_request[ptr->ip][pipenum] = USB_ON; + } + else + { + USB_PRINTF1("### usb_hstd_transfer_start_req snd_msg error (%ld)\n", err); + } + + #elif (BSP_CFG_RTOS == 1) /* (BSP_CFG_RTOS == 0) */ + err = USB_PGET_BLK(1, &p_tran_data, ptr->ip); + if (TX_SUCCESS != err) + { + USB_PRINTF0("### usb_hstd_transfer_start_req USB_PGET_BLK ERROR %x\n"); + + return USB_ERROR; + } + + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 0) */ + p_tran_data = (usb_utr_t *) pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == p_tran_data) + { + USB_PRINTF0("### usb_hstd_transfer_start_req pvPortMalloc ERROR\n"); + + return USB_ERROR; + } + #endif /* (BSP_CFG_RTOS == 0) */ + + #if (BSP_CFG_RTOS != 0) + *p_tran_data = *ptr; + if ((0 != ptr->p_setup) && (USB_PIPE0 == pipenum)) + { + p_tran_data->setup_data[0] = ptr->p_setup[0]; + p_tran_data->setup_data[1] = ptr->p_setup[1]; + p_tran_data->setup_data[2] = ptr->p_setup[2]; + p_tran_data->setup_data[3] = ptr->p_setup[3]; + p_tran_data->setup_data[4] = ptr->p_setup[4]; + p_tran_data->p_setup = (uint16_t *) &p_tran_data->setup_data; + } + + #if (BSP_CFG_RTOS == 1) /* (BSP_CFG_RTOS == 0) */ + p_tran_data->cur_task_hdl = tx_thread_identify(); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 0) */ + p_tran_data->cur_task_hdl = xTaskGetCurrentTaskHandle(); + #endif /* (BSP_CFG_RTOS == 2)*/ + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + if (0 != ptr->p_transfer_tx) + { + p_tran_data->p_transfer_tx = ptr->p_transfer_tx; + } + else + { + p_tran_data->p_transfer_tx = 0; + } + + if (0 != ptr->p_transfer_rx) + { + p_tran_data->p_transfer_rx = ptr->p_transfer_rx; + } + else + { + p_tran_data->p_transfer_rx = 0; + } + #endif + + /* Send message */ + err = USB_SND_MSG(USB_HCD_MBX, (usb_msg_t *) p_tran_data); + if (USB_OK != err) + { + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, p_tran_data); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + vPortFree(p_tran_data); + #endif /* (BSP_CFG_RTOS == 1) */ + } + #endif /* (BSP_CFG_RTOS != 0) */ + + return err; +} + +/****************************************************************************** + * End of function usb_hstd_transfer_start_req + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_device_resume + * Description : Send request for RESUME signal output to USB device to MGR task. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Argument : uint16_t devaddr : Device Address + * Return : none + ******************************************************************************/ +void usb_hstd_device_resume (usb_utr_t * ptr, uint16_t devaddr) +{ + usb_hstd_mgr_snd_mbx(ptr, (uint16_t) USB_MSG_HCD_RESUME, devaddr, (uint16_t) 0U); +} + +/****************************************************************************** + * End of function usb_hstd_device_resume + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_hcd_snd_mbx + * Description : Send specified message to HCD (Host Control Driver) task. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t msginfo : Message info.. + * : uint16_t dat : Pipe no. + * : uint16_t *adr : Address. + * : usb_cb_t callback: Callback function pointer. + * Return : usb_er_t : USB_OK etc. + ******************************************************************************/ +usb_er_t usb_hstd_hcd_snd_mbx (usb_utr_t * ptr, uint16_t msginfo, uint16_t dat, uint16_t * adr, usb_cb_t callback) +{ + usb_mh_t p_blf; + usb_er_t err; + usb_er_t err2; + usb_hcdinfo_t * hp; + + /* Get memory pool blk */ + err = USB_PGET_BLK(USB_HCD_MPL, &p_blf, ptr->ip); + if (USB_OK == err) + { + hp = (usb_hcdinfo_t *) p_blf; + hp->msghead = (usb_mh_t) USB_NULL; + hp->msginfo = msginfo; + hp->keyword = dat; + hp->p_tranadr = adr; + hp->complete = callback; + hp->ipp = ptr->ipp; + hp->ip = ptr->ip; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + hp->p_transfer_rx = ptr->p_transfer_rx; + hp->p_transfer_tx = ptr->p_transfer_tx; + #endif /* #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + #if (BSP_CFG_RTOS != 0) + hp->cur_task_hdl = ptr->cur_task_hdl; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + /* Send message */ + err = USB_SND_MSG(USB_HCD_MBX, (usb_msg_t *) hp); + if (USB_OK != err) + { + USB_PRINTF1("### hHcdSndMbx snd_msg error (%ld)\n", err); + err2 = USB_REL_BLK(USB_HCD_MPL, (usb_mh_t) hp); + if (USB_OK != err2) + { + USB_PRINTF1("### hHcdSndMbx rel_blk error (%ld)\n", err2); + } + } + } + else + { + /* Error */ + /* WAIT_LOOP */ + while (1) + { + /* error */ + } + } + + return err; +} + +/****************************************************************************** + * End of function usb_hstd_hcd_snd_mbx + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_mgr_snd_mbx + * Description : Send the message to MGR(Manager) task + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t msginfo : Message info. + * : uint16_t dat : Port no. + * : uint16_t res : Result + * Return : none + ******************************************************************************/ +void usb_hstd_mgr_snd_mbx (usb_utr_t * ptr, uint16_t msginfo, uint16_t dat, uint16_t res) +{ + usb_mh_t p_blf; + usb_er_t err; + usb_er_t err2; + usb_mgrinfo_t * mp; + + /* Get memory pool blk */ + err = USB_PGET_BLK(USB_MGR_MPL, &p_blf, ptr->ip); + if (USB_OK == err) + { + mp = (usb_mgrinfo_t *) p_blf; + mp->msghead = (usb_mh_t) USB_NULL; + mp->msginfo = msginfo; + mp->keyword = dat; + mp->result = res; + mp->ipp = ptr->ipp; + mp->ip = ptr->ip; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + mp->p_transfer_rx = ptr->p_transfer_rx; + mp->p_transfer_tx = ptr->p_transfer_tx; + #endif + #if (BSP_CFG_RTOS != 0) + mp->cur_task_hdl = ptr->cur_task_hdl; + #endif /* #if (BSP_CFG_RTOS != 0)*/ + + /* Send message */ + err = USB_SND_MSG(USB_MGR_MBX, (usb_msg_t *) mp); + if (USB_OK != err) + { + USB_PRINTF1("### hMgrSndMbx snd_msg error (%ld)\n", err); + err2 = USB_REL_BLK(USB_MGR_MPL, (usb_mh_t) mp); + if (USB_OK != err2) + { + USB_PRINTF1("### hMgrSndMbx rel_blk error (%ld)\n", err2); + } + } + } + else + { + /* Error */ + /* WAIT_LOOP */ + while (1) + { + /* error */ + } + } +} + +/****************************************************************************** + * End of function usb_hstd_mgr_snd_mbx + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_hcd_rel_mpl + * Description : Release the secured memory block. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t n : Error no. + * Return : none + ******************************************************************************/ +void usb_hstd_hcd_rel_mpl (usb_utr_t * ptr, uint16_t n) +{ + usb_er_t err; + + (void) n; + + /* Memory Pool Release */ + err = USB_REL_BLK(USB_HCD_MPL, (usb_mh_t) ptr); + if (USB_OK != err) + { + USB_PRINTF1("### USB HCD rel_blk error: %d\n", n); + } +} + +/****************************************************************************** + * End of function usb_hstd_hcd_rel_mpl + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_suspend + * Description : Request suspend for USB device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_suspend (usb_utr_t * ptr) +{ + usb_hcdinfo_t * hp; + + /* Control transfer idle stage ? */ + if (USB_IDLEST == g_usb_hstd_ctsq[ptr->ip]) + { + /* USB suspend process */ + usb_hstd_suspend_process(ptr); + usb_hstd_chk_clk(ptr, (uint16_t) USB_SUSPENDED); /* Check clock */ + hp = (usb_hcdinfo_t *) ptr; /* Callback */ + (hp->complete)(ptr, USB_NULL, ptr->msginfo); + } + else + { + /* 1ms wait */ + usb_cpu_delay_xms((uint16_t) 1); + + /* Change device state request */ + usb_hstd_hcd_snd_mbx(ptr, ptr->msginfo, USB_NULL, (uint16_t *) 0, &usb_hstd_status_result); + } +} + +/****************************************************************************** + * End of function usb_hstd_suspend + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_set_submitutr + * Description : Submit utr: Get the device address via the specified pipe num- + * : ber and do a USB transfer. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +static void usb_hstd_set_submitutr (usb_utr_t * ptr) +{ + uint16_t pipenum; + uint16_t devsel; + uint16_t connect_inf; + uint16_t end_flag; + usb_utr_t * pp; + + pipenum = ptr->keyword; + #if BSP_CFG_RTOS == 0 + g_p_usb_hstd_pipe[ptr->ip][pipenum] = ptr; + g_usb_hstd_pipe_request[ptr->ip][pipenum] = USB_OFF; + #endif /* BSP_CFG_RTOS == 0 */ + + /* Get device address from pipe number */ + if (USB_PIPE0 == pipenum) + { + devsel = (uint16_t) (ptr->p_setup[4] << USB_DEVADDRBIT); + } + else + { + /* Get device address from pipe number */ + devsel = usb_hstd_get_devsel(ptr, pipenum); + } + + /* Get device speed from device address */ + connect_inf = usb_hstd_get_dev_speed(ptr, devsel); + if (USB_NOCONNECT == connect_inf) + { + #if (BSP_CFG_RTOS != 0) + if (USB_PIPE0 == pipenum) + { + usb_cstd_pipe0_msg_clear(ptr, ptr->p_setup[4]); + } + else + { + usb_cstd_pipe_msg_clear(ptr, pipenum); + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + if (USB_PIPE0 == pipenum) + { + /* Control Read/Write End */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); + } + else + { + /* End of data transfer (IN/OUT) */ + usb_hstd_forced_termination(ptr, pipenum, (uint16_t) USB_DATA_ERR); + } + #endif /* #if (BSP_CFG_RTOS != 0) */ + + return; + } + + #if (BSP_CFG_RTOS != 0) + + /* Pipe Transfer Process check */ + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][pipenum]) + { + if (USB_PIPE0 == pipenum) + { + usb_cstd_pipe0_msg_forward(ptr, ptr->p_setup[4]); + } + else + { + usb_cstd_pipe_msg_forward(ptr, pipenum); + } + + return; + } + #endif /* #if (BSP_CFG_RTOS != 0) */ + + #if (BSP_CFG_RTOS != 0) + g_p_usb_hstd_pipe[ptr->ip][pipenum] = ptr; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + if ((USB_DEVICE_0 == devsel) && (USB_PIPE0 != pipenum)) + { + usb_hstd_forced_termination(ptr, pipenum, (uint16_t) USB_DATA_ERR); + + return; + } + + /* Control Transfer */ + if (USB_PIPE0 == pipenum) + { + /* Control transfer idle stage ? */ + if (USB_IDLEST == g_usb_hstd_ctsq[ptr->ip]) + { + usb_hstd_setup_start(ptr); + } + /* Control Read Data */ + else if (USB_DATARDCNT == g_usb_hstd_ctsq[ptr->ip]) + { + pp = g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]; + usb_hstd_ctrl_read_start(ptr, pp->tranlen, (uint8_t *) pp->p_tranadr); /* Control read start */ + } + /* Control Write Data */ + else if (USB_DATAWRCNT == g_usb_hstd_ctsq[ptr->ip]) + { + pp = g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]; + + /* Control write start */ + end_flag = usb_hstd_ctrl_write_start(ptr, pp->tranlen, (uint8_t *) pp->p_tranadr); + if (USB_FIFOERROR == end_flag) + { + USB_PRINTF0("### FIFO access error \n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); /* Control Read/Write End */ + } + } + else + { + USB_PRINTF0("### Control transfer sequence error \n"); + + /* Control Read/Write End */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); + } + } + else + { + usb_hstd_set_retransfer(ptr, pipenum); /* Data Transfer */ + } +} + +/****************************************************************************** + * End of function usb_hstd_set_submitutr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_set_retransfer + * Description : Start IN/OUT transfer based on the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number + * Return : none + ******************************************************************************/ +static void usb_hstd_set_retransfer (usb_utr_t * ptr, uint16_t pipe) +{ + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Data Transfer */ + if (usb_cstd_get_pipe_dir(ptr, pipe) == USB_DIR_H_IN) + { + /* IN Transfer */ + usb_hstd_receive_start(ptr, pipe); + } + else + { + /* OUT Transfer */ + usb_hstd_send_start(ptr, pipe); + } +} + +/****************************************************************************** + * End of function usb_hstd_set_retransfer + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_bus_int_disable + * Description : Disable USB Bus Interrupts OVRCR, ATTCH, DTCH, and BCHG. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_bus_int_disable (usb_utr_t * ptr) +{ + /* ATTCH interrupt disable */ + usb_hstd_attch_disable(ptr); + + /* DTCH interrupt disable */ + usb_hstd_dtch_disable(ptr); + + /* BCHG interrupt disable */ + usb_hstd_bchg_disable(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_bus_int_disable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_interrupt + * Description : Execute appropriate process depending on which USB interrupt + * : occurred. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +static void usb_hstd_interrupt (usb_utr_t * ptr) +{ + uint16_t intsts; + uint16_t end_flag; + usb_utr_t * pp; + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + usb_compliance_t disp_param; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + intsts = ptr->keyword; + + /* bitsts = ptr->status;*/ + switch (intsts) + { + /***** Processing PIPE0-MAX_PIPE_NO data *****/ + case USB_INT_BRDY: + { + usb_hstd_brdy_pipe(ptr); + break; + } + + case USB_INT_BEMP: + { + usb_hstd_bemp_pipe(ptr); + break; + } + + case USB_INT_NRDY: + { + usb_hstd_nrdy_pipe(ptr); + break; + } + + /***** Processing Setup transaction *****/ + case USB_INT_SACK: + { + switch (g_usb_hstd_ctsq[ptr->ip]) + { + case USB_SETUPRD: + + /* Next stage to Control read data */ + /* continue */ + case USB_SETUPRDCNT: + { + /* Next stage to Control read data */ + pp = g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]; + + /* Control read start */ + usb_hstd_ctrl_read_start(ptr, pp->tranlen, (uint8_t *) pp->p_tranadr); + break; + } + + case USB_SETUPWR: + + /* Next stage to Control Write data */ + /* continue */ + case USB_SETUPWRCNT: + { + /* Next stage to Control Write data */ + pp = g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]; + + /* Control write start */ + end_flag = usb_hstd_ctrl_write_start(ptr, pp->tranlen, (uint8_t *) pp->p_tranadr); + if (USB_FIFOERROR == end_flag) + { + USB_PRINTF0("### FIFO access error \n"); + + /* Control Read/Write End */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); + } + + break; + } + + case USB_SETUPNDC: + { + /* Next stage to Control write no data */ + usb_hstd_status_start(ptr); + break; + } + + default: + { + break; + } + } + + break; + } + + case USB_INT_SIGN: + { + USB_PRINTF0("***SIGN\n"); + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + disp_param.status = USB_COMPLIANCETEST_SETUP_ERR; + disp_param.pid = USB_NULL; + disp_param.vid = USB_NULL; + (*g_usb_compliance_callback[ptr->ip])((void *) &disp_param); + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + /* Ignore count */ + g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0]++; + USB_PRINTF2("### IGNORE Pipe %d is %d times (Setup) \n", + USB_PIPE0, + g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0]); + if (USB_PIPEERROR == g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0]) + { + /* Setup Device Ignore count over */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); + } + else + { + /* Interrupt enable */ + /* 5ms wait */ + usb_cpu_delay_xms((uint16_t) 5U); + + /* Status Clear */ + hw_usb_hclear_sts_sign(ptr); + hw_usb_hclear_sts_sack(ptr); + + /* Setup Ignore,Setup Acknowledge enable */ + hw_usb_hset_enb_signe(ptr); + hw_usb_hset_enb_sacke(ptr); + + /* SETUP request send */ + /* Send SETUP request */ + hw_usb_hset_sureq(ptr); + } + + break; + } + + /***** Processing rootport0 *****/ + case USB_INT_OVRCR0: + { + #if !defined(USB_CFG_OTG_USE) + + /* Port0 OVCR interrupt function */ + usb_hstd_ovrcr0function(ptr); + #endif /* !defined(USB_CFG_OTG_USE)*/ + break; + } + + case USB_INT_EOFERR0: + { + /* User program */ + break; + } + + case USB_INT_ATTCH0: + { + /* Port0 ATCH interrupt function */ + usb_hstd_attach_process(ptr); + #if defined(USB_CFG_OTG_USE) + (*g_p_otg_callback[ptr->ip])(UX_OTG_MODE_HOST); + #endif /* defined(USB_CFG_OTG_USE) */ + break; + } + + case USB_INT_BCHG0: + { + USB_PRINTF0("BCHG int port0\n"); + #if defined(USB_CFG_OTG_USE) + ptr->ipp->INTENB1 &= (uint16_t) ~USB_BCHGE; + ptr->ipp->INTENB1 |= USB_ATTCHE; + hw_usb_set_vbout(ptr); + #else + + /* Port0 BCHG interrupt function */ + usb_hstd_bchg0function(ptr); + #endif + break; + } + + case USB_INT_DTCH0: + { + USB_PRINTF0("DTCH int port0\n"); + #if defined(USB_CFG_OTG_USE) + { + CHAR * p_name; + UINT state; + ULONG run_count; + UINT priority; + UINT threshold; + ULONG time_slice; + TX_THREAD * p_thread; + TX_THREAD * p_next_thread; + TX_THREAD * p_suspend_thread; + + p_thread = &_ux_system_host->ux_system_host_hnp_polling_thread; + tx_thread_info_get(p_thread, + &p_name, + &state, + &run_count, + &priority, + &threshold, + &time_slice, + &p_next_thread, + &p_suspend_thread); + if ((TX_READY == state) || (TX_SLEEP == state) || (TX_SEMAPHORE_SUSP == state)) + { + tx_thread_terminate(p_thread); + tx_thread_reset(p_thread); + } + } + + if (USB_ON == g_usb_otg_hnp_process[ptr->ip]) + { + /* USB detach process */ + usb_hstd_detach_process(ptr); + + usb_hstd_otg_mode_to_peri(ptr); + + g_usb_usbmode[ptr->ip] = USB_MODE_PERI; + + (*g_p_otg_callback[ptr->ip])(UX_OTG_MODE_SLAVE); + + if (USB_YES == g_is_A_device[ptr->ip]) + { + if (USB_IP0 == ptr->ip) + { + tx_timer_activate(&g_usb_otg_detach_timer); + } + + #if USB_NUM_USBIP == 2 + else + { + tx_timer_activate(&g_usb2_otg_detach_timer); + } + #endif /* USB_NUM_USBIP == 2 */ + } + + g_usb_otg_hnp_process[ptr->ip] = USB_OFF; + } + else + #endif /* defined(USB_CFG_OTG_USE) */ + { + /* USB detach process */ + usb_hstd_detach_process(ptr); + #if defined(USB_CFG_OTG_USE) + if (USB_YES == g_is_A_device[ptr->ip]) + { + if (USB_YES == g_is_A_cable_detach[ptr->ip]) + { + g_is_A_cable_detach[ptr->ip] = USB_NO; + usb_hstd_otg_mode_to_peri(ptr); + g_is_A_device[ptr->ip] = USB_NO; + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; + } + else + { + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_A; + } + } + else + { + /* Detached B-cable */ + usb_hstd_otg_mode_to_peri(ptr); + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; + } + (*g_p_otg_callback[ptr->ip])(UX_OTG_MODE_IDLE); + #endif /* defined(USB_CFG_OTG_USE) */ + } + + break; + } + + #if USB_CFG_BC == USB_CFG_ENABLE + case USB_INT_PDDETINT0: + { + #if defined(USB_HIGH_SPEED_MODULE) + + /* Port0 PDDETINT interrupt function */ + if (USB_IP1 == ptr->ip) + { + usb_hstd_pddetint_process(ptr); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + + case USB_INT_VBINT: + { + /* User program */ + hw_usb_clear_enb_vbse(ptr); + break; + } + + case USB_INT_SOFR: + { + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + g_usb_hstd_response_counter[ptr->ip]++; + if (USB_RESPONSE_COUNTER_VALUE == g_usb_hstd_response_counter[ptr->ip]) + { + hw_usb_clear_enb_sofe(ptr); + disp_param.status = USB_COMPLIANCETEST_NORES; + disp_param.pid = USB_NULL; + disp_param.vid = USB_NULL; + (*g_usb_compliance_callback[ptr->ip])((void *) &disp_param); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_STOP); + } + + #else /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + /* User program */ + hw_usb_clear_enb_sofe(ptr); + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + break; + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + case USB_INT_DXFIFO: + { + usb_cstd_dma_stop(ptr, ptr->status); /* Stop DMA,FIFO access */ + usb_cstd_dma_send_continue(ptr, ptr->status); + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + #if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_OTG_USE) + case USB_INT_OTG_HOST_INIT: + { + usb_class_internal_t type; + + ptr->ipp = usb_hstd_get_usb_ip_adr((uint16_t) ptr->ip); + + if (USB_MODE_PERI == g_usb_usbmode[ptr->ip]) + { +/**********************************/ +/* Peri UninItialization Processing */ +/**********************************/ + usb_module_register_clear(ptr->ip); + + usb_pstd_driver_release(); /* Clear the information registered in the structure usb_pcdreg_t. */ + usb_pstd_clr_pipe_table(ptr->ip); + +/**********************************/ +/* Host InItialization Processing */ +/**********************************/ + + /* Since this fuction's second parameter + * only process usb HOST mode + * pass USB_NULL in this case */ + usb_hdriver_init(ptr, USB_NULL); + + /* Setting USB relation register */ + hw_usb_hmodule_init(ptr->ip); /* MCU */ + + #if USB_CFG_TYPEC == USB_CFG_DISABLE + usb_hstd_vbus_control(ptr, (uint16_t) USB_VBON); + #if USB_CFG_BC == USB_CFG_DISABLE + usb_cpu_delay_xms((uint16_t) USB_VALUE_100U); /* 100ms wait */ + #endif /* USB_CFG_BC == USB_CFG_DISABLE */ + #else /* USB_CFG_TYPEC == USB_CFG_DISABLE */ + usb_hstd_vbus_control(ptr, (uint16_t) USB_VBOFF); + #endif /* USB_CFG_TYPEC == USB_CFG_DISABLE */ + + #if defined(USB_CFG_HCDC_USE) + ux_host_stack_class_register(_ux_system_host_class_cdc_acm_name, ux_host_class_cdc_acm_entry); + if (USB_IP1 == ptr->ip) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hcdc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hcdc_fs", usb_host_usbx_initialize, R_USB_FS0_BASE, + 0); + } + type = USB_CLASS_INTERNAL_HCDC; + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + ux_host_stack_class_register(_ux_system_host_class_storage_name, ux_host_class_storage_entry); + if (USB_IP1 == ptr->ip) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hmsc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hmsc_fs", usb_host_usbx_initialize, R_USB_FS0_BASE, + 0); + } + type = USB_CLASS_INTERNAL_HMSC; + #endif /* defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + ux_host_stack_class_register(_ux_system_host_class_hid_name, ux_host_class_hid_entry); + + ux_host_class_hid_client_register(_ux_system_host_class_hid_client_keyboard_name, + ux_host_class_hid_keyboard_entry); + ux_host_class_hid_client_register(_ux_system_host_class_hid_client_mouse_name, + ux_host_class_hid_mouse_entry); + + if (USB_IP1 == ptr->ip) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hhid_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hhid_fs", usb_host_usbx_initialize, R_USB_FS0_BASE, + 0); + } + type = USB_CLASS_INTERNAL_HHID; + #endif /* defined(USB_CFG_HHID_USE) */ + + g_usb_open_class[ptr->ip] |= (uint16_t) (1 << type); /* Set USB Open device class */ + if (USB_CLASS_INTERNAL_HCDC == type) + { + g_usb_open_class[ptr->ip] |= (1 << USB_CLASS_INTERNAL_HCDCC); /* Set USB Open device class */ + } + + g_is_A_device[ptr->ip] = USB_YES; + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_A; + g_usb_usbmode[ptr->ip] = USB_MODE_HOST; + (*g_p_otg_callback[ptr->ip])(UX_OTG_MODE_HOST); + while (1) + { + if ((ptr->ipp->INTSTS1 & USB_ATTCH) == USB_ATTCH) + { + break; + } + } + + ptr->ipp->INTENB1 &= (uint16_t) (~(uint16_t) USB_ATTCHE); + ptr->ipp->INTENB1 |= (uint16_t) (USB_ATTCHE); + } + + break; + } + #endif /* defined(USB_CFG_OTG_USE) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ + + /*** ERROR ***/ + case USB_INT_UNKNOWN: + { + USB_PRINTF0("hINT_UNKNOWN\n"); + break; + } + + default: + { + USB_PRINTF1("hINT_default %X\n", intsts); + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_interrupt + ******************************************************************************/ + + #if defined(USB_CFG_OTG_USE) + +/****************************************************************************** + * Function Name : usb_hstd_otg_mode_to_peri + * Description : Initialize regsister and driver from USB Host to USB Peripheral + * Arguments : usb_utr_t *p_utr: Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +static void usb_hstd_otg_mode_to_peri (usb_utr_t * p_utr) +{ + p_utr->ipp = usb_hstd_get_usb_ip_adr(p_utr->ip); /* Get the USB IP base address. */ + + /* Host Uinitialization */ + usb_module_register_clear(p_utr->ip); + + usb_hstd_clr_pipe_table(p_utr->ip, USB_ADDRESS1); + + usb_pdriver_init_otg(); + + /* D+ Pullup Off */ + hw_usb_pclear_dprpu(p_utr->ip); + + /* D+ Pulldown Off */ + hw_usb_clear_drpd(p_utr); + + /* Change to Peri mode */ + hw_usb_clear_dcfm(p_utr); + + /* D+ Pullup On */ + hw_usb_pset_dprpu(p_utr->ip); + + g_usb_usbmode[p_utr->ip] = USB_MODE_PERI; + g_usb_otg_suspend_flag[p_utr->ip] = USB_NO; + + p_utr->ipp->INTENB0 = (USB_BEMPE | USB_BRDYE | USB_VBSE | USB_DVSE | USB_CTRE); +} + +/****************************************************************************** + * Function Name : usb_pdriver_init_otg + * Description : Initialize driver from USB Host to USB Peripheral + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pdriver_init_otg (void) +{ + uint16_t i; + usb_cfg_t cfg_usbx; + usb_instance_ctrl_t ctrl_usbx; + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAX_EP_NO + 1); i++) + { + g_usb_pstd_eptbl_index[0][i] = 0; + g_usb_pstd_eptbl_index[1][i] = 0; + } + + /* WAIT_LOOP */ + for (i = 0; i < USB_ALT_NO; i++) + { + g_usb_pstd_alt_num[i] = 0; + } + + g_usb_pstd_test_mode_select = USB_NULL; + g_usb_pstd_req_type = USB_NULL; + g_usb_pstd_req_value = USB_NULL; + g_usb_pstd_req_index = USB_NULL; + g_usb_pstd_req_length = USB_NULL; + g_usb_pstd_pipe0_request = USB_OFF; + g_usb_pstd_std_request = USB_NO; + g_usb_peri_connected = USB_FALSE; + memset((void *) &g_usb_pstd_req_reg, 0, sizeof(usb_setup_t)); + g_usb_pstd_stall_cb = USB_NULL; + memset((void *) &g_usb_pstd_driver, 0, sizeof(usb_pcdreg_t)); + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAX_PIPE_NO + 1); i++) + { + gp_usb_pstd_data[i] = USB_NULL; + g_usb_pstd_data_cnt[i] = 0; + } + + /* WAIT_LOOP */ + for (i = 0; i < USB_EVENT_MAX; i++) + { + #if (BSP_CFG_RTOS == 0) + g_usb_cstd_event.code[i] = USB_STATUS_NONE; + #else /*(BSP_CFG_RTOS == 0)*/ + g_usb_cstd_event[i].event = USB_STATUS_NONE; + #endif /*(BSP_CFG_RTOS == 0)*/ + } + + /* WAIT_LOOP */ + for (i = USB_PIPE0; i <= USB_MAX_PIPE_NO; i++) + { + g_usb_pstd_stall_pipe[i] = USB_FALSE; + g_p_usb_pstd_pipe[i] = (usb_utr_t *) USB_NULL; + } + + g_usb_pstd_config_num = 0; /* Configuration number */ + g_usb_pstd_remote_wakeup = USB_FALSE; /* Remote wake up enable flag */ + + cfg_usbx = *g_p_usb_otg_cfg; + cfg_usbx.p_usb_reg = &g_usbx_descriptor; + usb_pstd_ux_descriptor_to_basic(&cfg_usbx); + usb_peri_registration(&ctrl_usbx, &cfg_usbx); +} + + #endif /* defined(USB_CFG_OTG_USE) */ + +/****************************************************************************** + * Function Name : usb_hstd_clr_feature + * Description : Send ClearFeature command to the connected USB device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t addr : Device address. + * : uint16_t epnum : Endpoint number. + * : usb_cb_t complete : Callback function. + * Return value : uint16_t : Error info. + ******************************************************************************/ +usb_er_t usb_hstd_clr_feature (usb_utr_t * ptr, uint16_t addr, uint16_t epnum, usb_cb_t complete) +{ + usb_er_t ret_code; + + if (USB_VALUE_FFH == epnum) + { + /* ClearFeature(Device) */ + usb_shstd_clr_stall_request[ptr->ip][0] = USB_CLEAR_FEATURE | USB_HOST_TO_DEV | USB_STANDARD | USB_DEVICE; + usb_shstd_clr_stall_request[ptr->ip][1] = USB_DEV_REMOTE_WAKEUP; + usb_shstd_clr_stall_request[ptr->ip][2] = (uint16_t) 0x0000; + } + else + { + /* ClearFeature(endpoint) */ + usb_shstd_clr_stall_request[ptr->ip][0] = USB_CLEAR_FEATURE | USB_HOST_TO_DEV | USB_STANDARD | USB_ENDPOINT; + usb_shstd_clr_stall_request[ptr->ip][1] = USB_ENDPOINT_HALT; + usb_shstd_clr_stall_request[ptr->ip][2] = epnum; + } + + usb_shstd_clr_stall_request[ptr->ip][3] = (uint16_t) 0x0000; + usb_shstd_clr_stall_request[ptr->ip][4] = addr; + + usb_shstd_clr_stall_ctrl[ptr->ip].p_tranadr = USB_NULL; + usb_shstd_clr_stall_ctrl[ptr->ip].complete = complete; + usb_shstd_clr_stall_ctrl[ptr->ip].tranlen = 0; + usb_shstd_clr_stall_ctrl[ptr->ip].keyword = USB_PIPE0; + usb_shstd_clr_stall_ctrl[ptr->ip].p_setup = usb_shstd_clr_stall_request[ptr->ip]; + usb_shstd_clr_stall_ctrl[ptr->ip].segment = USB_TRAN_END; + + usb_shstd_clr_stall_ctrl[ptr->ip].ip = ptr->ip; + usb_shstd_clr_stall_ctrl[ptr->ip].ipp = ptr->ipp; + + ret_code = usb_hstd_transfer_start_req(&usb_shstd_clr_stall_ctrl[ptr->ip]); + + #if (BSP_CFG_RTOS != 0) + if (USB_QOVR == ret_code) + { + /** Submit overlap error **/ + /** Retry **/ + /* WAIT_LOOP */ + do + { + usb_cpu_delay_xms((uint16_t) 2); + ret_code = usb_hstd_transfer_start(&usb_shstd_clr_stall_ctrl[ptr->ip]); + } while (USB_QOVR == ret_code); + } + + if (USB_OK == ret_code) + { + ret_code = class_trans_wait_tmo(ptr, (uint16_t) USB_VALUE_3000); + } + #endif /* #if (BSP_CFG_RTOS != 0) */ + + return ret_code; +} + +/****************************************************************************** + * End of function usb_hstd_clr_feature + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_clr_stall + * Description : Clear Stall + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * : usb_cb_t complete : Callback function + * Return value : uint16_t : Error info. + ******************************************************************************/ +usb_er_t usb_hstd_clr_stall (usb_utr_t * ptr, uint16_t pipe, usb_cb_t complete) +{ + usb_er_t err; + uint8_t dir_ep; + uint16_t devsel; + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("### usb_hstd_clr_stall PipeNo ERROR pipenum:%d\n", pipe); + + return USB_ERROR; /* Error */ + } + + dir_ep = usb_hstd_pipe_to_epadr(ptr, pipe); + devsel = usb_hstd_get_device_address(ptr, pipe); + + err = usb_hstd_clr_feature(ptr, (uint16_t) (devsel >> USB_DEVADDRBIT), (uint16_t) dir_ep, complete); + #if (BSP_CFG_RTOS != 0) + if (USB_OK == err) + { + usb_cstd_clr_stall(ptr, usb_shstd_clr_stall_pipe[ptr->ip]); + hw_usb_set_sqclr(ptr, usb_shstd_clr_stall_pipe[ptr->ip]); /* SQCLR */ + } + #endif /* #if (BSP_CFG_RTOS != 0) */ + + return err; +} /* End of function usb_hstd_clr_stall() */ + +/****************************************************************************** + * End of function usb_hstd_clr_stall + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hstd_clr_stall_result + * Description : Callback function to notify HCD task that usb_hstd_clr_stall function is completed + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not Use + * : uint16_t data2 : Not Use + * Return value : none + ******************************************************************************/ +static void usb_hstd_clr_stall_result (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + usb_mh_t p_blf; + usb_er_t err; + usb_er_t err2; + usb_utr_t * up; + + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); + + /* Get memory pool blk */ + err = USB_PGET_BLK(USB_HCD_MPL, &p_blf, ptr->ip); + if (USB_OK == err) + { + up = (usb_utr_t *) p_blf; + up->msghead = (usb_mh_t) USB_NULL; + up->msginfo = USB_MSG_HCD_CLR_STALL_RESULT; + up->status = ptr->status; + + up->ipp = ptr->ipp; + up->ip = ptr->ip; + + /* Send message */ + err = USB_SND_MSG(USB_HCD_MBX, (usb_msg_t *) p_blf); + if (USB_OK != err) + { + USB_PRINTF1("### hHcdSndMbx snd_msg error (%ld)\n", err); + err2 = USB_REL_BLK(USB_HCD_MPL, (usb_mh_t) p_blf); + if (USB_OK != err2) + { + USB_PRINTF1("### hHcdSndMbx rel_blk error (%ld)\n", err2); + } + } + } + else + { + /* Error */ + /* WAIT_LOOP */ + while (1) + { + /* error */ + } + } +} + +/****************************************************************************** + * End of function usb_hstd_clr_stall_result + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hstd_hcd_task + * Description : USB Host Control Driver Task. + * Argument : usb_vp_int_t stacd : Task Start Code. + * Return : none + ******************************************************************************/ + #if (BSP_CFG_RTOS == 1) +void usb_hstd_hcd_task (ULONG entry_input) + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_hstd_hcd_task (void * stacd) + #endif /* #if (BSP_CFG_RTOS == 1) */ +{ + usb_utr_t * p_mess; + usb_utr_t * ptr; + usb_er_t err; + uint16_t rootport; + uint16_t pipenum; + uint16_t msginfo; + uint16_t connect_inf; + uint16_t result = 0; + #if (BSP_CFG_RTOS == 0) + uint16_t retval; + #endif /* (BSP_CFG_RTOS== 0) */ + usb_hcdinfo_t * hp; + + #if (BSP_CFG_RTOS == 1) + (void) entry_input; + #else /* #if (BSP_CFG_RTOS == 1) */ + (void) stacd; + #endif /* #if (BSP_CFG_RTOS == 1) */ + + #if (BSP_CFG_RTOS != 0) + + /* WAIT_LOOP */ + while (1) + { + #endif /* #if (BSP_CFG_RTOS != 0) */ + /* Receive message */ + err = USB_TRCV_MSG(USB_HCD_MBX, (usb_msg_t **) &p_mess, (usb_tm_t) 10000); + if (USB_OK != err) + { + #if (BSP_CFG_RTOS != 0) + result = 1; + #else /* #if (BSP_CFG_RTOS != 0) */ + result = 2; + #endif /* #if (BSP_CFG_RTOS != 0) */ + } + + else + { + ptr = p_mess; + hp = (usb_hcdinfo_t *) p_mess; + rootport = ptr->keyword; + pipenum = ptr->keyword; + + /* Branch Hcd Task receive Message Command */ + msginfo = ptr->msginfo; + switch (msginfo) + { + case USB_MSG_HCD_INT: + { + /* USB INT */ + usb_hstd_interrupt(ptr); + break; + } + + case USB_MSG_HCD_SUBMITUTR: + { + /* USB Submit utr */ + usb_hstd_set_submitutr(ptr); + break; + } + + case USB_MSG_HCD_ATTACH: + { + /* USB attach / detach */ + usb_hstd_attach_process(ptr); + + /* Callback */ + (hp->complete)(ptr, rootport, USB_MSG_HCD_ATTACH); + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_ATTACH_MGR: + { + /* USB attach / detach */ + usb_hstd_attach_process(ptr); + connect_inf = usb_cstd_port_speed(ptr); + + /* Callback */ + (hp->complete)(ptr, rootport, connect_inf); + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_DETACH: + { + /* USB detach process */ + usb_hstd_detach_process(ptr); + + /* Callback */ + (hp->complete)(ptr, rootport, USB_MSG_HCD_DETACH); + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_DETACH_MGR: + { + hw_usb_clear_dvstctr(ptr, (USB_RWUPE | USB_USBRST | USB_RESUME | USB_UACT)); + usb_cpu_delay_xms(1); + + /* interrupt disable */ + usb_hstd_attch_disable(ptr); + usb_hstd_dtch_disable(ptr); + usb_hstd_bchg_disable(ptr); + (hp->complete)(ptr, USB_NULL, USB_MSG_HCD_DETACH_MGR); + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_USBRESET: + { + /* USB bus reset */ + usb_hstd_bus_reset(ptr); + + /* Check current port speed */ + connect_inf = usb_cstd_port_speed(ptr); + + /* Callback */ + (hp->complete)(ptr, USB_NULL, connect_inf); + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_REMOTE: + { + /* Suspend device */ + g_usb_hstd_remort_port[ptr->ip] = USB_SUSPENDED; + usb_hstd_suspend(ptr); + + /* CallBack */ + (hp->complete)(ptr, USB_NULL, USB_MSG_HCD_REMOTE); + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_SUSPEND: + { + usb_hstd_suspend(ptr); /* Suspend device */ + (hp->complete)(ptr, rootport, USB_MSG_HCD_SUSPEND); + usb_hstd_hcd_rel_mpl(ptr, msginfo); /* Release Memory Block */ + break; + } + + #if defined(USB_CFG_OTG_USE) + case USB_MSG_HCD_OTG_SUSPEND: + { + ptr->ipp = usb_hstd_get_usb_ip_adr(ptr->ip); /* Get the USB IP base address. */ + hw_usb_hclear_uact(ptr); + usb_hstd_hcd_rel_mpl(ptr, msginfo); /* Release Memory Block */ + break; + } + #endif /* defined(USB_CFG_OTG_USE) */ + + case USB_MSG_HCD_RESUME: + { + usb_hstd_resume_process(ptr); /* USB resume */ + (hp->complete)(ptr, rootport, USB_MSG_HCD_RESUME); /* Callback */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); /* Release Memory Block */ + break; + } + + case USB_MSG_HCD_VBON: + { + usb_hstd_ovrcr_enable(ptr); /* Interrupt Enable */ + usb_hstd_vbus_control(ptr, (uint16_t) USB_VBON); /* USB VBUS control ON */ + #if USB_CFG_BC == USB_CFG_DISABLE + + /* 100ms wait */ + usb_cpu_delay_xms((uint16_t) USB_VALUE_100U); + #endif /* USB_CFG_BC == USB_CFG_DISABLE */ + (hp->complete)(ptr, rootport, USB_MSG_HCD_VBON); /* Callback */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); /* Release Memory Block */ + break; + } + + case USB_MSG_HCD_VBOFF: + { + usb_hstd_vbus_control(ptr, (uint16_t) USB_VBOFF); /* USB VBUS control OFF */ + usb_hstd_ovrcr_disable(ptr); + usb_cpu_delay_xms((uint16_t) USB_VALUE_100U); /* 100ms wait */ + (hp->complete)(ptr, rootport, USB_MSG_HCD_VBOFF); /* Callback */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); /* Release Memory Block */ + break; + } + + case USB_MSG_HCD_CLR_STALLBIT: + { + usb_cstd_clr_stall(ptr, pipenum); /* STALL */ + (hp->complete)(ptr, (uint16_t) USB_NO_ARG, (uint16_t) USB_MSG_HCD_CLR_STALLBIT); /* Callback */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); /* Release Memory Block */ + break; + } + + case USB_MSG_HCD_SQTGLBIT: + { + pipenum = ptr->keyword & USB_PIPENM; + usb_hstd_do_sqtgl(ptr, pipenum, ptr->keyword); /* SQ toggle */ + (hp->complete)(ptr, (uint16_t) USB_NO_ARG, (uint16_t) USB_MSG_HCD_SQTGLBIT); /* Callback */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); /* Release Memory Block */ + break; + } + + case USB_MSG_HCD_CLR_STALL: + { + #if (BSP_CFG_RTOS != 0) + usb_shstd_clr_stall_pipe[ptr->ip] = pipenum; + err = usb_hstd_clr_stall(ptr, pipenum, (usb_cb_t) &class_trans_result); + (hp->complete)(ptr, (uint16_t) err, USB_MSG_HCD_CLR_STALL); + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + #else /* #if (BSP_CFG_RTOS != 0) */ + usb_shstd_clr_stall_call = hp->complete; + usb_shstd_clr_stall_pipe[ptr->ip] = pipenum; + err = usb_hstd_clr_stall(ptr, pipenum, (usb_cb_t) &usb_hstd_clr_stall_result); + if (USB_QOVR == err) + { + USB_WAI_MSG(USB_HCD_MBX, ptr, 1000); /* Retry */ + } + else + { + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + } + #endif /* #if (BSP_CFG_RTOS != 0) */ + break; + } + + case USB_MSG_HCD_CLR_STALL_RESULT: + { + #if (BSP_CFG_RTOS != 0) + + /** Do nothing when running in RTOS + * The result will be checked immediately after issuing a "USB_MSG_HCD_CLR_STALL" request. **/ + #else /* #if (BSP_CFG_RTOS != 0) */ + ptr = p_mess; + retval = ptr->status; + + if (USB_DATA_TMO == retval) + { + USB_PRINTF0("*** Standard Request Timeout error !\n"); + } + else if (USB_DATA_STALL == retval) + { + USB_PRINTF0("*** Standard Request STALL !\n"); + } + else if (USB_CTRL_END != retval) + { + USB_PRINTF0("*** Standard Request error !\n"); + } + else + { + usb_cstd_clr_stall(ptr, usb_shstd_clr_stall_pipe[ptr->ip]); + hw_usb_set_sqclr(ptr, usb_shstd_clr_stall_pipe[ptr->ip]); /* SQCLR */ + } + + (*usb_shstd_clr_stall_call)(ptr, retval, USB_MSG_HCD_CLR_STALL); + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + #endif /* #if (BSP_CFG_RTOS != 0) */ + break; + } + + case USB_MSG_HCD_CLRSEQBIT: + { + hw_usb_set_sqclr(ptr, pipenum); /* SQCLR */ + (hp->complete)(ptr, (uint16_t) USB_NO_ARG, (uint16_t) USB_MSG_HCD_CLRSEQBIT); /* Callback */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_SETSEQBIT: + { + hw_usb_set_sqset(ptr, pipenum); /* SQSET */ + (hp->complete)(ptr, (uint16_t) USB_NO_ARG, (uint16_t) USB_MSG_HCD_SETSEQBIT); /* Callback */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); /* Release Memory Block */ + break; + } + + case USB_MSG_HCD_TRANSEND1: + { + /* Pipe Transfer Process check */ + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][pipenum]) + { + /* Control Transfer stop */ + if (USB_PIPE0 == pipenum) + { + /* Control Read/Write End */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_TMO); + } + else + { + /* Transfer stop */ + usb_hstd_forced_termination(ptr, pipenum, (uint16_t) USB_DATA_TMO); + } + } + else + { + USB_PRINTF1("### Host not transfer %d\n", pipenum); + } + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_TRANSEND2: + { + /* Pipe Transfer Process check */ + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][pipenum]) + { + /* Control Transfer stop */ + if (USB_PIPE0 == pipenum) + { + /* Control Read/Write End */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_STOP); + } + else + { + /* Transfer stop */ + usb_hstd_forced_termination(ptr, pipenum, (uint16_t) USB_DATA_STOP); + } + } + else + { + USB_PRINTF1("### Host not transfer %d\n", pipenum); + } + + /* Release Memory Block */ + usb_hstd_hcd_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_HCD_D1FIFO_INT: + { + break; + } + + case USB_MSG_HCD_RESM_INT: + { + break; + } + + default: + { + break; + } + } + } + + #if (BSP_CFG_RTOS != 0) + if (result == 1) + { + continue; + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + if (result == 2) + { + return; + } + #endif /* #if (BSP_CFG_RTOS != 0) */ + + #if (BSP_CFG_RTOS != 0) +} /* End of while(1) */ + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hstd_hcd_task + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_send_start + * Description : Start data transmission using CPU/DMA transfer to USB host/ + * : /device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe no. + * Return value : none + ******************************************************************************/ +void usb_hstd_send_start (usb_utr_t * ptr, uint16_t pipe) +{ + usb_utr_t * pp; + uint32_t length; + uint16_t useport; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #if defined(USB_CFG_HUVC_USE) || defined(USB_CFG_HAUD_USE) + uint16_t buf; + #endif /* defined(USB_CFG_HUVC_USE) | defined(USB_CFG_HAUD_USE) */ + uint8_t dma_ch; + dmac_extended_cfg_t * channel_info; + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Evacuation pointer */ + pp = g_p_usb_hstd_pipe[ptr->ip][pipe]; + length = pp->tranlen; + + /* Check transfer count */ + if (USB_TRAN_CONT == pp->segment) + { + /* Sequence toggle */ + usb_hstd_do_sqtgl(ptr, pipe, pp->pipectr); + } + + usb_cstd_set_nak(ptr, pipe); /* Select NAK */ + g_usb_hstd_data_cnt[ptr->ip][pipe] = length; /* Set data count */ + gp_usb_hstd_data_ptr[ptr->ip][pipe] = (uint8_t *) pp->p_tranadr; /* Set data pointer */ + g_usb_hstd_ignore_cnt[ptr->ip][pipe] = (uint16_t) 0; /* Ignore count clear */ + + hw_usb_clear_status_bemp(ptr, pipe); /* BEMP Status Clear */ + hw_usb_clear_sts_brdy(ptr, pipe); /* BRDY Status Clear */ + + useport = usb_hstd_pipe2fport(ptr, pipe); /* Pipe number to FIFO port select */ + + /* Check use FIFO access */ + switch (useport) + { + case USB_CUSE: /* CFIFO use */ + { + /* Buffer to FIFO data write */ + usb_hstd_buf_to_fifo(ptr, pipe, useport); + usb_cstd_set_buf(ptr, pipe); /* Set BUF */ + + break; + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* D0FIFO DMA */ + case USB_D0USE: + + /* D1FIFO DMA */ + case USB_D1USE: + { + if (USB_IP0 == ptr->ip) + { + channel_info = (dmac_extended_cfg_t *) ptr->p_transfer_tx->p_cfg->p_extend; + dma_ch = channel_info->channel; + } + else + { + channel_info = (dmac_extended_cfg_t *) ptr->p_transfer_tx->p_cfg->p_extend; + dma_ch = channel_info->channel; + } + + /* Setting for use PIPE number */ + g_usb_cstd_dma_pipe[ptr->ip][dma_ch] = pipe; + + /* Buffer size */ + g_usb_cstd_dma_fifo[ptr->ip][dma_ch] = usb_cstd_get_buf_size(ptr, pipe); + + /* Check data count */ + if (g_usb_hstd_data_cnt[ptr->ip][pipe] <= g_usb_cstd_dma_fifo[ptr->ip][dma_ch]) + { + /* Transfer data size */ + g_usb_cstd_dma_size[ptr->ip][dma_ch] = g_usb_hstd_data_cnt[ptr->ip][pipe]; + + /* Enable Empty Interrupt */ + hw_usb_set_bempenb(ptr, pipe); + } + else + { + /* Data size == FIFO size */ + g_usb_cstd_dma_size[ptr->ip][dma_ch] = (g_usb_hstd_data_cnt[ptr->ip][pipe] - + (g_usb_hstd_data_cnt[ptr->ip][pipe] % + g_usb_cstd_dma_fifo[ptr->ip][dma_ch])); + } + + usb_cstd_dma_send_start(ptr, pipe, useport); + + #if defined(USB_CFG_HUVC_USE) || defined(USB_CFG_HAUD_USE) + if (USB_TYPFIELD_ISO == usb_cstd_get_pipe_type(ptr, pipe)) + { + while (1) + { + buf = hw_usb_read_pipectr(ptr, pipe); + if (!(buf & USB_BSTS)) + { + break; + } + } + } + #endif /* defined(USB_CFG_HUVC_USE) | defined(USB_CFG_HAUD_USE) */ + + /* Set BUF */ + usb_cstd_set_buf(ptr, pipe); + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + default: + { + /* Access is NG */ + USB_PRINTF1("### USB-ITRON is not support(SND-else:pipe%d)\n", pipe); + usb_hstd_forced_termination(ptr, pipe, (uint16_t) USB_DATA_ERR); + + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_send_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_fifo_to_buf + * Description : Request readout from USB FIFO to buffer and process depending + * : on status; read complete or reading. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe no. + * Return value : none + ******************************************************************************/ +void usb_hstd_fifo_to_buf (usb_utr_t * ptr, uint16_t pipe, uint16_t useport) +{ + uint16_t end_flag = USB_ERROR; + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("### usb_hstd_fifo_to_buf PipeNo ERROR pipenum:%d\n", pipe); + + return; /* Error */ + } + + /* Ignore count clear */ + g_usb_hstd_ignore_cnt[ptr->ip][pipe] = (uint16_t) 0; + + end_flag = usb_hstd_read_data(ptr, pipe, useport); + + /* Check FIFO access sequence */ + switch (end_flag) + { + case USB_READING: + { + /* Continue of data read */ + + break; + } + + case USB_READEND: + { + /* End of data read */ + usb_hstd_data_end(ptr, pipe, (uint16_t) USB_DATA_OK); + + break; + } + + case USB_READSHRT: + { + /* End of data read */ + usb_hstd_data_end(ptr, pipe, (uint16_t) USB_DATA_SHT); + + break; + } + + case USB_READOVER: + { + /* Buffer over */ + USB_PRINTF1("###usb_hstd_fifo_to_buf Receive data over PIPE%d\n", pipe); + usb_hstd_forced_termination(ptr, pipe, (uint16_t) USB_DATA_OVR); + + break; + } + + case USB_FIFOERROR: + { + /* FIFO access error */ + USB_PRINTF0("###usb_hstd_fifo_to_buf FIFO access error \n"); + usb_hstd_forced_termination(ptr, pipe, (uint16_t) USB_DATA_ERR); + + break; + } + + default: + { + usb_hstd_forced_termination(ptr, pipe, (uint16_t) USB_DATA_ERR); + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_fifo_to_buf + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_buf_to_fifo + * Description : Set USB registers as required to write from data buffer to USB + * : FIFO, to have USB FIFO to write data to bus. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe no. + * : uint16_t useport : Port no. + * Return value : none + ******************************************************************************/ +void usb_hstd_buf_to_fifo (usb_utr_t * ptr, uint16_t pipe, uint16_t useport) +{ + uint16_t end_flag; + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Disable Ready Interrupt */ + hw_usb_clear_brdyenb(ptr, pipe); + + /* Ignore count clear */ + g_usb_hstd_ignore_cnt[ptr->ip][pipe] = (uint16_t) 0; + + end_flag = usb_hstd_write_data(ptr, pipe, useport); + + /* Check FIFO access sequence */ + switch (end_flag) + { + case USB_WRITING: + { + /* Continue of data write */ + /* Enable Ready Interrupt */ + hw_usb_set_brdyenb(ptr, pipe); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(ptr, pipe); + + break; + } + + case USB_WRITEEND: + + /* End of data write */ + /* continue */ + + case USB_WRITESHRT: + { + /* End of data write */ + /* Enable Empty Interrupt */ + hw_usb_set_bempenb(ptr, pipe); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(ptr, pipe); + + break; + } + + case USB_FIFOERROR: + { + /* FIFO access error */ + USB_PRINTF0("###usb_hstd_buf_to_fifo FIFO access error \n"); + usb_hstd_forced_termination(ptr, pipe, (uint16_t) USB_DATA_ERR); + + break; + } + + default: + { + usb_hstd_forced_termination(ptr, pipe, (uint16_t) USB_DATA_ERR); + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_buf_to_fifo + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_class_request_complete + * Description : Class request transfer complete + * Arguments : usb_utr_t *mess : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not used. + * : uint16_t data2 : Not used. + * Return : none + ******************************************************************************/ +void usb_class_request_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) +{ + usb_instance_ctrl_t ctrl; + + (void) data1; + (void) data2; + + if (USB_CTRL_END == mess->status) /* Check usb receive status */ + { + ctrl.status = USB_SETUP_STATUS_ACK; + } + else if (USB_DATA_STALL == mess->status) /* Check usb receive status */ + { + ctrl.status = USB_SETUP_STATUS_STALL; + } + else + { + ctrl.status = USB_ERROR; + } + + ctrl.type = USB_CLASS_REQUEST; + ctrl.module_number = mess->ip; /* Module number setting */ + ctrl.setup.request_type = mess->p_setup[0]; + ctrl.pipe = USB_PIPE0; + ctrl.setup.request_value = mess->p_setup[1]; + ctrl.setup.request_index = mess->p_setup[2]; + ctrl.setup.request_length = mess->p_setup[3]; + ctrl.device_address = (uint8_t) mess->p_setup[4]; + ctrl.data_size = ctrl.setup.request_length - g_usb_hstd_data_cnt_pipe0[mess->ip]; + #if (BSP_CFG_RTOS != 0) + ctrl.p_data = (void *) mess->cur_task_hdl; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + usb_set_event(USB_STATUS_REQUEST_COMPLETE, &ctrl); /* Set Event() */ +} + +/****************************************************************************** + * End of function usb_class_request_complete + ******************************************************************************/ + + #if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_hstd_transfer_end + * Description : Request HCD to force termination of data transfer. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number + * : uint16_t status : Data transfer status + * Return : usb_err_t error code : USB_OK etc + ******************************************************************************/ +usb_er_t usb_hstd_transfer_end (usb_utr_t * ptr, uint16_t pipe, uint16_t status) +{ + uint16_t msg; + usb_er_t err; + + #if (BSP_CFG_RTOS == 0) + if (USB_MAX_PIPE_NO < pipe) + { + return USB_ERROR; /* Error */ + } + + if (USB_ON == g_usb_hstd_pipe_request[ptr->ip][pipe]) + { + return USB_ERROR; + } + #endif /* (BSP_CFG_RTOS == 0) */ + + if (USB_NULL == g_p_usb_hstd_pipe[ptr->ip][pipe]) + { + USB_PRINTF1("### usb_hstd_transfer_end overlaps %d\n", pipe); + + return USB_QOVR; + } + + if (USB_DATA_TMO == status) + { + msg = USB_MSG_HCD_TRANSEND1; + } + else + { + msg = USB_MSG_HCD_TRANSEND2; + } + + err = usb_hstd_hcd_snd_mbx(ptr, msg, pipe, (uint16_t *) 0, &usb_hstd_dummy_function); + + return err; +} + +/****************************************************************************** + * End of function usb_hstd_transfer_end + ******************************************************************************/ + #endif /* #if (USB_UT_MODE == 0) */ + +/****************************************************************************** + * Function Name : usb_hstd_driver_registration + * Description : The HDCD information registered in the class driver structure + * : is registered in HCD. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : usb_hcdreg_t *callback : Pointer to usb_hcdreg_t structure + * Return : none + ******************************************************************************/ +void usb_hstd_driver_registration (usb_utr_t * ptr, usb_hcdreg_t * callback) +{ + usb_hcdreg_t * driver; + + if (g_usb_hstd_device_num[ptr->ip] <= USB_MAXDEVADDR) + { + driver = &g_usb_hstd_device_drv[ptr->ip][g_usb_hstd_device_num[ptr->ip]]; + + driver->rootport = USB_NOPORT; /* Root port */ + driver->devaddr = USB_NODEVICE; /* Device address */ + driver->devstate = USB_DETACHED; /* Device state */ + driver->ifclass = callback->ifclass; /* Interface Class */ + driver->p_tpl = callback->p_tpl; /* Target peripheral list */ + driver->classinit = callback->classinit; /* Driver init */ + driver->classcheck = callback->classcheck; /* Driver check */ + driver->devconfig = callback->devconfig; /* Device configured */ + driver->devdetach = callback->devdetach; /* Device detach */ + driver->devsuspend = callback->devsuspend; /* Device suspend */ + driver->devresume = callback->devresume; /* Device resume */ + /* Initialized device driver */ + (*driver->classinit)(ptr, driver->devaddr, (uint16_t) USB_NO_ARG); + g_usb_hstd_device_num[ptr->ip]++; + USB_PRINTF1("*** Registration driver 0x%02x\n", driver->ifclass); + } +} + +/****************************************************************************** + * End of function usb_hstd_driver_registration + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_driver_release + * Description : Release the Device Class Driver. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint8_t devclass : Interface class + * Return : none + ******************************************************************************/ +void usb_hstd_driver_release (usb_utr_t * ptr, uint8_t devclass) +{ + usb_hcdreg_t * driver; + uint16_t i; + uint16_t flg; + + if (USB_IFCLS_NOT == devclass) + { + /* Device driver number */ + g_usb_hstd_device_num[ptr->ip] = 0; + } + else + { + flg = 0U; + + /* WAIT_LOOP */ + for (i = 0U; (i < (USB_MAXDEVADDR + 1U)) && (0U == flg); i++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][i]; + if (driver->ifclass == devclass) + { + driver->rootport = USB_NOPORT; /* Root port */ + driver->devaddr = USB_NODEVICE; /* Device address */ + driver->devstate = USB_DETACHED; /* Device state */ + + /* Interface Class : NO class */ + driver->ifclass = (uint16_t) USB_IFCLS_NOT; + + g_usb_hstd_device_num[ptr->ip]--; + USB_PRINTF1("*** Release class %d driver ***\n", devclass); + flg = 1U; /* break; */ + } + } + } +} + +/****************************************************************************** + * End of function usb_hstd_driver_release + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_set_pipe_info + * Description : Copy information of pipe information table from source + * : (2nd argument) to destination (1st argument) + * Argument : usb_pipe_table_t *dst_ep_tbl : DEF_EP table pointer(destination) + * : usb_pipe_table_t *src_ep_tbl : DEF_EP table pointer(source) + * Return : none + ******************************************************************************/ +void usb_hstd_set_pipe_info (uint16_t ip_no, uint16_t pipe_no, usb_pipe_table_reg_t * src_ep_tbl) +{ + g_usb_pipe_table[ip_no][pipe_no].use_flag = USB_TRUE; + g_usb_pipe_table[ip_no][pipe_no].pipe_cfg = src_ep_tbl->pipe_cfg; + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ip_no) + { + g_usb_pipe_table[ip_no][pipe_no].pipe_buf = src_ep_tbl->pipe_buf; + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + g_usb_pipe_table[ip_no][pipe_no].pipe_maxp = src_ep_tbl->pipe_maxp; + g_usb_pipe_table[ip_no][pipe_no].pipe_peri = src_ep_tbl->pipe_peri; + + #if BSP_CFG_RTOS == 1 + tx_semaphore_create(&g_usb_host_usbx_sem[ip_no][pipe_no], "USB_FSP_SEMX_HOST", 0); + #endif +} + +/****************************************************************************** + * End of function usb_hstd_set_pipe_info + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hstd_return_enu_mgr + * Description : Continuous enumeration is requested to MGR task (API for nonOS) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t cls_result : class check result + * Return : none + ******************************************************************************/ +void usb_hstd_return_enu_mgr (usb_utr_t * ptr, uint16_t cls_result) +{ + g_usb_hstd_check_enu_result[ptr->ip] = cls_result; + usb_hstd_mgr_snd_mbx(ptr, USB_MSG_MGR_SUBMITRESULT, USB_PIPE0, USB_CTRL_END); +} + +/****************************************************************************** + * End of function usb_hstd_return_enu_mgr + ******************************************************************************/ + + #endif /* (BSP_CFG_RTOS == 0) */ + + #if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_hstd_change_device_state + * Description : Request to change the status of the connected USB Device + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : usb_cb_t complete : callback function pointer + * : uint16_t msginfo : Message Info + * : uint16_t member : Device address/pipe number + * Return : usb_err_t : USB_OK etc + ******************************************************************************/ +usb_er_t usb_hstd_change_device_state (usb_utr_t * ptr, usb_cb_t complete, uint16_t msginfo, uint16_t member) +{ + usb_mh_t p_blf; + usb_er_t err; + usb_er_t err2; + usb_hcdinfo_t * hp; + + switch (msginfo) + { + /* USB_MSG_HCD_CLR_STALL */ + case USB_DO_CLR_STALL: + { + err = usb_hstd_hcd_snd_mbx(ptr, USB_MSG_HCD_CLR_STALL, member, (uint16_t *) 0, complete); + break; + } + + /* USB_MSG_HCD_SQTGLBIT */ + case USB_DO_SET_SQTGL: + { + err = usb_hstd_hcd_snd_mbx(ptr, USB_MSG_HCD_SETSEQBIT, member, (uint16_t *) 0, complete); + break; + } + + /* USB_MSG_HCD_CLRSEQBIT */ + case USB_DO_CLR_SQTGL: + { + err = usb_hstd_hcd_snd_mbx(ptr, USB_MSG_HCD_CLRSEQBIT, member, (uint16_t *) 0, complete); + break; + } + + default: + { + /* Get memory pool blk */ + err = USB_PGET_BLK(USB_MGR_MPL, &p_blf, ptr->ip); + if (FSP_SUCCESS == err) + { + USB_PRINTF2("*** member%d : msginfo=%d ***\n", member, msginfo); + hp = (usb_hcdinfo_t *) p_blf; + hp->msghead = (usb_mh_t) USB_NULL; + hp->msginfo = msginfo; + hp->keyword = member; + hp->complete = complete; + + hp->ipp = ptr->ipp; + hp->ip = ptr->ip; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + hp->p_transfer_rx = ptr->p_transfer_rx; + hp->p_transfer_tx = ptr->p_transfer_tx; + #endif + #if (BSP_CFG_RTOS == 2) + hp->cur_task_hdl = xTaskGetCurrentTaskHandle(); + #elif (BSP_CFG_RTOS == 1) /* #if (BSP_CFG_RTOS == 2) */ + hp->cur_task_hdl = tx_thread_identify(); + #endif /* #if (BSP_CFG_RTOS == 2) */ + + /* Send message */ + err = USB_SND_MSG(USB_MGR_MBX, (usb_msg_t *) p_blf); + if (FSP_SUCCESS != err) + { + USB_PRINTF1("### hMgrChangeDeviceState snd_msg error (%ld)\n", err); + err2 = USB_REL_BLK(USB_MGR_MPL, (usb_mh_t) p_blf); + if (FSP_SUCCESS != err2) + { + USB_PRINTF1("### hMgrChangeDeviceState rel_blk error (%ld)\n", err2); + } + } + } + else + { + /* Error */ + /* WAIT_LOOP */ + while (1) + { + /* error */ + } + } + + break; + } + } + + return err; +} + +/****************************************************************************** + * End of function usb_hstd_change_device_state + ******************************************************************************/ + #endif /* #if (USB_UT_MODE == 0) */ + +/***************************************************************************//** + * @brief Start HCD(Host Control Driver) task + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_FAILED Failed in acquiring version information. + ******************************************************************************/ +fsp_err_t usb_hstd_hcd_open (usb_utr_t * ptr) +{ + static uint8_t is_init = USB_NO; + uint16_t i; + uint16_t j; + fsp_err_t err = FSP_SUCCESS; + + if (USB_MAXDEVADDR < USB_DEVICEADDR) + { + USB_PRINTF0("Device address error\n"); + + /* >yes no process */ + return FSP_ERR_USB_FAILED; + } + + /* Global Init */ + if (USB_NO == is_init) + { + #if (BSP_CFG_RTOS == 0) + usb_shstd_clr_stall_call = 0; + #endif /* (BSP_CFG_RTOS == 0) */ + + usb_shstd_clr_stall_pipe[0] = 0; + memset((void *) &usb_shstd_clr_stall_ctrl[0], 0, sizeof(usb_utr_t)); + memset((void *) &usb_shstd_clr_stall_request[0], 0, (5 * 2)); + #if (USB_NUM_USBIP == 2) + usb_shstd_clr_stall_pipe[1] = 0; + memset((void *) &usb_shstd_clr_stall_ctrl[1], 0, sizeof(usb_utr_t)); + memset((void *) &usb_shstd_clr_stall_request[1], 0, (5 * 2)); + #endif + is_init = USB_YES; + } + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAXDEVADDR + 1); i++) + { + memset((void *) &g_usb_hstd_device_drv[ptr->ip][i], 0, sizeof(usb_hcdreg_t)); + memset((void *) &g_usb_hstd_device_info[ptr->ip][i], 0, (8 * 2)); + g_usb_hstd_dcp_register[ptr->ip][i] = 0; + memset((void *) &g_usb_ctrl_request[ptr->ip][i], 0, sizeof(usb_ctrl_trans_t)); + } + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAX_PIPE_NO + 1); i++) + { + g_usb_hstd_data_cnt[ptr->ip][i] = 0; + gp_usb_hstd_data_ptr[ptr->ip][i] = 0; + g_usb_hstd_ignore_cnt[ptr->ip][i] = 0; + #if (BSP_CFG_RTOS == 0) + g_usb_hstd_pipe_request[ptr->ip][i] = 0; + #endif /* (BSP_CFG_RTOS == 0) */ + } + + g_usb_hstd_device_addr[ptr->ip] = 0; + g_usb_hstd_device_speed[ptr->ip] = 0; + g_usb_hstd_device_num[ptr->ip] = 0; + + /* Control transfer stage management */ + g_usb_hstd_ctsq[ptr->ip] = USB_IDLEST; + + g_usb_hstd_remort_port[ptr->ip] = USB_DEFAULT; + + j = ptr->ip; + + /* WAIT_LOOP */ + for (i = USB_PIPE0; i <= USB_MAX_PIPE_NO; i++) + { + g_p_usb_hstd_pipe[j][i] = (usb_utr_t *) USB_NULL; + } + + #if USB_CFG_BC == USB_CFG_ENABLE + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + g_usb_hstd_bc[ptr->ip].state = USB_BC_STATE_INIT; + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + + USB_PRINTF0("*** Install USB-HCD ***\n"); + + usb_cstd_set_task_pri(USB_HCD_TSK, USB_PRI_1); + + return err; +} + +/****************************************************************************** + * End of function usb_hstd_hcd_open + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_dummy_function + * Description : Dummy function + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not used. + * : uint16_t data2 : Not used. + * Return value : none + ******************************************************************************/ +void usb_hstd_dummy_function (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + (void) *ptr; + (void) data1; + (void) data2; + + /* None */ +} + +/****************************************************************************** + * End of function usb_hstd_dummy_function + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_suspend_complete + * Description : usb_hstd_change_device_state callback (Suspend) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not used. + * : uint16_t data2 : Not used. + * Return value : none + ******************************************************************************/ +void usb_hstd_suspend_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + usb_instance_ctrl_t ctrl; + usb_cfg_t * p_cfg = USB_NULL; + + (void) data1; + (void) data2; + + #if (BSP_CFG_RTOS == 0) + g_usb_change_device_state[ptr->ip] &= (uint16_t) (~(1 << USB_STATUS_SUSPEND)); + #endif /* BSP_CFG_RTOS == 0 */ + + ctrl.module_number = ptr->ip; /* USB Module Number */ + ctrl.device_address = 1; /* Device Address Number */ + #if (BSP_CFG_RTOS != 0) + g_usb_hstd_sus_res_task_id[ptr->ip] = ptr->cur_task_hdl; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + if (ptr->ip) + { + #if defined(USB_HIGH_SPEED_MODULE) + #if defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBHS_USB_INT_RESUME); + #endif /* defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME) */ + #else /* defined(USB_HIGH_SPEED_MODULE) */ + #if defined(VECTOR_NUMBER_USBFS_INT) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBFS_INT); + #endif /* defined(VECTOR_NUMBER_USBFS_INT) */ + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + } + else + { + #if defined(VECTOR_NUMBER_USBFS_INT) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBFS_INT); + #endif /* defined(VECTOR_NUMBER_USBFS_INT) */ + } + + if (USB_NULL != p_cfg) + { + ctrl.p_context = p_cfg->p_context; + } + + usb_set_event(USB_STATUS_SUSPEND, &ctrl); +} + +/****************************************************************************** + * End of function usb_hstd_suspend_complete + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_resume_complete + * Description : usb_hstd_change_device_state callback (Resume) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not used. + * : uint16_t data2 : Not used. + * Return value : none + ******************************************************************************/ +void usb_hstd_resume_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + usb_instance_ctrl_t ctrl; + usb_cfg_t * p_cfg = USB_NULL; + + (void) data1; + (void) data2; + + #if (BSP_CFG_RTOS == 0) + g_usb_change_device_state[ptr->ip] &= (uint16_t) (~(1 << USB_STATUS_RESUME)); + #endif /* BSP_CFG_RTOS == 0 */ + + ctrl.module_number = ptr->ip; + ctrl.device_address = 1; + #if (BSP_CFG_RTOS != 0) + ctrl.p_data = (void *) ptr->cur_task_hdl; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + if (ptr->ip) + { + #if defined(USB_HIGH_SPEED_MODULE) + #if defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBHS_USB_INT_RESUME); + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + #else /* defined(USB_HIGH_SPEED_MODULE) */ + #if defined(VECTOR_NUMBER_USBFS_INT) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBFS_INT); + #endif /* defined(VECTOR_NUMBER_USBFS_INT) */ + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + } + else + { + #if defined(VECTOR_NUMBER_USBFS_INT) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBFS_INT); + #endif /* defined(VECTOR_NUMBER_USBFS_INT) */ + } + + if (USB_NULL != p_cfg) + { + ctrl.p_context = p_cfg->p_context; + } + + usb_set_event(USB_STATUS_RESUME, &ctrl); +} /* End of function usb_hstd_resume_complete */ + +/****************************************************************************** + * Function Name : usb_hstd_device_information + * Description : Get the status of the connected USB Device + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t devaddr : Device address + * : uint16_t *tbl : Table Pointer + * Return : None + ******************************************************************************/ +void usb_hstd_device_information (usb_utr_t * ptr, uint16_t devaddr, uint16_t * tbl) +{ + uint16_t i; + uint16_t port; + uint16_t * p; + + if (0 == devaddr) + { + p = tbl; + for (i = 0; i < 8; ++i) + { + *p++ = USB_NOPORT; + } + + port = g_usb_hstd_device_info[ptr->ip][devaddr][0]; + tbl[0] = port; + tbl[1] = g_usb_hstd_mgr_mode[ptr->ip]; + tbl[4] = g_usb_hstd_device_info[ptr->ip][devaddr][4]; + } + else + { + for (i = 0; i < 8; ++i) + { + tbl[i] = g_usb_hstd_device_info[ptr->ip][devaddr][i]; + } + } + + tbl[8] = g_usb_hstd_mgr_mode[ptr->ip]; +} + +/****************************************************************************** + * End of function usb_hstd_device_information + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_host_registration + * Description : sample registration. + * Argument : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : usb_class_t type : USB class type + * Return : none + ******************************************************************************/ +void usb_host_registration (usb_utr_t * ptr, usb_class_t type) +{ + (void) *ptr; + (void) type; + + #if BSP_CFG_RTOS == 1 + usb_host_usbx_registration(ptr, type); + #else + #if (USB_CFG_MULTIPORT == USB_CFG_ENABLE) /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + if (USB_CLASS_HCDC == type) + #endif /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + { + #if defined(USB_CFG_HCDC_USE) /* defined(USB_CFG_HCDC_USE) */ + usb_hcdc_registration(ptr); + #endif /* defined(USB_CFG_HCDC_USE) */ + } + + #if (USB_CFG_MULTIPORT == USB_CFG_ENABLE) /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + if (USB_CLASS_HHID == type) + #endif /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + { + #if defined(USB_CFG_HHID_USE) /* defined(USB_CFG_HHID_USE) */ + usb_hhid_registration(ptr); + #endif /* defined(USB_CFG_HHID_USE) */ + } + + #if (USB_CFG_MULTIPORT == USB_CFG_ENABLE) /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + if (USB_CLASS_HMSC == type) + #endif /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + { + #if defined(USB_CFG_HMSC_USE) /* defined(USB_CFG_HMSC_USE) */ + usb_hmsc_registration(ptr); + #endif /* defined(USB_CFG_HMSC_USE) */ + } + + #if (USB_CFG_MULTIPORT == USB_CFG_ENABLE) /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + if (USB_CLASS_HVND == type) + #endif /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + { + #if defined(USB_CFG_HVND_USE) /* defined(USB_CFG_HVND_USE) */ + usb_hvnd_registration(ptr); + #endif /* defined(USB_CFG_HVND_USE) */ + } + + #if (USB_CFG_MULTIPORT == USB_CFG_ENABLE) /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + if (USB_CLASS_HAUD == type) + #endif /* USB_CFG_MULTIPORT == USB_CFG_ENABLE */ + { + #if defined(USB_CFG_HAUD_USE) + usb_haud_registration(ptr); + #endif /* defined(USB_CFG_HAUD_USE) */ + } + #endif /* BSP_CFG_RTOS == 1 */ +} + +/****************************************************************************** + * End of function usb_host_registration + ******************************************************************************/ + + #if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_hstd_transfer_start + * Description : Send a request for data transfer to HCD (Host Control Driver) + * : using the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : usb_er_t : USB_OK/USB_QOVR/USB_ERROR + ******************************************************************************/ +usb_er_t usb_hstd_transfer_start (usb_utr_t * ptr) +{ + usb_er_t err; + + /* Check enumeration */ + if (USB_PIPE0 == ptr->keyword) + { + if (USB_DEFAULT == g_usb_hstd_mgr_mode[ptr->ip]) + { + return USB_QOVR; + } + } + + err = usb_hstd_transfer_start_req(ptr); + + return err; +} + +/****************************************************************************** + * End of function usb_hstd_transfer_start + ******************************************************************************/ + #endif /* #if (USB_UT_MODE == 0) */ + +/****************************************************************************** + * Function Name : usb_hstd_connect_err_event_set + * Description : Set event for "USB_STS_NOT_SUPPORT" + * Arguments : uint16_t ip_no : IP no.(USB_IP0/USB_IP1) + * Return : none + ******************************************************************************/ +void usb_hstd_connect_err_event_set (uint16_t ip_no) +{ + usb_instance_ctrl_t ctrl; + + ctrl.device_address = (uint8_t) g_usb_hstd_device_addr[ip_no]; /* usb device address */ + ctrl.module_number = (uint8_t) ip_no; /* module number setting */ + usb_set_event(USB_STATUS_NOT_SUPPORT, &ctrl); /* set event() */ +} + +/****************************************************************************** + * End of function usb_hstd_connect_err_event_set + ******************************************************************************/ + + #if defined(USB_CFG_HVND_USE) + +/****************************************************************************** + * Function Name : usb_hvnd_set_pipe_registration + * Description : Host CDC pipe registration. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t devadr : Device address + * Return : usb_er_t : Error info + ******************************************************************************/ +usb_er_t usb_hvnd_set_pipe_registration (usb_utr_t * ptr, uint16_t dev_addr) +{ + usb_er_t err; /* Error code */ + uint8_t pipe_no; + + err = USB_ERROR; + + /* Device address check */ + if (0 != dev_addr) + { + /* Search use pipe block */ + /* WAIT_LOOP */ + for (pipe_no = USB_MIN_PIPE_NO; pipe_no < (USB_MAX_PIPE_NO + 1); pipe_no++) + { + /* Check use block */ + if (USB_TRUE == g_usb_pipe_table[ptr->ip][pipe_no].use_flag) + { + /* Check USB Device address */ + if ((uint16_t) (dev_addr << USB_DEVADDRBIT) == + (uint16_t) (g_usb_pipe_table[ptr->ip][pipe_no].pipe_maxp & USB_DEVSEL)) + { + usb_hstd_set_pipe_reg(ptr, pipe_no); + err = USB_OK; + } + } + } + } + else + { + /* Error */ + USB_PRINTF1("SmplOpen adr error %x\n", dev_addr); + } + + return err; +} + +/****************************************************************************** + * End of function usb_hvnd_set_pipe_registration() + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_configured + * Description : Host vendor application initialization. + * Argument : usb_utr_t *ptr : IP info (mode, IP no, reg. address). + * : uint16_t dev_addr : Device address. + * : uint16_t data2 : Not used. + * Return : none + ******************************************************************************/ +void usb_hvnd_configured (usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2) +{ + (void) data2; + + usb_instance_ctrl_t ctrl; + + ctrl.module_number = ptr->ip; /* Module number setting */ + ctrl.device_address = (uint8_t) dev_addr; + if (0 != dev_addr) + { + /* Registration */ + usb_hvnd_set_pipe_registration(ptr, dev_addr); /* Host CDC Pipe registration */ + } + + usb_set_event(USB_STATUS_CONFIGURED, &ctrl); +} + +/****************************************************************************** + * End of function usb_hvnd_configured + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_detach + * Description : Close host vendor application. + * Argument : usb_utr_t *ptr : IP info (mode, IP no, reg. address). + * : uint16_t data1 : Not Use + * : uint16_t data2 : Not Use + * Return : none + ******************************************************************************/ +void usb_hvnd_detach (usb_utr_t * ptr, uint16_t dev_addr, uint16_t data2) +{ + (void) data2; + + usb_instance_ctrl_t ctrl; + + usb_hstd_clr_pipe_table(ptr->ip, dev_addr); + + ctrl.module_number = ptr->ip; /* Module number setting */ + ctrl.device_address = (uint8_t) dev_addr; + usb_set_event(USB_STATUS_DETACH, &ctrl); +} + +/****************************************************************************** + * End of function usb_hvnd_detach + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_enumeration + * Description : Vendor class example enumeration execution by host. + * Argument : usb_clsinfo_t *mess : Class info data pointer. + * Return : none + ******************************************************************************/ +void usb_hvnd_enumeration (usb_clsinfo_t * mess, uint16_t ** table) +{ + uint8_t * p_desc; + uint16_t desc_len; + uint16_t speed; + + *table[3] = USB_OK; + + /* Pipe Information table set */ + speed = *table[6]; + p_desc = (uint8_t *) g_usb_hstd_config_descriptor[mess->ip]; + + desc_len = (uint16_t) (((uint16_t) *(p_desc + 3)) << 8); + desc_len = (uint16_t) (desc_len + *(p_desc + 2)); + + /* Pipe Information table set */ + usb_hvnd_pipe_info(mess, p_desc, speed, desc_len); + + #if (BSP_CFG_RTOS == 0) + usb_hstd_return_enu_mgr(mess, USB_OK); /* Return to MGR */ + #endif /* BSP_CFG_RTOS == 0 */ +} + +/****************************************************************************** + * End of function usb_hvnd_enumeration + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_pipe_info + * Description : Host pipe information check. Set EP table. + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure + * : uint8_t *table : Descriptor start address. + * : uint16_t speed : Device connected speed + * : uint16_t length : Configuration Descriptor Length + * Return value : none + ******************************************************************************/ +static void usb_hvnd_pipe_info (usb_utr_t * p_utr, uint8_t * table, uint16_t speed, uint16_t length) +{ + uint16_t ofdsc; + uint16_t pipe_no; + usb_pipe_table_reg_t ep_tbl; + + /* Check Endpoint Descriptor */ + ofdsc = table[0]; + + /* WAIT_LOOP */ + while (ofdsc < length) + { + /* Search within Interface */ + if (USB_DT_ENDPOINT == table[ofdsc + 1]) + { + pipe_no = (uint16_t) (usb_hvnd_make_pipe_reg_info(p_utr, USB_ADDRESS1, speed, &table[ofdsc], &ep_tbl)); + if (USB_NULL != pipe_no) + { + usb_hstd_set_pipe_info(p_utr->ip, pipe_no, &ep_tbl); + } + else + { + return; + } + } + + ofdsc = (uint16_t) (ofdsc + table[ofdsc]); + } +} + +/****************************************************************************** + * End of function usb_hvnd_pipe_info + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_read_complete + * Description : Notify application task of data reception completion. + * : (Callback function at completion of INT data reception.) + * Arguments : + * Return value : none + ******************************************************************************/ +void usb_hvnd_read_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + (void) data1; + (void) data2; + + usb_instance_ctrl_t ctrl; + + ctrl.module_number = ptr->ip; /* Module number setting */ + ctrl.pipe = (uint8_t) ptr->keyword; /* Pipe number setting */ + ctrl.type = USB_CLASS_HVND; /* Vendor class */ + + ctrl.data_size = ptr->read_req_len - ptr->tranlen; + ctrl.device_address = (uint8_t) (usb_hstd_get_devsel(ptr, ctrl.pipe) >> 12); + #if (BSP_CFG_RTOS != 0) + ctrl.p_data = (void *) ptr->cur_task_hdl; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + switch (ptr->status) + { + case USB_DATA_OK: + { + ctrl.status = FSP_SUCCESS; + break; + } + + case USB_DATA_SHT: + { + ctrl.status = FSP_ERR_USB_SIZE_SHORT; + break; + } + + case USB_DATA_OVR: + { + ctrl.status = FSP_ERR_USB_SIZE_OVER; + break; + } + + case USB_DATA_ERR: + default: + { + ctrl.status = FSP_ERR_USB_FAILED; + break; + } + } + + usb_set_event(USB_STATUS_READ_COMPLETE, &ctrl); /* Set Event() */ +} + +/****************************************************************************** + * End of function usb_hvnd_read_complete() + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_write_complete + * Description : Notify application task of data transmission completion. + * : (Callback function at completion of INT data reception.) + * Arguments : + * Return value : none + ******************************************************************************/ +void usb_hvnd_write_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + (void) data1; + (void) data2; + + usb_instance_ctrl_t ctrl; + + ctrl.module_number = ptr->ip; /* Module number setting */ + ctrl.pipe = (uint8_t) ptr->keyword; /* Pipe number setting */ + ctrl.type = USB_CLASS_HVND; /* Vendor class */ + ctrl.device_address = (uint8_t) (usb_hstd_get_devsel(ptr, ctrl.pipe) >> 12); + #if (BSP_CFG_RTOS != 0) + ctrl.p_data = (void *) ptr->cur_task_hdl; + #endif /* #if (BSP_CFG_RTOS != 0) */ + + if (USB_DATA_NONE == ptr->status) + { + ctrl.status = FSP_SUCCESS; + } + else + { + ctrl.status = FSP_ERR_USB_FAILED; + } + + usb_set_event(USB_STATUS_WRITE_COMPLETE, &ctrl); /* Set Event() */ +} + +/****************************************************************************** + * End of function usb_hvnd_write_complete() + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_registration + * Description : Host vendor class registration. + * Argument : usb_utr_t *ptr : IP info (mode, IP no, reg. address). + * Return : none + ******************************************************************************/ +void usb_hvnd_registration (usb_utr_t * ptr) +{ + usb_hcdreg_t driver; + + /* Driver registration */ + + /* Interface Class */ + driver.ifclass = (uint16_t) USB_IFCLS_VEN; + + /* Target peripheral list */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + driver.p_tpl = (uint16_t *) USB_CFG_TPL_TABLE; + #else /* #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + driver.p_tpl = (uint16_t *) &g_usb_apl_devicetpl; + #endif /* #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + /* Driver init */ + driver.classinit = &usb_hstd_dummy_function; + + /* Driver check */ + driver.classcheck = &usb_hvnd_enumeration; + + /* Device configured */ + driver.devconfig = &usb_hvnd_configured; + + /* Device detach */ + driver.devdetach = &usb_hvnd_detach; + + /* Device suspend */ + driver.devsuspend = &usb_hstd_dummy_function; + + /* Device resume */ + driver.devresume = &usb_hstd_dummy_function; + + usb_hstd_driver_registration(ptr, &driver); + + #if USB_CFG_HUB == USB_CFG_ENABLE + #if (BSP_CFG_RTOS == 0) + usb_cstd_set_task_pri(USB_HUB_TSK, USB_PRI_3); + #endif /* BSP_CFG_RTOS == 0 */ + usb_hhub_registration(ptr, USB_NULL); + #endif /* USB_CFG_HUB == USB_CFG_ENABLE */ +} + +/****************************************************************************** + * End of function usb_hvnd_registration + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hvnd_make_pipe_reg_info + * Description : Make value for USB PIPE registers set value. + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure + * : uint16_t address : USB Device address + * : usb_class_t usb_class : USB Device class(USB_HVND/USB_HCDC/USB_HHID/USB_HMSC/USB_HUB) + * : uint16_t speed : USB speed + * : uint8_t *descriptor : Address for End Point Descriptor + * : usb_pipe_table_reg_t *pipe_table_work : Address for Store PIPE reg set value. + * Return value : Pipe no (USB_PIPE1->USB_PIPE9:OK, USB_NULL:Error) + ******************************************************************************/ +static uint8_t usb_hvnd_make_pipe_reg_info (usb_utr_t * p_utr, + uint16_t address, + uint16_t speed, + uint8_t * descriptor, + usb_pipe_table_reg_t * pipe_table_work) +{ + uint8_t pipe_no; + uint16_t pipe_cfg; + uint16_t pipe_maxp; + uint16_t pipe_peri = USB_NULL; + #if defined(USB_HIGH_SPEED_MODULE) + uint16_t pipe_buf; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + /* Check Endpoint descriptor */ + if (USB_DT_ENDPOINT != descriptor[USB_DEV_B_DESCRIPTOR_TYPE]) + { + return USB_NULL; /* Error */ + } + + /* set pipe configuration value */ + switch ((uint16_t) (descriptor[USB_EP_B_ATTRIBUTES] & USB_EP_TRNSMASK)) + { + /* Bulk Endpoint */ + case USB_EP_BULK: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(receive) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_BULK | USB_CFG_DBLB | USB_SHTNAKFIELD | USB_DIR_H_IN); + pipe_no = usb_hvnd_get_pipe_no(p_utr, USB_EP_BULK, USB_PIPE_DIR_IN); + } + else + { + /* OUT(send) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_BULK | USB_CFG_DBLB | USB_DIR_H_OUT); + pipe_no = usb_hvnd_get_pipe_no(p_utr, USB_EP_BULK, USB_PIPE_DIR_OUT); + } + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == p_utr->ip) + { + pipe_cfg |= (uint16_t) (USB_CFG_CNTMD); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + /* Interrupt Endpoint */ + case USB_EP_INT: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(receive) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_INT | USB_DIR_H_IN); + pipe_no = usb_hvnd_get_pipe_no(p_utr, USB_EP_INT, USB_PIPE_DIR_IN); + } + else + { + /* OUT(send) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_INT | USB_DIR_H_OUT); + pipe_no = usb_hvnd_get_pipe_no(p_utr, USB_EP_INT, USB_PIPE_DIR_OUT); + } + + /* Get value for Interval Error Detection Interval */ + pipe_peri = usb_hstd_get_pipe_peri_value(speed, descriptor[USB_EP_B_INTERVAL]); + + break; + } + + default: + { + return USB_NULL; /* Error */ + break; + } + } + + /* Check Pipe no. */ + if (USB_NULL != pipe_no) + { + /* Endpoint number set */ + pipe_cfg = (uint16_t) (pipe_cfg | (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_NUMMASK)); + + /* set max packet size */ + pipe_maxp = (uint16_t) ((uint16_t) descriptor[USB_EP_B_MAXPACKETSIZE_L] | (address << USB_DEVADDRBIT)); + pipe_maxp = (uint16_t) (pipe_maxp | ((uint16_t) descriptor[USB_EP_B_MAXPACKETSIZE_H] << 8)); + + /* Store PIPE reg set value. */ + pipe_table_work->pipe_cfg = pipe_cfg; + pipe_table_work->pipe_maxp = pipe_maxp; + pipe_table_work->pipe_peri = pipe_peri; + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == p_utr->ip) + { + /* PIPEBUF is USBA module only */ + pipe_buf = usb_hstd_get_pipe_buf_value(pipe_no); + pipe_table_work->pipe_buf = pipe_buf; + } + #endif /* #if defined (USB_HIGH_SPEED_MODULE) */ + } + + return pipe_no; +} + +/****************************************************************************** + * End of function usb_hvnd_make_pipe_reg_info + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_get_pipe_no + * Description : Get PIPE No. + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure + * : uint16_t address : USB Device address + * : uint16_t class : USB Device class(USB_HVND/USB_HCDC/USB_HHID/USB_HMSC/USB_HUB) + * : uint8_t type : Transfer Type.(USB_EP_BULK/USB_EP_INT) + * : uint8_t dir : (USB_PIPE_DIR_IN/USB_PIPE_DIR_OUT) + * Return value : Pipe no (USB_PIPE1->USB_PIPE9:OK, USB_NULL:Error) + ******************************************************************************/ +static uint8_t usb_hvnd_get_pipe_no (usb_utr_t * p_utr, uint8_t type, uint8_t dir) +{ + #if (USB_CFG_DMA == USB_CFG_DISABLE) + (void) dir; + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + uint8_t pipe_no = USB_NULL; + uint8_t pipe; + + if (USB_EP_BULK == type) + { + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Check direction and transfer validity */ + if (((USB_PIPE_DIR_IN == dir) && (p_utr->p_transfer_rx != 0)) || + ((USB_PIPE_DIR_IN != dir) && (p_utr->p_transfer_tx != 0))) + { + pipe_no = pipe; /* Set free pipe */ + break; + } + } + else + { + /* Nothing */ + } + + #else + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Check Free pipe */ + pipe_no = pipe; /* Set Free pipe */ + break; + } + #endif + } + } + + if (USB_EP_INT == type) + { + /* Interrupt PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_INT_PIPE_START; pipe < (USB_INT_PIPE_END + 1); pipe++) + { + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Check Free pipe */ + pipe_no = pipe; /* Set Free pipe */ + break; + } + } + } + + return pipe_no; +} + +/****************************************************************************** + * End of function usb_hvnd_get_pipe_no + ******************************************************************************/ + #endif /* defined(USB_CFG_HVND_USE) */ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hhubsys.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hhubsys.c new file mode 100644 index 0000000000..0b3d0a87ca --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hhubsys.c @@ -0,0 +1,3700 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if USB_CFG_HUB == USB_CFG_ENABLE + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/* Condition compilation by the difference of the devices */ + #define USB_MAXHUB ((uint16_t) 1U) + + #define USB_HUB_CLSDATASIZE ((uint16_t) 512U) + #define USB_HUB_QOVR ((uint16_t) 0xFFFEU) + + #define USB_BIT_PORT_CONNECTION (0x00000001U) + #define USB_BIT_PORT_ENABLE (0x00000002U) + #define USB_BIT_PORT_SUSPEND (0x00000004U) + #define USB_BIT_PORT_OVER_CURRENT (0x00000008U) + #define USB_BIT_PORT_RESET (0x00000010U) + #define USB_BIT_PORT_POWER (0x00000100U) + #define USB_BIT_PORT_LOW_SPEED (0x00000200U) + #define USB_BIT_C_PORT_CONNECTION (0x00010000U) + #define USB_BIT_C_PORT_ENABLE (0x00020000U) + #define USB_BIT_C_PORT_SUSPEND (0x00040000U) + #define USB_BIT_C_PORT_OVER_CURRENT (0x00080000U) + #define USB_BIT_C_PORT_RESET (0x00100000U) + +/* HUB down port */ + #define USB_HUBDOWNPORT (4U) /* HUB down port (MAX15) */ + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ +typedef struct +{ + uint16_t up_addr; /* Up-address */ + uint16_t up_port_num; /* Up-port num */ + uint16_t port_num; /* Port number */ + uint16_t pipe_num; /* Pipe number */ +} usb_hub_info_t; + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ +static uint16_t usb_hhub_chk_config(uint16_t ** table, uint16_t spec); +static uint16_t usb_hhub_chk_interface(uint16_t ** table, uint16_t spec); +static uint16_t usb_hhub_pipe_info(usb_utr_t * ptr, uint8_t * table, uint16_t speed, uint16_t length); +static void usb_hhub_port_detach(usb_utr_t * ptr, uint16_t hubaddr, uint16_t portnum); +static void usb_hhub_selective_detach(usb_utr_t * ptr, uint16_t devaddr); +static void usb_hhub_trans_start(usb_utr_t * ptr, + uint16_t hubaddr, + uint32_t size, + uint8_t * table, + usb_cb_t complete); +static void usb_hhub_trans_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +static uint16_t usb_hhub_get_new_devaddr(usb_utr_t * ptr); +static uint16_t usb_hhub_get_hubaddr(usb_utr_t * ptr, uint16_t pipenum); +static uint16_t usb_hhub_get_cnn_devaddr(usb_utr_t * ptr, uint16_t hubaddr, uint16_t portnum); +static uint16_t usb_hhub_port_set_feature(usb_utr_t * ptr, + uint16_t hubaddr, + uint16_t port, + uint16_t command, + usb_cb_t complete); +static uint16_t usb_hhub_port_clr_feature(usb_utr_t * ptr, + uint16_t hubaddr, + uint16_t port, + uint16_t command, + usb_cb_t complete); +static void usb_hhub_init_down_port(usb_utr_t * ptr, uint16_t hubaddr, usb_clsinfo_t * mess); +static void usb_hhub_new_connect(usb_utr_t * ptr, uint16_t hubaddr, uint16_t portnum, usb_clsinfo_t * mess); +static uint16_t usb_hhub_port_attach(uint16_t hubaddr, uint16_t portnum, usb_clsinfo_t * mess); +static void usb_hhub_port_reset(usb_utr_t * ptr, uint16_t hubaddr, uint16_t portnum, usb_clsinfo_t * mess); + + #if (BSP_CFG_RTOS == 0) +static void usb_hhub_enumeration(usb_clsinfo_t * mess); +static void usb_hhub_event(usb_clsinfo_t * mess); +static void usb_hhub_specified_path(usb_clsinfo_t * mess); +static void usb_hhub_specified_path_wait(usb_clsinfo_t * mess, uint16_t times); +static void usb_hhub_class_request_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +static void usb_hhub_check_request(usb_utr_t * ptr, uint16_t result); +static uint16_t usb_hhub_request_result(uint16_t checkerr); + + #endif /* (BSP_CFG_RTOS == 0) */ + +static void usb_hhub_initial(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +static void usb_hhub_check_class(usb_utr_t * ptr, uint16_t ** table); + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + +/* Control transfer message */ +usb_utr_t g_usb_shhub_ctrl_mess[USB_NUM_USBIP]; + +/* Data transfer message */ +usb_utr_t g_usb_shhub_data_mess[USB_NUM_USBIP][USB_MAXDEVADDR + 1U]; + +/* HUB descriptor */ +uint8_t g_usb_hhub_descriptor[USB_NUM_USBIP][USB_CONFIGSIZE]; + +/* HUB status data */ +uint8_t g_usb_hhub_data[USB_NUM_USBIP][USB_MAXDEVADDR + 1U][8]; + +/* HUB down port status */ +uint16_t g_usb_shhub_down_port[USB_NUM_USBIP][USB_MAXDEVADDR + 1U]; + +/* Down port remote wake up */ +uint16_t g_usb_shhub_remote[USB_NUM_USBIP][USB_MAXDEVADDR + 1U]; + +/* Up-hubaddr, up-hubport, portnum, pipenum */ +usb_hub_info_t g_usb_shhub_info_data[USB_NUM_USBIP][USB_MAXDEVADDR + 1U]; +uint16_t g_usb_shhub_number[USB_NUM_USBIP]; +uint16_t g_usb_shhub_class_request[USB_NUM_USBIP][5]; + +/* Condition compilation by the difference of USB function */ + #if USB_NUM_USBIP == 2 +uint16_t g_usb_shhub_class_seq[USB_NUM_USBIP] = {USB_SEQ_0, USB_SEQ_0}; +uint16_t g_usb_shhub_init_seq[USB_NUM_USBIP] = {USB_SEQ_0, USB_SEQ_0}; +uint16_t g_usb_shhub_init_port[USB_NUM_USBIP] = {USB_HUB_P1, USB_HUB_P1}; +uint16_t g_usb_shhub_event_seq[USB_NUM_USBIP] = {USB_SEQ_0, USB_SEQ_0}; +uint16_t g_usb_shhub_event_port[USB_NUM_USBIP] = {USB_HUB_P1, USB_HUB_P1}; +uint16_t g_usb_shhub_attach_seq[USB_NUM_USBIP] = {USB_SEQ_0, USB_SEQ_0}; +uint16_t g_usb_shhub_reset_seq[USB_NUM_USBIP] = {USB_SEQ_0, USB_SEQ_0}; +uint16_t g_usb_shhub_info[USB_NUM_USBIP] = {USB_SEQ_0, USB_SEQ_0}; +uint16_t g_usb_shhub_hub_addr[USB_NUM_USBIP] = {USB_SEQ_0, USB_SEQ_0}; +uint16_t g_usb_shhub_process[USB_NUM_USBIP] = {USB_SEQ_0, USB_SEQ_0}; + #else /* USB_NUM_USBIP == 2 */ +uint16_t g_usb_shhub_class_seq[USB_NUM_USBIP] = {USB_SEQ_0}; +uint16_t g_usb_shhub_init_seq[USB_NUM_USBIP] = {USB_SEQ_0}; +uint16_t g_usb_shhub_init_port[USB_NUM_USBIP] = {USB_HUB_P1}; +uint16_t g_usb_shhub_event_seq[USB_NUM_USBIP] = {USB_SEQ_0}; +uint16_t g_usb_shhub_event_port[USB_NUM_USBIP] = {USB_HUB_P1}; +uint16_t g_usb_shhub_attach_seq[USB_NUM_USBIP] = {USB_SEQ_0}; +uint16_t g_usb_shhub_reset_seq[USB_NUM_USBIP] = {USB_SEQ_0}; +uint16_t g_usb_shhub_info[USB_NUM_USBIP] = {USB_SEQ_0}; +uint16_t g_usb_shhub_hub_addr[USB_NUM_USBIP] = {USB_SEQ_0}; +uint16_t g_usb_shhub_process[USB_NUM_USBIP] = {USB_SEQ_0}; + + #endif /* USB_NUM_USBIP == 2 */ + +uint8_t * g_p_usb_shhub_device_table[USB_NUM_USBIP]; +uint8_t * g_p_usb_shhub_config_table[USB_NUM_USBIP]; +uint8_t * g_p_usb_shhub_interface_table[USB_NUM_USBIP]; +uint16_t g_usb_shhub_spec[USB_NUM_USBIP]; +uint16_t g_usb_shhub_speed[USB_NUM_USBIP]; +uint16_t g_usb_shhub_dev_addr[USB_NUM_USBIP]; + +const uint16_t g_usb_hhub_tpl[4] = +{ + USB_CFG_HUB_TPLCNT, /* Number of tpl table */ + 0, /* Reserved */ + USB_CFG_HUB_TPL /* Vendor ID, Product ID */ +}; + +/****************************************************************************** + * Renesas Abstracted Hub Driver API functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_open + * Description : HUB sys open + * Arguments : uint16_t devaddr : Device address + * : uint16_t data2 : Not used + * Return value : usb_er_t : Error Info + ******************************************************************************/ +void usb_hhub_open (usb_utr_t * ptr, uint16_t devaddr, uint16_t data2) +{ + FSP_PARAMETER_NOT_USED(data2); + usb_er_t err = USB_ERROR; + usb_er_t err2; + usb_mh_t p_blf; + usb_mgrinfo_t * mp; + uint16_t hubaddr; + + hubaddr = (uint16_t) (devaddr << USB_DEVADDRBIT); + + if (USB_MAXHUB != g_usb_shhub_number[ptr->ip]) + { + /* Wait 10ms */ + usb_cpu_delay_xms((uint16_t) 10); + err = USB_PGET_BLK(USB_HUB_MPL, &p_blf, ptr->ip); + if (USB_OK == err) + { + mp = (usb_mgrinfo_t *) p_blf; + mp->msghead = (usb_mh_t) USB_NULL; + #if (BSP_CFG_RTOS != 0) + mp->msginfo = USB_MSG_HUB_START; + #else /* #if (BSP_CFG_RTOS != 0) */ + mp->msginfo = USB_MSG_CLS_INIT; + #endif /* #if (BSP_CFG_RTOS != 0) */ + mp->keyword = devaddr; + + mp->ipp = ptr->ipp; + mp->ip = ptr->ip; + + /* Send message */ + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) p_blf); + if (USB_OK != err) + { + /* Send Message failure */ + USB_PRINTF1("### hHubOpen snd_msg error (%ld)\n", err); + err2 = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) p_blf); + if (USB_OK != err2) + { + USB_PRINTF1("### hHubOpen rel_blk error (%ld)\n", err2); + } + } + } + else + { + /* Release memory block failure */ + USB_PRINTF1("### hHubOpen pget_blk error (%ld)\n", err); + + /* WAIT_LOOP */ + while (1) + { + /* Non */ + } + } + + /* Pipe number set */ + g_usb_shhub_info_data[ptr->ip][devaddr].pipe_num = USB_HUB_PIPE; + + /* HUB down port status */ + g_usb_shhub_down_port[ptr->ip][devaddr] = 0; + + /* Down port remote wake up */ + g_usb_shhub_remote[ptr->ip][devaddr] = 0; + g_usb_pipe_table[ptr->ip][USB_HUB_PIPE].pipe_maxp |= hubaddr; + + #if (BSP_CFG_RTOS == 0) + g_usb_shhub_process[ptr->ip] = USB_MSG_CLS_INIT; + #endif /* (BSP_CFG_RTOS == 0) */ + usb_hstd_set_pipe_reg(ptr, USB_HUB_PIPE); + + g_usb_shhub_number[ptr->ip]++; + } +} + +/****************************************************************************** + * End of function usb_hhub_open + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_close + * Description : HUB sys close + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : Hub address + * : uint16_t data2 : Not used + * Return value : usb_er_t : Error Info + ******************************************************************************/ +void usb_hhub_close (usb_utr_t * ptr, uint16_t hubaddr, uint16_t data2) +{ + FSP_PARAMETER_NOT_USED(data2); + uint16_t md, i; + usb_hcdreg_t * driver; + uint16_t devaddr; + + /* WAIT_LOOP */ + for (i = 1; i <= g_usb_shhub_info_data[ptr->ip][hubaddr].port_num; i++) + { + /* Now down port device search */ + devaddr = usb_hhub_get_cnn_devaddr(ptr, hubaddr, i); + if (0 != devaddr) + { + /* HUB down port selective disconnect */ + usb_hhub_selective_detach(ptr, devaddr); + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (devaddr == driver->devaddr) + { + (*driver->devdetach)(ptr, driver->devaddr, (uint16_t) USB_NO_ARG); + driver->rootport = USB_NOPORT; /* Root port */ + driver->devaddr = USB_NODEVICE; /* Device devaddress */ + driver->devstate = USB_DETACHED; /* Device state */ + } + } + } + } + + g_usb_shhub_number[ptr->ip]--; + + /* Set pipe information */ + /* WAIT_LOOP */ + for (i = 1; i <= USB_MAXDEVADDR; i++) + { + g_usb_shhub_info_data[ptr->ip][i].up_addr = 0; /* Up-address clear */ + g_usb_shhub_info_data[ptr->ip][i].up_port_num = 0; /* Up-port num clear */ + g_usb_shhub_info_data[ptr->ip][i].port_num = 0; /* Port number clear */ + g_usb_shhub_info_data[ptr->ip][i].pipe_num = 0; /* Pipe number clear */ + } + + g_usb_shhub_down_port[ptr->ip][hubaddr] = 0; + g_usb_shhub_remote[ptr->ip][hubaddr] = 0; + usb_hstd_clr_pipe_table(ptr->ip, hubaddr); +} + +/****************************************************************************** + * End of function usb_hhub_close + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_registration + * Description : Registration Processing for HUB driver + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : usb_hcdreg_t *callback : Pointer ot usb_hcdreg_t structure. + * Return value : none + ******************************************************************************/ +void usb_hhub_registration (usb_utr_t * ptr, usb_hcdreg_t * callback) +{ + usb_hcdreg_t driver; + + /* Driver registration */ + if (USB_NULL == callback) + { + /* Target peripheral list */ + driver.p_tpl = (uint16_t *) &g_usb_hhub_tpl[0]; + } + else + { + /* Target peripheral list */ + driver.p_tpl = callback->p_tpl; + } + + driver.ifclass = (uint16_t) USB_IFCLS_HUB; /* Interface Class */ + driver.classinit = &usb_hhub_initial; /* Driver init */ + driver.classcheck = &usb_hhub_check_class; /* Driver check */ + driver.devconfig = (usb_cb_t) &usb_hhub_open; /* Device configured */ + driver.devdetach = (usb_cb_t) &usb_hhub_close; /* Device detach */ + driver.devsuspend = &usb_hstd_dummy_function; /* Device suspend */ + driver.devresume = &usb_hstd_dummy_function; /* Device resume */ + + usb_hstd_driver_registration(ptr, (usb_hcdreg_t *) &driver); +} + +/****************************************************************************** + * End of function usb_hhub_registration + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_get_hub_information + * Description : Read HUB-Descriptor + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : hub address + * : usb_cb_t complete : callback function + * Return value : uint16_t : DONE/ERROR + ******************************************************************************/ +uint16_t usb_hhub_get_hub_information (usb_utr_t * ptr, uint16_t hubaddr, usb_cb_t complete) +{ + usb_er_t qerr; + + /* Request */ + g_usb_shhub_class_request[ptr->ip][0] = USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_CLASS | USB_DEVICE; + g_usb_shhub_class_request[ptr->ip][1] = USB_HUB_DESCRIPTOR; + g_usb_shhub_class_request[ptr->ip][2] = 0; + g_usb_shhub_class_request[ptr->ip][3] = 0x0047; + g_usb_shhub_class_request[ptr->ip][4] = hubaddr; /* Device address */ + + /* HUB Descriptor */ + g_usb_shhub_ctrl_mess[ptr->ip].keyword = USB_PIPE0; + g_usb_shhub_ctrl_mess[ptr->ip].p_tranadr = (void *) &g_usb_hhub_descriptor[ptr->ip][0]; + g_usb_shhub_ctrl_mess[ptr->ip].tranlen = (uint32_t) g_usb_shhub_class_request[ptr->ip][3]; + g_usb_shhub_ctrl_mess[ptr->ip].p_setup = g_usb_shhub_class_request[ptr->ip]; + g_usb_shhub_ctrl_mess[ptr->ip].segment = USB_TRAN_END; + g_usb_shhub_ctrl_mess[ptr->ip].complete = complete; + + g_usb_shhub_ctrl_mess[ptr->ip].ipp = ptr->ipp; + g_usb_shhub_ctrl_mess[ptr->ip].ip = ptr->ip; + + /* Transfer start */ + #if (BSP_CFG_RTOS != 0) + qerr = usb_hstd_transfer_start_req(&g_usb_shhub_ctrl_mess[ptr->ip]); + if (USB_QOVR == qerr) + { + /** Submit overlap error **/ + /** Retry **/ + /* WAIT_LOOP */ + do + { + usb_cpu_delay_xms((uint16_t) 10); + qerr = usb_hstd_transfer_start_req(&g_usb_shhub_ctrl_mess[ptr->ip]); + } while (USB_QOVR == qerr); + } + + if (USB_OK == qerr) + { + qerr = class_trans_wait_tmo(ptr, (uint16_t) 5000); + + return (uint16_t) qerr; + } + else + { + return USB_ERROR; + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + qerr = usb_hstd_transfer_start_req(&g_usb_shhub_ctrl_mess[ptr->ip]); + if (USB_QOVR == qerr) + { + return USB_HUB_QOVR; + } + return USB_OK; + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_get_hub_information + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_get_port_information + * Description : Get the port information + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : hub address + * : uint16_t port : down port number + * : usb_cb_t complete : Callback function + * Return value : uint16_t : DONE/ERROR + ******************************************************************************/ +uint16_t usb_hhub_get_port_information (usb_utr_t * ptr, uint16_t hubaddr, uint16_t port, usb_cb_t complete) +{ + usb_er_t qerr; + + /* Request */ + g_usb_shhub_class_request[ptr->ip][0] = USB_GET_STATUS | USB_DEV_TO_HOST | USB_CLASS | USB_OTHER; + g_usb_shhub_class_request[ptr->ip][1] = 0; + g_usb_shhub_class_request[ptr->ip][2] = port; /* Port number */ + g_usb_shhub_class_request[ptr->ip][3] = 4; + g_usb_shhub_class_request[ptr->ip][4] = hubaddr; /* Device address */ + + /* Port GetStatus */ + g_usb_shhub_ctrl_mess[ptr->ip].keyword = USB_PIPE0; + g_usb_shhub_ctrl_mess[ptr->ip].p_tranadr = (void *) &g_usb_hhub_data[ptr->ip][hubaddr][0]; + g_usb_shhub_ctrl_mess[ptr->ip].tranlen = (uint32_t) g_usb_shhub_class_request[ptr->ip][3]; + g_usb_shhub_ctrl_mess[ptr->ip].p_setup = g_usb_shhub_class_request[ptr->ip]; + g_usb_shhub_ctrl_mess[ptr->ip].segment = USB_TRAN_END; + g_usb_shhub_ctrl_mess[ptr->ip].complete = complete; + + g_usb_shhub_ctrl_mess[ptr->ip].ipp = ptr->ipp; + g_usb_shhub_ctrl_mess[ptr->ip].ip = ptr->ip; + + /* Transfer start */ + #if (BSP_CFG_RTOS != 0) + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + if (USB_QOVR == qerr) + { + /** Submit overlap error **/ + /** Retry **/ + /* WAIT_LOOP */ + do + { + usb_cpu_delay_xms((uint16_t) 10); + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + } while (USB_QOVR == qerr); + } + + if (USB_OK == qerr) + { + qerr = class_trans_wait_tmo(ptr, (uint16_t) 5000); + + return (uint16_t) qerr; + } + else + { + return USB_ERROR; + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + if (USB_QOVR == qerr) + { + return USB_HUB_QOVR; + } + return USB_OK; + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_get_port_information + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_task + * Description : HUB task + * Arguments : void * stacd : Start Code of Hub Task + * Return value : none + ******************************************************************************/ +void usb_hhub_task (void * stacd) +{ + FSP_PARAMETER_NOT_USED(stacd); + #if (BSP_CFG_RTOS != 0) + usb_utr_t * mess; + usb_utr_t * ptr; + usb_er_t err; + uint16_t hubaddr, pipenum, portnum, retval, devaddr; + uint32_t port_status; + + /* WAIT_LOOP */ + while (1) + { + /* Receive message */ + err = USB_TRCV_MSG(USB_HUB_MBX, (usb_msg_t **) &mess, (usb_tm_t) 0); + if (USB_OK != err) + { + continue; + } + + ptr = (usb_utr_t *) mess; + + switch (mess->msginfo) + { + case USB_MSG_HUB_START: + { + hubaddr = (uint16_t) (mess->keyword); + + /* Store Hub Down Port Address */ + g_usb_shhub_hub_addr[ptr->ip] = hubaddr; + + /* Hub Down Ports Initialize */ + usb_hhub_init_down_port(ptr, hubaddr, (usb_clsinfo_t *) USB_NULL); + + /* Release memory block */ + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) mess); + if (USB_OK != err) + { + USB_PRINTF0("### HUB Class rel_blk error !\n"); + } + + break; + } + + case USB_MSG_HUB_SUBMITRESULT: + { + /* Get Hub address from pipe number */ + pipenum = mess->keyword; + hubaddr = usb_hhub_get_hubaddr(ptr, pipenum); + + switch (mess->status) + { + case USB_DATA_SHT: + + /*USB_PRINTF1("*** receive short(pipe %d : HUB) !\n", pipenum);*/ + /* Continue */ + /* Direction is in then data receive end */ + case USB_DATA_OK: + { + if (USB_DEFAULT == g_usb_hstd_mgr_mode[ptr->ip]) + { + usb_cpu_delay_xms((uint16_t) 10); + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) mess); + if (USB_OK != err) + { + USB_PRINTF0("### HUB task snd_msg error\n"); + } + } + else + { + /* WAIT_LOOP */ + for (portnum = USB_HUB_P1; + portnum <= g_usb_shhub_info_data[ptr->ip][hubaddr].port_num; + portnum++) + { + /* Hub and Port Status Change Bitmap(b0:Hub,b1:DownPort1change detected,b2:DownPort2,...) */ + if (0 != (g_usb_hhub_data[ptr->ip][hubaddr][0] & USB_BITSET(portnum))) + { + USB_PRINTF1(" *** HUB port %d \t", portnum); + usb_cpu_delay_xms((uint16_t) 20); + + /* GetStatus request */ + retval = usb_hhub_get_port_information(ptr, hubaddr, portnum, class_trans_result); + if (USB_OK == retval) + { + port_status = (uint32_t) 0; + port_status = (uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][0]; + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][1] << 8); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][2] << 16); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][3] << 24); + USB_PRINTF2(" [port/status] : %d, 0x%08x\n", portnum, port_status); + + if (0 != (port_status & USB_BIT_C_PORT_CONNECTION)) /* C_PORT_CONNECTION */ + { + retval = usb_hhub_port_clr_feature(ptr, + hubaddr, + portnum, + (uint16_t) USB_HUB_C_PORT_CONNECTION, + class_trans_result); + if (USB_OK == retval) + { + port_status = (uint32_t) 0; + port_status = (uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][0]; + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][1] << 8); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][2] << 16); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][3] << 24); + USB_PRINTF2(" [port/status] : %d, 0x%08x\n", portnum, port_status); + + if (0 != (port_status & USB_BIT_PORT_CONNECTION)) /* PORT_CONNECTION */ + { + if (0 == + (g_usb_shhub_down_port[ptr->ip][hubaddr] & USB_BITSET(portnum))) + { + usb_hhub_new_connect(mess, + hubaddr, + portnum, + (usb_clsinfo_t *) USB_NULL); + } + } + else + { + /* Now down port device search */ + devaddr = usb_hhub_get_cnn_devaddr(ptr, hubaddr, portnum); + if (0 != devaddr) + { + usb_hhub_port_detach(ptr, hubaddr, portnum); + USB_PRINTF1(" Hubport disconnect address%d\n", devaddr); + g_usb_shhub_info_data[ptr->ip][devaddr].up_addr = 0; /* Up-address clear */ + g_usb_shhub_info_data[ptr->ip][devaddr].up_port_num = 0; /* Up-port num clear */ + g_usb_shhub_info_data[ptr->ip][devaddr].port_num = 0; /* Port number clear */ + g_usb_shhub_info_data[ptr->ip][devaddr].pipe_num = 0; /* Pipe number clear */ + } + } + } + } + else + { + /* Now down port device search */ + devaddr = usb_hhub_get_cnn_devaddr(ptr, hubaddr, portnum); + if (0 != (port_status & USB_BIT_PORT_ENABLE)) /* PORT_ENABLE */ + { + USB_PRINTF1(" Hubport error address%d\n", devaddr); + usb_hhub_port_clr_feature(ptr, + hubaddr, + portnum, + (uint16_t) USB_HUB_C_PORT_ENABLE, + class_trans_result); /* C_PORT_ENABLE */ + } + else if (0 != (port_status & USB_BIT_PORT_SUSPEND)) /* PORT_SUSPEND */ + { + USB_PRINTF1(" Hubport suspend(resume complete) address%d\n", devaddr); + usb_hhub_port_clr_feature(ptr, + hubaddr, + portnum, + (uint16_t) USB_HUB_C_PORT_SUSPEND, + class_trans_result); /* C_PORT_SUSPEND */ + } + else if (0 != (port_status & USB_BIT_C_PORT_OVER_CURRENT)) /* PORT_OVER_CURRENT */ + { + USB_PRINTF1(" Hubport over current address%d\n", devaddr); + usb_hhub_port_clr_feature(ptr, + hubaddr, + portnum, + (uint16_t) USB_HUB_C_PORT_OVER_CURRENT, + class_trans_result); /* C_PORT_OVER_CURRENT */ + } + else if (0 != (port_status & USB_BIT_PORT_RESET)) /* PORT_RESET */ + { + USB_PRINTF1(" Hubport reset(reset complete) address%d\n", devaddr); + usb_hhub_port_clr_feature(ptr, + hubaddr, + portnum, + (uint16_t) USB_HUB_C_PORT_RESET, + class_trans_result); /* C_PORT_RESET */ + } + else + { + /* None */ + } + } + } + } + } + + /* Next Command Check */ + usb_hhub_trans_start(ptr, + hubaddr, + (uint32_t) 1, + &g_usb_hhub_data[ptr->ip][hubaddr][0], + &usb_hhub_trans_complete); /* Get Hub and Port Status Change Bitmap */ + } + + break; + } + + case USB_DATA_STALL: + { + USB_PRINTF0("*** Data Read error. (STALL) !\n"); + + /* CLEAR_FEATURE */ + usb_hstd_clr_stall(mess, pipenum, (usb_cb_t) &class_trans_result); + break; + } + + case USB_DATA_OVR: + { + USB_PRINTF0("### receiver over. !\n"); + break; + } + + case USB_DATA_STOP: + { + USB_PRINTF0("### receiver stop. !\n"); + break; + } + + default: + { + USB_PRINTF0("### HUB Class Data Read error !\n"); + break; + } + } + + #if (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 2) */ + vPortFree(mess); + #endif /* #if (BSP_CFG_RTOS == 2) */ + break; + } + + default: + { + /* Release memory block */ + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) mess); + if (USB_OK != err) + { + USB_PRINTF0("### HUB Class rel_blk error !\n"); + } + + break; + } + } + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + usb_utr_t * mess; + usb_er_t err; + + /* Receive message */ + err = USB_TRCV_MSG(USB_HUB_MBX, (usb_msg_t **) &mess, (usb_tm_t) 0); + if (USB_OK != err) + { + return; + } + + switch (mess->msginfo) + { + case USB_MSG_CLS_CHECKREQUEST: + { + /* USB HUB Class Enumeration */ + usb_hhub_enumeration((usb_clsinfo_t *) mess); + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) mess); + if (USB_OK != err) + { + /* Release Memory block failure */ + USB_PRINTF0("### USB HUB Task rel_blk error\n"); + } + + break; + } + + case USB_MSG_CLS_INIT: + { + /* Down port initialize */ + usb_hhub_init_down_port(mess, (uint16_t) 0, (usb_clsinfo_t *) mess); + break; + } + + /* Enumeration waiting of other device */ + case USB_MSG_CLS_WAIT: + { + mess->msginfo = USB_MSG_MGR_AORDETACH; + err = USB_SND_MSG(USB_MGR_MBX, (usb_msg_t *) mess); + if (USB_OK != err) + { + /* Send Message failure */ + USB_PRINTF0("### USB HUB enuwait snd_msg error\n"); + } + + break; + } + + case USB_MSG_HUB_EVENT: + { + usb_hhub_event((usb_clsinfo_t *) mess); + break; + } + + case USB_MSG_HUB_ATTACH: + { + /* Hub Port attach */ + usb_hhub_port_attach((uint16_t) 0, (uint16_t) 0, (usb_clsinfo_t *) mess); + break; + } + + case USB_MSG_HUB_RESET: + { + /* Hub Reset */ + usb_hhub_port_reset(mess, (uint16_t) 0, (uint16_t) 0, (usb_clsinfo_t *) mess); + break; + } + + default: + { + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) mess); + if (USB_OK != err) + { + USB_PRINTF0("### USB HUB rel_blk error\n"); + } + + break; + } + } + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_task + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hhub_enumeration + * Description : USB HUB Class Enumeration + * Arguments : usb_clsinfo_t *ptr : Pointer to usb_clsinfo_t structure. + * Return value : none + ******************************************************************************/ +static void usb_hhub_enumeration (usb_clsinfo_t * ptr) +{ + uint16_t checkerr, retval; + uint8_t string; + uint16_t * table[8]; + + checkerr = ptr->result; + table[0] = (uint16_t *) g_p_usb_shhub_device_table[ptr->ip]; + table[1] = (uint16_t *) g_p_usb_shhub_config_table[ptr->ip]; + table[2] = (uint16_t *) g_p_usb_shhub_interface_table[ptr->ip]; + + /* Manager Mode Change */ + switch (g_usb_shhub_class_seq[ptr->ip]) + { + case USB_SEQ_0: + { + checkerr = USB_OK; + + /* Descriptor check */ + retval = usb_hhub_chk_config((uint16_t **) &table, (uint16_t) g_usb_shhub_spec[ptr->ip]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Configuration descriptor error !\n"); + checkerr = USB_ERROR; + break; + } + + /* Interface Descriptor check */ + retval = usb_hhub_chk_interface((uint16_t **) &table, (uint16_t) g_usb_shhub_spec[ptr->ip]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Interface descriptor error !\n"); + checkerr = USB_ERROR; + break; + } + + /* String descriptor */ + g_usb_shhub_process[ptr->ip] = USB_MSG_CLS_CHECKREQUEST; + usb_hhub_get_string_descriptor1(ptr, + g_usb_shhub_dev_addr[ptr->ip], + (uint16_t) 15, + (usb_cb_t) &usb_hhub_class_request_complete); + break; + } + + case USB_SEQ_1: + { + /* String descriptor check */ + retval = usb_hhub_get_string_descriptor1check(checkerr); + if (USB_OK == retval) + { + string = g_p_usb_shhub_device_table[ptr->ip][15]; + + /* String descriptor */ + g_usb_shhub_process[ptr->ip] = USB_MSG_CLS_CHECKREQUEST; + usb_hhub_get_string_descriptor2(ptr, + g_usb_shhub_dev_addr[ptr->ip], + (uint16_t) string, + (usb_cb_t) &usb_hhub_class_request_complete); + } + else + { + /* If USB_ERROR, Go case 3 (checkerr==USB_ERROR) */ + g_usb_shhub_class_seq[ptr->ip] = USB_SEQ_2; + + /* Next sequence */ + usb_hhub_check_request(ptr, USB_ERROR); + checkerr = USB_OK; + } + + break; + } + + case USB_SEQ_2: + { + /* String descriptor check */ + retval = usb_hhub_get_string_descriptor_to_check(checkerr); + if (USB_OK == retval) + { + /* Next sequence */ + usb_hhub_check_request(ptr, checkerr); + } + + break; + } + + case USB_SEQ_3: + { + /* String descriptor check */ + if (USB_OK == checkerr) + { + if (g_usb_hstd_class_data[ptr->ip][0] < (uint8_t) ((32 * 2) + 2)) + { + g_usb_hstd_class_data[ptr->ip][0] = (uint8_t) (g_usb_hstd_class_data[ptr->ip][0] / 2); + g_usb_hstd_class_data[ptr->ip][0] = (uint8_t) (g_usb_hstd_class_data[ptr->ip][0] - 1); + } + else + { + g_usb_hstd_class_data[ptr->ip][0] = (uint8_t) 32; + } + } + else + { + USB_PRINTF0("*** Product name error\n"); + checkerr = USB_OK; + } + + /* Get HUB descriptor */ + g_usb_shhub_process[ptr->ip] = USB_MSG_CLS_CHECKREQUEST; + checkerr = + usb_hhub_get_hub_information(ptr, g_usb_shhub_dev_addr[ptr->ip], usb_hhub_class_request_complete); + + /* Submit overlap error */ + if (USB_HUB_QOVR == checkerr) + { + usb_hhub_specified_path_wait(ptr, (uint16_t) 10); + } + + break; + } + + case USB_SEQ_4: + { + /* Get HUB descriptor Check */ + retval = usb_hhub_request_result(checkerr); + if (USB_OK == retval) + { + usb_hhub_check_request(ptr, checkerr); /* Next sequence */ + } + + break; + } + + case USB_SEQ_5: + { + /* Get HUB descriptor Check */ + if (USB_OK == checkerr) + { + retval = USB_OK; + } + else + { + USB_PRINTF0("### HUB Descriptor over\n"); + checkerr = USB_ERROR; + } + + /* Pipe Information table set */ + switch (g_usb_shhub_spec[ptr->ip]) + { + case USB_FSHUB: /* Full Speed Hub */ + { + if (USB_FSCONNECT == g_usb_shhub_speed[ptr->ip]) + { + retval = usb_hhub_pipe_info(ptr, + (uint8_t *) g_p_usb_shhub_interface_table[ptr->ip], + g_usb_shhub_speed[ptr->ip], + (uint16_t) g_p_usb_shhub_config_table[ptr->ip][2]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Device information error(HUB) !\n"); + checkerr = USB_ERROR; + } + } + else + { + USB_PRINTF0("### HUB Descriptor speed error\n"); + checkerr = USB_ERROR; + } + + break; + } + + case USB_HSHUBS: /* Hi Speed Hub(Single) */ + { + if (USB_HSCONNECT == g_usb_shhub_speed[ptr->ip]) + { + retval = usb_hhub_pipe_info(ptr, + (uint8_t *) g_p_usb_shhub_interface_table[ptr->ip], + g_usb_shhub_speed[ptr->ip], + (uint16_t) g_p_usb_shhub_config_table[ptr->ip][2]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Device information error(HUB) !\n"); + checkerr = USB_ERROR; + } + } + else + { + USB_PRINTF0("### HUB Descriptor speed error\n"); + checkerr = USB_ERROR; + } + + break; + } + + case USB_HSHUBM: /* Hi Speed Hub(Multi) */ + { + if (USB_HSCONNECT == g_usb_shhub_speed[ptr->ip]) + { + /* Set pipe information */ + retval = usb_hhub_pipe_info(ptr, + (uint8_t *) g_p_usb_shhub_interface_table[ptr->ip], + g_usb_shhub_speed[ptr->ip], + (uint16_t) g_p_usb_shhub_config_table[ptr->ip][2]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Device information error(HUB) !\n"); + checkerr = USB_ERROR; + } + + /* Set pipe information */ + retval = usb_hhub_pipe_info(ptr, + (uint8_t *) g_p_usb_shhub_interface_table[ptr->ip], + g_usb_shhub_speed[ptr->ip], + (uint16_t) g_p_usb_shhub_config_table[ptr->ip][2]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Device information error(HUB) !\n"); + checkerr = USB_ERROR; + } + } + else + { + USB_PRINTF0("### HUB Descriptor speed error\n"); + checkerr = USB_ERROR; + } + + break; + } + + default: + { + checkerr = USB_ERROR; + break; + } + } + + /* Port number set */ + g_usb_shhub_info_data[ptr->ip][g_usb_shhub_dev_addr[ptr->ip]].port_num = g_usb_hhub_descriptor[ptr->ip][2]; + g_usb_shhub_process[ptr->ip] = USB_NULL; + usb_hstd_return_enu_mgr((usb_utr_t *) ptr, checkerr); /* Return to MGR */ + break; + } + + default: + { + break; + } + } + + switch (checkerr) + { + /* Driver open */ + case USB_OK: + { + g_usb_shhub_class_seq[ptr->ip]++; + break; + } + + /* Submit overlap error */ + case USB_HUB_QOVR: + { + break; + } + + /* Descriptor error */ + case USB_ERROR: + { + USB_PRINTF0("### Enumeration is stoped(ClassCode-ERROR)\n"); + g_usb_shhub_process[ptr->ip] = USB_NULL; + usb_hstd_return_enu_mgr((usb_utr_t *) ptr, USB_ERROR); /* Return to MGR */ + break; + } + + default: + { + g_usb_shhub_process[ptr->ip] = USB_NULL; + usb_hstd_return_enu_mgr((usb_utr_t *) ptr, USB_ERROR); /* Return to MGR */ + break; + } + } +} + +/****************************************************************************** + * End of function usb_hhub_enumeration + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hhub_init_down_port + * Description : Down port initialized + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : Hub address + * : usb_clsinfo_t *mess : Pointer to usb_clsinfo_t structure. + * Return value : none + ******************************************************************************/ +static void usb_hhub_init_down_port (usb_utr_t * ptr, uint16_t hubaddr, usb_clsinfo_t * mess) +{ + #if (BSP_CFG_RTOS != 0) + FSP_PARAMETER_NOT_USED(mess); + uint16_t portnum; + uint16_t retval; + uint32_t port_status; + + USB_PRINTF0("\nHHHHHHHHHHHHHHHHHHHHHHHHH\n"); + USB_PRINTF0(" USB HOST \n"); + USB_PRINTF0(" HUB CLASS DEMO \n"); + USB_PRINTF0("HHHHHHHHHHHHHHHHHHHHHHHHH\n\n"); + + /* Hub Port Power */ + /* WAIT_LOOP */ + for (portnum = USB_HUB_P1; portnum <= g_usb_shhub_info_data[ptr->ip][hubaddr].port_num; portnum++) + { + /* SetFeature Request */ + retval = usb_hhub_port_set_feature(ptr, hubaddr, portnum, (uint16_t) USB_HUB_PORT_POWER, class_trans_result); + if (USB_ERROR == retval) + { + USB_PRINTF0("### HUB Port Power error\n"); + } + } + + /* Hub Down port Initialization */ + /* WAIT_LOOP */ + for (portnum = USB_HUB_P1; portnum <= g_usb_shhub_info_data[ptr->ip][hubaddr].port_num; portnum++) + { + /* ClearFeature Request */ + retval = usb_hhub_port_clr_feature(ptr, + hubaddr, + portnum, + (uint16_t) USB_HUB_C_PORT_CONNECTION, + class_trans_result); + if (USB_ERROR == retval) + { + USB_PRINTF0("### HUB Port Clear error\n"); + } + } + + /* Delay */ + usb_cpu_delay_xms((uint16_t) 20); + + /* Check HUB's all down-ports */ + /* WAIT_LOOP */ + for (portnum = USB_HUB_P1; portnum <= g_usb_shhub_info_data[ptr->ip][hubaddr].port_num; portnum++) + { + USB_PRINTF2(" *** address %d down port %d \t", hubaddr, portnum); + + /* GetStatus Request */ + retval = usb_hhub_get_port_information(ptr, hubaddr, portnum, class_trans_result); + + if (USB_OK == retval) + { + port_status = (uint32_t) 0; + port_status = (uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][0]; + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][1] << 8); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][2] << 16); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][3] << 24); + USB_PRINTF2(" [port/status] : %d, 0x%08x\n", portnum, port_status); + + if (0 != (port_status & USB_BIT_PORT_CONNECTION)) + { + /* PORT CONNECTION */ + usb_hhub_new_connect(ptr, hubaddr, portnum, (usb_clsinfo_t *) USB_NULL); + } + } + } + + /* Port check end */ + usb_hhub_trans_start(ptr, hubaddr, (uint32_t) 1, &g_usb_hhub_data[ptr->ip][hubaddr][0], &usb_hhub_trans_complete); /* Get Hub and Port Status Change Bitmap */ + #else /* #if (BSP_CFG_RTOS != 0) */ + usb_er_t err; + uint16_t retval; + + hubaddr = g_usb_shhub_hub_addr[ptr->ip]; + retval = USB_OK; + + if (USB_MSG_CLS_INIT != g_usb_shhub_process[ptr->ip]) /* Check Hub Process */ + { + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) mess); + if (USB_OK != err) + { + USB_PRINTF0("### HUB snd_msg error\n"); /* Send Message failure */ + } + } + else + { + switch (g_usb_shhub_init_seq[ptr->ip]) + { + case USB_SEQ_0: /* HUB port power */ + { + hubaddr = mess->keyword; + g_usb_shhub_hub_addr[ptr->ip] = hubaddr; + + USB_PRINTF0("\nHHHHHHHHHHHHHHHHHHHHHHHHH\n"); + USB_PRINTF0(" USB HOST \n"); + USB_PRINTF0(" HUB CLASS DEMO \n"); + USB_PRINTF0("HHHHHHHHHHHHHHHHHHHHHHHHH\n\n"); + g_usb_shhub_init_seq[ptr->ip] = USB_SEQ_1; /* Next Sequence */ + g_usb_shhub_init_port[ptr->ip] = USB_HUB_P1; + usb_hhub_specified_path(mess); /* Next Process Selector */ + break; + } + + case USB_SEQ_1: /* Request */ + { + retval = usb_hhub_port_set_feature(ptr, + hubaddr, + g_usb_shhub_init_port[ptr->ip], + (uint16_t) USB_HUB_PORT_POWER, + usb_hhub_class_request_complete); /* SetFeature request */ + if (USB_HUB_QOVR == retval) /* Submit overlap error */ + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); + } + else + { + g_usb_shhub_init_port[ptr->ip]++; /* Next Port */ + g_usb_shhub_init_seq[ptr->ip] = USB_SEQ_2; /* Next Sequence */ + } + + break; + } + + case USB_SEQ_2: /* Request Result Check */ + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + if (g_usb_shhub_init_port[ptr->ip] > g_usb_shhub_info_data[ptr->ip][hubaddr].port_num) + { + g_usb_shhub_init_port[ptr->ip] = USB_HUB_P1; /* Port Clear */ + g_usb_shhub_init_seq[ptr->ip] = USB_SEQ_3; /* Next Sequence */ + usb_hhub_specified_path(mess); /* Next Process Selector */ + } + else + { + g_usb_shhub_init_seq[ptr->ip] = USB_SEQ_1; /* Loop Sequence */ + usb_hhub_specified_path(mess); /* Next Process Selector */ + } + } + + break; + } + + case USB_SEQ_3: /* HUB down port initialize */ + { + retval = usb_hhub_port_clr_feature(ptr, + hubaddr, + g_usb_shhub_init_port[ptr->ip], + (uint16_t) USB_HUB_C_PORT_CONNECTION, + usb_hhub_class_request_complete); /* Request */ + if (USB_HUB_QOVR == retval) /* Submit overlap error */ + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); + } + else + { + g_usb_shhub_init_port[ptr->ip]++; /* Next Port */ + g_usb_shhub_init_seq[ptr->ip] = USB_SEQ_4; /* Next Sequence */ + } + + break; + } + + /* Request Result Check */ + case USB_SEQ_4: + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + if (g_usb_shhub_init_port[ptr->ip] > g_usb_shhub_info_data[ptr->ip][hubaddr].port_num) + { + g_usb_shhub_init_seq[ptr->ip] = USB_SEQ_0; /* Sequence Clear */ + g_usb_shhub_init_port[ptr->ip] = USB_HUB_P1; /* Port Clear */ + g_usb_shhub_info[ptr->ip] = USB_MSG_CLS_INIT; + g_usb_shhub_process[ptr->ip] = USB_MSG_HUB_EVENT; /* Next Attach Process */ + usb_hhub_specified_path(mess); /* Next Process Selector */ + } + else + { + g_usb_shhub_init_seq[ptr->ip] = USB_SEQ_3; /* Loop Sequence */ + usb_hhub_specified_path(mess); /* Next Process Selector */ + } + } + + break; + } + + default: + { + retval = USB_ERROR; + break; + } + } + + if ((USB_OK != retval) && (USB_HUB_QOVR != retval)) + { + g_usb_shhub_init_port[ptr->ip] = USB_HUB_P1; /* Port Clear */ + g_usb_shhub_init_seq[ptr->ip] = USB_SEQ_0; /* Sequence Clear */ + g_usb_shhub_info[ptr->ip] = USB_NULL; /* Clear */ + g_usb_shhub_process[ptr->ip] = USB_NULL; /* Clear */ + } + + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) mess); + if (USB_OK != err) + { + /* Release Memory block failure */ + USB_PRINTF0("### USB HostHubClass rel_blk error\n"); + } + } + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_init_down_port + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_port_attach + * Description : port attach + * Arguments : uint16_t hubaddr : hub address + * : uint16_t portnum : down port number + * : usb_clsinfo_t *mess : Pointer to usb_clsinfo_t structure + * Return value : uint16_t : Manager Mode + ******************************************************************************/ +static uint16_t usb_hhub_port_attach (uint16_t hubaddr, uint16_t portnum, usb_clsinfo_t * mess) +{ + #if (BSP_CFG_RTOS != 0) + uint16_t devaddr; + uint16_t hpphub, hubport, buffer; + usb_utr_t * ptr; + + ptr = (usb_utr_t *) mess; + + /* Down Port Reset */ + usb_hhub_port_reset(ptr, hubaddr, portnum, (usb_clsinfo_t *) USB_NULL); + + /* Device Enumeration */ + switch ((uint16_t) (g_usb_hhub_data[ptr->ip][hubaddr][1] & (uint8_t) 0x06)) + { + case 0x00: + { + g_usb_hstd_device_speed[ptr->ip] = USB_FSCONNECT; + USB_PRINTF0(" Full-Speed Device\n"); + break; + } + + case 0x02: + { + g_usb_hstd_device_speed[ptr->ip] = USB_LSCONNECT; + USB_PRINTF0(" Low-Speed Device\n"); + break; + } + + case 0x04: + { + g_usb_hstd_device_speed[ptr->ip] = USB_HSCONNECT; + USB_PRINTF0(" Hi-Speed Device\n"); + break; + } + + default: + { + g_usb_hstd_device_speed[ptr->ip] = USB_NOCONNECT; + USB_PRINTF0(" Detach Detached\n"); + break; + } + } + + devaddr = usb_hhub_get_cnn_devaddr(ptr, hubaddr, portnum); /* Now down port device search */ + g_usb_hstd_device_addr[ptr->ip] = devaddr; + devaddr = (uint16_t) (devaddr << USB_DEVADDRBIT); + g_usb_hstd_mgr_mode[ptr->ip] = USB_DEFAULT; + if (0 != devaddr) + { + usb_hstd_set_hub_port(ptr, devaddr, (uint16_t) (hubaddr << 11), (uint16_t) (portnum << 8)); + + /* Get DEVADDR register */ + buffer = hw_usb_hread_devadd(ptr, devaddr); + + /* WAIT_LOOP */ + do + { + hpphub = (uint16_t) (buffer & USB_UPPHUB); + hubport = (uint16_t) (buffer & USB_HUBPORT); + devaddr = (uint16_t) (hpphub << 1); + + /* Get DEVADDR register */ + buffer = hw_usb_hread_devadd(ptr, devaddr); + } while ((USB_HSCONNECT != (buffer & USB_USBSPD)) && (USB_DEVICE_0 != devaddr)); + + usb_hstd_set_dev_addr(ptr, (uint16_t) USB_DEVICE_0, g_usb_hstd_device_speed[ptr->ip]); + + /* Set up-port hub */ + usb_hstd_set_hub_port(ptr, (uint16_t) USB_DEVICE_0, hpphub, hubport); + + /* Set up-port hub */ + usb_hstd_set_hub_port(ptr, (uint16_t) (g_usb_hstd_device_addr[ptr->ip] << USB_DEVADDRBIT), hpphub, hubport); + + /* Clear Enumeration Sequence Number */ + g_usb_hstd_enum_seq[ptr->ip] = 0; + + if (USB_NOCONNECT != g_usb_hstd_device_speed[ptr->ip]) + { + (*g_usb_hstd_enumaration_process[0])(ptr, (uint16_t) USB_DEVICE_0, (uint16_t) 0); + + /* WAIT_LOOP */ + while (1) + { + usb_cpu_delay_xms((uint16_t) 3); + if ((USB_CONFIGURED == g_usb_hstd_mgr_mode[ptr->ip]) || + (USB_DEFAULT != g_usb_hstd_mgr_mode[ptr->ip])) + { + /* HUB down port status */ + g_usb_shhub_down_port[ptr->ip][hubaddr] |= USB_BITSET(portnum); + + return g_usb_hstd_mgr_mode[ptr->ip]; + } + } + } + } + else + { + USB_PRINTF0("### device count over !\n"); + + return g_usb_hstd_mgr_mode[ptr->ip]; + } + + return USB_DETACHED; + #else /* #if (BSP_CFG_RTOS != 0) */ + uint16_t devaddr = 0; + uint16_t retval; + uint16_t hpphub, hubport, buffer; + usb_er_t err; + usb_utr_t * ptr; + #if (!defined(USB_HIGH_SPEED_MODULE)) + usb_instance_ctrl_t ctrl; + #endif /* (!defined(USB_HIGH_SPEED_MODULE)) */ + + ptr = (usb_utr_t *) mess; + hubaddr = g_usb_shhub_hub_addr[ptr->ip]; + portnum = g_usb_shhub_event_port[ptr->ip]; + + if (USB_MSG_HUB_ATTACH != g_usb_shhub_process[ptr->ip]) + { + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) mess); + if (USB_OK != err) + { + /* Send Message failure */ + USB_PRINTF0("### HUB snd_msg error\n"); + } + } + else + { + switch (g_usb_shhub_attach_seq[ptr->ip]) + { + case USB_SEQ_0: + { + if (USB_NULL == g_p_usb_hstd_pipe[ptr->ip][USB_PIPE0]) + { + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_1; + g_usb_shhub_process[ptr->ip] = USB_MSG_HUB_RESET; + } + else + { + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_0; + } + + /* Next Process Selector */ + usb_hhub_specified_path(mess); + break; + } + + case USB_SEQ_1: + { + /* Device Enumeration */ + switch ((uint16_t) (g_usb_hhub_data[ptr->ip][hubaddr][1] & (uint8_t) 0x06)) + { + case 0x00: + { + g_usb_hstd_device_speed[ptr->ip] = USB_FSCONNECT; + USB_PRINTF0(" Full-Speed Device\n"); + break; + } + + case 0x02: + { + #if defined(USB_HIGH_SPEED_MODULE) + g_usb_hstd_device_speed[ptr->ip] = USB_LSCONNECT; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + g_usb_hstd_device_speed[ptr->ip] = USB_NOCONNECT; + + ctrl.device_address = 0; /* USB Device address */ + ctrl.module_number = (uint8_t) ptr->ip; /* Module number setting */ + usb_set_event(USB_STATUS_NOT_SUPPORT, &ctrl); /* Set Event() */ + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + USB_PRINTF0(" Low-Speed Device\n"); + break; + } + + case 0x04: + { + g_usb_hstd_device_speed[ptr->ip] = USB_HSCONNECT; + USB_PRINTF0(" Hi-Speed Device\n"); + break; + } + + default: + { + g_usb_hstd_device_speed[ptr->ip] = USB_NOCONNECT; + USB_PRINTF0(" Detach Detached\n"); + break; + } + } + + devaddr = usb_hhub_get_cnn_devaddr(ptr, hubaddr, portnum); /* Now downport device search */ + g_usb_hstd_device_addr[ptr->ip] = devaddr; + devaddr = (uint16_t) (devaddr << USB_DEVADDRBIT); + g_usb_hstd_mgr_mode[ptr->ip] = USB_DEFAULT; + if (0 != devaddr) + { + usb_hstd_set_hub_port(ptr, devaddr, (uint16_t) (hubaddr << 11), (uint16_t) (portnum << 8)); + + /* Get DEVADDR register */ + buffer = hw_usb_hread_devadd(ptr, devaddr); + + /* WAIT_LOOP */ + do + { + hpphub = (uint16_t) (buffer & USB_UPPHUB); + hubport = (uint16_t) (buffer & USB_HUBPORT); + devaddr = (uint16_t) (hpphub << 1); + + /* Get DEVADDR register */ + buffer = hw_usb_hread_devadd(ptr, devaddr); + } while ((USB_HSCONNECT != (buffer & USB_USBSPD)) && (USB_DEVICE_0 != devaddr)); + + usb_hstd_set_dev_addr(ptr, (uint16_t) USB_DEVICE_0, g_usb_hstd_device_speed[ptr->ip]); + + /* Set up-port hub */ + usb_hstd_set_hub_port(ptr, (uint16_t) USB_DEVICE_0, hpphub, hubport); + + /* Set up-port hub */ + usb_hstd_set_hub_port(ptr, + (uint16_t) (g_usb_hstd_device_addr[ptr->ip] << USB_DEVADDRBIT), + hpphub, + hubport); + + /* Clear Enumeration Sequence Number */ + g_usb_hstd_enum_seq[ptr->ip] = 0; + if (USB_NOCONNECT != g_usb_hstd_device_speed[ptr->ip]) + { + (*g_usb_hstd_enumaration_process[0])(ptr, (uint16_t) USB_DEVICE_0, (uint16_t) 0); + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_2; + usb_hhub_specified_path_wait(mess, 3U); + } + else + { + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_3; + usb_hhub_specified_path(mess); /* Next Process Selector */ + } + } + else + { + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_3; + + usb_hhub_specified_path(mess); /* Next Process Selector */ + } + + break; + } + + case USB_SEQ_2: + { + if ((USB_CONFIGURED == g_usb_hstd_mgr_mode[ptr->ip]) || + (USB_DEFAULT != g_usb_hstd_mgr_mode[ptr->ip])) + { + /* HUB down port status */ + g_usb_shhub_down_port[ptr->ip][hubaddr] |= USB_BITSET(portnum); + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_0; + g_usb_shhub_process[ptr->ip] = USB_MSG_HUB_EVENT; + usb_hhub_specified_path(mess); + } + else + { + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_2; + usb_hhub_specified_path_wait(mess, 3U); + } + + break; + } + + case USB_SEQ_3: + { + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_4; + g_usb_shhub_process[ptr->ip] = USB_MSG_HUB_RESET; + usb_hhub_specified_path(mess); /* Next Process Selector */ + break; + } + + case USB_SEQ_4: + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + /* Hub Port Set Feature Request */ + retval = usb_hhub_port_set_feature(ptr, + hubaddr, + portnum, + USB_HUB_PORT_SUSPEND, + usb_hhub_class_request_complete); + + /* Submit overlap error */ + if (USB_HUB_QOVR == retval) + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); + } + else + { + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_5; + } + } + + break; + } + + case USB_SEQ_5: + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + usb_hhub_port_detach(ptr, hubaddr, portnum); + g_usb_shhub_info_data[ptr->ip][devaddr].up_addr = 0; /* Up-hubaddr clear */ + g_usb_shhub_info_data[ptr->ip][devaddr].up_port_num = 0; /* Up-hubport clear */ + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_0; + g_usb_shhub_process[ptr->ip] = USB_MSG_HUB_EVENT; + usb_hhub_specified_path(mess); + } + + break; + } + + default: + { + g_usb_shhub_attach_seq[ptr->ip] = USB_SEQ_0; + g_usb_shhub_process[ptr->ip] = USB_NULL; + g_usb_shhub_info[ptr->ip] = USB_NULL; + break; + } + } + + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) mess); + if (USB_OK != err) + { + USB_PRINTF0("### USB HostHubClass rel_blk error\n"); + } + } + return USB_OK; + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_port_attach + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hhub_event + * Description : USB Hub Event process. + * Arguments : usb_clsinfo_t *mess : Pointer to usb_clsinfo_t structure. + * Return value : none + ******************************************************************************/ +static void usb_hhub_event (usb_clsinfo_t * mess) +{ + usb_er_t err; + uint16_t hubaddr, devaddr, retval; + usb_utr_t * ptr; + uint32_t port_status = 0; + uint16_t next_port_check = USB_FALSE; + uint16_t port_clr_feature_type; + + ptr = (usb_utr_t *) mess; + hubaddr = g_usb_shhub_hub_addr[ptr->ip]; + + if (USB_MSG_HUB_EVENT != g_usb_shhub_process[ptr->ip]) + { + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) mess); + if (USB_OK != err) + { + USB_PRINTF0("### HUB snd_msg error\n"); + } + } + else + { + switch (g_usb_shhub_event_seq[ptr->ip]) + { + case USB_SEQ_0: /* Request */ + { + if (USB_MSG_HUB_SUBMITRESULT == g_usb_shhub_info[ptr->ip]) /* Event Check */ + { + /* Hub and Port Status Change Bitmap(b0:Hub,b1:DownPort1change detected,b2:DownPort2,...) */ + if (0 != (g_usb_hhub_data[ptr->ip][hubaddr][0] & USB_BITSET(g_usb_shhub_event_port[ptr->ip]))) + { + USB_PRINTF1(" *** HUB port %d \t", g_usb_shhub_event_port[ptr->ip]); + + /* GetStatus request */ + retval = usb_hhub_get_port_information(ptr, + hubaddr, + g_usb_shhub_event_port[ptr->ip], + usb_hhub_class_request_complete); + if (USB_HUB_QOVR == retval) /* Submit overlap error */ + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); /* Retry */ + } + else + { + g_usb_shhub_event_seq[ptr->ip] = USB_SEQ_1; + } + } + else + { + /* Port check end */ + next_port_check = USB_TRUE; + } + } + else + /* if (USB_MSG_CLS_INIT == g_usb_shhub_info[ptr->ip]) */ /* Event Check */ + { + /* USB_MSG_HUB_INIT */ + USB_PRINTF2(" *** address %d down port %d \t", hubaddr, g_usb_shhub_event_port[ptr->ip]); + + /* GetStatus request */ + retval = usb_hhub_get_port_information(ptr, + hubaddr, + g_usb_shhub_event_port[ptr->ip], + usb_hhub_class_request_complete); + if (USB_HUB_QOVR == retval) /* Submit overlap error */ + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); /* Retry */ + } + else + { + g_usb_shhub_event_seq[ptr->ip] = USB_SEQ_3; + } + } + + break; + } + + case USB_SEQ_1: /* Request Result Check & Request */ + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + port_status = (uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][0]; + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][1] << 8); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][2] << 16); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][3] << 24); + USB_PRINTF2(" [port/status] : %d, 0x%08x\n", g_usb_shhub_event_port[ptr->ip], port_status); + + if (0 != (port_status & USB_BIT_C_PORT_CONNECTION)) /* C_PORT_CONNECTION */ + { + retval = usb_hhub_port_clr_feature(ptr, + hubaddr, + g_usb_shhub_event_port[ptr->ip], + (uint16_t) USB_HUB_C_PORT_CONNECTION, + usb_hhub_class_request_complete); + if (USB_HUB_QOVR == retval) /* Submit overlap error */ + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); /* Retry */ + } + else + { + g_usb_shhub_event_seq[ptr->ip] = USB_SEQ_3; /* Attach Sequence */ + } + } + else + { + /* Now down port device search */ + devaddr = usb_hhub_get_cnn_devaddr(ptr, hubaddr, g_usb_shhub_event_port[ptr->ip]); + if (0 != (port_status & USB_BIT_PORT_ENABLE)) /* PORT_ENABLE */ + { + USB_PRINTF1(" Hubport error address%d\n", devaddr); + port_clr_feature_type = USB_HUB_C_PORT_ENABLE; /* C_PORT_ENABLE */ + } + else if (0 != (port_status & USB_BIT_PORT_SUSPEND)) /* PORT_SUSPEND */ + { + USB_PRINTF1(" Hubport suspend(resume complete) address%d\n", devaddr); + port_clr_feature_type = USB_HUB_C_PORT_SUSPEND; /* C_PORT_SUSPEND */ + } + else if (0 != (port_status & USB_BIT_C_PORT_OVER_CURRENT)) /* PORT_OVER_CURRENT */ + { + USB_PRINTF1(" Hubport over current address%d\n", devaddr); + port_clr_feature_type = USB_HUB_C_PORT_OVER_CURRENT; /* C_PORT_OVER_CURRENT */ + } + else if (0 != (port_status & USB_BIT_PORT_RESET)) /* PORT_RESET */ + { + USB_PRINTF1(" Hubport reset(reset complete) address%d\n", devaddr); + port_clr_feature_type = USB_HUB_C_PORT_RESET; /* C_PORT_RESET */ + } + else + { + next_port_check = USB_TRUE; + } + + if (USB_FALSE == next_port_check) + { + /* ClearFeature request */ + retval = usb_hhub_port_clr_feature(ptr, + hubaddr, + g_usb_shhub_event_port[ptr->ip], + port_clr_feature_type, + usb_hhub_class_request_complete); + if (USB_HUB_QOVR == retval) /* Submit overlap error */ + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); /* Retry */ + } + else + { + g_usb_shhub_event_seq[ptr->ip] = USB_SEQ_2; /* Next Sequence */ + } + } + } + } + + break; + } + + case USB_SEQ_2: /* Request Result Check */ + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + if (0 != (port_status & USB_BIT_PORT_SUSPEND)) /* PORT_SUSPEND */ + { + /* C_PORT_SUSPEND */ + /* HUB down port status */ + g_usb_shhub_remote[ptr->ip][hubaddr] |= USB_BITSET(g_usb_shhub_event_port[ptr->ip]); + } + + next_port_check = USB_TRUE; + } + + break; + } + + case USB_SEQ_3: /* Attach Sequence */ + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + port_status = (uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][0]; + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][1] << 8); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][2] << 16); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][3] << 24); + USB_PRINTF2(" [port/status] : %d, 0x%08x\n", g_usb_shhub_event_port[ptr->ip], port_status); + + if (0 != (port_status & USB_BIT_PORT_CONNECTION)) /* PORT_CONNECTION */ + { + if (USB_MSG_HUB_SUBMITRESULT == g_usb_shhub_info[ptr->ip]) + { + if (0 == + (g_usb_shhub_down_port[ptr->ip][hubaddr] & + USB_BITSET(g_usb_shhub_event_port[ptr->ip]))) + { + g_usb_shhub_event_seq[ptr->ip] = USB_SEQ_4; /* Next Attach sequence */ + usb_hhub_new_connect(mess, (uint16_t) 0, (uint16_t) 0, mess); + } + else + { + next_port_check = USB_TRUE; /* Not PORT_CONNECTION */ + } + } + else + /* if (USB_MSG_CLS_INIT == g_usb_shhub_info[ptr->ip])*/ + { + g_usb_shhub_event_seq[ptr->ip] = USB_SEQ_4; /* Next Attach sequence */ + usb_hhub_new_connect(mess, (uint16_t) 0, (uint16_t) 0, mess); + } + } + else + { + /* non connect */ + if (USB_MSG_HUB_SUBMITRESULT == g_usb_shhub_info[ptr->ip]) /* */ + { + /* Now down port device search */ + devaddr = usb_hhub_get_cnn_devaddr(ptr, hubaddr, g_usb_shhub_event_port[ptr->ip]); + if (0 != devaddr) + { + usb_hhub_port_detach(ptr, hubaddr, g_usb_shhub_event_port[ptr->ip]); + USB_PRINTF1(" Hubport disconnect address%d\n", devaddr); + g_usb_shhub_info_data[ptr->ip][devaddr].up_addr = 0; /* Up-address clear */ + g_usb_shhub_info_data[ptr->ip][devaddr].up_port_num = 0; /* Up-port num clear */ + g_usb_shhub_info_data[ptr->ip][devaddr].port_num = 0; /* Port number clear */ + g_usb_shhub_info_data[ptr->ip][devaddr].pipe_num = 0; /* Pipe number clear */ + } + } + + next_port_check = USB_TRUE; + } + } + + break; + } + + case USB_SEQ_4: /* Attach */ + { + next_port_check = USB_TRUE; + break; + } + + default: + { + /* error */ + break; + } + } + + if (USB_TRUE == next_port_check) + { + if (g_usb_shhub_event_port[ptr->ip] >= g_usb_shhub_info_data[ptr->ip][hubaddr].port_num) + { + /* Port check end */ + usb_hhub_trans_start(ptr, + hubaddr, + (uint32_t) 1, + &g_usb_hhub_data[ptr->ip][hubaddr][0], + &usb_hhub_trans_complete); /* Get Hub and Port Status Change Bitmap */ + + g_usb_shhub_event_port[ptr->ip] = USB_HUB_P1; /* Port Clear */ + g_usb_shhub_event_seq[ptr->ip] = USB_SEQ_0; /* Sequence Clear */ + g_usb_shhub_process[ptr->ip] = USB_NULL; + g_usb_shhub_info[ptr->ip] = USB_NULL; + } + else + { + g_usb_shhub_event_port[ptr->ip]++; /* Next port check */ + g_usb_shhub_event_seq[ptr->ip] = USB_SEQ_0; /* Sequence Clear */ + usb_hhub_specified_path(mess); + } + } + + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) mess); + if (USB_OK != err) + { + USB_PRINTF0("### USB HostHubClass rel_blk error\n"); + } + } +} + +/****************************************************************************** + * End of function usb_hhub_event + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hhub_port_reset + * Description : HUB down port USB-reset request + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : hub address + * : uint16_t portnum : down port number + * : usb_clsinfo_t *mess : Pointer to usb_clsinfo_t structure. + * Return value : none + ******************************************************************************/ +static void usb_hhub_port_reset (usb_utr_t * ptr, uint16_t hubaddr, uint16_t portnum, usb_clsinfo_t * mess) +{ + #if (BSP_CFG_RTOS != 0) + FSP_PARAMETER_NOT_USED(mess); + uint16_t retval; + uint32_t port_status; + + /* Hub port SetFeature */ + usb_cpu_delay_xms((uint16_t) 100); + retval = usb_hhub_port_set_feature(ptr, hubaddr, portnum, (uint16_t) USB_HUB_PORT_RESET, class_trans_result); + if (USB_OK == retval) + { + usb_cpu_delay_xms((uint16_t) 50); + + /* WAIT_LOOP */ + do + { + usb_cpu_delay_xms((uint16_t) 10); + + /* Get Status */ + usb_hhub_get_port_information(ptr, hubaddr, portnum, class_trans_result); + + port_status = (uint32_t) 0; + port_status = (uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][0]; + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][1] << 8); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][2] << 16); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][3] << 24); + } while (USB_BIT_C_PORT_RESET != (port_status & USB_BIT_C_PORT_RESET)); + } + + /* Hub port ClearFeature */ + usb_cpu_delay_xms((uint16_t) 20); + + usb_hhub_port_clr_feature(ptr, hubaddr, portnum, (uint16_t) USB_HUB_C_PORT_RESET, class_trans_result); + #else /* #if (BSP_CFG_RTOS != 0) */ + usb_er_t err; + uint16_t retval; + uint32_t port_status; + + hubaddr = g_usb_shhub_hub_addr[ptr->ip]; + portnum = g_usb_shhub_event_port[ptr->ip]; + + if (USB_MSG_HUB_RESET != g_usb_shhub_process[ptr->ip]) + { + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) mess); + if (USB_OK != err) + { + USB_PRINTF0("### HUB snd_msg error\n"); + } + } + else + { + switch (g_usb_shhub_reset_seq[ptr->ip]) + { + case USB_SEQ_0: + { + /* Hub port SetFeature */ + usb_cpu_delay_xms((uint16_t) 100); + retval = usb_hhub_port_set_feature(ptr, + hubaddr, + portnum, + (uint16_t) USB_HUB_PORT_RESET, + usb_hhub_class_request_complete); + + /* Submit overlap error */ + if (USB_HUB_QOVR == retval) + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); + } + else + { + g_usb_shhub_reset_seq[ptr->ip] = USB_SEQ_1; + } + + break; + } + + case USB_SEQ_1: + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + usb_cpu_delay_xms((uint16_t) 60); + + /* Get Status */ + retval = usb_hhub_get_port_information(ptr, hubaddr, portnum, usb_hhub_class_request_complete); + + /* Submit overlap error */ + if (USB_HUB_QOVR == retval) + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); + } + else + { + g_usb_shhub_reset_seq[ptr->ip] = USB_SEQ_2; + } + } + + break; + } + + case USB_SEQ_2: + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + port_status = (uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][0]; + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][1] << 8); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][2] << 16); + port_status |= ((uint32_t) g_usb_hhub_data[ptr->ip][hubaddr][3] << 24); + + /* Check Reset Change(C_PORT_RESET) */ + if (USB_BIT_C_PORT_RESET != (port_status & USB_BIT_C_PORT_RESET)) + { + g_usb_shhub_reset_seq[ptr->ip] = USB_SEQ_0; + usb_hhub_specified_path_wait(mess, (uint16_t) 10); + } + else + { + /* Hub port ClearFeature */ + usb_cpu_delay_xms((uint16_t) 20); + + retval = usb_hhub_port_clr_feature(ptr, + hubaddr, + portnum, + (uint16_t) USB_HUB_C_PORT_RESET, + usb_hhub_class_request_complete); + + /* Submit overlap error */ + if (USB_HUB_QOVR == retval) + { + usb_hhub_specified_path_wait(mess, (uint16_t) 10); + } + else + { + g_usb_shhub_reset_seq[ptr->ip] = USB_SEQ_3; + } + } + } + + break; + } + + case USB_SEQ_3: + { + retval = usb_hhub_request_result(mess->result); + if (USB_OK == retval) + { + g_usb_shhub_reset_seq[ptr->ip] = USB_SEQ_0; + g_usb_shhub_process[ptr->ip] = USB_MSG_HUB_ATTACH; + usb_hhub_specified_path(mess); + } + + break; + } + + default: + { + g_usb_shhub_reset_seq[ptr->ip] = USB_SEQ_0; + g_usb_shhub_process[ptr->ip] = USB_NULL; + break; + } + } + + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) mess); + if (USB_OK != err) + { + USB_PRINTF0("### USB HostHubClass rel_blk error\n"); + } + } + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_port_reset + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_check_class + * Description : HUB Class driver check + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t **table : Descriptor, etc + * Return value : none + ******************************************************************************/ +static void usb_hhub_check_class (usb_utr_t * ptr, uint16_t ** table) +{ + #if (BSP_CFG_RTOS != 0) + uint16_t retval; + uint8_t string; + + g_p_usb_shhub_device_table[ptr->ip] = (uint8_t *) (table[0]); + g_p_usb_shhub_config_table[ptr->ip] = (uint8_t *) (table[1]); + g_p_usb_shhub_interface_table[ptr->ip] = (uint8_t *) (table[2]); + *table[3] = USB_OK; + g_usb_shhub_spec[ptr->ip] = *table[4]; + g_usb_shhub_speed[ptr->ip] = *table[6]; + g_usb_shhub_dev_addr[ptr->ip] = *table[7]; + + /* Descriptor check */ + retval = usb_hhub_chk_config((uint16_t **) table, (uint16_t) g_usb_shhub_spec[ptr->ip]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Configuration descriptor error !\n"); + *table[3] = USB_ERROR; + + return; + } + + /* Interface Descriptor check */ + retval = usb_hhub_chk_interface((uint16_t **) table, (uint16_t) g_usb_shhub_spec[ptr->ip]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Interface descriptor error !\n"); + *table[3] = USB_ERROR; + + return; + } + + /* String descriptor */ + retval = usb_hhub_get_string_descriptor1(ptr, + g_usb_shhub_dev_addr[ptr->ip], + (uint16_t) 15, + (usb_cb_t) &class_trans_result); + if (USB_ERROR == retval) + { + USB_PRINTF0("### String descriptor error !\n"); + *table[3] = USB_ERROR; + + return; + } + + /* String descriptor */ + string = g_p_usb_shhub_device_table[ptr->ip][15]; + retval = usb_hhub_get_string_descriptor2(ptr, + g_usb_shhub_dev_addr[ptr->ip], + (uint16_t) string, + (usb_cb_t) &class_trans_result); + if (USB_OK == retval) + { + if (g_usb_hstd_class_data[ptr->ip][0] < (uint8_t) ((32 * 2) + 2)) + { + g_usb_hstd_class_data[ptr->ip][0] = (uint8_t) (g_usb_hstd_class_data[ptr->ip][0] / 2); + g_usb_hstd_class_data[ptr->ip][0] = (uint8_t) (g_usb_hstd_class_data[ptr->ip][0] - 1); + } + else + { + g_usb_hstd_class_data[ptr->ip][0] = (uint8_t) 32; + } + } + else + { + USB_PRINTF0("*** Product name error\n"); + *table[3] = USB_ERROR; + + return; + } + + /* Get HUB descriptor */ + retval = usb_hhub_get_hub_information(ptr, g_usb_shhub_dev_addr[ptr->ip], class_trans_result); + if (USB_OK == retval) + { + /* Do nothing */ + } + else + { + USB_PRINTF0("### HUB Descriptor over\n"); + *table[3] = USB_ERROR; + + return; + } + + /* Pipe Information table set */ + switch (g_usb_shhub_spec[ptr->ip]) + { + case USB_FSHUB: /* Full Speed Hub */ + { + if (USB_FSCONNECT == g_usb_shhub_speed[ptr->ip]) + { + retval = + usb_hhub_pipe_info(ptr, (uint8_t *) g_p_usb_shhub_interface_table[ptr->ip], + g_usb_shhub_speed[ptr->ip], (uint16_t) g_p_usb_shhub_config_table[ptr->ip][2]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Device information error(HUB) !\n"); + *table[3] = USB_ERROR; + + return; + } + } + else + { + USB_PRINTF0("### HUB Descriptor speed error\n"); + *table[3] = USB_ERROR; + + return; + } + + break; + } + + case USB_HSHUBS: /* Hi Speed Hub(Single) */ + { + if (USB_HSCONNECT == g_usb_shhub_speed[ptr->ip]) + { + retval = + usb_hhub_pipe_info(ptr, (uint8_t *) g_p_usb_shhub_interface_table[ptr->ip], + g_usb_shhub_speed[ptr->ip], (uint16_t) g_p_usb_shhub_config_table[ptr->ip][2]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Device information error(HUB) !\n"); + *table[3] = USB_ERROR; + + return; + } + } + else + { + USB_PRINTF0("### HUB Descriptor speed error\n"); + *table[3] = USB_ERROR; + + return; + } + + break; + } + + case USB_HSHUBM: /* Hi Speed Hub(Multi) */ + { + if (USB_HSCONNECT == g_usb_shhub_speed[ptr->ip]) + { + /* Set pipe information */ + retval = + usb_hhub_pipe_info(ptr, (uint8_t *) g_p_usb_shhub_interface_table[ptr->ip], + g_usb_shhub_speed[ptr->ip], (uint16_t) g_p_usb_shhub_config_table[ptr->ip][2]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Device information error(HUB) !\n"); + *table[3] = USB_ERROR; + + return; + } + + /* Set pipe information */ + retval = + usb_hhub_pipe_info(ptr, (uint8_t *) g_p_usb_shhub_interface_table[ptr->ip], + g_usb_shhub_speed[ptr->ip], (uint16_t) g_p_usb_shhub_config_table[ptr->ip][2]); + if (USB_ERROR == retval) + { + USB_PRINTF0("### Device information error(HUB) !\n"); + *table[3] = USB_ERROR; + + return; + } + } + else + { + USB_PRINTF0("### HUB Descriptor speed error\n"); + *table[3] = USB_ERROR; + + return; + } + + break; + } + + default: + { + *table[3] = USB_ERROR; + + return; + break; + } + } + + /* Port number set */ + g_usb_shhub_info_data[ptr->ip][g_usb_shhub_dev_addr[ptr->ip]].port_num = g_usb_hhub_descriptor[ptr->ip][2]; + #else /* #if (BSP_CFG_RTOS != 0) */ + usb_clsinfo_t * p_blf; + usb_clsinfo_t * cp; + usb_er_t err; + + g_p_usb_shhub_device_table[ptr->ip] = (uint8_t *) (table[0]); + g_p_usb_shhub_config_table[ptr->ip] = (uint8_t *) (table[1]); + g_p_usb_shhub_interface_table[ptr->ip] = (uint8_t *) (table[2]); + *table[3] = USB_OK; + g_usb_shhub_spec[ptr->ip] = *table[4]; + g_usb_shhub_speed[ptr->ip] = *table[6]; + g_usb_shhub_dev_addr[ptr->ip] = *table[7]; + + g_usb_shhub_class_seq[ptr->ip] = 0; + + /* Get memory pool blk */ + if (USB_OK == USB_PGET_BLK(USB_HUB_MPL, &p_blf, ptr->ip)) + { + cp = (usb_clsinfo_t *) p_blf; + cp->msginfo = USB_MSG_CLS_CHECKREQUEST; + + cp->ipp = ptr->ipp; + cp->ip = ptr->ip; + + /* Class check of enumeration sequence move to class function */ + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) cp); + if (USB_OK != err) + { + /* Send Message failure */ + USB_PRINTF1("Host HUB snd_msg error %x\n", err); + } + } + else + { + /* Send Message failure */ + /* WAIT_LOOP */ + while (1) + { + /* Non */ + } + } + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_check_class + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_trans_start + * Description : HUB sys data transfer / control transfer + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : hub address + * : uint32_t size : Data Transfer size + * : uint8_t *table : Receive Data area + * : usb_cb_t complete : Callback function + * Return value : none + ******************************************************************************/ +static void usb_hhub_trans_start (usb_utr_t * ptr, uint16_t hubaddr, uint32_t size, uint8_t * table, usb_cb_t complete) +{ + usb_er_t err; + + /* Transfer structure setting */ + g_usb_shhub_data_mess[ptr->ip][hubaddr].keyword = g_usb_shhub_info_data[ptr->ip][hubaddr].pipe_num; + g_usb_shhub_data_mess[ptr->ip][hubaddr].p_tranadr = table; + g_usb_shhub_data_mess[ptr->ip][hubaddr].tranlen = size; + g_usb_shhub_data_mess[ptr->ip][hubaddr].p_setup = 0; + g_usb_shhub_data_mess[ptr->ip][hubaddr].status = USB_DATA_WAIT; + g_usb_shhub_data_mess[ptr->ip][hubaddr].complete = complete; + g_usb_shhub_data_mess[ptr->ip][hubaddr].segment = USB_TRAN_END; + + g_usb_shhub_data_mess[ptr->ip][hubaddr].ipp = ptr->ipp; + g_usb_shhub_data_mess[ptr->ip][hubaddr].ip = ptr->ip; + + /* Transfer start */ + err = usb_hstd_transfer_start(&g_usb_shhub_data_mess[ptr->ip][hubaddr]); + if (USB_OK != err) + { + /* Send Message failure */ + USB_PRINTF1("### usb_hhub_trans_start error (%ld)\n", err); + } +} + +/****************************************************************************** + * End of function usb_hhub_trans_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_port_set_feature + * Description : SetFeature request + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : hub address + * : uint16_t port : down port number + * : uint16_t command : request command + * Return value : uint16_t : DONE/ERROR + ******************************************************************************/ +static uint16_t usb_hhub_port_set_feature (usb_utr_t * ptr, + uint16_t hubaddr, + uint16_t port, + uint16_t command, + usb_cb_t complete) +{ + usb_er_t qerr; + + /* Request */ + g_usb_shhub_class_request[ptr->ip][0] = USB_SET_FEATURE | USB_HOST_TO_DEV | USB_CLASS | USB_OTHER; + g_usb_shhub_class_request[ptr->ip][1] = command; + g_usb_shhub_class_request[ptr->ip][2] = port; /* Port number */ + g_usb_shhub_class_request[ptr->ip][3] = 0; + g_usb_shhub_class_request[ptr->ip][4] = hubaddr; /* Device address */ + + /* Port SetFeature */ + g_usb_shhub_ctrl_mess[ptr->ip].keyword = USB_PIPE0; + g_usb_shhub_ctrl_mess[ptr->ip].p_tranadr = (void *) &g_usb_hhub_data[ptr->ip][hubaddr][0]; + g_usb_shhub_ctrl_mess[ptr->ip].tranlen = (uint32_t) g_usb_shhub_class_request[ptr->ip][3]; + g_usb_shhub_ctrl_mess[ptr->ip].p_setup = g_usb_shhub_class_request[ptr->ip]; + g_usb_shhub_ctrl_mess[ptr->ip].segment = USB_TRAN_END; + g_usb_shhub_ctrl_mess[ptr->ip].complete = complete; + + g_usb_shhub_ctrl_mess[ptr->ip].ipp = ptr->ipp; + g_usb_shhub_ctrl_mess[ptr->ip].ip = ptr->ip; + + /* Transfer start */ + #if (BSP_CFG_RTOS != 0) + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + if (USB_QOVR == qerr) + { + /** Submit overlap error **/ + /** Retry **/ + /* WAIT_LOOP */ + do + { + usb_cpu_delay_xms((uint16_t) 10); + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + } while (USB_QOVR == qerr); + } + + if (USB_OK == qerr) + { + qerr = class_trans_wait_tmo(ptr, (uint16_t) 5000); + + return (uint16_t) qerr; + } + else + { + return USB_ERROR; + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + if (USB_QOVR == qerr) + { + return USB_HUB_QOVR; + } + return USB_OK; + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_port_set_feature + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_port_clr_feature + * Description : ClearFeature request + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : hub address + * : uint16_t port : down port number + * : uint16_t command : request command + * Return value : uint16_t : DONE/ERROR + ******************************************************************************/ +static uint16_t usb_hhub_port_clr_feature (usb_utr_t * ptr, + uint16_t hubaddr, + uint16_t port, + uint16_t command, + usb_cb_t complete) +{ + usb_er_t qerr; + + /* Request */ + g_usb_shhub_class_request[ptr->ip][0] = USB_CLEAR_FEATURE | USB_HOST_TO_DEV | USB_CLASS | USB_OTHER; + g_usb_shhub_class_request[ptr->ip][1] = command; + g_usb_shhub_class_request[ptr->ip][2] = port; /* Port number */ + g_usb_shhub_class_request[ptr->ip][3] = 0; + g_usb_shhub_class_request[ptr->ip][4] = hubaddr; /* Device address */ + + /* Port ClearFeature */ + g_usb_shhub_ctrl_mess[ptr->ip].keyword = USB_PIPE0; + g_usb_shhub_ctrl_mess[ptr->ip].p_tranadr = (void *) &g_usb_hhub_data[ptr->ip][hubaddr][0]; + g_usb_shhub_ctrl_mess[ptr->ip].tranlen = (uint32_t) g_usb_shhub_class_request[ptr->ip][3]; + g_usb_shhub_ctrl_mess[ptr->ip].p_setup = g_usb_shhub_class_request[ptr->ip]; + g_usb_shhub_ctrl_mess[ptr->ip].segment = USB_TRAN_END; + g_usb_shhub_ctrl_mess[ptr->ip].complete = complete; + + g_usb_shhub_ctrl_mess[ptr->ip].ipp = ptr->ipp; + g_usb_shhub_ctrl_mess[ptr->ip].ip = ptr->ip; + + /* Transfer start */ + #if (BSP_CFG_RTOS != 0) + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + if (USB_QOVR == qerr) + { + /** Submit overlap error **/ + /** Retry **/ + /* WAIT_LOOP */ + do + { + usb_cpu_delay_xms((uint16_t) 10); + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + } while (USB_QOVR == qerr); + } + + if (USB_OK == qerr) + { + qerr = class_trans_wait_tmo(ptr, (uint16_t) 5000); + + return (uint16_t) qerr; + } + else + { + return USB_ERROR; + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + qerr = usb_hstd_transfer_start(&g_usb_shhub_ctrl_mess[ptr->ip]); + if (USB_QOVR == qerr) + { + return USB_HUB_QOVR; + } + return USB_OK; + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_port_clr_feature + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hhub_request_result + * Description : Hub Request Result Check + * Arguments : uint16_t errcheck : hub result + * Return value : uint16_t : USB_OK/USB_ERROR + ******************************************************************************/ +static uint16_t usb_hhub_request_result (uint16_t errcheck) +{ + if (USB_DATA_TMO == errcheck) + { + USB_PRINTF0("*** HUB Request Timeout error !\n"); + + return USB_ERROR; + } + else if (USB_DATA_STALL == errcheck) + { + USB_PRINTF0("*** HUB Request STALL !\n"); + + return USB_ERROR; + } + else if (USB_CTRL_END != errcheck) + { + USB_PRINTF0("*** HUB Request error !\n"); + + return USB_ERROR; + } + else + { + /* Non */ + } + + return USB_OK; +} + +/****************************************************************************** + * End of function usb_hhub_request_result + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hhub_trans_complete + * Description : Receive complete Hub and Port Status Change Bitmap + * Arguments : usb_utr_t *mess : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not used. + * : uint16_t data2 : Not used. + * Return value : none + ******************************************************************************/ +static void usb_hhub_trans_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) +{ + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); + #if (BSP_CFG_RTOS != 0) + usb_er_t err; + uint16_t pipenum, hubaddr; + + usb_utr_t * ptr; + + #if (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 2) */ + ptr = (usb_utr_t *) pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == ptr) + { + USB_PRINTF0("### usb_hhub_trans_complete pvPortMalloc ERROR\n"); + + return; + } + #endif /* (BSP_CFG_RTOS == 2) */ + *ptr = *mess; + + pipenum = mess->keyword; + hubaddr = usb_hhub_get_hubaddr(ptr, pipenum); + g_usb_shhub_hub_addr[ptr->ip] = hubaddr; + + /* Set new message info */ + ptr->msginfo = USB_MSG_HUB_SUBMITRESULT; + + /** Send message **/ + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) ptr); + if (USB_OK != err) + { + vPortFree(ptr); + + /** Send Message failure **/ + USB_PRINTF1("### HUB snd_msg error (%ld)\n", err); + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + usb_er_t err; + uint16_t pipenum, hubaddr; + usb_utr_t * ptr; + + ptr = (usb_utr_t *) mess; + pipenum = mess->keyword; + hubaddr = usb_hhub_get_hubaddr(ptr, pipenum); + g_usb_shhub_hub_addr[ptr->ip] = hubaddr; + + if ((USB_MSG_HUB_SUBMITRESULT != g_usb_shhub_process[ptr->ip]) && (USB_NULL != g_usb_shhub_process[ptr->ip])) + { + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) mess); + if (USB_OK != err) + { + /* Send Message failure */ + USB_PRINTF0("### HUB snd_msg error\n"); + } + } + else + { + g_usb_shhub_process[ptr->ip] = USB_NULL; + + switch (mess->status) + { + case USB_DATA_SHT: + + /*USB_PRINTF1("*** receive short(pipe %d : HUB) !\n", pipenum);*/ + /* Continue */ + /* Direction is in then data receive end */ + case USB_DATA_OK: + { + if (USB_DEFAULT == g_usb_hstd_mgr_mode[ptr->ip]) + { + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) mess); + if (USB_OK != err) + { + USB_PRINTF0("### HUB task snd_msg error\n"); + } + } + else + { + /* HUB port connection */ + g_usb_shhub_info[ptr->ip] = USB_MSG_HUB_SUBMITRESULT; + g_usb_shhub_process[ptr->ip] = USB_MSG_HUB_EVENT; + usb_hhub_specified_path(mess); + } + + break; + } + + case USB_DATA_STALL: + { + USB_PRINTF0("*** Data Read error. (STALL) !\n"); + + /* CLEAR_FEATURE */ + usb_hstd_clr_stall(ptr, pipenum, (usb_cb_t) &usb_hstd_dummy_function); + break; + } + + case USB_DATA_OVR: + { + USB_PRINTF0("### receiver over. !\n"); + break; + } + + case USB_DATA_STOP: + { + USB_PRINTF0("### receiver stop. !\n"); + break; + } + + default: + { + USB_PRINTF0("### HUB Class Data Read error !\n"); + break; + } + } + } + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_trans_complete + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hhub_class_request_complete + * Description : Hub class check result + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not used. + * : uint16_t data2 : Not used. + * Return value : none + ******************************************************************************/ +static void usb_hhub_class_request_complete (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); + usb_mh_t p_blf; + usb_er_t err; + usb_clsinfo_t * cp; + + /* Get memory pool blk */ + if (USB_OK == USB_PGET_BLK(USB_HUB_MPL, &p_blf, ptr->ip)) + { + cp = (usb_clsinfo_t *) p_blf; + cp->msginfo = g_usb_shhub_process[ptr->ip]; + cp->keyword = ptr->keyword; + cp->result = ptr->status; + + cp->ipp = ptr->ipp; + cp->ip = ptr->ip; + + /* Send message */ + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) p_blf); + if (USB_OK != err) + { + /* Send message failure */ + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) p_blf); + USB_PRINTF0("### CheckResult function snd_msg error\n"); + } + } + else + { + USB_PRINTF0("### CheckResult function pget_blk error\n"); + + /* WAIT_LOOP */ + while (1) + { + /* Non */ + } + } +} + +/****************************************************************************** + * End of function usb_hhub_class_request_complete + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hhub_initial + * Description : Global memory initialized + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not used. + * : uint16_t data2 : Not used. + * Return value : none + ******************************************************************************/ +static void usb_hhub_initial (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); + uint16_t i; + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAXDEVADDR + 1); i++) + { + memset(g_usb_hhub_data[ptr->ip][i], 0, 8); + g_usb_shhub_down_port[ptr->ip][i] = 0; + g_usb_shhub_remote[ptr->ip][i] = 0; + memset((void *) &g_usb_shhub_info_data[ptr->ip][i], 0, sizeof(usb_hub_info_t)); + memset((void *) &g_usb_shhub_data_mess[ptr->ip][i], 0, sizeof(usb_utr_t)); + } + + memset(g_usb_hhub_descriptor[ptr->ip], 0, USB_CONFIGSIZE); + memset(g_usb_shhub_class_request[ptr->ip], 0, (5 * 2)); + memset((void *) &g_usb_shhub_ctrl_mess[ptr->ip], 0, sizeof(usb_utr_t)); + + g_usb_shhub_spec[ptr->ip] = 0; + g_usb_shhub_speed[ptr->ip] = 0; + g_usb_shhub_dev_addr[ptr->ip] = 0; + g_usb_shhub_number[ptr->ip] = 0; + + g_p_usb_shhub_device_table[ptr->ip] = 0; + g_p_usb_shhub_config_table[ptr->ip] = 0; + g_p_usb_shhub_interface_table[ptr->ip] = 0; +} + +/****************************************************************************** + * End of function usb_hhub_initial + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_pipe_info + * Description : Set pipe information + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint8_t *table : Interface Descriptor + * : uint16_t speed : device speed + * : uint16_t length : Interface Descriptor length + * Return value : uint16_t : DONE/ERROR + ******************************************************************************/ +static uint16_t usb_hhub_pipe_info (usb_utr_t * ptr, uint8_t * table, uint16_t speed, uint16_t length) +{ + uint16_t ofdsc; + uint16_t pipe_no; + usb_pipe_table_reg_t ep_tbl; + + /* Check Descriptor */ + if (USB_DT_INTERFACE != table[1]) + { + /* Configuration Descriptor */ + USB_PRINTF0("### Interface descriptor error (HUB).\n"); + + return USB_ERROR; + } + + /* Check Endpoint Descriptor */ + ofdsc = table[0]; + + /* WAIT_LOOP */ + while (ofdsc < (length - table[0])) + { + /* Search within Interface */ + switch (table[ofdsc + 1]) + { + /* Device Descriptor */ + case USB_DT_DEVICE: + + /* Configuration Descriptor */ + case USB_DT_CONFIGURATION: + + /* String Descriptor */ + case USB_DT_STRING: + + /* Interface Descriptor */ + case USB_DT_INTERFACE: + { + USB_PRINTF0("### Endpoint Descriptor error(HUB).\n"); + + return USB_ERROR; + break; + } + + /* Endpoint Descriptor */ + case USB_DT_ENDPOINT: + { + /* Interrupt Endpoint */ + if (USB_EP_INT == (table[ofdsc + 3] & USB_EP_TRNSMASK)) + { + pipe_no = usb_hstd_make_pipe_reg_info(ptr->ip, + USB_DEVICEADDR, + USB_HUB, + speed, + &table[ofdsc], + &ep_tbl); + if (USB_NULL != pipe_no) + { + usb_hstd_set_pipe_info(ptr->ip, pipe_no, &ep_tbl); + + return USB_OK; + } + } + + ofdsc += table[ofdsc]; + break; + } + + /* Device Qualifier Descriptor */ + case USB_DT_DEVICE_QUALIFIER: + + /* Other Speed Configuration */ + case USB_DT_OTHER_SPEED_CONF: + + /* Interface Power Descriptor */ + case USB_DT_INTERFACE_POWER: + { + USB_PRINTF0("### Endpoint Descriptor error(HUB).\n"); + + return USB_ERROR; + break; + } + + /* Another Descriptor */ + default: + { + ofdsc += table[ofdsc]; + break; + } + } + } + + return USB_ERROR; +} + +/****************************************************************************** + * End of function usb_hhub_pipe_info + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hhub_check_request + * Description : Class check request + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t result : Check result value + * Return value : none + ******************************************************************************/ +static void usb_hhub_check_request (usb_utr_t * ptr, uint16_t result) +{ + usb_mh_t p_blf; + usb_er_t err; + usb_clsinfo_t * cp; + + /* Get memory pool blk */ + if (USB_OK == USB_PGET_BLK(USB_HUB_MPL, &p_blf, ptr->ip)) + { + cp = (usb_clsinfo_t *) p_blf; + cp->msginfo = USB_MSG_CLS_CHECKREQUEST; + cp->result = result; + + cp->ipp = ptr->ipp; + cp->ip = ptr->ip; + + /* Send message */ + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) p_blf); + if (USB_OK != err) + { + /* Send message failure */ + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) p_blf); + USB_PRINTF0("### CheckRequest function snd_msg error\n"); + } + } + else + { + /* Get memory block failure */ + USB_PRINTF0("### CheckRequest function pget_blk error\n"); + + /* WAIT_LOOP */ + while (1) + { + /* Non */ + } + } +} + +/****************************************************************************** + * End of function usb_hhub_check_request + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hhub_chk_config + * Description : Configuration Descriptor check + * Arguments : uint16_t **table : Pointer to Configuration Descriptor area + * : uint16_t spec : HUB specification + * Return value : uint16_t : DONE/ERROR + ******************************************************************************/ +static uint16_t usb_hhub_chk_config (uint16_t ** table, uint16_t spec) +{ + uint8_t * descriptor_table; + + descriptor_table = (uint8_t *) (table[1]); + + /* Check interface number */ + switch (spec) + { + case USB_FSHUB: /* Full Speed Hub */ + { + if (USB_HUB_INTNUMFS != descriptor_table[4]) + { + USB_PRINTF0("### HUB configuration descriptor error !\n"); + + return USB_ERROR; + } + + break; + } + + case USB_HSHUBS: /* Hi Speed Hub(Multi) */ + { + if (USB_HUB_INTNUMHSS != descriptor_table[4]) + { + USB_PRINTF0("### HUB configuration descriptor error !\n"); + + return USB_ERROR; + } + + break; + } + + case USB_HSHUBM: /* Hi Speed Hub(Single) */ + { + if (USB_HUB_INTNUMHSM != descriptor_table[4]) + { + USB_PRINTF0("### HUB configuration descriptor error !\n"); + + return USB_ERROR; + } + + break; + } + + default: + { + return USB_ERROR; + break; + } + } + + return USB_OK; +} + +/****************************************************************************** + * End of function usb_hhub_chk_config + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_chk_interface + * Description : Interface Descriptor check + * Arguments : uint16_t **table : Pointer to Interface Descriptor area + * : uint16_t spec : HUB specification + * Return value : uint16_t : DONE/ERROR + ******************************************************************************/ +static uint16_t usb_hhub_chk_interface (uint16_t ** table, uint16_t spec) +{ + uint8_t * descriptor_Table; + + descriptor_Table = (uint8_t *) (table[2]); + + /* Check interface class */ + if (USB_IFCLS_HUB != descriptor_Table[5]) + { + USB_PRINTF0("### HUB interface descriptor error !\n"); + + return USB_ERROR; + } + + /* Check interface number */ + switch (spec) + { + case USB_FSHUB: /* Full Speed Hub */ + { + if ((USB_HUB_INTNUMFS - 1U) != descriptor_Table[2]) + { + USB_PRINTF0("### HUB interface descriptor error !\n"); + + return USB_ERROR; + } + + break; + } + + case USB_HSHUBS: /* Hi Speed Hub(Single) */ + { + if ((USB_HUB_INTNUMHSS - 1U) != descriptor_Table[2]) + { + USB_PRINTF0("### HUB interface descriptor error !\n"); + + return USB_ERROR; + } + + break; + } + + case USB_HSHUBM: /* Hi Speed Hub(Multi) */ + { + if ((USB_HUB_INTNUMHSM - 1U) != descriptor_Table[2]) + { + USB_PRINTF0("### HUB interface descriptor error !\n"); + + return USB_ERROR; + } + + break; + } + + default: + { + return USB_ERROR; + break; + } + } + + return USB_OK; +} + +/****************************************************************************** + * End of function usb_hhub_chk_interface + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_new_connect + * Description : new connect + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : Hub address + * : uint16_t portnum : Down port number + * : usb_clsinfo_t *mess : Pointer to usb_clsinfo_t structure + * Return value : none + ******************************************************************************/ +static void usb_hhub_new_connect (usb_utr_t * ptr, uint16_t hubaddr, uint16_t portnum, usb_clsinfo_t * mess) +{ + #if (BSP_CFG_RTOS != 0) + FSP_PARAMETER_NOT_USED(mess); + uint16_t devaddr; + uint16_t result; + + /* New down port device search */ + devaddr = usb_hhub_get_new_devaddr(ptr); + if (0 != devaddr) + { + USB_PRINTF1(" Hubport connect address%d\n", devaddr); + g_usb_shhub_info_data[ptr->ip][devaddr].up_addr = hubaddr; /* Up-hubaddr set */ + g_usb_shhub_info_data[ptr->ip][devaddr].up_port_num = portnum; /* Up-hubport set */ + + result = usb_hhub_port_attach(hubaddr, portnum, (usb_clsinfo_t *) ptr); + if (USB_CONFIGURED != result) + { + /* Hub Port Reset */ + usb_hhub_port_reset(ptr, hubaddr, portnum, (usb_clsinfo_t *) USB_NULL); + + /* Hub Port Set Feature Request */ + usb_hhub_port_set_feature(ptr, hubaddr, portnum, (uint16_t) USB_HUB_PORT_SUSPEND, class_trans_result); + + /* Hub Port Detach */ + usb_hhub_port_detach(ptr, hubaddr, portnum); + g_usb_shhub_info_data[ptr->ip][devaddr].up_addr = 0; /* Up-hubaddr clear */ + g_usb_shhub_info_data[ptr->ip][devaddr].up_port_num = 0; /* Up-hubport clear */ + } + } + else + { + USB_PRINTF0("### device count over !\n"); + } + + #else /* #if (BSP_CFG_RTOS != 0) */ + uint16_t devaddr; + + hubaddr = g_usb_shhub_hub_addr[ptr->ip]; + portnum = g_usb_shhub_event_port[ptr->ip]; + + /* New down port device search */ + devaddr = usb_hhub_get_new_devaddr(ptr); + if (0 != devaddr) + { + USB_PRINTF1(" Hubport connect address%d\n", devaddr); + g_usb_shhub_info_data[ptr->ip][devaddr].up_addr = hubaddr; /* Up-hubaddr set */ + g_usb_shhub_info_data[ptr->ip][devaddr].up_port_num = portnum; /* Up-hubport set */ + g_usb_shhub_process[ptr->ip] = USB_MSG_HUB_ATTACH; + usb_hhub_specified_path(mess); /* Next Process Selector */ + } + else + { + USB_PRINTF0("### device count over !\n"); + } + #endif /* #if (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hhub_new_connect + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_port_detach + * Description : HUB down port disconnect + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : Hub address + * : uint16_t portnum : Down port number + * Return value : none + ******************************************************************************/ +static void usb_hhub_port_detach (usb_utr_t * ptr, uint16_t hubaddr, uint16_t portnum) +{ + uint16_t md; + usb_hcdreg_t * driver; + + /* Device number --> DeviceAddress */ + uint16_t devaddr; + + /* HUB down port status */ + g_usb_shhub_down_port[ptr->ip][hubaddr] &= (uint16_t) (~USB_BITSET(portnum)); + + /* HUB down port RemoteWakeup */ + g_usb_shhub_remote[ptr->ip][hubaddr] &= (uint16_t) (~USB_BITSET(portnum)); + + /* Now down port device search */ + devaddr = usb_hhub_get_cnn_devaddr(ptr, hubaddr, portnum); + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (devaddr == driver->devaddr) + { + (*driver->devdetach)(ptr, driver->devaddr, (uint16_t) USB_NO_ARG); + + /* Root port */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][0] = USB_NOPORT; + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][1] = USB_DETACHED; + + /* Not configured */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][2] = (uint16_t) 0; + + /* Interface Class : NO class */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][3] = (uint16_t) USB_IFCLS_NOT; + + /* No connect */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][4] = (uint16_t) USB_NOCONNECT; + + /* Root port */ + driver->rootport = USB_NOPORT; + + /* Device address */ + driver->devaddr = USB_NODEVICE; + + /* Device state */ + driver->devstate = USB_DETACHED; + } + } + + /* Selective detach */ + usb_hhub_selective_detach(ptr, devaddr); +} + +/****************************************************************************** + * End of function usb_hhub_port_detach + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_selective_detach + * Description : HUB down port Selective disconnect + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t devadr : Device address + * Return value : none + ******************************************************************************/ +static void usb_hhub_selective_detach (usb_utr_t * ptr, uint16_t devaddr) +{ + uint16_t addr, i; + + addr = (uint16_t) (devaddr << USB_DEVADDRBIT); + + /* Check Connection */ + if (USB_NOCONNECT != usb_hstd_get_dev_speed(ptr, addr)) + { + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i <= USB_MAX_PIPE_NO; i++) + { + /* Not control transfer */ + if (usb_hstd_get_device_address(ptr, i) == addr) + { + /* Agreement device address */ + if (USB_PID_BUF == usb_cstd_get_pid(ptr, i)) + { + /* PID=BUF ? */ + usb_hstd_transfer_end(ptr, i, (uint16_t) USB_DATA_STOP); + } + + usb_cstd_clr_pipe_cnfg(ptr, i); + } + } + + usb_hstd_set_dev_addr(ptr, addr, USB_NOCONNECT); + usb_hstd_set_hub_port(ptr, addr, USB_NULL, USB_NULL); + USB_PRINTF1("*** Device address %d clear.\n", devaddr); + } + + /* Root port */ + g_usb_hstd_device_info[ptr->ip][devaddr][0] = USB_NOPORT; + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][devaddr][1] = USB_DETACHED; + + /* Not configured */ + g_usb_hstd_device_info[ptr->ip][devaddr][2] = (uint16_t) 0; + + /* Interface Class : NO class */ + g_usb_hstd_device_info[ptr->ip][devaddr][3] = (uint16_t) USB_IFCLS_NOT; + + /* No connect */ + g_usb_hstd_device_info[ptr->ip][devaddr][4] = (uint16_t) USB_NOCONNECT; +} + +/****************************************************************************** + * End of function usb_hhub_selective_detach + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_get_string_descriptor1 + * Description : Get String descriptor + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t devaddr : Device address + * : uint16_t index : Descriptor index + * : usb_cb_t complete : Callback function + * Return value : uint16_t : error info + ******************************************************************************/ +uint16_t usb_hhub_get_string_descriptor1 (usb_utr_t * ptr, uint16_t devaddr, uint16_t index, usb_cb_t complete) +{ + FSP_PARAMETER_NOT_USED(index); + #if (BSP_CFG_RTOS != 0) + FSP_PARAMETER_NOT_USED(complete); + usb_hstd_get_string_desc(ptr, devaddr, (uint16_t) 0); + #else /* #if (BSP_CFG_RTOS != 0) */ + usb_hstd_get_string_desc(ptr, devaddr, (uint16_t) 0, complete); + #endif /* #if (BSP_CFG_RTOS != 0) */ + + return USB_OK; +} + +/****************************************************************************** + * End of function usb_hhub_get_string_descriptor1 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_get_string_descriptor2 + * Description : Get String descriptor + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t devaddr : Device address + * : uint16_t index : Descriptor index + * : usb_cb_t complete : Callback function + * Return value : uint16_t : error info + ******************************************************************************/ +uint16_t usb_hhub_get_string_descriptor2 (usb_utr_t * ptr, uint16_t devaddr, uint16_t index, usb_cb_t complete) +{ + #if (BSP_CFG_RTOS != 0) + FSP_PARAMETER_NOT_USED(complete); + usb_hstd_get_string_desc(ptr, devaddr, index); + #else /* #if (BSP_CFG_RTOS != 0) */ + usb_hstd_get_string_desc(ptr, devaddr, index, complete); + #endif /* #if (BSP_CFG_RTOS != 0) */ + return USB_OK; +} + +/****************************************************************************** + * End of function usb_hhub_get_string_descriptor2 + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hhub_get_string_descriptor1check + * Description : Get String descriptor Check + * Arguments : uint16_t errcheck : errcheck + * Return value : uint16_t : error info + ******************************************************************************/ +uint16_t usb_hhub_get_string_descriptor1check (uint16_t errcheck) +{ + if ((usb_er_t) USB_DATA_STALL == errcheck) + { + USB_PRINTF0("*** LanguageID not support !\n"); + + return USB_ERROR; + } + else if ((usb_er_t) USB_CTRL_END != errcheck) + { + USB_PRINTF0("*** LanguageID not support !\n"); + + return USB_ERROR; + } + else + { + /* Non */ + } + + return USB_OK; +} + +/****************************************************************************** + * End of function usb_hhub_get_string_descriptor1check + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_get_string_descriptor_to_check + * Description : Get String descriptor Check + * Arguments : uint16_t errcheck : errcheck + * Return value : uint16_t : error info + ******************************************************************************/ +uint16_t usb_hhub_get_string_descriptor_to_check (uint16_t errcheck) +{ + if ((usb_er_t) USB_DATA_STALL == errcheck) + { + USB_PRINTF0("*** SerialNumber not support !\n"); + + return USB_ERROR; + } + else if ((usb_er_t) USB_CTRL_END != errcheck) + { + USB_PRINTF0("*** SerialNumber not support !\n"); + + return USB_ERROR; + } + else + { + /* Non */ + } + + return USB_OK; +} + +/****************************************************************************** + * End of function usb_hhub_get_string_descriptor_to_check + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hhub_get_new_devaddr + * Description : Get the new device address + * : when connection of a device detected in the down port of HUB + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : uint16_t : Device address + ******************************************************************************/ +static uint16_t usb_hhub_get_new_devaddr (usb_utr_t * ptr) +{ + uint16_t i; + + /* Search new device */ + /* WAIT_LOOP */ + for (i = (USB_HUBDPADDR); i < (USB_MAXDEVADDR + 1U); i++) + { + if (0 == g_usb_shhub_info_data[ptr->ip][i].up_addr) + { + + /* New device address */ + return i; + } + } + + return 0; +} + +/****************************************************************************** + * End of function usb_hhub_get_new_devaddr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_get_hubaddr + * Description : Get the HUB address + * : from the pipe number for HUB notification + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipenum : Pipe number + * Return value : uint16_t : HUB address + ******************************************************************************/ +static uint16_t usb_hhub_get_hubaddr (usb_utr_t * ptr, uint16_t pipenum) +{ + uint16_t i; + + /* WAIT_LOOP */ + for (i = 1; i < (USB_MAXDEVADDR + 1U); i++) + { + if (g_usb_shhub_info_data[ptr->ip][i].pipe_num == pipenum) + { + + /* HUB address */ + return i; + } + } + + return 0; +} + +/****************************************************************************** + * End of function usb_hhub_get_hubaddr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_get_cnn_devaddr + * Description : Get the connected device address + * : from the HUB address and the down port number of a HUB + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t hubaddr : Hub address + * : uint16_t portnum : Down port number + * Return value : uint16_t : Connected device address + ******************************************************************************/ +static uint16_t usb_hhub_get_cnn_devaddr (usb_utr_t * ptr, uint16_t hubaddr, uint16_t portnum) +{ + uint16_t i; + + /* WAIT_LOOP */ + for (i = (USB_HUBDPADDR); i < (USB_MAXDEVADDR + 1U); i++) + { + if ((g_usb_shhub_info_data[ptr->ip][i].up_addr == hubaddr) && + (g_usb_shhub_info_data[ptr->ip][i].up_port_num == portnum)) + { + + /* Device address */ + return i; + } + } + + return 0; +} + +/****************************************************************************** + * End of function usb_hhub_get_cnn_devaddr + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hhub_specified_path + * Description : Next Process Selector + * Arguments : usb_clsinfo_t *ptr : Pointer to usb_clsinfo_t structure. + * Return value : none + ******************************************************************************/ +static void usb_hhub_specified_path (usb_clsinfo_t * ptr) +{ + usb_mh_t p_blf; + usb_er_t err; + usb_clsinfo_t * cp; + + /* Get memory pool blk */ + if (USB_OK == USB_PGET_BLK(USB_HUB_MPL, &p_blf, ptr->ip)) + { + cp = (usb_clsinfo_t *) p_blf; + cp->msginfo = g_usb_shhub_process[ptr->ip]; + cp->keyword = ptr->keyword; + cp->result = ptr->result; + + cp->ipp = ptr->ipp; + cp->ip = ptr->ip; + + /* Send message */ + err = USB_SND_MSG(USB_HUB_MBX, (usb_msg_t *) p_blf); + if (USB_OK != err) + { + /* Send message failure */ + err = USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) p_blf); + USB_PRINTF0("### SpecifiedPass function snd_msg error\n"); + } + } + else + { + /* Get memory block failure */ + USB_PRINTF0("### SpecifiedPass function pget_blk error\n"); + + /* WAIT_LOOP */ + while (1) + { + /* Non */ + } + } +} + +/****************************************************************************** + * End of function usb_hhub_specified_path + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hhub_specified_path_wait + * Description : Next Process Selector + * Arguments : usb_clsinfo_t *mess : USB system internal message. + * : uint16_t times : Timeout value. + * Return value : none + ******************************************************************************/ +static void usb_hhub_specified_path_wait (usb_clsinfo_t * ptr, uint16_t times) +{ + usb_mh_t p_blf; + fsp_err_t err; + usb_clsinfo_t * hp; + + /* Get memory pool blk */ + if (USB_OK == USB_PGET_BLK(USB_HUB_MPL, &p_blf, ptr->ip)) + { + hp = (usb_clsinfo_t *) p_blf; + hp->msginfo = g_usb_shhub_process[ptr->ip]; + hp->keyword = ptr->keyword; + hp->result = ptr->result; + + hp->ipp = ptr->ipp; + hp->ip = ptr->ip; + + /* Wait message */ + err = USB_WAI_MSG(USB_HUB_MBX, (usb_msg_t *) p_blf, times); + if (USB_OK != err) + { + /* Wait message failure */ + USB_REL_BLK(USB_HUB_MPL, (usb_mh_t) p_blf); + USB_PRINTF0("### SpecifiedPassWait function snd_msg error\n"); + } + } + else + { + USB_PRINTF0("### SpecifiedPassWait function pget_blk error\n"); + + /* WAIT_LOOP */ + while (1) + { + /* Non */ + } + } +} + +/****************************************************************************** + * End of function usb_hhub_specified_path_wait + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ +#endif /* USB_CFG_HUB == USB_CFG_ENABLE */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hintfifo.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hintfifo.c new file mode 100644 index 0000000000..bf3783a40f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hintfifo.c @@ -0,0 +1,365 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Renesas Abstracted Host FIFO Interrupt functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_brdy_pipe + * Description : BRDY Interrupt + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t bitsts : BRDYSTS Reg & BRDYENB Reg + * Return value : none + ******************************************************************************/ +void usb_hstd_brdy_pipe (usb_utr_t * ptr) +{ + uint16_t bitsts; + + bitsts = ptr->status; + + /* When operating by the host function, usb_hstd_brdy_pipe() is executed without fail because */ + /* only one BRDY message is issued even when the demand of PIPE0 and PIPEx has been generated at the same time. */ + if (USB_BRDY0 == (bitsts & USB_BRDY0)) + { + /* Branch by the Control transfer stage management */ + switch (g_usb_hstd_ctsq[ptr->ip]) + { + /* Data stage of Control read transfer */ + case USB_DATARD: + { + switch (usb_hstd_read_data(ptr, USB_PIPE0, USB_CUSE)) + { + /* End of data read */ + case USB_READEND: + + /* continue */ + /* End of data read */ + case USB_READSHRT: + { + usb_hstd_status_start(ptr); + break; + } + + case USB_READING: /* Continue of data read */ + { + break; + } + + case USB_READOVER: /* FIFO access error */ + { + USB_PRINTF0("### Receive data over PIPE0 \n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_OVR); /* Control Read/Write End */ + break; + } + + case USB_FIFOERROR: /* FIFO access error */ + { + USB_PRINTF0("### FIFO access error \n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); /* Control Read/Write End */ + break; + } + + default: + { + break; + } + } + + break; + } + + /* Data stage of Control read transfer */ + case USB_DATARDCNT: + { + switch (usb_hstd_read_data(ptr, USB_PIPE0, USB_CUSE)) + { + case USB_READEND: /* End of data read */ + { + usb_hstd_ctrl_end(ptr, (uint16_t) USB_CTRL_READING); /* Control Read/Write End */ + break; + } + + case USB_READSHRT: /* End of data read */ + { + usb_hstd_status_start(ptr); /* Control Read/Write Status */ + break; + } + + case USB_READING: /* Continue of data read */ + { + break; + } + + case USB_READOVER: /* FIFO access error */ + { + USB_PRINTF0("### Receive data over PIPE0 \n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_OVR); /* Control Read/Write End */ + break; + } + + case USB_FIFOERROR: /* FIFO access error */ + { + USB_PRINTF0("### FIFO access error \n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); /* Control Read/Write End */ + break; + } + + default: + { + break; + } + } + + break; + } + + /* Status stage of Control write (NoData control) transfer */ + case USB_STATUSWR: + { + usb_hstd_ctrl_end(ptr, (uint16_t) USB_CTRL_END); /* Control Read/Write End */ + break; + } + + default: + { + break; + } + } + } + + /* BRDY interrupt */ + usb_hstd_brdy_pipe_process(ptr, bitsts); +} + +/****************************************************************************** + * End of function usb_hstd_brdy_pipe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_nrdy_pipe + * Description : NRDY Interrupt + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t bitsts : NRDYSTS Reg & NRDYENB Reg + * Return value : none + ******************************************************************************/ +void usb_hstd_nrdy_pipe (usb_utr_t * ptr) +{ + uint16_t buffer; + uint16_t bitsts; + + bitsts = ptr->status; + + /* When operating by the host function, usb_hstd_nrdy_pipe() is executed without fail because */ + /* only one NRDY message is issued even when the demand of PIPE0 and PIPEx has been generated at the same time. */ + if (USB_NRDY0 == (bitsts & USB_NRDY0)) + { + /* Get Pipe PID from pipe number */ + buffer = usb_cstd_get_pid(ptr, (uint16_t) USB_PIPE0); + + /* STALL ? */ + if (USB_PID_STALL == (buffer & USB_PID_STALL)) + { + USB_PRINTF0("### STALL Pipe 0\n"); + + /* PIPE0 STALL call back */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_STALL); + } + else + { + /* Ignore count */ + g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0]++; + USB_PRINTF2("### IGNORE Pipe %d is %d times \n", USB_PIPE0, g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0]); + + /* Pipe error check */ + if (USB_PIPEERROR == g_usb_hstd_ignore_cnt[ptr->ip][USB_PIPE0]) + { + /* Control Data Stage Device Ignore X 3 call back */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); + } + else + { + /* Control Data Stage Retry */ + /* 5ms wait */ + usb_cpu_delay_xms((uint16_t) 5); + + /* PIPE0 Send IN or OUT token */ + usb_cstd_set_buf(ptr, (uint16_t) USB_PIPE0); + } + } + } + + /* Nrdy Pipe interrupt */ + usb_hstd_nrdy_pipe_process(ptr, bitsts); +} + +/****************************************************************************** + * End of function usb_hstd_nrdy_pipe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_bemp_pipe + * Description : BEMP interrupt + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t bitsts : BEMPSTS Reg & BEMPENB Reg + * Return value : none + ******************************************************************************/ +void usb_hstd_bemp_pipe (usb_utr_t * ptr) +{ + uint16_t buffer; + uint16_t bitsts; + + bitsts = ptr->status; + + /* When operating by the host function, usb_hstd_bemp_pipe() is executed without fail because */ + /* only one BEMP message is issued even when the demand of PIPE0 and PIPEx has been generated at the same time. */ + if (USB_BEMP0 == (bitsts & USB_BEMP0)) + { + buffer = usb_cstd_get_pid(ptr, (uint16_t) USB_PIPE0); /* Get Pipe PID from pipe number */ + if (USB_PID_STALL == (buffer & USB_PID_STALL)) /* MAX packet size error ? */ + { + USB_PRINTF0("### STALL Pipe 0\n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_STALL); /* PIPE0 STALL call back */ + } + else + { + switch (g_usb_hstd_ctsq[ptr->ip]) /* Branch by the Control transfer stage management */ + { + /* Continuas of data stage (Control write) */ + case USB_DATAWR: + { + switch (usb_hstd_write_data(ptr, USB_PIPE0, USB_CUSE)) /* Buffer to CFIFO data write */ + { + /* End of data write */ + case USB_WRITESHRT: + { + g_usb_hstd_ctsq[ptr->ip] = USB_STATUSWR; /* Next stage is Control write status stage */ + hw_usb_set_bempenb(ptr, (uint16_t) USB_PIPE0); /* Enable Empty Interrupt */ + usb_cstd_nrdy_enable(ptr, (uint16_t) USB_PIPE0); /* Enable Not Ready Interrupt */ + break; + } + + /* End of data write (not null) */ + case USB_WRITEEND: + + /* continue */ + /* Continue of data write */ + case USB_WRITING: + { + hw_usb_set_bempenb(ptr, (uint16_t) USB_PIPE0); /* Enable Empty Interrupt */ + usb_cstd_nrdy_enable(ptr, (uint16_t) USB_PIPE0); /* Enable Not Ready Interrupt */ + break; + } + + /* FIFO access error */ + case USB_FIFOERROR: + { + USB_PRINTF0("### FIFO access error \n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); /* Control Read/Write End */ + break; + } + + default: + { + break; + } + } + + break; + } + + /* Next stage to Control write data */ + case USB_DATAWRCNT: + { + /* Buffer to CFIFO data write */ + switch (usb_hstd_write_data(ptr, USB_PIPE0, USB_CUSE)) + { + /* End of data write */ + case USB_WRITESHRT: + { + g_usb_hstd_ctsq[ptr->ip] = USB_STATUSWR; /* Next stage is Control write status stage */ + hw_usb_set_bempenb(ptr, (uint16_t) USB_PIPE0); /* Enable Empty Interrupt */ + usb_cstd_nrdy_enable(ptr, (uint16_t) USB_PIPE0); /* Enable Not Ready Interrupt */ + break; + } + + /* End of data write (not null) */ + case USB_WRITEEND: + { + usb_hstd_ctrl_end(ptr, (uint16_t) USB_CTRL_WRITING); /* Control Read/Write End */ + break; + } + + /* Continue of data write */ + case USB_WRITING: + { + hw_usb_set_bempenb(ptr, (uint16_t) USB_PIPE0); /* Enable Empty Interrupt */ + usb_cstd_nrdy_enable(ptr, (uint16_t) USB_PIPE0); /* Enable Not Ready Interrupt */ + break; + } + + /* FIFO access error */ + case USB_FIFOERROR: + { + USB_PRINTF0("### FIFO access error \n"); + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); /* Control Read/Write End */ + break; + } + + default: + { + break; + } + } + + break; + } + + case USB_STATUSWR: /* End of data stage (Control write) */ + { + usb_hstd_status_start(ptr); + break; + } + + case USB_STATUSRD: /* Status stage of Control read transfer */ + { + usb_hstd_ctrl_end(ptr, (uint16_t) USB_CTRL_END); /* Control Read/Write End */ + break; + } + + default: + { + break; + } + } + } + } + + usb_hstd_bemp_pipe_process(ptr, bitsts); /* BEMP interrupt */ +} + +/****************************************************************************** + * End of function usb_hstd_bemp_pipe + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip0.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip0.c new file mode 100644 index 0000000000..8c12100b2d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip0.c @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +usb_utr_t g_usb_cstd_int_msg[USB_NUM_USBIP][USB_INTMSGMAX]; /* Interrupt message */ +uint16_t g_usb_cstd_int_msg_cnt[USB_NUM_USBIP]; /* Interrupt message count */ + +/****************************************************************************** + * Renesas Abstracted common Interrupt handler functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_usb_handler + * Description : USB interrupt routine. Analyze which USB interrupt occurred + * : and send message to PCD/HCD task. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_hstd_usb_handler (void) +{ + usb_utr_t * ptr; + usb_er_t err; + IRQn_Type irq; + usb_cfg_t * p_cfg; + + irq = R_FSP_CurrentIrqGet(); + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet(irq); + + /* Initial pointer */ + ptr = &g_usb_cstd_int_msg[0][g_usb_cstd_int_msg_cnt[0]]; + ptr->ip = USB_IP0; + ptr->ipp = usb_hstd_get_usb_ip_adr(ptr->ip); + ptr->p_transfer_rx = p_cfg->p_transfer_rx; + ptr->p_transfer_tx = p_cfg->p_transfer_tx; + + /* Host Function */ + /* Host Interrupt handler */ + usb_hstd_interrupt_handler(ptr); + ptr->msghead = (usb_mh_t) USB_NULL; + + /* Send message */ + err = USB_ISND_MSG(USB_HCD_MBX, (usb_msg_t *) ptr); + if (USB_OK != err) + { + USB_PRINTF1("### lib_UsbHandler DEF2 isnd_msg error (%ld)\n", err); + } + + /* Renewal Message count */ + g_usb_cstd_int_msg_cnt[0]++; + if (USB_INTMSGMAX == g_usb_cstd_int_msg_cnt[0]) + { + g_usb_cstd_int_msg_cnt[0] = 0; + } +} + +/****************************************************************************** + * End of function usb_hstd_usb_handler + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_dma_handler + * Description : DMA interrupt routine. Send message to PCD/HCD task. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_hstd_dma_handler (void) +{ + /* Non processing*/ +} + +/****************************************************************************** + * End of function usb_hstd_dma_handler + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_init_usb_message + * Description : Initialization of message to be used at time of USB interrupt. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_init_usb_message (usb_utr_t * ptr) +{ + /* TD.5.4 The interruption message of PCD is notified to HCD. */ + uint16_t i; + uint16_t msg_info; + + /* Host Function */ + msg_info = USB_MSG_HCD_INT; + + /* WAIT_LOOP */ + for (i = 0; i < USB_INTMSGMAX; i++) + { + g_usb_cstd_int_msg[ptr->ip][i].msginfo = msg_info; + } + + g_usb_cstd_int_msg_cnt[ptr->ip] = 0; +} + +/****************************************************************************** + * End of function usb_hstd_init_usb_message + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip1.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip1.c new file mode 100644 index 0000000000..2db5582923 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip1.c @@ -0,0 +1,76 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if USB_NUM_USBIP == 2 + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + +/****************************************************************************** + * Renesas Abstracted common Interrupt handler functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb2_hstd_usb_handler + * Description : USB2 interrupt routine. Analyze which USB interrupt occurred + * : and send message to PCD/HCD task. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb2_hstd_usb_handler (void) +{ + usb_utr_t * ptr; + usb_er_t err; + IRQn_Type irq; + usb_cfg_t * p_cfg; + + irq = R_FSP_CurrentIrqGet(); + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet(irq); + + /* Initial pointer */ + ptr = &g_usb_cstd_int_msg[1][g_usb_cstd_int_msg_cnt[1]]; + ptr->ip = USB_IP1; + ptr->ipp = usb_hstd_get_usb_ip_adr(ptr->ip); + ptr->p_transfer_rx = p_cfg->p_transfer_rx; + ptr->p_transfer_tx = p_cfg->p_transfer_tx; + + /* Host Function */ + /* Host Interrupt handler */ + usb_hstd_interrupt_handler(ptr); + ptr->msghead = (usb_mh_t) USB_NULL; + + /* Send message */ + err = USB_ISND_MSG(USB_HCD_MBX, (usb_msg_t *) ptr); + if (err != USB_OK) + { + /*USB_PRINTF1("### lib_UsbHandler DEF2 isnd_msg error (%ld)\n", err);*/ + } + + /* Renewal Message count */ + g_usb_cstd_int_msg_cnt[1]++; + if (USB_INTMSGMAX == g_usb_cstd_int_msg_cnt[1]) + { + g_usb_cstd_int_msg_cnt[1] = 0; + } +} + + #endif /* #if USB_NUM_USBIP == 2 */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c new file mode 100644 index 0000000000..06438c54fe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c @@ -0,0 +1,2531 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "../hw/inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HMSC_USE) + #include "../../../r_usb_hmsc/src/inc/r_usb_hmsc_driver.h" + #endif /* defined(USB_CFG_HMSC_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if defined(USB_CFG_OTG_USE) + #if defined(USB_CFG_HCDC_USE) + #include "r_usb_otg_cdc_cfg.h" + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) + #include "r_usb_otg_hid_cfg.h" + #endif /* defined(USB_CFG_HHID_USE) */ +#else /* defined(USB_CFG_OTG_USE) */ + #if defined(USB_CFG_HCDC_USE) + #include "r_usb_hcdc_cfg.h" +uint8_t g_usb_hcdc_bulk_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_hcdc_bulk_out_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_hcdc_int_in_pipe[USB_NUM_USBIP] = {0}; + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) +uint8_t g_usb_hcdc2_bulk_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_hcdc2_bulk_out_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_hcdc2_int_in_pipe[USB_NUM_USBIP] = {0}; + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) + #include "r_usb_hhid_cfg.h" +uint8_t g_usb_hhid_int_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_hhid_int_out_pipe[USB_NUM_USBIP] = {0}; + #if (USB_CFG_HHID_MULTI == USB_CFG_ENABLE) +uint8_t g_usb_hhid2_int_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_hhid3_int_in_pipe[USB_NUM_USBIP] = {0}; + #endif + #endif /* defined(USB_CFG_HHID_USE) */ +#endif /* defined(USB_CFG_OTG_USE) */ + +#if defined(USB_CFG_HPRN_USE) + #include "r_usb_hprn_cfg.h" +uint8_t g_usb_hprn_bulk_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_hprn_bulk_out_pipe[USB_NUM_USBIP] = {0}; + #if (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) +uint8_t g_usb_hprn2_bulk_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_hprn2_bulk_out_pipe[USB_NUM_USBIP] = {0}; + #endif +#endif /* defined(USB_CFG_HPRN_USE) */ + +#if defined(USB_CFG_HUVC_USE) + #include "r_usb_huvc_cfg.h" +uint8_t g_usb_huvc_iso_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_huvc_iso_out_pipe[USB_NUM_USBIP] = {0}; +#endif /* defined(USB_CFG_HPRN_USE) */ + +#if defined(USB_CFG_HAUD_USE) + #include "r_usb_haud_cfg.h" +uint8_t g_usb_haud_iso_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_haud_iso_out_pipe[USB_NUM_USBIP] = {0}; +#endif /* defined(USB_CFG_HAUD_USE) */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) +extern transfer_instance_t * g_p_usbx_transfer_tx[USB_NUM_USBIP]; +extern transfer_instance_t * g_p_usbx_transfer_rx[USB_NUM_USBIP]; + #endif /* #if (USB_CFG_DMA == USB_CFG_ENABLE) */ + +/****************************************************************************** + * Renesas Abstracted Host Lib IP functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_set_dev_addr + * Description : Set USB speed (Full/Hi) of the connected USB Device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t addr : device address + * : uint16_t speed : device speed + * Return value : none + ******************************************************************************/ +void usb_hstd_set_dev_addr (usb_utr_t * ptr, uint16_t addr, uint16_t speed) +{ + if (USB_DEVICE_0 == addr) + { + hw_usb_write_dcpmxps(ptr, (uint16_t) (USB_DEFPACKET + USB_DEVICE_0)); + } + + hw_usb_hset_usbspd(ptr, addr, speed); +} + +/****************************************************************************** + * End of function usb_hstd_set_dev_addr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_bchg_enable + * Description : Enable BCHG interrupt for the specified USB port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_bchg_enable (usb_utr_t * ptr) +{ + hw_usb_hclear_sts_bchg(ptr); + hw_usb_hset_enb_bchge(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_bchg_enable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_bchg_disable + * Description : Disable BCHG interrupt for specified USB port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_bchg_disable (usb_utr_t * ptr) +{ + hw_usb_hclear_sts_bchg(ptr); + hw_usb_hclear_enb_bchge(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_bchg_disable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_set_uact + * Description : Start sending SOF to the connected USB device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_set_uact (usb_utr_t * ptr) +{ + hw_usb_rmw_dvstctr(ptr, USB_UACT, ((USB_USBRST | USB_RESUME) | USB_UACT)); +} + +/****************************************************************************** + * End of function usb_hstd_set_uact + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_ovrcr_enable + * Description : Enable OVRCR interrupt of the specified USB port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_ovrcr_enable (usb_utr_t * ptr) +{ + hw_usb_hclear_sts_ovrcr(ptr); + hw_usb_hset_enb_ovrcre(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_ovrcr_enable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_ovrcr_disable + * Description : Disable OVRCR interrupt of the specified USB port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_ovrcr_disable (usb_utr_t * ptr) +{ + /* OVRCR Clear(INT_N edge sense) */ + hw_usb_hclear_sts_ovrcr(ptr); + + /* Over-current disable */ + hw_usb_hclear_enb_ovrcre(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_ovrcr_disable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_attch_enable + * Description : Enable ATTCH (attach) interrupt of the specified USB port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_attch_enable (usb_utr_t * ptr) +{ + /* ATTCH status Clear */ + hw_usb_hclear_sts_attch(ptr); + + /* Attach enable */ + hw_usb_hset_enb_attche(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_attch_enable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_attch_disable + * Description : Disable ATTCH (attach) interrupt of the specified USB port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_attch_disable (usb_utr_t * ptr) +{ + /* ATTCH Clear(INT_N edge sense) */ + hw_usb_hclear_sts_attch(ptr); + + /* Attach disable */ + hw_usb_hclear_enb_attche(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_attch_disable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_dtch_enable + * Description : Enable DTCH (detach) interrupt of the specified USB port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_dtch_enable (usb_utr_t * ptr) +{ + /* DTCH Clear */ + hw_usb_hclear_sts_dtch(ptr); + + /* Detach enable */ + hw_usb_hset_enb_dtche(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_dtch_enable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_dtch_disable + * Description : Disable DTCH (detach) interrupt of the specified USB port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_dtch_disable (usb_utr_t * ptr) +{ + /* DTCH Clear(INT_N edge sense) */ + hw_usb_hclear_sts_dtch(ptr); + + /* Detach disable */ + hw_usb_hclear_enb_dtche(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_dtch_disable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_chk_dev_addr + * Description : Get USB speed set in USB register based on the specified USB + * : Device address and USB port no. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t addr : device address + * Return value : uint16_t : USB speed etc + ******************************************************************************/ +uint16_t usb_hstd_chk_dev_addr (usb_utr_t * ptr, uint16_t addr) +{ + uint16_t buffer; + + /* Get device address configuration register from device address */ + buffer = hw_usb_hread_devadd(ptr, addr); + if (USB_ERROR != buffer) + { + + /* Return Address check result */ + return (uint16_t) (buffer & USB_USBSPD); + } + + return USB_NOCONNECT; +} + +/****************************************************************************** + * End of function usb_hstd_chk_dev_addr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_get_dev_speed + * Description : Get USB speed set in USB register based on the specified USB + * : Device address. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t addr : device address + * Return value : uint16_t : device speed + * Note : Use also to a connection check is possible + ******************************************************************************/ +uint16_t usb_hstd_get_dev_speed (usb_utr_t * ptr, uint16_t addr) +{ + uint16_t buffer; + + /* Get device address configuration register from device address */ + buffer = hw_usb_hread_devadd(ptr, addr); + if (USB_ERROR != buffer) + { + + /* Return device speed */ + return (uint16_t) (buffer & USB_USBSPD); + } + + return USB_NOCONNECT; +} + +/****************************************************************************** + * End of function usb_hstd_get_dev_speed + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_pipe_to_epadr + * Description : Get the associated endpoint value of the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint8_t : OK : Endpoint nr + direction. + * : : ERROR : Error. + ******************************************************************************/ +uint8_t usb_hstd_pipe_to_epadr (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t buffer; + uint16_t direp; + + if (USB_MAX_PIPE_NO < pipe) + { + return USB_NULL; /* Error */ + } + + /* Pipe select */ + hw_usb_write_pipesel(ptr, pipe); + + /* Read Pipe direction */ + buffer = hw_usb_read_pipecfg(ptr); + direp = (uint16_t) ((((buffer & USB_DIRFIELD) ^ USB_DIRFIELD) << 3) + (buffer & USB_EPNUMFIELD)); + + return (uint8_t) (direp); +} + +/****************************************************************************** + * End of function usb_hstd_pipe_to_epadr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_pipe2fport + * Description : Get port No. from the specified pipe No. by argument + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint16_t : FIFO port selector. + ******************************************************************************/ +uint16_t usb_hstd_pipe2fport (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t fifo_mode = USB_CUSE; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t usb_dir; + #endif /* #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (USB_MAX_PIPE_NO < pipe) + { + return USB_NULL; /* Error */ + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + { + #if ((USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) || (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE)) + if ((USB_PIPE1 == pipe) || (USB_PIPE2 == pipe)) + #else + if (USB_PIPE5 >= pipe) + #endif + { + hw_usb_write_pipesel(ptr, pipe); + usb_dir = hw_usb_read_pipecfg(ptr); + usb_dir = usb_dir & USB_DIRFIELD; + if (0 == usb_dir) + { + #if (BSP_CFG_RTOS == 1) + if (0 != g_p_usbx_transfer_rx[ptr->ip]) + { + fifo_mode = USB_D0USE; + } + + #else + if (0 != ptr->p_transfer_rx) + { + fifo_mode = USB_D0USE; + } + #endif + } + else + { + #if (BSP_CFG_RTOS == 1) + if (0 != g_p_usbx_transfer_tx[ptr->ip]) + { + fifo_mode = USB_D1USE; + } + + #else + if (0 != ptr->p_transfer_tx) + { + fifo_mode = USB_D1USE; + } + #endif + } + } + } + #else /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + (void) *ptr; + #endif + + return fifo_mode; +} + +/****************************************************************************** + * End of function usb_hstd_pipe2fport + ******************************************************************************/ + + #if defined(USB_HIGH_SPEED_MODULE) + +/****************************************************************************** + * Function Name : usb_hstd_set_hse + * Description : Set/clear the HSE-bit of the specified port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t speed : USB_HS_ENABLE/USB_HS_DISABLE. + * Return value : none + ******************************************************************************/ +void usb_hstd_set_hse (usb_utr_t * ptr, uint16_t speed) +{ + if (USB_HS_DISABLE == speed) + { + /* HSE = disable */ + hw_usb_clear_hse(ptr); + } + else + { + /* HSE = enable */ + hw_usb_set_hse(ptr); + } +} + +/****************************************************************************** + * End of function usb_hstd_set_hse + ******************************************************************************/ + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + +/****************************************************************************** + * Function Name : usb_hstd_berne_enable + * Description : Enable BRDY/NRDY/BEMP interrupt. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_berne_enable (usb_utr_t * ptr) +{ + /* Enable BEMP, NRDY, BRDY */ + hw_usb_set_intenb(ptr, ((USB_BEMPE | USB_NRDYE) | USB_BRDYE)); +} + +/****************************************************************************** + * End of function usb_hstd_berne_enable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_sw_reset + * Description : Request USB IP software reset + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_sw_reset (usb_utr_t * ptr) +{ + /* USB Enable */ + hw_usb_set_usbe(ptr); + + /* USB Reset */ + hw_usb_clear_usbe(ptr); + + /* USB Enable */ + hw_usb_set_usbe(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_sw_reset + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_do_sqtgl + * Description : Toggle setting of the toggle-bit for the specified pipe by + * : argument. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * : uint16_t toggle : Current toggle status. + * Return value : none + ******************************************************************************/ +void usb_hstd_do_sqtgl (usb_utr_t * ptr, uint16_t pipe, uint16_t toggle) +{ + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Check toggle */ + if (USB_SQMON == (toggle & USB_SQMON)) + { + /* Do pipe SQSET */ + hw_usb_set_sqset(ptr, pipe); + } + else + { + /* Do pipe SQCLR */ + hw_usb_set_sqclr(ptr, pipe); + } +} + +/****************************************************************************** + * End of function usb_hstd_do_sqtgl + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_get_devsel + * Description : Get device address from pipe number + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint16_t DEVSEL-bit status + ******************************************************************************/ +uint16_t usb_hstd_get_devsel (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t devsel; + uint16_t buffer; + + if (USB_MAX_PIPE_NO < pipe) + { + return USB_NULL; /* Error */ + } + + if (USB_PIPE0 == pipe) + { + buffer = hw_usb_read_dcpmaxp(ptr); + } + else + { + /* Pipe select */ + hw_usb_write_pipesel(ptr, pipe); + buffer = hw_usb_read_pipemaxp(ptr); + } + + /* Device address */ + devsel = (uint16_t) (buffer & USB_DEVSEL); + + return devsel; +} + +/****************************************************************************** + * End of function usb_hstd_get_devsel + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_get_device_address + * Description : Get the device address associated with the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint16_t DEVSEL-bit status + ******************************************************************************/ +uint16_t usb_hstd_get_device_address (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t buffer; + uint16_t result = USB_ERROR; + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("*** usb_hstd_get_device_address PipeNo ERROR %d\n", pipe); + result = USB_ERROR; /* Error */ + return result; + } + + /* Host */ + if (USB_PIPE0 == pipe) + { + buffer = hw_usb_read_dcpmaxp(ptr); + + /* Device address */ + result = (uint16_t) (buffer & USB_DEVSEL); + } + else + { + if (USB_TRUE == g_usb_pipe_table[ptr->ip][pipe].use_flag) + { + result = (uint16_t) (g_usb_pipe_table[ptr->ip][pipe].pipe_maxp & USB_DEVSEL); + } + } + + return result; +} + +/****************************************************************************** + * End of function usb_hstd_get_device_address + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_write_data + * Description : Switch PIPE, request the USB FIFO to write data, and manage + * : the size of written data. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe no. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : uint16_t end_flag + ******************************************************************************/ +uint16_t usb_hstd_write_data (usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode) +{ + uint16_t size; + uint16_t count; + uint16_t buffer; + uint16_t mxps; + uint16_t end_flag; + uint16_t read_pid; + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("### usb_hstd_write_data PipeNo ERROR pipenum:%d\n", pipe); + + return USB_WRITESHRT; /* Error */ + } + + /* Changes FIFO port by the pipe. */ + if ((USB_CUSE == pipemode) && (USB_PIPE0 == pipe)) + { + buffer = usb_cstd_is_set_frdy(ptr, pipe, (uint16_t) USB_CUSE, (uint16_t) USB_ISEL); + } + else + { + buffer = usb_cstd_is_set_frdy(ptr, pipe, pipemode, USB_FALSE); + } + + /* Check error */ + if (USB_FIFOERROR == buffer) + { + + /* FIFO access error */ + return USB_FIFOERROR; + } + + /* Data buffer size */ + size = usb_cstd_get_buf_size(ptr, pipe); + + /* Max Packet Size */ + mxps = usb_cstd_get_maxpacket_size(ptr, pipe); + + /* Data size check */ + if (g_usb_hstd_data_cnt[ptr->ip][pipe] <= (uint32_t) size) + { + count = (uint16_t) g_usb_hstd_data_cnt[ptr->ip][pipe]; + + /* Data count check */ + if (0 == count) + { + /* Null Packet is end of write */ + end_flag = USB_WRITESHRT; + } + else if (0 != (count % mxps)) + { + /* Short Packet is end of write */ + end_flag = USB_WRITESHRT; + } + else + { + if (USB_PIPE0 == pipe) + { + /* Just Send Size */ + end_flag = USB_WRITING; + } + else + { + /* Write continues */ + end_flag = USB_WRITEEND; + } + } + } + else + { + /* Write continues */ + end_flag = USB_WRITING; + count = size; + } + + read_pid = usb_cstd_get_pid(ptr, pipe); + usb_cstd_set_nak(ptr, pipe); + + gp_usb_hstd_data_ptr[ptr->ip][pipe] = + usb_hstd_write_fifo(ptr, count, pipemode, gp_usb_hstd_data_ptr[ptr->ip][pipe]); + + /* Check data count to remain */ + if (g_usb_hstd_data_cnt[ptr->ip][pipe] < (uint32_t) size) + { + /* Clear data count */ + g_usb_hstd_data_cnt[ptr->ip][pipe] = (uint32_t) 0U; + buffer = hw_usb_read_fifoctr(ptr, pipemode); /* Read CFIFOCTR */ + + /* Check BVAL */ + if (0U == (buffer & USB_BVAL)) + { + /* Short Packet */ + hw_usb_set_bval(ptr, pipemode); + } + } + else + { + /* Total data count - count */ + g_usb_hstd_data_cnt[ptr->ip][pipe] -= count; + } + + hw_usb_clear_status_bemp(ptr, pipe); + + /* USB_PID_BUF ? */ + if (USB_PID_BUF == (USB_PID & read_pid)) + { + usb_cstd_set_buf(ptr, pipe); + } + + /* End or Err or Continue */ + return end_flag; +} + +/****************************************************************************** + * End of function usb_hstd_write_data + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_receive_start + * Description : Start data reception using CPU/DMA transfer to USB Host/USB + * : device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe no. + * Return value : none + ******************************************************************************/ +void usb_hstd_receive_start (usb_utr_t * ptr, uint16_t pipe) +{ + usb_utr_t * pp; + uint32_t length; + uint16_t mxps; + uint16_t useport; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint8_t dma_ch; + dmac_extended_cfg_t * channel_info; + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Evacuation pointer */ + pp = g_p_usb_hstd_pipe[ptr->ip][pipe]; + length = pp->tranlen; + + /* Check transfer count */ + if (USB_TRAN_CONT == pp->segment) + { + /* Sequence toggle */ + usb_hstd_do_sqtgl(ptr, pipe, pp->pipectr); + } + + /* Select NAK */ + usb_cstd_set_nak(ptr, pipe); + g_usb_hstd_data_cnt[ptr->ip][pipe] = length; /* Set data count */ + gp_usb_hstd_data_ptr[ptr->ip][pipe] = (uint8_t *) pp->p_tranadr; /* Set data pointer */ + + /* Ignore count clear */ + g_usb_hstd_ignore_cnt[ptr->ip][pipe] = (uint16_t) 0U; + + /* Pipe number to FIFO port select */ + useport = usb_hstd_pipe2fport(ptr, pipe); + + /* Check use FIFO access */ + switch (useport) + { + /* CFIFO use */ + case USB_CUSE: + { + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(ptr, pipe, useport, USB_FALSE); + mxps = usb_cstd_get_maxpacket_size(ptr, pipe); /* Max Packet Size */ + if ((uint32_t) 0U != length) + { + /* Data length check */ + if ((uint32_t) 0U == (length % mxps)) + { + /* Set Transaction counter */ + usb_cstd_set_transaction_counter(ptr, pipe, (uint16_t) (length / mxps)); + } + else + { + /* Set Transaction counter */ + usb_cstd_set_transaction_counter(ptr, pipe, (uint16_t) ((length / mxps) + (uint32_t) 1U)); + } + } + + usb_cstd_set_buf(ptr, pipe); /* Set BUF */ + + /* Enable Ready Interrupt */ + hw_usb_set_brdyenb(ptr, pipe); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(ptr, pipe); + break; + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* D1FIFO DMA */ + case USB_D1USE: + + /* D0FIFO DMA */ + case USB_D0USE: + { + if (USB_IP0 == ptr->ip) + { + channel_info = (dmac_extended_cfg_t *) pp->p_transfer_rx->p_cfg->p_extend; + dma_ch = channel_info->channel; + } + else + { + channel_info = (dmac_extended_cfg_t *) pp->p_transfer_rx->p_cfg->p_extend; + dma_ch = channel_info->channel; + } + + /* Setting for use PIPE number */ + g_usb_cstd_dma_pipe[ptr->ip][dma_ch] = pipe; + + /* Buffer size */ + g_usb_cstd_dma_fifo[ptr->ip][dma_ch] = usb_cstd_get_buf_size(ptr, pipe); + + /* Transfer data size */ + g_usb_cstd_dma_size[ptr->ip][dma_ch] = g_usb_hstd_data_cnt[ptr->ip][pipe]; + usb_cstd_dma_rcv_start(ptr, pipe, useport); + + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + default: + { + USB_PRINTF1("### USB-ITRON is not support(RCV-else:pipe%d)\n", pipe); + usb_hstd_forced_termination(ptr, pipe, (uint16_t) USB_DATA_ERR); + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_receive_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_read_data + * Description : Request to read data from USB FIFO, and manage the size of + * : the data read. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe no. + * : uint16_t pipemode : Pipe mode (CFIFO/D0FIFO/D1FIFO) + * Return value : USB_READING / USB_READEND / USB_READSHRT / USB_READOVER + ******************************************************************************/ +uint16_t usb_hstd_read_data (usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode) +{ + uint16_t count; + uint16_t buffer; + uint16_t mxps; + uint16_t dtln; + uint16_t end_flag; + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("*** usb_hstd_read_data PipeNo ERROR %d\n", pipe); + + return USB_ERROR; /* Error */ + } + + /* Changes FIFO port by the pipe. */ + buffer = usb_cstd_is_set_frdy(ptr, pipe, pipemode, USB_FALSE); + if (USB_FIFOERROR == buffer) + { + + /* FIFO access error */ + return USB_FIFOERROR; + } + + dtln = (uint16_t) (buffer & USB_DTLN); + + /* Max Packet Size */ + mxps = usb_cstd_get_maxpacket_size(ptr, pipe); + + if (g_usb_hstd_data_cnt[ptr->ip][pipe] < dtln) + { + /* Buffer Over ? */ + end_flag = USB_READOVER; + usb_cstd_set_nak(ptr, pipe); /* Set NAK */ + count = (uint16_t) g_usb_hstd_data_cnt[ptr->ip][pipe]; + #if BSP_CFG_RTOS != 1 + g_usb_hstd_data_cnt[ptr->ip][pipe] = dtln; + #endif /* BSP_CFG_RTOS != 1 */ + } + else if (g_usb_hstd_data_cnt[ptr->ip][pipe] == dtln) + { + /* Just Receive Size */ + count = dtln; + end_flag = USB_READEND; + usb_cstd_set_nak(ptr, pipe); /* Set NAK */ + } + else + { + /* Continues Receive data */ + count = dtln; + end_flag = USB_READING; + if ((0 == count) || (0 != (count % mxps))) + { + /* Null Packet receive */ + end_flag = USB_READSHRT; + usb_cstd_set_nak(ptr, pipe); /* Select NAK */ + } + } + + if (0 == dtln) + { + /* 0 length packet */ + /* Clear BVAL */ + hw_usb_set_bclr(ptr, pipemode); + } + else + { + gp_usb_hstd_data_ptr[ptr->ip][pipe] = + usb_hstd_read_fifo(ptr, count, pipemode, gp_usb_hstd_data_ptr[ptr->ip][pipe]); + } + + g_usb_hstd_data_cnt[ptr->ip][pipe] -= count; + + /* End or Err or Continue */ + return end_flag; +} + +/****************************************************************************** + * End of function usb_hstd_read_data + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_data_end + * Description : Set USB registers as appropriate after data transmission/re- + * : ception, and call the callback function as transmission/recep- + * : tion is complete. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe no. + * : uint16_t status : Transfer status type. + * Return value : none + ******************************************************************************/ +void usb_hstd_data_end (usb_utr_t * ptr, uint16_t pipe, uint16_t status) +{ + uint16_t useport; + uint8_t ip; + + #if (BSP_CFG_RTOS == 0 || BSP_CFG_RTOS == 2) && defined(USB_CFG_HAUD_USE) + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t dma_ch; + #endif + #endif /* (BSP_CFG_RTOS == 0 || BSP_CFG_RTOS == 2) && defined(USB_CFG_HAUD_USE) */ + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + ip = ptr->ip; + + /* PID = NAK */ + /* Set NAK */ + usb_cstd_set_nak(ptr, pipe); + + /* Pipe number to FIFO port select */ + useport = usb_hstd_pipe2fport(ptr, pipe); + + /* Disable Interrupt */ + /* Disable Ready Interrupt */ + hw_usb_clear_brdyenb(ptr, pipe); + + /* Disable Not Ready Interrupt */ + hw_usb_clear_nrdyenb(ptr, pipe); + + /* Disable Empty Interrupt */ + hw_usb_clear_bempenb(ptr, pipe); + + /* Disable Transaction count */ + usb_cstd_clr_transaction_counter(ptr, pipe); + + /* Check use FIFO */ + switch (useport) + { + /* CFIFO use */ + case USB_CUSE: + { + break; + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* D0FIFO DMA */ + case USB_D0USE: + { + /* DMA buffer clear mode clear */ + hw_usb_clear_dclrm(ptr, USB_D0USE); + if (USB_IP0 == ip) + { + hw_usb_set_mbw(ptr, USB_D0USE, USB0_D0FIFO_MBW); + } + else if (USB_IP1 == ip) + { + hw_usb_set_mbw(ptr, USB_D0USE, USB1_D0FIFO_MBW); + } + else + { + /* None */ + } + + break; + } + + /* D1FIFO DMA */ + case USB_D1USE: + { + /* DMA buffer clear mode clear */ + hw_usb_clear_dclrm(ptr, USB_D1USE); + if (USB_IP0 == ip) + { + hw_usb_set_mbw(ptr, USB_D1USE, USB0_D1FIFO_MBW); + } + else if (USB_IP1 == ip) + { + hw_usb_set_mbw(ptr, USB_D1USE, USB1_D1FIFO_MBW); + } + else + { + /* None */ + } + + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + default: + { + break; + } + } + + #if (BSP_CFG_RTOS == 0 || BSP_CFG_RTOS == 2) && defined(USB_CFG_HAUD_USE) + if ((pipe == g_usb_haud_iso_in_pipe[ip]) && + (0 != g_usb_hstd_data_cnt[ip][pipe])) /* 0 Byte Data Received */ + { + g_p_usb_hstd_pipe[ip][pipe]->tranlen = g_usb_hstd_data_cnt[ip][pipe]; + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + dma_ch = usb_cstd_dma_ref_ch_no(ptr, useport); + g_p_usb_hstd_pipe[ip][pipe]->p_tranadr = gp_usb_hstd_data_ptr[ptr->ip][pipe] + g_usb_cstd_dma_size[ip][dma_ch]; + #else + g_p_usb_hstd_pipe[ip][pipe]->p_tranadr = gp_usb_hstd_data_ptr[ptr->ip][pipe]; + #endif + usb_hstd_receive_start(ptr, pipe); + + return; + } + #endif /* (BSP_CFG_RTOS == 0 || BSP_CFG_RTOS == 2) && defined(USB_CFG_HAUD_USE) */ + + /* Call Back */ + if (USB_NULL != g_p_usb_hstd_pipe[ip][pipe]) + { + /* Transfer information set */ + g_p_usb_hstd_pipe[ip][pipe]->tranlen = g_usb_hstd_data_cnt[ip][pipe]; + g_p_usb_hstd_pipe[ip][pipe]->status = status; + g_p_usb_hstd_pipe[ip][pipe]->pipectr = hw_usb_read_pipectr(ptr, pipe); + g_p_usb_hstd_pipe[ip][pipe]->errcnt = (uint8_t) g_usb_hstd_ignore_cnt[ip][pipe]; + g_p_usb_hstd_pipe[ip][pipe]->ipp = usb_hstd_get_usb_ip_adr(ip); + g_p_usb_hstd_pipe[ip][pipe]->ip = ip; + (g_p_usb_hstd_pipe[ip][pipe]->complete)(g_p_usb_hstd_pipe[ip][pipe], USB_NULL, USB_NULL); + + #if (BSP_CFG_RTOS == 0) + g_p_usb_hstd_pipe[ip][pipe] = (usb_utr_t *) USB_NULL; + #else /* (BSP_CFG_RTOS == 0) */ + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_hstd_pipe[ip][pipe]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_hstd_pipe[ip][pipe]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + g_p_usb_hstd_pipe[ip][pipe] = (usb_utr_t *) USB_NULL; + usb_cstd_pipe_msg_re_forward(ip, pipe); /* Get PIPE Transfer wait que and Message send to HCD */ + #endif /* (BSP_CFG_RTOS == 0) */ + } +} + +/****************************************************************************** + * End of function usb_hstd_data_end + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_brdy_pipe_process + * Description : Search for the PIPE No. that BRDY interrupt occurred, and + * : request data transmission/reception from the PIPE + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t bitsts : BRDYSTS Register & BRDYENB Register + * Return value : none + ******************************************************************************/ +void usb_hstd_brdy_pipe_process (usb_utr_t * ptr, uint16_t bitsts) +{ + uint16_t useport; + uint16_t i; + uint16_t ip; + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t buffer; + uint16_t maxps; + uint16_t set_dma_block_cnt; + uint16_t trans_dma_block_cnt; + uint16_t dma_ch; + uint16_t status; + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + ip = ptr->ip; + + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i <= USB_MAX_PIPE_NO; i++) + { + if (0 != (bitsts & USB_BITSET(i))) + { + /* Interrupt check */ + hw_usb_clear_status_bemp(ptr, i); + + if (USB_NULL != g_p_usb_hstd_pipe[ip][i]) + { + /* Pipe number to FIFO port select */ + useport = usb_hstd_pipe2fport(ptr, i); + if ((USB_D0USE == useport) || (USB_D1USE == useport)) + { + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + dma_ch = usb_cstd_dma_ref_ch_no(ptr, useport); + + maxps = g_usb_cstd_dma_fifo[ip][dma_ch]; + + /* DMA Transfer request disable */ + hw_usb_clear_dreqe(ptr, useport); + + /* DMA stop */ + usb_cstd_dma_stop(ptr, useport); + + /* Changes FIFO port by the pipe. */ + buffer = usb_cstd_is_set_frdy(ptr, i, useport, USB_FALSE); + + set_dma_block_cnt = (uint16_t) (((g_usb_hstd_data_cnt[ip][g_usb_cstd_dma_pipe[ip][dma_ch]] - 1) / + g_usb_cstd_dma_fifo[ip][dma_ch]) + 1); + + trans_dma_block_cnt = usb_cstd_dma_get_crtb(ptr); + + /* Get D0fifo Receive Data Length */ + g_usb_cstd_dma_size[ip][dma_ch] = buffer & USB_DTLN; + if (set_dma_block_cnt > trans_dma_block_cnt) + { + if (0 != g_usb_cstd_dma_size[ip][dma_ch]) + { + g_usb_cstd_dma_size[ip][dma_ch] = + (uint16_t) ((uint16_t) (g_usb_cstd_dma_size[ip][dma_ch]) + + (uint16_t) ((set_dma_block_cnt - (trans_dma_block_cnt + 1)) * maxps)); + } + else + { + g_usb_cstd_dma_size[ip][dma_ch] = + (uint16_t) ((set_dma_block_cnt - (trans_dma_block_cnt)) * maxps); + } + } + + /* Check data count */ + if (g_usb_cstd_dma_size[ip][dma_ch] == g_usb_hstd_data_cnt[ptr->ip][i]) + { + status = USB_DATA_OK; + } + else if (g_usb_cstd_dma_size[ip][dma_ch] > g_usb_hstd_data_cnt[ip][i]) + { + status = USB_DATA_OVR; + } + else + { + status = USB_DATA_SHT; + } + + /* D0FIFO access DMA stop */ + usb_cstd_dfifo_end(ptr, useport); + + /* End of data transfer */ + usb_hstd_data_end(ptr, i, status); + + /* Set BCLR */ + hw_usb_set_bclr(ptr, useport); + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + } + else + { + if (USB_BUF2FIFO == usb_cstd_get_pipe_dir(ptr, i)) + { + /* Buffer to FIFO data write */ + usb_hstd_buf_to_fifo(ptr, i, useport); + } + else + { + /* FIFO to Buffer data read */ + usb_hstd_fifo_to_buf(ptr, i, useport); + } + } + } + } + } +} /* End of function usb_hstd_brdy_pipe_process() */ + +/****************************************************************************** + * Function Name : usb_hstd_nrdy_pipe_process + * Description : Search for PIPE No. that occurred NRDY interrupt, and execute + * : the process for PIPE when NRDY interrupt occurred + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t bitsts : NRDYSTS Register & NRDYENB Register + * Return value : none + ******************************************************************************/ +void usb_hstd_nrdy_pipe_process (usb_utr_t * ptr, uint16_t bitsts) +{ + uint16_t buffer; + uint16_t i; + + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i <= USB_MAX_PIPE_NO; i++) + { + if (0 != (bitsts & USB_BITSET(i))) + { + /* Interrupt check */ + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][i]) + { + if (USB_TYPFIELD_ISO == usb_cstd_get_pipe_type(ptr, i)) + { + /* Wait for About 60ns */ + buffer = hw_usb_read_frmnum(ptr); + if (USB_OVRN == (buffer & USB_OVRN)) + { + /* @1 */ + /* End of data transfer */ + usb_hstd_forced_termination(ptr, i, (uint16_t) USB_DATA_OVR); + USB_PRINTF1("###ISO OVRN %lu\n", (unsigned long) g_usb_hstd_data_cnt[ptr->ip][i]); + } + else + { + /* @2 */ + /* End of data transfer */ + usb_hstd_forced_termination(ptr, i, (uint16_t) USB_DATA_ERR); + } + } + else + { + usb_hstd_nrdy_endprocess(ptr, i); + } + } + } + } +} + +/****************************************************************************** + * End of function usb_hstd_nrdy_pipe_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_bemp_pipe_process + * Description : Search for PIPE No. that BEMP interrupt occurred, and complete data transmission for the PIPE + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t bitsts : BEMPSTS Register & BEMPENB Register + * Return value : none + ******************************************************************************/ +void usb_hstd_bemp_pipe_process (usb_utr_t * ptr, uint16_t bitsts) +{ + uint16_t buffer; + uint16_t i; + uint16_t useport; + + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i <= USB_PIPE5; i++) + { + if (0 != (bitsts & USB_BITSET(i))) + { + /* Interrupt check */ + if ((USB_NULL != g_p_usb_hstd_pipe[ptr->ip][i]) && (USB_ON != g_usb_cstd_bemp_skip[ptr->ip][i])) + { + buffer = usb_cstd_get_pid(ptr, i); + + /* MAX packet size error ? */ + if (USB_PID_STALL == (buffer & USB_PID_STALL)) + { + USB_PRINTF1("### STALL Pipe %d\n", i); + usb_hstd_forced_termination(ptr, i, (uint16_t) USB_DATA_STALL); + } + else + { + if (USB_INBUFM != (hw_usb_read_pipectr(ptr, i) & USB_INBUFM)) + { + /* Pipe number to FIFO port select */ + useport = usb_hstd_pipe2fport(ptr, i); + + if (USB_CUSE != useport) + { + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + hw_usb_clear_status_bemp(ptr, i); + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + } + + g_usb_cstd_bemp_skip[ptr->ip][i] = USB_ON; + + /* End of data transfer */ + usb_hstd_data_end(ptr, i, (uint16_t) USB_DATA_NONE); + } + } + } + } + } + + /* WAIT_LOOP */ + for (i = USB_PIPE6; i <= USB_MAX_PIPE_NO; i++) + { + /* Interrupt check */ + if (0 != (bitsts & USB_BITSET(i))) + { + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][i]) + { + buffer = usb_cstd_get_pid(ptr, i); + + /* MAX packet size error ? */ + if (USB_PID_STALL == (buffer & USB_PID_STALL)) + { + /*USB_PRINTF1("### STALL Pipe %d\n", i);*/ + usb_hstd_forced_termination(ptr, i, (uint16_t) USB_DATA_STALL); + } + else + { + /* End of data transfer */ + usb_hstd_data_end(ptr, i, (uint16_t) USB_DATA_NONE); + } + } + } + } +} + +/****************************************************************************** + * End of function usb_hstd_bemp_pipe_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_make_pipe_reg_info + * Description : Make value for USB PIPE registers set value. + * Arguments : uint16_t ip_no : USB Module no.(USB_IP0/USB_IP1) + * : uint16_t address : USB Device address + * : usb_class_t usb_class : USB Device class(USB_HVND/USB_HCDC/USB_HHID/USB_HMSC/USB_HUB) + * : uint16_t speed : USB speed + * : uint8_t *descriptor : Address for End Point Descriptor + * : usb_pipe_table_reg_t *pipe_table_work : Address for Store PIPE reg set value. + * Return value : Pipe no (USB_PIPE1->USB_PIPE9:OK, USB_NULL:Error) + ******************************************************************************/ +uint8_t usb_hstd_make_pipe_reg_info (uint16_t ip_no, + uint16_t address, + uint16_t usb_class, + uint16_t speed, + uint8_t * descriptor, + usb_pipe_table_reg_t * pipe_table_work) +{ + uint8_t pipe_no; + uint16_t pipe_cfg; + uint16_t pipe_maxp; + uint16_t pipe_peri = USB_NULL; + #if defined(USB_HIGH_SPEED_MODULE) + uint16_t pipe_buf; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + /* Check Endpoint descriptor */ + if (USB_DT_ENDPOINT != descriptor[USB_DEV_B_DESCRIPTOR_TYPE]) + { + return USB_NULL; /* Error */ + } + + /* set pipe configuration value */ + switch ((uint16_t) (descriptor[USB_EP_B_ATTRIBUTES] & USB_EP_TRNSMASK)) + { + /* Bulk Endpoint */ + case USB_EP_BULK: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(receive) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_BULK | USB_CFG_DBLB | USB_SHTNAKFIELD | USB_DIR_H_IN); + pipe_no = usb_hstd_get_pipe_no(ip_no, address, usb_class, USB_EP_BULK, USB_PIPE_DIR_IN); + } + else + { + /* OUT(send) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_BULK | USB_CFG_DBLB | USB_DIR_H_OUT); + pipe_no = usb_hstd_get_pipe_no(ip_no, address, usb_class, USB_EP_BULK, USB_PIPE_DIR_OUT); + } + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ip_no) + { + pipe_cfg |= (uint16_t) (USB_CFG_CNTMD); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + /* Interrupt Endpoint */ + case USB_EP_INT: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(receive) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_INT | USB_DIR_H_IN); + pipe_no = usb_hstd_get_pipe_no(ip_no, address, usb_class, USB_EP_INT, USB_PIPE_DIR_IN); + } + else + { + /* OUT(send) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_INT | USB_DIR_H_OUT); + pipe_no = usb_hstd_get_pipe_no(ip_no, address, usb_class, USB_EP_INT, USB_PIPE_DIR_OUT); + } + + /* Get value for Interval Error Detection Interval */ + pipe_peri = usb_hstd_get_pipe_peri_value(speed, descriptor[USB_EP_B_INTERVAL]); + + break; + } + + case USB_EP_ISO: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(receive) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_ISO | USB_CFG_DBLB | USB_SHTNAKFIELD | USB_DIR_H_IN); + pipe_no = usb_hstd_get_pipe_no(ip_no, address, usb_class, USB_EP_ISO, USB_PIPE_DIR_IN); + } + else + { + /* OUT(send) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_ISO | USB_CFG_DBLB | USB_DIR_H_OUT); + pipe_no = usb_hstd_get_pipe_no(ip_no, address, usb_class, USB_EP_ISO, USB_PIPE_DIR_OUT); + } + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ip_no) + { + pipe_cfg |= (uint16_t) (USB_CFG_CNTMD); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + /* Get value for Interval Error Detection Interval */ + pipe_peri = usb_hstd_get_pipe_peri_value(speed, descriptor[USB_EP_B_INTERVAL]); + + break; + } + + default: + { + return USB_NULL; /* Error */ + break; + } + } + + /* Check Pipe no. */ + if (USB_NULL != pipe_no) + { + /* Endpoint number set */ + pipe_cfg = (uint16_t) (pipe_cfg | (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_NUMMASK)); + + /* set max packet size */ + pipe_maxp = (uint16_t) ((uint16_t) descriptor[USB_EP_B_MAXPACKETSIZE_L] | (address << USB_DEVADDRBIT)); + pipe_maxp = (uint16_t) (pipe_maxp | ((uint16_t) descriptor[USB_EP_B_MAXPACKETSIZE_H] << 8)); + + /* Store PIPE reg set value. */ + pipe_table_work->pipe_cfg = pipe_cfg; + pipe_table_work->pipe_maxp = pipe_maxp; + pipe_table_work->pipe_peri = pipe_peri; + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ip_no) + { + /* PIPEBUF is USBA module only */ + pipe_buf = usb_hstd_get_pipe_buf_value(pipe_no); + pipe_table_work->pipe_buf = pipe_buf; + } + #endif /* #if defined (USB_HIGH_SPEED_MODULE) */ + } + + return pipe_no; +} /* eof usb_hstd_make_pipe_reg_info() */ + +/****************************************************************************** + * Function Name : usb_hstd_clr_pipe_table + * Description : Clear pipe table. + * Arguments : uint16_t ip_no : USB Module no.(USB_IP0/USB_IP1) + * : uint16_t device_address : USB Device address + * Return value : none + ******************************************************************************/ +void usb_hstd_clr_pipe_table (uint16_t ip_no, uint16_t device_address) +{ + uint8_t pipe_no; + + /* Search use pipe block */ + /* WAIT_LOOP */ + for (pipe_no = USB_MIN_PIPE_NO; pipe_no < (USB_MAX_PIPE_NO + 1); pipe_no++) + { + /* Check use block */ + if (USB_TRUE == g_usb_pipe_table[ip_no][pipe_no].use_flag) + { + /* Check USB Device address */ + if ((device_address << USB_DEVADDRBIT) == + (uint16_t) (g_usb_pipe_table[ip_no][pipe_no].pipe_maxp & USB_DEVSEL)) + { + /* Clear use block */ + g_usb_pipe_table[ip_no][pipe_no].use_flag = USB_FALSE; + g_usb_pipe_table[ip_no][pipe_no].pipe_cfg = USB_NULL; + g_usb_pipe_table[ip_no][pipe_no].pipe_maxp = USB_NULL; + g_usb_pipe_table[ip_no][pipe_no].pipe_peri = USB_NULL; + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ip_no) + { + /* PIPEBUF is USBA module only */ + g_usb_pipe_table[ip_no][pipe_no].pipe_buf = USB_NULL; + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #if BSP_CFG_RTOS == 1 + tx_semaphore_put(&g_usb_host_usbx_sem[ip_no][pipe_no]); + tx_semaphore_delete(&g_usb_host_usbx_sem[ip_no][pipe_no]); + #endif + } + } + } +} /* eof usb_hstd_clr_pipe_table() */ + +/****************************************************************************** + * Function Name : usb_hstd_set_pipe_reg + * Description : Set up USB registers to use specified pipe (Pipe unit). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe_no : USB Pipe No. + * Return value : none + ******************************************************************************/ +void usb_hstd_set_pipe_reg (usb_utr_t * ptr, uint16_t pipe_no) +{ + uint16_t buf; + + /* Check use block */ + if (USB_TRUE == g_usb_pipe_table[ptr->ip][pipe_no].use_flag) + { + /* Current FIFO port Clear */ + buf = hw_usb_read_fifosel(ptr, USB_CUSE); + if ((buf & USB_CURPIPE) == pipe_no) + { + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, USB_FALSE); + } + + buf = hw_usb_read_fifosel(ptr, USB_D0USE); + if ((buf & USB_CURPIPE) == pipe_no) + { + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_D0USE, USB_FALSE); + } + + buf = hw_usb_read_fifosel(ptr, USB_D1USE); + if ((buf & USB_CURPIPE) == pipe_no) + { + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_D1USE, USB_FALSE); + } + + /* PIPE Setting */ + usb_cstd_pipe_init(ptr, pipe_no); + } +} /* eof usb_hstd_set_pipe_reg() */ + +/****************************************************************************** + * Function Name : usb_hstd_get_pipe_no + * Description : Get PIPE No. + * Arguments : uint16_t ip_no : USB Module no.(USB_IP0/USB_IP1) + * : uint16_t address : USB Device address + * : uint16_t class : USB Device class(USB_HVND/USB_HCDC/USB_HHID/USB_HMSC/USB_HUB) + * : uint8_t type : Transfer Type.(USB_EP_BULK/USB_EP_INT) + * : uint8_t dir : (USB_PIPE_DIR_IN/USB_PIPE_DIR_OUT) + * Return value : Pipe no (USB_PIPE1->USB_PIPE9:OK, USB_NULL:Error) + ******************************************************************************/ +uint8_t usb_hstd_get_pipe_no (uint16_t ip_no, uint16_t address, uint16_t usb_class, uint8_t type, uint8_t dir) +{ + uint8_t pipe = USB_NULL; + uint8_t idx = USB_NULL; + #if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HMSC_USE) + uint16_t side; + #endif /* defined(USB_CFG_HMSC_USE) */ + #endif /* #if (BSP_CFG_RTOS != 1) */ + + switch (usb_class) + { + case USB_CLASS_INTERNAL_HVND: + { + #if defined(USB_CFG_HVND_USE) + if (USB_EP_BULK == type) + { + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) + { + + /* Check Free pipe */ + return pipe; /* Set Free pipe */ + } + } + } + + if (USB_EP_INT == type) + { + /* Interrupt PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_INT_PIPE_START; pipe < (USB_INT_PIPE_END + 1); pipe++) + { + if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) + { + + /* Check Free pipe */ + return pipe; /* Set Free pipe */ + } + } + } + #endif /* defined(USB_CFG_HVND_USE) */ + break; + } + + case USB_CLASS_INTERNAL_HCDC: + { + #if defined(USB_CFG_HCDC_USE) + if (USB_EP_BULK == type) + { + #if (BSP_CFG_RTOS == 1) + if (USB_PIPE_DIR_IN == dir) + { + if (USB_NULL != (g_usb_hcdc_bulk_in_pipe[ip_no])) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_hcdc_bulk_in_pipe[ip_no]; + } + } + + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + if (USB_NULL != (g_usb_hcdc2_bulk_in_pipe[ip_no])) + { + /* Hub downport device2 */ + if (USB_ADDRESS3 == address) + { + return g_usb_hcdc2_bulk_in_pipe[ip_no]; + } + } + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + } + else + { + if (USB_NULL != (g_usb_hcdc_bulk_out_pipe[ip_no])) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_hcdc_bulk_out_pipe[ip_no]; + } + } + + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + if (USB_NULL != (g_usb_hcdc2_bulk_out_pipe[ip_no])) + { + /* Hub downport device2 */ + if (USB_ADDRESS3 == address) + { + return g_usb_hcdc2_bulk_out_pipe[ip_no]; + } + } + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + } + #endif + + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_hcdc_bulk_in_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hcdc_bulk_in_pipe[ip_no]; + break; + } + + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + + /* Hub downport device2 */ + else if (USB_ADDRESS3 == address) + { + g_usb_hcdc2_bulk_in_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hcdc2_bulk_in_pipe[ip_no]; + break; + } + else + { + /* Do nothing. */ + } + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + } + else + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_hcdc_bulk_out_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hcdc_bulk_out_pipe[ip_no]; + break; + } + + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + + /* Hub downport device2 */ + else if (USB_ADDRESS3 == address) + { + g_usb_hcdc2_bulk_out_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hcdc2_bulk_out_pipe[ip_no]; + break; + } + else + { + /* Do nothing. */ + } + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + } + } + } + } + + if (USB_EP_INT == type) + { + if (USB_PIPE_DIR_IN == dir) + { + #if (BSP_CFG_RTOS == 1) + if (USB_NULL != g_usb_hcdc_int_in_pipe[ip_no]) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_hcdc_int_in_pipe[ip_no]; + } + } + + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + if (USB_NULL != g_usb_hcdc2_int_in_pipe[ip_no]) + { + /* Hub downport device2 */ + if (USB_ADDRESS3 == address) + { + return g_usb_hcdc2_int_in_pipe[ip_no]; + } + } + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + #endif + usb_class = USB_CLASS_INTERNAL_HCDCC; + + /* Interrupt PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_INT_PIPE_START; pipe < (USB_INT_PIPE_END + 1); pipe++) + { + if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_hcdc_int_in_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hcdc_int_in_pipe[ip_no]; + break; + } + + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + + /* Hub downport device2 */ + else if (USB_ADDRESS3 == address) + { + g_usb_hcdc2_int_in_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hcdc2_int_in_pipe[ip_no]; + break; + } + else + { + /* Do nothing. */ + } + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + } + } + } + } + #endif /* defined(USB_CFG_HCDC_USE) */ + break; + } + + case USB_CLASS_INTERNAL_HHID: + { + #if defined(USB_CFG_HHID_USE) + if (USB_EP_INT == type) + { + if (USB_PIPE_DIR_IN == dir) + { + if (USB_NULL != (g_usb_hhid_int_in_pipe[ip_no])) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_hhid_int_in_pipe[ip_no]; + } + } + + #if (USB_CFG_HHID_MULTI == USB_CFG_ENABLE) + if (USB_NULL != (g_usb_hhid2_int_in_pipe[ip_no])) + { + /* Hub downport device2 */ + if (USB_ADDRESS3 == address) + { + return g_usb_hhid2_int_in_pipe[ip_no]; + } + } + + if (USB_NULL != (g_usb_hhid3_int_in_pipe[ip_no])) + { + if (USB_ADDRESS4 == address) + { + return g_usb_hhid3_int_in_pipe[ip_no]; + } + } + #endif /* (USB_CFG_HHID_MULTI == USB_CFG_ENABLE) */ + } + else + { + if (USB_NULL != (g_usb_hhid_int_out_pipe[ip_no])) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_hhid_int_out_pipe[ip_no]; + } + } + } + + /* Interrupt PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_INT_PIPE_START; pipe < (USB_INT_PIPE_END + 1); pipe++) + { + if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_hhid_int_in_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hhid_int_in_pipe[ip_no]; + break; + } + + #if (USB_CFG_HHID_MULTI == USB_CFG_ENABLE) + + /* Hub downport device2 */ + else if (USB_ADDRESS3 == address) + { + g_usb_hhid2_int_in_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hhid2_int_in_pipe[ip_no]; + break; + } + else if (USB_ADDRESS4 == address) + { + g_usb_hhid3_int_in_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hhid3_int_in_pipe[ip_no]; + break; + } + else + { + /* Do nothing. */ + } + #endif /* (USB_CFG_HHID_MULTI == USB_CFG_ENABLE) */ + } + else + { + /* Check root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_hhid_int_out_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_hhid_int_out_pipe[ip_no]; + break; + } + } + } + } + } + #endif /* defined(USB_CFG_HHID_USE) */ + break; + } + + case USB_CLASS_INTERNAL_HMSC: + { + #if defined(USB_CFG_HMSC_USE) + if (USB_EP_BULK == type) + { + #if (BSP_CFG_RTOS != 1) + + /* Add USB IP no. for USB Device address */ + if (USB_IP1 == ip_no) + { + address |= USBA_ADDRESS_OFFSET; + } + + /* Get Strage drive no. */ + side = usb_hmsc_ref_drvno(address); + + /* Check Strage drive no. */ + if (side < USB_MAXSTRAGE) + { + #if defined(USB_CFG_HCDC_USE) + if ((USB_PIPE2 >= g_usb_hcdc_bulk_in_pipe[ip_no]) && + (USB_PIPE2 >= g_usb_hcdc_bulk_out_pipe[ip_no]) && + ((USB_PIPE3 + side) <= USB_PIPE5)) + { + pipe = (uint8_t) (USB_PIPE3 + side); + } + else + #endif /* defined(USB_CFG_HCDC_USE) */ + { + pipe = (uint8_t) (USB_PIPE1 + side); + } + } + + #else /* #if (BSP_CFG_RTOS != 1) */ + pipe = USB_PIPE1; + #endif /* #if (BSP_CFG_RTOS != 1) */ + } + #endif /* defined(USB_CFG_HMSC_USE) */ + break; + } + + case USB_CLASS_INTERNAL_HPRN: + { + #if defined(USB_CFG_HPRN_USE) + if (USB_EP_BULK == type) + { + #if (BSP_CFG_RTOS == 1) + if (USB_PIPE_DIR_IN == dir) + { + if (USB_NULL != (g_usb_hprn_bulk_in_pipe[ip_no])) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_hprn_bulk_in_pipe[ip_no]; + } + } + + #if (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) + if (USB_NULL != (g_usb_hprn2_bulk_in_pipe[ip_no])) + { + /* Hub downport device2 */ + if (USB_ADDRESS3 == address) + { + return g_usb_hprn2_bulk_in_pipe[ip_no]; + } + } + #endif /* (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) */ + } + else + { + if (USB_NULL != (g_usb_hprn_bulk_out_pipe[ip_no])) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_hprn_bulk_out_pipe[ip_no]; + } + } + + #if (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) + if (USB_NULL != (g_usb_hprn2_bulk_out_pipe[ip_no])) + { + /* Hub downport device2 */ + if (USB_ADDRESS3 == address) + { + return g_usb_hprn2_bulk_out_pipe[ip_no]; + } + } + #endif /* (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) */ + } + #endif + + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_hprn_bulk_in_pipe[ip_no] = pipe; + break; + } + + #if (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) + + /* Hub downport device2 */ + else if (USB_ADDRESS3 == address) + { + g_usb_hprn2_bulk_in_pipe[ip_no] = pipe; + break; + } + else + { + /* Do nothing. */ + } + #endif /* (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) */ + } + else + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_hprn_bulk_out_pipe[ip_no] = pipe; + break; + } + + #if (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) + + /* Hub downport device2 */ + else if (USB_ADDRESS3 == address) + { + g_usb_hprn2_bulk_out_pipe[ip_no] = pipe; + break; + } + else + { + /* Do nothing. */ + } + #endif /* (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) */ + } + } + } + } + #endif /* defined(USB_CFG_HPRN_USE) */ + break; + } + + case USB_CLASS_INTERNAL_HUVC: + { + #if defined(USB_CFG_HUVC_USE) + if (USB_EP_ISO == type) + { + #if (BSP_CFG_RTOS == 1) + if (USB_PIPE_DIR_IN == dir) + { + if (USB_NULL != g_usb_huvc_iso_in_pipe[ip_no]) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_huvc_iso_in_pipe[ip_no]; + } + } + } + else + { + if (USB_NULL != g_usb_huvc_iso_out_pipe[ip_no]) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_huvc_iso_out_pipe[ip_no]; + } + } + } + #endif /* (BSP_CFG_RTOS == 1) */ + + /* Isochronous PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_ISO_PIPE_START; pipe < (USB_ISO_PIPE_END + 1); pipe++) + { + /* Check if the pipe is free */ + if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_huvc_iso_in_pipe[ip_no] = pipe; + break; + } + } + else + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_huvc_iso_out_pipe[ip_no] = pipe; + break; + } + } + } + } + } + #endif /* defined(USB_CFG_HUVC_USE) */ + break; + } + + case USB_CLASS_INTERNAL_HAUD: + { + #if defined(USB_CFG_HAUD_USE) + if (USB_EP_ISO == type) + { + #if (BSP_CFG_RTOS == 1) + if (USB_PIPE_DIR_IN == dir) + { + if (USB_NULL != g_usb_haud_iso_in_pipe[ip_no]) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_haud_iso_in_pipe[ip_no]; + } + } + } + else + { + if (USB_NULL != g_usb_haud_iso_out_pipe[ip_no]) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + return g_usb_haud_iso_out_pipe[ip_no]; + } + } + } + #endif + + /* Isochronous PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_ISO_PIPE_START; pipe < (USB_ISO_PIPE_END + 1); pipe++) + { + /* Check if the pipe is free */ + if (USB_FALSE == g_usb_pipe_table[ip_no][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_haud_iso_in_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_haud_iso_in_pipe[ip_no]; + + break; + } + } + else + { + /* Root port device1 or Hub downport device1 */ + if ((USB_ADDRESS1 == address) || (USB_ADDRESS2 == address)) + { + g_usb_haud_iso_out_pipe[ip_no] = pipe; + + /* Store the used pipe for a specific USB class based on the usb_class_internal_t enum. */ + idx = (uint8_t) (((((usb_class_internal_t) usb_class - USB_CLASS_INTERNAL_HCDC) * 8) + + ((address - 1) * 2)) + dir); + g_usb_pipe_host[idx] = g_usb_haud_iso_out_pipe[ip_no]; + + break; + } + } + } + } + } + #endif /* defined(USB_CFG_HAUD_USE) */ + break; + } + + case USB_HUB: + { + pipe = USB_HUB_PIPE; + break; + } + + default: + { + (void) ip_no; + (void) address; + (void) type; + (void) dir; + (void) idx; + + return USB_NULL; + break; + } + } + + return pipe; +} /* eof usb_hstd_get_pipe_no() */ + +/****************************************************************************** + * Function Name : usb_hstd_get_pipe_peri_value + * Description : Get value to be set in PIPEPERI + * Arguments : uint16_t speed : USB speed + * : uint8_t binterval : bInterval for ENDPOINT Descriptor. + * Return value : Value for set PIPEPERI + ******************************************************************************/ +uint16_t usb_hstd_get_pipe_peri_value (uint16_t speed, uint8_t binterval) +{ + uint16_t pipe_peri = USB_NULL; + uint16_t work1; + uint16_t work2; + + /* set interval counter */ + if (0 != binterval) + { + /* FS/LS interrupt */ + if (USB_HSCONNECT != speed) + { + /* The time of the FS/LS interrupt forwarding of the interval is specified by the unit of ms. */ + /* It is necessary to calculate to specify USB-IP by the n-th power of two. */ + /* The NAK rate of the control and the bulk transfer doesn't correspond. */ + work1 = binterval; + work2 = 0; + for ( ; work1 != 0; work2++) + { + work1 = (uint16_t) (work1 >> 1); + } + + if (0 != work2) + { + /* Interval time */ + pipe_peri |= (uint16_t) (work2 - 1); + } + } + else + { + /* Hi-Speed */ + if (8 >= binterval) + { + /* Interval time */ + pipe_peri = (uint16_t) (binterval - 1U); + } + else + { + /* Max Interval time */ + pipe_peri = (uint16_t) (USB_IITVFIELD); + } + } + } + + return pipe_peri; +} /* eof usb_hstd_get_pipe_peri_value() */ + + #if defined(USB_HIGH_SPEED_MODULE) + +/****************************************************************************** + * Function Name : usb_hstd_get_pipe_buf_value + * Description : Get Value for USBA Module PIPE BUF REG. + * Arguments : Pipe no. + * Return value : PIPE BUF set value. + ******************************************************************************/ +uint16_t usb_hstd_get_pipe_buf_value (uint16_t pipe_no) +{ + (void) pipe_no; + uint16_t pipe_buf = 0; + + #if defined(USB_CFG_HCDC_USE) + if (pipe_no == g_usb_hcdc_bulk_in_pipe[USB_IP1]) + { + #if (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(8U)); + #else /* (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + #endif /* (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + } + else if (pipe_no == g_usb_hcdc_bulk_out_pipe[USB_IP1]) + { + #if (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(40U)); + #else /* (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(72U)); + #endif /* (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + } + + #if (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) + else if (pipe_no == g_usb_hcdc2_bulk_in_pipe[USB_IP1]) + { + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(72U)); + } + else if (pipe_no == g_usb_hcdc2_bulk_out_pipe[USB_IP1]) + { + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(104U)); + } + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + else + { + /*Do nothing.*/ + } + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HMSC_USE) + #if (defined(USB_CFG_HCDC_USE) && (USB_CFG_MULTIPORT == USB_CFG_DISABLE)) + if ((pipe_no != g_usb_hcdc_bulk_in_pipe[USB_IP1]) && (pipe_no != g_usb_hcdc_bulk_out_pipe[USB_IP1])) + { + #if USB_CFG_DTC == USB_CFG_ENABLE + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(8U)); + #else /* USB_CFG_DTC == USB_CFG_ENABLE */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + } + + #else /* defined(USB_CFG_HCDC_USE) */ + switch (pipe_no) + { + case USB_PIPE1: + { + #if (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HMSC_MULTI == USB_CFG_ENABLE) + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(8U)); + #else /* USB_CFG_DTC == USB_CFG_ENABLE || USB_CFG_HMSC_MULTI == USB_CFG_ENABLE */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + #endif /* USB_CFG_DTC == USB_CFG_ENABLE || USB_CFG_HMSC_MULTI == USB_CFG_ENABLE */ + break; + } + + case USB_PIPE2: + { + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(40U)); + break; + } + + case USB_PIPE3: + { + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(72U)); + break; + } + + case USB_PIPE4: + { + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(104U)); + break; + } + } + #endif /* defined(USB_CFG_HCDC_USE) */ + #endif /* defined(USB_CFG_HMSC_USE) */ + + #if defined(USB_CFG_HVND_USE) + switch (pipe_no) + { + case USB_PIPE1: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(8U)); + break; + } + + case USB_PIPE2: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(24U)); + break; + } + + case USB_PIPE3: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(40U)); + break; + } + + case USB_PIPE4: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(56U)); + break; + } + + case USB_PIPE5: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(72U)); + break; + } + } + #endif /* defined(USB_CFG_HVND_USE) */ + + #if defined(USB_CFG_HPRN_USE) + if (pipe_no == g_usb_hprn_bulk_in_pipe[USB_IP1]) + { + #if (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(8U)); + #else /* (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + #endif /* (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) */ + } + else if (pipe_no == g_usb_hprn_bulk_out_pipe[USB_IP1]) + { + #if (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(40U)); + #else /* (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(72U)); + #endif /* (USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) */ + } + + #if (USB_CFG_HPRN_MULTI == USB_CFG_ENABLE) + else if (pipe_no == g_usb_hprn2_bulk_in_pipe[USB_IP1]) + { + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(72U)); + } + else if (pipe_no == g_usb_hprn2_bulk_out_pipe[USB_IP1]) + { + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(104U)); + } + #endif /* (USB_CFG_HCDC_MULTI == USB_CFG_ENABLE) */ + else + { + /* Do nothing. */ + } + #endif /* defined(USB_CFG_HPRN_USE) */ + + #if defined(USB_CFG_HUVC_USE) + if (pipe_no == g_usb_huvc_iso_in_pipe[USB_IP1]) + { + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + } + else if (pipe_no == g_usb_huvc_iso_out_pipe[USB_IP1]) + { + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(72U)); + } + else + { + /* Do nothing. */ + } + #endif /* defined(USB_CFG_HUVC_USE) */ + + #if defined(USB_CFG_HAUD_USE) + if (pipe_no == g_usb_haud_iso_in_pipe[USB_IP1]) + { + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + } + else if (pipe_no == g_usb_haud_iso_out_pipe[USB_IP1]) + { + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(72U)); + } + else + { + /* Do nothing. */ + } + #endif /* defined(USB_CFG_HAUD_USE) */ + + return pipe_buf; +} /* End of function usb_hstd_get_pipe_buf_value() */ + + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hmanager.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hmanager.c new file mode 100644 index 0000000000..5e5f64cc58 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hmanager.c @@ -0,0 +1,3387 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include +#include +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS == 1) + #include "ux_api.h" + #include "ux_host_stack.h" +#endif /* #if (BSP_CFG_RTOS == 1) */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/******************************************************************************* + * Macro definitions + ******************************************************************************/ + + #define USB_PET_VID (0x1a0a) /* USB-PET Vendor ID */ + #define USB_PET_PID (0x0200) /* USB-PET Product ID (Use Embedded Host Test) */ + #define USB_VALUE_FFH (0xFF) + #define USB_VALUE_40H (0x40) + #define USB_VALUE_100 (100) + #define USB_VALUE_3000 (3000) + #if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_HHID_USE) + #define USB_HID_SET_PROTOCOL (0x0B00) + #define BOOT_PROTCOL (0) + #endif /* #if defined(USB_CFG_HHID_USE) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ +static uint16_t usb_shstd_std_request[USB_NUM_USBIP][5]; +static usb_utr_t usb_shstd_std_req_msg[USB_NUM_USBIP]; + +/* Condition compilation by the difference of the operating system */ + #if (BSP_CFG_RTOS == 0) +static uint16_t usb_shstd_reg_pointer[USB_NUM_USBIP]; + #endif /* (BSP_CFG_RTOS == 0) */ +static usb_mgrinfo_t * p_usb_shstd_mgr_msg[USB_NUM_USBIP]; +static uint16_t usb_shstd_mgr_msginfo[USB_NUM_USBIP]; +static usb_cb_t usb_shstd_mgr_callback[USB_NUM_USBIP]; + #if (BSP_CFG_RTOS == 0) +static uint16_t usb_shstd_suspend_seq[USB_NUM_USBIP]; +static uint16_t usb_shstd_resume_seq[USB_NUM_USBIP]; +static void usb_hstd_susp_cont(usb_utr_t * ptr, uint16_t devaddr); +static void usb_hstd_resu_cont(usb_utr_t * ptr, uint16_t devaddr); + + #endif /* (BSP_CFG_RTOS == 0) */ + +static void usb_hstd_enumeration_err(uint16_t Rnum); + + #if (BSP_CFG_RTOS != 0) +static uint16_t usb_hstd_cmd_submit(usb_utr_t * ptr); + + #else /* (BSP_CFG_RTOS != 0) */ +static uint16_t usb_hstd_cmd_submit(usb_utr_t * ptr, usb_cb_t complete); + + #endif /* (BSP_CFG_RTOS != 0) */ + +static uint16_t usb_hstd_chk_remote(usb_utr_t * ptr); + +static void usb_hstd_mgr_rel_mpl(usb_utr_t * ptr, uint16_t n); + + #if (BSP_CFG_RTOS == 2) + #if defined(USB_CFG_HCDC_ECM_USE) +extern uint16_t * usb_hcdc_get_vendor_table(void); +extern uint16_t usb_hcdc_ecm_pre_check_config(uint8_t * table, uint16_t length); +extern uint16_t usb_hcdc_ecm_check_config(uint8_t * table, uint16_t length); + +extern uint16_t g_usb_hcdc_speed[USB_NUM_USBIP]; +extern uint16_t g_usb_hcdc_devaddr[USB_NUM_USBIP]; +static uint8_t g_idx_configuration[USB_NUM_USBIP]; +static uint8_t g_num_configuration[USB_NUM_USBIP]; + #endif /* defined(USB_CFG_HCDC_ECM_USE) */ + #endif /* #if (BSP_CFG_RTOS == 2) */ + +/****************************************************************************** + * Exported global functions (to be accessed by other files) + ******************************************************************************/ +uint16_t usb_hstd_chk_device_class(usb_utr_t * ptr, usb_hcdreg_t * driver); + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + +/* Manager */ +uint16_t g_usb_hstd_enum_seq[USB_NUM_USBIP]; /* Enumeration request */ +uint16_t g_usb_hstd_device_descriptor[USB_NUM_USBIP][USB_DEVICESIZE / 2U]; +uint16_t g_usb_hstd_config_descriptor[USB_NUM_USBIP][USB_CONFIGSIZE / 2U]; +uint16_t g_usb_hstd_suspend_pipe[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; + +uint16_t g_usb_hstd_check_enu_result[USB_NUM_USBIP]; + +uint8_t g_usb_hstd_class_data[USB_NUM_USBIP][CLSDATASIZE]; +usb_utr_t g_usb_hstd_class_ctrl[USB_NUM_USBIP]; +uint16_t g_usb_hstd_class_request[USB_NUM_USBIP][5]; + + #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) + +/* Enumeration Table */ +void (* g_usb_hstd_enumaration_process[9])(usb_utr_t *, uint16_t, uint16_t) = +{ + usb_hstd_enum_get_descriptor, usb_hstd_enum_set_address, + usb_hstd_enum_get_descriptor, usb_hstd_enum_get_descriptor, + usb_hstd_enum_get_descriptor, usb_hstd_enum_get_descriptor, + usb_hstd_enum_set_configuration, usb_hid_set_protocol, + usb_hid_get_string_desc, +}; + #else /* #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) */ +/* Enumeration Table */ +void (* g_usb_hstd_enumaration_process[8])(usb_utr_t *, uint16_t, uint16_t) = +{ + usb_hstd_enum_get_descriptor, usb_hstd_enum_set_address, + usb_hstd_enum_get_descriptor, usb_hstd_enum_get_descriptor, + usb_hstd_enum_get_descriptor, usb_hstd_enum_get_descriptor, + usb_hstd_enum_set_configuration, usb_hstd_enum_dummy_request, +}; + #endif /* #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) */ + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE +uint16_t g_usb_disp_param_set[USB_NUM_USBIP]; +usb_compliance_t g_usb_disp_param[USB_NUM_USBIP]; +extern usb_compliance_cb_t * g_usb_compliance_callback[USB_NUM_USBIP]; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + #if (BSP_CFG_RTOS == 1) +extern UX_DEVICE * g_p_usbx_device[USB_NUM_USBIP]; +UX_CONFIGURATION * g_p_usbx_configuration[USB_NUM_USBIP]; + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Function Name : usb_hstd_mgr_rel_mpl + * Description : Release a memory block. + * Argument : uint16_t n : Error no. + * Return : none + ******************************************************************************/ +static void usb_hstd_mgr_rel_mpl (usb_utr_t * ptr, uint16_t n) +{ + usb_er_t err; + + (void) n; + err = USB_REL_BLK(USB_MGR_MPL, (usb_mh_t) p_usb_shstd_mgr_msg[ptr->ip]); + if (USB_OK != err) + { + USB_PRINTF1("### USB MGR rel_blk error: %d\n", n); + } +} + +/****************************************************************************** + * End of function usb_hstd_mgr_rel_mpl + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_mgr_chgdevst_cb + * Description : Call the callback function specified by the argument given to + * : the API usb_hstd_change_device_state. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +static void usb_hstd_mgr_chgdevst_cb (usb_utr_t * ptr) +{ + if (0 != usb_shstd_mgr_msginfo[ptr->ip]) + { + (*usb_shstd_mgr_callback[ptr->ip])(ptr, USB_NULL, usb_shstd_mgr_msginfo[ptr->ip]); + usb_shstd_mgr_msginfo[ptr->ip] = 0; + } +} + +/****************************************************************************** + * End of function usb_hstd_mgr_chgdevst_cb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_enumeration + * Description : Execute enumeration on the connected USB device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : uint16_t : Enumeration status. + ******************************************************************************/ + #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) +static uint16_t usb_hstd_enumeration (usb_utr_t * ptr) +{ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + uint16_t vendor_id; + uint16_t product_id; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + uint16_t md; + uint16_t flg; + usb_hcdreg_t * driver; + uint16_t enume_mode; /* Enumeration mode (device state) */ + uint8_t * descriptor_table; + uint16_t devsel; + + UX_CONFIGURATION * configuration; + UX_CONFIGURATION * list_configuration; + UX_DEVICE * device; + uint32_t usbx_status = UX_ERROR; + + /* Attach Detect Mode */ + enume_mode = USB_NONDEVICE; + + /* Manager Mode Change */ + switch (p_usb_shstd_mgr_msg[ptr->ip]->result) + { + case USB_DATA_STALL: + case USB_CTRL_END: + { + enume_mode = USB_DEVICEENUMERATION; + switch (g_usb_hstd_enum_seq[ptr->ip]) + { + /* Receive Device Descriptor */ + case 0: + { + break; + } + + /* Set Address */ + case 1: + { + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + devsel = (uint16_t) (g_usb_hstd_device_addr[ptr->ip] << USB_DEVADDRBIT); + + /* Set device speed */ + usb_hstd_set_dev_addr(ptr, devsel, g_usb_hstd_device_speed[ptr->ip]); + g_usb_hstd_dcp_register[ptr->ip][g_usb_hstd_device_addr[ptr->ip]] = + (uint16_t) ((uint16_t) (descriptor_table[7] & USB_MAXPFIELD) | devsel); + break; + } + + /* Receive Device Descriptor(18) */ + case 2: + { + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + _ux_utility_descriptor_parse(descriptor_table, + _ux_system_device_descriptor_structure, + UX_DEVICE_DESCRIPTOR_ENTRIES, + (uint8_t *) &g_p_usbx_device[ptr->ip]->ux_device_descriptor); + + break; + } + + /* Receive Configuration Descriptor(9) */ + case 3: + { + device = g_p_usbx_device[ptr->ip]; + configuration = + _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_CONFIGURATION)); + configuration->ux_configuration_device = device; + configuration->ux_configuration_handle = (uint32_t) (ALIGN_TYPE) configuration; + if (device->ux_device_first_configuration == UX_NULL) + { + device->ux_device_first_configuration = configuration; + } + else + { + list_configuration = device->ux_device_first_configuration; + while (list_configuration->ux_configuration_next_configuration != UX_NULL) + { + list_configuration = list_configuration->ux_configuration_next_configuration; + } + + list_configuration->ux_configuration_next_configuration = configuration; + } + + descriptor_table = (uint8_t *) g_usb_hstd_config_descriptor[ptr->ip]; + _ux_utility_descriptor_parse(descriptor_table, + _ux_system_configuration_descriptor_structure, + UX_CONFIGURATION_DESCRIPTOR_ENTRIES, + (uint8_t *) &configuration->ux_configuration_descriptor); + + g_p_usbx_configuration[ptr->ip] = configuration; + + break; + } + + /* Receive Configuration Descriptor(xx) */ + case 4: + { + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + + /* If 'vendor_id' and 'product_id' value is defined by PET, */ + /* system works for compliance test mode. */ + /* Values ??defined by PET is the following. */ + /* vendor_id : 0x1A0A */ + /* product_id : 0x0101 - 0x0108 , 0x0200 */ + + vendor_id = (uint16_t) (descriptor_table[USB_DEV_ID_VENDOR_L] + + ((uint16_t) descriptor_table[USB_DEV_ID_VENDOR_H] << 8)); + + if (0x1A0A == vendor_id) + { + product_id = (uint16_t) (descriptor_table[USB_DEV_ID_PRODUCT_L] + + ((uint16_t) descriptor_table[USB_DEV_ID_PRODUCT_H] << 8)); + + descriptor_table = (uint8_t *) g_usb_hstd_config_descriptor[ptr->ip]; + #if USB_CFG_ELECTRICAL == USB_CFG_ENABLE + if ((0x0100 < product_id) && (product_id < 0x0109)) + { + usb_hstd_electrical_test_mode(ptr, product_id); + enume_mode = USB_NOTTPL; + break; + } + #endif /* USB_CFG_ELECTRICAL == USB_CFG_ENABLE */ + + if (0x0200 == product_id) + { + g_usb_hstd_enum_seq[ptr->ip]++; + break; + } + } + #endif /* USB_CFG_ELECTRICAL == USB_CFG_ENABLE */ + + /* Driver open */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + g_usb_disp_param_set[ptr->ip] = USB_OFF; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + flg = 0U; + + /* WAIT_LOOP */ + for (md = 0; (md < g_usb_hstd_device_num[ptr->ip]) && (0U == flg); md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (USB_DETACHED == driver->devstate) + { + uint16_t retval; + retval = usb_hstd_chk_device_class(ptr, driver); + if (USB_OK == retval) + { + driver->devaddr = g_usb_hstd_device_addr[ptr->ip]; + flg = 1; /* break; */ + } + + usbx_status = _ux_host_stack_interfaces_scan(g_p_usbx_configuration[ptr->ip], + (uint8_t *) g_usb_hstd_config_descriptor[ptr-> + ip]); + } + } + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + if (USB_ON == g_usb_disp_param_set[ptr->ip]) + { + (*g_usb_compliance_callback[ptr->ip])((void *) &g_usb_disp_param[ptr->ip]); + } + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + break; + } + + /* Class Check Result */ + case 5: + case 6: + case 7: + case 8: + { + break; + } + + /* Set Configuration */ + case 9: + { + /* Device enumeration function */ + USB_PRINTF0(" Configured Device\n"); + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (g_usb_hstd_device_addr[ptr->ip] == driver->devaddr) + { + /* Device state */ + g_usb_hstd_device_info[ptr->ip][g_usb_hstd_device_addr[ptr->ip]][1] = USB_CONFIGURED; + + /* Device speed */ + g_usb_hstd_device_info[ptr->ip][g_usb_hstd_device_addr[ptr->ip]][4] = + g_usb_hstd_device_speed[ptr->ip]; + + /* Device state */ + driver->devstate = USB_CONFIGURED; + + /* Call Back */ + (*driver->devconfig)(ptr, g_usb_hstd_device_addr[ptr->ip], (uint16_t) USB_NO_ARG); + + return USB_COMPLETEPIPESET; + } + } + + enume_mode = USB_COMPLETEPIPESET; + break; + } + + default: + { + break; + } + } + + if (USB_COMPLETEPIPESET != enume_mode) + { + g_usb_hstd_enum_seq[ptr->ip]++; + } + + /* Device Enumeration */ + if (USB_DEVICEENUMERATION == enume_mode) + { + switch (g_usb_hstd_enum_seq[ptr->ip]) + { + case 1: + { + (*g_usb_hstd_enumaration_process[1])(ptr, (uint16_t) USB_DEVICE_0, + g_usb_hstd_device_addr[ptr->ip]); + break; + } + + case 5: + { + (*g_usb_hstd_enumaration_process[8])(ptr, g_usb_hstd_device_addr[ptr->ip], 0); + break; + } + + case 6: + { + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + + (*g_usb_hstd_enumaration_process[8])(ptr, g_usb_hstd_device_addr[ptr->ip], + descriptor_table[15]); + break; + } + + case 7: + { + (*g_usb_hstd_enumaration_process[5])(ptr, g_usb_hstd_device_addr[ptr->ip], + g_usb_hstd_enum_seq[ptr->ip]); + break; + } + + case 8: + { + usbx_status = _ux_host_stack_class_device_scan(g_p_usbx_device[ptr->ip]); + if (UX_SUCCESS != usbx_status) + { + if (usbx_status == UX_NO_CLASS_MATCH) + { + #if defined(USB_CFG_OTG_USE) + UX_HCD * p_hcd; + p_hcd = UX_DEVICE_HCD_GET(g_p_usbx_device[ptr->ip]); + p_hcd->ux_hcd_otg_capabilities |= UX_HCD_OTG_CAPABLE; + #endif /* defined (USB_CFG_OTG_USE) */ + + usbx_status = _ux_host_stack_class_interface_scan(g_p_usbx_device[ptr->ip]); + } + } + + if (USB_IFCLS_HUB == + g_p_usbx_device[ptr->ip]->ux_device_first_configuration->ux_configuration_first_interface-> + ux_interface_descriptor.bInterfaceClass) + { + g_usb_hstd_enum_seq[ptr->ip]++; + } + + break; + } + + case 9: + { + if (USB_IFCLS_HID == + g_p_usbx_device[ptr->ip]->ux_device_first_configuration->ux_configuration_first_interface-> + ux_interface_descriptor.bInterfaceClass) + { + (*g_usb_hstd_enumaration_process[7])(ptr, g_usb_hstd_device_addr[ptr->ip], BOOT_PROTCOL); + } + + break; + } + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + case 10: + { + enume_mode = USB_NOTTPL; + break; + } + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + default: + { + (*g_usb_hstd_enumaration_process[g_usb_hstd_enum_seq[ptr->ip]])(ptr, + g_usb_hstd_device_addr[ptr->ip], + g_usb_hstd_enum_seq[ptr->ip]); + break; + } + } + } + + break; + } + + case USB_DATA_ERR: + { + USB_PRINTF0("### Enumeration is stopped(SETUP or DATA-ERROR)\n"); + usb_hstd_enumeration_err(g_usb_hstd_enum_seq[ptr->ip]); + break; + } + + case USB_DATA_OVR: + { + USB_PRINTF0("### Enumeration is stopped(receive data over)\n"); + usb_hstd_enumeration_err(g_usb_hstd_enum_seq[ptr->ip]); + break; + } + + default: + { + USB_PRINTF0("### Enumeration is stopped(result error)\n"); + usb_hstd_enumeration_err(g_usb_hstd_enum_seq[ptr->ip]); + break; + } + } + + return enume_mode; +} + + #else /* #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) */ + +static uint16_t usb_hstd_enumeration (usb_utr_t * ptr) +{ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + uint16_t vendor_id; + uint16_t product_id; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + uint16_t md; + #if defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) + volatile uint16_t flg; + #else + uint16_t flg; + #endif /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + usb_hcdreg_t * driver; + uint16_t enume_mode; /* Enumeration mode (device state) */ + uint8_t * descriptor_table; + uint16_t devsel; + + #if (BSP_CFG_RTOS == 0) + usb_instance_ctrl_t ctrl; + #endif /* (BSP_CFG_RTOS == 0) */ + + #if (BSP_CFG_RTOS == 1) + UX_CONFIGURATION * configuration; + UX_CONFIGURATION * list_configuration; + UX_DEVICE * device; + uint32_t usbx_status = UX_ERROR; + #endif /* BSP_CFG_RTOS == 1 */ + + #if (defined(USB_CFG_HMSC_USE) && defined(USB_CFG_HCDC_USE) && (USB_CFG_MULTIPORT == USB_CFG_DISABLE)) + uint32_t composite_cdc_check = 0; + uint32_t composite_msc_check = 0; + #endif + + /* Attach Detect Mode */ + enume_mode = USB_NONDEVICE; + + /* Manager Mode Change */ + switch (p_usb_shstd_mgr_msg[ptr->ip]->result) + { + case USB_CTRL_END: + { + enume_mode = USB_DEVICEENUMERATION; + switch (g_usb_hstd_enum_seq[ptr->ip]) + { + /* Receive Device Descriptor */ + case 0: + { + break; + } + + /* Set Address */ + case 1: + { + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + devsel = (uint16_t) (g_usb_hstd_device_addr[ptr->ip] << USB_DEVADDRBIT); + + /* Set device speed */ + usb_hstd_set_dev_addr(ptr, devsel, g_usb_hstd_device_speed[ptr->ip]); + g_usb_hstd_dcp_register[ptr->ip][g_usb_hstd_device_addr[ptr->ip]] = + (uint16_t) ((uint16_t) (descriptor_table[7] & USB_MAXPFIELD) | devsel); + break; + } + + /* Receive Device Descriptor(18) */ + case 2: + { + #if (BSP_CFG_RTOS == 1) + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + _ux_utility_descriptor_parse(descriptor_table, + _ux_system_device_descriptor_structure, + UX_DEVICE_DESCRIPTOR_ENTRIES, + (uint8_t *) &g_p_usbx_device[ptr->ip]->ux_device_descriptor); + #endif /* BSP_CFG_RTOS == 1 */ + + #if defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + g_num_configuration[ptr->ip] = descriptor_table[USB_DEV_B_NUM_CONFIGURATION]; + #endif /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + break; + } + + /* Receive Configuration Descriptor(9) */ + case 3: + { + #if (BSP_CFG_RTOS == 1) + device = g_p_usbx_device[ptr->ip]; + configuration = + _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_CONFIGURATION)); + configuration->ux_configuration_device = device; + configuration->ux_configuration_handle = (uint32_t) (ALIGN_TYPE) configuration; + if (device->ux_device_first_configuration == UX_NULL) + { + device->ux_device_first_configuration = configuration; + } + else + { + list_configuration = device->ux_device_first_configuration; + while (list_configuration->ux_configuration_next_configuration != UX_NULL) + { + list_configuration = list_configuration->ux_configuration_next_configuration; + } + + list_configuration->ux_configuration_next_configuration = configuration; + } + + descriptor_table = (uint8_t *) g_usb_hstd_config_descriptor[ptr->ip]; + _ux_utility_descriptor_parse(descriptor_table, + _ux_system_configuration_descriptor_structure, + UX_CONFIGURATION_DESCRIPTOR_ENTRIES, + (uint8_t *) &configuration->ux_configuration_descriptor); + + g_p_usbx_configuration[ptr->ip] = configuration; + #endif /* BSP_CFG_RTOS == 1 */ + + break; + } + + /* Receive Configuration Descriptor(xx) */ + case 4: + { + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + + /* If 'vendor_id' and 'product_id' value is defined by PET, */ + /* system works for compliance test mode. */ + /* Values ??defined by PET is the following. */ + /* vendor_id : 0x1A0A */ + /* product_id : 0x0101 - 0x0108 , 0x0200 */ + + vendor_id = (uint16_t) (descriptor_table[USB_DEV_ID_VENDOR_L] + + ((uint16_t) descriptor_table[USB_DEV_ID_VENDOR_H] << 8)); + + if (0x1A0A == vendor_id) + { + product_id = (uint16_t) (descriptor_table[USB_DEV_ID_PRODUCT_L] + + ((uint16_t) descriptor_table[USB_DEV_ID_PRODUCT_H] << 8)); + + descriptor_table = (uint8_t *) g_usb_hstd_config_descriptor[ptr->ip]; + #if USB_CFG_ELECTRICAL == USB_CFG_ENABLE + if ((0x0100 < product_id) && (product_id < 0x0109)) + { + usb_hstd_electrical_test_mode(ptr, product_id); + enume_mode = USB_NOTTPL; + break; + } + #endif /* USB_CFG_ELECTRICAL == USB_CFG_ENABLE */ + + if (0x0200 == product_id) + { + g_usb_hstd_enum_seq[ptr->ip]++; + break; + } + } + #endif /* USB_CFG_ELECTRICAL == USB_CFG_ENABLE */ + + /* Driver open */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + g_usb_disp_param_set[ptr->ip] = USB_OFF; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + flg = 0U; + + /* WAIT_LOOP */ + for (md = 0; (md < g_usb_hstd_device_num[ptr->ip]) && (0U == flg); md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (USB_DETACHED == driver->devstate) + { + uint16_t retval; + retval = usb_hstd_chk_device_class(ptr, driver); + #if (BSP_CFG_RTOS != 0) + if (USB_OK == retval) + { + #if (defined(USB_CFG_HMSC_USE) && defined(USB_CFG_HCDC_USE) && (USB_CFG_MULTIPORT == USB_CFG_DISABLE)) + if (USB_IFCLS_CDC == driver->ifclass) + { + composite_cdc_check = 1; + } + + if (USB_IFCLS_MAS == driver->ifclass) + { + composite_msc_check = 1; + } + + driver->devaddr = g_usb_hstd_device_addr[ptr->ip]; + + if ((1 == composite_cdc_check) && (1 == composite_msc_check)) + { + flg = 1; /* break; */ + } + + #else + driver->devaddr = g_usb_hstd_device_addr[ptr->ip]; + flg = 1; /* break; */ + #endif + } + + #if (BSP_CFG_RTOS == 1) + usbx_status = _ux_host_stack_interfaces_scan(g_p_usbx_configuration[ptr->ip], + (uint8_t *) g_usb_hstd_config_descriptor[ptr-> + ip]); + #endif /* BSP_CFG_RTOS == 1 */ + #else /* (BSP_CFG_RTOS != 0) */ + g_usb_hstd_check_enu_result[ptr->ip] = USB_OK; + + /* In this function, check device class of */ + /* enumeration flow move to class */ + /* "usb_hstd_return_enu_mgr()" is used to return */ + if (USB_OK == retval) + { + usb_shstd_reg_pointer[ptr->ip] = md; + flg = 1; /* break; */ + #if defined(USB_CFG_HAUD_USE) + if (g_usb_hstd_device_drv[ptr->ip][md].ifclass == USB_IFCLS_AUD) + { + driver->devaddr = g_usb_hstd_device_addr[ptr->ip]; + g_usb_hstd_enum_seq[ptr->ip]++; + } + #endif /* defined(USB_CFG_HAUD_USE) */ + } + #endif /* (BSP_CFG_RTOS != 0) */ + } + } + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + if (USB_ON == g_usb_disp_param_set[ptr->ip]) + { + (*g_usb_compliance_callback[ptr->ip])((void *) &g_usb_disp_param[ptr->ip]); + } + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + #if (BSP_CFG_RTOS == 0) + if (1 != flg) + { + ctrl.device_address = (uint8_t) g_usb_hstd_device_addr[ptr->ip]; /* USB Device address */ + ctrl.module_number = ptr->ip; /* Module number setting */ + usb_set_event(USB_STATUS_NOT_SUPPORT, &ctrl); /* Set Event() */ + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + g_usb_hstd_enum_seq[ptr->ip] = g_usb_hstd_enum_seq[ptr->ip] + 2; + #else /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + g_usb_hstd_enum_seq[ptr->ip]++; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + } + #endif /* (BSP_CFG_RTOS == 0) */ + break; + } + + /* Class Check Result */ + case 5: + { + #if (BSP_CFG_RTOS == 0) + switch (g_usb_hstd_check_enu_result[ptr->ip]) + { + case USB_OK: + { + driver = &g_usb_hstd_device_drv[ptr->ip][usb_shstd_reg_pointer[ptr->ip]]; + + /* Root port */ + driver->devaddr = g_usb_hstd_device_addr[ptr->ip]; + break; + } + + case USB_ERROR: + { + USB_PRINTF0("*** usb_hstd_enumeration USB_NOTTPL !\n"); + enume_mode = USB_NOTTPL; + break; + } + + default: + { + enume_mode = USB_NONDEVICE; + break; + } + } + #endif /* (BSP_CFG_RTOS == 0) */ + break; + } + + /* Set Configuration */ + case 6: + { + #if defined(USB_CFG_OTG_USE) + CHAR * p_name; + UINT state; + ULONG run_count; + UINT priority; + UINT threshold; + ULONG time_slice; + TX_THREAD * p_thread; + TX_THREAD * p_next_thread; + TX_THREAD * p_suspend_thread; + #endif /* defined(USB_CFG_OTG_USE) */ + + /* Device enumeration function */ + USB_PRINTF0(" Configured Device\n"); + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (g_usb_hstd_device_addr[ptr->ip] == driver->devaddr) + { + /* Device state */ + g_usb_hstd_device_info[ptr->ip][g_usb_hstd_device_addr[ptr->ip]][1] = USB_CONFIGURED; + + /* Device speed */ + g_usb_hstd_device_info[ptr->ip][g_usb_hstd_device_addr[ptr->ip]][4] = + g_usb_hstd_device_speed[ptr->ip]; + + /* Device state */ + driver->devstate = USB_CONFIGURED; + + /* Call Back */ + (*driver->devconfig)(ptr, g_usb_hstd_device_addr[ptr->ip], (uint16_t) USB_NO_ARG); + + #if defined(USB_CFG_OTG_USE) + p_thread = &_ux_system_host->ux_system_host_hnp_polling_thread; + tx_thread_info_get(p_thread, + &p_name, + &state, + &run_count, + &priority, + &threshold, + &time_slice, + &p_next_thread, + &p_suspend_thread); + + if (TX_SUSPENDED == state) + { + tx_thread_resume(p_thread); + } + #endif /* defined(USB_CFG_OTG_USE) */ + + #if (defined(USB_CFG_HMSC_USE) && defined(USB_CFG_HCDC_USE) && (USB_CFG_MULTIPORT == USB_CFG_DISABLE)) + if (USB_IFCLS_CDC == driver->ifclass) + { + composite_cdc_check = 1; + } + + if (USB_IFCLS_MAS == driver->ifclass) + { + composite_msc_check = 1; + } + + if ((1 == composite_cdc_check) && (1 == composite_msc_check)) + { + return USB_COMPLETEPIPESET; + } + + #else + + return USB_COMPLETEPIPESET; + #endif + } + } + + enume_mode = USB_COMPLETEPIPESET; + break; + } + + default: + { + break; + } + } + + if (USB_COMPLETEPIPESET != enume_mode) + { + #if defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) + if (4 == g_usb_hstd_enum_seq[ptr->ip]) + { + if (1 == flg) + { + g_usb_hstd_enum_seq[ptr->ip]++; + } + else + { + g_idx_configuration[ptr->ip]++; + if (g_idx_configuration[ptr->ip] < g_num_configuration[ptr->ip]) + { + g_usb_hstd_enum_seq[ptr->ip]--; + } + else + { + g_usb_hstd_enum_seq[ptr->ip]++; + } + } + } + else + { + g_usb_hstd_enum_seq[ptr->ip]++; + } + + #else /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + g_usb_hstd_enum_seq[ptr->ip]++; + #endif /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + } + + /* Device Enumeration */ + if (USB_DEVICEENUMERATION == enume_mode) + { + switch (g_usb_hstd_enum_seq[ptr->ip]) + { + case 1: + { + (*g_usb_hstd_enumaration_process[1])(ptr, (uint16_t) USB_DEVICE_0, + g_usb_hstd_device_addr[ptr->ip]); + break; + } + + case 5: + { + #if (BSP_CFG_RTOS != 0) + (*g_usb_hstd_enumaration_process[5])(ptr, g_usb_hstd_device_addr[ptr->ip], + g_usb_hstd_enum_seq[ptr->ip]); + #endif /* (BSP_CFG_RTOS != 0) */ + break; + } + + case 6: + { + #if (BSP_CFG_RTOS == 1) + usbx_status = _ux_host_stack_class_device_scan(g_p_usbx_device[ptr->ip]); + if (UX_SUCCESS != usbx_status) + { + if (usbx_status == UX_NO_CLASS_MATCH) + { + #if defined(USB_CFG_OTG_USE) + UX_HCD * p_hcd; + p_hcd = UX_DEVICE_HCD_GET(g_p_usbx_device[ptr->ip]); + p_hcd->ux_hcd_otg_capabilities |= UX_HCD_OTG_CAPABLE; + #endif /* defined (USB_CFG_OTG_USE) */ + usbx_status = _ux_host_stack_class_interface_scan(g_p_usbx_device[ptr->ip]); + } + } + + #else /* (BSP_CFG_RTOS == 1) */ + descriptor_table = (uint8_t *) g_usb_hstd_config_descriptor[ptr->ip]; + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][g_usb_hstd_device_addr[ptr->ip]][2] = descriptor_table[5]; + + (*g_usb_hstd_enumaration_process[6])(ptr, g_usb_hstd_device_addr[ptr->ip], + (uint16_t) (descriptor_table[5])); + #endif /* (BSP_CFG_RTOS == 1) */ + break; + } + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + case 7: + { + enume_mode = USB_NOTTPL; + break; + } + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + default: + { + (*g_usb_hstd_enumaration_process[g_usb_hstd_enum_seq[ptr->ip]])(ptr, + g_usb_hstd_device_addr[ptr->ip], + g_usb_hstd_enum_seq[ptr->ip]); + break; + } + } + } + + break; + } + + case USB_DATA_ERR: + { + USB_PRINTF0("### Enumeration is stopped(SETUP or DATA-ERROR)\n"); + usb_hstd_enumeration_err(g_usb_hstd_enum_seq[ptr->ip]); + break; + } + + case USB_DATA_OVR: + { + USB_PRINTF0("### Enumeration is stopped(receive data over)\n"); + usb_hstd_enumeration_err(g_usb_hstd_enum_seq[ptr->ip]); + break; + } + + case USB_DATA_STALL: + { + USB_PRINTF0("### Enumeration is stopped(SETUP or DATA-STALL)\n"); + usb_hstd_enumeration_err(g_usb_hstd_enum_seq[ptr->ip]); + break; + } + + default: + { + USB_PRINTF0("### Enumeration is stopped(result error)\n"); + usb_hstd_enumeration_err(g_usb_hstd_enum_seq[ptr->ip]); + break; + } + } + + return enume_mode; +} + + #endif /* #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) */ + +/****************************************************************************** + * End of function usb_hstd_enumeration + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_enumeration_err + * Description : Output error information when enumeration error occurred. + * Argument : uint16_t Rnum : enumeration sequence + * Return : none + ******************************************************************************/ +static void usb_hstd_enumeration_err (uint16_t Rnum) +{ + (void) Rnum; + + /* Condition compilation by the difference of useful function */ + #if defined(USB_DEBUG_ON) + switch (Rnum) + { + case 0: + { + USB_PRINTF0(" Get_DeviceDescrip(8)\n"); + break; + } + + case 1: + { + USB_PRINTF0(" Set_Address\n"); + break; + } + + case 2: + { + USB_PRINTF0(" Get_DeviceDescrip(18)\n"); + break; + } + + case 3: + { + USB_PRINTF0(" Get_ConfigDescrip(9)\n"); + break; + } + + case 4: + { + USB_PRINTF0(" Get_ConfigDescrip(xx)\n"); + break; + } + + case 5: + { + USB_PRINTF0(" Get_DeviceDescrip(8-2)\n"); + break; /* Device enumeration function */ + } + + case 6: + { + USB_PRINTF0(" Set_Configuration\n"); + break; + } + + default: + {} + break; + } + #endif /* defined(USB_DEBUG_ON) */ +} + +/****************************************************************************** + * End of function usb_hstd_enumeration_err + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_chk_device_class + * Description : Interface class search + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : usb_hcdreg_t *driver : Class driver + * Return : uint16_t : USB_OK / USB_ERROR + ******************************************************************************/ +uint16_t usb_hstd_chk_device_class (usb_utr_t * ptr, usb_hcdreg_t * driver) +{ + uint8_t * descriptor_table; + uint16_t total_length1; + uint16_t total_length2; + uint16_t result = USB_ERROR; + uint16_t hub_device; + uint16_t * table[9]; + uint16_t tmp4; + uint16_t tmp5; + uint16_t tmp6; + uint16_t vendor_id; + uint16_t product_id; + uint16_t id_check; + uint16_t i; + #if defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) + uint16_t * vendor_table; + uint16_t result2 = USB_ERROR; + #endif /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + + descriptor_table = (uint8_t *) g_usb_hstd_device_descriptor[ptr->ip]; + + /* Device class check */ + tmp4 = descriptor_table[USB_DEV_B_DEVICE_CLASS]; + tmp5 = descriptor_table[USB_DEV_B_DEVICE_SUBCLASS]; + tmp6 = descriptor_table[USB_DEV_B_DEVICE_PROTOCOL]; + hub_device = USB_OK; + if (((USB_VALUE_FFH == tmp4) && (USB_VALUE_FFH == tmp5)) && (USB_VALUE_FFH == tmp6)) + { + USB_PRINTF0("*** Vendor specific device.\n\n"); + } + else if (((USB_IFCLS_HUB == tmp4) && (0X00 == tmp5)) && (0X00 == tmp6)) + { + USB_PRINTF0("*** Full-Speed HUB device.\n\n"); + hub_device = USB_FSHUB; + } + else if (((USB_IFCLS_HUB == tmp4) && (0x00 == tmp5)) && (0x01 == tmp6)) + { + USB_PRINTF0("*** High-Speed single TT device.\n\n"); + hub_device = USB_HSHUBS; + } + else if (((USB_IFCLS_HUB == tmp4) && (0x00 == tmp5)) && (0x02 == tmp6)) + { + USB_PRINTF0("*** High-Speed multiple TT device.\n\n"); + hub_device = USB_HSHUBM; + } + else if (((0 != tmp4) || (0 != tmp5)) || (0 != tmp6)) + { + USB_PRINTF0("### Device class information error!\n\n"); + } + else + { + /* Non */ + } + + vendor_id = (uint16_t) (descriptor_table[USB_DEV_ID_VENDOR_L] + + ((uint16_t) descriptor_table[USB_DEV_ID_VENDOR_H] << 8)); + product_id = (uint16_t) (descriptor_table[USB_DEV_ID_PRODUCT_L] + + ((uint16_t) descriptor_table[USB_DEV_ID_PRODUCT_H] << 8)); + + /* Check PET connect */ + if ((USB_PET_VID == vendor_id) && (USB_PET_PID == product_id)) + { + result = USB_OK; + } + else + { + #if defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) + if (USB_IFCLS_CDC == driver->ifclass) + { + vendor_table = usb_hcdc_get_vendor_table(); + + /* WAIT_LOOP */ + for (i = 0; i < vendor_table[0]; i++) + { + if ((vendor_table[(i * 2) + 2] == vendor_id) && (vendor_table[(i * 2) + 3] == product_id)) + { + result = USB_OK; + g_usb_hcdc_speed[ptr->ip] = g_usb_hstd_device_speed[ptr->ip]; + g_usb_hcdc_devaddr[ptr->ip] = g_usb_hstd_device_addr[ptr->ip]; + } + } + + if (USB_OK == result) + { + return result; + } + else + { + descriptor_table = (uint8_t *) g_usb_hstd_config_descriptor[ptr->ip]; + + result2 = usb_hcdc_ecm_pre_check_config(descriptor_table, + (uint16_t) (((uint16_t) descriptor_table[3] << 8) + + (uint16_t) descriptor_table[2])); + + if (USB_OK == result2) + { + /* Do nothing. (Device has normal CDC Class IF)*/ + } + else + { + result = usb_hcdc_ecm_check_config(descriptor_table, + (uint16_t) (((uint16_t) descriptor_table[3] << 8) + + (uint16_t) descriptor_table[2])); + if (USB_OK == result) + { + g_usb_hcdc_speed[ptr->ip] = g_usb_hstd_device_speed[ptr->ip]; + g_usb_hcdc_devaddr[ptr->ip] = g_usb_hstd_device_addr[ptr->ip]; + + return result; + } + else + { + return USB_ERROR; + } + } + } + } + #endif /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + id_check = USB_ERROR; + + /* WAIT_LOOP */ + for (i = 0; i < driver->p_tpl[0]; i++) + { + if ((USB_NOVENDOR == driver->p_tpl[(i * 2) + 2]) || (driver->p_tpl[(i * 2) + 2] == vendor_id)) + { + if ((USB_NOPRODUCT == driver->p_tpl[(i * 2) + 3]) || (driver->p_tpl[(i * 2) + 3] == product_id)) + { + id_check = USB_OK; + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + g_usb_disp_param[ptr->ip].status = USB_COMPLIANCETEST_TPL; + g_usb_disp_param[ptr->ip].pid = product_id; + g_usb_disp_param[ptr->ip].vid = vendor_id; + g_usb_disp_param_set[ptr->ip] = USB_ON; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + } + } + } + } + + if (USB_OK == result) + { + return result; + } + + if (USB_ERROR == id_check) + { + USB_PRINTF0("### Not support device\n"); + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + if (USB_IFCLS_HUB == descriptor_table[4]) + { + g_usb_disp_param[ptr->ip].status = USB_COMPLIANCETEST_HUB; + g_usb_disp_param[ptr->ip].pid = product_id; + g_usb_disp_param[ptr->ip].vid = vendor_id; + g_usb_disp_param_set[ptr->ip] = USB_ON; + } + else + { + g_usb_disp_param[ptr->ip].status = USB_COMPLIANCETEST_NOTTPL; + g_usb_disp_param[ptr->ip].pid = product_id; + g_usb_disp_param[ptr->ip].vid = vendor_id; + g_usb_disp_param_set[ptr->ip] = USB_ON; + } + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + return USB_ERROR; + } + + descriptor_table = (uint8_t *) g_usb_hstd_config_descriptor[ptr->ip]; + total_length1 = 0; + total_length2 = (uint16_t) (descriptor_table[USB_DEV_W_TOTAL_LENGTH_L] + + ((uint16_t) descriptor_table[USB_DEV_W_TOTAL_LENGTH_H] << 8)); + + if (total_length2 > USB_CONFIGSIZE) + { + total_length2 = USB_CONFIGSIZE; + } + + /* Search within configuration total-length */ + /* WAIT_LOOP */ + while (total_length1 < total_length2) + { + switch (descriptor_table[total_length1 + 1]) + { + /* Configuration Descriptor ? */ + case USB_DT_CONFIGURATION: + { + table[1] = (uint16_t *) &descriptor_table[total_length1]; + break; + } + + /* Interface Descriptor ? */ + case USB_DT_INTERFACE: + { + if ((uint16_t) descriptor_table[total_length1 + 5] == driver->ifclass) + { + result = USB_ERROR; + table[0] = (uint16_t *) &g_usb_hstd_device_descriptor[ptr->ip]; + table[2] = (uint16_t *) &descriptor_table[total_length1]; + table[3] = &result; + table[4] = &hub_device; + table[6] = &g_usb_hstd_device_speed[ptr->ip]; + table[7] = &g_usb_hstd_device_addr[ptr->ip]; + (*driver->classcheck)(ptr, (uint16_t **) &table); + + /* Interface Class */ + g_usb_hstd_device_info[ptr->ip][g_usb_hstd_device_addr[ptr->ip]][3] = + descriptor_table[total_length1 + + 5]; + + return result; + } + + /* USB_PRINTF2("*** Interface class is 0x%02x (not 0x%02x)\n", + * descriptor_table[total_length1 + 5], driver->ifclass);*/ + break; + } + + default: + { + break; + } + } + + total_length1 = (uint16_t) (total_length1 + descriptor_table[total_length1]); + if (0 == descriptor_table[total_length1]) + { + break; + } + } + + USB_PRINTF0("### usb_hstd_chk_device_class Not Find Interface Descriptor\n"); + + return USB_ERROR; +} + +/****************************************************************************** + * End of function usb_hstd_chk_device_class + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_notif_ator_detach + * Description : Notify MGR (manager) task that attach or detach occurred. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t result : Result. + * Return : none + ******************************************************************************/ +void usb_hstd_notif_ator_detach (usb_utr_t * ptr, uint16_t result) +{ + usb_hstd_mgr_snd_mbx(ptr, (uint16_t) USB_MSG_MGR_AORDETACH, USB_NULL, result); +} + +/****************************************************************************** + * End of function usb_hstd_notif_ator_detach + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_ovcr_notifiation + * Description : Notify MGR (manager) task that overcurrent was generated + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_ovcr_notifiation (usb_utr_t * ptr) +{ + usb_hstd_mgr_snd_mbx(ptr, (uint16_t) USB_MSG_MGR_OVERCURRENT, USB_NULL, (uint16_t) 0U); +} + +/****************************************************************************** + * End of function usb_hstd_ovcr_notifiation + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_status_result + * Description : This is a callback as a result of calling + * : usb_hstd_change_device_state. This notifies the MGR (manager) + * : task that the change of USB Device status completed. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data1 : No use. + * : uint16_t result : Result. + * Return : none + ******************************************************************************/ +void usb_hstd_status_result (usb_utr_t * ptr, uint16_t data1, uint16_t result) +{ + (void) data1; + usb_hstd_mgr_snd_mbx(ptr, (uint16_t) USB_MSG_MGR_STATUSRESULT, USB_NULL, result); +} + +/****************************************************************************** + * End of function usb_hstd_status_result + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_submit_result + * Description : Callback after completion of a standard request. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t data1 : Not used + * : uint16_t data2t : Not used + * Return : none + ******************************************************************************/ +void usb_hstd_submit_result (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + (void) data1; + (void) data2; + usb_hstd_mgr_snd_mbx(ptr, (uint16_t) USB_MSG_MGR_SUBMITRESULT, ptr->keyword, ptr->status); +} + +/****************************************************************************** + * End of function usb_hstd_submit_result + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_enum_get_descriptor + * Description : Send GetDescriptor to the connected USB device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : Device Address + * : uint16_t cnt_value : Enumeration sequence + * Return : none + ******************************************************************************/ +void usb_hstd_enum_get_descriptor (usb_utr_t * ptr, uint16_t addr, uint16_t cnt_value) +{ + uint8_t * data_table; + + switch (cnt_value) + { + case 0: + + /* continue */ + case 1: + + /* continue */ + #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) + case 7: + #else + case 5: + #endif + { + usb_shstd_std_request[ptr->ip][0] = USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE; + usb_shstd_std_request[ptr->ip][1] = (uint16_t) USB_DEV_DESCRIPTOR; + usb_shstd_std_request[ptr->ip][2] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][3] = (uint16_t) USB_VALUE_40H; + if (usb_shstd_std_request[ptr->ip][3] > USB_DEVICESIZE) + { + usb_shstd_std_request[ptr->ip][3] = USB_DEVICESIZE; + } + + usb_shstd_std_req_msg[ptr->ip].p_tranadr = g_usb_hstd_device_descriptor[ptr->ip]; + break; + } + + case 2: + { + usb_shstd_std_request[ptr->ip][0] = USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE; + usb_shstd_std_request[ptr->ip][1] = (uint16_t) USB_DEV_DESCRIPTOR; + usb_shstd_std_request[ptr->ip][2] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][3] = (uint16_t) 0x0012; + if (usb_shstd_std_request[ptr->ip][3] > USB_DEVICESIZE) + { + usb_shstd_std_request[ptr->ip][3] = USB_DEVICESIZE; + } + + usb_shstd_std_req_msg[ptr->ip].p_tranadr = g_usb_hstd_device_descriptor[ptr->ip]; + break; + } + + case 3: + { + usb_shstd_std_request[ptr->ip][0] = USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE; + #if defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) + usb_shstd_std_request[ptr->ip][1] = (uint16_t) USB_CONF_DESCRIPTOR | g_idx_configuration[ptr->ip]; + #else /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + usb_shstd_std_request[ptr->ip][1] = (uint16_t) USB_CONF_DESCRIPTOR; + #endif /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + usb_shstd_std_request[ptr->ip][2] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][3] = (uint16_t) 0x0009; + usb_shstd_std_req_msg[ptr->ip].p_tranadr = g_usb_hstd_config_descriptor[ptr->ip]; + break; + } + + case 4: + { + data_table = (uint8_t *) g_usb_hstd_config_descriptor[ptr->ip]; + usb_shstd_std_request[ptr->ip][0] = USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE; + #if defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) + usb_shstd_std_request[ptr->ip][1] = (uint16_t) USB_CONF_DESCRIPTOR | g_idx_configuration[ptr->ip]; + #else /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + usb_shstd_std_request[ptr->ip][1] = (uint16_t) USB_CONF_DESCRIPTOR; + #endif /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + usb_shstd_std_request[ptr->ip][2] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][3] = (uint16_t) (((uint16_t) data_table[3] << 8) + (uint16_t) data_table[2]); + if (usb_shstd_std_request[ptr->ip][3] > USB_CONFIGSIZE) + { + usb_shstd_std_request[ptr->ip][3] = USB_CONFIGSIZE; + USB_PRINTF0("***WARNING Descriptor size over !\n"); + } + + usb_shstd_std_req_msg[ptr->ip].p_tranadr = g_usb_hstd_config_descriptor[ptr->ip]; + break; + } + + default: + { + return; + break; + } + } + + usb_shstd_std_request[ptr->ip][4] = addr; + usb_shstd_std_req_msg[ptr->ip].keyword = (uint16_t) USB_PIPE0; + usb_shstd_std_req_msg[ptr->ip].tranlen = (uint32_t) usb_shstd_std_request[ptr->ip][3]; + usb_shstd_std_req_msg[ptr->ip].p_setup = usb_shstd_std_request[ptr->ip]; + usb_shstd_std_req_msg[ptr->ip].status = USB_DATA_NONE; + usb_shstd_std_req_msg[ptr->ip].complete = (usb_cb_t) &usb_hstd_submit_result; + usb_shstd_std_req_msg[ptr->ip].segment = USB_TRAN_END; + + usb_shstd_std_req_msg[ptr->ip].ipp = ptr->ipp; + usb_shstd_std_req_msg[ptr->ip].ip = ptr->ip; + usb_shstd_std_req_msg[ptr->ip].p_transfer_rx = ptr->p_transfer_rx; + usb_shstd_std_req_msg[ptr->ip].p_transfer_tx = ptr->p_transfer_tx; + + usb_hstd_transfer_start_req(&usb_shstd_std_req_msg[ptr->ip]); +} + +/****************************************************************************** + * End of function usb_hstd_enum_get_descriptor + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_enum_set_address + * Description : Send SetAddress to the connected USB device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : Device Address. + * : uint16_t setaddr : New address. + * Return : none + ******************************************************************************/ +void usb_hstd_enum_set_address (usb_utr_t * ptr, uint16_t addr, uint16_t setaddr) +{ + usb_shstd_std_request[ptr->ip][0] = USB_SET_ADDRESS | USB_HOST_TO_DEV | USB_STANDARD | USB_DEVICE; + usb_shstd_std_request[ptr->ip][1] = setaddr; + usb_shstd_std_request[ptr->ip][2] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][3] = (uint16_t) 0x0000; /* wLength */ + usb_shstd_std_request[ptr->ip][4] = addr; + usb_shstd_std_req_msg[ptr->ip].keyword = (uint16_t) USB_PIPE0; + usb_shstd_std_req_msg[ptr->ip].p_tranadr = USB_NULL; + usb_shstd_std_req_msg[ptr->ip].tranlen = 0; + usb_shstd_std_req_msg[ptr->ip].p_setup = usb_shstd_std_request[ptr->ip]; + usb_shstd_std_req_msg[ptr->ip].status = USB_DATA_NONE; + usb_shstd_std_req_msg[ptr->ip].complete = (usb_cb_t) &usb_hstd_submit_result; + usb_shstd_std_req_msg[ptr->ip].segment = USB_TRAN_END; + + usb_shstd_std_req_msg[ptr->ip].ipp = ptr->ipp; + usb_shstd_std_req_msg[ptr->ip].ip = ptr->ip; + + usb_hstd_transfer_start_req(&usb_shstd_std_req_msg[ptr->ip]); +} + +/****************************************************************************** + * End of function usb_hstd_enum_set_address + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_enum_set_configuration + * Description : Send SetConfiguration to the connected USB device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : Device Address. + * : uint16_t confnum : Configuration number. + * Return : none + ******************************************************************************/ +void usb_hstd_enum_set_configuration (usb_utr_t * ptr, uint16_t addr, uint16_t confnum) +{ + usb_shstd_std_request[ptr->ip][0] = USB_SET_CONFIGURATION | USB_HOST_TO_DEV | USB_STANDARD | USB_DEVICE; + usb_shstd_std_request[ptr->ip][1] = confnum; + usb_shstd_std_request[ptr->ip][2] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][3] = (uint16_t) 0x0000; /* wLength */ + usb_shstd_std_request[ptr->ip][4] = addr; + usb_shstd_std_req_msg[ptr->ip].keyword = (uint16_t) USB_PIPE0; + usb_shstd_std_req_msg[ptr->ip].p_tranadr = USB_NULL; + usb_shstd_std_req_msg[ptr->ip].tranlen = 0; + usb_shstd_std_req_msg[ptr->ip].p_setup = usb_shstd_std_request[ptr->ip]; + usb_shstd_std_req_msg[ptr->ip].status = USB_DATA_NONE; + usb_shstd_std_req_msg[ptr->ip].complete = (usb_cb_t) &usb_hstd_submit_result; + usb_shstd_std_req_msg[ptr->ip].segment = USB_TRAN_END; + + usb_shstd_std_req_msg[ptr->ip].ipp = ptr->ipp; + usb_shstd_std_req_msg[ptr->ip].ip = ptr->ip; + + usb_hstd_transfer_start_req(&usb_shstd_std_req_msg[ptr->ip]); +} + +/****************************************************************************** + * End of function usb_hstd_enum_set_configuration + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_enum_dummy_request + * Description : Dummy function. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : Device Address + * : uint16_t cnt_value : Enumeration Sequence + * Return : none + ******************************************************************************/ +void usb_hstd_enum_dummy_request (usb_utr_t * ptr, uint16_t addr, uint16_t cnt_value) +{ + /* Non */ + (void) *ptr; + (void) addr; + (void) cnt_value; +} + +/****************************************************************************** + * End of function usb_hstd_enum_dummy_request + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_mgr_suspend + * Description : Suspend request + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t info : Info for release of memory block. + * Return : none + ******************************************************************************/ +void usb_hstd_mgr_suspend (usb_utr_t * ptr, uint16_t info) +{ + #if (BSP_CFG_RTOS != 0) + uint16_t devaddr; + uint16_t devsel; + uint16_t j; + uint16_t ret; + + devaddr = p_usb_shstd_mgr_msg[ptr->ip]->keyword; + devsel = (uint16_t) (devaddr << USB_DEVADDRBIT); + + /* Get root port number from device addr */ + if (USB_NOCONNECT != usb_hstd_chk_dev_addr(ptr, devsel)) + { + /* PIPE suspend */ + /* WAIT_LOOP */ + for (j = USB_MIN_PIPE_NO; j <= USB_MAX_PIPE_NO; j++) + { + /* Agreement device address */ + if (usb_hstd_get_devsel(ptr, j) == devsel) + { + /* PID=BUF ? */ + if (USB_PID_BUF == usb_cstd_get_pid(ptr, j)) + { + usb_cstd_set_nak(ptr, j); + g_usb_hstd_suspend_pipe[ptr->ip][j] = USB_SUSPENDED; + } + } + } + + /* Get Configuration Descriptor */ + usb_hstd_get_config_desc(ptr, devaddr, (uint16_t) 0x09); + + /* Check Remote Wake-up */ + if (USB_TRUE == usb_hstd_chk_remote(ptr)) + { + /* Set Feature */ + ret = usb_hstd_set_feature(ptr, devaddr, (uint16_t) USB_VALUE_FFH); + if (USB_OK == ret) + { + usb_hstd_device_state_ctrl(ptr, devaddr, (uint16_t) USB_MSG_HCD_REMOTE); + g_usb_hstd_mgr_mode[ptr->ip] = USB_SUSPENDED; + } + } + else + { + USB_PRINTF0("### Remote wake up disable\n"); + usb_hstd_device_state_ctrl(ptr, devaddr, (uint16_t) USB_MSG_HCD_REMOTE); + g_usb_hstd_mgr_mode[ptr->ip] = USB_SUSPENDED; + } + } + + usb_hstd_mgr_rel_mpl(ptr, info); + #else /* (BSP_CFG_RTOS != 0) */ + uint16_t devaddr; + uint16_t devsel; + uint16_t j; + + devaddr = p_usb_shstd_mgr_msg[ptr->ip]->keyword; + devsel = (uint16_t) (devaddr << USB_DEVADDRBIT); + + if (USB_NOCONNECT != usb_hstd_chk_dev_addr(ptr, devsel)) + { + /* PIPE suspend */ + /* WAIT_LOOP */ + for (j = USB_MIN_PIPE_NO; j <= USB_MAX_PIPE_NO; j++) + { + /* Agreement device address */ + if (usb_hstd_get_devsel(ptr, j) == devsel) + { + /* PID=BUF ? */ + if (USB_PID_BUF == usb_cstd_get_pid(ptr, j)) + { + usb_cstd_set_nak(ptr, j); + g_usb_hstd_suspend_pipe[ptr->ip][j] = USB_SUSPENDED; + } + } + } + + usb_shstd_suspend_seq[ptr->ip] = 0; + usb_hstd_susp_cont(ptr, devaddr); + g_usb_hstd_mgr_mode[ptr->ip] = USB_SUSPENDED_PROCESS; + } + usb_hstd_mgr_rel_mpl(ptr, info); + #endif /* (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hstd_mgr_suspend + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_device_state_ctrl + * Description : Setup a call to the function usb_hstd_change_device_state to re- + * : quest the connected USB Device to change status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t devaddr : Device address. + * : uint16_t msginfo : Request type. + * Return : none + ******************************************************************************/ +void usb_hstd_device_state_ctrl (usb_utr_t * ptr, uint16_t devaddr, uint16_t msginfo) +{ + switch (devaddr) + { + case 0: + { + USB_PRINTF0("### usbd_message device address error\n"); + break; + } + + case USB_DEVICEADDR: + { + usb_hstd_hcd_snd_mbx(ptr, msginfo, USB_NULL, (uint16_t *) 0, &usb_hstd_status_result); + break; + } + + default: + { + if (USB_HUBDPADDR <= devaddr) + { + /* Non */ + } + + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_device_state_ctrl + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_device_state_ctrl2 + * Description : Setup a call to the function usb_hstd_change_device_state to re- + * : quest the connected USB Device to change status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : usb_cb_t complete : Callback function Pointer + * : uint16_t devaddr : Device address + * : uint16_t msginfo : Request type for HCD + * : uint16_t mgr_msginfo : Request type for MGR + * Return : none + ******************************************************************************/ +void usb_hstd_device_state_ctrl2 (usb_utr_t * ptr, + usb_cb_t complete, + uint16_t devaddr, + uint16_t msginfo, + uint16_t mgr_msginfo) +{ + usb_shstd_mgr_callback[ptr->ip] = complete; + usb_shstd_mgr_msginfo[ptr->ip] = mgr_msginfo; + usb_hstd_device_state_ctrl(ptr, devaddr, msginfo); +} + +/****************************************************************************** + * End of function usb_hstd_device_state_ctrl2 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_mgr_reset + * Description : Request HCD (Host Control Driver) to do a USB bus reset. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t devaddr : Device address. + * Return : none + ******************************************************************************/ +void usb_hstd_mgr_reset (usb_utr_t * ptr, uint16_t addr) +{ + usb_hstd_device_state_ctrl(ptr, addr, (uint16_t) USB_MSG_HCD_USBRESET); + if (USB_DEVICEADDR == addr) + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_DEFAULT; + } + else + { + /* Non */ + } +} + +/****************************************************************************** + * End of function usb_hstd_mgr_reset + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_mgr_resume + * Description : Request HCD (Host Control Device) to send RESUME signal. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t info : Information. + * Return : none + ******************************************************************************/ +void usb_hstd_mgr_resume (usb_utr_t * ptr, uint16_t info) +{ + #if (BSP_CFG_RTOS != 0) + uint16_t rootport = 0; + uint16_t devaddr; + uint16_t devsel; + uint16_t md; + uint16_t j; + usb_er_t ret; + usb_hcdreg_t * driver; + + devaddr = p_usb_shstd_mgr_msg[ptr->ip]->keyword; + devsel = (uint16_t) (devaddr << USB_DEVADDRBIT); + + /* Get root port number from device addr */ + if (USB_NOCONNECT != usb_hstd_chk_dev_addr(ptr, devsel)) + { + /* Device resume */ + usb_hstd_device_state_ctrl(ptr, devaddr, p_usb_shstd_mgr_msg[ptr->ip]->msginfo); + + /* Wait resume signal */ + usb_cpu_delay_xms((uint16_t) USB_VALUE_100); + + /* Get Configuration Descriptor */ + usb_hstd_get_config_desc(ptr, devaddr, (uint16_t) 0x09); + + /* Check Remote wake-up */ + if (USB_TRUE == usb_hstd_chk_remote(ptr)) + { + ret = usb_hstd_clr_feature(ptr, devaddr, (uint16_t) USB_VALUE_FFH, (usb_cb_t) &class_trans_result); + if (USB_OK == ret) + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_CONFIGURED; + } + } + else + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_CONFIGURED; + } + } + + if (USB_CONFIGURED == g_usb_hstd_mgr_mode[ptr->ip]) + { + /* PIPE resume */ + /* WAIT_LOOP */ + for (j = USB_MIN_PIPE_NO; j <= USB_MAX_PIPE_NO; j++) + { + /* Agreement device address */ + if (usb_hstd_get_device_address(ptr, j) == devsel) + { + if (USB_SUSPENDED == g_usb_hstd_suspend_pipe[ptr->ip][j]) + { + usb_cstd_set_buf(ptr, j); + g_usb_hstd_suspend_pipe[ptr->ip][j] = USB_OK; + } + } + } + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if ((rootport + USB_DEVICEADDR) == driver->devaddr) + { + (*driver->devresume)(ptr, driver->devaddr, (uint16_t) USB_NO_ARG); + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][1] = USB_CONFIGURED; + + if (USB_DO_GLOBAL_RESUME == usb_shstd_mgr_msginfo[ptr->ip]) + { + usb_hstd_mgr_chgdevst_cb(ptr); + } + + /* Device state */ + driver->devstate = USB_CONFIGURED; + } + } + } + + usb_hstd_mgr_rel_mpl(ptr, info); + #else /* (BSP_CFG_RTOS != 0) */ + uint16_t devaddr; + uint16_t devsel; + + devaddr = p_usb_shstd_mgr_msg[ptr->ip]->keyword; + devsel = (uint16_t) (devaddr << USB_DEVADDRBIT); + + if (USB_NOCONNECT != usb_hstd_chk_dev_addr(ptr, devsel)) + { + /* Device resume */ + usb_hstd_device_state_ctrl(ptr, devaddr, p_usb_shstd_mgr_msg[ptr->ip]->msginfo); + g_usb_hstd_mgr_mode[ptr->ip] = USB_RESUME_PROCESS; + usb_shstd_resume_seq[ptr->ip] = 0; + } + usb_hstd_mgr_rel_mpl(ptr, info); + #endif /* (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hstd_mgr_resume + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hstd_susp_cont + * Description : Suspend the connected USB Device (Function for nonOS) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t devaddr : Device Address + * Return : none + ******************************************************************************/ +static void usb_hstd_susp_cont (usb_utr_t * ptr, uint16_t devaddr) +{ + uint16_t checkerr; + + checkerr = p_usb_shstd_mgr_msg[ptr->ip]->result; + + switch (usb_shstd_suspend_seq[ptr->ip]) + { + case 0: + { + usb_hstd_get_config_desc(ptr, devaddr, (uint16_t) 0x09, (usb_cb_t) &usb_hstd_submit_result); + usb_shstd_suspend_seq[ptr->ip]++; + break; + } + + case 1: + { + if (USB_OK == usb_hstd_std_req_check(checkerr)) + { + if (USB_TRUE == usb_hstd_chk_remote(ptr)) + { + usb_hstd_set_feature(ptr, devaddr, (uint16_t) USB_VALUE_FFH, (usb_cb_t) &usb_hstd_submit_result); + usb_shstd_suspend_seq[ptr->ip]++; + } + else + { + USB_PRINTF0("### Remote wake up disable\n"); + usb_hstd_device_state_ctrl(ptr, devaddr, (uint16_t) USB_MSG_HCD_REMOTE); + g_usb_hstd_mgr_mode[ptr->ip] = USB_SUSPENDED; + } + } + + break; + } + + case 2: + { + if (USB_OK == usb_hstd_std_req_check(checkerr)) + { + usb_hstd_device_state_ctrl(ptr, devaddr, (uint16_t) USB_MSG_HCD_REMOTE); + g_usb_hstd_mgr_mode[ptr->ip] = USB_SUSPENDED; + } + + break; + } + + default: + { + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_susp_cont + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_resu_cont + * Description : Resume the connected USB Device (Function for nonOS) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t devaddr : Device Address + * Return : none + ******************************************************************************/ +static void usb_hstd_resu_cont (usb_utr_t * ptr, uint16_t devaddr) +{ + uint16_t devsel; + uint16_t j; + uint16_t md; + usb_hcdreg_t * driver; + uint16_t checkerr; + + devsel = (uint16_t) (devaddr << USB_DEVADDRBIT); + checkerr = p_usb_shstd_mgr_msg[ptr->ip]->result; + + switch (usb_shstd_resume_seq[ptr->ip]) + { + case 0: + { + usb_hstd_get_config_desc(ptr, devaddr, (uint16_t) 0x09, (usb_cb_t) &usb_hstd_submit_result); + usb_shstd_resume_seq[ptr->ip]++; + break; + } + + case 1: + { + if (USB_OK == usb_hstd_std_req_check(checkerr)) + { + if (USB_TRUE == usb_hstd_chk_remote(ptr)) + { + usb_hstd_clr_feature(ptr, devaddr, (uint16_t) USB_VALUE_FFH, (usb_cb_t) &usb_hstd_submit_result); + usb_shstd_resume_seq[ptr->ip]++; + } + else + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_CONFIGURED; + } + } + + break; + } + + case 2: + { + if (USB_OK == usb_hstd_std_req_check(checkerr)) + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_CONFIGURED; + } + + break; + } + + default: + { + break; + } + } + + if (USB_CONFIGURED == g_usb_hstd_mgr_mode[ptr->ip]) + { + /* PIPE resume */ + /* WAIT_LOOP */ + for (j = USB_MIN_PIPE_NO; j <= USB_MAX_PIPE_NO; j++) + { + /* Agreement device address */ + if (usb_hstd_get_device_address(ptr, j) == devsel) + { + if (USB_SUSPENDED == g_usb_hstd_suspend_pipe[ptr->ip][j]) + { + usb_cstd_set_buf(ptr, j); + g_usb_hstd_suspend_pipe[ptr->ip][j] = USB_OK; + } + } + } + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (USB_DEVICEADDR == driver->devaddr) + { + (*driver->devresume)(ptr, driver->devaddr, (uint16_t) USB_NO_ARG); + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][1] = USB_CONFIGURED; + + if (USB_DO_GLOBAL_RESUME == usb_shstd_mgr_msginfo[ptr->ip]) + { + usb_hstd_mgr_chgdevst_cb(ptr); + } + + /* Device state */ + driver->devstate = USB_CONFIGURED; + } + } + } +} + +/****************************************************************************** + * End of function usb_hstd_resu_cont + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hstd_chk_remote + * Description : check remote + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : uint16_t : error info + ******************************************************************************/ +static uint16_t usb_hstd_chk_remote (usb_utr_t * ptr) +{ + if ((uint8_t) 0 != (g_usb_hstd_class_data[ptr->ip][7] & USB_CF_RWUPON)) + { + return USB_TRUE; + } + + return USB_FALSE; +} + +/****************************************************************************** + * End of function usb_hstd_chk_remote + ******************************************************************************/ + +/* Condition compilation by the difference of IP */ + +/****************************************************************************** + * Function Name : usb_hstd_cmd_submit + * Description : command submit + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : usb_cb_t complete : callback info + * Return value : uint16_t : USB_OK + ******************************************************************************/ + #if (BSP_CFG_RTOS != 0) +static uint16_t usb_hstd_cmd_submit (usb_utr_t * ptr) +{ + uint16_t retval; + + g_usb_hstd_class_ctrl[ptr->ip].p_tranadr = (void *) g_usb_hstd_class_data[ptr->ip]; + g_usb_hstd_class_ctrl[ptr->ip].complete = &class_trans_result; + g_usb_hstd_class_ctrl[ptr->ip].tranlen = (uint32_t) g_usb_hstd_class_request[ptr->ip][3]; + g_usb_hstd_class_ctrl[ptr->ip].keyword = USB_PIPE0; + g_usb_hstd_class_ctrl[ptr->ip].p_setup = g_usb_hstd_class_request[ptr->ip]; + g_usb_hstd_class_ctrl[ptr->ip].segment = USB_TRAN_END; + + g_usb_hstd_class_ctrl[ptr->ip].ip = ptr->ip; + g_usb_hstd_class_ctrl[ptr->ip].ipp = ptr->ipp; + + retval = (uint16_t) usb_hstd_transfer_start_req(&g_usb_hstd_class_ctrl[ptr->ip]); + + if (USB_QOVR == retval) + { + /** Submit overlap error **/ + /** Retry **/ + /* WAIT_LOOP */ + do + { + usb_cpu_delay_xms((uint16_t) 2); + retval = (uint16_t) usb_hstd_transfer_start_req(&g_usb_hstd_class_ctrl[ptr->ip]); + } while (USB_QOVR == retval); + } + + if (USB_OK == retval) + { + retval = class_trans_wait_tmo(ptr, (uint16_t) USB_VALUE_3000); + } + + return retval; +} + + #else /* (BSP_CFG_RTOS != 0) */ +static uint16_t usb_hstd_cmd_submit (usb_utr_t * ptr, usb_cb_t complete) +{ + g_usb_hstd_class_ctrl[ptr->ip].p_tranadr = (void *) g_usb_hstd_class_data[ptr->ip]; + g_usb_hstd_class_ctrl[ptr->ip].complete = complete; + g_usb_hstd_class_ctrl[ptr->ip].tranlen = (uint32_t) g_usb_hstd_class_request[ptr->ip][3]; + g_usb_hstd_class_ctrl[ptr->ip].keyword = USB_PIPE0; + g_usb_hstd_class_ctrl[ptr->ip].p_setup = g_usb_hstd_class_request[ptr->ip]; + g_usb_hstd_class_ctrl[ptr->ip].segment = USB_TRAN_END; + + g_usb_hstd_class_ctrl[ptr->ip].ip = ptr->ip; + g_usb_hstd_class_ctrl[ptr->ip].ipp = ptr->ipp; + + usb_hstd_transfer_start_req(&g_usb_hstd_class_ctrl[ptr->ip]); + + return USB_OK; +} + + #endif /* (BSP_CFG_RTOS != 0) */ + +/****************************************************************************** + * End of function usb_hstd_cmd_submit + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_set_feature + * Description : Set SetFeature + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : device address + * : uint16_t epnum : endpoint number + * : usb_cb_t complete : callback function + * Return value : uint16_t : error info + ******************************************************************************/ + #if (BSP_CFG_RTOS != 0) +uint16_t usb_hstd_set_feature (usb_utr_t * ptr, uint16_t addr, uint16_t epnum) + #else /* (BSP_CFG_RTOS != 0) */ +uint16_t usb_hstd_set_feature (usb_utr_t * ptr, uint16_t addr, uint16_t epnum, usb_cb_t complete) + #endif /* (BSP_CFG_RTOS != 0) */ +{ + if (USB_VALUE_FFH == epnum) + { + /* SetFeature(Device) */ + g_usb_hstd_class_request[ptr->ip][0] = USB_SET_FEATURE | USB_HOST_TO_DEV | USB_STANDARD | USB_DEVICE; + g_usb_hstd_class_request[ptr->ip][1] = USB_DEV_REMOTE_WAKEUP; + g_usb_hstd_class_request[ptr->ip][2] = (uint16_t) 0x0000; + } + else + { + /* SetFeature(endpoint) */ + g_usb_hstd_class_request[ptr->ip][0] = USB_SET_FEATURE | USB_HOST_TO_DEV | USB_STANDARD | USB_ENDPOINT; + g_usb_hstd_class_request[ptr->ip][1] = USB_ENDPOINT_HALT; + g_usb_hstd_class_request[ptr->ip][2] = epnum; + } + + g_usb_hstd_class_request[ptr->ip][3] = (uint16_t) 0x0000; + g_usb_hstd_class_request[ptr->ip][4] = addr; + + #if (BSP_CFG_RTOS != 0) + + return usb_hstd_cmd_submit(ptr); + #else /* (BSP_CFG_RTOS != 0) */ + return usb_hstd_cmd_submit(ptr, complete); + #endif /* (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hstd_set_feature + ******************************************************************************/ + + #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) + +/****************************************************************************** + * Function Name : usb_hid_set_protocol + * Description : Send SetProtocol to the connected USB device. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : Device Address. + * : uint16_t protocol : New address. + * Return : none + ******************************************************************************/ +void usb_hid_set_protocol (usb_utr_t * ptr, uint16_t addr, uint16_t protocol) +{ + usb_shstd_std_request[ptr->ip][0] = (USB_HID_SET_PROTOCOL | USB_HOST_TO_DEV | USB_CLASS | USB_INTERFACE); + usb_shstd_std_request[ptr->ip][1] = protocol; + usb_shstd_std_request[ptr->ip][2] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][3] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][4] = addr; + usb_shstd_std_req_msg[ptr->ip].keyword = (uint16_t) USB_PIPE0; + usb_shstd_std_req_msg[ptr->ip].tranlen = (uint32_t) usb_shstd_std_request[ptr->ip][3]; + usb_shstd_std_req_msg[ptr->ip].p_setup = usb_shstd_std_request[ptr->ip]; + usb_shstd_std_req_msg[ptr->ip].status = USB_DATA_NONE; + usb_shstd_std_req_msg[ptr->ip].complete = (usb_cb_t) &usb_hstd_submit_result; + usb_shstd_std_req_msg[ptr->ip].segment = USB_TRAN_END; + + usb_shstd_std_req_msg[ptr->ip].ipp = ptr->ipp; + usb_shstd_std_req_msg[ptr->ip].ip = ptr->ip; + usb_shstd_std_req_msg[ptr->ip].p_transfer_rx = ptr->p_transfer_rx; + usb_shstd_std_req_msg[ptr->ip].p_transfer_tx = ptr->p_transfer_tx; + + usb_hstd_transfer_start_req(&usb_shstd_std_req_msg[ptr->ip]); +} + +/****************************************************************************** + * Function Name : usb_hid_get_string_desc + * Description : Set GetDescriptor + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : device address + * : uint16_t string : descriptor index + ******************************************************************************/ +void usb_hid_get_string_desc (usb_utr_t * ptr, uint16_t addr, uint16_t string) +{ + uint16_t i; + + if (0 == string) + { + usb_shstd_std_request[ptr->ip][2] = (uint16_t) 0x0000; + usb_shstd_std_request[ptr->ip][3] = (uint16_t) 0x0004; + } + else + { + /* Set LanguageID */ + usb_shstd_std_request[ptr->ip][2] = (uint16_t) (g_usb_hstd_class_data[ptr->ip][2]); + usb_shstd_std_request[ptr->ip][2] |= (uint16_t) ((uint16_t) (g_usb_hstd_class_data[ptr->ip][3]) << 8); + usb_shstd_std_request[ptr->ip][3] = (uint16_t) CLSDATASIZE; + } + + usb_shstd_std_request[ptr->ip][0] = USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE; + usb_shstd_std_request[ptr->ip][1] = (uint16_t) (USB_STRING_DESCRIPTOR + string); + usb_shstd_std_request[ptr->ip][4] = addr; + + /* WAIT_LOOP */ + for (i = 0; i < usb_shstd_std_request[ptr->ip][3]; i++) + { + g_usb_hstd_class_data[ptr->ip][i] = (uint8_t) USB_VALUE_FFH; + } + + usb_shstd_std_req_msg[ptr->ip].keyword = USB_PIPE0; + usb_shstd_std_req_msg[ptr->ip].tranlen = (uint32_t) usb_shstd_std_request[ptr->ip][3]; + usb_shstd_std_req_msg[ptr->ip].p_setup = usb_shstd_std_request[ptr->ip]; + usb_shstd_std_req_msg[ptr->ip].complete = &usb_hstd_submit_result; + usb_shstd_std_req_msg[ptr->ip].segment = USB_TRAN_END; + usb_shstd_std_req_msg[ptr->ip].p_tranadr = (void *) g_usb_hstd_class_data[ptr->ip]; + + usb_shstd_std_req_msg[ptr->ip].ip = ptr->ip; + usb_shstd_std_req_msg[ptr->ip].ipp = ptr->ipp; + + usb_hstd_transfer_start_req(&usb_shstd_std_req_msg[ptr->ip]); +} + + #endif /* #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) */ + +/****************************************************************************** + * Function Name : usb_hstd_get_config_desc + * Description : Set GetConfigurationDescriptor + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : device address + * : uint16_t length : descriptor length + * : usb_cb_t complete : callback function + * Return value : uint16_t : error info + ******************************************************************************/ + #if (BSP_CFG_RTOS != 0) +uint16_t usb_hstd_get_config_desc (usb_utr_t * ptr, uint16_t addr, uint16_t length) + #else /* (BSP_CFG_RTOS != 0) */ +uint16_t usb_hstd_get_config_desc (usb_utr_t * ptr, uint16_t addr, uint16_t length, usb_cb_t complete) + #endif /* (BSP_CFG_RTOS != 0) */ +{ + uint16_t i; + + /* Get Configuration Descriptor */ + g_usb_hstd_class_request[ptr->ip][0] = USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE; + g_usb_hstd_class_request[ptr->ip][1] = USB_CONF_DESCRIPTOR; + g_usb_hstd_class_request[ptr->ip][2] = (uint16_t) 0x0000; + g_usb_hstd_class_request[ptr->ip][3] = length; + if (g_usb_hstd_class_request[ptr->ip][3] > CLSDATASIZE) + { + g_usb_hstd_class_request[ptr->ip][3] = (uint16_t) CLSDATASIZE; + USB_PRINTF0("***WARNING Descriptor size over !\n"); + } + + g_usb_hstd_class_request[ptr->ip][4] = addr; + + /* WAIT_LOOP */ + for (i = 0; i < g_usb_hstd_class_request[ptr->ip][3]; i++) + { + g_usb_hstd_class_data[ptr->ip][i] = (uint8_t) USB_VALUE_FFH; + } + + #if (BSP_CFG_RTOS != 0) + + return usb_hstd_cmd_submit(ptr); + #else /* (BSP_CFG_RTOS != 0) */ + return usb_hstd_cmd_submit(ptr, complete); + #endif /* (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hstd_get_config_desc + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_hstd_std_req_check + * Description : Sample Standard Request Check + * Arguments : uint16_t errcheck : error + * Return value : uint16_t : error info + ******************************************************************************/ +uint16_t usb_hstd_std_req_check (uint16_t errcheck) +{ + uint16_t result_code = USB_OK; + + if (USB_DATA_TMO == errcheck) + { + USB_PRINTF0("*** Standard Request Timeout error !\n"); + result_code = USB_ERROR; + } + else if (USB_DATA_STALL == errcheck) + { + USB_PRINTF0("*** Standard Request STALL !\n"); + result_code = USB_ERROR; + } + else if (USB_CTRL_END != errcheck) + { + USB_PRINTF0("*** Standard Request error !\n"); + result_code = USB_ERROR; + } + else + { + /* Non */ + } + + return result_code; +} + +/****************************************************************************** + * End of function usb_hstd_std_req_check + ******************************************************************************/ + #endif /* (BSP_CFG_RTOS == 0) */ + +/****************************************************************************** + * Function Name : usb_hstd_get_string_desc + * Description : Set GetDescriptor + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t addr : device address + * : uint16_t string : descriptor index + * : usb_cb_t complete : callback function + * Return value : uint16_t : error info + ******************************************************************************/ + #if (BSP_CFG_RTOS != 0) +uint16_t usb_hstd_get_string_desc (usb_utr_t * ptr, uint16_t addr, uint16_t string) + #else /* (BSP_CFG_RTOS != 0) */ +uint16_t usb_hstd_get_string_desc (usb_utr_t * ptr, uint16_t addr, uint16_t string, usb_cb_t complete) + #endif /* (BSP_CFG_RTOS != 0) */ +{ + uint16_t i; + + if (0 == string) + { + g_usb_hstd_class_request[ptr->ip][2] = (uint16_t) 0x0000; + g_usb_hstd_class_request[ptr->ip][3] = (uint16_t) 0x0004; + } + else + { + /* Set LanguageID */ + g_usb_hstd_class_request[ptr->ip][2] = (uint16_t) (g_usb_hstd_class_data[ptr->ip][2]); + g_usb_hstd_class_request[ptr->ip][2] |= (uint16_t) ((uint16_t) (g_usb_hstd_class_data[ptr->ip][3]) << 8); + g_usb_hstd_class_request[ptr->ip][3] = (uint16_t) CLSDATASIZE; + } + + g_usb_hstd_class_request[ptr->ip][0] = USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE; + g_usb_hstd_class_request[ptr->ip][1] = (uint16_t) (USB_STRING_DESCRIPTOR + string); + g_usb_hstd_class_request[ptr->ip][4] = addr; + + /* WAIT_LOOP */ + for (i = 0; i < g_usb_hstd_class_request[ptr->ip][3]; i++) + { + g_usb_hstd_class_data[ptr->ip][i] = (uint8_t) USB_VALUE_FFH; + } + + #if (BSP_CFG_RTOS != 0) + + return usb_hstd_cmd_submit(ptr); + #else /* (BSP_CFG_RTOS != 0) */ + return usb_hstd_cmd_submit(ptr, complete); + #endif /* (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hstd_get_string_desc + ******************************************************************************/ + + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + #if USB_CFG_ELECTRICAL == USB_CFG_ENABLE + +/****************************************************************************** + * Function Name : usb_hstd_electrical_test_mode + * Description : Host electrical test mode function + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t product_id : Task Start Code + * : uint16_t port : Port number + * Return : none + ******************************************************************************/ +void usb_hstd_electrical_test_mode (usb_utr_t * ptr, uint16_t product_id) +{ + uint16_t brdysts; + + switch (product_id) + { + case 0x0101: /* Test_SE0_NAK */ + { + usb_hstd_test_signal(ptr, 3); + + /* WAIT_LOOP */ + while (1) + { + /* This loops infinitely until it's reset. */ + } + + break; + } + + case 0x0102: /* Test_J */ + { + usb_hstd_test_signal(ptr, 1); + + /* WAIT_LOOP */ + while (1) + { + /* This loops infinitely until it's reset. */ + } + + break; + } + + case 0x0103: /* Test_K */ + { + usb_hstd_test_signal(ptr, 2); + + /* WAIT_LOOP */ + while (1) + { + /* This loops infinitely until it's reset. */ + } + + break; + } + + case 0x0104: /* Test_Packet */ + { + usb_hstd_test_signal(ptr, 4); + + /* WAIT_LOOP */ + while (1) + { + /* This loops infinitely until it's reset. */ + } + + break; + } + + case 0x0105: /* Reserved */ + { + break; + } + + case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */ + { + usb_cpu_delay_xms(15000); /* wait 15sec */ + usb_hstd_test_suspend(ptr); + usb_cpu_delay_xms(15000); /* wait 15sec */ + usb_hstd_test_resume(ptr); + break; + } + + case 0x0107: /* SINGLE_STEP_GET_DEV_DESC */ + { + usb_cpu_delay_xms(15000); /* wait 15sec */ + hw_usb_hwrite_usbreq(ptr, (USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE)); + hw_usb_hset_usbval(ptr, USB_DEV_DESCRIPTOR); + hw_usb_hset_usbleng(ptr, 0x0012); + hw_usb_hset_sureq(ptr); + break; + } + + case 0x0108: /* SINGLE_STEP_GET_DEV_DESC_DATA */ + { + hw_usb_hwrite_usbreq(ptr, (USB_GET_DESCRIPTOR | USB_DEV_TO_HOST | USB_STANDARD | USB_DEVICE)); + hw_usb_hset_usbval(ptr, USB_DEV_DESCRIPTOR); + hw_usb_hset_usbindx(ptr, 0x0000); + hw_usb_hset_usbleng(ptr, 0x0012); + hw_usb_hset_sureq(ptr); + usb_cpu_delay_xms(15000); /* wait 15sec */ + + usb_cstd_set_nak(ptr, USB_PIPE0); + hw_usb_write_dcpcfg(ptr, 0); + + hw_usb_hwrite_dcpctr(ptr, USB_SQSET); + usb_hstd_do_sqtgl(ptr, (uint16_t) USB_PIPE0, USB_SQMON); + + hw_usb_rmw_fifosel(ptr, USB_CUSE, (USB_RCNT | USB_PIPE0), (USB_RCNT | USB_ISEL | USB_CURPIPE)); + hw_usb_set_bclr(ptr, USB_CUSE); + usb_cstd_set_buf(ptr, USB_PIPE0); + + /* WAIT_LOOP */ + do + { + brdysts = hw_usb_read_brdysts(ptr); + } while (!(brdysts & USB_BRDY0)); + + usb_cstd_set_nak(ptr, USB_PIPE0); + hw_usb_set_sqclr(ptr, USB_PIPE0); + hw_usb_set_bclr(ptr, USB_CUSE); + break; + } + + default: + { + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_electrical_test_mode + ******************************************************************************/ + #endif /* USB_CFG_ELECTRICAL == USB_CFG_ENABLE */ + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + +/****************************************************************************** + * Function Name : usb_hstd_mgr_task + * Description : The host manager (MGR) task. + * Argument : usb_vp_int_t stacd : Task Start Code + * Return : none + ******************************************************************************/ + #if (BSP_CFG_RTOS == 1) +void usb_hstd_mgr_task (ULONG entry_input) + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_hstd_mgr_task (void * stacd) + #endif /* #if (BSP_CFG_RTOS == 1) */ +{ + usb_utr_t * mess; + usb_utr_t * ptr; + usb_er_t err; + usb_hcdreg_t * driver; + usb_hcdinfo_t * hp; + uint16_t rootport; + uint16_t devaddr; + uint16_t pipenum; + uint16_t msginfo; + uint16_t md; + uint16_t enume_mode; /* Enumeration mode (device state) */ + uint16_t connect_speed; + uint16_t result = 0; + usb_instance_ctrl_t ctrl; + #if defined(USB_CFG_HMSC_USE) && defined(USB_CFG_HCDC_USE) && (USB_CFG_MULTIPORT == USB_CFG_DISABLE) + usb_cfg_t * p_cfg = USB_NULL; + #endif /* defined(USB_CFG_HMSC_USE) && defined(USB_CFG_HCDC_USE) */ + #if (BSP_CFG_RTOS == 0) + uint16_t devsel; + #endif /* (BSP_CFG_RTOS == 0) */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + usb_compliance_t disp_param; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + #if defined(USB_CFG_OTG_USE) + uint16_t syssts; + #endif /* defined(USB_CFG_OTG_USE) */ + + #if (BSP_CFG_RTOS == 1) + (void) entry_input; + #else /* #if (BSP_CFG_RTOS == 1) */ + (void) stacd; + #endif /* #if (BSP_CFG_RTOS == 1) */ + + #if (BSP_CFG_RTOS != 0) + + /* WAIT_LOOP */ + while (1) + { + #endif /* (BSP_CFG_RTOS != 0) */ + /* Receive message */ + err = USB_TRCV_MSG(USB_MGR_MBX, (usb_msg_t **) &mess, (usb_tm_t) 10000); + if (USB_OK != err) + { + #if (BSP_CFG_RTOS != 0) + result = 1; + #else /* (BSP_CFG_RTOS != 0) */ + result = 0; + #endif /* (BSP_CFG_RTOS != 0) */ + } + + else + { + p_usb_shstd_mgr_msg[mess->ip] = (usb_mgrinfo_t *) mess; + rootport = p_usb_shstd_mgr_msg[mess->ip]->keyword; + devaddr = p_usb_shstd_mgr_msg[mess->ip]->keyword; + pipenum = p_usb_shstd_mgr_msg[mess->ip]->keyword; + #if (BSP_CFG_RTOS == 0) + #endif /* (BSP_CFG_RTOS != 0) */ + hp = (usb_hcdinfo_t *) mess; + ptr = mess; + + /* Detach is all device */ + msginfo = p_usb_shstd_mgr_msg[ptr->ip]->msginfo; + switch (p_usb_shstd_mgr_msg[ptr->ip]->msginfo) + { + /* USB-bus control (change device state) */ + case USB_MSG_MGR_STATUSRESULT: + { + switch (g_usb_hstd_mgr_mode[ptr->ip]) + { + /* End of reset signal */ + case USB_DEFAULT: + { + g_usb_hstd_device_speed[ptr->ip] = p_usb_shstd_mgr_msg[ptr->ip]->result; + + /* Set device speed */ + usb_hstd_set_dev_addr(ptr, (uint16_t) USB_DEVICE_0, g_usb_hstd_device_speed[ptr->ip]); + g_usb_hstd_dcp_register[ptr->ip][0] = (uint16_t) (USB_DEFPACKET + USB_DEVICE_0); + #if defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) + g_idx_configuration[ptr->ip] = 0; + #endif /* defined(USB_CFG_HCDC_ECM_USE) && (BSP_CFG_RTOS == 2) */ + g_usb_hstd_enum_seq[ptr->ip] = 0; + switch (g_usb_hstd_device_speed[ptr->ip]) + { + case USB_HSCONNECT: /* Hi Speed Device Connect */ + { + USB_PRINTF0(" Hi-Speed Device\n"); + (*g_usb_hstd_enumaration_process[0])(ptr, (uint16_t) USB_DEVICE_0, (uint16_t) 0); + break; + } + + case USB_FSCONNECT: /* Full Speed Device Connect */ + { + USB_PRINTF0(" Full-Speed Device\n"); + (*g_usb_hstd_enumaration_process[0])(ptr, (uint16_t) USB_DEVICE_0, (uint16_t) 0); + break; + } + + case USB_LSCONNECT: /* Low Speed Device Connect */ + { + USB_PRINTF0(" Low-Speed Device\n"); + hw_usb_hset_trnensel(ptr); + usb_hstd_ls_connect_function(ptr); + break; + } + + default: + { + USB_PRINTF0(" Device/Detached\n"); + g_usb_hstd_mgr_mode[ptr->ip] = USB_DETACHED; + break; + } + } + + #if (BSP_CFG_RTOS == 1) + if (USB_DETACHED != g_usb_hstd_mgr_mode[ptr->ip]) + { + usb_host_usbx_attach_init(ptr->ip); + } + #endif /* BSP_CFG_RTOS == 1 */ + + break; + } + + /* End of resume signal */ + case USB_CONFIGURED: + { + /* This Resume Sorce is moved to usb_hResuCont() by nonOS */ + #if (BSP_CFG_RTOS != 0) + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if ((rootport + USB_DEVICEADDR) == driver->devaddr) + { + (*driver->devresume)(ptr, driver->devaddr, (uint16_t) USB_NO_ARG); + + if (USB_DO_GLOBAL_RESUME == usb_shstd_mgr_msginfo[ptr->ip]) + { + usb_hstd_mgr_chgdevst_cb(ptr); + } + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][1] = USB_CONFIGURED; + + /* Device state */ + driver->devstate = USB_CONFIGURED; + } + } + #endif /* (BSP_CFG_RTOS != 0) */ + break; + } + + /* Start of suspended state */ + case USB_SUSPENDED: + { + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (USB_DEVICEADDR == driver->devaddr) + { + (*driver->devsuspend)(ptr, driver->devaddr, (uint16_t) USB_NO_ARG); + + if (USB_DO_GLOBAL_SUSPEND == usb_shstd_mgr_msginfo[ptr->ip]) + { + usb_hstd_mgr_chgdevst_cb(ptr); + } + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][1] = USB_SUSPENDED; + + /* Device state */ + driver->devstate = USB_SUSPENDED; + } + } + + break; + } + + /* Continue of resume signal */ + case USB_RESUME_PROCESS: + { + #if (BSP_CFG_RTOS == 0) + + /* Resume Sequence Number is 0 */ + usb_hstd_resu_cont(ptr, USB_DEVICEADDR); + #endif /* (BSP_CFG_RTOS == 0) */ + break; + } + + case USB_DETACHED: + { + switch (usb_shstd_mgr_msginfo[ptr->ip]) + { + case USB_PORT_DISABLE: + { + usb_hstd_mgr_chgdevst_cb(ptr); + break; + } + + default: + { + break; + } + } + + break; + } + + default: + { + break; + } + } + + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_MGR_SUBMITRESULT: + { + /* Agreement device address */ + #if (BSP_CFG_RTOS != 0) + usb_hstd_get_devsel(ptr, pipenum); + #else + devsel = usb_hstd_get_devsel(ptr, pipenum); + #endif /* (BSP_CFG_RTOS != 0) */ + + /* Get root port number from device addr */ + switch (g_usb_hstd_mgr_mode[ptr->ip]) + { + #if (BSP_CFG_RTOS == 0) + + /* Resume */ + case USB_RESUME_PROCESS: + { + /* Resume Sequence Number is 1 to 2 */ + usb_hstd_resu_cont(ptr, (uint16_t) (devsel >> USB_DEVADDRBIT)); + break; + } + + /* Suspend */ + case USB_SUSPENDED_PROCESS: + { + usb_hstd_susp_cont(ptr, (uint16_t) (devsel >> USB_DEVADDRBIT)); + break; + } + #endif /* (BSP_CFG_RTOS == 0) */ + + /* Enumeration */ + case USB_DEFAULT: + #if (BSP_CFG_RTOS == 1) + case USB_CONFIGURED: + #endif /* #if (BSP_CFG_RTOS == 1) */ + { + /* Peripheral Device Speed support check */ + connect_speed = usb_hstd_support_speed_check(ptr); + if (USB_NOCONNECT != connect_speed) + { + enume_mode = usb_hstd_enumeration(ptr); + switch (enume_mode) + { + /* Detach Mode */ + case USB_NONDEVICE: + { + USB_PRINTF1("### Enumeration error (address%d)\n", + g_usb_hstd_device_addr[ptr->ip]); + g_usb_hstd_mgr_mode[ptr->ip] = USB_DETACHED; + + if ((USB_DO_RESET_AND_ENUMERATION == usb_shstd_mgr_msginfo[ptr->ip]) || + (USB_PORT_ENABLE == usb_shstd_mgr_msginfo[ptr->ip])) + { + usb_hstd_mgr_chgdevst_cb(ptr); + } + + break; + } + + /* Detach Mode */ + case USB_NOTTPL: + { + USB_PRINTF1("### Not support device (address%d)\n", + g_usb_hstd_device_addr[ptr->ip]); + g_usb_hstd_mgr_mode[ptr->ip] = USB_DETACHED; + + if ((USB_DO_RESET_AND_ENUMERATION == usb_shstd_mgr_msginfo[ptr->ip]) || + (USB_PORT_ENABLE == usb_shstd_mgr_msginfo[ptr->ip])) + { + usb_hstd_mgr_chgdevst_cb(ptr); + } + + break; + } + + case USB_COMPLETEPIPESET: + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_CONFIGURED; + + if ((USB_DO_RESET_AND_ENUMERATION == usb_shstd_mgr_msginfo[ptr->ip]) || + (USB_PORT_ENABLE == usb_shstd_mgr_msginfo[ptr->ip])) + { + usb_hstd_mgr_chgdevst_cb(ptr); + } + + break; + } + + default: + { + break; + } + } + } + + break; + } + + default: + { + break; + } + } + + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + + case USB_MSG_MGR_AORDETACH: + { + switch (p_usb_shstd_mgr_msg[ptr->ip]->result) + { + case USB_DETACH: + { + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + disp_param.status = USB_COMPLIANCETEST_DETACH; + disp_param.pid = USB_NULL; + disp_param.vid = USB_NULL; + (*g_usb_compliance_callback[ptr->ip])((void *) &disp_param); + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + g_usb_hstd_mgr_mode[ptr->ip] = USB_DETACHED; + g_usb_hstd_device_speed[ptr->ip] = USB_NOCONNECT; + + #if !defined(USB_CFG_OTG_USE) + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if ((USB_DEVICEADDR == driver->devaddr) || (USB_CONFIGURED == driver->devstate)) + { + #else /* !defined(USB_CFG_OTG_USE) */ + driver = &g_usb_hstd_device_drv[ptr->ip][0]; + if (USB_DEVICEADDR == driver->devaddr) + { + #endif /* !defined(USB_CFG_OTG_USE) */ + + #if defined(USB_CFG_HHID_USE) + #if (BSP_CFG_RTOS == 0) + if (USB_DEVICEADDR == driver->devaddr) + { + g_usb_change_device_state[ptr->ip] = USB_NULL; + } + #endif /* BSP_CFG_RTOS_USED == 0 */ + #endif /* defined(USB_CFG_HHID_USE) */ + + (*driver->devdetach)(ptr, driver->devaddr, (uint16_t) USB_NO_ARG); + + /* Root port */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][0] = USB_NOPORT; + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][1] = USB_DETACHED; + + #if defined(USB_CFG_OTG_USE) + syssts = hw_usb_read_syssts(ptr); + if (USB_IDMON != (syssts & USB_IDMON)) + { + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_A; + } + else + { + syssts = hw_usb_read_syssts(ptr); + if (USB_SE0 == (syssts & USB_LNST)) + { + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; + } + } + #endif /* defined(USB_CFG_OTG_USE) */ + + /* Not configured */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][2] = (uint16_t) 0; + + /* Interface Class : NO class */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][3] = (uint16_t) USB_IFCLS_NOT; + + /* No connect */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][4] = (uint16_t) USB_NOCONNECT; + + /* Root port */ + driver->rootport = USB_NOPORT; + + /* Device address */ + driver->devaddr = USB_NODEVICE; + + /* Device state */ + driver->devstate = USB_DETACHED; + + #if !defined(USB_CFG_OTG_USE) + } + } + + #else /* !defined(USB_CFG_OTG_USE) */ + } + else + { + if (_ux_system_host->ux_system_host_change_function != UX_NULL) + { + /* Inform the application the device is removed. */ + _ux_system_host->ux_system_host_change_function(UX_DEVICE_REMOVAL, + USB_NULL, + (VOID *) USB_NULL); + } + } + #endif /* !defined(USB_CFG_OTG_USE) */ + + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + + case USB_ATTACHL: + + /* continue */ + case USB_ATTACHF: + { + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE + disp_param.status = USB_COMPLIANCETEST_ATTACH; + disp_param.pid = USB_NULL; + disp_param.vid = USB_NULL; + (*g_usb_compliance_callback[ptr->ip])((void *) &disp_param); + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + if (USB_DETACHED == g_usb_hstd_mgr_mode[ptr->ip]) + { + g_usb_hstd_device_addr[ptr->ip] = USB_DEVICEADDR; + if (USB_MAXDEVADDR < g_usb_hstd_device_addr[ptr->ip]) + { + /* For port1 */ + USB_PRINTF0("Device address error\n"); + } + else + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_DEFAULT; + + #if USB_CFG_BC == USB_CFG_ENABLE + + /* Call Back */ + /*USB_BC_ATTACH(ptr, g_usb_hstd_device_addr[ptr->ip], (uint16_t)g_usb_hstd_bc[ptr->ip].state); */ + if (USB_BC_STATE_CDP == g_usb_hstd_bc[ptr->ip].state) + { + #if defined(USB_CFG_HMSC_USE) && defined(USB_CFG_HCDC_USE) && (USB_CFG_MULTIPORT == USB_CFG_DISABLE) + if (ptr->ip) + { + #if defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet( + (IRQn_Type) VECTOR_NUMBER_USBHS_USB_INT_RESUME); + #endif /* #if defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME) */ + } + else + { + #if defined(VECTOR_NUMBER_USBFS_INT) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBFS_INT); + #endif /* #if defined(VECTOR_NUMBER_USBFS_INT) */ + } + + if (USB_NULL != p_cfg) + { + ctrl.p_context = (void *) p_cfg->p_context; + } + #endif /* defined(USB_CFG_HMSC_USE) && defined(USB_CFG_HCDC_USE) */ + ctrl.device_address = (uint8_t) g_usb_hstd_device_addr[ptr->ip]; /* USB Device address */ + ctrl.module_number = (uint8_t) ptr->ip; /* Module number setting */ + usb_set_event(USB_STATUS_BC, &ctrl); /* Set Event() */ + } + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + + usb_hstd_attach_function(); + usb_hstd_mgr_reset(ptr, g_usb_hstd_device_addr[ptr->ip]); + } + + usb_hstd_mgr_rel_mpl(ptr, msginfo); + } + else + { + usb_hstd_mgr_rel_mpl(ptr, msginfo); + } + + break; + } + + default: + { + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + } + + break; + } + + case USB_MSG_MGR_OVERCURRENT: + { + ctrl.module_number = ptr->ip; /* Module number setting */ + usb_set_event(USB_STATUS_OVERCURRENT, &ctrl); /* Set Event() */ + + USB_PRINTF0(" Please detach device \n "); + USB_PRINTF1("VBUS off port%d\n", rootport); + usb_hstd_vbus_control(ptr, (uint16_t) USB_VBOFF); + g_usb_hstd_mgr_mode[ptr->ip] = USB_DEFAULT; + + /* WAIT_LOOP */ + for (md = 0; md < g_usb_hstd_device_num[ptr->ip]; md++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][md]; + if (driver->rootport == rootport) + { + /* Root port */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][0] = USB_NOPORT; + + /* Device state */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][1] = USB_DETACHED; + + /* Not configured */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][2] = (uint16_t) 0; + + /* Interface Class : NO class */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][3] = (uint16_t) USB_IFCLS_NOT; + + /* No connect */ + g_usb_hstd_device_info[ptr->ip][driver->devaddr][4] = (uint16_t) USB_NOCONNECT; + + /* Root port */ + driver->rootport = USB_NOPORT; + + /* Device address */ + driver->devaddr = USB_NODEVICE; + + /* Device state */ + driver->devstate = USB_DETACHED; + } + } + + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + + /* USB_MSG_HCD_ATTACH */ + case USB_DO_RESET_AND_ENUMERATION: + { + ptr->msginfo = USB_MSG_HCD_ATTACH_MGR; + + if (USB_DEVICEADDR == devaddr) + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_DETACHED; + } + else + { + /* Non */ + } + + usb_hstd_device_state_ctrl2(ptr, hp->complete, devaddr, ptr->msginfo, msginfo); + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + + /* USB_MSG_HCD_VBON */ + case USB_PORT_ENABLE: + { + ptr->msginfo = USB_MSG_HCD_VBON; + if (USB_DEVICEADDR == devaddr) + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_DETACHED; + } + else + { + /* Non */ + } + + usb_hstd_device_state_ctrl2(ptr, hp->complete, devaddr, ptr->msginfo, msginfo); + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + + /* USB_MSG_HCD_VBOFF */ + case USB_PORT_DISABLE: + { + /* VBUS is off at the time of the abnormalities in a device */ + ptr->msginfo = USB_MSG_HCD_VBOFF; + if (USB_DEVICEADDR == devaddr) + { + g_usb_hstd_mgr_mode[ptr->ip] = USB_DETACHED; + } + else + { + /* Non */ + } + + usb_hstd_device_state_ctrl2(ptr, hp->complete, devaddr, ptr->msginfo, msginfo); + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + + /* USB_MSG_HCD_SUSPEND */ + case USB_DO_GLOBAL_SUSPEND: + { + ptr->msginfo = USB_MSG_HCD_REMOTE; + usb_shstd_mgr_callback[ptr->ip] = hp->complete; + usb_shstd_mgr_msginfo[ptr->ip] = msginfo; + usb_hstd_mgr_suspend(ptr, msginfo); + break; + } + + /* USB_MSG_HCD_SUSPEND */ + case USB_DO_SELECTIVE_SUSPEND: + { + ptr->msginfo = USB_MSG_HCD_REMOTE; + usb_hstd_mgr_suspend(ptr, msginfo); + usb_hstd_device_state_ctrl2(ptr, hp->complete, devaddr, ptr->msginfo, msginfo); + break; + } + + /* USB_MSG_HCD_RESUME */ + case USB_DO_GLOBAL_RESUME: + { + ptr->msginfo = USB_MSG_HCD_RESUME; + usb_shstd_mgr_callback[ptr->ip] = hp->complete; + usb_shstd_mgr_msginfo[ptr->ip] = msginfo; + usb_hstd_mgr_resume(ptr, msginfo); + break; + } + + /* USB_MSG_HCD_RESUME */ + case USB_MSG_HCD_RESUME: + { + usb_shstd_mgr_msginfo[ptr->ip] = msginfo; + usb_hstd_mgr_resume(ptr, msginfo); + break; + } + + /* USB_MSG_HCD_RESUME */ + case USB_DO_SELECTIVE_RESUME: + { + ptr->msginfo = USB_MSG_HCD_RESUME; + usb_hstd_mgr_resume(ptr, msginfo); + usb_hstd_device_state_ctrl2(ptr, hp->complete, devaddr, ptr->msginfo, msginfo); + break; + } + + default: + { + usb_hstd_mgr_rel_mpl(ptr, msginfo); + break; + } + } + } + + #if (BSP_CFG_RTOS != 0) + if (1 == result) + { + continue; + } + + #else /* (BSP_CFG_RTOS != 0) */ + if (0 == result) + { + return; + } + #endif /* (BSP_CFG_RTOS != 0) */ + + #if (BSP_CFG_RTOS != 0) +} /* End of while(1) */ + #endif /* (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_hstd_mgr_task + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_mgr_open + * Description : Initialize global variable that contains registration status + * : of HDCD. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +usb_er_t usb_hstd_mgr_open (usb_utr_t * ptr) +{ + usb_er_t err = USB_OK; + usb_hcdreg_t * driver; + uint16_t i; + static uint8_t is_init = USB_NO; + + if (USB_NO == is_init) + { + memset((void *) &usb_shstd_std_request, 0, (5 * 2)); + memset((void *) &usb_shstd_std_req_msg, 0, sizeof(usb_utr_t)); + is_init = USB_YES; + } + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAX_PIPE_NO + 1); i++) + { + g_usb_hstd_suspend_pipe[ptr->ip][i] = 0; + } + + memset(g_usb_hstd_class_data[ptr->ip], 0, CLSDATASIZE); + memset(g_usb_hstd_device_descriptor[ptr->ip], 0, USB_DEVICESIZE); + memset(g_usb_hstd_config_descriptor[ptr->ip], 0, USB_CONFIGSIZE); + memset((void *) &g_usb_hstd_class_request[ptr->ip], 0, (5 * 2)); + memset((void *) &g_usb_hstd_class_ctrl[ptr->ip], 0, sizeof(usb_utr_t)); + memset((void *) &p_usb_shstd_mgr_msg[ptr->ip], 0, sizeof(usb_mgrinfo_t *)); + + g_usb_hstd_enum_seq[ptr->ip] = 0; + g_usb_hstd_check_enu_result[ptr->ip] = 0; + usb_shstd_mgr_msginfo[ptr->ip] = 0; + #if (BSP_CFG_RTOS == 0) + usb_shstd_reg_pointer[ptr->ip] = 0; + usb_shstd_suspend_seq[ptr->ip] = 0; + usb_shstd_resume_seq[ptr->ip] = 0; + #endif /* (BSP_CFG_RTOS == 0) */ + usb_shstd_mgr_callback[ptr->ip] = 0; + + /* Manager Mode */ + g_usb_hstd_mgr_mode[ptr->ip] = USB_DETACHED; + g_usb_hstd_device_speed[ptr->ip] = USB_NOCONNECT; + + /* Device address */ + g_usb_hstd_device_addr[ptr->ip] = USB_DEVICE_0; + + /* Device driver number */ + g_usb_hstd_device_num[ptr->ip] = 0; + + /* WAIT_LOOP */ + for (i = USB_PIPE0; i <= USB_MAX_PIPE_NO; i++) + { + g_usb_hstd_suspend_pipe[ptr->ip][i] = USB_OK; + } + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAXDEVADDR + 1U); i++) + { + driver = &g_usb_hstd_device_drv[ptr->ip][i]; + + driver->rootport = USB_NOPORT; /* Root port */ + driver->devaddr = USB_NODEVICE; /* Device address */ + driver->devstate = USB_DETACHED; /* Device state */ + driver->ifclass = (uint16_t) USB_IFCLS_NOT; /* Interface Class : NO class */ + g_usb_hstd_device_info[ptr->ip][i][0] = USB_NOPORT; /* Root port */ + g_usb_hstd_device_info[ptr->ip][i][1] = USB_DETACHED; /* Device state */ + g_usb_hstd_device_info[ptr->ip][i][2] = (uint16_t) 0; /* Not configured */ + g_usb_hstd_device_info[ptr->ip][i][3] = (uint16_t) USB_IFCLS_NOT; /* Interface Class : NO class */ + g_usb_hstd_device_info[ptr->ip][i][4] = (uint16_t) USB_NOCONNECT; /* No connect */ + } + + USB_PRINTF0("*** Install USB-MGR ***\n"); + + usb_cstd_set_task_pri(USB_MGR_TSK, USB_PRI_2); + + return err; +} + +/****************************************************************************** + * End of function usb_hstd_mgr_open + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hscheduler.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hscheduler.c new file mode 100644 index 0000000000..1bcab1ae1f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hscheduler.c @@ -0,0 +1,504 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include +#include +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "../hw/inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +#if (BSP_CFG_RTOS == 0) + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + #define USB_IDMAX (11U) /* Maximum Task ID +1 */ + #define USB_PRIMAX (8U) /* Maximum Priority number +1 */ + #define USB_BLKMAX (20U) /* Maximum block */ + #define USB_TABLEMAX (USB_BLKMAX) /* Maximum priority table */ + #define USB_WAIT_EVENT_MAX (5U) + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ + +/* Priority Table */ +static usb_msg_t * p_usb_scheduler_table_add[USB_PRIMAX][USB_TABLEMAX]; +static uint8_t usb_scheduler_table_id[USB_PRIMAX][USB_TABLEMAX]; +static uint8_t usb_scheduler_pri_r[USB_PRIMAX]; +static uint8_t usb_scheduler_pri_w[USB_PRIMAX]; +static uint8_t usb_scheduler_pri[USB_IDMAX]; + +/* Schedule Set Flag */ +static uint8_t usb_scheduler_schedule_flag; + +/* Fixed-sized memory pools */ +static usb_utr_t usb_scheduler_block[USB_BLKMAX]; +static uint8_t usb_scheduler_blk_flg[USB_BLKMAX]; + +static usb_msg_t * p_usb_scheduler_add_use; +static uint8_t usb_scheduler_id_use; + +/* Wait MSG */ +static usb_msg_t * p_usb_scheduler_wait_add[USB_IDMAX][USB_WAIT_EVENT_MAX]; +static uint16_t usb_scheduler_wait_counter[USB_IDMAX][USB_WAIT_EVENT_MAX]; + +/****************************************************************************** + * Exported global variables + ******************************************************************************/ + +/****************************************************************************** + * Renesas Scheduler API functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_rec_msg + * Description : Receive a message to the specified id (mailbox). + * Argument : uint8_t id : ID number (mailbox). + * : usb_msg_t** mess : Message pointer + * : usb_tm_t tm : Timeout Value + * Return : uint16_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_rec_msg (uint8_t id, usb_msg_t ** mess, usb_tm_t tm) +{ + FSP_PARAMETER_NOT_USED(tm); + if ((id < USB_IDMAX) && (usb_scheduler_id_use < USB_IDMAX)) + { + if (id == usb_scheduler_id_use) + { + *mess = p_usb_scheduler_add_use; + + return USB_OK; + } + } + + return USB_ERROR; +} + +/****************************************************************************** + * End of function usb_cstd_rec_msg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_snd_msg + * Description : Send a message to the specified id (mailbox). + * Argument : uint8_t id : ID number (mailbox). + * : usb_msg_t* mess : Message pointer + * Return : usb_er_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_snd_msg (uint8_t id, usb_msg_t * mess) +{ + usb_er_t status; + + /* USB interrupt disable */ + usb_cpu_int_disable(); + status = usb_cstd_isnd_msg(id, mess); + + /* USB interrupt enable */ + usb_cpu_int_enable(); + + return status; +} + +/****************************************************************************** + * End of function usb_cstd_snd_msg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_isnd_msg + * Description : Send a message to the specified id (mailbox) while executing + * : an interrupt. + * Argument : uint8_t id : ID number (mailbox). + * : usb_msg_t* mess : Message pointer + * Return : usb_er_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_isnd_msg (uint8_t id, usb_msg_t * mess) +{ + uint8_t usb_pri; /* Task Priority */ + uint8_t usb_write; /* Priority Table Writing pointer */ + + if (id < USB_IDMAX) + { + /* Read priority and table pointer */ + usb_pri = usb_scheduler_pri[id]; + usb_write = usb_scheduler_pri_w[usb_pri]; + if (usb_pri < USB_PRIMAX) + { + /* Renewal write pointer */ + usb_write++; + if (usb_write >= USB_TABLEMAX) + { + usb_write = USB_TBLCLR; + } + + /* Check pointer */ + if (usb_write == usb_scheduler_pri_r[usb_pri]) + { + return USB_ERROR; + } + + /* Save message */ + /* Set priority table */ + usb_scheduler_table_id[usb_pri][usb_write] = id; + p_usb_scheduler_table_add[usb_pri][usb_write] = mess; + usb_scheduler_pri_w[usb_pri] = usb_write; + + return USB_OK; + } + } + + USB_PRINTF0("SND_MSG ERROR !!\n"); + + return USB_ERROR; +} + +/****************************************************************************** + * End of function usb_cstd_isnd_msg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_pget_blk + * Description : Get a memory block for the caller. + * Argument : uint8_t id : ID number (mailbox). + * : usb_utr_t** blk : Memory block pointer. + * Return : usb_er_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_pget_blk (uint8_t id, usb_utr_t ** blk, uint8_t ip) +{ + FSP_PARAMETER_NOT_USED(ip); + uint8_t usb_s_pblk_c; + + if (id < USB_IDMAX) + { + usb_s_pblk_c = USB_CNTCLR; + + /* WAIT_LOOP */ + while (USB_BLKMAX != usb_s_pblk_c) + { + if (USB_FLGCLR == usb_scheduler_blk_flg[usb_s_pblk_c]) + { + /* Acquire fixed-size memory block */ + *blk = &usb_scheduler_block[usb_s_pblk_c]; + usb_scheduler_blk_flg[usb_s_pblk_c] = USB_FLGSET; + + return FSP_SUCCESS; + } + + usb_s_pblk_c++; + } + + /* Error of BLK Table Full !! */ + USB_PRINTF1("usb_scBlkFlg[%d][] Full !!\n", id); + } + + return FSP_ERR_USB_FAILED; +} + +/****************************************************************************** + * End of function usb_cstd_pget_blk + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_rel_blk + * Description : Release a memory block. + * Argument : uint8_t id : ID number (mailbox). + * : usb_utr_t* blk : Memory block pointer. + * Return : usb_er_t : USB_OK / USB_ERROR + ******************************************************************************/ +usb_er_t usb_cstd_rel_blk (uint8_t id, usb_utr_t * blk) +{ + uint16_t usb_s_rblk_c; + + if (id < USB_IDMAX) + { + usb_s_rblk_c = USB_CNTCLR; + + /* WAIT_LOOP */ + while (USB_BLKMAX != usb_s_rblk_c) + { + if ((&usb_scheduler_block[usb_s_rblk_c]) == blk) + { + /* Release fixed-size memory block */ + usb_scheduler_blk_flg[usb_s_rblk_c] = USB_FLGCLR; + + return FSP_SUCCESS; + } + + usb_s_rblk_c++; + } + + /* Error of BLK Flag is not CLR !! */ + USB_PRINTF0("TskBlk NO CLR !!\n"); + } + + return FSP_ERR_USB_FAILED; +} + +/****************************************************************************** + * End of function usb_cstd_rel_blk + ******************************************************************************/ + +/***************************************************************************//** + * @brief Runs USB_SND_MSG after running the scheduler the specified number of times. + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_FAILED Failed in acquiring version information. + ******************************************************************************/ +fsp_err_t usb_cstd_wai_msg (uint8_t id, usb_msg_t * mess, usb_tm_t times) +{ + uint8_t i; + + if (id < USB_IDMAX) + { + /* WAIT_LOOP */ + for (i = 0; i < USB_WAIT_EVENT_MAX; i++) + { + if (0 == usb_scheduler_wait_counter[id][i]) + { + p_usb_scheduler_wait_add[id][i] = mess; + usb_scheduler_wait_counter[id][i] = (uint16_t) times; + + return FSP_SUCCESS; + } + } + } + + /* Error !! */ + USB_PRINTF0("WAI_MSG ERROR !!\n"); + + return FSP_ERR_USB_FAILED; +} + +/****************************************************************************** + * End of function usb_cstd_wai_msg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_wait_scheduler + * Description : Schedules a wait request. + * Argument : none + * Return : none + ******************************************************************************/ +void usb_cstd_wait_scheduler (void) +{ + usb_er_t err; + uint8_t id; + uint8_t i; + + /* WAIT_LOOP */ + for (id = 0; id < USB_IDMAX; id++) + { + /* WAIT_LOOP */ + for (i = 0; i < USB_WAIT_EVENT_MAX; i++) + { + if (0 != usb_scheduler_wait_counter[id][i]) + { + usb_scheduler_wait_counter[id][i]--; + if (0 == usb_scheduler_wait_counter[id][i]) + { + err = usb_cstd_snd_msg(id, p_usb_scheduler_wait_add[id][i]); + if (USB_OK != err) + { + usb_scheduler_wait_counter[id][i]++; + } + } + } + } + } +} + +/****************************************************************************** + * End of function usb_cstd_wait_scheduler + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_sche_init + * Description : Scheduler initialization. + * Argument : none + * Return : none + ******************************************************************************/ +void usb_cstd_sche_init (void) +{ + uint8_t i; + uint8_t j; + + memset(usb_scheduler_table_id, 0, sizeof(usb_scheduler_table_id)); + memset(usb_scheduler_pri_r, 0, sizeof(usb_scheduler_pri_r)); + memset(usb_scheduler_pri_w, 0, sizeof(usb_scheduler_pri_w)); + memset(usb_scheduler_pri, 0, sizeof(usb_scheduler_pri)); + memset((void *) &usb_scheduler_schedule_flag, 0, sizeof(usb_scheduler_schedule_flag)); + memset(usb_scheduler_blk_flg, 0, sizeof(usb_scheduler_blk_flg)); + memset((void *) &usb_scheduler_id_use, 0, sizeof(usb_scheduler_id_use)); + memset(usb_scheduler_wait_counter, 0, sizeof(usb_scheduler_wait_counter)); + memset(p_usb_scheduler_table_add, 0, sizeof(p_usb_scheduler_table_add)); + memset(usb_scheduler_block, 0, sizeof(usb_scheduler_block)); + p_usb_scheduler_add_use = NULL; + memset(p_usb_scheduler_wait_add, 0, sizeof(p_usb_scheduler_wait_add)); + + /* Initial Scheduler */ + usb_scheduler_id_use = USB_NULL; + usb_scheduler_schedule_flag = USB_NULL; + + /* Initialize priority table pointer and priority table */ + /* WAIT_LOOP */ + for (i = 0; USB_PRIMAX != i; i++) + { + usb_scheduler_pri_r[i] = USB_NULL; + usb_scheduler_pri_w[i] = USB_NULL; + + /* WAIT_LOOP */ + for (j = 0; USB_TABLEMAX != j; j++) + { + usb_scheduler_table_id[i][j] = USB_IDMAX; + } + } + + /* Initialize block table */ + /* WAIT_LOOP */ + for (i = 0; USB_BLKMAX != i; i++) + { + usb_scheduler_blk_flg[i] = USB_NULL; + } + + /* Initialize priority */ + /* WAIT_LOOP */ + for (i = 0; USB_IDMAX != i; i++) + { + usb_scheduler_pri[i] = (uint8_t) USB_IDCLR; + + /* WAIT_LOOP */ + for (j = 0; j < USB_WAIT_EVENT_MAX; j++) + { + p_usb_scheduler_wait_add[i][j] = (usb_msg_t *) USB_NULL; + usb_scheduler_wait_counter[i][j] = USB_NULL; + } + } +} + +/****************************************************************************** + * End of function usb_cstd_sche_init + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_scheduler + * Description : The scheduler. + * Argument : none + * Return : none + ******************************************************************************/ +void usb_cstd_scheduler (void) +{ + uint8_t usb_pri; /* Priority Counter */ + uint8_t usb_read; /* Priority Table read pointer */ + + /* wait msg */ + usb_cstd_wait_scheduler(); + + /* Priority Table reading */ + usb_pri = USB_CNTCLR; + + /* WAIT_LOOP */ + while (usb_pri < USB_PRIMAX) + { + usb_read = usb_scheduler_pri_r[usb_pri]; + if (usb_read != usb_scheduler_pri_w[usb_pri]) + { + /* Priority Table read pointer increment */ + usb_read++; + if (usb_read >= USB_TABLEMAX) + { + usb_read = USB_TBLCLR; + } + + /* Set practice message */ + usb_scheduler_id_use = usb_scheduler_table_id[usb_pri][usb_read]; + p_usb_scheduler_add_use = p_usb_scheduler_table_add[usb_pri][usb_read]; + usb_scheduler_table_id[usb_pri][usb_read] = USB_IDMAX; + usb_scheduler_pri_r[usb_pri] = usb_read; + usb_scheduler_schedule_flag = USB_FLGSET; + usb_pri = USB_PRIMAX; + } + else + { + usb_pri++; + } + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + usb_cstd_dma_driver(); /* USB DMA driver */ + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ +} + +/****************************************************************************** + * End of function usb_cstd_scheduler + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_set_task_pri + * Description : Set a task's priority. + * Argument : uint8_t tasknum : Task id. + * : uint8_t pri : The task priority to be set. + * Return : none + ******************************************************************************/ +void usb_cstd_set_task_pri (uint8_t tasknum, uint8_t pri) +{ + if (tasknum < USB_IDMAX) + { + if (pri < USB_PRIMAX) + { + usb_scheduler_pri[tasknum] = pri; + } + else if ((uint8_t) USB_IDCLR == pri) + { + usb_scheduler_pri[tasknum] = (uint8_t) USB_IDCLR; + } + else + { + /* Non */ + } + } +} + +/****************************************************************************** + * End of function usb_cstd_set_task_pri + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_check_schedule + * Description : Check schedule flag to see if caller's "time has come", then + * : clear it. + * Argument : none + * Return : flg : usb_scheduler_schedule_flag + ******************************************************************************/ +uint8_t usb_cstd_check_schedule (void) +{ + uint8_t flg; + + flg = usb_scheduler_schedule_flag; + usb_scheduler_schedule_flag = USB_FLGCLR; + + return flg; +} + +/****************************************************************************** + * End of function usb_cstd_check_schedule + ******************************************************************************/ + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#endif /* BSP_CFG_RTOS == 0 */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hsignal.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hsignal.c new file mode 100644 index 0000000000..b206545328 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hsignal.c @@ -0,0 +1,167 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Renesas Abstracted Host Signal functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_vbus_control + * Description : USB VBUS ON/OFF setting. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t command : ON / OFF. + * Return value : none + ******************************************************************************/ +void usb_hstd_vbus_control (usb_utr_t * ptr, uint16_t command) +{ + if (USB_VBON == command) + { + hw_usb_set_vbout(ptr); + #if USB_CFG_BC == USB_CFG_ENABLE + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + usb_hstd_bc_func[g_usb_hstd_bc[ptr->ip].state][USB_BC_EVENT_VB](ptr); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + } + else + { + hw_usb_clear_vbout(ptr); + } +} + +/****************************************************************************** + * End of function usb_hstd_vbus_control + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_suspend_process + * Description : Set USB registers as required when USB Device status is moved + * : to "Suspend". + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_suspend_process (usb_utr_t * ptr) +{ + /* SUSPENDED check */ + if (USB_SUSPENDED == g_usb_hstd_remort_port[ptr->ip]) + { + /* SOF OFF */ + hw_usb_hclear_uact(ptr); + + /* Wait */ + usb_cpu_delay_xms((uint16_t) 1); + usb_hstd_chk_sof(ptr); + + /* RWUPE=1, UACT=0 */ + hw_usb_hset_rwupe(ptr); + + /* Enable port BCHG interrupt */ + usb_hstd_bchg_enable(ptr); + + /* Wait */ + usb_cpu_delay_xms((uint16_t) 5); + } + else + { + /* SOF OFF */ + hw_usb_hclear_uact(ptr); + + /* Wait */ + usb_cpu_delay_xms((uint16_t) 5); + } +} + +/****************************************************************************** + * End of function usb_hstd_suspend_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_attach + * Description : Set USB registers as required when USB device is attached, + * : and notify MGR (manager) task that attach event occurred. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t result : Result. + * : uint16_t port : Port number. + * Return value : none + ******************************************************************************/ +void usb_hstd_attach (usb_utr_t * ptr, uint16_t result) +{ + /* DTCH interrupt enable */ + usb_hstd_dtch_enable(ptr); + + /* Interrupt Enable */ + usb_hstd_berne_enable(ptr); + + /* USB Mng API */ + usb_hstd_notif_ator_detach(ptr, result); + #if USB_CFG_BC == USB_CFG_ENABLE + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + usb_hstd_bc_func[g_usb_hstd_bc[ptr->ip].state][USB_BC_EVENT_AT](ptr); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ +} + +/****************************************************************************** + * End of function usb_hstd_attach + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_detach + * Description : Set USB register as required when USB device is detached, and + * : notify MGR (manager) task that detach occurred. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t port : Port number. + * Return value : none + ******************************************************************************/ +void usb_hstd_detach (usb_utr_t * ptr) +{ + #if !defined(USB_CFG_OTG_USE) + #if USB_CFG_BC == USB_CFG_ENABLE + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + usb_hstd_bc_func[g_usb_hstd_bc[ptr->ip].state][USB_BC_EVENT_DT](ptr); + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + + /* DVSTCTR clear */ + hw_usb_clear_dvstctr(ptr, (uint16_t) (USB_RWUPE | USB_USBRST | USB_RESUME | USB_UACT)); + #endif /* !defined (USB_CFG_OTG_USE) */ + /* ATTCH interrupt enable */ + usb_hstd_attch_enable(ptr); + + /* USB Mng API */ + usb_hstd_notif_ator_detach(ptr, (uint16_t) USB_DETACH); +} + +/****************************************************************************** + * End of function usb_hstd_detach + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hstdfunction.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hstdfunction.c new file mode 100644 index 0000000000..1b80abae15 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_hstdfunction.c @@ -0,0 +1,314 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" /* USB register access function */ +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HCDC_USE) + #include "r_usb_hcdc_api.h" + #include "r_usb_hcdc_driver.h" + + #endif /* defined(USB_CFG_HCDC_USE) */ + + #if defined(USB_CFG_HMSC_USE) + #include "r_usb_hmsc_api.h" + + #endif /* defined(USB_CFG_HMSC_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#if (BSP_CFG_RTOS != 1) + #if defined(USB_CFG_HHID_USE) + #include "r_usb_hhid_api.h" + #endif /* defined(USB_CFG_HHID_USE) */ +#endif /* #if (BSP_CFG_RTOS != 1) */ + +#define USB_VALUE_100 (100) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +static uint16_t g_usb_cstd_driver_open = USB_FALSE; + +/****************************************************************************** + * Renesas Abstracted Host Standard functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_bchg0function + * Description : Execute the process appropriate to the status of the connected + * : USB device when a BCHG interrupt occurred. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_bchg0function (usb_utr_t * ptr) +{ + uint16_t buf; + uint16_t connect_inf; + + /* SUSPENDED check */ + if (USB_SUSPENDED == g_usb_hstd_remort_port[ptr->ip]) + { + /* Device State Control Register - Resume enable check */ + buf = hw_usb_read_dvstctr(ptr); + + if (USB_RESUME == (uint16_t) (buf & USB_RESUME)) + { + USB_PRINTF0("remote wake up port0\n"); + g_usb_hstd_remort_port[ptr->ip] = USB_DEFAULT; + + /* Change device state to resume */ + usb_hstd_device_resume(ptr, USB_DEVICEADDR); + } + else + { + /* Decide USB Line state (ATTACH) */ + connect_inf = usb_hstd_chk_attach(ptr); + if (USB_DETACH == connect_inf) + { + g_usb_hstd_remort_port[ptr->ip] = USB_DEFAULT; + + /* USB detach process */ + usb_hstd_detach_process(ptr); + } + else + { + /* Enable port BCHG interrupt */ + usb_hstd_bchg_enable(ptr); + + /* Check clock */ + usb_hstd_chk_clk(ptr, (uint16_t) USB_SUSPENDED); + } + } + } + else + { + /* USB detach process */ + usb_hstd_detach_process(ptr); + } +} + +/****************************************************************************** + * End of function usb_hstd_bchg0function + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_ls_connect_function + * Description : Low-speed device connect. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_ls_connect_function (usb_utr_t * ptr) +{ + (*g_usb_hstd_enumaration_process[0])(ptr, (uint16_t) USB_DEVICE_0, (uint16_t) 0); +} + +/****************************************************************************** + * End of function usb_hstd_ls_connect_function + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_attach_function + * Description : Device attach. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_hstd_attach_function (void) +{ + /* 100ms wait */ + usb_cpu_delay_xms((uint16_t) USB_VALUE_100); +} + +/****************************************************************************** + * End of function usb_hstd_attach_function + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_ovrcr0function + * Description : Set USB registers as required due to an OVRCR (over-current) + * : interrupt, and notify the MGR (manager) task about this. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_ovrcr0function (usb_utr_t * ptr) +{ + /* Over-current bit check */ + USB_PRINTF0(" OVCR int port0\n"); + + /* OVRCR interrupt disable */ + /* Notification over current */ + usb_hstd_ovcr_notifiation(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_ovrcr0function + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hdriver_init + * Description : USB Host driver initialization + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : usb_class_t type : USB class type + * Return value : none + ******************************************************************************/ +void usb_hdriver_init (usb_utr_t * ptr, usb_class_t type) +{ + uint16_t i; + (void) type; + + if (USB_FALSE == g_usb_cstd_driver_open) + { + usb_cstd_sche_init(); /* Scheduler init */ + #if (BSP_CFG_RTOS == 0) + g_usb_cstd_event.write_pointer = USB_NULL; /* Write pointer */ + g_usb_cstd_event.read_pointer = USB_NULL; /* Read pointer */ + #endif /* (BSP_CFG_RTOS == 0) */ + + /* WAIT_LOOP */ + for (i = 0; i < USB_EVENT_MAX; i++) + { + #if (BSP_CFG_RTOS != 0) + g_usb_cstd_event[i].event = USB_STATUS_NONE; + g_usb_cstd_event[i].device_address = USB_NULL; + #else /* (BSP_CFG_RTOS != 0) */ + g_usb_cstd_event.code[i] = USB_STATUS_NONE; + g_usb_cstd_event.ctrl[i].device_address = USB_NULL; + #endif /* (BSP_CFG_RTOS != 0) */ + } + + g_usb_cstd_driver_open = USB_TRUE; + } + + usb_hstd_init_usb_message(ptr); /* USB interrupt message initialize */ + + usb_hstd_mgr_open(ptr); /* Manager open */ + usb_hstd_hcd_open(ptr); /* Hcd open */ + #if (BSP_CFG_RTOS == 1) + usb_host_registration(ptr, type); /* Class Registration */ + #else + #if defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HMSC_USE) || \ + defined(USB_CFG_HVND_USE) || defined(USB_CFG_HAUD_USE) + usb_class_driver_start(ptr); /* Init host class driver task. */ + usb_host_registration(ptr, type); /* Class Registration */ + #endif /* defined(USB_CFG_HCDC_USE)||defined(USB_CFG_HHID_USE)||defined(USB_CFG_HMSC_USE)||defined(USB_CFG_HVND_USE)|| defined(USB_CFG_HAUD_USE) */ + #endif +} /* End of function usb_hdriver_init() */ + + #if (BSP_CFG_RTOS != 1) + +/****************************************************************************** + * Function Name : usb_class_driver_start + * Description : Init host class driver task. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_class_driver_start (usb_utr_t * ptr) +{ + (void) ptr; + #if defined(USB_CFG_HCDC_USE) + usb_hcdc_driver_start(ptr); + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + usb_hmsc_driver_start(ptr->ip); + usb_hmsc_storage_driver_start(ptr->ip); + #endif /* defined(USB_CFG_HMSC_USE) */ + #if defined(USB_CFG_HHID_USE) + usb_hhid_driver_start(ptr); + #endif /* defined(USB_CFG_HHID_USE) */ +} /* End of function usb_class_driver_start() */ + + #endif /* #if (BSP_CFG_RTOS != 1) */ + + #if (BSP_CFG_RTOS != 0) + +/****************************************************************************** + * Function Name : class_trans_result + * Description : Send a message to notify the result of the class request. + * Argument : usb_utr_t *ptr : USB system internal structure. Selects channel. + * uint16_t data1 + * uint16_t data2 + * Return value : none + ******************************************************************************/ +void class_trans_result (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + usb_er_t err; + + (void) data1; + (void) data2; + + /* Send an internal message */ + err = USB_SND_MSG(USB_CLS_MBX, (usb_msg_t *) ptr); + if (USB_OK != err) + { + USB_PRINTF1("### class_trans_result sends message error (%ld)\n", err); + } +} /* End of function class_trans_result() */ + +/****************************************************************************** + * Function Name : class_trans_wait_tmo + * Description : Receive the result of the class request with a timeout. + * Argument : usb_utr_t *ptr : USB system internal structure. Selects channel. + * uint16_t tmo : Time-out value. + * Return value : USB_OK/USB_ERROR + ******************************************************************************/ +uint16_t class_trans_wait_tmo (usb_utr_t * ptr, uint16_t tmo) +{ + usb_utr_t * mess; + usb_er_t err; + uint16_t result; + + (void) *ptr; + + /* Receive message with time out */ + err = USB_TRCV_MSG(USB_CLS_MBX, (usb_msg_t **) &mess, (usb_tm_t) tmo); + if (USB_OK != err) + { + USB_PRINTF1("### class_trans_wait_tmo receives message error (%ld)\n", err); + + return USB_ERROR; + } + + /* Check the status of transfer */ + if (USB_DATA_TMO == (mess->status)) + { + USB_PRINTF0("*** Standard Request Timeout error !\n"); + result = USB_ERROR; + } + else if (USB_DATA_STALL == (mess->status)) + { + USB_PRINTF0("*** Standard Request STALL !\n"); + result = USB_ERROR; + } + else if (USB_CTRL_END != (mess->status)) + { + USB_PRINTF0("*** Standard Request error !\n"); + result = USB_ERROR; + } + else + { + result = USB_OK; + } + + return result; +} /* End of function class_trans_wait_tmo() */ + + #endif /* (BSP_CFG_RTOS != 0) */ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pbc.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pbc.c new file mode 100644 index 0000000000..26c2543c6b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pbc.c @@ -0,0 +1,218 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + + #if USB_CFG_BC == USB_CFG_ENABLE + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + #define USB_BC_DCD_TIME (600U) + #define USB_BC_DCD_DBNC (11U) + #define USB_BC_VDPSRC_ON (42U) + #define USB_BC_VDMSRC_DIS (22U) + #define USB_BC_VDMSRC_ON (42U) + + #define USB_BC_DCD_TIMEOUT (0U) + #define USB_BC_DCD_COMP_SE0 (1U) + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/* There is no typedef definition. */ + +/****************************************************************************** + * Exported global variables and functions (to be accessed by other files) + ******************************************************************************/ + +/* variables */ +uint16_t g_usb_bc_detect; + +/* functions */ +void usb_pstd_bc_detect_process(usb_utr_t * p_utr); + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ + +/* functions */ +uint8_t usb_pstd_bc_data_contact_detect(usb_utr_t * p_utr); +uint8_t usb_pstd_bc_primary_detection(usb_utr_t * p_utr); +uint8_t usb_pstd_bc_secondary_detection(usb_utr_t * p_utr); + +/****************************************************************************** + * Imported global variables and functions (from other files) + ******************************************************************************/ + +/****************************************************************************** + * Renesas Abstracted USB peripheral battery charging driver functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_bc_detect_process + * Description : Charging Port Detect Process + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_bc_detect_process (usb_utr_t * p_utr) +{ + usb_instance_ctrl_t ctrl; + + usb_pstd_bc_data_contact_detect(p_utr); + + if (usb_pstd_bc_primary_detection(p_utr)) + { + if (usb_pstd_bc_secondary_detection(p_utr)) + { + g_usb_bc_detect = USB_BCPORT_DCP; + } + else + { + g_usb_bc_detect = USB_BCPORT_CDP; + } + + ctrl.module_number = p_utr->ip; + usb_set_event(USB_STATUS_BC, &ctrl); + } + else + { + g_usb_bc_detect = USB_BCPORT_SDP; + } +} /* End of function usb_pstd_bc_detect_process() */ + +/****************************************************************************** + * Function Name : usb_pstd_bc_data_contact_detect + * Description : Data Contact Detect + * Arguments : none + * Return value : uint8_t : DCD Complete Status + ******************************************************************************/ +uint8_t usb_pstd_bc_data_contact_detect (usb_utr_t * p_utr) +{ + uint16_t buf; + uint16_t timer = 0; + + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_set_cnen(p_utr->ip); + hw_usb_set_bcctrl(p_utr, USB_IDPSRCE); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + usb_cpu_delay_xms((uint16_t) 5); /* wait stabilization */ + + /* WAIT_LOOP */ + while (timer < USB_BC_DCD_TIME) /* [BC1.2 Spec] DCD_TIMEOUT (300-900ms) */ + { + buf = hw_usb_read_syssts(p_utr); + if (USB_SE0 == (buf & USB_LNST)) + { + usb_cpu_delay_xms((uint16_t) USB_BC_DCD_DBNC); /* [BC1.2 Spec] DCD_DBNC (min:10ms) */ + timer = (uint16_t) (timer + USB_BC_DCD_DBNC); + buf = hw_usb_read_syssts(p_utr); + if (USB_SE0 == (buf & USB_LNST)) + { + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_clear_bcctrl(p_utr, USB_IDPSRCE); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + return USB_BC_DCD_COMP_SE0; /* Connected Data Line */ + } + } + + usb_cpu_delay_xms((uint16_t) 1); + timer++; + } + + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_clear_bcctrl(p_utr, USB_IDPSRCE); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + return USB_BC_DCD_TIMEOUT; /* DCD Timeout */ +} /* End of function usb_pstd_bc_data_contact_detect() */ + +/****************************************************************************** + * Function Name : usb_pstd_bc_primary_detection + * Description : Primary Detection + * Arguments : none + * Return value : uint8_t : Detection Port + ******************************************************************************/ +uint8_t usb_pstd_bc_primary_detection (usb_utr_t * p_utr) +{ + uint16_t buf; + uint8_t detect_port = 0; + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_set_bcctrl(p_utr, (USB_VDPSRCE | USB_IDMSINKE)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + usb_cpu_delay_xms((uint16_t) USB_BC_VDPSRC_ON); /* [BC1.2 Spec] TVDPSRC_ON (min:40ms) */ + buf = hw_usb_read_bcctrl(p_utr); + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_clear_bcctrl(p_utr, (USB_VDPSRCE | USB_IDMSINKE)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + usb_cpu_delay_xms((uint16_t) USB_BC_VDMSRC_DIS); /* [BC1.2 Spec] TVDMSRC_DIS (max:20ms) */ + + if (buf & USB_CHGDETSTS) + { + detect_port = 1; /* Detected Charging Port */ + } + else + { + detect_port = 0; /* Detected SDP */ + } + + return detect_port; +} /* End of function usb_pstd_bc_primary_detection() */ + +/****************************************************************************** + * Function Name : usb_pstd_secondary_detection + * Description : Secondary Detection + * Arguments : none + * Return value : uint8_t : Detection Port + ******************************************************************************/ +uint8_t usb_pstd_bc_secondary_detection (usb_utr_t * p_utr) +{ + uint16_t buf; + uint8_t detect_port = 0; + + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_set_bcctrl(p_utr, (USB_VDMSRCE | USB_IDPSINKE)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + usb_cpu_delay_xms((uint16_t) USB_BC_VDMSRC_ON); /* [BC1.2 Spec] TVDMSRC_ON (min:40ms) */ + buf = hw_usb_read_bcctrl(p_utr); + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_clear_bcctrl(p_utr, (USB_VDMSRCE | USB_IDPSINKE)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + if (buf & USB_PDDETSTS) + { + detect_port = 1; /* Detected DCP */ + } + else + { + detect_port = 0; /* Detected CDP */ + } + + return detect_port; +} /* End of function usb_pstd_secondary_detection() */ + + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pcontrolrw.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pcontrolrw.c new file mode 100644 index 0000000000..606241bddd --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pcontrolrw.c @@ -0,0 +1,192 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Renesas Abstracted Peripheral Control RW API functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_ctrl_read + * Description : Called by R_USB_PstdCtrlRead, see it for description. + * Arguments : uint32_t bsize : Read size in bytes. + * : uint8_t *table : Start address of read data buffer. + * Return value : uint16_t : USB_WRITESHRT/USB_WRITE_END/USB_WRITING/USB_FIFOERROR. + ******************************************************************************/ +uint16_t usb_pstd_ctrl_read (uint32_t bsize, uint8_t * table, usb_utr_t * p_utr) +{ + uint16_t end_flag; + + g_usb_pstd_pipe0_request = USB_ON; + + g_usb_pstd_data_cnt[USB_PIPE0] = bsize; + gp_usb_pstd_data[USB_PIPE0] = table; + + usb_cstd_chg_curpipe(p_utr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, (uint16_t) USB_ISEL); + + /* Buffer clear */ + hw_usb_set_bclr(p_utr, USB_CUSE); + + hw_usb_clear_status_bemp(p_utr, USB_PIPE0); + + /* Peripheral Control sequence */ + end_flag = usb_pstd_write_data(USB_PIPE0, USB_CUSE, p_utr); + + /* Peripheral control sequence */ + switch (end_flag) + { + /* End of data write */ + case USB_WRITESHRT: + { + /* Enable not ready interrupt */ + usb_cstd_nrdy_enable(p_utr, (uint16_t) USB_PIPE0); + + /* Set PID=BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + break; + } + + /* End of data write (not null) */ + case USB_WRITEEND: + + /* Continue */ + /* Continue of data write */ + case USB_WRITING: + { + /* Enable empty interrupt */ + hw_usb_set_bempenb(p_utr, (uint16_t) USB_PIPE0); + + /* Enable not ready interrupt */ + usb_cstd_nrdy_enable(p_utr, (uint16_t) USB_PIPE0); + + /* Set PID=BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + + break; + } + + /* FIFO access error */ + case USB_FIFOERROR: + { + USB_PRINTF0("###usb_pstd_ctrl_read USB_FIFOERROR\n"); + break; + } + + default: + { + break; + } + } + + return end_flag; /* End or error or continue */ +} + +/****************************************************************************** + * End of function usb_pstd_ctrl_read + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_ctrl_write + * Description : Called by R_USB_PstdCtrlWrite, see it for description. + * Arguments : uint32_t bsize : Write size in bytes. + * : uint8_t *table : Start address of write data buffer. + * Return value : none + ******************************************************************************/ +void usb_pstd_ctrl_write (uint32_t bsize, uint8_t * table, usb_utr_t * p_utr) +{ + g_usb_pstd_pipe0_request = USB_ON; + + g_usb_pstd_data_cnt[USB_PIPE0] = bsize; + gp_usb_pstd_data[USB_PIPE0] = table; + + usb_cstd_chg_curpipe(p_utr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, USB_FALSE); + + /* Buffer clear */ + hw_usb_set_bclr(p_utr, USB_CUSE); + + /* Interrupt enable */ + /* Enable ready interrupt */ + hw_usb_set_brdyenb(p_utr, (uint16_t) USB_PIPE0); + + /* Enable not ready interrupt */ + usb_cstd_nrdy_enable(p_utr, (uint16_t) USB_PIPE0); + + /* Set PID=BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); +} + +/****************************************************************************** + * End of function usb_pstd_ctrl_write + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_ctrl_end + * Description : End control transfer + * Arguments : uint16_t status : Transfer end status + * Return value : none + ******************************************************************************/ +void usb_pstd_ctrl_end (uint16_t status, usb_utr_t * p_utr) +{ + g_usb_pstd_pipe0_request = USB_OFF; + g_usb_pstd_std_request = USB_NO; + + /* Interrupt disable */ + /* BEMP0 disable */ + hw_usb_clear_bempenb(p_utr, (uint16_t) USB_PIPE0); + + /* BRDY0 disable */ + hw_usb_clear_brdyenb(p_utr, (uint16_t) USB_PIPE0); + + /* NRDY0 disable */ + hw_usb_clear_nrdyenb(p_utr, (uint16_t) USB_PIPE0); + + if (USB_CFG_IP1 == p_utr->ip) + { + hw_usb_set_mbw(p_utr, USB_CUSE, USB1_CFIFO_MBW); + } + else /* if (USB_CFG_IP1 == p_utr->ip) */ + { + hw_usb_set_mbw(p_utr, USB_CUSE, USB0_CFIFO_MBW); + } + + if ((USB_DATA_ERR == status) || (USB_DATA_OVR == status)) + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + else if (USB_DATA_STOP == status) + { + /* Pipe stop */ + usb_cstd_set_nak(p_utr, (uint16_t) USB_PIPE0); + } + else + { + /* Set CCPL bit */ + hw_usb_pset_ccpl(p_utr->ip); + } +} + +/****************************************************************************** + * End of function usb_pstd_ctrl_end + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c new file mode 100644 index 0000000000..b245d7b370 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c @@ -0,0 +1,2604 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "inc/r_usb_basic_define.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS == 1) + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_api.h" + #if defined(USB_CFG_OTG_USE) + #if defined(USB_CFG_HCDC_USE) + #include "ux_host_class_cdc_acm.h" + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) + #include "ux_host_class_hid.h" + #include "ux_host_class_hid_keyboard.h" + #include "ux_host_class_hid_mouse.h" + #include "ux_host_class_hid_remote_control.h" + #endif /* defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HMSC_USE) + #include "ux_host_class_storage.h" + #endif /* defined(USB_CFG_HMSC_USE) */ + #endif /* defined(USB_CFG_OTG_USE) */ + #if defined(USB_CFG_PCDC_USE) + #include "r_usb_pcdc_cfg.h" + #endif /* defined(USB_CFG_PCDC_USE) */ +#endif /* #if (BSP_CFG_RTOS == 1) */ + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "../hw/inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/******************************************************************************* + * Macro definitions + ******************************************************************************/ + + #define USB_VALUE_100 (100) + #define USB_OTG_SE0_BRST (16) + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ + #if (BSP_CFG_RTOS != 0) +static void usb_pstd_interrupt(usb_utr_t * p_mess); + + #else /*(BSP_CFG_RTOS != 0)*/ +static void usb_pstd_interrupt(uint16_t type, uint16_t status, usb_cfg_t * p_cfg); + + #endif /*(BSP_CFG_RTOS != 0)*/ + + #if defined(USB_CFG_OTG_USE) +static void usb_pstd_otg_hnp_process(usb_utr_t * p_utr); +static void usb_pstd_otg_mode_to_host(usb_utr_t * p_utr); + + #endif /* defined(USB_CFG_OTG_USE) */ + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +uint16_t g_usb_pstd_config_num = 0; /* Current configuration number */ +uint16_t g_usb_pstd_alt_num[USB_ALT_NO]; /* Alternate number */ +#endif /* ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + +usb_cb_t g_usb_pstd_stall_cb; /* Stall Callback function */ +uint16_t g_usb_pstd_stall_pipe[USB_MAX_PIPE_NO + 1U]; /* Stall Pipe info */ +uint16_t g_usb_pstd_remote_wakeup = USB_FALSE; /* Remote wake up enable flag */ +uint16_t g_usb_pstd_remote_wakeup_state; /* Result for Remote wake up */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +uint16_t g_usb_pstd_test_mode_select; /* Test mode selectors */ +uint16_t g_usb_pstd_test_mode_flag = USB_FALSE; /* Test mode flag */ + +uint16_t g_usb_pstd_eptbl_index[2][USB_MAX_EP_NO + 1U]; /* Index of endpoint information table */ +uint16_t g_usb_pstd_req_type; /* Request type */ +uint16_t g_usb_pstd_req_value; /* Value */ +uint16_t g_usb_pstd_req_index; /* Index */ +uint16_t g_usb_pstd_req_length; /* Length */ + +uint16_t g_usb_pstd_pipe0_request; +uint16_t g_usb_pstd_std_request; +uint16_t g_usb_peri_connected; /* Status for USB connect. */ + +/* Driver registration */ +usb_pcdreg_t g_usb_pstd_driver; +usb_setup_t g_usb_pstd_req_reg; /* Device Request - Request structure */ + + #if (BSP_CFG_RTOS == 1) +uint8_t g_usb_peri_usbx_is_configured[USB_NUM_USBIP]; + #endif /* (BSP_CFG_RTOS == 1) */ + +volatile uint8_t g_usb_is_otg_attach_interrupt[USB_NUM_USBIP]; + + #if (BSP_CFG_RTOS == 1) +extern bool g_usb_peri_usbx_is_detach[USB_MAX_PIPE_NO + 1]; +extern bool g_usb_peri_usbx_is_fifo_error[USB_MAX_PIPE_NO + 1]; +extern TX_SEMAPHORE g_usb_peri_usbx_sem[USB_MAX_PIPE_NO + 1]; +extern UINT usb_host_usbx_initialize(UX_HCD * hcd); + + #if defined(USB_CFG_OTG_USE) +extern uint8_t g_is_usbx_otg_host_class_init[USB_NUM_USBIP]; +extern rtos_task_id_t g_hcd_tsk_hdl; +extern uint8_t g_usb_otg_suspend_flag[USB_NUM_USBIP]; + + #endif /* #if defined(USB_CFG_OTG_USE) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Renesas Abstracted Peripheral Driver functions + ******************************************************************************/ + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_pstd_interrupt + * Description : Analyze the USB Peripheral interrupt event and execute the + * : appropriate process. + * Arguments : uint16_t type : Interrupt type. + * : uint16_t status : BRDYSTS register & BRDYENB register. + * Return value : none + ******************************************************************************/ +static void usb_pstd_interrupt (uint16_t type, uint16_t status, usb_cfg_t * p_cfg) +{ + uint16_t stginfo; + usb_utr_t utr; + + utr.ip = p_cfg->module_number; + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + utr.p_transfer_rx = p_cfg->p_transfer_rx; + utr.p_transfer_tx = p_cfg->p_transfer_tx; + #endif + + /* check interrupt status */ + switch (type) + { + /* BRDY, BEMP, NRDY */ + case USB_INT_BRDY: + { + usb_pstd_brdy_pipe(&utr, status); + break; + } + + case USB_INT_BEMP: + { + usb_pstd_bemp_pipe(&utr, status); + break; + } + + case USB_INT_NRDY: + { + usb_pstd_nrdy_pipe(&utr, status); + break; + } + + /* Resume */ + case USB_INT_RESM: + { + USB_PRINTF0("RESUME int peri\n"); + + /* Callback */ + if (USB_NULL != g_usb_pstd_driver.devresume) + { + (*g_usb_pstd_driver.devresume)(&utr, USB_NO_ARG, USB_NULL); + } + + usb_pstd_resume_process(&utr); + break; + } + + /* VBUS */ + case USB_INT_VBINT: + { + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_set_cnen(p_cfg->module_number); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + if (USB_ATTACH == usb_pstd_chk_vbsts(utr.ip)) + { + USB_PRINTF0("VBUS int attach\n"); + usb_pstd_attach_process(&utr); /* USB attach */ + } + else + { + USB_PRINTF0("VBUS int detach\n"); + usb_pstd_detach_process(&utr); /* USB detach */ + } + + break; + } + + /* SOF */ + case USB_INT_SOFR: + { + /* User program */ + break; + } + + /* DVST */ + case USB_INT_DVST: + { + switch ((uint16_t) (status & USB_DVSQ)) + { + /* Power state */ + case USB_DS_POWR: + { + break; + } + + /* Default state */ + case USB_DS_DFLT: + { + USB_PRINTF0("USB-reset int peri\n"); + usb_pstd_bus_reset(&utr); + break; + } + + /* Address state */ + case USB_DS_ADDS: + { + break; + } + + /* Configured state */ + case USB_DS_CNFG: + { + USB_PRINTF0("Device configuration int peri\n"); + break; + } + + /* Power suspend state */ + case USB_DS_SPD_POWR: + + /* Continue */ + /* Default suspend state */ + case USB_DS_SPD_DFLT: + + /* Continue */ + /* Address suspend state */ + case USB_DS_SPD_ADDR: + + /* Continue */ + /* Configured Suspend state */ + case USB_DS_SPD_CNFG: + { + USB_PRINTF0("SUSPEND int peri\n"); + usb_pstd_suspend_process(&utr); + break; + } + + /* Error */ + default: + { + break; + } + } + + break; + } + + /* CTRT */ + case USB_INT_CTRT: + { + stginfo = (uint16_t) (status & USB_CTSQ); + if (USB_CS_IDST == stginfo) + { + /* check Test mode */ + if (USB_TRUE == g_usb_pstd_test_mode_flag) + { + /* Test mode */ + usb_pstd_test_mode(&utr); + } + } + else + { + if (((USB_CS_RDDS == stginfo) || (USB_CS_WRDS == stginfo)) || (USB_CS_WRND == stginfo)) + { + /* Save request register */ + usb_pstd_save_request(p_cfg->module_number); + } + } + + if (USB_STANDARD == (g_usb_pstd_req_type & USB_BMREQUESTTYPETYPE)) + { + /* Switch on the control transfer stage (CTSQ). */ + switch (stginfo) + { + /* Idle or setup stage */ + case USB_CS_IDST: + { + g_usb_pstd_pipe0_request = USB_OFF; + g_usb_pstd_std_request = USB_NO; + usb_pstd_stand_req0(&utr); + break; + } + + /* Control read data stage */ + case USB_CS_RDDS: + { + usb_pstd_stand_req1(&utr); + break; + } + + /* Control write data stage */ + case USB_CS_WRDS: + { + usb_pstd_stand_req2(&utr); + break; + } + + /* Status stage of a control write where there is no data stage. */ + case USB_CS_WRND: + { + usb_pstd_stand_req3(&utr); + break; + } + + /* Control read status stage */ + case USB_CS_RDSS: + { + usb_pstd_stand_req4(&utr); + break; + } + + /* Control write status stage */ + case USB_CS_WRSS: + { + usb_pstd_stand_req5(&utr); + break; + } + + /* Control sequence error */ + case USB_CS_SQER: + { + usb_pstd_ctrl_end((uint16_t) USB_DATA_ERR, &utr); + break; + } + + /* Illegal */ + default: + { + usb_pstd_ctrl_end((uint16_t) USB_DATA_ERR, &utr); + break; + } + } + } + else + { + /* Vender Specific */ + g_usb_pstd_req_reg.request_type = g_usb_pstd_req_type; + g_usb_pstd_req_reg.request_value = g_usb_pstd_req_value; + g_usb_pstd_req_reg.request_index = g_usb_pstd_req_index; + g_usb_pstd_req_reg.request_length = g_usb_pstd_req_length; + + /* Callback */ + if (USB_NULL != g_usb_pstd_driver.ctrltrans) + { + (*g_usb_pstd_driver.ctrltrans)(&g_usb_pstd_req_reg, stginfo, &utr); + } + } + + break; + } + + /* Error */ + case USB_INT_UNKNOWN: + { + /* USB_PRINTF0("pINT_UNKNOWN\n"); */ + break; + } + + default: + { + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_interrupt + ******************************************************************************/ + #endif /*(BSP_CFG_RTOS == 0)*/ + + #if (BSP_CFG_RTOS != 0) + +/****************************************************************************** + * Function Name : usb_pstd_interrupt + * Description : Analyze the USB Peripheral interrupt event and execute the + * : appropriate process. + * Arguments : uint16_t type : Interrupt type. + * : uint16_t status : BRDYSTS register & BRDYENB register. + * Return value : none + ******************************************************************************/ +static void usb_pstd_interrupt (usb_utr_t * p_mess) +{ + uint16_t stginfo; + uint16_t type; + uint16_t status; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t fifo_type; + + fifo_type = p_mess->status; + #endif + type = p_mess->keyword; + status = p_mess->status; + + /* check interrupt status */ + switch (type) + { + /* BRDY, BEMP, NRDY */ + case USB_INT_BRDY: + { + usb_pstd_brdy_pipe(p_mess, status); + break; + } + + case USB_INT_BEMP: + { + usb_pstd_bemp_pipe(p_mess, status); + break; + } + + case USB_INT_NRDY: + { + usb_pstd_nrdy_pipe(p_mess, status); + break; + } + + /* Resume */ + case USB_INT_RESM: + { + USB_PRINTF0("RESUME int peri\n"); + + /* Callback */ + if (USB_NULL != g_usb_pstd_driver.devresume) + { + (*g_usb_pstd_driver.devresume)(p_mess, USB_NO_ARG, USB_NULL); + } + + usb_pstd_resume_process(p_mess); + break; + } + + /* VBUS */ + case USB_INT_VBINT: + { + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_set_cnen(p_mess->ip); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + if (USB_ATTACH == usb_pstd_chk_vbsts(p_mess->ip)) + { + USB_PRINTF0("VBUS int attach\n"); + usb_pstd_attach_process(p_mess); /* USB attach */ + #if defined(USB_CFG_OTG_USE) + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_B; /* IDLE --> DEVICE_B */ + (*g_p_otg_callback[p_mess->ip])(UX_OTG_MODE_SLAVE); + #endif /* defined(USB_CFG_OTG_USE) */ + } + else + { + USB_PRINTF0("VBUS int detach\n"); + usb_pstd_detach_process(p_mess); /* USB detach */ + #if (BSP_CFG_RTOS == 1) + if (USB_YES == g_usb_peri_usbx_is_configured[p_mess->ip]) + { + _ux_device_stack_disconnect(); + g_usb_peri_usbx_is_configured[p_mess->ip] = USB_NO; + } + #endif /* (BSP_CFG_RTOS == 1) */ + + #if defined(USB_CFG_OTG_USE) + if (USB_YES == g_is_A_device[p_mess->ip]) + { + if (USB_YES == g_is_A_cable_detach[p_mess->ip]) + { + g_is_A_device[p_mess->ip] = USB_NO; + + /* A device and A cable detach --> Peri mode */ + g_is_A_cable_detach[p_mess->ip] = USB_NO; + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; /* A Device --> IDLE */ + (*g_p_otg_callback[p_mess->ip])(UX_OTG_MODE_IDLE); + } + else + { + /* B cable detach in A device --> Host mode */ + p_mess->ipp = usb_hstd_get_usb_ip_adr(p_mess->ip); + usb_pstd_otg_mode_to_host(p_mess); + if (USB_IP0 == p_mess->ip) + { + tx_timer_deactivate(&g_usb_otg_detach_timer); + } + + #if USB_NUM_USBIP == 2 + else + { + tx_timer_deactivate(&g_usb2_otg_detach_timer); + } + #endif /* USB_NUM_USBIP == 2 */ + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_A; + (*g_p_otg_callback[p_mess->ip])(UX_OTG_MODE_HOST); + } + } + else + { + /* B Device only */ + g_usb_otg_suspend_flag[p_mess->ip] = USB_NO; + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; + (*g_p_otg_callback[p_mess->ip])(UX_OTG_MODE_IDLE); + } + #endif /* defined(USB_CFG_OTG_USE) */ + } + + break; + } + + /* SOF */ + case USB_INT_SOFR: + { + /* User program */ + break; + } + + /* DVST */ + case USB_INT_DVST: + { + switch ((uint16_t) (status & USB_DVSQ)) + { + /* Power state */ + case USB_DS_POWR: + { + break; + } + + /* Default state */ + case USB_DS_DFLT: + { + USB_PRINTF0("USB-reset int peri\n"); + usb_pstd_bus_reset(p_mess); + break; + } + + /* Address state */ + case USB_DS_ADDS: + { + break; + } + + /* Configured state */ + case USB_DS_CNFG: + { + USB_PRINTF0("Device configuration int peri\n"); + break; + } + + /* Power suspend state */ + case USB_DS_SPD_POWR: + + /* Continue */ + /* Default suspend state */ + case USB_DS_SPD_DFLT: + + /* Continue */ + /* Address suspend state */ + case USB_DS_SPD_ADDR: + + /* Continue */ + /* Configured Suspend state */ + case USB_DS_SPD_CNFG: + #if defined(USB_CFG_OTG_USE) + { + if ((USB_NO == g_usb_otg_suspend_flag[p_mess->ip]) && + (USB_DS_SPD_POWR == (uint16_t) (status & USB_DVSQ))) + { + g_usb_otg_suspend_flag[p_mess->ip] = USB_YES; + break; + } + } + #endif /* defined (USB_CFG_OTG_USE) */ + { + USB_PRINTF0("SUSPEND int peri\n"); + + #if defined(USB_CFG_OTG_USE) + p_mess->ipp = usb_hstd_get_usb_ip_adr(p_mess->ip); /* Get the USB IP base address. */ + + if (USB_ON == g_usb_otg_hnp_process[p_mess->ip]) + { + usb_pstd_otg_hnp_process(p_mess); + } + else + #endif /* defined(USB_CFG_OTG_USE) */ + { + usb_pstd_suspend_process(p_mess); + } + + break; + } + + /* Error */ + default: + { + break; + } + } + + break; + } + + /* CTRT */ + case USB_INT_CTRT: + { + stginfo = (uint16_t) (status & USB_CTSQ); + if (USB_CS_IDST == stginfo) + { + /* check Test mode */ + if (USB_TRUE == g_usb_pstd_test_mode_flag) + { + /* Test mode */ + usb_pstd_test_mode(p_mess); + } + } + else + { + if (((USB_CS_RDDS == stginfo) || (USB_CS_WRDS == stginfo)) || (USB_CS_WRND == stginfo)) + { + /* Save request register */ + usb_pstd_save_request(p_mess->ip); + } + } + + if (USB_STANDARD == (g_usb_pstd_req_type & USB_BMREQUESTTYPETYPE)) + { + /* Switch on the control transfer stage (CTSQ). */ + switch (stginfo) + { + /* Idle or setup stage */ + case USB_CS_IDST: + { + usb_pstd_stand_req0(p_mess); + break; + } + + /* Control read data stage */ + case USB_CS_RDDS: + { + usb_pstd_stand_req1(p_mess); + break; + } + + /* Control write data stage */ + case USB_CS_WRDS: + { + usb_pstd_stand_req2(p_mess); + break; + } + + /* Status stage of a control write where there is no data stage. */ + case USB_CS_WRND: + { + usb_pstd_stand_req3(p_mess); + break; + } + + /* Control read status stage */ + case USB_CS_RDSS: + { + usb_pstd_stand_req4(p_mess); + break; + } + + /* Control write status stage */ + case USB_CS_WRSS: + { + usb_pstd_stand_req5(p_mess); + break; + } + + /* Control sequence error */ + case USB_CS_SQER: + { + usb_pstd_ctrl_end((uint16_t) USB_DATA_ERR, p_mess); + break; + } + + /* Illegal */ + default: + { + usb_pstd_ctrl_end((uint16_t) USB_DATA_ERR, p_mess); + break; + } + } + } + else + { + /* Vender Specific */ + g_usb_pstd_req_reg.request_type = g_usb_pstd_req_type; + g_usb_pstd_req_reg.request_value = g_usb_pstd_req_value; + g_usb_pstd_req_reg.request_index = g_usb_pstd_req_index; + g_usb_pstd_req_reg.request_length = g_usb_pstd_req_length; + + /* Callback */ + if (USB_NULL != g_usb_pstd_driver.ctrltrans) + { + (*g_usb_pstd_driver.ctrltrans)(&g_usb_pstd_req_reg, stginfo, p_mess); + } + } + + break; + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + case USB_INT_DXFIFO: + { + usb_cstd_dma_stop(p_mess, fifo_type); /* Stop DMA,FIFO access */ + usb_cstd_dma_send_continue(p_mess, fifo_type); + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + /* Error */ + case USB_INT_UNKNOWN: + { + /* USB_PRINTF0("pINT_UNKNOWN\n"); */ + break; + } + + default: + { + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_interrupt + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_OTG_USE) + +/****************************************************************************** + * Function Name : usb_pstd_otg_mode_to_host + * Description : Initialize regsister and driver from USB Peripheral to USB Host + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_otg_mode_to_host (usb_utr_t * p_utr) +{ + /* D+ Pullup Off */ + hw_usb_pclear_dprpu(p_utr->ip); + + /* D+ Pulldown On */ + hw_usb_set_drpd(p_utr); + + /* Change to Host mode */ + hw_usb_set_dcfm(p_utr); + + /* Peri UninItialization */ + usb_module_register_clear(p_utr->ip); + + usb_pstd_clr_pipe_table(p_utr->ip); + + /* Host Initialization */ + + /* Since this fuction's second parameter + * only process usb HOST mode + * pass USB_NULL in this case */ + usb_hdriver_init(p_utr, USB_NULL); + + g_usb_usbmode[p_utr->ip] = USB_MODE_HOST; + + /* Attach Interrupt Enable */ + hw_usb_hset_enb_attche(p_utr); +} + +/****************************************************************************** + * End of function usb_pstd_otg_mode_to_host + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_otg_hnp_process + * Description : Swap Process from USB Peripheral to USB Host + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_otg_hnp_process (usb_utr_t * p_utr) +{ + uint16_t i; + uint16_t usb_reg; + uint8_t is_otg_hnp_possible = USB_NO; + + p_utr->ipp = (usb_regadr_t) usb_hstd_get_usb_ip_adr(p_utr->ip); /* Get the USB IP base address. */ + + /* D+ Pullup Off */ + hw_usb_pclear_dprpu(p_utr->ip); + + g_usb_otg_hnp_counter = 0; + tx_timer_activate(&g_usb_otg_hnp_timer); + + /* Change to Host mode */ + hw_usb_set_dcfm(p_utr); + + /* D+ Pulldown On */ + hw_usb_set_drpd(p_utr); + + g_usb_usbmode[p_utr->ip] = USB_MODE_HOST; + + _ux_utility_thread_suspend(&g_hcd_tsk_hdl); + + for (i = 0; i < USB_VALUE_100; i++) + { + /* Wait 3ms */ + usb_cpu_delay_xms((uint16_t) 1); + if (USB_ATTCH == (p_utr->ipp->INTSTS1 & USB_ATTCH)) + { + break; + } + } + + /* Attach Interrupt Enable */ + hw_usb_hset_enb_attche(p_utr); + + /* Wait 3ms */ + usb_cpu_delay_xms((uint16_t) 3); + + g_usb_otg_hnp_counter = 0; + if (g_usb_otg_hnp_counter <= USB_OTG_SE0_BRST) + { + is_otg_hnp_possible = USB_YES; + } + + tx_timer_deactivate(&g_usb_otg_hnp_timer); + + if (((USB_YES == g_usb_is_otg_attach_interrupt[p_utr->ip]) || + ((USB_YES == g_is_A_device[p_utr->ip]) && (USB_NO == g_is_A_cable_detach[p_utr->ip]))) && + (USB_YES == is_otg_hnp_possible)) + { + g_usb_is_otg_attach_interrupt[p_utr->ip] = USB_NO; + is_otg_hnp_possible = USB_NO; + + /* USB Peripheral --> USB Host */ + + /* Peri UninItialization */ + usb_module_register_clear(p_utr->ip); + + usb_pstd_clr_pipe_table(p_utr->ip); + + _ux_device_stack_disconnect(); + + /* Host Initialization */ + + /* Since this fuction's second parameter + * only process usb HOST mode + * pass USB_NULL in this case */ + usb_hdriver_init(p_utr, USB_NULL); + + if (USB_NO == g_is_usbx_otg_host_class_init[p_utr->ip]) + { + #if defined(USB_CFG_HCDC_USE) + ux_host_stack_class_register(_ux_system_host_class_cdc_acm_name, ux_host_class_cdc_acm_entry); + if (USB_IP1 == p_utr->ip) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hcdc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hcdc_fs", usb_host_usbx_initialize, R_USB_FS0_BASE, 0); + } + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HMSC_USE) + ux_host_stack_class_register(_ux_system_host_class_storage_name, ux_host_class_storage_entry); + if (USB_IP1 == p_utr->ip) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hmsc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hmsc_fs", usb_host_usbx_initialize, R_USB_FS0_BASE, 0); + } + #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HHID_USE) + ux_host_stack_class_register(_ux_system_host_class_hid_name, ux_host_class_hid_entry); + + ux_host_class_hid_client_register(_ux_system_host_class_hid_client_keyboard_name, + ux_host_class_hid_keyboard_entry); + ux_host_class_hid_client_register(_ux_system_host_class_hid_client_mouse_name, + ux_host_class_hid_mouse_entry); + + if (USB_IP1 == p_utr->ip) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hhid_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_hhid_fs", usb_host_usbx_initialize, R_USB_FS0_BASE, 0); + } + #endif /* defined(USB_CFG_HHID_USE) */ + + g_is_usbx_otg_host_class_init[p_utr->ip] = USB_YES; + } + + (*g_p_otg_callback[p_utr->ip])(UX_OTG_MODE_HOST); + + p_utr->ipp->INTENB1 &= (uint16_t) (~(uint16_t) USB_ATTCHE); + p_utr->ipp->INTENB1 |= (uint16_t) (USB_ATTCHE); + } + else + { + /* There is no Attach interrupt */ + + /* Host Uinitialization */ + usb_module_register_clear(p_utr->ip); + + /* D+ Pullup Off */ + hw_usb_pclear_dprpu(p_utr->ip); + + /* D+ Pulldown Off */ + hw_usb_clear_drpd(p_utr); + + /* Change to Peri mode */ + hw_usb_clear_dcfm(p_utr); + + /* D+ Pullup On */ + hw_usb_pset_dprpu(p_utr->ip); + + g_usb_usbmode[p_utr->ip] = USB_MODE_PERI; + + p_utr->ipp->INTENB0 = (USB_BEMPE | USB_BRDYE | USB_VBSE | USB_DVSE | USB_CTRE); + + if (USB_YES == g_is_A_device[p_utr->ip]) + { + usb_reg = hw_usb_read_syssts(p_utr); + if (0 == (usb_reg & USB_IDMON)) + { + (*g_p_otg_callback[p_utr->ip])(UX_OTG_MODE_SLAVE); + } + else + { + (*g_p_otg_callback[p_utr->ip])(UX_OTG_MODE_IDLE); + } + } + else + { + usb_reg = hw_usb_read_intsts(p_utr->ip); + if (USB_VBSTS == (usb_reg & USB_VBSTS)) + { + (*g_p_otg_callback[p_utr->ip])(UX_OTG_MODE_SLAVE); + } + else + { + (*g_p_otg_callback[p_utr->ip])(UX_OTG_MODE_IDLE); + } + } + } + + _ux_utility_thread_resume(&g_hcd_tsk_hdl); + + g_usb_otg_hnp_process[p_utr->ip] = USB_OFF; +} + + #endif /* defined(USB_CFG_OTG_USE) */ + #endif /* BSP_CFG_RTOS == 1 */ + + #endif /*(BSP_CFG_RTOS != 0)*/ + +/****************************************************************************** + * End of function usb_pstd_otg_hnp_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_pcd_task + * Description : The Peripheral Control Driver(PCD) task. + * Arguments : none + * Return value : none + ******************************************************************************/ + #if (BSP_CFG_RTOS == 1) +void usb_pstd_pcd_task (ULONG entry_input) + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_pstd_pcd_task (void) + #endif /* #if (BSP_CFG_RTOS == 1) */ +{ + #if (BSP_CFG_RTOS == 1) + (void) entry_input; + #endif /* #if (BSP_CFG_RTOS == 1) */ + #if (BSP_CFG_RTOS == 0) + if (g_usb_pstd_usb_int.wp != g_usb_pstd_usb_int.rp) + { + /* Pop Interrupt info */ + usb_pstd_interrupt(g_usb_pstd_usb_int.buf[g_usb_pstd_usb_int.rp].type, + g_usb_pstd_usb_int.buf[g_usb_pstd_usb_int.rp].status, + g_usb_pstd_usb_int.buf[g_usb_pstd_usb_int.rp].p_cfg); + + /* Read CountUp */ + g_usb_pstd_usb_int.rp = (uint8_t) ((uint8_t) (g_usb_pstd_usb_int.rp + 1) % USB_INT_BUFSIZE); + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + usb_cstd_dma_driver(); /* USB DMA driver */ + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + #endif /*(BSP_CFG_RTOS == 0)*/ + + #if (BSP_CFG_RTOS != 0) + usb_er_t err; + usb_utr_t * p_mess; + + /* WAIT_LOOP */ + while (1) + { + err = USB_TRCV_MSG(USB_PCD_MBX, (usb_msg_t **) &p_mess, (usb_tm_t) 1000); + if (USB_OK == err) + { + switch (p_mess->msginfo) + { + case USB_MSG_PCD_INT: + { + usb_pstd_interrupt(p_mess); + break; + } + + case USB_MSG_PCD_SUBMITUTR: + { + usb_pstd_set_submitutr(p_mess); + break; + } + + case USB_MSG_PCD_TRANSEND1: + { + usb_pstd_forced_termination(p_mess->keyword, (uint16_t) USB_DATA_STOP, p_mess); + break; + } + + case USB_MSG_PCD_REMOTEWAKEUP: + { + usb_pstd_self_clock(p_mess->ip); + usb_pstd_remote_wakeup(p_mess->ip); + break; + } + + default: + { + break; + } + } + } + } + #endif /*(BSP_CFG_RTOS != 0)*/ +} + +/****************************************************************************** + * End of function usb_pstd_pcd_task + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_submitutr + * Description : USB Peripheral Submit utr. + * Arguments : usb_utr_t *utrmsg : Pointer to usb_utr_t structure + * Return value : usb_er_t + ******************************************************************************/ +usb_er_t usb_pstd_set_submitutr (usb_utr_t * utrmsg) +{ + uint16_t pipenum; + + pipenum = utrmsg->keyword; + + #if (BSP_CFG_RTOS == 0) + g_p_usb_pstd_pipe[pipenum] = utrmsg; + #endif /* (BSP_CFG_RTOS == 0) */ + + /* Check state (Configured) */ + if (USB_TRUE == usb_pstd_chk_configured(utrmsg)) + { + #if (BSP_CFG_RTOS != 0) + if (USB_NULL != g_p_usb_pstd_pipe[pipenum]) + { + usb_cstd_pipe_msg_forward(utrmsg, pipenum); + + return USB_OK; + } + #endif /* (BSP_CFG_RTOS != 0) */ + + #if (BSP_CFG_RTOS != 0) + g_p_usb_pstd_pipe[pipenum] = utrmsg; + #endif /* (BSP_CFG_RTOS != 0) */ + + /* Data transfer */ + if (USB_DIR_P_OUT == usb_cstd_get_pipe_dir(utrmsg, pipenum)) + { + usb_pstd_receive_start(pipenum); /* Out transfer */ + } + else + { + /* In transfer */ + usb_pstd_send_start(pipenum); + } + } + else + { + #if (BSP_CFG_RTOS != 0) + if (USB_PIPE0 == pipenum) + { + usb_cstd_pipe0_msg_clear(utrmsg, 0); + } + else + { + usb_cstd_pipe_msg_clear(utrmsg, pipenum); + } + + #else /* (BSP_CFG_RTOS != 0) */ + /* Transfer stop */ + usb_pstd_forced_termination(pipenum, (uint16_t) USB_DATA_ERR, utrmsg); + #endif /* (BSP_CFG_RTOS != 0) */ + } + + return USB_OK; +} + +/****************************************************************************** + * End of function usb_pstd_set_submitutr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_clr_alt + * Description : Zero-clear the alternate table (buffer). + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_clr_alt (void) +{ + uint16_t i; + + /* WAIT_LOOP */ + for (i = 0; i < USB_ALT_NO; ++i) + { + /* Alternate table clear */ + g_usb_pstd_alt_num[i] = 0; + } +} + +/****************************************************************************** + * End of function usb_pstd_clr_alt + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_clr_mem + * Description : Initialize global variables defined for peripheral mode. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_clr_mem (void) +{ + g_usb_pstd_config_num = 0; /* Configuration number */ + g_usb_pstd_remote_wakeup = USB_FALSE; /* Remote wake up enable flag */ + usb_pstd_clr_alt(); /* Alternate setting clear */ +} + +/****************************************************************************** + * End of function usb_pstd_clr_mem + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_config_num + * Description : Set specified configuration number. + * Arguments : uint16_t value : Configuration number + * Return value : none + ******************************************************************************/ +void usb_pstd_set_config_num (uint16_t value) +{ + g_usb_pstd_config_num = value; /* Set configuration number */ + usb_pstd_clr_alt(); /* Alternate setting clear */ +} + +/****************************************************************************** + * End of function usb_pstd_set_config_num + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_clr_eptbl_index + * Description : Clear Endpoint Index Table (buffer). + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_clr_eptbl_index (void) +{ + uint16_t i; + + /* WAIT_LOOP */ + for (i = 0; i <= USB_MAX_EP_NO; ++i) + { + /* EndPoint index table clear */ + g_usb_pstd_eptbl_index[0][i] = USB_ERROR; + g_usb_pstd_eptbl_index[1][i] = USB_ERROR; + } +} + +/****************************************************************************** + * End of function usb_pstd_clr_eptbl_index + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_get_interface_num + * Description : Get interface number + * Arguments : void + * Return value : uint16_t : Number of this interface(bNumInterfaces) + ******************************************************************************/ +uint16_t usb_pstd_get_interface_num (void) +{ + uint16_t num_if = 0; + + /* Get NumInterfaces. 4:bNumInterfaces */ + num_if = *(g_usb_pstd_driver.p_configtbl + USB_DEV_B_NUM_INTERFACES); + + return num_if; +} + +/****************************************************************************** + * End of function usb_pstd_get_interface_num + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_get_alternate_num + * Description : Get Alternate Setting Number + * Arguments : uint16_t con_num : Configuration Number + * : uint16_t int_num : Interface Number + * Return value : uint16_t : Value used to select this alternate (bAlternateSetting) + ******************************************************************************/ +uint16_t usb_pstd_get_alternate_num (uint16_t int_num) +{ + uint16_t i; + uint16_t alt_num = 0; + uint8_t * ptr; + uint16_t length; + + ptr = g_usb_pstd_driver.p_configtbl; + i = ptr[0]; + + /* Interface descriptor[0] */ + ptr = (uint8_t *) ((uint32_t) ptr + ptr[0]); + length = (uint16_t) (*(uint8_t *) ((uint32_t) g_usb_pstd_driver.p_configtbl + (uint16_t) 2U)); + length |= (uint16_t) ((uint16_t) (*(uint8_t *) ((uint32_t) g_usb_pstd_driver.p_configtbl + (uint16_t) 3U)) << 8U); + + /* Search descriptor table size */ + /* WAIT_LOOP */ + for ( ; i < length; ) + { + /* Descriptor type ? */ + switch (ptr[1]) + { + /* Interface */ + case USB_DT_INTERFACE: + { + if (int_num == ptr[2]) + { + /* Alternate number count */ + alt_num = (uint16_t) ptr[3]; + } + + i = (uint16_t) (i + ptr[0]); + + /* Interface descriptor[0] */ + ptr = (uint8_t *) ((uint32_t) ptr + ptr[0]); + break; + } + + /* Device */ + case USB_DT_DEVICE: + + /* Continue */ + /* Configuration */ + case USB_DT_CONFIGURATION: + + /* Continue */ + /* String */ + case USB_DT_STRING: + + /* Continue */ + /* EndPoint */ + case USB_DT_ENDPOINT: + + /* Continue */ + /* Class, Vendor, else */ + default: + { + i = (uint16_t) (i + ptr[0]); + + /* Interface descriptor[0] */ + ptr = (uint8_t *) ((uint32_t) ptr + ptr[0]); + break; + } + } + } + + return alt_num; +} + +/****************************************************************************** + * End of function usb_pstd_get_alternate_num + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_eptbl_index + * Description : Set endpoint index in table (buffer) region based on config- + * : uration descriptor. In other words, set which endpoints to + * : use based on specified configuration, + * Arguments : uint16_t con_num : Configuration Number. + * : uint16_t int_num : Interface Number. + * : uint16_t alt_num : Alternate Setting. + * Return value : none + ******************************************************************************/ +void usb_pstd_set_eptbl_index (uint16_t int_num, uint16_t alt_num) +{ + uint8_t * ptr; + uint16_t i; + uint16_t j; + uint16_t length; + uint16_t start; + uint16_t numbers; + uint16_t ep; + uint16_t dir; + + /* Configuration descriptor */ + ptr = g_usb_pstd_driver.p_configtbl; + i = *ptr; + length = (uint16_t) (*(uint8_t *) ((uint32_t) ptr + (uint32_t) 3U)); + length = (uint16_t) (length << 8); + length = (uint16_t) (length + (uint16_t) (*(uint8_t *) ((uint32_t) ptr + (uint32_t) 2U))); + ptr = (uint8_t *) ((uint32_t) ptr + (*ptr)); + start = 0; + numbers = 0; + j = 0; + + /* WAIT_LOOP */ + for ( ; i < length; ) + { + /* Descriptor type ? */ + switch (*(uint8_t *) ((uint32_t) ptr + (uint32_t) 1U)) + { + /* Interface */ + case USB_DT_INTERFACE: + { + if (((*(uint8_t *) ((uint32_t) ptr + (uint32_t) 2U)) == int_num) && + ((*(uint8_t *) ((uint32_t) ptr + (uint32_t) 3U)) == alt_num)) + { + numbers = *(uint8_t *) ((uint32_t) ptr + (uint32_t) 4U); + } + else + { + start = (uint16_t) (start + (uint16_t) (*(uint8_t *) ((uint32_t) ptr + (uint32_t) 4U))); + } + + i = (uint8_t) (i + (*ptr)); + ptr = (uint8_t *) ((uint32_t) ptr + (*ptr)); + break; + } + + /* Endpoint */ + case USB_DT_ENDPOINT: + { + if (j < numbers) + { + ep = (uint16_t) *(uint8_t *) ((uint32_t) ptr + (uint32_t) 2U); + if (USB_EP_IN == (ep & USB_EP_DIRMASK)) + { + dir = 1; /* IN */ + } + else + { + dir = 0; /* OUT */ + } + + ep &= (uint16_t) 0x0f; + g_usb_pstd_eptbl_index[dir][ep] = (uint8_t) (start + j); + ++j; + } + + i = (uint16_t) (i + (*ptr)); + ptr = (uint8_t *) ((uint32_t) ptr + (*ptr)); + break; + } + + /* Device */ + case USB_DT_DEVICE: + + /* Continue */ + /* Configuration */ + case USB_DT_CONFIGURATION: + + /* Continue */ + /* String */ + case USB_DT_STRING: + + /* Continue */ + /* Class, Vendor, else */ + default: + { + i = (uint16_t) (i + (*ptr)); + ptr = (uint8_t *) ((uint32_t) ptr + (*ptr)); + break; + } + } + } +} + +/****************************************************************************** + * End of function usb_pstd_set_eptbl_index + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_chk_remote + * Description : Check if the RemoteWakeUp bit for the configuration descriptor is set. + * Arguments : none + * Return value : uint16_t : remote wakeup status (TRUE/FALSE). + ******************************************************************************/ +uint16_t usb_pstd_chk_remote (void) +{ + uint8_t atr; + + if (0 == g_usb_pstd_config_num) + { + return USB_FALSE; + } + + /* Get Configuration Descriptor - bmAttributes */ + atr = *(uint8_t *) ((uint32_t) g_usb_pstd_driver.p_configtbl + (uint32_t) 7U); + + /* Remote WakeUp check(= D5) */ + if (USB_CF_RWUPON == (atr & USB_CF_RWUPON)) + { + return USB_TRUE; + } + + return USB_FALSE; +} + +/****************************************************************************** + * End of function usb_pstd_chk_remote + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_get_current_power + * Description : Find out how the peripheral is powered by looking at the con- + * : figuration descriptor. + * Arguments : none + * Return value : uint8_t : Current power means; self-powered or bus-powered + * : (GS_SELFPOWERD/GS_BUSPOWERD). + ******************************************************************************/ +uint8_t usb_pstd_get_current_power (void) +{ + /* + * Please answer the currently power of your system. + */ + + uint8_t tmp; + uint8_t currentpower; + + /* Standard configuration descriptor */ + tmp = *(uint8_t *) ((uint32_t) g_usb_pstd_driver.p_configtbl + (uint32_t) 7U); + if (USB_CF_SELFP == (tmp & USB_CF_SELFP)) + { + /* Self Powered */ + currentpower = USB_GS_SELFPOWERD; + } + else + { + /* Bus Powered */ + currentpower = USB_GS_BUSPOWERD; + } + + /* Check currently powered */ + + return currentpower; +} + +/****************************************************************************** + * End of function usb_pstd_get_current_power + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_fifo_to_buf + * Description : Request readout from USB FIFO to buffer and process depending + * : on status; read complete or reading. + * Arguments : uint16_t pipe : Pipe no. + * : uint16_t useport : FIFO select(USB_CUSE,USB_DMA0,....) + * Return value : none + ******************************************************************************/ +void usb_pstd_fifo_to_buf (uint16_t pipe, uint16_t useport, usb_utr_t * p_utr) +{ + uint16_t end_flag = USB_ERROR; + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + end_flag = usb_pstd_read_data(pipe, useport, p_utr); + + /* Check FIFO access sequence */ + switch (end_flag) + { + case USB_READING: + { + /* Continue of data read */ + break; + } + + case USB_READEND: + { + /* End of data read */ + usb_pstd_data_end(pipe, (uint16_t) USB_DATA_OK, p_utr); + break; + } + + case USB_READSHRT: + { + /* End of data read */ + usb_pstd_data_end(pipe, (uint16_t) USB_DATA_SHT, p_utr); + break; + } + + case USB_READOVER: + { + /* Buffer over */ + USB_PRINTF1("### Receive data over PIPE%d\n", pipe); + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_OVR, p_utr); + break; + } + + case USB_FIFOERROR: + { + /* FIFO access error */ + USB_PRINTF0("###usb_pstd_fifo_to_buf FIFO access error \n"); + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_FIFO_ERR, p_utr); + break; + } + + default: + { + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_ERR, p_utr); + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_fifo_to_buf + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_buf_to_fifo + * Description : Set USB registers as required to write from data buffer to USB + * : FIFO, to have USB FIFO to write data to bus. + * Arguments : uint16_t pipe : Pipe no. + * : uint16_t useport : Port no. + * Return value : none + ******************************************************************************/ +void usb_pstd_buf_to_fifo (uint16_t pipe, uint16_t useport, usb_utr_t * p_utr) +{ + uint16_t end_flag; + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Disable Ready Interrupt */ + hw_usb_clear_brdyenb(p_utr, pipe); + + end_flag = usb_pstd_write_data(pipe, useport, p_utr); + + /* Check FIFO access sequence */ + switch (end_flag) + { + case USB_WRITING: + { + /* Continue of data write */ + /* Enable Ready Interrupt */ + hw_usb_set_brdyenb(p_utr, pipe); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(p_utr, pipe); + break; + } + + case USB_WRITEEND: + + /* End of data write */ + /* continue */ + case USB_WRITESHRT: + { + /* End of data write */ + /* Enable Empty Interrupt */ + hw_usb_set_bempenb(p_utr, pipe); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(p_utr, pipe); + break; + } + + case USB_FIFOERROR: + { + /* FIFO access error */ + USB_PRINTF0("###usb_pstd_buf_to_fifo FIFO access error \n"); + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_FIFO_ERR, p_utr); + break; + } + + default: + { + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_ERR, p_utr); + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_buf_to_fifo + ******************************************************************************/ + + #if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_pstd_transfer_start + * Description : Transfer the data of each pipe + * : Request PCD to transfer data, and the PCD transfers the data + * : based on the transfer information stored in ptr + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : usb_er_t : Error info. + ******************************************************************************/ +usb_er_t usb_pstd_transfer_start (usb_utr_t * ptr) +{ + usb_er_t err; + uint16_t pipenum; + #if (BSP_CFG_RTOS != 0) + usb_utr_t * p_tran_data; + #endif /* (BSP_CFG_RTOS != 0) */ + + #if (BSP_CFG_RTOS == 1) + #if (defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE)) + UINT status; + CHAR * p_sem_name; + ULONG cur_sem_count_value; + TX_THREAD * p_suspend_thread; + ULONG suspend_t_count; + TX_SEMAPHORE * p_next_sem; + #endif /* (defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE) */ + #endif /* #if (BSP_CFG_RTOS == 1) */ + + pipenum = ptr->keyword; + if (USB_PIPE0 == pipenum) + { + USB_PRINTF0("### usb_pstd_transfer_start PIPE0 is not support\n"); + + return USB_ERROR; + } + + #if (BSP_CFG_RTOS == 0) + if (USB_NULL != g_p_usb_pstd_pipe[pipenum]) + { + /* Get PIPE TYPE */ + if (USB_TYPFIELD_ISO != usb_cstd_get_pipe_type(ptr, pipenum)) + { + USB_PRINTF1("### usb_pstd_transfer_start overlaps %d\n", pipenum); + + return USB_QOVR; + } + } + + /* Check state (Configured) */ + if (USB_TRUE != usb_pstd_chk_configured(ptr)) + { + USB_PRINTF0("### usb_pstd_transfer_start not configured\n"); + + return USB_ERROR; + } + + err = usb_pstd_set_submitutr(ptr); + #else /* (BSP_CFG_RTOS == 0) */ + #if (BSP_CFG_RTOS == 1) /* BSP_CFG_RTOS == 0 */ + ptr->msghead = (usb_mh_t) USB_NULL; + ptr->msginfo = USB_MSG_PCD_SUBMITUTR; + + err = USB_PGET_BLK(1, &p_tran_data, ptr->ip); + if (TX_SUCCESS != err) + { + USB_PRINTF0("### usb_pstd_transfer_start USB_PGET_BLK ERROR\n"); + + return USB_ERROR; + } + + #elif (BSP_CFG_RTOS == 2) /* BSP_CFG_RTOS == 0 */ + ptr->msghead = (usb_mh_t) USB_NULL; + ptr->msginfo = USB_MSG_PCD_SUBMITUTR; + + p_tran_data = (usb_utr_t *) pvPortMalloc(sizeof(usb_utr_t)); + if (NULL == p_tran_data) + { + USB_PRINTF0("### usb_pstd_transfer_start pvPortMalloc ERROR\n"); + + return USB_ERROR; + } + #endif /* (BSP_CFG_RTOS == 0) */ + + *p_tran_data = *ptr; + #if (BSP_CFG_RTOS == 1) + p_tran_data->cur_task_hdl = tx_thread_identify(); + g_usb_peri_usbx_is_fifo_error[pipenum] = USB_NO; + #if defined(USB_CFG_PCDC_USE) && defined(USB_CFG_PMSC_USE) + if ((g_usb_pcdc_bulk_in_pipe[ptr->ip] == pipenum) || (g_usb_pcdc_bulk_out_pipe[ptr->ip] == pipenum)) + { + status = tx_semaphore_info_get(&g_usb_peri_usbx_sem[pipenum], + &p_sem_name, + &cur_sem_count_value, + &p_suspend_thread, + &suspend_t_count, + &p_next_sem); + if (TX_SUCCESS == status) + { + /* Check IOCTL timeout value has been set to the transfer request + * and check if transfer request semaphore count value is got + * incremented, due to the previous transfer request timeout. + * If both conditions true, then clear the previous transfer request semaphore, + * before starting current transfer request. */ + if ((TX_WAIT_FOREVER != ptr->timeout) && (cur_sem_count_value > 0)) + { + /* Clear the previous transfer request semaphore,if timeout has occurred. */ + tx_semaphore_get(&g_usb_peri_usbx_sem[pipenum], TX_NO_WAIT); + } + } + } + + #elif (defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE)) + status = tx_semaphore_info_get(&g_usb_peri_usbx_sem[pipenum], + &p_sem_name, + &cur_sem_count_value, + &p_suspend_thread, + &suspend_t_count, + &p_next_sem); + if (TX_SUCCESS == status) + { + /* Check IOCTL timeout value has been set to the transfer request + * and check if transfer request semaphore count value is got + * incremented, due to the previous transfer request timeout. + * If both conditions true, then clear the previous transfer request semaphore, + * before starting current transfer request. */ + if ((TX_WAIT_FOREVER != ptr->timeout) && (cur_sem_count_value > 0)) + { + /* Clear the previous transfer request semaphore,if timeout has occurred. */ + tx_semaphore_get(&g_usb_peri_usbx_sem[pipenum], TX_NO_WAIT); + } + } + #endif /* defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE) */ + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + p_tran_data->cur_task_hdl = xTaskGetCurrentTaskHandle(); + #endif /* (BSP_CFG_RTOS == 1) */ + + /* Send message */ + err = USB_SND_MSG(USB_PCD_MBX, (usb_msg_t *) p_tran_data); + if (USB_OK != err) + { + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, p_tran_data); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + vPortFree(p_tran_data); + #endif /* (BSP_CFG_RTOS == 1) */ + } + + #if (BSP_CFG_RTOS == 1) + if (0 != pipenum) + { + #if defined(USB_CFG_PCDC_USE) && defined(USB_CFG_PMSC_USE) + if ((g_usb_pcdc_bulk_in_pipe[ptr->ip] == pipenum) || (g_usb_pcdc_bulk_out_pipe[ptr->ip] == pipenum)) + { + UINT tx_err; + + /* Wait for the transfer request semaphore to wake up */ + tx_err = tx_semaphore_get(&g_usb_peri_usbx_sem[pipenum], p_tran_data->timeout); + + /* Check the error status code, and if this transfer is not successful end this + * transfer and return error code to the caller function.*/ + if (TX_SUCCESS != tx_err) + { + /* Set transfer request timeout status */ + p_tran_data->is_timeout = USB_YES; + + /* Once Time out occurs for this transfer request, terminate data transmission + * or reception. */ + usb_pstd_forced_termination(pipenum, (uint16_t) USB_DATA_STOP, p_tran_data); + USB_REL_BLK(1, p_tran_data); + err = USB_ERR_TMOUT; + } + else + { + /* Check for the FIFO error flag status */ + if (USB_YES == g_usb_peri_usbx_is_fifo_error[pipenum]) + { + g_usb_peri_usbx_is_fifo_error[pipenum] = USB_NO; + err = USB_ERR_FIFO_ACCESS; + } + } + } + else + { + tx_semaphore_get(&g_usb_peri_usbx_sem[pipenum], TX_WAIT_FOREVER); + } + + #elif defined(USB_CFG_PPRN_USE) + UINT tx_err; + tx_err = tx_semaphore_get(&g_usb_peri_usbx_sem[pipenum], p_tran_data->timeout); + if (TX_SUCCESS != tx_err) + { + p_tran_data->is_timeout = USB_YES; + err = usb_pstd_transfer_end(p_tran_data, pipenum); + if (USB_OK != err) + { + USB_REL_BLK(1, p_tran_data); + } + + err = USB_ERR_TMOUT; + } + else + { + if (USB_YES == g_usb_peri_usbx_is_fifo_error[pipenum]) + { + g_usb_peri_usbx_is_fifo_error[pipenum] = USB_NO; + err = USB_ERR_FIFO_ACCESS; + } + } + + #elif defined(USB_CFG_PCDC_USE) + UINT tx_err; + + /* Wait for the transfer request semaphore to wake up */ + tx_err = tx_semaphore_get(&g_usb_peri_usbx_sem[pipenum], p_tran_data->timeout); + + /* Check the error status code, and if this transfer is not successful end this + * transfer and return error code to the caller function.*/ + if (TX_SUCCESS != tx_err) + { + /* Set transfer request timeout status */ + p_tran_data->is_timeout = USB_YES; + + /* Once Time out occurs for this transfer request, terminate data transmission + * or reception. */ + usb_pstd_forced_termination(pipenum, (uint16_t) USB_DATA_STOP, p_tran_data); + USB_REL_BLK(1, p_tran_data); + err = USB_ERR_TMOUT; + } + else + { + /* Check for the FIFO error flag status */ + if (USB_YES == g_usb_peri_usbx_is_fifo_error[pipenum]) + { + g_usb_peri_usbx_is_fifo_error[pipenum] = USB_NO; + err = USB_ERR_FIFO_ACCESS; + } + } + + #else + tx_semaphore_get(&g_usb_peri_usbx_sem[pipenum], TX_WAIT_FOREVER); + #endif /* defined(USB_CFG_PPRN_USE) */ + } + #endif /* #if (BSP_CFG_RTOS == 1) */ + #endif /* (BSP_CFG_RTOS == 0) */ + + return err; +} + +/****************************************************************************** + * End of function usb_pstd_transfer_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_transfer_end + * Description : Force termination of data transfer of specified pipe. Request + * : PCD to force termination data transfer, + * : and the PCD forced-terminates data transfer. + * Arguments : uint16_t pipe : Pipe number. + * Return value : usb_er_t : Error info. + ******************************************************************************/ +usb_er_t usb_pstd_transfer_end (usb_utr_t * p_utr, uint16_t pipe) +{ + usb_er_t err = USB_OK; + #if (BSP_CFG_RTOS != 0) + usb_utr_t utr; + #endif /* (BSP_CFG_RTOS != 0) */ + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("### usb_pstd_transfer_end PipeNo ERROR:%d\n", pipe); + + return USB_ERROR; /* Error */ + } + + if (USB_NULL == g_p_usb_pstd_pipe[pipe]) + { + USB_PRINTF0("### usb_pstd_transfer_end overlaps\n"); + err = USB_ERROR; + } + else + { + #if (BSP_CFG_RTOS == 0) + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_STOP, p_utr); + #else /* BSP_CFG_RTOS == 0 */ + utr.msghead = (usb_mh_t) USB_NULL; + utr.msginfo = USB_MSG_PCD_TRANSEND1; + utr.keyword = pipe; + utr.ip = p_utr->ip; + + /* Send message */ + err = USB_SND_MSG(USB_PCD_MBX, (usb_msg_t *) &utr); + #endif /* (BSP_CFG_RTOS == 0) */ + } + + return err; +} + +/****************************************************************************** + * End of function usb_pstd_transfer_end + ******************************************************************************/ + #endif /* (USB_UT_MODE == 0) */ + + #if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_pstd_change_device_state + * Description : Change USB Device to the status specified by argument + * Arguments : uint16_t state : New device status. + * : uint16_t keyword : Pipe number etc. + * : usb_cb_t complete : Callback function. + * Return value : none + ******************************************************************************/ +void usb_pstd_change_device_state (uint16_t state, uint16_t keyword, usb_cb_t complete, usb_utr_t * p_utr) +{ + uint16_t pipenum; + #if (BSP_CFG_RTOS != 0) + static usb_utr_t utr; + uint16_t err; + #endif /* (BSP_CFG_RTOS != 0) */ + + pipenum = keyword; + switch (state) + { + case USB_DO_STALL: + { + usb_pstd_set_stall(pipenum, p_utr); + g_usb_pstd_stall_pipe[pipenum] = USB_TRUE; + g_usb_pstd_stall_cb = complete; + break; + } + + case USB_DO_REMOTEWAKEUP: + { + #if (BSP_CFG_RTOS == 0) + usb_pstd_self_clock(p_utr->ip); + usb_pstd_remote_wakeup(p_utr->ip); + #else /* BSP_CFG_RTOS == 0 */ + utr.msghead = (usb_mh_t) USB_NULL; + utr.msginfo = USB_MSG_PCD_REMOTEWAKEUP; + utr.ip = p_utr->ip; + + /* Send message */ + err = (uint16_t) USB_SND_MSG(USB_PCD_MBX, (usb_msg_t *) &utr); + if (USB_OK != err) + { + USB_PRINTF1("###usb_pstd_change_device_state USB_SND_MSG error:%04X\n", err); + g_usb_pstd_remote_wakeup_state = USB_ERROR; + } + #endif /* BSP_CFG_RTOS == 0 */ + break; + } + + case USB_MSG_PCD_DP_ENABLE: + { + hw_usb_pset_dprpu(p_utr->ip); + break; + } + + case USB_MSG_PCD_DP_DISABLE: + { + hw_usb_pclear_dprpu(p_utr->ip); + break; + } + + default: + { + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_change_device_state + ******************************************************************************/ + #endif /* #if (USB_UT_MODE == 0) */ + +/****************************************************************************** + * Function Name : usb_pstd_driver_registration + * Description : Register pipe information table, descriptor information table, + * : callback function, etc. This info is specified by the data in + * : the structure usb_pcdreg_t. + * Arguments : usb_pcdreg_t *registinfo : Class driver structure. + * Return value : none + ******************************************************************************/ +void usb_pstd_driver_registration (usb_pcdreg_t * registinfo) +{ + usb_pcdreg_t * driver; + + driver = &g_usb_pstd_driver; + + driver->p_devicetbl = registinfo->p_devicetbl; /* Device descriptor table address */ + driver->p_qualitbl = registinfo->p_qualitbl; /* Qualifier descriptor table address */ + driver->p_configtbl = registinfo->p_configtbl; /* Configuration descriptor table address */ + driver->p_othertbl = registinfo->p_othertbl; /* Other configuration descriptor table address */ + driver->p_stringtbl = registinfo->p_stringtbl; /* String descriptor table address */ + driver->devdefault = registinfo->devdefault; /* Device default */ + driver->devconfig = registinfo->devconfig; /* Device configured */ + driver->devdetach = registinfo->devdetach; /* Device detach */ + driver->devsuspend = registinfo->devsuspend; /* Device suspend */ + driver->devresume = registinfo->devresume; /* Device resume */ + driver->interface = registinfo->interface; /* Interfaced change */ + driver->ctrltrans = registinfo->ctrltrans; /* Control transfer */ + driver->num_string = registinfo->num_string; /* String descriptor number */ +} + +/****************************************************************************** + * End of function usb_pstd_driver_registration + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_driver_release + * Description : Clear the information registered in the structure usb_pcdreg_t. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_driver_release (void) +{ + usb_pcdreg_t * driver; + + driver = &g_usb_pstd_driver; + driver->p_devicetbl = (uint8_t *) 0U; /* Device descriptor table address */ + driver->p_qualitbl = (uint8_t *) 0U; /* Qualifier descriptor table address */ + driver->p_configtbl = (uint8_t *) 0U; /* Configuration descriptor table address */ + driver->p_othertbl = (uint8_t *) 0U; /* Other configuration descriptor table address */ + driver->p_stringtbl = (uint8_t **) 0U; /* String descriptor table address */ + driver->devdefault = &usb_pstd_dummy_function; /* Device default */ + driver->devconfig = &usb_pstd_dummy_function; /* Device configured */ + driver->devdetach = &usb_pstd_dummy_function; /* Device detach */ + driver->devsuspend = &usb_pstd_dummy_function; /* Device suspend */ + driver->devresume = &usb_pstd_dummy_function; /* Device resume */ + driver->interface = &usb_pstd_dummy_function; /* Interfaced change */ + driver->ctrltrans = &usb_pstd_dummy_trn; /* Control transfer */ +}/* End of function usb_pstd_driver_release() */ + +/****************************************************************************** + * Function Name : usb_pstd_dummy_function + * Description : dummy function + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data1 : Not used + * : uint16_t data2 : Not used + * Return value : none + ******************************************************************************/ +void usb_pstd_dummy_function (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + /* Dummy function */ + FSP_PARAMETER_NOT_USED(*ptr); + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); +} + +/****************************************************************************** + * End of function usb_pstd_dummy_function + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_dummy_trn + * Description : Class request processing for dummy + * Arguments : usb_setup_t *preq ; Class request information + * : uint16_t ctsq ; Control Stage + * Return value : none + ******************************************************************************/ +void usb_pstd_dummy_trn (usb_setup_t * preq, uint16_t ctsq, usb_utr_t * p_utr) +{ + /* Dummy function */ + FSP_PARAMETER_NOT_USED(*preq); + FSP_PARAMETER_NOT_USED(ctsq); + FSP_PARAMETER_NOT_USED(*p_utr); +} /* End of function usb_pstd_dummy_trn */ + +/****************************************************************************** + * Function Name : usb_pstd_device_information + * Description : Get USB Device information such as USB Device status and con- + * : figuration No. etc. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t *tbl : Device information storage pointer TBL. This + * : pointer is used to provide the caller with the device's sta- + * : tus, speed, configuration and interface number, and the value + * : of the remote wakeup flag. + * Return value : none + ******************************************************************************/ +void usb_pstd_device_information (usb_utr_t * ptr, uint16_t * tbl) +{ + /* Device status */ + tbl[0] = hw_usb_read_intsts(ptr->ip) & (uint16_t) (USB_VBSTS | USB_DVSQ); + + /* Speed */ + tbl[1] = usb_cstd_port_speed(ptr); + + /* Configuration number */ + tbl[2] = g_usb_pstd_config_num; + + /* Interface number */ + tbl[3] = usb_pstd_get_interface_num(); + + /* Remote Wakeup Flag */ + tbl[4] = g_usb_pstd_remote_wakeup; +} /* End of function usb_pstd_device_information() */ + +/****************************************************************************** + * Function Name : usb_pstd_set_stall_clr_feature + * Description : Set pipe stall request + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : usb_cb_t complete : callback function + * : uint16_t pipe : pipe number + * Return value : usb_er_t : Error Info + ******************************************************************************/ +usb_er_t usb_pstd_set_stall_clr_feature (usb_utr_t * ptr, usb_cb_t complete, uint16_t pipe) +{ + FSP_PARAMETER_NOT_USED(*ptr); + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("*** usb_pstd_set_stall_clr_feature PipeNo ERROR %d\n", pipe); + + return USB_ERROR; /* Error */ + } + + usb_pstd_change_device_state(USB_DO_STALL, pipe, complete, ptr); + + return USB_OK; +} + +/****************************************************************************** + * End of function usb_pstd_set_stall_clr_feature + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_peri_registration + * Description : Registration of peripheral Devices Class Driver + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_peri_registration (usb_instance_ctrl_t * ctrl, usb_cfg_t const * const cfg) +{ + usb_pcdreg_t pdriver; + + FSP_PARAMETER_NOT_USED(*ctrl); + + /* pdriver registration */ + pdriver.p_devicetbl = cfg->p_usb_reg->p_device; /* Device descriptor Table address */ + pdriver.p_qualitbl = cfg->p_usb_reg->p_qualifier; /* Qualifier descriptor Table address */ + if (USB_NULL == cfg->p_usb_reg->p_config_f) + { + pdriver.p_configtbl = cfg->p_usb_reg->p_config_h; /* Configuration descriptor Table address */ + } + else + { + pdriver.p_configtbl = cfg->p_usb_reg->p_config_f; /* Configuration descriptor Table address */ + } + + pdriver.p_othertbl = cfg->p_usb_reg->p_config_h; /* Other configuration descriptor Table address */ + pdriver.p_stringtbl = cfg->p_usb_reg->p_string; /* String descriptor Table address */ + pdriver.num_string = cfg->p_usb_reg->num_string; /* Num entry String descriptor */ + + pdriver.devdefault = &usb_peri_devdefault; /* Device default */ + pdriver.devconfig = &usb_peri_configured; /* Device configuered */ + pdriver.devdetach = &usb_peri_detach; /* Device detach */ + pdriver.devsuspend = (usb_cb_t) &usb_peri_suspended; /* Device suspend */ + pdriver.devresume = &usb_peri_resume; /* Device resume */ + pdriver.interface = &usb_peri_interface; /* Interface changed */ + pdriver.ctrltrans = (usb_cb_trn_t) &usb_peri_class_request; /* Control Transfer */ + + usb_pstd_driver_registration(&pdriver); +} /* End of function usb_peri_registration() */ + +/****************************************************************************** + * Function Name : usb_peri_devdefault + * Description : Descriptor change + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t mode ; Speed mode + * : uint16_t data2 ; BC Port Detect Result + * Return value : none + ******************************************************************************/ +void usb_peri_devdefault (usb_utr_t * ptr, uint16_t mode, uint16_t data2) +{ + uint8_t * ptable; + uint16_t len; + + FSP_PARAMETER_NOT_USED(data2); + + #if (defined(USB_CFG_PCDC_USE) | defined(USB_CFG_PHID_USE) | defined(USB_CFG_PPRN_USE)) + usb_instance_ctrl_t ctrl; + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + ctrl.p_transfer_rx = ptr->p_transfer_rx; + ctrl.p_transfer_tx = ptr->p_transfer_tx; + #endif + #endif + + usb_peri_detach(ptr, USB_DEFAULT, USB_NULL); + + /* Connect Speed = Hi-Speed? */ + if (USB_HSCONNECT == mode) + { + ptable = g_usb_pstd_driver.p_othertbl; + + /* Set Descriptor type. */ + /* Hi-Speed Mode */ + if (USB_NULL != g_usb_pstd_driver.p_configtbl) + { + g_usb_pstd_driver.p_configtbl[1] = USB_DT_OTHER_SPEED_CONF; + } + + if (USB_NULL != g_usb_pstd_driver.p_othertbl) + { + g_usb_pstd_driver.p_othertbl[1] = USB_DT_CONFIGURATION; + } + } + else + { + ptable = g_usb_pstd_driver.p_configtbl; + + /* Set Descriptor type. */ + /* Full-Speed Mode */ + if (USB_NULL != g_usb_pstd_driver.p_configtbl) + { + g_usb_pstd_driver.p_configtbl[1] = USB_DT_CONFIGURATION; + } + + if (USB_NULL != g_usb_pstd_driver.p_othertbl) + { + g_usb_pstd_driver.p_othertbl[1] = USB_DT_OTHER_SPEED_CONF; + } + } + + if (USB_NULL == ptable) + { + while (1) + { + /* Error */ + } + } + + len = (uint16_t) (*(uint8_t *) ((uint32_t) ptable + (uint32_t) 3)); + len = (uint16_t) (len << 8); + len = (uint16_t) (len + (uint16_t) (*(uint8_t *) ((uint32_t) ptable + (uint32_t) 2))); + + usb_pstd_clr_pipe_table(ptr->ip); + usb_peri_pipe_info(ptable, mode, len, ptr); + + #if (defined(USB_CFG_PCDC_USE) | defined(USB_CFG_PHID_USE) | defined(USB_CFG_PPRN_USE)) + ctrl.module_number = ptr->ip; + usb_set_event(USB_STATUS_DEFAULT, &ctrl); + #endif +} /* End of function usb_peri_devdefault() */ + + #define NUM_OF_INTERFACE (8U) + #ifdef USB_CFG_PAUD_USE +uint8_t g_usb_paud_iso_pipe[NUM_OF_INTERFACE]; + #endif + +/****************************************************************************** + * Function Name : usb_peri_pipe_info + * Description : Pipe Information check and EP Table Set + * Arguments : uint8_t *table : Check Start Descriptor address + * : uint16_t speed : Device connected speed + * : uint16_t length : Configuration Descriptor Length + * Return value : uint16_t : USB_E_OK / USB_E_ERROR + ******************************************************************************/ +uint16_t usb_peri_pipe_info (uint8_t * table, uint16_t speed, uint16_t length, usb_utr_t * p_utr) +{ + uint16_t ofdsc; + uint16_t retval = USB_ERROR; + uint8_t pipe_no; + uint8_t class_info = 0; + #ifdef USB_CFG_PAUD_USE + uint8_t interface_num = 0; + #endif // USB_CFG_PAUD_USE + + FSP_PARAMETER_NOT_USED(speed); + + /* Check Endpoint Descriptor */ + ofdsc = table[0]; + + /* WAIT_LOOP */ + while (ofdsc < length) + { + if (USB_DT_INTERFACE == table[ofdsc + USB_EP_B_DESCRIPTORTYPE]) + { + class_info = table[ofdsc + USB_IF_B_INTERFACECLASS]; + #ifdef USB_CFG_PAUD_USE + interface_num = table[ofdsc + USB_IF_B_INTERFACENUMBER]; + #endif // USB_CFG_PAUD_USE + } + + /* Endpoint Descriptor */ + if (USB_DT_ENDPOINT == table[ofdsc + USB_EP_B_DESCRIPTORTYPE]) + { + /* EP Table pipe Information set */ + pipe_no = usb_pstd_set_pipe_table(&table[ofdsc], p_utr, class_info); + if (USB_NULL != pipe_no) + { + retval = USB_OK; + #ifdef USB_CFG_PAUD_USE + g_usb_paud_iso_pipe[interface_num] = pipe_no; + #endif // USB_CFG_PAUD_USE + } + else + { + USB_PRINTF3("###usb_peri_pipe_info ERROR Type:%02X ADDR:%02X ATR:%02X \n", + table[USB_EP_B_DESCRIPTORTYPE], + table[USB_EP_B_ENDPOINTADDRESS], + table[USB_EP_B_ATTRIBUTES]); + } + } + + ofdsc = (uint16_t) (ofdsc + table[ofdsc]); + } + + return retval; +} /* End of function usb_peri_pipe_info() */ + +/****************************************************************************** + * Function Name : usb_peri_configured + * Description : Peripheral Devices Class open function + * Arguments : usb_utr_t *ptr : Not used + * : uint16_t data1 : Not used + * : uint16_t data2 : Not used + * Return value : none + ******************************************************************************/ +void usb_peri_configured (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + usb_instance_ctrl_t ctrl; + + FSP_PARAMETER_NOT_USED(*ptr); + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); + + g_usb_peri_connected = USB_TRUE; + + ctrl.module_number = ptr->ip; + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + ctrl.p_transfer_rx = ptr->p_transfer_rx; + ctrl.p_transfer_tx = ptr->p_transfer_tx; + #endif + usb_set_event(USB_STATUS_CONFIGURED, &ctrl); + + #if defined(USB_CFG_PMSC_USE) + #if (BSP_CFG_RTOS != 1) + usb_pmsc_receive_cbw(ptr); + #endif /* (BSP_CFG_RTOS != 1) */ + #endif +} /* End of function usb_configured() */ + +/****************************************************************************** + * Function Name : usb_peri_detach + * Description : Peripheral Devices Class close function + * Arguments : usb_utr_t *ptr : Not used + * : uint16_t usb_state : USB state + * : uint16_t data2 : Not used + * Return value : none + ******************************************************************************/ +void usb_peri_detach (usb_utr_t * ptr, uint16_t usb_state, uint16_t data2) +{ + usb_instance_ctrl_t ctrl; + #if (BSP_CFG_RTOS == 1) + uint8_t pipe; + uint16_t intsts; + #endif /* #if (BSP_CFG_RTOS == 1) */ + + FSP_PARAMETER_NOT_USED(*ptr); + FSP_PARAMETER_NOT_USED(data2); + + #if (BSP_CFG_RTOS == 1) + intsts = hw_usb_read_intsts(ptr->ip); + if (USB_VBSTS == (intsts & USB_VBSTS)) + { + /* When doing the warm start PC(USB_Host), PC sends the USB Reset. * + * The following code is needed to release the waiting status of the semaphore waiting task * + * before doing the warm start. */ + if (USB_DEFAULT == usb_state) + { + for (pipe = USB_MIN_PIPE_NO; pipe < (USB_MAX_PIPE_NO + 1); pipe++) + { + g_usb_peri_usbx_is_detach[pipe] = USB_NO; + tx_semaphore_put(&g_usb_peri_usbx_sem[pipe]); + tx_semaphore_delete(&g_usb_peri_usbx_sem[pipe]); + } + + if (USB_YES == g_usb_peri_usbx_is_configured[ptr->ip]) + { + /* The "ux_device_stack_disconnect" function must be not executed when attaching USB device to USB Host. */ + /* Because the unnecessary detaching event is notfied to the application program when attaching USB device to USB Host. */ + /* But, when doing the warm start PC, the "ux_device_stack_disconnect" function must be executed. */ + _ux_device_stack_disconnect(); + } + } + } + + #else /* #if (BSP_CFG_RTOS == 1) */ + FSP_PARAMETER_NOT_USED(usb_state); + #endif /* #if (BSP_CFG_RTOS == 1) */ + + if (USB_TRUE == g_usb_peri_connected) + { + g_usb_peri_connected = USB_FALSE; + + ctrl.module_number = ptr->ip; + usb_set_event(USB_STATUS_DETACH, &ctrl); + } +} /* End of function usb_peri_detach() */ + +/****************************************************************************** + * Function Name : usb_peri_suspended + * Description : Peripheral Devices Class suspended function + * Arguments : usb_utr_t *ptr : Not used + * : uint16_t data1 : Not used + * : uint16_t data2 : Not used + * Return value : none + ******************************************************************************/ +void usb_peri_suspended (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + usb_instance_ctrl_t ctrl; + + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); + + ctrl.module_number = ptr->ip; + usb_set_event(USB_STATUS_SUSPEND, &ctrl); + + #if BSP_CFG_RTOS == 1 + if (UX_NULL != _ux_system_slave->ux_system_slave_change_function) + { + _ux_system_slave->ux_system_slave_change_function(UX_DEVICE_SUSPENDED); + } + #endif /* #if (BSP_CFG_RTOS == 1) */ +} /* End of function usb_suspended() */ + +/****************************************************************************** + * Function Name : usb_peri_resume + * Description : Peripheral Devices Class resume function + * Arguments : usb_utr_t *ptr : Not used + * : uint16_t data1 : Not used + * : uint16_t data2 : Not used + * Return value : none + ******************************************************************************/ +void usb_peri_resume (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + usb_instance_ctrl_t ctrl; + + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); + + ctrl.module_number = ptr->ip; + #if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + ctrl.p_transfer_rx = ptr->p_transfer_rx; + ctrl.p_transfer_tx = ptr->p_transfer_tx; + #endif + #if (BSP_CFG_RTOS != 0) + ctrl.p_data = (void *) ptr->cur_task_hdl; + #endif /* (BSP_CFG_RTOS != 0) */ + + usb_set_event(USB_STATUS_RESUME, &ctrl); + + #if BSP_CFG_RTOS == 1 + if (UX_NULL != _ux_system_slave->ux_system_slave_change_function) + { + _ux_system_slave->ux_system_slave_change_function(UX_DEVICE_RESUMED); + } + #endif +} /* End of function usb_peri_resume() */ + +/****************************************************************************** + * Function Name : usb_peri_interface + * Description : Peripheral Devices Class set interface function + * Arguments : usb_utr_t *ptr : Not used + * : uint16_t data1 : Not used + * : uint16_t data2 : Not used + * Return value : none + ******************************************************************************/ +void usb_peri_interface (usb_utr_t * ptr, uint16_t data1, uint16_t data2) +{ + FSP_PARAMETER_NOT_USED(*ptr); + FSP_PARAMETER_NOT_USED(data1); + FSP_PARAMETER_NOT_USED(data2); + + #if defined(USB_CFG_PMSC_USE) + #if (BSP_CFG_RTOS != 1) + usb_pmsc_receive_cbw(ptr); + #endif /* (BSP_CFG_RTOS != 1) */ + #else /* defined(USB_CFG_PMSC_USE) */ + /* Non processing */ + #endif /* defined(USB_CFG_PMSC_USE) */ +} /* End of function usb_peri_interface() */ + + #if defined(USB_CFG_PVND_USE) + +/****************************************************************************** + * Function Name : usb_pvnd_read_complete + * Description : CallBack Function + * Argument : usb_utr_t *mess : Transfer result message + * Return : none + ******************************************************************************/ +void usb_pvnd_read_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) +{ + (void) data1; + (void) data2; + + usb_instance_ctrl_t ctrl; + + /* Set Receive data length */ + ctrl.data_size = mess->read_req_len - mess->tranlen; + ctrl.pipe = (uint8_t) mess->keyword; /* Pipe number setting */ + ctrl.type = USB_CLASS_PVND; /* Device class setting */ + #if (BSP_CFG_RTOS != 0) + ctrl.p_data = (void *) mess->cur_task_hdl; + #endif /* (BSP_CFG_RTOS != 0) */ + switch (mess->status) + { + case USB_DATA_OK: + { + ctrl.status = FSP_SUCCESS; + break; + } + + case USB_DATA_SHT: + { + ctrl.status = FSP_ERR_USB_SIZE_SHORT; + break; + } + + case USB_DATA_OVR: + { + ctrl.status = FSP_ERR_USB_SIZE_OVER; + break; + } + + case USB_DATA_ERR: + default: + { + ctrl.status = FSP_ERR_USB_FAILED; + break; + } + } + + ctrl.module_number = mess->ip; + usb_set_event(USB_STATUS_READ_COMPLETE, &ctrl); +} /* End of function usb_pvnd_read_complete() */ + +/****************************************************************************** + * Function Name : usb_pvnd_write_complete + * Description : CallBack Function + * Argument : usb_utr_t *mess : Transfer result message + * Return : none + ******************************************************************************/ +void usb_pvnd_write_complete (usb_utr_t * mess, uint16_t data1, uint16_t data2) +{ + (void) data1; + (void) data2; + + usb_instance_ctrl_t ctrl; + + ctrl.pipe = (uint8_t) mess->keyword; /* Pipe number setting */ + ctrl.type = USB_CLASS_PVND; /* CDC Control class */ + if (USB_DATA_NONE == mess->status) + { + ctrl.status = FSP_SUCCESS; + } + else + { + ctrl.status = FSP_ERR_USB_FAILED; + } + + ctrl.module_number = mess->ip; + #if (BSP_CFG_RTOS != 0) + ctrl.p_data = (void *) mess->cur_task_hdl; + #endif /* (BSP_CFG_RTOS != 0) */ + usb_set_event(USB_STATUS_WRITE_COMPLETE, &ctrl); +} /* End of function usb_pvnd_write_complete() */ + + #endif /* defined(USB_CFG_PVND_USE) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pintfifo.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pintfifo.c new file mode 100644 index 0000000000..a33e2cdb82 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pintfifo.c @@ -0,0 +1,188 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Renesas Abstracted Peripheral FIFO access functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_brdy_pipe + * Description : Execute data transfer for the PIPE for which a BRDY interrupt + * : occurred. + * Arguments : uint16_t bitsts : BRDYSTS register & BRDYENB register. + * Return value : none + ******************************************************************************/ +void usb_pstd_brdy_pipe (usb_utr_t * p_utr, uint16_t bitsts) +{ + /* When operating by the peripheral function, usb_pstd_brdy_pipe() is executed with PIPEx request because */ + /* two BRDY messages are issued even when the demand of PIPE0 and PIPEx has been generated at the same time. */ + if (USB_BRDY0 == (bitsts & USB_BRDY0)) + { + switch (usb_pstd_read_data(USB_PIPE0, USB_CUSE, p_utr)) + { + /* End of data read */ + case USB_READEND: + + /* Continue */ + /* End of data read */ + case USB_READSHRT: + { + hw_usb_clear_brdyenb(p_utr, (uint16_t) USB_PIPE0); + break; + } + + /* Continue of data read */ + case USB_READING: + { + /* PID = BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + break; + } + + /* FIFO access error */ + case USB_READOVER: + { + USB_PRINTF0("###usb_pstd_brdy_pipe Receive data over PIPE0 \n"); + + /* Clear BVAL */ + hw_usb_set_bclr(p_utr, USB_CUSE); + + /* Control transfer stop(end) */ + usb_pstd_ctrl_end((uint16_t) USB_DATA_OVR, p_utr); + break; + } + + /* FIFO access error */ + case USB_FIFOERROR: + { + USB_PRINTF0("###usb_pstd_brdy_pipe FIFO access error \n"); + + /* Control transfer stop(end) */ + usb_pstd_ctrl_end((uint16_t) USB_DATA_ERR, p_utr); + break; + } + + default: + { + break; + } + } + } + else + { + /* not PIPE0 */ + usb_pstd_brdy_pipe_process(p_utr, bitsts); + } +} + +/****************************************************************************** + * End of function usb_pstd_brdy_pipe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_nrdy_pipe + * Description : Execute appropriate processing for the PIPE for which a NRDY + * : interrupt occurred. + * Arguments : uint16_t bitsts : NRDYSTS register & NRDYENB register. + * Return value : none + ******************************************************************************/ +void usb_pstd_nrdy_pipe (usb_utr_t * p_utr, uint16_t bitsts) +{ + /* The function for peripheral driver is created here. */ + if (USB_NRDY0 == (bitsts & USB_NRDY0)) + { + /* Non processing. */ + } + else + { + /* Nrdy Pipe interrupt */ + usb_pstd_nrdy_pipe_process(p_utr, bitsts); + } +} + +/****************************************************************************** + * End of function usb_pstd_nrdy_pipe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_bemp_pipe + * Description : Execute data transfer for the PIPE for which a BEMP interrupt + * : occurred. + * Arguments : uint16_t bitsts : BEMPSTS register & BEMPENB register. + * Return value : none + ******************************************************************************/ +void usb_pstd_bemp_pipe (usb_utr_t * p_utr, uint16_t bitsts) +{ + /* When operating by the peripheral function, usb_pstd_bemp_pipe() is executed with PIPEx request because */ + /* two BEMP messages are issued even when the demand of PIPE0 and PIPEx has been generated at the same time. */ + if (USB_BEMP0 == (bitsts & USB_BEMP0)) + { + switch (usb_pstd_write_data(USB_PIPE0, USB_CUSE, p_utr)) + { + /* End of data write (not null) */ + case USB_WRITEEND: + + /* Continue */ + /* End of data write */ + case USB_WRITESHRT: + { + /* Enable empty interrupt */ + hw_usb_clear_bempenb(p_utr, (uint16_t) USB_PIPE0); + break; + } + + /* Continue of data write */ + case USB_WRITING: + { + /* PID = BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + break; + } + + /* FIFO access error */ + case USB_FIFOERROR: + { + USB_PRINTF0("###usb_pstd_brdy_pipe FIFO access error \n"); + + /* Control transfer stop(end) */ + usb_pstd_ctrl_end((uint16_t) USB_DATA_ERR, p_utr); + break; + } + + default: + { + break; + } + } + } + else + { + /* BEMP interrupt */ + usb_pstd_bemp_pipe_process(p_utr, bitsts); + } +} + +/****************************************************************************** + * End of function usb_pstd_bemp_pipe + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pinthandler_usbip0.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pinthandler_usbip0.c new file mode 100644 index 0000000000..01fb7d379d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pinthandler_usbip0.c @@ -0,0 +1,114 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +usb_int_t g_usb_pstd_usb_int; + + #if (BSP_CFG_RTOS != 0) +static usb_utr_t g_usb_pstd_int[USB_INT_BUFSIZE]; + #endif /* #if (BSP_CFG_RTOS != 0)*/ + + #if (BSP_CFG_RTOS == 1) +extern TX_QUEUE g_pcd_mbx_hdl; + #endif /* (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Renesas Abstracted common Interrupt handler functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_usb_handler + * Description : USB interrupt routine. Analyze which USB interrupt occurred + * : and send message to PCD task. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_usb_handler (void) +{ + #if (BSP_CFG_RTOS != 0) + usb_utr_t * p; + + p = get_usb_int_buf(); + #endif /*(BSP_CFG_RTOS != 0)*/ + IRQn_Type irq; + usb_cfg_t * p_cfg; + + irq = R_FSP_CurrentIrqGet(); + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet(irq); + + usb_pstd_interrupt_clock(p_cfg->module_number); + + /* Push Interrupt info */ + #if (BSP_CFG_RTOS != 0) + p->msginfo = USB_MSG_PCD_INT; + p->ip = p_cfg->module_number; + p->p_transfer_rx = p_cfg->p_transfer_rx; + p->p_transfer_tx = p_cfg->p_transfer_tx; + usb_pstd_interrupt_handler(&p->keyword, &p->status, p->ip); + + USB_ISND_MSG(USB_PCD_MBX, (usb_msg_t *) p); + #endif /*(BSP_CFG_RTOS != 0)*/ + + #if (BSP_CFG_RTOS == 0) + g_usb_pstd_usb_int.buf[g_usb_pstd_usb_int.wp].p_cfg = p_cfg; + + usb_pstd_interrupt_handler(&g_usb_pstd_usb_int.buf[g_usb_pstd_usb_int.wp].type, + &g_usb_pstd_usb_int.buf[g_usb_pstd_usb_int.wp].status, + g_usb_pstd_usb_int.buf[g_usb_pstd_usb_int.wp].p_cfg->module_number); + + /* Write count up */ + g_usb_pstd_usb_int.wp = (uint8_t) ((uint8_t) (g_usb_pstd_usb_int.wp + 1) % USB_INT_BUFSIZE); + #endif /*(BSP_CFG_RTOS == 0)*/ +} + +/****************************************************************************** + * End of function usb_pstd_usb_handler + ******************************************************************************/ + + #if (BSP_CFG_RTOS != 0) + +/****************************************************************************** + * Function Name : get_usb_int_buf + * Description : USB interrupt routine. Analyze which USB interrupt occurred + * : and send message to PCD task. + * Arguments : none + * Return value : Point to the area for usb_int_t structure + ******************************************************************************/ +usb_utr_t * get_usb_int_buf (void) +{ + static uint16_t count = 0; + usb_utr_t * p; + + p = &g_usb_pstd_int[count]; + + count = ((uint16_t) (((uint16_t) (count + 1)) % USB_INT_BUFSIZE)); + + return p; +} + +/****************************************************************************** + * End of function get_usb_int_buf + ******************************************************************************/ + #endif /* #if (BSP_CFG_RTOS != 0) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c new file mode 100644 index 0000000000..9cc53573c5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c @@ -0,0 +1,1916 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if defined(USB_CFG_OTG_USE) + #if defined(USB_CFG_PCDC_USE) + #include "r_usb_otg_cdc_cfg.h" + #endif /* (defined(USB_CFG_HCDC_USE) | defined(USB_CFG_PCDC_USE)) */ + #if defined(USB_CFG_PHID_USE) + #include "r_usb_otg_hid_cfg.h" + #endif /* (defined(USB_CFG_HCDC_USE) | defined(USB_CFG_PCDC_USE)) */ + #if defined(USB_CFG_PMSC_USE) + #include "r_usb_otg_msc_cfg.h" + #endif +#else /* defined(USB_CFG_OTG_USE) */ + #if defined(USB_CFG_PCDC_USE) +uint8_t g_usb_pcdc_bulk_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_pcdc_bulk_out_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_pcdc_int_in_pipe[USB_NUM_USBIP] = {0}; + #if defined(USB_CFG_PCDC2_USE) +uint8_t g_usb_pcdc2_bulk_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_pcdc2_bulk_out_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_pcdc2_int_in_pipe[USB_NUM_USBIP] = {0}; + #endif + #endif /* defined(USB_CFG_PCDC_USE) */ + #if defined(USB_CFG_PHID_USE) +uint8_t g_usb_phid_int_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_phid_int_out_pipe[USB_NUM_USBIP] = {0}; + #if defined(USB_CFG_PHID2_USE) +uint8_t g_usb_phid2_int_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_phid2_int_out_pipe[USB_NUM_USBIP] = {0}; + #endif /* defined(USB_CFG_PHID2_USE) */ + #endif /* defined(USB_CFG_PHID2_USE) */ + + #if defined(USB_CFG_PMSC_USE) +uint8_t g_usb_pmsc_bulk_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_pmsc_bulk_out_pipe[USB_NUM_USBIP] = {0}; + #endif /* defined(USB_CFG_PMSC_USE) */ + +#endif /* defined(USB_CFG_OTG_USE) */ + +#if defined(USB_CFG_PPRN_USE) +uint8_t g_usb_pprn_bulk_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_pprn_bulk_out_pipe[USB_NUM_USBIP] = {0}; +#endif /* defined(USB_CFG_PPRN_USE) */ + +#if defined(USB_CFG_PAUD_USE) +uint8_t g_usb_paud_iso_in_pipe[USB_NUM_USBIP] = {0}; +uint8_t g_usb_paud_iso_out_pipe[USB_NUM_USBIP] = {0}; +#endif /* defined(USB_CFG_PAUD_USE) */ +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "../hw/inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + #if defined(USB_CFG_PCDC_USE) + #if defined(USB_CFG_PMSC_USE) || defined(USB_CFG_PVND_USE) || defined(USB_CFG_PPRN_USE) || defined(USB_CFG_PAUD_USE) + #define USB_COMPOSITE_DEVICE + #else + #if defined(USB_CFG_PCDC2_USE) + #define USB_COMPOSITE_DEVICE + #else + #define USB_NO_COMPOSITE_DEVICE + #endif + #endif + #elif defined(USB_CFG_PMSC_USE) + #if defined(USB_CFG_PVND_USE) || defined(USB_CFG_PPRN_USE) || defined(USB_CFG_PAUD_USE) + #define USB_COMPOSITE_DEVICE + #else + #define USB_NO_COMPOSITE_DEVICE + #endif + #elif defined(USB_CFG_PPRN_USE) + #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_PVND_USE) + #define USB_COMPOSITE_DEVICE + #else + #define USB_NO_COMPOSITE_DEVICE + #endif + #elif defined(USB_CFG_PAUD_USE) + #if defined(USB_CFG_PVND_USE) + #define USB_COMPOSITE_DEVICE + #else + #define USB_NO_COMPOSITE_DEVICE + #endif + #endif + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + #if (BSP_CFG_RTOS == 1) +extern TX_SEMAPHORE g_usb_peri_usbx_sem[USB_MAX_PIPE_NO + 1]; + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Renesas Abstracted Host Lib IP functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_epadr2pipe + * Description : Get the associated pipe no. of the specified endpoint. + * Arguments : uint16_t dir_ep : Direction + endpoint number. + * Return value : uint16_t : OK : Pipe number. + * : : ERROR : Error. + ******************************************************************************/ +uint16_t usb_pstd_epadr2pipe (uint16_t dir_ep, usb_utr_t * p_utr) +{ + uint16_t i; + uint16_t direp; + uint16_t tmp; + + /* Peripheral */ + /* Get PIPE Number from Endpoint address */ + direp = (uint16_t) (((dir_ep & USB_ENDPOINT_DIRECTION) >> 3) | (dir_ep & USB_EPNUMFIELD)); + + /* EP table loop */ + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i < (USB_MAXPIPE_NUM + 1); i++) + { + if (USB_TRUE == g_usb_pipe_table[p_utr->ip][i].use_flag) + { + tmp = (uint16_t) (g_usb_pipe_table[p_utr->ip][i].pipe_cfg & (USB_DIRFIELD | USB_EPNUMFIELD)); + + /* EP table endpoint dir check */ + if (direp == tmp) + { + return i; + } + } + } + + USB_PRINTF1("###usb_pstd_epadr2pipe dir_ep:%02x\n", dir_ep); + + return USB_ERROR; +} + +/****************************************************************************** + * End of function usb_pstd_epadr2pipe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_pipe2fport + * Description : Get port No. from the specified pipe No. by argument + * Arguments : uint16_t pipe : Pipe number. + * Return value : uint16_t : FIFO port selector. + ******************************************************************************/ +uint16_t usb_pstd_pipe2fport (usb_utr_t * p_utr, uint16_t pipe) +{ + uint16_t fifo_mode = USB_CUSE; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t usb_dir; + #endif + + if (USB_MAX_PIPE_NO < pipe) + { + return USB_NULL; /* Error */ + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + if ((0 != p_utr->p_transfer_tx) || (0 != p_utr->p_transfer_rx)) + { + #ifdef USB_COMPOSITE_DEVICE + if ((USB_PIPE1 == pipe) || (USB_PIPE2 == pipe)) + #else + if (USB_PIPE5 >= pipe) + #endif + { + hw_usb_write_pipesel(p_utr, pipe); + usb_dir = hw_usb_read_pipecfg(p_utr); + usb_dir = usb_dir & USB_DIRFIELD; + if (0 == usb_dir) + { + fifo_mode = USB_D0USE; + } + else + { + fifo_mode = USB_D1USE; + } + } + } + #else + FSP_PARAMETER_NOT_USED(*p_utr); + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + return fifo_mode; +} + +/****************************************************************************** + * End of function usb_pstd_pipe2fport + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_hi_speed_enable + * Description : Check if set to Hi-speed. + * Arguments : none + * Return value : uint16_t : YES; Hi-Speed enabled. + * : : NO; Hi-Speed disabled. + ******************************************************************************/ +uint16_t usb_pstd_hi_speed_enable (usb_utr_t * p_utr) +{ + uint16_t buf; + uint16_t err; + + buf = hw_usb_read_syscfg(p_utr); + + if (USB_HSE == (buf & USB_HSE)) + { + /* Hi-Speed Enable */ + err = USB_TRUE; + } + else + { + /* Hi-Speed Disable */ + err = USB_FALSE; + } + + return err; +} + +/****************************************************************************** + * End of function usb_pstd_hi_speed_enable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_send_start + * Description : Start data transmission using CPU/DMA transfer to USB host. + * Arguments : uint16_t pipe : Pipe no. + * Return value : none + ******************************************************************************/ +void usb_pstd_send_start (uint16_t pipe) +{ + usb_utr_t * pp; + uint32_t length; + uint16_t useport; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t ip; + uint16_t ch; + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Evacuation pointer */ + pp = g_p_usb_pstd_pipe[pipe]; + length = pp->tranlen; + + /* Select NAK */ + usb_cstd_set_nak(pp, pipe); + + /* Set data count */ + g_usb_pstd_data_cnt[pipe] = length; + + /* Set data pointer */ + gp_usb_pstd_data[pipe] = (uint8_t *) pp->p_tranadr; + + /* BEMP Status Clear */ + hw_usb_clear_status_bemp(pp, pipe); + + /* BRDY Status Clear */ + hw_usb_clear_sts_brdy(pp, pipe); + + /* Pipe number to FIFO port select */ + useport = usb_pstd_pipe2fport(pp, pipe); + + /* Check use FIFO access */ + switch (useport) + { + /* CFIFO use */ + case USB_CUSE: + { + /* Buffer to FIFO data write */ + usb_pstd_buf_to_fifo(pipe, useport, pp); + + /* Set BUF */ + usb_cstd_set_buf(pp, pipe); + + break; + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* D0FIFO DMA */ + case USB_D0USE: + + /* D1FIFO DMA */ + case USB_D1USE: + { + if (USB_CFG_IP0 == pp->ip) + { + ip = USB_IP0; + } + else /* if (USB_CFG_IP0 == pp->ip) */ + { + ip = USB_IP1; + } + + ch = usb_cstd_dma_ref_ch_no(pp, useport); + + /* Setting for use PIPE number */ + g_usb_cstd_dma_pipe[ip][ch] = pipe; + + /* Buffer size */ + g_usb_cstd_dma_fifo[ip][ch] = usb_cstd_get_buf_size(pp, pipe); + + /* Check data count */ + if (g_usb_pstd_data_cnt[pipe] < g_usb_cstd_dma_fifo[ip][ch]) + { + /* Transfer data size */ + g_usb_cstd_dma_size[ip][ch] = g_usb_pstd_data_cnt[pipe]; + } + else + { + /* Transfer data size */ + g_usb_cstd_dma_size[ip][ch] = g_usb_pstd_data_cnt[pipe] - + (g_usb_pstd_data_cnt[pipe] % g_usb_cstd_dma_fifo[ip][ch]); + } + + usb_cstd_dma_send_start(pp, pipe, useport); + + /* Set BUF */ + usb_cstd_set_buf(pp, pipe); + + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + default: + { + /* Access is NG */ + USB_PRINTF0("### USB-FW is not support\n"); + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_ERR, pp); + + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_send_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_write_data + * Description : Switch PIPE, request the USB FIFO to write data, and manage + * : the size of written data. + * Arguments : uint16_t pipe : Pipe no. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : uint16_t end_flag + ******************************************************************************/ +uint16_t usb_pstd_write_data (uint16_t pipe, uint16_t pipemode, usb_utr_t * p_utr) +{ + uint16_t size; + uint16_t count; + uint16_t buffer; + uint16_t mxps; + uint16_t end_flag; + uint16_t read_pid; + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("*** usb_pstd_write_data PipeNo ERROR %d\n", pipe); + + return USB_ERROR; /* Error */ + } + + /* Changes FIFO port by the pipe. */ + if ((USB_CUSE == pipemode) && (USB_PIPE0 == pipe)) + { + buffer = usb_cstd_is_set_frdy(p_utr, pipe, (uint16_t) USB_CUSE, (uint16_t) USB_ISEL); + } + else + { + buffer = usb_cstd_is_set_frdy(p_utr, pipe, pipemode, USB_FALSE); + } + + /* Check error */ + if (USB_FIFOERROR == buffer) + { + /* FIFO access error */ + return USB_FIFOERROR; + } + + /* Data buffer size */ + size = usb_cstd_get_buf_size(p_utr, pipe); + + /* Max Packet Size */ + mxps = usb_cstd_get_maxpacket_size(p_utr, pipe); + + /* Data size check */ + if (g_usb_pstd_data_cnt[pipe] <= (uint32_t) size) + { + count = (uint16_t) g_usb_pstd_data_cnt[pipe]; + + /* Data count check */ + if (0 == count) + { + /* Null Packet is end of write */ + end_flag = USB_WRITESHRT; + } + else if (0 != (count % mxps)) + { + /* Short Packet is end of write */ + end_flag = USB_WRITESHRT; + } + else + { + if (USB_PIPE0 == pipe) + { + /* Just Send Size */ + end_flag = USB_WRITING; + } + else + { + /* Write continues */ + end_flag = USB_WRITEEND; + } + } + } + else + { + /* Write continues */ + end_flag = USB_WRITING; + count = size; + } + + read_pid = usb_cstd_get_pid(p_utr, pipe); + usb_cstd_set_nak(p_utr, pipe); + + gp_usb_pstd_data[pipe] = usb_pstd_write_fifo(count, pipemode, gp_usb_pstd_data[pipe], p_utr); + + /* Check data count to remain */ + if (g_usb_pstd_data_cnt[pipe] < (uint32_t) size) + { + /* Clear data count */ + g_usb_pstd_data_cnt[pipe] = (uint32_t) 0U; + + /* Read CFIFOCTR */ + buffer = hw_usb_read_fifoctr(p_utr, pipemode); + + /* Check BVAL */ + if (0U == (buffer & USB_BVAL)) + { + /* Short Packet */ + hw_usb_set_bval(p_utr, pipemode); + } + } + else + { + /* Total data count - count */ + g_usb_pstd_data_cnt[pipe] -= count; + } + + hw_usb_clear_status_bemp(p_utr, pipe); + + /* USB_PID_BUF ? */ + if (USB_PID_BUF == (USB_PID & read_pid)) + { + usb_cstd_set_buf(p_utr, pipe); + } + + /* End or Err or Continue */ + return end_flag; +} + +/****************************************************************************** + * End of function usb_pstd_write_data + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_receive_start + * Description : Start data reception using CPU/DMA transfer to USB Host. + * Arguments : uint16_t pipe : Pipe no. + * Return value : none + ******************************************************************************/ +void usb_pstd_receive_start (uint16_t pipe) +{ + usb_utr_t * pp; + uint32_t length; + uint16_t mxps; + uint16_t useport; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t ip; + uint16_t ch; + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* Evacuation pointer */ + pp = g_p_usb_pstd_pipe[pipe]; + length = pp->tranlen; + + /* Select NAK */ + usb_cstd_set_nak(pp, pipe); + + /* Set data count */ + g_usb_pstd_data_cnt[pipe] = length; + + /* Set data pointer */ + gp_usb_pstd_data[pipe] = (uint8_t *) pp->p_tranadr; + + /* Pipe number to FIFO port select */ + useport = usb_pstd_pipe2fport(pp, pipe); + + /* Check use FIFO access */ + switch (useport) + { + /* CFIFO use */ + case USB_CUSE: + { + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(pp, pipe, useport, USB_FALSE); + + /* Max Packet Size */ + mxps = usb_cstd_get_maxpacket_size(pp, pipe); + if ((uint32_t) 0U != length) + { + /* Data length check */ + if ((uint32_t) 0U == (length % mxps)) + { + /* Set Transaction counter */ + usb_cstd_set_transaction_counter(pp, pipe, (uint16_t) (length / mxps)); + } + else + { + /* Set Transaction counter */ + usb_cstd_set_transaction_counter(pp, pipe, (uint16_t) ((length / mxps) + (uint32_t) 1U)); + } + } + + /* Set BUF */ + usb_cstd_set_buf(pp, pipe); + + /* Enable Ready Interrupt */ + hw_usb_set_brdyenb(pp, pipe); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(pp, pipe); + break; + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* D0FIFO DMA */ + case USB_D0USE: + + /* D1FIFOB DMA */ + case USB_D1USE: + { + if (USB_CFG_IP0 == pp->ip) + { + ip = USB_IP0; + } + else /* if (USB_CFG_IP0 == pp->ip) */ + { + ip = USB_IP1; + } + + ch = usb_cstd_dma_ref_ch_no(pp, useport); + + /* Setting for use PIPE number */ + g_usb_cstd_dma_pipe[ip][ch] = pipe; + + /* Buffer size */ + g_usb_cstd_dma_fifo[ip][ch] = usb_cstd_get_buf_size(pp, pipe); + + /* Transfer data size */ + g_usb_cstd_dma_size[ip][ch] = g_usb_pstd_data_cnt[pipe]; + usb_cstd_dma_rcv_start(pp, pipe, useport); + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + default: + { + USB_PRINTF0("### USB-FW is not support\n"); + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_ERR, pp); + + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_receive_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_read_data + * Description : Request to read data from USB FIFO, and manage the size of + * : the data read. + * Arguments : uint16_t pipe : Pipe no. + * : uint16_t pipemode : FIFO select(USB_CUSE,USB_DMA0,....) + * Return value : uint16_t end_flag + ******************************************************************************/ +uint16_t usb_pstd_read_data (uint16_t pipe, uint16_t pipemode, usb_utr_t * p_utr) +{ + uint16_t count; + uint16_t buffer; + uint16_t mxps; + uint16_t dtln; + uint16_t end_flag; + + if (USB_MAX_PIPE_NO < pipe) + { + USB_PRINTF1("*** usb_pstd_read_data PipeNo ERROR %d\n", pipe); + + return USB_ERROR; /* Error */ + } + + /* Changes FIFO port by the pipe. */ + buffer = usb_cstd_is_set_frdy(p_utr, pipe, pipemode, USB_FALSE); + if (USB_FIFOERROR == buffer) + { + /* FIFO access error */ + return USB_FIFOERROR; + } + + dtln = (uint16_t) (buffer & USB_DTLN); + + /* Max Packet Size */ + mxps = usb_cstd_get_maxpacket_size(p_utr, pipe); + + if (g_usb_pstd_data_cnt[pipe] < dtln) + { + /* Buffer Over ? */ + end_flag = USB_READOVER; + + /* Set NAK */ + usb_cstd_set_nak(p_utr, pipe); + + count = (uint16_t) g_usb_pstd_data_cnt[pipe]; + #if BSP_CFG_RTOS != 1 + g_usb_pstd_data_cnt[pipe] = dtln; + #endif /* BSP_CFG_RTOS != 1 */ + } + else if (g_usb_pstd_data_cnt[pipe] == dtln) + { + /* Just Receive Size */ + count = dtln; + if ((USB_PIPE0 == pipe) && (0 == (dtln % mxps))) + { + /* Just Receive Size */ + /* Peripheral Function */ + end_flag = USB_READING; + } + else + { + end_flag = USB_READEND; + + /* Set NAK */ + usb_cstd_set_nak(p_utr, pipe); + } + } + else + { + /* Continuous Receive data */ + count = dtln; + end_flag = USB_READING; + if (0 == count) + { + /* Null Packet receive */ + end_flag = USB_READSHRT; + + /* Select NAK */ + usb_cstd_set_nak(p_utr, pipe); + } + + if (0 != (count % mxps)) + { + /* Null Packet receive */ + end_flag = USB_READSHRT; + + /* Select NAK */ + usb_cstd_set_nak(p_utr, pipe); + } + } + + if (0 == dtln) + { + /* 0 length packet */ + /* Clear BVAL */ + hw_usb_set_bclr(p_utr, pipemode); + } + else + { + gp_usb_pstd_data[pipe] = usb_pstd_read_fifo(count, pipemode, gp_usb_pstd_data[pipe], p_utr); + } + + g_usb_pstd_data_cnt[pipe] -= count; + + /* End or Err or Continue */ + return end_flag; +} + +/****************************************************************************** + * End of function usb_pstd_read_data + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_data_end + * Description : Set USB registers as appropriate after data transmission/re- + * : ception, and call the callback function as transmission/recep- + * : tion is complete. + * Arguments : uint16_t pipe : Pipe no. + * : uint16_t status : Transfer status type. + * Return value : none + ******************************************************************************/ +void usb_pstd_data_end (uint16_t pipe, uint16_t status, usb_utr_t * p_utr) +{ + uint16_t useport; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t ip; + + if (USB_CFG_IP0 == p_utr->ip) + { + ip = USB_IP0; + } + else /* if (USB_CFG_IP0 == p_utr->ip) */ + { + ip = USB_IP1; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (USB_MAX_PIPE_NO < pipe) + { + return; /* Error */ + } + + /* PID = NAK */ + /* Set NAK */ + usb_cstd_set_nak(p_utr, pipe); + + /* Pipe number to FIFO port select */ + useport = usb_pstd_pipe2fport(p_utr, pipe); + + /* Disable Interrupt */ + /* Disable Ready Interrupt */ + hw_usb_clear_brdyenb(p_utr, pipe); + + /* Disable Not Ready Interrupt */ + hw_usb_clear_nrdyenb(p_utr, pipe); + + /* Disable Empty Interrupt */ + hw_usb_clear_bempenb(p_utr, pipe); + + /* Disable Transaction count */ + usb_cstd_clr_transaction_counter(p_utr, pipe); + + /* Check use FIFO */ + switch (useport) + { + /* CFIFO use */ + case USB_CUSE: + { + break; + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* D0FIFO DMA */ + case USB_D0USE: + { + /* DMA buffer clear mode clear */ + hw_usb_clear_dclrm(p_utr, useport); + if (USB_IP0 == ip) + { + hw_usb_set_mbw(p_utr, USB_D0USE, USB0_D0FIFO_MBW); + } + else if (USB_IP1 == ip) + { + hw_usb_set_mbw(p_utr, USB_D0USE, USB1_D0FIFO_MBW); + } + else + { + /* IP error */ + } + + break; + } + + /* D1FIFO DMA */ + case USB_D1USE: + { + /* DMA buffer clear mode clear */ + hw_usb_clear_dclrm(p_utr, useport); + if (USB_IP0 == ip) + { + hw_usb_set_mbw(p_utr, USB_D1USE, USB0_D1FIFO_MBW); + } + else if (USB_IP1 == ip) + { + hw_usb_set_mbw(p_utr, USB_D1USE, USB1_D1FIFO_MBW); + } + else + { + /* IP error */ + } + + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + default: + { + break; + } + } + + /* Call Back */ + if (USB_NULL != g_p_usb_pstd_pipe[pipe]) + { + /* Transfer information set */ + g_p_usb_pstd_pipe[pipe]->tranlen = g_usb_pstd_data_cnt[pipe]; + g_p_usb_pstd_pipe[pipe]->status = status; + g_p_usb_pstd_pipe[pipe]->pipectr = hw_usb_read_pipectr(p_utr, pipe); + g_p_usb_pstd_pipe[pipe]->keyword = pipe; + ((usb_cb_t) g_p_usb_pstd_pipe[pipe]->complete)(g_p_usb_pstd_pipe[pipe], USB_NULL, USB_NULL); + + #if (BSP_CFG_RTOS == 0) + g_p_usb_pstd_pipe[pipe] = (usb_utr_t *) USB_NULL; + #else /* (BSP_CFG_RTOS == 0) */ + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_pstd_pipe[pipe]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_pstd_pipe[pipe]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + g_p_usb_pstd_pipe[pipe] = (usb_utr_t *) USB_NULL; + usb_cstd_pipe_msg_re_forward(p_utr->ip, pipe); /* Get PIPE Transfer wait que and Message send to PCD */ + #endif /* (BSP_CFG_RTOS == 0) */ + } +} + +/****************************************************************************** + * End of function usb_pstd_data_end + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_brdy_pipe_process + * Description : Search for the PIPE No. that BRDY interrupt occurred, and + * : request data transmission/reception from the PIPE + * Arguments : uint16_t bitsts ; BRDYSTS Register & BRDYENB Register + * Return value : none + ******************************************************************************/ +void usb_pstd_brdy_pipe_process (usb_utr_t * p_utr, uint16_t bitsts) +{ + uint16_t useport; + uint16_t i; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + uint16_t buffer; + uint16_t maxps; + uint16_t set_dma_block_cnt; + uint16_t trans_dma_block_cnt; + uint16_t dma_ch; + uint16_t status; + #else /* #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + (void) *p_utr; + #endif /* #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i <= USB_MAX_PIPE_NO; i++) + { + if (0U != (bitsts & USB_BITSET(i))) + { + /* Interrupt check */ + hw_usb_clear_status_bemp(p_utr, i); + + if (USB_NULL != g_p_usb_pstd_pipe[i]) + { + /* Pipe number to FIFO port select */ + useport = usb_pstd_pipe2fport(p_utr, i); + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + if ((USB_D0USE == useport) || (USB_D1USE == useport)) + { + dma_ch = usb_cstd_dma_ref_ch_no(p_utr, useport); + + maxps = g_usb_cstd_dma_fifo[p_utr->ip][dma_ch]; + + /* DMA Transfer request disable */ + hw_usb_clear_dreqe(p_utr, useport); + + /* DMA stop */ + usb_cstd_dma_stop(p_utr, useport); + + /* Changes FIFO port by the pipe. */ + buffer = usb_cstd_is_set_frdy(p_utr, i, useport, USB_FALSE); + + set_dma_block_cnt = + (uint16_t) (((g_usb_pstd_data_cnt[g_usb_cstd_dma_pipe[p_utr->ip][dma_ch]] - 1) / + g_usb_cstd_dma_fifo[p_utr->ip][dma_ch]) + 1); + + trans_dma_block_cnt = usb_cstd_dma_get_crtb(p_utr); + + /* Get D0fifo Receive Data Length */ + g_usb_cstd_dma_size[p_utr->ip][dma_ch] = (uint32_t) (buffer & USB_DTLN); + if (set_dma_block_cnt > trans_dma_block_cnt) + { + if (0 != g_usb_cstd_dma_size[p_utr->ip][dma_ch]) + { + g_usb_cstd_dma_size[p_utr->ip][dma_ch] = + g_usb_cstd_dma_size[p_utr->ip][dma_ch] + + (uint32_t) ((set_dma_block_cnt - (trans_dma_block_cnt + 1)) * maxps); + } + else + { + g_usb_cstd_dma_size[p_utr->ip][dma_ch] = + (uint32_t) ((set_dma_block_cnt - (trans_dma_block_cnt)) * maxps); + } + } + + /* Check data count */ + if (g_usb_cstd_dma_size[p_utr->ip][dma_ch] == g_usb_pstd_data_cnt[i]) + { + status = USB_DATA_OK; + } + else if (g_usb_cstd_dma_size[p_utr->ip][dma_ch] > g_usb_pstd_data_cnt[i]) + { + status = USB_DATA_OVR; + } + else + { + status = USB_DATA_SHT; + } + + /* D0FIFO access DMA stop */ + usb_cstd_dfifo_end(p_utr, useport); + + /* End of data transfer */ + usb_pstd_data_end(i, status, p_utr); + + /* Set BCLR */ + hw_usb_set_bclr(p_utr, useport); + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (USB_CUSE == useport) + { + if (USB_BUF2FIFO == usb_cstd_get_pipe_dir(p_utr, i)) + { + /* Buffer to FIFO data write */ + usb_pstd_buf_to_fifo(i, useport, p_utr); + } + else + { + /* FIFO to Buffer data read */ + usb_pstd_fifo_to_buf(i, useport, p_utr); + } + } + } + } + } +} /* End of function usb_pstd_brdy_pipe_process() */ + +/****************************************************************************** + * Function Name : usb_pstd_nrdy_pipe_process + * Description : Search for PIPE No. that occurred NRDY interrupt, and execute + * : the process for PIPE when NRDY interrupt occurred + * Arguments : uint16_t bitsts ; NRDYSTS Register & NRDYENB Register + * Return value : none + ******************************************************************************/ +void usb_pstd_nrdy_pipe_process (usb_utr_t * p_utr, uint16_t bitsts) +{ + uint16_t buffer; + uint16_t i; + + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i <= USB_MAX_PIPE_NO; i++) + { + if (0 != (bitsts & USB_BITSET(i))) + { + /* Interrupt check */ + if (USB_NULL != g_p_usb_pstd_pipe[i]) + { + if (USB_TYPFIELD_ISO == usb_cstd_get_pipe_type(p_utr, i)) + { + /* Wait for About 60ns */ + buffer = hw_usb_read_frmnum(p_utr); + if (USB_OVRN == (buffer & USB_OVRN)) + { + /* @1 */ + /* End of data transfer */ + usb_pstd_forced_termination(i, (uint16_t) USB_DATA_OVR, p_utr); + USB_PRINTF1("###ISO OVRN %lu\n", (unsigned long) g_usb_pstd_data_cnt[i]); + } + else + { + /* @2 */ + /* End of data transfer */ + usb_pstd_forced_termination(i, (uint16_t) USB_DATA_ERR, p_utr); + } + } + else + { + /* Non processing. */ + } + } + } + } +} + +/****************************************************************************** + * End of function usb_pstd_nrdy_pipe_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_bemp_pipe_process + * Description : Search for PIPE No. that BEMP interrupt occurred, + * : and complete data transmission for the PIPE + * Arguments : uint16_t bitsts ; BEMPSTS Register & BEMPENB Register + * Return value : none + ******************************************************************************/ +void usb_pstd_bemp_pipe_process (usb_utr_t * p_utr, uint16_t bitsts) +{ + uint16_t buffer; + uint16_t i; + + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i <= USB_PIPE5; i++) + { + if (0 != (bitsts & USB_BITSET(i))) + { + /* Interrupt check */ + if ((USB_NULL != g_p_usb_pstd_pipe[i]) && (USB_ON != g_usb_cstd_bemp_skip[p_utr->ip][i])) + { + buffer = usb_cstd_get_pid(p_utr, i); + + /* MAX packet size error ? */ + if (USB_PID_STALL == (buffer & USB_PID_STALL)) + { + USB_PRINTF1("### STALL Pipe %d\n", i); + usb_pstd_forced_termination(i, (uint16_t) USB_DATA_STALL, p_utr); + } + else + { + if (USB_INBUFM != (hw_usb_read_pipectr(p_utr, i) & USB_INBUFM)) + { + g_usb_cstd_bemp_skip[p_utr->ip][i] = USB_ON; + + usb_pstd_data_end(i, (uint16_t) USB_DATA_NONE, p_utr); + } + else + { + /* set BEMP enable */ + hw_usb_set_bempenb(p_utr, i); + } + } + } + } + } + + /* WAIT_LOOP */ + for (i = USB_PIPE6; i <= USB_MAX_PIPE_NO; i++) + { + /* Interrupt check */ + if (0 != (bitsts & USB_BITSET(i))) + { + if (USB_NULL != g_p_usb_pstd_pipe[i]) + { + buffer = usb_cstd_get_pid(p_utr, i); + + /* MAX packet size error ? */ + if (USB_PID_STALL == (buffer & USB_PID_STALL)) + { + USB_PRINTF1("### STALL Pipe %d\n", i); + usb_pstd_forced_termination(i, (uint16_t) USB_DATA_STALL, p_utr); + } + else + { + /* End of data transfer */ + usb_pstd_data_end(i, (uint16_t) USB_DATA_NONE, p_utr); + } + } + } + } +} + +/****************************************************************************** + * End of function usb_pstd_bemp_pipe_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_pipe_table + * Description : Set pipe table. + * Arguments : Address for Endpoint descriptor + * Return value : Pipe no (USB_PIPE1->USB_PIPE9:OK, USB_NULL:Error) + ******************************************************************************/ +uint8_t usb_pstd_set_pipe_table (uint8_t * descriptor, usb_utr_t * p_utr, uint8_t class_info) +{ + uint8_t pipe_no; + uint16_t pipe_cfg; + uint16_t pipe_maxp; + #if defined(USB_HIGH_SPEED_MODULE) + uint16_t pipe_buf; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + /* Check Endpoint descriptor */ + if (USB_DT_ENDPOINT != descriptor[USB_DEV_B_DESCRIPTOR_TYPE]) + { + return USB_NULL; /* Error */ + } + + /* set pipe configuration value */ + switch ((uint16_t) (descriptor[USB_EP_B_ATTRIBUTES] & USB_EP_TRNSMASK)) + { + /* Bulk Endpoint */ + case USB_EP_BULK: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(send) */ + pipe_no = usb_pstd_get_pipe_no(USB_EP_BULK, USB_PIPE_DIR_IN, p_utr, class_info); + pipe_cfg = (uint16_t) (USB_TYPFIELD_BULK | USB_CFG_DBLB | USB_DIR_P_IN); + } + else + { + /* OUT(receive) */ + pipe_no = usb_pstd_get_pipe_no(USB_EP_BULK, USB_PIPE_DIR_OUT, p_utr, class_info); + pipe_cfg = (uint16_t) (USB_TYPFIELD_BULK | USB_CFG_DBLB | USB_SHTNAKFIELD | USB_DIR_P_OUT); + } + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_CFG_IP1 == p_utr->ip) + { + pipe_cfg |= (uint16_t) (USB_CFG_CNTMD); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + /* Interrupt Endpoint */ + case USB_EP_INT: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(send) */ + pipe_no = usb_pstd_get_pipe_no(USB_EP_INT, USB_PIPE_DIR_IN, p_utr, class_info); + pipe_cfg = (uint16_t) (USB_TYPFIELD_INT | USB_DIR_P_IN); + } + else + { + /* OUT(receive) */ + pipe_no = usb_pstd_get_pipe_no(USB_EP_INT, USB_PIPE_DIR_OUT, p_utr, class_info); + pipe_cfg = (uint16_t) (USB_TYPFIELD_INT | USB_DIR_P_OUT); + } + + break; + } + + case USB_EP_ISO: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(send) */ + pipe_no = usb_pstd_get_pipe_no(USB_EP_ISO, USB_PIPE_DIR_IN, p_utr, class_info); + pipe_cfg = (uint16_t) (USB_TYPFIELD_ISO | USB_CFG_DBLB | USB_DIR_P_IN); + } + else + { + /* OUT(receive) */ + pipe_no = usb_pstd_get_pipe_no(USB_EP_ISO, USB_PIPE_DIR_OUT, p_utr, class_info); + pipe_cfg = (uint16_t) (USB_TYPFIELD_ISO | USB_CFG_DBLB | USB_SHTNAKFIELD | USB_DIR_P_OUT); + } + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_CFG_IP1 == p_utr->ip) + { + pipe_cfg |= (uint16_t) (USB_CFG_CNTMD); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + default: + { + return USB_NULL; /* Error */ + break; + } + } + + if ((USB_NULL != pipe_no) && (USB_TRUE != g_usb_pipe_table[p_utr->ip][pipe_no].use_flag)) + { + /* Endpoint number set */ + pipe_cfg = (uint16_t) (pipe_cfg | (uint16_t) (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_NUMMASK)); + + /* set max packet size */ + pipe_maxp = (uint16_t) descriptor[USB_EP_B_MAXPACKETSIZE_L]; + pipe_maxp = (uint16_t) (pipe_maxp | ((uint16_t) descriptor[USB_EP_B_MAXPACKETSIZE_H] << 8)); + + #if (BSP_CFG_RTOS == 1) + tx_semaphore_create(&g_usb_peri_usbx_sem[pipe_no], "USB_FSP_SEMX", 0); + #endif /* #if (BSP_CFG_RTOS == 1) */ + + /* Set Pipe table block */ + g_usb_pipe_table[p_utr->ip][pipe_no].use_flag = USB_TRUE; + g_usb_pipe_table[p_utr->ip][pipe_no].pipe_cfg = pipe_cfg; + g_usb_pipe_table[p_utr->ip][pipe_no].pipe_maxp = pipe_maxp; + g_usb_pipe_table[p_utr->ip][pipe_no].pipe_peri = USB_NULL; + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_CFG_IP1 == p_utr->ip) + { + pipe_buf = usb_pstd_get_pipe_buf_value(pipe_no); + g_usb_pipe_table[p_utr->ip][pipe_no].pipe_buf = pipe_buf; + } + else + { + (void) pipe_buf; + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + else + { + pipe_no = USB_NULL; /* Error */ + } + + return pipe_no; +} /* eof usb_pstd_set_pipe_table() */ + +/****************************************************************************** + * Function Name : usb_pstd_clr_pipe_table + * Description : Clear pipe table. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_clr_pipe_table (uint8_t usb_ip) +{ + uint8_t pipe_no; + + /* Search use pipe block */ + /* WAIT_LOOP */ + for (pipe_no = USB_MIN_PIPE_NO; pipe_no < (USB_MAX_PIPE_NO + 1); pipe_no++) + { + /* Check use block */ + if (USB_TRUE == g_usb_pipe_table[usb_ip][pipe_no].use_flag) + { + /* Clear use block */ + g_usb_pipe_table[usb_ip][pipe_no].use_flag = USB_FALSE; + g_usb_pipe_table[usb_ip][pipe_no].pipe_cfg = USB_NULL; + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_CFG_IP1 == usb_ip) + { + g_usb_pipe_table[usb_ip][pipe_no].pipe_buf = USB_NULL; + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + g_usb_pipe_table[usb_ip][pipe_no].pipe_maxp = USB_NULL; + g_usb_pipe_table[usb_ip][pipe_no].pipe_peri = USB_NULL; + } + } + + #if defined(USB_CFG_PCDC_USE) + g_usb_pcdc_bulk_in_pipe[usb_ip] = USB_NULL; + g_usb_pcdc_bulk_out_pipe[usb_ip] = USB_NULL; + g_usb_pcdc_int_in_pipe[usb_ip] = USB_NULL; + #if defined(USB_CFG_PCDC2_USE) + g_usb_pcdc2_bulk_in_pipe[usb_ip] = USB_NULL; + g_usb_pcdc2_bulk_out_pipe[usb_ip] = USB_NULL; + g_usb_pcdc2_int_in_pipe[usb_ip] = USB_NULL; + #endif + #endif + #if defined(USB_CFG_PHID_USE) + g_usb_phid_int_in_pipe[usb_ip] = USB_NULL; + g_usb_phid_int_out_pipe[usb_ip] = USB_NULL; + #if defined(USB_CFG_PHID2_USE) + g_usb_phid2_int_in_pipe[usb_ip] = USB_NULL; + g_usb_phid2_int_out_pipe[usb_ip] = USB_NULL; + #endif + #endif + + #if defined(USB_CFG_PMSC_USE) + g_usb_pmsc_bulk_in_pipe[usb_ip] = USB_NULL; + g_usb_pmsc_bulk_out_pipe[usb_ip] = USB_NULL; + #endif + + #if defined(USB_CFG_PPRN_USE) + g_usb_pprn_bulk_in_pipe[usb_ip] = USB_NULL; + g_usb_pprn_bulk_out_pipe[usb_ip] = USB_NULL; + #endif + + #if defined(USB_CFG_PAUD_USE) + g_usb_paud_iso_in_pipe[usb_ip] = USB_NULL; + g_usb_paud_iso_out_pipe[usb_ip] = USB_NULL; + #endif +} /* eof usb_pstd_clr_pipe_table() */ + +/****************************************************************************** + * Function Name : usb_pstd_set_pipe_reg + * Description : Set USB Pipe registers. (Use Pipe All) + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_set_pipe_reg (usb_utr_t * p_utr) +{ + uint8_t pipe_no; + + uint16_t buf; + + /* Search use pipe block */ + /* WAIT_LOOP */ + for (pipe_no = USB_MIN_PIPE_NO; pipe_no < (USB_MAX_PIPE_NO + 1); pipe_no++) + { + /* Check use block */ + if (USB_TRUE == g_usb_pipe_table[p_utr->ip][pipe_no].use_flag) + { + /* Current FIFO port Clear */ + buf = hw_usb_read_fifosel(p_utr, USB_CUSE); + if ((buf & USB_CURPIPE) == pipe_no) + { + usb_cstd_chg_curpipe(p_utr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, USB_FALSE); + } + + buf = hw_usb_read_fifosel(p_utr, USB_D0USE); + if ((buf & USB_CURPIPE) == pipe_no) + { + usb_cstd_chg_curpipe(p_utr, (uint16_t) USB_PIPE0, (uint16_t) USB_D0USE, USB_FALSE); + } + + buf = hw_usb_read_fifosel(p_utr, USB_D1USE); + if ((buf & USB_CURPIPE) == pipe_no) + { + usb_cstd_chg_curpipe(p_utr, (uint16_t) USB_PIPE0, (uint16_t) USB_D1USE, USB_FALSE); + } + + /* Initialization of registers associated with specified pipe. */ + usb_cstd_pipe_init(p_utr, pipe_no); + } + } +} /* eof usb_pstd_set_pipe_reg() */ + +/****************************************************************************** + * Function Name : usb_pstd_clr_pipe_reg + * Description : Clear Pipe registers. (Use Pipe All) + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_clr_pipe_reg (usb_utr_t * p_utr) +{ + uint8_t pipe_no; + + /* Search use pipe block */ + /* WAIT_LOOP */ + for (pipe_no = USB_MIN_PIPE_NO; pipe_no < (USB_MAX_PIPE_NO + 1); pipe_no++) + { + /* Check use block */ + if (USB_TRUE == g_usb_pipe_table[p_utr->ip][pipe_no].use_flag) + { + /* Clear specified pipe configuration register. */ + usb_cstd_clr_pipe_cnfg(p_utr, pipe_no); + } + } +} /* eof usb_pstd_clr_pipe_reg() */ + +/****************************************************************************** + * Function Name : usb_pstd_get_pipe_no + * Description : Get empty PIPE resource + * Arguments : uint8_t type : Transfer Type.(USB_EP_BULK/USB_EP_INT) + * : uint8_t dir : (USB_PIPE_DIR_IN/USB_PIPE_DIR_OUT) + * Return value : Pipe no (USB_PIPE1->USB_PIPE9:OK, USB_NULL:Error) + ******************************************************************************/ +uint8_t usb_pstd_get_pipe_no (uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint8_t class_info) +{ + uint8_t pipe = USB_NULL; + uint8_t idx = USB_NULL; + (void) type; + (void) dir; + (void) p_utr; + (void) class_info; + (void) idx; + + #if defined(USB_CFG_PCDC_USE) + if (USB_IFCLS_CDCD == class_info) + { + if (USB_EP_BULK == type) + { + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + /* Check if the pipe is free */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Check direction*/ + if (USB_PIPE_DIR_IN == dir) + { + /*Check if the pipe bulk in is not allocated for pcdc class*/ + if (USB_NULL == g_usb_pcdc_bulk_in_pipe[p_utr->ip]) + { + g_usb_pcdc_bulk_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = USB_CLASS_INTERNAL_PCDC + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_pcdc_bulk_in_pipe[p_utr->ip]; + break; + } + + #if defined(USB_CFG_PCDC2_USE) + + /*Check if the pipe bulk in is not allocated for pcdc2*/ + if (USB_NULL == g_usb_pcdc2_bulk_in_pipe[p_utr->ip]) + { + g_usb_pcdc2_bulk_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PCDC2 * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_pcdc2_bulk_in_pipe[p_utr->ip]; + break; + } + #endif + } + else + { + /*Check if the pipe bulk out is not allocated for pcdc*/ + if (USB_NULL == g_usb_pcdc_bulk_out_pipe[p_utr->ip]) + { + g_usb_pcdc_bulk_out_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = USB_CLASS_INTERNAL_PCDC + !dir; + g_usb_pipe_peri[idx] = g_usb_pcdc_bulk_out_pipe[p_utr->ip]; + break; + } + + #if defined(USB_CFG_PCDC2_USE) + + /*Check if the pipe bulk out is not allocated for pcdc2*/ + if (USB_NULL == g_usb_pcdc2_bulk_out_pipe[p_utr->ip]) + { + g_usb_pcdc2_bulk_out_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PCDC2 * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_pcdc2_bulk_out_pipe[p_utr->ip]; + break; + } + #endif + } + } + } + } + } + + if (USB_IFCLS_CDCC == class_info) + { + if (USB_EP_INT == type) + { + if (USB_PIPE_DIR_IN == dir) + { + for (pipe = USB_INT_PIPE_START; pipe < (USB_INT_PIPE_END + 1); pipe++) + { + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + if (USB_NULL == g_usb_pcdc_int_in_pipe[p_utr->ip]) + { + g_usb_pcdc_int_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PCDCC * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_pcdc_int_in_pipe[p_utr->ip]; + break; + } + + #if defined(USB_CFG_PCDC2_USE) + + /*Check if the int pipe is not allocated for pcdc2*/ + if (USB_NULL == g_usb_pcdc2_int_in_pipe[p_utr->ip]) + { + g_usb_pcdc2_int_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PCDCC2 * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_pcdc2_int_in_pipe[p_utr->ip]; + break; + } + #endif + } + } + } + } + } + #endif /* defined(USB_CFG_PCDC_USE) */ + + #if defined(USB_CFG_PPRN_USE) + if (USB_IFCLS_PRN == class_info) + { + if (USB_EP_BULK == type) + { + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + /* Check if the pipe is free */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /*Check if the pipe bulk in is not allocated for pprn class*/ + if (USB_NULL == g_usb_pprn_bulk_in_pipe[p_utr->ip]) + { + g_usb_pprn_bulk_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PPRN * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_pprn_bulk_in_pipe[p_utr->ip]; + break; + } + } + else + { + /*Check if the pipe bulk out is not allocated for pprn class*/ + if (USB_NULL == g_usb_pprn_bulk_out_pipe[p_utr->ip]) + { + g_usb_pprn_bulk_out_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PPRN * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_pprn_bulk_out_pipe[p_utr->ip]; + break; + } + } + } + } + } + } + #endif /* defined(USB_CFG_PPRN_USE) */ + + #if defined(USB_CFG_PHID_USE) + if (USB_IFCLS_HID == class_info) + { + if (USB_EP_INT == type) + { + for (pipe = USB_INT_PIPE_START; pipe < (USB_INT_PIPE_END + 1); pipe++) + { + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /*Check if the pipe interrupt in is not allocated for phid class*/ + if (USB_NULL == g_usb_phid_int_in_pipe[p_utr->ip]) + { + g_usb_phid_int_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PHID * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_phid_int_in_pipe[p_utr->ip]; + break; + } + + #if defined(USB_CFG_PHID2_USE) + + /*Check if the pipe interrupt in is not allocated for phid2 class*/ + if (USB_NULL == g_usb_phid2_int_in_pipe[p_utr->ip]) + { + g_usb_phid2_int_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PHID2 * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_phid2_int_in_pipe[p_utr->ip]; + break; + } + #endif + } + else + { + /*Check if the pipe interrupt out is not allocated for phid class*/ + if (USB_NULL == g_usb_phid_int_out_pipe[p_utr->ip]) + { + g_usb_phid_int_out_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PHID * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_phid_int_out_pipe[p_utr->ip]; + break; + } + + #if defined(USB_CFG_PHID2_USE) + + /*Check if the pipe interrupt out is not allocated for phid2 class*/ + if (USB_NULL == g_usb_phid2_int_out_pipe[p_utr->ip]) + { + g_usb_phid2_int_out_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PHID2 * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_phid2_int_out_pipe[p_utr->ip]; + break; + } + #endif + } + } + } + } + } + #endif /* defined(USB_CFG_PHID_USE) */ + + #if defined(USB_CFG_PMSC_USE) + if (USB_IFCLS_MAS == class_info) + { + if (USB_EP_BULK == type) + { + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + /* Check if the pipe is free */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /*Check if the pipe bulk in is not allocated for pmsc class*/ + if (USB_NULL == g_usb_pmsc_bulk_in_pipe[p_utr->ip]) + { + g_usb_pmsc_bulk_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + break; + } + } + else + { + /*Check if the pipe bulk out is not allocated for pmsc class*/ + if (USB_NULL == g_usb_pmsc_bulk_out_pipe[p_utr->ip]) + { + g_usb_pmsc_bulk_out_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + break; + } + } + } + } + } + } + #endif /* defined(USB_CFG_PMSC_USE) */ + + #if defined(USB_CFG_PAUD_USE) + if (USB_IFCLS_AUD == class_info) + { + if (USB_EP_ISO == type) + { + /* Isochronous PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_ISO_PIPE_START; pipe < (USB_ISO_PIPE_END + 1); pipe++) + { + /* Check if the pipe is free */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + if (USB_PIPE_DIR_IN == dir) + { + /*Check if the pipe iso in is not allocated for paud class*/ + if (USB_NULL == g_usb_paud_iso_in_pipe[p_utr->ip]) + { + g_usb_paud_iso_in_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PAUD * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_paud_iso_in_pipe[p_utr->ip]; + break; + } + } + else + { + /*Check if the pipe iso out is not allocated for paud class*/ + if (USB_NULL == g_usb_paud_iso_out_pipe[p_utr->ip]) + { + g_usb_paud_iso_out_pipe[p_utr->ip] = pipe; /* Set Free pipe */ + idx = (USB_CLASS_INTERNAL_PAUD * 2) + !dir; /*Calculate index*/ + g_usb_pipe_peri[idx] = g_usb_paud_iso_out_pipe[p_utr->ip]; + break; + } + } + } + } + } + } + #endif /* defined(USB_CFG_PAUD_USE) */ + + #if defined(USB_CFG_PVND_USE) + if (USB_IFCLS_VEN == class_info) + { + if (USB_EP_BULK == type) + { + /* BULK PIPE Loop */ + /* WAIT_LOOP */ + for (pipe = USB_BULK_PIPE_START; pipe < (USB_BULK_PIPE_END + 1); pipe++) + { + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* Check if the pipe is free */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Check direction and transfer validity */ + if (((dir == USB_PIPE_DIR_IN) && (p_utr->p_transfer_tx != 0)) || + ((dir != USB_PIPE_DIR_IN) && (p_utr->p_transfer_rx != 0))) + { + /* Return free bulk in/bulk out pipe */ + break; + } + } + #else /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Return free bulk in/bulk out pipe */ + break; + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + } + } + + if (USB_EP_INT == type) + { + /* Interrupt PIPE Loop */ + /* WAIT_LOOP */ + #if defined(USB_NO_COMPOSITE_DEVICE) + for (pipe = USB_INT_PIPE_START; pipe < (USB_INT_PIPE_END + 1); pipe++) + #else + for (pipe = USB_MAX_PIPE_NO; pipe >= USB_INT_PIPE_START; pipe--) + #endif + { + /* Check Free pipe */ + if (USB_FALSE == g_usb_pipe_table[p_utr->ip][pipe].use_flag) + { + /* Return free int pipe */ + break; + } + } + } + } + #endif /* defined(USB_CFG_PVND_USE) */ + + return pipe; +} + + #if defined(USB_HIGH_SPEED_MODULE) + +/****************************************************************************** + * Function Name : usb_pstd_get_pipe_buf_value + * Description : Get Value for USBA Module PIPE BUF REG. + * Arguments : Pipe no. + * Return value : PIPE BUF set value. + ******************************************************************************/ +uint16_t usb_pstd_get_pipe_buf_value (uint16_t pipe_no) +{ + uint16_t pipe_buf = 0; + + #if defined(USB_NO_COMPOSITE_DEVICE) + #if defined(USB_CFG_PCDC_USE) + if (g_usb_pcdc_bulk_in_pipe[USB_IP1] == pipe_no) + { + #if USB_CFG_DTC == USB_CFG_ENABLE + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(8U)); + #else /* USB_CFG_DTC == USB_CFG_ENABLE */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + } + else if (g_usb_pcdc_bulk_out_pipe[USB_IP1] == pipe_no) + { + #if USB_CFG_DTC == USB_CFG_ENABLE + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(40U)); + #else /* USB_CFG_DTC == USB_CFG_ENABLE */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(72U)); + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + } + else + { + /* Do nothing. */ + } + #endif /* defined(USB_CFG_PCDC_USE) */ + + #if defined(USB_CFG_PPRN_USE) + if (g_usb_pprn_bulk_in_pipe[USB_IP1] == pipe_no) + { + #if USB_CFG_DTC == USB_CFG_ENABLE + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(8U)); + #else /* USB_CFG_DTC == USB_CFG_ENABLE */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + } + else if (g_usb_pprn_bulk_out_pipe[USB_IP1] == pipe_no) + { + #if USB_CFG_DTC == USB_CFG_ENABLE + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(40U)); + #else /* USB_CFG_DTC == USB_CFG_ENABLE */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(72U)); + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + } + else + { + /* Do nothing. */ + } + #endif /* defined(USB_CFG_PPRN_USE) */ + + #if defined(USB_CFG_PMSC_USE) + if (g_usb_pmsc_bulk_in_pipe[USB_IP1] == pipe_no) + { + #if USB_CFG_DTC == USB_CFG_ENABLE + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(8U)); + #else /* USB_CFG_DTC == USB_CFG_ENABLE */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + } + else if (g_usb_pmsc_bulk_out_pipe[USB_IP1] == pipe_no) + { + #if USB_CFG_DTC == USB_CFG_ENABLE + pipe_buf = (USB_BUF_SIZE(1024U) | USB_BUF_NUMB(40U)); + #else /* USB_CFG_DTC == USB_CFG_ENABLE */ + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(72U)); + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + } + else + { + /* Do nothing. */ + } + #endif /* defined(USB_CFG_PMSC_USE) */ + + #if defined(USB_CFG_PVND_USE) + switch (pipe_no) + { + case USB_PIPE1: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(8U)); + break; + } + + case USB_PIPE2: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(24U)); + break; + } + + case USB_PIPE3: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(40U)); + break; + } + + case USB_PIPE4: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(56U)); + break; + } + + case USB_PIPE5: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(72U)); + break; + } + + default: + { + /* Error */ + break; + } + } + #endif /* defined(USB_CFG_PVND_USE) */ + + #if defined(USB_CFG_PAUD_USE) + if (g_usb_paud_iso_in_pipe[USB_IP1] == pipe_no) + { + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(8U)); + } + else if (g_usb_paud_iso_out_pipe[USB_IP1] == pipe_no) + { + pipe_buf = (USB_BUF_SIZE(2048U) | USB_BUF_NUMB(72U)); + } + else + { + /*Do nothing.*/ + } + #endif /* defined(USB_CFG_PAUD_USE) */ + #else /* defined(USB_NO_COMPOSITE_DEVICE) */ + switch (pipe_no) + { + case USB_PIPE1: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(8U)); + break; + } + + case USB_PIPE2: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(24U)); + break; + } + + case USB_PIPE3: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(40U)); + break; + } + + case USB_PIPE4: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(56U)); + break; + } + + case USB_PIPE5: + { + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(72U)); + break; + } + + default: + { + /* Error */ + break; + } + } + #endif /* defined(USB_NO_COMPOSITE_DEVICE) */ + + return pipe_buf; +} /* End of function usb_pstd_get_pipe_buf_value() */ + + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_psignal.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_psignal.c new file mode 100644 index 0000000000..272fe31e3b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_psignal.c @@ -0,0 +1,231 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS == 1) + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_api.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_system.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_utility.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_device_stack.h" +#endif /* #if (BSP_CFG_RTOS == 1) */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + #if USB_CFG_BC == USB_CFG_ENABLE +extern uint16_t g_usb_bc_detect; + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + + #if (BSP_CFG_RTOS == 1) +extern TX_SEMAPHORE g_usb_peri_usbx_sem[USB_MAX_PIPE_NO + 1]; +extern bool g_usb_peri_usbx_is_detach[USB_MAX_PIPE_NO + 1]; + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Renesas Abstracted Peripheral signal control functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_bus_reset + * Description : A USB bus reset was issued by the host. Execute relevant pro- + * : cessing. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_bus_reset (usb_utr_t * p_utr) +{ + uint16_t connect_info; + + /* Bus Reset */ + usb_pstd_busreset_function(); + + /* Memory clear */ + usb_pstd_clr_mem(); + connect_info = usb_cstd_port_speed(p_utr); + + #if (BSP_CFG_RTOS == 1) + switch (connect_info) + { + case USB_HSCONNECT: + { + _ux_system_slave->ux_system_slave_speed = (uint32_t) UX_HIGH_SPEED_DEVICE; + break; + } + + case USB_FSCONNECT: + { + _ux_system_slave->ux_system_slave_speed = (uint32_t) UX_FULL_SPEED_DEVICE; + break; + } + + case USB_LSCONNECT: + { + _ux_system_slave->ux_system_slave_speed = (uint32_t) UX_LOW_SPEED_DEVICE; + break; + } + + default: + { + break; + } + } + #endif /* #if (BSP_CFG_RTOS == 1) */ + + /* Callback */ + if (USB_NULL != g_usb_pstd_driver.devdefault) + { + #if USB_CFG_BC == USB_CFG_ENABLE + (*g_usb_pstd_driver.devdefault)(p_utr, connect_info, g_usb_bc_detect); + #else /* USB_CFG_BC == USB_CFG_ENABLE */ + (*g_usb_pstd_driver.devdefault)(p_utr, connect_info, USB_NULL); + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + + #if (BSP_CFG_RTOS == 1) + usb_peri_usbx_initialize_complete(); + #endif /* #if (BSP_CFG_RTOS == 1) */ + } + + /* DCP configuration register (0x5C) */ + hw_usb_write_dcpcfg(p_utr, 0); + + /* DCP maxpacket size register (0x5E) */ + hw_usb_write_dcpmxps(p_utr, g_usb_pstd_driver.p_devicetbl[USB_DEV_MAX_PKT_SIZE]); +} + +/****************************************************************************** + * End of function usb_pstd_bus_reset + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_attach_process + * Description : USB attach setting. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_attach_process (usb_utr_t * p_utr) +{ + usb_cpu_delay_xms((uint16_t) 10); + #if USB_CFG_BC == USB_CFG_ENABLE + usb_pstd_bc_detect_process(p_utr); + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + hw_usb_pset_dprpu(p_utr->ip); +} + +/****************************************************************************** + * End of function usb_pstd_attach_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_detach_process + * Description : Initialize USB registers for detaching, and call the callback + * : function that completes the detach. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_detach_process (usb_utr_t * p_utr) +{ + uint16_t i; + + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_clear_cnen(p_utr); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + /* Pull-up disable */ + hw_usb_pclear_dprpu(p_utr->ip); + + /* Configuration number */ + g_usb_pstd_config_num = 0; + + /* Remote wakeup enable flag */ + g_usb_pstd_remote_wakeup = USB_FALSE; + + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i < (USB_MAX_PIPE_NO + 1); i++) + { + if (USB_TRUE == g_usb_pipe_table[p_utr->ip][i].use_flag) + { + usb_pstd_forced_termination(i, (uint16_t) USB_DATA_STOP, p_utr); + usb_cstd_clr_pipe_cnfg(p_utr, i); + #if (BSP_CFG_RTOS == 1) + g_usb_peri_usbx_is_detach[i] = USB_YES; + tx_semaphore_put(&g_usb_peri_usbx_sem[i]); + tx_semaphore_delete(&g_usb_peri_usbx_sem[i]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + } + } + + /* Callback */ + if (USB_NULL != g_usb_pstd_driver.devdetach) + { + (*g_usb_pstd_driver.devdetach)(p_utr, USB_POWERED, USB_NULL); + } +} + +/****************************************************************************** + * End of function usb_pstd_detach_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_suspend_process + * Description : Perform a USB peripheral suspend. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_suspend_process (usb_utr_t * p_utr) +{ + uint16_t intsts0; + uint16_t buf; + + /* Resume interrupt enable */ + hw_usb_pset_enb_rsme(p_utr->ip); + + intsts0 = hw_usb_read_intsts(p_utr->ip); + buf = hw_usb_read_syssts(p_utr); + if (((uint16_t) 0 != (intsts0 & USB_DS_SUSP)) && (USB_FS_JSTS == (buf & USB_LNST))) + { + /* Suspend */ + usb_pstd_stop_clock(p_utr->ip); + usb_pstd_suspend_function(); + + /* Callback */ + if (USB_NULL != g_usb_pstd_driver.devsuspend) + { + (*g_usb_pstd_driver.devsuspend)(p_utr, g_usb_pstd_remote_wakeup, USB_NULL); + } + } + + /* --- SUSPEND -> RESUME --- */ + else + { + /* RESM status clear */ + hw_usb_pclear_sts_resm(p_utr->ip); + + /* RESM interrupt disable */ + hw_usb_pclear_enb_rsme(p_utr->ip); + } +} + +/****************************************************************************** + * End of function usb_pstd_suspend_process + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdfunction.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdfunction.c new file mode 100644 index 0000000000..a29ea43f62 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdfunction.c @@ -0,0 +1,380 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include +#include +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS == 1) + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_api.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_system.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_utility.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_device_stack.h" +#endif /* #if (BSP_CFG_RTOS == 1) */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + #define NUM_STRING_DESC (32) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ + #if (BSP_CFG_RTOS == 1) +extern uint8_t g_usb_peri_usbx_is_configured[USB_NUM_USBIP]; + #endif /* (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 1) +static uint8_t * g_p_usbx_string_table[NUM_STRING_DESC]; +usb_descriptor_t g_usbx_descriptor; + +void usb_pstd_ux_descriptor_to_basic(usb_cfg_t * p_cfg); + + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Renesas Abstracted Peripheral standard function functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_feature_function + * Description : Process a SET_FEATURE request. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_set_feature_function (usb_utr_t * p_utr) +{ + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); +} + +/****************************************************************************** + * End of function usb_pstd_set_feature_function + ******************************************************************************/ + + #if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : usb_pstd_chk_vbsts + * Description : Return the VBUS status. + * Arguments : none + * Return : uint16_t connection status(ATTACH/DETACH) + ******************************************************************************/ +uint16_t usb_pstd_chk_vbsts (uint8_t usb_ip) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + uint16_t connect_info; + + /* VBUS chattering cut */ + /* WAIT_LOOP */ + do + { + buf1 = hw_usb_read_intsts(usb_ip); + usb_cpu_delay_1us((uint16_t) 10); + buf2 = hw_usb_read_intsts(usb_ip); + usb_cpu_delay_1us((uint16_t) 10); + buf3 = hw_usb_read_intsts(usb_ip); + } while (((buf1 & USB_VBSTS) != (buf2 & USB_VBSTS)) || ((buf2 & USB_VBSTS) != (buf3 & USB_VBSTS))); + + /* VBUS status judge */ + if ((uint16_t) 0 != (buf1 & USB_VBSTS)) + { + /* Attach */ + connect_info = USB_ATTACH; + } + else + { + /* Detach */ + connect_info = USB_DETACH; + } + + return connect_info; +} + +/****************************************************************************** + * End of function usb_pstd_chk_vbsts + ******************************************************************************/ + #endif /* #if (USB_UT_MODE == 0) */ + +/****************************************************************************** + * Function Name : usb_pstd_busreset_function + * Description : Processing for USB bus reset detection. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_busreset_function (void) +{ + /* Non processing. */ +} + +/****************************************************************************** + * End of function usb_pstd_busreset_function + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_suspend_function + * Description : Processing for suspend signal detection. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_suspend_function (void) +{ + /* Non processing. */ +} + +/****************************************************************************** + * End of function usb_pstd_suspend_function + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 1) + +/****************************************************************************** + * Function Name : usb_pstd_ux_descriptor_to_basic + * Description : conversion from USBX descriptor to USB basic descriptor + * Arguments : p_cfg : Pointer to USB basic configuration structure + * Return value : none + ******************************************************************************/ +void usb_pstd_ux_descriptor_to_basic (usb_cfg_t * p_cfg) +{ + uint8_t * start_address; + uint8_t * end_address; + uint8_t * p; + uint8_t index; + uint8_t num_string = 0; + uint32_t length; + + /* Check the speed and set the correct descriptor. */ + if (USB_SPEED_FS == p_cfg->usb_speed) + { + start_address = (uint8_t *) (_ux_system_slave->ux_system_slave_device_framework_full_speed); + length = _ux_system_slave->ux_system_slave_device_framework_length_full_speed; + } + else + { + start_address = (uint8_t *) (_ux_system_slave->ux_system_slave_device_framework_high_speed); + length = _ux_system_slave->ux_system_slave_device_framework_length_high_speed; + } + + end_address = (start_address + length); + + p = start_address; + while (p < end_address) + { + switch (*(p + 1)) + { + case USB_DT_DEVICE: + { + p_cfg->p_usb_reg->p_device = p; + break; + } + + case USB_DT_CONFIGURATION: + { + if (USB_SPEED_FS == p_cfg->usb_speed) + { + p_cfg->p_usb_reg->p_config_f = p; + } + else + { + p_cfg->p_usb_reg->p_config_h = p; + } + + break; + } + + case USB_SOFT_CHANGE: + { + if (USB_SPEED_FS == p_cfg->usb_speed) + { + p_cfg->p_usb_reg->p_config_f = p; + } + else + { + p_cfg->p_usb_reg->p_config_h = p; + } + + break; + } + + case USB_DT_OTHER_SPEED_CONF: + { + if (USB_SPEED_FS == p_cfg->usb_speed) + { + p_cfg->p_usb_reg->p_config_h = p; + } + else + { + p_cfg->p_usb_reg->p_config_f = p; + } + + break; + } + + case USB_DT_DEVICE_QUALIFIER: + { + p_cfg->p_usb_reg->p_qualifier = p; + break; + } + + default: + { + break; + } + } + + length = *p; + p = p + length; + } + + if (USB_SPEED_HS == p_cfg->usb_speed) + { + start_address = (uint8_t *) (_ux_system_slave->ux_system_slave_device_framework_full_speed); + length = _ux_system_slave->ux_system_slave_device_framework_length_full_speed; + + end_address = (start_address + length); + + p = start_address; + if (USB_NULL != p) + { + while (p < end_address) + { + if ((USB_DT_OTHER_SPEED_CONF == *(p + 1)) || (USB_SOFT_CHANGE == *(p + 1))) + { + p_cfg->p_usb_reg->p_config_f = p; + break; + } + + length = *p; + p = p + length; + } + } + } + + if (USB_NULL != _ux_system_slave->ux_system_slave_language_id_framework) + { + g_p_usbx_string_table[0] = _ux_system_slave->ux_system_slave_language_id_framework; + } + + if (USB_NULL != _ux_system_slave->ux_system_slave_string_framework) + { + start_address = (uint8_t *) (_ux_system_slave->ux_system_slave_string_framework); + length = (uint16_t) (_ux_system_slave->ux_system_slave_string_framework_length); + end_address = (start_address + length); + + p = start_address; + while (p < end_address) + { + index = *(p + 2); + g_p_usbx_string_table[index] = p; + length = *(p + 3); + num_string++; + p = p + length + 4; + } + } + + p_cfg->p_usb_reg->p_string = g_p_usbx_string_table; + p_cfg->p_usb_reg->num_string = (uint8_t) (num_string + 1); +} /* End of function usb_pdriver_init() */ + + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Function Name : usb_pdriver_init + * Description : + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pdriver_init (usb_instance_ctrl_t * ctrl, usb_cfg_t const * const cfg) +{ + uint16_t i; + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAX_EP_NO + 1); i++) + { + g_usb_pstd_eptbl_index[0][i] = 0; + g_usb_pstd_eptbl_index[1][i] = 0; + } + + /* WAIT_LOOP */ + for (i = 0; i < USB_ALT_NO; i++) + { + g_usb_pstd_alt_num[i] = 0; + } + + g_usb_pstd_test_mode_select = USB_NULL; + g_usb_pstd_req_type = USB_NULL; + g_usb_pstd_req_value = USB_NULL; + g_usb_pstd_req_index = USB_NULL; + g_usb_pstd_req_length = USB_NULL; + g_usb_pstd_pipe0_request = USB_OFF; + g_usb_pstd_std_request = USB_NO; + g_usb_peri_connected = USB_FALSE; + memset((void *) &g_usb_pstd_req_reg, 0, sizeof(usb_setup_t)); + g_usb_pstd_stall_cb = USB_NULL; + memset((void *) &g_usb_pstd_driver, 0, sizeof(usb_pcdreg_t)); + + /* WAIT_LOOP */ + for (i = 0; i < (USB_MAX_PIPE_NO + 1); i++) + { + gp_usb_pstd_data[i] = USB_NULL; + g_usb_pstd_data_cnt[i] = 0; + } + + /* WAIT_LOOP */ + for (i = 0; i < USB_EVENT_MAX; i++) + { + #if (BSP_CFG_RTOS == 0) + g_usb_cstd_event.code[i] = USB_STATUS_NONE; + #else /*(BSP_CFG_RTOS == 0)*/ + g_usb_cstd_event[i].event = USB_STATUS_NONE; + #endif /*(BSP_CFG_RTOS == 0)*/ + } + + /* WAIT_LOOP */ + for (i = USB_PIPE0; i <= USB_MAX_PIPE_NO; i++) + { + g_usb_pstd_stall_pipe[i] = USB_FALSE; + g_p_usb_pstd_pipe[i] = (usb_utr_t *) USB_NULL; + } + + g_usb_pstd_config_num = 0; /* Configuration number */ + g_usb_pstd_remote_wakeup = USB_FALSE; /* Remote wake up enable flag */ + + #if (BSP_CFG_RTOS == 1) + { + usb_cfg_t cfg_usbx; + cfg_usbx = *cfg; + cfg_usbx.p_usb_reg = &g_usbx_descriptor; + usb_pstd_ux_descriptor_to_basic(&cfg_usbx); + usb_peri_registration(ctrl, &cfg_usbx); + + g_usb_peri_usbx_is_configured[cfg->module_number] = USB_NO; + } + #else /* #if (BSP_CFG_RTOS == 1) */ + usb_peri_registration(ctrl, cfg); + #endif /* #if (BSP_CFG_RTOS == 1) */ +} /* End of function usb_pdriver_init() */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c new file mode 100644 index 0000000000..f11aee3087 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c @@ -0,0 +1,2167 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include +#include + +#include "inc/r_usb_typedef.h" +#include "inc/r_usb_extern.h" +#include "../hw/inc/r_usb_bitdefine.h" +#include "../hw/inc/r_usb_reg_access.h" + +#if defined(USB_CFG_PMSC_USE) + #include "r_usb_pmsc_api.h" +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if defined(USB_CFG_PCDC_USE) + #include "r_usb_pcdc_api.h" +#endif /* defined(USB_CFG_PCDC_USE) */ + +#if (BSP_CFG_RTOS == 1) + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_api.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_system.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_utility.h" + #include "../../../../../microsoft/azure-rtos/usbx/common/core/inc/ux_device_stack.h" +#endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ +#define STRING_BUFFER_LEN (256) +#define VALUE_FFH (0xFF) +#define FSP_SETUP_REQUEST (1) +#define FSP_SETUP_VALUE (2) +#define FSP_SETUP_LENGTH (6) +#if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE) + #define FSP_SETUP_REQUEST_TYPE (0) + #define FSP_SETUP_INDEX_L (4) + #define FSP_SETUP_INDEX_H (5) +#endif /* #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)*/ + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +#if (BSP_CFG_RTOS == 1) +extern void usb_peri_usbx_set_control_length(usb_setup_t * p_req); + +extern uint8_t g_usb_peri_usbx_is_configured[USB_NUM_USBIP]; +#endif /* #if (BSP_CFG_RTOS == 1) */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ +static void usb_pstd_get_status1(usb_utr_t * p_utr); +static void usb_pstd_get_descriptor1(usb_utr_t * p_utr); +static void usb_pstd_get_configuration1(usb_utr_t * p_utr); +static void usb_pstd_get_interface1(usb_utr_t * p_utr); +static void usb_pstd_clr_feature0(void); +static void usb_pstd_clr_feature3(usb_utr_t * p_utr); +static void usb_pstd_set_feature0(void); +static void usb_pstd_set_feature3(usb_utr_t * p_utr); +static void usb_pstd_set_address0(void); +static void usb_pstd_set_address3(usb_utr_t * p_utr); +static void usb_pstd_set_descriptor2(usb_utr_t * p_utr); +static void usb_pstd_set_configuration0(usb_utr_t * p_utr); +static void usb_pstd_set_configuration3(usb_utr_t * p_utr); +static void usb_pstd_set_interface0(usb_utr_t * p_utr); +static void usb_pstd_set_interface3(usb_utr_t * p_utr); +static void usb_pstd_synch_rame1(usb_utr_t * p_utr); + + #if (BSP_CFG_RTOS == 1) +static void usb_peri_class_request_usbx(usb_setup_t * p_req); +static void usb_peri_class_reqeust_usbx_get_data(usb_setup_t * p_req, usb_utr_t * p_utr); + + #endif /* #if (BSP_CFG_RTOS == 1) */ + + #if USB_CFG_REQUEST == USB_CFG_ENABLE +static void usb_pstd_request_event_set(usb_utr_t * p_utr); + + #endif /* USB_CFG_REQUEST == USB_CFG_ENABLE */ + + #if (BSP_CFG_RTOS == 1) +static uint8_t g_usbx_string[STRING_BUFFER_LEN]; + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Renesas Abstracted Peripheral standard request functions + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_stand_req0 + * Description : The idle and setup stages of a standard request from host. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_stand_req0 (usb_utr_t * p_utr) +{ + g_usb_pstd_std_request = USB_NO; + + switch ((g_usb_pstd_req_type & USB_BREQUEST)) + { + case USB_CLEAR_FEATURE: + { + usb_pstd_clr_feature0(); /* Clear Feature0 */ + break; + } + + case USB_SET_FEATURE: + { + usb_pstd_set_feature0(); /* Set Feature0 */ + break; + } + + case USB_SET_ADDRESS: + { + usb_pstd_set_address0(); /* Set Address0 */ + break; + } + + case USB_SET_CONFIGURATION: + { + usb_pstd_set_configuration0(p_utr); /* Set Configuration0 */ + break; + } + + case USB_SET_INTERFACE: + { + usb_pstd_set_interface0(p_utr); /* Set Interface0 */ + break; + } + + default: + { + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_stand_req0 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_stand_req1 + * Description : The control read data stage of a standard request from host. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_stand_req1 (usb_utr_t * p_utr) +{ + switch ((g_usb_pstd_req_type & USB_BREQUEST)) + { + case USB_GET_STATUS: + { + usb_pstd_get_status1(p_utr); /* Get Status1 */ + break; + } + + case USB_GET_DESCRIPTOR: + { + usb_pstd_get_descriptor1(p_utr); /* Get Descriptor1 */ + break; + } + + case USB_GET_CONFIGURATION: + { + usb_pstd_get_configuration1(p_utr); /* Get Configuration1 */ + break; + } + + case USB_GET_INTERFACE: + { + usb_pstd_get_interface1(p_utr); /* Get Interface1 */ + break; + } + + case USB_SYNCH_FRAME: + { + usb_pstd_synch_rame1(p_utr); /* Synch Frame */ + break; + } + + default: + { + usb_pstd_set_stall_pipe0(p_utr); /* Set pipe USB_PID_STALL */ + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_stand_req1 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_stand_req2 + * Description : The control write data stage of a standard request from host. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_stand_req2 (usb_utr_t * p_utr) +{ + if (USB_SET_DESCRIPTOR == (g_usb_pstd_req_type & USB_BREQUEST)) + { + /* Set Descriptor2 */ + usb_pstd_set_descriptor2(p_utr); + } + else + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_stand_req2 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_stand_req3 + * Description : Standard request process. This is for the status stage of a + * : control write where there is no data stage. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_stand_req3 (usb_utr_t * p_utr) +{ + usb_instance_ctrl_t ctrl; + + switch ((g_usb_pstd_req_type & USB_BREQUEST)) + { + case USB_CLEAR_FEATURE: + { + usb_pstd_clr_feature3(p_utr); /* ClearFeature3 */ + break; + } + + case USB_SET_FEATURE: + { + usb_pstd_set_feature3(p_utr); /* SetFeature3 */ + break; + } + + case USB_SET_ADDRESS: + { + usb_pstd_set_address3(p_utr); /* SetAddress3 */ + break; + } + + case USB_SET_CONFIGURATION: + { + usb_pstd_set_configuration3(p_utr); /* SetConfiguration3 */ + break; + } + + case USB_SET_INTERFACE: + { + usb_pstd_set_interface3(p_utr); /* SetInterface3 */ + break; + } + + default: + { + usb_pstd_set_stall_pipe0(p_utr); /* Set pipe USB_PID_STALL */ + break; + } + } + + #if (BSP_CFG_RTOS == 0 || BSP_CFG_RTOS == 2) && defined(USB_CFG_PAUD_USE) + if (USB_SET_INTERFACE == (g_usb_pstd_req_type & USB_BREQUEST)) + #else + if (USB_YES == g_usb_pstd_std_request) + #endif + { + ctrl.setup.request_type = g_usb_pstd_req_type; /* Request type */ + ctrl.setup.request_value = g_usb_pstd_req_value; /* Value */ + ctrl.setup.request_index = g_usb_pstd_req_index; /* Index */ + ctrl.setup.request_length = g_usb_pstd_req_length; /* Length */ + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + ctrl.module_number = p_utr->ip; + #if (BSP_CFG_RTOS == 1) + ctrl.p_data = (void *) tx_thread_identify(); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + ctrl.p_data = (void *) xTaskGetCurrentTaskHandle(); + #endif /* (BSP_CFG_RTOS == 1) */ + usb_set_event(USB_STATUS_REQUEST_COMPLETE, &ctrl); + + g_usb_pstd_std_request = USB_NO; + } + + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* Control transfer stop(end) */ +} + +/****************************************************************************** + * End of function usb_pstd_stand_req3 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_stand_req4 + * Description : The control read status stage of a standard request from host. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_stand_req4 (usb_utr_t * p_utr) +{ + usb_instance_ctrl_t ctrl; + + switch ((g_usb_pstd_req_type & USB_BREQUEST)) + { + case USB_GET_STATUS: + { + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* GetStatus4 */ + break; + } + + case USB_GET_DESCRIPTOR: + { + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* GetDescriptor4 */ + break; + } + + case USB_GET_CONFIGURATION: + { + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* GetConfiguration4 */ + break; + } + + case USB_GET_INTERFACE: + { + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* GetInterface4 */ + break; + } + + case USB_SYNCH_FRAME: + { + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* SynchFrame4 */ + break; + } + + default: + { + usb_pstd_set_stall_pipe0(p_utr); /* Set pipe USB_PID_STALL */ + break; + } + } + + if (USB_YES == g_usb_pstd_std_request) + { + ctrl.setup.request_type = g_usb_pstd_req_type; /* Request type */ + ctrl.setup.request_value = g_usb_pstd_req_value; /* Value */ + ctrl.setup.request_index = g_usb_pstd_req_index; /* Index */ + ctrl.setup.request_length = g_usb_pstd_req_length; /* Length */ + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + ctrl.module_number = p_utr->ip; + #if (BSP_CFG_RTOS == 1) + ctrl.p_data = (void *) tx_thread_identify(); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + ctrl.p_data = (void *) xTaskGetCurrentTaskHandle(); + #endif /* (BSP_CFG_RTOS == 1) */ + usb_set_event(USB_STATUS_REQUEST_COMPLETE, &ctrl); + + g_usb_pstd_std_request = USB_NO; + } + + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* Control transfer stop(end) */ +} + +/****************************************************************************** + * End of function usb_pstd_stand_req4 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_stand_req5 + * Description : The control write status stage of a standard request from host. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_stand_req5 (usb_utr_t * p_utr) +{ + usb_instance_ctrl_t ctrl; + + if (USB_SET_DESCRIPTOR == (g_usb_pstd_req_type & USB_BREQUEST)) + { + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + else + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + } + + if (USB_YES == g_usb_pstd_std_request) + { + ctrl.setup.request_type = g_usb_pstd_req_type; /* Request type */ + ctrl.setup.request_value = g_usb_pstd_req_value; /* Value */ + ctrl.setup.request_index = g_usb_pstd_req_index; /* Index */ + ctrl.setup.request_length = g_usb_pstd_req_length; /* Length */ + + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + ctrl.module_number = p_utr->ip; + #if (BSP_CFG_RTOS == 1) + ctrl.p_data = (void *) tx_thread_identify(); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + ctrl.p_data = (void *) xTaskGetCurrentTaskHandle(); + #endif /* (BSP_CFG_RTOS == 1) */ + + usb_set_event(USB_STATUS_REQUEST_COMPLETE, &ctrl); + + g_usb_pstd_std_request = USB_NO; + } + + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* Control transfer stop(end) */ +} + +/****************************************************************************** + * End of function usb_pstd_stand_req5 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_get_status1 + * Description : Analyze a Get Status command and process it. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_get_status1 (usb_utr_t * p_utr) +{ + static uint8_t tbl[2]; + uint16_t ep; + uint16_t buffer; + uint16_t pipe; + + #if defined(USB_CFG_OTG_USE) + if ((0 == g_usb_pstd_req_value) && (1 == g_usb_pstd_req_length)) + #else + if ((0 == g_usb_pstd_req_value) && (2 == g_usb_pstd_req_length)) + #endif + { + tbl[0] = 0; + tbl[1] = 0; + + /* Check request type */ + switch ((g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + case USB_DEVICE: + { + if (0 == g_usb_pstd_req_index) + { + /* Self powered / Bus powered */ + tbl[0] = usb_pstd_get_current_power(); + + /* Support remote wakeup ? */ + if (USB_TRUE == g_usb_pstd_remote_wakeup) + { + tbl[0] |= USB_GS_REMOTEWAKEUP; + } + + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) 2, tbl, p_utr); + } + + #if defined(USB_CFG_OTG_USE) + else if (USB_OTG_SELECTOR == g_usb_pstd_req_index) + { + tbl[0] = (uint8_t) _ux_system_otg->ux_system_otg_slave_role_swap_flag; + + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) 1, tbl, p_utr); + } + #endif /* defined(USB_CFG_OTG_USE) */ + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + case USB_INTERFACE: + { + if (USB_TRUE == usb_pstd_chk_configured(p_utr)) + { + if (g_usb_pstd_req_index < usb_pstd_get_interface_num()) + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) 2, tbl, p_utr); + } + else + { + /* Request error (not exist interface) */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + case USB_ENDPOINT: + { + /* Endpoint number */ + ep = (uint16_t) (g_usb_pstd_req_index & USB_EPNUMFIELD); + + /* Endpoint 0 */ + if (0 == ep) + { + buffer = hw_usb_read_dcpctr(p_utr->ip); + if ((uint16_t) 0 != (buffer & USB_PID_STALL)) + { + /* Halt set */ + tbl[0] = USB_GS_HALT; + } + + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) 2, tbl, p_utr); + } + /* EP1 to max */ + else if (ep <= USB_MAX_EP_NO) + { + if (USB_TRUE == usb_pstd_chk_configured(p_utr)) + { + pipe = usb_pstd_epadr2pipe(g_usb_pstd_req_index, p_utr); + if (USB_ERROR == pipe) + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + } + else + { + buffer = usb_cstd_get_pid(p_utr, pipe); + if ((uint16_t) 0 != (buffer & USB_PID_STALL)) + { + /* Halt set */ + tbl[0] = USB_GS_HALT; + } + + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) 2, tbl, p_utr); + } + } + else + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + default: + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + break; + } + } + } + else + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_get_status1 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_get_descriptor1 + * Description : Analyze a Get Descriptor command from host and process it. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_get_descriptor1 (usb_utr_t * p_utr) +{ + uint16_t len; + uint16_t idx; + uint8_t * p_table; + uint16_t connect_info; + #if (BSP_CFG_RTOS == 1) + uint8_t i = 0; + #endif /* #if (BSP_CFG_RTOS == 1) */ + + if (USB_DEVICE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + idx = (uint16_t) (g_usb_pstd_req_value & USB_DT_INDEX); + switch ((uint16_t) USB_GET_DT_TYPE(g_usb_pstd_req_value)) + { + /*---- Device descriptor ----*/ + case USB_DT_DEVICE: + { + if (((uint16_t) 0 == g_usb_pstd_req_index) && ((uint16_t) 0 == idx)) + { + p_table = g_usb_pstd_driver.p_devicetbl; + if (g_usb_pstd_req_length < p_table[0]) + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) g_usb_pstd_req_length, p_table, p_utr); + } + else + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) p_table[0], p_table, p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + /*---- Configuration descriptor ----*/ + case USB_DT_CONFIGURATION: + { + if ((0 == g_usb_pstd_req_index) && ((uint16_t) 0 == idx)) + { + connect_info = usb_cstd_port_speed(p_utr); + if (USB_HSCONNECT == connect_info) + { + p_table = g_usb_pstd_driver.p_othertbl; + } + else + { + p_table = g_usb_pstd_driver.p_configtbl; + } + + len = (uint16_t) (*(uint8_t *) ((uint32_t) p_table + (uint32_t) 3)); + len = (uint16_t) (len << 8); + len = (uint16_t) (len + (uint16_t) (*(uint8_t *) ((uint32_t) p_table + (uint32_t) 2))); + + /* Descriptor > wLength */ + if (g_usb_pstd_req_length < len) + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) g_usb_pstd_req_length, p_table, p_utr); + } + else + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) len, p_table, p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + /*---- String descriptor ----*/ + case USB_DT_STRING: + { + if (idx < g_usb_pstd_driver.num_string) + { + #if (BSP_CFG_RTOS == 1) + g_usbx_string[1] = USB_DT_STRING; + p_table = g_usb_pstd_driver.p_stringtbl[idx]; + if (0 == idx) + { + if (g_usb_pstd_req_length == 2) + { + /* Lang ID */ + len = g_usb_pstd_req_length; + g_usbx_string[0] = (uint8_t) len; + g_usbx_string[2] = *p_table; + g_usbx_string[3] = *(p_table + 1); + } + else + { + /* Lang ID */ + len = 4; + g_usbx_string[0] = (uint8_t) len; + g_usbx_string[2] = *p_table; + g_usbx_string[3] = *(p_table + 1); + } + } + else + { + /* Other than Land ID */ + len = (uint16_t) (*(p_table + 3)); + g_usbx_string[0] = (uint8_t) ((len * 2) + 2); + if (g_usbx_string[0] > g_usb_pstd_req_length) + { + len = (uint16_t) ((g_usb_pstd_req_length - 2) / 2); + } + + for (i = 0; i < len; i++) + { + g_usbx_string[2 + (i * 2)] = *(p_table + i + 4); + g_usbx_string[3 + (i * 2)] = 0x00; + } + + len = (uint16_t) ((len * 2) + 2); + } + + usb_pstd_ctrl_read((uint32_t) len, g_usbx_string, p_utr); + #else /* #if (BSP_CFG_RTOS == 1) */ + p_table = g_usb_pstd_driver.p_stringtbl[idx]; + len = (uint16_t) (*(uint8_t *) ((uint32_t) p_table + (uint32_t) 0)); + if (g_usb_pstd_req_length < len) + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) g_usb_pstd_req_length, p_table, p_utr); + } + else + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) len, p_table, p_utr); + } + #endif /* #if (BSP_CFG_RTOS == 1) */ + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + /*---- Interface descriptor ----*/ + case USB_DT_INTERFACE: + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + break; + } + + /*---- Endpoint descriptor ----*/ + case USB_DT_ENDPOINT: + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + break; + } + + case USB_DT_DEVICE_QUALIFIER: + { + if ((USB_TRUE == usb_pstd_hi_speed_enable(p_utr)) && ((0 == g_usb_pstd_req_index) && (0 == idx))) + { + p_table = g_usb_pstd_driver.p_qualitbl; + if (g_usb_pstd_req_length < p_table[0]) + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) g_usb_pstd_req_length, p_table, p_utr); + } + else + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) p_table[0], p_table, p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + case USB_DT_OTHER_SPEED_CONF: + { + if ((USB_TRUE == usb_pstd_hi_speed_enable(p_utr)) && + ((0 == g_usb_pstd_req_index) && ((uint16_t) 0 == idx))) + { + connect_info = usb_cstd_port_speed(p_utr); + if (USB_HSCONNECT == connect_info) + { + p_table = g_usb_pstd_driver.p_configtbl; + } + else + { + p_table = g_usb_pstd_driver.p_othertbl; + } + + len = (uint16_t) (*(uint8_t *) ((uint32_t) p_table + (uint32_t) 3)); + len = (uint16_t) (len << 8); + len = (uint16_t) (len + (uint16_t) (*(uint8_t *) ((uint32_t) p_table + (uint32_t) 2))); + + /* Descriptor > wLength */ + if (g_usb_pstd_req_length < len) + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) g_usb_pstd_req_length, p_table, p_utr); + } + else + { + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) len, p_table, p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + case USB_DT_INTERFACE_POWER: + { + /* Not support */ + usb_pstd_set_stall_pipe0(p_utr); + break; + } + + default: + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + break; + } + } + } + else if (USB_INTERFACE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + g_usb_pstd_req_reg.request_type = g_usb_pstd_req_type; + g_usb_pstd_req_reg.request_value = g_usb_pstd_req_value; + g_usb_pstd_req_reg.request_index = g_usb_pstd_req_index; + g_usb_pstd_req_reg.request_length = g_usb_pstd_req_length; + if (USB_NULL != g_usb_pstd_driver.ctrltrans) + { + (*g_usb_pstd_driver.ctrltrans)(&g_usb_pstd_req_reg, (uint16_t) USB_NO_ARG, p_utr); + } + } + else + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_get_descriptor1 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_get_configuration1 + * Description : Analyze a Get Configuration command and process it. + * : (for control read data stage) + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_get_configuration1 (usb_utr_t * p_utr) +{ + static uint8_t tbl[2]; + + /* check request */ + if ((((USB_DEVICE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) && (0 == g_usb_pstd_req_value)) && + (0 == g_usb_pstd_req_index)) && (1 == g_usb_pstd_req_length)) + { + tbl[0] = (uint8_t) g_usb_pstd_config_num; + + /* Control read start */ + usb_pstd_ctrl_read((uint32_t) 1, tbl, p_utr); + } + else + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_get_configuration1 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_get_interface1 + * Description : Analyze a Get Interface command and process it. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_get_interface1 (usb_utr_t * p_utr) +{ + static uint8_t tbl[2]; + + /* check request */ + if (((USB_INTERFACE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) && (0 == g_usb_pstd_req_value)) && + (1 == g_usb_pstd_req_length)) + { + if (g_usb_pstd_req_index < USB_ALT_NO) + { + tbl[0] = (uint8_t) g_usb_pstd_alt_num[g_usb_pstd_req_index]; + + /* Start control read */ + usb_pstd_ctrl_read((uint32_t) 1, tbl, p_utr); + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_get_interface1 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_clr_feature0 + * Description : Clear Feature0 + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_clr_feature0 (void) +{ + #if USB_CFG_REQUEST == USB_CFG_ENABLE + if (0 == g_usb_pstd_req_length) + { + /* check request type */ + if (USB_DEVICE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + if ((USB_DEV_REMOTE_WAKEUP == g_usb_pstd_req_value) && (0 == g_usb_pstd_req_index)) + { + if (USB_TRUE == usb_pstd_chk_remote()) + { + usb_pstd_request_event_set(p_utr); + } + } + } + } + #endif /* USB_CFG_REQUEST == USB_CFG_ENABLE */ +} /* End of function usb_pstd_clr_feature0 */ + +/****************************************************************************** + * Function Name : usb_pstd_clr_feature3 + * Description : Analyze a Clear Feature command and process it. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_clr_feature3 (usb_utr_t * p_utr) +{ + uint16_t pipe; + uint16_t ep; + + if (0 == g_usb_pstd_req_length) + { + /* check request type */ + switch ((g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + case USB_DEVICE: + { + if ((USB_DEV_REMOTE_WAKEUP == g_usb_pstd_req_value) && (0 == g_usb_pstd_req_index)) + { + if (USB_TRUE == usb_pstd_chk_remote()) + { + g_usb_pstd_remote_wakeup = USB_FALSE; + + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + else + { + /* Not support remote wakeup */ + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); + } + + #if (BSP_CFG_RTOS == 1) + _ux_device_stack_clear_feature((ULONG) g_usb_pstd_req_type, + (ULONG) g_usb_pstd_req_value, + (ULONG) g_usb_pstd_req_index); + #endif /* BSP_CFG_RTOS == 1 */ + break; + } + + case USB_INTERFACE: + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + break; + } + + case USB_ENDPOINT: + { + /* Endpoint number */ + ep = (uint16_t) (g_usb_pstd_req_index & USB_EPNUMFIELD); + if (USB_ENDPOINT_HALT == g_usb_pstd_req_value) + { + /* EP0 */ + if (0 == ep) + { + /* Stall clear */ + usb_cstd_clr_stall(p_utr, (uint16_t) USB_PIPE0); + + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + /* EP1 to max */ + else if (ep <= USB_MAX_EP_NO) + { + pipe = usb_pstd_epadr2pipe(g_usb_pstd_req_index, p_utr); + if (USB_ERROR == pipe) + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + else + { + if (USB_PID_BUF == usb_cstd_get_pid(p_utr, pipe)) + { + usb_cstd_set_nak(p_utr, pipe); + + /* SQCLR=1 */ + hw_usb_set_sqclr(p_utr, pipe); + + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, pipe); + } + else + { + usb_cstd_clr_stall(p_utr, pipe); + + /* SQCLR=1 */ + hw_usb_set_sqclr(p_utr, pipe); + } + + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + if (USB_TRUE == g_usb_pstd_stall_pipe[pipe]) + { + g_usb_pstd_stall_pipe[pipe] = USB_FALSE; + (*g_usb_pstd_stall_cb)(p_utr, USB_NULL, USB_NULL); + } + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + + #if (BSP_CFG_RTOS == 1) + _ux_device_stack_clear_feature((ULONG) g_usb_pstd_req_type, + (ULONG) g_usb_pstd_req_value, + (ULONG) g_usb_pstd_req_index); + #endif /* BSP_CFG_RTOS == 1 */ + break; + } + + default: + { + usb_pstd_set_stall_pipe0(p_utr); + break; + } + } + } + else + { + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_clr_feature3 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_feature0 + * Description : Set Feature0 (for idle/setup stage) + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_feature0 (void) +{ + #if USB_CFG_REQUEST == USB_CFG_ENABLE + if (0 == g_usb_pstd_req_length) + { + /* check request type */ + if (USB_DEVICE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + if ((USB_DEV_REMOTE_WAKEUP == g_usb_pstd_req_value) && (0 == g_usb_pstd_req_index)) + { + if (USB_TRUE == usb_pstd_chk_remote()) + { + usb_pstd_request_event_set(p_utr); + } + } + } + } + #endif /* USB_CFG_REQUEST == USB_CFG_ENABLE */ +} /* End of function usb_pstd_set_feature0 */ + +/****************************************************************************** + * Function Name : usb_pstd_set_feature3 + * Description : Analyze a Set Feature command and process it. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_feature3 (usb_utr_t * p_utr) +{ + uint16_t pipe; + uint16_t ep; + + if (0 == g_usb_pstd_req_length) + { + /* check request type */ + switch ((g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + case USB_DEVICE: + { + switch (g_usb_pstd_req_value) + { + case USB_DEV_REMOTE_WAKEUP: + { + if (0 == g_usb_pstd_req_index) + { + if (USB_TRUE == usb_pstd_chk_remote()) + { + g_usb_pstd_remote_wakeup = USB_TRUE; + + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + else + { + /* Not support remote wakeup */ + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + case USB_TEST_MODE: + { + if (USB_HSCONNECT == usb_cstd_port_speed(p_utr)) + { + if ((g_usb_pstd_req_index < USB_TEST_RESERVED) || + (USB_TEST_VSTMODES <= g_usb_pstd_req_index)) + { + g_usb_pstd_test_mode_flag = USB_TRUE; + g_usb_pstd_test_mode_select = g_usb_pstd_req_index; + + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + else + { + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + #ifdef USB_CFG_OTG_USE + case B_HNP_ENABLE: + { + g_usb_otg_hnp_process[p_utr->ip] = USB_ON; + hw_usb_set_hnpbtoa(p_utr); + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + + break; + } + + case A_HNP_SUPPORT: + { + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + break; + } + #endif /* USB_CFG_OTG_USE */ + + default: + { + usb_pstd_set_feature_function(p_utr); + break; + } + } + + break; + } + + case USB_INTERFACE: + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); + break; + } + + case USB_ENDPOINT: + { + /* Endpoint number */ + ep = (uint16_t) (g_usb_pstd_req_index & USB_EPNUMFIELD); + if (USB_ENDPOINT_HALT == g_usb_pstd_req_value) + { + /* EP0 */ + if (0 == ep) + { + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + /* EP1 to max */ + else if (ep <= USB_MAX_EP_NO) + { + pipe = usb_pstd_epadr2pipe(g_usb_pstd_req_index, p_utr); + if (USB_ERROR == pipe) + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + else + { + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall(pipe, p_utr); + + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); + } + + break; + } + + default: + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + break; + } + } + + #if BSP_CFG_RTOS == 1 + _ux_device_stack_set_feature((ULONG) g_usb_pstd_req_type, + (ULONG) g_usb_pstd_req_value, + (ULONG) g_usb_pstd_req_index); + #endif + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_set_feature3 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_address0 + * Description : Set Address0 (for idle/setup stage). + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_address0 (void) +{ + /* Non processing. */ +} + +/****************************************************************************** + * End of function usb_pstd_set_address0 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_address3 + * Description : Analyze a Set Address command and process it. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_address3 (usb_utr_t * p_utr) +{ + if (USB_DEVICE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + if ((0 == g_usb_pstd_req_index) && (0 == g_usb_pstd_req_length)) + { + if (g_usb_pstd_req_value <= USB_DEVICE_ADDRESS_MAX) + { + /* Set pipe PID_BUF */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + else + { + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_set_address3 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_descriptor2 + * Description : Return STALL in response to a Set Descriptor command. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_descriptor2 (usb_utr_t * p_utr) +{ + /* Not specification */ + usb_pstd_set_stall_pipe0(p_utr); +} + +/****************************************************************************** + * End of function usb_pstd_set_descriptor2 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_configuration0 + * Description : Call callback function to notify the reception of SetConfiguration command + * : (for idle /setup stage) + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_configuration0 (usb_utr_t * p_utr) +{ + uint16_t config_num; + + config_num = g_usb_pstd_config_num; + + /* Configuration number set */ + usb_pstd_set_config_num(g_usb_pstd_req_value); + + if (g_usb_pstd_req_value != config_num) + { + if (USB_NULL != g_usb_pstd_driver.devconfig) + { + /* Registration open function call */ + (*g_usb_pstd_driver.devconfig)(p_utr, g_usb_pstd_config_num, USB_NULL); + + #if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_PHID_USE) + _ux_system_slave->ux_system_slave_remote_wakeup_enabled = UX_FALSE; + #endif /* #if defined(USB_CFG_PHID_USE) */ + g_usb_peri_usbx_is_configured[p_utr->ip] = USB_YES; + _ux_device_stack_configuration_set((uint32_t) g_usb_pstd_config_num); + #endif /* #if (BSP_CFG_RTOS == 1) */ + } + } +} + +/****************************************************************************** + * End of function usb_pstd_set_configuration0 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_configuration3 + * Description : Analyze a Set Configuration command and process it. This is + * : for the status stage of a control write where there is no data + * : stage. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_configuration3 (usb_utr_t * p_utr) +{ + uint16_t i; + + uint16_t ifc; + + uint16_t cfgok; + uint8_t * p_table2; + + if (USB_DEVICE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP)) + { + cfgok = USB_ERROR; + + p_table2 = g_usb_pstd_driver.p_configtbl; + + if ((((g_usb_pstd_req_value == p_table2[5]) || (0 == g_usb_pstd_req_value)) && (0 == g_usb_pstd_req_index)) && + (0 == g_usb_pstd_req_length)) + { + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + cfgok = USB_OK; + + if ((g_usb_pstd_req_value > 0) && (g_usb_pstd_req_value != g_usb_pstd_config_num)) + { + usb_pstd_clr_eptbl_index(); + ifc = usb_pstd_get_interface_num(); + + /* WAIT_LOOP */ + for (i = 0; i < ifc; ++i) + { + /* Pipe Information Table ("endpoint table") initialize */ + usb_pstd_set_eptbl_index(i, (uint16_t) 0); + } + + /* Clear pipe register */ + usb_pstd_clr_pipe_reg(p_utr); + + /* Set pipe register */ + usb_pstd_set_pipe_reg(p_utr); + } + } + + if (USB_ERROR == cfgok) + { + USB_PRINTF3("### usb_pstd_set_configuration3 NG value:%d index:%d length:%d \n", + g_usb_pstd_req_value, + g_usb_pstd_req_index, + g_usb_pstd_req_length); + + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_set_configuration3 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_interface0 + * Description : Call callback function to notify reception of SetInterface com- + * : mand. For idle/setup stage. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_interface0 (usb_utr_t * p_utr) +{ + if (USB_NULL != g_usb_pstd_driver.interface) + { + /* Interfaced change function call */ + (*g_usb_pstd_driver.interface)(p_utr, g_usb_pstd_alt_num[g_usb_pstd_req_index], USB_NULL); + } + + #if USB_CFG_REQUEST == USB_CFG_ENABLE + usb_pstd_request_event_set(p_utr); + #endif /* USB_CFG_REQUEST == USB_CFG_ENABLE */ +} + +/****************************************************************************** + * End of function usb_pstd_set_interface0 + ******************************************************************************/ + + #define NUM_OF_INTERFACE (8U) + #ifdef USB_CFG_PAUD_USE +extern uint8_t g_usb_paud_iso_pipe[NUM_OF_INTERFACE]; + #endif + #if (BSP_CFG_RTOS == 1) +extern TX_SEMAPHORE g_usb_peri_usbx_sem[USB_MAX_PIPE_NO + 1]; + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Function Name : usb_pstd_set_interface3 + * Description : Analyze a Set Interface command and request the process for + * : the command. This is for a status stage of a control write + * : where there is no data stage. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_set_interface3 (usb_utr_t * p_utr) +{ + #ifdef USB_CFG_PAUD_USE + uint16_t current_alt_value; + uint8_t pipe; + #endif // USB_CFG_PAUD_USE + + /* Configured ? */ + if ((USB_TRUE == usb_pstd_chk_configured(p_utr)) && + (USB_INTERFACE == (g_usb_pstd_req_type & USB_BMREQUESTTYPERECIP))) + { + #if defined(USB_CFG_PPRN_USE) + if (((1 == usb_pstd_get_interface_num()) && (0 == usb_pstd_get_alternate_num(0))) && + ((0 == g_usb_pstd_req_index) && (0 == g_usb_pstd_req_value))) + { + /* Do nothing about alternate setting */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + + #else /* defined(USB_CFG_PPRN_USE) */ + if ((g_usb_pstd_req_index <= usb_pstd_get_interface_num()) && (0 == g_usb_pstd_req_length)) + { + if (g_usb_pstd_req_value <= usb_pstd_get_alternate_num(g_usb_pstd_req_index)) + { + #ifdef USB_CFG_PAUD_USE + current_alt_value = g_usb_pstd_alt_num[g_usb_pstd_req_index]; + #endif // USB_CFG_PAUD_USE + g_usb_pstd_alt_num[g_usb_pstd_req_index] = (uint16_t) (g_usb_pstd_req_value & USB_ALT_SET); + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + usb_pstd_clr_eptbl_index(); + + /* Search endpoint setting */ + usb_pstd_set_eptbl_index(g_usb_pstd_req_index, g_usb_pstd_alt_num[g_usb_pstd_req_index]); + #if !defined(USB_CFG_PAUD_USE) && !defined(USB_CFG_DFU_USE) + usb_pstd_set_pipe_reg(p_utr); + #endif /* #if !defined(USB_CFG_PAUD_USE) && !defined(USB_CFG_DFU_USE) */ + + #ifdef USB_CFG_PAUD_USE + if (0 == (g_usb_pstd_req_value & USB_ALT_SET)) + { + if (current_alt_value == 1) + { + /* Alternate Setting 1 --> 0 */ + pipe = g_usb_paud_iso_pipe[g_usb_pstd_req_index]; // g_usb_pstd_req_index: Interface Number + usb_pstd_forced_termination(pipe, (uint16_t) USB_DATA_STOP, p_utr); + } + } + #endif + #if BSP_CFG_RTOS == 1 // USB_CFG_PAUD_USE + _ux_device_stack_alternate_setting_set((ULONG) g_usb_pstd_req_index, (ULONG) g_usb_pstd_req_value); + #endif + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + #endif /* defined(USB_CFG_PPRN_USE) */ + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } + } + else + { + /* Request error */ + usb_pstd_set_stall_pipe0(p_utr); + } +} + +/****************************************************************************** + * End of function usb_pstd_set_interface3 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_synch_rame1 + * Description : Return STALL response to SynchFrame command. + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_pstd_synch_rame1 (usb_utr_t * p_utr) +{ + /* Set pipe USB_PID_STALL */ + usb_pstd_set_stall_pipe0(p_utr); +} + +/****************************************************************************** + * End of function usb_pstd_synch_rame1 + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 1) + +/****************************************************************************** + * Function Name : usb_peri_class_request_usbx + * Description : Class request processing for data stage (USBX) + * Arguments : usb_setup_t *p_req : Pointer to usb_setup_t structure + * Return value : none + ******************************************************************************/ +static void usb_peri_class_request_usbx (usb_setup_t * p_req) +{ + UX_SLAVE_DEVICE * device; + UX_SLAVE_CLASS * class; + UX_SLAVE_CLASS_COMMAND class_command; + uint32_t class_index; + UX_SLAVE_TRANSFER * transfer_request; + uint32_t status; + + #if defined(USB_CFG_PHID_USE) + if ((USB_CLASS == (p_req->request_type & USB_BMREQUESTTYPETYPE)) || + (USB_VENDOR == (p_req->request_type & USB_BMREQUESTTYPETYPE)) || + (USB_STANDARD == (p_req->request_type & USB_BMREQUESTTYPETYPE))) + #else /* #if defined(USB_CFG_PHID_USE) */ + if ((USB_CLASS == (p_req->request_type & USB_BMREQUESTTYPETYPE)) || + (USB_VENDOR == (p_req->request_type & USB_BMREQUESTTYPETYPE))) + #endif /* #if defined(USB_CFG_PHID_USE) */ + { + class_command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_REQUEST; + for (class_index = 0; class_index < UX_MAX_SLAVE_INTERFACES; class_index++) + { + #if defined(USB_CFG_PAUD_USE) + + /* Check the received audio class request is for the interface + * (i.e. recipient is interface) or endpoint(i.e. recipient is endpoint). */ + if ((USB_INTERFACE == (p_req->request_type & USB_BMREQUESTTYPERECIP)) || + (USB_ENDPOINT == (p_req->request_type & USB_BMREQUESTTYPERECIP))) + #else /* defined(USB_CFG_PAUD_USE) */ + if (USB_INTERFACE == (p_req->request_type & USB_BMREQUESTTYPERECIP)) + #endif + { + #if defined(USB_CFG_PAUD_USE) + + /* Verify the interface value(i.e. request index value), + * only when received audio class request is for the interface + * (i.e. recipient is interface). */ + if (USB_INTERFACE == (p_req->request_type & USB_BMREQUESTTYPERECIP)) + { + #endif /* defined(USB_CFG_PAUD_USE) */ + if ((p_req->request_index & VALUE_FFH) != class_index) + { + continue; + } + + #if defined(USB_CFG_PAUD_USE) + } + #endif /* defined(USB_CFG_PAUD_USE) */ + class = _ux_system_slave->ux_system_slave_interface_class_array[class_index]; + if (UX_NULL == class) + { + continue; + } + + device = &_ux_system_slave->ux_system_slave_device; + transfer_request = + &device->ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request; + *(transfer_request->ux_slave_transfer_request_setup + + FSP_SETUP_REQUEST) = (uint8_t) (p_req->request_type >> 8); + *(uint16_t *) (transfer_request->ux_slave_transfer_request_setup + + FSP_SETUP_VALUE) = p_req->request_value; + *(uint16_t *) (transfer_request->ux_slave_transfer_request_setup + + FSP_SETUP_LENGTH) = p_req->request_length; + transfer_request->ux_slave_transfer_request_actual_length = p_req->request_length - + g_usb_pstd_data_cnt[USB_PIPE0]; + #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE) + *(transfer_request->ux_slave_transfer_request_setup + + FSP_SETUP_REQUEST_TYPE) = (uint8_t) (p_req->request_type & VALUE_FFH); + *(transfer_request->ux_slave_transfer_request_setup + + FSP_SETUP_INDEX_L) = (uint8_t) (p_req->request_index & VALUE_FFH); + *(transfer_request->ux_slave_transfer_request_setup + + FSP_SETUP_INDEX_H) = (uint8_t) (p_req->request_index >> 8); + #endif /* #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)*/ + class_command.ux_slave_class_command_class_ptr = class; + status = class->ux_slave_class_entry_function(&class_command); + if (status == UX_SUCCESS) + { + break; + } + } + } + } +} /* End of function usb_peri_class_request_usbx */ + +/****************************************************************************** + * Function Name : usb_peri_class_reqeust_usbx_get_data + * Description : Class request processing for data stage (USBX) + * Arguments : usb_setup_t *p_req : Pointer to usb_setup_t structure + * Return value : none + ******************************************************************************/ +static void usb_peri_class_reqeust_usbx_get_data (usb_setup_t * p_req, usb_utr_t * p_utr) +{ + FSP_PARAMETER_NOT_USED(p_req); + UX_SLAVE_DEVICE * device; + UX_SLAVE_TRANSFER * transfer_request; + usb_utr_t tran_data; + + tran_data.ip = p_utr->ip; + device = &_ux_system_slave->ux_system_slave_device; + transfer_request = &device->ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request; + + if (USB_YES == g_usb_pstd_pipe0_request) + { + while (1) + { + ; + } + } + + g_usb_pstd_std_request = USB_YES; + + usb_pstd_ctrl_write(p_req->request_length, transfer_request->ux_slave_transfer_request_data_pointer, &tran_data); +} /* End of function usb_peri_class_reqeust_usbx_get_data */ + + #endif /* #if (BSP_CFG_RTOS == 1) */ + +/****************************************************************************** + * Function Name : usb_peri_class_request + * Description : Class request processing for Device class + * Arguments : usb_setup_t *preq ; Class request information + * : uint16_t ctsq ; Control Stage + * Return value : none + ******************************************************************************/ +void usb_peri_class_request (usb_setup_t * preq, uint16_t ctsq, usb_utr_t * p_utr) +{ + /* Check Request type TYPE */ + if ((USB_CLASS == (preq->request_type & USB_BMREQUESTTYPETYPE)) || + (USB_VENDOR == (preq->request_type & USB_BMREQUESTTYPETYPE))) + { + /* Branch by the Control Transfer Stage */ + switch (ctsq) + { + case USB_CS_IDST: + { + g_usb_pstd_pipe0_request = USB_OFF; + g_usb_pstd_std_request = USB_NO; + usb_peri_class_request_ioss(preq); /* class request (idle or setup stage) */ + break; + } + + case USB_CS_RDDS: + { + usb_peri_class_request_rwds(preq, p_utr); /* class request (control read data stage) */ + break; + } + + case USB_CS_WRDS: + { + usb_peri_class_request_rwds(preq, p_utr); /* class request (control write data stage) */ + break; + } + + case USB_CS_WRND: + { + usb_peri_class_request_wnss(preq, p_utr); /* class request (control write nodata status stage) */ + break; + } + + case USB_CS_RDSS: + { + usb_peri_class_request_rss(preq, p_utr); /* class request (control read status stage) */ + break; + } + + case USB_CS_WRSS: + { + usb_peri_class_request_wss(preq, p_utr); /* class request (control write status stage) */ + break; + } + + case USB_CS_SQER: + { + usb_pstd_ctrl_end((uint16_t) USB_DATA_ERR, p_utr); /* End control transfer. */ + break; + } + + default: + { + usb_pstd_ctrl_end((uint16_t) USB_DATA_ERR, p_utr); /* End control transfer. */ + break; + } + } + } + else + { + usb_peri_other_request(preq, p_utr); + } +} /* End of function usb_peri_class_request */ + +/****************************************************************************** + * Function Name : usb_peri_class_request_ioss + * Description : Class Request (idle or setup stage) + * Arguments : usb_setup_t *req : Pointer to usb_setup_t structure + * Return value : none + ******************************************************************************/ +void usb_peri_class_request_ioss (usb_setup_t * req) +{ + (void) *req; + + /* Non */ +} /* End of function usb_peri_class_request_ioss */ + +/****************************************************************************** + * Function Name : usb_peri_class_request_rwds + * Description : Class request processing (control read/write data stage) + * Arguments : usb_setup_t *req : Pointer to usb_setup_t structure + * Return value : none + ******************************************************************************/ +void usb_peri_class_request_rwds (usb_setup_t * req, usb_utr_t * p_utr) +{ + #if (BSP_CFG_RTOS == 1) + if (0 != (req->request_type & USB_BMREQUESTTYPEDIR)) + { + /* In Data */ + usb_peri_class_request_usbx(req); + } + else + { + /* Out Data */ + usb_peri_class_reqeust_usbx_get_data(req, p_utr); + } + + #else /* (BSP_CFG_RTOS == 1) */ + #if defined(USB_CFG_PMSC_USE) + usb_instance_ctrl_t ctrl; + + /* Is a request receive target Interface? */ + if (USB_INTERFACE == (req->request_type & USB_BMREQUESTTYPERECIP)) + { + if (USB_GET_MAX_LUN == (req->request_type & USB_BREQUEST)) + { + usb_pmsc_get_max_lun(req->request_value, req->request_index, req->request_length, p_utr); + } + else + { + /* Get Line Coding Request etc */ + ctrl.module_number = p_utr->ip; + ctrl.setup = *req; /* Save setup data. */ + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + usb_set_event(USB_STATUS_REQUEST, &ctrl); + } + } + else + { + /* Set Stall */ + usb_pstd_set_stall_pipe0(p_utr); /* Req Error */ + } + + #else /* defined(USB_CFG_PMSC_USE) */ + usb_instance_ctrl_t ctrl; + + /* Is a request receive target Interface? */ + ctrl.module_number = p_utr->ip; + ctrl.setup = *req; /* Save setup data. */ + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + usb_set_event(USB_STATUS_REQUEST, &ctrl); + #endif /* defined(USB_CFG_PMSC_USE) */ + #endif /* (BSP_CFG_RTOS == 1) */ +} /* End of function usb_peri_class_request_rwds */ + +/****************************************************************************** + * Function Name : usb_peri_other_request + * Description : Processing to notify the reception of the USB request + * Arguments : usb_setup_t *req : Pointer to usb_setup_t structure + * Return value : none + ******************************************************************************/ +void usb_peri_other_request (usb_setup_t * req, usb_utr_t * p_utr) +{ + #if (BSP_CFG_RTOS == 1) + FSP_PARAMETER_NOT_USED(p_utr); + usb_peri_class_request_usbx(req); + #else /* #if (BSP_CFG_RTOS == 1) */ + usb_instance_ctrl_t ctrl; + + ctrl.type = USB_CLASS_REQUEST; + ctrl.setup = *req; /* Save setup data. */ + ctrl.module_number = p_utr->ip; + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + usb_set_event(USB_STATUS_REQUEST, &ctrl); + #endif /* #if (BSP_CFG_RTOS == 1) */ +} /* End of function usb_peri_other_request */ + +/****************************************************************************** + * Function Name : usb_peri_class_request_wnss + * Description : class request (control write nodata status stage) + * Arguments : usb_setup_t *req : Pointer to usb_setup_t structure + * Return value : none + ******************************************************************************/ +void usb_peri_class_request_wnss (usb_setup_t * req, usb_utr_t * p_utr) +{ + #if defined(USB_CFG_PCDC_USE) && defined(USB_CFG_PMSC_USE) + usb_instance_ctrl_t ctrl; + + /* Is a request receive target Interface? */ + if (USB_INTERFACE == (req->request_type & USB_BMREQUESTTYPERECIP)) + { + #if (BSP_CFG_RTOS == 1) + if ((USB_MASS_STORAGE_RESET == (req->request_type & USB_BREQUEST)) || + (USB_PCDC_SET_CONTROL_LINE_STATE == (req->request_type & USB_BREQUEST))) + #else + if (USB_MASS_STORAGE_RESET == (req->request_type & USB_BREQUEST)) + #endif /* (BSP_CFG_RTOS == 1) */ + { + #if (BSP_CFG_RTOS == 1) + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + usb_pstd_ctrl_end(USB_CTRL_END, p_utr); + + usb_peri_class_request_usbx(req); + #else /* (BSP_CFG_RTOS == 1) */ + usb_pmsc_mass_strage_reset(req->request_value, req->request_index, req->request_length, p_utr); + #endif /* (BSP_CFG_RTOS == 1) */ + } + else + { + ctrl.setup = *req; /* Save setup data. */ + ctrl.module_number = p_utr->ip; + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + usb_set_event(USB_STATUS_REQUEST, &ctrl); + } + } + else + { + usb_pstd_set_stall_pipe0(p_utr); /* Req Error */ + } + + #if (BSP_CFG_RTOS == 1) + if ((USB_MASS_STORAGE_RESET != (req->request_type & USB_BREQUEST)) && + (USB_PCDC_SET_CONTROL_LINE_STATE != (req->request_type & USB_BREQUEST))) + #else + if (USB_MASS_STORAGE_RESET != (req->request_type & USB_BREQUEST)) + #endif /* (BSP_CFG_RTOS == 1) */ + { + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* End control transfer. */ + } + + #elif defined(USB_CFG_PMSC_USE) + usb_instance_ctrl_t ctrl; + + /* Is a request receive target Interface? */ + if (USB_INTERFACE == (req->request_type & USB_BMREQUESTTYPERECIP)) + { + if (USB_MASS_STORAGE_RESET == (req->request_type & USB_BREQUEST)) + { + #if (BSP_CFG_RTOS == 1) + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + usb_pstd_ctrl_end(USB_CTRL_END, p_utr); + + usb_peri_class_request_usbx(req); + #else /* (BSP_CFG_RTOS == 1) */ + usb_pmsc_mass_strage_reset(req->request_value, req->request_index, req->request_length, p_utr); + #endif /* (BSP_CFG_RTOS == 1) */ + } + else + { + ctrl.setup = *req; /* Save setup data. */ + ctrl.module_number = p_utr->ip; + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + usb_set_event(USB_STATUS_REQUEST, &ctrl); + } + } + else + { + usb_pstd_set_stall_pipe0(p_utr); /* Req Error */ + } + + if (USB_MASS_STORAGE_RESET != (req->request_type & USB_BREQUEST)) + { + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* End control transfer. */ + } + + #else /* defined(USB_CFG_PCDC_USE) && defined(USB_CFG_PMSC_USE) */ + #if (BSP_CFG_RTOS != 1) + + /* Is a request receive target Interface? */ + usb_instance_ctrl_t ctrl; + ctrl.setup = *req; /* Save setup data. */ + ctrl.module_number = p_utr->ip; + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + usb_set_event(USB_STATUS_REQUEST, &ctrl); + #else /* #if (BSP_CFG_RTOS != 1) */ + FSP_PARAMETER_NOT_USED(req); + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* Set pipe PID_BUF */ + #endif /* #if (BSP_CFG_RTOS != 1) */ + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* End control transfer. */ + + #if (BSP_CFG_RTOS == 1) + usb_peri_class_request_usbx(req); + #endif /* #if (BSP_CFG_RTOS != 1) */ + #endif /* defined(USB_CFG_PCDC_USE) && defined(USB_CFG_PMSC_USE) */ +} /* End of function usb_peri_class_request_wnss */ + +/****************************************************************************** + * Function Name : usb_peri_class_request_rss + * Description : class request (control read status stage) + * Arguments : usb_setup_t *req : Pointer to usb_setup_t structure + * Return value : none + ******************************************************************************/ +void usb_peri_class_request_rss (usb_setup_t * req, usb_utr_t * p_utr) +{ + #if defined(USB_CFG_PMSC_USE) + + /* Is a request receive target Interface? */ + usb_instance_ctrl_t ctrl; + + if (USB_GET_MAX_LUN == (req->request_type & USB_BREQUEST)) + { + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); + } + else + { + ctrl.setup = *req; /* Save setup data. */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* Set pipe PID_BUF */ + ctrl.module_number = p_utr->ip; + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + #if (BSP_CFG_RTOS == 1) + ctrl.p_data = (void *) tx_thread_identify(); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + ctrl.p_data = (void *) xTaskGetCurrentTaskHandle(); + #endif /* (BSP_CFG_RTOS == 1) */ + usb_set_event(USB_STATUS_REQUEST_COMPLETE, &ctrl); + g_usb_pstd_std_request = USB_NO; + } + + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* End control transfer. */ + #else /* defined(USB_CFG_PMSC_USE) */ + /* Is a request receive target Interface? */ + #if (BSP_CFG_RTOS != 1) + usb_instance_ctrl_t ctrl; + + ctrl.setup = *req; /* Save setup data. */ + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* Set pipe PID_BUF */ + ctrl.module_number = p_utr->ip; + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + #if (BSP_CFG_RTOS == 1) + ctrl.p_data = (void *) tx_thread_identify(); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + ctrl.p_data = (void *) xTaskGetCurrentTaskHandle(); + #endif /* (BSP_CFG_RTOS == 1) */ + usb_set_event(USB_STATUS_REQUEST_COMPLETE, &ctrl); + #else /* #if (BSP_CFG_RTOS != 1) */ + FSP_PARAMETER_NOT_USED(req); + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* Set pipe PID_BUF */ + #endif /* #if (BSP_CFG_RTOS != 1) */ + g_usb_pstd_std_request = USB_NO; + + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); /* End control transfer. */ + #endif /* defined(USB_CFG_PMSC_USE) */ +} /* End of function usb_peri_class_request_rss */ + +/****************************************************************************** + * Function Name : usb_peri_class_request_wss + * Description : class request (control write status stage) + * Arguments : usb_setup_t *req : Pointer to usb_setup_t structure + * Return value : none + ******************************************************************************/ +void usb_peri_class_request_wss (usb_setup_t * req, usb_utr_t * p_utr) +{ + #if (BSP_CFG_RTOS != 1) + usb_instance_ctrl_t ctrl; + + ctrl.setup = *req; + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* Set BUF */ + ctrl.module_number = p_utr->ip; + ctrl.data_size = ctrl.setup.request_length - g_usb_pstd_data_cnt[USB_PIPE0]; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + #if (BSP_CFG_RTOS == 1) + ctrl.p_data = (void *) tx_thread_identify(); + #elif (BSP_CFG_RTOS == 2) /* (BSP_CFG_RTOS == 1) */ + ctrl.p_data = (void *) xTaskGetCurrentTaskHandle(); + #endif /* (BSP_CFG_RTOS == 1) */ + usb_set_event(USB_STATUS_REQUEST_COMPLETE, &ctrl); + #else /*#if (BSP_CFG_RTOS != 1) */ + FSP_PARAMETER_NOT_USED(req); + usb_cstd_set_buf(p_utr, (uint16_t) USB_PIPE0); /* Set BUF */ + #endif /*#if (BSP_CFG_RTOS != 1) */ + g_usb_pstd_std_request = USB_NO; + + usb_pstd_ctrl_end((uint16_t) USB_CTRL_END, p_utr); + #if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE) + usb_peri_usbx_set_control_length(req); + #endif /* #if defined(USB_CFG_PAUD_USE) || defined(USB_CFG_DFU_USE)*/ + usb_peri_class_request_usbx(req); + #endif /* #if (BSP_CFG_RTOS == 1) */ +} /* End of function usb_peri_class_request_wss */ + + #if USB_CFG_REQUEST == USB_CFG_ENABLE + +/****************************************************************************** + * Function Name : usb_pstd_request_event_set + * Description : + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_request_event_set (usb_utr_t * p_utr) +{ + usb_instance_ctrl_t ctrl; + + ctrl.setup.request_type = g_usb_pstd_req_type; /* Request type */ + ctrl.setup.request_value = g_usb_pstd_req_value; /* Value */ + ctrl.setup.request_index = g_usb_pstd_req_index; /* Index */ + ctrl.setup.request_length = g_usb_pstd_req_length; /* Length */ + ctrl.data_size = 0; + ctrl.status = USB_SETUP_STATUS_ACK; + ctrl.type = USB_CLASS_REQUEST; + ctrl.module_number = p_utr->ip; + usb_set_event(USB_STATUS_REQUEST, &ctrl); +} /* End of function usb_pstd_request_event_set */ + + #endif /* USB_CFG_REQUEST == USB_CFG_ENABLE */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h new file mode 100644 index 0000000000..4d08f43aa7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h @@ -0,0 +1,485 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef R_USB_BITDEFINE_H + #define R_USB_BITDEFINE_H + + #ifdef __cplusplus +extern "C" { + #endif + +/***************************************************************************** + * Structure Types + ******************************************************************************/ + +/* USB0 & USBHS Register definition */ + +/* System Configuration Control Register */ + #define USB_SCKE (0x0400U) /* b10: USB clock enable */ + #define USB_CNEN (0x0100U) /* b8: Single end receiver */ + #define USB_HSE (0x0080U) /* b7: Hi-speed enable */ + #define USB_DCFM (0x0040U) /* b6: Function select */ + #define USB_DRPD (0x0020U) /* b5: D+/D- pull down control */ + #define USB_DPRPU (0x0010U) /* b4: D+ pull up control */ + #define USB_DMRPU (0x0008U) /* b3: D- pull up control *//* For low speed */ + #define USB_USBE (0x0001U) /* b0: USB module enable */ + +/* CPU Bus Wait Register */ + #define USB_BWAIT (0x0F0FU) /* b3-0: Bus wait bit */ + #define USB_BWAIT_15 (0x0F0FU) /* 15 wait (access cycle 17) */ + #define USB_BWAIT_14 (0x0F0EU) /* 14 wait (access cycle 16) */ + #define USB_BWAIT_13 (0x0F0DU) /* 13 wait (access cycle 15) */ + #define USB_BWAIT_12 (0x0F0CU) /* 12 wait (access cycle 14) */ + #define USB_BWAIT_11 (0x0F0BU) /* 11 wait (access cycle 13) */ + #define USB_BWAIT_10 (0x0F0AU) /* 10 wait (access cycle 12) */ + #define USB_BWAIT_9 (0x0F09U) /* 9 wait (access cycle 11) */ + #define USB_BWAIT_8 (0x0F08U) /* 8 wait (access cycle 10) */ + #define USB_BWAIT_7 (0x0F07U) /* 7 wait (access cycle 9) */ + #define USB_BWAIT_6 (0x0F06U) /* 6 wait (access cycle 8) */ + #define USB_BWAIT_5 (0x0F05U) /* 5 wait (access cycle 7) */ + #define USB_BWAIT_4 (0x0F04U) /* 4 wait (access cycle 6) */ + #define USB_BWAIT_3 (0x0F03U) /* 3 wait (access cycle 5) */ + #define USB_BWAIT_2 (0x0F02U) /* 2 wait (access cycle 4) */ + #define USB_BWAIT_1 (0x0F01U) /* 1 wait (access cycle 3) */ + #define USB_BWAIT_0 (0x0F00U) /* 0 wait (access cycle 2) */ + #define USB_BWAIT_B11_B8_WRITE (0x0F00U) /* b11-b8: Reserved bit write */ + +/* System Configuration Status Register */ + #define USB_OVCMON (0xC000U) /* b15-14: Over-current monitor */ + #define USB_OVCBIT (0x8000U) /* b15-14: Over-current bit */ + #define USB_HTACT (0x0040U) /* b6: USB Host Sequencer Status Monitor */ + #define USB_SOFEA (0x0020U) /* b5: SOF monitor */ + #define USB_IDMON (0x0004U) /* b2: ID-pin monitor */ + #define USB_LNST (0x0003U) /* b1-0: D+, D- line status */ + #define USB_SE1 (0x0003U) /* SE1 */ + #define USB_FS_KSTS (0x0002U) /* Full-Speed K State */ + #define USB_FS_JSTS (0x0001U) /* Full-Speed J State */ + #define USB_LS_JSTS (0x0002U) /* Low-Speed J State */ + #define USB_LS_KSTS (0x0001U) /* Low-Speed K State */ + #define USB_SE0 (0x0000U) /* SE0 */ + +/* PLL Status Register */ + #define USB_PLLLOCK (0x0001U) + +/* Device State Control Register */ + #define USB_HNPBTOA (0x0800U) /* b11: Host negotiation protocol (BtoA) */ + #define USB_EXICEN (0x0400U) /* b10: EXICEN output terminal control */ + #define USB_VBUSEN (0x0200U) /* b9: VBUS output terminal control */ + #define USB_WKUP (0x0100U) /* b8: Remote wakeup */ + #define USB_RWUPE (0x0080U) /* b7: Remote wakeup sense */ + #define USB_USBRST (0x0040U) /* b6: USB reset enable */ + #define USB_RESUME (0x0020U) /* b5: Resume enable */ + #define USB_UACT (0x0010U) /* b4: USB bus enable */ + #define USB_RHST (0x0007U) /* b2-0: Reset handshake status */ + #define USB_HSPROC (0x0004U) /* HS handshake processing */ + #define USB_HSMODE (0x0003U) /* Hi-Speed mode */ + #define USB_FSMODE (0x0002U) /* Full-Speed mode */ + #define USB_LSMODE (0x0001U) /* Low-Speed mode */ + #define USB_UNDECID (0x0000U) /* Undecided */ + +/* Test Mode Register */ + #define USB_UTST (0x000FU) /* b3-0: Test mode */ + #define USB_H_TST_F_EN (0x000DU) /* HOST TEST FORCE ENABLE */ + #define USB_H_TST_PACKET (0x000CU) /* HOST TEST Packet */ + #define USB_H_TST_SE0_NAK (0x000BU) /* HOST TEST SE0 NAK */ + #define USB_H_TST_K (0x000AU) /* HOST TEST K */ + #define USB_H_TST_J (0x0009U) /* HOST TEST J */ + #define USB_H_TST_NORMAL (0x0000U) /* HOST Normal Mode */ + #define USB_P_TST_PACKET (0x0004U) /* PERI TEST Packet */ + #define USB_P_TST_SE0_NAK (0x0003U) /* PERI TEST SE0 NAK */ + #define USB_P_TST_K (0x0002U) /* PERI TEST K */ + #define USB_P_TST_J (0x0001U) /* PERI TEST J */ + #define USB_P_TST_NORMAL (0x0000U) /* PERI Normal Mode */ + +/* CFIFO/DxFIFO Port Select Register */ + #define USB_RCNT (0x8000U) /* b15: Read count mode */ + #define USB_REW (0x4000U) /* b14: Buffer rewind */ + #define USB_DCLRM (0x2000U) /* b13: Automatic buffer clear mode */ + #define USB_DREQE (0x1000U) /* b12: DREQ output enable */ + #define USB_MBW (0x0C00U) /* b10: Maximum bit width for FIFO access */ + #define USB_MBW_32 (0x0800U) /* FIFO access : 32bit */ + #define USB_MBW_16 (0x0400U) /* FIFO access : 16bit */ + #define USB_MBW_8 (0x0000U) /* FIFO access : 8bit */ + #define USB_BIGEND (0x0100U) /* b8: Big endian mode */ + #define USB_FIFO_BIG (0x0100U) /* Big endian */ + #define USB_FIFO_LITTLE (0x0000U) /* Little endian */ + #define USB_ISEL (0x0020U) /* b5: DCP FIFO port direction select */ + #define USB_CURPIPE (0x000FU) /* b2-0: PIPE select */ + +/* CFIFO/DxFIFO Port Control Register */ + #define USB_BVAL (0x8000U) /* b15: Buffer valid flag */ + #define USB_BCLR (0x4000U) /* b14: Buffer clear */ + #define USB_FRDY (0x2000U) /* b13: FIFO ready */ + #define USB_DTLN (0x0FFFU) /* b11-0: FIFO data length */ + +/* Interrupt Enable Register 0 */ + #define USB_VBSE (0x8000U) /* b15: VBUS interrupt */ + #define USB_RSME (0x4000U) /* b14: Resume interrupt */ + #define USB_SOFE (0x2000U) /* b13: Frame update interrupt */ + #define USB_DVSE (0x1000U) /* b12: Device state transition interrupt */ + #define USB_CTRE (0x0800U) /* b11: Control transfer stage transition interrupt */ + #define USB_BEMPE (0x0400U) /* b10: Buffer empty interrupt */ + #define USB_NRDYE (0x0200U) /* b9: Buffer notready interrupt */ + #define USB_BRDYE (0x0100U) /* b8: Buffer ready interrupt */ + +/* Interrupt Enable Register 1 */ + #define USB_OVRCRE (0x8000U) /* b15: Over-current interrupt */ + #define USB_BCHGE (0x4000U) /* b14: USB bus change interrupt */ + #define USB_DTCHE (0x1000U) /* b12: Detach sense interrupt */ + #define USB_ATTCHE (0x0800U) /* b11: Attach sense interrupt */ + #define USB_L1RSMENDE (0x0200U) /* b9: L1 resume completion interrupt */ + #define USB_LPMENDE (0x0100U) /* b8: LPM transaction completion interrupt */ + #define USB_EOFERRE (0x0040U) /* b6: EOF error interrupt */ + #define USB_SIGNE (0x0020U) /* b5: SETUP IGNORE interrupt */ + #define USB_SACKE (0x0010U) /* b4: SETUP ACK interrupt */ + #define USB_PDDETINTE (0x0001U) /* b0: PDDET detection interrupt */ + +/* BRDY Interrupt Enable/Status Register */ + #define USB_BRDY9 (0x0200U) /* b9: PIPE9 */ + #define USB_BRDY8 (0x0100U) /* b8: PIPE8 */ + #define USB_BRDY7 (0x0080U) /* b7: PIPE7 */ + #define USB_BRDY6 (0x0040U) /* b6: PIPE6 */ + #define USB_BRDY5 (0x0020U) /* b5: PIPE5 */ + #define USB_BRDY4 (0x0010U) /* b4: PIPE4 */ + #define USB_BRDY3 (0x0008U) /* b3: PIPE3 */ + #define USB_BRDY2 (0x0004U) /* b2: PIPE2 */ + #define USB_BRDY1 (0x0002U) /* b1: PIPE1 */ + #define USB_BRDY0 (0x0001U) /* b1: PIPE0 */ + +/* NRDY Interrupt Enable/Status Register */ + #define USB_NRDY9 (0x0200U) /* b9: PIPE9 */ + #define USB_NRDY8 (0x0100U) /* b8: PIPE8 */ + #define USB_NRDY7 (0x0080U) /* b7: PIPE7 */ + #define USB_NRDY6 (0x0040U) /* b6: PIPE6 */ + #define USB_NRDY5 (0x0020U) /* b5: PIPE5 */ + #define USB_NRDY4 (0x0010U) /* b4: PIPE4 */ + #define USB_NRDY3 (0x0008U) /* b3: PIPE3 */ + #define USB_NRDY2 (0x0004U) /* b2: PIPE2 */ + #define USB_NRDY1 (0x0002U) /* b1: PIPE1 */ + #define USB_NRDY0 (0x0001U) /* b1: PIPE0 */ + +/* BEMP Interrupt Enable/Status Register */ + #define USB_BEMP9 (0x0200U) /* b9: PIPE9 */ + #define USB_BEMP8 (0x0100U) /* b8: PIPE8 */ + #define USB_BEMP7 (0x0080U) /* b7: PIPE7 */ + #define USB_BEMP6 (0x0040U) /* b6: PIPE6 */ + #define USB_BEMP5 (0x0020U) /* b5: PIPE5 */ + #define USB_BEMP4 (0x0010U) /* b4: PIPE4 */ + #define USB_BEMP3 (0x0008U) /* b3: PIPE3 */ + #define USB_BEMP2 (0x0004U) /* b2: PIPE2 */ + #define USB_BEMP1 (0x0002U) /* b1: PIPE1 */ + #define USB_BEMP0 (0x0001U) /* b0: PIPE0 */ + +/* SOF Pin Configuration Register */ + #define USB_TRNENSEL (0x0100U) /* b8: Select transaction enable period */ + #define USB_BRDYM (0x0040U) /* b6: BRDY clear timing */ + #define USB_INTL (0x0020U) /* b5: Interrupt sense select */ + #define USB_EDGESTS (0x0010U) /* b4: */ + #define USB_SOFMODE (0x000CU) /* b3-2: SOF pin select */ + #define USB_SOF_125US (0x0008U) /* SOF 125us Frame Signal */ + #define USB_SOF_1MS (0x0004U) /* SOF 1ms Frame Signal */ + #define USB_SOF_DISABLE (0x0000U) /* SOF Disable */ + + #define USB_HSEB (0x8000U) /* b15: CL only mode bit */ + + #define USB_REPSTART (0x0800U) /* b11: Terminator adjustment forcible starting bit */ + #define USB_REPSEL (0x0300U) /* b9-8: Terminator adjustment cycle setting */ + #define USB_REPSEL_128 (0x0300U) /* 128 sec */ + #define USB_REPSEL_64 (0x0200U) /* 64 sec */ + #define USB_REPSEL_16 (0x0100U) /* 16 sec */ + #define USB_REPSEL_NONE (0x0000U) /* - */ + #define USB_CLKSEL (0x0030U) /* b5-4: System clock setting */ + #define USB_CLKSEL_24 (0x0030U) /* 24MHz */ + #define USB_CLKSEL_20 (0x0020U) /* 20MHz */ + #define USB_CLKSEL_48 (0x0010U) /* 48MHz */ + #define USB_CLKSEL_12 (0x0000U) /* 12MHz */ + #define USB_CDPEN (0x0008U) /* b3: Charging downstream port enable */ + #define USB_PLLRESET (0x0002U) /* b1: PLL reset control */ + #define USB_DIRPD (0x0001U) /* b0: Power down control */ + +/* Interrupt Status Register 0 */ + #define USB_VBINT (0x8000U) /* b15: VBUS interrupt */ + #define USB_RESM (0x4000U) /* b14: Resume interrupt */ + #define USB_SOFR (0x2000U) /* b13: SOF update interrupt */ + #define USB_DVST (0x1000U) /* b12: Device state transition interrupt */ + #define USB_CTRT (0x0800U) /* b11: Control transfer stage transition interrupt */ + #define USB_BEMP (0x0400U) /* b10: Buffer empty interrupt */ + #define USB_NRDY (0x0200U) /* b9: Buffer notready interrupt */ + #define USB_BRDY (0x0100U) /* b8: Buffer ready interrupt */ + #define USB_VBSTS (0x0080U) /* b7: VBUS input port */ + #define USB_DVSQ (0x0070U) /* b6-4: Device state */ + #define USB_DS_SPD_CNFG (0x0070U) /* Suspend Configured */ + #define USB_DS_SPD_ADDR (0x0060U) /* Suspend Address */ + #define USB_DS_SPD_DFLT (0x0050U) /* Suspend Default */ + #define USB_DS_SPD_POWR (0x0040U) /* Suspend Powered */ + #define USB_DS_SUSP (0x0040U) /* Suspend */ + #define USB_DS_CNFG (0x0030U) /* Configured */ + #define USB_DS_ADDS (0x0020U) /* Address */ + #define USB_DS_DFLT (0x0010U) /* Default */ + #define USB_DS_POWR (0x0000U) /* Powered */ + #define USB_DVSQS (0x0030U) /* b5-4: Device state */ + #define USB_VALID (0x0008U) /* b3: Setup packet detect flag */ + #define USB_CTSQ (0x0007U) /* b2-0: Control transfer stage */ + #define USB_CS_SQER (0x0006U) /* Sequence error */ + #define USB_CS_WRND (0x0005U) /* Ctrl write nodata status stage */ + #define USB_CS_WRSS (0x0004U) /* Ctrl write status stage */ + #define USB_CS_WRDS (0x0003U) /* Ctrl write data stage */ + #define USB_CS_RDSS (0x0002U) /* Ctrl read status stage */ + #define USB_CS_RDDS (0x0001U) /* Ctrl read data stage */ + #define USB_CS_IDST (0x0000U) /* Idle or setup stage */ + +/* Interrupt Status Register 1 */ + #define USB_OVRCR (0x8000U) /* b15: Over-current interrupt */ + #define USB_BCHG (0x4000U) /* b14: USB bus change interrupt */ + #define USB_DTCH (0x1000U) /* b12: Detach sense interrupt */ + #define USB_ATTCH (0x0800U) /* b11: Attach sense interrupt */ + #define USB_L1RSMEND (0x0200U) /* b9: L1 resume completion interrupt */ + #define USB_LPMEND (0x0100U) /* b8: LPM transaction completion interrupt */ + #define USB_EOFERR (0x0040U) /* b6: EOF-error interrupt */ + #define USB_SIGN (0x0020U) /* b5: Setup ignore interrupt */ + #define USB_SACK (0x0010U) /* b4: Setup ack interrupt */ + #define USB_PDDETINT (0x0001U) /* b0: PDDET detection interrupt */ + +/* Frame Number Register */ + #define USB_OVRN (0x8000U) /* b15: Overrun error */ + #define USB_CRCE (0x4000U) /* b14: Received data error */ + #define USB_FRNM (0x07FFU) /* b10-0: Frame number */ + +/* Device State Change Register */ /* For USB0 */ + #define USB_DVCHG (0x8000U) /* b15: Device state change */ + +/* Micro Frame Number Register */ /* For USBHS */ + #define USB_UFRNM (0x0007U) /* b2-0: Micro frame number */ + +/* USB Address / Low Power Status Recovery Register */ + #define USB_STSRECOV (0x0F00U) /* b11-8: Status Recovery */ + #define USB_USBADDR_MASK (0x007FU) /* b6-0: USB address */ + +/* USB Request Type Register */ + #define USB_BMREQUESTTYPE (0x00FFU) /* b7-0: USB_BMREQUESTTYPE */ + #define USB_BMREQUESTTYPEDIR (0x0080U) /* b7 : Data transfer direction */ + #define USB_BMREQUESTTYPETYPE (0x0060U) /* b6-5: Type */ + #define USB_BMREQUESTTYPERECIP (0x001FU) /* b4-0: Recipient */ + +/* USB Request Value Register */ + #define USB_WVALUE (0xFFFFU) /* b15-0: wValue */ + #define USB_DT_TYPE (0xFF00U) + #define USB_GET_DT_TYPE(v) (((v) & USB_DT_TYPE) >> 8) + #define USB_DT_INDEX (0x00FFU) + #define USB_CONF_NUM (0x00FFU) + #define USB_ALT_SET (0x00FFU) + +/* USB Request Index Register */ + #define USB_WINDEX (0xFFFFU) /* b15-0: wIndex */ + #define USB_TEST_SELECT (0xFF00U) /* b15-b8: Test Mode Selectors */ + #define USB_TEST_J (0x0100U) /* Test_J */ + #define USB_TEST_K (0x0200U) /* Test_K */ + #define USB_TEST_SE0_NAK (0x0300U) /* Test_SE0_NAK */ + #define USB_TEST_PACKET (0x0400U) /* Test_Packet */ + #define USB_TEST_FORCE_ENABLE (0x0500U) /* Test_Force_Enable */ + #define USB_TEST_STSelectors (0x0600U) /* Standard test selectors */ + #define USB_TEST_RESERVED (0x4000U) /* Reserved */ + #define USB_TEST_VSTMODES (0xC000U) /* VendorSpecific test modes */ + +/* USB Request Length Register */ + #define USB_WLENGTH (0xFFFFU) /* b15-0: wLength */ + +/* Refer to r_usb_cdefusbip.h */ + #define USB_TYPE (0xC000U) /* b15-14: Transfer type */ + #define USB_BFRE (0x0400U) /* b10: Buffer ready interrupt mode select */ + + #define USB_DEVSEL (0xF000U) /* b15-14: Device address select */ + #define USB_MAXP (0x007FU) /* b6-0: Maxpacket size of default control pipe */ + #define USB_MXPS (0x07FFU) /* b10-0: Maxpacket size */ + + #define USB_BSTS (0x8000U) /* b15: Buffer status */ + #define USB_SUREQ (0x4000U) /* b14: Send USB request */ + #define USB_INBUFM (0x4000U) /* b14: IN buffer monitor (Only for PIPE1 to 5) */ + #define USB_CSCLR (0x2000U) /* b13: c-split status clear */ + #define USB_CSSTS (0x1000U) /* b12: c-split status */ + #define USB_SUREQCLR (0x0800U) /* b11: stop setup request */ + #define USB_ATREPM (0x0400U) /* b10: Auto repeat mode */ + #define USB_ACLRM (0x0200U) /* b9: buffer auto clear mode */ + #define USB_SQCLR (0x0100U) /* b8: Sequence bit clear */ + #define USB_SQSET (0x0080U) /* b7: Sequence bit set */ + #define USB_SQMON (0x0040U) /* b6: Sequence bit monitor */ + #define USB_PBUSY (0x0020U) /* b5: pipe busy */ + #define USB_PINGE (0x0010U) /* b4: ping enable */ + #define USB_CCPL (0x0004U) /* b2: Enable control transfer complete */ + #define USB_PID (0x0003U) /* b1-0: Response PID */ + #define USB_PID_STALL (0x0002U) /* STALL */ + #define USB_PID_BUF (0x0001U) /* BUF */ + #define USB_PID_NAK (0x0000U) /* NAK */ + + #define USB_PIPENM (0x0007U) /* b2-0: Pipe select */ + +/* Refer to r_usb_cdefusbip.h */ + #define USB_BUFSIZE (0x7C00U) /* b14-10: Pipe buffer size */ + #define USB_BUFNMB (0x007FU) /* b6-0: Pipe buffer number */ + #define USB_PIPE0BUF (256U) + #define USB_PIPEXBUF (64U) + + #define USB_TRENB (0x0200U) /* b9: Transaction count enable */ + #define USB_TRCLR (0x0100U) /* b8: Transaction count clear */ + #define USB_TRNCNT (0xFFFFU) /* b15-0: Transaction counter */ + + #define USB_UCKSELC (0x0001U) /* b0: USB Clock Seielction Bit */ + + #define USB_VDCEN (0x0080U) /* b7: Regulator ON/OFF control */ + + #define USB_UPPHUB (0x7800U) /* b14-11: HUB register */ + #define USB_HUBPORT (0x0700U) /* b10-8: HUB port */ + #define USB_USBSPD (0x00C0U) /* b7-6: Device speed */ + + #define USB_BYTE_MASK (0x00FFU) /* b0-b7: Byte data Mask */ + + #define USB_CPU_DELAY_US (100U) /* USB CPU delay time microsecond */ + + #define USB_DEVICE_ADDRESS_MAX (127) /* Device Address Max */ + +/********* USB0 Only ******************************************************************************/ + +/* PHY Crosspoint Adjustment Register */ +/* PHYSLEW */ + #define USB_SLEWF01 (0x0008U) /* b3: Cross point adjustment bit 01 */ + #define USB_SLEWF00 (0x0004U) /* b2: Cross point adjustment bit 00 */ + #define USB_SLEWR01 (0x0002U) /* b1: Cross point adjustment bit 01 */ + #define USB_SLEWR00 (0x0001U) /* b0: Cross point adjustment bit 00 */ + +/* Deep Standby USB Transceiver Control/Terminal Monitor Register */ +/* DPUSR0R */ + #define USB_DVBSTS0 (0x00800000U) /* b23: USB0 VBUS input */ + #define USB_DOVCB0 (0x00200000U) /* b21: USB0 OVRCURB input */ + #define USB_DOVCA0 (0x00100000U) /* b20: USB0 OVRCURA input */ + #define USB_DM0 (0x00200000U) /* b17: USB0 D- input */ + #define USB_DP0 (0x00100000U) /* b16: USB0 D+ input */ + #define USB_FIXPHY0 (0x00000010U) /* b4: USB0 transceiver output fixed bit */ + #define USB_DRPD0 (0x00000008U) /* b3: D+/D- pull down resistor control bit */ + #define USB_RPUE0 (0x00000002U) /* b1: DP pull up resistor control bit */ + #define USB_SRPC0 (0x00000001U) /* b0: USB0 single end receiver control bit */ + +/* Deep Standby USB Suspend/Resume Interrupt Register */ +/* DPUSR1R */ + #define USB_DVBINT0 (0x00800000U) /* b23: USB0 VBUS monitor bit */ + #define USB_DOVRCRB0 (0x00200000U) /* b21: USB0 OVRCURB DM monitor bit */ + #define USB_DOVRCRA0 (0x00100000U) /* b20: USB0 OVRCURA DM monitor bit */ + #define USB_DMINT0 (0x00020000U) /* b17: USB0 DM monitor bit */ + #define USB_DPINT0 (0x00010000U) /* b16: USB0 DP monitor bit */ + #define USB_DVBSE0 (0x00000080U) /* b7: USB0 VBUS interrupt enable */ + #define USB_DOVRCRBE0 (0x00000020U) /* b5: USB0 OVRCURB interrupt enable */ + #define USB_DOVRCRAE0 (0x00000010U) /* b4: USB0 OVRCURA interrupt enable */ + #define USB_DMINTE0 (0x00000002U) /* b1: USB0 DM interrupt enable */ + #define USB_DPINTE0 (0x00000001U) /* b0: USB0 DP interrupt enable */ + +/**************************************************************************************************/ + +/********* USBHS Only *****************************************************************************/ + +/* Low Power Control Register */ +/* LPCTRL */ + #define USB_HWUPM (0x0080U) /* b7: */ + +/* Low Power Status Register */ +/* LPSTS */ + #define USB_SUSPENDM (0x4000U) /* b14: UTMI SuspendM control */ + +/* PHY Single Access Read Data Register */ +/* SPRDAT */ + #define USB_PHYRDAT (0x00FFU) /* PHY read data bit */ + +/* Battery Charging Control Register */ +/* BCCTRL */ + #define USB_PDDETSTS (0x0200U) /* b9: PDDET status */ + #define USB_CHGDETSTS (0x0100U) /* b8: CHGDET status */ + #define USB_DCPMODE (0x0020U) /* b5: DCP mode control */ + #define USB_VDMSRCE (0x0010U) /* b4: VDMSRC control */ + #define USB_IDPSINKE (0x0008U) /* b3: IDPSINK control */ + #define USB_VDPSRCE (0x0004U) /* b2: VDPSRC control */ + #define USB_IDMSINKE (0x0002U) /* b1: IDMSINK control */ + #define USB_IDPSRCE (0x0001U) /* b0: IDPSRC control */ + +/* Function L1 Control Register 1 */ +/* PL1CTRL1 */ + #define USB_L1EXTMD (0x4000U) /* b14: PHY control mode */ + #define USB_DVSQEX (0x0080U) /* b7: DVSQ extension bit */ + #define USB_DVSQ (0x0070U) /* b6-4: Mirror of DVSQ */ + #define USB_L1NEGOMD (0x0008U) /* b3: L1 response negotiation control */ + #define USB_L1RESPMD (0x0006U) /* b2-1: L1 response mode */ + #define USB_L1RESPEN (0x0001U) /* b0: L1 response enable */ + +/* Function L1 Control Register 2 */ +/* PL1CTRL2 */ + #define USB_HSRDMON (0x0F00U) /* b12: RWE monitor bit */ + #define USB_RWEMON (0x1000U) /* b11-8: HIRD monitor bit */ + +/* Host L1 Control Register 1 */ +/* HL1CTRL1 */ + #define USB_L1STATUS (0x0006U) /* b2-1: L1 request completion state */ + #define USB_L1REQ (0x0001U) /* b0: L1 changes request bit + */ + +/* Host L1 Control Register 2 */ +/* HL1CTRL2 */ + #define USB_BESL (0x8000U) /* b15: BESL & Alternate HIRD bit */ + #define USB_L1RWE (0x1000U) /* b12: L1 RemoteWake enable for LPM tokens */ + #define USB_HSRD (0x0F00U) /* b11-8: HIRD bit for LPM tokens */ + #define USB_L1ADDR (0x000FU) /* b3-0: DeviceAddress for LPM tokens */ + +/* PHY Timing Register 1 */ +/* PHYTRIM1 */ + #define USB_IMPOFFSET (0x7000U) /* b14-12: Terminator adjustment */ + #define USB_HSIUP (0x0F00U) /* b11-8: Output level setup of HS */ + #define USB_PCOMPENB (0x0080U) /* b7: PVDD starting detection setup */ + #define USB_DFALL (0x000CU) /* b3-2: FS/LS falling output waveform compensation function setting */ + #define USB_DRISE (0x0003U) /* b1-0: FS/LS standup output waveform compensation function setting */ + +/* PHY Timing Register 2 */ +/* PHYTRIM2 */ + #define USB_DIS (0x7000U) /* b14-12: Disconnect disregard level setup */ + #define USB_PDR (0x0300U) /* b9-8: HS output compensation function setting */ + #define USB_HSRXENMODE (0x0080U) /* b7: HS reception permission control mode setup */ + #define USB_SQU (0x000FU) /* b3-0: Squelch disregard level setup */ + +/* Deep Standby USB Register */ +/* DPUSR0R */ + #define USB_DVBSTSHM (0x00800000U) /* b23: VBUS input */ + #define USB_DOVCBHM (0x00200000U) /* b21: OVRCURB input */ + #define USB_DOVCAHM (0x00100000U) /* b20: OVRCURA input */ + +/* DPUSR1R */ + #define USB_DVBSTSH (0x00800000U) /* b23: Interruption factor return display of VBUS */ + #define USB_DOVCBH (0x00200000U) /* b21: Interruption factor return display of OVRCURB */ + #define USB_DOVCAH (0x00100000U) /* b20: Interruption factor return display of OVRCURA */ + #define USB_DVBSTSHE (0x00000080U) /* b7 : VBUS interrupt enable */ + #define USB_DOVCBHE (0x00000020U) /* b5 : OVRCURB interrupt enable */ + #define USB_DOVCAHE (0x00000010U) /* b4 : OVRCURA interrupt enable */ + +/**************************************************************************************************/ + +/* DMAx Pin Configuration Register */ + #define USB_DREQA (0x4000U) /* b14: Dreq active select */ + #define USB_BURST (0x2000U) /* b13: Burst mode */ + #define USB_DACKA (0x0400U) /* b10: Dack active select */ + #define USB_DFORM (0x0380U) /* b9-7: DMA mode select */ + #define USB_CPU_ADR_RD_WR (0x0000U) /* Address + RD/WR mode (CPU bus) */ + #define USB_CPU_DACK_RD_WR (0x0100U) /* DACK + RD/WR (CPU bus) */ + #define USB_CPU_DACK_ONLY (0x0180U) /* DACK only (CPU bus) */ + #define USB_SPLIT_DACK_ONLY (0x0200U) /* DACK only (SPLIT bus) */ + #define USB_DENDA (0x0040U) /* b6: Dend active select */ + #define USB_PKTM (0x0020U) /* b5: Packet mode */ + #define USB_DENDE (0x0010U) /* b4: Dend enable */ + #define USB_OBUS (0x0004U) /* b2: OUTbus mode */ + +/* USB IO Register Reserved bit mask */ + #define INTSTS1_MASK (0xD870U) /* INTSTS1 Reserved bit mask */ + #define BRDYSTS_MASK (0x03FFU) /* BRDYSTS Reserved bit mask */ + #define NRDYSTS_MASK (0x03FFU) /* NRDYSTS Reserved bit mask */ + #define BEMPSTS_MASK (0x03FFU) /* BEMPSTS Reserved bit mask */ + + #ifdef __cplusplus +} + #endif + +#endif /* R_USB_BITDEFINE_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h new file mode 100644 index 0000000000..4f62f6bce0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h @@ -0,0 +1,84 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef R_USB_DMAC_H +#define R_USB_DMAC_H + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + #include "r_dmac.h" + #elif (USB_CFG_DTC == USB_CFG_ENABLE) + #include "r_dtc.h" + #endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/******************************************************************************* + * Macro definitions + *******************************************************************************/ + #define USB_DMA_USE_CH_MAX (4) /* MAX USE DMAC CH for USB */ + #define USB_DMA_CH_PRI (3) /* DMACmI interrupt priority level for USB Pipe : DxFIFO->buff */ + #define USB_DMA_CH2_PRI (3) /* DMACmI interrupt priority level for USB Pipe : buff->DxFIFO */ + + #define USB_FIFO_ACCESS_TYPE_32BIT (0) /* FIFO port 32bit access */ + #define USB_FIFO_ACCESS_TYPE_16BIT (1) /* FIFO port 16bit access */ + #define USB_FIFO_ACCESS_TYPE_8BIT (2) /* FIFO port 8bit access */ + + #define USB_FIFO_ACCSESS_TYPE_NUM (USB_FIFO_ACCESS_TYPE_8BIT + 1) /* */ + + #define USB_BIT_MBW32 (3UL) /* Mod 4(4Byte=32Bit) */ + #define USB_BIT_MBW16 (1UL) /* Mod 2(2Byte=16Bit) */ + + #define USB_BIT_32_WIDTH (4) + #define USB_BIT_16_WIDTH (2) + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + #define USB_DMAC_PRV_REG(ch) ((R_DMAC0_Type *) ((R_DMAC1_BASE - R_DMAC0_BASE) * ch + R_DMAC0_BASE)) + #endif /* #if (USB_CFG_DMA == USB_CFG_ENABLE) */ + +/****************************************************************************** + * Exported global functions (to be accessed by other files) + ******************************************************************************/ +extern uint32_t g_usb_cstd_dma_size[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 buffer size */ +extern uint16_t g_usb_cstd_dma_fifo[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 FIFO buffer size */ +extern uint16_t g_usb_cstd_dma_pipe[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 pipe number */ + +void usb_cstd_dma_driver(void); +uint16_t usb_cstd_dma_get_crtb(usb_utr_t * p_utr); +uint16_t usb_cstd_dma_get_ir_vect(usb_utr_t * ptr, uint16_t use_port); +void usb_cstd_dma_clear_ir(usb_utr_t * ptr, uint16_t use_port); +void usb_cstd_dma_rcv_setting(usb_utr_t * ptr, uint32_t des_addr, uint16_t useport, uint32_t transfer_size); +void usb_cstd_dma_send_setting(usb_utr_t * ptr, uint32_t src_adr, uint16_t useport, uint32_t transfer_size); +void usb_cstd_transfer_wait(usb_utr_t * ptr, uint8_t dir); +void usb_cstd_dma_stop(usb_utr_t * p_utr, uint16_t use_port); +void usb_cstd_dfifo_end(usb_utr_t * ptr, uint16_t useport); +uint32_t hw_usb_get_dxfifo_adr(usb_utr_t * ptr, uint16_t use_port, uint16_t bit_width); + +uint8_t usb_cstd_dma_ref_ch_no(usb_utr_t * p_utr, uint16_t use_port); +void usb_cstd_dma_send_continue(usb_utr_t * ptr, uint16_t useport); + +void usb_cstd_dma_rcv_start(usb_utr_t * ptr, uint16_t pipe, uint16_t useport); +void usb_cstd_dma_send_start(usb_utr_t * ptr, uint16_t pipe, uint16_t useport); +void usb_cstd_dma_send_restart(usb_utr_t * ptr, uint32_t src, uint32_t data_size, uint8_t pipe); +void usb_cstd_dma_send_complete(uint8_t ip_no, uint16_t use_port); + + #if (USB_CFG_DMA == USB_CFG_ENABLE) +void usb_ip0_d1fifo_callback(dmac_callback_args_t * cb_data); +void usb_ip1_d1fifo_callback(dmac_callback_args_t * cb_data); + + #endif /* #if (USB_CFG_DMA == USB_CFG_ENABLE) */ + +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_DMAC_H */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h new file mode 100644 index 0000000000..5326204714 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h @@ -0,0 +1,449 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +#ifndef HW_USB_REG_ACCESS_H + #define HW_USB_REG_ACCESS_H + + #ifdef __cplusplus +extern "C" { + #endif + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + #define USB_BUFSIZE_BIT (10U) + #define USB_SUSPEND_MODE (1U) + #define USB_NORMAL_MODE (0) + + #define USB0_CFIFO8 (USB_M0->CFIFOLL) + #define USB0_D0FIFO8 (USB_M0->D0FIFOLL) + #define USB0_D1FIFO8 (USB_M0->D1FIFOLL) + #define USB0_CFIFO16 (USB_M0->CFIFOL) + #define USB0_D0FIFO16 (USB_M0->D0FIFOL) + #define USB0_D1FIFO16 (USB_M0->D1FIFOL) + + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + + #define USB1_CFIFO8 (USB_M1->CFIFOHH) + #define USB1_D0FIFO8 (USB_M1->D0FIFOHH) + #define USB1_D1FIFO8 (USB_M1->D1FIFOHH) + #define USB1_CFIFO16 (USB_M1->CFIFOH) + #define USB1_D0FIFO16 (USB_M1->D0FIFOH) + #define USB1_D1FIFO16 (USB_M1->D1FIFOH) + + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + + #if USB_CFG_ENDIAN == USB_CFG_BIG + #define USB1_CFIFO8 (USB_M1->CFIFOLL) + #define USB1_D0FIFO8 (USB_M1->D0FIFOLL) + #define USB1_D1FIFO8 (USB_M1->D1FIFOLL) + #define USB1_CFIFO16 (USB_M1->CFIFOL) + #define USB1_D0FIFO16 (USB_M1->D0FIFOL) + #define USB1_D1FIFO16 (USB_M1->D1FIFOL) + + #endif /* USB_CFG_ENDIAN == USB_CFG_BIG */ + + #define USB1_CFIFO32 (USB_M1->CFIFO) + #define USB1_D0FIFO32 (USB_M1->D0FIFO) + #define USB1_D1FIFO32 (USB_M1->D1FIFO) + + #if defined(USB_LDO_REGULATOR_MODULE) + #define USB_LDO_REGULATOR_MODULE + #endif /* USB_LDO_REGULATOR_MODULE */ + +/****************/ +/* INITIARIZE */ +/****************/ +void hw_usb_hmodule_init(uint8_t usb_ip); +void hw_usb_pmodule_init(uint8_t usb_ip); + +/************/ +/* SYSCFG */ +/************/ +uint16_t hw_usb_read_syscfg(usb_utr_t * ptr); +void hw_usb_write_syscfg(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_cnen(usb_utr_t * ptr); +void hw_usb_set_hse(usb_utr_t * ptr); +void hw_usb_clear_hse(usb_utr_t * ptr); +void hw_usb_set_dcfm(usb_utr_t * p_utr); +void hw_usb_clear_dcfm(usb_utr_t * ptr); +void hw_usb_set_drpd(usb_utr_t * ptr); +void hw_usb_clear_drpd(usb_utr_t * ptr); +void hw_usb_set_usbe(usb_utr_t * ptr); +void hw_usb_clear_usbe(usb_utr_t * ptr); + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +void hw_usb_set_cnen(uint8_t usb_ip); +void hw_usb_pset_dprpu(uint8_t usb_ip); +void hw_usb_pclear_dprpu(uint8_t usb_ip); +void hw_usb_pcontrol_dprpu(uint8_t usb_ip, uint8_t state); +void hw_usb_pcontrol_dcpctr_pid(uint8_t usb_ip, uint16_t data); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/************/ +/* BUSWAIT */ +/************/ +void hw_usb_set_buswait(usb_utr_t * ptr); + +/************/ +/* SYSSTS0 */ +/************/ +uint16_t hw_usb_read_syssts(usb_utr_t * ptr); + +/**************/ +/* DVSTCTR0 */ +/**************/ +uint16_t hw_usb_read_dvstctr(usb_utr_t * ptr); +void hw_usb_write_dvstctr(usb_utr_t * ptr, uint16_t data); +void hw_usb_rmw_dvstctr(usb_utr_t * ptr, uint16_t data, uint16_t bitptn); +void hw_usb_clear_dvstctr(usb_utr_t * ptr, uint16_t bitptn); +void hw_usb_set_vbout(usb_utr_t * ptr); +void hw_usb_clear_vbout(usb_utr_t * ptr); +void hw_usb_set_hnpbtoa(usb_utr_t * p_utr); +void hw_usb_clear_hnpbtoa(usb_utr_t * p_utr); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void hw_usb_hset_rwupe(usb_utr_t * ptr); +void hw_usb_hclear_rwupe(usb_utr_t * ptr); +void hw_usb_hset_resume(usb_utr_t * ptr); +void hw_usb_hclear_resume(usb_utr_t * ptr); +void hw_usb_hset_uact(usb_utr_t * ptr); +void hw_usb_hclear_uact(usb_utr_t * ptr); +void hw_usb_hmodule_otg_init(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +void hw_usb_pset_wkup(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/**************/ +/* TESTMODE */ +/**************/ +void hw_usb_set_utst(usb_utr_t * ptr, uint16_t data); + +/***************************/ +/* CFIFO, D0FIFO, D1FIFO */ +/***************************/ +uint32_t hw_usb_read_fifo32(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_write_fifo32(usb_utr_t * ptr, uint16_t pipemode, uint32_t data); +uint16_t hw_usb_read_fifo16(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_write_fifo16(usb_utr_t * ptr, uint16_t pipemode, uint16_t data); +void hw_usb_write_fifo8(usb_utr_t * ptr, uint16_t pipemode, uint8_t data); + +/************************************/ +/* CFIFOSEL, D0FIFOSEL, D1FIFOSEL */ +/************************************/ +uint16_t hw_usb_read_fifosel(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_rmw_fifosel(usb_utr_t * ptr, uint16_t pipemode, uint16_t data, uint16_t bitptn); +void hw_usb_set_dclrm(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_clear_dclrm(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_set_dreqe(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_clear_dreqe(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_set_mbw(usb_utr_t * ptr, uint16_t pipemode, uint16_t data); +void hw_usb_set_curpipe(usb_utr_t * ptr, uint16_t pipemode, uint16_t pipeno); + +/**********************************/ +/* CFIFOCTR, D0FIFOCTR, D1FIFOCTR */ +/**********************************/ +uint16_t hw_usb_read_fifoctr(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_set_bval(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_set_bclr(usb_utr_t * ptr, uint16_t pipemode); + +/*************/ +/* INTENB0 */ +/*************/ +uint16_t hw_usb_ReadIntenb(usb_utr_t * ptr); +void hw_usb_write_intenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_set_intenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_enb_vbse(usb_utr_t * ptr); +void hw_usb_clear_enb_sofe(usb_utr_t * ptr); + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +void hw_usb_pset_enb_rsme(uint8_t usb_ip); +void hw_usb_pclear_enb_rsme(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/*************/ +/* BRDYENB */ +/*************/ +void hw_usb_write_brdyenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_set_brdyenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_brdyenb(usb_utr_t * ptr, uint16_t pipeno); + +/*************/ +/* NRDYENB */ +/*************/ +void hw_usb_write_nrdyenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_set_nrdyenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_nrdyenb(usb_utr_t * ptr, uint16_t pipeno); + +/*************/ +/* BEMPENB */ +/*************/ +void hw_usb_write_bempenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_set_bempenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_bempenb(usb_utr_t * ptr, uint16_t pipeno); + +/*************/ +/* SOFCFG */ +/*************/ +void hw_usb_set_sofcfg(usb_utr_t * ptr, uint16_t data); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void hw_usb_hset_trnensel(usb_utr_t * ptr); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/*************/ +/* INTSTS0 */ +/*************/ +void hw_usb_write_intsts(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_sts_sofr(usb_utr_t * ptr); + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +uint16_t hw_usb_read_intsts(uint8_t usb_ip); +void hw_usb_pclear_sts_resm(uint8_t usb_ip); +void hw_usb_pclear_sts_valid(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/************/ +/* BRDYSTS */ +/************/ +uint16_t hw_usb_read_brdysts(usb_utr_t * ptr); +void hw_usb_write_brdysts(usb_utr_t * pt, uint16_t data); +void hw_usb_clear_sts_brdy(usb_utr_t * ptr, uint16_t pipeno); + +/************/ +/* NRDYSTS */ +/************/ +void hw_usb_write_nrdy_sts(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_status_nrdy(usb_utr_t * ptr, uint16_t pipeno); + +/************/ +/* BEMPSTS */ +/************/ +void hw_usb_write_bempsts(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_status_bemp(usb_utr_t * ptr, uint16_t pipeno); + +/************/ +/* FRMNUM */ +/************/ +uint16_t hw_usb_read_frmnum(usb_utr_t * ptr); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/************/ +/* USBREQ */ +/************/ +void hw_usb_hwrite_usbreq(usb_utr_t * ptr, uint16_t data); + +/************/ +/* USBVAL */ +/************/ +void hw_usb_hset_usbval(usb_utr_t * ptr, uint16_t data); + +/************/ +/* USBINDX */ +/************/ +void hw_usb_hset_usbindx(usb_utr_t * ptr, uint16_t data); + +/************/ +/* USBLENG */ +/************/ +void hw_usb_hset_usbleng(usb_utr_t * ptr, uint16_t data); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/************/ +/* USBREQ */ +/************/ +uint16_t hw_usb_read_usbreq(uint8_t usb_ip); + +/************/ +/* USBVAL */ +/************/ +uint16_t hw_usb_read_usbval(uint8_t usb_ip); + +/************/ +/* USBINDX */ +/************/ +uint16_t hw_usb_read_usbindx(uint8_t usb_ip); + +/************/ +/* USBLENG */ +/************/ +uint16_t hw_usb_read_usbleng(uint8_t usb_ip); + + #else + #if defined(USB_CFG_HUVC_USE) + +/************/ +/* USBREQ */ +/************/ +uint16_t hw_usb_read_usbreq(uint8_t usb_ip); + + #endif + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/************/ +/* DCPCFG */ +/************/ +uint16_t hw_usb_read_dcpcfg(usb_utr_t * ptr); +void hw_usb_write_dcpcfg(usb_utr_t * ptr, uint16_t data); + +/************/ +/* DCPMAXP */ +/************/ +uint16_t hw_usb_read_dcpmaxp(usb_utr_t * ptr); +void hw_usb_write_dcpmxps(usb_utr_t * ptr, uint16_t data); + +/************/ +/* DCPCTR */ +/************/ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void hw_usb_hwrite_dcpctr(usb_utr_t * ptr, uint16_t data); +void hw_usb_hset_sureq(usb_utr_t * ptr); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +uint16_t hw_usb_read_dcpctr(uint8_t usb_ip); +void hw_usb_pset_ccpl(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/************/ +/* PIPESEL */ +/************/ +void hw_usb_write_pipesel(usb_utr_t * ptr, uint16_t data); + +/************/ +/* PIPECFG */ +/************/ +uint16_t hw_usb_read_pipecfg(usb_utr_t * ptr); +void hw_usb_write_pipecfg(usb_utr_t * ptr, uint16_t data); + +/************/ +/* PIPEBUF */ +/************/ +void hw_usb_write_pipebuf(usb_utr_t * ptr, uint16_t data); +uint16_t hw_usb_read_pipebuf(usb_utr_t * ptr); + +/************/ +/* PIPEMAXP */ +/************/ +uint16_t hw_usb_read_pipemaxp(usb_utr_t * ptr); +void hw_usb_write_pipemaxp(usb_utr_t * ptr, uint16_t data); + +/************/ +/* PIPEPERI */ +/************/ +void hw_usb_write_pipeperi(usb_utr_t * ptr, uint16_t data); + +/********************/ +/* DCPCTR, PIPEnCTR */ +/********************/ +uint16_t hw_usb_read_pipectr(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_write_pipectr(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); +void hw_usb_set_csclr(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_aclrm(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_aclrm(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_sqclr(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_sqset(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_pid(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); +void hw_usb_clear_pid(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); + +/************/ +/* PIPEnTRE */ +/************/ +void hw_usb_set_trenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_trenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_trclr(usb_utr_t * ptr, uint16_t pipeno); + +/************/ +/* PIPEnTRN */ +/************/ +void hw_usb_write_pipetrn(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); + +/************/ +/* BCCTRL */ +/************/ +void hw_usb_set_bcctrl(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_bcctrl(usb_utr_t * ptr, uint16_t data); +uint16_t hw_usb_read_bcctrl(usb_utr_t * ptr); +void hw_usb_set_vdmsrce(usb_utr_t * ptr); +void hw_usb_clear_vdmsrce(usb_utr_t * ptr); +void hw_usb_set_idpsinke(usb_utr_t * ptr); +void hw_usb_set_suspendm(uint8_t usb_ip); +void hw_usb_clear_suspm(uint8_t usb_ip); +void hw_usb_clear_idpsinke(usb_utr_t * ptr); +void hw_usb_set_vdcen(void); +void hw_usb_clear_vdcen(void); +void hw_usb_set_uckselc(void); +void hw_usb_clear_uckselc(void); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void hw_usb_hset_dcpmode(usb_utr_t * ptr); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/**********************************/ +/* DMA0CFG, DMA1CFG for 597ASSP */ +/**********************************/ +void hw_usb_write_dmacfg(usb_utr_t * ptr, uint16_t pipemode, uint16_t data); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/*************/ +/* INTENB1 */ +/*************/ +void hw_usb_hwrite_intenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_hset_enb_ovrcre(usb_utr_t * ptr); +void hw_usb_hclear_enb_ovrcre(usb_utr_t * ptr); +void hw_usb_hset_enb_bchge(usb_utr_t * ptr); +void hw_usb_hclear_enb_bchge(usb_utr_t * ptr); +void hw_usb_hset_enb_dtche(usb_utr_t * ptr); +void hw_usb_hclear_enb_dtche(usb_utr_t * ptr); +void hw_usb_hset_enb_attche(usb_utr_t * ptr); +void hw_usb_hclear_enb_attche(usb_utr_t * ptr); +void hw_usb_hset_enb_signe(usb_utr_t * ptr); +void hw_usb_hset_enb_sacke(usb_utr_t * ptr); +void hw_usb_hset_enb_pddetinte(usb_utr_t * ptr); + +/*************/ +/* INTSTS1 */ +/*************/ +void hw_usb_hwrite_intsts(usb_utr_t * ptr, uint16_t data); +void hw_usb_hclear_sts_ovrcr(usb_utr_t * ptr); +void hw_usb_hclear_sts_bchg(usb_utr_t * ptr); +void hw_usb_hclear_sts_dtch(usb_utr_t * ptr); +void hw_usb_hclear_sts_attch(usb_utr_t * ptr); +void hw_usb_hclear_sts_sign(usb_utr_t * ptr); +void hw_usb_hclear_sts_sack(usb_utr_t * ptr); +void hw_usb_hclear_sts_pddetint(usb_utr_t * ptr); + +/************/ +/* DEVADDn */ +/************/ +uint16_t hw_usb_hread_devadd(usb_utr_t * ptr, uint16_t devsel); +void hw_usb_hrmw_devadd(usb_utr_t * ptr, uint16_t devsel, uint16_t data, uint16_t width); +void hw_usb_hset_usbspd(usb_utr_t * ptr, uint16_t devsel, uint16_t data); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + #ifdef __cplusplus +} + #endif + +#endif /* HW_USB_REG_ACCESS_H */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_abs.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_abs.c new file mode 100644 index 0000000000..e04acf8a65 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_abs.c @@ -0,0 +1,506 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS != 0) + #include "../driver/inc/r_usb_cstd_rtos.h" +#endif /* #if (BSP_CFG_RTOS != 0) */ + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ +#define USB_READ_PIPECTR_CNT (0xFFFFU) +#define USB_VALUE_100 (100) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +uint16_t g_usb_hstd_use_pipe[USB_NUM_USBIP]; + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : usb_cstd_get_buf_size + * Description : Return buffer size, or max packet size, of specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * Return value : uint16_t : FIFO buffer size or max packet size. + ******************************************************************************/ +uint16_t usb_cstd_get_buf_size (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t size; + uint16_t buffer; + + if (USB_PIPE0 == pipe) + { + buffer = hw_usb_read_dcpcfg(ptr); + if (USB_CFG_CNTMDON == (buffer & USB_CNTMDFIELD)) + { + /* Continuation transmit */ + /* Buffer Size */ + size = USB_PIPE0BUF; + } + else + { + /* Not continuation transmit */ + buffer = hw_usb_read_dcpmaxp(ptr); + + /* Max Packet Size */ + size = (uint16_t) (buffer & USB_MAXP); + } + } + else + { + /* Pipe select */ + hw_usb_write_pipesel(ptr, pipe); + +#if defined(USB_HIGH_SPEED_MODULE) + + /* Read CNTMD */ + buffer = hw_usb_read_pipecfg(ptr); + if (USB_CFG_CNTMDON == (buffer & USB_CNTMDFIELD)) + { + buffer = hw_usb_read_pipebuf(ptr); + + /* Buffer Size */ + size = (uint16_t) ((uint16_t) ((buffer >> USB_BUFSIZE_BIT) + 1) * USB_PIPEXBUF); + } + else + { +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + buffer = hw_usb_read_pipemaxp(ptr); + + /* Max Packet Size */ + size = (uint16_t) (buffer & USB_MXPS); +#if defined(USB_HIGH_SPEED_MODULE) + } +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + + return size; +} + +/****************************************************************************** + * End of function usb_cstd_get_buf_size + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_pipe_init + * Description : Initialization of registers associated with specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe Number + * Return value : none + ******************************************************************************/ +void usb_cstd_pipe_init (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t useport = USB_CUSE; + uint16_t ip_no = ptr->ip; + + if (g_usb_usbmode[ip_no] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (BSP_CFG_RTOS != 0) + if (USB_NULL != g_p_usb_pstd_pipe[pipe]) + { + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_pstd_pipe[pipe]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_pstd_pipe[pipe]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + } + #endif /* (BSP_CFG_RTOS != 0) */ + + g_p_usb_pstd_pipe[pipe] = (usb_utr_t *) USB_NULL; + useport = usb_pstd_pipe2fport(ptr, pipe); + ip_no = ptr->ip; +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if (BSP_CFG_RTOS != 0) + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][pipe]) + { + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_hstd_pipe[ptr->ip][pipe]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_hstd_pipe[ptr->ip][pipe]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + } + #endif /* (BSP_CFG_RTOS != 0) */ + + g_p_usb_hstd_pipe[ptr->ip][pipe] = (usb_utr_t *) USB_NULL; + useport = usb_hstd_pipe2fport(ptr, pipe); + ip_no = ptr->ip; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + /* Interrupt Disable */ + /* Ready Int Disable */ + hw_usb_clear_brdyenb(ptr, pipe); + + /* NotReady Int Disable */ + hw_usb_clear_nrdyenb(ptr, pipe); + + /* Empty/SizeErr Int Disable */ + hw_usb_clear_bempenb(ptr, pipe); + + /* PID=NAK & clear STALL */ + usb_cstd_clr_stall(ptr, pipe); + + /* PIPE Configuration */ + hw_usb_write_pipesel(ptr, pipe); + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + + /* Update use pipe no info */ + if (USB_NULL != g_usb_pipe_table[ip_no][pipe].pipe_cfg) + { + g_usb_hstd_use_pipe[ip_no] = (uint16_t) (g_usb_hstd_use_pipe[ip_no] | ((uint16_t) 1 << pipe)); + } + else + { + g_usb_hstd_use_pipe[ip_no] = (uint16_t) (g_usb_hstd_use_pipe[ip_no] & (~((uint16_t) 1 << pipe))); + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + if ((USB_D0USE == useport) || (USB_D1USE == useport)) + { + g_usb_pipe_table[ip_no][pipe].pipe_cfg |= USB_BFREON; + } + + hw_usb_write_pipecfg(ptr, g_usb_pipe_table[ip_no][pipe].pipe_cfg); + +#if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ip_no) + { + hw_usb_write_pipebuf(ptr, g_usb_pipe_table[ip_no][pipe].pipe_buf); + } +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + hw_usb_write_pipemaxp(ptr, g_usb_pipe_table[ip_no][pipe].pipe_maxp); + hw_usb_write_pipeperi(ptr, g_usb_pipe_table[ip_no][pipe].pipe_peri); + + /* FIFO buffer DATA-PID initialized */ + hw_usb_write_pipesel(ptr, USB_PIPE0); + + /* SQCLR */ + hw_usb_set_sqclr(ptr, pipe); + + /* ACLRM */ + usb_cstd_do_aclrm(ptr, pipe); + + /* CSSTS */ + hw_usb_set_csclr(ptr, pipe); + + /* Interrupt status clear */ + /* Ready Int Clear */ + hw_usb_clear_sts_brdy(ptr, pipe); + + /* NotReady Int Clear */ + hw_usb_clear_status_nrdy(ptr, pipe); + + /* Empty/SizeErr Int Clear */ + hw_usb_clear_status_bemp(ptr, pipe); +} + +/****************************************************************************** + * End of function usb_cstd_pipe_init + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_clr_pipe_cnfg + * Description : Clear specified pipe configuration register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe_no : pipe number + * Return value : none + ******************************************************************************/ +void usb_cstd_clr_pipe_cnfg (usb_utr_t * ptr, uint16_t pipe_no) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (BSP_CFG_RTOS != 0) + if (USB_NULL != g_p_usb_pstd_pipe[pipe_no]) + { + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_pstd_pipe[pipe_no]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_pstd_pipe[pipe_no]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + } + #endif /* (BSP_CFG_RTOS != 0) */ + + g_p_usb_pstd_pipe[pipe_no] = (usb_utr_t *) USB_NULL; +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if (BSP_CFG_RTOS != 0) + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][pipe_no]) + { + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_hstd_pipe[ptr->ip][pipe_no]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_hstd_pipe[ptr->ip][pipe_no]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + } + #endif /* (BSP_CFG_RTOS != 0) */ + + g_p_usb_hstd_pipe[ptr->ip][pipe_no] = (usb_utr_t *) USB_NULL; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + /* PID=NAK & clear STALL */ + usb_cstd_clr_stall(ptr, pipe_no); + + /* Interrupt disable */ + /* Ready Int Disable */ + hw_usb_clear_brdyenb(ptr, pipe_no); + + /* NotReady Int Disable */ + hw_usb_clear_nrdyenb(ptr, pipe_no); + + /* Empty/SizeErr Int Disable */ + hw_usb_clear_bempenb(ptr, pipe_no); + + /* PIPE Configuration */ + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, USB_FALSE); + hw_usb_write_pipesel(ptr, pipe_no); + hw_usb_write_pipecfg(ptr, 0); + +#if defined(USB_HIGH_SPEED_MODULE) + hw_usb_write_pipebuf(ptr, 0); +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + hw_usb_write_pipemaxp(ptr, 0); + hw_usb_write_pipeperi(ptr, 0); + hw_usb_write_pipesel(ptr, 0); + + /* FIFO buffer DATA-PID initialized */ + /* SQCLR */ + hw_usb_set_sqclr(ptr, pipe_no); + + /* ACLRM */ + usb_cstd_do_aclrm(ptr, pipe_no); + + /* CSSTS */ + hw_usb_set_csclr(ptr, pipe_no); + usb_cstd_clr_transaction_counter(ptr, pipe_no); + + /* Interrupt status clear */ + /* Ready Int Clear */ + hw_usb_clear_sts_brdy(ptr, pipe_no); + + /* NotReady Int Clear */ + hw_usb_clear_status_nrdy(ptr, pipe_no); + + /* Empty/SizeErr Int Clear */ + hw_usb_clear_status_bemp(ptr, pipe_no); +} + +/****************************************************************************** + * End of function usb_cstd_clr_pipe_cnfg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_set_nak + * Description : Set up to NAK the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe Number + * Return value : none + ******************************************************************************/ +void usb_cstd_set_nak (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t buf; + uint16_t n; + + /* Set NAK */ + hw_usb_clear_pid(ptr, pipe, (uint16_t) USB_PID_BUF); + + /* The state of PBUSY continues while transmitting the packet when it is a detach. */ + /* 1ms comes off when leaving because the packet duration might not exceed 1ms. */ + /* Whether it is PBUSY release or 1ms passage can be judged. */ + /* WAIT_LOOP */ + for (n = 0; n < USB_READ_PIPECTR_CNT; ++n) + { + /* PIPE control reg read */ + buf = hw_usb_read_pipectr(ptr, pipe); + if (0 == (uint16_t) (buf & USB_PBUSY)) + { + n = USB_READ_PIPECTR_CNT - 1; + } + } +} + +/****************************************************************************** + * End of function usb_cstd_set_nak + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_is_set_frdy + * Description : Changes the specified FIFO port by the specified pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe Number + * : uint16_t fifosel : FIFO select + * : uint16_t isel : ISEL bit status + * Return value : FRDY status + ******************************************************************************/ +uint16_t usb_cstd_is_set_frdy (usb_utr_t * ptr, uint16_t pipe, uint16_t fifosel, uint16_t isel) +{ + uint16_t buffer; + uint16_t i; + + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(ptr, pipe, fifosel, isel); + + /* WAIT_LOOP */ + + for (i = 0; i < USB_VALUE_100; i++) + { + buffer = hw_usb_read_fifoctr(ptr, fifosel); + + if (USB_FRDY == (uint16_t) (buffer & USB_FRDY)) + { + return buffer; + } + + USB_PRINTF1("*** FRDY wait pipe = %d\n", pipe); + + /* Caution!!! + * Depending on the external bus speed of CPU, you may need to wait + * for 100ns here. + * For details, please look at the data sheet. *//***** The example of reference. *****/ + buffer = hw_usb_read_syscfg(ptr); + (void) buffer; + buffer = hw_usb_read_syssts(ptr); + (void) buffer; + + usb_cpu_delay_1us((uint16_t) 10); + + /*************************************/ + } + + return USB_FIFOERROR; +} + +/****************************************************************************** + * End of function usb_cstd_is_set_frdy + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_chg_curpipe + * Description : Switch FIFO and pipe number. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe number. + * : uint16_t fifosel : FIFO selected (CPU, D0, D1..) + * : uint16_t isel : CFIFO Port Access Direction.(Pipe1 to 9:Set to 0) + * Return value : none + ******************************************************************************/ +void usb_cstd_chg_curpipe (usb_utr_t * ptr, uint16_t pipe, uint16_t fifosel, uint16_t isel) +{ + uint16_t buffer; + + /* Select FIFO */ + switch (fifosel) + { + /* CFIFO use */ + case USB_CUSE: + { + /* ISEL=1, CURPIPE=0 */ + hw_usb_rmw_fifosel(ptr, USB_CUSE, ((USB_RCNT | isel) | pipe), ((USB_RCNT | USB_ISEL) | USB_CURPIPE)); + + /* WAIT_LOOP */ + do + { + buffer = hw_usb_read_fifosel(ptr, USB_CUSE); + } while ((buffer & (uint16_t) (USB_ISEL | USB_CURPIPE)) != (uint16_t) (isel | pipe)); + + break; + } + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* D0FIFO use */ + case USB_D0USE: + + /* D1FIFO use */ + case USB_D1USE: + { + /* DxFIFO pipe select */ + hw_usb_set_curpipe(ptr, fifosel, pipe); + + /* WAIT_LOOP */ + do + { + buffer = hw_usb_read_fifosel(ptr, fifosel); + } while ((uint16_t) (buffer & USB_CURPIPE) != pipe); + + break; + } +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + default: + { + break; + } + } +} + +/****************************************************************************** + * End of function usb_cstd_chg_curpipe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_set_transaction_counter + * Description : Set specified Pipe Transaction Counter Register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t trnreg : Pipe number + * : uint16_t trncnt : Transaction counter + * Return value : none + ******************************************************************************/ +void usb_cstd_set_transaction_counter (usb_utr_t * ptr, uint16_t trnreg, uint16_t trncnt) +{ + hw_usb_set_trclr(ptr, trnreg); + hw_usb_write_pipetrn(ptr, trnreg, trncnt); + hw_usb_set_trenb(ptr, trnreg); +} + +/****************************************************************************** + * End of function usb_cstd_set_transaction_counter + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_clr_transaction_counter + * Description : Clear specified Pipe Transaction Counter Register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t trnreg : Pipe Number + * Return value : none + ******************************************************************************/ +void usb_cstd_clr_transaction_counter (usb_utr_t * ptr, uint16_t trnreg) +{ + hw_usb_clear_trenb(ptr, trnreg); + hw_usb_set_trclr(ptr, trnreg); +} + +/****************************************************************************** + * End of function usb_cstd_clr_transaction_counter + ******************************************************************************/ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c new file mode 100644 index 0000000000..ecf81bce40 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c @@ -0,0 +1,3932 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +#define USB_VALUE_0F00H (0x0f00) + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ +static void * hw_usb_get_fifosel_adr(usb_utr_t * ptr, uint16_t pipemode); +static void * hw_usb_get_fifoctr_adr(usb_utr_t * ptr, uint16_t pipemode); + +/****************************************************************************** + * Function Name : hw_usb_read_syscfg + * Description : Returns the specified port's SYSCFG register value. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : SYSCFG content. + ******************************************************************************/ +uint16_t hw_usb_read_syscfg (usb_utr_t * ptr) +{ + uint16_t ret_code = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + ret_code = USB_M0->SYSCFG; + } + else + { + ret_code = USB_M1->SYSCFG; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ret_code = ptr->ipp->SYSCFG; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return ret_code; +} + +/****************************************************************************** + * End of function hw_usb_read_syscfg + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_write_syscfg + * Description : Write specified value to the SYSCFG register of the given port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_write_syscfg (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->SYSCFG = data; +} + +/****************************************************************************** + * End of function hw_usb_write_syscfg + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if defined(USB_HIGH_SPEED_MODULE) + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Function Name : hw_usb_set_cnen + * Description : Enable single end receiver. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_set_cnen (uint8_t usb_ip) +{ + /* Only USBA module */ + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->SYSCFG |= USB_CNEN; + } +} + +/****************************************************************************** + * End of function hw_usb_set_cnen + ******************************************************************************/ + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * Function Name : hw_usb_clear_cnen + * Description : Disable single end receiver. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_cnen (usb_utr_t * ptr) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_CNEN)); + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp1->SYSCFG = (uint16_t) (ptr->ipp1->SYSCFG & (~USB_CNEN)); + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_cnen + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_hse + * Description : Not processed as the functionality is provided by R8A66597(ASSP). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_set_hse (usb_utr_t * ptr) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + USB_M1->SYSCFG |= USB_HSE; + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP1 == ptr->ip) + { + ptr->ipp1->SYSCFG |= USB_HSE; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_hse + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_hse + * Description : Clears HSE bit of the specified port's SYSCFG register + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_hse (usb_utr_t * ptr) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_HSE)); + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP1 == ptr->ip) + { + ptr->ipp->SYSCFG = (uint16_t) (ptr->ipp->SYSCFG & (~USB_HSE)); + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} /* End of function hw_usb_clear_hse */ + +/****************************************************************************** + * End of function hw_usb_clear_hse + ******************************************************************************/ +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + +/****************************************************************************** + * Function Name : hw_usb_set_dcfm + * Description : DCFM-bit set of register SYSCFG + * : (USB Host mode is selected.) + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_set_dcfm (usb_utr_t * p_utr) +{ + if (USB_CFG_IP0 == p_utr->ip) + { + USB_M0->SYSCFG |= USB_DCFM; + } + else + { + USB_M1->SYSCFG |= USB_DCFM; + } +} + +/****************************************************************************** + * End of function hw_usb_set_dcfm + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_dcfm + * Description : DCFM-bit clear of register SYSCFG. + * : (USB Peripheral mode is selected.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_dcfm (usb_utr_t * ptr) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->SYSCFG = (uint16_t) (USB_M0->SYSCFG & (~USB_DCFM)); + } + else + { + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_DCFM)); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->SYSCFG = (uint16_t) (ptr->ipp->SYSCFG & (~USB_DCFM)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_dcfm + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_set_drpd + * Description : Set bit of the specified port's SYSCFG DRPD register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_set_drpd (usb_utr_t * ptr) +{ + ptr->ipp->SYSCFG |= USB_DRPD; +} + +/****************************************************************************** + * End of function hw_usb_clear_drpd + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_drpd + * Description : Clear bit of the specified port's SYSCFG DRPD register. + * : (for USB Host mode; Enable D + / D-line PullDown.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_drpd (usb_utr_t * ptr) +{ + ptr->ipp->SYSCFG = (uint16_t) (ptr->ipp->SYSCFG & (~USB_DRPD)); +} + +/****************************************************************************** + * End of function hw_usb_clear_drpd + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_set_usbe + * Description : Enable USB operation. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_set_usbe (usb_utr_t * ptr) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->SYSCFG |= USB_USBE; + } + else + { + USB_M1->SYSCFG |= USB_USBE; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->SYSCFG |= USB_USBE; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_usbe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_usbe + * Description : Enable USB operation. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_usbe (usb_utr_t * ptr) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->SYSCFG = (uint16_t) (USB_M0->SYSCFG & (~USB_USBE)); + } + else + { + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_USBE)); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->SYSCFG = (uint16_t) (ptr->ipp->SYSCFG & (~USB_USBE)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_usbe + ******************************************************************************/ + +#if defined(USB_HIGH_SPEED_MODULE) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_set_buswait + * Description : Set BUSWAIT register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_set_buswait (usb_utr_t * ptr) +{ + ptr->ipp1->BUSWAIT = (USB_VALUE_0F00H | USB_CFG_BUSWAIT); +} + +/****************************************************************************** + * End of function hw_usb_set_buswait + ******************************************************************************/ + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_set_bcctrl + * Description : Set BCCTRL's bits. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_set_bcctrl (usb_utr_t * ptr, uint16_t data) +{ + FSP_PARAMETER_NOT_USED(data); + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + USB_M1->BCCTRL |= data; + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP1 == ptr->ip) + { + ptr->ipp1->BCCTRL |= data; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_bcctrl + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_bcctrl + * Description : Clear BCCTRL's bits. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_clear_bcctrl (usb_utr_t * ptr, uint16_t data) +{ + FSP_PARAMETER_NOT_USED(data); + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + USB_M1->BCCTRL = (uint16_t) (USB_M1->BCCTRL & (~data)); + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP1 == ptr->ip) + { + ptr->ipp1->BCCTRL = (uint16_t) (ptr->ipp1->BCCTRL & (~data)); + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_bcctrl + ******************************************************************************/ +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + +/****************************************************************************** + * Function Name : hw_usb_read_syssts + * Description : Returns the value of the specified port's SYSSTS register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : SYSSTS0 content + ******************************************************************************/ +uint16_t hw_usb_read_syssts (usb_utr_t * ptr) +{ + uint16_t result = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + result = USB_M0->SYSSTS0; + } + else + { + result = USB_M1->SYSSTS0; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + result = (ptr->ipp->SYSSTS0); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_syssts + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_dvstctr + * Description : Returns the specified port's DVSTCTR register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : DVSTCTR0 content + ******************************************************************************/ +uint16_t hw_usb_read_dvstctr (usb_utr_t * ptr) +{ + uint16_t result = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + result = USB_M0->DVSTCTR0; + } + else + { + result = USB_M1->DVSTCTR0; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp = usb_hstd_get_usb_ip_adr(ptr->ip); + result = (ptr->ipp->DVSTCTR0); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_dvstctr + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_write_dvstctr + * Description : Write data to the specified port's DVSTCTR register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_dvstctr (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->DVSTCTR0 = data; +} + +/****************************************************************************** + * End of function hw_usb_write_dvstctr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_rmw_dvstctr + * Description : Read-modify-write the specified port's DVSTCTR. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : The value to write. + * : uint16_t bitptn: Bit pattern to read-modify-write. + * Return value : none + ******************************************************************************/ +void hw_usb_rmw_dvstctr (usb_utr_t * ptr, uint16_t data, uint16_t bitptn) +{ + uint16_t buf; + + buf = ptr->ipp->DVSTCTR0; + buf = (uint16_t) (buf & (~bitptn)); + buf |= (data & bitptn); + ptr->ipp->DVSTCTR0 = buf; +} + +/****************************************************************************** + * End of function hw_usb_rmw_dvstctr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_dvstctr + * Description : Clear the bit pattern specified in argument, of the specified + * : port's DVSTCTR register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t bitptn: Bit pattern to read-modify-write. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_dvstctr (usb_utr_t * ptr, uint16_t bitptn) +{ + ptr->ipp->DVSTCTR0 = (uint16_t) (ptr->ipp->DVSTCTR0 & (~bitptn)); +} + +/****************************************************************************** + * End of function hw_usb_clear_dvstctr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_vbout + * Description : Set specified port's VBOUT-bit in the DVSTCTR register. + * : (To output a "High" to pin VBOUT.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_set_vbout (usb_utr_t * ptr) +{ + #if USB_CFG_VBUS == USB_CFG_HIGH + #if defined(USB_CFG_OTG_USE) + ptr->ipp->DVSTCTR0 |= USB_EXICEN; + #endif /* defined(USB_CFG_OTG_USE) */ + ptr->ipp->DVSTCTR0 |= USB_VBUSEN; + #else /* USB_CFG_VBUS == USB_CFG_HIGH */ + #if defined(USB_CFG_OTG_USE) + ptr->ipp->DVSTCTR0 = (uint16_t) (ptr->ipp->DVSTCTR0 & (~USB_EXICEN)); + #endif /* defined(USB_CFG_OTG_USE) */ + ptr->ipp->DVSTCTR0 = (uint16_t) (ptr->ipp->DVSTCTR0 & (~USB_VBUSEN)); + #endif /* USB_CFG_VBUS == USB_CFG_HIGH */ +} + +/****************************************************************************** + * End of function hw_usb_set_vbout + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_hnpbtoa + * Description : Set specified port's HNPBTOA bit in the DVSTCTR register. + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_set_hnpbtoa (usb_utr_t * p_utr) +{ + p_utr->ipp->DVSTCTR0 |= USB_HNPBTOA; +} + +/****************************************************************************** + * End of function hw_usb_set_hnpbtoa + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_hnpbtoa + * Description : Clear specified port's HNPBTOA bit in the DVSTCTR register. + * Arguments : usb_utr_t *p_utr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_hnpbtoa (usb_utr_t * p_utr) +{ + p_utr->ipp->DVSTCTR0 = (uint16_t) (p_utr->ipp->DVSTCTR0 & (~USB_HNPBTOA)); +} + +/****************************************************************************** + * End of function hw_usb_clear_hnpbtoa + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_vbout + * Description : Clear specified port's VBOUT-bit in the DVSTCTR register. + * : (To output a "Low" to pin VBOUT.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_vbout (usb_utr_t * ptr) +{ + #if USB_CFG_VBUS == USB_CFG_HIGH + ptr->ipp->DVSTCTR0 = (uint16_t) (ptr->ipp->DVSTCTR0 & (~USB_VBUSEN)); + #else /* USB_CFG_VBUS == USB_CFG_HIGH */ + ptr->ipp->DVSTCTR0 |= USB_VBUSEN; + #endif /* USB_CFG_VBUS == USB_CFG_HIGH */ +} + +/****************************************************************************** + * End of function hw_usb_clear_vbout + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if defined(USB_HIGH_SPEED_MODULE) + +/****************************************************************************** + * Function Name : hw_usb_set_utst + * Description : Not processed as the functionality is provided by R8A66597(ASSP). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_set_utst (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + FSP_PARAMETER_NOT_USED(data); + } + else + { + USB_M1->TESTMODE = data; + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp1->TESTMODE = data; + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_utst + ******************************************************************************/ +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + +#if defined(USB_HIGH_SPEED_MODULE) + +/****************************************************************************** + * Function Name : hw_usb_read_fifo32 + * Description : Data is read from the specified pipemode's FIFO register, 32-bits + * : wide, corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : CFIFO/D0FIFO/D1FIFO content (32-bit) + ******************************************************************************/ +uint32_t hw_usb_read_fifo32 (usb_utr_t * ptr, uint16_t pipemode) +{ + uint32_t data = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + switch (pipemode) + { + case USB_CUSE: + { + if (USB_CFG_IP1 == ptr->ip) + { + data = USB_M1->CFIFO; + } + else + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE2); + } + + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE2); + break; + } + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + switch (pipemode) + { + case USB_CUSE: + { + data = ptr->ipp1->CFIFO; + break; + } + + case USB_D0USE: + { + data = ptr->ipp1->D0FIFO; + break; + } + + case USB_D1USE: + { + data = ptr->ipp1->D1FIFO; + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE2); + break; + } + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return data; +} + +/****************************************************************************** + * End of function hw_usb_read_fifo32 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_fifo32 + * Description : Data is written to the specified pipemode's FIFO register, 32-bits + * : wide, corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * : uint32_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_fifo32 (usb_utr_t * ptr, uint16_t pipemode, uint32_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + switch (pipemode) + { + case USB_CUSE: + { + if (USB_CFG_IP1 == ptr->ip) + { + R_USB_HS0->CFIFO = data; + } + else + { + FSP_PARAMETER_NOT_USED(data); + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE2); + } + + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE3); + break; + } + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + switch (pipemode) + { + case USB_CUSE: + { + ptr->ipp1->CFIFO = data; + break; + } + + case USB_D0USE: + { + ptr->ipp1->D0FIFO = data; + break; + } + + case USB_D1USE: + { + ptr->ipp1->D1FIFO = data; + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE3); + break; + } + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_fifo32 + ******************************************************************************/ +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + +/****************************************************************************** + * Function Name : hw_usb_read_fifo16 + * Description : Data is read from the specified pipemode's FIFO register, 16-bits + * : wide, corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : CFIFO/D0FIFO/D1FIFO content (16-bit) + ******************************************************************************/ +uint16_t hw_usb_read_fifo16 (usb_utr_t * ptr, uint16_t pipemode) +{ + uint16_t data = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + switch (pipemode) + { + case USB_CUSE: + { + if (USB_IP1 == ptr->ip) + { + data = USB_M1->CFIFOH; + } + else + { + data = USB_M0->CFIFOL; + } + + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE5); + break; + } + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP0 == ptr->ip) + { + switch (pipemode) + { + case USB_CUSE: + { + data = ptr->ipp->CFIFOL; + break; + } + + case USB_D0USE: + { + data = ptr->ipp->D0FIFOL; + break; + } + + case USB_D1USE: + { + data = ptr->ipp->D1FIFOL; + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE4); + break; + } + } + } + + #if USB_NUM_USBIP == 2 + else if (USB_IP1 == ptr->ip) + { + switch (pipemode) + { + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + case USB_CUSE: + { + #if defined(USB_HIGH_SPEED_MODULE) + data = ptr->ipp1->CFIFOH; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + data = (uint16_t) ptr->ipp1->CFIFO; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + case USB_D0USE: + { + #if defined(USB_HIGH_SPEED_MODULE) + data = ptr->ipp1->D0FIFOH; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + data = (uint16_t) ptr->ipp1->D0FIFO; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + case USB_D1USE: + { + #if defined(USB_HIGH_SPEED_MODULE) + data = ptr->ipp1->D1FIFOH; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + data = (uint16_t) ptr->ipp1->D1FIFO; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + #else /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + case USB_CUSE: + { + #if defined(USB_HIGH_SPEED_MODULE) + data = ptr->ipp1->CFIFOL; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + data = (uint16_t) ptr->ipp1->CFIFO; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + case USB_D0USE: + { + #if defined(USB_HIGH_SPEED_MODULE) + data = ptr->ipp1->D0FIFOL; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + data = (uint16_t) ptr->ipp1->D0FIFO; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + case USB_D1USE: + { + #if defined(USB_HIGH_SPEED_MODULE) + data = ptr->ipp1->D1FIFOL; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + data = (uint16_t) ptr->ipp1->D1FIFO; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE5); + break; + } + } + } + #endif /* USB_NUM_USBIP == 2 */ + else + { + /* None */ + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return data; +} + +/****************************************************************************** + * End of function hw_usb_read_fifo16 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_fifo16 + * Description : Data is written to the specified pipemode's FIFO register, 16-bits + * : wide, corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_fifo16 (usb_utr_t * ptr, uint16_t pipemode, uint16_t data) +{ + uint16_t ip = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + ip = USB_IP1; + } + else + { + ip = USB_IP0; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ip = ptr->ip; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + if (USB_IP0 == ip) + { + switch (pipemode) + { + case USB_CUSE: + { + USB0_CFIFO16 = data; + break; + } + + case USB_D0USE: + { + USB0_D0FIFO16 = data; + break; + } + + case USB_D1USE: + { + USB0_D1FIFO16 = data; + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE6); + break; + } + } + } + +#if USB_NUM_USBIP == 2 + else if (USB_IP1 == ip) + { + switch (pipemode) + { + case USB_CUSE: + { + USB1_CFIFO16 = data; + break; + } + + case USB_D0USE: + { + USB1_D0FIFO16 = data; + break; + } + + case USB_D1USE: + { + USB1_D1FIFO16 = data; + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE7); + break; + } + } + } +#endif /* USB_NUM_USBIP == 2 */ + else + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE8); + } +} + +/****************************************************************************** + * End of function hw_usb_write_fifo16 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_fifo8 + * Description : Data is written to the specified pipemode's FIFO register, 8-bits + * : wide, corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * : uint8_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_fifo8 (usb_utr_t * ptr, uint16_t pipemode, uint8_t data) +{ + uint16_t ip = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + ip = USB_IP1; + } + else + { + ip = USB_IP0; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ip = ptr->ip; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + if (USB_IP0 == ip) + { + switch (pipemode) + { + case USB_CUSE: + { + USB0_CFIFO8 = data; + break; + } + + case USB_D0USE: + { + USB0_D0FIFO8 = data; + break; + } + + case USB_D1USE: + { + USB0_D1FIFO8 = data; + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE9); + break; + } + } + } + +#if USB_NUM_USBIP == 2 + else if (USB_IP1 == ip) + { + switch (pipemode) + { + case USB_CUSE: + { + USB1_CFIFO8 = data; + break; + } + + case USB_D0USE: + { + USB1_D0FIFO8 = data; + break; + } + + case USB_D1USE: + { + USB1_D1FIFO8 = data; + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE10); + break; + } + } + } +#endif /* USB_NUM_USBIP == 2 */ + else + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE11); + } +} + +/****************************************************************************** + * End of function hw_usb_write_fifo8 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_get_fifosel_adr + * Description : Returns the *address* of the FIFOSEL register corresponding to + * : specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : none + ******************************************************************************/ +static void * hw_usb_get_fifosel_adr (usb_utr_t * ptr, uint16_t pipemode) +{ + void * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + switch (pipemode) + { + case USB_CUSE: + { + if (USB_CFG_IP1 == ptr->ip) + { + p_reg = (void *) &(USB_M1->CFIFOSEL); + } + else + { + p_reg = (void *) &(USB_M0->CFIFOSEL); + } + + break; + } + + case USB_D0USE: + { + if (USB_CFG_IP1 == ptr->ip) + { + p_reg = (void *) &(USB_M1->D0FIFOSEL); + } + else + { + p_reg = (void *) &(USB_M0->D0FIFOSEL); + } + + break; + } + + case USB_D1USE: + { + if (USB_CFG_IP1 == ptr->ip) + { + p_reg = (void *) &(USB_M1->D1FIFOSEL); + } + else + { + p_reg = (void *) &(USB_M0->D1FIFOSEL); + } + + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE12); + break; + } + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + switch (pipemode) + { + case USB_CUSE: + { + p_reg = (void *) &(ptr->ipp->CFIFOSEL); + break; + } + + case USB_D0USE: + { + p_reg = (void *) &(ptr->ipp->D0FIFOSEL); + break; + } + + case USB_D1USE: + { + p_reg = (void *) &(ptr->ipp->D1FIFOSEL); + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE12); + break; + } + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return p_reg; +} + +/****************************************************************************** + * End of function hw_usb_get_fifosel_adr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_fifosel + * Description : Returns the value of the specified pipemode's FIFOSEL register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : FIFOSEL content + ******************************************************************************/ +uint16_t hw_usb_read_fifosel (usb_utr_t * ptr, uint16_t pipemode) +{ + volatile uint16_t * p_reg = 0; + + p_reg = (uint16_t *) hw_usb_get_fifosel_adr(ptr, pipemode); + + return *p_reg; +} + +/****************************************************************************** + * End of function hw_usb_read_fifosel + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_rmw_fifosel + * Description : Data is written to the specified pipemode's FIFOSEL register + * : (the FIFOSEL corresponding to the specified PIPEMODE), using + * : read-modify-write. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * : uint16_t data : Setting value + * : uint16_t bitptn : bitptn: Bit pattern to read-modify-write. + * Return value : none + ******************************************************************************/ +void hw_usb_rmw_fifosel (usb_utr_t * ptr, uint16_t pipemode, uint16_t data, uint16_t bitptn) +{ + uint16_t buf; + volatile uint16_t * p_reg = 0; + + p_reg = (uint16_t *) hw_usb_get_fifosel_adr(ptr, pipemode); + + buf = *p_reg; + buf = (uint16_t) (buf & (~bitptn)); + buf |= (data & bitptn); + *p_reg = buf; +} + +/****************************************************************************** + * End of function hw_usb_rmw_fifosel + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_dclrm + * Description : Set DCLRM-bits (FIFO buffer auto clear) of the FIFOSEL cor- + * : responding to specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : none + ******************************************************************************/ +void hw_usb_set_dclrm (usb_utr_t * ptr, uint16_t pipemode) +{ + volatile uint16_t * p_reg = 0; + + p_reg = (uint16_t *) hw_usb_get_fifosel_adr(ptr, pipemode); + + (*p_reg) |= USB_DCLRM; +} + +/****************************************************************************** + * End of function hw_usb_set_dclrm + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_dclrm + * Description : Reset DCLRM-bits (FIFO buffer not auto-cleared) of the FIFOSEL + * : corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : none + ******************************************************************************/ +void hw_usb_clear_dclrm (usb_utr_t * ptr, uint16_t pipemode) +{ + volatile uint16_t * p_reg = 0; + + p_reg = hw_usb_get_fifosel_adr(ptr, pipemode); + + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_DCLRM)); +} + +/****************************************************************************** + * End of function hw_usb_clear_dclrm + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_dreqe + * Description : Set DREQE-bits (to output signal DxREQ_Na) of the FIFOSEL cor- + * : responding to specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : none + ******************************************************************************/ +void hw_usb_set_dreqe (usb_utr_t * ptr, uint16_t pipemode) +{ + volatile uint16_t * p_reg = 0; + + p_reg = hw_usb_get_fifosel_adr(ptr, pipemode); + + if (true == usb_check_use_usba_module(ptr)) + { + (*p_reg) = (uint16_t) ((*p_reg) & (uint16_t) (~(USB_DREQE | USB_CURPIPE))); + + /* WAIT_LOOP */ + while (0 != ((*p_reg) & USB_CURPIPE)) + { + /* Wait Clear CURPIPE */ + } + } + else + { + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_DREQE)); + } + + (*p_reg) |= USB_DREQE; +} + +/****************************************************************************** + * End of function hw_usb_set_dreqe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_dreqe + * Description : Clear DREQE-bits (To prohibit the output of the signal DxREQ_N) + * : of the FIFOSEL corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : none + ******************************************************************************/ +void hw_usb_clear_dreqe (usb_utr_t * ptr, uint16_t pipemode) +{ + volatile uint16_t * p_reg = 0; + + p_reg = hw_usb_get_fifosel_adr(ptr, pipemode); + + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_DREQE)); +} + +/****************************************************************************** + * End of function hw_usb_clear_dreqe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_mbw + * Description : Set MBW-bits (CFIFO Port Access Bit Width) of the FIFOSEL cor- + * : responding to the specified PIPEMODE, to select 8 or 16-bit + * : wide FIFO port access. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * : uint16_t data : Setting value + * : (data = 0x0400), 32 bit (data = 0x0800) access mode. + * Return value : none + ******************************************************************************/ +void hw_usb_set_mbw (usb_utr_t * ptr, uint16_t pipemode, uint16_t data) +{ + volatile uint16_t * p_reg = 0; + + p_reg = hw_usb_get_fifosel_adr(ptr, pipemode); + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_MBW)); + if (0 != data) + { + (*p_reg) |= data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP0 == ptr->ip) + { + if (0 != data) + { + (*p_reg) |= USB_MBW_16; + } + else + { + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_MBW_16)); + } + } + else if (USB_IP1 == ptr->ip) + { + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_MBW)); + + if (0 != data) + { + (*p_reg) |= data; + } + } + else + { + /* None */ + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_mbw + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_curpipe + * Description : Set pipe to the number given; in the FIFOSEL corresponding + * : to specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * : uint16_t pipeno : Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_set_curpipe (usb_utr_t * ptr, uint16_t pipemode, uint16_t pipeno) +{ + volatile uint16_t * p_reg = 0; + volatile uint16_t reg; + + p_reg = hw_usb_get_fifosel_adr(ptr, pipemode); + reg = *p_reg; + + if ((USB_D0USE == pipemode) || (USB_D1USE == pipemode)) + { + if (false == usb_check_use_usba_module(ptr)) + { + reg = (uint16_t) (reg & (~USB_DREQE)); + } + } + + reg = (uint16_t) (reg & (~USB_CURPIPE)); + *p_reg = reg; + + /* WAIT_LOOP */ + while (0 != ((*p_reg) & USB_CURPIPE)) + { + /* Wait Clear CURPIPE */ + } + + reg |= pipeno; + + *p_reg = reg; +} + +/****************************************************************************** + * End of function hw_usb_set_curpipe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_get_fifoctr_adr + * Description : Returns the *address* of the FIFOCTR register corresponding to + * : specified PIPEMODE. + * : (FIFO Port Control Register.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : none + ******************************************************************************/ +static void * hw_usb_get_fifoctr_adr (usb_utr_t * ptr, uint16_t pipemode) +{ + void * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + switch (pipemode) + { + case USB_CUSE: + { + if (USB_CFG_IP1 == ptr->ip) + { + p_reg = (void *) &(USB_M1->CFIFOCTR); + } + else + { + p_reg = (void *) &(USB_M0->CFIFOCTR); + } + + break; + } + + case USB_D0USE: + { + if (USB_CFG_IP1 == ptr->ip) + { + p_reg = (void *) &(USB_M1->D0FIFOCTR); + } + else + { + p_reg = (void *) &(USB_M0->D0FIFOCTR); + } + + break; + } + + case USB_D1USE: + { + if (USB_CFG_IP1 == ptr->ip) + { + p_reg = (void *) &(USB_M1->D1FIFOCTR); + } + else + { + p_reg = (void *) &(USB_M0->D1FIFOCTR); + } + + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE13); + break; + } + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + switch (pipemode) + { + case USB_CUSE: + { + p_reg = (void *) &(ptr->ipp->CFIFOCTR); + break; + } + + case USB_D0USE: + { + p_reg = (void *) &(ptr->ipp->D0FIFOCTR); + break; + } + + case USB_D1USE: + { + p_reg = (void *) &(ptr->ipp->D1FIFOCTR); + break; + } + + default: + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE13); + break; + } + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return p_reg; +} + +/****************************************************************************** + * End of function hw_usb_get_fifoctr_adr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_fifoctr + * Description : Returns the value of the FIFOCTR register corresponding to + * : specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : FIFOCTR content + ******************************************************************************/ +uint16_t hw_usb_read_fifoctr (usb_utr_t * ptr, uint16_t pipemode) +{ + volatile uint16_t * p_reg = 0; + + p_reg = (uint16_t *) hw_usb_get_fifoctr_adr(ptr, pipemode); + + return *p_reg; +} + +/****************************************************************************** + * End of function hw_usb_read_fifoctr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_bval + * Description : Set BVAL (Buffer Memory Valid Flag) to the number given; in + * : the FIFOCTR corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : none + ******************************************************************************/ +void hw_usb_set_bval (usb_utr_t * ptr, uint16_t pipemode) +{ + volatile uint16_t * p_reg = 0; + + p_reg = (uint16_t *) hw_usb_get_fifoctr_adr(ptr, pipemode); + + (*p_reg) |= USB_BVAL; +} + +/****************************************************************************** + * End of function hw_usb_set_bval + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_bclr + * Description : Set BCLR (CPU Buffer Clear) to the number given; in the + * : FIFOCTR corresponding to the specified PIPEMODE. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipemode : CUSE/D0DMA/D1DMA + * Return value : none + ******************************************************************************/ +void hw_usb_set_bclr (usb_utr_t * ptr, uint16_t pipemode) +{ + volatile uint16_t * p_reg = 0; + + p_reg = (uint16_t *) hw_usb_get_fifoctr_adr(ptr, pipemode); + + *p_reg = USB_BCLR; +} + +/****************************************************************************** + * End of function hw_usb_set_bclr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_intenb + * Description : Data is written to INTENB register, + * : enabling/disabling the various USB interrupts. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : The value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_write_intenb (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->INTENB0 = data; + } + else + { + USB_M1->INTENB0 = data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->INTENB0 = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_intenb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_intenb + * Description : Bit(s) to be set in INTENB register, + * : enabling the respective USB interrupt(s). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Bit pattern: Respective interrupts with '1' + * : will be enabled. + * Return value : none + ******************************************************************************/ +void hw_usb_set_intenb (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->INTENB0 |= data; + } + else + { + USB_M1->INTENB0 |= data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->INTENB0 |= data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_intenb + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_clear_enb_vbse + * Description : Clear the VBE-bit of INTENB register, + * : to prohibit VBUS interrupts. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_enb_vbse (usb_utr_t * ptr) +{ + ptr->ipp->INTENB0 = (uint16_t) (ptr->ipp->INTENB0 & (~USB_VBSE)); +} + +/****************************************************************************** + * End of function hw_usb_clear_enb_vbse + ******************************************************************************/ + +/****************************************************************************** + * Description : Clear the SOFE-bit of INTENB register, + * : to prohibit Frame Number Update interrupts. + * Function Name : hw_usb_clear_enb_sofe + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_enb_sofe (usb_utr_t * ptr) +{ + ptr->ipp->INTENB0 = (uint16_t) (ptr->ipp->INTENB0 & (~USB_SOFE)); +} + +/****************************************************************************** + * End of function hw_usb_clear_enb_sofe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_brdyenb + * Description : Data is written to BRDYENB register, + * : enabling/disabling each respective pipe's BRDY interrupt. + * : (The BRDY interrupt indicates that a FIFO port is accessible.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_brdyenb (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->BRDYENB = data; +} + +/****************************************************************************** + * End of function hw_usb_write_brdyenb + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_set_brdyenb + * Description : A bit is set in the specified pipe's BRDYENB, enabling the + * : respective pipe BRDY interrupt(s). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_set_brdyenb (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->BRDYENB = (uint16_t) (USB_M0->BRDYENB | (1 << pipeno)); + } + else + { + USB_M1->BRDYENB = (uint16_t) (USB_M1->BRDYENB | (1 << pipeno)); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->BRDYENB = (uint16_t) (ptr->ipp->BRDYENB | (1 << pipeno)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_brdyenb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_brdyenb + * Description : Clear the PIPExBRDYE-bit of the specified pipe to prohibit + * : BRDY interrupts of that pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_brdyenb (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->BRDYENB = (uint16_t) (USB_M0->BRDYENB & (~(1 << pipeno))); + } + else + { + USB_M1->BRDYENB = (uint16_t) (USB_M1->BRDYENB & (~(1 << pipeno))); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->BRDYENB = (uint16_t) (ptr->ipp->BRDYENB & (~(1 << pipeno))); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_brdyenb + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_write_nrdyenb + * Description : Data is written to NRDYENB register, + * : enabling/disabling each respective pipe's NRDY interrupt + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_nrdyenb (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->NRDYENB = data; +} + +/****************************************************************************** + * End of function hw_usb_write_nrdyenb + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_set_nrdyenb + * Description : A bit is set in the specified pipe's NRDYENB, enabling the + * : respective pipe NRDY interrupt(s). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_set_nrdyenb (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->NRDYENB = (uint16_t) (USB_M0->NRDYENB | (1 << pipeno)); + } + else + { + USB_M1->NRDYENB = (uint16_t) (USB_M1->NRDYENB | (1 << pipeno)); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->NRDYENB = (uint16_t) (ptr->ipp->NRDYENB | (1 << pipeno)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_nrdyenb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_nrdyenb + * Description : Clear the PIPExNRDYE-bit of the specified pipe to prohibit + * : NRDY interrupts of that pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_nrdyenb (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->NRDYENB = (uint16_t) (USB_M0->NRDYENB & (~(1 << pipeno))); + } + else + { + USB_M1->NRDYENB = (uint16_t) (USB_M1->NRDYENB & (~(1 << pipeno))); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->NRDYENB = (uint16_t) (ptr->ipp->NRDYENB & (~(1 << pipeno))); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_nrdyenb + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_write_bempenb + * Description : Data is written to BEMPENB register, + * : enabling/disabling each respective pipe's BEMP interrupt. + * : (The BEMP interrupt indicates that the USB buffer is empty, + * : and so the FIFO can now be written to.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : The value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_write_bempenb (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->BEMPENB = data; +} + +/****************************************************************************** + * End of function hw_usb_write_bempenb + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_set_bempenb + * Description : A bit is set in the specified pipe's BEMPENB enabling the + * : respective pipe's BEMP interrupt(s). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_set_bempenb (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + g_usb_cstd_bemp_skip[USB_IP0][pipeno] = USB_OFF; + USB_M0->BEMPENB = (uint16_t) (USB_M0->BEMPENB | (1 << pipeno)); + } + + #if USB_NUM_USBIP == 2 + else + { + g_usb_cstd_bemp_skip[USB_IP1][pipeno] = USB_OFF; + USB_M1->BEMPENB = (uint16_t) (USB_M1->BEMPENB | (1 << pipeno)); + } + #endif /* USB_NUM_USBIP == 2 */ +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + g_usb_cstd_bemp_skip[ptr->ip][pipeno] = USB_OFF; + ptr->ipp->BEMPENB = (uint16_t) (ptr->ipp->BEMPENB | (1 << pipeno)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_bempenb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_bempenb + * Description : Clear the PIPExBEMPE-bit of the specified pipe to prohibit + * : BEMP interrupts of that pipe. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_bempenb (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->BEMPENB = (uint16_t) (USB_M0->BEMPENB & (~(1 << pipeno))); + } + else + { + USB_M1->BEMPENB = (uint16_t) (USB_M1->BEMPENB & (~(1 << pipeno))); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->BEMPENB = (uint16_t) (ptr->ipp->BEMPENB & (~(1 << pipeno))); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_bempenb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_sofcfg + * Description : Set Bit pattern for SOFCFG + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : The value to OR. + * Return value : none + ******************************************************************************/ +void hw_usb_set_sofcfg (usb_utr_t * ptr, uint16_t data) +{ + FSP_PARAMETER_NOT_USED(data); + FSP_PARAMETER_NOT_USED(*ptr); + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if USB_NUM_USBIP == 2 + if (USB_IP1 == ptr->ip) + { + ptr->ipp1->SOFCFG |= data; + } + #endif /* USB_NUM_USBIP == 2 */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_sofcfg + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (USB_UT_MODE == 0) + +/****************************************************************************** + * Function Name : hw_usb_read_intsts + * Description : Returns INTSTS0 register content. + * Arguments : none + * Return value : INTSTS0 content + ******************************************************************************/ +uint16_t hw_usb_read_intsts (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + return USB_M0->INTSTS0; + } + else + { + return USB_M1->INTSTS0; + } +} + +/****************************************************************************** + * End of function hw_usb_read_intsts + ******************************************************************************/ + #endif /* #if (USB_UT_MODE == 0) */ +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * Function Name : hw_usb_write_intsts + * Description : Data is written to INTSTS0 register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : The value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_write_intsts (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->INTSTS0 = data; + } + else + { + USB_M1->INTSTS0 = data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->INTSTS0 = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_intsts + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_clear_sts_sofr + * Description : Clear the SOFR-bit (Frame Number Refresh Interrupt Status) of + * : the clear SOF interrupt status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_sts_sofr (usb_utr_t * ptr) +{ + ptr->ipp->INTSTS0 = (uint16_t) ~USB_SOFR; +} + +/****************************************************************************** + * End of function hw_usb_clear_sts_sofr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_brdysts + * Description : Returns BRDYSTS register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : BRDYSTS content + ******************************************************************************/ +uint16_t hw_usb_read_brdysts (usb_utr_t * ptr) +{ + return ptr->ipp->BRDYSTS; +} + +/****************************************************************************** + * End of function hw_usb_read_brdysts + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_brdysts + * Description : Data is written to BRDYSTS register, to set the BRDY interrupt status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : The value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_write_brdysts (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->BRDYSTS = data; +} /* End of function hw_usb_write_brdysts() */ + +/****************************************************************************** + * End of function hw_usb_write_brdysts + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_clear_sts_brdy + * Description : Clear the PIPExBRDY status bit of the specified pipe to clear + * : its BRDY interrupt status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno: Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_sts_brdy (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->BRDYSTS = (uint16_t) (~(1 << pipeno)) & BRDYSTS_MASK; + } + else + { + USB_M1->BRDYSTS = (uint16_t) (~(1 << pipeno)) & BRDYSTS_MASK; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->BRDYSTS = (uint16_t) (~(1 << pipeno)) & BRDYSTS_MASK; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_sts_brdy + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_write_nrdy_sts + * Description : Data is written to NRDYSTS register, to + * : set the NRDY interrupt status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : The value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_write_nrdy_sts (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->NRDYSTS = data; +} + +/****************************************************************************** + * End of function hw_usb_clear_status_nrdy + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_clear_status_nrdy + * Description : Clear the PIPExNRDY status bit of the specified pipe to clear + * : its NRDY interrupt status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno: Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_status_nrdy (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->NRDYSTS = (uint16_t) ((uint16_t) (~(1 << pipeno)) & NRDYSTS_MASK); + } + else + { + USB_M1->NRDYSTS = (uint16_t) ((uint16_t) (~(1 << pipeno)) & NRDYSTS_MASK); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->NRDYSTS = (uint16_t) (~(1 << pipeno)) & NRDYSTS_MASK; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_status_nrdy + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_write_bempsts + * Description : Data is written to BEMPSTS register, to set the BEMP interrupt status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_bempsts (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->BEMPSTS = data; +} + +/****************************************************************************** + * End of function hw_usb_write_bempsts + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_clear_status_bemp + * Description : Clear the PIPExBEMP status bit of the specified pipe to clear + * : its BEMP interrupt status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno: Pipe number. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_status_bemp (usb_utr_t * ptr, uint16_t pipeno) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->BEMPSTS = (uint16_t) ((uint16_t) (~(1 << pipeno)) & BEMPSTS_MASK); + } + else + { + USB_M1->BEMPSTS = (uint16_t) ((uint16_t) (~(1 << pipeno)) & BEMPSTS_MASK); + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->BEMPSTS = (uint16_t) (~(1 << pipeno)) & BEMPSTS_MASK; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_status_bemp + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_frmnum + * Description : Returns FRMNUM register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : FRMNUM content + ******************************************************************************/ +uint16_t hw_usb_read_frmnum (usb_utr_t * ptr) +{ + uint16_t result = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + result = USB_M0->FRMNUM; + } + else + { + result = USB_M1->FRMNUM; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + result = ptr->ipp->FRMNUM; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_frmnum + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Function Name : hw_usb_read_usbreq + * Description : Returns USBREQ register content. + * Arguments : none + * Return value : USBREQ content + ******************************************************************************/ +uint16_t hw_usb_read_usbreq (uint8_t usb_ip) +{ + uint16_t result = 0; + + if (USB_CFG_IP0 == usb_ip) + { + result = USB_M0->USBREQ; + } + else + { + result = USB_M1->USBREQ; + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_usbreq + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_usbval + * Description : Returns USBVAL register content. + * Arguments : none + * Return value : USBVAL content + ******************************************************************************/ +uint16_t hw_usb_read_usbval (uint8_t usb_ip) +{ + uint16_t result = 0; + + if (USB_CFG_IP0 == usb_ip) + { + result = USB_M0->USBVAL; + } + else + { + result = USB_M1->USBVAL; + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_usbval + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_usbindx + * Description : Returns USBINDX register content. + * Arguments : none + * Return value : USBINDX content + ******************************************************************************/ +uint16_t hw_usb_read_usbindx (uint8_t usb_ip) +{ + uint16_t result = 0; + + if (USB_CFG_IP0 == usb_ip) + { + result = USB_M0->USBINDX; + } + else + { + result = USB_M1->USBINDX; + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_usbindx + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_usbleng + * Description : Returns USBLENG register content. + * Arguments : none + * Return value : USBLENG content + ******************************************************************************/ +uint16_t hw_usb_read_usbleng (uint8_t usb_ip) +{ + uint16_t result = 0; + + if (USB_CFG_IP0 == usb_ip) + { + result = USB_M0->USBLENG; + } + else + { + result = USB_M1->USBLENG; + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_usbleng + ******************************************************************************/ +#else + #if defined(USB_CFG_HUVC_USE) + +/****************************************************************************** + * Function Name : hw_usb_read_usbreq + * Description : Returns USBREQ register content. + * Arguments : none + * Return value : USBREQ content + ******************************************************************************/ +uint16_t hw_usb_read_usbreq (uint8_t usb_ip) +{ + uint16_t result = 0; + + if (USB_CFG_IP0 == usb_ip) + { + result = USB_M0->USBREQ; + } + else + { + result = USB_M1->USBREQ; + } + + return result; +} + + #endif +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * Function Name : hw_usb_read_dcpcfg + * Description : Returns DCPCFG register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : DCPCFG content + ******************************************************************************/ +uint16_t hw_usb_read_dcpcfg (usb_utr_t * ptr) +{ + uint16_t result = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + result = USB_M0->DCPCFG; + } + else + { + result = USB_M1->DCPCFG; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + result = ptr->ipp->DCPCFG; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_dcpcfg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_dcpcfg + * Description : Specified data is written to DCPCFG register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_dcpcfg (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->DCPCFG = data; + } + else + { + USB_M1->DCPCFG = data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->DCPCFG = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_dcpcfg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_dcpmaxp + * Description : Returns DCPMAXP register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : DCPMAXP content + ******************************************************************************/ +uint16_t hw_usb_read_dcpmaxp (usb_utr_t * ptr) +{ + uint16_t result = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + result = USB_M0->DCPMAXP; + } + else + { + result = USB_M1->DCPMAXP; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + result = ptr->ipp->DCPMAXP; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_dcpmaxp + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_dcpmxps + * Description : Specified data is written to DCPMAXP register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_dcpmxps (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->DCPMAXP = data; + } + else + { + USB_M1->DCPMAXP = data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->DCPMAXP = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_dcpmxps + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Function Name : hw_usb_read_dcpctr + * Description : Returns DCPCTR register content. + * Arguments : none + * Return value : DCPCTR content + ******************************************************************************/ +uint16_t hw_usb_read_dcpctr (uint8_t usb_ip) +{ + uint16_t result; + + if (USB_CFG_IP0 == usb_ip) + { + result = USB_M0->DCPCTR; + } + else + { + result = USB_M1->DCPCTR; + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_dcpctr + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * Function Name : hw_usb_write_pipesel + * Description : Specified data is written to PIPESEL register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : The value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_write_pipesel (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->PIPESEL = data; + } + else + { + USB_M1->PIPESEL = data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->PIPESEL = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_pipesel + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_pipecfg + * Description : Returns PIPECFG register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : PIPECFG content + ******************************************************************************/ +uint16_t hw_usb_read_pipecfg (usb_utr_t * ptr) +{ + uint16_t result = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + result = USB_M0->PIPECFG; + } + else + { + result = USB_M1->PIPECFG; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + result = ptr->ipp->PIPECFG; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_pipecfg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_pipecfg + * Description : Specified data is written to PIPECFG register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_pipecfg (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->PIPECFG = data; + } + else + { + USB_M1->PIPECFG = data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->PIPECFG = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_pipecfg + ******************************************************************************/ + +#if defined(USB_HIGH_SPEED_MODULE) + +/****************************************************************************** + * Function Name : hw_usb_write_pipebuf + * Description : Specified the value by 2nd argument is set to PIPEBUF register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_pipebuf (usb_utr_t * ptr, uint16_t data) +{ + FSP_PARAMETER_NOT_USED(data); + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + USB_M1->PIPEBUF = data; + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP1 == ptr->ip) + { + ptr->ipp1->PIPEBUF = data; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_pipebuf + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_pipebuf + * Description : Returns PIPECFG register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : PIPEBUF content + ******************************************************************************/ +uint16_t hw_usb_read_pipebuf (usb_utr_t * ptr) +{ + uint16_t result = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + result = 0; + } + else + { + result = USB_M1->PIPEBUF; + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP1 == ptr->ip) + { + result = ptr->ipp1->PIPEBUF; + } + else + { + result = 0; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_pipebuf + ******************************************************************************/ + +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + +/****************************************************************************** + * Function Name : hw_usb_read_pipemaxp + * Description : Returns PIPEMAXP register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : PIPEMAXP content + ******************************************************************************/ +uint16_t hw_usb_read_pipemaxp (usb_utr_t * ptr) +{ + uint16_t result = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + result = USB_M0->PIPEMAXP; + } + else + { + result = USB_M1->PIPEMAXP; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + result = ptr->ipp->PIPEMAXP; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_read_pipemaxp + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_pipemaxp + * Description : Specified data is written to PIPEMAXP register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_pipemaxp (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->PIPEMAXP = data; + } + else + { + USB_M1->PIPEMAXP = data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->PIPEMAXP = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_pipemaxp + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_pipeperi + * Description : Specified data is written to PIPEPERI register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_pipeperi (usb_utr_t * ptr, uint16_t data) +{ + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + USB_M0->PIPEPERI = data; + } + else + { + USB_M1->PIPEPERI = data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + ptr->ipp->PIPEPERI = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_pipeperi + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_read_pipectr + * Description : Returns DCPCTR or the specified pipe's PIPECTR register content. + * : The Pipe Control Register returned is determined by the speci- + * : fied pipe number. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number. + * Return value : PIPExCTR content + ******************************************************************************/ +uint16_t hw_usb_read_pipectr (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg; + volatile uint16_t reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + if (USB_PIPE0 == pipeno) + { + p_reg = (uint16_t *) &(USB_M0->DCPCTR); + } + else + { + p_reg = (uint16_t *) &(USB_M0->PIPE_CTR[0]) + (pipeno - 1); + } + + reg = *p_reg; + } + else + { + if (USB_PIPE0 == pipeno) + { + p_reg = (uint16_t *) &(USB_M1->DCPCTR); + } + else + { + p_reg = (uint16_t *) &(USB_M1->PIPE_CTR[0]) + (pipeno - 1); + } + + reg = *p_reg; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_PIPE0 == pipeno) + { + p_reg = (uint16_t *) &(ptr->ipp->DCPCTR); + } + else + { + p_reg = (uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1); + } + reg = *p_reg; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + + return reg; +} + +/****************************************************************************** + * End of function hw_usb_read_pipectr + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : hw_usb_write_pipectr + * Description : Specified data is written to the specified pipe's PIPEPERI register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_write_pipectr (usb_utr_t * ptr, uint16_t pipeno, uint16_t data) +{ + volatile uint16_t * p_reg; + + if (USB_PIPE0 == pipeno) + { + p_reg = (uint16_t *) &(ptr->ipp->DCPCTR); + } + else + { + p_reg = (uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1); + } + + *p_reg = data; +} + +/****************************************************************************** + * End of function hw_usb_write_pipectr + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Function Name : hw_usb_set_csclr + * Description : Set CSCLR bit in the specified pipe's PIPECTR register + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_set_csclr (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + p_reg = (uint16_t *) &(USB_M0->PIPE_CTR[0]) + (pipeno - 1); + } + else + { + p_reg = (uint16_t *) &(USB_M1->PIPE_CTR[0]) + (pipeno - 1); + } + (*p_reg) |= USB_CSCLR; +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_reg = (uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1); + (*p_reg) |= USB_CSCLR; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_csclr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_aclrm + * Description : The ACLRM-bit (Auto Buffer Clear Mode) is set in the specified + * : pipe's control register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_set_aclrm (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + p_reg = (uint16_t *) &(USB_M0->PIPE_CTR[0]) + (pipeno - 1); + (*p_reg) |= USB_ACLRM; + } + else + { + p_reg = (uint16_t *) &(USB_M1->PIPE_CTR[0]) + (pipeno - 1); + (*p_reg) |= USB_ACLRM; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_reg = (uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1); + (*p_reg) |= USB_ACLRM; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_aclrm + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_aclrm + * Description : Clear the ACLRM bit in the specified pipe's control register + * : to disable Auto Buffer Clear Mode. + * : its BEMP interrupt status. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_clear_aclrm (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + p_reg = (uint16_t *) &(USB_M0->PIPE_CTR[0]) + (pipeno - 1); + } + else + { + p_reg = (uint16_t *) &(USB_M1->PIPE_CTR[0]) + (pipeno - 1); + } + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_ACLRM)); +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_reg = (uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1); + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_ACLRM)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_aclrm + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_sqclr + * Description : The SQCLR-bit (Toggle Bit Clear) is set in the specified pipe's + * : control register. Setting SQSET to 1 makes DATA0 the expected + * : data in the pipe's next transfer. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_set_sqclr (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + if (USB_PIPE0 == pipeno) + { + USB_M0->DCPCTR |= USB_SQCLR; + } + else + { + p_reg = ((uint16_t *) &(USB_M0->PIPE_CTR[0]) + (pipeno - 1)); + (*p_reg) |= USB_SQCLR; + } + } + else + { + if (USB_PIPE0 == pipeno) + { + USB_M1->DCPCTR |= USB_SQCLR; + } + else + { + p_reg = ((uint16_t *) &(USB_M1->PIPE_CTR[0]) + (pipeno - 1)); + (*p_reg) |= USB_SQCLR; + } + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_PIPE0 == pipeno) + { + ptr->ipp->DCPCTR |= USB_SQCLR; + } + else + { + p_reg = ((uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1)); + (*p_reg) |= USB_SQCLR; + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_sqclr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_sqset + * Description : The SQSET-bit (Toggle Bit Set) is set in the specified pipe's + * : control register. Setting SQSET to 1 makes DATA1 the expected + * : data in the next transfer. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_set_sqset (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + if (USB_PIPE0 == pipeno) + { + USB_M0->DCPCTR |= USB_SQSET; + } + else + { + p_reg = ((uint16_t *) &(USB_M0->PIPE_CTR[0]) + (pipeno - 1)); + (*p_reg) |= USB_SQSET; + } + } + else + { + if (USB_PIPE0 == pipeno) + { + USB_M1->DCPCTR |= USB_SQSET; + } + else + { + p_reg = ((uint16_t *) &(USB_M1->PIPE_CTR[0]) + (pipeno - 1)); + (*p_reg) |= USB_SQSET; + } + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_PIPE0 == pipeno) + { + ptr->ipp->DCPCTR |= USB_SQSET; + } + else + { + p_reg = ((uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1)); + (*p_reg) |= USB_SQSET; + } +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_sqset + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_pid + * Description : Set the specified PID of the specified pipe's DCPCTR/PIPECTR + * : register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * : uint16_t data : NAK/BUF/STALL. + * Return value : none + ******************************************************************************/ +void hw_usb_set_pid (usb_utr_t * ptr, uint16_t pipeno, uint16_t data) +{ + volatile uint16_t * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + if (USB_PIPE0 == pipeno) + { + p_reg = ((uint16_t *) &(USB_M0->DCPCTR)); + } + else + { + p_reg = ((uint16_t *) &(USB_M0->PIPE_CTR[0]) + (pipeno - 1)); + } + + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_PID)); + (*p_reg) |= data; + } + else + { + if (USB_PIPE0 == pipeno) + { + p_reg = ((uint16_t *) &(USB_M1->DCPCTR)); + } + else + { + p_reg = ((uint16_t *) &(USB_M1->PIPE_CTR[0]) + (pipeno - 1)); + } + + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_PID)); + (*p_reg) |= data; + } +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_PIPE0 == pipeno) + { + p_reg = ((uint16_t *) &(ptr->ipp->DCPCTR)); + } + else + { + p_reg = ((uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1)); + } + + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_PID)); + (*p_reg) |= data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_pid + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_pid + * Description : Clear the specified PID-bits of the specified pipe's DCPCTR/ + * : PIPECTR register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * : uint16_t data : NAK/BUF/STALL - to be cleared. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_pid (usb_utr_t * ptr, uint16_t pipeno, uint16_t data) +{ + volatile uint16_t * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + if (USB_PIPE0 == pipeno) + { + p_reg = ((uint16_t *) &(USB_M0->DCPCTR)); + } + else + { + p_reg = ((uint16_t *) &(USB_M0->PIPE_CTR[0]) + (pipeno - 1)); + } + } + else + { + if (USB_PIPE0 == pipeno) + { + p_reg = ((uint16_t *) &(USB_M1->DCPCTR)); + } + else + { + p_reg = ((uint16_t *) &(USB_M1->PIPE_CTR[0]) + (pipeno - 1)); + } + } + (*p_reg) = (uint16_t) ((*p_reg) & (~data)); +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_PIPE0 == pipeno) + { + p_reg = ((uint16_t *) &(ptr->ipp->DCPCTR)); + } + else + { + p_reg = ((uint16_t *) &(ptr->ipp->PIPE_CTR[0]) + (pipeno - 1)); + } + (*p_reg) = (uint16_t) ((*p_reg) & (~data)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_pid + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_trenb + * Description : The TRENB-bit (Transaction Counter Enable) is set in the speci- + * : fied pipe's control register, to enable the counter. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_set_trenb (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + p_reg = (uint16_t *) &(USB_M0->PIPE_TR[0].E) + ((pipeno - 1) * 2); + } + else + { + p_reg = (uint16_t *) &(USB_M1->PIPE_TR[0].E) + ((pipeno - 1) * 2); + } + (*p_reg) |= USB_TRENB; +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_reg = (uint16_t *) &(ptr->ipp->PIPE_TR[0].E) + ((pipeno - 1) * 2); + (*p_reg) |= USB_TRENB; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_trenb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_trenb + * Description : The TRENB-bit (Transaction Counter Enable) is cleared in the + * : specified pipe's control register, to disable the counter. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_clear_trenb (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + p_reg = (uint16_t *) &(USB_M0->PIPE_TR[0].E) + ((pipeno - 1) * 2); + } + else + { + p_reg = (uint16_t *) &(USB_M1->PIPE_TR[0].E) + ((pipeno - 1) * 2); + } + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_TRENB)); +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_reg = (uint16_t *) &(ptr->ipp->PIPE_TR[0].E) + ((pipeno - 1) * 2); + (*p_reg) = (uint16_t) ((*p_reg) & (~USB_TRENB)); +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_trenb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_trclr + * Description : The TRENB-bit (Transaction Counter Clear) is set in the speci- + * : fied pipe's control register to clear the current counter + * : value. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * Return value : none + ******************************************************************************/ +void hw_usb_set_trclr (usb_utr_t * ptr, uint16_t pipeno) +{ + volatile uint16_t * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + p_reg = (uint16_t *) &(USB_M0->PIPE_TR[0].E) + ((pipeno - 1) * 2); + } + else + { + p_reg = (uint16_t *) &(USB_M1->PIPE_TR[0].E) + ((pipeno - 1) * 2); + } + (*p_reg) |= USB_TRCLR; +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_reg = (uint16_t *) &(ptr->ipp->PIPE_TR[0].E) + ((pipeno - 1) * 2); + (*p_reg) |= USB_TRCLR; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_trclr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_write_pipetrn + * Description : Specified data is written to the specified pipe's PIPETRN reg- + * : ister. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipeno : Pipe number + * : uint16_t data : The value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_write_pipetrn (usb_utr_t * ptr, uint16_t pipeno, uint16_t data) +{ + volatile uint16_t * p_reg = 0; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP0 == ptr->ip) + { + p_reg = (uint16_t *) &(USB_M0->PIPE_TR[0].N) + ((pipeno - 1) * 2); + } + else + { + p_reg = (uint16_t *) &(USB_M1->PIPE_TR[0].N) + ((pipeno - 1) * 2); + } + *p_reg = data; +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_reg = (uint16_t *) &(ptr->ipp->PIPE_TR[0].N) + ((pipeno - 1) * 2); + *p_reg = data; +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function hw_usb_write_pipetrn + ******************************************************************************/ + +#if USB_CFG_BC == USB_CFG_ENABLE + +/****************************************************************************** + * Function Name : hw_usb_read_bcctrl + * Description : Returns BCCTRL register content. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : BCCTRL content + ******************************************************************************/ +uint16_t hw_usb_read_bcctrl (usb_utr_t * ptr) +{ + uint16_t rtn_val = 0; + + FSP_PARAMETER_NOT_USED(*ptr); + #if defined(USB_HIGH_SPEED_MODULE) + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + if (USB_CFG_IP1 == ptr->ip) + { + return USB_M1->BCCTRL; + } + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + if (USB_IP1 == ptr->ip) + { + rtn_val = (uint16_t) ptr->ipp1->BCCTRL; + } + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + return rtn_val; +} /* End of function hw_usb_read_bcctrl() */ + +/****************************************************************************** + * End of function hw_usb_read_bcctrl + ******************************************************************************/ +#endif /* USB_CFG_BC == USB_CFG_ENABLE */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if USB_CFG_BC == USB_CFG_ENABLE + +/****************************************************************************** + * Function Name : hw_usb_set_vdmsrce + * Description : Set VDMSRCE bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_set_vdmsrce (usb_utr_t * ptr) +{ + if (USB_IP1 == ptr->ip) + { + #if defined(USB_HIGH_SPEED_MODULE) + ptr->ipp1->BCCTRL = (uint16_t) (ptr->ipp1->BCCTRL | (USB_VDMSRCE)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_vdmsrce + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_vdmsrce + * Description : Clear VDMSRCE bits. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_vdmsrce (usb_utr_t * ptr) +{ + if (USB_IP1 == ptr->ip) + { + #if defined(USB_HIGH_SPEED_MODULE) + ptr->ipp1->BCCTRL = (uint16_t) (ptr->ipp1->BCCTRL & (~USB_VDMSRCE)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_vdmsrce + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_set_idpsinke + * Description : Set IDPSINKE bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_set_idpsinke (usb_utr_t * ptr) +{ + if (USB_IP1 == ptr->ip) + { + #if defined(USB_HIGH_SPEED_MODULE) + ptr->ipp1->BCCTRL = (uint16_t) (ptr->ipp1->BCCTRL | (USB_IDPSINKE)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_idpsinke + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_idpsinke + * Description : Clear IDPSINKE bits. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_clear_idpsinke (usb_utr_t * ptr) +{ + if (USB_IP1 == ptr->ip) + { + #if defined(USB_HIGH_SPEED_MODULE) + ptr->ipp1->BCCTRL = (uint16_t) (ptr->ipp1->BCCTRL & (~USB_IDPSINKE)); + #endif /* vdefined (USB_HIGH_SPEED_MODULE) */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_idpsinke + ******************************************************************************/ + + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Function Name : hw_usb_set_suspendm + * Description : Set SUSPM bit. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_set_suspendm (uint8_t usb_ip) +{ + if (USB_CFG_IP1 == usb_ip) + { + #if defined(USB_HIGH_SPEED_MODULE) + USB_M1->LPSTS = (uint16_t) (USB_M1->LPSTS | (USB_SUSPENDM)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } +} + +/****************************************************************************** + * End of function hw_usb_set_suspendm + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_suspm + * Description : Clear SUSPM bit. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_clear_suspm (uint8_t usb_ip) +{ + if (USB_CFG_IP1 == usb_ip) + { + #if defined(USB_HIGH_SPEED_MODULE) + USB_M1->LPSTS = (uint16_t) (USB_M1->LPSTS & (~USB_SUSPENDM)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } +} + +/****************************************************************************** + * End of function hw_usb_clear_suspm + ******************************************************************************/ + +#endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + +#if (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) + +/****************************************************************************** + * Function Name : hw_usb_set_vdcen + * Description : Set VDCEN bit. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_set_vdcen (void) +{ + USB_M0->USBMC = (USB_M0->USBMC | USB_VDCEN); +} + +/****************************************************************************** + * End of function hw_usb_set_vdcen + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_vdcen + * Description : Clear VDCEN bit. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_clear_vdcen (void) +{ + USB_M0->USBMC = (uint16_t) (USB_M0->USBMC & (~USB_VDCEN)); +} + +/****************************************************************************** + * End of function hw_usb_clear_vdcen + ******************************************************************************/ + +#endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ + +#if defined(USB_SUPPORT_HOCO_MODULE) + +/****************************************************************************** + * Function Name : hw_usb_set_uckselc + * Description : Set UCKSELC bit in UCKSEL register. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_set_uckselc (void) +{ + USB_M0->UCKSEL |= USB_UCKSELC; +} + +/****************************************************************************** + * End of function hw_usb_set_uckselc + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_uckselc + * Description : Clear UCLKSELC bit in UCKSEL register. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_clear_uckselc (void) +{ + USB_M0->UCKSEL = (uint16_t) (USB_M0->UCKSEL & (~USB_UCKSELC)); +} + +/****************************************************************************** + * End of function hw_usb_clear_uckselc + ******************************************************************************/ + +#endif /* defined(USB_SUPPORT_HOCO_MODULE) */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c new file mode 100644 index 0000000000..41c4885e3b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c @@ -0,0 +1,1311 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/******************************************************************************* + * Includes , "Project Includes" + *******************************************************************************/ +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" + +#define ACTIVE_CNT_NUMBER (100) +#define DTC_PRV_OFFSET_IN_PROGRESS (15U) +#define USB_DMA_DIR_RD (0U) +#define USB_DMA_DIR_WR (1U) + +#if (USB_CFG_DMA == USB_CFG_ENABLE || USB_CFG_DTC == USB_CFG_ENABLE) + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + #include "r_dmac.h" + #elif (USB_CFG_DTC == USB_CFG_ENABLE) + #include "r_dtc.h" + #endif + + #include "inc/r_usb_dmac.h" + +/****************************************************************************** + * Exported global functions (to be accessed by other files) + ******************************************************************************/ + #if (BSP_CFG_RTOS == 0) +usb_dma_int_t gs_usb_cstd_dma_int; + #endif /* (BSP_CFG_RTOS == 0) */ + #if (BSP_CFG_RTOS != 0) +static usb_utr_t g_usb_cstd_int_dma[USB_INT_BUFSIZE]; + #endif /* #if (BSP_CFG_RTOS != 0)*/ + +usb_utr_t * get_usb_int_buf_dma(void); + +uint32_t g_usb_cstd_dma_size[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 buffer size */ +uint16_t g_usb_cstd_dma_fifo[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 FIFO buffer size */ +uint16_t g_usb_cstd_dma_pipe[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 pipe number */ + +uint8_t g_usb_cstd_dma_ch[USB_NUM_USBIP][USB_FIFO_ACCESS_NUM_MAX]; /* DMA ch no. table */ + +uint8_t g_usb_cstd_dma_fraction_size[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* fraction size(1-3) */ +uint32_t g_usb_cstd_dma_fraction_adr[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* fraction data address */ +uint32_t g_fifo_address[USB_NUM_USBIP][USB_FIFO_ACCESS_NUM_MAX][USB_FIFO_ACCSESS_TYPE_NUM] = +{ + { + /* IP0 */ + /* 32bit 16bit 8bit */ + {(uint32_t) 0, (uint32_t) &USB_M0->CFIFOL, + (uint32_t) &USB_M0->CFIFOLL}, /* USB0 CFIFO address */ + {(uint32_t) 0, (uint32_t) &USB_M0->D0FIFOL, + (uint32_t) &USB_M0->D0FIFOLL}, /* USB0 D0FIFO address */ + {(uint32_t) 0, (uint32_t) &USB_M0->D1FIFOL, + (uint32_t) &USB_M0->D1FIFOLL}, + }, + #if USB_NUM_USBIP == 2 + { + /* IP1 */ + + #if defined(USB_HIGH_SPEED_MODULE) + + /* Little */ + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + {(uint32_t) &USB_M1->CFIFO, (uint32_t) &USB_M1->CFIFOH, + (uint32_t) &USB_M1->CFIFOHH}, /* USBA CFIFO adr Little */ + {(uint32_t) &USB_M1->D0FIFO, (uint32_t) &USB_M1->D0FIFOH, + (uint32_t) &USB_M1->D0FIFOHH}, /* USBA D0FIFO adr Little */ + {(uint32_t) &USB_M1->D1FIFO, (uint32_t) &USB_M1->D1FIFOH, + (uint32_t) &USB_M1->D1FIFOHH} /* USBA D1FIFO adr Little */ + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + + /* Big */ + #if USB_CFG_ENDIAN == USB_CFG_BIG + {(uint32_t) &USB_M1->CFIFO, (uint32_t) &USB_M1->CFIFOL, + (uint32_t) &USB_M1->CFIFOLL}, /* USBA CFIFO adr Big */ + {(uint32_t) &USB_M1->D0FIFO, (uint32_t) &USB_M1->D0FIFOL, + (uint32_t) &USB_M1->D0FIFOLL}, /* USBA D0FIFO adr Big */ + {(uint32_t) &USB_M1->D1FIFO, (uint32_t) &USB_M1->D1FIFOL, + (uint32_t) &USB_M1->D1FIFOLL} /* USBA D1FIFO adr Big */ + #endif /* USB_CFG_ENDIAN == USB_CFG_BIG */ + #else /* defined (USB_HIGH_SPEED_MODULE) */ + {(uint32_t) 0, (uint32_t) &USB_M1->CFIFOL, + (uint32_t) &USB_M1->CFIFOLL}, /* USB0 CFIFO address */ + {(uint32_t) 0, (uint32_t) &USB_M1->D0FIFOL, + (uint32_t) &USB_M1->D0FIFOLL}, /* USB0 D0FIFO address */ + {(uint32_t) 0, (uint32_t) &USB_M1->D1FIFOL, + (uint32_t) &USB_M1->D1FIFOLL}, + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + #endif /* USB_NUM_USBIP == 2 */ +}; + +/****************************************************************************** + * Function Name : usb_cstd_dma_send_start + * Description : Start transfer using DMA. If transfer size is 0, write + * : more data to buffer. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t pipe : Pipe number + * : uint16_t useport: FIFO select + * Return value : none + ******************************************************************************/ +void usb_cstd_dma_send_start (usb_utr_t * ptr, uint16_t pipe, uint16_t useport) +{ + uint32_t dma_size; + uint8_t * p_data_ptr = 0; + uint16_t ip; + uint16_t ch; + + ip = ptr->ip; + + if (USB_MODE_HOST == g_usb_usbmode[ip]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_data_ptr = gp_usb_hstd_data_ptr[ptr->ip][pipe]; + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + p_data_ptr = gp_usb_pstd_data[pipe]; + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + + ch = usb_cstd_dma_ref_ch_no(ptr, useport); + + dma_size = g_usb_cstd_dma_size[ip][ch]; + + if (USB_IP0 == ip) + { + dma_size &= ~USB_BIT_MBW16; + } + else + { + #if defined(USB_HIGH_SPEED_MODULE) + dma_size &= ~USB_BIT_MBW32; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + dma_size &= ~USB_BIT_MBW16; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + + if (0U != dma_size) + { + hw_usb_clear_dreqe(ptr, useport); /* DMA Transfer request disable */ + + usb_cstd_dma_clear_ir(ptr, useport); + + if (dma_size >= g_usb_cstd_dma_fifo[ip][ch]) + { + /* Fifo size block transfer */ + dma_size = (dma_size - (dma_size % g_usb_cstd_dma_fifo[ip][ch])); + } + else + { + if (USB_IP0 == ip) + { + /* fraction size(1-3) */ + g_usb_cstd_dma_fraction_size[ip][ch] = g_usb_cstd_dma_size[ip][ch] & USB_BIT_MBW16; + } + + #if USB_NUM_USBIP == 2 + else + { + #if defined(USB_HIGH_SPEED_MODULE) + + /* fraction size(1-3) */ + g_usb_cstd_dma_fraction_size[ip][ch] = g_usb_cstd_dma_size[ip][ch] & USB_BIT_MBW32; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + /* fraction size(1-3) */ + g_usb_cstd_dma_fraction_size[ip][ch] = g_usb_cstd_dma_size[ip][ch] & USB_BIT_MBW16; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + #endif /* USB_NUM_USBIP == 2 */ + + g_usb_cstd_dma_fraction_adr[ip][ch] = (uint32_t) (p_data_ptr + dma_size); /* fraction data address */ + } + + g_usb_cstd_dma_size[ip][ch] = dma_size; + + usb_cstd_dma_send_setting(ptr, (uint32_t) p_data_ptr, useport, dma_size); + + /* Changes the FIFO port by the pipe. */ + if (false == usb_check_use_usba_module(ptr)) + { + usb_cstd_chg_curpipe(ptr, pipe, useport, USB_FALSE); + } + + hw_usb_set_dreqe(ptr, useport); + + if (true == usb_check_use_usba_module(ptr)) + { + usb_cstd_chg_curpipe(ptr, pipe, useport, USB_FALSE); + } + } + else + { + if (USB_MODE_HOST == g_usb_usbmode[ip]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_hstd_buf_to_fifo(ptr, pipe, useport); + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_pstd_buf_to_fifo(pipe, useport, ptr); + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } /* if (USB_MODE_HOST == g_usb_usbmode[ip]) */ + } /* if (0U != dma_size) */ +} + +/****************************************************************************** + * End of function usb_cstd_dma_send_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_rcv_start + * Description : Start transfer using DMA. If transfer size is 0, clear DMA. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t pipe : Pipe number + * : uint16_t useport : FIFO select + * Return value : none + ******************************************************************************/ +void usb_cstd_dma_rcv_start (usb_utr_t * ptr, uint16_t pipe, uint16_t useport) +{ + uint16_t mxps; + uint8_t * p_data_ptr = 0; + uint16_t ip; + uint16_t ch; + uint16_t trncnt; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_HOST) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_data_ptr = gp_usb_hstd_data_ptr[ptr->ip][pipe]; + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + ip = ptr->ip; + } + else + { + ip = ptr->ip; + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + p_data_ptr = gp_usb_pstd_data[pipe]; + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + + ch = usb_cstd_dma_ref_ch_no(ptr, useport); + + /* Data size check */ + if (0U != g_usb_cstd_dma_size[ip][ch]) + { + hw_usb_clear_dreqe(ptr, useport); /* DMA Transfer request disable */ + + usb_cstd_dma_clear_ir(ptr, useport); + + usb_cstd_dma_rcv_setting(ptr, (uint32_t) p_data_ptr, useport, g_usb_cstd_dma_size[ip][ch]); + + /* Changes the FIFO port by the pipe. */ + if (false == usb_check_use_usba_module(ptr)) + { + usb_cstd_chg_curpipe(ptr, pipe, useport, USB_FALSE); + } + + /* Max Packet Size */ + mxps = usb_cstd_get_maxpacket_size(ptr, pipe); + + /* Set Transaction counter */ + trncnt = (uint16_t) (((g_usb_cstd_dma_size[ip][ch] - (uint32_t) 1U) / mxps) + (uint32_t) 1U); + usb_cstd_set_transaction_counter(ptr, pipe, trncnt); + + /* Enable Ready Interrupt */ + hw_usb_set_brdyenb(ptr, pipe); + + /* Enable Not Ready Interrupt */ + usb_cstd_nrdy_enable(ptr, pipe); + + /* usb fifo set automatic clear mode */ + hw_usb_clear_dclrm(ptr, useport); + + /* Set DREQ enable */ + hw_usb_set_dreqe(ptr, useport); + + if (true == usb_check_use_usba_module(ptr)) + { + usb_cstd_chg_curpipe(ptr, pipe, useport, USB_FALSE); + } + + /* Set BUF */ + usb_cstd_set_buf(ptr, pipe); + } +} + +/****************************************************************************** + * End of function usb_cstd_dma_rcv_start + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dfifo_end + * Description : Setup external variables used for USB data transfer; to reg- + * : ister if you want to stop the transfer of DMA. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t useport : FIFO select + * Return value : none + ******************************************************************************/ +void usb_cstd_dfifo_end (usb_utr_t * ptr, uint16_t useport) +{ + uint16_t pipe; + uint16_t ip; + uint16_t channel; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + if (USB_CFG_IP0 == ptr->ip) + { + ip = USB_IP0; + } + else + { + ip = USB_IP1; + } + } + else + { + ip = ptr->ip; + } + + channel = usb_cstd_dma_ref_ch_no(ptr, useport); + pipe = g_usb_cstd_dma_pipe[ip][channel]; + + if (g_usb_usbmode[ptr->ip] == USB_MODE_PERI) + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + #if (BSP_CFG_RTOS == 1) + if (g_usb_pstd_data_cnt[pipe] < g_usb_cstd_dma_size[ip][channel]) + { + g_usb_pstd_data_cnt[pipe] = 0U; + } + else + { + g_usb_pstd_data_cnt[pipe] -= g_usb_cstd_dma_size[ip][channel]; + } + #else /* BSP_CFG_RTOS == 1 */ + /* received data size */ + g_usb_pstd_data_cnt[pipe] -= g_usb_cstd_dma_size[ip][channel]; + #endif /* BSP_CFG_RTOS == 1 */ + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if (BSP_CFG_RTOS == 1) + if (g_usb_hstd_data_cnt[ptr->ip][pipe] < g_usb_cstd_dma_size[ip][channel]) + { + g_usb_hstd_data_cnt[ptr->ip][pipe] = 0U; + } + else + { + g_usb_hstd_data_cnt[ptr->ip][pipe] -= g_usb_cstd_dma_size[ip][channel]; + } + #else /* BSP_CFG_RTOS == 1 */ + /* received data size */ + g_usb_hstd_data_cnt[ptr->ip][pipe] -= g_usb_cstd_dma_size[ip][channel]; + #endif /* BSP_CFG_RTOS == 1 */ + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } +} + +/****************************************************************************** + * End of function usb_cstd_dfifo_end + ******************************************************************************/ + + #if (BSP_CFG_RTOS == 0) + +/****************************************************************************** + * Function Name : usb_cstd_dma_driver + * Description : USB DMA transfer complete process. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_cstd_dma_driver (void) +{ + usb_utr_t utr; + + if (gs_usb_cstd_dma_int.wp != gs_usb_cstd_dma_int.rp) + { + utr.ip = (uint8_t) gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.rp].ip; + utr.p_transfer_tx = gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.wp].p_cfg->p_transfer_tx; + utr.p_transfer_rx = gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.wp].p_cfg->p_transfer_rx; + if (USB_MODE_HOST == g_usb_usbmode[utr.ip]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + + usb_cstd_dma_stop(&utr, gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.rp].fifo_type); /* Stop DMA,FIFO access */ + + usb_cstd_dma_send_continue(&utr, gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.rp].fifo_type); + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_cstd_dma_stop(&utr, gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.rp].fifo_type); /* Stop DMA,FIFO access */ + + usb_cstd_dma_send_continue(&utr, gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.rp].fifo_type); + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + } + + /* Read count up */ + gs_usb_cstd_dma_int.rp = (uint8_t) (((uint8_t) (gs_usb_cstd_dma_int.rp + 1)) % USB_INT_BUFSIZE); + } +} + +/****************************************************************************** + * End of function usb_cstd_dma_driver + ******************************************************************************/ + #endif /* BSP_CFG_RTOS_USED == 0 */ + +/****************************************************************************** + * Function Name : usb_cstd_dma_send_restart + * Description : Start transfer using DMA0. accsess size 32bytes. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint32_t src : transfer data pointer + * : uint32_t data_size : transfer data size + * : uint16_t pipe : Pipe number + * Return value : none + ******************************************************************************/ +void usb_cstd_dma_send_restart (usb_utr_t * ptr, uint32_t src, uint32_t data_size, uint8_t pipe) +{ + uint16_t useport = 0; + uint16_t usb_dir; + + hw_usb_write_pipesel(ptr, pipe); + usb_dir = hw_usb_read_pipecfg(ptr); + usb_dir = usb_dir & USB_DIRFIELD; + if (0 == usb_dir) + { + useport = USB_D0USE; + } + else + { + useport = USB_D1USE; + } + + /* Changes the FIFO port by the pipe. */ + if (false == usb_check_use_usba_module(ptr)) + { + usb_cstd_chg_curpipe(ptr, pipe, useport, USB_FALSE); + } + + hw_usb_clear_dreqe(ptr, useport); /* DMA Transfer request disable */ + + usb_cstd_dma_clear_ir(ptr, useport); + + /* dma trans setting Divisible by FIFO buffer size */ + usb_cstd_dma_send_setting(ptr, src, useport, data_size); + + /* Set DREQ enable */ + hw_usb_set_dreqe(ptr, useport); + + if (true == usb_check_use_usba_module(ptr)) + { + usb_cstd_chg_curpipe(ptr, pipe, useport, USB_FALSE); + } +} + +/****************************************************************************** + * End of function usb_cstd_dma_send_restart + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_send_continue + * Description : Set end of DMA transfer. Set to restart DMA trans- + * : fer according to data size of remaining functions to be pro- + * : cessed. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t useport : FIFO select + * Return value : none + ******************************************************************************/ +void usb_cstd_dma_send_continue (usb_utr_t * ptr, uint16_t useport) +{ + uint8_t * p_src_adr; + uint8_t pipe; + uint32_t * p_data_cnt = 0; + uint8_t * p_data_ptr = 0; + uint16_t ip; + uint16_t channel; + uint16_t dma_size; + bool cpu_write = false; + + ip = ptr->ip; + + channel = usb_cstd_dma_ref_ch_no(ptr, useport); + pipe = (uint8_t) g_usb_cstd_dma_pipe[ip][channel]; + + if (g_usb_usbmode[ip] == USB_MODE_HOST) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + p_data_cnt = &g_usb_hstd_data_cnt[ptr->ip][pipe]; + p_data_ptr = gp_usb_hstd_data_ptr[ptr->ip][pipe]; + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + p_data_cnt = &g_usb_pstd_data_cnt[pipe]; + p_data_ptr = gp_usb_pstd_data[pipe]; + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + + /* trans data smaller than Buffer size */ + /* equal all data transfer end */ + #if (USB_CFG_DTC == USB_CFG_ENABLE) + if (p_data_cnt && (*p_data_cnt != 0)) + #else + if (p_data_cnt) + #endif + { + if ((*p_data_cnt) < g_usb_cstd_dma_fifo[ip][channel]) + { + if (g_usb_cstd_dma_fraction_size[ip][channel] > 0) /* fraction size(1-3) */ + { + cpu_write = true; /* Set flag for CPU FIFO Write */ + } + else + { + #if (USB_CFG_DTC == USB_CFG_ENABLE) + (*p_data_cnt) -= g_usb_cstd_dma_size[ip][channel]; + #endif + + /* FIFO buffer empty flag clear */ + hw_usb_clear_status_bemp(ptr, pipe); + + /* bval control for transfer enable fifo 2 usb control */ + hw_usb_set_bval(ptr, useport); + + /* FIFO bufer empty interrupt enable */ + hw_usb_set_bempenb(ptr, pipe); + } + } + else + { + /* update remaining transfer data size */ + (*p_data_cnt) -= g_usb_cstd_dma_size[ip][channel]; + + /* check transfer remaining data */ + if (0U == (*p_data_cnt)) + { + /* FIFO buffer empty flag clear */ + hw_usb_clear_status_bemp(ptr, pipe); + + /* check FIFO_EMPTY / INBUF bit */ + if ((hw_usb_read_pipectr(ptr, pipe) & USB_INBUFM) != USB_INBUFM) + { + /* DMA transfer function end. call callback function */ + + if (g_usb_usbmode[ip] == USB_MODE_HOST) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_hstd_data_end(ptr, pipe, (uint16_t) USB_DATA_NONE); + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_pstd_data_end(pipe, (uint16_t) USB_DATA_NONE, ptr); + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + } + else + { + /* FIFO bufer empty interrupt enable */ + hw_usb_set_bempenb(ptr, pipe); + } + } + else + { + /* dma trans remaining data */ + /* DMA source address update */ + p_src_adr = (uint8_t *) ((uint32_t) p_data_ptr + g_usb_cstd_dma_size[ip][channel]); + + /* DMA Transfer size update */ + g_usb_cstd_dma_size[ip][channel] = *p_data_cnt; + + dma_size = (uint16_t) g_usb_cstd_dma_size[ip][channel]; + + if (USB_IP0 == ip) + { + g_usb_cstd_dma_fraction_size[ip][channel] = g_usb_cstd_dma_size[ip][channel] & USB_BIT_MBW16; /* fraction size(1-3) */ + dma_size = (uint16_t) (dma_size & ~USB_BIT_MBW16); + } + + #if USB_NUM_USBIP == 2 + else + { + #if defined(USB_HIGH_SPEED_MODULE) + g_usb_cstd_dma_fraction_size[ip][channel] = g_usb_cstd_dma_size[ip][channel] & USB_BIT_MBW32; /* fraction size(1-3) */ + dma_size = (uint16_t) (dma_size & ~USB_BIT_MBW32); + #else /* defined (USB_HIGH_SPEED_MODULE) */ + g_usb_cstd_dma_fraction_size[ip][channel] = g_usb_cstd_dma_size[ip][channel] & USB_BIT_MBW16; /* fraction size(1-3) */ + dma_size = (uint16_t) (dma_size & ~USB_BIT_MBW16); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + #endif /* USB_NUM_USBIP == 2 */ + + g_usb_cstd_dma_fraction_adr[ip][channel] = (uint32_t) (p_src_adr + dma_size); /* fraction data address */ + + if (0 != dma_size) + { + g_usb_cstd_dma_size[ip][channel] = dma_size; + + /* DMA0 1byte trans */ + usb_cstd_dma_send_restart(ptr, (uint32_t) p_src_adr, dma_size, pipe); + } + else + { + cpu_write = true; /* Set flag for CPU FIFO Write */ + } + } + } + } + + if (true == cpu_write) + { + if (USB_MODE_HOST == g_usb_usbmode[ip]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + g_usb_hstd_data_cnt[ptr->ip][pipe] = (uint32_t) g_usb_cstd_dma_fraction_size[ip][channel]; /* fraction size(1-3) */ + gp_usb_hstd_data_ptr[ptr->ip][pipe] = (uint8_t *) g_usb_cstd_dma_fraction_adr[ip][channel]; /* fraction data address */ + usb_hstd_buf_to_fifo(ptr, pipe, useport); + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + g_usb_pstd_data_cnt[pipe] = (uint32_t) g_usb_cstd_dma_fraction_size[ip][channel]; /* fraction size(1-3) */ + gp_usb_pstd_data[pipe] = (uint8_t *) g_usb_cstd_dma_fraction_adr[ip][channel]; /* fraction data address */ + usb_pstd_buf_to_fifo(pipe, useport, ptr); + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } + + g_usb_cstd_dma_fraction_size[ip][channel] = 0; + } +} + +/****************************************************************************** + * End of function usb_cstd_dma_send_continue + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_get_ir_vect + * Description : Get vector no. of USB DxFIFO + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t useport : FIFO select + * Return value : Vector no. + ******************************************************************************/ +uint16_t usb_cstd_dma_get_ir_vect (usb_utr_t * ptr, uint16_t use_port) +{ + uint16_t ip; + uint16_t vect = USB_NULL; + + ip = ptr->ip; + + if (USB_IP0 == ip) + { + if (USB_D0USE == use_port) + { + #if defined(ELC_EVENT_USBFS_FIFO_0) + vect = ELC_EVENT_USBFS_FIFO_0; + #endif /* define(ELC_EVENT_USBFS_FIFO_0) */ + } + else + { + #if defined(ELC_EVENT_USBFS_FIFO_1) + vect = ELC_EVENT_USBFS_FIFO_1; + #endif /* ELC_EVENT_USBFS_FIFO_1 */ + } + } + + #if USB_NUM_USBIP == 2 + else + { + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_D0USE == use_port) + { + #if defined(ELC_EVENT_USBHS_FIFO_0) + vect = ELC_EVENT_USBHS_FIFO_0; + #endif /* defined(ELC_EVENT_USBHS_FIFO_0) */ + } + else + { + #if defined(ELC_EVENT_USBHS_FIFO_1) + vect = ELC_EVENT_USBHS_FIFO_1; + #endif /* defined(ELC_EVENT_USBHS_FIFO_1) */ + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + #if (!defined(USB_HIGH_SPEED_MODULE)) + if (USB_D0USE == use_port) + { + #if defined(ELC_EVENT_USBFS_FIFO_0) + vect = ELC_EVENT_USBFS_FIFO_0; + #endif /* defined(ELC_EVENT_USBFS_FIFO_0) */ + } + else + { + #if defined(ELC_EVENT_USBFS_FIFO_1) + vect = ELC_EVENT_USBFS_FIFO_1; + #endif /* defined(ELC_EVENT_USBFS_FIFO_1) */ + } + #endif /* (!defined(USB_HIGH_SPEED_MODULE)) */ + } + #endif /* USB_NUM_USBIP == 2 */ + + return vect; +} + +/****************************************************************************** + * End of function usb_cstd_dma_get_ir_vect + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_clear_ir + * Description : Clear Interrupt status of USB DxFIFO. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t useport : FIFO select + * Return value : none + ******************************************************************************/ +void usb_cstd_dma_clear_ir (usb_utr_t * ptr, uint16_t use_port) +{ + uint16_t ip; + IRQn_Type irq; + + ip = ptr->ip; + + if (USB_IP0 == ip) + { + if (USB_D0USE == use_port) + { + #if defined(VECTOR_NUMBER_USBFS_FIFO_0) + irq = (IRQn_Type) VECTOR_NUMBER_USBFS_FIFO_0; + R_BSP_IrqStatusClear(irq); + #endif /* defined(VECTOR_NUMBER_USBFS_FIFO_0) */ + } + else + { + #if defined(VECTOR_NUMBER_USBFS_FIFO_1) + irq = (IRQn_Type) VECTOR_NUMBER_USBFS_FIFO_1; + R_BSP_IrqStatusClear(irq); + #endif /* defined(VECTOR_NUMBER_USBFS_FIFO_1) */ + } + } + + #if USB_NUM_USBIP == 2 + else + { + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_D0USE == use_port) + { + #if defined(VECTOR_NUMBER_USBHS_FIFO_0) + irq = (IRQn_Type) VECTOR_NUMBER_USBHS_FIFO_0; + R_BSP_IrqStatusClear(irq); + #endif /* defined(VECTOR_NUMBER_USBHS_FIFO_0) */ + } + else + { + #if defined(VECTOR_NUMBER_USBHS_FIFO_1) + irq = (IRQn_Type) VECTOR_NUMBER_USBHS_FIFO_1; + R_BSP_IrqStatusClear(irq); + #endif /* defined(VECTOR_NUMBER_USBHS_FIFO_1) */ + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + #if (!defined(USB_HIGH_SPEED_MODULE)) + if (USB_D0USE == use_port) + { + #if defined(VECTOR_NUMBER_USBFS_FIFO_0) + irq = (IRQn_Type) VECTOR_NUMBER_USBFS_FIFO_0; + R_BSP_IrqStatusClear(irq); + #endif /* defined(VECTOR_NUMBER_USBFS_FIFO_0) */ + } + else + { + #if defined(VECTOR_NUMBER_USBFS_FIFO_1) + irq = (IRQn_Type) VECTOR_NUMBER_USBFS_FIFO_1; + R_BSP_IrqStatusClear(irq); + #endif /* defined(VECTOR_NUMBER_USBFS_FIFO_1) */ + } + #endif /* (!defined(USB_HIGH_SPEED_MODULE)) */ + } + #endif /* USB_NUM_USBIP == 2 */ +} + +/****************************************************************************** + * End of function usb_cstd_dma_clear_ir + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_ref_ch_no + * Description : Get DMA channel no. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t useport : FIFO select + * Return value : DMA channel no. + ******************************************************************************/ +uint8_t usb_cstd_dma_ref_ch_no (usb_utr_t * p_utr, uint16_t use_port) +{ + uint8_t result = 10; + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + dmac_extended_cfg_t * channel_info; + + if (p_utr) + { + if (USB_D0USE == use_port) + { + channel_info = (dmac_extended_cfg_t *) p_utr->p_transfer_rx->p_cfg->p_extend; + } + else + { + channel_info = (dmac_extended_cfg_t *) p_utr->p_transfer_tx->p_cfg->p_extend; + } + + result = channel_info->channel; + } + #elif (USB_CFG_DTC == USB_CFG_ENABLE) + if (p_utr) + { + if (USB_D0USE == use_port) + { + result = USB_DMA_DIR_RD; + } + else + { + result = USB_DMA_DIR_WR; + } + } + #endif + + return result; /* DMA ch no. table */ +} + +/****************************************************************************** + * End of function usb_cstd_dma_ref_ch_no + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_send_complete + * Description : Set event for DMA transfer complete of Buffer to DxFIFO. + * Arguments : uint16_t ip_no : IP no.(USB_IP0/USB_IP1) + * : uint16_t useport: FIFO select(USB_D0USE/USB_D1USE) + * Return value : none + ******************************************************************************/ +void usb_cstd_dma_send_complete (uint8_t ip_no, uint16_t use_port) +{ + usb_cfg_t * p_cfg = USB_NULL; + usb_utr_t utr; + #if (BSP_CFG_RTOS != 0) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_utr_t * p_host; + #endif + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_utr_t * p_peri; + #endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + #endif /* #if (BSP_CFG_RTOS != 0) */ + + if (ip_no) + { + #if defined(USB_HIGH_SPEED_MODULE) + #if defined(VECTOR_NUMBER_USBHS_FIFO_1) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBHS_FIFO_1); + #endif /* defined(VECTOR_NUMBER_USBHS_FIFO_1) */ + #else /* defined(USB_HIGH_SPEED_MODULE) */ + #if defined(VECTOR_NUMBER_USBFS_FIFO_1) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBFS_FIFO_1); + #endif /* defined(VECTOR_NUMBER_USBFS_FIFO_1) */ + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + } + else + { + #if defined(VECTOR_NUMBER_USBFS_FIFO_1) + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet((IRQn_Type) VECTOR_NUMBER_USBFS_FIFO_1); + #endif /* defined(VECTOR_NUMBER_USBFS_FIFO_1) */ + } + + #if (BSP_CFG_RTOS != 0) + #if USB_NUM_USBIP == 2 + if (USB_MODE_HOST == g_usb_usbmode[ip_no]) + #else /* USB_NUM_USBIP == 2 */ + if (USB_MODE_HOST == g_usb_usbmode[0]) + #endif /* USB_NUM_USBIP == 2 */ + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ip = ip_no; + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + + hw_usb_clear_dreqe(&utr, use_port); /* DMA Transfer request disable */ + + p_host = get_usb_int_buf_dma(); + p_host->ip = ip_no; + p_host->msginfo = USB_MSG_HCD_INT; + p_host->keyword = USB_INT_DXFIFO; + p_host->status = use_port; + p_host->p_transfer_tx = p_cfg->p_transfer_tx; + p_host->p_transfer_rx = p_cfg->p_transfer_rx; + + p_host->ipp = utr.ipp; + USB_ISND_MSG(USB_HCD_MBX, (usb_msg_t *) p_host); + #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + utr.ip = ip_no; + + hw_usb_clear_dreqe(&utr, use_port); /* DMA Transfer request disable */ + + p_peri = get_usb_int_buf_dma(); + p_peri->ip = ip_no; + p_peri->msginfo = USB_MSG_PCD_INT; + p_peri->keyword = USB_INT_DXFIFO; + p_peri->status = use_port; + p_peri->p_transfer_tx = p_cfg->p_transfer_tx; + p_peri->p_transfer_rx = p_cfg->p_transfer_rx; + + USB_ISND_MSG(USB_PCD_MBX, (usb_msg_t *) p_peri); + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + } + #else /* (BSP_CFG_RTOS != 0) */ + gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.wp].ip = ip_no; + gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.wp].fifo_type = use_port; + gs_usb_cstd_dma_int.wp = (uint8_t) (((uint8_t) (gs_usb_cstd_dma_int.wp + 1)) % USB_INT_BUFSIZE); + gs_usb_cstd_dma_int.buf[gs_usb_cstd_dma_int.wp].p_cfg = p_cfg; + + utr.ip = ip_no; + #if USB_NUM_USBIP == 2 + if (USB_MODE_HOST == g_usb_usbmode[utr.ip]) + #else /* USB_NUM_USBIP == 2 */ + if (USB_MODE_HOST == g_usb_usbmode[0]) + #endif /* USB_NUM_USBIP == 2 */ + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + utr.ipp = usb_hstd_get_usb_ip_adr(utr.ip); + + hw_usb_clear_dreqe(&utr, use_port); /* DMA Transfer request disable */ + #endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + hw_usb_clear_dreqe(&utr, use_port); /* DMA Transfer request disable */ + #endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + } + #endif /* (BSP_CFG_RTOS != 0) */ +} + +/****************************************************************************** + * End of function usb_cstd_dma_send_complete + ******************************************************************************/ + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + +/******************************************************************************* + * Function Name: usb_ip0_d1fifo_callback + * Description : Interrupt service routine of D1FIFO + * Arguments : none + * Return Value : none + *******************************************************************************/ +void usb_ip0_d1fifo_callback (dmac_callback_args_t * cb_data) +{ + (void) *cb_data; + usb_cstd_dma_send_complete(USB_IP0, USB_D1USE); +} + +/****************************************************************************** + * End of function usb_ip0_d1fifo_callback + ******************************************************************************/ + +/******************************************************************************* + * Function Name: usb_ip1_d1fifo_callback + * Description : Interrupt service routine of D1FIFO + * Arguments : none + * Return Value : none + *******************************************************************************/ +void usb_ip1_d1fifo_callback (dmac_callback_args_t * cb_data) +{ + (void) *cb_data; + usb_cstd_dma_send_complete(USB_IP1, USB_D1USE); +} + +/****************************************************************************** + * End of function usb_ip1_d1fifo_callback + ******************************************************************************/ + #endif + +/****************************************************************************** + * Function Name : hw_usb_get_dxfifo_adr + * Description : Get FIFO port address of DMA/DTC. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t use_port : FIFO select + * : uint16_t bit_width : Access bit size of USB DxFIFO + * Return : Address of FIFO port. + ******************************************************************************/ +uint32_t hw_usb_get_dxfifo_adr (usb_utr_t * ptr, uint16_t use_port, uint16_t bit_width) +{ + uint32_t address; + uint8_t ip; + + /* Host mode */ + if (USB_IP0 == ptr->ip) + { + ip = USB_IP0; + } + else + { + ip = USB_IP1; + } + + address = g_fifo_address[ip][use_port][bit_width]; /* Set address of FIFO port */ + return address; +} + +/****************************************************************************** + * End of function hw_usb_get_dxfifo_adr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_transfer_wait + * Description : wait for DMA/DTC transfer to complete + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint8_t_t dir : USB setting direction + * Return value : void + ******************************************************************************/ +void usb_cstd_transfer_wait (usb_utr_t * ptr, uint8_t dir) +{ + #if (USB_CFG_DMA == USB_CFG_ENABLE) + uint16_t active_cnt = 0; + dmac_extended_cfg_t * channel_info; + dmac_instance_ctrl_t * p_dmac_ctrl; + + // Receive dir + if (dir == USB_DMA_DIR_RD) + { + channel_info = (dmac_extended_cfg_t *) ptr->p_transfer_rx->p_cfg->p_extend; + p_dmac_ctrl = (dmac_instance_ctrl_t *) ptr->p_transfer_rx->p_ctrl; + p_dmac_ctrl->p_reg = USB_DMAC_PRV_REG(channel_info->channel); + } + else + { + channel_info = (dmac_extended_cfg_t *) ptr->p_transfer_tx->p_cfg->p_extend; + p_dmac_ctrl = (dmac_instance_ctrl_t *) ptr->p_transfer_tx->p_ctrl; + p_dmac_ctrl->p_reg = USB_DMAC_PRV_REG(channel_info->channel); + } + + do + { + if (1 == p_dmac_ctrl->p_reg->DMSTS_b.ACT) + { + active_cnt = 0; + } + else + { + active_cnt++; + } + } while (active_cnt < ACTIVE_CNT_NUMBER); + #elif (USB_CFG_DTC == USB_CFG_ENABLE) + dtc_instance_ctrl_t * p_dtc_ctrl = (dir == 0) ? ptr->p_transfer_rx->p_ctrl : + ptr->p_transfer_tx->p_ctrl; + + uint32_t in_progress = (1U << DTC_PRV_OFFSET_IN_PROGRESS) | (uint32_t) p_dtc_ctrl->irq; + + uint16_t active_cnt = 0; + + /* Wait for Complete of DTC transfer. */ + /* WAIT_LOOP */ + do + { + if (R_DTC->DTCSTS == in_progress) + { + active_cnt = 0; + } + else + { + active_cnt++; + } + } while (active_cnt < ACTIVE_CNT_NUMBER); + #endif +} + +/****************************************************************************** + * Function Name : usb_cstd_dma_rcv_setting + * Description : FIFO to Buffer data read DMA start + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint32_t des_addr : Source address + * : uint16_t useport : FIFO Access mode + * : uint32_t transfer_size : Transfer size + * Return value : void + ******************************************************************************/ +void usb_cstd_dma_rcv_setting (usb_utr_t * ptr, uint32_t des_addr, uint16_t useport, uint32_t transfer_size) +{ + uint8_t dma_ch; + uint16_t ip; + uint16_t block_size; + + if (USB_NULL != ptr) + { + ip = ptr->ip; + + dma_ch = usb_cstd_dma_ref_ch_no(ptr, useport); + + /* Wait for Complete of DMA transfer. */ + /* WAIT_LOOP */ + usb_cstd_transfer_wait(ptr, USB_DMA_DIR_RD); + +/* DMA test code start */ + /* Operation - No Extended Repeat Area Function and No Offset Subtraction */ + + /* Source address is fixed + * Transfer data size is 32-bit (long word). + * DMAC transfer mode is Repeat mode & Source side is repeat area + * At the beginning of transfer, clear the interrupt flag of the activation source + * to 0. + * Transfer Request source is software. *//* Set Transfer data configuration. */ + const transfer_instance_t * p_transfer_rx = ptr->p_transfer_rx; + transfer_info_t * p_transfer_info = p_transfer_rx->p_cfg->p_info; + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ip) + { + p_transfer_info->p_src = (void *) hw_usb_get_dxfifo_adr(ptr, useport, USB_FIFO_ACCESS_TYPE_32BIT); + block_size = (uint16_t) (((g_usb_cstd_dma_fifo[ip][dma_ch] - 1) / 4) + 1); + } + else + { + p_transfer_info->p_src = (void *) hw_usb_get_dxfifo_adr(ptr, useport, USB_FIFO_ACCESS_TYPE_16BIT); + block_size = (uint16_t) (((g_usb_cstd_dma_fifo[ip][dma_ch] - 1) / 2) + 1); + } + #else /* defined (USB_HIGH_SPEED_MODULE) */ + p_transfer_info->p_src = (void *) hw_usb_get_dxfifo_adr(ptr, useport, USB_FIFO_ACCESS_TYPE_16BIT); + block_size = (uint16_t) (((g_usb_cstd_dma_fifo[ip][dma_ch] - 1) / 2) + 1); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + p_transfer_info->p_dest = (void *) des_addr; + p_transfer_info->length = block_size; + p_transfer_info->num_blocks = + (uint16_t) (((transfer_size - 1) / g_usb_cstd_dma_fifo[ip][dma_ch]) + 1); + + /* Call R_DMAC_Reconfigure(). */ + p_transfer_rx->p_api->reconfigure(p_transfer_rx->p_ctrl, p_transfer_info); + } /* if (USB_NULL != ptr) */ +} + +/****************************************************************************** + * End of function usb_cstd_dma_rcv_setting + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_send_setting + * Description : Buffer to FIFO data write DMA start + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint32_t src_adr : Source address + * : uint16_t useport : FIFO Access mode + * : uint32_t transfer_size : Transfer size + * Return value : none + ******************************************************************************/ +void usb_cstd_dma_send_setting (usb_utr_t * ptr, uint32_t src_adr, uint16_t useport, uint32_t transfer_size) +{ + uint8_t dma_ch; + uint16_t ip; + uint32_t block_size; + + if (USB_NULL != ptr) + { + ip = ptr->ip; + + dma_ch = usb_cstd_dma_ref_ch_no(ptr, useport); + + if (g_usb_cstd_dma_fifo[ip][dma_ch] > transfer_size) + { + block_size = transfer_size; + } + else + { + block_size = g_usb_cstd_dma_fifo[ip][dma_ch]; + } + + const transfer_instance_t * p_transfer_tx = ptr->p_transfer_tx; + transfer_info_t * p_transfer_info = p_transfer_tx->p_cfg->p_info; + #if defined(USB_HIGH_SPEED_MODULE) + if ((0 == (transfer_size & 0x03)) && (USB_IP1 == ip)) + { + p_transfer_info->p_dest = (void *) hw_usb_get_dxfifo_adr(ptr, useport, USB_FIFO_ACCESS_TYPE_32BIT); + block_size = (block_size / USB_BIT_32_WIDTH); + } + else + { + p_transfer_info->p_dest = (void *) hw_usb_get_dxfifo_adr(ptr, useport, USB_FIFO_ACCESS_TYPE_16BIT); + block_size = (block_size / USB_BIT_16_WIDTH); + } + #else /* defined (USB_HIGH_SPEED_MODULE) */ + p_transfer_info->p_dest = (void *) hw_usb_get_dxfifo_adr(ptr, useport, USB_FIFO_ACCESS_TYPE_16BIT); + block_size = (block_size / USB_BIT_16_WIDTH); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + /* Wait for Complete of DMA transfer. */ + /* WAIT_LOOP */ + usb_cstd_transfer_wait(ptr, USB_DMA_DIR_WR); + +/* DMA test code start */ + /* Operation - No Extended Repeat Area Function and No Offset Subtraction */ + + /* Source address is fixed + * Transfer data size is 32-bit (long word). + * DMAC transfer mode is Repeat mode & Source side is repeat area + * At the beginning of transfer, clear the interrupt flag of the activation source + * to 0. + * Transfer Request source is software. *//* Set Transfer data configuration. */ + p_transfer_info->p_src = (void *) src_adr; + p_transfer_info->length = (uint16_t) block_size; + p_transfer_info->num_blocks = + (uint16_t) ((transfer_size - 1) / (g_usb_cstd_dma_fifo[ip][dma_ch]) + 1); + + /* Call R_DMACA_Create(). */ + p_transfer_tx->p_api->reconfigure(p_transfer_tx->p_ctrl, p_transfer_info); + } /* if (USB_NULL != ptr) */ +} + +/****************************************************************************** + * End of function usb_cstd_dma_send_setting + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_stop + * Description : DMA stop + * Arguments : uint8_t ip_type : USB_IP0/USB_IP1 + * : uint16_t use_port : FIFO select + * Return value : void + ******************************************************************************/ +void usb_cstd_dma_stop (usb_utr_t * p_utr, uint16_t use_port) +{ + /* Wait for Complete of DMA transfer. */ + /* WAIT_LOOP */ + if (USB_D0USE == use_port) + { + usb_cstd_transfer_wait(p_utr, USB_DMA_DIR_RD); + } + else + { + usb_cstd_transfer_wait(p_utr, USB_DMA_DIR_WR); + } +} + +/****************************************************************************** + * End of function usb_cstd_dma_stop + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cstd_dma_get_crtb + * Description : Get DMA Current Transaction Byte reg B(CRTB). + * Arguments : uint16_t dma_ch : DMA Channel no. + * Return value : DMA Current Transaction Byte reg B(CRTB) + ******************************************************************************/ +uint16_t usb_cstd_dma_get_crtb (usb_utr_t * p_utr) +{ + transfer_properties_t result; + + p_utr->p_transfer_rx->p_api->infoGet(p_utr->p_transfer_rx->p_ctrl, &result); + + return (uint16_t) result.block_count_remaining; +} + +/****************************************************************************** + * End of function usb_cstd_dma_get_crtb + ******************************************************************************/ + + #if (BSP_CFG_RTOS != 0) + +/****************************************************************************** + * Function Name : get_usb_int_buf_dma + * Description : USB interrupt routine. Analyze which USB interrupt occurred + * : and send message to DMA. + * Arguments : none + * Return value : Point to the area for usb_int_t structure + ******************************************************************************/ +usb_utr_t * get_usb_int_buf_dma (void) +{ + static uint16_t count = 0; + usb_utr_t * p; + + p = &g_usb_cstd_int_dma[count]; + + count = ((uint16_t) (((uint16_t) (count + 1)) % USB_INT_BUFSIZE)); + + return p; +} + +/****************************************************************************** + * End of function get_usb_int_buf_dma + ******************************************************************************/ + #endif /* #if (BSP_CFG_RTOS != 0) */ + +#endif /* USB_CFG_DMA == USB_CFG_ENABLE */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hostelectrical.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hostelectrical.c new file mode 100644 index 0000000000..132172cd51 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hostelectrical.c @@ -0,0 +1,231 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" + +#define USB_VALUE_50 (50) +#define USB_VALUE_300 (300) + +#if defined(USB_HIGH_SPEED_MODULE) + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : usb_hstd_test_stop + * Description : Host electrical test stop + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t port : Port number + * Return value : none + ******************************************************************************/ +void usb_hstd_test_stop (usb_utr_t * ptr) +{ + /* USBRST=0, RESUME=0, UACT=1 */ + usb_hstd_set_uact(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_test_stop + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_test_signal + * Description : Host electrical test signal control. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t command : USB_UACTON / OFF + * Return value : none + ******************************************************************************/ +void usb_hstd_test_signal (usb_utr_t * ptr, uint16_t command) +{ + uint16_t buff; + + switch (command) + { + case 1: + { + buff = USB_H_TST_J; + break; + } + + case 2: + { + buff = USB_H_TST_K; + break; + } + + case 3: + { + buff = USB_H_TST_SE0_NAK; + break; + } + + case 4: + { + buff = USB_H_TST_PACKET; + break; + } + + default: + { + buff = USB_H_TST_NORMAL; + hw_usb_set_utst(ptr, buff); + usb_hstd_sw_reset(ptr); + break; + } + } + + usb_hstd_test_uact_ctrl(ptr, (uint16_t) USB_UACTOFF); + hw_usb_set_utst(ptr, buff); + usb_hstd_test_uact_ctrl(ptr, (uint16_t) USB_UACTON); +} + +/****************************************************************************** + * End of function usb_hstd_test_signal + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_test_uact_ctrl + * Description : Host electrical test SOF control. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t command : USB_UACTON / OFF + * Return value : none + ******************************************************************************/ +void usb_hstd_test_uact_ctrl (usb_utr_t * ptr, uint16_t command) +{ + if (USB_UACTON == command) + { + /* SOF out disable */ + hw_usb_hset_uact(ptr); + } + else + { + /* SOF out disable */ + hw_usb_hclear_uact(ptr); + } + + /* Wait 1ms */ + usb_cpu_delay_xms((uint16_t) 1); +} + +/****************************************************************************** + * End of function usb_hstd_test_uact_ctrl + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_test_vbus_ctrl + * Description : Host electrical test VBUS control. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t command : USB_UACTON / OFF + * Return value : none + ******************************************************************************/ +void usb_hstd_test_vbus_ctrl (usb_utr_t * ptr, uint16_t command) +{ + if (USB_VBON == command) + { + /* VBUS on */ + hw_usb_set_vbout(ptr); + } + else + { + /* VBUS off */ + hw_usb_clear_vbout(ptr); + } + + /* Wait 1ms */ + usb_cpu_delay_xms((uint16_t) 1); +} + +/****************************************************************************** + * End of function usb_hstd_test_vbus_ctrl + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_test_bus_reset + * Description : Host electrical test USB-reset signal control. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_test_bus_reset (usb_utr_t * ptr) +{ + /* USBRST=1, UACT=0 */ + hw_usb_rmw_dvstctr(ptr, USB_USBRST, (USB_USBRST | USB_UACT)); + + /* Wait 50ms */ + usb_cpu_delay_xms((uint16_t) USB_VALUE_50); + + /* USBRST=0 */ + hw_usb_clear_dvstctr(ptr, USB_USBRST); /* for UTMI */ + usb_cpu_delay_1us(USB_VALUE_300); /* for UTMI */ + + /* USBRST=0, RESUME=0, UACT=1 */ + usb_hstd_set_uact(ptr); + + /* Wait 10ms or more (USB reset recovery) */ + usb_cpu_delay_xms((uint16_t) 20); +} + +/****************************************************************************** + * End of function usb_hstd_test_bus_reset + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_test_suspend + * Description : Host electrical test suspend control. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_test_suspend (usb_utr_t * ptr) +{ + /* SOF out disable */ + hw_usb_hclear_uact(ptr); + + /* Wait 1ms */ + usb_cpu_delay_xms((uint16_t) 1); +} /* End of function */ + +/****************************************************************************** + * End of function usb_hstd_test_suspend + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_test_resume + * Description : Host electrical test resume control. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_test_resume (usb_utr_t * ptr) +{ + /* RESUME bit on */ + hw_usb_hset_resume(ptr); + + /* Wait */ + usb_cpu_delay_xms((uint16_t) 20); + + /* RESUME bit off */ + hw_usb_hclear_resume(ptr); + + /* SOF on */ + hw_usb_hset_uact(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_test_resume + ******************************************************************************/ + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_abs.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_abs.c new file mode 100644 index 0000000000..18a583f25e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_abs.c @@ -0,0 +1,1128 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" + +#define USB_VALUE_50 (50) +#define USB_VALUE_300 (300) +#define USB_VALUE_00FFH (0x00FF) +#define USB_VALUE_000000FFH (0x000000FF) + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : usb_hstd_set_hub_port + * Description : Set up-port hub + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t addr : device address + * : uint16_t upphub : up-port hub address + * : uint16_t hubport : hub port number + * Return value : none + ******************************************************************************/ +void usb_hstd_set_hub_port (usb_utr_t * ptr, uint16_t addr, uint16_t upphub, uint16_t hubport) +{ + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + hw_usb_hrmw_devadd(ptr, addr, (upphub | hubport), (uint16_t) (USB_UPPHUB | USB_HUBPORT)); + } + + #else /* defined (USB_HIGH_SPEED_MODULE) */ + FSP_PARAMETER_NOT_USED(*ptr); + FSP_PARAMETER_NOT_USED(addr); + FSP_PARAMETER_NOT_USED(upphub); + FSP_PARAMETER_NOT_USED(hubport); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ +} + +/****************************************************************************** + * End of function usb_hstd_set_hub_port + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_interrupt_handler + * Description : Analyzes which USB interrupt is generated + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return : none + ******************************************************************************/ +void usb_hstd_interrupt_handler (usb_utr_t * ptr) +{ + uint16_t intsts0; + uint16_t intenb0; + uint16_t ists0; + + uint16_t intsts1; + uint16_t intenb1; + uint16_t ists1; + + uint16_t brdysts; + uint16_t brdyenb; + uint16_t bsts; + + uint16_t nrdysts; + uint16_t nrdyenb; + uint16_t nsts; + + uint16_t bempsts; + uint16_t bempenb; + uint16_t ests; + + intsts0 = ptr->ipp->INTSTS0; + intsts1 = ptr->ipp->INTSTS1; + brdysts = ptr->ipp->BRDYSTS; + nrdysts = ptr->ipp->NRDYSTS; + bempsts = ptr->ipp->BEMPSTS; + intenb0 = ptr->ipp->INTENB0; + intenb1 = ptr->ipp->INTENB1; + brdyenb = ptr->ipp->BRDYENB; + nrdyenb = ptr->ipp->NRDYENB; + bempenb = ptr->ipp->BEMPENB; + + /* Interrupt Status Get */ + ptr->keyword = USB_INT_UNKNOWN; + ptr->status = 0; + + ists0 = (uint16_t) (intsts0 & intenb0); + ists1 = (uint16_t) (intsts1 & intenb1); + + /* ists2 = (uint16_t)(intsts2 & intenb2);*/ + bsts = (uint16_t) (brdysts & brdyenb); + nsts = (uint16_t) (nrdysts & nrdyenb); + ests = (uint16_t) (bempsts & bempenb); + + /***** Processing Setup transaction *****/ + if (USB_SACK == (ists1 & USB_SACK)) + { + /***** Setup ACK *****/ + /* SACK Clear */ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_SACK) & INTSTS1_MASK); + + /* Setup Ignore,Setup Acknowledge disable */ + ptr->ipp->INTENB1 &= (uint16_t) ~(USB_SIGNE | USB_SACKE); + ptr->keyword = USB_INT_SACK; + } + else if (USB_SIGN == (ists1 & USB_SIGN)) + { + /***** Setup Ignore *****/ + /* SIGN Clear */ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_SIGN) & INTSTS1_MASK); + + /* Setup Ignore,Setup Acknowledge disable */ + ptr->ipp->INTENB1 &= (uint16_t) ~((USB_SIGNE) | USB_SACKE); + ptr->keyword = USB_INT_SIGN; + } + /***** Processing PIPE0-MAX_PIPE_NO data *****/ + else if (USB_BRDY == (ists0 & USB_BRDY)) /***** EP0-7 BRDY *****/ + { + ptr->ipp->BRDYSTS = (uint16_t) ((uint16_t) (~bsts) & BRDYSTS_MASK); + ptr->keyword = USB_INT_BRDY; + ptr->status = bsts; + } + else if (USB_BEMP == (ists0 & USB_BEMP)) /***** EP0-7 BEMP *****/ + { + ptr->ipp->BEMPSTS = (uint16_t) ((uint16_t) (~ests) & BEMPSTS_MASK); + ptr->keyword = USB_INT_BEMP; + ptr->status = ests; + } + else if (USB_NRDY == (ists0 & USB_NRDY)) /***** EP0-7 NRDY *****/ + { + ptr->ipp->NRDYSTS = (uint16_t) ((uint16_t) (~nsts) & NRDYSTS_MASK); + ptr->keyword = USB_INT_NRDY; + ptr->status = nsts; + } + /***** Processing rootport0 *****/ + else if (USB_OVRCR == (ists1 & USB_OVRCR)) /***** OVER CURRENT *****/ + { + /* OVRCR Clear */ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_OVRCR) & INTSTS1_MASK); + ptr->keyword = USB_INT_OVRCR0; + } + else if (USB_ATTCH == (ists1 & USB_ATTCH)) /***** ATTCH INT *****/ + { + /* DTCH interrupt disable */ + usb_hstd_bus_int_disable(ptr); + ptr->keyword = USB_INT_ATTCH0; + #if defined(USB_CFG_OTG_USE) + if (USB_YES == g_usb_otg_hnp_process[ptr->ip]) + { + g_usb_is_otg_attach_interrupt[ptr->ip] = USB_YES; + } + #endif /* defined(USB_CFG_OTG_USE) */ + } + else if (USB_EOFERR == (ists1 & USB_EOFERR)) /***** EOFERR INT *****/ + { + /* EOFERR Clear */ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_EOFERR) & INTSTS1_MASK); + ptr->keyword = USB_INT_EOFERR0; + } + else if (USB_BCHG == (ists1 & USB_BCHG)) /***** BCHG INT *****/ + { + /* BCHG interrupt disable */ + usb_hstd_bchg_disable(ptr); + ptr->keyword = USB_INT_BCHG0; + } + else if (USB_DTCH == (ists1 & USB_DTCH)) /***** DETACH *****/ + { + /* DTCH interrupt disable */ + usb_hstd_bus_int_disable(ptr); + ptr->keyword = USB_INT_DTCH0; + } + + #if USB_CFG_BC == USB_CFG_ENABLE + else if (USB_PDDETINT == (ists1 & USB_PDDETINT)) /***** PDDETINT INT *****/ + { + if (USB_IP1 == ptr->ip) + { + /* PDDETINT interrupt disable */ + ptr->ipp1->INTSTS1 = (uint16_t) ((~USB_PDDETINT) & INTSTS1_MASK); + ptr->keyword = USB_INT_PDDETINT0; + } + } + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + /***** Processing VBUS/SOF *****/ + else if (USB_VBINT == (ists0 & USB_VBINT)) /***** VBUS change *****/ + { + /* Status Clear */ + ptr->ipp->INTSTS0 = (uint16_t) ~USB_VBINT; + ptr->keyword = USB_INT_VBINT; + } + else if (USB_SOFR == (ists0 & USB_SOFR)) /***** SOFR change *****/ + { + /* SOFR Clear */ + ptr->ipp->INTSTS0 = (uint16_t) ~USB_SOFR; + ptr->keyword = USB_INT_SOFR; + } + else + { + /* Non */ + } +} + +/****************************************************************************** + * End of function usb_hstd_interrupt_handler + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_chk_attach + * Description : Checks whether USB Device is attached or not and return USB speed + * : of USB Device + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : uint16_t : connection status + * : : (USB_ATTACHF/USB_ATTACHL/USB_DETACH/USB_OK) + * Note : Please change for your SYSTEM + ******************************************************************************/ +uint16_t usb_hstd_chk_attach (usb_utr_t * ptr) +{ + uint16_t buf[3]; + uint16_t result = USB_DETACH; + + usb_hstd_read_lnst(ptr, buf); + + if (USB_UNDECID == (uint16_t) (buf[1] & USB_RHST)) + { + if (USB_FS_JSTS == (buf[0] & USB_LNST)) + { + /* High/Full speed device */ + USB_PRINTF0(" Detect FS-J\n"); + #if !defined(USB_CFG_OTG_USE) + #if defined(USB_HIGH_SPEED_MODULE) + usb_hstd_set_hse(ptr, g_usb_hstd_hs_enable[ptr->ip]); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #endif /* !defined(USB_CFG_OTG_USE) */ + result = USB_ATTACHF; + } + else if (USB_LS_JSTS == (buf[0] & USB_LNST)) + { + /* Low speed device */ + USB_PRINTF0(" Attach LS device\n"); + #if !defined(USB_CFG_OTG_USE) + #if defined(USB_HIGH_SPEED_MODULE) + usb_hstd_set_hse(ptr, USB_HS_DISABLE); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #endif /* !defined(USB_CFG_OTG_USE) */ + result = USB_ATTACHL; + } + else if (USB_SE0 == (buf[0] & USB_LNST)) + { + USB_PRINTF0(" Detach device\n"); + } + else + { + USB_PRINTF0(" Attach unknown speed device\n"); + } + } + else + { + USB_PRINTF0(" Already device attached\n"); + result = USB_OK; + } + + return result; +} + +/****************************************************************************** + * End of function usb_hstd_chk_attach + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_chk_clk + * Description : Checks SOF sending setting when USB Device is detached or suspended + * : , BCHG interrupt enable setting and clock stop processing + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t event : device state + * Return value : none + ******************************************************************************/ +void usb_hstd_chk_clk (usb_utr_t * ptr, uint16_t event) +{ + (void) event; + if ((USB_DETACHED == g_usb_hstd_mgr_mode[ptr->ip]) || (USB_SUSPENDED == g_usb_hstd_mgr_mode[ptr->ip])) + { + usb_hstd_chk_sof(ptr); + + /* Enable port BCHG interrupt */ + usb_hstd_bchg_enable(ptr); + } +} /* End of function usb_hstd_chk_clk */ + +/****************************************************************************** + * End of function usb_hstd_chk_clk + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_detach_process + * Description : Handles the require processing when USB device is detached + * : (Data transfer forcibly termination processing to the connected USB Device, + * : the clock supply stop setting and the USB interrupt dissable setteing etc) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_detach_process (usb_utr_t * ptr) +{ + uint16_t connect_inf; + uint16_t md; + uint16_t i; + uint16_t addr; + + /* ATTCH interrupt disable */ + usb_hstd_attch_disable(ptr); + + /* DTCH interrupt disable */ + usb_hstd_dtch_disable(ptr); + usb_hstd_bchg_disable(ptr); + + /* WAIT_LOOP */ + for (md = 1U; md < (USB_MAXDEVADDR + 1U); md++) + { + addr = (uint16_t) (md << USB_DEVADDRBIT); + if (usb_hstd_chk_dev_addr(ptr, addr) != USB_NOCONNECT) + { + if (USB_IDLEST != g_usb_hstd_ctsq[ptr->ip]) + { + /* Control Read/Write End */ + usb_hstd_ctrl_end(ptr, (uint16_t) USB_DATA_ERR); + } + + /* WAIT_LOOP */ + for (i = USB_MIN_PIPE_NO; i <= USB_MAX_PIPE_NO; i++) + { + /* Not control transfer */ + /* Agreement device address */ + if (usb_hstd_get_devsel(ptr, i) == addr) + { + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][i]) + { + /* End of data transfer (IN/OUT) */ + usb_hstd_forced_termination(ptr, i, (uint16_t) USB_DATA_STOP); + } + + usb_cstd_clr_pipe_cnfg(ptr, i); + } + } + + usb_hstd_set_dev_addr(ptr, addr, USB_NOCONNECT); + usb_hstd_set_hub_port(ptr, addr, USB_NULL, USB_NULL); + USB_PRINTF1("*** Device address %d clear.\n", md); + } + } + + /* Decide USB Line state (ATTACH) */ + connect_inf = usb_hstd_chk_attach(ptr); + switch (connect_inf) + { + case USB_ATTACHL: + { + usb_hstd_attach(ptr, connect_inf); + break; + } + + case USB_ATTACHF: + { + usb_hstd_attach(ptr, connect_inf); + break; + } + + case USB_DETACH: + { + /* USB detach */ + usb_hstd_detach(ptr); + + #if !defined(USB_CFG_OTG_USE) + + /* Check clock */ + usb_hstd_chk_clk(ptr, (uint16_t) USB_DETACHED); + #endif /* !defined (USB_CFG_OTG_USE) */ + break; + } + + default: + { + /* USB detach */ + usb_hstd_detach(ptr); + + /* Check clock */ + usb_hstd_chk_clk(ptr, (uint16_t) USB_DETACHED); + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_detach_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_read_lnst + * Description : Reads LNST register two times, checks whether these values + * : are equal and returns the value of DVSTCTR register that correspond to + * : the port specified by 2nd argument. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t *buf : Pointer to the buffer to store DVSTCTR register + * Return value : none + * Note : Please change for your SYSTEM + ******************************************************************************/ +void usb_hstd_read_lnst (usb_utr_t * ptr, uint16_t * buf) +{ + /* WAIT_LOOP */ + do + { + buf[0] = hw_usb_read_syssts(ptr); + + /* 30ms wait */ + usb_cpu_delay_xms((uint16_t) 30); + buf[1] = hw_usb_read_syssts(ptr); + if ((buf[0] & USB_LNST) == (buf[1] & USB_LNST)) + { + /* 20ms wait */ + usb_cpu_delay_xms((uint16_t) 20); + buf[1] = hw_usb_read_syssts(ptr); + } + } while ((buf[0] & USB_LNST) != (buf[1] & USB_LNST)); + + buf[1] = hw_usb_read_dvstctr(ptr); +} + +/****************************************************************************** + * End of function usb_hstd_read_lnst + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_attach_process + * Description : Interrupt disable setting when USB Device is attached and + * : handles the required interrupt disable setting etc when USB device + * : is attached. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + * Note : Please change for your SYSTEM + ******************************************************************************/ +void usb_hstd_attach_process (usb_utr_t * ptr) +{ + uint16_t connect_inf; + + /* ATTCH interrupt disable */ + usb_hstd_attch_disable(ptr); + + /* DTCH interrupt disable */ + usb_hstd_dtch_disable(ptr); + usb_hstd_bchg_disable(ptr); + + /* Decide USB Line state (ATTACH) */ + connect_inf = usb_hstd_chk_attach(ptr); + switch (connect_inf) + { + case USB_ATTACHL: + { + usb_hstd_attach(ptr, connect_inf); + break; + } + + case USB_ATTACHF: + { + usb_hstd_attach(ptr, connect_inf); + break; + } + + case USB_DETACH: + { + /* USB detach */ + usb_hstd_detach(ptr); + + /* Check clock */ + usb_hstd_chk_clk(ptr, (uint16_t) USB_DETACHED); + break; + } + + default: + { + usb_hstd_attach(ptr, (uint16_t) USB_ATTACHF); + break; + } + } +} + +/****************************************************************************** + * End of function usb_hstd_attach_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_chk_sof + * Description : Checks whether SOF is sended or not + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_chk_sof (usb_utr_t * ptr) +{ + (void) *ptr; + usb_cpu_delay_1us((uint16_t) 1); /* Wait 640ns */ +} + +/****************************************************************************** + * End of function usb_hstd_chk_sof + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_bus_reset + * Description : Setting USB register when BUS Reset + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_bus_reset (usb_utr_t * ptr) +{ + uint16_t buf; + uint16_t i; + + /* USBRST=1, UACT=0 */ + hw_usb_rmw_dvstctr(ptr, USB_USBRST, (USB_USBRST | USB_UACT)); + + /* Wait 50ms */ + usb_cpu_delay_xms((uint16_t) USB_VALUE_50); + if (USB_IP1 == ptr->ip) + { + /* USBRST=0 */ + hw_usb_clear_dvstctr(ptr, USB_USBRST); /* for UTMI */ + usb_cpu_delay_1us(USB_VALUE_300); /* for UTMI */ + } + + #if defined(USB_CFG_OTG_USE) + hw_usb_clear_hnpbtoa(ptr); + #endif /* defined (USB_CFG_OTG_USE) */ + + /* USBRST=0, RESUME=0, UACT=1 */ + usb_hstd_set_uact(ptr); + + /* Wait 10ms or more (USB reset recovery) */ + usb_cpu_delay_xms((uint16_t) 20); + + buf = USB_HSPROC; + + /* WAIT_LOOP */ + for (i = 0; (i < 3) && (USB_HSPROC == buf); ++i) + { + /* DeviceStateControlRegister - ResetHandshakeStatusCheck */ + buf = hw_usb_read_dvstctr(ptr); + buf = (uint16_t) (buf & USB_RHST); + if (USB_HSPROC == buf) + { + /* Wait */ + usb_cpu_delay_xms((uint16_t) 10); + } + } + + /* 30ms wait */ + usb_cpu_delay_xms((uint16_t) 30); +} + +/****************************************************************************** + * End of function usb_hstd_bus_reset + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_resume_process + * Description : Setting USB register when RESUME signal is detected + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_hstd_resume_process (usb_utr_t * ptr) +{ + usb_hstd_bchg_disable(ptr); + + /* RESUME=1, RWUPE=0 */ + hw_usb_rmw_dvstctr(ptr, USB_RESUME, (USB_RESUME | USB_RWUPE)); + + /* Wait */ + usb_cpu_delay_xms((uint16_t) 20); + + /* USBRST=0, RESUME=0, UACT=1 */ + usb_hstd_set_uact(ptr); + + /* Wait */ + usb_cpu_delay_xms((uint16_t) 5); +} + +/****************************************************************************** + * End of function usb_hstd_resume_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_support_speed_check + * Description : Get USB-speed of the specified port. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : uint16_t : HSCONNECT : Hi-Speed + * : : FSCONNECT : Full-Speed + * : : LSCONNECT : Low-Speed + * : : NOCONNECT : not connect + ******************************************************************************/ +uint16_t usb_hstd_support_speed_check (usb_utr_t * ptr) +{ + uint16_t buf; + uint16_t conn_inf; + + buf = hw_usb_read_dvstctr(ptr); + + /* Reset handshake status get */ + buf = (uint16_t) (buf & USB_RHST); + + switch (buf) + { + /* Get port speed */ + case USB_HSMODE: + { + conn_inf = USB_HSCONNECT; + break; + } + + case USB_FSMODE: + { + conn_inf = USB_FSCONNECT; + break; + } + + case USB_LSMODE: + { + conn_inf = USB_LSCONNECT; + break; + } + + case USB_HSPROC: + { + conn_inf = USB_NOCONNECT; + break; + } + + default: + { + conn_inf = USB_NOCONNECT; + break; + } + } + + return conn_inf; +} + +/****************************************************************************** + * End of function usb_hstd_support_speed_check + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_write_fifo + * Description : Write specified amount of data to specified USB FIFO. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t count : Write size + * : uint16_t pipemode : The mode of CPU/DMA(D0)/DMA(D1). + * : uint16_t *write_p : Address of buffer of data to write. + * Return value : The incremented address of last argument (write_p). + ******************************************************************************/ +uint8_t * usb_hstd_write_fifo (usb_utr_t * ptr, uint16_t count, uint16_t pipemode, uint8_t * write_p) +{ + uint16_t even; + #if defined(USB_HIGH_SPEED_MODULE) + uint16_t odd; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP0 == ptr->ip) + { + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 1); (0 != even); --even) + { + /* 16bit access */ + hw_usb_write_fifo16(ptr, pipemode, *((uint16_t *) write_p)); + + /* Renewal write pointer */ + write_p += sizeof(uint16_t); + } + + if ((count & (uint16_t) 0x0001U) != 0U) + { + /* 8bit access */ + /* count == odd */ + /* Change FIFO access width */ + hw_usb_set_mbw(ptr, pipemode, USB_MBW_8); + + /* FIFO write */ + hw_usb_write_fifo8(ptr, pipemode, *write_p); + + /* Return FIFO access width */ + hw_usb_set_mbw(ptr, pipemode, USB_MBW_16); + + /* Renewal write pointer */ + write_p++; + } + } + else if (USB_IP1 == ptr->ip) + { + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 2); (0 != even); --even) + { + /* 16bit access */ + hw_usb_write_fifo32(ptr, pipemode, *((uint32_t *) write_p)); + + /* Renewal write pointer */ + write_p += sizeof(uint32_t); + } + + odd = count % 4; + if ((odd & (uint16_t) 0x0002U) != 0U) + { + /* 16bit access */ + /* Change FIFO access width */ + hw_usb_set_mbw(ptr, pipemode, USB_MBW_16); + + /* FIFO write */ + hw_usb_write_fifo16(ptr, pipemode, *((uint16_t *) write_p)); + + /* Renewal write pointer */ + write_p += sizeof(uint16_t); + } + + if ((odd & (uint16_t) 0x0001U) != 0U) + { + /* 8bit access */ + /* count == odd */ + /* Change FIFO access width */ + hw_usb_set_mbw(ptr, pipemode, USB_MBW_8); + + /* FIFO write */ + hw_usb_write_fifo8(ptr, pipemode, *write_p); + + /* Renewal write pointer */ + write_p++; + } + + /* Return FIFO access width */ + hw_usb_set_mbw(ptr, pipemode, USB_MBW_32); + } + else + { + /* Non */ + } + + #else /* defined (USB_HIGH_SPEED_MODULE) */ + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 1); (0 != even); --even) + { + /* 16bit access */ + hw_usb_write_fifo16(ptr, pipemode, *((uint16_t *) write_p)); + + /* Renewal write pointer */ + write_p += sizeof(uint16_t); + } + + if ((count & (uint16_t) 0x0001U) != 0U) + { + /* 8bit access */ + /* count == odd */ + /* Change FIFO access width */ + hw_usb_set_mbw(ptr, pipemode, USB_MBW_8); + + /* FIFO write */ + hw_usb_write_fifo8(ptr, pipemode, *write_p); + + /* Return FIFO access width */ + hw_usb_set_mbw(ptr, pipemode, USB_MBW_16); + + /* Renewal write pointer */ + write_p++; + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + return write_p; +} + +/****************************************************************************** + * End of function usb_hstd_write_fifo + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_read_fifo + * Description : Read specified buffer size from the USB FIFO. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t count : Read size + * : uint16_t pipemode : The mode of CPU/DMA(D0)/DMA(D1). + * : uint16_t *read_p : Address of buffer to store the read data + * Return value : Pointer to a buffer that contains the data to be read next. + ******************************************************************************/ +uint8_t * usb_hstd_read_fifo (usb_utr_t * ptr, uint16_t count, uint16_t pipemode, uint8_t * read_p) +{ + uint16_t even; + #if defined(USB_HIGH_SPEED_MODULE) + uint16_t odd; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + uint32_t odd_byte_data_temp; + + #if defined(USB_HIGH_SPEED_MODULE) + #if USB_CFG_ENDIAN == USB_CFG_BIG + uint16_t i; + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP0 == ptr->ip) + { + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 1); (0 != even); --even) + { + /* 16bit FIFO access */ + *(uint16_t *) read_p = hw_usb_read_fifo16(ptr, pipemode); + + /* Renewal read pointer */ + read_p += sizeof(uint16_t); + } + + if ((count & (uint16_t) 0x0001) != 0) + { + /* 16bit FIFO access */ + odd_byte_data_temp = hw_usb_read_fifo16(ptr, pipemode); + + /* Condition compilation by the difference of the little endian */ + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + *read_p = (uint8_t) (odd_byte_data_temp & USB_VALUE_00FFH); + #else /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + *read_p = (uint8_t) (odd_byte_data_temp >> 8); + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + + /* Renewal read pointer */ + read_p += sizeof(uint8_t); + } + } + else if (USB_IP1 == ptr->ip) + { + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 2); (0 != even); --even) + { + /* 32bit FIFO access */ + *(uint32_t *) read_p = hw_usb_read_fifo32(ptr, pipemode); + + /* Renewal read pointer */ + read_p += sizeof(uint32_t); + } + + odd = count % 4; + if (count < 4) + { + odd = count; + } + + if (odd != 0) + { + /* 32bit FIFO access */ + odd_byte_data_temp = hw_usb_read_fifo32(ptr, pipemode); + + /* Condition compilation by the difference of the little endian */ + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + + /* WAIT_LOOP */ + do + { + *read_p = (uint8_t) (odd_byte_data_temp & USB_VALUE_000000FFH); + odd_byte_data_temp = odd_byte_data_temp >> 8; + + /* Renewal read pointer */ + read_p += sizeof(uint8_t); + odd--; + } while (odd != 0); + + #else /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + /* WAIT_LOOP */ + for (i = 0; i < odd; i++) + { + *read_p = (uint8_t) ((odd_byte_data_temp >> (24 - (i * 8))) & 0x000000ff); + + /* Renewal read pointer */ + read_p += sizeof(uint8_t); + } + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + } + } + else + { + /* None */ + } + + #else /* defined (USB_HIGH_SPEED_MODULE) */ + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 1); (0 != even); --even) + { + /* 16bit FIFO access */ + *(uint16_t *) read_p = hw_usb_read_fifo16(ptr, pipemode); + + /* Renewal read pointer */ + read_p += sizeof(uint16_t); + } + + if ((count & (uint16_t) 0x0001) != 0) + { + /* 16bit FIFO access */ + odd_byte_data_temp = hw_usb_read_fifo16(ptr, pipemode); + + /* Condition compilation by the difference of the little endian */ + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + *read_p = (uint8_t) (odd_byte_data_temp & USB_VALUE_00FFH); + #else /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + *read_p = (uint8_t) (odd_byte_data_temp >> 8); + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + + /* Renewal read pointer */ + read_p += sizeof(uint8_t); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + return read_p; +} + +/****************************************************************************** + * End of function usb_hstd_read_fifo + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_forced_termination + * Description : Terminate data transmission and reception. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe Number + * : uint16_t status : Transfer status type + * Return value : none + * Note : In the case of timeout status, it does not call back. + ******************************************************************************/ +void usb_hstd_forced_termination (usb_utr_t * ptr, uint16_t pipe, uint16_t status) +{ + uint16_t buffer; + + /* PID = NAK */ + /* Set NAK */ + usb_cstd_set_nak(ptr, pipe); + + /* Disable Interrupt */ + /* Disable Ready Interrupt */ + hw_usb_clear_brdyenb(ptr, pipe); + + /* Disable Not Ready Interrupt */ + hw_usb_clear_nrdyenb(ptr, pipe); + + /* Disable Empty Interrupt */ + hw_usb_clear_bempenb(ptr, pipe); + + usb_cstd_clr_transaction_counter(ptr, pipe); + + /* Clear CFIFO-port */ + buffer = hw_usb_read_fifosel(ptr, USB_CUSE); + if ((buffer & USB_CURPIPE) == pipe) + { + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, USB_FALSE); + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* Clear D0FIFO-port */ + buffer = hw_usb_read_fifosel(ptr, USB_D0USE); + if ((buffer & USB_CURPIPE) == pipe) + { + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_D0USE, USB_FALSE); + } + + /* Clear D1FIFO-port */ + buffer = hw_usb_read_fifosel(ptr, USB_D1USE); + if ((buffer & USB_CURPIPE) == pipe) + { + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0, (uint16_t) USB_D1USE, USB_FALSE); + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + /* Do Aclr */ + usb_cstd_do_aclrm(ptr, pipe); + + /* FIFO buffer SPLIT transaction initialized */ + hw_usb_set_csclr(ptr, pipe); + + /* Call Back */ + if (USB_NULL != g_p_usb_hstd_pipe[ptr->ip][pipe]) + { + /* Transfer information set */ + g_p_usb_hstd_pipe[ptr->ip][pipe]->tranlen = g_usb_hstd_data_cnt[ptr->ip][pipe]; + g_p_usb_hstd_pipe[ptr->ip][pipe]->status = status; + g_p_usb_hstd_pipe[ptr->ip][pipe]->pipectr = hw_usb_read_pipectr(ptr, pipe); + g_p_usb_hstd_pipe[ptr->ip][pipe]->errcnt = (uint8_t) g_usb_hstd_ignore_cnt[ptr->ip][pipe]; + g_p_usb_hstd_pipe[ptr->ip][pipe]->ipp = ptr->ipp; + g_p_usb_hstd_pipe[ptr->ip][pipe]->ip = ptr->ip; + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + g_p_usb_hstd_pipe[ptr->ip][pipe]->p_transfer_rx = ptr->p_transfer_rx; + g_p_usb_hstd_pipe[ptr->ip][pipe]->p_transfer_tx = ptr->p_transfer_tx; + #endif + + if (USB_NULL != (g_p_usb_hstd_pipe[ptr->ip][pipe]->complete)) + { + (g_p_usb_hstd_pipe[ptr->ip][pipe]->complete)(g_p_usb_hstd_pipe[ptr->ip][pipe], 0, 0); + } + + #if (BSP_CFG_RTOS == 0) + g_p_usb_hstd_pipe[ptr->ip][pipe] = (usb_utr_t *) USB_NULL; + #else /* (BSP_CFG_RTOS == 0) */ + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_hstd_pipe[ptr->ip][pipe]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_hstd_pipe[ptr->ip][pipe]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + g_p_usb_hstd_pipe[ptr->ip][pipe] = (usb_utr_t *) USB_NULL; + usb_cstd_pipe_msg_re_forward(ptr->ip, pipe); /* Get PIPE Transfer wait que and Message send to HCD */ + #endif /* (BSP_CFG_RTOS == 0) */ + } +} + +/****************************************************************************** + * End of function usb_hstd_forced_termination + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_get_usb_ip_adr + * Description : Get base address of the selected USB channel's peripheral + * : registers. + * Argument : uint16_t ipnum : USB_IP0 (0), or USB_IP1 (1). + * Return : usb_regadr_t : A pointer to the USB_597IP register + * : structure USB_REGISTER containing all USB + * : channel's registers. + ******************************************************************************/ +usb_regadr_t usb_hstd_get_usb_ip_adr (uint16_t ipnum) +{ + usb_regadr_t ptr = 0; + + if (USB_IP0 == ipnum) + { + ptr = (usb_regadr_t) R_USB_FS0; + } + + #if USB_NUM_USBIP == 2 + else if (USB_IP1 == ipnum) + { + #if defined(USB_HIGH_SPEED_MODULE) + ptr = (usb_regadr_t) R_USB_HS0; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + #endif /* USB_NUM_USBIP == 2 */ + else + { + USB_DEBUG_HOOK(USB_DEBUG_HOOK_STD | USB_DEBUG_HOOK_CODE1); + } + + return ptr; +} + +/****************************************************************************** + * End of function usb_hstd_get_usb_ip_adr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_hstd_nrdy_endprocess + * Description : NRDY interrupt processing. (Forced termination of data trans- + * : mission and reception of specified pipe.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * : uint16_t pipe : Pipe No + * Return value : none + * Note : none + ******************************************************************************/ +void usb_hstd_nrdy_endprocess (usb_utr_t * ptr, uint16_t pipe) +{ + uint16_t buffer; + + /* + * Host Function + */ + buffer = usb_cstd_get_pid(ptr, pipe); + + /* STALL ? */ + if (USB_PID_STALL == (buffer & USB_PID_STALL)) + { + /*USB_PRINTF1("### STALL Pipe %d\n", pipe);*/ + /* @4 */ + /* End of data transfer */ + usb_hstd_forced_termination(ptr, pipe, USB_DATA_STALL); + } + else + { + /* Wait for About 60ns */ + hw_usb_read_syssts(ptr); + + /* @3 */ + g_usb_hstd_ignore_cnt[ptr->ip][pipe]++; + + /*USB_PRINTF2("### IGNORE Pipe %d is %d times \n", pipe, g_usb_hstd_ignore_cnt[ptr->ip][pipe]);*/ + if (USB_PIPEERROR == g_usb_hstd_ignore_cnt[ptr->ip][pipe]) + { + USB_PRINTF2("###usb_hstd_nrdy_endprocess ignore_cnt:%d pipe:%d\n", + g_usb_hstd_ignore_cnt[ptr->ip][pipe], + pipe); + + /* Data Device Ignore X 3 call back */ + /* End of data transfer */ + usb_hstd_forced_termination(ptr, pipe, USB_DATA_ERR); + } + else + { + /* 5ms wait */ + usb_cpu_delay_xms(5); + + /* PIPEx Data Retry */ + usb_cstd_set_buf(ptr, pipe); + } + } +} + +/****************************************************************************** + * End of function usb_hstd_nrdy_endprocess + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c new file mode 100644 index 0000000000..a32b34964b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c @@ -0,0 +1,1003 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + + #define USB_VALUE_50 (50) + #define USB_VALUE_0F00H (0x0f00) + +/****************************************************************************** + * Function Name : hw_usb_hset_rwupe + * Description : Set the RWUPE-bit specified port's DVSTCTR0 reg- + * : ister. When host. To allow detection of remote wake-up from + * : a USB Function. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_rwupe (usb_utr_t * ptr) +{ + ptr->ipp->DVSTCTR0 |= USB_RWUPE; +} + +/****************************************************************************** + * End of function hw_usb_hset_rwupe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_rwupe + * Description : Clear the RWUPE-bit specified port's DVSTCTR0 reg- + * : ister. When host. To prohibit detection of remote wake-up from + * : a USB Function. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_rwupe (usb_utr_t * ptr) +{ + ptr->ipp->DVSTCTR0 = (uint16_t) (ptr->ipp->DVSTCTR0 & (~USB_RWUPE)); +} + +/****************************************************************************** + * End of function hw_usb_hclear_rwupe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_resume + * Description : Set the RESUME-bit specified port's DVSTCTR0 register + * : When host. To allow output of resume signal to a USB Function. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_resume (usb_utr_t * ptr) +{ + ptr->ipp->DVSTCTR0 |= USB_RESUME; +} + +/****************************************************************************** + * End of function hw_usb_hset_resume + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_resume + * Description : Clear the RESUME-bit specified port's DVSTCTR0 register + * : When host. To prohibit output of resume signal to a USB Func- + * : tion. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_resume (usb_utr_t * ptr) +{ + ptr->ipp->DVSTCTR0 = (uint16_t) (ptr->ipp->DVSTCTR0 & (~USB_RESUME)); +} + +/****************************************************************************** + * End of function hw_usb_hset_uact + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_uact + * Description : Set UACT-bit (USB Bus Enable) specified port's DVSTCTR0 + * : register. When Host, to output SOF. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_uact (usb_utr_t * ptr) +{ + ptr->ipp->DVSTCTR0 |= USB_UACT; +} + +/****************************************************************************** + * End of function hw_usb_hset_uact + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_uact + * Description : Clear UACT-bit (USB Bus Enable) specified port's DVSTCTR0 + * : register. When Host, to prohibit output SOF. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_uact (usb_utr_t * ptr) +{ + ptr->ipp->DVSTCTR0 = (uint16_t) (ptr->ipp->DVSTCTR0 & (~USB_UACT)); +} + +/****************************************************************************** + * End of function hw_usb_hclear_uact + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hwrite_intenb + * Description : Write the specified data to the specified port's INTENB register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_hwrite_intenb (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->INTENB1 = data; +} + +/****************************************************************************** + * End of function hw_usb_hwrite_intenb + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_enb_ovrcre + * Description : Set specified port's OVRCRE-bit (Overcurrent Input Change Int- + * : errupt Status Enable) in the INTENB1 register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_enb_ovrcre (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 |= USB_OVRCRE; +} + +/****************************************************************************** + * End of function hw_usb_hset_enb_ovrcre + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_enb_ovrcre + * Description : Clear the OVRCRE-bit of the specified port's INTENB1 register, + * : to prohibit VBUS interrupts. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_enb_ovrcre (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 = (uint16_t) (ptr->ipp->INTENB1 & (~USB_OVRCRE)); +} + +/****************************************************************************** + * End of function hw_usb_hclear_enb_ovrcre + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_enb_bchge + * Description : The BCHGE-bit (USB Bus Change Interrupt Enable) is set in the + * : specified port's INTENB1 register. This will cause a BCHG + * : interrupt when a change of USB bus state has been detected. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_enb_bchge (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 |= USB_BCHGE; +} + +/****************************************************************************** + * End of function hw_usb_hset_enb_bchge + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_enb_bchge + * Description : The BCHGE-bit (USB Bus Change Interrupt Enable) is cleared in + * : the specified port's INTENB1 register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_enb_bchge (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 = (uint16_t) (ptr->ipp->INTENB1 & (~USB_BCHGE)); +} + +/****************************************************************************** + * End of function hw_usb_hclear_enb_bchge + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_enb_dtche + * Description : Enable the specified port's DTCHE-interrupt "Disconnection + * : Detection" by setting the DTCHE-bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_enb_dtche (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 |= USB_DTCHE; +} + +/****************************************************************************** + * End of function hw_usb_hset_enb_dtche + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_enb_dtche + * Description : Disable the specified port's DTCHE-interrupt "Disconnection + * : Detection" by clearing the DTCHE-bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_enb_dtche (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 = (uint16_t) (ptr->ipp->INTENB1 & (~USB_DTCHE)); +} + +/****************************************************************************** + * End of function hw_usb_hclear_enb_dtche + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_enb_attche + * Description : Enable the specified port's ATTCHE-interrupt "Connection + * : Detection" by setting the ATTCHE-bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_enb_attche (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 |= USB_ATTCHE; +} + +/****************************************************************************** + * End of function hw_usb_hset_enb_attche + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_enb_attche + * Description : Disable the specified port's ATTCHE-interrupt "Disconnection + * : Detection" by clearing the ATTCHE-bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_enb_attche (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 = (uint16_t) (ptr->ipp->INTENB1 & (~USB_ATTCHE)); +} + +/****************************************************************************** + * End of function hw_usb_hclear_enb_attche + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_enb_signe + * Description : Enable the SIGNE-interrupt "Setup Transaction + * : Error" by setting the SIGNE-bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_enb_signe (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 |= USB_SIGNE; +} + +/****************************************************************************** + * End of function hw_usb_hset_enb_signe + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_enb_sacke + * Description : Enable the SACKE-interrupt "Setup Transaction + * : Normal Response" by setting the SACKE-bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_enb_sacke (usb_utr_t * ptr) +{ + ptr->ipp->INTENB1 |= USB_SACKE; +} + +/****************************************************************************** + * End of function hw_usb_hset_enb_sacke + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_enb_pddetinte + * Description : Enable the PDDETINT-interrupt "Connection Detection for + * : Battery Charging Supporting Device" by setting + * : the PDDETINTE-bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_enb_pddetinte (usb_utr_t * ptr) +{ + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + ptr->ipp1->INTENB1 |= USB_PDDETINTE; + } + #else /* defined (USB_HIGH_SPEED_MODULE) */ + (void) *ptr; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ +} + +/****************************************************************************** + * End of function hw_usb_hset_enb_pddetinte + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hwrite_intsts + * Description : Write the specified data to the specified port's INTSTS1 reg- + * : ister. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_hwrite_intsts (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->INTSTS1 = data; +} + +/****************************************************************************** + * End of function hw_usb_hwrite_intsts + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_sts_ovrcr + * Description : Clear the specified port's OVRCR-bit; "Overcurrent + * : Input Change Interrupt Status". + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_sts_ovrcr (usb_utr_t * ptr) +{ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_OVRCR) & INTSTS1_MASK); +} + +/****************************************************************************** + * End of function hw_usb_hclear_sts_ovrcr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_sts_bchg + * Description : Clear the specified port's BCHG-bit; "USB Bus Change Interrupt + * : Status". + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_sts_bchg (usb_utr_t * ptr) +{ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_BCHG) & INTSTS1_MASK); +} /* End of function hw_usb_hclear_sts_bchg() */ + +/****************************************************************************** + * End of function hw_usb_hclear_sts_bchg + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_sts_dtch + * Description : Clear the specified port's DTCH-bit; "USB Disconnection Detec- + * : tion Interrupt Status". + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_sts_dtch (usb_utr_t * ptr) +{ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_DTCH) & INTSTS1_MASK); +} + +/****************************************************************************** + * End of function hw_usb_hclear_sts_dtch + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_sts_attch + * Description : Clear the specified port's ATTCH-bit; "ATTCH Interrupt Status". + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_sts_attch (usb_utr_t * ptr) +{ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_ATTCH) & INTSTS1_MASK); +} + +/****************************************************************************** + * End of function hw_usb_hclear_sts_attch + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_sts_sign + * Description : Clear the SIGN-bit; "Setup Transaction Error + * : Interrupt Status". + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_sts_sign (usb_utr_t * ptr) +{ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_SIGN) & INTSTS1_MASK); +} + +/****************************************************************************** + * End of function hw_usb_hclear_sts_sign + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_sts_sack + * Description : Clear the SACK-bit; "Setup Transaction Normal + * : Response Interrupt Status". + * : Interrupt Status". + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_sts_sack (usb_utr_t * ptr) +{ + ptr->ipp->INTSTS1 = (uint16_t) ((~USB_SACK) & INTSTS1_MASK); +} + +/****************************************************************************** + * End of function hw_usb_hclear_sts_sack + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hclear_sts_pddetint + * Description : Clear the PDDETINT-bit; " + * : ". + * : Interrupt Status". + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hclear_sts_pddetint (usb_utr_t * ptr) +{ + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + ptr->ipp1->INTSTS1 = (uint16_t) ((~USB_PDDETINT) & INTSTS1_MASK); + } + #else /* defined (USB_HIGH_SPEED_MODULE) */ + (void) *ptr; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ +} + +/****************************************************************************** + * End of function hw_usb_hclear_sts_pddetint + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hwrite_usbreq + * Description : Write bRequest and bmRequestType to USBREQ register. + * : When Host, the values of bRequest and bmRequestType + * : to be transmitted are written. (When Function, the received + * : values of bRequest and bmRequestType are stored in USBREQ). + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_hwrite_usbreq (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->USBREQ = data; +} + +/****************************************************************************** + * End of function hw_usb_hwrite_usbreq + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_usbval + * Description : Write the specified 'wValue' to USBVAL register, + * : to write the USB request. When Host, the value of + * : wValue to be transmitted is set. (When Function, the value of + * : wValue that has been received is stored in USBREQ.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_hset_usbval (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->USBVAL = data; +} + +/****************************************************************************** + * End of function hw_usb_hset_usbval + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_usbindx + * Description : Write the specified 'wIndex', the USB request, to USBINDX + * : register, for host setup requests for control + * : transfers. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_hset_usbindx (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->USBINDX = data; +} + +/****************************************************************************** + * End of function hw_usb_hset_usbindx + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_usbleng + * Description : Write the specified 'wLength' value to USBINDX register, + * : for host setup requests for control. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_hset_usbleng (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->USBLENG = data; +} + +/****************************************************************************** + * End of function hw_usb_hset_usbleng + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hwrite_dcpctr + * Description : Write the specified data value to the DCPCTR register. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t data : Setting value + * Return value : none + ******************************************************************************/ +void hw_usb_hwrite_dcpctr (usb_utr_t * ptr, uint16_t data) +{ + ptr->ipp->DCPCTR = data; +} + +/****************************************************************************** + * End of function hw_usb_hwrite_dcpctr + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_sureq + * Description : Set SUREQ-bit in the DCPCTR register + * : (Set SETUP packet send when HostController function is selected) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_sureq (usb_utr_t * ptr) +{ + ptr->ipp->DCPCTR |= USB_SUREQ; +} + +/****************************************************************************** + * End of function hw_usb_hset_sureq + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hread_devadd + * Description : Return the DEVADD register value for the specified USB device + * ; address. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t devsel : USB device address value + * Return value : DEVADDx content + ******************************************************************************/ +uint16_t hw_usb_hread_devadd (usb_utr_t * ptr, uint16_t devsel) +{ + volatile uint16_t * preg; + uint16_t devadr; + uint16_t return_value; + uint16_t result; + + devadr = devsel >> USB_DEVADDRBIT; + + if (devadr > USB_MAXDEVADDR) + { + USB_PRINTF1("### hw_usb_hread_devadd USB_MAXDEVADDR (%d)\n", devadr); + result = USB_ERROR; + } + else + { + preg = (uint16_t *) &(ptr->ipp->DEVADD[0]) + devadr; + return_value = ((*preg) & ((USB_UPPHUB | USB_HUBPORT) | USB_USBSPD)); + result = return_value; + } + + return result; +} + +/****************************************************************************** + * End of function hw_usb_hread_devadd + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hrmw_devadd + * Description : Read-modify-write the specified devsel's DEVADD. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t devsel : USB device address value + * : uint16_t data : The value to write. + * : uint16_t width : Bit pattern to read-modify-write. + * Return value : none + ******************************************************************************/ +void hw_usb_hrmw_devadd (usb_utr_t * ptr, uint16_t devsel, uint16_t data, uint16_t width) +{ + volatile uint16_t * preg; + uint16_t buf; + uint16_t devadr; + + devadr = devsel >> USB_DEVADDRBIT; + + preg = (uint16_t *) &(ptr->ipp->DEVADD[0]) + devadr; + + buf = *preg; + buf = (uint16_t) (buf & (~width)); + buf |= (data & width); + *preg = buf; +} + +/****************************************************************************** + * End of function hw_usb_hrmw_devadd + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_usbspd + * Description : Set the DEVADD register's USBSPD for the specified device add- + * : ress. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * : uint16_t devsel : USB device address value + * : uint16_t data : The value to write. + * Return value : none + ******************************************************************************/ +void hw_usb_hset_usbspd (usb_utr_t * ptr, uint16_t devsel, uint16_t data) +{ + volatile uint16_t * preg; + uint16_t devadr; + + devadr = devsel >> USB_DEVADDRBIT; + + preg = (uint16_t *) &(ptr->ipp->DEVADD[0]) + devadr; + + (*preg) = (uint16_t) ((*preg) & (~USB_USBSPD)); + (*preg) = (uint16_t) ((*preg) | data); +} + +/****************************************************************************** + * End of function hw_usb_hset_usbspd + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_dcpmode + * Description : Set DCPMODE bit. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_dcpmode (usb_utr_t * ptr) +{ + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + ptr->ipp1->BCCTRL |= USB_DCPMODE; + } + #else /* defined (USB_HIGH_SPEED_MODULE) */ + (void) *ptr; + #endif/* defined (USB_HIGH_SPEED_MODULE) */ +} + +/****************************************************************************** + * End of function hw_usb_hset_dcpmode + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hmodule_otg_init + * Description : USB OTG module initialization for USB Host mode + * Arguments : uint8_t usb_ip : USB module number + * Return value : none + ******************************************************************************/ +void hw_usb_hmodule_otg_init (uint8_t usb_ip) +{ + if (USB_IP0 == usb_ip) + { + USB_M0->DVSTCTR0 |= USB_USBRST; + usb_cpu_delay_xms((uint16_t) USB_VALUE_50); /* Need to wait greater equal 10ms in USB spec */ + USB_M0->DVSTCTR0 = (uint16_t) (USB_M0->DVSTCTR0 & (~USB_USBRST)); + + /* WAIT_LOOP */ + while (USB_HSPROC == (USB_M0->DVSTCTR0 & USB_HSPROC)) + { + /* HSPROC = 0100b */ + } + + USB_M0->DVSTCTR0 |= USB_UACT; + + USB_M0->INTSTS1 &= ((~USB_OVRCRE) & INTSTS1_MASK); + USB_M0->INTENB1 |= (USB_OVRCRE); + } + else + { + USB_M1->DVSTCTR0 |= USB_USBRST; + + usb_cpu_delay_xms((uint16_t) USB_VALUE_50); /* Need to wait greater equal 10ms in USB spec */ + + USB_M1->DVSTCTR0 = (uint16_t) (USB_M1->DVSTCTR0 & (~USB_USBRST)); + + /* WAIT_LOOP */ + while (USB_HSPROC == (USB_M1->DVSTCTR0 & USB_HSPROC)) + { + /* Wait for USB reset handshake in progress */ + } + + USB_M1->DVSTCTR0 |= USB_UACT; + + USB_M1->INTSTS1 &= (~USB_OVRCRE & INTSTS1_MASK); + USB_M1->INTENB1 |= (USB_OVRCRE); + } +} + +/****************************************************************************** + * End of function hw_usb_hmodule_otg_init + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hmodule_init + * Description : USB module initialization for USB Host mode + * Arguments : uint8_t usb_ip : USB module number + * Return value : none + ******************************************************************************/ +void hw_usb_hmodule_init (uint8_t usb_ip) +{ + uint16_t sts; + + if (USB_IP0 == usb_ip) + { + USB_M0->SYSCFG |= USB_SCKE; + + /* WAIT_LOOP */ + while (USB_SCKE != (USB_M0->SYSCFG & USB_SCKE)) + { + /* none */ + } + + #if defined(USB_SUPPORT_PHYSLEW) + USB_M0->PHYSLEW = USB_PHYSLEW_VALUE; + #endif /* defined(USB_SUPPORT_PHYSLEW) */ + + USB_M0->SYSCFG |= USB_DCFM; + + USB_M0->SYSCFG |= USB_DRPD; + + USB_M0->SYSCFG &= (uint16_t) ~USB_DPRPU; + + sts = usb_chattaring((uint16_t *) &USB_M0->SYSSTS0); + + USB_M0->SYSCFG |= USB_USBE; + + #if defined(USB_SUPPORT_HOCO_MODULE) + if (0 == (R_SYSTEM->SCKSCR & R_SYSTEM_SCKSCR_CKSEL_Msk)) + { + /* Use HOCO */ + hw_usb_set_uckselc(); + } + #endif /* defined(USB_SUPPORT_HOCO_MODULE) */ + + USB_M0->CFIFOSEL = USB0_CFIFO_MBW; + USB_M0->D0FIFOSEL = USB0_D0FIFO_MBW; + USB_M0->D1FIFOSEL = USB0_D1FIFO_MBW; + + #if USB_CFG_ENDIAN == USB_CFG_BIG + USB_M0->CFIFOSEL |= USB_BIGEND; + USB_M0->D0FIFOSEL |= USB_BIGEND; + USB_M0->D1FIFOSEL |= USB_BIGEND; + #endif /* USB_CFG_ENDIAN == USB_CFG_BIG */ + + switch (sts) + { + case USB_FS_JSTS: /* USB device already connected */ + case USB_LS_JSTS: + { + USB_M0->DVSTCTR0 |= USB_USBRST; + usb_cpu_delay_xms((uint16_t) USB_VALUE_50); /* Need to wait greater equal 10ms in USB spec */ + USB_M0->DVSTCTR0 = (uint16_t) (USB_M0->DVSTCTR0 & (~USB_USBRST)); + + /* WAIT_LOOP */ + while (USB_HSPROC == (USB_M0->DVSTCTR0 & USB_HSPROC)) + { + /* HSPROC = 0100b */ + } + + if (USB_LSMODE == (USB_M0->DVSTCTR0 & USB_RHST)) + { + USB_M0->SOFCFG |= USB_TRNENSEL; + } + + USB_M0->DVSTCTR0 |= USB_UACT; + break; + } + + case USB_SE0: /* USB device no connected */ + { + #if !defined(USB_CFG_OTG_USE) + USB_M0->INTENB1 = USB_ATTCH; + #endif /* !defined (USB_CFG_OTG_USE) */ + break; + } + + default: + { + break; + } + } + + /* + * When R_USB_Open function was called immediately after calling R_USB_Close function, + * D+ line keeps High level since VBUS shifts to High level before USB Periheral Device recognizes VBUS Low, + * The Attach interrupt is genrated since D+ line keeps High level. + * When "INTSTS1 = 0" is described code, the Attach interrupt is canceled. "INTSTS1 = 0" is NG. + * The following code(INTSTS1) is correct. + */ + USB_M0->INTSTS1 = ((~USB_OVRCRE) & INTSTS1_MASK); + + USB_M0->INTENB0 = ((USB_BEMPE | USB_NRDYE) | USB_BRDYE); + #if !defined(USB_CFG_OTG_USE) + USB_M0->INTENB1 = (USB_OVRCRE | USB_ATTCH); + #endif /* !defined (USB_CFG_OTG_USE) */ + } + + #if USB_NUM_USBIP == 2 + else + { + #if defined(USB_HIGH_SPEED_MODULE) + USB_M1->PHYSET |= (USB_DIRPD | USB_CLKSEL); + + #if USB_CFG_CLKSEL == USB_CFG_OTHER + USB_M1->PHYSET |= USB_HSEB; + #else /* USB_CFG_CLKSEL == USB_CFG_OTHER */ + #if USB_USBMCLK_HZ == USB_CLK_48MHZ + USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; + USB_M1->PHYSET |= USB_CLKSEL_48; + #endif /* USB_USBMCLK_HZ == USB_CLK_48MHZ */ + + #if USB_USBMCLK_HZ == USB_CLK_24MHZ + USB_M1->PHYSET &= (uint16_t) ~USB_HSEB; + #endif /* USB_USBMCLK_HZ == USB_CLK_24MHZ */ + + #if USB_USBMCLK_HZ == USB_CLK_20MHZ + USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; + USB_M1->PHYSET |= USB_CLKSEL_20; + #endif /* USB_USBMCLK_HZ == USB_CLK_20MHZ */ + + #if USB_USBMCLK_HZ == USB_CLK_12MHZ + USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; + USB_M1->PHYSET |= USB_CLKSEL_12; + #endif /* USB_USBMCLK_HZ == USB_CLK_12MHZ */ + + USB_M1->PHYSET |= USB_REPSEL_16; + #endif /* USB_CFG_CLKSEL == USB_CFG_OTHER */ + + usb_cpu_delay_1us((uint16_t) 1); /* wait 1usec */ + + USB_M1->PHYSET = (uint16_t) (USB_M1->PHYSET & (~USB_DIRPD)); + usb_cpu_delay_xms(1); /* wait 1msec */ + + #if USB_CFG_CLKSEL != USB_CFG_OTHER + USB_M1->PHYSET = (uint16_t) (USB_M1->PHYSET & (~USB_PLLRESET)); + #endif /* USB_CFG_CLKSEL != USB_CFG_OTHER */ + + USB_M1->LPSTS |= USB_SUSPENDM; + + #if USB_CFG_CLKSEL != USB_CFG_OTHER + + /* WAIT_LOOP */ + while (USB_PLLLOCK != (USB_M1->PLLSTA & USB_PLLLOCK)) + { + /* Wait for PLL Lock */ + } + ; + #endif /* USB_CFG_CLKSEL != USB_CFG_OTHER */ + + USB_M1->SYSCFG |= USB_DCFM; + + USB_M1->SYSCFG |= USB_DRPD; + + USB_M1->SYSCFG &= (uint16_t) (~(uint16_t) USB_DPRPU); + + USB_M1->SYSCFG |= USB_CNEN; + + USB_M1->BUSWAIT = (USB_CFG_BUSWAIT | USB_VALUE_0F00H); + usb_cpu_delay_1us((uint16_t) 1); /* wait 1usec */ + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + USB_M1->SOFCFG |= USB_INTL; + +// sts = usb_chattaring((uint16_t *) &USB_M1->SYSCFG); + sts = usb_chattaring((uint16_t *) &USB_M1->SYSSTS0); + + USB_M1->SYSCFG |= USB_USBE; + + USB_M1->CFIFOSEL = USB1_CFIFO_MBW; + USB_M1->D0FIFOSEL = USB1_D0FIFO_MBW; + USB_M1->D1FIFOSEL = USB1_D1FIFO_MBW; + + #if USB_CFG_ENDIAN == USB_CFG_BIG + USB_M1->CFIFOSEL |= USB_BIGEND; + USB_M1->D0FIFOSEL |= USB_BIGEND; + USB_M1->D1FIFOSEL |= USB_BIGEND; + #endif + + switch (sts) + { + case USB_FS_JSTS: /* USB device already connected */ + case USB_LS_JSTS: + { + USB_M1->DVSTCTR0 |= USB_USBRST; + + usb_cpu_delay_xms((uint16_t) USB_VALUE_50); /* Need to wait greater equal 10ms in USB spec */ + + USB_M1->DVSTCTR0 = (uint16_t) (USB_M1->DVSTCTR0 & (~USB_USBRST)); + + /* WAIT_LOOP */ + while (USB_HSPROC == (USB_M1->DVSTCTR0 & USB_HSPROC)) + { + /* Wait for USB reset handshake in progress */ + } + + ; + + if (USB_LSMODE == (USB_M1->DVSTCTR0 & USB_RHST)) + { + USB_M1->SOFCFG |= USB_TRNENSEL; + } + + USB_M1->DVSTCTR0 |= USB_UACT; + break; + } + + case USB_SE0: /* USB device no connected */ + { + #if defined(USB_HIGH_SPEED_MODULE) + USB_M1->INTENB1 = USB_ATTCH; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + default: + { + break; + } + } + + /* + * When R_USB_Open function was called immediately after calling R_USB_Close function, + * D+ line keeps High level since VBUS shifts to High level before USB Periheral Device recognizes VBUS Low, + * The Attach interrupt is genrated since D+ line keeps High level. + * When "INTSTS1 = 0" is described code, the Attach interrupt is canceled. "INTSTS1 = 0" is NG. + * The following code(INTSTS1) is correct. + */ + USB_M1->INTSTS1 = (~USB_OVRCRE & INTSTS1_MASK); + + USB_M1->INTENB0 = (USB_BEMPE | USB_NRDYE | USB_BRDYE); + #if defined(USB_HIGH_SPEED_MODULE) + USB_M1->INTENB1 = (USB_OVRCRE | USB_ATTCH); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + #endif /* USB_NUM_USBIP == 2 */ + + #if (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) + hw_usb_set_vdcen(); + #endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ +} + +/****************************************************************************** + * End of function hw_usb_hmodule_init + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_hset_trnensel + * Description : When host, set the TRNENSEL-bit; "Transac- + * : tion-Enabled Time Select" for low-speed USB communication. + * : This bit should be set to 0 if USB Function. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : none + ******************************************************************************/ +void hw_usb_hset_trnensel (usb_utr_t * ptr) +{ + ptr->ipp->SOFCFG |= USB_TRNENSEL; +} + +/****************************************************************************** + * End of function hw_usb_hset_trnensel + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c new file mode 100644 index 0000000000..90e2cf0a64 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c @@ -0,0 +1,1140 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" + +#if (BSP_CFG_RTOS == 1) + #include "../driver/inc/r_usb_cstd_rtos.h" + #if defined(USB_CFG_OTG_USE) + #include "ux_api.h" + #endif /* defined(USB_CFG_OTG_USE) */ +#endif /* #if (BSP_CFG_RTOS == 1) */ + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + #include "inc/r_usb_dmac.h" +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +#if defined(USB_CFG_HHID_USE) || defined(USB_CFG_PHID_USE) + #if USB_CFG_DTC == USB_CFG_ENABLE + #error In HID class, can not set USB_CFG_ENABLE to USB_CFG_DTC in r_usb_basic_cfg.h. + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + +#endif /* defined(USB_CFG_HHID_USE) || defined(USB_CFG_PHID_USE) */ + +#if USB_CFG_COMPLIANCE == USB_CFG_DISABLE + #if USB_CFG_ELECTRICAL == USB_CFG_ENABLE + #error Can not set USB_CFG_DISABLE to USB_CFG_COMPLIANCE when setting USB_CFG_ENABLE to USB_CFG_ELECTRICAL \ + in r_usb_basic_cfg.h. + + #endif /* USB_CFG_ELECTRICAL == USB_CFG_ENABLE */ +#endif /* USB_CFG_COMPLIANCE == USB_CFG_DISABLE */ + +#if USB_CFG_BC == USB_CFG_DISABLE + #if USB_CFG_DCP == USB_CFG_ENABLE + #error Can not set USB_CFG_DISABLE to USB_CFG_BC when setting USB_CFG_ENABLE to USB_CFG_DCP \ + in r_usb_basic_cfg.h. + + #endif /* USB_CFG_DCP == USB_CFG_ENABLE */ +#endif /* USB_CFG_BC == USB_CFG_DISABLE */ + +#if USB_CFG_DMA == USB_CFG_ENABLE + #if USB_CFG_DTC == USB_CFG_ENABLE + #error Can not set USB_CFG_ENABLE to the definitions (USB_CFG_DMA and USB_CFG_DTC) at the same time \ + in r_usb_basic_cfg.h. + + #endif /* USB_CFG_DTC == USB_CFG_ENABLE */ +#endif /* USB_CFG_DMA == USB_CFG_ENABLE */ + +#if !defined(USB_CFG_OTG_USE) + #if USB_CFG_MODE == USB_CFG_HOST + #if defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE) || defined(USB_CFG_PHID_USE) || \ + defined(USB_CFG_PMSC_USE) || defined(USB_CFG_PVND_USE) + #error \ + Can not enable these definitions(USB_CFG_PCDC_USE/USB_CFG_PPRN_USE/USB_CFG_PHID_USE/USB_CFG_PMSC_USE/USB_CFG_PVND_USE) \ + when setting USB_MODE_HOST to USB_CFG_MODE in r_usb_basic_cfg.h. + + #endif /* defined(USB_CFG_PCDC_USE || USB_CFG_PPRN_USE || USB_CFG_PHID_USE || USB_CFG_PMSC_USE || USB_CFG_PVND_USE) */ + #endif /* USB_CFG_MODE == USB_MODE_HOST */ + + #if USB_CFG_MODE == USB_CFG_PERI + #if defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HMSC_USE) || defined(USB_CFG_HVND_USE) + #error Can not enable these definitions(USB_CFG_HCDC_USE/USB_CFG_HHID_USE/USB_CFG_HMSC_USE/USB_CFG_HVND_USE) \ + when setting USB_MODE_PERI to USB_CFG_MODE in r_usb_basic_cfg.h. + + #endif /* defined(USB_CFG_HCDC_USE || USB_CFG_HHID_USE || USB_CFG_HMSC_USE || USB_CFG_HVND_USE) */ + #endif /* USB_CFG_MODE == USB_MODE_PERI */ +#endif /* !defined(USB_CFG_OTG_USE) */ + +#if (!defined(USB_HIGH_SPEED_MODULE)) + #if USB_CFG_ELECTRICAL == USB_CFG_ENABLE + #error Can not set USB_CFG_ENABLE to USB_CFG_ELECTRICAL when using other than Hi-speed module in r_usb_basic_cfg.h. + #endif /* USB_CFG_ELECTRICAL == USB_CFG_ENABLE */ + +#endif /* (!defined(USB_HIGH_SPEED_MODULE)) */ + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +static usb_cfg_t * g_p_usb_cfg_ip0; + #if defined(USB_HIGH_SPEED_MODULE) +static usb_cfg_t * g_p_usb_cfg_ip1; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ +#endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + +/****************************************************************************** + * Private global variables and functions + ******************************************************************************/ +void usbfs_interrupt_handler(void); +void usbfs_resume_handler(void); +void usbfs_d0fifo_handler(void); +void usbfs_d1fifo_handler(void); +void usbhs_interrupt_handler(void); +void usbhs_d0fifo_handler(void); +void usbhs_d1fifo_handler(void); + +#if defined(USB_CFG_OTG_USE) +static usb_utr_t g_usb_irq_otg_msg; +static usb_utr_t g_usb_otg_detach_msg; +static uint16_t g_usb_otg_frmnum_prev = 0; +volatile uint8_t g_usb_otg_chattering_counter = 0; +volatile uint8_t g_usb_otg_hnp_counter = 0; +#endif /* defined(USB_CFG_OTG_USE) */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +static uint16_t g_usb_hstd_m0_reg_intenb0; +static uint16_t g_usb_hstd_m0_reg_intenb1; + #if defined(USB_HIGH_SPEED_MODULE) +static uint16_t g_usb_hstd_m1_reg_intenb0; +static uint16_t g_usb_hstd_m1_reg_intenb1; + #endif /* defined(USB_HIGH_SPEED_MODULE) */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/****************************************************************************** + * Renesas Abstracted RSK functions + ******************************************************************************/ + +/**************************************************************************//** + * @brief This function stops USB module. + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_BUSY USB is in use. + ******************************************************************************/ +fsp_err_t usb_module_start (uint8_t ip_type) +{ + if (USB_IP0 == ip_type) + { + FSP_ERROR_RETURN(0 != R_MSTP->MSTPCRB_b.MSTPB11, FSP_ERR_USB_BUSY) + + /* Enable power for USB0 */ + R_BSP_MODULE_START(FSP_IP_USBFS, 0); + } + else + { +#if defined(USB_HIGH_SPEED_MODULE) + FSP_ERROR_RETURN(0 != R_MSTP->MSTPCRB_b.MSTPB12, FSP_ERR_USB_BUSY) + + /* Enable power for USBA */ + R_BSP_MODULE_START(FSP_IP_USBHS, 0); +#else /* defined (USB_HIGH_SPEED_MODULE) */ + FSP_ERROR_RETURN(0 != R_MSTP->MSTPCRB_b.MSTPB12, FSP_ERR_USB_BUSY) + + /* Enable power for USBA */ + R_BSP_MODULE_START(FSP_IP_USBFS, 0); +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + + return FSP_SUCCESS; +} + +/****************************************************************************** + * End of function usb_module_start + ******************************************************************************/ + +/**************************************************************************//** + * @brief This function clear USB module register. + * + * @retval FSP_SUCCESS Success. + ******************************************************************************/ +fsp_err_t usb_module_register_clear (uint8_t usb_ip) +{ + if (USB_IP0 == usb_ip) + { +#if defined(USB_CFG_OTG_USE) + USB_M0->DVSTCTR0 = (uint16_t) (USB_M0->DVSTCTR0 & (USB_EXICEN | USB_VBUSEN)); + USB_M0->DCPCTR = USB_SQSET; + USB_M0->PIPE_CTR[0] = 0; + USB_M0->PIPE_CTR[1] = 0; + USB_M0->PIPE_CTR[2] = 0; + USB_M0->PIPE_CTR[3] = 0; + USB_M0->PIPE_CTR[4] = 0; + USB_M0->PIPE_CTR[5] = 0; + USB_M0->PIPE_CTR[6] = 0; + USB_M0->PIPE_CTR[7] = 0; + USB_M0->PIPE_CTR[8] = 0; + USB_M0->BRDYENB = 0; + USB_M0->NRDYENB = 0; + USB_M0->BEMPENB = 0; + USB_M0->INTENB0 = 0; + USB_M0->INTENB1 = 0; + USB_M0->BRDYSTS = 0; + USB_M0->NRDYSTS = 0; + USB_M0->BEMPSTS = 0; +#else /* defined(USB_CFG_OTG_USE) */ + USB_M0->DVSTCTR0 = 0; + USB_M0->DCPCTR = USB_SQSET; + USB_M0->PIPE_CTR[0] = 0; + USB_M0->PIPE_CTR[1] = 0; + USB_M0->PIPE_CTR[2] = 0; + USB_M0->PIPE_CTR[3] = 0; + USB_M0->PIPE_CTR[4] = 0; + USB_M0->PIPE_CTR[5] = 0; + USB_M0->PIPE_CTR[6] = 0; + USB_M0->PIPE_CTR[7] = 0; + USB_M0->PIPE_CTR[8] = 0; + USB_M0->BRDYENB = 0; + USB_M0->NRDYENB = 0; + USB_M0->BEMPENB = 0; + USB_M0->INTENB0 = 0; + USB_M0->INTENB1 = 0; + USB_M0->BRDYSTS = 0; + USB_M0->NRDYSTS = 0; + USB_M0->BEMPSTS = 0; + USB_M0->SYSCFG = (uint16_t) (USB_M0->SYSCFG & (~USB_DPRPU)); + USB_M0->SYSCFG = (uint16_t) (USB_M0->SYSCFG & (~USB_DRPD)); + USB_M0->SYSCFG = (uint16_t) (USB_M0->SYSCFG & (~USB_DCFM)); + USB_M0->SYSCFG = (uint16_t) (USB_M0->SYSCFG & (~USB_USBE)); +#endif /* defined(USB_CFG_OTG_USE) */ + } + else + { +#if defined(USB_CFG_OTG_USE) + USB_M1->DVSTCTR0 = (uint16_t) (USB_M0->DVSTCTR0 & (USB_EXICEN | USB_VBUSEN)); + USB_M1->DCPCTR = USB_SQSET; + USB_M1->PIPE_CTR[0] = 0; + USB_M1->PIPE_CTR[1] = 0; + USB_M1->PIPE_CTR[2] = 0; + USB_M1->PIPE_CTR[3] = 0; + USB_M1->PIPE_CTR[4] = 0; + USB_M1->PIPE_CTR[5] = 0; + USB_M1->PIPE_CTR[6] = 0; + USB_M1->PIPE_CTR[7] = 0; + USB_M1->PIPE_CTR[8] = 0; + USB_M1->BRDYENB = 0; + USB_M1->NRDYENB = 0; + USB_M1->BEMPENB = 0; + USB_M1->INTENB0 = 0; + USB_M1->INTENB1 = 0; + USB_M1->BRDYSTS = 0; + USB_M1->NRDYSTS = 0; + USB_M1->BEMPSTS = 0; +#else /* defined(USB_CFG_OTG_USE) */ + USB_M1->DVSTCTR0 = 0; + USB_M1->DCPCTR = USB_SQSET; + USB_M1->PIPE_CTR[0] = 0; + USB_M1->PIPE_CTR[1] = 0; + USB_M1->PIPE_CTR[2] = 0; + USB_M1->PIPE_CTR[3] = 0; + USB_M1->PIPE_CTR[4] = 0; + USB_M1->PIPE_CTR[5] = 0; + USB_M1->PIPE_CTR[6] = 0; + USB_M1->PIPE_CTR[7] = 0; + USB_M1->PIPE_CTR[8] = 0; + USB_M1->BRDYENB = 0; + USB_M1->NRDYENB = 0; + USB_M1->BEMPENB = 0; + USB_M1->INTENB0 = 0; + USB_M1->INTENB1 = 0; + USB_M1->BRDYSTS = 0; + USB_M1->NRDYSTS = 0; + USB_M1->BEMPSTS = 0; + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_DPRPU)); + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_DRPD)); + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_DCFM)); + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_USBE)); + USB_M1->LPSTS = 0; +#endif /* defined(USB_CFG_OTG_USE) */ + } + + return FSP_SUCCESS; +} + +/**************************************************************************//** + * @brief This function stops USB module. + * + * @retval FSP_SUCCESS Success. + * @retval FSP_ERR_USB_FAILED The function could not be completed successfully. + * @retval FSP_ERR_USB_NOT_OPEN USB module is not open. + * @retval FSP_ERR_USB_PARAMETER USB IP type is wrong. + ******************************************************************************/ +fsp_err_t usb_module_stop (uint8_t ip_type) +{ + usb_module_register_clear(ip_type); + + if (USB_IP0 == ip_type) + { + FSP_ERROR_RETURN(1 != R_MSTP->MSTPCRB_b.MSTPB11, FSP_ERR_USB_FAILED) + FSP_ERROR_RETURN(0 == R_MSTP->MSTPCRB_b.MSTPB11, FSP_ERR_USB_NOT_OPEN) + + /* Disable power for USB0 */ + R_BSP_MODULE_STOP(FSP_IP_USBFS, 0); + } + else if (USB_IP1 == ip_type) + { +#if defined(USB_HIGH_SPEED_MODULE) + FSP_ERROR_RETURN(1 != R_MSTP->MSTPCRB_b.MSTPB12, FSP_ERR_USB_FAILED) + FSP_ERROR_RETURN(0 == R_MSTP->MSTPCRB_b.MSTPB12, FSP_ERR_USB_NOT_OPEN) + + /* Enable power for USBA */ + R_BSP_MODULE_STOP(FSP_IP_USBHS, 0); +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + else + { + return FSP_ERR_USB_PARAMETER; + } + + return FSP_SUCCESS; +} + +/****************************************************************************** + * End of function usb_module_stop + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cpu_usbint_init + * Description : USB interrupt Initialize + * Arguments : uint8_t ip_type : USB_IP0/USB_IP1 + * Return value : void + ******************************************************************************/ +void usb_cpu_usbint_init (uint8_t ip_type, usb_cfg_t const * const cfg) +{ + if (USB_IP0 == ip_type) + { +#if (!defined(USB_LDO_REGULATOR_MODULE)) + + /* Deep standby USB monitor register + * b0 SRPC0 USB0 single end control + * b1 PRUE0 DP Pull-Up Resistor control + * (Use this bit during operation in Deep Software Standby mode.) + * b2 Reserved 0 + * b3 DRPD0 DP/DM Pull-Down Resistor control + * (Use this bit during operation in Deep Software Standby mode.) + * b4 FIXPHY0 USB0 transceiver output fix + * b15-b5 Reserved 0 + * b16 DP0 USB0 DP input + * b17 DM0 USB0 DM input + * b19-b18 Reserved 0 + * b20 DOVCA0 USB0 OVRCURA input + * b21 DOVCB0 USB0 OVRCURB input + * b22 Reserved 0 + * b23 DVBSTS0 USB1 VBUS input + * b31-b24 Reserved 0 + */ + USB_M0->DPUSR0R_FS_b.FIXPHY0 = 0U; /* USB0 Transceiver Output fixed */ +#endif /* !defined(USB_LDO_REGULATOR_MODULE) */ + + /* Interrupt enable register + * b0 IEN0 Interrupt enable bit + * b1 IEN1 Interrupt enable bit + * b2 IEN2 Interrupt enable bit + * b3 IEN3 Interrupt enable bit + * b4 IEN4 Interrupt enable bit + * b5 IEN5 Interrupt enable bit + * b6 IEN6 Interrupt enable bit + * b7 IEN7 Interrupt enable bit + */ +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + if (cfg->irq_d0 >= 0) + { + R_BSP_IrqCfgEnable(cfg->irq_d0, cfg->ipl_d0, (void *) cfg); /* Enable D0FIFO interrupt */ + } + + if (cfg->irq_d1 >= 0) + { + R_BSP_IrqCfgEnable(cfg->irq_d1, cfg->ipl_d1, (void *) cfg); /* Enable D1FIFO interrupt */ + } +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (cfg->irq_r >= 0) + { + R_BSP_IrqCfgEnable(cfg->irq_r, cfg->ipl_r, (void *) cfg); /* USBR enable */ + } + + if (cfg->irq >= 0) + { + R_BSP_IrqCfgEnable(cfg->irq, cfg->ipl, (void *) cfg); /* USBI enable */ + } + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + g_p_usb_cfg_ip0 = (usb_cfg_t *) cfg; +#endif /*((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST)*/ + } + + if (ip_type == USB_IP1) + { +#if defined(USB_HIGH_SPEED_MODULE) + + /* Interrupt enable register + * b0 IEN0 Interrupt enable bit + * b1 IEN1 Interrupt enable bit + * b2 IEN2 Interrupt enable bit + * b3 IEN3 Interrupt enable bit + * b4 IEN4 Interrupt enable bit + * b5 IEN5 Interrupt enable bit + * b6 IEN6 Interrupt enable bit + * b7 IEN7 Interrupt enable bit + */ + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + if (cfg->hsirq_d0 >= 0) + { + R_BSP_IrqCfgEnable(cfg->hsirq_d0, cfg->hsipl_d0, (void *) cfg); /* Enable D0FIFO interrupt */ + } + + if (cfg->hsirq_d1 >= 0) + { + R_BSP_IrqCfgEnable(cfg->hsirq_d1, cfg->hsipl_d1, (void *) cfg); /* Enable D1FIFO interrupt */ + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + if (cfg->hsirq >= 0) + { + R_BSP_IrqCfgEnable(cfg->hsirq, cfg->hsipl, (void *) cfg); /* USBIR enable */ + } + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + g_p_usb_cfg_ip1 = (usb_cfg_t *) cfg; + #endif /*((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST)*/ +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + } +} + +/****************************************************************************** + * End of function usb_cpu_usbint_init + ******************************************************************************/ + +/****************************************************************************** + * TIMER function + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cpu_delay_1us + * Description : 1us Delay timer + * Arguments : uint16_t time ; Delay time(*1us) + * Return value : none + * Note : Please change for your MCU + ******************************************************************************/ +void usb_cpu_delay_1us (uint16_t time) +{ + R_BSP_SoftwareDelay((uint32_t) time, BSP_DELAY_UNITS_MICROSECONDS); +} + +/****************************************************************************** + * End of function usb_cpu_delay_1us + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cpu_delay_xms + * Description : xms Delay timer + * Arguments : uint16_t time ; Delay time(*1ms) + * Return value : void + * Note : Please change for your MCU + ******************************************************************************/ +void usb_cpu_delay_xms (uint16_t time) +{ +#if (BSP_CFG_RTOS == 0) + R_BSP_SoftwareDelay((uint32_t) time, BSP_DELAY_UNITS_MILLISECONDS); +#elif (BSP_CFG_RTOS == 1) + tx_thread_sleep(time); +#elif (BSP_CFG_RTOS == 2) + vTaskDelay((TickType_t) (time / portTICK_PERIOD_MS)); +#endif /* #if (BSP_CFG_RTOS == 0) */ +} + +/****************************************************************************** + * End of function usb_cpu_delay_xms + ******************************************************************************/ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/****************************************************************************** + * Function Name : usb_cpu_int_enable + * Description : USB Interrupt Enable + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_cpu_int_enable (void) +{ + /* Interrupt enable register (USB0 USBIO enable) + * b0 IEN0 Interrupt enable bit + * b1 IEN1 Interrupt enable bit + * b2 IEN2 Interrupt enable bit + * b3 IEN3 Interrupt enable bit + * b4 IEN4 Interrupt enable bit + * b5 IEN5 Interrupt enable bit + * b6 IEN6 Interrupt enable bit + * b7 IEN7 Interrupt enable bit + */ + if (USB_NULL != g_p_usb_cfg_ip0) + { + if (USB_MODE_HOST == g_p_usb_cfg_ip0->usb_mode) + { + if (g_p_usb_cfg_ip0->irq >= 0) + { + R_BSP_IrqCfgEnable(g_p_usb_cfg_ip0->irq, g_p_usb_cfg_ip0->ipl, g_p_usb_cfg_ip0); /* USBI enable */ + } + + USB_M0->INTENB0 = g_usb_hstd_m0_reg_intenb0; + USB_M0->INTENB1 = g_usb_hstd_m0_reg_intenb1; + } + } + + #if defined(USB_HIGH_SPEED_MODULE) + + /* Interrupt enable register (USB1 USBIO enable) + * b0 IEN0 Interrupt enable bit + * b1 IEN1 Interrupt enable bit + * b2 IEN2 Interrupt enable bit + * b3 IEN3 Interrupt enable bit + * b4 IEN4 Interrupt enable bit + * b5 IEN5 Interrupt enable bit + * b6 IEN6 Interrupt enable bit + * b7 IEN7 Interrupt enable bit + */ + if (USB_NULL != g_p_usb_cfg_ip1) + { + if (USB_MODE_HOST == g_p_usb_cfg_ip1->usb_mode) + { + if (g_p_usb_cfg_ip1->hsirq >= 0) + { + R_BSP_IrqCfgEnable(g_p_usb_cfg_ip1->hsirq, g_p_usb_cfg_ip1->hsipl, g_p_usb_cfg_ip1); /* USBIR enable */ + } + + USB_M1->INTENB0 = g_usb_hstd_m1_reg_intenb0; + USB_M1->INTENB1 = g_usb_hstd_m1_reg_intenb1; + } + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ +} + +/****************************************************************************** + * End of function usb_cpu_int_enable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_cpu_int_disable + * Description : USB Interrupt disable + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_cpu_int_disable (void) +{ + /* Interrupt enable register (USB0 USBIO disable) + * b0 IEN0 Interrupt enable bit + * b1 IEN1 Interrupt enable bit + * b2 IEN2 Interrupt enable bit + * b3 IEN3 Interrupt enable bit + * b4 IEN4 Interrupt enable bit + * b5 IEN5 Interrupt enable bit + * b6 IEN6 Interrupt enable bit + * b7 IEN7 Interrupt enable bit + */ + if (USB_NULL != g_p_usb_cfg_ip0) + { + if (USB_MODE_HOST == g_p_usb_cfg_ip0->usb_mode) + { + g_usb_hstd_m0_reg_intenb0 = USB_M0->INTENB0; + g_usb_hstd_m0_reg_intenb1 = USB_M0->INTENB1; + USB_M0->INTENB0 = 0; + USB_M0->INTENB1 = 0; + + R_BSP_IrqDisable(g_p_usb_cfg_ip0->irq); /* USBI enable */ + } + } + + #if defined(USB_HIGH_SPEED_MODULE) + + /* Interrupt enable register (USB1 USBIO disable) + * b0 IEN0 Interrupt enable bit + * b1 IEN1 Interrupt enable bit + * b2 IEN2 Interrupt enable bit + * b3 IEN3 Interrupt enable bit + * b4 IEN4 Interrupt enable bit + * b5 IEN5 Interrupt enable bit + * b6 IEN6 Interrupt enable bit + * b7 IEN7 Interrupt enable bit + */ + if (USB_NULL != g_p_usb_cfg_ip1) + { + if (USB_MODE_HOST == g_p_usb_cfg_ip1->usb_mode) + { + g_usb_hstd_m1_reg_intenb0 = USB_M1->INTENB0; + g_usb_hstd_m1_reg_intenb1 = USB_M1->INTENB1; + USB_M1->INTENB0 = 0; + USB_M1->INTENB1 = 0; + + R_BSP_IrqDisable(g_p_usb_cfg_ip1->hsirq); /* USBIR enable */ + } + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ +} + +/****************************************************************************** + * End of function usb_cpu_int_disable + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_chattaring + * Description : Remove chattaring processing + * Arguments : uint16_t *syssts : SYSSTS register value + * Return value : LNST bit value + ******************************************************************************/ +uint16_t usb_chattaring (uint16_t * syssts) +{ + uint16_t lnst[4]; + + /* WAIT_LOOP */ + while (1) + { + lnst[0] = (*syssts) & USB_LNST; + usb_cpu_delay_xms((uint16_t) 1); /* 1ms wait */ + lnst[1] = (*syssts) & USB_LNST; + usb_cpu_delay_xms((uint16_t) 1); /* 1ms wait */ + lnst[2] = (*syssts) & USB_LNST; + if ((lnst[0] == lnst[1]) && (lnst[0] == lnst[2])) + { + break; + } + } + + return lnst[0]; +} + +/****************************************************************************** + * End of function usb_chattaring + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_OTG_USE) + +/******************************************************************************* + * Function Name: usb_otg_irq_callback + * Description : IRQ Interrupt service for attaching and detaching OTG A-device of USB_IP0 + * Arguments : none + * Return Value : none + *******************************************************************************/ +void usb_otg_irq_callback (external_irq_callback_args_t * p_args) +{ + usb_er_t err; + usb_utr_t * p_utr; + uint16_t syssts; + + (void) p_args; + + p_utr = &g_usb_irq_otg_msg; + p_utr->msghead = (usb_mh_t) USB_NULL; + g_usb_otg_chattering_counter = 0; + while (g_usb_otg_chattering_counter != 5) + { + ; + } + + p_utr->ip = USB_IP0; + syssts = hw_usb_read_syssts(p_utr); + if (USB_IDMON != (syssts & USB_IDMON)) + { + /* For attaching */ + if (USB_MODE_PERI == g_usb_usbmode[0]) + { + p_utr->msginfo = USB_MSG_HCD_INT; + p_utr->keyword = USB_INT_OTG_HOST_INIT; + err = USB_SND_MSG(USB_HCD_MBX, (usb_msg_t *) p_utr); + } + else + { + return; + } + } + else + { + /* For Detaching */ + /* Don't set "USB_NO" to "g_is_A_device[]" */ + tx_timer_deactivate(&g_usb_otg_detach_timer); + g_is_A_cable_detach[0] = USB_YES; + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; + (*g_p_otg_callback[0])(UX_OTG_MODE_IDLE); + if (USB_MODE_PERI == g_usb_usbmode[0]) + { + p_utr->msginfo = USB_MSG_PCD_INT; + p_utr->keyword = USB_INT_VBINT; + err = USB_SND_MSG(USB_PCD_MBX, (usb_msg_t *) p_utr); + } + else + { + p_utr->keyword = USB_INT_DTCH0; + err = USB_SND_MSG(USB_HCD_MBX, (usb_msg_t *) p_utr); + } + } + + if (USB_OK != err) + { + USB_PRINTF1("### IRQ Interrupt for OTG snd_msg error (%ld)\n", err); + } +} + + #if USB_NUM_USBIP == 2 + +/******************************************************************************* + * Function Name: usb_otg_irq_callback + * Description : IRQ Interrupt service for attaching and detaching OTG A-device of USB_IP1 + * Arguments : none + * Return Value : none + *******************************************************************************/ +void usb2_otg_irq_callback (external_irq_callback_args_t * p_args) +{ + usb_er_t err; + usb_utr_t * p_utr; + uint16_t syssts; + + (void) p_args; + + p_utr = &g_usb_irq_otg_msg; + p_utr->msghead = (usb_mh_t) USB_NULL; + + g_usb_otg_chattering_counter = 0; + while (g_usb_otg_chattering_counter != 5) + { + ; + } + + p_utr->ip = USB_IP1; + syssts = hw_usb_read_syssts(p_utr); + if (USB_IDMON != (syssts & USB_IDMON)) + { + /* For attaching */ + if (USB_MODE_PERI == g_usb_usbmode[1]) + { + p_utr->msginfo = USB_MSG_HCD_INT; + p_utr->keyword = USB_INT_OTG_HOST_INIT; + err = USB_SND_MSG(USB_HCD_MBX, (usb_msg_t *) p_utr); + } + else + { + return; + } + } + else + { + /* For Detaching */ + /* Don't set "USB_NO" to "g_is_A_device[]" */ + tx_timer_deactivate(&g_usb_otg_detach_timer); + g_is_A_cable_detach[1] = USB_YES; + _ux_system_otg->ux_system_otg_device_type = UX_OTG_DEVICE_IDLE; + (*g_p_otg_callback[1])(UX_OTG_MODE_IDLE); + if (USB_MODE_PERI == g_usb_usbmode[1]) + { + p_utr->msginfo = USB_MSG_PCD_INT; + p_utr->keyword = USB_INT_VBINT; + err = USB_SND_MSG(USB_PCD_MBX, (usb_msg_t *) p_utr); + } + else + { + p_utr->keyword = USB_INT_DTCH0; + err = USB_SND_MSG(USB_HCD_MBX, (usb_msg_t *) p_utr); + } + } + + if (USB_OK != err) + { + USB_PRINTF1("### IRQ Interrupt for OTG snd_msg error (%ld)\n", err); + } +} + + #endif /* USB_NUM_USBIP == 2 */ + +/******************************************************************************* + * Function Name: usb_otg_detach_timer (5ms interval) + * Description : The timer to detect that USB B-cable is detached when A device is Peripheral mode for USB IP0 + * Arguments : args : No use + * Return Value : none + *******************************************************************************/ +VOID usb_otg_detach_timer (ULONG args) +{ + uint16_t frmnum; + usb_utr_t * p_utr; + usb_er_t err; + + (void) args; + p_utr = &g_usb_otg_detach_msg; + p_utr->ip = USB_IP0; + + if (USB_MODE_PERI == g_usb_usbmode[0]) + { + frmnum = hw_usb_read_frmnum(p_utr); + frmnum &= USB_FRNM; + + if ((g_usb_otg_frmnum_prev == frmnum) && (0 != frmnum)) + { + g_usb_otg_frmnum_prev = 0; + + /* Detect the B-cable detaching */ + p_utr->ip = USB_IP0; + p_utr->msghead = (usb_mh_t) USB_NULL; + p_utr->msginfo = USB_MSG_PCD_INT; + + p_utr->keyword = USB_INT_VBINT; + err = USB_SND_MSG(USB_PCD_MBX, (usb_msg_t *) p_utr); + if (USB_OK != err) + { + USB_PRINTF1("### IRQ Interrupt for OTG isnd_msg error (%ld)\n", err); + } + } + else + { + g_usb_otg_frmnum_prev = frmnum; + } + } +} + +/******************************************************************************* + * Function Name: usb_otg_chattering_timer (5ms interval) + * Description : The timer to detect that USB B-cable is detached when A device is Peripheral mode for USB IP0 + * Arguments : args : No use + * Return Value : none + *******************************************************************************/ +VOID usb_otg_chattering_timer (ULONG args) +{ + (void) args; + g_usb_otg_chattering_counter++; +} + +/******************************************************************************* + * Function Name: usb_otg_hnp_timer (10ms interval) + * Description : The timer to detect that USB B-cable is detached when A device is Peripheral mode for USB IP0 + * Arguments : args : No use + * Return Value : none + *******************************************************************************/ +VOID usb_otg_hnp_timer (ULONG args) +{ + (void) args; + g_usb_otg_hnp_counter++; +} + + #if USB_NUM_USBIP == 2 + +/******************************************************************************* + * Function Name: usb2_otg_detach_timer (5ms interval) + * Description : The timer to detect that USB B-cable is detached when A device is Peripheral mode for USB IP1 + * Arguments : args : No use + * Return Value : none + *******************************************************************************/ +VOID usb2_otg_detach_timer (ULONG args) +{ + uint16_t frmnum; + usb_utr_t * p_utr; + usb_er_t err; + + (void) args; + p_utr = &g_usb_otg_detach_msg; + + p_utr->ip = USB_IP1; + if (USB_MODE_PERI == g_usb_usbmode[1]) + { + frmnum = hw_usb_read_frmnum(p_utr); + frmnum &= USB_FRNM; + + if ((g_usb_otg_frmnum_prev == frmnum) && (0 != frmnum)) + { + /* Detect the B-cable detaching */ + p_utr->ip = USB_IP1; + p_utr->msghead = (usb_mh_t) USB_NULL; + p_utr->msginfo = USB_MSG_PCD_INT; + + p_utr->keyword = USB_INT_VBINT; + err = USB_SND_MSG(USB_PCD_MBX, (usb_msg_t *) p_utr); + if (USB_OK != err) + { + USB_PRINTF1("### IRQ Interrupt for OTG isnd_msg error (%ld)\n", err); + } + } + else + { + g_usb_otg_frmnum_prev = frmnum; + } + } +} + + #endif /* USB_NUM_USBIP == 2 */ + + #endif /* defined(USB_CFG_OTG_USE) */ +#endif /* if (BSP_CFG_RTOS == 1) */ + +/******************************************************************************* + * Function Name: usbfs_usbi_isr + * Description : Interrupt service routine of USBF + * Arguments : none + * Return Value : none + *******************************************************************************/ +static void usbfs_usbi_isr (void) +{ + /* Call USB interrupt routine */ + if (USB_MODE_HOST == g_usb_usbmode[USB_IP0]) + { +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + usb_hstd_usb_handler(); /* Call interrupt routine */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_pstd_usb_handler(); /* Call interrupt routine */ +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } +} + +/****************************************************************************** + * End of function usbfs_usbi_isr + ******************************************************************************/ + +#if defined(USB_HIGH_SPEED_MODULE) + +/******************************************************************************* + * Function Name: usbhs_usbir_isr + * Description : Interrupt service routine of USBF + * Arguments : none + * Return Value : none + *******************************************************************************/ +static void usbhs_usbir_isr (void) +{ + /* Condition compilation by the difference of USB function */ + if (USB_MODE_HOST == g_usb_usbmode[USB_IP1]) + { + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + #if USB_NUM_USBIP == 2 + usb2_hstd_usb_handler(); /* Call interrupt routine */ + #endif /* USB_NUM_USBIP == 2 */ + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + } + else + { + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_pstd_usb_handler(); + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + } +} + +/****************************************************************************** + * End of function usbhs_usbir_isr + ******************************************************************************/ +#endif /* defined (USB_HIGH_SPEED_MODULE)*/ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Function Name : usb_cpu_usb_int_hand_isr + * Description : + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_cpu_usb_int_hand_isr (uint8_t usb_ip) +{ + hw_usb_pclear_sts_resm(usb_ip); +} /* End of function usb_cpu_usb_int_hand_isr */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +#if USB_CFG_DTC == USB_CFG_ENABLE + +/****************************************************************************** + * Function Name : usb_cpu_d1fifo_int_hand + * Description : D0FIFO interrupt Handler + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb_cpu_d1fifo_int_hand (void) +{ + usb_cstd_dma_send_complete(USB_IP0, USB_D1USE); +} + +/****************************************************************************** + * End of function usb_cpu_d1fifo_int_hand + ******************************************************************************/ + + #if defined(USB_HIGH_SPEED_MODULE) + +/****************************************************************************** + * Function Name : usb2_cpu_d1fifo_int_hand + * Description : D0FIFO interrupt Handler + * Arguments : none + * Return value : none + ******************************************************************************/ +static void usb2_cpu_d1fifo_int_hand (void) +{ + usb_cstd_dma_send_complete(USB_IP1, USB_D1USE); +} + +/****************************************************************************** + * End of function usb2_cpu_d1fifo_int_hand + ******************************************************************************/ + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + +#endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + +/****************************************************************************** + * Function Name : usb_check_use_usba_module + * Description : + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure + * Return value : + ******************************************************************************/ +bool usb_check_use_usba_module (usb_utr_t * ptr) +{ + bool ret_code = false; + + FSP_PARAMETER_NOT_USED(ptr); +#if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ptr->ip) + { + ret_code = true; + } +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + + return ret_code; +} /* End of function usb_check_use_usba_module */ + +#if defined(USB_CFG_OTG_USE) +IRQn_Type g_otg_usb_fs_irq; +#endif /* defined(USB_CFG_OTG_USE) */ + +void usbfs_interrupt_handler (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); +#if defined(USB_CFG_OTG_USE) + g_otg_usb_fs_irq = irq; +#endif /* defined(USB_CFG_OTG_USE) */ + + usbfs_usbi_isr(); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +void usbfs_resume_handler (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + usb_cfg_t * p_cfg; + + p_cfg = (usb_cfg_t *) R_FSP_IsrContextGet(irq); + usb_cpu_usb_int_hand_isr(p_cfg->module_number); +#endif /* ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +void usbfs_d0fifo_handler (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +void usbfs_d1fifo_handler (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if USB_CFG_DTC == USB_CFG_ENABLE + usb_cpu_d1fifo_int_hand(); +#endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +void usbhs_interrupt_handler (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if defined(USB_HIGH_SPEED_MODULE) + usbhs_usbir_isr(); +#endif /* defined (USB_HIGH_SPEED_MODULE) */ + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +void usbhs_d0fifo_handler (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +void usbhs_d1fifo_handler (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if USB_CFG_DTC == USB_CFG_ENABLE + #if defined(USB_HIGH_SPEED_MODULE) + usb2_cpu_d1fifo_int_hand(); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ +#endif /* USB_CFG_DTC == USB_CFG_ENABLE */ + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE +} + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c new file mode 100644 index 0000000000..0b3bfa4782 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c @@ -0,0 +1,885 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" +#include "inc/r_usb_dmac.h" + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ +#define USB_VAL_FFH (0x00FFU) +#define USB_VAL_100 (100U) + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Exported global variables (to be accessed by other files) + ******************************************************************************/ +uint16_t g_usb_cstd_suspend_mode = USB_NORMAL_MODE; + +/****************************************************************************** + * Function Name : usb_pstd_interrupt_handler + * Description : Determine which USB interrupt occurred and report results to + * : the usb_utr_t argument's ipp, type, and status members. + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void usb_pstd_interrupt_handler (uint16_t * type, uint16_t * status, uint8_t usb_ip) +{ + uint16_t intsts0; + uint16_t intenb0; + uint16_t ists0; + uint16_t brdysts; + uint16_t brdyenb; + uint16_t bsts; + uint16_t nrdysts; + uint16_t nrdyenb; + uint16_t nsts; + uint16_t bempsts; + uint16_t bempenb; + uint16_t ests; + + /* Register Save */ + if (USB_CFG_IP1 == usb_ip) + { + intsts0 = USB_M1->INTSTS0; + brdysts = USB_M1->BRDYSTS; + nrdysts = USB_M1->NRDYSTS; + bempsts = USB_M1->BEMPSTS; + intenb0 = USB_M1->INTENB0; + brdyenb = USB_M1->BRDYENB; + nrdyenb = USB_M1->NRDYENB; + bempenb = USB_M1->BEMPENB; + } + else + { + intsts0 = USB_M0->INTSTS0; + brdysts = USB_M0->BRDYSTS; + nrdysts = USB_M0->NRDYSTS; + bempsts = USB_M0->BEMPSTS; + intenb0 = USB_M0->INTENB0; + brdyenb = USB_M0->BRDYENB; + nrdyenb = USB_M0->NRDYENB; + bempenb = USB_M0->BEMPENB; + } + + *type = USB_INT_UNKNOWN; + *status = 0; + + /* Interrupt status get */ + ists0 = (uint16_t) (intsts0 & intenb0); + bsts = (uint16_t) (brdysts & brdyenb); + nsts = (uint16_t) (nrdysts & nrdyenb); + ests = (uint16_t) (bempsts & bempenb); + + if (0U == ((USB_VBINT | USB_RESM | USB_SOFR | USB_DVST | + USB_CTRT | USB_BEMP | USB_NRDY | USB_BRDY) & intsts0)) + { + return; + } + + /***** Processing USB bus signal *****/ + /***** Resume signal *****/ + if (USB_RESM == (ists0 & USB_RESM)) + { + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->INTSTS0 = (uint16_t) ~USB_RESM; + } + else + { + USB_M0->INTSTS0 = (uint16_t) ~USB_RESM; + } + + *type = USB_INT_RESM; + } + + /***** Vbus change *****/ + else if (USB_VBINT == (ists0 & USB_VBINT)) + { + /* Status clear */ + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->INTSTS0 = (uint16_t) ~USB_VBINT; + } + else + { + USB_M0->INTSTS0 = (uint16_t) ~USB_VBINT; + } + + *type = USB_INT_VBINT; + } + + /***** SOFR change *****/ + else if (USB_SOFR == (ists0 & USB_SOFR)) + { + /* SOFR Clear */ + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->INTSTS0 = (uint16_t) ~USB_SOFR; + } + else + { + USB_M0->INTSTS0 = (uint16_t) ~USB_SOFR; + } + + *type = USB_INT_SOFR; + } + + /***** Processing device state *****/ + /***** DVST change *****/ + else if (USB_DVST == (ists0 & USB_DVST)) + { + /* DVST clear */ + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->INTSTS0 = (uint16_t) ~USB_DVST; + } + else + { + USB_M0->INTSTS0 = (uint16_t) ~USB_DVST; + } + + *type = USB_INT_DVST; + *status = intsts0; + } + + /***** Processing PIPE0 data *****/ + else if ((USB_BRDY == (ists0 & USB_BRDY)) && ((USB_BRDY0) == (bsts & USB_BRDY0))) + { + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->BRDYSTS = (uint16_t) ((~USB_BRDY0) & BRDYSTS_MASK); + } + else + { + USB_M0->BRDYSTS = (uint16_t) ((~USB_BRDY0) & BRDYSTS_MASK); + } + + *type = USB_INT_BRDY; + *status = USB_BRDY0; + } + else if ((USB_BEMP == (ists0 & USB_BEMP)) && (USB_BEMP0 == (ests & USB_BEMP0))) + { + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->BEMPSTS = (uint16_t) ((~USB_BEMP0) & BEMPSTS_MASK); + } + else + { + USB_M0->BEMPSTS = (uint16_t) ((~USB_BEMP0) & BEMPSTS_MASK); + } + + *type = USB_INT_BEMP; + *status = USB_BEMP0; + } + else if ((USB_NRDY == (ists0 & USB_NRDY)) && (USB_NRDY0 == (nsts & USB_NRDY0))) + { + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->NRDYSTS = (uint16_t) ((~USB_NRDY0) & NRDYSTS_MASK); + } + else + { + USB_M0->NRDYSTS = (uint16_t) ((~USB_NRDY0) & NRDYSTS_MASK); + } + + *type = USB_INT_NRDY; + *status = USB_NRDY0; + } + + /***** Processing setup transaction *****/ + else if (USB_CTRT == (ists0 & USB_CTRT)) + { + /* CTSQ bit changes later than CTRT bit for ASSP. */ + /* CTSQ reloading */ + *status = hw_usb_read_intsts(usb_ip); + + /* USB_CTRT clear */ + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->INTSTS0 = (uint16_t) ~USB_CTRT; + } + else + { + USB_M0->INTSTS0 = (uint16_t) ~USB_CTRT; + } + + *type = USB_INT_CTRT; + + if (USB_CS_SQER == (uint8_t) ((*status) & USB_CTSQ)) + { + hw_usb_pclear_sts_valid(usb_ip); + *type = USB_INT_UNKNOWN; + *status = 0; + + return; + } + } + + /***** Processing PIPE1-MAX_PIPE_NO data *****/ + else if (USB_BRDY == (ists0 & USB_BRDY)) + { + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->BRDYSTS = (uint16_t) ((uint16_t) (~bsts) & BRDYSTS_MASK); + } + else + { + USB_M0->BRDYSTS = (uint16_t) ((uint16_t) (~bsts) & BRDYSTS_MASK); + } + + *type = USB_INT_BRDY; + *status = bsts; + } + else if (USB_BEMP == (ists0 & USB_BEMP)) + { + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->BEMPSTS = (uint16_t) ((uint16_t) (~ests) & BEMPSTS_MASK); + } + else + { + USB_M0->BEMPSTS = (uint16_t) ((uint16_t) (~ests) & BEMPSTS_MASK); + } + + *type = USB_INT_BEMP; + *status = ests; + } + else if (USB_NRDY == (ists0 & USB_NRDY)) + { + if (USB_CFG_IP1 == usb_ip) + { + USB_M1->NRDYSTS = (uint16_t) ((uint16_t) (~nsts) & NRDYSTS_MASK); + } + else + { + USB_M0->NRDYSTS = (uint16_t) ((uint16_t) (~nsts) & NRDYSTS_MASK); + } + + *type = USB_INT_NRDY; + *status = nsts; + } + else + { + /* Non processing. */ + } +} + +/****************************************************************************** + * End of function usb_pstd_interrupt_handler + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_save_request + * Description : Save received USB command. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_save_request (uint8_t usb_ip) +{ + /* Valid clear */ + hw_usb_pclear_sts_valid(usb_ip); + + g_usb_pstd_req_type = hw_usb_read_usbreq(usb_ip); + g_usb_pstd_req_value = hw_usb_read_usbval(usb_ip); + g_usb_pstd_req_index = hw_usb_read_usbindx(usb_ip); + g_usb_pstd_req_length = hw_usb_read_usbleng(usb_ip); +} + +/****************************************************************************** + * End of function usb_pstd_save_request + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_chk_configured + * Description : Check if USB Device is in a CONFIGURED state. + * Arguments : none + * Return value : Configuration state (YES/NO) + ******************************************************************************/ +uint16_t usb_pstd_chk_configured (usb_utr_t * p_utr) +{ + uint16_t buf; + uint16_t err; + + buf = hw_usb_read_intsts(p_utr->ip); + + /* Device Status - Configured check */ + if (USB_DS_CNFG == (buf & USB_DVSQ)) + { + /* Configured */ + err = USB_TRUE; + } + else + { + /* not Configured */ + err = USB_FALSE; + } + + return err; +} + +/****************************************************************************** + * End of function usb_pstd_chk_configured + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_remote_wakeup + * Description : Set the USB peripheral to implement remote wake up. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_remote_wakeup (uint8_t usb_ip) +{ + uint16_t buf; + + g_usb_pstd_remote_wakeup_state = USB_ERROR; + + /* Support remote wakeup ? */ + if (USB_TRUE == g_usb_pstd_remote_wakeup) + { + /* RESM interrupt disable */ + hw_usb_pclear_enb_rsme(usb_ip); + + /* RESM status read */ + buf = hw_usb_read_intsts(usb_ip); + if ((buf & USB_RESM) != (uint16_t) 0) + { + g_usb_pstd_remote_wakeup_state = USB_QOVR; + + /* RESM status clear */ + hw_usb_pclear_sts_resm(usb_ip); + } + else + { + if ((buf & USB_DS_SUSP) != (uint16_t) 0) + { + /* Remote wakeup set */ + hw_usb_pset_wkup(usb_ip); + g_usb_pstd_remote_wakeup_state = USB_OK; + } + } + } +} + +/****************************************************************************** + * End of function usb_pstd_remote_wakeup + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_test_mode + * Description : USB Peripheral test mode function. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_test_mode (usb_utr_t * p_utr) +{ + (void) *p_utr; + switch ((uint16_t) (g_usb_pstd_test_mode_select & USB_TEST_SELECT)) + { + case USB_TEST_J: + + /* Continue */ + case USB_TEST_K: + + /* Continue */ + case USB_TEST_SE0_NAK: + + /* Continue */ + case USB_TEST_PACKET: + { + #if defined(USB_HIGH_SPEED_MODULE) + hw_usb_set_utst(p_utr, 0); + hw_usb_set_utst(p_utr, (uint16_t) (g_usb_pstd_test_mode_select >> 8)); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + + case USB_TEST_FORCE_ENABLE: + + /* Continue */ + default: + { + break; + } + } +} + +/****************************************************************************** + * End of function usb_pstd_test_mode + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_resume_process + * Description : Set USB registers to implement resume processing. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_resume_process (usb_utr_t * p_utr) +{ + /* RESM status clear */ + hw_usb_pclear_sts_resm(p_utr->ip); + + /* RESM interrupt disable */ + hw_usb_pclear_enb_rsme(p_utr->ip); +} + +/****************************************************************************** + * End of function usb_pstd_resume_process + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_stall + * Description : Set the specified pipe's PID to STALL. + * Arguments : uint16_t pipe : Pipe Number + * Return value : none + ******************************************************************************/ +void usb_pstd_set_stall (uint16_t pipe, usb_utr_t * p_utr) +{ + /* PIPE control reg set */ + hw_usb_set_pid(p_utr, pipe, USB_PID_STALL); +} + +/****************************************************************************** + * End of function usb_pstd_set_stall + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_set_stall_pipe0 + * Description : Set pipe "0" PID to STALL. + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_set_stall_pipe0 (usb_utr_t * p_utr) +{ + /* PIPE control reg set */ + hw_usb_set_pid(p_utr, USB_PIPE0, USB_PID_STALL); +} + +/****************************************************************************** + * End of function usb_pstd_set_stall_pipe0 + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_write_fifo + * Description : Write specified amount of data to specified USB FIFO. + * Arguments : uint16_t count : Write size. + * : uint16_t pipemode : The mode of CPU/DMA(D0)/DMA(D1). + * : uint16_t *write_p : Address of buffer of data to write. + * Return value : The incremented address of last argument (write_p). + ******************************************************************************/ +uint8_t * usb_pstd_write_fifo (uint16_t count, uint16_t pipemode, uint8_t * write_p, usb_utr_t * p_utr) +{ + uint16_t even; + #if defined(USB_HIGH_SPEED_MODULE) + uint16_t odd; + uint16_t hs_flag = 1; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + uint16_t hs_flag = 0; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + #if defined(USB_UNALIGNED_MEMORY_ACCESS_NG_MCU) + + /* The value of "write_p" is odd */ + if (USB_ODD == ((uint32_t) write_p & USB_ODD)) + { + /* 8bit access */ + /* write_p == odd */ + /* Change FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_8); + + for ( ; (0 != count); count--) + { + USB0_CFIFO8 = *write_p++; + } + + /* Return FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_16); + + return write_p; + } + #endif /* defined(USB_UNALIGNED_MEMORY_ACCESS_NG_MCU) */ + + if ((USB_CFG_IP0 == p_utr->ip) || (0 == hs_flag)) + { + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 1); (0 != even); --even) + { + /* 16bit access */ + hw_usb_write_fifo16(p_utr, pipemode, *((uint16_t *) write_p)); + + /* Renewal write pointer */ + write_p += sizeof(uint16_t); + } + + if ((count & (uint16_t) 0x0001U) != 0U) + { + /* 8bit access */ + /* count == odd */ + /* Change FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_8); + + /* FIFO write */ + hw_usb_write_fifo8(p_utr, pipemode, *write_p); + + /* Return FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_16); + + /* Renewal write pointer */ + write_p++; + } + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 2); (even != 0); --even) + { + /* 32bit access */ + hw_usb_write_fifo32(p_utr, pipemode, *((uint32_t *) write_p)); + + /* Renewal write pointer */ + write_p += sizeof(uint32_t); + } + + odd = count % 4; + if ((odd & (uint16_t) 0x0002U) != 0U) + { + /* 16bit access */ + /* Change FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_16); + + /* FIFO write */ + hw_usb_write_fifo16(p_utr, pipemode, *((uint16_t *) write_p)); + + /* Renewal write pointer */ + write_p += sizeof(uint16_t); + } + + if ((odd & (uint16_t) 0x0001U) != 0U) + { + /* 8bit access */ + /* count == odd */ + /* Change FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_8); + + /* FIFO write */ + hw_usb_write_fifo8(p_utr, pipemode, *write_p); + + /* Renewal write pointer */ + write_p++; + } + + /* Return FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_32); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + return write_p; +} + +/****************************************************************************** + * End of function usb_pstd_write_fifo + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_read_fifo + * Description : Read specified buffer size from the USB FIFO. + * Arguments : uint16_t count : Read size. + * : uint16_t pipemode : The mode of CPU/DMA(D0)/DMA(D1). + * : uint16_t *write_p : Address of buffer to store the read data. + * Return value : Pointer to a buffer that contains the data to be read next. + ******************************************************************************/ +uint8_t * usb_pstd_read_fifo (uint16_t count, uint16_t pipemode, uint8_t * read_p, usb_utr_t * p_utr) +{ + uint16_t even; + uint32_t odd_byte_data_temp; + #if USB_CFG_ENDIAN == USB_CFG_BIG + uint16_t i; + #endif + #if defined(USB_HIGH_SPEED_MODULE) + uint16_t odd; + uint16_t hs_flag = 1; + #else /* defined (USB_HIGH_SPEED_MODULE) */ + uint16_t hs_flag = 0; + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + #if defined(USB_UNALIGNED_MEMORY_ACCESS_NG_MCU) + + /* The value of "read_p" is odd */ + if (USB_ODD == ((uint32_t) read_p & USB_ODD)) + { + /* 8bit access */ + /* read_p == odd */ + /* Change FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_8); + + for ( ; (0 != count); count--) + { + *read_p++ = USB0_CFIFO8; + } + + /* Return FIFO access width */ + hw_usb_set_mbw(p_utr, pipemode, USB_MBW_16); + + return read_p; + } + #endif /* defined(USB_UNALIGNED_MEMORY_ACCESS_NG_MCU) */ + + if ((USB_CFG_IP0 == p_utr->ip) || (0 == hs_flag)) + { + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 1); (0 != even); --even) + { + /* 16bit FIFO access */ + *(uint16_t *) read_p = hw_usb_read_fifo16(p_utr, pipemode); + + /* Renewal read pointer */ + read_p += sizeof(uint16_t); + } + + if ((count & (uint16_t) 0x0001) != 0) + { + /* 16bit FIFO access */ + odd_byte_data_temp = hw_usb_read_fifo16(p_utr, pipemode); + + /* Condition compilation by the difference of the little endian */ + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + *read_p = (uint8_t) (odd_byte_data_temp & USB_VAL_FFH); + #else /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + *read_p = (uint8_t) (odd_byte_data_temp >> 8); + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + + /* Renewal read pointer */ + read_p += sizeof(uint8_t); + } + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* WAIT_LOOP */ + for (even = (uint16_t) (count >> 2); (even != 0); --even) + { + /* 32bit FIFO access */ + *(uint32_t *) read_p = hw_usb_read_fifo32(p_utr, pipemode); + + /* Renewal read pointer */ + read_p += sizeof(uint32_t); + } + + odd = count % 4; + if (count < 4) + { + odd = count; + } + + if (odd != 0) + { + /* 32bit FIFO access */ + odd_byte_data_temp = hw_usb_read_fifo32(p_utr, pipemode); + + /* Condition compilation by the difference of the endian */ + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + + /* WAIT_LOOP */ + do + { + *read_p = (uint8_t) (odd_byte_data_temp & USB_VAL_FFH); + odd_byte_data_temp = odd_byte_data_temp >> 8; + + /* Renewal read pointer */ + read_p += sizeof(uint8_t); + odd--; + } while (odd != 0); + #else /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + /* WAIT_LOOP */ + for (i = 0; i < odd; i++) + { + *read_p = (uint8_t) ((odd_byte_data_temp >> (24 - (i * 8))) & 0x000000ff); + + /* Renewal read pointer */ + read_p += sizeof(uint8_t); + } + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + } + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + + return read_p; +} + +/****************************************************************************** + * End of function usb_pstd_read_fifo + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_forced_termination + * Description : Terminate data transmission and reception. + * Arguments : uint16_t pipe : Pipe Number + * : uint16_t status : Transfer status type + * Return value : none + * Note : In the case of timeout status, it does not call back. + ******************************************************************************/ +void usb_pstd_forced_termination (uint16_t pipe, uint16_t status, usb_utr_t * p_utr) +{ + uint16_t buffer; + + /* PID = NAK */ + /* Set NAK */ + usb_cstd_set_nak(p_utr, pipe); + + /* Disable Interrupt */ + /* Disable Ready Interrupt */ + hw_usb_clear_brdyenb(p_utr, pipe); + + /* Disable Not Ready Interrupt */ + hw_usb_clear_nrdyenb(p_utr, pipe); + + /* Disable Empty Interrupt */ + hw_usb_clear_bempenb(p_utr, pipe); + + usb_cstd_clr_transaction_counter(p_utr, pipe); + + /* Clear CFIFO-port */ + buffer = hw_usb_read_fifosel(p_utr, USB_CUSE); + if ((buffer & USB_CURPIPE) == pipe) + { + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(p_utr, (uint16_t) USB_PIPE0, (uint16_t) USB_CUSE, USB_FALSE); + } + + #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + /* Clear D0FIFO-port */ + buffer = hw_usb_read_fifosel(p_utr, USB_D0USE); + if ((buffer & USB_CURPIPE) == pipe) + { + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(p_utr, (uint16_t) USB_PIPE0, (uint16_t) USB_D0USE, USB_FALSE); + + /* DMA Transfer request disable */ + hw_usb_clear_dreqe(p_utr, USB_D0USE); + } + + /* Clear D1FIFO-port */ + buffer = hw_usb_read_fifosel(p_utr, USB_D1USE); + if ((buffer & USB_CURPIPE) == pipe) + { + /* Changes the FIFO port by the pipe. */ + usb_cstd_chg_curpipe(p_utr, (uint16_t) USB_PIPE0, (uint16_t) USB_D1USE, USB_FALSE); + + /* DMA Transfer request disable */ + hw_usb_clear_dreqe(p_utr, USB_D1USE); + } + #endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + + /* Do Aclr */ + usb_cstd_do_aclrm(p_utr, pipe); + + /* FIFO buffer SPLIT transaction initialized */ + hw_usb_set_csclr(p_utr, pipe); + + /* Call Back */ + if (USB_NULL != g_p_usb_pstd_pipe[pipe]) + { + /* Transfer information set */ + g_p_usb_pstd_pipe[pipe]->tranlen = g_usb_pstd_data_cnt[pipe]; + g_p_usb_pstd_pipe[pipe]->status = status; + g_p_usb_pstd_pipe[pipe]->pipectr = hw_usb_read_pipectr(p_utr, pipe); + + if (USB_NULL != (g_p_usb_pstd_pipe[pipe]->complete)) + { + (g_p_usb_pstd_pipe[pipe]->complete)(g_p_usb_pstd_pipe[pipe], USB_NULL, USB_NULL); + } + + #if (BSP_CFG_RTOS == 0) + g_p_usb_pstd_pipe[pipe] = (usb_utr_t *) USB_NULL; + #else /* (BSP_CFG_RTOS == 0) */ + #if (BSP_CFG_RTOS == 1) + USB_REL_BLK(1, g_p_usb_pstd_pipe[pipe]); + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + vPortFree(g_p_usb_pstd_pipe[pipe]); + #endif /* #if (BSP_CFG_RTOS == 1) */ + g_p_usb_pstd_pipe[pipe] = (usb_utr_t *) USB_NULL; + usb_cstd_pipe_msg_re_forward(p_utr->ip, pipe); + #endif /* (BSP_CFG_RTOS == 0) */ + } +} + +/****************************************************************************** + * End of function usb_pstd_forced_termination + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_interrupt_clock + * Description : Not processed as the functionality is provided by R8A66597(ASSP). + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_interrupt_clock (uint8_t usb_ip) +{ + if (g_usb_cstd_suspend_mode != USB_NORMAL_MODE) + { + hw_usb_set_suspendm(usb_ip); /* UTMI Normal Mode (Not Suspend Mode) */ + usb_cpu_delay_1us(USB_CPU_DELAY_US); + g_usb_cstd_suspend_mode = USB_NORMAL_MODE; + } +} + +/****************************************************************************** + * End of function usb_pstd_interrupt_clock + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_self_clock + * Description : Not processed as the functionality is provided by R8A66597(ASSP). + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_self_clock (uint8_t usb_ip) +{ + if (g_usb_cstd_suspend_mode != USB_NORMAL_MODE) + { + hw_usb_set_suspendm(usb_ip); /* UTMI Normal Mode (Not Suspend Mode) */ + usb_cpu_delay_1us(USB_CPU_DELAY_US); + g_usb_cstd_suspend_mode = USB_NORMAL_MODE; + } +} + +/****************************************************************************** + * End of function usb_pstd_self_clock + ******************************************************************************/ + +/****************************************************************************** + * Function Name : usb_pstd_stop_clock + * Description : Not processed as the functionality is provided by R8A66597(ASSP). + * Arguments : none + * Return value : none + ******************************************************************************/ +void usb_pstd_stop_clock (uint8_t usb_ip) +{ + g_usb_cstd_suspend_mode = USB_SUSPEND_MODE; + hw_usb_clear_suspm(usb_ip); /* UTMI Suspend Mode */ +} + +/****************************************************************************** + * End of function usb_pstd_stop_clock + ******************************************************************************/ +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c new file mode 100644 index 0000000000..c768cd722f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c @@ -0,0 +1,408 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ + +#include +#include + +#include "../driver/inc/r_usb_typedef.h" +#include "../driver/inc/r_usb_extern.h" +#include "inc/r_usb_bitdefine.h" +#include "inc/r_usb_reg_access.h" + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/****************************************************************************** + * Function Name : hw_usb_pset_dprpu + * Description : Set DPRPU-bit SYSCFG0 register. + * : (Enable D+Line pullup when PeripheralController function is selected) + * Arguments : usb_utr_t *ptr : USB internal structure. Selects USB channel. + * Return value : none + ******************************************************************************/ +void hw_usb_pset_dprpu (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->SYSCFG |= USB_DPRPU; + } + else + { + USB_M1->SYSCFG |= USB_DPRPU; + } +} + +/****************************************************************************** + * End of function hw_usb_pset_dprpu + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pclear_dprpu + * Description : Clear DPRPU-bit of the SYSCFG0 register. + * : (Disable D+Line pullup when PeripheralController function is + * : selected.) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_pclear_dprpu (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->SYSCFG = (uint16_t) (USB_M0->SYSCFG & (~USB_DPRPU)); + } + else + { + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_DPRPU)); + } +} + +/****************************************************************************** + * End of function hw_usb_pclear_dprpu + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pset_wkup + * Description : Set WKUP-bit DVSTCTR register. + * : (Output Remote wakeup signal when PeripheralController function is selected) + * Arguments : usb_utr_t *ptr : Pointer to usb_utr_t structure. + * Return value : none + ******************************************************************************/ +void hw_usb_pset_wkup (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->DVSTCTR0 |= USB_WKUP; + } + else + { + USB_M1->DVSTCTR0 |= USB_WKUP; + } +} + +/****************************************************************************** + * End of function hw_usb_pset_wkup + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pset_enb_rsme + * Description : Enable interrupt from RESUME + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_pset_enb_rsme (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->INTENB0 |= USB_RSME; + } + else + { + USB_M1->INTENB0 |= USB_RSME; + } +} + +/****************************************************************************** + * End of function hw_usb_pset_enb_rsme + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pclear_enb_rsme + * Description : Disable interrupt from RESUME + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_pclear_enb_rsme (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->INTENB0 = (uint16_t) (USB_M0->INTENB0 & (~USB_RSME)); + } + else + { + USB_M1->INTENB0 = (uint16_t) (USB_M1->INTENB0 & (~USB_RSME)); + } +} + +/****************************************************************************** + * End of function hw_usb_pclear_enb_rsme + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pclear_sts_resm + * Description : Clear interrupt status of RESUME. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_pclear_sts_resm (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->INTSTS0 = (uint16_t) ~USB_RESM; + } + else + { + USB_M1->INTSTS0 = (uint16_t) ~USB_RESM; + } +} + +/****************************************************************************** + * End of function hw_usb_pclear_sts_resm + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pclear_sts_valid + * Description : Clear the Setup Packet Reception interrupt flag. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_pclear_sts_valid (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->INTSTS0 = (uint16_t) ~USB_VALID; + } + else + { + USB_M1->INTSTS0 = (uint16_t) ~USB_VALID; + } +} + +/****************************************************************************** + * End of function hw_usb_pclear_sts_valid + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pset_ccpl + * Description : Enable termination of control transfer status stage. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_pset_ccpl (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->DCPCTR |= USB_CCPL; + } + else + { + USB_M1->DCPCTR |= USB_CCPL; + } +} + +/****************************************************************************** + * End of function hw_usb_pset_ccpl + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pmodule_init + * Description : + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_pmodule_init (uint8_t usb_ip) +{ + if (USB_CFG_IP0 == usb_ip) + { + USB_M0->SYSCFG |= USB_SCKE; + + /* WAIT_LOOP */ + while (USB_SCKE != (USB_M0->SYSCFG & USB_SCKE)) + { + /* Wait for Set of SCKE */ + } + + #if defined(USB_SUPPORT_PHYSLEW) + USB_M0->PHYSLEW = USB_PHYSLEW_VALUE; + #endif /* defined(USB_SUPPORT_PHYSLEW) */ + + USB_M0->SYSCFG &= (uint16_t) (~USB_DRPD); + + USB_M0->SYSCFG |= USB_USBE; + + #if defined(USB_SUPPORT_HOCO_MODULE) + if (0 == (R_SYSTEM->SCKSCR & R_SYSTEM_SCKSCR_CKSEL_Msk)) + { + /* Use HOCO */ + hw_usb_set_uckselc(); + } + #endif /* defined(USB_SUPPORT_HOCO_MODULE) */ + + USB_M0->CFIFOSEL = USB0_CFIFO_MBW; + USB_M0->D0FIFOSEL = USB0_D0FIFO_MBW; + USB_M0->D1FIFOSEL = USB0_D1FIFO_MBW; + #if USB_CFG_ENDIAN == USB_CFG_BIG + USB_M0->CFIFOSEL |= USB_BIGEND; + USB_M0->D0FIFOSEL |= USB_BIGEND; + USB_M0->D1FIFOSEL |= USB_BIGEND; + #endif /* USB_CFG_ENDIAN == USB_CFG_BIG */ + + USB_M0->INTENB0 = (USB_BEMPE | USB_BRDYE | USB_VBSE | USB_DVSE | USB_CTRE); + } + else + { + #if defined(USB_HIGH_SPEED_MODULE) + USB_M1->PHYSET |= (USB_DIRPD | USB_CLKSEL); + + #if USB_CFG_CLKSEL == USB_CFG_OTHER + USB_M1->PHYSET |= USB_HSEB; + #else /* USB_CFG_CLKSEL == USB_CFG_OTHER */ + #if USB_USBMCLK_HZ == USB_CLK_48MHZ + USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; + USB_M1->PHYSET |= USB_CLKSEL_48; + #endif /* USB_USBMCLK_HZ == USB_CLK_48MHZ */ + + #if USB_USBMCLK_HZ == USB_CLK_24MHZ + USB_M1->PHYSET &= (uint16_t) ~USB_HSEB; + #endif /* USB_USBMCLK_HZ == USB_CLK_24MHZ */ + + #if USB_USBMCLK_HZ == USB_CLK_20MHZ + USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; + USB_M1->PHYSET |= USB_CLKSEL_20; + #endif /* USB_USBMCLK_HZ == USB_CLK_20MHZ */ + + #if USB_USBMCLK_HZ == USB_CLK_12MHZ + USB_M1->PHYSET &= (uint16_t) ~USB_CLKSEL; + USB_M1->PHYSET |= USB_CLKSEL_12; + #endif /* USB_USBMCLK_HZ == USB_CLK_12MHZ */ + #endif /* USB_CFG_CLKSEL == USB_CFG_OTHER */ + + usb_cpu_delay_1us((uint16_t) 1); /* wait 1usec */ + + USB_M1->PHYSET = (uint16_t) (USB_M1->PHYSET & (~USB_DIRPD)); + usb_cpu_delay_xms(1); /* wait 1msec */ + + #if USB_CFG_CLKSEL != USB_CFG_OTHER + USB_M1->PHYSET = (uint16_t) (USB_M1->PHYSET & (~USB_PLLRESET)); + #endif /* USB_CFG_CLKSEL != USB_CFG_OTHER */ + + USB_M1->SYSCFG = (uint16_t) (USB_M1->SYSCFG & (~USB_DRPD)); + + USB_M1->SYSCFG |= USB_USBE; + + USB_M1->LPSTS |= USB_SUSPENDM; + + #if USB_CFG_CLKSEL != USB_CFG_OTHER + + /* WAIT_LOOP */ + while (USB_PLLLOCK != (USB_M1->PLLSTA & USB_PLLLOCK)) + { + /* Wait for PLL Lock */ + } + #endif /* USB_CFG_CLKSEL != USB_CFG_OTHER */ + + USB_M1->BUSWAIT = (USB_CFG_BUSWAIT | USB_BWAIT_B11_B8_WRITE); + + USB_M1->PHYSET |= USB_REPSEL_16; + + USB_M1->CFIFOSEL = USB1_CFIFO_MBW; + USB_M1->D0FIFOSEL = USB1_D0FIFO_MBW; + USB_M1->D1FIFOSEL = USB1_D1FIFO_MBW; + + #if USB_CFG_ENDIAN == USB_CFG_BIG + USB_M1->CFIFOSEL |= USB_BIGEND; + USB_M1->D0FIFOSEL |= USB_BIGEND; + USB_M1->D1FIFOSEL |= USB_BIGEND; + #endif /* USB_CFG_ENDIAN == USB_CFG_BIG */ + + USB_M1->INTSTS0 = 0; + USB_M1->INTENB0 = (USB_BEMPE | USB_BRDYE | USB_VBSE | USB_DVSE | USB_CTRE); + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + } + + #if (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) + hw_usb_set_vdcen(); + #endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ +} + +/****************************************************************************** + * End of function hw_usb_pmodule_init + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pcontrol_dprpu + * Description : Set/Clear DPRPU-bit SYSCFG0 register. + * Arguments : usb_ip : USB module number (USB_IP0/USB_IP1) + * : state : USB_ON (D+ Line Pullup Enable) + * : : USB_OFF (D+ Line Pullup Disable) + * Return value : none + ******************************************************************************/ +void hw_usb_pcontrol_dprpu (uint8_t usb_ip, uint8_t state) +{ + if (USB_IP0 == usb_ip) + { + if (USB_ON == state) + { + USB_M0->SYSCFG |= (uint16_t) (USB_DPRPU); + } + else + { + USB_M0->SYSCFG &= (uint16_t) (~USB_DPRPU); + } + } + else + { + if (USB_ON == state) + { + USB_M1->SYSCFG |= (uint16_t) (USB_DPRPU); + } + else + { + USB_M1->SYSCFG &= (uint16_t) (~USB_DPRPU); + } + } +} + +/****************************************************************************** + * End of function hw_usb_pcontrol_dprpu + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_pcontrol_dcpctr_pid + * Description : Set ACK /STALL to PID bit for DCPCTR register + * Arguments : usb_ip : USB module number (USB_IP0/USB_IP1) + * : data : USB_PID_BUF (ACK) + * : : USB_PID_STALL (STALL) + * Return value : none + ******************************************************************************/ +void hw_usb_pcontrol_dcpctr_pid (uint8_t usb_ip, uint16_t data) +{ + if (USB_IP0 == usb_ip) + { + USB_M0->DCPCTR &= (uint16_t) (~USB_PID); + if (data == USB_SETUP_STATUS_ACK) + { + USB_M0->DCPCTR |= (uint16_t) USB_PID_BUF; + } + else + { + USB_M0->DCPCTR |= (uint16_t) USB_PID_STALL; + } + } + else + { + USB_M1->DCPCTR &= (uint16_t) (~USB_PID); + if (data == USB_SETUP_STATUS_ACK) + { + USB_M1->DCPCTR |= (uint16_t) USB_PID_BUF; + } + else + { + USB_M1->DCPCTR |= (uint16_t) USB_PID_STALL; + } + } +} + +/****************************************************************************** + * End of function hw_usb_pcontrol_dcpctr_pid + ******************************************************************************/ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_vin/r_vin.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_vin/r_vin.c new file mode 100644 index 0000000000..770865972f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_vin/r_vin.c @@ -0,0 +1,456 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_vin.h" +#include "r_vin_device_types.h" +#include "r_capture_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define VIN_OPEN (0x5256494E) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * vin_prv_ns_callback)(capture_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile vin_prv_ns_callback)(capture_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +const capture_api_t g_capture_on_vin = +{ + .open = R_VIN_Open, + .close = R_VIN_Close, + .captureStart = R_VIN_CaptureStart, + .statusGet = R_VIN_StatusGet, +}; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +void vin_status_isr(void); +void vin_error_isr(void); +static void vin_common_isr(vin_event_t event); + +static fsp_err_t vin_stop(vin_instance_ctrl_t * const p_ctrl); +static void vin_isr_enable(vin_irq_cfg_t const * irq_cfg, void * p_context); +static void vin_isr_disable(vin_irq_cfg_t const * irq_cfg); + +static void vin_call_callback(vin_instance_ctrl_t * p_ctrl, capture_callback_args_t * p_args); + +/*******************************************************************************************************************//** + * @addtogroup VIN + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/******************************************************************************************************************//** + * Initialize the VIN peripheral. + * + * @retval FSP_SUCCESS The channel was successfully opened. + * @retval FSP_ERR_ASSERTION One or both of the parameters was NULL. + * @retval FSP_ERR_ALREADY_OPEN The instance is already opened. + **********************************************************************************************************************/ +fsp_err_t R_VIN_Open (capture_ctrl_t * const p_api_ctrl, capture_cfg_t const * const p_cfg) +{ + vin_instance_ctrl_t * p_ctrl = (vin_instance_ctrl_t *) p_api_ctrl; + +#if VIN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(p_ctrl); + FSP_ERROR_RETURN(VIN_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + p_ctrl->p_cfg = p_cfg; + vin_extended_cfg_t const * p_extend = p_cfg->p_extend; + + /* Start clocks to the VIN peripheral */ + R_BSP_MODULE_START(FSP_IP_MIPI_CSI, 0); + + /* Ensure VIN Module is in a good state for configuration */ + R_VIN->FC_b.CC = 0; // Ensure Continuous Capture and Startup are disabled before starting configuration + R_VIN->MC = p_extend->input_ctrl.cfg_mask & ~(R_VIN_MC_ST_Msk | R_VIN_MC_ME_Msk); // Main control register (Disable start bit and module enable) + + R_VIN->CSI_IFMD = p_extend->input_ctrl.csi_mode_mask; + R_VIN->CSIFLD = p_extend->input_ctrl.csi_detect_mask; + R_VIN->DMR = p_extend->conversion_ctrl.data_mode_mask; + R_VIN->SLPRC = p_extend->input_ctrl.preclip.line_start; + R_VIN->ELPRC = p_extend->input_ctrl.preclip.line_end; + R_VIN->SPPRC = p_extend->input_ctrl.preclip.pixel_start; + R_VIN->EPPRC = p_extend->input_ctrl.preclip.pixel_end; + R_VIN->IS = p_extend->input_ctrl.image_stride; + R_VIN->MB1 = (uint32_t) p_extend->output_ctrl.image_buffer[0]; + R_VIN->MB2 = (uint32_t) p_extend->output_ctrl.image_buffer[1]; + R_VIN->MB3 = (uint32_t) p_extend->output_ctrl.image_buffer[2]; + R_VIN->UVAOF = (uint32_t) p_extend->conversion_data.uv_address; + + R_VIN->MC_b.BPS = p_extend->input_ctrl.cfg_bits.color_space_convert_bypass; // Set color space bypass register after other settings, according to Figure VIN initialization procedure of the relevant hardware manual + + R_VIN->CSCE1 = p_extend->conversion_data.yc_rgb_conversion_setting_1_mask; + R_VIN->CSCE2 = p_extend->conversion_data.yc_rgb_conversion_setting_2_mask; + R_VIN->CSCE3 = p_extend->conversion_data.yc_rgb_conversion_setting_3_mask; + R_VIN->CSCE4 = p_extend->conversion_data.yc_rgb_conversion_setting_4_mask; + + R_VIN->YCCR1 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[0].setting_1_mask; + R_VIN->YCCR2 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[0].setting_2_mask; + R_VIN->YCCR3 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[0].setting_3_mask; + + R_VIN->CBCCR1 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[1].setting_1_mask; + R_VIN->CBCCR2 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[1].setting_2_mask; + R_VIN->CBCCR3 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[1].setting_3_mask; + + R_VIN->CRCCR1 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[2].setting_1_mask; + R_VIN->CRCCR2 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[2].setting_2_mask; + R_VIN->CRCCR3 = p_extend->conversion_data.rgb_to_yuv_conversion_settings[2].setting_3_mask; + + R_VIN->MC_b.YUV444 = p_extend->input_ctrl.cfg_bits.yuv444_conversion; // Set YUV444 conversion register after other settings, according to Figure VIN initialization procedure of the relevant hardware manual + R_VIN->MC_b.DC = p_extend->input_ctrl.cfg_bits.dithering_mode; // Set Dithering mode register after other settings, according to Figure VIN initialization procedure of the relevant hardware manual + + R_VIN->UDS_PASS_BWIDTH = p_extend->conversion_data.uds_bwidth_mask; + R_VIN->UDS_CLIP_SIZE = p_extend->conversion_data.uds_clipping_mask; + R_VIN->MC_b.SCLE = p_extend->input_ctrl.cfg_bits.scaling_enable; + R_VIN->UDS_CTRL = p_extend->conversion_data.uds_ctrl_mask; + + R_VIN->IE = p_extend->interrupt_cfg.status_enable_mask; + R_VIN->SI = p_extend->interrupt_cfg.scanline_compare_value; + + p_ctrl->p_callback_memory = NULL; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + vin_isr_enable(&p_extend->interrupt_cfg.status, (void *) p_ctrl); + vin_isr_enable(&p_extend->interrupt_cfg.error, (void *) p_ctrl); + + /* Open MIPI CSI */ + mipi_csi_api_t const * p_csi_api = p_extend->p_mipi_csi_instance->p_api; + mipi_csi_cfg_t const * p_csi_cfg = p_extend->p_mipi_csi_instance->p_cfg; + mipi_csi_ctrl_t * p_csi_ctrl = p_extend->p_mipi_csi_instance->p_ctrl; + fsp_err_t err = p_csi_api->open(p_csi_ctrl, p_csi_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err) + + /* Mark control block as opened */ + p_ctrl->open = VIN_OPEN; + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Close VIN and display data instances, disable interrupts, and power-off the module. + * - NOTE: Application shall issue stop command to the peripheral and wait at least one full frame before calling + * CSI_Stop, after ensuring MIPI CSI reception is no longer active by checking data returned by MIPI_CSI GetStatus() + * + * @retval FSP_SUCCESS The channel is successfully closed. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + **********************************************************************************************************************/ +fsp_err_t R_VIN_Close (capture_ctrl_t * const p_api_ctrl) +{ + vin_instance_ctrl_t * p_ctrl = (vin_instance_ctrl_t *) p_api_ctrl; + +#if VIN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_ctrl->p_cfg); + FSP_ASSERT(p_ctrl->p_cfg->p_extend); + FSP_ERROR_RETURN(VIN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + capture_cfg_t const * const p_cfg = p_ctrl->p_cfg; + vin_extended_cfg_t const * p_extend = p_cfg->p_extend; + + fsp_err_t err = vin_stop(p_ctrl); + FSP_ERROR_LOG(err); + FSP_PARAMETER_NOT_USED(err); /* Suppress dead store when FSP_ERROR_LOG is not enabled */ + + /* Close MIPI CSI */ + mipi_csi_api_t const * p_csi_api = p_extend->p_mipi_csi_instance->p_api; + mipi_csi_ctrl_t * p_csi_ctrl = p_extend->p_mipi_csi_instance->p_ctrl; + err = p_csi_api->close(p_csi_ctrl); + FSP_ERROR_LOG(err); + + /* Set control block to closed */ + p_ctrl->open = 0U; + + vin_isr_disable(&p_extend->interrupt_cfg.status); + vin_isr_disable(&p_extend->interrupt_cfg.error); + + /* Stop clocks to the MIPI CSI peripheral */ + R_BSP_MODULE_STOP(FSP_IP_MIPI_CSI, 0); + + return err; +} + +/******************************************************************************************************************//** + * Start video capture. + * - NOTE: For best results, camera should not be transmitting data until after VIN capture start has been called. + * + * @retval FSP_SUCCESS Data is successfully written to the D/A Converter. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + * @retval FSP_ERR_IN_USE The physical interface is currently in use. + * @retval FSP_ERR_INVALID_STATE VIN is already in video mode. + * @retval FSP_ERR_UNSUPPORTED p_buffer parameter is not supported. + **********************************************************************************************************************/ +fsp_err_t R_VIN_CaptureStart (capture_ctrl_t * const p_api_ctrl, uint8_t * const p_buffer) +{ + vin_instance_ctrl_t * p_ctrl = (vin_instance_ctrl_t *) p_api_ctrl; +#if VIN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_ctrl->p_cfg); + FSP_ASSERT(p_ctrl->p_cfg->p_extend); + FSP_ERROR_RETURN(VIN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(!R_VIN->MC_b.ME, FSP_ERR_INVALID_STATE); + FSP_ERROR_RETURN(!R_VIN->FC_b.CC, FSP_ERR_INVALID_STATE); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + + capture_cfg_t const * const p_cfg = p_ctrl->p_cfg; + vin_extended_cfg_t const * p_extend = p_cfg->p_extend; +#if VIN_CFG_PARAM_CHECKING_ENABLE + if (!p_extend->output_ctrl.use_runtime_buffer && (NULL != p_buffer)) + { + return FSP_ERR_UNSUPPORTED; + } +#endif + + /*---------------------------------------------------------------------------------------------------- + * Set Capture buffers if not provided by configuration + * - Note: It is highly recommended to configure capture buffers via FSP configuration tool + *----------------------------------------------------------------------------------------------------*/ + if (p_extend->output_ctrl.use_runtime_buffer) + { +#if VIN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_buffer); +#endif + R_VIN->MB1 = (uint32_t) p_buffer; + R_VIN->MB2 = (uint32_t) p_buffer; + R_VIN->MB3 = (uint32_t) p_buffer; + } + else + { + FSP_PARAMETER_NOT_USED(p_buffer); + } + + /* Start VIN */ + R_VIN->MC_b.ST = 0x1; // Initialize the internal state of VIN + FSP_REGISTER_READ(R_VIN->MC_b.ST); // Wait at least 10 cycles of aclk (ICLK) + FSP_REGISTER_READ(R_VIN->MC_b.ST); + FSP_REGISTER_READ(R_VIN->MC_b.ST); + FSP_REGISTER_READ(R_VIN->MC_b.ST); + FSP_REGISTER_READ(R_VIN->MC_b.ST); + FSP_REGISTER_READ(R_VIN->MC_b.ST); + FSP_REGISTER_READ(R_VIN->MC_b.ST); + FSP_REGISTER_READ(R_VIN->MC_b.ST); + FSP_REGISTER_READ(R_VIN->MC_b.ST); + FSP_REGISTER_READ(R_VIN->MC_b.ST); + + R_VIN->UDS_SCALE = p_extend->conversion_data.uds_scale_mask; + + R_VIN->MC_b.ME = 1; // Start VIN + R_VIN->FC_b.CC = 1; // Put VIN in continuous frame capture mode waiting for video input + + /* Start MIPI CSI */ + mipi_csi_api_t const * p_csi_api = p_extend->p_mipi_csi_instance->p_api; + mipi_csi_ctrl_t * p_csi_ctrl = p_extend->p_mipi_csi_instance->p_ctrl; + fsp_err_t err = p_csi_api->start(p_csi_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err) + + return FSP_SUCCESS; +} + +/******************************************************************************************************************//** + * Provide information about current VIN status. + * + * @retval FSP_SUCCESS Information read successfully. + * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance is not open. + **********************************************************************************************************************/ +fsp_err_t R_VIN_StatusGet (capture_ctrl_t * const p_api_ctrl, capture_status_t * p_status) +{ +#if VIN_CFG_PARAM_CHECKING_ENABLE + vin_instance_ctrl_t * p_ctrl = (vin_instance_ctrl_t *) p_api_ctrl; + FSP_ASSERT(NULL != p_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(VIN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_api_ctrl); +#endif + uint32_t ** buffer_pointer = (uint32_t **) (&R_VIN->MB1); + + p_status->data_size = R_VIN->LC; + p_status->p_buffer = (R_VIN->MS_b.FBS >= 0x3) ? NULL : *(buffer_pointer + R_VIN->MS_b.FBS); // Buffer currently in use + p_status->state = R_VIN->MC_b.ME ? CAPTURE_STATE_BUSY : CAPTURE_STATE_IDLE; // Module enabled but no capture in progress + p_status->state = R_VIN->MS_b.CA ? CAPTURE_STATE_IN_PROGRESS : p_status->state; // Module enabled and capture in progress + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup VIN) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Private helper functions + **********************************************************************************************************************/ + +/************************************************************************************************************************************* + * Capture Stop - Follow procedure outlined in Figure "Stopping capture operation" in the VIN section of the relevant hardware manual + *************************************************************************************************************************************/ +static fsp_err_t vin_stop (vin_instance_ctrl_t * const p_ctrl) +{ + capture_cfg_t const * const p_cfg = p_ctrl->p_cfg; + vin_extended_cfg_t const * p_extend = p_cfg->p_extend; + + fsp_err_t err = R_VIN->MC_b.ME ? FSP_SUCCESS : FSP_ERR_INVALID_STATE; + FSP_ERROR_LOG(err); + FSP_PARAMETER_NOT_USED(err); /* Suppress dead store when FSP_ERROR_LOG is not enabled */ + + R_VIN->MC_b.ME = 0; // Stop VIN + R_VIN->FC_b.CC = 0; // Disable VIN continuous capture mode + + if (R_VIN->MS_b.CA || R_VIN->MTCSTOP_b.OUTSTAND) + { + FSP_ERROR_LOG(FSP_ERR_IN_USE); + } + + /* Stop MIPI CSI */ + mipi_csi_api_t const * p_csi_api = p_extend->p_mipi_csi_instance->p_api; + mipi_csi_ctrl_t * p_csi_ctrl = p_extend->p_mipi_csi_instance->p_ctrl; + err = p_csi_api->stop(p_csi_ctrl); + FSP_ERROR_LOG(err); + + R_VIN->MC_b.SCLE = 0; // Disable UDS scaling + + return err; +} + +/*********************************************************************************************************************** + * Enable the specified ISR and add the control structure to the ISR context lookup table. + **********************************************************************************************************************/ +static void vin_isr_enable (vin_irq_cfg_t const * irq_cfg, void * p_context) +{ + R_BSP_IrqCfgEnable(irq_cfg->irq, irq_cfg->ipl, p_context); +} + +/*********************************************************************************************************************** + * Disable the specified ISR + **********************************************************************************************************************/ +static void vin_isr_disable (vin_irq_cfg_t const * irq_cfg) +{ + R_BSP_IrqDisable(irq_cfg->irq); + R_FSP_IsrContextSet(irq_cfg->irq, NULL); +} + +/*********************************************************************************************************************** + * Interrupt Service Routines + **********************************************************************************************************************/ + +/*---------------------------------------------------------------------------------------------------- + * Status Interrupt Service Routine + *--------------------------------------------------------------------------------------------------*/ +void vin_status_isr (void) +{ + vin_common_isr(VIN_EVENT_NOTIFY); +} + +/*---------------------------------------------------------------------------------------------------- + * Error Interrupt Service Routine + *--------------------------------------------------------------------------------------------------*/ +void vin_error_isr (void) +{ + vin_common_isr(VIN_EVENT_ERROR); +} + +/*---------------------------------------------------------------------------------------------------- + * Common ISR Handler + *--------------------------------------------------------------------------------------------------*/ +void vin_common_isr (vin_event_t event) +{ + capture_callback_args_t args; + IRQn_Type irq = R_FSP_CurrentIrqGet(); + vin_instance_ctrl_t * p_ctrl = (vin_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + vin_module_status_t module_status = (vin_module_status_t) R_VIN->MS; + vin_interrupt_status_t interrupt_status = (vin_interrupt_status_t) R_VIN->INTS; + args.event = event; + args.event_status = module_status.mask; + args.interrupt_status = interrupt_status.mask; + args.p_buffer = NULL; + if (interrupt_status.bits.frame_complete) + { + uint32_t ** buffer_pointer = (uint32_t **) (&R_VIN->MB1); + args.p_buffer = (uint8_t *) ((R_VIN->MS_b.FBS >= 0x3) ? NULL : *(buffer_pointer + R_VIN->MS_b.FMS)); // Buffer currently in use + } + + args.p_context = p_ctrl->p_context; + + R_VIN->INTS = interrupt_status.mask | (R_VIN_INTS_FOS_Msk | R_VIN_INTS_ARES_Msk | R_VIN_INTS_FIS2_Msk); // FOS, ARES, FIS2 are cleared by writing '1'. Other bits are status/state, updated by the module. + R_BSP_IrqStatusClear(irq); + vin_call_callback(p_ctrl, &args); +} + +/*********************************************************************************************************************** + * Calls user callback + * + * @param[in] p_ctrl Pointer to VIN instance control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void vin_call_callback (vin_instance_ctrl_t * p_ctrl, capture_callback_args_t * p_args) +{ + capture_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + capture_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + vin_prv_ns_callback p_callback = (vin_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_vin/r_vin_device_types.h b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_vin/r_vin_device_types.h new file mode 100644 index 0000000000..c1273f0637 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_vin/r_vin_device_types.h @@ -0,0 +1,457 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*******************************************************************************************************************//** + * @addtogroup VIN + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_VIN_DEVICE_TYPES_H +#define R_VIN_DEVICE_TYPES_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_vin_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Type definitions + **********************************************************************************************************************/ + +/** VIN Interface Mode Type */ +typedef enum e_vin_interlace_mode +{ + VIN_INTERLACE_MODE_ODD_FIELD_CAPTURE = 0, ///< Odd-field (field 1) Capture Mode + VIN_INTERLACE_MODE_ODD_EVEN_FIELD_CAPTURE = 1, ///< Odd/Even-field Capture Mode + VIN_INTERLACE_MODE_EVEN_FEILD_CAPTURE = 2, ///< Even-field Cature Mode +} vin_interlace_mode_t; + +/** VIN Dithering Mode */ +typedef enum e_vin_dithering_mode +{ + VIN_DITHERING_MODE_WITH_ADDITION = 0, ///< Dithereing with Cumulative Addition + VIN_DITHERING_MODE_ORDERED_1 = 1, ///< Ordered Dithering 1 + VIN_DITHERING_MODE_ORDERED_2 = 2, ///< Ordered Dithering 2 +} vin_dithering_mode_t; + +/** VIN Input format */ +typedef enum e_vin_input_format +{ + VIN_INPUT_FORMAT_YCBCR422_8_BIT = 1, ///< Input Format 8-Bit YCbCr-422 + VIN_INPUT_FORMAT_YCBCR422_10_BIT = 3, ///< Input Format 10-Bit YCbCr-42 + VIN_INPUT_FORMAT_RAW8 = 4, ///< Input Format RAW8 + VIN_INPUT_FORMAT_RGB888_24_BIT = 6, ///< Input Format 24-Bit RGB888 +} vin_input_format_t; + +/** VIN Data Type Select */ +typedef enum e_vin_data_type +{ + VIN_DATA_TYPE_YUV422_8_BIT = 0x1E, ///< Data Type YUV422 8-bit + VIN_DATA_TYPE_YUV422_10_BIT = 0x1F, ///< Data Type YUV422 10-bit + VIN_DATA_TYPE_RGB888_BIT = 0x24, ///< Data Type RGB888 + VIN_DATA_TYPE_RAW8_BIT = 0x2A, ///< Data Type RAW8 +} vin_data_type_t; + +/** VIN Input YUV444 Conversion Mode */ +typedef enum e_vin_yuv444_conversion_mode +{ + VIN_YUV444_CONVERSION_MODE_DATA_EXTEND = 0, ///< The data of CbCr to be interpolated holds the data one pixel before + VIN_YUV444_CONVERSION_MODE_INTERPOLATE = 1, ///< Generates CbCr data to be interpolated +} vin_yuv444_conversion_mode_t; + +/** VIN Pixel Data Clipping */ +typedef enum e_vin_pixel_data_clipping +{ + VIN_PIXEL_DATA_CLIPPING_DEFAULT = 0x0, ///< Default clipping mode + VIN_PIXEL_DATA_CLIPPING_NIBBLE = 0x1, ///< Lower 4-bits clipping mode + VIN_PIXEL_DATA_CLIPPING_DISABLED = 0x3, ///< Clipping mode disabled +} vin_pixel_data_clipping_t; + +/** VIN Conversion Mode */ +typedef enum e_vin_conversion_mode +{ + VIN_CONVERSION_MODE_NONE = 0, ///< Data is not converted before output + VIN_CONVERSION_MODE_RGB_TO_ARGB = 1, ///< RGB input Data is converted to ARGB before output + VIN_CONVERSION_MODE_YC_SEPARATED = 2, ///< Y and CbCr data are separated before output +} vin_conversion_mode_t; + +/** VIN YC Transform Mode */ +typedef enum e_vin_yc_transform_mode +{ + VIN_YC_TRANSFORM_MODE_Y_CBCR = 0, ///< Y and CbCr data are transferred to memory + VIN_YC_TRANSFORM_MODE_Y = 1, ///< Y data is transferred to memory as 8-bit data + VIN_YC_TRANSFORM_MODE_Y10_CBCR = 2, ///< 10-bit Y data and 8-bit CbCr data are transferred to memory + VIN_YC_TRANSFORM_MODE_Y10 = 3, ///< 10-bit Y data is transferred to memory +} vin_yc_transform_mode_t; + +/** VIN Interpolation Mode */ +typedef enum e_vin_interpolation_mode +{ + VIN_INTERPOLATION_MODE_BILINEAR = 0, ///< Y and CbCr data are transferred to memory + VIN_INTERPOLATION_MODE_NEIGHBOR = 1, ///< Y data is transferred to memory as 8-bit data +} vin_interpolation_mode_t; + +/** VIN Input Control Structure */ +typedef struct st_vin_input_ctrl +{ + union + { + struct + { + uint32_t module_enable : 1; ///< Module dnable + uint32_t color_space_convert_bypass : 1; ///< Colo space conversion bypass mode (1: conversion is not performed) + uint32_t : 1; + vin_interlace_mode_t interlace_mode : 2; ///< Interlace mode selection + uint32_t : 1; + uint32_t big_endian : 1; ///< Big endian enable + uint32_t : 7; + vin_dithering_mode_t dithering_mode : 2; ///< Dithering mode control + vin_input_format_t input_mode : 3; ///< input format selection + uint32_t : 1; + uint32_t lut_enable : 1; ///< Look Up Table enabled for 10 to 8 bit conversion + uint32_t : 1; + uint32_t startup : 1; ///< Set 1 to perform initialization + uint32_t : 1; + uint32_t dithering_direction : 1; ///< Dithering direction + vin_yuv444_conversion_mode_t yuv444_conversion : 1; ///< yuv444 conversion type + uint32_t scaling_enable : 1; ///< Enable or disable scaling by the UDS + uint32_t : 1; + vin_pixel_data_clipping_t pixel_data_clipping : 2; ///< Pixel data clipping + uint32_t : 2; + } cfg_bits; + uint32_t cfg_mask; + }; + + struct + { + uint16_t line_start; ///< Line Start Number + uint16_t line_end; ///< Line End Number + uint16_t pixel_start; ///< Pixel Start Number + uint16_t pixel_end; ///< Pixel End Number + } preclip; + union + { + struct + { + uint32_t virtual_channel : 4; ///< Virtual (0-15) Channel Select + uint32_t : 4; + vin_data_type_t data_type : 6; ///< Data Type Select + uint32_t : 11; + uint32_t sign_extend_disable : 1; ///< Data Extension Select (0: sign-extend, 1:zero-extend) + uint32_t : 6; + } csi_mode_bits; + uint32_t csi_mode_mask; + }; + + union + { + struct + { + uint32_t field_detect_enable : 1; ///< Field Detect Enable (0:Even field detect disabled, 1:Even field detect enabled) + uint32_t : 3; + uint32_t even_field_detect_enable : 1; ///< Even Field Detect Select (1: When even_field_number matches the field number [0] bit) + uint32_t : 11; + uint32_t even_field_number : 1; ///< Value for detecting even fields in an interlaced image + uint32_t : 15; + } csi_detect_bits; + uint32_t csi_detect_mask; + }; + + uint16_t image_stride; ///< Image Stride (Setting Unit: pixel) +} vin_input_ctrl_t; + +/** VIN Output Control Structure */ +typedef struct st_vin_output_ctrl +{ + uint8_t * image_buffer[3]; ///< Pointer to Image Buffer Memory Base (64-byte aligned) + bool use_runtime_buffer; ///< 1: use runtime buffer, 0: use static buffer +} vin_output_ctrl_t; + +/** VIN Conversion Control Structure */ +typedef struct st_vin_conversion_ctrl +{ + union + { + struct + { + vin_conversion_mode_t data_conversion_mode : 2; ///< Data Conversion Mode + uint32_t alpha_bit_value : 1; ///< Alpha-bit value for ARGB-1555 Output + uint32_t : 1; + uint32_t output_data_byte_swap : 1; ///< Output Data Byte Swap Enable + uint32_t : 3; + uint32_t extend_rgb_converted_data : 1; ///< Extend data to 32-bit RGB conversion (when conversion mode is not YC, separated) + uint32_t : 2; + uint32_t yc_data_transform_enable : 1; ///< Transfer Y and CbCr data as 10-bit data (according to input format) instead of yc_data_transform_mode + vin_yc_transform_mode_t yc_transform_mode : 3; ///< YC transfer method of YCbCr data when YC separation is selected data_conversion_mode + uint32_t : 9; + uint32_t rgb8888_alpha_value : 8; ///< Alpha value to be applied for converted RGB8888 output data format + } data_mode_bits; + uint32_t data_mode_mask; + }; +} vin_conversion_ctrl_t; + +/** VIN Conversion Data Structure */ +typedef struct st_vin_conversion_data +{ + uint32_t * uv_address; ///< Address for YC separation of YCbCr-422 UV data. (64-byte aligned) + + union + { + struct + { + uint32_t y_mul : 14; ///< Y Multiplication Coefficient2 for RGB Calculation + uint32_t : 2; + uint32_t round_down_disable : 1; ///< Round Down Disable + uint32_t : 15; + } yc_rgb_conversion_setting_1_bits; + uint32_t yc_rgb_conversion_setting_1_mask; + }; + + union + { + struct + { + uint32_t csub2 : 12; ///< CbCr Subtraction Coefficient 2 for RGB Calculation + uint32_t : 4; + uint32_t ysub2 : 12; ///< Y Subtraction Coefficient 2 for RGB Calculation + uint32_t : 4; + } yc_rgb_conversion_setting_2_bits; + uint32_t yc_rgb_conversion_setting_2_mask; + }; + + union + { + struct + { + uint32_t cgrmul2 : 14; ///< Cr Multiplication Coefficient 2 for G Calculation + uint32_t : 2; + uint32_t rcrmul2 : 14; ///< Cr multiplication Coefficient 2 for R Calculation + uint32_t : 2; + } yc_rgb_conversion_setting_3_bits; + uint32_t yc_rgb_conversion_setting_3_mask; + }; + + union + { + struct + { + uint32_t bcbmul2 : 14; ///< Cb Multiplication Coefficient 2 for B Calculation + uint32_t : 2; + uint32_t gcbmul2 : 14; ///< Cb Multiplication Coefficient 2 for G Calculation + uint32_t : 2; + } yc_rgb_conversion_setting_4_bits; + uint32_t yc_rgb_conversion_setting_4_mask; + }; + + union + { + struct + { + uint32_t : 16; + uint32_t ne_bcb : 1; ///< B/Cb Interpolation Method When Bilinear/Nearest Neighbor Interpolation is Selected (0: Bilinear, 1: Nearest Neighbor) + uint32_t ne_gy : 1; ///< G/Y Interpolation Method When Bilinear/Nearest Neighbor Interpolation is Selected (0: Bilinear, 1: Nearest Neighbor) + uint32_t ne_rcr : 1; ///< R/Cr Interpolation Method When Bilinear/Nearest Neighbor Interpolation is Selected (0: Bilinear, 1: Nearest Neighbor) + uint32_t : 1; + uint32_t pixel_interpolation : 1; ///< Specifies the method for interpolating pixel components at scale-up/down (Bilinear or multi-tap mode) + uint32_t : 7; + uint32_t bilinear_advanced : 1; ///< Bilinear or Nearest Neighbor Interpolation Characteristic Advanced Mode + uint32_t : 1; + uint32_t scale_up_pixel_count : 1; ///< Advanced Mode: Pixel Count at Scale Up (0: 1+(n-1)*scalar, 1: n*scalar) + uint32_t : 1; + } uds_ctrl_bits; + uint32_t uds_ctrl_mask; + }; + + union + { + struct + { + union + { + struct + { + uint16_t vfrac : 12; ///< Multiplier (Fractional Part) of Vertical Scaling Factor + uint16_t vmant : 4; ///< Multiplier (Integral Part) of Vertical Scaling Factor + } vertical_bits; + uint16_t vertical_mask; + }; + union + { + struct + { + uint16_t hfrac : 12; ///< Multiplier (Fractional Part) of Horizontal Scaling Factor + uint16_t hmant : 4; ///< Multiplier (Integral Part) of Horizontal Scaling Factor + } horizontal_bits; + uint16_t horizontal_mask; + }; + } uds_scale_bits; + uint32_t uds_scale_mask; + }; + + union + { + struct + { + uint32_t bwidth_v : 7; ///< Vertical Signal Passband at Image Scale-Up/Down + uint32_t : 9; + uint32_t bwidth_h : 7; ///< Horizontal Signal Passband at Image Scale-Up/Down + uint32_t : 9; + } uds_bwidth_bits; + uint32_t uds_bwidth_mask; + }; + + union + { + struct + { + uint32_t cl_vsize : 12; ///< Clipping Size of Vertical Pixel Count after Scale-Up/-Down + uint32_t : 4; + uint32_t cl_hsize : 12; ///< Clipping Size of Horizontal Pixel Count after Scale-Up/-Down + uint32_t : 4; + } uds_clipping_bits; + uint32_t uds_clipping_mask; + }; + + struct + { + union + { + struct + { + int32_t lrp : 13; ///< R Multiplication Coefficient for Y/Cr/Cb Calculation + int32_t : 19; + } setting_1_bits; + uint32_t setting_1_mask; + }; + + union + { + struct + { + int32_t lgp : 12; ///< G Multiplication Coefficient for Y/Cr/Cb Calculation + int32_t : 4; + int32_t lbp : 12; ///< B Multiplication Coefficient for Y/Cr/Cb Calculation + int32_t : 4; + } setting_2_bits; + uint32_t setting_2_mask; + }; + + union + { + struct + { + uint32_t lap : 12; ///< Y/Cb/Cr Calculation Data Normalized Additional Value + uint32_t : 4; + uint32_t persistent_bit0 : 1; + uint32_t : 6; + uint32_t lhen : 1; ///< Y/Cb/Cr Calculation Shift Down Result Round-Off Enable + uint32_t lsft : 5; ///< Y/Cb/Cr Calculation Shift Down Volume + uint32_t : 2; + uint32_t persistent_bit1 : 1; + } setting_3_bits; + uint32_t setting_3_mask; + }; + } rgb_to_yuv_conversion_settings[3]; +} vin_conversion_data_t; + +/** VIN Module Status */ +typedef union e_vin_module_status +{ + struct + { + uint32_t capture_active : 1; ///< Capture Active Status + uint32_t active_video : 1; ///< Current field is in the active video area defined by the preclipping configuration. + uint32_t field_status : 1; ///< Current capture field + uint32_t frame_buffer : 2; ///< Latest frame buffer id (0b11 : Invalid). NOTE: Should be read after INTS.FIS is set to 1. + uint32_t : 11; + uint32_t memory_active : 1; ///< External memory capture is active + uint32_t : 2; + uint32_t latest_buffer : 2; ///< Latest valid frame buffer (0b11 : No valid frame buffer) + uint32_t : 11; + } bits; + uint32_t mask; +} vin_module_status_t; + +/** VIN Interrupt Status */ +typedef union e_vin_interrupt_status +{ + struct + { + uint32_t fifo_overfow : 1; ///< FIFO overflow has occurre d + uint32_t end_of_frame : 1; ///< End of frame detect + uint32_t scanline : 1; ///< Scanline detect + uint32_t : 1; + uint32_t field : 1; ///< Field detect + uint32_t frame_complete : 1; ///< Frame memory write complete detect + uint32_t : 2; + uint32_t preclip_h_err : 1; ///< Horizontal preclip error + uint32_t preclip_v_err : 1; ///< Vertical preclip error + uint32_t : 4; + uint32_t resp_overflow : 1; ///< Response overflow + uint32_t axi_err : 1; ///< Axi response error + uint32_t vsync_deasssert : 1; ///< V-Sync Deassert detect + uint32_t vsync_assert : 1; ///< V-Sync Assert detect + uint32_t : 13; + uint32_t field_detect2 : 1; ///< Field interrupt status 2 - This bit is set to 1 regardless of capture operation state. + } bits; + uint32_t mask; +} vin_interrupt_status_t; + +/** VIN IRQ Configuration */ +typedef struct st_vin_irq_cfg +{ + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< Interrupt vector number +} vin_irq_cfg_t; + +/** VIN Interrupt Control */ +typedef struct st_vin_interrupt_cfg +{ + vin_irq_cfg_t status; + vin_irq_cfg_t error; + + union + { + struct + { + uint32_t fifo_overflow : 1; ///< FIFO Overflow Interrupt Enable + uint32_t end_of_frame : 1; ///< End of Frame Interrupt Enable + uint32_t scanline_detect : 1; ///< Scanline Interrupt Enable + uint32_t : 1; + uint32_t field_detect_1 : 1; ///< Field Switching Interrupt Enable + uint32_t frame_write_complete : 1; ///< Frame MemoryWrite Completion Interrupt Enable + uint32_t : 2; + uint32_t pixel_count_error : 1; ///< Horizontal Valid Pixels of Input is Smaller Than Configuration + uint32_t line_count_error : 1; ///< Vertical Valid Lines of Input is Smaller Than Configuration + uint32_t : 4; + uint32_t response_overflow : 1; ///< Response Overflow Interrupt Enable + uint32_t axi_resp_error : 1; ///< AXI Resp Interrupt Enable + uint32_t vsync_deassert_detect : 1; ///< VSYNC Deassert Detect Interrupt Enable + uint32_t vsync_assert_detect : 1; ///< VSYNC Assert Detect Enable + uint32_t : 13; + uint32_t field_detect_2 : 1; ///< Field Interrupt Enable + } status_enable_bits; + uint32_t status_enable_mask; + }; + uint16_t scanline_compare_value; ///< 12-bit value to be compared with the received line count and trigger interrupt (0: disabled) +} vin_interrupt_cfg_t; + +/* @} (end addtogroup VIN) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_wdt/r_wdt.c b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_wdt/r_wdt.c new file mode 100644 index 0000000000..d1509a2dfc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/ra/fsp/src/r_wdt/r_wdt.c @@ -0,0 +1,711 @@ +/* +* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_wdt.h" +#include "bsp_api.h" +#include "bsp_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define WDT_OPEN (0X00574454ULL) + +/* On multi core MCU, core0 uses WDT0 settings on OFS0, and core1 uses WDT1 settings on OFS3*/ +#if 1 == BSP_CFG_CPU_CORE // Core1 + #ifdef BSP_CFG_OPTION_SETTING_OFS3_SEC + #define BSP_CFG_OPTION_SETTING_OFSX BSP_CFG_OPTION_SETTING_OFS3_SEC + #else + #define BSP_CFG_OPTION_SETTING_OFSX BSP_CFG_OPTION_SETTING_OFS3 + #endif + #define R_WDTX R_WDT1 +#else + #define BSP_CFG_OPTION_SETTING_OFSX BSP_CFG_OPTION_SETTING_OFS0 + #define R_WDTX R_WDT +#endif + +/* Lookup functions for WDT settings. Using function like macro for stringification. */ +#define WDT_PRV_OFSX_SETTING_GET(setting) (((uint32_t) BSP_CFG_OPTION_SETTING_OFSX >> \ + WDT_PRV_OFSX_ ## setting ## _BIT) & WDT_PRV_OFSX_ ## setting ## _MASK); +#define WDT_PRV_WDTCR_SETTING_GET(setting, \ + wdtcr) (((wdtcr >> WDT_PRV_WDTCR_ ## setting ## _BIT) & \ + WDT_PRV_WDTCR_ ## setting ## _MASK)); +#define WDT_PRV_WDTCR_SETTING_SET(setting, \ + value) ((value & WDT_PRV_WDTCR_ ## setting ## _MASK) << \ + WDT_PRV_WDTCR_ ## setting ## _BIT); + +/* OFS0/OFS3 register settings. */ +#define WDT_PRV_OFSX_AUTO_START_BIT (17) +#define WDT_PRV_OFSX_TIMEOUT_BIT (18) +#define WDT_PRV_OFSX_CLOCK_DIVISION_BIT (20) +#define WDT_PRV_OFSX_WINDOW_END_BIT (24) +#define WDT_PRV_OFSX_WINDOW_START_BIT (26) +#define WDT_PRV_OFSX_NMI_REQUEST_BIT (28) +#define WDT_PRV_OFSX_RESET_CONTROL_BIT (28) +#define WDT_PRV_OFSX_STOP_CONTROL_BIT (30) + +#define WDT_PRV_OFSX_AUTO_START_MASK (0x1U) // Bit 17 +#define WDT_PRV_OFSX_TIMEOUT_MASK (0x3U) // Bits 18-19 +#define WDT_PRV_OFSX_CLOCK_DIVISION_MASK (0xFU) // Bits 20-23 +#define WDT_PRV_OFSX_WINDOW_END_MASK (0x3U) // Bits 24-25 +#define WDT_PRV_OFSX_WINDOW_START_MASK (0x3U) // Bits 26-27 +#define WDT_PRV_OFSX_NMI_REQUEST_MASK (0x1U) // Bit 28 +#define WDT_PRV_OFSX_RESET_CONTROL_MASK (0x1U) // Bit 28 +#define WDT_PRV_OFSX_STOP_CONTROL_MASK (0x1U) // Bit 30 +#define WDT_PRV_NMI_EN_MASK (0x2) + +/* WDT register settings. */ +#define WDT_PRV_WDTSR_COUNTER_MASK (0x3FFFU) +#define WDT_PRV_WDTSR_FLAGS_MASK (0xC000U) + +#define WDT_PRV_WDTCR_TIMEOUT_BIT (0) +#define WDT_PRV_WDTCR_CLOCK_DIVISION_BIT (4) +#define WDT_PRV_WDTCR_WINDOW_END_BIT (8) +#define WDT_PRV_WDTCR_WINDOW_START_BIT (12) + +#define WDT_PRV_WDTRCR_RESET_CONTROL_BIT (7) +#define WDT_PRV_WDTCSTPR_STOP_CONTROL_BIT (7) + +#define WDT_PRV_WDTCR_TIMEOUT_MASK (0x3U) // Bits 0-1 +#define WDT_PRV_WDTCR_CLOCK_DIVISION_MASK (0xFU) // Bits 4-7 +#define WDT_PRV_WDTCR_WINDOW_END_MASK (0x3U) // Bits 8-9 +#define WDT_PRV_WDTCR_WINDOW_START_MASK (0x3U) // Bits 12-13 + +/* Macros for start mode and NMI support. */ +#if (BSP_CFG_OPTION_SETTING_OFSX >> WDT_PRV_OFSX_AUTO_START_BIT) & WDT_PRV_OFSX_AUTO_START_MASK + #define WDT_PRV_REGISTER_START_MODE (1) + #define WDT_PRV_NMI_SUPPORTED (WDT_CFG_REGISTER_START_NMI_SUPPORTED) +#else + +/* Auto start mode */ + #define WDT_PRV_REGISTER_START_MODE (0) + #if (BSP_CFG_OPTION_SETTING_OFSX >> WDT_PRV_OFSX_NMI_REQUEST_BIT) & WDT_PRV_OFSX_NMI_REQUEST_MASK + #define WDT_PRV_NMI_SUPPORTED (0) + #else + #define WDT_PRV_NMI_SUPPORTED (1) + #endif +#endif + +/* Refresh register values */ +#define WDT_PRV_REFRESH_STEP_1 (0U) +#define WDT_PRV_REFRESH_STEP_2 (0xFFU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * wdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile wdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_wdt_nmi_internal_callback(bsp_grp_irq_t irq); + +static uint32_t r_wdt_clock_divider_get(wdt_clock_division_t division); + +static fsp_err_t r_wdt_parameter_checking(wdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg); + +#if WDT_PRV_NMI_SUPPORTED +static void r_wdt_nmi_initialize(wdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static const uint8_t g_wdtcr_timeout[] = +{ + 0xFFU, // WDTCR value for WDT_TIMEOUT_128 (not supported by WDT). + 0xFFU, // WDTCR value for WDT_TIMEOUT_512 (not supported by WDT). + 0x00U, // WDTCR value for WDT_TIMEOUT_1024. + 0xFFU, // WDTCR value for WDT_TIMEOUT_2048 (not supported by WDT). + 0x01U, // WDTCR value for WDT_TIMEOUT_4096. + 0x02U, // WDTCR value for WDT_TIMEOUT_8192. + 0x03U, // WDTCR value for WDT_TIMEOUT_16384. +}; + +/* Convert WDT/IWDT timeout value to an integer */ +static const uint32_t g_wdt_timeout[] = +{ + 128U, + 512U, + 1024U, + 2048U, + 4096U, + 8192U, + 16384U +}; + +/* Converts WDT division enum to log base 2 of the division value, used to shift the PCLKB frequency. */ +static const uint8_t g_wdt_division_lookup[] = +{ + 0U, // log base 2(1) = 0 + 2U, // log base 2(4) = 2 + 4U, // log base 2(16) = 4 + 5U, // log base 2(32) = 5 + 6U, // log base 2(64) = 6 + 8U, // log base 2(256) = 8 + 9U, // log base 2(512) = 9 + 11U, // log base 2(2048) = 11 + 13U, // log base 2(8192) = 13 +}; + +/** Global pointer to control structure for use by the NMI callback. */ +static volatile wdt_instance_ctrl_t * gp_wdt_ctrl = NULL; + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/** Watchdog implementation of WDT Driver */ +const wdt_api_t g_wdt_on_wdt = +{ + .open = R_WDT_Open, + .refresh = R_WDT_Refresh, + .statusGet = R_WDT_StatusGet, + .statusClear = R_WDT_StatusClear, + .counterGet = R_WDT_CounterGet, + .timeoutGet = R_WDT_TimeoutGet, + .callbackSet = R_WDT_CallbackSet, +}; + +/*******************************************************************************************************************//** + * @addtogroup WDT WDT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure the WDT in register start mode. In auto-start_mode the NMI callback can be registered. Implements + * @ref wdt_api_t::open. + * + * This function should only be called once as WDT configuration registers can only be written to once so subsequent + * calls will have no effect. + * + * Example: + * @snippet r_wdt_example.c R_WDT_Open + * + * @retval FSP_SUCCESS WDT successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. + * + * @note In auto start mode the only valid configuration option is for registering the callback for the NMI ISR if + * NMI output has been selected. + **********************************************************************************************************************/ +fsp_err_t R_WDT_Open (wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg) +{ + wdt_instance_ctrl_t * p_instance_ctrl = (wdt_instance_ctrl_t *) p_ctrl; + fsp_err_t err; + + /* Check validity of the parameters */ + err = r_wdt_parameter_checking(p_instance_ctrl, p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Configuration only valid when WDT operating in register-start mode. */ +#if WDT_PRV_REGISTER_START_MODE + + /* Register-start mode. */ + + #if WDT_CFG_REGISTER_START_NMI_SUPPORTED + if (p_cfg->reset_control == WDT_RESET_CONTROL_NMI) + { + /* Register callback with BSP NMI ISR. */ + r_wdt_nmi_initialize(p_instance_ctrl, p_cfg); + } + + #else + + /* Eliminate toolchain warning when NMI output is not being used. */ + FSP_PARAMETER_NOT_USED(r_wdt_nmi_internal_callback); + #endif + + /* Set the configuration registers in register start mode. */ + R_WDTX->WDTRCR = (uint8_t) (p_cfg->reset_control << WDT_PRV_WDTRCR_RESET_CONTROL_BIT); + + uint32_t wdtcr = WDT_PRV_WDTCR_SETTING_SET(TIMEOUT, (uint16_t) g_wdtcr_timeout[p_cfg->timeout]); + wdtcr |= WDT_PRV_WDTCR_SETTING_SET(CLOCK_DIVISION, (uint16_t) p_cfg->clock_division); + wdtcr |= WDT_PRV_WDTCR_SETTING_SET(WINDOW_START, (uint16_t) p_cfg->window_start); + wdtcr |= WDT_PRV_WDTCR_SETTING_SET(WINDOW_END, (uint16_t) p_cfg->window_end); + + R_WDTX->WDTCR = (uint16_t) wdtcr; + R_WDTX->WDTCSTPR = (uint8_t) (p_cfg->stop_control << WDT_PRV_WDTCSTPR_STOP_CONTROL_BIT); +#else + + /* Auto start mode. */ + /* Check for NMI output mode. */ + #if WDT_PRV_NMI_SUPPORTED + + /* Register callback with BSP NMI ISR. */ + r_wdt_nmi_initialize(p_instance_ctrl, p_cfg); + #else + + /* Eliminate toolchain warning when NMI output is not being used. */ + FSP_PARAMETER_NOT_USED(r_wdt_nmi_internal_callback); + #endif +#endif + + p_instance_ctrl->wdt_open = WDT_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read timeout information for the watchdog timer. Implements @ref wdt_api_t::timeoutGet. + * + * @retval FSP_SUCCESS WDT timeout information retrieved successfully. + * @retval FSP_ERR_ASSERTION Null Pointer. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_WDT_TimeoutGet (wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout) +{ +#if WDT_CFG_PARAM_CHECKING_ENABLE + wdt_instance_ctrl_t * p_instance_ctrl = (wdt_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_timeout); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + FSP_PARAMETER_NOT_USED(p_ctrl); + uint32_t shift; + uint32_t index; + uint32_t timeout = 0; + wdt_clock_division_t clock_division; +#if WDT_PRV_REGISTER_START_MODE + + /* Read the configuration of the watchdog */ + uint32_t wdtcr = R_WDTX->WDTCR; + clock_division = (wdt_clock_division_t) WDT_PRV_WDTCR_SETTING_GET(CLOCK_DIVISION, wdtcr); + timeout = WDT_PRV_WDTCR_SETTING_GET(TIMEOUT, wdtcr); +#else /* Auto start mode */ + clock_division = (wdt_clock_division_t) WDT_PRV_OFSX_SETTING_GET(CLOCK_DIVISION); + timeout = WDT_PRV_OFSX_SETTING_GET(TIMEOUT); +#endif + + /* Get timeout value from WDTCR register. */ + for (index = 0U; index < (sizeof(g_wdtcr_timeout)); index++) + { + if (g_wdtcr_timeout[index] == timeout) + { + p_timeout->timeout_clocks = g_wdt_timeout[index]; + } + } + + /* Get the frequency of the clock supplying the watchdog */ + uint32_t pckb_frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + shift = r_wdt_clock_divider_get(clock_division); + + p_timeout->clock_frequency_hz = pckb_frequency >> shift; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Refresh the watchdog timer. Implements @ref wdt_api_t::refresh. + * + * In addition to refreshing the watchdog counter this function can be used to start the counter in register start mode. + * + * Example: + * @snippet r_wdt_example.c R_WDT_Refresh + * + * @retval FSP_SUCCESS WDT successfully refreshed. + * @retval FSP_ERR_ASSERTION p_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + * + * @note This function only returns FSP_SUCCESS. If the refresh fails due to being performed outside of the + * permitted refresh period the device will either reset or trigger an NMI ISR to run. + **********************************************************************************************************************/ +fsp_err_t R_WDT_Refresh (wdt_ctrl_t * const p_ctrl) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + +#if WDT_CFG_PARAM_CHECKING_ENABLE + wdt_instance_ctrl_t * p_instance_ctrl = (wdt_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + + R_WDTX->WDTRR = WDT_PRV_REFRESH_STEP_1; + R_WDTX->WDTRR = WDT_PRV_REFRESH_STEP_2; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Read the WDT status flags. Implements @ref wdt_api_t::statusGet. + * + * Indicates both status and error conditions. + * + * Example: + * @snippet r_wdt_example.c R_WDT_StatusGet + * + * @retval FSP_SUCCESS WDT status successfully read. + * @retval FSP_ERR_ASSERTION Null pointer as a parameter. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + * @retval FSP_ERR_UNSUPPORTED This function is only valid if the watchdog generates an NMI when an error occurs. + * + * @note When the WDT is configured to output a reset on underflow or refresh error reading the status and error flags + * serves no purpose as they will always indicate that no underflow has occurred and there is no refresh error. + * Reading the status and error flags is only valid when interrupt request output is enabled. + **********************************************************************************************************************/ +fsp_err_t R_WDT_StatusGet (wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status) +{ +#if WDT_PRV_NMI_SUPPORTED + #if WDT_CFG_PARAM_CHECKING_ENABLE + wdt_instance_ctrl_t * p_instance_ctrl = (wdt_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_status); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Check for refresh or underflow errors. */ + *p_status = (wdt_status_t) (R_WDTX->WDTSR >> 14); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_status); + + /* This function is only supported when the NMI is used. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Clear the WDT status and error flags. Implements @ref wdt_api_t::statusClear. + * + * Example: + * @snippet r_wdt_example.c R_WDT_StatusClear + * + * @retval FSP_SUCCESS WDT flag(s) successfully cleared. + * @retval FSP_ERR_ASSERTION Null pointer as a parameter. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + * @retval FSP_ERR_UNSUPPORTED This function is only valid if the watchdog generates an NMI when an error occurs. + * + * @note When the WDT is configured to output a reset on underflow or refresh error reading the status and error flags + * serves no purpose as they will always indicate that no underflow has occurred and there is no refresh error. + * Reading the status and error flags is only valid when interrupt request output is enabled. + **********************************************************************************************************************/ +fsp_err_t R_WDT_StatusClear (wdt_ctrl_t * const p_ctrl, const wdt_status_t status) +{ +#if WDT_PRV_NMI_SUPPORTED + uint16_t value; + uint16_t read_value; + + #if WDT_CFG_PARAM_CHECKING_ENABLE + wdt_instance_ctrl_t * p_instance_ctrl = (wdt_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); + #else + FSP_PARAMETER_NOT_USED(p_ctrl); + #endif + + /* Casts to uint16_t to ensure value is handled as unsigned. */ + value = (uint16_t) status; + + /* Write zero to clear flags. */ + value = (uint16_t) ~value; + value = (uint16_t) (value << 14); + + /* Read back status flags until required flag(s) cleared. */ + /* Flags cannot be cleared until the clock cycle after they are set. */ + do + { + R_WDTX->WDTSR = value; + read_value = R_WDTX->WDTSR; + + /* Isolate flags to clear. */ + read_value &= (uint16_t) ((uint16_t) status << 14); + } while (0U != read_value); + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(status); + + /* This function is only supported when the NMI is used. */ + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Read the current count value of the WDT. Implements @ref wdt_api_t::counterGet. + * + * Example: + * @snippet r_wdt_example.c R_WDT_CounterGet + * + * @retval FSP_SUCCESS WDT current count successfully read. + * @retval FSP_ERR_ASSERTION Null pointer passed as a parameter. + * @retval FSP_ERR_NOT_OPEN Instance control block is not initialized. + **********************************************************************************************************************/ +fsp_err_t R_WDT_CounterGet (wdt_ctrl_t * const p_ctrl, uint32_t * const p_count) +{ +#if WDT_CFG_PARAM_CHECKING_ENABLE + wdt_instance_ctrl_t * p_instance_ctrl = (wdt_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_count); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_count = (uint32_t) R_WDTX->WDTSR; + *p_count &= WDT_PRV_WDTSR_COUNTER_MASK; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements wdt_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_WDT_CallbackSet (wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void * const p_context, + wdt_callback_args_t * const p_callback_memory) +{ + wdt_instance_ctrl_t * p_instance_ctrl = (wdt_instance_ctrl_t *) p_ctrl; + +#if WDT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(WDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if WDT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + wdt_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(wdt_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup WDT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Internal NMI ISR callback which calls the user provided callback passing the context provided by the user. + * + * @param[in] irq IRQ which has triggered the NMI interrupt. + **********************************************************************************************************************/ +static void r_wdt_nmi_internal_callback (bsp_grp_irq_t irq) +{ + FSP_PARAMETER_NOT_USED(irq); + + /* Call user registered callback */ + if (NULL != gp_wdt_ctrl) + { + if (NULL != gp_wdt_ctrl->p_callback) + { + wdt_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + wdt_callback_args_t * p_args = gp_wdt_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = gp_wdt_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(gp_wdt_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + gp_wdt_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + wdt_prv_ns_callback p_callback = (wdt_prv_ns_callback) (gp_wdt_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + gp_wdt_ctrl->p_callback(p_args); +#endif + if (NULL != gp_wdt_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *gp_wdt_ctrl->p_callback_memory = args; + } + } + } +} + +/*******************************************************************************************************************//** + * Gets clock division shift value. + * + * @param[in] division Right shift value used to divide clock frequency. + **********************************************************************************************************************/ +static uint32_t r_wdt_clock_divider_get (wdt_clock_division_t division) +{ + uint32_t shift; + + if (WDT_CLOCK_DIVISION_128 == division) + { + shift = 7U; /* log base 2(128) = 7 */ + } + else + { + shift = g_wdt_division_lookup[division]; + } + + return shift; +} + +/*******************************************************************************************************************//** + * Initialize the NMI. + * + * @param[in] p_instance_ctrl Pointer to instance control structure + * @param[in] p_cfg Pointer to configuration structure + **********************************************************************************************************************/ +#if WDT_PRV_NMI_SUPPORTED +static void r_wdt_nmi_initialize (wdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg) +{ + /* Initialize global pointer to WDT for NMI callback use. */ + gp_wdt_ctrl = p_instance_ctrl; + + /* NMI output mode. */ + R_BSP_GroupIrqWrite(BSP_GRP_IRQ_WDT_ERROR, r_wdt_nmi_internal_callback); + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + + /* Enable the WDT underflow/refresh error interrupt (will generate an NMI). NMIER bits cannot be cleared after reset, + * so no need to read-modify-write. */ + R_ICU->NMIER = R_ICU_NMIER_WDTEN_Msk; +} + +#endif + +/*******************************************************************************************************************//** + * Parameter checking function for WDT Open + * + * @param[in] p_instance_ctrl Pointer to instance control structure + * @param[in] p_cfg Pointer to configuration structure + * + * @retval FSP_SUCCESS WDT successfully configured. + * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. + **********************************************************************************************************************/ +static fsp_err_t r_wdt_parameter_checking (wdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg) +{ +#if WDT_CFG_PARAM_CHECKING_ENABLE + + /* Check that control and config structure pointers are valid. */ + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(WDT_OPEN != p_instance_ctrl->wdt_open, FSP_ERR_ALREADY_OPEN); + + /* Ensure this module is in the same security state as the NMI */ + #if defined(BSP_TZ_NONSECURE_BUILD) && BSP_TZ_NONSECURE_BUILD + FSP_ERROR_RETURN(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk, FSP_ERR_INVALID_STATE); + #elif defined(BSP_TZ_SECURE_BUILD) && BSP_TZ_SECURE_BUILD + FSP_ERROR_RETURN(!(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk), FSP_ERR_INVALID_STATE); + #endif + + /* Check timeout parameter is supported by WDT. */ + + /* Enum checking is done here because some enums in wdt_timeout_t are not supported by the WDT peripheral (they are + * included for other implementations of the watchdog interface). */ + FSP_ASSERT((p_cfg->timeout == WDT_TIMEOUT_1024) || (p_cfg->timeout == WDT_TIMEOUT_4096) || \ + (p_cfg->timeout == WDT_TIMEOUT_8192) || (p_cfg->timeout == WDT_TIMEOUT_16384)); + + #if WDT_PRV_REGISTER_START_MODE + + /* Register-start mode. */ + + #if WDT_CFG_REGISTER_START_NMI_SUPPORTED + + /* Register callback with BSP NMI ISR. */ + if (p_cfg->reset_control == WDT_RESET_CONTROL_NMI) + { + FSP_ASSERT(NULL != p_cfg->p_callback); + } + else + { + FSP_ASSERT(NULL == p_cfg->p_callback); + } + + #else + FSP_ASSERT(p_cfg->reset_control == WDT_RESET_CONTROL_RESET); + #endif + #else + + /* Auto start mode. */ + + #if WDT_PRV_NMI_SUPPORTED + + /* NMI output mode. */ + FSP_ASSERT(NULL != p_cfg->p_callback); + #else + FSP_ASSERT(NULL == p_cfg->p_callback); + #endif + #endif +#else + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(p_cfg); +#endif + + return FSP_SUCCESS; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/reset_reason.c b/targets/TARGET_RENESAS/TARGET_RA/reset_reason.c new file mode 100644 index 0000000000..9f9ce7f824 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/reset_reason.c @@ -0,0 +1,137 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "reset_reason_api.h" +#include "bsp_api.h" + +/* + * Reset Source Summary + * + * RSTSR0: + * PORF Power-on reset + * LVD0RF LVD0 reset + * LVD1RF LVD1 reset + * LVD2RF LVD2 reset + * LVD4RF LVD4 reset + * LVD5RF LVD5 reset + * DPSRSTF Deep Standby reset + * + * RSTSR1: + * IWDTRF Independent WDT reset + * WDTRF WDT reset + * SWRF Software reset + * RPERF RAM parity error reset + * REERF RAM ECC error reset + * BUSSRF Bus slave error reset + * BUSMRF Bus master error reset + * SPERF Stack pointer error reset + * TZERF TrustZone error reset + * CPERF CPU exception reset + * + * RSTSR2: + * CWSF Cold/Warm start flag (NOT a reset source) + * + * RSTSR3: + * CVMRF Clock/Voltage monitor reset + * OCPRF Overcurrent reset + * TEMPRF Temperature reset + */ + +static reset_reason_t ra_map_reset_reason(uint16_t rstsr0, + uint16_t rstsr1, + uint16_t rstsr2, + uint16_t rstsr3) +{ + /* --- RSTSR0: Power / LVD / Deep Standby --- */ + + if (rstsr0 & R_SYSTEM_RSTSR0_PORF_Msk) { + return RESET_REASON_POWER_ON; + } + + if (rstsr0 & (R_SYSTEM_RSTSR0_LVD0RF_Msk + | R_SYSTEM_RSTSR0_LVD1RF_Msk + | R_SYSTEM_RSTSR0_LVD2RF_Msk +#ifdef R_SYSTEM_RSTSR0_LVD3RF_Msk + | R_SYSTEM_RSTSR0_LVD3RF_Msk + | R_SYSTEM_RSTSR0_LVD4RF_Msk + | R_SYSTEM_RSTSR0_LVD5RF_Msk +#endif + )) { + return RESET_REASON_BROWN_OUT; + } + + if (rstsr0 & R_SYSTEM_RSTSR0_DPSRSTF_Msk) { + return RESET_REASON_PLATFORM; /* Deep Standby exit */ + } + + /* --- RSTSR1: Watchdog / Software / Bus / ECC / CPU errors --- */ + + if (rstsr1 & (R_SYSTEM_RSTSR1_IWDTRF_Msk | + R_SYSTEM_RSTSR1_WDTRF_Msk)) { + return RESET_REASON_WATCHDOG; + } + + if (rstsr1 & R_SYSTEM_RSTSR1_SWRF_Msk) { + return RESET_REASON_SOFTWARE; + } + + /* All other RSTSR1 error resets -> PLATFORM */ + if (rstsr1 & ~(R_SYSTEM_RSTSR1_IWDTRF_Msk | + R_SYSTEM_RSTSR1_WDTRF_Msk | + R_SYSTEM_RSTSR1_SWRF_Msk)) { + return RESET_REASON_PLATFORM; + } + + /* --- RSTSR3: Voltage / Overcurrent / Temperature --- */ +#ifdef R_SYSTEM_RSTSR3_CVMRF_Msk + if (rstsr3 & (R_SYSTEM_RSTSR3_CVMRF_Msk | + R_SYSTEM_RSTSR3_OCPRF_Msk | + R_SYSTEM_RSTSR3_TEMPRF_Msk)) { + return RESET_REASON_BROWN_OUT; /* Broadly: power/environment abnormal */ + } +#endif + + if (rstsr0 == 0 && rstsr1 == 0 && rstsr2 == 0 && rstsr3 == 0) { + return RESET_REASON_PIN_RESET; + } + + return RESET_REASON_UNKNOWN; +} + +reset_reason_t hal_reset_reason_get(void) +{ + uint16_t rstsr0 = R_SYSTEM->RSTSR0; + uint16_t rstsr1 = R_SYSTEM->RSTSR1; + uint16_t rstsr2 = R_SYSTEM->RSTSR2; +#ifdef R_SYSTEM_RSTSR3_CVMRF_Msk + uint16_t rstsr3 = R_SYSTEM->RSTSR3; +#else + uint16_t rstsr3 = 0; +#endif + return ra_map_reset_reason(rstsr0, rstsr1, rstsr2, rstsr3); +} + +uint32_t hal_reset_reason_get_raw(void) +{ + return ((uint32_t)R_SYSTEM->RSTSR0) | + ((uint32_t)R_SYSTEM->RSTSR1 << 8) | + ((uint32_t)R_SYSTEM->RSTSR2 << 16) | +#ifdef R_SYSTEM_RSTSR3_CVMRF_Msk + ((uint32_t)R_SYSTEM->RSTSR3 << 24) +#else + 0 +#endif + ; +} + +void hal_reset_reason_clear(void) +{ + /* RA: write 0 to clear writable flags */ + R_SYSTEM->RSTSR0 = 0; + R_SYSTEM->RSTSR1 = 0; + R_SYSTEM->RSTSR2 = 0; /* CWSF is read-only, writing 0 is harmless */ +#ifdef R_SYSTEM_RSTSR3_CVMRF_Msk + R_SYSTEM->RSTSR3 = 0; +#endif +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/rtc_api.c b/targets/TARGET_RENESAS/TARGET_RA/rtc_api.c new file mode 100644 index 0000000000..bb01a20ca1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/rtc_api.c @@ -0,0 +1,105 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "rtc_api.h" +#include "bsp_api.h" +#include "hal_data.h" +#include "mbed_mktime.h" +#include "reset_reason_api.h" + +static bool rtc_opened = false; + +void rtc_init(void) +{ + if (rtc_opened) { + return; + } + + fsp_err_t err = R_RTC_Open(&g_rtc0_ctrl, &g_rtc0_cfg); + if (FSP_SUCCESS == err) { + rtc_opened = true; + } + +#if TARGET_FPB_RA8E1 + // To retain the RTC clock after reset, R_RTC_ClockSourceSet can only be called once after Power On. + // Unfortunately, only on FPB-RA8E1 we can get the correct Power Up reset reason + // Note: rtc_init() must be called before ResetReason::get() + reset_reason_t reset_reason = hal_reset_reason_get(); + if (reset_reason == RESET_REASON_POWER_ON) +#endif + { + R_RTC_ClockSourceSet(&g_rtc0_ctrl); + R_SYSTEM->RSTSR0_b.PORF = 0U; + } + + R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS); +} + +int rtc_isenabled(void) +{ + if (!rtc_opened) { + return 0; + } + return 1; +} + +time_t rtc_read(void) +{ + if (!rtc_opened) { + rtc_init(); + } + + rtc_time_t rtc_time; + fsp_err_t err = R_RTC_CalendarTimeGet(&g_rtc0_ctrl, &rtc_time); + if (FSP_SUCCESS != err) { + return 0; + } + + struct tm t; + memset(&t, 0, sizeof(t)); + t.tm_sec = rtc_time.tm_sec; + t.tm_min = rtc_time.tm_min; + t.tm_hour = rtc_time.tm_hour; + t.tm_mday = rtc_time.tm_mday; + t.tm_mon = rtc_time.tm_mon; // struct tm: 0-11 + t.tm_year = rtc_time.tm_year - 32; // struct tm: since 1900 + t.tm_isdst = 0; + + time_t ts = 0; + if (_rtc_maketime(&t, &ts, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } + + return ts; +} + +void rtc_write(time_t t) +{ + if (!rtc_opened) { + rtc_init(); + } + + struct tm timeinfo; + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return; + } + + rtc_time_t rtc_time; + rtc_time.tm_sec = timeinfo.tm_sec; + rtc_time.tm_min = timeinfo.tm_min; + rtc_time.tm_hour = timeinfo.tm_hour; + rtc_time.tm_mday = timeinfo.tm_mday; + rtc_time.tm_mon = timeinfo.tm_mon; + // ensure rtc_time.tm_year >= 100 + rtc_time.tm_year = timeinfo.tm_year + 32; + rtc_time.tm_wday = timeinfo.tm_wday; + rtc_time.tm_isdst = 0; + + (void) R_RTC_CalendarTimeSet(&g_rtc0_ctrl, &rtc_time); +} + +void rtc_free(void) +{ + /* RTC counts persistently; do not close hardware or stop counter */ +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/serial_api.c b/targets/TARGET_RENESAS/TARGET_RA/serial_api.c new file mode 100644 index 0000000000..1251bb7052 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/serial_api.c @@ -0,0 +1,354 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "serial_api.h" +#include "pinmap.h" +#include "hal_data.h" + +#define RX_BUF_SIZE 16 + +#if BSP_PERIPHERAL_SCI_B_PRESENT +#define baud_setting_t sci_b_baud_setting_t +#define R_SCI_UART_BaudCalculate R_SCI_B_UART_BaudCalculate +#define sci_uart_instance_ctrl_t sci_b_uart_instance_ctrl_t +#define R_SCI0_Type R_SCI_B0_Type +#define SSR_b CSR_b +#endif + +#if MBED_CONF_TARGET_CONSOLE_UART +int stdio_uart_inited = 0; // used in platform/mbed_board.c and platform/mbed_retarget.cpp +serial_t stdio_uart; +#endif + +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +extern uart_instance_t* const g_uart_instances[]; + +static uart_irq_handler g_irq_handler = NULL; +static uint32_t g_irq_id[UART_COUNT]; +static uint8_t g_rx_irq_enabled[UART_COUNT]; +static uint8_t g_tx_irq_enabled[UART_COUNT]; +static volatile uint8_t g_rx_buf[UART_COUNT][RX_BUF_SIZE]; +static volatile uint8_t g_rx_head[UART_COUNT]; +static volatile uint8_t g_rx_tail[UART_COUNT]; + +static inline int rxbuf_is_full(int idx) +{ + return ((g_rx_head[idx] + 1) & (RX_BUF_SIZE - 1)) == g_rx_tail[idx]; +} + +static inline int rxbuf_is_empty(int idx) +{ + return g_rx_head[idx] == g_rx_tail[idx]; +} + +static inline void rxbuf_push(int idx, uint8_t b) +{ + g_rx_buf[idx][g_rx_head[idx]] = b; + g_rx_head[idx] = (g_rx_head[idx] + 1) & (RX_BUF_SIZE - 1); +} + +static inline uint8_t rxbuf_pop(int idx) +{ + uint8_t b = g_rx_buf[idx][g_rx_tail[idx]]; + g_rx_tail[idx] = (g_rx_tail[idx] + 1) & (RX_BUF_SIZE - 1); + return b; +} + + +/* ---------------- PinMap UART channel ---------------- */ + +static int channel_from_pin(PinName tx, PinName rx) +{ + int tx_peri = pinmap_peripheral(tx, PinMap_UART_TX); + int rx_peri = pinmap_peripheral(rx, PinMap_UART_RX); + int merged = pinmap_merge(tx_peri, rx_peri); + if (merged == NC) { + return -1; + } + return merged; /* UART_0 / UART_1 / ... */ +} + +int instance_index_from_channel(int channel) +{ + for(int instane_index = 0; instane_index < UART_COUNT; instane_index++) { + if(g_uart_instances[instane_index]->p_cfg->channel == channel) { + return instane_index; + } + } + return -1; +} + +/* ---------------- Mbed API: init/free ---------------- */ + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + MBED_ASSERT(obj); + MBED_ASSERT(tx != NC && rx != NC); + + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + uint32_t peripheral = (int)pinmap_merge(uart_tx, uart_rx); + + int channel = channel_from_pin(tx, rx); + + uint32_t tx_function = pinmap_function(tx, PinMap_UART_TX); + uint32_t rx_function = pinmap_function(rx, PinMap_UART_RX); + pin_function(tx, tx_function); + pin_function(rx, rx_function); + + obj->instance_index = instance_index_from_channel(channel); + MBED_ASSERT(obj->instance_index >= 0 && obj->instance_index < UART_COUNT); + + uart_instance_t* const uart = g_uart_instances[obj->instance_index]; + + obj->p_api = uart->p_api; + obj->p_ctrl = (sci_uart_instance_ctrl_t *) uart->p_ctrl; + const uart_cfg_t *cfg_src = uart->p_cfg; + const sci_uart_extended_cfg_t *ext_src = (const sci_uart_extended_cfg_t *)cfg_src->p_extend; + + obj->cfg = *cfg_src; + if (ext_src) { + obj->ext = *ext_src; + obj->cfg.p_extend = &obj->ext; + } else { + obj->cfg.p_extend = NULL; + } + obj->cfg.p_context = obj; + obj->tx = tx; + obj->rx = rx; + + uint8_t stdio_config = false; +#if defined(MBED_CONF_TARGET_CONSOLE_UART) + if ((tx == CONSOLE_TX) || (rx == CONSOLE_RX)) { + stdio_config = true; + } else { + if (peripheral == pinmap_peripheral(CONSOLE_TX, PinMap_UART_TX)) { + error("Error: new serial object is using same UART as STDIO"); + } + } +#endif + + if (stdio_config) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + // baudrate takes value from platform/mbed_lib.json + R_SCI_UART_BaudCalculate(MBED_CONF_PLATFORM_STDIO_BAUD_RATE, true, 500, obj->ext.p_baud_setting); +#endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */ + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + // baudrate takes value from platform/mbed_lib.json + R_SCI_UART_BaudCalculate(MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE, true, 500, obj->ext.p_baud_setting); +#endif /* MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE */ + } + + g_rx_head[obj->instance_index] = 0; + g_rx_tail[obj->instance_index] = 0; + + fsp_err_t err = obj->p_api->open(obj->p_ctrl, &obj->cfg); + MBED_ASSERT(err == FSP_SUCCESS); + +#if MBED_CONF_TARGET_CONSOLE_UART + // For stdio management in platform/mbed_board.c and platform/mbed_retarget.cpp + if (stdio_config) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +#endif +} + +void serial_free(serial_t *obj) +{ + MBED_ASSERT(obj); + + obj->p_api->callbackSet(obj->p_ctrl, NULL, NULL, NULL); + g_rx_irq_enabled[obj->instance_index] = 0; + g_tx_irq_enabled[obj->instance_index] = 0; +} + +/* ---------------- Mbed API: baud/format ---------------- */ + +void serial_baud(serial_t *obj, int baudrate) +{ + MBED_ASSERT(obj); + + baud_setting_t setting; + fsp_err_t err = R_SCI_UART_BaudCalculate(baudrate, true, 500, &setting); + if (err == FSP_SUCCESS) { + obj->p_api->baudSet(obj->p_ctrl, &setting); + } +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + MBED_ASSERT(obj); + + uart_cfg_t *cfg = &obj->cfg; + + switch (data_bits) { + case 7: cfg->data_bits = UART_DATA_BITS_7; break; + case 8: + default: cfg->data_bits = UART_DATA_BITS_8; break; + } + + switch (parity) { + case ParityOdd: cfg->parity = UART_PARITY_ODD; break; + case ParityEven: cfg->parity = UART_PARITY_EVEN; break; + default: cfg->parity = UART_PARITY_OFF; break; + } + + cfg->stop_bits = (stop_bits == 2) ? UART_STOP_BITS_2 : UART_STOP_BITS_1; + + obj->p_api->close(obj->p_ctrl); + obj->p_api->open(obj->p_ctrl, cfg); + + void uartCallback(uart_callback_args_t *p_args); + obj->p_api->callbackSet(obj->p_ctrl, &uartCallback, NULL, NULL); +} + +/* ---------------- Mbed API: blocking getc/putc ---------------- */ + +int serial_getc(serial_t *obj) +{ + int idx = obj->instance_index; + + while (rxbuf_is_empty(idx)) { + __NOP(); + } + + return rxbuf_pop(idx); +} + +void serial_putc(serial_t *obj, int c) +{ + sci_uart_instance_ctrl_t *ctrl = obj->p_ctrl; + R_SCI0_Type *reg = ctrl->p_reg; + if(ctrl->fifo_depth > 0) + { +#if BSP_PERIPHERAL_SCI_B_PRESENT + while(reg->FTSR_b.T == ctrl->fifo_depth); + reg->TDR_BY = (uint8_t)c; +#else + while(reg->FDR_b.T == ctrl->fifo_depth); + reg->FTDRHL = (uint16_t)c; +#endif + } + else + { + reg->TDR = (uint8_t) c; + while (reg->SSR_b.TEND == 0); + } +} + + + +int serial_readable(serial_t *obj) +{ + return !rxbuf_is_empty(obj->instance_index); +} + +int serial_writable(serial_t *obj) +{ + (void) obj; + return 1; +} + +/* ---------------- Mbed API: IRQ ---------------- */ + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + (void)obj; + g_irq_handler = handler; + + if (obj) { + g_irq_id[obj->instance_index] = id; + } +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + MBED_ASSERT(obj); + + if (irq == RxIrq) g_rx_irq_enabled[obj->instance_index] = enable; + if (irq == TxIrq) g_tx_irq_enabled[obj->instance_index] = enable; +} + +void serial_break_set(serial_t *obj) +{ + (void)obj; +} + +void serial_break_clear(serial_t *obj) +{ + (void)obj; +} + +/* ---------------- UART callback ---------------- */ + +void uart_callback(uart_callback_args_t *p_args) +{ + serial_t *obj = (serial_t *) p_args->p_context; + int idx = obj->instance_index; + + switch (p_args->event) + { + case UART_EVENT_RX_CHAR: + { + rxbuf_push(idx, (uint8_t)p_args->data); + + sci_uart_instance_ctrl_t *p_ctrl = obj->p_ctrl; + if (p_ctrl->fifo_depth > 0U) { +#if BSP_PERIPHERAL_SCI_B_PRESENT + while (p_ctrl->p_reg->FRSR_b.R > 0U) { + uint8_t data = p_ctrl->p_reg->RDR_BY & 0xFF; +#else + while (p_ctrl->p_reg->FDR_b.R > 0U) { + uint8_t data = p_ctrl->p_reg->FRDRHL & 0xFF; +#endif + rxbuf_push(idx, data); + if (rxbuf_is_full(idx)) { + break; + } + } + } + + if (g_rx_irq_enabled[idx]) { + g_irq_handler(g_irq_id[idx], RxIrq); + } + break; + } + + case UART_EVENT_RX_COMPLETE: + if (g_rx_irq_enabled[idx]) + g_irq_handler(g_irq_id[idx], RxIrq); + break; + + case UART_EVENT_TX_DATA_EMPTY: + case UART_EVENT_TX_COMPLETE: + if (g_tx_irq_enabled[idx]) + g_irq_handler(g_irq_id[idx], TxIrq); + break; + + case UART_EVENT_ERR_PARITY: + case UART_EVENT_ERR_FRAMING: + case UART_EVENT_ERR_OVERFLOW: + case UART_EVENT_BREAK_DETECT: + if (g_rx_irq_enabled[idx]) + g_irq_handler(g_irq_id[idx], RxIrq); + break; + } +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + diff --git a/targets/TARGET_RENESAS/TARGET_RA/spi_api.c b/targets/TARGET_RENESAS/TARGET_RA/spi_api.c new file mode 100644 index 0000000000..342be0835f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/spi_api.c @@ -0,0 +1,435 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mbed_assert.h" +#include "mbed_error.h" +#include "spi_api.h" +#include "pinmap.h" + +#include "hal_data.h" /* FSP-generated: g_spi0, g_spi1, g_ioport etc. */ +#include "r_ioport.h" + +#define SPI_TIMEOUT_DEFAULT_VALUE 500 + +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/* -------------------------------------------------------------------------- + * Extern FSP instances + * -------------------------------------------------------------------------- */ + +extern const spi_instance_t g_spi0; +#if BSP_FEATURE_SPI_NUM_CHANNELS >= 2 +extern const spi_instance_t g_spi1; +#endif +extern const ioport_instance_t g_ioport; + +/* -------------------------------------------------------------------------- + * Helpers + * -------------------------------------------------------------------------- */ + +static const spi_instance_t *ra_spi_instance_from_channel(SPIName ch) +{ + switch (ch) { + case SPI_0: return &g_spi0; +#if BSP_FEATURE_SPI_NUM_CHANNELS >= 2 + case SPI_1: return &g_spi1; +#endif + default: return NULL; + } +} + +static void ra_spi_configure_pins(PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + /* Configure peripheral function for each pin using PinMap.function */ + uint32_t func; + + if (mosi != NC) { + func = pinmap_function(mosi, PinMap_SPI_MOSI); + if (func) { + pin_function(mosi, func); + } + } + + if (miso != NC) { + func = pinmap_function(miso, PinMap_SPI_MISO); + if (func) { + pin_function(miso, func); + } + } + + if (sclk != NC) { + func = pinmap_function(sclk, PinMap_SPI_SCLK); + if (func) { + pin_function(sclk, func); + } + } + + if (ssel != NC) { + func = pinmap_function(ssel, PinMap_SPI_SSEL); + if (func) { + pin_function(ssel, func); + } + } +} + +static uint32_t spi_actual_frequency(rspck_div_setting_t *div) +{ +#if BSP_FEATURE_SCI_HAS_SCISPI_CLOCK + // SPI clock source must be selected as SCISPICLK + uint32_t spi_source_clock = R_FSP_SciSpiClockHzGet(); +#elif BSP_FEATURE_SPI_HAS_CLOCK + // SPI clock source must be selected as SPICLK + uint32_t spi_source_clock = R_FSP_SpiClockHzGet(); +#else + // SPI clock source is PCLKA on RA4 and RA6 + uint32_t spi_source_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKA); +#endif + uint32_t spbr = div->spbr; + uint32_t brdv = div->brdv; + + uint32_t divisor = (2U * (spbr + 1U)) << brdv; + + return spi_source_clock / divisor; +} + +/* -------------------------------------------------------------------------- + * Mbed HAL API + * -------------------------------------------------------------------------- */ + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + MBED_ASSERT(obj != NULL); + + /* Resolve peripheral from pins */ + int mosi_periph = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + int miso_periph = pinmap_peripheral(miso, PinMap_SPI_MISO); + int sclk_periph = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + int ssel_periph = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + int spi_periph = pinmap_merge(mosi_periph, + pinmap_merge(miso_periph, + pinmap_merge(sclk_periph, ssel_periph))); + + if (spi_periph == (int)NC) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_INVALID_ARGUMENT), "spi_init"); + } + + obj->channel = (SPIName)spi_periph; + obj->has_miso = (miso != NC); + obj->has_mosi = (mosi != NC); + + /* Configure pins to peripheral function */ + ra_spi_configure_pins(mosi, miso, sclk, ssel); + + /* Bind to FSP instance and copy configuration */ + const spi_instance_t *inst = ra_spi_instance_from_channel(obj->channel); + MBED_ASSERT(inst != NULL); + + obj->p_ctrl = (spi_instance_ctrl_t *) inst->p_ctrl; + const spi_cfg_t *cfg_src = inst->p_cfg; + const spi_extended_cfg_t *ext_src = (const spi_extended_cfg_t *)cfg_src->p_extend; + + /* Shallow copy cfg and ext into local storage so we can tweak bitrate/mode later */ + obj->cfg = *cfg_src; + if (ext_src) { + obj->ext = *ext_src; + obj->cfg.p_extend = &obj->ext; + } else { + obj->cfg.p_extend = NULL; + } + + obj->cfg.p_context = obj; + obj->bits = 8; + obj->mode = 0; + + spi_extended_cfg_t *ext = (spi_extended_cfg_t *)obj->cfg.p_extend; + obj->hz = spi_actual_frequency(&ext->spck_div); + +#if MBED_CONF_RTOS_PRESENT + if(obj->semaphoreId == NULL) + { + osSemaphoreAttr_t attr = { 0 }; + attr.cb_mem = &obj->semaphoreMem; + attr.cb_size = sizeof(osRtxSemaphore_t); + obj->semaphoreId = osSemaphoreNew(1, 0, &attr); + } +#else + obj->xfer_done = true; +#endif + /* Open SPI */ + fsp_err_t err = R_SPI_Open(obj->p_ctrl, &obj->cfg); + if (FSP_SUCCESS != err) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_INITIALIZATION_FAILED), "spi_init"); + } +} + +void spi_init_direct(spi_t *obj, const spi_pinmap_t *pinmap) +{ + spi_init(obj, pinmap->mosi_pin, pinmap->miso_pin, pinmap->sclk_pin, pinmap->ssel_pin); +} + +void spi_free(spi_t *obj) +{ + if (!obj) { + return; + } + R_SPI_Close(obj->p_ctrl); +#if MBED_CONF_RTOS_PRESENT + osSemaphoreDelete(obj->semaphoreId); + obj->semaphoreId = NULL; +#endif +} + +/* bits: 4..16, mode: 0..3, slave: 0=master, 1=slave (we only support 8-bit master transfer here) */ +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT(obj != NULL); + + if (bits != 8) { + bits = 8; + } + + obj->bits = bits; + + int cpol = (mode & 0x2) ? 1 : 0; + int cpha = (mode & 0x1) ? 1 : 0; + + obj->cfg.clk_polarity = cpol ? SPI_CLK_POLARITY_HIGH : SPI_CLK_POLARITY_LOW; + obj->cfg.clk_phase = cpha ? SPI_CLK_PHASE_EDGE_EVEN : SPI_CLK_PHASE_EDGE_ODD; + + obj->cfg.operating_mode = SPI_MODE_MASTER; + + R_SPI_Close(obj->p_ctrl); + R_SPI_Open(obj->p_ctrl, &obj->cfg); +} + +static fsp_err_t spi_calculate_bitrate(int hz, rspck_div_setting_t *div) +{ +#if BSP_PERIPHERAL_SPI_B_PRESENT + fsp_err_t err = R_SPI_B_CalculateBitrate(hz, SPI_B_CLOCK_SOURCE_SCISPICLK, div); +#else + fsp_err_t err = R_SPI_CalculateBitrate(hz, div); +#endif + return err; +} + +static void spi_switch_tx_only_mode(spi_t *obj, bool enable_tx_only) +{ + if(enable_tx_only) + { + obj->ext.spi_comm = SPI_COMMUNICATION_TRANSMIT_ONLY; +#if BSP_PERIPHERAL_SPI_B_PRESENT + obj->p_ctrl->p_regs->SPCR &= ~R_SPI_B0_SPCR_SPRIE_Msk; + obj->p_ctrl->p_regs->SPCR |= (uint32_t) ((uint32_t)1 << R_SPI_B0_SPCR_TXMD_Pos); +#else + obj->p_ctrl->p_regs->SPCR &= ~R_SPI0_SPCR_SPRIE_Msk; + obj->p_ctrl->p_regs->SPCR |= (R_SPI0_SPCR_TXMD_Msk | R_SPI0_SPCR_SPTIE_Msk); +#endif + } + else + { + obj->ext.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX; +#if BSP_PERIPHERAL_SPI_B_PRESENT + obj->p_ctrl->p_regs->SPCR |= R_SPI_B0_SPCR_SPRIE_Msk; + obj->p_ctrl->p_regs->SPCR &= ~R_SPI_B0_SPCR_TXMD_Msk; +#else + obj->p_ctrl->p_regs->SPCR |= R_SPI0_SPCR_SPRIE_Msk; + obj->p_ctrl->p_regs->SPCR &= ~(R_SPI0_SPCR_TXMD_Msk | R_SPI0_SPCR_SPTIE_Msk); +#endif + } +} + +void spi_frequency(spi_t *obj, int hz) +{ + MBED_ASSERT(obj != NULL); + + if (hz <= 0) { + hz = 1000000; + } + + rspck_div_setting_t div; + + fsp_err_t err = spi_calculate_bitrate(hz, &div); + if (err != FSP_SUCCESS) { + hz = 1000000; + spi_calculate_bitrate(hz, &div); + } + + spi_extended_cfg_t *ext = (spi_extended_cfg_t *)obj->cfg.p_extend; + ext->spck_div = div; + + obj->hz = spi_actual_frequency(&div); + + R_SPI_Close(obj->p_ctrl); + R_SPI_Open(obj->p_ctrl, &obj->cfg); +} + +/* Waiting for SPI transmission to complete */ +static void spi_wait(spi_t *obj) +{ +#if MBED_CONF_RTOS_PRESENT + osSemaphoreAcquire(obj->semaphoreId, SPI_TIMEOUT_DEFAULT_VALUE); +#else + while (!obj->xfer_done); +#endif +} + +/* Blocking 8-bit transfer: write one byte, return received byte */ +int spi_master_write(spi_t *obj, int value) +{ + MBED_ASSERT(obj != NULL); + + uint8_t tx = (uint8_t)value; + uint8_t rx = 0; + +#if BSP_CFG_DCACHE_ENABLED + SCB_CleanDCache_by_Addr((volatile void *)&value, 1); +#endif + + fsp_err_t err = 0; +#if !MBED_CONF_RTOS_PRESENT + obj->xfer_done = false; +#endif + spi_switch_tx_only_mode(obj, !obj->has_miso); + + if (obj->has_miso) { + err = R_SPI_WriteRead(obj->p_ctrl, &tx, &rx, 1, SPI_BIT_WIDTH_8_BITS); + } + else { + err = R_SPI_Write(obj->p_ctrl, &tx, 1, SPI_BIT_WIDTH_8_BITS); + } + if (FSP_SUCCESS != err) { + /* On error, return -1 to signal failure */ + return -1; + } + spi_wait(obj); + + return (int)rx; +} + +int spi_master_block_write(spi_t *obj, + const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, + char write_fill) +{ + MBED_ASSERT(obj != NULL); + + int total = tx_length > rx_length ? tx_length : rx_length; + if (total <= 0) { + return 0; + } + + const int CHUNK = 1024; + int offset = 0; + + uint8_t fill = write_fill; + uint8_t dummy_rx; + +#if BSP_CFG_DCACHE_ENABLED + if(tx_length != 0) + { + SCB_CleanDCache_by_Addr((volatile void *)tx_buffer, tx_length); + } +#endif + bool is_tx_only = !obj->has_miso || rx_buffer == NULL || rx_length == 0; + spi_switch_tx_only_mode(obj, is_tx_only); + + while (offset < total) { + + int chunk = total - offset; + if (chunk > CHUNK) { + chunk = CHUNK; + } + + const uint8_t *tx_ptr; + uint8_t *rx_ptr; + + if (offset < tx_length) { + tx_ptr = (const uint8_t *)(tx_buffer + offset); + } else { + tx_ptr = &fill; + } + + if (offset < rx_length) { + rx_ptr = (uint8_t *)(rx_buffer + offset); + } else { + rx_ptr = &dummy_rx; + } + + fsp_err_t err = 0; +#if !MBED_CONF_RTOS_PRESENT + obj->xfer_done = false; +#endif + + if(!is_tx_only) { + if(tx_length == 0) { + err = R_SPI_Read(obj->p_ctrl, rx_ptr, chunk, SPI_BIT_WIDTH_8_BITS); + } + else { + err = R_SPI_WriteRead(obj->p_ctrl, tx_ptr, rx_ptr, chunk, SPI_BIT_WIDTH_8_BITS); + } + } + else { + err = R_SPI_Write(obj->p_ctrl, tx_ptr, chunk, SPI_BIT_WIDTH_8_BITS); + } + + if (FSP_SUCCESS != err) { + return -1; + } + + spi_wait(obj); + + offset += chunk; + } + + return total; +} + + +int spi_busy(spi_t *obj) +{ +#if MBED_CONF_RTOS_PRESENT + return osSemaphoreGetCount(obj->semaphoreId) == 0; +#else + return !obj->xfer_done; +#endif +} + +/* ---------------- SPI callback ---------------- */ + +void spi_callback(spi_callback_args_t * p_args) +{ + spi_t *obj = (spi_t *) p_args->p_context; +#if MBED_CONF_RTOS_PRESENT + osSemaphoreRelease(obj->semaphoreId); +#else + obj->xfer_done = true; +#endif +} + +/* ---------------- PinMap getters ---------------- */ + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/trng_api.c b/targets/TARGET_RENESAS/TARGET_RA/trng_api.c new file mode 100644 index 0000000000..f6d28d264b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/trng_api.c @@ -0,0 +1,197 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "trng_api.h" +#include "common_data.h" +#include "mbed_error.h" + +#ifdef TARGET_RA4E1 + +// In RA4E1, TRNG is part of SCE9 + +#include "r_sce.h" + +void trng_init(trng_t *obj) +{ + (void)obj; + fsp_err_t err = FSP_SUCCESS; + err = R_SCE_Open(&sce_ctrl, &sce_cfg); + if (err != FSP_SUCCESS) + { + mbed_error(MBED_ERROR_CODE_OPEN_FAILED, "Failed to open SCE for random number generator", 0, MBED_FILENAME, __LINE__); + } +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *actual) +{ + (void)obj; + + uint32_t rnd[4]; + size_t generated = 0; + + while (generated < length) + { + fsp_err_t err = R_SCE_RandomNumberGenerate(rnd); + + if (err != FSP_SUCCESS) + { + *actual = generated; + return -1; + } + + size_t remain = length - generated; + size_t copy_len = (remain >= 16) ? 16 : remain; + + memcpy(output + generated, rnd, copy_len); + generated += copy_len; + } + + *actual = generated; + return 0; +} + +void trng_free(trng_t *obj) +{ + (void)obj; +} + +#elif defined(TARGET_RA6E2) + +// In RA6E2, TRNG is standalone and only accessible via registers + +void trng_init(trng_t *obj) +{ + (void)obj; + + /* Cancel Random Number Generator Module Stop */ + R_MSTP->MSTPCRC_b.MSTPC28 = 0; + + /* SEED Generation Circuit Enable */ + R_TRNG->TRNGSCR0_b.SGCEN = 1; +} + + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *actual) +{ + (void)obj; + + uint32_t previous_seed = 0xFFFFFFFF; + size_t generated = 0; + + while (generated < length) + { + /* Start SEED generation */ + R_TRNG->TRNGSCR0_b.SGSTART = 1; + + while (R_TRNG->TRNGSCR0_b.RDRDY == 0) + { + /* wait */ + } + + /* Read 32-bit SEEDs */ + uint32_t seed = 0; + seed |= ((uint32_t)R_TRNG->TRNGSDR) << 24; + seed |= ((uint32_t)R_TRNG->TRNGSDR) << 16; + seed |= ((uint32_t)R_TRNG->TRNGSDR) << 8; + seed |= ((uint32_t)R_TRNG->TRNGSDR); + + /* FIPS 140-2 continuous test */ + if (seed == previous_seed) + { + return 0; + } + previous_seed = seed; + + /* output as bytes */ + for (int i = 0; i < 4 && generated < length; i++) + { + output[generated++] = (seed >> (24 - i * 8)) & 0xFF; + } + } + + *actual = generated; + return 0; +} + +void trng_free(trng_t *obj) +{ + (void)obj; + + /* SEED Generation Circuit Disable */ + R_TRNG->TRNGSCR0_b.SGCEN = 0; + + /* Random Number Generator Module Stop */ + R_MSTP->MSTPCRC_b.MSTPC28 = 1; +} + +#elif defined(TARGET_RA8E1) + +// In RA8E1, TRNG is part of RSIP + +#include "r_rsip.h" + +void trng_init(trng_t *obj) +{ + (void)obj; + fsp_err_t err = FSP_SUCCESS; + err = R_RSIP_Open(&g_rsip_ctrl, &g_rsip_cfg); + if (err != FSP_SUCCESS) + { + mbed_error(MBED_ERROR_CODE_OPEN_FAILED, "Failed to open RSIP for random number generator", 0, MBED_FILENAME, __LINE__); + } +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *actual) +{ + (void)obj; + + uint32_t rnd[4]; + size_t generated = 0; + + while (generated < length) + { + fsp_err_t err = R_RSIP_RandomNumberGenerate(&g_rsip_ctrl, (uint8_t*) rnd); + + if (err != FSP_SUCCESS) + { + *actual = generated; + return -1; + } + + size_t remain = length - generated; + size_t copy_len = (remain >= 16) ? 16 : remain; + + memcpy(output + generated, rnd, copy_len); + generated += copy_len; + } + + *actual = generated; + return 0; +} + +void trng_free(trng_t *obj) +{ + (void)obj; +} + +#else + +void trng_init(trng_t *obj) +{ + (void)obj; +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *actual) +{ + (void)obj; + + return -1; +} + +void trng_free(trng_t *obj) +{ + (void)obj; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RA/us_ticker.c b/targets/TARGET_RENESAS/TARGET_RA/us_ticker.c new file mode 100644 index 0000000000..5845f804b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/us_ticker.c @@ -0,0 +1,134 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "mbed_error.h" +#include "us_ticker_api.h" +#include "us_ticker_defines.h" +#include "r_gpt.h" +#include "r_gpt_cfg.h" + +extern const timer_instance_t US_TICKER_VAR; + +static int us_ticker_inited = 0; + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + US_TICKER_CLOCK_HZ, + US_TICKER_CLOCK_BITS + }; + return &info; +} + +static void us_ticker_gpt_init(void) +{ + fsp_err_t err; + + err = US_TICKER_VAR.p_api->open(US_TICKER_VAR.p_ctrl, US_TICKER_VAR.p_cfg); + if (FSP_SUCCESS != err && FSP_ERR_ALREADY_OPEN != err) { + mbed_error(MBED_ERROR_CODE_OPEN_FAILED, "Failed to open GPT channel for us ticker", 0, MBED_FILENAME, __LINE__); + return; + } + + err = US_TICKER_VAR.p_api->start(US_TICKER_VAR.p_ctrl); + if (FSP_SUCCESS != err) { + mbed_error(MBED_ERROR_CODE_OPEN_FAILED, "Failed to start GPT channel for us ticker", 0, MBED_FILENAME, __LINE__); + return; + } +} + +static void us_ticker_gpt_set_compare(uint32_t timestamp) +{ + US_TICKER_INSTANCE->GTCCR[0] = (uint32_t)timestamp; + US_TICKER_INSTANCE->GTST = R_GPT0_GTST_TCFA_Msk; +} + +static void us_ticker_gpt_disable_irq(void) +{ + R_BSP_IrqDisable(US_TICKER_IRQ); +} + +static void us_ticker_gpt_clear_irq_flag(void) +{ + US_TICKER_INSTANCE->GTST = R_GPT0_GTST_TCFA_Msk; + R_BSP_IrqClearPending(US_TICKER_IRQ); +} + +void us_ticker_init(void) +{ + if (us_ticker_inited) { + return; + } + + us_ticker_gpt_init(); + + us_ticker_gpt_disable_irq(); + us_ticker_gpt_clear_irq_flag(); + + us_ticker_inited = 1; +} + +uint32_t (us_ticker_read)() +{ + /* Invoke the macro */ + return us_ticker_read(); +} + +void us_ticker_fire_interrupt(void) +{ + us_ticker_gpt_clear_irq_flag(); + R_BSP_IrqEnable(US_TICKER_IRQ); + us_ticker_irq_handler(); +} + +void us_ticker_disable_interrupt(void) +{ + us_ticker_gpt_disable_irq(); +} + +void us_ticker_clear_interrupt(void) +{ + us_ticker_gpt_clear_irq_flag(); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + if (!us_ticker_inited) { + us_ticker_init(); + } + + uint32_t now = us_ticker_read(); + uint32_t delta = (uint32_t)(timestamp - now); + + if (delta <= 1) { + us_ticker_irq_handler(); + return; + } + + us_ticker_gpt_set_compare(timestamp); + + R_BSP_IrqEnable(US_TICKER_IRQ); +} + +void us_ticker_free(void) +{ + if (!us_ticker_inited) { + return; + } + + us_ticker_gpt_disable_irq(); + + US_TICKER_VAR.p_api->stop(US_TICKER_VAR.p_ctrl); + + us_ticker_inited = 0; +} + +void usticker_compare_match_callback(timer_callback_args_t * p_args) +{ + if(p_args->event == TIMER_EVENT_CAPTURE_A || p_args->event == TIMER_EVENT_CYCLE_END) + { + us_ticker_gpt_clear_irq_flag(); + us_ticker_irq_handler(); + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RA/us_ticker_defines.h b/targets/TARGET_RENESAS/TARGET_RA/us_ticker_defines.h new file mode 100644 index 0000000000..31eb94efc0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/us_ticker_defines.h @@ -0,0 +1,33 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_US_TICKER_DEFINES_H_ +#define MBED_US_TICKER_DEFINES_H_ + +#include "us_ticker_data.h" + +#if US_TICKER_CLOCK_BITS == 16 +#define US_TICKER_MASK 0xFFFF +#elif US_TICKER_CLOCK_BITS == 32 +#define US_TICKER_MASK 0xFFFFFFFF +#else +#error "Bad US_TICKER_CLOCK_BITS" +#endif + +/* Macro-optimised form of us_ticker_read */ +#define us_ticker_read() (US_TICKER_INSTANCE->GTCNT) + +#endif /* MBED_US_TICKER_DEFINES_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RA/watchdog_api.c b/targets/TARGET_RENESAS/TARGET_RA/watchdog_api.c new file mode 100644 index 0000000000..93b54b15b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RA/watchdog_api.c @@ -0,0 +1,162 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + */ +#include "watchdog_api.h" +#include "hal_data.h" +#include "mbed_error.h" + +extern const wdt_instance_t g_wdt0; + +static uint32_t s_timeout_ms = 0; +static uint32_t s_effective_timeout_ms = 0; + +static const wdt_timeout_t s_timeouts[] = { + WDT_TIMEOUT_1024, + WDT_TIMEOUT_4096, + WDT_TIMEOUT_8192, + WDT_TIMEOUT_16384, +}; + +static const uint32_t s_timeout_cycles[] = { + 1024u, + 4096u, + 8192u, + 16384u, +}; + +static const wdt_clock_division_t s_divs[] = { + WDT_CLOCK_DIVISION_4, + WDT_CLOCK_DIVISION_64, + WDT_CLOCK_DIVISION_128, + WDT_CLOCK_DIVISION_256, + WDT_CLOCK_DIVISION_512, + WDT_CLOCK_DIVISION_2048, + WDT_CLOCK_DIVISION_8192, +}; + +static const uint32_t s_div_values[] = { + 4u, + 64u, + 128u, + 256u, + 512u, + 2048u, + 8192u, +}; + +static bool pick_wdt_params(uint32_t requested_ms, + wdt_timeout_t *p_timeout, + wdt_clock_division_t *p_div, + uint32_t *p_effective_ms) +{ + const uint32_t pclkb = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + + if ((pclkb == 0U) || (requested_ms == 0U)) { + return false; + } + + bool found = false; + uint64_t best_cycles = UINT64_MAX; + size_t best_i = 0; + size_t best_j = 0; + + for (size_t i = 0; i < sizeof(s_timeouts) / sizeof(s_timeouts[0]); i++) { + for (size_t j = 0; j < sizeof(s_divs) / sizeof(s_divs[0]); j++) { + const uint64_t cycles = (uint64_t)s_timeout_cycles[i] * (uint64_t)s_div_values[j]; + if ((cycles * 1000ULL) >= ((uint64_t)requested_ms * (uint64_t)pclkb) && + (cycles * 1000ULL) <= ((uint64_t)requested_ms * (uint64_t)pclkb * 2ULL)) { + if ((!found) || (cycles < best_cycles)) { + found = true; + best_cycles = cycles; + best_i = i; + best_j = j; + } + } + } + } + + if (!found) { + return false; + } + + uint32_t effective_ms = + (uint32_t)((best_cycles * 1000ULL) / (uint64_t)pclkb); + + if (effective_ms == 0U) { + effective_ms = 1U; + } + + *p_timeout = s_timeouts[best_i]; + *p_div = s_divs[best_j]; + *p_effective_ms = effective_ms; + + return true; +} + +watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) +{ + if ((config == NULL) || (config->timeout_ms == 0U)) { + return WATCHDOG_STATUS_NOT_SUPPORTED; + } + + wdt_timeout_t timeout_sel; + wdt_clock_division_t div_sel; + uint32_t effective_ms = 0; + + if (!pick_wdt_params(config->timeout_ms, &timeout_sel, &div_sel, &effective_ms)) { + return WATCHDOG_STATUS_NOT_SUPPORTED; + } + + s_timeout_ms = config->timeout_ms; + s_effective_timeout_ms = effective_ms; + + wdt_cfg_t cfg = *g_wdt0.p_cfg; + + cfg.timeout = timeout_sel; + cfg.clock_division = div_sel; + + fsp_err_t err = g_wdt0.p_api->open(g_wdt0.p_ctrl, &cfg); + if (FSP_SUCCESS != err) { + return WATCHDOG_STATUS_NOT_SUPPORTED; + } + + err = g_wdt0.p_api->refresh(g_wdt0.p_ctrl); + if (FSP_SUCCESS != err) { + return WATCHDOG_STATUS_NOT_SUPPORTED; + } + + return WATCHDOG_STATUS_OK; +} + +watchdog_status_t hal_watchdog_stop(void) +{ + return WATCHDOG_STATUS_NOT_SUPPORTED; +} + +void hal_watchdog_kick(void) +{ + fsp_err_t err = g_wdt0.p_api->refresh(g_wdt0.p_ctrl); + if (FSP_SUCCESS != err) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_WATCHDOG, MBED_ERROR_FAILED_OPERATION), + "WDT refresh failed"); + } +} + +uint32_t hal_watchdog_get_reload_value(void) +{ + return s_effective_timeout_ms; +} + +watchdog_features_t hal_watchdog_get_platform_features(void) +{ + watchdog_features_t features; + const uint32_t pclkb = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); + uint64_t max_cycles = 16384ULL * 8192ULL; + features.max_timeout = (uint32_t)((max_cycles * 1000ULL) / (uint64_t)pclkb); + features.update_config = false; + features.disable_watchdog = false; + features.clock_typical_frequency = 24000; + features.clock_max_frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) / 4; + return features; +} diff --git a/targets/TARGET_STM/TARGET_STM32F7/linker_scripts/STM32F7_COMMON.ld b/targets/TARGET_STM/TARGET_STM32F7/linker_scripts/STM32F7_COMMON.ld index d6bf2e8936..5591cc73ad 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/linker_scripts/STM32F7_COMMON.ld +++ b/targets/TARGET_STM/TARGET_STM32F7/linker_scripts/STM32F7_COMMON.ld @@ -70,6 +70,25 @@ ENTRY(Reset_Handler) SECTIONS { + /* Non-cached data section. + * This section is configured in the MPU as uncached, so reads and writes go directly through to memory. + * We put this first in SRAM so it's very, very aligned. */ + .noncached (NOLOAD): + { + __noncached_start = .; + *(.noncached) + + /* For the MPU configuration, we need to align the size of this section up to + * the next power of two. Also note that the MPU does not support regions + * smaller than 32 bytes so round up if smaller than that. */ + __noncached_data_size = (. - __noncached_start); + __noncached_aligned_size = MAX(32, 1 << LOG2CEIL(__noncached_data_size)); + + . += (__noncached_aligned_size - __noncached_data_size); + + __noncached_end = .; + } > RAM + .text : { __vector_flash_start__ = ABSOLUTE(.); diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/STM32H743_H72x.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/STM32H743_H72x.ld index 2ffdfe63ee..fed8756cf1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/STM32H743_H72x.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/STM32H743_H72x.ld @@ -71,6 +71,25 @@ ENTRY(Reset_Handler) SECTIONS { + /* Non-cached data section. + * This section is configured in the MPU as uncached, so reads and writes go directly through to memory. + * We put this first in SRAM so it's very, very aligned. */ + .noncached (NOLOAD): + { + __noncached_start = .; + *(.noncached) + + /* For the MPU configuration, we need to align the size of this section up to + * the next power of two. Also note that the MPU does not support regions + * smaller than 32 bytes so round up if smaller than that. */ + __noncached_data_size = (. - __noncached_start); + __noncached_aligned_size = MAX(32, 1 << LOG2CEIL(__noncached_data_size)); + + . += (__noncached_aligned_size - __noncached_data_size); + + __noncached_end = .; + } > SRAM + .text : { KEEP(*(.isr_vector)) diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld index dadb368cb4..40313cf314 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld @@ -71,6 +71,25 @@ ENTRY(Reset_Handler) SECTIONS { + /* Non-cached data section. + * This section is configured in the MPU as uncached, so reads and writes go directly through to memory. + * We put this first in SRAM so it's very, very aligned. */ + .noncached (NOLOAD): + { + __noncached_start = .; + *(.noncached) + + /* For the MPU configuration, we need to align the size of this section up to + * the next power of two. Also note that the MPU does not support regions + * smaller than 32 bytes so round up if smaller than that. */ + __noncached_data_size = (. - __noncached_start); + __noncached_aligned_size = MAX(32, 1 << LOG2CEIL(__noncached_data_size)); + + . += (__noncached_aligned_size - __noncached_data_size); + + __noncached_end = .; + } > SRAM + .text : { KEEP(*(.isr_vector)) diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/STM32H7Ax.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/STM32H7Ax.ld index ad85f598bf..710455aa46 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/STM32H7Ax.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/STM32H7Ax.ld @@ -71,6 +71,25 @@ ENTRY(Reset_Handler) SECTIONS { + /* Non-cached data section. + * This section is configured in the MPU as uncached, so reads and writes go directly through to memory. + * We put this first in SRAM so it's very, very aligned. */ + .noncached (NOLOAD): + { + __noncached_start = .; + *(.noncached) + + /* For the MPU configuration, we need to align the size of this section up to + * the next power of two. Also note that the MPU does not support regions + * smaller than 32 bytes so round up if smaller than that. */ + __noncached_data_size = (. - __noncached_start); + __noncached_aligned_size = MAX(32, 1 << LOG2CEIL(__noncached_data_size)); + + . += (__noncached_aligned_size - __noncached_data_size); + + __noncached_end = .; + } > SRAM + .text : { KEEP(*(.isr_vector)) diff --git a/targets/cmsis_mcu_descriptions.json5 b/targets/cmsis_mcu_descriptions.json5 index 12f69c66f4..3cd516379b 100644 --- a/targets/cmsis_mcu_descriptions.json5 +++ b/targets/cmsis_mcu_descriptions.json5 @@ -14853,5 +14853,446 @@ } }, "vendor": "RPi:170" + }, + "R7FA4E10D": { + "algorithms": [ + { + "default": true, + "file_name": "Flash/RA4E1_512K.FLM", + "ram_size": 30720, + "ram_start": 536870912, + "size": 524288, + "start": 0, + "style": "Keil" + }, + { + "default": true, + "file_name": "Flash/RA4E1_DATA_C512K.FLM", + "ram_size": 30720, + "ram_start": 536870912, + "size": 8192, + "start": 134217728, + "style": "Keil" + }, + { + "default": true, + "file_name": "Flash/RA4E1_CONF.FLM", + "ram_size": 30720, + "ram_start": 536870912, + "size": 512, + "start": 16818432, + "style": "Keil" + } + ], + "family": "RA4E1 Series", + "from_pack": { + "pack": "RA_DFP", + "url": "https://www2.renesas.eu/Keil_MDK_Packs/", + "vendor": "Renesas", + "version": "5.7.0" + }, + "memories": { + "ConfigROM": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "p_name": null, + "size": 512, + "start": 16818432, + "startup": false + }, + "DataFlash": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "p_name": null, + "size": 8192, + "start": 134217728, + "startup": false + }, + "Flash": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "p_name": null, + "size": 524288, + "start": 0, + "startup": true + }, + "SRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "p_name": null, + "size": 131072, + "start": 536870912, + "startup": false + } + }, + "name": "R7FA4E10D", + "processors": [ + { + "address": null, + "ap": 0, + "apid": null, + "core": "CortexM33", + "default_reset_sequence": null, + "dp": 0, + "fpu": "SinglePrecision", + "mpu": "Present", + "name": null, + "svd": null, + "unit": 0 + } + ], + "sub_family": "RA4E1_512K", + "vendor": "Renesas:117" + }, + "R7FA8E1AF": { + "algorithms": [ + { + "default": true, + "file_name": "Flash/RA8E1_1M.FLM", + "ram_size": 30720, + "ram_start": 570818560, + "size": 1048576, + "start": 33554432, + "style": "Keil" + }, + { + "default": true, + "file_name": "Flash/RA8E1_DATA_C1M.FLM", + "ram_size": 30720, + "ram_start": 570818560, + "size": 12288, + "start": 654311424, + "style": "Keil" + }, + { + "default": true, + "file_name": "Flash/RA8E1_CCONF.FLM", + "ram_size": 30720, + "ram_start": 570818560, + "size": 512, + "start": 50372864, + "style": "Keil" + }, + { + "default": true, + "file_name": "Flash/RA8E1_DCONF.FLM", + "ram_size": 30720, + "ram_start": 570818560, + "size": 712, + "start": 654508184, + "style": "Keil" + } + ], + "family": "RA8E1 Series", + "from_pack": { + "pack": "RA_DFP", + "url": "https://www2.renesas.eu/Keil_MDK_Packs/", + "vendor": "Renesas", + "version": "6.3.0" + }, + "memories": { + "ConfigROM": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "p_name": null, + "size": 256, + "start": 50372864, + "startup": false + }, + "ConfigROM_S": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "p_name": null, + "size": 256, + "start": 50373120, + "startup": false + }, + "DTCM": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "p_name": null, + "size": 16384, + "start": 536870912, + "startup": false + }, + "DataFlash": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "p_name": null, + "size": 12288, + "start": 654311424, + "startup": false + }, + "DataFlash_Config": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "p_name": null, + "size": 736, + "start": 654508160, + "startup": false + }, + "Flash": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "p_name": null, + "size": 1048576, + "start": 33554432, + "startup": true + }, + "ITCM": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "p_name": null, + "size": 16384, + "start": 0, + "startup": false + }, + "SRAM": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "p_name": null, + "size": 524288, + "start": 570818560, + "startup": false + } + }, + "name": "R7FA8E1AF", + "processors": [ + { + "address": null, + "ap": { + "Index": 0 + }, + "core": "CortexM85", + "default_reset_sequence": null, + "dp": 0, + "fpu": "DoublePrecision", + "mpu": "Present", + "name": null, + "svd": "SVD/R7FA8E1AF.svd", + "unit": 0 + } + ], + "sub_family": "RA8E1_1M", + "vendor": "Renesas:117" + }, + "R7FA6E2BB": { + "algorithms": [ + { + "default": true, + "file_name": "Flash/RA6E2_256K.FLM", + "ram_size": 30720, + "ram_start": 536870912, + "size": 262144, + "start": 0, + "style": "Keil" + }, + { + "default": true, + "file_name": "Flash/RA6E2_DATA_C256K.FLM", + "ram_size": 30720, + "ram_start": 536870912, + "size": 4096, + "start": 134217728, + "style": "Keil" + }, + { + "default": true, + "file_name": "Flash/RA6E2_CONF.FLM", + "ram_size": 30720, + "ram_start": 536870912, + "size": 512, + "start": 16818432, + "style": "Keil" + } + ], + "family": "RA6E2 Series", + "from_pack": { + "pack": "RA_DFP", + "url": "https://www2.renesas.eu/Keil_MDK_Packs/", + "vendor": "Renesas", + "version": "6.3.0" + }, + "memories": { + "ConfigROM": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "p_name": null, + "size": 512, + "start": 16818432, + "startup": false + }, + "DataFlash": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "p_name": null, + "size": 4096, + "start": 134217728, + "startup": false + }, + "Flash": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "p_name": null, + "size": 262144, + "start": 0, + "startup": true + }, + "SRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "p_name": null, + "size": 40960, + "start": 536870912, + "startup": false + } + }, + "name": "R7FA6E2BB", + "processors": [ + { + "address": null, + "ap": { + "Index": 0 + }, + "core": "CortexM33", + "default_reset_sequence": null, + "dp": 0, + "fpu": "SinglePrecision", + "mpu": "Present", + "name": null, + "svd": "SVD/R7FA6E2BB.svd", + "unit": 0 + } + ], + "sub_family": "RA6E2_256K", + "vendor": "Renesas:117" } } diff --git a/targets/targets.json5 b/targets/targets.json5 index c08f6b628f..6cd8fcc5dd 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -1988,7 +1988,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "device_name": "STM32F756ZGTx", "overrides": { "network-default-interface-type": "ETHERNET", - + // ADC reference voltage is same as MCU VDD. "default-adc-vref": 3.3 }, @@ -2027,7 +2027,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "device_name": "STM32F767ZITx", "overrides": { "network-default-interface-type": "ETHERNET", - + // ADC reference voltage is same as MCU VDD. "default-adc-vref": 3.3 }, @@ -5065,6 +5065,39 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "USTICKER" ], "device_name": "MIMXRT1176DVMAA", + + memory_banks: { + // EVK board has W25Q512NWEIQ flash mounted + "EXT_FLASH": { + "access": { + "execute": true, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 0x4000000, // 64MiB (though NXP product page says 16MiB...) + "start": 0x30000000, + "startup": true + }, + + // EVK board has 2x W9825G6KH-5I mounted in parallel on SEMC0 + "SDRAM": { + "access": { + "execute": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 0x4000000, // 64MiB + "start": 0x80000000, + "startup": false + } + }, + "image_url": "https://www.nxp.com/assets/images/en/dev-board-image/MIMXRT1170-EVKB-TOP-IMG.jpg" }, @@ -8597,5 +8630,146 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", } }, "image_url": "https://www.olimex.com/Products/RaspberryPi/PICO/PICO2-XXL/images/thumbs/310x230/PICO2-XXL1w.jpg" + }, + // Renesas RA Targets ------------------------------------------------------------------------------------------ + "MCU_RA": { + "inherits": [ + "Target" + ], + "public": false, + "extra_labels": [ + "RENESAS", + "RA" + ], + "config": { + "lse-available": { + "help": "Define if a Low Speed External xtal (LSE) is available on the board (0 = No, 1 = Yes). If Yes, the LSE will be used to clock the RTC, LPUART, ... otherwise the Low Speed Internal clock (LOCO) will be used", + "value": "1" + }, + "rtc-clock-source": { + "help": "Define the RTC clock source. RTC_CLOCK_SOURCE_SUBCLK, RTC_CLOCK_SOURCE_LOCO, RTC_CLOCK_SOURCE_MAINCLK.", + "value": "RTC_CLOCK_SOURCE_SUBCLK" + }, + }, + "overrides": { + "deep-sleep-latency": 4, + "init-us-ticker-at-boot": true, + "console-uart": false, + "console-rtt": true + }, + "device_has": [ + "MPU", + "USTICKER", + //"LPTICKER", + "RTC", + "CRC", + "TRNG", + "ANALOGIN", + "ANALOGOUT", + "I2C", + //"I2CSLAVE", + //"I2C_ASYNCH", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + //"SERIAL_FC", + //"SLEEP", + "SPI", + //"SPISLAVE", + //"SPI_ASYNCH", + "FLASH", + //"USBDEVICE", + //"EMAC", + //"QSPI", + //"OSPI", + "WATCHDOG", + "RESET_REASON" + ], + "OUTPUT_EXT": "hex" + }, + "MCU_RA4E1": { + "inherits": [ + "MCU_RA" + ], + "public": false, + "core": "Cortex-M33", + "device_has_add": [ + "CAN" + ], + "extra_labels_add": [ + "RA4E1" + ] + }, + "FPB_RA4E1": { + "inherits": [ + "MCU_RA4E1" + ], + "public": true, + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "overrides": { + "lse-available": 0, + "rtc-clock-source": "RTC_CLOCK_SOURCE_LOCO" + }, + "device_name": "R7FA4E10D", + "image_url": "https://www.renesas.com/sites/default/files/styles/product_features_large/public/fpb-ra4e1-pcb.png" + }, + "MCU_RA6E2": { + "inherits": [ + "MCU_RA" + ], + "public": false, + "core": "Cortex-M33", + "device_has_add": [ + "CAN", + "CAN_FD" + ], + "extra_labels_add": [ + "RA6E2" + ] + }, + "FPB_RA6E2": { + "inherits": [ + "MCU_RA6E2" + ], + "public": true, + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "device_name": "R7FA6E2BB", + "image_url": "https://www.renesas.com/sites/default/files/styles/product_features_large/public/fpb-ra6e2-fast-prototyping-board.jpg" + }, + "MCU_RA8E1": { + "inherits": [ + "MCU_RA" + ], + "public": false, + "core": "Cortex-M85FE", + "device_has_add": [ + "CAN", + "CAN_FD" + ], + "extra_labels_add": [ + "RA8E1" + ] + }, + "FPB_RA8E1": { + "inherits": [ + "MCU_RA8E1" + ], + "public": true, + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "device_name": "R7FA8E1AF", + "image_url": "https://www.renesas.com/sites/default/files/styles/product_features_large/public/fpb-ra8e1-top.jpg", + "overrides": { + "console-uart": true, + "console-rtt": false + }, } } diff --git a/targets/upload_method_cfg/FPB_RA4E1.cmake b/targets/upload_method_cfg/FPB_RA4E1.cmake new file mode 100644 index 0000000000..28d39e1daa --- /dev/null +++ b/targets/upload_method_cfg/FPB_RA4E1.cmake @@ -0,0 +1,27 @@ +# Mbed OS upload method configuration file for target FPB_RA4E1 +# To change any of these parameters from their default values, set them in your build script between where you +# include app.cmake and where you add mbed os as a subdirectory. + +# General config parameters +# ------------------------------------------------------------- +set(UPLOAD_METHOD_DEFAULT PYOCD) + +# Config options for MBED +# ------------------------------------------------------------- + +set(MBED_UPLOAD_ENABLED FALSE) + +# Config options for PYOCD +# ------------------------------------------------------------- + +set(PYOCD_UPLOAD_ENABLED TRUE) +set(PYOCD_TARGET_NAME R7FA4E10D) +set(PYOCD_CLOCK_SPEED 4000k) + +# Config options for JLINK +# ------------------------------------------------------------- + +set(JLINK_UPLOAD_ENABLED TRUE) +set(JLINK_CPU_NAME R7FA4E10D) +set(JLINK_CLOCK_SPEED 4000) +set(JLINK_UPLOAD_INTERFACE SWD) diff --git a/targets/upload_method_cfg/FPB_RA6E2.cmake b/targets/upload_method_cfg/FPB_RA6E2.cmake new file mode 100644 index 0000000000..22e730e6a5 --- /dev/null +++ b/targets/upload_method_cfg/FPB_RA6E2.cmake @@ -0,0 +1,27 @@ +# Mbed OS upload method configuration file for target FPB_RA6E2 +# To change any of these parameters from their default values, set them in your build script between where you +# include app.cmake and where you add mbed os as a subdirectory. + +# General config parameters +# ------------------------------------------------------------- +set(UPLOAD_METHOD_DEFAULT PYOCD) + +# Config options for MBED +# ------------------------------------------------------------- + +set(MBED_UPLOAD_ENABLED FALSE) + +# Config options for PYOCD +# ------------------------------------------------------------- + +set(PYOCD_UPLOAD_ENABLED TRUE) +set(PYOCD_TARGET_NAME R7FA6E2BB) +set(PYOCD_CLOCK_SPEED 4000k) + +# Config options for JLINK +# ------------------------------------------------------------- + +set(JLINK_UPLOAD_ENABLED TRUE) +set(JLINK_CPU_NAME R7FA6E2BB) +set(JLINK_CLOCK_SPEED 4000) +set(JLINK_UPLOAD_INTERFACE SWD) diff --git a/targets/upload_method_cfg/FPB_RA8E1.cmake b/targets/upload_method_cfg/FPB_RA8E1.cmake new file mode 100644 index 0000000000..814f772871 --- /dev/null +++ b/targets/upload_method_cfg/FPB_RA8E1.cmake @@ -0,0 +1,27 @@ +# Mbed OS upload method configuration file for target FPB_RA8E1 +# To change any of these parameters from their default values, set them in your build script between where you +# include app.cmake and where you add mbed os as a subdirectory. + +# General config parameters +# ------------------------------------------------------------- +set(UPLOAD_METHOD_DEFAULT PYOCD) + +# Config options for MBED +# ------------------------------------------------------------- + +set(MBED_UPLOAD_ENABLED FALSE) + +# Config options for PYOCD +# ------------------------------------------------------------- + +set(PYOCD_UPLOAD_ENABLED TRUE) +set(PYOCD_TARGET_NAME R7FA8E1AF) +set(PYOCD_CLOCK_SPEED 4000k) + +# Config options for JLINK +# ------------------------------------------------------------- + +set(JLINK_UPLOAD_ENABLED TRUE) +set(JLINK_CPU_NAME R7FA8E1AF) +set(JLINK_CLOCK_SPEED 4000) +set(JLINK_UPLOAD_INTERFACE SWD) diff --git a/tools/cmake/UploadMethodManager.cmake b/tools/cmake/UploadMethodManager.cmake index 6b1a0b368b..998a221d02 100644 --- a/tools/cmake/UploadMethodManager.cmake +++ b/tools/cmake/UploadMethodManager.cmake @@ -99,16 +99,33 @@ if("MBED_CONF_TARGET_CONSOLE_RTT=1" IN_LIST MBED_CONFIG_DEFINITIONS) # on the device memory layout. So, we need to give them some more help. # The alternative would be to put the RTT CB at a fixed address, but that would likely require # specific configuration for each target, so it's probably a non-starter. - string(REGEX MATCH "MBED_RAM_RANGE_START=([^;]+)" RTT_RAM_RANGE_MATCH "${MBED_CONFIG_DEFINITIONS}") - # Handle old build configs that didn't provide this definition - if("${RTT_RAM_RANGE_MATCH}" STREQUAL "") - message(FATAL_ERROR "Memory bank information not available for this target, cannot configure RTT support. This may be caused by an old build directory -- try deleting and recreating it if you made it with an older version of Mbed.") + # Try to get start from JSON option, but fall back to start of all RAM banks + mbed_get_json_option_value("rtt.cb-search-range-start" MBED_RTT_RAM_RANGE_START) + if(NOT DEFINED MBED_RTT_RAM_RANGE_START) + mbed_get_config_definition_value(MBED_RAM_RANGE_START MBED_RTT_RAM_RANGE_START) + + # Handle old build configs that didn't provide this definition + if("${MBED_RTT_RAM_RANGE_START}" STREQUAL "") + message(FATAL_ERROR "Memory bank information not available for this target, cannot configure RTT support. This may be caused by an old build directory -- try deleting and recreating it if you made it with an older version of Mbed.") + endif() + endif() + + # Also get end + mbed_get_json_option_value("rtt.cb-search-range-end" MBED_RTT_RAM_RANGE_END) + if(NOT DEFINED MBED_RTT_RAM_RANGE_END) + mbed_get_config_definition_value(MBED_RAM_RANGE_END MBED_RTT_RAM_RANGE_END) + endif() + + # For cleanliness, convert everything to hex + math(EXPR MBED_RTT_RAM_RANGE_START "${MBED_RTT_RAM_RANGE_START}" OUTPUT_FORMAT HEXADECIMAL) + math(EXPR MBED_RTT_RAM_RANGE_END "${MBED_RTT_RAM_RANGE_END}" OUTPUT_FORMAT HEXADECIMAL) + + if(MBED_RTT_RAM_RANGE_END LESS MBED_RTT_RAM_RANGE_START) + message(FATAL_ERROR "RTT search range end (${MBED_RTT_RAM_RANGE_END}) cannot be less than search range start (${MBED_RTT_RAM_RANGE_START})!") endif() - set(MBED_RTT_RAM_RANGE_START ${CMAKE_MATCH_1}) - string(REGEX MATCH "MBED_RAM_RANGE_END=([^;]+)" _ "${MBED_CONFIG_DEFINITIONS}") - set(MBED_RTT_RAM_RANGE_END ${CMAKE_MATCH_1}) + # Compute size math(EXPR MBED_RTT_RAM_RANGE_SIZE "${MBED_RTT_RAM_RANGE_END} - ${MBED_RTT_RAM_RANGE_START} + 1" OUTPUT_FORMAT HEXADECIMAL) endif() diff --git a/tools/cmake/cores/Cortex-M85.cmake b/tools/cmake/cores/Cortex-M85.cmake new file mode 100644 index 0000000000..f209349b7a --- /dev/null +++ b/tools/cmake/cores/Cortex-M85.cmake @@ -0,0 +1,28 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# Sets cpu core options +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + list(APPEND common_options + "-mthumb" + "-mfpu=fpv5-sp-d16" + "-mfloat-abi=hard" + "-mcpu=cortex-m85" + ) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + list(APPEND common_options + "-mfpu=fpv5-sp-d16" + "-mfloat-abi=hard" + "-mcpu=cortex-m85" + ) +endif() + + +function(mbed_set_cpu_core_definitions target) + target_compile_definitions(${target} + INTERFACE + __CORTEX_M85 + __FPU_PRESENT=1U + __CMSIS_RTOS + ) +endfunction() diff --git a/tools/cmake/cores/Cortex-M85FE.cmake b/tools/cmake/cores/Cortex-M85FE.cmake new file mode 100644 index 0000000000..c95706cd23 --- /dev/null +++ b/tools/cmake/cores/Cortex-M85FE.cmake @@ -0,0 +1,27 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# Sets cpu core options +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + list(APPEND common_options + "-mthumb" + "-mfpu=fpv5-sp-d16" + "-mfloat-abi=hard" + "-mcpu=cortex-m85" + ) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + list(APPEND common_options + "-mfpu=fpv5-sp-d16" + "-mfloat-abi=hard" + "-mcpu=cortex-m85+dsp" + ) +endif() + +function(mbed_set_cpu_core_definitions target) + target_compile_definitions(${target} + INTERFACE + __CORTEX_M85 + ARM_MATH_ARMV8_1MML + __CMSIS_RTOS + ) +endfunction() diff --git a/tools/cmake/mbed_generate_configuration.cmake b/tools/cmake/mbed_generate_configuration.cmake index 221adf0868..94ef487008 100644 --- a/tools/cmake/mbed_generate_configuration.cmake +++ b/tools/cmake/mbed_generate_configuration.cmake @@ -155,4 +155,30 @@ endif() include(${CMAKE_CURRENT_BINARY_DIR}/mbed_config.cmake) # Make it so that if any config JSON files are modified, CMake is rerun. -set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${MBED_CONFIG_JSON_SOURCE_FILES}) \ No newline at end of file +set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${MBED_CONFIG_JSON_SOURCE_FILES}) + +# Helper function to get config definition values. +# Sets RESULT_VARIABLE to the value of DEF_NAME. +# Does not set RESULT_VARIABLE if the setting is not in MBED_CONFIG_DEFINITIONS. +function(mbed_get_config_definition_value DEF_NAME RESULT_VARIABLE) + if(MBED_CONFIG_DEFINITIONS MATCHES "${DEF_NAME}=([^;]+)") + set(${RESULT_VARIABLE} ${CMAKE_MATCH_1} PARENT_SCOPE) + endif() +endfunction(mbed_get_config_definition_value) + +# Helper function to getthe value of a JSON option +# Sets RESULT_VARIABLE to the value of the option described by OPT_NAME. +# Does not set RESULT_VARIABLE if the setting is not in MBED_CONFIG_DEFINITIONS. +function(mbed_get_json_option_value OPT_NAME RESULT_VARIABLE) + # Transform the JSON option name into the CMake option name. + # This mirrors the logic in mbed_config.tmpl. + string(TOUPPER ${OPT_NAME} OPT_NAME_UCASE) + string(REPLACE "-" "_" OPT_NAME_CMAKE ${OPT_NAME_UCASE}) + string(REPLACE "." "_" OPT_NAME_CMAKE ${OPT_NAME_CMAKE}) + set(OPT_NAME_CMAKE MBED_CONF_${OPT_NAME_CMAKE}) + + mbed_get_config_definition_value(${OPT_NAME_CMAKE} ${RESULT_VARIABLE}) + if(DEFINED ${RESULT_VARIABLE}) + set(${RESULT_VARIABLE} "${${RESULT_VARIABLE}}" PARENT_SCOPE) + endif() +endfunction(mbed_get_json_option_value) \ No newline at end of file diff --git a/tools/python/mbed_tools/targets/_internal/data/targets_metadata.json b/tools/python/mbed_tools/targets/_internal/data/targets_metadata.json index ee96f63245..882c2c8cf7 100644 --- a/tools/python/mbed_tools/targets/_internal/data/targets_metadata.json +++ b/tools/python/mbed_tools/targets/_internal/data/targets_metadata.json @@ -161,6 +161,45 @@ "CORTEX_M", "LIKE_CORTEX_M55", "CORTEX" + ], + "Cortex-M85": [ + "M85", + "CORTEX_M", + "LIKE_CORTEX_M85", + "CORTEX" + ], + "Cortex-M85-NS": [ + "M85", + "M85_NS", + "CORTEX_M", + "LIKE_CORTEX_M85", + "CORTEX" + ], + "Cortex-M85F": [ + "M85", + "CORTEX_M", + "LIKE_CORTEX_M85", + "CORTEX" + ], + "Cortex-M85F-NS": [ + "M85", + "M85_NS", + "CORTEX_M", + "LIKE_CORTEX_M85", + "CORTEX" + ], + "Cortex-M85FE": [ + "M85", + "CORTEX_M", + "LIKE_CORTEX_M85", + "CORTEX" + ], + "Cortex-M85FE-NS": [ + "M85", + "M85_NS", + "CORTEX_M", + "LIKE_CORTEX_M85", + "CORTEX" ] } }